diff --git a/sources/rtk-be550/src/hal/phy/Kconfig b/sources/rtk-be550/src/hal/phy/Kconfig new file mode 100755 index 00000000..2be2ebc8 --- /dev/null +++ b/sources/rtk-be550/src/hal/phy/Kconfig @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Copyright (c) 2023 Realtek Semiconductor Corp. All rights reserved. +# + +config RTK_MSSDK_PHY + tristate "Realtek MSSDK PHYs" + help + Currently supports the RTL8261N,RTL8264B PHYs. + diff --git a/sources/rtk-be550/src/hal/phy/Makefile b/sources/rtk-be550/src/hal/phy/Makefile new file mode 100755 index 00000000..f199c3cf --- /dev/null +++ b/sources/rtk-be550/src/hal/phy/Makefile @@ -0,0 +1,25 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Copyright (c) 2023 Realtek Semiconductor Corp. All rights reserved. +# + +ccflags-y := -DRTK_PHYDRV_IN_LINUX +ccflags-y += -DDEBUG + +obj-$(CONFIG_RTK_MSSDK_PHY) += rtk-ms-phy.o + +rtk-ms-phy-objs := rtk_phy.o +rtk-ms-phy-objs += rtk_osal.o + +# files from SDK +rtk-ms-phy-objs += phy_patch.o +rtk-ms-phy-objs += phy_rtl826xb_patch.o + +# rtk phylib +rtk-ms-phy-objs += rtk_phylib.o +rtk-ms-phy-objs += rtk_phylib_rtl826xb.o + +ifdef CONFIG_MACSEC +rtk-ms-phy-objs += rtk_macsec.o +rtk-ms-phy-objs += rtk_phylib_macsec.o +endif diff --git a/sources/rtk-be550/src/hal/phy/construct/conf_rtl8261n_c.c b/sources/rtk-be550/src/hal/phy/construct/conf_rtl8261n_c.c new file mode 100755 index 00000000..7348214e --- /dev/null +++ b/sources/rtk-be550/src/hal/phy/construct/conf_rtl8261n_c.c @@ -0,0 +1,2144 @@ +/* + * SPDX-License-Identifier: GPL-2.0-only + * + * Copyright (c) 2024 Realtek Semiconductor Corp. All rights reserved. + */ +//Date: Tue Mar 5 12:47:27 2024 + +rtk_hwpatch_t rtl8261n_c_top_conf[17] = { + {RTK_PATCH_OP_TOP , 0xf , 2 , 20 , 15, 0 , 0x5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 2 , 21 , 15, 0 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 2 , 22 , 15, 0 , 0x280 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 2 , 23 , 15, 0 , 0x0014, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 3 , 16 , 15, 0 , 0x0300, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 3 , 17 , 15, 0 , 0x01ff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 3 , 18 , 15, 0 , 0x000c, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 3 , 19 , 15, 0 , 0x01ff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 3 , 20 , 15, 0 , 0x0200, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 3 , 21 , 15, 0 , 0x0015, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 3 , 22 , 15, 0 , 0x0200, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 3 , 23 , 15, 0 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 4 , 16 , 15, 0 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 13 , 23 , 8 , 5 , 0x6 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 90 , 18 , 15, 0 , 0x14 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 90 , 19 , 15, 0 , 0x14 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 90 , 20 , 15, 8 , 0x01 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, +}; + +rtk_hwpatch_t rtl8261n_c_sds_conf[103] = { + {RTK_PATCH_OP_TOP , 0xf , 24 , 18 , 15, 0 , 0x881F, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 24 , 19 , 15, 0 , 0x003F, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 24 , 20 , 15, 0 , 0x003F, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 24 , 21 , 15, 0 , 0x003F, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 24 , 22 , 15, 0 , 0x001F, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x06 , 0x0D , 15, 0 , 0x0F00, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x06 , 0x0E , 15, 0 , 0x3F5A, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x07 , 0x10 , 15, 12, 0x8 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x07 , 0x10 , 7 , 0 , 0x3 , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x06 , 0x1D , 15, 0 , 0x0600, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x21 , 0x00 , 15, 0 , 0x4902, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x21 , 0x08 , 15, 0 , 0x0FC0, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x21 , 0x09 , 15, 0 , 0x33F0, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x21 , 0x0C , 15, 0 , 0x08BF, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x21 , 0x12 , 15, 0 , 0x8000, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x36 , 0x07 , 15, 0 , 0x04C0, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x36 , 0x08 , 15, 0 , 0x2000, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2E , 0x0B , 15, 0 , 0x2390, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2E , 0x0C , 15, 0 , 0xAA17, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2E , 0x0D , 15, 0 , 0xFE40, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2E , 0x0E , 15, 0 , 0x12F4, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2E , 0x11 , 15, 0 , 0xF2AD, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2E , 0x15 , 15, 0 , 0x7A41, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2E , 0x16 , 15, 0 , 0x0041, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2F , 0x00 , 15, 0 , 0x1F00, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2F , 0x01 , 15, 0 , 0x2800, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2F , 0x02 , 15, 0 , 0x0FC8, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2F , 0x11 , 15, 0 , 0x3000, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2F , 0x13 , 15, 0 , 0xF400, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2F , 0x1E , 15, 0 , 0x0500, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x34 , 0x0B , 15, 0 , 0x2390, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x34 , 0x0C , 15, 0 , 0xA517, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x34 , 0x0D , 15, 0 , 0xFE41, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x34 , 0x0E , 15, 0 , 0x12F4, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x34 , 0x11 , 15, 0 , 0xF2AD, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x34 , 0x15 , 15, 0 , 0x7A41, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x34 , 0x16 , 15, 0 , 0x0041, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x35 , 0x00 , 15, 0 , 0x1F80, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x35 , 0x01 , 15, 0 , 0x0800, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x35 , 0x02 , 15, 0 , 0x0FC8, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x35 , 0x11 , 15, 0 , 0x3001, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x35 , 0x13 , 15, 0 , 0xF400, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x35 , 0x1E , 15, 0 , 0x0100, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2C , 0x0B , 15, 0 , 0x2390, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2C , 0x0C , 15, 0 , 0xA517, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2C , 0x0D , 15, 0 , 0xFE41, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2C , 0x0E , 15, 0 , 0x12F4, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2C , 0x11 , 15, 0 , 0xF2AD, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2C , 0x15 , 15, 0 , 0x7A61, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2C , 0x16 , 15, 0 , 0x0041, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2D , 0x00 , 15, 0 , 0x1F80, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2D , 0x01 , 15, 0 , 0x0800, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2D , 0x02 , 15, 0 , 0x0FC8, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2D , 0x11 , 15, 0 , 0x3001, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2D , 0x13 , 15, 0 , 0xF400, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2D , 0x1E , 15, 0 , 0x0100, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x28 , 0x0B , 15, 0 , 0x2390, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x28 , 0x0C , 15, 0 , 0xA514, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x28 , 0x0D , 15, 0 , 0xFE43, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x28 , 0x0E , 15, 0 , 0x12F4, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x28 , 0x11 , 15, 0 , 0xF2AD, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x28 , 0x15 , 15, 0 , 0x7A61, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x28 , 0x16 , 15, 0 , 0x0041, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x29 , 0x00 , 15, 0 , 0x1F80, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x29 , 0x01 , 15, 0 , 0x0800, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x29 , 0x02 , 15, 0 , 0x0FC8, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x29 , 0x11 , 15, 0 , 0x3001, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x29 , 0x13 , 15, 0 , 0xF400, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x29 , 0x1E , 15, 0 , 0x0100, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x26 , 0x0B , 15, 0 , 0x2390, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x26 , 0x0C , 15, 0 , 0xA514, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x26 , 0x0D , 15, 0 , 0xFE43, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x26 , 0x0E , 15, 0 , 0x12F4, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x26 , 0x11 , 15, 0 , 0xF2AD, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x26 , 0x15 , 15, 0 , 0x7A41, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x26 , 0x16 , 15, 0 , 0x0041, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x27 , 0x00 , 15, 0 , 0x1F80, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x27 , 0x01 , 15, 0 , 0x0800, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x27 , 0x02 , 15, 0 , 0x0FC8, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x27 , 0x11 , 15, 0 , 0x3001, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x27 , 0x13 , 15, 0 , 0xF400, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x27 , 0x1E , 15, 0 , 0x0100, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x24 , 0x0B , 15, 0 , 0x2390, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x24 , 0x0C , 15, 0 , 0xA514, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x24 , 0x0D , 15, 0 , 0xFE43, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x24 , 0x0E , 15, 0 , 0x12F4, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x24 , 0x11 , 15, 0 , 0xF2AD, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x24 , 0x15 , 15, 0 , 0x7A41, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x24 , 0x16 , 15, 0 , 0x0041, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x25 , 0x00 , 15, 0 , 0x1F80, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x25 , 0x01 , 15, 0 , 0x0800, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x25 , 0x02 , 15, 0 , 0x0FC8, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x25 , 0x11 , 15, 0 , 0x3001, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x25 , 0x13 , 15, 0 , 0xF400, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x25 , 0x1E , 15, 0 , 0x0100, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 24 , 18 , 15, 0 , 0x880D, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 24 , 19 , 15, 0 , 0x0024, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 24 , 20 , 15, 0 , 0x0036, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 24 , 21 , 15, 0 , 0x0035, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 24 , 22 , 15, 0 , 0x001A, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x1F , 0x00 , 15, 0 , 0x001B, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x1F , 0x00 , 15, 0 , 0x0000, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 90 , 20 , 7 , 0 , 0x01 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, +}; + +rtk_hwpatch_t rtl8261n_c_afe_conf[2] = { + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbf1a, 3 , 2 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 90 , 21 , 15, 8 , 0x01 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, +}; + +rtk_hwpatch_t rtl8261n_c_uc_conf[10] = { + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb820, 7 , 7 , 0x0 , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbd8a, 5 , 3 , 0x3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbd8c, 6 , 4 , 0x5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8060, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 12, 10, 0x3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8061, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 13, 0x5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa466, 1 , 1 , 0x1 , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8491, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x3D , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, +}; + +rtk_hwpatch_t rtl8261n_c_uc2_conf[402] = { + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb820, 7 , 7 , 0x1 , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb87c, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8af6, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb87e, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xaf8b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8af6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0eaf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8af8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8b41, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8afa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xaf8b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8afc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4faf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8afe}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8b5b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b00}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xaf8b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b02}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xb4af, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b04}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8bc0, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b06}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xaf8b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b08}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xdaaf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b0a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8c2d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b0c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf8ef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b0e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x49f8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b10}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf70, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b12}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3f02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b14}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6772, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b16}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xad28, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b18}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13e1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b1a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8a55, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b1c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xad28, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b1e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0502, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b20}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5ee2, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b22}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xae0e, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b24}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x025d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b26}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8f02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b28}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8d1e, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b2a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xae06, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b2c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x025d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b2e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x7002, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b30}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8d66, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b32}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe087, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b34}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1ef6, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b36}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x27e4, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b38}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x871e, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b3a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xfcef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b3c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x94fc, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b3e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x04a1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b40}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0103, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b42}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x028d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b44}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x42e0, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b46}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8a09, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b48}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xef23, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b4a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xaf5e, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b4c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5bac, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b4e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5003, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b50}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xaf62, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b52}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8a02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b54}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8d66, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b56}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xaf62, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b58}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xb0bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b5a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x68e0, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b5c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0267, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b5e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x72ef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b60}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x31bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b62}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x68dd, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b64}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0267, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b66}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x721e, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b68}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x31ac, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b6a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3819, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b6c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf68, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b6e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe902, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b70}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6772, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b72}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xef31, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b74}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf68, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b76}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe602, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b78}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6772, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b7a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1e31, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b7c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xac38, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b7e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0cee, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b80}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8933, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b82}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x02ae, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b84}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0aee, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b86}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8933, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b88}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x00ae, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b8a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x04ee, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b8c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8933, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b8e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x01bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b90}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8ff9, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b92}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe189, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b94}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x331a, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b96}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x91db, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b98}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf69, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b9a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4c02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b9c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6772, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b9e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1f00, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ba0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1f22, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ba2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1b45, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ba4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xad27, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ba6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x05e1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ba8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x870d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8baa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xae03, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bac}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe187, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bae}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0eaf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bb0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2d1a, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bb2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0248, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bb4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf702, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bb6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8d8a, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bb8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0222, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bba}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4faf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bbc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4176, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bbe}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf8d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bc0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd402, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bc2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x70eb, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bc4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf8d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bc6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe302, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bc8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x70eb, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bca}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf8d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bcc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe902, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bce}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x70eb, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bd0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd300, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bd2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0241, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bd4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x7caf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bd6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x46b2, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bd8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf69, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bda}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x7f02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bdc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6772, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bde}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe58f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8be0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf8d0, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8be2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x00d1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8be4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x00bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8be6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x697f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8be8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0267, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bea}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x53bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bec}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6f0a, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bee}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0270, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bf0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xebbf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bf2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6f0a, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bf4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0270, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bf6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf4d6, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bf8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bfa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bfc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0d02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bfe}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x70f4, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c00}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c02}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0d02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c04}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x70eb, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c06}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa600, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c08}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x7f07, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c0a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd001, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c0c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe489, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c0e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xfeae, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c10}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0cbf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c12}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6f52, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c14}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0267, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c16}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x72ad, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c18}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2803, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c1a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x16ae, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c1c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xddd0, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c1e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x00e1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c20}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8ff8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c22}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf69, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c24}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x7f02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c26}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6753, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c28}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xaf53, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c2a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa2ef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c2c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x56ef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c2e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x67cf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c30}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2f00, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c32}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x02ef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c34}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x97d8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c36}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x19d9, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c38}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xef74, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c3a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0271, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c3c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf5bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c3e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8948, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c40}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xef47, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c42}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xdc19, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c44}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xddef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c46}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x7502, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c48}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x71f5, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c4a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xef67, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c4c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe189, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c4e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33ad, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c50}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x280a, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c52}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xad4f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c54}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x05d6, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c56}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c58}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xae02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c5a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c61, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c5c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbdd8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c5e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x19d9, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c60}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xef74, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c62}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0271, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c64}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf5bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c66}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x894a, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c68}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xef47, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c6a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xdc19, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c6c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xddcf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c6e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2f00, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c70}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x06ef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c72}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x97d8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c74}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x19d9, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c76}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xef74, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c78}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe189, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c7a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c7c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0050, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c7e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf89, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c80}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x46d8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c82}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x19d9, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c84}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xef64, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c86}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0d63, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c88}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0d77, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c8a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1b67, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c8c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf89, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c8e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x48d8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c90}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x19d9, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c92}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xef74, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c94}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1b67, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c96}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf89, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c98}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4ad8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c9a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x19d9, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c9c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xef74, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c9e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xad5f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ca0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x05d7, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ca2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ca4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xae02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ca6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c71, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ca8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1a76, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8caa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xee87, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cac}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd500, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cae}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe186, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cb0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xc0e5, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cb2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x892a, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cb4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe186, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cb6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbde5, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cb8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x892b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cba}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xad5f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cbc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x03af, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cbe}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x32a5, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cc0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xef67, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cc2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3e00, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cc4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf6ac, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cc6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4f03, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cc8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cca}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf5af, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ccc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x32a8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cce}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe189, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cd0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cd2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0145, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cd4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf89, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cd6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x46d8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cd8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x19d9, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cda}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xef64, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cdc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0d62, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cde}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0d75, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ce0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1b67, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ce2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf89, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ce4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x48d8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ce6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x19d9, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ce8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1b64, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cea}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xef76, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cec}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf89, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cee}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4ad8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cf0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x19d9, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cf2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0d41, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cf4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1a74, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cf6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0d72, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cf8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xee87, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cfa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd519, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cfc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe186, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cfe}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xc1e5, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d00}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x892a, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d02}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe186, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d04}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbee5, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d06}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x892b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d08}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xac5f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d0a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xb2ef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d0c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x673e, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d0e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x00e2, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d10}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xac4f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d12}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xb8d7, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d14}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x00e1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d16}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xaf32, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d18}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa8af, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d1a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3263, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d1c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf8ef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d1e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x49f8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d20}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d22}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3a02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d24}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6772, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d26}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xac28, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d28}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x12bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d2a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6d63, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d2c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0267, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d2e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x72e5, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d30}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8ffc, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d32}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d34}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6f02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d36}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6772, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d38}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe58f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d3a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xfdfc, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d3c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xef94, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d3e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xfc04, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d40}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf8ef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d42}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x49f8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d44}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d46}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3a02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d48}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6772, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d4a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xac28, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d4c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x12e1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d4e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8ffe, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d50}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d52}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6302, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d54}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6753, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d56}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe18f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d58}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffbf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d5a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6d6f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d5c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0267, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d5e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x53fc, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d60}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xef94, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d62}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xfc04, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d64}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf8ef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d66}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x49f8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d68}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d6a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3a02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d6c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6772, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d6e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xac28, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d70}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x12e1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d72}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8ffc, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d74}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d76}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6302, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d78}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6753, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d7a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe18f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d7c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xfdbf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d7e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6d6f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d80}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0267, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d82}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x53fc, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d84}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xef94, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d86}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xfc04, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d88}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf8fa, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d8a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xef69, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d8c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d8e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3a02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d90}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6772, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d92}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xad28, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d94}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0ebf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d96}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8dd7, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d98}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0270, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d9a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf4bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d9c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8dd4, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d9e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0270, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8da0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf4ae, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8da2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2ad1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8da4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0fbf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8da6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8dda, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8da8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0267, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8daa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x53bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dac}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8ddd, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dae}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0270, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8db0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xebd1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8db2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x00bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8db4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8de0, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8db6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0267, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8db8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x53bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dba}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8de3, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dbc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0270, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dbe}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf4d1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dc0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x00bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dc2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8de6, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dc4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0267, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dc6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x53bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dc8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8de9, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dca}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0270, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dcc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf4ef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dce}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x96fe, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dd0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xfc04, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dd2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x77bd, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dd4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6c66, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dd6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbd6c, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dd8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x30bd, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dda}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5444, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ddc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbd54, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dde}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x85bd, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8de0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5e55, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8de2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbd54, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8de4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa7bd, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8de6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5cbb, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8de8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbd5c, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dea}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb85e, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x62ba, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb860, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5e56, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb862, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6287, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb864, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2d07, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb886, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4170, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb888, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x46ad, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb88a, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5370, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb88c, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x316e, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb838, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x00ff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb820, 7 , 7 , 0x0 , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, +}; + +rtk_hwpatch_t rtl8261n_c_nctl0_conf[80] = { + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb820, 7 , 7 , 0x1 , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA016, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA012, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA014, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8010, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x801a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8023, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8035, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8035, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8035, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8035, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8035, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd719, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3bb7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8014, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd704, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x406e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x12db, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1301, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2a69, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8020, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9f01, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0d45, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf01, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0d43, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xc6bf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1da6, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd708, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2630, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1b58, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x7f63, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2c72, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x802d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8024, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1da6, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd708, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x30}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2630, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x31}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1b58, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x32}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2318, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x33}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1b55, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x34}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x35}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x802d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x36}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA026, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA024, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA022, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA020, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA006, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA004, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1b4c, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA002, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0d42, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA000, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x12d7, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA008, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0300, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb820, 7 , 7 , 0x0 , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, +}; + +rtk_hwpatch_t rtl8261n_c_nctl1_conf[72] = { + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb820, 7 , 7 , 0x1 , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA016, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0010, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA012, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA014, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8010, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x801f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x802f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x802f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x802f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x802f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x802f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x802f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x38c1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8019, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd73e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6122, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0241, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x801d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd501, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce01, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa50f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd500, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x02e7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x38c1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8029, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd73e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6142, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0288, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8a0f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x802d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd501, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce01, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa50f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd500, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x00d3, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA08E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA08C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA08A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA088, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA086, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA084, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA082, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x00ce, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA080, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x02e3, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA090, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0003, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb820, 7 , 7 , 0x0 , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, +}; + +rtk_hwpatch_t rtl8261n_c_nctl2_conf[878] = { + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb820, 7 , 7 , 0x1 , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA016, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0020, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA012, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA014, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8010, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8029, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8217, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x82d0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x82f9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8322, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8336, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8336, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcb0a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0cc7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4127, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c0f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b05, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c38, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0d28, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf008, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c0f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b0a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c38, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0d18, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0f73, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8034, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8031, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1bf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd06d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x30}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1dd, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x31}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd06d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x32}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x33}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x34}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd06e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x35}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x36}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x37}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x38}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5fba, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x39}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd05a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x60cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x60f1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6113, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6135, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x40}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6157, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x41}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x42}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x43}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x44}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x45}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf008, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x46}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x47}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x48}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x49}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf004, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf002, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x142d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x50}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x51}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0ccf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x52}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b40, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x53}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c3f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x54}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c24, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x55}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x56}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa340, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x57}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x58}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x147c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x59}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa110, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1435, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8110, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1485, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa304, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x60}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa8c0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x61}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8810, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x62}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x63}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x64}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa310, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x65}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0cfc, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x66}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0224, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x67}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0ca0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x68}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0480, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x69}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa340, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd162, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x70}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x71}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x72}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5fba, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x73}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8840, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x74}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1c4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x75}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd045, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x76}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x77}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x78}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x79}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5fba, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6127, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f3b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x88c0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x800a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x80}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x81}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8350, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x82}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x84a0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x83}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffb6, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x84}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xb920, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x85}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcd33, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x86}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x87}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x88}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x89}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x7fb4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9920, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6065, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f94, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x90}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffee, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x91}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xb820, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x92}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x93}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x94}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x95}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x7fa5, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x96}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9820, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x97}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x800a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x98}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x99}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x147c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa108, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1435, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8108, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1485, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa2fc, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa304, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8880, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0cc0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0440, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcd34, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0cc0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xaa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b80, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xab}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xac3f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xac}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c38, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xad}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0d08, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xae}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xaf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa810, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa480, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa604, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x80bb, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xba}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd19f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xbb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xbc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xbd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xbe}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xbf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x63f4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f7a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4368, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0cc0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b40, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8c3f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8d38, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xca}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xcb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xcc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xcd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x80d7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xce}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xcf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x80d4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1f4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1b7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1c6, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xda}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xdb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6074, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xdc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xdd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f7a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xde}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xdf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4056, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf004, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x61fc, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xfff9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xea}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4070, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xeb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xec}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x81a4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xed}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xee}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xef}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xae80, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x81a4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd05a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x60cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x60f1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6113, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6135, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xfa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6157, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xfb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xfc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xfd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xfe}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xff}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf008, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x100}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x101}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x102}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x103}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf004, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x104}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x105}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf002, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x106}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x107}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x108}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x142d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x109}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0ccf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b40, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c3f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c24, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x110}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa340, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x111}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x112}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x147c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x113}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa110, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x114}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x115}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1435, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x116}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8110, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x117}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x118}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1485, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x119}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa304, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa8c0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8810, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa310, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0cfc, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x120}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0224, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x121}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0ca0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x122}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0480, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x123}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8604, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x124}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcd35, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x125}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd162, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x126}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x127}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x128}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x129}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5fba, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8840, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1c4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd045, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x130}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x131}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5fba, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x132}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x133}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6127, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x134}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x135}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f3b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x136}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x88c0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x137}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x800a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x138}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x139}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8350, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x84a0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffb8, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbb80, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x140}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5fb4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x141}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xb920, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x142}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcd36, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x143}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x144}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x145}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x146}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x7fb4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x147}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9920, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x148}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9b80, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x149}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6065, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f94, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffe8, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xb820, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x150}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x151}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x152}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x153}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x7fa5, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x154}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9820, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x155}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x800a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x156}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x157}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x158}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x147c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x159}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa108, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1435, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8108, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1485, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa2fc, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x160}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa304, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x161}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8880, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x162}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0cc0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x163}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0440, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x164}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcd37, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x165}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x166}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x167}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0cc0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x168}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b80, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x169}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xac3f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c38, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0d08, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa810, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x170}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa480, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x171}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa604, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x172}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x173}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x174}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x817e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x175}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x176}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x817b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x177}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x178}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x179}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x180}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x181}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x182}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1463, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x183}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x184}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f7a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x185}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x186}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f28, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x187}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x188}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x189}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0cc0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b40, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8c3f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8d38, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x190}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x819a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x191}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x192}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8197, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x193}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x194}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x195}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x196}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x197}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x198}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x199}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd189, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1463, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f7a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f28, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c0f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b05, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x60cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1aa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x60f1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ab}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6113, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ac}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6135, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ad}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6157, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ae}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1af}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce08, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce08, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf008, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce08, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce08, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf004, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce08, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf002, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce08, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ba}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1bb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x142d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1bc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa180, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1bd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcd38, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1be}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1bf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x81d4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x81cc, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf013, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd100, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ca}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf010, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1cb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1cc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1cd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1b7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ce}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1cf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd100, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf008, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1da}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd13b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1db}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd055, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1dc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1dd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1de}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1df}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1463, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f7b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa302, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1463, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f7a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ea}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f28, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1eb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ec}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ed}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c3f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ee}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c12, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ef}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8206, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x81fe, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf013, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1fa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd100, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1fb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1fc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf010, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1fd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1fe}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ff}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x200}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x201}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x202}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd100, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x203}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd040, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x204}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf008, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x205}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x206}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x207}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x208}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x209}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd16b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1463, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x210}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x211}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f7a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x212}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x213}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f2a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x214}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x215}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x087a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x216}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x217}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x646d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x218}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x219}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8231, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8227, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x40c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x220}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd100, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x221}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x222}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf01a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x223}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x224}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x225}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf017, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x226}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x227}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x40c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x228}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x229}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd100, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf010, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x230}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x231}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x40c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x232}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x233}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x234}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x235}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x236}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x237}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x238}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x239}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1463, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x240}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x241}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f7a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x242}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x243}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f29, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x244}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x245}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x60cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x246}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x60f1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x247}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6113, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x248}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6135, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x249}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6157, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf008, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x250}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x251}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x252}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf004, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x253}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x254}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf002, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x255}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x256}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x257}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x142d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x258}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x259}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8bc0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c3f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c09, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa310, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x260}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa420, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x261}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcd3b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x262}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x263}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x65ad, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x264}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x43c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x265}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x266}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x267}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x827b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x268}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x269}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8273, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf024, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd15d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x270}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x271}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf021, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x272}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x273}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x274}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1c6, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x275}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x276}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf01c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x277}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd15d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x278}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x279}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf019, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf014, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x280}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x281}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf011, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x282}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x283}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x284}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x828e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x285}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x286}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x828b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x287}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1e5, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x288}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x289}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf009, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd191, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x290}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd16b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x291}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x292}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x293}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x294}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x295}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1463, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x296}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x297}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f7a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x298}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x299}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f2c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x40e7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c0f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b05, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c0f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b0a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcd3c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x644d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2aa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x43c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ab}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ac}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ad}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x82c1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ae}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2af}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x82b9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf019, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf016, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ba}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2bb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2bc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf011, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2bd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd13e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2be}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2bf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf009, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ca}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2cb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2cc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2cd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ce}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0956, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2cf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2969, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x82f5, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x82eb, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x82e1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x40c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2da}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd15c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2db}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2dc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf01a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2dd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2de}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2df}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf017, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x40c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd13e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf010, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ea}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2eb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x40c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ec}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ed}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ee}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ef}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x09a0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2969, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2fa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x831e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2fb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2fc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8314, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2fd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2fe}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x830a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ff}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x300}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x40c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x301}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x302}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x303}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd15d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x304}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x305}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf01a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x306}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x307}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x308}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf017, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x309}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x30a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x40c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x30b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x30c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x30d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd16b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x30e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x30f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf010, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x310}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x311}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x312}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x313}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x314}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x40c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x315}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x316}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x317}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x318}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x319}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x31a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x31b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x31c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x31d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1b7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x31e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x31f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x320}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0a39, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x321}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x322}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2969, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x323}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8332, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x324}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x325}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x832f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x326}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x327}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x832c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x328}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd18a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x329}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x32a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf009, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x32b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x32c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x32d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x32e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1c6, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x32f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x330}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x331}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1b7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x332}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x333}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x334}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0506, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x335}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA10E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA10C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA10A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x04f4, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA108, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0a12, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA106, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0979, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA104, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x089f, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA102, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0692, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA100, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0f60, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA110, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x003f, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA016, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0020, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA012, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1ff8, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA014, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b0e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ff8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b0e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ff9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b0e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ffa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ffb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ffc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ffd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ffe}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1fff}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA164, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0baa, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA166, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c19, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA168, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1293, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA16A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3fff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA16C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3fff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA16E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3fff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA170, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3fff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA172, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3fff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA162, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0007, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb820, 7 , 7 , 0x0 , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, +}; + +rtk_hwpatch_t rtl8261n_c_algxg_conf[184] = { + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8165, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x22 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8167, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x33 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x827E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x68 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8013, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x39 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8ffb, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x14 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8ff9, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x1e , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x82D9, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x20 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x82DA, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x816E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0xab , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8159, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x58 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x815A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x99 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8139, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x25 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8125, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x67 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8126, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x89 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x827D, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x4c , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8205, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x4d , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8FFA, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x78 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8159, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x58 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x815A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x99 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x815B, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x77 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x815C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0xfb , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8125, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x67 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8126, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x89 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8127, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x77 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8128, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0xf7 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x80DF, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x51 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x80E0, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x94 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x80F1, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x99 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x80F2, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x97 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x80F4, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0xF9 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x80F7, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x99 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x80F8, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x9A , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x80FA, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x39 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x817B, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x40 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x817C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0xCC , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8149, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x28 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x814A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0xE3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x816D, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0xAA , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x80F3, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x75 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x80F9, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x73 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x869D, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0xD , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8695, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x39 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x868D, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x869E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x61 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8696, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x66 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x868E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0xF3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x869F, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x15 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8697, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x3E , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x868F, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0xE , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x86A0, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x89 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8698, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x95 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8690, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0xC1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x86A1, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x35 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8699, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x64 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8691, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x32 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x86A2, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0xDC , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x869A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x59 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8692, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0xC8 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x86A3, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x1E , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x869B, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x2F , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8693, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x13 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x86A4, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x5A , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x869C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0xC , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8694, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x7D , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x86B5, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x9 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x86AD, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x21 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x86A5, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x4 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x86B6, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x9 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x86AE, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x6D , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x86A6, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x88 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x86B7, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x12 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x86AF, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x2D , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x86A7, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0xC , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x86B8, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x59 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x86B0, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x72 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x86A8, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x41 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x86B9, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x34 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x86B1, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x57 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x86A9, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x30 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x86BA, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0xA2 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x86B2, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0xBD , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x86AA, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x48 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x86BB, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x22 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x86B3, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x2F , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x86AB, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x22 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x86BC, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x10 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x86B4, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x82 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x86AC, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0xF5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x820A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x61 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x820B, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x97 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x820C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x7C , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x820D, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0xB2 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, +}; + +rtk_hwpatch_t rtl8261n_c_alg_giga_conf[5] = { + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa836, 15, 15, 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa85c, 7 , 7 , 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa85c, 6 , 3 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8367, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x5d , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, +}; + +rtk_hwpatch_t rtl8261n_c_normal_conf[21] = { + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x817d, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x07 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb516, 6 , 0 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8ffe, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x04 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8fff, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x05 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8132, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x77 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8134, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x88 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x80ca, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x77 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x80cc, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x88 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8062, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x77 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8064, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x88 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x801E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0014, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, +}; + +rtk_hwpatch_t rtl8261n_c_dataram_conf[148] = { + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb820, 7 , 7 , 0x0 , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb896, 0 , 0 , 0x0 , RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb892, 15, 8 , 0x0 , RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC10B, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xD5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC10C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xD5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC10D, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xD5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC10E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xD5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC10F, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xD5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC110, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xD5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC149, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x08 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC14A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x08 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC14B, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x08 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC14C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x08 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC14D, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x08 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC14E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x08 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC166, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xEE , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC167, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xEE , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC168, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x07 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC169, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x09 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC16A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x0B , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC16B, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x0D , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC16C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x13 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC16D, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x0E , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC16E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x11 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC16F, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x14 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC170, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x17 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC171, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x15 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC172, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x10 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC173, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x0B , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC128, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xF7 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC129, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xF7 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC12A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xF8 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC12B, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xF7 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC12C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xF6 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC12D, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xF5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC12E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xF2 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC12F, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xF7 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC130, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xF5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC131, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xF2 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC132, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xF0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC133, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xF1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC134, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xF4 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC135, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xF7 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC118, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xEC , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC119, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xEB , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC11A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xEB , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC11B, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xE8 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC11C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xE8 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC11D, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xEA , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC11E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xE9 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC11F, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xE7 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC120, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xE6 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC121, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xE7 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC122, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xE6 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC123, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xEA , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC124, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xEB , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC125, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xED , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC126, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xE3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC127, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xE0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC156, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x19 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC157, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x1B , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC158, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x1B , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC159, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x1F , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC15A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x1E , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC15B, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x1C , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC15C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x1D , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC15D, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x20 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC15E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x22 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC15F, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x21 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC160, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x25 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC161, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x20 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC162, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x21 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC163, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x27 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC164, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x57 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC165, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x74 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb896, 0 , 0 , 0x1 , RTK_PATCH_CMP_W , 0, 0, 0, 0}, +}; + +rtk_hwpatch_t rtl8261n_c_rtct_conf[176] = { + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa468, 1 , 0 , 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa422, 0 , 0 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xc010, 9 , 9 , 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xc010, 10, 10, 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xc010, 14, 13, 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xc000, 0 , 0 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_DELAY_MS, 0 , 0 , 0 , 0 , 0 , 1000 , RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8260, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x25 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8270, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x8 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8271, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x1D , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8280, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x1E , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8281, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xA0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8278, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x02 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8279, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8274, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x01 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8275, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x01 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8276, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8277, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x827C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x3A , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x827D, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xE0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x827E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x827F, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x25 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x827A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x03 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x827B, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xC0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8263, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x34 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8264, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xBC , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8261, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x32 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8262, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8265, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8273, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xE4 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8266, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x45 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8267, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xE0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8282, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8283, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x08 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8284, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8285, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x1D , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8286, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xFF , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8287, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xFA , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8288, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8289, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x03 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x828A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x05 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x828B, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xE7 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x828C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xFF , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x828D, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x5F , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x828E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x828F, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x3E , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8290, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xFF , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8291, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xF4 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8292, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x06 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8293, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xF5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8294, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xFF , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8295, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x12 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8296, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8297, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x59 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8298, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xFF , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8299, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xF2 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x829A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xF8 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x829B, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xEA , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x829C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x829D, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x35 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x829E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xFF , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x829F, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xBE , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82A0, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82A1, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x36 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82A2, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xFA , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82A3, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x30 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82A4, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82A5, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x35 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82A6, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xFF , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82A7, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xBE , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82A8, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82A9, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x36 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82AA, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x06 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82AB, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x10 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82AC, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xFF , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82AD, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x98 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82AE, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82AF, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x10 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82B0, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82B1, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x06 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82B2, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x02 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82B3, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x60 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82B4, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82B5, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82B6, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82B7, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82B8, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82B9, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x826D, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x2B , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x826E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x03 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa422, 1 , 1 , 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa422, 7 , 4 , 0xf , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 90 , 21 , 7 , 0 , 0x4 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, +}; + diff --git a/sources/rtk-be550/src/hal/phy/construct/conf_rtl8261n_c_lp.c b/sources/rtk-be550/src/hal/phy/construct/conf_rtl8261n_c_lp.c new file mode 100755 index 00000000..8053d4af --- /dev/null +++ b/sources/rtk-be550/src/hal/phy/construct/conf_rtl8261n_c_lp.c @@ -0,0 +1,2243 @@ +/* + * SPDX-License-Identifier: GPL-2.0-only + * + * Copyright (c) 2024 Realtek Semiconductor Corp. All rights reserved. + */ +//Date: Tue Mar 5 12:48:30 2024 + +rtk_hwpatch_t rtl8261n_c_top_conf[17] = { + {RTK_PATCH_OP_TOP , 0xf , 2 , 20 , 15, 0 , 0x5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 2 , 21 , 15, 0 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 2 , 22 , 15, 0 , 0x280 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 2 , 23 , 15, 0 , 0x0014, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 3 , 16 , 15, 0 , 0x0300, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 3 , 17 , 15, 0 , 0x01ff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 3 , 18 , 15, 0 , 0x000c, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 3 , 19 , 15, 0 , 0x01ff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 3 , 20 , 15, 0 , 0x0200, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 3 , 21 , 15, 0 , 0x0015, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 3 , 22 , 15, 0 , 0x0200, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 3 , 23 , 15, 0 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 4 , 16 , 15, 0 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 13 , 23 , 8 , 5 , 0x6 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 90 , 18 , 15, 0 , 0x14 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 90 , 19 , 15, 0 , 0x14 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 90 , 20 , 15, 8 , 0x01 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, +}; + +rtk_hwpatch_t rtl8261n_c_sds_conf[103] = { + {RTK_PATCH_OP_TOP , 0xf , 24 , 18 , 15, 0 , 0x881F, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 24 , 19 , 15, 0 , 0x003F, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 24 , 20 , 15, 0 , 0x003F, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 24 , 21 , 15, 0 , 0x003F, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 24 , 22 , 15, 0 , 0x001F, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x06 , 0x0D , 15, 0 , 0x0F00, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x06 , 0x0E , 15, 0 , 0x3F5A, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x07 , 0x10 , 15, 12, 0x8 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x07 , 0x10 , 7 , 0 , 0x3 , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x06 , 0x1D , 15, 0 , 0x0600, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x21 , 0x00 , 15, 0 , 0x4902, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x21 , 0x08 , 15, 0 , 0x0FC0, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x21 , 0x09 , 15, 0 , 0x33F0, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x21 , 0x0C , 15, 0 , 0x08BF, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x21 , 0x12 , 15, 0 , 0x8000, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x36 , 0x07 , 15, 0 , 0x04C0, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x36 , 0x08 , 15, 0 , 0x2000, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2E , 0x0B , 15, 0 , 0x2390, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2E , 0x0C , 15, 0 , 0xAA17, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2E , 0x0D , 15, 0 , 0xFE40, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2E , 0x0E , 15, 0 , 0x12F4, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2E , 0x11 , 15, 0 , 0xF2AD, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2E , 0x15 , 15, 0 , 0x7A41, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2E , 0x16 , 15, 0 , 0x0041, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2F , 0x00 , 15, 0 , 0x1F00, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2F , 0x01 , 15, 0 , 0x2800, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2F , 0x02 , 15, 0 , 0x0FC8, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2F , 0x11 , 15, 0 , 0x3000, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2F , 0x13 , 15, 0 , 0xF400, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2F , 0x1E , 15, 0 , 0x0500, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x34 , 0x0B , 15, 0 , 0x2390, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x34 , 0x0C , 15, 0 , 0xA517, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x34 , 0x0D , 15, 0 , 0xFE41, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x34 , 0x0E , 15, 0 , 0x12F4, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x34 , 0x11 , 15, 0 , 0xF2AD, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x34 , 0x15 , 15, 0 , 0x7A41, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x34 , 0x16 , 15, 0 , 0x0041, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x35 , 0x00 , 15, 0 , 0x1F80, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x35 , 0x01 , 15, 0 , 0x0800, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x35 , 0x02 , 15, 0 , 0x0FC8, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x35 , 0x11 , 15, 0 , 0x3001, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x35 , 0x13 , 15, 0 , 0xF400, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x35 , 0x1E , 15, 0 , 0x0100, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2C , 0x0B , 15, 0 , 0x2390, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2C , 0x0C , 15, 0 , 0xA517, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2C , 0x0D , 15, 0 , 0xFE41, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2C , 0x0E , 15, 0 , 0x12F4, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2C , 0x11 , 15, 0 , 0xF2AD, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2C , 0x15 , 15, 0 , 0x7A61, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2C , 0x16 , 15, 0 , 0x0041, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2D , 0x00 , 15, 0 , 0x1F80, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2D , 0x01 , 15, 0 , 0x0800, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2D , 0x02 , 15, 0 , 0x0FC8, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2D , 0x11 , 15, 0 , 0x3001, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2D , 0x13 , 15, 0 , 0xF400, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2D , 0x1E , 15, 0 , 0x0100, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x28 , 0x0B , 15, 0 , 0x2390, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x28 , 0x0C , 15, 0 , 0xA514, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x28 , 0x0D , 15, 0 , 0xFE43, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x28 , 0x0E , 15, 0 , 0x12F4, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x28 , 0x11 , 15, 0 , 0xF2AD, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x28 , 0x15 , 15, 0 , 0x7A61, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x28 , 0x16 , 15, 0 , 0x0041, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x29 , 0x00 , 15, 0 , 0x1F80, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x29 , 0x01 , 15, 0 , 0x0800, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x29 , 0x02 , 15, 0 , 0x0FC8, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x29 , 0x11 , 15, 0 , 0x3001, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x29 , 0x13 , 15, 0 , 0xF400, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x29 , 0x1E , 15, 0 , 0x0100, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x26 , 0x0B , 15, 0 , 0x2390, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x26 , 0x0C , 15, 0 , 0xA514, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x26 , 0x0D , 15, 0 , 0xFE43, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x26 , 0x0E , 15, 0 , 0x12F4, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x26 , 0x11 , 15, 0 , 0xF2AD, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x26 , 0x15 , 15, 0 , 0x7A41, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x26 , 0x16 , 15, 0 , 0x0041, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x27 , 0x00 , 15, 0 , 0x1F80, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x27 , 0x01 , 15, 0 , 0x0800, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x27 , 0x02 , 15, 0 , 0x0FC8, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x27 , 0x11 , 15, 0 , 0x3001, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x27 , 0x13 , 15, 0 , 0xF400, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x27 , 0x1E , 15, 0 , 0x0100, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x24 , 0x0B , 15, 0 , 0x2390, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x24 , 0x0C , 15, 0 , 0xA514, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x24 , 0x0D , 15, 0 , 0xFE43, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x24 , 0x0E , 15, 0 , 0x12F4, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x24 , 0x11 , 15, 0 , 0xF2AD, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x24 , 0x15 , 15, 0 , 0x7A41, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x24 , 0x16 , 15, 0 , 0x0041, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x25 , 0x00 , 15, 0 , 0x1F80, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x25 , 0x01 , 15, 0 , 0x0800, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x25 , 0x02 , 15, 0 , 0x0FC8, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x25 , 0x11 , 15, 0 , 0x3001, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x25 , 0x13 , 15, 0 , 0xF400, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x25 , 0x1E , 15, 0 , 0x0100, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 24 , 18 , 15, 0 , 0x880D, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 24 , 19 , 15, 0 , 0x0024, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 24 , 20 , 15, 0 , 0x0036, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 24 , 21 , 15, 0 , 0x0035, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 24 , 22 , 15, 0 , 0x001A, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x1F , 0x00 , 15, 0 , 0x001B, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x1F , 0x00 , 15, 0 , 0x0000, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 90 , 20 , 7 , 0 , 0x01 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, +}; + +rtk_hwpatch_t rtl8261n_c_afe_conf[31] = { + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbf1a, 3 , 2 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbfb0, 15, 13, 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbf9c, 15, 13, 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbfb0, 12, 10, 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbf9c, 12, 10, 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbfb0, 9 , 7 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbfb0, 6 , 4 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbfa0, 15, 13, 0x5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbf14, 15, 13, 0x5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbf14, 4 , 2 , 0x5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbfb0, 1 , 0 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbf9c, 9 , 8 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbf9c, 7 , 6 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbf14, 12, 10, 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbf14, 9 , 7 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbf12, 5 , 3 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbf10, 2 , 0 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbf14, 1 , 0 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbf14, 6 , 5 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbf8e, 3 , 3 , 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbfa8, 2 , 2 , 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbfa8, 3 , 3 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbf1c, 4 , 4 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8061, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 10, 8 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbc3c, 15, 0 , 0x100 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbf18, 15, 13, 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbf18, 12, 11, 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbd5c, 6 , 4 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbd80, 15, 0 , 0x280 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 90 , 21 , 15, 8 , 0x03 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, +}; + +rtk_hwpatch_t rtl8261n_c_uc_conf[10] = { + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb820, 7 , 7 , 0x0 , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbd8a, 5 , 3 , 0x3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbd8c, 6 , 4 , 0x5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8060, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 12, 10, 0x3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8061, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 13, 0x5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa466, 1 , 1 , 0x1 , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8491, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x3D , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, +}; + +rtk_hwpatch_t rtl8261n_c_uc2_conf[402] = { + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb820, 7 , 7 , 0x1 , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb87c, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8af6, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb87e, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xaf8b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8af6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0eaf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8af8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8b41, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8afa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xaf8b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8afc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4faf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8afe}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8b5b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b00}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xaf8b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b02}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xb4af, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b04}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8bc0, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b06}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xaf8b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b08}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xdaaf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b0a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8c2d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b0c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf8ef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b0e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x49f8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b10}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf70, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b12}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3f02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b14}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6772, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b16}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xad28, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b18}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13e1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b1a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8a55, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b1c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xad28, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b1e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0502, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b20}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5ee2, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b22}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xae0e, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b24}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x025d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b26}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8f02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b28}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8d1e, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b2a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xae06, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b2c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x025d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b2e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x7002, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b30}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8d66, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b32}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe087, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b34}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1ef6, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b36}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x27e4, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b38}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x871e, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b3a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xfcef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b3c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x94fc, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b3e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x04a1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b40}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0103, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b42}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x028d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b44}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x42e0, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b46}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8a09, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b48}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xef23, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b4a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xaf5e, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b4c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5bac, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b4e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5003, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b50}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xaf62, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b52}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8a02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b54}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8d66, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b56}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xaf62, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b58}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xb0bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b5a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x68e0, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b5c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0267, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b5e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x72ef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b60}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x31bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b62}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x68dd, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b64}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0267, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b66}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x721e, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b68}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x31ac, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b6a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3819, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b6c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf68, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b6e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe902, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b70}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6772, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b72}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xef31, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b74}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf68, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b76}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe602, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b78}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6772, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b7a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1e31, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b7c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xac38, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b7e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0cee, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b80}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8933, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b82}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x02ae, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b84}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0aee, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b86}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8933, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b88}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x00ae, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b8a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x04ee, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b8c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8933, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b8e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x01bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b90}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8ff9, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b92}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe189, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b94}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x331a, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b96}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x91db, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b98}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf69, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b9a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4c02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b9c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6772, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b9e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1f00, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ba0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1f22, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ba2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1b45, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ba4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xad27, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ba6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x05e1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ba8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x870d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8baa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xae03, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bac}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe187, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bae}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0eaf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bb0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2d1a, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bb2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0248, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bb4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf702, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bb6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8d8a, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bb8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0222, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bba}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4faf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bbc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4176, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bbe}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf8d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bc0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd402, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bc2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x70eb, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bc4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf8d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bc6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe302, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bc8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x70eb, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bca}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf8d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bcc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe902, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bce}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x70eb, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bd0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd300, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bd2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0241, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bd4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x7caf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bd6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x46b2, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bd8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf69, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bda}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x7f02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bdc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6772, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bde}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe58f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8be0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf8d0, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8be2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x00d1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8be4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x00bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8be6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x697f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8be8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0267, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bea}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x53bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bec}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6f0a, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bee}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0270, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bf0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xebbf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bf2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6f0a, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bf4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0270, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bf6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf4d6, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bf8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bfa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bfc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0d02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bfe}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x70f4, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c00}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c02}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0d02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c04}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x70eb, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c06}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa600, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c08}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x7f07, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c0a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd001, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c0c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe489, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c0e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xfeae, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c10}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0cbf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c12}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6f52, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c14}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0267, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c16}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x72ad, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c18}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2803, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c1a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x16ae, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c1c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xddd0, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c1e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x00e1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c20}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8ff8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c22}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf69, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c24}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x7f02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c26}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6753, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c28}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xaf53, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c2a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa2ef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c2c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x56ef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c2e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x67cf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c30}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2f00, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c32}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x02ef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c34}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x97d8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c36}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x19d9, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c38}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xef74, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c3a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0271, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c3c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf5bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c3e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8948, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c40}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xef47, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c42}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xdc19, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c44}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xddef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c46}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x7502, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c48}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x71f5, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c4a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xef67, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c4c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe189, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c4e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33ad, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c50}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x280a, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c52}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xad4f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c54}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x05d6, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c56}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c58}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xae02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c5a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c61, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c5c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbdd8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c5e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x19d9, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c60}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xef74, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c62}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0271, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c64}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf5bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c66}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x894a, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c68}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xef47, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c6a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xdc19, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c6c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xddcf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c6e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2f00, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c70}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x06ef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c72}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x97d8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c74}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x19d9, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c76}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xef74, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c78}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe189, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c7a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c7c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0050, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c7e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf89, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c80}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x46d8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c82}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x19d9, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c84}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xef64, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c86}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0d63, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c88}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0d77, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c8a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1b67, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c8c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf89, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c8e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x48d8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c90}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x19d9, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c92}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xef74, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c94}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1b67, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c96}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf89, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c98}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4ad8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c9a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x19d9, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c9c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xef74, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c9e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xad5f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ca0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x05d7, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ca2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ca4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xae02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ca6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c71, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ca8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1a76, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8caa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xee87, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cac}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd500, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cae}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe186, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cb0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xc0e5, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cb2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x892a, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cb4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe186, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cb6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbde5, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cb8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x892b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cba}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xad5f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cbc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x03af, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cbe}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x32a5, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cc0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xef67, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cc2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3e00, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cc4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf6ac, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cc6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4f03, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cc8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cca}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf5af, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ccc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x32a8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cce}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe189, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cd0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cd2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0145, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cd4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf89, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cd6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x46d8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cd8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x19d9, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cda}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xef64, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cdc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0d62, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cde}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0d75, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ce0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1b67, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ce2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf89, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ce4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x48d8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ce6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x19d9, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ce8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1b64, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cea}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xef76, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cec}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf89, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cee}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4ad8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cf0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x19d9, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cf2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0d41, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cf4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1a74, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cf6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0d72, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cf8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xee87, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cfa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd519, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cfc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe186, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cfe}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xc1e5, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d00}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x892a, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d02}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe186, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d04}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbee5, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d06}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x892b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d08}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xac5f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d0a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xb2ef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d0c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x673e, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d0e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x00e2, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d10}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xac4f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d12}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xb8d7, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d14}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x00e1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d16}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xaf32, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d18}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa8af, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d1a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3263, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d1c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf8ef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d1e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x49f8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d20}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d22}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3a02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d24}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6772, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d26}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xac28, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d28}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x12bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d2a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6d63, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d2c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0267, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d2e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x72e5, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d30}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8ffc, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d32}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d34}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6f02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d36}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6772, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d38}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe58f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d3a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xfdfc, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d3c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xef94, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d3e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xfc04, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d40}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf8ef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d42}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x49f8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d44}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d46}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3a02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d48}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6772, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d4a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xac28, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d4c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x12e1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d4e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8ffe, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d50}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d52}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6302, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d54}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6753, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d56}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe18f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d58}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffbf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d5a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6d6f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d5c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0267, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d5e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x53fc, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d60}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xef94, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d62}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xfc04, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d64}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf8ef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d66}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x49f8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d68}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d6a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3a02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d6c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6772, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d6e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xac28, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d70}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x12e1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d72}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8ffc, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d74}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d76}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6302, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d78}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6753, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d7a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe18f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d7c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xfdbf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d7e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6d6f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d80}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0267, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d82}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x53fc, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d84}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xef94, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d86}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xfc04, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d88}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf8fa, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d8a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xef69, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d8c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d8e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3a02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d90}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6772, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d92}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xad28, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d94}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0ebf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d96}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8dd7, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d98}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0270, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d9a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf4bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d9c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8dd4, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d9e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0270, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8da0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf4ae, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8da2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2ad1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8da4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0fbf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8da6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8dda, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8da8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0267, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8daa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x53bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dac}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8ddd, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dae}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0270, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8db0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xebd1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8db2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x00bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8db4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8de0, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8db6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0267, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8db8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x53bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dba}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8de3, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dbc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0270, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dbe}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf4d1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dc0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x00bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dc2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8de6, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dc4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0267, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dc6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x53bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dc8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8de9, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dca}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0270, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dcc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf4ef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dce}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x96fe, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dd0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xfc04, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dd2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x77bd, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dd4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6c66, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dd6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbd6c, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dd8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x30bd, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dda}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5444, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ddc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbd54, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dde}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x85bd, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8de0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5e55, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8de2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbd54, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8de4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa7bd, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8de6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5cbb, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8de8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbd5c, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dea}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb85e, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x62ba, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb860, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5e56, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb862, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6287, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb864, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2d07, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb886, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4170, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb888, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x46ad, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb88a, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5370, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb88c, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x316e, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb838, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x00ff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb820, 7 , 7 , 0x0 , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, +}; + +rtk_hwpatch_t rtl8261n_c_nctl0_conf[80] = { + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb820, 7 , 7 , 0x1 , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA016, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA012, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA014, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8010, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x801a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8023, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8035, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8035, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8035, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8035, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8035, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd719, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3bb7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8014, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd704, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x406e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x12db, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1301, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2a69, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8020, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9f01, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0d45, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf01, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0d43, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xc6bf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1da6, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd708, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2630, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1b58, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x7f63, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2c72, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x802d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8024, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1da6, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd708, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x30}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2630, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x31}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1b58, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x32}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2318, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x33}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1b55, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x34}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x35}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x802d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x36}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA026, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA024, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA022, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA020, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA006, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA004, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1b4c, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA002, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0d42, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA000, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x12d7, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA008, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0300, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb820, 7 , 7 , 0x0 , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, +}; + +rtk_hwpatch_t rtl8261n_c_nctl1_conf[72] = { + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb820, 7 , 7 , 0x1 , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA016, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0010, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA012, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA014, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8010, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x801f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x802f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x802f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x802f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x802f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x802f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x802f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x38c1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8019, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd73e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6122, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0241, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x801d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd501, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce01, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa50f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd500, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x02e7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x38c1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8029, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd73e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6142, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0288, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8a0f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x802d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd501, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce01, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa50f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd500, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x00d3, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA08E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA08C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA08A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA088, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA086, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA084, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA082, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x00ce, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA080, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x02e3, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA090, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0003, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb820, 7 , 7 , 0x0 , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, +}; + +rtk_hwpatch_t rtl8261n_c_nctl2_conf[878] = { + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb820, 7 , 7 , 0x1 , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA016, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0020, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA012, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA014, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8010, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8029, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8217, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x82d0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x82f9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8322, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8336, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8336, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcb0a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0cc7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4127, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c0f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b05, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c38, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0d28, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf008, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c0f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b0a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c38, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0d18, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0f73, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8034, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8031, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1bf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd06d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x30}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1dd, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x31}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd06d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x32}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x33}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x34}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd06e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x35}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x36}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x37}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x38}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5fba, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x39}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd05a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x60cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x60f1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6113, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6135, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x40}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6157, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x41}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x42}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x43}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x44}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x45}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf008, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x46}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x47}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x48}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x49}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf004, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf002, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x142d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x50}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x51}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0ccf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x52}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b40, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x53}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c3f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x54}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c24, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x55}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x56}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa340, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x57}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x58}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x147c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x59}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa110, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1435, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8110, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1485, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa304, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x60}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa8c0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x61}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8810, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x62}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x63}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x64}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa310, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x65}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0cfc, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x66}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0224, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x67}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0ca0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x68}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0480, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x69}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa340, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd162, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x70}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x71}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x72}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5fba, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x73}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8840, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x74}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1c4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x75}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd045, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x76}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x77}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x78}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x79}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5fba, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6127, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f3b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x88c0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x800a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x80}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x81}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8350, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x82}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x84a0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x83}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffb6, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x84}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xb920, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x85}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcd33, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x86}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x87}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x88}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x89}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x7fb4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9920, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6065, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f94, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x90}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffee, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x91}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xb820, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x92}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x93}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x94}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x95}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x7fa5, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x96}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9820, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x97}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x800a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x98}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x99}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x147c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa108, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1435, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8108, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1485, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa2fc, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa304, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8880, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0cc0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0440, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcd34, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0cc0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xaa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b80, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xab}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xac3f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xac}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c38, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xad}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0d08, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xae}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xaf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa810, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa480, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa604, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x80bb, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xba}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd19f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xbb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xbc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xbd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xbe}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xbf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x63f4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f7a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4368, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0cc0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b40, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8c3f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8d38, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xca}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xcb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xcc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xcd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x80d7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xce}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xcf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x80d4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1f4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1b7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1c6, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xda}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xdb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6074, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xdc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xdd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f7a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xde}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xdf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4056, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf004, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x61fc, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xfff9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xea}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4070, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xeb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xec}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x81a4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xed}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xee}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xef}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xae80, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x81a4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd05a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x60cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x60f1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6113, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6135, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xfa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6157, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xfb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xfc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xfd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xfe}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xff}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf008, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x100}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x101}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x102}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x103}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf004, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x104}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x105}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf002, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x106}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x107}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x108}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x142d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x109}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0ccf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b40, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c3f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c24, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x110}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa340, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x111}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x112}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x147c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x113}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa110, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x114}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x115}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1435, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x116}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8110, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x117}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x118}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1485, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x119}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa304, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa8c0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8810, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa310, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0cfc, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x120}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0224, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x121}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0ca0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x122}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0480, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x123}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8604, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x124}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcd35, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x125}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd162, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x126}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x127}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x128}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x129}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5fba, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8840, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1c4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd045, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x130}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x131}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5fba, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x132}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x133}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6127, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x134}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x135}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f3b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x136}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x88c0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x137}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x800a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x138}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x139}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8350, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x84a0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffb8, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbb80, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x140}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5fb4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x141}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xb920, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x142}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcd36, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x143}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x144}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x145}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x146}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x7fb4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x147}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9920, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x148}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9b80, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x149}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6065, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f94, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffe8, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xb820, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x150}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x151}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x152}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x153}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x7fa5, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x154}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9820, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x155}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x800a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x156}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x157}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x158}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x147c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x159}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa108, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1435, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8108, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1485, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa2fc, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x160}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa304, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x161}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8880, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x162}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0cc0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x163}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0440, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x164}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcd37, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x165}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x166}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x167}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0cc0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x168}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b80, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x169}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xac3f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c38, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0d08, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa810, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x170}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa480, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x171}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa604, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x172}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x173}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x174}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x817e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x175}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x176}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x817b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x177}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x178}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x179}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x180}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x181}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x182}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1463, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x183}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x184}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f7a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x185}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x186}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f28, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x187}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x188}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x189}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0cc0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b40, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8c3f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8d38, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x190}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x819a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x191}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x192}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8197, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x193}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x194}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x195}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x196}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x197}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x198}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x199}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd189, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1463, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f7a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f28, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c0f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b05, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x60cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1aa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x60f1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ab}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6113, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ac}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6135, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ad}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6157, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ae}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1af}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce08, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce08, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf008, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce08, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce08, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf004, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce08, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf002, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce08, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ba}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1bb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x142d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1bc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa180, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1bd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcd38, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1be}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1bf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x81d4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x81cc, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf013, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd100, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ca}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf010, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1cb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1cc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1cd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1b7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ce}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1cf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd100, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf008, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1da}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd13b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1db}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd055, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1dc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1dd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1de}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1df}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1463, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f7b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa302, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1463, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f7a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ea}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f28, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1eb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ec}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ed}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c3f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ee}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c12, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ef}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8206, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x81fe, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf013, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1fa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd100, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1fb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1fc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf010, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1fd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1fe}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ff}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x200}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x201}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x202}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd100, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x203}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd040, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x204}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf008, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x205}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x206}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x207}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x208}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x209}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd16b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1463, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x210}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x211}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f7a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x212}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x213}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f2a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x214}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x215}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x087a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x216}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x217}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x646d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x218}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x219}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8231, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8227, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x40c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x220}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd100, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x221}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x222}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf01a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x223}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x224}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x225}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf017, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x226}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x227}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x40c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x228}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x229}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd100, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf010, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x230}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x231}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x40c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x232}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x233}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x234}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x235}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x236}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x237}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x238}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x239}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1463, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x240}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x241}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f7a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x242}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x243}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f29, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x244}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x245}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x60cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x246}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x60f1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x247}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6113, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x248}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6135, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x249}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6157, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf008, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x250}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x251}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x252}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf004, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x253}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x254}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf002, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x255}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x256}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x257}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x142d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x258}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x259}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8bc0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c3f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c09, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa310, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x260}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa420, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x261}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcd3b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x262}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x263}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x65ad, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x264}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x43c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x265}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x266}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x267}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x827b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x268}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x269}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8273, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf024, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd15d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x270}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x271}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf021, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x272}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x273}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x274}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1c6, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x275}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x276}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf01c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x277}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd15d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x278}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x279}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf019, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf014, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x280}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x281}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf011, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x282}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x283}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x284}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x828e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x285}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x286}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x828b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x287}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1e5, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x288}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x289}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf009, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd191, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x290}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd16b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x291}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x292}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x293}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x294}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x295}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1463, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x296}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x297}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f7a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x298}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x299}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f2c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x40e7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c0f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b05, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c0f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b0a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcd3c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x644d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2aa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x43c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ab}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ac}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ad}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x82c1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ae}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2af}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x82b9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf019, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf016, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ba}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2bb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2bc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf011, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2bd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd13e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2be}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2bf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf009, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ca}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2cb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2cc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2cd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ce}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0956, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2cf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2969, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x82f5, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x82eb, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x82e1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x40c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2da}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd15c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2db}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2dc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf01a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2dd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2de}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2df}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf017, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x40c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd13e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf010, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ea}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2eb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x40c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ec}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ed}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ee}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ef}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x09a0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2969, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2fa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x831e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2fb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2fc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8314, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2fd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2fe}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x830a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ff}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x300}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x40c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x301}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x302}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x303}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd15d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x304}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x305}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf01a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x306}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x307}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x308}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf017, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x309}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x30a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x40c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x30b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x30c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x30d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd16b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x30e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x30f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf010, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x310}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x311}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x312}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x313}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x314}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x40c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x315}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x316}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x317}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x318}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x319}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x31a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x31b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x31c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x31d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1b7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x31e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x31f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x320}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0a39, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x321}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x322}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2969, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x323}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8332, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x324}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x325}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x832f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x326}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x327}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x832c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x328}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd18a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x329}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x32a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf009, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x32b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x32c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x32d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x32e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1c6, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x32f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x330}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x331}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1b7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x332}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x333}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x334}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0506, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x335}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA10E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA10C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA10A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x04f4, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA108, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0a12, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA106, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0979, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA104, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x089f, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA102, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0692, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA100, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0f60, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA110, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x003f, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA016, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0020, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA012, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1ff8, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA014, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b0e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ff8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b0e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ff9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b0e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ffa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ffb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ffc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ffd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ffe}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1fff}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA164, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0baa, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA166, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c19, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA168, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1293, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA16A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3fff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA16C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3fff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA16E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3fff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA170, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3fff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA172, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3fff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA162, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0007, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb820, 7 , 7 , 0x0 , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, +}; + +rtk_hwpatch_t rtl8261n_c_algxg_conf[184] = { + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8165, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x22 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8167, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x33 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x827E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x68 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8013, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x39 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8ffb, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x14 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8ff9, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x1e , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x82D9, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x20 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x82DA, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x816E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0xab , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8159, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x58 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x815A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x99 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8139, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x25 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8125, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x67 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8126, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x89 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x827D, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x4c , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8205, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x4d , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8FFA, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x78 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8159, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x58 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x815A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x99 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x815B, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x77 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x815C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0xfb , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8125, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x67 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8126, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x89 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8127, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x77 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8128, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0xf7 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x80DF, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x51 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x80E0, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x94 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x80F1, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x99 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x80F2, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x97 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x80F4, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0xF9 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x80F7, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x99 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x80F8, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x9A , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x80FA, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x39 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x817B, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x40 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x817C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0xCC , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8149, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x28 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x814A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0xE3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x816D, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0xAA , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x80F3, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x75 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x80F9, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x73 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x869D, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0xD , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8695, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x39 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x868D, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x869E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x61 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8696, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x66 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x868E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0xF3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x869F, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x15 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8697, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x3E , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x868F, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0xE , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x86A0, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x89 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8698, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x95 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8690, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0xC1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x86A1, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x35 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8699, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x64 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8691, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x32 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x86A2, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0xDC , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x869A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x59 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8692, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0xC8 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x86A3, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x1E , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x869B, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x2F , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8693, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x13 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x86A4, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x5A , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x869C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0xC , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8694, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x7D , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x86B5, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x9 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x86AD, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x21 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x86A5, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x4 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x86B6, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x9 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x86AE, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x6D , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x86A6, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x88 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x86B7, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x12 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x86AF, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x2D , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x86A7, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0xC , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x86B8, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x59 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x86B0, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x72 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x86A8, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x41 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x86B9, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x34 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x86B1, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x57 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x86A9, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x30 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x86BA, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0xA2 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x86B2, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0xBD , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x86AA, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x48 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x86BB, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x22 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x86B3, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x2F , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x86AB, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x22 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x86BC, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x10 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x86B4, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x82 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x86AC, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0xF5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x820A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x61 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x820B, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x97 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x820C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x7C , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x820D, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0xB2 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, +}; + +rtk_hwpatch_t rtl8261n_c_alg_giga_conf[5] = { + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa836, 15, 15, 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa85c, 7 , 7 , 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa85c, 6 , 3 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8367, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x5d , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, +}; + +rtk_hwpatch_t rtl8261n_c_normal_conf[91] = { + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x817d, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x07 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb516, 6 , 0 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8ffe, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x04 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8fff, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x05 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8132, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x77 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8134, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x88 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x80ca, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x77 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x80cc, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x88 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8062, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x77 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8064, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x88 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x801E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0014, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xac1c, 8 , 7 , 0x3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xac1e, 13, 12, 0x3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xad96, 7 , 6 , 0x3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xad96, 5 , 4 , 0x3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xad96, 3 , 2 , 0x3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xad96, 1 , 0 , 0x3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xad98, 3 , 2 , 0x3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xad98, 1 , 0 , 0x3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xae38, 3 , 2 , 0x3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xae38, 1 , 0 , 0x3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb00a, 14, 14, 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb006, 13, 12, 0x3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb00a, 10, 10, 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb00a, 9 , 9 , 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb00a, 8 , 8 , 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb008, 13, 12, 0x3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb008, 9 , 8 , 0x3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb008, 5 , 4 , 0x3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb00a, 6 , 6 , 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb00a, 4 , 4 , 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb00a, 2 , 2 , 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb10a, 14, 14, 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb106, 13, 12, 0x3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb10a, 10, 10, 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb10a, 9 , 9 , 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb10a, 8 , 8 , 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb108, 13, 12, 0x3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb108, 9 , 8 , 0x3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb108, 5 , 4 , 0x3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb10a, 6 , 6 , 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb10a, 4 , 4 , 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb10a, 2 , 2 , 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb20a, 14, 14, 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb206, 13, 12, 0x3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb20a, 10, 10, 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb20a, 9 , 9 , 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb20a, 8 , 8 , 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb208, 13, 12, 0x3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb208, 9 , 8 , 0x3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb208, 5 , 4 , 0x3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb20a, 6 , 6 , 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb20a, 4 , 4 , 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb20a, 2 , 2 , 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb30a, 14, 14, 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb306, 13, 12, 0x3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb30a, 10, 10, 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb30a, 9 , 9 , 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb30a, 8 , 8 , 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb308, 13, 12, 0x3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb308, 9 , 8 , 0x3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb308, 5 , 4 , 0x3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb30a, 6 , 6 , 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb30a, 4 , 4 , 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb30a, 2 , 2 , 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x82DF, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8267, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x81EF, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x829A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8222, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x81AA, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x829B, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x7 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8223, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x7 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, +}; + +rtk_hwpatch_t rtl8261n_c_dataram_conf[148] = { + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb820, 7 , 7 , 0x0 , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb896, 0 , 0 , 0x0 , RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb892, 15, 8 , 0x0 , RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC10B, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xD5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC10C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xD5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC10D, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xD5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC10E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xD5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC10F, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xD5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC110, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xD5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC149, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x08 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC14A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x08 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC14B, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x08 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC14C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x08 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC14D, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x08 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC14E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x08 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC166, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xEE , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC167, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xEE , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC168, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x07 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC169, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x09 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC16A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x0B , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC16B, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x0D , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC16C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x13 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC16D, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x0E , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC16E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x11 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC16F, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x14 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC170, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x17 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC171, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x15 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC172, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x10 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC173, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x0B , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC128, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xF7 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC129, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xF7 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC12A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xF8 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC12B, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xF7 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC12C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xF6 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC12D, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xF5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC12E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xF2 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC12F, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xF7 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC130, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xF5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC131, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xF2 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC132, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xF0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC133, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xF1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC134, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xF4 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC135, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xF7 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC118, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xEC , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC119, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xEB , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC11A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xEB , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC11B, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xE8 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC11C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xE8 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC11D, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xEA , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC11E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xE9 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC11F, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xE7 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC120, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xE6 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC121, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xE7 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC122, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xE6 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC123, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xEA , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC124, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xEB , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC125, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xED , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC126, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xE3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC127, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xE0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC156, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x19 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC157, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x1B , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC158, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x1B , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC159, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x1F , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC15A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x1E , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC15B, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x1C , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC15C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x1D , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC15D, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x20 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC15E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x22 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC15F, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x21 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC160, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x25 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC161, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x20 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC162, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x21 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC163, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x27 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC164, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x57 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC165, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x74 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb896, 0 , 0 , 0x1 , RTK_PATCH_CMP_W , 0, 0, 0, 0}, +}; + +rtk_hwpatch_t rtl8261n_c_rtct_conf[176] = { + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa468, 1 , 0 , 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa422, 0 , 0 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xc010, 9 , 9 , 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xc010, 10, 10, 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xc010, 14, 13, 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xc000, 0 , 0 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_DELAY_MS, 0 , 0 , 0 , 0 , 0 , 1000 , RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8260, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x25 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8270, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x8 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8271, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x1D , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8280, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x1E , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8281, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xA0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8278, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x02 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8279, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8274, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x01 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8275, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x01 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8276, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8277, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x827C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x3A , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x827D, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xE0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x827E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x827F, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x25 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x827A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x03 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x827B, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xC0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8263, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x34 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8264, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xBC , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8261, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x32 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8262, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8265, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8273, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xE4 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8266, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x45 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8267, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xE0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8282, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8283, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x08 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8284, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8285, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x1D , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8286, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xFF , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8287, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xFA , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8288, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8289, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x03 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x828A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x05 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x828B, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xE7 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x828C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xFF , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x828D, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x5F , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x828E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x828F, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x3E , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8290, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xFF , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8291, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xF4 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8292, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x06 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8293, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xF5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8294, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xFF , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8295, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x12 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8296, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8297, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x59 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8298, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xFF , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8299, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xF2 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x829A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xF8 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x829B, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xEA , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x829C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x829D, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x35 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x829E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xFF , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x829F, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xBE , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82A0, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82A1, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x36 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82A2, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xFA , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82A3, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x30 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82A4, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82A5, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x35 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82A6, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xFF , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82A7, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xBE , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82A8, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82A9, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x36 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82AA, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x06 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82AB, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x10 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82AC, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xFF , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82AD, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x98 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82AE, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82AF, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x10 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82B0, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82B1, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x06 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82B2, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x02 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82B3, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x60 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82B4, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82B5, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82B6, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82B7, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82B8, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82B9, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x826D, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x2B , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x826E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x03 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa422, 1 , 1 , 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa422, 7 , 4 , 0xf , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 90 , 21 , 7 , 0 , 0x4 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, +}; + diff --git a/sources/rtk-be550/src/hal/phy/construct/conf_rtl8264b.c b/sources/rtk-be550/src/hal/phy/construct/conf_rtl8264b.c new file mode 100755 index 00000000..8f61054e --- /dev/null +++ b/sources/rtk-be550/src/hal/phy/construct/conf_rtl8264b.c @@ -0,0 +1,2331 @@ +/* + * SPDX-License-Identifier: GPL-2.0-only + * + * Copyright (c) 2023 Realtek Semiconductor Corp. All rights reserved. + */ +//Date: Tue Jan 31 11:51:10 2023 + +rtk_hwpatch_t rtl8264b_top_conf[] = { + {RTK_PATCH_OP_TOP , 0xf , 2 , 20 , 15, 0 , 0x5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 2 , 21 , 15, 0 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 2 , 22 , 15, 0 , 0x280 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 2 , 23 , 15, 0 , 0x0014, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 3 , 16 , 15, 0 , 0x0300, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 3 , 17 , 15, 0 , 0x01ff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 3 , 18 , 15, 0 , 0x000c, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 3 , 19 , 15, 0 , 0x01ff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 3 , 20 , 15, 0 , 0x0200, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 3 , 21 , 15, 0 , 0x0015, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 3 , 22 , 15, 0 , 0x0200, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 3 , 23 , 15, 0 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 4 , 16 , 15, 0 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 13 , 23 , 8 , 5 , 0x6 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 90 , 18 , 15, 0 , 0xd , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 90 , 19 , 15, 0 , 0xd , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 90 , 20 , 15, 8 , 0x02 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, +}; + +rtk_hwpatch_t rtl8264b_sds_conf[] = { + {RTK_PATCH_OP_TOP , 0xf , 24 , 18 , 15, 0 , 0x881F, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 24 , 19 , 15, 0 , 0x003F, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 24 , 20 , 15, 0 , 0x003F, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 24 , 21 , 15, 0 , 0x003F, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 24 , 22 , 15, 0 , 0x001F, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x06 , 0x0D , 15, 0 , 0x0F00, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x06 , 0x0E , 15, 0 , 0x3F5A, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x07 , 0x10 , 15, 12, 0x8 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x07 , 0x10 , 7 , 0 , 0x3 , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x06 , 0x1D , 15, 0 , 0x0600, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x21 , 0x00 , 15, 0 , 0x4902, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x21 , 0x08 , 15, 0 , 0x0FC0, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x21 , 0x09 , 15, 0 , 0x33F0, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x21 , 0x0C , 15, 0 , 0x08BF, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x21 , 0x12 , 15, 0 , 0x8000, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x36 , 0x07 , 15, 0 , 0x04C0, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x36 , 0x08 , 15, 0 , 0x2000, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2E , 0x0B , 15, 0 , 0x2390, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2E , 0x0C , 15, 0 , 0xAA17, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2E , 0x0D , 15, 0 , 0xFE40, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2E , 0x0E , 15, 0 , 0x12F4, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2E , 0x11 , 15, 0 , 0xF2AD, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2E , 0x15 , 15, 0 , 0x7A41, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2E , 0x16 , 15, 0 , 0x0041, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2F , 0x00 , 15, 0 , 0x1F00, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2F , 0x01 , 15, 0 , 0x2800, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2F , 0x02 , 15, 0 , 0x0FC8, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2F , 0x11 , 15, 0 , 0x3000, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2F , 0x13 , 15, 0 , 0xF400, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2F , 0x1E , 15, 0 , 0x0500, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x34 , 0x0B , 15, 0 , 0x2390, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x34 , 0x0C , 15, 0 , 0xA517, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x34 , 0x0D , 15, 0 , 0xFE41, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x34 , 0x0E , 15, 0 , 0x12F4, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x34 , 0x11 , 15, 0 , 0xF2AD, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x34 , 0x15 , 15, 0 , 0x7A41, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x34 , 0x16 , 15, 0 , 0x0041, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x35 , 0x00 , 15, 0 , 0x1F80, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x35 , 0x01 , 15, 0 , 0x0800, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x35 , 0x02 , 15, 0 , 0x0FC8, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x35 , 0x11 , 15, 0 , 0x3001, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x35 , 0x13 , 15, 0 , 0xF400, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x35 , 0x1E , 15, 0 , 0x0100, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2C , 0x0B , 15, 0 , 0x2390, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2C , 0x0C , 15, 0 , 0xA517, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2C , 0x0D , 15, 0 , 0xFE41, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2C , 0x0E , 15, 0 , 0x12F4, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2C , 0x11 , 15, 0 , 0xF2AD, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2C , 0x15 , 15, 0 , 0x7A61, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2C , 0x16 , 15, 0 , 0x0041, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2D , 0x00 , 15, 0 , 0x1F80, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2D , 0x01 , 15, 0 , 0x0800, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2D , 0x02 , 15, 0 , 0x0FC8, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2D , 0x11 , 15, 0 , 0x3001, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2D , 0x13 , 15, 0 , 0xF400, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2D , 0x1E , 15, 0 , 0x0100, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x28 , 0x0B , 15, 0 , 0x2390, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x28 , 0x0C , 15, 0 , 0xA514, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x28 , 0x0D , 15, 0 , 0xFE43, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x28 , 0x0E , 15, 0 , 0x12F4, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x28 , 0x11 , 15, 0 , 0xF2AD, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x28 , 0x15 , 15, 0 , 0x7A61, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x28 , 0x16 , 15, 0 , 0x0041, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x29 , 0x00 , 15, 0 , 0x1F80, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x29 , 0x01 , 15, 0 , 0x0800, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x29 , 0x02 , 15, 0 , 0x0FC8, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x29 , 0x11 , 15, 0 , 0x3001, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x29 , 0x13 , 15, 0 , 0xF400, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x29 , 0x1E , 15, 0 , 0x0100, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x26 , 0x0B , 15, 0 , 0x2390, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x26 , 0x0C , 15, 0 , 0xA514, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x26 , 0x0D , 15, 0 , 0xFE43, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x26 , 0x0E , 15, 0 , 0x12F4, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x26 , 0x11 , 15, 0 , 0xF2AD, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x26 , 0x15 , 15, 0 , 0x7A41, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x26 , 0x16 , 15, 0 , 0x0041, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x27 , 0x00 , 15, 0 , 0x1F80, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x27 , 0x01 , 15, 0 , 0x0800, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x27 , 0x02 , 15, 0 , 0x0FC8, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x27 , 0x11 , 15, 0 , 0x3001, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x27 , 0x13 , 15, 0 , 0xF400, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x27 , 0x1E , 15, 0 , 0x0100, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x24 , 0x0B , 15, 0 , 0x2390, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x24 , 0x0C , 15, 0 , 0xA514, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x24 , 0x0D , 15, 0 , 0xFE43, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x24 , 0x0E , 15, 0 , 0x12F4, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x24 , 0x11 , 15, 0 , 0xF2AD, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x24 , 0x15 , 15, 0 , 0x7A41, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x24 , 0x16 , 15, 0 , 0x0041, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x25 , 0x00 , 15, 0 , 0x1F80, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x25 , 0x01 , 15, 0 , 0x0800, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x25 , 0x02 , 15, 0 , 0x0FC8, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x25 , 0x11 , 15, 0 , 0x3001, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x25 , 0x13 , 15, 0 , 0xF400, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x25 , 0x1E , 15, 0 , 0x0100, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 24 , 18 , 15, 0 , 0x880D, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 24 , 19 , 15, 0 , 0x0024, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 24 , 20 , 15, 0 , 0x0036, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 24 , 21 , 15, 0 , 0x0035, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 24 , 22 , 15, 0 , 0x001A, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x1F , 0x00 , 15, 0 , 0x001B, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x1F , 0x00 , 15, 0 , 0x0000, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 90 , 20 , 7 , 0 , 0x04 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, +}; + +rtk_hwpatch_t rtl8264b_afe_conf[] = { + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbf92, 15, 11, 0x1C , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbfaa, 10, 8 , 0x5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbfae, 8 , 6 , 0x5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbfaa, 12, 11, 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbf1c, 4 , 4 , 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbf0e, 5 , 4 , 0x3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbf1c, 15, 13, 0x5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbf16, 12, 12, 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbc24, 3 , 2 , 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbc24, 1 , 0 , 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbf08, 2 , 0 , 0x6 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbf0c, 5 , 3 , 0x7 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbf0c, 8 , 6 , 0x7 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbf0c, 11, 9 , 0x7 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbf0c, 14, 12, 0x7 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbf1a, 3 , 2 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 90 , 21 , 15, 8 , 0x04 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, +}; + +rtk_hwpatch_t rtl8264b_uc_conf[] = { + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb820, 7 , 7 , 0x0 , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbd8a, 5 , 3 , 0x3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbd8c, 6 , 4 , 0x5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8060, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 12, 10, 0x3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8061, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 13, 0x5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa466, 1 , 1 , 0x1 , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8491, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x1D , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8018, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 12, 12, 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x85af, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xaf85, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85af}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xc7af, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85b1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x85df, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85b3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xaf86, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85b5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1baf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85b7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8674, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85b9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xaf86, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85bb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x7daf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85bd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x875b, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85bf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xaf87, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85c1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x67af, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85c3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8774, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85c5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf85, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85c7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xdc02, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85c9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6957, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85cb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe48f, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85cd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2ce5, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85cf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8f2d, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85d1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe084, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85d3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x11e1, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85d5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8412, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85d7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xaf5d, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85d9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x73f6, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85db}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xb01a, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85dd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe08f, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85df}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2ce1, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85e1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8f2d, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85e3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6d, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85e5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6802, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85e7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6938, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85e9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6d, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85eb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6b02, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85ed}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6938, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85ef}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6d, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85f1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6e02, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85f3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6938, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85f5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6d, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85f7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x7102, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85f9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6938, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85fb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6d, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85fd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x7402, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85ff}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x70e5, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8601}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6d, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8603}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x7702, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8605}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x70e5, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8607}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6d, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8609}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x7a02, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x860b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x70e5, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x860d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6d, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x860f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x7d02, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8611}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x70e5, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8613}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd784, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8615}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa2af, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8617}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5eed, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8619}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0286, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x861b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x21af, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x861d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x07ad, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x861f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf8f9, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8621}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xfaef, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8623}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x69e0, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8625}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8018, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8627}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xad24, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8629}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x39d4, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x862b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x002e, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x862d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6e, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x862f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0402, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8631}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6938, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8633}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd480, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8635}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x03bf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8637}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x866e, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8639}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0269, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x863b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x38d4, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x863d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x000f, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x863f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf86, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8641}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x7102, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8643}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6938, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8645}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf86, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8647}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x7102, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8649}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x70dc, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x864b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd480, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x864d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0bbf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x864f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x866e, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8651}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0269, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8653}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x38d4, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8655}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x000f, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8657}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf86, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8659}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x7102, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x865b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6938, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x865d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf86, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x865f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x7102, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8661}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x70dc, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8663}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0208, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8665}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1eef, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8667}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x96fe, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8669}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xfdfc, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x866b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x04f0, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x866d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbd94, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x866f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x30bd, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8671}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9602, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8673}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8621, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8675}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0254, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8677}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xdcaf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8679}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x03c1, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x867b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0286, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x867d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2102, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x867f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8686, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8681}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xaf04, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8683}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x41f8, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8685}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xfbef, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8687}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x79e0, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8689}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8018, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x868b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xac20, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x868d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x03af, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x868f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8756, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8691}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6b, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8693}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3402, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8695}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x70dc, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8697}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6b, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8699}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3102, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x869b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x70e5, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x869d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6f, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x869f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4902, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86a1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x70dc, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86a3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6f, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86a5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4c02, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86a7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x70e5, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86a9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6f, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86ab}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4f02, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86ad}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x70e5, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86af}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6b, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86b1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3702, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86b3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x70dc, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86b5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6c, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86b7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c02, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86b9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x70dc, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86bb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6b, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86bd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3402, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86bf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x70e5, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86c1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1f00, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86c3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe183, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86c5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd4bf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86c7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6bcd, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86c9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0269, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86cb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x38bf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86cd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6bd0, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86cf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0269, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86d1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x38bf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86d3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6bd3, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86d5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0269, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86d7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x38bf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86d9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6bd6, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86db}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0269, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86dd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x38bf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86df}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6bd9, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86e1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0270, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86e3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe5bf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86e5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6bdc, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86e7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0270, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86e9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe5bf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86eb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6bdf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86ed}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0270, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86ef}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe5bf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86f1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6be2, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86f3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0270, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86f5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe5bf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86f7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6f46, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86f9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0270, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86fb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xdce1, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86fd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x83d3, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86ff}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6f, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8701}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3a02, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8703}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6938, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8705}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0d14, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8707}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6f, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8709}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4002, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x870b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6938, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x870d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0d12, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x870f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6f, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8711}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3d02, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8713}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6938, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8715}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6f, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8717}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4302, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8719}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x70dc, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x871b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0238, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x871d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xb5bf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x871f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6bd9, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8721}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0270, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8723}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xdcbf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8725}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6bdc, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8727}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0270, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8729}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xdcbf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x872b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6bdf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x872d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0270, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x872f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xdcbf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8731}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6be2, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8733}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0270, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8735}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xdcbf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8737}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6b34, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8739}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0270, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x873b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xdcbf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x873d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6b37, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x873f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0270, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8741}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe5bf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8743}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6f4f, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8745}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0270, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8747}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xdcbf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8749}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6b31, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x874b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0270, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x874d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xdcbf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x874f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6f4c, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8751}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0270, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8753}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xdcef, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8755}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x97ff, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8757}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xfc04, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8759}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xac2f, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x875b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x03af, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x875d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b2a, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x875f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x020e, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8761}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x95af, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8763}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b3f, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8765}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xee84, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8767}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3c00, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8769}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6c, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x876b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c02, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x876d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x70e5, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x876f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xaf01, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8771}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0300, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8773}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb818, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5d6d, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb81a, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5eea, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb81c, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x07aa, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb81e, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x03be, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb850, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x043e, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb852, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b26, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb878, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x00fd, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb884, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb832, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x007f, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, +}; + +rtk_hwpatch_t rtl8264b_uc2_conf[] = { + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb820, 7 , 7 , 0x1 , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb87c, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8acf, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb87e, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xaf8a, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8acf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe7af, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ad1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8b40, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ad3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xaf8b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ad5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4caf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ad7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8b6a, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ad9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xaf8b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8adb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xb5af, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8add}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8bd1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8adf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xaf8c, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ae1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x04af, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ae3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8c12, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ae5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf67, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ae7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6302, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ae9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x65f5, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8aeb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xef31, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8aed}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf67, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8aef}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6002, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8af1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x65f5, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8af3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1e31, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8af5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xac38, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8af7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x19bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8af9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x676c, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8afb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0265, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8afd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf5ef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8aff}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x31bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b01}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6769, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b03}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0265, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b05}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf51e, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b07}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x31ac, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b09}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x380c, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b0b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xee89, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b0d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2c02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b0f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xae0a, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b11}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xee89, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b13}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2c00, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b15}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xae04, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b17}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xee89, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b19}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2c01, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b1b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf8f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b1d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd5e1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b1f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x892c, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b21}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1a91, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b23}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xdbbf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b25}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x67cf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b27}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0265, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b29}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf51f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b2b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x001f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b2d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x221b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b2f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x45ad, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b31}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2705, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b33}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe187, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b35}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x06ae, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b37}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x03e1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b39}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8707, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b3b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xaf2d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b3d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1a02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b3f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8c1e, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b41}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x028c, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b43}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x7b02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b45}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x224f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b47}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xaf40, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b49}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xb8ac, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b4b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2f0f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b4d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0210, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b4f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x62bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b51}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6d36, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b53}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0265, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b55}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf5e5, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b57}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8fde, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b59}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xaf10, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b5b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4ae1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b5d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8fde, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b5f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b61}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3602, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b63}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x65d6, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b65}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xaf10, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b67}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x59e1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b69}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8fdd, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b6b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa100, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b6d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0dbf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b6f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6d36, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b71}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0265, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b73}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf5e5, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b75}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8fdc, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b77}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xee8f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b79}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xdd01, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b7b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b7d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3602, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b7f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6f77, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b81}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf86, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b83}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xc7e1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b85}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x892c, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b87}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4903, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b89}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1a91, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b8b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xef69, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b8d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xdbbf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b8f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x67cf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b91}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0265, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b93}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf51f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b95}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x001f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b97}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x22ef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b99}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x741b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b9b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x45ad, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b9d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2711, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b9f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf86, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ba1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd0d0, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ba3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x00e1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ba5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8fdc, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ba7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ba9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3602, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bab}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x65d6, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bad}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xaf35, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8baf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x46af, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bb1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3527, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bb3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x026f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bb5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6eee, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bb7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8fdd, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bb9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x00bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bbb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8d31, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bbd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x026f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bbf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6ebf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bc1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8d40, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bc3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x026f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bc5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6ebf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bc7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8d46, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bc9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x026f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bcb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6eaf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bcd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x36a9, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bcf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf8ef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bd1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x49f8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bd3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6e, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bd5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xc202, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bd7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x65f5, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bd9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xad28, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bdb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13e1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bdd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8a4e, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bdf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xad28, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8be1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0502, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8be3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5d65, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8be5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xae0e, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8be7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x025c, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8be9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1202, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8beb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8cc5, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bed}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xae06, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bef}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x025b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bf1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf302, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bf3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8d0d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bf5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe087, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bf7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x17f6, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bf9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x27e4, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bfb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8717, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bfd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xfcef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bff}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x94fc, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c01}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x04a1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c03}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0103, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c05}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x028c, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c07}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe9e0, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c09}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8a02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c0b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xef23, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c0d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xaf5c, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c0f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xdeac, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c11}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5003, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c13}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xaf61, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c15}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0d02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c17}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8d0d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c19}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xaf61, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c1b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33f8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c1d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xfafb, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c1f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xef79, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c21}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xfbbf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c23}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6766, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c25}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0265, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c27}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf5ad, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c29}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2810, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c2b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xad30, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c2d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x05d7, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c2f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0002, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c31}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xae16, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c33}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xad32, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c35}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x24d7, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c37}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0003, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c39}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xae0e, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c3b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xad31, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c3d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x05d7, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c3f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c41}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xae06, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c43}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xad33, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c45}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x14d7, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c47}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0001, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c49}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf8f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c4b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xdf4f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c4d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0008, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c4f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1a97, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c51}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd78c, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c53}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x63d6, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c55}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8c7b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c57}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0265, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c59}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3bff, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c5b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xef97, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c5d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xfffe, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c5f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xfc04, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c61}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x206b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c63}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0e20, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c65}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6b11, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c67}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x206b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c69}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1420, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c6b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6b17, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c6d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x206b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c6f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2020, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c71}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6b23, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c73}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x206b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c75}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2600, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c77}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6b29, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c79}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf8fa, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c7b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xef69, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c7d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c7f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbd02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c81}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x65f5, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c83}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xad28, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c85}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0ebf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c87}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8d34, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c89}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x026f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c8b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x77bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c8d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8d31, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c8f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x026f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c91}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x77ae, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c93}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2ad1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c95}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0fbf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c97}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8d37, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c99}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0265, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c9b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd6bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c9d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8d3a, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c9f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x026f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ca1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6ed1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ca3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x00bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ca5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8d3d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ca7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0265, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ca9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd6bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cab}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8d40, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cad}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x026f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8caf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x77d1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cb1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x00bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cb3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8d43, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cb5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0265, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cb7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd6bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cb9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8d46, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cbb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x026f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cbd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x77ef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cbf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x96fe, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cc1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xfc04, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cc3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf8ef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cc5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x49f8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cc7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cc9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbd02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ccb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x65f5, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ccd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xac28, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ccf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x12bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cd1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6be6, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cd3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0265, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cd5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf5e5, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cd7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8fd8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cd9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cdb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf202, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cdd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x65f5, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cdf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe58f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ce1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd9fc, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ce3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xef94, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ce5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xfc04, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ce7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf8ef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ce9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x49f8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ceb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ced}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbd02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cef}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x65f5, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cf1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xac28, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cf3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x12e1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cf5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8fda, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cf7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cf9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe602, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cfb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x65d6, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cfd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe18f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cff}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xdbbf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d01}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6bf2, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d03}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0265, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d05}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd6fc, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d07}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xef94, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d09}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xfc04, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d0b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf8ef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d0d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x49f8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d0f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d11}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbd02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d13}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x65f5, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d15}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xac28, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d17}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x12e1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d19}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8fd8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d1b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d1d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe602, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d1f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x65d6, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d21}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe18f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d23}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd9bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d25}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6bf2, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d27}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0265, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d29}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd6fc, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d2b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xef94, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d2d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xfc04, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d2f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x77bd, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d31}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6c66, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d33}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbd6c, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d35}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x30bd, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d37}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5444, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d39}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbd54, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d3b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x85bd, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d3d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5e55, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d3f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbd54, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d41}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa7bd, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d43}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5cbb, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d45}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbd5c, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d47}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb85e, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2d07, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb860, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x40b5, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb862, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1047, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb864, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3504, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb886, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x36A6, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb888, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x613d, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb88a, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5cd9, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb88c, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x610a, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb838, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x00ff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb820, 7 , 7 , 0x0 , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, +}; + +rtk_hwpatch_t rtl8264b_nctl0_conf[] = { + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb820, 7 , 7 , 0x1 , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA016, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA012, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA014, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8010, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8015, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8020, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x802a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8030, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8035, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8046, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x806b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd707, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x606f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x801a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd707, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x606f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x801a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce10, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcf01, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd705, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4004, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcf02, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd719, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3bb7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8024, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd704, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x406e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x12bd, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x12e3, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xab80, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd500, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xc402, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x004a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x30}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8b80, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x31}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd500, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x32}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x33}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0108, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x34}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c0f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x35}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x090f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x36}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c0f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x37}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0a03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x38}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd004, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x39}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1c1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x401c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce00, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd500, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x801a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x40}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd501, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x41}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce01, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x42}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x43}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x44}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0aa9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x45}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd500, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x46}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x47}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2a69, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x48}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8056, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x49}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3f48, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8058, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3f4b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x805a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x618c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3f40, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x805c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x50}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3f43, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x51}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x805e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x52}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x616b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x53}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6187, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x54}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x55}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcc8f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x56}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x57}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcc8d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x58}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf008, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x59}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcc8b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcc89, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf004, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcc87, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf002, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcc91, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x60}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x61}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b9a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x62}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x63}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xca80, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x64}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x65}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0ba0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x66}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xca00, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x67}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd504, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x68}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x69}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1658, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa208, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0a88, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0d91, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA026, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0d90, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA024, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1657, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA022, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0aa1, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA020, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0047, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA006, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0049, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA004, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x12b9, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA002, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0be5, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA000, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1811, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA008, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xff00, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA016, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA012, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0ff8, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA014, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xc483, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x0ff8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xc483, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xff9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xffa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xffb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xffc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xffd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xffe}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xfff}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA152, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1a83, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA154, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1d29, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA156, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3fff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA158, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3fff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA15A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3fff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA15C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3fff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA15E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3fff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA160, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3fff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA150, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0003, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb820, 7 , 7 , 0x0 , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, +}; + +rtk_hwpatch_t rtl8264b_nctl1_conf[] = { +}; + +rtk_hwpatch_t rtl8264b_nctl2_conf[] = { + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb820, 7 , 7 , 0x1 , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA016, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0020, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA012, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA014, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8010, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8022, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x809f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x80fb, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x810f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8116, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8304, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x831d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8370, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd707, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x416f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd05a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa501, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd701, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5fbd, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8501, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0427, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x040b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa610, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcd16, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa501, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd701, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5fbd, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8501, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd707, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x406f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x803d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x30}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x31}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x32}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x33}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5fbe, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x34}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x35}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x36}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8380, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x37}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x38}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd403, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x39}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13c5, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa340, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1433, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa108, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x40}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x41}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13ec, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x42}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8108, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x43}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x44}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x143c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x45}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa304, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x46}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa8c0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x47}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa2fc, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x48}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x49}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0ca0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0480, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x14a5, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcd17, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1c4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd057, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x50}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1c4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x51}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd066, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x52}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1c4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x53}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd076, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x54}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x55}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x56}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x57}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x607c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x58}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x613d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x59}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xfffb, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa310, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5fbd, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa607, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x60}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf007, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x61}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa607, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x62}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x63}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x64}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x65}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5fbc, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x66}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa310, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x67}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x68}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x69}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5fbb, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8840, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0cf8, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0d48, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x70}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x71}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1c4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x72}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd055, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x73}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x74}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x75}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x76}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5fbb, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x77}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x78}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x61e7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x79}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f3a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x88c0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x82fc, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8350, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x84a0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x80}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8607, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x81}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x82}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x83}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8df8, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x84}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8370, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x85}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x86}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xff9b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x87}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8510, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x88}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa508, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x89}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8508, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcd18, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5fb4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xb920, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x90}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x91}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x92}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x93}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x7fb4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x94}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9920, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x95}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9a20, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x96}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x97}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x98}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x99}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6065, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f94, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffe0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0233, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd705, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3fa7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x80a6, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd75f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x699c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1340, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd704, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4066, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x800a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf002, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xaa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd705, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xab}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x61b4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xac}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd704, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xad}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x609f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xae}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6150, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xaf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2d71, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x80b9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0cf0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x05a0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13b1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xba}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8220, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xbb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c30, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xbc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0410, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xbd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xbe}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x800a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xbf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x81a0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8302, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8480, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8684, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8203, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8340, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xaa10, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8b07, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xca}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xcb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x60cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xcc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x60f1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xcd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6113, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xce}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6135, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xcf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6157, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce0b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce0b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf008, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce0a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce0a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf004, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce09, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xda}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf002, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xdb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce09, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xdc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xdd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xde}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa204, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xdf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13e4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xab08, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcda0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd705, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x40de, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd162, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd045, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf10, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xea}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13b1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xeb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9f10, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xec}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xed}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13b1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xee}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xef}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x607a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13b1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9f10, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8210, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa210, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1340, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xfa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xfb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2969, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xfc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x810b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xfd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xfe}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8108, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xff}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x100}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8105, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x101}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd18a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x102}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x103}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf009, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x104}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x105}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x106}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x107}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1c6, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x108}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x109}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1b7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x04eb, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x110}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8df8, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x111}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8370, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x112}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x113}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x114}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x009e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x115}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x116}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x117}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8121, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x118}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x119}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x811e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1bf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd06d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1dd, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd06d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x120}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x121}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd06e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x122}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x123}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x124}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x125}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5fba, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x126}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x127}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd05a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x128}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x129}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x60cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x60f1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6113, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6135, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6157, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x130}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x131}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x132}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf008, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x133}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x134}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x135}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x136}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf004, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x137}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x138}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf002, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x139}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13e4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0ccf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b40, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x140}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c3f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x141}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c24, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x142}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x143}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa340, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x144}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x145}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1433, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x146}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa110, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x147}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x148}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13ec, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x149}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8110, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x143c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa304, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa8c0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8810, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x150}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x151}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa310, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x152}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0cfc, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x153}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0224, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x154}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0ca0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x155}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0480, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x156}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x157}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x158}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa340, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x159}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd162, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5fba, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x160}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8840, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x161}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1c4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x162}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd045, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x163}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x164}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x165}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x166}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5fba, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x167}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x168}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6127, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x169}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f3b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x88c0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x800a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8350, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x84a0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x170}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffb6, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x171}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xb920, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x172}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcd33, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x173}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x174}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x175}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x176}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x7fb4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x177}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9920, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x178}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x179}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6065, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f94, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffee, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xb820, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x180}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x181}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x182}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x7fa5, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x183}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9820, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x184}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x800a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x185}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x186}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x187}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1433, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x188}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa108, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x189}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13ec, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8108, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x143c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa2fc, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa304, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x190}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8880, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x191}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0cc0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x192}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0440, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x193}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcd34, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x194}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x195}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x196}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0cc0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x197}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b80, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x198}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xac3f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x199}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c38, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0d08, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa810, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa480, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa604, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x81a8, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd19f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1aa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ab}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ac}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x63f4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ad}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ae}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f7a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1af}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4368, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0cc0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b40, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8c3f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8d38, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ba}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x81c4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1bb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1bc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x81c1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1bd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1f4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1be}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1bf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1b7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1c6, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6074, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ca}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f7a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1cb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1cc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1cd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ce}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4056, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1cf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf004, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x61fc, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xfff9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4070, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8291, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1da}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1db}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1dc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xae80, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1dd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1de}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1df}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8291, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd05a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x60cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x60f1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6113, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6135, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6157, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ea}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1eb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ec}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf008, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ed}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ee}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ef}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf004, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf002, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13e4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0ccf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b40, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1fa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c3f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1fb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c24, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1fc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1fd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa340, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1fe}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ff}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1433, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x200}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa110, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x201}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x202}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13ec, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x203}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8110, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x204}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x205}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x143c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x206}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa304, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x207}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa8c0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x208}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8810, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x209}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa310, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0cfc, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0224, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0ca0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0480, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x210}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8604, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x211}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcd35, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x212}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd162, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x213}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x214}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x215}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x216}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x217}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5fba, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x218}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8840, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x219}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1c4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd045, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5fba, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x220}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6127, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x221}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x222}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f3b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x223}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x88c0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x224}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x800a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x225}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x226}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8350, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x227}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x84a0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x228}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffb8, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x229}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbb80, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5fb4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xb920, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcd36, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x230}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x231}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x232}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x233}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x7fb4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x234}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9920, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x235}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9b80, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x236}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x237}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x238}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x239}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6065, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f94, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffe8, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xb820, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x240}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x7fa5, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x241}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9820, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x242}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x800a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x243}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x244}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x245}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1433, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x246}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa108, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x247}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x248}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13ec, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x249}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8108, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x143c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa2fc, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa304, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8880, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0cc0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x250}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0440, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x251}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcd37, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x252}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x253}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x254}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0cc0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x255}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b80, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x256}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xac3f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x257}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c38, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x258}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0d08, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x259}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa810, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa480, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa604, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x260}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x261}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x826b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x262}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x263}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8268, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x264}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x265}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x266}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x267}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x268}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x269}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x141a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x270}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x271}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f7a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x272}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x273}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f28, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x274}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x275}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x276}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0cc0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x277}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b40, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x278}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8c3f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x279}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8d38, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8287, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8284, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x280}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x281}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x282}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x283}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x284}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x285}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x286}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd189, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x287}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x288}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x289}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x141a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f7a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f28, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x290}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x291}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x292}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c0f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x293}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b05, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x294}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x295}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x296}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x60cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x297}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x60f1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x298}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6113, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x299}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6135, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6157, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce08, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce08, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf008, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce08, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce08, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf004, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce08, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf002, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce08, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13e4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa180, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2aa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcd38, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ab}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ac}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ad}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x82c1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ae}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2af}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x82b9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf013, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd100, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf010, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ba}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1b7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2bb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2bc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2bd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd100, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2be}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2bf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf008, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd13b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd055, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ca}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2cb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2cc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x141a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2cd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ce}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f7b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2cf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa302, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x141a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f7a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f28, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2da}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c3f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2db}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c12, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2dc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2dd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2de}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2df}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x82f3, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x82eb, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf013, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd100, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf010, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ea}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2eb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ec}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ed}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ee}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ef}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd100, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd040, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf008, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd16b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2fa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2fb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2fc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x141a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2fd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2fe}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f7a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ff}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x300}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f2a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x301}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x302}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x085e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x303}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x304}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x305}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcb0a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x306}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0cc7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x307}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x308}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x309}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x30a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4127, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x30b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x30c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x30d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c0f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x30e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b05, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x30f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c38, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x310}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0d28, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x311}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x312}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf008, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x313}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x314}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x315}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c0f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x316}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b0a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x317}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c38, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x318}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0d18, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x319}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x31a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x31b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0f45, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x31c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x31d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x646d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x31e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x31f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8337, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x320}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x321}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x832d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x322}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x323}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x40c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x324}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x325}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x326}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd100, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x327}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x328}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf01a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x329}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x32a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x32b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf017, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x32c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x32d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x40c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x32e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x32f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x330}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd100, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x331}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x332}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf010, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x333}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x334}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x335}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x336}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x337}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x40c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x338}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x339}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x33a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x33b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x33c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x33d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x33e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x33f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x340}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x341}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x342}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x343}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x344}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x345}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x141a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x346}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x347}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f7a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x348}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x349}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f29, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x34a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x34b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x60cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x34c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x60f1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x34d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6113, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x34e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6135, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x34f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6157, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x350}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x351}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x352}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x353}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x354}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf008, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x355}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x356}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x357}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x358}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf004, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x359}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x35a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf002, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x35b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x35c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x35d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13e4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x35e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x35f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x360}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8bc0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x361}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c3f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x362}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c09, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x363}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x364}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x365}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa310, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x366}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa420, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x367}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcd3b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x368}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x369}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x65ad, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x36a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x43c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x36b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x36c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x36d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8381, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x36e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x36f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8379, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x370}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x371}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x372}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x373}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x374}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf024, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x375}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd15d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x376}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x377}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf021, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x378}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x379}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x37a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1c6, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x37b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x37c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf01c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x37d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd15d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x37e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x37f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf019, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x380}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x381}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x382}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x383}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x384}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf014, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x385}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x386}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x387}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf011, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x388}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x389}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x38a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8394, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x38b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x38c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8391, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x38d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1e5, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x38e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x38f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf009, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x390}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd191, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x391}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x392}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x393}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x394}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x395}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x396}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd16b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x397}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x398}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x399}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x39a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x39b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x141a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x39c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x39d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f7a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x39e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x39f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f2c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3a0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3a1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x40e7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3a2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3a3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3a4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c0f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3a5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b05, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3a6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3a7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3a8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3a9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3aa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c0f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3ab}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b0a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3ac}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3ad}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcd3c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3ae}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3af}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x644d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3b0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x43c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3b1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3b2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3b3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x83c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3b4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3b5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x83bf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3b6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3b7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3b8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3b9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3ba}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf019, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3bb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3bc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3bd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf016, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3be}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3bf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3c0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3c1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3c2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf011, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3c3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd13e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3c4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3c5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3c6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3c7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3c8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3c9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3ca}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf009, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3cb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3cc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3cd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3ce}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3cf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3d0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3d1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3d2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3d3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3d4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x093a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3d5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA10E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0883, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA10C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0f32, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA10A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0676, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA108, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x00fa, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA106, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x04d9, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA104, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x12fe, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA102, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x01c1, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA100, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x047f, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA110, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x00ff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA016, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0020, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA012, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1ff8, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA014, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd13e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ff8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd15c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ff9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd16b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ffa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd15d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ffb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b0e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ffc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b0e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ffd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b0e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ffe}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1fff}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA164, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0972, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA166, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0968, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA168, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0a0b, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA16A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0a01, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA16C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b8a, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA16E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0bf9, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA170, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x125c, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA172, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3fff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA162, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x007F, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb820, 7 , 7 , 0x0 , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, +}; + +rtk_hwpatch_t rtl8264b_algxg_conf[] = { + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x80CD, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x25 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8065, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x15 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8175, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0xa2 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8176, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0xc5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8077, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x40 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8078, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0xcc , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8969, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x0f , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8957, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x2C , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8959, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x15 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x895A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x3E , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x895F, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x1E , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8165, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x22 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x827E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x68 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8167, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x33 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8013, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x39 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8fd7, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x14 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8fd5, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x1e , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x82D9, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x20 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x82DA, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x816E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0xab , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8159, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x58 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x815A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x99 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8139, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x25 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8125, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x67 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8126, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x89 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x827D, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x4c , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8205, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x4d , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8FD6, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x78 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8159, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x58 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x815A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x99 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x815B, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x77 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x815C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0xfb , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8125, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x67 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8126, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x89 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8127, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x77 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8128, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0xf7 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x80DF, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x51 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x80E0, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x94 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, +}; + +rtk_hwpatch_t rtl8264b_alg_giga_conf[] = { + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x80b8, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x4d , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x80b9, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xcc , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x80ba, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x80bb, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 13, 8 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x80bc, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x37 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x80bd, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 12, 8 , 0x0c , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x80be, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xBB , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x80bf, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xca , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x80c0, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x45 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x80c2, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x3b , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x80cc, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x16 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x80cd, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 10, 8 , 0x4 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x80ce, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x80cf, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 13, 8 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x80d0, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x53 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x80d1, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 12, 8 , 0x0a , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x80d2, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xB9 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x80d3, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xd0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x80d4, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x4a , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x80d6, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x35 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x80a4, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x0d , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x80a5, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xa4 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x80a6, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x59 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x80a7, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 13, 8 , 0x05 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x80a8, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xab , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x80a9, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 12, 8 , 0x0b , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x80aa, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xef , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x80ab, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xae , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x80ac, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xdf , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x80ae, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x28 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa836, 15, 15, 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa85c, 7 , 7 , 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa85c, 6 , 3 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8367, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x5d , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, +}; + +rtk_hwpatch_t rtl8264b_normal_conf[] = { + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbd92, 15, 0 , 0x002e, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbd94, 15, 0 , 0x8003, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbd96, 3 , 0 , 0xf , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbd96, 3 , 0 , 0x0 , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbd94, 15, 0 , 0x800b, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbd96, 3 , 0 , 0xf , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbd96, 3 , 0 , 0x0 , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x817D, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x07 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8426, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x46 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8428, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x46 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x84de, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x84e0, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x00fc, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x84e2, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf61a, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x84e4, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x58 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x84e6, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x84e8, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x00fc, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x84ea, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf61a, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x84ec, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x58 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x84ee, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x84f0, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x00fc, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x84f2, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf61a, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x84f4, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x58 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xae32, 5 , 5 , 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8018, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 12, 12, 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8fdf, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 0 , 0x0496, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8fe1, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 0 , 0x03a5, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8fe3, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 0 , 0x02e5, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8fe5, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 0 , 0x020d, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8fe7, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 0 , 0x0496, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8fe9, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 0 , 0x03a5, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8feb, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 0 , 0x02e5, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8fed, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 0 , 0x020d, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8fef, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 0 , 0x0496, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8ff1, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 0 , 0x03a5, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8ff3, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 0 , 0x02e5, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8ff5, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 0 , 0x020d, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8ff7, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 0 , 0x0496, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8ff9, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 0 , 0x03a5, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8ffb, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 0 , 0x02e5, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8ffd, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 0 , 0x020d, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb516, 6 , 0 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8fda, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x04 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8fdb, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x05 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8132, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x77 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8134, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x88 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x80ca, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x77 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x80cc, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x88 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8062, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x77 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8064, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x88 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x801E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0013, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, +}; + +rtk_hwpatch_t rtl8264b_dataram_conf[] = { + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb820, 7 , 7 , 0x0 , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb896, 0 , 0 , 0x0 , RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb892, 15, 8 , 0x0 , RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC037, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x33 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC038, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x2A , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC039, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x25 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC03A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x20 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC03B, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x1C , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC03C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x17 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC03D, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x13 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC075, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xA1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC076, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xB1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC077, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x2E , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC078, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x55 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC079, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x19 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC07A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xDC , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC07B, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xA0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC10B, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xD5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC10C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xD5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC10D, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xD5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC10E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xD5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC10F, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xD5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC110, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xD5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC149, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x08 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC14A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x08 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC14B, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x08 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC14C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x08 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC14D, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x08 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC14E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x08 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC166, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xEE , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC167, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xEE , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC168, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x07 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC169, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x09 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC16A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x0B , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC16B, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x0D , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC16C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x13 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC16D, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x0E , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC16E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x11 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC16F, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x14 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC170, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x17 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC171, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x15 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC172, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x10 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC173, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x0B , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC128, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xF7 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC129, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xF7 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC12A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xF8 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC12B, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xF7 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC12C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xF6 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC12D, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xF5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC12E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xF2 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC12F, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xF7 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC130, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xF5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC131, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xF2 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC132, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xF0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC133, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xF1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC134, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xF4 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC135, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xF7 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb896, 0 , 0 , 0x1 , RTK_PATCH_CMP_W , 0, 0, 0, 0}, +}; + +rtk_hwpatch_t rtl8264b_rtct_conf[] = { +}; + diff --git a/sources/rtk-be550/src/hal/phy/error.h b/sources/rtk-be550/src/hal/phy/error.h new file mode 100755 index 00000000..d99a996f --- /dev/null +++ b/sources/rtk-be550/src/hal/phy/error.h @@ -0,0 +1,165 @@ +/* + * SPDX-License-Identifier: GPL-2.0-only + * + * Copyright (c) 2023 Realtek Semiconductor Corp. All rights reserved. + */ + +#ifndef __COMMON_ERROR_H__ +#define __COMMON_ERROR_H__ + +/* + * Include Files + */ +#if defined(RTK_PHYDRV_IN_LINUX) + #include "type.h" +#else + #include +#endif +/* + * Data Type Declaration + */ +typedef enum rt_error_common_e +{ + RT_ERR_FAILED = -1, /* General Error */ + + /* 0x0000xxxx for common error code */ + RT_ERR_OK = 0, /* 0x00000000, OK */ + RT_ERR_INPUT = 0xF001, /* 0x0000F001, invalid input parameter */ + RT_ERR_UNIT_ID, /* 0x0000F002, invalid unit id */ + RT_ERR_PORT_ID, /* 0x0000F003, invalid port id */ + RT_ERR_PORT_MASK, /* 0x0000F004, invalid port mask */ + RT_ERR_PORT_LINKDOWN, /* 0x0000F005, link down port status */ + RT_ERR_ENTRY_INDEX, /* 0x0000F006, invalid entry index */ + RT_ERR_NULL_POINTER, /* 0x0000F007, input parameter is null pointer */ + RT_ERR_QUEUE_ID, /* 0x0000F008, invalid queue id */ + RT_ERR_QUEUE_NUM, /* 0x0000F009, invalid queue number */ + RT_ERR_BUSYWAIT_TIMEOUT, /* 0x0000F00a, busy watting time out */ + RT_ERR_MAC, /* 0x0000F00b, invalid mac address */ + RT_ERR_OUT_OF_RANGE, /* 0x0000F00c, input parameter out of range */ + RT_ERR_CHIP_NOT_SUPPORTED, /* 0x0000F00d, functions not supported by this chip model */ + RT_ERR_SMI, /* 0x0000F00e, SMI error */ + RT_ERR_NOT_INIT, /* 0x0000F00f, The module is not initial */ + RT_ERR_CHIP_NOT_FOUND, /* 0x0000F010, The chip can not found */ + RT_ERR_NOT_ALLOWED, /* 0x0000F011, actions not allowed by the function */ + RT_ERR_DRIVER_NOT_FOUND, /* 0x0000F012, The driver can not found */ + RT_ERR_SEM_LOCK_FAILED, /* 0x0000F013, Failed to lock semaphore */ + RT_ERR_SEM_UNLOCK_FAILED, /* 0x0000F014, Failed to unlock semaphore */ + RT_ERR_THREAD_EXIST, /* 0x0000F015, Thread exist */ + RT_ERR_THREAD_CREATE_FAILED, /* 0x0000F016, Thread create fail */ + RT_ERR_FWD_ACTION, /* 0x0000F017, Invalid forwarding Action */ + RT_ERR_IPV4_ADDRESS, /* 0x0000F018, Invalid IPv4 address */ + RT_ERR_IPV6_ADDRESS, /* 0x0000F019, Invalid IPv6 address */ + RT_ERR_PRIORITY, /* 0x0000F01a, Invalid Priority value */ + RT_ERR_FID, /* 0x0000F01b, invalid fid */ + RT_ERR_ENTRY_NOTFOUND, /* 0x0000F01c, specified entry not found */ + RT_ERR_DROP_PRECEDENCE, /* 0x0000F01d, invalid drop precedence */ + RT_ERR_NOT_FINISH, /* 0x0000F01e, Action not finish, still need to wait */ + RT_ERR_TIMEOUT, /* 0x0000F01f, Time out */ + RT_ERR_REG_ARRAY_INDEX_1, /* 0x0000F020, invalid index 1 of register array */ + RT_ERR_REG_ARRAY_INDEX_2, /* 0x0000F021, invalid index 2 of register array */ + RT_ERR_ETHER_TYPE, /* 0x0000F022, invalid ether type */ + RT_ERR_MBUF_PKT_NOT_AVAILABLE, /* 0x0000F023, mbuf->packet is not available */ + RT_ERR_QOS_INVLD_RSN, /* 0x0000F024, invalid pkt to CPU reason */ + RT_ERR_CB_FUNCTION_EXIST, /* 0x0000F025, Callback function exist */ + RT_ERR_CB_FUNCTION_FULL, /* 0x0000F026, Callback function number is full */ + RT_ERR_CB_FUNCTION_NOT_FOUND, /* 0x0000F027, Callback function can not found */ + RT_ERR_TBL_FULL, /* 0x0000F028, The table is full */ + RT_ERR_TRUNK_ID, /* 0x0000F029, invalid trunk id */ + RT_ERR_TYPE, /* 0x0000F02a, invalid type */ + RT_ERR_ENTRY_EXIST, /* 0x0000F02b, entry exists */ + RT_ERR_CHIP_UNDEFINED_VALUE, /* 0x0000F02c, chip returned an undefined value */ + RT_ERR_EXCEEDS_CAPACITY, /* 0x0000F02d, exceeds the capacity of hardware */ + RT_ERR_ENTRY_REFERRED, /* 0x0000F02e, entry is still being referred */ + RT_ERR_OPER_DENIED, /* 0x0000F02f, operation denied */ + RT_ERR_PORT_NOT_SUPPORTED, /* 0x0000F030, functions not supported by this port */ + RT_ERR_SOCKET, /* 0x0000F031, socket error */ + RT_ERR_MEM_ALLOC, /* 0x0000F032, insufficient memory resource */ + RT_ERR_ABORT, /* 0x0000F033, operation aborted */ + RT_ERR_DEV_ID, /* 0x0000F034, invalid device id */ + RT_ERR_DRIVER_NOT_SUPPORTED, /* 0x0000F035, functions not supported by this driver */ + RT_ERR_NOT_SUPPORTED, /* 0x0000F036, functions not supported */ + RT_ERR_SER, /* 0x0000F037, ECC or parity error */ + RT_ERR_MEM_NOT_ALIGN, /* 0x0000F038, memory address is not aligned */ + RT_ERR_SEM_FAKELOCK_OK, /* 0x0000F039, attach thread lock a semaphore which was already locked */ + RT_ERR_CHECK_FAILED, /* 0x0000F03a, check result is failed */ + + RT_ERR_COMMON_END = 0xFFFF /* The symbol is the latest symbol of common error */ +} rt_error_common_t; + +/* + * Macro Definition + */ +#define RT_PARAM_CHK(expr, errCode)\ +do {\ + if ((int32)(expr)) {\ + return errCode; \ + }\ +} while (0) + +#define RT_PARAM_CHK_EHDL(expr, errCode, err_hdl)\ +do {\ + if ((int32)(expr)) {\ + {err_hdl}\ + return errCode; \ + }\ +} while (0) + +#define RT_INIT_CHK(state)\ +do {\ + if (INIT_COMPLETED != (state)) {\ + return RT_ERR_NOT_INIT;\ + }\ +} while (0) + +#define RT_INIT_REENTRY_CHK(state)\ +do {\ + if (INIT_COMPLETED == (state)) {\ + osal_printf(" %s had already been initialized!\n", __FUNCTION__);\ + return RT_ERR_OK;\ + }\ +} while (0) + +#define RT_INIT_REENTRY_CHK_NO_WARNING(state)\ + do {\ + if (INIT_COMPLETED == (state)) {\ + return RT_ERR_OK;\ + }\ + } while (0) + +#define RT_ERR_CHK(op, ret)\ +do {\ + if ((ret = (op)) != RT_ERR_OK)\ + return ret;\ +} while(0) + +#define RT_ERR_HDL(op, errHandle, ret)\ +do {\ + if ((ret = (op)) != RT_ERR_OK)\ + goto errHandle;\ +} while(0) + +#define RT_ERR_CHK_EHDL(op, ret, err_hdl)\ +do {\ + if ((ret = (op)) != RT_ERR_OK)\ + {\ + {err_hdl}\ + return ret;\ + }\ +} while(0) + +#define RT_NULL_HDL(pointer, err_label)\ +do {\ + if (NULL == (pointer)) {\ + goto err_label;\ + }\ +} while (0) + +#define RT_ERR_VOID_CHK(op, ret)\ +do {\ + if ((ret = (op)) != RT_ERR_OK) {\ + osal_printf("Fail in %s %d, ret %x!\n", __FUNCTION__, __LINE__, ret);\ + return ;}\ +} while(0) + +#endif /* __COMMON_ERROR_H__ */ + diff --git a/sources/rtk-be550/src/hal/phy/phy_patch.c b/sources/rtk-be550/src/hal/phy/phy_patch.c new file mode 100755 index 00000000..f9af3ffe --- /dev/null +++ b/sources/rtk-be550/src/hal/phy/phy_patch.c @@ -0,0 +1,179 @@ +/* + * SPDX-License-Identifier: GPL-2.0-only + * + * Copyright (c) 2023 Realtek Semiconductor Corp. All rights reserved. + */ + +/* + * Include Files + */ +#if defined(RTK_PHYDRV_IN_LINUX) + #include "rtk_osal.h" +#else + #include + #include + #include + #include + #include +#endif + +/* + * Function Declaration + */ +uint8 phy_patch_op_translate(uint8 patch_mode, uint8 patch_op, uint8 compare_op) +{ + if (patch_mode != PHY_PATCH_MODE_CMP) + { + return patch_op; + } + else + { + switch (compare_op) + { + case RTK_PATCH_CMP_WS: + return RTK_PATCH_OP_SKIP; + case RTK_PATCH_CMP_W: + case RTK_PATCH_CMP_WC: + case RTK_PATCH_CMP_SWC: + default: + return RTK_PATCH_OP_TO_CMP(patch_op, compare_op); + } + } +} + +int32 phy_patch_op(rt_phy_patch_db_t *pPhy_patchDb, uint32 unit, rtk_port_t port, uint8 portOffset, uint8 patch_op, uint16 portmask, uint16 pagemmd, uint16 addr, uint8 msb, uint8 lsb, uint16 data, uint8 patch_mode) +{ + rtk_hwpatch_t op; + + op.patch_op = patch_op; + op.portmask = portmask; + op.pagemmd = pagemmd; + op.addr = addr; + op.msb = msb; + op.lsb = lsb; + op.data = data; + op.compare_op = RTK_PATCH_CMP_W; + + return pPhy_patchDb->fPatch_op(unit, port, portOffset, &op, patch_mode); +} + +static int32 _phy_patch_process(uint32 unit, rtk_port_t port, uint8 portOffset, rtk_hwpatch_t *pPatch, int32 size, uint8 patch_mode) +{ + int32 i = 0; + int32 ret = 0; + int32 chk_ret = RT_ERR_OK; + int32 n; + rtk_hwpatch_t *patch = pPatch; + rt_phy_patch_db_t *pPatchDb = NULL; + + PHYPATCH_DB_GET(unit, port, pPatchDb); + + if (size <= 0) + { + return RT_ERR_OK; + } + n = size / sizeof(rtk_hwpatch_t); + + for (i = 0; i < n; i++) + { + ret = pPatchDb->fPatch_op(unit, port, portOffset, &patch[i], patch_mode); + if ((ret != RT_ERR_ABORT) && (ret != RT_ERR_OK)) + { + if ((ret == RT_ERR_CHECK_FAILED) && (patch_mode == PHY_PATCH_MODE_CMP)) + { + osal_printf("PATCH CHECK: Failed entry:%u|%u|0x%X|0x%X|%u|%u|0x%X\n", + i + 1, patch[i].patch_op, patch[i].pagemmd, patch[i].addr, patch[i].msb, patch[i].lsb, patch[i].data); + chk_ret = RT_ERR_CHECK_FAILED; + continue; + } + else + { + RT_LOG(LOG_MAJOR_ERR, (MOD_HAL | MOD_PHY), "U%u P%u %s failed! %u[%u][0x%X][0x%X][0x%X] ret=0x%X\n", unit, port, __FUNCTION__, + i+1, patch[i].patch_op, patch[i].pagemmd, patch[i].addr, patch[i].data, ret); + return ret; + } + } + + } + return (chk_ret == RT_ERR_CHECK_FAILED) ? chk_ret : RT_ERR_OK; +} + +/* Function Name: + * phy_patch + * Description: + * apply initial patch data to PHY + * Input: + * unit - unit id + * port - port id + * portOffset - the index offset of port based the base port in the PHY chip + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_CHECK_FAILED + * RT_ERR_NOT_SUPPORTED + * Note: + * None + */ +int32 phy_patch(uint32 unit, rtk_port_t port, uint8 portOffset, uint8 patch_mode) +{ + int32 ret = RT_ERR_OK; + int32 chk_ret = RT_ERR_OK; + uint32 i = 0; + uint8 patch_type = 0; + rt_phy_patch_db_t *pPatchDb = NULL; + rtk_hwpatch_seq_t *table = NULL; + + PHYPATCH_DB_GET(unit, port, pPatchDb); + + if ((pPatchDb == NULL) || (pPatchDb->fPatch_op == NULL) || (pPatchDb->fPatch_flow == NULL)) + { + RT_LOG(LOG_MAJOR_ERR, (MOD_HAL | MOD_PHY), "U%u P%u phy_patch, db is NULL\n", unit, port); + return RT_ERR_DRIVER_NOT_SUPPORTED; + } + + if (patch_mode == PHY_PATCH_MODE_CMP) + { + table = pPatchDb->cmp_table; + } + else + { + table = pPatchDb->seq_table; + } + RT_LOG(LOG_INFO, (MOD_HAL | MOD_PHY), "phy_patch: U%u P%u portOffset:%u patch_mode:%u\n", unit, port, portOffset, patch_mode); + + for (i = 0; i < RTK_PATCH_SEQ_MAX; i++) + { + patch_type = table[i].patch_type; + RT_LOG(LOG_INFO, (MOD_HAL | MOD_PHY), "phy_patch: table[%u] patch_type:%u\n", i, patch_type); + + if (RTK_PATCH_TYPE_IS_DATA(patch_type)) + { + ret = _phy_patch_process(unit, port, portOffset, table[i].patch.data.conf, table[i].patch.data.size, patch_mode); + + if (ret == RT_ERR_CHECK_FAILED) + chk_ret = ret; + else if (ret != RT_ERR_OK) + { + RT_LOG(LOG_MAJOR_ERR, (MOD_HAL | MOD_PHY), "U%u P%u patch_mode:%u id:%u patch-%u failed. ret:0x%X\n", unit, port, patch_mode, i, patch_type, ret); + return ret; + } + } + else if (RTK_PATCH_TYPE_IS_FLOW(patch_type)) + { + RT_ERR_CHK_EHDL(pPatchDb->fPatch_flow(unit, port, portOffset, table[i].patch.flow_id, patch_mode), + ret, RT_LOG(LOG_MAJOR_ERR, (MOD_HAL | MOD_PHY), "U%u P%u patch_mode:%u id:%u patch-%u failed. ret:0x%X\n", unit, port, patch_mode, i, patch_type, ret);); + } + else + { + break; + } + } + + return (chk_ret == RT_ERR_CHECK_FAILED) ? chk_ret : RT_ERR_OK; +} + + + + diff --git a/sources/rtk-be550/src/hal/phy/phy_patch.h b/sources/rtk-be550/src/hal/phy/phy_patch.h new file mode 100755 index 00000000..c2b7b127 --- /dev/null +++ b/sources/rtk-be550/src/hal/phy/phy_patch.h @@ -0,0 +1,174 @@ +/* + * SPDX-License-Identifier: GPL-2.0-only + * + * Copyright (c) 2023 Realtek Semiconductor Corp. All rights reserved. + */ + +#ifndef __HAL_PHY_PATCH_H__ +#define __HAL_PHY_PATCH_H__ + +/* + * Include Files + */ +#if defined(RTK_PHYDRV_IN_LINUX) + #include "rtk_phylib_def.h" +#else + #include + #include +#endif + +/* + * Symbol Definition + */ +#define PHYPATCH_PHYCTRL_IN_HALCTRL 0 /* 3.6.x: 1 ,4.0.x: 1, 4.1.x+: 0 */ +#define PHYPATCH_FMAILY_IN_HWP 0 /* 3.6.x: 1 ,4.0.x: 0, 4.1.x+: 0 */ +#define PHY_PATCH_MODE_BCAST_DEFAULT PHY_PATCH_MODE_BCAST /* 3.6.x: PHY_PATCH_MODE_BCAST_BUS ,4.0.x+: PHY_PATCH_MODE_BCAST */ + +#define PHY_PATCH_MODE_NORMAL 0 +#define PHY_PATCH_MODE_CMP 1 +#define PHY_PATCH_MODE_BCAST 2 +#define PHY_PATCH_MODE_BCAST_BUS 3 + +#define RTK_PATCH_CMP_W 0 /* write */ +#define RTK_PATCH_CMP_WC 1 /* compare */ +#define RTK_PATCH_CMP_SWC 2 /* sram compare */ +#define RTK_PATCH_CMP_WS 3 /* skip */ + +#define RTK_PATCH_OP_SECTION_SIZE 50 +#define RTK_PATCH_OP_TO_CMP(_op, _cmp) (_op + (RTK_PATCH_OP_SECTION_SIZE * _cmp)) +/* 0~49 normal op */ +#define RTK_PATCH_OP_PHY 0 +#define RTK_PATCH_OP_PHYOCP 1 +#define RTK_PATCH_OP_TOP 2 +#define RTK_PATCH_OP_TOPOCP 3 +#define RTK_PATCH_OP_PSDS0 4 +#define RTK_PATCH_OP_PSDS1 5 +#define RTK_PATCH_OP_MSDS 6 +#define RTK_PATCH_OP_MAC 7 + +/* 50~99 normal op for compare */ +#define RTK_PATCH_OP_CMP_PHY RTK_PATCH_OP_TO_CMP(RTK_PATCH_OP_PHY , RTK_PATCH_CMP_WC) +#define RTK_PATCH_OP_CMP_PHYOCP RTK_PATCH_OP_TO_CMP(RTK_PATCH_OP_PHYOCP , RTK_PATCH_CMP_WC) +#define RTK_PATCH_OP_CMP_TOP RTK_PATCH_OP_TO_CMP(RTK_PATCH_OP_TOP , RTK_PATCH_CMP_WC) +#define RTK_PATCH_OP_CMP_TOPOCP RTK_PATCH_OP_TO_CMP(RTK_PATCH_OP_TOPOCP , RTK_PATCH_CMP_WC) +#define RTK_PATCH_OP_CMP_PSDS0 RTK_PATCH_OP_TO_CMP(RTK_PATCH_OP_PSDS0 , RTK_PATCH_CMP_WC) +#define RTK_PATCH_OP_CMP_PSDS1 RTK_PATCH_OP_TO_CMP(RTK_PATCH_OP_PSDS1 , RTK_PATCH_CMP_WC) +#define RTK_PATCH_OP_CMP_MSDS RTK_PATCH_OP_TO_CMP(RTK_PATCH_OP_MSDS , RTK_PATCH_CMP_WC) +#define RTK_PATCH_OP_CMP_MAC RTK_PATCH_OP_TO_CMP(RTK_PATCH_OP_MAC , RTK_PATCH_CMP_WC) + +/* 100~149 normal op for sram compare */ +#define RTK_PATCH_OP_CMP_SRAM_PHY RTK_PATCH_OP_TO_CMP(RTK_PATCH_OP_PHY , RTK_PATCH_CMP_SWC) +#define RTK_PATCH_OP_CMP_SRAM_PHYOCP RTK_PATCH_OP_TO_CMP(RTK_PATCH_OP_PHYOCP , RTK_PATCH_CMP_SWC) +#define RTK_PATCH_OP_CMP_SRAM_TOP RTK_PATCH_OP_TO_CMP(RTK_PATCH_OP_TOP , RTK_PATCH_CMP_SWC) +#define RTK_PATCH_OP_CMP_SRAM_TOPOCP RTK_PATCH_OP_TO_CMP(RTK_PATCH_OP_TOPOCP , RTK_PATCH_CMP_SWC) +#define RTK_PATCH_OP_CMP_SRAM_PSDS0 RTK_PATCH_OP_TO_CMP(RTK_PATCH_OP_PSDS0 , RTK_PATCH_CMP_SWC) +#define RTK_PATCH_OP_CMP_SRAM_PSDS1 RTK_PATCH_OP_TO_CMP(RTK_PATCH_OP_PSDS1 , RTK_PATCH_CMP_SWC) +#define RTK_PATCH_OP_CMP_SRAM_MSDS RTK_PATCH_OP_TO_CMP(RTK_PATCH_OP_MSDS , RTK_PATCH_CMP_SWC) +#define RTK_PATCH_OP_CMP_SRAM_MAC RTK_PATCH_OP_TO_CMP(RTK_PATCH_OP_MAC , RTK_PATCH_CMP_SWC) + +/* 200~255 control op */ +#define RTK_PATCH_OP_DELAY_MS 200 +#define RTK_PATCH_OP_SKIP 255 + + +/* + patch type PHY_PATCH_TYPE_NONE => empty + patch type: PHY_PATCH_TYPE_TOP ~ (PHY_PATCH_TYPE_END-1) => data array + patch type: PHY_PATCH_TYPE_END ~ (PHY_PATCH_TYPE_END + RTK_PATCH_TYPE_FLOW_MAX) => flow +*/ +#define RTK_PATCH_TYPE_IS_DATA(_patch_type) (_patch_type > PHY_PATCH_TYPE_NONE && _patch_type < PHY_PATCH_TYPE_END) +#define RTK_PATCH_TYPE_IS_FLOW(_patch_type) (_patch_type >= PHY_PATCH_TYPE_END && _patch_type <= (PHY_PATCH_TYPE_END + RTK_PATCH_TYPE_FLOWID_MAX)) + + +/* + * Macro Definition + */ +#if PHYPATCH_PHYCTRL_IN_HALCTRL + #define PHYPATCH_DB_GET(_unit, _port, _pPatchDb) \ + do {\ + hal_control_t *pHalCtrl = NULL;\ + if ((pHalCtrl = hal_ctrlInfo_get(_unit)) == NULL)\ + return RT_ERR_FAILED;\ + _pPatchDb = (pHalCtrl->pPhy_ctrl[_port]->pPhy_patchDb);\ + } while(0) +#else + #if defined(RTK_PHYDRV_IN_LINUX) + #else + #include + #include + #endif + #define PHYPATCH_DB_GET(_unit, _port, _pPatchDb) \ + do {\ + rt_phyctrl_t *pPhyCtrl = NULL;\ + if ((pPhyCtrl = phy_phyctrl_get(_unit, _port)) == NULL)\ + return RT_ERR_FAILED;\ + _pPatchDb = (pPhyCtrl->pPhy_patchDb);\ + } while(0) +#endif + +#if PHYPATCH_FMAILY_IN_HWP + #define PHYPATCH_IS_RTKSDS(_unit) (HWP_9300_FAMILY_ID(_unit) || HWP_9310_FAMILY_ID(_unit)) +#else + #define PHYPATCH_IS_RTKSDS(_unit) (RTK_9300_FAMILY_ID(_unit) || RTK_9310_FAMILY_ID(_unit) || RTK_9311B_FAMILY_ID(_unit) || RTK_9330_FAMILY_ID(_unit)) +#endif + +#define PHYPATCH_TABLE_ASSIGN(_pPatchDb, _table, _idx, _patch_type, _para) \ + do {\ + if (RTK_PATCH_TYPE_IS_DATA(_patch_type)) {\ + _pPatchDb->_table[_idx].patch_type = _patch_type;\ + _pPatchDb->_table[_idx].patch.data.conf = _para;\ + _pPatchDb->_table[_idx].patch.data.size = sizeof(_para);\ + }\ + else if (RTK_PATCH_TYPE_IS_FLOW(_patch_type)) {\ + _pPatchDb->_table[_idx].patch_type = _patch_type;\ + _pPatchDb->_table[_idx].patch.flow_id = _patch_type;\ + }\ + else {\ + _pPatchDb->_table[_idx].patch_type = PHY_PATCH_TYPE_NONE;\ + }\ + } while(0) +#define PHYPATCH_SEQ_TABLE_ASSIGN(_pPatchDb, _idx, _patch_type, _para) PHYPATCH_TABLE_ASSIGN(_pPatchDb, seq_table, _idx, _patch_type, _para) +#define PHYPATCH_CMP_TABLE_ASSIGN(_pPatchDb, _idx, _patch_type, _para) PHYPATCH_TABLE_ASSIGN(_pPatchDb, cmp_table, _idx, _patch_type, _para) + +#define PHYPATCH_COMPARE(_mmdpage, _reg, _msb, _lsb, _exp, _real, _mask) \ + do {\ + uint32 _rData = REG32_FIELD_GET(_real, _lsb, _mask);\ + if (_exp != _rData) {\ + osal_printf("PATCH CHECK: %u(0x%X).%u(0x%X)[%u:%u] = 0x%X (!= 0x%X)\n", _mmdpage, _mmdpage, _reg, _reg, _msb, _lsb, _rData, _exp);\ + return RT_ERR_CHECK_FAILED;\ + }\ + } while (0) + +/* + * Function Declaration + */ + +extern uint8 phy_patch_op_translate(uint8 patch_mode, uint8 patch_op, uint8 compare_op); +extern int32 phy_patch_op(rt_phy_patch_db_t *pPhy_patchDb, uint32 unit, rtk_port_t port, uint8 portOffset, + uint8 patch_op, uint16 portmask, uint16 pagemmd, uint16 addr, uint8 msb, uint8 lsb, uint16 data, + uint8 patch_mode); + + +/* Function Name: + * phy_patch + * Description: + * apply initial patch data to PHY + * Input: + * unit - unit id + * port - port id + * portOffset - the index offset of port based the base port in the PHY chip + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_CHECK_FAILED + * RT_ERR_NOT_SUPPORTED + * Note: + * None + */ +extern int32 phy_patch(uint32 unit, rtk_port_t port, uint8 portOffset, uint8 patch_mode); + + + +#endif /* __HAL_PHY_PATCH_H__ */ diff --git a/sources/rtk-be550/src/hal/phy/phy_rtl826xb_patch.c b/sources/rtk-be550/src/hal/phy/phy_rtl826xb_patch.c new file mode 100755 index 00000000..98a9609f --- /dev/null +++ b/sources/rtk-be550/src/hal/phy/phy_rtl826xb_patch.c @@ -0,0 +1,1123 @@ +/* + * SPDX-License-Identifier: GPL-2.0-only + * + * Copyright (c) 2023 Realtek Semiconductor Corp. All rights reserved. + */ + +/* + * Include Files + */ + +/* set LOW_POWER_INIT_PATCH to 1 to initial chip in low power consumption mode + and supported max cable length will downgrade to 50M */ +#define LOW_POWER_INIT_PATCH 0 + +#if defined(RTK_PHYDRV_IN_LINUX) + #include + #include "phy_rtl826xb_patch.h" + #include "construct/conf_rtl8264b.c" + #if LOW_POWER_INIT_PATCH + #include "construct/conf_rtl8261n_c_lp.c" + #else + #include "construct/conf_rtl8261n_c.c" + #endif +#else + #include + #include + #include + #include + #include + #include + #include + #include + #include + #include + #include + #include + #if defined(CONFIG_SDK_RTL826XB) + #include + #include + #include + #endif +#endif +/* + * Symbol Definition + */ +#define PHY_PATCH_WAIT_TIMEOUT 10000000 + +#define PHY_PATCH_LOG LOG_INFO + +/* + * Data Declaration + */ + +/* + * Macro Declaration + */ + +/* + * Function Declaration + */ +static uint16 _phy_rtl826xb_mmd_convert(uint16 page, uint16 addr) +{ + uint16 reg = 0; + if (addr < 16) + { + reg = 0xA400 + (page * 2); + } + else if (addr < 24) + { + reg = (16*page) + ((addr - 16) * 2); + } + else + { + reg = 0xA430 + ((addr - 24) * 2); + } + return reg; +} + +int32 +_phy_rtl826xb_patch_wait(uint32 unit, rtk_port_t port, uint32 mmdAddr, uint32 mmdReg, uint32 data, uint32 mask, uint8 patch_mode) +{ + int32 ret = 0; + uint32 rData = 0; + uint32 cnt = 0; + WAIT_COMPLETE_VAR() + + rtk_port_t p = 0; + uint8 smiBus = HWP_PORT_SMI(unit, port); + uint32 phyChip = HWP_PHY_MODEL_BY_PORT(unit, port); + uint8 bcast_phyad = HWP_PHY_ADDR(unit, port); + + if (patch_mode == PHY_PATCH_MODE_BCAST_BUS) + { + if ((ret = phy_826xb_ctrl_set(unit, port, RTK_PHY_CTRL_MIIM_BCAST, 0)) != RT_ERR_OK) + { + RT_LOG(LOG_MAJOR_ERR, (MOD_HAL | MOD_PHY), "U%u P%u 826XB patch wait disable broadcast failed! 0x%X\n", unit, p, ret); + return ret; + } + + HWP_PORT_TRAVS_EXCEPT_CPU(unit, p) + { + if ((HWP_PORT_SMI(unit, p) == smiBus) && (HWP_PHY_MODEL_BY_PORT(unit, p) == phyChip)) + { + WAIT_COMPLETE(PHY_PATCH_WAIT_TIMEOUT) + { + if ((ret = phy_common_general_reg_mmd_get(unit, p, mmdAddr, mmdReg, &rData)) != RT_ERR_OK) + { + return ret; + } + ++cnt; + + if ((rData & mask) == data) + break; + + //osal_time_udelay(10); + } + + if (WAIT_COMPLETE_IS_TIMEOUT()) + { + RT_LOG(LOG_MAJOR_ERR, (MOD_HAL | MOD_PHY), "U%u P%u 826XB patch wait[%u,0x%X,0x%X,0x%X]:0x%X cnt:%u\n", unit, p, mmdAddr, mmdReg, data, mask, rData, cnt); + return RT_ERR_TIMEOUT; + } + } + } + + osal_time_mdelay(1); + //for port in same SMI bus, set mdio broadcast ENABLE + HWP_PORT_TRAVS_EXCEPT_CPU(unit, p) + { + if ((HWP_PORT_SMI(unit, p) == smiBus) && (HWP_PHY_MODEL_BY_PORT(unit, p) == phyChip)) + { + if ((ret = phy_826xb_ctrl_set(unit, p, RTK_PHY_CTRL_MIIM_BCAST_PHYAD, (uint32)bcast_phyad)) != RT_ERR_OK) + { + RT_LOG(LOG_MAJOR_ERR, (MOD_HAL | MOD_PHY), "U%u P%u 826XB patch wait set broadcast PHYAD failed! 0x%X\n", unit, p, ret); + return ret; + } + + if ((ret = phy_826xb_ctrl_set(unit, p, RTK_PHY_CTRL_MIIM_BCAST, 1)) != RT_ERR_OK) + { + RT_LOG(LOG_MAJOR_ERR, (MOD_HAL | MOD_PHY), "U%u P%u 826XB patch wait enable broadcast failed! 0x%X\n", unit, p, ret); + return ret; + } + } + } + } + else if (patch_mode == PHY_PATCH_MODE_BCAST) + { + if ((ret = phy_826xb_ctrl_set(unit, port, RTK_PHY_CTRL_MIIM_BCAST, 0)) != RT_ERR_OK) + { + RT_LOG(LOG_MAJOR_ERR, (MOD_HAL | MOD_PHY), "U%u P%u 826x patch wait disable broadcast failed! 0x%X\n", unit, p, ret); + return ret; + } + + HWP_PORT_TRAVS_EXCEPT_CPU(unit, p) + { + if (HWP_PHY_BASE_MACID(unit, p) == HWP_PHY_BASE_MACID(unit, port)) + { + WAIT_COMPLETE(PHY_PATCH_WAIT_TIMEOUT) + { + if ((ret = phy_common_general_reg_mmd_get(unit, p, mmdAddr, mmdReg, &rData)) != RT_ERR_OK) + { + return ret; + } + ++cnt; + + if ((rData & mask) == data) + break; + //osal_time_udelay(10); + } + + if (WAIT_COMPLETE_IS_TIMEOUT()) + { + RT_LOG(LOG_MAJOR_ERR, (MOD_HAL | MOD_PHY), "U%u P%u 826x patch wait[%u,0x%X,0x%X,0x%X]:0x%X cnt:%u\n", unit, p, mmdAddr, mmdReg, data, mask, rData, cnt); + return RT_ERR_TIMEOUT; + } + } + } + + osal_time_mdelay(1); + //for port in same PHY, set mdio broadcast ENABLE + HWP_PORT_TRAVS_EXCEPT_CPU(unit, p) + { + if (HWP_PHY_BASE_MACID(unit, p) == HWP_PHY_BASE_MACID(unit, port)) + { + if ((ret = phy_826xb_ctrl_set(unit, p, RTK_PHY_CTRL_MIIM_BCAST_PHYAD, (uint32)bcast_phyad)) != RT_ERR_OK) + { + RT_LOG(LOG_MAJOR_ERR, (MOD_HAL | MOD_PHY), "U%u P%u 826XB patch wait set broadcast PHYAD failed! 0x%X\n", unit, p, ret); + return ret; + } + + if ((ret = phy_826xb_ctrl_set(unit, p, RTK_PHY_CTRL_MIIM_BCAST, 1)) != RT_ERR_OK) + { + RT_LOG(LOG_MAJOR_ERR, (MOD_HAL | MOD_PHY), "U%u P%u 826XB patch wait enable broadcast failed! 0x%X\n", unit, p, ret); + return ret; + } + } + } + } + else + { + WAIT_COMPLETE(PHY_PATCH_WAIT_TIMEOUT) + { + if ((ret = phy_common_general_reg_mmd_get(unit, port, mmdAddr, mmdReg, &rData)) != RT_ERR_OK) + return ret; + + ++cnt; + if ((rData & mask) == data) + break; + + osal_time_mdelay(1); + } + + if (WAIT_COMPLETE_IS_TIMEOUT()) + { + RT_LOG(LOG_MAJOR_ERR, (MOD_HAL | MOD_PHY), "U%u P%u 826XB patch wait[%u,0x%X,0x%X,0x%X]:0x%X cnt:%u\n", unit, port, mmdAddr, mmdReg, data, mask, rData, cnt); + return RT_ERR_TIMEOUT; + } + } + + return RT_ERR_OK; +} + +int32 +_phy_rtl826xb_patch_wait_not_equal(uint32 unit, rtk_port_t port, uint32 mmdAddr, uint32 mmdReg, uint32 data, uint32 mask, uint8 patch_mode) +{ + int32 ret = 0; + uint32 rData = 0; + uint32 cnt = 0; + WAIT_COMPLETE_VAR() + + rtk_port_t p = 0; + uint8 smiBus = HWP_PORT_SMI(unit, port); + uint32 phyChip = HWP_PHY_MODEL_BY_PORT(unit, port); + uint8 bcast_phyad = HWP_PHY_ADDR(unit, port); + + if (patch_mode == PHY_PATCH_MODE_BCAST_BUS) + { + if ((ret = phy_826xb_ctrl_set(unit, port, RTK_PHY_CTRL_MIIM_BCAST, 0)) != RT_ERR_OK) + { + RT_LOG(LOG_MAJOR_ERR, (MOD_HAL | MOD_PHY), "U%u P%u 826XB patch wait disable broadcast failed! 0x%X\n", unit, p, ret); + return ret; + } + + HWP_PORT_TRAVS_EXCEPT_CPU(unit, p) + { + if ((HWP_PORT_SMI(unit, p) == smiBus) && (HWP_PHY_MODEL_BY_PORT(unit, p) == phyChip)) + { + WAIT_COMPLETE(PHY_PATCH_WAIT_TIMEOUT) + { + if ((ret = phy_common_general_reg_mmd_get(unit, p, mmdAddr, mmdReg, &rData)) != RT_ERR_OK) + { + return ret; + } + ++cnt; + + if ((rData & mask) != data) + break; + + //osal_time_udelay(10); + } + if (WAIT_COMPLETE_IS_TIMEOUT()) + { + RT_LOG(LOG_MAJOR_ERR, (MOD_HAL | MOD_PHY), "U%u P%u 826XB patch wait[%u,0x%X,0x%X,0x%X]:0x%X cnt:%u\n", unit, p, mmdAddr, mmdReg, data, mask, rData, cnt); + return RT_ERR_TIMEOUT; + } + } + } + + osal_time_mdelay(1); + //for port in same SMI bus, set mdio broadcast ENABLE + HWP_PORT_TRAVS_EXCEPT_CPU(unit, p) + { + if ((HWP_PORT_SMI(unit, p) == smiBus) && (HWP_PHY_MODEL_BY_PORT(unit, p) == phyChip)) + { + if ((ret = phy_826xb_ctrl_set(unit, p, RTK_PHY_CTRL_MIIM_BCAST_PHYAD, (uint32)bcast_phyad)) != RT_ERR_OK) + { + RT_LOG(LOG_MAJOR_ERR, (MOD_HAL | MOD_PHY), "U%u P%u 826XB patch wait set broadcast PHYAD failed! 0x%X\n", unit, p, ret); + return ret; + } + + if ((ret = phy_826xb_ctrl_set(unit, p, RTK_PHY_CTRL_MIIM_BCAST, 1)) != RT_ERR_OK) + { + RT_LOG(LOG_MAJOR_ERR, (MOD_HAL | MOD_PHY), "U%u P%u 826XB patch wait enable broadcast failed! 0x%X\n", unit, p, ret); + return ret; + } + } + } + } + else if (patch_mode == PHY_PATCH_MODE_BCAST) + { + if ((ret = phy_826xb_ctrl_set(unit, port, RTK_PHY_CTRL_MIIM_BCAST, 0)) != RT_ERR_OK) + { + RT_LOG(LOG_MAJOR_ERR, (MOD_HAL | MOD_PHY), "U%u P%u 826x patch wait disable broadcast failed! 0x%X\n", unit, p, ret); + return ret; + } + + HWP_PORT_TRAVS_EXCEPT_CPU(unit, p) + { + if (HWP_PHY_BASE_MACID(unit, p) == HWP_PHY_BASE_MACID(unit, port)) + { + WAIT_COMPLETE(PHY_PATCH_WAIT_TIMEOUT) + { + if ((ret = phy_common_general_reg_mmd_get(unit, p, mmdAddr, mmdReg, &rData)) != RT_ERR_OK) + { + return ret; + } + ++cnt; + + if (((rData & mask) != data)) + break; + + //osal_time_udelay(10); + } + + if (WAIT_COMPLETE_IS_TIMEOUT()) + { + RT_LOG(LOG_MAJOR_ERR, (MOD_HAL | MOD_PHY), "U%u P%u 826XB patch wait[%u,0x%X,0x%X,0x%X]:0x%X cnt:%u\n", unit, p, mmdAddr, mmdReg, data, mask, rData, cnt); + return RT_ERR_TIMEOUT; + } + } + } + + osal_time_mdelay(1); + //for port in same PHY, set mdio broadcast ENABLE + HWP_PORT_TRAVS_EXCEPT_CPU(unit, p) + { + if (HWP_PHY_BASE_MACID(unit, p) == HWP_PHY_BASE_MACID(unit, port)) + { + if ((ret = phy_826xb_ctrl_set(unit, p, RTK_PHY_CTRL_MIIM_BCAST_PHYAD, (uint32)bcast_phyad)) != RT_ERR_OK) + { + RT_LOG(LOG_MAJOR_ERR, (MOD_HAL | MOD_PHY), "U%u P%u 826XB patch wait set broadcast PHYAD failed! 0x%X\n", unit, p, ret); + return ret; + } + + if ((ret = phy_826xb_ctrl_set(unit, p, RTK_PHY_CTRL_MIIM_BCAST, 1)) != RT_ERR_OK) + { + RT_LOG(LOG_MAJOR_ERR, (MOD_HAL | MOD_PHY), "U%u P%u 826XB patch wait enable broadcast failed! 0x%X\n", unit, p, ret); + return ret; + } + } + } + } + else + { + WAIT_COMPLETE(PHY_PATCH_WAIT_TIMEOUT) + { + if ((ret = phy_common_general_reg_mmd_get(unit, port, mmdAddr, mmdReg, &rData)) != RT_ERR_OK) + return ret; + + ++cnt; + if ((rData & mask) != data) + break; + + osal_time_mdelay(1); + } + if (WAIT_COMPLETE_IS_TIMEOUT()) + { + RT_LOG(LOG_MAJOR_ERR, (MOD_HAL | MOD_PHY), "U%u P%u 826xb patch wait[%u,0x%X,0x%X,0x%X]:0x%X cnt:%u\n", unit, port, mmdAddr, mmdReg, data, mask, rData, cnt); + return RT_ERR_TIMEOUT; + } + + } + + return RT_ERR_OK; +} + +int32 +_phy_rtl826xb_patch_top_get(uint32 unit, rtk_port_t port, uint32 topPage, uint32 topReg, uint32 *pData) +{ + int32 ret = 0; + uint32 rData = 0; + uint32 topAddr = (topPage * 8) + (topReg - 16); + + if ((ret = phy_common_general_reg_mmd_get(unit, port, PHY_MMD_VEND1, topAddr, &rData)) != RT_ERR_OK) + return ret; + *pData = rData; + return RT_ERR_OK; +} + +int32 +_phy_rtl826xb_patch_top_set(uint32 unit, rtk_port_t port, uint32 topPage, uint32 topReg, uint32 wData) +{ + int32 ret = 0; + uint32 topAddr = (topPage * 8) + (topReg - 16); + if ((ret = phy_common_general_reg_mmd_set(unit, port, PHY_MMD_VEND1, topAddr, wData)) != RT_ERR_OK) + return ret; + return RT_ERR_OK; +} + +int32 +_phy_rtl826xb_patch_sds_get(uint32 unit, rtk_port_t port, uint32 sdsPage, uint32 sdsReg, uint32 *pData) +{ + int32 ret = 0; + uint32 rData = 0; + uint32 sdsAddr = 0x8000 + (sdsReg << 6) + sdsPage; + + if ((ret = _phy_rtl826xb_patch_top_set(unit, port, 40, 19, sdsAddr)) != RT_ERR_OK) + return ret; + if ((ret = _phy_rtl826xb_patch_top_get(unit, port, 40, 18, &rData)) != RT_ERR_OK) + return ret; + *pData = rData; + return _phy_rtl826xb_patch_wait(unit, port, PHY_MMD_VEND1, 0x143, 0, BIT_15, PHY_PATCH_MODE_NORMAL); +} + +int32 +_phy_rtl826xb_patch_sds_set(uint32 unit, rtk_port_t port, uint32 sdsPage, uint32 sdsReg, uint32 wData, uint8 patch_mode) +{ + int32 ret = 0; + uint32 sdsAddr = 0x8800 + (sdsReg << 6) + sdsPage; + + if ((ret = _phy_rtl826xb_patch_top_set(unit, port, 40, 17, wData)) != RT_ERR_OK) + return ret; + if ((ret = _phy_rtl826xb_patch_top_set(unit, port, 40, 19, sdsAddr)) != RT_ERR_OK) + return ret; + return _phy_rtl826xb_patch_wait(unit, port, PHY_MMD_VEND1, 0x143, 0, BIT_15, patch_mode); +} + +static int32 _phy_rtl826xb_flow_r1(uint32 unit, rtk_port_t port, uint8 portOffset, uint8 patch_mode) +{ + int32 ret = RT_ERR_OK; + rt_phy_patch_db_t *pPatchDb = NULL; + + PHYPATCH_DB_GET(unit, port, pPatchDb); + + //PHYReg_bit w $PHYID 0xb82 16 4 4 0x1 + RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xb82, 16, 4, 4, 0x1, patch_mode), ret); + //PHYReg_bit w $PHYID 0xb82 16 4 4 0x1 + RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xb82, 16, 4, 4, 0x1, patch_mode), ret); + + //set patch_rdy [PHYReg_bit r $PHYID 0xb80 16 6 6] ; Wait for patch ready = 1 + RT_ERR_CHK(_phy_rtl826xb_patch_wait(unit, port, 31, _phy_rtl826xb_mmd_convert(0xb80, 16), BIT_6, BIT_6, patch_mode), ret); + + //PHYReg w $PHYID 0xa43 27 $0x8023 + RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa43, 27, 15, 0, 0x8023, patch_mode), ret); + //PHYReg w $PHYID 0xa43 28 $0x3802 + RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa43, 28, 15, 0, 0x3802, patch_mode), ret); + //PHYReg w $PHYID 0xa43 27 0xB82E + RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa43, 27, 15, 0, 0xB82E, patch_mode), ret); + //PHYReg w $PHYID 0xa43 28 0x1 + RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa43, 28, 15, 0, 0x1, patch_mode), ret); + + return RT_ERR_OK; +} + +static int32 _phy_rtl826xb_flow_r12(uint32 unit, rtk_port_t port, uint8 portOffset, uint8 patch_mode) +{ + int32 ret = RT_ERR_OK; + rt_phy_patch_db_t *pPatchDb = NULL; + + PHYPATCH_DB_GET(unit, port, pPatchDb); + + //PHYReg_bit w $PHYID 0xb82 16 4 4 0x1 + //RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xb82, 16, 4, 4, 0x1, patch_mode), ret); + //PHYReg_bit w $PHYID 0xb82 16 4 4 0x1 + RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xb82, 16, 4, 4, 0x1, patch_mode), ret); + + //set patch_rdy [PHYReg_bit r $PHYID 0xb80 16 6 6] ; Wait for patch ready = 1 + RT_ERR_CHK(_phy_rtl826xb_patch_wait(unit, port, 31, _phy_rtl826xb_mmd_convert(0xb80, 16), BIT_6, BIT_6, patch_mode), ret); + + //PHYReg w $PHYID 0xa43 27 $0x8023 + RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa43, 27, 15, 0, 0x8023, patch_mode), ret); + //PHYReg w $PHYID 0xa43 28 $0x3800 + RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa43, 28, 15, 0, 0x3800, patch_mode), ret); + //PHYReg w $PHYID 0xa43 27 0xB82E + RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa43, 27, 15, 0, 0xB82E, patch_mode), ret); + //PHYReg w $PHYID 0xa43 28 0x1 + RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa43, 28, 15, 0, 0x1, patch_mode), ret); + + return RT_ERR_OK; +} + + +static int32 _phy_rtl826xb_flow_r2(uint32 unit, rtk_port_t port, uint8 portOffset, uint8 patch_mode) +{ + int32 ret = RT_ERR_OK; + rt_phy_patch_db_t *pPatchDb = NULL; + + PHYPATCH_DB_GET(unit, port, pPatchDb); + + //PHYReg w $PHYID 0xa43 27 0x0000 + RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa43, 27, 15, 0, 0x0000, patch_mode), ret); + //PHYReg w $PHYID 0xa43 28 0x0000 + RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa43, 28, 15, 0, 0x0000, patch_mode), ret); + //PHYReg_bit w $PHYID 0xB82 23 0 0 0x0 + RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xB82, 23, 0, 0, 0x0, patch_mode), ret); + //PHYReg w $PHYID 0xa43 27 $0x8023 + RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa43, 27, 15, 0, 0x8023, patch_mode), ret); + //PHYReg w $PHYID 0xa43 28 0x0000 + RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa43, 28, 15, 0, 0x0000, patch_mode), ret); + + //PHYReg_bit w $PHYID 0xb82 16 4 4 0x0 + RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xb82, 16, 4, 4, 0x0, patch_mode), ret); + //set patch_rdy [PHYReg_bit r $PHYID 0xb80 16 6 6] ; Wait for patch ready != 1 + RT_ERR_CHK( _phy_rtl826xb_patch_wait_not_equal(unit, port, 31, _phy_rtl826xb_mmd_convert(0xb80, 16), BIT_6, BIT_6, patch_mode), ret); + + return RT_ERR_OK; +} + +static int32 _phy_rtl826xb_flow_l1(uint32 unit, rtk_port_t port, uint8 portOffset, uint8 patch_mode) +{ + int32 ret = RT_ERR_OK; + rt_phy_patch_db_t *pPatchDb = NULL; + + PHYPATCH_DB_GET(unit, port, pPatchDb); + + //PHYReg_bit w $PHYID 0xa4a 16 10 10 0x1 + RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa4a, 16, 10, 10, 0x1, patch_mode), ret); + //PHYReg_bit w $PHYID 0xa4a 16 10 10 0x1 + RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa4a, 16, 10, 10, 0x1, patch_mode), ret); + + //set pcs_state [PHYReg_bit r $PHYID 0xa60 16 7 0] ; Wait for pcs state = 1 + RT_ERR_CHK( _phy_rtl826xb_patch_wait(unit, port, 31, _phy_rtl826xb_mmd_convert(0xa60, 16), 0x1, 0xFF, patch_mode), ret); + + return RT_ERR_OK; +} + +static int32 _phy_rtl826xb_flow_l2(uint32 unit, rtk_port_t port, uint8 portOffset, uint8 patch_mode) +{ + int32 ret = RT_ERR_OK; + rt_phy_patch_db_t *pPatchDb = NULL; + + PHYPATCH_DB_GET(unit, port, pPatchDb); + + //PHYReg_bit w $PHYID 0xa4a 16 10 10 0x0 + RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa4a, 16, 10, 10, 0x0, patch_mode), ret); + + //set pcs_state [PHYReg_bit r $PHYID 0xa60 16 7 0] ; Wait for pcs state != 1 + RT_ERR_CHK( _phy_rtl826xb_patch_wait_not_equal(unit, port, 31, _phy_rtl826xb_mmd_convert(0xa60, 16), 0x1, 0xFF, patch_mode), ret); + + return RT_ERR_OK; +} + +static int32 _phy_rtl826xb_flow_pi(uint32 unit, rtk_port_t port, uint8 portOffset, uint8 patch_mode) +{ + int32 ret = RT_ERR_OK; + rt_phy_patch_db_t *pPatchDb = NULL; + uint32 rData = 0, cnt = 0; + + PHYPATCH_DB_GET(unit, port, pPatchDb); + + _phy_rtl826xb_flow_l1(unit, port, portOffset, patch_mode); + + // PP_PHYReg_bit w $PHYID 0xbf86 9 9 0x1; #SS_EN_XG = 1 + RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHYOCP, 0xFF, 31, 0xbf86, 9, 9, 0x1, patch_mode), ret); + // PP_PHYReg_bit w $PHYID 0xbf86 8 8 0x0; + RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHYOCP, 0xFF, 31, 0xbf86, 8, 8, 0x0, patch_mode), ret); + // PP_PHYReg_bit w $PHYID 0xbf86 7 7 0x1; + RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHYOCP, 0xFF, 31, 0xbf86, 7, 7, 0x1, patch_mode), ret); + // PP_PHYReg_bit w $PHYID 0xbf86 6 6 0x1; + RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHYOCP, 0xFF, 31, 0xbf86, 6, 6, 0x1, patch_mode), ret); + // PP_PHYReg_bit w $PHYID 0xbf86 5 5 0x1; + RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHYOCP, 0xFF, 31, 0xbf86, 5, 5, 0x1, patch_mode), ret); + // PP_PHYReg_bit w $PHYID 0xbf86 4 4 0x1; + RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHYOCP, 0xFF, 31, 0xbf86, 4, 4, 0x1, patch_mode), ret); + // PP_PHYReg_bit w $PHYID 0xbf86 6 6 0x0; + RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHYOCP, 0xFF, 31, 0xbf86, 6, 6, 0x0, patch_mode), ret); + // PP_PHYReg_bit w $PHYID 0xbf86 9 9 0x0; + RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHYOCP, 0xFF, 31, 0xbf86, 9, 9, 0x0, patch_mode), ret); + // PP_PHYReg_bit w $PHYID 0xbf86 7 7 0x0; + RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHYOCP, 0xFF, 31, 0xbf86, 7, 7, 0x0, patch_mode), ret); + + //PP_PHYReg_bit r $PHYID 0xbc62 12 8 + if ((ret = phy_common_general_reg_mmd_get(unit, port, PHY_MMD_VEND2, 0xbc62, &rData)) != RT_ERR_OK) + return ret; + rData = REG32_FIELD_GET(rData, 8, 0x1F00); + for (cnt = 0; cnt <= rData; cnt++) + { + //PP_PHYReg_bit w $PHYID 0xbc62 12 8 $t + RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHYOCP, 0xFF, 31, 0xbc62, 12, 8, cnt, patch_mode), ret); + } + + // PP_PHYReg_bit w $PHYID 0xbc02 2 2 0x1 + RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHYOCP, 0xFF, 31, 0xbc02, 2, 2, 0x1, patch_mode), ret); + // PP_PHYReg_bit w $PHYID 0xbc02 3 3 0x1 + RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHYOCP, 0xFF, 31, 0xbc02, 3, 3, 0x1, patch_mode), ret); + // PP_PHYReg_bit w $PHYID 0xbf86 6 6 0x1 + RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHYOCP, 0xFF, 31, 0xbf86, 6, 6, 0x1, patch_mode), ret); + // PP_PHYReg_bit w $PHYID 0xbf86 9 9 0x1 + RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHYOCP, 0xFF, 31, 0xbf86, 9, 9, 0x1, patch_mode), ret); + // PP_PHYReg_bit w $PHYID 0xbf86 7 7 0x1 + RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHYOCP, 0xFF, 31, 0xbf86, 7, 7, 0x1, patch_mode), ret); + // PP_PHYReg_bit w $PHYID 0xbc04 9 2 0xff + RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHYOCP, 0xFF, 31, 0xbc04, 9, 2, 0xff, patch_mode), ret); + + _phy_rtl826xb_flow_l2(unit, port, portOffset, patch_mode); + return RT_ERR_OK; +} + +static int32 _phy_rtl826xb_flow_n01(uint32 unit, rtk_port_t port, uint8 portOffset, uint8 patch_mode) +{ + int32 ret = RT_ERR_OK; + rt_phy_patch_db_t *pPatchDb = NULL; + + PHYPATCH_DB_GET(unit, port, pPatchDb); + + //PHYReg_bit w $PHYID 0xa01 21 15 0 0x1 + RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa01, 21, 15, 0, 0x1, patch_mode), ret); + //PHYReg_bit w $PHYID 0xa01 19 15 0 0x0000 + RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa01, 19, 15, 0, 0x0000, patch_mode), ret); + //# PHYReg_bit w $PHYID 0xa01 17 15 0 0x0000 + //RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa01, 17, 15, 0, 0x0000, patch_mode), ret); + + return RT_ERR_OK; +} + +static int32 _phy_rtl826xb_flow_n02(uint32 unit, rtk_port_t port, uint8 portOffset, uint8 patch_mode) +{ + int32 ret = RT_ERR_OK; + rt_phy_patch_db_t *pPatchDb = NULL; + + PHYPATCH_DB_GET(unit, port, pPatchDb); + + //PHYReg_bit w $PHYID 0xa01 21 15 0 0x0 + RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa01, 21, 15, 0, 0x0, patch_mode), ret); + //PHYReg_bit w $PHYID 0xa01 19 15 0 0x0000 + RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa01, 19, 15, 0, 0x0000, patch_mode), ret); + //PHYReg_bit w $PHYID 0xa01 17 15 0 0x0000 + RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa01, 17, 15, 0, 0x0000, patch_mode), ret); + return RT_ERR_OK; +} + +static int32 _phy_rtl826xb_flow_n11(uint32 unit, rtk_port_t port, uint8 portOffset, uint8 patch_mode) +{ + int32 ret = RT_ERR_OK; + rt_phy_patch_db_t *pPatchDb = NULL; + + PHYPATCH_DB_GET(unit, port, pPatchDb); + + //PHYReg_bit w $PHYID 0xa01 21 15 0 0x1 + RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa01, 21, 15, 0, 0x1, patch_mode), ret); + //PHYReg_bit w $PHYID 0xa01 19 15 0 0x0010 + RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa01, 19, 15, 0, 0x0010, patch_mode), ret); + //# PHYReg_bit w $PHYID 0xa01 17 15 0 0x0000 + //RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa01, 17, 15, 0, 0x0000, patch_mode), ret); + + return RT_ERR_OK; +} + +static int32 _phy_rtl826xb_flow_n12(uint32 unit, rtk_port_t port, uint8 portOffset, uint8 patch_mode) +{ + int32 ret = RT_ERR_OK; + rt_phy_patch_db_t *pPatchDb = NULL; + + PHYPATCH_DB_GET(unit, port, pPatchDb); + + //PHYReg_bit w $PHYID 0xa01 21 15 0 0x0 + RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa01, 21, 15, 0, 0x0, patch_mode), ret); + //PHYReg_bit w $PHYID 0xa01 19 15 0 0x0010 + RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa01, 19, 15, 0, 0x0010, patch_mode), ret); + //PHYReg_bit w $PHYID 0xa01 17 15 0 0x0000 + RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa01, 17, 15, 0, 0x0000, patch_mode), ret); + + return RT_ERR_OK; +} + +static int32 _phy_rtl826xb_flow_n21(uint32 unit, rtk_port_t port, uint8 portOffset, uint8 patch_mode) +{ + int32 ret = RT_ERR_OK; + rt_phy_patch_db_t *pPatchDb = NULL; + + PHYPATCH_DB_GET(unit, port, pPatchDb); + + //PHYReg_bit w $PHYID 0xa01 21 15 0 0x1 + RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa01, 21, 15, 0, 0x1, patch_mode), ret); + //PHYReg_bit w $PHYID 0xa01 19 15 0 0x0020 + RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa01, 19, 15, 0, 0x0020, patch_mode), ret); + //# PHYReg_bit w $PHYID 0xa01 17 15 0 0x0000 + //RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa01, 17, 15, 0, 0x0000, patch_mode), ret); + + return RT_ERR_OK; +} + +static int32 _phy_rtl826xb_flow_n22(uint32 unit, rtk_port_t port, uint8 portOffset, uint8 patch_mode) +{ + int32 ret = RT_ERR_OK; + rt_phy_patch_db_t *pPatchDb = NULL; + + PHYPATCH_DB_GET(unit, port, pPatchDb); + + //PHYReg_bit w $PHYID 0xa01 21 15 0 0x0 + RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa01, 21, 15, 0, 0x0, patch_mode), ret); + //PHYReg_bit w $PHYID 0xa01 19 15 0 0x0020 + RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa01, 19, 15, 0, 0x0020, patch_mode), ret); + //PHYReg_bit w $PHYID 0xa01 17 15 0 0x0000 + RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa01, 17, 15, 0, 0x0000, patch_mode), ret); + + return RT_ERR_OK; +} + +static int32 _phy_rtl826xb_flow_s(uint32 unit, rtk_port_t port, uint8 portOffset, uint8 patch_mode) +{ + int32 ret = RT_ERR_OK; + rt_phy_patch_db_t *pPatchDb = NULL; + + if (PHYPATCH_IS_RTKSDS(unit)) + { + PHYPATCH_DB_GET(unit, port, pPatchDb); + + RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PSDS0, 0xff, 0x07, 0x10, 15, 0, 0x80aa, patch_mode), ret); + RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PSDS0, 0xff, 0x06, 0x12, 15, 0, 0x5078, patch_mode), ret); + } + + return RT_ERR_OK; +} + +static int32 _phy_rtl826xb_flow_cmpstart(uint32 unit, rtk_port_t port, uint8 portOffset, uint8 patch_mode) +{ + int32 ret = RT_ERR_OK; + rt_phy_patch_db_t *pPatchDb = NULL; + + PHYPATCH_DB_GET(unit, port, pPatchDb); + RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHYOCP, 0xFF, 1, 0, 11, 11, 0x0, patch_mode), ret); + return RT_ERR_OK; +} + +static int32 _phy_rtl826xb_flow_cmpend(uint32 unit, rtk_port_t port, uint8 portOffset, uint8 patch_mode) +{ + int32 ret = RT_ERR_OK; + rt_phy_patch_db_t *pPatchDb = NULL; + + PHYPATCH_DB_GET(unit, port, pPatchDb); + RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHYOCP, 0xFF, 1, 0, 11, 11, 0x1, patch_mode), ret); + return RT_ERR_OK; +} + +int32 phy_rtl826xb_patch_op(uint32 unit, rtk_port_t port, uint8 portOffset, rtk_hwpatch_t *pPatch_data, uint8 patch_mode) +{ + int32 ret = RT_ERR_OK; + uint32 rData = 0, wData = 0; + uint16 reg = 0; + uint8 patch_op = 0; + uint32 mask = 0; + + if ((pPatch_data->portmask & (1 << portOffset)) == 0) + { + return RT_ERR_ABORT; + } + mask = UINT32_BITS_MASK(pPatch_data->msb, pPatch_data->lsb); + patch_op = phy_patch_op_translate(patch_mode, pPatch_data->patch_op, pPatch_data->compare_op); + + #if 0 + osal_printf("[%s,%d]u%up%u, patch_mode:%u/patch_op:%u/compare_op:%u => op: %u\n", __FUNCTION__, __LINE__, unit, port, + patch_mode, pPatch_data->patch_op, pPatch_data->compare_op, + patch_op); + #endif + + switch (patch_op) + { + case RTK_PATCH_OP_PHY: + reg = _phy_rtl826xb_mmd_convert(pPatch_data->pagemmd, pPatch_data->addr); + if ((pPatch_data->msb != 15) || (pPatch_data->lsb != 0)) + { + RT_ERR_CHK(phy_common_general_reg_mmd_get(unit, port, 31, reg, &rData), ret); + } + wData = REG32_FIELD_SET(rData, pPatch_data->data, pPatch_data->lsb, mask); + RT_ERR_CHK(phy_common_general_reg_mmd_set(unit, port, 31, reg, wData), ret); + break; + case RTK_PATCH_OP_CMP_PHY: + reg = _phy_rtl826xb_mmd_convert(pPatch_data->pagemmd, pPatch_data->addr); + RT_ERR_CHK(phy_common_general_reg_mmd_get(unit, port, 31, reg, &rData), ret); + PHYPATCH_COMPARE(pPatch_data->pagemmd, pPatch_data->addr, pPatch_data->msb, pPatch_data->lsb, pPatch_data->data, rData, mask); + break; + case RTK_PATCH_OP_CMP_SRAM_PHY: + reg = _phy_rtl826xb_mmd_convert(pPatch_data->sram_p, pPatch_data->sram_rw); + RT_ERR_CHK(phy_common_general_reg_mmd_set(unit, port, 31, reg, pPatch_data->sram_a), ret); + reg = _phy_rtl826xb_mmd_convert(pPatch_data->sram_p, pPatch_data->sram_rr); + RT_ERR_CHK(phy_common_general_reg_mmd_get(unit, port, 31, reg, &rData), ret); + PHYPATCH_COMPARE(pPatch_data->pagemmd, pPatch_data->addr, pPatch_data->msb, pPatch_data->lsb, pPatch_data->data, rData, mask); + break; + + case RTK_PATCH_OP_PHYOCP: + if ((pPatch_data->msb != 15) || (pPatch_data->lsb != 0)) + { + RT_ERR_CHK(phy_common_general_reg_mmd_get(unit, port, 31, pPatch_data->addr, &rData), ret); + } + wData = REG32_FIELD_SET(rData, pPatch_data->data, pPatch_data->lsb, mask); + RT_ERR_CHK(phy_common_general_reg_mmd_set(unit, port, 31, pPatch_data->addr, wData), ret); + break; + case RTK_PATCH_OP_CMP_PHYOCP: + RT_ERR_CHK(phy_common_general_reg_mmd_get(unit, port, 31, pPatch_data->addr, &rData), ret); + PHYPATCH_COMPARE(pPatch_data->pagemmd, pPatch_data->addr, pPatch_data->msb, pPatch_data->lsb, pPatch_data->data, rData, mask); + break; + case RTK_PATCH_OP_CMP_SRAM_PHYOCP: + RT_ERR_CHK(phy_common_general_reg_mmd_set(unit, port, 31, pPatch_data->sram_rw, pPatch_data->sram_a), ret); + RT_ERR_CHK(phy_common_general_reg_mmd_get(unit, port, 31, pPatch_data->sram_rr, &rData), ret); + PHYPATCH_COMPARE(pPatch_data->pagemmd, pPatch_data->addr, pPatch_data->msb, pPatch_data->lsb, pPatch_data->data, rData, mask); + break; + + case RTK_PATCH_OP_TOP: + if ((pPatch_data->msb != 15) || (pPatch_data->lsb != 0)) + { + RT_ERR_CHK(_phy_rtl826xb_patch_top_get(unit, port, pPatch_data->pagemmd, pPatch_data->addr, &rData), ret); + } + wData = REG32_FIELD_SET(rData, pPatch_data->data, pPatch_data->lsb, mask); + RT_ERR_CHK(_phy_rtl826xb_patch_top_set(unit, port, pPatch_data->pagemmd, pPatch_data->addr, wData), ret); + break; + case RTK_PATCH_OP_CMP_TOP: + RT_ERR_CHK(_phy_rtl826xb_patch_top_get(unit, port, pPatch_data->pagemmd, pPatch_data->addr, &rData), ret); + PHYPATCH_COMPARE(pPatch_data->pagemmd, pPatch_data->addr, pPatch_data->msb, pPatch_data->lsb, pPatch_data->data, rData, mask); + break; + case RTK_PATCH_OP_CMP_SRAM_TOP: + RT_ERR_CHK(_phy_rtl826xb_patch_top_set(unit, port, pPatch_data->sram_p, pPatch_data->sram_rw, pPatch_data->sram_a), ret); + RT_ERR_CHK(_phy_rtl826xb_patch_top_get(unit, port, pPatch_data->sram_p, pPatch_data->sram_rr, &rData), ret); + PHYPATCH_COMPARE(pPatch_data->pagemmd, pPatch_data->addr, pPatch_data->msb, pPatch_data->lsb, pPatch_data->data, rData, mask); + break; + + case RTK_PATCH_OP_PSDS0: + if ((pPatch_data->msb != 15) || (pPatch_data->lsb != 0)) + { + RT_ERR_CHK(_phy_rtl826xb_patch_sds_get(unit, port, pPatch_data->pagemmd, pPatch_data->addr, &rData), ret); + } + wData = REG32_FIELD_SET(rData, pPatch_data->data, pPatch_data->lsb, mask); + RT_ERR_CHK(_phy_rtl826xb_patch_sds_set(unit, port, pPatch_data->pagemmd, pPatch_data->addr, wData, patch_mode), ret); + break; + case RTK_PATCH_OP_CMP_PSDS0: + RT_ERR_CHK(_phy_rtl826xb_patch_sds_get(unit, port, pPatch_data->pagemmd, pPatch_data->addr, &rData), ret); + PHYPATCH_COMPARE(pPatch_data->pagemmd, pPatch_data->addr, pPatch_data->msb, pPatch_data->lsb, pPatch_data->data, rData, mask); + break; + case RTK_PATCH_OP_CMP_SRAM_PSDS0: + RT_ERR_CHK(_phy_rtl826xb_patch_sds_set(unit, port, pPatch_data->sram_p, pPatch_data->sram_rw, pPatch_data->sram_a, patch_mode), ret); + RT_ERR_CHK(_phy_rtl826xb_patch_sds_get(unit, port, pPatch_data->sram_p, pPatch_data->sram_rr, &rData), ret); + PHYPATCH_COMPARE(pPatch_data->pagemmd, pPatch_data->addr, pPatch_data->msb, pPatch_data->lsb, pPatch_data->data, rData, mask); + break; + + case RTK_PATCH_OP_DELAY_MS: + osal_time_mdelay(pPatch_data->data); + break; + + case RTK_PATCH_OP_SKIP: + return RT_ERR_ABORT; + + default: + RT_LOG(LOG_MAJOR_ERR, (MOD_HAL | MOD_PHY), "U%u P%u patch_op:%u not implemented yet!\n", unit, port, pPatch_data->patch_op); + return RT_ERR_DRIVER_NOT_SUPPORTED; + } + + return ret; +} + +int32 phy_rtl826xb_patch_flow(uint32 unit, rtk_port_t port, uint8 portOffset, uint8 patch_flow, uint8 patch_mode) +{ + int32 ret = RT_ERR_OK; + + RT_LOG(LOG_INFO, (MOD_HAL | MOD_PHY), "[%s]U%u,P%u,flow%u\n", __FUNCTION__, unit, port, (patch_flow - PHY_PATCH_TYPE_END)); + switch (patch_flow) + { + case RTK_PATCH_TYPE_FLOW(0): + RT_ERR_CHK(_phy_rtl826xb_flow_r1(unit, port, portOffset, patch_mode), ret); + break; + case RTK_PATCH_TYPE_FLOW(1): + RT_ERR_CHK(_phy_rtl826xb_flow_r2(unit, port, portOffset, patch_mode), ret); + break; + + case RTK_PATCH_TYPE_FLOW(2): + RT_ERR_CHK(_phy_rtl826xb_flow_l1(unit, port, portOffset, patch_mode), ret); + break; + case RTK_PATCH_TYPE_FLOW(3): + RT_ERR_CHK(_phy_rtl826xb_flow_l2(unit, port, portOffset, patch_mode), ret); + break; + + case RTK_PATCH_TYPE_FLOW(4): + RT_ERR_CHK(_phy_rtl826xb_flow_n01(unit, port, portOffset, patch_mode), ret); + break; + case RTK_PATCH_TYPE_FLOW(5): + RT_ERR_CHK(_phy_rtl826xb_flow_n02(unit, port, portOffset, patch_mode), ret); + break; + + case RTK_PATCH_TYPE_FLOW(6): + RT_ERR_CHK(_phy_rtl826xb_flow_n11(unit, port, portOffset, patch_mode), ret); + break; + case RTK_PATCH_TYPE_FLOW(7): + RT_ERR_CHK(_phy_rtl826xb_flow_n12(unit, port, portOffset, patch_mode), ret); + break; + + case RTK_PATCH_TYPE_FLOW(8): + RT_ERR_CHK(_phy_rtl826xb_flow_n21(unit, port, portOffset, patch_mode), ret); + break; + case RTK_PATCH_TYPE_FLOW(9): + RT_ERR_CHK(_phy_rtl826xb_flow_n22(unit, port, portOffset, patch_mode), ret); + break; + + case RTK_PATCH_TYPE_FLOW(10): + RT_ERR_CHK(_phy_rtl826xb_flow_s(unit, port, portOffset, patch_mode), ret); + break; + + case RTK_PATCH_TYPE_FLOW(11): + RT_ERR_CHK(_phy_rtl826xb_flow_pi(unit, port, portOffset, patch_mode), ret); + break; + case RTK_PATCH_TYPE_FLOW(12): + RT_ERR_CHK(_phy_rtl826xb_flow_r12(unit, port, portOffset, patch_mode), ret); + break; + + case RTK_PATCH_TYPE_FLOW(13): + RT_ERR_CHK(_phy_rtl826xb_flow_cmpstart(unit, port, portOffset, patch_mode), ret); + break; + case RTK_PATCH_TYPE_FLOW(14): + RT_ERR_CHK(_phy_rtl826xb_flow_cmpend(unit, port, portOffset, patch_mode), ret); + break; + + default: + return RT_ERR_INPUT; + } + return RT_ERR_OK; +} + +int32 phy_rtl826xb_patch_db_init(uint32 unit, rtk_port_t port, rt_phy_patch_db_t **pPhy_patchDb) +{ + int32 ret = RT_ERR_OK; + rt_phy_patch_db_t *patch_db = NULL; + uint32 rData = 0; + + patch_db = osal_alloc(sizeof(rt_phy_patch_db_t)); + RT_PARAM_CHK(NULL == patch_db, RT_ERR_MEM_ALLOC); + osal_memset(patch_db, 0x0, sizeof(rt_phy_patch_db_t)); + + /* patch callback */ + patch_db->fPatch_op = phy_rtl826xb_patch_op; + patch_db->fPatch_flow = phy_rtl826xb_patch_flow; + + /* patch table */ + RT_ERR_CHK(phy_common_general_reg_mmd_get(unit, port, 30, 0x104, &rData), ret); + if ((rData & 0xFFC0) == 0x1140) /* RTL8261BE */ + { + /* patch */ + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 0, RTK_PATCH_TYPE_FLOW(0), NULL); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 1, PHY_PATCH_TYPE_NCTL0, rtl8261n_c_nctl0_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 2, PHY_PATCH_TYPE_NCTL1, rtl8261n_c_nctl1_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 3, PHY_PATCH_TYPE_NCTL2, rtl8261n_c_nctl2_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 4, PHY_PATCH_TYPE_UC2, rtl8261n_c_uc2_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 5, PHY_PATCH_TYPE_UC, rtl8261n_c_uc_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 6, PHY_PATCH_TYPE_DATARAM, rtl8261n_c_dataram_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 7, RTK_PATCH_TYPE_FLOW(1), NULL); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 8, RTK_PATCH_TYPE_FLOW(2), NULL); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 9, PHY_PATCH_TYPE_ALGXG, rtl8261n_c_algxg_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 10, PHY_PATCH_TYPE_ALG1G, rtl8261n_c_alg_giga_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 11, PHY_PATCH_TYPE_NORMAL, rtl8261n_c_normal_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 12, PHY_PATCH_TYPE_TOP, rtl8261n_c_top_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 13, PHY_PATCH_TYPE_SDS, rtl8261n_c_sds_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 14, PHY_PATCH_TYPE_AFE, rtl8261n_c_afe_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 15, PHY_PATCH_TYPE_RTCT, rtl8261n_c_rtct_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 16, RTK_PATCH_TYPE_FLOW(3), NULL); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 17, RTK_PATCH_TYPE_FLOW(10), NULL); + + /* compare */ + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 0, RTK_PATCH_TYPE_FLOW(13), NULL); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 1, PHY_PATCH_TYPE_TOP, rtl8261n_c_top_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 2, PHY_PATCH_TYPE_SDS, rtl8261n_c_sds_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 3, PHY_PATCH_TYPE_AFE, rtl8261n_c_afe_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 4, RTK_PATCH_TYPE_FLOW(4), NULL); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 5, PHY_PATCH_TYPE_NCTL0, rtl8261n_c_nctl0_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 6, RTK_PATCH_TYPE_FLOW(5), NULL); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 7, RTK_PATCH_TYPE_FLOW(6), NULL); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 8, PHY_PATCH_TYPE_NCTL1, rtl8261n_c_nctl1_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 9, RTK_PATCH_TYPE_FLOW(7), NULL); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 10, RTK_PATCH_TYPE_FLOW(8), NULL); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 11, PHY_PATCH_TYPE_NCTL2, rtl8261n_c_nctl2_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 12, RTK_PATCH_TYPE_FLOW(9), NULL); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 13, PHY_PATCH_TYPE_UC, rtl8261n_c_uc_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 14, PHY_PATCH_TYPE_UC2, rtl8261n_c_uc2_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 15, RTK_PATCH_TYPE_FLOW(0), NULL); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 16, PHY_PATCH_TYPE_DATARAM, rtl8261n_c_dataram_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 17, RTK_PATCH_TYPE_FLOW(1), NULL); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 18, PHY_PATCH_TYPE_ALGXG, rtl8261n_c_algxg_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 19, PHY_PATCH_TYPE_ALG1G, rtl8261n_c_alg_giga_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 20, PHY_PATCH_TYPE_NORMAL, rtl8261n_c_normal_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 21, PHY_PATCH_TYPE_RTCT, rtl8261n_c_rtct_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 22, RTK_PATCH_TYPE_FLOW(14), NULL); + } + else if ((rData & 0xF) == 0x0) + { + /* patch */ + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 0, RTK_PATCH_TYPE_FLOW(12), NULL); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 1, PHY_PATCH_TYPE_NCTL0, rtl8264b_nctl0_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 2, PHY_PATCH_TYPE_NCTL1, rtl8264b_nctl1_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 3, PHY_PATCH_TYPE_NCTL2, rtl8264b_nctl2_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 4, PHY_PATCH_TYPE_UC2, rtl8264b_uc2_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 5, PHY_PATCH_TYPE_UC, rtl8264b_uc_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 6, PHY_PATCH_TYPE_DATARAM, rtl8264b_dataram_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 7, RTK_PATCH_TYPE_FLOW(1), NULL); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 8, RTK_PATCH_TYPE_FLOW(2), NULL); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 9, PHY_PATCH_TYPE_ALGXG, rtl8264b_algxg_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 10, PHY_PATCH_TYPE_ALG1G, rtl8264b_alg_giga_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 11, PHY_PATCH_TYPE_NORMAL, rtl8264b_normal_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 12, PHY_PATCH_TYPE_TOP, rtl8264b_top_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 13, PHY_PATCH_TYPE_SDS, rtl8264b_sds_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 14, PHY_PATCH_TYPE_AFE, rtl8264b_afe_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 15, PHY_PATCH_TYPE_RTCT, rtl8264b_rtct_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 16, RTK_PATCH_TYPE_FLOW(3), NULL); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 17, RTK_PATCH_TYPE_FLOW(11), NULL); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 18, RTK_PATCH_TYPE_FLOW(10), NULL); + + /* compare */ + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 0, RTK_PATCH_TYPE_FLOW(13), NULL); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 1, PHY_PATCH_TYPE_TOP, rtl8264b_top_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 2, PHY_PATCH_TYPE_SDS, rtl8264b_sds_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 3, PHY_PATCH_TYPE_AFE, rtl8264b_afe_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 4, RTK_PATCH_TYPE_FLOW(4), NULL); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 5, PHY_PATCH_TYPE_NCTL0, rtl8264b_nctl0_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 6, RTK_PATCH_TYPE_FLOW(5), NULL); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 7, RTK_PATCH_TYPE_FLOW(6), NULL); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 8, PHY_PATCH_TYPE_NCTL1, rtl8264b_nctl1_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 9, RTK_PATCH_TYPE_FLOW(7), NULL); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 10, RTK_PATCH_TYPE_FLOW(8), NULL); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 11, PHY_PATCH_TYPE_NCTL2, rtl8264b_nctl2_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 12, RTK_PATCH_TYPE_FLOW(9), NULL); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 13, PHY_PATCH_TYPE_UC, rtl8264b_uc_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 14, PHY_PATCH_TYPE_UC2, rtl8264b_uc2_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 15, RTK_PATCH_TYPE_FLOW(12), NULL); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 16, PHY_PATCH_TYPE_DATARAM, rtl8264b_dataram_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 17, RTK_PATCH_TYPE_FLOW(1), NULL); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 18, PHY_PATCH_TYPE_ALGXG, rtl8264b_algxg_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 19, PHY_PATCH_TYPE_ALG1G, rtl8264b_alg_giga_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 20, PHY_PATCH_TYPE_NORMAL, rtl8264b_normal_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 21, PHY_PATCH_TYPE_RTCT, rtl8264b_rtct_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 22, RTK_PATCH_TYPE_FLOW(14), NULL); + } + else + { + /* patch */ + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 0, RTK_PATCH_TYPE_FLOW(0), NULL); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 1, PHY_PATCH_TYPE_NCTL0, rtl8261n_c_nctl0_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 2, PHY_PATCH_TYPE_NCTL1, rtl8261n_c_nctl1_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 3, PHY_PATCH_TYPE_NCTL2, rtl8261n_c_nctl2_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 4, PHY_PATCH_TYPE_UC2, rtl8261n_c_uc2_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 5, PHY_PATCH_TYPE_UC, rtl8261n_c_uc_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 6, PHY_PATCH_TYPE_DATARAM, rtl8261n_c_dataram_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 7, RTK_PATCH_TYPE_FLOW(1), NULL); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 8, RTK_PATCH_TYPE_FLOW(2), NULL); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 9, PHY_PATCH_TYPE_ALGXG, rtl8261n_c_algxg_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 10, PHY_PATCH_TYPE_ALG1G, rtl8261n_c_alg_giga_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 11, PHY_PATCH_TYPE_NORMAL, rtl8261n_c_normal_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 12, PHY_PATCH_TYPE_TOP, rtl8261n_c_top_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 13, PHY_PATCH_TYPE_SDS, rtl8261n_c_sds_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 14, PHY_PATCH_TYPE_AFE, rtl8261n_c_afe_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 15, PHY_PATCH_TYPE_RTCT, rtl8261n_c_rtct_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 16, RTK_PATCH_TYPE_FLOW(3), NULL); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 17, RTK_PATCH_TYPE_FLOW(10), NULL); + + /* compare */ + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 0, RTK_PATCH_TYPE_FLOW(13), NULL); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 1, PHY_PATCH_TYPE_TOP, rtl8261n_c_top_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 2, PHY_PATCH_TYPE_SDS, rtl8261n_c_sds_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 3, PHY_PATCH_TYPE_AFE, rtl8261n_c_afe_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 4, RTK_PATCH_TYPE_FLOW(4), NULL); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 5, PHY_PATCH_TYPE_NCTL0, rtl8261n_c_nctl0_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 6, RTK_PATCH_TYPE_FLOW(5), NULL); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 7, RTK_PATCH_TYPE_FLOW(6), NULL); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 8, PHY_PATCH_TYPE_NCTL1, rtl8261n_c_nctl1_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 9, RTK_PATCH_TYPE_FLOW(7), NULL); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 10, RTK_PATCH_TYPE_FLOW(8), NULL); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 11, PHY_PATCH_TYPE_NCTL2, rtl8261n_c_nctl2_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 12, RTK_PATCH_TYPE_FLOW(9), NULL); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 13, PHY_PATCH_TYPE_UC, rtl8261n_c_uc_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 14, PHY_PATCH_TYPE_UC2, rtl8261n_c_uc2_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 15, RTK_PATCH_TYPE_FLOW(0), NULL); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 16, PHY_PATCH_TYPE_DATARAM, rtl8261n_c_dataram_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 17, RTK_PATCH_TYPE_FLOW(1), NULL); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 18, PHY_PATCH_TYPE_ALGXG, rtl8261n_c_algxg_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 19, PHY_PATCH_TYPE_ALG1G, rtl8261n_c_alg_giga_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 20, PHY_PATCH_TYPE_NORMAL, rtl8261n_c_normal_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 21, PHY_PATCH_TYPE_RTCT, rtl8261n_c_rtct_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 22, RTK_PATCH_TYPE_FLOW(14), NULL); + } + *pPhy_patchDb = patch_db; + return ret; +} + +/* Function Name: + * phy_rtl826xb_patch + * Description: + * apply initial patch data to PHY + * Input: + * unit - unit id + * baseport - base port id on the PHY chip + * portOffset - the index offset base on baseport for the port to patch + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_SUPPORTED + * RT_ERR_ABORT + * Note: + * None + */ +int32 phy_rtl826xb_patch(uint32 unit, rtk_port_t port, uint8 portOffset) +{ + return phy_patch( unit, port, portOffset, PHY_PATCH_MODE_NORMAL); +} + +/* Function Name: + * phy_rtl826xb_broadcast_patch + * Description: + * apply patch data to PHY + * Input: + * unit - unit id + * baseport - base port id on the PHY chip + * portOffset - the index offset base on baseport for the port to patch + * perChip - 1 for per-chip mode, 0 for per-bus mode + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_SUPPORTED + * RT_ERR_ABORT + * Note: + * None + */ +int32 phy_rtl826xb_broadcast_patch(uint32 unit, rtk_port_t port, uint8 portOffset, uint8 perChip) +{ + int32 ret = 0; + if (perChip == 0) + { + ret = phy_patch(unit, port, portOffset, PHY_PATCH_MODE_BCAST_BUS); + } + else + { + ret = phy_patch(unit, port, portOffset, PHY_PATCH_MODE_BCAST); + } + return ret; +} + diff --git a/sources/rtk-be550/src/hal/phy/phy_rtl826xb_patch.h b/sources/rtk-be550/src/hal/phy/phy_rtl826xb_patch.h new file mode 100755 index 00000000..c2311ef2 --- /dev/null +++ b/sources/rtk-be550/src/hal/phy/phy_rtl826xb_patch.h @@ -0,0 +1,63 @@ +/* + * SPDX-License-Identifier: GPL-2.0-only + * + * Copyright (c) 2023 Realtek Semiconductor Corp. All rights reserved. + */ + +#ifndef __HAL_PHY_PHY_RTL826XB_PATCH_H__ +#define __HAL_PHY_PHY_RTL826XB_PATCH_H__ + +/* + * Include Files + */ +#if defined(RTK_PHYDRV_IN_LINUX) + #include "rtk_osal.h" + #include "rtk_phylib_def.h" +#else + #include + #include +#endif + +/* Function Name: + * phy_rtl826xb_patch + * Description: + * apply patch data to PHY + * Input: + * unit - unit id + * baseport - base port id on the PHY chip + * portOffset - the index offset base on baseport for the port to patch + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_SUPPORTED + * RT_ERR_ABORT + * Note: + * None + */ +extern int32 phy_rtl826xb_patch(uint32 unit, rtk_port_t baseport, uint8 portOffset); + +/* Function Name: + * phy_rtl826xb_broadcast_patch + * Description: + * apply patch data to PHY + * Input: + * unit - unit id + * baseport - base port id on the PHY chip + * portOffset - the index offset base on baseport for the port to patch + * perChip - 1 for per-chip mode, 0 for per-bus mode + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_SUPPORTED + * RT_ERR_ABORT + * Note: + * None + */ +extern int32 phy_rtl826xb_broadcast_patch(uint32 unit, rtk_port_t port, uint8 portOffset, uint8 perChip); + +extern int32 phy_rtl826xb_patch_db_init(uint32 unit, rtk_port_t port, rt_phy_patch_db_t **pPhy_patchDb); +#endif /* __HAL_PHY_PHY_RTL826XB_PATCH_H__ */ diff --git a/sources/rtk-be550/src/hal/phy/rtk_macsec.c b/sources/rtk-be550/src/hal/phy/rtk_macsec.c new file mode 100755 index 00000000..dd645ced --- /dev/null +++ b/sources/rtk-be550/src/hal/phy/rtk_macsec.c @@ -0,0 +1,888 @@ +/* + * SPDX-License-Identifier: GPL-2.0-only + * + * Copyright (c) 2023 Realtek Semiconductor Corp. All rights reserved. + */ + +#include +#include +#include +#include "rtk_phylib_macsec.h" +#include "rtk_phylib_rtl826xb.h" +#include "rtk_phylib.h" +#include "rtk_phy.h" + +static int rtk_macsec_del_txsa(struct macsec_context *ctx); +static int rtk_macsec_del_rxsa(struct macsec_context *ctx); + +static int __rtk_macsec_clear_txsc(struct macsec_context *ctx, uint32 sc_id) +{ + int32 ret = 0; + RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_sc_del(ctx->phydev, RTK_MACSEC_DIR_EGRESS, sc_id)); + return ret; +} + +static int __rtk_macsec_clear_rxsc(struct macsec_context *ctx, uint32 sc_id) +{ + int32 ret = 0; + RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_sc_del(ctx->phydev, RTK_MACSEC_DIR_INGRESS, sc_id)); + return ret; +} + +static int rtk_macsec_dev_open(struct macsec_context *ctx) +{ + PR_DBG("[%s] ctx->prepare: %u\n", __FUNCTION__, ctx->prepare); + if (ctx->prepare) + return 0; + + return rtk_phylib_macsec_enable_set(ctx->phydev, 1); +} + +static int rtk_macsec_dev_stop(struct macsec_context *ctx) +{ + PR_DBG("[%s] ctx->prepare: %u\n", __FUNCTION__, ctx->prepare); + if (ctx->prepare) + return 0; + + return rtk_phylib_macsec_enable_set(ctx->phydev, 0); +} + +static int rtk_macsec_add_secy(struct macsec_context *ctx) +{ + int32 ret = 0; + struct rtk_phy_priv *priv = ctx->phydev->priv; + rtk_macsec_port_info_t *macsec_db = priv->macsec; + + PR_DBG("[%s] ctx->prepare: %u\n", __FUNCTION__, ctx->prepare); + if (ctx->prepare) + { + return 0; + } + + if(MACSEC_SC_IS_USED(macsec_db, RTK_MACSEC_DIR_EGRESS, 0)) + { + PR_ERR("[%s]MACSEC_SC_IS_USED\n",__FUNCTION__); + return -EEXIST; + } + + /* create TX SC */ + { + uint32 sc_id = 0; + rtk_macsec_sc_t sc; + memset(&sc, 0x0, sizeof(rtk_macsec_sc_t)); + + switch (ctx->secy->key_len) + { + case 16: + sc.tx.cipher_suite = (ctx->secy->xpn) ? RTK_MACSEC_CIPHER_GCM_ASE_XPN_128 : RTK_MACSEC_CIPHER_GCM_ASE_128; + break; + case 32: + sc.tx.cipher_suite = (ctx->secy->xpn) ? RTK_MACSEC_CIPHER_GCM_ASE_XPN_256 : RTK_MACSEC_CIPHER_GCM_ASE_256; + break; + default: + PR_ERR("Not support key_len %d\n", ctx->secy->key_len); + return -EINVAL; + } + + RTK_PHYLIB_VAL_TO_BYTE_ARRAY(ctx->secy->sci, 8, sc.tx.sci, 0, 8); + PR_DBG("[%s]secy->sci: 0x%llX\n", __FUNCTION__, ctx->secy->sci); + sc.tx.flow_match = RTK_MACSEC_MATCH_NON_CTRL; + sc.tx.protect_frame = ctx->secy->protect_frames; + sc.tx.include_sci = ctx->secy->tx_sc.send_sci; + sc.tx.use_es = ctx->secy->tx_sc.end_station; + sc.tx.use_scb = ctx->secy->tx_sc.scb; + sc.tx.conf_protect = ctx->secy->tx_sc.encrypt; + + RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_sc_create(ctx->phydev, RTK_MACSEC_DIR_EGRESS, &sc, &sc_id, (ctx->secy->tx_sc.active) ? 1 : 0)); + } + + return ret; +} + +static int rtk_macsec_del_secy(struct macsec_context *ctx) +{ + int32 ret = 0; + struct rtk_phy_priv *priv = ctx->phydev->priv; + rtk_macsec_port_info_t *macsec_db = priv->macsec; + uint32 i = 0; + + PR_DBG("[%s] ctx->prepare: %u\n", __FUNCTION__, ctx->prepare); + if (ctx->prepare) + { + return 0; + } + + for (i = 0; i < MACSEC_SC_MAX(macsec_db); i++) + { + if(MACSEC_SC_IS_USED(macsec_db, RTK_MACSEC_DIR_EGRESS, i)) + { + PR_DBG("[%s] clear TX SC %u\n", __FUNCTION__, i); + RTK_PHYLIB_ERR_CHK(__rtk_macsec_clear_txsc(ctx, i)); + } + + if(MACSEC_SC_IS_USED(macsec_db, RTK_MACSEC_DIR_INGRESS, i)) + { + PR_DBG("[%s] clear RX SC %u\n", __FUNCTION__, i); + RTK_PHYLIB_ERR_CHK(__rtk_macsec_clear_rxsc(ctx, i)); + } + } + memset(&(macsec_db->port_stats), 0x0, sizeof(rtk_macsec_sc_t)); + return ret; +} + +static int rtk_macsec_upd_secy(struct macsec_context *ctx) +{ + int32 ret = 0; + struct rtk_phy_priv *priv = ctx->phydev->priv; + rtk_macsec_port_info_t *macsec_db = priv->macsec; + + rtk_macsec_cipher_t cipher_suite; + + if (ctx->prepare) + { + return 0; + } + + if(MACSEC_SC_IS_CLEAR(macsec_db, RTK_MACSEC_DIR_EGRESS, 0)) + { + PR_ERR("[%s]MACSEC_SC_IS_CLEAR\n",__FUNCTION__); + return -ENOENT; + } + + /* create TX SC */ + { + uint32 sc_id = 0; + rtk_macsec_sc_t sc; + rtk_macsec_sc_t cur_sc; + RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_sc_get(ctx->phydev, RTK_MACSEC_DIR_EGRESS, 0, &sc)); + memcpy(&cur_sc, &sc, sizeof(rtk_macsec_sc_t)); + + switch (ctx->secy->key_len) + { + case 16: + cipher_suite = (ctx->secy->xpn) ? RTK_MACSEC_CIPHER_GCM_ASE_XPN_128 : RTK_MACSEC_CIPHER_GCM_ASE_128; + break; + case 32: + cipher_suite = (ctx->secy->xpn) ? RTK_MACSEC_CIPHER_GCM_ASE_XPN_256 : RTK_MACSEC_CIPHER_GCM_ASE_256; + break; + default: + PR_ERR("Not support key_len %d\n", ctx->secy->key_len); + return -EINVAL; + } + + RTK_PHYLIB_VAL_TO_BYTE_ARRAY(ctx->secy->sci, 8, sc.tx.sci, 0, 8); + #ifdef MACSEC_DBG_PRINT + PR_DBG("[%s]secy->sci: 0x%llX\n", __FUNCTION__, ctx->secy->sci); + PR_DBG("cipher_suite %u => %u\n", sc.tx.cipher_suite, cipher_suite); + PR_DBG("flow_match %u => %u\n", sc.tx.flow_match, RTK_MACSEC_MATCH_NON_CTRL); + PR_DBG("protect_frame %u => %u\n", sc.tx.protect_frame, ctx->secy->protect_frames); + PR_DBG("include_sci %u => %u\n", sc.tx.include_sci, ctx->secy->tx_sc.send_sci); + PR_DBG("use_es %u => %u\n", sc.tx.use_es, ctx->secy->tx_sc.end_station); + PR_DBG("use_scb %u => %u\n", sc.tx.use_scb, ctx->secy->tx_sc.scb); + PR_DBG("conf_protect %u => %u\n", sc.tx.conf_protect, ctx->secy->tx_sc.encrypt); + #endif + sc.tx.cipher_suite = cipher_suite; + sc.tx.flow_match = RTK_MACSEC_MATCH_NON_CTRL; + sc.tx.protect_frame = ctx->secy->protect_frames; + sc.tx.include_sci = ctx->secy->tx_sc.send_sci; + sc.tx.use_es = ctx->secy->tx_sc.end_station; + sc.tx.use_scb = ctx->secy->tx_sc.scb; + sc.tx.conf_protect = ctx->secy->tx_sc.encrypt; + + if(memcmp(&cur_sc, &sc, sizeof(rtk_macsec_sc_t)) != 0) + RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_sc_update(ctx->phydev, RTK_MACSEC_DIR_EGRESS, &sc, &sc_id, (ctx->secy->tx_sc.active) ? 1 : 0)); + } + + return ret; +} + +static int rtk_macsec_add_rxsc(struct macsec_context *ctx) +{ + int32 ret = 0; + uint32 sc_id = 0; + rtk_macsec_sc_t sc; + memset(&sc, 0x0, sizeof(rtk_macsec_sc_t)); + + PR_DBG("[%s] ctx->prepare: %u\n", __FUNCTION__, ctx->prepare); + if (ctx->prepare) + { + return 0; + } + + ret = rtk_phylib_macsec_sci_to_scid(ctx->phydev, RTK_MACSEC_DIR_INGRESS, ctx->rx_sc->sci, &sc_id); + if(ret != RTK_PHYLIB_ERR_ENTRY_NOTFOUND) //sc is existed + { + PR_DBG("[%s] ret:%d sc_id:%d is existed \n", __FUNCTION__, ret, sc_id); + return -EEXIST; + } + PR_DBG("[%s]rx_sc->sci: 0x%llX\n", __FUNCTION__, ctx->rx_sc->sci); + + switch (ctx->secy->key_len) + { + case 16: + sc.rx.cipher_suite = (ctx->secy->xpn) ? RTK_MACSEC_CIPHER_GCM_ASE_XPN_128 : RTK_MACSEC_CIPHER_GCM_ASE_128; + break; + case 32: + sc.rx.cipher_suite = (ctx->secy->xpn) ? RTK_MACSEC_CIPHER_GCM_ASE_XPN_256 : RTK_MACSEC_CIPHER_GCM_ASE_256; + break; + default: + PR_ERR("Not support key_len %d\n", ctx->secy->key_len); + return -EINVAL; + } + + PR_DBG("[%s]rx_sc->sci: 0x%llX\n", __FUNCTION__, ctx->rx_sc->sci); + RTK_PHYLIB_VAL_TO_BYTE_ARRAY(ctx->rx_sc->sci, 8, sc.rx.sci, 0, 8); + sc.rx.flow_match = RTK_MACSEC_MATCH_SCI; + + switch (ctx->secy->validate_frames) + { + case MACSEC_VALIDATE_DISABLED: + sc.rx.validate_frames = RTK_MACSEC_VALIDATE_DISABLE; + break; + case MACSEC_VALIDATE_CHECK: + sc.rx.validate_frames = RTK_MACSEC_VALIDATE_CHECK; + break; + case MACSEC_VALIDATE_STRICT: + sc.rx.validate_frames = RTK_MACSEC_VALIDATE_STRICT; + break; + default: + PR_ERR("Not support validate_frames %d\n", ctx->secy->validate_frames); + return -EINVAL; + } + + sc.rx.replay_protect = ctx->secy->replay_protect; + sc.rx.replay_window = ctx->secy->replay_window; + + RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_sc_create(ctx->phydev, RTK_MACSEC_DIR_INGRESS, &sc, &sc_id, (ctx->rx_sc->active) ? 1 : 0)); + return ret; +} + +static int rtk_macsec_del_rxsc(struct macsec_context *ctx) +{ + int32 ret = 0; + uint32 sc_id = 0; + + PR_DBG("[%s] ctx->prepare: %u\n", __FUNCTION__, ctx->prepare); + if (ctx->prepare) + { + return 0; + } + + RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_sci_to_scid(ctx->phydev, RTK_MACSEC_DIR_INGRESS, ctx->rx_sc->sci, &sc_id)); + RTK_PHYLIB_ERR_CHK(__rtk_macsec_clear_rxsc(ctx, sc_id)); + + return ret; +} + +static int rtk_macsec_upd_rxsc(struct macsec_context *ctx) +{ + int32 ret = 0; + uint32 sc_id = 0; + rtk_macsec_sc_t sc; + rtk_macsec_sc_t cur_sc; + + if (ctx->prepare) + { + return 0; + } + + ret = rtk_phylib_macsec_sci_to_scid(ctx->phydev, RTK_MACSEC_DIR_INGRESS, ctx->rx_sc->sci, &sc_id); + if(ret == RTK_PHYLIB_ERR_ENTRY_NOTFOUND) //sc is not existed + { + PR_DBG("[%s] ret:%d sc_id:%d is not existed \n", __FUNCTION__, ret, sc_id); + return -ENOENT; + } + PR_DBG("[%s]rx_sc->sci: 0x%llX\n", __FUNCTION__, ctx->rx_sc->sci); + + RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_sc_get(ctx->phydev, RTK_MACSEC_DIR_INGRESS, sc_id, &sc)); + memcpy(&cur_sc, &sc, sizeof(rtk_macsec_sc_t)); + + switch (ctx->secy->key_len) + { + case 16: + sc.rx.cipher_suite = (ctx->secy->xpn) ? RTK_MACSEC_CIPHER_GCM_ASE_XPN_128 : RTK_MACSEC_CIPHER_GCM_ASE_128; + break; + case 32: + sc.rx.cipher_suite = (ctx->secy->xpn) ? RTK_MACSEC_CIPHER_GCM_ASE_XPN_256 : RTK_MACSEC_CIPHER_GCM_ASE_256; + break; + default: + PR_ERR("Not support key_len %d\n", ctx->secy->key_len); + return -EINVAL; + } + + PR_DBG("[%s]rx_sc->sci: 0x%llX\n", __FUNCTION__, ctx->rx_sc->sci); + RTK_PHYLIB_VAL_TO_BYTE_ARRAY(ctx->rx_sc->sci, 8, sc.rx.sci, 0, 8); + sc.rx.flow_match = RTK_MACSEC_MATCH_SCI; + + switch (ctx->secy->validate_frames) + { + case MACSEC_VALIDATE_DISABLED: + sc.rx.validate_frames = RTK_MACSEC_VALIDATE_DISABLE; + break; + case MACSEC_VALIDATE_CHECK: + sc.rx.validate_frames = RTK_MACSEC_VALIDATE_CHECK; + break; + case MACSEC_VALIDATE_STRICT: + sc.rx.validate_frames = RTK_MACSEC_VALIDATE_STRICT; + break; + default: + PR_ERR("Not support validate_frames %d\n", ctx->secy->validate_frames); + return -EINVAL; + } + + sc.rx.replay_protect = ctx->secy->replay_protect; + sc.rx.replay_window = ctx->secy->replay_window; + + if(memcmp(&cur_sc, &sc, sizeof(rtk_macsec_sc_t)) != 0) + RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_sc_update(ctx->phydev, RTK_MACSEC_DIR_INGRESS, &sc, &sc_id, (ctx->rx_sc->active) ? 1 : 0)); + + return ret; +} + +static int __rtk_macsec_set_rxsa(struct macsec_context *ctx, bool update) +{ + int32 ret = 0; + uint32 sc_id = 0; + rtk_macsec_sa_t sa; + memset(&sa, 0x0, sizeof(rtk_macsec_sa_t)); + + RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_sci_to_scid(ctx->phydev, RTK_MACSEC_DIR_INGRESS, ctx->sa.rx_sa->sc->sci, &sc_id)); + + if (update) + { + RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_sa_get(ctx->phydev, RTK_MACSEC_DIR_INGRESS, sc_id, ctx->sa.assoc_num, &sa)); + } + else + { + sa.key_bytes = ctx->secy->key_len; + memcpy(sa.key, ctx->sa.key, sa.key_bytes); + if(ctx->secy->xpn) + { + memcpy(sa.salt, ctx->sa.rx_sa->key.salt.bytes, MACSEC_SALT_LEN); + RTK_PHYLIB_VAL_TO_BYTE_ARRAY(ctx->sa.rx_sa->ssci, 4, sa.ssci, 0, 4); + } + } + + sa.pn = ctx->sa.tx_sa->next_pn_halves.lower; + sa.pn_h = ctx->sa.tx_sa->next_pn_halves.upper; + + #ifdef MACSEC_DBG_PRINT + { + PR_DBG("[%s,%d] update:%u \n", __FUNCTION__, __LINE__, update); + PR_DBG(" KEY 0-15 = 0x%02X%02X%02X%02X%02X%02X%02X%02X %02X%02X%02X%02X%02X%02X%02X%02X\n", + sa.key[0], sa.key[1], sa.key[2], sa.key[3], + sa.key[4], sa.key[5], sa.key[6], sa.key[7], + sa.key[8], sa.key[9], sa.key[10],sa.key[11], + sa.key[12],sa.key[13],sa.key[14],sa.key[15]); + if (ctx->secy->key_len == 32) + { + PR_DBG(" KEY16-31 = 0x%02X%02X%02X%02X%02X%02X%02X%02X %02X%02X%02X%02X%02X%02X%02X%02X\n", + sa.key[16],sa.key[17],sa.key[18],sa.key[19], + sa.key[20],sa.key[21],sa.key[22],sa.key[23], + sa.key[24],sa.key[25],sa.key[26],sa.key[27], + sa.key[28],sa.key[29],sa.key[30],sa.key[31]); + } + PR_DBG(" ctx->sa.rx_sa->active: %u\n", ctx->sa.rx_sa->active); + PR_DBG(" ctx->secy->xpn: %u\n", ctx->secy->xpn); + PR_DBG(" sa.pn: 0x%X, sa.pn_h: 0x%X\n", sa.pn, sa.pn_h); + if(ctx->secy->xpn) + { + PR_DBG(" ctx->sa.tx_sa->key.salt = 0x%02X%02X%02X%02X %02X%02X%02X%02X %02X%02X%02X%02X\n", + sa.salt[0], sa.salt[1], sa.salt[2], sa.salt[3], + sa.salt[4], sa.salt[5], sa.salt[6], sa.salt[7], + sa.salt[8], sa.salt[9], sa.salt[10], sa.salt[11]); + } + } + #endif + + RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_sa_create(ctx->phydev, RTK_MACSEC_DIR_INGRESS, sc_id, ctx->sa.assoc_num, &sa)); + + if (ctx->sa.rx_sa->active) + { + RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_sa_activate(ctx->phydev, RTK_MACSEC_DIR_INGRESS, sc_id, ctx->sa.assoc_num)); + } + else + { + RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_rxsa_disable(ctx->phydev, sc_id, ctx->sa.assoc_num)); + } + + return ret; +} + +static int rtk_macsec_add_rxsa(struct macsec_context *ctx) +{ + int32 ret = 0; + uint32 sc_id = 0, sa_id = 0; + struct rtk_phy_priv *priv = ctx->phydev->priv; + rtk_macsec_port_info_t *macsec_db = priv->macsec; + + PR_DBG("[%s] ctx->prepare: %u\n", __FUNCTION__, ctx->prepare); + if (ctx->prepare) + { + return 0; + } + RTK_PHYLIB_ERR_CHK(__rtk_macsec_set_rxsa(ctx, false)); + + RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_sci_to_scid(ctx->phydev, RTK_MACSEC_DIR_INGRESS, ctx->sa.rx_sa->sc->sci, &sc_id)); + sa_id = PHY_MACSEC_HW_SA_ID(sc_id, ctx->sa.assoc_num); + macsec_db->rxsa_stats[sa_id] = kzalloc(sizeof(rtk_macsec_rxsa_stats_t), GFP_KERNEL); + if (macsec_db->rxsa_stats[sa_id] == NULL) + { + rtk_macsec_del_rxsa(ctx); + return -ENOMEM; + } + + return ret; +} + +static int rtk_macsec_del_rxsa(struct macsec_context *ctx) +{ + int32 ret = 0; + uint32 sc_id = 0, sa_id = 0; + struct rtk_phy_priv *priv = ctx->phydev->priv; + rtk_macsec_port_info_t *macsec_db = priv->macsec; + + PR_DBG("[%s] ctx->prepare: %u\n", __FUNCTION__, ctx->prepare); + if (ctx->prepare) + { + return 0; + } + RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_sci_to_scid(ctx->phydev, RTK_MACSEC_DIR_INGRESS, ctx->sa.rx_sa->sc->sci, &sc_id)); + RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_sa_del(ctx->phydev, RTK_MACSEC_DIR_INGRESS, sc_id, ctx->sa.assoc_num)); + + sa_id = PHY_MACSEC_HW_SA_ID(sc_id, ctx->sa.assoc_num); + if (macsec_db->rxsa_stats[sa_id] != NULL) + { + kfree(macsec_db->rxsa_stats[sa_id]); + macsec_db->rxsa_stats[sa_id] = NULL; + } + + return ret; +} + +static int rtk_macsec_upd_rxsa(struct macsec_context *ctx) +{ + int32 ret = 0; + + PR_DBG("[%s] ctx->prepare: %u\n", __FUNCTION__, ctx->prepare); + if (ctx->prepare) + { + return 0; + } + RTK_PHYLIB_ERR_CHK(__rtk_macsec_set_rxsa(ctx, true)); + return ret; +} + +static int __rtk_macsec_set_txsa(struct macsec_context *ctx, bool update) +{ + int32 ret = 0; + uint32 sc_id = 0; + rtk_macsec_sa_t sa; + memset(&sa, 0x0, sizeof(rtk_macsec_sa_t)); + + RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_sci_to_scid(ctx->phydev, RTK_MACSEC_DIR_EGRESS, ctx->secy->sci, &sc_id)); + + if (update) + { + RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_sa_get(ctx->phydev, RTK_MACSEC_DIR_EGRESS, sc_id, ctx->sa.assoc_num, &sa)); + } + else + { + sa.key_bytes = ctx->secy->key_len; + memcpy(sa.key, ctx->sa.key, sa.key_bytes); + if(ctx->secy->xpn) + { + memcpy(sa.salt, ctx->sa.tx_sa->key.salt.bytes, MACSEC_SALT_LEN); + RTK_PHYLIB_VAL_TO_BYTE_ARRAY(ctx->sa.tx_sa->ssci, 4, sa.ssci, 0, 4); + } + } + + sa.pn = ctx->sa.tx_sa->next_pn_halves.lower; + sa.pn_h = ctx->sa.tx_sa->next_pn_halves.upper; + + #ifdef MACSEC_DBG_PRINT + { + PR_DBG("[%s,%d] update:%u \n", __FUNCTION__, __LINE__, update); + PR_DBG(" KEY 0-15 = 0x%02X%02X%02X%02X%02X%02X%02X%02X %02X%02X%02X%02X%02X%02X%02X%02X\n", + sa.key[0], sa.key[1], sa.key[2], sa.key[3], + sa.key[4], sa.key[5], sa.key[6], sa.key[7], + sa.key[8], sa.key[9], sa.key[10],sa.key[11], + sa.key[12],sa.key[13],sa.key[14],sa.key[15]); + if (ctx->secy->key_len == 32) + { + PR_DBG(" KEY16-31 = 0x%02X%02X%02X%02X%02X%02X%02X%02X %02X%02X%02X%02X%02X%02X%02X%02X\n", + sa.key[16],sa.key[17],sa.key[18],sa.key[19], + sa.key[20],sa.key[21],sa.key[22],sa.key[23], + sa.key[24],sa.key[25],sa.key[26],sa.key[27], + sa.key[28],sa.key[29],sa.key[30],sa.key[31]); + } + PR_DBG(" ctx->sa.tx_sa->active: %u\n", ctx->sa.tx_sa->active); + PR_DBG(" ctx->secy->xpn: %u\n", ctx->secy->xpn); + PR_DBG(" sa.pn: 0x%X, sa.pn_h: 0x%X\n", sa.pn, sa.pn_h); + if(ctx->secy->xpn) + { + PR_DBG(" ctx->sa.tx_sa->key.salt = 0x%02X%02X%02X%02X %02X%02X%02X%02X %02X%02X%02X%02X\n", + sa.salt[0], sa.salt[1], sa.salt[2], sa.salt[3], + sa.salt[4], sa.salt[5], sa.salt[6], sa.salt[7], + sa.salt[8], sa.salt[9], sa.salt[10], sa.salt[11]); + } + } + #endif + + RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_sa_create(ctx->phydev, RTK_MACSEC_DIR_EGRESS, sc_id, ctx->sa.assoc_num, &sa)); + + if (ctx->sa.tx_sa->active) + { + RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_sa_activate(ctx->phydev, RTK_MACSEC_DIR_EGRESS, sc_id, ctx->sa.assoc_num)); + } + else + { + RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_txsa_disable(ctx->phydev, sc_id)); + + } + return ret; +} + +static int rtk_macsec_add_txsa(struct macsec_context *ctx) +{ + int32 ret = 0; + uint32 sc_id = 0, sa_id = 0; + struct rtk_phy_priv *priv = ctx->phydev->priv; + rtk_macsec_port_info_t *macsec_db = priv->macsec; + + + PR_DBG("[%s] ctx->prepare: %u\n", __FUNCTION__, ctx->prepare); + if (ctx->prepare) + { + return 0; + } + RTK_PHYLIB_ERR_CHK(__rtk_macsec_set_txsa(ctx, false)); + + RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_sci_to_scid(ctx->phydev, RTK_MACSEC_DIR_EGRESS, ctx->secy->sci, &sc_id)); + sa_id = PHY_MACSEC_HW_SA_ID(sc_id, ctx->sa.assoc_num); + macsec_db->txsa_stats[sa_id] = kzalloc(sizeof(rtk_macsec_txsa_stats_t), GFP_KERNEL); + if (macsec_db->txsa_stats[sa_id] == NULL) + { + rtk_macsec_del_txsa(ctx); + return -ENOMEM; + } + + return ret; +} + +static int rtk_macsec_del_txsa(struct macsec_context *ctx) +{ + int32 ret = 0; + uint32 sc_id = 0, sa_id = 0; + struct rtk_phy_priv *priv = ctx->phydev->priv; + rtk_macsec_port_info_t *macsec_db = priv->macsec; + + + PR_DBG("[%s] ctx->prepare: %u\n", __FUNCTION__, ctx->prepare); + if (ctx->prepare) + { + return 0; + } + RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_sci_to_scid(ctx->phydev, RTK_MACSEC_DIR_EGRESS, ctx->secy->sci, &sc_id)); + RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_sa_del(ctx->phydev, RTK_MACSEC_DIR_EGRESS, sc_id, ctx->sa.assoc_num)); + + sa_id = PHY_MACSEC_HW_SA_ID(sc_id, ctx->sa.assoc_num); + if (macsec_db->txsa_stats[sa_id] != NULL) + { + kfree(macsec_db->txsa_stats[sa_id]); + macsec_db->txsa_stats[sa_id] = NULL; + } + + return ret; +} + +static int rtk_macsec_upd_txsa(struct macsec_context *ctx) +{ + int32 ret = 0; + + PR_DBG("[%s] ctx->prepare: %u\n", __FUNCTION__, ctx->prepare); + if (ctx->prepare) + { + return 0; + } + RTK_PHYLIB_ERR_CHK(__rtk_macsec_set_txsa(ctx, true)); + return ret; +} + + +static int rtk_macsec_get_dev_stats(struct macsec_context *ctx) +{ + int32 ret = 0; + uint64 cnt = 0; + uint32 sc_id = 0, an = 0; + + if (ctx->prepare) + { + return 0; + } + + RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_stat_port_get(ctx->phydev, RTK_MACSEC_STAT_OutPktsUntagged, &cnt)); + ctx->stats.dev_stats->OutPktsUntagged = cnt; + + RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_stat_port_get(ctx->phydev, RTK_MACSEC_STAT_InPktsUntagged, &cnt)); + ctx->stats.dev_stats->InPktsUntagged = cnt; + + RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_stat_port_get(ctx->phydev, RTK_MACSEC_STAT_InPktsNoTag, &cnt)); + ctx->stats.dev_stats->InPktsNoTag = cnt; + + RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_stat_port_get(ctx->phydev, RTK_MACSEC_STAT_InPktsBadTag, &cnt)); + ctx->stats.dev_stats->InPktsBadTag = cnt; + + RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_stat_port_get(ctx->phydev, RTK_MACSEC_STAT_InPktsUnknownSCI, &cnt)); + ctx->stats.dev_stats->InPktsUnknownSCI = cnt; + + RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_stat_port_get(ctx->phydev, RTK_MACSEC_STAT_InPktsNoSCI, &cnt)); + ctx->stats.dev_stats->InPktsNoSCI = cnt; + + ctx->stats.dev_stats->InPktsOverrun = 0; /* not support */ + + /* accumulate over each egress SA */ + RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_sci_to_scid(ctx->phydev, RTK_MACSEC_DIR_EGRESS, ctx->secy->sci, &sc_id)); + for (an = 0; an < MACSEC_NUM_AN; an++) + { + if (0 == rtk_phylib_macsec_stat_txsa_get(ctx->phydev, sc_id, an, RTK_MACSEC_TXSA_STAT_OutPktsTooLong, &cnt)) + { + ctx->stats.dev_stats->OutPktsTooLong += cnt; + } + } + + return ret; +} + +static int rtk_macsec_get_txsc_stats(struct macsec_context *ctx) +{ + int32 ret = 0; + uint64 cnt = 0; + uint32 sc_id = 0, an = 0; + + if (ctx->prepare) + { + return 0; + } + + RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_sci_to_scid(ctx->phydev, RTK_MACSEC_DIR_EGRESS, ctx->secy->sci, &sc_id)); + + /* accumulate over each egress SA */ + for (an = 0; an < MACSEC_NUM_AN; an++) + { + if (0 == rtk_phylib_macsec_stat_txsa_get(ctx->phydev, sc_id, an, RTK_MACSEC_TXSA_STAT_OutPktsProtectedEncrypted, &cnt)) + { + if (ctx->secy->tx_sc.encrypt) + { + ctx->stats.tx_sc_stats->OutPktsEncrypted += cnt; + } + else + { + ctx->stats.tx_sc_stats->OutPktsProtected += cnt; + } + } + + if (0 == rtk_phylib_macsec_stat_txsa_get(ctx->phydev, sc_id, an, RTK_MACSEC_TXSA_STAT_OutOctetsProtectedEncrypted, &cnt)) + { + if (ctx->secy->tx_sc.encrypt) + { + ctx->stats.tx_sc_stats->OutOctetsEncrypted += cnt; + } + else + { + ctx->stats.tx_sc_stats->OutOctetsProtected += cnt; + } + } + + } + + return ret; +} + +static int rtk_macsec_get_rxsc_stats(struct macsec_context *ctx) +{ + int32 ret = 0; + uint64 cnt = 0; + uint32 sc_id = 0, an = 0; + + if (ctx->prepare) + { + return 0; + } + + RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_sci_to_scid(ctx->phydev, RTK_MACSEC_DIR_INGRESS, ctx->rx_sc->sci, &sc_id)); + + /* accumulate over each ingress SA */ + for (an = 0; an < MACSEC_NUM_AN; an++) + { + if (0 == rtk_phylib_macsec_stat_rxsa_get(ctx->phydev, sc_id, an, RTK_MACSEC_RXSA_STAT_InOctetsDecryptedValidated, &cnt)) + { + ctx->stats.rx_sc_stats->InOctetsValidated += cnt; + ctx->stats.rx_sc_stats->InOctetsDecrypted = ctx->stats.rx_sc_stats->InOctetsValidated; + } + if (0 == rtk_phylib_macsec_stat_rxsa_get(ctx->phydev, sc_id, an, RTK_MACSEC_RXSA_STAT_InPktsUnchecked, &cnt)) + { + ctx->stats.rx_sc_stats->InPktsUnchecked += cnt; + } + if (0 == rtk_phylib_macsec_stat_rxsa_get(ctx->phydev, sc_id, an, RTK_MACSEC_RXSA_STAT_InPktsDelayed, &cnt)) + { + ctx->stats.rx_sc_stats->InPktsDelayed += cnt; + } + if (0 == rtk_phylib_macsec_stat_rxsa_get(ctx->phydev, sc_id, an, RTK_MACSEC_RXSA_STAT_InPktsOK, &cnt)) + { + ctx->stats.rx_sc_stats->InPktsOK += cnt; + } + if (0 == rtk_phylib_macsec_stat_rxsa_get(ctx->phydev, sc_id, an, RTK_MACSEC_RXSA_STAT_InPktsInvalid, &cnt)) + { + ctx->stats.rx_sc_stats->InPktsInvalid += cnt; + } + if (0 == rtk_phylib_macsec_stat_rxsa_get(ctx->phydev, sc_id, an, RTK_MACSEC_RXSA_STAT_InPktsLate, &cnt)) + { + ctx->stats.rx_sc_stats->InPktsLate += cnt; + } + if (0 == rtk_phylib_macsec_stat_rxsa_get(ctx->phydev, sc_id, an, RTK_MACSEC_RXSA_STAT_InPktsNotValid, &cnt)) + { + ctx->stats.rx_sc_stats->InPktsNotValid += cnt; + } + if (0 == rtk_phylib_macsec_stat_rxsa_get(ctx->phydev, sc_id, an, RTK_MACSEC_RXSA_STAT_InPktsNotUsingSA, &cnt)) + { + ctx->stats.rx_sc_stats->InPktsNotUsingSA += cnt; + } + if (0 == rtk_phylib_macsec_stat_rxsa_get(ctx->phydev, sc_id, an, RTK_MACSEC_RXSA_STAT_InPktsUnusedSA, &cnt)) + { + ctx->stats.rx_sc_stats->InPktsUnusedSA += cnt; + } + } + + return ret; +} + +static int rtk_macsec_get_txsa_stats(struct macsec_context *ctx) +{ + int32 ret = 0; + uint64 cnt = 0; + uint32 sc_id = 0; + rtk_macsec_sa_t sa; + + if (ctx->prepare) + { + return 0; + } + + RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_sci_to_scid(ctx->phydev, RTK_MACSEC_DIR_EGRESS, ctx->secy->sci, &sc_id)); + + RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_stat_txsa_get(ctx->phydev, sc_id, ctx->sa.assoc_num, RTK_MACSEC_TXSA_STAT_OutPktsProtectedEncrypted, &cnt)); + if (ctx->secy->tx_sc.encrypt) + { + ctx->stats.tx_sa_stats->OutPktsEncrypted = (uint32)cnt; + } + else + { + ctx->stats.tx_sa_stats->OutPktsProtected = (uint32)cnt; + } + + RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_sa_get(ctx->phydev, RTK_MACSEC_DIR_EGRESS, sc_id, ctx->sa.assoc_num, &sa)); + ctx->sa.tx_sa->next_pn_halves.lower = sa.pn; + ctx->sa.tx_sa->next_pn_halves.upper = sa.pn_h; + + return ret; +} + +static int rtk_macsec_get_rxsa_stats(struct macsec_context *ctx) +{ + int32 ret = 0; + uint64 cnt = 0; + uint32 sc_id = 0; + rtk_macsec_sa_t sa; + + if (ctx->prepare) + { + return 0; + } + + RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_sci_to_scid(ctx->phydev, RTK_MACSEC_DIR_INGRESS, ctx->rx_sc->sci, &sc_id)); + + RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_stat_rxsa_get(ctx->phydev, sc_id, ctx->sa.assoc_num, RTK_MACSEC_RXSA_STAT_InPktsOK, &cnt)); + ctx->stats.rx_sa_stats->InPktsOK = (uint32)cnt; + + RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_stat_rxsa_get(ctx->phydev, sc_id, ctx->sa.assoc_num, RTK_MACSEC_RXSA_STAT_InPktsInvalid, &cnt)); + ctx->stats.rx_sa_stats->InPktsInvalid = (uint32)cnt; + + RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_stat_rxsa_get(ctx->phydev, sc_id, ctx->sa.assoc_num, RTK_MACSEC_RXSA_STAT_InPktsNotValid, &cnt)); + ctx->stats.rx_sa_stats->InPktsNotValid = (uint32)cnt; + + RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_stat_rxsa_get(ctx->phydev, sc_id, ctx->sa.assoc_num, RTK_MACSEC_RXSA_STAT_InPktsNotUsingSA, &cnt)); + ctx->stats.rx_sa_stats->InPktsNotUsingSA = (uint32)cnt; + + RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_stat_rxsa_get(ctx->phydev, sc_id, ctx->sa.assoc_num, RTK_MACSEC_RXSA_STAT_InPktsUnusedSA, &cnt)); + ctx->stats.rx_sa_stats->InPktsUnusedSA = (uint32)cnt; + + RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_sa_get(ctx->phydev, RTK_MACSEC_DIR_INGRESS, sc_id, ctx->sa.assoc_num, &sa)); + ctx->sa.rx_sa->next_pn_halves.lower = sa.pn; + ctx->sa.rx_sa->next_pn_halves.upper = sa.pn_h; + + return ret; +} + +static const struct macsec_ops rtk_macsec_ops = { + /* Device wide */ + .mdo_dev_open = rtk_macsec_dev_open, + .mdo_dev_stop = rtk_macsec_dev_stop, + /* SecY */ + .mdo_add_secy = rtk_macsec_add_secy, + .mdo_upd_secy = rtk_macsec_upd_secy, + .mdo_del_secy = rtk_macsec_del_secy, + /* Security channels */ + .mdo_add_rxsc = rtk_macsec_add_rxsc, + .mdo_upd_rxsc = rtk_macsec_upd_rxsc, + .mdo_del_rxsc = rtk_macsec_del_rxsc, + /* Security associations */ + .mdo_add_rxsa = rtk_macsec_add_rxsa, + .mdo_upd_rxsa = rtk_macsec_upd_rxsa, + .mdo_del_rxsa = rtk_macsec_del_rxsa, + .mdo_add_txsa = rtk_macsec_add_txsa, + .mdo_upd_txsa = rtk_macsec_upd_txsa, + .mdo_del_txsa = rtk_macsec_del_txsa, + /* Statistics */ + .mdo_get_dev_stats = rtk_macsec_get_dev_stats, + .mdo_get_tx_sc_stats = rtk_macsec_get_txsc_stats, + .mdo_get_rx_sc_stats = rtk_macsec_get_rxsc_stats, + .mdo_get_tx_sa_stats = rtk_macsec_get_txsa_stats, + .mdo_get_rx_sa_stats = rtk_macsec_get_rxsa_stats, +}; + +int rtk_macsec_init(struct phy_device *phydev) +{ + int32 ret = 0; + struct rtk_phy_priv *priv = phydev->priv; + + priv->macsec = kzalloc(sizeof(*(priv->macsec)), GFP_KERNEL); + if (!priv->macsec) + return -ENOMEM; + memset(priv->macsec, 0, sizeof(*(priv->macsec))); + + switch (phydev->drv->phy_id) + { + case REALTEK_PHY_ID_RTL8261N: + case REALTEK_PHY_ID_RTL8264B: + phydev->macsec_ops = &rtk_macsec_ops; + priv->macsec->max_sa_num = 64; + priv->macsec->max_sc_num = 64/4; + ret = rtk_phylib_826xb_macsec_init(phydev); + if (ret != 0) + { + phydev_err(phydev, "[%s]rtk_phylib_826xb_macsec_init failed!! 0x%X\n", __FUNCTION__, ret); + return ret; + } + break; + default: + PR_ERR("[%s]phy_id: 0x%X not support!\n", __FUNCTION__, phydev->drv->phy_id); + kfree(priv->macsec); + priv->macsec = NULL; + return -EOPNOTSUPP; + } + + RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_init(phydev)); + + return 0; +} diff --git a/sources/rtk-be550/src/hal/phy/rtk_osal.c b/sources/rtk-be550/src/hal/phy/rtk_osal.c new file mode 100755 index 00000000..bf3ac4b1 --- /dev/null +++ b/sources/rtk-be550/src/hal/phy/rtk_osal.c @@ -0,0 +1,56 @@ +/* + * SPDX-License-Identifier: GPL-2.0-only + * + * Copyright (c) 2023 Realtek Semiconductor Corp. All rights reserved. + */ + +#include "type.h" +#include "error.h" +#include "rtk_phylib_def.h" + +#include +#include +#include +#include +#include +#include +#include +#include + +int32 +osal_time_usecs_get(osal_usecs_t *pUsec) +{ + struct timespec64 ts; + + RT_PARAM_CHK((NULL == pUsec), RT_ERR_NULL_POINTER); + + ktime_get_ts64(&ts); + *pUsec = (osal_usecs_t)((ts.tv_sec * USEC_PER_SEC) + (ts.tv_nsec / NSEC_PER_USEC)); + return RT_ERR_OK; +} + +void * +osal_alloc(uint32 size) +{ + void *p; + p = kmalloc((size_t)size, GFP_ATOMIC); + return p; +} + +int32 +phy_common_general_reg_mmd_get(uint32 unit, rtk_port_t port, uint32 mmdAddr, uint32 mmdReg, uint32 *pData) +{ + int32 rData = 0; + rData = phy_read_mmd(port, mmdAddr, mmdReg); + if (rData < 0) + return RT_ERR_FAILED; + *pData = (uint32)rData; + return RT_ERR_OK; +} + +int32 +phy_common_general_reg_mmd_set(uint32 unit, rtk_port_t port, uint32 mmdAddr, uint32 mmdReg, uint32 data) +{ + int ret = phy_write_mmd(port, mmdAddr, mmdReg, data); + return (ret < 0) ? RT_ERR_FAILED : RT_ERR_OK; +} diff --git a/sources/rtk-be550/src/hal/phy/rtk_osal.h b/sources/rtk-be550/src/hal/phy/rtk_osal.h new file mode 100755 index 00000000..edf67461 --- /dev/null +++ b/sources/rtk-be550/src/hal/phy/rtk_osal.h @@ -0,0 +1,99 @@ +/* + * SPDX-License-Identifier: GPL-2.0-only + * + * Copyright (c) 2023 Realtek Semiconductor Corp. All rights reserved. + */ + +#ifndef __RTK_PHY_OSAL_H +#define __RTK_PHY_OSAL_H + +#include +#include +#include "type.h" +#include "error.h" +#include "phy_patch.h" +#include "rtk_phylib.h" + +#ifdef PHYPATCH_DB_GET + #undef PHYPATCH_DB_GET +#endif + +#define PHYPATCH_DB_GET(_unit, _pPhy_device, _pPatchDb) \ + do { \ + struct rtk_phy_priv *_pPriv = (_pPhy_device)->priv; \ + rt_phy_patch_db_t *_pDb = _pPriv->patch; _pPatchDb = _pDb; \ + /*printk("[PHYPATCH_DB_GET] ? [%s]\n", (_pDb != NULL) ? "E":"N");*/ \ + } while(0) + +#define HWP_9300_FAMILY_ID(_unit) 0 +#define HWP_9310_FAMILY_ID(_unit) 0 +#define RTK_9300_FAMILY_ID(_unit) 0 +#define RTK_9310_FAMILY_ID(_unit) 0 +#define RTK_9311B_FAMILY_ID(_unit) 0 +#define RTK_9330_FAMILY_ID(_unit) 0 + +#ifndef WAIT_COMPLETE_VAR +#define WAIT_COMPLETE_VAR() \ + osal_usecs_t _t, _now, _t_wait=0, _timeout; \ + int32 _chkCnt=0; + +#define WAIT_COMPLETE(_timeout_us) \ + _timeout = _timeout_us; \ + for(osal_time_usecs_get(&_t),osal_time_usecs_get(&_now),_t_wait=0,_chkCnt=0 ; \ + (_t_wait <= _timeout); \ + osal_time_usecs_get(&_now), _chkCnt++, _t_wait += ((_now >= _t) ? (_now - _t) : (0xFFFFFFFF - _t + _now)),_t = _now \ + ) + +#define WAIT_COMPLETE_IS_TIMEOUT() (_t_wait > _timeout) +#endif + +/* OSAL */ +#include +int32 osal_time_usecs_get(osal_usecs_t *pUsec); +void *osal_alloc(uint32 size); +#define osal_time_mdelay mdelay + +#include /* for Kernel Space */ +#include +#include +#define osal_strlen strlen +#define osal_strcmp strcmp +#define osal_strcpy strcpy +#define osal_strncpy strncpy +#define osal_strcat strcat +#define osal_strchr strchr +#define osal_memset memset +#define osal_memcpy memcpy +#define osal_memcmp memcmp +#define osal_strdup strdup +#define osal_strncmp strncmp +#define osal_strstr strstr +#define osal_strtok strtok +#define osal_strtok_r strtok_r +#define osal_toupper toupper + +#define osal_printf printk + +/* HWP */ +#define HWP_PORT_SMI(unit, port) 0 +#define HWP_PHY_MODEL_BY_PORT(unit, port) 0 +#define HWP_PHY_ADDR(unit, port) 0 +#define HWP_PHY_BASE_MACID(unit, p) 0 +#define HWP_PORT_TRAVS_EXCEPT_CPU(unit, p) if (bcast_phyad < 0x1F && p != NULL) + + +/* RT_LOG */ +//#define RT_LOG(level, module, fmt, args...) do { printk("RT_LOG:"fmt, ## args); } while(0) +#define RT_LOG(level, module, fmt, args...) do {} while(0) +#define RT_ERR(error_code, module, fmt, args...) do {} while(0) +#define RT_INIT_ERR(error_code, module, fmt, args...) do {} while(0) +#define RT_INIT_MSG(fmt, args...) do {} while(0) + +#define phy_826xb_ctrl_set(unit, p, RTK_PHY_CTRL_MIIM_BCAST_PHYAD, bcast_phyad) 0 + +/* reg access */ +int32 phy_common_general_reg_mmd_get(uint32 unit, rtk_port_t port, uint32 mmdAddr, uint32 mmdReg, uint32 *pData); +int32 phy_common_general_reg_mmd_set(uint32 unit, rtk_port_t port, uint32 mmdAddr, uint32 mmdReg, uint32 data); + + +#endif /* __RTK_PHY_OSAL_H */ diff --git a/sources/rtk-be550/src/hal/phy/rtk_phy.c b/sources/rtk-be550/src/hal/phy/rtk_phy.c new file mode 100755 index 00000000..c54b07c3 --- /dev/null +++ b/sources/rtk-be550/src/hal/phy/rtk_phy.c @@ -0,0 +1,654 @@ +/* + * SPDX-License-Identifier: GPL-2.0-only + * + * Copyright (c) 2023 Realtek Semiconductor Corp. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include "phy_rtl826xb_patch.h" + +#include "rtk_phylib_rtl826xb.h" +#include "rtk_phylib_macsec.h" +#include "rtk_phylib.h" + +#include "rtk_phy.h" + +static struct dentry *phy_sm_barrier = NULL; +static struct dentry *allow_phy_up_toggle = NULL; +static unsigned int allow_phy_up = 0; + +static int rtkphy_c45_suspend(struct phy_device *phydev); + +#if 0 +static int rtk_phy_cable_test_report_trans(rtk_rtct_channel_result_t *result) +{ + if(result->cable_status == 0) + return ETHTOOL_A_CABLE_RESULT_CODE_OK; + + if(result->cable_status & RTK_PHYLIB_CABLE_STATUS_INTER_PAIR_SHORT) + return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT; + if(result->cable_status & RTK_PHYLIB_CABLE_STATUS_SHORT) + return ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT; + if(result->cable_status & RTK_PHYLIB_CABLE_STATUS_OPEN) + return ETHTOOL_A_CABLE_RESULT_CODE_OPEN; + if(result->cable_status & RTK_PHYLIB_CABLE_STATUS_CROSS) + return ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT; + + return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC; +} +#endif + +static int rtl826xb_get_features(struct phy_device *phydev) +{ + int ret; + struct rtk_phy_priv *priv = phydev->priv; + + ret = genphy_c45_pma_read_abilities(phydev); + if (ret) + return ret; + + linkmode_or(phydev->supported, phydev->supported, PHY_BASIC_FEATURES); + + linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, + phydev->supported); + linkmode_set_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, + phydev->supported); + linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, + phydev->supported); + linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, + phydev->supported); + /* not support 10M modes */ + linkmode_clear_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, + phydev->supported); + linkmode_clear_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, + phydev->supported); + + switch (priv->phytype) + { + case RTK_PHYLIB_RTL8251L: + case RTK_PHYLIB_RTL8254B: + linkmode_clear_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, + phydev->supported); + break; + + default: + break; + } + + return 0; +} + +static int rtl826xb_probe(struct phy_device *phydev) +{ + struct rtk_phy_priv *priv = NULL; + int data = 0; + + phy_sm_barrier = debugfs_create_dir("rtk_phy_sm_barrier", NULL); + if ( !phy_sm_barrier ) + { + printk("cannot create rtk debugfs dir phy_sm_barrier.\n"); + } + else + { + allow_phy_up_toggle = debugfs_create_u32("allow_phy_up", S_IRUGO | S_IWUSR, phy_sm_barrier, &allow_phy_up); + if ( !allow_phy_up_toggle ) + { + printk("cannot create rtk debugfs allow_phy_up.\n"); + debugfs_remove_recursive(phy_sm_barrier); + phy_sm_barrier = NULL; + } + else + printk("create rtk debugfs allow_phy_up.\n"); + } + + priv = devm_kzalloc(&phydev->mdio.dev, sizeof(struct rtk_phy_priv), GFP_KERNEL); + if (!priv) + { + return -ENOMEM; + } + memset(priv, 0, sizeof(struct rtk_phy_priv)); + + if (phy_rtl826xb_patch_db_init(0, phydev, &(priv->patch)) != RT_ERR_OK) + return -ENOMEM; + + if (phydev->drv->phy_id == REALTEK_PHY_ID_RTL8261N) + { + data = phy_read_mmd(phydev, 30, 0x103); + if (data < 0) + return data; + + if (data == 0x8251) + { + priv->phytype = RTK_PHYLIB_RTL8251L; + } + else + { + priv->phytype = RTK_PHYLIB_RTL8261N; + } + } + else if (phydev->drv->phy_id == REALTEK_PHY_ID_RTL8264B) + { + data = phy_read_mmd(phydev, 30, 0x103); + if (data < 0) + return data; + + if (data == 0x8254) + { + priv->phytype = RTK_PHYLIB_RTL8254B; + } + else + { + priv->phytype = RTK_PHYLIB_RTL8264B; + } + } + priv->isBasePort = (phydev->drv->phy_id == REALTEK_PHY_ID_RTL8261N) ? (1) : (((phydev->mdio.addr % 4) == 0) ? (1) : (0)); + phydev->priv = priv; + + return 0; +} + +static int rtkphy_config_init(struct phy_device *phydev) +{ + int ret = 0; + switch (phydev->drv->phy_id) + { + case REALTEK_PHY_ID_RTL8261N: + case REALTEK_PHY_ID_RTL8264B: + phydev_info(phydev, "%s:%u [RTL8261N/RTL826XB] phy_id: 0x%X PHYAD:%d\n", __FUNCTION__, __LINE__, phydev->drv->phy_id, phydev->mdio.addr); + + #if 1 /* toggle reset */ + phy_write_mmd(phydev, 30, 0x145, 0x0001); + phy_write_mmd(phydev, 30, 0x145, 0x0000); + mdelay(30); + #endif + + ret = phy_patch(0, phydev, 0, PHY_PATCH_MODE_NORMAL); + if (ret) + { + phydev_err(phydev, "%s:%u [RTL8261N/RTL826XB] patch failed!! 0x%X\n", __FUNCTION__, __LINE__, ret); + return ret; + } + + ret = rtk_phylib_826xb_intr_init(phydev); + if (ret) + { + phydev_err(phydev, "%s:%u [RTL8261N/RTL826XB] rtk_phylib_826xb_intr_init failed!! 0x%X\n", __FUNCTION__, __LINE__, ret); + return ret; + } + + ret = rtk_macsec_init(phydev); + if (ret) + { + phydev_err(phydev, "%s:%u [RTL8261N/RTL826XB] rtk_macsec_init failed!! 0x%X\n", __FUNCTION__, __LINE__, ret); + return ret; + } + ret = rtk_phylib_826xb_sds_write(phydev, 6, 3, 15, 0, 0x88C6); + if (ret) + { + phydev_err(phydev, "%s:%u [RTL8261N/RTL826XB] SerDes init failed!! 0x%X\n", __FUNCTION__, __LINE__, ret); + return ret; + } + rtkphy_c45_suspend(phydev); + #if 0 /* Debug: patch check */ + ret = phy_patch(0, phydev, 0, PHY_PATCH_MODE_CMP); + if (ret) + { + phydev_err(phydev, "%s:%u [RTL8261N/RTL826XB] phy_patch failed!! 0x%X\n", __FUNCTION__, __LINE__, ret); + return ret; + } + printk("[%s,%u] patch chk %s\n", __FUNCTION__, __LINE__, (ret == 0) ? "PASS" : "FAIL"); + #endif + #if 0 /* Debug: USXGMII*/ + { + uint32 data = 0; + rtk_phylib_826xb_sds_read(phydev, 0x07, 0x10, 15, 0, &data); + printk("[%s,%u] SDS 0x07, 0x10 : 0x%X\n", __FUNCTION__, __LINE__, data); + rtk_phylib_826xb_sds_read(phydev, 0x06, 0x12, 15, 0, &data); + printk("[%s,%u] SDS 0x06, 0x12 : 0x%X\n", __FUNCTION__, __LINE__, data); + } + { + u16 sdspage = 0x5, sdsreg = 0x0; + u16 regData = (sdspage & 0x3f) | ((sdsreg & 0x1f) << 6) | BIT(15); + u16 readData = 0; + phy_write_mmd(phydev, 30, 323, regData); + do + { + udelay(10); + readData = phy_read_mmd(phydev, 30, 323); + } while ((readData & BIT(15)) != 0); + readData = phy_read_mmd(phydev, 30, 322); + printk("[%s,%d] sds link [%s] (0x%X)\n", __FUNCTION__, __LINE__, (readData & BIT(12)) ? "UP" : "DOWN", readData); + } + #endif + + break; + default: + phydev_err(phydev, "%s:%u Unknow phy_id: 0x%X\n", __FUNCTION__, __LINE__, phydev->drv->phy_id); + return -EPERM; + } + + return ret; +} + +static int rtkphy_c45_suspend(struct phy_device *phydev) +{ + int ret = 0; + + ret = rtk_phylib_c45_power_low(phydev); + + phydev->speed = SPEED_UNKNOWN; + phydev->duplex = DUPLEX_UNKNOWN; + phydev->pause = 0; + phydev->asym_pause = 0; + + return ret; +} + +static int rtkphy_c45_resume(struct phy_device *phydev) +{ + if ( !likely(READ_ONCE(allow_phy_up)) ) + { + return 0; + } + return rtk_phylib_c45_power_normal(phydev); +} + +static int rtkphy_c45_config_aneg(struct phy_device *phydev) +{ + bool changed = false; + u16 reg = 0; + int ret = 0; + u32 adv,status; + + phydev->mdix_ctrl = ETH_TP_MDI_AUTO; + if (phydev->autoneg == AUTONEG_DISABLE) + { + if (phydev->speed != SPEED_100) + { + return -EPERM; + } + return genphy_c45_pma_setup_forced(phydev); + } + + linkmode_and(phydev->advertising, phydev->advertising, + phydev->supported); + + status = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE); + linkmode_mod_bit(ETHTOOL_LINK_MODE_Pause_BIT, + phydev->advertising, status & ADVERTISE_PAUSE_CAP); + linkmode_mod_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, + phydev->advertising, status & ADVERTISE_PAUSE_ASYM); + + adv = linkmode_adv_to_mii_adv_t(phydev->advertising); + + ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE, + ADVERTISE_ALL | ADVERTISE_100BASE4, + adv); + if (ret < 0) + return ret; + if (ret > 0) + changed = true; + + adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising); + + ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, + MDIO_AN_10GBT_CTRL_ADV10G | + MDIO_AN_10GBT_CTRL_ADV5G | + MDIO_AN_10GBT_CTRL_ADV2_5G, adv); + if (ret < 0) + return ret; + if (ret > 0) + changed = true; + + reg = 0; + if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, + phydev->advertising)) + reg |= BIT(9); + + if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, + phydev->advertising)) + reg |= BIT(8); + + ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, 0xA412, + BIT(9) | BIT(8) , reg); + if (ret < 0) + return ret; + if (ret > 0) + changed = true; + + return genphy_c45_check_and_restart_aneg(phydev, changed); +} + +static int rtkphy_c45_aneg_done(struct phy_device *phydev) +{ + return genphy_c45_aneg_done(phydev); +} + +static int rtkphy_c45_read_status(struct phy_device *phydev) +{ + int ret = 0, status = 0; + phydev->speed = SPEED_UNKNOWN; + phydev->duplex = DUPLEX_UNKNOWN; + phydev->pause = 0; + phydev->asym_pause = 0; + + ret = genphy_c45_read_link(phydev); + if (ret) + return ret; + + if (phydev->autoneg == AUTONEG_ENABLE) + { + linkmode_clear_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, + phydev->lp_advertising); + + ret = genphy_c45_read_lpa(phydev); + if (ret) + return ret; + + status = phy_read_mmd(phydev, 31, 0xA414); + if (status < 0) + return status; + linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, + phydev->lp_advertising, status & BIT(11)); + + phy_resolve_aneg_linkmode(phydev); + } + else + { + ret = genphy_c45_read_pma(phydev); + } + + /* mdix*/ + status = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBT_SWAPPOL); + if (status < 0) + return status; + + switch (status & 0x3) + { + case MDIO_PMA_10GBT_SWAPPOL_ABNX | MDIO_PMA_10GBT_SWAPPOL_CDNX: + phydev->mdix = ETH_TP_MDI; + break; + + case 0: + phydev->mdix = ETH_TP_MDI_X; + break; + + default: + phydev->mdix = ETH_TP_MDI_INVALID; + break; + } + + return ret; +} + +static int rtkphy_c45_pcs_loopback(struct phy_device *phydev, bool enable) +{ + return rtk_phylib_c45_pcs_loopback(phydev, (enable == true) ? 1 : 0); +} + +#if 0 +static int rtl826xb_cable_test_start(struct phy_device *phydev) +{ + return rtk_phylib_826xb_cable_test_start(phydev); +} + +static int rtl826xb_cable_test_get_status(struct phy_device *phydev, bool *finished) +{ + uint32 finish_read = 0; + int32 ret = 0; + uint32 pair = 0; + rtk_rtct_channel_result_t reslut; + + *finished = false; + RTK_PHYLIB_ERR_CHK(rtk_phylib_826xb_cable_test_finished_get(phydev, &finish_read)); + *finished = (finish_read == 1) ? true : false; + + if (finish_read == 1) + { + for (pair = 0; pair < 4; pair++) + { + RTK_PHYLIB_ERR_CHK(rtk_phylib_826xb_cable_test_result_get(phydev, pair, &reslut)); + ethnl_cable_test_result(phydev, pair, rtk_phy_cable_test_report_trans(&reslut)); + + if(reslut.cable_status != RTK_PHYLIB_CABLE_STATUS_NORMAL) + ethnl_cable_test_fault_length(phydev, pair, reslut.length_cm); + } + } + return ret; +} +#endif + +static int rtl826xb_config_intr(struct phy_device *phydev) +{ + int32 ret = 0; + + RTK_PHYLIB_ERR_CHK(rtk_phylib_826xb_intr_enable(phydev, (phydev->interrupts == PHY_INTERRUPT_ENABLED)? 1 : 0)); + return ret; +} + +static int rtl826xb_ack_intr(struct phy_device *phydev) +{ + int32 ret = 0; + uint32 status = 0; + + RTK_PHYLIB_ERR_CHK(rtk_phylib_826xb_intr_read_clear(phydev, &status)); + if (status & RTK_PHY_INTR_WOL) + { + rtk_phylib_826xb_wol_reset(phydev); + } + + return ret; +} + +static int rtl826xb_handle_intr(struct phy_device *phydev) +{ + irqreturn_t ret; + uint32 status = 0; + + RTK_PHYLIB_ERR_CHK(rtk_phylib_826xb_intr_read_clear(phydev, &status)); + if (status & RTK_PHY_INTR_LINK_CHANGE) + { + pr_debug("[%s,%d] RTK_PHY_INTR_LINK_CHANGE\n", __FUNCTION__, __LINE__); + phy_mac_interrupt(phydev); + } + + if (status & RTK_PHY_INTR_WOL) + { + pr_debug("[%s,%d] RTK_PHY_INTR_WOL\n", __FUNCTION__, __LINE__); + rtk_phylib_826xb_wol_reset(phydev); + } + + return 0; +} + +static int rtl826xb_get_tunable(struct phy_device *phydev, struct ethtool_tunable *tuna, void *data) +{ + int32 ret = 0; + uint32 val = 0; + + switch (tuna->id) + { + case ETHTOOL_PHY_EDPD: + RTK_PHYLIB_ERR_CHK(rtk_phylib_826xb_link_down_power_saving_get(phydev, &val)); + *(u16 *)data = (val == 0) ? ETHTOOL_PHY_EDPD_DISABLE : ETHTOOL_PHY_EDPD_DFLT_TX_MSECS; + return 0; + + default: + return -EOPNOTSUPP; + } +} + +static int rtl826xb_set_tunable(struct phy_device *phydev, struct ethtool_tunable *tuna, const void *data) +{ + int32 ret = 0; + uint32 val = 0; + + switch (tuna->id) + { + case ETHTOOL_PHY_EDPD: + switch (*(const u16 *)data) + { + case ETHTOOL_PHY_EDPD_DFLT_TX_MSECS: + val = 1; + break; + case ETHTOOL_PHY_EDPD_DISABLE: + val = 0; + break; + default: + return -EINVAL; + } + RTK_PHYLIB_ERR_CHK(rtk_phylib_826xb_link_down_power_saving_set(phydev, val)); + return 0; + + default: + return -EOPNOTSUPP; + } +} + +static int rtl826xb_set_wol(struct phy_device *phydev, + struct ethtool_wolinfo *wol) +{ + int32 ret = 0; + uint8 *mac_addr = NULL; + uint32 rtk_wol_opts = 0; + + struct net_device *ndev = phydev->attached_dev; + if (!ndev) + return RTK_PHYLIB_ERR_FAILED; + + if (wol->wolopts & ~( WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)) + return -EOPNOTSUPP; + + if (wol->wolopts & (WAKE_MAGIC | WAKE_UCAST)) + { + mac_addr = (uint8 *) ndev->dev_addr; + RTK_PHYLIB_ERR_CHK(rtk_phylib_826xb_wol_unicast_addr_set(phydev, mac_addr)); + } + + if (wol->wolopts & WAKE_MCAST) + { + RTK_PHYLIB_ERR_CHK(rtk_phylib_826xb_wol_multicast_mask_reset(phydev)); + + if (!netdev_mc_empty(ndev)) + { + struct netdev_hw_addr *ha; + netdev_for_each_mc_addr(ha, ndev) + { + pr_info("[%s,%d] mac: %pM \n", __FUNCTION__, __LINE__, ha->addr); + RTK_PHYLIB_ERR_CHK(rtk_phylib_826xb_wol_multicast_mask_add(phydev, rtk_phylib_826xb_wol_multicast_mac2offset(ha->addr))); + } + } + } + + if (wol->wolopts & WAKE_PHY) + rtk_wol_opts |= RTK_WOL_OPT_LINK; + if (wol->wolopts & WAKE_MAGIC) + rtk_wol_opts |= RTK_WOL_OPT_MAGIC; + if (wol->wolopts & WAKE_UCAST) + rtk_wol_opts |= RTK_WOL_OPT_UCAST; + if (wol->wolopts & WAKE_BCAST) + rtk_wol_opts |= RTK_WOL_OPT_BCAST; + if (wol->wolopts & WAKE_MCAST) + rtk_wol_opts |= RTK_WOL_OPT_MCAST; + + RTK_PHYLIB_ERR_CHK(rtk_phylib_826xb_wol_set(phydev, rtk_wol_opts)); + + return 0; +} + + +static void rtl826xb_get_wol(struct phy_device *phydev, + struct ethtool_wolinfo *wol) +{ + int32 ret = 0; + uint32 rtk_wol_opts = 0; + + wol->supported = WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST; + wol->wolopts = 0; + + ret = rtk_phylib_826xb_wol_get(phydev, &rtk_wol_opts); + if (ret != 0) + return; + + if (rtk_wol_opts & RTK_WOL_OPT_LINK) + wol->wolopts |= WAKE_PHY; + if (rtk_wol_opts & RTK_WOL_OPT_MAGIC) + wol->wolopts |= WAKE_MAGIC; + if (rtk_wol_opts & RTK_WOL_OPT_UCAST) + wol->wolopts |= WAKE_UCAST; + if (rtk_wol_opts & RTK_WOL_OPT_MCAST) + wol->wolopts |= WAKE_MCAST; + if (rtk_wol_opts & RTK_WOL_OPT_BCAST) + wol->wolopts |= WAKE_BCAST; +} + +static struct phy_driver rtk_phy_drivers[] = { + { + PHY_ID_MATCH_EXACT(REALTEK_PHY_ID_RTL8261N), + .name = "Realtek RTL8261N/8261BE/8251L", + .get_features = rtl826xb_get_features, + .config_init = rtkphy_config_init, + .probe = rtl826xb_probe, + .suspend = rtkphy_c45_suspend, + .resume = rtkphy_c45_resume, + .config_aneg = rtkphy_c45_config_aneg, + .aneg_done = rtkphy_c45_aneg_done, + .read_status = rtkphy_c45_read_status, + .set_loopback = rtkphy_c45_pcs_loopback, +#if 0 + .cable_test_start = rtl826xb_cable_test_start, + .cable_test_get_status = rtl826xb_cable_test_get_status, +#endif + .config_intr = rtl826xb_config_intr, + .ack_interrupt = rtl826xb_ack_intr, + .handle_interrupt = rtl826xb_handle_intr, + .get_tunable = rtl826xb_get_tunable, + .set_tunable = rtl826xb_set_tunable, + .set_wol = rtl826xb_set_wol, + .get_wol = rtl826xb_get_wol, + }, + { + PHY_ID_MATCH_EXACT(REALTEK_PHY_ID_RTL8264B), + .name = "Realtek RTL8264B/8254B", + .get_features = rtl826xb_get_features, + .config_init = rtkphy_config_init, + .probe = rtl826xb_probe, + .suspend = rtkphy_c45_suspend, + .resume = rtkphy_c45_resume, + .config_aneg = rtkphy_c45_config_aneg, + .aneg_done = rtkphy_c45_aneg_done, + .read_status = rtkphy_c45_read_status, + .set_loopback = rtkphy_c45_pcs_loopback, +#if 0 + .cable_test_start = rtl826xb_cable_test_start, + .cable_test_get_status = rtl826xb_cable_test_get_status, +#endif + .config_intr = rtl826xb_config_intr, + .ack_interrupt = rtl826xb_ack_intr, + .handle_interrupt = rtl826xb_handle_intr, + .get_tunable = rtl826xb_get_tunable, + .set_tunable = rtl826xb_set_tunable, + .set_wol = rtl826xb_set_wol, + .get_wol = rtl826xb_get_wol, + }, +}; + +module_phy_driver(rtk_phy_drivers); + + +static struct mdio_device_id __maybe_unused rtk_phy_tbl[] = { + { PHY_ID_MATCH_EXACT(REALTEK_PHY_ID_RTL8261N) }, + { PHY_ID_MATCH_EXACT(REALTEK_PHY_ID_RTL8264B) }, + { }, +}; + +MODULE_DEVICE_TABLE(mdio, rtk_phy_tbl); + +MODULE_AUTHOR("Realtek"); +MODULE_DESCRIPTION("Realtek PHY drivers"); +MODULE_LICENSE("GPL"); diff --git a/sources/rtk-be550/src/hal/phy/rtk_phy.h b/sources/rtk-be550/src/hal/phy/rtk_phy.h new file mode 100755 index 00000000..8b26f7b4 --- /dev/null +++ b/sources/rtk-be550/src/hal/phy/rtk_phy.h @@ -0,0 +1,20 @@ +/* + * SPDX-License-Identifier: GPL-2.0-only + * + * Copyright (c) 2023 Realtek Semiconductor Corp. All rights reserved. + */ + +#define REALTEK_PHY_ID_RTL8261N 0x001CCAF3 +#define REALTEK_PHY_ID_RTL8264B 0x001CC813 + +#if IS_ENABLED(CONFIG_MACSEC) +int rtk_macsec_init(struct phy_device *phydev); +#else +static inline int rtk_macsec_init(struct phy_device *phydev) +{ + return 0; +} +#endif + + + diff --git a/sources/rtk-be550/src/hal/phy/rtk_phylib.c b/sources/rtk-be550/src/hal/phy/rtk_phylib.c new file mode 100755 index 00000000..83d77150 --- /dev/null +++ b/sources/rtk-be550/src/hal/phy/rtk_phylib.c @@ -0,0 +1,117 @@ +/* + * SPDX-License-Identifier: GPL-2.0-only + * + * Copyright (c) 2023 Realtek Semiconductor Corp. All rights reserved. + */ + +#include "rtk_phylib.h" +#include +#include + +/* OSAL */ + +void rtk_phylib_mdelay(uint32 msec) +{ +#if defined(RTK_PHYDRV_IN_LINUX) + mdelay(msec); +#else + osal_time_mdelay(msec); +#endif +} + + +void rtk_phylib_udelay(uint32 usec) +{ +#if defined(RTK_PHYDRV_IN_LINUX) + if (1000 <= usec) + { + mdelay(usec/1000); + usec = usec % 1000; + } + udelay(usec); +#else + osal_time_udelay(usec); +#endif +} + +int32 rtk_phylib_time_usecs_get(uint32 *pUsec) +{ + struct timespec64 ts; + + if(NULL == pUsec) + return RTK_PHYLIB_ERR_INPUT; + + ktime_get_ts64(&ts); + *pUsec = ((ts.tv_sec * USEC_PER_SEC) + (ts.tv_nsec / NSEC_PER_USEC)); + return 0; +} + +/* Register Access APIs */ +int32 rtk_phylib_mmd_write(rtk_phydev *phydev, uint32 mmd, uint32 reg, uint8 msb, uint8 lsb, uint32 data) +{ + int32 ret = 0; + uint32 mask = 0; + mask = UINT32_BITS_MASK(msb,lsb); + +#if defined(RTK_PHYDRV_IN_LINUX) + ret = phy_modify_mmd(phydev, mmd, reg, mask, (data << lsb)); +#else + { + uint32 rData = 0, wData = 0; + if ((msb != 15) || (lsb != 0)) + { + if ((ret = phy_common_general_reg_mmd_get(phydev->unit, phydev->port, page, reg, &rData)) != RT_ERR_OK) + return ret; + } + wData = REG32_FIELD_SET(rData, data, lsb, mask); + ret = phy_common_general_reg_mmd_set(phydev->unit, phydev->port, page, reg, wData); + } +#endif + + return ret; +} + +int32 rtk_phylib_mmd_read(rtk_phydev *phydev, uint32 mmd, uint32 reg, uint8 msb, uint8 lsb, uint32 *pData) +{ + int32 ret = 0; + uint32 rData = 0; + uint32 mask = 0; + mask = UINT32_BITS_MASK(msb,lsb); + +#if defined(RTK_PHYDRV_IN_LINUX) + rData = phy_read_mmd(phydev, mmd, reg); +#else + { + ret = phy_common_general_reg_mmd_get(phydev->unit, phydev->port, page, reg, &rData); + } +#endif + + *pData = REG32_FIELD_GET(rData, lsb, mask); + return ret; +} + +/* Function Driver */ + +int32 rtk_phylib_c45_power_normal(rtk_phydev *phydev) +{ + int32 ret = 0; + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 1, 0, 11, 11, 0)); + + return 0; +} + +int32 rtk_phylib_c45_power_low(rtk_phydev *phydev) +{ + int32 ret = 0; + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 1, 0, 11, 11, 1)); + + return 0; +} + +int32 rtk_phylib_c45_pcs_loopback(rtk_phydev *phydev, uint32 enable) +{ + int32 ret = 0; + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 3, 0, 14, 14, (enable == 0) ? 0 : 1)); + + return 0; +} diff --git a/sources/rtk-be550/src/hal/phy/rtk_phylib.h b/sources/rtk-be550/src/hal/phy/rtk_phylib.h new file mode 100755 index 00000000..05a4c181 --- /dev/null +++ b/sources/rtk-be550/src/hal/phy/rtk_phylib.h @@ -0,0 +1,257 @@ +/* + * SPDX-License-Identifier: GPL-2.0-only + * + * Copyright (c) 2023 Realtek Semiconductor Corp. All rights reserved. + */ + +#ifndef __RTK_PHYLIB_H +#define __RTK_PHYLIB_H + +#if defined(RTK_PHYDRV_IN_LINUX) + #include + #include "type.h" + #include "rtk_phylib_def.h" +#else + //#include SDK headers +#endif + +#if defined(DEBUG) + #define MACSEC_DBG_PRINT 1 +#endif + +#if defined(RTK_PHYDRV_IN_LINUX) + #define PR_INFO(_fmt, _args...) pr_info(_fmt, ##_args) + #define PR_DBG(_fmt, _args...) pr_debug(_fmt, ##_args) + #define PR_ERR(_fmt, _args...) pr_err("ERROR: "_fmt, ##_args) + + #define RTK_PHYLIB_ERR_FAILED (-EPERM) + #define RTK_PHYLIB_ERR_INPUT (-EINVAL) + #define RTK_PHYLIB_ERR_EXCEEDS_CAPACITY (-ENOSPC) + #define RTK_PHYLIB_ERR_TIMEOUT (-ETIME) + #define RTK_PHYLIB_ERR_ENTRY_NOTFOUND (-ENODATA) + #define RTK_PHYLIB_ERR_OPER_DENIED (-EACCES) +#else + #define PR_INFO(_fmt, _args...) RT_LOG(LOG_INFO, (MOD_HAL|MOD_PHY), _fmt, ##_args) + #define PR_DBG(_fmt, _args...) RT_LOG(LOG_DEBUG, (MOD_HAL|MOD_PHY), _fmt, ##_args) + #define PR_ERR(_fmt, _args...) RT_LOG(LOG_MAJOR_ERR, (MOD_HAL|MOD_PHY), _fmt, ##_args) + + #define RTK_PHYLIB_ERR_FAILED (RT_ERR_FAILED) + #define RTK_PHYLIB_ERR_INPUT (RT_ERR_INPUT) + #define RTK_PHYLIB_ERR_EXCEEDS_CAPACITY (RT_ERR_EXCEEDS_CAPACITY) + #define RTK_PHYLIB_ERR_TIMEOUT (RT_ERR_BUSYWAIT_TIMEOUT) + #define RTK_PHYLIB_ERR_ENTRY_NOTFOUND (RT_ERR_ENTRY_NOTFOUND) + #define RTK_PHYLIB_ERR_OPER_DENIED (RT_ERR_OPER_DENIED) +#endif + +typedef enum rtk_phylib_phy_e +{ + RTK_PHYLIB_NONE, + RTK_PHYLIB_RTL8261N, + RTK_PHYLIB_RTL8264B, + RTK_PHYLIB_RTL8251L, + RTK_PHYLIB_RTL8254B, + RTK_PHYLIB_END +} rtk_phylib_phy_t; + +#if defined(RTK_PHYDRV_IN_LINUX) + typedef struct phy_device rtk_phydev; +#else + struct rtk_phy_dev_s + { + uint32 unit; + rtk_port_t port; + + struct rtk_phy_priv *priv; + }; + typedef struct rtk_phy_dev_s rtk_phydev; +#endif + +#define RTK_PHYLIB_ERR_CHK(op)\ +do {\ + if ((ret = (op)) != 0)\ + return ret;\ +} while(0) + +#define RTK_PHYLIB_VAL_TO_BYTE_ARRAY(_val, _valbytes, _array, _start, _bytes)\ +do{\ + uint32 _i = 0;\ + for (_i = 0; _i < _bytes; _i++)\ + _array[(_bytes-1)-_i] = (_val >> (8* (_valbytes - _i - 1)));\ +}while(0) + +#define RTK_PHYLIB_BYTE_ARRAY_TO_VAL(_val, _array, _start, _bytes)\ +do{\ + uint32 _i = 0;\ + _val = 0;\ + for (_i = 0; _i < _bytes; _i++)\ + _val = (_val << 8) | _array[(_bytes-1)-_i];\ +}while(0) + + +/* RTCT */ +#define RTK_PHYLIB_CABLE_STATUS_NORMAL (0) +#define RTK_PHYLIB_CABLE_STATUS_UNKNOWN (1u << 0) +#define RTK_PHYLIB_CABLE_STATUS_SHORT (1u << 1) +#define RTK_PHYLIB_CABLE_STATUS_OPEN (1u << 2) +#define RTK_PHYLIB_CABLE_STATUS_MISMATCH (1u << 3) +#define RTK_PHYLIB_CABLE_STATUS_CROSS (1u << 4) +#define RTK_PHYLIB_CABLE_STATUS_INTER_PAIR_SHORT (1u << 5) + +typedef struct rtk_rtct_channel_result_s +{ + uint32 cable_status; + uint32 length_cm; +} rtk_rtct_channel_result_t; + +/* MACsec */ +typedef struct rtk_macsec_sa_info_s +{ + uint8 ssci[4]; +} rtk_macsec_sa_info_t; + +#define MACSEC_SA_IS_USED(macsec_port_info_ptr, dir, sa_id) (macsec_port_info_ptr->sa_used[dir][sa_id]) +#define MACSEC_SC_IS_USED(macsec_port_info_ptr, dir, sc_id) (macsec_port_info_ptr->sc_used[dir][sc_id]) + +#define MACSEC_SA_IS_CLEAR(macsec_port_info_ptr, dir, sa_id) (!MACSEC_SA_IS_USED(macsec_port_info_ptr, dir, sa_id)) +#define MACSEC_SC_IS_CLEAR(macsec_port_info_ptr, dir, sc_id) (!MACSEC_SC_IS_USED(macsec_port_info_ptr, dir, sc_id)) + +#define MACSEC_SA_SET_USED(macsec_port_info_ptr, dir, sa_id) do { macsec_port_info_ptr->sa_used[dir][sa_id] = 1; }while(0) +#define MACSEC_SC_SET_USED(macsec_port_info_ptr, dir, sc_id) do { macsec_port_info_ptr->sc_used[dir][sc_id] = 1; }while(0) + +#define MACSEC_SA_UNSET_USED(macsec_port_info_ptr, dir, sa_id) do { macsec_port_info_ptr->sa_used[dir][sa_id] = 0; }while(0) +#define MACSEC_SC_UNSET_USED(macsec_port_info_ptr, dir, sc_id) do { macsec_port_info_ptr->sc_used[dir][sc_id] = 0; }while(0) + +#define MACSEC_SA_MAX(macsec_port_info_ptr) macsec_port_info_ptr->max_sa_num +#define MACSEC_SC_MAX(macsec_port_info_ptr) macsec_port_info_ptr->max_sc_num +#define MACSEC_SC_CS(macsec_port_info_ptr, dir, sc_id) macsec_port_info_ptr->cipher_suite[dir][sc_id] +#define MACSEC_SC_MATCH(macsec_port_info_ptr, dir, sc_id) macsec_port_info_ptr->flow_match[dir][sc_id] +#define MACSEC_SA_SSCI(macsec_port_info_ptr, sa_id) macsec_port_info_ptr->sa_info[sa_id].ssci + + +typedef struct rtk_macsec_port_stats_s +{ + uint64 InPktsUntagged; + uint64 InPktsNoTag; + uint64 InPktsBadTag; + uint64 InPktsUnknownSCI; + uint64 InPktsNoSCI; + uint64 OutPktsUntagged; +}rtk_macsec_port_stats_t; + +typedef struct rtk_macsec_txsa_stats_s +{ + uint64 OutPktsTooLong; + uint64 OutOctetsProtectedEncrypted; + uint64 OutPktsProtectedEncrypted; +}rtk_macsec_txsa_stats_t; + +typedef struct rtk_macsec_rxsa_stats_s +{ + uint64 InPktsUnusedSA; + uint64 InPktsNotUsingSA; + uint64 InPktsUnchecked; + uint64 InPktsDelayed; + uint64 InPktsLate; + uint64 InPktsOK; + uint64 InPktsInvalid; + uint64 InPktsNotValid; + uint64 InOctetsDecryptedValidated; +}rtk_macsec_rxsa_stats_t; + +typedef struct rtk_macsec_port_info_s +{ + int32 (*macsec_reg_get)(rtk_phydev *phydev, rtk_macsec_dir_t dir, uint32 reg, uint8 msb, uint8 lsb, uint32 *pData); + int32 (*macsec_reg_set)(rtk_phydev *phydev, rtk_macsec_dir_t dir, uint32 reg, uint8 msb, uint8 lsb, uint32 data); + + uint16 sa_gen_seq; + uint32 max_sa_num; + uint32 max_sc_num; + rtk_macsec_cipher_t cipher_suite[RTK_MACSEC_DIR_END][RTK_MAX_MACSEC_SC_PER_PORT]; + uint32 flow_match[RTK_MACSEC_DIR_END][RTK_MAX_MACSEC_SC_PER_PORT]; + uint8 sc_used[RTK_MACSEC_DIR_END][RTK_MAX_MACSEC_SC_PER_PORT]; + uint8 sa_used[RTK_MACSEC_DIR_END][RTK_MAX_MACSEC_SA_PER_PORT]; + rtk_macsec_sa_info_t sa_info[RTK_MAX_MACSEC_SA_PER_PORT]; + uint64 sci[RTK_MACSEC_DIR_END][RTK_MAX_MACSEC_SC_PER_PORT]; + + rtk_macsec_port_stats_t port_stats; + rtk_macsec_txsa_stats_t *txsa_stats[RTK_MAX_MACSEC_SA_PER_PORT]; + rtk_macsec_rxsa_stats_t *rxsa_stats[RTK_MAX_MACSEC_SA_PER_PORT]; +} rtk_macsec_port_info_t; + +struct rtk_phy_priv { + rtk_phylib_phy_t phytype; + uint8 isBasePort; + rt_phy_patch_db_t *patch; + rtk_macsec_port_info_t *macsec; +}; + +/* OSAL */ +void rtk_phylib_mdelay(uint32 msec); +void rtk_phylib_udelay(uint32 usec); +#define rtk_phylib_strlen strlen +#define rtk_phylib_strcmp strcmp +#define rtk_phylib_strcpy strcpy +#define rtk_phylib_strncpy strncpy +#define rtk_phylib_strcat strcat +#define rtk_phylib_strchr strchr +#define rtk_phylib_memset memset +#define rtk_phylib_memcpy memcpy +#define rtk_phylib_memcmp memcmp +#define rtk_phylib_strdup strdup +#define rtk_phylib_strncmp strncmp +#define rtk_phylib_strstr strstr +#define rtk_phylib_strtok strtok +#define rtk_phylib_strtok_r strtok_r +#define rtk_phylib_toupper toupper + +int rtk_phylib_time_usecs_get(uint32 *pUsec); +#ifndef WAIT_COMPLETE_VAR +#define WAIT_COMPLETE_VAR() \ + uint32 _t, _now, _t_wait=0, _timeout; \ + int32 _chkCnt=0; + +#define WAIT_COMPLETE(_timeout_us) \ + _timeout = _timeout_us; \ + for(rtk_phylib_time_usecs_get(&_t),rtk_phylib_time_usecs_get(&_now),_t_wait=0,_chkCnt=0 ; \ + (_t_wait <= _timeout); \ + rtk_phylib_time_usecs_get(&_now), _chkCnt++, _t_wait += ((_now >= _t) ? (_now - _t) : (0xFFFFFFFF - _t + _now)),_t = _now \ + ) + +#define WAIT_COMPLETE_IS_TIMEOUT() (_t_wait > _timeout) +#endif + + +/* Register Access APIs */ +int32 rtk_phylib_mmd_write(rtk_phydev *phydev, uint32 mmd, uint32 reg, uint8 msb, uint8 lsb, uint32 data); +int32 rtk_phylib_mmd_read(rtk_phydev *phydev, uint32 mmd, uint32 reg, uint8 msb, uint8 lsb, uint32 *pData); + +/* Function Driver */ +int32 rtk_phylib_c45_power_normal(rtk_phydev *phydev); +int32 rtk_phylib_c45_power_low(rtk_phydev *phydev); +int32 rtk_phylib_c45_pcs_loopback(rtk_phydev *phydev, uint32 enable); + +/* MACsec*/ +int32 rtk_phylib_macsec_init(rtk_phydev *phydev); +int32 rtk_phylib_macsec_enable_get(rtk_phydev *phydev, uint32 *pEna); +int32 rtk_phylib_macsec_enable_set(rtk_phydev *phydev, uint32 ena); + +int32 rtk_phylib_macsec_sc_create(rtk_phydev *phydev, rtk_macsec_dir_t dir, rtk_macsec_sc_t *pSc, uint32 *pSc_id, uint8 active); +int32 rtk_phylib_macsec_sc_update(rtk_phydev *phydev, rtk_macsec_dir_t dir, rtk_macsec_sc_t *pSc, uint32 *pSc_id, uint8 active); +int32 rtk_phylib_macsec_sc_del(rtk_phydev *phydev, rtk_macsec_dir_t dir, uint32 sc_id); +int32 rtk_phylib_macsec_sci_to_scid(rtk_phydev *phydev, rtk_macsec_dir_t dir, uint64 sci, uint32 *sc_id); +int32 rtk_phylib_macsec_sc_status_get(rtk_phydev *phydev, rtk_macsec_dir_t dir,uint32 sc_id, rtk_macsec_sc_status_t *pSc_status); +int32 rtk_phylib_macsec_sc_get(rtk_phydev *phydev, rtk_macsec_dir_t dir, uint32 sc_id, rtk_macsec_sc_t *pSc); + +int32 rtk_phylib_macsec_sa_activate(rtk_phydev *phydev, rtk_macsec_dir_t dir, uint32 sc_id, rtk_macsec_an_t an); +int32 rtk_phylib_macsec_rxsa_disable(rtk_phydev *phydev, uint32 rxsc_id, rtk_macsec_an_t an); +int32 rtk_phylib_macsec_txsa_disable(rtk_phydev *phydev, uint32 txsc_id); +int32 rtk_phylib_macsec_sa_create(rtk_phydev *phydev, rtk_macsec_dir_t dir, uint32 sc_id, rtk_macsec_an_t an, rtk_macsec_sa_t *pSa); +int32 rtk_phylib_macsec_sa_get(rtk_phydev *phydev, rtk_macsec_dir_t dir, uint32 sc_id, rtk_macsec_an_t an, rtk_macsec_sa_t *pSa); +int32 rtk_phylib_macsec_sa_del(rtk_phydev *phydev, rtk_macsec_dir_t dir, uint32 sc_id, rtk_macsec_an_t an); + +int32 rtk_phylib_macsec_stat_port_get(rtk_phydev *phydev, rtk_macsec_stat_t stat, uint64 *pCnt); +int32 rtk_phylib_macsec_stat_txsa_get(rtk_phydev *phydev, uint32 sc_id, rtk_macsec_an_t an, rtk_macsec_txsa_stat_t stat, uint64 *pCnt); +int32 rtk_phylib_macsec_stat_rxsa_get(rtk_phydev *phydev, uint32 sc_id, rtk_macsec_an_t an, rtk_macsec_rxsa_stat_t stat, uint64 *pCnt); + + +#endif /* __RTK_PHYLIB_H */ diff --git a/sources/rtk-be550/src/hal/phy/rtk_phylib_def.h b/sources/rtk-be550/src/hal/phy/rtk_phylib_def.h new file mode 100755 index 00000000..261599a4 --- /dev/null +++ b/sources/rtk-be550/src/hal/phy/rtk_phylib_def.h @@ -0,0 +1,394 @@ +/* + * SPDX-License-Identifier: GPL-2.0-only + * + * Copyright (c) 2023 Realtek Semiconductor Corp. All rights reserved. + */ + +#ifndef __RTK_PHYLIB_DEF_H +#define __RTK_PHYLIB_DEF_H + +#include "type.h" + +#define PHY_C22_MMD_PAGE 0x0A41 +#define PHY_C22_MMD_DEV_REG 13 +#define PHY_C22_MMD_ADD_REG 14 + +/* MDIO Manageable Device(MDD) address*/ +#define PHY_MMD_PMAPMD 1 +#define PHY_MMD_PCS 3 +#define PHY_MMD_AN 7 +#define PHY_MMD_VEND1 30 /* Vendor specific 1 */ +#define PHY_MMD_VEND2 31 /* Vendor specific 2 */ + +#define BIT_0 0x00000001U +#define BIT_1 0x00000002U +#define BIT_2 0x00000004U +#define BIT_3 0x00000008U +#define BIT_4 0x00000010U +#define BIT_5 0x00000020U +#define BIT_6 0x00000040U +#define BIT_7 0x00000080U +#define BIT_8 0x00000100U +#define BIT_9 0x00000200U +#define BIT_10 0x00000400U +#define BIT_11 0x00000800U +#define BIT_12 0x00001000U +#define BIT_13 0x00002000U +#define BIT_14 0x00004000U +#define BIT_15 0x00008000U +#define BIT_16 0x00010000U +#define BIT_17 0x00020000U +#define BIT_18 0x00040000U +#define BIT_19 0x00080000U +#define BIT_20 0x00100000U +#define BIT_21 0x00200000U +#define BIT_22 0x00400000U +#define BIT_23 0x00800000U +#define BIT_24 0x01000000U +#define BIT_25 0x02000000U +#define BIT_26 0x04000000U +#define BIT_27 0x08000000U +#define BIT_28 0x10000000U +#define BIT_29 0x20000000U +#define BIT_30 0x40000000U +#define BIT_31 0x80000000U + +#define MASK_1_BITS (BIT_1 - 1) +#define MASK_2_BITS (BIT_2 - 1) +#define MASK_3_BITS (BIT_3 - 1) +#define MASK_4_BITS (BIT_4 - 1) +#define MASK_5_BITS (BIT_5 - 1) +#define MASK_6_BITS (BIT_6 - 1) +#define MASK_7_BITS (BIT_7 - 1) +#define MASK_8_BITS (BIT_8 - 1) +#define MASK_9_BITS (BIT_9 - 1) +#define MASK_10_BITS (BIT_10 - 1) +#define MASK_11_BITS (BIT_11 - 1) +#define MASK_12_BITS (BIT_12 - 1) +#define MASK_13_BITS (BIT_13 - 1) +#define MASK_14_BITS (BIT_14 - 1) +#define MASK_15_BITS (BIT_15 - 1) +#define MASK_16_BITS (BIT_16 - 1) +#define MASK_17_BITS (BIT_17 - 1) +#define MASK_18_BITS (BIT_18 - 1) +#define MASK_19_BITS (BIT_19 - 1) +#define MASK_20_BITS (BIT_20 - 1) +#define MASK_21_BITS (BIT_21 - 1) +#define MASK_22_BITS (BIT_22 - 1) +#define MASK_23_BITS (BIT_23 - 1) +#define MASK_24_BITS (BIT_24 - 1) +#define MASK_25_BITS (BIT_25 - 1) +#define MASK_26_BITS (BIT_26 - 1) +#define MASK_27_BITS (BIT_27 - 1) +#define MASK_28_BITS (BIT_28 - 1) +#define MASK_29_BITS (BIT_29 - 1) +#define MASK_30_BITS (BIT_30 - 1) +#define MASK_31_BITS (BIT_31 - 1) + +#define REG32_FIELD_SET(_data, _val, _fOffset, _fMask) ((_data & ~(_fMask)) | ((_val << (_fOffset)) & (_fMask))) +#define REG32_FIELD_GET(_data, _fOffset, _fMask) ((_data & (_fMask)) >> (_fOffset)) +#define UINT32_BITS_MASK(_mBit, _lBit) ((0xFFFFFFFF >> (31 - _mBit)) ^ ((1 << _lBit) - 1)) + +typedef struct phy_device * rtk_port_t; + +#if 1 /* ss\sdk\include\hal\phy\phydef.h */ +/* unified patch format */ +typedef enum rtk_phypatch_type_e +{ + PHY_PATCH_TYPE_NONE = 0, + PHY_PATCH_TYPE_TOP = 1, + PHY_PATCH_TYPE_SDS, + PHY_PATCH_TYPE_AFE, + PHY_PATCH_TYPE_UC, + PHY_PATCH_TYPE_UC2, + PHY_PATCH_TYPE_NCTL0, + PHY_PATCH_TYPE_NCTL1, + PHY_PATCH_TYPE_NCTL2, + PHY_PATCH_TYPE_ALGXG, + PHY_PATCH_TYPE_ALG1G, + PHY_PATCH_TYPE_NORMAL, + PHY_PATCH_TYPE_DATARAM, + PHY_PATCH_TYPE_RTCT, + PHY_PATCH_TYPE_END +} rtk_phypatch_type_t; + +#define RTK_PATCH_TYPE_FLOW(_id) (PHY_PATCH_TYPE_END + _id) +#define RTK_PATCH_TYPE_FLOWID_MAX PHY_PATCH_TYPE_END +#define RTK_PATCH_SEQ_MAX ( PHY_PATCH_TYPE_END + RTK_PATCH_TYPE_FLOWID_MAX -1) + +/* Interrupt */ +/* PHY Interrupt Status */ +#define RTK_PHY_INTR_NEXT_PAGE_RECV (BIT_0) +#define RTK_PHY_INTR_AN_COMPLETE (BIT_1) +#define RTK_PHY_INTR_LINK_CHANGE (BIT_2) +#define RTK_PHY_INTR_ALDPS_STATE_CHANGE (BIT_3) +#define RTK_PHY_INTR_RLFD (BIT_4) +#define RTK_PHY_INTR_TM_LOW (BIT_5) +#define RTK_PHY_INTR_TM_HIGH (BIT_6) +#define RTK_PHY_INTR_FATAL_ERROR (BIT_7) +#define RTK_PHY_INTR_MACSEC (BIT_8) +#define RTK_PHY_INTR_PTP1588 (BIT_9) +#define RTK_PHY_INTR_WOL (BIT_10) + +typedef struct rtk_hwpatch_s +{ + uint8 patch_op; + uint8 portmask; + uint16 pagemmd; + uint16 addr; + uint8 msb; + uint8 lsb; + uint16 data; + uint8 compare_op; + uint16 sram_p; + uint16 sram_rr; + uint16 sram_rw; + uint16 sram_a; +} rtk_hwpatch_t; + +typedef struct rtk_hwpatch_data_s +{ + rtk_hwpatch_t *conf; + uint32 size; +} rtk_hwpatch_data_t; + +typedef struct rtk_hwpatch_seq_s +{ + uint8 patch_type; + union + { + rtk_hwpatch_data_t data; + uint8 flow_id; + } patch; +} rtk_hwpatch_seq_t; + +typedef struct rt_phy_patch_db_s +{ + /* patch operation */ + int32 (*fPatch_op)(uint32 unit, rtk_port_t port, uint8 portOffset, rtk_hwpatch_t *pPatch_data, uint8 patch_mode); + int32 (*fPatch_flow)(uint32 unit, rtk_port_t port, uint8 portOffset, uint8 patch_flow, uint8 patch_mode); + + /* patch data */ + rtk_hwpatch_seq_t seq_table[RTK_PATCH_SEQ_MAX]; + rtk_hwpatch_seq_t cmp_table[RTK_PATCH_SEQ_MAX]; + +} rt_phy_patch_db_t; +#endif + +/* cable type for cable test */ +typedef enum { + RTK_RTCT_CABLE_COMMON, + RTK_RTCT_CABLE_CAT5E, + RTK_RTCT_CABLE_CAT6A, +} rtk_rtct_cable_type_t; + +/* MACSec */ +#ifndef RTK_MAX_MACSEC_SA_PER_PORT + #define RTK_MAX_MACSEC_SA_PER_PORT 64 /* max number of Secure Association by a port*/ + #define RTK_MAX_MACSEC_SC_PER_PORT RTK_MAX_MACSEC_SA_PER_PORT/4 /* max number of Secure Channel by a port (4 AN per SC) */ +#endif + +#define RTK_MACSEC_MAX_KEY_LEN 32 + +typedef enum rtk_macsec_reg_e +{ + RTK_MACSEC_DIR_EGRESS = 0, + RTK_MACSEC_DIR_INGRESS, + RTK_MACSEC_DIR_END, +} rtk_macsec_dir_t; + +typedef enum rtk_macsec_an_e +{ + RTK_MACSEC_AN0 = 0, + RTK_MACSEC_AN1, + RTK_MACSEC_AN2, + RTK_MACSEC_AN3, + RTK_MACSEC_AN_MAX, +} rtk_macsec_an_t ; + +typedef enum rtk_macsec_flow_e +{ + RTK_MACSEC_FLOW_BYPASS = 0, + RTK_MACSEC_FLOW_DROP, + RTK_MACSEC_FLOW_INGRESS, + RTK_MACSEC_FLOW_EGRESS, +} rtk_macsec_flow_type_t; + +typedef enum rtk_macsec_validate_e +{ + RTK_MACSEC_VALIDATE_STRICT = 0, + RTK_MACSEC_VALIDATE_CHECK, + RTK_MACSEC_VALIDATE_DISABLE, +} rtk_macsec_validate_t; + +typedef enum rtk_macsec_cipher_e +{ + RTK_MACSEC_CIPHER_GCM_ASE_128 = 0, + RTK_MACSEC_CIPHER_GCM_ASE_256, + RTK_MACSEC_CIPHER_GCM_ASE_XPN_128, + RTK_MACSEC_CIPHER_GCM_ASE_XPN_256, + RTK_MACSEC_CIPHER_MAX, +} rtk_macsec_cipher_t; + +typedef enum rtk_macsec_stat_e +{ + RTK_MACSEC_STAT_InPktsUntagged = 0, + RTK_MACSEC_STAT_InPktsNoTag, + RTK_MACSEC_STAT_InPktsBadTag, + RTK_MACSEC_STAT_InPktsUnknownSCI, + RTK_MACSEC_STAT_InPktsNoSCI, + RTK_MACSEC_STAT_OutPktsUntagged, + RTK_MACSEC_STAT_MAX, +} rtk_macsec_stat_t; + +typedef enum rtk_macsec_txsa_stat_e +{ + RTK_MACSEC_TXSA_STAT_OutPktsTooLong = 0, + RTK_MACSEC_TXSA_STAT_OutOctetsProtectedEncrypted, + RTK_MACSEC_TXSA_STAT_OutPktsProtectedEncrypted, + RTK_MACSEC_TXSA_STAT_MAX, +} rtk_macsec_txsa_stat_t; + +typedef enum rtk_macsec_rxsa_stat_e +{ + RTK_MACSEC_RXSA_STAT_InPktsUnusedSA = 0, + RTK_MACSEC_RXSA_STAT_InPktsNotUsingSA, + RTK_MACSEC_RXSA_STAT_InPktsUnchecked, + RTK_MACSEC_RXSA_STAT_InPktsDelayed, + RTK_MACSEC_RXSA_STAT_InPktsLate, + RTK_MACSEC_RXSA_STAT_InPktsOK, + RTK_MACSEC_RXSA_STAT_InPktsInvalid, + RTK_MACSEC_RXSA_STAT_InPktsNotValid, + RTK_MACSEC_RXSA_STAT_InOctetsDecryptedValidated, + RTK_MACSEC_RXSA_STAT_MAX, +} rtk_macsec_rxsa_stat_t; + + +typedef enum rtk_macsec_match_tx_e +{ + RTK_MACSEC_MATCH_NON_CTRL = 0, /* match all non-control and untagged packets */ + RTK_MACSEC_MATCH_MAC_DA, /* match all non-control and untagged packets with specific MAC DA */ +} rtk_macsec_match_tx_t; + +typedef struct rtk_macsec_txsc_s +{ + /* 8-byte SCI([0:5] = MAC address, [6:7] = port index) for this secure channel */ + uint8 sci[8]; + + /* cipher suite for this SC */ + rtk_macsec_cipher_t cipher_suite; + + /* packet flow type to match this SC */ + rtk_macsec_match_tx_t flow_match; + rtk_mac_t mac_da; /* the target address for RTK_MACSEC_MATCH_MAC_DA */ + + uint8 protect_frame; /* 1 = enable frame protection */ + uint8 include_sci; /* 1 = include explicit SCI in packet */ + uint8 use_es; /* 1 = set ES (End Station) bit in TCI field */ + uint8 use_scb; /* 1 = set SCB (Single Copy Broadcast) bit in TCI field */ + uint8 conf_protect; /* 1 = enable confidentiality protection, */ +}rtk_macsec_txsc_t; + +typedef enum rtk_macsec_match_rx_e +{ + RTK_MACSEC_MATCH_SCI = 0, + RTK_MACSEC_MATCH_MAC_SA, //for pkt without SCI field/TCI.SC=0, +} rtk_macsec_match_rx_t; + +typedef struct rtk_macsec_rxsc_s +{ + /* 8-byte SCI([0:5] = MAC address, [6:7] = port index) for this secure channel */ + uint8 sci[8]; + + /* cipher suite for this SC */ + rtk_macsec_cipher_t cipher_suite; + + /* packet flow type to match this SC */ + rtk_macsec_match_rx_t flow_match; + rtk_mac_t mac_sa; /* the target address for RTK_MACSEC_MATCH_MAC_SA */ + + /* frame validation level */ + rtk_macsec_validate_t validate_frames; + + /* replay protection */ + uint8 replay_protect; /* 1 = enable replay protection */ + uint32 replay_window; /* the window size for replay protection, range for PN: 0 ~ 2^32 - 1, for XPN: 0 ~ 2^30 */ + +}rtk_macsec_rxsc_t; + +typedef union rtk_macsec_sc_u +{ + rtk_macsec_txsc_t tx; + rtk_macsec_rxsc_t rx; +} +rtk_macsec_sc_t; + +typedef struct rtk_macsec_txsc_status_s +{ + uint32 hw_flow_index; + uint32 hw_sa_index; + uint8 sa_inUse; + uint32 hw_flow_data; + uint8 hw_sc_flow_status; + rtk_macsec_an_t running_an; +} +rtk_macsec_txsc_status_t; + +typedef struct rtk_macsec_rxsc_status_s +{ + uint32 hw_flow_base; + uint32 hw_sa_index[RTK_MACSEC_AN_MAX]; + uint8 sa_inUse[RTK_MACSEC_AN_MAX]; + uint32 hw_flow_data[RTK_MACSEC_AN_MAX]; + uint8 hw_sc_flow_status[RTK_MACSEC_AN_MAX]; +} +rtk_macsec_rxsc_status_t; + +typedef union rtk_macsec_sc_status_u +{ + rtk_macsec_txsc_status_t tx; + rtk_macsec_rxsc_status_t rx; +} +rtk_macsec_sc_status_t; + +typedef struct rtk_macsec_sa_s +{ + uint8 key[RTK_MACSEC_MAX_KEY_LEN]; // MACsec Key. + uint32 key_bytes; // Size of the MACsec key in bytes (16 for AES128, 32 for AES256). + + uint32 pn; // PN (32-bit) or lower 32-bit of XPN (64-bit) + uint32 pn_h; // higher 32-bit of XPN (64-bit) + uint8 salt[12]; // 12-byte salt (for XPN). + uint8 ssci[4]; // 4-byte SSCI value (for XPN). +} rtk_macsec_sa_t; + +#define RTK_MACSEC_INTR_EGRESS_PN_THRESHOLD 0x00000001 +#define RTK_MACSEC_INTR_EGRESS_PN_ROLLOVER 0x00000002 + +typedef struct rtk_macsec_intr_status_s +{ + /* a bitmap of RTK_MACSEC_INTR_* to present occured event */ + uint32 status; + + /* When read 1b, the corresponding MACsec egress SA is about to expire due to + the packet number crossing the rtk_macsec_port_cfg_t.pn_intr_threshold or xpn_intr_threshold*/ + uint8 egress_pn_thr_an_bmap[RTK_MAX_MACSEC_SC_PER_PORT]; //bitmap of AN3~0. + + /* When read 1b, the corresponding MACsec egress SA has expired due to + the packet number reaching the maximum allowed value. */ + uint8 egress_pn_exp_an_bmap[RTK_MAX_MACSEC_SC_PER_PORT]; //bitmap of AN3~0. +} +rtk_macsec_intr_status_t; + + +typedef enum rtk_wol_opt_e +{ + RTK_WOL_OPT_LINK = (0x1U << 0), + RTK_WOL_OPT_MAGIC = (0x1U << 1), + RTK_WOL_OPT_UCAST = (0x1U << 2), + RTK_WOL_OPT_MCAST = (0x1U << 3), + RTK_WOL_OPT_BCAST = (0x1U << 4), +} rtk_wol_opt_t; + + +#endif /* __RTK_PHYLIB_DEF_H */ diff --git a/sources/rtk-be550/src/hal/phy/rtk_phylib_macsec.c b/sources/rtk-be550/src/hal/phy/rtk_phylib_macsec.c new file mode 100755 index 00000000..ea24defe --- /dev/null +++ b/sources/rtk-be550/src/hal/phy/rtk_phylib_macsec.c @@ -0,0 +1,2448 @@ +/* + * SPDX-License-Identifier: GPL-2.0-only + * + * Copyright (c) 2023 Realtek Semiconductor Corp. All rights reserved. + */ + +#if defined(RTK_PHYDRV_IN_LINUX) + #include + #include "rtk_phylib.h" + #include "rtk_phylib_macsec.h" + #include "rtk_phylib_rtl826xb.h" +#else + //#include SDK headers + #include + #include + #include + #include + #include + #include + #include +#endif + + +#define MACSEC_REG_GET(phydev, dir, reg, pData) \ +do\ +{\ + struct rtk_phy_priv *_priv = phydev->priv;\ + RTK_PHYLIB_ERR_CHK(_priv->macsec->macsec_reg_get(phydev, dir, reg, 31, 0, pData));\ +} while (0) + +#define MACSEC_REG_SET(phydev, dir, reg, data) \ +do\ +{\ + struct rtk_phy_priv *_priv = phydev->priv;\ + RTK_PHYLIB_ERR_CHK(_priv->macsec->macsec_reg_set(phydev, dir, reg, 31, 0, data));\ +} while (0) + +#define MACSEC_REG_ARRAY_GET(phydev, dir, reg, pArray, cnt) \ +do\ +{\ + if((ret = __rtk_phylib_macsec_reg_array_get(phydev, dir, reg, pArray, cnt)) != 0)\ + {\ + return ret;\ + }\ +} while(0) + +#define MACSEC_REG_ARRAY_SET(phydev, dir, reg, pArray, cnt) \ +do\ +{\ + if((ret = __rtk_phylib_macsec_reg_array_set(phydev, dir, reg, pArray, cnt)) != 0)\ + {\ + return ret;\ + }\ +} while(0) + +static void __rtk_macsec_aes_encrypt(const uint8 * const In_p, uint8 * const Out_p, + const uint8 * const Key_p, const unsigned int KeyByteCount) +{ + struct crypto_aes_ctx ctx; + int ret = 0; + ret = aes_expandkey(&ctx, Key_p, KeyByteCount); + if (ret) + { + PR_ERR("aes_expandkey failed!"); + return; + } + aes_encrypt(&ctx, Out_p, In_p); +} + +static int32 __rtk_phylib_macsec_reg_array_get(rtk_phydev *phydev, rtk_macsec_dir_t dir, + const uint32 reg, uint32* pArray, const uint32 cnt) +{ + int32 ret = 0; + uint32 data = 0, i = 0; + uint32 offset = reg; + + for (i = 0; i < cnt; i++) + { + MACSEC_REG_GET(phydev, dir, offset, &data); + pArray[i] = data; + offset += MACSEC_REG_OFFS; + } + return ret; +} + +static int32 __rtk_phylib_macsec_reg_array_set(rtk_phydev *phydev, rtk_macsec_dir_t dir, + const uint32 reg, uint32* pArray, const uint32 cnt) +{ + int32 ret = 0; + uint32 data = 0, i = 0; + uint32 offset = reg; + + for (i = 0; i < cnt; i++) + { + data = pArray[i]; + MACSEC_REG_SET(phydev, dir, offset, data); + offset += MACSEC_REG_OFFS; + } + return ret; +} + +static int32 __rtk_phylib_macsec_hw_flow_action_write( + rtk_phydev *phydev, + rtk_macsec_dir_t dir, uint32 flow_index, + const uint32 SAIndex, + const uint8 FlowType, + const uint8 DestPort, + const uint8 fDropNonReserved, + const uint8 fFlowCryptAuth, + const uint8 DropAction, + const uint8 fProtect, + const uint8 fSAInUse, + const uint8 fIncludeSCI, + const uint8 ValidateFrames, + const uint8 TagBypassSize, + const uint8 fSaIndexUpdate, + const uint8 ConfOffset, + const uint8 fConfProtect) +{ + int32 ret = 0; + uint32 data = 0; + + if(fDropNonReserved) + data |= BIT_4; + else + data &= ~BIT_4; + + if(fFlowCryptAuth) + data |= BIT_5; + else + data &= ~BIT_5; + + if(fProtect) + data |= BIT_16; + else + data &= ~BIT_16; + + if(fSAInUse) + data |= BIT_17; + else + data &= ~BIT_17; + + if(fIncludeSCI) + data |= BIT_18; + else + data &= ~BIT_18; + + if(fSaIndexUpdate) + data |= BIT_23; + else + data &= ~BIT_23; + + if(fConfProtect) + data |= BIT_31; + else + data &= ~BIT_31; + + data |= (uint32)((((uint32)ConfOffset) & MASK_7_BITS) << 24); + data |= (uint32)((((uint32)TagBypassSize) & MASK_2_BITS) << 21); + data |= (uint32)((((uint32)ValidateFrames) & MASK_2_BITS) << 19); + data |= (uint32)((((uint32)SAIndex) & MASK_8_BITS) << 8); + data |= (uint32)((((uint32)DropAction) & MASK_2_BITS) << 6); + data |= (uint32)((((uint32)DestPort) & MASK_2_BITS) << 2); + data |= (uint32)((((uint32)FlowType) & MASK_2_BITS)); + + MACSEC_REG_SET(phydev, dir, MACSEC_REG_SAM_FLOW_CTRL(flow_index), data); + + PR_DBG("FLOW[%u] = 0x%08X\n", flow_index, data); + + return ret; +} + +static void __rtk_phylib_macsec_copy_key_to_raw(uint32 *pRaw, uint32 offset, uint8 *pKey, uint32 key_bytes) +{ + uint32_t *dst = pRaw + offset; + const uint8_t *src = pKey; + unsigned int i,j; + uint32_t w; + if (pRaw == NULL) + return; + for(i=0; i<(key_bytes+3)/4; i++) + { + w=0; + for(j=0; j<4; j++) + w=(w>>8)|(*src++ << 24); + *dst++ = w; + } +} + +static void __rtk_phylib_macsec_copy_raw_to_key(uint32 *pRaw, uint32 offset ,uint8 *pKey, uint32 raw_words) +{ + uint32_t *src = pRaw + offset; + uint8_t *dst = pKey; + unsigned int i; + if (pRaw == NULL) + return; + + for (i = 0; i < raw_words; i++) + { + *dst++ = (uint8)((src[i] & 0xff)); + *dst++ = (uint8)((src[i] & 0xff00) >> 8) ; + *dst++ = (uint8)((src[i] & 0xff0000) >> 16) ; + *dst++ = (uint8)((src[i] & 0xff000000) >> 24) ; + } +} + +static void __rtk_phylib_macsec_hw_sa_offset_parse(phy_macsec_sa_params_t *pSa, phy_macsec_sa_offset_t *pOffs) +{ + unsigned int long_key; + rtk_phylib_memset(pOffs, 0, sizeof(phy_macsec_sa_offset_t)); + + pOffs->key_offs = 2; + if (pSa->key_bytes == 16) + { + long_key = 0; + } + else + { + long_key = 4; + } + pOffs->hkey_offs = long_key + 6; + pOffs->seq_offs = long_key + 10; + if (pSa->direction == RTK_MACSEC_DIR_EGRESS) + { + if ((pSa->flags & RTK_PHY_MACSEC_SA_FLAG_XPN) != 0) + { + pOffs->ctx_salt_offs = long_key + 13; + pOffs->iv_offs = long_key + 16; + if (long_key) + pOffs->upd_ctrl_offs = 16; + else + pOffs->upd_ctrl_offs = 19; + } + else + { + pOffs->iv_offs = long_key + 11; + pOffs->upd_ctrl_offs = long_key + 15; + } + } + else + { + if ((pSa->flags & RTK_PHY_MACSEC_SA_FLAG_XPN) != 0) + { + pOffs->mask_offs = long_key + 12; + pOffs->ctx_salt_offs = long_key + 13; + pOffs->upd_ctrl_offs = 0; + } + else + { + pOffs->mask_offs = long_key + 11; + pOffs->iv_offs = long_key + 12; + pOffs->upd_ctrl_offs = 0; + } + } +} + +static uint32 __rtk_phylib_macsec_hw_context_id_gen(rtk_phydev *phydev, rtk_macsec_dir_t dir, uint32 sa_index) +{ + struct rtk_phy_priv *priv = phydev->priv; + rtk_macsec_port_info_t *macsec_db = priv->macsec; + + uint32 context_id = 0; + context_id = 0x10000 * (macsec_db->sa_gen_seq & (0xFFFF)) + 0x1000 * (dir)+ sa_index; + macsec_db->sa_gen_seq++; + return context_id; +} + +static int32 __rtk_phylib_macsec_hw_sa_parse(rtk_phydev *phydev, uint32 sa_index, uint32 *pSa_raw, phy_macsec_sa_params_t *pSa) +{ + struct rtk_phy_priv *priv = phydev->priv; + rtk_macsec_port_info_t *macsec_db = priv->macsec; + + int32 ret = 0; + uint32 next_offs = 0, words = 0; + uint8 tmp8 = 0; + if (pSa == NULL || pSa_raw == NULL) + return RTK_PHYLIB_ERR_INPUT; + + rtk_phylib_memset(pSa, 0, sizeof(phy_macsec_sa_params_t)); + + if (pSa_raw[0] & BIT_29) + { + pSa->flags |= RTK_PHY_MACSEC_SA_FLAG_XPN; + } + + if ((pSa_raw[0] & MASK_4_BITS) == 0b0110) + { + pSa->direction = RTK_MACSEC_DIR_EGRESS; + + pSa->an = (uint8)((pSa_raw[0] >> 26) & 0x3); + } + else + { + pSa->direction = RTK_MACSEC_DIR_INGRESS; + } + + if (((pSa_raw[0] >> 17) & MASK_3_BITS) == 0b101) + { + pSa->key_bytes = 16; + } + else + { + pSa->key_bytes = 32; + } + next_offs = 2; + + pSa->context_id = pSa_raw[1]; + + /* key */ + words = (pSa->key_bytes * 8) / 32; + __rtk_phylib_macsec_copy_raw_to_key(pSa_raw, next_offs, pSa->key, words); + next_offs += words + 4; + + /* seq */ + pSa->seq = pSa_raw[next_offs]; + words = 1; + + if (pSa->flags & RTK_PHY_MACSEC_SA_FLAG_XPN) + { + pSa->seq_h = pSa_raw[next_offs+1]; + words = 2; + } + next_offs += words; + + /* replay_window(ingress) */ + if (pSa->direction == RTK_MACSEC_DIR_EGRESS) + { + words = (pSa->flags & RTK_PHY_MACSEC_SA_FLAG_XPN) ? 1 : 0; + } + else + { + pSa->replay_window = pSa_raw[next_offs]; + words = 1; + } + next_offs += words; + + /* CtxSalt */ + if (pSa->flags & RTK_PHY_MACSEC_SA_FLAG_XPN) + { + words = 3; + + pSa->ssci[0] = macsec_db->sa_info[sa_index].ssci[0]; + pSa->ssci[1] = macsec_db->sa_info[sa_index].ssci[1]; + pSa->ssci[2] = macsec_db->sa_info[sa_index].ssci[2]; + pSa->ssci[3] = macsec_db->sa_info[sa_index].ssci[3]; + + tmp8 = (uint8)(pSa_raw[next_offs] & 0xFF); + pSa->salt[0] = (tmp8 ^ (pSa->ssci[0])); + tmp8 = (uint8)((pSa_raw[next_offs] & 0xFF00) >> 8 ); + pSa->salt[1] = (tmp8 ^ (pSa->ssci[1])); + tmp8 = (uint8)((pSa_raw[next_offs] & 0xFF0000) >> 16 ); + pSa->salt[2] = (tmp8 ^ (pSa->ssci[2])); + tmp8 = (uint8)((pSa_raw[next_offs] & 0xFF000000) >> 24 ); + pSa->salt[3] = (tmp8 ^ (pSa->ssci[3])); + + __rtk_phylib_macsec_copy_raw_to_key(pSa_raw, next_offs + 1, &pSa->salt[4], 2); + + } + else + { + words = 0; + } + next_offs += words; + + /* IV(SCI) */ + if (pSa->flags & RTK_PHY_MACSEC_SA_FLAG_XPN) + { + if (pSa->direction == RTK_MACSEC_DIR_EGRESS) + { + words = 3; + } + else + { + words = 0; + } + } + else + { + words = 4; + } + + if (words != 0) + { + __rtk_phylib_macsec_copy_raw_to_key(pSa_raw, next_offs, pSa->sci, 2); + } + next_offs += words; + + /* Update Control */ + if (pSa->direction == RTK_MACSEC_DIR_EGRESS) + { + + pSa->flow_index = (uint32)((pSa_raw[next_offs] >> 16) & MASK_15_BITS); + pSa->next_sa_index = (uint32)(pSa_raw[next_offs] & MASK_14_BITS); + pSa->update_en = (pSa_raw[next_offs] & BIT_31) ? 1 : 0; + pSa->next_sa_valid = (pSa_raw[next_offs] & BIT_15) ? 1 : 0; + pSa->sa_expired_irq = (pSa_raw[next_offs] & BIT_14) ? 1 : 0; + } + + return ret; +} + +static int32 __rtk_phylib_macsec_hw_sa_build(rtk_phydev *phydev, uint32 sa_index, phy_macsec_sa_params_t *pSa, uint32 *pSa_raw) +{ + struct rtk_phy_priv *priv = phydev->priv; + rtk_macsec_port_info_t *macsec_db = priv->macsec; + + int32 ret = 0; + phy_macsec_sa_offset_t offs; + + uint8 hkey[16] = { 0 }; + uint32 tmp = 0; + uint32_t seq = 0; // sequence number. + uint32_t seq_h = 0; // High part of sequence number (64-bit sequence numbers) + uint32 gen_id = 0; + + if (pSa == NULL || pSa_raw == NULL) + return RTK_PHYLIB_ERR_INPUT; + if (pSa->an > 3) + return RTK_PHYLIB_ERR_INPUT; + + if ((pSa->direction != RTK_MACSEC_DIR_INGRESS) && + (pSa->direction != RTK_MACSEC_DIR_EGRESS)) + { + PR_ERR("unknown direction:%d", pSa->direction); + return RTK_PHYLIB_ERR_INPUT; + } + + if (pSa->context_id == 0) + { + gen_id = __rtk_phylib_macsec_hw_context_id_gen(phydev, pSa->direction, sa_index); + } + else + { + gen_id = pSa->context_id; + } + + // Compute offsets for various fields. + __rtk_phylib_macsec_hw_sa_offset_parse(pSa, &offs); + + // Fill the entire SA record with zeros. + rtk_phylib_memset(pSa_raw, 0, PHY_MACSEC_MAX_SA_SIZE * sizeof(uint32_t)); + + if (pSa->direction == RTK_MACSEC_DIR_EGRESS) + { + if((pSa->flags & RTK_PHY_MACSEC_SA_FLAG_XPN) != 0) + { + pSa_raw[0] = MACSEC_SAB_CW0_MACSEC_EG64; + } + else + { + pSa_raw[0] = MACSEC_SAB_CW0_MACSEC_EG32; + } + seq = pSa->seq; + seq_h = pSa->seq_h; + pSa_raw[0] |= (pSa->an & 0x3) << 26; + } + else //RTK_MACSEC_DIR_INGRESS + { + if((pSa->flags & RTK_PHY_MACSEC_SA_FLAG_XPN) != 0) + { + pSa_raw[0] = MACSEC_SAB_CW0_MACSEC_IG64; + } + else + { + pSa_raw[0] = MACSEC_SAB_CW0_MACSEC_IG32; + } + seq = (pSa->seq == 0 && pSa->seq_h == 0) ? 1 : pSa->seq; + seq_h = pSa->seq_h; + } + + switch (pSa->key_bytes) + { + case 16: + pSa_raw[0] |= MACSEC_SAB_CW0_AES128; + break; + case 32: + pSa_raw[0] |= MACSEC_SAB_CW0_AES256; + break; + default: + PR_ERR("unsupported AES key size:%d", pSa->key_bytes); + return RTK_PHYLIB_ERR_INPUT; + } + + // Fill in ID + pSa_raw[1] = gen_id; + + // Fill Key and HKey + __rtk_phylib_macsec_copy_key_to_raw(pSa_raw, offs.key_offs, pSa->key, pSa->key_bytes); + /* generate hkey from key, encrypt a single all-zero block */ + __rtk_macsec_aes_encrypt((uint8_t *)(pSa_raw + offs.hkey_offs), hkey, pSa->key, pSa->key_bytes); + __rtk_phylib_macsec_copy_key_to_raw(pSa_raw, offs.hkey_offs, hkey, 16); + + // Fill in sequence number/seqmask. + pSa_raw[offs.seq_offs] = seq; + if ((pSa->flags & RTK_PHY_MACSEC_SA_FLAG_XPN) != 0) + pSa_raw[offs.seq_offs + 1] = seq_h; + + if (pSa->direction == RTK_MACSEC_DIR_INGRESS) + pSa_raw[offs.mask_offs] = pSa->replay_window; + + // Fill in CtxSalt field. + if (offs.ctx_salt_offs > 0) + { + //__rtk_phylib_macsec_copy_key_to_raw(&phy_macsec_info[unit]->ssci[port], 0, pSa->ssci, 8); + macsec_db->sa_info[sa_index].ssci[0] = pSa->ssci[0]; + macsec_db->sa_info[sa_index].ssci[1] = pSa->ssci[1]; + macsec_db->sa_info[sa_index].ssci[2] = pSa->ssci[2]; + macsec_db->sa_info[sa_index].ssci[3] = pSa->ssci[3]; + + //[0] = most significant 32-bits Salt XOR-ed with SSCI + tmp = (pSa->salt[0] ^ pSa->ssci[0]) | + ((pSa->salt[1] ^ pSa->ssci[1]) << 8) | + ((pSa->salt[2] ^ pSa->ssci[2]) << 16) | + ((pSa->salt[3] ^ pSa->ssci[3]) << 24); + pSa_raw[offs.ctx_salt_offs] = tmp; + //[1:2] = lower 64-bits Salt + __rtk_phylib_macsec_copy_key_to_raw(pSa_raw, offs.ctx_salt_offs + 1, pSa->salt + 4, 8); + } + + // Fill in IV(SCI) fields. + if (offs.iv_offs > 0) + { + __rtk_phylib_macsec_copy_key_to_raw(pSa_raw, offs.iv_offs, pSa->sci, 8); + } + + // Fill in update control fields. + if(offs.upd_ctrl_offs > 0) + { + tmp = (pSa->next_sa_index & MASK_14_BITS) | + ((pSa->flow_index & MASK_15_BITS) << 16); + + if (pSa->update_en) + tmp |= BIT_31; + if (pSa->next_sa_valid) + tmp |= BIT_15; + if (pSa->sa_expired_irq) + tmp |= BIT_14; + + pSa_raw[offs.upd_ctrl_offs] = tmp; + } + + return ret; +} + +int32 __rtk_phylib_macsec_hw_sa_del(rtk_phydev *phydev, rtk_macsec_dir_t dir, uint32 sa_index) +{ + int32 ret = 0; + uint32 sa_raw[PHY_MACSEC_MAX_SA_SIZE] = {0}; + + MACSEC_REG_ARRAY_SET(phydev, dir, MACSEC_REG_XFORM_REC_OFFS(sa_index, dir, 0), sa_raw, MACSEC_XFORM_REC_SIZE(dir)); + + return ret; +} + +static int32 __rtk_phylib_macsec_hw_sa_set(rtk_phydev *phydev, rtk_macsec_dir_t dir, uint32 sa_index, phy_macsec_sa_params_t *pSa) +{ + int32 ret = 0; + uint32 sa_raw[PHY_MACSEC_MAX_SA_SIZE] = {0}; + + if (pSa == NULL) + return RTK_PHYLIB_ERR_INPUT; + + if (pSa->direction == RTK_MACSEC_DIR_EGRESS && dir == RTK_MACSEC_DIR_INGRESS) + { + PR_ERR("direction mismatch!(set egress entry on ingress)"); + return RTK_PHYLIB_ERR_INPUT; + } + if (pSa->direction == RTK_MACSEC_DIR_INGRESS && dir == RTK_MACSEC_DIR_EGRESS) + { + PR_ERR("direction mismatch!(set ingress entry on egress)"); + return RTK_PHYLIB_ERR_INPUT; + } + + if ((ret = __rtk_phylib_macsec_hw_sa_build(phydev, sa_index, pSa, sa_raw)) != 0) + return ret; + + MACSEC_REG_ARRAY_SET(phydev, dir, MACSEC_REG_XFORM_REC_OFFS(sa_index, dir, 0), sa_raw, MACSEC_XFORM_REC_SIZE(dir)); + + #ifdef MACSEC_DBG_PRINT + { + uint32 __i = 0; + PR_DBG("flow_index: %u\n", pSa->flow_index); + PR_DBG("next_sa_index: %u\n", pSa->next_sa_index); + PR_DBG("update_en: %u, next_sa_valid: %u, sa_expired_irq:%u\n", pSa->update_en, pSa->next_sa_valid, pSa->sa_expired_irq); + + PR_DBG("SA offset = 0x%04X\n", MACSEC_REG_XFORM_REC_OFFS(sa_index, dir, 0)); + for (__i = 0; __i < MACSEC_XFORM_REC_SIZE(dir); __i++) + { + PR_DBG("SA[%02u] = 0x%08X\n", __i, sa_raw[__i]); + } + } + #endif + + return ret; +} + +static int32 __rtk_phylib_macsec_hw_sa_get(rtk_phydev *phydev, rtk_macsec_dir_t dir, uint32 sa_index, phy_macsec_sa_params_t *pSa) +{ + int32 ret = 0; + uint32 sa_raw[PHY_MACSEC_MAX_SA_SIZE] = {0}; + + if (pSa == NULL) + return RTK_PHYLIB_ERR_INPUT; + + MACSEC_REG_ARRAY_GET(phydev, dir, MACSEC_REG_XFORM_REC_OFFS(sa_index, dir, 0), sa_raw, MACSEC_XFORM_REC_SIZE(dir)); + + __rtk_phylib_macsec_hw_sa_parse(phydev, sa_index, sa_raw, pSa); + + return ret; +} + +static int32 __rtk_phylib_macsec_hw_flow_action_rule_set(rtk_phydev *phydev, rtk_macsec_dir_t dir, uint32 flow_index, phy_macsec_flow_action_t *pAct) +{ + struct rtk_phy_priv *priv = phydev->priv; + rtk_macsec_port_info_t *macsec_db = priv->macsec; + + int32 ret = 0; + uint32 sa_index = pAct->sa_index; + uint8 flow_type = 0; + uint8 dest_port = 0; + uint8 drop_non_reserved = 0; //do not drop + uint8 flow_crypt_auth = 0; + uint8 drop_action = 0; // CRC + uint8 protect = 0; + uint8 sa_in_use = 0; + uint8 include_sci = 0; + uint8 validate_frames = 0; + uint8 tag_bypass_size = 0; + uint8 sa_index_update = 0; + uint8 conf_offset = 0; + uint8 conf_protect = 0; + + if (flow_index >= MACSEC_SA_MAX(macsec_db)) + { + PR_ERR("flow_index out of range!"); + return RTK_PHYLIB_ERR_INPUT; + } + if (pAct->flow_type == RTK_MACSEC_FLOW_EGRESS && dir == RTK_MACSEC_DIR_INGRESS) + { + PR_ERR("flow_type mismatch!(set egress entry on ingress)"); + return RTK_PHYLIB_ERR_INPUT; + } + if (pAct->flow_type == RTK_MACSEC_FLOW_INGRESS && dir == RTK_MACSEC_DIR_EGRESS) + { + PR_ERR("flow_type mismatch!(set ingress entry on egress)"); + return RTK_PHYLIB_ERR_INPUT; + } + + dest_port = pAct->dest_port; + switch (pAct->flow_type) + { + case RTK_MACSEC_FLOW_EGRESS: + flow_type = 0b11; + dest_port = RTK_MACSEC_PORT_COMMON; + flow_crypt_auth = 0b0; + protect = pAct->params.egress.protect_frame; + sa_in_use = pAct->params.egress.sa_in_use; + include_sci = pAct->params.egress.include_sci; + validate_frames = pAct->params.egress.use_es | ( pAct->params.egress.use_scb << 1); + tag_bypass_size = pAct->params.egress.tag_bypass_size; + conf_offset = pAct->params.egress.confidentiality_offset; + conf_protect = pAct->params.egress.conf_protect; + break; + + case RTK_MACSEC_FLOW_INGRESS: + flow_type = 0b10; + dest_port = RTK_MACSEC_PORT_CONTROLLED; + flow_crypt_auth = 0b0; + protect = pAct->params.ingress.replay_protect; + sa_in_use = pAct->params.ingress.sa_in_use; + + switch (pAct->params.ingress.validate_frames) + { + case RTK_MACSEC_VALIDATE_DISABLE: + validate_frames = 0b00; + break; + case RTK_MACSEC_VALIDATE_CHECK: + validate_frames = 0b01; + break; + case RTK_MACSEC_VALIDATE_STRICT: + validate_frames = 0b10; + break; + default: + PR_ERR("unknown type of validate_frames!"); + return RTK_PHYLIB_ERR_INPUT; + } + conf_offset = pAct->params.ingress.confidentiality_offset; + break; + + case RTK_MACSEC_FLOW_BYPASS: + flow_type = 0b00; + flow_crypt_auth = 0b0; + //sa_in_use = 1; + sa_in_use = pAct->params.bypass_drop.sa_in_use; + break; + + case RTK_MACSEC_FLOW_DROP: + flow_type = 0b01; + flow_crypt_auth = 0b0; + //sa_in_use = 1; + sa_in_use = pAct->params.bypass_drop.sa_in_use; + break; + + default: + return RTK_PHYLIB_ERR_INPUT; + } + + ret = __rtk_phylib_macsec_hw_flow_action_write( + phydev, + dir, flow_index, + sa_index, + flow_type, + dest_port, + drop_non_reserved, + flow_crypt_auth, + drop_action, + protect, + sa_in_use, + include_sci, + validate_frames, + tag_bypass_size, + sa_index_update, + conf_offset, + conf_protect); + + return ret; +} + +static int32 __rtk_phylib_macsec_hw_flow_action_rule_get(rtk_phydev *phydev, rtk_macsec_dir_t dir, uint32 flow_index, phy_macsec_flow_action_t *pAct) +{ + int32 ret = 0; + uint32 reg = 0, reg_data = 0; + uint8 flow_type = 0; + + if(pAct == NULL) + return RTK_PHYLIB_ERR_INPUT; + + rtk_phylib_memset(pAct, 0, sizeof(phy_macsec_flow_action_t)); + + reg = MACSEC_REG_SAM_FLOW_CTRL(flow_index); + MACSEC_REG_GET(phydev, dir, reg, ®_data); + + pAct->dest_port = (reg_data >> 2) & MASK_2_BITS; + + pAct->sa_index = (reg_data >> 8) & MASK_8_BITS; + + flow_type = reg_data & MASK_2_BITS; + switch (flow_type) + { + case 0b11: + pAct->flow_type = RTK_MACSEC_FLOW_EGRESS; + pAct->params.egress.protect_frame = (reg_data >> 16) & MASK_1_BITS; + pAct->params.egress.sa_in_use = (reg_data >> 17) & MASK_1_BITS; + pAct->params.egress.include_sci = (reg_data >> 18) & MASK_1_BITS; + pAct->params.egress.use_es = (reg_data >> 19) & MASK_1_BITS; + pAct->params.egress.use_scb = (reg_data >> 20) & MASK_1_BITS; + pAct->params.egress.tag_bypass_size = (reg_data >> 21) & MASK_2_BITS; + pAct->params.egress.sa_index_update_by_hw = (reg_data >> 23) & MASK_2_BITS; + pAct->params.egress.confidentiality_offset = (reg_data >> 24) & MASK_7_BITS; + pAct->params.egress.conf_protect = (reg_data >> 31) & MASK_1_BITS; + break; + case 0b10: + pAct->flow_type = RTK_MACSEC_FLOW_INGRESS; + pAct->params.ingress.replay_protect = (reg_data >> 16) & MASK_1_BITS; + switch ((reg_data >> 19) & MASK_2_BITS) + { + case 0b00: + pAct->params.ingress.validate_frames = RTK_MACSEC_VALIDATE_DISABLE; + break; + case 0b01: + pAct->params.ingress.validate_frames = RTK_MACSEC_VALIDATE_CHECK; + break; + case 0b10: + pAct->params.ingress.validate_frames = RTK_MACSEC_VALIDATE_STRICT; + break; + default: + return RTK_PHYLIB_ERR_FAILED; + } + + pAct->params.ingress.confidentiality_offset = (reg_data >> 24) & MASK_7_BITS; + break; + case 0b01: + case 0b00: + default: + pAct->flow_type = (flow_type == 0b01) ? RTK_MACSEC_FLOW_DROP : RTK_MACSEC_FLOW_BYPASS; + pAct->params.bypass_drop.sa_in_use = (reg_data >> 17) & MASK_1_BITS; + break; + } + + return ret; +} + +static int32 __rtk_phylib_macsec_hw_flow_action_rule_del(rtk_phydev *phydev, rtk_macsec_dir_t dir, uint32 flow_index) +{ + int32 ret = 0; + + ret = __rtk_phylib_macsec_hw_flow_action_write( + phydev, + dir, flow_index, + 0, + 0, 0, 0, 0, 0, 0, + 0, //SA not in use + 0, 0, 0, 0, 0, 0); + return ret; +} + + +static int32 __rtk_phylib_macsec_hw_flow_match_rule_set(rtk_phydev *phydev, rtk_macsec_dir_t dir, uint32 flow_index, phy_macsec_flow_match_t *pMatch) +{ + struct rtk_phy_priv *priv = phydev->priv; + rtk_macsec_port_info_t *macsec_db = priv->macsec; + + int32 ret = 0; + uint32 reg_data = 0; + uint32 srcPort = 0; + uint16 tmp = 0; + + if (pMatch == NULL) + return RTK_PHYLIB_ERR_INPUT; + + if (flow_index >= MACSEC_SA_MAX(macsec_db)) + { + PR_ERR("flow_index out of range!"); + return RTK_PHYLIB_ERR_INPUT; + } + + { + reg_data = 0; + reg_data |= (uint32)((((uint32)pMatch->mac_sa[3]) & MASK_8_BITS) << 24); + reg_data |= (uint32)((((uint32)pMatch->mac_sa[2]) & MASK_8_BITS) << 16); + reg_data |= (uint32)((((uint32)pMatch->mac_sa[1]) & MASK_8_BITS) << 8); + reg_data |= (uint32)((((uint32)pMatch->mac_sa[0]) & MASK_8_BITS)); + MACSEC_REG_SET(phydev, dir, MACSEC_REG_SAM_MAC_SA_MATCH_LO(flow_index), reg_data); + + reg_data = 0; + tmp = ((pMatch->etherType & 0xFF) << 8) | (pMatch->etherType >> 8); + reg_data |= (uint32)((((uint32)tmp) & MASK_16_BITS) << 16); + + reg_data |= (uint32)((((uint32)pMatch->mac_sa[5]) & MASK_8_BITS) << 8); + reg_data |= (uint32)((((uint32)pMatch->mac_sa[4]) & MASK_8_BITS)); + MACSEC_REG_SET(phydev, dir, MACSEC_REG_SAM_MAC_SA_MATCH_HI(flow_index), reg_data); + } + + { + reg_data = 0; + reg_data |= (uint32)((((uint32)pMatch->mac_da[3]) & MASK_8_BITS) << 24); + reg_data |= (uint32)((((uint32)pMatch->mac_da[2]) & MASK_8_BITS) << 16); + reg_data |= (uint32)((((uint32)pMatch->mac_da[1]) & MASK_8_BITS) << 8); + reg_data |= (uint32)((((uint32)pMatch->mac_da[0]) & MASK_8_BITS)); + MACSEC_REG_SET(phydev, dir, MACSEC_REG_SAM_MAC_DA_MATCH_LO(flow_index), reg_data); + + reg_data = 0; + reg_data |= (uint32)((((uint32)pMatch->vlan_id) & MASK_12_BITS) << 16); + reg_data |= (uint32)((((uint32)pMatch->mac_da[5]) & MASK_8_BITS) << 8); + reg_data |= (uint32)((((uint32)pMatch->mac_da[4]) & MASK_8_BITS)); + MACSEC_REG_SET(phydev, dir, MACSEC_REG_SAM_MAC_DA_MATCH_HI(flow_index), reg_data); + } + + { + srcPort = pMatch->sourcePort; + + reg_data = 0; + reg_data |= (pMatch->fVLANValid) ? (BIT_0) : 0; + reg_data |= (pMatch->fQinQFound) ? (BIT_1) : 0; + reg_data |= (pMatch->fSTagValid) ? (BIT_2) : 0; + reg_data |= (pMatch->fQTagFound) ? (BIT_3) : 0; + + reg_data |= (pMatch->fControlPacket) ? (BIT_7) : 0; + reg_data |= (pMatch->fUntagged) ? (BIT_8) : 0; + reg_data |= (pMatch->fTagged) ? (BIT_9) : 0; + reg_data |= (pMatch->fBadTag) ? (BIT_10) : 0; + reg_data |= (pMatch->fKayTag) ? (BIT_11) : 0; + + reg_data |= (uint32)((((uint32)pMatch->macsec_TCI_AN) & MASK_8_BITS) << 24); + reg_data |= (uint32)((((uint32)pMatch->matchPriority) & MASK_4_BITS) << 16); + reg_data |= (uint32)((((uint32)srcPort) & MASK_2_BITS) << 12); + reg_data |= (uint32)((((uint32)pMatch->vlanUserPriority) & MASK_3_BITS) << 4); + MACSEC_REG_SET(phydev, dir, MACSEC_REG_SAM_MISC_MATCH(flow_index), reg_data); + } + + { + #ifdef MACSEC_DBG_PRINT + { + PR_DBG("[%s]SCI = 0x%02X%02X%02X%02X%02X%02X%02X%02X\n", __FUNCTION__, + pMatch->sci[0], pMatch->sci[1], pMatch->sci[2], pMatch->sci[3], + pMatch->sci[4], pMatch->sci[5], pMatch->sci[6], pMatch->sci[7]); + } + #endif + reg_data = 0; + reg_data |= (uint32)(((uint32)(pMatch->sci[3]) & MASK_8_BITS) << 24); + reg_data |= (uint32)(((uint32)(pMatch->sci[2]) & MASK_8_BITS) << 16); + reg_data |= (uint32)(((uint32)(pMatch->sci[1]) & MASK_8_BITS) << 8); + reg_data |= (uint32)(((uint32)(pMatch->sci[0]) & MASK_8_BITS)); + MACSEC_REG_SET(phydev, dir, MACSEC_REG_SAM_SCI_MATCH_LO(flow_index), reg_data); + #ifdef MACSEC_DBG_PRINT + { + PR_DBG("[%s]SCI_LO = 0x%08X\n", __FUNCTION__, reg_data); + MACSEC_REG_GET(phydev, dir, MACSEC_REG_SAM_SCI_MATCH_LO(flow_index), ®_data); + PR_DBG("CHECK read[0x%04X] = 0x%08X\n", MACSEC_REG_SAM_SCI_MATCH_LO(flow_index), reg_data); + } + #endif + + reg_data = 0; + reg_data |= (uint32)(((uint32)(pMatch->sci[7]) & MASK_8_BITS) << 24); + reg_data |= (uint32)(((uint32)(pMatch->sci[6]) & MASK_8_BITS) << 16); + reg_data |= (uint32)(((uint32)(pMatch->sci[5]) & MASK_8_BITS) << 8); + reg_data |= (uint32)(((uint32)(pMatch->sci[4]) & MASK_8_BITS)); + MACSEC_REG_SET(phydev, dir, MACSEC_REG_SAM_SCI_MATCH_HI(flow_index), reg_data); + #ifdef MACSEC_DBG_PRINT + { + PR_DBG("[%s]SCI_HI = 0x%08X\n", __FUNCTION__, reg_data); + MACSEC_REG_GET(phydev, dir, MACSEC_REG_SAM_SCI_MATCH_HI(flow_index), ®_data); + PR_DBG("CHECK read[0x%04X] = 0x%08X\n", MACSEC_REG_SAM_SCI_MATCH_HI(flow_index), reg_data); + } + #endif + } + + { + reg_data = 0; + reg_data |= pMatch->matchMask; + MACSEC_REG_SET(phydev, dir, MACSEC_REG_SAM_MASK(flow_index), reg_data); + } + + { + reg_data = 0; + reg_data |= (uint32)((((uint32)pMatch->flow_index) & MASK_8_BITS) << 16); + reg_data |= (uint32)((((uint32)pMatch->vlanUpInner) & MASK_3_BITS) << 12); + reg_data |= (uint32)((((uint32)pMatch->vlanIdInner) & MASK_12_BITS)); + MACSEC_REG_SET(phydev, dir, MACSEC_REG_SAM_EXT_MATCH(flow_index), reg_data); + } + return ret; +} + +static int32 __rtk_phylib_macsec_hw_flow_match_rule_get(rtk_phydev *phydev, rtk_macsec_dir_t dir, uint32 flow_index, phy_macsec_flow_match_t *pMatch) +{ + int32 ret = 0; + uint32 reg = 0, reg_data = 0; + uint16 tmp = 0; + + if (pMatch == NULL) + return RTK_PHYLIB_ERR_INPUT; + + rtk_phylib_memset(pMatch, 0, sizeof(phy_macsec_flow_match_t)); + + reg = MACSEC_REG_SAM_MAC_SA_MATCH_LO(flow_index); + MACSEC_REG_GET(phydev, dir, reg, ®_data); + PR_DBG("read[0x%04X] = 0x%08X\n", reg, reg_data); + pMatch->mac_sa[3] = (uint8)((reg_data >> 24) & MASK_8_BITS); + pMatch->mac_sa[2] = (uint8)((reg_data >> 16) & MASK_8_BITS); + pMatch->mac_sa[1] = (uint8)((reg_data >> 8) & MASK_8_BITS); + pMatch->mac_sa[0] = (uint8)((reg_data) & MASK_8_BITS); + + reg = MACSEC_REG_SAM_MAC_SA_MATCH_HI(flow_index); + MACSEC_REG_GET(phydev, dir, reg, ®_data); + PR_DBG("read[0x%04X] = 0x%08X\n", reg, reg_data); + tmp = (uint16)((reg_data >> 16) & MASK_16_BITS); + pMatch->etherType = ((tmp & 0xFF) << 8) | ((tmp >> 8) & 0xFF); + pMatch->mac_sa[5] = (uint8)((reg_data >> 8) & MASK_8_BITS); + pMatch->mac_sa[4] = (uint8)((reg_data) & MASK_8_BITS); + + reg = MACSEC_REG_SAM_MAC_DA_MATCH_LO(flow_index); + MACSEC_REG_GET(phydev, dir, reg, ®_data); + PR_DBG("read[0x%04X] = 0x%08X\n", reg, reg_data); + pMatch->mac_da[3] = (uint8)((reg_data >> 24) & MASK_8_BITS); + pMatch->mac_da[2] = (uint8)((reg_data >> 16) & MASK_8_BITS); + pMatch->mac_da[1] = (uint8)((reg_data >> 8) & MASK_8_BITS); + pMatch->mac_da[0] = (uint8)((reg_data) & MASK_8_BITS); + + reg = MACSEC_REG_SAM_MAC_DA_MATCH_HI(flow_index); + MACSEC_REG_GET(phydev, dir, reg, ®_data); + PR_DBG("read[0x%04X] = 0x%08X\n", reg, reg_data); + pMatch->vlan_id = (uint16)((reg_data >> 16) & MASK_12_BITS); + pMatch->mac_da[5] = (uint8)((reg_data >> 8) & MASK_8_BITS); + pMatch->mac_da[4] = (uint8)((reg_data) & MASK_8_BITS); + + reg = MACSEC_REG_SAM_MISC_MATCH(flow_index); + MACSEC_REG_GET(phydev, dir, reg, ®_data); + PR_DBG("read[0x%04X] = 0x%08X\n", reg, reg_data); + pMatch->fVLANValid = (reg_data & BIT_0) ? 1 : 0; + pMatch->fQinQFound = (reg_data & BIT_1) ? 1 : 0; + pMatch->fSTagValid = (reg_data & BIT_2) ? 1 : 0; + pMatch->fQTagFound = (reg_data & BIT_3) ? 1 : 0; + + pMatch->fControlPacket = (reg_data & BIT_7) ? 1 : 0; + pMatch->fUntagged = (reg_data & BIT_8) ? 1 : 0; + pMatch->fTagged = (reg_data & BIT_9) ? 1 : 0; + pMatch->fBadTag = (reg_data & BIT_10) ? 1 : 0; + pMatch->fKayTag = (reg_data & BIT_11) ? 1 : 0; + + pMatch->macsec_TCI_AN = (uint8)((reg_data >> 24) & MASK_8_BITS); + pMatch->matchPriority = (uint8)((reg_data >> 16) & MASK_4_BITS); + pMatch->sourcePort = (uint8)((reg_data >> 12) & MASK_2_BITS); + + pMatch->vlanUserPriority = (uint8)((reg_data >> 4) & MASK_3_BITS); + + reg = MACSEC_REG_SAM_SCI_MATCH_LO(flow_index); + MACSEC_REG_GET(phydev, dir, reg, ®_data); + PR_DBG("read[0x%04X] = 0x%08X\n", reg, reg_data); + pMatch->sci[3] = (uint8)((reg_data >> 24) & MASK_8_BITS); + pMatch->sci[2] = (uint8)((reg_data >> 16) & MASK_8_BITS); + pMatch->sci[1] = (uint8)((reg_data >> 8) & MASK_8_BITS); + pMatch->sci[0] = (uint8)((reg_data) & MASK_8_BITS); + + reg = MACSEC_REG_SAM_SCI_MATCH_HI(flow_index); + MACSEC_REG_GET(phydev, dir, reg, ®_data); + PR_DBG("read[0x%04X] = 0x%08X\n", reg, reg_data); + pMatch->sci[7] = (uint8)((reg_data >> 24) & MASK_8_BITS); + pMatch->sci[6] = (uint8)((reg_data >> 16) & MASK_8_BITS); + pMatch->sci[5] = (uint8)((reg_data >> 8) & MASK_8_BITS); + pMatch->sci[4] = (uint8)((reg_data) & MASK_8_BITS); + + reg = MACSEC_REG_SAM_MASK(flow_index); + MACSEC_REG_GET(phydev, dir, reg, ®_data); + PR_DBG("read[0x%04X] = 0x%08X\n", reg, reg_data); + pMatch->matchMask = reg_data; + + reg = MACSEC_REG_SAM_EXT_MATCH(flow_index); + MACSEC_REG_GET(phydev, dir, reg, ®_data); + PR_DBG("read[0x%04X] = 0x%08X\n", reg, reg_data); + pMatch->flow_index = (uint32) ((reg_data >> 16) & MASK_8_BITS); + pMatch->vlanUpInner = (uint8) ((reg_data >> 12) & MASK_3_BITS); + pMatch->vlanIdInner = (uint16) ((reg_data) & MASK_12_BITS); + + return ret; +} + +static int32 __rtk_phylib_macsec_hw_flow_match_rule_del(rtk_phydev *phydev, rtk_macsec_dir_t dir, uint32 flow_index) +{ + int32 ret = 0; + uint32 reg_data = 0; + + MACSEC_REG_SET(phydev, dir, MACSEC_REG_SAM_MAC_SA_MATCH_LO(flow_index), reg_data); + MACSEC_REG_SET(phydev, dir, MACSEC_REG_SAM_MAC_SA_MATCH_HI(flow_index), reg_data); + MACSEC_REG_SET(phydev, dir, MACSEC_REG_SAM_MAC_DA_MATCH_LO(flow_index), reg_data); + MACSEC_REG_SET(phydev, dir, MACSEC_REG_SAM_MAC_DA_MATCH_HI(flow_index), reg_data); + MACSEC_REG_SET(phydev, dir, MACSEC_REG_SAM_MISC_MATCH(flow_index), reg_data); + MACSEC_REG_SET(phydev, dir, MACSEC_REG_SAM_SCI_MATCH_LO(flow_index), reg_data); + MACSEC_REG_SET(phydev, dir, MACSEC_REG_SAM_SCI_MATCH_HI(flow_index), reg_data); + MACSEC_REG_SET(phydev, dir, MACSEC_REG_SAM_MASK(flow_index), reg_data); + MACSEC_REG_SET(phydev, dir, MACSEC_REG_SAM_EXT_MATCH(flow_index), reg_data); + + return ret; +} + +static int32 __rtk_phylib_macsec_hw_flow_enable_get(rtk_phydev *phydev, rtk_macsec_dir_t dir, uint32 flow_index, uint32 *pEnable) +{ + int32 ret = 0; + uint32 reg_data; + + MACSEC_REG_GET(phydev, dir, MACSEC_REG_SAM_ENTRY_ENABLE(flow_index/32), ®_data); + *pEnable = (reg_data & (BIT_0 << (flow_index % 32))) ? ENABLED : DISABLED; + + return ret; +} + +static int32 __rtk_phylib_macsec_hw_flow_enable_set(rtk_phydev *phydev, rtk_macsec_dir_t dir, uint32 flow_index, uint32 enable) +{ + int32 ret = 0; + uint32 reg_data = 0; + uint32 cur_ena = 0; + WAIT_COMPLETE_VAR(); + + if ((ret = __rtk_phylib_macsec_hw_flow_enable_get(phydev, dir, flow_index, &cur_ena)) != 0) + { + return ret; + } + + if (enable != cur_ena) + { + MACSEC_REG_SET(phydev, dir, (enable == ENABLED)? + MACSEC_REG_SAM_ENTRY_SET(flow_index/32) : MACSEC_REG_SAM_ENTRY_CLEAR(flow_index/32), + BIT_0 << (flow_index % 32)); + + if (enable == 0) + { + WAIT_COMPLETE(10000000) + { + MACSEC_REG_GET(phydev, dir, MACSEC_REG_SAM_IN_FLIGHT, ®_data); + if ((reg_data & 0x3F) == 0) + break; + } + if (WAIT_COMPLETE_IS_TIMEOUT()) + { + ret = RTK_PHYLIB_ERR_TIMEOUT; + PR_ERR("flow delete timeout, val=0x%x", (reg_data & 0x3F)); + return ret; + } + } + + } + + return ret; +} + +int32 rtk_phylib_macsec_init(rtk_phydev *phydev) +{ + int32 ret = 0; + uint32 data = 0; + struct rtk_phy_priv *priv = phydev->priv; + + switch (priv->phytype) + { + case RTK_PHYLIB_RTL8261N: + case RTK_PHYLIB_RTL8264B: + case RTK_PHYLIB_RTL8251L: + case RTK_PHYLIB_RTL8254B: + priv->macsec->macsec_reg_get = rtk_phylib_826xb_macsec_read; + priv->macsec->macsec_reg_set = rtk_phylib_826xb_macsec_write; + break; + default: + return RTK_PHYLIB_ERR_FAILED; + } + + //read HW version + MACSEC_REG_GET(phydev, RTK_MACSEC_DIR_EGRESS, 0xFFFC, &data); + if ((data & MASK_8_BITS) != 160) + PR_ERR("[%s] HW ver: 0x%X, mismatch!\n", __FUNCTION__, (data & MASK_8_BITS)); + else + PR_INFO("[%s] HW ver: 0x%X\n", __FUNCTION__, (data & MASK_8_BITS)); + + MACSEC_REG_SET(phydev, RTK_MACSEC_DIR_EGRESS, MACSEC_REG_COUNT_CTRL, 0x00000001); + MACSEC_REG_SET(phydev, RTK_MACSEC_DIR_EGRESS, MACSEC_REG_COUNT_CTRL, 0x0000000c); + MACSEC_REG_SET(phydev, RTK_MACSEC_DIR_EGRESS, MACSEC_REG_COUNT_SECFAIL1, 0x80fe0000); + MACSEC_REG_SET(phydev, RTK_MACSEC_DIR_EGRESS, MACSEC_REG_MISC_CONTROL, 0x02000046); + MACSEC_REG_SET(phydev, RTK_MACSEC_DIR_EGRESS, MACSEC_REG_CTX_CTRL, 0xe5880618); + MACSEC_REG_SET(phydev, RTK_MACSEC_DIR_EGRESS, MACSEC_REG_CTX_UPD_CTRL, 0x00000003); + + MACSEC_REG_SET(phydev, RTK_MACSEC_DIR_INGRESS, MACSEC_REG_COUNT_CTRL, 0x00000001); + MACSEC_REG_SET(phydev, RTK_MACSEC_DIR_INGRESS, MACSEC_REG_COUNT_CTRL, 0x0000000c); + MACSEC_REG_SET(phydev, RTK_MACSEC_DIR_INGRESS, MACSEC_REG_COUNT_SECFAIL1, 0x80fe0000); + MACSEC_REG_SET(phydev, RTK_MACSEC_DIR_INGRESS, MACSEC_REG_MISC_CONTROL, 0x01001046); + MACSEC_REG_SET(phydev, RTK_MACSEC_DIR_INGRESS, MACSEC_REG_CTX_CTRL, 0xe5880614); + MACSEC_REG_SET(phydev, RTK_MACSEC_DIR_INGRESS, MACSEC_REG_CTX_UPD_CTRL, 0x00000003); + MACSEC_REG_SET(phydev, RTK_MACSEC_DIR_INGRESS, MACSEC_REG_SAM_CP_TAG, 0xe0fac688); + MACSEC_REG_SET(phydev, RTK_MACSEC_DIR_INGRESS, MACSEC_REG_IG_CC_CONTROL, 0x0000C000); + MACSEC_REG_SET(phydev, RTK_MACSEC_DIR_INGRESS, MACSEC_REG_SAM_NM_PARAMS, 0xe588003f); + + /* default Egress non-match pkt action: + bypass: NCP - KaY tag; CP - Untagged + drop: others + */ + MACSEC_REG_SET(phydev, RTK_MACSEC_DIR_EGRESS, MACSEC_REG_SAM_NM_FLOW_NCP, 0x00010101); + MACSEC_REG_SET(phydev, RTK_MACSEC_DIR_EGRESS, MACSEC_REG_SAM_NM_FLOW_CP, 0x01010100); + /* default Ingress non-match pkt action: + bypass: NCP - KaY tag,Tagged; CP - Untagged + drop: others + */ + MACSEC_REG_SET(phydev, RTK_MACSEC_DIR_INGRESS, MACSEC_REG_SAM_NM_FLOW_NCP, 0x08090809); + MACSEC_REG_SET(phydev, RTK_MACSEC_DIR_INGRESS, MACSEC_REG_SAM_NM_FLOW_CP, 0x09090908); + + MACSEC_REG_SET(phydev, RTK_MACSEC_DIR_EGRESS, 0xF810, 0x000003ff); + MACSEC_REG_SET(phydev, RTK_MACSEC_DIR_EGRESS, 0xF808, 0x00000300); + + MACSEC_REG_SET(phydev, RTK_MACSEC_DIR_EGRESS, 0x780C, 0x8e880000); + MACSEC_REG_SET(phydev, RTK_MACSEC_DIR_EGRESS, 0x78FC, 0x80200); + MACSEC_REG_SET(phydev, RTK_MACSEC_DIR_INGRESS, 0x780C, 0x8e880000); + MACSEC_REG_SET(phydev, RTK_MACSEC_DIR_INGRESS, 0x78FC, 0x80200); + + return 0; +} + +int32 rtk_phylib_macsec_enable_get(rtk_phydev *phydev, uint32 *pEna) +{ + int32 ret = 0; + struct rtk_phy_priv *priv = phydev->priv; + uint32 val = 0; + switch (priv->phytype) + { + case RTK_PHYLIB_RTL8261N: + case RTK_PHYLIB_RTL8264B: + case RTK_PHYLIB_RTL8251L: + case RTK_PHYLIB_RTL8254B: + RTK_PHYLIB_ERR_CHK(rtk_phylib_826xb_macsec_bypass_get(phydev, &val)); + *pEna = (val == 0) ? 1 : 0; + break; + default: + return RTK_PHYLIB_ERR_FAILED; + } + return ret; +} +int32 rtk_phylib_macsec_enable_set(rtk_phydev *phydev, uint32 ena) +{ + int32 ret = 0; + struct rtk_phy_priv *priv = phydev->priv; + + switch (priv->phytype) + { + case RTK_PHYLIB_RTL8261N: + case RTK_PHYLIB_RTL8264B: + case RTK_PHYLIB_RTL8251L: + case RTK_PHYLIB_RTL8254B: + ret = rtk_phylib_826xb_macsec_bypass_set(phydev, (ena == 0) ? 1 : 0); + break; + default: + ret = RTK_PHYLIB_ERR_FAILED; + } + PR_DBG("[%s]ena=%u ret=%d\n", __FUNCTION__, ena, ret); + return ret; +} + +int32 rtk_phylib_macsec_sc_create(rtk_phydev *phydev, rtk_macsec_dir_t dir, + rtk_macsec_sc_t *pSc, uint32 *pSc_id, uint8 active) +{ + struct rtk_phy_priv *priv = phydev->priv; + rtk_macsec_port_info_t *macsec_db = priv->macsec; + + int32 ret = 0; + uint8 an = 0, tci_an = 0; + uint32 i = 0, sc_id = 0xFFFFFFFF; + uint32 sa_id = 0; + uint32 flow_base = 0; + rtk_macsec_cipher_t cs = RTK_MACSEC_CIPHER_GCM_ASE_128; + phy_macsec_flow_action_t flow; + phy_macsec_flow_match_t match; + phy_macsec_sa_params_t hwsa; + + if (pSc == NULL || pSc_id == NULL) + return RTK_PHYLIB_ERR_INPUT; + + for (i = 0; i < MACSEC_SC_MAX(macsec_db); i++) + { + if(MACSEC_SC_IS_CLEAR(macsec_db, dir, i)) + { + sc_id = i; + break; + } + } + if ( sc_id == 0xFFFFFFFF ) + { + PR_ERR("no empty SC entry!"); + return RTK_PHYLIB_ERR_EXCEEDS_CAPACITY; + } + + flow_base = PHY_MACSEC_HW_FLOW_ID(sc_id); + + rtk_phylib_memset(&flow, 0, sizeof(phy_macsec_flow_action_t)); + rtk_phylib_memset(&match, 0, sizeof(phy_macsec_flow_match_t)); + rtk_phylib_memset(&hwsa, 0, sizeof(phy_macsec_sa_params_t)); + + cs = (dir == RTK_MACSEC_DIR_EGRESS) ? (pSc->tx.cipher_suite) : (pSc->rx.cipher_suite); + switch (cs) + { + case RTK_MACSEC_CIPHER_GCM_ASE_128: + hwsa.flags = 0; + hwsa.key_bytes = 16; + if(dir == RTK_MACSEC_DIR_INGRESS && pSc->rx.replay_window > 0xFFFFFFFF) + { + PR_ERR("PN replay_window %u out of range 0~%u", pSc->rx.replay_window, (0xFFFFFFFF)); + return RTK_PHYLIB_ERR_INPUT; + } + break; + case RTK_MACSEC_CIPHER_GCM_ASE_256: + hwsa.flags = 0; + hwsa.key_bytes = 32; + if(dir == RTK_MACSEC_DIR_INGRESS && pSc->rx.replay_window > 0xFFFFFFFF) + { + PR_ERR("PN replay_window %u out of range 0~%u", pSc->rx.replay_window, (0xFFFFFFFF)); + return RTK_PHYLIB_ERR_INPUT; + } + break; + case RTK_MACSEC_CIPHER_GCM_ASE_XPN_128: + hwsa.flags = RTK_PHY_MACSEC_SA_FLAG_XPN; + hwsa.key_bytes = 16; + if(dir == RTK_MACSEC_DIR_INGRESS && pSc->rx.replay_window > 0x40000000) + { + PR_ERR("XPN replay_window %u out of range 0~%u", pSc->rx.replay_window, (0x40000000)); + return RTK_PHYLIB_ERR_INPUT; + } + break; + case RTK_MACSEC_CIPHER_GCM_ASE_XPN_256: + hwsa.flags = RTK_PHY_MACSEC_SA_FLAG_XPN; + hwsa.key_bytes = 32; + if(dir == RTK_MACSEC_DIR_INGRESS && pSc->rx.replay_window > 0x40000000) + { + PR_ERR("XPN replay_window %u out of range 0~%u", pSc->rx.replay_window, (0x40000000)); + return RTK_PHYLIB_ERR_INPUT; + } + break; + default: + return RTK_PHYLIB_ERR_INPUT; + } + + if (dir == RTK_MACSEC_DIR_EGRESS) + { + PR_DBG("[%s]SCI = 0x%02X%02X%02X%02X%02X%02X%02X%02X\n", __FUNCTION__, + pSc->tx.sci[0], pSc->tx.sci[1], pSc->tx.sci[2], pSc->tx.sci[3], + pSc->tx.sci[4], pSc->tx.sci[5], pSc->tx.sci[6], pSc->tx.sci[7]); + PR_DBG("[%s]pf %u/is %u/es %u/scb %u/cp %u\n", __FUNCTION__, + pSc->tx.protect_frame, pSc->tx.include_sci, pSc->tx.use_es, pSc->tx.use_scb, pSc->tx.conf_protect); + + /* match rule */ + match.fUntagged = 1; + match.fControlPacket = 0; + switch (pSc->tx.flow_match) + { + case RTK_MACSEC_MATCH_NON_CTRL: + match.matchMask = MACSEC_SA_MATCH_MASK_CTRL_PKT; + break; + + case RTK_MACSEC_MATCH_MAC_DA: + rtk_phylib_memcpy(match.mac_da, pSc->tx.mac_da.octet, 6 * sizeof(uint8)); + match.matchMask = (MACSEC_SA_MATCH_MASK_MAC_DA_FULL + | MACSEC_SA_MATCH_MASK_CTRL_PKT); + break; + + default: + return RTK_PHYLIB_ERR_INPUT; + } + match.flow_index = flow_base; + RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_match_rule_set(phydev, dir, flow_base, &match)); + MACSEC_SC_MATCH(macsec_db, dir, sc_id) = pSc->tx.flow_match; + + /* flow ctrl */ + flow.flow_type = RTK_MACSEC_FLOW_EGRESS; + flow.dest_port = RTK_MACSEC_PORT_COMMON; + flow.sa_index = PHY_MACSEC_HW_SA_ID(sc_id, 0); + flow.params.egress.protect_frame = pSc->tx.protect_frame; + flow.params.egress.sa_in_use = 0; + flow.params.egress.include_sci = pSc->tx.include_sci; + flow.params.egress.use_es = pSc->tx.use_es; + flow.params.egress.use_scb = pSc->tx.use_scb; + flow.params.egress.confidentiality_offset = 0; + flow.params.egress.conf_protect = pSc->tx.conf_protect; + + RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_action_rule_set(phydev, dir, flow_base, &flow)); + + /* TC */ + hwsa.direction = dir; + hwsa.flow_index = flow_base; + hwsa.sa_expired_irq = 1; + hwsa.update_en = 1; + hwsa.next_sa_valid = 0; + rtk_phylib_memcpy(hwsa.sci, pSc->tx.sci, 8 * sizeof(uint8)); + for (an = 0; an < 4; an++) + { + hwsa.an = an; + hwsa.next_sa_index = PHY_MACSEC_HW_SA_ID(sc_id, ((an + 1) % 4)); + RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_sa_set(phydev, dir, PHY_MACSEC_HW_SA_ID(sc_id, an), &hwsa)); + } + } + else /* RTK_MACSEC_DIR_INGRESS */ + { + PR_DBG("[%s]SCI = 0x%02X%02X%02X%02X%02X%02X%02X%02X\n", __FUNCTION__, + pSc->rx.sci[0], pSc->rx.sci[1], pSc->rx.sci[2], pSc->rx.sci[3], + pSc->rx.sci[4], pSc->rx.sci[5], pSc->rx.sci[6], pSc->rx.sci[7]); + PR_DBG("[%s]rp %u/rw %u\n", __FUNCTION__, + pSc->rx.replay_protect, pSc->rx.replay_window); + /* match rule */ + match.fTagged = 1; + match.fControlPacket = 0; + rtk_phylib_memcpy(match.sci, pSc->rx.sci, 8 * sizeof(uint8)); + switch (pSc->rx.flow_match) + { + case RTK_MACSEC_MATCH_SCI: + tci_an = 0x20; + match.matchMask = (MACSEC_SA_MATCH_MASK_MACSEC_SCI + | MACSEC_SA_MATCH_MASK_MACSEC_TCI_AN_SC + | MACSEC_SA_MATCH_MASK_CTRL_PKT); + break; + + case RTK_MACSEC_MATCH_MAC_SA: + tci_an = 0x0; + rtk_phylib_memcpy(match.mac_sa, pSc->rx.mac_sa.octet, 6 * sizeof(uint8)); + match.matchMask = (MACSEC_SA_MATCH_MASK_MAC_SA_FULL + | MACSEC_SA_MATCH_MASK_MACSEC_TCI_AN_SC + | MACSEC_SA_MATCH_MASK_CTRL_PKT); + break; + + default: + return RTK_PHYLIB_ERR_INPUT; + } + for (an = 0; an < 4; an++) + { + match.macsec_TCI_AN = an | tci_an; + match.flow_index = flow_base + an; + RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_match_rule_set(phydev, dir, (flow_base + an), &match)); + } + MACSEC_SC_MATCH(macsec_db, dir, sc_id) = pSc->rx.flow_match; + + /* flow ctrl */ + flow.flow_type = RTK_MACSEC_FLOW_INGRESS; + flow.dest_port = RTK_MACSEC_PORT_CONTROLLED; + + flow.params.ingress.replay_protect = pSc->rx.replay_protect; + flow.params.ingress.sa_in_use = 0; + flow.params.ingress.validate_frames = pSc->rx.validate_frames; + flow.params.ingress.confidentiality_offset = 0; + + for (an = 0; an < 4; an++) + { + flow.sa_index = PHY_MACSEC_HW_SA_ID(sc_id, an); + RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_action_rule_set(phydev, dir, (flow_base + an), &flow)); + } + + /* TC */ + hwsa.direction = dir; + hwsa.replay_window = pSc->rx.replay_window; + rtk_phylib_memcpy(hwsa.sci, pSc->rx.sci, 8 * sizeof(uint8)); + for (an = 0; an < 4; an++) + { + RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_sa_set(phydev, dir, PHY_MACSEC_HW_SA_ID(sc_id, an), &hwsa)); + } + } + + RTK_PHYLIB_BYTE_ARRAY_TO_VAL(macsec_db->sci[dir][sc_id], hwsa.sci, 0, 8); + + MACSEC_SC_CS(macsec_db, dir, sc_id) = cs; + MACSEC_SC_SET_USED(macsec_db, dir, sc_id); + PR_DBG("[%s]%s SC:%u \n", __FUNCTION__, (RTK_MACSEC_DIR_EGRESS == dir) ? "TX" : "RX", sc_id); + + if (dir == RTK_MACSEC_DIR_EGRESS) + { + RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_enable_set(phydev, dir, flow_base, active)); + } + else /* RTK_MACSEC_DIR_INGRESS */ + { + for (an = 0; an < 4; an++) + { + sa_id = PHY_MACSEC_HW_SA_ID(sc_id, an); + if(MACSEC_SA_IS_USED(macsec_db, dir, sa_id)) + { + RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_enable_set(phydev, dir, flow_base + an, active)); + } + } + } + + *pSc_id = sc_id; + return ret; +} + +int32 rtk_phylib_macsec_sc_update(rtk_phydev *phydev, rtk_macsec_dir_t dir, + rtk_macsec_sc_t *pSc, uint32 *pSc_id, uint8 active) +{ + struct rtk_phy_priv *priv = phydev->priv; + rtk_macsec_port_info_t *macsec_db = priv->macsec; + + int32 ret = 0; + uint8 an = 0, tci_an = 0; + uint32 sc_id = 0xFFFFFFFF; + uint32 flow_base = 0; + rtk_macsec_cipher_t cs = RTK_MACSEC_CIPHER_GCM_ASE_128; + phy_macsec_flow_action_t flow[4]; + phy_macsec_flow_match_t match[4]; + phy_macsec_sa_params_t hwsa[4]; + uint64 sci_val = 0; + rtk_macsec_sc_status_t sc_status; + uint32 hwsa_flags = 0, hwsa_key_bytes = 0; + + rtk_phylib_memset(&flow, 0, sizeof(flow)); + rtk_phylib_memset(&match, 0, sizeof(match)); + rtk_phylib_memset(&hwsa, 0, sizeof(hwsa)); + + if (pSc == NULL || pSc_id == NULL) + return RTK_PHYLIB_ERR_INPUT; + + if (RTK_MACSEC_DIR_INGRESS == dir) + RTK_PHYLIB_BYTE_ARRAY_TO_VAL(sci_val, pSc->rx.sci, 0, 8); + else + RTK_PHYLIB_BYTE_ARRAY_TO_VAL(sci_val, pSc->tx.sci, 0, 8); + RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_sci_to_scid(phydev, dir, sci_val, &sc_id)); + PR_DBG("[%s]update %s SC %u\n", __FUNCTION__, (RTK_MACSEC_DIR_EGRESS == dir) ? "TX" : "RX", sc_id); + flow_base = PHY_MACSEC_HW_FLOW_ID(sc_id); + + RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_sc_status_get(phydev, dir, sc_id, &sc_status)); + if (dir == RTK_MACSEC_DIR_EGRESS) + { + if (sc_status.tx.hw_sc_flow_status == 1) /* Disable active flow before update */ + { + RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_enable_set(phydev, dir, flow_base, DISABLED)); + } + + RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_action_rule_get(phydev, dir, flow_base, &flow[0])); + RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_match_rule_get(phydev, dir, flow_base, &match[0])); + for (an = 0; an < 4; an++) + { + RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_sa_get(phydev, dir, PHY_MACSEC_HW_SA_ID(sc_id, an), &hwsa[an])); + } + } + else /* RTK_MACSEC_DIR_INGRESS */ + { + for (an = 0; an < 4; an++) + { + if (sc_status.rx.hw_sc_flow_status[an] == 1) /* Disable active flow before update */ + { + RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_enable_set(phydev, dir, flow_base + an, DISABLED)); + } + + RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_action_rule_get(phydev, dir, flow_base + an, &flow[0])); + RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_match_rule_get(phydev, dir, flow_base + an, &match[0])); + RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_sa_get(phydev, dir, PHY_MACSEC_HW_SA_ID(sc_id, an), &hwsa[an])); + } + } + + cs = (dir == RTK_MACSEC_DIR_EGRESS) ? (pSc->tx.cipher_suite) : (pSc->rx.cipher_suite); + switch (cs) + { + case RTK_MACSEC_CIPHER_GCM_ASE_128: + hwsa_flags = 0; + hwsa_key_bytes = 16; + if(dir == RTK_MACSEC_DIR_INGRESS && pSc->rx.replay_window > 0xFFFFFFFF) + { + PR_ERR("PN replay_window %u out of range 0~%u", pSc->rx.replay_window, (0xFFFFFFFF)); + return RTK_PHYLIB_ERR_INPUT; + } + break; + case RTK_MACSEC_CIPHER_GCM_ASE_256: + hwsa_flags = 0; + hwsa_key_bytes = 32; + if(dir == RTK_MACSEC_DIR_INGRESS && pSc->rx.replay_window > 0xFFFFFFFF) + { + PR_ERR("PN replay_window %u out of range 0~%u", pSc->rx.replay_window, (0xFFFFFFFF)); + return RTK_PHYLIB_ERR_INPUT; + } + break; + case RTK_MACSEC_CIPHER_GCM_ASE_XPN_128: + hwsa_flags = RTK_PHY_MACSEC_SA_FLAG_XPN; + hwsa_key_bytes = 16; + if(dir == RTK_MACSEC_DIR_INGRESS && pSc->rx.replay_window > 0x40000000) + { + PR_ERR("XPN replay_window %u out of range 0~%u", pSc->rx.replay_window, (0x40000000)); + return RTK_PHYLIB_ERR_INPUT; + } + break; + case RTK_MACSEC_CIPHER_GCM_ASE_XPN_256: + hwsa_flags = RTK_PHY_MACSEC_SA_FLAG_XPN; + hwsa_key_bytes = 32; + if(dir == RTK_MACSEC_DIR_INGRESS && pSc->rx.replay_window > 0x40000000) + { + PR_ERR("XPN replay_window %u out of range 0~%u", pSc->rx.replay_window, (0x40000000)); + return RTK_PHYLIB_ERR_INPUT; + } + break; + default: + return RTK_PHYLIB_ERR_INPUT; + } + + if (dir == RTK_MACSEC_DIR_EGRESS) + { + PR_DBG("[%s]SCI = 0x%02X%02X%02X%02X%02X%02X%02X%02X\n", __FUNCTION__, + pSc->tx.sci[0], pSc->tx.sci[1], pSc->tx.sci[2], pSc->tx.sci[3], + pSc->tx.sci[4], pSc->tx.sci[5], pSc->tx.sci[6], pSc->tx.sci[7]); + PR_DBG("[%s]pf %u/is %u/es %u/scb %u/cp %u\n", __FUNCTION__, + pSc->tx.protect_frame, pSc->tx.include_sci, pSc->tx.use_es, pSc->tx.use_scb, pSc->tx.conf_protect); + + /* match rule */ + switch (pSc->tx.flow_match) + { + case RTK_MACSEC_MATCH_NON_CTRL: + match[0].matchMask = MACSEC_SA_MATCH_MASK_CTRL_PKT; + break; + + case RTK_MACSEC_MATCH_MAC_DA: + rtk_phylib_memcpy(match[0].mac_da, pSc->tx.mac_da.octet, 6 * sizeof(uint8)); + match[0].matchMask = (MACSEC_SA_MATCH_MASK_MAC_DA_FULL + | MACSEC_SA_MATCH_MASK_CTRL_PKT); + break; + + default: + return RTK_PHYLIB_ERR_INPUT; + } + match[0].flow_index = flow_base; + RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_match_rule_set(phydev, dir, flow_base, &match[0])); + MACSEC_SC_MATCH(macsec_db, dir, sc_id) = pSc->tx.flow_match; + + /* flow ctrl */ + flow[0].params.egress.protect_frame = pSc->tx.protect_frame; + flow[0].params.egress.include_sci = pSc->tx.include_sci; + flow[0].params.egress.use_es = pSc->tx.use_es; + flow[0].params.egress.use_scb = pSc->tx.use_scb; + flow[0].params.egress.conf_protect = pSc->tx.conf_protect; + + RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_action_rule_set(phydev, dir, flow_base, &flow[0])); + + /* TC */ + for (an = 0; an < 4; an++) + { + rtk_phylib_memcpy(hwsa[an].sci, pSc->tx.sci, 8 * sizeof(uint8)); + hwsa[an].flags = hwsa_flags; + hwsa[an].key_bytes = hwsa_key_bytes; + RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_sa_set(phydev, dir, PHY_MACSEC_HW_SA_ID(sc_id, an), &hwsa[an])); + + } + } + else /* RTK_MACSEC_DIR_INGRESS */ + { + PR_DBG("[%s]SCI = 0x%02X%02X%02X%02X%02X%02X%02X%02X\n", __FUNCTION__, + pSc->rx.sci[0], pSc->rx.sci[1], pSc->rx.sci[2], pSc->rx.sci[3], + pSc->rx.sci[4], pSc->rx.sci[5], pSc->rx.sci[6], pSc->rx.sci[7]); + PR_DBG("[%s]rp %u/rw %u\n", __FUNCTION__, + pSc->rx.replay_protect, pSc->rx.replay_window); + MACSEC_SC_MATCH(macsec_db, dir, sc_id) = pSc->rx.flow_match; + for (an = 0; an < 4; an++) + { + /* match rule */ + rtk_phylib_memcpy(match[an].sci, pSc->rx.sci, 8 * sizeof(uint8)); + switch (pSc->rx.flow_match) + { + case RTK_MACSEC_MATCH_SCI: + tci_an = 0x20; + match[an].matchMask = (MACSEC_SA_MATCH_MASK_MACSEC_SCI + | MACSEC_SA_MATCH_MASK_MACSEC_TCI_AN_SC + | MACSEC_SA_MATCH_MASK_CTRL_PKT); + break; + + case RTK_MACSEC_MATCH_MAC_SA: + tci_an = 0x0; + rtk_phylib_memcpy(match[an].mac_sa, pSc->rx.mac_sa.octet, 6 * sizeof(uint8)); + match[an].matchMask = (MACSEC_SA_MATCH_MASK_MAC_SA_FULL + | MACSEC_SA_MATCH_MASK_MACSEC_TCI_AN_SC + | MACSEC_SA_MATCH_MASK_CTRL_PKT); + break; + + default: + return RTK_PHYLIB_ERR_INPUT; + } + match[an].macsec_TCI_AN = an | tci_an; + match[an].flow_index = flow_base + an; + RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_match_rule_set(phydev, dir, (flow_base + an), &match[an])); + + + /* flow ctrl */ + flow[an].params.ingress.replay_protect = pSc->rx.replay_protect; + flow[an].params.ingress.validate_frames = pSc->rx.validate_frames; + flow[an].sa_index = PHY_MACSEC_HW_SA_ID(sc_id, an); + RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_action_rule_set(phydev, dir, (flow_base + an), &flow[an])); + + /* TC */ + hwsa[an].replay_window = pSc->rx.replay_window; + rtk_phylib_memcpy(hwsa[an].sci, pSc->rx.sci, 8 * sizeof(uint8)); + + hwsa[an].flags = hwsa_flags; + hwsa[an].key_bytes =hwsa_key_bytes; + + RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_sa_set(phydev, dir, PHY_MACSEC_HW_SA_ID(sc_id, an), &hwsa[an])); + } + } + RTK_PHYLIB_BYTE_ARRAY_TO_VAL(macsec_db->sci[dir][sc_id], hwsa[0].sci, 0, 8); + + MACSEC_SC_CS(macsec_db, dir, sc_id) = cs; + MACSEC_SC_SET_USED(macsec_db, dir, sc_id); + PR_DBG("[%s]%s SC:%u \n", __FUNCTION__, (RTK_MACSEC_DIR_EGRESS == dir) ? "TX" : "RX", sc_id); + + /* Recover active flow after update */ + if (dir == RTK_MACSEC_DIR_EGRESS) + { + if (sc_status.tx.hw_sc_flow_status == 1) + { + RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_enable_set(phydev, dir, flow_base, ENABLED)); + } + } + else /* RTK_MACSEC_DIR_INGRESS */ + { + for (an = 0; an < 4; an++) + { + if (sc_status.rx.hw_sc_flow_status[an] == 1) + { + RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_enable_set(phydev, dir, flow_base + an, ENABLED)); + } + } + } + + *pSc_id = sc_id; + return ret; +} + +int32 rtk_phylib_macsec_sc_get(rtk_phydev *phydev, rtk_macsec_dir_t dir, + uint32 sc_id, rtk_macsec_sc_t *pSc) +{ + struct rtk_phy_priv *priv = phydev->priv; + rtk_macsec_port_info_t *macsec_db = priv->macsec; + + int32 ret = 0; + uint32 flow_base = 0, sa_base = 0; + phy_macsec_flow_action_t flow; + phy_macsec_flow_match_t match; + phy_macsec_sa_params_t hwsa; + + if (pSc == NULL) + return RTK_PHYLIB_ERR_INPUT; + if (sc_id >= MACSEC_SC_MAX(macsec_db)) + return RTK_PHYLIB_ERR_INPUT; + + if (MACSEC_SC_IS_CLEAR(macsec_db, dir, sc_id)) + { + PR_ERR("%s SC %u is not existed!",(RTK_MACSEC_DIR_EGRESS == dir) ? "TX" : "RX",sc_id); + return RTK_PHYLIB_ERR_ENTRY_NOTFOUND; + } + rtk_phylib_memset(pSc, 0, sizeof(rtk_macsec_sc_t)); + + flow_base = PHY_MACSEC_HW_FLOW_ID(sc_id); + sa_base = PHY_MACSEC_HW_SA_ID(sc_id, 0); + + RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_action_rule_get(phydev, dir, flow_base, &flow)); + RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_sa_get(phydev, dir, sa_base, &hwsa)); + + if (dir == RTK_MACSEC_DIR_EGRESS) + { + pSc->tx.cipher_suite = MACSEC_SC_CS(macsec_db, dir, sc_id); + pSc->tx.flow_match = MACSEC_SC_MATCH(macsec_db, dir, sc_id); + if (RTK_MACSEC_MATCH_MAC_DA == pSc->tx.flow_match) + { + RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_match_rule_get(phydev, dir, flow_base, &match)); + rtk_phylib_memcpy(pSc->tx.mac_da.octet, match.mac_da, 6 * sizeof(uint8)); + } + + pSc->tx.protect_frame = flow.params.egress.protect_frame; + pSc->tx.include_sci = flow.params.egress.include_sci; + pSc->tx.use_es = flow.params.egress.use_es; + pSc->tx.use_scb = flow.params.egress.use_scb; + pSc->tx.conf_protect = flow.params.egress.conf_protect; + + rtk_phylib_memcpy(pSc->tx.sci, hwsa.sci, 8 * sizeof(uint8)); + } + else /* RTK_MACSEC_DIR_INGRESS */ + { + pSc->rx.cipher_suite = MACSEC_SC_CS(macsec_db, dir, sc_id); + pSc->rx.flow_match = MACSEC_SC_MATCH(macsec_db, dir, sc_id); + RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_match_rule_get(phydev, dir, flow_base, &match)); + if (RTK_MACSEC_MATCH_MAC_SA == pSc->rx.flow_match) + { + rtk_phylib_memcpy(pSc->rx.mac_sa.octet, match.mac_sa, 6 * sizeof(uint8)); + } + rtk_phylib_memcpy(pSc->rx.sci, match.sci, 8 * sizeof(uint8)); + + pSc->rx.replay_protect = flow.params.ingress.replay_protect; + pSc->rx.validate_frames = flow.params.ingress.validate_frames; + + pSc->rx.replay_window = hwsa.replay_window; + } + return ret; +} + +int32 rtk_phylib_macsec_sc_del(rtk_phydev *phydev, rtk_macsec_dir_t dir, uint32 sc_id) +{ + struct rtk_phy_priv *priv = phydev->priv; + rtk_macsec_port_info_t *macsec_db = priv->macsec; + + int32 ret = 0; + uint8 an = 0; + uint32 flow_base = 0, flow_id = 0; + + PR_DBG("[%s]%s SC:%u\n", __FUNCTION__, (RTK_MACSEC_DIR_EGRESS == dir) ? "TX" : "RX", sc_id); + + if (sc_id >= MACSEC_SC_MAX(macsec_db)) + return RTK_PHYLIB_ERR_INPUT; + + if (MACSEC_SC_IS_CLEAR(macsec_db, dir, sc_id)) + return 0; + + flow_base = PHY_MACSEC_HW_FLOW_ID(sc_id); + + if (dir == RTK_MACSEC_DIR_EGRESS) + { + flow_id = flow_base; + + RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_enable_set(phydev, dir, flow_id, 0)); + RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_match_rule_del(phydev, dir, flow_id)); + RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_action_rule_del(phydev, dir, flow_id)); + + for (an = 0; an < 4; an++) + { + RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_sa_del(phydev, dir, PHY_MACSEC_HW_SA_ID(sc_id, an))); + MACSEC_SA_UNSET_USED(macsec_db, dir, PHY_MACSEC_HW_SA_ID(sc_id, an)); + } + } + else /* RTK_MACSEC_DIR_INGRESS */ + { + for (an = 0; an < 4; an++) + { + flow_id = flow_base + an; + RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_enable_set(phydev, dir, flow_id, 0)); + RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_match_rule_del(phydev, dir, flow_id)); + RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_action_rule_del(phydev, dir, flow_id)); + RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_sa_del(phydev, dir, PHY_MACSEC_HW_SA_ID(sc_id, an))); + MACSEC_SA_UNSET_USED(macsec_db, dir, PHY_MACSEC_HW_SA_ID(sc_id, an)); + } + } + + macsec_db->sci[dir][sc_id] = 0; + MACSEC_SC_UNSET_USED(macsec_db, dir, sc_id); + return ret; +} + +int32 rtk_phylib_macsec_sc_status_get(rtk_phydev *phydev, rtk_macsec_dir_t dir, + uint32 sc_id, rtk_macsec_sc_status_t *pSc_status) +{ + struct rtk_phy_priv *priv = phydev->priv; + rtk_macsec_port_info_t *macsec_db = priv->macsec; + + int32 ret = 0; + phy_macsec_flow_action_t flow; + uint32 flow_base = 0, flow_id = 0; + uint32 flow_reg = 0, flow_data = 0; + rtk_enable_t ena = DISABLED; + rtk_macsec_an_t an; + + if (pSc_status == NULL) + return RTK_PHYLIB_ERR_INPUT; + if (sc_id >= MACSEC_SC_MAX(macsec_db)) + return RTK_PHYLIB_ERR_INPUT; + if (MACSEC_SC_IS_CLEAR(macsec_db, dir, sc_id)) + { + PR_ERR("%s SC %u is not existed!", (RTK_MACSEC_DIR_EGRESS == dir) ? "TX" : "RX",sc_id); + return RTK_PHYLIB_ERR_ENTRY_NOTFOUND; + } + rtk_phylib_memset(pSc_status, 0, sizeof(rtk_macsec_sc_status_t)); + + flow_base = PHY_MACSEC_HW_FLOW_ID(sc_id); + RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_action_rule_get(phydev, dir, flow_base, &flow)); + + if (dir == RTK_MACSEC_DIR_EGRESS) + { + RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_action_rule_get(phydev, dir, flow_base, &flow)); + RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_enable_get(phydev, dir, flow_base, &ena)); + pSc_status->tx.hw_flow_index = flow_base; + pSc_status->tx.hw_sa_index = flow.sa_index; + pSc_status->tx.sa_inUse = flow.params.egress.sa_in_use; + pSc_status->tx.hw_sc_flow_status = (ena == ENABLED) ? 1 : 0; + pSc_status->tx.running_an = PHY_MACSEC_HW_SA_TO_AN(flow.sa_index); + + flow_reg = MACSEC_REG_SAM_FLOW_CTRL(flow_base); + MACSEC_REG_GET(phydev, dir, flow_reg, &flow_data); + pSc_status->tx.hw_flow_data = flow_data; + } + else /* RTK_MACSEC_DIR_INGRESS */ + { + pSc_status->rx.hw_flow_base = flow_base; + for (an = RTK_MACSEC_AN0; an < RTK_MACSEC_AN_MAX; an++) + { + flow_id = flow_base + an; + RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_action_rule_get(phydev, dir, flow_id, &flow)); + RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_enable_get(phydev, dir, flow_id, &ena)); + pSc_status->rx.hw_sa_index[an] = flow.sa_index; + pSc_status->rx.sa_inUse[an] = flow.params.ingress.sa_in_use; + pSc_status->rx.hw_sc_flow_status[an] = (ena == ENABLED) ? 1 : 0; + + flow_reg = MACSEC_REG_SAM_FLOW_CTRL(flow_id); + MACSEC_REG_GET(phydev, dir, flow_reg, &flow_data); + pSc_status->rx.hw_flow_data[an] = flow_data; + } + } + + return ret; +} + +int32 rtk_phylib_macsec_sa_activate(rtk_phydev *phydev, rtk_macsec_dir_t dir, + uint32 sc_id, rtk_macsec_an_t an) +{ + struct rtk_phy_priv *priv = phydev->priv; + rtk_macsec_port_info_t *macsec_db = priv->macsec; + + int32 ret = 0; + uint32 sa_id = PHY_MACSEC_HW_SA_ID(sc_id, an); + uint32 flow_id = 0; + phy_macsec_flow_action_t flow; + + if (sc_id >= MACSEC_SC_MAX(macsec_db)) + return RTK_PHYLIB_ERR_INPUT; + if (sa_id >= MACSEC_SA_MAX(macsec_db)) + return RTK_PHYLIB_ERR_INPUT; + if (MACSEC_SC_IS_CLEAR(macsec_db, dir, sc_id)) + { + PR_ERR("[%s]%s SC %u is not existed!", __FUNCTION__, + (RTK_MACSEC_DIR_EGRESS == dir) ? "TX" : "RX",sc_id); + return RTK_PHYLIB_ERR_ENTRY_NOTFOUND; + } + if (MACSEC_SA_IS_CLEAR(macsec_db, dir, sa_id)) + { + PR_ERR("[%s]%s SA(SC %u, AN %u) is not existed!", __FUNCTION__, + (RTK_MACSEC_DIR_EGRESS == dir) ? "TX" : "RX", sc_id, an); + return RTK_PHYLIB_ERR_ENTRY_NOTFOUND; + } + + PR_DBG("[%s]%s SC:%u AN:%u\n", __FUNCTION__, (RTK_MACSEC_DIR_EGRESS == dir) ? "TX" : "RX", sc_id, an); + if (dir == RTK_MACSEC_DIR_EGRESS) + { + flow_id = PHY_MACSEC_HW_FLOW_ID(sc_id); + RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_action_rule_get(phydev, dir, flow_id, &flow)); + flow.sa_index = sa_id; + flow.params.egress.sa_in_use = 1; + } + else /* RTK_MACSEC_DIR_INGRESS */ + { + flow_id = PHY_MACSEC_HW_FLOW_ID(sc_id) + an; + RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_action_rule_get(phydev, dir, flow_id, &flow)); + flow.sa_index = sa_id; + flow.params.ingress.sa_in_use = 1; + } + + RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_action_rule_set(phydev, dir, flow_id, &flow)); + RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_enable_set(phydev, dir, flow_id, ENABLED)); + return ret; +} + +int32 rtk_phylib_macsec_rxsa_disable(rtk_phydev *phydev, uint32 rxsc_id, + rtk_macsec_an_t an) +{ + struct rtk_phy_priv *priv = phydev->priv; + rtk_macsec_port_info_t *macsec_db = priv->macsec; + + int32 ret = 0; + rtk_macsec_dir_t dir = RTK_MACSEC_DIR_INGRESS; + uint32 sa_id = PHY_MACSEC_HW_SA_ID(rxsc_id, an); + uint32 flow_id = PHY_MACSEC_HW_FLOW_ID(rxsc_id) + an; + phy_macsec_flow_action_t flow; + + PR_DBG("[%s]SC %u AN %u\n", __FUNCTION__, rxsc_id, an); + + if (rxsc_id >= MACSEC_SC_MAX(macsec_db)) + return RTK_PHYLIB_ERR_INPUT; + if (sa_id >= MACSEC_SA_MAX(macsec_db)) + return RTK_PHYLIB_ERR_INPUT; + if (MACSEC_SC_IS_CLEAR(macsec_db, dir, rxsc_id)) + { + PR_ERR("%s SC %u is not existed!", + (RTK_MACSEC_DIR_EGRESS == dir) ? "TX" : "RX" ,rxsc_id); + return RTK_PHYLIB_ERR_ENTRY_NOTFOUND; + } + if (MACSEC_SA_IS_CLEAR(macsec_db, dir, sa_id)) + { + PR_ERR("[%s]%s SA(SC %u, AN %u) is not existed!", __FUNCTION__, + (RTK_MACSEC_DIR_EGRESS == dir) ? "TX" : "RX", rxsc_id, an); + return RTK_PHYLIB_ERR_ENTRY_NOTFOUND; + } + + RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_action_rule_get(phydev, dir, flow_id, &flow)); + flow.params.ingress.sa_in_use = 0; + RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_action_rule_set(phydev, dir, flow_id, &flow)); + + return ret; +} + +int32 +rtk_phylib_macsec_txsa_disable(rtk_phydev *phydev, uint32 txsc_id) +{ + struct rtk_phy_priv *priv = phydev->priv; + rtk_macsec_port_info_t *macsec_db = priv->macsec; + + int32 ret = 0; + rtk_macsec_dir_t dir = RTK_MACSEC_DIR_EGRESS; + uint32 flow_id = PHY_MACSEC_HW_FLOW_ID(txsc_id); + phy_macsec_flow_action_t flow; + + PR_DBG("[%s]SC %u\n", __FUNCTION__, txsc_id); + + if (txsc_id >= MACSEC_SC_MAX(macsec_db)) + return RTK_PHYLIB_ERR_INPUT; + + if (MACSEC_SC_IS_CLEAR(macsec_db, dir, txsc_id)) + { + PR_ERR("%s SC %u is not existed!", + (RTK_MACSEC_DIR_EGRESS == dir) ? "TX" : "RX",txsc_id); + return RTK_PHYLIB_ERR_ENTRY_NOTFOUND; + } + + RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_action_rule_get(phydev, dir, flow_id, &flow)); + flow.params.egress.sa_in_use = 0; + RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_action_rule_set(phydev, dir, flow_id, &flow)); + + return ret; +} + +int32 rtk_phylib_macsec_sa_create(rtk_phydev *phydev, rtk_macsec_dir_t dir, + uint32 sc_id, rtk_macsec_an_t an, rtk_macsec_sa_t *pSa) +{ + struct rtk_phy_priv *priv = phydev->priv; + rtk_macsec_port_info_t *macsec_db = priv->macsec; + + int32 ret = 0; + phy_macsec_sa_params_t hwsa; + rtk_macsec_cipher_t cs; + rtk_macsec_sc_status_t sc_status; + uint32 sa_id = PHY_MACSEC_HW_SA_ID(sc_id, an); + uint32 post_sa_id = PHY_MACSEC_HW_SA_ID(sc_id, ((an + 3) % 4)); + uint8 flow_state_recover = 0; + uint32 flow_id = PHY_MACSEC_HW_FLOW_ID(sc_id) + an; + + PR_DBG("[%s]%s SC:%u AN:%u\n", __FUNCTION__, (RTK_MACSEC_DIR_EGRESS == dir) ? "TX" : "RX", sc_id, an); + + if (pSa == NULL) + return RTK_PHYLIB_ERR_INPUT; + if (sc_id >= MACSEC_SC_MAX(macsec_db)) + return RTK_PHYLIB_ERR_INPUT; + if (sa_id >= MACSEC_SA_MAX(macsec_db)) + return RTK_PHYLIB_ERR_INPUT; + + if (MACSEC_SC_IS_CLEAR(macsec_db, dir, sc_id)) + { + PR_ERR("%s SC %u is not existed!", + (RTK_MACSEC_DIR_EGRESS == dir) ? "TX" : "RX", sc_id); + return RTK_PHYLIB_ERR_ENTRY_NOTFOUND; + } + + cs = MACSEC_SC_CS(macsec_db, dir, sc_id); + PR_DBG("[%s]CS: %u, key_bytes: %u\n", __FUNCTION__, cs, pSa->key_bytes); + switch (cs) + { + case RTK_MACSEC_CIPHER_GCM_ASE_128: + case RTK_MACSEC_CIPHER_GCM_ASE_XPN_128: + if (pSa->key_bytes != 16) + { + PR_ERR("Bad key_bytes:%u for AES-128.", pSa->key_bytes); + return RTK_PHYLIB_ERR_INPUT; + } + break; + + case RTK_MACSEC_CIPHER_GCM_ASE_XPN_256: + case RTK_MACSEC_CIPHER_GCM_ASE_256: + if (pSa->key_bytes != 32) + { + PR_ERR("Bad key_bytes:%u for AES-256.", pSa->key_bytes); + return RTK_PHYLIB_ERR_INPUT; + } + break; + default: + return RTK_PHYLIB_ERR_FAILED; + } + + RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_sc_status_get(phydev, dir, sc_id, &sc_status)); + if (dir == RTK_MACSEC_DIR_EGRESS) + { + /* disable flow for running AN */ + if ((sc_status.tx.hw_sc_flow_status == 1) && (sc_status.tx.running_an == an)) + { + RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_enable_set(phydev, dir, flow_id, DISABLED)); + flow_state_recover = 1; + } + + } + else /* RTK_MACSEC_DIR_INGRESS */ + { + if (sc_status.rx.hw_sc_flow_status[an] == 1) + { + RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_rxsa_disable(phydev, sc_id, an)); + flow_state_recover = 1; + } + } + + RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_sa_get(phydev, dir, sa_id, &hwsa)); + switch (cs) + { + case RTK_MACSEC_CIPHER_GCM_ASE_128: + case RTK_MACSEC_CIPHER_GCM_ASE_256: + hwsa.key_bytes = pSa->key_bytes; + hwsa.seq = pSa->pn; + hwsa.seq_h = 0; + rtk_phylib_memset(hwsa.salt, 0x0, sizeof(uint8) * 12); + rtk_phylib_memset(hwsa.ssci, 0x0, sizeof(uint8) * 4); + break; + + case RTK_MACSEC_CIPHER_GCM_ASE_XPN_128: + case RTK_MACSEC_CIPHER_GCM_ASE_XPN_256: + hwsa.flags = RTK_PHY_MACSEC_SA_FLAG_XPN; + hwsa.key_bytes = pSa->key_bytes; + hwsa.seq = pSa->pn; + hwsa.seq_h = pSa->pn_h; + rtk_phylib_memcpy(hwsa.salt, pSa->salt, sizeof(uint8) * 12); + rtk_phylib_memcpy(hwsa.ssci, pSa->ssci, sizeof(uint8) * 4); + break; + default: + return RTK_PHYLIB_ERR_FAILED; + } + + rtk_phylib_memcpy(hwsa.key, pSa->key, sizeof(uint8) * hwsa.key_bytes); + RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_sa_set(phydev, dir, sa_id, &hwsa)); + + if ((dir == RTK_MACSEC_DIR_EGRESS) && MACSEC_SA_IS_USED(macsec_db, dir, post_sa_id)) + { + RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_sa_get(phydev, dir, post_sa_id, &hwsa)); + hwsa.next_sa_valid = 1; + RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_sa_set(phydev, dir, post_sa_id, &hwsa)); + } + + if (flow_state_recover == 1) + { + RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_enable_set(phydev, dir, flow_id, ENABLED)); + } + + MACSEC_SA_SET_USED(macsec_db, dir, sa_id); + return ret; +} + +int32 rtk_phylib_macsec_sa_get(rtk_phydev *phydev, rtk_macsec_dir_t dir, + uint32 sc_id, rtk_macsec_an_t an, rtk_macsec_sa_t *pSa) +{ + struct rtk_phy_priv *priv = phydev->priv; + rtk_macsec_port_info_t *macsec_db = priv->macsec; + + int32 ret = 0; + uint32 sa_id = PHY_MACSEC_HW_SA_ID(sc_id, an); + phy_macsec_sa_params_t hwsa; + + if (pSa == NULL) + return RTK_PHYLIB_ERR_INPUT; + if (sc_id >= MACSEC_SC_MAX(macsec_db)) + return RTK_PHYLIB_ERR_INPUT; + if (sa_id >= MACSEC_SA_MAX(macsec_db)) + return RTK_PHYLIB_ERR_INPUT; + if (MACSEC_SC_IS_CLEAR(macsec_db, dir, sc_id)) + { + PR_ERR("%s SC %u is not existed!", (RTK_MACSEC_DIR_EGRESS == dir) ? "TX" : "RX",sc_id); + return RTK_PHYLIB_ERR_ENTRY_NOTFOUND; + } + if (MACSEC_SC_IS_CLEAR(macsec_db, dir, sc_id)) + { + PR_ERR("[%s]%s SA(SC %u, AN %u) is not existed!", __FUNCTION__, + (RTK_MACSEC_DIR_EGRESS == dir) ? "TX" : "RX", sc_id, an); + return RTK_PHYLIB_ERR_ENTRY_NOTFOUND; + } + + rtk_phylib_memset(pSa, 0x0, sizeof(rtk_macsec_sa_t)); + RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_sa_get(phydev, dir, sa_id, &hwsa)); + + pSa->key_bytes = hwsa.key_bytes; + rtk_phylib_memcpy(pSa->key, hwsa.key, sizeof(uint8) * hwsa.key_bytes); + if (hwsa.flags & RTK_PHY_MACSEC_SA_FLAG_XPN) + { + pSa->pn = hwsa.seq; + pSa->pn_h = hwsa.seq_h; + rtk_phylib_memcpy(pSa->salt, hwsa.salt, sizeof(uint8) * 12); + rtk_phylib_memcpy(pSa->ssci, hwsa.ssci, sizeof(uint8) * 4); + } + else /* PN */ + { + pSa->pn = hwsa.seq; + } + + return ret; +} + +int32 rtk_phylib_macsec_sa_del(rtk_phydev *phydev, rtk_macsec_dir_t dir, + uint32 sc_id, rtk_macsec_an_t an) +{ + struct rtk_phy_priv *priv = phydev->priv; + rtk_macsec_port_info_t *macsec_db = priv->macsec; + + int32 ret = 0; + uint32 sa_id = PHY_MACSEC_HW_SA_ID(sc_id, an); + phy_macsec_sa_params_t hwsa; + rtk_macsec_sc_status_t sc_status; + + PR_DBG("[%s]%s SC:%u AN:%u\n", __FUNCTION__, (RTK_MACSEC_DIR_EGRESS == dir) ? "TX" : "RX", sc_id, an); + + if (sc_id >= MACSEC_SC_MAX(macsec_db)) + return RTK_PHYLIB_ERR_INPUT; + if (sa_id >= MACSEC_SA_MAX(macsec_db)) + return RTK_PHYLIB_ERR_INPUT; + if (MACSEC_SC_IS_CLEAR(macsec_db, dir, sc_id)) + { + PR_ERR("%s SC %u is not existed!", + (RTK_MACSEC_DIR_EGRESS == dir) ? "TX" : "RX",sc_id); + return RTK_PHYLIB_ERR_ENTRY_NOTFOUND; + } + + RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_sc_status_get(phydev, dir, sc_id, &sc_status)); + if (dir == RTK_MACSEC_DIR_EGRESS) + { + /* disable flow for running AN */ + if ((sc_status.tx.hw_sc_flow_status == 1) && (sc_status.tx.running_an == an)) + { + RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_txsa_disable(phydev, sc_id)); + } + } + else /* RTK_MACSEC_DIR_INGRESS */ + { + if (sc_status.rx.hw_sc_flow_status[an] == 1) + { + RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_rxsa_disable(phydev, sc_id, an)); + } + } + + RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_sa_get(phydev, dir, sa_id, &hwsa)); + rtk_phylib_memset(hwsa.key, 0, sizeof(uint8) * RTK_MACSEC_MAX_KEY_LEN); + rtk_phylib_memset(hwsa.salt, 0x0, sizeof(uint8) * 12); + rtk_phylib_memset(hwsa.ssci, 0x0, sizeof(uint8) * 4); + hwsa.seq = 0; + hwsa.seq_h = 0; + RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_sa_set(phydev, dir, sa_id, &hwsa)); + + MACSEC_SA_UNSET_USED(macsec_db, dir, sa_id); + return ret; +} + +int32 rtk_phylib_macsec_stat_port_get(rtk_phydev *phydev, rtk_macsec_stat_t stat, + uint64 *pCnt) +{ + struct rtk_phy_priv *priv = phydev->priv; + rtk_macsec_port_info_t *macsec_db = priv->macsec; + int32 ret = 0; + uint64 cnt_h = 0, cnt_l = 0; + uint32 data= 0; + + if (pCnt == NULL) + return RTK_PHYLIB_ERR_INPUT; + + switch (stat) + { + case RTK_MACSEC_STAT_InPktsUntagged: + MACSEC_REG_GET(phydev, RTK_MACSEC_DIR_INGRESS, 0xC418, &data); + cnt_l = (uint64)data; + MACSEC_REG_GET(phydev, RTK_MACSEC_DIR_INGRESS, 0xC41C, &data); + cnt_h = (uint64)data; + macsec_db->port_stats.InPktsUntagged += ((cnt_h << 32) | cnt_l); + *pCnt = macsec_db->port_stats.InPktsUntagged; + break; + case RTK_MACSEC_STAT_InPktsNoTag: + MACSEC_REG_GET(phydev, RTK_MACSEC_DIR_INGRESS, 0xC410, &data); + cnt_l = (uint64)data; + MACSEC_REG_GET(phydev, RTK_MACSEC_DIR_INGRESS, 0xC414, &data); + cnt_h = (uint64)data; + macsec_db->port_stats.InPktsNoTag += ((cnt_h << 32) | cnt_l); + *pCnt = macsec_db->port_stats.InPktsNoTag; + break; + case RTK_MACSEC_STAT_InPktsBadTag: + MACSEC_REG_GET(phydev, RTK_MACSEC_DIR_INGRESS, 0xC428, &data); + cnt_l = (uint64)data; + MACSEC_REG_GET(phydev, RTK_MACSEC_DIR_INGRESS, 0xC42C, &data); + cnt_h = (uint64)data; + macsec_db->port_stats.InPktsBadTag += ((cnt_h << 32) | cnt_l); + *pCnt = macsec_db->port_stats.InPktsBadTag; + break; + case RTK_MACSEC_STAT_InPktsUnknownSCI: + MACSEC_REG_GET(phydev, RTK_MACSEC_DIR_INGRESS, 0xC440, &data); + cnt_l = (uint64)data; + MACSEC_REG_GET(phydev, RTK_MACSEC_DIR_INGRESS, 0xC444, &data); + cnt_h = (uint64)data; + macsec_db->port_stats.InPktsUnknownSCI += ((cnt_h << 32) | cnt_l); + *pCnt = macsec_db->port_stats.InPktsUnknownSCI; + break; + case RTK_MACSEC_STAT_InPktsNoSCI: + MACSEC_REG_GET(phydev, RTK_MACSEC_DIR_INGRESS, 0xC438, &data); + cnt_l = (uint64)data; + MACSEC_REG_GET(phydev, RTK_MACSEC_DIR_INGRESS, 0xC43C, &data); + cnt_h = (uint64)data; + macsec_db->port_stats.InPktsNoSCI += ((cnt_h << 32) | cnt_l); + *pCnt = macsec_db->port_stats.InPktsNoSCI; + break; + case RTK_MACSEC_STAT_OutPktsUntagged: + MACSEC_REG_GET(phydev, RTK_MACSEC_DIR_EGRESS, 0xC418, &data); + cnt_l = (uint64)data; + MACSEC_REG_GET(phydev, RTK_MACSEC_DIR_EGRESS, 0xC41C, &data); + cnt_h = (uint64)data; + macsec_db->port_stats.OutPktsUntagged += ((cnt_h << 32) | cnt_l); + *pCnt = macsec_db->port_stats.OutPktsUntagged; + break; + default: + return RTK_PHYLIB_ERR_INPUT; + } + return ret; +} + +int32 rtk_phylib_macsec_stat_txsa_get(rtk_phydev *phydev, uint32 sc_id, + rtk_macsec_an_t an, rtk_macsec_txsa_stat_t stat, uint64 *pCnt) +{ + struct rtk_phy_priv *priv = phydev->priv; + rtk_macsec_port_info_t *macsec_db = priv->macsec; + + int32 ret = 0; + uint64 cnt_h = 0, cnt_l = 0; + uint32 data= 0, base = 0; + uint32 sa_id = PHY_MACSEC_HW_SA_ID(sc_id, an); + rtk_macsec_dir_t dir = RTK_MACSEC_DIR_EGRESS; + + if (pCnt == NULL) + return RTK_PHYLIB_ERR_INPUT; + if (sc_id >= MACSEC_SC_MAX(macsec_db)) + return RTK_PHYLIB_ERR_INPUT; + if (sa_id >= MACSEC_SA_MAX(macsec_db)) + return RTK_PHYLIB_ERR_INPUT; + if (MACSEC_SC_IS_CLEAR(macsec_db, dir, sc_id)) + { + return RTK_PHYLIB_ERR_ENTRY_NOTFOUND; + } + if (MACSEC_SA_IS_CLEAR(macsec_db, dir, sa_id)) + { + return RTK_PHYLIB_ERR_ENTRY_NOTFOUND; + } + + base = (sa_id * 0x80); + switch (stat) + { + case RTK_MACSEC_TXSA_STAT_OutPktsTooLong: + MACSEC_REG_GET(phydev, dir, (base + 0x8018), &data); + cnt_l = (uint64)data; + MACSEC_REG_GET(phydev, dir, (base + 0x801C), &data); + cnt_h = (uint64)data; + macsec_db->txsa_stats[sa_id]->OutPktsTooLong += ((cnt_h << 32) | cnt_l); + *pCnt = macsec_db->txsa_stats[sa_id]->OutPktsTooLong; + break; + case RTK_MACSEC_TXSA_STAT_OutOctetsProtectedEncrypted: + MACSEC_REG_GET(phydev, dir, (base + 0x8000), &data); + cnt_l = (uint64)data; + MACSEC_REG_GET(phydev, dir, (base + 0x8004), &data); + cnt_h = (uint64)data; + macsec_db->txsa_stats[sa_id]->OutOctetsProtectedEncrypted += ((cnt_h << 32) | cnt_l); + *pCnt = macsec_db->txsa_stats[sa_id]->OutOctetsProtectedEncrypted; + break; + case RTK_MACSEC_TXSA_STAT_OutPktsProtectedEncrypted: + MACSEC_REG_GET(phydev, dir, (base + 0x8010), &data); + cnt_l = (uint64)data; + MACSEC_REG_GET(phydev, dir, (base + 0x8014), &data); + cnt_h = (uint64)data; + macsec_db->txsa_stats[sa_id]->OutPktsProtectedEncrypted += ((cnt_h << 32) | cnt_l); + *pCnt = macsec_db->txsa_stats[sa_id]->OutPktsProtectedEncrypted; + break; + + default: + return RTK_PHYLIB_ERR_INPUT; + } + return ret; +} + +int32 rtk_phylib_macsec_stat_rxsa_get(rtk_phydev *phydev, uint32 sc_id, + rtk_macsec_an_t an, rtk_macsec_rxsa_stat_t stat, uint64 *pCnt) +{ + struct rtk_phy_priv *priv = phydev->priv; + rtk_macsec_port_info_t *macsec_db = priv->macsec; + + int32 ret = 0; + uint64 cnt_h = 0, cnt_l = 0; + uint32 data= 0, base = 0; + uint32 sa_id = PHY_MACSEC_HW_SA_ID(sc_id, an); + rtk_macsec_dir_t dir = RTK_MACSEC_DIR_INGRESS; + + if (pCnt == NULL) + return RTK_PHYLIB_ERR_INPUT; + if (sc_id >= MACSEC_SC_MAX(macsec_db)) + return RTK_PHYLIB_ERR_INPUT; + if (sa_id >= MACSEC_SA_MAX(macsec_db)) + return RTK_PHYLIB_ERR_INPUT; + if (MACSEC_SC_IS_CLEAR(macsec_db, dir, sc_id)) + { + return RTK_PHYLIB_ERR_ENTRY_NOTFOUND; + } + if (MACSEC_SA_IS_CLEAR(macsec_db, dir, sa_id)) + { + return RTK_PHYLIB_ERR_ENTRY_NOTFOUND; + } + + base = (sa_id * 0x80); + switch (stat) + { + case RTK_MACSEC_RXSA_STAT_InPktsUnusedSA: + MACSEC_REG_GET(phydev, dir, (base + 0x8048), &data); + cnt_l = (uint64)data; + MACSEC_REG_GET(phydev, dir, (base + 0x804C), &data); + cnt_h = (uint64)data; + macsec_db->rxsa_stats[sa_id]->InPktsUnusedSA += ((cnt_h << 32) | cnt_l); + *pCnt = macsec_db->rxsa_stats[sa_id]->InPktsUnusedSA; + break; + case RTK_MACSEC_RXSA_STAT_InPktsNotUsingSA: + MACSEC_REG_GET(phydev, dir, (base + 0x8040), &data); + cnt_l = (uint64)data; + MACSEC_REG_GET(phydev, dir, (base + 0x8044), &data); + cnt_h = (uint64)data; + macsec_db->rxsa_stats[sa_id]->InPktsNotUsingSA += ((cnt_h << 32) | cnt_l); + *pCnt = macsec_db->rxsa_stats[sa_id]->InPktsNotUsingSA; + break; + case RTK_MACSEC_RXSA_STAT_InPktsUnchecked: + MACSEC_REG_GET(phydev, dir, (base + 0x8010), &data); + cnt_l = (uint64)data; + MACSEC_REG_GET(phydev, dir, (base + 0x8014), &data); + cnt_h = (uint64)data; + macsec_db->rxsa_stats[sa_id]->InPktsUnchecked += ((cnt_h << 32) | cnt_l); + *pCnt = macsec_db->rxsa_stats[sa_id]->InPktsUnchecked; + break; + case RTK_MACSEC_RXSA_STAT_InPktsDelayed: + MACSEC_REG_GET(phydev, dir, (base + 0x8018), &data); + cnt_l = (uint64)data; + MACSEC_REG_GET(phydev, dir, (base + 0x801C), &data); + cnt_h = (uint64)data; + macsec_db->rxsa_stats[sa_id]->InPktsDelayed += ((cnt_h << 32) | cnt_l); + *pCnt = macsec_db->rxsa_stats[sa_id]->InPktsDelayed; + break; + case RTK_MACSEC_RXSA_STAT_InPktsLate: + MACSEC_REG_GET(phydev, dir, (base + 0x8020), &data); + cnt_l = (uint64)data; + MACSEC_REG_GET(phydev, dir, (base + 0x8024), &data); + cnt_h = (uint64)data; + macsec_db->rxsa_stats[sa_id]->InPktsLate += ((cnt_h << 32) | cnt_l); + *pCnt = macsec_db->rxsa_stats[sa_id]->InPktsLate; + break; + case RTK_MACSEC_RXSA_STAT_InPktsOK: + MACSEC_REG_GET(phydev, dir, (base + 0x8028), &data); + cnt_l = (uint64)data; + MACSEC_REG_GET(phydev, dir, (base + 0x802C), &data); + cnt_h = (uint64)data; + macsec_db->rxsa_stats[sa_id]->InPktsOK += ((cnt_h << 32) | cnt_l); + *pCnt = macsec_db->rxsa_stats[sa_id]->InPktsOK; + break; + case RTK_MACSEC_RXSA_STAT_InPktsInvalid: + MACSEC_REG_GET(phydev, dir, (base + 0x8030), &data); + cnt_l = (uint64)data; + MACSEC_REG_GET(phydev, dir, (base + 0x8034), &data); + cnt_h = (uint64)data; + macsec_db->rxsa_stats[sa_id]->InPktsInvalid += ((cnt_h << 32) | cnt_l); + *pCnt = macsec_db->rxsa_stats[sa_id]->InPktsInvalid; + break; + case RTK_MACSEC_RXSA_STAT_InPktsNotValid: + MACSEC_REG_GET(phydev, dir, (base + 0x8038), &data); + cnt_l = (uint64)data; + MACSEC_REG_GET(phydev, dir, (base + 0x803C), &data); + cnt_h = (uint64)data; + macsec_db->rxsa_stats[sa_id]->InPktsNotValid += ((cnt_h << 32) | cnt_l); + *pCnt = macsec_db->rxsa_stats[sa_id]->InPktsNotValid; + break; + case RTK_MACSEC_RXSA_STAT_InOctetsDecryptedValidated: + MACSEC_REG_GET(phydev, dir, (base + 0x8000), &data); + cnt_l = (uint64)data; + MACSEC_REG_GET(phydev, dir, (base + 0x8004), &data); + cnt_h = (uint64)data; + macsec_db->rxsa_stats[sa_id]->InOctetsDecryptedValidated += ((cnt_h << 32) | cnt_l); + *pCnt = macsec_db->rxsa_stats[sa_id]->InOctetsDecryptedValidated; + break; + default: + return RTK_PHYLIB_ERR_INPUT; + } + return ret; +} + +/* ------------------------------------------------------------------------------------------------------------------------------- */ +/* id mapping */ +int32 rtk_phylib_macsec_sci_to_scid(rtk_phydev *phydev, rtk_macsec_dir_t dir, uint64 sci, uint32 *sc_id) +{ + struct rtk_phy_priv *priv = phydev->priv; + rtk_macsec_port_info_t *macsec_db = priv->macsec; + + int32 ret = RTK_PHYLIB_ERR_ENTRY_NOTFOUND; + uint32 i = 0; + uint64 sci_val = 0; + + PR_DBG("[%s]sci: 0x%016llX\n", __FUNCTION__, sci); + for (i = 0; i < MACSEC_SC_MAX(macsec_db); i++) + { + if(MACSEC_SC_IS_USED(macsec_db, dir, i)) + { + sci_val = macsec_db->sci[dir][i]; + PR_DBG("[%s]find sci: 0x%016llX, sc id: %u, 0x%016llX\n", __FUNCTION__, sci, i, sci_val); + if (sci_val == sci) + { + *sc_id = i; + return 0; + } + } + } + return ret; +} + diff --git a/sources/rtk-be550/src/hal/phy/rtk_phylib_macsec.h b/sources/rtk-be550/src/hal/phy/rtk_phylib_macsec.h new file mode 100755 index 00000000..103c695a --- /dev/null +++ b/sources/rtk-be550/src/hal/phy/rtk_phylib_macsec.h @@ -0,0 +1,329 @@ +/* + * SPDX-License-Identifier: GPL-2.0-only + * + * Copyright (c) 2023 Realtek Semiconductor Corp. All rights reserved. + */ + +#ifndef __RTK_PHYLIB_MACSEC_H +#define __RTK_PHYLIB_MACSEC_H + +#if defined(RTK_PHYDRV_IN_LINUX) + #include "type.h" + #include "rtk_phylib_def.h" +#endif + +#define PHY_MACSEC_DEV_EGRESS 0 +#define PHY_MACSEC_DEV_INGRESS 1 + +#define MACSEC_REG_OFFS 4 + +#define PHY_MACSEC_HW_SA_ID(sc_id, an) (sc_id * 4 + an) +#define PHY_MACSEC_HW_FLOW_ID(sc_id) (sc_id * 4) +#define PHY_MACSEC_HW_SA_TO_AN(sa_id) (sa_id % 4) + +#define PHY_MACSEC_MAX_SA_EN_SIZE 24 //32-bit words +#define PHY_MACSEC_MAX_SA_IN_SIZE 20 +#define PHY_MACSEC_MAX_SA_SIZE PHY_MACSEC_MAX_SA_EN_SIZE + +#define MACSEC_XFORM_REC_BASE (0x0000) +#define MACSEC_XFORM_REC_SIZE(dir) ((RTK_MACSEC_DIR_EGRESS == dir) ? PHY_MACSEC_MAX_SA_EN_SIZE : PHY_MACSEC_MAX_SA_IN_SIZE ) + +#define MACSEC_REG_XFORM_REC(n, dir) (MACSEC_XFORM_REC_BASE + MACSEC_XFORM_REC_SIZE(dir) * \ + MACSEC_REG_OFFS * (n % 128)) +#define MACSEC_REG_XFORM_REC_OFFS(n, dir, off) (MACSEC_REG_XFORM_REC(n, dir) + off * MACSEC_REG_OFFS) + + +#define MACSEC_REG_SAM_MAC_SA_MATCH_LO(n) (0x4000 + 16 * MACSEC_REG_OFFS * (n % 128)) +#define MACSEC_REG_SAM_MAC_SA_MATCH_HI(n) (0x4004 + 16 * MACSEC_REG_OFFS * (n % 128)) +#define MACSEC_REG_SAM_MAC_DA_MATCH_LO(n) (0x4008 + 16 * MACSEC_REG_OFFS * (n % 128)) +#define MACSEC_REG_SAM_MAC_DA_MATCH_HI(n) (0x400C + 16 * MACSEC_REG_OFFS * (n % 128)) + +#define MACSEC_REG_SAM_MISC_MATCH(n) (0x4010 + 16 * MACSEC_REG_OFFS * (n % 128)) +#define MACSEC_REG_SAM_SCI_MATCH_LO(n) (0x4014 + 16 * MACSEC_REG_OFFS * (n % 128)) +#define MACSEC_REG_SAM_SCI_MATCH_HI(n) (0x4018 + 16 * MACSEC_REG_OFFS * (n % 128)) +#define MACSEC_REG_SAM_MASK(n) (0x401C + 16 * MACSEC_REG_OFFS * (n % 128)) +#define MACSEC_REG_SAM_EXT_MATCH(n) (0x4020 + 16 * MACSEC_REG_OFFS * (n % 128)) + +#define MACSEC_REG_SAM_ENTRY_ENABLE(n) (0x6000 + (n * MACSEC_REG_OFFS)) +#define MACSEC_REG_SAM_ENTRY_TOGGLE(n) (0x6040 + (n * MACSEC_REG_OFFS)) +#define MACSEC_REG_SAM_ENTRY_SET(n) (0x6080 + (n * MACSEC_REG_OFFS)) +#define MACSEC_REG_SAM_ENTRY_CLEAR(n) (0x60C0 + (n * MACSEC_REG_OFFS)) +#define MACSEC_REG_SAM_ENTRY_ENABLE_CTRL (0x6100) +#define MACSEC_REG_SAM_IN_FLIGHT (0x6104) + +#define MACSEC_REG_SAM_FLOW_CTRL(n) (0x7000 + MACSEC_REG_OFFS * (n % 128)) + + +#define MACSEC_REG_SAM_IN_FLIGHT (0x6104) +#define MACSEC_REG_COUNT_CTRL (0xC810) +#define MACSEC_REG_IG_CC_CONTROL (0xE840) +#define MACSEC_REG_COUNT_SECFAIL1 (0xF124) +#define MACSEC_REG_CTX_CTRL (0xF408) +#define MACSEC_REG_CTX_UPD_CTRL (0xF430) +#define MACSEC_REG_SAM_CP_TAG (0x7900) +#define MACSEC_REG_SAM_NM_PARAMS (0x7940) +#define MACSEC_REG_SAM_NM_FLOW_NCP (0x7944) +#define MACSEC_REG_SAM_NM_FLOW_CP (0x7948) + +#define MACSEC_REG_MISC_CONTROL (0x797C) + +// Mask last byte received of MAC source address +#define MACSEC_SA_MATCH_MASK_MAC_SA_0 BIT_0 +#define MACSEC_SA_MATCH_MASK_MAC_SA_1 BIT_1 +#define MACSEC_SA_MATCH_MASK_MAC_SA_2 BIT_2 +#define MACSEC_SA_MATCH_MASK_MAC_SA_3 BIT_3 +#define MACSEC_SA_MATCH_MASK_MAC_SA_4 BIT_4 +// Mask first byte received of MAC source address +#define MACSEC_SA_MATCH_MASK_MAC_SA_5 BIT_5 + +#define MACSEC_SA_MATCH_MASK_MAC_SA_FULL (BIT_0 | BIT_1 | BIT_2 | BIT_3 | BIT_4 | BIT_5) + +// Mask last byte received of MAC destination address +#define MACSEC_SA_MATCH_MASK_MAC_DA_0 BIT_6 +#define MACSEC_SA_MATCH_MASK_MAC_DA_1 BIT_7 +#define MACSEC_SA_MATCH_MASK_MAC_DA_2 BIT_8 +#define MACSEC_SA_MATCH_MASK_MAC_DA_3 BIT_9 +#define MACSEC_SA_MATCH_MASK_MAC_DA_4 BIT_10 +// Mask first byte received of MAC destination address +#define MACSEC_SA_MATCH_MASK_MAC_DA_5 BIT_11 + +#define MACSEC_SA_MATCH_MASK_MAC_DA_FULL (BIT_6 | BIT_7 | BIT_8 | BIT_9 | BIT_10 | BIT_11) + +#define MACSEC_SA_MATCH_MASK_MAC_ETYPE BIT_12 +#define MACSEC_SA_MATCH_MASK_VLAN_VALID BIT_13 +#define MACSEC_SA_MATCH_MASK_QINQ_FOUND BIT_14 +#define MACSEC_SA_MATCH_MASK_STAG_VALID BIT_15 +#define MACSEC_SA_MATCH_MASK_QTAG_VALID BIT_16 +#define MACSEC_SA_MATCH_MASK_VLAN_UP BIT_17 +#define MACSEC_SA_MATCH_MASK_VLAN_ID BIT_18 +#define MACSEC_SA_MATCH_MASK_SRC_PORT BIT_19 +#define MACSEC_SA_MATCH_MASK_CTRL_PKT BIT_20 + +// For ingress only +#define MACSEC_SA_MATCH_MASK_MACSEC_SCI BIT_23 +#define MACSEC_SA_MATCH_MASK_MACSEC_TCI_AN_SC (BIT_24 | BIT_25 | BIT_29) + +#define MACSEC_SAB_CW0_MACSEC_EG32 0x9241e066 +#define MACSEC_SAB_CW0_MACSEC_IG32 0xd241e06f +#define MACSEC_SAB_CW0_MACSEC_EG64 0xa241e066 +#define MACSEC_SAB_CW0_MACSEC_IG64 0xe241a0ef +#define MACSEC_SAB_CW0_AES128 0x000a0000 +#define MACSEC_SAB_CW0_AES256 0x000e0000 + + +#define RTK_MACSEC_PORT_COMMON 0 +#define RTK_MACSEC_PORT_RESERVED 1 +#define RTK_MACSEC_PORT_CONTROLLED 2 +#define RTK_MACSEC_PORT_UNCONTROLLED 3 + + + +typedef struct phy_macsec_flow_action_e_s +{ + // 1 - enable frame protection, + // 0 - bypass frame through device + uint8 protect_frame; + + // 1 - SA is in use, packets classified for it can be transformed + // 0 - SA not in use, packets classified for it can not be transformed + uint8 sa_in_use; + + // 1 - inserts explicit SCI in the packet, + // 0 - use implicit SCI (not transferred) + uint8 include_sci; + + // 1 - enable ES bit in the generated SecTAG + // 0 - disable ES bit in the generated SecTAG + uint8 use_es; + + // 1 - enable SCB bit in the generated SecTAG + // 0 - disable SCB bit in the generated SecTAG + uint8 use_scb; + + // Number of VLAN tags to bypass for egress processing. + // Valid values: 0, 1 and 2. + // This feature is only available on HW4.1 and possibly later versions. + uint8 tag_bypass_size; + + // 1 - Does not update sa_in_use flag + // 0 - Update sa_in_use flag + uint8 sa_index_update_by_hw; + + // The number of bytes (in the range of 0-127) that are authenticated but + // not encrypted following the SecTAG in the encrypted packet. Values + // 65-127 are reserved in HW < 4.0 and should not be used there. + uint8 confidentiality_offset; + + // 1 - enable confidentiality protection + // 0 - disable confidentiality protection + uint8 conf_protect; + +} phy_macsec_flow_action_e_t; + +typedef struct phy_macsec_flow_action_i_s +{ + // 1 - enable replay protection + // 0 - disable replay protection + uint8 replay_protect; + + // true - SA is in use, packets classified for it can be transformed + // false - SA not in use, packets classified for it can not be transformed + uint8 sa_in_use; + + // MACsec frame validation level + rtk_macsec_validate_t validate_frames; + + // The number of bytes (in the range of 0-127) that are authenticated but + // not encrypted following the SecTAG in the encrypted packet. + uint8 confidentiality_offset; + +} phy_macsec_flow_action_i_t; + +typedef struct phy_macsec_flow_action_bd_s +{ + // 1 - enable statistics counting for the associated SA + // 0 - disable statistics counting for the associated SA + uint8 sa_in_use; +} phy_macsec_flow_action_bd_t; + +typedef struct phy_macsec_flow_action_s +{ + uint32 sa_index; + + rtk_macsec_flow_type_t flow_type; + union + { + phy_macsec_flow_action_e_t egress; + phy_macsec_flow_action_i_t ingress; + phy_macsec_flow_action_bd_t bypass_drop; + } params; + + uint8 dest_port; + +} phy_macsec_flow_action_t; + +typedef struct +{ + // index for flow control rule entry + uint32 flow_index; + + // Packet field values to match + + // MAC source address + uint8 mac_sa[6]; + + // MAC destination address + uint8 mac_da[6]; + + // EtherType + uint16 etherType; + + // SCI, for ingress only + uint8 sci[8]; + + // Parsed VLAN ID compare value + uint16 vlan_id; + + // Parsed VLAN valid flag compare value + uint8 fVLANValid; + + // Parsed QinQ found flag compare value + uint8 fQinQFound; + + // Parsed STAG valid flag compare value + uint8 fSTagValid; + + // Parsed QTAG valid flag compare value + uint8 fQTagFound; + + // Parsed VLAN User Priority compare value + uint8 vlanUserPriority; + + // Packet is a control packet (as pre-decoded) compare value + uint8 fControlPacket; + + // true - allow packets without a MACsec tag to match + uint8 fUntagged; + + // true - allow packets with a standard and valid MACsec tag to match + uint8 fTagged; + + // true - allow packets with an invalid MACsec tag to match + uint8 fBadTag; + + // true - allow packets with a MACsec tag indicating KaY handling + // to be done to match + uint8 fKayTag; + + // Source port compare value + uint8 sourcePort; + + // Priority of this entry for determining the actual transform used + // on a match when multiple entries match, 0 = lowest, 15 = highest. + // In case of identical priorities, the lowest numbered entry takes + // precedence. + uint8 matchPriority; + + // MACsec TCI/AN byte compare value, bits are individually masked for + // comparing. The TCI bits are in bits [7:2] while the AN bits reside + // in bits [1:0]. the macsec_TCI_AN field should only be set to + // non-zero for an actual MACsec packet. + uint8 macsec_TCI_AN; + + // Match mask for the SA flow rules, see MACSEC_SA_MATCH_MASK_* + uint32 matchMask; + + // Parsed inner VLAN ID compare value + uint16 vlanIdInner; + + // Parsed inner VLAN UP compare value + uint8 vlanUpInner; + +} phy_macsec_flow_match_t; + +typedef struct { + uint8 key_offs; + uint8 hkey_offs; + uint8 seq_offs; + uint8 mask_offs; + uint8 ctx_salt_offs; + uint8 iv_offs; + uint8 upd_ctrl_offs; +} phy_macsec_sa_offset_t; + +#define RTK_PHY_MACSEC_SA_FLAG_XPN 0x00000001U //Extended Packet Numbering + +typedef struct +{ + uint32 context_id; //keep 0 for create + rtk_macsec_dir_t direction; + uint32 flow_index; //the flow entry index apply to this SA + uint32 flags; // a bitmap of RTK_PHY_MACSEC_SA_FLAG_* + + uint8 an; // 2-bit AN inserted in SecTAG (egress). + uint8 sci[8]; // 8-byte SCI.([0:5] = MAC address, [6:7] = port index) + + uint8 key[RTK_MACSEC_MAX_KEY_LEN]; // MACsec Key. + uint32 key_bytes; // Size of the MACsec key in bytes (16 for AES128, 32 for AES256). + + uint8 salt[12]; // 12-byte salt (64-bit sequence numbers). + uint8 ssci[4]; // 4-byte SSCI value (64-bit sequence numbers). + + uint32 seq; // sequence number. + uint32 seq_h; // High part of sequence number (64-bit sequence numbers) + uint32 replay_window; // Size of the replay window, 0 for strict ordering (ingress). + + /* update ctrl */ + uint32 next_sa_index; // SA index of the next chained SA (egress). + uint8 sa_expired_irq; // 1 if SA expired IRQ is to be generated. + uint8 next_sa_valid; // SA Index field is a valid SA. + uint8 update_en; // Set to true if the SA must be updated. +} phy_macsec_sa_params_t; + +typedef void (*phy_macsec_aes_cb)( + const uint8 * const In_p, + uint8 * const Out_p, + const uint8 * const Key_p, + const unsigned int KeyByteCount); + +#endif /* __RTK_PHYLIB_MACSEC_H */ diff --git a/sources/rtk-be550/src/hal/phy/rtk_phylib_rtl826xb.c b/sources/rtk-be550/src/hal/phy/rtk_phylib_rtl826xb.c new file mode 100755 index 00000000..a2069813 --- /dev/null +++ b/sources/rtk-be550/src/hal/phy/rtk_phylib_rtl826xb.c @@ -0,0 +1,568 @@ +/* + * SPDX-License-Identifier: GPL-2.0-only + * + * Copyright (c) 2023 Realtek Semiconductor Corp. All rights reserved. + */ + +#include "rtk_phylib_rtl826xb.h" + +/* Indirect Register Access APIs */ +int rtk_phylib_826xb_sds_read(rtk_phydev *phydev, uint32 page, uint32 reg, uint8 msb, uint8 lsb, uint32 *pData) +{ + int32 ret = 0; + uint32 rData = 0; + uint32 op = (page & 0x3f) | ((reg & 0x1f) << 6) | (0x8000); + uint32 i = 0; + uint32 mask = 0; + mask = UINT32_BITS_MASK(msb,lsb); + + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 323, 15, 0, op)); + + for (i = 0; i < 10; i++) + { + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_read(phydev, 30, 323, 15, 15, &rData)); + if (rData == 0) + { + break; + } + rtk_phylib_udelay(10); + } + if (i == 10) + { + return -1; + } + + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_read(phydev, 30, 322, 15, 0, &rData)); + *pData = REG32_FIELD_GET(rData, lsb, mask); + + return ret; +} + +int rtk_phylib_826xb_sds_write(rtk_phydev *phydev, uint32 page, uint32 reg, uint8 msb, uint8 lsb, uint32 data) +{ + int32 ret = 0; + uint32 wData = 0, rData = 0; + uint32 op = (page & 0x3f) | ((reg & 0x1f) << 6) | (0x8800); + uint32 mask = 0; + mask = UINT32_BITS_MASK(msb,lsb); + + RTK_PHYLIB_ERR_CHK(rtk_phylib_826xb_sds_read(phydev, page, reg, 15, 0, &rData)); + + wData = REG32_FIELD_SET(rData, data, lsb, mask); + + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 321, 15, 0, wData)); + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 323, 15, 0, op)); + + return ret; +} + +int rtk_phylib_826xb_indirect_read(rtk_phydev *phydev, uint32 indr_addr, uint32 *pData) +{ + int32 ret = 0; + uint32 rData; + + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 31, 0xA436, 15, 0, indr_addr)); + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_read(phydev, 31, 0xA438, 15, 0, &rData)); + *pData = rData; + + return ret; +} + +int rtk_phylib_826xb_sram_read(rtk_phydev *phydev, uint32 indr_addr, uint8 msb, uint8 lsb, uint32 *pData) +{ + int32 ret = 0; + uint32 mask = 0, rData = 0; + + mask = UINT32_BITS_MASK(msb,lsb); + RTK_PHYLIB_ERR_CHK(rtk_phylib_826xb_indirect_read(phydev, indr_addr, &rData)); + *pData = REG32_FIELD_GET(rData, lsb, mask); + return ret; +} + +/* MACsec */ +int rtk_phylib_826xb_macsec_read(rtk_phydev *phydev, rtk_macsec_dir_t dir, uint32 reg, uint8 msb, uint8 lsb, uint32 *pData) +{ + int32 ret = 0; + uint32 data_h = 0, data_l = 0; + uint32 rData = 0; + uint32 mask = 0; + uint32 data_e = 0; + WAIT_COMPLETE_VAR(); + + mask = UINT32_BITS_MASK(msb,lsb); + + switch(dir) + { + case RTK_MACSEC_DIR_EGRESS: + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0x02FB, 15, 0, reg)); + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0x02FC, 15, 0, 0x10)); + WAIT_COMPLETE(10000000) + { + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_read(phydev, 30, 0x02FC, 15, 0, &data_e)); + if ((data_e & 0x10) == 0x0) + { + #ifdef MACSEC_DBG_PRINT + if (_t_wait != 0) + PR_DBG("[%s-%u] _t_wait: %u\n", __FUNCTION__, dir, _t_wait); + #endif + break; + } + } + if (WAIT_COMPLETE_IS_TIMEOUT()) + { + PR_ERR("[%s-%u] timeout!\n", __FUNCTION__, dir); + return RTK_PHYLIB_ERR_TIMEOUT; + } + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_read(phydev, 30, 0x02F8, 15, 0, &data_h)); + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_read(phydev, 30, 0x02F9, 15, 0, &data_l)); + break; + case RTK_MACSEC_DIR_INGRESS: + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 31, 0xA6EA, 1, 1, 0x1)); + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0x0300, 15, 0, reg)); + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0x0301, 15, 0, 0x10)); + WAIT_COMPLETE(10000000) + { + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_read(phydev, 30, 0x0301, 15, 0, &data_e)); + if ((data_e & 0x10) == 0x0) + { + #ifdef MACSEC_DBG_PRINT + if (_t_wait != 0) + PR_DBG("[%s-%u] _t_wait: %u\n", __FUNCTION__, dir, _t_wait); + #endif + break; + } + } + if (WAIT_COMPLETE_IS_TIMEOUT()) + { + PR_ERR("[%s-%u] timeout!\n", __FUNCTION__, dir); + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 31, 0xA6EA, 1, 1, 0x0)); + return RTK_PHYLIB_ERR_TIMEOUT; + } + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_read(phydev, 30, 0x02FD, 15, 0, &data_h)); + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_read(phydev, 30, 0x02FE, 15, 0, &data_l)); + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 31, 0xA6EA, 1, 1, 0x0)); + break; + default: + return -1; + } + + rData = (data_h << 16) + data_l; + *pData = REG32_FIELD_GET(rData, lsb, mask); + return ret; +} + +int rtk_phylib_826xb_macsec_write(rtk_phydev *phydev, rtk_macsec_dir_t dir, uint32 reg, uint8 msb, uint8 lsb, uint32 data) +{ + int32 ret = 0; + uint32 data_l = data & 0xFFFF; + uint32 data_h = (data >> 16) & 0xFFFF; + uint32 data_e = 0; + WAIT_COMPLETE_VAR(); + + switch(dir) + { + case RTK_MACSEC_DIR_EGRESS: + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0x02F8 , 15, 0, data_h)); + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0x02F9 , 15, 0, data_l)); + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0x02FB , 15, 0, reg)); + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0x02FC, 15, 0, 0x1)); + WAIT_COMPLETE(10000000) + { + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_read(phydev, 30, 0x02FC, 15, 0, &data_e)); + if ((data_e & 0x1) == 0x0) + { + #ifdef MACSEC_DBG_PRINT + if (_t_wait != 0) + PR_DBG("[%s-%u] _t_wait: %u\n", __FUNCTION__, dir, _t_wait); + #endif + break; + } + } + if (WAIT_COMPLETE_IS_TIMEOUT()) + { + PR_ERR("[%s-%u] timeout!\n", __FUNCTION__, dir); + return RTK_PHYLIB_ERR_TIMEOUT; + } + break; + + case RTK_MACSEC_DIR_INGRESS: + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 31, 0xA6EA, 1, 1, 0x1)); + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0x02FD, 15, 0, data_h)); + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0x02FE, 15, 0, data_l)); + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0x0300, 15, 0, reg)); + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0x0301, 15, 0, 0x1)); + WAIT_COMPLETE(10000000) + { + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_read(phydev, 30, 0x0301, 15, 0, &data_e)); + if ((data_e & 0x1) == 0x0) + { + #ifdef MACSEC_DBG_PRINT + if (_t_wait != 0) + PR_DBG("[%s-%u] _t_wait: %u\n", __FUNCTION__, dir, _t_wait); + #endif + break; + } + } + if (WAIT_COMPLETE_IS_TIMEOUT()) + { + PR_ERR("[%s-%u] timeout!\n", __FUNCTION__, dir); + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 31, 0xA6EA, 1, 1, 0x0)); + return RTK_PHYLIB_ERR_TIMEOUT; + } + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 31, 0xA6EA, 1, 1, 0x0)); + break; + + default: + return RTK_PHYLIB_ERR_INPUT; + } + return ret; +} + +int rtk_phylib_826xb_macsec_init(rtk_phydev *phydev) +{ + int32 ret = 0; + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0x2e0, 1, 0, 0b11)); + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0x2d8, 15, 0, 0x5313)); + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0x2da, 15, 0, 0x0101)); + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0x2dc, 15, 0, 0x0101)); + + //MACSEC_RXSYS_CFG4 + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0x3c6, 7, 0, 0xa)); + //MACSEC_TXLINE_CFG4 + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0x37b, 7, 0, 0x6)); + //loopback fifo_setting + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0x2f7, 15, 0, 0x486c)); + //RA_setting + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0x3f1, 15, 0, 0x72)); + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0x3f0, 15, 0, 0x0b0b)); + //RA ifg + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0x3ee, 15, 13, 0x2)); + return ret; +} + +int rtk_phylib_826xb_macsec_bypass_set(rtk_phydev *phydev, uint32 bypass) +{ + int32 ret = 0; + + if (bypass != 0) + { + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0x2d8, 15, 0, 0x5313)); + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0x3f1, 15, 0, 0x72)); + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0x3f0, 15, 0, 0x0b0b)); + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0x398, 2, 0, 0x7)); + } + else + { + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0x2d8, 15, 0, 0x5111)); + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0x3f1, 15, 0, 0xe871)); + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0x3f0, 15, 0, 0x0c0c)); + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0x398, 2, 0, 0x5)); + } + return ret; +} + +int rtk_phylib_826xb_macsec_bypass_get(rtk_phydev *phydev, uint32 *pBypass) +{ + int32 ret = 0; + uint32 bypass_rx = 0; + uint32 bypass_tx = 0; + + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_read(phydev, 30, 0x2d8, 9, 9, &bypass_rx)); + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_read(phydev, 30, 0x2d8, 1, 1, &bypass_tx)); + + *pBypass = (bypass_rx == 0 && bypass_tx == 0) ? 0 : 1; + + return ret; +} + +/* RTCT */ +int rtk_phylib_826xb_cable_test_start(rtk_phydev *phydev) +{ + int32 ret = 0; + + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 31, 0xa4a0, 10, 10, 1)); + rtk_phylib_mdelay(1000); + + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 31, 0xa422, 15, 0, 0xF2)); + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 31, 0xa422, 0, 0, 1)); + + return 0; +} + +int rtk_phylib_826xb_cable_test_finished_get(rtk_phydev *phydev, uint32 *finished) +{ + int32 ret = 0; + uint32 rData = 0; + + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_read(phydev, 31, 0xA422, 15, 15, &rData)); + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 31, 0xa4a0, 10, 10, 0)); + *finished = rData; + + return 0; +} + +int rtk_phylib_826xb_cable_test_result_get(rtk_phydev *phydev, uint32 pair, rtk_rtct_channel_result_t *result) +{ + int32 ret = 0; + uint32 cable_factor = 7820; + uint32 indr_add_ss = 0x8027 + (pair * 0x4); + uint32 indr_add_lh = 0x8028 + (pair * 0x4); + uint32 indr_add_ll = 0x8029 + (pair * 0x4); + uint32 rtct_status = 0; + uint32 rtct_len_h = 0; + uint32 rtct_len_l = 0; + int32 len_cnt = 0; + + if (pair > 3) + return RTK_PHYLIB_ERR_INPUT; + + rtk_phylib_memset(result, 0x0, sizeof(rtk_rtct_channel_result_t)); + + RTK_PHYLIB_ERR_CHK(rtk_phylib_826xb_sram_read(phydev, indr_add_ss, 15, 8, &rtct_status)); + RTK_PHYLIB_ERR_CHK(rtk_phylib_826xb_sram_read(phydev, indr_add_lh, 15, 8, &rtct_len_h)); + RTK_PHYLIB_ERR_CHK(rtk_phylib_826xb_sram_read(phydev, indr_add_ll, 15, 8, &rtct_len_l)); + + result->cable_status = RTK_PHYLIB_CABLE_STATUS_NORMAL; + switch (rtct_status) + { + case 0x60: /* normal */ + result->cable_status = RTK_PHYLIB_CABLE_STATUS_NORMAL; + break; + case 0x48: /* open */ + result->cable_status |= RTK_PHYLIB_CABLE_STATUS_OPEN; + break; + case 0x50: /* short */ + result->cable_status |= RTK_PHYLIB_CABLE_STATUS_SHORT; + break; + case 0xC0: /* inter pair short */ + result->cable_status |= RTK_PHYLIB_CABLE_STATUS_INTER_PAIR_SHORT; + break; + case 0x42: /* mismatch-open */ + result->cable_status |= RTK_PHYLIB_CABLE_STATUS_MISMATCH; + result->cable_status |= RTK_PHYLIB_CABLE_STATUS_OPEN; + break; + case 0x44: /* mismatch-short */ + result->cable_status |= RTK_PHYLIB_CABLE_STATUS_MISMATCH; + result->cable_status |= RTK_PHYLIB_CABLE_STATUS_SHORT; + break; + default: + result->cable_status |= RTK_PHYLIB_CABLE_STATUS_INTER_PAIR_SHORT; + break; + } + + len_cnt = ((int32)rtct_len_h << 8) + (int32)rtct_len_l - 255; + if (len_cnt < 0) + result->length_cm = 0; + else + result->length_cm = ((uint32)len_cnt * 10000)/cable_factor; + + return 0; +} + +/* Interrupt */ +int rtk_phylib_826xb_intr_enable(rtk_phydev *phydev, uint32 en) +{ + int32 ret = 0; + /* enable normal interrupt IMR_INT_PHY0 */ + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0xE1, 0, 0, (en == 0) ? 0x0 : 0x1)); + + return ret; +} + +int rtk_phylib_826xb_intr_read_clear(rtk_phydev *phydev, uint32 *status) +{ + int32 ret = 0; + uint32 rData = 0; + uint32 rStatus = 0; + + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_read(phydev, 31, 0xA43A, 15, 0, &rData)); + if(rData & BIT_1) + rStatus |= RTK_PHY_INTR_RLFD; + if(rData & BIT_2) + rStatus |= RTK_PHY_INTR_NEXT_PAGE_RECV; + if(rData & BIT_3) + rStatus |= RTK_PHY_INTR_AN_COMPLETE; + if(rData & BIT_4) + rStatus |= RTK_PHY_INTR_LINK_CHANGE; + if(rData & BIT_9) + rStatus |= RTK_PHY_INTR_ALDPS_STATE_CHANGE; + if(rData & BIT_11) + rStatus |= RTK_PHY_INTR_FATAL_ERROR; + if(rData & BIT_7) + rStatus |= RTK_PHY_INTR_WOL; + + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_read(phydev, 30, 0xE2, 15, 0, &rData)); + if(rData & BIT_3) + rStatus |= RTK_PHY_INTR_TM_LOW; + if(rData & BIT_4) + rStatus |= RTK_PHY_INTR_TM_HIGH; + if(rData & BIT_6) + rStatus |= RTK_PHY_INTR_MACSEC; + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0xE2, 15, 0, 0xFF)); + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0x2DC, 15, 0, 0xFF)); + + *status = rStatus; + return ret; +} + +int rtk_phylib_826xb_intr_init(rtk_phydev *phydev) +{ + int32 ret = 0; + uint32 status = 0; + + /* Disable all IMR*/ + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0xE1, 15, 0, 0)); + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0xE3, 15, 0, 0)); + + /* source */ + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0xE4, 15, 0, 0x1)); + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0xE0, 15, 0, 0x2F)); + + /* init common link change */ + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 31, 0xA424, 15, 0, 0x10)); + /* init rlfd */ + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 31, 0xA442, 15, 15, 0x1)); + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 31, 0xA448, 7, 7, 0x1)); + /* init tm */ + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0x1A0, 11, 11, 0x1)); + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0x19D, 11, 11, 0x1)); + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0x1A1, 11, 11, 0x1)); + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0x19F, 11, 11, 0x1)); + /* init WOL */ + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 31, 0xA424, 7, 7, 0x1)); + + /* clear status */ + RTK_PHYLIB_ERR_CHK(rtk_phylib_826xb_intr_read_clear(phydev, &status)); + + return ret; +} + +int rtk_phylib_826xb_link_down_power_saving_set(rtk_phydev *phydev, uint32 ena) +{ + int32 ret = 0; + uint32 data = (ena > 0) ? 0x1 : 0x0; + + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 31, 0xA430, 2, 2, data)); + return ret; +} + +int rtk_phylib_826xb_link_down_power_saving_get(rtk_phydev *phydev, uint32 *pEna) +{ + int32 ret = 0; + uint32 data = 0; + + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_read(phydev, 31, 0xA430, 2, 2, &data)); + *pEna = data; + return ret; +} + +int rtk_phylib_826xb_wol_reset(rtk_phydev *phydev) +{ + int32 ret = 0; + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 31, 0xD8A2, 15, 15, 0)); + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 31, 0xD8A2, 15, 15, 1)); + return ret; +} + +int rtk_phylib_826xb_wol_set(rtk_phydev *phydev, uint32 wol_opts) +{ + int32 ret = 0; + + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 31, 0xD8A0, 13, 13, (wol_opts & RTK_WOL_OPT_LINK) ? 1 : 0)); + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 31, 0xD8A0, 12, 12, (wol_opts & RTK_WOL_OPT_MAGIC) ? 1 : 0)); + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 31, 0xD8A0, 10, 10, (wol_opts & RTK_WOL_OPT_UCAST) ? 1 : 0)); + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 31, 0xD8A0, 9, 9, (wol_opts & RTK_WOL_OPT_MCAST) ? 1 : 0)); + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 31, 0xD8A0, 8, 8, (wol_opts & RTK_WOL_OPT_BCAST) ? 1 : 0)); + + return ret; + +} + +int rtk_phylib_826xb_wol_get(rtk_phydev *phydev, uint32 *pWol_opts) +{ + int32 ret = 0; + uint32 data = 0; + uint32 wol_opts = 0; + + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_read(phydev, 31, 0xD8A0, 13, 13, &data)); + wol_opts |= ((data) ? RTK_WOL_OPT_LINK : 0); + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_read(phydev, 31, 0xD8A0, 12, 12, &data)); + wol_opts |= ((data) ? RTK_WOL_OPT_MAGIC : 0); + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_read(phydev, 31, 0xD8A0, 10, 10, &data)); + wol_opts |= ((data) ? RTK_WOL_OPT_UCAST : 0); + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_read(phydev, 31, 0xD8A0, 9, 9, &data)); + wol_opts |= ((data) ? RTK_WOL_OPT_MCAST : 0); + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_read(phydev, 31, 0xD8A0, 8, 8, &data)); + wol_opts |= ((data) ? RTK_WOL_OPT_BCAST : 0); + + *pWol_opts = wol_opts; + return ret; +} + +int rtk_phylib_826xb_wol_unicast_addr_set(rtk_phydev *phydev, uint8 *mac_addr) +{ + int32 ret = 0; + + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 31, 0xD8C0, 15, 0, (mac_addr[1] << 8 | mac_addr[0]))); + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 31, 0xD8C2, 15, 0, (mac_addr[3] << 8 | mac_addr[2]))); + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 31, 0xD8C4, 15, 0, (mac_addr[5] << 8 | mac_addr[4]))); + return ret; +} + +uint32 rtk_phylib_826xb_wol_multicast_mac2offset(uint8 *mac_addr) +{ + uint32 crc = 0xFFFFFFFF; + uint32 i = 0, j = 0; + uint32 b0 = 0, b1 = 0, b2 = 0, b3 = 0, b4 = 0, b5 = 0; + + for (i = 0; i < 6; i++) { + crc ^= mac_addr[i]; + for (j = 0; j < 8; j++) { + if (crc & 1) { + crc = (crc >> 1) ^ 0xEDB88320; + } else { + crc >>= 1; + } + } + } + crc = ~crc; + + b5 = ((crc & 0b000001) << 5 ); + b4 = ((crc & 0b000010) << 3 ); + b3 = ((crc & 0b000100) << 1 ); + b2 = (((crc & 0b001000) ? 0 : 1) << 2 ); + b1 = (((crc & 0b010000) ? 0 : 1) << 1 ); + b0 = (((crc & 0b100000) ? 0 : 1) << 0 ); + + return (b5 | b4 | b3 | b2 | b1 | b0); +} + +int rtk_phylib_826xb_wol_multicast_mask_add(rtk_phydev *phydev, uint32 offset) +{ + const uint32 cfg_reg[4] = {0xD8C6, 0xD8C8, 0xD8CA, 0xD8CC}; + int32 ret = 0; + uint32 idx = offset/16; + uint32 multicast_cfg = 0; + + + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_read(phydev, 31, cfg_reg[idx], 15, 0, &multicast_cfg)); + + multicast_cfg = (multicast_cfg | (0b1 << (offset % 16))); + + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 31, cfg_reg[idx], 15, 0, multicast_cfg)); + return ret; +} + +int rtk_phylib_826xb_wol_multicast_mask_reset(rtk_phydev *phydev) +{ + const uint32 cfg_reg[4] = {0xD8C6, 0xD8C8, 0xD8CA, 0xD8CC}; + int32 ret = 0; + uint32 idx = 0; + + for (idx = 0; idx < 4; idx++) + { + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 31, cfg_reg[idx], 15, 0, 0)); + } + + return ret; +} diff --git a/sources/rtk-be550/src/hal/phy/rtk_phylib_rtl826xb.h b/sources/rtk-be550/src/hal/phy/rtk_phylib_rtl826xb.h new file mode 100755 index 00000000..377ff41f --- /dev/null +++ b/sources/rtk-be550/src/hal/phy/rtk_phylib_rtl826xb.h @@ -0,0 +1,46 @@ +/* + * SPDX-License-Identifier: GPL-2.0-only + * + * Copyright (c) 2023 Realtek Semiconductor Corp. All rights reserved. + */ + +#ifndef __RTK_PHYLIB_RTL826XB_H +#define __RTK_PHYLIB_RTL826XB_H + +#include "rtk_phylib.h" + +/* Register Access*/ +int rtk_phylib_826xb_sds_read(rtk_phydev *phydev, uint32 page, uint32 reg, uint8 msb, uint8 lsb, uint32 *pData); +int rtk_phylib_826xb_sds_write(rtk_phydev *phydev, uint32 page, uint32 reg, uint8 msb, uint8 lsb, uint32 data); + +/* Interrupt */ +int rtk_phylib_826xb_intr_enable(rtk_phydev *phydev, uint32 en); +int rtk_phylib_826xb_intr_read_clear(rtk_phydev *phydev, uint32 *status); +int rtk_phylib_826xb_intr_init(rtk_phydev *phydev); + +/* Cable Test */ +int rtk_phylib_826xb_cable_test_start(rtk_phydev *phydev);; +int rtk_phylib_826xb_cable_test_finished_get(rtk_phydev *phydev, uint32 *finished); +int rtk_phylib_826xb_cable_test_result_get(rtk_phydev *phydev, uint32 pair, rtk_rtct_channel_result_t *result); + +/* MACsec */ +int rtk_phylib_826xb_macsec_init(rtk_phydev *phydev); +int rtk_phylib_826xb_macsec_read(rtk_phydev *phydev, rtk_macsec_dir_t dir, uint32 reg, uint8 msb, uint8 lsb, uint32 *pData); +int rtk_phylib_826xb_macsec_write(rtk_phydev *phydev, rtk_macsec_dir_t dir, uint32 reg, uint8 msb, uint8 lsb, uint32 data); +int rtk_phylib_826xb_macsec_bypass_set(rtk_phydev *phydev, uint32 bypass); +int rtk_phylib_826xb_macsec_bypass_get(rtk_phydev *phydev, uint32 *pBypass); + +/* Link-down-power-saving/EDPD */ +int rtk_phylib_826xb_link_down_power_saving_set(rtk_phydev *phydev, uint32 ena); +int rtk_phylib_826xb_link_down_power_saving_get(rtk_phydev *phydev, uint32 *pEna); + +/* Wake on Lan */ +int rtk_phylib_826xb_wol_reset(rtk_phydev *phydev); +int rtk_phylib_826xb_wol_set(rtk_phydev *phydev, uint32 wol_opts); +int rtk_phylib_826xb_wol_get(rtk_phydev *phydev, uint32 *pWol_opts); +int rtk_phylib_826xb_wol_unicast_addr_set(rtk_phydev *phydev, uint8 *mac_addr); +int rtk_phylib_826xb_wol_multicast_mask_add(rtk_phydev *phydev, uint32 offset); +int rtk_phylib_826xb_wol_multicast_mask_reset(rtk_phydev *phydev); +uint32 rtk_phylib_826xb_wol_multicast_mac2offset(uint8 *mac_addr); + +#endif /* __RTK_PHYLIB_RTL826XB_H */ diff --git a/sources/rtk-be550/src/hal/phy/type.h b/sources/rtk-be550/src/hal/phy/type.h new file mode 100755 index 00000000..98d7e15e --- /dev/null +++ b/sources/rtk-be550/src/hal/phy/type.h @@ -0,0 +1,117 @@ +/* + * SPDX-License-Identifier: GPL-2.0-only + * + * Copyright (c) 2023 Realtek Semiconductor Corp. All rights reserved. + */ + +#ifndef __COMMON_TYPE_H__ +#define __COMMON_TYPE_H__ + +/* + * Symbol Definition + */ + +#define USING_RTSTK_PKT_AS_RAIL + + +#ifndef NULL +#define NULL 0 +#endif + +#ifndef TRUE +#define TRUE 1 +#endif + +#ifndef FALSE +#define FALSE 0 +#endif + +#ifndef ETHER_ADDR_LEN +#define ETHER_ADDR_LEN 6 +#endif + +#ifndef IP6_ADDR_LEN +#define IP6_ADDR_LEN 16 +#endif + + +/* + * Data Type Declaration + */ +#ifndef uint64 +typedef unsigned long long uint64; +#endif + +#ifndef int64 +typedef signed long long int64; +#endif + +#ifndef uint32 +typedef unsigned int uint32; +#endif + +#ifndef int32 +typedef signed int int32; +#endif + +#ifndef uint16 +typedef unsigned short uint16; +#endif + +#ifndef int16 +typedef signed short int16; +#endif + +#ifndef uint8 +typedef unsigned char uint8; +#endif + +#ifndef int8 +typedef signed char int8; +#endif + +//#define CONFIG_SDK_WORDSIZE_64 /* not ready */ +#ifdef CONFIG_SDK_WORDSIZE_64 + typedef long int intptr; + typedef unsigned long int uintptr; +#else + typedef int intptr; + typedef unsigned int uintptr; +#endif + + +#ifndef ipaddr_t +typedef uint32 ipaddr_t; /* ipv4 address type */ +#endif + +/* configuration mode type */ +typedef enum rtk_enable_e +{ + DISABLED = 0, + ENABLED, + RTK_ENABLE_END +} rtk_enable_t; + +/* initial state of module */ +typedef enum init_state_e +{ + INIT_NOT_COMPLETED = 0, + INIT_COMPLETED, + INIT_STATE_END +} init_state_t; + +/* ethernet address type */ +typedef struct rtk_mac_s +{ + uint8 octet[ETHER_ADDR_LEN]; +} rtk_mac_t; + +typedef uint32 osal_time_t; +typedef uint32 osal_usecs_t; + +/* + * Macro Definition + */ + +#endif /* __COMMON_TYPE_H__ */ + diff --git a/sources/uboot-be550/drivers/net/4xx_enet.c b/sources/uboot-be550/drivers/net/4xx_enet.c new file mode 100644 index 00000000..3c30f42b --- /dev/null +++ b/sources/uboot-be550/drivers/net/4xx_enet.c @@ -0,0 +1,2062 @@ +/* + * SPDX-License-Identifier: GPL-2.0 IBM-pibs + */ +/*-----------------------------------------------------------------------------+ + * + * File Name: enetemac.c + * + * Function: Device driver for the ethernet EMAC3 macro on the 405GP. + * + * Author: Mark Wisner + * + * Change Activity- + * + * Date Description of Change BY + * --------- --------------------- --- + * 05-May-99 Created MKW + * 27-Jun-99 Clean up JWB + * 16-Jul-99 Added MAL error recovery and better IP packet handling MKW + * 29-Jul-99 Added Full duplex support MKW + * 06-Aug-99 Changed names for Mal CR reg MKW + * 23-Aug-99 Turned off SYE when running at 10Mbs MKW + * 24-Aug-99 Marked descriptor empty after call_xlc MKW + * 07-Sep-99 Set MAL RX buffer size reg to ENET_MAX_MTU_ALIGNED / 16 MCG + * to avoid chaining maximum sized packets. Push starting + * RX descriptor address up to the next cache line boundary. + * 16-Jan-00 Added support for booting with IP of 0x0 MKW + * 15-Mar-00 Updated enetInit() to enable broadcast addresses in the + * EMAC0_RXM register. JWB + * 12-Mar-01 anne-sophie.harnois@nextream.fr + * - Variables are compatible with those already defined in + * include/net.h + * - Receive buffer descriptor ring is used to send buffers + * to the user + * - Info print about send/received/handled packet number if + * INFO_405_ENET is set + * 17-Apr-01 stefan.roese@esd-electronics.com + * - MAL reset in "eth_halt" included + * - Enet speed and duplex output now in one line + * 08-May-01 stefan.roese@esd-electronics.com + * - MAL error handling added (eth_init called again) + * 13-Nov-01 stefan.roese@esd-electronics.com + * - Set IST bit in EMAC0_MR1 reg upon 100MBit or full duplex + * 04-Jan-02 stefan.roese@esd-electronics.com + * - Wait for PHY auto negotiation to complete added + * 06-Feb-02 stefan.roese@esd-electronics.com + * - Bug fixed in waiting for auto negotiation to complete + * 26-Feb-02 stefan.roese@esd-electronics.com + * - rx and tx buffer descriptors now allocated (no fixed address + * used anymore) + * 17-Jun-02 stefan.roese@esd-electronics.com + * - MAL error debug printf 'M' removed (rx de interrupt may + * occur upon many incoming packets with only 4 rx buffers). + *-----------------------------------------------------------------------------* + * 17-Nov-03 travis.sawyer@sandburst.com + * - ported from 405gp_enet.c to utilized upto 4 EMAC ports + * in the 440GX. This port should work with the 440GP + * (2 EMACs) also + * 15-Aug-05 sr@denx.de + * - merged 405gp_enet.c and 440gx_enet.c to generic 4xx_enet.c + now handling all 4xx cpu's. + *-----------------------------------------------------------------------------*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) +#error "CONFIG_MII has to be defined!" +#endif + +#define EMAC_RESET_TIMEOUT 1000 /* 1000 ms reset timeout */ +#define PHY_AUTONEGOTIATE_TIMEOUT 5000 /* 5000 ms autonegotiate timeout */ + +/* Ethernet Transmit and Receive Buffers */ +/* AS.HARNOIS + * In the same way ENET_MAX_MTU and ENET_MAX_MTU_ALIGNED are set from + * PKTSIZE and PKTSIZE_ALIGN (include/net.h) + */ +#define ENET_MAX_MTU PKTSIZE +#define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN + +/*-----------------------------------------------------------------------------+ + * Defines for MAL/EMAC interrupt conditions as reported in the UIC (Universal + * Interrupt Controller). + *-----------------------------------------------------------------------------*/ +#define ETH_IRQ_NUM(dev) (VECNUM_ETH0 + ((dev) * VECNUM_ETH1_OFFS)) + +#if defined(CONFIG_HAS_ETH3) +#if !defined(CONFIG_440GX) +#define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)) || \ + UIC_MASK(ETH_IRQ_NUM(2)) || UIC_MASK(ETH_IRQ_NUM(3))) +#else +/* Unfortunately 440GX spreads EMAC interrupts on multiple UIC's */ +#define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1))) +#define UIC_ETHxB (UIC_MASK(ETH_IRQ_NUM(2)) || UIC_MASK(ETH_IRQ_NUM(3))) +#endif /* !defined(CONFIG_440GX) */ +#elif defined(CONFIG_HAS_ETH2) +#define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)) || \ + UIC_MASK(ETH_IRQ_NUM(2))) +#elif defined(CONFIG_HAS_ETH1) +#define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1))) +#else +#define UIC_ETHx UIC_MASK(ETH_IRQ_NUM(0)) +#endif + +/* + * Define a default version for UIC_ETHxB for non 440GX so that we can + * use common code for all 4xx variants + */ +#if !defined(UIC_ETHxB) +#define UIC_ETHxB 0 +#endif + +#define UIC_MAL_SERR UIC_MASK(VECNUM_MAL_SERR) +#define UIC_MAL_TXDE UIC_MASK(VECNUM_MAL_TXDE) +#define UIC_MAL_RXDE UIC_MASK(VECNUM_MAL_RXDE) +#define UIC_MAL_TXEOB UIC_MASK(VECNUM_MAL_TXEOB) +#define UIC_MAL_RXEOB UIC_MASK(VECNUM_MAL_RXEOB) + +#define MAL_UIC_ERR (UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE) +#define MAL_UIC_DEF (UIC_MAL_RXEOB | MAL_UIC_ERR) + +/* + * We have 3 different interrupt types: + * - MAL interrupts indicating successful transfer + * - MAL error interrupts indicating MAL related errors + * - EMAC interrupts indicating EMAC related errors + * + * All those interrupts can be on different UIC's, but since + * now at least all interrupts from one type are on the same + * UIC. Only exception is 440GX where the EMAC interrupts are + * spread over two UIC's! + */ +#if defined(CONFIG_440GX) +#define UIC_BASE_MAL UIC1_DCR_BASE +#define UIC_BASE_MAL_ERR UIC2_DCR_BASE +#define UIC_BASE_EMAC UIC2_DCR_BASE +#define UIC_BASE_EMAC_B UIC3_DCR_BASE +#else +#define UIC_BASE_MAL (UIC0_DCR_BASE + (UIC_NR(VECNUM_MAL_TXEOB) * 0x10)) +#define UIC_BASE_MAL_ERR (UIC0_DCR_BASE + (UIC_NR(VECNUM_MAL_SERR) * 0x10)) +#define UIC_BASE_EMAC (UIC0_DCR_BASE + (UIC_NR(ETH_IRQ_NUM(0)) * 0x10)) +#define UIC_BASE_EMAC_B (UIC0_DCR_BASE + (UIC_NR(ETH_IRQ_NUM(0)) * 0x10)) +#endif + +#undef INFO_4XX_ENET + +#define BI_PHYMODE_NONE 0 +#define BI_PHYMODE_ZMII 1 +#define BI_PHYMODE_RGMII 2 +#define BI_PHYMODE_GMII 3 +#define BI_PHYMODE_RTBI 4 +#define BI_PHYMODE_TBI 5 +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_405EX) +#define BI_PHYMODE_SMII 6 +#define BI_PHYMODE_MII 7 +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) +#define BI_PHYMODE_RMII 8 +#endif +#endif +#define BI_PHYMODE_SGMII 9 + +#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_405EX) +#define SDR0_MFR_ETH_CLK_SEL_V(n) ((0x01<<27) / (n+1)) +#endif + +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) +#define SDR0_ETH_CFG_CLK_SEL_V(n) (0x01 << (8 + n)) +#endif + +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) +#define MAL_RX_CHAN_MUL 8 /* 460EX/GT uses MAL channel 8 for EMAC1 */ +#else +#define MAL_RX_CHAN_MUL 1 +#endif + +/*--------------------------------------------------------------------+ + * Fixed PHY (PHY-less) support for Ethernet Ports. + *--------------------------------------------------------------------*/ + +/* + * Some boards do not have a PHY for each ethernet port. These ports + * are known as Fixed PHY (or PHY-less) ports. For such ports, set + * the appropriate CONFIG_PHY_ADDR equal to CONFIG_FIXED_PHY and + * then define CONFIG_SYS_FIXED_PHY_PORTS to define what the speed and + * duplex should be for these ports in the board configuration + * file. + * + * For Example: + * #define CONFIG_FIXED_PHY 0xFFFFFFFF + * + * #define CONFIG_PHY_ADDR CONFIG_FIXED_PHY + * #define CONFIG_PHY1_ADDR 1 + * #define CONFIG_PHY2_ADDR CONFIG_FIXED_PHY + * #define CONFIG_PHY3_ADDR 3 + * + * #define CONFIG_SYS_FIXED_PHY_PORT(devnum,speed,duplex) \ + * {devnum, speed, duplex}, + * + * #define CONFIG_SYS_FIXED_PHY_PORTS \ + * CONFIG_SYS_FIXED_PHY_PORT(0,1000,FULL) \ + * CONFIG_SYS_FIXED_PHY_PORT(2,100,HALF) + */ + +#ifndef CONFIG_FIXED_PHY +#define CONFIG_FIXED_PHY 0xFFFFFFFF /* Fixed PHY (PHY-less) */ +#endif + +#ifndef CONFIG_SYS_FIXED_PHY_PORTS +#define CONFIG_SYS_FIXED_PHY_PORTS /* default is an empty array */ +#endif + +struct fixed_phy_port { + unsigned int devnum; /* ethernet port */ + unsigned int speed; /* specified speed 10,100 or 1000 */ + unsigned int duplex; /* specified duplex FULL or HALF */ +}; + +static const struct fixed_phy_port fixed_phy_port[] = { + CONFIG_SYS_FIXED_PHY_PORTS /* defined in board configuration file */ +}; + +/*-----------------------------------------------------------------------------+ + * Global variables. TX and RX descriptors and buffers. + *-----------------------------------------------------------------------------*/ + +/* + * Get count of EMAC devices (doesn't have to be the max. possible number + * supported by the cpu) + * + * CONFIG_BOARD_EMAC_COUNT added so now a "dynamic" way to configure the + * EMAC count is possible. As it is needed for the Kilauea/Haleakala + * 405EX/405EXr eval board, using the same binary. + */ +#if defined(CONFIG_BOARD_EMAC_COUNT) +#define LAST_EMAC_NUM board_emac_count() +#else /* CONFIG_BOARD_EMAC_COUNT */ +#if defined(CONFIG_HAS_ETH3) +#define LAST_EMAC_NUM 4 +#elif defined(CONFIG_HAS_ETH2) +#define LAST_EMAC_NUM 3 +#elif defined(CONFIG_HAS_ETH1) +#define LAST_EMAC_NUM 2 +#else +#define LAST_EMAC_NUM 1 +#endif +#endif /* CONFIG_BOARD_EMAC_COUNT */ + +/* normal boards start with EMAC0 */ +#if !defined(CONFIG_EMAC_NR_START) +#define CONFIG_EMAC_NR_START 0 +#endif + +#define MAL_RX_DESC_SIZE 2048 +#define MAL_TX_DESC_SIZE 2048 +#define MAL_ALLOC_SIZE (MAL_TX_DESC_SIZE + MAL_RX_DESC_SIZE) + +/*-----------------------------------------------------------------------------+ + * Prototypes and externals. + *-----------------------------------------------------------------------------*/ +static void enet_rcv (struct eth_device *dev, unsigned long malisr); + +int enetInt (struct eth_device *dev); +static void mal_err (struct eth_device *dev, unsigned long isr, + unsigned long uic, unsigned long maldef, + unsigned long mal_errr); +static void emac_err (struct eth_device *dev, unsigned long isr); + +extern int phy_setup_aneg (char *devname, unsigned char addr); +extern int emac4xx_miiphy_read (const char *devname, unsigned char addr, + unsigned char reg, unsigned short *value); +extern int emac4xx_miiphy_write (const char *devname, unsigned char addr, + unsigned char reg, unsigned short value); + +int board_emac_count(void); + +static void emac_loopback_enable(EMAC_4XX_HW_PST hw_p) +{ +#if defined(CONFIG_440SPE) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_405EX) + u32 val; + + mfsdr(SDR0_MFR, val); + val |= SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum); + mtsdr(SDR0_MFR, val); +#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) + u32 val; + + mfsdr(SDR0_ETH_CFG, val); + val |= SDR0_ETH_CFG_CLK_SEL_V(hw_p->devnum); + mtsdr(SDR0_ETH_CFG, val); +#endif +} + +static void emac_loopback_disable(EMAC_4XX_HW_PST hw_p) +{ +#if defined(CONFIG_440SPE) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_405EX) + u32 val; + + mfsdr(SDR0_MFR, val); + val &= ~SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum); + mtsdr(SDR0_MFR, val); +#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) + u32 val; + + mfsdr(SDR0_ETH_CFG, val); + val &= ~SDR0_ETH_CFG_CLK_SEL_V(hw_p->devnum); + mtsdr(SDR0_ETH_CFG, val); +#endif +} + +/*-----------------------------------------------------------------------------+ +| ppc_4xx_eth_halt +| Disable MAL channel, and EMACn ++-----------------------------------------------------------------------------*/ +static void ppc_4xx_eth_halt (struct eth_device *dev) +{ + EMAC_4XX_HW_PST hw_p = dev->priv; + u32 val = 10000; + + out_be32((void *)EMAC0_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */ + + /* 1st reset MAL channel */ + /* Note: writing a 0 to a channel has no effect */ +#if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR) + mtdcr (MAL0_TXCARR, (MAL_CR_MMSR >> (hw_p->devnum * 2))); +#else + mtdcr (MAL0_TXCARR, (MAL_CR_MMSR >> hw_p->devnum)); +#endif + mtdcr (MAL0_RXCARR, (MAL_CR_MMSR >> hw_p->devnum)); + + /* wait for reset */ + while (mfdcr (MAL0_RXCASR) & (MAL_CR_MMSR >> hw_p->devnum)) { + udelay (1000); /* Delay 1 MS so as not to hammer the register */ + val--; + if (val == 0) + break; + } + + /* provide clocks for EMAC internal loopback */ + emac_loopback_enable(hw_p); + + /* EMAC RESET */ + out_be32((void *)EMAC0_MR0 + hw_p->hw_addr, EMAC_MR0_SRST); + + /* remove clocks for EMAC internal loopback */ + emac_loopback_disable(hw_p); + +#ifndef CONFIG_NETCONSOLE + hw_p->print_speed = 1; /* print speed message again next time */ +#endif + +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) + /* don't bypass the TAHOE0/TAHOE1 cores for Linux */ + mfsdr(SDR0_ETH_CFG, val); + val &= ~(SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS); + mtsdr(SDR0_ETH_CFG, val); +#endif + + return; +} + +#if defined (CONFIG_440GX) +int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) +{ + unsigned long pfc1; + unsigned long zmiifer; + unsigned long rmiifer; + + mfsdr(SDR0_PFC1, pfc1); + pfc1 = SDR0_PFC1_EPS_DECODE(pfc1); + + zmiifer = 0; + rmiifer = 0; + + switch (pfc1) { + case 1: + zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0); + zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1); + zmiifer |= ZMII_FER_RMII << ZMII_FER_V(2); + zmiifer |= ZMII_FER_RMII << ZMII_FER_V(3); + bis->bi_phymode[0] = BI_PHYMODE_ZMII; + bis->bi_phymode[1] = BI_PHYMODE_ZMII; + bis->bi_phymode[2] = BI_PHYMODE_ZMII; + bis->bi_phymode[3] = BI_PHYMODE_ZMII; + break; + case 2: + zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0); + zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1); + zmiifer |= ZMII_FER_SMII << ZMII_FER_V(2); + zmiifer |= ZMII_FER_SMII << ZMII_FER_V(3); + bis->bi_phymode[0] = BI_PHYMODE_ZMII; + bis->bi_phymode[1] = BI_PHYMODE_ZMII; + bis->bi_phymode[2] = BI_PHYMODE_ZMII; + bis->bi_phymode[3] = BI_PHYMODE_ZMII; + break; + case 3: + zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0); + rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2); + bis->bi_phymode[0] = BI_PHYMODE_ZMII; + bis->bi_phymode[1] = BI_PHYMODE_NONE; + bis->bi_phymode[2] = BI_PHYMODE_RGMII; + bis->bi_phymode[3] = BI_PHYMODE_NONE; + break; + case 4: + zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0); + zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1); + rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (2); + rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (3); + bis->bi_phymode[0] = BI_PHYMODE_ZMII; + bis->bi_phymode[1] = BI_PHYMODE_ZMII; + bis->bi_phymode[2] = BI_PHYMODE_RGMII; + bis->bi_phymode[3] = BI_PHYMODE_RGMII; + break; + case 5: + zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0); + zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1); + zmiifer |= ZMII_FER_SMII << ZMII_FER_V (2); + rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3); + bis->bi_phymode[0] = BI_PHYMODE_ZMII; + bis->bi_phymode[1] = BI_PHYMODE_ZMII; + bis->bi_phymode[2] = BI_PHYMODE_ZMII; + bis->bi_phymode[3] = BI_PHYMODE_RGMII; + break; + case 6: + zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0); + zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1); + rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2); + bis->bi_phymode[0] = BI_PHYMODE_ZMII; + bis->bi_phymode[1] = BI_PHYMODE_ZMII; + bis->bi_phymode[2] = BI_PHYMODE_RGMII; + break; + case 0: + default: + zmiifer = ZMII_FER_MII << ZMII_FER_V(devnum); + rmiifer = 0x0; + bis->bi_phymode[0] = BI_PHYMODE_ZMII; + bis->bi_phymode[1] = BI_PHYMODE_ZMII; + bis->bi_phymode[2] = BI_PHYMODE_ZMII; + bis->bi_phymode[3] = BI_PHYMODE_ZMII; + break; + } + + /* Ensure we setup mdio for this devnum and ONLY this devnum */ + zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum); + + out_be32((void *)ZMII0_FER, zmiifer); + out_be32((void *)RGMII_FER, rmiifer); + + return ((int)pfc1); +} +#endif /* CONFIG_440_GX */ + +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) +int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) +{ + unsigned long zmiifer=0x0; + unsigned long pfc1; + + mfsdr(SDR0_PFC1, pfc1); + pfc1 &= SDR0_PFC1_SELECT_MASK; + + switch (pfc1) { + case SDR0_PFC1_SELECT_CONFIG_2: + /* 1 x GMII port */ + out_be32((void *)ZMII0_FER, 0x00); + out_be32((void *)RGMII_FER, 0x00000037); + bis->bi_phymode[0] = BI_PHYMODE_GMII; + bis->bi_phymode[1] = BI_PHYMODE_NONE; + break; + case SDR0_PFC1_SELECT_CONFIG_4: + /* 2 x RGMII ports */ + out_be32((void *)ZMII0_FER, 0x00); + out_be32((void *)RGMII_FER, 0x00000055); + bis->bi_phymode[0] = BI_PHYMODE_RGMII; + bis->bi_phymode[1] = BI_PHYMODE_RGMII; + break; + case SDR0_PFC1_SELECT_CONFIG_6: + /* 2 x SMII ports */ + out_be32((void *)ZMII0_FER, + ((ZMII_FER_SMII) << ZMII_FER_V(0)) | + ((ZMII_FER_SMII) << ZMII_FER_V(1))); + out_be32((void *)RGMII_FER, 0x00000000); + bis->bi_phymode[0] = BI_PHYMODE_SMII; + bis->bi_phymode[1] = BI_PHYMODE_SMII; + break; + case SDR0_PFC1_SELECT_CONFIG_1_2: + /* only 1 x MII supported */ + out_be32((void *)ZMII0_FER, (ZMII_FER_MII) << ZMII_FER_V(0)); + out_be32((void *)RGMII_FER, 0x00000000); + bis->bi_phymode[0] = BI_PHYMODE_MII; + bis->bi_phymode[1] = BI_PHYMODE_NONE; + break; + default: + break; + } + + /* Ensure we setup mdio for this devnum and ONLY this devnum */ + zmiifer = in_be32((void *)ZMII0_FER); + zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum); + out_be32((void *)ZMII0_FER, zmiifer); + + return ((int)0x0); +} +#endif /* CONFIG_440EPX */ + +#if defined(CONFIG_405EX) +int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) +{ + u32 rgmiifer = 0; + + /* + * The 405EX(r)'s RGMII bridge can operate in one of several + * modes, only one of which (2 x RGMII) allows the + * simultaneous use of both EMACs on the 405EX. + */ + + switch (CONFIG_EMAC_PHY_MODE) { + + case EMAC_PHY_MODE_NONE: + /* No ports */ + rgmiifer |= RGMII_FER_DIS << 0; + rgmiifer |= RGMII_FER_DIS << 4; + out_be32((void *)RGMII_FER, rgmiifer); + bis->bi_phymode[0] = BI_PHYMODE_NONE; + bis->bi_phymode[1] = BI_PHYMODE_NONE; + break; + case EMAC_PHY_MODE_NONE_RGMII: + /* 1 x RGMII port on channel 0 */ + rgmiifer |= RGMII_FER_RGMII << 0; + rgmiifer |= RGMII_FER_DIS << 4; + out_be32((void *)RGMII_FER, rgmiifer); + bis->bi_phymode[0] = BI_PHYMODE_RGMII; + bis->bi_phymode[1] = BI_PHYMODE_NONE; + break; + case EMAC_PHY_MODE_RGMII_NONE: + /* 1 x RGMII port on channel 1 */ + rgmiifer |= RGMII_FER_DIS << 0; + rgmiifer |= RGMII_FER_RGMII << 4; + out_be32((void *)RGMII_FER, rgmiifer); + bis->bi_phymode[0] = BI_PHYMODE_NONE; + bis->bi_phymode[1] = BI_PHYMODE_RGMII; + break; + case EMAC_PHY_MODE_RGMII_RGMII: + /* 2 x RGMII ports */ + rgmiifer |= RGMII_FER_RGMII << 0; + rgmiifer |= RGMII_FER_RGMII << 4; + out_be32((void *)RGMII_FER, rgmiifer); + bis->bi_phymode[0] = BI_PHYMODE_RGMII; + bis->bi_phymode[1] = BI_PHYMODE_RGMII; + break; + case EMAC_PHY_MODE_NONE_GMII: + /* 1 x GMII port on channel 0 */ + rgmiifer |= RGMII_FER_GMII << 0; + rgmiifer |= RGMII_FER_DIS << 4; + out_be32((void *)RGMII_FER, rgmiifer); + bis->bi_phymode[0] = BI_PHYMODE_GMII; + bis->bi_phymode[1] = BI_PHYMODE_NONE; + break; + case EMAC_PHY_MODE_NONE_MII: + /* 1 x MII port on channel 0 */ + rgmiifer |= RGMII_FER_MII << 0; + rgmiifer |= RGMII_FER_DIS << 4; + out_be32((void *)RGMII_FER, rgmiifer); + bis->bi_phymode[0] = BI_PHYMODE_MII; + bis->bi_phymode[1] = BI_PHYMODE_NONE; + break; + case EMAC_PHY_MODE_GMII_NONE: + /* 1 x GMII port on channel 1 */ + rgmiifer |= RGMII_FER_DIS << 0; + rgmiifer |= RGMII_FER_GMII << 4; + out_be32((void *)RGMII_FER, rgmiifer); + bis->bi_phymode[0] = BI_PHYMODE_NONE; + bis->bi_phymode[1] = BI_PHYMODE_GMII; + break; + case EMAC_PHY_MODE_MII_NONE: + /* 1 x MII port on channel 1 */ + rgmiifer |= RGMII_FER_DIS << 0; + rgmiifer |= RGMII_FER_MII << 4; + out_be32((void *)RGMII_FER, rgmiifer); + bis->bi_phymode[0] = BI_PHYMODE_NONE; + bis->bi_phymode[1] = BI_PHYMODE_MII; + break; + default: + break; + } + + /* Ensure we setup mdio for this devnum and ONLY this devnum */ + rgmiifer = in_be32((void *)RGMII_FER); + rgmiifer |= (1 << (19-devnum)); + out_be32((void *)RGMII_FER, rgmiifer); + + return ((int)0x0); +} +#endif /* CONFIG_405EX */ + +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) +int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) +{ + u32 eth_cfg; + u32 zmiifer; /* ZMII0_FER reg. */ + u32 rmiifer; /* RGMII0_FER reg. Bridge 0 */ + u32 rmiifer1; /* RGMII0_FER reg. Bridge 1 */ + int mode; + + zmiifer = 0; + rmiifer = 0; + rmiifer1 = 0; + +#if defined(CONFIG_460EX) + mode = 9; + mfsdr(SDR0_ETH_CFG, eth_cfg); + if (((eth_cfg & SDR0_ETH_CFG_SGMII0_ENABLE) > 0) && + ((eth_cfg & SDR0_ETH_CFG_SGMII1_ENABLE) > 0)) + mode = 11; /* config SGMII */ +#else + mode = 10; + mfsdr(SDR0_ETH_CFG, eth_cfg); + if (((eth_cfg & SDR0_ETH_CFG_SGMII0_ENABLE) > 0) && + ((eth_cfg & SDR0_ETH_CFG_SGMII1_ENABLE) > 0) && + ((eth_cfg & SDR0_ETH_CFG_SGMII2_ENABLE) > 0)) + mode = 12; /* config SGMII */ +#endif + + /* TODO: + * NOTE: 460GT has 2 RGMII bridge cores: + * emac0 ------ RGMII0_BASE + * | + * emac1 -----+ + * + * emac2 ------ RGMII1_BASE + * | + * emac3 -----+ + * + * 460EX has 1 RGMII bridge core: + * and RGMII1_BASE is disabled + * emac0 ------ RGMII0_BASE + * | + * emac1 -----+ + */ + + /* + * Right now only 2*RGMII is supported. Please extend when needed. + * sr - 2008-02-19 + * Add SGMII support. + * vg - 2008-07-28 + */ + switch (mode) { + case 1: + /* 1 MII - 460EX */ + /* GMC0 EMAC4_0, ZMII Bridge */ + zmiifer |= ZMII_FER_MII << ZMII_FER_V(0); + bis->bi_phymode[0] = BI_PHYMODE_MII; + bis->bi_phymode[1] = BI_PHYMODE_NONE; + bis->bi_phymode[2] = BI_PHYMODE_NONE; + bis->bi_phymode[3] = BI_PHYMODE_NONE; + break; + case 2: + /* 2 MII - 460GT */ + /* GMC0 EMAC4_0, GMC1 EMAC4_2, ZMII Bridge */ + zmiifer |= ZMII_FER_MII << ZMII_FER_V(0); + zmiifer |= ZMII_FER_MII << ZMII_FER_V(2); + bis->bi_phymode[0] = BI_PHYMODE_MII; + bis->bi_phymode[1] = BI_PHYMODE_NONE; + bis->bi_phymode[2] = BI_PHYMODE_MII; + bis->bi_phymode[3] = BI_PHYMODE_NONE; + break; + case 3: + /* 2 RMII - 460EX */ + /* GMC0 EMAC4_0, GMC0 EMAC4_1, ZMII Bridge */ + zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0); + zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1); + bis->bi_phymode[0] = BI_PHYMODE_RMII; + bis->bi_phymode[1] = BI_PHYMODE_RMII; + bis->bi_phymode[2] = BI_PHYMODE_NONE; + bis->bi_phymode[3] = BI_PHYMODE_NONE; + break; + case 4: + /* 4 RMII - 460GT */ + /* GMC0 EMAC4_0, GMC0 EMAC4_1, GMC1 EMAC4_2, GMC1, EMAC4_3 */ + /* ZMII Bridge */ + zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0); + zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1); + zmiifer |= ZMII_FER_RMII << ZMII_FER_V(2); + zmiifer |= ZMII_FER_RMII << ZMII_FER_V(3); + bis->bi_phymode[0] = BI_PHYMODE_RMII; + bis->bi_phymode[1] = BI_PHYMODE_RMII; + bis->bi_phymode[2] = BI_PHYMODE_RMII; + bis->bi_phymode[3] = BI_PHYMODE_RMII; + break; + case 5: + /* 2 SMII - 460EX */ + /* GMC0 EMAC4_0, GMC0 EMAC4_1, ZMII Bridge */ + zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0); + zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1); + bis->bi_phymode[0] = BI_PHYMODE_SMII; + bis->bi_phymode[1] = BI_PHYMODE_SMII; + bis->bi_phymode[2] = BI_PHYMODE_NONE; + bis->bi_phymode[3] = BI_PHYMODE_NONE; + break; + case 6: + /* 4 SMII - 460GT */ + /* GMC0 EMAC4_0, GMC0 EMAC4_1, GMC0 EMAC4_3, GMC0 EMAC4_3 */ + /* ZMII Bridge */ + zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0); + zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1); + zmiifer |= ZMII_FER_SMII << ZMII_FER_V(2); + zmiifer |= ZMII_FER_SMII << ZMII_FER_V(3); + bis->bi_phymode[0] = BI_PHYMODE_SMII; + bis->bi_phymode[1] = BI_PHYMODE_SMII; + bis->bi_phymode[2] = BI_PHYMODE_SMII; + bis->bi_phymode[3] = BI_PHYMODE_SMII; + break; + case 7: + /* This is the default mode that we want for board bringup - Maple */ + /* 1 GMII - 460EX */ + /* GMC0 EMAC4_0, RGMII Bridge 0 */ + rmiifer |= RGMII_FER_MDIO(0); + + if (devnum == 0) { + rmiifer |= RGMII_FER_GMII << RGMII_FER_V(2); /* CH0CFG - EMAC0 */ + bis->bi_phymode[0] = BI_PHYMODE_GMII; + bis->bi_phymode[1] = BI_PHYMODE_NONE; + bis->bi_phymode[2] = BI_PHYMODE_NONE; + bis->bi_phymode[3] = BI_PHYMODE_NONE; + } else { + rmiifer |= RGMII_FER_GMII << RGMII_FER_V(3); /* CH1CFG - EMAC1 */ + bis->bi_phymode[0] = BI_PHYMODE_NONE; + bis->bi_phymode[1] = BI_PHYMODE_GMII; + bis->bi_phymode[2] = BI_PHYMODE_NONE; + bis->bi_phymode[3] = BI_PHYMODE_NONE; + } + break; + case 8: + /* 2 GMII - 460GT */ + /* GMC0 EMAC4_0, RGMII Bridge 0 */ + /* GMC1 EMAC4_2, RGMII Bridge 1 */ + rmiifer |= RGMII_FER_GMII << RGMII_FER_V(2); /* CH0CFG - EMAC0 */ + rmiifer1 |= RGMII_FER_GMII << RGMII_FER_V(2); /* CH0CFG - EMAC2 */ + rmiifer |= RGMII_FER_MDIO(0); /* enable MDIO - EMAC0 */ + rmiifer1 |= RGMII_FER_MDIO(0); /* enable MDIO - EMAC2 */ + + bis->bi_phymode[0] = BI_PHYMODE_GMII; + bis->bi_phymode[1] = BI_PHYMODE_NONE; + bis->bi_phymode[2] = BI_PHYMODE_GMII; + bis->bi_phymode[3] = BI_PHYMODE_NONE; + break; + case 9: + /* 2 RGMII - 460EX */ + /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */ + rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2); + rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3); + rmiifer |= RGMII_FER_MDIO(0); /* enable MDIO - EMAC0 */ + + bis->bi_phymode[0] = BI_PHYMODE_RGMII; + bis->bi_phymode[1] = BI_PHYMODE_RGMII; + bis->bi_phymode[2] = BI_PHYMODE_NONE; + bis->bi_phymode[3] = BI_PHYMODE_NONE; + break; + case 10: + /* 4 RGMII - 460GT */ + /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */ + /* GMC1 EMAC4_2, GMC1 EMAC4_3, RGMII Bridge 1 */ + rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2); + rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3); + rmiifer1 |= RGMII_FER_RGMII << RGMII_FER_V(2); + rmiifer1 |= RGMII_FER_RGMII << RGMII_FER_V(3); + bis->bi_phymode[0] = BI_PHYMODE_RGMII; + bis->bi_phymode[1] = BI_PHYMODE_RGMII; + bis->bi_phymode[2] = BI_PHYMODE_RGMII; + bis->bi_phymode[3] = BI_PHYMODE_RGMII; + break; + case 11: + /* 2 SGMII - 460EX */ + bis->bi_phymode[0] = BI_PHYMODE_SGMII; + bis->bi_phymode[1] = BI_PHYMODE_SGMII; + bis->bi_phymode[2] = BI_PHYMODE_NONE; + bis->bi_phymode[3] = BI_PHYMODE_NONE; + break; + case 12: + /* 3 SGMII - 460GT */ + bis->bi_phymode[0] = BI_PHYMODE_SGMII; + bis->bi_phymode[1] = BI_PHYMODE_SGMII; + bis->bi_phymode[2] = BI_PHYMODE_SGMII; + bis->bi_phymode[3] = BI_PHYMODE_NONE; + break; + default: + break; + } + + /* Set EMAC for MDIO */ + mfsdr(SDR0_ETH_CFG, eth_cfg); + eth_cfg |= SDR0_ETH_CFG_MDIO_SEL_EMAC0; + mtsdr(SDR0_ETH_CFG, eth_cfg); + + out_be32((void *)RGMII_FER, rmiifer); +#if defined(CONFIG_460GT) + out_be32((void *)RGMII_FER + RGMII1_BASE_OFFSET, rmiifer1); +#endif + + /* bypass the TAHOE0/TAHOE1 cores for U-Boot */ + mfsdr(SDR0_ETH_CFG, eth_cfg); + eth_cfg |= (SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS); + mtsdr(SDR0_ETH_CFG, eth_cfg); + + return 0; +} +#endif /* CONFIG_460EX || CONFIG_460GT */ + +static inline void *malloc_aligned(u32 size, u32 align) +{ + return (void *)(((u32)malloc(size + align) + align - 1) & + ~(align - 1)); +} + +static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) +{ + int i; + unsigned long reg = 0; + unsigned long msr; + unsigned long speed; + unsigned long duplex; + unsigned long failsafe; + unsigned mode_reg; + unsigned short devnum; + unsigned short reg_short; +#if defined(CONFIG_440GX) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_405EX) + u32 opbfreq; + sys_info_t sysinfo; +#if defined(CONFIG_440GX) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_405EX) + __maybe_unused int ethgroup = -1; +#endif +#endif + u32 bd_cached; + u32 bd_uncached = 0; +#ifdef CONFIG_4xx_DCACHE + static u32 last_used_ea = 0; +#endif +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_405EX) + int rgmii_channel; +#endif + + EMAC_4XX_HW_PST hw_p = dev->priv; + + /* before doing anything, figure out if we have a MAC address */ + /* if not, bail */ + if (memcmp (dev->enetaddr, "\0\0\0\0\0\0", 6) == 0) { + printf("ERROR: ethaddr not set!\n"); + return -1; + } + +#if defined(CONFIG_440GX) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_405EX) + /* Need to get the OPB frequency so we can access the PHY */ + get_sys_info (&sysinfo); +#endif + + msr = mfmsr (); + mtmsr (msr & ~(MSR_EE)); /* disable interrupts */ + + devnum = hw_p->devnum; + +#ifdef INFO_4XX_ENET + /* AS.HARNOIS + * We should have : + * hw_p->stats.pkts_handled <= hw_p->stats.pkts_rx <= hw_p->stats.pkts_handled+PKTBUFSRX + * In the most cases hw_p->stats.pkts_handled = hw_p->stats.pkts_rx, but it + * is possible that new packets (without relationship with + * current transfer) have got the time to arrived before + * netloop calls eth_halt + */ + printf ("About preceeding transfer (eth%d):\n" + "- Sent packet number %d\n" + "- Received packet number %d\n" + "- Handled packet number %d\n", + hw_p->devnum, + hw_p->stats.pkts_tx, + hw_p->stats.pkts_rx, hw_p->stats.pkts_handled); + + hw_p->stats.pkts_tx = 0; + hw_p->stats.pkts_rx = 0; + hw_p->stats.pkts_handled = 0; + hw_p->print_speed = 1; /* print speed message again next time */ +#endif + + hw_p->tx_err_index = 0; /* Transmit Error Index for tx_err_log */ + hw_p->rx_err_index = 0; /* Receive Error Index for rx_err_log */ + + hw_p->rx_slot = 0; /* MAL Receive Slot */ + hw_p->rx_i_index = 0; /* Receive Interrupt Queue Index */ + hw_p->rx_u_index = 0; /* Receive User Queue Index */ + + hw_p->tx_slot = 0; /* MAL Transmit Slot */ + hw_p->tx_i_index = 0; /* Transmit Interrupt Queue Index */ + hw_p->tx_u_index = 0; /* Transmit User Queue Index */ + +#if defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) + /* set RMII mode */ + /* NOTE: 440GX spec states that mode is mutually exclusive */ + /* NOTE: Therefore, disable all other EMACS, since we handle */ + /* NOTE: only one emac at a time */ + reg = 0; + out_be32((void *)ZMII0_FER, 0); + udelay (100); + +#if defined(CONFIG_440GP) || defined(CONFIG_440EP) || defined(CONFIG_440GR) + out_be32((void *)ZMII0_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum)); +#elif defined(CONFIG_440GX) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) + ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis); +#endif + + out_be32((void *)ZMII0_SSR, ZMII0_SSR_SP << ZMII0_SSR_V(devnum)); +#endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */ +#if defined(CONFIG_405EX) + ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis); +#endif + + sync(); + + /* provide clocks for EMAC internal loopback */ + emac_loopback_enable(hw_p); + + /* EMAC RESET */ + out_be32((void *)EMAC0_MR0 + hw_p->hw_addr, EMAC_MR0_SRST); + + /* remove clocks for EMAC internal loopback */ + emac_loopback_disable(hw_p); + + failsafe = 1000; + while ((in_be32((void *)EMAC0_MR0 + hw_p->hw_addr) & (EMAC_MR0_SRST)) && failsafe) { + udelay (1000); + failsafe--; + } + if (failsafe <= 0) + printf("\nProblem resetting EMAC!\n"); + +#if defined(CONFIG_440GX) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_405EX) + /* Whack the M1 register */ + mode_reg = 0x0; + mode_reg &= ~0x00000038; + opbfreq = sysinfo.freqOPB / 1000000; + if (opbfreq <= 50); + else if (opbfreq <= 66) + mode_reg |= EMAC_MR1_OBCI_66; + else if (opbfreq <= 83) + mode_reg |= EMAC_MR1_OBCI_83; + else if (opbfreq <= 100) + mode_reg |= EMAC_MR1_OBCI_100; + else + mode_reg |= EMAC_MR1_OBCI_GT100; + + out_be32((void *)EMAC0_MR1 + hw_p->hw_addr, mode_reg); +#endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */ + +#if defined(CONFIG_GPCS_PHY_ADDR) || defined(CONFIG_GPCS_PHY1_ADDR) || \ + defined(CONFIG_GPCS_PHY2_ADDR) || defined(CONFIG_GPCS_PHY3_ADDR) + if (bis->bi_phymode[devnum] == BI_PHYMODE_SGMII) { + /* + * In SGMII mode, GPCS access is needed for + * communication with the internal SGMII SerDes. + */ + switch (devnum) { +#if defined(CONFIG_GPCS_PHY_ADDR) + case 0: + reg = CONFIG_GPCS_PHY_ADDR; + break; +#endif +#if defined(CONFIG_GPCS_PHY1_ADDR) + case 1: + reg = CONFIG_GPCS_PHY1_ADDR; + break; +#endif +#if defined(CONFIG_GPCS_PHY2_ADDR) + case 2: + reg = CONFIG_GPCS_PHY2_ADDR; + break; +#endif +#if defined(CONFIG_GPCS_PHY3_ADDR) + case 3: + reg = CONFIG_GPCS_PHY3_ADDR; + break; +#endif + } + + mode_reg = in_be32((void *)EMAC0_MR1 + hw_p->hw_addr); + mode_reg |= EMAC_MR1_MF_1000GPCS | EMAC_MR1_IPPA_SET(reg); + out_be32((void *)EMAC0_MR1 + hw_p->hw_addr, mode_reg); + + /* Configure GPCS interface to recommended setting for SGMII */ + miiphy_reset(dev->name, reg); + miiphy_write(dev->name, reg, 0x04, 0x8120); /* AsymPause, FDX */ + miiphy_write(dev->name, reg, 0x07, 0x2801); /* msg_pg, toggle */ + miiphy_write(dev->name, reg, 0x00, 0x0140); /* 1Gbps, FDX */ + } +#endif /* defined(CONFIG_GPCS_PHY_ADDR) */ + + /* wait for PHY to complete auto negotiation */ + reg_short = 0; + switch (devnum) { + case 0: + reg = CONFIG_PHY_ADDR; + break; +#if defined (CONFIG_PHY1_ADDR) + case 1: + reg = CONFIG_PHY1_ADDR; + break; +#endif +#if defined (CONFIG_PHY2_ADDR) + case 2: + reg = CONFIG_PHY2_ADDR; + break; +#endif +#if defined (CONFIG_PHY3_ADDR) + case 3: + reg = CONFIG_PHY3_ADDR; + break; +#endif + default: + reg = CONFIG_PHY_ADDR; + break; + } + + bis->bi_phynum[devnum] = reg; + + if (reg == CONFIG_FIXED_PHY) + goto get_speed; + +#if defined(CONFIG_PHY_RESET) + /* + * Reset the phy, only if its the first time through + * otherwise, just check the speeds & feeds + */ + if (hw_p->first_init == 0) { +#if defined(CONFIG_M88E1111_PHY) + miiphy_write (dev->name, reg, 0x14, 0x0ce3); + miiphy_write (dev->name, reg, 0x18, 0x4101); + miiphy_write (dev->name, reg, 0x09, 0x0e00); + miiphy_write (dev->name, reg, 0x04, 0x01e1); +#if defined(CONFIG_M88E1111_DISABLE_FIBER) + miiphy_read(dev->name, reg, 0x1b, ®_short); + reg_short |= 0x8000; + miiphy_write(dev->name, reg, 0x1b, reg_short); +#endif +#endif +#if defined(CONFIG_M88E1112_PHY) + if (bis->bi_phymode[devnum] == BI_PHYMODE_SGMII) { + /* + * Marvell 88E1112 PHY needs to have the SGMII MAC + * interace (page 2) properly configured to + * communicate with the 460EX/GT GPCS interface. + */ + + /* Set access to Page 2 */ + miiphy_write(dev->name, reg, 0x16, 0x0002); + + miiphy_write(dev->name, reg, 0x00, 0x0040); /* 1Gbps */ + miiphy_read(dev->name, reg, 0x1a, ®_short); + reg_short |= 0x8000; /* bypass Auto-Negotiation */ + miiphy_write(dev->name, reg, 0x1a, reg_short); + miiphy_reset(dev->name, reg); /* reset MAC interface */ + + /* Reset access to Page 0 */ + miiphy_write(dev->name, reg, 0x16, 0x0000); + } +#endif /* defined(CONFIG_M88E1112_PHY) */ + miiphy_reset (dev->name, reg); + +#if defined(CONFIG_440GX) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_405EX) + +#if defined(CONFIG_CIS8201_PHY) + /* + * Cicada 8201 PHY needs to have an extended register whacked + * for RGMII mode. + */ + if (((devnum == 2) || (devnum == 3)) && (4 == ethgroup)) { +#if defined(CONFIG_CIS8201_SHORT_ETCH) + miiphy_write (dev->name, reg, 23, 0x1300); +#else + miiphy_write (dev->name, reg, 23, 0x1000); +#endif + /* + * Vitesse VSC8201/Cicada CIS8201 errata: + * Interoperability problem with Intel 82547EI phys + * This work around (provided by Vitesse) changes + * the default timer convergence from 8ms to 12ms + */ + miiphy_write (dev->name, reg, 0x1f, 0x2a30); + miiphy_write (dev->name, reg, 0x08, 0x0200); + miiphy_write (dev->name, reg, 0x1f, 0x52b5); + miiphy_write (dev->name, reg, 0x02, 0x0004); + miiphy_write (dev->name, reg, 0x01, 0x0671); + miiphy_write (dev->name, reg, 0x00, 0x8fae); + miiphy_write (dev->name, reg, 0x1f, 0x2a30); + miiphy_write (dev->name, reg, 0x08, 0x0000); + miiphy_write (dev->name, reg, 0x1f, 0x0000); + /* end Vitesse/Cicada errata */ + } +#endif /* defined(CONFIG_CIS8201_PHY) */ + +#if defined(CONFIG_ET1011C_PHY) + /* + * Agere ET1011c PHY needs to have an extended register whacked + * for RGMII mode. + */ + if (((devnum == 2) || (devnum ==3)) && (4 == ethgroup)) { + miiphy_read (dev->name, reg, 0x16, ®_short); + reg_short &= ~(0x7); + reg_short |= 0x6; /* RGMII DLL Delay*/ + miiphy_write (dev->name, reg, 0x16, reg_short); + + miiphy_read (dev->name, reg, 0x17, ®_short); + reg_short &= ~(0x40); + miiphy_write (dev->name, reg, 0x17, reg_short); + + miiphy_write(dev->name, reg, 0x1c, 0x74f0); + } +#endif /* defined(CONFIG_ET1011C_PHY) */ + +#endif /* defined(CONFIG_440GX) ... */ + /* Start/Restart autonegotiation */ + phy_setup_aneg (dev->name, reg); + udelay (1000); + } +#endif /* defined(CONFIG_PHY_RESET) */ + + miiphy_read (dev->name, reg, MII_BMSR, ®_short); + + /* + * Wait if PHY is capable of autonegotiation and autonegotiation is not complete + */ + if ((reg_short & BMSR_ANEGCAPABLE) + && !(reg_short & BMSR_ANEGCOMPLETE)) { + puts ("Waiting for PHY auto negotiation to complete"); + i = 0; + while (!(reg_short & BMSR_ANEGCOMPLETE)) { + /* + * Timeout reached ? + */ + if (i > PHY_AUTONEGOTIATE_TIMEOUT) { + puts (" TIMEOUT !\n"); + break; + } + + if ((i++ % 1000) == 0) { + putc ('.'); + } + udelay (1000); /* 1 ms */ + miiphy_read (dev->name, reg, MII_BMSR, ®_short); + } + puts (" done\n"); + udelay (500000); /* another 500 ms (results in faster booting) */ + } + +get_speed: + if (reg == CONFIG_FIXED_PHY) { + for (i = 0; i < ARRAY_SIZE(fixed_phy_port); i++) { + if (devnum == fixed_phy_port[i].devnum) { + speed = fixed_phy_port[i].speed; + duplex = fixed_phy_port[i].duplex; + break; + } + } + + if (i == ARRAY_SIZE(fixed_phy_port)) { + printf("ERROR: PHY (%s) not configured correctly!\n", + dev->name); + return -1; + } + } else { + speed = miiphy_speed(dev->name, reg); + duplex = miiphy_duplex(dev->name, reg); + } + + if (hw_p->print_speed) { + hw_p->print_speed = 0; + printf ("ENET Speed is %d Mbps - %s duplex connection (EMAC%d)\n", + (int) speed, (duplex == HALF) ? "HALF" : "FULL", + hw_p->devnum); + } + +#if defined(CONFIG_440) && \ + !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \ + !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) && \ + !defined(CONFIG_460EX) && !defined(CONFIG_460GT) +#if defined(CONFIG_440EP) || defined(CONFIG_440GR) + mfsdr(SDR0_MFR, reg); + if (speed == 100) { + reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_100M; + } else { + reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M; + } + mtsdr(SDR0_MFR, reg); +#endif + + /* Set ZMII/RGMII speed according to the phy link speed */ + reg = in_be32((void *)ZMII0_SSR); + if ( (speed == 100) || (speed == 1000) ) + out_be32((void *)ZMII0_SSR, reg | (ZMII0_SSR_SP << ZMII0_SSR_V (devnum))); + else + out_be32((void *)ZMII0_SSR, reg & (~(ZMII0_SSR_SP << ZMII0_SSR_V (devnum)))); + + if ((devnum == 2) || (devnum == 3)) { + if (speed == 1000) + reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum)); + else if (speed == 100) + reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V (devnum)); + else if (speed == 10) + reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V (devnum)); + else { + printf("Error in RGMII Speed\n"); + return -1; + } + out_be32((void *)RGMII_SSR, reg); + } +#endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */ + +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_405EX) + if (devnum >= 2) + rgmii_channel = devnum - 2; + else + rgmii_channel = devnum; + + if (speed == 1000) + reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V(rgmii_channel)); + else if (speed == 100) + reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V(rgmii_channel)); + else if (speed == 10) + reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V(rgmii_channel)); + else { + printf("Error in RGMII Speed\n"); + return -1; + } + out_be32((void *)RGMII_SSR, reg); +#if defined(CONFIG_460GT) + if ((devnum == 2) || (devnum == 3)) + out_be32((void *)RGMII_SSR + RGMII1_BASE_OFFSET, reg); +#endif +#endif + + /* set the Mal configuration reg */ +#if defined(CONFIG_440GX) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_405EX) + mtdcr (MAL0_CFG, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | + MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000); +#else + mtdcr (MAL0_CFG, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT); + /* Errata 1.12: MAL_1 -- Disable MAL bursting */ + if (get_pvr() == PVR_440GP_RB) { + mtdcr (MAL0_CFG, mfdcr(MAL0_CFG) & ~MAL_CR_PLBB); + } +#endif + + /* + * Malloc MAL buffer desciptors, make sure they are + * aligned on cache line boundary size + * (401/403/IOP480 = 16, 405 = 32) + * and doesn't cross cache block boundaries. + */ + if (hw_p->first_init == 0) { + debug("*** Allocating descriptor memory ***\n"); + + bd_cached = (u32)malloc_aligned(MAL_ALLOC_SIZE, 4096); + if (!bd_cached) { + printf("%s: Error allocating MAL descriptor buffers!\n", __func__); + return -1; + } + +#ifdef CONFIG_4xx_DCACHE + flush_dcache_range(bd_cached, bd_cached + MAL_ALLOC_SIZE); + if (!last_used_ea) +#if defined(CONFIG_SYS_MEM_TOP_HIDE) + bd_uncached = bis->bi_memsize + CONFIG_SYS_MEM_TOP_HIDE; +#else + bd_uncached = bis->bi_memsize; +#endif + else + bd_uncached = last_used_ea + MAL_ALLOC_SIZE; + + last_used_ea = bd_uncached; + program_tlb(bd_cached, bd_uncached, MAL_ALLOC_SIZE, + TLB_WORD2_I_ENABLE); +#else + bd_uncached = bd_cached; +#endif + hw_p->tx_phys = bd_cached; + hw_p->rx_phys = bd_cached + MAL_TX_DESC_SIZE; + hw_p->tx = (mal_desc_t *)(bd_uncached); + hw_p->rx = (mal_desc_t *)(bd_uncached + MAL_TX_DESC_SIZE); + debug("hw_p->tx=%p, hw_p->rx=%p\n", hw_p->tx, hw_p->rx); + } + + for (i = 0; i < NUM_TX_BUFF; i++) { + hw_p->tx[i].ctrl = 0; + hw_p->tx[i].data_len = 0; + if (hw_p->first_init == 0) + hw_p->txbuf_ptr = malloc_aligned(MAL_ALLOC_SIZE, + L1_CACHE_BYTES); + hw_p->tx[i].data_ptr = hw_p->txbuf_ptr; + if ((NUM_TX_BUFF - 1) == i) + hw_p->tx[i].ctrl |= MAL_TX_CTRL_WRAP; + hw_p->tx_run[i] = -1; + debug("TX_BUFF %d @ 0x%08x\n", i, (u32)hw_p->tx[i].data_ptr); + } + + for (i = 0; i < NUM_RX_BUFF; i++) { + hw_p->rx[i].ctrl = 0; + hw_p->rx[i].data_len = 0; + hw_p->rx[i].data_ptr = (char *)net_rx_packets[i]; + if ((NUM_RX_BUFF - 1) == i) + hw_p->rx[i].ctrl |= MAL_RX_CTRL_WRAP; + hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR; + hw_p->rx_ready[i] = -1; + debug("RX_BUFF %d @ 0x%08x\n", i, (u32)hw_p->rx[i].data_ptr); + } + + reg = 0x00000000; + + reg |= dev->enetaddr[0]; /* set high address */ + reg = reg << 8; + reg |= dev->enetaddr[1]; + + out_be32((void *)EMAC0_IAH + hw_p->hw_addr, reg); + + reg = 0x00000000; + reg |= dev->enetaddr[2]; /* set low address */ + reg = reg << 8; + reg |= dev->enetaddr[3]; + reg = reg << 8; + reg |= dev->enetaddr[4]; + reg = reg << 8; + reg |= dev->enetaddr[5]; + + out_be32((void *)EMAC0_IAL + hw_p->hw_addr, reg); + + switch (devnum) { + case 1: + /* setup MAL tx & rx channel pointers */ +#if defined (CONFIG_405EP) || defined (CONFIG_440EP) || defined (CONFIG_440GR) + mtdcr (MAL0_TXCTP2R, hw_p->tx_phys); +#else + mtdcr (MAL0_TXCTP1R, hw_p->tx_phys); +#endif +#if defined(CONFIG_440) + mtdcr (MAL0_TXBADDR, 0x0); + mtdcr (MAL0_RXBADDR, 0x0); +#endif + +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) + mtdcr (MAL0_RXCTP8R, hw_p->rx_phys); + /* set RX buffer size */ + mtdcr (MAL0_RCBS8, ENET_MAX_MTU_ALIGNED / 16); +#else + mtdcr (MAL0_RXCTP1R, hw_p->rx_phys); + /* set RX buffer size */ + mtdcr (MAL0_RCBS1, ENET_MAX_MTU_ALIGNED / 16); +#endif + break; +#if defined (CONFIG_440GX) + case 2: + /* setup MAL tx & rx channel pointers */ + mtdcr (MAL0_TXBADDR, 0x0); + mtdcr (MAL0_RXBADDR, 0x0); + mtdcr (MAL0_TXCTP2R, hw_p->tx_phys); + mtdcr (MAL0_RXCTP2R, hw_p->rx_phys); + /* set RX buffer size */ + mtdcr (MAL0_RCBS2, ENET_MAX_MTU_ALIGNED / 16); + break; + case 3: + /* setup MAL tx & rx channel pointers */ + mtdcr (MAL0_TXBADDR, 0x0); + mtdcr (MAL0_TXCTP3R, hw_p->tx_phys); + mtdcr (MAL0_RXBADDR, 0x0); + mtdcr (MAL0_RXCTP3R, hw_p->rx_phys); + /* set RX buffer size */ + mtdcr (MAL0_RCBS3, ENET_MAX_MTU_ALIGNED / 16); + break; +#endif /* CONFIG_440GX */ +#if defined (CONFIG_460GT) + case 2: + /* setup MAL tx & rx channel pointers */ + mtdcr (MAL0_TXBADDR, 0x0); + mtdcr (MAL0_RXBADDR, 0x0); + mtdcr (MAL0_TXCTP2R, hw_p->tx_phys); + mtdcr (MAL0_RXCTP16R, hw_p->rx_phys); + /* set RX buffer size */ + mtdcr (MAL0_RCBS16, ENET_MAX_MTU_ALIGNED / 16); + break; + case 3: + /* setup MAL tx & rx channel pointers */ + mtdcr (MAL0_TXBADDR, 0x0); + mtdcr (MAL0_RXBADDR, 0x0); + mtdcr (MAL0_TXCTP3R, hw_p->tx_phys); + mtdcr (MAL0_RXCTP24R, hw_p->rx_phys); + /* set RX buffer size */ + mtdcr (MAL0_RCBS24, ENET_MAX_MTU_ALIGNED / 16); + break; +#endif /* CONFIG_460GT */ + case 0: + default: + /* setup MAL tx & rx channel pointers */ +#if defined(CONFIG_440) + mtdcr (MAL0_TXBADDR, 0x0); + mtdcr (MAL0_RXBADDR, 0x0); +#endif + mtdcr (MAL0_TXCTP0R, hw_p->tx_phys); + mtdcr (MAL0_RXCTP0R, hw_p->rx_phys); + /* set RX buffer size */ + mtdcr (MAL0_RCBS0, ENET_MAX_MTU_ALIGNED / 16); + break; + } + + /* Enable MAL transmit and receive channels */ +#if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR) + mtdcr (MAL0_TXCASR, (MAL_TXRX_CASR >> (hw_p->devnum*2))); +#else + mtdcr (MAL0_TXCASR, (MAL_TXRX_CASR >> hw_p->devnum)); +#endif + mtdcr (MAL0_RXCASR, (MAL_TXRX_CASR >> hw_p->devnum)); + + /* set transmit enable & receive enable */ + out_be32((void *)EMAC0_MR0 + hw_p->hw_addr, EMAC_MR0_TXE | EMAC_MR0_RXE); + + mode_reg = in_be32((void *)EMAC0_MR1 + hw_p->hw_addr); + + /* set rx-/tx-fifo size */ + mode_reg = (mode_reg & ~EMAC_MR1_FIFO_MASK) | EMAC_MR1_FIFO_SIZE; + + /* set speed */ + if (speed == _1000BASET) { +#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) + unsigned long pfc1; + + mfsdr (SDR0_PFC1, pfc1); + pfc1 |= SDR0_PFC1_EM_1000; + mtsdr (SDR0_PFC1, pfc1); +#endif + mode_reg = mode_reg | EMAC_MR1_MF_1000MBPS | EMAC_MR1_IST; + } else if (speed == _100BASET) + mode_reg = mode_reg | EMAC_MR1_MF_100MBPS | EMAC_MR1_IST; + else + mode_reg = mode_reg & ~0x00C00000; /* 10 MBPS */ + if (duplex == FULL) + mode_reg = mode_reg | 0x80000000 | EMAC_MR1_IST; + + out_be32((void *)EMAC0_MR1 + hw_p->hw_addr, mode_reg); + + /* Enable broadcast and indvidual address */ + /* TBS: enabling runts as some misbehaved nics will send runts */ + out_be32((void *)EMAC0_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE); + + /* we probably need to set the tx mode1 reg? maybe at tx time */ + + /* set transmit request threshold register */ + out_be32((void *)EMAC0_TRTR + hw_p->hw_addr, 0x18000000); /* 256 byte threshold */ + + /* set receive low/high water mark register */ +#if defined(CONFIG_440) + /* 440s has a 64 byte burst length */ + out_be32((void *)EMAC0_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000); +#else + /* 405s have a 16 byte burst length */ + out_be32((void *)EMAC0_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000); +#endif /* defined(CONFIG_440) */ + out_be32((void *)EMAC0_TMR1 + hw_p->hw_addr, 0xf8640000); + + /* Set fifo limit entry in tx mode 0 */ + out_be32((void *)EMAC0_TMR0 + hw_p->hw_addr, 0x00000003); + /* Frame gap set */ + out_be32((void *)EMAC0_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008); + + /* Set EMAC IER */ + hw_p->emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS | EMAC_ISR_ORE | EMAC_ISR_IRE; + if (speed == _100BASET) + hw_p->emac_ier = hw_p->emac_ier | EMAC_ISR_SYE; + + out_be32((void *)EMAC0_ISR + hw_p->hw_addr, 0xffffffff); /* clear pending interrupts */ + out_be32((void *)EMAC0_IER + hw_p->hw_addr, hw_p->emac_ier); + + if (hw_p->first_init == 0) { + /* + * Connect interrupt service routines + */ + irq_install_handler(ETH_IRQ_NUM(hw_p->devnum), + (interrupt_handler_t *) enetInt, dev); + } + + mtmsr (msr); /* enable interrupts again */ + + hw_p->bis = bis; + hw_p->first_init = 1; + + return 0; +} + + +static int ppc_4xx_eth_send(struct eth_device *dev, void *ptr, int len) +{ + struct enet_frame *ef_ptr; + ulong time_start, time_now; + unsigned long temp_txm0; + EMAC_4XX_HW_PST hw_p = dev->priv; + + ef_ptr = (struct enet_frame *) ptr; + + /*-----------------------------------------------------------------------+ + * Copy in our address into the frame. + *-----------------------------------------------------------------------*/ + (void) memcpy (ef_ptr->source_addr, dev->enetaddr, ENET_ADDR_LENGTH); + + /*-----------------------------------------------------------------------+ + * If frame is too long or too short, modify length. + *-----------------------------------------------------------------------*/ + /* TBS: where does the fragment go???? */ + if (len > ENET_MAX_MTU) + len = ENET_MAX_MTU; + + /* memcpy ((void *) &tx_buff[tx_slot], (const void *) ptr, len); */ + memcpy ((void *) hw_p->txbuf_ptr, (const void *) ptr, len); + flush_dcache_range((u32)hw_p->txbuf_ptr, (u32)hw_p->txbuf_ptr + len); + + /*-----------------------------------------------------------------------+ + * set TX Buffer busy, and send it + *-----------------------------------------------------------------------*/ + hw_p->tx[hw_p->tx_slot].ctrl = (MAL_TX_CTRL_LAST | + EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP) & + ~(EMAC_TX_CTRL_ISA | EMAC_TX_CTRL_RSA); + if ((NUM_TX_BUFF - 1) == hw_p->tx_slot) + hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_WRAP; + + hw_p->tx[hw_p->tx_slot].data_len = (short) len; + hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_READY; + + sync(); + + out_be32((void *)EMAC0_TMR0 + hw_p->hw_addr, + in_be32((void *)EMAC0_TMR0 + hw_p->hw_addr) | EMAC_TMR0_GNP0); +#ifdef INFO_4XX_ENET + hw_p->stats.pkts_tx++; +#endif + + /*-----------------------------------------------------------------------+ + * poll unitl the packet is sent and then make sure it is OK + *-----------------------------------------------------------------------*/ + time_start = get_timer (0); + while (1) { + temp_txm0 = in_be32((void *)EMAC0_TMR0 + hw_p->hw_addr); + /* loop until either TINT turns on or 3 seconds elapse */ + if ((temp_txm0 & EMAC_TMR0_GNP0) != 0) { + /* transmit is done, so now check for errors + * If there is an error, an interrupt should + * happen when we return + */ + time_now = get_timer (0); + if ((time_now - time_start) > 3000) { + return (-1); + } + } else { + return (len); + } + } +} + +int enetInt (struct eth_device *dev) +{ + int serviced; + int rc = -1; /* default to not us */ + u32 mal_isr; + u32 emac_isr = 0; + u32 mal_eob; + u32 uic_mal; + u32 uic_mal_err; + u32 uic_emac; + u32 uic_emac_b; + EMAC_4XX_HW_PST hw_p; + + /* + * Because the mal is generic, we need to get the current + * eth device + */ + dev = eth_get_dev(); + + hw_p = dev->priv; + + /* enter loop that stays in interrupt code until nothing to service */ + do { + serviced = 0; + + uic_mal = mfdcr(UIC_BASE_MAL + UIC_MSR); + uic_mal_err = mfdcr(UIC_BASE_MAL_ERR + UIC_MSR); + uic_emac = mfdcr(UIC_BASE_EMAC + UIC_MSR); + uic_emac_b = mfdcr(UIC_BASE_EMAC_B + UIC_MSR); + + if (!(uic_mal & (UIC_MAL_RXEOB | UIC_MAL_TXEOB)) + && !(uic_mal_err & (UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)) + && !(uic_emac & UIC_ETHx) && !(uic_emac_b & UIC_ETHxB)) { + /* not for us */ + return (rc); + } + + /* get and clear controller status interrupts */ + /* look at MAL and EMAC error interrupts */ + if (uic_mal_err & (UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)) { + /* we have a MAL error interrupt */ + mal_isr = mfdcr(MAL0_ESR); + mal_err(dev, mal_isr, uic_mal_err, + MAL_UIC_DEF, MAL_UIC_ERR); + + /* clear MAL error interrupt status bits */ + mtdcr(UIC_BASE_MAL_ERR + UIC_SR, + UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE); + + return -1; + } + + /* look for EMAC errors */ + if ((uic_emac & UIC_ETHx) || (uic_emac_b & UIC_ETHxB)) { + emac_isr = in_be32((void *)EMAC0_ISR + hw_p->hw_addr); + emac_err(dev, emac_isr); + + /* clear EMAC error interrupt status bits */ + mtdcr(UIC_BASE_EMAC + UIC_SR, UIC_ETHx); + mtdcr(UIC_BASE_EMAC_B + UIC_SR, UIC_ETHxB); + + return -1; + } + + /* handle MAX TX EOB interrupt from a tx */ + if (uic_mal & UIC_MAL_TXEOB) { + /* clear MAL interrupt status bits */ + mal_eob = mfdcr(MAL0_TXEOBISR); + mtdcr(MAL0_TXEOBISR, mal_eob); + mtdcr(UIC_BASE_MAL + UIC_SR, UIC_MAL_TXEOB); + + /* indicate that we serviced an interrupt */ + serviced = 1; + rc = 0; + } + + /* handle MAL RX EOB interrupt from a receive */ + /* check for EOB on valid channels */ + if (uic_mal & UIC_MAL_RXEOB) { + mal_eob = mfdcr(MAL0_RXEOBISR); + if (mal_eob & + (0x80000000 >> (hw_p->devnum * MAL_RX_CHAN_MUL))) { + /* push packet to upper layer */ + enet_rcv(dev, emac_isr); + + /* clear MAL interrupt status bits */ + mtdcr(UIC_BASE_MAL + UIC_SR, UIC_MAL_RXEOB); + + /* indicate that we serviced an interrupt */ + serviced = 1; + rc = 0; + } + } +#if defined(CONFIG_405EZ) + /* + * On 405EZ the RX-/TX-interrupts are coalesced into + * one IRQ bit in the UIC. We need to acknowledge the + * RX-/TX-interrupts in the SDR0_ICINTSTAT reg as well. + */ + mtsdr(SDR0_ICINTSTAT, + SDR_ICRX_STAT | SDR_ICTX0_STAT | SDR_ICTX1_STAT); +#endif /* defined(CONFIG_405EZ) */ + } while (serviced); + + return (rc); +} + +/*-----------------------------------------------------------------------------+ + * MAL Error Routine + *-----------------------------------------------------------------------------*/ +static void mal_err (struct eth_device *dev, unsigned long isr, + unsigned long uic, unsigned long maldef, + unsigned long mal_errr) +{ + mtdcr (MAL0_ESR, isr); /* clear interrupt */ + + /* clear DE interrupt */ + mtdcr (MAL0_TXDEIR, 0xC0000000); + mtdcr (MAL0_RXDEIR, 0x80000000); + +#ifdef INFO_4XX_ENET + printf("\nMAL error occured.... ISR = %lx UIC = = %lx MAL_DEF = %lx MAL_ERR= %lx\n", + isr, uic, maldef, mal_errr); +#endif + + eth_init(); /* start again... */ +} + +/*-----------------------------------------------------------------------------+ + * EMAC Error Routine + *-----------------------------------------------------------------------------*/ +static void emac_err (struct eth_device *dev, unsigned long isr) +{ + EMAC_4XX_HW_PST hw_p = dev->priv; + + printf ("EMAC%d error occured.... ISR = %lx\n", hw_p->devnum, isr); + out_be32((void *)EMAC0_ISR + hw_p->hw_addr, isr); +} + +/*-----------------------------------------------------------------------------+ + * enet_rcv() handles the ethernet receive data + *-----------------------------------------------------------------------------*/ +static void enet_rcv (struct eth_device *dev, unsigned long malisr) +{ + unsigned long data_len; + unsigned long rx_eob_isr; + EMAC_4XX_HW_PST hw_p = dev->priv; + + int handled = 0; + int i; + int loop_count = 0; + + rx_eob_isr = mfdcr (MAL0_RXEOBISR); + if ((0x80000000 >> (hw_p->devnum * MAL_RX_CHAN_MUL)) & rx_eob_isr) { + /* clear EOB */ + mtdcr (MAL0_RXEOBISR, rx_eob_isr); + + /* EMAC RX done */ + while (1) { /* do all */ + i = hw_p->rx_slot; + + if ((MAL_RX_CTRL_EMPTY & hw_p->rx[i].ctrl) + || (loop_count >= NUM_RX_BUFF)) + break; + + loop_count++; + handled++; + data_len = (unsigned long) hw_p->rx[i].data_len & 0x0fff; /* Get len */ + if (data_len) { + if (data_len > ENET_MAX_MTU) /* Check len */ + data_len = 0; + else { + if (EMAC_RX_ERRORS & hw_p->rx[i].ctrl) { /* Check Errors */ + data_len = 0; + hw_p->stats.rx_err_log[hw_p-> + rx_err_index] + = hw_p->rx[i].ctrl; + hw_p->rx_err_index++; + if (hw_p->rx_err_index == + MAX_ERR_LOG) + hw_p->rx_err_index = + 0; + } /* emac_erros */ + } /* data_len < max mtu */ + } /* if data_len */ + if (!data_len) { /* no data */ + hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY; /* Free Recv Buffer */ + + hw_p->stats.data_len_err++; /* Error at Rx */ + } + + /* !data_len */ + /* AS.HARNOIS */ + /* Check if user has already eaten buffer */ + /* if not => ERROR */ + else if (hw_p->rx_ready[hw_p->rx_i_index] != -1) { + if (hw_p->is_receiving) + printf ("ERROR : Receive buffers are full!\n"); + break; + } else { + hw_p->stats.rx_frames++; + hw_p->stats.rx += data_len; +#ifdef INFO_4XX_ENET + hw_p->stats.pkts_rx++; +#endif + /* AS.HARNOIS + * use ring buffer + */ + hw_p->rx_ready[hw_p->rx_i_index] = i; + hw_p->rx_i_index++; + if (NUM_RX_BUFF == hw_p->rx_i_index) + hw_p->rx_i_index = 0; + + hw_p->rx_slot++; + if (NUM_RX_BUFF == hw_p->rx_slot) + hw_p->rx_slot = 0; + + /* AS.HARNOIS + * free receive buffer only when + * buffer has been handled (eth_rx) + rx[i].ctrl |= MAL_RX_CTRL_EMPTY; + */ + } /* if data_len */ + } /* while */ + } /* if EMACK_RXCHL */ +} + + +static int ppc_4xx_eth_rx (struct eth_device *dev) +{ + int length; + int user_index; + unsigned long msr; + EMAC_4XX_HW_PST hw_p = dev->priv; + + hw_p->is_receiving = 1; /* tell driver */ + + for (;;) { + /* AS.HARNOIS + * use ring buffer and + * get index from rx buffer desciptor queue + */ + user_index = hw_p->rx_ready[hw_p->rx_u_index]; + if (user_index == -1) { + length = -1; + break; /* nothing received - leave for() loop */ + } + + msr = mfmsr (); + mtmsr (msr & ~(MSR_EE)); + + length = hw_p->rx[user_index].data_len & 0x0fff; + + /* + * Pass the packet up to the protocol layers. + * net_process_received_packet(net_rx_packets[rxIdx], + * length - 4); + * net_process_received_packet(net_rx_packets[i], length); + */ + invalidate_dcache_range((u32)hw_p->rx[user_index].data_ptr, + (u32)hw_p->rx[user_index].data_ptr + + length - 4); + net_process_received_packet(net_rx_packets[user_index], + length - 4); + /* Free Recv Buffer */ + hw_p->rx[user_index].ctrl |= MAL_RX_CTRL_EMPTY; + /* Free rx buffer descriptor queue */ + hw_p->rx_ready[hw_p->rx_u_index] = -1; + hw_p->rx_u_index++; + if (NUM_RX_BUFF == hw_p->rx_u_index) + hw_p->rx_u_index = 0; + +#ifdef INFO_4XX_ENET + hw_p->stats.pkts_handled++; +#endif + + mtmsr (msr); /* Enable IRQ's */ + } + + hw_p->is_receiving = 0; /* tell driver */ + + return length; +} + +int ppc_4xx_eth_initialize (bd_t * bis) +{ + static int virgin = 0; + struct eth_device *dev; + int eth_num = 0; + EMAC_4XX_HW_PST hw = NULL; + u8 ethaddr[4 + CONFIG_EMAC_NR_START][6]; + u32 hw_addr[4]; + u32 mal_ier; + +#if defined(CONFIG_440GX) + unsigned long pfc1; + + mfsdr (SDR0_PFC1, pfc1); + pfc1 &= ~(0x01e00000); + pfc1 |= 0x01200000; + mtsdr (SDR0_PFC1, pfc1); +#endif + + /* first clear all mac-addresses */ + for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) + memcpy(ethaddr[eth_num], "\0\0\0\0\0\0", 6); + + for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) { + int ethaddr_idx = eth_num + CONFIG_EMAC_NR_START; + switch (eth_num) { + default: /* fall through */ + case 0: + eth_getenv_enetaddr("ethaddr", ethaddr[ethaddr_idx]); + hw_addr[eth_num] = 0x0; + break; +#ifdef CONFIG_HAS_ETH1 + case 1: + eth_getenv_enetaddr("eth1addr", ethaddr[ethaddr_idx]); + hw_addr[eth_num] = 0x100; + break; +#endif +#ifdef CONFIG_HAS_ETH2 + case 2: + eth_getenv_enetaddr("eth2addr", ethaddr[ethaddr_idx]); +#if defined(CONFIG_460GT) + hw_addr[eth_num] = 0x300; +#else + hw_addr[eth_num] = 0x400; +#endif + break; +#endif +#ifdef CONFIG_HAS_ETH3 + case 3: + eth_getenv_enetaddr("eth3addr", ethaddr[ethaddr_idx]); +#if defined(CONFIG_460GT) + hw_addr[eth_num] = 0x400; +#else + hw_addr[eth_num] = 0x600; +#endif + break; +#endif + } + } + + /* set phy num and mode */ + bis->bi_phynum[0] = CONFIG_PHY_ADDR; + bis->bi_phymode[0] = 0; + +#if defined(CONFIG_PHY1_ADDR) + bis->bi_phynum[1] = CONFIG_PHY1_ADDR; + bis->bi_phymode[1] = 0; +#endif +#if defined(CONFIG_440GX) + bis->bi_phynum[2] = CONFIG_PHY2_ADDR; + bis->bi_phynum[3] = CONFIG_PHY3_ADDR; + bis->bi_phymode[2] = 2; + bis->bi_phymode[3] = 2; +#endif + +#if defined(CONFIG_440GX) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_405EX) + ppc_4xx_eth_setup_bridge(0, bis); +#endif + + for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) { + /* + * See if we can actually bring up the interface, + * otherwise, skip it + */ + if (memcmp (ethaddr[eth_num], "\0\0\0\0\0\0", 6) == 0) { + bis->bi_phymode[eth_num] = BI_PHYMODE_NONE; + continue; + } + + /* Allocate device structure */ + dev = (struct eth_device *) malloc (sizeof (*dev)); + if (dev == NULL) { + printf ("ppc_4xx_eth_initialize: " + "Cannot allocate eth_device %d\n", eth_num); + return (-1); + } + memset(dev, 0, sizeof(*dev)); + + /* Allocate our private use data */ + hw = (EMAC_4XX_HW_PST) malloc (sizeof (*hw)); + if (hw == NULL) { + printf ("ppc_4xx_eth_initialize: " + "Cannot allocate private hw data for eth_device %d", + eth_num); + free (dev); + return (-1); + } + memset(hw, 0, sizeof(*hw)); + + hw->hw_addr = hw_addr[eth_num]; + memcpy (dev->enetaddr, ethaddr[eth_num], 6); + hw->devnum = eth_num; + hw->print_speed = 1; + + sprintf (dev->name, "ppc_4xx_eth%d", eth_num - CONFIG_EMAC_NR_START); + dev->priv = (void *) hw; + dev->init = ppc_4xx_eth_init; + dev->halt = ppc_4xx_eth_halt; + dev->send = ppc_4xx_eth_send; + dev->recv = ppc_4xx_eth_rx; + + eth_register(dev); + +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) + miiphy_register(dev->name, + emac4xx_miiphy_read, emac4xx_miiphy_write); +#endif + + if (0 == virgin) { + /* set the MAL IER ??? names may change with new spec ??? */ +#if defined(CONFIG_440SPE) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_405EX) + mal_ier = + MAL_IER_PT | MAL_IER_PRE | MAL_IER_PWE | + MAL_IER_DE | MAL_IER_OTE | MAL_IER_OE | MAL_IER_PE ; +#else + mal_ier = + MAL_IER_DE | MAL_IER_NE | MAL_IER_TE | + MAL_IER_OPBE | MAL_IER_PLBE; +#endif + mtdcr (MAL0_ESR, 0xffffffff); /* clear pending interrupts */ + mtdcr (MAL0_TXDEIR, 0xffffffff); /* clear pending interrupts */ + mtdcr (MAL0_RXDEIR, 0xffffffff); /* clear pending interrupts */ + mtdcr (MAL0_IER, mal_ier); + + /* install MAL interrupt handler */ + irq_install_handler (VECNUM_MAL_SERR, + (interrupt_handler_t *) enetInt, + dev); + irq_install_handler (VECNUM_MAL_TXEOB, + (interrupt_handler_t *) enetInt, + dev); + irq_install_handler (VECNUM_MAL_RXEOB, + (interrupt_handler_t *) enetInt, + dev); + irq_install_handler (VECNUM_MAL_TXDE, + (interrupt_handler_t *) enetInt, + dev); + irq_install_handler (VECNUM_MAL_RXDE, + (interrupt_handler_t *) enetInt, + dev); + virgin = 1; + } + } /* end for each supported device */ + + return 0; +} diff --git a/sources/uboot-be550/drivers/net/8390.h b/sources/uboot-be550/drivers/net/8390.h new file mode 100644 index 00000000..f087217e --- /dev/null +++ b/sources/uboot-be550/drivers/net/8390.h @@ -0,0 +1,124 @@ +/* + +Ported to U-Boot by Christian Pellegrin + +Based on sources from the Linux kernel (pcnet_cs.c, 8390.h) and +eCOS(if_dp83902a.c, if_dp83902a.h). Both of these 2 wonderful world +are GPL, so this is, of course, GPL. + +*/ + +/* Generic NS8390 register definitions. */ +/* This file is part of Donald Becker's 8390 drivers, and is distributed + under the same license. Auto-loading of 8390.o only in v2.2 - Paul G. + Some of these names and comments originated from the Crynwr + packet drivers, which are distributed under the GPL. */ + +#ifndef _8390_h +#define _8390_h + +/* Some generic ethernet register configurations. */ +#define E8390_TX_IRQ_MASK 0xa /* For register EN0_ISR */ +#define E8390_RX_IRQ_MASK 0x5 +#define E8390_RXCONFIG 0x4 /* EN0_RXCR: broadcasts, no multicast,errors */ +#define E8390_RXOFF 0x20 /* EN0_RXCR: Accept no packets */ +#define E8390_TXCONFIG 0x00 /* EN0_TXCR: Normal transmit mode */ +#define E8390_TXOFF 0x02 /* EN0_TXCR: Transmitter off */ + +/* Register accessed at EN_CMD, the 8390 base addr. */ +#define E8390_STOP 0x01 /* Stop and reset the chip */ +#define E8390_START 0x02 /* Start the chip, clear reset */ +#define E8390_TRANS 0x04 /* Transmit a frame */ +#define E8390_RREAD 0x08 /* Remote read */ +#define E8390_RWRITE 0x10 /* Remote write */ +#define E8390_NODMA 0x20 /* Remote DMA */ +#define E8390_PAGE0 0x00 /* Select page chip registers */ +#define E8390_PAGE1 0x40 /* using the two high-order bits */ +#define E8390_PAGE2 0x80 /* Page 3 is invalid. */ + +/* + * Only generate indirect loads given a machine that needs them. + * - removed AMIGA_PCMCIA from this list, handled as ISA io now + */ + +#define n2k_inb(port) (*((volatile unsigned char *)(port+CONFIG_DRIVER_NE2000_BASE))) +#define n2k_outb(val,port) (*((volatile unsigned char *)(port+CONFIG_DRIVER_NE2000_BASE)) = val) + +#define EI_SHIFT(x) (x) + +#define E8390_CMD EI_SHIFT(0x00) /* The command register (for all pages) */ +/* Page 0 register offsets. */ +#define EN0_CLDALO EI_SHIFT(0x01) /* Low byte of current local dma addr RD */ +#define EN0_STARTPG EI_SHIFT(0x01) /* Starting page of ring bfr WR */ +#define EN0_CLDAHI EI_SHIFT(0x02) /* High byte of current local dma addr RD */ +#define EN0_STOPPG EI_SHIFT(0x02) /* Ending page +1 of ring bfr WR */ +#define EN0_BOUNDARY EI_SHIFT(0x03) /* Boundary page of ring bfr RD WR */ +#define EN0_TSR EI_SHIFT(0x04) /* Transmit status reg RD */ +#define EN0_TPSR EI_SHIFT(0x04) /* Transmit starting page WR */ +#define EN0_NCR EI_SHIFT(0x05) /* Number of collision reg RD */ +#define EN0_TCNTLO EI_SHIFT(0x05) /* Low byte of tx byte count WR */ +#define EN0_FIFO EI_SHIFT(0x06) /* FIFO RD */ +#define EN0_TCNTHI EI_SHIFT(0x06) /* High byte of tx byte count WR */ +#define EN0_ISR EI_SHIFT(0x07) /* Interrupt status reg RD WR */ +#define EN0_CRDALO EI_SHIFT(0x08) /* low byte of current remote dma address RD */ +#define EN0_RSARLO EI_SHIFT(0x08) /* Remote start address reg 0 */ +#define EN0_CRDAHI EI_SHIFT(0x09) /* high byte, current remote dma address RD */ +#define EN0_RSARHI EI_SHIFT(0x09) /* Remote start address reg 1 */ +#define EN0_RCNTLO EI_SHIFT(0x0a) /* Remote byte count reg WR */ +#define EN0_RCNTHI EI_SHIFT(0x0b) /* Remote byte count reg WR */ +#define EN0_RSR EI_SHIFT(0x0c) /* rx status reg RD */ +#define EN0_RXCR EI_SHIFT(0x0c) /* RX configuration reg WR */ +#define EN0_TXCR EI_SHIFT(0x0d) /* TX configuration reg WR */ +#define EN0_COUNTER0 EI_SHIFT(0x0d) /* Rcv alignment error counter RD */ +#define EN0_DCFG EI_SHIFT(0x0e) /* Data configuration reg WR */ +#define EN0_COUNTER1 EI_SHIFT(0x0e) /* Rcv CRC error counter RD */ +#define EN0_IMR EI_SHIFT(0x0f) /* Interrupt mask reg WR */ +#define EN0_COUNTER2 EI_SHIFT(0x0f) /* Rcv missed frame error counter RD */ + +/* Bits in EN0_ISR - Interrupt status register */ +#define ENISR_RX 0x01 /* Receiver, no error */ +#define ENISR_TX 0x02 /* Transmitter, no error */ +#define ENISR_RX_ERR 0x04 /* Receiver, with error */ +#define ENISR_TX_ERR 0x08 /* Transmitter, with error */ +#define ENISR_OVER 0x10 /* Receiver overwrote the ring */ +#define ENISR_COUNTERS 0x20 /* Counters need emptying */ +#define ENISR_RDC 0x40 /* remote dma complete */ +#define ENISR_RESET 0x80 /* Reset completed */ +#define ENISR_ALL 0x3f /* Interrupts we will enable */ + +/* Bits in EN0_DCFG - Data config register */ +#define ENDCFG_WTS 0x01 /* word transfer mode selection */ +#define ENDCFG_BOS 0x02 /* byte order selection */ +#define ENDCFG_AUTO_INIT 0x10 /* Auto-init to remove packets from ring */ +#define ENDCFG_FIFO 0x40 /* 8 bytes */ + +/* Page 1 register offsets. */ +#define EN1_PHYS EI_SHIFT(0x01) /* This board's physical enet addr RD WR */ +#define EN1_PHYS_SHIFT(i) EI_SHIFT(i+1) /* Get and set mac address */ +#define EN1_CURPAG EI_SHIFT(0x07) /* Current memory page RD WR */ +#define EN1_MULT EI_SHIFT(0x08) /* Multicast filter mask array (8 bytes) RD WR */ +#define EN1_MULT_SHIFT(i) EI_SHIFT(8+i) /* Get and set multicast filter */ + +/* Bits in received packet status byte and EN0_RSR*/ +#define ENRSR_RXOK 0x01 /* Received a good packet */ +#define ENRSR_CRC 0x02 /* CRC error */ +#define ENRSR_FAE 0x04 /* frame alignment error */ +#define ENRSR_FO 0x08 /* FIFO overrun */ +#define ENRSR_MPA 0x10 /* missed pkt */ +#define ENRSR_PHY 0x20 /* physical/multicast address */ +#define ENRSR_DIS 0x40 /* receiver disable. set in monitor mode */ +#define ENRSR_DEF 0x80 /* deferring */ + +/* Transmitted packet status, EN0_TSR. */ +#define ENTSR_PTX 0x01 /* Packet transmitted without error */ +#define ENTSR_ND 0x02 /* The transmit wasn't deferred. */ +#define ENTSR_COL 0x04 /* The transmit collided at least once. */ +#define ENTSR_ABT 0x08 /* The transmit collided 16 times, and was deferred. */ +#define ENTSR_CRS 0x10 /* The carrier sense was lost. */ +#define ENTSR_FU 0x20 /* A "FIFO underrun" occurred during transmit. */ +#define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */ +#define ENTSR_OWC 0x80 /* There was an out-of-window collision. */ + +#define NIC_RECEIVE_MONITOR_MODE 0x20 + +#endif /* _8390_h */ diff --git a/sources/uboot-be550/drivers/net/Kconfig b/sources/uboot-be550/drivers/net/Kconfig new file mode 100644 index 00000000..71988df3 --- /dev/null +++ b/sources/uboot-be550/drivers/net/Kconfig @@ -0,0 +1,158 @@ +config DM_ETH + bool "Enable Driver Model for Ethernet drivers" + depends on DM + help + Enable driver model for Ethernet. + + The eth_*() interface will be implemented by the UC_ETH class + This is currently implemented in net/eth.c + Look in include/net.h for details. + +config PHYLIB + bool "Ethernet PHY (physical media interface) support" + help + Enable Ethernet PHY (physical media interface) support. + +menuconfig NETDEVICES + bool "Network device support" + depends on NET + default y if DM_ETH + help + You must select Y to enable any network device support + Generally if you have any networking support this is a given + + If unsure, say Y + +if NETDEVICES + +config ALTERA_TSE + bool "Altera Triple-Speed Ethernet MAC support" + depends on DM_ETH + select PHYLIB + help + This driver supports the Altera Triple-Speed (TSE) Ethernet MAC. + Please find details on the "Triple-Speed Ethernet MegaCore Function + Resource Center" of Altera. + +config E1000 + bool "Intel PRO/1000 Gigabit Ethernet support" + help + This driver supports Intel(R) PRO/1000 gigabit ethernet family of + adapters. For more information on how to identify your adapter, go + to the Adapter & Driver ID Guide at: + + + +config E1000_SPI_GENERIC + bool "Allow access to the Intel 8257x SPI bus" + depends on E1000 + help + Allow generic access to the SPI bus on the Intel 8257x, for + example with the "sspi" command. + +config E1000_SPI + bool "Enable SPI bus utility code" + depends on E1000 + help + Utility code for direct access to the SPI bus on Intel 8257x. + This does not do anything useful unless you set at least one + of CONFIG_CMD_E1000 or CONFIG_E1000_SPI_GENERIC. + +config CMD_E1000 + bool "Enable the e1000 command" + depends on E1000 + help + This enables the 'e1000' management command for E1000 devices. When + used on devices with SPI support you can reprogram the EEPROM from + U-Boot. + +config ETH_SANDBOX + depends on DM_ETH && SANDBOX + default y + bool "Sandbox: Mocked Ethernet driver" + help + This driver simply responds with fake ARP replies and ping + replies that are used to verify network stack functionality + + This driver is particularly useful in the test/dm/eth.c tests + +config ETH_SANDBOX_RAW + depends on DM_ETH && SANDBOX + default y + bool "Sandbox: Bridge to Linux Raw Sockets" + help + This driver is a bridge from the bottom of the network stack + in U-Boot to the RAW AF_PACKET API in Linux. This allows real + network traffic to be tested from within sandbox. See + board/sandbox/README.sandbox for more details. + +config ETH_DESIGNWARE + bool "Synopsys Designware Ethernet MAC" + select PHYLIB + help + This MAC is present in SoCs from various vendors. It supports + 100Mbit and 1 Gbit operation. You must enable CONFIG_PHYLIB to + provide the PHY (physical media interface). + +config PCH_GBE + bool "Intel Platform Controller Hub EG20T GMAC driver" + depends on DM_ETH && DM_PCI + select PHYLIB + help + This MAC is present in Intel Platform Controller Hub EG20T. It + supports 10/100/1000 Mbps operation. + +config ZYNQ_GEM + depends on DM_ETH && (ARCH_ZYNQ || ARCH_ZYNQMP) + select PHYLIB + bool "Xilinx Ethernet GEM" + help + This MAC is present in Xilinx Zynq and ZynqMP SoCs. + +endif # NETDEVICES + +config IPQ_QCA_AQUANTIA_PHY + bool "Aquantia PHY support" + help + Enable Aquantia PHY support. + +config ATHRS17C_SWITCH + bool "QTI S17C switch support" + help + Enable QTI S17C switch support. + +config QCA8084_PHY + depends on QCA8081_PHY + bool "Enable QCA8084 Ethernet Chip support" + +if QCA8084_PHY + +config QCA8084_PHY_MODE + bool "Enable QCA8084 PHY Mode support" + help + Enable QCA8084 PHY Mode support. + +config QCA8084_SWT_MODE + bool "Enable QCA8084 Switch Mode support" + help + Enable QCA8084 Switch Mode support. + +if QCA8084_SWT_MODE + +config QCA8084_BYPASS_MODE + bool "Enable QCA8084 By-pass support" + help + Enable QCA808 By-pass support. + +endif # QCA8084_SWT_MODE + +config QCA8084_DEBUG + bool "Enable QCA8084 Debug support" + help + Enable QCA8084 Debug support. + +endif # QCA8084_PHY + +config IPQ_QTI_BIT_BANGMII + bool "Enable MDIO Gpio bit bang support" + depends on BITBANGMII diff --git a/sources/uboot-be550/drivers/net/Makefile b/sources/uboot-be550/drivers/net/Makefile new file mode 100644 index 00000000..c2ca605b --- /dev/null +++ b/sources/uboot-be550/drivers/net/Makefile @@ -0,0 +1,236 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ccflags-y += -I$(srctree)/board/qca/arm/ipq40xx -I$(srctree)/board/qca/arm/common +ccflags-y += -I$(srctree)/drivers/net/ipq_common + +ifeq ($(strip $(CONFIG_TP_EXT_PHY_RTL8251B)),y) +ccflags-y += -I$(srctree)/drivers/net/rtl8251b +endif + +ifeq ($(strip $(CONFIG_TP_EXT_SWITCH_RTL8367_ALL)),y) +ccflags-y += -I$(srctree)/drivers/net/rtl8367_common_V1_4_2 -I$(srctree)/drivers/net/rtl8367_common_V1_4_2/dal/ -I$(srctree)/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/ -I$(srctree)/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/ +EXTRA_CFLAGS += $(TP_SDK_CFLAGS) -DMDC_MDIO_OPERATION -DCONFIG_DAL_RTL8367D +endif + +ifeq ($(strip $(CONFIG_TP_EXT_PHY_RTL8221B)),y) +ccflags-y += -I$(srctree)/drivers/net/rtl8221b +endif + +ifeq ($(strip $(CONFIG_TP_EXT_SWITCH_RTL8372)),y) +ccflags-y += -I$(srctree)/drivers/net/rtl8372 -I$(srctree)/drivers/net/rtl8372/dal/ -I$(srctree)/drivers/net/rtl8372/dal/rtl8373/ +EXTRA_CFLAGS += $(TP_SDK_CFLAGS) -DCONFIG_TP_EXT_SWITCH_RTL8372 -DCONFIG_TP_EXT_SWITCH -DMDC_MDIO_OPERATION +endif + +obj-$(CONFIG_PPC4xx_EMAC) += 4xx_enet.o +obj-$(CONFIG_ALTERA_TSE) += altera_tse.o +obj-$(CONFIG_ARMADA100_FEC) += armada100_fec.o +obj-$(CONFIG_DRIVER_AT91EMAC) += at91_emac.o +obj-$(CONFIG_DRIVER_AX88180) += ax88180.o +obj-$(CONFIG_BCM_SF2_ETH) += bcm-sf2-eth.o +obj-$(CONFIG_BCM_SF2_ETH_GMAC) += bcm-sf2-eth-gmac.o +obj-$(CONFIG_BFIN_MAC) += bfin_mac.o +obj-$(CONFIG_CALXEDA_XGMAC) += calxedaxgmac.o +obj-$(CONFIG_CS8900) += cs8900.o +obj-$(CONFIG_TULIP) += dc2114x.o +obj-$(CONFIG_ETH_DESIGNWARE) += designware.o +obj-$(CONFIG_DRIVER_DM9000) += dm9000x.o +obj-$(CONFIG_DNET) += dnet.o +obj-$(CONFIG_E1000) += e1000.o +obj-$(CONFIG_E1000_SPI) += e1000_spi.o +obj-$(CONFIG_EEPRO100) += eepro100.o +obj-$(CONFIG_SUNXI_EMAC) += sunxi_emac.o +obj-$(CONFIG_ENC28J60) += enc28j60.o +obj-$(CONFIG_EP93XX) += ep93xx_eth.o +obj-$(CONFIG_ETHOC) += ethoc.o +obj-$(CONFIG_FEC_MXC) += fec_mxc.o +obj-$(CONFIG_FSLDMAFEC) += fsl_mcdmafec.o mcfmii.o +obj-$(CONFIG_FTGMAC100) += ftgmac100.o +obj-$(CONFIG_FTMAC110) += ftmac110.o +obj-$(CONFIG_FTMAC100) += ftmac100.o +obj-$(CONFIG_GRETH) += greth.o +obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_net.o +obj-$(CONFIG_KS8851_MLL) += ks8851_mll.o +obj-$(CONFIG_LAN91C96) += lan91c96.o +obj-$(CONFIG_LPC32XX_ETH) += lpc32xx_eth.o +obj-$(CONFIG_MACB) += macb.o +obj-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o +obj-$(CONFIG_MPC5xxx_FEC) += mpc5xxx_fec.o +obj-$(CONFIG_MPC512x_FEC) += mpc512x_fec.o +obj-$(CONFIG_MVGBE) += mvgbe.o +obj-$(CONFIG_MVNETA) += mvneta.o +obj-$(CONFIG_NATSEMI) += natsemi.o +obj-$(CONFIG_DRIVER_NE2000) += ne2000.o ne2000_base.o +obj-$(CONFIG_DRIVER_AX88796L) += ax88796.o ne2000_base.o +obj-$(CONFIG_NETCONSOLE) += netconsole.o +obj-$(CONFIG_NS8382X) += ns8382x.o +obj-$(CONFIG_PCH_GBE) += pch_gbe.o +obj-$(CONFIG_PCNET) += pcnet.o +obj-$(CONFIG_RTL8139) += rtl8139.o +obj-$(CONFIG_RTL8169) += rtl8169.o +obj-$(CONFIG_ETH_SANDBOX) += sandbox.o +obj-$(CONFIG_ETH_SANDBOX_RAW) += sandbox-raw.o +obj-$(CONFIG_SH_ETHER) += sh_eth.o +obj-$(CONFIG_SMC91111) += smc91111.o +obj-$(CONFIG_SMC911X) += smc911x.o +obj-$(CONFIG_DRIVER_TI_EMAC) += davinci_emac.o +obj-$(CONFIG_TSEC_ENET) += tsec.o fsl_mdio.o +obj-$(CONFIG_DRIVER_TI_CPSW) += cpsw.o +obj-$(CONFIG_FMAN_ENET) += fsl_mdio.o +obj-$(CONFIG_TSI108_ETH) += tsi108_eth.o +obj-$(CONFIG_ULI526X) += uli526x.o +obj-$(CONFIG_VSC7385_ENET) += vsc7385.o +obj-$(CONFIG_XILINX_AXIEMAC) += xilinx_axi_emac.o +obj-$(CONFIG_XILINX_EMACLITE) += xilinx_emaclite.o +obj-$(CONFIG_XILINX_LL_TEMAC) += xilinx_ll_temac.o xilinx_ll_temac_mdio.o \ + xilinx_ll_temac_fifo.o xilinx_ll_temac_sdma.o +obj-$(CONFIG_ZYNQ_GEM) += zynq_gem.o +obj-$(CONFIG_FSL_MC_ENET) += fsl-mc/ +obj-$(CONFIG_FSL_MC_ENET) += ldpaa_eth/ +obj-$(CONFIG_FSL_MEMAC) += fm/memac_phy.o +obj-$(CONFIG_VSC9953) += vsc9953.o +obj-$(CONFIG_IPQ40XX_EDMA) += ipq40xx/ipq40xx_edma_eth.o +obj-$(CONFIG_IPQ40XX_ESS) += ipq40xx/ipq40xx_ess_sw.o +obj-$(CONFIG_IPQ_SNPS_GMAC) += ipq806x/ipq_gmac_eth.o +obj-$(CONFIG_IPQ_SWITCH_ATHRS17) += ipq806x/athrs17_phy.o +obj-$(CONFIG_IPQ_SWITCH_QCA8511) += ipq806x/qca8511.o +obj-$(CONFIG_IPQ807X_EDMA) += ipq807x/ipq807x_edma.o +obj-$(CONFIG_IPQ807X_EDMA) += ipq807x/ipq807x_ppe.o +obj-$(CONFIG_IPQ807X_EDMA) += ipq807x/ipq807x_uniphy.o +obj-$(CONFIG_IPQ6018_EDMA) += ipq6018/ipq6018_edma.o +obj-$(CONFIG_IPQ6018_EDMA) += ipq6018/ipq6018_ppe.o +obj-$(CONFIG_IPQ6018_EDMA) += ipq6018/ipq6018_uniphy.o +obj-$(CONFIG_IPQ9574_EDMA) += ipq9574/ipq9574_ppe.o +obj-$(CONFIG_IPQ9574_EDMA) += ipq9574/ipq9574_uniphy.o +obj-$(CONFIG_IPQ9574_EDMA) += ipq9574/ipq9574_edma.o +obj-$(CONFIG_IPQ5018_GMAC) += ipq5018/ipq5018_gmac.o +obj-$(CONFIG_IPQ5018_GMAC) += ipq5018/ipq5018_uniphy.o +obj-$(CONFIG_IPQ5018_MDIO) += ipq5018/ipq5018_mdio.o +obj-$(CONFIG_IPQ5018_GMAC) += ipq5018/athrs17_phy.o +obj-$(CONFIG_IPQ5332_EDMA) += ipq5332/ipq5332_edma.o +obj-$(CONFIG_IPQ5332_EDMA) += ipq5332/ipq5332_ppe.o + +ifndef CONFIG_IPQ5332_RUMI +obj-$(CONFIG_IPQ5332_EDMA) += ipq5332/ipq5332_uniphy.o +endif + +ifeq ($(strip $(CONFIG_TP_EXT_SWITCH_RTL8367_ALL)),y) +obj-$(CONFIG_IPQ5332_EDMA) += rtl8367_common_V1_4_2/dal/rtl8367d/rtl8367d_asicdrv.o +obj-$(CONFIG_IPQ5332_EDMA) += rtl8367_common_V1_4_2/dal/rtl8367d/rtl8367d_smi.o +obj-$(CONFIG_IPQ5332_EDMA) += rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_acl.o +obj-$(CONFIG_IPQ5332_EDMA) += rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_cpu.o +obj-$(CONFIG_IPQ5332_EDMA) += rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_dot1x.o +obj-$(CONFIG_IPQ5332_EDMA) += rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_eee.o +obj-$(CONFIG_IPQ5332_EDMA) += rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_gpio.o +obj-$(CONFIG_IPQ5332_EDMA) += rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_igmp.o +obj-$(CONFIG_IPQ5332_EDMA) += rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_interrupt.o +obj-$(CONFIG_IPQ5332_EDMA) += rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_l2.o +obj-$(CONFIG_IPQ5332_EDMA) += rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_leaky.o +obj-$(CONFIG_IPQ5332_EDMA) += rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_led.o +obj-$(CONFIG_IPQ5332_EDMA) += rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_mapper.o +obj-$(CONFIG_IPQ5332_EDMA) += rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_mirror.o +obj-$(CONFIG_IPQ5332_EDMA) += rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_port.o +obj-$(CONFIG_IPQ5332_EDMA) += rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_qos.o +obj-$(CONFIG_IPQ5332_EDMA) += rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_rate.o +obj-$(CONFIG_IPQ5332_EDMA) += rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_rldp.o +obj-$(CONFIG_IPQ5332_EDMA) += rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_stat.o +obj-$(CONFIG_IPQ5332_EDMA) += rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_storm.o +obj-$(CONFIG_IPQ5332_EDMA) += rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_svlan.o +obj-$(CONFIG_IPQ5332_EDMA) += rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_switch.o +obj-$(CONFIG_IPQ5332_EDMA) += rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_trap.o +obj-$(CONFIG_IPQ5332_EDMA) += rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_trunk.o +obj-$(CONFIG_IPQ5332_EDMA) += rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_vlan.o + +obj-$(CONFIG_IPQ5332_EDMA) += rtl8367_common_V1_4_2/rtk_switch.o +obj-$(CONFIG_IPQ5332_EDMA) += rtl8367_common_V1_4_2/port.o +obj-$(CONFIG_IPQ5332_EDMA) += rtl8367_common_V1_4_2/vlan.o +obj-$(CONFIG_IPQ5332_EDMA) += rtl8367_common_V1_4_2/chip.o +obj-$(CONFIG_IPQ5332_EDMA) += rtl8367_common_V1_4_2/dal/dal_mgmt.o +endif + +ifeq ($(strip $(CONFIG_TP_EXT_SWITCH_RTL8372)),y) +obj-$(CONFIG_IPQ5332_EDMA) += rtl8372/dal/rtl8373/dal_rtl8373_switch.o +obj-$(CONFIG_IPQ5332_EDMA) += rtl8372/dal/rtl8373/dal_rtl8373_port.o +obj-$(CONFIG_IPQ5332_EDMA) += rtl8372/dal/rtl8373/dal_rtl8373_acl.o +obj-$(CONFIG_IPQ5332_EDMA) += rtl8372/dal/rtl8373/dal_rtl8373_fc.o +obj-$(CONFIG_IPQ5332_EDMA) += rtl8372/dal/rtl8373/dal_rtl8373_isolation.o +obj-$(CONFIG_IPQ5332_EDMA) += rtl8372/dal/rtl8373/rtl8373_asicdrv.o +obj-$(CONFIG_IPQ5332_EDMA) += rtl8372/dal/rtl8373/dal_rtl8373_mirror.o +obj-$(CONFIG_IPQ5332_EDMA) += rtl8372/dal/rtl8373/dal_rtl8373_rate.o +obj-$(CONFIG_IPQ5332_EDMA) += rtl8372/dal/rtl8373/dal_rtl8373_svlan.o +obj-$(CONFIG_IPQ5332_EDMA) += rtl8372/dal/rtl8373/rtl8373_regField_list.o +obj-$(CONFIG_IPQ5332_EDMA) += rtl8372/dal/rtl8373/dal_rtl8373_cpuTag.o +obj-$(CONFIG_IPQ5332_EDMA) += rtl8372/dal/rtl8373/dal_rtl8373_gpio.o +obj-$(CONFIG_IPQ5332_EDMA) += rtl8372/dal/rtl8373/dal_rtl8373_led.o +obj-$(CONFIG_IPQ5332_EDMA) += rtl8372/dal/rtl8373/dal_rtl8373_nic.o +obj-$(CONFIG_IPQ5332_EDMA) += rtl8372/dal/rtl8373/dal_rtl8373_rma.o +obj-$(CONFIG_IPQ5332_EDMA) += rtl8372/dal/rtl8373/dal_rtl8373_switch.o +obj-$(CONFIG_IPQ5332_EDMA) += rtl8372/dal/rtl8373/rtl8373_reg_list.o +obj-$(CONFIG_IPQ5332_EDMA) += rtl8372/dal/rtl8373/dal_rtl8373_dos.o +obj-$(CONFIG_IPQ5332_EDMA) += rtl8372/dal/rtl8373/dal_rtl8373_hsb.o +obj-$(CONFIG_IPQ5332_EDMA) += rtl8372/dal/rtl8373/dal_rtl8373_lut.o +obj-$(CONFIG_IPQ5332_EDMA) += rtl8372/dal/rtl8373/dal_rtl8373_parser.o +obj-$(CONFIG_IPQ5332_EDMA) += rtl8372/dal/rtl8373/dal_rtl8373_rtkpp.o +obj-$(CONFIG_IPQ5332_EDMA) += rtl8372/dal/rtl8373/dal_rtl8373_trunk.o +obj-$(CONFIG_IPQ5332_EDMA) += rtl8372/dal/rtl8373/rtl8373_smi.o +obj-$(CONFIG_IPQ5332_EDMA) += rtl8372/dal/rtl8373/dal_rtl8373_dot1x.o +obj-$(CONFIG_IPQ5332_EDMA) += rtl8372/dal/rtl8373/dal_rtl8373_i2c.o +obj-$(CONFIG_IPQ5332_EDMA) += rtl8372/dal/rtl8373/dal_rtl8373_macsec.o +obj-$(CONFIG_IPQ5332_EDMA) += rtl8372/dal/rtl8373/dal_rtl8373_sharemeter.o +obj-$(CONFIG_IPQ5332_EDMA) += rtl8372/dal/rtl8373/dal_rtl8373_vlan.o +obj-$(CONFIG_IPQ5332_EDMA) += rtl8372/dal/rtl8373/rtl8373_tableField_list.o +obj-$(CONFIG_IPQ5332_EDMA) += rtl8372/dal/rtl8373/dal_rtl8373_drv.o +obj-$(CONFIG_IPQ5332_EDMA) += rtl8372/dal/rtl8373/dal_rtl8373_igmp.o +obj-$(CONFIG_IPQ5332_EDMA) += rtl8372/dal/rtl8373/dal_rtl8373_mapper.o +obj-$(CONFIG_IPQ5332_EDMA) += rtl8372/dal/rtl8373/dal_rtl8373_ptp.o +obj-$(CONFIG_IPQ5332_EDMA) += rtl8372/dal/rtl8373/dal_rtl8373_storm.o +obj-$(CONFIG_IPQ5332_EDMA) += rtl8372/dal/rtl8373/dal_rtl8373_wol.o +obj-$(CONFIG_IPQ5332_EDMA) += rtl8372/dal/rtl8373/rtl8373_table_list.o +obj-$(CONFIG_IPQ5332_EDMA) += rtl8372/dal/rtl8373/dal_rtl8373_eee.o +obj-$(CONFIG_IPQ5332_EDMA) += rtl8372/dal/rtl8373/dal_rtl8373_interrupt.o +obj-$(CONFIG_IPQ5332_EDMA) += rtl8372/dal/rtl8373/dal_rtl8373_mib.o +obj-$(CONFIG_IPQ5332_EDMA) += rtl8372/dal/rtl8373/dal_rtl8373_qos.o +obj-$(CONFIG_IPQ5332_EDMA) += rtl8372/dal/rtl8373/dal_rtl8373_stp.o + +obj-$(CONFIG_IPQ5332_EDMA) += rtl8372/rtk_switch.o +obj-$(CONFIG_IPQ5332_EDMA) += rtl8372/port.o +obj-$(CONFIG_IPQ5332_EDMA) += rtl8372/vlan.o +obj-$(CONFIG_IPQ5332_EDMA) += rtl8372/chip.o +obj-$(CONFIG_IPQ5332_EDMA) += rtl8372/identify.o +obj-$(CONFIG_IPQ5332_EDMA) += rtl8372/dal/dal_mgmt.o +endif + +ifeq ($(strip $(CONFIG_TP_EXT_PHY_RTL8261B)),y) +obj-$(CONFIG_TP_EXT_PHY_RTL8261B) += ipq_common/rtl8261_phy.o +obj-$(CONFIG_TP_EXT_PHY_RTL8261B) += ipq_common/rtl8261_patch.o +endif + +ifeq ($(strip $(CONFIG_TP_EXT_PHY_RTL8251B)),y) +obj-$(CONFIG_TP_EXT_PHY_RTL8251B) += rtl8251b/nic_rtl8251b.o +obj-$(CONFIG_TP_EXT_PHY_RTL8251B) += rtl8251b/nic_rtl8251b_init.o +endif + +ifeq ($(strip $(CONFIG_TP_EXT_PHY_RTL8221B)),y) +obj-$(CONFIG_TP_EXT_PHY_RTL8221B) += rtl8221b/nic_rtl8226b.o +obj-$(CONFIG_TP_EXT_PHY_RTL8221B) += rtl8221b/nic_rtl8226b_init.o +endif + +obj-$(CONFIG_IPQ_MDIO) += ipq_common/ipq_mdio.o +obj-$(CONFIG_IPQ_QTI_BIT_BANGMII) += ipq_common/ipq_bitbangmii.o +obj-$(CONFIG_GEPHY) += ipq_common/ipq_gephy.o +obj-$(CONFIG_QCA8075_PHY) += ipq_common/ipq_qca8075.o +obj-$(CONFIG_QCA8084_PHY) += ipq_common/ipq_qca8084.o +obj-$(CONFIG_QCA8084_PHY) += ipq_common/ipq_qca8084_clk.o +obj-$(CONFIG_QCA8084_PHY) += ipq_common/ipq_qca8084_interface_ctrl.o +obj-$(CONFIG_ATHRS17C_SWITCH) += ipq_common/athrs17_phy.o +obj-$(CONFIG_IPQ9574_QCA8075_PHY) += ipq9574/ipq9574_qca8075.o +obj-$(CONFIG_QCA8033_PHY) += ipq_common/ipq_qca8033.o +obj-$(CONFIG_QCA8081_PHY) += ipq_common/ipq_qca8081.o +obj-$(CONFIG_IPQ_QCA_AQUANTIA_PHY) += ipq_common/ipq_aquantia_phy.o +obj-$(CONFIG_QCA_AQUANTIA_PHY) += ipq807x/ipq807x_aquantia_phy.o +obj-$(CONFIG_IPQ6018_QCA_AQUANTIA_PHY) += ipq6018/ipq6018_aquantia_phy.o +obj-$(CONFIG_IPQ9574_QCA_AQUANTIA_PHY) += ipq9574/ipq9574_aquantia_phy.o diff --git a/sources/uboot-be550/drivers/net/altera_tse.c b/sources/uboot-be550/drivers/net/altera_tse.c new file mode 100644 index 00000000..3eaa2706 --- /dev/null +++ b/sources/uboot-be550/drivers/net/altera_tse.c @@ -0,0 +1,714 @@ +/* + * Altera 10/100/1000 triple speed ethernet mac driver + * + * Copyright (C) 2008 Altera Corporation. + * Copyright (C) 2010 Thomas Chou + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "altera_tse.h" + +DECLARE_GLOBAL_DATA_PTR; + +static inline void alt_sgdma_construct_descriptor( + struct alt_sgdma_descriptor *desc, + struct alt_sgdma_descriptor *next, + void *read_addr, + void *write_addr, + u16 length_or_eop, + int generate_eop, + int read_fixed, + int write_fixed_or_sop) +{ + u8 val; + + /* + * Mark the "next" descriptor as "not" owned by hardware. This prevents + * The SGDMA controller from continuing to process the chain. + */ + next->descriptor_control = next->descriptor_control & + ~ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK; + + memset(desc, 0, sizeof(struct alt_sgdma_descriptor)); + desc->source = virt_to_phys(read_addr); + desc->destination = virt_to_phys(write_addr); + desc->next = virt_to_phys(next); + desc->bytes_to_transfer = length_or_eop; + + /* + * Set the descriptor control block as follows: + * - Set "owned by hardware" bit + * - Optionally set "generate EOP" bit + * - Optionally set the "read from fixed address" bit + * - Optionally set the "write to fixed address bit (which serves + * serves as a "generate SOP" control bit in memory-to-stream mode). + * - Set the 4-bit atlantic channel, if specified + * + * Note this step is performed after all other descriptor information + * has been filled out so that, if the controller already happens to be + * pointing at this descriptor, it will not run (via the "owned by + * hardware" bit) until all other descriptor has been set up. + */ + val = ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK; + if (generate_eop) + val |= ALT_SGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MSK; + if (read_fixed) + val |= ALT_SGDMA_DESCRIPTOR_CONTROL_READ_FIXED_ADDRESS_MSK; + if (write_fixed_or_sop) + val |= ALT_SGDMA_DESCRIPTOR_CONTROL_WRITE_FIXED_ADDRESS_MSK; + desc->descriptor_control = val; +} + +static int alt_sgdma_wait_transfer(struct alt_sgdma_registers *regs) +{ + int status; + ulong ctime; + + /* Wait for the descriptor (chain) to complete */ + ctime = get_timer(0); + while (1) { + status = readl(®s->status); + if (!(status & ALT_SGDMA_STATUS_BUSY_MSK)) + break; + if (get_timer(ctime) > ALT_TSE_SGDMA_BUSY_TIMEOUT) { + status = -ETIMEDOUT; + debug("sgdma timeout\n"); + break; + } + } + + /* Clear Run */ + writel(0, ®s->control); + /* Clear status */ + writel(0xff, ®s->status); + + return status; +} + +static int alt_sgdma_start_transfer(struct alt_sgdma_registers *regs, + struct alt_sgdma_descriptor *desc) +{ + u32 val; + + /* Point the controller at the descriptor */ + writel(virt_to_phys(desc), ®s->next_descriptor_pointer); + + /* + * Set up SGDMA controller to: + * - Disable interrupt generation + * - Run once a valid descriptor is written to controller + * - Stop on an error with any particular descriptor + */ + val = ALT_SGDMA_CONTROL_RUN_MSK | ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK; + writel(val, ®s->control); + + return 0; +} + +static void tse_adjust_link(struct altera_tse_priv *priv, + struct phy_device *phydev) +{ + struct alt_tse_mac *mac_dev = priv->mac_dev; + u32 refvar; + + if (!phydev->link) { + debug("%s: No link.\n", phydev->dev->name); + return; + } + + refvar = readl(&mac_dev->command_config); + + if (phydev->duplex) + refvar |= ALTERA_TSE_CMD_HD_ENA_MSK; + else + refvar &= ~ALTERA_TSE_CMD_HD_ENA_MSK; + + switch (phydev->speed) { + case 1000: + refvar |= ALTERA_TSE_CMD_ETH_SPEED_MSK; + refvar &= ~ALTERA_TSE_CMD_ENA_10_MSK; + break; + case 100: + refvar &= ~ALTERA_TSE_CMD_ETH_SPEED_MSK; + refvar &= ~ALTERA_TSE_CMD_ENA_10_MSK; + break; + case 10: + refvar &= ~ALTERA_TSE_CMD_ETH_SPEED_MSK; + refvar |= ALTERA_TSE_CMD_ENA_10_MSK; + break; + } + writel(refvar, &mac_dev->command_config); +} + +static int altera_tse_send_sgdma(struct udevice *dev, void *packet, int length) +{ + struct altera_tse_priv *priv = dev_get_priv(dev); + struct alt_sgdma_descriptor *tx_desc = priv->tx_desc; + + alt_sgdma_construct_descriptor( + tx_desc, + tx_desc + 1, + packet, /* read addr */ + NULL, /* write addr */ + length, /* length or EOP ,will change for each tx */ + 1, /* gen eop */ + 0, /* read fixed */ + 1 /* write fixed or sop */ + ); + + /* send the packet */ + alt_sgdma_start_transfer(priv->sgdma_tx, tx_desc); + alt_sgdma_wait_transfer(priv->sgdma_tx); + debug("sent %d bytes\n", tx_desc->actual_bytes_transferred); + + return tx_desc->actual_bytes_transferred; +} + +static int altera_tse_recv_sgdma(struct udevice *dev, int flags, + uchar **packetp) +{ + struct altera_tse_priv *priv = dev_get_priv(dev); + struct alt_sgdma_descriptor *rx_desc = priv->rx_desc; + int packet_length; + + if (rx_desc->descriptor_status & + ALT_SGDMA_DESCRIPTOR_STATUS_TERMINATED_BY_EOP_MSK) { + alt_sgdma_wait_transfer(priv->sgdma_rx); + packet_length = rx_desc->actual_bytes_transferred; + debug("recv %d bytes\n", packet_length); + *packetp = priv->rx_buf; + + return packet_length; + } + + return -EAGAIN; +} + +static int altera_tse_free_pkt_sgdma(struct udevice *dev, uchar *packet, + int length) +{ + struct altera_tse_priv *priv = dev_get_priv(dev); + struct alt_sgdma_descriptor *rx_desc = priv->rx_desc; + + alt_sgdma_construct_descriptor( + rx_desc, + rx_desc + 1, + NULL, /* read addr */ + priv->rx_buf, /* write addr */ + 0, /* length or EOP */ + 0, /* gen eop */ + 0, /* read fixed */ + 0 /* write fixed or sop */ + ); + + /* setup the sgdma */ + alt_sgdma_start_transfer(priv->sgdma_rx, rx_desc); + debug("recv setup\n"); + + return 0; +} + +static void altera_tse_stop_mac(struct altera_tse_priv *priv) +{ + struct alt_tse_mac *mac_dev = priv->mac_dev; + u32 status; + ulong ctime; + + /* reset the mac */ + writel(ALTERA_TSE_CMD_SW_RESET_MSK, &mac_dev->command_config); + ctime = get_timer(0); + while (1) { + status = readl(&mac_dev->command_config); + if (!(status & ALTERA_TSE_CMD_SW_RESET_MSK)) + break; + if (get_timer(ctime) > ALT_TSE_SW_RESET_TIMEOUT) { + debug("Reset mac timeout\n"); + break; + } + } +} + +static void altera_tse_stop_sgdma(struct udevice *dev) +{ + struct altera_tse_priv *priv = dev_get_priv(dev); + struct alt_sgdma_registers *rx_sgdma = priv->sgdma_rx; + struct alt_sgdma_registers *tx_sgdma = priv->sgdma_tx; + struct alt_sgdma_descriptor *rx_desc = priv->rx_desc; + int ret; + + /* clear rx desc & wait for sgdma to complete */ + rx_desc->descriptor_control = 0; + writel(0, &rx_sgdma->control); + ret = alt_sgdma_wait_transfer(rx_sgdma); + if (ret == -ETIMEDOUT) + writel(ALT_SGDMA_CONTROL_SOFTWARERESET_MSK, + &rx_sgdma->control); + + writel(0, &tx_sgdma->control); + ret = alt_sgdma_wait_transfer(tx_sgdma); + if (ret == -ETIMEDOUT) + writel(ALT_SGDMA_CONTROL_SOFTWARERESET_MSK, + &tx_sgdma->control); +} + +static void msgdma_reset(struct msgdma_csr *csr) +{ + u32 status; + ulong ctime; + + /* Reset mSGDMA */ + writel(MSGDMA_CSR_STAT_MASK, &csr->status); + writel(MSGDMA_CSR_CTL_RESET, &csr->control); + ctime = get_timer(0); + while (1) { + status = readl(&csr->status); + if (!(status & MSGDMA_CSR_STAT_RESETTING)) + break; + if (get_timer(ctime) > ALT_TSE_SW_RESET_TIMEOUT) { + debug("Reset msgdma timeout\n"); + break; + } + } + /* Clear status */ + writel(MSGDMA_CSR_STAT_MASK, &csr->status); +} + +static u32 msgdma_wait(struct msgdma_csr *csr) +{ + u32 status; + ulong ctime; + + /* Wait for the descriptor to complete */ + ctime = get_timer(0); + while (1) { + status = readl(&csr->status); + if (!(status & MSGDMA_CSR_STAT_BUSY)) + break; + if (get_timer(ctime) > ALT_TSE_SGDMA_BUSY_TIMEOUT) { + debug("sgdma timeout\n"); + break; + } + } + /* Clear status */ + writel(MSGDMA_CSR_STAT_MASK, &csr->status); + + return status; +} + +static int altera_tse_send_msgdma(struct udevice *dev, void *packet, + int length) +{ + struct altera_tse_priv *priv = dev_get_priv(dev); + struct msgdma_extended_desc *desc = priv->tx_desc; + u32 tx_buf = virt_to_phys(packet); + u32 status; + + writel(tx_buf, &desc->read_addr_lo); + writel(0, &desc->read_addr_hi); + writel(0, &desc->write_addr_lo); + writel(0, &desc->write_addr_hi); + writel(length, &desc->len); + writel(0, &desc->burst_seq_num); + writel(MSGDMA_DESC_TX_STRIDE, &desc->stride); + writel(MSGDMA_DESC_CTL_TX_SINGLE, &desc->control); + status = msgdma_wait(priv->sgdma_tx); + debug("sent %d bytes, status %08x\n", length, status); + + return 0; +} + +static int altera_tse_recv_msgdma(struct udevice *dev, int flags, + uchar **packetp) +{ + struct altera_tse_priv *priv = dev_get_priv(dev); + struct msgdma_csr *csr = priv->sgdma_rx; + struct msgdma_response *resp = priv->rx_resp; + u32 level, length, status; + + level = readl(&csr->resp_fill_level); + if (level & 0xffff) { + length = readl(&resp->bytes_transferred); + status = readl(&resp->status); + debug("recv %d bytes, status %08x\n", length, status); + *packetp = priv->rx_buf; + + return length; + } + + return -EAGAIN; +} + +static int altera_tse_free_pkt_msgdma(struct udevice *dev, uchar *packet, + int length) +{ + struct altera_tse_priv *priv = dev_get_priv(dev); + struct msgdma_extended_desc *desc = priv->rx_desc; + u32 rx_buf = virt_to_phys(priv->rx_buf); + + writel(0, &desc->read_addr_lo); + writel(0, &desc->read_addr_hi); + writel(rx_buf, &desc->write_addr_lo); + writel(0, &desc->write_addr_hi); + writel(PKTSIZE_ALIGN, &desc->len); + writel(0, &desc->burst_seq_num); + writel(MSGDMA_DESC_RX_STRIDE, &desc->stride); + writel(MSGDMA_DESC_CTL_RX_SINGLE, &desc->control); + debug("recv setup\n"); + + return 0; +} + +static void altera_tse_stop_msgdma(struct udevice *dev) +{ + struct altera_tse_priv *priv = dev_get_priv(dev); + + msgdma_reset(priv->sgdma_rx); + msgdma_reset(priv->sgdma_tx); +} + +static int tse_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) +{ + struct altera_tse_priv *priv = bus->priv; + struct alt_tse_mac *mac_dev = priv->mac_dev; + u32 value; + + /* set mdio address */ + writel(addr, &mac_dev->mdio_phy1_addr); + /* get the data */ + value = readl(&mac_dev->mdio_phy1[reg]); + + return value & 0xffff; +} + +static int tse_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, + u16 val) +{ + struct altera_tse_priv *priv = bus->priv; + struct alt_tse_mac *mac_dev = priv->mac_dev; + + /* set mdio address */ + writel(addr, &mac_dev->mdio_phy1_addr); + /* set the data */ + writel(val, &mac_dev->mdio_phy1[reg]); + + return 0; +} + +static int tse_mdio_init(const char *name, struct altera_tse_priv *priv) +{ + struct mii_dev *bus = mdio_alloc(); + + if (!bus) { + printf("Failed to allocate MDIO bus\n"); + return -ENOMEM; + } + + bus->read = tse_mdio_read; + bus->write = tse_mdio_write; + snprintf(bus->name, sizeof(bus->name), name); + + bus->priv = (void *)priv; + + return mdio_register(bus); +} + +static int tse_phy_init(struct altera_tse_priv *priv, void *dev) +{ + struct phy_device *phydev; + unsigned int mask = 0xffffffff; + + if (priv->phyaddr) + mask = 1 << priv->phyaddr; + + phydev = phy_find_by_mask(priv->bus, mask, priv->interface); + if (!phydev) + return -ENODEV; + + phy_connect_dev(phydev, dev); + + phydev->supported &= PHY_GBIT_FEATURES; + phydev->advertising = phydev->supported; + + priv->phydev = phydev; + phy_config(phydev); + + return 0; +} + +static int altera_tse_write_hwaddr(struct udevice *dev) +{ + struct altera_tse_priv *priv = dev_get_priv(dev); + struct alt_tse_mac *mac_dev = priv->mac_dev; + struct eth_pdata *pdata = dev_get_platdata(dev); + u8 *hwaddr = pdata->enetaddr; + u32 mac_lo, mac_hi; + + mac_lo = (hwaddr[3] << 24) | (hwaddr[2] << 16) | + (hwaddr[1] << 8) | hwaddr[0]; + mac_hi = (hwaddr[5] << 8) | hwaddr[4]; + debug("Set MAC address to 0x%04x%08x\n", mac_hi, mac_lo); + + writel(mac_lo, &mac_dev->mac_addr_0); + writel(mac_hi, &mac_dev->mac_addr_1); + writel(mac_lo, &mac_dev->supp_mac_addr_0_0); + writel(mac_hi, &mac_dev->supp_mac_addr_0_1); + writel(mac_lo, &mac_dev->supp_mac_addr_1_0); + writel(mac_hi, &mac_dev->supp_mac_addr_1_1); + writel(mac_lo, &mac_dev->supp_mac_addr_2_0); + writel(mac_hi, &mac_dev->supp_mac_addr_2_1); + writel(mac_lo, &mac_dev->supp_mac_addr_3_0); + writel(mac_hi, &mac_dev->supp_mac_addr_3_1); + + return 0; +} + +static int altera_tse_send(struct udevice *dev, void *packet, int length) +{ + struct altera_tse_priv *priv = dev_get_priv(dev); + unsigned long tx_buf = (unsigned long)packet; + + flush_dcache_range(tx_buf, tx_buf + length); + + return priv->ops->send(dev, packet, length); +} + +static int altera_tse_recv(struct udevice *dev, int flags, uchar **packetp) +{ + struct altera_tse_priv *priv = dev_get_priv(dev); + + return priv->ops->recv(dev, flags, packetp); +} + +static int altera_tse_free_pkt(struct udevice *dev, uchar *packet, + int length) +{ + struct altera_tse_priv *priv = dev_get_priv(dev); + unsigned long rx_buf = (unsigned long)priv->rx_buf; + + invalidate_dcache_range(rx_buf, rx_buf + PKTSIZE_ALIGN); + + return priv->ops->free_pkt(dev, packet, length); +} + +static void altera_tse_stop(struct udevice *dev) +{ + struct altera_tse_priv *priv = dev_get_priv(dev); + + priv->ops->stop(dev); + altera_tse_stop_mac(priv); +} + +static int altera_tse_start(struct udevice *dev) +{ + struct altera_tse_priv *priv = dev_get_priv(dev); + struct alt_tse_mac *mac_dev = priv->mac_dev; + u32 val; + int ret; + + /* need to create sgdma */ + debug("Configuring rx desc\n"); + altera_tse_free_pkt(dev, priv->rx_buf, PKTSIZE_ALIGN); + /* start TSE */ + debug("Configuring TSE Mac\n"); + /* Initialize MAC registers */ + writel(PKTSIZE_ALIGN, &mac_dev->max_frame_length); + writel(priv->rx_fifo_depth - 16, &mac_dev->rx_sel_empty_threshold); + writel(0, &mac_dev->rx_sel_full_threshold); + writel(priv->tx_fifo_depth - 16, &mac_dev->tx_sel_empty_threshold); + writel(0, &mac_dev->tx_sel_full_threshold); + writel(8, &mac_dev->rx_almost_empty_threshold); + writel(8, &mac_dev->rx_almost_full_threshold); + writel(8, &mac_dev->tx_almost_empty_threshold); + writel(3, &mac_dev->tx_almost_full_threshold); + + /* NO Shift */ + writel(0, &mac_dev->rx_cmd_stat); + writel(0, &mac_dev->tx_cmd_stat); + + /* enable MAC */ + val = ALTERA_TSE_CMD_TX_ENA_MSK | ALTERA_TSE_CMD_RX_ENA_MSK; + writel(val, &mac_dev->command_config); + + /* Start up the PHY */ + ret = phy_startup(priv->phydev); + if (ret) { + debug("Could not initialize PHY %s\n", + priv->phydev->dev->name); + return ret; + } + + tse_adjust_link(priv, priv->phydev); + + if (!priv->phydev->link) + return -EIO; + + return 0; +} + +static const struct tse_ops tse_sgdma_ops = { + .send = altera_tse_send_sgdma, + .recv = altera_tse_recv_sgdma, + .free_pkt = altera_tse_free_pkt_sgdma, + .stop = altera_tse_stop_sgdma, +}; + +static const struct tse_ops tse_msgdma_ops = { + .send = altera_tse_send_msgdma, + .recv = altera_tse_recv_msgdma, + .free_pkt = altera_tse_free_pkt_msgdma, + .stop = altera_tse_stop_msgdma, +}; + +static int altera_tse_probe(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + struct altera_tse_priv *priv = dev_get_priv(dev); + void *blob = (void *)gd->fdt_blob; + int node = dev->of_offset; + const char *list, *end; + const fdt32_t *cell; + void *base, *desc_mem = NULL; + unsigned long addr, size; + int parent, addrc, sizec; + int len, idx; + int ret; + + priv->dma_type = dev_get_driver_data(dev); + if (priv->dma_type == ALT_SGDMA) + priv->ops = &tse_sgdma_ops; + else + priv->ops = &tse_msgdma_ops; + /* + * decode regs. there are multiple reg tuples, and they need to + * match with reg-names. + */ + parent = fdt_parent_offset(blob, node); + of_bus_default_count_cells(blob, parent, &addrc, &sizec); + list = fdt_getprop(blob, node, "reg-names", &len); + if (!list) + return -ENOENT; + end = list + len; + cell = fdt_getprop(blob, node, "reg", &len); + if (!cell) + return -ENOENT; + idx = 0; + while (list < end) { + addr = fdt_translate_address((void *)blob, + node, cell + idx); + size = fdt_addr_to_cpu(cell[idx + addrc]); + base = map_physmem(addr, size, MAP_NOCACHE); + len = strlen(list); + if (strcmp(list, "control_port") == 0) + priv->mac_dev = base; + else if (strcmp(list, "rx_csr") == 0) + priv->sgdma_rx = base; + else if (strcmp(list, "rx_desc") == 0) + priv->rx_desc = base; + else if (strcmp(list, "rx_resp") == 0) + priv->rx_resp = base; + else if (strcmp(list, "tx_csr") == 0) + priv->sgdma_tx = base; + else if (strcmp(list, "tx_desc") == 0) + priv->tx_desc = base; + else if (strcmp(list, "s1") == 0) + desc_mem = base; + idx += addrc + sizec; + list += (len + 1); + } + /* decode fifo depth */ + priv->rx_fifo_depth = fdtdec_get_int(blob, node, + "rx-fifo-depth", 0); + priv->tx_fifo_depth = fdtdec_get_int(blob, node, + "tx-fifo-depth", 0); + /* decode phy */ + addr = fdtdec_get_int(blob, node, + "phy-handle", 0); + addr = fdt_node_offset_by_phandle(blob, addr); + priv->phyaddr = fdtdec_get_int(blob, addr, + "reg", 0); + /* init desc */ + if (priv->dma_type == ALT_SGDMA) { + len = sizeof(struct alt_sgdma_descriptor) * 4; + if (!desc_mem) { + desc_mem = dma_alloc_coherent(len, &addr); + if (!desc_mem) + return -ENOMEM; + } + memset(desc_mem, 0, len); + priv->tx_desc = desc_mem; + priv->rx_desc = priv->tx_desc + + 2 * sizeof(struct alt_sgdma_descriptor); + } + /* allocate recv packet buffer */ + priv->rx_buf = malloc_cache_aligned(PKTSIZE_ALIGN); + if (!priv->rx_buf) + return -ENOMEM; + + /* stop controller */ + debug("Reset TSE & SGDMAs\n"); + altera_tse_stop(dev); + + /* start the phy */ + priv->interface = pdata->phy_interface; + tse_mdio_init(dev->name, priv); + priv->bus = miiphy_get_dev_by_name(dev->name); + + ret = tse_phy_init(priv, dev); + + return ret; +} + +static int altera_tse_ofdata_to_platdata(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + const char *phy_mode; + + pdata->phy_interface = -1; + phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL); + if (phy_mode) + pdata->phy_interface = phy_get_interface_by_name(phy_mode); + if (pdata->phy_interface == -1) { + debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); + return -EINVAL; + } + + return 0; +} + +static const struct eth_ops altera_tse_ops = { + .start = altera_tse_start, + .send = altera_tse_send, + .recv = altera_tse_recv, + .free_pkt = altera_tse_free_pkt, + .stop = altera_tse_stop, + .write_hwaddr = altera_tse_write_hwaddr, +}; + +static const struct udevice_id altera_tse_ids[] = { + { .compatible = "altr,tse-msgdma-1.0", .data = ALT_MSGDMA }, + { .compatible = "altr,tse-1.0", .data = ALT_SGDMA }, + {} +}; + +U_BOOT_DRIVER(altera_tse) = { + .name = "altera_tse", + .id = UCLASS_ETH, + .of_match = altera_tse_ids, + .ops = &altera_tse_ops, + .ofdata_to_platdata = altera_tse_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct eth_pdata), + .priv_auto_alloc_size = sizeof(struct altera_tse_priv), + .probe = altera_tse_probe, +}; diff --git a/sources/uboot-be550/drivers/net/altera_tse.h b/sources/uboot-be550/drivers/net/altera_tse.h new file mode 100644 index 00000000..2b1af814 --- /dev/null +++ b/sources/uboot-be550/drivers/net/altera_tse.h @@ -0,0 +1,231 @@ +/* + * Altera 10/100/1000 triple speed ethernet mac + * + * Copyright (C) 2008 Altera Corporation. + * Copyright (C) 2010 Thomas Chou + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef _ALTERA_TSE_H_ +#define _ALTERA_TSE_H_ + +#define __packed_1_ __packed __aligned(1) + +/* dma type */ +#define ALT_SGDMA 0 +#define ALT_MSGDMA 1 + +/* SGDMA Stuff */ +#define ALT_SGDMA_STATUS_BUSY_MSK BIT(4) + +#define ALT_SGDMA_CONTROL_RUN_MSK BIT(5) +#define ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK BIT(6) +#define ALT_SGDMA_CONTROL_SOFTWARERESET_MSK BIT(16) + +/* + * Descriptor control bit masks & offsets + * + * Note: The control byte physically occupies bits [31:24] in memory. + * The following bit-offsets are expressed relative to the LSB of + * the control register bitfield. + */ +#define ALT_SGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MSK BIT(0) +#define ALT_SGDMA_DESCRIPTOR_CONTROL_READ_FIXED_ADDRESS_MSK BIT(1) +#define ALT_SGDMA_DESCRIPTOR_CONTROL_WRITE_FIXED_ADDRESS_MSK BIT(2) +#define ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK BIT(7) + +/* + * Descriptor status bit masks & offsets + * + * Note: The status byte physically occupies bits [23:16] in memory. + * The following bit-offsets are expressed relative to the LSB of + * the status register bitfield. + */ +#define ALT_SGDMA_DESCRIPTOR_STATUS_TERMINATED_BY_EOP_MSK BIT(7) + +/* + * The SGDMA controller buffer descriptor allocates + * 64 bits for each address. To support ANSI C, the + * struct implementing a descriptor places 32-bits + * of padding directly above each address; each pad must + * be cleared when initializing a descriptor. + */ + +/* + * Buffer Descriptor data structure + * + */ +struct alt_sgdma_descriptor { + u32 source; /* the address of data to be read. */ + u32 source_pad; + + u32 destination; /* the address to write data */ + u32 destination_pad; + + u32 next; /* the next descriptor in the list. */ + u32 next_pad; + + u16 bytes_to_transfer; /* the number of bytes to transfer */ + u8 read_burst; + u8 write_burst; + + u16 actual_bytes_transferred;/* bytes transferred by DMA */ + u8 descriptor_status; + u8 descriptor_control; + +} __packed_1_; + +/* SG-DMA Control/Status Slave registers map */ + +struct alt_sgdma_registers { + u32 status; + u32 status_pad[3]; + u32 control; + u32 control_pad[3]; + u32 next_descriptor_pointer; + u32 descriptor_pad[3]; +}; + +/* mSGDMA Stuff */ + +/* mSGDMA extended descriptor format */ +struct msgdma_extended_desc { + u32 read_addr_lo; /* data buffer source address low bits */ + u32 write_addr_lo; /* data buffer destination address low bits */ + u32 len; + u32 burst_seq_num; + u32 stride; + u32 read_addr_hi; /* data buffer source address high bits */ + u32 write_addr_hi; /* data buffer destination address high bits */ + u32 control; /* characteristics of the transfer */ +}; + +/* mSGDMA descriptor control field bit definitions */ +#define MSGDMA_DESC_CTL_GEN_SOP BIT(8) +#define MSGDMA_DESC_CTL_GEN_EOP BIT(9) +#define MSGDMA_DESC_CTL_END_ON_EOP BIT(12) +#define MSGDMA_DESC_CTL_END_ON_LEN BIT(13) +#define MSGDMA_DESC_CTL_GO BIT(31) + +/* Tx buffer control flags */ +#define MSGDMA_DESC_CTL_TX_SINGLE (MSGDMA_DESC_CTL_GEN_SOP | \ + MSGDMA_DESC_CTL_GEN_EOP | \ + MSGDMA_DESC_CTL_GO) + +#define MSGDMA_DESC_CTL_RX_SINGLE (MSGDMA_DESC_CTL_END_ON_EOP | \ + MSGDMA_DESC_CTL_END_ON_LEN | \ + MSGDMA_DESC_CTL_GO) + +/* mSGDMA extended descriptor stride definitions */ +#define MSGDMA_DESC_TX_STRIDE 0x00010001 +#define MSGDMA_DESC_RX_STRIDE 0x00010001 + +/* mSGDMA dispatcher control and status register map */ +struct msgdma_csr { + u32 status; /* Read/Clear */ + u32 control; /* Read/Write */ + u32 rw_fill_level; + u32 resp_fill_level; /* bit 15:0 */ + u32 rw_seq_num; + u32 pad[3]; /* reserved */ +}; + +/* mSGDMA CSR status register bit definitions */ +#define MSGDMA_CSR_STAT_BUSY BIT(0) +#define MSGDMA_CSR_STAT_RESETTING BIT(6) +#define MSGDMA_CSR_STAT_MASK 0x3FF + +/* mSGDMA CSR control register bit definitions */ +#define MSGDMA_CSR_CTL_RESET BIT(1) + +/* mSGDMA response register map */ +struct msgdma_response { + u32 bytes_transferred; + u32 status; +}; + +/* TSE Stuff */ +#define ALTERA_TSE_CMD_TX_ENA_MSK BIT(0) +#define ALTERA_TSE_CMD_RX_ENA_MSK BIT(1) +#define ALTERA_TSE_CMD_ETH_SPEED_MSK BIT(3) +#define ALTERA_TSE_CMD_HD_ENA_MSK BIT(10) +#define ALTERA_TSE_CMD_SW_RESET_MSK BIT(13) +#define ALTERA_TSE_CMD_ENA_10_MSK BIT(25) + +#define ALT_TSE_SW_RESET_TIMEOUT (3 * CONFIG_SYS_HZ) +#define ALT_TSE_SGDMA_BUSY_TIMEOUT (3 * CONFIG_SYS_HZ) + +/* MAC register Space */ + +struct alt_tse_mac { + u32 megacore_revision; + u32 scratch_pad; + u32 command_config; + u32 mac_addr_0; + u32 mac_addr_1; + u32 max_frame_length; + u32 pause_quanta; + u32 rx_sel_empty_threshold; + u32 rx_sel_full_threshold; + u32 tx_sel_empty_threshold; + u32 tx_sel_full_threshold; + u32 rx_almost_empty_threshold; + u32 rx_almost_full_threshold; + u32 tx_almost_empty_threshold; + u32 tx_almost_full_threshold; + u32 mdio_phy0_addr; + u32 mdio_phy1_addr; + + u32 reserved1[0x29]; + + /*FIFO control register. */ + u32 tx_cmd_stat; + u32 rx_cmd_stat; + + u32 reserved2[0x44]; + + /*Registers 0 to 31 within PHY device 0/1 */ + u32 mdio_phy0[0x20]; + u32 mdio_phy1[0x20]; + + /*4 Supplemental MAC Addresses */ + u32 supp_mac_addr_0_0; + u32 supp_mac_addr_0_1; + u32 supp_mac_addr_1_0; + u32 supp_mac_addr_1_1; + u32 supp_mac_addr_2_0; + u32 supp_mac_addr_2_1; + u32 supp_mac_addr_3_0; + u32 supp_mac_addr_3_1; + + u32 reserved3[0x38]; +}; + +struct tse_ops { + int (*send)(struct udevice *dev, void *packet, int length); + int (*recv)(struct udevice *dev, int flags, uchar **packetp); + int (*free_pkt)(struct udevice *dev, uchar *packet, int length); + void (*stop)(struct udevice *dev); +}; + +struct altera_tse_priv { + struct alt_tse_mac *mac_dev; + void *sgdma_rx; + void *sgdma_tx; + unsigned int rx_fifo_depth; + unsigned int tx_fifo_depth; + void *rx_desc; + void *tx_desc; + void *rx_resp; + unsigned char *rx_buf; + unsigned int phyaddr; + unsigned int interface; + struct phy_device *phydev; + struct mii_dev *bus; + const struct tse_ops *ops; + int dma_type; +}; + +#endif /* _ALTERA_TSE_H_ */ diff --git a/sources/uboot-be550/drivers/net/armada100_fec.c b/sources/uboot-be550/drivers/net/armada100_fec.c new file mode 100644 index 00000000..e6a62525 --- /dev/null +++ b/sources/uboot-be550/drivers/net/armada100_fec.c @@ -0,0 +1,727 @@ +/* + * (C) Copyright 2011 + * eInfochips Ltd. + * Written-by: Ajay Bhargav + * + * (C) Copyright 2010 + * Marvell Semiconductor + * Contributor: Mahavir Jain + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "armada100_fec.h" + +#define PHY_ADR_REQ 0xFF /* Magic number to read/write PHY address */ + +#ifdef DEBUG +static int eth_dump_regs(struct eth_device *dev) +{ + struct armdfec_device *darmdfec = to_darmdfec(dev); + struct armdfec_reg *regs = darmdfec->regs; + unsigned int i = 0; + + printf("\noffset: phy_adr, value: 0x%x\n", readl(®s->phyadr)); + printf("offset: smi, value: 0x%x\n", readl(®s->smi)); + for (i = 0x400; i <= 0x4e4; i += 4) + printf("offset: 0x%x, value: 0x%x\n", + i, readl(ARMD1_FEC_BASE + i)); + return 0; +} +#endif + +static int armdfec_phy_timeout(u32 *reg, u32 flag, int cond) +{ + u32 timeout = PHY_WAIT_ITERATIONS; + u32 reg_val; + + while (--timeout) { + reg_val = readl(reg); + if (cond && (reg_val & flag)) + break; + else if (!cond && !(reg_val & flag)) + break; + udelay(PHY_WAIT_MICRO_SECONDS); + } + return !timeout; +} + +static int smi_reg_read(const char *devname, u8 phy_addr, u8 phy_reg, + u16 *value) +{ + struct eth_device *dev = eth_get_dev_by_name(devname); + struct armdfec_device *darmdfec = to_darmdfec(dev); + struct armdfec_reg *regs = darmdfec->regs; + u32 val; + + if (phy_addr == PHY_ADR_REQ && phy_reg == PHY_ADR_REQ) { + val = readl(®s->phyadr); + *value = val & 0x1f; + return 0; + } + + /* check parameters */ + if (phy_addr > PHY_MASK) { + printf("ARMD100 FEC: (%s) Invalid phy address: 0x%X\n", + __func__, phy_addr); + return -EINVAL; + } + if (phy_reg > PHY_MASK) { + printf("ARMD100 FEC: (%s) Invalid register offset: 0x%X\n", + __func__, phy_reg); + return -EINVAL; + } + + /* wait for the SMI register to become available */ + if (armdfec_phy_timeout(®s->smi, SMI_BUSY, false)) { + printf("ARMD100 FEC: (%s) PHY busy timeout\n", __func__); + return -1; + } + + writel((phy_addr << 16) | (phy_reg << 21) | SMI_OP_R, ®s->smi); + + /* now wait for the data to be valid */ + if (armdfec_phy_timeout(®s->smi, SMI_R_VALID, true)) { + val = readl(®s->smi); + printf("ARMD100 FEC: (%s) PHY Read timeout, val=0x%x\n", + __func__, val); + return -1; + } + val = readl(®s->smi); + *value = val & 0xffff; + + return 0; +} + +static int smi_reg_write(const char *devname, + u8 phy_addr, u8 phy_reg, u16 value) +{ + struct eth_device *dev = eth_get_dev_by_name(devname); + struct armdfec_device *darmdfec = to_darmdfec(dev); + struct armdfec_reg *regs = darmdfec->regs; + + if (phy_addr == PHY_ADR_REQ && phy_reg == PHY_ADR_REQ) { + clrsetbits_le32(®s->phyadr, 0x1f, value & 0x1f); + return 0; + } + + /* check parameters */ + if (phy_addr > PHY_MASK) { + printf("ARMD100 FEC: (%s) Invalid phy address\n", __func__); + return -EINVAL; + } + if (phy_reg > PHY_MASK) { + printf("ARMD100 FEC: (%s) Invalid register offset\n", __func__); + return -EINVAL; + } + + /* wait for the SMI register to become available */ + if (armdfec_phy_timeout(®s->smi, SMI_BUSY, false)) { + printf("ARMD100 FEC: (%s) PHY busy timeout\n", __func__); + return -1; + } + + writel((phy_addr << 16) | (phy_reg << 21) | SMI_OP_W | (value & 0xffff), + ®s->smi); + return 0; +} + +/* + * Abort any transmit and receive operations and put DMA + * in idle state. AT and AR bits are cleared upon entering + * in IDLE state. So poll those bits to verify operation. + */ +static void abortdma(struct eth_device *dev) +{ + struct armdfec_device *darmdfec = to_darmdfec(dev); + struct armdfec_reg *regs = darmdfec->regs; + int delay; + int maxretries = 40; + u32 tmp; + + while (--maxretries) { + writel(SDMA_CMD_AR | SDMA_CMD_AT, ®s->sdma_cmd); + udelay(100); + + delay = 10; + while (--delay) { + tmp = readl(®s->sdma_cmd); + if (!(tmp & (SDMA_CMD_AR | SDMA_CMD_AT))) + break; + udelay(10); + } + if (delay) + break; + } + + if (!maxretries) + printf("ARMD100 FEC: (%s) DMA Stuck\n", __func__); +} + +static inline u32 nibble_swapping_32_bit(u32 x) +{ + return ((x & 0xf0f0f0f0) >> 4) | ((x & 0x0f0f0f0f) << 4); +} + +static inline u32 nibble_swapping_16_bit(u32 x) +{ + return ((x & 0x0000f0f0) >> 4) | ((x & 0x00000f0f) << 4); +} + +static inline u32 flip_4_bits(u32 x) +{ + return ((x & 0x01) << 3) | ((x & 0x002) << 1) + | ((x & 0x04) >> 1) | ((x & 0x008) >> 3); +} + +/* + * This function will calculate the hash function of the address. + * depends on the hash mode and hash size. + * Inputs + * mach - the 2 most significant bytes of the MAC address. + * macl - the 4 least significant bytes of the MAC address. + * Outputs + * return the calculated entry. + */ +static u32 hash_function(u32 mach, u32 macl) +{ + u32 hashresult; + u32 addrh; + u32 addrl; + u32 addr0; + u32 addr1; + u32 addr2; + u32 addr3; + u32 addrhswapped; + u32 addrlswapped; + + addrh = nibble_swapping_16_bit(mach); + addrl = nibble_swapping_32_bit(macl); + + addrhswapped = flip_4_bits(addrh & 0xf) + + ((flip_4_bits((addrh >> 4) & 0xf)) << 4) + + ((flip_4_bits((addrh >> 8) & 0xf)) << 8) + + ((flip_4_bits((addrh >> 12) & 0xf)) << 12); + + addrlswapped = flip_4_bits(addrl & 0xf) + + ((flip_4_bits((addrl >> 4) & 0xf)) << 4) + + ((flip_4_bits((addrl >> 8) & 0xf)) << 8) + + ((flip_4_bits((addrl >> 12) & 0xf)) << 12) + + ((flip_4_bits((addrl >> 16) & 0xf)) << 16) + + ((flip_4_bits((addrl >> 20) & 0xf)) << 20) + + ((flip_4_bits((addrl >> 24) & 0xf)) << 24) + + ((flip_4_bits((addrl >> 28) & 0xf)) << 28); + + addrh = addrhswapped; + addrl = addrlswapped; + + addr0 = (addrl >> 2) & 0x03f; + addr1 = (addrl & 0x003) | (((addrl >> 8) & 0x7f) << 2); + addr2 = (addrl >> 15) & 0x1ff; + addr3 = ((addrl >> 24) & 0x0ff) | ((addrh & 1) << 8); + + hashresult = (addr0 << 9) | (addr1 ^ addr2 ^ addr3); + hashresult = hashresult & 0x07ff; + return hashresult; +} + +/* + * This function will add an entry to the address table. + * depends on the hash mode and hash size that was initialized. + * Inputs + * mach - the 2 most significant bytes of the MAC address. + * macl - the 4 least significant bytes of the MAC address. + * skip - if 1, skip this address. + * rd - the RD field in the address table. + * Outputs + * address table entry is added. + * 0 if success. + * -ENOSPC if table full + */ +static int add_del_hash_entry(struct armdfec_device *darmdfec, u32 mach, + u32 macl, u32 rd, u32 skip, int del) +{ + struct addr_table_entry_t *entry, *start; + u32 newhi; + u32 newlo; + u32 i; + + newlo = (((mach >> 4) & 0xf) << 15) + | (((mach >> 0) & 0xf) << 11) + | (((mach >> 12) & 0xf) << 7) + | (((mach >> 8) & 0xf) << 3) + | (((macl >> 20) & 0x1) << 31) + | (((macl >> 16) & 0xf) << 27) + | (((macl >> 28) & 0xf) << 23) + | (((macl >> 24) & 0xf) << 19) + | (skip << HTESKIP) | (rd << HTERDBIT) + | HTEVALID; + + newhi = (((macl >> 4) & 0xf) << 15) + | (((macl >> 0) & 0xf) << 11) + | (((macl >> 12) & 0xf) << 7) + | (((macl >> 8) & 0xf) << 3) + | (((macl >> 21) & 0x7) << 0); + + /* + * Pick the appropriate table, start scanning for free/reusable + * entries at the index obtained by hashing the specified MAC address + */ + start = (struct addr_table_entry_t *)(darmdfec->htpr); + entry = start + hash_function(mach, macl); + for (i = 0; i < HOP_NUMBER; i++) { + if (!(entry->lo & HTEVALID)) { + break; + } else { + /* if same address put in same position */ + if (((entry->lo & 0xfffffff8) == (newlo & 0xfffffff8)) + && (entry->hi == newhi)) + break; + } + if (entry == start + 0x7ff) + entry = start; + else + entry++; + } + + if (((entry->lo & 0xfffffff8) != (newlo & 0xfffffff8)) && + (entry->hi != newhi) && del) + return 0; + + if (i == HOP_NUMBER) { + if (!del) { + printf("ARMD100 FEC: (%s) table section is full\n", + __func__); + return -ENOSPC; + } else { + return 0; + } + } + + /* + * Update the selected entry + */ + if (del) { + entry->hi = 0; + entry->lo = 0; + } else { + entry->hi = newhi; + entry->lo = newlo; + } + + return 0; +} + +/* + * Create an addressTable entry from MAC address info + * found in the specifed net_device struct + * + * Input : pointer to ethernet interface network device structure + * Output : N/A + */ +static void update_hash_table_mac_address(struct armdfec_device *darmdfec, + u8 *oaddr, u8 *addr) +{ + u32 mach; + u32 macl; + + /* Delete old entry */ + if (oaddr) { + mach = (oaddr[0] << 8) | oaddr[1]; + macl = (oaddr[2] << 24) | (oaddr[3] << 16) | + (oaddr[4] << 8) | oaddr[5]; + add_del_hash_entry(darmdfec, mach, macl, 1, 0, HASH_DELETE); + } + + /* Add new entry */ + mach = (addr[0] << 8) | addr[1]; + macl = (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) | addr[5]; + add_del_hash_entry(darmdfec, mach, macl, 1, 0, HASH_ADD); +} + +/* Address Table Initialization */ +static void init_hashtable(struct eth_device *dev) +{ + struct armdfec_device *darmdfec = to_darmdfec(dev); + struct armdfec_reg *regs = darmdfec->regs; + memset(darmdfec->htpr, 0, HASH_ADDR_TABLE_SIZE); + writel((u32)darmdfec->htpr, ®s->htpr); +} + +/* + * This detects PHY chip from address 0-31 by reading PHY status + * registers. PHY chip can be connected at any of this address. + */ +static int ethernet_phy_detect(struct eth_device *dev) +{ + u32 val; + u16 tmp, mii_status; + u8 addr; + + for (addr = 0; addr < 32; addr++) { + if (miiphy_read(dev->name, addr, MII_BMSR, &mii_status) != 0) + /* try next phy */ + continue; + + /* invalid MII status. More validation required here... */ + if (mii_status == 0 || mii_status == 0xffff) + /* try next phy */ + continue; + + if (miiphy_read(dev->name, addr, MII_PHYSID1, &tmp) != 0) + /* try next phy */ + continue; + + val = tmp << 16; + if (miiphy_read(dev->name, addr, MII_PHYSID2, &tmp) != 0) + /* try next phy */ + continue; + + val |= tmp; + + if ((val & 0xfffffff0) != 0) + return addr; + } + return -1; +} + +static void armdfec_init_rx_desc_ring(struct armdfec_device *darmdfec) +{ + struct rx_desc *p_rx_desc; + int i; + + /* initialize the Rx descriptors ring */ + p_rx_desc = darmdfec->p_rxdesc; + for (i = 0; i < RINGSZ; i++) { + p_rx_desc->cmd_sts = BUF_OWNED_BY_DMA | RX_EN_INT; + p_rx_desc->buf_size = PKTSIZE_ALIGN; + p_rx_desc->byte_cnt = 0; + p_rx_desc->buf_ptr = darmdfec->p_rxbuf + i * PKTSIZE_ALIGN; + if (i == (RINGSZ - 1)) { + p_rx_desc->nxtdesc_p = darmdfec->p_rxdesc; + } else { + p_rx_desc->nxtdesc_p = (struct rx_desc *) + ((u32)p_rx_desc + ARMDFEC_RXQ_DESC_ALIGNED_SIZE); + p_rx_desc = p_rx_desc->nxtdesc_p; + } + } + darmdfec->p_rxdesc_curr = darmdfec->p_rxdesc; +} + +static int armdfec_init(struct eth_device *dev, bd_t *bd) +{ + struct armdfec_device *darmdfec = to_darmdfec(dev); + struct armdfec_reg *regs = darmdfec->regs; + int phy_adr; + u32 temp; + + armdfec_init_rx_desc_ring(darmdfec); + + /* Disable interrupts */ + writel(0, ®s->im); + writel(0, ®s->ic); + /* Write to ICR to clear interrupts. */ + writel(0, ®s->iwc); + + /* + * Abort any transmit and receive operations and put DMA + * in idle state. + */ + abortdma(dev); + + /* Initialize address hash table */ + init_hashtable(dev); + + /* SDMA configuration */ + writel(SDCR_BSZ8 | /* Burst size = 32 bytes */ + SDCR_RIFB | /* Rx interrupt on frame */ + SDCR_BLMT | /* Little endian transmit */ + SDCR_BLMR | /* Little endian receive */ + SDCR_RC_MAX_RETRANS, /* Max retransmit count */ + ®s->sdma_conf); + /* Port Configuration */ + writel(PCR_HS, ®s->pconf); /* Hash size is 1/2kb */ + + /* Set extended port configuration */ + writel(PCXR_2BSM | /* Two byte suffix aligns IP hdr */ + PCXR_DSCP_EN | /* Enable DSCP in IP */ + PCXR_MFL_1536 | /* Set MTU = 1536 */ + PCXR_FLP | /* do not force link pass */ + PCXR_TX_HIGH_PRI, /* Transmit - high priority queue */ + ®s->pconf_ext); + + update_hash_table_mac_address(darmdfec, NULL, dev->enetaddr); + + /* Update TX and RX queue descriptor register */ + temp = (u32)®s->txcdp[TXQ]; + writel((u32)darmdfec->p_txdesc, temp); + temp = (u32)®s->rxfdp[RXQ]; + writel((u32)darmdfec->p_rxdesc, temp); + temp = (u32)®s->rxcdp[RXQ]; + writel((u32)darmdfec->p_rxdesc_curr, temp); + + /* Enable Interrupts */ + writel(ALL_INTS, ®s->im); + + /* Enable Ethernet Port */ + setbits_le32(®s->pconf, PCR_EN); + + /* Enable RX DMA engine */ + setbits_le32(®s->sdma_cmd, SDMA_CMD_ERD); + +#ifdef DEBUG + eth_dump_regs(dev); +#endif + +#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) + +#if defined(CONFIG_PHY_BASE_ADR) + miiphy_write(dev->name, PHY_ADR_REQ, PHY_ADR_REQ, CONFIG_PHY_BASE_ADR); +#else + /* Search phy address from range 0-31 */ + phy_adr = ethernet_phy_detect(dev); + if (phy_adr < 0) { + printf("ARMD100 FEC: PHY not detected at address range 0-31\n"); + return -1; + } else { + debug("ARMD100 FEC: PHY detected at addr %d\n", phy_adr); + miiphy_write(dev->name, PHY_ADR_REQ, PHY_ADR_REQ, phy_adr); + } +#endif + +#if defined(CONFIG_SYS_FAULT_ECHO_LINK_DOWN) + /* Wait up to 5s for the link status */ + for (i = 0; i < 5; i++) { + u16 phy_adr; + + miiphy_read(dev->name, 0xFF, 0xFF, &phy_adr); + /* Return if we get link up */ + if (miiphy_link(dev->name, phy_adr)) + return 0; + udelay(1000000); + } + + printf("ARMD100 FEC: No link on %s\n", dev->name); + return -1; +#endif +#endif + return 0; +} + +static void armdfec_halt(struct eth_device *dev) +{ + struct armdfec_device *darmdfec = to_darmdfec(dev); + struct armdfec_reg *regs = darmdfec->regs; + + /* Stop RX DMA */ + clrbits_le32(®s->sdma_cmd, SDMA_CMD_ERD); + + /* + * Abort any transmit and receive operations and put DMA + * in idle state. + */ + abortdma(dev); + + /* Disable interrupts */ + writel(0, ®s->im); + writel(0, ®s->ic); + writel(0, ®s->iwc); + + /* Disable Port */ + clrbits_le32(®s->pconf, PCR_EN); +} + +static int armdfec_send(struct eth_device *dev, void *dataptr, int datasize) +{ + struct armdfec_device *darmdfec = to_darmdfec(dev); + struct armdfec_reg *regs = darmdfec->regs; + struct tx_desc *p_txdesc = darmdfec->p_txdesc; + void *p = (void *)dataptr; + int retry = PHY_WAIT_ITERATIONS * PHY_WAIT_MICRO_SECONDS; + u32 cmd_sts, temp; + + /* Copy buffer if it's misaligned */ + if ((u32)dataptr & 0x07) { + if (datasize > PKTSIZE_ALIGN) { + printf("ARMD100 FEC: Non-aligned data too large (%d)\n", + datasize); + return -1; + } + memcpy(darmdfec->p_aligned_txbuf, p, datasize); + p = darmdfec->p_aligned_txbuf; + } + + p_txdesc->cmd_sts = TX_ZERO_PADDING | TX_GEN_CRC; + p_txdesc->cmd_sts |= TX_FIRST_DESC | TX_LAST_DESC; + p_txdesc->cmd_sts |= BUF_OWNED_BY_DMA; + p_txdesc->cmd_sts |= TX_EN_INT; + p_txdesc->buf_ptr = p; + p_txdesc->byte_cnt = datasize; + + /* Apply send command using high priority TX queue */ + temp = (u32)®s->txcdp[TXQ]; + writel((u32)p_txdesc, temp); + writel(SDMA_CMD_TXDL | SDMA_CMD_TXDH | SDMA_CMD_ERD, ®s->sdma_cmd); + + /* + * wait for packet xmit completion + */ + cmd_sts = readl(&p_txdesc->cmd_sts); + while (cmd_sts & BUF_OWNED_BY_DMA) { + /* return fail if error is detected */ + if ((cmd_sts & (TX_ERROR | TX_LAST_DESC)) == + (TX_ERROR | TX_LAST_DESC)) { + printf("ARMD100 FEC: (%s) in xmit packet\n", __func__); + return -1; + } + cmd_sts = readl(&p_txdesc->cmd_sts); + if (!(retry--)) { + printf("ARMD100 FEC: (%s) xmit packet timeout!\n", + __func__); + return -1; + } + } + + return 0; +} + +static int armdfec_recv(struct eth_device *dev) +{ + struct armdfec_device *darmdfec = to_darmdfec(dev); + struct rx_desc *p_rxdesc_curr = darmdfec->p_rxdesc_curr; + u32 cmd_sts; + u32 timeout = 0; + u32 temp; + + /* wait untill rx packet available or timeout */ + do { + if (timeout < PHY_WAIT_ITERATIONS * PHY_WAIT_MICRO_SECONDS) { + timeout++; + } else { + debug("ARMD100 FEC: %s time out...\n", __func__); + return -1; + } + } while (readl(&p_rxdesc_curr->cmd_sts) & BUF_OWNED_BY_DMA); + + if (p_rxdesc_curr->byte_cnt != 0) { + debug("ARMD100 FEC: %s: Received %d byte Packet @ 0x%x" + "(cmd_sts= %08x)\n", __func__, + (u32)p_rxdesc_curr->byte_cnt, + (u32)p_rxdesc_curr->buf_ptr, + (u32)p_rxdesc_curr->cmd_sts); + } + + /* + * In case received a packet without first/last bits on + * OR the error summary bit is on, + * the packets needs to be dropeed. + */ + cmd_sts = readl(&p_rxdesc_curr->cmd_sts); + + if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) != + (RX_FIRST_DESC | RX_LAST_DESC)) { + printf("ARMD100 FEC: (%s) Dropping packet spread on" + " multiple descriptors\n", __func__); + } else if (cmd_sts & RX_ERROR) { + printf("ARMD100 FEC: (%s) Dropping packet with errors\n", + __func__); + } else { + /* !!! call higher layer processing */ + debug("ARMD100 FEC: (%s) Sending Received packet to" + " upper layer (net_process_received_packet)\n", __func__); + + /* + * let the upper layer handle the packet, subtract offset + * as two dummy bytes are added in received buffer see + * PORT_CONFIG_EXT register bit TWO_Byte_Stuff_Mode bit. + */ + net_process_received_packet( + p_rxdesc_curr->buf_ptr + RX_BUF_OFFSET, + (int)(p_rxdesc_curr->byte_cnt - RX_BUF_OFFSET)); + } + /* + * free these descriptors and point next in the ring + */ + p_rxdesc_curr->cmd_sts = BUF_OWNED_BY_DMA | RX_EN_INT; + p_rxdesc_curr->buf_size = PKTSIZE_ALIGN; + p_rxdesc_curr->byte_cnt = 0; + + temp = (u32)&darmdfec->p_rxdesc_curr; + writel((u32)p_rxdesc_curr->nxtdesc_p, temp); + + return 0; +} + +int armada100_fec_register(unsigned long base_addr) +{ + struct armdfec_device *darmdfec; + struct eth_device *dev; + + darmdfec = malloc(sizeof(struct armdfec_device)); + if (!darmdfec) + goto error; + + memset(darmdfec, 0, sizeof(struct armdfec_device)); + + darmdfec->htpr = memalign(8, HASH_ADDR_TABLE_SIZE); + if (!darmdfec->htpr) + goto error1; + + darmdfec->p_rxdesc = memalign(PKTALIGN, + ARMDFEC_RXQ_DESC_ALIGNED_SIZE * RINGSZ + 1); + + if (!darmdfec->p_rxdesc) + goto error1; + + darmdfec->p_rxbuf = memalign(PKTALIGN, RINGSZ * PKTSIZE_ALIGN + 1); + if (!darmdfec->p_rxbuf) + goto error1; + + darmdfec->p_aligned_txbuf = memalign(8, PKTSIZE_ALIGN); + if (!darmdfec->p_aligned_txbuf) + goto error1; + + darmdfec->p_txdesc = memalign(PKTALIGN, sizeof(struct tx_desc) + 1); + if (!darmdfec->p_txdesc) + goto error1; + + dev = &darmdfec->dev; + /* Assign ARMADA100 Fast Ethernet Controller Base Address */ + darmdfec->regs = (void *)base_addr; + + /* must be less than sizeof(dev->name) */ + strcpy(dev->name, "armd-fec0"); + + dev->init = armdfec_init; + dev->halt = armdfec_halt; + dev->send = armdfec_send; + dev->recv = armdfec_recv; + + eth_register(dev); + +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) + miiphy_register(dev->name, smi_reg_read, smi_reg_write); +#endif + return 0; + +error1: + free(darmdfec->p_aligned_txbuf); + free(darmdfec->p_rxbuf); + free(darmdfec->p_rxdesc); + free(darmdfec->htpr); +error: + free(darmdfec); + printf("AMD100 FEC: (%s) Failed to allocate memory\n", __func__); + return -1; +} diff --git a/sources/uboot-be550/drivers/net/armada100_fec.h b/sources/uboot-be550/drivers/net/armada100_fec.h new file mode 100644 index 00000000..5a0a3d98 --- /dev/null +++ b/sources/uboot-be550/drivers/net/armada100_fec.h @@ -0,0 +1,209 @@ +/* + * (C) Copyright 2011 + * eInfochips Ltd. + * Written-by: Ajay Bhargav + * + * (C) Copyright 2010 + * Marvell Semiconductor + * Contributor: Mahavir Jain + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ARMADA100_FEC_H__ +#define __ARMADA100_FEC_H__ + +#define PORT_NUM 0x0 + +/* RX & TX descriptor command */ +#define BUF_OWNED_BY_DMA (1<<31) + +/* RX descriptor status */ +#define RX_EN_INT (1<<23) +#define RX_FIRST_DESC (1<<17) +#define RX_LAST_DESC (1<<16) +#define RX_ERROR (1<<15) + +/* TX descriptor command */ +#define TX_EN_INT (1<<23) +#define TX_GEN_CRC (1<<22) +#define TX_ZERO_PADDING (1<<18) +#define TX_FIRST_DESC (1<<17) +#define TX_LAST_DESC (1<<16) +#define TX_ERROR (1<<15) + +/* smi register */ +#define SMI_BUSY (1<<28) /* 0 - Write, 1 - Read */ +#define SMI_R_VALID (1<<27) /* 0 - Write, 1 - Read */ +#define SMI_OP_W (0<<26) /* Write operation */ +#define SMI_OP_R (1<<26) /* Read operation */ + +#define HASH_ADD 0 +#define HASH_DELETE 1 +#define HASH_ADDR_TABLE_SIZE 0x4000 /* 16K (1/2K address - PCR_HS == 1) */ +#define HOP_NUMBER 12 + +#define PHY_WAIT_ITERATIONS 1000 /* 1000 iterations * 10uS = 10mS max */ +#define PHY_WAIT_MICRO_SECONDS 10 + +#define ETH_HW_IP_ALIGN 2 /* hw aligns IP header */ +#define ETH_EXTRA_HEADER (6+6+2+4) + /* dest+src addr+protocol id+crc */ +#define MAX_PKT_SIZE 1536 + + +/* Bit definitions of the SDMA Config Reg */ +#define SDCR_BSZ_OFF 12 +#define SDCR_BSZ8 (3< +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#undef MII_DEBUG +#undef ET_DEBUG + +#if (CONFIG_SYS_RX_ETH_BUFFER > 1024) +#error AT91 EMAC supports max 1024 RX buffers. \ + Please decrease the CONFIG_SYS_RX_ETH_BUFFER value +#endif + +#ifndef CONFIG_DRIVER_AT91EMAC_PHYADDR +#define CONFIG_DRIVER_AT91EMAC_PHYADDR 0 +#endif + +/* MDIO clock must not exceed 2.5 MHz, so enable MCK divider */ +#if (AT91C_MASTER_CLOCK > 80000000) + #define HCLK_DIV AT91_EMAC_CFG_MCLK_64 +#elif (AT91C_MASTER_CLOCK > 40000000) + #define HCLK_DIV AT91_EMAC_CFG_MCLK_32 +#elif (AT91C_MASTER_CLOCK > 20000000) + #define HCLK_DIV AT91_EMAC_CFG_MCLK_16 +#else + #define HCLK_DIV AT91_EMAC_CFG_MCLK_8 +#endif + +#ifdef ET_DEBUG +#define DEBUG_AT91EMAC 1 +#else +#define DEBUG_AT91EMAC 0 +#endif + +#ifdef MII_DEBUG +#define DEBUG_AT91PHY 1 +#else +#define DEBUG_AT91PHY 0 +#endif + +#ifndef CONFIG_DRIVER_AT91EMAC_QUIET +#define VERBOSEP 1 +#else +#define VERBOSEP 0 +#endif + +#define RBF_ADDR 0xfffffffc +#define RBF_OWNER (1<<0) +#define RBF_WRAP (1<<1) +#define RBF_BROADCAST (1<<31) +#define RBF_MULTICAST (1<<30) +#define RBF_UNICAST (1<<29) +#define RBF_EXTERNAL (1<<28) +#define RBF_UNKNOWN (1<<27) +#define RBF_SIZE 0x07ff +#define RBF_LOCAL4 (1<<26) +#define RBF_LOCAL3 (1<<25) +#define RBF_LOCAL2 (1<<24) +#define RBF_LOCAL1 (1<<23) + +#define RBF_FRAMEMAX CONFIG_SYS_RX_ETH_BUFFER +#define RBF_FRAMELEN 0x600 + +typedef struct { + unsigned long addr, size; +} rbf_t; + +typedef struct { + rbf_t rbfdt[RBF_FRAMEMAX]; + unsigned long rbindex; +} emac_device; + +void at91emac_EnableMDIO(at91_emac_t *at91mac) +{ + /* Mac CTRL reg set for MDIO enable */ + writel(readl(&at91mac->ctl) | AT91_EMAC_CTL_MPE, &at91mac->ctl); +} + +void at91emac_DisableMDIO(at91_emac_t *at91mac) +{ + /* Mac CTRL reg set for MDIO disable */ + writel(readl(&at91mac->ctl) & ~AT91_EMAC_CTL_MPE, &at91mac->ctl); +} + +int at91emac_read(at91_emac_t *at91mac, unsigned char addr, + unsigned char reg, unsigned short *value) +{ + unsigned long netstat; + at91emac_EnableMDIO(at91mac); + + writel(AT91_EMAC_MAN_HIGH | AT91_EMAC_MAN_RW_R | + AT91_EMAC_MAN_REGA(reg) | AT91_EMAC_MAN_CODE_802_3 | + AT91_EMAC_MAN_PHYA(addr), + &at91mac->man); + + do { + netstat = readl(&at91mac->sr); + debug_cond(DEBUG_AT91PHY, "poll SR %08lx\n", netstat); + } while (!(netstat & AT91_EMAC_SR_IDLE)); + + *value = readl(&at91mac->man) & AT91_EMAC_MAN_DATA_MASK; + + at91emac_DisableMDIO(at91mac); + + debug_cond(DEBUG_AT91PHY, + "AT91PHY read %p REG(%d)=%x\n", at91mac, reg, *value); + + return 0; +} + +int at91emac_write(at91_emac_t *at91mac, unsigned char addr, + unsigned char reg, unsigned short value) +{ + unsigned long netstat; + debug_cond(DEBUG_AT91PHY, + "AT91PHY write %p REG(%d)=%p\n", at91mac, reg, &value); + + at91emac_EnableMDIO(at91mac); + + writel(AT91_EMAC_MAN_HIGH | AT91_EMAC_MAN_RW_W | + AT91_EMAC_MAN_REGA(reg) | AT91_EMAC_MAN_CODE_802_3 | + AT91_EMAC_MAN_PHYA(addr) | (value & AT91_EMAC_MAN_DATA_MASK), + &at91mac->man); + + do { + netstat = readl(&at91mac->sr); + debug_cond(DEBUG_AT91PHY, "poll SR %08lx\n", netstat); + } while (!(netstat & AT91_EMAC_SR_IDLE)); + + at91emac_DisableMDIO(at91mac); + + return 0; +} + +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) + +at91_emac_t *get_emacbase_by_name(const char *devname) +{ + struct eth_device *netdev; + + netdev = eth_get_dev_by_name(devname); + return (at91_emac_t *) netdev->iobase; +} + +int at91emac_mii_read(const char *devname, unsigned char addr, + unsigned char reg, unsigned short *value) +{ + at91_emac_t *emac; + + emac = get_emacbase_by_name(devname); + at91emac_read(emac , addr, reg, value); + return 0; +} + + +int at91emac_mii_write(const char *devname, unsigned char addr, + unsigned char reg, unsigned short value) +{ + at91_emac_t *emac; + + emac = get_emacbase_by_name(devname); + at91emac_write(emac, addr, reg, value); + return 0; +} + +#endif + +static int at91emac_phy_reset(struct eth_device *netdev) +{ + int i; + u16 status, adv; + at91_emac_t *emac; + + emac = (at91_emac_t *) netdev->iobase; + + adv = ADVERTISE_CSMA | ADVERTISE_ALL; + at91emac_write(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, + MII_ADVERTISE, adv); + debug_cond(VERBOSEP, "%s: Starting autonegotiation...\n", netdev->name); + at91emac_write(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, MII_BMCR, + (BMCR_ANENABLE | BMCR_ANRESTART)); + + for (i = 0; i < 30000; i++) { + at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, + MII_BMSR, &status); + if (status & BMSR_ANEGCOMPLETE) + break; + udelay(100); + } + + if (status & BMSR_ANEGCOMPLETE) { + debug_cond(VERBOSEP, + "%s: Autonegotiation complete\n", netdev->name); + } else { + printf("%s: Autonegotiation timed out (status=0x%04x)\n", + netdev->name, status); + return -1; + } + return 0; +} + +static int at91emac_phy_init(struct eth_device *netdev) +{ + u16 phy_id, status, adv, lpa; + int media, speed, duplex; + int i; + at91_emac_t *emac; + + emac = (at91_emac_t *) netdev->iobase; + + /* Check if the PHY is up to snuff... */ + at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, + MII_PHYSID1, &phy_id); + if (phy_id == 0xffff) { + printf("%s: No PHY present\n", netdev->name); + return -1; + } + + at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, + MII_BMSR, &status); + + if (!(status & BMSR_LSTATUS)) { + /* Try to re-negotiate if we don't have link already. */ + if (at91emac_phy_reset(netdev)) + return -2; + + for (i = 0; i < 100000 / 100; i++) { + at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, + MII_BMSR, &status); + if (status & BMSR_LSTATUS) + break; + udelay(100); + } + } + if (!(status & BMSR_LSTATUS)) { + debug_cond(VERBOSEP, "%s: link down\n", netdev->name); + return -3; + } else { + at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, + MII_ADVERTISE, &adv); + at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, + MII_LPA, &lpa); + media = mii_nway_result(lpa & adv); + speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) + ? 1 : 0); + duplex = (media & ADVERTISE_FULL) ? 1 : 0; + debug_cond(VERBOSEP, "%s: link up, %sMbps %s-duplex\n", + netdev->name, + speed ? "100" : "10", + duplex ? "full" : "half"); + } + return 0; +} + +int at91emac_UpdateLinkSpeed(at91_emac_t *emac) +{ + unsigned short stat1; + + at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, MII_BMSR, &stat1); + + if (!(stat1 & BMSR_LSTATUS)) /* link status up? */ + return -1; + + if (stat1 & BMSR_100FULL) { + /*set Emac for 100BaseTX and Full Duplex */ + writel(readl(&emac->cfg) | + AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD, + &emac->cfg); + return 0; + } + + if (stat1 & BMSR_10FULL) { + /*set MII for 10BaseT and Full Duplex */ + writel((readl(&emac->cfg) & + ~(AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD) + ) | AT91_EMAC_CFG_FD, + &emac->cfg); + return 0; + } + + if (stat1 & BMSR_100HALF) { + /*set MII for 100BaseTX and Half Duplex */ + writel((readl(&emac->cfg) & + ~(AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD) + ) | AT91_EMAC_CFG_SPD, + &emac->cfg); + return 0; + } + + if (stat1 & BMSR_10HALF) { + /*set MII for 10BaseT and Half Duplex */ + writel((readl(&emac->cfg) & + ~(AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD)), + &emac->cfg); + return 0; + } + return 0; +} + +static int at91emac_init(struct eth_device *netdev, bd_t *bd) +{ + int i; + u32 value; + emac_device *dev; + at91_emac_t *emac; + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + + emac = (at91_emac_t *) netdev->iobase; + dev = (emac_device *) netdev->priv; + + /* PIO Disable Register */ + value = ATMEL_PMX_AA_EMDIO | ATMEL_PMX_AA_EMDC | + ATMEL_PMX_AA_ERXER | ATMEL_PMX_AA_ERX1 | + ATMEL_PMX_AA_ERX0 | ATMEL_PMX_AA_ECRS | + ATMEL_PMX_AA_ETX1 | ATMEL_PMX_AA_ETX0 | + ATMEL_PMX_AA_ETXEN | ATMEL_PMX_AA_EREFCK; + + writel(value, &pio->pioa.pdr); + writel(value, &pio->pioa.asr); + +#ifdef CONFIG_RMII + value = ATMEL_PMX_BA_ERXCK; +#else + value = ATMEL_PMX_BA_ERXCK | ATMEL_PMX_BA_ECOL | + ATMEL_PMX_BA_ERXDV | ATMEL_PMX_BA_ERX3 | + ATMEL_PMX_BA_ERX2 | ATMEL_PMX_BA_ETXER | + ATMEL_PMX_BA_ETX3 | ATMEL_PMX_BA_ETX2; +#endif + writel(value, &pio->piob.pdr); + writel(value, &pio->piob.bsr); + + writel(1 << ATMEL_ID_EMAC, &pmc->pcer); + writel(readl(&emac->ctl) | AT91_EMAC_CTL_CSR, &emac->ctl); + + /* Init Ethernet buffers */ + for (i = 0; i < RBF_FRAMEMAX; i++) { + dev->rbfdt[i].addr = (unsigned long) net_rx_packets[i]; + dev->rbfdt[i].size = 0; + } + dev->rbfdt[RBF_FRAMEMAX - 1].addr |= RBF_WRAP; + dev->rbindex = 0; + writel((u32) &(dev->rbfdt[0]), &emac->rbqp); + + writel(readl(&emac->rsr) & + ~(AT91_EMAC_RSR_OVR | AT91_EMAC_RSR_REC | AT91_EMAC_RSR_BNA), + &emac->rsr); + + value = AT91_EMAC_CFG_CAF | AT91_EMAC_CFG_NBC | + HCLK_DIV; +#ifdef CONFIG_RMII + value |= AT91_EMAC_CFG_RMII; +#endif + writel(value, &emac->cfg); + + writel(readl(&emac->ctl) | AT91_EMAC_CTL_TE | AT91_EMAC_CTL_RE, + &emac->ctl); + + if (!at91emac_phy_init(netdev)) { + at91emac_UpdateLinkSpeed(emac); + return 0; + } + return -1; +} + +static void at91emac_halt(struct eth_device *netdev) +{ + at91_emac_t *emac; + + emac = (at91_emac_t *) netdev->iobase; + writel(readl(&emac->ctl) & ~(AT91_EMAC_CTL_TE | AT91_EMAC_CTL_RE), + &emac->ctl); + debug_cond(DEBUG_AT91EMAC, "halt MAC\n"); +} + +static int at91emac_send(struct eth_device *netdev, void *packet, int length) +{ + at91_emac_t *emac; + + emac = (at91_emac_t *) netdev->iobase; + + while (!(readl(&emac->tsr) & AT91_EMAC_TSR_BNQ)) + ; + writel((u32) packet, &emac->tar); + writel(AT91_EMAC_TCR_LEN(length), &emac->tcr); + while (AT91_EMAC_TCR_LEN(readl(&emac->tcr))) + ; + debug_cond(DEBUG_AT91EMAC, "Send %d\n", length); + writel(readl(&emac->tsr) | AT91_EMAC_TSR_COMP, &emac->tsr); + return 0; +} + +static int at91emac_recv(struct eth_device *netdev) +{ + emac_device *dev; + at91_emac_t *emac; + rbf_t *rbfp; + int size; + + emac = (at91_emac_t *) netdev->iobase; + dev = (emac_device *) netdev->priv; + + rbfp = &dev->rbfdt[dev->rbindex]; + while (rbfp->addr & RBF_OWNER) { + size = rbfp->size & RBF_SIZE; + net_process_received_packet(net_rx_packets[dev->rbindex], size); + + debug_cond(DEBUG_AT91EMAC, "Recv[%ld]: %d bytes @ %lx\n", + dev->rbindex, size, rbfp->addr); + + rbfp->addr &= ~RBF_OWNER; + rbfp->size = 0; + if (dev->rbindex < (RBF_FRAMEMAX-1)) + dev->rbindex++; + else + dev->rbindex = 0; + + rbfp = &(dev->rbfdt[dev->rbindex]); + if (!(rbfp->addr & RBF_OWNER)) + writel(readl(&emac->rsr) | AT91_EMAC_RSR_REC, + &emac->rsr); + } + + if (readl(&emac->isr) & AT91_EMAC_IxR_RBNA) { + /* EMAC silicon bug 41.3.1 workaround 1 */ + writel(readl(&emac->ctl) & ~AT91_EMAC_CTL_RE, &emac->ctl); + writel(readl(&emac->ctl) | AT91_EMAC_CTL_RE, &emac->ctl); + dev->rbindex = 0; + printf("%s: reset receiver (EMAC dead lock bug)\n", + netdev->name); + } + return 0; +} + +static int at91emac_write_hwaddr(struct eth_device *netdev) +{ + at91_emac_t *emac; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + emac = (at91_emac_t *) netdev->iobase; + + writel(1 << ATMEL_ID_EMAC, &pmc->pcer); + debug_cond(DEBUG_AT91EMAC, + "init MAC-ADDR %02x:%02x:%02x:%02x:%02x:%02x\n", + netdev->enetaddr[5], netdev->enetaddr[4], netdev->enetaddr[3], + netdev->enetaddr[2], netdev->enetaddr[1], netdev->enetaddr[0]); + writel( (netdev->enetaddr[0] | netdev->enetaddr[1] << 8 | + netdev->enetaddr[2] << 16 | netdev->enetaddr[3] << 24), + &emac->sa2l); + writel((netdev->enetaddr[4] | netdev->enetaddr[5] << 8), &emac->sa2h); + debug_cond(DEBUG_AT91EMAC, "init MAC-ADDR %x%x\n", + readl(&emac->sa2h), readl(&emac->sa2l)); + return 0; +} + +int at91emac_register(bd_t *bis, unsigned long iobase) +{ + emac_device *emac; + emac_device *emacfix; + struct eth_device *dev; + + if (iobase == 0) + iobase = ATMEL_BASE_EMAC; + emac = malloc(sizeof(*emac)+512); + if (emac == NULL) + return -1; + dev = malloc(sizeof(*dev)); + if (dev == NULL) { + free(emac); + return -1; + } + /* alignment as per Errata (64 bytes) is insufficient! */ + emacfix = (emac_device *) (((unsigned long) emac + 0x1ff) & 0xFFFFFE00); + memset(emacfix, 0, sizeof(emac_device)); + + memset(dev, 0, sizeof(*dev)); + sprintf(dev->name, "emac"); + dev->iobase = iobase; + dev->priv = emacfix; + dev->init = at91emac_init; + dev->halt = at91emac_halt; + dev->send = at91emac_send; + dev->recv = at91emac_recv; + dev->write_hwaddr = at91emac_write_hwaddr; + + eth_register(dev); + +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) + miiphy_register(dev->name, at91emac_mii_read, at91emac_mii_write); +#endif + return 1; +} diff --git a/sources/uboot-be550/drivers/net/ax88180.c b/sources/uboot-be550/drivers/net/ax88180.c new file mode 100644 index 00000000..ded9e064 --- /dev/null +++ b/sources/uboot-be550/drivers/net/ax88180.c @@ -0,0 +1,757 @@ +/* + * ax88180: ASIX AX88180 Non-PCI Gigabit Ethernet u-boot driver + * + * This program is free software; you can distribute it and/or modify + * it under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * This program is distributed in the hope it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See the GNU General Public License for more details. + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, + * USA. + */ + +/* + * ======================================================================== + * ASIX AX88180 Non-PCI 16/32-bit Gigabit Ethernet Linux Driver + * + * The AX88180 Ethernet controller is a high performance and highly + * integrated local CPU bus Ethernet controller with embedded 40K bytes + * SRAM and supports both 16-bit and 32-bit SRAM-Like interfaces for any + * embedded systems. + * The AX88180 is a single chip 10/100/1000Mbps Gigabit Ethernet + * controller that supports both MII and RGMII interfaces and is + * compliant to IEEE 802.3, IEEE 802.3u and IEEE 802.3z standards. + * + * Please visit ASIX's web site (http://www.asix.com.tw) for more + * details. + * + * Module Name : ax88180.c + * Date : 2008-07-07 + * History + * 09/06/2006 : New release for AX88180 US2 chip. + * 07/07/2008 : Fix up the coding style and using inline functions + * instead of macros + * ======================================================================== + */ +#include +#include +#include +#include +#include +#include "ax88180.h" + +/* + * =========================================================================== + * Local SubProgram Declaration + * =========================================================================== + */ +static void ax88180_rx_handler (struct eth_device *dev); +static int ax88180_phy_initial (struct eth_device *dev); +static void ax88180_media_config (struct eth_device *dev); +static unsigned long get_CicadaPHY_media_mode (struct eth_device *dev); +static unsigned long get_MarvellPHY_media_mode (struct eth_device *dev); +static unsigned short ax88180_mdio_read (struct eth_device *dev, + unsigned long regaddr); +static void ax88180_mdio_write (struct eth_device *dev, + unsigned long regaddr, unsigned short regdata); + +/* + * =========================================================================== + * Local SubProgram Bodies + * =========================================================================== + */ +static int ax88180_mdio_check_complete (struct eth_device *dev) +{ + int us_cnt = 10000; + unsigned short tmpval; + + /* MDIO read/write should not take more than 10 ms */ + while (--us_cnt) { + tmpval = INW (dev, MDIOCTRL); + if (((tmpval & READ_PHY) == 0) && ((tmpval & WRITE_PHY) == 0)) + break; + } + + return us_cnt; +} + +static unsigned short +ax88180_mdio_read (struct eth_device *dev, unsigned long regaddr) +{ + struct ax88180_private *priv = (struct ax88180_private *)dev->priv; + unsigned long tmpval = 0; + + OUTW (dev, (READ_PHY | (regaddr << 8) | priv->PhyAddr), MDIOCTRL); + + if (ax88180_mdio_check_complete (dev)) + tmpval = INW (dev, MDIODP); + else + printf ("Failed to read PHY register!\n"); + + return (unsigned short)(tmpval & 0xFFFF); +} + +static void +ax88180_mdio_write (struct eth_device *dev, unsigned long regaddr, + unsigned short regdata) +{ + struct ax88180_private *priv = (struct ax88180_private *)dev->priv; + + OUTW (dev, regdata, MDIODP); + + OUTW (dev, (WRITE_PHY | (regaddr << 8) | priv->PhyAddr), MDIOCTRL); + + if (!ax88180_mdio_check_complete (dev)) + printf ("Failed to write PHY register!\n"); +} + +static int ax88180_phy_reset (struct eth_device *dev) +{ + unsigned short delay_cnt = 500; + + ax88180_mdio_write (dev, MII_BMCR, (BMCR_RESET | BMCR_ANENABLE)); + + /* Wait for the reset to complete, or time out (500 ms) */ + while (ax88180_mdio_read (dev, MII_BMCR) & BMCR_RESET) { + udelay (1000); + if (--delay_cnt == 0) { + printf ("Failed to reset PHY!\n"); + return -1; + } + } + + return 0; +} + +static void ax88180_mac_reset (struct eth_device *dev) +{ + unsigned long tmpval; + unsigned char i; + + struct { + unsigned short offset, value; + } program_seq[] = { + { + MISC, MISC_NORMAL}, { + RXINDICATOR, DEFAULT_RXINDICATOR}, { + TXCMD, DEFAULT_TXCMD}, { + TXBS, DEFAULT_TXBS}, { + TXDES0, DEFAULT_TXDES0}, { + TXDES1, DEFAULT_TXDES1}, { + TXDES2, DEFAULT_TXDES2}, { + TXDES3, DEFAULT_TXDES3}, { + TXCFG, DEFAULT_TXCFG}, { + MACCFG2, DEFAULT_MACCFG2}, { + MACCFG3, DEFAULT_MACCFG3}, { + TXLEN, DEFAULT_TXLEN}, { + RXBTHD0, DEFAULT_RXBTHD0}, { + RXBTHD1, DEFAULT_RXBTHD1}, { + RXFULTHD, DEFAULT_RXFULTHD}, { + DOGTHD0, DEFAULT_DOGTHD0}, { + DOGTHD1, DEFAULT_DOGTHD1},}; + + OUTW (dev, MISC_RESET_MAC, MISC); + tmpval = INW (dev, MISC); + + for (i = 0; i < ARRAY_SIZE(program_seq); i++) + OUTW (dev, program_seq[i].value, program_seq[i].offset); +} + +static int ax88180_poll_tx_complete (struct eth_device *dev) +{ + struct ax88180_private *priv = (struct ax88180_private *)dev->priv; + unsigned long tmpval, txbs_txdp; + int TimeOutCnt = 10000; + + txbs_txdp = 1 << priv->NextTxDesc; + + while (TimeOutCnt--) { + + tmpval = INW (dev, TXBS); + + if ((tmpval & txbs_txdp) == 0) + break; + + udelay (100); + } + + if (TimeOutCnt) + return 0; + else + return -TimeOutCnt; +} + +static void ax88180_rx_handler (struct eth_device *dev) +{ + struct ax88180_private *priv = (struct ax88180_private *)dev->priv; + unsigned long data_size; + unsigned short rxcurt_ptr, rxbound_ptr, next_ptr; + int i; +#if defined (CONFIG_DRIVER_AX88180_16BIT) + unsigned short *rxdata = (unsigned short *)net_rx_packets[0]; +#else + unsigned long *rxdata = (unsigned long *)net_rx_packets[0]; +#endif + unsigned short count; + + rxcurt_ptr = INW (dev, RXCURT); + rxbound_ptr = INW (dev, RXBOUND); + next_ptr = (rxbound_ptr + 1) & RX_PAGE_NUM_MASK; + + debug ("ax88180: RX original RXBOUND=0x%04x," + " RXCURT=0x%04x\n", rxbound_ptr, rxcurt_ptr); + + while (next_ptr != rxcurt_ptr) { + + OUTW (dev, RX_START_READ, RXINDICATOR); + + data_size = READ_RXBUF (dev) & 0xFFFF; + + if ((data_size == 0) || (data_size > MAX_RX_SIZE)) { + + OUTW (dev, RX_STOP_READ, RXINDICATOR); + + ax88180_mac_reset (dev); + printf ("ax88180: Invalid Rx packet length!" + " (len=0x%04lx)\n", data_size); + + debug ("ax88180: RX RXBOUND=0x%04x," + "RXCURT=0x%04x\n", rxbound_ptr, rxcurt_ptr); + return; + } + + rxbound_ptr += (((data_size + 0xF) & 0xFFF0) >> 4) + 1; + rxbound_ptr &= RX_PAGE_NUM_MASK; + + /* Comput access times */ + count = (data_size + priv->PadSize) >> priv->BusWidth; + + for (i = 0; i < count; i++) { + *(rxdata + i) = READ_RXBUF (dev); + } + + OUTW (dev, RX_STOP_READ, RXINDICATOR); + + /* Pass the packet up to the protocol layers. */ + net_process_received_packet(net_rx_packets[0], data_size); + + OUTW (dev, rxbound_ptr, RXBOUND); + + rxcurt_ptr = INW (dev, RXCURT); + rxbound_ptr = INW (dev, RXBOUND); + next_ptr = (rxbound_ptr + 1) & RX_PAGE_NUM_MASK; + + debug ("ax88180: RX updated RXBOUND=0x%04x," + "RXCURT=0x%04x\n", rxbound_ptr, rxcurt_ptr); + } + + return; +} + +static int ax88180_phy_initial (struct eth_device *dev) +{ + struct ax88180_private *priv = (struct ax88180_private *)dev->priv; + unsigned long tmp_regval; + unsigned short phyaddr; + + /* Search for first avaliable PHY chipset */ +#ifdef CONFIG_PHY_ADDR + phyaddr = CONFIG_PHY_ADDR; +#else + for (phyaddr = 0; phyaddr < 32; ++phyaddr) +#endif + { + priv->PhyAddr = phyaddr; + priv->PhyID0 = ax88180_mdio_read(dev, MII_PHYSID1); + priv->PhyID1 = ax88180_mdio_read(dev, MII_PHYSID2); + + switch (priv->PhyID0) { + case MARVELL_ALASKA_PHYSID0: + debug("ax88180: Found Marvell Alaska PHY family." + " (PHY Addr=0x%x)\n", priv->PhyAddr); + + switch (priv->PhyID1) { + case MARVELL_88E1118_PHYSID1: + ax88180_mdio_write(dev, M88E1118_PAGE_SEL, 2); + ax88180_mdio_write(dev, M88E1118_CR, + M88E1118_CR_DEFAULT); + ax88180_mdio_write(dev, M88E1118_PAGE_SEL, 3); + ax88180_mdio_write(dev, M88E1118_LEDCTL, + M88E1118_LEDCTL_DEFAULT); + ax88180_mdio_write(dev, M88E1118_LEDMIX, + M88E1118_LEDMIX_LED050 | M88E1118_LEDMIX_LED150 | 0x15); + ax88180_mdio_write(dev, M88E1118_PAGE_SEL, 0); + default: /* Default to 88E1111 Phy */ + tmp_regval = ax88180_mdio_read(dev, M88E1111_EXT_SSR); + if ((tmp_regval & HWCFG_MODE_MASK) != RGMII_COPPER_MODE) + ax88180_mdio_write(dev, M88E1111_EXT_SCR, + DEFAULT_EXT_SCR); + } + + if (ax88180_phy_reset(dev) < 0) + return 0; + ax88180_mdio_write(dev, M88_IER, LINK_CHANGE_INT); + + return 1; + + case CICADA_CIS8201_PHYSID0: + debug("ax88180: Found CICADA CIS8201 PHY" + " chipset. (PHY Addr=0x%x)\n", priv->PhyAddr); + + ax88180_mdio_write(dev, CIS_IMR, + (CIS_INT_ENABLE | LINK_CHANGE_INT)); + + /* Set CIS_SMI_PRIORITY bit before force the media mode */ + tmp_regval = ax88180_mdio_read(dev, CIS_AUX_CTRL_STATUS); + tmp_regval &= ~CIS_SMI_PRIORITY; + ax88180_mdio_write(dev, CIS_AUX_CTRL_STATUS, tmp_regval); + + return 1; + + case 0xffff: + /* No PHY at this addr */ + break; + + default: + printf("ax88180: Unknown PHY chipset %#x at addr %#x\n", + priv->PhyID0, priv->PhyAddr); + break; + } + } + + printf("ax88180: Unknown PHY chipset!!\n"); + return 0; +} + +static void ax88180_media_config (struct eth_device *dev) +{ + struct ax88180_private *priv = (struct ax88180_private *)dev->priv; + unsigned long bmcr_val, bmsr_val; + unsigned long rxcfg_val, maccfg0_val, maccfg1_val; + unsigned long RealMediaMode; + int i; + + /* Waiting 2 seconds for PHY link stable */ + for (i = 0; i < 20000; i++) { + bmsr_val = ax88180_mdio_read (dev, MII_BMSR); + if (bmsr_val & BMSR_LSTATUS) { + break; + } + udelay (100); + } + + bmsr_val = ax88180_mdio_read (dev, MII_BMSR); + debug ("ax88180: BMSR=0x%04x\n", (unsigned int)bmsr_val); + + if (bmsr_val & BMSR_LSTATUS) { + bmcr_val = ax88180_mdio_read (dev, MII_BMCR); + + if (bmcr_val & BMCR_ANENABLE) { + + /* + * Waiting for Auto-negotiation completion, this may + * take up to 5 seconds. + */ + debug ("ax88180: Auto-negotiation is " + "enabled. Waiting for NWay completion..\n"); + for (i = 0; i < 50000; i++) { + bmsr_val = ax88180_mdio_read (dev, MII_BMSR); + if (bmsr_val & BMSR_ANEGCOMPLETE) { + break; + } + udelay (100); + } + } else + debug ("ax88180: Auto-negotiation is disabled.\n"); + + debug ("ax88180: BMCR=0x%04x, BMSR=0x%04x\n", + (unsigned int)bmcr_val, (unsigned int)bmsr_val); + + /* Get real media mode here */ + switch (priv->PhyID0) { + case MARVELL_ALASKA_PHYSID0: + RealMediaMode = get_MarvellPHY_media_mode(dev); + break; + case CICADA_CIS8201_PHYSID0: + RealMediaMode = get_CicadaPHY_media_mode(dev); + break; + default: + RealMediaMode = MEDIA_1000FULL; + break; + } + + priv->LinkState = INS_LINK_UP; + + switch (RealMediaMode) { + case MEDIA_1000FULL: + debug ("ax88180: 1000Mbps Full-duplex mode.\n"); + rxcfg_val = RXFLOW_ENABLE | DEFAULT_RXCFG; + maccfg0_val = TXFLOW_ENABLE | DEFAULT_MACCFG0; + maccfg1_val = GIGA_MODE_EN | RXFLOW_EN | + FULLDUPLEX | DEFAULT_MACCFG1; + break; + + case MEDIA_1000HALF: + debug ("ax88180: 1000Mbps Half-duplex mode.\n"); + rxcfg_val = DEFAULT_RXCFG; + maccfg0_val = DEFAULT_MACCFG0; + maccfg1_val = GIGA_MODE_EN | DEFAULT_MACCFG1; + break; + + case MEDIA_100FULL: + debug ("ax88180: 100Mbps Full-duplex mode.\n"); + rxcfg_val = RXFLOW_ENABLE | DEFAULT_RXCFG; + maccfg0_val = SPEED100 | TXFLOW_ENABLE + | DEFAULT_MACCFG0; + maccfg1_val = RXFLOW_EN | FULLDUPLEX | DEFAULT_MACCFG1; + break; + + case MEDIA_100HALF: + debug ("ax88180: 100Mbps Half-duplex mode.\n"); + rxcfg_val = DEFAULT_RXCFG; + maccfg0_val = SPEED100 | DEFAULT_MACCFG0; + maccfg1_val = DEFAULT_MACCFG1; + break; + + case MEDIA_10FULL: + debug ("ax88180: 10Mbps Full-duplex mode.\n"); + rxcfg_val = RXFLOW_ENABLE | DEFAULT_RXCFG; + maccfg0_val = TXFLOW_ENABLE | DEFAULT_MACCFG0; + maccfg1_val = RXFLOW_EN | FULLDUPLEX | DEFAULT_MACCFG1; + break; + + case MEDIA_10HALF: + debug ("ax88180: 10Mbps Half-duplex mode.\n"); + rxcfg_val = DEFAULT_RXCFG; + maccfg0_val = DEFAULT_MACCFG0; + maccfg1_val = DEFAULT_MACCFG1; + break; + default: + debug ("ax88180: Unknow media mode.\n"); + rxcfg_val = DEFAULT_RXCFG; + maccfg0_val = DEFAULT_MACCFG0; + maccfg1_val = DEFAULT_MACCFG1; + + priv->LinkState = INS_LINK_DOWN; + break; + } + + } else { + rxcfg_val = DEFAULT_RXCFG; + maccfg0_val = DEFAULT_MACCFG0; + maccfg1_val = DEFAULT_MACCFG1; + + priv->LinkState = INS_LINK_DOWN; + } + + OUTW (dev, rxcfg_val, RXCFG); + OUTW (dev, maccfg0_val, MACCFG0); + OUTW (dev, maccfg1_val, MACCFG1); + + return; +} + +static unsigned long get_MarvellPHY_media_mode (struct eth_device *dev) +{ + unsigned long m88_ssr; + unsigned long MediaMode; + + m88_ssr = ax88180_mdio_read (dev, M88_SSR); + switch (m88_ssr & SSR_MEDIA_MASK) { + case SSR_1000FULL: + MediaMode = MEDIA_1000FULL; + break; + case SSR_1000HALF: + MediaMode = MEDIA_1000HALF; + break; + case SSR_100FULL: + MediaMode = MEDIA_100FULL; + break; + case SSR_100HALF: + MediaMode = MEDIA_100HALF; + break; + case SSR_10FULL: + MediaMode = MEDIA_10FULL; + break; + case SSR_10HALF: + MediaMode = MEDIA_10HALF; + break; + default: + MediaMode = MEDIA_UNKNOWN; + break; + } + + return MediaMode; +} + +static unsigned long get_CicadaPHY_media_mode (struct eth_device *dev) +{ + unsigned long tmp_regval; + unsigned long MediaMode; + + tmp_regval = ax88180_mdio_read (dev, CIS_AUX_CTRL_STATUS); + switch (tmp_regval & CIS_MEDIA_MASK) { + case CIS_1000FULL: + MediaMode = MEDIA_1000FULL; + break; + case CIS_1000HALF: + MediaMode = MEDIA_1000HALF; + break; + case CIS_100FULL: + MediaMode = MEDIA_100FULL; + break; + case CIS_100HALF: + MediaMode = MEDIA_100HALF; + break; + case CIS_10FULL: + MediaMode = MEDIA_10FULL; + break; + case CIS_10HALF: + MediaMode = MEDIA_10HALF; + break; + default: + MediaMode = MEDIA_UNKNOWN; + break; + } + + return MediaMode; +} + +static void ax88180_halt (struct eth_device *dev) +{ + /* Disable AX88180 TX/RX functions */ + OUTW (dev, WAKEMOD, CMD); +} + +static int ax88180_init (struct eth_device *dev, bd_t * bd) +{ + struct ax88180_private *priv = (struct ax88180_private *)dev->priv; + unsigned short tmp_regval; + + ax88180_mac_reset (dev); + + /* Disable interrupt */ + OUTW (dev, CLEAR_IMR, IMR); + + /* Disable AX88180 TX/RX functions */ + OUTW (dev, WAKEMOD, CMD); + + /* Fill the MAC address */ + tmp_regval = + dev->enetaddr[0] | (((unsigned short)dev->enetaddr[1]) << 8); + OUTW (dev, tmp_regval, MACID0); + + tmp_regval = + dev->enetaddr[2] | (((unsigned short)dev->enetaddr[3]) << 8); + OUTW (dev, tmp_regval, MACID1); + + tmp_regval = + dev->enetaddr[4] | (((unsigned short)dev->enetaddr[5]) << 8); + OUTW (dev, tmp_regval, MACID2); + + ax88180_media_config (dev); + + OUTW (dev, DEFAULT_RXFILTER, RXFILTER); + + /* Initial variables here */ + priv->FirstTxDesc = TXDP0; + priv->NextTxDesc = TXDP0; + + /* Check if there is any invalid interrupt status and clear it. */ + OUTW (dev, INW (dev, ISR), ISR); + + /* Start AX88180 TX/RX functions */ + OUTW (dev, (RXEN | TXEN | WAKEMOD), CMD); + + return 0; +} + +/* Get a data block via Ethernet */ +static int ax88180_recv (struct eth_device *dev) +{ + unsigned short ISR_Status; + unsigned short tmp_regval; + + /* Read and check interrupt status here. */ + ISR_Status = INW (dev, ISR); + + while (ISR_Status) { + /* Clear the interrupt status */ + OUTW (dev, ISR_Status, ISR); + + debug ("\nax88180: The interrupt status = 0x%04x\n", + ISR_Status); + + if (ISR_Status & ISR_PHY) { + /* Read ISR register once to clear PHY interrupt bit */ + tmp_regval = ax88180_mdio_read (dev, M88_ISR); + ax88180_media_config (dev); + } + + if ((ISR_Status & ISR_RX) || (ISR_Status & ISR_RXBUFFOVR)) { + ax88180_rx_handler (dev); + } + + /* Read and check interrupt status again */ + ISR_Status = INW (dev, ISR); + } + + return 0; +} + +/* Send a data block via Ethernet. */ +static int ax88180_send(struct eth_device *dev, void *packet, int length) +{ + struct ax88180_private *priv = (struct ax88180_private *)dev->priv; + unsigned short TXDES_addr; + unsigned short txcmd_txdp, txbs_txdp; + unsigned short tmp_data; + int i; +#if defined (CONFIG_DRIVER_AX88180_16BIT) + volatile unsigned short *txdata = (volatile unsigned short *)packet; +#else + volatile unsigned long *txdata = (volatile unsigned long *)packet; +#endif + unsigned short count; + + if (priv->LinkState != INS_LINK_UP) { + return 0; + } + + priv->FirstTxDesc = priv->NextTxDesc; + txbs_txdp = 1 << priv->FirstTxDesc; + + debug ("ax88180: TXDP%d is available\n", priv->FirstTxDesc); + + txcmd_txdp = priv->FirstTxDesc << 13; + TXDES_addr = TXDES0 + (priv->FirstTxDesc << 2); + + OUTW (dev, (txcmd_txdp | length | TX_START_WRITE), TXCMD); + + /* Comput access times */ + count = (length + priv->PadSize) >> priv->BusWidth; + + for (i = 0; i < count; i++) { + WRITE_TXBUF (dev, *(txdata + i)); + } + + OUTW (dev, txcmd_txdp | length, TXCMD); + OUTW (dev, txbs_txdp, TXBS); + OUTW (dev, (TXDPx_ENABLE | length), TXDES_addr); + + priv->NextTxDesc = (priv->NextTxDesc + 1) & TXDP_MASK; + + /* + * Check the available transmit descriptor, if we had exhausted all + * transmit descriptor ,then we have to wait for at least one free + * descriptor + */ + txbs_txdp = 1 << priv->NextTxDesc; + tmp_data = INW (dev, TXBS); + + if (tmp_data & txbs_txdp) { + if (ax88180_poll_tx_complete (dev) < 0) { + ax88180_mac_reset (dev); + priv->FirstTxDesc = TXDP0; + priv->NextTxDesc = TXDP0; + printf ("ax88180: Transmit time out occurred!\n"); + } + } + + return 0; +} + +static void ax88180_read_mac_addr (struct eth_device *dev) +{ + unsigned short macid0_val, macid1_val, macid2_val; + unsigned short tmp_regval; + unsigned short i; + + /* Reload MAC address from EEPROM */ + OUTW (dev, RELOAD_EEPROM, PROMCTRL); + + /* Waiting for reload eeprom completion */ + for (i = 0; i < 500; i++) { + tmp_regval = INW (dev, PROMCTRL); + if ((tmp_regval & RELOAD_EEPROM) == 0) + break; + udelay (1000); + } + + /* Get MAC addresses */ + macid0_val = INW (dev, MACID0); + macid1_val = INW (dev, MACID1); + macid2_val = INW (dev, MACID2); + + if (((macid0_val | macid1_val | macid2_val) != 0) && + ((macid0_val & 0x01) == 0)) { + dev->enetaddr[0] = (unsigned char)macid0_val; + dev->enetaddr[1] = (unsigned char)(macid0_val >> 8); + dev->enetaddr[2] = (unsigned char)macid1_val; + dev->enetaddr[3] = (unsigned char)(macid1_val >> 8); + dev->enetaddr[4] = (unsigned char)macid2_val; + dev->enetaddr[5] = (unsigned char)(macid2_val >> 8); + } +} + +/* +=========================================================================== +<<<<<< Exported SubProgram Bodies >>>>>> +=========================================================================== +*/ +int ax88180_initialize (bd_t * bis) +{ + struct eth_device *dev; + struct ax88180_private *priv; + + dev = (struct eth_device *)malloc (sizeof *dev); + + if (NULL == dev) + return 0; + + memset (dev, 0, sizeof *dev); + + priv = (struct ax88180_private *)malloc (sizeof (*priv)); + + if (NULL == priv) + return 0; + + memset (priv, 0, sizeof *priv); + + sprintf (dev->name, "ax88180"); + dev->iobase = AX88180_BASE; + dev->priv = priv; + dev->init = ax88180_init; + dev->halt = ax88180_halt; + dev->send = ax88180_send; + dev->recv = ax88180_recv; + + priv->BusWidth = BUS_WIDTH_32; + priv->PadSize = 3; +#if defined (CONFIG_DRIVER_AX88180_16BIT) + OUTW (dev, (START_BASE >> 8), BASE); + OUTW (dev, DECODE_EN, DECODE); + + priv->BusWidth = BUS_WIDTH_16; + priv->PadSize = 1; +#endif + + ax88180_mac_reset (dev); + + /* Disable interrupt */ + OUTW (dev, CLEAR_IMR, IMR); + + /* Disable AX88180 TX/RX functions */ + OUTW (dev, WAKEMOD, CMD); + + ax88180_read_mac_addr (dev); + + eth_register (dev); + + return ax88180_phy_initial (dev); + +} diff --git a/sources/uboot-be550/drivers/net/ax88180.h b/sources/uboot-be550/drivers/net/ax88180.h new file mode 100644 index 00000000..daf18e01 --- /dev/null +++ b/sources/uboot-be550/drivers/net/ax88180.h @@ -0,0 +1,396 @@ +/* ax88180.h: ASIX AX88180 Non-PCI Gigabit Ethernet u-boot driver */ +/* + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + */ + +#ifndef _AX88180_H_ +#define _AX88180_H_ + +#include +#include +#include + +typedef enum _ax88180_link_state { + INS_LINK_DOWN, + INS_LINK_UP, + INS_LINK_UNKNOWN +} ax88180_link_state; + +struct ax88180_private { + unsigned char BusWidth; + unsigned char PadSize; + unsigned short PhyAddr; + unsigned short PhyID0; + unsigned short PhyID1; + unsigned short FirstTxDesc; + unsigned short NextTxDesc; + ax88180_link_state LinkState; +}; + +#define BUS_WIDTH_16 1 +#define BUS_WIDTH_32 2 + +#define ENABLE_JUMBO 1 +#define DISABLE_JUMBO 0 + +#define ENABLE_BURST 1 +#define DISABLE_BURST 0 + +#define NORMAL_RX_MODE 0 +#define RX_LOOPBACK_MODE 1 +#define RX_INIFINIT_LOOP_MODE 2 +#define TX_INIFINIT_LOOP_MODE 3 + +#define DEFAULT_ETH_MTU 1500 + +/* Jumbo packet size 4086 bytes included 4 bytes CRC*/ +#define MAX_JUMBO_MTU 4072 + +/* Max Tx Jumbo size 4086 bytes included 4 bytes CRC */ +#define MAX_TX_JUMBO_SIZE 4086 + +/* Max Rx Jumbo size is 15K Bytes */ +#define MAX_RX_SIZE 0x3C00 + +#define MARVELL_ALASKA_PHYSID0 0x141 +#define MARVELL_88E1118_PHYSID1 0xE40 + +#define CICADA_CIS8201_PHYSID0 0x000F + +#define MEDIA_AUTO 0 +#define MEDIA_1000FULL 1 +#define MEDIA_1000HALF 2 +#define MEDIA_100FULL 3 +#define MEDIA_100HALF 4 +#define MEDIA_10FULL 5 +#define MEDIA_10HALF 6 +#define MEDIA_UNKNOWN 7 + +#define AUTO_MEDIA 0 +#define FORCE_MEDIA 1 + +#define TXDP_MASK 3 +#define TXDP0 0 +#define TXDP1 1 +#define TXDP2 2 +#define TXDP3 3 + +#define CMD_MAP_SIZE 0x100 + +#if defined (CONFIG_DRIVER_AX88180_16BIT) + #define AX88180_MEMORY_SIZE 0x00004000 + #define START_BASE 0x1000 + + #define RX_BUF_SIZE 0x1000 + #define TX_BUF_SIZE 0x0F00 + + #define TX_BASE START_BASE + #define CMD_BASE (TX_BASE + TX_BUF_SIZE) + #define RX_BASE (CMD_BASE + CMD_MAP_SIZE) +#else + #define AX88180_MEMORY_SIZE 0x00010000 + + #define RX_BUF_SIZE 0x8000 + #define TX_BUF_SIZE 0x7C00 + + #define RX_BASE 0x0000 + #define TX_BASE (RX_BASE + RX_BUF_SIZE) + #define CMD_BASE (TX_BASE + TX_BUF_SIZE) +#endif + +/* AX88180 Memory Mapping Definition */ +#define RXBUFFER_START RX_BASE + #define RX_PACKET_LEN_OFFSET 0 + #define RX_PAGE_NUM_MASK 0x7FF /* RX pages 0~7FFh */ +#define TXBUFFER_START TX_BASE + +/* AX88180 MAC Register Definition */ +#define DECODE (0) + #define DECODE_EN 0x00000001 +#define BASE (6) +#define CMD (CMD_BASE + 0x0000) + #define WAKEMOD 0x00000001 + #define TXEN 0x00000100 + #define RXEN 0x00000200 + #define DEFAULT_CMD WAKEMOD +#define IMR (CMD_BASE + 0x0004) + #define IMR_RXBUFFOVR 0x00000001 + #define IMR_WATCHDOG 0x00000002 + #define IMR_TX 0x00000008 + #define IMR_RX 0x00000010 + #define IMR_PHY 0x00000020 + #define CLEAR_IMR 0x00000000 + #define DEFAULT_IMR (IMR_PHY | IMR_RX | IMR_TX |\ + IMR_RXBUFFOVR | IMR_WATCHDOG) +#define ISR (CMD_BASE + 0x0008) + #define ISR_RXBUFFOVR 0x00000001 + #define ISR_WATCHDOG 0x00000002 + #define ISR_TX 0x00000008 + #define ISR_RX 0x00000010 + #define ISR_PHY 0x00000020 +#define TXCFG (CMD_BASE + 0x0010) + #define AUTOPAD_CRC 0x00000050 + #define DEFAULT_TXCFG AUTOPAD_CRC +#define TXCMD (CMD_BASE + 0x0014) + #define TXCMD_TXDP_MASK 0x00006000 + #define TXCMD_TXDP0 0x00000000 + #define TXCMD_TXDP1 0x00002000 + #define TXCMD_TXDP2 0x00004000 + #define TXCMD_TXDP3 0x00006000 + #define TX_START_WRITE 0x00008000 + #define TX_STOP_WRITE 0x00000000 + #define DEFAULT_TXCMD 0x00000000 +#define TXBS (CMD_BASE + 0x0018) + #define TXDP0_USED 0x00000001 + #define TXDP1_USED 0x00000002 + #define TXDP2_USED 0x00000004 + #define TXDP3_USED 0x00000008 + #define DEFAULT_TXBS 0x00000000 +#define TXDES0 (CMD_BASE + 0x0020) + #define TXDPx_ENABLE 0x00008000 + #define TXDPx_LEN_MASK 0x00001FFF + #define DEFAULT_TXDES0 0x00000000 +#define TXDES1 (CMD_BASE + 0x0024) + #define TXDPx_ENABLE 0x00008000 + #define TXDPx_LEN_MASK 0x00001FFF + #define DEFAULT_TXDES1 0x00000000 +#define TXDES2 (CMD_BASE + 0x0028) + #define TXDPx_ENABLE 0x00008000 + #define TXDPx_LEN_MASK 0x00001FFF + #define DEFAULT_TXDES2 0x00000000 +#define TXDES3 (CMD_BASE + 0x002C) + #define TXDPx_ENABLE 0x00008000 + #define TXDPx_LEN_MASK 0x00001FFF + #define DEFAULT_TXDES3 0x00000000 +#define RXCFG (CMD_BASE + 0x0030) + #define RXBUFF_PROTECT 0x00000001 + #define RXTCPCRC_CHECK 0x00000010 + #define RXFLOW_ENABLE 0x00000100 + #define DEFAULT_RXCFG RXBUFF_PROTECT +#define RXCURT (CMD_BASE + 0x0034) + #define DEFAULT_RXCURT 0x00000000 +#define RXBOUND (CMD_BASE + 0x0038) + #define DEFAULT_RXBOUND 0x7FF /* RX pages 0~7FFh */ +#define MACCFG0 (CMD_BASE + 0x0040) + #define MACCFG0_BIT3_0 0x00000007 + #define IPGT_VAL 0x00000150 + #define TXFLOW_ENABLE 0x00001000 + #define SPEED100 0x00008000 + #define DEFAULT_MACCFG0 (IPGT_VAL | MACCFG0_BIT3_0) +#define MACCFG1 (CMD_BASE + 0x0044) + #define RGMII_EN 0x00000002 + #define RXFLOW_EN 0x00000020 + #define FULLDUPLEX 0x00000040 + #define MAX_JUMBO_LEN 0x00000780 + #define RXJUMBO_EN 0x00000800 + #define GIGA_MODE_EN 0x00001000 + #define RXCRC_CHECK 0x00002000 + #define RXPAUSE_DA_CHECK 0x00004000 + + #define JUMBO_LEN_4K 0x00000200 + #define JUMBO_LEN_15K 0x00000780 + #define DEFAULT_MACCFG1 (RXCRC_CHECK | RXPAUSE_DA_CHECK | \ + RGMII_EN) + #define CICADA_DEFAULT_MACCFG1 (RXCRC_CHECK | RXPAUSE_DA_CHECK) +#define MACCFG2 (CMD_BASE + 0x0048) + #define MACCFG2_BIT15_8 0x00000100 + #define JAM_LIMIT_MASK 0x000000FC + #define DEFAULT_JAM_LIMIT 0x00000064 + #define DEFAULT_MACCFG2 MACCFG2_BIT15_8 +#define MACCFG3 (CMD_BASE + 0x004C) + #define IPGR2_VAL 0x0000000E + #define IPGR1_VAL 0x00000600 + #define NOABORT 0x00008000 + #define DEFAULT_MACCFG3 (IPGR1_VAL | IPGR2_VAL) +#define TXPAUT (CMD_BASE + 0x0054) + #define DEFAULT_TXPAUT 0x001FE000 +#define RXBTHD0 (CMD_BASE + 0x0058) + #define DEFAULT_RXBTHD0 0x00000300 +#define RXBTHD1 (CMD_BASE + 0x005C) + #define DEFAULT_RXBTHD1 0x00000600 +#define RXFULTHD (CMD_BASE + 0x0060) + #define DEFAULT_RXFULTHD 0x00000100 +#define MISC (CMD_BASE + 0x0068) + /* Normal operation mode */ + #define MISC_NORMAL 0x00000003 + /* Clear bit 0 to reset MAC */ + #define MISC_RESET_MAC 0x00000002 + /* Clear bit 1 to reset PHY */ + #define MISC_RESET_PHY 0x00000001 + /* Clear bit 0 and 1 to reset MAC and PHY */ + #define MISC_RESET_MAC_PHY 0x00000000 + #define DEFAULT_MISC MISC_NORMAL +#define MACID0 (CMD_BASE + 0x0070) +#define MACID1 (CMD_BASE + 0x0074) +#define MACID2 (CMD_BASE + 0x0078) +#define TXLEN (CMD_BASE + 0x007C) + #define DEFAULT_TXLEN 0x000005FC +#define RXFILTER (CMD_BASE + 0x0080) + #define RX_RXANY 0x00000001 + #define RX_MULTICAST 0x00000002 + #define RX_UNICAST 0x00000004 + #define RX_BROADCAST 0x00000008 + #define RX_MULTI_HASH 0x00000010 + #define DISABLE_RXFILTER 0x00000000 + #define DEFAULT_RXFILTER (RX_BROADCAST + RX_UNICAST) +#define MDIOCTRL (CMD_BASE + 0x0084) + #define PHY_ADDR_MASK 0x0000001F + #define REG_ADDR_MASK 0x00001F00 + #define READ_PHY 0x00004000 + #define WRITE_PHY 0x00008000 +#define MDIODP (CMD_BASE + 0x0088) +#define GPIOCTRL (CMD_BASE + 0x008C) +#define RXINDICATOR (CMD_BASE + 0x0090) + #define RX_START_READ 0x00000001 + #define RX_STOP_READ 0x00000000 + #define DEFAULT_RXINDICATOR RX_STOP_READ +#define TXST (CMD_BASE + 0x0094) +#define MDCCLKPAT (CMD_BASE + 0x00A0) +#define RXIPCRCCNT (CMD_BASE + 0x00A4) +#define RXCRCCNT (CMD_BASE + 0x00A8) +#define TXFAILCNT (CMD_BASE + 0x00AC) +#define PROMDP (CMD_BASE + 0x00B0) +#define PROMCTRL (CMD_BASE + 0x00B4) + #define RELOAD_EEPROM 0x00000200 +#define MAXRXLEN (CMD_BASE + 0x00B8) +#define HASHTAB0 (CMD_BASE + 0x00C0) +#define HASHTAB1 (CMD_BASE + 0x00C4) +#define HASHTAB2 (CMD_BASE + 0x00C8) +#define HASHTAB3 (CMD_BASE + 0x00CC) +#define DOGTHD0 (CMD_BASE + 0x00E0) + #define DEFAULT_DOGTHD0 0x0000FFFF +#define DOGTHD1 (CMD_BASE + 0x00E4) + #define START_WATCHDOG_TIMER 0x00008000 + #define DEFAULT_DOGTHD1 0x00000FFF +#define SOFTRST (CMD_BASE + 0x00EC) + #define SOFTRST_NORMAL 0x00000003 + #define SOFTRST_RESET_MAC 0x00000002 + +/* Marvell 88E1111 Gigabit PHY Register Definition */ +#define M88_SSR 0x0011 + #define SSR_SPEED_MASK 0xC000 + #define SSR_SPEED_1000 0x8000 + #define SSR_SPEED_100 0x4000 + #define SSR_SPEED_10 0x0000 + #define SSR_DUPLEX 0x2000 + #define SSR_MEDIA_RESOLVED_OK 0x0800 + + #define SSR_MEDIA_MASK (SSR_SPEED_MASK | SSR_DUPLEX) + #define SSR_1000FULL (SSR_SPEED_1000 | SSR_DUPLEX) + #define SSR_1000HALF SSR_SPEED_1000 + #define SSR_100FULL (SSR_SPEED_100 | SSR_DUPLEX) + #define SSR_100HALF SSR_SPEED_100 + #define SSR_10FULL (SSR_SPEED_10 | SSR_DUPLEX) + #define SSR_10HALF SSR_SPEED_10 +#define M88_IER 0x0012 + #define LINK_CHANGE_INT 0x0400 +#define M88_ISR 0x0013 + #define LINK_CHANGE_STATUS 0x0400 +#define M88E1111_EXT_SCR 0x0014 + #define RGMII_RXCLK_DELAY 0x0080 + #define RGMII_TXCLK_DELAY 0x0002 + #define DEFAULT_EXT_SCR (RGMII_TXCLK_DELAY | RGMII_RXCLK_DELAY) +#define M88E1111_EXT_SSR 0x001B + #define HWCFG_MODE_MASK 0x000F + #define RGMII_COPPER_MODE 0x000B + +/* Marvell 88E1118 Gigabit PHY Register Definition */ +#define M88E1118_CR 0x14 + #define M88E1118_CR_RGMII_RXCLK_DELAY 0x0020 + #define M88E1118_CR_RGMII_TXCLK_DELAY 0x0010 + #define M88E1118_CR_DEFAULT (M88E1118_CR_RGMII_TXCLK_DELAY | \ + M88E1118_CR_RGMII_RXCLK_DELAY) +#define M88E1118_LEDCTL 0x10 /* Reg 16 on page 3 */ + #define M88E1118_LEDCTL_LED2INT 0x200 + #define M88E1118_LEDCTL_LED2BLNK 0x400 + #define M88E1118_LEDCTL_LED0DUALMODE1 0xc + #define M88E1118_LEDCTL_LED0DUALMODE2 0xd + #define M88E1118_LEDCTL_LED0DUALMODE3 0xe + #define M88E1118_LEDCTL_LED0DUALMODE4 0xf + #define M88E1118_LEDCTL_DEFAULT (M88E1118_LEDCTL_LED2BLNK | \ + M88E1118_LEDCTL_LED0DUALMODE4) + +#define M88E1118_LEDMIX 0x11 /* Reg 17 on page 3 */ + #define M88E1118_LEDMIX_LED050 0x4 + #define M88E1118_LEDMIX_LED150 0x8 + +#define M88E1118_PAGE_SEL 0x16 /* Reg page select */ + +/* CICADA CIS8201 Gigabit PHY Register Definition */ +#define CIS_IMR 0x0019 + #define CIS_INT_ENABLE 0x8000 + #define CIS_LINK_CHANGE_INT 0x2000 +#define CIS_ISR 0x001A + #define CIS_INT_PENDING 0x8000 + #define CIS_LINK_CHANGE_STATUS 0x2000 +#define CIS_AUX_CTRL_STATUS 0x001C + #define CIS_AUTONEG_COMPLETE 0x8000 + #define CIS_SPEED_MASK 0x0018 + #define CIS_SPEED_1000 0x0010 + #define CIS_SPEED_100 0x0008 + #define CIS_SPEED_10 0x0000 + #define CIS_DUPLEX 0x0020 + + #define CIS_MEDIA_MASK (CIS_SPEED_MASK | CIS_DUPLEX) + #define CIS_1000FULL (CIS_SPEED_1000 | CIS_DUPLEX) + #define CIS_1000HALF CIS_SPEED_1000 + #define CIS_100FULL (CIS_SPEED_100 | CIS_DUPLEX) + #define CIS_100HALF CIS_SPEED_100 + #define CIS_10FULL (CIS_SPEED_10 | CIS_DUPLEX) + #define CIS_10HALF CIS_SPEED_10 + #define CIS_SMI_PRIORITY 0x0004 + +static inline unsigned short INW (struct eth_device *dev, unsigned long addr) +{ + return le16_to_cpu(readw(addr + (void *)dev->iobase)); +} + +/* + Access RXBUFFER_START/TXBUFFER_START to read RX buffer/write TX buffer +*/ +#if defined (CONFIG_DRIVER_AX88180_16BIT) +static inline void OUTW (struct eth_device *dev, unsigned short command, unsigned long addr) +{ + writew(cpu_to_le16(command), addr + (void *)dev->iobase); +} + +static inline unsigned short READ_RXBUF (struct eth_device *dev) +{ + return le16_to_cpu(readw(RXBUFFER_START + (void *)dev->iobase)); +} + +static inline void WRITE_TXBUF (struct eth_device *dev, unsigned short data) +{ + writew(cpu_to_le16(data), TXBUFFER_START + (void *)dev->iobase); +} +#else +static inline void OUTW (struct eth_device *dev, unsigned short command, unsigned long addr) +{ + writel(cpu_to_le32(command), addr + (void *)dev->iobase); +} + +static inline unsigned long READ_RXBUF (struct eth_device *dev) +{ + return le32_to_cpu(readl(RXBUFFER_START + (void *)dev->iobase)); +} + +static inline void WRITE_TXBUF (struct eth_device *dev, unsigned long data) +{ + writel(cpu_to_le32(data), TXBUFFER_START + (void *)dev->iobase); +} +#endif + +#endif /* _AX88180_H_ */ diff --git a/sources/uboot-be550/drivers/net/ax88796.c b/sources/uboot-be550/drivers/net/ax88796.c new file mode 100644 index 00000000..c45f6461 --- /dev/null +++ b/sources/uboot-be550/drivers/net/ax88796.c @@ -0,0 +1,144 @@ +/* + * (c) 2007 Nobuhiro Iwamatsu + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include "ax88796.h" + +/* + * Set 1 bit data + */ +static void ax88796_bitset(u32 bit) +{ + /* DATA1 */ + if( bit ) + EEDI_HIGH; + else + EEDI_LOW; + + EECLK_LOW; + udelay(1000); + EECLK_HIGH; + udelay(1000); + EEDI_LOW; +} + +/* + * Get 1 bit data + */ +static u8 ax88796_bitget(void) +{ + u8 bit; + + EECLK_LOW; + udelay(1000); + /* DATA */ + bit = EEDO; + EECLK_HIGH; + udelay(1000); + + return bit; +} + +/* + * Send COMMAND to EEPROM + */ +static void ax88796_eep_cmd(u8 cmd) +{ + ax88796_bitset(BIT_DUMMY); + switch(cmd){ + case MAC_EEP_READ: + ax88796_bitset(1); + ax88796_bitset(1); + ax88796_bitset(0); + break; + + case MAC_EEP_WRITE: + ax88796_bitset(1); + ax88796_bitset(0); + ax88796_bitset(1); + break; + + case MAC_EEP_ERACE: + ax88796_bitset(1); + ax88796_bitset(1); + ax88796_bitset(1); + break; + + case MAC_EEP_EWEN: + ax88796_bitset(1); + ax88796_bitset(0); + ax88796_bitset(0); + break; + + case MAC_EEP_EWDS: + ax88796_bitset(1); + ax88796_bitset(0); + ax88796_bitset(0); + break; + default: + break; + } +} + +static void ax88796_eep_setaddr(u16 addr) +{ + int i ; + + for( i = 7 ; i >= 0 ; i-- ) + ax88796_bitset(addr & (1 << i)); +} + +/* + * Get data from EEPROM + */ +static u16 ax88796_eep_getdata(void) +{ + ushort data = 0; + int i; + + ax88796_bitget(); /* DUMMY */ + for( i = 0 ; i < 16 ; i++ ){ + data <<= 1; + data |= ax88796_bitget(); + } + return data; +} + +static void ax88796_mac_read(u8 *buff) +{ + int i ; + u16 data; + u16 addr = 0; + + for( i = 0 ; i < 3; i++ ) + { + EECS_HIGH; + EEDI_LOW; + udelay(1000); + /* READ COMMAND */ + ax88796_eep_cmd(MAC_EEP_READ); + /* ADDRESS */ + ax88796_eep_setaddr(addr++); + /* GET DATA */ + data = ax88796_eep_getdata(); + *buff++ = (uchar)(data & 0xff); + *buff++ = (uchar)((data >> 8) & 0xff); + EECLK_LOW; + EEDI_LOW; + EECS_LOW; + } +} + +int get_prom(u8* mac_addr, u8* base_addr) +{ + u8 prom[32]; + int i; + + ax88796_mac_read(prom); + for (i = 0; i < 6; i++){ + mac_addr[i] = prom[i]; + } + return 1; +} diff --git a/sources/uboot-be550/drivers/net/ax88796.h b/sources/uboot-be550/drivers/net/ax88796.h new file mode 100644 index 00000000..2b4e05af --- /dev/null +++ b/sources/uboot-be550/drivers/net/ax88796.h @@ -0,0 +1,67 @@ +/* + * AX88796L(NE2000) support + * + * (c) 2007 Nobuhiro Iwamatsu + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DRIVERS_AX88796L_H__ +#define __DRIVERS_AX88796L_H__ + +#define DP_DATA (0x10 << 1) +#define START_PG 0x40 /* First page of TX buffer */ +#define START_PG2 0x48 +#define STOP_PG 0x80 /* Last page +1 of RX ring */ +#define TX_PAGES 12 +#define RX_START (START_PG+TX_PAGES) +#define RX_END STOP_PG + +#define AX88796L_BASE_ADDRESS CONFIG_DRIVER_NE2000_BASE +#define AX88796L_BYTE_ACCESS 0x00001000 +#define AX88796L_OFFSET 0x00000400 +#define AX88796L_ADDRESS_BYTE AX88796L_BASE_ADDRESS + \ + AX88796L_BYTE_ACCESS + AX88796L_OFFSET +#define AX88796L_REG_MEMR AX88796L_ADDRESS_BYTE + (0x14<<1) +#define AX88796L_REG_CR AX88796L_ADDRESS_BYTE + (0x00<<1) + +#define AX88796L_CR (*(vu_short *)(AX88796L_REG_CR)) +#define AX88796L_MEMR (*(vu_short *)(AX88796L_REG_MEMR)) + +#define EECS_HIGH (AX88796L_MEMR |= 0x10) +#define EECS_LOW (AX88796L_MEMR &= 0xef) +#define EECLK_HIGH (AX88796L_MEMR |= 0x80) +#define EECLK_LOW (AX88796L_MEMR &= 0x7f) +#define EEDI_HIGH (AX88796L_MEMR |= 0x20) +#define EEDI_LOW (AX88796L_MEMR &= 0xdf) +#define EEDO ((AX88796L_MEMR & 0x40)>>6) + +#define PAGE0_SET (AX88796L_CR &= 0x3f) +#define PAGE1_SET (AX88796L_CR = (AX88796L_CR & 0x3f) | 0x40) + +#define BIT_DUMMY 0 +#define MAC_EEP_READ 1 +#define MAC_EEP_WRITE 2 +#define MAC_EEP_ERACE 3 +#define MAC_EEP_EWEN 4 +#define MAC_EEP_EWDS 5 + +/* R7780MP Specific code */ +#if defined(CONFIG_R7780MP) +#define ISA_OFFSET 0x1400 +#define DP_IN(_b_, _o_, _d_) (_d_) = \ + *( (vu_short *) ((_b_) + ((_o_) * 2) + ISA_OFFSET)) +#define DP_OUT(_b_, _o_, _d_) \ + *((vu_short *)((_b_) + ((_o_) * 2) + ISA_OFFSET)) = (_d_) +#define DP_IN_DATA(_b_, _d_) (_d_) = *( (vu_short *) ((_b_) + ISA_OFFSET)) +#define DP_OUT_DATA(_b_, _d_) *( (vu_short *) ((_b_)+ISA_OFFSET)) = (_d_) +#else +/* Please change for your target boards */ +#define ISA_OFFSET 0x0000 +#define DP_IN(_b_, _o_, _d_) (_d_) = *( (vu_short *)((_b_)+(_o_ )+ISA_OFFSET)) +#define DP_OUT(_b_, _o_, _d_) *((vu_short *)((_b_)+(_o_)+ISA_OFFSET)) = (_d_) +#define DP_IN_DATA(_b_, _d_) (_d_) = *( (vu_short *) ((_b_)+ISA_OFFSET)) +#define DP_OUT_DATA(_b_, _d_) *( (vu_short *) ((_b_)+ISA_OFFSET)) = (_d_) +#endif + +#endif /* __DRIVERS_AX88796L_H__ */ diff --git a/sources/uboot-be550/drivers/net/bcm-sf2-eth-gmac.c b/sources/uboot-be550/drivers/net/bcm-sf2-eth-gmac.c new file mode 100644 index 00000000..977feec3 --- /dev/null +++ b/sources/uboot-be550/drivers/net/bcm-sf2-eth-gmac.c @@ -0,0 +1,971 @@ +/* + * Copyright 2014 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifdef BCM_GMAC_DEBUG +#ifndef DEBUG +#define DEBUG +#endif +#endif + +#include +#include +#include +#include +#include +#include + +#include "bcm-sf2-eth.h" +#include "bcm-sf2-eth-gmac.h" + +#define SPINWAIT(exp, us) { \ + uint countdown = (us) + 9; \ + while ((exp) && (countdown >= 10)) {\ + udelay(10); \ + countdown -= 10; \ + } \ +} + +static int gmac_disable_dma(struct eth_dma *dma, int dir); +static int gmac_enable_dma(struct eth_dma *dma, int dir); + +/* DMA Descriptor */ +typedef struct { + /* misc control bits */ + uint32_t ctrl1; + /* buffer count and address extension */ + uint32_t ctrl2; + /* memory address of the date buffer, bits 31:0 */ + uint32_t addrlow; + /* memory address of the date buffer, bits 63:32 */ + uint32_t addrhigh; +} dma64dd_t; + +uint32_t g_dmactrlflags; + +static uint32_t dma_ctrlflags(uint32_t mask, uint32_t flags) +{ + debug("%s enter\n", __func__); + + g_dmactrlflags &= ~mask; + g_dmactrlflags |= flags; + + /* If trying to enable parity, check if parity is actually supported */ + if (g_dmactrlflags & DMA_CTRL_PEN) { + uint32_t control; + + control = readl(GMAC0_DMA_TX_CTRL_ADDR); + writel(control | D64_XC_PD, GMAC0_DMA_TX_CTRL_ADDR); + if (readl(GMAC0_DMA_TX_CTRL_ADDR) & D64_XC_PD) { + /* + * We *can* disable it, therefore it is supported; + * restore control register + */ + writel(control, GMAC0_DMA_TX_CTRL_ADDR); + } else { + /* Not supported, don't allow it to be enabled */ + g_dmactrlflags &= ~DMA_CTRL_PEN; + } + } + + return g_dmactrlflags; +} + +static inline void reg32_clear_bits(uint32_t reg, uint32_t value) +{ + uint32_t v = readl(reg); + v &= ~(value); + writel(v, reg); +} + +static inline void reg32_set_bits(uint32_t reg, uint32_t value) +{ + uint32_t v = readl(reg); + v |= value; + writel(v, reg); +} + +#ifdef BCM_GMAC_DEBUG +static void dma_tx_dump(struct eth_dma *dma) +{ + dma64dd_t *descp = NULL; + uint8_t *bufp; + int i; + + printf("TX DMA Register:\n"); + printf("control:0x%x; ptr:0x%x; addrl:0x%x; addrh:0x%x; stat0:0x%x, stat1:0x%x\n", + readl(GMAC0_DMA_TX_CTRL_ADDR), + readl(GMAC0_DMA_TX_PTR_ADDR), + readl(GMAC0_DMA_TX_ADDR_LOW_ADDR), + readl(GMAC0_DMA_TX_ADDR_HIGH_ADDR), + readl(GMAC0_DMA_TX_STATUS0_ADDR), + readl(GMAC0_DMA_TX_STATUS1_ADDR)); + + printf("TX Descriptors:\n"); + for (i = 0; i < TX_BUF_NUM; i++) { + descp = (dma64dd_t *)(dma->tx_desc_aligned) + i; + printf("ctrl1:0x%08x; ctrl2:0x%08x; addr:0x%x 0x%08x\n", + descp->ctrl1, descp->ctrl2, + descp->addrhigh, descp->addrlow); + } + + printf("TX Buffers:\n"); + /* Initialize TX DMA descriptor table */ + for (i = 0; i < TX_BUF_NUM; i++) { + bufp = (uint8_t *)(dma->tx_buf + i * TX_BUF_SIZE); + printf("buf%d:0x%x; ", i, (uint32_t)bufp); + } + printf("\n"); +} + +static void dma_rx_dump(struct eth_dma *dma) +{ + dma64dd_t *descp = NULL; + uint8_t *bufp; + int i; + + printf("RX DMA Register:\n"); + printf("control:0x%x; ptr:0x%x; addrl:0x%x; addrh:0x%x; stat0:0x%x, stat1:0x%x\n", + readl(GMAC0_DMA_RX_CTRL_ADDR), + readl(GMAC0_DMA_RX_PTR_ADDR), + readl(GMAC0_DMA_RX_ADDR_LOW_ADDR), + readl(GMAC0_DMA_RX_ADDR_HIGH_ADDR), + readl(GMAC0_DMA_RX_STATUS0_ADDR), + readl(GMAC0_DMA_RX_STATUS1_ADDR)); + + printf("RX Descriptors:\n"); + for (i = 0; i < RX_BUF_NUM; i++) { + descp = (dma64dd_t *)(dma->rx_desc_aligned) + i; + printf("ctrl1:0x%08x; ctrl2:0x%08x; addr:0x%x 0x%08x\n", + descp->ctrl1, descp->ctrl2, + descp->addrhigh, descp->addrlow); + } + + printf("RX Buffers:\n"); + for (i = 0; i < RX_BUF_NUM; i++) { + bufp = dma->rx_buf + i * RX_BUF_SIZE; + printf("buf%d:0x%x; ", i, (uint32_t)bufp); + } + printf("\n"); +} +#endif + +static int dma_tx_init(struct eth_dma *dma) +{ + dma64dd_t *descp = NULL; + uint8_t *bufp; + int i; + uint32_t ctrl; + + debug("%s enter\n", __func__); + + /* clear descriptor memory */ + memset((void *)(dma->tx_desc_aligned), 0, + TX_BUF_NUM * sizeof(dma64dd_t)); + memset(dma->tx_buf, 0, TX_BUF_NUM * TX_BUF_SIZE); + + /* Initialize TX DMA descriptor table */ + for (i = 0; i < TX_BUF_NUM; i++) { + descp = (dma64dd_t *)(dma->tx_desc_aligned) + i; + bufp = dma->tx_buf + i * TX_BUF_SIZE; + /* clear buffer memory */ + memset((void *)bufp, 0, TX_BUF_SIZE); + + ctrl = 0; + /* if last descr set endOfTable */ + if (i == (TX_BUF_NUM-1)) + ctrl = D64_CTRL1_EOT; + descp->ctrl1 = ctrl; + descp->ctrl2 = 0; + descp->addrlow = (uint32_t)bufp; + descp->addrhigh = 0; + } + + /* flush descriptor and buffer */ + descp = dma->tx_desc_aligned; + bufp = dma->tx_buf; + flush_dcache_range((unsigned long)descp, + (unsigned long)(descp + + sizeof(dma64dd_t) * TX_BUF_NUM)); + flush_dcache_range((unsigned long)(bufp), + (unsigned long)(bufp + TX_BUF_SIZE * TX_BUF_NUM)); + + /* initialize the DMA channel */ + writel((uint32_t)(dma->tx_desc_aligned), GMAC0_DMA_TX_ADDR_LOW_ADDR); + writel(0, GMAC0_DMA_TX_ADDR_HIGH_ADDR); + + /* now update the dma last descriptor */ + writel(((uint32_t)(dma->tx_desc_aligned)) & D64_XP_LD_MASK, + GMAC0_DMA_TX_PTR_ADDR); + + return 0; +} + +static int dma_rx_init(struct eth_dma *dma) +{ + uint32_t last_desc; + dma64dd_t *descp = NULL; + uint8_t *bufp; + uint32_t ctrl; + int i; + + debug("%s enter\n", __func__); + + /* clear descriptor memory */ + memset((void *)(dma->rx_desc_aligned), 0, + RX_BUF_NUM * sizeof(dma64dd_t)); + /* clear buffer memory */ + memset(dma->rx_buf, 0, RX_BUF_NUM * RX_BUF_SIZE); + + /* Initialize RX DMA descriptor table */ + for (i = 0; i < RX_BUF_NUM; i++) { + descp = (dma64dd_t *)(dma->rx_desc_aligned) + i; + bufp = dma->rx_buf + i * RX_BUF_SIZE; + ctrl = 0; + /* if last descr set endOfTable */ + if (i == (RX_BUF_NUM - 1)) + ctrl = D64_CTRL1_EOT; + descp->ctrl1 = ctrl; + descp->ctrl2 = RX_BUF_SIZE; + descp->addrlow = (uint32_t)bufp; + descp->addrhigh = 0; + + last_desc = ((uint32_t)(descp) & D64_XP_LD_MASK) + + sizeof(dma64dd_t); + } + + descp = dma->rx_desc_aligned; + bufp = dma->rx_buf; + /* flush descriptor and buffer */ + flush_dcache_range((unsigned long)descp, + (unsigned long)(descp + + sizeof(dma64dd_t) * RX_BUF_NUM)); + flush_dcache_range((unsigned long)(bufp), + (unsigned long)(bufp + RX_BUF_SIZE * RX_BUF_NUM)); + + /* initailize the DMA channel */ + writel((uint32_t)descp, GMAC0_DMA_RX_ADDR_LOW_ADDR); + writel(0, GMAC0_DMA_RX_ADDR_HIGH_ADDR); + + /* now update the dma last descriptor */ + writel(last_desc, GMAC0_DMA_RX_PTR_ADDR); + + return 0; +} + +static int dma_init(struct eth_dma *dma) +{ + debug(" %s enter\n", __func__); + + /* + * Default flags: For backwards compatibility both + * Rx Overflow Continue and Parity are DISABLED. + */ + dma_ctrlflags(DMA_CTRL_ROC | DMA_CTRL_PEN, 0); + + debug("rx burst len 0x%x\n", + (readl(GMAC0_DMA_RX_CTRL_ADDR) & D64_RC_BL_MASK) + >> D64_RC_BL_SHIFT); + debug("tx burst len 0x%x\n", + (readl(GMAC0_DMA_TX_CTRL_ADDR) & D64_XC_BL_MASK) + >> D64_XC_BL_SHIFT); + + dma_tx_init(dma); + dma_rx_init(dma); + + /* From end of chip_init() */ + /* enable the overflow continue feature and disable parity */ + dma_ctrlflags(DMA_CTRL_ROC | DMA_CTRL_PEN /* mask */, + DMA_CTRL_ROC /* value */); + + return 0; +} + +static int dma_deinit(struct eth_dma *dma) +{ + debug(" %s enter\n", __func__); + + gmac_disable_dma(dma, MAC_DMA_RX); + gmac_disable_dma(dma, MAC_DMA_TX); + + free(dma->tx_buf); + dma->tx_buf = NULL; + free(dma->tx_desc); + dma->tx_desc = NULL; + dma->tx_desc_aligned = NULL; + + free(dma->rx_buf); + dma->rx_buf = NULL; + free(dma->rx_desc); + dma->rx_desc = NULL; + dma->rx_desc_aligned = NULL; + + return 0; +} + +int gmac_tx_packet(struct eth_dma *dma, void *packet, int length) +{ + uint8_t *bufp = dma->tx_buf + dma->cur_tx_index * TX_BUF_SIZE; + + /* kick off the dma */ + size_t len = length; + int txout = dma->cur_tx_index; + uint32_t flags; + dma64dd_t *descp = NULL; + uint32_t ctrl; + uint32_t last_desc = (((uint32_t)dma->tx_desc_aligned) + + sizeof(dma64dd_t)) & D64_XP_LD_MASK; + size_t buflen; + + debug("%s enter\n", __func__); + + /* load the buffer */ + memcpy(bufp, packet, len); + + /* Add 4 bytes for Ethernet FCS/CRC */ + buflen = len + 4; + + ctrl = (buflen & D64_CTRL2_BC_MASK); + + /* the transmit will only be one frame or set SOF, EOF */ + /* also set int on completion */ + flags = D64_CTRL1_SOF | D64_CTRL1_IOC | D64_CTRL1_EOF; + + /* txout points to the descriptor to uset */ + /* if last descriptor then set EOT */ + if (txout == (TX_BUF_NUM - 1)) { + flags |= D64_CTRL1_EOT; + last_desc = ((uint32_t)(dma->tx_desc_aligned)) & D64_XP_LD_MASK; + } + + /* write the descriptor */ + descp = ((dma64dd_t *)(dma->tx_desc_aligned)) + txout; + descp->addrlow = (uint32_t)bufp; + descp->addrhigh = 0; + descp->ctrl1 = flags; + descp->ctrl2 = ctrl; + + /* flush descriptor and buffer */ + flush_dcache_range((unsigned long)descp, + (unsigned long)(descp + sizeof(dma64dd_t))); + flush_dcache_range((unsigned long)bufp, + (unsigned long)(bufp + TX_BUF_SIZE)); + + /* now update the dma last descriptor */ + writel(last_desc, GMAC0_DMA_TX_PTR_ADDR); + + /* tx dma should be enabled so packet should go out */ + + /* update txout */ + dma->cur_tx_index = (txout + 1) & (TX_BUF_NUM - 1); + + return 0; +} + +bool gmac_check_tx_done(struct eth_dma *dma) +{ + /* wait for tx to complete */ + uint32_t intstatus; + bool xfrdone = false; + + debug("%s enter\n", __func__); + + intstatus = readl(GMAC0_INT_STATUS_ADDR); + + debug("int(0x%x)\n", intstatus); + if (intstatus & (I_XI0 | I_XI1 | I_XI2 | I_XI3)) { + xfrdone = true; + /* clear the int bits */ + intstatus &= ~(I_XI0 | I_XI1 | I_XI2 | I_XI3); + writel(intstatus, GMAC0_INT_STATUS_ADDR); + } else { + debug("Tx int(0x%x)\n", intstatus); + } + + return xfrdone; +} + +int gmac_check_rx_done(struct eth_dma *dma, uint8_t *buf) +{ + void *bufp, *datap; + size_t rcvlen = 0, buflen = 0; + uint32_t stat0 = 0, stat1 = 0; + uint32_t control, offset; + uint8_t statbuf[HWRXOFF*2]; + + int index, curr, active; + dma64dd_t *descp = NULL; + + /* udelay(50); */ + + /* + * this api will check if a packet has been received. + * If so it will return the address of the buffer and current + * descriptor index will be incremented to the + * next descriptor. Once done with the frame the buffer should be + * added back onto the descriptor and the lastdscr should be updated + * to this descriptor. + */ + index = dma->cur_rx_index; + offset = (uint32_t)(dma->rx_desc_aligned); + stat0 = readl(GMAC0_DMA_RX_STATUS0_ADDR) & D64_RS0_CD_MASK; + stat1 = readl(GMAC0_DMA_RX_STATUS1_ADDR) & D64_RS0_CD_MASK; + curr = ((stat0 - offset) & D64_RS0_CD_MASK) / sizeof(dma64dd_t); + active = ((stat1 - offset) & D64_RS0_CD_MASK) / sizeof(dma64dd_t); + + /* check if any frame */ + if (index == curr) + return -1; + + debug("received packet\n"); + debug("expect(0x%x) curr(0x%x) active(0x%x)\n", index, curr, active); + /* remove warning */ + if (index == active) + ; + + /* get the packet pointer that corresponds to the rx descriptor */ + bufp = dma->rx_buf + index * RX_BUF_SIZE; + + descp = (dma64dd_t *)(dma->rx_desc_aligned) + index; + /* flush descriptor and buffer */ + flush_dcache_range((unsigned long)descp, + (unsigned long)(descp + sizeof(dma64dd_t))); + flush_dcache_range((unsigned long)bufp, + (unsigned long)(bufp + RX_BUF_SIZE)); + + buflen = (descp->ctrl2 & D64_CTRL2_BC_MASK); + + stat0 = readl(GMAC0_DMA_RX_STATUS0_ADDR); + stat1 = readl(GMAC0_DMA_RX_STATUS1_ADDR); + + debug("bufp(0x%x) index(0x%x) buflen(0x%x) stat0(0x%x) stat1(0x%x)\n", + (uint32_t)bufp, index, buflen, stat0, stat1); + + dma->cur_rx_index = (index + 1) & (RX_BUF_NUM - 1); + + /* get buffer offset */ + control = readl(GMAC0_DMA_RX_CTRL_ADDR); + offset = (control & D64_RC_RO_MASK) >> D64_RC_RO_SHIFT; + rcvlen = *(uint16_t *)bufp; + + debug("Received %d bytes\n", rcvlen); + /* copy status into temp buf then copy data from rx buffer */ + memcpy(statbuf, bufp, offset); + datap = (void *)((uint32_t)bufp + offset); + memcpy(buf, datap, rcvlen); + + /* update descriptor that is being added back on ring */ + descp->ctrl2 = RX_BUF_SIZE; + descp->addrlow = (uint32_t)bufp; + descp->addrhigh = 0; + /* flush descriptor */ + flush_dcache_range((unsigned long)descp, + (unsigned long)(descp + sizeof(dma64dd_t))); + + /* set the lastdscr for the rx ring */ + writel(((uint32_t)descp) & D64_XP_LD_MASK, GMAC0_DMA_RX_PTR_ADDR); + + return (int)rcvlen; +} + +static int gmac_disable_dma(struct eth_dma *dma, int dir) +{ + int status; + + debug("%s enter\n", __func__); + + if (dir == MAC_DMA_TX) { + /* address PR8249/PR7577 issue */ + /* suspend tx DMA first */ + writel(D64_XC_SE, GMAC0_DMA_TX_CTRL_ADDR); + SPINWAIT(((status = (readl(GMAC0_DMA_TX_STATUS0_ADDR) & + D64_XS0_XS_MASK)) != + D64_XS0_XS_DISABLED) && + (status != D64_XS0_XS_IDLE) && + (status != D64_XS0_XS_STOPPED), 10000); + + /* + * PR2414 WAR: DMA engines are not disabled until + * transfer finishes + */ + writel(0, GMAC0_DMA_TX_CTRL_ADDR); + SPINWAIT(((status = (readl(GMAC0_DMA_TX_STATUS0_ADDR) & + D64_XS0_XS_MASK)) != + D64_XS0_XS_DISABLED), 10000); + + /* wait for the last transaction to complete */ + udelay(2); + + status = (status == D64_XS0_XS_DISABLED); + } else { + /* + * PR2414 WAR: DMA engines are not disabled until + * transfer finishes + */ + writel(0, GMAC0_DMA_RX_CTRL_ADDR); + SPINWAIT(((status = (readl(GMAC0_DMA_RX_STATUS0_ADDR) & + D64_RS0_RS_MASK)) != + D64_RS0_RS_DISABLED), 10000); + + status = (status == D64_RS0_RS_DISABLED); + } + + return status; +} + +static int gmac_enable_dma(struct eth_dma *dma, int dir) +{ + uint32_t control; + + debug("%s enter\n", __func__); + + if (dir == MAC_DMA_TX) { + dma->cur_tx_index = 0; + + /* + * These bits 20:18 (burstLen) of control register can be + * written but will take effect only if these bits are + * valid. So this will not affect previous versions + * of the DMA. They will continue to have those bits set to 0. + */ + control = readl(GMAC0_DMA_TX_CTRL_ADDR); + + control |= D64_XC_XE; + if ((g_dmactrlflags & DMA_CTRL_PEN) == 0) + control |= D64_XC_PD; + + writel(control, GMAC0_DMA_TX_CTRL_ADDR); + + /* initailize the DMA channel */ + writel((uint32_t)(dma->tx_desc_aligned), + GMAC0_DMA_TX_ADDR_LOW_ADDR); + writel(0, GMAC0_DMA_TX_ADDR_HIGH_ADDR); + } else { + dma->cur_rx_index = 0; + + control = (readl(GMAC0_DMA_RX_CTRL_ADDR) & + D64_RC_AE) | D64_RC_RE; + + if ((g_dmactrlflags & DMA_CTRL_PEN) == 0) + control |= D64_RC_PD; + + if (g_dmactrlflags & DMA_CTRL_ROC) + control |= D64_RC_OC; + + /* + * These bits 20:18 (burstLen) of control register can be + * written but will take effect only if these bits are + * valid. So this will not affect previous versions + * of the DMA. They will continue to have those bits set to 0. + */ + control &= ~D64_RC_BL_MASK; + /* Keep default Rx burstlen */ + control |= readl(GMAC0_DMA_RX_CTRL_ADDR) & D64_RC_BL_MASK; + control |= HWRXOFF << D64_RC_RO_SHIFT; + + writel(control, GMAC0_DMA_RX_CTRL_ADDR); + + /* + * the rx descriptor ring should have + * the addresses set properly; + * set the lastdscr for the rx ring + */ + writel(((uint32_t)(dma->rx_desc_aligned) + + (RX_BUF_NUM - 1) * RX_BUF_SIZE) & + D64_XP_LD_MASK, GMAC0_DMA_RX_PTR_ADDR); + } + + return 0; +} + +bool gmac_mii_busywait(unsigned int timeout) +{ + uint32_t tmp = 0; + + while (timeout > 10) { + tmp = readl(GMAC_MII_CTRL_ADDR); + if (tmp & (1 << GMAC_MII_BUSY_SHIFT)) { + udelay(10); + timeout -= 10; + } else { + break; + } + } + return tmp & (1 << GMAC_MII_BUSY_SHIFT); +} + +int gmac_miiphy_read(const char *devname, unsigned char phyaddr, + unsigned char reg, unsigned short *value) +{ + uint32_t tmp = 0; + + (void)devname; + + /* Busy wait timeout is 1ms */ + if (gmac_mii_busywait(1000)) { + error("%s: Prepare MII read: MII/MDIO busy\n", __func__); + return -1; + } + + /* Read operation */ + tmp = GMAC_MII_DATA_READ_CMD; + tmp |= (phyaddr << GMAC_MII_PHY_ADDR_SHIFT) | + (reg << GMAC_MII_PHY_REG_SHIFT); + debug("MII read cmd 0x%x, phy 0x%x, reg 0x%x\n", tmp, phyaddr, reg); + writel(tmp, GMAC_MII_DATA_ADDR); + + if (gmac_mii_busywait(1000)) { + error("%s: MII read failure: MII/MDIO busy\n", __func__); + return -1; + } + + *value = readl(GMAC_MII_DATA_ADDR) & 0xffff; + debug("MII read data 0x%x\n", *value); + return 0; +} + +int gmac_miiphy_write(const char *devname, unsigned char phyaddr, + unsigned char reg, unsigned short value) +{ + uint32_t tmp = 0; + + (void)devname; + + /* Busy wait timeout is 1ms */ + if (gmac_mii_busywait(1000)) { + error("%s: Prepare MII write: MII/MDIO busy\n", __func__); + return -1; + } + + /* Write operation */ + tmp = GMAC_MII_DATA_WRITE_CMD | (value & 0xffff); + tmp |= ((phyaddr << GMAC_MII_PHY_ADDR_SHIFT) | + (reg << GMAC_MII_PHY_REG_SHIFT)); + debug("MII write cmd 0x%x, phy 0x%x, reg 0x%x, data 0x%x\n", + tmp, phyaddr, reg, value); + writel(tmp, GMAC_MII_DATA_ADDR); + + if (gmac_mii_busywait(1000)) { + error("%s: MII write failure: MII/MDIO busy\n", __func__); + return -1; + } + + return 0; +} + +void gmac_init_reset(void) +{ + debug("%s enter\n", __func__); + + /* set command config reg CC_SR */ + reg32_set_bits(UNIMAC0_CMD_CFG_ADDR, CC_SR); + udelay(GMAC_RESET_DELAY); +} + +void gmac_clear_reset(void) +{ + debug("%s enter\n", __func__); + + /* clear command config reg CC_SR */ + reg32_clear_bits(UNIMAC0_CMD_CFG_ADDR, CC_SR); + udelay(GMAC_RESET_DELAY); +} + +static void gmac_enable_local(bool en) +{ + uint32_t cmdcfg; + + debug("%s enter\n", __func__); + + /* read command config reg */ + cmdcfg = readl(UNIMAC0_CMD_CFG_ADDR); + + /* put mac in reset */ + gmac_init_reset(); + + cmdcfg |= CC_SR; + + /* first deassert rx_ena and tx_ena while in reset */ + cmdcfg &= ~(CC_RE | CC_TE); + /* write command config reg */ + writel(cmdcfg, UNIMAC0_CMD_CFG_ADDR); + + /* bring mac out of reset */ + gmac_clear_reset(); + + /* if not enable exit now */ + if (!en) + return; + + /* enable the mac transmit and receive paths now */ + udelay(2); + cmdcfg &= ~CC_SR; + cmdcfg |= (CC_RE | CC_TE); + + /* assert rx_ena and tx_ena when out of reset to enable the mac */ + writel(cmdcfg, UNIMAC0_CMD_CFG_ADDR); + + return; +} + +int gmac_enable(void) +{ + gmac_enable_local(1); + + /* clear interrupts */ + writel(I_INTMASK, GMAC0_INT_STATUS_ADDR); + return 0; +} + +int gmac_disable(void) +{ + gmac_enable_local(0); + return 0; +} + +int gmac_set_speed(int speed, int duplex) +{ + uint32_t cmdcfg; + uint32_t hd_ena; + uint32_t speed_cfg; + + hd_ena = duplex ? 0 : CC_HD; + if (speed == 1000) { + speed_cfg = 2; + } else if (speed == 100) { + speed_cfg = 1; + } else if (speed == 10) { + speed_cfg = 0; + } else { + error("%s: Invalid GMAC speed(%d)!\n", __func__, speed); + return -1; + } + + cmdcfg = readl(UNIMAC0_CMD_CFG_ADDR); + cmdcfg &= ~(CC_ES_MASK | CC_HD); + cmdcfg |= ((speed_cfg << CC_ES_SHIFT) | hd_ena); + + printf("Change GMAC speed to %dMB\n", speed); + debug("GMAC speed cfg 0x%x\n", cmdcfg); + writel(cmdcfg, UNIMAC0_CMD_CFG_ADDR); + + return 0; +} + +int gmac_set_mac_addr(unsigned char *mac) +{ + /* set our local address */ + debug("GMAC: %02x:%02x:%02x:%02x:%02x:%02x\n", + mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); + writel(htonl(*(uint32_t *)mac), UNIMAC0_MAC_MSB_ADDR); + writew(htons(*(uint32_t *)&mac[4]), UNIMAC0_MAC_LSB_ADDR); + + return 0; +} + +int gmac_mac_init(struct eth_device *dev) +{ + struct eth_info *eth = (struct eth_info *)(dev->priv); + struct eth_dma *dma = &(eth->dma); + + uint32_t tmp; + uint32_t cmdcfg; + int chipid; + + debug("%s enter\n", __func__); + + /* Always use GMAC0 */ + printf("Using GMAC%d\n", 0); + + /* Reset AMAC0 core */ + writel(0, AMAC0_IDM_RESET_ADDR); + tmp = readl(AMAC0_IO_CTRL_DIRECT_ADDR); + /* Set clock */ + tmp &= ~(1 << AMAC0_IO_CTRL_CLK_250_SEL_SHIFT); + tmp |= (1 << AMAC0_IO_CTRL_GMII_MODE_SHIFT); + /* Set Tx clock */ + tmp &= ~(1 << AMAC0_IO_CTRL_DEST_SYNC_MODE_EN_SHIFT); + writel(tmp, AMAC0_IO_CTRL_DIRECT_ADDR); + + /* reset gmac */ + /* + * As AMAC is just reset, NO need? + * set eth_data into loopback mode to ensure no rx traffic + * gmac_loopback(eth_data, TRUE); + * ET_TRACE(("%s gmac loopback\n", __func__)); + * udelay(1); + */ + + cmdcfg = readl(UNIMAC0_CMD_CFG_ADDR); + cmdcfg &= ~(CC_TE | CC_RE | CC_RPI | CC_TAI | CC_HD | CC_ML | + CC_CFE | CC_RL | CC_RED | CC_PE | CC_TPI | + CC_PAD_EN | CC_PF); + cmdcfg |= (CC_PROM | CC_NLC | CC_CFE); + /* put mac in reset */ + gmac_init_reset(); + writel(cmdcfg, UNIMAC0_CMD_CFG_ADDR); + gmac_clear_reset(); + + /* enable clear MIB on read */ + reg32_set_bits(GMAC0_DEV_CTRL_ADDR, DC_MROR); + /* PHY: set smi_master to drive mdc_clk */ + reg32_set_bits(GMAC0_PHY_CTRL_ADDR, PC_MTE); + + /* clear persistent sw intstatus */ + writel(0, GMAC0_INT_STATUS_ADDR); + + if (dma_init(dma) < 0) { + error("%s: GMAC dma_init failed\n", __func__); + goto err_exit; + } + + chipid = CHIPID; + printf("%s: Chip ID: 0x%x\n", __func__, chipid); + + /* set switch bypass mode */ + tmp = readl(SWITCH_GLOBAL_CONFIG_ADDR); + tmp |= (1 << CDRU_SWITCH_BYPASS_SWITCH_SHIFT); + + /* Switch mode */ + /* tmp &= ~(1 << CDRU_SWITCH_BYPASS_SWITCH_SHIFT); */ + + writel(tmp, SWITCH_GLOBAL_CONFIG_ADDR); + + tmp = readl(CRMU_CHIP_IO_PAD_CONTROL_ADDR); + tmp &= ~(1 << CDRU_IOMUX_FORCE_PAD_IN_SHIFT); + writel(tmp, CRMU_CHIP_IO_PAD_CONTROL_ADDR); + + /* Set MDIO to internal GPHY */ + tmp = readl(GMAC_MII_CTRL_ADDR); + /* Select internal MDC/MDIO bus*/ + tmp &= ~(1 << GMAC_MII_CTRL_BYP_SHIFT); + /* select MDC/MDIO connecting to on-chip internal PHYs */ + tmp &= ~(1 << GMAC_MII_CTRL_EXT_SHIFT); + /* + * give bit[6:0](MDCDIV) with required divisor to set + * the MDC clock frequency, 66MHZ/0x1A=2.5MHZ + */ + tmp |= 0x1A; + + writel(tmp, GMAC_MII_CTRL_ADDR); + + if (gmac_mii_busywait(1000)) { + error("%s: Configure MDIO: MII/MDIO busy\n", __func__); + goto err_exit; + } + + /* Configure GMAC0 */ + /* enable one rx interrupt per received frame */ + writel(1 << GMAC0_IRL_FRAMECOUNT_SHIFT, GMAC0_INTR_RECV_LAZY_ADDR); + + /* read command config reg */ + cmdcfg = readl(UNIMAC0_CMD_CFG_ADDR); + /* enable 802.3x tx flow control (honor received PAUSE frames) */ + cmdcfg &= ~CC_RPI; + /* enable promiscuous mode */ + cmdcfg |= CC_PROM; + /* Disable loopback mode */ + cmdcfg &= ~CC_ML; + /* set the speed */ + cmdcfg &= ~(CC_ES_MASK | CC_HD); + /* Set to 1Gbps and full duplex by default */ + cmdcfg |= (2 << CC_ES_SHIFT); + + /* put mac in reset */ + gmac_init_reset(); + /* write register */ + writel(cmdcfg, UNIMAC0_CMD_CFG_ADDR); + /* bring mac out of reset */ + gmac_clear_reset(); + + /* set max frame lengths; account for possible vlan tag */ + writel(PKTSIZE + 32, UNIMAC0_FRM_LENGTH_ADDR); + + return 0; + +err_exit: + dma_deinit(dma); + return -1; +} + +int gmac_add(struct eth_device *dev) +{ + struct eth_info *eth = (struct eth_info *)(dev->priv); + struct eth_dma *dma = &(eth->dma); + void *tmp; + + /* + * Desc has to be 16-byte aligned ? + * If it is 8-byte aligned by malloc, fail Tx + */ + tmp = malloc(sizeof(dma64dd_t) * TX_BUF_NUM + 8); + if (tmp == NULL) { + printf("%s: Failed to allocate TX desc Buffer\n", __func__); + return -1; + } + + dma->tx_desc = (void *)tmp; + dma->tx_desc_aligned = (void *)(((uint32_t)tmp) & (~0xf)); + debug("TX Descriptor Buffer: %p; length: 0x%x\n", + dma->tx_desc_aligned, sizeof(dma64dd_t) * TX_BUF_NUM); + + tmp = malloc(TX_BUF_SIZE * TX_BUF_NUM); + if (tmp == NULL) { + printf("%s: Failed to allocate TX Data Buffer\n", __func__); + free(dma->tx_desc); + return -1; + } + dma->tx_buf = (uint8_t *)tmp; + debug("TX Data Buffer: %p; length: 0x%x\n", + dma->tx_buf, TX_BUF_SIZE * TX_BUF_NUM); + + /* Desc has to be 16-byte aligned ? */ + tmp = malloc(sizeof(dma64dd_t) * RX_BUF_NUM + 8); + if (tmp == NULL) { + printf("%s: Failed to allocate RX Descriptor\n", __func__); + free(dma->tx_desc); + free(dma->tx_buf); + return -1; + } + dma->rx_desc = tmp; + dma->rx_desc_aligned = (void *)(((uint32_t)tmp) & (~0xf)); + debug("RX Descriptor Buffer: %p, length: 0x%x\n", + dma->rx_desc_aligned, sizeof(dma64dd_t) * RX_BUF_NUM); + + tmp = malloc(RX_BUF_SIZE * RX_BUF_NUM); + if (tmp == NULL) { + printf("%s: Failed to allocate RX Data Buffer\n", __func__); + free(dma->tx_desc); + free(dma->tx_buf); + free(dma->rx_desc); + return -1; + } + dma->rx_buf = tmp; + debug("RX Data Buffer: %p; length: 0x%x\n", + dma->rx_buf, RX_BUF_SIZE * RX_BUF_NUM); + + g_dmactrlflags = 0; + + eth->phy_interface = PHY_INTERFACE_MODE_GMII; + + dma->tx_packet = gmac_tx_packet; + dma->check_tx_done = gmac_check_tx_done; + + dma->check_rx_done = gmac_check_rx_done; + + dma->enable_dma = gmac_enable_dma; + dma->disable_dma = gmac_disable_dma; + + eth->miiphy_read = gmac_miiphy_read; + eth->miiphy_write = gmac_miiphy_write; + + eth->mac_init = gmac_mac_init; + eth->disable_mac = gmac_disable; + eth->enable_mac = gmac_enable; + eth->set_mac_addr = gmac_set_mac_addr; + eth->set_mac_speed = gmac_set_speed; + + return 0; +} diff --git a/sources/uboot-be550/drivers/net/bcm-sf2-eth-gmac.h b/sources/uboot-be550/drivers/net/bcm-sf2-eth-gmac.h new file mode 100644 index 00000000..810a6172 --- /dev/null +++ b/sources/uboot-be550/drivers/net/bcm-sf2-eth-gmac.h @@ -0,0 +1,224 @@ +/* + * Copyright 2014 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _BCM_SF2_ETH_GMAC_H_ +#define _BCM_SF2_ETH_GMAC_H_ + +#define BCM_SF2_ETH_MAC_NAME "gmac" + +#ifndef ETHHW_PORT_INT +#define ETHHW_PORT_INT 8 +#endif + +#define GMAC0_REG_BASE 0x18042000 +#define GMAC0_DEV_CTRL_ADDR GMAC0_REG_BASE +#define GMAC0_INT_STATUS_ADDR (GMAC0_REG_BASE + 0x020) +#define GMAC0_INTR_RECV_LAZY_ADDR (GMAC0_REG_BASE + 0x100) +#define GMAC0_PHY_CTRL_ADDR (GMAC0_REG_BASE + 0x188) + + +#define GMAC_DMA_PTR_OFFSET 0x04 +#define GMAC_DMA_ADDR_LOW_OFFSET 0x08 +#define GMAC_DMA_ADDR_HIGH_OFFSET 0x0c +#define GMAC_DMA_STATUS0_OFFSET 0x10 +#define GMAC_DMA_STATUS1_OFFSET 0x14 + +#define GMAC0_DMA_TX_CTRL_ADDR (GMAC0_REG_BASE + 0x200) +#define GMAC0_DMA_TX_PTR_ADDR \ + (GMAC0_DMA_TX_CTRL_ADDR + GMAC_DMA_PTR_OFFSET) +#define GMAC0_DMA_TX_ADDR_LOW_ADDR \ + (GMAC0_DMA_TX_CTRL_ADDR + GMAC_DMA_ADDR_LOW_OFFSET) +#define GMAC0_DMA_TX_ADDR_HIGH_ADDR \ + (GMAC0_DMA_TX_CTRL_ADDR + GMAC_DMA_ADDR_HIGH_OFFSET) +#define GMAC0_DMA_TX_STATUS0_ADDR \ + (GMAC0_DMA_TX_CTRL_ADDR + GMAC_DMA_STATUS0_OFFSET) +#define GMAC0_DMA_TX_STATUS1_ADDR \ + (GMAC0_DMA_TX_CTRL_ADDR + GMAC_DMA_STATUS1_OFFSET) + +#define GMAC0_DMA_RX_CTRL_ADDR (GMAC0_REG_BASE + 0x220) +#define GMAC0_DMA_RX_PTR_ADDR \ + (GMAC0_DMA_RX_CTRL_ADDR + GMAC_DMA_PTR_OFFSET) +#define GMAC0_DMA_RX_ADDR_LOW_ADDR \ + (GMAC0_DMA_RX_CTRL_ADDR + GMAC_DMA_ADDR_LOW_OFFSET) +#define GMAC0_DMA_RX_ADDR_HIGH_ADDR \ + (GMAC0_DMA_RX_CTRL_ADDR + GMAC_DMA_ADDR_HIGH_OFFSET) +#define GMAC0_DMA_RX_STATUS0_ADDR \ + (GMAC0_DMA_RX_CTRL_ADDR + GMAC_DMA_STATUS0_OFFSET) +#define GMAC0_DMA_RX_STATUS1_ADDR \ + (GMAC0_DMA_RX_CTRL_ADDR + GMAC_DMA_STATUS1_OFFSET) + +#define UNIMAC0_CMD_CFG_ADDR (GMAC0_REG_BASE + 0x808) +#define UNIMAC0_MAC_MSB_ADDR (GMAC0_REG_BASE + 0x80c) +#define UNIMAC0_MAC_LSB_ADDR (GMAC0_REG_BASE + 0x810) +#define UNIMAC0_FRM_LENGTH_ADDR (GMAC0_REG_BASE + 0x814) + +#define GMAC0_IRL_FRAMECOUNT_SHIFT 24 + +/* transmit channel control */ +/* transmit enable */ +#define D64_XC_XE 0x00000001 +/* transmit suspend request */ +#define D64_XC_SE 0x00000002 +/* parity check disable */ +#define D64_XC_PD 0x00000800 +/* BurstLen bits */ +#define D64_XC_BL_MASK 0x001C0000 +#define D64_XC_BL_SHIFT 18 + +/* transmit descriptor table pointer */ +/* last valid descriptor */ +#define D64_XP_LD_MASK 0x00001fff + +/* transmit channel status */ +/* transmit state */ +#define D64_XS0_XS_MASK 0xf0000000 +#define D64_XS0_XS_SHIFT 28 +#define D64_XS0_XS_DISABLED 0x00000000 +#define D64_XS0_XS_ACTIVE 0x10000000 +#define D64_XS0_XS_IDLE 0x20000000 +#define D64_XS0_XS_STOPPED 0x30000000 +#define D64_XS0_XS_SUSP 0x40000000 + +/* receive channel control */ +/* receive enable */ +#define D64_RC_RE 0x00000001 +/* address extension bits */ +#define D64_RC_AE 0x00030000 +/* overflow continue */ +#define D64_RC_OC 0x00000400 +/* parity check disable */ +#define D64_RC_PD 0x00000800 +/* receive frame offset */ +#define D64_RC_RO_MASK 0x000000fe +#define D64_RC_RO_SHIFT 1 +/* BurstLen bits */ +#define D64_RC_BL_MASK 0x001C0000 +#define D64_RC_BL_SHIFT 18 + +/* flags for dma controller */ +/* partity enable */ +#define DMA_CTRL_PEN (1 << 0) +/* rx overflow continue */ +#define DMA_CTRL_ROC (1 << 1) + +/* receive descriptor table pointer */ +/* last valid descriptor */ +#define D64_RP_LD_MASK 0x00001fff + +/* receive channel status */ +/* current descriptor pointer */ +#define D64_RS0_CD_MASK 0x00001fff +/* receive state */ +#define D64_RS0_RS_MASK 0xf0000000 +#define D64_RS0_RS_SHIFT 28 +#define D64_RS0_RS_DISABLED 0x00000000 +#define D64_RS0_RS_ACTIVE 0x10000000 +#define D64_RS0_RS_IDLE 0x20000000 +#define D64_RS0_RS_STOPPED 0x30000000 +#define D64_RS0_RS_SUSP 0x40000000 + +/* descriptor control flags 1 */ +/* core specific flags */ +#define D64_CTRL_COREFLAGS 0x0ff00000 +/* end of descriptor table */ +#define D64_CTRL1_EOT ((uint32_t)1 << 28) +/* interrupt on completion */ +#define D64_CTRL1_IOC ((uint32_t)1 << 29) +/* end of frame */ +#define D64_CTRL1_EOF ((uint32_t)1 << 30) +/* start of frame */ +#define D64_CTRL1_SOF ((uint32_t)1 << 31) + +/* descriptor control flags 2 */ +/* buffer byte count. real data len must <= 16KB */ +#define D64_CTRL2_BC_MASK 0x00007fff +/* address extension bits */ +#define D64_CTRL2_AE 0x00030000 +#define D64_CTRL2_AE_SHIFT 16 +/* parity bit */ +#define D64_CTRL2_PARITY 0x00040000 +/* control flags in the range [27:20] are core-specific and not defined here */ +#define D64_CTRL_CORE_MASK 0x0ff00000 + +#define DC_MROR 0x00000010 +#define PC_MTE 0x00800000 + +/* command config */ +#define CC_TE 0x00000001 +#define CC_RE 0x00000002 +#define CC_ES_MASK 0x0000000c +#define CC_ES_SHIFT 2 +#define CC_PROM 0x00000010 +#define CC_PAD_EN 0x00000020 +#define CC_CF 0x00000040 +#define CC_PF 0x00000080 +#define CC_RPI 0x00000100 +#define CC_TAI 0x00000200 +#define CC_HD 0x00000400 +#define CC_HD_SHIFT 10 +#define CC_SR 0x00002000 +#define CC_ML 0x00008000 +#define CC_AE 0x00400000 +#define CC_CFE 0x00800000 +#define CC_NLC 0x01000000 +#define CC_RL 0x02000000 +#define CC_RED 0x04000000 +#define CC_PE 0x08000000 +#define CC_TPI 0x10000000 +#define CC_AT 0x20000000 + +#define I_PDEE 0x00000400 +#define I_PDE 0x00000800 +#define I_DE 0x00001000 +#define I_RDU 0x00002000 +#define I_RFO 0x00004000 +#define I_XFU 0x00008000 +#define I_RI 0x00010000 +#define I_XI0 0x01000000 +#define I_XI1 0x02000000 +#define I_XI2 0x04000000 +#define I_XI3 0x08000000 +#define I_ERRORS (I_PDEE | I_PDE | I_DE | I_RDU | I_RFO | I_XFU) +#define DEF_INTMASK (I_XI0 | I_XI1 | I_XI2 | I_XI3 | I_RI | I_ERRORS) + +#define I_INTMASK 0x0f01fcff + +#define CHIP_DRU_BASE 0x0301d000 +#define CRMU_CHIP_IO_PAD_CONTROL_ADDR (CHIP_DRU_BASE + 0x0bc) +#define SWITCH_GLOBAL_CONFIG_ADDR (CHIP_DRU_BASE + 0x194) + +#define CDRU_IOMUX_FORCE_PAD_IN_SHIFT 0 +#define CDRU_SWITCH_BYPASS_SWITCH_SHIFT 13 + +#define AMAC0_IDM_RESET_ADDR 0x18110800 +#define AMAC0_IO_CTRL_DIRECT_ADDR 0x18110408 +#define AMAC0_IO_CTRL_CLK_250_SEL_SHIFT 6 +#define AMAC0_IO_CTRL_GMII_MODE_SHIFT 5 +#define AMAC0_IO_CTRL_DEST_SYNC_MODE_EN_SHIFT 3 + +#define CHIPA_CHIP_ID_ADDR 0x18000000 +#define CHIPID (readl(CHIPA_CHIP_ID_ADDR) & 0xFFFF) +#define CHIPREV (((readl(CHIPA_CHIP_ID_ADDR) >> 16) & 0xF) +#define CHIPSKU (((readl(CHIPA_CHIP_ID_ADDR) >> 20) & 0xF) + +#define GMAC_MII_CTRL_ADDR 0x18002000 +#define GMAC_MII_CTRL_BYP_SHIFT 10 +#define GMAC_MII_CTRL_EXT_SHIFT 9 +#define GMAC_MII_DATA_ADDR 0x18002004 +#define GMAC_MII_DATA_READ_CMD 0x60020000 +#define GMAC_MII_DATA_WRITE_CMD 0x50020000 +#define GMAC_MII_BUSY_SHIFT 8 +#define GMAC_MII_PHY_ADDR_SHIFT 23 +#define GMAC_MII_PHY_REG_SHIFT 18 + +#define GMAC_RESET_DELAY 2 +#define HWRXOFF 30 +#define MAXNAMEL 8 +#define NUMTXQ 4 + +int gmac_add(struct eth_device *dev); + +#endif /* _BCM_SF2_ETH_GMAC_H_ */ diff --git a/sources/uboot-be550/drivers/net/bcm-sf2-eth.c b/sources/uboot-be550/drivers/net/bcm-sf2-eth.c new file mode 100644 index 00000000..eab4c1f9 --- /dev/null +++ b/sources/uboot-be550/drivers/net/bcm-sf2-eth.c @@ -0,0 +1,262 @@ +/* + * Copyright 2014 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +#include +#include + +#include + +#include +#include "bcm-sf2-eth.h" + +#if defined(CONFIG_BCM_SF2_ETH_GMAC) +#include "bcm-sf2-eth-gmac.h" +#else +#error "bcm_sf2_eth: NEED to define a MAC!" +#endif + +#define BCM_NET_MODULE_DESCRIPTION "Broadcom Starfighter2 Ethernet driver" +#define BCM_NET_MODULE_VERSION "0.1" +#define BCM_SF2_ETH_DEV_NAME "bcm_sf2" + +static const char banner[] = + BCM_NET_MODULE_DESCRIPTION " " BCM_NET_MODULE_VERSION "\n"; + +static int bcm_sf2_eth_init(struct eth_device *dev) +{ + struct eth_info *eth = (struct eth_info *)(dev->priv); + struct eth_dma *dma = &(eth->dma); + struct phy_device *phydev; + int rc = 0; + int i; + + rc = eth->mac_init(dev); + if (rc) { + error("%s: Couldn't cofigure MAC!\n", __func__); + return rc; + } + + /* disable DMA */ + dma->disable_dma(dma, MAC_DMA_RX); + dma->disable_dma(dma, MAC_DMA_TX); + + eth->port_num = 0; + debug("Connecting PHY 0...\n"); + phydev = phy_connect(miiphy_get_dev_by_name(dev->name), + 0, dev, eth->phy_interface); + if (phydev != NULL) { + eth->port[0] = phydev; + eth->port_num += 1; + } else { + debug("No PHY found for port 0\n"); + } + + for (i = 0; i < eth->port_num; i++) + phy_config(eth->port[i]); + + return rc; +} + +/* + * u-boot net functions + */ + +static int bcm_sf2_eth_send(struct eth_device *dev, void *packet, int length) +{ + struct eth_dma *dma = &(((struct eth_info *)(dev->priv))->dma); + uint8_t *buf = (uint8_t *)packet; + int rc = 0; + int i = 0; + + debug("%s enter\n", __func__); + + /* load buf and start transmit */ + rc = dma->tx_packet(dma, buf, length); + if (rc) { + debug("ERROR - Tx failed\n"); + return rc; + } + + while (!(dma->check_tx_done(dma))) { + udelay(100); + debug("."); + i++; + if (i > 20) { + error("%s: Tx timeout: retried 20 times\n", __func__); + rc = -1; + break; + } + } + + debug("%s exit rc(0x%x)\n", __func__, rc); + return rc; +} + +static int bcm_sf2_eth_receive(struct eth_device *dev) +{ + struct eth_dma *dma = &(((struct eth_info *)(dev->priv))->dma); + uint8_t *buf = (uint8_t *)net_rx_packets[0]; + int rcvlen; + int rc = 0; + int i = 0; + + while (1) { + /* Poll Rx queue to get a packet */ + rcvlen = dma->check_rx_done(dma, buf); + if (rcvlen < 0) { + /* No packet received */ + rc = -1; + debug("\nNO More Rx\n"); + break; + } else if ((rcvlen == 0) || (rcvlen > RX_BUF_SIZE)) { + error("%s: Wrong Ethernet packet size (%d B), skip!\n", + __func__, rcvlen); + break; + } else { + debug("recieved\n"); + + /* Forward received packet to uboot network handler */ + net_process_received_packet(buf, rcvlen); + + if (++i >= PKTBUFSRX) + i = 0; + buf = net_rx_packets[i]; + } + } + + return rc; +} + +static int bcm_sf2_eth_write_hwaddr(struct eth_device *dev) +{ + struct eth_info *eth = (struct eth_info *)(dev->priv); + + printf(" ETH MAC: %02x:%02x:%02x:%02x:%02x:%02x\n", + dev->enetaddr[0], dev->enetaddr[1], dev->enetaddr[2], + dev->enetaddr[3], dev->enetaddr[4], dev->enetaddr[5]); + + return eth->set_mac_addr(dev->enetaddr); +} + +static int bcm_sf2_eth_open(struct eth_device *dev, bd_t *bt) +{ + struct eth_info *eth = (struct eth_info *)(dev->priv); + struct eth_dma *dma = &(eth->dma); + int i; + + debug("Enabling BCM SF2 Ethernet.\n"); + + eth->enable_mac(); + + /* enable tx and rx DMA */ + dma->enable_dma(dma, MAC_DMA_RX); + dma->enable_dma(dma, MAC_DMA_TX); + + /* + * Need to start PHY here because link speed can change + * before each ethernet operation + */ + for (i = 0; i < eth->port_num; i++) { + if (phy_startup(eth->port[i])) { + error("%s: PHY %d startup failed!\n", __func__, i); + if (i == CONFIG_BCM_SF2_ETH_DEFAULT_PORT) { + error("%s: No default port %d!\n", __func__, i); + return -1; + } + } + } + + /* Set MAC speed using default port */ + i = CONFIG_BCM_SF2_ETH_DEFAULT_PORT; + debug("PHY %d: speed:%d, duplex:%d, link:%d\n", i, + eth->port[i]->speed, eth->port[i]->duplex, eth->port[i]->link); + eth->set_mac_speed(eth->port[i]->speed, eth->port[i]->duplex); + + debug("Enable Ethernet Done.\n"); + + return 0; +} + +static void bcm_sf2_eth_close(struct eth_device *dev) +{ + struct eth_info *eth = (struct eth_info *)(dev->priv); + struct eth_dma *dma = &(eth->dma); + + /* disable DMA */ + dma->disable_dma(dma, MAC_DMA_RX); + dma->disable_dma(dma, MAC_DMA_TX); + + eth->disable_mac(); +} + +int bcm_sf2_eth_register(bd_t *bis, u8 dev_num) +{ + struct eth_device *dev; + struct eth_info *eth; + int rc; + + dev = (struct eth_device *)malloc(sizeof(struct eth_device)); + if (dev == NULL) { + error("%s: Not enough memory!\n", __func__); + return -1; + } + + eth = (struct eth_info *)malloc(sizeof(struct eth_info)); + if (eth == NULL) { + error("%s: Not enough memory!\n", __func__); + return -1; + } + + printf(banner); + + memset(dev, 0, sizeof(*dev)); + sprintf(dev->name, "%s_%s-%hu", BCM_SF2_ETH_DEV_NAME, + BCM_SF2_ETH_MAC_NAME, dev_num); + + dev->priv = (void *)eth; + dev->iobase = 0; + + dev->init = bcm_sf2_eth_open; + dev->halt = bcm_sf2_eth_close; + dev->send = bcm_sf2_eth_send; + dev->recv = bcm_sf2_eth_receive; + dev->write_hwaddr = bcm_sf2_eth_write_hwaddr; + +#ifdef CONFIG_BCM_SF2_ETH_GMAC + if (gmac_add(dev)) { + free(eth); + free(dev); + error("%s: Adding GMAC failed!\n", __func__); + return -1; + } +#else +#error "bcm_sf2_eth: NEED to register a MAC!" +#endif + + eth_register(dev); + +#ifdef CONFIG_CMD_MII + miiphy_register(dev->name, eth->miiphy_read, eth->miiphy_write); +#endif + + /* Initialization */ + debug("Ethernet initialization ..."); + + rc = bcm_sf2_eth_init(dev); + if (rc != 0) { + error("%s: configuration failed!\n", __func__); + return -1; + } + + printf("Basic ethernet functionality initialized\n"); + + return 0; +} diff --git a/sources/uboot-be550/drivers/net/bcm-sf2-eth.h b/sources/uboot-be550/drivers/net/bcm-sf2-eth.h new file mode 100644 index 00000000..49a58361 --- /dev/null +++ b/sources/uboot-be550/drivers/net/bcm-sf2-eth.h @@ -0,0 +1,70 @@ +/* + * Copyright 2014 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _BCM_SF2_ETH_H_ +#define _BCM_SF2_ETH_H_ + +#include + +#define RX_BUF_SIZE 2048 +/* RX_BUF_NUM must be power of 2 */ +#define RX_BUF_NUM 32 + +#define TX_BUF_SIZE 2048 +/* TX_BUF_NUM must be power of 2 */ +#define TX_BUF_NUM 2 + +/* Support 2 Ethernet ports now */ +#define BCM_ETH_MAX_PORT_NUM 2 + +#define CONFIG_BCM_SF2_ETH_DEFAULT_PORT 0 + +enum { + MAC_DMA_TX = 1, + MAC_DMA_RX = 2 +}; + +struct eth_dma { + void *tx_desc_aligned; + void *rx_desc_aligned; + void *tx_desc; + void *rx_desc; + + uint8_t *tx_buf; + uint8_t *rx_buf; + + int cur_tx_index; + int cur_rx_index; + + int (*tx_packet)(struct eth_dma *dma, void *packet, int length); + bool (*check_tx_done)(struct eth_dma *dma); + + int (*check_rx_done)(struct eth_dma *dma, uint8_t *buf); + + int (*enable_dma)(struct eth_dma *dma, int dir); + int (*disable_dma)(struct eth_dma *dma, int dir); +}; + +struct eth_info { + struct eth_dma dma; + phy_interface_t phy_interface; + struct phy_device *port[BCM_ETH_MAX_PORT_NUM]; + int port_num; + + int (*miiphy_read)(const char *devname, unsigned char phyaddr, + unsigned char reg, unsigned short *value); + int (*miiphy_write)(const char *devname, unsigned char phyaddr, + unsigned char reg, unsigned short value); + + int (*mac_init)(struct eth_device *dev); + int (*enable_mac)(void); + int (*disable_mac)(void); + int (*set_mac_addr)(unsigned char *mac); + int (*set_mac_speed)(int speed, int duplex); + +}; + +#endif /* _BCM_SF2_ETH_H_ */ diff --git a/sources/uboot-be550/drivers/net/bfin_mac.c b/sources/uboot-be550/drivers/net/bfin_mac.c new file mode 100644 index 00000000..61cb1b0c --- /dev/null +++ b/sources/uboot-be550/drivers/net/bfin_mac.c @@ -0,0 +1,498 @@ +/* + * Driver for Blackfin On-Chip MAC device + * + * Copyright (c) 2005-2008 Analog Device, Inc. + * + * Licensed under the GPL-2 or later. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "bfin_mac.h" + +#ifndef CONFIG_PHY_ADDR +# define CONFIG_PHY_ADDR 1 +#endif +#ifndef CONFIG_PHY_CLOCK_FREQ +# define CONFIG_PHY_CLOCK_FREQ 2500000 +#endif + +#ifdef CONFIG_POST +#include +#endif + +#define RXBUF_BASE_ADDR 0xFF900000 +#define TXBUF_BASE_ADDR 0xFF800000 +#define TX_BUF_CNT 1 + +#define TOUT_LOOP 1000000 + +static ADI_ETHER_BUFFER *txbuf[TX_BUF_CNT]; +static ADI_ETHER_BUFFER *rxbuf[PKTBUFSRX]; +static u16 txIdx; /* index of the current RX buffer */ +static u16 rxIdx; /* index of the current TX buffer */ + +/* DMAx_CONFIG values at DMA Restart */ +static const union { + u16 data; + ADI_DMA_CONFIG_REG reg; +} txdmacfg = { + .reg = { + .b_DMA_EN = 1, /* enabled */ + .b_WNR = 0, /* read from memory */ + .b_WDSIZE = 2, /* wordsize is 32 bits */ + .b_DMA2D = 0, + .b_RESTART = 0, + .b_DI_SEL = 0, + .b_DI_EN = 0, /* no interrupt */ + .b_NDSIZE = 5, /* 5 half words is desc size */ + .b_FLOW = 7 /* large desc flow */ + }, +}; + +static int bfin_miiphy_wait(void) +{ + /* poll the STABUSY bit */ + while (bfin_read_EMAC_STAADD() & STABUSY) + continue; + return 0; +} + +static int bfin_miiphy_read(const char *devname, uchar addr, uchar reg, ushort *val) +{ + if (bfin_miiphy_wait()) + return 1; + bfin_write_EMAC_STAADD(SET_PHYAD(addr) | SET_REGAD(reg) | STABUSY); + if (bfin_miiphy_wait()) + return 1; + *val = bfin_read_EMAC_STADAT(); + return 0; +} + +static int bfin_miiphy_write(const char *devname, uchar addr, uchar reg, ushort val) +{ + if (bfin_miiphy_wait()) + return 1; + bfin_write_EMAC_STADAT(val); + bfin_write_EMAC_STAADD(SET_PHYAD(addr) | SET_REGAD(reg) | STAOP | STABUSY); + return 0; +} + +int bfin_EMAC_initialize(bd_t *bis) +{ + struct eth_device *dev; + dev = malloc(sizeof(*dev)); + if (dev == NULL) + hang(); + + memset(dev, 0, sizeof(*dev)); + strcpy(dev->name, "bfin_mac"); + + dev->iobase = 0; + dev->priv = 0; + dev->init = bfin_EMAC_init; + dev->halt = bfin_EMAC_halt; + dev->send = bfin_EMAC_send; + dev->recv = bfin_EMAC_recv; + dev->write_hwaddr = bfin_EMAC_setup_addr; + + eth_register(dev); + +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) + miiphy_register(dev->name, bfin_miiphy_read, bfin_miiphy_write); +#endif + + return 0; +} + +static int bfin_EMAC_send(struct eth_device *dev, void *packet, int length) +{ + int i; + int result = 0; + + if (length <= 0) { + printf("Ethernet: bad packet size: %d\n", length); + goto out; + } + + if (bfin_read_DMA2_IRQ_STATUS() & DMA_ERR) { + printf("Ethernet: tx DMA error\n"); + goto out; + } + + for (i = 0; (bfin_read_DMA2_IRQ_STATUS() & DMA_RUN); ++i) { + if (i > TOUT_LOOP) { + puts("Ethernet: tx time out\n"); + goto out; + } + } + txbuf[txIdx]->FrmData->NoBytes = length; + memcpy(txbuf[txIdx]->FrmData->Dest, (void *)packet, length); + txbuf[txIdx]->Dma[0].START_ADDR = (u32) txbuf[txIdx]->FrmData; + bfin_write_DMA2_NEXT_DESC_PTR(txbuf[txIdx]->Dma); + bfin_write_DMA2_CONFIG(txdmacfg.data); + bfin_write_EMAC_OPMODE(bfin_read_EMAC_OPMODE() | TE); + + for (i = 0; (txbuf[txIdx]->StatusWord & TX_COMP) == 0; i++) { + if (i > TOUT_LOOP) { + puts("Ethernet: tx error\n"); + goto out; + } + } + result = txbuf[txIdx]->StatusWord; + txbuf[txIdx]->StatusWord = 0; + if ((txIdx + 1) >= TX_BUF_CNT) + txIdx = 0; + else + txIdx++; + out: + debug("BFIN EMAC send: length = %d\n", length); + return result; +} + +static int bfin_EMAC_recv(struct eth_device *dev) +{ + int length = 0; + + for (;;) { + if ((rxbuf[rxIdx]->StatusWord & RX_COMP) == 0) { + length = -1; + break; + } + if ((rxbuf[rxIdx]->StatusWord & RX_DMAO) != 0) { + printf("Ethernet: rx dma overrun\n"); + break; + } + if ((rxbuf[rxIdx]->StatusWord & RX_OK) == 0) { + printf("Ethernet: rx error\n"); + break; + } + length = rxbuf[rxIdx]->StatusWord & 0x000007FF; + if (length <= 4) { + printf("Ethernet: bad frame\n"); + break; + } + + debug("%s: len = %d\n", __func__, length - 4); + + net_rx_packets[rxIdx] = rxbuf[rxIdx]->FrmData->Dest; + net_process_received_packet(net_rx_packets[rxIdx], length - 4); + bfin_write_DMA1_IRQ_STATUS(DMA_DONE | DMA_ERR); + rxbuf[rxIdx]->StatusWord = 0x00000000; + if ((rxIdx + 1) >= PKTBUFSRX) + rxIdx = 0; + else + rxIdx++; + } + + return length; +} + +/************************************************************** + * + * Ethernet Initialization Routine + * + *************************************************************/ + +/* MDC = SCLK / MDC_freq / 2 - 1 */ +#define MDC_FREQ_TO_DIV(mdc_freq) (get_sclk() / (mdc_freq) / 2 - 1) + +#ifndef CONFIG_BFIN_MAC_PINS +# ifdef CONFIG_RMII +# define CONFIG_BFIN_MAC_PINS P_RMII0 +# else +# define CONFIG_BFIN_MAC_PINS P_MII0 +# endif +#endif + +static int bfin_miiphy_init(struct eth_device *dev, int *opmode) +{ + const unsigned short pins[] = CONFIG_BFIN_MAC_PINS; + u16 phydat; + size_t count; + + /* Enable PHY output */ + bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE); + + /* Set all the pins to peripheral mode */ + peripheral_request_list(pins, "bfin_mac"); + + /* Odd word alignment for Receive Frame DMA word */ + /* Configure checksum support and rcve frame word alignment */ + bfin_write_EMAC_SYSCTL(RXDWA | RXCKS | SET_MDCDIV(MDC_FREQ_TO_DIV(CONFIG_PHY_CLOCK_FREQ))); + + /* turn on auto-negotiation and wait for link to come up */ + bfin_miiphy_write(dev->name, CONFIG_PHY_ADDR, MII_BMCR, BMCR_ANENABLE); + count = 0; + while (1) { + ++count; + if (bfin_miiphy_read(dev->name, CONFIG_PHY_ADDR, MII_BMSR, &phydat)) + return -1; + if (phydat & BMSR_LSTATUS) + break; + if (count > 30000) { + printf("%s: link down, check cable\n", dev->name); + return -1; + } + udelay(100); + } + + /* see what kind of link we have */ + if (bfin_miiphy_read(dev->name, CONFIG_PHY_ADDR, MII_LPA, &phydat)) + return -1; + if (phydat & LPA_DUPLEX) + *opmode = FDMODE; + else + *opmode = 0; + + bfin_write_EMAC_MMC_CTL(RSTC | CROLL); + bfin_write_EMAC_VLAN1(EMAC_VLANX_DEF_VAL); + bfin_write_EMAC_VLAN2(EMAC_VLANX_DEF_VAL); + + /* Initialize the TX DMA channel registers */ + bfin_write_DMA2_X_COUNT(0); + bfin_write_DMA2_X_MODIFY(4); + bfin_write_DMA2_Y_COUNT(0); + bfin_write_DMA2_Y_MODIFY(0); + + /* Initialize the RX DMA channel registers */ + bfin_write_DMA1_X_COUNT(0); + bfin_write_DMA1_X_MODIFY(4); + bfin_write_DMA1_Y_COUNT(0); + bfin_write_DMA1_Y_MODIFY(0); + + return 0; +} + +static int bfin_EMAC_setup_addr(struct eth_device *dev) +{ + bfin_write_EMAC_ADDRLO( + dev->enetaddr[0] | + dev->enetaddr[1] << 8 | + dev->enetaddr[2] << 16 | + dev->enetaddr[3] << 24 + ); + bfin_write_EMAC_ADDRHI( + dev->enetaddr[4] | + dev->enetaddr[5] << 8 + ); + return 0; +} + +static int bfin_EMAC_init(struct eth_device *dev, bd_t *bd) +{ + u32 opmode; + int dat; + int i; + debug("Eth_init: ......\n"); + + txIdx = 0; + rxIdx = 0; + + /* Initialize System Register */ + if (bfin_miiphy_init(dev, &dat) < 0) + return -1; + + /* Initialize EMAC address */ + bfin_EMAC_setup_addr(dev); + + /* Initialize TX and RX buffer */ + for (i = 0; i < PKTBUFSRX; i++) { + rxbuf[i] = SetupRxBuffer(i); + if (i > 0) { + rxbuf[i - 1]->Dma[1].NEXT_DESC_PTR = rxbuf[i]->Dma; + if (i == (PKTBUFSRX - 1)) + rxbuf[i]->Dma[1].NEXT_DESC_PTR = rxbuf[0]->Dma; + } + } + for (i = 0; i < TX_BUF_CNT; i++) { + txbuf[i] = SetupTxBuffer(i); + if (i > 0) { + txbuf[i - 1]->Dma[1].NEXT_DESC_PTR = txbuf[i]->Dma; + if (i == (TX_BUF_CNT - 1)) + txbuf[i]->Dma[1].NEXT_DESC_PTR = txbuf[0]->Dma; + } + } + + /* Set RX DMA */ + bfin_write_DMA1_NEXT_DESC_PTR(rxbuf[0]->Dma); + bfin_write_DMA1_CONFIG(rxbuf[0]->Dma[0].CONFIG_DATA); + + /* Wait MII done */ + bfin_miiphy_wait(); + + /* We enable only RX here */ + /* ASTP : Enable Automatic Pad Stripping + PR : Promiscuous Mode for test + PSF : Receive frames with total length less than 64 bytes. + FDMODE : Full Duplex Mode + LB : Internal Loopback for test + RE : Receiver Enable */ + if (dat == FDMODE) + opmode = ASTP | FDMODE | PSF; + else + opmode = ASTP | PSF; + opmode |= RE; +#ifdef CONFIG_RMII + opmode |= TE | RMII; +#endif + /* Turn on the EMAC */ + bfin_write_EMAC_OPMODE(opmode); + return 0; +} + +static void bfin_EMAC_halt(struct eth_device *dev) +{ + debug("Eth_halt: ......\n"); + /* Turn off the EMAC */ + bfin_write_EMAC_OPMODE(0); + /* Turn off the EMAC RX DMA */ + bfin_write_DMA1_CONFIG(0); + bfin_write_DMA2_CONFIG(0); +} + +ADI_ETHER_BUFFER *SetupRxBuffer(int no) +{ + ADI_ETHER_FRAME_BUFFER *frmbuf; + ADI_ETHER_BUFFER *buf; + int nobytes_buffer = sizeof(ADI_ETHER_BUFFER[2]) / 2; /* ensure a multi. of 4 */ + int total_size = nobytes_buffer + RECV_BUFSIZE; + + buf = (void *) (RXBUF_BASE_ADDR + no * total_size); + frmbuf = (void *) (RXBUF_BASE_ADDR + no * total_size + nobytes_buffer); + + memset(buf, 0x00, nobytes_buffer); + buf->FrmData = frmbuf; + memset(frmbuf, 0xfe, RECV_BUFSIZE); + + /* set up first desc to point to receive frame buffer */ + buf->Dma[0].NEXT_DESC_PTR = &(buf->Dma[1]); + buf->Dma[0].START_ADDR = (u32) buf->FrmData; + buf->Dma[0].CONFIG.b_DMA_EN = 1; /* enabled */ + buf->Dma[0].CONFIG.b_WNR = 1; /* Write to memory */ + buf->Dma[0].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */ + buf->Dma[0].CONFIG.b_NDSIZE = 5; /* 5 half words is desc size. */ + buf->Dma[0].CONFIG.b_FLOW = 7; /* large desc flow */ + + /* set up second desc to point to status word */ + buf->Dma[1].NEXT_DESC_PTR = buf->Dma; + buf->Dma[1].START_ADDR = (u32) & buf->IPHdrChksum; + buf->Dma[1].CONFIG.b_DMA_EN = 1; /* enabled */ + buf->Dma[1].CONFIG.b_WNR = 1; /* Write to memory */ + buf->Dma[1].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */ + buf->Dma[1].CONFIG.b_DI_EN = 1; /* enable interrupt */ + buf->Dma[1].CONFIG.b_NDSIZE = 5; /* must be 0 when FLOW is 0 */ + buf->Dma[1].CONFIG.b_FLOW = 7; /* stop */ + + return buf; +} + +ADI_ETHER_BUFFER *SetupTxBuffer(int no) +{ + ADI_ETHER_FRAME_BUFFER *frmbuf; + ADI_ETHER_BUFFER *buf; + int nobytes_buffer = sizeof(ADI_ETHER_BUFFER[2]) / 2; /* ensure a multi. of 4 */ + int total_size = nobytes_buffer + RECV_BUFSIZE; + + buf = (void *) (TXBUF_BASE_ADDR + no * total_size); + frmbuf = (void *) (TXBUF_BASE_ADDR + no * total_size + nobytes_buffer); + + memset(buf, 0x00, nobytes_buffer); + buf->FrmData = frmbuf; + memset(frmbuf, 0x00, RECV_BUFSIZE); + + /* set up first desc to point to receive frame buffer */ + buf->Dma[0].NEXT_DESC_PTR = &(buf->Dma[1]); + buf->Dma[0].START_ADDR = (u32) buf->FrmData; + buf->Dma[0].CONFIG.b_DMA_EN = 1; /* enabled */ + buf->Dma[0].CONFIG.b_WNR = 0; /* Read to memory */ + buf->Dma[0].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */ + buf->Dma[0].CONFIG.b_NDSIZE = 5; /* 5 half words is desc size. */ + buf->Dma[0].CONFIG.b_FLOW = 7; /* large desc flow */ + + /* set up second desc to point to status word */ + buf->Dma[1].NEXT_DESC_PTR = &(buf->Dma[0]); + buf->Dma[1].START_ADDR = (u32) & buf->StatusWord; + buf->Dma[1].CONFIG.b_DMA_EN = 1; /* enabled */ + buf->Dma[1].CONFIG.b_WNR = 1; /* Write to memory */ + buf->Dma[1].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */ + buf->Dma[1].CONFIG.b_DI_EN = 1; /* enable interrupt */ + buf->Dma[1].CONFIG.b_NDSIZE = 0; /* must be 0 when FLOW is 0 */ + buf->Dma[1].CONFIG.b_FLOW = 0; /* stop */ + + return buf; +} + +#if defined(CONFIG_POST) && defined(CONFIG_SYS_POST_ETHER) +int ether_post_test(int flags) +{ + uchar buf[64]; + int i, value = 0; + int length; + uint addr; + + printf("\n--------"); + bfin_EMAC_init(NULL, NULL); + /* construct the package */ + addr = bfin_read_EMAC_ADDRLO(); + buf[0] = buf[6] = addr; + buf[1] = buf[7] = addr >> 8; + buf[2] = buf[8] = addr >> 16; + buf[3] = buf[9] = addr >> 24; + addr = bfin_read_EMAC_ADDRHI(); + buf[4] = buf[10] = addr; + buf[5] = buf[11] = addr >> 8; + buf[12] = 0x08; /* Type: ARP */ + buf[13] = 0x06; + buf[14] = 0x00; /* Hardware type: Ethernet */ + buf[15] = 0x01; + buf[16] = 0x08; /* Protocal type: IP */ + buf[17] = 0x00; + buf[18] = 0x06; /* Hardware size */ + buf[19] = 0x04; /* Protocol size */ + buf[20] = 0x00; /* Opcode: request */ + buf[21] = 0x01; + + for (i = 0; i < 42; i++) + buf[i + 22] = i; + printf("--------Send 64 bytes......\n"); + bfin_EMAC_send(NULL, buf, 64); + for (i = 0; i < 100; i++) { + udelay(10000); + if ((rxbuf[rxIdx]->StatusWord & RX_COMP) != 0) { + value = 1; + break; + } + } + if (value == 0) { + printf("--------EMAC can't receive any data\n"); + eth_halt(); + return -1; + } + length = rxbuf[rxIdx]->StatusWord & 0x000007FF - 4; + for (i = 0; i < length; i++) { + if (rxbuf[rxIdx]->FrmData->Dest[i] != buf[i]) { + printf("--------EMAC receive error data!\n"); + eth_halt(); + return -1; + } + } + printf("--------receive %d bytes, matched\n", length); + bfin_EMAC_halt(NULL); + return 0; +} +#endif diff --git a/sources/uboot-be550/drivers/net/bfin_mac.h b/sources/uboot-be550/drivers/net/bfin_mac.h new file mode 100644 index 00000000..54ffb383 --- /dev/null +++ b/sources/uboot-be550/drivers/net/bfin_mac.h @@ -0,0 +1,65 @@ +/* + * bfin_mac.h - some defines/structures for the Blackfin on-chip MAC. + * + * Copyright (c) 2005-2008 Analog Device, Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __BFIN_MAC_H__ +#define __BFIN_MAC_H__ + +#define RECV_BUFSIZE (0x614) + +typedef struct ADI_DMA_CONFIG_REG { + u16 b_DMA_EN:1; /* 0 Enabled */ + u16 b_WNR:1; /* 1 Direction */ + u16 b_WDSIZE:2; /* 2:3 Transfer word size */ + u16 b_DMA2D:1; /* 4 DMA mode */ + u16 b_RESTART:1; /* 5 Retain FIFO */ + u16 b_DI_SEL:1; /* 6 Data interrupt timing select */ + u16 b_DI_EN:1; /* 7 Data interrupt enabled */ + u16 b_NDSIZE:4; /* 8:11 Flex descriptor size */ + u16 b_FLOW:3; /* 12:14Flow */ +} ADI_DMA_CONFIG_REG; + +typedef struct adi_ether_frame_buffer { + u16 NoBytes; /* the no. of following bytes */ + u8 Dest[6]; /* destination MAC address */ + u8 Srce[6]; /* source MAC address */ + u16 LTfield; /* length/type field */ + u8 Data[0]; /* payload bytes */ +} ADI_ETHER_FRAME_BUFFER; +/* 16 bytes/struct */ + +typedef struct dma_descriptor { + struct dma_descriptor *NEXT_DESC_PTR; + u32 START_ADDR; + union { + u16 CONFIG_DATA; + ADI_DMA_CONFIG_REG CONFIG; + }; +} DMA_DESCRIPTOR; +/* 10 bytes/struct in 12 bytes */ + +typedef struct adi_ether_buffer { + DMA_DESCRIPTOR Dma[2]; /* first for the frame, second for the status */ + ADI_ETHER_FRAME_BUFFER *FrmData;/* pointer to data */ + struct adi_ether_buffer *pNext; /* next buffer */ + struct adi_ether_buffer *pPrev; /* prev buffer */ + u16 IPHdrChksum; /* the IP header checksum */ + u16 IPPayloadChksum; /* the IP header and payload checksum */ + volatile u32 StatusWord; /* the frame status word */ +} ADI_ETHER_BUFFER; +/* 40 bytes/struct in 44 bytes */ + +static ADI_ETHER_BUFFER *SetupRxBuffer(int no); +static ADI_ETHER_BUFFER *SetupTxBuffer(int no); + +static int bfin_EMAC_init(struct eth_device *dev, bd_t *bd); +static void bfin_EMAC_halt(struct eth_device *dev); +static int bfin_EMAC_send(struct eth_device *dev, void *packet, int length); +static int bfin_EMAC_recv(struct eth_device *dev); +static int bfin_EMAC_setup_addr(struct eth_device *dev); + +#endif diff --git a/sources/uboot-be550/drivers/net/calxedaxgmac.c b/sources/uboot-be550/drivers/net/calxedaxgmac.c new file mode 100644 index 00000000..c02b397f --- /dev/null +++ b/sources/uboot-be550/drivers/net/calxedaxgmac.c @@ -0,0 +1,544 @@ +/* + * Copyright 2010-2011 Calxeda, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +#define TX_NUM_DESC 1 +#define RX_NUM_DESC 32 + +#define MAC_TIMEOUT (5*CONFIG_SYS_HZ) + +#define ETH_BUF_SZ 2048 +#define TX_BUF_SZ (ETH_BUF_SZ * TX_NUM_DESC) +#define RX_BUF_SZ (ETH_BUF_SZ * RX_NUM_DESC) + +#define RXSTART 0x00000002 +#define TXSTART 0x00002000 + +#define RXENABLE 0x00000004 +#define TXENABLE 0x00000008 + +#define XGMAC_CONTROL_SPD 0x40000000 +#define XGMAC_CONTROL_SPD_MASK 0x60000000 +#define XGMAC_CONTROL_SARC 0x10000000 +#define XGMAC_CONTROL_SARK_MASK 0x18000000 +#define XGMAC_CONTROL_CAR 0x04000000 +#define XGMAC_CONTROL_CAR_MASK 0x06000000 +#define XGMAC_CONTROL_CAR_SHIFT 25 +#define XGMAC_CONTROL_DP 0x01000000 +#define XGMAC_CONTROL_WD 0x00800000 +#define XGMAC_CONTROL_JD 0x00400000 +#define XGMAC_CONTROL_JE 0x00100000 +#define XGMAC_CONTROL_LM 0x00001000 +#define XGMAC_CONTROL_IPC 0x00000400 +#define XGMAC_CONTROL_ACS 0x00000080 +#define XGMAC_CONTROL_DDIC 0x00000010 +#define XGMAC_CONTROL_TE 0x00000008 +#define XGMAC_CONTROL_RE 0x00000004 + +#define XGMAC_DMA_BUSMODE_RESET 0x00000001 +#define XGMAC_DMA_BUSMODE_DSL 0x00000004 +#define XGMAC_DMA_BUSMODE_DSL_MASK 0x0000007c +#define XGMAC_DMA_BUSMODE_DSL_SHIFT 2 +#define XGMAC_DMA_BUSMODE_ATDS 0x00000080 +#define XGMAC_DMA_BUSMODE_PBL_MASK 0x00003f00 +#define XGMAC_DMA_BUSMODE_PBL_SHIFT 8 +#define XGMAC_DMA_BUSMODE_FB 0x00010000 +#define XGMAC_DMA_BUSMODE_USP 0x00800000 +#define XGMAC_DMA_BUSMODE_8PBL 0x01000000 +#define XGMAC_DMA_BUSMODE_AAL 0x02000000 + +#define XGMAC_DMA_AXIMODE_ENLPI 0x80000000 +#define XGMAC_DMA_AXIMODE_MGK 0x40000000 +#define XGMAC_DMA_AXIMODE_WROSR 0x00100000 +#define XGMAC_DMA_AXIMODE_WROSR_MASK 0x00F00000 +#define XGMAC_DMA_AXIMODE_WROSR_SHIFT 20 +#define XGMAC_DMA_AXIMODE_RDOSR 0x00010000 +#define XGMAC_DMA_AXIMODE_RDOSR_MASK 0x000F0000 +#define XGMAC_DMA_AXIMODE_RDOSR_SHIFT 16 +#define XGMAC_DMA_AXIMODE_AAL 0x00001000 +#define XGMAC_DMA_AXIMODE_BLEN256 0x00000080 +#define XGMAC_DMA_AXIMODE_BLEN128 0x00000040 +#define XGMAC_DMA_AXIMODE_BLEN64 0x00000020 +#define XGMAC_DMA_AXIMODE_BLEN32 0x00000010 +#define XGMAC_DMA_AXIMODE_BLEN16 0x00000008 +#define XGMAC_DMA_AXIMODE_BLEN8 0x00000004 +#define XGMAC_DMA_AXIMODE_BLEN4 0x00000002 +#define XGMAC_DMA_AXIMODE_UNDEF 0x00000001 + +#define XGMAC_CORE_OMR_RTC_SHIFT 3 +#define XGMAC_CORE_OMR_RTC_MASK 0x00000018 +#define XGMAC_CORE_OMR_RTC 0x00000010 +#define XGMAC_CORE_OMR_RSF 0x00000020 +#define XGMAC_CORE_OMR_DT 0x00000040 +#define XGMAC_CORE_OMR_FEF 0x00000080 +#define XGMAC_CORE_OMR_EFC 0x00000100 +#define XGMAC_CORE_OMR_RFA_SHIFT 9 +#define XGMAC_CORE_OMR_RFA_MASK 0x00000E00 +#define XGMAC_CORE_OMR_RFD_SHIFT 12 +#define XGMAC_CORE_OMR_RFD_MASK 0x00007000 +#define XGMAC_CORE_OMR_TTC_SHIFT 16 +#define XGMAC_CORE_OMR_TTC_MASK 0x00030000 +#define XGMAC_CORE_OMR_TTC 0x00020000 +#define XGMAC_CORE_OMR_FTF 0x00100000 +#define XGMAC_CORE_OMR_TSF 0x00200000 + +#define FIFO_MINUS_1K 0x0 +#define FIFO_MINUS_2K 0x1 +#define FIFO_MINUS_3K 0x2 +#define FIFO_MINUS_4K 0x3 +#define FIFO_MINUS_6K 0x4 +#define FIFO_MINUS_8K 0x5 +#define FIFO_MINUS_12K 0x6 +#define FIFO_MINUS_16K 0x7 + +#define XGMAC_CORE_FLOW_PT_SHIFT 16 +#define XGMAC_CORE_FLOW_PT_MASK 0xFFFF0000 +#define XGMAC_CORE_FLOW_PT 0x00010000 +#define XGMAC_CORE_FLOW_DZQP 0x00000080 +#define XGMAC_CORE_FLOW_PLT_SHIFT 4 +#define XGMAC_CORE_FLOW_PLT_MASK 0x00000030 +#define XGMAC_CORE_FLOW_PLT 0x00000010 +#define XGMAC_CORE_FLOW_UP 0x00000008 +#define XGMAC_CORE_FLOW_RFE 0x00000004 +#define XGMAC_CORE_FLOW_TFE 0x00000002 +#define XGMAC_CORE_FLOW_FCB 0x00000001 + +/* XGMAC Descriptor Defines */ +#define MAX_DESC_BUF_SZ (0x2000 - 8) + +#define RXDESC_EXT_STATUS 0x00000001 +#define RXDESC_CRC_ERR 0x00000002 +#define RXDESC_RX_ERR 0x00000008 +#define RXDESC_RX_WDOG 0x00000010 +#define RXDESC_FRAME_TYPE 0x00000020 +#define RXDESC_GIANT_FRAME 0x00000080 +#define RXDESC_LAST_SEG 0x00000100 +#define RXDESC_FIRST_SEG 0x00000200 +#define RXDESC_VLAN_FRAME 0x00000400 +#define RXDESC_OVERFLOW_ERR 0x00000800 +#define RXDESC_LENGTH_ERR 0x00001000 +#define RXDESC_SA_FILTER_FAIL 0x00002000 +#define RXDESC_DESCRIPTOR_ERR 0x00004000 +#define RXDESC_ERROR_SUMMARY 0x00008000 +#define RXDESC_FRAME_LEN_OFFSET 16 +#define RXDESC_FRAME_LEN_MASK 0x3fff0000 +#define RXDESC_DA_FILTER_FAIL 0x40000000 + +#define RXDESC1_END_RING 0x00008000 + +#define RXDESC_IP_PAYLOAD_MASK 0x00000003 +#define RXDESC_IP_PAYLOAD_UDP 0x00000001 +#define RXDESC_IP_PAYLOAD_TCP 0x00000002 +#define RXDESC_IP_PAYLOAD_ICMP 0x00000003 +#define RXDESC_IP_HEADER_ERR 0x00000008 +#define RXDESC_IP_PAYLOAD_ERR 0x00000010 +#define RXDESC_IPV4_PACKET 0x00000040 +#define RXDESC_IPV6_PACKET 0x00000080 +#define TXDESC_UNDERFLOW_ERR 0x00000001 +#define TXDESC_JABBER_TIMEOUT 0x00000002 +#define TXDESC_LOCAL_FAULT 0x00000004 +#define TXDESC_REMOTE_FAULT 0x00000008 +#define TXDESC_VLAN_FRAME 0x00000010 +#define TXDESC_FRAME_FLUSHED 0x00000020 +#define TXDESC_IP_HEADER_ERR 0x00000040 +#define TXDESC_PAYLOAD_CSUM_ERR 0x00000080 +#define TXDESC_ERROR_SUMMARY 0x00008000 +#define TXDESC_SA_CTRL_INSERT 0x00040000 +#define TXDESC_SA_CTRL_REPLACE 0x00080000 +#define TXDESC_2ND_ADDR_CHAINED 0x00100000 +#define TXDESC_END_RING 0x00200000 +#define TXDESC_CSUM_IP 0x00400000 +#define TXDESC_CSUM_IP_PAYLD 0x00800000 +#define TXDESC_CSUM_ALL 0x00C00000 +#define TXDESC_CRC_EN_REPLACE 0x01000000 +#define TXDESC_CRC_EN_APPEND 0x02000000 +#define TXDESC_DISABLE_PAD 0x04000000 +#define TXDESC_FIRST_SEG 0x10000000 +#define TXDESC_LAST_SEG 0x20000000 +#define TXDESC_INTERRUPT 0x40000000 + +#define DESC_OWN 0x80000000 +#define DESC_BUFFER1_SZ_MASK 0x00001fff +#define DESC_BUFFER2_SZ_MASK 0x1fff0000 +#define DESC_BUFFER2_SZ_OFFSET 16 + +struct xgmac_regs { + u32 config; + u32 framefilter; + u32 resv_1[4]; + u32 flow_control; + u32 vlantag; + u32 version; + u32 vlaninclude; + u32 resv_2[2]; + u32 pacestretch; + u32 vlanhash; + u32 resv_3; + u32 intreg; + struct { + u32 hi; /* 0x40 */ + u32 lo; /* 0x44 */ + } macaddr[16]; + u32 resv_4[0xd0]; + u32 core_opmode; /* 0x400 */ + u32 resv_5[0x2bf]; + u32 busmode; /* 0xf00 */ + u32 txpoll; + u32 rxpoll; + u32 rxdesclist; + u32 txdesclist; + u32 dma_status; + u32 dma_opmode; + u32 intenable; + u32 resv_6[2]; + u32 axi_mode; /* 0xf28 */ +}; + +struct xgmac_dma_desc { + __le32 flags; + __le32 buf_size; + __le32 buf1_addr; /* Buffer 1 Address Pointer */ + __le32 buf2_addr; /* Buffer 2 Address Pointer */ + __le32 ext_status; + __le32 res[3]; +}; + +/* XGMAC Descriptor Access Helpers */ +static inline void desc_set_buf_len(struct xgmac_dma_desc *p, u32 buf_sz) +{ + if (buf_sz > MAX_DESC_BUF_SZ) + p->buf_size = cpu_to_le32(MAX_DESC_BUF_SZ | + (buf_sz - MAX_DESC_BUF_SZ) << DESC_BUFFER2_SZ_OFFSET); + else + p->buf_size = cpu_to_le32(buf_sz); +} + +static inline int desc_get_buf_len(struct xgmac_dma_desc *p) +{ + u32 len = le32_to_cpu(p->buf_size); + return (len & DESC_BUFFER1_SZ_MASK) + + ((len & DESC_BUFFER2_SZ_MASK) >> DESC_BUFFER2_SZ_OFFSET); +} + +static inline void desc_init_rx_desc(struct xgmac_dma_desc *p, int ring_size, + int buf_sz) +{ + struct xgmac_dma_desc *end = p + ring_size - 1; + + memset(p, 0, sizeof(*p) * ring_size); + + for (; p <= end; p++) + desc_set_buf_len(p, buf_sz); + + end->buf_size |= cpu_to_le32(RXDESC1_END_RING); +} + +static inline void desc_init_tx_desc(struct xgmac_dma_desc *p, u32 ring_size) +{ + memset(p, 0, sizeof(*p) * ring_size); + p[ring_size - 1].flags = cpu_to_le32(TXDESC_END_RING); +} + +static inline int desc_get_owner(struct xgmac_dma_desc *p) +{ + return le32_to_cpu(p->flags) & DESC_OWN; +} + +static inline void desc_set_rx_owner(struct xgmac_dma_desc *p) +{ + /* Clear all fields and set the owner */ + p->flags = cpu_to_le32(DESC_OWN); +} + +static inline void desc_set_tx_owner(struct xgmac_dma_desc *p, u32 flags) +{ + u32 tmpflags = le32_to_cpu(p->flags); + tmpflags &= TXDESC_END_RING; + tmpflags |= flags | DESC_OWN; + p->flags = cpu_to_le32(tmpflags); +} + +static inline void *desc_get_buf_addr(struct xgmac_dma_desc *p) +{ + return (void *)le32_to_cpu(p->buf1_addr); +} + +static inline void desc_set_buf_addr(struct xgmac_dma_desc *p, + void *paddr, int len) +{ + p->buf1_addr = cpu_to_le32(paddr); + if (len > MAX_DESC_BUF_SZ) + p->buf2_addr = cpu_to_le32(paddr + MAX_DESC_BUF_SZ); +} + +static inline void desc_set_buf_addr_and_size(struct xgmac_dma_desc *p, + void *paddr, int len) +{ + desc_set_buf_len(p, len); + desc_set_buf_addr(p, paddr, len); +} + +static inline int desc_get_rx_frame_len(struct xgmac_dma_desc *p) +{ + u32 data = le32_to_cpu(p->flags); + u32 len = (data & RXDESC_FRAME_LEN_MASK) >> RXDESC_FRAME_LEN_OFFSET; + if (data & RXDESC_FRAME_TYPE) + len -= 4; + + return len; +} + +struct calxeda_eth_dev { + struct xgmac_dma_desc rx_chain[RX_NUM_DESC]; + struct xgmac_dma_desc tx_chain[TX_NUM_DESC]; + char rxbuffer[RX_BUF_SZ]; + + u32 tx_currdesc; + u32 rx_currdesc; + + struct eth_device *dev; +} __aligned(32); + +/* + * Initialize a descriptor ring. Calxeda XGMAC is configured to use + * advanced descriptors. + */ + +static void init_rx_desc(struct calxeda_eth_dev *priv) +{ + struct xgmac_dma_desc *rxdesc = priv->rx_chain; + struct xgmac_regs *regs = (struct xgmac_regs *)priv->dev->iobase; + void *rxbuffer = priv->rxbuffer; + int i; + + desc_init_rx_desc(rxdesc, RX_NUM_DESC, ETH_BUF_SZ); + writel((ulong)rxdesc, ®s->rxdesclist); + + for (i = 0; i < RX_NUM_DESC; i++) { + desc_set_buf_addr(rxdesc + i, rxbuffer + (i * ETH_BUF_SZ), + ETH_BUF_SZ); + desc_set_rx_owner(rxdesc + i); + } +} + +static void init_tx_desc(struct calxeda_eth_dev *priv) +{ + struct xgmac_regs *regs = (struct xgmac_regs *)priv->dev->iobase; + + desc_init_tx_desc(priv->tx_chain, TX_NUM_DESC); + writel((ulong)priv->tx_chain, ®s->txdesclist); +} + +static int xgmac_reset(struct eth_device *dev) +{ + struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase; + int timeout = MAC_TIMEOUT; + u32 value; + + value = readl(®s->config) & XGMAC_CONTROL_SPD_MASK; + + writel(XGMAC_DMA_BUSMODE_RESET, ®s->busmode); + while ((timeout-- >= 0) && + (readl(®s->busmode) & XGMAC_DMA_BUSMODE_RESET)) + udelay(1); + + writel(value, ®s->config); + + return timeout; +} + +static void xgmac_hwmacaddr(struct eth_device *dev) +{ + struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase; + u32 macaddr[2]; + + memcpy(macaddr, dev->enetaddr, 6); + writel(macaddr[1], ®s->macaddr[0].hi); + writel(macaddr[0], ®s->macaddr[0].lo); +} + +static int xgmac_init(struct eth_device *dev, bd_t * bis) +{ + struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase; + struct calxeda_eth_dev *priv = dev->priv; + int value; + + if (xgmac_reset(dev) < 0) + return -1; + + /* set the hardware MAC address */ + xgmac_hwmacaddr(dev); + + /* set the AXI bus modes */ + value = XGMAC_DMA_BUSMODE_ATDS | + (16 << XGMAC_DMA_BUSMODE_PBL_SHIFT) | + XGMAC_DMA_BUSMODE_FB | XGMAC_DMA_BUSMODE_AAL; + writel(value, ®s->busmode); + + value = XGMAC_DMA_AXIMODE_AAL | XGMAC_DMA_AXIMODE_BLEN16 | + XGMAC_DMA_AXIMODE_BLEN8 | XGMAC_DMA_AXIMODE_BLEN4; + writel(value, ®s->axi_mode); + + /* set flow control parameters and store and forward mode */ + value = (FIFO_MINUS_12K << XGMAC_CORE_OMR_RFD_SHIFT) | + (FIFO_MINUS_4K << XGMAC_CORE_OMR_RFA_SHIFT) | + XGMAC_CORE_OMR_EFC | XGMAC_CORE_OMR_TSF; + writel(value, ®s->core_opmode); + + /* enable pause frames */ + value = (1024 << XGMAC_CORE_FLOW_PT_SHIFT) | + (1 << XGMAC_CORE_FLOW_PLT_SHIFT) | + XGMAC_CORE_FLOW_UP | XGMAC_CORE_FLOW_RFE | XGMAC_CORE_FLOW_TFE; + writel(value, ®s->flow_control); + + /* Initialize the descriptor chains */ + init_rx_desc(priv); + init_tx_desc(priv); + + /* must set to 0, or when started up will cause issues */ + priv->tx_currdesc = 0; + priv->rx_currdesc = 0; + + /* set default core values */ + value = readl(®s->config); + value &= XGMAC_CONTROL_SPD_MASK; + value |= XGMAC_CONTROL_DDIC | XGMAC_CONTROL_ACS | + XGMAC_CONTROL_IPC | XGMAC_CONTROL_CAR; + + /* Everything is ready enable both mac and DMA */ + value |= RXENABLE | TXENABLE; + writel(value, ®s->config); + + value = readl(®s->dma_opmode); + value |= RXSTART | TXSTART; + writel(value, ®s->dma_opmode); + + return 0; +} + +static int xgmac_tx(struct eth_device *dev, void *packet, int length) +{ + struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase; + struct calxeda_eth_dev *priv = dev->priv; + u32 currdesc = priv->tx_currdesc; + struct xgmac_dma_desc *txdesc = &priv->tx_chain[currdesc]; + int timeout; + + desc_set_buf_addr_and_size(txdesc, packet, length); + desc_set_tx_owner(txdesc, TXDESC_FIRST_SEG | + TXDESC_LAST_SEG | TXDESC_CRC_EN_APPEND); + + /* write poll demand */ + writel(1, ®s->txpoll); + + timeout = 1000000; + while (desc_get_owner(txdesc)) { + if (timeout-- < 0) { + printf("xgmac: TX timeout\n"); + return -ETIMEDOUT; + } + udelay(1); + } + + priv->tx_currdesc = (currdesc + 1) & (TX_NUM_DESC - 1); + return 0; +} + +static int xgmac_rx(struct eth_device *dev) +{ + struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase; + struct calxeda_eth_dev *priv = dev->priv; + u32 currdesc = priv->rx_currdesc; + struct xgmac_dma_desc *rxdesc = &priv->rx_chain[currdesc]; + int length = 0; + + /* check if the host has the desc */ + if (desc_get_owner(rxdesc)) + return -1; /* something bad happened */ + + length = desc_get_rx_frame_len(rxdesc); + + net_process_received_packet(desc_get_buf_addr(rxdesc), length); + + /* set descriptor back to owned by XGMAC */ + desc_set_rx_owner(rxdesc); + writel(1, ®s->rxpoll); + + priv->rx_currdesc = (currdesc + 1) & (RX_NUM_DESC - 1); + + return length; +} + +static void xgmac_halt(struct eth_device *dev) +{ + struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase; + struct calxeda_eth_dev *priv = dev->priv; + int value; + + /* Disable TX/RX */ + value = readl(®s->config); + value &= ~(RXENABLE | TXENABLE); + writel(value, ®s->config); + + /* Disable DMA */ + value = readl(®s->dma_opmode); + value &= ~(RXSTART | TXSTART); + writel(value, ®s->dma_opmode); + + /* must set to 0, or when started up will cause issues */ + priv->tx_currdesc = 0; + priv->rx_currdesc = 0; +} + +int calxedaxgmac_initialize(u32 id, ulong base_addr) +{ + struct eth_device *dev; + struct calxeda_eth_dev *priv; + struct xgmac_regs *regs; + u32 macaddr[2]; + + regs = (struct xgmac_regs *)base_addr; + + /* check hardware version */ + if (readl(®s->version) != 0x1012) + return -1; + + dev = malloc(sizeof(*dev)); + if (!dev) + return 0; + memset(dev, 0, sizeof(*dev)); + + /* Structure must be aligned, because it contains the descriptors */ + priv = memalign(32, sizeof(*priv)); + if (!priv) { + free(dev); + return 0; + } + + dev->iobase = (int)base_addr; + dev->priv = priv; + priv->dev = dev; + sprintf(dev->name, "xgmac%d", id); + + /* The MAC address is already configured, so read it from registers. */ + macaddr[1] = readl(®s->macaddr[0].hi); + macaddr[0] = readl(®s->macaddr[0].lo); + memcpy(dev->enetaddr, macaddr, 6); + + dev->init = xgmac_init; + dev->send = xgmac_tx; + dev->recv = xgmac_rx; + dev->halt = xgmac_halt; + + eth_register(dev); + + return 1; +} diff --git a/sources/uboot-be550/drivers/net/cpsw.c b/sources/uboot-be550/drivers/net/cpsw.c new file mode 100644 index 00000000..3dff9df3 --- /dev/null +++ b/sources/uboot-be550/drivers/net/cpsw.c @@ -0,0 +1,1294 @@ +/* + * CPSW Ethernet Switch Driver + * + * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define BITMASK(bits) (BIT(bits) - 1) +#define PHY_REG_MASK 0x1f +#define PHY_ID_MASK 0x1f +#define NUM_DESCS (PKTBUFSRX * 2) +#define PKT_MIN 60 +#define PKT_MAX (1500 + 14 + 4 + 4) +#define CLEAR_BIT 1 +#define GIGABITEN BIT(7) +#define FULLDUPLEXEN BIT(0) +#define MIIEN BIT(15) + +/* reg offset */ +#define CPSW_HOST_PORT_OFFSET 0x108 +#define CPSW_SLAVE0_OFFSET 0x208 +#define CPSW_SLAVE1_OFFSET 0x308 +#define CPSW_SLAVE_SIZE 0x100 +#define CPSW_CPDMA_OFFSET 0x800 +#define CPSW_HW_STATS 0x900 +#define CPSW_STATERAM_OFFSET 0xa00 +#define CPSW_CPTS_OFFSET 0xc00 +#define CPSW_ALE_OFFSET 0xd00 +#define CPSW_SLIVER0_OFFSET 0xd80 +#define CPSW_SLIVER1_OFFSET 0xdc0 +#define CPSW_BD_OFFSET 0x2000 +#define CPSW_MDIO_DIV 0xff + +#define AM335X_GMII_SEL_OFFSET 0x630 + +/* DMA Registers */ +#define CPDMA_TXCONTROL 0x004 +#define CPDMA_RXCONTROL 0x014 +#define CPDMA_SOFTRESET 0x01c +#define CPDMA_RXFREE 0x0e0 +#define CPDMA_TXHDP_VER1 0x100 +#define CPDMA_TXHDP_VER2 0x200 +#define CPDMA_RXHDP_VER1 0x120 +#define CPDMA_RXHDP_VER2 0x220 +#define CPDMA_TXCP_VER1 0x140 +#define CPDMA_TXCP_VER2 0x240 +#define CPDMA_RXCP_VER1 0x160 +#define CPDMA_RXCP_VER2 0x260 + +/* Descriptor mode bits */ +#define CPDMA_DESC_SOP BIT(31) +#define CPDMA_DESC_EOP BIT(30) +#define CPDMA_DESC_OWNER BIT(29) +#define CPDMA_DESC_EOQ BIT(28) + +/* + * This timeout definition is a worst-case ultra defensive measure against + * unexpected controller lock ups. Ideally, we should never ever hit this + * scenario in practice. + */ +#define MDIO_TIMEOUT 100 /* msecs */ +#define CPDMA_TIMEOUT 100 /* msecs */ + +struct cpsw_mdio_regs { + u32 version; + u32 control; +#define CONTROL_IDLE BIT(31) +#define CONTROL_ENABLE BIT(30) + + u32 alive; + u32 link; + u32 linkintraw; + u32 linkintmasked; + u32 __reserved_0[2]; + u32 userintraw; + u32 userintmasked; + u32 userintmaskset; + u32 userintmaskclr; + u32 __reserved_1[20]; + + struct { + u32 access; + u32 physel; +#define USERACCESS_GO BIT(31) +#define USERACCESS_WRITE BIT(30) +#define USERACCESS_ACK BIT(29) +#define USERACCESS_READ (0) +#define USERACCESS_DATA (0xffff) + } user[0]; +}; + +struct cpsw_regs { + u32 id_ver; + u32 control; + u32 soft_reset; + u32 stat_port_en; + u32 ptype; +}; + +struct cpsw_slave_regs { + u32 max_blks; + u32 blk_cnt; + u32 flow_thresh; + u32 port_vlan; + u32 tx_pri_map; +#ifdef CONFIG_AM33XX + u32 gap_thresh; +#elif defined(CONFIG_TI814X) + u32 ts_ctl; + u32 ts_seq_ltype; + u32 ts_vlan; +#endif + u32 sa_lo; + u32 sa_hi; +}; + +struct cpsw_host_regs { + u32 max_blks; + u32 blk_cnt; + u32 flow_thresh; + u32 port_vlan; + u32 tx_pri_map; + u32 cpdma_tx_pri_map; + u32 cpdma_rx_chan_map; +}; + +struct cpsw_sliver_regs { + u32 id_ver; + u32 mac_control; + u32 mac_status; + u32 soft_reset; + u32 rx_maxlen; + u32 __reserved_0; + u32 rx_pause; + u32 tx_pause; + u32 __reserved_1; + u32 rx_pri_map; +}; + +#define ALE_ENTRY_BITS 68 +#define ALE_ENTRY_WORDS DIV_ROUND_UP(ALE_ENTRY_BITS, 32) + +/* ALE Registers */ +#define ALE_CONTROL 0x08 +#define ALE_UNKNOWNVLAN 0x18 +#define ALE_TABLE_CONTROL 0x20 +#define ALE_TABLE 0x34 +#define ALE_PORTCTL 0x40 + +#define ALE_TABLE_WRITE BIT(31) + +#define ALE_TYPE_FREE 0 +#define ALE_TYPE_ADDR 1 +#define ALE_TYPE_VLAN 2 +#define ALE_TYPE_VLAN_ADDR 3 + +#define ALE_UCAST_PERSISTANT 0 +#define ALE_UCAST_UNTOUCHED 1 +#define ALE_UCAST_OUI 2 +#define ALE_UCAST_TOUCHED 3 + +#define ALE_MCAST_FWD 0 +#define ALE_MCAST_BLOCK_LEARN_FWD 1 +#define ALE_MCAST_FWD_LEARN 2 +#define ALE_MCAST_FWD_2 3 + +enum cpsw_ale_port_state { + ALE_PORT_STATE_DISABLE = 0x00, + ALE_PORT_STATE_BLOCK = 0x01, + ALE_PORT_STATE_LEARN = 0x02, + ALE_PORT_STATE_FORWARD = 0x03, +}; + +/* ALE unicast entry flags - passed into cpsw_ale_add_ucast() */ +#define ALE_SECURE 1 +#define ALE_BLOCKED 2 + +struct cpsw_slave { + struct cpsw_slave_regs *regs; + struct cpsw_sliver_regs *sliver; + int slave_num; + u32 mac_control; + struct cpsw_slave_data *data; +}; + +struct cpdma_desc { + /* hardware fields */ + u32 hw_next; + u32 hw_buffer; + u32 hw_len; + u32 hw_mode; + /* software fields */ + u32 sw_buffer; + u32 sw_len; +}; + +struct cpdma_chan { + struct cpdma_desc *head, *tail; + void *hdp, *cp, *rxfree; +}; + +#define desc_write(desc, fld, val) __raw_writel((u32)(val), &(desc)->fld) +#define desc_read(desc, fld) __raw_readl(&(desc)->fld) +#define desc_read_ptr(desc, fld) ((void *)__raw_readl(&(desc)->fld)) + +#define chan_write(chan, fld, val) __raw_writel((u32)(val), (chan)->fld) +#define chan_read(chan, fld) __raw_readl((chan)->fld) +#define chan_read_ptr(chan, fld) ((void *)__raw_readl((chan)->fld)) + +#define for_active_slave(slave, priv) \ + slave = (priv)->slaves + (priv)->data.active_slave; if (slave) +#define for_each_slave(slave, priv) \ + for (slave = (priv)->slaves; slave != (priv)->slaves + \ + (priv)->data.slaves; slave++) + +struct cpsw_priv { +#ifdef CONFIG_DM_ETH + struct udevice *dev; +#else + struct eth_device *dev; +#endif + struct cpsw_platform_data data; + int host_port; + + struct cpsw_regs *regs; + void *dma_regs; + struct cpsw_host_regs *host_port_regs; + void *ale_regs; + + struct cpdma_desc *descs; + struct cpdma_desc *desc_free; + struct cpdma_chan rx_chan, tx_chan; + + struct cpsw_slave *slaves; + struct phy_device *phydev; + struct mii_dev *bus; + + u32 phy_mask; +}; + +static inline int cpsw_ale_get_field(u32 *ale_entry, u32 start, u32 bits) +{ + int idx; + + idx = start / 32; + start -= idx * 32; + idx = 2 - idx; /* flip */ + return (ale_entry[idx] >> start) & BITMASK(bits); +} + +static inline void cpsw_ale_set_field(u32 *ale_entry, u32 start, u32 bits, + u32 value) +{ + int idx; + + value &= BITMASK(bits); + idx = start / 32; + start -= idx * 32; + idx = 2 - idx; /* flip */ + ale_entry[idx] &= ~(BITMASK(bits) << start); + ale_entry[idx] |= (value << start); +} + +#define DEFINE_ALE_FIELD(name, start, bits) \ +static inline int cpsw_ale_get_##name(u32 *ale_entry) \ +{ \ + return cpsw_ale_get_field(ale_entry, start, bits); \ +} \ +static inline void cpsw_ale_set_##name(u32 *ale_entry, u32 value) \ +{ \ + cpsw_ale_set_field(ale_entry, start, bits, value); \ +} + +DEFINE_ALE_FIELD(entry_type, 60, 2) +DEFINE_ALE_FIELD(mcast_state, 62, 2) +DEFINE_ALE_FIELD(port_mask, 66, 3) +DEFINE_ALE_FIELD(ucast_type, 62, 2) +DEFINE_ALE_FIELD(port_num, 66, 2) +DEFINE_ALE_FIELD(blocked, 65, 1) +DEFINE_ALE_FIELD(secure, 64, 1) +DEFINE_ALE_FIELD(mcast, 40, 1) + +/* The MAC address field in the ALE entry cannot be macroized as above */ +static inline void cpsw_ale_get_addr(u32 *ale_entry, u8 *addr) +{ + int i; + + for (i = 0; i < 6; i++) + addr[i] = cpsw_ale_get_field(ale_entry, 40 - 8*i, 8); +} + +static inline void cpsw_ale_set_addr(u32 *ale_entry, const u8 *addr) +{ + int i; + + for (i = 0; i < 6; i++) + cpsw_ale_set_field(ale_entry, 40 - 8*i, 8, addr[i]); +} + +static int cpsw_ale_read(struct cpsw_priv *priv, int idx, u32 *ale_entry) +{ + int i; + + __raw_writel(idx, priv->ale_regs + ALE_TABLE_CONTROL); + + for (i = 0; i < ALE_ENTRY_WORDS; i++) + ale_entry[i] = __raw_readl(priv->ale_regs + ALE_TABLE + 4 * i); + + return idx; +} + +static int cpsw_ale_write(struct cpsw_priv *priv, int idx, u32 *ale_entry) +{ + int i; + + for (i = 0; i < ALE_ENTRY_WORDS; i++) + __raw_writel(ale_entry[i], priv->ale_regs + ALE_TABLE + 4 * i); + + __raw_writel(idx | ALE_TABLE_WRITE, priv->ale_regs + ALE_TABLE_CONTROL); + + return idx; +} + +static int cpsw_ale_match_addr(struct cpsw_priv *priv, const u8 *addr) +{ + u32 ale_entry[ALE_ENTRY_WORDS]; + int type, idx; + + for (idx = 0; idx < priv->data.ale_entries; idx++) { + u8 entry_addr[6]; + + cpsw_ale_read(priv, idx, ale_entry); + type = cpsw_ale_get_entry_type(ale_entry); + if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR) + continue; + cpsw_ale_get_addr(ale_entry, entry_addr); + if (memcmp(entry_addr, addr, 6) == 0) + return idx; + } + return -ENOENT; +} + +static int cpsw_ale_match_free(struct cpsw_priv *priv) +{ + u32 ale_entry[ALE_ENTRY_WORDS]; + int type, idx; + + for (idx = 0; idx < priv->data.ale_entries; idx++) { + cpsw_ale_read(priv, idx, ale_entry); + type = cpsw_ale_get_entry_type(ale_entry); + if (type == ALE_TYPE_FREE) + return idx; + } + return -ENOENT; +} + +static int cpsw_ale_find_ageable(struct cpsw_priv *priv) +{ + u32 ale_entry[ALE_ENTRY_WORDS]; + int type, idx; + + for (idx = 0; idx < priv->data.ale_entries; idx++) { + cpsw_ale_read(priv, idx, ale_entry); + type = cpsw_ale_get_entry_type(ale_entry); + if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR) + continue; + if (cpsw_ale_get_mcast(ale_entry)) + continue; + type = cpsw_ale_get_ucast_type(ale_entry); + if (type != ALE_UCAST_PERSISTANT && + type != ALE_UCAST_OUI) + return idx; + } + return -ENOENT; +} + +static int cpsw_ale_add_ucast(struct cpsw_priv *priv, const u8 *addr, + int port, int flags) +{ + u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0}; + int idx; + + cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR); + cpsw_ale_set_addr(ale_entry, addr); + cpsw_ale_set_ucast_type(ale_entry, ALE_UCAST_PERSISTANT); + cpsw_ale_set_secure(ale_entry, (flags & ALE_SECURE) ? 1 : 0); + cpsw_ale_set_blocked(ale_entry, (flags & ALE_BLOCKED) ? 1 : 0); + cpsw_ale_set_port_num(ale_entry, port); + + idx = cpsw_ale_match_addr(priv, addr); + if (idx < 0) + idx = cpsw_ale_match_free(priv); + if (idx < 0) + idx = cpsw_ale_find_ageable(priv); + if (idx < 0) + return -ENOMEM; + + cpsw_ale_write(priv, idx, ale_entry); + return 0; +} + +static int cpsw_ale_add_mcast(struct cpsw_priv *priv, const u8 *addr, + int port_mask) +{ + u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0}; + int idx, mask; + + idx = cpsw_ale_match_addr(priv, addr); + if (idx >= 0) + cpsw_ale_read(priv, idx, ale_entry); + + cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR); + cpsw_ale_set_addr(ale_entry, addr); + cpsw_ale_set_mcast_state(ale_entry, ALE_MCAST_FWD_2); + + mask = cpsw_ale_get_port_mask(ale_entry); + port_mask |= mask; + cpsw_ale_set_port_mask(ale_entry, port_mask); + + if (idx < 0) + idx = cpsw_ale_match_free(priv); + if (idx < 0) + idx = cpsw_ale_find_ageable(priv); + if (idx < 0) + return -ENOMEM; + + cpsw_ale_write(priv, idx, ale_entry); + return 0; +} + +static inline void cpsw_ale_control(struct cpsw_priv *priv, int bit, int val) +{ + u32 tmp, mask = BIT(bit); + + tmp = __raw_readl(priv->ale_regs + ALE_CONTROL); + tmp &= ~mask; + tmp |= val ? mask : 0; + __raw_writel(tmp, priv->ale_regs + ALE_CONTROL); +} + +#define cpsw_ale_enable(priv, val) cpsw_ale_control(priv, 31, val) +#define cpsw_ale_clear(priv, val) cpsw_ale_control(priv, 30, val) +#define cpsw_ale_vlan_aware(priv, val) cpsw_ale_control(priv, 2, val) + +static inline void cpsw_ale_port_state(struct cpsw_priv *priv, int port, + int val) +{ + int offset = ALE_PORTCTL + 4 * port; + u32 tmp, mask = 0x3; + + tmp = __raw_readl(priv->ale_regs + offset); + tmp &= ~mask; + tmp |= val & mask; + __raw_writel(tmp, priv->ale_regs + offset); +} + +static struct cpsw_mdio_regs *mdio_regs; + +/* wait until hardware is ready for another user access */ +static inline u32 wait_for_user_access(void) +{ + u32 reg = 0; + int timeout = MDIO_TIMEOUT; + + while (timeout-- && + ((reg = __raw_readl(&mdio_regs->user[0].access)) & USERACCESS_GO)) + udelay(10); + + if (timeout == -1) { + printf("wait_for_user_access Timeout\n"); + return -ETIMEDOUT; + } + return reg; +} + +/* wait until hardware state machine is idle */ +static inline void wait_for_idle(void) +{ + int timeout = MDIO_TIMEOUT; + + while (timeout-- && + ((__raw_readl(&mdio_regs->control) & CONTROL_IDLE) == 0)) + udelay(10); + + if (timeout == -1) + printf("wait_for_idle Timeout\n"); +} + +static int cpsw_mdio_read(struct mii_dev *bus, int phy_id, + int dev_addr, int phy_reg) +{ + int data; + u32 reg; + + if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK) + return -EINVAL; + + wait_for_user_access(); + reg = (USERACCESS_GO | USERACCESS_READ | (phy_reg << 21) | + (phy_id << 16)); + __raw_writel(reg, &mdio_regs->user[0].access); + reg = wait_for_user_access(); + + data = (reg & USERACCESS_ACK) ? (reg & USERACCESS_DATA) : -1; + return data; +} + +static int cpsw_mdio_write(struct mii_dev *bus, int phy_id, int dev_addr, + int phy_reg, u16 data) +{ + u32 reg; + + if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK) + return -EINVAL; + + wait_for_user_access(); + reg = (USERACCESS_GO | USERACCESS_WRITE | (phy_reg << 21) | + (phy_id << 16) | (data & USERACCESS_DATA)); + __raw_writel(reg, &mdio_regs->user[0].access); + wait_for_user_access(); + + return 0; +} + +static void cpsw_mdio_init(const char *name, u32 mdio_base, u32 div) +{ + struct mii_dev *bus = mdio_alloc(); + + mdio_regs = (struct cpsw_mdio_regs *)mdio_base; + + /* set enable and clock divider */ + __raw_writel(div | CONTROL_ENABLE, &mdio_regs->control); + + /* + * wait for scan logic to settle: + * the scan time consists of (a) a large fixed component, and (b) a + * small component that varies with the mii bus frequency. These + * were estimated using measurements at 1.1 and 2.2 MHz on tnetv107x + * silicon. Since the effect of (b) was found to be largely + * negligible, we keep things simple here. + */ + udelay(1000); + + bus->read = cpsw_mdio_read; + bus->write = cpsw_mdio_write; + sprintf(bus->name, name); + + mdio_register(bus); +} + +/* Set a self-clearing bit in a register, and wait for it to clear */ +static inline void setbit_and_wait_for_clear32(void *addr) +{ + __raw_writel(CLEAR_BIT, addr); + while (__raw_readl(addr) & CLEAR_BIT) + ; +} + +#define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \ + ((mac)[2] << 16) | ((mac)[3] << 24)) +#define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8)) + +static void cpsw_set_slave_mac(struct cpsw_slave *slave, + struct cpsw_priv *priv) +{ +#ifdef CONFIG_DM_ETH + struct eth_pdata *pdata = dev_get_platdata(priv->dev); + + writel(mac_hi(pdata->enetaddr), &slave->regs->sa_hi); + writel(mac_lo(pdata->enetaddr), &slave->regs->sa_lo); +#else + __raw_writel(mac_hi(priv->dev->enetaddr), &slave->regs->sa_hi); + __raw_writel(mac_lo(priv->dev->enetaddr), &slave->regs->sa_lo); +#endif +} + +static void cpsw_slave_update_link(struct cpsw_slave *slave, + struct cpsw_priv *priv, int *link) +{ + struct phy_device *phy; + u32 mac_control = 0; + + phy = priv->phydev; + + if (!phy) + return; + + phy_startup(phy); + *link = phy->link; + + if (*link) { /* link up */ + mac_control = priv->data.mac_control; + if (phy->speed == 1000) + mac_control |= GIGABITEN; + if (phy->duplex == DUPLEX_FULL) + mac_control |= FULLDUPLEXEN; + if (phy->speed == 100) + mac_control |= MIIEN; + } + + if (mac_control == slave->mac_control) + return; + + if (mac_control) { + printf("link up on port %d, speed %d, %s duplex\n", + slave->slave_num, phy->speed, + (phy->duplex == DUPLEX_FULL) ? "full" : "half"); + } else { + printf("link down on port %d\n", slave->slave_num); + } + + __raw_writel(mac_control, &slave->sliver->mac_control); + slave->mac_control = mac_control; +} + +static int cpsw_update_link(struct cpsw_priv *priv) +{ + int link = 0; + struct cpsw_slave *slave; + + for_active_slave(slave, priv) + cpsw_slave_update_link(slave, priv, &link); + + return link; +} + +static inline u32 cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num) +{ + if (priv->host_port == 0) + return slave_num + 1; + else + return slave_num; +} + +static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv) +{ + u32 slave_port; + + setbit_and_wait_for_clear32(&slave->sliver->soft_reset); + + /* setup priority mapping */ + __raw_writel(0x76543210, &slave->sliver->rx_pri_map); + __raw_writel(0x33221100, &slave->regs->tx_pri_map); + + /* setup max packet size, and mac address */ + __raw_writel(PKT_MAX, &slave->sliver->rx_maxlen); + cpsw_set_slave_mac(slave, priv); + + slave->mac_control = 0; /* no link yet */ + + /* enable forwarding */ + slave_port = cpsw_get_slave_port(priv, slave->slave_num); + cpsw_ale_port_state(priv, slave_port, ALE_PORT_STATE_FORWARD); + + cpsw_ale_add_mcast(priv, net_bcast_ethaddr, 1 << slave_port); + + priv->phy_mask |= 1 << slave->data->phy_addr; +} + +static struct cpdma_desc *cpdma_desc_alloc(struct cpsw_priv *priv) +{ + struct cpdma_desc *desc = priv->desc_free; + + if (desc) + priv->desc_free = desc_read_ptr(desc, hw_next); + return desc; +} + +static void cpdma_desc_free(struct cpsw_priv *priv, struct cpdma_desc *desc) +{ + if (desc) { + desc_write(desc, hw_next, priv->desc_free); + priv->desc_free = desc; + } +} + +static int cpdma_submit(struct cpsw_priv *priv, struct cpdma_chan *chan, + void *buffer, int len) +{ + struct cpdma_desc *desc, *prev; + u32 mode; + + desc = cpdma_desc_alloc(priv); + if (!desc) + return -ENOMEM; + + if (len < PKT_MIN) + len = PKT_MIN; + + mode = CPDMA_DESC_OWNER | CPDMA_DESC_SOP | CPDMA_DESC_EOP; + + desc_write(desc, hw_next, 0); + desc_write(desc, hw_buffer, buffer); + desc_write(desc, hw_len, len); + desc_write(desc, hw_mode, mode | len); + desc_write(desc, sw_buffer, buffer); + desc_write(desc, sw_len, len); + + if (!chan->head) { + /* simple case - first packet enqueued */ + chan->head = desc; + chan->tail = desc; + chan_write(chan, hdp, desc); + goto done; + } + + /* not the first packet - enqueue at the tail */ + prev = chan->tail; + desc_write(prev, hw_next, desc); + chan->tail = desc; + + /* next check if EOQ has been triggered already */ + if (desc_read(prev, hw_mode) & CPDMA_DESC_EOQ) + chan_write(chan, hdp, desc); + +done: + if (chan->rxfree) + chan_write(chan, rxfree, 1); + return 0; +} + +static int cpdma_process(struct cpsw_priv *priv, struct cpdma_chan *chan, + void **buffer, int *len) +{ + struct cpdma_desc *desc = chan->head; + u32 status; + + if (!desc) + return -ENOENT; + + status = desc_read(desc, hw_mode); + + if (len) + *len = status & 0x7ff; + + if (buffer) + *buffer = desc_read_ptr(desc, sw_buffer); + + if (status & CPDMA_DESC_OWNER) { + if (chan_read(chan, hdp) == 0) { + if (desc_read(desc, hw_mode) & CPDMA_DESC_OWNER) + chan_write(chan, hdp, desc); + } + + return -EBUSY; + } + + chan->head = desc_read_ptr(desc, hw_next); + chan_write(chan, cp, desc); + + cpdma_desc_free(priv, desc); + return 0; +} + +static int _cpsw_init(struct cpsw_priv *priv, u8 *enetaddr) +{ + struct cpsw_slave *slave; + int i, ret; + + /* soft reset the controller and initialize priv */ + setbit_and_wait_for_clear32(&priv->regs->soft_reset); + + /* initialize and reset the address lookup engine */ + cpsw_ale_enable(priv, 1); + cpsw_ale_clear(priv, 1); + cpsw_ale_vlan_aware(priv, 0); /* vlan unaware mode */ + + /* setup host port priority mapping */ + __raw_writel(0x76543210, &priv->host_port_regs->cpdma_tx_pri_map); + __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map); + + /* disable priority elevation and enable statistics on all ports */ + __raw_writel(0, &priv->regs->ptype); + + /* enable statistics collection only on the host port */ + __raw_writel(BIT(priv->host_port), &priv->regs->stat_port_en); + __raw_writel(0x7, &priv->regs->stat_port_en); + + cpsw_ale_port_state(priv, priv->host_port, ALE_PORT_STATE_FORWARD); + + cpsw_ale_add_ucast(priv, enetaddr, priv->host_port, ALE_SECURE); + cpsw_ale_add_mcast(priv, net_bcast_ethaddr, 1 << priv->host_port); + + for_active_slave(slave, priv) + cpsw_slave_init(slave, priv); + + cpsw_update_link(priv); + + /* init descriptor pool */ + for (i = 0; i < NUM_DESCS; i++) { + desc_write(&priv->descs[i], hw_next, + (i == (NUM_DESCS - 1)) ? 0 : &priv->descs[i+1]); + } + priv->desc_free = &priv->descs[0]; + + /* initialize channels */ + if (priv->data.version == CPSW_CTRL_VERSION_2) { + memset(&priv->rx_chan, 0, sizeof(struct cpdma_chan)); + priv->rx_chan.hdp = priv->dma_regs + CPDMA_RXHDP_VER2; + priv->rx_chan.cp = priv->dma_regs + CPDMA_RXCP_VER2; + priv->rx_chan.rxfree = priv->dma_regs + CPDMA_RXFREE; + + memset(&priv->tx_chan, 0, sizeof(struct cpdma_chan)); + priv->tx_chan.hdp = priv->dma_regs + CPDMA_TXHDP_VER2; + priv->tx_chan.cp = priv->dma_regs + CPDMA_TXCP_VER2; + } else { + memset(&priv->rx_chan, 0, sizeof(struct cpdma_chan)); + priv->rx_chan.hdp = priv->dma_regs + CPDMA_RXHDP_VER1; + priv->rx_chan.cp = priv->dma_regs + CPDMA_RXCP_VER1; + priv->rx_chan.rxfree = priv->dma_regs + CPDMA_RXFREE; + + memset(&priv->tx_chan, 0, sizeof(struct cpdma_chan)); + priv->tx_chan.hdp = priv->dma_regs + CPDMA_TXHDP_VER1; + priv->tx_chan.cp = priv->dma_regs + CPDMA_TXCP_VER1; + } + + /* clear dma state */ + setbit_and_wait_for_clear32(priv->dma_regs + CPDMA_SOFTRESET); + + if (priv->data.version == CPSW_CTRL_VERSION_2) { + for (i = 0; i < priv->data.channels; i++) { + __raw_writel(0, priv->dma_regs + CPDMA_RXHDP_VER2 + 4 + * i); + __raw_writel(0, priv->dma_regs + CPDMA_RXFREE + 4 + * i); + __raw_writel(0, priv->dma_regs + CPDMA_RXCP_VER2 + 4 + * i); + __raw_writel(0, priv->dma_regs + CPDMA_TXHDP_VER2 + 4 + * i); + __raw_writel(0, priv->dma_regs + CPDMA_TXCP_VER2 + 4 + * i); + } + } else { + for (i = 0; i < priv->data.channels; i++) { + __raw_writel(0, priv->dma_regs + CPDMA_RXHDP_VER1 + 4 + * i); + __raw_writel(0, priv->dma_regs + CPDMA_RXFREE + 4 + * i); + __raw_writel(0, priv->dma_regs + CPDMA_RXCP_VER1 + 4 + * i); + __raw_writel(0, priv->dma_regs + CPDMA_TXHDP_VER1 + 4 + * i); + __raw_writel(0, priv->dma_regs + CPDMA_TXCP_VER1 + 4 + * i); + + } + } + + __raw_writel(1, priv->dma_regs + CPDMA_TXCONTROL); + __raw_writel(1, priv->dma_regs + CPDMA_RXCONTROL); + + /* submit rx descs */ + for (i = 0; i < PKTBUFSRX; i++) { + ret = cpdma_submit(priv, &priv->rx_chan, net_rx_packets[i], + PKTSIZE); + if (ret < 0) { + printf("error %d submitting rx desc\n", ret); + break; + } + } + + return 0; +} + +static void _cpsw_halt(struct cpsw_priv *priv) +{ + writel(0, priv->dma_regs + CPDMA_TXCONTROL); + writel(0, priv->dma_regs + CPDMA_RXCONTROL); + + /* soft reset the controller and initialize priv */ + setbit_and_wait_for_clear32(&priv->regs->soft_reset); + + /* clear dma state */ + setbit_and_wait_for_clear32(priv->dma_regs + CPDMA_SOFTRESET); + +} + +static int _cpsw_send(struct cpsw_priv *priv, void *packet, int length) +{ + void *buffer; + int len; + int timeout = CPDMA_TIMEOUT; + + flush_dcache_range((unsigned long)packet, + (unsigned long)packet + length); + + /* first reap completed packets */ + while (timeout-- && + (cpdma_process(priv, &priv->tx_chan, &buffer, &len) >= 0)) + ; + + if (timeout == -1) { + printf("cpdma_process timeout\n"); + return -ETIMEDOUT; + } + + return cpdma_submit(priv, &priv->tx_chan, packet, length); +} + +static int _cpsw_recv(struct cpsw_priv *priv, uchar **pkt) +{ + void *buffer; + int len; + int ret = -EAGAIN; + + ret = cpdma_process(priv, &priv->rx_chan, &buffer, &len); + if (ret < 0) + return ret; + + invalidate_dcache_range((unsigned long)buffer, + (unsigned long)buffer + PKTSIZE_ALIGN); + *pkt = buffer; + + return len; +} + +static void cpsw_slave_setup(struct cpsw_slave *slave, int slave_num, + struct cpsw_priv *priv) +{ + void *regs = priv->regs; + struct cpsw_slave_data *data = priv->data.slave_data + slave_num; + slave->slave_num = slave_num; + slave->data = data; + slave->regs = regs + data->slave_reg_ofs; + slave->sliver = regs + data->sliver_reg_ofs; +} + +static int cpsw_phy_init(struct cpsw_priv *priv, struct cpsw_slave *slave) +{ + struct phy_device *phydev; + u32 supported = PHY_GBIT_FEATURES; + + phydev = phy_connect(priv->bus, + slave->data->phy_addr, + priv->dev, + slave->data->phy_if); + + if (!phydev) + return -1; + + phydev->supported &= supported; + phydev->advertising = phydev->supported; + + priv->phydev = phydev; + phy_config(phydev); + + return 1; +} + +int _cpsw_register(struct cpsw_priv *priv) +{ + struct cpsw_slave *slave; + struct cpsw_platform_data *data = &priv->data; + void *regs = (void *)data->cpsw_base; + + priv->slaves = malloc(sizeof(struct cpsw_slave) * data->slaves); + if (!priv->slaves) { + return -ENOMEM; + } + + priv->host_port = data->host_port_num; + priv->regs = regs; + priv->host_port_regs = regs + data->host_port_reg_ofs; + priv->dma_regs = regs + data->cpdma_reg_ofs; + priv->ale_regs = regs + data->ale_reg_ofs; + priv->descs = (void *)regs + data->bd_ram_ofs; + + int idx = 0; + + for_each_slave(slave, priv) { + cpsw_slave_setup(slave, idx, priv); + idx = idx + 1; + } + + cpsw_mdio_init(priv->dev->name, data->mdio_base, data->mdio_div); + priv->bus = miiphy_get_dev_by_name(priv->dev->name); + for_active_slave(slave, priv) + cpsw_phy_init(priv, slave); + + return 0; +} + +#ifndef CONFIG_DM_ETH +static int cpsw_init(struct eth_device *dev, bd_t *bis) +{ + struct cpsw_priv *priv = dev->priv; + + return _cpsw_init(priv, dev->enetaddr); +} + +static void cpsw_halt(struct eth_device *dev) +{ + struct cpsw_priv *priv = dev->priv; + + return _cpsw_halt(priv); +} + +static int cpsw_send(struct eth_device *dev, void *packet, int length) +{ + struct cpsw_priv *priv = dev->priv; + + return _cpsw_send(priv, packet, length); +} + +static int cpsw_recv(struct eth_device *dev) +{ + struct cpsw_priv *priv = dev->priv; + uchar *pkt = NULL; + int len; + + len = _cpsw_recv(priv, &pkt); + + if (len > 0) { + net_process_received_packet(pkt, len); + cpdma_submit(priv, &priv->rx_chan, pkt, PKTSIZE); + } + + return len; +} + +int cpsw_register(struct cpsw_platform_data *data) +{ + struct cpsw_priv *priv; + struct eth_device *dev; + int ret; + + dev = calloc(sizeof(*dev), 1); + if (!dev) + return -ENOMEM; + + priv = calloc(sizeof(*priv), 1); + if (!priv) { + free(dev); + return -ENOMEM; + } + + priv->dev = dev; + priv->data = *data; + + strcpy(dev->name, "cpsw"); + dev->iobase = 0; + dev->init = cpsw_init; + dev->halt = cpsw_halt; + dev->send = cpsw_send; + dev->recv = cpsw_recv; + dev->priv = priv; + + eth_register(dev); + + ret = _cpsw_register(priv); + if (ret < 0) { + eth_unregister(dev); + free(dev); + free(priv); + return ret; + } + + return 1; +} +#else +static int cpsw_eth_start(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + struct cpsw_priv *priv = dev_get_priv(dev); + + return _cpsw_init(priv, pdata->enetaddr); +} + +static int cpsw_eth_send(struct udevice *dev, void *packet, int length) +{ + struct cpsw_priv *priv = dev_get_priv(dev); + + return _cpsw_send(priv, packet, length); +} + +static int cpsw_eth_recv(struct udevice *dev, int flags, uchar **packetp) +{ + struct cpsw_priv *priv = dev_get_priv(dev); + + return _cpsw_recv(priv, packetp); +} + +static int cpsw_eth_free_pkt(struct udevice *dev, uchar *packet, + int length) +{ + struct cpsw_priv *priv = dev_get_priv(dev); + + return cpdma_submit(priv, &priv->rx_chan, packet, PKTSIZE); +} + +static void cpsw_eth_stop(struct udevice *dev) +{ + struct cpsw_priv *priv = dev_get_priv(dev); + + return _cpsw_halt(priv); +} + + +static int cpsw_eth_probe(struct udevice *dev) +{ + struct cpsw_priv *priv = dev_get_priv(dev); + + priv->dev = dev; + + return _cpsw_register(priv); +} + +static const struct eth_ops cpsw_eth_ops = { + .start = cpsw_eth_start, + .send = cpsw_eth_send, + .recv = cpsw_eth_recv, + .free_pkt = cpsw_eth_free_pkt, + .stop = cpsw_eth_stop, +}; + +static int cpsw_eth_ofdata_to_platdata(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + struct cpsw_priv *priv = dev_get_priv(dev); + const char *phy_mode; + const void *fdt = gd->fdt_blob; + int node = dev->of_offset; + int subnode; + int slave_index = 0; + uint32_t mac_hi, mac_lo; + fdt32_t gmii = 0; + int active_slave; + + pdata->iobase = dev_get_addr(dev); + priv->data.version = CPSW_CTRL_VERSION_2; + priv->data.bd_ram_ofs = CPSW_BD_OFFSET; + priv->data.ale_reg_ofs = CPSW_ALE_OFFSET; + priv->data.cpdma_reg_ofs = CPSW_CPDMA_OFFSET; + priv->data.mdio_div = CPSW_MDIO_DIV; + priv->data.host_port_reg_ofs = CPSW_HOST_PORT_OFFSET, + + pdata->phy_interface = -1; + + priv->data.cpsw_base = pdata->iobase; + priv->data.channels = fdtdec_get_int(fdt, node, "cpdma_channels", -1); + if (priv->data.channels <= 0) { + printf("error: cpdma_channels not found in dt\n"); + return -ENOENT; + } + + priv->data.slaves = fdtdec_get_int(fdt, node, "slaves", -1); + if (priv->data.slaves <= 0) { + printf("error: slaves not found in dt\n"); + return -ENOENT; + } + priv->data.slave_data = malloc(sizeof(struct cpsw_slave_data) * + priv->data.slaves); + + priv->data.ale_entries = fdtdec_get_int(fdt, node, "ale_entries", -1); + if (priv->data.ale_entries <= 0) { + printf("error: ale_entries not found in dt\n"); + return -ENOENT; + } + + priv->data.bd_ram_ofs = fdtdec_get_int(fdt, node, "bd_ram_size", -1); + if (priv->data.bd_ram_ofs <= 0) { + printf("error: bd_ram_size not found in dt\n"); + return -ENOENT; + } + + priv->data.mac_control = fdtdec_get_int(fdt, node, "mac_control", -1); + if (priv->data.mac_control <= 0) { + printf("error: ale_entries not found in dt\n"); + return -ENOENT; + } + + active_slave = fdtdec_get_int(fdt, node, "active_slave", 0); + priv->data.active_slave = active_slave; + + fdt_for_each_subnode(fdt, subnode, node) { + int len; + const char *name; + + name = fdt_get_name(fdt, subnode, &len); + if (!strncmp(name, "mdio", 4)) { + priv->data.mdio_base = fdtdec_get_addr(fdt, subnode, + "reg"); + } + + if (!strncmp(name, "slave", 5)) { + u32 phy_id[2]; + + if (slave_index >= priv->data.slaves) { + printf("error: num slaves and slave nodes did not match\n"); + return -EINVAL; + } + phy_mode = fdt_getprop(fdt, subnode, "phy-mode", NULL); + if (phy_mode) + priv->data.slave_data[slave_index].phy_if = + phy_get_interface_by_name(phy_mode); + fdtdec_get_int_array(fdt, subnode, "phy_id", phy_id, 2); + priv->data.slave_data[slave_index].phy_addr = phy_id[1]; + slave_index++; + } + + if (!strncmp(name, "cpsw-phy-sel", 12)) { + priv->data.gmii_sel = fdtdec_get_addr(fdt, subnode, + "reg"); + } + } + + priv->data.slave_data[0].slave_reg_ofs = CPSW_SLAVE0_OFFSET; + priv->data.slave_data[0].sliver_reg_ofs = CPSW_SLIVER0_OFFSET; + + if (priv->data.slaves == 2) { + priv->data.slave_data[1].slave_reg_ofs = CPSW_SLAVE1_OFFSET; + priv->data.slave_data[1].sliver_reg_ofs = CPSW_SLIVER1_OFFSET; + } + + subnode = fdtdec_lookup_phandle(fdt, node, "syscon"); + priv->data.mac_id = fdt_translate_address((void *)fdt, subnode, &gmii); + priv->data.mac_id += AM335X_GMII_SEL_OFFSET; + priv->data.mac_id += active_slave * 8; + + /* try reading mac address from efuse */ + mac_lo = readl(priv->data.mac_id); + mac_hi = readl(priv->data.mac_id + 4); + pdata->enetaddr[0] = mac_hi & 0xFF; + pdata->enetaddr[1] = (mac_hi & 0xFF00) >> 8; + pdata->enetaddr[2] = (mac_hi & 0xFF0000) >> 16; + pdata->enetaddr[3] = (mac_hi & 0xFF000000) >> 24; + pdata->enetaddr[4] = mac_lo & 0xFF; + pdata->enetaddr[5] = (mac_lo & 0xFF00) >> 8; + + pdata->phy_interface = priv->data.slave_data[active_slave].phy_if; + if (pdata->phy_interface == -1) { + debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); + return -EINVAL; + } + switch (pdata->phy_interface) { + case PHY_INTERFACE_MODE_MII: + writel(MII_MODE_ENABLE, priv->data.gmii_sel); + break; + case PHY_INTERFACE_MODE_RMII: + writel(RMII_MODE_ENABLE, priv->data.gmii_sel); + break; + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + writel(RGMII_MODE_ENABLE, priv->data.gmii_sel); + break; + } + return 0; +} + + +static const struct udevice_id cpsw_eth_ids[] = { + { .compatible = "ti,cpsw" }, + { .compatible = "ti,am335x-cpsw" }, + { } +}; + +U_BOOT_DRIVER(eth_cpsw) = { + .name = "eth_cpsw", + .id = UCLASS_ETH, + .of_match = cpsw_eth_ids, + .ofdata_to_platdata = cpsw_eth_ofdata_to_platdata, + .probe = cpsw_eth_probe, + .ops = &cpsw_eth_ops, + .priv_auto_alloc_size = sizeof(struct cpsw_priv), + .platdata_auto_alloc_size = sizeof(struct eth_pdata), + .flags = DM_FLAG_ALLOC_PRIV_DMA, +}; +#endif /* CONFIG_DM_ETH */ diff --git a/sources/uboot-be550/drivers/net/cs8900.c b/sources/uboot-be550/drivers/net/cs8900.c new file mode 100644 index 00000000..0713464c --- /dev/null +++ b/sources/uboot-be550/drivers/net/cs8900.c @@ -0,0 +1,319 @@ +/* + * Cirrus Logic CS8900A Ethernet + * + * (C) 2009 Ben Warren , biggerbadderben@gmail.com + * Converted to use CONFIG_NET_MULTI API + * + * (C) 2003 Wolfgang Denk, wd@denx.de + * Extension to synchronize ethaddr environment variable + * against value in EEPROM + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * Copyright (C) 1999 Ben Williamson + * + * This program is loaded into SRAM in bootstrap mode, where it waits + * for commands on UART1 to read and write memory, jump to code etc. + * A design goal for this program is to be entirely independent of the + * target board. Anything with a CL-PS7111 or EP7211 should be able to run + * this code in bootstrap mode. All the board specifics can be handled on + * the host. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include "cs8900.h" + +#undef DEBUG + +/* packet page register access functions */ + +#ifdef CONFIG_CS8900_BUS32 + +#define REG_WRITE(v, a) writel((v),(a)) +#define REG_READ(a) readl((a)) + +/* we don't need 16 bit initialisation on 32 bit bus */ +#define get_reg_init_bus(r,d) get_reg((r),(d)) + +#else + +#define REG_WRITE(v, a) writew((v),(a)) +#define REG_READ(a) readw((a)) + +static u16 get_reg_init_bus(struct eth_device *dev, int regno) +{ + /* force 16 bit busmode */ + struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv); + uint8_t volatile * const iob = (uint8_t volatile * const)dev->iobase; + + readb(iob); + readb(iob + 1); + readb(iob); + readb(iob + 1); + readb(iob); + + REG_WRITE(regno, &priv->regs->pptr); + return REG_READ(&priv->regs->pdata); +} +#endif + +static u16 get_reg(struct eth_device *dev, int regno) +{ + struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv); + REG_WRITE(regno, &priv->regs->pptr); + return REG_READ(&priv->regs->pdata); +} + + +static void put_reg(struct eth_device *dev, int regno, u16 val) +{ + struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv); + REG_WRITE(regno, &priv->regs->pptr); + REG_WRITE(val, &priv->regs->pdata); +} + +static void cs8900_reset(struct eth_device *dev) +{ + int tmo; + u16 us; + + /* reset NIC */ + put_reg(dev, PP_SelfCTL, get_reg(dev, PP_SelfCTL) | PP_SelfCTL_Reset); + + /* wait for 200ms */ + udelay(200000); + /* Wait until the chip is reset */ + + tmo = get_timer(0) + 1 * CONFIG_SYS_HZ; + while ((((us = get_reg_init_bus(dev, PP_SelfSTAT)) & + PP_SelfSTAT_InitD) == 0) && tmo < get_timer(0)) + /*NOP*/; +} + +static void cs8900_reginit(struct eth_device *dev) +{ + /* receive only error free packets addressed to this card */ + put_reg(dev, PP_RxCTL, + PP_RxCTL_IA | PP_RxCTL_Broadcast | PP_RxCTL_RxOK); + /* do not generate any interrupts on receive operations */ + put_reg(dev, PP_RxCFG, 0); + /* do not generate any interrupts on transmit operations */ + put_reg(dev, PP_TxCFG, 0); + /* do not generate any interrupts on buffer operations */ + put_reg(dev, PP_BufCFG, 0); + /* enable transmitter/receiver mode */ + put_reg(dev, PP_LineCTL, PP_LineCTL_Rx | PP_LineCTL_Tx); +} + +void cs8900_get_enetaddr(struct eth_device *dev) +{ + int i; + + /* verify chip id */ + if (get_reg_init_bus(dev, PP_ChipID) != 0x630e) + return; + cs8900_reset(dev); + if ((get_reg(dev, PP_SelfSTAT) & + (PP_SelfSTAT_EEPROM | PP_SelfSTAT_EEPROM_OK)) == + (PP_SelfSTAT_EEPROM | PP_SelfSTAT_EEPROM_OK)) { + + /* Load the MAC from EEPROM */ + for (i = 0; i < 3; i++) { + u32 Addr; + + Addr = get_reg(dev, PP_IA + i * 2); + dev->enetaddr[i * 2] = Addr & 0xFF; + dev->enetaddr[i * 2 + 1] = Addr >> 8; + } + } +} + +void cs8900_halt(struct eth_device *dev) +{ + /* disable transmitter/receiver mode */ + put_reg(dev, PP_LineCTL, 0); + + /* "shutdown" to show ChipID or kernel wouldn't find he cs8900 ... */ + get_reg_init_bus(dev, PP_ChipID); +} + +static int cs8900_init(struct eth_device *dev, bd_t * bd) +{ + uchar *enetaddr = dev->enetaddr; + u16 id; + + /* verify chip id */ + id = get_reg_init_bus(dev, PP_ChipID); + if (id != 0x630e) { + printf ("CS8900 Ethernet chip not found: " + "ID=0x%04x instead 0x%04x\n", id, 0x630e); + return 1; + } + + cs8900_reset (dev); + /* set the ethernet address */ + put_reg(dev, PP_IA + 0, enetaddr[0] | (enetaddr[1] << 8)); + put_reg(dev, PP_IA + 2, enetaddr[2] | (enetaddr[3] << 8)); + put_reg(dev, PP_IA + 4, enetaddr[4] | (enetaddr[5] << 8)); + + cs8900_reginit(dev); + return 0; +} + +/* Get a data block via Ethernet */ +static int cs8900_recv(struct eth_device *dev) +{ + int i; + u16 rxlen; + u16 *addr; + u16 status; + + struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv); + + status = get_reg(dev, PP_RER); + + if ((status & PP_RER_RxOK) == 0) + return 0; + + status = REG_READ(&priv->regs->rtdata); + rxlen = REG_READ(&priv->regs->rtdata); + + if (rxlen > PKTSIZE_ALIGN + PKTALIGN) + debug("packet too big!\n"); + for (addr = (u16 *)net_rx_packets[0], i = rxlen >> 1; i > 0; i--) + *addr++ = REG_READ(&priv->regs->rtdata); + if (rxlen & 1) + *addr++ = REG_READ(&priv->regs->rtdata); + + /* Pass the packet up to the protocol layers. */ + net_process_received_packet(net_rx_packets[0], rxlen); + return rxlen; +} + +/* Send a data block via Ethernet. */ +static int cs8900_send(struct eth_device *dev, void *packet, int length) +{ + volatile u16 *addr; + int tmo; + u16 s; + struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv); + +retry: + /* initiate a transmit sequence */ + REG_WRITE(PP_TxCmd_TxStart_Full, &priv->regs->txcmd); + REG_WRITE(length, &priv->regs->txlen); + + /* Test to see if the chip has allocated memory for the packet */ + if ((get_reg(dev, PP_BusSTAT) & PP_BusSTAT_TxRDY) == 0) { + /* Oops... this should not happen! */ + debug("cs: unable to send packet; retrying...\n"); + for (tmo = get_timer(0) + 5 * CONFIG_SYS_HZ; + get_timer(0) < tmo;) + /*NOP*/; + cs8900_reset(dev); + cs8900_reginit(dev); + goto retry; + } + + /* Write the contents of the packet */ + /* assume even number of bytes */ + for (addr = packet; length > 0; length -= 2) + REG_WRITE(*addr++, &priv->regs->rtdata); + + /* wait for transfer to succeed */ + tmo = get_timer(0) + 5 * CONFIG_SYS_HZ; + while ((s = get_reg(dev, PP_TER) & ~0x1F) == 0) { + if (get_timer(0) >= tmo) + break; + } + + /* nothing */ ; + if((s & (PP_TER_CRS | PP_TER_TxOK)) != PP_TER_TxOK) { + debug("\ntransmission error %#x\n", s); + } + + return 0; +} + +static void cs8900_e2prom_ready(struct eth_device *dev) +{ + while (get_reg(dev, PP_SelfSTAT) & SI_BUSY) + ; +} + +/***********************************************************/ +/* read a 16-bit word out of the EEPROM */ +/***********************************************************/ + +int cs8900_e2prom_read(struct eth_device *dev, + u8 addr, u16 *value) +{ + cs8900_e2prom_ready(dev); + put_reg(dev, PP_EECMD, EEPROM_READ_CMD | addr); + cs8900_e2prom_ready(dev); + *value = get_reg(dev, PP_EEData); + + return 0; +} + + +/***********************************************************/ +/* write a 16-bit word into the EEPROM */ +/***********************************************************/ + +int cs8900_e2prom_write(struct eth_device *dev, u8 addr, u16 value) +{ + cs8900_e2prom_ready(dev); + put_reg(dev, PP_EECMD, EEPROM_WRITE_EN); + cs8900_e2prom_ready(dev); + put_reg(dev, PP_EEData, value); + put_reg(dev, PP_EECMD, EEPROM_WRITE_CMD | addr); + cs8900_e2prom_ready(dev); + put_reg(dev, PP_EECMD, EEPROM_WRITE_DIS); + cs8900_e2prom_ready(dev); + + return 0; +} + +int cs8900_initialize(u8 dev_num, int base_addr) +{ + struct eth_device *dev; + struct cs8900_priv *priv; + + dev = malloc(sizeof(*dev)); + if (!dev) { + return 0; + } + memset(dev, 0, sizeof(*dev)); + + priv = malloc(sizeof(*priv)); + if (!priv) { + free(dev); + return 0; + } + memset(priv, 0, sizeof(*priv)); + priv->regs = (struct cs8900_regs *)base_addr; + + dev->iobase = base_addr; + dev->priv = priv; + dev->init = cs8900_init; + dev->halt = cs8900_halt; + dev->send = cs8900_send; + dev->recv = cs8900_recv; + + /* Load MAC address from EEPROM */ + cs8900_get_enetaddr(dev); + + sprintf(dev->name, "%s-%hu", CS8900_DRIVERNAME, dev_num); + + eth_register(dev); + return 0; +} diff --git a/sources/uboot-be550/drivers/net/cs8900.h b/sources/uboot-be550/drivers/net/cs8900.h new file mode 100644 index 00000000..79877dd5 --- /dev/null +++ b/sources/uboot-be550/drivers/net/cs8900.h @@ -0,0 +1,249 @@ +#ifndef CS8900_H +#define CS8900_H +/* + * Cirrus Logic CS8900A Ethernet + * + * (C) 2009 Ben Warren , biggerbadderben@gmail.com + * Converted to use CONFIG_NET_MULTI API + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * Copyright (C) 1999 Ben Williamson + * + * This program is loaded into SRAM in bootstrap mode, where it waits + * for commands on UART1 to read and write memory, jump to code etc. + * A design goal for this program is to be entirely independent of the + * target board. Anything with a CL-PS7111 or EP7211 should be able to run + * this code in bootstrap mode. All the board specifics can be handled on + * the host. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +#define CS8900_DRIVERNAME "CS8900" +/* although the registers are 16 bit, they are 32-bit aligned on the + EDB7111. so we have to read them as 32-bit registers and ignore the + upper 16-bits. i'm not sure if this holds for the EDB7211. */ + +#ifdef CONFIG_CS8900_BUS16 + /* 16 bit aligned registers, 16 bit wide */ + #define CS8900_REG u16 +#elif defined(CONFIG_CS8900_BUS32) + /* 32 bit aligned registers, 16 bit wide (we ignore upper 16 bits) */ + #define CS8900_REG u32 +#else + #error unknown bussize ... +#endif + +struct cs8900_regs { + CS8900_REG rtdata; + CS8900_REG pad0; + CS8900_REG txcmd; + CS8900_REG txlen; + CS8900_REG isq; + CS8900_REG pptr; + CS8900_REG pdata; +}; + +struct cs8900_priv { + struct cs8900_regs *regs; +}; + +#define ISQ_RxEvent 0x04 +#define ISQ_TxEvent 0x08 +#define ISQ_BufEvent 0x0C +#define ISQ_RxMissEvent 0x10 +#define ISQ_TxColEvent 0x12 +#define ISQ_EventMask 0x3F + +/* packet page register offsets */ + +/* bus interface registers */ +#define PP_ChipID 0x0000 /* Chip identifier - must be 0x630E */ +#define PP_ChipRev 0x0002 /* Chip revision, model codes */ + +#define PP_IntReg 0x0022 /* Interrupt configuration */ +#define PP_IntReg_IRQ0 0x0000 /* Use INTR0 pin */ +#define PP_IntReg_IRQ1 0x0001 /* Use INTR1 pin */ +#define PP_IntReg_IRQ2 0x0002 /* Use INTR2 pin */ +#define PP_IntReg_IRQ3 0x0003 /* Use INTR3 pin */ + +/* status and control registers */ + +#define PP_RxCFG 0x0102 /* Receiver configuration */ +#define PP_RxCFG_Skip1 0x0040 /* Skip (i.e. discard) current frame */ +#define PP_RxCFG_Stream 0x0080 /* Enable streaming mode */ +#define PP_RxCFG_RxOK 0x0100 /* RxOK interrupt enable */ +#define PP_RxCFG_RxDMAonly 0x0200 /* Use RxDMA for all frames */ +#define PP_RxCFG_AutoRxDMA 0x0400 /* Select RxDMA automatically */ +#define PP_RxCFG_BufferCRC 0x0800 /* Include CRC characters in frame */ +#define PP_RxCFG_CRC 0x1000 /* Enable interrupt on CRC error */ +#define PP_RxCFG_RUNT 0x2000 /* Enable interrupt on RUNT frames */ +#define PP_RxCFG_EXTRA 0x4000 /* Enable interrupt on frames with extra data */ + +#define PP_RxCTL 0x0104 /* Receiver control */ +#define PP_RxCTL_IAHash 0x0040 /* Accept frames that match hash */ +#define PP_RxCTL_Promiscuous 0x0080 /* Accept any frame */ +#define PP_RxCTL_RxOK 0x0100 /* Accept well formed frames */ +#define PP_RxCTL_Multicast 0x0200 /* Accept multicast frames */ +#define PP_RxCTL_IA 0x0400 /* Accept frame that matches IA */ +#define PP_RxCTL_Broadcast 0x0800 /* Accept broadcast frames */ +#define PP_RxCTL_CRC 0x1000 /* Accept frames with bad CRC */ +#define PP_RxCTL_RUNT 0x2000 /* Accept runt frames */ +#define PP_RxCTL_EXTRA 0x4000 /* Accept frames that are too long */ + +#define PP_TxCFG 0x0106 /* Transmit configuration */ +#define PP_TxCFG_CRS 0x0040 /* Enable interrupt on loss of carrier */ +#define PP_TxCFG_SQE 0x0080 /* Enable interrupt on Signal Quality Error */ +#define PP_TxCFG_TxOK 0x0100 /* Enable interrupt on successful xmits */ +#define PP_TxCFG_Late 0x0200 /* Enable interrupt on "out of window" */ +#define PP_TxCFG_Jabber 0x0400 /* Enable interrupt on jabber detect */ +#define PP_TxCFG_Collision 0x0800 /* Enable interrupt if collision */ +#define PP_TxCFG_16Collisions 0x8000 /* Enable interrupt if > 16 collisions */ + +#define PP_TxCmd 0x0108 /* Transmit command status */ +#define PP_TxCmd_TxStart_5 0x0000 /* Start after 5 bytes in buffer */ +#define PP_TxCmd_TxStart_381 0x0040 /* Start after 381 bytes in buffer */ +#define PP_TxCmd_TxStart_1021 0x0080 /* Start after 1021 bytes in buffer */ +#define PP_TxCmd_TxStart_Full 0x00C0 /* Start after all bytes loaded */ +#define PP_TxCmd_Force 0x0100 /* Discard any pending packets */ +#define PP_TxCmd_OneCollision 0x0200 /* Abort after a single collision */ +#define PP_TxCmd_NoCRC 0x1000 /* Do not add CRC */ +#define PP_TxCmd_NoPad 0x2000 /* Do not pad short packets */ + +#define PP_BufCFG 0x010A /* Buffer configuration */ +#define PP_BufCFG_SWI 0x0040 /* Force interrupt via software */ +#define PP_BufCFG_RxDMA 0x0080 /* Enable interrupt on Rx DMA */ +#define PP_BufCFG_TxRDY 0x0100 /* Enable interrupt when ready for Tx */ +#define PP_BufCFG_TxUE 0x0200 /* Enable interrupt in Tx underrun */ +#define PP_BufCFG_RxMiss 0x0400 /* Enable interrupt on missed Rx packets */ +#define PP_BufCFG_Rx128 0x0800 /* Enable Rx interrupt after 128 bytes */ +#define PP_BufCFG_TxCol 0x1000 /* Enable int on Tx collision ctr overflow */ +#define PP_BufCFG_Miss 0x2000 /* Enable int on Rx miss ctr overflow */ +#define PP_BufCFG_RxDest 0x8000 /* Enable int on Rx dest addr match */ + +#define PP_LineCTL 0x0112 /* Line control */ +#define PP_LineCTL_Rx 0x0040 /* Enable receiver */ +#define PP_LineCTL_Tx 0x0080 /* Enable transmitter */ +#define PP_LineCTL_AUIonly 0x0100 /* AUI interface only */ +#define PP_LineCTL_AutoAUI10BT 0x0200 /* Autodetect AUI or 10BaseT interface */ +#define PP_LineCTL_ModBackoffE 0x0800 /* Enable modified backoff algorithm */ +#define PP_LineCTL_PolarityDis 0x1000 /* Disable Rx polarity autodetect */ +#define PP_LineCTL_2partDefDis 0x2000 /* Disable two-part defferal */ +#define PP_LineCTL_LoRxSquelch 0x4000 /* Reduce receiver squelch threshold */ + +#define PP_SelfCTL 0x0114 /* Chip self control */ +#define PP_SelfCTL_Reset 0x0040 /* Self-clearing reset */ +#define PP_SelfCTL_SWSuspend 0x0100 /* Initiate suspend mode */ +#define PP_SelfCTL_HWSleepE 0x0200 /* Enable SLEEP input */ +#define PP_SelfCTL_HWStandbyE 0x0400 /* Enable standby mode */ +#define PP_SelfCTL_HC0E 0x1000 /* use HCB0 for LINK LED */ +#define PP_SelfCTL_HC1E 0x2000 /* use HCB1 for BSTATUS LED */ +#define PP_SelfCTL_HCB0 0x4000 /* control LINK LED if HC0E set */ +#define PP_SelfCTL_HCB1 0x8000 /* control BSTATUS LED if HC1E set */ + +#define PP_BusCTL 0x0116 /* Bus control */ +#define PP_BusCTL_ResetRxDMA 0x0040 /* Reset RxDMA pointer */ +#define PP_BusCTL_DMAextend 0x0100 /* Extend DMA cycle */ +#define PP_BusCTL_UseSA 0x0200 /* Assert MEMCS16 on address decode */ +#define PP_BusCTL_MemoryE 0x0400 /* Enable memory mode */ +#define PP_BusCTL_DMAburst 0x0800 /* Limit DMA access burst */ +#define PP_BusCTL_IOCHRDYE 0x1000 /* Set IOCHRDY high impedence */ +#define PP_BusCTL_RxDMAsize 0x2000 /* Set DMA buffer size 64KB */ +#define PP_BusCTL_EnableIRQ 0x8000 /* Generate interrupt on interrupt event */ + +#define PP_TestCTL 0x0118 /* Test control */ +#define PP_TestCTL_DisableLT 0x0080 /* Disable link status */ +#define PP_TestCTL_ENDECloop 0x0200 /* Internal loopback */ +#define PP_TestCTL_AUIloop 0x0400 /* AUI loopback */ +#define PP_TestCTL_DisBackoff 0x0800 /* Disable backoff algorithm */ +#define PP_TestCTL_FDX 0x4000 /* Enable full duplex mode */ + +#define PP_ISQ 0x0120 /* Interrupt Status Queue */ + +#define PP_RER 0x0124 /* Receive event */ +#define PP_RER_IAHash 0x0040 /* Frame hash match */ +#define PP_RER_Dribble 0x0080 /* Frame had 1-7 extra bits after last byte */ +#define PP_RER_RxOK 0x0100 /* Frame received with no errors */ +#define PP_RER_Hashed 0x0200 /* Frame address hashed OK */ +#define PP_RER_IA 0x0400 /* Frame address matched IA */ +#define PP_RER_Broadcast 0x0800 /* Broadcast frame */ +#define PP_RER_CRC 0x1000 /* Frame had CRC error */ +#define PP_RER_RUNT 0x2000 /* Runt frame */ +#define PP_RER_EXTRA 0x4000 /* Frame was too long */ + +#define PP_TER 0x0128 /* Transmit event */ +#define PP_TER_CRS 0x0040 /* Carrier lost */ +#define PP_TER_SQE 0x0080 /* Signal Quality Error */ +#define PP_TER_TxOK 0x0100 /* Packet sent without error */ +#define PP_TER_Late 0x0200 /* Out of window */ +#define PP_TER_Jabber 0x0400 /* Stuck transmit? */ +#define PP_TER_NumCollisions 0x7800 /* Number of collisions */ +#define PP_TER_16Collisions 0x8000 /* > 16 collisions */ + +#define PP_BER 0x012C /* Buffer event */ +#define PP_BER_SWint 0x0040 /* Software interrupt */ +#define PP_BER_RxDMAFrame 0x0080 /* Received framed DMAed */ +#define PP_BER_Rdy4Tx 0x0100 /* Ready for transmission */ +#define PP_BER_TxUnderrun 0x0200 /* Transmit underrun */ +#define PP_BER_RxMiss 0x0400 /* Received frame missed */ +#define PP_BER_Rx128 0x0800 /* 128 bytes received */ +#define PP_BER_RxDest 0x8000 /* Received framed passed address filter */ + +#define PP_RxMiss 0x0130 /* Receiver miss counter */ + +#define PP_TxCol 0x0132 /* Transmit collision counter */ + +#define PP_LineSTAT 0x0134 /* Line status */ +#define PP_LineSTAT_LinkOK 0x0080 /* Line is connected and working */ +#define PP_LineSTAT_AUI 0x0100 /* Connected via AUI */ +#define PP_LineSTAT_10BT 0x0200 /* Connected via twisted pair */ +#define PP_LineSTAT_Polarity 0x1000 /* Line polarity OK (10BT only) */ +#define PP_LineSTAT_CRS 0x4000 /* Frame being received */ + +#define PP_SelfSTAT 0x0136 /* Chip self status */ +#define PP_SelfSTAT_33VActive 0x0040 /* supply voltage is 3.3V */ +#define PP_SelfSTAT_InitD 0x0080 /* Chip initialization complete */ +#define PP_SelfSTAT_SIBSY 0x0100 /* EEPROM is busy */ +#define PP_SelfSTAT_EEPROM 0x0200 /* EEPROM present */ +#define PP_SelfSTAT_EEPROM_OK 0x0400 /* EEPROM checks out */ +#define PP_SelfSTAT_ELPresent 0x0800 /* External address latch logic available */ +#define PP_SelfSTAT_EEsize 0x1000 /* Size of EEPROM */ + +#define PP_BusSTAT 0x0138 /* Bus status */ +#define PP_BusSTAT_TxBid 0x0080 /* Tx error */ +#define PP_BusSTAT_TxRDY 0x0100 /* Ready for Tx data */ + +#define PP_TDR 0x013C /* AUI Time Domain Reflectometer */ + +/* initiate transmit registers */ + +#define PP_TxCommand 0x0144 /* Tx Command */ +#define PP_TxLength 0x0146 /* Tx Length */ + + +/* address filter registers */ + +#define PP_LAF 0x0150 /* Logical address filter (6 bytes) */ +#define PP_IA 0x0158 /* Individual address (MAC) */ + +/* EEPROM Kram */ +#define SI_BUSY 0x0100 +#define PP_EECMD 0x0040 /* NVR Interface Command register */ +#define PP_EEData 0x0042 /* NVR Interface Data Register */ +#define EEPROM_WRITE_EN 0x00F0 +#define EEPROM_WRITE_DIS 0x0000 +#define EEPROM_WRITE_CMD 0x0100 +#define EEPROM_READ_CMD 0x0200 +#define EEPROM_ERASE_CMD 0x0300 + +/* Exported functions */ +int cs8900_e2prom_read(struct eth_device *dev, uchar, ushort *); +int cs8900_e2prom_write(struct eth_device *dev, uchar, ushort); + +#endif /* CS8900_H */ diff --git a/sources/uboot-be550/drivers/net/davinci_emac.c b/sources/uboot-be550/drivers/net/davinci_emac.c new file mode 100644 index 00000000..04447953 --- /dev/null +++ b/sources/uboot-be550/drivers/net/davinci_emac.c @@ -0,0 +1,897 @@ +/* + * Ethernet driver for TI TMS320DM644x (DaVinci) chips. + * + * Copyright (C) 2007 Sergey Kubushyn + * + * Parts shamelessly stolen from TI's dm644x_emac.c. Original copyright + * follows: + * + * ---------------------------------------------------------------------------- + * + * dm644x_emac.c + * + * TI DaVinci (DM644X) EMAC peripheral driver source for DV-EVM + * + * Copyright (C) 2005 Texas Instruments. + * + * ---------------------------------------------------------------------------- + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Modifications: + * ver. 1.0: Sep 2005, Anant Gole - Created EMAC version for uBoot. + * ver 1.1: Nov 2005, Anant Gole - Extended the RX logic for multiple descriptors + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "davinci_emac.h" + +unsigned int emac_dbg = 0; +#define debug_emac(fmt,args...) if (emac_dbg) printf(fmt,##args) + +#ifdef EMAC_HW_RAM_ADDR +static inline unsigned long BD_TO_HW(unsigned long x) +{ + if (x == 0) + return 0; + + return x - EMAC_WRAPPER_RAM_ADDR + EMAC_HW_RAM_ADDR; +} + +static inline unsigned long HW_TO_BD(unsigned long x) +{ + if (x == 0) + return 0; + + return x - EMAC_HW_RAM_ADDR + EMAC_WRAPPER_RAM_ADDR; +} +#else +#define BD_TO_HW(x) (x) +#define HW_TO_BD(x) (x) +#endif + +#ifdef DAVINCI_EMAC_GIG_ENABLE +#define emac_gigabit_enable(phy_addr) davinci_eth_gigabit_enable(phy_addr) +#else +#define emac_gigabit_enable(phy_addr) /* no gigabit to enable */ +#endif + +#if !defined(CONFIG_SYS_EMAC_TI_CLKDIV) +#define CONFIG_SYS_EMAC_TI_CLKDIV ((EMAC_MDIO_BUS_FREQ / \ + EMAC_MDIO_CLOCK_FREQ) - 1) +#endif + +static void davinci_eth_mdio_enable(void); + +static int gen_init_phy(int phy_addr); +static int gen_is_phy_connected(int phy_addr); +static int gen_get_link_speed(int phy_addr); +static int gen_auto_negotiate(int phy_addr); + +void eth_mdio_enable(void) +{ + davinci_eth_mdio_enable(); +} + +/* EMAC Addresses */ +static volatile emac_regs *adap_emac = (emac_regs *)EMAC_BASE_ADDR; +static volatile ewrap_regs *adap_ewrap = (ewrap_regs *)EMAC_WRAPPER_BASE_ADDR; +static volatile mdio_regs *adap_mdio = (mdio_regs *)EMAC_MDIO_BASE_ADDR; + +/* EMAC descriptors */ +static volatile emac_desc *emac_rx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_RX_DESC_BASE); +static volatile emac_desc *emac_tx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_TX_DESC_BASE); +static volatile emac_desc *emac_rx_active_head = 0; +static volatile emac_desc *emac_rx_active_tail = 0; +static int emac_rx_queue_active = 0; + +/* Receive packet buffers */ +static unsigned char emac_rx_buffers[EMAC_MAX_RX_BUFFERS * EMAC_RXBUF_SIZE] + __aligned(ARCH_DMA_MINALIGN); + +#ifndef CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT +#define CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT 3 +#endif + +/* PHY address for a discovered PHY (0xff - not found) */ +static u_int8_t active_phy_addr[CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT]; + +/* number of PHY found active */ +static u_int8_t num_phy; + +phy_t phy[CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT]; + +static inline void davinci_flush_rx_descs(void) +{ + /* flush the whole RX descs area */ + flush_dcache_range(EMAC_WRAPPER_RAM_ADDR + EMAC_RX_DESC_BASE, + EMAC_WRAPPER_RAM_ADDR + EMAC_TX_DESC_BASE); +} + +static inline void davinci_invalidate_rx_descs(void) +{ + /* invalidate the whole RX descs area */ + invalidate_dcache_range(EMAC_WRAPPER_RAM_ADDR + EMAC_RX_DESC_BASE, + EMAC_WRAPPER_RAM_ADDR + EMAC_TX_DESC_BASE); +} + +static inline void davinci_flush_desc(emac_desc *desc) +{ + flush_dcache_range((unsigned long)desc, + (unsigned long)desc + sizeof(*desc)); +} + +static int davinci_eth_set_mac_addr(struct eth_device *dev) +{ + unsigned long mac_hi; + unsigned long mac_lo; + + /* + * Set MAC Addresses & Init multicast Hash to 0 (disable any multicast + * receive) + * Using channel 0 only - other channels are disabled + * */ + writel(0, &adap_emac->MACINDEX); + mac_hi = (dev->enetaddr[3] << 24) | + (dev->enetaddr[2] << 16) | + (dev->enetaddr[1] << 8) | + (dev->enetaddr[0]); + mac_lo = (dev->enetaddr[5] << 8) | + (dev->enetaddr[4]); + + writel(mac_hi, &adap_emac->MACADDRHI); +#if defined(DAVINCI_EMAC_VERSION2) + writel(mac_lo | EMAC_MAC_ADDR_IS_VALID | EMAC_MAC_ADDR_MATCH, + &adap_emac->MACADDRLO); +#else + writel(mac_lo, &adap_emac->MACADDRLO); +#endif + + writel(0, &adap_emac->MACHASH1); + writel(0, &adap_emac->MACHASH2); + + /* Set source MAC address - REQUIRED */ + writel(mac_hi, &adap_emac->MACSRCADDRHI); + writel(mac_lo, &adap_emac->MACSRCADDRLO); + + + return 0; +} + +static void davinci_eth_mdio_enable(void) +{ + u_int32_t clkdiv; + + clkdiv = CONFIG_SYS_EMAC_TI_CLKDIV; + + writel((clkdiv & 0xff) | + MDIO_CONTROL_ENABLE | + MDIO_CONTROL_FAULT | + MDIO_CONTROL_FAULT_ENABLE, + &adap_mdio->CONTROL); + + while (readl(&adap_mdio->CONTROL) & MDIO_CONTROL_IDLE) + ; +} + +/* + * Tries to find an active connected PHY. Returns 1 if address if found. + * If no active PHY (or more than one PHY) found returns 0. + * Sets active_phy_addr variable. + */ +static int davinci_eth_phy_detect(void) +{ + u_int32_t phy_act_state; + int i; + int j; + unsigned int count = 0; + + for (i = 0; i < CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT; i++) + active_phy_addr[i] = 0xff; + + udelay(1000); + phy_act_state = readl(&adap_mdio->ALIVE); + + if (phy_act_state == 0) + return 0; /* No active PHYs */ + + debug_emac("davinci_eth_phy_detect(), ALIVE = 0x%08x\n", phy_act_state); + + for (i = 0, j = 0; i < 32; i++) + if (phy_act_state & (1 << i)) { + count++; + if (count <= CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT) { + active_phy_addr[j++] = i; + } else { + printf("%s: to many PHYs detected.\n", + __func__); + count = 0; + break; + } + } + + num_phy = count; + + return count; +} + + +/* Read a PHY register via MDIO inteface. Returns 1 on success, 0 otherwise */ +int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data) +{ + int tmp; + + while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO) + ; + + writel(MDIO_USERACCESS0_GO | + MDIO_USERACCESS0_WRITE_READ | + ((reg_num & 0x1f) << 21) | + ((phy_addr & 0x1f) << 16), + &adap_mdio->USERACCESS0); + + /* Wait for command to complete */ + while ((tmp = readl(&adap_mdio->USERACCESS0)) & MDIO_USERACCESS0_GO) + ; + + if (tmp & MDIO_USERACCESS0_ACK) { + *data = tmp & 0xffff; + return(1); + } + + *data = -1; + return(0); +} + +/* Write to a PHY register via MDIO inteface. Blocks until operation is complete. */ +int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data) +{ + + while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO) + ; + + writel(MDIO_USERACCESS0_GO | + MDIO_USERACCESS0_WRITE_WRITE | + ((reg_num & 0x1f) << 21) | + ((phy_addr & 0x1f) << 16) | + (data & 0xffff), + &adap_mdio->USERACCESS0); + + /* Wait for command to complete */ + while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO) + ; + + return(1); +} + +/* PHY functions for a generic PHY */ +static int gen_init_phy(int phy_addr) +{ + int ret = 1; + + if (gen_get_link_speed(phy_addr)) { + /* Try another time */ + ret = gen_get_link_speed(phy_addr); + } + + return(ret); +} + +static int gen_is_phy_connected(int phy_addr) +{ + u_int16_t dummy; + + return davinci_eth_phy_read(phy_addr, MII_PHYSID1, &dummy); +} + +static int get_active_phy(void) +{ + int i; + + for (i = 0; i < num_phy; i++) + if (phy[i].get_link_speed(active_phy_addr[i])) + return i; + + return -1; /* Return error if no link */ +} + +static int gen_get_link_speed(int phy_addr) +{ + u_int16_t tmp; + + if (davinci_eth_phy_read(phy_addr, MII_STATUS_REG, &tmp) && + (tmp & 0x04)) { +#if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \ + defined(CONFIG_MACH_DAVINCI_DA850_EVM) + davinci_eth_phy_read(phy_addr, MII_LPA, &tmp); + + /* Speed doesn't matter, there is no setting for it in EMAC. */ + if (tmp & (LPA_100FULL | LPA_10FULL)) { + /* set EMAC for Full Duplex */ + writel(EMAC_MACCONTROL_MIIEN_ENABLE | + EMAC_MACCONTROL_FULLDUPLEX_ENABLE, + &adap_emac->MACCONTROL); + } else { + /*set EMAC for Half Duplex */ + writel(EMAC_MACCONTROL_MIIEN_ENABLE, + &adap_emac->MACCONTROL); + } + + if (tmp & (LPA_100FULL | LPA_100HALF)) + writel(readl(&adap_emac->MACCONTROL) | + EMAC_MACCONTROL_RMIISPEED_100, + &adap_emac->MACCONTROL); + else + writel(readl(&adap_emac->MACCONTROL) & + ~EMAC_MACCONTROL_RMIISPEED_100, + &adap_emac->MACCONTROL); +#endif + return(1); + } + + return(0); +} + +static int gen_auto_negotiate(int phy_addr) +{ + u_int16_t tmp; + u_int16_t val; + unsigned long cntr = 0; + + if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp)) + return 0; + + val = tmp | BMCR_FULLDPLX | BMCR_ANENABLE | + BMCR_SPEED100; + davinci_eth_phy_write(phy_addr, MII_BMCR, val); + + if (!davinci_eth_phy_read(phy_addr, MII_ADVERTISE, &val)) + return 0; + + val |= (ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL | + ADVERTISE_10HALF); + davinci_eth_phy_write(phy_addr, MII_ADVERTISE, val); + + if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp)) + return(0); + + /* Restart Auto_negotiation */ + tmp |= BMCR_ANRESTART; + davinci_eth_phy_write(phy_addr, MII_BMCR, tmp); + + /*check AutoNegotiate complete */ + do { + udelay(40000); + if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp)) + return 0; + + if (tmp & BMSR_ANEGCOMPLETE) + break; + + cntr++; + } while (cntr < 200); + + if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp)) + return(0); + + if (!(tmp & BMSR_ANEGCOMPLETE)) + return(0); + + return(gen_get_link_speed(phy_addr)); +} +/* End of generic PHY functions */ + + +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) +static int davinci_mii_phy_read(const char *devname, unsigned char addr, unsigned char reg, unsigned short *value) +{ + return(davinci_eth_phy_read(addr, reg, value) ? 0 : 1); +} + +static int davinci_mii_phy_write(const char *devname, unsigned char addr, unsigned char reg, unsigned short value) +{ + return(davinci_eth_phy_write(addr, reg, value) ? 0 : 1); +} +#endif + +static void __attribute__((unused)) davinci_eth_gigabit_enable(int phy_addr) +{ + u_int16_t data; + + if (davinci_eth_phy_read(phy_addr, 0, &data)) { + if (data & (1 << 6)) { /* speed selection MSB */ + /* + * Check if link detected is giga-bit + * If Gigabit mode detected, enable gigbit in MAC + */ + writel(readl(&adap_emac->MACCONTROL) | + EMAC_MACCONTROL_GIGFORCE | + EMAC_MACCONTROL_GIGABIT_ENABLE, + &adap_emac->MACCONTROL); + } + } +} + +/* Eth device open */ +static int davinci_eth_open(struct eth_device *dev, bd_t *bis) +{ + dv_reg_p addr; + u_int32_t clkdiv, cnt; + volatile emac_desc *rx_desc; + int index; + + debug_emac("+ emac_open\n"); + + /* Reset EMAC module and disable interrupts in wrapper */ + writel(1, &adap_emac->SOFTRESET); + while (readl(&adap_emac->SOFTRESET) != 0) + ; +#if defined(DAVINCI_EMAC_VERSION2) + writel(1, &adap_ewrap->softrst); + while (readl(&adap_ewrap->softrst) != 0) + ; +#else + writel(0, &adap_ewrap->EWCTL); + for (cnt = 0; cnt < 5; cnt++) { + clkdiv = readl(&adap_ewrap->EWCTL); + } +#endif + +#if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \ + defined(CONFIG_MACH_DAVINCI_DA850_EVM) + adap_ewrap->c0rxen = adap_ewrap->c1rxen = adap_ewrap->c2rxen = 0; + adap_ewrap->c0txen = adap_ewrap->c1txen = adap_ewrap->c2txen = 0; + adap_ewrap->c0miscen = adap_ewrap->c1miscen = adap_ewrap->c2miscen = 0; +#endif + rx_desc = emac_rx_desc; + + writel(1, &adap_emac->TXCONTROL); + writel(1, &adap_emac->RXCONTROL); + + davinci_eth_set_mac_addr(dev); + + /* Set DMA 8 TX / 8 RX Head pointers to 0 */ + addr = &adap_emac->TX0HDP; + for(cnt = 0; cnt < 16; cnt++) + writel(0, addr++); + + addr = &adap_emac->RX0HDP; + for(cnt = 0; cnt < 16; cnt++) + writel(0, addr++); + + /* Clear Statistics (do this before setting MacControl register) */ + addr = &adap_emac->RXGOODFRAMES; + for(cnt = 0; cnt < EMAC_NUM_STATS; cnt++) + writel(0, addr++); + + /* No multicast addressing */ + writel(0, &adap_emac->MACHASH1); + writel(0, &adap_emac->MACHASH2); + + /* Create RX queue and set receive process in place */ + emac_rx_active_head = emac_rx_desc; + for (cnt = 0; cnt < EMAC_MAX_RX_BUFFERS; cnt++) { + rx_desc->next = BD_TO_HW((u_int32_t)(rx_desc + 1)); + rx_desc->buffer = &emac_rx_buffers[cnt * EMAC_RXBUF_SIZE]; + rx_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE; + rx_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT; + rx_desc++; + } + + /* Finalize the rx desc list */ + rx_desc--; + rx_desc->next = 0; + emac_rx_active_tail = rx_desc; + emac_rx_queue_active = 1; + + davinci_flush_rx_descs(); + + /* Enable TX/RX */ + writel(EMAC_MAX_ETHERNET_PKT_SIZE, &adap_emac->RXMAXLEN); + writel(0, &adap_emac->RXBUFFEROFFSET); + + /* + * No fancy configs - Use this for promiscous debug + * - EMAC_RXMBPENABLE_RXCAFEN_ENABLE + */ + writel(EMAC_RXMBPENABLE_RXBROADEN, &adap_emac->RXMBPENABLE); + + /* Enable ch 0 only */ + writel(1, &adap_emac->RXUNICASTSET); + + /* Enable MII interface and Full duplex mode */ +#if defined(CONFIG_SOC_DA8XX) || \ + (defined(CONFIG_OMAP34XX) && defined(CONFIG_DRIVER_TI_EMAC_USE_RMII)) + writel((EMAC_MACCONTROL_MIIEN_ENABLE | + EMAC_MACCONTROL_FULLDUPLEX_ENABLE | + EMAC_MACCONTROL_RMIISPEED_100), + &adap_emac->MACCONTROL); +#else + writel((EMAC_MACCONTROL_MIIEN_ENABLE | + EMAC_MACCONTROL_FULLDUPLEX_ENABLE), + &adap_emac->MACCONTROL); +#endif + + /* Init MDIO & get link state */ + clkdiv = CONFIG_SYS_EMAC_TI_CLKDIV; + writel((clkdiv & 0xff) | MDIO_CONTROL_ENABLE | MDIO_CONTROL_FAULT, + &adap_mdio->CONTROL); + + /* We need to wait for MDIO to start */ + udelay(1000); + + index = get_active_phy(); + if (index == -1) + return(0); + + emac_gigabit_enable(active_phy_addr[index]); + + /* Start receive process */ + writel(BD_TO_HW((u_int32_t)emac_rx_desc), &adap_emac->RX0HDP); + + debug_emac("- emac_open\n"); + + return(1); +} + +/* EMAC Channel Teardown */ +static void davinci_eth_ch_teardown(int ch) +{ + dv_reg dly = 0xff; + dv_reg cnt; + + debug_emac("+ emac_ch_teardown\n"); + + if (ch == EMAC_CH_TX) { + /* Init TX channel teardown */ + writel(0, &adap_emac->TXTEARDOWN); + do { + /* + * Wait here for Tx teardown completion interrupt to + * occur. Note: A task delay can be called here to pend + * rather than occupying CPU cycles - anyway it has + * been found that teardown takes very few cpu cycles + * and does not affect functionality + */ + dly--; + udelay(1); + if (dly == 0) + break; + cnt = readl(&adap_emac->TX0CP); + } while (cnt != 0xfffffffc); + writel(cnt, &adap_emac->TX0CP); + writel(0, &adap_emac->TX0HDP); + } else { + /* Init RX channel teardown */ + writel(0, &adap_emac->RXTEARDOWN); + do { + /* + * Wait here for Rx teardown completion interrupt to + * occur. Note: A task delay can be called here to pend + * rather than occupying CPU cycles - anyway it has + * been found that teardown takes very few cpu cycles + * and does not affect functionality + */ + dly--; + udelay(1); + if (dly == 0) + break; + cnt = readl(&adap_emac->RX0CP); + } while (cnt != 0xfffffffc); + writel(cnt, &adap_emac->RX0CP); + writel(0, &adap_emac->RX0HDP); + } + + debug_emac("- emac_ch_teardown\n"); +} + +/* Eth device close */ +static void davinci_eth_close(struct eth_device *dev) +{ + debug_emac("+ emac_close\n"); + + davinci_eth_ch_teardown(EMAC_CH_TX); /* TX Channel teardown */ + if (readl(&adap_emac->RXCONTROL) & 1) + davinci_eth_ch_teardown(EMAC_CH_RX); /* RX Channel teardown */ + + /* Reset EMAC module and disable interrupts in wrapper */ + writel(1, &adap_emac->SOFTRESET); +#if defined(DAVINCI_EMAC_VERSION2) + writel(1, &adap_ewrap->softrst); +#else + writel(0, &adap_ewrap->EWCTL); +#endif + +#if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \ + defined(CONFIG_MACH_DAVINCI_DA850_EVM) + adap_ewrap->c0rxen = adap_ewrap->c1rxen = adap_ewrap->c2rxen = 0; + adap_ewrap->c0txen = adap_ewrap->c1txen = adap_ewrap->c2txen = 0; + adap_ewrap->c0miscen = adap_ewrap->c1miscen = adap_ewrap->c2miscen = 0; +#endif + debug_emac("- emac_close\n"); +} + +static int tx_send_loop = 0; + +/* + * This function sends a single packet on the network and returns + * positive number (number of bytes transmitted) or negative for error + */ +static int davinci_eth_send_packet (struct eth_device *dev, + void *packet, int length) +{ + int ret_status = -1; + int index; + tx_send_loop = 0; + + index = get_active_phy(); + if (index == -1) { + printf(" WARN: emac_send_packet: No link\n"); + return (ret_status); + } + + emac_gigabit_enable(active_phy_addr[index]); + + /* Check packet size and if < EMAC_MIN_ETHERNET_PKT_SIZE, pad it up */ + if (length < EMAC_MIN_ETHERNET_PKT_SIZE) { + length = EMAC_MIN_ETHERNET_PKT_SIZE; + } + + /* Populate the TX descriptor */ + emac_tx_desc->next = 0; + emac_tx_desc->buffer = (u_int8_t *) packet; + emac_tx_desc->buff_off_len = (length & 0xffff); + emac_tx_desc->pkt_flag_len = ((length & 0xffff) | + EMAC_CPPI_SOP_BIT | + EMAC_CPPI_OWNERSHIP_BIT | + EMAC_CPPI_EOP_BIT); + + flush_dcache_range((unsigned long)packet, + (unsigned long)packet + length); + davinci_flush_desc(emac_tx_desc); + + /* Send the packet */ + writel(BD_TO_HW((unsigned long)emac_tx_desc), &adap_emac->TX0HDP); + + /* Wait for packet to complete or link down */ + while (1) { + if (!phy[index].get_link_speed(active_phy_addr[index])) { + davinci_eth_ch_teardown (EMAC_CH_TX); + return (ret_status); + } + + emac_gigabit_enable(active_phy_addr[index]); + + if (readl(&adap_emac->TXINTSTATRAW) & 0x01) { + ret_status = length; + break; + } + tx_send_loop++; + } + + return (ret_status); +} + +/* + * This function handles receipt of a packet from the network + */ +static int davinci_eth_rcv_packet (struct eth_device *dev) +{ + volatile emac_desc *rx_curr_desc; + volatile emac_desc *curr_desc; + volatile emac_desc *tail_desc; + int status, ret = -1; + + davinci_invalidate_rx_descs(); + + rx_curr_desc = emac_rx_active_head; + status = rx_curr_desc->pkt_flag_len; + if ((rx_curr_desc) && ((status & EMAC_CPPI_OWNERSHIP_BIT) == 0)) { + if (status & EMAC_CPPI_RX_ERROR_FRAME) { + /* Error in packet - discard it and requeue desc */ + printf ("WARN: emac_rcv_pkt: Error in packet\n"); + } else { + unsigned long tmp = (unsigned long)rx_curr_desc->buffer; + + invalidate_dcache_range(tmp, tmp + EMAC_RXBUF_SIZE); + net_process_received_packet( + rx_curr_desc->buffer, + rx_curr_desc->buff_off_len & 0xffff); + ret = rx_curr_desc->buff_off_len & 0xffff; + } + + /* Ack received packet descriptor */ + writel(BD_TO_HW((ulong)rx_curr_desc), &adap_emac->RX0CP); + curr_desc = rx_curr_desc; + emac_rx_active_head = + (volatile emac_desc *) (HW_TO_BD(rx_curr_desc->next)); + + if (status & EMAC_CPPI_EOQ_BIT) { + if (emac_rx_active_head) { + writel(BD_TO_HW((ulong)emac_rx_active_head), + &adap_emac->RX0HDP); + } else { + emac_rx_queue_active = 0; + printf ("INFO:emac_rcv_packet: RX Queue not active\n"); + } + } + + /* Recycle RX descriptor */ + rx_curr_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE; + rx_curr_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT; + rx_curr_desc->next = 0; + davinci_flush_desc(rx_curr_desc); + + if (emac_rx_active_head == 0) { + printf ("INFO: emac_rcv_pkt: active queue head = 0\n"); + emac_rx_active_head = curr_desc; + emac_rx_active_tail = curr_desc; + if (emac_rx_queue_active != 0) { + writel(BD_TO_HW((ulong)emac_rx_active_head), + &adap_emac->RX0HDP); + printf ("INFO: emac_rcv_pkt: active queue head = 0, HDP fired\n"); + emac_rx_queue_active = 1; + } + } else { + tail_desc = emac_rx_active_tail; + emac_rx_active_tail = curr_desc; + tail_desc->next = BD_TO_HW((ulong) curr_desc); + status = tail_desc->pkt_flag_len; + if (status & EMAC_CPPI_EOQ_BIT) { + davinci_flush_desc(tail_desc); + writel(BD_TO_HW((ulong)curr_desc), + &adap_emac->RX0HDP); + status &= ~EMAC_CPPI_EOQ_BIT; + tail_desc->pkt_flag_len = status; + } + davinci_flush_desc(tail_desc); + } + return (ret); + } + return (0); +} + +/* + * This function initializes the emac hardware. It does NOT initialize + * EMAC modules power or pin multiplexors, that is done by board_init() + * much earlier in bootup process. Returns 1 on success, 0 otherwise. + */ +int davinci_emac_initialize(void) +{ + u_int32_t phy_id; + u_int16_t tmp; + int i; + int ret; + struct eth_device *dev; + + dev = malloc(sizeof *dev); + + if (dev == NULL) + return -1; + + memset(dev, 0, sizeof *dev); + sprintf(dev->name, "DaVinci-EMAC"); + + dev->iobase = 0; + dev->init = davinci_eth_open; + dev->halt = davinci_eth_close; + dev->send = davinci_eth_send_packet; + dev->recv = davinci_eth_rcv_packet; + dev->write_hwaddr = davinci_eth_set_mac_addr; + + eth_register(dev); + + davinci_eth_mdio_enable(); + + /* let the EMAC detect the PHYs */ + udelay(5000); + + for (i = 0; i < 256; i++) { + if (readl(&adap_mdio->ALIVE)) + break; + udelay(1000); + } + + if (i >= 256) { + printf("No ETH PHY detected!!!\n"); + return(0); + } + + /* Find if PHY(s) is/are connected */ + ret = davinci_eth_phy_detect(); + if (!ret) + return(0); + else + debug_emac(" %d ETH PHY detected\n", ret); + + /* Get PHY ID and initialize phy_ops for a detected PHY */ + for (i = 0; i < num_phy; i++) { + if (!davinci_eth_phy_read(active_phy_addr[i], MII_PHYSID1, + &tmp)) { + active_phy_addr[i] = 0xff; + continue; + } + + phy_id = (tmp << 16) & 0xffff0000; + + if (!davinci_eth_phy_read(active_phy_addr[i], MII_PHYSID2, + &tmp)) { + active_phy_addr[i] = 0xff; + continue; + } + + phy_id |= tmp & 0x0000ffff; + + switch (phy_id) { +#ifdef PHY_KSZ8873 + case PHY_KSZ8873: + sprintf(phy[i].name, "KSZ8873 @ 0x%02x", + active_phy_addr[i]); + phy[i].init = ksz8873_init_phy; + phy[i].is_phy_connected = ksz8873_is_phy_connected; + phy[i].get_link_speed = ksz8873_get_link_speed; + phy[i].auto_negotiate = ksz8873_auto_negotiate; + break; +#endif +#ifdef PHY_LXT972 + case PHY_LXT972: + sprintf(phy[i].name, "LXT972 @ 0x%02x", + active_phy_addr[i]); + phy[i].init = lxt972_init_phy; + phy[i].is_phy_connected = lxt972_is_phy_connected; + phy[i].get_link_speed = lxt972_get_link_speed; + phy[i].auto_negotiate = lxt972_auto_negotiate; + break; +#endif +#ifdef PHY_DP83848 + case PHY_DP83848: + sprintf(phy[i].name, "DP83848 @ 0x%02x", + active_phy_addr[i]); + phy[i].init = dp83848_init_phy; + phy[i].is_phy_connected = dp83848_is_phy_connected; + phy[i].get_link_speed = dp83848_get_link_speed; + phy[i].auto_negotiate = dp83848_auto_negotiate; + break; +#endif +#ifdef PHY_ET1011C + case PHY_ET1011C: + sprintf(phy[i].name, "ET1011C @ 0x%02x", + active_phy_addr[i]); + phy[i].init = gen_init_phy; + phy[i].is_phy_connected = gen_is_phy_connected; + phy[i].get_link_speed = et1011c_get_link_speed; + phy[i].auto_negotiate = gen_auto_negotiate; + break; +#endif + default: + sprintf(phy[i].name, "GENERIC @ 0x%02x", + active_phy_addr[i]); + phy[i].init = gen_init_phy; + phy[i].is_phy_connected = gen_is_phy_connected; + phy[i].get_link_speed = gen_get_link_speed; + phy[i].auto_negotiate = gen_auto_negotiate; + } + + debug("Ethernet PHY: %s\n", phy[i].name); + + miiphy_register(phy[i].name, davinci_mii_phy_read, + davinci_mii_phy_write); + } + +#if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \ + defined(CONFIG_MACH_DAVINCI_DA850_EVM) && \ + !defined(CONFIG_DRIVER_TI_EMAC_RMII_NO_NEGOTIATE) + for (i = 0; i < num_phy; i++) { + if (phy[i].is_phy_connected(i)) + phy[i].auto_negotiate(i); + } +#endif + return(1); +} diff --git a/sources/uboot-be550/drivers/net/davinci_emac.h b/sources/uboot-be550/drivers/net/davinci_emac.h new file mode 100644 index 00000000..13cd68f0 --- /dev/null +++ b/sources/uboot-be550/drivers/net/davinci_emac.h @@ -0,0 +1,303 @@ +/* + * Copyright (C) 2011 Ilya Yanok, Emcraft Systems + * + * Based on: mach-davinci/emac_defs.h + * Copyright (C) 2007 Sergey Kubushyn + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _DAVINCI_EMAC_H_ +#define _DAVINCI_EMAC_H_ +/* Ethernet Min/Max packet size */ +#define EMAC_MIN_ETHERNET_PKT_SIZE 60 +#define EMAC_MAX_ETHERNET_PKT_SIZE 1518 +/* Buffer size (should be aligned on 32 byte and cache line) */ +#define EMAC_RXBUF_SIZE ALIGN(ALIGN(EMAC_MAX_ETHERNET_PKT_SIZE, 32),\ + ARCH_DMA_MINALIGN) + +/* Number of RX packet buffers + * NOTE: Only 1 buffer supported as of now + */ +#define EMAC_MAX_RX_BUFFERS 10 + + +/*********************************************** + ******** Internally used macros *************** + ***********************************************/ + +#define EMAC_CH_TX 1 +#define EMAC_CH_RX 0 + +/* Each descriptor occupies 4 words, lets start RX desc's at 0 and + * reserve space for 64 descriptors max + */ +#define EMAC_RX_DESC_BASE 0x0 +#define EMAC_TX_DESC_BASE 0x1000 + +/* EMAC Teardown value */ +#define EMAC_TEARDOWN_VALUE 0xfffffffc + +/* MII Status Register */ +#define MII_STATUS_REG 1 + +/* Number of statistics registers */ +#define EMAC_NUM_STATS 36 + + +/* EMAC Descriptor */ +typedef volatile struct _emac_desc +{ + u_int32_t next; /* Pointer to next descriptor + in chain */ + u_int8_t *buffer; /* Pointer to data buffer */ + u_int32_t buff_off_len; /* Buffer Offset(MSW) and Length(LSW) */ + u_int32_t pkt_flag_len; /* Packet Flags(MSW) and Length(LSW) */ +} emac_desc; + +/* CPPI bit positions */ +#define EMAC_CPPI_SOP_BIT (0x80000000) +#define EMAC_CPPI_EOP_BIT (0x40000000) +#define EMAC_CPPI_OWNERSHIP_BIT (0x20000000) +#define EMAC_CPPI_EOQ_BIT (0x10000000) +#define EMAC_CPPI_TEARDOWN_COMPLETE_BIT (0x08000000) +#define EMAC_CPPI_PASS_CRC_BIT (0x04000000) + +#define EMAC_CPPI_RX_ERROR_FRAME (0x03fc0000) + +#define EMAC_MACCONTROL_MIIEN_ENABLE (0x20) +#define EMAC_MACCONTROL_FULLDUPLEX_ENABLE (0x1) +#define EMAC_MACCONTROL_GIGABIT_ENABLE (1 << 7) +#define EMAC_MACCONTROL_GIGFORCE (1 << 17) +#define EMAC_MACCONTROL_RMIISPEED_100 (1 << 15) + +#define EMAC_MAC_ADDR_MATCH (1 << 19) +#define EMAC_MAC_ADDR_IS_VALID (1 << 20) + +#define EMAC_RXMBPENABLE_RXCAFEN_ENABLE (0x200000) +#define EMAC_RXMBPENABLE_RXBROADEN (0x2000) + + +#define MDIO_CONTROL_IDLE (0x80000000) +#define MDIO_CONTROL_ENABLE (0x40000000) +#define MDIO_CONTROL_FAULT_ENABLE (0x40000) +#define MDIO_CONTROL_FAULT (0x80000) +#define MDIO_USERACCESS0_GO (0x80000000) +#define MDIO_USERACCESS0_WRITE_READ (0x0) +#define MDIO_USERACCESS0_WRITE_WRITE (0x40000000) +#define MDIO_USERACCESS0_ACK (0x20000000) + +/* Ethernet MAC Registers Structure */ +typedef struct { + dv_reg TXIDVER; + dv_reg TXCONTROL; + dv_reg TXTEARDOWN; + u_int8_t RSVD0[4]; + dv_reg RXIDVER; + dv_reg RXCONTROL; + dv_reg RXTEARDOWN; + u_int8_t RSVD1[100]; + dv_reg TXINTSTATRAW; + dv_reg TXINTSTATMASKED; + dv_reg TXINTMASKSET; + dv_reg TXINTMASKCLEAR; + dv_reg MACINVECTOR; + u_int8_t RSVD2[12]; + dv_reg RXINTSTATRAW; + dv_reg RXINTSTATMASKED; + dv_reg RXINTMASKSET; + dv_reg RXINTMASKCLEAR; + dv_reg MACINTSTATRAW; + dv_reg MACINTSTATMASKED; + dv_reg MACINTMASKSET; + dv_reg MACINTMASKCLEAR; + u_int8_t RSVD3[64]; + dv_reg RXMBPENABLE; + dv_reg RXUNICASTSET; + dv_reg RXUNICASTCLEAR; + dv_reg RXMAXLEN; + dv_reg RXBUFFEROFFSET; + dv_reg RXFILTERLOWTHRESH; + u_int8_t RSVD4[8]; + dv_reg RX0FLOWTHRESH; + dv_reg RX1FLOWTHRESH; + dv_reg RX2FLOWTHRESH; + dv_reg RX3FLOWTHRESH; + dv_reg RX4FLOWTHRESH; + dv_reg RX5FLOWTHRESH; + dv_reg RX6FLOWTHRESH; + dv_reg RX7FLOWTHRESH; + dv_reg RX0FREEBUFFER; + dv_reg RX1FREEBUFFER; + dv_reg RX2FREEBUFFER; + dv_reg RX3FREEBUFFER; + dv_reg RX4FREEBUFFER; + dv_reg RX5FREEBUFFER; + dv_reg RX6FREEBUFFER; + dv_reg RX7FREEBUFFER; + dv_reg MACCONTROL; + dv_reg MACSTATUS; + dv_reg EMCONTROL; + dv_reg FIFOCONTROL; + dv_reg MACCONFIG; + dv_reg SOFTRESET; + u_int8_t RSVD5[88]; + dv_reg MACSRCADDRLO; + dv_reg MACSRCADDRHI; + dv_reg MACHASH1; + dv_reg MACHASH2; + dv_reg BOFFTEST; + dv_reg TPACETEST; + dv_reg RXPAUSE; + dv_reg TXPAUSE; + u_int8_t RSVD6[16]; + dv_reg RXGOODFRAMES; + dv_reg RXBCASTFRAMES; + dv_reg RXMCASTFRAMES; + dv_reg RXPAUSEFRAMES; + dv_reg RXCRCERRORS; + dv_reg RXALIGNCODEERRORS; + dv_reg RXOVERSIZED; + dv_reg RXJABBER; + dv_reg RXUNDERSIZED; + dv_reg RXFRAGMENTS; + dv_reg RXFILTERED; + dv_reg RXQOSFILTERED; + dv_reg RXOCTETS; + dv_reg TXGOODFRAMES; + dv_reg TXBCASTFRAMES; + dv_reg TXMCASTFRAMES; + dv_reg TXPAUSEFRAMES; + dv_reg TXDEFERRED; + dv_reg TXCOLLISION; + dv_reg TXSINGLECOLL; + dv_reg TXMULTICOLL; + dv_reg TXEXCESSIVECOLL; + dv_reg TXLATECOLL; + dv_reg TXUNDERRUN; + dv_reg TXCARRIERSENSE; + dv_reg TXOCTETS; + dv_reg FRAME64; + dv_reg FRAME65T127; + dv_reg FRAME128T255; + dv_reg FRAME256T511; + dv_reg FRAME512T1023; + dv_reg FRAME1024TUP; + dv_reg NETOCTETS; + dv_reg RXSOFOVERRUNS; + dv_reg RXMOFOVERRUNS; + dv_reg RXDMAOVERRUNS; + u_int8_t RSVD7[624]; + dv_reg MACADDRLO; + dv_reg MACADDRHI; + dv_reg MACINDEX; + u_int8_t RSVD8[244]; + dv_reg TX0HDP; + dv_reg TX1HDP; + dv_reg TX2HDP; + dv_reg TX3HDP; + dv_reg TX4HDP; + dv_reg TX5HDP; + dv_reg TX6HDP; + dv_reg TX7HDP; + dv_reg RX0HDP; + dv_reg RX1HDP; + dv_reg RX2HDP; + dv_reg RX3HDP; + dv_reg RX4HDP; + dv_reg RX5HDP; + dv_reg RX6HDP; + dv_reg RX7HDP; + dv_reg TX0CP; + dv_reg TX1CP; + dv_reg TX2CP; + dv_reg TX3CP; + dv_reg TX4CP; + dv_reg TX5CP; + dv_reg TX6CP; + dv_reg TX7CP; + dv_reg RX0CP; + dv_reg RX1CP; + dv_reg RX2CP; + dv_reg RX3CP; + dv_reg RX4CP; + dv_reg RX5CP; + dv_reg RX6CP; + dv_reg RX7CP; +} emac_regs; + +/* EMAC Wrapper Registers Structure */ +typedef struct { +#ifdef DAVINCI_EMAC_VERSION2 + dv_reg idver; + dv_reg softrst; + dv_reg emctrl; + dv_reg c0rxthreshen; + dv_reg c0rxen; + dv_reg c0txen; + dv_reg c0miscen; + dv_reg c1rxthreshen; + dv_reg c1rxen; + dv_reg c1txen; + dv_reg c1miscen; + dv_reg c2rxthreshen; + dv_reg c2rxen; + dv_reg c2txen; + dv_reg c2miscen; + dv_reg c0rxthreshstat; + dv_reg c0rxstat; + dv_reg c0txstat; + dv_reg c0miscstat; + dv_reg c1rxthreshstat; + dv_reg c1rxstat; + dv_reg c1txstat; + dv_reg c1miscstat; + dv_reg c2rxthreshstat; + dv_reg c2rxstat; + dv_reg c2txstat; + dv_reg c2miscstat; + dv_reg c0rximax; + dv_reg c0tximax; + dv_reg c1rximax; + dv_reg c1tximax; + dv_reg c2rximax; + dv_reg c2tximax; +#else + u_int8_t RSVD0[4100]; + dv_reg EWCTL; + dv_reg EWINTTCNT; +#endif +} ewrap_regs; + +/* EMAC MDIO Registers Structure */ +typedef struct { + dv_reg VERSION; + dv_reg CONTROL; + dv_reg ALIVE; + dv_reg LINK; + dv_reg LINKINTRAW; + dv_reg LINKINTMASKED; + u_int8_t RSVD0[8]; + dv_reg USERINTRAW; + dv_reg USERINTMASKED; + dv_reg USERINTMASKSET; + dv_reg USERINTMASKCLEAR; + u_int8_t RSVD1[80]; + dv_reg USERACCESS0; + dv_reg USERPHYSEL0; + dv_reg USERACCESS1; + dv_reg USERPHYSEL1; +} mdio_regs; + +int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data); +int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data); + +typedef struct { + char name[64]; + int (*init)(int phy_addr); + int (*is_phy_connected)(int phy_addr); + int (*get_link_speed)(int phy_addr); + int (*auto_negotiate)(int phy_addr); +} phy_t; + +#endif /* _DAVINCI_EMAC_H_ */ diff --git a/sources/uboot-be550/drivers/net/dc2114x.c b/sources/uboot-be550/drivers/net/dc2114x.c new file mode 100644 index 00000000..8245cf51 --- /dev/null +++ b/sources/uboot-be550/drivers/net/dc2114x.c @@ -0,0 +1,763 @@ +/* + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +#undef DEBUG_SROM +#undef DEBUG_SROM2 + +#undef UPDATE_SROM + +/* PCI Registers. + */ +#define PCI_CFDA_PSM 0x43 + +#define CFRV_RN 0x000000f0 /* Revision Number */ + +#define WAKEUP 0x00 /* Power Saving Wakeup */ +#define SLEEP 0x80 /* Power Saving Sleep Mode */ + +#define DC2114x_BRK 0x0020 /* CFRV break between DC21142 & DC21143 */ + +/* Ethernet chip registers. + */ +#define DE4X5_BMR 0x000 /* Bus Mode Register */ +#define DE4X5_TPD 0x008 /* Transmit Poll Demand Reg */ +#define DE4X5_RRBA 0x018 /* RX Ring Base Address Reg */ +#define DE4X5_TRBA 0x020 /* TX Ring Base Address Reg */ +#define DE4X5_STS 0x028 /* Status Register */ +#define DE4X5_OMR 0x030 /* Operation Mode Register */ +#define DE4X5_SICR 0x068 /* SIA Connectivity Register */ +#define DE4X5_APROM 0x048 /* Ethernet Address PROM */ + +/* Register bits. + */ +#define BMR_SWR 0x00000001 /* Software Reset */ +#define STS_TS 0x00700000 /* Transmit Process State */ +#define STS_RS 0x000e0000 /* Receive Process State */ +#define OMR_ST 0x00002000 /* Start/Stop Transmission Command */ +#define OMR_SR 0x00000002 /* Start/Stop Receive */ +#define OMR_PS 0x00040000 /* Port Select */ +#define OMR_SDP 0x02000000 /* SD Polarity - MUST BE ASSERTED */ +#define OMR_PM 0x00000080 /* Pass All Multicast */ + +/* Descriptor bits. + */ +#define R_OWN 0x80000000 /* Own Bit */ +#define RD_RER 0x02000000 /* Receive End Of Ring */ +#define RD_LS 0x00000100 /* Last Descriptor */ +#define RD_ES 0x00008000 /* Error Summary */ +#define TD_TER 0x02000000 /* Transmit End Of Ring */ +#define T_OWN 0x80000000 /* Own Bit */ +#define TD_LS 0x40000000 /* Last Segment */ +#define TD_FS 0x20000000 /* First Segment */ +#define TD_ES 0x00008000 /* Error Summary */ +#define TD_SET 0x08000000 /* Setup Packet */ + +/* The EEPROM commands include the alway-set leading bit. */ +#define SROM_WRITE_CMD 5 +#define SROM_READ_CMD 6 +#define SROM_ERASE_CMD 7 + +#define SROM_HWADD 0x0014 /* Hardware Address offset in SROM */ +#define SROM_RD 0x00004000 /* Read from Boot ROM */ +#define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */ +#define EE_WRITE_0 0x4801 +#define EE_WRITE_1 0x4805 +#define EE_DATA_READ 0x08 /* EEPROM chip data out. */ +#define SROM_SR 0x00000800 /* Select Serial ROM when set */ + +#define DT_IN 0x00000004 /* Serial Data In */ +#define DT_CLK 0x00000002 /* Serial ROM Clock */ +#define DT_CS 0x00000001 /* Serial ROM Chip Select */ + +#define POLL_DEMAND 1 + +#ifdef CONFIG_TULIP_FIX_DAVICOM +#define RESET_DM9102(dev) {\ + unsigned long i;\ + i=INL(dev, 0x0);\ + udelay(1000);\ + OUTL(dev, i | BMR_SWR, DE4X5_BMR);\ + udelay(1000);\ +} +#else +#define RESET_DE4X5(dev) {\ + int i;\ + i=INL(dev, DE4X5_BMR);\ + udelay(1000);\ + OUTL(dev, i | BMR_SWR, DE4X5_BMR);\ + udelay(1000);\ + OUTL(dev, i, DE4X5_BMR);\ + udelay(1000);\ + for (i=0;i<5;i++) {INL(dev, DE4X5_BMR); udelay(10000);}\ + udelay(1000);\ +} +#endif + +#define START_DE4X5(dev) {\ + s32 omr; \ + omr = INL(dev, DE4X5_OMR);\ + omr |= OMR_ST | OMR_SR;\ + OUTL(dev, omr, DE4X5_OMR); /* Enable the TX and/or RX */\ +} + +#define STOP_DE4X5(dev) {\ + s32 omr; \ + omr = INL(dev, DE4X5_OMR);\ + omr &= ~(OMR_ST|OMR_SR);\ + OUTL(dev, omr, DE4X5_OMR); /* Disable the TX and/or RX */ \ +} + +#define NUM_RX_DESC PKTBUFSRX +#ifndef CONFIG_TULIP_FIX_DAVICOM + #define NUM_TX_DESC 1 /* Number of TX descriptors */ +#else + #define NUM_TX_DESC 4 +#endif +#define RX_BUFF_SZ PKTSIZE_ALIGN + +#define TOUT_LOOP 1000000 + +#define SETUP_FRAME_LEN 192 +#define ETH_ALEN 6 + +struct de4x5_desc { + volatile s32 status; + u32 des1; + u32 buf; + u32 next; +}; + +static struct de4x5_desc rx_ring[NUM_RX_DESC] __attribute__ ((aligned(32))); /* RX descriptor ring */ +static struct de4x5_desc tx_ring[NUM_TX_DESC] __attribute__ ((aligned(32))); /* TX descriptor ring */ +static int rx_new; /* RX descriptor ring pointer */ +static int tx_new; /* TX descriptor ring pointer */ + +static char rxRingSize; +static char txRingSize; + +#if defined(UPDATE_SROM) || !defined(CONFIG_TULIP_FIX_DAVICOM) +static void sendto_srom(struct eth_device* dev, u_int command, u_long addr); +static int getfrom_srom(struct eth_device* dev, u_long addr); +static int do_eeprom_cmd(struct eth_device *dev, u_long ioaddr,int cmd,int cmd_len); +static int do_read_eeprom(struct eth_device *dev,u_long ioaddr,int location,int addr_len); +#endif /* UPDATE_SROM || !CONFIG_TULIP_FIX_DAVICOM */ +#ifdef UPDATE_SROM +static int write_srom(struct eth_device *dev, u_long ioaddr, int index, int new_value); +static void update_srom(struct eth_device *dev, bd_t *bis); +#endif +#ifndef CONFIG_TULIP_FIX_DAVICOM +static int read_srom(struct eth_device *dev, u_long ioaddr, int index); +static void read_hw_addr(struct eth_device* dev, bd_t * bis); +#endif /* CONFIG_TULIP_FIX_DAVICOM */ +static void send_setup_frame(struct eth_device* dev, bd_t * bis); + +static int dc21x4x_init(struct eth_device* dev, bd_t* bis); +static int dc21x4x_send(struct eth_device *dev, void *packet, int length); +static int dc21x4x_recv(struct eth_device* dev); +static void dc21x4x_halt(struct eth_device* dev); +#ifdef CONFIG_TULIP_SELECT_MEDIA +extern void dc21x4x_select_media(struct eth_device* dev); +#endif + +#if defined(CONFIG_E500) +#define phys_to_bus(a) (a) +#else +#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a) +#endif + +static int INL(struct eth_device* dev, u_long addr) +{ + return le32_to_cpu(*(volatile u_long *)(addr + dev->iobase)); +} + +static void OUTL(struct eth_device* dev, int command, u_long addr) +{ + *(volatile u_long *)(addr + dev->iobase) = cpu_to_le32(command); +} + +static struct pci_device_id supported[] = { + { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST }, + { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142 }, +#ifdef CONFIG_TULIP_FIX_DAVICOM + { PCI_VENDOR_ID_DAVICOM, PCI_DEVICE_ID_DAVICOM_DM9102A }, +#endif + { } +}; + +int dc21x4x_initialize(bd_t *bis) +{ + int idx=0; + int card_number = 0; + unsigned int cfrv; + unsigned char timer; + pci_dev_t devbusfn; + unsigned int iobase; + unsigned short status; + struct eth_device* dev; + + while(1) { + devbusfn = pci_find_devices(supported, idx++); + if (devbusfn == -1) { + break; + } + + /* Get the chip configuration revision register. */ + pci_read_config_dword(devbusfn, PCI_REVISION_ID, &cfrv); + +#ifndef CONFIG_TULIP_FIX_DAVICOM + if ((cfrv & CFRV_RN) < DC2114x_BRK ) { + printf("Error: The chip is not DC21143.\n"); + continue; + } +#endif + + pci_read_config_word(devbusfn, PCI_COMMAND, &status); + status |= +#ifdef CONFIG_TULIP_USE_IO + PCI_COMMAND_IO | +#else + PCI_COMMAND_MEMORY | +#endif + PCI_COMMAND_MASTER; + pci_write_config_word(devbusfn, PCI_COMMAND, status); + + pci_read_config_word(devbusfn, PCI_COMMAND, &status); +#ifdef CONFIG_TULIP_USE_IO + if (!(status & PCI_COMMAND_IO)) { + printf("Error: Can not enable I/O access.\n"); + continue; + } +#else + if (!(status & PCI_COMMAND_MEMORY)) { + printf("Error: Can not enable MEMORY access.\n"); + continue; + } +#endif + + if (!(status & PCI_COMMAND_MASTER)) { + printf("Error: Can not enable Bus Mastering.\n"); + continue; + } + + /* Check the latency timer for values >= 0x60. */ + pci_read_config_byte(devbusfn, PCI_LATENCY_TIMER, &timer); + + if (timer < 0x60) { + pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x60); + } + +#ifdef CONFIG_TULIP_USE_IO + /* read BAR for memory space access */ + pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &iobase); + iobase &= PCI_BASE_ADDRESS_IO_MASK; +#else + /* read BAR for memory space access */ + pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, &iobase); + iobase &= PCI_BASE_ADDRESS_MEM_MASK; +#endif + debug ("dc21x4x: DEC 21142 PCI Device @0x%x\n", iobase); + + dev = (struct eth_device*) malloc(sizeof *dev); + + if (!dev) { + printf("Can not allocalte memory of dc21x4x\n"); + break; + } + memset(dev, 0, sizeof(*dev)); + +#ifdef CONFIG_TULIP_FIX_DAVICOM + sprintf(dev->name, "Davicom#%d", card_number); +#else + sprintf(dev->name, "dc21x4x#%d", card_number); +#endif + +#ifdef CONFIG_TULIP_USE_IO + dev->iobase = pci_io_to_phys(devbusfn, iobase); +#else + dev->iobase = pci_mem_to_phys(devbusfn, iobase); +#endif + dev->priv = (void*) devbusfn; + dev->init = dc21x4x_init; + dev->halt = dc21x4x_halt; + dev->send = dc21x4x_send; + dev->recv = dc21x4x_recv; + + /* Ensure we're not sleeping. */ + pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP); + + udelay(10 * 1000); + +#ifndef CONFIG_TULIP_FIX_DAVICOM + read_hw_addr(dev, bis); +#endif + eth_register(dev); + + card_number++; + } + + return card_number; +} + +static int dc21x4x_init(struct eth_device* dev, bd_t* bis) +{ + int i; + int devbusfn = (int) dev->priv; + + /* Ensure we're not sleeping. */ + pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP); + +#ifdef CONFIG_TULIP_FIX_DAVICOM + RESET_DM9102(dev); +#else + RESET_DE4X5(dev); +#endif + + if ((INL(dev, DE4X5_STS) & (STS_TS | STS_RS)) != 0) { + printf("Error: Cannot reset ethernet controller.\n"); + return -1; + } + +#ifdef CONFIG_TULIP_SELECT_MEDIA + dc21x4x_select_media(dev); +#else + OUTL(dev, OMR_SDP | OMR_PS | OMR_PM, DE4X5_OMR); +#endif + + for (i = 0; i < NUM_RX_DESC; i++) { + rx_ring[i].status = cpu_to_le32(R_OWN); + rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ); + rx_ring[i].buf = cpu_to_le32( + phys_to_bus((u32)net_rx_packets[i])); +#ifdef CONFIG_TULIP_FIX_DAVICOM + rx_ring[i].next = cpu_to_le32( + phys_to_bus((u32)&rx_ring[(i + 1) % NUM_RX_DESC])); +#else + rx_ring[i].next = 0; +#endif + } + + for (i=0; i < NUM_TX_DESC; i++) { + tx_ring[i].status = 0; + tx_ring[i].des1 = 0; + tx_ring[i].buf = 0; + +#ifdef CONFIG_TULIP_FIX_DAVICOM + tx_ring[i].next = cpu_to_le32(phys_to_bus((u32) &tx_ring[(i+1) % NUM_TX_DESC])); +#else + tx_ring[i].next = 0; +#endif + } + + rxRingSize = NUM_RX_DESC; + txRingSize = NUM_TX_DESC; + + /* Write the end of list marker to the descriptor lists. */ + rx_ring[rxRingSize - 1].des1 |= cpu_to_le32(RD_RER); + tx_ring[txRingSize - 1].des1 |= cpu_to_le32(TD_TER); + + /* Tell the adapter where the TX/RX rings are located. */ + OUTL(dev, phys_to_bus((u32) &rx_ring), DE4X5_RRBA); + OUTL(dev, phys_to_bus((u32) &tx_ring), DE4X5_TRBA); + + START_DE4X5(dev); + + tx_new = 0; + rx_new = 0; + + send_setup_frame(dev, bis); + + return 0; +} + +static int dc21x4x_send(struct eth_device *dev, void *packet, int length) +{ + int status = -1; + int i; + + if (length <= 0) { + printf("%s: bad packet size: %d\n", dev->name, length); + goto Done; + } + + for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) { + if (i >= TOUT_LOOP) { + printf("%s: tx error buffer not ready\n", dev->name); + goto Done; + } + } + + tx_ring[tx_new].buf = cpu_to_le32(phys_to_bus((u32) packet)); + tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_LS | TD_FS | length); + tx_ring[tx_new].status = cpu_to_le32(T_OWN); + + OUTL(dev, POLL_DEMAND, DE4X5_TPD); + + for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) { + if (i >= TOUT_LOOP) { + printf(".%s: tx buffer not ready\n", dev->name); + goto Done; + } + } + + if (le32_to_cpu(tx_ring[tx_new].status) & TD_ES) { +#if 0 /* test-only */ + printf("TX error status = 0x%08X\n", + le32_to_cpu(tx_ring[tx_new].status)); +#endif + tx_ring[tx_new].status = 0x0; + goto Done; + } + + status = length; + + Done: + tx_new = (tx_new+1) % NUM_TX_DESC; + return status; +} + +static int dc21x4x_recv(struct eth_device* dev) +{ + s32 status; + int length = 0; + + for ( ; ; ) { + status = (s32)le32_to_cpu(rx_ring[rx_new].status); + + if (status & R_OWN) { + break; + } + + if (status & RD_LS) { + /* Valid frame status. + */ + if (status & RD_ES) { + + /* There was an error. + */ + printf("RX error status = 0x%08X\n", status); + } else { + /* A valid frame received. + */ + length = (le32_to_cpu(rx_ring[rx_new].status) >> 16); + + /* Pass the packet up to the protocol + * layers. + */ + net_process_received_packet( + net_rx_packets[rx_new], length - 4); + } + + /* Change buffer ownership for this frame, back + * to the adapter. + */ + rx_ring[rx_new].status = cpu_to_le32(R_OWN); + } + + /* Update entry information. + */ + rx_new = (rx_new + 1) % rxRingSize; + } + + return length; +} + +static void dc21x4x_halt(struct eth_device* dev) +{ + int devbusfn = (int) dev->priv; + + STOP_DE4X5(dev); + OUTL(dev, 0, DE4X5_SICR); + + pci_write_config_byte(devbusfn, PCI_CFDA_PSM, SLEEP); +} + +static void send_setup_frame(struct eth_device* dev, bd_t *bis) +{ + int i; + char setup_frame[SETUP_FRAME_LEN]; + char *pa = &setup_frame[0]; + + memset(pa, 0xff, SETUP_FRAME_LEN); + + for (i = 0; i < ETH_ALEN; i++) { + *(pa + (i & 1)) = dev->enetaddr[i]; + if (i & 0x01) { + pa += 4; + } + } + + for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) { + if (i >= TOUT_LOOP) { + printf("%s: tx error buffer not ready\n", dev->name); + goto Done; + } + } + + tx_ring[tx_new].buf = cpu_to_le32(phys_to_bus((u32) &setup_frame[0])); + tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_SET| SETUP_FRAME_LEN); + tx_ring[tx_new].status = cpu_to_le32(T_OWN); + + OUTL(dev, POLL_DEMAND, DE4X5_TPD); + + for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) { + if (i >= TOUT_LOOP) { + printf("%s: tx buffer not ready\n", dev->name); + goto Done; + } + } + + if (le32_to_cpu(tx_ring[tx_new].status) != 0x7FFFFFFF) { + printf("TX error status2 = 0x%08X\n", le32_to_cpu(tx_ring[tx_new].status)); + } + tx_new = (tx_new+1) % NUM_TX_DESC; + +Done: + return; +} + +#if defined(UPDATE_SROM) || !defined(CONFIG_TULIP_FIX_DAVICOM) +/* SROM Read and write routines. + */ +static void +sendto_srom(struct eth_device* dev, u_int command, u_long addr) +{ + OUTL(dev, command, addr); + udelay(1); +} + +static int +getfrom_srom(struct eth_device* dev, u_long addr) +{ + s32 tmp; + + tmp = INL(dev, addr); + udelay(1); + + return tmp; +} + +/* Note: this routine returns extra data bits for size detection. */ +static int do_read_eeprom(struct eth_device *dev, u_long ioaddr, int location, int addr_len) +{ + int i; + unsigned retval = 0; + int read_cmd = location | (SROM_READ_CMD << addr_len); + + sendto_srom(dev, SROM_RD | SROM_SR, ioaddr); + sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr); + +#ifdef DEBUG_SROM + printf(" EEPROM read at %d ", location); +#endif + + /* Shift the read command bits out. */ + for (i = 4 + addr_len; i >= 0; i--) { + short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0; + sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | dataval, ioaddr); + udelay(10); + sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | dataval | DT_CLK, ioaddr); + udelay(10); +#ifdef DEBUG_SROM2 + printf("%X", getfrom_srom(dev, ioaddr) & 15); +#endif + retval = (retval << 1) | ((getfrom_srom(dev, ioaddr) & EE_DATA_READ) ? 1 : 0); + } + + sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr); + +#ifdef DEBUG_SROM2 + printf(" :%X:", getfrom_srom(dev, ioaddr) & 15); +#endif + + for (i = 16; i > 0; i--) { + sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | DT_CLK, ioaddr); + udelay(10); +#ifdef DEBUG_SROM2 + printf("%X", getfrom_srom(dev, ioaddr) & 15); +#endif + retval = (retval << 1) | ((getfrom_srom(dev, ioaddr) & EE_DATA_READ) ? 1 : 0); + sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr); + udelay(10); + } + + /* Terminate the EEPROM access. */ + sendto_srom(dev, SROM_RD | SROM_SR, ioaddr); + +#ifdef DEBUG_SROM2 + printf(" EEPROM value at %d is %5.5x.\n", location, retval); +#endif + + return retval; +} +#endif /* UPDATE_SROM || !CONFIG_TULIP_FIX_DAVICOM */ + +/* This executes a generic EEPROM command, typically a write or write + * enable. It returns the data output from the EEPROM, and thus may + * also be used for reads. + */ +#if defined(UPDATE_SROM) || !defined(CONFIG_TULIP_FIX_DAVICOM) +static int do_eeprom_cmd(struct eth_device *dev, u_long ioaddr, int cmd, int cmd_len) +{ + unsigned retval = 0; + +#ifdef DEBUG_SROM + printf(" EEPROM op 0x%x: ", cmd); +#endif + + sendto_srom(dev,SROM_RD | SROM_SR | DT_CS | DT_CLK, ioaddr); + + /* Shift the command bits out. */ + do { + short dataval = (cmd & (1 << cmd_len)) ? EE_WRITE_1 : EE_WRITE_0; + sendto_srom(dev,dataval, ioaddr); + udelay(10); + +#ifdef DEBUG_SROM2 + printf("%X", getfrom_srom(dev,ioaddr) & 15); +#endif + + sendto_srom(dev,dataval | DT_CLK, ioaddr); + udelay(10); + retval = (retval << 1) | ((getfrom_srom(dev,ioaddr) & EE_DATA_READ) ? 1 : 0); + } while (--cmd_len >= 0); + sendto_srom(dev,SROM_RD | SROM_SR | DT_CS, ioaddr); + + /* Terminate the EEPROM access. */ + sendto_srom(dev,SROM_RD | SROM_SR, ioaddr); + +#ifdef DEBUG_SROM + printf(" EEPROM result is 0x%5.5x.\n", retval); +#endif + + return retval; +} +#endif /* UPDATE_SROM || !CONFIG_TULIP_FIX_DAVICOM */ + +#ifndef CONFIG_TULIP_FIX_DAVICOM +static int read_srom(struct eth_device *dev, u_long ioaddr, int index) +{ + int ee_addr_size = do_read_eeprom(dev, ioaddr, 0xff, 8) & 0x40000 ? 8 : 6; + + return do_eeprom_cmd(dev, ioaddr, + (((SROM_READ_CMD << ee_addr_size) | index) << 16) + | 0xffff, 3 + ee_addr_size + 16); +} +#endif /* CONFIG_TULIP_FIX_DAVICOM */ + +#ifdef UPDATE_SROM +static int write_srom(struct eth_device *dev, u_long ioaddr, int index, int new_value) +{ + int ee_addr_size = do_read_eeprom(dev, ioaddr, 0xff, 8) & 0x40000 ? 8 : 6; + int i; + unsigned short newval; + + udelay(10*1000); /* test-only */ + +#ifdef DEBUG_SROM + printf("ee_addr_size=%d.\n", ee_addr_size); + printf("Writing new entry 0x%4.4x to offset %d.\n", new_value, index); +#endif + + /* Enable programming modes. */ + do_eeprom_cmd(dev, ioaddr, (0x4f << (ee_addr_size-4)), 3+ee_addr_size); + + /* Do the actual write. */ + do_eeprom_cmd(dev, ioaddr, + (((SROM_WRITE_CMD<enetaddr[0]); + int i, j = 0; + + for (i = 0; i < (ETH_ALEN >> 1); i++) { + tmp = read_srom(dev, DE4X5_APROM, ((SROM_HWADD >> 1) + i)); + *p = le16_to_cpu(tmp); + j += *p++; + } + + if ((j == 0) || (j == 0x2fffd)) { + memset (dev->enetaddr, 0, ETH_ALEN); + debug ("Warning: can't read HW address from SROM.\n"); + goto Done; + } + + return; + +Done: +#ifdef UPDATE_SROM + update_srom(dev, bis); +#endif + return; +} +#endif /* CONFIG_TULIP_FIX_DAVICOM */ + +#ifdef UPDATE_SROM +static void update_srom(struct eth_device *dev, bd_t *bis) +{ + int i; + static unsigned short eeprom[0x40] = { + 0x140b, 0x6610, 0x0000, 0x0000, /* 00 */ + 0x0000, 0x0000, 0x0000, 0x0000, /* 04 */ + 0x00a3, 0x0103, 0x0000, 0x0000, /* 08 */ + 0x0000, 0x1f00, 0x0000, 0x0000, /* 0c */ + 0x0108, 0x038d, 0x0000, 0x0000, /* 10 */ + 0xe078, 0x0001, 0x0040, 0x0018, /* 14 */ + 0x0000, 0x0000, 0x0000, 0x0000, /* 18 */ + 0x0000, 0x0000, 0x0000, 0x0000, /* 1c */ + 0x0000, 0x0000, 0x0000, 0x0000, /* 20 */ + 0x0000, 0x0000, 0x0000, 0x0000, /* 24 */ + 0x0000, 0x0000, 0x0000, 0x0000, /* 28 */ + 0x0000, 0x0000, 0x0000, 0x0000, /* 2c */ + 0x0000, 0x0000, 0x0000, 0x0000, /* 30 */ + 0x0000, 0x0000, 0x0000, 0x0000, /* 34 */ + 0x0000, 0x0000, 0x0000, 0x0000, /* 38 */ + 0x0000, 0x0000, 0x0000, 0x4e07, /* 3c */ + }; + uchar enetaddr[6]; + + /* Ethernet Addr... */ + if (!eth_getenv_enetaddr("ethaddr", enetaddr)) + return; + eeprom[0x0a] = (enetaddr[1] << 8) | enetaddr[0]; + eeprom[0x0b] = (enetaddr[3] << 8) | enetaddr[2]; + eeprom[0x0c] = (enetaddr[5] << 8) | enetaddr[4]; + + for (i=0; i<0x40; i++) { + write_srom(dev, DE4X5_APROM, i, eeprom[i]); + } +} +#endif /* UPDATE_SROM */ diff --git a/sources/uboot-be550/drivers/net/designware.c b/sources/uboot-be550/drivers/net/designware.c new file mode 100644 index 00000000..04114a12 --- /dev/null +++ b/sources/uboot-be550/drivers/net/designware.c @@ -0,0 +1,676 @@ +/* + * (C) Copyright 2010 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * Designware ethernet IP driver for U-Boot + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "designware.h" + +DECLARE_GLOBAL_DATA_PTR; + +static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) +{ + struct eth_mac_regs *mac_p = bus->priv; + ulong start; + u16 miiaddr; + int timeout = CONFIG_MDIO_TIMEOUT; + + miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | + ((reg << MIIREGSHIFT) & MII_REGMSK); + + writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); + + start = get_timer(0); + while (get_timer(start) < timeout) { + if (!(readl(&mac_p->miiaddr) & MII_BUSY)) + return readl(&mac_p->miidata); + udelay(10); + }; + + return -ETIMEDOUT; +} + +static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, + u16 val) +{ + struct eth_mac_regs *mac_p = bus->priv; + ulong start; + u16 miiaddr; + int ret = -ETIMEDOUT, timeout = CONFIG_MDIO_TIMEOUT; + + writel(val, &mac_p->miidata); + miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | + ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE; + + writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); + + start = get_timer(0); + while (get_timer(start) < timeout) { + if (!(readl(&mac_p->miiaddr) & MII_BUSY)) { + ret = 0; + break; + } + udelay(10); + }; + + return ret; +} + +static int dw_mdio_init(const char *name, struct eth_mac_regs *mac_regs_p) +{ + struct mii_dev *bus = mdio_alloc(); + + if (!bus) { + printf("Failed to allocate MDIO bus\n"); + return -ENOMEM; + } + + bus->read = dw_mdio_read; + bus->write = dw_mdio_write; + snprintf(bus->name, sizeof(bus->name), name); + + bus->priv = (void *)mac_regs_p; + + return mdio_register(bus); +} + +static void tx_descs_init(struct dw_eth_dev *priv) +{ + struct eth_dma_regs *dma_p = priv->dma_regs_p; + struct dmamacdescr *desc_table_p = &priv->tx_mac_descrtable[0]; + char *txbuffs = &priv->txbuffs[0]; + struct dmamacdescr *desc_p; + u32 idx; + + for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) { + desc_p = &desc_table_p[idx]; + desc_p->dmamac_addr = &txbuffs[idx * CONFIG_ETH_BUFSIZE]; + desc_p->dmamac_next = &desc_table_p[idx + 1]; + +#if defined(CONFIG_DW_ALTDESCRIPTOR) + desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST | + DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS | + DESC_TXSTS_TXCHECKINSCTRL | + DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS); + + desc_p->txrx_status |= DESC_TXSTS_TXCHAIN; + desc_p->dmamac_cntl = 0; + desc_p->txrx_status &= ~(DESC_TXSTS_MSK | DESC_TXSTS_OWNBYDMA); +#else + desc_p->dmamac_cntl = DESC_TXCTRL_TXCHAIN; + desc_p->txrx_status = 0; +#endif + } + + /* Correcting the last pointer of the chain */ + desc_p->dmamac_next = &desc_table_p[0]; + + /* Flush all Tx buffer descriptors at once */ + flush_dcache_range((unsigned int)priv->tx_mac_descrtable, + (unsigned int)priv->tx_mac_descrtable + + sizeof(priv->tx_mac_descrtable)); + + writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr); + priv->tx_currdescnum = 0; +} + +static void rx_descs_init(struct dw_eth_dev *priv) +{ + struct eth_dma_regs *dma_p = priv->dma_regs_p; + struct dmamacdescr *desc_table_p = &priv->rx_mac_descrtable[0]; + char *rxbuffs = &priv->rxbuffs[0]; + struct dmamacdescr *desc_p; + u32 idx; + + /* Before passing buffers to GMAC we need to make sure zeros + * written there right after "priv" structure allocation were + * flushed into RAM. + * Otherwise there's a chance to get some of them flushed in RAM when + * GMAC is already pushing data to RAM via DMA. This way incoming from + * GMAC data will be corrupted. */ + flush_dcache_range((unsigned int)rxbuffs, (unsigned int)rxbuffs + + RX_TOTAL_BUFSIZE); + + for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) { + desc_p = &desc_table_p[idx]; + desc_p->dmamac_addr = &rxbuffs[idx * CONFIG_ETH_BUFSIZE]; + desc_p->dmamac_next = &desc_table_p[idx + 1]; + + desc_p->dmamac_cntl = + (MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) | + DESC_RXCTRL_RXCHAIN; + + desc_p->txrx_status = DESC_RXSTS_OWNBYDMA; + } + + /* Correcting the last pointer of the chain */ + desc_p->dmamac_next = &desc_table_p[0]; + + /* Flush all Rx buffer descriptors at once */ + flush_dcache_range((unsigned int)priv->rx_mac_descrtable, + (unsigned int)priv->rx_mac_descrtable + + sizeof(priv->rx_mac_descrtable)); + + writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr); + priv->rx_currdescnum = 0; +} + +static int _dw_write_hwaddr(struct dw_eth_dev *priv, u8 *mac_id) +{ + struct eth_mac_regs *mac_p = priv->mac_regs_p; + u32 macid_lo, macid_hi; + + macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) + + (mac_id[3] << 24); + macid_hi = mac_id[4] + (mac_id[5] << 8); + + writel(macid_hi, &mac_p->macaddr0hi); + writel(macid_lo, &mac_p->macaddr0lo); + + return 0; +} + +static void dw_adjust_link(struct eth_mac_regs *mac_p, + struct phy_device *phydev) +{ + u32 conf = readl(&mac_p->conf) | FRAMEBURSTENABLE | DISABLERXOWN; + + if (!phydev->link) { + printf("%s: No link.\n", phydev->dev->name); + return; + } + + if (phydev->speed != 1000) + conf |= MII_PORTSELECT; + + if (phydev->speed == 100) + conf |= FES_100; + + if (phydev->duplex) + conf |= FULLDPLXMODE; + + writel(conf, &mac_p->conf); + + printf("Speed: %d, %s duplex%s\n", phydev->speed, + (phydev->duplex) ? "full" : "half", + (phydev->port == PORT_FIBRE) ? ", fiber mode" : ""); +} + +static void _dw_eth_halt(struct dw_eth_dev *priv) +{ + struct eth_mac_regs *mac_p = priv->mac_regs_p; + struct eth_dma_regs *dma_p = priv->dma_regs_p; + + writel(readl(&mac_p->conf) & ~(RXENABLE | TXENABLE), &mac_p->conf); + writel(readl(&dma_p->opmode) & ~(RXSTART | TXSTART), &dma_p->opmode); + + phy_shutdown(priv->phydev); +} + +static int _dw_eth_init(struct dw_eth_dev *priv, u8 *enetaddr) +{ + struct eth_mac_regs *mac_p = priv->mac_regs_p; + struct eth_dma_regs *dma_p = priv->dma_regs_p; + unsigned int start; + int ret; + + writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode); + + start = get_timer(0); + while (readl(&dma_p->busmode) & DMAMAC_SRST) { + if (get_timer(start) >= CONFIG_MACRESET_TIMEOUT) { + printf("DMA reset timeout\n"); + return -ETIMEDOUT; + } + + mdelay(100); + }; + + /* + * Soft reset above clears HW address registers. + * So we have to set it here once again. + */ + _dw_write_hwaddr(priv, enetaddr); + + rx_descs_init(priv); + tx_descs_init(priv); + + writel(FIXEDBURST | PRIORXTX_41 | DMA_PBL, &dma_p->busmode); + +#ifndef CONFIG_DW_MAC_FORCE_THRESHOLD_MODE + writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD, + &dma_p->opmode); +#else + writel(readl(&dma_p->opmode) | FLUSHTXFIFO, + &dma_p->opmode); +#endif + + writel(readl(&dma_p->opmode) | RXSTART | TXSTART, &dma_p->opmode); + +#ifdef CONFIG_DW_AXI_BURST_LEN + writel((CONFIG_DW_AXI_BURST_LEN & 0x1FF >> 1), &dma_p->axibus); +#endif + + /* Start up the PHY */ + ret = phy_startup(priv->phydev); + if (ret) { + printf("Could not initialize PHY %s\n", + priv->phydev->dev->name); + return ret; + } + + dw_adjust_link(mac_p, priv->phydev); + + if (!priv->phydev->link) + return -EIO; + + writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf); + + return 0; +} + +static int _dw_eth_send(struct dw_eth_dev *priv, void *packet, int length) +{ + struct eth_dma_regs *dma_p = priv->dma_regs_p; + u32 desc_num = priv->tx_currdescnum; + struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num]; + uint32_t desc_start = (uint32_t)desc_p; + uint32_t desc_end = desc_start + + roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); + uint32_t data_start = (uint32_t)desc_p->dmamac_addr; + uint32_t data_end = data_start + + roundup(length, ARCH_DMA_MINALIGN); + /* + * Strictly we only need to invalidate the "txrx_status" field + * for the following check, but on some platforms we cannot + * invalidate only 4 bytes, so we flush the entire descriptor, + * which is 16 bytes in total. This is safe because the + * individual descriptors in the array are each aligned to + * ARCH_DMA_MINALIGN and padded appropriately. + */ + invalidate_dcache_range(desc_start, desc_end); + + /* Check if the descriptor is owned by CPU */ + if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) { + printf("CPU not owner of tx frame\n"); + return -EPERM; + } + + memcpy(desc_p->dmamac_addr, packet, length); + + /* Flush data to be sent */ + flush_dcache_range(data_start, data_end); + +#if defined(CONFIG_DW_ALTDESCRIPTOR) + desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST; + desc_p->dmamac_cntl |= (length << DESC_TXCTRL_SIZE1SHFT) & + DESC_TXCTRL_SIZE1MASK; + + desc_p->txrx_status &= ~(DESC_TXSTS_MSK); + desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA; +#else + desc_p->dmamac_cntl |= ((length << DESC_TXCTRL_SIZE1SHFT) & + DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST | + DESC_TXCTRL_TXFIRST; + + desc_p->txrx_status = DESC_TXSTS_OWNBYDMA; +#endif + + /* Flush modified buffer descriptor */ + flush_dcache_range(desc_start, desc_end); + + /* Test the wrap-around condition. */ + if (++desc_num >= CONFIG_TX_DESCR_NUM) + desc_num = 0; + + priv->tx_currdescnum = desc_num; + + /* Start the transmission */ + writel(POLL_DATA, &dma_p->txpolldemand); + + return 0; +} + +static int _dw_eth_recv(struct dw_eth_dev *priv, uchar **packetp) +{ + u32 status, desc_num = priv->rx_currdescnum; + struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num]; + int length = -EAGAIN; + uint32_t desc_start = (uint32_t)desc_p; + uint32_t desc_end = desc_start + + roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); + uint32_t data_start = (uint32_t)desc_p->dmamac_addr; + uint32_t data_end; + + /* Invalidate entire buffer descriptor */ + invalidate_dcache_range(desc_start, desc_end); + + status = desc_p->txrx_status; + + /* Check if the owner is the CPU */ + if (!(status & DESC_RXSTS_OWNBYDMA)) { + + length = (status & DESC_RXSTS_FRMLENMSK) >> + DESC_RXSTS_FRMLENSHFT; + + /* Invalidate received data */ + data_end = data_start + roundup(length, ARCH_DMA_MINALIGN); + invalidate_dcache_range(data_start, data_end); + *packetp = desc_p->dmamac_addr; + } + + return length; +} + +static int _dw_free_pkt(struct dw_eth_dev *priv) +{ + u32 desc_num = priv->rx_currdescnum; + struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num]; + uint32_t desc_start = (uint32_t)desc_p; + uint32_t desc_end = desc_start + + roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); + + /* + * Make the current descriptor valid again and go to + * the next one + */ + desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA; + + /* Flush only status field - others weren't changed */ + flush_dcache_range(desc_start, desc_end); + + /* Test the wrap-around condition. */ + if (++desc_num >= CONFIG_RX_DESCR_NUM) + desc_num = 0; + priv->rx_currdescnum = desc_num; + + return 0; +} + +static int dw_phy_init(struct dw_eth_dev *priv, void *dev) +{ + struct phy_device *phydev; + int mask = 0xffffffff; + +#ifdef CONFIG_PHY_ADDR + mask = 1 << CONFIG_PHY_ADDR; +#endif + + phydev = phy_find_by_mask(priv->bus, mask, priv->interface); + if (!phydev) + return -ENODEV; + + phy_connect_dev(phydev, dev); + + phydev->supported &= PHY_GBIT_FEATURES; + phydev->advertising = phydev->supported; + + priv->phydev = phydev; + phy_config(phydev); + + return 0; +} + +#ifndef CONFIG_DM_ETH +static int dw_eth_init(struct eth_device *dev, bd_t *bis) +{ + return _dw_eth_init(dev->priv, dev->enetaddr); +} + +static int dw_eth_send(struct eth_device *dev, void *packet, int length) +{ + return _dw_eth_send(dev->priv, packet, length); +} + +static int dw_eth_recv(struct eth_device *dev) +{ + uchar *packet; + int length; + + length = _dw_eth_recv(dev->priv, &packet); + if (length == -EAGAIN) + return 0; + net_process_received_packet(packet, length); + + _dw_free_pkt(dev->priv); + + return 0; +} + +static void dw_eth_halt(struct eth_device *dev) +{ + return _dw_eth_halt(dev->priv); +} + +static int dw_write_hwaddr(struct eth_device *dev) +{ + return _dw_write_hwaddr(dev->priv, dev->enetaddr); +} + +int designware_initialize(ulong base_addr, u32 interface) +{ + struct eth_device *dev; + struct dw_eth_dev *priv; + + dev = (struct eth_device *) malloc(sizeof(struct eth_device)); + if (!dev) + return -ENOMEM; + + /* + * Since the priv structure contains the descriptors which need a strict + * buswidth alignment, memalign is used to allocate memory + */ + priv = (struct dw_eth_dev *) memalign(ARCH_DMA_MINALIGN, + sizeof(struct dw_eth_dev)); + if (!priv) { + free(dev); + return -ENOMEM; + } + + memset(dev, 0, sizeof(struct eth_device)); + memset(priv, 0, sizeof(struct dw_eth_dev)); + + sprintf(dev->name, "dwmac.%lx", base_addr); + dev->iobase = (int)base_addr; + dev->priv = priv; + + priv->dev = dev; + priv->mac_regs_p = (struct eth_mac_regs *)base_addr; + priv->dma_regs_p = (struct eth_dma_regs *)(base_addr + + DW_DMA_BASE_OFFSET); + + dev->init = dw_eth_init; + dev->send = dw_eth_send; + dev->recv = dw_eth_recv; + dev->halt = dw_eth_halt; + dev->write_hwaddr = dw_write_hwaddr; + + eth_register(dev); + + priv->interface = interface; + + dw_mdio_init(dev->name, priv->mac_regs_p); + priv->bus = miiphy_get_dev_by_name(dev->name); + + return dw_phy_init(priv, dev); +} +#endif + +#ifdef CONFIG_DM_ETH +static int designware_eth_start(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + + return _dw_eth_init(dev->priv, pdata->enetaddr); +} + +static int designware_eth_send(struct udevice *dev, void *packet, int length) +{ + struct dw_eth_dev *priv = dev_get_priv(dev); + + return _dw_eth_send(priv, packet, length); +} + +static int designware_eth_recv(struct udevice *dev, int flags, uchar **packetp) +{ + struct dw_eth_dev *priv = dev_get_priv(dev); + + return _dw_eth_recv(priv, packetp); +} + +static int designware_eth_free_pkt(struct udevice *dev, uchar *packet, + int length) +{ + struct dw_eth_dev *priv = dev_get_priv(dev); + + return _dw_free_pkt(priv); +} + +static void designware_eth_stop(struct udevice *dev) +{ + struct dw_eth_dev *priv = dev_get_priv(dev); + + return _dw_eth_halt(priv); +} + +static int designware_eth_write_hwaddr(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + struct dw_eth_dev *priv = dev_get_priv(dev); + + return _dw_write_hwaddr(priv, pdata->enetaddr); +} + +static int designware_eth_bind(struct udevice *dev) +{ +#ifdef CONFIG_DM_PCI + static int num_cards; + char name[20]; + + /* Create a unique device name for PCI type devices */ + if (device_is_on_pci_bus(dev)) { + sprintf(name, "eth_designware#%u", num_cards++); + device_set_name(dev, name); + } +#endif + + return 0; +} + +static int designware_eth_probe(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + struct dw_eth_dev *priv = dev_get_priv(dev); + u32 iobase = pdata->iobase; + int ret; + +#ifdef CONFIG_DM_PCI + /* + * If we are on PCI bus, either directly attached to a PCI root port, + * or via a PCI bridge, fill in platdata before we probe the hardware. + */ + if (device_is_on_pci_bus(dev)) { + pci_dev_t bdf = pci_get_bdf(dev); + + dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase); + iobase &= PCI_BASE_ADDRESS_MEM_MASK; + iobase = pci_mem_to_phys(bdf, iobase); + + pdata->iobase = iobase; + pdata->phy_interface = PHY_INTERFACE_MODE_RMII; + } +#endif + + debug("%s, iobase=%x, priv=%p\n", __func__, iobase, priv); + priv->mac_regs_p = (struct eth_mac_regs *)iobase; + priv->dma_regs_p = (struct eth_dma_regs *)(iobase + DW_DMA_BASE_OFFSET); + priv->interface = pdata->phy_interface; + + dw_mdio_init(dev->name, priv->mac_regs_p); + priv->bus = miiphy_get_dev_by_name(dev->name); + + ret = dw_phy_init(priv, dev); + debug("%s, ret=%d\n", __func__, ret); + + return ret; +} + +static int designware_eth_remove(struct udevice *dev) +{ + struct dw_eth_dev *priv = dev_get_priv(dev); + + free(priv->phydev); + mdio_unregister(priv->bus); + mdio_free(priv->bus); + + return 0; +} + +static const struct eth_ops designware_eth_ops = { + .start = designware_eth_start, + .send = designware_eth_send, + .recv = designware_eth_recv, + .free_pkt = designware_eth_free_pkt, + .stop = designware_eth_stop, + .write_hwaddr = designware_eth_write_hwaddr, +}; + +static int designware_eth_ofdata_to_platdata(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + const char *phy_mode; + + pdata->iobase = dev_get_addr(dev); + pdata->phy_interface = -1; + phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL); + if (phy_mode) + pdata->phy_interface = phy_get_interface_by_name(phy_mode); + if (pdata->phy_interface == -1) { + debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); + return -EINVAL; + } + + return 0; +} + +static const struct udevice_id designware_eth_ids[] = { + { .compatible = "allwinner,sun7i-a20-gmac" }, + { .compatible = "altr,socfpga-stmmac" }, + { } +}; + +U_BOOT_DRIVER(eth_designware) = { + .name = "eth_designware", + .id = UCLASS_ETH, + .of_match = designware_eth_ids, + .ofdata_to_platdata = designware_eth_ofdata_to_platdata, + .bind = designware_eth_bind, + .probe = designware_eth_probe, + .remove = designware_eth_remove, + .ops = &designware_eth_ops, + .priv_auto_alloc_size = sizeof(struct dw_eth_dev), + .platdata_auto_alloc_size = sizeof(struct eth_pdata), + .flags = DM_FLAG_ALLOC_PRIV_DMA, +}; + +static struct pci_device_id supported[] = { + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_EMAC) }, + { } +}; + +U_BOOT_PCI_DEVICE(eth_designware, supported); +#endif diff --git a/sources/uboot-be550/drivers/net/designware.h b/sources/uboot-be550/drivers/net/designware.h new file mode 100644 index 00000000..4b9ec39c --- /dev/null +++ b/sources/uboot-be550/drivers/net/designware.h @@ -0,0 +1,238 @@ +/* + * (C) Copyright 2010 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _DW_ETH_H +#define _DW_ETH_H + +#define CONFIG_TX_DESCR_NUM 16 +#define CONFIG_RX_DESCR_NUM 16 +#define CONFIG_ETH_BUFSIZE 2048 +#define TX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM) +#define RX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM) + +#define CONFIG_MACRESET_TIMEOUT (3 * CONFIG_SYS_HZ) +#define CONFIG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ) + +struct eth_mac_regs { + u32 conf; /* 0x00 */ + u32 framefilt; /* 0x04 */ + u32 hashtablehigh; /* 0x08 */ + u32 hashtablelow; /* 0x0c */ + u32 miiaddr; /* 0x10 */ + u32 miidata; /* 0x14 */ + u32 flowcontrol; /* 0x18 */ + u32 vlantag; /* 0x1c */ + u32 version; /* 0x20 */ + u8 reserved_1[20]; + u32 intreg; /* 0x38 */ + u32 intmask; /* 0x3c */ + u32 macaddr0hi; /* 0x40 */ + u32 macaddr0lo; /* 0x44 */ +}; + +/* MAC configuration register definitions */ +#define FRAMEBURSTENABLE (1 << 21) +#define MII_PORTSELECT (1 << 15) +#define FES_100 (1 << 14) +#define DISABLERXOWN (1 << 13) +#define FULLDPLXMODE (1 << 11) +#define RXENABLE (1 << 2) +#define TXENABLE (1 << 3) + +/* MII address register definitions */ +#define MII_BUSY (1 << 0) +#define MII_WRITE (1 << 1) +#define MII_CLKRANGE_60_100M (0) +#define MII_CLKRANGE_100_150M (0x4) +#define MII_CLKRANGE_20_35M (0x8) +#define MII_CLKRANGE_35_60M (0xC) +#define MII_CLKRANGE_150_250M (0x10) +#define MII_CLKRANGE_250_300M (0x14) + +#define MIIADDRSHIFT (11) +#define MIIREGSHIFT (6) +#define MII_REGMSK (0x1F << 6) +#define MII_ADDRMSK (0x1F << 11) + + +struct eth_dma_regs { + u32 busmode; /* 0x00 */ + u32 txpolldemand; /* 0x04 */ + u32 rxpolldemand; /* 0x08 */ + u32 rxdesclistaddr; /* 0x0c */ + u32 txdesclistaddr; /* 0x10 */ + u32 status; /* 0x14 */ + u32 opmode; /* 0x18 */ + u32 intenable; /* 0x1c */ + u32 reserved1[2]; + u32 axibus; /* 0x28 */ + u32 reserved2[7]; + u32 currhosttxdesc; /* 0x48 */ + u32 currhostrxdesc; /* 0x4c */ + u32 currhosttxbuffaddr; /* 0x50 */ + u32 currhostrxbuffaddr; /* 0x54 */ +}; + +#define DW_DMA_BASE_OFFSET (0x1000) + +/* Default DMA Burst length */ +#ifndef CONFIG_DW_GMAC_DEFAULT_DMA_PBL +#define CONFIG_DW_GMAC_DEFAULT_DMA_PBL 8 +#endif + +/* Bus mode register definitions */ +#define FIXEDBURST (1 << 16) +#define PRIORXTX_41 (3 << 14) +#define PRIORXTX_31 (2 << 14) +#define PRIORXTX_21 (1 << 14) +#define PRIORXTX_11 (0 << 14) +#define DMA_PBL (CONFIG_DW_GMAC_DEFAULT_DMA_PBL<<8) +#define RXHIGHPRIO (1 << 1) +#define DMAMAC_SRST (1 << 0) + +/* Poll demand definitions */ +#define POLL_DATA (0xFFFFFFFF) + +/* Operation mode definitions */ +#define STOREFORWARD (1 << 21) +#define FLUSHTXFIFO (1 << 20) +#define TXSTART (1 << 13) +#define TXSECONDFRAME (1 << 2) +#define RXSTART (1 << 1) + +/* Descriptior related definitions */ +#define MAC_MAX_FRAME_SZ (1600) + +struct dmamacdescr { + u32 txrx_status; + u32 dmamac_cntl; + void *dmamac_addr; + struct dmamacdescr *dmamac_next; +} __aligned(ARCH_DMA_MINALIGN); + +/* + * txrx_status definitions + */ + +/* tx status bits definitions */ +#if defined(CONFIG_DW_ALTDESCRIPTOR) + +#define DESC_TXSTS_OWNBYDMA (1 << 31) +#define DESC_TXSTS_TXINT (1 << 30) +#define DESC_TXSTS_TXLAST (1 << 29) +#define DESC_TXSTS_TXFIRST (1 << 28) +#define DESC_TXSTS_TXCRCDIS (1 << 27) + +#define DESC_TXSTS_TXPADDIS (1 << 26) +#define DESC_TXSTS_TXCHECKINSCTRL (3 << 22) +#define DESC_TXSTS_TXRINGEND (1 << 21) +#define DESC_TXSTS_TXCHAIN (1 << 20) +#define DESC_TXSTS_MSK (0x1FFFF << 0) + +#else + +#define DESC_TXSTS_OWNBYDMA (1 << 31) +#define DESC_TXSTS_MSK (0x1FFFF << 0) + +#endif + +/* rx status bits definitions */ +#define DESC_RXSTS_OWNBYDMA (1 << 31) +#define DESC_RXSTS_DAFILTERFAIL (1 << 30) +#define DESC_RXSTS_FRMLENMSK (0x3FFF << 16) +#define DESC_RXSTS_FRMLENSHFT (16) + +#define DESC_RXSTS_ERROR (1 << 15) +#define DESC_RXSTS_RXTRUNCATED (1 << 14) +#define DESC_RXSTS_SAFILTERFAIL (1 << 13) +#define DESC_RXSTS_RXIPC_GIANTFRAME (1 << 12) +#define DESC_RXSTS_RXDAMAGED (1 << 11) +#define DESC_RXSTS_RXVLANTAG (1 << 10) +#define DESC_RXSTS_RXFIRST (1 << 9) +#define DESC_RXSTS_RXLAST (1 << 8) +#define DESC_RXSTS_RXIPC_GIANT (1 << 7) +#define DESC_RXSTS_RXCOLLISION (1 << 6) +#define DESC_RXSTS_RXFRAMEETHER (1 << 5) +#define DESC_RXSTS_RXWATCHDOG (1 << 4) +#define DESC_RXSTS_RXMIIERROR (1 << 3) +#define DESC_RXSTS_RXDRIBBLING (1 << 2) +#define DESC_RXSTS_RXCRC (1 << 1) + +/* + * dmamac_cntl definitions + */ + +/* tx control bits definitions */ +#if defined(CONFIG_DW_ALTDESCRIPTOR) + +#define DESC_TXCTRL_SIZE1MASK (0x1FFF << 0) +#define DESC_TXCTRL_SIZE1SHFT (0) +#define DESC_TXCTRL_SIZE2MASK (0x1FFF << 16) +#define DESC_TXCTRL_SIZE2SHFT (16) + +#else + +#define DESC_TXCTRL_TXINT (1 << 31) +#define DESC_TXCTRL_TXLAST (1 << 30) +#define DESC_TXCTRL_TXFIRST (1 << 29) +#define DESC_TXCTRL_TXCHECKINSCTRL (3 << 27) +#define DESC_TXCTRL_TXCRCDIS (1 << 26) +#define DESC_TXCTRL_TXRINGEND (1 << 25) +#define DESC_TXCTRL_TXCHAIN (1 << 24) + +#define DESC_TXCTRL_SIZE1MASK (0x7FF << 0) +#define DESC_TXCTRL_SIZE1SHFT (0) +#define DESC_TXCTRL_SIZE2MASK (0x7FF << 11) +#define DESC_TXCTRL_SIZE2SHFT (11) + +#endif + +/* rx control bits definitions */ +#if defined(CONFIG_DW_ALTDESCRIPTOR) + +#define DESC_RXCTRL_RXINTDIS (1 << 31) +#define DESC_RXCTRL_RXRINGEND (1 << 15) +#define DESC_RXCTRL_RXCHAIN (1 << 14) + +#define DESC_RXCTRL_SIZE1MASK (0x1FFF << 0) +#define DESC_RXCTRL_SIZE1SHFT (0) +#define DESC_RXCTRL_SIZE2MASK (0x1FFF << 16) +#define DESC_RXCTRL_SIZE2SHFT (16) + +#else + +#define DESC_RXCTRL_RXINTDIS (1 << 31) +#define DESC_RXCTRL_RXRINGEND (1 << 25) +#define DESC_RXCTRL_RXCHAIN (1 << 24) + +#define DESC_RXCTRL_SIZE1MASK (0x7FF << 0) +#define DESC_RXCTRL_SIZE1SHFT (0) +#define DESC_RXCTRL_SIZE2MASK (0x7FF << 11) +#define DESC_RXCTRL_SIZE2SHFT (11) + +#endif + +struct dw_eth_dev { + struct dmamacdescr tx_mac_descrtable[CONFIG_TX_DESCR_NUM]; + struct dmamacdescr rx_mac_descrtable[CONFIG_RX_DESCR_NUM]; + char txbuffs[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN); + char rxbuffs[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN); + + u32 interface; + u32 tx_currdescnum; + u32 rx_currdescnum; + + struct eth_mac_regs *mac_regs_p; + struct eth_dma_regs *dma_regs_p; +#ifndef CONFIG_DM_ETH + struct eth_device *dev; +#endif + struct phy_device *phydev; + struct mii_dev *bus; +}; + +#endif diff --git a/sources/uboot-be550/drivers/net/dm9000x.c b/sources/uboot-be550/drivers/net/dm9000x.c new file mode 100644 index 00000000..3c41cec3 --- /dev/null +++ b/sources/uboot-be550/drivers/net/dm9000x.c @@ -0,0 +1,638 @@ +/* + dm9000.c: Version 1.2 12/15/2003 + + A Davicom DM9000 ISA NIC fast Ethernet driver for Linux. + Copyright (C) 1997 Sten Wang + + * SPDX-License-Identifier: GPL-2.0+ + + (C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved. + +V0.11 06/20/2001 REG_0A bit3=1, default enable BP with DA match + 06/22/2001 Support DM9801 progrmming + E3: R25 = ((R24 + NF) & 0x00ff) | 0xf000 + E4: R25 = ((R24 + NF) & 0x00ff) | 0xc200 + R17 = (R17 & 0xfff0) | NF + 3 + E5: R25 = ((R24 + NF - 3) & 0x00ff) | 0xc200 + R17 = (R17 & 0xfff0) | NF + +v1.00 modify by simon 2001.9.5 + change for kernel 2.4.x + +v1.1 11/09/2001 fix force mode bug + +v1.2 03/18/2003 Weilun Huang : + Fixed phy reset. + Added tx/rx 32 bit mode. + Cleaned up for kernel merge. + +-------------------------------------- + + 12/15/2003 Initial port to u-boot by + Sascha Hauer + + 06/03/2008 Remy Bohmer + - Fixed the driver to work with DM9000A. + (check on ISR receive status bit before reading the + FIFO as described in DM9000 programming guide and + application notes) + - Added autodetect of databus width. + - Made debug code compile again. + - Adapt eth_send such that it matches the DM9000* + application notes. Needed to make it work properly + for DM9000A. + - Adapted reset procedure to match DM9000 application + notes (i.e. double reset) + - some minor code cleanups + These changes are tested with DM9000{A,EP,E} together + with a 200MHz Atmel AT91SAM9261 core + +TODO: external MII is not functional, only internal at the moment. +*/ + +#include +#include +#include +#include +#include + +#include "dm9000x.h" + +/* Board/System/Debug information/definition ---------------- */ + +/* #define CONFIG_DM9000_DEBUG */ + +#ifdef CONFIG_DM9000_DEBUG +#define DM9000_DBG(fmt,args...) printf(fmt, ##args) +#define DM9000_DMP_PACKET(func,packet,length) \ + do { \ + int i; \ + printf("%s: length: %d\n", func, length); \ + for (i = 0; i < length; i++) { \ + if (i % 8 == 0) \ + printf("\n%s: %02x: ", func, i); \ + printf("%02x ", ((unsigned char *) packet)[i]); \ + } printf("\n"); \ + } while(0) +#else +#define DM9000_DBG(fmt,args...) +#define DM9000_DMP_PACKET(func,packet,length) +#endif + +/* Structure/enum declaration ------------------------------- */ +typedef struct board_info { + u32 runt_length_counter; /* counter: RX length < 64byte */ + u32 long_length_counter; /* counter: RX length > 1514byte */ + u32 reset_counter; /* counter: RESET */ + u32 reset_tx_timeout; /* RESET caused by TX Timeout */ + u32 reset_rx_status; /* RESET caused by RX Statsus wrong */ + u16 tx_pkt_cnt; + u16 queue_start_addr; + u16 dbug_cnt; + u8 phy_addr; + u8 device_wait_reset; /* device state */ + unsigned char srom[128]; + void (*outblk)(volatile void *data_ptr, int count); + void (*inblk)(void *data_ptr, int count); + void (*rx_status)(u16 *RxStatus, u16 *RxLen); + struct eth_device netdev; +} board_info_t; +static board_info_t dm9000_info; + + +/* function declaration ------------------------------------- */ +static int dm9000_probe(void); +static u16 dm9000_phy_read(int); +static void dm9000_phy_write(int, u16); +static u8 DM9000_ior(int); +static void DM9000_iow(int reg, u8 value); + +/* DM9000 network board routine ---------------------------- */ +#ifndef CONFIG_DM9000_BYTE_SWAPPED +#define DM9000_outb(d,r) writeb(d, (volatile u8 *)(r)) +#define DM9000_outw(d,r) writew(d, (volatile u16 *)(r)) +#define DM9000_outl(d,r) writel(d, (volatile u32 *)(r)) +#define DM9000_inb(r) readb((volatile u8 *)(r)) +#define DM9000_inw(r) readw((volatile u16 *)(r)) +#define DM9000_inl(r) readl((volatile u32 *)(r)) +#else +#define DM9000_outb(d, r) __raw_writeb(d, r) +#define DM9000_outw(d, r) __raw_writew(d, r) +#define DM9000_outl(d, r) __raw_writel(d, r) +#define DM9000_inb(r) __raw_readb(r) +#define DM9000_inw(r) __raw_readw(r) +#define DM9000_inl(r) __raw_readl(r) +#endif + +#ifdef CONFIG_DM9000_DEBUG +static void +dump_regs(void) +{ + DM9000_DBG("\n"); + DM9000_DBG("NCR (0x00): %02x\n", DM9000_ior(0)); + DM9000_DBG("NSR (0x01): %02x\n", DM9000_ior(1)); + DM9000_DBG("TCR (0x02): %02x\n", DM9000_ior(2)); + DM9000_DBG("TSRI (0x03): %02x\n", DM9000_ior(3)); + DM9000_DBG("TSRII (0x04): %02x\n", DM9000_ior(4)); + DM9000_DBG("RCR (0x05): %02x\n", DM9000_ior(5)); + DM9000_DBG("RSR (0x06): %02x\n", DM9000_ior(6)); + DM9000_DBG("ISR (0xFE): %02x\n", DM9000_ior(DM9000_ISR)); + DM9000_DBG("\n"); +} +#endif + +static void dm9000_outblk_8bit(volatile void *data_ptr, int count) +{ + int i; + for (i = 0; i < count; i++) + DM9000_outb((((u8 *) data_ptr)[i] & 0xff), DM9000_DATA); +} + +static void dm9000_outblk_16bit(volatile void *data_ptr, int count) +{ + int i; + u32 tmplen = (count + 1) / 2; + + for (i = 0; i < tmplen; i++) + DM9000_outw(((u16 *) data_ptr)[i], DM9000_DATA); +} +static void dm9000_outblk_32bit(volatile void *data_ptr, int count) +{ + int i; + u32 tmplen = (count + 3) / 4; + + for (i = 0; i < tmplen; i++) + DM9000_outl(((u32 *) data_ptr)[i], DM9000_DATA); +} + +static void dm9000_inblk_8bit(void *data_ptr, int count) +{ + int i; + for (i = 0; i < count; i++) + ((u8 *) data_ptr)[i] = DM9000_inb(DM9000_DATA); +} + +static void dm9000_inblk_16bit(void *data_ptr, int count) +{ + int i; + u32 tmplen = (count + 1) / 2; + + for (i = 0; i < tmplen; i++) + ((u16 *) data_ptr)[i] = DM9000_inw(DM9000_DATA); +} +static void dm9000_inblk_32bit(void *data_ptr, int count) +{ + int i; + u32 tmplen = (count + 3) / 4; + + for (i = 0; i < tmplen; i++) + ((u32 *) data_ptr)[i] = DM9000_inl(DM9000_DATA); +} + +static void dm9000_rx_status_32bit(u16 *RxStatus, u16 *RxLen) +{ + u32 tmpdata; + + DM9000_outb(DM9000_MRCMD, DM9000_IO); + + tmpdata = DM9000_inl(DM9000_DATA); + *RxStatus = __le16_to_cpu(tmpdata); + *RxLen = __le16_to_cpu(tmpdata >> 16); +} + +static void dm9000_rx_status_16bit(u16 *RxStatus, u16 *RxLen) +{ + DM9000_outb(DM9000_MRCMD, DM9000_IO); + + *RxStatus = __le16_to_cpu(DM9000_inw(DM9000_DATA)); + *RxLen = __le16_to_cpu(DM9000_inw(DM9000_DATA)); +} + +static void dm9000_rx_status_8bit(u16 *RxStatus, u16 *RxLen) +{ + DM9000_outb(DM9000_MRCMD, DM9000_IO); + + *RxStatus = + __le16_to_cpu(DM9000_inb(DM9000_DATA) + + (DM9000_inb(DM9000_DATA) << 8)); + *RxLen = + __le16_to_cpu(DM9000_inb(DM9000_DATA) + + (DM9000_inb(DM9000_DATA) << 8)); +} + +/* + Search DM9000 board, allocate space and register it +*/ +int +dm9000_probe(void) +{ + u32 id_val; + id_val = DM9000_ior(DM9000_VIDL); + id_val |= DM9000_ior(DM9000_VIDH) << 8; + id_val |= DM9000_ior(DM9000_PIDL) << 16; + id_val |= DM9000_ior(DM9000_PIDH) << 24; + if (id_val == DM9000_ID) { + printf("dm9000 i/o: 0x%x, id: 0x%x \n", CONFIG_DM9000_BASE, + id_val); + return 0; + } else { + printf("dm9000 not found at 0x%08x id: 0x%08x\n", + CONFIG_DM9000_BASE, id_val); + return -1; + } +} + +/* General Purpose dm9000 reset routine */ +static void +dm9000_reset(void) +{ + DM9000_DBG("resetting DM9000\n"); + + /* Reset DM9000, + see DM9000 Application Notes V1.22 Jun 11, 2004 page 29 */ + + /* DEBUG: Make all GPIO0 outputs, all others inputs */ + DM9000_iow(DM9000_GPCR, GPCR_GPIO0_OUT); + /* Step 1: Power internal PHY by writing 0 to GPIO0 pin */ + DM9000_iow(DM9000_GPR, 0); + /* Step 2: Software reset */ + DM9000_iow(DM9000_NCR, (NCR_LBK_INT_MAC | NCR_RST)); + + do { + DM9000_DBG("resetting the DM9000, 1st reset\n"); + udelay(25); /* Wait at least 20 us */ + } while (DM9000_ior(DM9000_NCR) & 1); + + DM9000_iow(DM9000_NCR, 0); + DM9000_iow(DM9000_NCR, (NCR_LBK_INT_MAC | NCR_RST)); /* Issue a second reset */ + + do { + DM9000_DBG("resetting the DM9000, 2nd reset\n"); + udelay(25); /* Wait at least 20 us */ + } while (DM9000_ior(DM9000_NCR) & 1); + + /* Check whether the ethernet controller is present */ + if ((DM9000_ior(DM9000_PIDL) != 0x0) || + (DM9000_ior(DM9000_PIDH) != 0x90)) + printf("ERROR: resetting DM9000 -> not responding\n"); +} + +/* Initialize dm9000 board +*/ +static int dm9000_init(struct eth_device *dev, bd_t *bd) +{ + int i, oft, lnk; + u8 io_mode; + struct board_info *db = &dm9000_info; + + DM9000_DBG("%s\n", __func__); + + /* RESET device */ + dm9000_reset(); + + if (dm9000_probe() < 0) + return -1; + + /* Auto-detect 8/16/32 bit mode, ISR Bit 6+7 indicate bus width */ + io_mode = DM9000_ior(DM9000_ISR) >> 6; + + switch (io_mode) { + case 0x0: /* 16-bit mode */ + printf("DM9000: running in 16 bit mode\n"); + db->outblk = dm9000_outblk_16bit; + db->inblk = dm9000_inblk_16bit; + db->rx_status = dm9000_rx_status_16bit; + break; + case 0x01: /* 32-bit mode */ + printf("DM9000: running in 32 bit mode\n"); + db->outblk = dm9000_outblk_32bit; + db->inblk = dm9000_inblk_32bit; + db->rx_status = dm9000_rx_status_32bit; + break; + case 0x02: /* 8 bit mode */ + printf("DM9000: running in 8 bit mode\n"); + db->outblk = dm9000_outblk_8bit; + db->inblk = dm9000_inblk_8bit; + db->rx_status = dm9000_rx_status_8bit; + break; + default: + /* Assume 8 bit mode, will probably not work anyway */ + printf("DM9000: Undefined IO-mode:0x%x\n", io_mode); + db->outblk = dm9000_outblk_8bit; + db->inblk = dm9000_inblk_8bit; + db->rx_status = dm9000_rx_status_8bit; + break; + } + + /* Program operating register, only internal phy supported */ + DM9000_iow(DM9000_NCR, 0x0); + /* TX Polling clear */ + DM9000_iow(DM9000_TCR, 0); + /* Less 3Kb, 200us */ + DM9000_iow(DM9000_BPTR, BPTR_BPHW(3) | BPTR_JPT_600US); + /* Flow Control : High/Low Water */ + DM9000_iow(DM9000_FCTR, FCTR_HWOT(3) | FCTR_LWOT(8)); + /* SH FIXME: This looks strange! Flow Control */ + DM9000_iow(DM9000_FCR, 0x0); + /* Special Mode */ + DM9000_iow(DM9000_SMCR, 0); + /* clear TX status */ + DM9000_iow(DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END); + /* Clear interrupt status */ + DM9000_iow(DM9000_ISR, ISR_ROOS | ISR_ROS | ISR_PTS | ISR_PRS); + + printf("MAC: %pM\n", dev->enetaddr); + if (!is_valid_ethaddr(dev->enetaddr)) { + printf("WARNING: Bad MAC address (uninitialized EEPROM?)\n"); + } + + /* fill device MAC address registers */ + for (i = 0, oft = DM9000_PAR; i < 6; i++, oft++) + DM9000_iow(oft, dev->enetaddr[i]); + for (i = 0, oft = 0x16; i < 8; i++, oft++) + DM9000_iow(oft, 0xff); + + /* read back mac, just to be sure */ + for (i = 0, oft = 0x10; i < 6; i++, oft++) + DM9000_DBG("%02x:", DM9000_ior(oft)); + DM9000_DBG("\n"); + + /* Activate DM9000 */ + /* RX enable */ + DM9000_iow(DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN); + /* Enable TX/RX interrupt mask */ + DM9000_iow(DM9000_IMR, IMR_PAR); + + i = 0; + while (!(dm9000_phy_read(1) & 0x20)) { /* autonegation complete bit */ + udelay(1000); + i++; + if (i == 10000) { + printf("could not establish link\n"); + return 0; + } + } + + /* see what we've got */ + lnk = dm9000_phy_read(17) >> 12; + printf("operating at "); + switch (lnk) { + case 1: + printf("10M half duplex "); + break; + case 2: + printf("10M full duplex "); + break; + case 4: + printf("100M half duplex "); + break; + case 8: + printf("100M full duplex "); + break; + default: + printf("unknown: %d ", lnk); + break; + } + printf("mode\n"); + return 0; +} + +/* + Hardware start transmission. + Send a packet to media from the upper layer. +*/ +static int dm9000_send(struct eth_device *netdev, void *packet, int length) +{ + int tmo; + struct board_info *db = &dm9000_info; + + DM9000_DMP_PACKET(__func__ , packet, length); + + DM9000_iow(DM9000_ISR, IMR_PTM); /* Clear Tx bit in ISR */ + + /* Move data to DM9000 TX RAM */ + DM9000_outb(DM9000_MWCMD, DM9000_IO); /* Prepare for TX-data */ + + /* push the data to the TX-fifo */ + (db->outblk)(packet, length); + + /* Set TX length to DM9000 */ + DM9000_iow(DM9000_TXPLL, length & 0xff); + DM9000_iow(DM9000_TXPLH, (length >> 8) & 0xff); + + /* Issue TX polling command */ + DM9000_iow(DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */ + + /* wait for end of transmission */ + tmo = get_timer(0) + 5 * CONFIG_SYS_HZ; + while ( !(DM9000_ior(DM9000_NSR) & (NSR_TX1END | NSR_TX2END)) || + !(DM9000_ior(DM9000_ISR) & IMR_PTM) ) { + if (get_timer(0) >= tmo) { + printf("transmission timeout\n"); + break; + } + } + DM9000_iow(DM9000_ISR, IMR_PTM); /* Clear Tx bit in ISR */ + + DM9000_DBG("transmit done\n\n"); + return 0; +} + +/* + Stop the interface. + The interface is stopped when it is brought. +*/ +static void dm9000_halt(struct eth_device *netdev) +{ + DM9000_DBG("%s\n", __func__); + + /* RESET devie */ + dm9000_phy_write(0, 0x8000); /* PHY RESET */ + DM9000_iow(DM9000_GPR, 0x01); /* Power-Down PHY */ + DM9000_iow(DM9000_IMR, 0x80); /* Disable all interrupt */ + DM9000_iow(DM9000_RCR, 0x00); /* Disable RX */ +} + +/* + Received a packet and pass to upper layer +*/ +static int dm9000_rx(struct eth_device *netdev) +{ + u8 rxbyte; + u8 *rdptr = (u8 *)net_rx_packets[0]; + u16 RxStatus, RxLen = 0; + struct board_info *db = &dm9000_info; + + /* Check packet ready or not, we must check + the ISR status first for DM9000A */ + if (!(DM9000_ior(DM9000_ISR) & 0x01)) /* Rx-ISR bit must be set. */ + return 0; + + DM9000_iow(DM9000_ISR, 0x01); /* clear PR status latched in bit 0 */ + + /* There is _at least_ 1 package in the fifo, read them all */ + for (;;) { + DM9000_ior(DM9000_MRCMDX); /* Dummy read */ + + /* Get most updated data, + only look at bits 0:1, See application notes DM9000 */ + rxbyte = DM9000_inb(DM9000_DATA) & 0x03; + + /* Status check: this byte must be 0 or 1 */ + if (rxbyte > DM9000_PKT_RDY) { + DM9000_iow(DM9000_RCR, 0x00); /* Stop Device */ + DM9000_iow(DM9000_ISR, 0x80); /* Stop INT request */ + printf("DM9000 error: status check fail: 0x%x\n", + rxbyte); + return 0; + } + + if (rxbyte != DM9000_PKT_RDY) + return 0; /* No packet received, ignore */ + + DM9000_DBG("receiving packet\n"); + + /* A packet ready now & Get status/length */ + (db->rx_status)(&RxStatus, &RxLen); + + DM9000_DBG("rx status: 0x%04x rx len: %d\n", RxStatus, RxLen); + + /* Move data from DM9000 */ + /* Read received packet from RX SRAM */ + (db->inblk)(rdptr, RxLen); + + if ((RxStatus & 0xbf00) || (RxLen < 0x40) + || (RxLen > DM9000_PKT_MAX)) { + if (RxStatus & 0x100) { + printf("rx fifo error\n"); + } + if (RxStatus & 0x200) { + printf("rx crc error\n"); + } + if (RxStatus & 0x8000) { + printf("rx length error\n"); + } + if (RxLen > DM9000_PKT_MAX) { + printf("rx length too big\n"); + dm9000_reset(); + } + } else { + DM9000_DMP_PACKET(__func__ , rdptr, RxLen); + + DM9000_DBG("passing packet to upper layer\n"); + net_process_received_packet(net_rx_packets[0], RxLen); + } + } + return 0; +} + +/* + Read a word data from SROM +*/ +#if !defined(CONFIG_DM9000_NO_SROM) +void dm9000_read_srom_word(int offset, u8 *to) +{ + DM9000_iow(DM9000_EPAR, offset); + DM9000_iow(DM9000_EPCR, 0x4); + udelay(8000); + DM9000_iow(DM9000_EPCR, 0x0); + to[0] = DM9000_ior(DM9000_EPDRL); + to[1] = DM9000_ior(DM9000_EPDRH); +} + +void dm9000_write_srom_word(int offset, u16 val) +{ + DM9000_iow(DM9000_EPAR, offset); + DM9000_iow(DM9000_EPDRH, ((val >> 8) & 0xff)); + DM9000_iow(DM9000_EPDRL, (val & 0xff)); + DM9000_iow(DM9000_EPCR, 0x12); + udelay(8000); + DM9000_iow(DM9000_EPCR, 0); +} +#endif + +static void dm9000_get_enetaddr(struct eth_device *dev) +{ +#if !defined(CONFIG_DM9000_NO_SROM) + int i; + for (i = 0; i < 3; i++) + dm9000_read_srom_word(i, dev->enetaddr + (2 * i)); +#endif +} + +/* + Read a byte from I/O port +*/ +static u8 +DM9000_ior(int reg) +{ + DM9000_outb(reg, DM9000_IO); + return DM9000_inb(DM9000_DATA); +} + +/* + Write a byte to I/O port +*/ +static void +DM9000_iow(int reg, u8 value) +{ + DM9000_outb(reg, DM9000_IO); + DM9000_outb(value, DM9000_DATA); +} + +/* + Read a word from phyxcer +*/ +static u16 +dm9000_phy_read(int reg) +{ + u16 val; + + /* Fill the phyxcer register into REG_0C */ + DM9000_iow(DM9000_EPAR, DM9000_PHY | reg); + DM9000_iow(DM9000_EPCR, 0xc); /* Issue phyxcer read command */ + udelay(100); /* Wait read complete */ + DM9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer read command */ + val = (DM9000_ior(DM9000_EPDRH) << 8) | DM9000_ior(DM9000_EPDRL); + + /* The read data keeps on REG_0D & REG_0E */ + DM9000_DBG("dm9000_phy_read(0x%x): 0x%x\n", reg, val); + return val; +} + +/* + Write a word to phyxcer +*/ +static void +dm9000_phy_write(int reg, u16 value) +{ + + /* Fill the phyxcer register into REG_0C */ + DM9000_iow(DM9000_EPAR, DM9000_PHY | reg); + + /* Fill the written data into REG_0D & REG_0E */ + DM9000_iow(DM9000_EPDRL, (value & 0xff)); + DM9000_iow(DM9000_EPDRH, ((value >> 8) & 0xff)); + DM9000_iow(DM9000_EPCR, 0xa); /* Issue phyxcer write command */ + udelay(500); /* Wait write complete */ + DM9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer write command */ + DM9000_DBG("dm9000_phy_write(reg:0x%x, value:0x%x)\n", reg, value); +} + +int dm9000_initialize(bd_t *bis) +{ + struct eth_device *dev = &(dm9000_info.netdev); + + /* Load MAC address from EEPROM */ + dm9000_get_enetaddr(dev); + + dev->init = dm9000_init; + dev->halt = dm9000_halt; + dev->send = dm9000_send; + dev->recv = dm9000_rx; + sprintf(dev->name, "dm9000"); + + eth_register(dev); + + return 0; +} diff --git a/sources/uboot-be550/drivers/net/dm9000x.h b/sources/uboot-be550/drivers/net/dm9000x.h new file mode 100644 index 00000000..0d123e2e --- /dev/null +++ b/sources/uboot-be550/drivers/net/dm9000x.h @@ -0,0 +1,140 @@ +/* + * dm9000 Ethernet + */ + +#ifdef CONFIG_DRIVER_DM9000 + +#define DM9000_ID 0x90000A46 +#define DM9000_PKT_MAX 1536 /* Received packet max size */ +#define DM9000_PKT_RDY 0x01 /* Packet ready to receive */ + +/* although the registers are 16 bit, they are 32-bit aligned. + */ + +#define DM9000_NCR 0x00 +#define DM9000_NSR 0x01 +#define DM9000_TCR 0x02 +#define DM9000_TSR1 0x03 +#define DM9000_TSR2 0x04 +#define DM9000_RCR 0x05 +#define DM9000_RSR 0x06 +#define DM9000_ROCR 0x07 +#define DM9000_BPTR 0x08 +#define DM9000_FCTR 0x09 +#define DM9000_FCR 0x0A +#define DM9000_EPCR 0x0B +#define DM9000_EPAR 0x0C +#define DM9000_EPDRL 0x0D +#define DM9000_EPDRH 0x0E +#define DM9000_WCR 0x0F + +#define DM9000_PAR 0x10 +#define DM9000_MAR 0x16 + +#define DM9000_GPCR 0x1e +#define DM9000_GPR 0x1f +#define DM9000_TRPAL 0x22 +#define DM9000_TRPAH 0x23 +#define DM9000_RWPAL 0x24 +#define DM9000_RWPAH 0x25 + +#define DM9000_VIDL 0x28 +#define DM9000_VIDH 0x29 +#define DM9000_PIDL 0x2A +#define DM9000_PIDH 0x2B + +#define DM9000_CHIPR 0x2C +#define DM9000_SMCR 0x2F + +#define DM9000_PHY 0x40 /* PHY address 0x01 */ + +#define DM9000_MRCMDX 0xF0 +#define DM9000_MRCMD 0xF2 +#define DM9000_MRRL 0xF4 +#define DM9000_MRRH 0xF5 +#define DM9000_MWCMDX 0xF6 +#define DM9000_MWCMD 0xF8 +#define DM9000_MWRL 0xFA +#define DM9000_MWRH 0xFB +#define DM9000_TXPLL 0xFC +#define DM9000_TXPLH 0xFD +#define DM9000_ISR 0xFE +#define DM9000_IMR 0xFF + +#define NCR_EXT_PHY (1<<7) +#define NCR_WAKEEN (1<<6) +#define NCR_FCOL (1<<4) +#define NCR_FDX (1<<3) +#define NCR_LBK (3<<1) +#define NCR_LBK_INT_MAC (1<<1) +#define NCR_LBK_INT_PHY (2<<1) +#define NCR_RST (1<<0) + +#define NSR_SPEED (1<<7) +#define NSR_LINKST (1<<6) +#define NSR_WAKEST (1<<5) +#define NSR_TX2END (1<<3) +#define NSR_TX1END (1<<2) +#define NSR_RXOV (1<<1) + +#define TCR_TJDIS (1<<6) +#define TCR_EXCECM (1<<5) +#define TCR_PAD_DIS2 (1<<4) +#define TCR_CRC_DIS2 (1<<3) +#define TCR_PAD_DIS1 (1<<2) +#define TCR_CRC_DIS1 (1<<1) +#define TCR_TXREQ (1<<0) + +#define TSR_TJTO (1<<7) +#define TSR_LC (1<<6) +#define TSR_NC (1<<5) +#define TSR_LCOL (1<<4) +#define TSR_COL (1<<3) +#define TSR_EC (1<<2) + +#define RCR_WTDIS (1<<6) +#define RCR_DIS_LONG (1<<5) +#define RCR_DIS_CRC (1<<4) +#define RCR_ALL (1<<3) +#define RCR_RUNT (1<<2) +#define RCR_PRMSC (1<<1) +#define RCR_RXEN (1<<0) + +#define RSR_RF (1<<7) +#define RSR_MF (1<<6) +#define RSR_LCS (1<<5) +#define RSR_RWTO (1<<4) +#define RSR_PLE (1<<3) +#define RSR_AE (1<<2) +#define RSR_CE (1<<1) +#define RSR_FOE (1<<0) + +#define EPCR_EPOS_PHY (1<<3) +#define EPCR_EPOS_EE (0<<3) +#define EPCR_ERPRR (1<<2) +#define EPCR_ERPRW (1<<1) +#define EPCR_ERRE (1<<0) + +#define FCTR_HWOT(ot) (( ot & 0xf ) << 4 ) +#define FCTR_LWOT(ot) ( ot & 0xf ) + +#define BPTR_BPHW(x) ((x) << 4) +#define BPTR_JPT_200US (0x07) +#define BPTR_JPT_600US (0x0f) + +#define IMR_PAR (1<<7) +#define IMR_ROOM (1<<3) +#define IMR_ROM (1<<2) +#define IMR_PTM (1<<1) +#define IMR_PRM (1<<0) + +#define ISR_ROOS (1<<3) +#define ISR_ROS (1<<2) +#define ISR_PTS (1<<1) +#define ISR_PRS (1<<0) + +#define GPCR_GPIO0_OUT (1<<0) + +#define GPR_PHY_PWROFF (1<<0) + +#endif diff --git a/sources/uboot-be550/drivers/net/dnet.c b/sources/uboot-be550/drivers/net/dnet.c new file mode 100644 index 00000000..933d1fc2 --- /dev/null +++ b/sources/uboot-be550/drivers/net/dnet.c @@ -0,0 +1,393 @@ +/* + * Dave Ethernet Controller driver + * + * Copyright (C) 2008 Dave S.r.l. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include + +#ifndef CONFIG_DNET_AUTONEG_TIMEOUT +#define CONFIG_DNET_AUTONEG_TIMEOUT 5000000 /* default value */ +#endif + +#include +#include +#include + +#include +#include +#include + +#include "dnet.h" + +struct dnet_device { + struct dnet_registers *regs; + const struct device *dev; + struct eth_device netdev; + unsigned short phy_addr; +}; + +/* get struct dnet_device from given struct netdev */ +#define to_dnet(_nd) container_of(_nd, struct dnet_device, netdev) + +/* function for reading internal MAC register */ +u16 dnet_readw_mac(struct dnet_device *dnet, u16 reg) +{ + u16 data_read; + + /* issue a read */ + writel(reg, &dnet->regs->MACREG_ADDR); + + /* since a read/write op to the MAC is very slow, + * we must wait before reading the data */ + udelay(1); + + /* read data read from the MAC register */ + data_read = readl(&dnet->regs->MACREG_DATA); + + /* all done */ + return data_read; +} + +/* function for writing internal MAC register */ +void dnet_writew_mac(struct dnet_device *dnet, u16 reg, u16 val) +{ + /* load data to write */ + writel(val, &dnet->regs->MACREG_DATA); + + /* issue a write */ + writel(reg | DNET_INTERNAL_WRITE, &dnet->regs->MACREG_ADDR); + + /* since a read/write op to the MAC is very slow, + * we must wait before exiting */ + udelay(1); +} + +static void dnet_mdio_write(struct dnet_device *dnet, u8 reg, u16 value) +{ + u16 tmp; + + debug(DRIVERNAME "dnet_mdio_write %02x:%02x <- %04x\n", + dnet->phy_addr, reg, value); + + while (!(dnet_readw_mac(dnet, DNET_INTERNAL_GMII_MNG_CTL_REG) & + DNET_INTERNAL_GMII_MNG_CMD_FIN)) + ; + + /* prepare for a write operation */ + tmp = (1 << 13); + + /* only 5 bits allowed for register offset */ + reg &= 0x1f; + + /* prepare reg_value for a write */ + tmp |= (dnet->phy_addr << 8); + tmp |= reg; + + /* write data to write first */ + dnet_writew_mac(dnet, DNET_INTERNAL_GMII_MNG_DAT_REG, value); + + /* write control word */ + dnet_writew_mac(dnet, DNET_INTERNAL_GMII_MNG_CTL_REG, tmp); + + while (!(dnet_readw_mac(dnet, DNET_INTERNAL_GMII_MNG_CTL_REG) & + DNET_INTERNAL_GMII_MNG_CMD_FIN)) + ; +} + +static u16 dnet_mdio_read(struct dnet_device *dnet, u8 reg) +{ + u16 value; + + while (!(dnet_readw_mac(dnet, DNET_INTERNAL_GMII_MNG_CTL_REG) & + DNET_INTERNAL_GMII_MNG_CMD_FIN)) + ; + + /* only 5 bits allowed for register offset*/ + reg &= 0x1f; + + /* prepare reg_value for a read */ + value = (dnet->phy_addr << 8); + value |= reg; + + /* write control word */ + dnet_writew_mac(dnet, DNET_INTERNAL_GMII_MNG_CTL_REG, value); + + /* wait for end of transfer */ + while (!(dnet_readw_mac(dnet, DNET_INTERNAL_GMII_MNG_CTL_REG) & + DNET_INTERNAL_GMII_MNG_CMD_FIN)) + ; + + value = dnet_readw_mac(dnet, DNET_INTERNAL_GMII_MNG_DAT_REG); + + debug(DRIVERNAME "dnet_mdio_read %02x:%02x <- %04x\n", + dnet->phy_addr, reg, value); + + return value; +} + +static int dnet_send(struct eth_device *netdev, void *packet, int length) +{ + struct dnet_device *dnet = to_dnet(netdev); + int i, wrsz; + unsigned int *bufp; + unsigned int tx_cmd; + + debug(DRIVERNAME "[%s] Sending %u bytes\n", __func__, length); + + bufp = (unsigned int *) (((u32)packet) & 0xFFFFFFFC); + wrsz = (u32)length + 3; + wrsz += ((u32)packet) & 0x3; + wrsz >>= 2; + tx_cmd = ((((unsigned int)(packet)) & 0x03) << 16) | (u32)length; + + /* check if there is enough room for the current frame */ + if (wrsz < (DNET_FIFO_SIZE - readl(&dnet->regs->TX_FIFO_WCNT))) { + for (i = 0; i < wrsz; i++) + writel(*bufp++, &dnet->regs->TX_DATA_FIFO); + /* + * inform MAC that a packet's written and ready + * to be shipped out + */ + writel(tx_cmd, &dnet->regs->TX_LEN_FIFO); + } else { + printf(DRIVERNAME "No free space (actual %d, required %d " + "(words))\n", DNET_FIFO_SIZE - + readl(&dnet->regs->TX_FIFO_WCNT), wrsz); + } + + /* No one cares anyway */ + return 0; +} + + +static int dnet_recv(struct eth_device *netdev) +{ + struct dnet_device *dnet = to_dnet(netdev); + unsigned int *data_ptr; + int pkt_len, poll, i; + u32 cmd_word; + + debug("Waiting for pkt (polling)\n"); + poll = 50; + while ((readl(&dnet->regs->RX_FIFO_WCNT) >> 16) == 0) { + udelay(10); /* wait 10 usec */ + if (--poll == 0) + return 0; /* no pkt available */ + } + + cmd_word = readl(&dnet->regs->RX_LEN_FIFO); + pkt_len = cmd_word & 0xFFFF; + + debug("Got pkt with size %d bytes\n", pkt_len); + + if (cmd_word & 0xDF180000) + printf("%s packet receive error %x\n", __func__, cmd_word); + + data_ptr = (unsigned int *)net_rx_packets[0]; + + for (i = 0; i < (pkt_len + 3) >> 2; i++) + *data_ptr++ = readl(&dnet->regs->RX_DATA_FIFO); + + /* ok + 5 ?? */ + net_process_received_packet(net_rx_packets[0], pkt_len + 5); + + return 0; +} + +static void dnet_set_hwaddr(struct eth_device *netdev) +{ + struct dnet_device *dnet = to_dnet(netdev); + u16 tmp; + + tmp = get_unaligned_be16(netdev->enetaddr); + dnet_writew_mac(dnet, DNET_INTERNAL_MAC_ADDR_0_REG, tmp); + tmp = get_unaligned_be16(&netdev->enetaddr[2]); + dnet_writew_mac(dnet, DNET_INTERNAL_MAC_ADDR_1_REG, tmp); + tmp = get_unaligned_be16(&netdev->enetaddr[4]); + dnet_writew_mac(dnet, DNET_INTERNAL_MAC_ADDR_2_REG, tmp); +} + +static void dnet_phy_reset(struct dnet_device *dnet) +{ + struct eth_device *netdev = &dnet->netdev; + int i; + u16 status, adv; + + adv = ADVERTISE_CSMA | ADVERTISE_ALL; + dnet_mdio_write(dnet, MII_ADVERTISE, adv); + printf("%s: Starting autonegotiation...\n", netdev->name); + dnet_mdio_write(dnet, MII_BMCR, (BMCR_ANENABLE + | BMCR_ANRESTART)); + + for (i = 0; i < CONFIG_DNET_AUTONEG_TIMEOUT / 100; i++) { + status = dnet_mdio_read(dnet, MII_BMSR); + if (status & BMSR_ANEGCOMPLETE) + break; + udelay(100); + } + + if (status & BMSR_ANEGCOMPLETE) + printf("%s: Autonegotiation complete\n", netdev->name); + else + printf("%s: Autonegotiation timed out (status=0x%04x)\n", + netdev->name, status); +} + +static int dnet_phy_init(struct dnet_device *dnet) +{ + struct eth_device *netdev = &dnet->netdev; + u16 phy_id, status, adv, lpa; + int media, speed, duplex; + int i; + u32 ctl_reg; + + /* Find a PHY */ + for (i = 0; i < 32; i++) { + dnet->phy_addr = i; + phy_id = dnet_mdio_read(dnet, MII_PHYSID1); + if (phy_id != 0xffff) { + /* ok we found it */ + printf("Found PHY at address %d PHYID (%04x:%04x)\n", + i, phy_id, + dnet_mdio_read(dnet, MII_PHYSID2)); + break; + } + } + + /* Check if the PHY is up to snuff... */ + phy_id = dnet_mdio_read(dnet, MII_PHYSID1); + if (phy_id == 0xffff) { + printf("%s: No PHY present\n", netdev->name); + return -1; + } + + status = dnet_mdio_read(dnet, MII_BMSR); + if (!(status & BMSR_LSTATUS)) { + /* Try to re-negotiate if we don't have link already. */ + dnet_phy_reset(dnet); + + for (i = 0; i < CONFIG_DNET_AUTONEG_TIMEOUT / 100; i++) { + status = dnet_mdio_read(dnet, MII_BMSR); + if (status & BMSR_LSTATUS) + break; + udelay(100); + } + } + + if (!(status & BMSR_LSTATUS)) { + printf("%s: link down (status: 0x%04x)\n", + netdev->name, status); + return -1; + } else { + adv = dnet_mdio_read(dnet, MII_ADVERTISE); + lpa = dnet_mdio_read(dnet, MII_LPA); + media = mii_nway_result(lpa & adv); + speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) + ? 1 : 0); + duplex = (media & ADVERTISE_FULL) ? 1 : 0; + /* 1000BaseT ethernet is not supported */ + printf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n", + netdev->name, + speed ? "100" : "10", + duplex ? "full" : "half", + lpa); + + ctl_reg = dnet_readw_mac(dnet, DNET_INTERNAL_RXTX_CONTROL_REG); + + if (duplex) + ctl_reg &= ~(DNET_INTERNAL_RXTX_CONTROL_ENABLEHALFDUP); + else + ctl_reg |= DNET_INTERNAL_RXTX_CONTROL_ENABLEHALFDUP; + + dnet_writew_mac(dnet, DNET_INTERNAL_RXTX_CONTROL_REG, ctl_reg); + + return 0; + } +} + +static int dnet_init(struct eth_device *netdev, bd_t *bd) +{ + struct dnet_device *dnet = to_dnet(netdev); + u32 config; + + /* + * dnet_halt should have been called at some point before now, + * so we'll assume the controller is idle. + */ + + /* set hardware address */ + dnet_set_hwaddr(netdev); + + if (dnet_phy_init(dnet) < 0) + return -1; + + /* flush rx/tx fifos */ + writel(DNET_SYS_CTL_RXFIFOFLUSH | DNET_SYS_CTL_TXFIFOFLUSH, + &dnet->regs->SYS_CTL); + udelay(1000); + writel(0, &dnet->regs->SYS_CTL); + + config = dnet_readw_mac(dnet, DNET_INTERNAL_RXTX_CONTROL_REG); + + config |= DNET_INTERNAL_RXTX_CONTROL_RXPAUSE | + DNET_INTERNAL_RXTX_CONTROL_RXBROADCAST | + DNET_INTERNAL_RXTX_CONTROL_DROPCONTROL | + DNET_INTERNAL_RXTX_CONTROL_DISCFXFCS; + + dnet_writew_mac(dnet, DNET_INTERNAL_RXTX_CONTROL_REG, config); + + /* Enable TX and RX */ + dnet_writew_mac(dnet, DNET_INTERNAL_MODE_REG, + DNET_INTERNAL_MODE_RXEN | DNET_INTERNAL_MODE_TXEN); + + return 0; +} + +static void dnet_halt(struct eth_device *netdev) +{ + struct dnet_device *dnet = to_dnet(netdev); + + /* Disable TX and RX */ + dnet_writew_mac(dnet, DNET_INTERNAL_MODE_REG, 0); +} + +int dnet_eth_initialize(int id, void *regs, unsigned int phy_addr) +{ + struct dnet_device *dnet; + struct eth_device *netdev; + unsigned int dev_capa; + + dnet = malloc(sizeof(struct dnet_device)); + if (!dnet) { + printf("Error: Failed to allocate memory for DNET%d\n", id); + return -1; + } + memset(dnet, 0, sizeof(struct dnet_device)); + + netdev = &dnet->netdev; + + dnet->regs = (struct dnet_registers *)regs; + dnet->phy_addr = phy_addr; + + sprintf(netdev->name, "dnet%d", id); + netdev->init = dnet_init; + netdev->halt = dnet_halt; + netdev->send = dnet_send; + netdev->recv = dnet_recv; + + dev_capa = readl(&dnet->regs->VERCAPS) & 0xFFFF; + debug("%s: has %smdio, %sirq, %sgigabit, %sdma \n", netdev->name, + (dev_capa & DNET_HAS_MDIO) ? "" : "no ", + (dev_capa & DNET_HAS_IRQ) ? "" : "no ", + (dev_capa & DNET_HAS_GIGABIT) ? "" : "no ", + (dev_capa & DNET_HAS_DMA) ? "" : "no "); + + eth_register(netdev); + + return 0; +} diff --git a/sources/uboot-be550/drivers/net/dnet.h b/sources/uboot-be550/drivers/net/dnet.h new file mode 100644 index 00000000..fdb4fd2d --- /dev/null +++ b/sources/uboot-be550/drivers/net/dnet.h @@ -0,0 +1,166 @@ +/* + * Dave Ethernet Controller driver + * + * Copyright (C) 2008 Dave S.r.l. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __DRIVERS_DNET_H__ +#define __DRIVERS_DNET_H__ + +#define DRIVERNAME "dnet" + +struct dnet_registers { + /* ALL DNET FIFO REGISTERS */ + u32 RX_LEN_FIFO; + u32 RX_DATA_FIFO; + u32 TX_LEN_FIFO; + u32 TX_DATA_FIFO; + u32 pad1[0x3c]; + /* ALL DNET CONTROL/STATUS REGISTERS */ + u32 VERCAPS; + u32 INTR_SRC; + u32 INTR_ENB; + u32 RX_STATUS; + u32 TX_STATUS; + u32 RX_FRAMES_CNT; + u32 TX_FRAMES_CNT; + u32 RX_FIFO_TH; + u32 TX_FIFO_TH; + u32 SYS_CTL; + u32 PAUSE_TMR; + u32 RX_FIFO_WCNT; + u32 TX_FIFO_WCNT; + u32 pad2[0x33]; + /* ALL DNET MAC REGISTERS */ + u32 MACREG_DATA; /* Mac-Reg Data */ + u32 MACREG_ADDR; /* Mac-Reg Addr */ + u32 pad3[0x3e]; + /* ALL DNET RX STATISTICS COUNTERS */ + u32 RX_PKT_IGNR_CNT; + u32 RX_LEN_CHK_ERR_CNT; + u32 RX_LNG_FRM_CNT; + u32 RX_SHRT_FRM_CNT; + u32 RX_IPG_VIOL_CNT; + u32 RX_CRC_ERR_CNT; + u32 RX_OK_PKT_CNT; + u32 RX_CTL_FRM_CNT; + u32 RX_PAUSE_FRM_CNT; + u32 RX_MULTICAST_CNT; + u32 RX_BROADCAST_CNT; + u32 RX_VLAN_TAG_CNT; + u32 RX_PRE_SHRINK_CNT; + u32 RX_DRIB_NIB_CNT; + u32 RX_UNSUP_OPCD_CNT; + u32 RX_BYTE_CNT; + u32 pad4[0x30]; + /* DNET TX STATISTICS COUNTERS */ + u32 TX_UNICAST_CNT; + u32 TX_PAUSE_FRM_CNT; + u32 TX_MULTICAST_CNT; + u32 TX_BRDCAST_CNT; + u32 TX_VLAN_TAG_CNT; + u32 TX_BAD_FCS_CNT; + u32 TX_JUMBO_CNT; + u32 TX_BYTE_CNT; +}; + +/* SOME INTERNAL MAC-CORE REGISTER */ +#define DNET_INTERNAL_MODE_REG 0x0 +#define DNET_INTERNAL_RXTX_CONTROL_REG 0x2 +#define DNET_INTERNAL_MAX_PKT_SIZE_REG 0x4 +#define DNET_INTERNAL_IGP_REG 0x8 +#define DNET_INTERNAL_MAC_ADDR_0_REG 0xa +#define DNET_INTERNAL_MAC_ADDR_1_REG 0xc +#define DNET_INTERNAL_MAC_ADDR_2_REG 0xe +#define DNET_INTERNAL_TX_RX_STS_REG 0x12 +#define DNET_INTERNAL_GMII_MNG_CTL_REG 0x14 +#define DNET_INTERNAL_GMII_MNG_DAT_REG 0x16 + +#define DNET_INTERNAL_GMII_MNG_CMD_FIN (1 << 14) + +#define DNET_INTERNAL_WRITE (1 << 31) + +/* MAC-CORE REGISTER FIELDS */ + +/* MAC-CORE MODE REGISTER FIELDS */ +#define DNET_INTERNAL_MODE_GBITEN (1 << 0) +#define DNET_INTERNAL_MODE_FCEN (1 << 1) +#define DNET_INTERNAL_MODE_RXEN (1 << 2) +#define DNET_INTERNAL_MODE_TXEN (1 << 3) + +/* MAC-CORE RXTX CONTROL REGISTER FIELDS */ +#define DNET_INTERNAL_RXTX_CONTROL_RXSHORTFRAME (1 << 8) +#define DNET_INTERNAL_RXTX_CONTROL_RXBROADCAST (1 << 7) +#define DNET_INTERNAL_RXTX_CONTROL_RXMULTICAST (1 << 4) +#define DNET_INTERNAL_RXTX_CONTROL_RXPAUSE (1 << 3) +#define DNET_INTERNAL_RXTX_CONTROL_DISTXFCS (1 << 2) +#define DNET_INTERNAL_RXTX_CONTROL_DISCFXFCS (1 << 1) +#define DNET_INTERNAL_RXTX_CONTROL_ENPROMISC (1 << 0) +#define DNET_INTERNAL_RXTX_CONTROL_DROPCONTROL (1 << 6) +#define DNET_INTERNAL_RXTX_CONTROL_ENABLEHALFDUP (1 << 5) + +/* SYSTEM CONTROL REGISTER FIELDS */ +#define DNET_SYS_CTL_IGNORENEXTPKT (1 << 0) +#define DNET_SYS_CTL_SENDPAUSE (1 << 2) +#define DNET_SYS_CTL_RXFIFOFLUSH (1 << 3) +#define DNET_SYS_CTL_TXFIFOFLUSH (1 << 4) + +/* TX STATUS REGISTER FIELDS */ +#define DNET_TX_STATUS_FIFO_ALMOST_EMPTY (1 << 2) +#define DNET_TX_STATUS_FIFO_ALMOST_FULL (1 << 1) + +/* INTERRUPT SOURCE REGISTER FIELDS */ +#define DNET_INTR_SRC_TX_PKTSENT (1 << 0) +#define DNET_INTR_SRC_TX_FIFOAF (1 << 1) +#define DNET_INTR_SRC_TX_FIFOAE (1 << 2) +#define DNET_INTR_SRC_TX_DISCFRM (1 << 3) +#define DNET_INTR_SRC_TX_FIFOFULL (1 << 4) +#define DNET_INTR_SRC_RX_CMDFIFOAF (1 << 8) +#define DNET_INTR_SRC_RX_CMDFIFOFF (1 << 9) +#define DNET_INTR_SRC_RX_DATAFIFOFF (1 << 10) +#define DNET_INTR_SRC_TX_SUMMARY (1 << 16) +#define DNET_INTR_SRC_RX_SUMMARY (1 << 17) +#define DNET_INTR_SRC_PHY (1 << 19) + +/* INTERRUPT ENABLE REGISTER FIELDS */ +#define DNET_INTR_ENB_TX_PKTSENT (1 << 0) +#define DNET_INTR_ENB_TX_FIFOAF (1 << 1) +#define DNET_INTR_ENB_TX_FIFOAE (1 << 2) +#define DNET_INTR_ENB_TX_DISCFRM (1 << 3) +#define DNET_INTR_ENB_TX_FIFOFULL (1 << 4) +#define DNET_INTR_ENB_RX_PKTRDY (1 << 8) +#define DNET_INTR_ENB_RX_FIFOAF (1 << 9) +#define DNET_INTR_ENB_RX_FIFOERR (1 << 10) +#define DNET_INTR_ENB_RX_ERROR (1 << 11) +#define DNET_INTR_ENB_RX_FIFOFULL (1 << 12) +#define DNET_INTR_ENB_RX_FIFOAE (1 << 13) +#define DNET_INTR_ENB_TX_SUMMARY (1 << 16) +#define DNET_INTR_ENB_RX_SUMMARY (1 << 17) +#define DNET_INTR_ENB_GLOBAL_ENABLE (1 << 18) + +/* + * Capabilities. Used by the driver to know the capabilities that + * the ethernet controller inside the FPGA have. + */ + +#define DNET_HAS_MDIO (1 << 0) +#define DNET_HAS_IRQ (1 << 1) +#define DNET_HAS_GIGABIT (1 << 2) +#define DNET_HAS_DMA (1 << 3) + +#define DNET_HAS_MII (1 << 4) /* or GMII */ +#define DNET_HAS_RMII (1 << 5) /* or RGMII */ + +#define DNET_CAPS_MASK 0xFFFF + +#define DNET_FIFO_SIZE 2048 /* 2K x 32 bit */ +#define DNET_FIFO_TX_DATA_AF_TH (DNET_FIFO_SIZE - 384) /* 384 = 1536 / 4 */ +#define DNET_FIFO_TX_DATA_AE_TH (384) + +#define DNET_FIFO_RX_CMD_AF_TH (1 << 16) /* just one frame inside the FIFO */ + +#endif diff --git a/sources/uboot-be550/drivers/net/e1000.c b/sources/uboot-be550/drivers/net/e1000.c new file mode 100644 index 00000000..6124bf0a --- /dev/null +++ b/sources/uboot-be550/drivers/net/e1000.c @@ -0,0 +1,5681 @@ +/************************************************************************** +Intel Pro 1000 for ppcboot/das-u-boot +Drivers are port from Intel's Linux driver e1000-4.3.15 +and from Etherboot pro 1000 driver by mrakes at vivato dot net +tested on both gig copper and gig fiber boards +***************************************************************************/ +/******************************************************************************* + + + Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved. + + * SPDX-License-Identifier: GPL-2.0+ + + Contact Information: + Linux NICS + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 + +*******************************************************************************/ +/* + * Copyright (C) Archway Digital Solutions. + * + * written by Chrsitopher Li or + * 2/9/2002 + * + * Copyright (C) Linux Networx. + * Massive upgrade to work with the new intel gigabit NICs. + * + * + * Copyright 2011 Freescale Semiconductor, Inc. + */ + +#include +#include +#include +#include +#include +#include "e1000.h" + +#define TOUT_LOOP 100000 + +#define virt_to_bus(devno, v) pci_virt_to_mem(devno, (void *) (v)) +#define bus_to_phys(devno, a) pci_mem_to_phys(devno, a) + +#define E1000_DEFAULT_PCI_PBA 0x00000030 +#define E1000_DEFAULT_PCIE_PBA 0x000a0026 + +/* NIC specific static variables go here */ + +/* Intel i210 needs the DMA descriptor rings aligned to 128b */ +#define E1000_BUFFER_ALIGN 128 + +/* + * TODO(sjg@chromium.org): Even with driver model we share these buffers. + * Concurrent receiving on multiple active Ethernet devices will not work. + * Normally U-Boot does not support this anyway. To fix it in this driver, + * move these buffers and the tx/rx pointers to struct e1000_hw. + */ +DEFINE_ALIGN_BUFFER(struct e1000_tx_desc, tx_base, 16, E1000_BUFFER_ALIGN); +DEFINE_ALIGN_BUFFER(struct e1000_rx_desc, rx_base, 16, E1000_BUFFER_ALIGN); +DEFINE_ALIGN_BUFFER(unsigned char, packet, 4096, E1000_BUFFER_ALIGN); + +static int tx_tail; +static int rx_tail, rx_last; +#ifdef CONFIG_DM_ETH +static int num_cards; /* Number of E1000 devices seen so far */ +#endif + +static struct pci_device_id e1000_supported[] = { + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82542) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_FIBER) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_COPPER) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_COPPER) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_FIBER) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_COPPER) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_LOM) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_COPPER) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545GM_COPPER) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_COPPER) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_COPPER) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541GI_LF) }, + /* E1000 PCIe card */ + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_COPPER) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_FIBER) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571PT_QUAD_COPPER) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_FIBER) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER_LOWPROFILE) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_DUAL) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_QUAD) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_COPPER) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_FIBER) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_SERDES) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E_IAMT) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573L) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82574L) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_QUAD_COPPER_KSP3) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_DPT) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_SPT) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_SPT) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_COPPER) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_1000BASEKX) }, + + {} +}; + +/* Function forward declarations */ +static int e1000_setup_link(struct e1000_hw *hw); +static int e1000_setup_fiber_link(struct e1000_hw *hw); +static int e1000_setup_copper_link(struct e1000_hw *hw); +static int e1000_phy_setup_autoneg(struct e1000_hw *hw); +static void e1000_config_collision_dist(struct e1000_hw *hw); +static int e1000_config_mac_to_phy(struct e1000_hw *hw); +static int e1000_config_fc_after_link_up(struct e1000_hw *hw); +static int e1000_check_for_link(struct e1000_hw *hw); +static int e1000_wait_autoneg(struct e1000_hw *hw); +static int e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed, + uint16_t * duplex); +static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, + uint16_t * phy_data); +static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, + uint16_t phy_data); +static int32_t e1000_phy_hw_reset(struct e1000_hw *hw); +static int e1000_phy_reset(struct e1000_hw *hw); +static int e1000_detect_gig_phy(struct e1000_hw *hw); +static void e1000_set_media_type(struct e1000_hw *hw); + +static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask); +static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask); +static int32_t e1000_check_phy_reset_block(struct e1000_hw *hw); + +#ifndef CONFIG_E1000_NO_NVM +static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw); +static int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset, + uint16_t words, + uint16_t *data); +/****************************************************************************** + * Raises the EEPROM's clock input. + * + * hw - Struct containing variables accessed by shared code + * eecd - EECD's current value + *****************************************************************************/ +void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t * eecd) +{ + /* Raise the clock input to the EEPROM (by setting the SK bit), and then + * wait 50 microseconds. + */ + *eecd = *eecd | E1000_EECD_SK; + E1000_WRITE_REG(hw, EECD, *eecd); + E1000_WRITE_FLUSH(hw); + udelay(50); +} + +/****************************************************************************** + * Lowers the EEPROM's clock input. + * + * hw - Struct containing variables accessed by shared code + * eecd - EECD's current value + *****************************************************************************/ +void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t * eecd) +{ + /* Lower the clock input to the EEPROM (by clearing the SK bit), and then + * wait 50 microseconds. + */ + *eecd = *eecd & ~E1000_EECD_SK; + E1000_WRITE_REG(hw, EECD, *eecd); + E1000_WRITE_FLUSH(hw); + udelay(50); +} + +/****************************************************************************** + * Shift data bits out to the EEPROM. + * + * hw - Struct containing variables accessed by shared code + * data - data to send to the EEPROM + * count - number of bits to shift out + *****************************************************************************/ +static void +e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, uint16_t count) +{ + uint32_t eecd; + uint32_t mask; + + /* We need to shift "count" bits out to the EEPROM. So, value in the + * "data" parameter will be shifted out to the EEPROM one bit at a time. + * In order to do this, "data" must be broken down into bits. + */ + mask = 0x01 << (count - 1); + eecd = E1000_READ_REG(hw, EECD); + eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); + do { + /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1", + * and then raising and then lowering the clock (the SK bit controls + * the clock input to the EEPROM). A "0" is shifted out to the EEPROM + * by setting "DI" to "0" and then raising and then lowering the clock. + */ + eecd &= ~E1000_EECD_DI; + + if (data & mask) + eecd |= E1000_EECD_DI; + + E1000_WRITE_REG(hw, EECD, eecd); + E1000_WRITE_FLUSH(hw); + + udelay(50); + + e1000_raise_ee_clk(hw, &eecd); + e1000_lower_ee_clk(hw, &eecd); + + mask = mask >> 1; + + } while (mask); + + /* We leave the "DI" bit set to "0" when we leave this routine. */ + eecd &= ~E1000_EECD_DI; + E1000_WRITE_REG(hw, EECD, eecd); +} + +/****************************************************************************** + * Shift data bits in from the EEPROM + * + * hw - Struct containing variables accessed by shared code + *****************************************************************************/ +static uint16_t +e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count) +{ + uint32_t eecd; + uint32_t i; + uint16_t data; + + /* In order to read a register from the EEPROM, we need to shift 'count' + * bits in from the EEPROM. Bits are "shifted in" by raising the clock + * input to the EEPROM (setting the SK bit), and then reading the + * value of the "DO" bit. During this "shifting in" process the + * "DI" bit should always be clear. + */ + + eecd = E1000_READ_REG(hw, EECD); + + eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); + data = 0; + + for (i = 0; i < count; i++) { + data = data << 1; + e1000_raise_ee_clk(hw, &eecd); + + eecd = E1000_READ_REG(hw, EECD); + + eecd &= ~(E1000_EECD_DI); + if (eecd & E1000_EECD_DO) + data |= 1; + + e1000_lower_ee_clk(hw, &eecd); + } + + return data; +} + +/****************************************************************************** + * Returns EEPROM to a "standby" state + * + * hw - Struct containing variables accessed by shared code + *****************************************************************************/ +void e1000_standby_eeprom(struct e1000_hw *hw) +{ + struct e1000_eeprom_info *eeprom = &hw->eeprom; + uint32_t eecd; + + eecd = E1000_READ_REG(hw, EECD); + + if (eeprom->type == e1000_eeprom_microwire) { + eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); + E1000_WRITE_REG(hw, EECD, eecd); + E1000_WRITE_FLUSH(hw); + udelay(eeprom->delay_usec); + + /* Clock high */ + eecd |= E1000_EECD_SK; + E1000_WRITE_REG(hw, EECD, eecd); + E1000_WRITE_FLUSH(hw); + udelay(eeprom->delay_usec); + + /* Select EEPROM */ + eecd |= E1000_EECD_CS; + E1000_WRITE_REG(hw, EECD, eecd); + E1000_WRITE_FLUSH(hw); + udelay(eeprom->delay_usec); + + /* Clock low */ + eecd &= ~E1000_EECD_SK; + E1000_WRITE_REG(hw, EECD, eecd); + E1000_WRITE_FLUSH(hw); + udelay(eeprom->delay_usec); + } else if (eeprom->type == e1000_eeprom_spi) { + /* Toggle CS to flush commands */ + eecd |= E1000_EECD_CS; + E1000_WRITE_REG(hw, EECD, eecd); + E1000_WRITE_FLUSH(hw); + udelay(eeprom->delay_usec); + eecd &= ~E1000_EECD_CS; + E1000_WRITE_REG(hw, EECD, eecd); + E1000_WRITE_FLUSH(hw); + udelay(eeprom->delay_usec); + } +} + +/*************************************************************************** +* Description: Determines if the onboard NVM is FLASH or EEPROM. +* +* hw - Struct containing variables accessed by shared code +****************************************************************************/ +static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw) +{ + uint32_t eecd = 0; + + DEBUGFUNC(); + + if (hw->mac_type == e1000_ich8lan) + return false; + + if (hw->mac_type == e1000_82573 || hw->mac_type == e1000_82574) { + eecd = E1000_READ_REG(hw, EECD); + + /* Isolate bits 15 & 16 */ + eecd = ((eecd >> 15) & 0x03); + + /* If both bits are set, device is Flash type */ + if (eecd == 0x03) + return false; + } + return true; +} + +/****************************************************************************** + * Prepares EEPROM for access + * + * hw - Struct containing variables accessed by shared code + * + * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This + * function should be called before issuing a command to the EEPROM. + *****************************************************************************/ +int32_t e1000_acquire_eeprom(struct e1000_hw *hw) +{ + struct e1000_eeprom_info *eeprom = &hw->eeprom; + uint32_t eecd, i = 0; + + DEBUGFUNC(); + + if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM)) + return -E1000_ERR_SWFW_SYNC; + eecd = E1000_READ_REG(hw, EECD); + + if (hw->mac_type != e1000_82573 && hw->mac_type != e1000_82574) { + /* Request EEPROM Access */ + if (hw->mac_type > e1000_82544) { + eecd |= E1000_EECD_REQ; + E1000_WRITE_REG(hw, EECD, eecd); + eecd = E1000_READ_REG(hw, EECD); + while ((!(eecd & E1000_EECD_GNT)) && + (i < E1000_EEPROM_GRANT_ATTEMPTS)) { + i++; + udelay(5); + eecd = E1000_READ_REG(hw, EECD); + } + if (!(eecd & E1000_EECD_GNT)) { + eecd &= ~E1000_EECD_REQ; + E1000_WRITE_REG(hw, EECD, eecd); + DEBUGOUT("Could not acquire EEPROM grant\n"); + return -E1000_ERR_EEPROM; + } + } + } + + /* Setup EEPROM for Read/Write */ + + if (eeprom->type == e1000_eeprom_microwire) { + /* Clear SK and DI */ + eecd &= ~(E1000_EECD_DI | E1000_EECD_SK); + E1000_WRITE_REG(hw, EECD, eecd); + + /* Set CS */ + eecd |= E1000_EECD_CS; + E1000_WRITE_REG(hw, EECD, eecd); + } else if (eeprom->type == e1000_eeprom_spi) { + /* Clear SK and CS */ + eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); + E1000_WRITE_REG(hw, EECD, eecd); + udelay(1); + } + + return E1000_SUCCESS; +} + +/****************************************************************************** + * Sets up eeprom variables in the hw struct. Must be called after mac_type + * is configured. Additionally, if this is ICH8, the flash controller GbE + * registers must be mapped, or this will crash. + * + * hw - Struct containing variables accessed by shared code + *****************************************************************************/ +static int32_t e1000_init_eeprom_params(struct e1000_hw *hw) +{ + struct e1000_eeprom_info *eeprom = &hw->eeprom; + uint32_t eecd; + int32_t ret_val = E1000_SUCCESS; + uint16_t eeprom_size; + + if (hw->mac_type == e1000_igb) + eecd = E1000_READ_REG(hw, I210_EECD); + else + eecd = E1000_READ_REG(hw, EECD); + + DEBUGFUNC(); + + switch (hw->mac_type) { + case e1000_82542_rev2_0: + case e1000_82542_rev2_1: + case e1000_82543: + case e1000_82544: + eeprom->type = e1000_eeprom_microwire; + eeprom->word_size = 64; + eeprom->opcode_bits = 3; + eeprom->address_bits = 6; + eeprom->delay_usec = 50; + eeprom->use_eerd = false; + eeprom->use_eewr = false; + break; + case e1000_82540: + case e1000_82545: + case e1000_82545_rev_3: + case e1000_82546: + case e1000_82546_rev_3: + eeprom->type = e1000_eeprom_microwire; + eeprom->opcode_bits = 3; + eeprom->delay_usec = 50; + if (eecd & E1000_EECD_SIZE) { + eeprom->word_size = 256; + eeprom->address_bits = 8; + } else { + eeprom->word_size = 64; + eeprom->address_bits = 6; + } + eeprom->use_eerd = false; + eeprom->use_eewr = false; + break; + case e1000_82541: + case e1000_82541_rev_2: + case e1000_82547: + case e1000_82547_rev_2: + if (eecd & E1000_EECD_TYPE) { + eeprom->type = e1000_eeprom_spi; + eeprom->opcode_bits = 8; + eeprom->delay_usec = 1; + if (eecd & E1000_EECD_ADDR_BITS) { + eeprom->page_size = 32; + eeprom->address_bits = 16; + } else { + eeprom->page_size = 8; + eeprom->address_bits = 8; + } + } else { + eeprom->type = e1000_eeprom_microwire; + eeprom->opcode_bits = 3; + eeprom->delay_usec = 50; + if (eecd & E1000_EECD_ADDR_BITS) { + eeprom->word_size = 256; + eeprom->address_bits = 8; + } else { + eeprom->word_size = 64; + eeprom->address_bits = 6; + } + } + eeprom->use_eerd = false; + eeprom->use_eewr = false; + break; + case e1000_82571: + case e1000_82572: + eeprom->type = e1000_eeprom_spi; + eeprom->opcode_bits = 8; + eeprom->delay_usec = 1; + if (eecd & E1000_EECD_ADDR_BITS) { + eeprom->page_size = 32; + eeprom->address_bits = 16; + } else { + eeprom->page_size = 8; + eeprom->address_bits = 8; + } + eeprom->use_eerd = false; + eeprom->use_eewr = false; + break; + case e1000_82573: + case e1000_82574: + eeprom->type = e1000_eeprom_spi; + eeprom->opcode_bits = 8; + eeprom->delay_usec = 1; + if (eecd & E1000_EECD_ADDR_BITS) { + eeprom->page_size = 32; + eeprom->address_bits = 16; + } else { + eeprom->page_size = 8; + eeprom->address_bits = 8; + } + if (e1000_is_onboard_nvm_eeprom(hw) == false) { + eeprom->use_eerd = true; + eeprom->use_eewr = true; + + eeprom->type = e1000_eeprom_flash; + eeprom->word_size = 2048; + + /* Ensure that the Autonomous FLASH update bit is cleared due to + * Flash update issue on parts which use a FLASH for NVM. */ + eecd &= ~E1000_EECD_AUPDEN; + E1000_WRITE_REG(hw, EECD, eecd); + } + break; + case e1000_80003es2lan: + eeprom->type = e1000_eeprom_spi; + eeprom->opcode_bits = 8; + eeprom->delay_usec = 1; + if (eecd & E1000_EECD_ADDR_BITS) { + eeprom->page_size = 32; + eeprom->address_bits = 16; + } else { + eeprom->page_size = 8; + eeprom->address_bits = 8; + } + eeprom->use_eerd = true; + eeprom->use_eewr = false; + break; + case e1000_igb: + /* i210 has 4k of iNVM mapped as EEPROM */ + eeprom->type = e1000_eeprom_invm; + eeprom->opcode_bits = 8; + eeprom->delay_usec = 1; + eeprom->page_size = 32; + eeprom->address_bits = 16; + eeprom->use_eerd = true; + eeprom->use_eewr = false; + break; + + /* ich8lan does not support currently. if needed, please + * add corresponding code and functions. + */ +#if 0 + case e1000_ich8lan: + { + int32_t i = 0; + + eeprom->type = e1000_eeprom_ich8; + eeprom->use_eerd = false; + eeprom->use_eewr = false; + eeprom->word_size = E1000_SHADOW_RAM_WORDS; + uint32_t flash_size = E1000_READ_ICH_FLASH_REG(hw, + ICH_FLASH_GFPREG); + /* Zero the shadow RAM structure. But don't load it from NVM + * so as to save time for driver init */ + if (hw->eeprom_shadow_ram != NULL) { + for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { + hw->eeprom_shadow_ram[i].modified = false; + hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF; + } + } + + hw->flash_base_addr = (flash_size & ICH_GFPREG_BASE_MASK) * + ICH_FLASH_SECTOR_SIZE; + + hw->flash_bank_size = ((flash_size >> 16) + & ICH_GFPREG_BASE_MASK) + 1; + hw->flash_bank_size -= (flash_size & ICH_GFPREG_BASE_MASK); + + hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE; + + hw->flash_bank_size /= 2 * sizeof(uint16_t); + break; + } +#endif + default: + break; + } + + if (eeprom->type == e1000_eeprom_spi || + eeprom->type == e1000_eeprom_invm) { + /* eeprom_size will be an enum [0..8] that maps + * to eeprom sizes 128B to + * 32KB (incremented by powers of 2). + */ + if (hw->mac_type <= e1000_82547_rev_2) { + /* Set to default value for initial eeprom read. */ + eeprom->word_size = 64; + ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, + &eeprom_size); + if (ret_val) + return ret_val; + eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) + >> EEPROM_SIZE_SHIFT; + /* 256B eeprom size was not supported in earlier + * hardware, so we bump eeprom_size up one to + * ensure that "1" (which maps to 256B) is never + * the result used in the shifting logic below. */ + if (eeprom_size) + eeprom_size++; + } else { + eeprom_size = (uint16_t)((eecd & + E1000_EECD_SIZE_EX_MASK) >> + E1000_EECD_SIZE_EX_SHIFT); + } + + eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT); + } + return ret_val; +} + +/****************************************************************************** + * Polls the status bit (bit 1) of the EERD to determine when the read is done. + * + * hw - Struct containing variables accessed by shared code + *****************************************************************************/ +static int32_t +e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd) +{ + uint32_t attempts = 100000; + uint32_t i, reg = 0; + int32_t done = E1000_ERR_EEPROM; + + for (i = 0; i < attempts; i++) { + if (eerd == E1000_EEPROM_POLL_READ) { + if (hw->mac_type == e1000_igb) + reg = E1000_READ_REG(hw, I210_EERD); + else + reg = E1000_READ_REG(hw, EERD); + } else { + if (hw->mac_type == e1000_igb) + reg = E1000_READ_REG(hw, I210_EEWR); + else + reg = E1000_READ_REG(hw, EEWR); + } + + if (reg & E1000_EEPROM_RW_REG_DONE) { + done = E1000_SUCCESS; + break; + } + udelay(5); + } + + return done; +} + +/****************************************************************************** + * Reads a 16 bit word from the EEPROM using the EERD register. + * + * hw - Struct containing variables accessed by shared code + * offset - offset of word in the EEPROM to read + * data - word read from the EEPROM + * words - number of words to read + *****************************************************************************/ +static int32_t +e1000_read_eeprom_eerd(struct e1000_hw *hw, + uint16_t offset, + uint16_t words, + uint16_t *data) +{ + uint32_t i, eerd = 0; + int32_t error = 0; + + for (i = 0; i < words; i++) { + eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) + + E1000_EEPROM_RW_REG_START; + + if (hw->mac_type == e1000_igb) + E1000_WRITE_REG(hw, I210_EERD, eerd); + else + E1000_WRITE_REG(hw, EERD, eerd); + + error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ); + + if (error) + break; + + if (hw->mac_type == e1000_igb) { + data[i] = (E1000_READ_REG(hw, I210_EERD) >> + E1000_EEPROM_RW_REG_DATA); + } else { + data[i] = (E1000_READ_REG(hw, EERD) >> + E1000_EEPROM_RW_REG_DATA); + } + + } + + return error; +} + +void e1000_release_eeprom(struct e1000_hw *hw) +{ + uint32_t eecd; + + DEBUGFUNC(); + + eecd = E1000_READ_REG(hw, EECD); + + if (hw->eeprom.type == e1000_eeprom_spi) { + eecd |= E1000_EECD_CS; /* Pull CS high */ + eecd &= ~E1000_EECD_SK; /* Lower SCK */ + + E1000_WRITE_REG(hw, EECD, eecd); + + udelay(hw->eeprom.delay_usec); + } else if (hw->eeprom.type == e1000_eeprom_microwire) { + /* cleanup eeprom */ + + /* CS on Microwire is active-high */ + eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); + + E1000_WRITE_REG(hw, EECD, eecd); + + /* Rising edge of clock */ + eecd |= E1000_EECD_SK; + E1000_WRITE_REG(hw, EECD, eecd); + E1000_WRITE_FLUSH(hw); + udelay(hw->eeprom.delay_usec); + + /* Falling edge of clock */ + eecd &= ~E1000_EECD_SK; + E1000_WRITE_REG(hw, EECD, eecd); + E1000_WRITE_FLUSH(hw); + udelay(hw->eeprom.delay_usec); + } + + /* Stop requesting EEPROM access */ + if (hw->mac_type > e1000_82544) { + eecd &= ~E1000_EECD_REQ; + E1000_WRITE_REG(hw, EECD, eecd); + } + + e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM); +} + +/****************************************************************************** + * Reads a 16 bit word from the EEPROM. + * + * hw - Struct containing variables accessed by shared code + *****************************************************************************/ +static int32_t +e1000_spi_eeprom_ready(struct e1000_hw *hw) +{ + uint16_t retry_count = 0; + uint8_t spi_stat_reg; + + DEBUGFUNC(); + + /* Read "Status Register" repeatedly until the LSB is cleared. The + * EEPROM will signal that the command has been completed by clearing + * bit 0 of the internal status register. If it's not cleared within + * 5 milliseconds, then error out. + */ + retry_count = 0; + do { + e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI, + hw->eeprom.opcode_bits); + spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8); + if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI)) + break; + + udelay(5); + retry_count += 5; + + e1000_standby_eeprom(hw); + } while (retry_count < EEPROM_MAX_RETRY_SPI); + + /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and + * only 0-5mSec on 5V devices) + */ + if (retry_count >= EEPROM_MAX_RETRY_SPI) { + DEBUGOUT("SPI EEPROM Status error\n"); + return -E1000_ERR_EEPROM; + } + + return E1000_SUCCESS; +} + +/****************************************************************************** + * Reads a 16 bit word from the EEPROM. + * + * hw - Struct containing variables accessed by shared code + * offset - offset of word in the EEPROM to read + * data - word read from the EEPROM + *****************************************************************************/ +static int32_t +e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset, + uint16_t words, uint16_t *data) +{ + struct e1000_eeprom_info *eeprom = &hw->eeprom; + uint32_t i = 0; + + DEBUGFUNC(); + + /* If eeprom is not yet detected, do so now */ + if (eeprom->word_size == 0) + e1000_init_eeprom_params(hw); + + /* A check for invalid values: offset too large, too many words, + * and not enough words. + */ + if ((offset >= eeprom->word_size) || + (words > eeprom->word_size - offset) || + (words == 0)) { + DEBUGOUT("\"words\" parameter out of bounds." + "Words = %d, size = %d\n", offset, eeprom->word_size); + return -E1000_ERR_EEPROM; + } + + /* EEPROM's that don't use EERD to read require us to bit-bang the SPI + * directly. In this case, we need to acquire the EEPROM so that + * FW or other port software does not interrupt. + */ + if (e1000_is_onboard_nvm_eeprom(hw) == true && + hw->eeprom.use_eerd == false) { + + /* Prepare the EEPROM for bit-bang reading */ + if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) + return -E1000_ERR_EEPROM; + } + + /* Eerd register EEPROM access requires no eeprom aquire/release */ + if (eeprom->use_eerd == true) + return e1000_read_eeprom_eerd(hw, offset, words, data); + + /* ich8lan does not support currently. if needed, please + * add corresponding code and functions. + */ +#if 0 + /* ICH EEPROM access is done via the ICH flash controller */ + if (eeprom->type == e1000_eeprom_ich8) + return e1000_read_eeprom_ich8(hw, offset, words, data); +#endif + /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have + * acquired the EEPROM at this point, so any returns should relase it */ + if (eeprom->type == e1000_eeprom_spi) { + uint16_t word_in; + uint8_t read_opcode = EEPROM_READ_OPCODE_SPI; + + if (e1000_spi_eeprom_ready(hw)) { + e1000_release_eeprom(hw); + return -E1000_ERR_EEPROM; + } + + e1000_standby_eeprom(hw); + + /* Some SPI eeproms use the 8th address bit embedded in + * the opcode */ + if ((eeprom->address_bits == 8) && (offset >= 128)) + read_opcode |= EEPROM_A8_OPCODE_SPI; + + /* Send the READ command (opcode + addr) */ + e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits); + e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2), + eeprom->address_bits); + + /* Read the data. The address of the eeprom internally + * increments with each byte (spi) being read, saving on the + * overhead of eeprom setup and tear-down. The address + * counter will roll over if reading beyond the size of + * the eeprom, thus allowing the entire memory to be read + * starting from any offset. */ + for (i = 0; i < words; i++) { + word_in = e1000_shift_in_ee_bits(hw, 16); + data[i] = (word_in >> 8) | (word_in << 8); + } + } else if (eeprom->type == e1000_eeprom_microwire) { + for (i = 0; i < words; i++) { + /* Send the READ command (opcode + addr) */ + e1000_shift_out_ee_bits(hw, + EEPROM_READ_OPCODE_MICROWIRE, + eeprom->opcode_bits); + e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i), + eeprom->address_bits); + + /* Read the data. For microwire, each word requires + * the overhead of eeprom setup and tear-down. */ + data[i] = e1000_shift_in_ee_bits(hw, 16); + e1000_standby_eeprom(hw); + } + } + + /* End this read operation */ + e1000_release_eeprom(hw); + + return E1000_SUCCESS; +} + +/****************************************************************************** + * Verifies that the EEPROM has a valid checksum + * + * hw - Struct containing variables accessed by shared code + * + * Reads the first 64 16 bit words of the EEPROM and sums the values read. + * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is + * valid. + *****************************************************************************/ +static int e1000_validate_eeprom_checksum(struct e1000_hw *hw) +{ + uint16_t i, checksum, checksum_reg, *buf; + + DEBUGFUNC(); + + /* Allocate a temporary buffer */ + buf = malloc(sizeof(buf[0]) * (EEPROM_CHECKSUM_REG + 1)); + if (!buf) { + E1000_ERR(hw, "Unable to allocate EEPROM buffer!\n"); + return -E1000_ERR_EEPROM; + } + + /* Read the EEPROM */ + if (e1000_read_eeprom(hw, 0, EEPROM_CHECKSUM_REG + 1, buf) < 0) { + E1000_ERR(hw, "Unable to read EEPROM!\n"); + return -E1000_ERR_EEPROM; + } + + /* Compute the checksum */ + checksum = 0; + for (i = 0; i < EEPROM_CHECKSUM_REG; i++) + checksum += buf[i]; + checksum = ((uint16_t)EEPROM_SUM) - checksum; + checksum_reg = buf[i]; + + /* Verify it! */ + if (checksum == checksum_reg) + return 0; + + /* Hrm, verification failed, print an error */ + E1000_ERR(hw, "EEPROM checksum is incorrect!\n"); + E1000_ERR(hw, " ...register was 0x%04hx, calculated 0x%04hx\n", + checksum_reg, checksum); + + return -E1000_ERR_EEPROM; +} +#endif /* CONFIG_E1000_NO_NVM */ + +/***************************************************************************** + * Set PHY to class A mode + * Assumes the following operations will follow to enable the new class mode. + * 1. Do a PHY soft reset + * 2. Restart auto-negotiation or force link. + * + * hw - Struct containing variables accessed by shared code + ****************************************************************************/ +static int32_t +e1000_set_phy_mode(struct e1000_hw *hw) +{ +#ifndef CONFIG_E1000_NO_NVM + int32_t ret_val; + uint16_t eeprom_data; + + DEBUGFUNC(); + + if ((hw->mac_type == e1000_82545_rev_3) && + (hw->media_type == e1000_media_type_copper)) { + ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, + 1, &eeprom_data); + if (ret_val) + return ret_val; + + if ((eeprom_data != EEPROM_RESERVED_WORD) && + (eeprom_data & EEPROM_PHY_CLASS_A)) { + ret_val = e1000_write_phy_reg(hw, + M88E1000_PHY_PAGE_SELECT, 0x000B); + if (ret_val) + return ret_val; + ret_val = e1000_write_phy_reg(hw, + M88E1000_PHY_GEN_CONTROL, 0x8104); + if (ret_val) + return ret_val; + + hw->phy_reset_disable = false; + } + } +#endif + return E1000_SUCCESS; +} + +#ifndef CONFIG_E1000_NO_NVM +/*************************************************************************** + * + * Obtaining software semaphore bit (SMBI) before resetting PHY. + * + * hw: Struct containing variables accessed by shared code + * + * returns: - E1000_ERR_RESET if fail to obtain semaphore. + * E1000_SUCCESS at any other case. + * + ***************************************************************************/ +static int32_t +e1000_get_software_semaphore(struct e1000_hw *hw) +{ + int32_t timeout = hw->eeprom.word_size + 1; + uint32_t swsm; + + DEBUGFUNC(); + + if (hw->mac_type != e1000_80003es2lan) + return E1000_SUCCESS; + + while (timeout) { + swsm = E1000_READ_REG(hw, SWSM); + /* If SMBI bit cleared, it is now set and we hold + * the semaphore */ + if (!(swsm & E1000_SWSM_SMBI)) + break; + mdelay(1); + timeout--; + } + + if (!timeout) { + DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); + return -E1000_ERR_RESET; + } + + return E1000_SUCCESS; +} +#endif + +/*************************************************************************** + * This function clears HW semaphore bits. + * + * hw: Struct containing variables accessed by shared code + * + * returns: - None. + * + ***************************************************************************/ +static void +e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw) +{ +#ifndef CONFIG_E1000_NO_NVM + uint32_t swsm; + + DEBUGFUNC(); + + if (!hw->eeprom_semaphore_present) + return; + + swsm = E1000_READ_REG(hw, SWSM); + if (hw->mac_type == e1000_80003es2lan) { + /* Release both semaphores. */ + swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); + } else + swsm &= ~(E1000_SWSM_SWESMBI); + E1000_WRITE_REG(hw, SWSM, swsm); +#endif +} + +/*************************************************************************** + * + * Using the combination of SMBI and SWESMBI semaphore bits when resetting + * adapter or Eeprom access. + * + * hw: Struct containing variables accessed by shared code + * + * returns: - E1000_ERR_EEPROM if fail to access EEPROM. + * E1000_SUCCESS at any other case. + * + ***************************************************************************/ +static int32_t +e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw) +{ +#ifndef CONFIG_E1000_NO_NVM + int32_t timeout; + uint32_t swsm; + + DEBUGFUNC(); + + if (!hw->eeprom_semaphore_present) + return E1000_SUCCESS; + + if (hw->mac_type == e1000_80003es2lan) { + /* Get the SW semaphore. */ + if (e1000_get_software_semaphore(hw) != E1000_SUCCESS) + return -E1000_ERR_EEPROM; + } + + /* Get the FW semaphore. */ + timeout = hw->eeprom.word_size + 1; + while (timeout) { + swsm = E1000_READ_REG(hw, SWSM); + swsm |= E1000_SWSM_SWESMBI; + E1000_WRITE_REG(hw, SWSM, swsm); + /* if we managed to set the bit we got the semaphore. */ + swsm = E1000_READ_REG(hw, SWSM); + if (swsm & E1000_SWSM_SWESMBI) + break; + + udelay(50); + timeout--; + } + + if (!timeout) { + /* Release semaphores */ + e1000_put_hw_eeprom_semaphore(hw); + DEBUGOUT("Driver can't access the Eeprom - " + "SWESMBI bit is set.\n"); + return -E1000_ERR_EEPROM; + } +#endif + return E1000_SUCCESS; +} + +/* Take ownership of the PHY */ +static int32_t +e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask) +{ + uint32_t swfw_sync = 0; + uint32_t swmask = mask; + uint32_t fwmask = mask << 16; + int32_t timeout = 200; + + DEBUGFUNC(); + while (timeout) { + if (e1000_get_hw_eeprom_semaphore(hw)) + return -E1000_ERR_SWFW_SYNC; + + swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); + if (!(swfw_sync & (fwmask | swmask))) + break; + + /* firmware currently using resource (fwmask) */ + /* or other software thread currently using resource (swmask) */ + e1000_put_hw_eeprom_semaphore(hw); + mdelay(5); + timeout--; + } + + if (!timeout) { + DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); + return -E1000_ERR_SWFW_SYNC; + } + + swfw_sync |= swmask; + E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync); + + e1000_put_hw_eeprom_semaphore(hw); + return E1000_SUCCESS; +} + +static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask) +{ + uint32_t swfw_sync = 0; + + DEBUGFUNC(); + while (e1000_get_hw_eeprom_semaphore(hw)) + ; /* Empty */ + + swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); + swfw_sync &= ~mask; + E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync); + + e1000_put_hw_eeprom_semaphore(hw); +} + +static bool e1000_is_second_port(struct e1000_hw *hw) +{ + switch (hw->mac_type) { + case e1000_80003es2lan: + case e1000_82546: + case e1000_82571: + if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) + return true; + /* Fallthrough */ + default: + return false; + } +} + +#ifndef CONFIG_E1000_NO_NVM +/****************************************************************************** + * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the + * second function of dual function devices + * + * nic - Struct containing variables accessed by shared code + *****************************************************************************/ +static int +e1000_read_mac_addr(struct e1000_hw *hw, unsigned char enetaddr[6]) +{ + uint16_t offset; + uint16_t eeprom_data; + uint32_t reg_data = 0; + int i; + + DEBUGFUNC(); + + for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) { + offset = i >> 1; + if (hw->mac_type == e1000_igb) { + /* i210 preloads MAC address into RAL/RAH registers */ + if (offset == 0) + reg_data = E1000_READ_REG_ARRAY(hw, RA, 0); + else if (offset == 1) + reg_data >>= 16; + else if (offset == 2) + reg_data = E1000_READ_REG_ARRAY(hw, RA, 1); + eeprom_data = reg_data & 0xffff; + } else if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { + DEBUGOUT("EEPROM Read Error\n"); + return -E1000_ERR_EEPROM; + } + enetaddr[i] = eeprom_data & 0xff; + enetaddr[i + 1] = (eeprom_data >> 8) & 0xff; + } + + /* Invert the last bit if this is the second device */ + if (e1000_is_second_port(hw)) + enetaddr[5] ^= 1; + + return 0; +} +#endif + +/****************************************************************************** + * Initializes receive address filters. + * + * hw - Struct containing variables accessed by shared code + * + * Places the MAC address in receive address register 0 and clears the rest + * of the receive addresss registers. Clears the multicast table. Assumes + * the receiver is in reset when the routine is called. + *****************************************************************************/ +static void +e1000_init_rx_addrs(struct e1000_hw *hw, unsigned char enetaddr[6]) +{ + uint32_t i; + uint32_t addr_low; + uint32_t addr_high; + + DEBUGFUNC(); + + /* Setup the receive address. */ + DEBUGOUT("Programming MAC Address into RAR[0]\n"); + addr_low = (enetaddr[0] | + (enetaddr[1] << 8) | + (enetaddr[2] << 16) | (enetaddr[3] << 24)); + + addr_high = (enetaddr[4] | (enetaddr[5] << 8) | E1000_RAH_AV); + + E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low); + E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high); + + /* Zero out the other 15 receive addresses. */ + DEBUGOUT("Clearing RAR[1-15]\n"); + for (i = 1; i < E1000_RAR_ENTRIES; i++) { + E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); + E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); + } +} + +/****************************************************************************** + * Clears the VLAN filer table + * + * hw - Struct containing variables accessed by shared code + *****************************************************************************/ +static void +e1000_clear_vfta(struct e1000_hw *hw) +{ + uint32_t offset; + + for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) + E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0); +} + +/****************************************************************************** + * Set the mac type member in the hw struct. + * + * hw - Struct containing variables accessed by shared code + *****************************************************************************/ +int32_t +e1000_set_mac_type(struct e1000_hw *hw) +{ + DEBUGFUNC(); + + switch (hw->device_id) { + case E1000_DEV_ID_82542: + switch (hw->revision_id) { + case E1000_82542_2_0_REV_ID: + hw->mac_type = e1000_82542_rev2_0; + break; + case E1000_82542_2_1_REV_ID: + hw->mac_type = e1000_82542_rev2_1; + break; + default: + /* Invalid 82542 revision ID */ + return -E1000_ERR_MAC_TYPE; + } + break; + case E1000_DEV_ID_82543GC_FIBER: + case E1000_DEV_ID_82543GC_COPPER: + hw->mac_type = e1000_82543; + break; + case E1000_DEV_ID_82544EI_COPPER: + case E1000_DEV_ID_82544EI_FIBER: + case E1000_DEV_ID_82544GC_COPPER: + case E1000_DEV_ID_82544GC_LOM: + hw->mac_type = e1000_82544; + break; + case E1000_DEV_ID_82540EM: + case E1000_DEV_ID_82540EM_LOM: + case E1000_DEV_ID_82540EP: + case E1000_DEV_ID_82540EP_LOM: + case E1000_DEV_ID_82540EP_LP: + hw->mac_type = e1000_82540; + break; + case E1000_DEV_ID_82545EM_COPPER: + case E1000_DEV_ID_82545EM_FIBER: + hw->mac_type = e1000_82545; + break; + case E1000_DEV_ID_82545GM_COPPER: + case E1000_DEV_ID_82545GM_FIBER: + case E1000_DEV_ID_82545GM_SERDES: + hw->mac_type = e1000_82545_rev_3; + break; + case E1000_DEV_ID_82546EB_COPPER: + case E1000_DEV_ID_82546EB_FIBER: + case E1000_DEV_ID_82546EB_QUAD_COPPER: + hw->mac_type = e1000_82546; + break; + case E1000_DEV_ID_82546GB_COPPER: + case E1000_DEV_ID_82546GB_FIBER: + case E1000_DEV_ID_82546GB_SERDES: + case E1000_DEV_ID_82546GB_PCIE: + case E1000_DEV_ID_82546GB_QUAD_COPPER: + case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: + hw->mac_type = e1000_82546_rev_3; + break; + case E1000_DEV_ID_82541EI: + case E1000_DEV_ID_82541EI_MOBILE: + case E1000_DEV_ID_82541ER_LOM: + hw->mac_type = e1000_82541; + break; + case E1000_DEV_ID_82541ER: + case E1000_DEV_ID_82541GI: + case E1000_DEV_ID_82541GI_LF: + case E1000_DEV_ID_82541GI_MOBILE: + hw->mac_type = e1000_82541_rev_2; + break; + case E1000_DEV_ID_82547EI: + case E1000_DEV_ID_82547EI_MOBILE: + hw->mac_type = e1000_82547; + break; + case E1000_DEV_ID_82547GI: + hw->mac_type = e1000_82547_rev_2; + break; + case E1000_DEV_ID_82571EB_COPPER: + case E1000_DEV_ID_82571EB_FIBER: + case E1000_DEV_ID_82571EB_SERDES: + case E1000_DEV_ID_82571EB_SERDES_DUAL: + case E1000_DEV_ID_82571EB_SERDES_QUAD: + case E1000_DEV_ID_82571EB_QUAD_COPPER: + case E1000_DEV_ID_82571PT_QUAD_COPPER: + case E1000_DEV_ID_82571EB_QUAD_FIBER: + case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE: + hw->mac_type = e1000_82571; + break; + case E1000_DEV_ID_82572EI_COPPER: + case E1000_DEV_ID_82572EI_FIBER: + case E1000_DEV_ID_82572EI_SERDES: + case E1000_DEV_ID_82572EI: + hw->mac_type = e1000_82572; + break; + case E1000_DEV_ID_82573E: + case E1000_DEV_ID_82573E_IAMT: + case E1000_DEV_ID_82573L: + hw->mac_type = e1000_82573; + break; + case E1000_DEV_ID_82574L: + hw->mac_type = e1000_82574; + break; + case E1000_DEV_ID_80003ES2LAN_COPPER_SPT: + case E1000_DEV_ID_80003ES2LAN_SERDES_SPT: + case E1000_DEV_ID_80003ES2LAN_COPPER_DPT: + case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: + hw->mac_type = e1000_80003es2lan; + break; + case E1000_DEV_ID_ICH8_IGP_M_AMT: + case E1000_DEV_ID_ICH8_IGP_AMT: + case E1000_DEV_ID_ICH8_IGP_C: + case E1000_DEV_ID_ICH8_IFE: + case E1000_DEV_ID_ICH8_IFE_GT: + case E1000_DEV_ID_ICH8_IFE_G: + case E1000_DEV_ID_ICH8_IGP_M: + hw->mac_type = e1000_ich8lan; + break; + case PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED: + case PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED: + case PCI_DEVICE_ID_INTEL_I210_COPPER: + case PCI_DEVICE_ID_INTEL_I211_COPPER: + case PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS: + case PCI_DEVICE_ID_INTEL_I210_SERDES: + case PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS: + case PCI_DEVICE_ID_INTEL_I210_1000BASEKX: + hw->mac_type = e1000_igb; + break; + default: + /* Should never have loaded on this device */ + return -E1000_ERR_MAC_TYPE; + } + return E1000_SUCCESS; +} + +/****************************************************************************** + * Reset the transmit and receive units; mask and clear all interrupts. + * + * hw - Struct containing variables accessed by shared code + *****************************************************************************/ +void +e1000_reset_hw(struct e1000_hw *hw) +{ + uint32_t ctrl; + uint32_t ctrl_ext; + uint32_t manc; + uint32_t pba = 0; + uint32_t reg; + + DEBUGFUNC(); + + /* get the correct pba value for both PCI and PCIe*/ + if (hw->mac_type < e1000_82571) + pba = E1000_DEFAULT_PCI_PBA; + else + pba = E1000_DEFAULT_PCIE_PBA; + + /* For 82542 (rev 2.0), disable MWI before issuing a device reset */ + if (hw->mac_type == e1000_82542_rev2_0) { + DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); + pci_write_config_word(hw->pdev, PCI_COMMAND, + hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE); + } + + /* Clear interrupt mask to stop board from generating interrupts */ + DEBUGOUT("Masking off all interrupts\n"); + if (hw->mac_type == e1000_igb) + E1000_WRITE_REG(hw, I210_IAM, 0); + E1000_WRITE_REG(hw, IMC, 0xffffffff); + + /* Disable the Transmit and Receive units. Then delay to allow + * any pending transactions to complete before we hit the MAC with + * the global reset. + */ + E1000_WRITE_REG(hw, RCTL, 0); + E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP); + E1000_WRITE_FLUSH(hw); + + /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */ + hw->tbi_compatibility_on = false; + + /* Delay to allow any outstanding PCI transactions to complete before + * resetting the device + */ + mdelay(10); + + /* Issue a global reset to the MAC. This will reset the chip's + * transmit, receive, DMA, and link units. It will not effect + * the current PCI configuration. The global reset bit is self- + * clearing, and should clear within a microsecond. + */ + DEBUGOUT("Issuing a global reset to MAC\n"); + ctrl = E1000_READ_REG(hw, CTRL); + + E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); + + /* Force a reload from the EEPROM if necessary */ + if (hw->mac_type == e1000_igb) { + mdelay(20); + reg = E1000_READ_REG(hw, STATUS); + if (reg & E1000_STATUS_PF_RST_DONE) + DEBUGOUT("PF OK\n"); + reg = E1000_READ_REG(hw, I210_EECD); + if (reg & E1000_EECD_AUTO_RD) + DEBUGOUT("EEC OK\n"); + } else if (hw->mac_type < e1000_82540) { + /* Wait for reset to complete */ + udelay(10); + ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); + ctrl_ext |= E1000_CTRL_EXT_EE_RST; + E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); + E1000_WRITE_FLUSH(hw); + /* Wait for EEPROM reload */ + mdelay(2); + } else { + /* Wait for EEPROM reload (it happens automatically) */ + mdelay(4); + /* Dissable HW ARPs on ASF enabled adapters */ + manc = E1000_READ_REG(hw, MANC); + manc &= ~(E1000_MANC_ARP_EN); + E1000_WRITE_REG(hw, MANC, manc); + } + + /* Clear interrupt mask to stop board from generating interrupts */ + DEBUGOUT("Masking off all interrupts\n"); + if (hw->mac_type == e1000_igb) + E1000_WRITE_REG(hw, I210_IAM, 0); + E1000_WRITE_REG(hw, IMC, 0xffffffff); + + /* Clear any pending interrupt events. */ + E1000_READ_REG(hw, ICR); + + /* If MWI was previously enabled, reenable it. */ + if (hw->mac_type == e1000_82542_rev2_0) { + pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); + } + if (hw->mac_type != e1000_igb) + E1000_WRITE_REG(hw, PBA, pba); +} + +/****************************************************************************** + * + * Initialize a number of hardware-dependent bits + * + * hw: Struct containing variables accessed by shared code + * + * This function contains hardware limitation workarounds for PCI-E adapters + * + *****************************************************************************/ +static void +e1000_initialize_hardware_bits(struct e1000_hw *hw) +{ + if ((hw->mac_type >= e1000_82571) && + (!hw->initialize_hw_bits_disable)) { + /* Settings common to all PCI-express silicon */ + uint32_t reg_ctrl, reg_ctrl_ext; + uint32_t reg_tarc0, reg_tarc1; + uint32_t reg_tctl; + uint32_t reg_txdctl, reg_txdctl1; + + /* link autonegotiation/sync workarounds */ + reg_tarc0 = E1000_READ_REG(hw, TARC0); + reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); + + /* Enable not-done TX descriptor counting */ + reg_txdctl = E1000_READ_REG(hw, TXDCTL); + reg_txdctl |= E1000_TXDCTL_COUNT_DESC; + E1000_WRITE_REG(hw, TXDCTL, reg_txdctl); + + reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1); + reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC; + E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1); + + /* IGB is cool */ + if (hw->mac_type == e1000_igb) + return; + + switch (hw->mac_type) { + case e1000_82571: + case e1000_82572: + /* Clear PHY TX compatible mode bits */ + reg_tarc1 = E1000_READ_REG(hw, TARC1); + reg_tarc1 &= ~((1 << 30)|(1 << 29)); + + /* link autonegotiation/sync workarounds */ + reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23)); + + /* TX ring control fixes */ + reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24)); + + /* Multiple read bit is reversed polarity */ + reg_tctl = E1000_READ_REG(hw, TCTL); + if (reg_tctl & E1000_TCTL_MULR) + reg_tarc1 &= ~(1 << 28); + else + reg_tarc1 |= (1 << 28); + + E1000_WRITE_REG(hw, TARC1, reg_tarc1); + break; + case e1000_82573: + case e1000_82574: + reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); + reg_ctrl_ext &= ~(1 << 23); + reg_ctrl_ext |= (1 << 22); + + /* TX byte count fix */ + reg_ctrl = E1000_READ_REG(hw, CTRL); + reg_ctrl &= ~(1 << 29); + + E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext); + E1000_WRITE_REG(hw, CTRL, reg_ctrl); + break; + case e1000_80003es2lan: + /* improve small packet performace for fiber/serdes */ + if ((hw->media_type == e1000_media_type_fiber) + || (hw->media_type == + e1000_media_type_internal_serdes)) { + reg_tarc0 &= ~(1 << 20); + } + + /* Multiple read bit is reversed polarity */ + reg_tctl = E1000_READ_REG(hw, TCTL); + reg_tarc1 = E1000_READ_REG(hw, TARC1); + if (reg_tctl & E1000_TCTL_MULR) + reg_tarc1 &= ~(1 << 28); + else + reg_tarc1 |= (1 << 28); + + E1000_WRITE_REG(hw, TARC1, reg_tarc1); + break; + case e1000_ich8lan: + /* Reduce concurrent DMA requests to 3 from 4 */ + if ((hw->revision_id < 3) || + ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) && + (hw->device_id != E1000_DEV_ID_ICH8_IGP_M))) + reg_tarc0 |= ((1 << 29)|(1 << 28)); + + reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); + reg_ctrl_ext |= (1 << 22); + E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext); + + /* workaround TX hang with TSO=on */ + reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23)); + + /* Multiple read bit is reversed polarity */ + reg_tctl = E1000_READ_REG(hw, TCTL); + reg_tarc1 = E1000_READ_REG(hw, TARC1); + if (reg_tctl & E1000_TCTL_MULR) + reg_tarc1 &= ~(1 << 28); + else + reg_tarc1 |= (1 << 28); + + /* workaround TX hang with TSO=on */ + reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24)); + + E1000_WRITE_REG(hw, TARC1, reg_tarc1); + break; + default: + break; + } + + E1000_WRITE_REG(hw, TARC0, reg_tarc0); + } +} + +/****************************************************************************** + * Performs basic configuration of the adapter. + * + * hw - Struct containing variables accessed by shared code + * + * Assumes that the controller has previously been reset and is in a + * post-reset uninitialized state. Initializes the receive address registers, + * multicast table, and VLAN filter table. Calls routines to setup link + * configuration and flow control settings. Clears all on-chip counters. Leaves + * the transmit and receive units disabled and uninitialized. + *****************************************************************************/ +static int +e1000_init_hw(struct e1000_hw *hw, unsigned char enetaddr[6]) +{ + uint32_t ctrl; + uint32_t i; + int32_t ret_val; + uint16_t pcix_cmd_word; + uint16_t pcix_stat_hi_word; + uint16_t cmd_mmrbc; + uint16_t stat_mmrbc; + uint32_t mta_size; + uint32_t reg_data; + uint32_t ctrl_ext; + DEBUGFUNC(); + /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */ + if ((hw->mac_type == e1000_ich8lan) && + ((hw->revision_id < 3) || + ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) && + (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) { + reg_data = E1000_READ_REG(hw, STATUS); + reg_data &= ~0x80000000; + E1000_WRITE_REG(hw, STATUS, reg_data); + } + /* Do not need initialize Identification LED */ + + /* Set the media type and TBI compatibility */ + e1000_set_media_type(hw); + + /* Must be called after e1000_set_media_type + * because media_type is used */ + e1000_initialize_hardware_bits(hw); + + /* Disabling VLAN filtering. */ + DEBUGOUT("Initializing the IEEE VLAN\n"); + /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */ + if (hw->mac_type != e1000_ich8lan) { + if (hw->mac_type < e1000_82545_rev_3) + E1000_WRITE_REG(hw, VET, 0); + e1000_clear_vfta(hw); + } + + /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ + if (hw->mac_type == e1000_82542_rev2_0) { + DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); + pci_write_config_word(hw->pdev, PCI_COMMAND, + hw-> + pci_cmd_word & ~PCI_COMMAND_INVALIDATE); + E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST); + E1000_WRITE_FLUSH(hw); + mdelay(5); + } + + /* Setup the receive address. This involves initializing all of the Receive + * Address Registers (RARs 0 - 15). + */ + e1000_init_rx_addrs(hw, enetaddr); + + /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */ + if (hw->mac_type == e1000_82542_rev2_0) { + E1000_WRITE_REG(hw, RCTL, 0); + E1000_WRITE_FLUSH(hw); + mdelay(1); + pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); + } + + /* Zero out the Multicast HASH table */ + DEBUGOUT("Zeroing the MTA\n"); + mta_size = E1000_MC_TBL_SIZE; + if (hw->mac_type == e1000_ich8lan) + mta_size = E1000_MC_TBL_SIZE_ICH8LAN; + for (i = 0; i < mta_size; i++) { + E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); + /* use write flush to prevent Memory Write Block (MWB) from + * occuring when accessing our register space */ + E1000_WRITE_FLUSH(hw); + } +#if 0 + /* Set the PCI priority bit correctly in the CTRL register. This + * determines if the adapter gives priority to receives, or if it + * gives equal priority to transmits and receives. Valid only on + * 82542 and 82543 silicon. + */ + if (hw->dma_fairness && hw->mac_type <= e1000_82543) { + ctrl = E1000_READ_REG(hw, CTRL); + E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR); + } +#endif + switch (hw->mac_type) { + case e1000_82545_rev_3: + case e1000_82546_rev_3: + case e1000_igb: + break; + default: + /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */ + if (hw->bus_type == e1000_bus_type_pcix) { + pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER, + &pcix_cmd_word); + pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI, + &pcix_stat_hi_word); + cmd_mmrbc = + (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >> + PCIX_COMMAND_MMRBC_SHIFT; + stat_mmrbc = + (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> + PCIX_STATUS_HI_MMRBC_SHIFT; + if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) + stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; + if (cmd_mmrbc > stat_mmrbc) { + pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK; + pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; + pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER, + pcix_cmd_word); + } + } + break; + } + + /* More time needed for PHY to initialize */ + if (hw->mac_type == e1000_ich8lan) + mdelay(15); + if (hw->mac_type == e1000_igb) + mdelay(15); + + /* Call a subroutine to configure the link and setup flow control. */ + ret_val = e1000_setup_link(hw); + + /* Set the transmit descriptor write-back policy */ + if (hw->mac_type > e1000_82544) { + ctrl = E1000_READ_REG(hw, TXDCTL); + ctrl = + (ctrl & ~E1000_TXDCTL_WTHRESH) | + E1000_TXDCTL_FULL_TX_DESC_WB; + E1000_WRITE_REG(hw, TXDCTL, ctrl); + } + + /* Set the receive descriptor write back policy */ + if (hw->mac_type >= e1000_82571) { + ctrl = E1000_READ_REG(hw, RXDCTL); + ctrl = + (ctrl & ~E1000_RXDCTL_WTHRESH) | + E1000_RXDCTL_FULL_RX_DESC_WB; + E1000_WRITE_REG(hw, RXDCTL, ctrl); + } + + switch (hw->mac_type) { + default: + break; + case e1000_80003es2lan: + /* Enable retransmit on late collisions */ + reg_data = E1000_READ_REG(hw, TCTL); + reg_data |= E1000_TCTL_RTLC; + E1000_WRITE_REG(hw, TCTL, reg_data); + + /* Configure Gigabit Carry Extend Padding */ + reg_data = E1000_READ_REG(hw, TCTL_EXT); + reg_data &= ~E1000_TCTL_EXT_GCEX_MASK; + reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX; + E1000_WRITE_REG(hw, TCTL_EXT, reg_data); + + /* Configure Transmit Inter-Packet Gap */ + reg_data = E1000_READ_REG(hw, TIPG); + reg_data &= ~E1000_TIPG_IPGT_MASK; + reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; + E1000_WRITE_REG(hw, TIPG, reg_data); + + reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001); + reg_data &= ~0x00100000; + E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data); + /* Fall through */ + case e1000_82571: + case e1000_82572: + case e1000_ich8lan: + ctrl = E1000_READ_REG(hw, TXDCTL1); + ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) + | E1000_TXDCTL_FULL_TX_DESC_WB; + E1000_WRITE_REG(hw, TXDCTL1, ctrl); + break; + case e1000_82573: + case e1000_82574: + reg_data = E1000_READ_REG(hw, GCR); + reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; + E1000_WRITE_REG(hw, GCR, reg_data); + case e1000_igb: + break; + } + +#if 0 + /* Clear all of the statistics registers (clear on read). It is + * important that we do this after we have tried to establish link + * because the symbol error count will increment wildly if there + * is no link. + */ + e1000_clear_hw_cntrs(hw); + + /* ICH8 No-snoop bits are opposite polarity. + * Set to snoop by default after reset. */ + if (hw->mac_type == e1000_ich8lan) + e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL); +#endif + + if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER || + hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) { + ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); + /* Relaxed ordering must be disabled to avoid a parity + * error crash in a PCI slot. */ + ctrl_ext |= E1000_CTRL_EXT_RO_DIS; + E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); + } + + return ret_val; +} + +/****************************************************************************** + * Configures flow control and link settings. + * + * hw - Struct containing variables accessed by shared code + * + * Determines which flow control settings to use. Calls the apropriate media- + * specific link configuration function. Configures the flow control settings. + * Assuming the adapter has a valid link partner, a valid link should be + * established. Assumes the hardware has previously been reset and the + * transmitter and receiver are not enabled. + *****************************************************************************/ +static int +e1000_setup_link(struct e1000_hw *hw) +{ + int32_t ret_val; +#ifndef CONFIG_E1000_NO_NVM + uint32_t ctrl_ext; + uint16_t eeprom_data; +#endif + + DEBUGFUNC(); + + /* In the case of the phy reset being blocked, we already have a link. + * We do not have to set it up again. */ + if (e1000_check_phy_reset_block(hw)) + return E1000_SUCCESS; + +#ifndef CONFIG_E1000_NO_NVM + /* Read and store word 0x0F of the EEPROM. This word contains bits + * that determine the hardware's default PAUSE (flow control) mode, + * a bit that determines whether the HW defaults to enabling or + * disabling auto-negotiation, and the direction of the + * SW defined pins. If there is no SW over-ride of the flow + * control setting, then the variable hw->fc will + * be initialized based on a value in the EEPROM. + */ + if (e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1, + &eeprom_data) < 0) { + DEBUGOUT("EEPROM Read Error\n"); + return -E1000_ERR_EEPROM; + } +#endif + if (hw->fc == e1000_fc_default) { + switch (hw->mac_type) { + case e1000_ich8lan: + case e1000_82573: + case e1000_82574: + case e1000_igb: + hw->fc = e1000_fc_full; + break; + default: +#ifndef CONFIG_E1000_NO_NVM + ret_val = e1000_read_eeprom(hw, + EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data); + if (ret_val) { + DEBUGOUT("EEPROM Read Error\n"); + return -E1000_ERR_EEPROM; + } + if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0) + hw->fc = e1000_fc_none; + else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == + EEPROM_WORD0F_ASM_DIR) + hw->fc = e1000_fc_tx_pause; + else +#endif + hw->fc = e1000_fc_full; + break; + } + } + + /* We want to save off the original Flow Control configuration just + * in case we get disconnected and then reconnected into a different + * hub or switch with different Flow Control capabilities. + */ + if (hw->mac_type == e1000_82542_rev2_0) + hw->fc &= (~e1000_fc_tx_pause); + + if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1)) + hw->fc &= (~e1000_fc_rx_pause); + + hw->original_fc = hw->fc; + + DEBUGOUT("After fix-ups FlowControl is now = %x\n", hw->fc); + +#ifndef CONFIG_E1000_NO_NVM + /* Take the 4 bits from EEPROM word 0x0F that determine the initial + * polarity value for the SW controlled pins, and setup the + * Extended Device Control reg with that info. + * This is needed because one of the SW controlled pins is used for + * signal detection. So this should be done before e1000_setup_pcs_link() + * or e1000_phy_setup() is called. + */ + if (hw->mac_type == e1000_82543) { + ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << + SWDPIO__EXT_SHIFT); + E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); + } +#endif + + /* Call the necessary subroutine to configure the link. */ + ret_val = (hw->media_type == e1000_media_type_fiber) ? + e1000_setup_fiber_link(hw) : e1000_setup_copper_link(hw); + if (ret_val < 0) { + return ret_val; + } + + /* Initialize the flow control address, type, and PAUSE timer + * registers to their default values. This is done even if flow + * control is disabled, because it does not hurt anything to + * initialize these registers. + */ + DEBUGOUT("Initializing the Flow Control address, type" + "and timer regs\n"); + + /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */ + if (hw->mac_type != e1000_ich8lan) { + E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE); + E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH); + E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW); + } + + E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time); + + /* Set the flow control receive threshold registers. Normally, + * these registers will be set to a default threshold that may be + * adjusted later by the driver's runtime code. However, if the + * ability to transmit pause frames in not enabled, then these + * registers will be set to 0. + */ + if (!(hw->fc & e1000_fc_tx_pause)) { + E1000_WRITE_REG(hw, FCRTL, 0); + E1000_WRITE_REG(hw, FCRTH, 0); + } else { + /* We need to set up the Receive Threshold high and low water marks + * as well as (optionally) enabling the transmission of XON frames. + */ + if (hw->fc_send_xon) { + E1000_WRITE_REG(hw, FCRTL, + (hw->fc_low_water | E1000_FCRTL_XONE)); + E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); + } else { + E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water); + E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); + } + } + return ret_val; +} + +/****************************************************************************** + * Sets up link for a fiber based adapter + * + * hw - Struct containing variables accessed by shared code + * + * Manipulates Physical Coding Sublayer functions in order to configure + * link. Assumes the hardware has been previously reset and the transmitter + * and receiver are not enabled. + *****************************************************************************/ +static int +e1000_setup_fiber_link(struct e1000_hw *hw) +{ + uint32_t ctrl; + uint32_t status; + uint32_t txcw = 0; + uint32_t i; + uint32_t signal; + int32_t ret_val; + + DEBUGFUNC(); + /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be + * set when the optics detect a signal. On older adapters, it will be + * cleared when there is a signal + */ + ctrl = E1000_READ_REG(hw, CTRL); + if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS)) + signal = E1000_CTRL_SWDPIN1; + else + signal = 0; + + printf("signal for %s is %x (ctrl %08x)!!!!\n", hw->name, signal, + ctrl); + /* Take the link out of reset */ + ctrl &= ~(E1000_CTRL_LRST); + + e1000_config_collision_dist(hw); + + /* Check for a software override of the flow control settings, and setup + * the device accordingly. If auto-negotiation is enabled, then software + * will have to set the "PAUSE" bits to the correct value in the Tranmsit + * Config Word Register (TXCW) and re-start auto-negotiation. However, if + * auto-negotiation is disabled, then software will have to manually + * configure the two flow control enable bits in the CTRL register. + * + * The possible values of the "fc" parameter are: + * 0: Flow control is completely disabled + * 1: Rx flow control is enabled (we can receive pause frames, but + * not send pause frames). + * 2: Tx flow control is enabled (we can send pause frames but we do + * not support receiving pause frames). + * 3: Both Rx and TX flow control (symmetric) are enabled. + */ + switch (hw->fc) { + case e1000_fc_none: + /* Flow control is completely disabled by a software over-ride. */ + txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); + break; + case e1000_fc_rx_pause: + /* RX Flow control is enabled and TX Flow control is disabled by a + * software over-ride. Since there really isn't a way to advertise + * that we are capable of RX Pause ONLY, we will advertise that we + * support both symmetric and asymmetric RX PAUSE. Later, we will + * disable the adapter's ability to send PAUSE frames. + */ + txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); + break; + case e1000_fc_tx_pause: + /* TX Flow control is enabled, and RX Flow control is disabled, by a + * software over-ride. + */ + txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); + break; + case e1000_fc_full: + /* Flow control (both RX and TX) is enabled by a software over-ride. */ + txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); + break; + default: + DEBUGOUT("Flow control param set incorrectly\n"); + return -E1000_ERR_CONFIG; + break; + } + + /* Since auto-negotiation is enabled, take the link out of reset (the link + * will be in reset, because we previously reset the chip). This will + * restart auto-negotiation. If auto-neogtiation is successful then the + * link-up status bit will be set and the flow control enable bits (RFCE + * and TFCE) will be set according to their negotiated value. + */ + DEBUGOUT("Auto-negotiation enabled (%#x)\n", txcw); + + E1000_WRITE_REG(hw, TXCW, txcw); + E1000_WRITE_REG(hw, CTRL, ctrl); + E1000_WRITE_FLUSH(hw); + + hw->txcw = txcw; + mdelay(1); + + /* If we have a signal (the cable is plugged in) then poll for a "Link-Up" + * indication in the Device Status Register. Time-out if a link isn't + * seen in 500 milliseconds seconds (Auto-negotiation should complete in + * less than 500 milliseconds even if the other end is doing it in SW). + */ + if ((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) { + DEBUGOUT("Looking for Link\n"); + for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) { + mdelay(10); + status = E1000_READ_REG(hw, STATUS); + if (status & E1000_STATUS_LU) + break; + } + if (i == (LINK_UP_TIMEOUT / 10)) { + /* AutoNeg failed to achieve a link, so we'll call + * e1000_check_for_link. This routine will force the link up if we + * detect a signal. This will allow us to communicate with + * non-autonegotiating link partners. + */ + DEBUGOUT("Never got a valid link from auto-neg!!!\n"); + hw->autoneg_failed = 1; + ret_val = e1000_check_for_link(hw); + if (ret_val < 0) { + DEBUGOUT("Error while checking for link\n"); + return ret_val; + } + hw->autoneg_failed = 0; + } else { + hw->autoneg_failed = 0; + DEBUGOUT("Valid Link Found\n"); + } + } else { + DEBUGOUT("No Signal Detected\n"); + return -E1000_ERR_NOLINK; + } + return 0; +} + +/****************************************************************************** +* Make sure we have a valid PHY and change PHY mode before link setup. +* +* hw - Struct containing variables accessed by shared code +******************************************************************************/ +static int32_t +e1000_copper_link_preconfig(struct e1000_hw *hw) +{ + uint32_t ctrl; + int32_t ret_val; + uint16_t phy_data; + + DEBUGFUNC(); + + ctrl = E1000_READ_REG(hw, CTRL); + /* With 82543, we need to force speed and duplex on the MAC equal to what + * the PHY speed and duplex configuration is. In addition, we need to + * perform a hardware reset on the PHY to take it out of reset. + */ + if (hw->mac_type > e1000_82543) { + ctrl |= E1000_CTRL_SLU; + ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); + E1000_WRITE_REG(hw, CTRL, ctrl); + } else { + ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX + | E1000_CTRL_SLU); + E1000_WRITE_REG(hw, CTRL, ctrl); + ret_val = e1000_phy_hw_reset(hw); + if (ret_val) + return ret_val; + } + + /* Make sure we have a valid PHY */ + ret_val = e1000_detect_gig_phy(hw); + if (ret_val) { + DEBUGOUT("Error, did not detect valid phy.\n"); + return ret_val; + } + DEBUGOUT("Phy ID = %x\n", hw->phy_id); + + /* Set PHY to class A mode (if necessary) */ + ret_val = e1000_set_phy_mode(hw); + if (ret_val) + return ret_val; + if ((hw->mac_type == e1000_82545_rev_3) || + (hw->mac_type == e1000_82546_rev_3)) { + ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, + &phy_data); + phy_data |= 0x00000008; + ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, + phy_data); + } + + if (hw->mac_type <= e1000_82543 || + hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 || + hw->mac_type == e1000_82541_rev_2 + || hw->mac_type == e1000_82547_rev_2) + hw->phy_reset_disable = false; + + return E1000_SUCCESS; +} + +/***************************************************************************** + * + * This function sets the lplu state according to the active flag. When + * activating lplu this function also disables smart speed and vise versa. + * lplu will not be activated unless the device autonegotiation advertisment + * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. + * hw: Struct containing variables accessed by shared code + * active - true to enable lplu false to disable lplu. + * + * returns: - E1000_ERR_PHY if fail to read/write the PHY + * E1000_SUCCESS at any other case. + * + ****************************************************************************/ + +static int32_t +e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active) +{ + uint32_t phy_ctrl = 0; + int32_t ret_val; + uint16_t phy_data; + DEBUGFUNC(); + + if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2 + && hw->phy_type != e1000_phy_igp_3) + return E1000_SUCCESS; + + /* During driver activity LPLU should not be used or it will attain link + * from the lowest speeds starting from 10Mbps. The capability is used + * for Dx transitions and states */ + if (hw->mac_type == e1000_82541_rev_2 + || hw->mac_type == e1000_82547_rev_2) { + ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, + &phy_data); + if (ret_val) + return ret_val; + } else if (hw->mac_type == e1000_ich8lan) { + /* MAC writes into PHY register based on the state transition + * and start auto-negotiation. SW driver can overwrite the + * settings in CSR PHY power control E1000_PHY_CTRL register. */ + phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); + } else { + ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, + &phy_data); + if (ret_val) + return ret_val; + } + + if (!active) { + if (hw->mac_type == e1000_82541_rev_2 || + hw->mac_type == e1000_82547_rev_2) { + phy_data &= ~IGP01E1000_GMII_FLEX_SPD; + ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, + phy_data); + if (ret_val) + return ret_val; + } else { + if (hw->mac_type == e1000_ich8lan) { + phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; + E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); + } else { + phy_data &= ~IGP02E1000_PM_D3_LPLU; + ret_val = e1000_write_phy_reg(hw, + IGP02E1000_PHY_POWER_MGMT, phy_data); + if (ret_val) + return ret_val; + } + } + + /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during + * Dx states where the power conservation is most important. During + * driver activity we should enable SmartSpeed, so performance is + * maintained. */ + if (hw->smart_speed == e1000_smart_speed_on) { + ret_val = e1000_read_phy_reg(hw, + IGP01E1000_PHY_PORT_CONFIG, &phy_data); + if (ret_val) + return ret_val; + + phy_data |= IGP01E1000_PSCFR_SMART_SPEED; + ret_val = e1000_write_phy_reg(hw, + IGP01E1000_PHY_PORT_CONFIG, phy_data); + if (ret_val) + return ret_val; + } else if (hw->smart_speed == e1000_smart_speed_off) { + ret_val = e1000_read_phy_reg(hw, + IGP01E1000_PHY_PORT_CONFIG, &phy_data); + if (ret_val) + return ret_val; + + phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; + ret_val = e1000_write_phy_reg(hw, + IGP01E1000_PHY_PORT_CONFIG, phy_data); + if (ret_val) + return ret_val; + } + + } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) + || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) || + (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) { + + if (hw->mac_type == e1000_82541_rev_2 || + hw->mac_type == e1000_82547_rev_2) { + phy_data |= IGP01E1000_GMII_FLEX_SPD; + ret_val = e1000_write_phy_reg(hw, + IGP01E1000_GMII_FIFO, phy_data); + if (ret_val) + return ret_val; + } else { + if (hw->mac_type == e1000_ich8lan) { + phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; + E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); + } else { + phy_data |= IGP02E1000_PM_D3_LPLU; + ret_val = e1000_write_phy_reg(hw, + IGP02E1000_PHY_POWER_MGMT, phy_data); + if (ret_val) + return ret_val; + } + } + + /* When LPLU is enabled we should disable SmartSpeed */ + ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, + &phy_data); + if (ret_val) + return ret_val; + + phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; + ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, + phy_data); + if (ret_val) + return ret_val; + } + return E1000_SUCCESS; +} + +/***************************************************************************** + * + * This function sets the lplu d0 state according to the active flag. When + * activating lplu this function also disables smart speed and vise versa. + * lplu will not be activated unless the device autonegotiation advertisment + * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. + * hw: Struct containing variables accessed by shared code + * active - true to enable lplu false to disable lplu. + * + * returns: - E1000_ERR_PHY if fail to read/write the PHY + * E1000_SUCCESS at any other case. + * + ****************************************************************************/ + +static int32_t +e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active) +{ + uint32_t phy_ctrl = 0; + int32_t ret_val; + uint16_t phy_data; + DEBUGFUNC(); + + if (hw->mac_type <= e1000_82547_rev_2) + return E1000_SUCCESS; + + if (hw->mac_type == e1000_ich8lan) { + phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); + } else if (hw->mac_type == e1000_igb) { + phy_ctrl = E1000_READ_REG(hw, I210_PHY_CTRL); + } else { + ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, + &phy_data); + if (ret_val) + return ret_val; + } + + if (!active) { + if (hw->mac_type == e1000_ich8lan) { + phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; + E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); + } else if (hw->mac_type == e1000_igb) { + phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; + E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl); + } else { + phy_data &= ~IGP02E1000_PM_D0_LPLU; + ret_val = e1000_write_phy_reg(hw, + IGP02E1000_PHY_POWER_MGMT, phy_data); + if (ret_val) + return ret_val; + } + + if (hw->mac_type == e1000_igb) + return E1000_SUCCESS; + + /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during + * Dx states where the power conservation is most important. During + * driver activity we should enable SmartSpeed, so performance is + * maintained. */ + if (hw->smart_speed == e1000_smart_speed_on) { + ret_val = e1000_read_phy_reg(hw, + IGP01E1000_PHY_PORT_CONFIG, &phy_data); + if (ret_val) + return ret_val; + + phy_data |= IGP01E1000_PSCFR_SMART_SPEED; + ret_val = e1000_write_phy_reg(hw, + IGP01E1000_PHY_PORT_CONFIG, phy_data); + if (ret_val) + return ret_val; + } else if (hw->smart_speed == e1000_smart_speed_off) { + ret_val = e1000_read_phy_reg(hw, + IGP01E1000_PHY_PORT_CONFIG, &phy_data); + if (ret_val) + return ret_val; + + phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; + ret_val = e1000_write_phy_reg(hw, + IGP01E1000_PHY_PORT_CONFIG, phy_data); + if (ret_val) + return ret_val; + } + + + } else { + + if (hw->mac_type == e1000_ich8lan) { + phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; + E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); + } else if (hw->mac_type == e1000_igb) { + phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; + E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl); + } else { + phy_data |= IGP02E1000_PM_D0_LPLU; + ret_val = e1000_write_phy_reg(hw, + IGP02E1000_PHY_POWER_MGMT, phy_data); + if (ret_val) + return ret_val; + } + + if (hw->mac_type == e1000_igb) + return E1000_SUCCESS; + + /* When LPLU is enabled we should disable SmartSpeed */ + ret_val = e1000_read_phy_reg(hw, + IGP01E1000_PHY_PORT_CONFIG, &phy_data); + if (ret_val) + return ret_val; + + phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; + ret_val = e1000_write_phy_reg(hw, + IGP01E1000_PHY_PORT_CONFIG, phy_data); + if (ret_val) + return ret_val; + + } + return E1000_SUCCESS; +} + +/******************************************************************** +* Copper link setup for e1000_phy_igp series. +* +* hw - Struct containing variables accessed by shared code +*********************************************************************/ +static int32_t +e1000_copper_link_igp_setup(struct e1000_hw *hw) +{ + uint32_t led_ctrl; + int32_t ret_val; + uint16_t phy_data; + + DEBUGFUNC(); + + if (hw->phy_reset_disable) + return E1000_SUCCESS; + + ret_val = e1000_phy_reset(hw); + if (ret_val) { + DEBUGOUT("Error Resetting the PHY\n"); + return ret_val; + } + + /* Wait 15ms for MAC to configure PHY from eeprom settings */ + mdelay(15); + if (hw->mac_type != e1000_ich8lan) { + /* Configure activity LED after PHY reset */ + led_ctrl = E1000_READ_REG(hw, LEDCTL); + led_ctrl &= IGP_ACTIVITY_LED_MASK; + led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); + E1000_WRITE_REG(hw, LEDCTL, led_ctrl); + } + + /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */ + if (hw->phy_type == e1000_phy_igp) { + /* disable lplu d3 during driver init */ + ret_val = e1000_set_d3_lplu_state(hw, false); + if (ret_val) { + DEBUGOUT("Error Disabling LPLU D3\n"); + return ret_val; + } + } + + /* disable lplu d0 during driver init */ + ret_val = e1000_set_d0_lplu_state(hw, false); + if (ret_val) { + DEBUGOUT("Error Disabling LPLU D0\n"); + return ret_val; + } + /* Configure mdi-mdix settings */ + ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); + if (ret_val) + return ret_val; + + if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { + hw->dsp_config_state = e1000_dsp_config_disabled; + /* Force MDI for earlier revs of the IGP PHY */ + phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX + | IGP01E1000_PSCR_FORCE_MDI_MDIX); + hw->mdix = 1; + + } else { + hw->dsp_config_state = e1000_dsp_config_enabled; + phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; + + switch (hw->mdix) { + case 1: + phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; + break; + case 2: + phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; + break; + case 0: + default: + phy_data |= IGP01E1000_PSCR_AUTO_MDIX; + break; + } + } + ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); + if (ret_val) + return ret_val; + + /* set auto-master slave resolution settings */ + if (hw->autoneg) { + e1000_ms_type phy_ms_setting = hw->master_slave; + + if (hw->ffe_config_state == e1000_ffe_config_active) + hw->ffe_config_state = e1000_ffe_config_enabled; + + if (hw->dsp_config_state == e1000_dsp_config_activated) + hw->dsp_config_state = e1000_dsp_config_enabled; + + /* when autonegotiation advertisment is only 1000Mbps then we + * should disable SmartSpeed and enable Auto MasterSlave + * resolution as hardware default. */ + if (hw->autoneg_advertised == ADVERTISE_1000_FULL) { + /* Disable SmartSpeed */ + ret_val = e1000_read_phy_reg(hw, + IGP01E1000_PHY_PORT_CONFIG, &phy_data); + if (ret_val) + return ret_val; + phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; + ret_val = e1000_write_phy_reg(hw, + IGP01E1000_PHY_PORT_CONFIG, phy_data); + if (ret_val) + return ret_val; + /* Set auto Master/Slave resolution process */ + ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, + &phy_data); + if (ret_val) + return ret_val; + phy_data &= ~CR_1000T_MS_ENABLE; + ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, + phy_data); + if (ret_val) + return ret_val; + } + + ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); + if (ret_val) + return ret_val; + + /* load defaults for future use */ + hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ? + ((phy_data & CR_1000T_MS_VALUE) ? + e1000_ms_force_master : + e1000_ms_force_slave) : + e1000_ms_auto; + + switch (phy_ms_setting) { + case e1000_ms_force_master: + phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); + break; + case e1000_ms_force_slave: + phy_data |= CR_1000T_MS_ENABLE; + phy_data &= ~(CR_1000T_MS_VALUE); + break; + case e1000_ms_auto: + phy_data &= ~CR_1000T_MS_ENABLE; + default: + break; + } + ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); + if (ret_val) + return ret_val; + } + + return E1000_SUCCESS; +} + +/***************************************************************************** + * This function checks the mode of the firmware. + * + * returns - true when the mode is IAMT or false. + ****************************************************************************/ +bool +e1000_check_mng_mode(struct e1000_hw *hw) +{ + uint32_t fwsm; + DEBUGFUNC(); + + fwsm = E1000_READ_REG(hw, FWSM); + + if (hw->mac_type == e1000_ich8lan) { + if ((fwsm & E1000_FWSM_MODE_MASK) == + (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) + return true; + } else if ((fwsm & E1000_FWSM_MODE_MASK) == + (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) + return true; + + return false; +} + +static int32_t +e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data) +{ + uint16_t swfw = E1000_SWFW_PHY0_SM; + uint32_t reg_val; + DEBUGFUNC(); + + if (e1000_is_second_port(hw)) + swfw = E1000_SWFW_PHY1_SM; + + if (e1000_swfw_sync_acquire(hw, swfw)) + return -E1000_ERR_SWFW_SYNC; + + reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) + & E1000_KUMCTRLSTA_OFFSET) | data; + E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); + udelay(2); + + return E1000_SUCCESS; +} + +static int32_t +e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data) +{ + uint16_t swfw = E1000_SWFW_PHY0_SM; + uint32_t reg_val; + DEBUGFUNC(); + + if (e1000_is_second_port(hw)) + swfw = E1000_SWFW_PHY1_SM; + + if (e1000_swfw_sync_acquire(hw, swfw)) { + debug("%s[%i]\n", __func__, __LINE__); + return -E1000_ERR_SWFW_SYNC; + } + + /* Write register address */ + reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) & + E1000_KUMCTRLSTA_OFFSET) | E1000_KUMCTRLSTA_REN; + E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); + udelay(2); + + /* Read the data returned */ + reg_val = E1000_READ_REG(hw, KUMCTRLSTA); + *data = (uint16_t)reg_val; + + return E1000_SUCCESS; +} + +/******************************************************************** +* Copper link setup for e1000_phy_gg82563 series. +* +* hw - Struct containing variables accessed by shared code +*********************************************************************/ +static int32_t +e1000_copper_link_ggp_setup(struct e1000_hw *hw) +{ + int32_t ret_val; + uint16_t phy_data; + uint32_t reg_data; + + DEBUGFUNC(); + + if (!hw->phy_reset_disable) { + /* Enable CRS on TX for half-duplex operation. */ + ret_val = e1000_read_phy_reg(hw, + GG82563_PHY_MAC_SPEC_CTRL, &phy_data); + if (ret_val) + return ret_val; + + phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; + /* Use 25MHz for both link down and 1000BASE-T for Tx clock */ + phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ; + + ret_val = e1000_write_phy_reg(hw, + GG82563_PHY_MAC_SPEC_CTRL, phy_data); + if (ret_val) + return ret_val; + + /* Options: + * MDI/MDI-X = 0 (default) + * 0 - Auto for all speeds + * 1 - MDI mode + * 2 - MDI-X mode + * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) + */ + ret_val = e1000_read_phy_reg(hw, + GG82563_PHY_SPEC_CTRL, &phy_data); + if (ret_val) + return ret_val; + + phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK; + + switch (hw->mdix) { + case 1: + phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI; + break; + case 2: + phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX; + break; + case 0: + default: + phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO; + break; + } + + /* Options: + * disable_polarity_correction = 0 (default) + * Automatic Correction for Reversed Cable Polarity + * 0 - Disabled + * 1 - Enabled + */ + phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE; + ret_val = e1000_write_phy_reg(hw, + GG82563_PHY_SPEC_CTRL, phy_data); + + if (ret_val) + return ret_val; + + /* SW Reset the PHY so all changes take effect */ + ret_val = e1000_phy_reset(hw); + if (ret_val) { + DEBUGOUT("Error Resetting the PHY\n"); + return ret_val; + } + } /* phy_reset_disable */ + + if (hw->mac_type == e1000_80003es2lan) { + /* Bypass RX and TX FIFO's */ + ret_val = e1000_write_kmrn_reg(hw, + E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL, + E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS + | E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS); + if (ret_val) + return ret_val; + + ret_val = e1000_read_phy_reg(hw, + GG82563_PHY_SPEC_CTRL_2, &phy_data); + if (ret_val) + return ret_val; + + phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG; + ret_val = e1000_write_phy_reg(hw, + GG82563_PHY_SPEC_CTRL_2, phy_data); + + if (ret_val) + return ret_val; + + reg_data = E1000_READ_REG(hw, CTRL_EXT); + reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK); + E1000_WRITE_REG(hw, CTRL_EXT, reg_data); + + ret_val = e1000_read_phy_reg(hw, + GG82563_PHY_PWR_MGMT_CTRL, &phy_data); + if (ret_val) + return ret_val; + + /* Do not init these registers when the HW is in IAMT mode, since the + * firmware will have already initialized them. We only initialize + * them if the HW is not in IAMT mode. + */ + if (e1000_check_mng_mode(hw) == false) { + /* Enable Electrical Idle on the PHY */ + phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE; + ret_val = e1000_write_phy_reg(hw, + GG82563_PHY_PWR_MGMT_CTRL, phy_data); + if (ret_val) + return ret_val; + + ret_val = e1000_read_phy_reg(hw, + GG82563_PHY_KMRN_MODE_CTRL, &phy_data); + if (ret_val) + return ret_val; + + phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; + ret_val = e1000_write_phy_reg(hw, + GG82563_PHY_KMRN_MODE_CTRL, phy_data); + + if (ret_val) + return ret_val; + } + + /* Workaround: Disable padding in Kumeran interface in the MAC + * and in the PHY to avoid CRC errors. + */ + ret_val = e1000_read_phy_reg(hw, + GG82563_PHY_INBAND_CTRL, &phy_data); + if (ret_val) + return ret_val; + phy_data |= GG82563_ICR_DIS_PADDING; + ret_val = e1000_write_phy_reg(hw, + GG82563_PHY_INBAND_CTRL, phy_data); + if (ret_val) + return ret_val; + } + return E1000_SUCCESS; +} + +/******************************************************************** +* Copper link setup for e1000_phy_m88 series. +* +* hw - Struct containing variables accessed by shared code +*********************************************************************/ +static int32_t +e1000_copper_link_mgp_setup(struct e1000_hw *hw) +{ + int32_t ret_val; + uint16_t phy_data; + + DEBUGFUNC(); + + if (hw->phy_reset_disable) + return E1000_SUCCESS; + + /* Enable CRS on TX. This must be set for half-duplex operation. */ + ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); + if (ret_val) + return ret_val; + + phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; + + /* Options: + * MDI/MDI-X = 0 (default) + * 0 - Auto for all speeds + * 1 - MDI mode + * 2 - MDI-X mode + * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) + */ + phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; + + switch (hw->mdix) { + case 1: + phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; + break; + case 2: + phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; + break; + case 3: + phy_data |= M88E1000_PSCR_AUTO_X_1000T; + break; + case 0: + default: + phy_data |= M88E1000_PSCR_AUTO_X_MODE; + break; + } + + /* Options: + * disable_polarity_correction = 0 (default) + * Automatic Correction for Reversed Cable Polarity + * 0 - Disabled + * 1 - Enabled + */ + phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; + ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); + if (ret_val) + return ret_val; + + if (hw->phy_revision < M88E1011_I_REV_4) { + /* Force TX_CLK in the Extended PHY Specific Control Register + * to 25MHz clock. + */ + ret_val = e1000_read_phy_reg(hw, + M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); + if (ret_val) + return ret_val; + + phy_data |= M88E1000_EPSCR_TX_CLK_25; + + if ((hw->phy_revision == E1000_REVISION_2) && + (hw->phy_id == M88E1111_I_PHY_ID)) { + /* Vidalia Phy, set the downshift counter to 5x */ + phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK); + phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; + ret_val = e1000_write_phy_reg(hw, + M88E1000_EXT_PHY_SPEC_CTRL, phy_data); + if (ret_val) + return ret_val; + } else { + /* Configure Master and Slave downshift values */ + phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK + | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); + phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X + | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); + ret_val = e1000_write_phy_reg(hw, + M88E1000_EXT_PHY_SPEC_CTRL, phy_data); + if (ret_val) + return ret_val; + } + } + + /* SW Reset the PHY so all changes take effect */ + ret_val = e1000_phy_reset(hw); + if (ret_val) { + DEBUGOUT("Error Resetting the PHY\n"); + return ret_val; + } + + return E1000_SUCCESS; +} + +/******************************************************************** +* Setup auto-negotiation and flow control advertisements, +* and then perform auto-negotiation. +* +* hw - Struct containing variables accessed by shared code +*********************************************************************/ +static int32_t +e1000_copper_link_autoneg(struct e1000_hw *hw) +{ + int32_t ret_val; + uint16_t phy_data; + + DEBUGFUNC(); + + /* Perform some bounds checking on the hw->autoneg_advertised + * parameter. If this variable is zero, then set it to the default. + */ + hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT; + + /* If autoneg_advertised is zero, we assume it was not defaulted + * by the calling code so we set to advertise full capability. + */ + if (hw->autoneg_advertised == 0) + hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; + + /* IFE phy only supports 10/100 */ + if (hw->phy_type == e1000_phy_ife) + hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL; + + DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); + ret_val = e1000_phy_setup_autoneg(hw); + if (ret_val) { + DEBUGOUT("Error Setting up Auto-Negotiation\n"); + return ret_val; + } + DEBUGOUT("Restarting Auto-Neg\n"); + + /* Restart auto-negotiation by setting the Auto Neg Enable bit and + * the Auto Neg Restart bit in the PHY control register. + */ + ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); + if (ret_val) + return ret_val; + + phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); + ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); + if (ret_val) + return ret_val; + + /* Does the user want to wait for Auto-Neg to complete here, or + * check at a later time (for example, callback routine). + */ + /* If we do not wait for autonegtation to complete I + * do not see a valid link status. + * wait_autoneg_complete = 1 . + */ + if (hw->wait_autoneg_complete) { + ret_val = e1000_wait_autoneg(hw); + if (ret_val) { + DEBUGOUT("Error while waiting for autoneg" + "to complete\n"); + return ret_val; + } + } + + hw->get_link_status = true; + + return E1000_SUCCESS; +} + +/****************************************************************************** +* Config the MAC and the PHY after link is up. +* 1) Set up the MAC to the current PHY speed/duplex +* if we are on 82543. If we +* are on newer silicon, we only need to configure +* collision distance in the Transmit Control Register. +* 2) Set up flow control on the MAC to that established with +* the link partner. +* 3) Config DSP to improve Gigabit link quality for some PHY revisions. +* +* hw - Struct containing variables accessed by shared code +******************************************************************************/ +static int32_t +e1000_copper_link_postconfig(struct e1000_hw *hw) +{ + int32_t ret_val; + DEBUGFUNC(); + + if (hw->mac_type >= e1000_82544) { + e1000_config_collision_dist(hw); + } else { + ret_val = e1000_config_mac_to_phy(hw); + if (ret_val) { + DEBUGOUT("Error configuring MAC to PHY settings\n"); + return ret_val; + } + } + ret_val = e1000_config_fc_after_link_up(hw); + if (ret_val) { + DEBUGOUT("Error Configuring Flow Control\n"); + return ret_val; + } + return E1000_SUCCESS; +} + +/****************************************************************************** +* Detects which PHY is present and setup the speed and duplex +* +* hw - Struct containing variables accessed by shared code +******************************************************************************/ +static int +e1000_setup_copper_link(struct e1000_hw *hw) +{ + int32_t ret_val; + uint16_t i; + uint16_t phy_data; + uint16_t reg_data; + + DEBUGFUNC(); + + switch (hw->mac_type) { + case e1000_80003es2lan: + case e1000_ich8lan: + /* Set the mac to wait the maximum time between each + * iteration and increase the max iterations when + * polling the phy; this fixes erroneous timeouts at 10Mbps. */ + ret_val = e1000_write_kmrn_reg(hw, + GG82563_REG(0x34, 4), 0xFFFF); + if (ret_val) + return ret_val; + ret_val = e1000_read_kmrn_reg(hw, + GG82563_REG(0x34, 9), ®_data); + if (ret_val) + return ret_val; + reg_data |= 0x3F; + ret_val = e1000_write_kmrn_reg(hw, + GG82563_REG(0x34, 9), reg_data); + if (ret_val) + return ret_val; + default: + break; + } + + /* Check if it is a valid PHY and set PHY mode if necessary. */ + ret_val = e1000_copper_link_preconfig(hw); + if (ret_val) + return ret_val; + switch (hw->mac_type) { + case e1000_80003es2lan: + /* Kumeran registers are written-only */ + reg_data = + E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT; + reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING; + ret_val = e1000_write_kmrn_reg(hw, + E1000_KUMCTRLSTA_OFFSET_INB_CTRL, reg_data); + if (ret_val) + return ret_val; + break; + default: + break; + } + + if (hw->phy_type == e1000_phy_igp || + hw->phy_type == e1000_phy_igp_3 || + hw->phy_type == e1000_phy_igp_2) { + ret_val = e1000_copper_link_igp_setup(hw); + if (ret_val) + return ret_val; + } else if (hw->phy_type == e1000_phy_m88 || + hw->phy_type == e1000_phy_igb) { + ret_val = e1000_copper_link_mgp_setup(hw); + if (ret_val) + return ret_val; + } else if (hw->phy_type == e1000_phy_gg82563) { + ret_val = e1000_copper_link_ggp_setup(hw); + if (ret_val) + return ret_val; + } + + /* always auto */ + /* Setup autoneg and flow control advertisement + * and perform autonegotiation */ + ret_val = e1000_copper_link_autoneg(hw); + if (ret_val) + return ret_val; + + /* Check link status. Wait up to 100 microseconds for link to become + * valid. + */ + for (i = 0; i < 10; i++) { + ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); + if (ret_val) + return ret_val; + ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); + if (ret_val) + return ret_val; + + if (phy_data & MII_SR_LINK_STATUS) { + /* Config the MAC and PHY after link is up */ + ret_val = e1000_copper_link_postconfig(hw); + if (ret_val) + return ret_val; + + DEBUGOUT("Valid link established!!!\n"); + return E1000_SUCCESS; + } + udelay(10); + } + + DEBUGOUT("Unable to establish link!!!\n"); + return E1000_SUCCESS; +} + +/****************************************************************************** +* Configures PHY autoneg and flow control advertisement settings +* +* hw - Struct containing variables accessed by shared code +******************************************************************************/ +int32_t +e1000_phy_setup_autoneg(struct e1000_hw *hw) +{ + int32_t ret_val; + uint16_t mii_autoneg_adv_reg; + uint16_t mii_1000t_ctrl_reg; + + DEBUGFUNC(); + + /* Read the MII Auto-Neg Advertisement Register (Address 4). */ + ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); + if (ret_val) + return ret_val; + + if (hw->phy_type != e1000_phy_ife) { + /* Read the MII 1000Base-T Control Register (Address 9). */ + ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, + &mii_1000t_ctrl_reg); + if (ret_val) + return ret_val; + } else + mii_1000t_ctrl_reg = 0; + + /* Need to parse both autoneg_advertised and fc and set up + * the appropriate PHY registers. First we will parse for + * autoneg_advertised software override. Since we can advertise + * a plethora of combinations, we need to check each bit + * individually. + */ + + /* First we clear all the 10/100 mb speed bits in the Auto-Neg + * Advertisement Register (Address 4) and the 1000 mb speed bits in + * the 1000Base-T Control Register (Address 9). + */ + mii_autoneg_adv_reg &= ~REG4_SPEED_MASK; + mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK; + + DEBUGOUT("autoneg_advertised %x\n", hw->autoneg_advertised); + + /* Do we want to advertise 10 Mb Half Duplex? */ + if (hw->autoneg_advertised & ADVERTISE_10_HALF) { + DEBUGOUT("Advertise 10mb Half duplex\n"); + mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; + } + + /* Do we want to advertise 10 Mb Full Duplex? */ + if (hw->autoneg_advertised & ADVERTISE_10_FULL) { + DEBUGOUT("Advertise 10mb Full duplex\n"); + mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; + } + + /* Do we want to advertise 100 Mb Half Duplex? */ + if (hw->autoneg_advertised & ADVERTISE_100_HALF) { + DEBUGOUT("Advertise 100mb Half duplex\n"); + mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; + } + + /* Do we want to advertise 100 Mb Full Duplex? */ + if (hw->autoneg_advertised & ADVERTISE_100_FULL) { + DEBUGOUT("Advertise 100mb Full duplex\n"); + mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; + } + + /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ + if (hw->autoneg_advertised & ADVERTISE_1000_HALF) { + DEBUGOUT + ("Advertise 1000mb Half duplex requested, request denied!\n"); + } + + /* Do we want to advertise 1000 Mb Full Duplex? */ + if (hw->autoneg_advertised & ADVERTISE_1000_FULL) { + DEBUGOUT("Advertise 1000mb Full duplex\n"); + mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; + } + + /* Check for a software override of the flow control settings, and + * setup the PHY advertisement registers accordingly. If + * auto-negotiation is enabled, then software will have to set the + * "PAUSE" bits to the correct value in the Auto-Negotiation + * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation. + * + * The possible values of the "fc" parameter are: + * 0: Flow control is completely disabled + * 1: Rx flow control is enabled (we can receive pause frames + * but not send pause frames). + * 2: Tx flow control is enabled (we can send pause frames + * but we do not support receiving pause frames). + * 3: Both Rx and TX flow control (symmetric) are enabled. + * other: No software override. The flow control configuration + * in the EEPROM is used. + */ + switch (hw->fc) { + case e1000_fc_none: /* 0 */ + /* Flow control (RX & TX) is completely disabled by a + * software over-ride. + */ + mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); + break; + case e1000_fc_rx_pause: /* 1 */ + /* RX Flow control is enabled, and TX Flow control is + * disabled, by a software over-ride. + */ + /* Since there really isn't a way to advertise that we are + * capable of RX Pause ONLY, we will advertise that we + * support both symmetric and asymmetric RX PAUSE. Later + * (in e1000_config_fc_after_link_up) we will disable the + *hw's ability to send PAUSE frames. + */ + mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); + break; + case e1000_fc_tx_pause: /* 2 */ + /* TX Flow control is enabled, and RX Flow control is + * disabled, by a software over-ride. + */ + mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; + mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; + break; + case e1000_fc_full: /* 3 */ + /* Flow control (both RX and TX) is enabled by a software + * over-ride. + */ + mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); + break; + default: + DEBUGOUT("Flow control param set incorrectly\n"); + return -E1000_ERR_CONFIG; + } + + ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); + if (ret_val) + return ret_val; + + DEBUGOUT("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); + + if (hw->phy_type != e1000_phy_ife) { + ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, + mii_1000t_ctrl_reg); + if (ret_val) + return ret_val; + } + + return E1000_SUCCESS; +} + +/****************************************************************************** +* Sets the collision distance in the Transmit Control register +* +* hw - Struct containing variables accessed by shared code +* +* Link should have been established previously. Reads the speed and duplex +* information from the Device Status register. +******************************************************************************/ +static void +e1000_config_collision_dist(struct e1000_hw *hw) +{ + uint32_t tctl, coll_dist; + + DEBUGFUNC(); + + if (hw->mac_type < e1000_82543) + coll_dist = E1000_COLLISION_DISTANCE_82542; + else + coll_dist = E1000_COLLISION_DISTANCE; + + tctl = E1000_READ_REG(hw, TCTL); + + tctl &= ~E1000_TCTL_COLD; + tctl |= coll_dist << E1000_COLD_SHIFT; + + E1000_WRITE_REG(hw, TCTL, tctl); + E1000_WRITE_FLUSH(hw); +} + +/****************************************************************************** +* Sets MAC speed and duplex settings to reflect the those in the PHY +* +* hw - Struct containing variables accessed by shared code +* mii_reg - data to write to the MII control register +* +* The contents of the PHY register containing the needed information need to +* be passed in. +******************************************************************************/ +static int +e1000_config_mac_to_phy(struct e1000_hw *hw) +{ + uint32_t ctrl; + uint16_t phy_data; + + DEBUGFUNC(); + + /* Read the Device Control Register and set the bits to Force Speed + * and Duplex. + */ + ctrl = E1000_READ_REG(hw, CTRL); + ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); + ctrl &= ~(E1000_CTRL_ILOS); + ctrl |= (E1000_CTRL_SPD_SEL); + + /* Set up duplex in the Device Control and Transmit Control + * registers depending on negotiated values. + */ + if (e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) { + DEBUGOUT("PHY Read Error\n"); + return -E1000_ERR_PHY; + } + if (phy_data & M88E1000_PSSR_DPLX) + ctrl |= E1000_CTRL_FD; + else + ctrl &= ~E1000_CTRL_FD; + + e1000_config_collision_dist(hw); + + /* Set up speed in the Device Control register depending on + * negotiated values. + */ + if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) + ctrl |= E1000_CTRL_SPD_1000; + else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) + ctrl |= E1000_CTRL_SPD_100; + /* Write the configured values back to the Device Control Reg. */ + E1000_WRITE_REG(hw, CTRL, ctrl); + return 0; +} + +/****************************************************************************** + * Forces the MAC's flow control settings. + * + * hw - Struct containing variables accessed by shared code + * + * Sets the TFCE and RFCE bits in the device control register to reflect + * the adapter settings. TFCE and RFCE need to be explicitly set by + * software when a Copper PHY is used because autonegotiation is managed + * by the PHY rather than the MAC. Software must also configure these + * bits when link is forced on a fiber connection. + *****************************************************************************/ +static int +e1000_force_mac_fc(struct e1000_hw *hw) +{ + uint32_t ctrl; + + DEBUGFUNC(); + + /* Get the current configuration of the Device Control Register */ + ctrl = E1000_READ_REG(hw, CTRL); + + /* Because we didn't get link via the internal auto-negotiation + * mechanism (we either forced link or we got link via PHY + * auto-neg), we have to manually enable/disable transmit an + * receive flow control. + * + * The "Case" statement below enables/disable flow control + * according to the "hw->fc" parameter. + * + * The possible values of the "fc" parameter are: + * 0: Flow control is completely disabled + * 1: Rx flow control is enabled (we can receive pause + * frames but not send pause frames). + * 2: Tx flow control is enabled (we can send pause frames + * frames but we do not receive pause frames). + * 3: Both Rx and TX flow control (symmetric) is enabled. + * other: No other values should be possible at this point. + */ + + switch (hw->fc) { + case e1000_fc_none: + ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); + break; + case e1000_fc_rx_pause: + ctrl &= (~E1000_CTRL_TFCE); + ctrl |= E1000_CTRL_RFCE; + break; + case e1000_fc_tx_pause: + ctrl &= (~E1000_CTRL_RFCE); + ctrl |= E1000_CTRL_TFCE; + break; + case e1000_fc_full: + ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); + break; + default: + DEBUGOUT("Flow control param set incorrectly\n"); + return -E1000_ERR_CONFIG; + } + + /* Disable TX Flow Control for 82542 (rev 2.0) */ + if (hw->mac_type == e1000_82542_rev2_0) + ctrl &= (~E1000_CTRL_TFCE); + + E1000_WRITE_REG(hw, CTRL, ctrl); + return 0; +} + +/****************************************************************************** + * Configures flow control settings after link is established + * + * hw - Struct containing variables accessed by shared code + * + * Should be called immediately after a valid link has been established. + * Forces MAC flow control settings if link was forced. When in MII/GMII mode + * and autonegotiation is enabled, the MAC flow control settings will be set + * based on the flow control negotiated by the PHY. In TBI mode, the TFCE + * and RFCE bits will be automaticaly set to the negotiated flow control mode. + *****************************************************************************/ +static int32_t +e1000_config_fc_after_link_up(struct e1000_hw *hw) +{ + int32_t ret_val; + uint16_t mii_status_reg; + uint16_t mii_nway_adv_reg; + uint16_t mii_nway_lp_ability_reg; + uint16_t speed; + uint16_t duplex; + + DEBUGFUNC(); + + /* Check for the case where we have fiber media and auto-neg failed + * so we had to force link. In this case, we need to force the + * configuration of the MAC to match the "fc" parameter. + */ + if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) + || ((hw->media_type == e1000_media_type_internal_serdes) + && (hw->autoneg_failed)) + || ((hw->media_type == e1000_media_type_copper) + && (!hw->autoneg))) { + ret_val = e1000_force_mac_fc(hw); + if (ret_val < 0) { + DEBUGOUT("Error forcing flow control settings\n"); + return ret_val; + } + } + + /* Check for the case where we have copper media and auto-neg is + * enabled. In this case, we need to check and see if Auto-Neg + * has completed, and if so, how the PHY and link partner has + * flow control configured. + */ + if (hw->media_type == e1000_media_type_copper) { + /* Read the MII Status Register and check to see if AutoNeg + * has completed. We read this twice because this reg has + * some "sticky" (latched) bits. + */ + if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) { + DEBUGOUT("PHY Read Error\n"); + return -E1000_ERR_PHY; + } + if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) { + DEBUGOUT("PHY Read Error\n"); + return -E1000_ERR_PHY; + } + + if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) { + /* The AutoNeg process has completed, so we now need to + * read both the Auto Negotiation Advertisement Register + * (Address 4) and the Auto_Negotiation Base Page Ability + * Register (Address 5) to determine how flow control was + * negotiated. + */ + if (e1000_read_phy_reg + (hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg) < 0) { + DEBUGOUT("PHY Read Error\n"); + return -E1000_ERR_PHY; + } + if (e1000_read_phy_reg + (hw, PHY_LP_ABILITY, + &mii_nway_lp_ability_reg) < 0) { + DEBUGOUT("PHY Read Error\n"); + return -E1000_ERR_PHY; + } + + /* Two bits in the Auto Negotiation Advertisement Register + * (Address 4) and two bits in the Auto Negotiation Base + * Page Ability Register (Address 5) determine flow control + * for both the PHY and the link partner. The following + * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, + * 1999, describes these PAUSE resolution bits and how flow + * control is determined based upon these settings. + * NOTE: DC = Don't Care + * + * LOCAL DEVICE | LINK PARTNER + * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution + *-------|---------|-------|---------|-------------------- + * 0 | 0 | DC | DC | e1000_fc_none + * 0 | 1 | 0 | DC | e1000_fc_none + * 0 | 1 | 1 | 0 | e1000_fc_none + * 0 | 1 | 1 | 1 | e1000_fc_tx_pause + * 1 | 0 | 0 | DC | e1000_fc_none + * 1 | DC | 1 | DC | e1000_fc_full + * 1 | 1 | 0 | 0 | e1000_fc_none + * 1 | 1 | 0 | 1 | e1000_fc_rx_pause + * + */ + /* Are both PAUSE bits set to 1? If so, this implies + * Symmetric Flow Control is enabled at both ends. The + * ASM_DIR bits are irrelevant per the spec. + * + * For Symmetric Flow Control: + * + * LOCAL DEVICE | LINK PARTNER + * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result + *-------|---------|-------|---------|-------------------- + * 1 | DC | 1 | DC | e1000_fc_full + * + */ + if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && + (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { + /* Now we need to check if the user selected RX ONLY + * of pause frames. In this case, we had to advertise + * FULL flow control because we could not advertise RX + * ONLY. Hence, we must now check to see if we need to + * turn OFF the TRANSMISSION of PAUSE frames. + */ + if (hw->original_fc == e1000_fc_full) { + hw->fc = e1000_fc_full; + DEBUGOUT("Flow Control = FULL.\r\n"); + } else { + hw->fc = e1000_fc_rx_pause; + DEBUGOUT + ("Flow Control = RX PAUSE frames only.\r\n"); + } + } + /* For receiving PAUSE frames ONLY. + * + * LOCAL DEVICE | LINK PARTNER + * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result + *-------|---------|-------|---------|-------------------- + * 0 | 1 | 1 | 1 | e1000_fc_tx_pause + * + */ + else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && + (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && + (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && + (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) + { + hw->fc = e1000_fc_tx_pause; + DEBUGOUT + ("Flow Control = TX PAUSE frames only.\r\n"); + } + /* For transmitting PAUSE frames ONLY. + * + * LOCAL DEVICE | LINK PARTNER + * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result + *-------|---------|-------|---------|-------------------- + * 1 | 1 | 0 | 1 | e1000_fc_rx_pause + * + */ + else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && + (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && + !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && + (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) + { + hw->fc = e1000_fc_rx_pause; + DEBUGOUT + ("Flow Control = RX PAUSE frames only.\r\n"); + } + /* Per the IEEE spec, at this point flow control should be + * disabled. However, we want to consider that we could + * be connected to a legacy switch that doesn't advertise + * desired flow control, but can be forced on the link + * partner. So if we advertised no flow control, that is + * what we will resolve to. If we advertised some kind of + * receive capability (Rx Pause Only or Full Flow Control) + * and the link partner advertised none, we will configure + * ourselves to enable Rx Flow Control only. We can do + * this safely for two reasons: If the link partner really + * didn't want flow control enabled, and we enable Rx, no + * harm done since we won't be receiving any PAUSE frames + * anyway. If the intent on the link partner was to have + * flow control enabled, then by us enabling RX only, we + * can at least receive pause frames and process them. + * This is a good idea because in most cases, since we are + * predominantly a server NIC, more times than not we will + * be asked to delay transmission of packets than asking + * our link partner to pause transmission of frames. + */ + else if (hw->original_fc == e1000_fc_none || + hw->original_fc == e1000_fc_tx_pause) { + hw->fc = e1000_fc_none; + DEBUGOUT("Flow Control = NONE.\r\n"); + } else { + hw->fc = e1000_fc_rx_pause; + DEBUGOUT + ("Flow Control = RX PAUSE frames only.\r\n"); + } + + /* Now we need to do one last check... If we auto- + * negotiated to HALF DUPLEX, flow control should not be + * enabled per IEEE 802.3 spec. + */ + e1000_get_speed_and_duplex(hw, &speed, &duplex); + + if (duplex == HALF_DUPLEX) + hw->fc = e1000_fc_none; + + /* Now we call a subroutine to actually force the MAC + * controller to use the correct flow control settings. + */ + ret_val = e1000_force_mac_fc(hw); + if (ret_val < 0) { + DEBUGOUT + ("Error forcing flow control settings\n"); + return ret_val; + } + } else { + DEBUGOUT + ("Copper PHY and Auto Neg has not completed.\r\n"); + } + } + return E1000_SUCCESS; +} + +/****************************************************************************** + * Checks to see if the link status of the hardware has changed. + * + * hw - Struct containing variables accessed by shared code + * + * Called by any function that needs to check the link status of the adapter. + *****************************************************************************/ +static int +e1000_check_for_link(struct e1000_hw *hw) +{ + uint32_t rxcw; + uint32_t ctrl; + uint32_t status; + uint32_t rctl; + uint32_t signal; + int32_t ret_val; + uint16_t phy_data; + uint16_t lp_capability; + + DEBUGFUNC(); + + /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be + * set when the optics detect a signal. On older adapters, it will be + * cleared when there is a signal + */ + ctrl = E1000_READ_REG(hw, CTRL); + if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS)) + signal = E1000_CTRL_SWDPIN1; + else + signal = 0; + + status = E1000_READ_REG(hw, STATUS); + rxcw = E1000_READ_REG(hw, RXCW); + DEBUGOUT("ctrl: %#08x status %#08x rxcw %#08x\n", ctrl, status, rxcw); + + /* If we have a copper PHY then we only want to go out to the PHY + * registers to see if Auto-Neg has completed and/or if our link + * status has changed. The get_link_status flag will be set if we + * receive a Link Status Change interrupt or we have Rx Sequence + * Errors. + */ + if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) { + /* First we want to see if the MII Status Register reports + * link. If so, then we want to get the current speed/duplex + * of the PHY. + * Read the register twice since the link bit is sticky. + */ + if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { + DEBUGOUT("PHY Read Error\n"); + return -E1000_ERR_PHY; + } + if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { + DEBUGOUT("PHY Read Error\n"); + return -E1000_ERR_PHY; + } + + if (phy_data & MII_SR_LINK_STATUS) { + hw->get_link_status = false; + } else { + /* No link detected */ + return -E1000_ERR_NOLINK; + } + + /* We have a M88E1000 PHY and Auto-Neg is enabled. If we + * have Si on board that is 82544 or newer, Auto + * Speed Detection takes care of MAC speed/duplex + * configuration. So we only need to configure Collision + * Distance in the MAC. Otherwise, we need to force + * speed/duplex on the MAC to the current PHY speed/duplex + * settings. + */ + if (hw->mac_type >= e1000_82544) + e1000_config_collision_dist(hw); + else { + ret_val = e1000_config_mac_to_phy(hw); + if (ret_val < 0) { + DEBUGOUT + ("Error configuring MAC to PHY settings\n"); + return ret_val; + } + } + + /* Configure Flow Control now that Auto-Neg has completed. First, we + * need to restore the desired flow control settings because we may + * have had to re-autoneg with a different link partner. + */ + ret_val = e1000_config_fc_after_link_up(hw); + if (ret_val < 0) { + DEBUGOUT("Error configuring flow control\n"); + return ret_val; + } + + /* At this point we know that we are on copper and we have + * auto-negotiated link. These are conditions for checking the link + * parter capability register. We use the link partner capability to + * determine if TBI Compatibility needs to be turned on or off. If + * the link partner advertises any speed in addition to Gigabit, then + * we assume that they are GMII-based, and TBI compatibility is not + * needed. If no other speeds are advertised, we assume the link + * partner is TBI-based, and we turn on TBI Compatibility. + */ + if (hw->tbi_compatibility_en) { + if (e1000_read_phy_reg + (hw, PHY_LP_ABILITY, &lp_capability) < 0) { + DEBUGOUT("PHY Read Error\n"); + return -E1000_ERR_PHY; + } + if (lp_capability & (NWAY_LPAR_10T_HD_CAPS | + NWAY_LPAR_10T_FD_CAPS | + NWAY_LPAR_100TX_HD_CAPS | + NWAY_LPAR_100TX_FD_CAPS | + NWAY_LPAR_100T4_CAPS)) { + /* If our link partner advertises anything in addition to + * gigabit, we do not need to enable TBI compatibility. + */ + if (hw->tbi_compatibility_on) { + /* If we previously were in the mode, turn it off. */ + rctl = E1000_READ_REG(hw, RCTL); + rctl &= ~E1000_RCTL_SBP; + E1000_WRITE_REG(hw, RCTL, rctl); + hw->tbi_compatibility_on = false; + } + } else { + /* If TBI compatibility is was previously off, turn it on. For + * compatibility with a TBI link partner, we will store bad + * packets. Some frames have an additional byte on the end and + * will look like CRC errors to to the hardware. + */ + if (!hw->tbi_compatibility_on) { + hw->tbi_compatibility_on = true; + rctl = E1000_READ_REG(hw, RCTL); + rctl |= E1000_RCTL_SBP; + E1000_WRITE_REG(hw, RCTL, rctl); + } + } + } + } + /* If we don't have link (auto-negotiation failed or link partner cannot + * auto-negotiate), the cable is plugged in (we have signal), and our + * link partner is not trying to auto-negotiate with us (we are receiving + * idles or data), we need to force link up. We also need to give + * auto-negotiation time to complete, in case the cable was just plugged + * in. The autoneg_failed flag does this. + */ + else if ((hw->media_type == e1000_media_type_fiber) && + (!(status & E1000_STATUS_LU)) && + ((ctrl & E1000_CTRL_SWDPIN1) == signal) && + (!(rxcw & E1000_RXCW_C))) { + if (hw->autoneg_failed == 0) { + hw->autoneg_failed = 1; + return 0; + } + DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n"); + + /* Disable auto-negotiation in the TXCW register */ + E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE)); + + /* Force link-up and also force full-duplex. */ + ctrl = E1000_READ_REG(hw, CTRL); + ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); + E1000_WRITE_REG(hw, CTRL, ctrl); + + /* Configure Flow Control after forcing link up. */ + ret_val = e1000_config_fc_after_link_up(hw); + if (ret_val < 0) { + DEBUGOUT("Error configuring flow control\n"); + return ret_val; + } + } + /* If we are forcing link and we are receiving /C/ ordered sets, re-enable + * auto-negotiation in the TXCW register and disable forced link in the + * Device Control register in an attempt to auto-negotiate with our link + * partner. + */ + else if ((hw->media_type == e1000_media_type_fiber) && + (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { + DEBUGOUT + ("RXing /C/, enable AutoNeg and stop forcing link.\r\n"); + E1000_WRITE_REG(hw, TXCW, hw->txcw); + E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU)); + } + return 0; +} + +/****************************************************************************** +* Configure the MAC-to-PHY interface for 10/100Mbps +* +* hw - Struct containing variables accessed by shared code +******************************************************************************/ +static int32_t +e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex) +{ + int32_t ret_val = E1000_SUCCESS; + uint32_t tipg; + uint16_t reg_data; + + DEBUGFUNC(); + + reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT; + ret_val = e1000_write_kmrn_reg(hw, + E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data); + if (ret_val) + return ret_val; + + /* Configure Transmit Inter-Packet Gap */ + tipg = E1000_READ_REG(hw, TIPG); + tipg &= ~E1000_TIPG_IPGT_MASK; + tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100; + E1000_WRITE_REG(hw, TIPG, tipg); + + ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); + + if (ret_val) + return ret_val; + + if (duplex == HALF_DUPLEX) + reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER; + else + reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; + + ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); + + return ret_val; +} + +static int32_t +e1000_configure_kmrn_for_1000(struct e1000_hw *hw) +{ + int32_t ret_val = E1000_SUCCESS; + uint16_t reg_data; + uint32_t tipg; + + DEBUGFUNC(); + + reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT; + ret_val = e1000_write_kmrn_reg(hw, + E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data); + if (ret_val) + return ret_val; + + /* Configure Transmit Inter-Packet Gap */ + tipg = E1000_READ_REG(hw, TIPG); + tipg &= ~E1000_TIPG_IPGT_MASK; + tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; + E1000_WRITE_REG(hw, TIPG, tipg); + + ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); + + if (ret_val) + return ret_val; + + reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; + ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); + + return ret_val; +} + +/****************************************************************************** + * Detects the current speed and duplex settings of the hardware. + * + * hw - Struct containing variables accessed by shared code + * speed - Speed of the connection + * duplex - Duplex setting of the connection + *****************************************************************************/ +static int +e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t *speed, + uint16_t *duplex) +{ + uint32_t status; + int32_t ret_val; + uint16_t phy_data; + + DEBUGFUNC(); + + if (hw->mac_type >= e1000_82543) { + status = E1000_READ_REG(hw, STATUS); + if (status & E1000_STATUS_SPEED_1000) { + *speed = SPEED_1000; + DEBUGOUT("1000 Mbs, "); + } else if (status & E1000_STATUS_SPEED_100) { + *speed = SPEED_100; + DEBUGOUT("100 Mbs, "); + } else { + *speed = SPEED_10; + DEBUGOUT("10 Mbs, "); + } + + if (status & E1000_STATUS_FD) { + *duplex = FULL_DUPLEX; + DEBUGOUT("Full Duplex\r\n"); + } else { + *duplex = HALF_DUPLEX; + DEBUGOUT(" Half Duplex\r\n"); + } + } else { + DEBUGOUT("1000 Mbs, Full Duplex\r\n"); + *speed = SPEED_1000; + *duplex = FULL_DUPLEX; + } + + /* IGP01 PHY may advertise full duplex operation after speed downgrade + * even if it is operating at half duplex. Here we set the duplex + * settings to match the duplex in the link partner's capabilities. + */ + if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) { + ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data); + if (ret_val) + return ret_val; + + if (!(phy_data & NWAY_ER_LP_NWAY_CAPS)) + *duplex = HALF_DUPLEX; + else { + ret_val = e1000_read_phy_reg(hw, + PHY_LP_ABILITY, &phy_data); + if (ret_val) + return ret_val; + if ((*speed == SPEED_100 && + !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) + || (*speed == SPEED_10 + && !(phy_data & NWAY_LPAR_10T_FD_CAPS))) + *duplex = HALF_DUPLEX; + } + } + + if ((hw->mac_type == e1000_80003es2lan) && + (hw->media_type == e1000_media_type_copper)) { + if (*speed == SPEED_1000) + ret_val = e1000_configure_kmrn_for_1000(hw); + else + ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex); + if (ret_val) + return ret_val; + } + return E1000_SUCCESS; +} + +/****************************************************************************** +* Blocks until autoneg completes or times out (~4.5 seconds) +* +* hw - Struct containing variables accessed by shared code +******************************************************************************/ +static int +e1000_wait_autoneg(struct e1000_hw *hw) +{ + uint16_t i; + uint16_t phy_data; + + DEBUGFUNC(); + DEBUGOUT("Waiting for Auto-Neg to complete.\n"); + + /* We will wait for autoneg to complete or timeout to expire. */ + for (i = PHY_AUTO_NEG_TIME; i > 0; i--) { + /* Read the MII Status Register and wait for Auto-Neg + * Complete bit to be set. + */ + if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { + DEBUGOUT("PHY Read Error\n"); + return -E1000_ERR_PHY; + } + if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { + DEBUGOUT("PHY Read Error\n"); + return -E1000_ERR_PHY; + } + if (phy_data & MII_SR_AUTONEG_COMPLETE) { + DEBUGOUT("Auto-Neg complete.\n"); + return 0; + } + mdelay(100); + } + DEBUGOUT("Auto-Neg timedout.\n"); + return -E1000_ERR_TIMEOUT; +} + +/****************************************************************************** +* Raises the Management Data Clock +* +* hw - Struct containing variables accessed by shared code +* ctrl - Device control register's current value +******************************************************************************/ +static void +e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl) +{ + /* Raise the clock input to the Management Data Clock (by setting the MDC + * bit), and then delay 2 microseconds. + */ + E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC)); + E1000_WRITE_FLUSH(hw); + udelay(2); +} + +/****************************************************************************** +* Lowers the Management Data Clock +* +* hw - Struct containing variables accessed by shared code +* ctrl - Device control register's current value +******************************************************************************/ +static void +e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl) +{ + /* Lower the clock input to the Management Data Clock (by clearing the MDC + * bit), and then delay 2 microseconds. + */ + E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC)); + E1000_WRITE_FLUSH(hw); + udelay(2); +} + +/****************************************************************************** +* Shifts data bits out to the PHY +* +* hw - Struct containing variables accessed by shared code +* data - Data to send out to the PHY +* count - Number of bits to shift out +* +* Bits are shifted out in MSB to LSB order. +******************************************************************************/ +static void +e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, uint16_t count) +{ + uint32_t ctrl; + uint32_t mask; + + /* We need to shift "count" number of bits out to the PHY. So, the value + * in the "data" parameter will be shifted out to the PHY one bit at a + * time. In order to do this, "data" must be broken down into bits. + */ + mask = 0x01; + mask <<= (count - 1); + + ctrl = E1000_READ_REG(hw, CTRL); + + /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */ + ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); + + while (mask) { + /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and + * then raising and lowering the Management Data Clock. A "0" is + * shifted out to the PHY by setting the MDIO bit to "0" and then + * raising and lowering the clock. + */ + if (data & mask) + ctrl |= E1000_CTRL_MDIO; + else + ctrl &= ~E1000_CTRL_MDIO; + + E1000_WRITE_REG(hw, CTRL, ctrl); + E1000_WRITE_FLUSH(hw); + + udelay(2); + + e1000_raise_mdi_clk(hw, &ctrl); + e1000_lower_mdi_clk(hw, &ctrl); + + mask = mask >> 1; + } +} + +/****************************************************************************** +* Shifts data bits in from the PHY +* +* hw - Struct containing variables accessed by shared code +* +* Bits are shifted in in MSB to LSB order. +******************************************************************************/ +static uint16_t +e1000_shift_in_mdi_bits(struct e1000_hw *hw) +{ + uint32_t ctrl; + uint16_t data = 0; + uint8_t i; + + /* In order to read a register from the PHY, we need to shift in a total + * of 18 bits from the PHY. The first two bit (turnaround) times are used + * to avoid contention on the MDIO pin when a read operation is performed. + * These two bits are ignored by us and thrown away. Bits are "shifted in" + * by raising the input to the Management Data Clock (setting the MDC bit), + * and then reading the value of the MDIO bit. + */ + ctrl = E1000_READ_REG(hw, CTRL); + + /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */ + ctrl &= ~E1000_CTRL_MDIO_DIR; + ctrl &= ~E1000_CTRL_MDIO; + + E1000_WRITE_REG(hw, CTRL, ctrl); + E1000_WRITE_FLUSH(hw); + + /* Raise and Lower the clock before reading in the data. This accounts for + * the turnaround bits. The first clock occurred when we clocked out the + * last bit of the Register Address. + */ + e1000_raise_mdi_clk(hw, &ctrl); + e1000_lower_mdi_clk(hw, &ctrl); + + for (data = 0, i = 0; i < 16; i++) { + data = data << 1; + e1000_raise_mdi_clk(hw, &ctrl); + ctrl = E1000_READ_REG(hw, CTRL); + /* Check to see if we shifted in a "1". */ + if (ctrl & E1000_CTRL_MDIO) + data |= 1; + e1000_lower_mdi_clk(hw, &ctrl); + } + + e1000_raise_mdi_clk(hw, &ctrl); + e1000_lower_mdi_clk(hw, &ctrl); + + return data; +} + +/***************************************************************************** +* Reads the value from a PHY register +* +* hw - Struct containing variables accessed by shared code +* reg_addr - address of the PHY register to read +******************************************************************************/ +static int +e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t * phy_data) +{ + uint32_t i; + uint32_t mdic = 0; + const uint32_t phy_addr = 1; + + if (reg_addr > MAX_PHY_REG_ADDRESS) { + DEBUGOUT("PHY Address %d is out of range\n", reg_addr); + return -E1000_ERR_PARAM; + } + + if (hw->mac_type > e1000_82543) { + /* Set up Op-code, Phy Address, and register address in the MDI + * Control register. The MAC will take care of interfacing with the + * PHY to retrieve the desired data. + */ + mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) | + (phy_addr << E1000_MDIC_PHY_SHIFT) | + (E1000_MDIC_OP_READ)); + + E1000_WRITE_REG(hw, MDIC, mdic); + + /* Poll the ready bit to see if the MDI read completed */ + for (i = 0; i < 64; i++) { + udelay(10); + mdic = E1000_READ_REG(hw, MDIC); + if (mdic & E1000_MDIC_READY) + break; + } + if (!(mdic & E1000_MDIC_READY)) { + DEBUGOUT("MDI Read did not complete\n"); + return -E1000_ERR_PHY; + } + if (mdic & E1000_MDIC_ERROR) { + DEBUGOUT("MDI Error\n"); + return -E1000_ERR_PHY; + } + *phy_data = (uint16_t) mdic; + } else { + /* We must first send a preamble through the MDIO pin to signal the + * beginning of an MII instruction. This is done by sending 32 + * consecutive "1" bits. + */ + e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); + + /* Now combine the next few fields that are required for a read + * operation. We use this method instead of calling the + * e1000_shift_out_mdi_bits routine five different times. The format of + * a MII read instruction consists of a shift out of 14 bits and is + * defined as follows: + * + * followed by a shift in of 18 bits. This first two bits shifted in + * are TurnAround bits used to avoid contention on the MDIO pin when a + * READ operation is performed. These two bits are thrown away + * followed by a shift in of 16 bits which contains the desired data. + */ + mdic = ((reg_addr) | (phy_addr << 5) | + (PHY_OP_READ << 10) | (PHY_SOF << 12)); + + e1000_shift_out_mdi_bits(hw, mdic, 14); + + /* Now that we've shifted out the read command to the MII, we need to + * "shift in" the 16-bit value (18 total bits) of the requested PHY + * register address. + */ + *phy_data = e1000_shift_in_mdi_bits(hw); + } + return 0; +} + +/****************************************************************************** +* Writes a value to a PHY register +* +* hw - Struct containing variables accessed by shared code +* reg_addr - address of the PHY register to write +* data - data to write to the PHY +******************************************************************************/ +static int +e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data) +{ + uint32_t i; + uint32_t mdic = 0; + const uint32_t phy_addr = 1; + + if (reg_addr > MAX_PHY_REG_ADDRESS) { + DEBUGOUT("PHY Address %d is out of range\n", reg_addr); + return -E1000_ERR_PARAM; + } + + if (hw->mac_type > e1000_82543) { + /* Set up Op-code, Phy Address, register address, and data intended + * for the PHY register in the MDI Control register. The MAC will take + * care of interfacing with the PHY to send the desired data. + */ + mdic = (((uint32_t) phy_data) | + (reg_addr << E1000_MDIC_REG_SHIFT) | + (phy_addr << E1000_MDIC_PHY_SHIFT) | + (E1000_MDIC_OP_WRITE)); + + E1000_WRITE_REG(hw, MDIC, mdic); + + /* Poll the ready bit to see if the MDI read completed */ + for (i = 0; i < 64; i++) { + udelay(10); + mdic = E1000_READ_REG(hw, MDIC); + if (mdic & E1000_MDIC_READY) + break; + } + if (!(mdic & E1000_MDIC_READY)) { + DEBUGOUT("MDI Write did not complete\n"); + return -E1000_ERR_PHY; + } + } else { + /* We'll need to use the SW defined pins to shift the write command + * out to the PHY. We first send a preamble to the PHY to signal the + * beginning of the MII instruction. This is done by sending 32 + * consecutive "1" bits. + */ + e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); + + /* Now combine the remaining required fields that will indicate a + * write operation. We use this method instead of calling the + * e1000_shift_out_mdi_bits routine for each field in the command. The + * format of a MII write instruction is as follows: + * . + */ + mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) | + (PHY_OP_WRITE << 12) | (PHY_SOF << 14)); + mdic <<= 16; + mdic |= (uint32_t) phy_data; + + e1000_shift_out_mdi_bits(hw, mdic, 32); + } + return 0; +} + +/****************************************************************************** + * Checks if PHY reset is blocked due to SOL/IDER session, for example. + * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to + * the caller to figure out how to deal with it. + * + * hw - Struct containing variables accessed by shared code + * + * returns: - E1000_BLK_PHY_RESET + * E1000_SUCCESS + * + *****************************************************************************/ +int32_t +e1000_check_phy_reset_block(struct e1000_hw *hw) +{ + uint32_t manc = 0; + uint32_t fwsm = 0; + + if (hw->mac_type == e1000_ich8lan) { + fwsm = E1000_READ_REG(hw, FWSM); + return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS + : E1000_BLK_PHY_RESET; + } + + if (hw->mac_type > e1000_82547_rev_2) + manc = E1000_READ_REG(hw, MANC); + return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? + E1000_BLK_PHY_RESET : E1000_SUCCESS; +} + +/*************************************************************************** + * Checks if the PHY configuration is done + * + * hw: Struct containing variables accessed by shared code + * + * returns: - E1000_ERR_RESET if fail to reset MAC + * E1000_SUCCESS at any other case. + * + ***************************************************************************/ +static int32_t +e1000_get_phy_cfg_done(struct e1000_hw *hw) +{ + int32_t timeout = PHY_CFG_TIMEOUT; + uint32_t cfg_mask = E1000_EEPROM_CFG_DONE; + + DEBUGFUNC(); + + switch (hw->mac_type) { + default: + mdelay(10); + break; + + case e1000_80003es2lan: + /* Separate *_CFG_DONE_* bit for each port */ + if (e1000_is_second_port(hw)) + cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1; + /* Fall Through */ + + case e1000_82571: + case e1000_82572: + case e1000_igb: + while (timeout) { + if (hw->mac_type == e1000_igb) { + if (E1000_READ_REG(hw, I210_EEMNGCTL) & cfg_mask) + break; + } else { + if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask) + break; + } + mdelay(1); + timeout--; + } + if (!timeout) { + DEBUGOUT("MNG configuration cycle has not " + "completed.\n"); + return -E1000_ERR_RESET; + } + break; + } + + return E1000_SUCCESS; +} + +/****************************************************************************** +* Returns the PHY to the power-on reset state +* +* hw - Struct containing variables accessed by shared code +******************************************************************************/ +int32_t +e1000_phy_hw_reset(struct e1000_hw *hw) +{ + uint16_t swfw = E1000_SWFW_PHY0_SM; + uint32_t ctrl, ctrl_ext; + uint32_t led_ctrl; + int32_t ret_val; + + DEBUGFUNC(); + + /* In the case of the phy reset being blocked, it's not an error, we + * simply return success without performing the reset. */ + ret_val = e1000_check_phy_reset_block(hw); + if (ret_val) + return E1000_SUCCESS; + + DEBUGOUT("Resetting Phy...\n"); + + if (hw->mac_type > e1000_82543) { + if (e1000_is_second_port(hw)) + swfw = E1000_SWFW_PHY1_SM; + + if (e1000_swfw_sync_acquire(hw, swfw)) { + DEBUGOUT("Unable to acquire swfw sync\n"); + return -E1000_ERR_SWFW_SYNC; + } + + /* Read the device control register and assert the E1000_CTRL_PHY_RST + * bit. Then, take it out of reset. + */ + ctrl = E1000_READ_REG(hw, CTRL); + E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST); + E1000_WRITE_FLUSH(hw); + + if (hw->mac_type < e1000_82571) + udelay(10); + else + udelay(100); + + E1000_WRITE_REG(hw, CTRL, ctrl); + E1000_WRITE_FLUSH(hw); + + if (hw->mac_type >= e1000_82571) + mdelay(10); + + } else { + /* Read the Extended Device Control Register, assert the PHY_RESET_DIR + * bit to put the PHY into reset. Then, take it out of reset. + */ + ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); + ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; + ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; + E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); + E1000_WRITE_FLUSH(hw); + mdelay(10); + ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; + E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); + E1000_WRITE_FLUSH(hw); + } + udelay(150); + + if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { + /* Configure activity LED after PHY reset */ + led_ctrl = E1000_READ_REG(hw, LEDCTL); + led_ctrl &= IGP_ACTIVITY_LED_MASK; + led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); + E1000_WRITE_REG(hw, LEDCTL, led_ctrl); + } + + e1000_swfw_sync_release(hw, swfw); + + /* Wait for FW to finish PHY configuration. */ + ret_val = e1000_get_phy_cfg_done(hw); + if (ret_val != E1000_SUCCESS) + return ret_val; + + return ret_val; +} + +/****************************************************************************** + * IGP phy init script - initializes the GbE PHY + * + * hw - Struct containing variables accessed by shared code + *****************************************************************************/ +static void +e1000_phy_init_script(struct e1000_hw *hw) +{ + uint32_t ret_val; + uint16_t phy_saved_data; + DEBUGFUNC(); + + if (hw->phy_init_script) { + mdelay(20); + + /* Save off the current value of register 0x2F5B to be + * restored at the end of this routine. */ + ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); + + /* Disabled the PHY transmitter */ + e1000_write_phy_reg(hw, 0x2F5B, 0x0003); + + mdelay(20); + + e1000_write_phy_reg(hw, 0x0000, 0x0140); + + mdelay(5); + + switch (hw->mac_type) { + case e1000_82541: + case e1000_82547: + e1000_write_phy_reg(hw, 0x1F95, 0x0001); + + e1000_write_phy_reg(hw, 0x1F71, 0xBD21); + + e1000_write_phy_reg(hw, 0x1F79, 0x0018); + + e1000_write_phy_reg(hw, 0x1F30, 0x1600); + + e1000_write_phy_reg(hw, 0x1F31, 0x0014); + + e1000_write_phy_reg(hw, 0x1F32, 0x161C); + + e1000_write_phy_reg(hw, 0x1F94, 0x0003); + + e1000_write_phy_reg(hw, 0x1F96, 0x003F); + + e1000_write_phy_reg(hw, 0x2010, 0x0008); + break; + + case e1000_82541_rev_2: + case e1000_82547_rev_2: + e1000_write_phy_reg(hw, 0x1F73, 0x0099); + break; + default: + break; + } + + e1000_write_phy_reg(hw, 0x0000, 0x3300); + + mdelay(20); + + /* Now enable the transmitter */ + if (!ret_val) + e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); + + if (hw->mac_type == e1000_82547) { + uint16_t fused, fine, coarse; + + /* Move to analog registers page */ + e1000_read_phy_reg(hw, + IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused); + + if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) { + e1000_read_phy_reg(hw, + IGP01E1000_ANALOG_FUSE_STATUS, &fused); + + fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK; + coarse = fused + & IGP01E1000_ANALOG_FUSE_COARSE_MASK; + + if (coarse > + IGP01E1000_ANALOG_FUSE_COARSE_THRESH) { + coarse -= + IGP01E1000_ANALOG_FUSE_COARSE_10; + fine -= IGP01E1000_ANALOG_FUSE_FINE_1; + } else if (coarse + == IGP01E1000_ANALOG_FUSE_COARSE_THRESH) + fine -= IGP01E1000_ANALOG_FUSE_FINE_10; + + fused = (fused + & IGP01E1000_ANALOG_FUSE_POLY_MASK) | + (fine + & IGP01E1000_ANALOG_FUSE_FINE_MASK) | + (coarse + & IGP01E1000_ANALOG_FUSE_COARSE_MASK); + + e1000_write_phy_reg(hw, + IGP01E1000_ANALOG_FUSE_CONTROL, fused); + e1000_write_phy_reg(hw, + IGP01E1000_ANALOG_FUSE_BYPASS, + IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL); + } + } + } +} + +/****************************************************************************** +* Resets the PHY +* +* hw - Struct containing variables accessed by shared code +* +* Sets bit 15 of the MII Control register +******************************************************************************/ +int32_t +e1000_phy_reset(struct e1000_hw *hw) +{ + int32_t ret_val; + uint16_t phy_data; + + DEBUGFUNC(); + + /* In the case of the phy reset being blocked, it's not an error, we + * simply return success without performing the reset. */ + ret_val = e1000_check_phy_reset_block(hw); + if (ret_val) + return E1000_SUCCESS; + + switch (hw->phy_type) { + case e1000_phy_igp: + case e1000_phy_igp_2: + case e1000_phy_igp_3: + case e1000_phy_ife: + case e1000_phy_igb: + ret_val = e1000_phy_hw_reset(hw); + if (ret_val) + return ret_val; + break; + default: + ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); + if (ret_val) + return ret_val; + + phy_data |= MII_CR_RESET; + ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); + if (ret_val) + return ret_val; + + udelay(1); + break; + } + + if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2) + e1000_phy_init_script(hw); + + return E1000_SUCCESS; +} + +static int e1000_set_phy_type (struct e1000_hw *hw) +{ + DEBUGFUNC (); + + if (hw->mac_type == e1000_undefined) + return -E1000_ERR_PHY_TYPE; + + switch (hw->phy_id) { + case M88E1000_E_PHY_ID: + case M88E1000_I_PHY_ID: + case M88E1011_I_PHY_ID: + case M88E1111_I_PHY_ID: + hw->phy_type = e1000_phy_m88; + break; + case IGP01E1000_I_PHY_ID: + if (hw->mac_type == e1000_82541 || + hw->mac_type == e1000_82541_rev_2 || + hw->mac_type == e1000_82547 || + hw->mac_type == e1000_82547_rev_2) { + hw->phy_type = e1000_phy_igp; + break; + } + case IGP03E1000_E_PHY_ID: + hw->phy_type = e1000_phy_igp_3; + break; + case IFE_E_PHY_ID: + case IFE_PLUS_E_PHY_ID: + case IFE_C_E_PHY_ID: + hw->phy_type = e1000_phy_ife; + break; + case GG82563_E_PHY_ID: + if (hw->mac_type == e1000_80003es2lan) { + hw->phy_type = e1000_phy_gg82563; + break; + } + case BME1000_E_PHY_ID: + hw->phy_type = e1000_phy_bm; + break; + case I210_I_PHY_ID: + hw->phy_type = e1000_phy_igb; + break; + /* Fall Through */ + default: + /* Should never have loaded on this device */ + hw->phy_type = e1000_phy_undefined; + return -E1000_ERR_PHY_TYPE; + } + + return E1000_SUCCESS; +} + +/****************************************************************************** +* Probes the expected PHY address for known PHY IDs +* +* hw - Struct containing variables accessed by shared code +******************************************************************************/ +static int32_t +e1000_detect_gig_phy(struct e1000_hw *hw) +{ + int32_t phy_init_status, ret_val; + uint16_t phy_id_high, phy_id_low; + bool match = false; + + DEBUGFUNC(); + + /* The 82571 firmware may still be configuring the PHY. In this + * case, we cannot access the PHY until the configuration is done. So + * we explicitly set the PHY values. */ + if (hw->mac_type == e1000_82571 || + hw->mac_type == e1000_82572) { + hw->phy_id = IGP01E1000_I_PHY_ID; + hw->phy_type = e1000_phy_igp_2; + return E1000_SUCCESS; + } + + /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a + * work- around that forces PHY page 0 to be set or the reads fail. + * The rest of the code in this routine uses e1000_read_phy_reg to + * read the PHY ID. So for ESB-2 we need to have this set so our + * reads won't fail. If the attached PHY is not a e1000_phy_gg82563, + * the routines below will figure this out as well. */ + if (hw->mac_type == e1000_80003es2lan) + hw->phy_type = e1000_phy_gg82563; + + /* Read the PHY ID Registers to identify which PHY is onboard. */ + ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high); + if (ret_val) + return ret_val; + + hw->phy_id = (uint32_t) (phy_id_high << 16); + udelay(20); + ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low); + if (ret_val) + return ret_val; + + hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK); + hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK; + + switch (hw->mac_type) { + case e1000_82543: + if (hw->phy_id == M88E1000_E_PHY_ID) + match = true; + break; + case e1000_82544: + if (hw->phy_id == M88E1000_I_PHY_ID) + match = true; + break; + case e1000_82540: + case e1000_82545: + case e1000_82545_rev_3: + case e1000_82546: + case e1000_82546_rev_3: + if (hw->phy_id == M88E1011_I_PHY_ID) + match = true; + break; + case e1000_82541: + case e1000_82541_rev_2: + case e1000_82547: + case e1000_82547_rev_2: + if(hw->phy_id == IGP01E1000_I_PHY_ID) + match = true; + + break; + case e1000_82573: + if (hw->phy_id == M88E1111_I_PHY_ID) + match = true; + break; + case e1000_82574: + if (hw->phy_id == BME1000_E_PHY_ID) + match = true; + break; + case e1000_80003es2lan: + if (hw->phy_id == GG82563_E_PHY_ID) + match = true; + break; + case e1000_ich8lan: + if (hw->phy_id == IGP03E1000_E_PHY_ID) + match = true; + if (hw->phy_id == IFE_E_PHY_ID) + match = true; + if (hw->phy_id == IFE_PLUS_E_PHY_ID) + match = true; + if (hw->phy_id == IFE_C_E_PHY_ID) + match = true; + break; + case e1000_igb: + if (hw->phy_id == I210_I_PHY_ID) + match = true; + break; + default: + DEBUGOUT("Invalid MAC type %d\n", hw->mac_type); + return -E1000_ERR_CONFIG; + } + + phy_init_status = e1000_set_phy_type(hw); + + if ((match) && (phy_init_status == E1000_SUCCESS)) { + DEBUGOUT("PHY ID 0x%X detected\n", hw->phy_id); + return 0; + } + DEBUGOUT("Invalid PHY ID 0x%X\n", hw->phy_id); + return -E1000_ERR_PHY; +} + +/***************************************************************************** + * Set media type and TBI compatibility. + * + * hw - Struct containing variables accessed by shared code + * **************************************************************************/ +void +e1000_set_media_type(struct e1000_hw *hw) +{ + uint32_t status; + + DEBUGFUNC(); + + if (hw->mac_type != e1000_82543) { + /* tbi_compatibility is only valid on 82543 */ + hw->tbi_compatibility_en = false; + } + + switch (hw->device_id) { + case E1000_DEV_ID_82545GM_SERDES: + case E1000_DEV_ID_82546GB_SERDES: + case E1000_DEV_ID_82571EB_SERDES: + case E1000_DEV_ID_82571EB_SERDES_DUAL: + case E1000_DEV_ID_82571EB_SERDES_QUAD: + case E1000_DEV_ID_82572EI_SERDES: + case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: + hw->media_type = e1000_media_type_internal_serdes; + break; + default: + switch (hw->mac_type) { + case e1000_82542_rev2_0: + case e1000_82542_rev2_1: + hw->media_type = e1000_media_type_fiber; + break; + case e1000_ich8lan: + case e1000_82573: + case e1000_82574: + case e1000_igb: + /* The STATUS_TBIMODE bit is reserved or reused + * for the this device. + */ + hw->media_type = e1000_media_type_copper; + break; + default: + status = E1000_READ_REG(hw, STATUS); + if (status & E1000_STATUS_TBIMODE) { + hw->media_type = e1000_media_type_fiber; + /* tbi_compatibility not valid on fiber */ + hw->tbi_compatibility_en = false; + } else { + hw->media_type = e1000_media_type_copper; + } + break; + } + } +} + +/** + * e1000_sw_init - Initialize general software structures (struct e1000_adapter) + * + * e1000_sw_init initializes the Adapter private data structure. + * Fields are initialized based on PCI device information and + * OS network device settings (MTU size). + **/ + +static int +e1000_sw_init(struct e1000_hw *hw) +{ + int result; + + /* PCI config space info */ + pci_read_config_word(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id); + pci_read_config_word(hw->pdev, PCI_DEVICE_ID, &hw->device_id); + pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID, + &hw->subsystem_vendor_id); + pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id); + + pci_read_config_byte(hw->pdev, PCI_REVISION_ID, &hw->revision_id); + pci_read_config_word(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word); + + /* identify the MAC */ + result = e1000_set_mac_type(hw); + if (result) { + E1000_ERR(hw, "Unknown MAC Type\n"); + return result; + } + + switch (hw->mac_type) { + default: + break; + case e1000_82541: + case e1000_82547: + case e1000_82541_rev_2: + case e1000_82547_rev_2: + hw->phy_init_script = 1; + break; + } + + /* flow control settings */ + hw->fc_high_water = E1000_FC_HIGH_THRESH; + hw->fc_low_water = E1000_FC_LOW_THRESH; + hw->fc_pause_time = E1000_FC_PAUSE_TIME; + hw->fc_send_xon = 1; + + /* Media type - copper or fiber */ + hw->tbi_compatibility_en = true; + e1000_set_media_type(hw); + + if (hw->mac_type >= e1000_82543) { + uint32_t status = E1000_READ_REG(hw, STATUS); + + if (status & E1000_STATUS_TBIMODE) { + DEBUGOUT("fiber interface\n"); + hw->media_type = e1000_media_type_fiber; + } else { + DEBUGOUT("copper interface\n"); + hw->media_type = e1000_media_type_copper; + } + } else { + hw->media_type = e1000_media_type_fiber; + } + + hw->wait_autoneg_complete = true; + if (hw->mac_type < e1000_82543) + hw->report_tx_early = 0; + else + hw->report_tx_early = 1; + + return E1000_SUCCESS; +} + +void +fill_rx(struct e1000_hw *hw) +{ + struct e1000_rx_desc *rd; + unsigned long flush_start, flush_end; + + rx_last = rx_tail; + rd = rx_base + rx_tail; + rx_tail = (rx_tail + 1) % 8; + memset(rd, 0, 16); + rd->buffer_addr = cpu_to_le64((unsigned long)packet); + + /* + * Make sure there are no stale data in WB over this area, which + * might get written into the memory while the e1000 also writes + * into the same memory area. + */ + invalidate_dcache_range((unsigned long)packet, + (unsigned long)packet + 4096); + /* Dump the DMA descriptor into RAM. */ + flush_start = ((unsigned long)rd) & ~(ARCH_DMA_MINALIGN - 1); + flush_end = flush_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN); + flush_dcache_range(flush_start, flush_end); + + E1000_WRITE_REG(hw, RDT, rx_tail); +} + +/** + * e1000_configure_tx - Configure 8254x Transmit Unit after Reset + * @adapter: board private structure + * + * Configure the Tx unit of the MAC after a reset. + **/ + +static void +e1000_configure_tx(struct e1000_hw *hw) +{ + unsigned long tctl; + unsigned long tipg, tarc; + uint32_t ipgr1, ipgr2; + + E1000_WRITE_REG(hw, TDBAL, lower_32_bits((unsigned long)tx_base)); + E1000_WRITE_REG(hw, TDBAH, upper_32_bits((unsigned long)tx_base)); + + E1000_WRITE_REG(hw, TDLEN, 128); + + /* Setup the HW Tx Head and Tail descriptor pointers */ + E1000_WRITE_REG(hw, TDH, 0); + E1000_WRITE_REG(hw, TDT, 0); + tx_tail = 0; + + /* Set the default values for the Tx Inter Packet Gap timer */ + if (hw->mac_type <= e1000_82547_rev_2 && + (hw->media_type == e1000_media_type_fiber || + hw->media_type == e1000_media_type_internal_serdes)) + tipg = DEFAULT_82543_TIPG_IPGT_FIBER; + else + tipg = DEFAULT_82543_TIPG_IPGT_COPPER; + + /* Set the default values for the Tx Inter Packet Gap timer */ + switch (hw->mac_type) { + case e1000_82542_rev2_0: + case e1000_82542_rev2_1: + tipg = DEFAULT_82542_TIPG_IPGT; + ipgr1 = DEFAULT_82542_TIPG_IPGR1; + ipgr2 = DEFAULT_82542_TIPG_IPGR2; + break; + case e1000_80003es2lan: + ipgr1 = DEFAULT_82543_TIPG_IPGR1; + ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2; + break; + default: + ipgr1 = DEFAULT_82543_TIPG_IPGR1; + ipgr2 = DEFAULT_82543_TIPG_IPGR2; + break; + } + tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT; + tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT; + E1000_WRITE_REG(hw, TIPG, tipg); + /* Program the Transmit Control Register */ + tctl = E1000_READ_REG(hw, TCTL); + tctl &= ~E1000_TCTL_CT; + tctl |= E1000_TCTL_EN | E1000_TCTL_PSP | + (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); + + if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) { + tarc = E1000_READ_REG(hw, TARC0); + /* set the speed mode bit, we'll clear it if we're not at + * gigabit link later */ + /* git bit can be set to 1*/ + } else if (hw->mac_type == e1000_80003es2lan) { + tarc = E1000_READ_REG(hw, TARC0); + tarc |= 1; + E1000_WRITE_REG(hw, TARC0, tarc); + tarc = E1000_READ_REG(hw, TARC1); + tarc |= 1; + E1000_WRITE_REG(hw, TARC1, tarc); + } + + + e1000_config_collision_dist(hw); + /* Setup Transmit Descriptor Settings for eop descriptor */ + hw->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS; + + /* Need to set up RS bit */ + if (hw->mac_type < e1000_82543) + hw->txd_cmd |= E1000_TXD_CMD_RPS; + else + hw->txd_cmd |= E1000_TXD_CMD_RS; + + + if (hw->mac_type == e1000_igb) { + E1000_WRITE_REG(hw, TCTL_EXT, 0x42 << 10); + + uint32_t reg_txdctl = E1000_READ_REG(hw, TXDCTL); + reg_txdctl |= 1 << 25; + E1000_WRITE_REG(hw, TXDCTL, reg_txdctl); + mdelay(20); + } + + + + E1000_WRITE_REG(hw, TCTL, tctl); + + +} + +/** + * e1000_setup_rctl - configure the receive control register + * @adapter: Board private structure + **/ +static void +e1000_setup_rctl(struct e1000_hw *hw) +{ + uint32_t rctl; + + rctl = E1000_READ_REG(hw, RCTL); + + rctl &= ~(3 << E1000_RCTL_MO_SHIFT); + + rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO + | E1000_RCTL_RDMTS_HALF; /* | + (hw.mc_filter_type << E1000_RCTL_MO_SHIFT); */ + + if (hw->tbi_compatibility_on == 1) + rctl |= E1000_RCTL_SBP; + else + rctl &= ~E1000_RCTL_SBP; + + rctl &= ~(E1000_RCTL_SZ_4096); + rctl |= E1000_RCTL_SZ_2048; + rctl &= ~(E1000_RCTL_BSEX | E1000_RCTL_LPE); + E1000_WRITE_REG(hw, RCTL, rctl); +} + +/** + * e1000_configure_rx - Configure 8254x Receive Unit after Reset + * @adapter: board private structure + * + * Configure the Rx unit of the MAC after a reset. + **/ +static void +e1000_configure_rx(struct e1000_hw *hw) +{ + unsigned long rctl, ctrl_ext; + rx_tail = 0; + + /* make sure receives are disabled while setting up the descriptors */ + rctl = E1000_READ_REG(hw, RCTL); + E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN); + if (hw->mac_type >= e1000_82540) { + /* Set the interrupt throttling rate. Value is calculated + * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */ +#define MAX_INTS_PER_SEC 8000 +#define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256) + E1000_WRITE_REG(hw, ITR, DEFAULT_ITR); + } + + if (hw->mac_type >= e1000_82571) { + ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); + /* Reset delay timers after every interrupt */ + ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR; + E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); + E1000_WRITE_FLUSH(hw); + } + /* Setup the Base and Length of the Rx Descriptor Ring */ + E1000_WRITE_REG(hw, RDBAL, lower_32_bits((unsigned long)rx_base)); + E1000_WRITE_REG(hw, RDBAH, upper_32_bits((unsigned long)rx_base)); + + E1000_WRITE_REG(hw, RDLEN, 128); + + /* Setup the HW Rx Head and Tail Descriptor Pointers */ + E1000_WRITE_REG(hw, RDH, 0); + E1000_WRITE_REG(hw, RDT, 0); + /* Enable Receives */ + + if (hw->mac_type == e1000_igb) { + + uint32_t reg_rxdctl = E1000_READ_REG(hw, RXDCTL); + reg_rxdctl |= 1 << 25; + E1000_WRITE_REG(hw, RXDCTL, reg_rxdctl); + mdelay(20); + } + + E1000_WRITE_REG(hw, RCTL, rctl); + + fill_rx(hw); +} + +/************************************************************************** +POLL - Wait for a frame +***************************************************************************/ +static int +_e1000_poll(struct e1000_hw *hw) +{ + struct e1000_rx_desc *rd; + unsigned long inval_start, inval_end; + uint32_t len; + + /* return true if there's an ethernet packet ready to read */ + rd = rx_base + rx_last; + + /* Re-load the descriptor from RAM. */ + inval_start = ((unsigned long)rd) & ~(ARCH_DMA_MINALIGN - 1); + inval_end = inval_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN); + invalidate_dcache_range(inval_start, inval_end); + + if (!(rd->status & E1000_RXD_STAT_DD)) + return 0; + /* DEBUGOUT("recv: packet len=%d\n", rd->length); */ + /* Packet received, make sure the data are re-loaded from RAM. */ + len = le16_to_cpu(rd->length); + invalidate_dcache_range((unsigned long)packet, + (unsigned long)packet + + roundup(len, ARCH_DMA_MINALIGN)); + return len; +} + +static int _e1000_transmit(struct e1000_hw *hw, void *txpacket, int length) +{ + void *nv_packet = (void *)txpacket; + struct e1000_tx_desc *txp; + int i = 0; + unsigned long flush_start, flush_end; + + txp = tx_base + tx_tail; + tx_tail = (tx_tail + 1) % 8; + + txp->buffer_addr = cpu_to_le64(virt_to_bus(hw->pdev, nv_packet)); + txp->lower.data = cpu_to_le32(hw->txd_cmd | length); + txp->upper.data = 0; + + /* Dump the packet into RAM so e1000 can pick them. */ + flush_dcache_range((unsigned long)nv_packet, + (unsigned long)nv_packet + + roundup(length, ARCH_DMA_MINALIGN)); + /* Dump the descriptor into RAM as well. */ + flush_start = ((unsigned long)txp) & ~(ARCH_DMA_MINALIGN - 1); + flush_end = flush_start + roundup(sizeof(*txp), ARCH_DMA_MINALIGN); + flush_dcache_range(flush_start, flush_end); + + E1000_WRITE_REG(hw, TDT, tx_tail); + + E1000_WRITE_FLUSH(hw); + while (1) { + invalidate_dcache_range(flush_start, flush_end); + if (le32_to_cpu(txp->upper.data) & E1000_TXD_STAT_DD) + break; + if (i++ > TOUT_LOOP) { + DEBUGOUT("e1000: tx timeout\n"); + return 0; + } + udelay(10); /* give the nic a chance to write to the register */ + } + return 1; +} + +static void +_e1000_disable(struct e1000_hw *hw) +{ + /* Turn off the ethernet interface */ + E1000_WRITE_REG(hw, RCTL, 0); + E1000_WRITE_REG(hw, TCTL, 0); + + /* Clear the transmit ring */ + E1000_WRITE_REG(hw, TDH, 0); + E1000_WRITE_REG(hw, TDT, 0); + + /* Clear the receive ring */ + E1000_WRITE_REG(hw, RDH, 0); + E1000_WRITE_REG(hw, RDT, 0); + + /* put the card in its initial state */ +#if 0 + E1000_WRITE_REG(hw, CTRL, E1000_CTRL_RST); +#endif + mdelay(10); +} + +/*reset function*/ +static inline int +e1000_reset(struct e1000_hw *hw, unsigned char enetaddr[6]) +{ + e1000_reset_hw(hw); + if (hw->mac_type >= e1000_82544) + E1000_WRITE_REG(hw, WUC, 0); + + return e1000_init_hw(hw, enetaddr); +} + +static int +_e1000_init(struct e1000_hw *hw, unsigned char enetaddr[6]) +{ + int ret_val = 0; + + ret_val = e1000_reset(hw, enetaddr); + if (ret_val < 0) { + if ((ret_val == -E1000_ERR_NOLINK) || + (ret_val == -E1000_ERR_TIMEOUT)) { + E1000_ERR(hw, "Valid Link not detected: %d\n", ret_val); + } else { + E1000_ERR(hw, "Hardware Initialization Failed\n"); + } + return ret_val; + } + e1000_configure_tx(hw); + e1000_setup_rctl(hw); + e1000_configure_rx(hw); + return 0; +} + +/****************************************************************************** + * Gets the current PCI bus type of hardware + * + * hw - Struct containing variables accessed by shared code + *****************************************************************************/ +void e1000_get_bus_type(struct e1000_hw *hw) +{ + uint32_t status; + + switch (hw->mac_type) { + case e1000_82542_rev2_0: + case e1000_82542_rev2_1: + hw->bus_type = e1000_bus_type_pci; + break; + case e1000_82571: + case e1000_82572: + case e1000_82573: + case e1000_82574: + case e1000_80003es2lan: + case e1000_ich8lan: + case e1000_igb: + hw->bus_type = e1000_bus_type_pci_express; + break; + default: + status = E1000_READ_REG(hw, STATUS); + hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ? + e1000_bus_type_pcix : e1000_bus_type_pci; + break; + } +} + +#ifndef CONFIG_DM_ETH +/* A list of all registered e1000 devices */ +static LIST_HEAD(e1000_hw_list); +#endif + +static int e1000_init_one(struct e1000_hw *hw, int cardnum, pci_dev_t devno, + unsigned char enetaddr[6]) +{ + u32 val; + + /* Assign the passed-in values */ + hw->pdev = devno; + hw->cardnum = cardnum; + + /* Print a debug message with the IO base address */ + pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &val); + E1000_DBG(hw, "iobase 0x%08x\n", val & 0xfffffff0); + + /* Try to enable I/O accesses and bus-mastering */ + val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; + pci_write_config_dword(devno, PCI_COMMAND, val); + + /* Make sure it worked */ + pci_read_config_dword(devno, PCI_COMMAND, &val); + if (!(val & PCI_COMMAND_MEMORY)) { + E1000_ERR(hw, "Can't enable I/O memory\n"); + return -ENOSPC; + } + if (!(val & PCI_COMMAND_MASTER)) { + E1000_ERR(hw, "Can't enable bus-mastering\n"); + return -EPERM; + } + + /* Are these variables needed? */ + hw->fc = e1000_fc_default; + hw->original_fc = e1000_fc_default; + hw->autoneg_failed = 0; + hw->autoneg = 1; + hw->get_link_status = true; +#ifndef CONFIG_E1000_NO_NVM + hw->eeprom_semaphore_present = true; +#endif + hw->hw_addr = pci_map_bar(devno, PCI_BASE_ADDRESS_0, + PCI_REGION_MEM); + hw->mac_type = e1000_undefined; + + /* MAC and Phy settings */ + if (e1000_sw_init(hw) < 0) { + E1000_ERR(hw, "Software init failed\n"); + return -EIO; + } + if (e1000_check_phy_reset_block(hw)) + E1000_ERR(hw, "PHY Reset is blocked!\n"); + + /* Basic init was OK, reset the hardware and allow SPI access */ + e1000_reset_hw(hw); + +#ifndef CONFIG_E1000_NO_NVM + /* Validate the EEPROM and get chipset information */ +#if !defined(CONFIG_MVBC_1G) + if (e1000_init_eeprom_params(hw)) { + E1000_ERR(hw, "EEPROM is invalid!\n"); + return -EINVAL; + } + if ((E1000_READ_REG(hw, I210_EECD) & E1000_EECD_FLUPD) && + e1000_validate_eeprom_checksum(hw)) + return -ENXIO; +#endif + e1000_read_mac_addr(hw, enetaddr); +#endif + e1000_get_bus_type(hw); + +#ifndef CONFIG_E1000_NO_NVM + printf("e1000: %02x:%02x:%02x:%02x:%02x:%02x\n ", + enetaddr[0], enetaddr[1], enetaddr[2], + enetaddr[3], enetaddr[4], enetaddr[5]); +#else + memset(enetaddr, 0, 6); + printf("e1000: no NVM\n"); +#endif + + return 0; +} + +/* Put the name of a device in a string */ +static void e1000_name(char *str, int cardnum) +{ + sprintf(str, "e1000#%u", cardnum); +} + +#ifndef CONFIG_DM_ETH +/************************************************************************** +TRANSMIT - Transmit a frame +***************************************************************************/ +static int e1000_transmit(struct eth_device *nic, void *txpacket, int length) +{ + struct e1000_hw *hw = nic->priv; + + return _e1000_transmit(hw, txpacket, length); +} + +/************************************************************************** +DISABLE - Turn off ethernet interface +***************************************************************************/ +static void +e1000_disable(struct eth_device *nic) +{ + struct e1000_hw *hw = nic->priv; + + _e1000_disable(hw); +} + +/************************************************************************** +INIT - set up ethernet interface(s) +***************************************************************************/ +static int +e1000_init(struct eth_device *nic, bd_t *bis) +{ + struct e1000_hw *hw = nic->priv; + + return _e1000_init(hw, nic->enetaddr); +} + +static int +e1000_poll(struct eth_device *nic) +{ + struct e1000_hw *hw = nic->priv; + int len; + + len = _e1000_poll(hw); + if (len) { + net_process_received_packet((uchar *)packet, len); + fill_rx(hw); + } + + return len ? 1 : 0; +} + +/************************************************************************** +PROBE - Look for an adapter, this routine's visible to the outside +You should omit the last argument struct pci_device * for a non-PCI NIC +***************************************************************************/ +int +e1000_initialize(bd_t * bis) +{ + unsigned int i; + pci_dev_t devno; + int ret; + + DEBUGFUNC(); + + /* Find and probe all the matching PCI devices */ + for (i = 0; (devno = pci_find_devices(e1000_supported, i)) >= 0; i++) { + /* + * These will never get freed due to errors, this allows us to + * perform SPI EEPROM programming from U-boot, for example. + */ + struct eth_device *nic = malloc(sizeof(*nic)); + struct e1000_hw *hw = malloc(sizeof(*hw)); + if (!nic || !hw) { + printf("e1000#%u: Out of Memory!\n", i); + free(nic); + free(hw); + continue; + } + + /* Make sure all of the fields are initially zeroed */ + memset(nic, 0, sizeof(*nic)); + memset(hw, 0, sizeof(*hw)); + nic->priv = hw; + + /* Generate a card name */ + e1000_name(nic->name, i); + hw->name = nic->name; + + ret = e1000_init_one(hw, i, devno, nic->enetaddr); + if (ret) + continue; + list_add_tail(&hw->list_node, &e1000_hw_list); + + hw->nic = nic; + + /* Set up the function pointers and register the device */ + nic->init = e1000_init; + nic->recv = e1000_poll; + nic->send = e1000_transmit; + nic->halt = e1000_disable; + eth_register(nic); + } + + return i; +} + +struct e1000_hw *e1000_find_card(unsigned int cardnum) +{ + struct e1000_hw *hw; + + list_for_each_entry(hw, &e1000_hw_list, list_node) + if (hw->cardnum == cardnum) + return hw; + + return NULL; +} +#endif /* !CONFIG_DM_ETH */ + +#ifdef CONFIG_CMD_E1000 +static int do_e1000(cmd_tbl_t *cmdtp, int flag, + int argc, char * const argv[]) +{ + unsigned char *mac = NULL; +#ifdef CONFIG_DM_ETH + struct eth_pdata *plat; + struct udevice *dev; + char name[30]; + int ret; +#else + struct e1000_hw *hw; +#endif + int cardnum; + + if (argc < 3) { + cmd_usage(cmdtp); + return 1; + } + + /* Make sure we can find the requested e1000 card */ + cardnum = simple_strtoul(argv[1], NULL, 10); +#ifdef CONFIG_DM_ETH + e1000_name(name, cardnum); + ret = uclass_get_device_by_name(UCLASS_ETH, name, &dev); + if (!ret) { + plat = dev_get_platdata(dev); + mac = plat->enetaddr; + } +#else + hw = e1000_find_card(cardnum); + if (hw) + mac = hw->nic->enetaddr; +#endif + if (!mac) { + printf("e1000: ERROR: No such device: e1000#%s\n", argv[1]); + return 1; + } + + if (!strcmp(argv[2], "print-mac-address")) { + printf("%02x:%02x:%02x:%02x:%02x:%02x\n", + mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); + return 0; + } + +#ifdef CONFIG_E1000_SPI + /* Handle the "SPI" subcommand */ + if (!strcmp(argv[2], "spi")) + return do_e1000_spi(cmdtp, hw, argc - 3, argv + 3); +#endif + + cmd_usage(cmdtp); + return 1; +} + +U_BOOT_CMD( + e1000, 7, 0, do_e1000, + "Intel e1000 controller management", + /* */" print-mac-address\n" +#ifdef CONFIG_E1000_SPI + "e1000 spi show [ []]\n" + "e1000 spi dump \n" + "e1000 spi program \n" + "e1000 spi checksum [update]\n" +#endif + " - Manage the Intel E1000 PCI device" +); +#endif /* not CONFIG_CMD_E1000 */ + +#ifdef CONFIG_DM_ETH +static int e1000_eth_start(struct udevice *dev) +{ + struct eth_pdata *plat = dev_get_platdata(dev); + struct e1000_hw *hw = dev_get_priv(dev); + + return _e1000_init(hw, plat->enetaddr); +} + +static void e1000_eth_stop(struct udevice *dev) +{ + struct e1000_hw *hw = dev_get_priv(dev); + + _e1000_disable(hw); +} + +static int e1000_eth_send(struct udevice *dev, void *packet, int length) +{ + struct e1000_hw *hw = dev_get_priv(dev); + int ret; + + ret = _e1000_transmit(hw, packet, length); + + return ret ? 0 : -ETIMEDOUT; +} + +static int e1000_eth_recv(struct udevice *dev, int flags, uchar **packetp) +{ + struct e1000_hw *hw = dev_get_priv(dev); + int len; + + len = _e1000_poll(hw); + if (len) + *packetp = packet; + + return len ? len : -EAGAIN; +} + +static int e1000_free_pkt(struct udevice *dev, uchar *packet, int length) +{ + struct e1000_hw *hw = dev_get_priv(dev); + + fill_rx(hw); + + return 0; +} + +static int e1000_eth_probe(struct udevice *dev) +{ + struct eth_pdata *plat = dev_get_platdata(dev); + struct e1000_hw *hw = dev_get_priv(dev); + int ret; + + hw->name = dev->name; + ret = e1000_init_one(hw, trailing_strtol(dev->name), pci_get_bdf(dev), + plat->enetaddr); + if (ret < 0) { + printf(pr_fmt("failed to initialize card: %d\n"), ret); + return ret; + } + + return 0; +} + +static int e1000_eth_bind(struct udevice *dev) +{ + char name[20]; + + /* + * A simple way to number the devices. When device tree is used this + * is unnecessary, but when the device is just discovered on the PCI + * bus we need a name. We could instead have the uclass figure out + * which devices are different and number them. + */ + e1000_name(name, num_cards++); + + return device_set_name(dev, name); +} + +static const struct eth_ops e1000_eth_ops = { + .start = e1000_eth_start, + .send = e1000_eth_send, + .recv = e1000_eth_recv, + .stop = e1000_eth_stop, + .free_pkt = e1000_free_pkt, +}; + +static const struct udevice_id e1000_eth_ids[] = { + { .compatible = "intel,e1000" }, + { } +}; + +U_BOOT_DRIVER(eth_e1000) = { + .name = "eth_e1000", + .id = UCLASS_ETH, + .of_match = e1000_eth_ids, + .bind = e1000_eth_bind, + .probe = e1000_eth_probe, + .ops = &e1000_eth_ops, + .priv_auto_alloc_size = sizeof(struct e1000_hw), + .platdata_auto_alloc_size = sizeof(struct eth_pdata), +}; + +U_BOOT_PCI_DEVICE(eth_e1000, e1000_supported); +#endif diff --git a/sources/uboot-be550/drivers/net/e1000.h b/sources/uboot-be550/drivers/net/e1000.h new file mode 100644 index 00000000..c851922a --- /dev/null +++ b/sources/uboot-be550/drivers/net/e1000.h @@ -0,0 +1,2617 @@ +/******************************************************************************* + + + Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved. + Copyright 2011 Freescale Semiconductor, Inc. + + * SPDX-License-Identifier: GPL-2.0+ + + Contact Information: + Linux NICS + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 + +*******************************************************************************/ + +/* e1000_hw.h + * Structures, enums, and macros for the MAC + */ + +#ifndef _E1000_HW_H_ +#define _E1000_HW_H_ + +#include +#include +#include +/* Avoids a compile error since struct eth_device is not defined */ +#ifndef CONFIG_DM_ETH +#include +#endif +#include +#include + +#ifdef CONFIG_E1000_SPI +#include +#endif + +#define E1000_ERR(NIC, fmt, args...) \ + printf("e1000: %s: ERROR: " fmt, (NIC)->name ,##args) + +#ifdef E1000_DEBUG +#define E1000_DBG(NIC, fmt, args...) \ + printf("e1000: %s: DEBUG: " fmt, (NIC)->name ,##args) +#define DEBUGOUT(fmt, args...) printf(fmt ,##args) +#define DEBUGFUNC() printf("%s\n", __func__); +#else +#define E1000_DBG(HW, args...) do { } while (0) +#define DEBUGFUNC() do { } while (0) +#define DEBUGOUT(fmt, args...) do { } while (0) +#endif + +/* I/O wrapper functions */ +#define E1000_WRITE_REG(a, reg, value) \ + writel((value), ((a)->hw_addr + E1000_##reg)) +#define E1000_READ_REG(a, reg) \ + readl((a)->hw_addr + E1000_##reg) +#define E1000_WRITE_REG_ARRAY(a, reg, offset, value) \ + writel((value), ((a)->hw_addr + E1000_##reg + ((offset) << 2))) +#define E1000_READ_REG_ARRAY(a, reg, offset) \ + readl((a)->hw_addr + E1000_##reg + ((offset) << 2)) +#define E1000_WRITE_FLUSH(a) \ + do { E1000_READ_REG(a, STATUS); } while (0) + +/* Forward declarations of structures used by the shared code */ +struct e1000_hw; +struct e1000_hw_stats; + +/* Internal E1000 helper functions */ +struct e1000_hw *e1000_find_card(unsigned int cardnum); + +#ifndef CONFIG_E1000_NO_NVM +int32_t e1000_acquire_eeprom(struct e1000_hw *hw); +void e1000_standby_eeprom(struct e1000_hw *hw); +void e1000_release_eeprom(struct e1000_hw *hw); +void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t *eecd); +void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t *eecd); +#endif + +#ifdef CONFIG_E1000_SPI +int do_e1000_spi(cmd_tbl_t *cmdtp, struct e1000_hw *hw, + int argc, char * const argv[]); +#endif + +/* Enumerated types specific to the e1000 hardware */ +/* Media Access Controlers */ +typedef enum { + e1000_undefined = 0, + e1000_82542_rev2_0, + e1000_82542_rev2_1, + e1000_82543, + e1000_82544, + e1000_82540, + e1000_82545, + e1000_82545_rev_3, + e1000_82546, + e1000_82546_rev_3, + e1000_82541, + e1000_82541_rev_2, + e1000_82547, + e1000_82547_rev_2, + e1000_82571, + e1000_82572, + e1000_82573, + e1000_82574, + e1000_80003es2lan, + e1000_ich8lan, + e1000_igb, + e1000_num_macs +} e1000_mac_type; + +/* Media Types */ +typedef enum { + e1000_media_type_copper = 0, + e1000_media_type_fiber = 1, + e1000_media_type_internal_serdes = 2, + e1000_num_media_types +} e1000_media_type; + +typedef enum { + e1000_eeprom_uninitialized = 0, + e1000_eeprom_spi, + e1000_eeprom_microwire, + e1000_eeprom_flash, + e1000_eeprom_ich8, + e1000_eeprom_none, /* No NVM support */ + e1000_eeprom_invm, + e1000_num_eeprom_types +} e1000_eeprom_type; + +typedef enum { + e1000_10_half = 0, + e1000_10_full = 1, + e1000_100_half = 2, + e1000_100_full = 3 +} e1000_speed_duplex_type; + +/* Flow Control Settings */ +typedef enum { + e1000_fc_none = 0, + e1000_fc_rx_pause = 1, + e1000_fc_tx_pause = 2, + e1000_fc_full = 3, + e1000_fc_default = 0xFF +} e1000_fc_type; + +/* PCI bus types */ +typedef enum { + e1000_bus_type_unknown = 0, + e1000_bus_type_pci, + e1000_bus_type_pcix, + e1000_bus_type_pci_express, + e1000_bus_type_reserved +} e1000_bus_type; + +/* PCI bus speeds */ +typedef enum { + e1000_bus_speed_unknown = 0, + e1000_bus_speed_33, + e1000_bus_speed_66, + e1000_bus_speed_100, + e1000_bus_speed_133, + e1000_bus_speed_reserved +} e1000_bus_speed; + +/* PCI bus widths */ +typedef enum { + e1000_bus_width_unknown = 0, + e1000_bus_width_32, + e1000_bus_width_64 +} e1000_bus_width; + +/* PHY status info structure and supporting enums */ +typedef enum { + e1000_cable_length_50 = 0, + e1000_cable_length_50_80, + e1000_cable_length_80_110, + e1000_cable_length_110_140, + e1000_cable_length_140, + e1000_cable_length_undefined = 0xFF +} e1000_cable_length; + +typedef enum { + e1000_10bt_ext_dist_enable_normal = 0, + e1000_10bt_ext_dist_enable_lower, + e1000_10bt_ext_dist_enable_undefined = 0xFF +} e1000_10bt_ext_dist_enable; + +typedef enum { + e1000_rev_polarity_normal = 0, + e1000_rev_polarity_reversed, + e1000_rev_polarity_undefined = 0xFF +} e1000_rev_polarity; + +typedef enum { + e1000_polarity_reversal_enabled = 0, + e1000_polarity_reversal_disabled, + e1000_polarity_reversal_undefined = 0xFF +} e1000_polarity_reversal; + +typedef enum { + e1000_auto_x_mode_manual_mdi = 0, + e1000_auto_x_mode_manual_mdix, + e1000_auto_x_mode_auto1, + e1000_auto_x_mode_auto2, + e1000_auto_x_mode_undefined = 0xFF +} e1000_auto_x_mode; + +typedef enum { + e1000_1000t_rx_status_not_ok = 0, + e1000_1000t_rx_status_ok, + e1000_1000t_rx_status_undefined = 0xFF +} e1000_1000t_rx_status; + +typedef enum { + e1000_phy_m88 = 0, + e1000_phy_igp, + e1000_phy_igp_2, + e1000_phy_gg82563, + e1000_phy_igp_3, + e1000_phy_ife, + e1000_phy_igb, + e1000_phy_bm, + e1000_phy_undefined = 0xFF +} e1000_phy_type; + +struct e1000_phy_info { + e1000_cable_length cable_length; + e1000_10bt_ext_dist_enable extended_10bt_distance; + e1000_rev_polarity cable_polarity; + e1000_polarity_reversal polarity_correction; + e1000_auto_x_mode mdix_mode; + e1000_1000t_rx_status local_rx; + e1000_1000t_rx_status remote_rx; +}; + +struct e1000_phy_stats { + uint32_t idle_errors; + uint32_t receive_errors; +}; + +/* Error Codes */ +#define E1000_SUCCESS 0 +#define E1000_ERR_EEPROM 1 +#define E1000_ERR_PHY 2 +#define E1000_ERR_CONFIG 3 +#define E1000_ERR_PARAM 4 +#define E1000_ERR_MAC_TYPE 5 +#define E1000_ERR_PHY_TYPE 6 +#define E1000_ERR_NOLINK 7 +#define E1000_ERR_TIMEOUT 8 +#define E1000_ERR_RESET 9 +#define E1000_ERR_MASTER_REQUESTS_PENDING 10 +#define E1000_ERR_HOST_INTERFACE_COMMAND 11 +#define E1000_BLK_PHY_RESET 12 +#define E1000_ERR_SWFW_SYNC 13 + +/* PCI Device IDs */ +#define E1000_DEV_ID_82542 0x1000 +#define E1000_DEV_ID_82543GC_FIBER 0x1001 +#define E1000_DEV_ID_82543GC_COPPER 0x1004 +#define E1000_DEV_ID_82544EI_COPPER 0x1008 +#define E1000_DEV_ID_82544EI_FIBER 0x1009 +#define E1000_DEV_ID_82544GC_COPPER 0x100C +#define E1000_DEV_ID_82544GC_LOM 0x100D +#define E1000_DEV_ID_82540EM 0x100E +#define E1000_DEV_ID_82540EM_LOM 0x1015 +#define E1000_DEV_ID_82540EP_LOM 0x1016 +#define E1000_DEV_ID_82540EP 0x1017 +#define E1000_DEV_ID_82540EP_LP 0x101E +#define E1000_DEV_ID_82545EM_COPPER 0x100F +#define E1000_DEV_ID_82545EM_FIBER 0x1011 +#define E1000_DEV_ID_82545GM_COPPER 0x1026 +#define E1000_DEV_ID_82545GM_FIBER 0x1027 +#define E1000_DEV_ID_82545GM_SERDES 0x1028 +#define E1000_DEV_ID_82546EB_COPPER 0x1010 +#define E1000_DEV_ID_82546EB_FIBER 0x1012 +#define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D +#define E1000_DEV_ID_82541EI 0x1013 +#define E1000_DEV_ID_82541EI_MOBILE 0x1018 +#define E1000_DEV_ID_82541ER_LOM 0x1014 +#define E1000_DEV_ID_82541ER 0x1078 +#define E1000_DEV_ID_82547GI 0x1075 +#define E1000_DEV_ID_82541GI 0x1076 +#define E1000_DEV_ID_82541GI_MOBILE 0x1077 +#define E1000_DEV_ID_82541GI_LF 0x107C +#define E1000_DEV_ID_82546GB_COPPER 0x1079 +#define E1000_DEV_ID_82546GB_FIBER 0x107A +#define E1000_DEV_ID_82546GB_SERDES 0x107B +#define E1000_DEV_ID_82546GB_PCIE 0x108A +#define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099 +#define E1000_DEV_ID_82547EI 0x1019 +#define E1000_DEV_ID_82547EI_MOBILE 0x101A +#define E1000_DEV_ID_82571EB_COPPER 0x105E +#define E1000_DEV_ID_82571EB_FIBER 0x105F +#define E1000_DEV_ID_82571EB_SERDES 0x1060 +#define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4 +#define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5 +#define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5 +#define E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE 0x10BC +#define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9 +#define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA +#define E1000_DEV_ID_82572EI_COPPER 0x107D +#define E1000_DEV_ID_82572EI_FIBER 0x107E +#define E1000_DEV_ID_82572EI_SERDES 0x107F +#define E1000_DEV_ID_82572EI 0x10B9 +#define E1000_DEV_ID_82573E 0x108B +#define E1000_DEV_ID_82573E_IAMT 0x108C +#define E1000_DEV_ID_82573L 0x109A +#define E1000_DEV_ID_82574L 0x10D3 +#define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5 +#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096 +#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098 +#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA +#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB + +#define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049 +#define E1000_DEV_ID_ICH8_IGP_AMT 0x104A +#define E1000_DEV_ID_ICH8_IGP_C 0x104B +#define E1000_DEV_ID_ICH8_IFE 0x104C +#define E1000_DEV_ID_ICH8_IFE_GT 0x10C4 +#define E1000_DEV_ID_ICH8_IFE_G 0x10C5 +#define E1000_DEV_ID_ICH8_IGP_M 0x104D + +#define IGP03E1000_E_PHY_ID 0x02A80390 +#define IFE_E_PHY_ID 0x02A80330 /* 10/100 PHY */ +#define IFE_PLUS_E_PHY_ID 0x02A80320 +#define IFE_C_E_PHY_ID 0x02A80310 + +#define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10 /* 100BaseTx Extended Status, + Control and Address */ +#define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY special + control register */ +#define IFE_PHY_RCV_FALSE_CARRIER 0x13 /* 100BaseTx Receive false + Carrier Counter */ +#define IFE_PHY_RCV_DISCONNECT 0x14 /* 100BaseTx Receive Disconnet + Counter */ +#define IFE_PHY_RCV_ERROT_FRAME 0x15 /* 100BaseTx Receive Error + Frame Counter */ +#define IFE_PHY_RCV_SYMBOL_ERR 0x16 /* Receive Symbol Error + Counter */ +#define IFE_PHY_PREM_EOF_ERR 0x17 /* 100BaseTx Receive + Premature End Of Frame + Error Counter */ +#define IFE_PHY_RCV_EOF_ERR 0x18 /* 10BaseT Receive End Of + Frame Error Counter */ +#define IFE_PHY_TX_JABBER_DETECT 0x19 /* 10BaseT Transmit Jabber + Detect Counter */ +#define IFE_PHY_EQUALIZER 0x1A /* PHY Equalizer Control and + Status */ +#define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY special control and + LED configuration */ +#define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control register */ +#define IFE_PHY_HWI_CONTROL 0x1D /* Hardware Integrity Control + (HWI) */ + +#define IFE_PESC_REDUCED_POWER_DOWN_DISABLE 0x2000 /* Defaut 1 = Disable auto + reduced power down */ +#define IFE_PESC_100BTX_POWER_DOWN 0x0400 /* Indicates the power + state of 100BASE-TX */ +#define IFE_PESC_10BTX_POWER_DOWN 0x0200 /* Indicates the power + state of 10BASE-T */ +#define IFE_PESC_POLARITY_REVERSED 0x0100 /* Indicates 10BASE-T + polarity */ +#define IFE_PESC_PHY_ADDR_MASK 0x007C /* Bit 6:2 for sampled PHY + address */ +#define IFE_PESC_SPEED 0x0002 /* Auto-negotiation speed + result 1=100Mbs, 0=10Mbs */ +#define IFE_PESC_DUPLEX 0x0001 /* Auto-negotiation + duplex result 1=Full, 0=Half */ +#define IFE_PESC_POLARITY_REVERSED_SHIFT 8 + +#define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN 0x0100 /* 1 = Dyanmic Power Down + disabled */ +#define IFE_PSC_FORCE_POLARITY 0x0020 /* 1=Reversed Polarity, + 0=Normal */ +#define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010 /* 1=Auto Polarity + Disabled, 0=Enabled */ +#define IFE_PSC_JABBER_FUNC_DISABLE 0x0001 /* 1=Jabber Disabled, + 0=Normal Jabber Operation */ +#define IFE_PSC_FORCE_POLARITY_SHIFT 5 +#define IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT 4 + +#define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable MDI/MDI-X + feature, default 0=disabled */ +#define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDIX-X, + 0=force MDI */ +#define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */ +#define IFE_PMC_AUTO_MDIX_COMPLETE 0x0010 /* Resolution algorithm + is completed */ +#define IFE_PMC_MDIX_MODE_SHIFT 6 +#define IFE_PHC_MDIX_RESET_ALL_MASK 0x0000 /* Disable auto MDI-X */ + +#define IFE_PHC_HWI_ENABLE 0x8000 /* Enable the HWI + feature */ +#define IFE_PHC_ABILITY_CHECK 0x4000 /* 1= Test Passed, + 0=failed */ +#define IFE_PHC_TEST_EXEC 0x2000 /* PHY launch test pulses + on the wire */ +#define IFE_PHC_HIGHZ 0x0200 /* 1 = Open Circuit */ +#define IFE_PHC_LOWZ 0x0400 /* 1 = Short Circuit */ +#define IFE_PHC_LOW_HIGH_Z_MASK 0x0600 /* Mask for indication + type of problem on the line */ +#define IFE_PHC_DISTANCE_MASK 0x01FF /* Mask for distance to + the cable problem, in 80cm granularity */ +#define IFE_PHC_RESET_ALL_MASK 0x0000 /* Disable HWI */ +#define IFE_PSCL_PROBE_MODE 0x0020 /* LED Probe mode */ +#define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 + off */ +#define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */ + + +#define NUM_DEV_IDS 16 + +#define NODE_ADDRESS_SIZE 6 +#define ETH_LENGTH_OF_ADDRESS 6 + +/* MAC decode size is 128K - This is the size of BAR0 */ +#define MAC_DECODE_SIZE (128 * 1024) + +#define E1000_82542_2_0_REV_ID 2 +#define E1000_82542_2_1_REV_ID 3 +#define E1000_REVISION_0 0 +#define E1000_REVISION_1 1 +#define E1000_REVISION_2 2 +#define E1000_REVISION_3 3 + +#define SPEED_10 10 +#define SPEED_100 100 +#define SPEED_1000 1000 +#define HALF_DUPLEX 1 +#define FULL_DUPLEX 2 + +/* The sizes (in bytes) of a ethernet packet */ +#define ENET_HEADER_SIZE 14 +#define MAXIMUM_ETHERNET_FRAME_SIZE 1518 /* With FCS */ +#define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */ +#define MAXIMUM_ETHERNET_PACKET_SIZE \ + (MAXIMUM_ETHERNET_FRAME_SIZE - ETH_FCS_LEN) +#define MINIMUM_ETHERNET_PACKET_SIZE \ + (MINIMUM_ETHERNET_FRAME_SIZE - ETH_FCS_LEN) +#define CRC_LENGTH ETH_FCS_LEN +#define MAX_JUMBO_FRAME_SIZE 0x3F00 + +/* 802.1q VLAN Packet Sizes */ +#define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMAed) */ + +/* Ethertype field values */ +#define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */ +#define ETHERNET_IP_TYPE 0x0800 /* IP packets */ +#define ETHERNET_ARP_TYPE 0x0806 /* Address Resolution Protocol (ARP) */ + +/* Packet Header defines */ +#define IP_PROTOCOL_TCP 6 +#define IP_PROTOCOL_UDP 0x11 + +/* This defines the bits that are set in the Interrupt Mask + * Set/Read Register. Each bit is documented below: + * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) + * o RXSEQ = Receive Sequence Error + */ +#define POLL_IMS_ENABLE_MASK ( \ + E1000_IMS_RXDMT0 | \ + E1000_IMS_RXSEQ) + +/* This defines the bits that are set in the Interrupt Mask + * Set/Read Register. Each bit is documented below: + * o RXT0 = Receiver Timer Interrupt (ring 0) + * o TXDW = Transmit Descriptor Written Back + * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) + * o RXSEQ = Receive Sequence Error + * o LSC = Link Status Change + */ +#define IMS_ENABLE_MASK ( \ + E1000_IMS_RXT0 | \ + E1000_IMS_TXDW | \ + E1000_IMS_RXDMT0 | \ + E1000_IMS_RXSEQ | \ + E1000_IMS_LSC) + +/* The number of high/low register pairs in the RAR. The RAR (Receive Address + * Registers) holds the directed and multicast addresses that we monitor. We + * reserve one of these spots for our directed address, allowing us room for + * E1000_RAR_ENTRIES - 1 multicast addresses. + */ +#define E1000_RAR_ENTRIES 16 + +#define MIN_NUMBER_OF_DESCRIPTORS 8 +#define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8 + +/* Receive Descriptor */ +struct e1000_rx_desc { + uint64_t buffer_addr; /* Address of the descriptor's data buffer */ + uint16_t length; /* Length of data DMAed into data buffer */ + uint16_t csum; /* Packet checksum */ + uint8_t status; /* Descriptor status */ + uint8_t errors; /* Descriptor Errors */ + uint16_t special; +}; + +/* Receive Decriptor bit definitions */ +#define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ +#define E1000_RXD_STAT_EOP 0x02 /* End of Packet */ +#define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */ +#define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ +#define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ +#define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ +#define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */ +#define E1000_RXD_ERR_CE 0x01 /* CRC Error */ +#define E1000_RXD_ERR_SE 0x02 /* Symbol Error */ +#define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */ +#define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */ +#define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */ +#define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */ +#define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */ +#define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ +#define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */ +#define E1000_RXD_SPC_PRI_SHIFT 0x000D /* Priority is in upper 3 of 16 */ +#define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */ +#define E1000_RXD_SPC_CFI_SHIFT 0x000C /* CFI is bit 12 */ + +/* mask to determine if packets should be dropped due to frame errors */ +#define E1000_RXD_ERR_FRAME_ERR_MASK ( \ + E1000_RXD_ERR_CE | \ + E1000_RXD_ERR_SE | \ + E1000_RXD_ERR_SEQ | \ + E1000_RXD_ERR_CXE | \ + E1000_RXD_ERR_RXE) + +/* Transmit Descriptor */ +struct e1000_tx_desc { + uint64_t buffer_addr; /* Address of the descriptor's data buffer */ + union { + uint32_t data; + struct { + uint16_t length; /* Data buffer length */ + uint8_t cso; /* Checksum offset */ + uint8_t cmd; /* Descriptor control */ + } flags; + } lower; + union { + uint32_t data; + struct { + uint8_t status; /* Descriptor status */ + uint8_t css; /* Checksum start */ + uint16_t special; + } fields; + } upper; +}; + +/* Transmit Descriptor bit definitions */ +#define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */ +#define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */ +#define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ +#define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ +#define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */ +#define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ +#define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */ +#define E1000_TXD_CMD_RS 0x08000000 /* Report Status */ +#define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */ +#define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */ +#define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ +#define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */ +#define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */ +#define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */ +#define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */ +#define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */ +#define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */ +#define E1000_TXD_CMD_IP 0x02000000 /* IP packet */ +#define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */ +#define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */ + +/* Offload Context Descriptor */ +struct e1000_context_desc { + union { + uint32_t ip_config; + struct { + uint8_t ipcss; /* IP checksum start */ + uint8_t ipcso; /* IP checksum offset */ + uint16_t ipcse; /* IP checksum end */ + } ip_fields; + } lower_setup; + union { + uint32_t tcp_config; + struct { + uint8_t tucss; /* TCP checksum start */ + uint8_t tucso; /* TCP checksum offset */ + uint16_t tucse; /* TCP checksum end */ + } tcp_fields; + } upper_setup; + uint32_t cmd_and_length; /* */ + union { + uint32_t data; + struct { + uint8_t status; /* Descriptor status */ + uint8_t hdr_len; /* Header length */ + uint16_t mss; /* Maximum segment size */ + } fields; + } tcp_seg_setup; +}; + +/* Offload data descriptor */ +struct e1000_data_desc { + uint64_t buffer_addr; /* Address of the descriptor's buffer address */ + union { + uint32_t data; + struct { + uint16_t length; /* Data buffer length */ + uint8_t typ_len_ext; /* */ + uint8_t cmd; /* */ + } flags; + } lower; + union { + uint32_t data; + struct { + uint8_t status; /* Descriptor status */ + uint8_t popts; /* Packet Options */ + uint16_t special; /* */ + } fields; + } upper; +}; + +/* Filters */ +#define E1000_NUM_UNICAST 16 /* Unicast filter entries */ +#define E1000_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */ +#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ + +/* Receive Address Register */ +struct e1000_rar { + volatile uint32_t low; /* receive address low */ + volatile uint32_t high; /* receive address high */ +}; + +/* The number of entries in the Multicast Table Array (MTA). */ +#define E1000_NUM_MTA_REGISTERS 128 + +/* IPv4 Address Table Entry */ +struct e1000_ipv4_at_entry { + volatile uint32_t ipv4_addr; /* IP Address (RW) */ + volatile uint32_t reserved; +}; + +/* Four wakeup IP addresses are supported */ +#define E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 4 +#define E1000_IP4AT_SIZE E1000_WAKEUP_IP_ADDRESS_COUNT_MAX +#define E1000_IP6AT_SIZE 1 + +/* IPv6 Address Table Entry */ +struct e1000_ipv6_at_entry { + volatile uint8_t ipv6_addr[16]; +}; + +/* Flexible Filter Length Table Entry */ +struct e1000_fflt_entry { + volatile uint32_t length; /* Flexible Filter Length (RW) */ + volatile uint32_t reserved; +}; + +/* Flexible Filter Mask Table Entry */ +struct e1000_ffmt_entry { + volatile uint32_t mask; /* Flexible Filter Mask (RW) */ + volatile uint32_t reserved; +}; + +/* Flexible Filter Value Table Entry */ +struct e1000_ffvt_entry { + volatile uint32_t value; /* Flexible Filter Value (RW) */ + volatile uint32_t reserved; +}; + +/* Four Flexible Filters are supported */ +#define E1000_FLEXIBLE_FILTER_COUNT_MAX 4 + +/* Each Flexible Filter is at most 128 (0x80) bytes in length */ +#define E1000_FLEXIBLE_FILTER_SIZE_MAX 128 + +#define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX +#define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX +#define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX + +/* Register Set. (82543, 82544) + * + * Registers are defined to be 32 bits and should be accessed as 32 bit values. + * These registers are physically located on the NIC, but are mapped into the + * host memory address space. + * + * RW - register is both readable and writable + * RO - register is read only + * WO - register is write only + * R/clr - register is read only and is cleared when read + * A - register array + */ +#define E1000_CTRL 0x00000 /* Device Control - RW */ +#define E1000_STATUS 0x00008 /* Device Status - RO */ +#define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */ +#define E1000_I210_EECD 0x12010 /* EEPROM/Flash Control - RW */ +#define E1000_EERD 0x00014 /* EEPROM Read - RW */ +#define E1000_I210_EERD 0x12014 /* EEPROM Read - RW */ +#define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */ +#define E1000_MDIC 0x00020 /* MDI Control - RW */ +#define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */ +#define E1000_FCAH 0x0002C /* Flow Control Address High -RW */ +#define E1000_FCT 0x00030 /* Flow Control Type - RW */ +#define E1000_VET 0x00038 /* VLAN Ether Type - RW */ +#define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */ +#define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */ +#define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */ +#define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */ +#define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */ +#define E1000_I210_IAM 0x000E0 /* Interrupt Ack Auto Mask - RW */ +#define E1000_RCTL 0x00100 /* RX Control - RW */ +#define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */ +#define E1000_TXCW 0x00178 /* TX Configuration Word - RW */ +#define E1000_RXCW 0x00180 /* RX Configuration Word - RO */ +#define E1000_TCTL 0x00400 /* TX Control - RW */ +#define E1000_TCTL_EXT 0x00404 /* Extended TX Control - RW */ +#define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */ +#define E1000_TBT 0x00448 /* TX Burst Timer - RW */ +#define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */ +#define E1000_LEDCTL 0x00E00 /* LED Control - RW */ +#define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */ +#define E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */ +#define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */ +#define E1000_I210_PHY_CTRL 0x00E14 /* PHY Control Register in CSR */ +#define FEXTNVM_SW_CONFIG 0x0001 +#define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */ +#define E1000_PBS 0x01008 /* Packet Buffer Size */ +#define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */ +#define E1000_I210_EEMNGCTL 0x12030 /* MNG EEprom Control */ +#define E1000_FLASH_UPDATES 1000 +#define E1000_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */ +#define E1000_FLASHT 0x01028 /* FLASH Timer Register */ +#define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */ +#define E1000_I210_EEWR 0x12018 /* EEPROM Write Register - RW */ +#define E1000_FLSWCTL 0x01030 /* FLASH control register */ +#define E1000_FLSWDATA 0x01034 /* FLASH data register */ +#define E1000_FLSWCNT 0x01038 /* FLASH Access Counter */ +#define E1000_FLOP 0x0103C /* FLASH Opcode Register */ +#define E1000_ERT 0x02008 /* Early Rx Threshold - RW */ +#define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */ +#define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */ +#define E1000_RDBAL 0x02800 /* RX Descriptor Base Address Low - RW */ +#define E1000_RDBAH 0x02804 /* RX Descriptor Base Address High - RW */ +#define E1000_RDLEN 0x02808 /* RX Descriptor Length - RW */ +#define E1000_RDH 0x02810 /* RX Descriptor Head - RW */ +#define E1000_RDT 0x02818 /* RX Descriptor Tail - RW */ +#define E1000_RDTR 0x02820 /* RX Delay Timer - RW */ +#define E1000_RXDCTL 0x02828 /* RX Descriptor Control - RW */ +#define E1000_RADV 0x0282C /* RX Interrupt Absolute Delay Timer - RW */ +#define E1000_RSRPD 0x02C00 /* RX Small Packet Detect - RW */ +#define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */ +#define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */ +#define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */ +#define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */ +#define E1000_TDFTS 0x03428 /* TX Data FIFO Tail Saved - RW */ +#define E1000_TDFPC 0x03430 /* TX Data FIFO Packet Count - RW */ +#define E1000_TDBAL 0x03800 /* TX Descriptor Base Address Low - RW */ +#define E1000_TDBAH 0x03804 /* TX Descriptor Base Address High - RW */ +#define E1000_TDLEN 0x03808 /* TX Descriptor Length - RW */ +#define E1000_TDH 0x03810 /* TX Descriptor Head - RW */ +#define E1000_TDT 0x03818 /* TX Descripotr Tail - RW */ +#define E1000_TIDV 0x03820 /* TX Interrupt Delay Value - RW */ +#define E1000_TXDCTL 0x03828 /* TX Descriptor Control - RW */ +#define E1000_TADV 0x0382C /* TX Interrupt Absolute Delay Val - RW */ +#define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */ +#define E1000_TARC0 0x03840 /* TX Arbitration Count (0) */ +#define E1000_TDBAL1 0x03900 /* TX Desc Base Address Low (1) - RW */ +#define E1000_TDBAH1 0x03904 /* TX Desc Base Address High (1) - RW */ +#define E1000_TDLEN1 0x03908 /* TX Desc Length (1) - RW */ +#define E1000_TDH1 0x03910 /* TX Desc Head (1) - RW */ +#define E1000_TDT1 0x03918 /* TX Desc Tail (1) - RW */ +#define E1000_TXDCTL1 0x03928 /* TX Descriptor Control (1) - RW */ +#define E1000_TARC1 0x03940 /* TX Arbitration Count (1) */ +#define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */ +#define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */ +#define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */ +#define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */ +#define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */ +#define E1000_SCC 0x04014 /* Single Collision Count - R/clr */ +#define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */ +#define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */ +#define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */ +#define E1000_COLC 0x04028 /* Collision Count - R/clr */ +#define E1000_DC 0x04030 /* Defer Count - R/clr */ +#define E1000_TNCRS 0x04034 /* TX-No CRS - R/clr */ +#define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */ +#define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */ +#define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */ +#define E1000_XONRXC 0x04048 /* XON RX Count - R/clr */ +#define E1000_XONTXC 0x0404C /* XON TX Count - R/clr */ +#define E1000_XOFFRXC 0x04050 /* XOFF RX Count - R/clr */ +#define E1000_XOFFTXC 0x04054 /* XOFF TX Count - R/clr */ +#define E1000_FCRUC 0x04058 /* Flow Control RX Unsupported Count- R/clr */ +#define E1000_PRC64 0x0405C /* Packets RX (64 bytes) - R/clr */ +#define E1000_PRC127 0x04060 /* Packets RX (65-127 bytes) - R/clr */ +#define E1000_PRC255 0x04064 /* Packets RX (128-255 bytes) - R/clr */ +#define E1000_PRC511 0x04068 /* Packets RX (255-511 bytes) - R/clr */ +#define E1000_PRC1023 0x0406C /* Packets RX (512-1023 bytes) - R/clr */ +#define E1000_PRC1522 0x04070 /* Packets RX (1024-1522 bytes) - R/clr */ +#define E1000_GPRC 0x04074 /* Good Packets RX Count - R/clr */ +#define E1000_BPRC 0x04078 /* Broadcast Packets RX Count - R/clr */ +#define E1000_MPRC 0x0407C /* Multicast Packets RX Count - R/clr */ +#define E1000_GPTC 0x04080 /* Good Packets TX Count - R/clr */ +#define E1000_GORCL 0x04088 /* Good Octets RX Count Low - R/clr */ +#define E1000_GORCH 0x0408C /* Good Octets RX Count High - R/clr */ +#define E1000_GOTCL 0x04090 /* Good Octets TX Count Low - R/clr */ +#define E1000_GOTCH 0x04094 /* Good Octets TX Count High - R/clr */ +#define E1000_RNBC 0x040A0 /* RX No Buffers Count - R/clr */ +#define E1000_RUC 0x040A4 /* RX Undersize Count - R/clr */ +#define E1000_RFC 0x040A8 /* RX Fragment Count - R/clr */ +#define E1000_ROC 0x040AC /* RX Oversize Count - R/clr */ +#define E1000_RJC 0x040B0 /* RX Jabber Count - R/clr */ +#define E1000_MGTPRC 0x040B4 /* Management Packets RX Count - R/clr */ +#define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */ +#define E1000_MGTPTC 0x040BC /* Management Packets TX Count - R/clr */ +#define E1000_TORL 0x040C0 /* Total Octets RX Low - R/clr */ +#define E1000_TORH 0x040C4 /* Total Octets RX High - R/clr */ +#define E1000_TOTL 0x040C8 /* Total Octets TX Low - R/clr */ +#define E1000_TOTH 0x040CC /* Total Octets TX High - R/clr */ +#define E1000_TPR 0x040D0 /* Total Packets RX - R/clr */ +#define E1000_TPT 0x040D4 /* Total Packets TX - R/clr */ +#define E1000_PTC64 0x040D8 /* Packets TX (64 bytes) - R/clr */ +#define E1000_PTC127 0x040DC /* Packets TX (65-127 bytes) - R/clr */ +#define E1000_PTC255 0x040E0 /* Packets TX (128-255 bytes) - R/clr */ +#define E1000_PTC511 0x040E4 /* Packets TX (256-511 bytes) - R/clr */ +#define E1000_PTC1023 0x040E8 /* Packets TX (512-1023 bytes) - R/clr */ +#define E1000_PTC1522 0x040EC /* Packets TX (1024-1522 Bytes) - R/clr */ +#define E1000_MPTC 0x040F0 /* Multicast Packets TX Count - R/clr */ +#define E1000_BPTC 0x040F4 /* Broadcast Packets TX Count - R/clr */ +#define E1000_TSCTC 0x040F8 /* TCP Segmentation Context TX - R/clr */ +#define E1000_TSCTFC 0x040FC /* TCP Segmentation Context TX Fail - R/clr */ +#define E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */ +#define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */ +#define E1000_RA 0x05400 /* Receive Address - RW Array */ +#define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */ +#define E1000_WUC 0x05800 /* Wakeup Control - RW */ +#define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */ +#define E1000_WUS 0x05810 /* Wakeup Status - RO */ +#define E1000_MANC 0x05820 /* Management Control - RW */ +#define E1000_IPAV 0x05838 /* IP Address Valid - RW */ +#define E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */ +#define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */ +#define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */ +#define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */ +#define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */ +#define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */ +#define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */ + +/* Register Set (82542) + * + * Some of the 82542 registers are located at different offsets than they are + * in more current versions of the 8254x. Despite the difference in location, + * the registers function in the same manner. + */ +#define E1000_82542_CTRL E1000_CTRL +#define E1000_82542_STATUS E1000_STATUS +#define E1000_82542_EECD E1000_EECD +#define E1000_82542_EERD E1000_EERD +#define E1000_82542_CTRL_EXT E1000_CTRL_EXT +#define E1000_82542_MDIC E1000_MDIC +#define E1000_82542_FCAL E1000_FCAL +#define E1000_82542_FCAH E1000_FCAH +#define E1000_82542_FCT E1000_FCT +#define E1000_82542_VET E1000_VET +#define E1000_82542_RA 0x00040 +#define E1000_82542_ICR E1000_ICR +#define E1000_82542_ITR E1000_ITR +#define E1000_82542_ICS E1000_ICS +#define E1000_82542_IMS E1000_IMS +#define E1000_82542_IMC E1000_IMC +#define E1000_82542_RCTL E1000_RCTL +#define E1000_82542_RDTR 0x00108 +#define E1000_82542_RDBAL 0x00110 +#define E1000_82542_RDBAH 0x00114 +#define E1000_82542_RDLEN 0x00118 +#define E1000_82542_RDH 0x00120 +#define E1000_82542_RDT 0x00128 +#define E1000_82542_FCRTH 0x00160 +#define E1000_82542_FCRTL 0x00168 +#define E1000_82542_FCTTV E1000_FCTTV +#define E1000_82542_TXCW E1000_TXCW +#define E1000_82542_RXCW E1000_RXCW +#define E1000_82542_MTA 0x00200 +#define E1000_82542_TCTL E1000_TCTL +#define E1000_82542_TIPG E1000_TIPG +#define E1000_82542_TDBAL 0x00420 +#define E1000_82542_TDBAH 0x00424 +#define E1000_82542_TDLEN 0x00428 +#define E1000_82542_TDH 0x00430 +#define E1000_82542_TDT 0x00438 +#define E1000_82542_TIDV 0x00440 +#define E1000_82542_TBT E1000_TBT +#define E1000_82542_AIT E1000_AIT +#define E1000_82542_VFTA 0x00600 +#define E1000_82542_LEDCTL E1000_LEDCTL +#define E1000_82542_PBA E1000_PBA +#define E1000_82542_RXDCTL E1000_RXDCTL +#define E1000_82542_RADV E1000_RADV +#define E1000_82542_RSRPD E1000_RSRPD +#define E1000_82542_TXDMAC E1000_TXDMAC +#define E1000_82542_TXDCTL E1000_TXDCTL +#define E1000_82542_TADV E1000_TADV +#define E1000_82542_TSPMT E1000_TSPMT +#define E1000_82542_CRCERRS E1000_CRCERRS +#define E1000_82542_ALGNERRC E1000_ALGNERRC +#define E1000_82542_SYMERRS E1000_SYMERRS +#define E1000_82542_RXERRC E1000_RXERRC +#define E1000_82542_MPC E1000_MPC +#define E1000_82542_SCC E1000_SCC +#define E1000_82542_ECOL E1000_ECOL +#define E1000_82542_MCC E1000_MCC +#define E1000_82542_LATECOL E1000_LATECOL +#define E1000_82542_COLC E1000_COLC +#define E1000_82542_DC E1000_DC +#define E1000_82542_TNCRS E1000_TNCRS +#define E1000_82542_SEC E1000_SEC +#define E1000_82542_CEXTERR E1000_CEXTERR +#define E1000_82542_RLEC E1000_RLEC +#define E1000_82542_XONRXC E1000_XONRXC +#define E1000_82542_XONTXC E1000_XONTXC +#define E1000_82542_XOFFRXC E1000_XOFFRXC +#define E1000_82542_XOFFTXC E1000_XOFFTXC +#define E1000_82542_FCRUC E1000_FCRUC +#define E1000_82542_PRC64 E1000_PRC64 +#define E1000_82542_PRC127 E1000_PRC127 +#define E1000_82542_PRC255 E1000_PRC255 +#define E1000_82542_PRC511 E1000_PRC511 +#define E1000_82542_PRC1023 E1000_PRC1023 +#define E1000_82542_PRC1522 E1000_PRC1522 +#define E1000_82542_GPRC E1000_GPRC +#define E1000_82542_BPRC E1000_BPRC +#define E1000_82542_MPRC E1000_MPRC +#define E1000_82542_GPTC E1000_GPTC +#define E1000_82542_GORCL E1000_GORCL +#define E1000_82542_GORCH E1000_GORCH +#define E1000_82542_GOTCL E1000_GOTCL +#define E1000_82542_GOTCH E1000_GOTCH +#define E1000_82542_RNBC E1000_RNBC +#define E1000_82542_RUC E1000_RUC +#define E1000_82542_RFC E1000_RFC +#define E1000_82542_ROC E1000_ROC +#define E1000_82542_RJC E1000_RJC +#define E1000_82542_MGTPRC E1000_MGTPRC +#define E1000_82542_MGTPDC E1000_MGTPDC +#define E1000_82542_MGTPTC E1000_MGTPTC +#define E1000_82542_TORL E1000_TORL +#define E1000_82542_TORH E1000_TORH +#define E1000_82542_TOTL E1000_TOTL +#define E1000_82542_TOTH E1000_TOTH +#define E1000_82542_TPR E1000_TPR +#define E1000_82542_TPT E1000_TPT +#define E1000_82542_PTC64 E1000_PTC64 +#define E1000_82542_PTC127 E1000_PTC127 +#define E1000_82542_PTC255 E1000_PTC255 +#define E1000_82542_PTC511 E1000_PTC511 +#define E1000_82542_PTC1023 E1000_PTC1023 +#define E1000_82542_PTC1522 E1000_PTC1522 +#define E1000_82542_MPTC E1000_MPTC +#define E1000_82542_BPTC E1000_BPTC +#define E1000_82542_TSCTC E1000_TSCTC +#define E1000_82542_TSCTFC E1000_TSCTFC +#define E1000_82542_RXCSUM E1000_RXCSUM +#define E1000_82542_WUC E1000_WUC +#define E1000_82542_WUFC E1000_WUFC +#define E1000_82542_WUS E1000_WUS +#define E1000_82542_MANC E1000_MANC +#define E1000_82542_IPAV E1000_IPAV +#define E1000_82542_IP4AT E1000_IP4AT +#define E1000_82542_IP6AT E1000_IP6AT +#define E1000_82542_WUPL E1000_WUPL +#define E1000_82542_WUPM E1000_WUPM +#define E1000_82542_FFLT E1000_FFLT +#define E1000_82542_FFMT E1000_FFMT +#define E1000_82542_FFVT E1000_FFVT + +/* Statistics counters collected by the MAC */ +struct e1000_hw_stats { + uint64_t crcerrs; + uint64_t algnerrc; + uint64_t symerrs; + uint64_t rxerrc; + uint64_t mpc; + uint64_t scc; + uint64_t ecol; + uint64_t mcc; + uint64_t latecol; + uint64_t colc; + uint64_t dc; + uint64_t tncrs; + uint64_t sec; + uint64_t cexterr; + uint64_t rlec; + uint64_t xonrxc; + uint64_t xontxc; + uint64_t xoffrxc; + uint64_t xofftxc; + uint64_t fcruc; + uint64_t prc64; + uint64_t prc127; + uint64_t prc255; + uint64_t prc511; + uint64_t prc1023; + uint64_t prc1522; + uint64_t gprc; + uint64_t bprc; + uint64_t mprc; + uint64_t gptc; + uint64_t gorcl; + uint64_t gorch; + uint64_t gotcl; + uint64_t gotch; + uint64_t rnbc; + uint64_t ruc; + uint64_t rfc; + uint64_t roc; + uint64_t rjc; + uint64_t mgprc; + uint64_t mgpdc; + uint64_t mgptc; + uint64_t torl; + uint64_t torh; + uint64_t totl; + uint64_t toth; + uint64_t tpr; + uint64_t tpt; + uint64_t ptc64; + uint64_t ptc127; + uint64_t ptc255; + uint64_t ptc511; + uint64_t ptc1023; + uint64_t ptc1522; + uint64_t mptc; + uint64_t bptc; + uint64_t tsctc; + uint64_t tsctfc; +}; + +#ifndef CONFIG_E1000_NO_NVM +struct e1000_eeprom_info { +e1000_eeprom_type type; + uint16_t word_size; + uint16_t opcode_bits; + uint16_t address_bits; + uint16_t delay_usec; + uint16_t page_size; + bool use_eerd; + bool use_eewr; +}; +#endif + +typedef enum { + e1000_smart_speed_default = 0, + e1000_smart_speed_on, + e1000_smart_speed_off +} e1000_smart_speed; + +typedef enum { + e1000_dsp_config_disabled = 0, + e1000_dsp_config_enabled, + e1000_dsp_config_activated, + e1000_dsp_config_undefined = 0xFF +} e1000_dsp_config; + +typedef enum { + e1000_ms_hw_default = 0, + e1000_ms_force_master, + e1000_ms_force_slave, + e1000_ms_auto +} e1000_ms_type; + +typedef enum { + e1000_ffe_config_enabled = 0, + e1000_ffe_config_active, + e1000_ffe_config_blocked +} e1000_ffe_config; + + +/* Structure containing variables used by the shared code (e1000_hw.c) */ +struct e1000_hw { + const char *name; + struct list_head list_node; +#ifndef CONFIG_DM_ETH + struct eth_device *nic; +#endif +#ifdef CONFIG_E1000_SPI + struct spi_slave spi; +#endif + unsigned int cardnum; + + pci_dev_t pdev; + uint8_t *hw_addr; + e1000_mac_type mac_type; + e1000_phy_type phy_type; + uint32_t phy_init_script; + uint32_t txd_cmd; + e1000_media_type media_type; + e1000_fc_type fc; + e1000_bus_type bus_type; +#if 0 + e1000_bus_speed bus_speed; + e1000_bus_width bus_width; + uint32_t io_base; +#endif + uint32_t asf_firmware_present; +#ifndef CONFIG_E1000_NO_NVM + uint32_t eeprom_semaphore_present; +#endif + uint32_t swfw_sync_present; + uint32_t swfwhw_semaphore_present; +#ifndef CONFIG_E1000_NO_NVM + struct e1000_eeprom_info eeprom; +#endif + e1000_ms_type master_slave; + e1000_ms_type original_master_slave; + e1000_ffe_config ffe_config_state; + uint32_t phy_id; + uint32_t phy_revision; + uint32_t phy_addr; + uint32_t original_fc; + uint32_t txcw; + uint32_t autoneg_failed; +#if 0 + uint32_t max_frame_size; + uint32_t min_frame_size; + uint32_t mc_filter_type; + uint32_t num_mc_addrs; + uint32_t collision_delta; + uint32_t tx_packet_delta; + uint32_t ledctl_default; + uint32_t ledctl_mode1; + uint32_t ledctl_mode2; +#endif + uint16_t autoneg_advertised; + uint16_t pci_cmd_word; + uint16_t fc_high_water; + uint16_t fc_low_water; + uint16_t fc_pause_time; +#if 0 + uint16_t current_ifs_val; + uint16_t ifs_min_val; + uint16_t ifs_max_val; + uint16_t ifs_step_size; + uint16_t ifs_ratio; +#endif + uint16_t device_id; + uint16_t vendor_id; + uint16_t subsystem_id; + uint16_t subsystem_vendor_id; + uint8_t revision_id; + uint8_t autoneg; + uint8_t mdix; + uint8_t forced_speed_duplex; + uint8_t wait_autoneg_complete; + uint8_t dma_fairness; +#if 0 + uint8_t perm_mac_addr[NODE_ADDRESS_SIZE]; +#endif + bool disable_polarity_correction; + bool speed_downgraded; + bool get_link_status; + bool tbi_compatibility_en; + bool tbi_compatibility_on; + bool fc_strict_ieee; + bool fc_send_xon; + bool report_tx_early; + bool phy_reset_disable; + bool initialize_hw_bits_disable; +#if 0 + bool adaptive_ifs; + bool ifs_params_forced; + bool in_ifs_mode; +#endif + e1000_smart_speed smart_speed; + e1000_dsp_config dsp_config_state; +}; + +#define E1000_EEPROM_SWDPIN0 0x0001 /* SWDPIN 0 EEPROM Value */ +#define E1000_EEPROM_LED_LOGIC 0x0020 /* Led Logic Word */ +#define E1000_EEPROM_RW_REG_DATA 16 /* Offset to data in EEPROM + read/write registers */ +#define E1000_EEPROM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */ +#define E1000_EEPROM_RW_REG_START 1 /* First bit for telling part to start + operation */ +#define E1000_EEPROM_RW_ADDR_SHIFT 2 /* Shift to the address bits */ +#define E1000_EEPROM_POLL_WRITE 1 /* Flag for polling for write + complete */ +#define E1000_EEPROM_POLL_READ 0 /* Flag for polling for read complete */ +#define EEPROM_RESERVED_WORD 0xFFFF + +/* Register Bit Masks */ +/* Device Control */ +#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ +#define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */ +#define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */ +#define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */ +#define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */ +#define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */ +#define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ +#define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ +#define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ +#define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */ +#define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */ +#define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */ +#define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */ +#define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */ +#define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */ +#define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ +#define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ +#define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ +#define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */ +#define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */ +#define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */ +#define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */ +#define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */ +#define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */ +#define E1000_CTRL_RST 0x04000000 /* Global reset */ +#define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ +#define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */ +#define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */ +#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ +#define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */ + +/* Device Status */ +#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */ +#define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ +#define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ +#define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */ +#define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */ +#define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */ +#define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */ +#define E1000_STATUS_SPEED_MASK 0x000000C0 +#define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */ +#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ +#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ +#define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */ +#define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */ +#define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */ +#define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */ +#define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */ +#define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */ +#define E1000_STATUS_PF_RST_DONE 0x00200000 /* PCI-X bus speed */ + +/* Constants used to intrepret the masked PCI-X bus speed. */ +#define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus speed 50-66 MHz */ +#define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed 66-100 MHz */ +#define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus speed 100-133 MHz */ + +/* EEPROM/Flash Control */ +#define E1000_EECD_SK 0x00000001 /* EEPROM Clock */ +#define E1000_EECD_CS 0x00000002 /* EEPROM Chip Select */ +#define E1000_EECD_DI 0x00000004 /* EEPROM Data In */ +#define E1000_EECD_DO 0x00000008 /* EEPROM Data Out */ +#define E1000_EECD_FWE_MASK 0x00000030 +#define E1000_EECD_FWE_DIS 0x00000010 /* Disable FLASH writes */ +#define E1000_EECD_FWE_EN 0x00000020 /* Enable FLASH writes */ +#define E1000_EECD_FWE_SHIFT 4 +#define E1000_EECD_SIZE 0x00000200 /* EEPROM Size (0=64 word 1=256 word) */ +#define E1000_EECD_REQ 0x00000040 /* EEPROM Access Request */ +#define E1000_EECD_GNT 0x00000080 /* EEPROM Access Grant */ +#define E1000_EECD_PRES 0x00000100 /* EEPROM Present */ +#define E1000_EECD_ADDR_BITS 0x00000400 /* EEPROM Addressing bits based on type + * (0-small, 1-large) */ + +#define E1000_EECD_TYPE 0x00002000 /* EEPROM Type (1-SPI, 0-Microwire) */ +#ifndef E1000_EEPROM_GRANT_ATTEMPTS +#define E1000_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */ +#endif +#define E1000_EECD_AUTO_RD 0x00000200 /* EEPROM Auto Read done */ +#define E1000_EECD_SIZE_EX_MASK 0x00007800 /* EEprom Size */ +#define E1000_EECD_SIZE_EX_SHIFT 11 +#define E1000_EECD_NVADDS 0x00018000 /* NVM Address Size */ +#define E1000_EECD_SELSHAD 0x00020000 /* Select Shadow RAM */ +#define E1000_EECD_INITSRAM 0x00040000 /* Initialize Shadow RAM */ +#define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */ +#define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */ +#define E1000_EECD_SHADV 0x00200000 /* Shadow RAM Data Valid */ +#define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */ +#define E1000_EECD_SECVAL_SHIFT 22 +#define E1000_STM_OPCODE 0xDB00 +#define E1000_HICR_FW_RESET 0xC0 + +#define E1000_SHADOW_RAM_WORDS 2048 +#define E1000_ICH_NVM_SIG_WORD 0x13 +#define E1000_ICH_NVM_SIG_MASK 0xC0 + +/* EEPROM Read */ +#define E1000_EERD_START 0x00000001 /* Start Read */ +#define E1000_EERD_DONE 0x00000010 /* Read Done */ +#define E1000_EERD_ADDR_SHIFT 8 +#define E1000_EERD_ADDR_MASK 0x0000FF00 /* Read Address */ +#define E1000_EERD_DATA_SHIFT 16 +#define E1000_EERD_DATA_MASK 0xFFFF0000 /* Read Data */ + +/* EEPROM Commands - Microwire */ +#define EEPROM_READ_OPCODE_MICROWIRE 0x6 /* EEPROM read opcode */ +#define EEPROM_WRITE_OPCODE_MICROWIRE 0x5 /* EEPROM write opcode */ +#define EEPROM_ERASE_OPCODE_MICROWIRE 0x7 /* EEPROM erase opcode */ +#define EEPROM_EWEN_OPCODE_MICROWIRE 0x13 /* EEPROM erase/write enable */ +#define EEPROM_EWDS_OPCODE_MICROWIRE 0x10 /* EEPROM erast/write disable */ + +/* EEPROM Commands - SPI */ +#define EEPROM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */ +#define EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */ +#define EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */ +#define EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */ +#define EEPROM_WREN_OPCODE_SPI 0x06 /* EEPROM set Write Enable latch */ +#define EEPROM_WRDI_OPCODE_SPI 0x04 /* EEPROM reset Write Enable latch */ +#define EEPROM_RDSR_OPCODE_SPI 0x05 /* EEPROM read Status register */ +#define EEPROM_WRSR_OPCODE_SPI 0x01 /* EEPROM write Status register */ +#define EEPROM_ERASE4K_OPCODE_SPI 0x20 /* EEPROM ERASE 4KB */ +#define EEPROM_ERASE64K_OPCODE_SPI 0xD8 /* EEPROM ERASE 64KB */ +#define EEPROM_ERASE256_OPCODE_SPI 0xDB /* EEPROM ERASE 256B */ + +/* EEPROM Size definitions */ +#define EEPROM_WORD_SIZE_SHIFT 6 +#define EEPROM_SIZE_SHIFT 10 +#define EEPROM_SIZE_MASK 0x1C00 + +/* EEPROM Word Offsets */ +#define EEPROM_COMPAT 0x0003 +#define EEPROM_ID_LED_SETTINGS 0x0004 +#define EEPROM_VERSION 0x0005 +#define EEPROM_SERDES_AMPLITUDE 0x0006 /* For SERDES output amplitude + adjustment. */ +#define EEPROM_PHY_CLASS_WORD 0x0007 +#define EEPROM_INIT_CONTROL1_REG 0x000A +#define EEPROM_INIT_CONTROL2_REG 0x000F +#define EEPROM_SWDEF_PINS_CTRL_PORT_1 0x0010 +#define EEPROM_INIT_CONTROL3_PORT_B 0x0014 +#define EEPROM_INIT_3GIO_3 0x001A +#define EEPROM_SWDEF_PINS_CTRL_PORT_0 0x0020 +#define EEPROM_INIT_CONTROL3_PORT_A 0x0024 +#define EEPROM_CFG 0x0012 +#define EEPROM_FLASH_VERSION 0x0032 +#define EEPROM_CHECKSUM_REG 0x003F + +#define E1000_EEPROM_CFG_DONE 0x00040000 /* MNG config cycle done */ +#define E1000_EEPROM_CFG_DONE_PORT_1 0x00080000 /* ...for second port */ + +/* Extended Device Control */ +#define E1000_CTRL_EXT_GPI0_EN 0x00000001 /* Maps SDP4 to GPI0 */ +#define E1000_CTRL_EXT_GPI1_EN 0x00000002 /* Maps SDP5 to GPI1 */ +#define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN +#define E1000_CTRL_EXT_GPI2_EN 0x00000004 /* Maps SDP6 to GPI2 */ +#define E1000_CTRL_EXT_GPI3_EN 0x00000008 /* Maps SDP7 to GPI3 */ +#define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Defineable + Pin 4 */ +#define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Defineable + Pin 5 */ +#define E1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA +#define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Defineable Pin 6 */ +#define E1000_CTRL_EXT_SWDPIN6 0x00000040 /* SWDPIN 6 value */ +#define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Defineable Pin 7 */ +#define E1000_CTRL_EXT_SWDPIN7 0x00000080 /* SWDPIN 7 value */ +#define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */ +#define E1000_CTRL_EXT_SDP5_DIR 0x00000200 /* Direction of SDP5 0=in 1=out */ +#define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */ +#define E1000_CTRL_EXT_SWDPIO6 0x00000400 /* SWDPIN 6 Input or output */ +#define E1000_CTRL_EXT_SDP7_DIR 0x00000800 /* Direction of SDP7 0=in 1=out */ +#define E1000_CTRL_EXT_SWDPIO7 0x00000800 /* SWDPIN 7 Input or output */ +#define E1000_CTRL_EXT_ASDCHK 0x00001000 /* Initiate an ASD sequence */ +#define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */ +#define E1000_CTRL_EXT_IPS 0x00004000 /* Invert Power State */ +#define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */ +#define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ +#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 +#define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000 +#define E1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000 +#define E1000_CTRL_EXT_WR_WMARK_MASK 0x03000000 +#define E1000_CTRL_EXT_WR_WMARK_256 0x00000000 +#define E1000_CTRL_EXT_WR_WMARK_320 0x01000000 +#define E1000_CTRL_EXT_WR_WMARK_384 0x02000000 +#define E1000_CTRL_EXT_WR_WMARK_448 0x03000000 + +/* MDI Control */ +#define E1000_MDIC_DATA_MASK 0x0000FFFF +#define E1000_MDIC_REG_MASK 0x001F0000 +#define E1000_MDIC_REG_SHIFT 16 +#define E1000_MDIC_PHY_MASK 0x03E00000 +#define E1000_MDIC_PHY_SHIFT 21 +#define E1000_MDIC_OP_WRITE 0x04000000 +#define E1000_MDIC_OP_READ 0x08000000 +#define E1000_MDIC_READY 0x10000000 +#define E1000_MDIC_INT_EN 0x20000000 +#define E1000_MDIC_ERROR 0x40000000 + +#define E1000_PHY_CTRL_SPD_EN 0x00000001 +#define E1000_PHY_CTRL_D0A_LPLU 0x00000002 +#define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004 +#define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008 +#define E1000_PHY_CTRL_GBE_DISABLE 0x00000040 +#define E1000_PHY_CTRL_B2B_EN 0x00000080 +/* LED Control */ +#define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F +#define E1000_LEDCTL_LED0_MODE_SHIFT 0 +#define E1000_LEDCTL_LED0_IVRT 0x00000040 +#define E1000_LEDCTL_LED0_BLINK 0x00000080 +#define E1000_LEDCTL_LED1_MODE_MASK 0x00000F00 +#define E1000_LEDCTL_LED1_MODE_SHIFT 8 +#define E1000_LEDCTL_LED1_IVRT 0x00004000 +#define E1000_LEDCTL_LED1_BLINK 0x00008000 +#define E1000_LEDCTL_LED2_MODE_MASK 0x000F0000 +#define E1000_LEDCTL_LED2_MODE_SHIFT 16 +#define E1000_LEDCTL_LED2_IVRT 0x00400000 +#define E1000_LEDCTL_LED2_BLINK 0x00800000 +#define E1000_LEDCTL_LED3_MODE_MASK 0x0F000000 +#define E1000_LEDCTL_LED3_MODE_SHIFT 24 +#define E1000_LEDCTL_LED3_IVRT 0x40000000 +#define E1000_LEDCTL_LED3_BLINK 0x80000000 + +#define E1000_LEDCTL_MODE_LINK_10_1000 0x0 +#define E1000_LEDCTL_MODE_LINK_100_1000 0x1 +#define E1000_LEDCTL_MODE_LINK_UP 0x2 +#define E1000_LEDCTL_MODE_ACTIVITY 0x3 +#define E1000_LEDCTL_MODE_LINK_ACTIVITY 0x4 +#define E1000_LEDCTL_MODE_LINK_10 0x5 +#define E1000_LEDCTL_MODE_LINK_100 0x6 +#define E1000_LEDCTL_MODE_LINK_1000 0x7 +#define E1000_LEDCTL_MODE_PCIX_MODE 0x8 +#define E1000_LEDCTL_MODE_FULL_DUPLEX 0x9 +#define E1000_LEDCTL_MODE_COLLISION 0xA +#define E1000_LEDCTL_MODE_BUS_SPEED 0xB +#define E1000_LEDCTL_MODE_BUS_SIZE 0xC +#define E1000_LEDCTL_MODE_PAUSED 0xD +#define E1000_LEDCTL_MODE_LED_ON 0xE +#define E1000_LEDCTL_MODE_LED_OFF 0xF + +/* Receive Address */ +#define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */ + +/* Interrupt Cause Read */ +#define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */ +#define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */ +#define E1000_ICR_LSC 0x00000004 /* Link Status Change */ +#define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */ +#define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */ +#define E1000_ICR_RXO 0x00000040 /* rx overrun */ +#define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */ +#define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */ +#define E1000_ICR_RXCFG 0x00000400 /* RX /c/ ordered set */ +#define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */ +#define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */ +#define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */ +#define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */ +#define E1000_ICR_TXD_LOW 0x00008000 +#define E1000_ICR_SRPD 0x00010000 + +/* Interrupt Cause Set */ +#define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ +#define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ +#define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ +#define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ +#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ +#define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */ +#define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ +#define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */ +#define E1000_ICS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ +#define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ +#define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ +#define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ +#define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ +#define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW +#define E1000_ICS_SRPD E1000_ICR_SRPD + +/* Interrupt Mask Set */ +#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ +#define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ +#define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */ +#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ +#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ +#define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */ +#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ +#define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */ +#define E1000_IMS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ +#define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ +#define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ +#define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ +#define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ +#define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW +#define E1000_IMS_SRPD E1000_ICR_SRPD + +/* Interrupt Mask Clear */ +#define E1000_IMC_TXDW E1000_ICR_TXDW /* Transmit desc written back */ +#define E1000_IMC_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ +#define E1000_IMC_LSC E1000_ICR_LSC /* Link Status Change */ +#define E1000_IMC_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ +#define E1000_IMC_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ +#define E1000_IMC_RXO E1000_ICR_RXO /* rx overrun */ +#define E1000_IMC_RXT0 E1000_ICR_RXT0 /* rx timer intr */ +#define E1000_IMC_MDAC E1000_ICR_MDAC /* MDIO access complete */ +#define E1000_IMC_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ +#define E1000_IMC_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ +#define E1000_IMC_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ +#define E1000_IMC_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ +#define E1000_IMC_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ +#define E1000_IMC_TXD_LOW E1000_ICR_TXD_LOW +#define E1000_IMC_SRPD E1000_ICR_SRPD + +/* Receive Control */ +#define E1000_RCTL_RST 0x00000001 /* Software reset */ +#define E1000_RCTL_EN 0x00000002 /* enable */ +#define E1000_RCTL_SBP 0x00000004 /* store bad packet */ +#define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */ +#define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */ +#define E1000_RCTL_LPE 0x00000020 /* long packet enable */ +#define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */ +#define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ +#define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */ +#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ +#define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */ +#define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min threshold size */ +#define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min threshold size */ +#define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */ +#define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */ +#define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */ +#define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */ +#define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */ +#define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */ +#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */ +/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */ +#define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */ +#define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */ +#define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */ +#define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */ +/* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */ +#define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */ +#define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */ +#define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */ +#define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */ +#define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */ +#define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */ +#define E1000_RCTL_DPF 0x00400000 /* discard pause frames */ +#define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */ +#define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */ + +/* SW_W_SYNC definitions */ +#define E1000_SWFW_EEP_SM 0x0001 +#define E1000_SWFW_PHY0_SM 0x0002 +#define E1000_SWFW_PHY1_SM 0x0004 +#define E1000_SWFW_MAC_CSR_SM 0x0008 + +/* Receive Descriptor */ +#define E1000_RDT_DELAY 0x0000ffff /* Delay timer (1=1024us) */ +#define E1000_RDT_FPDB 0x80000000 /* Flush descriptor block */ +#define E1000_RDLEN_LEN 0x0007ff80 /* descriptor length */ +#define E1000_RDH_RDH 0x0000ffff /* receive descriptor head */ +#define E1000_RDT_RDT 0x0000ffff /* receive descriptor tail */ + +/* Flow Control */ +#define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */ +#define E1000_FCRTH_XFCE 0x80000000 /* External Flow Control Enable */ +#define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */ +#define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ + +/* Receive Descriptor Control */ +#define E1000_RXDCTL_PTHRESH 0x0000003F /* RXDCTL Prefetch Threshold */ +#define E1000_RXDCTL_HTHRESH 0x00003F00 /* RXDCTL Host Threshold */ +#define E1000_RXDCTL_WTHRESH 0x003F0000 /* RXDCTL Writeback Threshold */ +#define E1000_RXDCTL_GRAN 0x01000000 /* RXDCTL Granularity */ +#define E1000_RXDCTL_FULL_RX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */ + +/* Transmit Descriptor Control */ +#define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */ +#define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */ +#define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */ +#define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */ +#define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */ +#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */ +#define E1000_TXDCTL_COUNT_DESC 0x00400000 /* Enable the counting of desc. + still to be processed. */ + +/* Transmit Configuration Word */ +#define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */ +#define E1000_TXCW_HD 0x00000040 /* TXCW half duplex */ +#define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */ +#define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */ +#define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */ +#define E1000_TXCW_RF 0x00003000 /* TXCW remote fault */ +#define E1000_TXCW_NP 0x00008000 /* TXCW next page */ +#define E1000_TXCW_CW 0x0000ffff /* TxConfigWord mask */ +#define E1000_TXCW_TXC 0x40000000 /* Transmit Config control */ +#define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */ + +/* Receive Configuration Word */ +#define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */ +#define E1000_RXCW_NC 0x04000000 /* Receive config no carrier */ +#define E1000_RXCW_IV 0x08000000 /* Receive config invalid */ +#define E1000_RXCW_CC 0x10000000 /* Receive config change */ +#define E1000_RXCW_C 0x20000000 /* Receive config */ +#define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */ +#define E1000_RXCW_ANC 0x80000000 /* Auto-neg complete */ + +/* Transmit Control */ +#define E1000_TCTL_RST 0x00000001 /* software reset */ +#define E1000_TCTL_EN 0x00000002 /* enable tx */ +#define E1000_TCTL_BCE 0x00000004 /* busy check enable */ +#define E1000_TCTL_PSP 0x00000008 /* pad short packets */ +#define E1000_TCTL_CT 0x00000ff0 /* collision threshold */ +#define E1000_TCTL_COLD 0x003ff000 /* collision distance */ +#define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */ +#define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */ +#define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ +#define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */ +#define E1000_TCTL_MULR 0x10000000 /* Multiple request support */ + +/* Receive Checksum Control */ +#define E1000_RXCSUM_PCSS_MASK 0x000000FF /* Packet Checksum Start */ +#define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */ +#define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */ +#define E1000_RXCSUM_IPV6OFL 0x00000400 /* IPv6 checksum offload */ + +/* Definitions for power management and wakeup registers */ +/* Wake Up Control */ +#define E1000_WUC_APME 0x00000001 /* APM Enable */ +#define E1000_WUC_PME_EN 0x00000002 /* PME Enable */ +#define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */ +#define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */ + +/* Wake Up Filter Control */ +#define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ +#define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ +#define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ +#define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ +#define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ +#define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ +#define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */ +#define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */ +#define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */ +#define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */ +#define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */ +#define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */ +#define E1000_WUFC_ALL_FILTERS 0x000F00FF /* Mask for all wakeup filters */ +#define E1000_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */ +#define E1000_WUFC_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */ + +/* Wake Up Status */ +#define E1000_WUS_LNKC 0x00000001 /* Link Status Changed */ +#define E1000_WUS_MAG 0x00000002 /* Magic Packet Received */ +#define E1000_WUS_EX 0x00000004 /* Directed Exact Received */ +#define E1000_WUS_MC 0x00000008 /* Directed Multicast Received */ +#define E1000_WUS_BC 0x00000010 /* Broadcast Received */ +#define E1000_WUS_ARP 0x00000020 /* ARP Request Packet Received */ +#define E1000_WUS_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Received */ +#define E1000_WUS_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Received */ +#define E1000_WUS_FLX0 0x00010000 /* Flexible Filter 0 Match */ +#define E1000_WUS_FLX1 0x00020000 /* Flexible Filter 1 Match */ +#define E1000_WUS_FLX2 0x00040000 /* Flexible Filter 2 Match */ +#define E1000_WUS_FLX3 0x00080000 /* Flexible Filter 3 Match */ +#define E1000_WUS_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */ + +/* Management Control */ +#define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */ +#define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */ +#define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */ +#define E1000_MANC_RMCP_EN 0x00000100 /* Enable RCMP 026Fh Filtering */ +#define E1000_MANC_0298_EN 0x00000200 /* Enable RCMP 0298h Filtering */ +#define E1000_MANC_IPV4_EN 0x00000400 /* Enable IPv4 */ +#define E1000_MANC_IPV6_EN 0x00000800 /* Enable IPv6 */ +#define E1000_MANC_SNAP_EN 0x00001000 /* Accept LLC/SNAP */ +#define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */ +#define E1000_MANC_NEIGHBOR_EN 0x00004000 /* Enable Neighbor Discovery + * Filtering */ +#define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */ +#define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ +#define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */ +#define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */ +#define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */ +#define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */ +#define E1000_MANC_SMB_DATA_IN 0x08000000 /* SMBus Data In */ +#define E1000_MANC_SMB_DATA_OUT 0x10000000 /* SMBus Data Out */ +#define E1000_MANC_SMB_CLK_OUT 0x20000000 /* SMBus Clock Out */ + +#define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */ +#define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */ + +/* Wake Up Packet Length */ +#define E1000_WUPL_LENGTH_MASK 0x0FFF /* Only the lower 12 bits are valid */ + +#define E1000_MDALIGN 4096 + +/* EEPROM Commands */ +#define EEPROM_READ_OPCODE 0x6 /* EERPOM read opcode */ +#define EEPROM_WRITE_OPCODE 0x5 /* EERPOM write opcode */ +#define EEPROM_ERASE_OPCODE 0x7 /* EERPOM erase opcode */ +#define EEPROM_EWEN_OPCODE 0x13 /* EERPOM erase/write enable */ +#define EEPROM_EWDS_OPCODE 0x10 /* EERPOM erast/write disable */ + +/* Word definitions for ID LED Settings */ +#define ID_LED_RESERVED_0000 0x0000 +#define ID_LED_RESERVED_FFFF 0xFFFF +#define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \ + (ID_LED_OFF1_OFF2 << 8) | \ + (ID_LED_DEF1_DEF2 << 4) | \ + (ID_LED_DEF1_DEF2)) +#define ID_LED_DEF1_DEF2 0x1 +#define ID_LED_DEF1_ON2 0x2 +#define ID_LED_DEF1_OFF2 0x3 +#define ID_LED_ON1_DEF2 0x4 +#define ID_LED_ON1_ON2 0x5 +#define ID_LED_ON1_OFF2 0x6 +#define ID_LED_OFF1_DEF2 0x7 +#define ID_LED_OFF1_ON2 0x8 +#define ID_LED_OFF1_OFF2 0x9 + +/* Mask bits for fields in Word 0x03 of the EEPROM */ +#define EEPROM_COMPAT_SERVER 0x0400 +#define EEPROM_COMPAT_CLIENT 0x0200 + +/* Mask bits for fields in Word 0x0a of the EEPROM */ +#define EEPROM_WORD0A_ILOS 0x0010 +#define EEPROM_WORD0A_SWDPIO 0x01E0 +#define EEPROM_WORD0A_LRST 0x0200 +#define EEPROM_WORD0A_FD 0x0400 +#define EEPROM_WORD0A_66MHZ 0x0800 + +/* Mask bits for fields in Word 0x0f of the EEPROM */ +#define EEPROM_WORD0F_PAUSE_MASK 0x3000 +#define EEPROM_WORD0F_PAUSE 0x1000 +#define EEPROM_WORD0F_ASM_DIR 0x2000 +#define EEPROM_WORD0F_ANE 0x0800 +#define EEPROM_WORD0F_SWPDIO_EXT 0x00F0 + +/* For checksumming, the sum of all words in the EEPROM should equal 0xBABA. */ +#define EEPROM_SUM 0xBABA + +/* EEPROM Map defines (WORD OFFSETS)*/ +#define EEPROM_NODE_ADDRESS_BYTE_0 0 +#define EEPROM_PBA_BYTE_1 8 + +/* EEPROM Map Sizes (Byte Counts) */ +#define PBA_SIZE 4 + +/* Collision related configuration parameters */ +#define E1000_COLLISION_THRESHOLD 0xF +#define E1000_CT_SHIFT 4 +#define E1000_COLLISION_DISTANCE 63 +#define E1000_COLLISION_DISTANCE_82542 64 +#define E1000_FDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE +#define E1000_HDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE +#define E1000_GB_HDX_COLLISION_DISTANCE 512 +#define E1000_COLD_SHIFT 12 + +/* The number of Transmit and Receive Descriptors must be a multiple of 8 */ +#define REQ_TX_DESCRIPTOR_MULTIPLE 8 +#define REQ_RX_DESCRIPTOR_MULTIPLE 8 + +/* Default values for the transmit IPG register */ +#define DEFAULT_82542_TIPG_IPGT 10 +#define DEFAULT_82543_TIPG_IPGT_FIBER 9 +#define DEFAULT_82543_TIPG_IPGT_COPPER 8 + +#define E1000_TIPG_IPGT_MASK 0x000003FF +#define E1000_TIPG_IPGR1_MASK 0x000FFC00 +#define E1000_TIPG_IPGR2_MASK 0x3FF00000 + +#define DEFAULT_82542_TIPG_IPGR1 2 +#define DEFAULT_82543_TIPG_IPGR1 8 +#define E1000_TIPG_IPGR1_SHIFT 10 + +#define DEFAULT_82542_TIPG_IPGR2 10 +#define DEFAULT_82543_TIPG_IPGR2 6 +#define DEFAULT_80003ES2LAN_TIPG_IPGR2 7 +#define E1000_TIPG_IPGR2_SHIFT 20 + +#define E1000_TXDMAC_DPP 0x00000001 + +/* Adaptive IFS defines */ +#define TX_THRESHOLD_START 8 +#define TX_THRESHOLD_INCREMENT 10 +#define TX_THRESHOLD_DECREMENT 1 +#define TX_THRESHOLD_STOP 190 +#define TX_THRESHOLD_DISABLE 0 +#define TX_THRESHOLD_TIMER_MS 10000 +#define MIN_NUM_XMITS 1000 +#define IFS_MAX 80 +#define IFS_STEP 10 +#define IFS_MIN 40 +#define IFS_RATIO 4 + +/* PBA constants */ +#define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */ +#define E1000_PBA_24K 0x0018 +#define E1000_PBA_38K 0x0026 +#define E1000_PBA_40K 0x0028 +#define E1000_PBA_48K 0x0030 /* 48KB, default RX allocation */ + +/* Flow Control Constants */ +#define FLOW_CONTROL_ADDRESS_LOW 0x00C28001 +#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100 +#define FLOW_CONTROL_TYPE 0x8808 + +/* The historical defaults for the flow control values are given below. */ +#define FC_DEFAULT_HI_THRESH (0x8000) /* 32KB */ +#define FC_DEFAULT_LO_THRESH (0x4000) /* 16KB */ +#define FC_DEFAULT_TX_TIMER (0x100) /* ~130 us */ + +/* Flow Control High-Watermark: 43464 bytes */ +#define E1000_FC_HIGH_THRESH 0xA9C8 +/* Flow Control Low-Watermark: 43456 bytes */ +#define E1000_FC_LOW_THRESH 0xA9C0 +/* Flow Control Pause Time: 858 usec */ +#define E1000_FC_PAUSE_TIME 0x0680 + +/* PCIX Config space */ +#define PCIX_COMMAND_REGISTER 0xE6 +#define PCIX_STATUS_REGISTER_LO 0xE8 +#define PCIX_STATUS_REGISTER_HI 0xEA + +#define PCIX_COMMAND_MMRBC_MASK 0x000C +#define PCIX_COMMAND_MMRBC_SHIFT 0x2 +#define PCIX_STATUS_HI_MMRBC_MASK 0x0060 +#define PCIX_STATUS_HI_MMRBC_SHIFT 0x5 +#define PCIX_STATUS_HI_MMRBC_4K 0x3 +#define PCIX_STATUS_HI_MMRBC_2K 0x2 + +/* The number of bits that we need to shift right to move the "pause" + * bits from the EEPROM (bits 13:12) to the "pause" (bits 8:7) field + * in the TXCW register + */ +#define PAUSE_SHIFT 5 + +/* The number of bits that we need to shift left to move the "SWDPIO" + * bits from the EEPROM (bits 8:5) to the "SWDPIO" (bits 25:22) field + * in the CTRL register + */ +#define SWDPIO_SHIFT 17 + +/* The number of bits that we need to shift left to move the "SWDPIO_EXT" + * bits from the EEPROM word F (bits 7:4) to the bits 11:8 of The + * Extended CTRL register. + * in the CTRL register + */ +#define SWDPIO__EXT_SHIFT 4 + +/* The number of bits that we need to shift left to move the "ILOS" + * bit from the EEPROM (bit 4) to the "ILOS" (bit 7) field + * in the CTRL register + */ +#define ILOS_SHIFT 3 + +#define RECEIVE_BUFFER_ALIGN_SIZE (256) + +/* The number of milliseconds we wait for auto-negotiation to complete */ +#define LINK_UP_TIMEOUT 500 + +#define E1000_TX_BUFFER_SIZE ((uint32_t)1514) + +/* The carrier extension symbol, as received by the NIC. */ +#define CARRIER_EXTENSION 0x0F + +/* TBI_ACCEPT macro definition: + * + * This macro requires: + * adapter = a pointer to struct e1000_hw + * status = the 8 bit status field of the RX descriptor with EOP set + * error = the 8 bit error field of the RX descriptor with EOP set + * length = the sum of all the length fields of the RX descriptors that + * make up the current frame + * last_byte = the last byte of the frame DMAed by the hardware + * max_frame_length = the maximum frame length we want to accept. + * min_frame_length = the minimum frame length we want to accept. + * + * This macro is a conditional that should be used in the interrupt + * handler's Rx processing routine when RxErrors have been detected. + * + * Typical use: + * ... + * if (TBI_ACCEPT) { + * accept_frame = true; + * e1000_tbi_adjust_stats(adapter, MacAddress); + * frame_length--; + * } else { + * accept_frame = false; + * } + * ... + */ + +#define TBI_ACCEPT(adapter, status, errors, length, last_byte) \ + ((adapter)->tbi_compatibility_on && \ + (((errors) & E1000_RXD_ERR_FRAME_ERR_MASK) == E1000_RXD_ERR_CE) && \ + ((last_byte) == CARRIER_EXTENSION) && \ + (((status) & E1000_RXD_STAT_VP) ? \ + (((length) > ((adapter)->min_frame_size - VLAN_TAG_SIZE)) && \ + ((length) <= ((adapter)->max_frame_size + 1))) : \ + (((length) > (adapter)->min_frame_size) && \ + ((length) <= ((adapter)->max_frame_size + VLAN_TAG_SIZE + 1))))) + +/* Structures, enums, and macros for the PHY */ + +/* Bit definitions for the Management Data IO (MDIO) and Management Data + * Clock (MDC) pins in the Device Control Register. + */ +#define E1000_CTRL_PHY_RESET_DIR E1000_CTRL_SWDPIO0 +#define E1000_CTRL_PHY_RESET E1000_CTRL_SWDPIN0 +#define E1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2 +#define E1000_CTRL_MDIO E1000_CTRL_SWDPIN2 +#define E1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3 +#define E1000_CTRL_MDC E1000_CTRL_SWDPIN3 +#define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR +#define E1000_CTRL_PHY_RESET4 E1000_CTRL_EXT_SDP4_DATA + +/* PHY 1000 MII Register/Bit Definitions */ +/* PHY Registers defined by IEEE */ +#define PHY_CTRL 0x00 /* Control Register */ +#define PHY_STATUS 0x01 /* Status Regiser */ +#define PHY_ID1 0x02 /* Phy Id Reg (word 1) */ +#define PHY_ID2 0x03 /* Phy Id Reg (word 2) */ +#define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ +#define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */ +#define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */ +#define PHY_NEXT_PAGE_TX 0x07 /* Next Page TX */ +#define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */ +#define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */ +#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */ +#define PHY_EXT_STATUS 0x0F /* Extended Status Reg */ + +/* M88E1000 Specific Registers */ +#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */ +#define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */ +#define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Register */ +#define M88E1000_INT_STATUS 0x13 /* Interrupt Status Register */ +#define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */ +#define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */ + +#define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */ +#define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */ + +#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ + +/* M88EC018 Rev 2 specific DownShift settings */ +#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00 +#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_1X 0x0000 +#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_2X 0x0200 +#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_3X 0x0400 +#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_4X 0x0600 +#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800 +#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_6X 0x0A00 +#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_7X 0x0C00 +#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_8X 0x0E00 + +/* IGP01E1000 specifics */ +#define IGP01E1000_IEEE_REGS_PAGE 0x0000 +#define IGP01E1000_IEEE_RESTART_AUTONEG 0x3300 +#define IGP01E1000_IEEE_FORCE_GIGA 0x0140 + +/* IGP01E1000 Specific Registers */ +#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* PHY Specific Port Config Register */ +#define IGP01E1000_PHY_PORT_STATUS 0x11 /* PHY Specific Status Register */ +#define IGP01E1000_PHY_PORT_CTRL 0x12 /* PHY Specific Control Register */ +#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health Register */ +#define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO Register */ +#define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality Register */ +#define IGP02E1000_PHY_POWER_MGMT 0x19 +#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* PHY Page Select Core Register */ + +/* IGP01E1000 AGC Registers - stores the cable length values*/ +#define IGP01E1000_PHY_AGC_A 0x1172 +#define IGP01E1000_PHY_AGC_B 0x1272 +#define IGP01E1000_PHY_AGC_C 0x1472 +#define IGP01E1000_PHY_AGC_D 0x1872 + +/* IGP01E1000 Specific Port Config Register - R/W */ +#define IGP01E1000_PSCFR_AUTO_MDIX_PAR_DETECT 0x0010 +#define IGP01E1000_PSCFR_PRE_EN 0x0020 +#define IGP01E1000_PSCFR_SMART_SPEED 0x0080 +#define IGP01E1000_PSCFR_DISABLE_TPLOOPBACK 0x0100 +#define IGP01E1000_PSCFR_DISABLE_JABBER 0x0400 +#define IGP01E1000_PSCFR_DISABLE_TRANSMIT 0x2000 +/* IGP02E1000 AGC Registers for cable length values */ +#define IGP02E1000_PHY_AGC_A 0x11B1 +#define IGP02E1000_PHY_AGC_B 0x12B1 +#define IGP02E1000_PHY_AGC_C 0x14B1 +#define IGP02E1000_PHY_AGC_D 0x18B1 + +#define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */ +#define IGP02E1000_PM_D3_LPLU 0x0004 /* Enable LPLU in + non-D0a modes */ +#define IGP02E1000_PM_D0_LPLU 0x0002 /* Enable LPLU in + D0a mode */ + +/* IGP01E1000 DSP Reset Register */ +#define IGP01E1000_PHY_DSP_RESET 0x1F33 +#define IGP01E1000_PHY_DSP_SET 0x1F71 +#define IGP01E1000_PHY_DSP_FFE 0x1F35 + +#define IGP01E1000_PHY_CHANNEL_NUM 4 +#define IGP02E1000_PHY_CHANNEL_NUM 4 + +#define IGP01E1000_PHY_AGC_PARAM_A 0x1171 +#define IGP01E1000_PHY_AGC_PARAM_B 0x1271 +#define IGP01E1000_PHY_AGC_PARAM_C 0x1471 +#define IGP01E1000_PHY_AGC_PARAM_D 0x1871 + +#define IGP01E1000_PHY_EDAC_MU_INDEX 0xC000 +#define IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS 0x8000 + +#define IGP01E1000_PHY_ANALOG_TX_STATE 0x2890 +#define IGP01E1000_PHY_ANALOG_CLASS_A 0x2000 +#define IGP01E1000_PHY_FORCE_ANALOG_ENABLE 0x0004 +#define IGP01E1000_PHY_DSP_FFE_CM_CP 0x0069 + +#define IGP01E1000_PHY_DSP_FFE_DEFAULT 0x002A +/* IGP01E1000 PCS Initialization register - stores the polarity status when + * speed = 1000 Mbps. */ +#define IGP01E1000_PHY_PCS_INIT_REG 0x00B4 +#define IGP01E1000_PHY_PCS_CTRL_REG 0x00B5 + +#define IGP01E1000_ANALOG_REGS_PAGE 0x20C0 + +/* IGP01E1000 GMII FIFO Register */ +#define IGP01E1000_GMII_FLEX_SPD 0x10 /* Enable flexible speed + * on Link-Up */ +#define IGP01E1000_GMII_SPD 0x20 /* Enable SPD */ + +/* IGP01E1000 Analog Register */ +#define IGP01E1000_ANALOG_SPARE_FUSE_STATUS 0x20D1 +#define IGP01E1000_ANALOG_FUSE_STATUS 0x20D0 +#define IGP01E1000_ANALOG_FUSE_CONTROL 0x20DC +#define IGP01E1000_ANALOG_FUSE_BYPASS 0x20DE + +#define IGP01E1000_ANALOG_FUSE_POLY_MASK 0xF000 +#define IGP01E1000_ANALOG_FUSE_FINE_MASK 0x0F80 +#define IGP01E1000_ANALOG_FUSE_COARSE_MASK 0x0070 +#define IGP01E1000_ANALOG_SPARE_FUSE_ENABLED 0x0100 +#define IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL 0x0002 + +#define IGP01E1000_ANALOG_FUSE_COARSE_THRESH 0x0040 +#define IGP01E1000_ANALOG_FUSE_COARSE_10 0x0010 +#define IGP01E1000_ANALOG_FUSE_FINE_1 0x0080 +#define IGP01E1000_ANALOG_FUSE_FINE_10 0x0500 + +/* IGP01E1000 Specific Port Control Register - R/W */ +#define IGP01E1000_PSCR_TP_LOOPBACK 0x0010 +#define IGP01E1000_PSCR_CORRECT_NC_SCMBLR 0x0200 +#define IGP01E1000_PSCR_TEN_CRS_SELECT 0x0400 +#define IGP01E1000_PSCR_FLIP_CHIP 0x0800 +#define IGP01E1000_PSCR_AUTO_MDIX 0x1000 +#define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0-MDI, 1-MDIX */ +/* GG82563 PHY Specific Status Register (Page 0, Register 16 */ +#define GG82563_PSCR_DISABLE_JABBER 0x0001 /* 1=Disable Jabber */ +#define GG82563_PSCR_POLARITY_REVERSAL_DISABLE 0x0002 /* 1=Polarity Reversal + Disabled */ +#define GG82563_PSCR_POWER_DOWN 0x0004 /* 1=Power Down */ +#define GG82563_PSCR_COPPER_TRANSMITER_DISABLE 0x0008 /* 1=Transmitter + Disabled */ +#define GG82563_PSCR_CROSSOVER_MODE_MASK 0x0060 +#define GG82563_PSCR_CROSSOVER_MODE_MDI 0x0000 /* 00=Manual MDI + configuration */ +#define GG82563_PSCR_CROSSOVER_MODE_MDIX 0x0020 /* 01=Manual MDIX + configuration */ +#define GG82563_PSCR_CROSSOVER_MODE_AUTO 0x0060 /* 11=Automatic + crossover */ +#define GG82563_PSCR_ENALBE_EXTENDED_DISTANCE 0x0080 /* 1=Enable Extended + Distance */ +#define GG82563_PSCR_ENERGY_DETECT_MASK 0x0300 +#define GG82563_PSCR_ENERGY_DETECT_OFF 0x0000 /* 00,01=Off */ +#define GG82563_PSCR_ENERGY_DETECT_RX 0x0200 /* 10=Sense on Rx only + (Energy Detect) */ +#define GG82563_PSCR_ENERGY_DETECT_RX_TM 0x0300 /* 11=Sense and Tx NLP */ +#define GG82563_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force Link Good */ +#define GG82563_PSCR_DOWNSHIFT_ENABLE 0x0800 /* 1=Enable Downshift */ +#define GG82563_PSCR_DOWNSHIFT_COUNTER_MASK 0x7000 +#define GG82563_PSCR_DOWNSHIFT_COUNTER_SHIFT 12 + +/* PHY Specific Status Register (Page 0, Register 17) */ +#define GG82563_PSSR_JABBER 0x0001 /* 1=Jabber */ +#define GG82563_PSSR_POLARITY 0x0002 /* 1=Polarity Reversed */ +#define GG82563_PSSR_LINK 0x0008 /* 1=Link is Up */ +#define GG82563_PSSR_ENERGY_DETECT 0x0010 /* 1=Sleep, 0=Active */ +#define GG82563_PSSR_DOWNSHIFT 0x0020 /* 1=Downshift */ +#define GG82563_PSSR_CROSSOVER_STATUS 0x0040 /* 1=MDIX, 0=MDI */ +#define GG82563_PSSR_RX_PAUSE_ENABLED 0x0100 /* 1=Receive Pause Enabled */ +#define GG82563_PSSR_TX_PAUSE_ENABLED 0x0200 /* 1=Transmit Pause Enabled */ +#define GG82563_PSSR_LINK_UP 0x0400 /* 1=Link Up */ +#define GG82563_PSSR_SPEED_DUPLEX_RESOLVED 0x0800 /* 1=Resolved */ +#define GG82563_PSSR_PAGE_RECEIVED 0x1000 /* 1=Page Received */ +#define GG82563_PSSR_DUPLEX 0x2000 /* 1-Full-Duplex */ +#define GG82563_PSSR_SPEED_MASK 0xC000 +#define GG82563_PSSR_SPEED_10MBPS 0x0000 /* 00=10Mbps */ +#define GG82563_PSSR_SPEED_100MBPS 0x4000 /* 01=100Mbps */ +#define GG82563_PSSR_SPEED_1000MBPS 0x8000 /* 10=1000Mbps */ + +/* PHY Specific Status Register 2 (Page 0, Register 19) */ +#define GG82563_PSSR2_JABBER 0x0001 /* 1=Jabber */ +#define GG82563_PSSR2_POLARITY_CHANGED 0x0002 /* 1=Polarity Changed */ +#define GG82563_PSSR2_ENERGY_DETECT_CHANGED 0x0010 /* 1=Energy Detect Changed */ +#define GG82563_PSSR2_DOWNSHIFT_INTERRUPT 0x0020 /* 1=Downshift Detected */ +#define GG82563_PSSR2_MDI_CROSSOVER_CHANGE 0x0040 /* 1=Crossover Changed */ +#define GG82563_PSSR2_FALSE_CARRIER 0x0100 /* 1=false Carrier */ +#define GG82563_PSSR2_SYMBOL_ERROR 0x0200 /* 1=Symbol Error */ +#define GG82563_PSSR2_LINK_STATUS_CHANGED 0x0400 /* 1=Link Status Changed */ +#define GG82563_PSSR2_AUTO_NEG_COMPLETED 0x0800 /* 1=Auto-Neg Completed */ +#define GG82563_PSSR2_PAGE_RECEIVED 0x1000 /* 1=Page Received */ +#define GG82563_PSSR2_DUPLEX_CHANGED 0x2000 /* 1=Duplex Changed */ +#define GG82563_PSSR2_SPEED_CHANGED 0x4000 /* 1=Speed Changed */ +#define GG82563_PSSR2_AUTO_NEG_ERROR 0x8000 /* 1=Auto-Neg Error */ + +/* PHY Specific Control Register 2 (Page 0, Register 26) */ +#define GG82563_PSCR2_10BT_POLARITY_FORCE 0x0002 /* 1=Force Negative + Polarity */ +#define GG82563_PSCR2_1000MB_TEST_SELECT_MASK 0x000C +#define GG82563_PSCR2_1000MB_TEST_SELECT_NORMAL 0x0000 /* 00,01=Normal + Operation */ +#define GG82563_PSCR2_1000MB_TEST_SELECT_112NS 0x0008 /* 10=Select 112ns + Sequence */ +#define GG82563_PSCR2_1000MB_TEST_SELECT_16NS 0x000C /* 11=Select 16ns + Sequence */ +#define GG82563_PSCR2_REVERSE_AUTO_NEG 0x2000 /* 1=Reverse + Auto-Negotiation */ +#define GG82563_PSCR2_1000BT_DISABLE 0x4000 /* 1=Disable + 1000BASE-T */ +#define GG82563_PSCR2_TRANSMITER_TYPE_MASK 0x8000 +#define GG82563_PSCR2_TRANSMITTER_TYPE_CLASS_B 0x0000 /* 0=Class B */ +#define GG82563_PSCR2_TRANSMITTER_TYPE_CLASS_A 0x8000 /* 1=Class A */ + +/* MAC Specific Control Register (Page 2, Register 21) */ +/* Tx clock speed for Link Down and 1000BASE-T for the following speeds */ +#define GG82563_MSCR_TX_CLK_MASK 0x0007 +#define GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ 0x0004 +#define GG82563_MSCR_TX_CLK_100MBPS_25MHZ 0x0005 +#define GG82563_MSCR_TX_CLK_1000MBPS_2_5MHZ 0x0006 +#define GG82563_MSCR_TX_CLK_1000MBPS_25MHZ 0x0007 + +#define GG82563_MSCR_ASSERT_CRS_ON_TX 0x0010 /* 1=Assert */ + +/* DSP Distance Register (Page 5, Register 26) */ +#define GG82563_DSPD_CABLE_LENGTH 0x0007 /* 0 = <50M; + 1 = 50-80M; + 2 = 80-110M; + 3 = 110-140M; + 4 = >140M */ + +/* Kumeran Mode Control Register (Page 193, Register 16) */ +#define GG82563_KMCR_PHY_LEDS_EN 0x0020 /* 1=PHY LEDs, + 0=Kumeran Inband LEDs */ +#define GG82563_KMCR_FORCE_LINK_UP 0x0040 /* 1=Force Link Up */ +#define GG82563_KMCR_SUPPRESS_SGMII_EPD_EXT 0x0080 +#define GG82563_KMCR_MDIO_BUS_SPEED_SELECT_MASK 0x0400 +#define GG82563_KMCR_MDIO_BUS_SPEED_SELECT 0x0400 /* 1=6.25MHz, + 0=0.8MHz */ +#define GG82563_KMCR_PASS_FALSE_CARRIER 0x0800 + +/* Power Management Control Register (Page 193, Register 20) */ +#define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE 0x0001 /* 1=Enalbe SERDES + Electrical Idle */ +#define GG82563_PMCR_DISABLE_PORT 0x0002 /* 1=Disable Port */ +#define GG82563_PMCR_DISABLE_SERDES 0x0004 /* 1=Disable SERDES */ +#define GG82563_PMCR_REVERSE_AUTO_NEG 0x0008 /* 1=Enable Reverse + Auto-Negotiation */ +#define GG82563_PMCR_DISABLE_1000_NON_D0 0x0010 /* 1=Disable 1000Mbps + Auto-Neg in non D0 */ +#define GG82563_PMCR_DISABLE_1000 0x0020 /* 1=Disable 1000Mbps + Auto-Neg Always */ +#define GG82563_PMCR_REVERSE_AUTO_NEG_D0A 0x0040 /* 1=Enable D0a + Reverse Auto-Negotiation */ +#define GG82563_PMCR_FORCE_POWER_STATE 0x0080 /* 1=Force Power State */ +#define GG82563_PMCR_PROGRAMMED_POWER_STATE_MASK 0x0300 +#define GG82563_PMCR_PROGRAMMED_POWER_STATE_DR 0x0000 /* 00=Dr */ +#define GG82563_PMCR_PROGRAMMED_POWER_STATE_D0U 0x0100 /* 01=D0u */ +#define GG82563_PMCR_PROGRAMMED_POWER_STATE_D0A 0x0200 /* 10=D0a */ +#define GG82563_PMCR_PROGRAMMED_POWER_STATE_D3 0x0300 /* 11=D3 */ + +/* In-Band Control Register (Page 194, Register 18) */ +#define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding Use */ + + +/* Bits... + * 15-5: page + * 4-0: register offset + */ +#define GG82563_PAGE_SHIFT 5 +#define GG82563_REG(page, reg) \ + (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS)) +#define GG82563_MIN_ALT_REG 30 + +/* GG82563 Specific Registers */ +#define GG82563_PHY_SPEC_CTRL \ + GG82563_REG(0, 16) /* PHY Specific Control */ +#define GG82563_PHY_SPEC_STATUS \ + GG82563_REG(0, 17) /* PHY Specific Status */ +#define GG82563_PHY_INT_ENABLE \ + GG82563_REG(0, 18) /* Interrupt Enable */ +#define GG82563_PHY_SPEC_STATUS_2 \ + GG82563_REG(0, 19) /* PHY Specific Status 2 */ +#define GG82563_PHY_RX_ERR_CNTR \ + GG82563_REG(0, 21) /* Receive Error Counter */ +#define GG82563_PHY_PAGE_SELECT \ + GG82563_REG(0, 22) /* Page Select */ +#define GG82563_PHY_SPEC_CTRL_2 \ + GG82563_REG(0, 26) /* PHY Specific Control 2 */ +#define GG82563_PHY_PAGE_SELECT_ALT \ + GG82563_REG(0, 29) /* Alternate Page Select */ +#define GG82563_PHY_TEST_CLK_CTRL \ + GG82563_REG(0, 30) /* Test Clock Control (use reg. 29 to select) */ + +#define GG82563_PHY_MAC_SPEC_CTRL \ + GG82563_REG(2, 21) /* MAC Specific Control Register */ +#define GG82563_PHY_MAC_SPEC_CTRL_2 \ + GG82563_REG(2, 26) /* MAC Specific Control 2 */ + +#define GG82563_PHY_DSP_DISTANCE \ + GG82563_REG(5, 26) /* DSP Distance */ + +/* Page 193 - Port Control Registers */ +#define GG82563_PHY_KMRN_MODE_CTRL \ + GG82563_REG(193, 16) /* Kumeran Mode Control */ +#define GG82563_PHY_PORT_RESET \ + GG82563_REG(193, 17) /* Port Reset */ +#define GG82563_PHY_REVISION_ID \ + GG82563_REG(193, 18) /* Revision ID */ +#define GG82563_PHY_DEVICE_ID \ + GG82563_REG(193, 19) /* Device ID */ +#define GG82563_PHY_PWR_MGMT_CTRL \ + GG82563_REG(193, 20) /* Power Management Control */ +#define GG82563_PHY_RATE_ADAPT_CTRL \ + GG82563_REG(193, 25) /* Rate Adaptation Control */ + +/* Page 194 - KMRN Registers */ +#define GG82563_PHY_KMRN_FIFO_CTRL_STAT \ + GG82563_REG(194, 16) /* FIFO's Control/Status */ +#define GG82563_PHY_KMRN_CTRL \ + GG82563_REG(194, 17) /* Control */ +#define GG82563_PHY_INBAND_CTRL \ + GG82563_REG(194, 18) /* Inband Control */ +#define GG82563_PHY_KMRN_DIAGNOSTIC \ + GG82563_REG(194, 19) /* Diagnostic */ +#define GG82563_PHY_ACK_TIMEOUTS \ + GG82563_REG(194, 20) /* Acknowledge Timeouts */ +#define GG82563_PHY_ADV_ABILITY \ + GG82563_REG(194, 21) /* Advertised Ability */ +#define GG82563_PHY_LINK_PARTNER_ADV_ABILITY \ + GG82563_REG(194, 23) /* Link Partner Advertised Ability */ +#define GG82563_PHY_ADV_NEXT_PAGE \ + GG82563_REG(194, 24) /* Advertised Next Page */ +#define GG82563_PHY_LINK_PARTNER_ADV_NEXT_PAGE \ + GG82563_REG(194, 25) /* Link Partner Advertised Next page */ +#define GG82563_PHY_KMRN_MISC \ + GG82563_REG(194, 26) /* Misc. */ + +/* PHY Control Register */ +#define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */ +#define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */ +#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ +#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ +#define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */ +#define MII_CR_POWER_DOWN 0x0800 /* Power down */ +#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ +#define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */ +#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ +#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ + +/* PHY Status Register */ +#define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */ +#define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */ +#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */ +#define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */ +#define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */ +#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */ +#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */ +#define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */ +#define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */ +#define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */ +#define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */ +#define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */ +#define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */ +#define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */ +#define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */ + +/* Autoneg Advertisement Register */ +#define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */ +#define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */ +#define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */ +#define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */ +#define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */ +#define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */ +#define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */ +#define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */ +#define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */ +#define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */ + +/* Link Partner Ability Register (Base Page) */ +#define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */ +#define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP is 10T Half Duplex Capable */ +#define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP is 10T Full Duplex Capable */ +#define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP is 100TX Half Duplex Capable */ +#define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP is 100TX Full Duplex Capable */ +#define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */ +#define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */ +#define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */ +#define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP has detected Remote Fault */ +#define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP has rx'd link code word */ +#define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */ + +/* Autoneg Expansion Register */ +#define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */ +#define NWAY_ER_PAGE_RXD 0x0002 /* LP is 10T Half Duplex Capable */ +#define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP is 10T Full Duplex Capable */ +#define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */ +#define NWAY_ER_PAR_DETECT_FAULT 0x0100 /* LP is 100TX Full Duplex Capable */ + +/* Next Page TX Register */ +#define NPTX_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */ +#define NPTX_TOGGLE 0x0800 /* Toggles between exchanges + * of different NP + */ +#define NPTX_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg + * 0 = cannot comply with msg + */ +#define NPTX_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */ +#define NPTX_NEXT_PAGE 0x8000 /* 1 = addition NP will follow + * 0 = sending last NP + */ + +/* Link Partner Next Page Register */ +#define LP_RNPR_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */ +#define LP_RNPR_TOGGLE 0x0800 /* Toggles between exchanges + * of different NP + */ +#define LP_RNPR_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg + * 0 = cannot comply with msg + */ +#define LP_RNPR_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */ +#define LP_RNPR_ACKNOWLDGE 0x4000 /* 1 = ACK / 0 = NO ACK */ +#define LP_RNPR_NEXT_PAGE 0x8000 /* 1 = addition NP will follow + * 0 = sending last NP + */ + +/* 1000BASE-T Control Register */ +#define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */ +#define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */ +#define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */ +#define CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port */ + /* 0=DTE device */ +#define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */ + /* 0=Configure PHY as Slave */ +#define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */ + /* 0=Automatic Master/Slave config */ +#define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */ +#define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */ +#define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */ +#define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */ +#define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */ + +/* 1000BASE-T Status Register */ +#define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle errors since last read */ +#define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asymmetric pause direction bit */ +#define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */ +#define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */ +#define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */ +#define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */ +#define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master, 0=Slave */ +#define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */ +#define SR_1000T_REMOTE_RX_STATUS_SHIFT 12 +#define SR_1000T_LOCAL_RX_STATUS_SHIFT 13 + +/* Extended Status Register */ +#define IEEE_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */ +#define IEEE_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */ +#define IEEE_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */ +#define IEEE_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */ + +#define PHY_TX_POLARITY_MASK 0x0100 /* register 10h bit 8 (polarity bit) */ +#define PHY_TX_NORMAL_POLARITY 0 /* register 10h bit 8 (normal polarity) */ + +#define AUTO_POLARITY_DISABLE 0x0010 /* register 11h bit 4 */ + /* (0=enable, 1=disable) */ + +/* M88E1000 PHY Specific Control Register */ +#define M88E1000_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */ +#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */ +#define M88E1000_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */ +#define M88E1000_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low, + * 0=CLK125 toggling + */ +#define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */ + /* Manual MDI configuration */ +#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */ +#define M88E1000_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover, + * 100BASE-TX/10BASE-T: + * MDI Mode + */ +#define M88E1000_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled + * all speeds. + */ +#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE 0x0080 + /* 1=Enable Extended 10BASE-T distance + * (Lower 10BASE-T RX Threshold) + * 0=Normal 10BASE-T RX Threshold */ +#define M88E1000_PSCR_MII_5BIT_ENABLE 0x0100 + /* 1=5-Bit interface in 100BASE-TX + * 0=MII interface in 100BASE-TX */ +#define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */ +#define M88E1000_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */ +#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */ + +#define M88E1000_PSCR_POLARITY_REVERSAL_SHIFT 1 +#define M88E1000_PSCR_AUTO_X_MODE_SHIFT 5 +#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7 + +/* M88E1000 PHY Specific Status Register */ +#define M88E1000_PSSR_JABBER 0x0001 /* 1=Jabber */ +#define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */ +#define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */ +#define M88E1000_PSSR_CABLE_LENGTH 0x0380 /* 0=<50M;1=50-80M;2=80-110M; + * 3=110-140M;4=>140M */ +#define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */ +#define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */ +#define M88E1000_PSSR_PAGE_RCVD 0x1000 /* 1=Page received */ +#define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */ +#define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */ +#define M88E1000_PSSR_10MBS 0x0000 /* 00=10Mbs */ +#define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */ +#define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */ + +#define M88E1000_PSSR_REV_POLARITY_SHIFT 1 +#define M88E1000_PSSR_MDIX_SHIFT 6 +#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7 + +/* M88E1000 Extended PHY Specific Control Register */ +#define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */ +#define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000 /* 1=Lost lock detect enabled. + * Will assert lost lock and bring + * link down if idle not seen + * within 1ms in 1000BASE-T + */ +/* Number of times we will attempt to autonegotiate before downshifting if we + * are the master */ +#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00 +#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000 +#define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X 0x0400 +#define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X 0x0800 +#define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X 0x0C00 +/* Number of times we will attempt to autonegotiate before downshifting if we + * are the slave */ +#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300 +#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS 0x0000 +#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100 +#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X 0x0200 +#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X 0x0300 +#define M88E1000_EPSCR_TX_CLK_2_5 0x0060 /* 2.5 MHz TX_CLK */ +#define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */ +#define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */ + +/* Bit definitions for valid PHY IDs. */ +#define M88E1000_E_PHY_ID 0x01410C50 +#define M88E1000_I_PHY_ID 0x01410C30 +#define M88E1011_I_PHY_ID 0x01410C20 +#define M88E1000_12_PHY_ID M88E1000_E_PHY_ID +#define M88E1000_14_PHY_ID M88E1000_E_PHY_ID +#define IGP01E1000_I_PHY_ID 0x02A80380 +#define M88E1011_I_REV_4 0x04 +#define M88E1111_I_PHY_ID 0x01410CC0 +#define L1LXT971A_PHY_ID 0x001378E0 +#define GG82563_E_PHY_ID 0x01410CA0 + +#define BME1000_E_PHY_ID 0x01410CB0 + +#define I210_I_PHY_ID 0x01410C00 + +/* Miscellaneous PHY bit definitions. */ +#define PHY_PREAMBLE 0xFFFFFFFF +#define PHY_SOF 0x01 +#define PHY_OP_READ 0x02 +#define PHY_OP_WRITE 0x01 +#define PHY_TURNAROUND 0x02 +#define PHY_PREAMBLE_SIZE 32 +#define MII_CR_SPEED_1000 0x0040 +#define MII_CR_SPEED_100 0x2000 +#define MII_CR_SPEED_10 0x0000 +#define E1000_PHY_ADDRESS 0x01 +#define PHY_AUTO_NEG_TIME 80 /* 8.0 Seconds */ +#define PHY_FORCE_TIME 20 /* 2.0 Seconds */ +#define PHY_REVISION_MASK 0xFFFFFFF0 +#define DEVICE_SPEED_MASK 0x00000300 /* Device Ctrl Reg Speed Mask */ +#define REG4_SPEED_MASK 0x01E0 +#define REG9_SPEED_MASK 0x0300 +#define ADVERTISE_10_HALF 0x0001 +#define ADVERTISE_10_FULL 0x0002 +#define ADVERTISE_100_HALF 0x0004 +#define ADVERTISE_100_FULL 0x0008 +#define ADVERTISE_1000_HALF 0x0010 +#define ADVERTISE_1000_FULL 0x0020 + +#define ICH_FLASH_GFPREG 0x0000 +#define ICH_FLASH_HSFSTS 0x0004 +#define ICH_FLASH_HSFCTL 0x0006 +#define ICH_FLASH_FADDR 0x0008 +#define ICH_FLASH_FDATA0 0x0010 +#define ICH_FLASH_FRACC 0x0050 +#define ICH_FLASH_FREG0 0x0054 +#define ICH_FLASH_FREG1 0x0058 +#define ICH_FLASH_FREG2 0x005C +#define ICH_FLASH_FREG3 0x0060 +#define ICH_FLASH_FPR0 0x0074 +#define ICH_FLASH_FPR1 0x0078 +#define ICH_FLASH_SSFSTS 0x0090 +#define ICH_FLASH_SSFCTL 0x0092 +#define ICH_FLASH_PREOP 0x0094 +#define ICH_FLASH_OPTYPE 0x0096 +#define ICH_FLASH_OPMENU 0x0098 + +#define ICH_FLASH_REG_MAPSIZE 0x00A0 +#define ICH_FLASH_SECTOR_SIZE 4096 +#define ICH_GFPREG_BASE_MASK 0x1FFF +#define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF + +#define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */ + +/* SPI EEPROM Status Register */ +#define EEPROM_STATUS_RDY_SPI 0x01 +#define EEPROM_STATUS_WEN_SPI 0x02 +#define EEPROM_STATUS_BP0_SPI 0x04 +#define EEPROM_STATUS_BP1_SPI 0x08 +#define EEPROM_STATUS_WPEN_SPI 0x80 + +/* SW Semaphore Register */ +#define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ +#define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ +#define E1000_SWSM_WMNG 0x00000004 /* Wake MNG Clock */ +#define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */ + +/* FW Semaphore Register */ +#define E1000_FWSM_MODE_MASK 0x0000000E /* FW mode */ +#define E1000_FWSM_MODE_SHIFT 1 +#define E1000_FWSM_FW_VALID 0x00008000 /* FW established a valid mode */ + +#define E1000_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI reset */ +#define E1000_FWSM_DISSW 0x10000000 /* FW disable SW Write Access */ +#define E1000_FWSM_SKUSEL_MASK 0x60000000 /* LAN SKU select */ +#define E1000_FWSM_SKUEL_SHIFT 29 +#define E1000_FWSM_SKUSEL_EMB 0x0 /* Embedded SKU */ +#define E1000_FWSM_SKUSEL_CONS 0x1 /* Consumer SKU */ +#define E1000_FWSM_SKUSEL_PERF_100 0x2 /* Perf & Corp 10/100 SKU */ +#define E1000_FWSM_SKUSEL_PERF_GBE 0x3 /* Perf & Copr GbE SKU */ + +#define E1000_GCR 0x05B00 /* PCI-Ex Control */ +#define E1000_GSCL_1 0x05B10 /* PCI-Ex Statistic Control #1 */ +#define E1000_GSCL_2 0x05B14 /* PCI-Ex Statistic Control #2 */ +#define E1000_GSCL_3 0x05B18 /* PCI-Ex Statistic Control #3 */ +#define E1000_GSCL_4 0x05B1C /* PCI-Ex Statistic Control #4 */ +#define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */ +#define E1000_SWSM 0x05B50 /* SW Semaphore */ +#define E1000_FWSM 0x05B54 /* FW Semaphore */ +#define E1000_FFLT_DBG 0x05F04 /* Debug Register */ +#define E1000_HICR 0x08F00 /* Host Inteface Control */ + +#define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF +#define IGP_ACTIVITY_LED_ENABLE 0x0300 +#define IGP_LED3_MODE 0x07000000 + +/* Mask bit for PHY class in Word 7 of the EEPROM */ +#define EEPROM_PHY_CLASS_A 0x8000 +#define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* Everything but 1000-Half */ +#define AUTONEG_ADVERTISE_10_100_ALL 0x000F /* All 10/100 speeds*/ +#define AUTONEG_ADVERTISE_10_ALL 0x0003 /* 10Mbps Full & Half speeds*/ + +#define E1000_KUMCTRLSTA_MASK 0x0000FFFF +#define E1000_KUMCTRLSTA_OFFSET 0x001F0000 +#define E1000_KUMCTRLSTA_OFFSET_SHIFT 16 +#define E1000_KUMCTRLSTA_REN 0x00200000 + +#define E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL 0x00000000 +#define E1000_KUMCTRLSTA_OFFSET_CTRL 0x00000001 +#define E1000_KUMCTRLSTA_OFFSET_INB_CTRL 0x00000002 +#define E1000_KUMCTRLSTA_OFFSET_DIAG 0x00000003 +#define E1000_KUMCTRLSTA_OFFSET_TIMEOUTS 0x00000004 +#define E1000_KUMCTRLSTA_OFFSET_INB_PARAM 0x00000009 +#define E1000_KUMCTRLSTA_OFFSET_HD_CTRL 0x00000010 +#define E1000_KUMCTRLSTA_OFFSET_M2P_SERDES 0x0000001E +#define E1000_KUMCTRLSTA_OFFSET_M2P_MODES 0x0000001F + +/* FIFO Control */ +#define E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS 0x00000008 +#define E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS 0x00000800 + +/* In-Band Control */ +#define E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT 0x00000500 +#define E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING 0x00000010 + +/* Half-Duplex Control */ +#define E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT 0x00000004 +#define E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT 0x00000000 + +#define E1000_KUMCTRLSTA_OFFSET_K0S_CTRL 0x0000001E + +#define E1000_KUMCTRLSTA_DIAG_FELPBK 0x2000 +#define E1000_KUMCTRLSTA_DIAG_NELPBK 0x1000 + +#define E1000_KUMCTRLSTA_K0S_100_EN 0x2000 +#define E1000_KUMCTRLSTA_K0S_GBE_EN 0x1000 +#define E1000_KUMCTRLSTA_K0S_ENTRY_LATENCY_MASK 0x0003 + +#define E1000_MNG_ICH_IAMT_MODE 0x2 +#define E1000_MNG_IAMT_MODE 0x3 +#define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */ +#define E1000_KUMCTRLSTA 0x00034 /* MAC-PHY interface - RW */ +/* Number of milliseconds we wait for PHY configuration done after MAC reset */ +#define PHY_CFG_TIMEOUT 100 +#define DEFAULT_80003ES2LAN_TIPG_IPGT_10_100 0x00000009 +#define DEFAULT_80003ES2LAN_TIPG_IPGT_1000 0x00000008 +#define AUTO_ALL_MODES 0 + +#ifndef E1000_MASTER_SLAVE +/* Switch to override PHY master/slave setting */ +#define E1000_MASTER_SLAVE e1000_ms_hw_default +#endif +/* Extended Transmit Control */ +#define E1000_TCTL_EXT_BST_MASK 0x000003FF /* Backoff Slot Time */ +#define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */ + +#define DEFAULT_80003ES2LAN_TCTL_EXT_GCEX 0x00010000 + +#define PCI_EX_82566_SNOOP_ALL PCI_EX_NO_SNOOP_ALL + +#define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000 +#define E1000_MC_TBL_SIZE_ICH8LAN 32 + +#define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers + after IMS clear */ +#endif /* _E1000_HW_H_ */ diff --git a/sources/uboot-be550/drivers/net/e1000_spi.c b/sources/uboot-be550/drivers/net/e1000_spi.c new file mode 100644 index 00000000..df723752 --- /dev/null +++ b/sources/uboot-be550/drivers/net/e1000_spi.c @@ -0,0 +1,579 @@ +#include +#include +#include "e1000.h" +#include + +/*----------------------------------------------------------------------- + * SPI transfer + * + * This writes "bitlen" bits out the SPI MOSI port and simultaneously clocks + * "bitlen" bits in the SPI MISO port. That's just the way SPI works. + * + * The source of the outgoing bits is the "dout" parameter and the + * destination of the input bits is the "din" parameter. Note that "dout" + * and "din" can point to the same memory location, in which case the + * input data overwrites the output data (since both are buffered by + * temporary variables, this is OK). + * + * This may be interrupted with Ctrl-C if "intr" is true, otherwise it will + * never return an error. + */ +static int e1000_spi_xfer(struct e1000_hw *hw, unsigned int bitlen, + const void *dout_mem, void *din_mem, bool intr) +{ + const uint8_t *dout = dout_mem; + uint8_t *din = din_mem; + + uint8_t mask = 0; + uint32_t eecd; + unsigned long i; + + /* Pre-read the control register */ + eecd = E1000_READ_REG(hw, EECD); + + /* Iterate over each bit */ + for (i = 0, mask = 0x80; i < bitlen; i++, mask = (mask >> 1)?:0x80) { + /* Check for interrupt */ + if (intr && ctrlc()) + return -1; + + /* Determine the output bit */ + if (dout && dout[i >> 3] & mask) + eecd |= E1000_EECD_DI; + else + eecd &= ~E1000_EECD_DI; + + /* Write the output bit and wait 50us */ + E1000_WRITE_REG(hw, EECD, eecd); + E1000_WRITE_FLUSH(hw); + udelay(50); + + /* Poke the clock (waits 50us) */ + e1000_raise_ee_clk(hw, &eecd); + + /* Now read the input bit */ + eecd = E1000_READ_REG(hw, EECD); + if (din) { + if (eecd & E1000_EECD_DO) + din[i >> 3] |= mask; + else + din[i >> 3] &= ~mask; + } + + /* Poke the clock again (waits 50us) */ + e1000_lower_ee_clk(hw, &eecd); + } + + /* Now clear any remaining bits of the input */ + if (din && (i & 7)) + din[i >> 3] &= ~((mask << 1) - 1); + + return 0; +} + +#ifdef CONFIG_E1000_SPI_GENERIC +static inline struct e1000_hw *e1000_hw_from_spi(struct spi_slave *spi) +{ + return container_of(spi, struct e1000_hw, spi); +} + +/* Not sure why all of these are necessary */ +void spi_init_r(void) { /* Nothing to do */ } +void spi_init_f(void) { /* Nothing to do */ } +void spi_init(void) { /* Nothing to do */ } + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + /* Find the right PCI device */ + struct e1000_hw *hw = e1000_find_card(bus); + if (!hw) { + printf("ERROR: No such e1000 device: e1000#%u\n", bus); + return NULL; + } + + /* Make sure it has an SPI chip */ + if (hw->eeprom.type != e1000_eeprom_spi) { + E1000_ERR(hw->nic, "No attached SPI EEPROM found!\n"); + return NULL; + } + + /* Argument sanity checks */ + if (cs != 0) { + E1000_ERR(hw->nic, "No such SPI chip: %u\n", cs); + return NULL; + } + if (mode != SPI_MODE_0) { + E1000_ERR(hw->nic, "Only SPI MODE-0 is supported!\n"); + return NULL; + } + + /* TODO: Use max_hz somehow */ + E1000_DBG(hw->nic, "EEPROM SPI access requested\n"); + return &hw->spi; +} + +void spi_free_slave(struct spi_slave *spi) +{ + __maybe_unused struct e1000_hw *hw = e1000_hw_from_spi(spi); + E1000_DBG(hw->nic, "EEPROM SPI access released\n"); +} + +int spi_claim_bus(struct spi_slave *spi) +{ + struct e1000_hw *hw = e1000_hw_from_spi(spi); + + if (e1000_acquire_eeprom(hw)) { + E1000_ERR(hw->nic, "EEPROM SPI cannot be acquired!\n"); + return -1; + } + + return 0; +} + +void spi_release_bus(struct spi_slave *spi) +{ + struct e1000_hw *hw = e1000_hw_from_spi(spi); + e1000_release_eeprom(hw); +} + +/* Skinny wrapper around e1000_spi_xfer */ +int spi_xfer(struct spi_slave *spi, unsigned int bitlen, + const void *dout_mem, void *din_mem, unsigned long flags) +{ + struct e1000_hw *hw = e1000_hw_from_spi(spi); + int ret; + + if (flags & SPI_XFER_BEGIN) + e1000_standby_eeprom(hw); + + ret = e1000_spi_xfer(hw, bitlen, dout_mem, din_mem, true); + + if (flags & SPI_XFER_END) + e1000_standby_eeprom(hw); + + return ret; +} + +#endif /* not CONFIG_E1000_SPI_GENERIC */ + +#ifdef CONFIG_CMD_E1000 + +/* The EEPROM opcodes */ +#define SPI_EEPROM_ENABLE_WR 0x06 +#define SPI_EEPROM_DISABLE_WR 0x04 +#define SPI_EEPROM_WRITE_STATUS 0x01 +#define SPI_EEPROM_READ_STATUS 0x05 +#define SPI_EEPROM_WRITE_PAGE 0x02 +#define SPI_EEPROM_READ_PAGE 0x03 + +/* The EEPROM status bits */ +#define SPI_EEPROM_STATUS_BUSY 0x01 +#define SPI_EEPROM_STATUS_WREN 0x02 + +static int e1000_spi_eeprom_enable_wr(struct e1000_hw *hw, bool intr) +{ + u8 op[] = { SPI_EEPROM_ENABLE_WR }; + e1000_standby_eeprom(hw); + return e1000_spi_xfer(hw, 8*sizeof(op), op, NULL, intr); +} + +/* + * These have been tested to perform correctly, but they are not used by any + * of the EEPROM commands at this time. + */ +#if 0 +static int e1000_spi_eeprom_disable_wr(struct e1000_hw *hw, bool intr) +{ + u8 op[] = { SPI_EEPROM_DISABLE_WR }; + e1000_standby_eeprom(hw); + return e1000_spi_xfer(hw, 8*sizeof(op), op, NULL, intr); +} + +static int e1000_spi_eeprom_write_status(struct e1000_hw *hw, + u8 status, bool intr) +{ + u8 op[] = { SPI_EEPROM_WRITE_STATUS, status }; + e1000_standby_eeprom(hw); + return e1000_spi_xfer(hw, 8*sizeof(op), op, NULL, intr); +} +#endif + +static int e1000_spi_eeprom_read_status(struct e1000_hw *hw, bool intr) +{ + u8 op[] = { SPI_EEPROM_READ_STATUS, 0 }; + e1000_standby_eeprom(hw); + if (e1000_spi_xfer(hw, 8*sizeof(op), op, op, intr)) + return -1; + return op[1]; +} + +static int e1000_spi_eeprom_write_page(struct e1000_hw *hw, + const void *data, u16 off, u16 len, bool intr) +{ + u8 op[] = { + SPI_EEPROM_WRITE_PAGE, + (off >> (hw->eeprom.address_bits - 8)) & 0xff, off & 0xff + }; + + e1000_standby_eeprom(hw); + + if (e1000_spi_xfer(hw, 8 + hw->eeprom.address_bits, op, NULL, intr)) + return -1; + if (e1000_spi_xfer(hw, len << 3, data, NULL, intr)) + return -1; + + return 0; +} + +static int e1000_spi_eeprom_read_page(struct e1000_hw *hw, + void *data, u16 off, u16 len, bool intr) +{ + u8 op[] = { + SPI_EEPROM_READ_PAGE, + (off >> (hw->eeprom.address_bits - 8)) & 0xff, off & 0xff + }; + + e1000_standby_eeprom(hw); + + if (e1000_spi_xfer(hw, 8 + hw->eeprom.address_bits, op, NULL, intr)) + return -1; + if (e1000_spi_xfer(hw, len << 3, NULL, data, intr)) + return -1; + + return 0; +} + +static int e1000_spi_eeprom_poll_ready(struct e1000_hw *hw, bool intr) +{ + int status; + while ((status = e1000_spi_eeprom_read_status(hw, intr)) >= 0) { + if (!(status & SPI_EEPROM_STATUS_BUSY)) + return 0; + } + return -1; +} + +static int e1000_spi_eeprom_dump(struct e1000_hw *hw, + void *data, u16 off, unsigned int len, bool intr) +{ + /* Interruptibly wait for the EEPROM to be ready */ + if (e1000_spi_eeprom_poll_ready(hw, intr)) + return -1; + + /* Dump each page in sequence */ + while (len) { + /* Calculate the data bytes on this page */ + u16 pg_off = off & (hw->eeprom.page_size - 1); + u16 pg_len = hw->eeprom.page_size - pg_off; + if (pg_len > len) + pg_len = len; + + /* Now dump the page */ + if (e1000_spi_eeprom_read_page(hw, data, off, pg_len, intr)) + return -1; + + /* Otherwise go on to the next page */ + len -= pg_len; + off += pg_len; + data += pg_len; + } + + /* We're done! */ + return 0; +} + +static int e1000_spi_eeprom_program(struct e1000_hw *hw, + const void *data, u16 off, u16 len, bool intr) +{ + /* Program each page in sequence */ + while (len) { + /* Calculate the data bytes on this page */ + u16 pg_off = off & (hw->eeprom.page_size - 1); + u16 pg_len = hw->eeprom.page_size - pg_off; + if (pg_len > len) + pg_len = len; + + /* Interruptibly wait for the EEPROM to be ready */ + if (e1000_spi_eeprom_poll_ready(hw, intr)) + return -1; + + /* Enable write access */ + if (e1000_spi_eeprom_enable_wr(hw, intr)) + return -1; + + /* Now program the page */ + if (e1000_spi_eeprom_write_page(hw, data, off, pg_len, intr)) + return -1; + + /* Otherwise go on to the next page */ + len -= pg_len; + off += pg_len; + data += pg_len; + } + + /* Wait for the last write to complete */ + if (e1000_spi_eeprom_poll_ready(hw, intr)) + return -1; + + /* We're done! */ + return 0; +} + +static int do_e1000_spi_show(cmd_tbl_t *cmdtp, struct e1000_hw *hw, + int argc, char * const argv[]) +{ + unsigned int length = 0; + u16 i, offset = 0; + u8 *buffer; + int err; + + if (argc > 2) { + cmd_usage(cmdtp); + return 1; + } + + /* Parse the offset and length */ + if (argc >= 1) + offset = simple_strtoul(argv[0], NULL, 0); + if (argc == 2) + length = simple_strtoul(argv[1], NULL, 0); + else if (offset < (hw->eeprom.word_size << 1)) + length = (hw->eeprom.word_size << 1) - offset; + + /* Extra sanity checks */ + if (!length) { + E1000_ERR(hw->nic, "Requested zero-sized dump!\n"); + return 1; + } + if ((0x10000 < length) || (0x10000 - length < offset)) { + E1000_ERR(hw->nic, "Can't dump past 0xFFFF!\n"); + return 1; + } + + /* Allocate a buffer to hold stuff */ + buffer = malloc(length); + if (!buffer) { + E1000_ERR(hw->nic, "Out of Memory!\n"); + return 1; + } + + /* Acquire the EEPROM and perform the dump */ + if (e1000_acquire_eeprom(hw)) { + E1000_ERR(hw->nic, "EEPROM SPI cannot be acquired!\n"); + free(buffer); + return 1; + } + err = e1000_spi_eeprom_dump(hw, buffer, offset, length, true); + e1000_release_eeprom(hw); + if (err) { + E1000_ERR(hw->nic, "Interrupted!\n"); + free(buffer); + return 1; + } + + /* Now hexdump the result */ + printf("%s: ===== Intel e1000 EEPROM (0x%04hX - 0x%04hX) =====", + hw->nic->name, offset, offset + length - 1); + for (i = 0; i < length; i++) { + if ((i & 0xF) == 0) + printf("\n%s: %04hX: ", hw->nic->name, offset + i); + else if ((i & 0xF) == 0x8) + printf(" "); + printf(" %02hx", buffer[i]); + } + printf("\n"); + + /* Success! */ + free(buffer); + return 0; +} + +static int do_e1000_spi_dump(cmd_tbl_t *cmdtp, struct e1000_hw *hw, + int argc, char * const argv[]) +{ + unsigned int length; + u16 offset; + void *dest; + + if (argc != 3) { + cmd_usage(cmdtp); + return 1; + } + + /* Parse the arguments */ + dest = (void *)simple_strtoul(argv[0], NULL, 16); + offset = simple_strtoul(argv[1], NULL, 0); + length = simple_strtoul(argv[2], NULL, 0); + + /* Extra sanity checks */ + if (!length) { + E1000_ERR(hw->nic, "Requested zero-sized dump!\n"); + return 1; + } + if ((0x10000 < length) || (0x10000 - length < offset)) { + E1000_ERR(hw->nic, "Can't dump past 0xFFFF!\n"); + return 1; + } + + /* Acquire the EEPROM */ + if (e1000_acquire_eeprom(hw)) { + E1000_ERR(hw->nic, "EEPROM SPI cannot be acquired!\n"); + return 1; + } + + /* Perform the programming operation */ + if (e1000_spi_eeprom_dump(hw, dest, offset, length, true) < 0) { + E1000_ERR(hw->nic, "Interrupted!\n"); + e1000_release_eeprom(hw); + return 1; + } + + e1000_release_eeprom(hw); + printf("%s: ===== EEPROM DUMP COMPLETE =====\n", hw->nic->name); + return 0; +} + +static int do_e1000_spi_program(cmd_tbl_t *cmdtp, struct e1000_hw *hw, + int argc, char * const argv[]) +{ + unsigned int length; + const void *source; + u16 offset; + + if (argc != 3) { + cmd_usage(cmdtp); + return 1; + } + + /* Parse the arguments */ + source = (const void *)simple_strtoul(argv[0], NULL, 16); + offset = simple_strtoul(argv[1], NULL, 0); + length = simple_strtoul(argv[2], NULL, 0); + + /* Acquire the EEPROM */ + if (e1000_acquire_eeprom(hw)) { + E1000_ERR(hw->nic, "EEPROM SPI cannot be acquired!\n"); + return 1; + } + + /* Perform the programming operation */ + if (e1000_spi_eeprom_program(hw, source, offset, length, true) < 0) { + E1000_ERR(hw->nic, "Interrupted!\n"); + e1000_release_eeprom(hw); + return 1; + } + + e1000_release_eeprom(hw); + printf("%s: ===== EEPROM PROGRAMMED =====\n", hw->nic->name); + return 0; +} + +static int do_e1000_spi_checksum(cmd_tbl_t *cmdtp, struct e1000_hw *hw, + int argc, char * const argv[]) +{ + uint16_t i, length, checksum = 0, checksum_reg; + uint16_t *buffer; + bool upd; + + if (argc == 0) + upd = 0; + else if ((argc == 1) && !strcmp(argv[0], "update")) + upd = 1; + else { + cmd_usage(cmdtp); + return 1; + } + + /* Allocate a temporary buffer */ + length = sizeof(uint16_t) * (EEPROM_CHECKSUM_REG + 1); + buffer = malloc(length); + if (!buffer) { + E1000_ERR(hw->nic, "Unable to allocate EEPROM buffer!\n"); + return 1; + } + + /* Acquire the EEPROM */ + if (e1000_acquire_eeprom(hw)) { + E1000_ERR(hw->nic, "EEPROM SPI cannot be acquired!\n"); + return 1; + } + + /* Read the EEPROM */ + if (e1000_spi_eeprom_dump(hw, buffer, 0, length, true) < 0) { + E1000_ERR(hw->nic, "Interrupted!\n"); + e1000_release_eeprom(hw); + return 1; + } + + /* Compute the checksum and read the expected value */ + for (i = 0; i < EEPROM_CHECKSUM_REG; i++) + checksum += le16_to_cpu(buffer[i]); + checksum = ((uint16_t)EEPROM_SUM) - checksum; + checksum_reg = le16_to_cpu(buffer[i]); + + /* Verify it! */ + if (checksum_reg == checksum) { + printf("%s: INFO: EEPROM checksum is correct! (0x%04hx)\n", + hw->nic->name, checksum); + e1000_release_eeprom(hw); + return 0; + } + + /* Hrm, verification failed, print an error */ + E1000_ERR(hw->nic, "EEPROM checksum is incorrect!\n"); + E1000_ERR(hw->nic, " ...register was 0x%04hx, calculated 0x%04hx\n", + checksum_reg, checksum); + + /* If they didn't ask us to update it, just return an error */ + if (!upd) { + e1000_release_eeprom(hw); + return 1; + } + + /* Ok, correct it! */ + printf("%s: Reprogramming the EEPROM checksum...\n", hw->nic->name); + buffer[i] = cpu_to_le16(checksum); + if (e1000_spi_eeprom_program(hw, &buffer[i], i * sizeof(uint16_t), + sizeof(uint16_t), true)) { + E1000_ERR(hw->nic, "Interrupted!\n"); + e1000_release_eeprom(hw); + return 1; + } + + e1000_release_eeprom(hw); + return 0; +} + +int do_e1000_spi(cmd_tbl_t *cmdtp, struct e1000_hw *hw, + int argc, char * const argv[]) +{ + if (argc < 1) { + cmd_usage(cmdtp); + return 1; + } + + /* Make sure it has an SPI chip */ + if (hw->eeprom.type != e1000_eeprom_spi) { + E1000_ERR(hw->nic, "No attached SPI EEPROM found!\n"); + return 1; + } + + /* Check the eeprom sub-sub-command arguments */ + if (!strcmp(argv[0], "show")) + return do_e1000_spi_show(cmdtp, hw, argc - 1, argv + 1); + + if (!strcmp(argv[0], "dump")) + return do_e1000_spi_dump(cmdtp, hw, argc - 1, argv + 1); + + if (!strcmp(argv[0], "program")) + return do_e1000_spi_program(cmdtp, hw, argc - 1, argv + 1); + + if (!strcmp(argv[0], "checksum")) + return do_e1000_spi_checksum(cmdtp, hw, argc - 1, argv + 1); + + cmd_usage(cmdtp); + return 1; +} + +#endif /* not CONFIG_CMD_E1000 */ diff --git a/sources/uboot-be550/drivers/net/eepro100.c b/sources/uboot-be550/drivers/net/eepro100.c new file mode 100644 index 00000000..f2cd32c5 --- /dev/null +++ b/sources/uboot-be550/drivers/net/eepro100.c @@ -0,0 +1,932 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +#undef DEBUG + + /* Ethernet chip registers. + */ +#define SCBStatus 0 /* Rx/Command Unit Status *Word* */ +#define SCBIntAckByte 1 /* Rx/Command Unit STAT/ACK byte */ +#define SCBCmd 2 /* Rx/Command Unit Command *Word* */ +#define SCBIntrCtlByte 3 /* Rx/Command Unit Intr.Control Byte */ +#define SCBPointer 4 /* General purpose pointer. */ +#define SCBPort 8 /* Misc. commands and operands. */ +#define SCBflash 12 /* Flash memory control. */ +#define SCBeeprom 14 /* EEPROM memory control. */ +#define SCBCtrlMDI 16 /* MDI interface control. */ +#define SCBEarlyRx 20 /* Early receive byte count. */ +#define SCBGenControl 28 /* 82559 General Control Register */ +#define SCBGenStatus 29 /* 82559 General Status register */ + + /* 82559 SCB status word defnitions + */ +#define SCB_STATUS_CX 0x8000 /* CU finished command (transmit) */ +#define SCB_STATUS_FR 0x4000 /* frame received */ +#define SCB_STATUS_CNA 0x2000 /* CU left active state */ +#define SCB_STATUS_RNR 0x1000 /* receiver left ready state */ +#define SCB_STATUS_MDI 0x0800 /* MDI read/write cycle done */ +#define SCB_STATUS_SWI 0x0400 /* software generated interrupt */ +#define SCB_STATUS_FCP 0x0100 /* flow control pause interrupt */ + +#define SCB_INTACK_MASK 0xFD00 /* all the above */ + +#define SCB_INTACK_TX (SCB_STATUS_CX | SCB_STATUS_CNA) +#define SCB_INTACK_RX (SCB_STATUS_FR | SCB_STATUS_RNR) + + /* System control block commands + */ +/* CU Commands */ +#define CU_NOP 0x0000 +#define CU_START 0x0010 +#define CU_RESUME 0x0020 +#define CU_STATSADDR 0x0040 /* Load Dump Statistics ctrs addr */ +#define CU_SHOWSTATS 0x0050 /* Dump statistics counters. */ +#define CU_ADDR_LOAD 0x0060 /* Base address to add to CU commands */ +#define CU_DUMPSTATS 0x0070 /* Dump then reset stats counters. */ + +/* RUC Commands */ +#define RUC_NOP 0x0000 +#define RUC_START 0x0001 +#define RUC_RESUME 0x0002 +#define RUC_ABORT 0x0004 +#define RUC_ADDR_LOAD 0x0006 /* (seems not to clear on acceptance) */ +#define RUC_RESUMENR 0x0007 + +#define CU_CMD_MASK 0x00f0 +#define RU_CMD_MASK 0x0007 + +#define SCB_M 0x0100 /* 0 = enable interrupt, 1 = disable */ +#define SCB_SWI 0x0200 /* 1 - cause device to interrupt */ + +#define CU_STATUS_MASK 0x00C0 +#define RU_STATUS_MASK 0x003C + +#define RU_STATUS_IDLE (0<<2) +#define RU_STATUS_SUS (1<<2) +#define RU_STATUS_NORES (2<<2) +#define RU_STATUS_READY (4<<2) +#define RU_STATUS_NO_RBDS_SUS ((1<<2)|(8<<2)) +#define RU_STATUS_NO_RBDS_NORES ((2<<2)|(8<<2)) +#define RU_STATUS_NO_RBDS_READY ((4<<2)|(8<<2)) + + /* 82559 Port interface commands. + */ +#define I82559_RESET 0x00000000 /* Software reset */ +#define I82559_SELFTEST 0x00000001 /* 82559 Selftest command */ +#define I82559_SELECTIVE_RESET 0x00000002 +#define I82559_DUMP 0x00000003 +#define I82559_DUMP_WAKEUP 0x00000007 + + /* 82559 Eeprom interface. + */ +#define EE_SHIFT_CLK 0x01 /* EEPROM shift clock. */ +#define EE_CS 0x02 /* EEPROM chip select. */ +#define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */ +#define EE_WRITE_0 0x01 +#define EE_WRITE_1 0x05 +#define EE_DATA_READ 0x08 /* EEPROM chip data out. */ +#define EE_ENB (0x4800 | EE_CS) +#define EE_CMD_BITS 3 +#define EE_DATA_BITS 16 + + /* The EEPROM commands include the alway-set leading bit. + */ +#define EE_EWENB_CMD (4 << addr_len) +#define EE_WRITE_CMD (5 << addr_len) +#define EE_READ_CMD (6 << addr_len) +#define EE_ERASE_CMD (7 << addr_len) + + /* Receive frame descriptors. + */ +struct RxFD { + volatile u16 status; + volatile u16 control; + volatile u32 link; /* struct RxFD * */ + volatile u32 rx_buf_addr; /* void * */ + volatile u32 count; + + volatile u8 data[PKTSIZE_ALIGN]; +}; + +#define RFD_STATUS_C 0x8000 /* completion of received frame */ +#define RFD_STATUS_OK 0x2000 /* frame received with no errors */ + +#define RFD_CONTROL_EL 0x8000 /* 1=last RFD in RFA */ +#define RFD_CONTROL_S 0x4000 /* 1=suspend RU after receiving frame */ +#define RFD_CONTROL_H 0x0010 /* 1=RFD is a header RFD */ +#define RFD_CONTROL_SF 0x0008 /* 0=simplified, 1=flexible mode */ + +#define RFD_COUNT_MASK 0x3fff +#define RFD_COUNT_F 0x4000 +#define RFD_COUNT_EOF 0x8000 + +#define RFD_RX_CRC 0x0800 /* crc error */ +#define RFD_RX_ALIGNMENT 0x0400 /* alignment error */ +#define RFD_RX_RESOURCE 0x0200 /* out of space, no resources */ +#define RFD_RX_DMA_OVER 0x0100 /* DMA overrun */ +#define RFD_RX_SHORT 0x0080 /* short frame error */ +#define RFD_RX_LENGTH 0x0020 +#define RFD_RX_ERROR 0x0010 /* receive error */ +#define RFD_RX_NO_ADR_MATCH 0x0004 /* no address match */ +#define RFD_RX_IA_MATCH 0x0002 /* individual address does not match */ +#define RFD_RX_TCO 0x0001 /* TCO indication */ + + /* Transmit frame descriptors + */ +struct TxFD { /* Transmit frame descriptor set. */ + volatile u16 status; + volatile u16 command; + volatile u32 link; /* void * */ + volatile u32 tx_desc_addr; /* Always points to the tx_buf_addr element. */ + volatile s32 count; + + volatile u32 tx_buf_addr0; /* void *, frame to be transmitted. */ + volatile s32 tx_buf_size0; /* Length of Tx frame. */ + volatile u32 tx_buf_addr1; /* void *, frame to be transmitted. */ + volatile s32 tx_buf_size1; /* Length of Tx frame. */ +}; + +#define TxCB_CMD_TRANSMIT 0x0004 /* transmit command */ +#define TxCB_CMD_SF 0x0008 /* 0=simplified, 1=flexible mode */ +#define TxCB_CMD_NC 0x0010 /* 0=CRC insert by controller */ +#define TxCB_CMD_I 0x2000 /* generate interrupt on completion */ +#define TxCB_CMD_S 0x4000 /* suspend on completion */ +#define TxCB_CMD_EL 0x8000 /* last command block in CBL */ + +#define TxCB_COUNT_MASK 0x3fff +#define TxCB_COUNT_EOF 0x8000 + + /* The Speedo3 Rx and Tx frame/buffer descriptors. + */ +struct descriptor { /* A generic descriptor. */ + volatile u16 status; + volatile u16 command; + volatile u32 link; /* struct descriptor * */ + + unsigned char params[0]; +}; + +#define CONFIG_SYS_CMD_EL 0x8000 +#define CONFIG_SYS_CMD_SUSPEND 0x4000 +#define CONFIG_SYS_CMD_INT 0x2000 +#define CONFIG_SYS_CMD_IAS 0x0001 /* individual address setup */ +#define CONFIG_SYS_CMD_CONFIGURE 0x0002 /* configure */ + +#define CONFIG_SYS_STATUS_C 0x8000 +#define CONFIG_SYS_STATUS_OK 0x2000 + + /* Misc. + */ +#define NUM_RX_DESC PKTBUFSRX +#define NUM_TX_DESC 1 /* Number of TX descriptors */ + +#define TOUT_LOOP 1000000 + +#define ETH_ALEN 6 + +static struct RxFD rx_ring[NUM_RX_DESC]; /* RX descriptor ring */ +static struct TxFD tx_ring[NUM_TX_DESC]; /* TX descriptor ring */ +static int rx_next; /* RX descriptor ring pointer */ +static int tx_next; /* TX descriptor ring pointer */ +static int tx_threshold; + +/* + * The parameters for a CmdConfigure operation. + * There are so many options that it would be difficult to document + * each bit. We mostly use the default or recommended settings. + */ +static const char i82557_config_cmd[] = { + 22, 0x08, 0, 0, 0, 0, 0x32, 0x03, 1, /* 1=Use MII 0=Use AUI */ + 0, 0x2E, 0, 0x60, 0, + 0xf2, 0x48, 0, 0x40, 0xf2, 0x80, /* 0x40=Force full-duplex */ + 0x3f, 0x05, +}; +static const char i82558_config_cmd[] = { + 22, 0x08, 0, 1, 0, 0, 0x22, 0x03, 1, /* 1=Use MII 0=Use AUI */ + 0, 0x2E, 0, 0x60, 0x08, 0x88, + 0x68, 0, 0x40, 0xf2, 0x84, /* Disable FC */ + 0x31, 0x05, +}; + +static void init_rx_ring (struct eth_device *dev); +static void purge_tx_ring (struct eth_device *dev); + +static void read_hw_addr (struct eth_device *dev, bd_t * bis); + +static int eepro100_init (struct eth_device *dev, bd_t * bis); +static int eepro100_send(struct eth_device *dev, void *packet, int length); +static int eepro100_recv (struct eth_device *dev); +static void eepro100_halt (struct eth_device *dev); + +#if defined(CONFIG_E500) +#define bus_to_phys(a) (a) +#define phys_to_bus(a) (a) +#else +#define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a) +#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a) +#endif + +static inline int INW (struct eth_device *dev, u_long addr) +{ + return le16_to_cpu (*(volatile u16 *) (addr + dev->iobase)); +} + +static inline void OUTW (struct eth_device *dev, int command, u_long addr) +{ + *(volatile u16 *) ((addr + dev->iobase)) = cpu_to_le16 (command); +} + +static inline void OUTL (struct eth_device *dev, int command, u_long addr) +{ + *(volatile u32 *) ((addr + dev->iobase)) = cpu_to_le32 (command); +} + +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) +static inline int INL (struct eth_device *dev, u_long addr) +{ + return le32_to_cpu (*(volatile u32 *) (addr + dev->iobase)); +} + +static int get_phyreg (struct eth_device *dev, unsigned char addr, + unsigned char reg, unsigned short *value) +{ + int cmd; + int timeout = 50; + + /* read requested data */ + cmd = (2 << 26) | ((addr & 0x1f) << 21) | ((reg & 0x1f) << 16); + OUTL (dev, cmd, SCBCtrlMDI); + + do { + udelay(1000); + cmd = INL (dev, SCBCtrlMDI); + } while (!(cmd & (1 << 28)) && (--timeout)); + + if (timeout == 0) + return -1; + + *value = (unsigned short) (cmd & 0xffff); + + return 0; +} + +static int set_phyreg (struct eth_device *dev, unsigned char addr, + unsigned char reg, unsigned short value) +{ + int cmd; + int timeout = 50; + + /* write requested data */ + cmd = (1 << 26) | ((addr & 0x1f) << 21) | ((reg & 0x1f) << 16); + OUTL (dev, cmd | value, SCBCtrlMDI); + + while (!(INL (dev, SCBCtrlMDI) & (1 << 28)) && (--timeout)) + udelay(1000); + + if (timeout == 0) + return -1; + + return 0; +} + +/* Check if given phyaddr is valid, i.e. there is a PHY connected. + * Do this by checking model value field from ID2 register. + */ +static struct eth_device* verify_phyaddr (const char *devname, + unsigned char addr) +{ + struct eth_device *dev; + unsigned short value; + unsigned char model; + + dev = eth_get_dev_by_name(devname); + if (dev == NULL) { + printf("%s: no such device\n", devname); + return NULL; + } + + /* read id2 register */ + if (get_phyreg(dev, addr, MII_PHYSID2, &value) != 0) { + printf("%s: mii read timeout!\n", devname); + return NULL; + } + + /* get model */ + model = (unsigned char)((value >> 4) & 0x003f); + + if (model == 0) { + printf("%s: no PHY at address %d\n", devname, addr); + return NULL; + } + + return dev; +} + +static int eepro100_miiphy_read(const char *devname, unsigned char addr, + unsigned char reg, unsigned short *value) +{ + struct eth_device *dev; + + dev = verify_phyaddr(devname, addr); + if (dev == NULL) + return -1; + + if (get_phyreg(dev, addr, reg, value) != 0) { + printf("%s: mii read timeout!\n", devname); + return -1; + } + + return 0; +} + +static int eepro100_miiphy_write(const char *devname, unsigned char addr, + unsigned char reg, unsigned short value) +{ + struct eth_device *dev; + + dev = verify_phyaddr(devname, addr); + if (dev == NULL) + return -1; + + if (set_phyreg(dev, addr, reg, value) != 0) { + printf("%s: mii write timeout!\n", devname); + return -1; + } + + return 0; +} + +#endif + +/* Wait for the chip get the command. +*/ +static int wait_for_eepro100 (struct eth_device *dev) +{ + int i; + + for (i = 0; INW (dev, SCBCmd) & (CU_CMD_MASK | RU_CMD_MASK); i++) { + if (i >= TOUT_LOOP) { + return 0; + } + } + + return 1; +} + +static struct pci_device_id supported[] = { + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82557}, + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82559}, + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82559ER}, + {} +}; + +int eepro100_initialize (bd_t * bis) +{ + pci_dev_t devno; + int card_number = 0; + struct eth_device *dev; + u32 iobase, status; + int idx = 0; + + while (1) { + /* Find PCI device + */ + if ((devno = pci_find_devices (supported, idx++)) < 0) { + break; + } + + pci_read_config_dword (devno, PCI_BASE_ADDRESS_0, &iobase); + iobase &= ~0xf; + +#ifdef DEBUG + printf ("eepro100: Intel i82559 PCI EtherExpressPro @0x%x\n", + iobase); +#endif + + pci_write_config_dword (devno, + PCI_COMMAND, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + + /* Check if I/O accesses and Bus Mastering are enabled. + */ + pci_read_config_dword (devno, PCI_COMMAND, &status); + if (!(status & PCI_COMMAND_MEMORY)) { + printf ("Error: Can not enable MEM access.\n"); + continue; + } + + if (!(status & PCI_COMMAND_MASTER)) { + printf ("Error: Can not enable Bus Mastering.\n"); + continue; + } + + dev = (struct eth_device *) malloc (sizeof *dev); + if (!dev) { + printf("eepro100: Can not allocate memory\n"); + break; + } + memset(dev, 0, sizeof(*dev)); + + sprintf (dev->name, "i82559#%d", card_number); + dev->priv = (void *) devno; /* this have to come before bus_to_phys() */ + dev->iobase = bus_to_phys (iobase); + dev->init = eepro100_init; + dev->halt = eepro100_halt; + dev->send = eepro100_send; + dev->recv = eepro100_recv; + + eth_register (dev); + +#if defined (CONFIG_MII) || defined(CONFIG_CMD_MII) + /* register mii command access routines */ + miiphy_register(dev->name, + eepro100_miiphy_read, eepro100_miiphy_write); +#endif + + card_number++; + + /* Set the latency timer for value. + */ + pci_write_config_byte (devno, PCI_LATENCY_TIMER, 0x20); + + udelay (10 * 1000); + + read_hw_addr (dev, bis); + } + + return card_number; +} + + +static int eepro100_init (struct eth_device *dev, bd_t * bis) +{ + int i, status = -1; + int tx_cur; + struct descriptor *ias_cmd, *cfg_cmd; + + /* Reset the ethernet controller + */ + OUTL (dev, I82559_SELECTIVE_RESET, SCBPort); + udelay (20); + + OUTL (dev, I82559_RESET, SCBPort); + udelay (20); + + if (!wait_for_eepro100 (dev)) { + printf ("Error: Can not reset ethernet controller.\n"); + goto Done; + } + OUTL (dev, 0, SCBPointer); + OUTW (dev, SCB_M | RUC_ADDR_LOAD, SCBCmd); + + if (!wait_for_eepro100 (dev)) { + printf ("Error: Can not reset ethernet controller.\n"); + goto Done; + } + OUTL (dev, 0, SCBPointer); + OUTW (dev, SCB_M | CU_ADDR_LOAD, SCBCmd); + + /* Initialize Rx and Tx rings. + */ + init_rx_ring (dev); + purge_tx_ring (dev); + + /* Tell the adapter where the RX ring is located. + */ + if (!wait_for_eepro100 (dev)) { + printf ("Error: Can not reset ethernet controller.\n"); + goto Done; + } + + OUTL (dev, phys_to_bus ((u32) & rx_ring[rx_next]), SCBPointer); + OUTW (dev, SCB_M | RUC_START, SCBCmd); + + /* Send the Configure frame */ + tx_cur = tx_next; + tx_next = ((tx_next + 1) % NUM_TX_DESC); + + cfg_cmd = (struct descriptor *) &tx_ring[tx_cur]; + cfg_cmd->command = cpu_to_le16 ((CONFIG_SYS_CMD_SUSPEND | CONFIG_SYS_CMD_CONFIGURE)); + cfg_cmd->status = 0; + cfg_cmd->link = cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next])); + + memcpy (cfg_cmd->params, i82558_config_cmd, + sizeof (i82558_config_cmd)); + + if (!wait_for_eepro100 (dev)) { + printf ("Error---CONFIG_SYS_CMD_CONFIGURE: Can not reset ethernet controller.\n"); + goto Done; + } + + OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer); + OUTW (dev, SCB_M | CU_START, SCBCmd); + + for (i = 0; + !(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_C); + i++) { + if (i >= TOUT_LOOP) { + printf ("%s: Tx error buffer not ready\n", dev->name); + goto Done; + } + } + + if (!(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_OK)) { + printf ("TX error status = 0x%08X\n", + le16_to_cpu (tx_ring[tx_cur].status)); + goto Done; + } + + /* Send the Individual Address Setup frame + */ + tx_cur = tx_next; + tx_next = ((tx_next + 1) % NUM_TX_DESC); + + ias_cmd = (struct descriptor *) &tx_ring[tx_cur]; + ias_cmd->command = cpu_to_le16 ((CONFIG_SYS_CMD_SUSPEND | CONFIG_SYS_CMD_IAS)); + ias_cmd->status = 0; + ias_cmd->link = cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next])); + + memcpy (ias_cmd->params, dev->enetaddr, 6); + + /* Tell the adapter where the TX ring is located. + */ + if (!wait_for_eepro100 (dev)) { + printf ("Error: Can not reset ethernet controller.\n"); + goto Done; + } + + OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer); + OUTW (dev, SCB_M | CU_START, SCBCmd); + + for (i = 0; !(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_C); + i++) { + if (i >= TOUT_LOOP) { + printf ("%s: Tx error buffer not ready\n", + dev->name); + goto Done; + } + } + + if (!(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_OK)) { + printf ("TX error status = 0x%08X\n", + le16_to_cpu (tx_ring[tx_cur].status)); + goto Done; + } + + status = 0; + + Done: + return status; +} + +static int eepro100_send(struct eth_device *dev, void *packet, int length) +{ + int i, status = -1; + int tx_cur; + + if (length <= 0) { + printf ("%s: bad packet size: %d\n", dev->name, length); + goto Done; + } + + tx_cur = tx_next; + tx_next = (tx_next + 1) % NUM_TX_DESC; + + tx_ring[tx_cur].command = cpu_to_le16 ( TxCB_CMD_TRANSMIT | + TxCB_CMD_SF | + TxCB_CMD_S | + TxCB_CMD_EL ); + tx_ring[tx_cur].status = 0; + tx_ring[tx_cur].count = cpu_to_le32 (tx_threshold); + tx_ring[tx_cur].link = + cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next])); + tx_ring[tx_cur].tx_desc_addr = + cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_cur].tx_buf_addr0)); + tx_ring[tx_cur].tx_buf_addr0 = + cpu_to_le32 (phys_to_bus ((u_long) packet)); + tx_ring[tx_cur].tx_buf_size0 = cpu_to_le32 (length); + + if (!wait_for_eepro100 (dev)) { + printf ("%s: Tx error ethernet controller not ready.\n", + dev->name); + goto Done; + } + + /* Send the packet. + */ + OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer); + OUTW (dev, SCB_M | CU_START, SCBCmd); + + for (i = 0; !(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_C); + i++) { + if (i >= TOUT_LOOP) { + printf ("%s: Tx error buffer not ready\n", dev->name); + goto Done; + } + } + + if (!(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_OK)) { + printf ("TX error status = 0x%08X\n", + le16_to_cpu (tx_ring[tx_cur].status)); + goto Done; + } + + status = length; + + Done: + return status; +} + +static int eepro100_recv (struct eth_device *dev) +{ + u16 status, stat; + int rx_prev, length = 0; + + stat = INW (dev, SCBStatus); + OUTW (dev, stat & SCB_STATUS_RNR, SCBStatus); + + for (;;) { + status = le16_to_cpu (rx_ring[rx_next].status); + + if (!(status & RFD_STATUS_C)) { + break; + } + + /* Valid frame status. + */ + if ((status & RFD_STATUS_OK)) { + /* A valid frame received. + */ + length = le32_to_cpu (rx_ring[rx_next].count) & 0x3fff; + + /* Pass the packet up to the protocol + * layers. + */ + net_process_received_packet((u8 *)rx_ring[rx_next].data, + length); + } else { + /* There was an error. + */ + printf ("RX error status = 0x%08X\n", status); + } + + rx_ring[rx_next].control = cpu_to_le16 (RFD_CONTROL_S); + rx_ring[rx_next].status = 0; + rx_ring[rx_next].count = cpu_to_le32 (PKTSIZE_ALIGN << 16); + + rx_prev = (rx_next + NUM_RX_DESC - 1) % NUM_RX_DESC; + rx_ring[rx_prev].control = 0; + + /* Update entry information. + */ + rx_next = (rx_next + 1) % NUM_RX_DESC; + } + + if (stat & SCB_STATUS_RNR) { + + printf ("%s: Receiver is not ready, restart it !\n", dev->name); + + /* Reinitialize Rx ring. + */ + init_rx_ring (dev); + + if (!wait_for_eepro100 (dev)) { + printf ("Error: Can not restart ethernet controller.\n"); + goto Done; + } + + OUTL (dev, phys_to_bus ((u32) & rx_ring[rx_next]), SCBPointer); + OUTW (dev, SCB_M | RUC_START, SCBCmd); + } + + Done: + return length; +} + +static void eepro100_halt (struct eth_device *dev) +{ + /* Reset the ethernet controller + */ + OUTL (dev, I82559_SELECTIVE_RESET, SCBPort); + udelay (20); + + OUTL (dev, I82559_RESET, SCBPort); + udelay (20); + + if (!wait_for_eepro100 (dev)) { + printf ("Error: Can not reset ethernet controller.\n"); + goto Done; + } + OUTL (dev, 0, SCBPointer); + OUTW (dev, SCB_M | RUC_ADDR_LOAD, SCBCmd); + + if (!wait_for_eepro100 (dev)) { + printf ("Error: Can not reset ethernet controller.\n"); + goto Done; + } + OUTL (dev, 0, SCBPointer); + OUTW (dev, SCB_M | CU_ADDR_LOAD, SCBCmd); + + Done: + return; +} + + /* SROM Read. + */ +static int read_eeprom (struct eth_device *dev, int location, int addr_len) +{ + unsigned short retval = 0; + int read_cmd = location | EE_READ_CMD; + int i; + + OUTW (dev, EE_ENB & ~EE_CS, SCBeeprom); + OUTW (dev, EE_ENB, SCBeeprom); + + /* Shift the read command bits out. */ + for (i = 12; i >= 0; i--) { + short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0; + + OUTW (dev, EE_ENB | dataval, SCBeeprom); + udelay (1); + OUTW (dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom); + udelay (1); + } + OUTW (dev, EE_ENB, SCBeeprom); + + for (i = 15; i >= 0; i--) { + OUTW (dev, EE_ENB | EE_SHIFT_CLK, SCBeeprom); + udelay (1); + retval = (retval << 1) | + ((INW (dev, SCBeeprom) & EE_DATA_READ) ? 1 : 0); + OUTW (dev, EE_ENB, SCBeeprom); + udelay (1); + } + + /* Terminate the EEPROM access. */ + OUTW (dev, EE_ENB & ~EE_CS, SCBeeprom); + return retval; +} + +#ifdef CONFIG_EEPRO100_SROM_WRITE +int eepro100_write_eeprom (struct eth_device* dev, int location, int addr_len, unsigned short data) +{ + unsigned short dataval; + int enable_cmd = 0x3f | EE_EWENB_CMD; + int write_cmd = location | EE_WRITE_CMD; + int i; + unsigned long datalong, tmplong; + + OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom); + udelay(1); + OUTW(dev, EE_ENB, SCBeeprom); + + /* Shift the enable command bits out. */ + for (i = (addr_len+EE_CMD_BITS-1); i >= 0; i--) + { + dataval = (enable_cmd & (1 << i)) ? EE_DATA_WRITE : 0; + OUTW(dev, EE_ENB | dataval, SCBeeprom); + udelay(1); + OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom); + udelay(1); + } + + OUTW(dev, EE_ENB, SCBeeprom); + udelay(1); + OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom); + udelay(1); + OUTW(dev, EE_ENB, SCBeeprom); + + + /* Shift the write command bits out. */ + for (i = (addr_len+EE_CMD_BITS-1); i >= 0; i--) + { + dataval = (write_cmd & (1 << i)) ? EE_DATA_WRITE : 0; + OUTW(dev, EE_ENB | dataval, SCBeeprom); + udelay(1); + OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom); + udelay(1); + } + + /* Write the data */ + datalong= (unsigned long) ((((data) & 0x00ff) << 8) | ( (data) >> 8)); + + for (i = 0; i< EE_DATA_BITS; i++) + { + /* Extract and move data bit to bit DI */ + dataval = ((datalong & 0x8000)>>13) ? EE_DATA_WRITE : 0; + + OUTW(dev, EE_ENB | dataval, SCBeeprom); + udelay(1); + OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom); + udelay(1); + OUTW(dev, EE_ENB | dataval, SCBeeprom); + udelay(1); + + datalong = datalong << 1; /* Adjust significant data bit*/ + } + + /* Finish up command (toggle CS) */ + OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom); + udelay(1); /* delay for more than 250 ns */ + OUTW(dev, EE_ENB, SCBeeprom); + + /* Wait for programming ready (D0 = 1) */ + tmplong = 10; + do + { + dataval = INW(dev, SCBeeprom); + if (dataval & EE_DATA_READ) + break; + udelay(10000); + } + while (-- tmplong); + + if (tmplong == 0) + { + printf ("Write i82559 eeprom timed out (100 ms waiting for data ready.\n"); + return -1; + } + + /* Terminate the EEPROM access. */ + OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom); + + return 0; +} +#endif + +static void init_rx_ring (struct eth_device *dev) +{ + int i; + + for (i = 0; i < NUM_RX_DESC; i++) { + rx_ring[i].status = 0; + rx_ring[i].control = + (i == NUM_RX_DESC - 1) ? cpu_to_le16 (RFD_CONTROL_S) : 0; + rx_ring[i].link = + cpu_to_le32 (phys_to_bus + ((u32) & rx_ring[(i + 1) % NUM_RX_DESC])); + rx_ring[i].rx_buf_addr = 0xffffffff; + rx_ring[i].count = cpu_to_le32 (PKTSIZE_ALIGN << 16); + } + + rx_next = 0; +} + +static void purge_tx_ring (struct eth_device *dev) +{ + int i; + + tx_next = 0; + tx_threshold = 0x01208000; + + for (i = 0; i < NUM_TX_DESC; i++) { + tx_ring[i].status = 0; + tx_ring[i].command = 0; + tx_ring[i].link = 0; + tx_ring[i].tx_desc_addr = 0; + tx_ring[i].count = 0; + + tx_ring[i].tx_buf_addr0 = 0; + tx_ring[i].tx_buf_size0 = 0; + tx_ring[i].tx_buf_addr1 = 0; + tx_ring[i].tx_buf_size1 = 0; + } +} + +static void read_hw_addr (struct eth_device *dev, bd_t * bis) +{ + u16 sum = 0; + int i, j; + int addr_len = read_eeprom (dev, 0, 6) == 0xffff ? 8 : 6; + + for (j = 0, i = 0; i < 0x40; i++) { + u16 value = read_eeprom (dev, i, addr_len); + + sum += value; + if (i < 3) { + dev->enetaddr[j++] = value; + dev->enetaddr[j++] = value >> 8; + } + } + + if (sum != 0xBABA) { + memset (dev->enetaddr, 0, ETH_ALEN); +#ifdef DEBUG + printf ("%s: Invalid EEPROM checksum %#4.4x, " + "check settings before activating this device!\n", + dev->name, sum); +#endif + } +} diff --git a/sources/uboot-be550/drivers/net/enc28j60.c b/sources/uboot-be550/drivers/net/enc28j60.c new file mode 100644 index 00000000..59ea11cd --- /dev/null +++ b/sources/uboot-be550/drivers/net/enc28j60.c @@ -0,0 +1,964 @@ +/* + * (C) Copyright 2010 + * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de + * Martin Krause, Martin.Krause@tqs.de + * reworked original enc28j60.c + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include "enc28j60.h" + +/* + * IMPORTANT: spi_claim_bus() and spi_release_bus() + * are called at begin and end of each of the following functions: + * enc_miiphy_read(), enc_miiphy_write(), enc_write_hwaddr(), + * enc_init(), enc_recv(), enc_send(), enc_halt() + * ALL other functions assume that the bus has already been claimed! + * Since net_process_received_packet() might call enc_send() in return, the bus + * must be released, net_process_received_packet() called and claimed again. + */ + +/* + * Controller memory layout. + * We only allow 1 frame for transmission and reserve the rest + * for reception to handle as many broadcast packets as possible. + * Also use the memory from 0x0000 for receiver buffer. See errata pt. 5 + * 0x0000 - 0x19ff 6656 bytes receive buffer + * 0x1a00 - 0x1fff 1536 bytes transmit buffer = + * control(1)+frame(1518)+status(7)+reserve(10). + */ +#define ENC_RX_BUF_START 0x0000 +#define ENC_RX_BUF_END 0x19ff +#define ENC_TX_BUF_START 0x1a00 +#define ENC_TX_BUF_END 0x1fff +#define ENC_MAX_FRM_LEN 1518 +#define RX_RESET_COUNTER 1000 + +/* + * For non data transfer functions, like phy read/write, set hwaddr, init + * we do not need a full, time consuming init including link ready wait. + * This enum helps to bring the chip through the minimum necessary inits. + */ +enum enc_initstate {none=0, setupdone, linkready}; +typedef struct enc_device { + struct eth_device *dev; /* back pointer */ + struct spi_slave *slave; + int rx_reset_counter; + u16 next_pointer; + u8 bank; /* current bank in enc28j60 */ + enum enc_initstate initstate; +} enc_dev_t; + +/* + * enc_bset: set bits in a common register + * enc_bclr: clear bits in a common register + * + * making the reg parameter u8 will give a compile time warning if the + * functions are called with a register not accessible in all Banks + */ +static void enc_bset(enc_dev_t *enc, const u8 reg, const u8 data) +{ + u8 dout[2]; + + dout[0] = CMD_BFS(reg); + dout[1] = data; + spi_xfer(enc->slave, 2 * 8, dout, NULL, + SPI_XFER_BEGIN | SPI_XFER_END); +} + +static void enc_bclr(enc_dev_t *enc, const u8 reg, const u8 data) +{ + u8 dout[2]; + + dout[0] = CMD_BFC(reg); + dout[1] = data; + spi_xfer(enc->slave, 2 * 8, dout, NULL, + SPI_XFER_BEGIN | SPI_XFER_END); +} + +/* + * high byte of the register contains bank number: + * 0: no bank switch necessary + * 1: switch to bank 0 + * 2: switch to bank 1 + * 3: switch to bank 2 + * 4: switch to bank 3 + */ +static void enc_set_bank(enc_dev_t *enc, const u16 reg) +{ + u8 newbank = reg >> 8; + + if (newbank == 0 || newbank == enc->bank) + return; + switch (newbank) { + case 1: + enc_bclr(enc, CTL_REG_ECON1, + ENC_ECON1_BSEL0 | ENC_ECON1_BSEL1); + break; + case 2: + enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_BSEL0); + enc_bclr(enc, CTL_REG_ECON1, ENC_ECON1_BSEL1); + break; + case 3: + enc_bclr(enc, CTL_REG_ECON1, ENC_ECON1_BSEL0); + enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_BSEL1); + break; + case 4: + enc_bset(enc, CTL_REG_ECON1, + ENC_ECON1_BSEL0 | ENC_ECON1_BSEL1); + break; + } + enc->bank = newbank; +} + +/* + * local functions to access SPI + * + * reg: register inside ENC28J60 + * data: 8/16 bits to write + * c: number of retries + * + * enc_r8: read 8 bits + * enc_r16: read 16 bits + * enc_w8: write 8 bits + * enc_w16: write 16 bits + * enc_w8_retry: write 8 bits, verify and retry + * enc_rbuf: read from ENC28J60 into buffer + * enc_wbuf: write from buffer into ENC28J60 + */ + +/* + * MAC and MII registers need a 3 byte SPI transfer to read, + * all other registers need a 2 byte SPI transfer. + */ +static int enc_reg2nbytes(const u16 reg) +{ + /* check if MAC or MII register */ + return ((reg >= CTL_REG_MACON1 && reg <= CTL_REG_MIRDH) || + (reg >= CTL_REG_MAADR1 && reg <= CTL_REG_MAADR4) || + (reg == CTL_REG_MISTAT)) ? 3 : 2; +} + +/* + * Read a byte register + */ +static u8 enc_r8(enc_dev_t *enc, const u16 reg) +{ + u8 dout[3]; + u8 din[3]; + int nbytes = enc_reg2nbytes(reg); + + enc_set_bank(enc, reg); + dout[0] = CMD_RCR(reg); + spi_xfer(enc->slave, nbytes * 8, dout, din, + SPI_XFER_BEGIN | SPI_XFER_END); + return din[nbytes-1]; +} + +/* + * Read a L/H register pair and return a word. + * Must be called with the L register's address. + */ +static u16 enc_r16(enc_dev_t *enc, const u16 reg) +{ + u8 dout[3]; + u8 din[3]; + u16 result; + int nbytes = enc_reg2nbytes(reg); + + enc_set_bank(enc, reg); + dout[0] = CMD_RCR(reg); + spi_xfer(enc->slave, nbytes * 8, dout, din, + SPI_XFER_BEGIN | SPI_XFER_END); + result = din[nbytes-1]; + dout[0]++; /* next register */ + spi_xfer(enc->slave, nbytes * 8, dout, din, + SPI_XFER_BEGIN | SPI_XFER_END); + result |= din[nbytes-1] << 8; + return result; +} + +/* + * Write a byte register + */ +static void enc_w8(enc_dev_t *enc, const u16 reg, const u8 data) +{ + u8 dout[2]; + + enc_set_bank(enc, reg); + dout[0] = CMD_WCR(reg); + dout[1] = data; + spi_xfer(enc->slave, 2 * 8, dout, NULL, + SPI_XFER_BEGIN | SPI_XFER_END); +} + +/* + * Write a L/H register pair. + * Must be called with the L register's address. + */ +static void enc_w16(enc_dev_t *enc, const u16 reg, const u16 data) +{ + u8 dout[2]; + + enc_set_bank(enc, reg); + dout[0] = CMD_WCR(reg); + dout[1] = data; + spi_xfer(enc->slave, 2 * 8, dout, NULL, + SPI_XFER_BEGIN | SPI_XFER_END); + dout[0]++; /* next register */ + dout[1] = data >> 8; + spi_xfer(enc->slave, 2 * 8, dout, NULL, + SPI_XFER_BEGIN | SPI_XFER_END); +} + +/* + * Write a byte register, verify and retry + */ +static void enc_w8_retry(enc_dev_t *enc, const u16 reg, const u8 data, const int c) +{ + u8 dout[2]; + u8 readback; + int i; + + enc_set_bank(enc, reg); + for (i = 0; i < c; i++) { + dout[0] = CMD_WCR(reg); + dout[1] = data; + spi_xfer(enc->slave, 2 * 8, dout, NULL, + SPI_XFER_BEGIN | SPI_XFER_END); + readback = enc_r8(enc, reg); + if (readback == data) + break; + /* wait 1ms */ + udelay(1000); + } + if (i == c) { + printf("%s: write reg 0x%03x failed\n", enc->dev->name, reg); + } +} + +/* + * Read ENC RAM into buffer + */ +static void enc_rbuf(enc_dev_t *enc, const u16 length, u8 *buf) +{ + u8 dout[1]; + + dout[0] = CMD_RBM; + spi_xfer(enc->slave, 8, dout, NULL, SPI_XFER_BEGIN); + spi_xfer(enc->slave, length * 8, NULL, buf, SPI_XFER_END); +#ifdef DEBUG + puts("Rx:\n"); + print_buffer(0, buf, 1, length, 0); +#endif +} + +/* + * Write buffer into ENC RAM + */ +static void enc_wbuf(enc_dev_t *enc, const u16 length, const u8 *buf, const u8 control) +{ + u8 dout[2]; + dout[0] = CMD_WBM; + dout[1] = control; + spi_xfer(enc->slave, 2 * 8, dout, NULL, SPI_XFER_BEGIN); + spi_xfer(enc->slave, length * 8, buf, NULL, SPI_XFER_END); +#ifdef DEBUG + puts("Tx:\n"); + print_buffer(0, buf, 1, length, 0); +#endif +} + +/* + * Try to claim the SPI bus. + * Print error message on failure. + */ +static int enc_claim_bus(enc_dev_t *enc) +{ + int rc = spi_claim_bus(enc->slave); + if (rc) + printf("%s: failed to claim SPI bus\n", enc->dev->name); + return rc; +} + +/* + * Release previously claimed SPI bus. + * This function is mainly for symmetry to enc_claim_bus(). + * Let the toolchain decide to inline it... + */ +static void enc_release_bus(enc_dev_t *enc) +{ + spi_release_bus(enc->slave); +} + +/* + * Read PHY register + */ +static u16 enc_phy_read(enc_dev_t *enc, const u8 addr) +{ + uint64_t etime; + u8 status; + + enc_w8(enc, CTL_REG_MIREGADR, addr); + enc_w8(enc, CTL_REG_MICMD, ENC_MICMD_MIIRD); + /* 1 second timeout - only happens on hardware problem */ + etime = get_ticks() + get_tbclk(); + /* poll MISTAT.BUSY bit until operation is complete */ + do + { + status = enc_r8(enc, CTL_REG_MISTAT); + } while (get_ticks() <= etime && (status & ENC_MISTAT_BUSY)); + if (status & ENC_MISTAT_BUSY) { + printf("%s: timeout reading phy\n", enc->dev->name); + return 0; + } + enc_w8(enc, CTL_REG_MICMD, 0); + return enc_r16(enc, CTL_REG_MIRDL); +} + +/* + * Write PHY register + */ +static void enc_phy_write(enc_dev_t *enc, const u8 addr, const u16 data) +{ + uint64_t etime; + u8 status; + + enc_w8(enc, CTL_REG_MIREGADR, addr); + enc_w16(enc, CTL_REG_MIWRL, data); + /* 1 second timeout - only happens on hardware problem */ + etime = get_ticks() + get_tbclk(); + /* poll MISTAT.BUSY bit until operation is complete */ + do + { + status = enc_r8(enc, CTL_REG_MISTAT); + } while (get_ticks() <= etime && (status & ENC_MISTAT_BUSY)); + if (status & ENC_MISTAT_BUSY) { + printf("%s: timeout writing phy\n", enc->dev->name); + return; + } +} + +/* + * Verify link status, wait if necessary + * + * Note: with a 10 MBit/s only PHY there is no autonegotiation possible, + * half/full duplex is a pure setup matter. For the time being, this driver + * will setup in half duplex mode only. + */ +static int enc_phy_link_wait(enc_dev_t *enc) +{ + u16 status; + int duplex; + uint64_t etime; + +#ifdef CONFIG_ENC_SILENTLINK + /* check if we have a link, then just return */ + status = enc_phy_read(enc, PHY_REG_PHSTAT1); + if (status & ENC_PHSTAT1_LLSTAT) + return 0; +#endif + + /* wait for link with 1 second timeout */ + etime = get_ticks() + get_tbclk(); + while (get_ticks() <= etime) { + status = enc_phy_read(enc, PHY_REG_PHSTAT1); + if (status & ENC_PHSTAT1_LLSTAT) { + /* now we have a link */ + status = enc_phy_read(enc, PHY_REG_PHSTAT2); + duplex = (status & ENC_PHSTAT2_DPXSTAT) ? 1 : 0; + printf("%s: link up, 10Mbps %s-duplex\n", + enc->dev->name, duplex ? "full" : "half"); + return 0; + } + udelay(1000); + } + + /* timeout occured */ + printf("%s: link down\n", enc->dev->name); + return 1; +} + +/* + * This function resets the receiver only. + */ +static void enc_reset_rx(enc_dev_t *enc) +{ + u8 econ1; + + econ1 = enc_r8(enc, CTL_REG_ECON1); + if ((econ1 & ENC_ECON1_RXRST) == 0) { + enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_RXRST); + enc->rx_reset_counter = RX_RESET_COUNTER; + } +} + +/* + * Reset receiver and reenable it. + */ +static void enc_reset_rx_call(enc_dev_t *enc) +{ + enc_bclr(enc, CTL_REG_ECON1, ENC_ECON1_RXRST); + enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_RXEN); +} + +/* + * Copy a packet from the receive ring and forward it to + * the protocol stack. + */ +static void enc_receive(enc_dev_t *enc) +{ + u8 *packet = (u8 *)net_rx_packets[0]; + u16 pkt_len; + u16 copy_len; + u16 status; + u8 pkt_cnt = 0; + u16 rxbuf_rdpt; + u8 hbuf[6]; + + enc_w16(enc, CTL_REG_ERDPTL, enc->next_pointer); + do { + enc_rbuf(enc, 6, hbuf); + enc->next_pointer = hbuf[0] | (hbuf[1] << 8); + pkt_len = hbuf[2] | (hbuf[3] << 8); + status = hbuf[4] | (hbuf[5] << 8); + debug("next_pointer=$%04x pkt_len=%u status=$%04x\n", + enc->next_pointer, pkt_len, status); + if (pkt_len <= ENC_MAX_FRM_LEN) + copy_len = pkt_len; + else + copy_len = 0; + if ((status & (1L << 7)) == 0) /* check Received Ok bit */ + copy_len = 0; + /* check if next pointer is resonable */ + if (enc->next_pointer >= ENC_TX_BUF_START) + copy_len = 0; + if (copy_len > 0) { + enc_rbuf(enc, copy_len, packet); + } + /* advance read pointer to next pointer */ + enc_w16(enc, CTL_REG_ERDPTL, enc->next_pointer); + /* decrease packet counter */ + enc_bset(enc, CTL_REG_ECON2, ENC_ECON2_PKTDEC); + /* + * Only odd values should be written to ERXRDPTL, + * see errata B4 pt.13 + */ + rxbuf_rdpt = enc->next_pointer - 1; + if ((rxbuf_rdpt < enc_r16(enc, CTL_REG_ERXSTL)) || + (rxbuf_rdpt > enc_r16(enc, CTL_REG_ERXNDL))) { + enc_w16(enc, CTL_REG_ERXRDPTL, + enc_r16(enc, CTL_REG_ERXNDL)); + } else { + enc_w16(enc, CTL_REG_ERXRDPTL, rxbuf_rdpt); + } + /* read pktcnt */ + pkt_cnt = enc_r8(enc, CTL_REG_EPKTCNT); + if (copy_len == 0) { + (void)enc_r8(enc, CTL_REG_EIR); + enc_reset_rx(enc); + printf("%s: receive copy_len=0\n", enc->dev->name); + continue; + } + /* + * Because net_process_received_packet() might call enc_send(), + * we need to release the SPI bus, call + * net_process_received_packet(), reclaim the bus. + */ + enc_release_bus(enc); + net_process_received_packet(packet, pkt_len); + if (enc_claim_bus(enc)) + return; + (void)enc_r8(enc, CTL_REG_EIR); + } while (pkt_cnt); + /* Use EPKTCNT not EIR.PKTIF flag, see errata pt. 6 */ +} + +/* + * Poll for completely received packets. + */ +static void enc_poll(enc_dev_t *enc) +{ + u8 eir_reg; + u8 pkt_cnt; + +#ifdef CONFIG_USE_IRQ + /* clear global interrupt enable bit in enc28j60 */ + enc_bclr(enc, CTL_REG_EIE, ENC_EIE_INTIE); +#endif + (void)enc_r8(enc, CTL_REG_ESTAT); + eir_reg = enc_r8(enc, CTL_REG_EIR); + if (eir_reg & ENC_EIR_TXIF) { + /* clear TXIF bit in EIR */ + enc_bclr(enc, CTL_REG_EIR, ENC_EIR_TXIF); + } + /* We have to use pktcnt and not pktif bit, see errata pt. 6 */ + pkt_cnt = enc_r8(enc, CTL_REG_EPKTCNT); + if (pkt_cnt > 0) { + if ((eir_reg & ENC_EIR_PKTIF) == 0) { + debug("enc_poll: pkt cnt > 0, but pktif not set\n"); + } + enc_receive(enc); + /* + * clear PKTIF bit in EIR, this should not need to be done + * but it seems like we get problems if we do not + */ + enc_bclr(enc, CTL_REG_EIR, ENC_EIR_PKTIF); + } + if (eir_reg & ENC_EIR_RXERIF) { + printf("%s: rx error\n", enc->dev->name); + enc_bclr(enc, CTL_REG_EIR, ENC_EIR_RXERIF); + } + if (eir_reg & ENC_EIR_TXERIF) { + printf("%s: tx error\n", enc->dev->name); + enc_bclr(enc, CTL_REG_EIR, ENC_EIR_TXERIF); + } +#ifdef CONFIG_USE_IRQ + /* set global interrupt enable bit in enc28j60 */ + enc_bset(enc, CTL_REG_EIE, ENC_EIE_INTIE); +#endif +} + +/* + * Completely Reset the ENC + */ +static void enc_reset(enc_dev_t *enc) +{ + u8 dout[1]; + + dout[0] = CMD_SRC; + spi_xfer(enc->slave, 8, dout, NULL, + SPI_XFER_BEGIN | SPI_XFER_END); + /* sleep 1 ms. See errata pt. 2 */ + udelay(1000); +} + +/* + * Initialisation data for most of the ENC registers + */ +static const u16 enc_initdata[] = { + /* + * Setup the buffer space. The reset values are valid for the + * other pointers. + * + * We shall not write to ERXST, see errata pt. 5. Instead we + * have to make sure that ENC_RX_BUS_START is 0. + */ + CTL_REG_ERXSTL, ENC_RX_BUF_START, + CTL_REG_ERXSTH, ENC_RX_BUF_START >> 8, + CTL_REG_ERXNDL, ENC_RX_BUF_END, + CTL_REG_ERXNDH, ENC_RX_BUF_END >> 8, + CTL_REG_ERDPTL, ENC_RX_BUF_START, + CTL_REG_ERDPTH, ENC_RX_BUF_START >> 8, + /* + * Set the filter to receive only good-CRC, unicast and broadcast + * frames. + * Note: some DHCP servers return their answers as broadcasts! + * So its unwise to remove broadcast from this. This driver + * might incur receiver overruns with packet loss on a broadcast + * flooded network. + */ + CTL_REG_ERXFCON, ENC_RFR_BCEN | ENC_RFR_UCEN | ENC_RFR_CRCEN, + + /* enable MAC to receive frames */ + CTL_REG_MACON1, + ENC_MACON1_MARXEN | ENC_MACON1_TXPAUS | ENC_MACON1_RXPAUS, + + /* configure pad, tx-crc and duplex */ + CTL_REG_MACON3, + ENC_MACON3_PADCFG0 | ENC_MACON3_TXCRCEN | + ENC_MACON3_FRMLNEN, + + /* Allow infinite deferals if the medium is continously busy */ + CTL_REG_MACON4, ENC_MACON4_DEFER, + + /* Late collisions occur beyond 63 bytes */ + CTL_REG_MACLCON2, 63, + + /* + * Set (low byte) Non-Back-to_Back Inter-Packet Gap. + * Recommended 0x12 + */ + CTL_REG_MAIPGL, 0x12, + + /* + * Set (high byte) Non-Back-to_Back Inter-Packet Gap. + * Recommended 0x0c for half-duplex. Nothing for full-duplex + */ + CTL_REG_MAIPGH, 0x0C, + + /* set maximum frame length */ + CTL_REG_MAMXFLL, ENC_MAX_FRM_LEN, + CTL_REG_MAMXFLH, ENC_MAX_FRM_LEN >> 8, + + /* + * Set MAC back-to-back inter-packet gap. + * Recommended 0x12 for half duplex + * and 0x15 for full duplex. + */ + CTL_REG_MABBIPG, 0x12, + + /* end of table */ + 0xffff +}; + +/* + * Wait for the XTAL oscillator to become ready + */ +static int enc_clock_wait(enc_dev_t *enc) +{ + uint64_t etime; + + /* one second timeout */ + etime = get_ticks() + get_tbclk(); + + /* + * Wait for CLKRDY to become set (i.e., check that we can + * communicate with the ENC) + */ + do + { + if (enc_r8(enc, CTL_REG_ESTAT) & ENC_ESTAT_CLKRDY) + return 0; + } while (get_ticks() <= etime); + + printf("%s: timeout waiting for CLKRDY\n", enc->dev->name); + return -1; +} + +/* + * Write the MAC address into the ENC + */ +static int enc_write_macaddr(enc_dev_t *enc) +{ + unsigned char *p = enc->dev->enetaddr; + + enc_w8_retry(enc, CTL_REG_MAADR5, *p++, 5); + enc_w8_retry(enc, CTL_REG_MAADR4, *p++, 5); + enc_w8_retry(enc, CTL_REG_MAADR3, *p++, 5); + enc_w8_retry(enc, CTL_REG_MAADR2, *p++, 5); + enc_w8_retry(enc, CTL_REG_MAADR1, *p++, 5); + enc_w8_retry(enc, CTL_REG_MAADR0, *p, 5); + return 0; +} + +/* + * Setup most of the ENC registers + */ +static int enc_setup(enc_dev_t *enc) +{ + u16 phid1 = 0; + u16 phid2 = 0; + const u16 *tp; + + /* reset enc struct values */ + enc->next_pointer = ENC_RX_BUF_START; + enc->rx_reset_counter = RX_RESET_COUNTER; + enc->bank = 0xff; /* invalidate current bank in enc28j60 */ + + /* verify PHY identification */ + phid1 = enc_phy_read(enc, PHY_REG_PHID1); + phid2 = enc_phy_read(enc, PHY_REG_PHID2) & ENC_PHID2_MASK; + if (phid1 != ENC_PHID1_VALUE || phid2 != ENC_PHID2_VALUE) { + printf("%s: failed to identify PHY. Found %04x:%04x\n", + enc->dev->name, phid1, phid2); + return -1; + } + + /* now program registers */ + for (tp = enc_initdata; *tp != 0xffff; tp += 2) + enc_w8_retry(enc, tp[0], tp[1], 10); + + /* + * Prevent automatic loopback of data beeing transmitted by setting + * ENC_PHCON2_HDLDIS + */ + enc_phy_write(enc, PHY_REG_PHCON2, (1<<8)); + + /* + * LEDs configuration + * LEDA: LACFG = 0100 -> display link status + * LEDB: LBCFG = 0111 -> display TX & RX activity + * STRCH = 1 -> LED pulses + */ + enc_phy_write(enc, PHY_REG_PHLCON, 0x0472); + + /* Reset PDPXMD-bit => half duplex */ + enc_phy_write(enc, PHY_REG_PHCON1, 0); + +#ifdef CONFIG_USE_IRQ + /* enable interrupts */ + enc_bset(enc, CTL_REG_EIE, ENC_EIE_PKTIE); + enc_bset(enc, CTL_REG_EIE, ENC_EIE_TXIE); + enc_bset(enc, CTL_REG_EIE, ENC_EIE_RXERIE); + enc_bset(enc, CTL_REG_EIE, ENC_EIE_TXERIE); + enc_bset(enc, CTL_REG_EIE, ENC_EIE_INTIE); +#endif + + return 0; +} + +/* + * Check if ENC has been initialized. + * If not, try to initialize it. + * Remember initialized state in struct. + */ +static int enc_initcheck(enc_dev_t *enc, const enum enc_initstate requiredstate) +{ + if (enc->initstate >= requiredstate) + return 0; + + if (enc->initstate < setupdone) { + /* Initialize the ENC only */ + enc_reset(enc); + /* if any of functions fails, skip the rest and return an error */ + if (enc_clock_wait(enc) || enc_setup(enc) || enc_write_macaddr(enc)) { + return -1; + } + enc->initstate = setupdone; + } + /* if that's all we need, return here */ + if (enc->initstate >= requiredstate) + return 0; + + /* now wait for link ready condition */ + if (enc_phy_link_wait(enc)) { + return -1; + } + enc->initstate = linkready; + return 0; +} + +#if defined(CONFIG_CMD_MII) +/* + * Read a PHY register. + * + * This function is registered with miiphy_register(). + */ +int enc_miiphy_read(const char *devname, u8 phy_adr, u8 reg, u16 *value) +{ + struct eth_device *dev = eth_get_dev_by_name(devname); + enc_dev_t *enc; + + if (!dev || phy_adr != 0) + return -1; + + enc = dev->priv; + if (enc_claim_bus(enc)) + return -1; + if (enc_initcheck(enc, setupdone)) { + enc_release_bus(enc); + return -1; + } + *value = enc_phy_read(enc, reg); + enc_release_bus(enc); + return 0; +} + +/* + * Write a PHY register. + * + * This function is registered with miiphy_register(). + */ +int enc_miiphy_write(const char *devname, u8 phy_adr, u8 reg, u16 value) +{ + struct eth_device *dev = eth_get_dev_by_name(devname); + enc_dev_t *enc; + + if (!dev || phy_adr != 0) + return -1; + + enc = dev->priv; + if (enc_claim_bus(enc)) + return -1; + if (enc_initcheck(enc, setupdone)) { + enc_release_bus(enc); + return -1; + } + enc_phy_write(enc, reg, value); + enc_release_bus(enc); + return 0; +} +#endif + +/* + * Write hardware (MAC) address. + * + * This function entered into eth_device structure. + */ +static int enc_write_hwaddr(struct eth_device *dev) +{ + enc_dev_t *enc = dev->priv; + + if (enc_claim_bus(enc)) + return -1; + if (enc_initcheck(enc, setupdone)) { + enc_release_bus(enc); + return -1; + } + enc_release_bus(enc); + return 0; +} + +/* + * Initialize ENC28J60 for use. + * + * This function entered into eth_device structure. + */ +static int enc_init(struct eth_device *dev, bd_t *bis) +{ + enc_dev_t *enc = dev->priv; + + if (enc_claim_bus(enc)) + return -1; + if (enc_initcheck(enc, linkready)) { + enc_release_bus(enc); + return -1; + } + /* enable receive */ + enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_RXEN); + enc_release_bus(enc); + return 0; +} + +/* + * Check for received packets. + * + * This function entered into eth_device structure. + */ +static int enc_recv(struct eth_device *dev) +{ + enc_dev_t *enc = dev->priv; + + if (enc_claim_bus(enc)) + return -1; + if (enc_initcheck(enc, linkready)) { + enc_release_bus(enc); + return -1; + } + /* Check for dead receiver */ + if (enc->rx_reset_counter > 0) + enc->rx_reset_counter--; + else + enc_reset_rx_call(enc); + enc_poll(enc); + enc_release_bus(enc); + return 0; +} + +/* + * Send a packet. + * + * This function entered into eth_device structure. + * + * Should we wait here until we have a Link? Or shall we leave that to + * protocol retries? + */ +static int enc_send( + struct eth_device *dev, + void *packet, + int length) +{ + enc_dev_t *enc = dev->priv; + + if (enc_claim_bus(enc)) + return -1; + if (enc_initcheck(enc, linkready)) { + enc_release_bus(enc); + return -1; + } + /* setup transmit pointers */ + enc_w16(enc, CTL_REG_EWRPTL, ENC_TX_BUF_START); + enc_w16(enc, CTL_REG_ETXNDL, length + ENC_TX_BUF_START); + enc_w16(enc, CTL_REG_ETXSTL, ENC_TX_BUF_START); + /* write packet to ENC */ + enc_wbuf(enc, length, (u8 *) packet, 0x00); + /* + * Check that the internal transmit logic has not been altered + * by excessive collisions. Reset transmitter if so. + * See Errata B4 12 and 14. + */ + if (enc_r8(enc, CTL_REG_EIR) & ENC_EIR_TXERIF) { + enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_TXRST); + enc_bclr(enc, CTL_REG_ECON1, ENC_ECON1_TXRST); + } + enc_bclr(enc, CTL_REG_EIR, (ENC_EIR_TXERIF | ENC_EIR_TXIF)); + /* start transmitting */ + enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_TXRTS); + enc_release_bus(enc); + return 0; +} + +/* + * Finish use of ENC. + * + * This function entered into eth_device structure. + */ +static void enc_halt(struct eth_device *dev) +{ + enc_dev_t *enc = dev->priv; + + if (enc_claim_bus(enc)) + return; + /* Just disable receiver */ + enc_bclr(enc, CTL_REG_ECON1, ENC_ECON1_RXEN); + enc_release_bus(enc); +} + +/* + * This is the only exported function. + * + * It may be called several times with different bus:cs combinations. + */ +int enc28j60_initialize(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct eth_device *dev; + enc_dev_t *enc; + + /* try to allocate, check and clear eth_device object */ + dev = malloc(sizeof(*dev)); + if (!dev) { + return -1; + } + memset(dev, 0, sizeof(*dev)); + + /* try to allocate, check and clear enc_dev_t object */ + enc = malloc(sizeof(*enc)); + if (!enc) { + free(dev); + return -1; + } + memset(enc, 0, sizeof(*enc)); + + /* try to setup the SPI slave */ + enc->slave = spi_setup_slave(bus, cs, max_hz, mode); + if (!enc->slave) { + printf("enc28j60: invalid SPI device %i:%i\n", bus, cs); + free(enc); + free(dev); + return -1; + } + + enc->dev = dev; + /* now fill the eth_device object */ + dev->priv = enc; + dev->init = enc_init; + dev->halt = enc_halt; + dev->send = enc_send; + dev->recv = enc_recv; + dev->write_hwaddr = enc_write_hwaddr; + sprintf(dev->name, "enc%i.%i", bus, cs); + eth_register(dev); +#if defined(CONFIG_CMD_MII) + miiphy_register(dev->name, enc_miiphy_read, enc_miiphy_write); +#endif + return 0; +} diff --git a/sources/uboot-be550/drivers/net/enc28j60.h b/sources/uboot-be550/drivers/net/enc28j60.h new file mode 100644 index 00000000..289e4128 --- /dev/null +++ b/sources/uboot-be550/drivers/net/enc28j60.h @@ -0,0 +1,238 @@ +/* + * (X) extracted from enc28j60.c + * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _enc28j60_h +#define _enc28j60_h + +/* + * SPI Commands + * + * Bits 7-5: Command + * Bits 4-0: Register + */ +#define CMD_RCR(x) (0x00+((x)&0x1f)) /* Read Control Register */ +#define CMD_RBM 0x3a /* Read Buffer Memory */ +#define CMD_WCR(x) (0x40+((x)&0x1f)) /* Write Control Register */ +#define CMD_WBM 0x7a /* Write Buffer Memory */ +#define CMD_BFS(x) (0x80+((x)&0x1f)) /* Bit Field Set */ +#define CMD_BFC(x) (0xa0+((x)&0x1f)) /* Bit Field Clear */ +#define CMD_SRC 0xff /* System Reset Command */ + +/* NEW: encode (bank number+1) in upper byte */ + +/* Common Control Registers accessible in all Banks */ +#define CTL_REG_EIE 0x01B +#define CTL_REG_EIR 0x01C +#define CTL_REG_ESTAT 0x01D +#define CTL_REG_ECON2 0x01E +#define CTL_REG_ECON1 0x01F + +/* Control Registers accessible in Bank 0 */ +#define CTL_REG_ERDPTL 0x100 +#define CTL_REG_ERDPTH 0x101 +#define CTL_REG_EWRPTL 0x102 +#define CTL_REG_EWRPTH 0x103 +#define CTL_REG_ETXSTL 0x104 +#define CTL_REG_ETXSTH 0x105 +#define CTL_REG_ETXNDL 0x106 +#define CTL_REG_ETXNDH 0x107 +#define CTL_REG_ERXSTL 0x108 +#define CTL_REG_ERXSTH 0x109 +#define CTL_REG_ERXNDL 0x10A +#define CTL_REG_ERXNDH 0x10B +#define CTL_REG_ERXRDPTL 0x10C +#define CTL_REG_ERXRDPTH 0x10D +#define CTL_REG_ERXWRPTL 0x10E +#define CTL_REG_ERXWRPTH 0x10F +#define CTL_REG_EDMASTL 0x110 +#define CTL_REG_EDMASTH 0x111 +#define CTL_REG_EDMANDL 0x112 +#define CTL_REG_EDMANDH 0x113 +#define CTL_REG_EDMADSTL 0x114 +#define CTL_REG_EDMADSTH 0x115 +#define CTL_REG_EDMACSL 0x116 +#define CTL_REG_EDMACSH 0x117 + +/* Control Registers accessible in Bank 1 */ +#define CTL_REG_EHT0 0x200 +#define CTL_REG_EHT1 0x201 +#define CTL_REG_EHT2 0x202 +#define CTL_REG_EHT3 0x203 +#define CTL_REG_EHT4 0x204 +#define CTL_REG_EHT5 0x205 +#define CTL_REG_EHT6 0x206 +#define CTL_REG_EHT7 0x207 +#define CTL_REG_EPMM0 0x208 +#define CTL_REG_EPMM1 0x209 +#define CTL_REG_EPMM2 0x20A +#define CTL_REG_EPMM3 0x20B +#define CTL_REG_EPMM4 0x20C +#define CTL_REG_EPMM5 0x20D +#define CTL_REG_EPMM6 0x20E +#define CTL_REG_EPMM7 0x20F +#define CTL_REG_EPMCSL 0x210 +#define CTL_REG_EPMCSH 0x211 +#define CTL_REG_EPMOL 0x214 +#define CTL_REG_EPMOH 0x215 +#define CTL_REG_EWOLIE 0x216 +#define CTL_REG_EWOLIR 0x217 +#define CTL_REG_ERXFCON 0x218 +#define CTL_REG_EPKTCNT 0x219 + +/* Control Registers accessible in Bank 2 */ +#define CTL_REG_MACON1 0x300 +#define CTL_REG_MACON2 0x301 +#define CTL_REG_MACON3 0x302 +#define CTL_REG_MACON4 0x303 +#define CTL_REG_MABBIPG 0x304 +#define CTL_REG_MAIPGL 0x306 +#define CTL_REG_MAIPGH 0x307 +#define CTL_REG_MACLCON1 0x308 +#define CTL_REG_MACLCON2 0x309 +#define CTL_REG_MAMXFLL 0x30A +#define CTL_REG_MAMXFLH 0x30B +#define CTL_REG_MAPHSUP 0x30D +#define CTL_REG_MICON 0x311 +#define CTL_REG_MICMD 0x312 +#define CTL_REG_MIREGADR 0x314 +#define CTL_REG_MIWRL 0x316 +#define CTL_REG_MIWRH 0x317 +#define CTL_REG_MIRDL 0x318 +#define CTL_REG_MIRDH 0x319 + +/* Control Registers accessible in Bank 3 */ +#define CTL_REG_MAADR1 0x400 +#define CTL_REG_MAADR0 0x401 +#define CTL_REG_MAADR3 0x402 +#define CTL_REG_MAADR2 0x403 +#define CTL_REG_MAADR5 0x404 +#define CTL_REG_MAADR4 0x405 +#define CTL_REG_EBSTSD 0x406 +#define CTL_REG_EBSTCON 0x407 +#define CTL_REG_EBSTCSL 0x408 +#define CTL_REG_EBSTCSH 0x409 +#define CTL_REG_MISTAT 0x40A +#define CTL_REG_EREVID 0x412 +#define CTL_REG_ECOCON 0x415 +#define CTL_REG_EFLOCON 0x417 +#define CTL_REG_EPAUSL 0x418 +#define CTL_REG_EPAUSH 0x419 + +/* PHY Register */ +#define PHY_REG_PHCON1 0x00 +#define PHY_REG_PHSTAT1 0x01 +#define PHY_REG_PHID1 0x02 +#define PHY_REG_PHID2 0x03 +#define PHY_REG_PHCON2 0x10 +#define PHY_REG_PHSTAT2 0x11 +#define PHY_REG_PHLCON 0x14 + +/* Receive Filter Register (ERXFCON) bits */ +#define ENC_RFR_UCEN 0x80 +#define ENC_RFR_ANDOR 0x40 +#define ENC_RFR_CRCEN 0x20 +#define ENC_RFR_PMEN 0x10 +#define ENC_RFR_MPEN 0x08 +#define ENC_RFR_HTEN 0x04 +#define ENC_RFR_MCEN 0x02 +#define ENC_RFR_BCEN 0x01 + +/* ECON1 Register Bits */ +#define ENC_ECON1_TXRST 0x80 +#define ENC_ECON1_RXRST 0x40 +#define ENC_ECON1_DMAST 0x20 +#define ENC_ECON1_CSUMEN 0x10 +#define ENC_ECON1_TXRTS 0x08 +#define ENC_ECON1_RXEN 0x04 +#define ENC_ECON1_BSEL1 0x02 +#define ENC_ECON1_BSEL0 0x01 + +/* ECON2 Register Bits */ +#define ENC_ECON2_AUTOINC 0x80 +#define ENC_ECON2_PKTDEC 0x40 +#define ENC_ECON2_PWRSV 0x20 +#define ENC_ECON2_VRPS 0x08 + +/* EIR Register Bits */ +#define ENC_EIR_PKTIF 0x40 +#define ENC_EIR_DMAIF 0x20 +#define ENC_EIR_LINKIF 0x10 +#define ENC_EIR_TXIF 0x08 +#define ENC_EIR_WOLIF 0x04 +#define ENC_EIR_TXERIF 0x02 +#define ENC_EIR_RXERIF 0x01 + +/* ESTAT Register Bits */ +#define ENC_ESTAT_INT 0x80 +#define ENC_ESTAT_LATECOL 0x10 +#define ENC_ESTAT_RXBUSY 0x04 +#define ENC_ESTAT_TXABRT 0x02 +#define ENC_ESTAT_CLKRDY 0x01 + +/* EIE Register Bits */ +#define ENC_EIE_INTIE 0x80 +#define ENC_EIE_PKTIE 0x40 +#define ENC_EIE_DMAIE 0x20 +#define ENC_EIE_LINKIE 0x10 +#define ENC_EIE_TXIE 0x08 +#define ENC_EIE_WOLIE 0x04 +#define ENC_EIE_TXERIE 0x02 +#define ENC_EIE_RXERIE 0x01 + +/* MACON1 Register Bits */ +#define ENC_MACON1_LOOPBK 0x10 +#define ENC_MACON1_TXPAUS 0x08 +#define ENC_MACON1_RXPAUS 0x04 +#define ENC_MACON1_PASSALL 0x02 +#define ENC_MACON1_MARXEN 0x01 + +/* MACON2 Register Bits */ +#define ENC_MACON2_MARST 0x80 +#define ENC_MACON2_RNDRST 0x40 +#define ENC_MACON2_MARXRST 0x08 +#define ENC_MACON2_RFUNRST 0x04 +#define ENC_MACON2_MATXRST 0x02 +#define ENC_MACON2_TFUNRST 0x01 + +/* MACON3 Register Bits */ +#define ENC_MACON3_PADCFG2 0x80 +#define ENC_MACON3_PADCFG1 0x40 +#define ENC_MACON3_PADCFG0 0x20 +#define ENC_MACON3_TXCRCEN 0x10 +#define ENC_MACON3_PHDRLEN 0x08 +#define ENC_MACON3_HFRMEN 0x04 +#define ENC_MACON3_FRMLNEN 0x02 +#define ENC_MACON3_FULDPX 0x01 + +/* MACON4 Register Bits */ +#define ENC_MACON4_DEFER 0x40 + +/* MICMD Register Bits */ +#define ENC_MICMD_MIISCAN 0x02 +#define ENC_MICMD_MIIRD 0x01 + +/* MISTAT Register Bits */ +#define ENC_MISTAT_NVALID 0x04 +#define ENC_MISTAT_SCAN 0x02 +#define ENC_MISTAT_BUSY 0x01 + +/* PHID1 and PHID2 values */ +#define ENC_PHID1_VALUE 0x0083 +#define ENC_PHID2_VALUE 0x1400 +#define ENC_PHID2_MASK 0xFC00 + +/* PHCON1 values */ +#define ENC_PHCON1_PDPXMD 0x0100 + +/* PHSTAT1 values */ +#define ENC_PHSTAT1_LLSTAT 0x0004 + +/* PHSTAT2 values */ +#define ENC_PHSTAT2_LSTAT 0x0400 +#define ENC_PHSTAT2_DPXSTAT 0x0200 + +#endif diff --git a/sources/uboot-be550/drivers/net/ep93xx_eth.c b/sources/uboot-be550/drivers/net/ep93xx_eth.c new file mode 100644 index 00000000..a3721c55 --- /dev/null +++ b/sources/uboot-be550/drivers/net/ep93xx_eth.c @@ -0,0 +1,640 @@ +/* + * Cirrus Logic EP93xx ethernet MAC / MII driver. + * + * Copyright (C) 2010, 2009 + * Matthias Kaehlcke + * + * Copyright (C) 2004, 2005 + * Cory T. Tusar, Videon Central, Inc., + * + * Based on the original eth.[ch] Cirrus Logic EP93xx Rev D. Ethernet Driver, + * which is + * + * (C) Copyright 2002 2003 + * Adam Bezanson, Network Audio Technologies, Inc. + * + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include "ep93xx_eth.h" + +#define GET_PRIV(eth_dev) ((struct ep93xx_priv *)(eth_dev)->priv) +#define GET_REGS(eth_dev) (GET_PRIV(eth_dev)->regs) + +/* ep93xx_miiphy ops forward declarations */ +static int ep93xx_miiphy_read(const char * const dev, unsigned char const addr, + unsigned char const reg, unsigned short * const value); +static int ep93xx_miiphy_write(const char * const dev, unsigned char const addr, + unsigned char const reg, unsigned short const value); + +#if defined(EP93XX_MAC_DEBUG) +/** + * Dump ep93xx_mac values to the terminal. + */ +static void dump_dev(struct eth_device *dev) +{ + struct ep93xx_priv *priv = GET_PRIV(dev); + int i; + + printf("\ndump_dev()\n"); + printf(" rx_dq.base %p\n", priv->rx_dq.base); + printf(" rx_dq.current %p\n", priv->rx_dq.current); + printf(" rx_dq.end %p\n", priv->rx_dq.end); + printf(" rx_sq.base %p\n", priv->rx_sq.base); + printf(" rx_sq.current %p\n", priv->rx_sq.current); + printf(" rx_sq.end %p\n", priv->rx_sq.end); + + for (i = 0; i < NUMRXDESC; i++) + printf(" rx_buffer[%2.d] %p\n", i, net_rx_packets[i]); + + printf(" tx_dq.base %p\n", priv->tx_dq.base); + printf(" tx_dq.current %p\n", priv->tx_dq.current); + printf(" tx_dq.end %p\n", priv->tx_dq.end); + printf(" tx_sq.base %p\n", priv->tx_sq.base); + printf(" tx_sq.current %p\n", priv->tx_sq.current); + printf(" tx_sq.end %p\n", priv->tx_sq.end); +} + +/** + * Dump all RX status queue entries to the terminal. + */ +static void dump_rx_status_queue(struct eth_device *dev) +{ + struct ep93xx_priv *priv = GET_PRIV(dev); + int i; + + printf("\ndump_rx_status_queue()\n"); + printf(" descriptor address word1 word2\n"); + for (i = 0; i < NUMRXDESC; i++) { + printf(" [ %p ] %08X %08X\n", + priv->rx_sq.base + i, + (priv->rx_sq.base + i)->word1, + (priv->rx_sq.base + i)->word2); + } +} + +/** + * Dump all RX descriptor queue entries to the terminal. + */ +static void dump_rx_descriptor_queue(struct eth_device *dev) +{ + struct ep93xx_priv *priv = GET_PRIV(dev); + int i; + + printf("\ndump_rx_descriptor_queue()\n"); + printf(" descriptor address word1 word2\n"); + for (i = 0; i < NUMRXDESC; i++) { + printf(" [ %p ] %08X %08X\n", + priv->rx_dq.base + i, + (priv->rx_dq.base + i)->word1, + (priv->rx_dq.base + i)->word2); + } +} + +/** + * Dump all TX descriptor queue entries to the terminal. + */ +static void dump_tx_descriptor_queue(struct eth_device *dev) +{ + struct ep93xx_priv *priv = GET_PRIV(dev); + int i; + + printf("\ndump_tx_descriptor_queue()\n"); + printf(" descriptor address word1 word2\n"); + for (i = 0; i < NUMTXDESC; i++) { + printf(" [ %p ] %08X %08X\n", + priv->tx_dq.base + i, + (priv->tx_dq.base + i)->word1, + (priv->tx_dq.base + i)->word2); + } +} + +/** + * Dump all TX status queue entries to the terminal. + */ +static void dump_tx_status_queue(struct eth_device *dev) +{ + struct ep93xx_priv *priv = GET_PRIV(dev); + int i; + + printf("\ndump_tx_status_queue()\n"); + printf(" descriptor address word1\n"); + for (i = 0; i < NUMTXDESC; i++) { + printf(" [ %p ] %08X\n", + priv->rx_sq.base + i, + (priv->rx_sq.base + i)->word1); + } +} +#else +#define dump_dev(x) +#define dump_rx_descriptor_queue(x) +#define dump_rx_status_queue(x) +#define dump_tx_descriptor_queue(x) +#define dump_tx_status_queue(x) +#endif /* defined(EP93XX_MAC_DEBUG) */ + +/** + * Reset the EP93xx MAC by twiddling the soft reset bit and spinning until + * it's cleared. + */ +static void ep93xx_mac_reset(struct eth_device *dev) +{ + struct mac_regs *mac = GET_REGS(dev); + uint32_t value; + + debug("+ep93xx_mac_reset"); + + value = readl(&mac->selfctl); + value |= SELFCTL_RESET; + writel(value, &mac->selfctl); + + while (readl(&mac->selfctl) & SELFCTL_RESET) + ; /* noop */ + + debug("-ep93xx_mac_reset"); +} + +/* Eth device open */ +static int ep93xx_eth_open(struct eth_device *dev, bd_t *bd) +{ + struct ep93xx_priv *priv = GET_PRIV(dev); + struct mac_regs *mac = GET_REGS(dev); + uchar *mac_addr = dev->enetaddr; + int i; + + debug("+ep93xx_eth_open"); + + /* Reset the MAC */ + ep93xx_mac_reset(dev); + + /* Reset the descriptor queues' current and end address values */ + priv->tx_dq.current = priv->tx_dq.base; + priv->tx_dq.end = (priv->tx_dq.base + NUMTXDESC); + + priv->tx_sq.current = priv->tx_sq.base; + priv->tx_sq.end = (priv->tx_sq.base + NUMTXDESC); + + priv->rx_dq.current = priv->rx_dq.base; + priv->rx_dq.end = (priv->rx_dq.base + NUMRXDESC); + + priv->rx_sq.current = priv->rx_sq.base; + priv->rx_sq.end = (priv->rx_sq.base + NUMRXDESC); + + /* + * Set the transmit descriptor and status queues' base address, + * current address, and length registers. Set the maximum frame + * length and threshold. Enable the transmit descriptor processor. + */ + writel((uint32_t)priv->tx_dq.base, &mac->txdq.badd); + writel((uint32_t)priv->tx_dq.base, &mac->txdq.curadd); + writel(sizeof(struct tx_descriptor) * NUMTXDESC, &mac->txdq.blen); + + writel((uint32_t)priv->tx_sq.base, &mac->txstsq.badd); + writel((uint32_t)priv->tx_sq.base, &mac->txstsq.curadd); + writel(sizeof(struct tx_status) * NUMTXDESC, &mac->txstsq.blen); + + writel(0x00040000, &mac->txdthrshld); + writel(0x00040000, &mac->txststhrshld); + + writel((TXSTARTMAX << 0) | (PKTSIZE_ALIGN << 16), &mac->maxfrmlen); + writel(BMCTL_TXEN, &mac->bmctl); + + /* + * Set the receive descriptor and status queues' base address, + * current address, and length registers. Enable the receive + * descriptor processor. + */ + writel((uint32_t)priv->rx_dq.base, &mac->rxdq.badd); + writel((uint32_t)priv->rx_dq.base, &mac->rxdq.curadd); + writel(sizeof(struct rx_descriptor) * NUMRXDESC, &mac->rxdq.blen); + + writel((uint32_t)priv->rx_sq.base, &mac->rxstsq.badd); + writel((uint32_t)priv->rx_sq.base, &mac->rxstsq.curadd); + writel(sizeof(struct rx_status) * NUMRXDESC, &mac->rxstsq.blen); + + writel(0x00040000, &mac->rxdthrshld); + + writel(BMCTL_RXEN, &mac->bmctl); + + writel(0x00040000, &mac->rxststhrshld); + + /* Wait until the receive descriptor processor is active */ + while (!(readl(&mac->bmsts) & BMSTS_RXACT)) + ; /* noop */ + + /* + * Initialize the RX descriptor queue. Clear the TX descriptor queue. + * Clear the RX and TX status queues. Enqueue the RX descriptor and + * status entries to the MAC. + */ + for (i = 0; i < NUMRXDESC; i++) { + /* set buffer address */ + (priv->rx_dq.base + i)->word1 = (uint32_t)net_rx_packets[i]; + + /* set buffer length, clear buffer index and NSOF */ + (priv->rx_dq.base + i)->word2 = PKTSIZE_ALIGN; + } + + memset(priv->tx_dq.base, 0, + (sizeof(struct tx_descriptor) * NUMTXDESC)); + memset(priv->rx_sq.base, 0, + (sizeof(struct rx_status) * NUMRXDESC)); + memset(priv->tx_sq.base, 0, + (sizeof(struct tx_status) * NUMTXDESC)); + + writel(NUMRXDESC, &mac->rxdqenq); + writel(NUMRXDESC, &mac->rxstsqenq); + + /* Set the primary MAC address */ + writel(AFP_IAPRIMARY, &mac->afp); + writel(mac_addr[0] | (mac_addr[1] << 8) | + (mac_addr[2] << 16) | (mac_addr[3] << 24), + &mac->indad); + writel(mac_addr[4] | (mac_addr[5] << 8), &mac->indad_upper); + + /* Turn on RX and TX */ + writel(RXCTL_IA0 | RXCTL_BA | RXCTL_SRXON | + RXCTL_RCRCA | RXCTL_MA, &mac->rxctl); + writel(TXCTL_STXON, &mac->txctl); + + /* Dump data structures if we're debugging */ + dump_dev(dev); + dump_rx_descriptor_queue(dev); + dump_rx_status_queue(dev); + dump_tx_descriptor_queue(dev); + dump_tx_status_queue(dev); + + debug("-ep93xx_eth_open"); + + return 1; +} + +/** + * Halt EP93xx MAC transmit and receive by clearing the TxCTL and RxCTL + * registers. + */ +static void ep93xx_eth_close(struct eth_device *dev) +{ + struct mac_regs *mac = GET_REGS(dev); + + debug("+ep93xx_eth_close"); + + writel(0x00000000, &mac->rxctl); + writel(0x00000000, &mac->txctl); + + debug("-ep93xx_eth_close"); +} + +/** + * Copy a frame of data from the MAC into the protocol layer for further + * processing. + */ +static int ep93xx_eth_rcv_packet(struct eth_device *dev) +{ + struct mac_regs *mac = GET_REGS(dev); + struct ep93xx_priv *priv = GET_PRIV(dev); + int len = -1; + + debug("+ep93xx_eth_rcv_packet"); + + if (RX_STATUS_RFP(priv->rx_sq.current)) { + if (RX_STATUS_RWE(priv->rx_sq.current)) { + /* + * We have a good frame. Extract the frame's length + * from the current rx_status_queue entry, and copy + * the frame's data into net_rx_packets[] of the + * protocol stack. We track the total number of + * bytes in the frame (nbytes_frame) which will be + * used when we pass the data off to the protocol + * layer via net_process_received_packet(). + */ + len = RX_STATUS_FRAME_LEN(priv->rx_sq.current); + + net_process_received_packet( + (uchar *)priv->rx_dq.current->word1, len); + + debug("reporting %d bytes...\n", len); + } else { + /* Do we have an erroneous packet? */ + error("packet rx error, status %08X %08X", + priv->rx_sq.current->word1, + priv->rx_sq.current->word2); + dump_rx_descriptor_queue(dev); + dump_rx_status_queue(dev); + } + + /* + * Clear the associated status queue entry, and + * increment our current pointers to the next RX + * descriptor and status queue entries (making sure + * we wrap properly). + */ + memset((void *)priv->rx_sq.current, 0, + sizeof(struct rx_status)); + + priv->rx_sq.current++; + if (priv->rx_sq.current >= priv->rx_sq.end) + priv->rx_sq.current = priv->rx_sq.base; + + priv->rx_dq.current++; + if (priv->rx_dq.current >= priv->rx_dq.end) + priv->rx_dq.current = priv->rx_dq.base; + + /* + * Finally, return the RX descriptor and status entries + * back to the MAC engine, and loop again, checking for + * more descriptors to process. + */ + writel(1, &mac->rxdqenq); + writel(1, &mac->rxstsqenq); + } else { + len = 0; + } + + debug("-ep93xx_eth_rcv_packet %d", len); + return len; +} + +/** + * Send a block of data via ethernet. + */ +static int ep93xx_eth_send_packet(struct eth_device *dev, + void * const packet, int const length) +{ + struct mac_regs *mac = GET_REGS(dev); + struct ep93xx_priv *priv = GET_PRIV(dev); + int ret = -1; + + debug("+ep93xx_eth_send_packet"); + + /* Parameter check */ + BUG_ON(packet == NULL); + + /* + * Initialize the TX descriptor queue with the new packet's info. + * Clear the associated status queue entry. Enqueue the packet + * to the MAC for transmission. + */ + + /* set buffer address */ + priv->tx_dq.current->word1 = (uint32_t)packet; + + /* set buffer length and EOF bit */ + priv->tx_dq.current->word2 = length | TX_DESC_EOF; + + /* clear tx status */ + priv->tx_sq.current->word1 = 0; + + /* enqueue the TX descriptor */ + writel(1, &mac->txdqenq); + + /* wait for the frame to become processed */ + while (!TX_STATUS_TXFP(priv->tx_sq.current)) + ; /* noop */ + + if (!TX_STATUS_TXWE(priv->tx_sq.current)) { + error("packet tx error, status %08X", + priv->tx_sq.current->word1); + dump_tx_descriptor_queue(dev); + dump_tx_status_queue(dev); + + /* TODO: Add better error handling? */ + goto eth_send_out; + } + + ret = 0; + /* Fall through */ + +eth_send_out: + debug("-ep93xx_eth_send_packet %d", ret); + return ret; +} + +#if defined(CONFIG_MII) +int ep93xx_miiphy_initialize(bd_t * const bd) +{ + miiphy_register("ep93xx_eth0", ep93xx_miiphy_read, ep93xx_miiphy_write); + return 0; +} +#endif + +/** + * Initialize the EP93xx MAC. The MAC hardware is reset. Buffers are + * allocated, if necessary, for the TX and RX descriptor and status queues, + * as well as for received packets. The EP93XX MAC hardware is initialized. + * Transmit and receive operations are enabled. + */ +int ep93xx_eth_initialize(u8 dev_num, int base_addr) +{ + int ret = -1; + struct eth_device *dev; + struct ep93xx_priv *priv; + + debug("+ep93xx_eth_initialize"); + + priv = malloc(sizeof(*priv)); + if (!priv) { + error("malloc() failed"); + goto eth_init_failed_0; + } + memset(priv, 0, sizeof(*priv)); + + priv->regs = (struct mac_regs *)base_addr; + + priv->tx_dq.base = calloc(NUMTXDESC, + sizeof(struct tx_descriptor)); + if (priv->tx_dq.base == NULL) { + error("calloc() failed"); + goto eth_init_failed_1; + } + + priv->tx_sq.base = calloc(NUMTXDESC, + sizeof(struct tx_status)); + if (priv->tx_sq.base == NULL) { + error("calloc() failed"); + goto eth_init_failed_2; + } + + priv->rx_dq.base = calloc(NUMRXDESC, + sizeof(struct rx_descriptor)); + if (priv->rx_dq.base == NULL) { + error("calloc() failed"); + goto eth_init_failed_3; + } + + priv->rx_sq.base = calloc(NUMRXDESC, + sizeof(struct rx_status)); + if (priv->rx_sq.base == NULL) { + error("calloc() failed"); + goto eth_init_failed_4; + } + + dev = malloc(sizeof *dev); + if (dev == NULL) { + error("malloc() failed"); + goto eth_init_failed_5; + } + memset(dev, 0, sizeof *dev); + + dev->iobase = base_addr; + dev->priv = priv; + dev->init = ep93xx_eth_open; + dev->halt = ep93xx_eth_close; + dev->send = ep93xx_eth_send_packet; + dev->recv = ep93xx_eth_rcv_packet; + + sprintf(dev->name, "ep93xx_eth-%hu", dev_num); + + eth_register(dev); + + /* Done! */ + ret = 1; + goto eth_init_done; + +eth_init_failed_5: + free(priv->rx_sq.base); + /* Fall through */ + +eth_init_failed_4: + free(priv->rx_dq.base); + /* Fall through */ + +eth_init_failed_3: + free(priv->tx_sq.base); + /* Fall through */ + +eth_init_failed_2: + free(priv->tx_dq.base); + /* Fall through */ + +eth_init_failed_1: + free(priv); + /* Fall through */ + +eth_init_failed_0: + /* Fall through */ + +eth_init_done: + debug("-ep93xx_eth_initialize %d", ret); + return ret; +} + +#if defined(CONFIG_MII) + +/** + * Maximum MII address we support + */ +#define MII_ADDRESS_MAX 31 + +/** + * Maximum MII register address we support + */ +#define MII_REGISTER_MAX 31 + +/** + * Read a 16-bit value from an MII register. + */ +static int ep93xx_miiphy_read(const char * const dev, unsigned char const addr, + unsigned char const reg, unsigned short * const value) +{ + struct mac_regs *mac = (struct mac_regs *)MAC_BASE; + int ret = -1; + uint32_t self_ctl; + + debug("+ep93xx_miiphy_read"); + + /* Parameter checks */ + BUG_ON(dev == NULL); + BUG_ON(addr > MII_ADDRESS_MAX); + BUG_ON(reg > MII_REGISTER_MAX); + BUG_ON(value == NULL); + + /* + * Save the current SelfCTL register value. Set MAC to suppress + * preamble bits. Wait for any previous MII command to complete + * before issuing the new command. + */ + self_ctl = readl(&mac->selfctl); +#if defined(CONFIG_MII_SUPPRESS_PREAMBLE) + writel(self_ctl & ~(1 << 8), &mac->selfctl); +#endif /* defined(CONFIG_MII_SUPPRESS_PREAMBLE) */ + + while (readl(&mac->miists) & MIISTS_BUSY) + ; /* noop */ + + /* + * Issue the MII 'read' command. Wait for the command to complete. + * Read the MII data value. + */ + writel(MIICMD_OPCODE_READ | ((uint32_t)addr << 5) | (uint32_t)reg, + &mac->miicmd); + while (readl(&mac->miists) & MIISTS_BUSY) + ; /* noop */ + + *value = (unsigned short)readl(&mac->miidata); + + /* Restore the saved SelfCTL value and return. */ + writel(self_ctl, &mac->selfctl); + + ret = 0; + /* Fall through */ + + debug("-ep93xx_miiphy_read"); + return ret; +} + +/** + * Write a 16-bit value to an MII register. + */ +static int ep93xx_miiphy_write(const char * const dev, unsigned char const addr, + unsigned char const reg, unsigned short const value) +{ + struct mac_regs *mac = (struct mac_regs *)MAC_BASE; + int ret = -1; + uint32_t self_ctl; + + debug("+ep93xx_miiphy_write"); + + /* Parameter checks */ + BUG_ON(dev == NULL); + BUG_ON(addr > MII_ADDRESS_MAX); + BUG_ON(reg > MII_REGISTER_MAX); + + /* + * Save the current SelfCTL register value. Set MAC to suppress + * preamble bits. Wait for any previous MII command to complete + * before issuing the new command. + */ + self_ctl = readl(&mac->selfctl); +#if defined(CONFIG_MII_SUPPRESS_PREAMBLE) + writel(self_ctl & ~(1 << 8), &mac->selfctl); +#endif /* defined(CONFIG_MII_SUPPRESS_PREAMBLE) */ + + while (readl(&mac->miists) & MIISTS_BUSY) + ; /* noop */ + + /* Issue the MII 'write' command. Wait for the command to complete. */ + writel((uint32_t)value, &mac->miidata); + writel(MIICMD_OPCODE_WRITE | ((uint32_t)addr << 5) | (uint32_t)reg, + &mac->miicmd); + while (readl(&mac->miists) & MIISTS_BUSY) + ; /* noop */ + + /* Restore the saved SelfCTL value and return. */ + writel(self_ctl, &mac->selfctl); + + ret = 0; + /* Fall through */ + + debug("-ep93xx_miiphy_write"); + return ret; +} +#endif /* defined(CONFIG_MII) */ diff --git a/sources/uboot-be550/drivers/net/ep93xx_eth.h b/sources/uboot-be550/drivers/net/ep93xx_eth.h new file mode 100644 index 00000000..e6c949ff --- /dev/null +++ b/sources/uboot-be550/drivers/net/ep93xx_eth.h @@ -0,0 +1,127 @@ +/* + * Copyright (C) 2009 Matthias Kaehlcke + * + * Copyright (C) 2004, 2005 + * Cory T. Tusar, Videon Central, Inc., + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _EP93XX_ETH_H +#define _EP93XX_ETH_H + +#include + +/** + * #define this to dump device status and queue info during initialization and + * following errors. + */ +#undef EP93XX_MAC_DEBUG + +/** + * Number of descriptor and status entries in our RX queues. + * It must be power of 2 ! + */ +#define NUMRXDESC PKTBUFSRX + +/** + * Number of descriptor and status entries in our TX queues. + */ +#define NUMTXDESC 1 + +/** + * 944 = (1024 - 64) - 16, Fifo size - Minframesize - 16 (Chip FACT) + */ +#define TXSTARTMAX 944 + +/** + * Receive descriptor queue entry + */ +struct rx_descriptor { + uint32_t word1; + uint32_t word2; +}; + +/** + * Receive status queue entry + */ +struct rx_status { + uint32_t word1; + uint32_t word2; +}; + +#define RX_STATUS_RWE(rx_status) ((rx_status->word1 >> 30) & 0x01) +#define RX_STATUS_RFP(rx_status) ((rx_status->word1 >> 31) & 0x01) +#define RX_STATUS_FRAME_LEN(rx_status) (rx_status->word2 & 0xFFFF) + +/** + * Transmit descriptor queue entry + */ +struct tx_descriptor { + uint32_t word1; + uint32_t word2; +}; + +#define TX_DESC_EOF (1 << 31) + +/** + * Transmit status queue entry + */ +struct tx_status { + uint32_t word1; +}; + +#define TX_STATUS_TXWE(tx_status) (((tx_status)->word1 >> 30) & 0x01) +#define TX_STATUS_TXFP(tx_status) (((tx_status)->word1 >> 31) & 0x01) + +/** + * Transmit descriptor queue + */ +struct tx_descriptor_queue { + struct tx_descriptor *base; + struct tx_descriptor *current; + struct tx_descriptor *end; +}; + +/** + * Transmit status queue + */ +struct tx_status_queue { + struct tx_status *base; + volatile struct tx_status *current; + struct tx_status *end; +}; + +/** + * Receive descriptor queue + */ +struct rx_descriptor_queue { + struct rx_descriptor *base; + struct rx_descriptor *current; + struct rx_descriptor *end; +}; + +/** + * Receive status queue + */ +struct rx_status_queue { + struct rx_status *base; + volatile struct rx_status *current; + struct rx_status *end; +}; + +/** + * EP93xx MAC private data structure + */ +struct ep93xx_priv { + struct rx_descriptor_queue rx_dq; + struct rx_status_queue rx_sq; + void *rx_buffer[NUMRXDESC]; + + struct tx_descriptor_queue tx_dq; + struct tx_status_queue tx_sq; + + struct mac_regs *regs; +}; + +#endif diff --git a/sources/uboot-be550/drivers/net/ethoc.c b/sources/uboot-be550/drivers/net/ethoc.c new file mode 100644 index 00000000..edb3c808 --- /dev/null +++ b/sources/uboot-be550/drivers/net/ethoc.c @@ -0,0 +1,511 @@ +/* + * Opencore 10/100 ethernet mac driver + * + * Copyright (C) 2007-2008 Avionic Design Development GmbH + * Copyright (C) 2008-2009 Avionic Design GmbH + * Thierry Reding + * Copyright (C) 2010 Thomas Chou + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include + +/* register offsets */ +#define MODER 0x00 +#define INT_SOURCE 0x04 +#define INT_MASK 0x08 +#define IPGT 0x0c +#define IPGR1 0x10 +#define IPGR2 0x14 +#define PACKETLEN 0x18 +#define COLLCONF 0x1c +#define TX_BD_NUM 0x20 +#define CTRLMODER 0x24 +#define MIIMODER 0x28 +#define MIICOMMAND 0x2c +#define MIIADDRESS 0x30 +#define MIITX_DATA 0x34 +#define MIIRX_DATA 0x38 +#define MIISTATUS 0x3c +#define MAC_ADDR0 0x40 +#define MAC_ADDR1 0x44 +#define ETH_HASH0 0x48 +#define ETH_HASH1 0x4c +#define ETH_TXCTRL 0x50 + +/* mode register */ +#define MODER_RXEN (1 << 0) /* receive enable */ +#define MODER_TXEN (1 << 1) /* transmit enable */ +#define MODER_NOPRE (1 << 2) /* no preamble */ +#define MODER_BRO (1 << 3) /* broadcast address */ +#define MODER_IAM (1 << 4) /* individual address mode */ +#define MODER_PRO (1 << 5) /* promiscuous mode */ +#define MODER_IFG (1 << 6) /* interframe gap for incoming frames */ +#define MODER_LOOP (1 << 7) /* loopback */ +#define MODER_NBO (1 << 8) /* no back-off */ +#define MODER_EDE (1 << 9) /* excess defer enable */ +#define MODER_FULLD (1 << 10) /* full duplex */ +#define MODER_RESET (1 << 11) /* FIXME: reset (undocumented) */ +#define MODER_DCRC (1 << 12) /* delayed CRC enable */ +#define MODER_CRC (1 << 13) /* CRC enable */ +#define MODER_HUGE (1 << 14) /* huge packets enable */ +#define MODER_PAD (1 << 15) /* padding enabled */ +#define MODER_RSM (1 << 16) /* receive small packets */ + +/* interrupt source and mask registers */ +#define INT_MASK_TXF (1 << 0) /* transmit frame */ +#define INT_MASK_TXE (1 << 1) /* transmit error */ +#define INT_MASK_RXF (1 << 2) /* receive frame */ +#define INT_MASK_RXE (1 << 3) /* receive error */ +#define INT_MASK_BUSY (1 << 4) +#define INT_MASK_TXC (1 << 5) /* transmit control frame */ +#define INT_MASK_RXC (1 << 6) /* receive control frame */ + +#define INT_MASK_TX (INT_MASK_TXF | INT_MASK_TXE) +#define INT_MASK_RX (INT_MASK_RXF | INT_MASK_RXE) + +#define INT_MASK_ALL ( \ + INT_MASK_TXF | INT_MASK_TXE | \ + INT_MASK_RXF | INT_MASK_RXE | \ + INT_MASK_TXC | INT_MASK_RXC | \ + INT_MASK_BUSY \ + ) + +/* packet length register */ +#define PACKETLEN_MIN(min) (((min) & 0xffff) << 16) +#define PACKETLEN_MAX(max) (((max) & 0xffff) << 0) +#define PACKETLEN_MIN_MAX(min, max) (PACKETLEN_MIN(min) | \ + PACKETLEN_MAX(max)) + +/* transmit buffer number register */ +#define TX_BD_NUM_VAL(x) (((x) <= 0x80) ? (x) : 0x80) + +/* control module mode register */ +#define CTRLMODER_PASSALL (1 << 0) /* pass all receive frames */ +#define CTRLMODER_RXFLOW (1 << 1) /* receive control flow */ +#define CTRLMODER_TXFLOW (1 << 2) /* transmit control flow */ + +/* MII mode register */ +#define MIIMODER_CLKDIV(x) ((x) & 0xfe) /* needs to be an even number */ +#define MIIMODER_NOPRE (1 << 8) /* no preamble */ + +/* MII command register */ +#define MIICOMMAND_SCAN (1 << 0) /* scan status */ +#define MIICOMMAND_READ (1 << 1) /* read status */ +#define MIICOMMAND_WRITE (1 << 2) /* write control data */ + +/* MII address register */ +#define MIIADDRESS_FIAD(x) (((x) & 0x1f) << 0) +#define MIIADDRESS_RGAD(x) (((x) & 0x1f) << 8) +#define MIIADDRESS_ADDR(phy, reg) (MIIADDRESS_FIAD(phy) | \ + MIIADDRESS_RGAD(reg)) + +/* MII transmit data register */ +#define MIITX_DATA_VAL(x) ((x) & 0xffff) + +/* MII receive data register */ +#define MIIRX_DATA_VAL(x) ((x) & 0xffff) + +/* MII status register */ +#define MIISTATUS_LINKFAIL (1 << 0) +#define MIISTATUS_BUSY (1 << 1) +#define MIISTATUS_INVALID (1 << 2) + +/* TX buffer descriptor */ +#define TX_BD_CS (1 << 0) /* carrier sense lost */ +#define TX_BD_DF (1 << 1) /* defer indication */ +#define TX_BD_LC (1 << 2) /* late collision */ +#define TX_BD_RL (1 << 3) /* retransmission limit */ +#define TX_BD_RETRY_MASK (0x00f0) +#define TX_BD_RETRY(x) (((x) & 0x00f0) >> 4) +#define TX_BD_UR (1 << 8) /* transmitter underrun */ +#define TX_BD_CRC (1 << 11) /* TX CRC enable */ +#define TX_BD_PAD (1 << 12) /* pad enable */ +#define TX_BD_WRAP (1 << 13) +#define TX_BD_IRQ (1 << 14) /* interrupt request enable */ +#define TX_BD_READY (1 << 15) /* TX buffer ready */ +#define TX_BD_LEN(x) (((x) & 0xffff) << 16) +#define TX_BD_LEN_MASK (0xffff << 16) + +#define TX_BD_STATS (TX_BD_CS | TX_BD_DF | TX_BD_LC | \ + TX_BD_RL | TX_BD_RETRY_MASK | TX_BD_UR) + +/* RX buffer descriptor */ +#define RX_BD_LC (1 << 0) /* late collision */ +#define RX_BD_CRC (1 << 1) /* RX CRC error */ +#define RX_BD_SF (1 << 2) /* short frame */ +#define RX_BD_TL (1 << 3) /* too long */ +#define RX_BD_DN (1 << 4) /* dribble nibble */ +#define RX_BD_IS (1 << 5) /* invalid symbol */ +#define RX_BD_OR (1 << 6) /* receiver overrun */ +#define RX_BD_MISS (1 << 7) +#define RX_BD_CF (1 << 8) /* control frame */ +#define RX_BD_WRAP (1 << 13) +#define RX_BD_IRQ (1 << 14) /* interrupt request enable */ +#define RX_BD_EMPTY (1 << 15) +#define RX_BD_LEN(x) (((x) & 0xffff) << 16) + +#define RX_BD_STATS (RX_BD_LC | RX_BD_CRC | RX_BD_SF | RX_BD_TL | \ + RX_BD_DN | RX_BD_IS | RX_BD_OR | RX_BD_MISS) + +#define ETHOC_BUFSIZ 1536 +#define ETHOC_ZLEN 64 +#define ETHOC_BD_BASE 0x400 +#define ETHOC_TIMEOUT (HZ / 2) +#define ETHOC_MII_TIMEOUT (1 + (HZ / 5)) + +/** + * struct ethoc - driver-private device structure + * @num_tx: number of send buffers + * @cur_tx: last send buffer written + * @dty_tx: last buffer actually sent + * @num_rx: number of receive buffers + * @cur_rx: current receive buffer + */ +struct ethoc { + u32 num_tx; + u32 cur_tx; + u32 dty_tx; + u32 num_rx; + u32 cur_rx; +}; + +/** + * struct ethoc_bd - buffer descriptor + * @stat: buffer statistics + * @addr: physical memory address + */ +struct ethoc_bd { + u32 stat; + u32 addr; +}; + +static inline u32 ethoc_read(struct eth_device *dev, size_t offset) +{ + return readl(dev->iobase + offset); +} + +static inline void ethoc_write(struct eth_device *dev, size_t offset, u32 data) +{ + writel(data, dev->iobase + offset); +} + +static inline void ethoc_read_bd(struct eth_device *dev, int index, + struct ethoc_bd *bd) +{ + size_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd)); + bd->stat = ethoc_read(dev, offset + 0); + bd->addr = ethoc_read(dev, offset + 4); +} + +static inline void ethoc_write_bd(struct eth_device *dev, int index, + const struct ethoc_bd *bd) +{ + size_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd)); + ethoc_write(dev, offset + 0, bd->stat); + ethoc_write(dev, offset + 4, bd->addr); +} + +static int ethoc_set_mac_address(struct eth_device *dev) +{ + u8 *mac = dev->enetaddr; + + ethoc_write(dev, MAC_ADDR0, (mac[2] << 24) | (mac[3] << 16) | + (mac[4] << 8) | (mac[5] << 0)); + ethoc_write(dev, MAC_ADDR1, (mac[0] << 8) | (mac[1] << 0)); + return 0; +} + +static inline void ethoc_ack_irq(struct eth_device *dev, u32 mask) +{ + ethoc_write(dev, INT_SOURCE, mask); +} + +static inline void ethoc_enable_rx_and_tx(struct eth_device *dev) +{ + u32 mode = ethoc_read(dev, MODER); + mode |= MODER_RXEN | MODER_TXEN; + ethoc_write(dev, MODER, mode); +} + +static inline void ethoc_disable_rx_and_tx(struct eth_device *dev) +{ + u32 mode = ethoc_read(dev, MODER); + mode &= ~(MODER_RXEN | MODER_TXEN); + ethoc_write(dev, MODER, mode); +} + +static int ethoc_init_ring(struct eth_device *dev) +{ + struct ethoc *priv = (struct ethoc *)dev->priv; + struct ethoc_bd bd; + int i; + + priv->cur_tx = 0; + priv->dty_tx = 0; + priv->cur_rx = 0; + + /* setup transmission buffers */ + bd.stat = TX_BD_IRQ | TX_BD_CRC; + + for (i = 0; i < priv->num_tx; i++) { + if (i == priv->num_tx - 1) + bd.stat |= TX_BD_WRAP; + + ethoc_write_bd(dev, i, &bd); + } + + bd.stat = RX_BD_EMPTY | RX_BD_IRQ; + + for (i = 0; i < priv->num_rx; i++) { + bd.addr = (u32)net_rx_packets[i]; + if (i == priv->num_rx - 1) + bd.stat |= RX_BD_WRAP; + + flush_dcache_range(bd.addr, bd.addr + PKTSIZE_ALIGN); + ethoc_write_bd(dev, priv->num_tx + i, &bd); + } + + return 0; +} + +static int ethoc_reset(struct eth_device *dev) +{ + u32 mode; + + /* TODO: reset controller? */ + + ethoc_disable_rx_and_tx(dev); + + /* TODO: setup registers */ + + /* enable FCS generation and automatic padding */ + mode = ethoc_read(dev, MODER); + mode |= MODER_CRC | MODER_PAD; + ethoc_write(dev, MODER, mode); + + /* set full-duplex mode */ + mode = ethoc_read(dev, MODER); + mode |= MODER_FULLD; + ethoc_write(dev, MODER, mode); + ethoc_write(dev, IPGT, 0x15); + + ethoc_ack_irq(dev, INT_MASK_ALL); + ethoc_enable_rx_and_tx(dev); + return 0; +} + +static int ethoc_init(struct eth_device *dev, bd_t * bd) +{ + struct ethoc *priv = (struct ethoc *)dev->priv; + printf("ethoc\n"); + + priv->num_tx = 1; + priv->num_rx = PKTBUFSRX; + ethoc_write(dev, TX_BD_NUM, priv->num_tx); + ethoc_init_ring(dev); + ethoc_reset(dev); + + return 0; +} + +static int ethoc_update_rx_stats(struct ethoc_bd *bd) +{ + int ret = 0; + + if (bd->stat & RX_BD_TL) { + debug("ETHOC: " "RX: frame too long\n"); + ret++; + } + + if (bd->stat & RX_BD_SF) { + debug("ETHOC: " "RX: frame too short\n"); + ret++; + } + + if (bd->stat & RX_BD_DN) + debug("ETHOC: " "RX: dribble nibble\n"); + + if (bd->stat & RX_BD_CRC) { + debug("ETHOC: " "RX: wrong CRC\n"); + ret++; + } + + if (bd->stat & RX_BD_OR) { + debug("ETHOC: " "RX: overrun\n"); + ret++; + } + + if (bd->stat & RX_BD_LC) { + debug("ETHOC: " "RX: late collision\n"); + ret++; + } + + return ret; +} + +static int ethoc_rx(struct eth_device *dev, int limit) +{ + struct ethoc *priv = (struct ethoc *)dev->priv; + int count; + + for (count = 0; count < limit; ++count) { + u32 entry; + struct ethoc_bd bd; + + entry = priv->num_tx + (priv->cur_rx % priv->num_rx); + ethoc_read_bd(dev, entry, &bd); + if (bd.stat & RX_BD_EMPTY) + break; + + debug("%s(): RX buffer %d, %x received\n", + __func__, priv->cur_rx, bd.stat); + if (ethoc_update_rx_stats(&bd) == 0) { + int size = bd.stat >> 16; + size -= 4; /* strip the CRC */ + net_process_received_packet((void *)bd.addr, size); + } + + /* clear the buffer descriptor so it can be reused */ + flush_dcache_range(bd.addr, bd.addr + PKTSIZE_ALIGN); + bd.stat &= ~RX_BD_STATS; + bd.stat |= RX_BD_EMPTY; + ethoc_write_bd(dev, entry, &bd); + priv->cur_rx++; + } + + return count; +} + +static int ethoc_update_tx_stats(struct ethoc_bd *bd) +{ + if (bd->stat & TX_BD_LC) + debug("ETHOC: " "TX: late collision\n"); + + if (bd->stat & TX_BD_RL) + debug("ETHOC: " "TX: retransmit limit\n"); + + if (bd->stat & TX_BD_UR) + debug("ETHOC: " "TX: underrun\n"); + + if (bd->stat & TX_BD_CS) + debug("ETHOC: " "TX: carrier sense lost\n"); + + return 0; +} + +static void ethoc_tx(struct eth_device *dev) +{ + struct ethoc *priv = (struct ethoc *)dev->priv; + u32 entry = priv->dty_tx % priv->num_tx; + struct ethoc_bd bd; + + ethoc_read_bd(dev, entry, &bd); + if ((bd.stat & TX_BD_READY) == 0) + (void)ethoc_update_tx_stats(&bd); +} + +static int ethoc_send(struct eth_device *dev, void *packet, int length) +{ + struct ethoc *priv = (struct ethoc *)dev->priv; + struct ethoc_bd bd; + u32 entry; + u32 pending; + int tmo; + + entry = priv->cur_tx % priv->num_tx; + ethoc_read_bd(dev, entry, &bd); + if (unlikely(length < ETHOC_ZLEN)) + bd.stat |= TX_BD_PAD; + else + bd.stat &= ~TX_BD_PAD; + bd.addr = (u32)packet; + + flush_dcache_range(bd.addr, bd.addr + length); + bd.stat &= ~(TX_BD_STATS | TX_BD_LEN_MASK); + bd.stat |= TX_BD_LEN(length); + ethoc_write_bd(dev, entry, &bd); + + /* start transmit */ + bd.stat |= TX_BD_READY; + ethoc_write_bd(dev, entry, &bd); + + /* wait for transfer to succeed */ + tmo = get_timer(0) + 5 * CONFIG_SYS_HZ; + while (1) { + pending = ethoc_read(dev, INT_SOURCE); + ethoc_ack_irq(dev, pending & ~INT_MASK_RX); + if (pending & INT_MASK_BUSY) + debug("%s(): packet dropped\n", __func__); + + if (pending & INT_MASK_TX) { + ethoc_tx(dev); + break; + } + if (get_timer(0) >= tmo) { + debug("%s(): timed out\n", __func__); + return -1; + } + } + + debug("%s(): packet sent\n", __func__); + return 0; +} + +static void ethoc_halt(struct eth_device *dev) +{ + ethoc_disable_rx_and_tx(dev); +} + +static int ethoc_recv(struct eth_device *dev) +{ + u32 pending; + + pending = ethoc_read(dev, INT_SOURCE); + ethoc_ack_irq(dev, pending); + if (pending & INT_MASK_BUSY) + debug("%s(): packet dropped\n", __func__); + if (pending & INT_MASK_RX) { + debug("%s(): rx irq\n", __func__); + ethoc_rx(dev, PKTBUFSRX); + } + + return 0; +} + +int ethoc_initialize(u8 dev_num, int base_addr) +{ + struct ethoc *priv; + struct eth_device *dev; + + priv = malloc(sizeof(*priv)); + if (!priv) + return 0; + dev = malloc(sizeof(*dev)); + if (!dev) { + free(priv); + return 0; + } + + memset(dev, 0, sizeof(*dev)); + dev->priv = priv; + dev->iobase = base_addr; + dev->init = ethoc_init; + dev->halt = ethoc_halt; + dev->send = ethoc_send; + dev->recv = ethoc_recv; + dev->write_hwaddr = ethoc_set_mac_address; + sprintf(dev->name, "%s-%hu", "ETHOC", dev_num); + + eth_register(dev); + return 1; +} diff --git a/sources/uboot-be550/drivers/net/fec_mxc.c b/sources/uboot-be550/drivers/net/fec_mxc.c new file mode 100644 index 00000000..3340dd25 --- /dev/null +++ b/sources/uboot-be550/drivers/net/fec_mxc.c @@ -0,0 +1,1145 @@ +/* + * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd + * (C) Copyright 2008,2009 Eric Jarrige + * (C) Copyright 2008 Armadeus Systems nc + * (C) Copyright 2007 Pengutronix, Sascha Hauer + * (C) Copyright 2007 Pengutronix, Juergen Beisert + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include "fec_mxc.h" + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Timeout the transfer after 5 mS. This is usually a bit more, since + * the code in the tightloops this timeout is used in adds some overhead. + */ +#define FEC_XFER_TIMEOUT 5000 + +/* + * The standard 32-byte DMA alignment does not work on mx6solox, which requires + * 64-byte alignment in the DMA RX FEC buffer. + * Introduce the FEC_DMA_RX_MINALIGN which can cover mx6solox needs and also + * satisfies the alignment on other SoCs (32-bytes) + */ +#define FEC_DMA_RX_MINALIGN 64 + +#ifndef CONFIG_MII +#error "CONFIG_MII has to be defined!" +#endif + +#ifndef CONFIG_FEC_XCV_TYPE +#define CONFIG_FEC_XCV_TYPE MII100 +#endif + +/* + * The i.MX28 operates with packets in big endian. We need to swap them before + * sending and after receiving. + */ +#ifdef CONFIG_MX28 +#define CONFIG_FEC_MXC_SWAP_PACKET +#endif + +#define RXDESC_PER_CACHELINE (ARCH_DMA_MINALIGN/sizeof(struct fec_bd)) + +/* Check various alignment issues at compile time */ +#if ((ARCH_DMA_MINALIGN < 16) || (ARCH_DMA_MINALIGN % 16 != 0)) +#error "ARCH_DMA_MINALIGN must be multiple of 16!" +#endif + +#if ((PKTALIGN < ARCH_DMA_MINALIGN) || \ + (PKTALIGN % ARCH_DMA_MINALIGN != 0)) +#error "PKTALIGN must be multiple of ARCH_DMA_MINALIGN!" +#endif + +#undef DEBUG + +#ifdef CONFIG_FEC_MXC_SWAP_PACKET +static void swap_packet(uint32_t *packet, int length) +{ + int i; + + for (i = 0; i < DIV_ROUND_UP(length, 4); i++) + packet[i] = __swab32(packet[i]); +} +#endif + +/* + * MII-interface related functions + */ +static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyAddr, + uint8_t regAddr) +{ + uint32_t reg; /* convenient holder for the PHY register */ + uint32_t phy; /* convenient holder for the PHY */ + uint32_t start; + int val; + + /* + * reading from any PHY's register is done by properly + * programming the FEC's MII data register. + */ + writel(FEC_IEVENT_MII, ð->ievent); + reg = regAddr << FEC_MII_DATA_RA_SHIFT; + phy = phyAddr << FEC_MII_DATA_PA_SHIFT; + + writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | + phy | reg, ð->mii_data); + + /* + * wait for the related interrupt + */ + start = get_timer(0); + while (!(readl(ð->ievent) & FEC_IEVENT_MII)) { + if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) { + printf("Read MDIO failed...\n"); + return -1; + } + } + + /* + * clear mii interrupt bit + */ + writel(FEC_IEVENT_MII, ð->ievent); + + /* + * it's now safe to read the PHY's register + */ + val = (unsigned short)readl(ð->mii_data); + debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyAddr, + regAddr, val); + return val; +} + +static void fec_mii_setspeed(struct ethernet_regs *eth) +{ + /* + * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock + * and do not drop the Preamble. + * + * The i.MX28 and i.MX6 types have another field in the MSCR (aka + * MII_SPEED) register that defines the MDIO output hold time. Earlier + * versions are RAZ there, so just ignore the difference and write the + * register always. + * The minimal hold time according to IEE802.3 (clause 22) is 10 ns. + * HOLDTIME + 1 is the number of clk cycles the fec is holding the + * output. + * The HOLDTIME bitfield takes values between 0 and 7 (inclusive). + * Given that ceil(clkrate / 5000000) <= 64, the calculation for + * holdtime cannot result in a value greater than 3. + */ + u32 pclk = imx_get_fecclk(); + u32 speed = DIV_ROUND_UP(pclk, 5000000); + u32 hold = DIV_ROUND_UP(pclk, 100000000) - 1; +#ifdef FEC_QUIRK_ENET_MAC + speed--; +#endif + writel(speed << 1 | hold << 8, ð->mii_speed); + debug("%s: mii_speed %08x\n", __func__, readl(ð->mii_speed)); +} + +static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyAddr, + uint8_t regAddr, uint16_t data) +{ + uint32_t reg; /* convenient holder for the PHY register */ + uint32_t phy; /* convenient holder for the PHY */ + uint32_t start; + + reg = regAddr << FEC_MII_DATA_RA_SHIFT; + phy = phyAddr << FEC_MII_DATA_PA_SHIFT; + + writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR | + FEC_MII_DATA_TA | phy | reg | data, ð->mii_data); + + /* + * wait for the MII interrupt + */ + start = get_timer(0); + while (!(readl(ð->ievent) & FEC_IEVENT_MII)) { + if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) { + printf("Write MDIO failed...\n"); + return -1; + } + } + + /* + * clear MII interrupt bit + */ + writel(FEC_IEVENT_MII, ð->ievent); + debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyAddr, + regAddr, data); + + return 0; +} + +static int fec_phy_read(struct mii_dev *bus, int phyAddr, int dev_addr, + int regAddr) +{ + return fec_mdio_read(bus->priv, phyAddr, regAddr); +} + +static int fec_phy_write(struct mii_dev *bus, int phyAddr, int dev_addr, + int regAddr, u16 data) +{ + return fec_mdio_write(bus->priv, phyAddr, regAddr, data); +} + +#ifndef CONFIG_PHYLIB +static int miiphy_restart_aneg(struct eth_device *dev) +{ + int ret = 0; +#if !defined(CONFIG_FEC_MXC_NO_ANEG) + struct fec_priv *fec = (struct fec_priv *)dev->priv; + struct ethernet_regs *eth = fec->bus->priv; + + /* + * Wake up from sleep if necessary + * Reset PHY, then delay 300ns + */ +#ifdef CONFIG_MX27 + fec_mdio_write(eth, fec->phy_id, MII_DCOUNTER, 0x00FF); +#endif + fec_mdio_write(eth, fec->phy_id, MII_BMCR, BMCR_RESET); + udelay(1000); + + /* + * Set the auto-negotiation advertisement register bits + */ + fec_mdio_write(eth, fec->phy_id, MII_ADVERTISE, + LPA_100FULL | LPA_100HALF | LPA_10FULL | + LPA_10HALF | PHY_ANLPAR_PSB_802_3); + fec_mdio_write(eth, fec->phy_id, MII_BMCR, + BMCR_ANENABLE | BMCR_ANRESTART); + + if (fec->mii_postcall) + ret = fec->mii_postcall(fec->phy_id); + +#endif + return ret; +} + +static int miiphy_wait_aneg(struct eth_device *dev) +{ + uint32_t start; + int status; + struct fec_priv *fec = (struct fec_priv *)dev->priv; + struct ethernet_regs *eth = fec->bus->priv; + + /* + * Wait for AN completion + */ + start = get_timer(0); + do { + if (get_timer(start) > (CONFIG_SYS_HZ * 5)) { + printf("%s: Autonegotiation timeout\n", dev->name); + return -1; + } + + status = fec_mdio_read(eth, fec->phy_id, MII_BMSR); + if (status < 0) { + printf("%s: Autonegotiation failed. status: %d\n", + dev->name, status); + return -1; + } + } while (!(status & BMSR_LSTATUS)); + + return 0; +} +#endif + +static int fec_rx_task_enable(struct fec_priv *fec) +{ + writel(FEC_R_DES_ACTIVE_RDAR, &fec->eth->r_des_active); + return 0; +} + +static int fec_rx_task_disable(struct fec_priv *fec) +{ + return 0; +} + +static int fec_tx_task_enable(struct fec_priv *fec) +{ + writel(FEC_X_DES_ACTIVE_TDAR, &fec->eth->x_des_active); + return 0; +} + +static int fec_tx_task_disable(struct fec_priv *fec) +{ + return 0; +} + +/** + * Initialize receive task's buffer descriptors + * @param[in] fec all we know about the device yet + * @param[in] count receive buffer count to be allocated + * @param[in] dsize desired size of each receive buffer + * @return 0 on success + * + * Init all RX descriptors to default values. + */ +static void fec_rbd_init(struct fec_priv *fec, int count, int dsize) +{ + uint32_t size; + uint8_t *data; + int i; + + /* + * Reload the RX descriptors with default values and wipe + * the RX buffers. + */ + size = roundup(dsize, ARCH_DMA_MINALIGN); + for (i = 0; i < count; i++) { + data = (uint8_t *)fec->rbd_base[i].data_pointer; + memset(data, 0, dsize); + flush_dcache_range((uint32_t)data, (uint32_t)data + size); + + fec->rbd_base[i].status = FEC_RBD_EMPTY; + fec->rbd_base[i].data_length = 0; + } + + /* Mark the last RBD to close the ring. */ + fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY; + fec->rbd_index = 0; + + flush_dcache_range((unsigned)fec->rbd_base, + (unsigned)fec->rbd_base + size); +} + +/** + * Initialize transmit task's buffer descriptors + * @param[in] fec all we know about the device yet + * + * Transmit buffers are created externally. We only have to init the BDs here.\n + * Note: There is a race condition in the hardware. When only one BD is in + * use it must be marked with the WRAP bit to use it for every transmitt. + * This bit in combination with the READY bit results into double transmit + * of each data buffer. It seems the state machine checks READY earlier then + * resetting it after the first transfer. + * Using two BDs solves this issue. + */ +static void fec_tbd_init(struct fec_priv *fec) +{ + unsigned addr = (unsigned)fec->tbd_base; + unsigned size = roundup(2 * sizeof(struct fec_bd), + ARCH_DMA_MINALIGN); + + memset(fec->tbd_base, 0, size); + fec->tbd_base[0].status = 0; + fec->tbd_base[1].status = FEC_TBD_WRAP; + fec->tbd_index = 0; + flush_dcache_range(addr, addr + size); +} + +/** + * Mark the given read buffer descriptor as free + * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0 + * @param[in] pRbd buffer descriptor to mark free again + */ +static void fec_rbd_clean(int last, struct fec_bd *pRbd) +{ + unsigned short flags = FEC_RBD_EMPTY; + if (last) + flags |= FEC_RBD_WRAP; + writew(flags, &pRbd->status); + writew(0, &pRbd->data_length); +} + +static int fec_get_hwaddr(struct eth_device *dev, int dev_id, + unsigned char *mac) +{ + imx_get_mac_from_fuse(dev_id, mac); + return !is_valid_ethaddr(mac); +} + +static int fec_set_hwaddr(struct eth_device *dev) +{ + uchar *mac = dev->enetaddr; + struct fec_priv *fec = (struct fec_priv *)dev->priv; + + writel(0, &fec->eth->iaddr1); + writel(0, &fec->eth->iaddr2); + writel(0, &fec->eth->gaddr1); + writel(0, &fec->eth->gaddr2); + + /* + * Set physical address + */ + writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3], + &fec->eth->paddr1); + writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2); + + return 0; +} + +/* + * Do initial configuration of the FEC registers + */ +static void fec_reg_setup(struct fec_priv *fec) +{ + uint32_t rcntrl; + + /* + * Set interrupt mask register + */ + writel(0x00000000, &fec->eth->imask); + + /* + * Clear FEC-Lite interrupt event register(IEVENT) + */ + writel(0xffffffff, &fec->eth->ievent); + + + /* + * Set FEC-Lite receive control register(R_CNTRL): + */ + + /* Start with frame length = 1518, common for all modes. */ + rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT; + if (fec->xcv_type != SEVENWIRE) /* xMII modes */ + rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE; + if (fec->xcv_type == RGMII) + rcntrl |= FEC_RCNTRL_RGMII; + else if (fec->xcv_type == RMII) + rcntrl |= FEC_RCNTRL_RMII; + + writel(rcntrl, &fec->eth->r_cntrl); +} + +/** + * Start the FEC engine + * @param[in] dev Our device to handle + */ +static int fec_open(struct eth_device *edev) +{ + struct fec_priv *fec = (struct fec_priv *)edev->priv; + int speed; + uint32_t addr, size; + int i; + + debug("fec_open: fec_open(dev)\n"); + /* full-duplex, heartbeat disabled */ + writel(1 << 2, &fec->eth->x_cntrl); + fec->rbd_index = 0; + + /* Invalidate all descriptors */ + for (i = 0; i < FEC_RBD_NUM - 1; i++) + fec_rbd_clean(0, &fec->rbd_base[i]); + fec_rbd_clean(1, &fec->rbd_base[i]); + + /* Flush the descriptors into RAM */ + size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), + ARCH_DMA_MINALIGN); + addr = (uint32_t)fec->rbd_base; + flush_dcache_range(addr, addr + size); + +#ifdef FEC_QUIRK_ENET_MAC + /* Enable ENET HW endian SWAP */ + writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_DBSWAP, + &fec->eth->ecntrl); + /* Enable ENET store and forward mode */ + writel(readl(&fec->eth->x_wmrk) | FEC_X_WMRK_STRFWD, + &fec->eth->x_wmrk); +#endif + /* + * Enable FEC-Lite controller + */ + writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN, + &fec->eth->ecntrl); +#if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL) + udelay(100); + /* + * setup the MII gasket for RMII mode + */ + + /* disable the gasket */ + writew(0, &fec->eth->miigsk_enr); + + /* wait for the gasket to be disabled */ + while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) + udelay(2); + + /* configure gasket for RMII, 50 MHz, no loopback, and no echo */ + writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr); + + /* re-enable the gasket */ + writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr); + + /* wait until MII gasket is ready */ + int max_loops = 10; + while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) { + if (--max_loops <= 0) { + printf("WAIT for MII Gasket ready timed out\n"); + break; + } + } +#endif + +#ifdef CONFIG_PHYLIB + { + /* Start up the PHY */ + int ret = phy_startup(fec->phydev); + + if (ret) { + printf("Could not initialize PHY %s\n", + fec->phydev->dev->name); + return ret; + } + speed = fec->phydev->speed; + } +#else + miiphy_wait_aneg(edev); + speed = miiphy_speed(edev->name, fec->phy_id); + miiphy_duplex(edev->name, fec->phy_id); +#endif + +#ifdef FEC_QUIRK_ENET_MAC + { + u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED; + u32 rcr = readl(&fec->eth->r_cntrl) & ~FEC_RCNTRL_RMII_10T; + if (speed == _1000BASET) + ecr |= FEC_ECNTRL_SPEED; + else if (speed != _100BASET) + rcr |= FEC_RCNTRL_RMII_10T; + writel(ecr, &fec->eth->ecntrl); + writel(rcr, &fec->eth->r_cntrl); + } +#endif + debug("%s:Speed=%i\n", __func__, speed); + + /* + * Enable SmartDMA receive task + */ + fec_rx_task_enable(fec); + + udelay(100000); + return 0; +} + +static int fec_init(struct eth_device *dev, bd_t* bd) +{ + struct fec_priv *fec = (struct fec_priv *)dev->priv; + uint32_t mib_ptr = (uint32_t)&fec->eth->rmon_t_drop; + int i; + + /* Initialize MAC address */ + fec_set_hwaddr(dev); + + /* + * Setup transmit descriptors, there are two in total. + */ + fec_tbd_init(fec); + + /* Setup receive descriptors. */ + fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE); + + fec_reg_setup(fec); + + if (fec->xcv_type != SEVENWIRE) + fec_mii_setspeed(fec->bus->priv); + + /* + * Set Opcode/Pause Duration Register + */ + writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */ + writel(0x2, &fec->eth->x_wmrk); + /* + * Set multicast address filter + */ + writel(0x00000000, &fec->eth->gaddr1); + writel(0x00000000, &fec->eth->gaddr2); + + + /* Do not access reserved register for i.MX6UL */ + if (!is_cpu_type(MXC_CPU_MX6UL)) { + /* clear MIB RAM */ + for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4) + writel(0, i); + + /* FIFO receive start register */ + writel(0x520, &fec->eth->r_fstart); + } + + /* size and address of each buffer */ + writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr); + writel((uint32_t)fec->tbd_base, &fec->eth->etdsr); + writel((uint32_t)fec->rbd_base, &fec->eth->erdsr); + +#ifndef CONFIG_PHYLIB + if (fec->xcv_type != SEVENWIRE) + miiphy_restart_aneg(dev); +#endif + fec_open(dev); + return 0; +} + +/** + * Halt the FEC engine + * @param[in] dev Our device to handle + */ +static void fec_halt(struct eth_device *dev) +{ + struct fec_priv *fec = (struct fec_priv *)dev->priv; + int counter = 0xffff; + + /* + * issue graceful stop command to the FEC transmitter if necessary + */ + writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl), + &fec->eth->x_cntrl); + + debug("eth_halt: wait for stop regs\n"); + /* + * wait for graceful stop to register + */ + while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA))) + udelay(1); + + /* + * Disable SmartDMA tasks + */ + fec_tx_task_disable(fec); + fec_rx_task_disable(fec); + + /* + * Disable the Ethernet Controller + * Note: this will also reset the BD index counter! + */ + writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN, + &fec->eth->ecntrl); + fec->rbd_index = 0; + fec->tbd_index = 0; + debug("eth_halt: done\n"); +} + +/** + * Transmit one frame + * @param[in] dev Our ethernet device to handle + * @param[in] packet Pointer to the data to be transmitted + * @param[in] length Data count in bytes + * @return 0 on success + */ +static int fec_send(struct eth_device *dev, void *packet, int length) +{ + unsigned int status; + uint32_t size, end; + uint32_t addr; + int timeout = FEC_XFER_TIMEOUT; + int ret = 0; + + /* + * This routine transmits one frame. This routine only accepts + * 6-byte Ethernet addresses. + */ + struct fec_priv *fec = (struct fec_priv *)dev->priv; + + /* + * Check for valid length of data. + */ + if ((length > 1500) || (length <= 0)) { + printf("Payload (%d) too large\n", length); + return -1; + } + + /* + * Setup the transmit buffer. We are always using the first buffer for + * transmission, the second will be empty and only used to stop the DMA + * engine. We also flush the packet to RAM here to avoid cache trouble. + */ +#ifdef CONFIG_FEC_MXC_SWAP_PACKET + swap_packet((uint32_t *)packet, length); +#endif + + addr = (uint32_t)packet; + end = roundup(addr + length, ARCH_DMA_MINALIGN); + addr &= ~(ARCH_DMA_MINALIGN - 1); + flush_dcache_range(addr, end); + + writew(length, &fec->tbd_base[fec->tbd_index].data_length); + writel(addr, &fec->tbd_base[fec->tbd_index].data_pointer); + + /* + * update BD's status now + * This block: + * - is always the last in a chain (means no chain) + * - should transmitt the CRC + * - might be the last BD in the list, so the address counter should + * wrap (-> keep the WRAP flag) + */ + status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP; + status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY; + writew(status, &fec->tbd_base[fec->tbd_index].status); + + /* + * Flush data cache. This code flushes both TX descriptors to RAM. + * After this code, the descriptors will be safely in RAM and we + * can start DMA. + */ + size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN); + addr = (uint32_t)fec->tbd_base; + flush_dcache_range(addr, addr + size); + + /* + * Below we read the DMA descriptor's last four bytes back from the + * DRAM. This is important in order to make sure that all WRITE + * operations on the bus that were triggered by previous cache FLUSH + * have completed. + * + * Otherwise, on MX28, it is possible to observe a corruption of the + * DMA descriptors. Please refer to schematic "Figure 1-2" in MX28RM + * for the bus structure of MX28. The scenario is as follows: + * + * 1) ARM core triggers a series of WRITEs on the AHB_ARB2 bus going + * to DRAM due to flush_dcache_range() + * 2) ARM core writes the FEC registers via AHB_ARB2 + * 3) FEC DMA starts reading/writing from/to DRAM via AHB_ARB3 + * + * Note that 2) does sometimes finish before 1) due to reordering of + * WRITE accesses on the AHB bus, therefore triggering 3) before the + * DMA descriptor is fully written into DRAM. This results in occasional + * corruption of the DMA descriptor. + */ + readl(addr + size - 4); + + /* + * Enable SmartDMA transmit task + */ + fec_tx_task_enable(fec); + + /* + * Wait until frame is sent. On each turn of the wait cycle, we must + * invalidate data cache to see what's really in RAM. Also, we need + * barrier here. + */ + while (--timeout) { + if (!(readl(&fec->eth->x_des_active) & FEC_X_DES_ACTIVE_TDAR)) + break; + } + + if (!timeout) { + ret = -EINVAL; + goto out; + } + + /* + * The TDAR bit is cleared when the descriptors are all out from TX + * but on mx6solox we noticed that the READY bit is still not cleared + * right after TDAR. + * These are two distinct signals, and in IC simulation, we found that + * TDAR always gets cleared prior than the READY bit of last BD becomes + * cleared. + * In mx6solox, we use a later version of FEC IP. It looks like that + * this intrinsic behaviour of TDAR bit has changed in this newer FEC + * version. + * + * Fix this by polling the READY bit of BD after the TDAR polling, + * which covers the mx6solox case and does not harm the other SoCs. + */ + timeout = FEC_XFER_TIMEOUT; + while (--timeout) { + invalidate_dcache_range(addr, addr + size); + if (!(readw(&fec->tbd_base[fec->tbd_index].status) & + FEC_TBD_READY)) + break; + } + + if (!timeout) + ret = -EINVAL; + +out: + debug("fec_send: status 0x%x index %d ret %i\n", + readw(&fec->tbd_base[fec->tbd_index].status), + fec->tbd_index, ret); + /* for next transmission use the other buffer */ + if (fec->tbd_index) + fec->tbd_index = 0; + else + fec->tbd_index = 1; + + return ret; +} + +/** + * Pull one frame from the card + * @param[in] dev Our ethernet device to handle + * @return Length of packet read + */ +static int fec_recv(struct eth_device *dev) +{ + struct fec_priv *fec = (struct fec_priv *)dev->priv; + struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index]; + unsigned long ievent; + int frame_length, len = 0; + uint16_t bd_status; + uint32_t addr, size, end; + int i; + ALLOC_CACHE_ALIGN_BUFFER(uchar, buff, FEC_MAX_PKT_SIZE); + + /* + * Check if any critical events have happened + */ + ievent = readl(&fec->eth->ievent); + writel(ievent, &fec->eth->ievent); + debug("fec_recv: ievent 0x%lx\n", ievent); + if (ievent & FEC_IEVENT_BABR) { + fec_halt(dev); + fec_init(dev, fec->bd); + printf("some error: 0x%08lx\n", ievent); + return 0; + } + if (ievent & FEC_IEVENT_HBERR) { + /* Heartbeat error */ + writel(0x00000001 | readl(&fec->eth->x_cntrl), + &fec->eth->x_cntrl); + } + if (ievent & FEC_IEVENT_GRA) { + /* Graceful stop complete */ + if (readl(&fec->eth->x_cntrl) & 0x00000001) { + fec_halt(dev); + writel(~0x00000001 & readl(&fec->eth->x_cntrl), + &fec->eth->x_cntrl); + fec_init(dev, fec->bd); + } + } + + /* + * Read the buffer status. Before the status can be read, the data cache + * must be invalidated, because the data in RAM might have been changed + * by DMA. The descriptors are properly aligned to cachelines so there's + * no need to worry they'd overlap. + * + * WARNING: By invalidating the descriptor here, we also invalidate + * the descriptors surrounding this one. Therefore we can NOT change the + * contents of this descriptor nor the surrounding ones. The problem is + * that in order to mark the descriptor as processed, we need to change + * the descriptor. The solution is to mark the whole cache line when all + * descriptors in the cache line are processed. + */ + addr = (uint32_t)rbd; + addr &= ~(ARCH_DMA_MINALIGN - 1); + size = roundup(sizeof(struct fec_bd), ARCH_DMA_MINALIGN); + invalidate_dcache_range(addr, addr + size); + + bd_status = readw(&rbd->status); + debug("fec_recv: status 0x%x\n", bd_status); + + if (!(bd_status & FEC_RBD_EMPTY)) { + if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) && + ((readw(&rbd->data_length) - 4) > 14)) { + /* + * Get buffer address and size + */ + addr = readl(&rbd->data_pointer); + frame_length = readw(&rbd->data_length) - 4; + /* + * Invalidate data cache over the buffer + */ + end = roundup(addr + frame_length, ARCH_DMA_MINALIGN); + addr &= ~(ARCH_DMA_MINALIGN - 1); + invalidate_dcache_range(addr, end); + + /* + * Fill the buffer and pass it to upper layers + */ +#ifdef CONFIG_FEC_MXC_SWAP_PACKET + swap_packet((uint32_t *)addr, frame_length); +#endif + memcpy(buff, (char *)addr, frame_length); + net_process_received_packet(buff, frame_length); + len = frame_length; + } else { + if (bd_status & FEC_RBD_ERR) + printf("error frame: 0x%08x 0x%08x\n", + addr, bd_status); + } + + /* + * Free the current buffer, restart the engine and move forward + * to the next buffer. Here we check if the whole cacheline of + * descriptors was already processed and if so, we mark it free + * as whole. + */ + size = RXDESC_PER_CACHELINE - 1; + if ((fec->rbd_index & size) == size) { + i = fec->rbd_index - size; + addr = (uint32_t)&fec->rbd_base[i]; + for (; i <= fec->rbd_index ; i++) { + fec_rbd_clean(i == (FEC_RBD_NUM - 1), + &fec->rbd_base[i]); + } + flush_dcache_range(addr, + addr + ARCH_DMA_MINALIGN); + } + + fec_rx_task_enable(fec); + fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM; + } + debug("fec_recv: stop\n"); + + return len; +} + +static void fec_set_dev_name(char *dest, int dev_id) +{ + sprintf(dest, (dev_id == -1) ? "FEC" : "FEC%i", dev_id); +} + +static int fec_alloc_descs(struct fec_priv *fec) +{ + unsigned int size; + int i; + uint8_t *data; + + /* Allocate TX descriptors. */ + size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN); + fec->tbd_base = memalign(ARCH_DMA_MINALIGN, size); + if (!fec->tbd_base) + goto err_tx; + + /* Allocate RX descriptors. */ + size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), ARCH_DMA_MINALIGN); + fec->rbd_base = memalign(ARCH_DMA_MINALIGN, size); + if (!fec->rbd_base) + goto err_rx; + + memset(fec->rbd_base, 0, size); + + /* Allocate RX buffers. */ + + /* Maximum RX buffer size. */ + size = roundup(FEC_MAX_PKT_SIZE, FEC_DMA_RX_MINALIGN); + for (i = 0; i < FEC_RBD_NUM; i++) { + data = memalign(FEC_DMA_RX_MINALIGN, size); + if (!data) { + printf("%s: error allocating rxbuf %d\n", __func__, i); + goto err_ring; + } + + memset(data, 0, size); + + fec->rbd_base[i].data_pointer = (uint32_t)data; + fec->rbd_base[i].status = FEC_RBD_EMPTY; + fec->rbd_base[i].data_length = 0; + /* Flush the buffer to memory. */ + flush_dcache_range((uint32_t)data, (uint32_t)data + size); + } + + /* Mark the last RBD to close the ring. */ + fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY; + + fec->rbd_index = 0; + fec->tbd_index = 0; + + return 0; + +err_ring: + for (; i >= 0; i--) + free((void *)fec->rbd_base[i].data_pointer); + free(fec->rbd_base); +err_rx: + free(fec->tbd_base); +err_tx: + return -ENOMEM; +} + +static void fec_free_descs(struct fec_priv *fec) +{ + int i; + + for (i = 0; i < FEC_RBD_NUM; i++) + free((void *)fec->rbd_base[i].data_pointer); + free(fec->rbd_base); + free(fec->tbd_base); +} + +#ifdef CONFIG_PHYLIB +int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr, + struct mii_dev *bus, struct phy_device *phydev) +#else +static int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr, + struct mii_dev *bus, int phy_id) +#endif +{ + struct eth_device *edev; + struct fec_priv *fec; + unsigned char ethaddr[6]; + uint32_t start; + int ret = 0; + + /* create and fill edev struct */ + edev = (struct eth_device *)malloc(sizeof(struct eth_device)); + if (!edev) { + puts("fec_mxc: not enough malloc memory for eth_device\n"); + ret = -ENOMEM; + goto err1; + } + + fec = (struct fec_priv *)malloc(sizeof(struct fec_priv)); + if (!fec) { + puts("fec_mxc: not enough malloc memory for fec_priv\n"); + ret = -ENOMEM; + goto err2; + } + + memset(edev, 0, sizeof(*edev)); + memset(fec, 0, sizeof(*fec)); + + ret = fec_alloc_descs(fec); + if (ret) + goto err3; + + edev->priv = fec; + edev->init = fec_init; + edev->send = fec_send; + edev->recv = fec_recv; + edev->halt = fec_halt; + edev->write_hwaddr = fec_set_hwaddr; + + fec->eth = (struct ethernet_regs *)base_addr; + fec->bd = bd; + + fec->xcv_type = CONFIG_FEC_XCV_TYPE; + + /* Reset chip. */ + writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl); + start = get_timer(0); + while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) { + if (get_timer(start) > (CONFIG_SYS_HZ * 5)) { + printf("FEC MXC: Timeout reseting chip\n"); + goto err4; + } + udelay(10); + } + + fec_reg_setup(fec); + fec_set_dev_name(edev->name, dev_id); + fec->dev_id = (dev_id == -1) ? 0 : dev_id; + fec->bus = bus; + fec_mii_setspeed(bus->priv); +#ifdef CONFIG_PHYLIB + fec->phydev = phydev; + phy_connect_dev(phydev, edev); + /* Configure phy */ + phy_config(phydev); +#else + fec->phy_id = phy_id; +#endif + eth_register(edev); + + if (fec_get_hwaddr(edev, dev_id, ethaddr) == 0) { + debug("got MAC%d address from fuse: %pM\n", dev_id, ethaddr); + memcpy(edev->enetaddr, ethaddr, 6); + if (!getenv("ethaddr")) + eth_setenv_enetaddr("ethaddr", ethaddr); + } + return ret; +err4: + fec_free_descs(fec); +err3: + free(fec); +err2: + free(edev); +err1: + return ret; +} + +struct mii_dev *fec_get_miibus(uint32_t base_addr, int dev_id) +{ + struct ethernet_regs *eth = (struct ethernet_regs *)base_addr; + struct mii_dev *bus; + int ret; + + bus = mdio_alloc(); + if (!bus) { + printf("mdio_alloc failed\n"); + return NULL; + } + bus->read = fec_phy_read; + bus->write = fec_phy_write; + bus->priv = eth; + fec_set_dev_name(bus->name, dev_id); + + ret = mdio_register(bus); + if (ret) { + printf("mdio_register failed\n"); + free(bus); + return NULL; + } + fec_mii_setspeed(eth); + return bus; +} + +int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr) +{ + uint32_t base_mii; + struct mii_dev *bus = NULL; +#ifdef CONFIG_PHYLIB + struct phy_device *phydev = NULL; +#endif + int ret; + +#ifdef CONFIG_MX28 + /* + * The i.MX28 has two ethernet interfaces, but they are not equal. + * Only the first one can access the MDIO bus. + */ + base_mii = MXS_ENET0_BASE; +#else + base_mii = addr; +#endif + debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr); + bus = fec_get_miibus(base_mii, dev_id); + if (!bus) + return -ENOMEM; +#ifdef CONFIG_PHYLIB + phydev = phy_find_by_mask(bus, 1 << phy_id, PHY_INTERFACE_MODE_RGMII); + if (!phydev) { + mdio_unregister(bus); + free(bus); + return -ENOMEM; + } + ret = fec_probe(bd, dev_id, addr, bus, phydev); +#else + ret = fec_probe(bd, dev_id, addr, bus, phy_id); +#endif + if (ret) { +#ifdef CONFIG_PHYLIB + free(phydev); +#endif + mdio_unregister(bus); + free(bus); + } + return ret; +} + +#ifdef CONFIG_FEC_MXC_PHYADDR +int fecmxc_initialize(bd_t *bd) +{ + return fecmxc_initialize_multi(bd, -1, CONFIG_FEC_MXC_PHYADDR, + IMX_FEC_BASE); +} +#endif + +#ifndef CONFIG_PHYLIB +int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int)) +{ + struct fec_priv *fec = (struct fec_priv *)dev->priv; + fec->mii_postcall = cb; + return 0; +} +#endif diff --git a/sources/uboot-be550/drivers/net/fec_mxc.h b/sources/uboot-be550/drivers/net/fec_mxc.h new file mode 100644 index 00000000..0717cc6c --- /dev/null +++ b/sources/uboot-be550/drivers/net/fec_mxc.h @@ -0,0 +1,323 @@ +/* + * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd + * (C) Copyright 2008 Armadeus Systems, nc + * (C) Copyright 2008 Eric Jarrige + * (C) Copyright 2007 Pengutronix, Sascha Hauer + * (C) Copyright 2007 Pengutronix, Juergen Beisert + * + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * This file is based on mpc4200fec.h + * (C) Copyright Motorola, Inc., 2000 + * + * SPDX-License-Identifier: GPL-2.0+ + */ + + +#ifndef __FEC_MXC_H +#define __FEC_MXC_H + +void imx_get_mac_from_fuse(int dev_id, unsigned char *mac); + +/** + * Layout description of the FEC + */ +struct ethernet_regs { + +/* [10:2]addr = 00 */ + +/* Control and status Registers (offset 000-1FF) */ + + uint32_t res0[1]; /* MBAR_ETH + 0x000 */ + uint32_t ievent; /* MBAR_ETH + 0x004 */ + uint32_t imask; /* MBAR_ETH + 0x008 */ + + uint32_t res1[1]; /* MBAR_ETH + 0x00C */ + uint32_t r_des_active; /* MBAR_ETH + 0x010 */ + uint32_t x_des_active; /* MBAR_ETH + 0x014 */ + uint32_t res2[3]; /* MBAR_ETH + 0x018-20 */ + uint32_t ecntrl; /* MBAR_ETH + 0x024 */ + + uint32_t res3[6]; /* MBAR_ETH + 0x028-03C */ + uint32_t mii_data; /* MBAR_ETH + 0x040 */ + uint32_t mii_speed; /* MBAR_ETH + 0x044 */ + uint32_t res4[7]; /* MBAR_ETH + 0x048-60 */ + uint32_t mib_control; /* MBAR_ETH + 0x064 */ + + uint32_t res5[7]; /* MBAR_ETH + 0x068-80 */ + uint32_t r_cntrl; /* MBAR_ETH + 0x084 */ + uint32_t res6[15]; /* MBAR_ETH + 0x088-C0 */ + uint32_t x_cntrl; /* MBAR_ETH + 0x0C4 */ + uint32_t res7[7]; /* MBAR_ETH + 0x0C8-E0 */ + uint32_t paddr1; /* MBAR_ETH + 0x0E4 */ + uint32_t paddr2; /* MBAR_ETH + 0x0E8 */ + uint32_t op_pause; /* MBAR_ETH + 0x0EC */ + + uint32_t res8[10]; /* MBAR_ETH + 0x0F0-114 */ + uint32_t iaddr1; /* MBAR_ETH + 0x118 */ + uint32_t iaddr2; /* MBAR_ETH + 0x11C */ + uint32_t gaddr1; /* MBAR_ETH + 0x120 */ + uint32_t gaddr2; /* MBAR_ETH + 0x124 */ + uint32_t res9[7]; /* MBAR_ETH + 0x128-140 */ + + uint32_t x_wmrk; /* MBAR_ETH + 0x144 */ + uint32_t res10[1]; /* MBAR_ETH + 0x148 */ + uint32_t r_bound; /* MBAR_ETH + 0x14C */ + uint32_t r_fstart; /* MBAR_ETH + 0x150 */ + uint32_t res11[11]; /* MBAR_ETH + 0x154-17C */ + uint32_t erdsr; /* MBAR_ETH + 0x180 */ + uint32_t etdsr; /* MBAR_ETH + 0x184 */ + uint32_t emrbr; /* MBAR_ETH + 0x188 */ + uint32_t res12[29]; /* MBAR_ETH + 0x18C-1FC */ + +/* MIB COUNTERS (Offset 200-2FF) */ + + uint32_t rmon_t_drop; /* MBAR_ETH + 0x200 */ + uint32_t rmon_t_packets; /* MBAR_ETH + 0x204 */ + uint32_t rmon_t_bc_pkt; /* MBAR_ETH + 0x208 */ + uint32_t rmon_t_mc_pkt; /* MBAR_ETH + 0x20C */ + uint32_t rmon_t_crc_align; /* MBAR_ETH + 0x210 */ + uint32_t rmon_t_undersize; /* MBAR_ETH + 0x214 */ + uint32_t rmon_t_oversize; /* MBAR_ETH + 0x218 */ + uint32_t rmon_t_frag; /* MBAR_ETH + 0x21C */ + uint32_t rmon_t_jab; /* MBAR_ETH + 0x220 */ + uint32_t rmon_t_col; /* MBAR_ETH + 0x224 */ + uint32_t rmon_t_p64; /* MBAR_ETH + 0x228 */ + uint32_t rmon_t_p65to127; /* MBAR_ETH + 0x22C */ + uint32_t rmon_t_p128to255; /* MBAR_ETH + 0x230 */ + uint32_t rmon_t_p256to511; /* MBAR_ETH + 0x234 */ + uint32_t rmon_t_p512to1023; /* MBAR_ETH + 0x238 */ + uint32_t rmon_t_p1024to2047; /* MBAR_ETH + 0x23C */ + uint32_t rmon_t_p_gte2048; /* MBAR_ETH + 0x240 */ + uint32_t rmon_t_octets; /* MBAR_ETH + 0x244 */ + uint32_t ieee_t_drop; /* MBAR_ETH + 0x248 */ + uint32_t ieee_t_frame_ok; /* MBAR_ETH + 0x24C */ + uint32_t ieee_t_1col; /* MBAR_ETH + 0x250 */ + uint32_t ieee_t_mcol; /* MBAR_ETH + 0x254 */ + uint32_t ieee_t_def; /* MBAR_ETH + 0x258 */ + uint32_t ieee_t_lcol; /* MBAR_ETH + 0x25C */ + uint32_t ieee_t_excol; /* MBAR_ETH + 0x260 */ + uint32_t ieee_t_macerr; /* MBAR_ETH + 0x264 */ + uint32_t ieee_t_cserr; /* MBAR_ETH + 0x268 */ + uint32_t ieee_t_sqe; /* MBAR_ETH + 0x26C */ + uint32_t t_fdxfc; /* MBAR_ETH + 0x270 */ + uint32_t ieee_t_octets_ok; /* MBAR_ETH + 0x274 */ + + uint32_t res13[2]; /* MBAR_ETH + 0x278-27C */ + uint32_t rmon_r_drop; /* MBAR_ETH + 0x280 */ + uint32_t rmon_r_packets; /* MBAR_ETH + 0x284 */ + uint32_t rmon_r_bc_pkt; /* MBAR_ETH + 0x288 */ + uint32_t rmon_r_mc_pkt; /* MBAR_ETH + 0x28C */ + uint32_t rmon_r_crc_align; /* MBAR_ETH + 0x290 */ + uint32_t rmon_r_undersize; /* MBAR_ETH + 0x294 */ + uint32_t rmon_r_oversize; /* MBAR_ETH + 0x298 */ + uint32_t rmon_r_frag; /* MBAR_ETH + 0x29C */ + uint32_t rmon_r_jab; /* MBAR_ETH + 0x2A0 */ + + uint32_t rmon_r_resvd_0; /* MBAR_ETH + 0x2A4 */ + + uint32_t rmon_r_p64; /* MBAR_ETH + 0x2A8 */ + uint32_t rmon_r_p65to127; /* MBAR_ETH + 0x2AC */ + uint32_t rmon_r_p128to255; /* MBAR_ETH + 0x2B0 */ + uint32_t rmon_r_p256to511; /* MBAR_ETH + 0x2B4 */ + uint32_t rmon_r_p512to1023; /* MBAR_ETH + 0x2B8 */ + uint32_t rmon_r_p1024to2047; /* MBAR_ETH + 0x2BC */ + uint32_t rmon_r_p_gte2048; /* MBAR_ETH + 0x2C0 */ + uint32_t rmon_r_octets; /* MBAR_ETH + 0x2C4 */ + uint32_t ieee_r_drop; /* MBAR_ETH + 0x2C8 */ + uint32_t ieee_r_frame_ok; /* MBAR_ETH + 0x2CC */ + uint32_t ieee_r_crc; /* MBAR_ETH + 0x2D0 */ + uint32_t ieee_r_align; /* MBAR_ETH + 0x2D4 */ + uint32_t r_macerr; /* MBAR_ETH + 0x2D8 */ + uint32_t r_fdxfc; /* MBAR_ETH + 0x2DC */ + uint32_t ieee_r_octets_ok; /* MBAR_ETH + 0x2E0 */ + + uint32_t res14[7]; /* MBAR_ETH + 0x2E4-2FC */ + +#if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL) + uint16_t miigsk_cfgr; /* MBAR_ETH + 0x300 */ + uint16_t res15[3]; /* MBAR_ETH + 0x302-306 */ + uint16_t miigsk_enr; /* MBAR_ETH + 0x308 */ + uint16_t res16[3]; /* MBAR_ETH + 0x30a-30e */ + uint32_t res17[60]; /* MBAR_ETH + 0x300-3FF */ +#else + uint32_t res15[64]; /* MBAR_ETH + 0x300-3FF */ +#endif +}; + +#define FEC_IEVENT_HBERR 0x80000000 +#define FEC_IEVENT_BABR 0x40000000 +#define FEC_IEVENT_BABT 0x20000000 +#define FEC_IEVENT_GRA 0x10000000 +#define FEC_IEVENT_TXF 0x08000000 +#define FEC_IEVENT_TXB 0x04000000 +#define FEC_IEVENT_RXF 0x02000000 +#define FEC_IEVENT_RXB 0x01000000 +#define FEC_IEVENT_MII 0x00800000 +#define FEC_IEVENT_EBERR 0x00400000 +#define FEC_IEVENT_LC 0x00200000 +#define FEC_IEVENT_RL 0x00100000 +#define FEC_IEVENT_UN 0x00080000 + +#define FEC_IMASK_HBERR 0x80000000 +#define FEC_IMASK_BABR 0x40000000 +#define FEC_IMASKT_BABT 0x20000000 +#define FEC_IMASK_GRA 0x10000000 +#define FEC_IMASKT_TXF 0x08000000 +#define FEC_IMASK_TXB 0x04000000 +#define FEC_IMASKT_RXF 0x02000000 +#define FEC_IMASK_RXB 0x01000000 +#define FEC_IMASK_MII 0x00800000 +#define FEC_IMASK_EBERR 0x00400000 +#define FEC_IMASK_LC 0x00200000 +#define FEC_IMASKT_RL 0x00100000 +#define FEC_IMASK_UN 0x00080000 + + +#define FEC_RCNTRL_MAX_FL_SHIFT 16 +#define FEC_RCNTRL_LOOP 0x00000001 +#define FEC_RCNTRL_DRT 0x00000002 +#define FEC_RCNTRL_MII_MODE 0x00000004 +#define FEC_RCNTRL_PROM 0x00000008 +#define FEC_RCNTRL_BC_REJ 0x00000010 +#define FEC_RCNTRL_FCE 0x00000020 +#define FEC_RCNTRL_RGMII 0x00000040 +#define FEC_RCNTRL_RMII 0x00000100 +#define FEC_RCNTRL_RMII_10T 0x00000200 + +#define FEC_TCNTRL_GTS 0x00000001 +#define FEC_TCNTRL_HBC 0x00000002 +#define FEC_TCNTRL_FDEN 0x00000004 +#define FEC_TCNTRL_TFC_PAUSE 0x00000008 +#define FEC_TCNTRL_RFC_PAUSE 0x00000010 + +#define FEC_ECNTRL_RESET 0x00000001 /* reset the FEC */ +#define FEC_ECNTRL_ETHER_EN 0x00000002 /* enable the FEC */ +#define FEC_ECNTRL_SPEED 0x00000020 +#define FEC_ECNTRL_DBSWAP 0x00000100 + +#define FEC_X_WMRK_STRFWD 0x00000100 + +#define FEC_X_DES_ACTIVE_TDAR 0x01000000 +#define FEC_R_DES_ACTIVE_RDAR 0x01000000 + +#if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL) +/* defines for MIIGSK */ +/* RMII frequency control: 0=50MHz, 1=5MHz */ +#define MIIGSK_CFGR_FRCONT (1 << 6) +/* loopback mode */ +#define MIIGSK_CFGR_LBMODE (1 << 4) +/* echo mode */ +#define MIIGSK_CFGR_EMODE (1 << 3) +/* MII gasket mode field */ +#define MIIGSK_CFGR_IF_MODE_MASK (3 << 0) +/* MMI/7-Wire mode */ +#define MIIGSK_CFGR_IF_MODE_MII (0 << 0) +/* RMII mode */ +#define MIIGSK_CFGR_IF_MODE_RMII (1 << 0) +/* reflects MIIGSK Enable bit (RO) */ +#define MIIGSK_ENR_READY (1 << 2) +/* enable MIGSK (set by default) */ +#define MIIGSK_ENR_EN (1 << 1) +#endif + +/** + * @brief Receive & Transmit Buffer Descriptor definitions + * + * Note: The first BD must be aligned (see DB_ALIGNMENT) + */ +struct fec_bd { + uint16_t data_length; /* payload's length in bytes */ + uint16_t status; /* BD's staus (see datasheet) */ + uint32_t data_pointer; /* payload's buffer address */ +}; + +/** + * Supported phy types on this platform + */ +enum xceiver_type { + SEVENWIRE, /* 7-wire */ + MII10, /* MII 10Mbps */ + MII100, /* MII 100Mbps */ + RMII, /* RMII */ + RGMII, /* RGMII */ +}; + +/** + * @brief i.MX27-FEC private structure + */ +struct fec_priv { + struct ethernet_regs *eth; /* pointer to register'S base */ + enum xceiver_type xcv_type; /* transceiver type */ + struct fec_bd *rbd_base; /* RBD ring */ + int rbd_index; /* next receive BD to read */ + struct fec_bd *tbd_base; /* TBD ring */ + int tbd_index; /* next transmit BD to write */ + bd_t *bd; + uint8_t *tdb_ptr; + int dev_id; + struct mii_dev *bus; +#ifdef CONFIG_PHYLIB + struct phy_device *phydev; +#else + int phy_id; + int (*mii_postcall)(int); +#endif +}; + +/** + * @brief Numbers of buffer descriptors for receiving + * + * The number defines the stocked memory buffers for the receiving task. + * Larger values makes no sense in this limited environment. + */ +#define FEC_RBD_NUM 64 + +/** + * @brief Define the ethernet packet size limit in memory + * + * Note: Do not shrink this number. This will force the FEC to spread larger + * frames in more than one BD. This is nothing to worry about, but the current + * driver can't handle it. + */ +#define FEC_MAX_PKT_SIZE 1536 + +/* Receive BD status bits */ +#define FEC_RBD_EMPTY 0x8000 /* Receive BD status: Buffer is empty */ +#define FEC_RBD_WRAP 0x2000 /* Receive BD status: Last BD in ring */ +/* Receive BD status: Buffer is last in frame (useless here!) */ +#define FEC_RBD_LAST 0x0800 +#define FEC_RBD_MISS 0x0100 /* Receive BD status: Miss bit for prom mode */ +/* Receive BD status: The received frame is broadcast frame */ +#define FEC_RBD_BC 0x0080 +/* Receive BD status: The received frame is multicast frame */ +#define FEC_RBD_MC 0x0040 +#define FEC_RBD_LG 0x0020 /* Receive BD status: Frame length violation */ +#define FEC_RBD_NO 0x0010 /* Receive BD status: Nonoctet align frame */ +#define FEC_RBD_CR 0x0004 /* Receive BD status: CRC error */ +#define FEC_RBD_OV 0x0002 /* Receive BD status: Receive FIFO overrun */ +#define FEC_RBD_TR 0x0001 /* Receive BD status: Frame is truncated */ +#define FEC_RBD_ERR (FEC_RBD_LG | FEC_RBD_NO | FEC_RBD_CR | \ + FEC_RBD_OV | FEC_RBD_TR) + +/* Transmit BD status bits */ +#define FEC_TBD_READY 0x8000 /* Tansmit BD status: Buffer is ready */ +#define FEC_TBD_WRAP 0x2000 /* Tansmit BD status: Mark as last BD in ring */ +#define FEC_TBD_LAST 0x0800 /* Tansmit BD status: Buffer is last in frame */ +#define FEC_TBD_TC 0x0400 /* Tansmit BD status: Transmit the CRC */ +#define FEC_TBD_ABC 0x0200 /* Tansmit BD status: Append bad CRC */ + +/* MII-related definitios */ +#define FEC_MII_DATA_ST 0x40000000 /* Start of frame delimiter */ +#define FEC_MII_DATA_OP_RD 0x20000000 /* Perform a read operation */ +#define FEC_MII_DATA_OP_WR 0x10000000 /* Perform a write operation */ +#define FEC_MII_DATA_PA_MSK 0x0f800000 /* PHY Address field mask */ +#define FEC_MII_DATA_RA_MSK 0x007c0000 /* PHY Register field mask */ +#define FEC_MII_DATA_TA 0x00020000 /* Turnaround */ +#define FEC_MII_DATA_DATAMSK 0x0000ffff /* PHY data field */ + +#define FEC_MII_DATA_RA_SHIFT 18 /* MII Register address bits */ +#define FEC_MII_DATA_PA_SHIFT 23 /* MII PHY address bits */ + +#endif /* __FEC_MXC_H */ diff --git a/sources/uboot-be550/drivers/net/fm/Makefile b/sources/uboot-be550/drivers/net/fm/Makefile new file mode 100644 index 00000000..a3c9f996 --- /dev/null +++ b/sources/uboot-be550/drivers/net/fm/Makefile @@ -0,0 +1,40 @@ +# +# Copyright 2009-2011 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += dtsec.o +obj-y += eth.o +obj-y += fm.o +obj-y += init.o +obj-y += tgec.o +obj-y += tgec_phy.o + +# Soc have FMAN v3 with mEMAC +obj-$(CONFIG_SYS_FMAN_V3) += memac_phy.o +obj-$(CONFIG_SYS_FMAN_V3) += memac.o + +# SoC specific SERDES support +obj-$(CONFIG_P1017) += p1023.o +obj-$(CONFIG_P1023) += p1023.o +# The P204x, P304x, and P5020 are the same +obj-$(CONFIG_PPC_P2041) += p5020.o +obj-$(CONFIG_PPC_P3041) += p5020.o +obj-$(CONFIG_PPC_P4080) += p4080.o +obj-$(CONFIG_PPC_P5020) += p5020.o +obj-$(CONFIG_PPC_P5040) += p5040.o +obj-$(CONFIG_PPC_T1040) += t1040.o +obj-$(CONFIG_PPC_T1042) += t1040.o +obj-$(CONFIG_PPC_T1020) += t1040.o +obj-$(CONFIG_PPC_T1022) += t1040.o +obj-$(CONFIG_PPC_T1023) += t1024.o +obj-$(CONFIG_PPC_T1024) += t1024.o +obj-$(CONFIG_PPC_T2080) += t2080.o +obj-$(CONFIG_PPC_T2081) += t2080.o +obj-$(CONFIG_PPC_T4240) += t4240.o +obj-$(CONFIG_PPC_T4160) += t4240.o +obj-$(CONFIG_PPC_T4080) += t4240.o +obj-$(CONFIG_PPC_B4420) += b4860.o +obj-$(CONFIG_PPC_B4860) += b4860.o +obj-$(CONFIG_LS1043A) += ls1043.o diff --git a/sources/uboot-be550/drivers/net/fm/b4860.c b/sources/uboot-be550/drivers/net/fm/b4860.c new file mode 100644 index 00000000..eb058c9c --- /dev/null +++ b/sources/uboot-be550/drivers/net/fm/b4860.c @@ -0,0 +1,137 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * Roy Zang + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include +#include +#include + +u32 port_to_devdisr[] = { + [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1, + [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2, + [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3, + [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4, + [FM1_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC1_5, + [FM1_DTSEC6] = FSL_CORENET_DEVDISR2_DTSEC1_6, + [FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1_1, + [FM1_10GEC2] = FSL_CORENET_DEVDISR2_10GEC1_2, +}; + +static int is_device_disabled(enum fm_port port) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 devdisr2 = in_be32(&gur->devdisr2); + + return port_to_devdisr[port] & devdisr2; +} + +void fman_disable_port(enum fm_port port) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + setbits_be32(&gur->devdisr2, port_to_devdisr[port]); +} + +void fman_enable_port(enum fm_port port) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + clrbits_be32(&gur->devdisr2, port_to_devdisr[port]); +} + +phy_interface_t fman_port_enet_if(enum fm_port port) +{ +#if defined(CONFIG_B4860QDS) + u32 serdes2_prtcl; + char buffer[HWCONFIG_BUFFER_SIZE]; + char *buf = NULL; + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); +#endif + + if (is_device_disabled(port)) + return PHY_INTERFACE_MODE_NONE; + + /*B4860 has two 10Gig Mac*/ + if ((port == FM1_10GEC1 || port == FM1_10GEC2) && + ((is_serdes_configured(XAUI_FM1_MAC9)) || + #if !defined(CONFIG_B4860QDS) + (is_serdes_configured(XFI_FM1_MAC9)) || + (is_serdes_configured(XFI_FM1_MAC10)) || + #endif + (is_serdes_configured(XAUI_FM1_MAC10)) + )) + return PHY_INTERFACE_MODE_XGMII; + +#if defined(CONFIG_B4860QDS) + serdes2_prtcl = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS2_PRTCL; + + if (serdes2_prtcl) { + serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; + switch (serdes2_prtcl) { + case 0x80: + case 0x81: + case 0x82: + case 0x83: + case 0x84: + case 0x85: + case 0x86: + case 0x87: + case 0x88: + case 0x89: + case 0x8a: + case 0x8b: + case 0x8c: + case 0x8d: + case 0x8e: + case 0xb1: + case 0xb2: + /* + * Extract hwconfig from environment since environment + * is not setup yet + */ + getenv_f("hwconfig", buffer, sizeof(buffer)); + buf = buffer; + + /* check if XFI interface enable in hwconfig for 10g */ + if (hwconfig_subarg_cmp_f("fsl_b4860_serdes2", + "sfp_amc", "sfp", buf)) { + if ((port == FM1_10GEC1 || + port == FM1_10GEC2) && + ((is_serdes_configured(XFI_FM1_MAC9)) || + (is_serdes_configured(XFI_FM1_MAC10)))) + return PHY_INTERFACE_MODE_XGMII; + else if ((port == FM1_DTSEC1) || + (port == FM1_DTSEC2) || + (port == FM1_DTSEC3) || + (port == FM1_DTSEC4)) + return PHY_INTERFACE_MODE_NONE; + } + } + } +#endif + + /* Fix me need to handle RGMII here first */ + + switch (port) { + case FM1_DTSEC1: + case FM1_DTSEC2: + case FM1_DTSEC3: + case FM1_DTSEC4: + case FM1_DTSEC5: + case FM1_DTSEC6: + if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1)) + return PHY_INTERFACE_MODE_SGMII; + break; + default: + return PHY_INTERFACE_MODE_NONE; + } + + return PHY_INTERFACE_MODE_NONE; +} diff --git a/sources/uboot-be550/drivers/net/fm/dtsec.c b/sources/uboot-be550/drivers/net/fm/dtsec.c new file mode 100644 index 00000000..b339a84e --- /dev/null +++ b/sources/uboot-be550/drivers/net/fm/dtsec.c @@ -0,0 +1,167 @@ +/* + * Copyright 2009-2011 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +#include "fm.h" + +#define RCTRL_INIT (RCTRL_GRS | RCTRL_UPROM) +#define TCTRL_INIT TCTRL_GTS +#define MACCFG1_INIT MACCFG1_SOFT_RST + +#define MACCFG2_INIT (MACCFG2_PRE_LEN(0x7) | MACCFG2_LEN_CHECK | \ + MACCFG2_PAD_CRC | MACCFG2_FULL_DUPLEX | \ + MACCFG2_IF_MODE_NIBBLE) + +/* MAXFRM - maximum frame length register */ +#define MAXFRM_MASK 0x00003fff + +static void dtsec_init_mac(struct fsl_enet_mac *mac) +{ + struct dtsec *regs = mac->base; + + /* soft reset */ + out_be32(®s->maccfg1, MACCFG1_SOFT_RST); + udelay(1000); + + /* clear soft reset, Rx/Tx MAC disable */ + out_be32(®s->maccfg1, 0); + + /* graceful stop rx */ + out_be32(®s->rctrl, RCTRL_INIT); + udelay(1000); + + /* graceful stop tx */ + out_be32(®s->tctrl, TCTRL_INIT); + udelay(1000); + + /* disable all interrupts */ + out_be32(®s->imask, IMASK_MASK_ALL); + + /* clear all events */ + out_be32(®s->ievent, IEVENT_CLEAR_ALL); + + /* set the max Rx length */ + out_be32(®s->maxfrm, mac->max_rx_len & MAXFRM_MASK); + + /* set the ecntrl to reset value */ + out_be32(®s->ecntrl, ECNTRL_DEFAULT); + + /* + * Rx length check, no strip CRC for Rx, pad and append CRC for Tx, + * full duplex + */ + out_be32(®s->maccfg2, MACCFG2_INIT); +} + +static void dtsec_enable_mac(struct fsl_enet_mac *mac) +{ + struct dtsec *regs = mac->base; + + /* enable Rx/Tx MAC */ + setbits_be32(®s->maccfg1, MACCFG1_RXTX_EN); + + /* clear the graceful Rx stop */ + clrbits_be32(®s->rctrl, RCTRL_GRS); + + /* clear the graceful Tx stop */ + clrbits_be32(®s->tctrl, TCTRL_GTS); +} + +static void dtsec_disable_mac(struct fsl_enet_mac *mac) +{ + struct dtsec *regs = mac->base; + + /* graceful Rx stop */ + setbits_be32(®s->rctrl, RCTRL_GRS); + + /* graceful Tx stop */ + setbits_be32(®s->tctrl, TCTRL_GTS); + + /* disable Rx/Tx MAC */ + clrbits_be32(®s->maccfg1, MACCFG1_RXTX_EN); +} + +static void dtsec_set_mac_addr(struct fsl_enet_mac *mac, u8 *mac_addr) +{ + struct dtsec *regs = mac->base; + u32 mac_addr1, mac_addr2; + + /* + * if a station address of 0x12345678ABCD, perform a write to + * MACSTNADDR1 of 0xCDAB7856, MACSTNADDR2 of 0x34120000 + */ + mac_addr1 = (mac_addr[5] << 24) | (mac_addr[4] << 16) | \ + (mac_addr[3] << 8) | (mac_addr[2]); + out_be32(®s->macstnaddr1, mac_addr1); + + mac_addr2 = ((mac_addr[1] << 24) | (mac_addr[0] << 16)) & 0xffff0000; + out_be32(®s->macstnaddr2, mac_addr2); +} + +static void dtsec_set_interface_mode(struct fsl_enet_mac *mac, + phy_interface_t type, int speed) +{ + struct dtsec *regs = mac->base; + u32 ecntrl, maccfg2; + + /* clear all bits relative with interface mode */ + ecntrl = in_be32(®s->ecntrl); + ecntrl &= ~(ECNTRL_TBIM | ECNTRL_GMIIM | ECNTRL_RPM | + ECNTRL_R100M | ECNTRL_SGMIIM); + + maccfg2 = in_be32(®s->maccfg2); + maccfg2 &= ~MACCFG2_IF_MODE_MASK; + + if (speed == SPEED_1000) + maccfg2 |= MACCFG2_IF_MODE_BYTE; + else + maccfg2 |= MACCFG2_IF_MODE_NIBBLE; + + /* set interface mode */ + switch (type) { + case PHY_INTERFACE_MODE_GMII: + ecntrl |= ECNTRL_GMIIM; + break; + case PHY_INTERFACE_MODE_RGMII: + ecntrl |= (ECNTRL_GMIIM | ECNTRL_RPM); + if (speed == SPEED_100) + ecntrl |= ECNTRL_R100M; + break; + case PHY_INTERFACE_MODE_RMII: + if (speed == SPEED_100) + ecntrl |= ECNTRL_R100M; + break; + case PHY_INTERFACE_MODE_SGMII: + ecntrl |= (ECNTRL_SGMIIM | ECNTRL_TBIM); + if (speed == SPEED_100) + ecntrl |= ECNTRL_R100M; + break; + default: + break; + } + + out_be32(®s->ecntrl, ecntrl); + out_be32(®s->maccfg2, maccfg2); +} + +void init_dtsec(struct fsl_enet_mac *mac, void *base, + void *phyregs, int max_rx_len) +{ + mac->base = base; + mac->phyregs = phyregs; + mac->max_rx_len = max_rx_len; + mac->init_mac = dtsec_init_mac; + mac->enable_mac = dtsec_enable_mac; + mac->disable_mac = dtsec_disable_mac; + mac->set_mac_addr = dtsec_set_mac_addr; + mac->set_if_mode = dtsec_set_interface_mode; +} diff --git a/sources/uboot-be550/drivers/net/fm/eth.c b/sources/uboot-be550/drivers/net/fm/eth.c new file mode 100644 index 00000000..eb8e9361 --- /dev/null +++ b/sources/uboot-be550/drivers/net/fm/eth.c @@ -0,0 +1,783 @@ +/* + * Copyright 2009-2012 Freescale Semiconductor, Inc. + * Dave Liu + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "fm.h" + +static struct eth_device *devlist[NUM_FM_PORTS]; +static int num_controllers; + +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) && !defined(BITBANGMII) + +#define TBIANA_SETTINGS (TBIANA_ASYMMETRIC_PAUSE | TBIANA_SYMMETRIC_PAUSE | \ + TBIANA_FULL_DUPLEX) + +#define TBIANA_SGMII_ACK 0x4001 + +#define TBICR_SETTINGS (TBICR_ANEG_ENABLE | TBICR_RESTART_ANEG | \ + TBICR_FULL_DUPLEX | TBICR_SPEED1_SET) + +/* Configure the TBI for SGMII operation */ +static void dtsec_configure_serdes(struct fm_eth *priv) +{ +#ifdef CONFIG_SYS_FMAN_V3 + u32 value; + struct mii_dev bus; + bus.priv = priv->mac->phyregs; + bool sgmii_2500 = (priv->enet_if == + PHY_INTERFACE_MODE_SGMII_2500) ? true : false; + int i = 0; + +qsgmii_loop: + /* SGMII IF mode + AN enable only for 1G SGMII, not for 2.5G */ + value = PHY_SGMII_IF_MODE_SGMII; + if (!sgmii_2500) + value |= PHY_SGMII_IF_MODE_AN; + + memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x14, value); + + /* Dev ability according to SGMII specification */ + value = PHY_SGMII_DEV_ABILITY_SGMII; + memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x4, value); + + /* Adjust link timer for SGMII - + 1.6 ms in units of 8 ns = 2 * 10^5 = 0x30d40 */ + memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x13, 0x3); + memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x12, 0xd40); + + /* Restart AN */ + value = PHY_SGMII_CR_DEF_VAL; + if (!sgmii_2500) + value |= PHY_SGMII_CR_RESET_AN; + memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0, value); + + if ((priv->enet_if == PHY_INTERFACE_MODE_QSGMII) && (i < 3)) { + i++; + goto qsgmii_loop; + } +#else + struct dtsec *regs = priv->mac->base; + struct tsec_mii_mng *phyregs = priv->mac->phyregs; + + /* + * Access TBI PHY registers at given TSEC register offset as + * opposed to the register offset used for external PHY accesses + */ + tsec_local_mdio_write(phyregs, in_be32(®s->tbipa), 0, TBI_TBICON, + TBICON_CLK_SELECT); + tsec_local_mdio_write(phyregs, in_be32(®s->tbipa), 0, TBI_ANA, + TBIANA_SGMII_ACK); + tsec_local_mdio_write(phyregs, in_be32(®s->tbipa), 0, + TBI_CR, TBICR_SETTINGS); +#endif +} + +static void dtsec_init_phy(struct eth_device *dev) +{ + struct fm_eth *fm_eth = dev->priv; +#ifndef CONFIG_SYS_FMAN_V3 + struct dtsec *regs = (struct dtsec *)CONFIG_SYS_FSL_FM1_DTSEC1_ADDR; + + /* Assign a Physical address to the TBI */ + out_be32(®s->tbipa, CONFIG_SYS_TBIPA_VALUE); +#endif + + if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII || + fm_eth->enet_if == PHY_INTERFACE_MODE_QSGMII || + fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500) + dtsec_configure_serdes(fm_eth); +} + +#ifdef CONFIG_PHYLIB +static int tgec_is_fibre(struct eth_device *dev) +{ + struct fm_eth *fm = dev->priv; + char phyopt[20]; + + sprintf(phyopt, "fsl_fm%d_xaui_phy", fm->fm_index + 1); + + return hwconfig_arg_cmp(phyopt, "xfi"); +} +#endif +#endif + +static u16 muram_readw(u16 *addr) +{ + ulong base = (ulong)addr & ~0x3UL; + u32 val32 = in_be32((void *)base); + int byte_pos; + u16 ret; + + byte_pos = (ulong)addr & 0x3UL; + if (byte_pos) + ret = (u16)(val32 & 0x0000ffff); + else + ret = (u16)((val32 & 0xffff0000) >> 16); + + return ret; +} + +static void muram_writew(u16 *addr, u16 val) +{ + ulong base = (ulong)addr & ~0x3UL; + u32 org32 = in_be32((void *)base); + u32 val32; + int byte_pos; + + byte_pos = (ulong)addr & 0x3UL; + if (byte_pos) + val32 = (org32 & 0xffff0000) | val; + else + val32 = (org32 & 0x0000ffff) | ((u32)val << 16); + + out_be32((void *)base, val32); +} + +static void bmi_rx_port_disable(struct fm_bmi_rx_port *rx_port) +{ + int timeout = 1000000; + + clrbits_be32(&rx_port->fmbm_rcfg, FMBM_RCFG_EN); + + /* wait until the rx port is not busy */ + while ((in_be32(&rx_port->fmbm_rst) & FMBM_RST_BSY) && timeout--) + ; +} + +static void bmi_rx_port_init(struct fm_bmi_rx_port *rx_port) +{ + /* set BMI to independent mode, Rx port disable */ + out_be32(&rx_port->fmbm_rcfg, FMBM_RCFG_IM); + /* clear FOF in IM case */ + out_be32(&rx_port->fmbm_rim, 0); + /* Rx frame next engine -RISC */ + out_be32(&rx_port->fmbm_rfne, NIA_ENG_RISC | NIA_RISC_AC_IM_RX); + /* Rx command attribute - no order, MR[3] = 1 */ + clrbits_be32(&rx_port->fmbm_rfca, FMBM_RFCA_ORDER | FMBM_RFCA_MR_MASK); + setbits_be32(&rx_port->fmbm_rfca, FMBM_RFCA_MR(4)); + /* enable Rx statistic counters */ + out_be32(&rx_port->fmbm_rstc, FMBM_RSTC_EN); + /* disable Rx performance counters */ + out_be32(&rx_port->fmbm_rpc, 0); +} + +static void bmi_tx_port_disable(struct fm_bmi_tx_port *tx_port) +{ + int timeout = 1000000; + + clrbits_be32(&tx_port->fmbm_tcfg, FMBM_TCFG_EN); + + /* wait until the tx port is not busy */ + while ((in_be32(&tx_port->fmbm_tst) & FMBM_TST_BSY) && timeout--) + ; +} + +static void bmi_tx_port_init(struct fm_bmi_tx_port *tx_port) +{ + /* set BMI to independent mode, Tx port disable */ + out_be32(&tx_port->fmbm_tcfg, FMBM_TCFG_IM); + /* Tx frame next engine -RISC */ + out_be32(&tx_port->fmbm_tfne, NIA_ENG_RISC | NIA_RISC_AC_IM_TX); + out_be32(&tx_port->fmbm_tfene, NIA_ENG_RISC | NIA_RISC_AC_IM_TX); + /* Tx command attribute - no order, MR[3] = 1 */ + clrbits_be32(&tx_port->fmbm_tfca, FMBM_TFCA_ORDER | FMBM_TFCA_MR_MASK); + setbits_be32(&tx_port->fmbm_tfca, FMBM_TFCA_MR(4)); + /* enable Tx statistic counters */ + out_be32(&tx_port->fmbm_tstc, FMBM_TSTC_EN); + /* disable Tx performance counters */ + out_be32(&tx_port->fmbm_tpc, 0); +} + +static int fm_eth_rx_port_parameter_init(struct fm_eth *fm_eth) +{ + struct fm_port_global_pram *pram; + u32 pram_page_offset; + void *rx_bd_ring_base; + void *rx_buf_pool; + u32 bd_ring_base_lo, bd_ring_base_hi; + u32 buf_lo, buf_hi; + struct fm_port_bd *rxbd; + struct fm_port_qd *rxqd; + struct fm_bmi_rx_port *bmi_rx_port = fm_eth->rx_port; + int i; + + /* alloc global parameter ram at MURAM */ + pram = (struct fm_port_global_pram *)fm_muram_alloc(fm_eth->fm_index, + FM_PRAM_SIZE, FM_PRAM_ALIGN); + if (!pram) { + printf("%s: No muram for Rx global parameter\n", __func__); + return -ENOMEM; + } + + fm_eth->rx_pram = pram; + + /* parameter page offset to MURAM */ + pram_page_offset = (void *)pram - fm_muram_base(fm_eth->fm_index); + + /* enable global mode- snooping data buffers and BDs */ + out_be32(&pram->mode, PRAM_MODE_GLOBAL); + + /* init the Rx queue descriptor pionter */ + out_be32(&pram->rxqd_ptr, pram_page_offset + 0x20); + + /* set the max receive buffer length, power of 2 */ + muram_writew(&pram->mrblr, MAX_RXBUF_LOG2); + + /* alloc Rx buffer descriptors from main memory */ + rx_bd_ring_base = malloc(sizeof(struct fm_port_bd) + * RX_BD_RING_SIZE); + if (!rx_bd_ring_base) + return -ENOMEM; + + memset(rx_bd_ring_base, 0, sizeof(struct fm_port_bd) + * RX_BD_RING_SIZE); + + /* alloc Rx buffer from main memory */ + rx_buf_pool = malloc(MAX_RXBUF_LEN * RX_BD_RING_SIZE); + if (!rx_buf_pool) + return -ENOMEM; + + memset(rx_buf_pool, 0, MAX_RXBUF_LEN * RX_BD_RING_SIZE); + debug("%s: rx_buf_pool = %p\n", __func__, rx_buf_pool); + + /* save them to fm_eth */ + fm_eth->rx_bd_ring = rx_bd_ring_base; + fm_eth->cur_rxbd = rx_bd_ring_base; + fm_eth->rx_buf = rx_buf_pool; + + /* init Rx BDs ring */ + rxbd = (struct fm_port_bd *)rx_bd_ring_base; + for (i = 0; i < RX_BD_RING_SIZE; i++) { + muram_writew(&rxbd->status, RxBD_EMPTY); + muram_writew(&rxbd->len, 0); + buf_hi = upper_32_bits(virt_to_phys(rx_buf_pool + + i * MAX_RXBUF_LEN)); + buf_lo = lower_32_bits(virt_to_phys(rx_buf_pool + + i * MAX_RXBUF_LEN)); + muram_writew(&rxbd->buf_ptr_hi, (u16)buf_hi); + out_be32(&rxbd->buf_ptr_lo, buf_lo); + rxbd++; + } + + /* set the Rx queue descriptor */ + rxqd = &pram->rxqd; + muram_writew(&rxqd->gen, 0); + bd_ring_base_hi = upper_32_bits(virt_to_phys(rx_bd_ring_base)); + bd_ring_base_lo = lower_32_bits(virt_to_phys(rx_bd_ring_base)); + muram_writew(&rxqd->bd_ring_base_hi, (u16)bd_ring_base_hi); + out_be32(&rxqd->bd_ring_base_lo, bd_ring_base_lo); + muram_writew(&rxqd->bd_ring_size, sizeof(struct fm_port_bd) + * RX_BD_RING_SIZE); + muram_writew(&rxqd->offset_in, 0); + muram_writew(&rxqd->offset_out, 0); + + /* set IM parameter ram pointer to Rx Frame Queue ID */ + out_be32(&bmi_rx_port->fmbm_rfqid, pram_page_offset); + + return 0; +} + +static int fm_eth_tx_port_parameter_init(struct fm_eth *fm_eth) +{ + struct fm_port_global_pram *pram; + u32 pram_page_offset; + void *tx_bd_ring_base; + u32 bd_ring_base_lo, bd_ring_base_hi; + struct fm_port_bd *txbd; + struct fm_port_qd *txqd; + struct fm_bmi_tx_port *bmi_tx_port = fm_eth->tx_port; + int i; + + /* alloc global parameter ram at MURAM */ + pram = (struct fm_port_global_pram *)fm_muram_alloc(fm_eth->fm_index, + FM_PRAM_SIZE, FM_PRAM_ALIGN); + if (!pram) { + printf("%s: No muram for Tx global parameter\n", __func__); + return -ENOMEM; + } + fm_eth->tx_pram = pram; + + /* parameter page offset to MURAM */ + pram_page_offset = (void *)pram - fm_muram_base(fm_eth->fm_index); + + /* enable global mode- snooping data buffers and BDs */ + out_be32(&pram->mode, PRAM_MODE_GLOBAL); + + /* init the Tx queue descriptor pionter */ + out_be32(&pram->txqd_ptr, pram_page_offset + 0x40); + + /* alloc Tx buffer descriptors from main memory */ + tx_bd_ring_base = malloc(sizeof(struct fm_port_bd) + * TX_BD_RING_SIZE); + if (!tx_bd_ring_base) + return -ENOMEM; + + memset(tx_bd_ring_base, 0, sizeof(struct fm_port_bd) + * TX_BD_RING_SIZE); + /* save it to fm_eth */ + fm_eth->tx_bd_ring = tx_bd_ring_base; + fm_eth->cur_txbd = tx_bd_ring_base; + + /* init Tx BDs ring */ + txbd = (struct fm_port_bd *)tx_bd_ring_base; + for (i = 0; i < TX_BD_RING_SIZE; i++) { + muram_writew(&txbd->status, TxBD_LAST); + muram_writew(&txbd->len, 0); + muram_writew(&txbd->buf_ptr_hi, 0); + out_be32(&txbd->buf_ptr_lo, 0); + txbd++; + } + + /* set the Tx queue decriptor */ + txqd = &pram->txqd; + bd_ring_base_hi = upper_32_bits(virt_to_phys(tx_bd_ring_base)); + bd_ring_base_lo = lower_32_bits(virt_to_phys(tx_bd_ring_base)); + muram_writew(&txqd->bd_ring_base_hi, (u16)bd_ring_base_hi); + out_be32(&txqd->bd_ring_base_lo, bd_ring_base_lo); + muram_writew(&txqd->bd_ring_size, sizeof(struct fm_port_bd) + * TX_BD_RING_SIZE); + muram_writew(&txqd->offset_in, 0); + muram_writew(&txqd->offset_out, 0); + + /* set IM parameter ram pointer to Tx Confirmation Frame Queue ID */ + out_be32(&bmi_tx_port->fmbm_tcfqid, pram_page_offset); + + return 0; +} + +static int fm_eth_init(struct fm_eth *fm_eth) +{ + int ret; + + ret = fm_eth_rx_port_parameter_init(fm_eth); + if (ret) + return ret; + + ret = fm_eth_tx_port_parameter_init(fm_eth); + if (ret) + return ret; + + return 0; +} + +static int fm_eth_startup(struct fm_eth *fm_eth) +{ + struct fsl_enet_mac *mac; + int ret; + + mac = fm_eth->mac; + + /* Rx/TxBDs, Rx/TxQDs, Rx buff and parameter ram init */ + ret = fm_eth_init(fm_eth); + if (ret) + return ret; + /* setup the MAC controller */ + mac->init_mac(mac); + + /* For some reason we need to set SPEED_100 */ + if (((fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII) || + (fm_eth->enet_if == PHY_INTERFACE_MODE_QSGMII)) && + mac->set_if_mode) + mac->set_if_mode(mac, fm_eth->enet_if, SPEED_100); + + /* init bmi rx port, IM mode and disable */ + bmi_rx_port_init(fm_eth->rx_port); + /* init bmi tx port, IM mode and disable */ + bmi_tx_port_init(fm_eth->tx_port); + + return 0; +} + +static void fmc_tx_port_graceful_stop_enable(struct fm_eth *fm_eth) +{ + struct fm_port_global_pram *pram; + + pram = fm_eth->tx_pram; + /* graceful stop transmission of frames */ + setbits_be32(&pram->mode, PRAM_MODE_GRACEFUL_STOP); + sync(); +} + +static void fmc_tx_port_graceful_stop_disable(struct fm_eth *fm_eth) +{ + struct fm_port_global_pram *pram; + + pram = fm_eth->tx_pram; + /* re-enable transmission of frames */ + clrbits_be32(&pram->mode, PRAM_MODE_GRACEFUL_STOP); + sync(); +} + +static int fm_eth_open(struct eth_device *dev, bd_t *bd) +{ + struct fm_eth *fm_eth; + struct fsl_enet_mac *mac; +#ifdef CONFIG_PHYLIB + int ret; +#endif + + fm_eth = (struct fm_eth *)dev->priv; + mac = fm_eth->mac; + + /* setup the MAC address */ + if (dev->enetaddr[0] & 0x01) { + printf("%s: MacAddress is multcast address\n", __func__); + return 1; + } + mac->set_mac_addr(mac, dev->enetaddr); + + /* enable bmi Rx port */ + setbits_be32(&fm_eth->rx_port->fmbm_rcfg, FMBM_RCFG_EN); + /* enable MAC rx/tx port */ + mac->enable_mac(mac); + /* enable bmi Tx port */ + setbits_be32(&fm_eth->tx_port->fmbm_tcfg, FMBM_TCFG_EN); + /* re-enable transmission of frame */ + fmc_tx_port_graceful_stop_disable(fm_eth); + +#ifdef CONFIG_PHYLIB + if (fm_eth->phydev) { + ret = phy_startup(fm_eth->phydev); + if (ret) { + printf("%s: Could not initialize\n", + fm_eth->phydev->dev->name); + return ret; + } + } else { + return 0; + } +#else + fm_eth->phydev->speed = SPEED_1000; + fm_eth->phydev->link = 1; + fm_eth->phydev->duplex = DUPLEX_FULL; +#endif + + /* set the MAC-PHY mode */ + mac->set_if_mode(mac, fm_eth->enet_if, fm_eth->phydev->speed); + + if (!fm_eth->phydev->link) + printf("%s: No link.\n", fm_eth->phydev->dev->name); + + return fm_eth->phydev->link ? 0 : -1; +} + +static void fm_eth_halt(struct eth_device *dev) +{ + struct fm_eth *fm_eth; + struct fsl_enet_mac *mac; + + fm_eth = (struct fm_eth *)dev->priv; + mac = fm_eth->mac; + + /* graceful stop the transmission of frames */ + fmc_tx_port_graceful_stop_enable(fm_eth); + /* disable bmi Tx port */ + bmi_tx_port_disable(fm_eth->tx_port); + /* disable MAC rx/tx port */ + mac->disable_mac(mac); + /* disable bmi Rx port */ + bmi_rx_port_disable(fm_eth->rx_port); + +#ifdef CONFIG_PHYLIB + if (fm_eth->phydev) + phy_shutdown(fm_eth->phydev); +#endif +} + +static int fm_eth_send(struct eth_device *dev, void *buf, int len) +{ + struct fm_eth *fm_eth; + struct fm_port_global_pram *pram; + struct fm_port_bd *txbd, *txbd_base; + u16 offset_in; + int i; + + fm_eth = (struct fm_eth *)dev->priv; + pram = fm_eth->tx_pram; + txbd = fm_eth->cur_txbd; + + /* find one empty TxBD */ + for (i = 0; muram_readw(&txbd->status) & TxBD_READY; i++) { + udelay(100); + if (i > 0x1000) { + printf("%s: Tx buffer not ready, txbd->status = 0x%x\n", + dev->name, muram_readw(&txbd->status)); + return 0; + } + } + /* setup TxBD */ + muram_writew(&txbd->buf_ptr_hi, (u16)upper_32_bits(virt_to_phys(buf))); + out_be32(&txbd->buf_ptr_lo, lower_32_bits(virt_to_phys(buf))); + muram_writew(&txbd->len, len); + sync(); + muram_writew(&txbd->status, TxBD_READY | TxBD_LAST); + sync(); + + /* update TxQD, let RISC to send the packet */ + offset_in = muram_readw(&pram->txqd.offset_in); + offset_in += sizeof(struct fm_port_bd); + if (offset_in >= muram_readw(&pram->txqd.bd_ring_size)) + offset_in = 0; + muram_writew(&pram->txqd.offset_in, offset_in); + sync(); + + /* wait for buffer to be transmitted */ + for (i = 0; muram_readw(&txbd->status) & TxBD_READY; i++) { + udelay(100); + if (i > 0x10000) { + printf("%s: Tx error, txbd->status = 0x%x\n", + dev->name, muram_readw(&txbd->status)); + return 0; + } + } + + /* advance the TxBD */ + txbd++; + txbd_base = (struct fm_port_bd *)fm_eth->tx_bd_ring; + if (txbd >= (txbd_base + TX_BD_RING_SIZE)) + txbd = txbd_base; + /* update current txbd */ + fm_eth->cur_txbd = (void *)txbd; + + return 1; +} + +static int fm_eth_recv(struct eth_device *dev) +{ + struct fm_eth *fm_eth; + struct fm_port_global_pram *pram; + struct fm_port_bd *rxbd, *rxbd_base; + u16 status, len; + u32 buf_lo, buf_hi; + u8 *data; + u16 offset_out; + int ret = 1; + + fm_eth = (struct fm_eth *)dev->priv; + pram = fm_eth->rx_pram; + rxbd = fm_eth->cur_rxbd; + status = muram_readw(&rxbd->status); + + while (!(status & RxBD_EMPTY)) { + if (!(status & RxBD_ERROR)) { + buf_hi = muram_readw(&rxbd->buf_ptr_hi); + buf_lo = in_be32(&rxbd->buf_ptr_lo); + data = (u8 *)((ulong)(buf_hi << 16) << 16 | buf_lo); + len = muram_readw(&rxbd->len); + net_process_received_packet(data, len); + } else { + printf("%s: Rx error\n", dev->name); + ret = 0; + } + + /* clear the RxBDs */ + muram_writew(&rxbd->status, RxBD_EMPTY); + muram_writew(&rxbd->len, 0); + sync(); + + /* advance RxBD */ + rxbd++; + rxbd_base = (struct fm_port_bd *)fm_eth->rx_bd_ring; + if (rxbd >= (rxbd_base + RX_BD_RING_SIZE)) + rxbd = rxbd_base; + /* read next status */ + status = muram_readw(&rxbd->status); + + /* update RxQD */ + offset_out = muram_readw(&pram->rxqd.offset_out); + offset_out += sizeof(struct fm_port_bd); + if (offset_out >= muram_readw(&pram->rxqd.bd_ring_size)) + offset_out = 0; + muram_writew(&pram->rxqd.offset_out, offset_out); + sync(); + } + fm_eth->cur_rxbd = (void *)rxbd; + + return ret; +} + +static int fm_eth_init_mac(struct fm_eth *fm_eth, struct ccsr_fman *reg) +{ + struct fsl_enet_mac *mac; + int num; + void *base, *phyregs = NULL; + + num = fm_eth->num; + +#ifdef CONFIG_SYS_FMAN_V3 +#ifndef CONFIG_FSL_FM_10GEC_REGULAR_NOTATION + if (fm_eth->type == FM_ETH_10G_E) { + /* 10GEC1/10GEC2 use mEMAC9/mEMAC10 on T2080/T4240. + * 10GEC3/10GEC4 use mEMAC1/mEMAC2 on T2080. + * 10GEC1 uses mEMAC1 on T1024. + * so it needs to change the num. + */ + if (fm_eth->num >= 2) + num -= 2; + else + num += 8; + } +#endif + base = ®->memac[num].fm_memac; + phyregs = ®->memac[num].fm_memac_mdio; +#else + /* Get the mac registers base address */ + if (fm_eth->type == FM_ETH_1G_E) { + base = ®->mac_1g[num].fm_dtesc; + phyregs = ®->mac_1g[num].fm_mdio.miimcfg; + } else { + base = ®->mac_10g[num].fm_10gec; + phyregs = ®->mac_10g[num].fm_10gec_mdio; + } +#endif + + /* alloc mac controller */ + mac = malloc(sizeof(struct fsl_enet_mac)); + if (!mac) + return -ENOMEM; + memset(mac, 0, sizeof(struct fsl_enet_mac)); + + /* save the mac to fm_eth struct */ + fm_eth->mac = mac; + +#ifdef CONFIG_SYS_FMAN_V3 + init_memac(mac, base, phyregs, MAX_RXBUF_LEN); +#else + if (fm_eth->type == FM_ETH_1G_E) + init_dtsec(mac, base, phyregs, MAX_RXBUF_LEN); + else + init_tgec(mac, base, phyregs, MAX_RXBUF_LEN); +#endif + + return 0; +} + +static int init_phy(struct eth_device *dev) +{ + struct fm_eth *fm_eth = dev->priv; +#ifdef CONFIG_PHYLIB + struct phy_device *phydev = NULL; + u32 supported; +#endif + + if (fm_eth->type == FM_ETH_1G_E) + dtsec_init_phy(dev); + +#ifdef CONFIG_PHYLIB + if (fm_eth->bus) { + phydev = phy_connect(fm_eth->bus, fm_eth->phyaddr, dev, + fm_eth->enet_if); + if (!phydev) { + printf("Failed to connect\n"); + return -1; + } + } else { + return 0; + } + + if (fm_eth->type == FM_ETH_1G_E) { + supported = (SUPPORTED_10baseT_Half | + SUPPORTED_10baseT_Full | + SUPPORTED_100baseT_Half | + SUPPORTED_100baseT_Full | + SUPPORTED_1000baseT_Full); + } else { + supported = SUPPORTED_10000baseT_Full; + + if (tgec_is_fibre(dev)) + phydev->port = PORT_FIBRE; + } + + phydev->supported &= supported; + phydev->advertising = phydev->supported; + + fm_eth->phydev = phydev; + + phy_config(phydev); +#endif + + return 0; +} + +int fm_eth_initialize(struct ccsr_fman *reg, struct fm_eth_info *info) +{ + struct eth_device *dev; + struct fm_eth *fm_eth; + int i, num = info->num; + int ret; + + /* alloc eth device */ + dev = (struct eth_device *)malloc(sizeof(struct eth_device)); + if (!dev) + return -ENOMEM; + memset(dev, 0, sizeof(struct eth_device)); + + /* alloc the FMan ethernet private struct */ + fm_eth = (struct fm_eth *)malloc(sizeof(struct fm_eth)); + if (!fm_eth) + return -ENOMEM; + memset(fm_eth, 0, sizeof(struct fm_eth)); + + /* save off some things we need from the info struct */ + fm_eth->fm_index = info->index - 1; /* keep as 0 based for muram */ + fm_eth->num = num; + fm_eth->type = info->type; + + fm_eth->rx_port = (void *)®->port[info->rx_port_id - 1].fm_bmi; + fm_eth->tx_port = (void *)®->port[info->tx_port_id - 1].fm_bmi; + + /* set the ethernet max receive length */ + fm_eth->max_rx_len = MAX_RXBUF_LEN; + + /* init global mac structure */ + ret = fm_eth_init_mac(fm_eth, reg); + if (ret) + return ret; + + /* keep same as the manual, we call FMAN1, FMAN2, DTSEC1, DTSEC2, etc */ + if (fm_eth->type == FM_ETH_1G_E) + sprintf(dev->name, "FM%d@DTSEC%d", info->index, num + 1); + else + sprintf(dev->name, "FM%d@TGEC%d", info->index, num + 1); + + devlist[num_controllers++] = dev; + dev->iobase = 0; + dev->priv = (void *)fm_eth; + dev->init = fm_eth_open; + dev->halt = fm_eth_halt; + dev->send = fm_eth_send; + dev->recv = fm_eth_recv; + fm_eth->dev = dev; + fm_eth->bus = info->bus; + fm_eth->phyaddr = info->phy_addr; + fm_eth->enet_if = info->enet_if; + + /* startup the FM im */ + ret = fm_eth_startup(fm_eth); + if (ret) + return ret; + + init_phy(dev); + + /* clear the ethernet address */ + for (i = 0; i < 6; i++) + dev->enetaddr[i] = 0; + eth_register(dev); + + return 0; +} diff --git a/sources/uboot-be550/drivers/net/fm/fm.c b/sources/uboot-be550/drivers/net/fm/fm.c new file mode 100644 index 00000000..df5db723 --- /dev/null +++ b/sources/uboot-be550/drivers/net/fm/fm.c @@ -0,0 +1,425 @@ +/* + * Copyright 2009-2011 Freescale Semiconductor, Inc. + * Dave Liu + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include + +#include "fm.h" +#include "../../qe/qe.h" /* For struct qe_firmware */ + +#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND +#include +#elif defined(CONFIG_SYS_QE_FW_IN_SPIFLASH) +#include +#elif defined(CONFIG_SYS_QE_FMAN_FW_IN_MMC) +#include +#endif + +struct fm_muram muram[CONFIG_SYS_NUM_FMAN]; + +void *fm_muram_base(int fm_idx) +{ + return muram[fm_idx].base; +} + +void *fm_muram_alloc(int fm_idx, size_t size, ulong align) +{ + void *ret; + ulong align_mask; + size_t off; + void *save; + + align_mask = align - 1; + save = muram[fm_idx].alloc; + + off = (ulong)save & align_mask; + if (off != 0) + muram[fm_idx].alloc += (align - off); + off = size & align_mask; + if (off != 0) + size += (align - off); + if ((muram[fm_idx].alloc + size) >= muram[fm_idx].top) { + muram[fm_idx].alloc = save; + printf("%s: run out of ram.\n", __func__); + return NULL; + } + + ret = muram[fm_idx].alloc; + muram[fm_idx].alloc += size; + memset((void *)ret, 0, size); + + return ret; +} + +static void fm_init_muram(int fm_idx, void *reg) +{ + void *base = reg; + + muram[fm_idx].base = base; + muram[fm_idx].size = CONFIG_SYS_FM_MURAM_SIZE; + muram[fm_idx].alloc = base + FM_MURAM_RES_SIZE; + muram[fm_idx].top = base + CONFIG_SYS_FM_MURAM_SIZE; +} + +/* + * fm_upload_ucode - Fman microcode upload worker function + * + * This function does the actual uploading of an Fman microcode + * to an Fman. + */ +static void fm_upload_ucode(int fm_idx, struct fm_imem *imem, + u32 *ucode, unsigned int size) +{ + unsigned int i; + unsigned int timeout = 1000000; + + /* enable address auto increase */ + out_be32(&imem->iadd, IRAM_IADD_AIE); + /* write microcode to IRAM */ + for (i = 0; i < size / 4; i++) + out_be32(&imem->idata, (be32_to_cpu(ucode[i]))); + + /* verify if the writing is over */ + out_be32(&imem->iadd, 0); + while ((in_be32(&imem->idata) != be32_to_cpu(ucode[0])) && --timeout) + ; + if (!timeout) + printf("Fman%u: microcode upload timeout\n", fm_idx + 1); + + /* enable microcode from IRAM */ + out_be32(&imem->iready, IRAM_READY); +} + +/* + * Upload an Fman firmware + * + * This function is similar to qe_upload_firmware(), exception that it uploads + * a microcode to the Fman instead of the QE. + * + * Because the process for uploading a microcode to the Fman is similar for + * that of the QE, the QE firmware binary format is used for Fman microcode. + * It should be possible to unify these two functions, but for now we keep them + * separate. + */ +static int fman_upload_firmware(int fm_idx, + struct fm_imem *fm_imem, + const struct qe_firmware *firmware) +{ + unsigned int i; + u32 crc; + size_t calc_size = sizeof(struct qe_firmware); + size_t length; + const struct qe_header *hdr; + + if (!firmware) { + printf("Fman%u: Invalid address for firmware\n", fm_idx + 1); + return -EINVAL; + } + + hdr = &firmware->header; + length = be32_to_cpu(hdr->length); + + /* Check the magic */ + if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') || + (hdr->magic[2] != 'F')) { + printf("Fman%u: Data at %p is not a firmware\n", fm_idx + 1, + firmware); + return -EPERM; + } + + /* Check the version */ + if (hdr->version != 1) { + printf("Fman%u: Unsupported firmware version %u\n", fm_idx + 1, + hdr->version); + return -EPERM; + } + + /* Validate some of the fields */ + if ((firmware->count != 1)) { + printf("Fman%u: Invalid data in firmware header\n", fm_idx + 1); + return -EINVAL; + } + + /* Validate the length and check if there's a CRC */ + calc_size += (firmware->count - 1) * sizeof(struct qe_microcode); + + for (i = 0; i < firmware->count; i++) + /* + * For situations where the second RISC uses the same microcode + * as the first, the 'code_offset' and 'count' fields will be + * zero, so it's okay to add those. + */ + calc_size += sizeof(u32) * + be32_to_cpu(firmware->microcode[i].count); + + /* Validate the length */ + if (length != calc_size + sizeof(u32)) { + printf("Fman%u: Invalid length in firmware header\n", + fm_idx + 1); + return -EPERM; + } + + /* + * Validate the CRC. We would normally call crc32_no_comp(), but that + * function isn't available unless you turn on JFFS support. + */ + crc = be32_to_cpu(*(u32 *)((void *)firmware + calc_size)); + if (crc != (crc32(-1, (const void *)firmware, calc_size) ^ -1)) { + printf("Fman%u: Firmware CRC is invalid\n", fm_idx + 1); + return -EIO; + } + + /* Loop through each microcode. */ + for (i = 0; i < firmware->count; i++) { + const struct qe_microcode *ucode = &firmware->microcode[i]; + + /* Upload a microcode if it's present */ + if (be32_to_cpu(ucode->code_offset)) { + u32 ucode_size; + u32 *code; + printf("Fman%u: Uploading microcode version %u.%u.%u\n", + fm_idx + 1, ucode->major, ucode->minor, + ucode->revision); + code = (void *)firmware + + be32_to_cpu(ucode->code_offset); + ucode_size = sizeof(u32) * be32_to_cpu(ucode->count); + fm_upload_ucode(fm_idx, fm_imem, code, ucode_size); + } + } + + return 0; +} + +static u32 fm_assign_risc(int port_id) +{ + u32 risc_sel, val; + risc_sel = (port_id & 0x1) ? FMFPPRC_RISC2 : FMFPPRC_RISC1; + val = (port_id << FMFPPRC_PORTID_SHIFT) & FMFPPRC_PORTID_MASK; + val |= ((risc_sel << FMFPPRC_ORA_SHIFT) | risc_sel); + + return val; +} + +static void fm_init_fpm(struct fm_fpm *fpm) +{ + int i, port_id; + u32 val; + + setbits_be32(&fpm->fmfpee, FMFPEE_EHM | FMFPEE_UEC | + FMFPEE_CER | FMFPEE_DER); + + /* IM mode, each even port ID to RISC#1, each odd port ID to RISC#2 */ + + /* offline/parser port */ + for (i = 0; i < MAX_NUM_OH_PORT; i++) { + port_id = OH_PORT_ID_BASE + i; + val = fm_assign_risc(port_id); + out_be32(&fpm->fpmprc, val); + } + /* Rx 1G port */ + for (i = 0; i < MAX_NUM_RX_PORT_1G; i++) { + port_id = RX_PORT_1G_BASE + i; + val = fm_assign_risc(port_id); + out_be32(&fpm->fpmprc, val); + } + /* Tx 1G port */ + for (i = 0; i < MAX_NUM_TX_PORT_1G; i++) { + port_id = TX_PORT_1G_BASE + i; + val = fm_assign_risc(port_id); + out_be32(&fpm->fpmprc, val); + } + /* Rx 10G port */ + port_id = RX_PORT_10G_BASE; + val = fm_assign_risc(port_id); + out_be32(&fpm->fpmprc, val); + /* Tx 10G port */ + port_id = TX_PORT_10G_BASE; + val = fm_assign_risc(port_id); + out_be32(&fpm->fpmprc, val); + + /* disable the dispatch limit in IM case */ + out_be32(&fpm->fpmflc, FMFP_FLC_DISP_LIM_NONE); + /* clear events */ + out_be32(&fpm->fmfpee, FMFPEE_CLEAR_EVENT); + + /* clear risc events */ + for (i = 0; i < 4; i++) + out_be32(&fpm->fpmcev[i], 0xffffffff); + + /* clear error */ + out_be32(&fpm->fpmrcr, FMFP_RCR_MDEC | FMFP_RCR_IDEC); +} + +static int fm_init_bmi(int fm_idx, struct fm_bmi_common *bmi) +{ + int blk, i, port_id; + u32 val; + size_t offset; + void *base; + + /* alloc free buffer pool in MURAM */ + base = fm_muram_alloc(fm_idx, FM_FREE_POOL_SIZE, FM_FREE_POOL_ALIGN); + if (!base) { + printf("%s: no muram for free buffer pool\n", __func__); + return -ENOMEM; + } + offset = base - fm_muram_base(fm_idx); + + /* Need 128KB total free buffer pool size */ + val = offset / 256; + blk = FM_FREE_POOL_SIZE / 256; + /* in IM, we must not begin from offset 0 in MURAM */ + val |= ((blk - 1) << FMBM_CFG1_FBPS_SHIFT); + out_be32(&bmi->fmbm_cfg1, val); + + /* disable all BMI interrupt */ + out_be32(&bmi->fmbm_ier, FMBM_IER_DISABLE_ALL); + + /* clear all events */ + out_be32(&bmi->fmbm_ievr, FMBM_IEVR_CLEAR_ALL); + + /* + * set port parameters - FMBM_PP_x + * max tasks 10G Rx/Tx=12, 1G Rx/Tx 4, others is 1 + * max dma 10G Rx/Tx=3, others is 1 + * set port FIFO size - FMBM_PFS_x + * 4KB for all Rx and Tx ports + */ + /* offline/parser port */ + for (i = 0; i < MAX_NUM_OH_PORT; i++) { + port_id = OH_PORT_ID_BASE + i - 1; + /* max tasks=1, max dma=1, no extra */ + out_be32(&bmi->fmbm_pp[port_id], 0); + /* port FIFO size - 256 bytes, no extra */ + out_be32(&bmi->fmbm_pfs[port_id], 0); + } + /* Rx 1G port */ + for (i = 0; i < MAX_NUM_RX_PORT_1G; i++) { + port_id = RX_PORT_1G_BASE + i - 1; + /* max tasks=4, max dma=1, no extra */ + out_be32(&bmi->fmbm_pp[port_id], FMBM_PP_MXT(4)); + /* FIFO size - 4KB, no extra */ + out_be32(&bmi->fmbm_pfs[port_id], FMBM_PFS_IFSZ(0xf)); + } + /* Tx 1G port FIFO size - 4KB, no extra */ + for (i = 0; i < MAX_NUM_TX_PORT_1G; i++) { + port_id = TX_PORT_1G_BASE + i - 1; + /* max tasks=4, max dma=1, no extra */ + out_be32(&bmi->fmbm_pp[port_id], FMBM_PP_MXT(4)); + /* FIFO size - 4KB, no extra */ + out_be32(&bmi->fmbm_pfs[port_id], FMBM_PFS_IFSZ(0xf)); + } + /* Rx 10G port */ + port_id = RX_PORT_10G_BASE - 1; + /* max tasks=12, max dma=3, no extra */ + out_be32(&bmi->fmbm_pp[port_id], FMBM_PP_MXT(12) | FMBM_PP_MXD(3)); + /* FIFO size - 4KB, no extra */ + out_be32(&bmi->fmbm_pfs[port_id], FMBM_PFS_IFSZ(0xf)); + + /* Tx 10G port */ + port_id = TX_PORT_10G_BASE - 1; + /* max tasks=12, max dma=3, no extra */ + out_be32(&bmi->fmbm_pp[port_id], FMBM_PP_MXT(12) | FMBM_PP_MXD(3)); + /* FIFO size - 4KB, no extra */ + out_be32(&bmi->fmbm_pfs[port_id], FMBM_PFS_IFSZ(0xf)); + + /* initialize internal buffers data base (linked list) */ + out_be32(&bmi->fmbm_init, FMBM_INIT_START); + + return 0; +} + +static void fm_init_qmi(struct fm_qmi_common *qmi) +{ + /* disable enqueue and dequeue of QMI */ + clrbits_be32(&qmi->fmqm_gc, FMQM_GC_ENQ_EN | FMQM_GC_DEQ_EN); + + /* disable all error interrupts */ + out_be32(&qmi->fmqm_eien, FMQM_EIEN_DISABLE_ALL); + /* clear all error events */ + out_be32(&qmi->fmqm_eie, FMQM_EIE_CLEAR_ALL); + + /* disable all interrupts */ + out_be32(&qmi->fmqm_ien, FMQM_IEN_DISABLE_ALL); + /* clear all interrupts */ + out_be32(&qmi->fmqm_ie, FMQM_IE_CLEAR_ALL); +} + +/* Init common part of FM, index is fm num# like fm as above */ +int fm_init_common(int index, struct ccsr_fman *reg) +{ + int rc; +#if defined(CONFIG_SYS_QE_FMAN_FW_IN_NOR) + void *addr = (void *)CONFIG_SYS_FMAN_FW_ADDR; +#elif defined(CONFIG_SYS_QE_FMAN_FW_IN_NAND) + size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH; + void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH); + + rc = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_FMAN_FW_ADDR, + &fw_length, (u_char *)addr); + if (rc == -EUCLEAN) { + printf("NAND read of FMAN firmware at offset 0x%x failed %d\n", + CONFIG_SYS_FMAN_FW_ADDR, rc); + } +#elif defined(CONFIG_SYS_QE_FW_IN_SPIFLASH) + struct spi_flash *ucode_flash; + void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH); + int ret = 0; + + ucode_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS, + CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE); + if (!ucode_flash) + printf("SF: probe for ucode failed\n"); + else { + ret = spi_flash_read(ucode_flash, CONFIG_SYS_FMAN_FW_ADDR, + CONFIG_SYS_QE_FMAN_FW_LENGTH, addr); + if (ret) + printf("SF: read for ucode failed\n"); + spi_flash_free(ucode_flash); + } +#elif defined(CONFIG_SYS_QE_FMAN_FW_IN_MMC) + int dev = CONFIG_SYS_MMC_ENV_DEV; + void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH); + u32 cnt = CONFIG_SYS_QE_FMAN_FW_LENGTH / 512; + u32 blk = CONFIG_SYS_FMAN_FW_ADDR / 512; + struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV); + + if (!mmc) + printf("\nMMC cannot find device for ucode\n"); + else { + printf("\nMMC read: dev # %u, block # %u, count %u ...\n", + dev, blk, cnt); + mmc_init(mmc); + (void)mmc->block_dev.block_read(dev, blk, cnt, addr); + /* flush cache after read */ + flush_cache((ulong)addr, cnt * 512); + } +#elif defined(CONFIG_SYS_QE_FMAN_FW_IN_REMOTE) + void *addr = (void *)CONFIG_SYS_FMAN_FW_ADDR; +#else + void *addr = NULL; +#endif + + /* Upload the Fman microcode if it's present */ + rc = fman_upload_firmware(index, ®->fm_imem, addr); + if (rc) + return rc; + setenv_addr("fman_ucode", addr); + + fm_init_muram(index, ®->muram); + fm_init_qmi(®->fm_qmi_common); + fm_init_fpm(®->fm_fpm); + + /* clear DMA status */ + setbits_be32(®->fm_dma.fmdmsr, FMDMSR_CLEAR_ALL); + + /* set DMA mode */ + setbits_be32(®->fm_dma.fmdmmr, FMDMMR_SBER); + + return fm_init_bmi(index, ®->fm_bmi_common); +} diff --git a/sources/uboot-be550/drivers/net/fm/fm.h b/sources/uboot-be550/drivers/net/fm/fm.h new file mode 100644 index 00000000..fa9bc9f4 --- /dev/null +++ b/sources/uboot-be550/drivers/net/fm/fm.h @@ -0,0 +1,149 @@ +/* + * Copyright 2009-2011 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FM_H__ +#define __FM_H__ + +#include +#include +#include +#include + +/* Port ID */ +#define OH_PORT_ID_BASE 0x01 +#define MAX_NUM_OH_PORT 7 +#define RX_PORT_1G_BASE 0x08 +#define MAX_NUM_RX_PORT_1G CONFIG_SYS_NUM_FM1_DTSEC +#define RX_PORT_10G_BASE 0x10 +#define RX_PORT_10G_BASE2 0x08 +#define TX_PORT_1G_BASE 0x28 +#define MAX_NUM_TX_PORT_1G CONFIG_SYS_NUM_FM1_DTSEC +#define TX_PORT_10G_BASE 0x30 +#define TX_PORT_10G_BASE2 0x28 +#define MIIM_TIMEOUT 0xFFFF + +struct fm_muram { + void *base; + void *top; + size_t size; + void *alloc; +}; +#define FM_MURAM_RES_SIZE 0x01000 + +/* Rx/Tx buffer descriptor */ +struct fm_port_bd { + u16 status; + u16 len; + u32 res0; + u16 res1; + u16 buf_ptr_hi; + u32 buf_ptr_lo; +}; + +/* Common BD flags */ +#define BD_LAST 0x0800 + +/* Rx BD status flags */ +#define RxBD_EMPTY 0x8000 +#define RxBD_LAST BD_LAST +#define RxBD_FIRST 0x0400 +#define RxBD_PHYS_ERR 0x0008 +#define RxBD_SIZE_ERR 0x0004 +#define RxBD_ERROR (RxBD_PHYS_ERR | RxBD_SIZE_ERR) + +/* Tx BD status flags */ +#define TxBD_READY 0x8000 +#define TxBD_LAST BD_LAST + +/* Rx/Tx queue descriptor */ +struct fm_port_qd { + u16 gen; + u16 bd_ring_base_hi; + u32 bd_ring_base_lo; + u16 bd_ring_size; + u16 offset_in; + u16 offset_out; + u16 res0; + u32 res1[0x4]; +}; + +/* IM global parameter RAM */ +struct fm_port_global_pram { + u32 mode; /* independent mode register */ + u32 rxqd_ptr; /* Rx queue descriptor pointer */ + u32 txqd_ptr; /* Tx queue descriptor pointer */ + u16 mrblr; /* max Rx buffer length */ + u16 rxqd_bsy_cnt; /* RxQD busy counter, should be cleared */ + u32 res0[0x4]; + struct fm_port_qd rxqd; /* Rx queue descriptor */ + struct fm_port_qd txqd; /* Tx queue descriptor */ + u32 res1[0x28]; +}; + +#define FM_PRAM_SIZE sizeof(struct fm_port_global_pram) +#define FM_PRAM_ALIGN 256 +#define PRAM_MODE_GLOBAL 0x20000000 +#define PRAM_MODE_GRACEFUL_STOP 0x00800000 + +#if defined(CONFIG_P1017) || defined(CONFIG_P1023) +#define FM_FREE_POOL_SIZE 0x2000 /* 8K bytes */ +#else +#define FM_FREE_POOL_SIZE 0x20000 /* 128K bytes */ +#endif +#define FM_FREE_POOL_ALIGN 256 + +void *fm_muram_alloc(int fm_idx, size_t size, ulong align); +void *fm_muram_base(int fm_idx); +int fm_init_common(int index, struct ccsr_fman *reg); +int fm_eth_initialize(struct ccsr_fman *reg, struct fm_eth_info *info); +phy_interface_t fman_port_enet_if(enum fm_port port); +void fman_disable_port(enum fm_port port); +void fman_enable_port(enum fm_port port); + +struct fsl_enet_mac { + void *base; /* MAC controller registers base address */ + void *phyregs; + int max_rx_len; + void (*init_mac)(struct fsl_enet_mac *mac); + void (*enable_mac)(struct fsl_enet_mac *mac); + void (*disable_mac)(struct fsl_enet_mac *mac); + void (*set_mac_addr)(struct fsl_enet_mac *mac, u8 *mac_addr); + void (*set_if_mode)(struct fsl_enet_mac *mac, phy_interface_t type, + int speed); +}; + +/* Fman ethernet private struct */ +struct fm_eth { + int fm_index; /* Fman index */ + u32 num; /* 0..n-1 for give type */ + struct fm_bmi_tx_port *tx_port; + struct fm_bmi_rx_port *rx_port; + enum fm_eth_type type; /* 1G or 10G ethernet */ + phy_interface_t enet_if; + struct fsl_enet_mac *mac; /* MAC controller */ + struct mii_dev *bus; + struct phy_device *phydev; + int phyaddr; + struct eth_device *dev; + int max_rx_len; + struct fm_port_global_pram *rx_pram; /* Rx parameter table */ + struct fm_port_global_pram *tx_pram; /* Tx parameter table */ + void *rx_bd_ring; /* Rx BD ring base */ + void *cur_rxbd; /* current Rx BD */ + void *rx_buf; /* Rx buffer base */ + void *tx_bd_ring; /* Tx BD ring base */ + void *cur_txbd; /* current Tx BD */ +}; + +#define RX_BD_RING_SIZE 8 +#define TX_BD_RING_SIZE 8 +#define MAX_RXBUF_LOG2 11 +#define MAX_RXBUF_LEN (1 << MAX_RXBUF_LOG2) + +#define PORT_IS_ENABLED(port) (fm_port_to_index(port) == -1 ? \ + 0 : fm_info[fm_port_to_index(port)].enabled) + +#endif /* __FM_H__ */ diff --git a/sources/uboot-be550/drivers/net/fm/init.c b/sources/uboot-be550/drivers/net/fm/init.c new file mode 100644 index 00000000..7e312f15 --- /dev/null +++ b/sources/uboot-be550/drivers/net/fm/init.c @@ -0,0 +1,381 @@ +/* + * Copyright 2011-2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#ifdef CONFIG_FSL_LAYERSCAPE +#include +#else +#include +#endif + +#include "fm.h" + +struct fm_eth_info fm_info[] = { +#if (CONFIG_SYS_NUM_FM1_DTSEC >= 1) + FM_DTSEC_INFO_INITIALIZER(1, 1), +#endif +#if (CONFIG_SYS_NUM_FM1_DTSEC >= 2) + FM_DTSEC_INFO_INITIALIZER(1, 2), +#endif +#if (CONFIG_SYS_NUM_FM1_DTSEC >= 3) + FM_DTSEC_INFO_INITIALIZER(1, 3), +#endif +#if (CONFIG_SYS_NUM_FM1_DTSEC >= 4) + FM_DTSEC_INFO_INITIALIZER(1, 4), +#endif +#if (CONFIG_SYS_NUM_FM1_DTSEC >= 5) + FM_DTSEC_INFO_INITIALIZER(1, 5), +#endif +#if (CONFIG_SYS_NUM_FM1_DTSEC >= 6) + FM_DTSEC_INFO_INITIALIZER(1, 6), +#endif +#if (CONFIG_SYS_NUM_FM1_DTSEC >= 7) + FM_DTSEC_INFO_INITIALIZER(1, 9), +#endif +#if (CONFIG_SYS_NUM_FM1_DTSEC >= 8) + FM_DTSEC_INFO_INITIALIZER(1, 10), +#endif +#if (CONFIG_SYS_NUM_FM2_DTSEC >= 1) + FM_DTSEC_INFO_INITIALIZER(2, 1), +#endif +#if (CONFIG_SYS_NUM_FM2_DTSEC >= 2) + FM_DTSEC_INFO_INITIALIZER(2, 2), +#endif +#if (CONFIG_SYS_NUM_FM2_DTSEC >= 3) + FM_DTSEC_INFO_INITIALIZER(2, 3), +#endif +#if (CONFIG_SYS_NUM_FM2_DTSEC >= 4) + FM_DTSEC_INFO_INITIALIZER(2, 4), +#endif +#if (CONFIG_SYS_NUM_FM2_DTSEC >= 5) + FM_DTSEC_INFO_INITIALIZER(2, 5), +#endif +#if (CONFIG_SYS_NUM_FM2_DTSEC >= 6) + FM_DTSEC_INFO_INITIALIZER(2, 6), +#endif +#if (CONFIG_SYS_NUM_FM2_DTSEC >= 7) + FM_DTSEC_INFO_INITIALIZER(2, 9), +#endif +#if (CONFIG_SYS_NUM_FM2_DTSEC >= 8) + FM_DTSEC_INFO_INITIALIZER(2, 10), +#endif +#if (CONFIG_SYS_NUM_FM1_10GEC >= 1) + FM_TGEC_INFO_INITIALIZER(1, 1), +#endif +#if (CONFIG_SYS_NUM_FM1_10GEC >= 2) + FM_TGEC_INFO_INITIALIZER(1, 2), +#endif +#if (CONFIG_SYS_NUM_FM1_10GEC >= 3) + FM_TGEC_INFO_INITIALIZER2(1, 3), +#endif +#if (CONFIG_SYS_NUM_FM1_10GEC >= 4) + FM_TGEC_INFO_INITIALIZER2(1, 4), +#endif +#if (CONFIG_SYS_NUM_FM2_10GEC >= 1) + FM_TGEC_INFO_INITIALIZER(2, 1), +#endif +#if (CONFIG_SYS_NUM_FM2_10GEC >= 2) + FM_TGEC_INFO_INITIALIZER(2, 2), +#endif +}; + +int fm_standard_init(bd_t *bis) +{ + int i; + struct ccsr_fman *reg; + + reg = (void *)CONFIG_SYS_FSL_FM1_ADDR; + if (fm_init_common(0, reg)) + return 0; + + for (i = 0; i < ARRAY_SIZE(fm_info); i++) { + if ((fm_info[i].enabled) && (fm_info[i].index == 1)) + fm_eth_initialize(reg, &fm_info[i]); + } + +#if (CONFIG_SYS_NUM_FMAN == 2) + reg = (void *)CONFIG_SYS_FSL_FM2_ADDR; + if (fm_init_common(1, reg)) + return 0; + + for (i = 0; i < ARRAY_SIZE(fm_info); i++) { + if ((fm_info[i].enabled) && (fm_info[i].index == 2)) + fm_eth_initialize(reg, &fm_info[i]); + } +#endif + + return 1; +} + +/* simple linear search to map from port to array index */ +static int fm_port_to_index(enum fm_port port) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(fm_info); i++) { + if (fm_info[i].port == port) + return i; + } + + return -1; +} + +/* + * Determine if an interface is actually active based on HW config + * we expect fman_port_enet_if() to report PHY_INTERFACE_MODE_NONE if + * the interface is not active based on HW cfg of the SoC + */ +void fman_enet_init(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(fm_info); i++) { + phy_interface_t enet_if; + + enet_if = fman_port_enet_if(fm_info[i].port); + if (enet_if != PHY_INTERFACE_MODE_NONE) { + fm_info[i].enabled = 1; + fm_info[i].enet_if = enet_if; + } else { + fm_info[i].enabled = 0; + } + } + + return ; +} + +void fm_disable_port(enum fm_port port) +{ + int i = fm_port_to_index(port); + + if (i == -1) + return; + + fm_info[i].enabled = 0; +#ifndef CONFIG_SYS_FMAN_V3 + fman_disable_port(port); +#endif +} + +void fm_enable_port(enum fm_port port) +{ + int i = fm_port_to_index(port); + + if (i == -1) + return; + + fm_info[i].enabled = 1; + fman_enable_port(port); +} + +void fm_info_set_mdio(enum fm_port port, struct mii_dev *bus) +{ + int i = fm_port_to_index(port); + + if (i == -1) + return; + + fm_info[i].bus = bus; +} + +void fm_info_set_phy_address(enum fm_port port, int address) +{ + int i = fm_port_to_index(port); + + if (i == -1) + return; + + fm_info[i].phy_addr = address; +} + +/* + * Returns the PHY address for a given Fman port + * + * The port must be set via a prior call to fm_info_set_phy_address(). + * A negative error code is returned if the port is invalid. + */ +int fm_info_get_phy_address(enum fm_port port) +{ + int i = fm_port_to_index(port); + + if (i == -1) + return -1; + + return fm_info[i].phy_addr; +} + +/* + * Returns the type of the data interface between the given MAC and its PHY. + * This is typically determined by the RCW. + */ +phy_interface_t fm_info_get_enet_if(enum fm_port port) +{ + int i = fm_port_to_index(port); + + if (i == -1) + return PHY_INTERFACE_MODE_NONE; + + if (fm_info[i].enabled) + return fm_info[i].enet_if; + + return PHY_INTERFACE_MODE_NONE; +} + +static void +__def_board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa, + enum fm_port port, int offset) +{ + return ; +} + +void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa, + enum fm_port port, int offset) + __attribute__((weak, alias("__def_board_ft_fman_fixup_port"))); + +int ft_fixup_port(void *blob, struct fm_eth_info *info, char *prop) +{ + int off; + uint32_t ph; + phys_addr_t paddr = CONFIG_SYS_CCSRBAR_PHYS + info->compat_offset; +#ifndef CONFIG_SYS_FMAN_V3 + u64 dtsec1_addr = (u64)CONFIG_SYS_CCSRBAR_PHYS + + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET; +#endif + + off = fdt_node_offset_by_compat_reg(blob, prop, paddr); + if (off == -FDT_ERR_NOTFOUND) + return -EINVAL; + + if (info->enabled) { + fdt_fixup_phy_connection(blob, off, info->enet_if); + board_ft_fman_fixup_port(blob, prop, paddr, info->port, off); + return 0; + } + +#ifdef CONFIG_SYS_FMAN_V3 +#ifndef CONFIG_FSL_FM_10GEC_REGULAR_NOTATION + /* + * On T2/T4 SoCs, physically FM1_DTSEC9 and FM1_10GEC1 use the same + * dual-role MAC, when FM1_10GEC1 is enabled and FM1_DTSEC9 + * is disabled, ensure that the dual-role MAC is not disabled, + * ditto for other dual-role MACs. + */ + if (((info->port == FM1_DTSEC9) && (PORT_IS_ENABLED(FM1_10GEC1))) || + ((info->port == FM1_DTSEC10) && (PORT_IS_ENABLED(FM1_10GEC2))) || + ((info->port == FM1_DTSEC1) && (PORT_IS_ENABLED(FM1_10GEC3))) || + ((info->port == FM1_DTSEC2) && (PORT_IS_ENABLED(FM1_10GEC4))) || + ((info->port == FM1_10GEC1) && (PORT_IS_ENABLED(FM1_DTSEC9))) || + ((info->port == FM1_10GEC2) && (PORT_IS_ENABLED(FM1_DTSEC10))) || + ((info->port == FM1_10GEC3) && (PORT_IS_ENABLED(FM1_DTSEC1))) || + ((info->port == FM1_10GEC4) && (PORT_IS_ENABLED(FM1_DTSEC2))) +#if (CONFIG_SYS_NUM_FMAN == 2) + || + ((info->port == FM2_DTSEC9) && (PORT_IS_ENABLED(FM2_10GEC1))) || + ((info->port == FM2_DTSEC10) && (PORT_IS_ENABLED(FM2_10GEC2))) || + ((info->port == FM2_10GEC1) && (PORT_IS_ENABLED(FM2_DTSEC9))) || + ((info->port == FM2_10GEC2) && (PORT_IS_ENABLED(FM2_DTSEC10))) +#endif +#else + /* FM1_DTSECx and FM1_10GECx use the same dual-role MAC */ + if (((info->port == FM1_DTSEC1) && (PORT_IS_ENABLED(FM1_10GEC1))) || + ((info->port == FM1_DTSEC2) && (PORT_IS_ENABLED(FM1_10GEC2))) || + ((info->port == FM1_DTSEC3) && (PORT_IS_ENABLED(FM1_10GEC3))) || + ((info->port == FM1_DTSEC4) && (PORT_IS_ENABLED(FM1_10GEC4))) || + ((info->port == FM1_10GEC1) && (PORT_IS_ENABLED(FM1_DTSEC1))) || + ((info->port == FM1_10GEC2) && (PORT_IS_ENABLED(FM1_DTSEC2))) || + ((info->port == FM1_10GEC3) && (PORT_IS_ENABLED(FM1_DTSEC3))) || + ((info->port == FM1_10GEC4) && (PORT_IS_ENABLED(FM1_DTSEC4))) +#endif + ) + return 0; +#endif + /* board code might have caused offset to change */ + off = fdt_node_offset_by_compat_reg(blob, prop, paddr); + +#ifndef CONFIG_SYS_FMAN_V3 + /* Don't disable FM1-DTSEC1 MAC as its used for MDIO */ + if (paddr != dtsec1_addr) +#endif + fdt_status_disabled(blob, off); /* disable the MAC node */ + + /* disable the fsl,dpa-ethernet node that points to the MAC */ + ph = fdt_get_phandle(blob, off); + do_fixup_by_prop(blob, "fsl,fman-mac", &ph, sizeof(ph), + "status", "disabled", strlen("disabled") + 1, 1); + + return 0; +} + +void fdt_fixup_fman_ethernet(void *blob) +{ + int i; + +#ifdef CONFIG_SYS_FMAN_V3 + for (i = 0; i < ARRAY_SIZE(fm_info); i++) + ft_fixup_port(blob, &fm_info[i], "fsl,fman-memac"); +#else + for (i = 0; i < ARRAY_SIZE(fm_info); i++) { + /* Try the new compatible first. + * If the node is missing, try the old. + */ + if (fm_info[i].type == FM_ETH_1G_E) { + if (ft_fixup_port(blob, &fm_info[i], "fsl,fman-dtsec")) + ft_fixup_port(blob, &fm_info[i], + "fsl,fman-1g-mac"); + } else { + if (ft_fixup_port(blob, &fm_info[i], "fsl,fman-tgec")) + ft_fixup_port(blob, &fm_info[i], + "fsl,fman-10g-mac"); + } + } +#endif +} + +/*QSGMII Riser Card can work in SGMII mode, but the PHY address is different. + *This function scans which Riser Card being used(QSGMII or SGMII Riser Card), + *then set the correct PHY address + */ +void set_sgmii_phy(struct mii_dev *bus, enum fm_port base_port, + unsigned int port_num, int phy_base_addr) +{ + unsigned int regnum = 0; + int qsgmii; + int i; + int phy_real_addr; + + qsgmii = is_qsgmii_riser_card(bus, phy_base_addr, port_num, regnum); + + if (!qsgmii) + return; + + for (i = base_port; i < base_port + port_num; i++) { + if (fm_info_get_enet_if(i) == PHY_INTERFACE_MODE_SGMII) { + phy_real_addr = phy_base_addr + i - base_port; + fm_info_set_phy_address(i, phy_real_addr); + } + } +} + +/*to check whether qsgmii riser card is used*/ +int is_qsgmii_riser_card(struct mii_dev *bus, int phy_base_addr, + unsigned int port_num, unsigned regnum) +{ + int i; + int val; + + if (!bus) + return 0; + + for (i = phy_base_addr; i < phy_base_addr + port_num; i++) { + val = bus->read(bus, i, MDIO_DEVAD_NONE, regnum); + if (val != MIIM_TIMEOUT) + return 1; + } + + return 0; +} diff --git a/sources/uboot-be550/drivers/net/fm/ls1043.c b/sources/uboot-be550/drivers/net/fm/ls1043.c new file mode 100644 index 00000000..93ba318b --- /dev/null +++ b/sources/uboot-be550/drivers/net/fm/ls1043.c @@ -0,0 +1,112 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include + +#define FSL_CHASSIS2_RCWSR13_EC1 0xe0000000 /* bits 416..418 */ +#define FSL_CHASSIS2_RCWSR13_EC1_DTSEC3_RGMII 0x00000000 +#define FSL_CHASSIS2_RCWSR13_EC1_GPIO 0x20000000 +#define FSL_CHASSIS2_RCWSR13_EC1_FTM 0xa0000000 +#define FSL_CHASSIS2_RCWSR13_EC2 0x1c000000 /* bits 419..421 */ +#define FSL_CHASSIS2_RCWSR13_EC2_DTSEC4_RGMII 0x00000000 +#define FSL_CHASSIS2_RCWSR13_EC2_GPIO 0x04000000 +#define FSL_CHASSIS2_RCWSR13_EC2_1588 0x08000000 +#define FSL_CHASSIS2_RCWSR13_EC2_FTM 0x14000000 + +u32 port_to_devdisr[] = { + [FM1_DTSEC1] = FSL_CHASSIS2_DEVDISR2_DTSEC1_1, + [FM1_DTSEC2] = FSL_CHASSIS2_DEVDISR2_DTSEC1_2, + [FM1_DTSEC3] = FSL_CHASSIS2_DEVDISR2_DTSEC1_3, + [FM1_DTSEC4] = FSL_CHASSIS2_DEVDISR2_DTSEC1_4, + [FM1_DTSEC5] = FSL_CHASSIS2_DEVDISR2_DTSEC1_5, + [FM1_DTSEC6] = FSL_CHASSIS2_DEVDISR2_DTSEC1_6, + [FM1_DTSEC9] = FSL_CHASSIS2_DEVDISR2_DTSEC1_9, + [FM1_DTSEC10] = FSL_CHASSIS2_DEVDISR2_DTSEC1_10, + [FM1_10GEC1] = FSL_CHASSIS2_DEVDISR2_10GEC1_1, + [FM1_10GEC2] = FSL_CHASSIS2_DEVDISR2_10GEC1_2, + [FM1_10GEC3] = FSL_CHASSIS2_DEVDISR2_10GEC1_3, + [FM1_10GEC4] = FSL_CHASSIS2_DEVDISR2_10GEC1_4, +}; + +static int is_device_disabled(enum fm_port port) +{ + struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + u32 devdisr2 = in_be32(&gur->devdisr2); + + return port_to_devdisr[port] & devdisr2; +} + +void fman_disable_port(enum fm_port port) +{ + struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + + setbits_be32(&gur->devdisr2, port_to_devdisr[port]); +} + +phy_interface_t fman_port_enet_if(enum fm_port port) +{ + struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + u32 rcwsr13 = in_be32(&gur->rcwsr[13]); + + if (is_device_disabled(port)) + return PHY_INTERFACE_MODE_NONE; + + if ((port == FM1_10GEC1) && (is_serdes_configured(XFI_FM1_MAC9))) + return PHY_INTERFACE_MODE_XGMII; + + if ((port == FM1_DTSEC9) && (is_serdes_configured(XFI_FM1_MAC9))) + return PHY_INTERFACE_MODE_NONE; + + if (port == FM1_DTSEC3) + if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC1) == + FSL_CHASSIS2_RCWSR13_EC1_DTSEC3_RGMII) { + return PHY_INTERFACE_MODE_RGMII; + } + if (port == FM1_DTSEC4) + if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC2) == + FSL_CHASSIS2_RCWSR13_EC2_DTSEC4_RGMII) { + return PHY_INTERFACE_MODE_RGMII; + } + + /* handle SGMII */ + switch (port) { + case FM1_DTSEC1: + case FM1_DTSEC2: + if ((port == FM1_DTSEC2) && + is_serdes_configured(SGMII_2500_FM1_DTSEC2)) + return PHY_INTERFACE_MODE_SGMII_2500; + case FM1_DTSEC5: + case FM1_DTSEC6: + case FM1_DTSEC9: + if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1)) + return PHY_INTERFACE_MODE_SGMII; + else if ((port == FM1_DTSEC9) && + is_serdes_configured(SGMII_2500_FM1_DTSEC9)) + return PHY_INTERFACE_MODE_SGMII_2500; + break; + default: + break; + } + + /* handle QSGMII */ + switch (port) { + case FM1_DTSEC1: + case FM1_DTSEC2: + case FM1_DTSEC5: + case FM1_DTSEC6: + /* only MAC 1,2,5,6 available for QSGMII */ + if (is_serdes_configured(QSGMII_FM1_A)) + return PHY_INTERFACE_MODE_QSGMII; + break; + default: + break; + } + + return PHY_INTERFACE_MODE_NONE; +} diff --git a/sources/uboot-be550/drivers/net/fm/memac.c b/sources/uboot-be550/drivers/net/fm/memac.c new file mode 100644 index 00000000..81a64bf6 --- /dev/null +++ b/sources/uboot-be550/drivers/net/fm/memac.c @@ -0,0 +1,142 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * Roy Zang + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* MAXFRM - maximum frame length */ +#define MAXFRM_MASK 0x0000ffff + +#include +#include +#include +#include +#include + +#include "fm.h" + +static void memac_init_mac(struct fsl_enet_mac *mac) +{ + struct memac *regs = mac->base; + + /* mask all interrupt */ + out_be32(®s->imask, IMASK_MASK_ALL); + + /* clear all events */ + out_be32(®s->ievent, IEVENT_CLEAR_ALL); + + /* set the max receive length */ + out_be32(®s->maxfrm, mac->max_rx_len & MAXFRM_MASK); + + /* multicast frame reception for the hash entry disable */ + out_be32(®s->hashtable_ctrl, 0); +} + +static void memac_enable_mac(struct fsl_enet_mac *mac) +{ + struct memac *regs = mac->base; + + setbits_be32(®s->command_config, + MEMAC_CMD_CFG_RXTX_EN | MEMAC_CMD_CFG_NO_LEN_CHK); +} + +static void memac_disable_mac(struct fsl_enet_mac *mac) +{ + struct memac *regs = mac->base; + + clrbits_be32(®s->command_config, MEMAC_CMD_CFG_RXTX_EN); +} + +static void memac_set_mac_addr(struct fsl_enet_mac *mac, u8 *mac_addr) +{ + struct memac *regs = mac->base; + u32 mac_addr0, mac_addr1; + + /* + * if a station address of 0x12345678ABCD, perform a write to + * MAC_ADDR0 of 0x78563412, MAC_ADDR1 of 0x0000CDAB + */ + mac_addr0 = (mac_addr[3] << 24) | (mac_addr[2] << 16) | \ + (mac_addr[1] << 8) | (mac_addr[0]); + out_be32(®s->mac_addr_0, mac_addr0); + + mac_addr1 = ((mac_addr[5] << 8) | mac_addr[4]) & 0x0000ffff; + out_be32(®s->mac_addr_1, mac_addr1); +} + +static void memac_set_interface_mode(struct fsl_enet_mac *mac, + phy_interface_t type, int speed) +{ + /* Roy need more work here */ + + struct memac *regs = mac->base; + u32 if_mode, if_status; + + /* clear all bits relative with interface mode */ + if_mode = in_be32(®s->if_mode); + if_status = in_be32(®s->if_status); + + /* set interface mode */ + switch (type) { + case PHY_INTERFACE_MODE_GMII: + if_mode &= ~IF_MODE_MASK; + if_mode |= IF_MODE_GMII; + break; + case PHY_INTERFACE_MODE_RGMII: + if_mode |= (IF_MODE_GMII | IF_MODE_RG); + break; + case PHY_INTERFACE_MODE_RMII: + if_mode |= (IF_MODE_GMII | IF_MODE_RM); + break; + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_QSGMII: + if_mode &= ~IF_MODE_MASK; + if_mode |= (IF_MODE_GMII); + break; + case PHY_INTERFACE_MODE_XGMII: + if_mode &= ~IF_MODE_MASK; + if_mode |= IF_MODE_XGMII; + break; + default: + break; + } + /* Enable automatic speed selection for Non-XGMII */ + if (type != PHY_INTERFACE_MODE_XGMII) + if_mode |= IF_MODE_EN_AUTO; + + if (type == PHY_INTERFACE_MODE_RGMII) { + if_mode &= ~IF_MODE_EN_AUTO; + if_mode &= ~IF_MODE_SETSP_MASK; + switch (speed) { + case SPEED_1000: + if_mode |= IF_MODE_SETSP_1000M; + break; + case SPEED_100: + if_mode |= IF_MODE_SETSP_100M; + break; + case SPEED_10: + if_mode |= IF_MODE_SETSP_10M; + default: + break; + } + } + + debug(" %s, if_mode = %x\n", __func__, if_mode); + debug(" %s, if_status = %x\n", __func__, if_status); + out_be32(®s->if_mode, if_mode); + return; +} + +void init_memac(struct fsl_enet_mac *mac, void *base, + void *phyregs, int max_rx_len) +{ + mac->base = base; + mac->phyregs = phyregs; + mac->max_rx_len = max_rx_len; + mac->init_mac = memac_init_mac; + mac->enable_mac = memac_enable_mac; + mac->disable_mac = memac_disable_mac; + mac->set_mac_addr = memac_set_mac_addr; + mac->set_if_mode = memac_set_interface_mode; +} diff --git a/sources/uboot-be550/drivers/net/fm/memac_phy.c b/sources/uboot-be550/drivers/net/fm/memac_phy.c new file mode 100644 index 00000000..4ab78e6c --- /dev/null +++ b/sources/uboot-be550/drivers/net/fm/memac_phy.c @@ -0,0 +1,170 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * Andy Fleming + * Roy Zang + * + * SPDX-License-Identifier: GPL-2.0+ + * Some part is taken from tsec.c + */ +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_SYS_MEMAC_LITTLE_ENDIAN +#define memac_out_32(a, v) out_le32(a, v) +#define memac_clrbits_32(a, v) clrbits_le32(a, v) +#define memac_setbits_32(a, v) setbits_le32(a, v) +#else +#define memac_out_32(a, v) out_be32(a, v) +#define memac_clrbits_32(a, v) clrbits_be32(a, v) +#define memac_setbits_32(a, v) setbits_be32(a, v) +#endif + +static u32 memac_in_32(u32 *reg) +{ +#ifdef CONFIG_SYS_MEMAC_LITTLE_ENDIAN + return in_le32(reg); +#else + return in_be32(reg); +#endif +} + +/* + * Write value to the PHY for this device to the register at regnum, waiting + * until the write is done before it returns. All PHY configuration has to be + * done through the TSEC1 MIIM regs + */ +int memac_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr, + int regnum, u16 value) +{ + u32 mdio_ctl; + struct memac_mdio_controller *regs = bus->priv; + u32 c45 = 1; /* Default to 10G interface */ + + if (dev_addr == MDIO_DEVAD_NONE) { + c45 = 0; /* clause 22 */ + dev_addr = regnum & 0x1f; + memac_clrbits_32(®s->mdio_stat, MDIO_STAT_ENC); + } else + memac_setbits_32(®s->mdio_stat, MDIO_STAT_ENC); + + /* Wait till the bus is free */ + while ((memac_in_32(®s->mdio_stat)) & MDIO_STAT_BSY) + ; + + /* Set the port and dev addr */ + mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr); + memac_out_32(®s->mdio_ctl, mdio_ctl); + + /* Set the register address */ + if (c45) + memac_out_32(®s->mdio_addr, regnum & 0xffff); + + /* Wait till the bus is free */ + while ((memac_in_32(®s->mdio_stat)) & MDIO_STAT_BSY) + ; + + /* Write the value to the register */ + memac_out_32(®s->mdio_data, MDIO_DATA(value)); + + /* Wait till the MDIO write is complete */ + while ((memac_in_32(®s->mdio_data)) & MDIO_DATA_BSY) + ; + + return 0; +} + +/* + * Reads from register regnum in the PHY for device dev, returning the value. + * Clears miimcom first. All PHY configuration has to be done through the + * TSEC1 MIIM regs + */ +int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr, + int regnum) +{ + u32 mdio_ctl; + struct memac_mdio_controller *regs = bus->priv; + u32 c45 = 1; + + if (dev_addr == MDIO_DEVAD_NONE) { + if (!strcmp(bus->name, DEFAULT_FM_TGEC_MDIO_NAME)) + return 0xffff; + c45 = 0; /* clause 22 */ + dev_addr = regnum & 0x1f; + memac_clrbits_32(®s->mdio_stat, MDIO_STAT_ENC); + } else + memac_setbits_32(®s->mdio_stat, MDIO_STAT_ENC); + + /* Wait till the bus is free */ + while ((memac_in_32(®s->mdio_stat)) & MDIO_STAT_BSY) + ; + + /* Set the Port and Device Addrs */ + mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr); + memac_out_32(®s->mdio_ctl, mdio_ctl); + + /* Set the register address */ + if (c45) + memac_out_32(®s->mdio_addr, regnum & 0xffff); + + /* Wait till the bus is free */ + while ((memac_in_32(®s->mdio_stat)) & MDIO_STAT_BSY) + ; + + /* Initiate the read */ + mdio_ctl |= MDIO_CTL_READ; + memac_out_32(®s->mdio_ctl, mdio_ctl); + + /* Wait till the MDIO write is complete */ + while ((memac_in_32(®s->mdio_data)) & MDIO_DATA_BSY) + ; + + /* Return all Fs if nothing was there */ + if (memac_in_32(®s->mdio_stat) & MDIO_STAT_RD_ER) + return 0xffff; + + return memac_in_32(®s->mdio_data) & 0xffff; +} + +int memac_mdio_reset(struct mii_dev *bus) +{ + return 0; +} + +int fm_memac_mdio_init(bd_t *bis, struct memac_mdio_info *info) +{ + struct mii_dev *bus = mdio_alloc(); + + if (!bus) { + printf("Failed to allocate FM TGEC MDIO bus\n"); + return -1; + } + + bus->read = memac_mdio_read; + bus->write = memac_mdio_write; + bus->reset = memac_mdio_reset; + sprintf(bus->name, info->name); + + bus->priv = info->regs; + + /* + * On some platforms like B4860, default value of MDIO_CLK_DIV bits + * in mdio_stat(mdio_cfg) register generates MDIO clock too high + * (much higher than 2.5MHz), violating the IEEE specs. + * On other platforms like T1040, default value of MDIO_CLK_DIV bits + * is zero, so MDIO clock is disabled. + * So, for proper functioning of MDIO, MDIO_CLK_DIV bits needs to + * be properly initialized. + * NEG bit default should be '1' as per FMAN-v3 RM, but on platform + * like T2080QDS, this bit default is '0', which leads to MDIO failure + * on XAUI PHY, so set this bit definitely. + */ + memac_setbits_32( + &((struct memac_mdio_controller *)info->regs)->mdio_stat, + MDIO_STAT_CLKDIV(258) | MDIO_STAT_NEG); + + return mdio_register(bus); +} diff --git a/sources/uboot-be550/drivers/net/fm/p1023.c b/sources/uboot-be550/drivers/net/fm/p1023.c new file mode 100644 index 00000000..b25d10ae --- /dev/null +++ b/sources/uboot-be550/drivers/net/fm/p1023.c @@ -0,0 +1,73 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include +#include + +static u32 port_to_devdisr[] = { + [FM1_DTSEC1] = MPC85xx_DEVDISR_TSEC1, + [FM1_DTSEC2] = MPC85xx_DEVDISR_TSEC2, +}; + +static int is_device_disabled(enum fm_port port) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 devdisr = in_be32(&gur->devdisr); + + return port_to_devdisr[port] & devdisr; +} + +void fman_disable_port(enum fm_port port) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + /* don't allow disabling of DTSEC1 as its needed for MDIO */ + if (port == FM1_DTSEC1) + return; + + setbits_be32(&gur->devdisr, port_to_devdisr[port]); +} + +void fman_enable_port(enum fm_port port) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + clrbits_be32(&gur->devdisr, port_to_devdisr[port]); +} + +phy_interface_t fman_port_enet_if(enum fm_port port) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 pordevsr = in_be32(&gur->pordevsr); + + if (is_device_disabled(port)) + return PHY_INTERFACE_MODE_NONE; + + /* DTSEC1 can be SGMII, RGMII or RMII */ + if (port == FM1_DTSEC1) { + if (is_serdes_configured(SGMII_FM1_DTSEC1)) + return PHY_INTERFACE_MODE_SGMII; + if (pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS) { + if (pordevsr & MPC85xx_PORDEVSR_TSEC1_PRTC) + return PHY_INTERFACE_MODE_RGMII; + else + return PHY_INTERFACE_MODE_RMII; + } + } + + /* DTSEC2 only supports SGMII or RGMII */ + if (port == FM1_DTSEC2) { + if (is_serdes_configured(SGMII_FM1_DTSEC2)) + return PHY_INTERFACE_MODE_SGMII; + if (pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS) + return PHY_INTERFACE_MODE_RGMII; + } + + return PHY_INTERFACE_MODE_NONE; +} diff --git a/sources/uboot-be550/drivers/net/fm/p4080.c b/sources/uboot-be550/drivers/net/fm/p4080.c new file mode 100644 index 00000000..de719113 --- /dev/null +++ b/sources/uboot-be550/drivers/net/fm/p4080.c @@ -0,0 +1,99 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include +#include + +static u32 port_to_devdisr[] = { + [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1, + [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2, + [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3, + [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4, + [FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1, + [FM2_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC2_1, + [FM2_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC2_2, + [FM2_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC2_3, + [FM2_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC2_4, + [FM2_10GEC1] = FSL_CORENET_DEVDISR2_10GEC2, +}; + +static int is_device_disabled(enum fm_port port) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 devdisr2 = in_be32(&gur->devdisr2); + + return port_to_devdisr[port] & devdisr2; +} + +void fman_disable_port(enum fm_port port) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + /* don't allow disabling of DTSEC1 as its needed for MDIO */ + if (port == FM1_DTSEC1) + return; + + setbits_be32(&gur->devdisr2, port_to_devdisr[port]); +} + +void fman_enable_port(enum fm_port port) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + clrbits_be32(&gur->devdisr2, port_to_devdisr[port]); +} + +phy_interface_t fman_port_enet_if(enum fm_port port) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 rcwsr11 = in_be32(&gur->rcwsr[11]); + + if (is_device_disabled(port)) + return PHY_INTERFACE_MODE_NONE; + + if ((port == FM1_10GEC1) && (is_serdes_configured(XAUI_FM1))) + return PHY_INTERFACE_MODE_XGMII; + + if ((port == FM2_10GEC1) && (is_serdes_configured(XAUI_FM2))) + return PHY_INTERFACE_MODE_XGMII; + + /* handle RGMII first */ + if ((port == FM1_DTSEC1) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) == + FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1)) + return PHY_INTERFACE_MODE_RGMII; + + if ((port == FM1_DTSEC2) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) == + FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2)) + return PHY_INTERFACE_MODE_RGMII; + + if ((port == FM2_DTSEC1) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) == + FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1)) + return PHY_INTERFACE_MODE_RGMII; + + switch (port) { + case FM1_DTSEC1: + case FM1_DTSEC2: + case FM1_DTSEC3: + case FM1_DTSEC4: + if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1)) + return PHY_INTERFACE_MODE_SGMII; + break; + case FM2_DTSEC1: + case FM2_DTSEC2: + case FM2_DTSEC3: + case FM2_DTSEC4: + if (is_serdes_configured(SGMII_FM2_DTSEC1 + port - FM2_DTSEC1)) + return PHY_INTERFACE_MODE_SGMII; + break; + default: + return PHY_INTERFACE_MODE_NONE; + } + + return PHY_INTERFACE_MODE_NONE; +} diff --git a/sources/uboot-be550/drivers/net/fm/p5020.c b/sources/uboot-be550/drivers/net/fm/p5020.c new file mode 100644 index 00000000..5c158cd5 --- /dev/null +++ b/sources/uboot-be550/drivers/net/fm/p5020.c @@ -0,0 +1,90 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include +#include + +static u32 port_to_devdisr[] = { + [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1, + [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2, + [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3, + [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4, + [FM1_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC1_5, + [FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1, +}; + +static int is_device_disabled(enum fm_port port) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 devdisr2 = in_be32(&gur->devdisr2); + + return port_to_devdisr[port] & devdisr2; +} + +void fman_disable_port(enum fm_port port) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + /* don't allow disabling of DTSEC1 as its needed for MDIO */ + if (port == FM1_DTSEC1) + return; + + setbits_be32(&gur->devdisr2, port_to_devdisr[port]); +} + +void fman_enable_port(enum fm_port port) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + clrbits_be32(&gur->devdisr2, port_to_devdisr[port]); +} + +phy_interface_t fman_port_enet_if(enum fm_port port) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 rcwsr11 = in_be32(&gur->rcwsr[11]); + + if (is_device_disabled(port)) + return PHY_INTERFACE_MODE_NONE; + + if ((port == FM1_10GEC1) && (is_serdes_configured(XAUI_FM1))) + return PHY_INTERFACE_MODE_XGMII; + + /* handle RGMII first */ + if ((port == FM1_DTSEC4) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) == + FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_RGMII)) + return PHY_INTERFACE_MODE_RGMII; + + if ((port == FM1_DTSEC4) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) == + FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_MII)) + return PHY_INTERFACE_MODE_MII; + + if ((port == FM1_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) == + FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_RGMII)) + return PHY_INTERFACE_MODE_RGMII; + + if ((port == FM1_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) == + FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_MII)) + return PHY_INTERFACE_MODE_MII; + + switch (port) { + case FM1_DTSEC1: + case FM1_DTSEC2: + case FM1_DTSEC3: + case FM1_DTSEC4: + case FM1_DTSEC5: + if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1)) + return PHY_INTERFACE_MODE_SGMII; + break; + default: + return PHY_INTERFACE_MODE_NONE; + } + + return PHY_INTERFACE_MODE_NONE; +} diff --git a/sources/uboot-be550/drivers/net/fm/p5040.c b/sources/uboot-be550/drivers/net/fm/p5040.c new file mode 100644 index 00000000..403d7d79 --- /dev/null +++ b/sources/uboot-be550/drivers/net/fm/p5040.c @@ -0,0 +1,107 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include +#include + +u32 port_to_devdisr[] = { + [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1, + [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2, + [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3, + [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4, + [FM1_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC1_5, + [FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1, + [FM2_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC2_1, + [FM2_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC2_2, + [FM2_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC2_3, + [FM2_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC2_4, + [FM2_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC2_5, + [FM2_10GEC1] = FSL_CORENET_DEVDISR2_10GEC2, +}; + +static int is_device_disabled(enum fm_port port) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 devdisr2 = in_be32(&gur->devdisr2); + + return port_to_devdisr[port] & devdisr2; +} + +void fman_disable_port(enum fm_port port) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + /* don't allow disabling of DTSEC1 as its needed for MDIO */ + if (port == FM1_DTSEC1) + return; + + setbits_be32(&gur->devdisr2, port_to_devdisr[port]); +} + +void fman_enable_port(enum fm_port port) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + clrbits_be32(&gur->devdisr2, port_to_devdisr[port]); +} + +phy_interface_t fman_port_enet_if(enum fm_port port) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 rcwsr11 = in_be32(&gur->rcwsr[11]); + + if (is_device_disabled(port)) + return PHY_INTERFACE_MODE_NONE; + + if ((port == FM1_10GEC1) && (is_serdes_configured(XAUI_FM1))) + return PHY_INTERFACE_MODE_XGMII; + + if ((port == FM2_10GEC1) && (is_serdes_configured(XAUI_FM2))) + return PHY_INTERFACE_MODE_XGMII; + + /* handle RGMII first */ + if ((port == FM1_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) == + FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_RGMII)) + return PHY_INTERFACE_MODE_RGMII; + + if ((port == FM1_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) == + FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_MII)) + return PHY_INTERFACE_MODE_MII; + + if ((port == FM2_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) == + FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_RGMII)) + return PHY_INTERFACE_MODE_RGMII; + + if ((port == FM2_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) == + FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII)) + return PHY_INTERFACE_MODE_MII; + + switch (port) { + case FM1_DTSEC1: + case FM1_DTSEC2: + case FM1_DTSEC3: + case FM1_DTSEC4: + case FM1_DTSEC5: + if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1)) + return PHY_INTERFACE_MODE_SGMII; + break; + case FM2_DTSEC1: + case FM2_DTSEC2: + case FM2_DTSEC3: + case FM2_DTSEC4: + case FM2_DTSEC5: + if (is_serdes_configured(SGMII_FM2_DTSEC1 + port - FM2_DTSEC1)) + return PHY_INTERFACE_MODE_SGMII; + break; + default: + return PHY_INTERFACE_MODE_NONE; + } + + return PHY_INTERFACE_MODE_NONE; +} diff --git a/sources/uboot-be550/drivers/net/fm/t1024.c b/sources/uboot-be550/drivers/net/fm/t1024.c new file mode 100644 index 00000000..9b311734 --- /dev/null +++ b/sources/uboot-be550/drivers/net/fm/t1024.c @@ -0,0 +1,88 @@ +/* Copyright 2014 Freescale Semiconductor, Inc. + * + * Shengzhou Liu + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +u32 port_to_devdisr[] = { + [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1, + [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2, + [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3, + [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4, + [FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1_1, /* MAC1 */ +}; + +static int is_device_disabled(enum fm_port port) +{ + ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 devdisr2 = in_be32(&gur->devdisr2); + + return port_to_devdisr[port] & devdisr2; +} + +void fman_disable_port(enum fm_port port) +{ + ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + setbits_be32(&gur->devdisr2, port_to_devdisr[port]); +} + +phy_interface_t fman_port_enet_if(enum fm_port port) +{ + ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 rcwsr13 = in_be32(&gur->rcwsr[13]); + + if (is_device_disabled(port)) + return PHY_INTERFACE_MODE_NONE; + + if ((port == FM1_10GEC1) && (is_serdes_configured(XFI_FM1_MAC1))) + return PHY_INTERFACE_MODE_XGMII; + + if ((port == FM1_DTSEC3) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) == + FSL_CORENET_RCWSR13_EC2_RGMII) && + (!is_serdes_configured(QSGMII_FM1_A))) + return PHY_INTERFACE_MODE_RGMII; + + if ((port == FM1_DTSEC4) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) == + FSL_CORENET_RCWSR13_EC1_RGMII) && + (!is_serdes_configured(QSGMII_FM1_A))) + return PHY_INTERFACE_MODE_RGMII; + + /* handle SGMII */ + switch (port) { + case FM1_DTSEC1: + case FM1_DTSEC2: + case FM1_DTSEC3: + if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1)) + return PHY_INTERFACE_MODE_SGMII; + else if (is_serdes_configured(SGMII_2500_FM1_DTSEC1 + + port - FM1_DTSEC1)) + return PHY_INTERFACE_MODE_SGMII_2500; + break; + default: + break; + } + + /* handle QSGMII */ + switch (port) { + case FM1_DTSEC1: + case FM1_DTSEC2: + case FM1_DTSEC3: + case FM1_DTSEC4: + /* check lane A on SerDes1 */ + if (is_serdes_configured(QSGMII_FM1_A)) + return PHY_INTERFACE_MODE_QSGMII; + break; + default: + break; + } + + return PHY_INTERFACE_MODE_NONE; +} diff --git a/sources/uboot-be550/drivers/net/fm/t1040.c b/sources/uboot-be550/drivers/net/fm/t1040.c new file mode 100644 index 00000000..04583661 --- /dev/null +++ b/sources/uboot-be550/drivers/net/fm/t1040.c @@ -0,0 +1,67 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include +#include + +phy_interface_t fman_port_enet_if(enum fm_port port) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 rcwsr13 = in_be32(&gur->rcwsr[13]); + + /* handle RGMII first */ + if ((port == FM1_DTSEC2) && + ((rcwsr13 & FSL_CORENET_RCWSR13_MAC2_GMII_SEL) == + FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT)) { + if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) == + FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_RGMII) + return PHY_INTERFACE_MODE_RGMII; + else if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) == + FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII) + return PHY_INTERFACE_MODE_MII; + } + + if ((port == FM1_DTSEC4) && + ((rcwsr13 & FSL_CORENET_RCWSR13_MAC2_GMII_SEL) == + FSL_CORENET_RCWSR13_MAC2_GMII_SEL_L2_SWITCH)) { + if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) == + FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_RGMII) + return PHY_INTERFACE_MODE_RGMII; + else if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) == + FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII) + return PHY_INTERFACE_MODE_MII; + } + + if (port == FM1_DTSEC5) { + if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) == + FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII) + return PHY_INTERFACE_MODE_RGMII; + else if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) == + FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_MII) + return PHY_INTERFACE_MODE_MII; + } + + switch (port) { + case FM1_DTSEC1: + case FM1_DTSEC2: + if (is_serdes_configured(QSGMII_SW1_A + port - FM1_DTSEC1) || + is_serdes_configured(SGMII_SW1_MAC1 + port - FM1_DTSEC1)) + return PHY_INTERFACE_MODE_QSGMII; + case FM1_DTSEC3: + case FM1_DTSEC4: + case FM1_DTSEC5: + if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1)) + return PHY_INTERFACE_MODE_SGMII; + break; + default: + return PHY_INTERFACE_MODE_NONE; + } + + return PHY_INTERFACE_MODE_NONE; +} diff --git a/sources/uboot-be550/drivers/net/fm/t2080.c b/sources/uboot-be550/drivers/net/fm/t2080.c new file mode 100644 index 00000000..3b6212f8 --- /dev/null +++ b/sources/uboot-be550/drivers/net/fm/t2080.c @@ -0,0 +1,93 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * Shengzhou Liu + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +u32 port_to_devdisr[] = { + [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1, + [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2, + [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3, + [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4, + [FM1_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC1_5, + [FM1_DTSEC6] = FSL_CORENET_DEVDISR2_DTSEC1_6, + [FM1_DTSEC9] = FSL_CORENET_DEVDISR2_DTSEC1_9, + [FM1_DTSEC10] = FSL_CORENET_DEVDISR2_DTSEC1_10, + [FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1_1, + [FM1_10GEC2] = FSL_CORENET_DEVDISR2_10GEC1_2, + [FM1_10GEC3] = FSL_CORENET_DEVDISR2_10GEC1_3, + [FM1_10GEC4] = FSL_CORENET_DEVDISR2_10GEC1_4, +}; + +static int is_device_disabled(enum fm_port port) +{ + ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 devdisr2 = in_be32(&gur->devdisr2); + + return port_to_devdisr[port] & devdisr2; +} + +void fman_disable_port(enum fm_port port) +{ + ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + setbits_be32(&gur->devdisr2, port_to_devdisr[port]); +} + +phy_interface_t fman_port_enet_if(enum fm_port port) +{ + ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 rcwsr13 = in_be32(&gur->rcwsr[13]); + + if (is_device_disabled(port)) + return PHY_INTERFACE_MODE_NONE; + + if ((port == FM1_10GEC1 || port == FM1_10GEC2) && + ((is_serdes_configured(XAUI_FM1_MAC9)) || + (is_serdes_configured(XFI_FM1_MAC9)) || + (is_serdes_configured(XFI_FM1_MAC10)))) + return PHY_INTERFACE_MODE_XGMII; + + if ((port == FM1_10GEC3 || port == FM1_10GEC4) && + ((is_serdes_configured(XFI_FM1_MAC1)) || + (is_serdes_configured(XFI_FM1_MAC2)))) + return PHY_INTERFACE_MODE_XGMII; + + if ((port == FM1_DTSEC3) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) == + FSL_CORENET_RCWSR13_EC1_DTSEC3_RGMII)) + return PHY_INTERFACE_MODE_RGMII; + + if ((port == FM1_DTSEC4) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) == + FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII)) + return PHY_INTERFACE_MODE_RGMII; + + if ((port == FM1_DTSEC10) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) == + FSL_CORENET_RCWSR13_EC2_DTSEC10_RGMII)) + return PHY_INTERFACE_MODE_RGMII; + + switch (port) { + case FM1_DTSEC1: + case FM1_DTSEC2: + case FM1_DTSEC3: + case FM1_DTSEC4: + case FM1_DTSEC5: + case FM1_DTSEC6: + case FM1_DTSEC9: + case FM1_DTSEC10: + if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1)) + return PHY_INTERFACE_MODE_SGMII; + break; + default: + return PHY_INTERFACE_MODE_NONE; + } + + return PHY_INTERFACE_MODE_NONE; +} diff --git a/sources/uboot-be550/drivers/net/fm/t4240.c b/sources/uboot-be550/drivers/net/fm/t4240.c new file mode 100644 index 00000000..ae5aca4b --- /dev/null +++ b/sources/uboot-be550/drivers/net/fm/t4240.c @@ -0,0 +1,171 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * Roy Zang + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include +#include + +u32 port_to_devdisr[] = { + [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1, + [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2, + [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3, + [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4, + [FM1_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC1_5, + [FM1_DTSEC6] = FSL_CORENET_DEVDISR2_DTSEC1_6, + [FM1_DTSEC9] = FSL_CORENET_DEVDISR2_DTSEC1_9, + [FM1_DTSEC10] = FSL_CORENET_DEVDISR2_DTSEC1_10, + [FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1_1, + [FM1_10GEC2] = FSL_CORENET_DEVDISR2_10GEC1_2, + [FM2_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC2_1, + [FM2_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC2_2, + [FM2_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC2_3, + [FM2_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC2_4, + [FM2_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC2_5, + [FM2_DTSEC6] = FSL_CORENET_DEVDISR2_DTSEC2_6, + [FM2_DTSEC9] = FSL_CORENET_DEVDISR2_DTSEC2_9, + [FM2_DTSEC10] = FSL_CORENET_DEVDISR2_DTSEC2_10, + [FM2_10GEC1] = FSL_CORENET_DEVDISR2_10GEC2_1, + [FM2_10GEC2] = FSL_CORENET_DEVDISR2_10GEC2_2, +}; + +static int is_device_disabled(enum fm_port port) +{ + ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 devdisr2 = in_be32(&gur->devdisr2); + + return port_to_devdisr[port] & devdisr2; +} + +void fman_disable_port(enum fm_port port) +{ + ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + setbits_be32(&gur->devdisr2, port_to_devdisr[port]); +} + +void fman_enable_port(enum fm_port port) +{ + ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + clrbits_be32(&gur->devdisr2, port_to_devdisr[port]); +} + +phy_interface_t fman_port_enet_if(enum fm_port port) +{ + ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 rcwsr13 = in_be32(&gur->rcwsr[13]); + + if (is_device_disabled(port)) + return PHY_INTERFACE_MODE_NONE; + + if ((port == FM1_10GEC1 || port == FM1_10GEC2) && + ((is_serdes_configured(XAUI_FM1_MAC9)) || + (is_serdes_configured(XAUI_FM1_MAC10)) || + (is_serdes_configured(XFI_FM1_MAC9)) || + (is_serdes_configured(XFI_FM1_MAC10)))) + return PHY_INTERFACE_MODE_XGMII; + + if ((port == FM1_DTSEC9 || port == FM1_DTSEC10) && + ((is_serdes_configured(XFI_FM1_MAC9)) || + (is_serdes_configured(XFI_FM1_MAC10)))) + return PHY_INTERFACE_MODE_XGMII; + + if ((port == FM2_10GEC1 || port == FM2_10GEC2) && + ((is_serdes_configured(XAUI_FM2_MAC9)) || + (is_serdes_configured(XAUI_FM2_MAC10)) || + (is_serdes_configured(XFI_FM2_MAC9)) || + (is_serdes_configured(XFI_FM2_MAC10)))) + return PHY_INTERFACE_MODE_XGMII; + +#define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */ +#define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII 0x00000000 +#define FSL_CORENET_RCWSR13_EC1_FM2_GPIO 0x40000000 +#define FSL_CORENET_RCWSR13_EC2 0x18000000 /* bits 419..420 */ +#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII 0x00000000 +#define FSL_CORENET_RCWSR13_EC2_FM2_DTSEC6_RGMII 0x08000000 +#define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000 + /* handle RGMII first */ + if ((port == FM2_DTSEC5) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) == + FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII)) + return PHY_INTERFACE_MODE_RGMII; + + if ((port == FM1_DTSEC5) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) == + FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII)) + return PHY_INTERFACE_MODE_RGMII; + + if ((port == FM2_DTSEC6) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) == + FSL_CORENET_RCWSR13_EC2_FM2_DTSEC6_RGMII)) + return PHY_INTERFACE_MODE_RGMII; + switch (port) { + case FM1_DTSEC1: + case FM1_DTSEC2: + case FM1_DTSEC3: + case FM1_DTSEC4: + case FM1_DTSEC5: + case FM1_DTSEC6: + case FM1_DTSEC9: + case FM1_DTSEC10: + if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1)) + return PHY_INTERFACE_MODE_SGMII; + break; + case FM2_DTSEC1: + case FM2_DTSEC2: + case FM2_DTSEC3: + case FM2_DTSEC4: + case FM2_DTSEC5: + case FM2_DTSEC6: + case FM2_DTSEC9: + case FM2_DTSEC10: + if (is_serdes_configured(SGMII_FM2_DTSEC1 + port - FM2_DTSEC1)) + return PHY_INTERFACE_MODE_SGMII; + break; + default: + break; + } + + /* handle QSGMII */ + switch (port) { + case FM1_DTSEC1: + case FM1_DTSEC2: + case FM1_DTSEC3: + case FM1_DTSEC4: + /* check lane G on SerDes1 */ + if (is_serdes_configured(QSGMII_FM1_A)) + return PHY_INTERFACE_MODE_QSGMII; + break; + case FM1_DTSEC5: + case FM1_DTSEC6: + case FM1_DTSEC9: + case FM1_DTSEC10: + /* check lane C on SerDes1 */ + if (is_serdes_configured(QSGMII_FM1_B)) + return PHY_INTERFACE_MODE_QSGMII; + break; + case FM2_DTSEC1: + case FM2_DTSEC2: + case FM2_DTSEC3: + case FM2_DTSEC4: + /* check lane G on SerDes2 */ + if (is_serdes_configured(QSGMII_FM2_A)) + return PHY_INTERFACE_MODE_QSGMII; + break; + case FM2_DTSEC5: + case FM2_DTSEC6: + case FM2_DTSEC9: + case FM2_DTSEC10: + /* check lane C on SerDes2 */ + if (is_serdes_configured(QSGMII_FM2_B)) + return PHY_INTERFACE_MODE_QSGMII; + break; + default: + break; + } + + return PHY_INTERFACE_MODE_NONE; +} diff --git a/sources/uboot-be550/drivers/net/fm/tgec.c b/sources/uboot-be550/drivers/net/fm/tgec.c new file mode 100644 index 00000000..8d4622ff --- /dev/null +++ b/sources/uboot-be550/drivers/net/fm/tgec.c @@ -0,0 +1,105 @@ +/* + * Copyright 2009-2011 Freescale Semiconductor, Inc. + * Dave Liu + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* MAXFRM - maximum frame length */ +#define MAXFRM_MASK 0x0000ffff + +#include +#include +#include +#include +#include + +#include "fm.h" + +#define TGEC_CMD_CFG_INIT (TGEC_CMD_CFG_NO_LEN_CHK | \ + TGEC_CMD_CFG_RX_ER_DISC | \ + TGEC_CMD_CFG_STAT_CLR | \ + TGEC_CMD_CFG_PAUSE_IGNORE | \ + TGEC_CMD_CFG_CRC_FWD) +#define TGEC_CMD_CFG_FINAL (TGEC_CMD_CFG_NO_LEN_CHK | \ + TGEC_CMD_CFG_RX_ER_DISC | \ + TGEC_CMD_CFG_PAUSE_IGNORE | \ + TGEC_CMD_CFG_CRC_FWD) + +static void tgec_init_mac(struct fsl_enet_mac *mac) +{ + struct tgec *regs = mac->base; + + /* mask all interrupt */ + out_be32(®s->imask, IMASK_MASK_ALL); + + /* clear all events */ + out_be32(®s->ievent, IEVENT_CLEAR_ALL); + + /* set the max receive length */ + out_be32(®s->maxfrm, mac->max_rx_len & MAXFRM_MASK); + + /* + * 1588 disable, insert second mac disable payload length check + * disable, normal operation, any rx error frame is discarded, clear + * counters, pause frame ignore, no promiscuous, LAN mode Rx CRC no + * strip, Tx CRC append, Rx disable and Tx disable + */ + out_be32(®s->command_config, TGEC_CMD_CFG_INIT); + udelay(1000); + out_be32(®s->command_config, TGEC_CMD_CFG_FINAL); + + /* multicast frame reception for the hash entry disable */ + out_be32(®s->hashtable_ctrl, 0); +} + +static void tgec_enable_mac(struct fsl_enet_mac *mac) +{ + struct tgec *regs = mac->base; + + setbits_be32(®s->command_config, TGEC_CMD_CFG_RXTX_EN); +} + +static void tgec_disable_mac(struct fsl_enet_mac *mac) +{ + struct tgec *regs = mac->base; + + clrbits_be32(®s->command_config, TGEC_CMD_CFG_RXTX_EN); +} + +static void tgec_set_mac_addr(struct fsl_enet_mac *mac, u8 *mac_addr) +{ + struct tgec *regs = mac->base; + u32 mac_addr0, mac_addr1; + + /* + * if a station address of 0x12345678ABCD, perform a write to + * MAC_ADDR0 of 0x78563412, MAC_ADDR1 of 0x0000CDAB + */ + mac_addr0 = (mac_addr[3] << 24) | (mac_addr[2] << 16) | \ + (mac_addr[1] << 8) | (mac_addr[0]); + out_be32(®s->mac_addr_0, mac_addr0); + + mac_addr1 = ((mac_addr[5] << 8) | mac_addr[4]) & 0x0000ffff; + out_be32(®s->mac_addr_1, mac_addr1); +} + +static void tgec_set_interface_mode(struct fsl_enet_mac *mac, + phy_interface_t type, int speed) +{ + /* nothing right now */ + return; +} + +void init_tgec(struct fsl_enet_mac *mac, void *base, + void *phyregs, int max_rx_len) +{ + mac->base = base; + mac->phyregs = phyregs; + mac->max_rx_len = max_rx_len; + mac->init_mac = tgec_init_mac; + mac->enable_mac = tgec_enable_mac; + mac->disable_mac = tgec_disable_mac; + mac->set_mac_addr = tgec_set_mac_addr; + mac->set_if_mode = tgec_set_interface_mode; +} diff --git a/sources/uboot-be550/drivers/net/fm/tgec_phy.c b/sources/uboot-be550/drivers/net/fm/tgec_phy.c new file mode 100644 index 00000000..24cb17b6 --- /dev/null +++ b/sources/uboot-be550/drivers/net/fm/tgec_phy.c @@ -0,0 +1,126 @@ +/* + * Copyright 2009-2011 Freescale Semiconductor, Inc. + * Andy Fleming + * + * SPDX-License-Identifier: GPL-2.0+ + * Some part is taken from tsec.c + */ +#include +#include +#include +#include +#include +#include + +/* + * Write value to the PHY for this device to the register at regnum, waiting + * until the write is done before it returns. All PHY configuration has to be + * done through the TSEC1 MIIM regs + */ +static int tgec_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr, + int regnum, u16 value) +{ + u32 mdio_ctl; + u32 stat_val; + struct tgec_mdio_controller *regs = bus->priv; + + if (dev_addr == MDIO_DEVAD_NONE) + return 0; + + /* Wait till the bus is free */ + stat_val = MDIO_STAT_CLKDIV(100); + out_be32(®s->mdio_stat, stat_val); + while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY) + ; + + /* Set the port and dev addr */ + mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr); + out_be32(®s->mdio_ctl, mdio_ctl); + + /* Set the register address */ + out_be32(®s->mdio_addr, regnum & 0xffff); + + /* Wait till the bus is free */ + while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY) + ; + + /* Write the value to the register */ + out_be32(®s->mdio_data, MDIO_DATA(value)); + + /* Wait till the MDIO write is complete */ + while ((in_be32(®s->mdio_data)) & MDIO_DATA_BSY) + ; + + return 0; +} + +/* + * Reads from register regnum in the PHY for device dev, returning the value. + * Clears miimcom first. All PHY configuration has to be done through the + * TSEC1 MIIM regs + */ +static int tgec_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr, + int regnum) +{ + u32 mdio_ctl; + u32 stat_val; + struct tgec_mdio_controller *regs = bus->priv; + + if (dev_addr == MDIO_DEVAD_NONE) + return 0xffff; + + stat_val = MDIO_STAT_CLKDIV(100); + out_be32(®s->mdio_stat, stat_val); + /* Wait till the bus is free */ + while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY) + ; + + /* Set the Port and Device Addrs */ + mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr); + out_be32(®s->mdio_ctl, mdio_ctl); + + /* Set the register address */ + out_be32(®s->mdio_addr, regnum & 0xffff); + + /* Wait till the bus is free */ + while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY) + ; + + /* Initiate the read */ + mdio_ctl |= MDIO_CTL_READ; + out_be32(®s->mdio_ctl, mdio_ctl); + + /* Wait till the MDIO write is complete */ + while ((in_be32(®s->mdio_data)) & MDIO_DATA_BSY) + ; + + /* Return all Fs if nothing was there */ + if (in_be32(®s->mdio_stat) & MDIO_STAT_RD_ER) + return 0xffff; + + return in_be32(®s->mdio_data) & 0xffff; +} + +static int tgec_mdio_reset(struct mii_dev *bus) +{ + return 0; +} + +int fm_tgec_mdio_init(bd_t *bis, struct tgec_mdio_info *info) +{ + struct mii_dev *bus = mdio_alloc(); + + if (!bus) { + printf("Failed to allocate FM TGEC MDIO bus\n"); + return -1; + } + + bus->read = tgec_mdio_read; + bus->write = tgec_mdio_write; + bus->reset = tgec_mdio_reset; + sprintf(bus->name, info->name); + + bus->priv = info->regs; + + return mdio_register(bus); +} diff --git a/sources/uboot-be550/drivers/net/fsl-mc/Makefile b/sources/uboot-be550/drivers/net/fsl-mc/Makefile new file mode 100644 index 00000000..a4923888 --- /dev/null +++ b/sources/uboot-be550/drivers/net/fsl-mc/Makefile @@ -0,0 +1,15 @@ +# +# Copyright 2014 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +# Layerscape MC driver +obj-y += mc.o \ + mc_sys.o \ + dpmng.o \ + dprc.o \ + dpbp.o \ + dpni.o \ + dpmac.o +obj-y += dpio/ diff --git a/sources/uboot-be550/drivers/net/fsl-mc/dpbp.c b/sources/uboot-be550/drivers/net/fsl-mc/dpbp.c new file mode 100644 index 00000000..ba9536d4 --- /dev/null +++ b/sources/uboot-be550/drivers/net/fsl-mc/dpbp.c @@ -0,0 +1,159 @@ +/* + * Freescale Layerscape MC I/O wrapper + * + * Copyright (C) 2013-2015 Freescale Semiconductor, Inc. + * Author: German Rivera + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include + +int dpbp_open(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + int dpbp_id, + uint16_t *token) +{ + struct mc_command cmd = { 0 }; + int err; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPBP_CMDID_OPEN, + cmd_flags, + 0); + DPBP_CMD_OPEN(cmd, dpbp_id); + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + /* retrieve response parameters */ + *token = MC_CMD_HDR_READ_TOKEN(cmd.header); + + return err; +} + +int dpbp_close(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token) +{ + struct mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPBP_CMDID_CLOSE, cmd_flags, + token); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} + +int dpbp_create(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + const struct dpbp_cfg *cfg, + uint16_t *token) +{ + struct mc_command cmd = { 0 }; + int err; + + (void)(cfg); /* unused */ + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPBP_CMDID_CREATE, + cmd_flags, + 0); + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + /* retrieve response parameters */ + *token = MC_CMD_HDR_READ_TOKEN(cmd.header); + + return 0; +} + +int dpbp_destroy(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token) +{ + struct mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPBP_CMDID_DESTROY, + cmd_flags, + token); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} + +int dpbp_enable(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token) +{ + struct mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPBP_CMDID_ENABLE, cmd_flags, + token); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} + +int dpbp_disable(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token) +{ + struct mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPBP_CMDID_DISABLE, + cmd_flags, + token); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} + +int dpbp_reset(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token) +{ + struct mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPBP_CMDID_RESET, + cmd_flags, + token); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} + +int dpbp_get_attributes(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + struct dpbp_attr *attr) +{ + struct mc_command cmd = { 0 }; + int err; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPBP_CMDID_GET_ATTR, + cmd_flags, + token); + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + /* retrieve response parameters */ + DPBP_RSP_GET_ATTRIBUTES(cmd, attr); + + return 0; +} diff --git a/sources/uboot-be550/drivers/net/fsl-mc/dpio/Makefile b/sources/uboot-be550/drivers/net/fsl-mc/dpio/Makefile new file mode 100644 index 00000000..1ccefc0d --- /dev/null +++ b/sources/uboot-be550/drivers/net/fsl-mc/dpio/Makefile @@ -0,0 +1,9 @@ +# +# Copyright 2014 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +# Layerscape MC DPIO driver +obj-y += dpio.o \ + qbman_portal.o diff --git a/sources/uboot-be550/drivers/net/fsl-mc/dpio/dpio.c b/sources/uboot-be550/drivers/net/fsl-mc/dpio/dpio.c new file mode 100644 index 00000000..b61df528 --- /dev/null +++ b/sources/uboot-be550/drivers/net/fsl-mc/dpio/dpio.c @@ -0,0 +1,158 @@ +/* + * Copyright (C) 2013-2015 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +int dpio_open(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + int dpio_id, + uint16_t *token) +{ + struct mc_command cmd = { 0 }; + int err; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPIO_CMDID_OPEN, + cmd_flags, + 0); + DPIO_CMD_OPEN(cmd, dpio_id); + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + /* retrieve response parameters */ + *token = MC_CMD_HDR_READ_TOKEN(cmd.header); + + return 0; +} + +int dpio_close(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token) +{ + struct mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPIO_CMDID_CLOSE, + cmd_flags, + token); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} + +int dpio_create(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + const struct dpio_cfg *cfg, + uint16_t *token) +{ + struct mc_command cmd = { 0 }; + int err; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPIO_CMDID_CREATE, + cmd_flags, + 0); + DPIO_CMD_CREATE(cmd, cfg); + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + /* retrieve response parameters */ + *token = MC_CMD_HDR_READ_TOKEN(cmd.header); + + return 0; +} + +int dpio_destroy(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token) +{ + struct mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPIO_CMDID_DESTROY, + cmd_flags, + token); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} + +int dpio_enable(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token) +{ + struct mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPIO_CMDID_ENABLE, + cmd_flags, + token); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} + +int dpio_disable(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token) +{ + struct mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPIO_CMDID_DISABLE, + cmd_flags, + token); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} + +int dpio_reset(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token) +{ + struct mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPIO_CMDID_RESET, + cmd_flags, + token); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} + +int dpio_get_attributes(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + struct dpio_attr *attr) +{ + struct mc_command cmd = { 0 }; + int err; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPIO_CMDID_GET_ATTR, + cmd_flags, + token); + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + /* retrieve response parameters */ + DPIO_RSP_GET_ATTR(cmd, attr); + + return 0; +} diff --git a/sources/uboot-be550/drivers/net/fsl-mc/dpio/qbman_portal.c b/sources/uboot-be550/drivers/net/fsl-mc/dpio/qbman_portal.c new file mode 100644 index 00000000..449ff8a8 --- /dev/null +++ b/sources/uboot-be550/drivers/net/fsl-mc/dpio/qbman_portal.c @@ -0,0 +1,599 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "qbman_portal.h" + +/* QBMan portal management command codes */ +#define QBMAN_MC_ACQUIRE 0x30 +#define QBMAN_WQCHAN_CONFIGURE 0x46 + +/* CINH register offsets */ +#define QBMAN_CINH_SWP_EQAR 0x8c0 +#define QBMAN_CINH_SWP_DCAP 0xac0 +#define QBMAN_CINH_SWP_SDQCR 0xb00 +#define QBMAN_CINH_SWP_RAR 0xcc0 + +/* CENA register offsets */ +#define QBMAN_CENA_SWP_EQCR(n) (0x000 + ((uint32_t)(n) << 6)) +#define QBMAN_CENA_SWP_DQRR(n) (0x200 + ((uint32_t)(n) << 6)) +#define QBMAN_CENA_SWP_RCR(n) (0x400 + ((uint32_t)(n) << 6)) +#define QBMAN_CENA_SWP_CR 0x600 +#define QBMAN_CENA_SWP_RR(vb) (0x700 + ((uint32_t)(vb) >> 1)) +#define QBMAN_CENA_SWP_VDQCR 0x780 + +/* Reverse mapping of QBMAN_CENA_SWP_DQRR() */ +#define QBMAN_IDX_FROM_DQRR(p) (((unsigned long)p & 0xff) >> 6) + +/*******************************/ +/* Pre-defined attribute codes */ +/*******************************/ + +struct qb_attr_code code_generic_verb = QB_CODE(0, 0, 7); +struct qb_attr_code code_generic_rslt = QB_CODE(0, 8, 8); + +/*************************/ +/* SDQCR attribute codes */ +/*************************/ + +/* we put these here because at least some of them are required by + * qbman_swp_init() */ +struct qb_attr_code code_sdqcr_dct = QB_CODE(0, 24, 2); +struct qb_attr_code code_sdqcr_fc = QB_CODE(0, 29, 1); +struct qb_attr_code code_sdqcr_tok = QB_CODE(0, 16, 8); +#define CODE_SDQCR_DQSRC(n) QB_CODE(0, n, 1) +enum qbman_sdqcr_dct { + qbman_sdqcr_dct_null = 0, + qbman_sdqcr_dct_prio_ics, + qbman_sdqcr_dct_active_ics, + qbman_sdqcr_dct_active +}; +enum qbman_sdqcr_fc { + qbman_sdqcr_fc_one = 0, + qbman_sdqcr_fc_up_to_3 = 1 +}; + +/*********************************/ +/* Portal constructor/destructor */ +/*********************************/ + +/* Software portals should always be in the power-on state when we initialise, + * due to the CCSR-based portal reset functionality that MC has. */ +struct qbman_swp *qbman_swp_init(const struct qbman_swp_desc *d) +{ + int ret; + struct qbman_swp *p = malloc(sizeof(struct qbman_swp)); + + if (!p) + return NULL; + p->desc = d; +#ifdef QBMAN_CHECKING + p->mc.check = swp_mc_can_start; +#endif + p->mc.valid_bit = QB_VALID_BIT; + p->sdq = 0; + qb_attr_code_encode(&code_sdqcr_dct, &p->sdq, qbman_sdqcr_dct_prio_ics); + qb_attr_code_encode(&code_sdqcr_fc, &p->sdq, qbman_sdqcr_fc_up_to_3); + qb_attr_code_encode(&code_sdqcr_tok, &p->sdq, 0xbb); + atomic_set(&p->vdq.busy, 1); + p->vdq.valid_bit = QB_VALID_BIT; + p->dqrr.next_idx = 0; + p->dqrr.valid_bit = QB_VALID_BIT; + ret = qbman_swp_sys_init(&p->sys, d); + if (ret) { + free(p); + printf("qbman_swp_sys_init() failed %d\n", ret); + return NULL; + } + qbman_cinh_write(&p->sys, QBMAN_CINH_SWP_SDQCR, p->sdq); + return p; +} + +/***********************/ +/* Management commands */ +/***********************/ + +/* + * Internal code common to all types of management commands. + */ + +void *qbman_swp_mc_start(struct qbman_swp *p) +{ + void *ret; +#ifdef QBMAN_CHECKING + BUG_ON(p->mc.check != swp_mc_can_start); +#endif + ret = qbman_cena_write_start(&p->sys, QBMAN_CENA_SWP_CR); +#ifdef QBMAN_CHECKING + if (!ret) + p->mc.check = swp_mc_can_submit; +#endif + return ret; +} + +void qbman_swp_mc_submit(struct qbman_swp *p, void *cmd, uint32_t cmd_verb) +{ + uint32_t *v = cmd; +#ifdef QBMAN_CHECKING + BUG_ON(p->mc.check != swp_mc_can_submit); +#endif + lwsync(); + /* TBD: "|=" is going to hurt performance. Need to move as many fields + * out of word zero, and for those that remain, the "OR" needs to occur + * at the caller side. This debug check helps to catch cases where the + * caller wants to OR but has forgotten to do so. */ + BUG_ON((*v & cmd_verb) != *v); + *v = cmd_verb | p->mc.valid_bit; + qbman_cena_write_complete(&p->sys, QBMAN_CENA_SWP_CR, cmd); + /* TODO: add prefetch support for GPP */ +#ifdef QBMAN_CHECKING + p->mc.check = swp_mc_can_poll; +#endif +} + +void *qbman_swp_mc_result(struct qbman_swp *p) +{ + uint32_t *ret, verb; +#ifdef QBMAN_CHECKING + BUG_ON(p->mc.check != swp_mc_can_poll); +#endif + ret = qbman_cena_read(&p->sys, QBMAN_CENA_SWP_RR(p->mc.valid_bit)); + /* Remove the valid-bit - command completed iff the rest is non-zero */ + verb = ret[0] & ~QB_VALID_BIT; + if (!verb) + return NULL; +#ifdef QBMAN_CHECKING + p->mc.check = swp_mc_can_start; +#endif + p->mc.valid_bit ^= QB_VALID_BIT; + return ret; +} + +/***********/ +/* Enqueue */ +/***********/ + +/* These should be const, eventually */ +static struct qb_attr_code code_eq_cmd = QB_CODE(0, 0, 2); +static struct qb_attr_code code_eq_orp_en = QB_CODE(0, 2, 1); +static struct qb_attr_code code_eq_tgt_id = QB_CODE(2, 0, 24); +/* static struct qb_attr_code code_eq_tag = QB_CODE(3, 0, 32); */ +static struct qb_attr_code code_eq_qd_en = QB_CODE(0, 4, 1); +static struct qb_attr_code code_eq_qd_bin = QB_CODE(4, 0, 16); +static struct qb_attr_code code_eq_qd_pri = QB_CODE(4, 16, 4); +static struct qb_attr_code code_eq_rsp_stash = QB_CODE(5, 16, 1); +static struct qb_attr_code code_eq_rsp_lo = QB_CODE(6, 0, 32); + +enum qbman_eq_cmd_e { + /* No enqueue, primarily for plugging ORP gaps for dropped frames */ + qbman_eq_cmd_empty, + /* DMA an enqueue response once complete */ + qbman_eq_cmd_respond, + /* DMA an enqueue response only if the enqueue fails */ + qbman_eq_cmd_respond_reject +}; + +void qbman_eq_desc_clear(struct qbman_eq_desc *d) +{ + memset(d, 0, sizeof(*d)); +} + +void qbman_eq_desc_set_no_orp(struct qbman_eq_desc *d, int respond_success) +{ + uint32_t *cl = qb_cl(d); + + qb_attr_code_encode(&code_eq_orp_en, cl, 0); + qb_attr_code_encode(&code_eq_cmd, cl, + respond_success ? qbman_eq_cmd_respond : + qbman_eq_cmd_respond_reject); +} + +void qbman_eq_desc_set_response(struct qbman_eq_desc *d, + dma_addr_t storage_phys, + int stash) +{ + uint32_t *cl = qb_cl(d); + + qb_attr_code_encode_64(&code_eq_rsp_lo, (uint64_t *)cl, storage_phys); + qb_attr_code_encode(&code_eq_rsp_stash, cl, !!stash); +} + + +void qbman_eq_desc_set_qd(struct qbman_eq_desc *d, uint32_t qdid, + uint32_t qd_bin, uint32_t qd_prio) +{ + uint32_t *cl = qb_cl(d); + + qb_attr_code_encode(&code_eq_qd_en, cl, 1); + qb_attr_code_encode(&code_eq_tgt_id, cl, qdid); + qb_attr_code_encode(&code_eq_qd_bin, cl, qd_bin); + qb_attr_code_encode(&code_eq_qd_pri, cl, qd_prio); +} + +#define EQAR_IDX(eqar) ((eqar) & 0x7) +#define EQAR_VB(eqar) ((eqar) & 0x80) +#define EQAR_SUCCESS(eqar) ((eqar) & 0x100) + +int qbman_swp_enqueue(struct qbman_swp *s, const struct qbman_eq_desc *d, + const struct qbman_fd *fd) +{ + uint32_t *p; + const uint32_t *cl = qb_cl(d); + uint32_t eqar = qbman_cinh_read(&s->sys, QBMAN_CINH_SWP_EQAR); + debug("EQAR=%08x\n", eqar); + if (!EQAR_SUCCESS(eqar)) + return -EBUSY; + p = qbman_cena_write_start(&s->sys, + QBMAN_CENA_SWP_EQCR(EQAR_IDX(eqar))); + word_copy(&p[1], &cl[1], 7); + word_copy(&p[8], fd, sizeof(*fd) >> 2); + lwsync(); + /* Set the verb byte, have to substitute in the valid-bit */ + p[0] = cl[0] | EQAR_VB(eqar); + qbman_cena_write_complete(&s->sys, + QBMAN_CENA_SWP_EQCR(EQAR_IDX(eqar)), + p); + return 0; +} + +/***************************/ +/* Volatile (pull) dequeue */ +/***************************/ + +/* These should be const, eventually */ +static struct qb_attr_code code_pull_dct = QB_CODE(0, 0, 2); +static struct qb_attr_code code_pull_dt = QB_CODE(0, 2, 2); +static struct qb_attr_code code_pull_rls = QB_CODE(0, 4, 1); +static struct qb_attr_code code_pull_stash = QB_CODE(0, 5, 1); +static struct qb_attr_code code_pull_numframes = QB_CODE(0, 8, 4); +static struct qb_attr_code code_pull_token = QB_CODE(0, 16, 8); +static struct qb_attr_code code_pull_dqsource = QB_CODE(1, 0, 24); +static struct qb_attr_code code_pull_rsp_lo = QB_CODE(2, 0, 32); + +enum qb_pull_dt_e { + qb_pull_dt_channel, + qb_pull_dt_workqueue, + qb_pull_dt_framequeue +}; + +void qbman_pull_desc_clear(struct qbman_pull_desc *d) +{ + memset(d, 0, sizeof(*d)); +} + +void qbman_pull_desc_set_storage(struct qbman_pull_desc *d, + struct ldpaa_dq *storage, + dma_addr_t storage_phys, + int stash) +{ + uint32_t *cl = qb_cl(d); + + /* Squiggle the pointer 'storage' into the extra 2 words of the + * descriptor (which aren't copied to the hw command) */ + *(void **)&cl[4] = storage; + if (!storage) { + qb_attr_code_encode(&code_pull_rls, cl, 0); + return; + } + qb_attr_code_encode(&code_pull_rls, cl, 1); + qb_attr_code_encode(&code_pull_stash, cl, !!stash); + qb_attr_code_encode_64(&code_pull_rsp_lo, (uint64_t *)cl, storage_phys); +} + +void qbman_pull_desc_set_numframes(struct qbman_pull_desc *d, uint8_t numframes) +{ + uint32_t *cl = qb_cl(d); + + BUG_ON(!numframes || (numframes > 16)); + qb_attr_code_encode(&code_pull_numframes, cl, + (uint32_t)(numframes - 1)); +} + +void qbman_pull_desc_set_token(struct qbman_pull_desc *d, uint8_t token) +{ + uint32_t *cl = qb_cl(d); + + qb_attr_code_encode(&code_pull_token, cl, token); +} + +void qbman_pull_desc_set_fq(struct qbman_pull_desc *d, uint32_t fqid) +{ + uint32_t *cl = qb_cl(d); + + qb_attr_code_encode(&code_pull_dct, cl, 1); + qb_attr_code_encode(&code_pull_dt, cl, qb_pull_dt_framequeue); + qb_attr_code_encode(&code_pull_dqsource, cl, fqid); +} + +int qbman_swp_pull(struct qbman_swp *s, struct qbman_pull_desc *d) +{ + uint32_t *p; + uint32_t *cl = qb_cl(d); + + if (!atomic_dec_and_test(&s->vdq.busy)) { + atomic_inc(&s->vdq.busy); + return -EBUSY; + } + s->vdq.storage = *(void **)&cl[4]; + s->vdq.token = qb_attr_code_decode(&code_pull_token, cl); + p = qbman_cena_write_start(&s->sys, QBMAN_CENA_SWP_VDQCR); + word_copy(&p[1], &cl[1], 3); + lwsync(); + /* Set the verb byte, have to substitute in the valid-bit */ + p[0] = cl[0] | s->vdq.valid_bit; + s->vdq.valid_bit ^= QB_VALID_BIT; + qbman_cena_write_complete(&s->sys, QBMAN_CENA_SWP_VDQCR, p); + return 0; +} + +/****************/ +/* Polling DQRR */ +/****************/ + +static struct qb_attr_code code_dqrr_verb = QB_CODE(0, 0, 8); +static struct qb_attr_code code_dqrr_response = QB_CODE(0, 0, 7); +static struct qb_attr_code code_dqrr_stat = QB_CODE(0, 8, 8); + +#define QBMAN_DQRR_RESPONSE_DQ 0x60 +#define QBMAN_DQRR_RESPONSE_FQRN 0x21 +#define QBMAN_DQRR_RESPONSE_FQRNI 0x22 +#define QBMAN_DQRR_RESPONSE_FQPN 0x24 +#define QBMAN_DQRR_RESPONSE_FQDAN 0x25 +#define QBMAN_DQRR_RESPONSE_CDAN 0x26 +#define QBMAN_DQRR_RESPONSE_CSCN_MEM 0x27 +#define QBMAN_DQRR_RESPONSE_CGCU 0x28 +#define QBMAN_DQRR_RESPONSE_BPSCN 0x29 +#define QBMAN_DQRR_RESPONSE_CSCN_WQ 0x2a + + +/* NULL return if there are no unconsumed DQRR entries. Returns a DQRR entry + * only once, so repeated calls can return a sequence of DQRR entries, without + * requiring they be consumed immediately or in any particular order. */ +const struct ldpaa_dq *qbman_swp_dqrr_next(struct qbman_swp *s) +{ + uint32_t verb; + uint32_t response_verb; + uint32_t flags; + const struct ldpaa_dq *dq; + const uint32_t *p; + + dq = qbman_cena_read(&s->sys, QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx)); + p = qb_cl(dq); + verb = qb_attr_code_decode(&code_dqrr_verb, p); + + /* If the valid-bit isn't of the expected polarity, nothing there. Note, + * in the DQRR reset bug workaround, we shouldn't need to skip these + * check, because we've already determined that a new entry is available + * and we've invalidated the cacheline before reading it, so the + * valid-bit behaviour is repaired and should tell us what we already + * knew from reading PI. + */ + if ((verb & QB_VALID_BIT) != s->dqrr.valid_bit) { + qbman_cena_invalidate_prefetch(&s->sys, + QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx)); + return NULL; + } + /* There's something there. Move "next_idx" attention to the next ring + * entry (and prefetch it) before returning what we found. */ + s->dqrr.next_idx++; + s->dqrr.next_idx &= QBMAN_DQRR_SIZE - 1; /* Wrap around at 4 */ + /* TODO: it's possible to do all this without conditionals, optimise it + * later. */ + if (!s->dqrr.next_idx) + s->dqrr.valid_bit ^= QB_VALID_BIT; + + /* If this is the final response to a volatile dequeue command + indicate that the vdq is no longer busy */ + flags = ldpaa_dq_flags(dq); + response_verb = qb_attr_code_decode(&code_dqrr_response, &verb); + if ((response_verb == QBMAN_DQRR_RESPONSE_DQ) && + (flags & LDPAA_DQ_STAT_VOLATILE) && + (flags & LDPAA_DQ_STAT_EXPIRED)) + atomic_inc(&s->vdq.busy); + + qbman_cena_invalidate_prefetch(&s->sys, + QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx)); + return dq; +} + +/* Consume DQRR entries previously returned from qbman_swp_dqrr_next(). */ +void qbman_swp_dqrr_consume(struct qbman_swp *s, const struct ldpaa_dq *dq) +{ + qbman_cinh_write(&s->sys, QBMAN_CINH_SWP_DCAP, QBMAN_IDX_FROM_DQRR(dq)); +} + +/*********************************/ +/* Polling user-provided storage */ +/*********************************/ + +void qbman_dq_entry_set_oldtoken(struct ldpaa_dq *dq, + unsigned int num_entries, + uint8_t oldtoken) +{ + memset(dq, oldtoken, num_entries * sizeof(*dq)); +} + +int qbman_dq_entry_has_newtoken(struct qbman_swp *s, + const struct ldpaa_dq *dq, + uint8_t newtoken) +{ + /* To avoid converting the little-endian DQ entry to host-endian prior + * to us knowing whether there is a valid entry or not (and run the + * risk of corrupting the incoming hardware LE write), we detect in + * hardware endianness rather than host. This means we need a different + * "code" depending on whether we are BE or LE in software, which is + * where DQRR_TOK_OFFSET comes in... */ + static struct qb_attr_code code_dqrr_tok_detect = + QB_CODE(0, DQRR_TOK_OFFSET, 8); + /* The user trying to poll for a result treats "dq" as const. It is + * however the same address that was provided to us non-const in the + * first place, for directing hardware DMA to. So we can cast away the + * const because it is mutable from our perspective. */ + uint32_t *p = qb_cl((struct ldpaa_dq *)dq); + uint32_t token; + + token = qb_attr_code_decode(&code_dqrr_tok_detect, &p[1]); + if (token != newtoken) + return 0; + + /* Only now do we convert from hardware to host endianness. Also, as we + * are returning success, the user has promised not to call us again, so + * there's no risk of us converting the endianness twice... */ + make_le32_n(p, 16); + + /* VDQCR "no longer busy" hook - not quite the same as DQRR, because the + * fact "VDQCR" shows busy doesn't mean that the result we're looking at + * is from the same command. Eg. we may be looking at our 10th dequeue + * result from our first VDQCR command, yet the second dequeue command + * could have been kicked off already, after seeing the 1st result. Ie. + * the result we're looking at is not necessarily proof that we can + * reset "busy". We instead base the decision on whether the current + * result is sitting at the first 'storage' location of the busy + * command. */ + if (s->vdq.storage == dq) { + s->vdq.storage = NULL; + atomic_inc(&s->vdq.busy); + } + return 1; +} + +/********************************/ +/* Categorising dequeue entries */ +/********************************/ + +static inline int __qbman_dq_entry_is_x(const struct ldpaa_dq *dq, uint32_t x) +{ + const uint32_t *p = qb_cl(dq); + uint32_t response_verb = qb_attr_code_decode(&code_dqrr_response, p); + + return response_verb == x; +} + +int qbman_dq_entry_is_DQ(const struct ldpaa_dq *dq) +{ + return __qbman_dq_entry_is_x(dq, QBMAN_DQRR_RESPONSE_DQ); +} + +/*********************************/ +/* Parsing frame dequeue results */ +/*********************************/ + +/* These APIs assume qbman_dq_entry_is_DQ() is TRUE */ + +uint32_t ldpaa_dq_flags(const struct ldpaa_dq *dq) +{ + const uint32_t *p = qb_cl(dq); + + return qb_attr_code_decode(&code_dqrr_stat, p); +} + +const struct dpaa_fd *ldpaa_dq_fd(const struct ldpaa_dq *dq) +{ + const uint32_t *p = qb_cl(dq); + + return (const struct dpaa_fd *)&p[8]; +} + +/******************/ +/* Buffer release */ +/******************/ + +/* These should be const, eventually */ +/* static struct qb_attr_code code_release_num = QB_CODE(0, 0, 3); */ +static struct qb_attr_code code_release_set_me = QB_CODE(0, 5, 1); +static struct qb_attr_code code_release_bpid = QB_CODE(0, 16, 16); + +void qbman_release_desc_clear(struct qbman_release_desc *d) +{ + uint32_t *cl; + + memset(d, 0, sizeof(*d)); + cl = qb_cl(d); + qb_attr_code_encode(&code_release_set_me, cl, 1); +} + +void qbman_release_desc_set_bpid(struct qbman_release_desc *d, uint32_t bpid) +{ + uint32_t *cl = qb_cl(d); + + qb_attr_code_encode(&code_release_bpid, cl, bpid); +} + +#define RAR_IDX(rar) ((rar) & 0x7) +#define RAR_VB(rar) ((rar) & 0x80) +#define RAR_SUCCESS(rar) ((rar) & 0x100) + +int qbman_swp_release(struct qbman_swp *s, const struct qbman_release_desc *d, + const uint64_t *buffers, unsigned int num_buffers) +{ + uint32_t *p; + const uint32_t *cl = qb_cl(d); + uint32_t rar = qbman_cinh_read(&s->sys, QBMAN_CINH_SWP_RAR); + debug("RAR=%08x\n", rar); + if (!RAR_SUCCESS(rar)) + return -EBUSY; + BUG_ON(!num_buffers || (num_buffers > 7)); + /* Start the release command */ + p = qbman_cena_write_start(&s->sys, + QBMAN_CENA_SWP_RCR(RAR_IDX(rar))); + /* Copy the caller's buffer pointers to the command */ + u64_to_le32_copy(&p[2], buffers, num_buffers); + lwsync(); + /* Set the verb byte, have to substitute in the valid-bit and the number + * of buffers. */ + p[0] = cl[0] | RAR_VB(rar) | num_buffers; + qbman_cena_write_complete(&s->sys, + QBMAN_CENA_SWP_RCR(RAR_IDX(rar)), + p); + return 0; +} + +/*******************/ +/* Buffer acquires */ +/*******************/ + +/* These should be const, eventually */ +static struct qb_attr_code code_acquire_bpid = QB_CODE(0, 16, 16); +static struct qb_attr_code code_acquire_num = QB_CODE(1, 0, 3); +static struct qb_attr_code code_acquire_r_num = QB_CODE(1, 0, 3); + +int qbman_swp_acquire(struct qbman_swp *s, uint32_t bpid, uint64_t *buffers, + unsigned int num_buffers) +{ + uint32_t *p; + uint32_t verb, rslt, num; + + BUG_ON(!num_buffers || (num_buffers > 7)); + + /* Start the management command */ + p = qbman_swp_mc_start(s); + + if (!p) + return -EBUSY; + + /* Encode the caller-provided attributes */ + qb_attr_code_encode(&code_acquire_bpid, p, bpid); + qb_attr_code_encode(&code_acquire_num, p, num_buffers); + + /* Complete the management command */ + p = qbman_swp_mc_complete(s, p, p[0] | QBMAN_MC_ACQUIRE); + + /* Decode the outcome */ + verb = qb_attr_code_decode(&code_generic_verb, p); + rslt = qb_attr_code_decode(&code_generic_rslt, p); + num = qb_attr_code_decode(&code_acquire_r_num, p); + BUG_ON(verb != QBMAN_MC_ACQUIRE); + + /* Determine success or failure */ + if (unlikely(rslt != QBMAN_MC_RSLT_OK)) { + printf("Acquire buffers from BPID 0x%x failed, code=0x%02x\n", + bpid, rslt); + return -EIO; + } + BUG_ON(num > num_buffers); + /* Copy the acquired buffers to the caller's array */ + u64_from_le32_copy(buffers, &p[2], num); + return (int)num; +} diff --git a/sources/uboot-be550/drivers/net/fsl-mc/dpio/qbman_portal.h b/sources/uboot-be550/drivers/net/fsl-mc/dpio/qbman_portal.h new file mode 100644 index 00000000..86e2c3aa --- /dev/null +++ b/sources/uboot-be550/drivers/net/fsl-mc/dpio/qbman_portal.h @@ -0,0 +1,167 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "qbman_private.h" +#include +#include + +/* All QBMan command and result structures use this "valid bit" encoding */ +#define QB_VALID_BIT ((uint32_t)0x80) + +/* Management command result codes */ +#define QBMAN_MC_RSLT_OK 0xf0 + +/* TBD: as of QBMan 4.1, DQRR will be 8 rather than 4! */ +#define QBMAN_DQRR_SIZE 4 + + +/* --------------------- */ +/* portal data structure */ +/* --------------------- */ + +struct qbman_swp { + const struct qbman_swp_desc *desc; + /* The qbman_sys (ie. arch/OS-specific) support code can put anything it + * needs in here. */ + struct qbman_swp_sys sys; + /* Management commands */ + struct { +#ifdef QBMAN_CHECKING + enum swp_mc_check { + swp_mc_can_start, /* call __qbman_swp_mc_start() */ + swp_mc_can_submit, /* call __qbman_swp_mc_submit() */ + swp_mc_can_poll, /* call __qbman_swp_mc_result() */ + } check; +#endif + uint32_t valid_bit; /* 0x00 or 0x80 */ + } mc; + /* Push dequeues */ + uint32_t sdq; + /* Volatile dequeues */ + struct { + /* VDQCR supports a "1 deep pipeline", meaning that if you know + * the last-submitted command is already executing in the + * hardware (as evidenced by at least 1 valid dequeue result), + * you can write another dequeue command to the register, the + * hardware will start executing it as soon as the + * already-executing command terminates. (This minimises latency + * and stalls.) With that in mind, this "busy" variable refers + * to whether or not a command can be submitted, not whether or + * not a previously-submitted command is still executing. In + * other words, once proof is seen that the previously-submitted + * command is executing, "vdq" is no longer "busy". + */ + atomic_t busy; + uint32_t valid_bit; /* 0x00 or 0x80 */ + /* We need to determine when vdq is no longer busy. This depends + * on whether the "busy" (last-submitted) dequeue command is + * targeting DQRR or main-memory, and detected is based on the + * presence of the dequeue command's "token" showing up in + * dequeue entries in DQRR or main-memory (respectively). Debug + * builds will, when submitting vdq commands, verify that the + * dequeue result location is not already equal to the command's + * token value. */ + struct ldpaa_dq *storage; /* NULL if DQRR */ + uint32_t token; + } vdq; + /* DQRR */ + struct { + uint32_t next_idx; + uint32_t valid_bit; + } dqrr; +}; + +/* -------------------------- */ +/* portal management commands */ +/* -------------------------- */ + +/* Different management commands all use this common base layer of code to issue + * commands and poll for results. The first function returns a pointer to where + * the caller should fill in their MC command (though they should ignore the + * verb byte), the second function commits merges in the caller-supplied command + * verb (which should not include the valid-bit) and submits the command to + * hardware, and the third function checks for a completed response (returns + * non-NULL if only if the response is complete). */ +void *qbman_swp_mc_start(struct qbman_swp *p); +void qbman_swp_mc_submit(struct qbman_swp *p, void *cmd, uint32_t cmd_verb); +void *qbman_swp_mc_result(struct qbman_swp *p); + +/* Wraps up submit + poll-for-result */ +static inline void *qbman_swp_mc_complete(struct qbman_swp *swp, void *cmd, + uint32_t cmd_verb) +{ + int loopvar; + + qbman_swp_mc_submit(swp, cmd, cmd_verb); + DBG_POLL_START(loopvar); + do { + DBG_POLL_CHECK(loopvar); + cmd = qbman_swp_mc_result(swp); + } while (!cmd); + return cmd; +} + +/* ------------ */ +/* qb_attr_code */ +/* ------------ */ + +/* This struct locates a sub-field within a QBMan portal (CENA) cacheline which + * is either serving as a configuration command or a query result. The + * representation is inherently little-endian, as the indexing of the words is + * itself little-endian in nature and layerscape is little endian for anything + * that crosses a word boundary too (64-bit fields are the obvious examples). + */ +struct qb_attr_code { + unsigned int word; /* which uint32_t[] array member encodes the field */ + unsigned int lsoffset; /* encoding offset from ls-bit */ + unsigned int width; /* encoding width. (bool must be 1.) */ +}; + +/* Macros to define codes */ +#define QB_CODE(a, b, c) { a, b, c} + +/* decode a field from a cacheline */ +static inline uint32_t qb_attr_code_decode(const struct qb_attr_code *code, + const uint32_t *cacheline) +{ + return d32_uint32_t(code->lsoffset, code->width, cacheline[code->word]); +} + + +/* encode a field to a cacheline */ +static inline void qb_attr_code_encode(const struct qb_attr_code *code, + uint32_t *cacheline, uint32_t val) +{ + cacheline[code->word] = + r32_uint32_t(code->lsoffset, code->width, cacheline[code->word]) + | e32_uint32_t(code->lsoffset, code->width, val); +} + +static inline void qb_attr_code_encode_64(const struct qb_attr_code *code, + uint64_t *cacheline, uint64_t val) +{ + cacheline[code->word / 2] = val; +} + +/* ---------------------- */ +/* Descriptors/cachelines */ +/* ---------------------- */ + +/* To avoid needless dynamic allocation, the driver API often gives the caller + * a "descriptor" type that the caller can instantiate however they like. + * Ultimately though, it is just a cacheline of binary storage (or something + * smaller when it is known that the descriptor doesn't need all 64 bytes) for + * holding pre-formatted pieces of hardware commands. The performance-critical + * code can then copy these descriptors directly into hardware command + * registers more efficiently than trying to construct/format commands + * on-the-fly. The API user sees the descriptor as an array of 32-bit words in + * order for the compiler to know its size, but the internal details are not + * exposed. The following macro is used within the driver for converting *any* + * descriptor pointer to a usable array pointer. The use of a macro (instead of + * an inline) is necessary to work with different descriptor types and to work + * correctly with const and non-const inputs (and similarly-qualified outputs). + */ +#define qb_cl(d) (&(d)->dont_manipulate_directly[0]) diff --git a/sources/uboot-be550/drivers/net/fsl-mc/dpio/qbman_private.h b/sources/uboot-be550/drivers/net/fsl-mc/dpio/qbman_private.h new file mode 100644 index 00000000..f1f16b82 --- /dev/null +++ b/sources/uboot-be550/drivers/net/fsl-mc/dpio/qbman_private.h @@ -0,0 +1,169 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* Perform extra checking */ +#include +#include +#include +#include +#include +#include +#include + +#define QBMAN_CHECKING + +/* Any time there is a register interface which we poll on, this provides a + * "break after x iterations" scheme for it. It's handy for debugging, eg. + * where you don't want millions of lines of log output from a polling loop + * that won't, because such things tend to drown out the earlier log output + * that might explain what caused the problem. (NB: put ";" after each macro!) + * TODO: we should probably remove this once we're done sanitising the + * simulator... + */ +#define DBG_POLL_START(loopvar) (loopvar = 10) +#define DBG_POLL_CHECK(loopvar) \ + do {if (!(loopvar--)) BUG_ON(NULL == "DBG_POLL_CHECK"); } while (0) + +/* For CCSR or portal-CINH registers that contain fields at arbitrary offsets + * and widths, these macro-generated encode/decode/isolate/remove inlines can + * be used. + * + * Eg. to "d"ecode a 14-bit field out of a register (into a "uint16_t" type), + * where the field is located 3 bits "up" from the least-significant bit of the + * register (ie. the field location within the 32-bit register corresponds to a + * mask of 0x0001fff8), you would do; + * uint16_t field = d32_uint16_t(3, 14, reg_value); + * + * Or to "e"ncode a 1-bit boolean value (input type is "int", zero is FALSE, + * non-zero is TRUE, so must convert all non-zero inputs to 1, hence the "!!" + * operator) into a register at bit location 0x00080000 (19 bits "in" from the + * LS bit), do; + * reg_value |= e32_int(19, 1, !!field); + * + * If you wish to read-modify-write a register, such that you leave the 14-bit + * field as-is but have all other fields set to zero, then "i"solate the 14-bit + * value using; + * reg_value = i32_uint16_t(3, 14, reg_value); + * + * Alternatively, you could "r"emove the 1-bit boolean field (setting it to + * zero) but leaving all other fields as-is; + * reg_val = r32_int(19, 1, reg_value); + * + */ +#define MAKE_MASK32(width) (width == 32 ? 0xffffffff : \ + (uint32_t)((1 << width) - 1)) +#define DECLARE_CODEC32(t) \ +static inline uint32_t e32_##t(uint32_t lsoffset, uint32_t width, t val) \ +{ \ + BUG_ON(width > (sizeof(t) * 8)); \ + return ((uint32_t)val & MAKE_MASK32(width)) << lsoffset; \ +} \ +static inline t d32_##t(uint32_t lsoffset, uint32_t width, uint32_t val) \ +{ \ + BUG_ON(width > (sizeof(t) * 8)); \ + return (t)((val >> lsoffset) & MAKE_MASK32(width)); \ +} \ +static inline uint32_t i32_##t(uint32_t lsoffset, uint32_t width, \ + uint32_t val) \ +{ \ + BUG_ON(width > (sizeof(t) * 8)); \ + return e32_##t(lsoffset, width, d32_##t(lsoffset, width, val)); \ +} \ +static inline uint32_t r32_##t(uint32_t lsoffset, uint32_t width, \ + uint32_t val) \ +{ \ + BUG_ON(width > (sizeof(t) * 8)); \ + return ~(MAKE_MASK32(width) << lsoffset) & val; \ +} +DECLARE_CODEC32(uint32_t) +DECLARE_CODEC32(uint16_t) +DECLARE_CODEC32(uint8_t) +DECLARE_CODEC32(int) + + /*********************/ + /* Debugging assists */ + /*********************/ + +static inline void __hexdump(unsigned long start, unsigned long end, + unsigned long p, size_t sz, const unsigned char *c) +{ + while (start < end) { + unsigned int pos = 0; + char buf[64]; + int nl = 0; + + pos += sprintf(buf + pos, "%08lx: ", start); + do { + if ((start < p) || (start >= (p + sz))) + pos += sprintf(buf + pos, ".."); + else + pos += sprintf(buf + pos, "%02x", *(c++)); + if (!(++start & 15)) { + buf[pos++] = '\n'; + nl = 1; + } else { + nl = 0; + if (!(start & 1)) + buf[pos++] = ' '; + if (!(start & 3)) + buf[pos++] = ' '; + } + } while (start & 15); + if (!nl) + buf[pos++] = '\n'; + buf[pos] = '\0'; + debug("%s", buf); + } +} +static inline void hexdump(const void *ptr, size_t sz) +{ + unsigned long p = (unsigned long)ptr; + unsigned long start = p & ~(unsigned long)15; + unsigned long end = (p + sz + 15) & ~(unsigned long)15; + const unsigned char *c = ptr; + + __hexdump(start, end, p, sz, c); +} + +#if defined(__BIG_ENDIAN) +#define DQRR_TOK_OFFSET 0 +#else +#define DQRR_TOK_OFFSET 24 +#endif + +/* Similarly-named functions */ +#define upper32(a) upper_32_bits(a) +#define lower32(a) lower_32_bits(a) + + /****************/ + /* arch assists */ + /****************/ + +static inline void dcbz(void *ptr) +{ + uint32_t *p = ptr; + BUG_ON((unsigned long)ptr & 63); + p[0] = 0; + p[1] = 0; + p[2] = 0; + p[3] = 0; + p[4] = 0; + p[5] = 0; + p[6] = 0; + p[7] = 0; + p[8] = 0; + p[9] = 0; + p[10] = 0; + p[11] = 0; + p[12] = 0; + p[13] = 0; + p[14] = 0; + p[15] = 0; +} + +#define lwsync() + +#include "qbman_sys.h" diff --git a/sources/uboot-be550/drivers/net/fsl-mc/dpio/qbman_sys.h b/sources/uboot-be550/drivers/net/fsl-mc/dpio/qbman_sys.h new file mode 100644 index 00000000..235d641b --- /dev/null +++ b/sources/uboot-be550/drivers/net/fsl-mc/dpio/qbman_sys.h @@ -0,0 +1,290 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* qbman_sys_decl.h and qbman_sys.h are the two platform-specific files in the + * driver. They are only included via qbman_private.h, which is itself a + * platform-independent file and is included by all the other driver source. + * + * qbman_sys_decl.h is included prior to all other declarations and logic, and + * it exists to provide compatibility with any linux interfaces our + * single-source driver code is dependent on (eg. kmalloc). Ie. this file + * provides linux compatibility. + * + * This qbman_sys.h header, on the other hand, is included *after* any common + * and platform-neutral declarations and logic in qbman_private.h, and exists to + * implement any platform-specific logic of the qbman driver itself. Ie. it is + * *not* to provide linux compatibility. + */ + +/* Trace the 3 different classes of read/write access to QBMan. #undef as + * required. */ +#undef QBMAN_CCSR_TRACE +#undef QBMAN_CINH_TRACE +#undef QBMAN_CENA_TRACE + +/* Temporarily define this to get around the fact that cache enabled mapping is + * not working right now. Will remove this after uboot could map the cache + * enabled portal memory. + */ +#define QBMAN_CINH_ONLY + +static inline void word_copy(void *d, const void *s, unsigned int cnt) +{ + uint32_t *dd = d; + const uint32_t *ss = s; + + while (cnt--) + *(dd++) = *(ss++); +} + +/* Currently, the CENA support code expects each 32-bit word to be written in + * host order, and these are converted to hardware (little-endian) order on + * command submission. However, 64-bit quantities are must be written (and read) + * as two 32-bit words with the least-significant word first, irrespective of + * host endianness. */ +static inline void u64_to_le32_copy(void *d, const uint64_t *s, + unsigned int cnt) +{ + uint32_t *dd = d; + const uint32_t *ss = (const uint32_t *)s; + + while (cnt--) { + /* TBD: the toolchain was choking on the use of 64-bit types up + * until recently so this works entirely with 32-bit variables. + * When 64-bit types become usable again, investigate better + * ways of doing this. */ +#if defined(__BIG_ENDIAN) + *(dd++) = ss[1]; + *(dd++) = ss[0]; + ss += 2; +#else + *(dd++) = *(ss++); + *(dd++) = *(ss++); +#endif + } +} +static inline void u64_from_le32_copy(uint64_t *d, const void *s, + unsigned int cnt) +{ + const uint32_t *ss = s; + uint32_t *dd = (uint32_t *)d; + + while (cnt--) { +#if defined(__BIG_ENDIAN) + dd[1] = *(ss++); + dd[0] = *(ss++); + dd += 2; +#else + *(dd++) = *(ss++); + *(dd++) = *(ss++); +#endif + } +} + +/* Convert a host-native 32bit value into little endian */ +#if defined(__BIG_ENDIAN) +static inline uint32_t make_le32(uint32_t val) +{ + return ((val & 0xff) << 24) | ((val & 0xff00) << 8) | + ((val & 0xff0000) >> 8) | ((val & 0xff000000) >> 24); +} +#else +#define make_le32(val) (val) +#endif +static inline void make_le32_n(uint32_t *val, unsigned int num) +{ + while (num--) { + *val = make_le32(*val); + val++; + } +} + + /******************/ + /* Portal access */ + /******************/ +struct qbman_swp_sys { + /* On GPP, the sys support for qbman_swp is here. The CENA region isi + * not an mmap() of the real portal registers, but an allocated + * place-holder, because the actual writes/reads to/from the portal are + * marshalled from these allocated areas using QBMan's "MC access + * registers". CINH accesses are atomic so there's no need for a + * place-holder. */ + void *cena; + void __iomem *addr_cena; + void __iomem *addr_cinh; +}; + +/* P_OFFSET is (ACCESS_CMD,0,12) - offset within the portal + * C is (ACCESS_CMD,12,1) - is inhibited? (0==CENA, 1==CINH) + * SWP_IDX is (ACCESS_CMD,16,10) - Software portal index + * P is (ACCESS_CMD,28,1) - (0==special portal, 1==any portal) + * T is (ACCESS_CMD,29,1) - Command type (0==READ, 1==WRITE) + * E is (ACCESS_CMD,31,1) - Command execute (1 to issue, poll for 0==complete) + */ + +static inline void qbman_cinh_write(struct qbman_swp_sys *s, uint32_t offset, + uint32_t val) +{ + __raw_writel(val, s->addr_cinh + offset); +#ifdef QBMAN_CINH_TRACE + pr_info("qbman_cinh_write(%p:0x%03x) 0x%08x\n", + s->addr_cinh, offset, val); +#endif +} + +static inline uint32_t qbman_cinh_read(struct qbman_swp_sys *s, uint32_t offset) +{ + uint32_t reg = __raw_readl(s->addr_cinh + offset); + +#ifdef QBMAN_CINH_TRACE + pr_info("qbman_cinh_read(%p:0x%03x) 0x%08x\n", + s->addr_cinh, offset, reg); +#endif + return reg; +} + +static inline void *qbman_cena_write_start(struct qbman_swp_sys *s, + uint32_t offset) +{ + void *shadow = s->cena + offset; + +#ifdef QBMAN_CENA_TRACE + pr_info("qbman_cena_write_start(%p:0x%03x) %p\n", + s->addr_cena, offset, shadow); +#endif + BUG_ON(offset & 63); + dcbz(shadow); + return shadow; +} + +static inline void qbman_cena_write_complete(struct qbman_swp_sys *s, + uint32_t offset, void *cmd) +{ + const uint32_t *shadow = cmd; + int loop; + +#ifdef QBMAN_CENA_TRACE + pr_info("qbman_cena_write_complete(%p:0x%03x) %p\n", + s->addr_cena, offset, shadow); + hexdump(cmd, 64); +#endif + for (loop = 15; loop >= 0; loop--) +#ifdef QBMAN_CINH_ONLY + __raw_writel(shadow[loop], s->addr_cinh + + offset + loop * 4); +#else + __raw_writel(shadow[loop], s->addr_cena + + offset + loop * 4); +#endif +} + +static inline void *qbman_cena_read(struct qbman_swp_sys *s, uint32_t offset) +{ + uint32_t *shadow = s->cena + offset; + unsigned int loop; + +#ifdef QBMAN_CENA_TRACE + pr_info("qbman_cena_read(%p:0x%03x) %p\n", + s->addr_cena, offset, shadow); +#endif + + for (loop = 0; loop < 16; loop++) +#ifdef QBMAN_CINH_ONLY + shadow[loop] = __raw_readl(s->addr_cinh + offset + + loop * 4); +#else + shadow[loop] = __raw_readl(s->addr_cena + offset + + loop * 4); +#endif +#ifdef QBMAN_CENA_TRACE + hexdump(shadow, 64); +#endif + return shadow; +} + +static inline void qbman_cena_invalidate_prefetch(struct qbman_swp_sys *s, + uint32_t offset) +{ +} + + /******************/ + /* Portal support */ + /******************/ + +/* The SWP_CFG portal register is special, in that it is used by the + * platform-specific code rather than the platform-independent code in + * qbman_portal.c. So use of it is declared locally here. */ +#define QBMAN_CINH_SWP_CFG 0xd00 + +/* For MC portal use, we always configure with + * DQRR_MF is (SWP_CFG,20,3) - DQRR max fill (<- 0x4) + * EST is (SWP_CFG,16,3) - EQCR_CI stashing threshold (<- 0x0) + * RPM is (SWP_CFG,12,2) - RCR production notification mode (<- 0x3) + * DCM is (SWP_CFG,10,2) - DQRR consumption notification mode (<- 0x2) + * EPM is (SWP_CFG,8,2) - EQCR production notification mode (<- 0x3) + * SD is (SWP_CFG,5,1) - memory stashing drop enable (<- FALSE) + * SP is (SWP_CFG,4,1) - memory stashing priority (<- TRUE) + * SE is (SWP_CFG,3,1) - memory stashing enable (<- 0x0) + * DP is (SWP_CFG,2,1) - dequeue stashing priority (<- TRUE) + * DE is (SWP_CFG,1,1) - dequeue stashing enable (<- 0x0) + * EP is (SWP_CFG,0,1) - EQCR_CI stashing priority (<- FALSE) + */ +static inline uint32_t qbman_set_swp_cfg(uint8_t max_fill, uint8_t wn, + uint8_t est, uint8_t rpm, uint8_t dcm, + uint8_t epm, int sd, int sp, int se, + int dp, int de, int ep) +{ + uint32_t reg; + + reg = e32_uint8_t(20, 3, max_fill) | e32_uint8_t(16, 3, est) | + e32_uint8_t(12, 2, rpm) | e32_uint8_t(10, 2, dcm) | + e32_uint8_t(8, 2, epm) | e32_int(5, 1, sd) | + e32_int(4, 1, sp) | e32_int(3, 1, se) | e32_int(2, 1, dp) | + e32_int(1, 1, de) | e32_int(0, 1, ep) | e32_uint8_t(14, 1, wn); + return reg; +} + +static inline int qbman_swp_sys_init(struct qbman_swp_sys *s, + const struct qbman_swp_desc *d) +{ + uint32_t reg; + + s->addr_cena = d->cena_bar; + s->addr_cinh = d->cinh_bar; + s->cena = (void *)valloc(CONFIG_SYS_PAGE_SIZE); + memset((void *)s->cena, 0x00, CONFIG_SYS_PAGE_SIZE); + if (!s->cena) { + printf("Could not allocate page for cena shadow\n"); + return -1; + } + +#ifdef QBMAN_CHECKING + /* We should never be asked to initialise for a portal that isn't in + * the power-on state. (Ie. don't forget to reset portals when they are + * decommissioned!) + */ + reg = qbman_cinh_read(s, QBMAN_CINH_SWP_CFG); + BUG_ON(reg); +#endif +#ifdef QBMAN_CINH_ONLY + reg = qbman_set_swp_cfg(4, 1, 0, 3, 2, 3, 0, 1, 0, 1, 0, 0); +#else + reg = qbman_set_swp_cfg(4, 0, 0, 3, 2, 3, 0, 1, 0, 1, 0, 0); +#endif + qbman_cinh_write(s, QBMAN_CINH_SWP_CFG, reg); + reg = qbman_cinh_read(s, QBMAN_CINH_SWP_CFG); + if (!reg) { + printf("The portal is not enabled!\n"); + free(s->cena); + return -1; + } + return 0; +} + +static inline void qbman_swp_sys_finish(struct qbman_swp_sys *s) +{ + free((void *)s->cena); +} diff --git a/sources/uboot-be550/drivers/net/fsl-mc/dpmac.c b/sources/uboot-be550/drivers/net/fsl-mc/dpmac.c new file mode 100644 index 00000000..072a90dc --- /dev/null +++ b/sources/uboot-be550/drivers/net/fsl-mc/dpmac.c @@ -0,0 +1,222 @@ +/* + * Freescale Layerscape MC I/O wrapper + * + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Author: Prabhakar Kushwaha + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +int dpmac_open(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + int dpmac_id, + uint16_t *token) +{ + struct mc_command cmd = { 0 }; + int err; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPMAC_CMDID_OPEN, + cmd_flags, + 0); + DPMAC_CMD_OPEN(cmd, dpmac_id); + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + /* retrieve response parameters */ + *token = MC_CMD_HDR_READ_TOKEN(cmd.header); + + return err; +} + +int dpmac_close(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token) +{ + struct mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPMAC_CMDID_CLOSE, cmd_flags, + token); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} + +int dpmac_create(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + const struct dpmac_cfg *cfg, + uint16_t *token) +{ + struct mc_command cmd = { 0 }; + int err; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPMAC_CMDID_CREATE, + cmd_flags, + 0); + DPMAC_CMD_CREATE(cmd, cfg); + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + /* retrieve response parameters */ + *token = MC_CMD_HDR_READ_TOKEN(cmd.header); + + return 0; +} + +int dpmac_destroy(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token) +{ + struct mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPMAC_CMDID_DESTROY, + cmd_flags, + token); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} + +int dpmac_get_attributes(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + struct dpmac_attr *attr) +{ + struct mc_command cmd = { 0 }; + int err; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPMAC_CMDID_GET_ATTR, + cmd_flags, + token); + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + /* retrieve response parameters */ + DPMAC_RSP_GET_ATTRIBUTES(cmd, attr); + + return 0; +} + +int dpmac_mdio_read(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + struct dpmac_mdio_cfg *cfg) +{ + struct mc_command cmd = { 0 }; + int err; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPMAC_CMDID_MDIO_READ, + cmd_flags, + token); + DPMAC_CMD_MDIO_READ(cmd, cfg); + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + /* retrieve response parameters */ + DPMAC_RSP_MDIO_READ(cmd, cfg->data); + + return 0; +} + +int dpmac_mdio_write(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + struct dpmac_mdio_cfg *cfg) +{ + struct mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPMAC_CMDID_MDIO_WRITE, + cmd_flags, + token); + DPMAC_CMD_MDIO_WRITE(cmd, cfg); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} + +int dpmac_get_link_cfg(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + struct dpmac_link_cfg *cfg) +{ + struct mc_command cmd = { 0 }; + int err = 0; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPMAC_CMDID_GET_LINK_CFG, + cmd_flags, + token); + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + DPMAC_RSP_GET_LINK_CFG(cmd, cfg); + + return 0; +} + +int dpmac_set_link_state(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + struct dpmac_link_state *link_state) +{ + struct mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPMAC_CMDID_SET_LINK_STATE, + cmd_flags, + token); + DPMAC_CMD_SET_LINK_STATE(cmd, link_state); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} + +int dpmac_get_counter(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + enum dpmac_counter type, + uint64_t *counter) +{ + struct mc_command cmd = { 0 }; + int err = 0; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPMAC_CMDID_GET_COUNTER, + cmd_flags, + token); + DPMAC_CMD_GET_COUNTER(cmd, type); + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + DPMAC_RSP_GET_COUNTER(cmd, *counter); + + return 0; +} diff --git a/sources/uboot-be550/drivers/net/fsl-mc/dpmng.c b/sources/uboot-be550/drivers/net/fsl-mc/dpmng.c new file mode 100644 index 00000000..d96e26b7 --- /dev/null +++ b/sources/uboot-be550/drivers/net/fsl-mc/dpmng.c @@ -0,0 +1,31 @@ +/* Copyright 2013-2015 Freescale Semiconductor Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include "fsl_dpmng_cmd.h" + +int mc_get_version(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + struct mc_version *mc_ver_info) +{ + struct mc_command cmd = { 0 }; + int err; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPMNG_CMDID_GET_VERSION, + cmd_flags, + 0); + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + /* retrieve response parameters */ + DPMNG_RSP_GET_VERSION(cmd, mc_ver_info); + + return 0; +} diff --git a/sources/uboot-be550/drivers/net/fsl-mc/dpni.c b/sources/uboot-be550/drivers/net/fsl-mc/dpni.c new file mode 100644 index 00000000..eacb3c8b --- /dev/null +++ b/sources/uboot-be550/drivers/net/fsl-mc/dpni.c @@ -0,0 +1,604 @@ +/* + * Copyright (C) 2013-2015 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +int dpni_open(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + int dpni_id, + uint16_t *token) +{ + struct mc_command cmd = { 0 }; + int err; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPNI_CMDID_OPEN, + cmd_flags, + 0); + DPNI_CMD_OPEN(cmd, dpni_id); + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + /* retrieve response parameters */ + *token = MC_CMD_HDR_READ_TOKEN(cmd.header); + + return 0; +} + +int dpni_close(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token) +{ + struct mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPNI_CMDID_CLOSE, + cmd_flags, + token); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} + +int dpni_create(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + const struct dpni_cfg *cfg, + uint16_t *token) +{ + struct mc_command cmd = { 0 }; + int err; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPNI_CMDID_CREATE, + cmd_flags, + 0); + DPNI_CMD_CREATE(cmd, cfg); + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + /* retrieve response parameters */ + *token = MC_CMD_HDR_READ_TOKEN(cmd.header); + + return 0; +} + +int dpni_destroy(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token) +{ + struct mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPNI_CMDID_DESTROY, + cmd_flags, + token); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} + +int dpni_set_pools(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + const struct dpni_pools_cfg *cfg) +{ + struct mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_POOLS, + cmd_flags, + token); + DPNI_CMD_SET_POOLS(cmd, cfg); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} + +int dpni_enable(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token) +{ + struct mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPNI_CMDID_ENABLE, + cmd_flags, + token); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} + +int dpni_disable(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token) +{ + struct mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPNI_CMDID_DISABLE, + cmd_flags, + token); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} + +int dpni_reset(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token) +{ + struct mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPNI_CMDID_RESET, + cmd_flags, + token); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} + +int dpni_get_attributes(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + struct dpni_attr *attr) +{ + struct mc_command cmd = { 0 }; + int err; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_ATTR, + cmd_flags, + token); + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + /* retrieve response parameters */ + DPNI_RSP_GET_ATTR(cmd, attr); + + return 0; +} + +int dpni_get_rx_buffer_layout(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + struct dpni_buffer_layout *layout) +{ + struct mc_command cmd = { 0 }; + int err; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_RX_BUFFER_LAYOUT, + cmd_flags, + token); + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + /* retrieve response parameters */ + DPNI_RSP_GET_RX_BUFFER_LAYOUT(cmd, layout); + + return 0; +} + +int dpni_set_rx_buffer_layout(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + const struct dpni_buffer_layout *layout) +{ + struct mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_RX_BUFFER_LAYOUT, + cmd_flags, + token); + DPNI_CMD_SET_RX_BUFFER_LAYOUT(cmd, layout); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} + +int dpni_get_tx_buffer_layout(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + struct dpni_buffer_layout *layout) +{ + struct mc_command cmd = { 0 }; + int err; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_TX_BUFFER_LAYOUT, + cmd_flags, + token); + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + /* retrieve response parameters */ + DPNI_RSP_GET_TX_BUFFER_LAYOUT(cmd, layout); + + return 0; +} + +int dpni_set_tx_buffer_layout(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + const struct dpni_buffer_layout *layout) +{ + struct mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_TX_BUFFER_LAYOUT, + cmd_flags, + token); + DPNI_CMD_SET_TX_BUFFER_LAYOUT(cmd, layout); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} + +int dpni_get_tx_conf_buffer_layout(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + struct dpni_buffer_layout *layout) +{ + struct mc_command cmd = { 0 }; + int err; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_TX_CONF_BUFFER_LAYOUT, + cmd_flags, + token); + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + /* retrieve response parameters */ + DPNI_RSP_GET_TX_CONF_BUFFER_LAYOUT(cmd, layout); + + return 0; +} + +int dpni_set_tx_conf_buffer_layout(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + const struct dpni_buffer_layout *layout) +{ + struct mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_TX_CONF_BUFFER_LAYOUT, + cmd_flags, + token); + DPNI_CMD_SET_TX_CONF_BUFFER_LAYOUT(cmd, layout); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} + +int dpni_get_qdid(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + uint16_t *qdid) +{ + struct mc_command cmd = { 0 }; + int err; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_QDID, + cmd_flags, + token); + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + /* retrieve response parameters */ + DPNI_RSP_GET_QDID(cmd, *qdid); + + return 0; +} + +int dpni_get_tx_data_offset(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + uint16_t *data_offset) +{ + struct mc_command cmd = { 0 }; + int err; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_TX_DATA_OFFSET, + cmd_flags, + token); + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + /* retrieve response parameters */ + DPNI_RSP_GET_TX_DATA_OFFSET(cmd, *data_offset); + + return 0; +} + +int dpni_get_counter(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + enum dpni_counter counter, + uint64_t *value) +{ + struct mc_command cmd = { 0 }; + int err; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_COUNTER, + cmd_flags, + token); + DPNI_CMD_GET_COUNTER(cmd, counter); + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + /* retrieve response parameters */ + DPNI_RSP_GET_COUNTER(cmd, *value); + + return 0; +} + +int dpni_set_counter(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + enum dpni_counter counter, + uint64_t value) +{ + struct mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_COUNTER, + cmd_flags, + token); + DPNI_CMD_SET_COUNTER(cmd, counter, value); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} + +int dpni_set_link_cfg(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + const struct dpni_link_cfg *cfg) +{ + struct mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_LINK_CFG, + cmd_flags, + token); + DPNI_CMD_SET_LINK_CFG(cmd, cfg); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} + +int dpni_get_link_state(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + struct dpni_link_state *state) +{ + struct mc_command cmd = { 0 }; + int err; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_LINK_STATE, + cmd_flags, + token); + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + /* retrieve response parameters */ + DPNI_RSP_GET_LINK_STATE(cmd, state); + + return 0; +} + + +int dpni_set_primary_mac_addr(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + const uint8_t mac_addr[6]) +{ + struct mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_PRIM_MAC, + cmd_flags, + token); + DPNI_CMD_SET_PRIMARY_MAC_ADDR(cmd, mac_addr); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} + +int dpni_get_primary_mac_addr(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + uint8_t mac_addr[6]) +{ + struct mc_command cmd = { 0 }; + int err; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_PRIM_MAC, + cmd_flags, + token); + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + /* retrieve response parameters */ + DPNI_RSP_GET_PRIMARY_MAC_ADDR(cmd, mac_addr); + + return 0; +} + +int dpni_add_mac_addr(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + const uint8_t mac_addr[6]) +{ + struct mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPNI_CMDID_ADD_MAC_ADDR, + cmd_flags, + token); + DPNI_CMD_ADD_MAC_ADDR(cmd, mac_addr); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} + +int dpni_remove_mac_addr(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + const uint8_t mac_addr[6]) +{ + struct mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPNI_CMDID_REMOVE_MAC_ADDR, + cmd_flags, + token); + DPNI_CMD_REMOVE_MAC_ADDR(cmd, mac_addr); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} + +int dpni_set_tx_flow(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + uint16_t *flow_id, + const struct dpni_tx_flow_cfg *cfg) +{ + struct mc_command cmd = { 0 }; + int err; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_TX_FLOW, + cmd_flags, + token); + DPNI_CMD_SET_TX_FLOW(cmd, *flow_id, cfg); + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + /* retrieve response parameters */ + DPNI_RSP_SET_TX_FLOW(cmd, *flow_id); + + return 0; +} + +int dpni_get_tx_flow(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + uint16_t flow_id, + struct dpni_tx_flow_attr *attr) +{ + struct mc_command cmd = { 0 }; + int err; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_TX_FLOW, + cmd_flags, + token); + DPNI_CMD_GET_TX_FLOW(cmd, flow_id); + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + /* retrieve response parameters */ + DPNI_RSP_GET_TX_FLOW(cmd, attr); + + return 0; +} + +int dpni_set_rx_flow(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + uint8_t tc_id, + uint16_t flow_id, + const struct dpni_queue_cfg *cfg) +{ + struct mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_RX_FLOW, + cmd_flags, + token); + DPNI_CMD_SET_RX_FLOW(cmd, tc_id, flow_id, cfg); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} + +int dpni_get_rx_flow(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + uint8_t tc_id, + uint16_t flow_id, + struct dpni_queue_attr *attr) +{ + struct mc_command cmd = { 0 }; + int err; + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_RX_FLOW, + cmd_flags, + token); + DPNI_CMD_GET_RX_FLOW(cmd, tc_id, flow_id); + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + /* retrieve response parameters */ + DPNI_RSP_GET_RX_FLOW(cmd, attr); + + return 0; +} diff --git a/sources/uboot-be550/drivers/net/fsl-mc/dprc.c b/sources/uboot-be550/drivers/net/fsl-mc/dprc.c new file mode 100644 index 00000000..7d34355b --- /dev/null +++ b/sources/uboot-be550/drivers/net/fsl-mc/dprc.c @@ -0,0 +1,355 @@ +/* + * Freescale Layerscape MC I/O wrapper + * + * Copyright (C) 2013-2015 Freescale Semiconductor, Inc. + * Author: German Rivera + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +int dprc_get_container_id(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + int *container_id) +{ + struct mc_command cmd = { 0 }; + int err; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_CONT_ID, + cmd_flags, + 0); + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + /* retrieve response parameters */ + DPRC_RSP_GET_CONTAINER_ID(cmd, *container_id); + + return 0; +} + +int dprc_open(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + int container_id, + uint16_t *token) +{ + struct mc_command cmd = { 0 }; + int err; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPRC_CMDID_OPEN, cmd_flags, + 0); + DPRC_CMD_OPEN(cmd, container_id); + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + /* retrieve response parameters */ + *token = MC_CMD_HDR_READ_TOKEN(cmd.header); + + return 0; +} + +int dprc_close(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token) +{ + struct mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPRC_CMDID_CLOSE, cmd_flags, + token); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} + +int dprc_create_container(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + struct dprc_cfg *cfg, + int *child_container_id, + uint64_t *child_portal_paddr) +{ + struct mc_command cmd = { 0 }; + int err; + + /* prepare command */ + DPRC_CMD_CREATE_CONTAINER(cmd, cfg); + + cmd.header = mc_encode_cmd_header(DPRC_CMDID_CREATE_CONT, + cmd_flags, + token); + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + /* retrieve response parameters */ + DPRC_RSP_CREATE_CONTAINER(cmd, *child_container_id, + *child_portal_paddr); + + return 0; +} + +int dprc_destroy_container(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + int child_container_id) +{ + struct mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPRC_CMDID_DESTROY_CONT, + cmd_flags, + token); + DPRC_CMD_DESTROY_CONTAINER(cmd, child_container_id); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} + +int dprc_reset_container(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + int child_container_id) +{ + struct mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPRC_CMDID_RESET_CONT, + cmd_flags, + token); + DPRC_CMD_RESET_CONTAINER(cmd, child_container_id); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} + +int dprc_get_attributes(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + struct dprc_attributes *attr) +{ + struct mc_command cmd = { 0 }; + int err; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_ATTR, + cmd_flags, + token); + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + /* retrieve response parameters */ + DPRC_RSP_GET_ATTRIBUTES(cmd, attr); + + return 0; +} + +int dprc_get_obj_count(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + int *obj_count) +{ + struct mc_command cmd = { 0 }; + int err; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_OBJ_COUNT, + cmd_flags, + token); + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + /* retrieve response parameters */ + DPRC_RSP_GET_OBJ_COUNT(cmd, *obj_count); + + return 0; +} + +int dprc_get_obj(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + int obj_index, + struct dprc_obj_desc *obj_desc) +{ + struct mc_command cmd = { 0 }; + int err; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_OBJ, + cmd_flags, + token); + DPRC_CMD_GET_OBJ(cmd, obj_index); + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + /* retrieve response parameters */ + DPRC_RSP_GET_OBJ(cmd, obj_desc); + + return 0; +} + +int dprc_get_res_count(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + char *type, + int *res_count) +{ + struct mc_command cmd = { 0 }; + int err; + + *res_count = 0; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_RES_COUNT, + cmd_flags, + token); + DPRC_CMD_GET_RES_COUNT(cmd, type); + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + /* retrieve response parameters */ + DPRC_RSP_GET_RES_COUNT(cmd, *res_count); + + return 0; +} + +int dprc_get_res_ids(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + char *type, + struct dprc_res_ids_range_desc *range_desc) +{ + struct mc_command cmd = { 0 }; + int err; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_RES_IDS, + cmd_flags, + token); + DPRC_CMD_GET_RES_IDS(cmd, range_desc, type); + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + /* retrieve response parameters */ + DPRC_RSP_GET_RES_IDS(cmd, range_desc); + + return 0; +} + +int dprc_get_obj_region(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + char *obj_type, + int obj_id, + uint8_t region_index, + struct dprc_region_desc *region_desc) +{ + struct mc_command cmd = { 0 }; + int err; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_OBJ_REG, + cmd_flags, + token); + DPRC_CMD_GET_OBJ_REGION(cmd, obj_type, obj_id, region_index); + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + /* retrieve response parameters */ + DPRC_RSP_GET_OBJ_REGION(cmd, region_desc); + + return 0; +} + +int dprc_connect(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + const struct dprc_endpoint *endpoint1, + const struct dprc_endpoint *endpoint2, + const struct dprc_connection_cfg *cfg) +{ + struct mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPRC_CMDID_CONNECT, + cmd_flags, + token); + DPRC_CMD_CONNECT(cmd, endpoint1, endpoint2, cfg); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} + +int dprc_disconnect(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + const struct dprc_endpoint *endpoint) +{ + struct mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPRC_CMDID_DISCONNECT, + cmd_flags, + token); + DPRC_CMD_DISCONNECT(cmd, endpoint); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} + +int dprc_get_connection(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + const struct dprc_endpoint *endpoint1, + struct dprc_endpoint *endpoint2, + int *state) +{ + struct mc_command cmd = { 0 }; + int err; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_CONNECTION, + cmd_flags, + token); + DPRC_CMD_GET_CONNECTION(cmd, endpoint1); + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + /* retrieve response parameters */ + DPRC_RSP_GET_CONNECTION(cmd, endpoint2, *state); + + return 0; +} diff --git a/sources/uboot-be550/drivers/net/fsl-mc/fsl_dpmng_cmd.h b/sources/uboot-be550/drivers/net/fsl-mc/fsl_dpmng_cmd.h new file mode 100644 index 00000000..33f84f39 --- /dev/null +++ b/sources/uboot-be550/drivers/net/fsl-mc/fsl_dpmng_cmd.h @@ -0,0 +1,19 @@ +/* Copyright 2013-2015 Freescale Semiconductor Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __FSL_DPMNG_CMD_H +#define __FSL_DPMNG_CMD_H + +/* Command IDs */ +#define DPMNG_CMDID_GET_VERSION 0x831 + +/* cmd, param, offset, width, type, arg_name */ +#define DPMNG_RSP_GET_VERSION(cmd, mc_ver_info) \ +do { \ + MC_RSP_OP(cmd, 0, 0, 32, uint32_t, mc_ver_info->revision); \ + MC_RSP_OP(cmd, 0, 32, 32, uint32_t, mc_ver_info->major); \ + MC_RSP_OP(cmd, 1, 0, 32, uint32_t, mc_ver_info->minor); \ +} while (0) + +#endif /* __FSL_DPMNG_CMD_H */ diff --git a/sources/uboot-be550/drivers/net/fsl-mc/mc.c b/sources/uboot-be550/drivers/net/fsl-mc/mc.c new file mode 100644 index 00000000..47c93593 --- /dev/null +++ b/sources/uboot-be550/drivers/net/fsl-mc/mc.c @@ -0,0 +1,1228 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MC_RAM_BASE_ADDR_ALIGNMENT (512UL * 1024 * 1024) +#define MC_RAM_BASE_ADDR_ALIGNMENT_MASK (~(MC_RAM_BASE_ADDR_ALIGNMENT - 1)) +#define MC_RAM_SIZE_ALIGNMENT (256UL * 1024 * 1024) + +#define MC_MEM_SIZE_ENV_VAR "mcmemsize" +#define MC_BOOT_TIMEOUT_ENV_VAR "mcboottimeout" + +DECLARE_GLOBAL_DATA_PTR; +static int mc_boot_status = -1; +static int mc_dpl_applied = -1; +#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET +static int mc_aiop_applied = -1; +#endif +struct fsl_mc_io *root_mc_io = NULL; +struct fsl_mc_io *dflt_mc_io = NULL; /* child container */ +uint16_t root_dprc_handle = 0; +uint16_t dflt_dprc_handle = 0; +int child_dprc_id; +struct fsl_dpbp_obj *dflt_dpbp = NULL; +struct fsl_dpio_obj *dflt_dpio = NULL; +struct fsl_dpni_obj *dflt_dpni = NULL; + +#ifdef DEBUG +void dump_ram_words(const char *title, void *addr) +{ + int i; + uint32_t *words = addr; + + printf("Dumping beginning of %s (%p):\n", title, addr); + for (i = 0; i < 16; i++) + printf("%#x ", words[i]); + + printf("\n"); +} + +void dump_mc_ccsr_regs(struct mc_ccsr_registers __iomem *mc_ccsr_regs) +{ + printf("MC CCSR registers:\n" + "reg_gcr1 %#x\n" + "reg_gsr %#x\n" + "reg_sicbalr %#x\n" + "reg_sicbahr %#x\n" + "reg_sicapr %#x\n" + "reg_mcfbalr %#x\n" + "reg_mcfbahr %#x\n" + "reg_mcfapr %#x\n" + "reg_psr %#x\n", + mc_ccsr_regs->reg_gcr1, + mc_ccsr_regs->reg_gsr, + mc_ccsr_regs->reg_sicbalr, + mc_ccsr_regs->reg_sicbahr, + mc_ccsr_regs->reg_sicapr, + mc_ccsr_regs->reg_mcfbalr, + mc_ccsr_regs->reg_mcfbahr, + mc_ccsr_regs->reg_mcfapr, + mc_ccsr_regs->reg_psr); +} +#else + +#define dump_ram_words(title, addr) +#define dump_mc_ccsr_regs(mc_ccsr_regs) + +#endif /* DEBUG */ + +#ifndef CONFIG_SYS_LS_MC_FW_IN_DDR +/** + * Copying MC firmware or DPL image to DDR + */ +static int mc_copy_image(const char *title, + u64 image_addr, u32 image_size, u64 mc_ram_addr) +{ + debug("%s copied to address %p\n", title, (void *)mc_ram_addr); + memcpy((void *)mc_ram_addr, (void *)image_addr, image_size); + flush_dcache_range(mc_ram_addr, mc_ram_addr + image_size); + return 0; +} + +/** + * MC firmware FIT image parser checks if the image is in FIT + * format, verifies integrity of the image and calculates + * raw image address and size values. + * Returns 0 on success and a negative errno on error. + * task fail. + **/ +int parse_mc_firmware_fit_image(u64 mc_fw_addr, + const void **raw_image_addr, + size_t *raw_image_size) +{ + int format; + void *fit_hdr; + int node_offset; + const void *data; + size_t size; + const char *uname = "firmware"; + + fit_hdr = (void *)mc_fw_addr; + + /* Check if Image is in FIT format */ + format = genimg_get_format(fit_hdr); + + if (format != IMAGE_FORMAT_FIT) { + printf("fsl-mc: ERR: Bad firmware image (not a FIT image)\n"); + return -EINVAL; + } + + if (fit_check_format(fit_hdr, IMAGE_SIZE_INVAL)) { + printf("fsl-mc: ERR: Bad firmware image (bad FIT header)\n"); + return -EINVAL; + } + + node_offset = fit_image_get_node(fit_hdr, uname); + + if (node_offset < 0) { + printf("fsl-mc: ERR: Bad firmware image (missing subimage)\n"); + return -ENOENT; + } + + /* Verify MC firmware image */ + if (!(fit_image_verify(fit_hdr, node_offset))) { + printf("fsl-mc: ERR: Bad firmware image (bad CRC)\n"); + return -EINVAL; + } + + /* Get address and size of raw image */ + fit_image_get_data(fit_hdr, node_offset, &data, &size); + + *raw_image_addr = data; + *raw_image_size = size; + + return 0; +} +#endif + +/* + * Calculates the values to be used to specify the address range + * for the MC private DRAM block, in the MCFBALR/MCFBAHR registers. + * It returns the highest 512MB-aligned address within the given + * address range, in '*aligned_base_addr', and the number of 256 MiB + * blocks in it, in 'num_256mb_blocks'. + */ +static int calculate_mc_private_ram_params(u64 mc_private_ram_start_addr, + size_t mc_ram_size, + u64 *aligned_base_addr, + u8 *num_256mb_blocks) +{ + u64 addr; + u16 num_blocks; + + if (mc_ram_size % MC_RAM_SIZE_ALIGNMENT != 0) { + printf("fsl-mc: ERROR: invalid MC private RAM size (%lu)\n", + mc_ram_size); + return -EINVAL; + } + + num_blocks = mc_ram_size / MC_RAM_SIZE_ALIGNMENT; + if (num_blocks < 1 || num_blocks > 0xff) { + printf("fsl-mc: ERROR: invalid MC private RAM size (%lu)\n", + mc_ram_size); + return -EINVAL; + } + + addr = (mc_private_ram_start_addr + mc_ram_size - 1) & + MC_RAM_BASE_ADDR_ALIGNMENT_MASK; + + if (addr < mc_private_ram_start_addr) { + printf("fsl-mc: ERROR: bad start address %#llx\n", + mc_private_ram_start_addr); + return -EFAULT; + } + + *aligned_base_addr = addr; + *num_256mb_blocks = num_blocks; + return 0; +} + +static int mc_fixup_dpc(u64 dpc_addr) +{ + void *blob = (void *)dpc_addr; + int nodeoffset; + + /* delete any existing ICID pools */ + nodeoffset = fdt_path_offset(blob, "/resources/icid_pools"); + if (fdt_del_node(blob, nodeoffset) < 0) + printf("\nfsl-mc: WARNING: could not delete ICID pool\n"); + + /* add a new pool */ + nodeoffset = fdt_path_offset(blob, "/resources"); + if (nodeoffset < 0) { + printf("\nfsl-mc: ERROR: DPC is missing /resources\n"); + return -EINVAL; + } + nodeoffset = fdt_add_subnode(blob, nodeoffset, "icid_pools"); + nodeoffset = fdt_add_subnode(blob, nodeoffset, "icid_pool@0"); + do_fixup_by_path_u32(blob, "/resources/icid_pools/icid_pool@0", + "base_icid", FSL_DPAA2_STREAM_ID_START, 1); + do_fixup_by_path_u32(blob, "/resources/icid_pools/icid_pool@0", + "num", + FSL_DPAA2_STREAM_ID_END - + FSL_DPAA2_STREAM_ID_START + 1, 1); + + flush_dcache_range(dpc_addr, dpc_addr + fdt_totalsize(blob)); + + return 0; +} + +static int load_mc_dpc(u64 mc_ram_addr, size_t mc_ram_size, u64 mc_dpc_addr) +{ + u64 mc_dpc_offset; +#ifndef CONFIG_SYS_LS_MC_DPC_IN_DDR + int error; + void *dpc_fdt_hdr; + int dpc_size; +#endif + +#ifdef CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET + BUILD_BUG_ON((CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET & 0x3) != 0 || + CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET > 0xffffffff); + + mc_dpc_offset = CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET; +#else +#error "CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET not defined" +#endif + + /* + * Load the MC DPC blob in the MC private DRAM block: + */ +#ifdef CONFIG_SYS_LS_MC_DPC_IN_DDR + printf("MC DPC is preloaded to %#llx\n", mc_ram_addr + mc_dpc_offset); +#else + /* + * Get address and size of the DPC blob stored in flash: + */ + dpc_fdt_hdr = (void *)mc_dpc_addr; + + error = fdt_check_header(dpc_fdt_hdr); + if (error != 0) { + /* + * Don't return with error here, since the MC firmware can + * still boot without a DPC + */ + printf("\nfsl-mc: WARNING: No DPC image found"); + return 0; + } + + dpc_size = fdt_totalsize(dpc_fdt_hdr); + if (dpc_size > CONFIG_SYS_LS_MC_DPC_MAX_LENGTH) { + printf("\nfsl-mc: ERROR: Bad DPC image (too large: %d)\n", + dpc_size); + return -EINVAL; + } + + mc_copy_image("MC DPC blob", + (u64)dpc_fdt_hdr, dpc_size, mc_ram_addr + mc_dpc_offset); +#endif /* not defined CONFIG_SYS_LS_MC_DPC_IN_DDR */ + + if (mc_fixup_dpc(mc_ram_addr + mc_dpc_offset)) + return -EINVAL; + + dump_ram_words("DPC", (void *)(mc_ram_addr + mc_dpc_offset)); + return 0; +} + +static int load_mc_dpl(u64 mc_ram_addr, size_t mc_ram_size, u64 mc_dpl_addr) +{ + u64 mc_dpl_offset; +#ifndef CONFIG_SYS_LS_MC_DPL_IN_DDR + int error; + void *dpl_fdt_hdr; + int dpl_size; +#endif + +#ifdef CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET + BUILD_BUG_ON((CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET & 0x3) != 0 || + CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET > 0xffffffff); + + mc_dpl_offset = CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET; +#else +#error "CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET not defined" +#endif + + /* + * Load the MC DPL blob in the MC private DRAM block: + */ +#ifdef CONFIG_SYS_LS_MC_DPL_IN_DDR + printf("MC DPL is preloaded to %#llx\n", mc_ram_addr + mc_dpl_offset); +#else + /* + * Get address and size of the DPL blob stored in flash: + */ + dpl_fdt_hdr = (void *)mc_dpl_addr; + + error = fdt_check_header(dpl_fdt_hdr); + if (error != 0) { + printf("\nfsl-mc: ERROR: Bad DPL image (bad header)\n"); + return error; + } + + dpl_size = fdt_totalsize(dpl_fdt_hdr); + if (dpl_size > CONFIG_SYS_LS_MC_DPL_MAX_LENGTH) { + printf("\nfsl-mc: ERROR: Bad DPL image (too large: %d)\n", + dpl_size); + return -EINVAL; + } + + mc_copy_image("MC DPL blob", + (u64)dpl_fdt_hdr, dpl_size, mc_ram_addr + mc_dpl_offset); +#endif /* not defined CONFIG_SYS_LS_MC_DPL_IN_DDR */ + + dump_ram_words("DPL", (void *)(mc_ram_addr + mc_dpl_offset)); + return 0; +} + +/** + * Return the MC boot timeout value in milliseconds + */ +static unsigned long get_mc_boot_timeout_ms(void) +{ + unsigned long timeout_ms = CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS; + + char *timeout_ms_env_var = getenv(MC_BOOT_TIMEOUT_ENV_VAR); + + if (timeout_ms_env_var) { + timeout_ms = simple_strtoul(timeout_ms_env_var, NULL, 10); + if (timeout_ms == 0) { + printf("fsl-mc: WARNING: Invalid value for \'" + MC_BOOT_TIMEOUT_ENV_VAR + "\' environment variable: %lu\n", + timeout_ms); + + timeout_ms = CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS; + } + } + + return timeout_ms; +} + +#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET +static int load_mc_aiop_img(u64 aiop_fw_addr) +{ + u64 mc_ram_addr = mc_get_dram_addr(); +#ifndef CONFIG_SYS_LS_MC_DPC_IN_DDR + void *aiop_img; +#endif + + /* + * Load the MC AIOP image in the MC private DRAM block: + */ + +#ifdef CONFIG_SYS_LS_MC_DPC_IN_DDR + printf("MC AIOP is preloaded to %#llx\n", mc_ram_addr + + CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET); +#else + aiop_img = (void *)aiop_fw_addr; + mc_copy_image("MC AIOP image", + (u64)aiop_img, CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH, + mc_ram_addr + CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET); +#endif + mc_aiop_applied = 0; + + return 0; +} +#endif + +static int wait_for_mc(bool booting_mc, u32 *final_reg_gsr) +{ + u32 reg_gsr; + u32 mc_fw_boot_status; + unsigned long timeout_ms = get_mc_boot_timeout_ms(); + struct mc_ccsr_registers __iomem *mc_ccsr_regs = MC_CCSR_BASE_ADDR; + + dmb(); + assert(timeout_ms > 0); + for (;;) { + udelay(1000); /* throttle polling */ + reg_gsr = in_le32(&mc_ccsr_regs->reg_gsr); + mc_fw_boot_status = (reg_gsr & GSR_FS_MASK); + if (mc_fw_boot_status & 0x1) + break; + + timeout_ms--; + if (timeout_ms == 0) + break; + } + + if (timeout_ms == 0) { + printf("ERROR: timeout\n"); + + /* TODO: Get an error status from an MC CCSR register */ + return -ETIMEDOUT; + } + + if (mc_fw_boot_status != 0x1) { + /* + * TODO: Identify critical errors from the GSR register's FS + * field and for those errors, set error to -ENODEV or other + * appropriate errno, so that the status property is set to + * failure in the fsl,dprc device tree node. + */ + printf("WARNING: Firmware returned an error (GSR: %#x)\n", + reg_gsr); + } else { + printf("SUCCESS\n"); + } + + + *final_reg_gsr = reg_gsr; + return 0; +} + +int mc_init(u64 mc_fw_addr, u64 mc_dpc_addr) +{ + int error = 0; + int portal_id = 0; + struct mc_ccsr_registers __iomem *mc_ccsr_regs = MC_CCSR_BASE_ADDR; + u64 mc_ram_addr = mc_get_dram_addr(); + u32 reg_gsr; + u32 reg_mcfbalr; +#ifndef CONFIG_SYS_LS_MC_FW_IN_DDR + const void *raw_image_addr; + size_t raw_image_size = 0; +#endif + struct mc_version mc_ver_info; + u64 mc_ram_aligned_base_addr; + u8 mc_ram_num_256mb_blocks; + size_t mc_ram_size = mc_get_dram_block_size(); + + + error = calculate_mc_private_ram_params(mc_ram_addr, + mc_ram_size, + &mc_ram_aligned_base_addr, + &mc_ram_num_256mb_blocks); + if (error != 0) + goto out; + + /* + * Management Complex cores should be held at reset out of POR. + * U-boot should be the first software to touch MC. To be safe, + * we reset all cores again by setting GCR1 to 0. It doesn't do + * anything if they are held at reset. After we setup the firmware + * we kick off MC by deasserting the reset bit for core 0, and + * deasserting the reset bits for Command Portal Managers. + * The stop bits are not touched here. They are used to stop the + * cores when they are active. Setting stop bits doesn't stop the + * cores from fetching instructions when they are released from + * reset. + */ + out_le32(&mc_ccsr_regs->reg_gcr1, 0); + dmb(); + +#ifdef CONFIG_SYS_LS_MC_FW_IN_DDR + printf("MC firmware is preloaded to %#llx\n", mc_ram_addr); +#else + error = parse_mc_firmware_fit_image(mc_fw_addr, &raw_image_addr, + &raw_image_size); + if (error != 0) + goto out; + /* + * Load the MC FW at the beginning of the MC private DRAM block: + */ + mc_copy_image("MC Firmware", + (u64)raw_image_addr, raw_image_size, mc_ram_addr); +#endif + dump_ram_words("firmware", (void *)mc_ram_addr); + + error = load_mc_dpc(mc_ram_addr, mc_ram_size, mc_dpc_addr); + if (error != 0) + goto out; + + debug("mc_ccsr_regs %p\n", mc_ccsr_regs); + dump_mc_ccsr_regs(mc_ccsr_regs); + + /* + * Tell MC what is the address range of the DRAM block assigned to it: + */ + reg_mcfbalr = (u32)mc_ram_aligned_base_addr | + (mc_ram_num_256mb_blocks - 1); + out_le32(&mc_ccsr_regs->reg_mcfbalr, reg_mcfbalr); + out_le32(&mc_ccsr_regs->reg_mcfbahr, + (u32)(mc_ram_aligned_base_addr >> 32)); + out_le32(&mc_ccsr_regs->reg_mcfapr, FSL_BYPASS_AMQ); + + /* + * Tell the MC that we want delayed DPL deployment. + */ + out_le32(&mc_ccsr_regs->reg_gsr, 0xDD00); + + printf("\nfsl-mc: Booting Management Complex ... "); + + /* + * Deassert reset and release MC core 0 to run + */ + out_le32(&mc_ccsr_regs->reg_gcr1, GCR1_P1_DE_RST | GCR1_M_ALL_DE_RST); + error = wait_for_mc(true, ®_gsr); + if (error != 0) + goto out; + + /* + * TODO: need to obtain the portal_id for the root container from the + * DPL + */ + portal_id = 0; + + /* + * Initialize the global default MC portal + * And check that the MC firmware is responding portal commands: + */ + root_mc_io = (struct fsl_mc_io *)malloc(sizeof(struct fsl_mc_io)); + if (!root_mc_io) { + printf(" No memory: malloc() failed\n"); + return -ENOMEM; + } + + root_mc_io->mmio_regs = SOC_MC_PORTAL_ADDR(portal_id); + debug("Checking access to MC portal of root DPRC container (portal_id %d, portal physical addr %p)\n", + portal_id, root_mc_io->mmio_regs); + + error = mc_get_version(root_mc_io, MC_CMD_NO_FLAGS, &mc_ver_info); + if (error != 0) { + printf("fsl-mc: ERROR: Firmware version check failed (error: %d)\n", + error); + goto out; + } + + printf("fsl-mc: Management Complex booted (version: %d.%d.%d, boot status: %#x)\n", + mc_ver_info.major, mc_ver_info.minor, mc_ver_info.revision, + reg_gsr & GSR_FS_MASK); + +out: + if (error != 0) + mc_boot_status = error; + else + mc_boot_status = 0; + + return error; +} + +int mc_apply_dpl(u64 mc_dpl_addr) +{ + struct mc_ccsr_registers __iomem *mc_ccsr_regs = MC_CCSR_BASE_ADDR; + int error = 0; + u32 reg_gsr; + u64 mc_ram_addr = mc_get_dram_addr(); + size_t mc_ram_size = mc_get_dram_block_size(); + + error = load_mc_dpl(mc_ram_addr, mc_ram_size, mc_dpl_addr); + if (error != 0) + return error; + + /* + * Tell the MC to deploy the DPL: + */ + out_le32(&mc_ccsr_regs->reg_gsr, 0x0); + printf("fsl-mc: Deploying data path layout ... "); + error = wait_for_mc(false, ®_gsr); + + if (!error) + mc_dpl_applied = 0; + + return error; +} + +int get_mc_boot_status(void) +{ + return mc_boot_status; +} + +#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET +int get_aiop_apply_status(void) +{ + return mc_aiop_applied; +} +#endif + +int get_dpl_apply_status(void) +{ + return mc_dpl_applied; +} + +/** + * Return the MC address of private DRAM block. + */ +u64 mc_get_dram_addr(void) +{ + u64 mc_ram_addr; + + /* + * The MC private DRAM block was already carved at the end of DRAM + * by board_init_f() using CONFIG_SYS_MEM_TOP_HIDE: + */ + if (gd->bd->bi_dram[1].start) { + mc_ram_addr = + gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size; + } else { + mc_ram_addr = + gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size; + } + + return mc_ram_addr; +} + +/** + * Return the actual size of the MC private DRAM block. + */ +unsigned long mc_get_dram_block_size(void) +{ + unsigned long dram_block_size = CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE; + + char *dram_block_size_env_var = getenv(MC_MEM_SIZE_ENV_VAR); + + if (dram_block_size_env_var) { + dram_block_size = simple_strtoul(dram_block_size_env_var, NULL, + 10); + + if (dram_block_size < CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE) { + printf("fsl-mc: WARNING: Invalid value for \'" + MC_MEM_SIZE_ENV_VAR + "\' environment variable: %lu\n", + dram_block_size); + + dram_block_size = CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE; + } + } + + return dram_block_size; +} + +int fsl_mc_ldpaa_init(bd_t *bis) +{ + int i; + + for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) + if ((wriop_is_enabled_dpmac(i) == 1) && + (wriop_get_phy_address(i) != -1)) + ldpaa_eth_init(i, wriop_get_enet_if(i)); + return 0; +} + +static int dpio_init(void) +{ + struct qbman_swp_desc p_des; + struct dpio_attr attr; + struct dpio_cfg dpio_cfg; + int err = 0; + + dflt_dpio = (struct fsl_dpio_obj *)malloc(sizeof(struct fsl_dpio_obj)); + if (!dflt_dpio) { + printf("No memory: malloc() failed\n"); + err = -ENOMEM; + goto err_malloc; + } + + dpio_cfg.channel_mode = DPIO_LOCAL_CHANNEL; + dpio_cfg.num_priorities = 8; + + err = dpio_create(dflt_mc_io, MC_CMD_NO_FLAGS, &dpio_cfg, + &dflt_dpio->dpio_handle); + if (err < 0) { + printf("dpio_create() failed: %d\n", err); + err = -ENODEV; + goto err_create; + } + + memset(&attr, 0, sizeof(struct dpio_attr)); + err = dpio_get_attributes(dflt_mc_io, MC_CMD_NO_FLAGS, + dflt_dpio->dpio_handle, &attr); + if (err < 0) { + printf("dpio_get_attributes() failed: %d\n", err); + goto err_get_attr; + } + + dflt_dpio->dpio_id = attr.id; +#ifdef DEBUG + printf("Init: DPIO id=0x%d\n", dflt_dpio->dpio_id); +#endif + + err = dpio_enable(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio->dpio_handle); + if (err < 0) { + printf("dpio_enable() failed %d\n", err); + goto err_get_enable; + } + debug("ce_offset=0x%llx, ci_offset=0x%llx, portalid=%d, prios=%d\n", + attr.qbman_portal_ce_offset, + attr.qbman_portal_ci_offset, + attr.qbman_portal_id, + attr.num_priorities); + + p_des.cena_bar = (void *)(SOC_QBMAN_PORTALS_BASE_ADDR + + attr.qbman_portal_ce_offset); + p_des.cinh_bar = (void *)(SOC_QBMAN_PORTALS_BASE_ADDR + + attr.qbman_portal_ci_offset); + + dflt_dpio->sw_portal = qbman_swp_init(&p_des); + if (dflt_dpio->sw_portal == NULL) { + printf("qbman_swp_init() failed\n"); + goto err_get_swp_init; + } + return 0; + +err_get_swp_init: + dpio_disable(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio->dpio_handle); +err_get_enable: + free(dflt_dpio); +err_get_attr: + dpio_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio->dpio_handle); + dpio_destroy(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio->dpio_handle); +err_create: +err_malloc: + return err; +} + +static int dpio_exit(void) +{ + int err; + + err = dpio_disable(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio->dpio_handle); + if (err < 0) { + printf("dpio_disable() failed: %d\n", err); + goto err; + } + + err = dpio_destroy(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio->dpio_handle); + if (err < 0) { + printf("dpio_destroy() failed: %d\n", err); + goto err; + } + +#ifdef DEBUG + printf("Exit: DPIO id=0x%d\n", dflt_dpio->dpio_id); +#endif + + if (dflt_dpio) + free(dflt_dpio); + + return 0; +err: + return err; +} + +static int dprc_init(void) +{ + int err, child_portal_id, container_id; + struct dprc_cfg cfg; + uint64_t mc_portal_offset; + + /* Open root container */ + err = dprc_get_container_id(root_mc_io, MC_CMD_NO_FLAGS, &container_id); + if (err < 0) { + printf("dprc_get_container_id(): Root failed: %d\n", err); + goto err_root_container_id; + } + +#ifdef DEBUG + printf("Root container id = %d\n", container_id); +#endif + err = dprc_open(root_mc_io, MC_CMD_NO_FLAGS, container_id, + &root_dprc_handle); + if (err < 0) { + printf("dprc_open(): Root Container failed: %d\n", err); + goto err_root_open; + } + + if (!root_dprc_handle) { + printf("dprc_open(): Root Container Handle is not valid\n"); + goto err_root_open; + } + + cfg.options = DPRC_CFG_OPT_TOPOLOGY_CHANGES_ALLOWED | + DPRC_CFG_OPT_OBJ_CREATE_ALLOWED | + DPRC_CFG_OPT_ALLOC_ALLOWED; + cfg.icid = DPRC_GET_ICID_FROM_POOL; + cfg.portal_id = 250; + err = dprc_create_container(root_mc_io, MC_CMD_NO_FLAGS, + root_dprc_handle, + &cfg, + &child_dprc_id, + &mc_portal_offset); + if (err < 0) { + printf("dprc_create_container() failed: %d\n", err); + goto err_create; + } + + dflt_mc_io = (struct fsl_mc_io *)malloc(sizeof(struct fsl_mc_io)); + if (!dflt_mc_io) { + err = -ENOMEM; + printf(" No memory: malloc() failed\n"); + goto err_malloc; + } + + child_portal_id = MC_PORTAL_OFFSET_TO_PORTAL_ID(mc_portal_offset); + dflt_mc_io->mmio_regs = SOC_MC_PORTAL_ADDR(child_portal_id); +#ifdef DEBUG + printf("MC portal of child DPRC container: %d, physical addr %p)\n", + child_dprc_id, dflt_mc_io->mmio_regs); +#endif + + err = dprc_open(dflt_mc_io, MC_CMD_NO_FLAGS, child_dprc_id, + &dflt_dprc_handle); + if (err < 0) { + printf("dprc_open(): Child container failed: %d\n", err); + goto err_child_open; + } + + if (!dflt_dprc_handle) { + printf("dprc_open(): Child container Handle is not valid\n"); + goto err_child_open; + } + + return 0; +err_child_open: + free(dflt_mc_io); +err_malloc: + dprc_destroy_container(root_mc_io, MC_CMD_NO_FLAGS, + root_dprc_handle, child_dprc_id); +err_create: + dprc_close(root_mc_io, MC_CMD_NO_FLAGS, root_dprc_handle); +err_root_open: +err_root_container_id: + return err; +} + +static int dprc_exit(void) +{ + int err; + + err = dprc_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dprc_handle); + if (err < 0) { + printf("dprc_close(): Child failed: %d\n", err); + goto err; + } + + err = dprc_destroy_container(root_mc_io, MC_CMD_NO_FLAGS, + root_dprc_handle, child_dprc_id); + if (err < 0) { + printf("dprc_destroy_container() failed: %d\n", err); + goto err; + } + + err = dprc_close(root_mc_io, MC_CMD_NO_FLAGS, root_dprc_handle); + if (err < 0) { + printf("dprc_close(): Root failed: %d\n", err); + goto err; + } + + if (dflt_mc_io) + free(dflt_mc_io); + + if (root_mc_io) + free(root_mc_io); + + return 0; + +err: + return err; +} + +static int dpbp_init(void) +{ + int err; + struct dpbp_attr dpbp_attr; + struct dpbp_cfg dpbp_cfg; + + dflt_dpbp = (struct fsl_dpbp_obj *)malloc(sizeof(struct fsl_dpbp_obj)); + if (!dflt_dpbp) { + printf("No memory: malloc() failed\n"); + err = -ENOMEM; + goto err_malloc; + } + + dpbp_cfg.options = 512; + + err = dpbp_create(dflt_mc_io, MC_CMD_NO_FLAGS, &dpbp_cfg, + &dflt_dpbp->dpbp_handle); + + if (err < 0) { + err = -ENODEV; + printf("dpbp_create() failed: %d\n", err); + goto err_create; + } + + memset(&dpbp_attr, 0, sizeof(struct dpbp_attr)); + err = dpbp_get_attributes(dflt_mc_io, MC_CMD_NO_FLAGS, + dflt_dpbp->dpbp_handle, + &dpbp_attr); + if (err < 0) { + printf("dpbp_get_attributes() failed: %d\n", err); + goto err_get_attr; + } + + dflt_dpbp->dpbp_attr.id = dpbp_attr.id; +#ifdef DEBUG + printf("Init: DPBP id=0x%d\n", dflt_dpbp->dpbp_attr.id); +#endif + + err = dpbp_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpbp->dpbp_handle); + if (err < 0) { + printf("dpbp_close() failed: %d\n", err); + goto err_close; + } + + return 0; + +err_close: + free(dflt_dpbp); +err_get_attr: + dpbp_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpbp->dpbp_handle); + dpbp_destroy(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpbp->dpbp_handle); +err_create: +err_malloc: + return err; +} + +static int dpbp_exit(void) +{ + int err; + + err = dpbp_open(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpbp->dpbp_attr.id, + &dflt_dpbp->dpbp_handle); + if (err < 0) { + printf("dpbp_open() failed: %d\n", err); + goto err; + } + + err = dpbp_destroy(dflt_mc_io, MC_CMD_NO_FLAGS, + dflt_dpbp->dpbp_handle); + if (err < 0) { + printf("dpbp_destroy() failed: %d\n", err); + goto err; + } + +#ifdef DEBUG + printf("Exit: DPBP id=0x%d\n", dflt_dpbp->dpbp_attr.id); +#endif + + if (dflt_dpbp) + free(dflt_dpbp); + return 0; + +err: + return err; +} + +static int dpni_init(void) +{ + int err; + struct dpni_attr dpni_attr; + struct dpni_cfg dpni_cfg; + + dflt_dpni = (struct fsl_dpni_obj *)malloc(sizeof(struct fsl_dpni_obj)); + if (!dflt_dpni) { + printf("No memory: malloc() failed\n"); + err = -ENOMEM; + goto err_malloc; + } + + memset(&dpni_cfg, 0, sizeof(dpni_cfg)); + dpni_cfg.adv.options = DPNI_OPT_UNICAST_FILTER | + DPNI_OPT_MULTICAST_FILTER; + + err = dpni_create(dflt_mc_io, MC_CMD_NO_FLAGS, &dpni_cfg, + &dflt_dpni->dpni_handle); + + if (err < 0) { + err = -ENODEV; + printf("dpni_create() failed: %d\n", err); + goto err_create; + } + + memset(&dpni_attr, 0, sizeof(struct dpni_attr)); + err = dpni_get_attributes(dflt_mc_io, MC_CMD_NO_FLAGS, + dflt_dpni->dpni_handle, + &dpni_attr); + if (err < 0) { + printf("dpni_get_attributes() failed: %d\n", err); + goto err_get_attr; + } + + dflt_dpni->dpni_id = dpni_attr.id; +#ifdef DEBUG + printf("Init: DPNI id=0x%d\n", dflt_dpni->dpni_id); +#endif + + err = dpni_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle); + if (err < 0) { + printf("dpni_close() failed: %d\n", err); + goto err_close; + } + + return 0; + +err_close: + free(dflt_dpni); +err_get_attr: + dpni_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle); + dpni_destroy(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle); +err_create: +err_malloc: + return err; +} + +static int dpni_exit(void) +{ + int err; + + err = dpni_open(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_id, + &dflt_dpni->dpni_handle); + if (err < 0) { + printf("dpni_open() failed: %d\n", err); + goto err; + } + + err = dpni_destroy(dflt_mc_io, MC_CMD_NO_FLAGS, + dflt_dpni->dpni_handle); + if (err < 0) { + printf("dpni_destroy() failed: %d\n", err); + goto err; + } + +#ifdef DEBUG + printf("Exit: DPNI id=0x%d\n", dflt_dpni->dpni_id); +#endif + + if (dflt_dpni) + free(dflt_dpni); + return 0; + +err: + return err; +} + +static int mc_init_object(void) +{ + int err = 0; + + err = dprc_init(); + if (err < 0) { + printf("dprc_init() failed: %d\n", err); + goto err; + } + + err = dpbp_init(); + if (err < 0) { + printf("dpbp_init() failed: %d\n", err); + goto err; + } + + err = dpio_init(); + if (err < 0) { + printf("dpio_init() failed: %d\n", err); + goto err; + } + + err = dpni_init(); + if (err < 0) { + printf("dpni_init() failed: %d\n", err); + goto err; + } + + return 0; +err: + return err; +} + +int fsl_mc_ldpaa_exit(bd_t *bd) +{ + int err = 0; + + if (bd && get_mc_boot_status() == -1) + return 0; + + if (bd && !get_mc_boot_status() && get_dpl_apply_status() == -1) { + printf("ERROR: fsl-mc: DPL is not applied\n"); + err = -ENODEV; + return err; + } + + if (bd && !get_mc_boot_status() && !get_dpl_apply_status()) + return err; + + err = dpbp_exit(); + if (err < 0) { + printf("dpni_exit() failed: %d\n", err); + goto err; + } + + err = dpio_exit(); + if (err < 0) { + printf("dpio_exit() failed: %d\n", err); + goto err; + } + + err = dpni_exit(); + if (err < 0) { + printf("dpni_exit() failed: %d\n", err); + goto err; + } + + err = dprc_exit(); + if (err < 0) { + printf("dprc_exit() failed: %d\n", err); + goto err; + } + + return 0; +err: + return err; +} + +static int do_fsl_mc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int err = 0; + if (argc < 3) + goto usage; + + switch (argv[1][0]) { + case 's': { + char sub_cmd; + u64 mc_fw_addr, mc_dpc_addr; +#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET + u64 aiop_fw_addr; +#endif + + sub_cmd = argv[2][0]; + switch (sub_cmd) { + case 'm': + if (argc < 5) + goto usage; + + if (get_mc_boot_status() == 0) { + printf("fsl-mc: MC is already booted"); + printf("\n"); + return err; + } + mc_fw_addr = simple_strtoull(argv[3], NULL, 16); + mc_dpc_addr = simple_strtoull(argv[4], NULL, + 16); + + if (!mc_init(mc_fw_addr, mc_dpc_addr)) + err = mc_init_object(); + break; + +#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET + case 'a': + if (argc < 4) + goto usage; + if (get_aiop_apply_status() == 0) { + printf("fsl-mc: AIOP FW is already"); + printf(" applied\n"); + return err; + } + + aiop_fw_addr = simple_strtoull(argv[3], NULL, + 16); + + err = load_mc_aiop_img(aiop_fw_addr); + if (!err) + printf("fsl-mc: AIOP FW applied\n"); + break; +#endif + default: + printf("Invalid option: %s\n", argv[2]); + goto usage; + + break; + } + } + break; + + case 'a': { + u64 mc_dpl_addr; + + if (argc < 4) + goto usage; + + if (get_dpl_apply_status() == 0) { + printf("fsl-mc: DPL already applied\n"); + return err; + } + + mc_dpl_addr = simple_strtoull(argv[3], NULL, + 16); + + if (get_mc_boot_status() != 0) { + printf("fsl-mc: Deploying data path layout .."); + printf("ERROR (MC is not booted)\n"); + return -ENODEV; + } + + if (!fsl_mc_ldpaa_exit(NULL)) + err = mc_apply_dpl(mc_dpl_addr); + break; + } + default: + printf("Invalid option: %s\n", argv[1]); + goto usage; + break; + } + return err; + usage: + return CMD_RET_USAGE; +} + +U_BOOT_CMD( + fsl_mc, CONFIG_SYS_MAXARGS, 1, do_fsl_mc, + "DPAA2 command to manage Management Complex (MC)", + "start mc [FW_addr] [DPC_addr] - Start Management Complex\n" + "fsl_mc apply DPL [DPL_addr] - Apply DPL file\n" + "fsl_mc start aiop [FW_addr] - Start AIOP\n" +); diff --git a/sources/uboot-be550/drivers/net/fsl-mc/mc_sys.c b/sources/uboot-be550/drivers/net/fsl-mc/mc_sys.c new file mode 100644 index 00000000..71e14564 --- /dev/null +++ b/sources/uboot-be550/drivers/net/fsl-mc/mc_sys.c @@ -0,0 +1,63 @@ +/* + * Freescale Layerscape MC I/O wrapper + * + * Copyright (C) 2013-2015 Freescale Semiconductor, Inc. + * Author: German Rivera + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +#define MC_CMD_HDR_READ_CMDID(_hdr) \ + ((uint16_t)mc_dec((_hdr), MC_CMD_HDR_CMDID_O, MC_CMD_HDR_CMDID_S)) + +/** + * mc_send_command - Send MC command and wait for response + * + * @mc_io: Pointer to MC I/O object to be used + * @cmd: MC command buffer. On input, it contains the command to send to the MC. + * On output, it contains the response from the MC if any. + * + * Depending on the sharing option specified when creating the MC portal + * wrapper, this function will use a spinlock or mutex to ensure exclusive + * access to the MC portal from the point when the command is sent until a + * response is received from the MC. + */ +int mc_send_command(struct fsl_mc_io *mc_io, + struct mc_command *cmd) +{ + enum mc_cmd_status status; + int timeout = 12000; + + mc_write_command(mc_io->mmio_regs, cmd); + + for ( ; ; ) { + status = mc_read_response(mc_io->mmio_regs, cmd); + if (status != MC_CMD_STATUS_READY) + break; + + if (--timeout == 0) { + printf("Error: Timeout waiting for MC response\n"); + return -ETIMEDOUT; + } + + udelay(500); + } + + if (status != MC_CMD_STATUS_OK) { + printf("Error: MC command failed (portal: %p, obj handle: %#x, command: %#x, status: %#x)\n", + mc_io->mmio_regs, + (unsigned int)MC_CMD_HDR_READ_TOKEN(cmd->header), + (unsigned int)MC_CMD_HDR_READ_CMDID(cmd->header), + (unsigned int)status); + + return -EIO; + } + + return 0; +} diff --git a/sources/uboot-be550/drivers/net/fsl_mcdmafec.c b/sources/uboot-be550/drivers/net/fsl_mcdmafec.c new file mode 100644 index 00000000..792534b1 --- /dev/null +++ b/sources/uboot-be550/drivers/net/fsl_mcdmafec.c @@ -0,0 +1,572 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +#undef ET_DEBUG +#undef MII_DEBUG + +/* Ethernet Transmit and Receive Buffers */ +#define DBUF_LENGTH 1520 +#define PKT_MAXBUF_SIZE 1518 +#define PKT_MINBUF_SIZE 64 +#define PKT_MAXBLR_SIZE 1536 +#define LAST_PKTBUFSRX PKTBUFSRX - 1 +#define BD_ENET_RX_W_E (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY) +#define BD_ENET_TX_RDY_LST (BD_ENET_TX_READY | BD_ENET_TX_LAST) +#define FIFO_ERRSTAT (FIFO_STAT_RXW | FIFO_STAT_UF | FIFO_STAT_OF) + +/* RxBD bits definitions */ +#define BD_ENET_RX_ERR (BD_ENET_RX_LG | BD_ENET_RX_NO | BD_ENET_RX_CR | \ + BD_ENET_RX_OV | BD_ENET_RX_TR) + +#include +#include + +#include "MCD_dma.h" + +DECLARE_GLOBAL_DATA_PTR; + +struct fec_info_dma fec_info[] = { +#ifdef CONFIG_SYS_FEC0_IOBASE + { + 0, /* index */ + CONFIG_SYS_FEC0_IOBASE, /* io base */ + CONFIG_SYS_FEC0_PINMUX, /* gpio pin muxing */ + CONFIG_SYS_FEC0_MIIBASE, /* mii base */ + -1, /* phy_addr */ + 0, /* duplex and speed */ + 0, /* phy name */ + 0, /* phyname init */ + 0, /* RX BD */ + 0, /* TX BD */ + 0, /* rx Index */ + 0, /* tx Index */ + 0, /* tx buffer */ + 0, /* initialized flag */ + (struct fec_info_dma *)-1, /* next */ + FEC0_RX_TASK, /* rxTask */ + FEC0_TX_TASK, /* txTask */ + FEC0_RX_PRIORITY, /* rxPri */ + FEC0_TX_PRIORITY, /* txPri */ + FEC0_RX_INIT, /* rxInit */ + FEC0_TX_INIT, /* txInit */ + 0, /* usedTbdIndex */ + 0, /* cleanTbdNum */ + }, +#endif +#ifdef CONFIG_SYS_FEC1_IOBASE + { + 1, /* index */ + CONFIG_SYS_FEC1_IOBASE, /* io base */ + CONFIG_SYS_FEC1_PINMUX, /* gpio pin muxing */ + CONFIG_SYS_FEC1_MIIBASE, /* mii base */ + -1, /* phy_addr */ + 0, /* duplex and speed */ + 0, /* phy name */ + 0, /* phy name init */ +#ifdef CONFIG_SYS_DMA_USE_INTSRAM + (cbd_t *)DBUF_LENGTH, /* RX BD */ +#else + 0, /* RX BD */ +#endif + 0, /* TX BD */ + 0, /* rx Index */ + 0, /* tx Index */ + 0, /* tx buffer */ + 0, /* initialized flag */ + (struct fec_info_dma *)-1, /* next */ + FEC1_RX_TASK, /* rxTask */ + FEC1_TX_TASK, /* txTask */ + FEC1_RX_PRIORITY, /* rxPri */ + FEC1_TX_PRIORITY, /* txPri */ + FEC1_RX_INIT, /* rxInit */ + FEC1_TX_INIT, /* txInit */ + 0, /* usedTbdIndex */ + 0, /* cleanTbdNum */ + } +#endif +}; + +static int fec_send(struct eth_device *dev, void *packet, int length); +static int fec_recv(struct eth_device *dev); +static int fec_init(struct eth_device *dev, bd_t * bd); +static void fec_halt(struct eth_device *dev); + +#ifdef ET_DEBUG +static void dbg_fec_regs(struct eth_device *dev) +{ + struct fec_info_dma *info = dev->priv; + volatile fecdma_t *fecp = (fecdma_t *) (info->iobase); + + printf("=====\n"); + printf("ievent %x - %x\n", (int)&fecp->eir, fecp->eir); + printf("imask %x - %x\n", (int)&fecp->eimr, fecp->eimr); + printf("ecntrl %x - %x\n", (int)&fecp->ecr, fecp->ecr); + printf("mii_mframe %x - %x\n", (int)&fecp->mmfr, fecp->mmfr); + printf("mii_speed %x - %x\n", (int)&fecp->mscr, fecp->mscr); + printf("mii_ctrlstat %x - %x\n", (int)&fecp->mibc, fecp->mibc); + printf("r_cntrl %x - %x\n", (int)&fecp->rcr, fecp->rcr); + printf("r hash %x - %x\n", (int)&fecp->rhr, fecp->rhr); + printf("x_cntrl %x - %x\n", (int)&fecp->tcr, fecp->tcr); + printf("padr_l %x - %x\n", (int)&fecp->palr, fecp->palr); + printf("padr_u %x - %x\n", (int)&fecp->paur, fecp->paur); + printf("op_pause %x - %x\n", (int)&fecp->opd, fecp->opd); + printf("iadr_u %x - %x\n", (int)&fecp->iaur, fecp->iaur); + printf("iadr_l %x - %x\n", (int)&fecp->ialr, fecp->ialr); + printf("gadr_u %x - %x\n", (int)&fecp->gaur, fecp->gaur); + printf("gadr_l %x - %x\n", (int)&fecp->galr, fecp->galr); + printf("x_wmrk %x - %x\n", (int)&fecp->tfwr, fecp->tfwr); + printf("r_fdata %x - %x\n", (int)&fecp->rfdr, fecp->rfdr); + printf("r_fstat %x - %x\n", (int)&fecp->rfsr, fecp->rfsr); + printf("r_fctrl %x - %x\n", (int)&fecp->rfcr, fecp->rfcr); + printf("r_flrfp %x - %x\n", (int)&fecp->rlrfp, fecp->rlrfp); + printf("r_flwfp %x - %x\n", (int)&fecp->rlwfp, fecp->rlwfp); + printf("r_frfar %x - %x\n", (int)&fecp->rfar, fecp->rfar); + printf("r_frfrp %x - %x\n", (int)&fecp->rfrp, fecp->rfrp); + printf("r_frfwp %x - %x\n", (int)&fecp->rfwp, fecp->rfwp); + printf("t_fdata %x - %x\n", (int)&fecp->tfdr, fecp->tfdr); + printf("t_fstat %x - %x\n", (int)&fecp->tfsr, fecp->tfsr); + printf("t_fctrl %x - %x\n", (int)&fecp->tfcr, fecp->tfcr); + printf("t_flrfp %x - %x\n", (int)&fecp->tlrfp, fecp->tlrfp); + printf("t_flwfp %x - %x\n", (int)&fecp->tlwfp, fecp->tlwfp); + printf("t_ftfar %x - %x\n", (int)&fecp->tfar, fecp->tfar); + printf("t_ftfrp %x - %x\n", (int)&fecp->tfrp, fecp->tfrp); + printf("t_ftfwp %x - %x\n", (int)&fecp->tfwp, fecp->tfwp); + printf("frst %x - %x\n", (int)&fecp->frst, fecp->frst); + printf("ctcwr %x - %x\n", (int)&fecp->ctcwr, fecp->ctcwr); +} +#endif + +static void set_fec_duplex_speed(volatile fecdma_t * fecp, bd_t * bd, + int dup_spd) +{ + if ((dup_spd >> 16) == FULL) { + /* Set maximum frame length */ + fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | FEC_RCR_MII_MODE | + FEC_RCR_PROM | 0x100; + fecp->tcr = FEC_TCR_FDEN; + } else { + /* Half duplex mode */ + fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | + FEC_RCR_MII_MODE | FEC_RCR_DRT; + fecp->tcr &= ~FEC_TCR_FDEN; + } + + if ((dup_spd & 0xFFFF) == _100BASET) { +#ifdef MII_DEBUG + printf("100Mbps\n"); +#endif + bd->bi_ethspeed = 100; + } else { +#ifdef MII_DEBUG + printf("10Mbps\n"); +#endif + bd->bi_ethspeed = 10; + } +} + +static int fec_send(struct eth_device *dev, void *packet, int length) +{ + struct fec_info_dma *info = dev->priv; + cbd_t *pTbd, *pUsedTbd; + u16 phyStatus; + + miiphy_read(dev->name, info->phy_addr, MII_BMSR, &phyStatus); + + /* process all the consumed TBDs */ + while (info->cleanTbdNum < CONFIG_SYS_TX_ETH_BUFFER) { + pUsedTbd = &info->txbd[info->usedTbdIdx]; + if (pUsedTbd->cbd_sc & BD_ENET_TX_READY) { +#ifdef ET_DEBUG + printf("Cannot clean TBD %d, in use\n", + info->cleanTbdNum); +#endif + return 0; + } + + /* clean this buffer descriptor */ + if (info->usedTbdIdx == (CONFIG_SYS_TX_ETH_BUFFER - 1)) + pUsedTbd->cbd_sc = BD_ENET_TX_WRAP; + else + pUsedTbd->cbd_sc = 0; + + /* update some indeces for a correct handling of the TBD ring */ + info->cleanTbdNum++; + info->usedTbdIdx = (info->usedTbdIdx + 1) % CONFIG_SYS_TX_ETH_BUFFER; + } + + /* Check for valid length of data. */ + if ((length > 1500) || (length <= 0)) { + return -1; + } + + /* Check the number of vacant TxBDs. */ + if (info->cleanTbdNum < 1) { + printf("No available TxBDs ...\n"); + return -1; + } + + /* Get the first TxBD to send the mac header */ + pTbd = &info->txbd[info->txIdx]; + pTbd->cbd_datlen = length; + pTbd->cbd_bufaddr = (u32) packet; + pTbd->cbd_sc |= BD_ENET_TX_LAST | BD_ENET_TX_TC | BD_ENET_TX_READY; + info->txIdx = (info->txIdx + 1) % CONFIG_SYS_TX_ETH_BUFFER; + + /* Enable DMA transmit task */ + MCD_continDma(info->txTask); + + info->cleanTbdNum -= 1; + + /* wait until frame is sent . */ + while (pTbd->cbd_sc & BD_ENET_TX_READY) { + udelay(10); + } + + return (int)(info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_STATS); +} + +static int fec_recv(struct eth_device *dev) +{ + struct fec_info_dma *info = dev->priv; + volatile fecdma_t *fecp = (fecdma_t *) (info->iobase); + + cbd_t *prbd = &info->rxbd[info->rxIdx]; + u32 ievent; + int frame_length, len = 0; + + /* Check if any critical events have happened */ + ievent = fecp->eir; + if (ievent != 0) { + fecp->eir = ievent; + + if (ievent & (FEC_EIR_BABT | FEC_EIR_TXERR | FEC_EIR_RXERR)) { + printf("fec_recv: error\n"); + fec_halt(dev); + fec_init(dev, NULL); + return 0; + } + + if (ievent & FEC_EIR_HBERR) { + /* Heartbeat error */ + fecp->tcr |= FEC_TCR_GTS; + } + + if (ievent & FEC_EIR_GRA) { + /* Graceful stop complete */ + if (fecp->tcr & FEC_TCR_GTS) { + printf("fec_recv: tcr_gts\n"); + fec_halt(dev); + fecp->tcr &= ~FEC_TCR_GTS; + fec_init(dev, NULL); + } + } + } + + if (!(prbd->cbd_sc & BD_ENET_RX_EMPTY)) { + if ((prbd->cbd_sc & BD_ENET_RX_LAST) && + !(prbd->cbd_sc & BD_ENET_RX_ERR) && + ((prbd->cbd_datlen - 4) > 14)) { + + /* Get buffer address and size */ + frame_length = prbd->cbd_datlen - 4; + + /* Fill the buffer and pass it to upper layers */ + net_process_received_packet((uchar *)prbd->cbd_bufaddr, + frame_length); + len = frame_length; + } + + /* Reset buffer descriptor as empty */ + if ((info->rxIdx) == (PKTBUFSRX - 1)) + prbd->cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY); + else + prbd->cbd_sc = BD_ENET_RX_EMPTY; + + prbd->cbd_datlen = PKTSIZE_ALIGN; + + /* Now, we have an empty RxBD, restart the DMA receive task */ + MCD_continDma(info->rxTask); + + /* Increment BD count */ + info->rxIdx = (info->rxIdx + 1) % PKTBUFSRX; + } + + return len; +} + +static void fec_set_hwaddr(volatile fecdma_t * fecp, u8 * mac) +{ + u8 currByte; /* byte for which to compute the CRC */ + int byte; /* loop - counter */ + int bit; /* loop - counter */ + u32 crc = 0xffffffff; /* initial value */ + + for (byte = 0; byte < 6; byte++) { + currByte = mac[byte]; + for (bit = 0; bit < 8; bit++) { + if ((currByte & 0x01) ^ (crc & 0x01)) { + crc >>= 1; + crc = crc ^ 0xedb88320; + } else { + crc >>= 1; + } + currByte >>= 1; + } + } + + crc = crc >> 26; + + /* Set individual hash table register */ + if (crc >= 32) { + fecp->ialr = (1 << (crc - 32)); + fecp->iaur = 0; + } else { + fecp->ialr = 0; + fecp->iaur = (1 << crc); + } + + /* Set physical address */ + fecp->palr = (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3]; + fecp->paur = (mac[4] << 24) + (mac[5] << 16) + 0x8808; + + /* Clear multicast address hash table */ + fecp->gaur = 0; + fecp->galr = 0; +} + +static int fec_init(struct eth_device *dev, bd_t * bd) +{ + struct fec_info_dma *info = dev->priv; + volatile fecdma_t *fecp = (fecdma_t *) (info->iobase); + int i; + uchar enetaddr[6]; + +#ifdef ET_DEBUG + printf("fec_init: iobase 0x%08x ...\n", info->iobase); +#endif + + fecpin_setclear(dev, 1); + + fec_halt(dev); + +#if defined(CONFIG_CMD_MII) || defined (CONFIG_MII) || \ + defined (CONFIG_SYS_DISCOVER_PHY) + + mii_init(); + + set_fec_duplex_speed(fecp, bd, info->dup_spd); +#else +#ifndef CONFIG_SYS_DISCOVER_PHY + set_fec_duplex_speed(fecp, bd, (FECDUPLEX << 16) | FECSPEED); +#endif /* ifndef CONFIG_SYS_DISCOVER_PHY */ +#endif /* CONFIG_CMD_MII || CONFIG_MII */ + + /* We use strictly polling mode only */ + fecp->eimr = 0; + + /* Clear any pending interrupt */ + fecp->eir = 0xffffffff; + + /* Set station address */ + if ((u32) fecp == CONFIG_SYS_FEC0_IOBASE) + eth_getenv_enetaddr("ethaddr", enetaddr); + else + eth_getenv_enetaddr("eth1addr", enetaddr); + fec_set_hwaddr(fecp, enetaddr); + + /* Set Opcode/Pause Duration Register */ + fecp->opd = 0x00010020; + + /* Setup Buffers and Buffer Desriptors */ + info->rxIdx = 0; + info->txIdx = 0; + + /* Setup Receiver Buffer Descriptors (13.14.24.18) + * Settings: Empty, Wrap */ + for (i = 0; i < PKTBUFSRX; i++) { + info->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY; + info->rxbd[i].cbd_datlen = PKTSIZE_ALIGN; + info->rxbd[i].cbd_bufaddr = (uint) net_rx_packets[i]; + } + info->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP; + + /* Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19) + * Settings: Last, Tx CRC */ + for (i = 0; i < CONFIG_SYS_TX_ETH_BUFFER; i++) { + info->txbd[i].cbd_sc = 0; + info->txbd[i].cbd_datlen = 0; + info->txbd[i].cbd_bufaddr = (uint) (&info->txbuf[0]); + } + info->txbd[CONFIG_SYS_TX_ETH_BUFFER - 1].cbd_sc |= BD_ENET_TX_WRAP; + + info->usedTbdIdx = 0; + info->cleanTbdNum = CONFIG_SYS_TX_ETH_BUFFER; + + /* Set Rx FIFO alarm and granularity value */ + fecp->rfcr = 0x0c000000; + fecp->rfar = 0x0000030c; + + /* Set Tx FIFO granularity value */ + fecp->tfcr = FIFO_CTRL_FRAME | FIFO_CTRL_GR(6) | 0x00040000; + fecp->tfar = 0x00000080; + + fecp->tfwr = 0x2; + fecp->ctcwr = 0x03000000; + + /* Enable DMA receive task */ + MCD_startDma(info->rxTask, /* Dma channel */ + (s8 *) info->rxbd, /*Source Address */ + 0, /* Source increment */ + (s8 *) (&fecp->rfdr), /* dest */ + 4, /* dest increment */ + 0, /* DMA size */ + 4, /* xfer size */ + info->rxInit, /* initiator */ + info->rxPri, /* priority */ + (MCD_FECRX_DMA | MCD_TT_FLAGS_DEF), /* Flags */ + (MCD_NO_CSUM | MCD_NO_BYTE_SWAP) /* Function description */ + ); + + /* Enable DMA tx task with no ready buffer descriptors */ + MCD_startDma(info->txTask, /* Dma channel */ + (s8 *) info->txbd, /*Source Address */ + 0, /* Source increment */ + (s8 *) (&fecp->tfdr), /* dest */ + 4, /* dest incr */ + 0, /* DMA size */ + 4, /* xfer size */ + info->txInit, /* initiator */ + info->txPri, /* priority */ + (MCD_FECTX_DMA | MCD_TT_FLAGS_DEF), /* Flags */ + (MCD_NO_CSUM | MCD_NO_BYTE_SWAP) /* Function description */ + ); + + /* Now enable the transmit and receive processing */ + fecp->ecr |= FEC_ECR_ETHER_EN; + + return 1; +} + +static void fec_halt(struct eth_device *dev) +{ + struct fec_info_dma *info = dev->priv; + volatile fecdma_t *fecp = (fecdma_t *) (info->iobase); + int counter = 0xffff; + + /* issue graceful stop command to the FEC transmitter if necessary */ + fecp->tcr |= FEC_TCR_GTS; + + /* wait for graceful stop to register */ + while ((counter--) && (!(fecp->eir & FEC_EIR_GRA))) ; + + /* Disable DMA tasks */ + MCD_killDma(info->txTask); + MCD_killDma(info->rxTask);; + + /* Disable the Ethernet Controller */ + fecp->ecr &= ~FEC_ECR_ETHER_EN; + + /* Clear FIFO status registers */ + fecp->rfsr &= FIFO_ERRSTAT; + fecp->tfsr &= FIFO_ERRSTAT; + + fecp->frst = 0x01000000; + + /* Issue a reset command to the FEC chip */ + fecp->ecr |= FEC_ECR_RESET; + + /* wait at least 20 clock cycles */ + udelay(10000); + +#ifdef ET_DEBUG + printf("Ethernet task stopped\n"); +#endif +} + +int mcdmafec_initialize(bd_t * bis) +{ + struct eth_device *dev; + int i; +#ifdef CONFIG_SYS_DMA_USE_INTSRAM + u32 tmp = CONFIG_SYS_INTSRAM + 0x2000; +#endif + + for (i = 0; i < ARRAY_SIZE(fec_info); i++) { + + dev = + (struct eth_device *)memalign(CONFIG_SYS_CACHELINE_SIZE, + sizeof *dev); + if (dev == NULL) + hang(); + + memset(dev, 0, sizeof(*dev)); + + sprintf(dev->name, "FEC%d", fec_info[i].index); + + dev->priv = &fec_info[i]; + dev->init = fec_init; + dev->halt = fec_halt; + dev->send = fec_send; + dev->recv = fec_recv; + + /* setup Receive and Transmit buffer descriptor */ +#ifdef CONFIG_SYS_DMA_USE_INTSRAM + fec_info[i].rxbd = (cbd_t *)((u32)fec_info[i].rxbd + tmp); + tmp = (u32)fec_info[i].rxbd; + fec_info[i].txbd = + (cbd_t *)((u32)fec_info[i].txbd + tmp + + (PKTBUFSRX * sizeof(cbd_t))); + tmp = (u32)fec_info[i].txbd; + fec_info[i].txbuf = + (char *)((u32)fec_info[i].txbuf + tmp + + (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t))); + tmp = (u32)fec_info[i].txbuf; +#else + fec_info[i].rxbd = + (cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE, + (PKTBUFSRX * sizeof(cbd_t))); + fec_info[i].txbd = + (cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE, + (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t))); + fec_info[i].txbuf = + (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, DBUF_LENGTH); +#endif + +#ifdef ET_DEBUG + printf("rxbd %x txbd %x\n", + (int)fec_info[i].rxbd, (int)fec_info[i].txbd); +#endif + + fec_info[i].phy_name = (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, 32); + + eth_register(dev); + +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) + miiphy_register(dev->name, + mcffec_miiphy_read, mcffec_miiphy_write); +#endif + + if (i > 0) + fec_info[i - 1].next = &fec_info[i]; + } + fec_info[i - 1].next = &fec_info[0]; + + /* default speed */ + bis->bi_ethspeed = 10; + + return 0; +} diff --git a/sources/uboot-be550/drivers/net/fsl_mdio.c b/sources/uboot-be550/drivers/net/fsl_mdio.c new file mode 100644 index 00000000..d6b181b3 --- /dev/null +++ b/sources/uboot-be550/drivers/net/fsl_mdio.c @@ -0,0 +1,112 @@ +/* + * Copyright 2009-2010, 2013 Freescale Semiconductor, Inc. + * Jun-jie Zhang + * Mingkai Hu + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include +#include + +void tsec_local_mdio_write(struct tsec_mii_mng __iomem *phyregs, int port_addr, + int dev_addr, int regnum, int value) +{ + int timeout = 1000000; + + out_be32(&phyregs->miimadd, (port_addr << 8) | (regnum & 0x1f)); + out_be32(&phyregs->miimcon, value); + /* Memory barrier */ + mb(); + + while ((in_be32(&phyregs->miimind) & MIIMIND_BUSY) && timeout--) + ; +} + +int tsec_local_mdio_read(struct tsec_mii_mng __iomem *phyregs, int port_addr, + int dev_addr, int regnum) +{ + int value; + int timeout = 1000000; + + /* Put the address of the phy, and the register + * number into MIIMADD */ + out_be32(&phyregs->miimadd, (port_addr << 8) | (regnum & 0x1f)); + + /* Clear the command register, and wait */ + out_be32(&phyregs->miimcom, 0); + /* Memory barrier */ + mb(); + + /* Initiate a read command, and wait */ + out_be32(&phyregs->miimcom, MIIMCOM_READ_CYCLE); + /* Memory barrier */ + mb(); + + /* Wait for the the indication that the read is done */ + while ((in_be32(&phyregs->miimind) & (MIIMIND_NOTVALID | MIIMIND_BUSY)) + && timeout--) + ; + + /* Grab the value read from the PHY */ + value = in_be32(&phyregs->miimstat); + + return value; +} + +static int fsl_pq_mdio_reset(struct mii_dev *bus) +{ + struct tsec_mii_mng __iomem *regs = + (struct tsec_mii_mng __iomem *)bus->priv; + + /* Reset MII (due to new addresses) */ + out_be32(®s->miimcfg, MIIMCFG_RESET_MGMT); + + out_be32(®s->miimcfg, MIIMCFG_INIT_VALUE); + + while (in_be32(®s->miimind) & MIIMIND_BUSY) + ; + + return 0; +} + +int tsec_phy_read(struct mii_dev *bus, int addr, int dev_addr, int regnum) +{ + struct tsec_mii_mng __iomem *phyregs = + (struct tsec_mii_mng __iomem *)bus->priv; + + return tsec_local_mdio_read(phyregs, addr, dev_addr, regnum); +} + +int tsec_phy_write(struct mii_dev *bus, int addr, int dev_addr, int regnum, + u16 value) +{ + struct tsec_mii_mng __iomem *phyregs = + (struct tsec_mii_mng __iomem *)bus->priv; + + tsec_local_mdio_write(phyregs, addr, dev_addr, regnum, value); + + return 0; +} + +int fsl_pq_mdio_init(bd_t *bis, struct fsl_pq_mdio_info *info) +{ + struct mii_dev *bus = mdio_alloc(); + + if (!bus) { + printf("Failed to allocate FSL MDIO bus\n"); + return -1; + } + + bus->read = tsec_phy_read; + bus->write = tsec_phy_write; + bus->reset = fsl_pq_mdio_reset; + sprintf(bus->name, info->name); + + bus->priv = (void *)info->regs; + + return mdio_register(bus); +} diff --git a/sources/uboot-be550/drivers/net/ftgmac100.c b/sources/uboot-be550/drivers/net/ftgmac100.c new file mode 100644 index 00000000..515f0b27 --- /dev/null +++ b/sources/uboot-be550/drivers/net/ftgmac100.c @@ -0,0 +1,583 @@ +/* + * Faraday FTGMAC100 Ethernet + * + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang + * + * (C) Copyright 2010 Andes Technology + * Macpaul Lin + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "ftgmac100.h" + +#define ETH_ZLEN 60 +#define CFG_XBUF_SIZE 1536 + +/* RBSR - hw default init value is also 0x640 */ +#define RBSR_DEFAULT_VALUE 0x640 + +/* PKTBUFSTX/PKTBUFSRX must both be power of 2 */ +#define PKTBUFSTX 4 /* must be power of 2 */ + +struct ftgmac100_data { + ulong txdes_dma; + struct ftgmac100_txdes *txdes; + ulong rxdes_dma; + struct ftgmac100_rxdes *rxdes; + int tx_index; + int rx_index; + int phy_addr; +}; + +/* + * struct mii_bus functions + */ +static int ftgmac100_mdiobus_read(struct eth_device *dev, int phy_addr, + int regnum) +{ + struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; + int phycr; + int i; + + phycr = readl(&ftgmac100->phycr); + + /* preserve MDC cycle threshold */ + phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK; + + phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) + | FTGMAC100_PHYCR_REGAD(regnum) + | FTGMAC100_PHYCR_MIIRD; + + writel(phycr, &ftgmac100->phycr); + + for (i = 0; i < 10; i++) { + phycr = readl(&ftgmac100->phycr); + + if ((phycr & FTGMAC100_PHYCR_MIIRD) == 0) { + int data; + + data = readl(&ftgmac100->phydata); + return FTGMAC100_PHYDATA_MIIRDATA(data); + } + + mdelay(10); + } + + debug("mdio read timed out\n"); + return -1; +} + +static int ftgmac100_mdiobus_write(struct eth_device *dev, int phy_addr, + int regnum, u16 value) +{ + struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; + int phycr; + int data; + int i; + + phycr = readl(&ftgmac100->phycr); + + /* preserve MDC cycle threshold */ + phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK; + + phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) + | FTGMAC100_PHYCR_REGAD(regnum) + | FTGMAC100_PHYCR_MIIWR; + + data = FTGMAC100_PHYDATA_MIIWDATA(value); + + writel(data, &ftgmac100->phydata); + writel(phycr, &ftgmac100->phycr); + + for (i = 0; i < 10; i++) { + phycr = readl(&ftgmac100->phycr); + + if ((phycr & FTGMAC100_PHYCR_MIIWR) == 0) { + debug("(phycr & FTGMAC100_PHYCR_MIIWR) == 0: " \ + "phy_addr: %x\n", phy_addr); + return 0; + } + + mdelay(1); + } + + debug("mdio write timed out\n"); + return -1; +} + +int ftgmac100_phy_read(struct eth_device *dev, int addr, int reg, u16 *value) +{ + *value = ftgmac100_mdiobus_read(dev , addr, reg); + + if (*value == -1) + return -1; + + return 0; +} + +int ftgmac100_phy_write(struct eth_device *dev, int addr, int reg, u16 value) +{ + if (ftgmac100_mdiobus_write(dev, addr, reg, value) == -1) + return -1; + + return 0; +} + +static int ftgmac100_phy_reset(struct eth_device *dev) +{ + struct ftgmac100_data *priv = dev->priv; + int i; + u16 status, adv; + + adv = ADVERTISE_CSMA | ADVERTISE_ALL; + + ftgmac100_phy_write(dev, priv->phy_addr, MII_ADVERTISE, adv); + + printf("%s: Starting autonegotiation...\n", dev->name); + + ftgmac100_phy_write(dev, priv->phy_addr, + MII_BMCR, (BMCR_ANENABLE | BMCR_ANRESTART)); + + for (i = 0; i < 100000 / 100; i++) { + ftgmac100_phy_read(dev, priv->phy_addr, MII_BMSR, &status); + + if (status & BMSR_ANEGCOMPLETE) + break; + mdelay(1); + } + + if (status & BMSR_ANEGCOMPLETE) { + printf("%s: Autonegotiation complete\n", dev->name); + } else { + printf("%s: Autonegotiation timed out (status=0x%04x)\n", + dev->name, status); + return 0; + } + + return 1; +} + +static int ftgmac100_phy_init(struct eth_device *dev) +{ + struct ftgmac100_data *priv = dev->priv; + + int phy_addr; + u16 phy_id, status, adv, lpa, stat_ge; + int media, speed, duplex; + int i; + + /* Check if the PHY is up to snuff... */ + for (phy_addr = 0; phy_addr < CONFIG_PHY_MAX_ADDR; phy_addr++) { + + ftgmac100_phy_read(dev, phy_addr, MII_PHYSID1, &phy_id); + + /* + * When it is unable to found PHY, + * the interface usually return 0xffff or 0x0000 + */ + if (phy_id != 0xffff && phy_id != 0x0) { + printf("%s: found PHY at 0x%02x\n", + dev->name, phy_addr); + priv->phy_addr = phy_addr; + break; + } + } + + if (phy_id == 0xffff || phy_id == 0x0) { + printf("%s: no PHY present\n", dev->name); + return 0; + } + + ftgmac100_phy_read(dev, priv->phy_addr, MII_BMSR, &status); + + if (!(status & BMSR_LSTATUS)) { + /* Try to re-negotiate if we don't have link already. */ + ftgmac100_phy_reset(dev); + + for (i = 0; i < 100000 / 100; i++) { + ftgmac100_phy_read(dev, priv->phy_addr, + MII_BMSR, &status); + if (status & BMSR_LSTATUS) + break; + udelay(100); + } + } + + if (!(status & BMSR_LSTATUS)) { + printf("%s: link down\n", dev->name); + return 0; + } + +#ifdef CONFIG_FTGMAC100_EGIGA + /* 1000 Base-T Status Register */ + ftgmac100_phy_read(dev, priv->phy_addr, + MII_STAT1000, &stat_ge); + + speed = (stat_ge & (LPA_1000FULL | LPA_1000HALF) + ? 1 : 0); + + duplex = ((stat_ge & LPA_1000FULL) + ? 1 : 0); + + if (speed) { /* Speed is 1000 */ + printf("%s: link up, 1000bps %s-duplex\n", + dev->name, duplex ? "full" : "half"); + return 0; + } +#endif + + ftgmac100_phy_read(dev, priv->phy_addr, MII_ADVERTISE, &adv); + ftgmac100_phy_read(dev, priv->phy_addr, MII_LPA, &lpa); + + media = mii_nway_result(lpa & adv); + speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) ? 1 : 0); + duplex = (media & ADVERTISE_FULL) ? 1 : 0; + + printf("%s: link up, %sMbps %s-duplex\n", + dev->name, speed ? "100" : "10", duplex ? "full" : "half"); + + return 1; +} + +static int ftgmac100_update_link_speed(struct eth_device *dev) +{ + struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; + struct ftgmac100_data *priv = dev->priv; + + unsigned short stat_fe; + unsigned short stat_ge; + unsigned int maccr; + +#ifdef CONFIG_FTGMAC100_EGIGA + /* 1000 Base-T Status Register */ + ftgmac100_phy_read(dev, priv->phy_addr, MII_STAT1000, &stat_ge); +#endif + + ftgmac100_phy_read(dev, priv->phy_addr, MII_BMSR, &stat_fe); + + if (!(stat_fe & BMSR_LSTATUS)) /* link status up? */ + return 0; + + /* read MAC control register and clear related bits */ + maccr = readl(&ftgmac100->maccr) & + ~(FTGMAC100_MACCR_GIGA_MODE | + FTGMAC100_MACCR_FAST_MODE | + FTGMAC100_MACCR_FULLDUP); + +#ifdef CONFIG_FTGMAC100_EGIGA + if (stat_ge & LPA_1000FULL) { + /* set gmac for 1000BaseTX and Full Duplex */ + maccr |= FTGMAC100_MACCR_GIGA_MODE | FTGMAC100_MACCR_FULLDUP; + } + + if (stat_ge & LPA_1000HALF) { + /* set gmac for 1000BaseTX and Half Duplex */ + maccr |= FTGMAC100_MACCR_GIGA_MODE; + } +#endif + + if (stat_fe & BMSR_100FULL) { + /* set MII for 100BaseTX and Full Duplex */ + maccr |= FTGMAC100_MACCR_FAST_MODE | FTGMAC100_MACCR_FULLDUP; + } + + if (stat_fe & BMSR_10FULL) { + /* set MII for 10BaseT and Full Duplex */ + maccr |= FTGMAC100_MACCR_FULLDUP; + } + + if (stat_fe & BMSR_100HALF) { + /* set MII for 100BaseTX and Half Duplex */ + maccr |= FTGMAC100_MACCR_FAST_MODE; + } + + if (stat_fe & BMSR_10HALF) { + /* set MII for 10BaseT and Half Duplex */ + /* we have already clear these bits, do nothing */ + ; + } + + /* update MII config into maccr */ + writel(maccr, &ftgmac100->maccr); + + return 1; +} + +/* + * Reset MAC + */ +static void ftgmac100_reset(struct eth_device *dev) +{ + struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; + + debug("%s()\n", __func__); + + writel(FTGMAC100_MACCR_SW_RST, &ftgmac100->maccr); + + while (readl(&ftgmac100->maccr) & FTGMAC100_MACCR_SW_RST) + ; +} + +/* + * Set MAC address + */ +static void ftgmac100_set_mac(struct eth_device *dev, + const unsigned char *mac) +{ + struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; + unsigned int maddr = mac[0] << 8 | mac[1]; + unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5]; + + debug("%s(%x %x)\n", __func__, maddr, laddr); + + writel(maddr, &ftgmac100->mac_madr); + writel(laddr, &ftgmac100->mac_ladr); +} + +static void ftgmac100_set_mac_from_env(struct eth_device *dev) +{ + eth_getenv_enetaddr("ethaddr", dev->enetaddr); + + ftgmac100_set_mac(dev, dev->enetaddr); +} + +/* + * disable transmitter, receiver + */ +static void ftgmac100_halt(struct eth_device *dev) +{ + struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; + + debug("%s()\n", __func__); + + writel(0, &ftgmac100->maccr); +} + +static int ftgmac100_init(struct eth_device *dev, bd_t *bd) +{ + struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; + struct ftgmac100_data *priv = dev->priv; + struct ftgmac100_txdes *txdes; + struct ftgmac100_rxdes *rxdes; + unsigned int maccr; + void *buf; + int i; + + debug("%s()\n", __func__); + + if (!priv->txdes) { + txdes = dma_alloc_coherent( + sizeof(*txdes) * PKTBUFSTX, &priv->txdes_dma); + if (!txdes) + panic("ftgmac100: out of memory\n"); + memset(txdes, 0, sizeof(*txdes) * PKTBUFSTX); + priv->txdes = txdes; + } + txdes = priv->txdes; + + if (!priv->rxdes) { + rxdes = dma_alloc_coherent( + sizeof(*rxdes) * PKTBUFSRX, &priv->rxdes_dma); + if (!rxdes) + panic("ftgmac100: out of memory\n"); + memset(rxdes, 0, sizeof(*rxdes) * PKTBUFSRX); + priv->rxdes = rxdes; + } + rxdes = priv->rxdes; + + /* set the ethernet address */ + ftgmac100_set_mac_from_env(dev); + + /* disable all interrupts */ + writel(0, &ftgmac100->ier); + + /* initialize descriptors */ + priv->tx_index = 0; + priv->rx_index = 0; + + txdes[PKTBUFSTX - 1].txdes0 = FTGMAC100_TXDES0_EDOTR; + rxdes[PKTBUFSRX - 1].rxdes0 = FTGMAC100_RXDES0_EDORR; + + for (i = 0; i < PKTBUFSTX; i++) { + /* TXBUF_BADR */ + if (!txdes[i].txdes2) { + buf = memalign(ARCH_DMA_MINALIGN, CFG_XBUF_SIZE); + if (!buf) + panic("ftgmac100: out of memory\n"); + txdes[i].txdes3 = virt_to_phys(buf); + txdes[i].txdes2 = (uint)buf; + } + txdes[i].txdes1 = 0; + } + + for (i = 0; i < PKTBUFSRX; i++) { + /* RXBUF_BADR */ + if (!rxdes[i].rxdes2) { + buf = net_rx_packets[i]; + rxdes[i].rxdes3 = virt_to_phys(buf); + rxdes[i].rxdes2 = (uint)buf; + } + rxdes[i].rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY; + } + + /* transmit ring */ + writel(priv->txdes_dma, &ftgmac100->txr_badr); + + /* receive ring */ + writel(priv->rxdes_dma, &ftgmac100->rxr_badr); + + /* poll receive descriptor automatically */ + writel(FTGMAC100_APTC_RXPOLL_CNT(1), &ftgmac100->aptc); + + /* config receive buffer size register */ + writel(FTGMAC100_RBSR_SIZE(RBSR_DEFAULT_VALUE), &ftgmac100->rbsr); + + /* enable transmitter, receiver */ + maccr = FTGMAC100_MACCR_TXMAC_EN | + FTGMAC100_MACCR_RXMAC_EN | + FTGMAC100_MACCR_TXDMA_EN | + FTGMAC100_MACCR_RXDMA_EN | + FTGMAC100_MACCR_CRC_APD | + FTGMAC100_MACCR_FULLDUP | + FTGMAC100_MACCR_RX_RUNT | + FTGMAC100_MACCR_RX_BROADPKT; + + writel(maccr, &ftgmac100->maccr); + + if (!ftgmac100_phy_init(dev)) { + if (!ftgmac100_update_link_speed(dev)) + return -1; + } + + return 0; +} + +/* + * Get a data block via Ethernet + */ +static int ftgmac100_recv(struct eth_device *dev) +{ + struct ftgmac100_data *priv = dev->priv; + struct ftgmac100_rxdes *curr_des; + unsigned short rxlen; + + curr_des = &priv->rxdes[priv->rx_index]; + + if (!(curr_des->rxdes0 & FTGMAC100_RXDES0_RXPKT_RDY)) + return -1; + + if (curr_des->rxdes0 & (FTGMAC100_RXDES0_RX_ERR | + FTGMAC100_RXDES0_CRC_ERR | + FTGMAC100_RXDES0_FTL | + FTGMAC100_RXDES0_RUNT | + FTGMAC100_RXDES0_RX_ODD_NB)) { + return -1; + } + + rxlen = FTGMAC100_RXDES0_VDBC(curr_des->rxdes0); + + debug("%s(): RX buffer %d, %x received\n", + __func__, priv->rx_index, rxlen); + + /* invalidate d-cache */ + dma_map_single((void *)curr_des->rxdes2, rxlen, DMA_FROM_DEVICE); + + /* pass the packet up to the protocol layers. */ + net_process_received_packet((void *)curr_des->rxdes2, rxlen); + + /* release buffer to DMA */ + curr_des->rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY; + + priv->rx_index = (priv->rx_index + 1) % PKTBUFSRX; + + return 0; +} + +/* + * Send a data block via Ethernet + */ +static int ftgmac100_send(struct eth_device *dev, void *packet, int length) +{ + struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; + struct ftgmac100_data *priv = dev->priv; + struct ftgmac100_txdes *curr_des = &priv->txdes[priv->tx_index]; + + if (curr_des->txdes0 & FTGMAC100_TXDES0_TXDMA_OWN) { + debug("%s(): no TX descriptor available\n", __func__); + return -1; + } + + debug("%s(%x, %x)\n", __func__, (int)packet, length); + + length = (length < ETH_ZLEN) ? ETH_ZLEN : length; + + memcpy((void *)curr_des->txdes2, (void *)packet, length); + dma_map_single((void *)curr_des->txdes2, length, DMA_TO_DEVICE); + + /* only one descriptor on TXBUF */ + curr_des->txdes0 &= FTGMAC100_TXDES0_EDOTR; + curr_des->txdes0 |= FTGMAC100_TXDES0_FTS | + FTGMAC100_TXDES0_LTS | + FTGMAC100_TXDES0_TXBUF_SIZE(length) | + FTGMAC100_TXDES0_TXDMA_OWN ; + + /* start transmit */ + writel(1, &ftgmac100->txpd); + + debug("%s(): packet sent\n", __func__); + + priv->tx_index = (priv->tx_index + 1) % PKTBUFSTX; + + return 0; +} + +int ftgmac100_initialize(bd_t *bd) +{ + struct eth_device *dev; + struct ftgmac100_data *priv; + + dev = malloc(sizeof *dev); + if (!dev) { + printf("%s(): failed to allocate dev\n", __func__); + goto out; + } + + /* Transmit and receive descriptors should align to 16 bytes */ + priv = memalign(16, sizeof(struct ftgmac100_data)); + if (!priv) { + printf("%s(): failed to allocate priv\n", __func__); + goto free_dev; + } + + memset(dev, 0, sizeof(*dev)); + memset(priv, 0, sizeof(*priv)); + + sprintf(dev->name, "FTGMAC100"); + dev->iobase = CONFIG_FTGMAC100_BASE; + dev->init = ftgmac100_init; + dev->halt = ftgmac100_halt; + dev->send = ftgmac100_send; + dev->recv = ftgmac100_recv; + dev->priv = priv; + + eth_register(dev); + + ftgmac100_reset(dev); + + return 1; + +free_dev: + free(dev); +out: + return 0; +} diff --git a/sources/uboot-be550/drivers/net/ftgmac100.h b/sources/uboot-be550/drivers/net/ftgmac100.h new file mode 100644 index 00000000..71121ba9 --- /dev/null +++ b/sources/uboot-be550/drivers/net/ftgmac100.h @@ -0,0 +1,243 @@ +/* + * Faraday FTGMAC100 Ethernet + * + * (C) Copyright 2010 Faraday Technology + * Po-Yu Chuang + * + * (C) Copyright 2010 Andes Technology + * Macpaul Lin + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FTGMAC100_H +#define __FTGMAC100_H + +/* The registers offset table of ftgmac100 */ +struct ftgmac100 { + unsigned int isr; /* 0x00 */ + unsigned int ier; /* 0x04 */ + unsigned int mac_madr; /* 0x08 */ + unsigned int mac_ladr; /* 0x0c */ + unsigned int maht0; /* 0x10 */ + unsigned int maht1; /* 0x14 */ + unsigned int txpd; /* 0x18 */ + unsigned int rxpd; /* 0x1c */ + unsigned int txr_badr; /* 0x20 */ + unsigned int rxr_badr; /* 0x24 */ + unsigned int hptxpd; /* 0x28 */ + unsigned int hptxpd_badr; /* 0x2c */ + unsigned int itc; /* 0x30 */ + unsigned int aptc; /* 0x34 */ + unsigned int dblac; /* 0x38 */ + unsigned int dmafifos; /* 0x3c */ + unsigned int revr; /* 0x40 */ + unsigned int fear; /* 0x44 */ + unsigned int tpafcr; /* 0x48 */ + unsigned int rbsr; /* 0x4c */ + unsigned int maccr; /* 0x50 */ + unsigned int macsr; /* 0x54 */ + unsigned int tm; /* 0x58 */ + unsigned int resv1; /* 0x5c */ /* not defined in spec */ + unsigned int phycr; /* 0x60 */ + unsigned int phydata; /* 0x64 */ + unsigned int fcr; /* 0x68 */ + unsigned int bpr; /* 0x6c */ + unsigned int wolcr; /* 0x70 */ + unsigned int wolsr; /* 0x74 */ + unsigned int wfcrc; /* 0x78 */ + unsigned int resv2; /* 0x7c */ /* not defined in spec */ + unsigned int wfbm1; /* 0x80 */ + unsigned int wfbm2; /* 0x84 */ + unsigned int wfbm3; /* 0x88 */ + unsigned int wfbm4; /* 0x8c */ + unsigned int nptxr_ptr; /* 0x90 */ + unsigned int hptxr_ptr; /* 0x94 */ + unsigned int rxr_ptr; /* 0x98 */ + unsigned int resv3; /* 0x9c */ /* not defined in spec */ + unsigned int tx; /* 0xa0 */ + unsigned int tx_mcol_scol; /* 0xa4 */ + unsigned int tx_ecol_fail; /* 0xa8 */ + unsigned int tx_lcol_und; /* 0xac */ + unsigned int rx; /* 0xb0 */ + unsigned int rx_bc; /* 0xb4 */ + unsigned int rx_mc; /* 0xb8 */ + unsigned int rx_pf_aep; /* 0xbc */ + unsigned int rx_runt; /* 0xc0 */ + unsigned int rx_crcer_ftl; /* 0xc4 */ + unsigned int rx_col_lost; /* 0xc8 */ +}; + +/* + * Interrupt status register & interrupt enable register + */ +#define FTGMAC100_INT_RPKT_BUF (1 << 0) +#define FTGMAC100_INT_RPKT_FIFO (1 << 1) +#define FTGMAC100_INT_NO_RXBUF (1 << 2) +#define FTGMAC100_INT_RPKT_LOST (1 << 3) +#define FTGMAC100_INT_XPKT_ETH (1 << 4) +#define FTGMAC100_INT_XPKT_FIFO (1 << 5) +#define FTGMAC100_INT_NO_NPTXBUF (1 << 6) +#define FTGMAC100_INT_XPKT_LOST (1 << 7) +#define FTGMAC100_INT_AHB_ERR (1 << 8) +#define FTGMAC100_INT_PHYSTS_CHG (1 << 9) +#define FTGMAC100_INT_NO_HPTXBUF (1 << 10) + +/* + * Interrupt timer control register + */ +#define FTGMAC100_ITC_RXINT_CNT(x) (((x) & 0xf) << 0) +#define FTGMAC100_ITC_RXINT_THR(x) (((x) & 0x7) << 4) +#define FTGMAC100_ITC_RXINT_TIME_SEL (1 << 7) +#define FTGMAC100_ITC_TXINT_CNT(x) (((x) & 0xf) << 8) +#define FTGMAC100_ITC_TXINT_THR(x) (((x) & 0x7) << 12) +#define FTGMAC100_ITC_TXINT_TIME_SEL (1 << 15) + +/* + * Automatic polling timer control register + */ +#define FTGMAC100_APTC_RXPOLL_CNT(x) (((x) & 0xf) << 0) +#define FTGMAC100_APTC_RXPOLL_TIME_SEL (1 << 4) +#define FTGMAC100_APTC_TXPOLL_CNT(x) (((x) & 0xf) << 8) +#define FTGMAC100_APTC_TXPOLL_TIME_SEL (1 << 12) + +/* + * DMA burst length and arbitration control register + */ +#define FTGMAC100_DBLAC_RXFIFO_LTHR(x) (((x) & 0x7) << 0) +#define FTGMAC100_DBLAC_RXFIFO_HTHR(x) (((x) & 0x7) << 3) +#define FTGMAC100_DBLAC_RX_THR_EN (1 << 6) +#define FTGMAC100_DBLAC_RXBURST_SIZE(x) (((x) & 0x3) << 8) +#define FTGMAC100_DBLAC_TXBURST_SIZE(x) (((x) & 0x3) << 10) +#define FTGMAC100_DBLAC_RXDES_SIZE(x) (((x) & 0xf) << 12) +#define FTGMAC100_DBLAC_TXDES_SIZE(x) (((x) & 0xf) << 16) +#define FTGMAC100_DBLAC_IFG_CNT(x) (((x) & 0x7) << 20) +#define FTGMAC100_DBLAC_IFG_INC (1 << 23) + +/* + * DMA FIFO status register + */ +#define FTGMAC100_DMAFIFOS_RXDMA1_SM(dmafifos) ((dmafifos) & 0xf) +#define FTGMAC100_DMAFIFOS_RXDMA2_SM(dmafifos) (((dmafifos) >> 4) & 0xf) +#define FTGMAC100_DMAFIFOS_RXDMA3_SM(dmafifos) (((dmafifos) >> 8) & 0x7) +#define FTGMAC100_DMAFIFOS_TXDMA1_SM(dmafifos) (((dmafifos) >> 12) & 0xf) +#define FTGMAC100_DMAFIFOS_TXDMA2_SM(dmafifos) (((dmafifos) >> 16) & 0x3) +#define FTGMAC100_DMAFIFOS_TXDMA3_SM(dmafifos) (((dmafifos) >> 18) & 0xf) +#define FTGMAC100_DMAFIFOS_RXFIFO_EMPTY (1 << 26) +#define FTGMAC100_DMAFIFOS_TXFIFO_EMPTY (1 << 27) +#define FTGMAC100_DMAFIFOS_RXDMA_GRANT (1 << 28) +#define FTGMAC100_DMAFIFOS_TXDMA_GRANT (1 << 29) +#define FTGMAC100_DMAFIFOS_RXDMA_REQ (1 << 30) +#define FTGMAC100_DMAFIFOS_TXDMA_REQ (1 << 31) + +/* + * Receive buffer size register + */ +#define FTGMAC100_RBSR_SIZE(x) ((x) & 0x3fff) + +/* + * MAC control register + */ +#define FTGMAC100_MACCR_TXDMA_EN (1 << 0) +#define FTGMAC100_MACCR_RXDMA_EN (1 << 1) +#define FTGMAC100_MACCR_TXMAC_EN (1 << 2) +#define FTGMAC100_MACCR_RXMAC_EN (1 << 3) +#define FTGMAC100_MACCR_RM_VLAN (1 << 4) +#define FTGMAC100_MACCR_HPTXR_EN (1 << 5) +#define FTGMAC100_MACCR_LOOP_EN (1 << 6) +#define FTGMAC100_MACCR_ENRX_IN_HALFTX (1 << 7) +#define FTGMAC100_MACCR_FULLDUP (1 << 8) +#define FTGMAC100_MACCR_GIGA_MODE (1 << 9) +#define FTGMAC100_MACCR_CRC_APD (1 << 10) +#define FTGMAC100_MACCR_RX_RUNT (1 << 12) +#define FTGMAC100_MACCR_JUMBO_LF (1 << 13) +#define FTGMAC100_MACCR_RX_ALL (1 << 14) +#define FTGMAC100_MACCR_HT_MULTI_EN (1 << 15) +#define FTGMAC100_MACCR_RX_MULTIPKT (1 << 16) +#define FTGMAC100_MACCR_RX_BROADPKT (1 << 17) +#define FTGMAC100_MACCR_DISCARD_CRCERR (1 << 18) +#define FTGMAC100_MACCR_FAST_MODE (1 << 19) +#define FTGMAC100_MACCR_SW_RST (1 << 31) + +/* + * PHY control register + */ +#define FTGMAC100_PHYCR_MDC_CYCTHR_MASK 0x3f +#define FTGMAC100_PHYCR_MDC_CYCTHR(x) ((x) & 0x3f) +#define FTGMAC100_PHYCR_PHYAD(x) (((x) & 0x1f) << 16) +#define FTGMAC100_PHYCR_REGAD(x) (((x) & 0x1f) << 21) +#define FTGMAC100_PHYCR_MIIRD (1 << 26) +#define FTGMAC100_PHYCR_MIIWR (1 << 27) + +/* + * PHY data register + */ +#define FTGMAC100_PHYDATA_MIIWDATA(x) ((x) & 0xffff) +#define FTGMAC100_PHYDATA_MIIRDATA(phydata) (((phydata) >> 16) & 0xffff) + +/* + * Transmit descriptor, aligned to 16 bytes + */ +struct ftgmac100_txdes { + unsigned int txdes0; + unsigned int txdes1; + unsigned int txdes2; /* not used by HW */ + unsigned int txdes3; /* TXBUF_BADR */ +} __attribute__ ((aligned(16))); + +#define FTGMAC100_TXDES0_TXBUF_SIZE(x) ((x) & 0x3fff) +#define FTGMAC100_TXDES0_EDOTR (1 << 15) +#define FTGMAC100_TXDES0_CRC_ERR (1 << 19) +#define FTGMAC100_TXDES0_LTS (1 << 28) +#define FTGMAC100_TXDES0_FTS (1 << 29) +#define FTGMAC100_TXDES0_TXDMA_OWN (1 << 31) + +#define FTGMAC100_TXDES1_VLANTAG_CI(x) ((x) & 0xffff) +#define FTGMAC100_TXDES1_INS_VLANTAG (1 << 16) +#define FTGMAC100_TXDES1_TCP_CHKSUM (1 << 17) +#define FTGMAC100_TXDES1_UDP_CHKSUM (1 << 18) +#define FTGMAC100_TXDES1_IP_CHKSUM (1 << 19) +#define FTGMAC100_TXDES1_LLC (1 << 22) +#define FTGMAC100_TXDES1_TX2FIC (1 << 30) +#define FTGMAC100_TXDES1_TXIC (1 << 31) + +/* + * Receive descriptor, aligned to 16 bytes + */ +struct ftgmac100_rxdes { + unsigned int rxdes0; + unsigned int rxdes1; + unsigned int rxdes2; /* not used by HW */ + unsigned int rxdes3; /* RXBUF_BADR */ +} __attribute__ ((aligned(16))); + +#define FTGMAC100_RXDES0_VDBC(x) ((x) & 0x3fff) +#define FTGMAC100_RXDES0_EDORR (1 << 15) +#define FTGMAC100_RXDES0_MULTICAST (1 << 16) +#define FTGMAC100_RXDES0_BROADCAST (1 << 17) +#define FTGMAC100_RXDES0_RX_ERR (1 << 18) +#define FTGMAC100_RXDES0_CRC_ERR (1 << 19) +#define FTGMAC100_RXDES0_FTL (1 << 20) +#define FTGMAC100_RXDES0_RUNT (1 << 21) +#define FTGMAC100_RXDES0_RX_ODD_NB (1 << 22) +#define FTGMAC100_RXDES0_FIFO_FULL (1 << 23) +#define FTGMAC100_RXDES0_PAUSE_OPCODE (1 << 24) +#define FTGMAC100_RXDES0_PAUSE_FRAME (1 << 25) +#define FTGMAC100_RXDES0_LRS (1 << 28) +#define FTGMAC100_RXDES0_FRS (1 << 29) +#define FTGMAC100_RXDES0_RXPKT_RDY (1 << 31) + +#define FTGMAC100_RXDES1_VLANTAG_CI 0xffff +#define FTGMAC100_RXDES1_PROT_MASK (0x3 << 20) +#define FTGMAC100_RXDES1_PROT_NONIP (0x0 << 20) +#define FTGMAC100_RXDES1_PROT_IP (0x1 << 20) +#define FTGMAC100_RXDES1_PROT_TCPIP (0x2 << 20) +#define FTGMAC100_RXDES1_PROT_UDPIP (0x3 << 20) +#define FTGMAC100_RXDES1_LLC (1 << 22) +#define FTGMAC100_RXDES1_DF (1 << 23) +#define FTGMAC100_RXDES1_VLANTAG_AVAIL (1 << 24) +#define FTGMAC100_RXDES1_TCP_CHKSUM_ERR (1 << 25) +#define FTGMAC100_RXDES1_UDP_CHKSUM_ERR (1 << 26) +#define FTGMAC100_RXDES1_IP_CHKSUM_ERR (1 << 27) + +#endif /* __FTGMAC100_H */ diff --git a/sources/uboot-be550/drivers/net/ftmac100.c b/sources/uboot-be550/drivers/net/ftmac100.c new file mode 100644 index 00000000..bd94f83f --- /dev/null +++ b/sources/uboot-be550/drivers/net/ftmac100.c @@ -0,0 +1,265 @@ +/* + * Faraday FTMAC100 Ethernet + * + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +#include "ftmac100.h" + +#define ETH_ZLEN 60 + +struct ftmac100_data { + struct ftmac100_txdes txdes[1]; + struct ftmac100_rxdes rxdes[PKTBUFSRX]; + int rx_index; +}; + +/* + * Reset MAC + */ +static void ftmac100_reset (struct eth_device *dev) +{ + struct ftmac100 *ftmac100 = (struct ftmac100 *)dev->iobase; + + debug ("%s()\n", __func__); + + writel (FTMAC100_MACCR_SW_RST, &ftmac100->maccr); + + while (readl (&ftmac100->maccr) & FTMAC100_MACCR_SW_RST) + ; +} + +/* + * Set MAC address + */ +static void ftmac100_set_mac (struct eth_device *dev, const unsigned char *mac) +{ + struct ftmac100 *ftmac100 = (struct ftmac100 *)dev->iobase; + unsigned int maddr = mac[0] << 8 | mac[1]; + unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5]; + + debug ("%s(%x %x)\n", __func__, maddr, laddr); + + writel (maddr, &ftmac100->mac_madr); + writel (laddr, &ftmac100->mac_ladr); +} + +static void ftmac100_set_mac_from_env (struct eth_device *dev) +{ + eth_getenv_enetaddr ("ethaddr", dev->enetaddr); + + ftmac100_set_mac (dev, dev->enetaddr); +} + +/* + * disable transmitter, receiver + */ +static void ftmac100_halt (struct eth_device *dev) +{ + struct ftmac100 *ftmac100 = (struct ftmac100 *)dev->iobase; + + debug ("%s()\n", __func__); + + writel (0, &ftmac100->maccr); +} + +static int ftmac100_init (struct eth_device *dev, bd_t *bd) +{ + struct ftmac100 *ftmac100 = (struct ftmac100 *)dev->iobase; + struct ftmac100_data *priv = dev->priv; + struct ftmac100_txdes *txdes = priv->txdes; + struct ftmac100_rxdes *rxdes = priv->rxdes; + unsigned int maccr; + int i; + + debug ("%s()\n", __func__); + + ftmac100_reset (dev); + + /* set the ethernet address */ + + ftmac100_set_mac_from_env (dev); + + /* disable all interrupts */ + + writel (0, &ftmac100->imr); + + /* initialize descriptors */ + + priv->rx_index = 0; + + txdes[0].txdes1 = FTMAC100_TXDES1_EDOTR; + rxdes[PKTBUFSRX - 1].rxdes1 = FTMAC100_RXDES1_EDORR; + + for (i = 0; i < PKTBUFSRX; i++) { + /* RXBUF_BADR */ + rxdes[i].rxdes2 = (unsigned int)net_rx_packets[i]; + rxdes[i].rxdes1 |= FTMAC100_RXDES1_RXBUF_SIZE (PKTSIZE_ALIGN); + rxdes[i].rxdes0 = FTMAC100_RXDES0_RXDMA_OWN; + } + + /* transmit ring */ + + writel ((unsigned int)txdes, &ftmac100->txr_badr); + + /* receive ring */ + + writel ((unsigned int)rxdes, &ftmac100->rxr_badr); + + /* poll receive descriptor automatically */ + + writel (FTMAC100_APTC_RXPOLL_CNT (1), &ftmac100->aptc); + + /* enable transmitter, receiver */ + + maccr = FTMAC100_MACCR_XMT_EN | + FTMAC100_MACCR_RCV_EN | + FTMAC100_MACCR_XDMA_EN | + FTMAC100_MACCR_RDMA_EN | + FTMAC100_MACCR_CRC_APD | + FTMAC100_MACCR_ENRX_IN_HALFTX | + FTMAC100_MACCR_RX_RUNT | + FTMAC100_MACCR_RX_BROADPKT; + + writel (maccr, &ftmac100->maccr); + + return 0; +} + +/* + * Get a data block via Ethernet + */ +static int ftmac100_recv (struct eth_device *dev) +{ + struct ftmac100_data *priv = dev->priv; + struct ftmac100_rxdes *curr_des; + unsigned short rxlen; + + curr_des = &priv->rxdes[priv->rx_index]; + + if (curr_des->rxdes0 & FTMAC100_RXDES0_RXDMA_OWN) + return -1; + + if (curr_des->rxdes0 & (FTMAC100_RXDES0_RX_ERR | + FTMAC100_RXDES0_CRC_ERR | + FTMAC100_RXDES0_FTL | + FTMAC100_RXDES0_RUNT | + FTMAC100_RXDES0_RX_ODD_NB)) { + return -1; + } + + rxlen = FTMAC100_RXDES0_RFL (curr_des->rxdes0); + + debug ("%s(): RX buffer %d, %x received\n", + __func__, priv->rx_index, rxlen); + + /* pass the packet up to the protocol layers. */ + + net_process_received_packet((void *)curr_des->rxdes2, rxlen); + + /* release buffer to DMA */ + + curr_des->rxdes0 |= FTMAC100_RXDES0_RXDMA_OWN; + + priv->rx_index = (priv->rx_index + 1) % PKTBUFSRX; + + return 0; +} + +/* + * Send a data block via Ethernet + */ +static int ftmac100_send(struct eth_device *dev, void *packet, int length) +{ + struct ftmac100 *ftmac100 = (struct ftmac100 *)dev->iobase; + struct ftmac100_data *priv = dev->priv; + struct ftmac100_txdes *curr_des = priv->txdes; + ulong start; + + if (curr_des->txdes0 & FTMAC100_TXDES0_TXDMA_OWN) { + debug ("%s(): no TX descriptor available\n", __func__); + return -1; + } + + debug ("%s(%x, %x)\n", __func__, (int)packet, length); + + length = (length < ETH_ZLEN) ? ETH_ZLEN : length; + + /* initiate a transmit sequence */ + + curr_des->txdes2 = (unsigned int)packet; /* TXBUF_BADR */ + + curr_des->txdes1 &= FTMAC100_TXDES1_EDOTR; + curr_des->txdes1 |= FTMAC100_TXDES1_FTS | + FTMAC100_TXDES1_LTS | + FTMAC100_TXDES1_TXBUF_SIZE (length); + + curr_des->txdes0 = FTMAC100_TXDES0_TXDMA_OWN; + + /* start transmit */ + + writel (1, &ftmac100->txpd); + + /* wait for transfer to succeed */ + + start = get_timer(0); + while (curr_des->txdes0 & FTMAC100_TXDES0_TXDMA_OWN) { + if (get_timer(start) >= 5) { + debug ("%s(): timed out\n", __func__); + return -1; + } + } + + debug ("%s(): packet sent\n", __func__); + + return 0; +} + +int ftmac100_initialize (bd_t *bd) +{ + struct eth_device *dev; + struct ftmac100_data *priv; + + dev = malloc (sizeof *dev); + if (!dev) { + printf ("%s(): failed to allocate dev\n", __func__); + goto out; + } + + /* Transmit and receive descriptors should align to 16 bytes */ + + priv = memalign (16, sizeof (struct ftmac100_data)); + if (!priv) { + printf ("%s(): failed to allocate priv\n", __func__); + goto free_dev; + } + + memset (dev, 0, sizeof (*dev)); + memset (priv, 0, sizeof (*priv)); + + sprintf (dev->name, "FTMAC100"); + dev->iobase = CONFIG_FTMAC100_BASE; + dev->init = ftmac100_init; + dev->halt = ftmac100_halt; + dev->send = ftmac100_send; + dev->recv = ftmac100_recv; + dev->priv = priv; + + eth_register (dev); + + return 1; + +free_dev: + free (dev); +out: + return 0; +} diff --git a/sources/uboot-be550/drivers/net/ftmac100.h b/sources/uboot-be550/drivers/net/ftmac100.h new file mode 100644 index 00000000..b674d029 --- /dev/null +++ b/sources/uboot-be550/drivers/net/ftmac100.h @@ -0,0 +1,142 @@ +/* + * Faraday FTMAC100 Ethernet + * + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FTMAC100_H +#define __FTMAC100_H + +struct ftmac100 { + unsigned int isr; /* 0x00 */ + unsigned int imr; /* 0x04 */ + unsigned int mac_madr; /* 0x08 */ + unsigned int mac_ladr; /* 0x0c */ + unsigned int maht0; /* 0x10 */ + unsigned int maht1; /* 0x14 */ + unsigned int txpd; /* 0x18 */ + unsigned int rxpd; /* 0x1c */ + unsigned int txr_badr; /* 0x20 */ + unsigned int rxr_badr; /* 0x24 */ + unsigned int itc; /* 0x28 */ + unsigned int aptc; /* 0x2c */ + unsigned int dblac; /* 0x30 */ + unsigned int pad1[3]; /* 0x34 - 0x3c */ + unsigned int pad2[16]; /* 0x40 - 0x7c */ + unsigned int pad3[2]; /* 0x80 - 0x84 */ + unsigned int maccr; /* 0x88 */ + unsigned int macsr; /* 0x8c */ + unsigned int phycr; /* 0x90 */ + unsigned int phywdata; /* 0x94 */ + unsigned int fcr; /* 0x98 */ + unsigned int bpr; /* 0x9c */ + unsigned int pad4[8]; /* 0xa0 - 0xbc */ + unsigned int pad5; /* 0xc0 */ + unsigned int ts; /* 0xc4 */ + unsigned int dmafifos; /* 0xc8 */ + unsigned int tm; /* 0xcc */ + unsigned int pad6; /* 0xd0 */ + unsigned int tx_mcol_scol; /* 0xd4 */ + unsigned int rpf_aep; /* 0xd8 */ + unsigned int xm_pg; /* 0xdc */ + unsigned int runt_tlcc; /* 0xe0 */ + unsigned int crcer_ftl; /* 0xe4 */ + unsigned int rlc_rcc; /* 0xe8 */ + unsigned int broc; /* 0xec */ + unsigned int mulca; /* 0xf0 */ + unsigned int rp; /* 0xf4 */ + unsigned int xp; /* 0xf8 */ +}; + +/* + * Interrupt status register & interrupt mask register + */ +#define FTMAC100_INT_RPKT_FINISH (1 << 0) +#define FTMAC100_INT_NORXBUF (1 << 1) +#define FTMAC100_INT_XPKT_FINISH (1 << 2) +#define FTMAC100_INT_NOTXBUF (1 << 3) +#define FTMAC100_INT_XPKT_OK (1 << 4) +#define FTMAC100_INT_XPKT_LOST (1 << 5) +#define FTMAC100_INT_RPKT_SAV (1 << 6) +#define FTMAC100_INT_RPKT_LOST (1 << 7) +#define FTMAC100_INT_AHB_ERR (1 << 8) +#define FTMAC100_INT_PHYSTS_CHG (1 << 9) + +/* + * Automatic polling timer control register + */ +#define FTMAC100_APTC_RXPOLL_CNT(x) (((x) & 0xf) << 0) +#define FTMAC100_APTC_RXPOLL_TIME_SEL (1 << 4) +#define FTMAC100_APTC_TXPOLL_CNT(x) (((x) & 0xf) << 8) +#define FTMAC100_APTC_TXPOLL_TIME_SEL (1 << 12) + +/* + * MAC control register + */ +#define FTMAC100_MACCR_XDMA_EN (1 << 0) +#define FTMAC100_MACCR_RDMA_EN (1 << 1) +#define FTMAC100_MACCR_SW_RST (1 << 2) +#define FTMAC100_MACCR_LOOP_EN (1 << 3) +#define FTMAC100_MACCR_CRC_DIS (1 << 4) +#define FTMAC100_MACCR_XMT_EN (1 << 5) +#define FTMAC100_MACCR_ENRX_IN_HALFTX (1 << 6) +#define FTMAC100_MACCR_RCV_EN (1 << 8) +#define FTMAC100_MACCR_HT_MULTI_EN (1 << 9) +#define FTMAC100_MACCR_RX_RUNT (1 << 10) +#define FTMAC100_MACCR_RX_FTL (1 << 11) +#define FTMAC100_MACCR_RCV_ALL (1 << 12) +#define FTMAC100_MACCR_CRC_APD (1 << 14) +#define FTMAC100_MACCR_FULLDUP (1 << 15) +#define FTMAC100_MACCR_RX_MULTIPKT (1 << 16) +#define FTMAC100_MACCR_RX_BROADPKT (1 << 17) + +/* + * Transmit descriptor, aligned to 16 bytes + */ +struct ftmac100_txdes { + unsigned int txdes0; + unsigned int txdes1; + unsigned int txdes2; /* TXBUF_BADR */ + unsigned int txdes3; /* not used by HW */ +} __attribute__ ((aligned(16))); + +#define FTMAC100_TXDES0_TXPKT_LATECOL (1 << 0) +#define FTMAC100_TXDES0_TXPKT_EXSCOL (1 << 1) +#define FTMAC100_TXDES0_TXDMA_OWN (1 << 31) + +#define FTMAC100_TXDES1_TXBUF_SIZE(x) ((x) & 0x7ff) +#define FTMAC100_TXDES1_LTS (1 << 27) +#define FTMAC100_TXDES1_FTS (1 << 28) +#define FTMAC100_TXDES1_TX2FIC (1 << 29) +#define FTMAC100_TXDES1_TXIC (1 << 30) +#define FTMAC100_TXDES1_EDOTR (1 << 31) + +/* + * Receive descriptor, aligned to 16 bytes + */ +struct ftmac100_rxdes { + unsigned int rxdes0; + unsigned int rxdes1; + unsigned int rxdes2; /* RXBUF_BADR */ + unsigned int rxdes3; /* not used by HW */ +} __attribute__ ((aligned(16))); + +#define FTMAC100_RXDES0_RFL(des) ((des) & 0x7ff) +#define FTMAC100_RXDES0_MULTICAST (1 << 16) +#define FTMAC100_RXDES0_BROADCAST (1 << 17) +#define FTMAC100_RXDES0_RX_ERR (1 << 18) +#define FTMAC100_RXDES0_CRC_ERR (1 << 19) +#define FTMAC100_RXDES0_FTL (1 << 20) +#define FTMAC100_RXDES0_RUNT (1 << 21) +#define FTMAC100_RXDES0_RX_ODD_NB (1 << 22) +#define FTMAC100_RXDES0_LRS (1 << 28) +#define FTMAC100_RXDES0_FRS (1 << 29) +#define FTMAC100_RXDES0_RXDMA_OWN (1 << 31) + +#define FTMAC100_RXDES1_RXBUF_SIZE(x) ((x) & 0x7ff) +#define FTMAC100_RXDES1_EDORR (1 << 31) + +#endif /* __FTMAC100_H */ diff --git a/sources/uboot-be550/drivers/net/ftmac110.c b/sources/uboot-be550/drivers/net/ftmac110.c new file mode 100644 index 00000000..4f17015b --- /dev/null +++ b/sources/uboot-be550/drivers/net/ftmac110.c @@ -0,0 +1,477 @@ +/* + * Faraday 10/100Mbps Ethernet Controller + * + * (C) Copyright 2013 Faraday Technology + * Dante Su + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) +#include +#endif + +#include "ftmac110.h" + +#define CFG_RXDES_NUM 8 +#define CFG_TXDES_NUM 2 +#define CFG_XBUF_SIZE 1536 + +#define CFG_MDIORD_TIMEOUT (CONFIG_SYS_HZ >> 1) /* 500 ms */ +#define CFG_MDIOWR_TIMEOUT (CONFIG_SYS_HZ >> 1) /* 500 ms */ +#define CFG_LINKUP_TIMEOUT (CONFIG_SYS_HZ << 2) /* 4 sec */ + +/* + * FTMAC110 DMA design issue + * + * Its DMA engine has a weird restriction that its Rx DMA engine + * accepts only 16-bits aligned address, 32-bits aligned is not + * acceptable. However this restriction does not apply to Tx DMA. + * + * Conclusion: + * (1) Tx DMA Buffer Address: + * 1 bytes aligned: Invalid + * 2 bytes aligned: O.K + * 4 bytes aligned: O.K (-> u-boot ZeroCopy is possible) + * (2) Rx DMA Buffer Address: + * 1 bytes aligned: Invalid + * 2 bytes aligned: O.K + * 4 bytes aligned: Invalid + */ + +struct ftmac110_chip { + void __iomem *regs; + uint32_t imr; + uint32_t maccr; + uint32_t lnkup; + uint32_t phy_addr; + + struct ftmac110_desc *rxd; + ulong rxd_dma; + uint32_t rxd_idx; + + struct ftmac110_desc *txd; + ulong txd_dma; + uint32_t txd_idx; +}; + +static int ftmac110_reset(struct eth_device *dev); + +static uint16_t mdio_read(struct eth_device *dev, + uint8_t phyaddr, uint8_t phyreg) +{ + struct ftmac110_chip *chip = dev->priv; + struct ftmac110_regs *regs = chip->regs; + uint32_t tmp, ts; + uint16_t ret = 0xffff; + + tmp = PHYCR_READ + | (phyaddr << PHYCR_ADDR_SHIFT) + | (phyreg << PHYCR_REG_SHIFT); + + writel(tmp, ®s->phycr); + + for (ts = get_timer(0); get_timer(ts) < CFG_MDIORD_TIMEOUT; ) { + tmp = readl(®s->phycr); + if (tmp & PHYCR_READ) + continue; + break; + } + + if (tmp & PHYCR_READ) + printf("ftmac110: mdio read timeout\n"); + else + ret = (uint16_t)(tmp & 0xffff); + + return ret; +} + +static void mdio_write(struct eth_device *dev, + uint8_t phyaddr, uint8_t phyreg, uint16_t phydata) +{ + struct ftmac110_chip *chip = dev->priv; + struct ftmac110_regs *regs = chip->regs; + uint32_t tmp, ts; + + tmp = PHYCR_WRITE + | (phyaddr << PHYCR_ADDR_SHIFT) + | (phyreg << PHYCR_REG_SHIFT); + + writel(phydata, ®s->phydr); + writel(tmp, ®s->phycr); + + for (ts = get_timer(0); get_timer(ts) < CFG_MDIOWR_TIMEOUT; ) { + if (readl(®s->phycr) & PHYCR_WRITE) + continue; + break; + } + + if (readl(®s->phycr) & PHYCR_WRITE) + printf("ftmac110: mdio write timeout\n"); +} + +static uint32_t ftmac110_phyqry(struct eth_device *dev) +{ + ulong ts; + uint32_t maccr; + uint16_t pa, tmp, bmsr, bmcr; + struct ftmac110_chip *chip = dev->priv; + + /* Default = 100Mbps Full */ + maccr = MACCR_100M | MACCR_FD; + + /* 1. find the phy device */ + for (pa = 0; pa < 32; ++pa) { + tmp = mdio_read(dev, pa, MII_PHYSID1); + if (tmp == 0xFFFF || tmp == 0x0000) + continue; + chip->phy_addr = pa; + break; + } + if (pa >= 32) { + puts("ftmac110: phy device not found!\n"); + goto exit; + } + + /* 2. wait until link-up & auto-negotiation complete */ + chip->lnkup = 0; + bmcr = mdio_read(dev, chip->phy_addr, MII_BMCR); + ts = get_timer(0); + do { + bmsr = mdio_read(dev, chip->phy_addr, MII_BMSR); + chip->lnkup = (bmsr & BMSR_LSTATUS) ? 1 : 0; + if (!chip->lnkup) + continue; + if (!(bmcr & BMCR_ANENABLE) || (bmsr & BMSR_ANEGCOMPLETE)) + break; + } while (get_timer(ts) < CFG_LINKUP_TIMEOUT); + if (!chip->lnkup) { + puts("ftmac110: link down\n"); + goto exit; + } + if (!(bmcr & BMCR_ANENABLE)) + puts("ftmac110: auto negotiation disabled\n"); + else if (!(bmsr & BMSR_ANEGCOMPLETE)) + puts("ftmac110: auto negotiation timeout\n"); + + /* 3. derive MACCR */ + if ((bmcr & BMCR_ANENABLE) && (bmsr & BMSR_ANEGCOMPLETE)) { + tmp = mdio_read(dev, chip->phy_addr, MII_ADVERTISE); + tmp &= mdio_read(dev, chip->phy_addr, MII_LPA); + if (tmp & LPA_100FULL) /* 100Mbps full-duplex */ + maccr = MACCR_100M | MACCR_FD; + else if (tmp & LPA_100HALF) /* 100Mbps half-duplex */ + maccr = MACCR_100M; + else if (tmp & LPA_10FULL) /* 10Mbps full-duplex */ + maccr = MACCR_FD; + else if (tmp & LPA_10HALF) /* 10Mbps half-duplex */ + maccr = 0; + } else { + if (bmcr & BMCR_SPEED100) + maccr = MACCR_100M; + else + maccr = 0; + if (bmcr & BMCR_FULLDPLX) + maccr |= MACCR_FD; + } + +exit: + printf("ftmac110: %d Mbps, %s\n", + (maccr & MACCR_100M) ? 100 : 10, + (maccr & MACCR_FD) ? "Full" : "half"); + return maccr; +} + +static int ftmac110_reset(struct eth_device *dev) +{ + uint8_t *a; + uint32_t i, maccr; + struct ftmac110_chip *chip = dev->priv; + struct ftmac110_regs *regs = chip->regs; + + /* 1. MAC reset */ + writel(MACCR_RESET, ®s->maccr); + for (i = get_timer(0); get_timer(i) < 1000; ) { + if (readl(®s->maccr) & MACCR_RESET) + continue; + break; + } + if (readl(®s->maccr) & MACCR_RESET) { + printf("ftmac110: reset failed\n"); + return -ENXIO; + } + + /* 1-1. Init tx ring */ + for (i = 0; i < CFG_TXDES_NUM; ++i) { + /* owned by SW */ + chip->txd[i].ctrl &= cpu_to_le64(FTMAC110_TXD_CLRMASK); + } + chip->txd_idx = 0; + + /* 1-2. Init rx ring */ + for (i = 0; i < CFG_RXDES_NUM; ++i) { + /* owned by HW */ + chip->rxd[i].ctrl &= cpu_to_le64(FTMAC110_RXD_CLRMASK); + chip->rxd[i].ctrl |= cpu_to_le64(FTMAC110_RXD_OWNER); + } + chip->rxd_idx = 0; + + /* 2. PHY status query */ + maccr = ftmac110_phyqry(dev); + + /* 3. Fix up the MACCR value */ + chip->maccr = maccr | MACCR_CRCAPD | MACCR_RXALL | MACCR_RXRUNT + | MACCR_RXEN | MACCR_TXEN | MACCR_RXDMAEN | MACCR_TXDMAEN; + + /* 4. MAC address setup */ + a = dev->enetaddr; + writel(a[1] | (a[0] << 8), ®s->mac[0]); + writel(a[5] | (a[4] << 8) | (a[3] << 16) + | (a[2] << 24), ®s->mac[1]); + + /* 5. MAC registers setup */ + writel(chip->rxd_dma, ®s->rxba); + writel(chip->txd_dma, ®s->txba); + /* interrupt at each tx/rx */ + writel(ITC_DEFAULT, ®s->itc); + /* no tx pool, rx poll = 1 normal cycle */ + writel(APTC_DEFAULT, ®s->aptc); + /* rx threshold = [6/8 fifo, 2/8 fifo] */ + writel(DBLAC_DEFAULT, ®s->dblac); + /* disable & clear all interrupt status */ + chip->imr = 0; + writel(ISR_ALL, ®s->isr); + writel(chip->imr, ®s->imr); + /* enable mac */ + writel(chip->maccr, ®s->maccr); + + return 0; +} + +static int ftmac110_probe(struct eth_device *dev, bd_t *bis) +{ + debug("ftmac110: probe\n"); + + if (ftmac110_reset(dev)) + return -1; + + return 0; +} + +static void ftmac110_halt(struct eth_device *dev) +{ + struct ftmac110_chip *chip = dev->priv; + struct ftmac110_regs *regs = chip->regs; + + writel(0, ®s->imr); + writel(0, ®s->maccr); + + debug("ftmac110: halt\n"); +} + +static int ftmac110_send(struct eth_device *dev, void *pkt, int len) +{ + struct ftmac110_chip *chip = dev->priv; + struct ftmac110_regs *regs = chip->regs; + struct ftmac110_desc *txd; + uint64_t ctrl; + + if (!chip->lnkup) + return 0; + + if (len <= 0 || len > CFG_XBUF_SIZE) { + printf("ftmac110: bad tx pkt len(%d)\n", len); + return 0; + } + + len = max(60, len); + + txd = &chip->txd[chip->txd_idx]; + ctrl = le64_to_cpu(txd->ctrl); + if (ctrl & FTMAC110_TXD_OWNER) { + /* kick-off Tx DMA */ + writel(0xffffffff, ®s->txpd); + printf("ftmac110: out of txd\n"); + return 0; + } + + memcpy(txd->vbuf, (void *)pkt, len); + dma_map_single(txd->vbuf, len, DMA_TO_DEVICE); + + /* clear control bits */ + ctrl &= FTMAC110_TXD_CLRMASK; + /* set len, fts and lts */ + ctrl |= FTMAC110_TXD_LEN(len) | FTMAC110_TXD_FTS | FTMAC110_TXD_LTS; + /* set owner bit */ + ctrl |= FTMAC110_TXD_OWNER; + /* write back to descriptor */ + txd->ctrl = cpu_to_le64(ctrl); + + /* kick-off Tx DMA */ + writel(0xffffffff, ®s->txpd); + + chip->txd_idx = (chip->txd_idx + 1) % CFG_TXDES_NUM; + + return len; +} + +static int ftmac110_recv(struct eth_device *dev) +{ + struct ftmac110_chip *chip = dev->priv; + struct ftmac110_desc *rxd; + uint32_t len, rlen = 0; + uint64_t ctrl; + uint8_t *buf; + + if (!chip->lnkup) + return 0; + + do { + rxd = &chip->rxd[chip->rxd_idx]; + ctrl = le64_to_cpu(rxd->ctrl); + if (ctrl & FTMAC110_RXD_OWNER) + break; + + len = (uint32_t)FTMAC110_RXD_LEN(ctrl); + buf = rxd->vbuf; + + if (ctrl & FTMAC110_RXD_ERRMASK) { + printf("ftmac110: rx error\n"); + } else { + dma_map_single(buf, len, DMA_FROM_DEVICE); + net_process_received_packet(buf, len); + rlen += len; + } + + /* owned by hardware */ + ctrl &= FTMAC110_RXD_CLRMASK; + ctrl |= FTMAC110_RXD_OWNER; + rxd->ctrl |= cpu_to_le64(ctrl); + + chip->rxd_idx = (chip->rxd_idx + 1) % CFG_RXDES_NUM; + } while (0); + + return rlen; +} + +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) + +static int ftmac110_mdio_read( + const char *devname, uint8_t addr, uint8_t reg, uint16_t *value) +{ + int ret = 0; + struct eth_device *dev; + + dev = eth_get_dev_by_name(devname); + if (dev == NULL) { + printf("%s: no such device\n", devname); + ret = -1; + } else { + *value = mdio_read(dev, addr, reg); + } + + return ret; +} + +static int ftmac110_mdio_write( + const char *devname, uint8_t addr, uint8_t reg, uint16_t value) +{ + int ret = 0; + struct eth_device *dev; + + dev = eth_get_dev_by_name(devname); + if (dev == NULL) { + printf("%s: no such device\n", devname); + ret = -1; + } else { + mdio_write(dev, addr, reg, value); + } + + return ret; +} + +#endif /* #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) */ + +int ftmac110_initialize(bd_t *bis) +{ + int i, card_nr = 0; + struct eth_device *dev; + struct ftmac110_chip *chip; + + dev = malloc(sizeof(*dev) + sizeof(*chip)); + if (dev == NULL) { + panic("ftmac110: out of memory 1\n"); + return -1; + } + chip = (struct ftmac110_chip *)(dev + 1); + memset(dev, 0, sizeof(*dev) + sizeof(*chip)); + + sprintf(dev->name, "FTMAC110#%d", card_nr); + + dev->iobase = CONFIG_FTMAC110_BASE; + chip->regs = (void __iomem *)dev->iobase; + dev->priv = chip; + dev->init = ftmac110_probe; + dev->halt = ftmac110_halt; + dev->send = ftmac110_send; + dev->recv = ftmac110_recv; + + /* allocate tx descriptors (it must be 16 bytes aligned) */ + chip->txd = dma_alloc_coherent( + sizeof(struct ftmac110_desc) * CFG_TXDES_NUM, &chip->txd_dma); + if (!chip->txd) + panic("ftmac110: out of memory 3\n"); + memset(chip->txd, 0, + sizeof(struct ftmac110_desc) * CFG_TXDES_NUM); + for (i = 0; i < CFG_TXDES_NUM; ++i) { + void *va = memalign(ARCH_DMA_MINALIGN, CFG_XBUF_SIZE); + + if (!va) + panic("ftmac110: out of memory 4\n"); + chip->txd[i].vbuf = va; + chip->txd[i].pbuf = cpu_to_le32(virt_to_phys(va)); + chip->txd[i].ctrl = 0; /* owned by SW */ + } + chip->txd[i - 1].ctrl |= cpu_to_le64(FTMAC110_TXD_END); + chip->txd_idx = 0; + + /* allocate rx descriptors (it must be 16 bytes aligned) */ + chip->rxd = dma_alloc_coherent( + sizeof(struct ftmac110_desc) * CFG_RXDES_NUM, &chip->rxd_dma); + if (!chip->rxd) + panic("ftmac110: out of memory 4\n"); + memset((void *)chip->rxd, 0, + sizeof(struct ftmac110_desc) * CFG_RXDES_NUM); + for (i = 0; i < CFG_RXDES_NUM; ++i) { + void *va = memalign(ARCH_DMA_MINALIGN, CFG_XBUF_SIZE + 2); + + if (!va) + panic("ftmac110: out of memory 5\n"); + /* it needs to be exactly 2 bytes aligned */ + va = ((uint8_t *)va + 2); + chip->rxd[i].vbuf = va; + chip->rxd[i].pbuf = cpu_to_le32(virt_to_phys(va)); + chip->rxd[i].ctrl = cpu_to_le64(FTMAC110_RXD_OWNER + | FTMAC110_RXD_BUFSZ(CFG_XBUF_SIZE)); + } + chip->rxd[i - 1].ctrl |= cpu_to_le64(FTMAC110_RXD_END); + chip->rxd_idx = 0; + + eth_register(dev); + +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) + miiphy_register(dev->name, ftmac110_mdio_read, ftmac110_mdio_write); +#endif + + card_nr++; + + return card_nr; +} diff --git a/sources/uboot-be550/drivers/net/ftmac110.h b/sources/uboot-be550/drivers/net/ftmac110.h new file mode 100644 index 00000000..2772ae7b --- /dev/null +++ b/sources/uboot-be550/drivers/net/ftmac110.h @@ -0,0 +1,176 @@ +/* + * Faraday 10/100Mbps Ethernet Controller + * + * (C) Copyright 2013 Faraday Technology + * Dante Su + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _FTMAC110_H +#define _FTMAC110_H + +struct ftmac110_regs { + uint32_t isr; /* 0x00: Interrups Status Register */ + uint32_t imr; /* 0x04: Interrupt Mask Register */ + uint32_t mac[2]; /* 0x08: MAC Address */ + uint32_t mht[2]; /* 0x10: Multicast Hash Table Register */ + uint32_t txpd; /* 0x18: Tx Poll Demand Register */ + uint32_t rxpd; /* 0x1c: Rx Poll Demand Register */ + uint32_t txba; /* 0x20: Tx Ring Base Address Register */ + uint32_t rxba; /* 0x24: Rx Ring Base Address Register */ + uint32_t itc; /* 0x28: Interrupt Timer Control Register */ + uint32_t aptc; /* 0x2C: Automatic Polling Timer Control Register */ + uint32_t dblac; /* 0x30: DMA Burst Length&Arbitration Control */ + uint32_t revr; /* 0x34: Revision Register */ + uint32_t fear; /* 0x38: Feature Register */ + uint32_t rsvd[19]; + uint32_t maccr; /* 0x88: MAC Control Register */ + uint32_t macsr; /* 0x8C: MAC Status Register */ + uint32_t phycr; /* 0x90: PHY Control Register */ + uint32_t phydr; /* 0x94: PHY Data Register */ + uint32_t fcr; /* 0x98: Flow Control Register */ + uint32_t bpr; /* 0x9C: Back Pressure Register */ +}; + +/* + * Interrupt status/mask register(ISR/IMR) bits + */ +#define ISR_ALL 0x3ff +#define ISR_PHYSTCHG (1 << 9) /* phy status change */ +#define ISR_AHBERR (1 << 8) /* bus error */ +#define ISR_RXLOST (1 << 7) /* rx lost */ +#define ISR_RXFIFO (1 << 6) /* rx to fifo */ +#define ISR_TXLOST (1 << 5) /* tx lost */ +#define ISR_TXOK (1 << 4) /* tx to ethernet */ +#define ISR_NOTXBUF (1 << 3) /* out of tx buffer */ +#define ISR_TXFIFO (1 << 2) /* tx to fifo */ +#define ISR_NORXBUF (1 << 1) /* out of rx buffer */ +#define ISR_RXOK (1 << 0) /* rx to buffer */ + +/* + * MACCR control bits + */ +#define MACCR_100M (1 << 18) /* 100Mbps mode */ +#define MACCR_RXBCST (1 << 17) /* rx broadcast packet */ +#define MACCR_RXMCST (1 << 16) /* rx multicast packet */ +#define MACCR_FD (1 << 15) /* full duplex */ +#define MACCR_CRCAPD (1 << 14) /* tx crc append */ +#define MACCR_RXALL (1 << 12) /* rx all packets */ +#define MACCR_RXFTL (1 << 11) /* rx packet even it's > 1518 byte */ +#define MACCR_RXRUNT (1 << 10) /* rx packet even it's < 64 byte */ +#define MACCR_RXMCSTHT (1 << 9) /* rx multicast hash table */ +#define MACCR_RXEN (1 << 8) /* rx enable */ +#define MACCR_RXINHDTX (1 << 6) /* rx in half duplex tx */ +#define MACCR_TXEN (1 << 5) /* tx enable */ +#define MACCR_CRCDIS (1 << 4) /* tx packet even it's crc error */ +#define MACCR_LOOPBACK (1 << 3) /* loop-back */ +#define MACCR_RESET (1 << 2) /* reset */ +#define MACCR_RXDMAEN (1 << 1) /* rx dma enable */ +#define MACCR_TXDMAEN (1 << 0) /* tx dma enable */ + +/* + * PHYCR control bits + */ +#define PHYCR_READ (1 << 26) +#define PHYCR_WRITE (1 << 27) +#define PHYCR_REG_SHIFT 21 +#define PHYCR_ADDR_SHIFT 16 + +/* + * ITC control bits + */ + +/* Tx Cycle Length */ +#define ITC_TX_CYCLONG (1 << 15) /* 100Mbps=81.92us; 10Mbps=819.2us */ +#define ITC_TX_CYCNORM (0 << 15) /* 100Mbps=5.12us; 10Mbps=51.2us */ +/* Tx Threshold: Aggregate n interrupts as 1 interrupt */ +#define ITC_TX_THR(n) (((n) & 0x7) << 12) +/* Tx Interrupt Timeout = n * Tx Cycle */ +#define ITC_TX_ITMO(n) (((n) & 0xf) << 8) +/* Rx Cycle Length */ +#define ITC_RX_CYCLONG (1 << 7) /* 100Mbps=81.92us; 10Mbps=819.2us */ +#define ITC_RX_CYCNORM (0 << 7) /* 100Mbps=5.12us; 10Mbps=51.2us */ +/* Rx Threshold: Aggregate n interrupts as 1 interrupt */ +#define ITC_RX_THR(n) (((n) & 0x7) << 4) +/* Rx Interrupt Timeout = n * Rx Cycle */ +#define ITC_RX_ITMO(n) (((n) & 0xf) << 0) + +#define ITC_DEFAULT \ + (ITC_TX_THR(1) | ITC_TX_ITMO(0) | ITC_RX_THR(1) | ITC_RX_ITMO(0)) + +/* + * APTC contrl bits + */ + +/* Tx Cycle Length */ +#define APTC_TX_CYCLONG (1 << 12) /* 100Mbps=81.92us; 10Mbps=819.2us */ +#define APTC_TX_CYCNORM (0 << 12) /* 100Mbps=5.12us; 10Mbps=51.2us */ +/* Tx Poll Timeout = n * Tx Cycle, 0=No auto polling */ +#define APTC_TX_PTMO(n) (((n) & 0xf) << 8) +/* Rx Cycle Length */ +#define APTC_RX_CYCLONG (1 << 4) /* 100Mbps=81.92us; 10Mbps=819.2us */ +#define APTC_RX_CYCNORM (0 << 4) /* 100Mbps=5.12us; 10Mbps=51.2us */ +/* Rx Poll Timeout = n * Rx Cycle, 0=No auto polling */ +#define APTC_RX_PTMO(n) (((n) & 0xf) << 0) + +#define APTC_DEFAULT (APTC_TX_PTMO(0) | APTC_RX_PTMO(1)) + +/* + * DBLAC contrl bits + */ +#define DBLAC_BURST_MAX_ANY (0 << 14) /* un-limited */ +#define DBLAC_BURST_MAX_32X4 (2 << 14) /* max = 32 x 4 bytes */ +#define DBLAC_BURST_MAX_64X4 (3 << 14) /* max = 64 x 4 bytes */ +#define DBLAC_RXTHR_EN (1 << 9) /* enable rx threshold arbitration */ +#define DBLAC_RXTHR_HIGH(n) (((n) & 0x7) << 6) /* upper bound = n/8 fifo */ +#define DBLAC_RXTHR_LOW(n) (((n) & 0x7) << 3) /* lower bound = n/8 fifo */ +#define DBLAC_BURST_CAP16 (1 << 2) /* support burst 16 */ +#define DBLAC_BURST_CAP8 (1 << 1) /* support burst 8 */ +#define DBLAC_BURST_CAP4 (1 << 0) /* support burst 4 */ + +#define DBLAC_DEFAULT \ + (DBLAC_RXTHR_EN | DBLAC_RXTHR_HIGH(6) | DBLAC_RXTHR_LOW(2)) + +/* + * descriptor structure + */ +struct ftmac110_desc { + uint64_t ctrl; + uint32_t pbuf; + void *vbuf; +}; + +#define FTMAC110_RXD_END ((uint64_t)1 << 63) +#define FTMAC110_RXD_BUFSZ(x) (((uint64_t)(x) & 0x7ff) << 32) + +#define FTMAC110_RXD_OWNER ((uint64_t)1 << 31) /* owner: 1=HW, 0=SW */ +#define FTMAC110_RXD_FRS ((uint64_t)1 << 29) /* first pkt desc */ +#define FTMAC110_RXD_LRS ((uint64_t)1 << 28) /* last pkt desc */ +#define FTMAC110_RXD_ODDNB ((uint64_t)1 << 22) /* odd nibble */ +#define FTMAC110_RXD_RUNT ((uint64_t)1 << 21) /* runt pkt */ +#define FTMAC110_RXD_FTL ((uint64_t)1 << 20) /* frame too long */ +#define FTMAC110_RXD_CRC ((uint64_t)1 << 19) /* pkt crc error */ +#define FTMAC110_RXD_ERR ((uint64_t)1 << 18) /* bus error */ +#define FTMAC110_RXD_ERRMASK ((uint64_t)0x1f << 18) +#define FTMAC110_RXD_BCST ((uint64_t)1 << 17) /* Bcst pkt */ +#define FTMAC110_RXD_MCST ((uint64_t)1 << 16) /* Mcst pkt */ +#define FTMAC110_RXD_LEN(x) ((uint64_t)((x) & 0x7ff)) + +#define FTMAC110_RXD_CLRMASK \ + (FTMAC110_RXD_END | FTMAC110_RXD_BUFSZ(0x7ff)) + +#define FTMAC110_TXD_END ((uint64_t)1 << 63) /* end of ring */ +#define FTMAC110_TXD_TXIC ((uint64_t)1 << 62) /* tx done interrupt */ +#define FTMAC110_TXD_TX2FIC ((uint64_t)1 << 61) /* tx fifo interrupt */ +#define FTMAC110_TXD_FTS ((uint64_t)1 << 60) /* first pkt desc */ +#define FTMAC110_TXD_LTS ((uint64_t)1 << 59) /* last pkt desc */ +#define FTMAC110_TXD_LEN(x) ((uint64_t)((x) & 0x7ff) << 32) + +#define FTMAC110_TXD_OWNER ((uint64_t)1 << 31) /* owner: 1=HW, 0=SW */ +#define FTMAC110_TXD_COL ((uint64_t)3) /* collision */ + +#define FTMAC110_TXD_CLRMASK \ + (FTMAC110_TXD_END) + +#endif /* FTMAC110_H */ diff --git a/sources/uboot-be550/drivers/net/greth.c b/sources/uboot-be550/drivers/net/greth.c new file mode 100644 index 00000000..088cb229 --- /dev/null +++ b/sources/uboot-be550/drivers/net/greth.c @@ -0,0 +1,677 @@ +/* Gaisler.com GRETH 10/100/1000 Ethernet MAC driver + * + * Driver use polling mode (no Interrupt) + * + * (C) Copyright 2007 + * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* #define DEBUG */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +/* Default to 3s timeout on autonegotiation */ +#ifndef GRETH_PHY_TIMEOUT_MS +#define GRETH_PHY_TIMEOUT_MS 3000 +#endif + +/* Default to PHY adrress 0 not not specified */ +#ifdef CONFIG_SYS_GRLIB_GRETH_PHYADDR +#define GRETH_PHY_ADR_DEFAULT CONFIG_SYS_GRLIB_GRETH_PHYADDR +#else +#define GRETH_PHY_ADR_DEFAULT 0 +#endif + +/* Let board select which GRETH to use as network interface, set + * this to zero if only one GRETH is available. + */ +#ifndef CONFIG_SYS_GRLIB_GRETH_INDEX +#define CONFIG_SYS_GRLIB_GRETH_INDEX 0 +#endif + +/* ByPass Cache when reading regs */ +#define GRETH_REGLOAD(addr) SPARC_NOCACHE_READ(addr) +/* Write-through cache ==> no bypassing needed on writes */ +#define GRETH_REGSAVE(addr,data) (*(volatile unsigned int *)(addr) = (data)) +#define GRETH_REGORIN(addr,data) GRETH_REGSAVE(addr,GRETH_REGLOAD(addr)|data) +#define GRETH_REGANDIN(addr,data) GRETH_REGSAVE(addr,GRETH_REGLOAD(addr)&data) + +#define GRETH_RXBD_CNT 4 +#define GRETH_TXBD_CNT 1 + +#define GRETH_RXBUF_SIZE 1540 +#define GRETH_BUF_ALIGN 4 +#define GRETH_RXBUF_EFF_SIZE \ + ( (GRETH_RXBUF_SIZE&~(GRETH_BUF_ALIGN-1))+GRETH_BUF_ALIGN ) + +typedef struct { + greth_regs *regs; + int irq; + struct eth_device *dev; + + /* Hardware info */ + unsigned char phyaddr; + int gbit_mac; + + /* Current operating Mode */ + int gb; /* GigaBit */ + int fd; /* Full Duplex */ + int sp; /* 10/100Mbps speed (1=100,0=10) */ + int auto_neg; /* Auto negotiate done */ + + unsigned char hwaddr[6]; /* MAC Address */ + + /* Descriptors */ + greth_bd *rxbd_base, *rxbd_max; + greth_bd *txbd_base, *txbd_max; + + greth_bd *rxbd_curr; + + /* rx buffers in rx descriptors */ + void *rxbuf_base; /* (GRETH_RXBUF_SIZE+ALIGNBYTES) * GRETH_RXBD_CNT */ + + /* unused for gbit_mac, temp buffer for sending packets with unligned + * start. + * Pointer to packet allocated with malloc. + */ + void *txbuf; + + struct { + /* rx status */ + unsigned int rx_packets, + rx_crc_errors, rx_frame_errors, rx_length_errors, rx_errors; + + /* tx stats */ + unsigned int tx_packets, + tx_latecol_errors, + tx_underrun_errors, tx_limit_errors, tx_errors; + } stats; +} greth_priv; + +/* Read MII register 'addr' from core 'regs' */ +static int read_mii(int phyaddr, int regaddr, volatile greth_regs * regs) +{ + while (GRETH_REGLOAD(®s->mdio) & GRETH_MII_BUSY) { + } + + GRETH_REGSAVE(®s->mdio, ((phyaddr & 0x1F) << 11) | ((regaddr & 0x1F) << 6) | 2); + + while (GRETH_REGLOAD(®s->mdio) & GRETH_MII_BUSY) { + } + + if (!(GRETH_REGLOAD(®s->mdio) & GRETH_MII_NVALID)) { + return (GRETH_REGLOAD(®s->mdio) >> 16) & 0xFFFF; + } else { + return -1; + } +} + +static void write_mii(int phyaddr, int regaddr, int data, volatile greth_regs * regs) +{ + while (GRETH_REGLOAD(®s->mdio) & GRETH_MII_BUSY) { + } + + GRETH_REGSAVE(®s->mdio, + ((data & 0xFFFF) << 16) | ((phyaddr & 0x1F) << 11) | + ((regaddr & 0x1F) << 6) | 1); + + while (GRETH_REGLOAD(®s->mdio) & GRETH_MII_BUSY) { + } + +} + +/* init/start hardware and allocate descriptor buffers for rx side + * + */ +int greth_init(struct eth_device *dev, bd_t * bis) +{ + int i; + + greth_priv *greth = dev->priv; + greth_regs *regs = greth->regs; + + debug("greth_init\n"); + + /* Reset core */ + GRETH_REGSAVE(®s->control, (GRETH_RESET | (greth->gb << 8) | + (greth->sp << 7) | (greth->fd << 4))); + + /* Wait for Reset to complete */ + while ( GRETH_REGLOAD(®s->control) & GRETH_RESET) ; + + GRETH_REGSAVE(®s->control, + ((greth->gb << 8) | (greth->sp << 7) | (greth->fd << 4))); + + if (!greth->rxbd_base) { + + /* allocate descriptors */ + greth->rxbd_base = (greth_bd *) + memalign(0x1000, GRETH_RXBD_CNT * sizeof(greth_bd)); + greth->txbd_base = (greth_bd *) + memalign(0x1000, GRETH_TXBD_CNT * sizeof(greth_bd)); + + /* allocate buffers to all descriptors */ + greth->rxbuf_base = + malloc(GRETH_RXBUF_EFF_SIZE * GRETH_RXBD_CNT); + } + + /* initate rx decriptors */ + for (i = 0; i < GRETH_RXBD_CNT; i++) { + greth->rxbd_base[i].addr = (unsigned int) + greth->rxbuf_base + (GRETH_RXBUF_EFF_SIZE * i); + /* enable desciptor & set wrap bit if last descriptor */ + if (i >= (GRETH_RXBD_CNT - 1)) { + greth->rxbd_base[i].stat = GRETH_BD_EN | GRETH_BD_WR; + } else { + greth->rxbd_base[i].stat = GRETH_BD_EN; + } + } + + /* initiate indexes */ + greth->rxbd_curr = greth->rxbd_base; + greth->rxbd_max = greth->rxbd_base + (GRETH_RXBD_CNT - 1); + greth->txbd_max = greth->txbd_base + (GRETH_TXBD_CNT - 1); + /* + * greth->txbd_base->addr = 0; + * greth->txbd_base->stat = GRETH_BD_WR; + */ + + /* initate tx decriptors */ + for (i = 0; i < GRETH_TXBD_CNT; i++) { + greth->txbd_base[i].addr = 0; + /* enable desciptor & set wrap bit if last descriptor */ + if (i >= (GRETH_TXBD_CNT - 1)) { + greth->txbd_base[i].stat = GRETH_BD_WR; + } else { + greth->txbd_base[i].stat = 0; + } + } + + /**** SET HARDWARE REGS ****/ + + /* Set pointer to tx/rx descriptor areas */ + GRETH_REGSAVE(®s->rx_desc_p, (unsigned int)&greth->rxbd_base[0]); + GRETH_REGSAVE(®s->tx_desc_p, (unsigned int)&greth->txbd_base[0]); + + /* Enable Transmitter, GRETH will now scan descriptors for packets + * to transmitt */ + debug("greth_init: enabling receiver\n"); + GRETH_REGORIN(®s->control, GRETH_RXEN); + + return 0; +} + +/* Initiate PHY to a relevant speed + * return: + * - 0 = success + * - 1 = timeout/fail + */ +int greth_init_phy(greth_priv * dev, bd_t * bis) +{ + greth_regs *regs = dev->regs; + int tmp, tmp1, tmp2, i; + unsigned int start, timeout; + int phyaddr = GRETH_PHY_ADR_DEFAULT; + +#ifndef CONFIG_SYS_GRLIB_GRETH_PHYADDR + /* If BSP doesn't provide a hardcoded PHY address the driver will + * try to autodetect PHY address by stopping the search on the first + * PHY address which has REG0 implemented. + */ + for (i=0; i<32; i++) { + tmp = read_mii(i, 0, regs); + if ( (tmp != 0) && (tmp != 0xffff) ) { + phyaddr = i; + break; + } + } +#endif + + /* Save PHY Address */ + dev->phyaddr = phyaddr; + + debug("GRETH PHY ADDRESS: %d\n", phyaddr); + + /* X msecs to ticks */ + timeout = GRETH_PHY_TIMEOUT_MS * 1000; + + /* Get system timer0 current value + * Total timeout is 5s + */ + start = get_timer(0); + + /* get phy control register default values */ + + while ((tmp = read_mii(phyaddr, 0, regs)) & 0x8000) { + if (get_timer(start) > timeout) { + debug("greth_init_phy: PHY read 1 failed\n"); + return 1; /* Fail */ + } + } + + /* reset PHY and wait for completion */ + write_mii(phyaddr, 0, 0x8000 | tmp, regs); + + while (((tmp = read_mii(phyaddr, 0, regs))) & 0x8000) { + if (get_timer(start) > timeout) { + debug("greth_init_phy: PHY read 2 failed\n"); + return 1; /* Fail */ + } + } + + /* Check if PHY is autoneg capable and then determine operating + * mode, otherwise force it to 10 Mbit halfduplex + */ + dev->gb = 0; + dev->fd = 0; + dev->sp = 0; + dev->auto_neg = 0; + if (!((tmp >> 12) & 1)) { + write_mii(phyaddr, 0, 0, regs); + } else { + /* wait for auto negotiation to complete and then check operating mode */ + dev->auto_neg = 1; + i = 0; + while (!(((tmp = read_mii(phyaddr, 1, regs)) >> 5) & 1)) { + if (get_timer(start) > timeout) { + printf("Auto negotiation timed out. " + "Selecting default config\n"); + tmp = read_mii(phyaddr, 0, regs); + dev->gb = ((tmp >> 6) & 1) + && !((tmp >> 13) & 1); + dev->sp = !((tmp >> 6) & 1) + && ((tmp >> 13) & 1); + dev->fd = (tmp >> 8) & 1; + goto auto_neg_done; + } + } + if ((tmp >> 8) & 1) { + tmp1 = read_mii(phyaddr, 9, regs); + tmp2 = read_mii(phyaddr, 10, regs); + if ((tmp1 & GRETH_MII_EXTADV_1000FD) && + (tmp2 & GRETH_MII_EXTPRT_1000FD)) { + dev->gb = 1; + dev->fd = 1; + } + if ((tmp1 & GRETH_MII_EXTADV_1000HD) && + (tmp2 & GRETH_MII_EXTPRT_1000HD)) { + dev->gb = 1; + dev->fd = 0; + } + } + if ((dev->gb == 0) || ((dev->gb == 1) && (dev->gbit_mac == 0))) { + tmp1 = read_mii(phyaddr, 4, regs); + tmp2 = read_mii(phyaddr, 5, regs); + if ((tmp1 & GRETH_MII_100TXFD) && + (tmp2 & GRETH_MII_100TXFD)) { + dev->sp = 1; + dev->fd = 1; + } + if ((tmp1 & GRETH_MII_100TXHD) && + (tmp2 & GRETH_MII_100TXHD)) { + dev->sp = 1; + dev->fd = 0; + } + if ((tmp1 & GRETH_MII_10FD) && (tmp2 & GRETH_MII_10FD)) { + dev->fd = 1; + } + if ((dev->gb == 1) && (dev->gbit_mac == 0)) { + dev->gb = 0; + dev->fd = 0; + write_mii(phyaddr, 0, dev->sp << 13, regs); + } + } + + } + auto_neg_done: + debug("%s GRETH Ethermac at [0x%x] irq %d. Running \ + %d Mbps %s duplex\n", dev->gbit_mac ? "10/100/1000" : "10/100", (unsigned int)(regs), (unsigned int)(dev->irq), dev->gb ? 1000 : (dev->sp ? 100 : 10), dev->fd ? "full" : "half"); + /* Read out PHY info if extended registers are available */ + if (tmp & 1) { + tmp1 = read_mii(phyaddr, 2, regs); + tmp2 = read_mii(phyaddr, 3, regs); + tmp1 = (tmp1 << 6) | ((tmp2 >> 10) & 0x3F); + tmp = tmp2 & 0xF; + + tmp2 = (tmp2 >> 4) & 0x3F; + debug("PHY: Vendor %x Device %x Revision %d\n", tmp1, + tmp2, tmp); + } else { + printf("PHY info not available\n"); + } + + /* set speed and duplex bits in control register */ + GRETH_REGORIN(®s->control, + (dev->gb << 8) | (dev->sp << 7) | (dev->fd << 4)); + + return 0; +} + +void greth_halt(struct eth_device *dev) +{ + greth_priv *greth; + greth_regs *regs; + int i; + + debug("greth_halt\n"); + + if (!dev || !dev->priv) + return; + + greth = dev->priv; + regs = greth->regs; + + if (!regs) + return; + + /* disable receiver/transmitter by clearing the enable bits */ + GRETH_REGANDIN(®s->control, ~(GRETH_RXEN | GRETH_TXEN)); + + /* reset rx/tx descriptors */ + if (greth->rxbd_base) { + for (i = 0; i < GRETH_RXBD_CNT; i++) { + greth->rxbd_base[i].stat = + (i >= (GRETH_RXBD_CNT - 1)) ? GRETH_BD_WR : 0; + } + } + + if (greth->txbd_base) { + for (i = 0; i < GRETH_TXBD_CNT; i++) { + greth->txbd_base[i].stat = + (i >= (GRETH_TXBD_CNT - 1)) ? GRETH_BD_WR : 0; + } + } +} + +int greth_send(struct eth_device *dev, void *eth_data, int data_length) +{ + greth_priv *greth = dev->priv; + greth_regs *regs = greth->regs; + greth_bd *txbd; + void *txbuf; + unsigned int status; + + debug("greth_send\n"); + + /* send data, wait for data to be sent, then return */ + if (((unsigned int)eth_data & (GRETH_BUF_ALIGN - 1)) + && !greth->gbit_mac) { + /* data not aligned as needed by GRETH 10/100, solve this by allocating 4 byte aligned buffer + * and copy data to before giving it to GRETH. + */ + if (!greth->txbuf) { + greth->txbuf = malloc(GRETH_RXBUF_SIZE); + } + + txbuf = greth->txbuf; + + /* copy data info buffer */ + memcpy((char *)txbuf, (char *)eth_data, data_length); + + /* keep buffer to next time */ + } else { + txbuf = (void *)eth_data; + } + /* get descriptor to use, only 1 supported... hehe easy */ + txbd = greth->txbd_base; + + /* setup descriptor to wrap around to it self */ + txbd->addr = (unsigned int)txbuf; + txbd->stat = GRETH_BD_EN | GRETH_BD_WR | data_length; + + /* Remind Core which descriptor to use when sending */ + GRETH_REGSAVE(®s->tx_desc_p, (unsigned int)txbd); + + /* initate send by enabling transmitter */ + GRETH_REGORIN(®s->control, GRETH_TXEN); + + /* Wait for data to be sent */ + while ((status = GRETH_REGLOAD(&txbd->stat)) & GRETH_BD_EN) { + ; + } + + /* was the packet transmitted succesfully? */ + if (status & GRETH_TXBD_ERR_AL) { + greth->stats.tx_limit_errors++; + } + + if (status & GRETH_TXBD_ERR_UE) { + greth->stats.tx_underrun_errors++; + } + + if (status & GRETH_TXBD_ERR_LC) { + greth->stats.tx_latecol_errors++; + } + + if (status & + (GRETH_TXBD_ERR_LC | GRETH_TXBD_ERR_UE | GRETH_TXBD_ERR_AL)) { + /* any error */ + greth->stats.tx_errors++; + return -1; + } + + /* bump tx packet counter */ + greth->stats.tx_packets++; + + /* return succefully */ + return 0; +} + +int greth_recv(struct eth_device *dev) +{ + greth_priv *greth = dev->priv; + greth_regs *regs = greth->regs; + greth_bd *rxbd; + unsigned int status, len = 0, bad; + char *d; + int enable = 0; + int i; + + /* Receive One packet only, but clear as many error packets as there are + * available. + */ + { + /* current receive descriptor */ + rxbd = greth->rxbd_curr; + + /* get status of next received packet */ + status = GRETH_REGLOAD(&rxbd->stat); + + bad = 0; + + /* stop if no more packets received */ + if (status & GRETH_BD_EN) { + goto done; + } + + debug("greth_recv: packet 0x%x, 0x%x, len: %d\n", + (unsigned int)rxbd, status, status & GRETH_BD_LEN); + + /* Check status for errors. + */ + if (status & GRETH_RXBD_ERR_FT) { + greth->stats.rx_length_errors++; + bad = 1; + } + if (status & (GRETH_RXBD_ERR_AE | GRETH_RXBD_ERR_OE)) { + greth->stats.rx_frame_errors++; + bad = 1; + } + if (status & GRETH_RXBD_ERR_CRC) { + greth->stats.rx_crc_errors++; + bad = 1; + } + if (bad) { + greth->stats.rx_errors++; + printf + ("greth_recv: Bad packet (%d, %d, %d, 0x%08x, %d)\n", + greth->stats.rx_length_errors, + greth->stats.rx_frame_errors, + greth->stats.rx_crc_errors, status, + greth->stats.rx_packets); + /* print all rx descriptors */ + for (i = 0; i < GRETH_RXBD_CNT; i++) { + printf("[%d]: Stat=0x%lx, Addr=0x%lx\n", i, + GRETH_REGLOAD(&greth->rxbd_base[i].stat), + GRETH_REGLOAD(&greth->rxbd_base[i].addr)); + } + } else { + /* Process the incoming packet. */ + len = status & GRETH_BD_LEN; + d = (char *)rxbd->addr; + + debug + ("greth_recv: new packet, length: %d. data: %x %x %x %x %x %x %x %x\n", + len, d[0], d[1], d[2], d[3], d[4], d[5], d[6], + d[7]); + + /* flush all data cache to make sure we're not reading old packet data */ + sparc_dcache_flush_all(); + + /* pass packet on to network subsystem */ + net_process_received_packet((void *)d, len); + + /* bump stats counters */ + greth->stats.rx_packets++; + + /* bad is now 0 ==> will stop loop */ + } + + /* reenable descriptor to receive more packet with this descriptor, wrap around if needed */ + rxbd->stat = + GRETH_BD_EN | + (((unsigned int)greth->rxbd_curr >= + (unsigned int)greth->rxbd_max) ? GRETH_BD_WR : 0); + enable = 1; + + /* increase index */ + greth->rxbd_curr = + ((unsigned int)greth->rxbd_curr >= + (unsigned int)greth->rxbd_max) ? greth-> + rxbd_base : (greth->rxbd_curr + 1); + + } + + if (enable) { + GRETH_REGORIN(®s->control, GRETH_RXEN); + } + done: + /* return positive length of packet or 0 if non received */ + return len; +} + +void greth_set_hwaddr(greth_priv * greth, unsigned char *mac) +{ + /* save new MAC address */ + greth->dev->enetaddr[0] = greth->hwaddr[0] = mac[0]; + greth->dev->enetaddr[1] = greth->hwaddr[1] = mac[1]; + greth->dev->enetaddr[2] = greth->hwaddr[2] = mac[2]; + greth->dev->enetaddr[3] = greth->hwaddr[3] = mac[3]; + greth->dev->enetaddr[4] = greth->hwaddr[4] = mac[4]; + greth->dev->enetaddr[5] = greth->hwaddr[5] = mac[5]; + greth->regs->esa_msb = (mac[0] << 8) | mac[1]; + greth->regs->esa_lsb = + (mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5]; + + debug("GRETH: New MAC address: %02x:%02x:%02x:%02x:%02x:%02x\n", + mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); +} + +int greth_initialize(bd_t * bis) +{ + greth_priv *greth; + ambapp_apbdev apbdev; + struct eth_device *dev; + int i; + char *addr_str, *end; + unsigned char addr[6]; + + debug("Scanning for GRETH\n"); + + /* Find Device & IRQ via AMBA Plug&Play information, + * CONFIG_SYS_GRLIB_GRETH_INDEX select which GRETH if multiple + * GRETHs in system. + */ + if (ambapp_apb_find(&ambapp_plb, VENDOR_GAISLER, GAISLER_ETHMAC, + CONFIG_SYS_GRLIB_GRETH_INDEX, &apbdev) != 1) { + return -1; /* GRETH not found */ + } + + greth = (greth_priv *) malloc(sizeof(greth_priv)); + dev = (struct eth_device *)malloc(sizeof(struct eth_device)); + memset(dev, 0, sizeof(struct eth_device)); + memset(greth, 0, sizeof(greth_priv)); + + greth->regs = (greth_regs *) apbdev.address; + greth->irq = apbdev.irq; + debug("Found GRETH at %p, irq %d\n", greth->regs, greth->irq); + dev->priv = (void *)greth; + dev->iobase = (unsigned int)greth->regs; + dev->init = greth_init; + dev->halt = greth_halt; + dev->send = greth_send; + dev->recv = greth_recv; + greth->dev = dev; + + /* Reset Core */ + GRETH_REGSAVE(&greth->regs->control, GRETH_RESET); + + /* Wait for core to finish reset cycle */ + while (GRETH_REGLOAD(&greth->regs->control) & GRETH_RESET) ; + + /* Get the phy address which assumed to have been set + correctly with the reset value in hardware */ + greth->phyaddr = (GRETH_REGLOAD(&greth->regs->mdio) >> 11) & 0x1F; + + /* Check if mac is gigabit capable */ + greth->gbit_mac = (GRETH_REGLOAD(&greth->regs->control) >> 27) & 1; + + /* Make descriptor string */ + if (greth->gbit_mac) { + sprintf(dev->name, "GRETH_10/100/GB"); + } else { + sprintf(dev->name, "GRETH_10/100"); + } + + /* initiate PHY, select speed/duplex depending on connected PHY */ + if (greth_init_phy(greth, bis)) { + /* Failed to init PHY (timedout) */ + debug("GRETH[%p]: Failed to init PHY\n", greth->regs); + return -1; + } + + /* Register Device to EtherNet subsystem */ + eth_register(dev); + + /* Get MAC address */ + if ((addr_str = getenv("ethaddr")) != NULL) { + for (i = 0; i < 6; i++) { + addr[i] = + addr_str ? simple_strtoul(addr_str, &end, 16) : 0; + if (addr_str) { + addr_str = (*end) ? end + 1 : end; + } + } + } else { + /* No ethaddr set */ + return -EINVAL; + } + + /* set and remember MAC address */ + greth_set_hwaddr(greth, addr); + + debug("GRETH[%p]: Initialized successfully\n", greth->regs); + return 0; +} diff --git a/sources/uboot-be550/drivers/net/greth.h b/sources/uboot-be550/drivers/net/greth.h new file mode 100644 index 00000000..5299b286 --- /dev/null +++ b/sources/uboot-be550/drivers/net/greth.h @@ -0,0 +1,81 @@ +/* Gaisler.com GRETH 10/100/1000 Ethernet MAC driver + * + * (C) Copyright 2007 + * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#define GRETH_FD 0x10 +#define GRETH_RESET 0x40 +#define GRETH_MII_BUSY 0x8 +#define GRETH_MII_NVALID 0x10 + +/* MII registers */ +#define GRETH_MII_EXTADV_1000FD 0x00000200 +#define GRETH_MII_EXTADV_1000HD 0x00000100 +#define GRETH_MII_EXTPRT_1000FD 0x00000800 +#define GRETH_MII_EXTPRT_1000HD 0x00000400 + +#define GRETH_MII_100T4 0x00000200 +#define GRETH_MII_100TXFD 0x00000100 +#define GRETH_MII_100TXHD 0x00000080 +#define GRETH_MII_10FD 0x00000040 +#define GRETH_MII_10HD 0x00000020 + +#define GRETH_BD_EN 0x800 +#define GRETH_BD_WR 0x1000 +#define GRETH_BD_IE 0x2000 +#define GRETH_BD_LEN 0x7FF + +#define GRETH_TXEN 0x1 +#define GRETH_INT_TX 0x8 +#define GRETH_TXI 0x4 +#define GRETH_TXBD_STATUS 0x0001C000 +#define GRETH_TXBD_MORE 0x20000 +#define GRETH_TXBD_IPCS 0x40000 +#define GRETH_TXBD_TCPCS 0x80000 +#define GRETH_TXBD_UDPCS 0x100000 +#define GRETH_TXBD_ERR_LC 0x10000 +#define GRETH_TXBD_ERR_UE 0x4000 +#define GRETH_TXBD_ERR_AL 0x8000 +#define GRETH_TXBD_NUM 128 +#define GRETH_TXBD_NUM_MASK (GRETH_TXBD_NUM-1) +#define GRETH_TX_BUF_SIZE 2048 + +#define GRETH_INT_RX 0x4 +#define GRETH_RXEN 0x2 +#define GRETH_RXI 0x8 +#define GRETH_RXBD_STATUS 0xFFFFC000 +#define GRETH_RXBD_ERR_AE 0x4000 +#define GRETH_RXBD_ERR_FT 0x8000 +#define GRETH_RXBD_ERR_CRC 0x10000 +#define GRETH_RXBD_ERR_OE 0x20000 +#define GRETH_RXBD_ERR_LE 0x40000 +#define GRETH_RXBD_IP_DEC 0x80000 +#define GRETH_RXBD_IP_CSERR 0x100000 +#define GRETH_RXBD_UDP_DEC 0x200000 +#define GRETH_RXBD_UDP_CSERR 0x400000 +#define GRETH_RXBD_TCP_DEC 0x800000 +#define GRETH_RXBD_TCP_CSERR 0x1000000 + +#define GRETH_RXBD_NUM 128 +#define GRETH_RXBD_NUM_MASK (GRETH_RXBD_NUM-1) +#define GRETH_RX_BUF_SIZE 2048 + +/* Ethernet configuration registers */ +typedef struct _greth_regs { + volatile unsigned int control; + volatile unsigned int status; + volatile unsigned int esa_msb; + volatile unsigned int esa_lsb; + volatile unsigned int mdio; + volatile unsigned int tx_desc_p; + volatile unsigned int rx_desc_p; +} greth_regs; + +/* Ethernet buffer descriptor */ +typedef struct _greth_bd { + volatile unsigned int stat; + unsigned int addr; /* Buffer address not changed by HW */ +} greth_bd; diff --git a/sources/uboot-be550/drivers/net/ipq40xx/ipq40xx_edma_eth.c b/sources/uboot-be550/drivers/net/ipq40xx/ipq40xx_edma_eth.c new file mode 100755 index 00000000..a2219c93 --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq40xx/ipq40xx_edma_eth.c @@ -0,0 +1,1034 @@ +/* + * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. + + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "ipq40xx_edma_eth.h" +#include "ipq40xx.h" +#include "ipq_phy.h" +#include +#ifdef DEBUG +#define debugf(fmt, args...) printf(fmt, ##args); +#else +#define debugf(fmt, args...) +#endif + +static struct ipq40xx_eth_dev *ipq40xx_edma_dev[IPQ40XX_EDMA_DEV]; +static int (*ipq40xx_switch_init)(struct phy_ops **ops); +uchar ipq40xx_def_enetaddr[6] = {0x00, 0x03, 0x7F, 0xBA, 0xDB, 0xAD}; + +void ipq40xx_register_switch(int(*sw_init)(struct phy_ops **ops)) +{ + ipq40xx_switch_init = sw_init; +} + +/* + * Enable RX queue control + */ +static void ipq40xx_edma_enable_rx_ctrl(struct ipq40xx_edma_hw *hw) +{ + volatile u32 data; + + ipq40xx_edma_read_reg(EDMA_REG_RXQ_CTRL, &data); + data |= EDMA_RXQ_CTRL_EN; + ipq40xx_edma_write_reg(EDMA_REG_RXQ_CTRL, data); +} + +/* + * Enable TX queue control + */ +static void ipq40xx_edma_enable_tx_ctrl(struct ipq40xx_edma_hw *hw) +{ + volatile u32 data; + + ipq40xx_edma_read_reg(EDMA_REG_TXQ_CTRL, &data); + data |= EDMA_TXQ_CTRL_TXQ_EN; + ipq40xx_edma_write_reg(EDMA_REG_TXQ_CTRL, data); +} + +/* + * ipq40xx_edma_init_desc() + * Update descriptor ring size, + * Update buffer and producer/consumer index + */ +static void ipq40xx_edma_init_desc( + struct ipq40xx_edma_common_info *c_info, u8 unit) +{ + struct ipq40xx_edma_desc_ring *rfd_ring; + struct ipq40xx_edma_desc_ring *etdr; + volatile u32 data = 0; + u16 hw_cons_idx = 0; + + /* + * Set the base address of every TPD ring. + */ + etdr = c_info->tpd_ring[unit]; + /* + * Update TX descriptor ring base address. + */ + ipq40xx_edma_write_reg(EDMA_REG_TPD_BASE_ADDR_Q(unit), + (u32)(etdr->dma & 0xffffffff)); + ipq40xx_edma_read_reg(EDMA_REG_TPD_IDX_Q(unit), &data); + /* + * Calculate hardware consumer index for Tx. + */ + hw_cons_idx = (data >> EDMA_TPD_CONS_IDX_SHIFT) & 0xffff; + etdr->sw_next_to_fill = hw_cons_idx; + etdr->sw_next_to_clean = hw_cons_idx; + data &= ~(EDMA_TPD_PROD_IDX_MASK << EDMA_TPD_PROD_IDX_SHIFT); + data |= hw_cons_idx; + /* + * Update producer index for Tx. + */ + ipq40xx_edma_write_reg(EDMA_REG_TPD_IDX_Q(unit), data); + /* + * Update SW consumer index register for Tx. + */ + ipq40xx_edma_write_reg(EDMA_REG_TX_SW_CONS_IDX_Q(unit), + hw_cons_idx); + /* + * Set TPD ring size. + */ + ipq40xx_edma_write_reg(EDMA_REG_TPD_RING_SIZE, + (u32)(c_info->tx_ring_count & EDMA_TPD_RING_SIZE_MASK)); + /* + * Configure Rx ring. + */ + rfd_ring = c_info->rfd_ring[unit]; + /* + * Update Receive Free descriptor ring base address. + */ + ipq40xx_edma_write_reg(EDMA_REG_RFD_BASE_ADDR_Q(unit), + (u32)(rfd_ring->dma & 0xffffffff)); + ipq40xx_edma_read_reg(EDMA_REG_RFD_BASE_ADDR_Q(unit), &data); + /* + * Update RFD ring size and RX buffer size. + */ + data = (c_info->rx_ring_count & EDMA_RFD_RING_SIZE_MASK) + << EDMA_RFD_RING_SIZE_SHIFT; + data |= (c_info->rx_buffer_len & EDMA_RX_BUF_SIZE_MASK) + << EDMA_RX_BUF_SIZE_SHIFT; + ipq40xx_edma_write_reg(EDMA_REG_RX_DESC0, data); + /* + * Disable TX FIFO low watermark and high watermark + */ + ipq40xx_edma_write_reg(EDMA_REG_TXF_WATER_MARK, 0); + /* + * Load all of base address above + */ + ipq40xx_edma_read_reg(EDMA_REG_TX_SRAM_PART, &data); + data |= 1 << EDMA_LOAD_PTR_SHIFT; + ipq40xx_edma_write_reg(EDMA_REG_TX_SRAM_PART, data); +} + +/* + * ipq40xx_edma_alloc_rx_buf() + * Allocates buffer for the received packets. + */ +static int ipq40xx_edma_alloc_rx_buf( + struct ipq40xx_edma_common_info *c_info, + struct ipq40xx_edma_desc_ring *erdr, + u32 cleaned_count, u8 queue_id) +{ + struct edma_rx_free_desc *rx_desc; + struct edma_sw_desc *sw_desc; + unsigned int i; + u16 prod_idx, length; + u32 reg_data; + + if (cleaned_count > erdr->count) { + debugf("Incorrect cleaned_count %d", cleaned_count); + return -1; + } + i = erdr->sw_next_to_fill; + + while (cleaned_count--) { + sw_desc = &erdr->sw_desc[i]; + length = c_info->rx_buffer_len; + + sw_desc->dma = virt_to_phys(net_rx_packets[i]); + /* + * Update the buffer info. + */ + sw_desc->data = net_rx_packets[i]; + sw_desc->length = length; + rx_desc = (&((struct edma_rx_free_desc *)(erdr->hw_desc))[i]); + rx_desc->buffer_addr = cpu_to_le64(sw_desc->dma); + + flush_dcache_range((unsigned long)rx_desc, + (unsigned long)rx_desc + + sizeof(struct edma_rx_free_desc)); + if (unlikely(++i == erdr->count)) + i = 0; + } + erdr->sw_next_to_fill = i; + + if (unlikely(i == 0)) + prod_idx = erdr->count - 1; + else + prod_idx = i - 1; + + /* Update the producer index */ + ipq40xx_edma_read_reg(EDMA_REG_RFD_IDX_Q(queue_id), ®_data); + reg_data &= ~EDMA_RFD_PROD_IDX_BITS; + reg_data |= prod_idx; + ipq40xx_edma_write_reg(EDMA_REG_RFD_IDX_Q(queue_id), reg_data); + return 0; +} + +/* + * configure reception control data. + */ +static void ipq40xx_edma_configure_rx( + struct ipq40xx_edma_common_info *c_info) +{ + struct ipq40xx_edma_hw *hw = &c_info->hw; + u32 rss_type, rx_desc1, rxq_ctrl_data; + + /* + * Set RSS type + */ + rss_type = hw->rss_type; + ipq40xx_edma_write_reg(EDMA_REG_RSS_TYPE, rss_type); + /* + * Set RFD burst number + */ + rx_desc1 = (EDMA_RFD_BURST << EDMA_RXQ_RFD_BURST_NUM_SHIFT); + /* + * Set RFD prefetch threshold + */ + rx_desc1 |= (EDMA_RFD_THR << EDMA_RXQ_RFD_PF_THRESH_SHIFT); + /* + * Set RFD in host ring low threshold to generte interrupt + */ + rx_desc1 |= (EDMA_RFD_LTHR << EDMA_RXQ_RFD_LOW_THRESH_SHIFT); + ipq40xx_edma_write_reg(EDMA_REG_RX_DESC1, rx_desc1); + /* + * Set Rx FIFO threshold to start to DMA data to host + */ + rxq_ctrl_data = EDMA_FIFO_THRESH_128_BYTE; + /* + * Set RX remove vlan bit + */ + rxq_ctrl_data |= EDMA_RXQ_CTRL_RMV_VLAN; + ipq40xx_edma_write_reg(EDMA_REG_RXQ_CTRL, rxq_ctrl_data); +} + +/* + * Configure transmission control data + */ +static void ipq40xx_edma_configure_tx( + struct ipq40xx_edma_common_info *c_info) +{ + u32 txq_ctrl_data; + + txq_ctrl_data = (EDMA_TPD_BURST << EDMA_TXQ_NUM_TPD_BURST_SHIFT); + txq_ctrl_data |= + EDMA_TXQ_CTRL_TPD_BURST_EN; + txq_ctrl_data |= + (EDMA_TXF_BURST << EDMA_TXQ_TXF_BURST_NUM_SHIFT); + ipq40xx_edma_write_reg(EDMA_REG_TXQ_CTRL, txq_ctrl_data); +} + +static int ipq40xx_edma_configure( + struct ipq40xx_edma_common_info *c_info) +{ + struct ipq40xx_edma_hw *hw = &c_info->hw; + u32 intr_modrt_data; + u32 intr_ctrl_data = 0; + + ipq40xx_edma_read_reg(EDMA_REG_INTR_CTRL, &intr_ctrl_data); + intr_ctrl_data &= ~(1 << EDMA_INTR_SW_IDX_W_TYP_SHIFT); + intr_ctrl_data |= + hw->intr_sw_idx_w << EDMA_INTR_SW_IDX_W_TYP_SHIFT; + ipq40xx_edma_write_reg(EDMA_REG_INTR_CTRL, intr_ctrl_data); + + /* clear interrupt status */ + ipq40xx_edma_write_reg(EDMA_REG_RX_ISR, 0xff); + ipq40xx_edma_write_reg(EDMA_REG_TX_ISR, 0xffff); + ipq40xx_edma_write_reg(EDMA_REG_MISC_ISR, 0x1fff); + ipq40xx_edma_write_reg(EDMA_REG_WOL_ISR, 0x1); + + /* Clear any WOL status */ + ipq40xx_edma_write_reg(EDMA_REG_WOL_CTRL, 0); + intr_modrt_data = (EDMA_TX_IMT << EDMA_IRQ_MODRT_TX_TIMER_SHIFT); + intr_modrt_data |= (EDMA_RX_IMT << EDMA_IRQ_MODRT_RX_TIMER_SHIFT); + ipq40xx_edma_write_reg(EDMA_REG_IRQ_MODRT_TIMER_INIT, + intr_modrt_data); + + ipq40xx_edma_configure_tx(c_info); + ipq40xx_edma_configure_rx(c_info); + return 0; +} + +static void ipq40xx_edma_stop_rx_tx(struct ipq40xx_edma_hw *hw) +{ + volatile u32 data; + + ipq40xx_edma_read_reg(EDMA_REG_RXQ_CTRL, &data); + data &= ~EDMA_RXQ_CTRL_EN; + ipq40xx_edma_write_reg(EDMA_REG_RXQ_CTRL, data); + ipq40xx_edma_read_reg(EDMA_REG_TXQ_CTRL, &data); + data &= ~EDMA_TXQ_CTRL_TXQ_EN; + ipq40xx_edma_write_reg(EDMA_REG_TXQ_CTRL, data); +} + +static int ipq40xx_edma_reset(struct ipq40xx_edma_common_info *c_info) +{ + struct ipq40xx_edma_hw *hw = &c_info->hw; + int i; + + for (i = 0; i < IPQ40XX_EDMA_DEV; i++) + ipq40xx_edma_write_reg(EDMA_REG_RX_INT_MASK_Q(i), 0); + + for (i = 0; i < IPQ40XX_EDMA_DEV; i++) + ipq40xx_edma_write_reg(EDMA_REG_TX_INT_MASK_Q(i), 0); + + ipq40xx_edma_write_reg(EDMA_REG_MISC_IMR, 0); + ipq40xx_edma_write_reg(EDMA_REG_WOL_IMR, 0); + ipq40xx_edma_write_reg(EDMA_REG_RX_ISR, 0xff); + ipq40xx_edma_write_reg(EDMA_REG_TX_ISR, 0xffff); + ipq40xx_edma_write_reg(EDMA_REG_MISC_ISR, 0x1fff); + ipq40xx_edma_write_reg(EDMA_REG_WOL_ISR, 0x1); + ipq40xx_edma_stop_rx_tx(hw); + return 0; +} + +/* + * ipq40xx_edma_get_tx_buffer() + * Get sw_desc corresponding to the TPD + */ +static struct edma_sw_desc *ipq40xx_edma_get_tx_buffer( + struct ipq40xx_edma_common_info *c_info, + struct edma_tx_desc *tpd, int queue_id) +{ + struct ipq40xx_edma_desc_ring *etdr = + c_info->tpd_ring[queue_id]; + return &etdr->sw_desc[tpd - + (struct edma_tx_desc *)etdr->hw_desc]; +} + +/* + * edma_get_next_tpd() + * Return a TPD descriptor for transfer + */ +static struct edma_tx_desc *ipq40xx_edma_get_next_tpd( + struct ipq40xx_edma_common_info *c_info, + int queue_id) +{ + struct ipq40xx_edma_desc_ring *etdr = + c_info->tpd_ring[queue_id]; + u16 sw_next_to_fill = etdr->sw_next_to_fill; + struct edma_tx_desc *tpd_desc = + (&((struct edma_tx_desc *)(etdr->hw_desc))[sw_next_to_fill]); + etdr->sw_next_to_fill = + (etdr->sw_next_to_fill + 1) % etdr->count; + return tpd_desc; +} + +/* + * ipq40xx_edma_tx_update_hw_idx() + * update the producer index for the ring transmitted + */ +static void ipq40xx_edma_tx_update_hw_idx( + struct ipq40xx_edma_common_info *c_info, + void *skb, int queue_id) +{ + struct ipq40xx_edma_desc_ring *etdr = + c_info->tpd_ring[queue_id]; + volatile u32 tpd_idx_data; + + /* Read and update the producer index */ + ipq40xx_edma_read_reg( + EDMA_REG_TPD_IDX_Q(queue_id), &tpd_idx_data); + tpd_idx_data &= ~EDMA_TPD_PROD_IDX_BITS; + tpd_idx_data |= + ((etdr->sw_next_to_fill & EDMA_TPD_PROD_IDX_MASK) + << EDMA_TPD_PROD_IDX_SHIFT); + ipq40xx_edma_write_reg( + EDMA_REG_TPD_IDX_Q(queue_id), tpd_idx_data); +} + +/* + * ipq40xx_edma_tx_map_and_fill() + * gets called from edma_xmit_frame + * This is where the dma of the buffer to be transmitted + * gets mapped + */ +static int ipq40xx_edma_tx_map_and_fill( + struct ipq40xx_edma_common_info *c_info, + void *skb, int queue_id, + unsigned int flags_transmit, + unsigned int length) +{ + struct edma_sw_desc *sw_desc = NULL; + struct edma_tx_desc *tpd = NULL; + u32 word1 = 0, word3 = 0, lso_word1 = 0, svlan_tag = 0; + u16 buf_len = length; + + if (likely (buf_len)) { + tpd = ipq40xx_edma_get_next_tpd(c_info, queue_id); + sw_desc = ipq40xx_edma_get_tx_buffer(c_info, tpd, queue_id); + sw_desc->dma = virt_to_phys(skb); + + tpd->addr = cpu_to_le32(sw_desc->dma); + tpd->len = cpu_to_le16(buf_len); + + word3 |= EDMA_PORT_ENABLE_ALL << EDMA_TPD_PORT_BITMAP_SHIFT; + + tpd->svlan_tag = svlan_tag; + tpd->word1 = word1 | lso_word1; + tpd->word3 = word3; + + /* The last buffer info contain the skb address, + * so it will be free after unmap + */ + sw_desc->length = buf_len; + sw_desc->flags |= EDMA_SW_DESC_FLAG_SKB_HEAD; + tpd->word1 |= 1 << EDMA_TPD_EOP_SHIFT; + + sw_desc->data = skb; + sw_desc->flags |= EDMA_SW_DESC_FLAG_LAST; + + flush_dcache_range((unsigned long)tpd, + (unsigned long)tpd + + sizeof( struct edma_tx_desc)); + flush_dcache_range((unsigned long)(tpd->addr), + (unsigned long)(tpd->addr) + + PKTSIZE_ALIGN); + } + return 0; +} + +/* + * ipq40xx_edma_tpd_available() + * Check number of free TPDs + */ +static inline u16 ipq40xx_edma_tpd_available( + struct ipq40xx_edma_common_info *c_info, + int queue_id) +{ + struct ipq40xx_edma_desc_ring *etdr = + c_info->tpd_ring[queue_id]; + u16 sw_next_to_fill; + u16 sw_next_to_clean; + u16 count = 0; + + sw_next_to_clean = etdr->sw_next_to_clean; + sw_next_to_fill = etdr->sw_next_to_fill; + + if (likely(sw_next_to_clean <= sw_next_to_fill)) + count = etdr->count; + + return count + sw_next_to_clean - sw_next_to_fill - 1; +} + +static inline void ipq40xx_edma_tx_unmap_and_free( + struct edma_sw_desc *sw_desc) +{ + sw_desc->flags = 0; +} + +/* + * ipq40xx_edma_tx_complete() + * used to clean tx queues and + * update hardware and consumer index + */ +static void ipq40xx_edma_tx_complete( + struct ipq40xx_edma_common_info *c_info, + int queue_id) +{ + struct ipq40xx_edma_desc_ring *etdr = c_info->tpd_ring[queue_id]; + struct edma_sw_desc *sw_desc; + + u16 sw_next_to_clean = etdr->sw_next_to_clean; + u16 hw_next_to_clean = 0; + volatile u32 data = 0; + ipq40xx_edma_read_reg(EDMA_REG_TPD_IDX_Q(queue_id), &data); + hw_next_to_clean = + (data >> EDMA_TPD_CONS_IDX_SHIFT) & EDMA_TPD_CONS_IDX_MASK; + /* clean the buffer here */ + while (sw_next_to_clean != hw_next_to_clean) { + sw_desc = &etdr->sw_desc[sw_next_to_clean]; + ipq40xx_edma_tx_unmap_and_free(sw_desc); + flush_dcache_range((unsigned long)sw_desc, + (unsigned long)sw_desc + + sizeof(struct edma_sw_desc)); + sw_next_to_clean = (sw_next_to_clean + 1) % etdr->count; + etdr->sw_next_to_clean = sw_next_to_clean; + } + /* update the TPD consumer index register */ + ipq40xx_edma_write_reg( + EDMA_REG_TX_SW_CONS_IDX_Q(queue_id), sw_next_to_clean); + +} + +/* + * ipq40xx_edma_rx_complete() + */ +static int ipq40xx_edma_rx_complete( + struct ipq40xx_edma_common_info *c_info, + int queue_id) +{ + u16 cleaned_count = 0; + u16 length = 0; + int i = 0; + u8 rrd[16]; + volatile u32 data = 0; + u16 hw_next_to_clean = 0; + u16 sw_next_to_clean = 0; + struct ipq40xx_edma_desc_ring *erdr = c_info->rfd_ring[queue_id]; + struct edma_sw_desc *sw_desc; + uchar *skb; + int rx = CONFIG_SYS_RX_ETH_BUFFER; + sw_next_to_clean = erdr->sw_next_to_clean; + + invalidate_dcache_range((unsigned long)&erdr->sw_desc[0], + (unsigned long)(&erdr->sw_desc[0] + + sizeof(struct edma_sw_desc) * + CONFIG_SYS_RX_ETH_BUFFER)); + while (rx) { + + sw_desc = &erdr->sw_desc[sw_next_to_clean]; + ipq40xx_edma_read_reg(EDMA_REG_RFD_IDX_Q(queue_id), &data); + hw_next_to_clean = (data >> RFD_CONS_IDX_SHIFT) & + RFD_CONS_IDX_MASK; + + if (hw_next_to_clean == sw_next_to_clean) { + break; + } + + invalidate_dcache_range((unsigned long)sw_desc->data, + (unsigned long)(sw_desc->data + + PKTSIZE_ALIGN)); + + skb = sw_desc->data; + + /* Get RRD */ + for (i = 0; i < 16; i++) + rrd[i] = skb[i]; + + /* use next descriptor */ + sw_next_to_clean = (sw_next_to_clean + 1) % erdr->count; + cleaned_count++; + + /* Check if RRD is valid */ + if (rrd[15] & 0x80) { + /* Get the packet size and allocate buffer */ + length = ((rrd[13] & 0x3f) << 8) + rrd[12]; + /* Get the number of RFD from RRD */ + } + skb = skb + 16; + net_process_received_packet(skb, length); + rx--; + } + erdr->sw_next_to_clean = sw_next_to_clean; + /* alloc_rx_buf */ + if (cleaned_count) { + ipq40xx_edma_alloc_rx_buf(c_info, erdr, + cleaned_count, queue_id); + ipq40xx_edma_write_reg(EDMA_REG_RX_SW_CONS_IDX_Q(queue_id), + erdr->sw_next_to_clean); + } + return 0; +} + +static int ipq40xx_eth_recv(struct eth_device *dev) +{ + struct ipq40xx_eth_dev *priv = dev->priv; + struct ipq40xx_edma_common_info *c_info = priv->c_info; + struct queue_per_cpu_info *q_cinfo = c_info->q_cinfo; + volatile u32 reg_data; + u32 shadow_rx_status; + + ipq40xx_edma_read_reg(EDMA_REG_RX_ISR, ®_data); + q_cinfo->rx_status |= reg_data & q_cinfo->rx_mask; + shadow_rx_status = q_cinfo->rx_status; + + ipq40xx_edma_rx_complete(c_info, priv->mac_unit); + ipq40xx_edma_write_reg(EDMA_REG_RX_ISR, shadow_rx_status); + return 0; +} + +static int ipq40xx_edma_wr_macaddr(struct eth_device *dev) +{ + return 0; +} + +static int ipq40xx_eth_init(struct eth_device *eth_dev, bd_t *this) +{ + struct ipq40xx_eth_dev *priv = eth_dev->priv; + struct ipq40xx_edma_common_info *c_info = priv->c_info; + struct ipq40xx_edma_desc_ring *ring; + struct ipq40xx_edma_hw *hw; + struct phy_ops *phy_get_ops; + static int linkup = 0; + int i; + u8 status; + fal_port_speed_t speed; + fal_port_duplex_t duplex; + char *lstatus[] = {"up", "Down"}; + char *dp[] = {"Half", "Full"}; + hw = &c_info->hw; + /* + * Allocate the RX buffer + * Qid is based on mac unit. + */ + ring = c_info->rfd_ring[priv->mac_unit]; + ipq40xx_edma_alloc_rx_buf(c_info, ring, ring->count, + priv->mac_unit); + if (!priv->ops) { + printf ("Phy ops not mapped\n"); + return -1; + } + phy_get_ops = priv->ops; + if (!phy_get_ops->phy_get_link_status || + !phy_get_ops->phy_get_speed || + !phy_get_ops->phy_get_duplex) { + printf ("Link status/Get speed/Get duplex not mapped\n"); + return -1; + } + /* + * Check PHY link, speed, Duplex on all phys. + * we will proceed even if single link is up + * else we will return with -1; + */ + for (i = 0; i < PHY_MAX; i++) { + status = phy_get_ops->phy_get_link_status(priv->mac_unit, i); + if (status == 0) + linkup++; + phy_get_ops->phy_get_speed(priv->mac_unit, i, &speed); + phy_get_ops->phy_get_duplex(priv->mac_unit, i, &duplex); + switch (speed) { + case FAL_SPEED_10: + case FAL_SPEED_100: + case FAL_SPEED_1000: + printf ("eth%d PHY%d %s Speed :%d %s duplex\n", + priv->mac_unit, i, lstatus[status], speed, + dp[duplex]); + break; + default: + printf("Unknown speed\n"); + break; + } + } + + if (linkup <= 0) { + /* No PHY link is alive */ + return -1; + } else { + /* reset the flag */ + linkup = 0; + } + /* Configure RSS indirection table. + * 128 hash will be configured in the following + * pattern: hash{0,1,2,3} = {Q0,Q2,Q4,Q6} respectively + * and so on + */ + for (i = 0; i < EDMA_NUM_IDT; i++) + ipq40xx_edma_write_reg(EDMA_REG_RSS_IDT(i), EDMA_RSS_IDT_VALUE); + + ipq40xx_edma_enable_tx_ctrl(hw); + ipq40xx_edma_enable_rx_ctrl(hw); + ipq40xx_ess_enable_lookup(); + return 0; +} + +static int ipq40xx_eth_snd(struct eth_device *dev, void *packet, int length) +{ + int num_tpds_needed; + struct ipq40xx_eth_dev *priv = dev->priv; + struct ipq40xx_edma_common_info *c_info = priv->c_info; + struct queue_per_cpu_info *q_cinfo = c_info->q_cinfo; + unsigned int flags_transmit = 0; + u32 shadow_tx_status, reg_data; + + num_tpds_needed = 1; + + if ((num_tpds_needed > + ipq40xx_edma_tpd_available(c_info, priv->mac_unit))) { + debugf("Not enough descriptors available"); + return NETDEV_TX_BUSY; + } + + flags_transmit |= EDMA_HW_CHECKSUM; + ipq40xx_edma_tx_map_and_fill(c_info, + packet, priv->mac_unit, + flags_transmit, length); + + ipq40xx_edma_tx_update_hw_idx(c_info, + packet, priv->mac_unit); + + /* Check for tx dma completion */ + ipq40xx_edma_read_reg(EDMA_REG_TX_ISR, ®_data); + q_cinfo->tx_status |= reg_data & q_cinfo->tx_mask; + shadow_tx_status = q_cinfo->tx_status; + + ipq40xx_edma_tx_complete(c_info, priv->mac_unit); + ipq40xx_edma_write_reg(EDMA_REG_TX_ISR, shadow_tx_status); + return 0; +} + +static void ipq40xx_eth_halt(struct eth_device *dev) +{ + struct ipq40xx_eth_dev *priv = dev->priv; + struct ipq40xx_edma_common_info *c_info = priv->c_info; + + ipq40xx_ess_disable_lookup(); + ipq40xx_edma_reset(c_info); +} + +/* + * Free Tx and Rx rings + */ +static void ipq40xx_edma_free_rings( + struct ipq40xx_edma_common_info *c_info) +{ + int i; + struct ipq40xx_edma_desc_ring *etdr; + struct ipq40xx_edma_desc_ring *rxdr; + + for (i = 0; i < c_info->num_tx_queues; i++) { + if (!c_info->tpd_ring[i]) + continue; + etdr = c_info->tpd_ring[i]; + if (etdr->hw_desc) + ipq40xx_free_mem(etdr->hw_desc); + if (etdr->sw_desc) + ipq40xx_free_mem(etdr->sw_desc); + } + + for (i = 0; i < c_info->num_rx_queues; i++) { + if (!c_info->tpd_ring[i]) + continue; + rxdr = c_info->rfd_ring[i]; + if (rxdr->hw_desc) + ipq40xx_free_mem(rxdr->hw_desc); + if (rxdr->sw_desc) + ipq40xx_free_mem(rxdr->sw_desc); + } +} + +/* + * ipq40xx_edma_alloc_ring() + * allocate edma ring descriptor. + */ +static int ipq40xx_edma_alloc_ring( + struct ipq40xx_edma_common_info *c_info, + struct ipq40xx_edma_desc_ring *erd) +{ + erd->size = (sizeof(struct edma_sw_desc) * erd->count); + erd->sw_next_to_fill = 0; + erd->sw_next_to_clean = 0; + /* Allocate SW descriptors */ + erd->sw_desc = ipq40xx_alloc_memalign(erd->size); + if (!erd->sw_desc) + return -ENOMEM; + + /* Alloc HW descriptors */ + erd->hw_desc = ipq40xx_alloc_memalign(erd->size); + erd->dma = virt_to_phys(erd->hw_desc); + if (!erd->hw_desc) { + ipq40xx_free_mem(erd->sw_desc); + return -ENOMEM; + } + return 0; + +} + +/* + * ipq40xx_allocate_tx_rx_rings() + */ +static int ipq40xx_edma_alloc_tx_rx_rings( + struct ipq40xx_edma_common_info *c_info) +{ + int i, ret; + for (i = 0; i < c_info->num_tx_queues; i++) { + ret = ipq40xx_edma_alloc_ring(c_info, + c_info->tpd_ring[i]); + if (ret) + goto err_ring; + } + + for (i = 0; i < c_info->num_rx_queues; i++) { + ret = ipq40xx_edma_alloc_ring(c_info, + c_info->rfd_ring[i]); + if (ret) + goto err_ring; + } + return 0; +err_ring: + return -1; +} + +/* + * Free Tx and Rx Queues. + */ +static void ipq40xx_edma_free_queues( + struct ipq40xx_edma_common_info *c_info) +{ + int i; + for (i = 0; i < c_info->num_tx_queues; i++) { + if (c_info->tpd_ring[i]) { + ipq40xx_free_mem(c_info->tpd_ring[i]); + c_info->tpd_ring[i] = NULL; + } + } + + for (i = 0; i < c_info->num_rx_queues; i++) { + if (c_info->rfd_ring[i]) { + ipq40xx_free_mem(c_info->rfd_ring[i]); + c_info->rfd_ring[i] = NULL; + } + } + + c_info->num_tx_queues = 0; + c_info->num_rx_queues = 0; +} + +/* + * Allocate Tx and Rx queues. + */ +static int ipq40xx_edma_alloc_tx_rx_queue( + struct ipq40xx_edma_common_info *c_info) +{ + int i; + struct ipq40xx_edma_desc_ring *etdr; + struct ipq40xx_edma_desc_ring *rfd_ring; + /* Tx queue allocation*/ + for (i = 0; i < c_info->num_tx_queues; i++) { + etdr = ipq40xx_alloc_memalign( + sizeof(struct ipq40xx_edma_desc_ring)); + if (!etdr) + goto err; + etdr->count = c_info->tx_ring_count; + c_info->tpd_ring[i] = etdr; + } + /* Rx Queue allocation */ + for (i = 0; i < c_info->num_rx_queues; i++) { + rfd_ring = ipq40xx_alloc_memalign( + sizeof(struct ipq40xx_edma_desc_ring)); + if (!rfd_ring) + goto err; + rfd_ring->count = c_info->rx_ring_count; + rfd_ring->queue_index = i; + c_info->rfd_ring[i] = rfd_ring; + } + return 0; +err: + return -1; +} + +int ipq40xx_edma_init(ipq40xx_edma_board_cfg_t *edma_cfg) +{ + static int ipq40xx_ess_init_done = 0; + static int cfg_edma = 0; + static int sw_init_done = 0; + struct eth_device *dev[IPQ40XX_EDMA_DEV]; + struct ipq40xx_edma_common_info *c_info[IPQ40XX_EDMA_DEV]; + struct ipq40xx_edma_hw *hw[IPQ40XX_EDMA_DEV]; + uchar enet_addr[IPQ40XX_EDMA_DEV * 6]; + int i; + int ret; + + memset(c_info, 0, (sizeof(c_info) * IPQ40XX_EDMA_DEV)); + memset(enet_addr, 0, sizeof(enet_addr)); + /* Getting the MAC address from ART partition */ + ret = get_eth_mac_address(enet_addr, IPQ40XX_EDMA_DEV); + + /* + * Register EDMA as single ethernet + * interface. + */ + for (i = 0; i < IPQ40XX_EDMA_DEV; edma_cfg++, i++) { + dev[i] = ipq40xx_alloc_mem(sizeof(struct eth_device)); + if (!dev[i]) + goto failed; + memset(dev[i], 0, sizeof(struct eth_device)); + + c_info[i] = ipq40xx_alloc_mem( + sizeof(struct ipq40xx_edma_common_info)); + if (!c_info[i]) + goto failed; + memset(c_info[i], 0, + sizeof(struct ipq40xx_edma_common_info)); + + c_info[i]->num_tx_queues = IPQ40XX_EDMA_TX_QUEUE; + c_info[i]->tx_ring_count = IPQ40XX_EDMA_TX_RING_SIZE; + c_info[i]->num_rx_queues = IPQ40XX_EDMA_RX_QUEUE; + c_info[i]->rx_ring_count = IPQ40XX_EDMA_RX_RING_SIZE; + c_info[i]->rx_buffer_len = IPQ40XX_EDMA_RX_BUFF_SIZE; + + hw[i] = &c_info[i]->hw; + + hw[i]->tx_intr_mask = IPQ40XX_EDMA_TX_IMR_NORMAL_MASK; + hw[i]->rx_intr_mask = IPQ40XX_EDMA_RX_IMR_NORMAL_MASK; + hw[i]->rx_buff_size = IPQ40XX_EDMA_RX_BUFF_SIZE; + hw[i]->misc_intr_mask = 0; + hw[i]->wol_intr_mask = 0; + hw[i]->intr_clear_type = IPQ40XX_EDMA_INTR_CLEAR_TYPE; + hw[i]->intr_sw_idx_w = IPQ40XX_EDMA_INTR_SW_IDX_W_TYPE; + hw[i]->rss_type = IPQ40XX_EDMA_RSS_TYPE_NONE; + + c_info[i]->hw.hw_addr = (unsigned long __iomem *) + IPQ40XX_EDMA_CFG_BASE; + + ipq40xx_edma_dev[i] = ipq40xx_alloc_mem( + sizeof(struct ipq40xx_eth_dev)); + if (!ipq40xx_edma_dev[i]) + goto failed; + memset (ipq40xx_edma_dev[i], 0, + sizeof(struct ipq40xx_eth_dev)); + + dev[i]->iobase = edma_cfg->base; + dev[i]->init = ipq40xx_eth_init; + dev[i]->halt = ipq40xx_eth_halt; + dev[i]->recv = ipq40xx_eth_recv; + dev[i]->send = ipq40xx_eth_snd; + dev[i]->write_hwaddr = ipq40xx_edma_wr_macaddr; + dev[i]->priv = (void *)ipq40xx_edma_dev[i]; + + if ((ret < 0) || + (!is_valid_ethaddr(&enet_addr[edma_cfg->unit * 6]))) { + memcpy(&dev[i]->enetaddr[0], ipq40xx_def_enetaddr, 6); + } else { + memcpy(&dev[i]->enetaddr[0], + &enet_addr[edma_cfg->unit * 6], 6); + } + printf("MAC%x addr:%x:%x:%x:%x:%x:%x\n", + edma_cfg->unit, dev[i]->enetaddr[0], + dev[i]->enetaddr[1], + dev[i]->enetaddr[2], + dev[i]->enetaddr[3], + dev[i]->enetaddr[4], + dev[i]->enetaddr[5]); + + snprintf(dev[i]->name, sizeof(dev[i]->name), "eth%d", i); + ipq40xx_edma_dev[i]->dev = dev[i]; + ipq40xx_edma_dev[i]->mac_unit = edma_cfg->unit; + ipq40xx_edma_dev[i]->c_info = c_info[i]; + edma_hw_addr = (unsigned long)c_info[i]->hw.hw_addr; + + ret = ipq40xx_edma_alloc_tx_rx_queue(c_info[i]); + if (ret) + goto failed; + + ret = ipq40xx_edma_alloc_tx_rx_rings(c_info[i]); + if (ret) + goto failed; + + c_info[i]->q_cinfo[i].tx_mask = + (IPQ40XX_EDMA_TX_PER_CPU_MASK << + (i << IPQ40XX_EDMA_TX_PER_CPU_MASK_SHIFT)); + c_info[i]->q_cinfo[i].rx_mask = + (IPQ40XX_EDMA_RX_PER_CPU_MASK << + (i << IPQ40XX_EDMA_RX_PER_CPU_MASK_SHIFT)); + c_info[i]->q_cinfo[i].tx_start = + i << IPQ40XX_EDMA_TX_CPU_START_SHIFT; + c_info[i]->q_cinfo[i].rx_start = + i << IPQ40XX_EDMA_RX_CPU_START_SHIFT; + c_info[i]->q_cinfo[i].tx_status = 0; + c_info[i]->q_cinfo[i].rx_status = 0; + c_info[i]->q_cinfo[i].c_info = c_info[i]; + + ret = ipq_sw_mdio_init(edma_cfg->phy_name); + if (ret) + goto failed; + + switch (edma_cfg->phy) { + case PHY_INTERFACE_MODE_PSGMII: + writel(PSGMIIPHY_PLL_VCO_VAL, + PSGMIIPHY_PLL_VCO_RELATED_CTRL); + writel(PSGMIIPHY_VCO_VAL, + PSGMIIPHY_VCO_CALIBRATION_CTRL); + /* wait for 10ms */ + mdelay(10); + writel(PSGMIIPHY_VCO_RST_VAL, PSGMIIPHY_VCO_CALIBRATION_CTRL); + break; + case PHY_INTERFACE_MODE_RGMII: + writel(0x1, RGMII_TCSR_ESS_CFG); + writel(0x400, ESS_RGMII_CTRL); + break; + default: + printf("unknown MII interface\n"); + goto failed; + } + eth_register(dev[i]); + + if (!sw_init_done) { + if (ipq40xx_switch_init(&ipq40xx_edma_dev[i]->ops) == 0) { + sw_init_done = 1; + } else { + printf ("SW inits failed\n"); + goto failed; + } + } + + if(edma_cfg->phy == PHY_INTERFACE_MODE_PSGMII) { + qca8075_ess_reset(); + mdelay(100); + psgmii_self_test(); + mdelay(300); + clear_self_test_config(); + } + + /* + * Configure EDMA This should + * happen Only once. + */ + if (!cfg_edma) { + ipq40xx_edma_reset(c_info[i]); + ipq40xx_edma_configure(c_info[i]); + cfg_edma = 1; + } + /* + * Configure descriptor Ring based on eth_unit + * 1 Rx/Tx Q is maintained per eth device. + */ + ipq40xx_edma_init_desc(c_info[i], + edma_cfg->unit); + + if (!ipq40xx_ess_init_done) { + ipq40xx_ess_sw_init(edma_cfg); + ipq40xx_ess_disable_lookup(); + ipq40xx_ess_init_done = 1; + } + + } + return 0; + +failed: + printf("Error in allocating Mem\n"); + for (i = 0; i < IPQ40XX_EDMA_DEV; i++) { + if (dev[i]) { + eth_unregister(dev[i]); + ipq40xx_free_mem(dev[i]); + } + if (c_info[i]) { + ipq40xx_edma_free_rings(c_info[i]); + ipq40xx_edma_free_queues(c_info[i]); + ipq40xx_free_mem(c_info[i]); + } + if (ipq40xx_edma_dev[i]) { + ipq40xx_free_mem(ipq40xx_edma_dev[i]); + } + } + return -1; +} diff --git a/sources/uboot-be550/drivers/net/ipq40xx/ipq40xx_edma_eth.h b/sources/uboot-be550/drivers/net/ipq40xx/ipq40xx_edma_eth.h new file mode 100755 index 00000000..be503b93 --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq40xx/ipq40xx_edma_eth.h @@ -0,0 +1,178 @@ +/* + * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. + + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. +*/ + +#ifndef _IPQ40XX_EDMA_ETH_H +#define _IPQ40XX_EDMA_ETH_H +#include +#include +#include +#include +#include + +#define IPQ40XX_EDMA_DEV 1 +#define IPQ40XX_EDMA_TX_QUEUE 1 +#define IPQ40XX_EDMA_RX_QUEUE 1 +#define IPQ40XX_EDMA_TX_RING_SIZE 8 +#define IPQ40XX_EDMA_RX_RING_SIZE 16 +#define IPQ40XX_EDMA_TX_IMR_NORMAL_MASK 1 +#define IPQ40XX_EDMA_RX_IMR_NORMAL_MASK 1 +#define IPQ40XX_EDMA_RX_BUFF_SIZE 1540 +#define IPQ40XX_EDMA_INTR_CLEAR_TYPE 0 +#define IPQ40XX_EDMA_INTR_SW_IDX_W_TYPE 0 +#define IPQ40XX_EDMA_RSS_TYPE_NONE 0x1 + +#define IPQ40XX_EDMA_TX_PER_CPU_MASK 0xF +#define IPQ40XX_EDMA_TX_PER_CPU_MASK_SHIFT 0x2 +#define IPQ40XX_EDMA_RX_PER_CPU_MASK 0x3 +#define IPQ40XX_EDMA_RX_PER_CPU_MASK_SHIFT 0x1 +#define IPQ40XX_EDMA_TX_CPU_START_SHIFT 0x2 +#define IPQ40XX_EDMA_RX_CPU_START_SHIFT 0x1 + +#define PSGMIIPHY_PLL_VCO_RELATED_CTRL 0x0009878c +#define PSGMIIPHY_PLL_VCO_VAL 0x2803 + +#define PSGMIIPHY_VCO_CALIBRATION_CTRL 0x0009809c +#define PSGMIIPHY_VCO_VAL 0x4ADA +#define PSGMIIPHY_VCO_RST_VAL 0xADA + +#define RGMII_TCSR_ESS_CFG 0x01953000 +#define ESS_RGMII_CTRL 0x0C000004 + +/* edma transmit descriptor */ +struct edma_tx_desc { + __le16 len; /* full packet including CRC */ + __le16 svlan_tag; /* vlan tag */ + __le32 word1; /* byte 4-7 */ + __le32 addr; /* address of buffer */ + __le32 word3; /* byte 12 */ +}; + +/* edma receive return descriptor */ +struct edma_rx_return_desc { + __le32 word0; + __le32 word1; + __le32 word2; + __le32 word3; +}; + +/* RFD descriptor */ +struct edma_rx_free_desc { + __le32 buffer_addr; /* buffer address */ +}; + +/* edma_sw_desc stores software descriptor + * SW descriptor has 1:1 map with HW descriptor + */ +struct edma_sw_desc { + uchar *data; + dma_addr_t dma; /* dma address */ + u16 length; /* Tx/Rx buffer length */ + u32 flags; +}; + +/* per core queue related information */ +struct queue_per_cpu_info { + u32 tx_mask; /* tx interrupt mask */ + u32 rx_mask; /* rx interrupt mask */ + u32 tx_status; /* tx interrupt status */ + u32 rx_status; /* rx interrupt status */ + u32 tx_start; /* tx queue start */ + u32 rx_start; /* rx queue start */ + struct ipq40xx_edma_common_info *c_info; /* edma common info */ +}; + +/* edma hw specific data */ +struct ipq40xx_edma_hw { + unsigned long __iomem *hw_addr; /* inner register address */ + struct edma_adapter *adapter; /* netdevice adapter */ + u32 rx_intr_mask; /*rx interrupt mask */ + u32 tx_intr_mask; /* tx interrupt nask */ + u32 misc_intr_mask; /* misc interrupt mask */ + u32 wol_intr_mask; /* wake on lan interrupt mask */ + u8 intr_clear_type; /* interrupt clear */ + u8 intr_sw_idx_w; /* To do chk type interrupt software index */ + u16 rx_buff_size; /* To do chk type Rx buffer size */ + u8 rss_type; /* rss protocol type */ +}; + +/* transimit packet descriptor (tpd) ring */ +struct ipq40xx_edma_desc_ring { + u8 queue_index; /* queue index */ + u16 size; /* descriptor ring length in bytes */ + u16 count; /* number of descriptors in the ring */ + void *hw_desc; /* descriptor ring virtual address */ + dma_addr_t dma; /* descriptor ring physical address */ + u16 sw_next_to_fill; /* next Tx descriptor to fill */ + u16 sw_next_to_clean; /* next Tx descriptor to clean */ + struct edma_sw_desc *sw_desc; /* buffer associated with ring */ +}; + +struct ipq40xx_edma_common_info { + struct ipq40xx_edma_desc_ring *tpd_ring[IPQ40XX_EDMA_TX_QUEUE]; + struct ipq40xx_edma_desc_ring *rfd_ring[IPQ40XX_EDMA_RX_QUEUE]; + int num_rx_queues; /* number of rx queue */ + int num_tx_queues; /* number of tx queue */ + u16 tx_ring_count; + u16 rx_ring_count; + u16 rx_buffer_len; + struct ipq40xx_edma_hw hw; + struct queue_per_cpu_info q_cinfo[IPQ40XX_EDMA_DEV]; +}; + +struct ipq40xx_eth_dev { + u8 *phy_address; + uint no_of_phys; + uint interface; + uint speed; + uint duplex; + uint sw_configured; + uint mac_unit; + uint mac_ps; + int link_printed; + u32 padding; + struct eth_device *dev; + struct ipq40xx_edma_common_info *c_info; + struct phy_ops *ops; + const char phy_name[MDIO_NAME_LEN]; +} __attribute__ ((aligned(8))); + +static int edma_hw_addr; + +static inline void ipq40xx_edma_write_reg(u16 reg_addr, u32 reg_value) +{ + writel(reg_value, ((void __iomem *)(edma_hw_addr + reg_addr))); +} +static inline void ipq40xx_edma_read_reg(u16 reg_addr, volatile u32 *reg_value) +{ + *reg_value = readl((void __iomem *)(edma_hw_addr + reg_addr)); +} + +static inline void* ipq40xx_alloc_mem(u32 size) +{ + return malloc(size); +} + +static inline void* ipq40xx_alloc_memalign(u32 size) +{ + void *p = memalign(CONFIG_SYS_CACHELINE_SIZE, size); + if (p != 0) + memset(p, 0, size); + return p; +} + +static inline void ipq40xx_free_mem(void *ptr) +{ + if (ptr) + free(ptr); +} +#endif /* _IPQ40XX_EDMA_H */ diff --git a/sources/uboot-be550/drivers/net/ipq40xx/ipq40xx_ess_sw.c b/sources/uboot-be550/drivers/net/ipq40xx/ipq40xx_ess_sw.c new file mode 100644 index 00000000..807b1164 --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq40xx/ipq40xx_ess_sw.c @@ -0,0 +1,336 @@ +/* + * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. + + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. +*/ + +#include +#include +#include +#include + +#include "ipq40xx_ess_sw.h" +#include "ipq40xx.h" + +DECLARE_GLOBAL_DATA_PTR; + +static inline void ipq40xx_ess_sw_rd(u32 addr, u32 * data) +{ + *data = readl((void __iomem *)(IPQ40XX_NSS_BASE + addr)); +} + +static inline void ipq40xx_ess_sw_wr(u32 addr, u32 data) +{ + writel(data, ((void __iomem *)(IPQ40XX_NSS_BASE + addr))); +} + +void ipq40xx_ess_disable_lookup(void) +{ + ipq40xx_ess_sw_wr(S17_P0LOOKUP_CTRL_REG, 0x140000); + ipq40xx_ess_sw_wr(S17_P1LOOKUP_CTRL_REG, 0x14001c); + ipq40xx_ess_sw_wr(S17_P2LOOKUP_CTRL_REG, 0x14001a); + ipq40xx_ess_sw_wr(S17_P3LOOKUP_CTRL_REG, 0x140016); + ipq40xx_ess_sw_wr(S17_P4LOOKUP_CTRL_REG, 0x14001e); + ipq40xx_ess_sw_wr(S17_P5LOOKUP_CTRL_REG, 0x140000); + ipq40xx_ess_sw_wr(S17_GLOFW_CTRL1_REG, 0x3e3e3e); +} + +void ipq40xx_ess_enable_lookup(void) +{ + ipq40xx_ess_sw_wr(S17_P0LOOKUP_CTRL_REG, 0x14003e); + ipq40xx_ess_sw_wr(S17_P1LOOKUP_CTRL_REG, 0x14001d); + ipq40xx_ess_sw_wr(S17_P2LOOKUP_CTRL_REG, 0x14001b); + ipq40xx_ess_sw_wr(S17_P3LOOKUP_CTRL_REG, 0x140017); + ipq40xx_ess_sw_wr(S17_P4LOOKUP_CTRL_REG, 0x14000f); + ipq40xx_ess_sw_wr(S17_P5LOOKUP_CTRL_REG, 0x140001); + ipq40xx_ess_sw_wr(S17_GLOFW_CTRL1_REG, 0x3f3f3f); +} + +int ipq40xx_ess_sw_init(ipq40xx_edma_board_cfg_t *cfg) +{ + u32 data; + + ipq40xx_ess_sw_wr(S17_GLOFW_CTRL1_REG, 0x3e3e3e); + /* + * configure Speed, Duplex. + */ + ipq40xx_ess_sw_wr(S17_P0STATUS_REG, S17_PORT_SPEED(2) | + S17_PORT_FULL_DUP | + S17_TX_FLOW_EN | + S17_RX_FLOW_EN); + + switch(gd->bd->bi_arch_number) { + case MACH_TYPE_IPQ40XX_AP_DK01_1_S1: + case MACH_TYPE_IPQ40XX_AP_DK01_1_C1: + case MACH_TYPE_IPQ40XX_AP_DK01_1_C2: + case MACH_TYPE_IPQ40XX_AP_DK04_1_C1: + case MACH_TYPE_IPQ40XX_AP_DK04_1_C4: + case MACH_TYPE_IPQ40XX_AP_DK04_1_C2: + case MACH_TYPE_IPQ40XX_AP_DK04_1_C3: + case MACH_TYPE_IPQ40XX_AP_DK04_1_C6: + case MACH_TYPE_IPQ40XX_AP_DK05_1_C1: + case MACH_TYPE_IPQ40XX_AP_DK06_1_C1: + case MACH_TYPE_IPQ40XX_AP_DK07_1_C1: + case MACH_TYPE_IPQ40XX_AP_DK07_1_C2: + case MACH_TYPE_IPQ40XX_AP_DK07_1_C3: + case MACH_TYPE_IPQ40XX_AP_DK07_1_C4: + + ipq40xx_ess_sw_wr(S17_P0LOOKUP_CTRL_REG, 0x140000); + ipq40xx_ess_sw_wr(S17_P1LOOKUP_CTRL_REG, 0x140000); + ipq40xx_ess_sw_wr(S17_P2LOOKUP_CTRL_REG, 0x140000); + ipq40xx_ess_sw_wr(S17_P3LOOKUP_CTRL_REG, 0x140000); + ipq40xx_ess_sw_wr(S17_P4LOOKUP_CTRL_REG, 0x140000); + ipq40xx_ess_sw_wr(S17_P5LOOKUP_CTRL_REG, 0x140000); + /* + * HOL setting for Port0 + */ + ipq40xx_ess_sw_wr(S17_PORT0_HOL_CTRL0, 0x1e444444); + ipq40xx_ess_sw_wr(S17_PORT0_HOL_CTRL1, 0x1c6); + /* + * HOL setting for Port1 + */ + ipq40xx_ess_sw_wr(S17_PORT1_HOL_CTRL0, 0x1e004444); + ipq40xx_ess_sw_wr(S17_PORT1_HOL_CTRL1, 0x1c6); + /* + * HOL setting for Port2 + */ + ipq40xx_ess_sw_wr(S17_PORT2_HOL_CTRL0, 0x1e004444); + ipq40xx_ess_sw_wr(S17_PORT2_HOL_CTRL1, 0x1c6); + /* + * HOL setting for Port3 + */ + ipq40xx_ess_sw_wr(S17_PORT3_HOL_CTRL0, 0x1e004444); + ipq40xx_ess_sw_wr(S17_PORT3_HOL_CTRL1, 0x1c6); + /* + * HOL setting for Port4 + */ + ipq40xx_ess_sw_wr(S17_PORT4_HOL_CTRL0, 0x1e004444); + ipq40xx_ess_sw_wr(S17_PORT4_HOL_CTRL1, 0x1c6); + /* + * HOL setting for Port5 + */ + ipq40xx_ess_sw_wr(S17_PORT5_HOL_CTRL0, 0x1e444444); + ipq40xx_ess_sw_wr(S17_PORT5_HOL_CTRL1, 0x1c6); + break; + case MACH_TYPE_IPQ40XX_DB_DK02_1_C1: + case MACH_TYPE_IPQ40XX_DB_DK01_1_C1: + ipq40xx_ess_sw_wr(S17_P4STATUS_REG, S17_PORT_SPEED(2) | + S17_PORT_FULL_DUP | + S17_TX_FLOW_EN | + S17_RX_FLOW_EN | + S17_PORT_TX_MAC_EN | + S17_PORT_RX_MAC_EN); + ipq40xx_ess_sw_wr(S17_P5STATUS_REG, S17_PORT_SPEED(2) | + S17_PORT_FULL_DUP | + S17_TX_FLOW_EN | + S17_RX_FLOW_EN | + S17_PORT_TX_MAC_EN | + S17_PORT_RX_MAC_EN); + ipq40xx_ess_sw_wr(ESS_MIB_REG, 0x100000); + ipq40xx_ess_sw_wr(S17_P4LOOKUP_CTRL_REG, 0x34006f);; + break; + default: + printf("ess cfg not supported for %lx machid\n", + gd->bd->bi_arch_number); + return -1; + } + mdelay(1); + /* + * Enable Rx and Tx mac. + */ + ipq40xx_ess_sw_rd(S17_P0STATUS_REG, &data); + ipq40xx_ess_sw_wr(S17_P0STATUS_REG, data | + S17_PORT_TX_MAC_EN | + S17_PORT_RX_MAC_EN); + ipq40xx_ess_sw_rd(ESS_MIB_OFFSET, &data); + ipq40xx_ess_sw_wr(ESS_MIB_OFFSET, data | + ESS_MIB_EN); + ipq40xx_ess_sw_wr(S17_GLOFW_CTRL1_REG, 0x7f7f7f); + printf ("%s done\n", __func__); + + return 0; +} + +#ifdef CONFIG_ESS_MIB_EN +static void ess_dump_stats(struct ess_rx_stats *rx, + struct ess_tx_stats *tx, u32 port) +{ + /* + * Tx stats + */ + printf ("########tx port: %d stats ########\n", port); + printf("port: %d tx_broadcast: %d\n", port, tx->tx_broad); + printf("port: %d tx_pause: %d\n", port, tx->tx_pause); + printf("port: %d tx_multi: %d\n", port, tx->tx_multi); + printf("port: %d tx_underrun: %d\n", port, tx->tx_underrun); + printf("port: %d tx_64 byte: %d\n", port, tx->tx_64b); + printf("port: %d tx_128 byte: %d\n", port, tx->tx_128b); + printf("port: %d tx_256 byte: %d\n", port, tx->tx_256b); + printf("port: %d tx_512 byte: %d\n", port, tx->tx_512b); + printf("port: %d tx_1024 byte: %d\n", port, tx->tx_1024b); + printf("port: %d tx_1518 byte: %d\n", port, tx->tx_1518b); + printf("port: %d tx_max byte: %d\n", port, tx->tx_maxb); + printf("port: %d tx_oversize: %d\n", port, tx->tx_oversiz); + printf("port: %d tx_byte_lo: %d\n", port, tx->tx_bytel); + printf("port: %d tx_byte_hi: %d\n", port, tx->tx_byteh); + printf("port: %d tx_collision: %d\n", port, tx->tx_collision); + printf("port: %d tx_abort_col: %d\n", port, tx->tx_abortcol); + printf("port: %d tx_multi_col: %d\n", port, tx->tx_multicol); + printf("port: %d tx_singla_col: %d\n", port, tx->tx_singalcol); + printf("port: %d tx_exec_defer: %d\n", port, tx->tx_execdefer); + printf("port: %d tx_defer: %d\n", port, tx->tx_defer); + printf("port: %d tx_late_col: %d\n", port, tx->tx_latecol); + printf("port: %d tx_unicast: %d\n", port, tx->tx_unicast); + /* + * rx stats + */ + printf ("########rx port: %d stats ########\n\n", port); + printf("port: %d rx_broadcast: %d\n", port, rx->rx_broad); + printf("port: %d rx_pause: %d\n", port, rx->rx_pause); + printf("port: %d rx_multi: %d\n", port, rx->rx_multi); + printf("port: %d rx_fcserr: %d\n", port, rx->rx_fcserr); + printf("port: %d rx_allignerr: %d\n", port, rx->rx_allignerr); + printf("port: %d rx_runt: %d\n", port, rx->rx_runt); + printf("port: %d rx_frag: %d\n", port, rx->rx_frag); + printf("port: %d rx_64 byte: %d\n", port, rx->rx_64b); + printf("port: %d rx_128 byte: %d\n", port, rx->rx_128b); + printf("port: %d rx_256 byte: %d\n", port, rx->rx_256b); + printf("port: %d rx_512 byte: %d\n", port, rx->rx_512b); + printf("port: %d rx_1024 byte: %d\n", port, rx->rx_1024b); + printf("port: %d rx_1518 byte: %d\n", port, rx->rx_1518b); + printf("port: %d rx_max byte: %d\n", port, rx->rx_maxb); + printf("port: %d rx_too long: %d\n", port, rx->rx_tool); + printf("port: %d rx_good byte lo: %d\n", port, rx->rx_goodbl); + printf("port: %d rx_good byte hi: %d\n", port, rx->rx_goodbh); + printf("port: %d rx overflow: %d\n", port, rx->rx_overflow); + printf("port: %d rx_bad lo: %d\n", port, rx->rx_badbl); + printf("port: %d rx_bad hi: %d\n", port, rx->rx_badbu); + printf("port: %d rx unicast: %d\n", port, rx->rx_unicast); +} + +static int ipq40xx_ess_stats(cmd_tbl_t *cmdtp, int flag, + int argc, char *const argv[]) +{ + struct ess_rx_stats rx_mib; + struct ess_tx_stats tx_mib; + u32 portno; + unsigned long timebase; + + if (argc != 2) + return CMD_RET_USAGE; + + portno = simple_strtoul(argv[1], NULL, 16); + + if (portno > 6) + return CMD_RET_USAGE; + /* + * Tx stats + */ + ipq40xx_ess_sw_rd((ess_mib(portno) | + ESS_PHY_TX_BROAD_REG), &tx_mib.tx_broad); + ipq40xx_ess_sw_rd((ess_mib(portno) | + ESS_PHY_TX_PAUSE_REG), &tx_mib.tx_pause); + ipq40xx_ess_sw_rd((ess_mib(portno) | + ESS_PHY_TX_MULTI_REG), &tx_mib.tx_multi); + ipq40xx_ess_sw_rd((ess_mib(portno) | + ESS_PHY_TX_MULTI_REG), &tx_mib.tx_underrun); + ipq40xx_ess_sw_rd((ess_mib(portno) | + ESS_PHY_TX_64B_REG), &tx_mib.tx_64b); + ipq40xx_ess_sw_rd((ess_mib(portno) | + ESS_PHY_TX_128B_REG), &tx_mib.tx_128b); + ipq40xx_ess_sw_rd((ess_mib(portno) | + ESS_PHY_TX_256B_REG), &tx_mib.tx_256b); + ipq40xx_ess_sw_rd((ess_mib(portno) | + ESS_PHY_TX_512B_REG), &tx_mib.tx_512b); + ipq40xx_ess_sw_rd((ess_mib(portno) | + ESS_PHY_TX_1024B_REG), &tx_mib.tx_1024b); + ipq40xx_ess_sw_rd((ess_mib(portno) | + ESS_PHY_TX_1518B_REG), &tx_mib.tx_1518b); + ipq40xx_ess_sw_rd((ess_mib(portno) | + ESS_PHY_TX_MAXB_REG), &tx_mib.tx_maxb); + ipq40xx_ess_sw_rd((ess_mib(portno) | + ESS_PHY_TX_OVSIZE_REG), &tx_mib.tx_oversiz); + ipq40xx_ess_sw_rd((ess_mib(portno) | + ESS_PHY_TX_TXBYTEL_REG), &tx_mib.tx_bytel); + ipq40xx_ess_sw_rd((ess_mib(portno) | + ESS_PHY_TX_TXBYTEU_REG), &tx_mib.tx_byteh); + ipq40xx_ess_sw_rd((ess_mib(portno) | + ESS_PHY_TX_COLL_REG), &tx_mib.tx_collision); + ipq40xx_ess_sw_rd((ess_mib(portno) | + ESS_PHY_TX_ABTCOLL_REG), &tx_mib.tx_abortcol); + ipq40xx_ess_sw_rd((ess_mib(portno) | + ESS_PHY_TX_MLTCOL_REG), &tx_mib.tx_multicol); + ipq40xx_ess_sw_rd((ess_mib(portno) | + ESS_PHY_TX_SINGCOL_REG), &tx_mib.tx_singalcol); + ipq40xx_ess_sw_rd((ess_mib(portno) | + ESS_PHY_TX_EXDF_REG), &tx_mib.tx_execdefer); + ipq40xx_ess_sw_rd((ess_mib(portno) | + ESS_PHY_TX_DEF_REG), &tx_mib.tx_defer); + ipq40xx_ess_sw_rd((ess_mib(portno) | + ESS_PHY_TX_LATECOL_REG), &tx_mib.tx_latecol); + ipq40xx_ess_sw_rd((ess_mib(portno) | + ESS_PHY_TX_UNICAST), &tx_mib.tx_unicast); + /* + * Rx stats + */ + + ipq40xx_ess_sw_rd((ess_mib(portno) | + ESS_PHY_RX_BROAD_REG), &rx_mib.rx_broad); + ipq40xx_ess_sw_rd((ess_mib(portno) | + ESS_PHY_RX_PAUSE_REG), &rx_mib.rx_pause); + ipq40xx_ess_sw_rd((ess_mib(portno) | + ESS_PHY_RX_MULTI_REG), &rx_mib.rx_multi); + ipq40xx_ess_sw_rd((ess_mib(portno) | + ESS_PHY_RX_FCSERR_REG), &rx_mib.rx_fcserr); + ipq40xx_ess_sw_rd((ess_mib(portno) | + ESS_PHY_RX_ALIGNERR_REG), &rx_mib.rx_allignerr); + ipq40xx_ess_sw_rd((ess_mib(portno) | + ESS_PHY_RX_RUNT_REG), &rx_mib.rx_runt); + ipq40xx_ess_sw_rd((ess_mib(portno) | + ESS_PHY_RX_FRAGMENT_REG), &rx_mib.rx_frag); + ipq40xx_ess_sw_rd((ess_mib(portno) | + ESS_PHY_RX_RUNT_REG), &rx_mib.rx_64b); + ipq40xx_ess_sw_rd((ess_mib(portno) | + ESS_PHY_RX_128B_REG), &rx_mib.rx_128b); + ipq40xx_ess_sw_rd((ess_mib(portno) | + ESS_phy_RX_256B_REG), &rx_mib.rx_256b); + ipq40xx_ess_sw_rd((ess_mib(portno) | + ESS_PHY_RX_512B_REG), &rx_mib.rx_512b); + ipq40xx_ess_sw_rd((ess_mib(portno) | + ESS_PHY_RX_1024B_REG), &rx_mib.rx_1024b); + ipq40xx_ess_sw_rd((ess_mib(portno) | + ESS_PHY_RX_1518B_REG), &rx_mib.rx_1518b); + ipq40xx_ess_sw_rd((ess_mib(portno) | + ESS_PHY_RX_MAXB_REG), &rx_mib.rx_maxb); + ipq40xx_ess_sw_rd((ess_mib(portno) | + ESS_PHY_RX_TOLO_REG), &rx_mib.rx_tool); + ipq40xx_ess_sw_rd((ess_mib(portno) | + ESS_PHY_RX_GOODBL_REG), &rx_mib.rx_goodbl); + ipq40xx_ess_sw_rd((ess_mib(portno) | + ESS_PHY_RX_GOODBU_REG), &rx_mib.rx_goodbh); + ipq40xx_ess_sw_rd((ess_mib(portno) | + ESS_PHY_RX_OVERFLW_REG), rx_mib.rx_overflow); + ipq40xx_ess_sw_rd((ess_mib(portno) | + ESS_PHY_RX_BADBL_REG), &rx_mib.rx_badbl); + ipq40xx_ess_sw_rd((ess_mib(portno) | + ESS_PHY_RX_BADBL_REG), &rx_mib.rx_badbu); + ipq40xx_ess_sw_rd((ess_mib(portno) | + ESS_PHY_RX_UNICAST), &rx_mib.rx_unicast); + /* + * Dump stats + */ + ess_dump_stats(&rx_mib, &tx_mib, portno); + return 0; +} +U_BOOT_CMD(essstats, 2, 0, ipq40xx_ess_stats, + "get ess mib stats for the given ess port", + "essstats <0 - 5>"); +#endif + diff --git a/sources/uboot-be550/drivers/net/ipq40xx/ipq40xx_ess_sw.h b/sources/uboot-be550/drivers/net/ipq40xx/ipq40xx_ess_sw.h new file mode 100644 index 00000000..208b96e3 --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq40xx/ipq40xx_ess_sw.h @@ -0,0 +1,181 @@ +/* + * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. + + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. +*/ + +#ifndef _AR8327_PHY_H +#define _AR8327_PHY_H +#define IPQ40XX_NSS_BASE 0xC000000 + +#define S17_P0STATUS_REG 0x007c +#define S17_P1STATUS_REG 0x0080 +#define S17_P2STATUS_REG 0x0084 +#define S17_P3STATUS_REG 0x0088 +#define S17_P4STATUS_REG 0x008c +#define S17_P5STATUS_REG 0x0090 +#define S17_P6STATUS_REG 0x0094 + +#define S17_PORT_SPEED(x) (x << 0) +#define S17_TX_FLOW_EN (1 << 4) +#define S17_RX_FLOW_EN (1 << 5) +#define S17_PORT_TX_MAC_EN (1 << 2) +#define S17_PORT_RX_MAC_EN (1 << 3) +#define S17_PORT_FULL_DUP (1 << 6) + +#define S17_GLOFW_CTRL1_REG 0x0624 +#define S17_GLOLEARN_LIMIT_REG 0x0628 +#define S17_TOS_PRIMAP_REG0 0x0630 +#define S17_TOS_PRIMAP_REG1 0x0634 +#define S17_TOS_PRIMAP_REG2 0x0638 +#define S17_TOS_PRIMAP_REG3 0x063c +#define S17_TOS_PRIMAP_REG4 0x0640 +#define S17_TOS_PRIMAP_REG5 0x0644 +#define S17_TOS_PRIMAP_REG6 0x0648 +#define S17_TOS_PRIMAP_REG7 0x064c +#define S17_VLAN_PRIMAP_REG0 0x0650 +#define S17_LOOP_CHECK_REG 0x0654 +#define S17_P0LOOKUP_CTRL_REG 0x0660 +#define S17_P0PRI_CTRL_REG 0x0664 +#define S17_P0LEARN_LMT_REG 0x0668 +#define S17_P1LOOKUP_CTRL_REG 0x066c +#define S17_P1PRI_CTRL_REG 0x0670 +#define S17_P1LEARN_LMT_REG 0x0674 +#define S17_P2LOOKUP_CTRL_REG 0x0678 +#define S17_P2PRI_CTRL_REG 0x067c +#define S17_P2LEARN_LMT_REG 0x0680 +#define S17_P3LOOKUP_CTRL_REG 0x0684 +#define S17_P3PRI_CTRL_REG 0x0688 +#define S17_P3LEARN_LMT_REG 0x068c +#define S17_P4LOOKUP_CTRL_REG 0x0690 +#define S17_P4PRI_CTRL_REG 0x0694 +#define S17_P4LEARN_LMT_REG 0x0698 +#define S17_P5LOOKUP_CTRL_REG 0x069c + +/* Queue Management Registers */ +#define S17_PORT0_HOL_CTRL0 0x0970 +#define S17_PORT0_HOL_CTRL1 0x0974 +#define S17_PORT1_HOL_CTRL0 0x0978 +#define S17_PORT1_HOL_CTRL1 0x097c +#define S17_PORT2_HOL_CTRL0 0x0980 +#define S17_PORT2_HOL_CTRL1 0x0984 +#define S17_PORT3_HOL_CTRL0 0x0988 +#define S17_PORT3_HOL_CTRL1 0x098c +#define S17_PORT4_HOL_CTRL0 0x0990 +#define S17_PORT4_HOL_CTRL1 0x0994 +#define S17_PORT5_HOL_CTRL0 0x0998 +#define S17_PORT5_HOL_CTRL1 0x099c + +#define ess_mib(x) ((0x1000 | (x * 0x100))) +#define ESS_MIB_OFFSET 0x30 +#define ESS_MIB_REG 0x34 +#define ESS_MIB_EN (1 << 0) +#ifdef CONFIG_ESS_MIB_EN +/* + * Tx Mib counter offset + */ +#define ESS_PHY_TX_BROAD_REG 0x54 +#define ESS_PHY_TX_PAUSE_REG 0x58 +#define ESS_PHY_TX_MULTI_REG 0x5c +#define ESS_PHY_TX_UNDERRN_REG 0x60 +#define ESS_PHY_TX_64B_REG 0x64 +#define ESS_PHY_TX_128B_REG 0x68 +#define ESS_PHY_TX_256B_REG 0x6c +#define ESS_PHY_TX_512B_REG 0x70 +#define ESS_PHY_TX_1024B_REG 0x74 +#define ESS_PHY_TX_1518B_REG 0x78 +#define ESS_PHY_TX_MAXB_REG 0x7c +#define ESS_PHY_TX_OVSIZE_REG 0x80 +#define ESS_PHY_TX_TXBYTEL_REG 0x88 +#define ESS_PHY_TX_TXBYTEU_REG 0x84 +#define ESS_PHY_TX_COLL_REG 0x8c +#define ESS_PHY_TX_ABTCOLL_REG 0x90 +#define ESS_PHY_TX_MLTCOL_REG 0x94 +#define ESS_PHY_TX_SINGCOL_REG 0x98 +#define ESS_PHY_TX_EXDF_REG 0x9c +#define ESS_PHY_TX_DEF_REG 0xA0 +#define ESS_PHY_TX_LATECOL_REG 0xA4 +#define ESS_PHY_TX_UNICAST 0xAc +/* + * Rx Mib counter offset + */ +#define ESS_PHY_RX_BROAD_REG 0x00 +#define ESS_PHY_RX_PAUSE_REG 0x04 +#define ESS_PHY_RX_MULTI_REG 0x08 +#define ESS_PHY_RX_FCSERR_REG 0x0c +#define ESS_PHY_RX_ALIGNERR_REG 0x10 +#define ESS_PHY_RX_RUNT_REG 0x14 +#define ESS_PHY_RX_FRAGMENT_REG 0x18 +#define ESS_PHY_RX_64B_REG 0x1c +#define ESS_PHY_RX_128B_REG 0x20 +#define ESS_phy_RX_256B_REG 0x24 +#define ESS_PHY_RX_512B_REG 0x28 +#define ESS_PHY_RX_1024B_REG 0x2c +#define ESS_PHY_RX_1518B_REG 0x30 +#define ESS_PHY_RX_MAXB_REG 0x34 +#define ESS_PHY_RX_TOLO_REG 0x38 +#define ESS_PHY_RX_GOODBL_REG 0x40 +#define ESS_PHY_RX_GOODBU_REG 0x3c +#define ESS_PHY_RX_BADBL_REG 0x48 +#define ESS_PHY_RX_BADBU_REG 0x44 +#define ESS_PHY_RX_OVERFLW_REG 0x4c +#define ESS_PHY_RX_FILTERD_REG 0x50 +#define ESS_PHY_RX_UNICAST 0xA8 + +struct ess_rx_stats { + u32 rx_broad; + u32 rx_pause; + u32 rx_multi; + u32 rx_fcserr; + u32 rx_allignerr; + u32 rx_runt; + u32 rx_frag; + u32 rx_64b; + u32 rx_128b; + u32 rx_256b; + u32 rx_512b; + u32 rx_1024b; + u32 rx_1518b; + u32 rx_maxb; + u32 rx_tool; + u32 rx_goodbl; + u32 rx_goodbh; + u32 rx_overflow; + u32 rx_badbl; + u32 rx_badbu; + u32 rx_unicast; +}; + +struct ess_tx_stats{ + u32 tx_broad; + u32 tx_pause; + u32 tx_multi; + u32 tx_underrun; + u32 tx_64b; + u32 tx_128b; + u32 tx_256b; + u32 tx_512b; + u32 tx_1024b; + u32 tx_1518b; + u32 tx_maxb; + u32 tx_oversiz; + u32 tx_bytel; + u32 tx_byteh; + u32 tx_collision; + u32 tx_abortcol; + u32 tx_multicol; + u32 tx_singalcol; + u32 tx_execdefer; + u32 tx_defer; + u32 tx_latecol; + u32 tx_unicast; +}; +#endif +#endif diff --git a/sources/uboot-be550/drivers/net/ipq40xx/ipq40xx_mdio.c b/sources/uboot-be550/drivers/net/ipq40xx/ipq40xx_mdio.c new file mode 100644 index 00000000..d4dd918f --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq40xx/ipq40xx_mdio.c @@ -0,0 +1,124 @@ +/* + * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. + + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. +*/ + +#include +#include +#include +#include +#include +#include "ipq40xx_mdio.h" + +struct ipq40xx_mdio_data { + struct mii_bus *bus; + int phy_irq[PHY_MAX_ADDR]; +}; + +static int ipq40xx_mdio_wait_busy(void) +{ + int i; + u32 busy; + for (i = 0; i < IPQ40XX_MDIO_RETRY; i++) { + udelay(IPQ40XX_MDIO_DELAY); + busy = readl(IPQ40XX_MDIO_BASE + + MDIO_CTRL_4_REG) & + MDIO_CTRL_4_ACCESS_BUSY; + + if (!busy) + return 0; + udelay(IPQ40XX_MDIO_DELAY); + } + printf("%s: MDIO operation timed out\n", + __func__); + return -ETIMEDOUT; +} + +int ipq40xx_mdio_write(int mii_id, int regnum, u16 value) +{ + if (ipq40xx_mdio_wait_busy()) + return -ETIMEDOUT; + /* Issue the phy addreass and reg */ + writel((mii_id << 8 | regnum), + IPQ40XX_MDIO_BASE + MDIO_CTRL_1_REG); + + /* Issue a write data */ + writel(value, IPQ40XX_MDIO_BASE + MDIO_CTRL_2_REG); + + /* Issue write command */ + writel((MDIO_CTRL_4_ACCESS_START | + MDIO_CTRL_4_ACCESS_CODE_WRITE), + (IPQ40XX_MDIO_BASE + MDIO_CTRL_4_REG)); + + /* Wait for write complete */ + + if (ipq40xx_mdio_wait_busy()) + return -ETIMEDOUT; + + return 0; +} + +int ipq40xx_mdio_read(int mii_id, int regnum, ushort *data) +{ + u32 val; + if (ipq40xx_mdio_wait_busy()) + return -ETIMEDOUT; + + /* Issue the phy address and reg */ + writel((mii_id << 8) | regnum, + IPQ40XX_MDIO_BASE + MDIO_CTRL_1_REG); + + /* issue read command */ + writel((MDIO_CTRL_4_ACCESS_START | + MDIO_CTRL_4_ACCESS_CODE_READ), + (IPQ40XX_MDIO_BASE + MDIO_CTRL_4_REG)); + + if (ipq40xx_mdio_wait_busy()) + return -ETIMEDOUT; + + /* Read data */ + val = readl(IPQ40XX_MDIO_BASE + MDIO_CTRL_3_REG); + + if (data != NULL) + *data = val; + + return val; +} + +int ipq40xx_phy_write(struct mii_dev *bus, + int addr, int dev_addr, + int regnum, ushort value) +{ + return ipq40xx_mdio_write( + addr, regnum, value); +} + +int ipq40xx_phy_read(struct mii_dev *bus, + int addr, int dev_addr, int regnum) +{ + return ipq40xx_mdio_read( + addr, regnum, NULL); +} + +int ipq40xx_sw_mdio_init(const char *name) +{ + struct mii_dev *bus = mdio_alloc(); + if(!bus) { + printf("Failed to allocate IPQ MDIO bus\n"); + return -1; + } + bus->read = ipq40xx_phy_read; + bus->write = ipq40xx_phy_write; + bus->reset = NULL; + snprintf(bus->name, MDIO_NAME_LEN, name); + return mdio_register(bus); +} + diff --git a/sources/uboot-be550/drivers/net/ipq40xx/ipq40xx_mdio.h b/sources/uboot-be550/drivers/net/ipq40xx/ipq40xx_mdio.h new file mode 100644 index 00000000..16b4a88c --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq40xx/ipq40xx_mdio.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. + + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. +*/ +#ifndef _IPQ40XX_MDIO_H +#define _IPQ40XX_MDIO_H + +#define IPQ40XX_MDIO_BASE 0x90000 +#define MDIO_CTRL_0_REG 0x40 +#define MDIO_CTRL_1_REG 0x44 +#define MDIO_CTRL_2_REG 0x48 +#define MDIO_CTRL_3_REG 0x4c +#define MDIO_CTRL_4_REG 0x50 +#define MDIO_CTRL_4_ACCESS_BUSY (1 << 16) +#define MDIO_CTRL_4_ACCESS_START (1 << 8) +#define MDIO_CTRL_4_ACCESS_CODE_READ 0 +#define MDIO_CTRL_4_ACCESS_CODE_WRITE 1 + +#define IPQ40XX_MDIO_RETRY 1000 +#define IPQ40XX_MDIO_DELAY 5 +#endif /* End _IPQ40XX_MDIO_H */ diff --git a/sources/uboot-be550/drivers/net/ipq40xx/ipq40xx_qca8075.c b/sources/uboot-be550/drivers/net/ipq40xx/ipq40xx_qca8075.c new file mode 100644 index 00000000..452902cf --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq40xx/ipq40xx_qca8075.c @@ -0,0 +1,772 @@ +/* + * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. + + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. +*/ +#include +#include +#include +#include +#include +#include +#include "ipq40xx_edma_eth.h" +#include "ipq40xx_qca8075.h" + +extern int ipq40xx_mdio_write(int mii_id, + int regnum, u16 value); +extern int ipq40xx_mdio_read(int mii_id, + int regnum, ushort *data); + +static u32 qca8075_id; +static u16 qca8075_phy_reg_write(u32 dev_id, u32 phy_id, + u32 reg_id, u16 reg_val) +{ + ipq40xx_mdio_write(phy_id, reg_id, reg_val); + return 0; +} + +u16 qca8075_phy_reg_read(u32 dev_id, u32 phy_id, u32 reg_id) +{ + return ipq40xx_mdio_read(phy_id, reg_id, NULL); +} + +/* + * phy4 prfer medium + * get phy4 prefer medum, fiber or copper; + */ +static qca8075_phy_medium_t __phy_prefer_medium_get(u32 dev_id, + u32 phy_id) +{ + u16 phy_medium; + phy_medium = + qca8075_phy_reg_read(dev_id, phy_id, + QCA8075_PHY_CHIP_CONFIG); + + return ((phy_medium & QCA8075_PHY4_PREFER_FIBER) ? + QCA8075_PHY_MEDIUM_FIBER : QCA8075_PHY_MEDIUM_COPPER); +} + +/* + * phy4 activer medium + * get phy4 current active medium, fiber or copper; + */ +static qca8075_phy_medium_t __phy_active_medium_get(u32 dev_id, + u32 phy_id) +{ + u16 phy_data = 0; + u32 phy_mode; + + phy_mode = qca8075_phy_reg_read(dev_id, phy_id, + QCA8075_PHY_CHIP_CONFIG); + phy_mode &= 0x000f; + + if (phy_mode == QCA8075_PHY_PSGMII_AMDET) { + phy_data = qca8075_phy_reg_read(dev_id, + phy_id, QCA8075_PHY_SGMII_STATUS); + + if ((phy_data & QCA8075_PHY4_AUTO_COPPER_SELECT)) { + return QCA8075_PHY_MEDIUM_COPPER; + } else if ((phy_data & QCA8075_PHY4_AUTO_BX1000_SELECT)) { + /* PHY_MEDIUM_FIBER_BX1000 */ + return QCA8075_PHY_MEDIUM_FIBER; + } else if ((phy_data & QCA8075_PHY4_AUTO_FX100_SELECT)) { + /* PHY_MEDIUM_FIBER_FX100 */ + return QCA8075_PHY_MEDIUM_FIBER; + } + /* link down */ + return __phy_prefer_medium_get(dev_id, phy_id); + } else if ((phy_mode == QCA8075_PHY_PSGMII_BASET) || + (phy_mode == QCA8075_PHY_SGMII_BASET)) { + return QCA8075_PHY_MEDIUM_COPPER; + } else if ((phy_mode == QCA8075_PHY_PSGMII_BX1000) || + (phy_mode == QCA8075_PHY_PSGMII_FX100)) { + return QCA8075_PHY_MEDIUM_FIBER; + } else { + return QCA8075_PHY_MEDIUM_COPPER; + } +} + +/* + * phy4 copper page or fiber page select + * set phy4 copper or fiber page + */ + +static u8 __phy_reg_pages_sel(u32 dev_id, u32 phy_id, + qca8075_phy_reg_pages_t phy_reg_pages) +{ + u16 reg_pages; + reg_pages = qca8075_phy_reg_read(dev_id, + phy_id, QCA8075_PHY_CHIP_CONFIG); + + if (phy_reg_pages == QCA8075_PHY_COPPER_PAGES) { + reg_pages |= 0x8000; + } else if (phy_reg_pages == QCA8075_PHY_SGBX_PAGES) { + reg_pages &= ~0x8000; + } else + return -EINVAL; + + qca8075_phy_reg_write(dev_id, phy_id, + QCA8075_PHY_CHIP_CONFIG, reg_pages); + return 0; +} + +/* + * phy4 reg pages selection by active medium + * phy4 reg pages selection + */ +static u32 __phy_reg_pages_sel_by_active_medium(u32 dev_id, + u32 phy_id) +{ + qca8075_phy_medium_t phy_medium; + qca8075_phy_reg_pages_t reg_pages; + + phy_medium = __phy_active_medium_get(dev_id, phy_id); + if (phy_medium == QCA8075_PHY_MEDIUM_FIBER) { + reg_pages = QCA8075_PHY_SGBX_PAGES; + } else if (phy_medium == QCA8075_PHY_MEDIUM_COPPER) { + reg_pages = QCA8075_PHY_COPPER_PAGES; + } else { + return -1; + } + + return __phy_reg_pages_sel(dev_id, phy_id, reg_pages); +} + +u8 qca8075_phy_get_link_status(u32 dev_id, u32 phy_id) +{ + u16 phy_data; + if (phy_id == COMBO_PHY_ID) + __phy_reg_pages_sel_by_active_medium(dev_id, phy_id); + phy_data = qca8075_phy_reg_read(dev_id, + phy_id, QCA8075_PHY_SPEC_STATUS); + if (phy_data & QCA8075_STATUS_LINK_PASS) + return 0; + + return 1; +} + +u32 qca8075_phy_get_duplex(u32 dev_id, u32 phy_id, + fal_port_duplex_t * duplex) +{ + u16 phy_data; + + if (phy_id == COMBO_PHY_ID) { + __phy_reg_pages_sel_by_active_medium(dev_id, phy_id); + } + + phy_data = qca8075_phy_reg_read(dev_id, phy_id, + QCA8075_PHY_SPEC_STATUS); + + /* + * Read duplex + */ + if (phy_data & QCA8075_STATUS_FULL_DUPLEX) + *duplex = FAL_FULL_DUPLEX; + else + *duplex = FAL_HALF_DUPLEX; + + return 0; +} + +u32 qca8075_phy_get_speed(u32 dev_id, u32 phy_id, + fal_port_speed_t * speed) +{ + u16 phy_data; + + if (phy_id == COMBO_PHY_ID) { + __phy_reg_pages_sel_by_active_medium(dev_id, phy_id); + } + phy_data = qca8075_phy_reg_read(dev_id, + phy_id, QCA8075_PHY_SPEC_STATUS); + + switch (phy_data & QCA8075_STATUS_SPEED_MASK) { + case QCA8075_STATUS_SPEED_1000MBS: + *speed = FAL_SPEED_1000; + break; + case QCA8075_STATUS_SPEED_100MBS: + *speed = FAL_SPEED_100; + break; + case QCA8075_STATUS_SPEED_10MBS: + *speed = FAL_SPEED_10; + break; + default: + return -EINVAL; + } + return 0; +} + +static u32 qca8075_phy_mmd_write(u32 dev_id, u32 phy_id, + u16 mmd_num, u16 reg_id, u16 reg_val) +{ + qca8075_phy_reg_write(dev_id, phy_id, + QCA8075_MMD_CTRL_REG, mmd_num); + qca8075_phy_reg_write(dev_id, phy_id, + QCA8075_MMD_DATA_REG, reg_id); + qca8075_phy_reg_write(dev_id, phy_id, + QCA8075_MMD_CTRL_REG, + 0x4000 | mmd_num); + qca8075_phy_reg_write(dev_id, phy_id, + QCA8075_MMD_DATA_REG, reg_val); + + return 0; +} + +static u16 qca8075_phy_mmd_read(u32 dev_id, u32 phy_id, + u16 mmd_num, u16 reg_id) +{ + qca8075_phy_reg_write(dev_id, phy_id, + QCA8075_MMD_CTRL_REG, mmd_num); + qca8075_phy_reg_write(dev_id, phy_id, + QCA8075_MMD_DATA_REG, reg_id); + qca8075_phy_reg_write(dev_id, phy_id, + QCA8075_MMD_CTRL_REG, + 0x4000 | mmd_num); + return qca8075_phy_reg_read(dev_id, phy_id, + QCA8075_MMD_DATA_REG); +} + +/* + * get phy4 medium is 100fx + */ +static u8 __medium_is_fiber_100fx(u32 dev_id, u32 phy_id) +{ + u16 phy_data; + phy_data = qca8075_phy_reg_read(dev_id, phy_id, + QCA8075_PHY_SGMII_STATUS); + + if (phy_data & QCA8075_PHY4_AUTO_FX100_SELECT) { + return 1; + } + /* Link down */ + if ((!(phy_data & QCA8075_PHY4_AUTO_COPPER_SELECT)) && + (!(phy_data & QCA8075_PHY4_AUTO_BX1000_SELECT)) && + (!(phy_data & QCA8075_PHY4_AUTO_SGMII_SELECT))) { + + phy_data = qca8075_phy_reg_read(dev_id, phy_id, + QCA8075_PHY_CHIP_CONFIG); + if ((phy_data & QCA8075_PHY4_PREFER_FIBER) + && (!(phy_data & QCA8075_PHY4_FIBER_MODE_1000BX))) { + return 1; + } + } + return 0; +} + +/* + * qca8075_phy_set_hibernate - set hibernate status + * set hibernate status + */ +static u32 qca8075_phy_set_hibernate(u32 dev_id, u32 phy_id, u8 enable) +{ + u16 phy_data; + + qca8075_phy_reg_write(dev_id, phy_id, QCA8075_DEBUG_PORT_ADDRESS, + QCA8075_DEBUG_PHY_HIBERNATION_CTRL); + + phy_data = qca8075_phy_reg_read(dev_id, phy_id, + QCA8075_DEBUG_PORT_DATA); + + if (enable) { + phy_data |= 0x8000; + } else { + phy_data &= ~0x8000; + } + + qca8075_phy_reg_write(dev_id, phy_id, QCA8075_DEBUG_PORT_DATA, phy_data); + return 0; +} + +/* + * qca8075_restart_autoneg - restart the phy autoneg + */ +static u32 qca8075_phy_restart_autoneg(u32 dev_id, u32 phy_id) +{ + u16 phy_data; + + if (phy_id == COMBO_PHY_ID) { + if (__medium_is_fiber_100fx(dev_id, phy_id)) + return -1; + __phy_reg_pages_sel_by_active_medium(dev_id, phy_id); + } + phy_data = qca8075_phy_reg_read(dev_id, phy_id, QCA8075_PHY_CONTROL); + phy_data |= QCA8075_CTRL_AUTONEGOTIATION_ENABLE; + qca8075_phy_reg_write(dev_id, phy_id, QCA8075_PHY_CONTROL, + phy_data | QCA8075_CTRL_RESTART_AUTONEGOTIATION); + + return 0; +} + +/* + * qca8075_phy_get_8023az status + * get 8023az status + */ +static u32 qca8075_phy_get_8023az(u32 dev_id, u32 phy_id, u8 *enable) +{ + u16 phy_data; + if (phy_id == COMBO_PHY_ID) { + if (QCA8075_PHY_MEDIUM_COPPER != + __phy_active_medium_get(dev_id, phy_id)) + return -1; + } + *enable = 0; + + phy_data = qca8075_phy_mmd_read(dev_id, phy_id, QCA8075_PHY_MMD7_NUM, + QCA8075_PHY_MMD7_ADDR_8023AZ_EEE_CTRL); + + if ((phy_data & 0x0004) && (phy_data & 0x0002)) + *enable = 1; + + return 0; +} + +/* + * qca8075_phy_set_powersave - set power saving status + */ +static u32 qca8075_phy_set_powersave(u32 dev_id, u32 phy_id, u8 enable) +{ + u16 phy_data; + u8 status = 0; + + if (phy_id == COMBO_PHY_ID) { + if (QCA8075_PHY_MEDIUM_COPPER != + __phy_active_medium_get(dev_id, phy_id)) + return -1; + } + + if (enable) { + qca8075_phy_get_8023az(dev_id, phy_id, &status); + if (!status) { + phy_data = qca8075_phy_mmd_read(dev_id, phy_id, + QCA8075_PHY_MMD3_NUM, + QCA8075_PHY_MMD3_ADDR_8023AZ_TIMER_CTRL); + phy_data &= ~(1 << 14); + qca8075_phy_mmd_write(dev_id, phy_id, + QCA8075_PHY_MMD3_NUM, + QCA8075_PHY_MMD3_ADDR_8023AZ_TIMER_CTRL, + phy_data); + } + phy_data = qca8075_phy_mmd_read(dev_id, phy_id, + QCA8075_PHY_MMD3_NUM, + QCA8075_PHY_MMD3_ADDR_CLD_CTRL5); + phy_data &= ~(1 << 14); + qca8075_phy_mmd_write(dev_id, phy_id, QCA8075_PHY_MMD3_NUM, + QCA8075_PHY_MMD3_ADDR_CLD_CTRL5, + phy_data); + + phy_data = qca8075_phy_mmd_read(dev_id, phy_id, + QCA8075_PHY_MMD3_NUM, + QCA8075_PHY_MMD3_ADDR_CLD_CTRL3); + phy_data &= ~(1 << 15); + qca8075_phy_mmd_write(dev_id, phy_id, QCA8075_PHY_MMD3_NUM, + QCA8075_PHY_MMD3_ADDR_CLD_CTRL3, phy_data); + + } else { + phy_data = qca8075_phy_mmd_read(dev_id, phy_id, + QCA8075_PHY_MMD3_NUM, + QCA8075_PHY_MMD3_ADDR_8023AZ_TIMER_CTRL); + phy_data |= (1 << 14); + qca8075_phy_mmd_write(dev_id, phy_id, QCA8075_PHY_MMD3_NUM, + QCA8075_PHY_MMD3_ADDR_8023AZ_TIMER_CTRL, + phy_data); + + phy_data = qca8075_phy_mmd_read(dev_id, phy_id, + QCA8075_PHY_MMD3_NUM, + QCA8075_PHY_MMD3_ADDR_CLD_CTRL5); + phy_data |= (1 << 14); + qca8075_phy_mmd_write(dev_id, phy_id, QCA8075_PHY_MMD3_NUM, + QCA8075_PHY_MMD3_ADDR_CLD_CTRL5, phy_data); + + phy_data = qca8075_phy_mmd_read(dev_id, phy_id, + QCA8075_PHY_MMD3_NUM, + QCA8075_PHY_MMD3_ADDR_CLD_CTRL3); + phy_data |= (1 << 15); + qca8075_phy_mmd_write(dev_id, phy_id, QCA8075_PHY_MMD3_NUM, + QCA8075_PHY_MMD3_ADDR_CLD_CTRL3, phy_data); + + } + qca8075_phy_reg_write(dev_id, phy_id, QCA8075_PHY_CONTROL, 0x9040); + return 0; +} + +/* + * qca8075_phy_set_802.3az + */ + static u32 qca8075_phy_set_8023az(u32 dev_id, u32 phy_id, u8 enable) +{ + u16 phy_data; + + if (phy_id == COMBO_PHY_ID) { + if (QCA8075_PHY_MEDIUM_COPPER != + __phy_active_medium_get(dev_id, phy_id)) + return -1; + } + phy_data = qca8075_phy_mmd_read(dev_id, phy_id, QCA8075_PHY_MMD7_NUM, + QCA8075_PHY_MMD7_ADDR_8023AZ_EEE_CTRL); + if (enable) { + phy_data |= 0x0006; + + qca8075_phy_mmd_write(dev_id, phy_id, QCA8075_PHY_MMD7_NUM, + QCA8075_PHY_MMD7_ADDR_8023AZ_EEE_CTRL, phy_data); + if (qca8075_id == QCA8075_PHY_V1_0_5P) { + /* + * Workaround to avoid packet loss and < 10m cable + * 1000M link not stable under az enable + */ + qca8075_phy_mmd_write(dev_id, phy_id, + QCA8075_PHY_MMD3_NUM, + QCA8075_PHY_MMD3_ADDR_8023AZ_TIMER_CTRL, + AZ_TIMER_CTRL_ADJUST_VALUE); + + qca8075_phy_mmd_write(dev_id, phy_id, + QCA8075_PHY_MMD3_NUM, + QCA8075_PHY_MMD3_ADDR_8023AZ_CLD_CTRL, + AZ_CLD_CTRL_ADJUST_VALUE); + } + } else { + phy_data &= ~0x0006; + qca8075_phy_mmd_write(dev_id, phy_id, QCA8075_PHY_MMD7_NUM, + QCA8075_PHY_MMD7_ADDR_8023AZ_EEE_CTRL, phy_data); + if (qca8075_id == QCA8075_PHY_V1_0_5P) { + qca8075_phy_mmd_write(dev_id, phy_id, + QCA8075_PHY_MMD3_NUM, + QCA8075_PHY_MMD3_ADDR_8023AZ_TIMER_CTRL, + AZ_TIMER_CTRL_DEFAULT_VALUE); + } + } + qca8075_phy_restart_autoneg(dev_id, phy_id); + return 0; +} + +void ess_reset(void) +{ + writel(0x1, 0x1812008); + mdelay(10); + writel(0x0, 0x1812008); + mdelay(100); +} + +void qca8075_ess_reset(void) +{ + int i; + u32 status; + /* + * Fix phy psgmii RX 20bit + */ + qca8075_phy_reg_write(0, 5, 0x0, 0x005b); + /* + * Reset phy psgmii + */ + qca8075_phy_reg_write(0, 5, 0x0, 0x001b); + /* + * Release reset phy psgmii + */ + qca8075_phy_reg_write(0, 5, 0x0, 0x005b); + for (i = 0; i < QCA8075_MAX_TRIES; i++) { + status = qca8075_phy_mmd_read(0, 5, 1, 0x28); + if(status & 0x1) + break; + mdelay(10); + } + if (i >= QCA8075_MAX_TRIES) + printf("qca8075 PSGMII PLL_VCO_CALIB Not Ready\n"); + mdelay(50); + /* + * Check qca8075 psgmii calibration done end. + * Freeze phy psgmii RX CDR + */ + qca8075_phy_reg_write(0, 5, 0x1a, 0x2230); + + ess_reset(); + /* + * Check ipq40xx psgmii calibration done start + */ + for (i = 0; i < QCA8075_MAX_TRIES; i++) { + status = readl(0x000980A0); + if (status & 0x1) + break; + mdelay(10); + } + if (i >= QCA8075_MAX_TRIES) + printf("PSGMII PLL_VCO_CALIB Not Ready\n"); + mdelay(50); + /* + * Check ipq40xx psgmii calibration done end. + * Relesae phy psgmii RX CDR + */ + qca8075_phy_reg_write(0, 5, 0x1a, 0x3230); + /* + * Release phy psgmii RX 20bit + */ + qca8075_phy_reg_write(0, 5, 0x0, 0x005f); + mdelay(200); +} + +void psgmii_self_test(void) +{ + int i, phy, j; + u32 value; + u32 phy_t_status; + u16 status; + u32 tx_counter_ok, tx_counter_error; + u32 rx_counter_ok, rx_counter_error; + u32 tx_counter_ok_high16; + u32 rx_counter_ok_high16; + u32 tx_ok, rx_ok; + + /* + * Switch to access MII reg for copper + */ + qca8075_phy_reg_write(0, 4, 0x1f, 0x8500); + for (phy = 0; phy < 5; phy++) { + /* + * Enable phy mdio broadcast write + */ + qca8075_phy_mmd_write(0, phy, 7, 0x8028, 0x801f); + } + /* + * Force no link by power down + */ + qca8075_phy_reg_write(0, 0x1f, 0x0, 0x1840); + /* + * Packet number + */ + qca8075_phy_mmd_write(0, 0x1f, 7, 0x8021, 0x3000); + qca8075_phy_mmd_write(0, 0x1f, 7, 0x8062, 0x05e0); + /* + * Fix mdi status + */ + qca8075_phy_reg_write(0, 0x1f, 0x10, 0x6800); + + for (i = 0; i < 100; i++) { + phy_t_status = 0; + for (phy = 0; phy < 5; phy++) { + value = readl(0xc00066c + (phy * 0xc)); + /* + * Enable mac loop back + */ + writel((value | (1 << 21)), (0xc00066c + (phy * 0xc))); + } + /* + * Phy single test + */ + for (phy = 0; phy < 5; phy++) { + /* + * Enable loopback + */ + qca8075_phy_reg_write(0, phy, 0x0, 0x9000); + qca8075_phy_reg_write(0, phy, 0x0, 0x4140); + /* + * Check link + */ + j = 0; + while (j < 100) { + status = qca8075_phy_reg_read(0, phy, 0x11); + if (status & (1 << 10)) + break; + mdelay(10); + j++; + } + /* + * Enable check + */ + qca8075_phy_mmd_write(0, phy, 7, 0x8029, 0x0000); + qca8075_phy_mmd_write(0, phy, 7, 0x8029, 0x0003); + /* + * Start traffic + */ + qca8075_phy_mmd_write(0, phy, 7, 0x8020, 0xa000); + mdelay(200); + /* + * check counter + */ + tx_counter_ok = qca8075_phy_mmd_read(0, phy, 7, 0x802e); + tx_counter_ok_high16 = qca8075_phy_mmd_read(0, phy, 7, 0x802d); + tx_counter_error = qca8075_phy_mmd_read(0, phy, 7, 0x802f); + rx_counter_ok = qca8075_phy_mmd_read(0, phy, 7, 0x802b); + rx_counter_ok_high16 = qca8075_phy_mmd_read(0, phy, 7, 0x802a); + rx_counter_error = qca8075_phy_mmd_read(0, phy, 7, 0x802c); + tx_ok = tx_counter_ok + (tx_counter_ok_high16 << 16); + rx_ok = rx_counter_ok + (rx_counter_ok_high16 << 16); + /* + * Success + */ + if((tx_ok == 0x3000) && (tx_counter_error == 0)) { + phy_t_status &= (~(1 << phy)); + } else { + phy_t_status |= (1 << phy); + } + /* + * Power down + */ + qca8075_phy_reg_write(0, phy, 0x0, 0x1840); + } + /* + * Reset 5-phy + */ + qca8075_phy_reg_write(0, 0x1f, 0x0, 0x9000); + /* + * Enable 5-phy loopback + */ + qca8075_phy_reg_write(0, 0x1f, 0x0, 0x4140); + /* + * check link + */ + j = 0; + while (j < 100) { + for (phy = 0; phy < 5; phy++) { + status = qca8075_phy_reg_read(0, phy, 0x11); + if (!(status & (1 << 10))) + break; + } + if (phy >= 5) + break; + mdelay(10); + j++; + } + /* + * Enable check + */ + qca8075_phy_mmd_write(0, 0x1f, 7, 0x8029, 0x0000); + qca8075_phy_mmd_write(0, 0x1f, 7, 0x8029, 0x0003); + /* + * Start traffic + */ + qca8075_phy_mmd_write(0, 0x1f, 7, 0x8020, 0xa000); + mdelay(200); + for (phy = 0; phy < 5; phy++) { + /* + * Check counter + */ + tx_counter_ok = qca8075_phy_mmd_read(0, phy, 7, 0x802e); + tx_counter_ok_high16 = qca8075_phy_mmd_read(0, phy, 7, 0x802d); + tx_counter_error = qca8075_phy_mmd_read(0, phy, 7, 0x802f); + rx_counter_ok = qca8075_phy_mmd_read(0, phy, 7, 0x802b); + rx_counter_ok_high16 = qca8075_phy_mmd_read(0, phy, 7, 0x802a); + rx_counter_error = qca8075_phy_mmd_read(0, phy, 7, 0x802c); + tx_ok = tx_counter_ok + (tx_counter_ok_high16 << 16); + rx_ok = rx_counter_ok + (rx_counter_ok_high16 << 16); + debug("rx_ok: %d, tx_ok: %d", rx_ok, tx_ok); + debug("rx_counter_error: %d, tx_counter_error: %d", + rx_counter_error, tx_counter_error); + /* + * Success + */ + if ((tx_ok == 0x3000) && (tx_counter_error == 0)) { + phy_t_status &= (~(1 << (phy + 8))); + } else { + phy_t_status |= (1 << (phy + 8)); + } + } + if (phy_t_status) { + qca8075_ess_reset(); + } else { + break; + } + } + /* + * Configuration recover + */ + /* + * Packet number + */ + qca8075_phy_mmd_write(0, 0x1f, 7, 0x8021, 0x0); + /* + * Disable check + */ + qca8075_phy_mmd_write(0, 0x1f, 7, 0x8029, 0x0); + /* + * Disable traffic + */ + qca8075_phy_mmd_write(0, 0x1f, 7, 0x8020, 0x0); +} + +void clear_self_test_config(void) +{ + int phy = 0; + u32 value = 0; + + /* + * Disable phy internal loopback + */ + qca8075_phy_reg_write(0, 0x1f, 0x10, 0x6860); + qca8075_phy_reg_write(0, 0x1f, 0x0, 0x9040); + + for (phy = 0; phy < 5; phy++) { + value = readl(0xc00066c + (phy * 0xc)); + /* + * Disable mac loop back + */ + writel((value&(~(1 << 21))), (0xc00066c + (phy * 0xc))); + /* + * Disable phy mdio broadcast writei + */ + qca8075_phy_mmd_write(0, phy, 7, 0x8028, 0x001f); + } + +} + +int ipq40xx_qca8075_phy_init(struct ipq40xx_eth_dev *info) +{ + u16 phy_data; + u32 phy_id = 0; + struct phy_ops *qca8075_ops; + + qca8075_ops = (struct phy_ops *)malloc(sizeof(struct phy_ops)); + if (!qca8075_ops) + return -ENOMEM; + + qca8075_ops->phy_get_link_status = qca8075_phy_get_link_status; + qca8075_ops->phy_get_speed = qca8075_phy_get_speed; + qca8075_ops->phy_get_duplex = qca8075_phy_get_duplex; + info->ops = qca8075_ops; + + qca8075_id = phy_data = qca8075_phy_reg_read(0x0, 0x0, QCA8075_PHY_ID1); + printf ("PHY ID1: 0x%x\n", phy_data); + phy_data = qca8075_phy_reg_read(0x0, 0x0, QCA8075_PHY_ID2); + printf ("PHY ID2: 0x%x\n", phy_data); + qca8075_id = (qca8075_id << 16) | phy_data; + + if (qca8075_id == QCA8075_PHY_V1_0_5P) { + phy_data = qca8075_phy_mmd_read(0, PSGMII_ID, + QCA8075_PHY_MMD1_NUM, QCA8075_PSGMII_FIFI_CTRL); + phy_data &= 0xbfff; + qca8075_phy_mmd_write(0, PSGMII_ID, QCA8075_PHY_MMD1_NUM, + QCA8075_PSGMII_FIFI_CTRL, phy_data); + } + + /* + * Enable AZ transmitting ability + */ + qca8075_phy_mmd_write(0, PSGMII_ID, QCA8075_PHY_MMD1_NUM, + QCA8075_PSGMII_MODE_CTRL, + QCA8075_PHY_PSGMII_MODE_CTRL_ADJUST_VALUE); + + /* + * Enable phy power saving function by default + */ + if (qca8075_id == QCA8075_PHY_V1_1_2P) + phy_id = 3; + + if ((qca8075_id == QCA8075_PHY_V1_0_5P) || + (qca8075_id == QCA8075_PHY_V1_1_5P) || + (qca8075_id == QCA8075_PHY_V1_1_2P)) { + for (; phy_id < 5; phy_id++) { + qca8075_phy_set_8023az(0x0, phy_id, 0x1); + qca8075_phy_set_powersave(0x0, phy_id, 0x1); + qca8075_phy_set_hibernate(0x0, phy_id, 0x1); + } + } + + phy_data = qca8075_phy_mmd_read(0, 4, QCA8075_PHY_MMD3_NUM, 0x805a); + phy_data &= (~(1 << 1)); + qca8075_phy_mmd_write(0, 4, QCA8075_PHY_MMD3_NUM, 0x805a, phy_data); + + return 0; +} diff --git a/sources/uboot-be550/drivers/net/ipq40xx/ipq40xx_qca8075.h b/sources/uboot-be550/drivers/net/ipq40xx/ipq40xx_qca8075.h new file mode 100644 index 00000000..2d69336d --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq40xx/ipq40xx_qca8075.h @@ -0,0 +1,480 @@ +/* + * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. + + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. +*/ + +#ifndef _QCA8075_PHY_H_ +#define _QCA8075_PHY_H_ + +#define QCA8075_PHY_V1_0_5P 0x004DD0B0 +#define QCA8075_PHY_V1_1_5P 0x004DD0B1 +#define QCA8075_PHY_V1_1_2P 0x004DD0B2 + +#define QCA8075_PHY_CONTROL 0 +#define QCA8075_PHY_STATUS 1 +#define QCA8075_PHY_ID1 2 +#define QCA8075_PHY_ID2 3 +#define QCA8075_AUTONEG_ADVERT 4 +#define QCA8075_LINK_PARTNER_ABILITY 5 +#define QCA8075_AUTONEG_EXPANSION 6 +#define QCA8075_NEXT_PAGE_TRANSMIT 7 +#define QCA8075_LINK_PARTNER_NEXT_PAGE 8 +#define QCA8075_1000BASET_CONTROL 9 +#define QCA8075_1000BASET_STATUS 10 +#define QCA8075_MMD_CTRL_REG 13 +#define QCA8075_MMD_DATA_REG 14 +#define QCA8075_EXTENDED_STATUS 15 +#define QCA8075_PHY_SPEC_CONTROL 16 +#define QCA8075_PHY_SPEC_STATUS 17 +#define QCA8075_PHY_INTR_MASK 18 +#define QCA8075_PHY_INTR_STATUS 19 +#define QCA8075_PHY_CDT_CONTROL 22 +#define QCA8075_PHY_CDT_STATUS 28 +#define QCA8075_DEBUG_PORT_ADDRESS 29 +#define QCA8075_DEBUG_PORT_DATA 30 +#define COMBO_PHY_ID 4 +#define PSGMII_ID 5 + +#define QCA8075_DEBUG_PHY_HIBERNATION_CTRL 0xb +#define QCA8075_DEBUG_PHY_POWER_SAVING_CTRL 0x29 +#define QCA8075_PHY_MMD7_ADDR_8023AZ_EEE_CTRL 0x3c +#define QCA8075_PHY_MMD3_ADDR_REMOTE_LOOPBACK_CTRL 0x805a +#define QCA8075_PHY_MMD3_WOL_MAGIC_MAC_CTRL1 0x804a +#define QCA8075_PHY_MMD3_WOL_MAGIC_MAC_CTRL2 0x804b +#define QCA8075_PHY_MMD3_WOL_MAGIC_MAC_CTRL3 0x804c +#define QCA8075_PHY_MMD3_WOL_CTRL 0x8012 + +#define QCA8075_PSGMII_FIFI_CTRL 0x6e +#define QCA8075_PSGMII_CALIB_CTRL 0x27 +#define QCA8075_PSGMII_MODE_CTRL 0x6d +#define QCA8075_PHY_PSGMII_MODE_CTRL_ADJUST_VALUE 0x220c + +#define QCA8075_PHY_MMD7_NUM 7 +#define QCA8075_PHY_MMD3_NUM 3 +#define QCA8075_PHY_MMD1_NUM 1 + +#define QCA8075_PHY_SGMII_STATUS 0x1a /* sgmii_status Register */ +#define QCA8075_PHY4_AUTO_SGMII_SELECT 0x40 +#define QCA8075_PHY4_AUTO_COPPER_SELECT 0x20 +#define QCA8075_PHY4_AUTO_BX1000_SELECT 0x10 +#define QCA8075_PHY4_AUTO_FX100_SELECT 0x8 + +#define QCA8075_PHY_CHIP_CONFIG 0x1f /* Chip Configuration Register */ +#define BT_BX_SG_REG_SELECT BIT_15 +#define BT_BX_SG_REG_SELECT_OFFSET 15 +#define BT_BX_SG_REG_SELECT_LEN 1 +#define QCA8075_SG_BX_PAGES 0x0 +#define QCA8075_SG_COPPER_PAGES 0x1 + +#define QCA8075_PHY_PSGMII_BASET 0x0 +#define QCA8075_PHY_PSGMII_BX1000 0x1 +#define QCA8075_PHY_PSGMII_FX100 0x2 +#define QCA8075_PHY_PSGMII_AMDET 0x3 +#define QCA8075_PHY_SGMII_BASET 0x4 + +#define QCA8075_PHY4_PREFER_FIBER 0x400 +#define PHY4_PREFER_COPPER 0x0 +#define PHY4_PREFER_FIBER 0x1 + +#define QCA8075_PHY4_FIBER_MODE_1000BX 0x100 +#define AUTO_100FX_FIBER 0x0 +#define AUTO_1000BX_FIBER 0x1 + +#define QCA8075_PHY_MDIX 0x0020 +#define QCA8075_PHY_MDIX_AUTO 0x0060 +#define QCA8075_PHY_MDIX_STATUS 0x0040 + +#define MODE_CFG_QUAL BIT_4 +#define MODE_CFG_QUAL_OFFSET 4 +#define MODE_CFG_QUAL_LEN 4 + +#define MODE_CFG BIT_0 +#define MODE_CFG_OFFSET 0 +#define MODE_CFG_LEN 4 + +#define QCA8075_PHY_MMD3_ADDR_8023AZ_CLD_CTRL 0x8007 +#define QCA8075_PHY_MMD3_ADDR_8023AZ_TIMER_CTRL 0x804e +#define QCA8075_PHY_MMD3_ADDR_CLD_CTRL5 0x8005 +#define QCA8075_PHY_MMD3_ADDR_CLD_CTRL3 0x8003 + +#define AZ_TIMER_CTRL_DEFAULT_VALUE 0x3062 +#define AZ_CLD_CTRL_DEFAULT_VALUE 0x83f6 +#define AZ_TIMER_CTRL_ADJUST_VALUE 0x7062 +#define AZ_CLD_CTRL_ADJUST_VALUE 0x8396 + + /*debug port */ +#define QCA8075_DEBUG_PORT_RGMII_MODE 18 +#define QCA8075_DEBUG_PORT_RGMII_MODE_EN 0x0008 + +#define QCA8075_DEBUG_PORT_RX_DELAY 0 +#define QCA8075_DEBUG_PORT_RX_DELAY_EN 0x8000 + +#define QCA8075_DEBUG_PORT_TX_DELAY 5 +#define QCA8075_DEBUG_PORT_TX_DELAY_EN 0x0100 + + /* PHY Registers Field */ + + /* Control Register fields offset:0 */ + /* bits 6,13: 10=1000, 01=100, 00=10 */ +#define QCA8075_CTRL_SPEED_MSB 0x0040 + + /* Collision test enable */ +#define QCA8075_CTRL_COLL_TEST_ENABLE 0x0080 + + /* FDX =1, half duplex =0 */ +#define QCA8075_CTRL_FULL_DUPLEX 0x0100 + + /* Restart auto negotiation */ +#define QCA8075_CTRL_RESTART_AUTONEGOTIATION 0x0200 + + /* Isolate PHY from MII */ +#define QCA8075_CTRL_ISOLATE 0x0400 + + /* Power down */ +#define QCA8075_CTRL_POWER_DOWN 0x0800 + + /* Auto Neg Enable */ +#define QCA8075_CTRL_AUTONEGOTIATION_ENABLE 0x1000 + + /* Local Loopback Enable */ +#define QCA8075_LOCAL_LOOPBACK_ENABLE 0x4000 + + /* bits 6,13: 10=1000, 01=100, 00=10 */ +#define QCA8075_CTRL_SPEED_LSB 0x2000 + + /* 0 = normal, 1 = loopback */ +#define QCA8075_CTRL_LOOPBACK 0x4000 +#define QCA8075_CTRL_SOFTWARE_RESET 0x8000 + +#define QCA8075_CTRL_SPEED_MASK 0x2040 +#define QCA8075_CTRL_SPEED_1000 0x0040 +#define QCA8075_CTRL_SPEED_100 0x2000 +#define QCA8075_CTRL_SPEED_10 0x0000 + +#define QCA8075_RESET_DONE(phy_control) \ + (((phy_control) & (QCA8075_CTRL_SOFTWARE_RESET)) == 0) + + /* Status Register fields offset:1 */ + /* Extended register capabilities */ +#define QCA8075_STATUS_EXTENDED_CAPS 0x0001 + + /* Jabber Detected */ +#define QCA8075_STATUS_JABBER_DETECT 0x0002 + + /* Link Status 1 = link */ +#define QCA8075_STATUS_LINK_STATUS_UP 0x0004 + + /* Auto Neg Capable */ +#define QCA8075_STATUS_AUTONEG_CAPS 0x0008 + + /* Remote Fault Detect */ +#define QCA8075_STATUS_REMOTE_FAULT 0x0010 + + /* Auto Neg Complete */ +#define QCA8075_STATUS_AUTO_NEG_DONE 0x0020 + + /* Preamble may be suppressed */ +#define QCA8075_STATUS_PREAMBLE_SUPPRESS 0x0040 + + /* Ext. status info in Reg 0x0F */ +#define QCA8075_STATUS_EXTENDED_STATUS 0x0100 + + /* 100T2 Half Duplex Capable */ +#define QCA8075_STATUS_100T2_HD_CAPS 0x0200 + + /* 100T2 Full Duplex Capable */ +#define QCA8075_STATUS_100T2_FD_CAPS 0x0400 + + /* 10T Half Duplex Capable */ +#define QCA8075_STATUS_10T_HD_CAPS 0x0800 + + /* 10T Full Duplex Capable */ +#define QCA8075_STATUS_10T_FD_CAPS 0x1000 + + /* 100X Half Duplex Capable */ +#define QCA8075_STATUS_100X_HD_CAPS 0x2000 + + /* 100X Full Duplex Capable */ +#define QCA8075_STATUS_100X_FD_CAPS 0x4000 + + /* 100T4 Capable */ +#define QCA8075_STATUS_100T4_CAPS 0x8000 + + /* extended status register capabilities */ + +#define QCA8075_STATUS_1000T_HD_CAPS 0x1000 + +#define QCA8075_STATUS_1000T_FD_CAPS 0x2000 + +#define QCA8075_STATUS_1000X_HD_CAPS 0x4000 + +#define QCA8075_STATUS_1000X_FD_CAPS 0x8000 + +#define QCA8075_AUTONEG_DONE(ip_phy_status) \ + (((ip_phy_status) & (QCA8075_STATUS_AUTO_NEG_DONE)) == \ + (QCA8075_STATUS_AUTO_NEG_DONE)) + + /* PHY identifier1 offset:2 */ +//Organizationally Unique Identifier bits 3:18 + + /* PHY identifier2 offset:3 */ +//Organizationally Unique Identifier bits 19:24 + + /* Auto-Negotiation Advertisement register. offset:4 */ + /* indicates IEEE 802.3 CSMA/CD */ +#define QCA8075_ADVERTISE_SELECTOR_FIELD 0x0001 + + /* 10T Half Duplex Capable */ +#define QCA8075_ADVERTISE_10HALF 0x0020 + + /* 10T Full Duplex Capable */ +#define QCA8075_ADVERTISE_10FULL 0x0040 + + /* 100TX Half Duplex Capable */ +#define QCA8075_ADVERTISE_100HALF 0x0080 + + /* 100TX Full Duplex Capable */ +#define QCA8075_ADVERTISE_100FULL 0x0100 + + /* 100T4 Capable */ +#define QCA8075_ADVERTISE_100T4 0x0200 + + /* Pause operation desired */ +#define QCA8075_ADVERTISE_PAUSE 0x0400 + + /* Asymmetric Pause Direction bit */ +#define QCA8075_ADVERTISE_ASYM_PAUSE 0x0800 + + /* Remote Fault detected */ +#define QCA8075_ADVERTISE_REMOTE_FAULT 0x2000 + + /* Next Page ability supported */ +#define QCA8075_ADVERTISE_NEXT_PAGE 0x8000 + + /* 100TX Half Duplex Capable */ +#define QCA8075_ADVERTISE_1000HALF 0x0100 + + /* 100TX Full Duplex Capable */ +#define QCA8075_ADVERTISE_1000FULL 0x0200 + +#define QCA8075_ADVERTISE_ALL \ + (QCA8075_ADVERTISE_10HALF | QCA8075_ADVERTISE_10FULL | \ + QCA8075_ADVERTISE_100HALF | QCA8075_ADVERTISE_100FULL | \ + QCA8075_ADVERTISE_1000FULL) + +#define QCA8075_ADVERTISE_MEGA_ALL \ + (QCA8075_ADVERTISE_10HALF | QCA8075_ADVERTISE_10FULL | \ + QCA8075_ADVERTISE_100HALF | QCA8075_ADVERTISE_100FULL) + +#define QCA8075_BX_ADVERTISE_1000FULL 0x0020 +#define QCA8075_BX_ADVERTISE_1000HALF 0x0040 +#define QCA8075_BX_ADVERTISE_PAUSE 0x0080 +#define QCA8075_BX_ADVERTISE_ASYM_PAUSE 0x0100 + +#define QCA8075_BX_ADVERTISE_ALL \ + (QCA8075_BX_ADVERTISE_ASYM_PAUSE | QCA8075_BX_ADVERTISE_PAUSE | \ + QCA8075_BX_ADVERTISE_1000HALF | QCA8075_BX_ADVERTISE_1000FULL) + + /* Link Partner ability offset:5 */ + /* Same as advertise selector */ +#define QCA8075_LINK_SLCT 0x001f + + /* Can do 10mbps half-duplex */ +#define QCA8075_LINK_10BASETX_HALF_DUPLEX 0x0020 + + /* Can do 10mbps full-duplex */ +#define QCA8075_LINK_10BASETX_FULL_DUPLEX 0x0040 + + /* Can do 100mbps half-duplex */ +#define QCA8075_LINK_100BASETX_HALF_DUPLEX 0x0080 + + /* Can do 100mbps full-duplex */ +#define QCA8075_LINK_100BASETX_FULL_DUPLEX 0x0100 + + /* Can do 1000mbps full-duplex */ +#define QCA8075_LINK_1000BASETX_FULL_DUPLEX 0x0800 + + /* Can do 1000mbps half-duplex */ +#define QCA8075_LINK_1000BASETX_HALF_DUPLEX 0x0400 + + /* 100BASE-T4 */ +#define QCA8075_LINK_100BASE4 0x0200 + + /* PAUSE */ +#define QCA8075_LINK_PAUSE 0x0400 + + /* Asymmetrical PAUSE */ +#define QCA8075_LINK_ASYPAUSE 0x0800 + + /* Link partner faulted */ +#define QCA8075_LINK_RFAULT 0x2000 + + /* Link partner acked us */ +#define QCA8075_LINK_LPACK 0x4000 + + /* Next page bit */ +#define QCA8075_LINK_NPAGE 0x8000 + + /* Auto-Negotiation Expansion Register offset:6 */ + + /* Next Page Transmit Register offset:7 */ + + /* Link partner Next Page Register offset:8 */ + + /* 1000BASE-T Control Register offset:9 */ + /* Advertise 1000T HD capability */ +#define QCA8075_CTL_1000T_HD_CAPS 0x0100 + + /* Advertise 1000T FD capability */ +#define QCA8075_CTL_1000T_FD_CAPS 0x0200 + + /* 1=Repeater/switch device port 0=DTE device */ +#define QCA8075_CTL_1000T_REPEATER_DTE 0x0400 + + /* 1=Configure PHY as Master 0=Configure PHY as Slave */ +#define QCA8075_CTL_1000T_MS_VALUE 0x0800 + + /* 1=Master/Slave manual config value 0=Automatic Master/Slave config */ +#define QCA8075_CTL_1000T_MS_ENABLE 0x1000 + + /* Normal Operation */ +#define QCA8075_CTL_1000T_TEST_MODE_NORMAL 0x0000 + + /* Transmit Waveform test */ +#define QCA8075_CTL_1000T_TEST_MODE_1 0x2000 + + /* Master Transmit Jitter test */ +#define QCA8075_CTL_1000T_TEST_MODE_2 0x4000 + + /* Slave Transmit Jitter test */ +#define QCA8075_CTL_1000T_TEST_MODE_3 0x6000 + + /* Transmitter Distortion test */ +#define QCA8075_CTL_1000T_TEST_MODE_4 0x8000 +#define QCA8075_CTL_1000T_SPEED_MASK 0x0300 +#define QCA8075_CTL_1000T_DEFAULT_CAP_MASK 0x0300 + + /* 1000BASE-T Status Register offset:10 */ + /* LP is 1000T HD capable */ +#define QCA8075_STATUS_1000T_LP_HD_CAPS 0x0400 + + /* LP is 1000T FD capable */ +#define QCA8075_STATUS_1000T_LP_FD_CAPS 0x0800 + + /* Remote receiver OK */ +#define QCA8075_STATUS_1000T_REMOTE_RX_STATUS 0x1000 + + /* Local receiver OK */ +#define QCA8075_STATUS_1000T_LOCAL_RX_STATUS 0x2000 + + /* 1=Local TX is Master, 0=Slave */ +#define QCA8075_STATUS_1000T_MS_CONFIG_RES 0x4000 + +#define QCA8075_STATUS_1000T_MS_CONFIG_FAULT 0x8000 + + /* Master/Slave config fault */ +#define QCA8075_STATUS_1000T_REMOTE_RX_STATUS_SHIFT 12 +#define QCA8075_STATUS_1000T_LOCAL_RX_STATUS_SHIFT 13 + + /* Phy Specific Control Register offset:16 */ + /* 1=Jabber Function disabled */ +#define QCA8075_CTL_JABBER_DISABLE 0x0001 + + /* 1=Polarity Reversal enabled */ +#define QCA8075_CTL_POLARITY_REVERSAL 0x0002 + + /* 1=SQE Test enabled */ +#define QCA8075_CTL_SQE_TEST 0x0004 +#define QCA8075_CTL_MAC_POWERDOWN 0x0008 + + /* 1=CLK125 low, 0=CLK125 toggling + #define QCA8075_CTL_CLK125_DISABLE 0x0010 + */ + /* MDI Crossover Mode bits 6:5 */ + /* Manual MDI configuration */ +#define QCA8075_CTL_MDI_MANUAL_MODE 0x0000 + + /* Manual MDIX configuration */ +#define QCA8075_CTL_MDIX_MANUAL_MODE 0x0020 + + /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */ +#define QCA8075_CTL_AUTO_X_1000T 0x0040 + + /* Auto crossover enabled all speeds */ +#define QCA8075_CTL_AUTO_X_MODE 0x0060 + + /* 1=Enable Extended 10BASE-T distance + * (Lower 10BASE-T RX Threshold) + * 0=Normal 10BASE-T RX Threshold */ +#define QCA8075_CTL_10BT_EXT_DIST_ENABLE 0x0080 + + /* 1=5-Bit interface in 100BASE-TX + * 0=MII interface in 100BASE-TX */ +#define QCA8075_CTL_MII_5BIT_ENABLE 0x0100 + + /* 1=Scrambler disable */ +#define QCA8075_CTL_SCRAMBLER_DISABLE 0x0200 + + /* 1=Force link good */ +#define QCA8075_CTL_FORCE_LINK_GOOD 0x0400 + + /* 1=Assert CRS on Transmit */ +#define QCA8075_CTL_ASSERT_CRS_ON_TX 0x0800 + +#define QCA8075_CTL_POLARITY_REVERSAL_SHIFT 1 +#define QCA8075_CTL_AUTO_X_MODE_SHIFT 5 +#define QCA8075_CTL_10BT_EXT_DIST_ENABLE_SHIFT 7 + + + /* Phy Specific status fields offset:17 */ + /* 1=Speed & Duplex resolved */ +#define QCA8075_STATUS_LINK_PASS 0x0400 +#define QCA8075_STATUS_RESOVLED 0x0800 + + /* 1=Duplex 0=Half Duplex */ +#define QCA8075_STATUS_FULL_DUPLEX 0x2000 + + /* Speed, bits 14:15 */ +#define QCA8075_STATUS_SPEED 0xC000 +#define QCA8075_STATUS_SPEED_MASK 0xC000 + + /* 00=10Mbs */ +#define QCA8075_STATUS_SPEED_10MBS 0x0000 + + /* 01=100Mbs */ +#define QCA8075_STATUS_SPEED_100MBS 0x4000 + + /* 10=1000Mbs */ +#define QCA8075_STATUS_SPEED_1000MBS 0x8000 +#define QCA8075_SPEED_DUPLEX_RESOVLED(phy_status) \ + (((phy_status) & \ + (QCA8075_STATUS_RESOVLED)) == \ + (QCA8075_STATUS_RESOVLED)) + + /*phy debug port1 register offset:29 */ + /*phy debug port2 register offset:30 */ + + /*QCA8075 interrupt flag */ +#define QCA8075_INTR_SPEED_CHANGE 0x4000 +#define QCA8075_INTR_DUPLEX_CHANGE 0x2000 +#define QCA8075_INTR_STATUS_UP_CHANGE 0x0400 +#define QCA8075_INTR_STATUS_DOWN_CHANGE 0x0800 +#define QCA8075_INTR_BX_FX_STATUS_DOWN_CHANGE 0x0100 +#define QCA8075_INTR_BX_FX_STATUS_UP_CHANGE 0x0080 +#define QCA8075_INTR_MEDIA_STATUS_CHANGE 0x1000 +#define QCA8075_INTR_WOL 0x0001 +#define QCA8075_INTR_POE 0x0002 + +#define RUN_CDT 0x8000 +#define CABLE_LENGTH_UNIT 0x0400 +#define QCA8075_MAX_TRIES 100 + +#endif /* _QCA8075_PHY_H_ */ diff --git a/sources/uboot-be550/drivers/net/ipq5018/athrs17_phy.c b/sources/uboot-be550/drivers/net/ipq5018/athrs17_phy.c new file mode 100644 index 00000000..dbc514f0 --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq5018/athrs17_phy.c @@ -0,0 +1,328 @@ +/* + * Copyright (c) 2015-2016, 2020 The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Manage the atheros ethernet PHY. + * + * All definitions in this file are operating system independent! + */ + +#include +#include + +/* + * Externel Common mdio read, PHY Name : IPQ MDIO1 + */ + +extern int ipq_mdio_write(int mii_id, + int regnum, u16 value); +extern int ipq_mdio_read(int mii_id, + int regnum, ushort *data); + +/****************************************************************************** + * FUNCTION DESCRIPTION: Read switch internal register. + * Switch internal register is accessed through the + * MDIO interface. MDIO access is only 16 bits wide so + * it needs the two time access to complete the internal + * register access. + * INPUT : register address + * OUTPUT : Register value + * + *****************************************************************************/ +static uint32_t +athrs17_reg_read(uint32_t reg_addr) +{ + uint32_t reg_word_addr; + uint32_t phy_addr, reg_val; + uint16_t phy_val; + uint16_t tmp_val; + uint8_t phy_reg; + + /* change reg_addr to 16-bit word address, 32-bit aligned */ + reg_word_addr = (reg_addr & 0xfffffffc) >> 1; + + /* configure register high address */ + phy_addr = 0x18; + phy_reg = 0x0; + phy_val = (uint16_t) ((reg_word_addr >> 8) & 0x1ff); /* bit16-8 of reg address */ + ipq_mdio_write(phy_addr, phy_reg, phy_val); + /* + * For some registers such as MIBs, since it is read/clear, we should + * read the lower 16-bit register then the higher one + */ + + /* read register in lower address */ + phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */ + phy_reg = (uint8_t) (reg_word_addr & 0x1f); /* bit4-0 of reg address */ + ipq_mdio_read(phy_addr, phy_reg, &phy_val); + + /* read register in higher address */ + reg_word_addr++; + phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */ + phy_reg = (uint8_t) (reg_word_addr & 0x1f); /* bit4-0 of reg address */ + ipq_mdio_read(phy_addr, phy_reg, &tmp_val); + reg_val = (tmp_val << 16 | phy_val); + + return reg_val; +} + +/****************************************************************************** + * FUNCTION DESCRIPTION: Write switch internal register. + * Switch internal register is accessed through the + * MDIO interface. MDIO access is only 16 bits wide so + * it needs the two time access to complete the internal + * register access. + * INPUT : register address, value to be written + * OUTPUT : NONE + * + *****************************************************************************/ +static void +athrs17_reg_write(uint32_t reg_addr, uint32_t reg_val) +{ + uint32_t reg_word_addr; + uint32_t phy_addr; + uint16_t phy_val; + uint8_t phy_reg; + + /* change reg_addr to 16-bit word address, 32-bit aligned */ + reg_word_addr = (reg_addr & 0xfffffffc) >> 1; + + /* configure register high address */ + phy_addr = 0x18; + phy_reg = 0x0; + phy_val = (uint16_t) ((reg_word_addr >> 8) & 0x1ff); /* bit16-8 of reg address */ + ipq_mdio_write(phy_addr, phy_reg, phy_val); + + /* + * For some registers such as ARL and VLAN, since they include BUSY bit + * in lower address, we should write the higher 16-bit register then the + * lower one + */ + + /* read register in higher address */ + reg_word_addr++; + phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */ + phy_reg = (uint8_t) (reg_word_addr & 0x1f); /* bit4-0 of reg address */ + phy_val = (uint16_t) ((reg_val >> 16) & 0xffff); + ipq_mdio_write(phy_addr, phy_reg, phy_val); + + /* write register in lower address */ + reg_word_addr--; + phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */ + phy_reg = (uint8_t) (reg_word_addr & 0x1f); /* bit4-0 of reg address */ + phy_val = (uint16_t) (reg_val & 0xffff); + ipq_mdio_write(phy_addr, phy_reg, phy_val); +} + +/********************************************************************* + * FUNCTION DESCRIPTION: V-lan configuration given by Switch team + Vlan 1:PHY0,1,2,3 and Mac 6 of s17c + Vlan 2:PHY4 and Mac 0 of s17c + * INPUT : NONE + * OUTPUT: NONE + *********************************************************************/ +void athrs17_vlan_config(void) +{ + athrs17_reg_write(S17_P0LOOKUP_CTRL_REG, 0x00140020); + athrs17_reg_write(S17_P0VLAN_CTRL0_REG, 0x20001); + + athrs17_reg_write(S17_P1LOOKUP_CTRL_REG, 0x0014005c); + athrs17_reg_write(S17_P1VLAN_CTRL0_REG, 0x10001); + + athrs17_reg_write(S17_P2LOOKUP_CTRL_REG, 0x0014005a); + athrs17_reg_write(S17_P2VLAN_CTRL0_REG, 0x10001); + + athrs17_reg_write(S17_P3LOOKUP_CTRL_REG, 0x00140056); + athrs17_reg_write(S17_P3VLAN_CTRL0_REG, 0x10001); + + athrs17_reg_write(S17_P4LOOKUP_CTRL_REG, 0x0014004e); + athrs17_reg_write(S17_P4VLAN_CTRL0_REG, 0x10001); + + athrs17_reg_write(S17_P5LOOKUP_CTRL_REG, 0x00140001); + athrs17_reg_write(S17_P5VLAN_CTRL0_REG, 0x20001); + + athrs17_reg_write(S17_P6LOOKUP_CTRL_REG, 0x0014001e); + athrs17_reg_write(S17_P6VLAN_CTRL0_REG, 0x10001); + printf("%s ...done\n", __func__); +} + +/******************************************************************* +* FUNCTION DESCRIPTION: Reset S17 register +* INPUT: NONE +* OUTPUT: NONE +*******************************************************************/ +int athrs17_init_switch(void) +{ + uint32_t data; + uint32_t i = 0; + + /* Reset the switch before initialization */ + athrs17_reg_write(S17_MASK_CTRL_REG, S17_MASK_CTRL_SOFT_RET); + do { + udelay(10); + data = athrs17_reg_read(S17_MASK_CTRL_REG); + i++; + if (i == 10){ + printf("QCA_8337: Failed to reset\n"); + return -1; + } + } while (data & S17_MASK_CTRL_SOFT_RET); + + i = 0; + + do { + udelay(10); + data = athrs17_reg_read(S17_GLOBAL_INT0_REG); + i++; + if (i == 10) + return -1; + } while ((data & S17_GLOBAL_INITIALIZED_STATUS) != S17_GLOBAL_INITIALIZED_STATUS); + + return 0; +} + +/********************************************************************* + * FUNCTION DESCRIPTION: Configure S17 register + * INPUT : NONE + * OUTPUT: NONE + *********************************************************************/ +void athrs17_reg_init(ipq_gmac_board_cfg_t *gmac_cfg) +{ + athrs17_reg_write(S17_MAC_PWR_REG, gmac_cfg->mac_pwr); + + athrs17_reg_write(S17_P0STATUS_REG, (S17_SPEED_1000M | + S17_TXMAC_EN | + S17_RXMAC_EN | + S17_DUPLEX_FULL)); + + athrs17_reg_write(S17_GLOFW_CTRL1_REG, (S17_IGMP_JOIN_LEAVE_DPALL | + S17_BROAD_DPALL | + S17_MULTI_FLOOD_DPALL | + S17_UNI_FLOOD_DPALL)); + + athrs17_reg_write(S17_P5PAD_MODE_REG, S17_MAC0_RGMII_RXCLK_DELAY); + + athrs17_reg_write(S17_P0PAD_MODE_REG, (S17_MAC0_RGMII_EN | + S17_MAC0_RGMII_TXCLK_DELAY | + S17_MAC0_RGMII_RXCLK_DELAY | + (0x1 << S17_MAC0_RGMII_TXCLK_SHIFT) | + (0x2 << S17_MAC0_RGMII_RXCLK_SHIFT))); + + printf("%s: complete\n", __func__); +} + +/********************************************************************* + * FUNCTION DESCRIPTION: Configure S17 register + * INPUT : NONE + * OUTPUT: NONE + *********************************************************************/ +void athrs17_reg_init_lan(ipq_gmac_board_cfg_t *gmac_cfg) +{ + uint32_t reg_val; + + athrs17_reg_write(S17_P6STATUS_REG, (S17_SPEED_1000M | + S17_TXMAC_EN | + S17_RXMAC_EN | + S17_DUPLEX_FULL)); + + athrs17_reg_write(S17_MAC_PWR_REG, gmac_cfg->mac_pwr); + reg_val = athrs17_reg_read(S17_P6PAD_MODE_REG); + athrs17_reg_write(S17_P6PAD_MODE_REG, (reg_val | S17_MAC6_SGMII_EN)); + + athrs17_reg_write(S17_PWS_REG, 0x2613a0); + + athrs17_reg_write(S17_SGMII_CTRL_REG,(S17c_SGMII_EN_PLL | + S17c_SGMII_EN_RX | + S17c_SGMII_EN_TX | + S17c_SGMII_EN_SD | + S17c_SGMII_BW_HIGH | + S17c_SGMII_SEL_CLK125M | + S17c_SGMII_TXDR_CTRL_600mV | + S17c_SGMII_CDR_BW_8 | + S17c_SGMII_DIS_AUTO_LPI_25M | + S17c_SGMII_MODE_CTRL_SGMII_PHY | + S17c_SGMII_PAUSE_SG_TX_EN_25M | + S17c_SGMII_ASYM_PAUSE_25M | + S17c_SGMII_PAUSE_25M | + S17c_SGMII_HALF_DUPLEX_25M | + S17c_SGMII_FULL_DUPLEX_25M)); + + athrs17_reg_write(S17_MODULE_EN_REG, S17_MIB_COUNTER_ENABLE); +} + +struct athrs17_regmap { + uint32_t start; + uint32_t end; +}; + +struct athrs17_regmap regmap[] = { + { 0x000, 0x0e4 }, + { 0x100, 0x168 }, + { 0x200, 0x270 }, + { 0x400, 0x454 }, + { 0x600, 0x718 }, + { 0x800, 0xb70 }, + { 0xC00, 0xC80 }, + { 0x1100, 0x11a7 }, + { 0x1200, 0x12a7 }, + { 0x1300, 0x13a7 }, + { 0x1400, 0x14a7 }, + { 0x1600, 0x16a7 }, +}; + +int do_ar8xxx_dump(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { + int i; + + for (i = 0; i < ARRAY_SIZE(regmap); i++) { + uint32_t reg; + struct athrs17_regmap *section = ®map[i]; + + for (reg = section->start; reg <= section->end; reg += sizeof(uint32_t)) { + uint32_t val = athrs17_reg_read(reg); + printf("%03zx: %08zx\n", reg, val); + } + } + + return 0; +}; +U_BOOT_CMD( + ar8xxx_dump, 1, 1, do_ar8xxx_dump, + "Dump ar8xxx registers", + "\n - print all ar8xxx registers\n" +); + +/********************************************************************* + * + * FUNCTION DESCRIPTION: This function invokes RGMII, + * SGMII switch init routines. + * INPUT : ipq_gmac_board_cfg_t * + * OUTPUT: NONE + * +**********************************************************************/ +int ipq_athrs17_init(ipq_gmac_board_cfg_t *gmac_cfg) +{ + int ret; + + if (gmac_cfg == NULL) + return -1; + + ret = athrs17_init_switch(); + if (ret != -1) { + athrs17_reg_init(gmac_cfg); + athrs17_reg_init_lan(gmac_cfg); + athrs17_vlan_config(); + printf ("S17c init done\n"); + } + + return ret; +} diff --git a/sources/uboot-be550/drivers/net/ipq5018/ipq5018_gmac.c b/sources/uboot-be550/drivers/net/ipq5018/ipq5018_gmac.c new file mode 100644 index 00000000..e45a680b --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq5018/ipq5018_gmac.c @@ -0,0 +1,915 @@ +/* +* Copyright (c) 2019-2021 The Linux Foundation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 and +* only version 2 as published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "ipq_phy.h" +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define ipq_info printf +#define ipq_dbg printf +#define DESC_SIZE (sizeof(ipq_gmac_desc_t)) +#define DESC_FLUSH_SIZE (((DESC_SIZE + (CONFIG_SYS_CACHELINE_SIZE - 1)) \ + / CONFIG_SYS_CACHELINE_SIZE) * \ + (CONFIG_SYS_CACHELINE_SIZE)) + +static struct ipq_eth_dev *ipq_gmac_macs[IPQ5018_GMAC_PORT]; + +uchar ipq_def_enetaddr[6] = {0x00, 0x11, 0x22, 0x33, 0x44, 0x55}; +phy_info_t *phy_info[IPQ5018_PHY_MAX] = {0}; + +extern int ipq_mdio_read(int mii_id, int regnum, ushort *data); +extern int ipq_mdio_write(int mii_id, int regnum, u16 value); +extern int ipq5018_mdio_write(int mii_id, int regnum, u16 value); +extern int ipq5018_mdio_read(int mii_id, int regnum, ushort *data); +extern int ipq_qca8033_phy_init(struct phy_ops **ops, u32 phy_id); +extern int ipq_qca8081_phy_init(struct phy_ops **ops, u32 phy_id); +extern int ipq_gephy_phy_init(struct phy_ops **ops, u32 phy_id); +extern int ipq_sw_mdio_init(const char *); +extern int ipq5018_sw_mdio_init(const char *); +extern void ppe_uniphy_mode_set(uint32_t mode, uint32_t phy_mode); +extern void uniphy_channel0_input_output_6_get(int mode, u32 gpio, u8 *status, + fal_port_speed_t *speed, + fal_port_duplex_t *duplex); +extern int ipq_athrs17_init(ipq_gmac_board_cfg_t *gmac_cfg); + +static int ipq_eth_wr_macaddr(struct eth_device *dev) +{ + struct ipq_eth_dev *priv = dev->priv; + struct eth_mac_regs *mac_p = (struct eth_mac_regs *)priv->mac_regs_p; + u32 macid_lo, macid_hi; + u8 *mac_id = &dev->enetaddr[0]; + + macid_lo = mac_id[0] + (mac_id[1] << 8) + + (mac_id[2] << 16) + (mac_id[3] << 24); + macid_hi = mac_id[4] + (mac_id[5] << 8); + + writel(macid_hi, &mac_p->macaddr0hi); + writel(macid_lo, &mac_p->macaddr0lo); + + return 0; +} + +static void ipq_mac_reset(struct eth_device *dev) +{ + struct ipq_eth_dev *priv = dev->priv; + struct eth_dma_regs *dma_reg = (struct eth_dma_regs *)priv->dma_regs_p; + u32 val; + + writel(DMAMAC_SRST, &dma_reg->busmode); + do { + udelay(10); + val = readl(&dma_reg->busmode); + } while (val & DMAMAC_SRST); + +} + +static void ipq_eth_mac_cfg(struct eth_device *dev) +{ + struct ipq_eth_dev *priv = dev->priv; + struct eth_mac_regs *mac_reg = (struct eth_mac_regs *)priv->mac_regs_p; + uint speed = 0; + uint ipq_mac_cfg = 0; + uint ipq_mac_framefilter = 0; + + ipq_mac_framefilter = PROMISCUOUS_MODE_ON; + + if (priv->mac_unit) { + if (priv->phy_type == QCA8081_1_1_PHY || priv->phy_type == QCA8033_PHY) + speed = priv->speed; + + ipq_mac_cfg |= (FRAME_BURST_ENABLE | JUMBO_FRAME_ENABLE | JABBER_DISABLE | + TX_ENABLE | RX_ENABLE | FULL_DUPLEX_ENABLE | speed); + + writel(ipq_mac_cfg, &mac_reg->conf); + } else { + ipq_mac_cfg |= (priv->speed | FULL_DUPLEX_ENABLE | FRAME_BURST_ENABLE | + TX_ENABLE | RX_ENABLE); + writel(ipq_mac_cfg, &mac_reg->conf); + } + + writel(ipq_mac_framefilter, &mac_reg->framefilt); + +} + +static void ipq_eth_dma_cfg(struct eth_device *dev) +{ + struct ipq_eth_dev *priv = dev->priv; + struct eth_dma_regs *dma_reg = (struct eth_dma_regs *)priv->dma_regs_p; + uint ipq_dma_bus_mode; + uint ipq_dma_op_mode; + + ipq_dma_op_mode = DmaStoreAndForward | DmaRxThreshCtrl128 | + DmaTxSecondFrame; + ipq_dma_bus_mode = DmaFixedBurstEnable | DmaBurstLength16 | + DmaDescriptorSkip0 | DmaDescriptor8Words | + DmaArbitPr; + + writel(ipq_dma_bus_mode, &dma_reg->busmode); + writel(ipq_dma_op_mode, &dma_reg->opmode); +} + +static void ipq_eth_flw_cntl_cfg(struct eth_device *dev) +{ + struct ipq_eth_dev *priv = dev->priv; + struct eth_mac_regs *mac_reg = (struct eth_mac_regs *)priv->mac_regs_p; + struct eth_dma_regs *dma_reg = (struct eth_dma_regs *)priv->dma_regs_p; + uint ipq_dma_flw_cntl; + uint ipq_mac_flw_cntl; + + ipq_dma_flw_cntl = DmaRxFlowCtrlAct3K | DmaRxFlowCtrlDeact4K | + DmaEnHwFlowCtrl; + ipq_mac_flw_cntl = GmacRxFlowControl | GmacTxFlowControl | 0xFFFF0000; + + setbits_le32(&dma_reg->opmode, ipq_dma_flw_cntl); + setbits_le32(&mac_reg->flowcontrol, ipq_mac_flw_cntl); +} + +static int ipq_gmac_alloc_fifo(int ndesc, ipq_gmac_desc_t **fifo) +{ + int i; + void *addr; + + addr = memalign((CONFIG_SYS_CACHELINE_SIZE), + (ndesc * DESC_FLUSH_SIZE)); + + for (i = 0; i < ndesc; i++) { + fifo[i] = (ipq_gmac_desc_t *)((unsigned long)addr + + (i * DESC_FLUSH_SIZE)); + if (fifo[i] == NULL) { + ipq_info("Can't allocate desc fifos\n"); + return -1; + } + } + return 0; +} + +static int ipq_gmac_rx_desc_setup(struct ipq_eth_dev *priv) +{ + struct eth_dma_regs *dma_reg = (struct eth_dma_regs *)priv->dma_regs_p; + ipq_gmac_desc_t *rxdesc; + int i; + + for (i = 0; i < NO_OF_RX_DESC; i++) { + rxdesc = priv->desc_rx[i]; + rxdesc->length |= ((ETH_MAX_FRAME_LEN << DescSize1Shift) & + DescSize1Mask); + rxdesc->buffer1 = virt_to_phys(net_rx_packets[i]); + rxdesc->data1 = (unsigned long)priv->desc_rx[(i + 1) % + NO_OF_RX_DESC]; + + rxdesc->extstatus = 0; + rxdesc->reserved1 = 0; + rxdesc->timestamplow = 0; + rxdesc->timestamphigh = 0; + rxdesc->status = DescOwnByDma; + + + flush_dcache_range((unsigned long)rxdesc, + (unsigned long)rxdesc + DESC_SIZE); + + } + /* Assign Descriptor base address to dmadesclist addr reg */ + writel((uint)priv->desc_rx[0], &dma_reg->rxdesclistaddr); + + return 0; +} + +static int ipq_gmac_tx_rx_desc_ring(struct ipq_eth_dev *priv) +{ + int i; + ipq_gmac_desc_t *desc; + + if (ipq_gmac_alloc_fifo(NO_OF_TX_DESC, priv->desc_tx)) + return -1; + + for (i = 0; i < NO_OF_TX_DESC; i++) { + desc = priv->desc_tx[i]; + memset(desc, 0, DESC_SIZE); + + desc->status = + (i == (NO_OF_TX_DESC - 1)) ? TxDescEndOfRing : 0; + + desc->status |= TxDescChain; + + desc->data1 = (unsigned long)priv->desc_tx[(i + 1) % + NO_OF_TX_DESC ]; + + flush_dcache_range((unsigned long)desc, + (unsigned long)desc + DESC_SIZE); + + } + + if (ipq_gmac_alloc_fifo(NO_OF_RX_DESC, priv->desc_rx)) + return -1; + + for (i = 0; i < NO_OF_RX_DESC; i++) { + desc = priv->desc_rx[i]; + memset(desc, 0, DESC_SIZE); + desc->length = + (i == (NO_OF_RX_DESC - 1)) ? RxDescEndOfRing : 0; + desc->length |= RxDescChain; + + desc->data1 = (unsigned long)priv->desc_rx[(i + 1) % + NO_OF_RX_DESC]; + + flush_dcache_range((unsigned long)desc, + (unsigned long)desc + DESC_SIZE); + + } + + priv->next_tx = 0; + priv->next_rx = 0; + + return 0; +} + +static inline void ipq_gmac_give_to_dma(ipq_gmac_desc_t *fr) +{ + fr->status |= DescOwnByDma; +} + +static inline u32 ipq_gmac_owned_by_dma(ipq_gmac_desc_t *fr) +{ + return (fr->status & DescOwnByDma); +} + +static inline u32 ipq_gmac_is_desc_empty(ipq_gmac_desc_t *fr) +{ + return ((fr->length & DescSize1Mask) == 0); +} + +static void ipq5018_gmac0_speed_clock_set(int speed_clock1, + int speed_clock2, int gmacid) +{ + int iTxRx; + uint32_t reg_value; + /* + * iTxRx indicates Tx and RX register + * 0 = Rx and 1 = Tx + */ + for (iTxRx = 0; iTxRx < 2; ++iTxRx){ + /* gcc port first clock divider */ + reg_value = 0; + reg_value = readl(GCC_GMAC0_RX_CFG_RCGR + + (iTxRx * 8) + (gmacid * 0x10)); + reg_value &= ~0x1f; + reg_value |= speed_clock1; + writel(reg_value, GCC_GMAC0_RX_CFG_RCGR + + (iTxRx * 8) + (gmacid * 0x10)); + /* gcc port second clock divider */ + reg_value = 0; + reg_value = readl(GCC_GMAC0_RX_MISC + + (iTxRx * 4) + (gmacid * 0x10)); + reg_value &= ~0xf; + reg_value |= speed_clock2; + writel(reg_value, GCC_GMAC0_RX_MISC + + (iTxRx * 4) + (gmacid * 0x10)); + /* update above clock configuration */ + reg_value = 0; + reg_value = readl(GCC_GMAC0_RX_CMD_RCGR + + (iTxRx * 8) + (gmacid * 0x10)); + reg_value &= ~0x1; + reg_value |= 0x1; + writel(reg_value, GCC_GMAC0_RX_CMD_RCGR + + (iTxRx * 8) + (gmacid * 0x10)); + } +} + +static void ipq5018_enable_gephy(void) +{ + uint32_t reg_val; + + reg_val = readl(GCC_GEPHY_RX_CBCR); + reg_val |= GCC_CBCR_CLK_ENABLE; + writel(reg_val, GCC_GEPHY_RX_CBCR); + mdelay(20); + + reg_val = readl(GCC_GEPHY_TX_CBCR); + reg_val |= GCC_CBCR_CLK_ENABLE; + writel(reg_val, GCC_GEPHY_TX_CBCR); + mdelay(20); +} + +static int ipq5018_s17c_Link_Update(struct ipq_eth_dev *priv) +{ + uint16_t phy_data; + int status = 1; + + for(int i = 0; + i < priv->gmac_board_cfg->switch_port_count; ++i){ + phy_data = ipq_mdio_read( + priv->gmac_board_cfg->switch_port_phy_address[i], + 0x11, + NULL); + + if (phy_data == 0x50) + continue; + + /* Atleast one port should be link up*/ + if (phy_data & LINK_UP) + status = 0; + + printf("Port%d %s ", i + 1, LINK(phy_data)); + + switch(SPEED(phy_data)){ + case SPEED_1000M: + printf("Speed :1000M "); + break; + case SPEED_100M: + printf("Speed :100M "); + break; + default: + printf("Speed :10M "); + } + + printf ("%s \n", DUPLEX(phy_data)); + } + return status; +} + +static int ipq5018_phy_link_update(struct eth_device *dev) +{ + struct ipq_eth_dev *priv = dev->priv; + u8 status = 1; + struct phy_ops *phy_get_ops; + fal_port_speed_t speed; + fal_port_duplex_t duplex; + char *lstatus[] = {"up", "Down"}; + char *dp[] = {"Half", "Full"}; + int speed_clock1 = 0, speed_clock2 = 0; + int mode = PORT_WRAPPER_SGMII0_RGMII4; + uint32_t phy_mode = 0x70; + + phy_get_ops = priv->ops; + + if (priv->ipq_swith) { + speed_clock1 = 1; + speed_clock2 = 0; + status = ipq5018_s17c_Link_Update(priv); + } + + if (priv->sfp_tx_gpio || phy_get_ops) { + if (phy_get_ops && + phy_get_ops->phy_get_link_status != NULL && + phy_get_ops->phy_get_speed != NULL && + phy_get_ops->phy_get_duplex != NULL){ + + status = phy_get_ops->phy_get_link_status(priv->mac_unit, + priv->phy_address); + phy_get_ops->phy_get_speed(priv->mac_unit, + priv->phy_address, &speed); + phy_get_ops->phy_get_duplex(priv->mac_unit, + priv->phy_address, &duplex); + } + + if (priv->sfp_tx_gpio) { + mode = priv->sfp_mode; + uniphy_channel0_input_output_6_get(priv->sfp_mode, + priv->sfp_rx_gpio, + &status, + &speed, &duplex); + } + + switch (speed) { + case FAL_SPEED_10: + speed_clock1 = 9; + speed_clock2 = 9; + priv->speed = MII_PORT_SELECT; + printf ("eth%d %s Speed :%d %s duplex\n", + priv->mac_unit, + lstatus[status], speed, + dp[duplex]); + break; + case FAL_SPEED_100: + priv->speed = MII_PORT_SELECT | FES_PORT_SPEED; + speed_clock1 = 9; + speed_clock2 = 0; + printf ("eth%d %s Speed :%d %s duplex\n", + priv->mac_unit, + lstatus[status], speed, + dp[duplex]); + break; + case FAL_SPEED_1000: + priv->speed = SGMII_PORT_SELECT; + speed_clock1 = 1; + speed_clock2 = 0; + if (priv->sfp_tx_gpio) + phy_mode = 0x30; + printf ("eth%d %s Speed :%d %s duplex\n", + priv->mac_unit, + lstatus[status], speed, + dp[duplex]); + break; + case FAL_SPEED_2500: + priv->speed = SGMII_PORT_SELECT; + mode = PORT_WRAPPER_SGMII_PLUS; + speed_clock1 = 1; + speed_clock2 = 0; + + if (priv->sfp_tx_gpio) + phy_mode = 0x50; + else + phy_mode = 0x30; + printf ("eth%d %s Speed :%d %s duplex\n", + priv->mac_unit, + lstatus[status], speed, + dp[duplex]); + break; + default: + printf("Unknown speed\n"); + break; + } + } + + if (status) { + /* No PHY link is alive */ + if (priv->ipq_swith == 0 && phy_get_ops == NULL) + printf("Link status/Get speed/Get duplex not mapped\n"); + return -1; + } + + if (priv->mac_unit){ + ppe_uniphy_mode_set(mode, phy_mode); + } else { + ipq5018_enable_gephy(); + } + + ipq5018_gmac0_speed_clock_set(speed_clock1, speed_clock2, priv->mac_unit); + + return 0; +} + +int ipq_eth_init(struct eth_device *dev, bd_t *this) +{ + struct ipq_eth_dev *priv = dev->priv; + struct eth_dma_regs *dma_reg = (struct eth_dma_regs *)priv->dma_regs_p; + u32 data; + + if(ipq5018_phy_link_update(dev) < 0) { + return -1; + } + + priv->next_rx = 0; + priv->next_tx = 0; + + ipq_mac_reset(dev); + ipq_eth_wr_macaddr(dev); + + /* DMA, MAC configuration for Synopsys GMAC */ + ipq_eth_dma_cfg(dev); + ipq_eth_mac_cfg(dev); + ipq_eth_flw_cntl_cfg(dev); + + /* clear all pending interrupts if any */ + data = readl(&dma_reg->status); + writel(data, &dma_reg->status); + + /* Setup Rx fifos and assign base address to */ + ipq_gmac_rx_desc_setup(priv); + + writel((uint)priv->desc_tx[0], &dma_reg->txdesclistaddr); + setbits_le32(&dma_reg->opmode, (RXSTART)); + setbits_le32(&dma_reg->opmode, (TXSTART)); + + return 1; +} + +static int ipq_eth_send(struct eth_device *dev, void *packet, int length) +{ + struct ipq_eth_dev *priv = dev->priv; + struct eth_dma_regs *dma_p = (struct eth_dma_regs *)priv->dma_regs_p; + ipq_gmac_desc_t *txdesc = priv->desc_tx[priv->next_tx]; + int i; + + invalidate_dcache_range((unsigned long)txdesc, + (unsigned long)txdesc + DESC_FLUSH_SIZE); + + /* Check if the dma descriptor is still owned by DMA */ + if (ipq_gmac_owned_by_dma(txdesc)) { + ipq_info("BUG: Tx descriptor is owned by DMA %p\n", txdesc); + return NETDEV_TX_BUSY; + } + + txdesc->length |= ((length <status |= (DescTxFirst | DescTxLast | DescTxIntEnable); + txdesc->buffer1 = virt_to_phys(packet); + ipq_gmac_give_to_dma(txdesc); + + flush_dcache_range((unsigned long)txdesc, + (unsigned long)txdesc + DESC_SIZE); + + flush_dcache_range((unsigned long)(txdesc->buffer1), + (unsigned long)(txdesc->buffer1) + PKTSIZE_ALIGN); + + /* Start the transmission */ + writel(POLL_DATA, &dma_p->txpolldemand); + + for (i = 0; i < MAX_WAIT; i++) { + + udelay(10); + + invalidate_dcache_range((unsigned long)txdesc, + (unsigned long)txdesc + DESC_FLUSH_SIZE); + + if (!ipq_gmac_owned_by_dma(txdesc)) + break; + } + + if (i == MAX_WAIT) { + ipq_info("Tx Timed out\n"); + } + + /* reset the descriptors */ + txdesc->status = (priv->next_tx == (NO_OF_TX_DESC - 1)) ? + TxDescEndOfRing : 0; + txdesc->status |= TxDescChain; + txdesc->length = 0; + txdesc->buffer1 = 0; + + priv->next_tx = (priv->next_tx + 1) % NO_OF_TX_DESC; + + txdesc->data1 = (unsigned long)priv->desc_tx[priv->next_tx]; + + + flush_dcache_range((unsigned long)txdesc, + (unsigned long)txdesc + DESC_SIZE); + + return 0; +} + +static int ipq_eth_recv(struct eth_device *dev) +{ + struct ipq_eth_dev *priv = dev->priv; + struct eth_dma_regs *dma_p = (struct eth_dma_regs *)priv->dma_regs_p; + int length = 0; + ipq_gmac_desc_t *rxdesc = priv->desc_rx[priv->next_rx]; + uint status; + + invalidate_dcache_range((unsigned long)(priv->desc_rx[0]), + (unsigned long)(priv->desc_rx[NO_OF_RX_DESC - 1]) + + DESC_FLUSH_SIZE); + + for (rxdesc = priv->desc_rx[priv->next_rx]; + !ipq_gmac_owned_by_dma(rxdesc); + rxdesc = priv->desc_rx[priv->next_rx]) { + + status = rxdesc->status; + length = ((status & DescFrameLengthMask) >> + DescFrameLengthShift); + + invalidate_dcache_range( + (unsigned long)(net_rx_packets[priv->next_rx]), + (unsigned long)(net_rx_packets[priv->next_rx]) + + PKTSIZE_ALIGN); + net_process_received_packet(net_rx_packets[priv->next_rx], length - 4); + + rxdesc->length = ((ETH_MAX_FRAME_LEN << DescSize1Shift) & + DescSize1Mask); + + rxdesc->length |= (priv->next_rx == (NO_OF_RX_DESC - 1)) ? + RxDescEndOfRing : 0; + rxdesc->length |= RxDescChain; + + rxdesc->buffer1 = virt_to_phys(net_rx_packets[priv->next_rx]); + + priv->next_rx = (priv->next_rx + 1) % NO_OF_RX_DESC; + + rxdesc->data1 = (unsigned long)priv->desc_rx[priv->next_rx]; + + rxdesc->extstatus = 0; + rxdesc->reserved1 = 0; + rxdesc->timestamplow = 0; + rxdesc->timestamphigh = 0; + rxdesc->status = DescOwnByDma; + + flush_dcache_range((unsigned long)rxdesc, + (unsigned long)rxdesc + DESC_SIZE); + + writel(POLL_DATA, &dma_p->rxpolldemand); + } + + return length; +} + +static void ipq_eth_halt(struct eth_device *dev) +{ + if (dev->state != ETH_STATE_ACTIVE) + return; + /* reset the mac */ + ipq_mac_reset(dev); +} + +static int QCA8337_switch_init(ipq_gmac_board_cfg_t *gmac_cfg) +{ + for (int port = 0; + port < gmac_cfg->switch_port_count; + ++port) { + u32 phy_val; + /* phy powerdown */ + ipq_mdio_write( + gmac_cfg->switch_port_phy_address[port], + 0x0, + 0x0800 + ); + phy_val = ipq_mdio_read( + gmac_cfg->switch_port_phy_address[port], + 0x3d, + NULL + ); + phy_val &= ~0x0040; + ipq_mdio_write( + gmac_cfg->switch_port_phy_address[port], + 0x3d, + phy_val + ); + /* + * PHY will stop the tx clock for a while when link is down + * en_anychange debug port 0xb bit13 = 0 //speed up link down tx_clk + * sel_rst_80us debug port 0xb bit10 = 0 //speed up speed mode change to 2'b10 tx_clk + */ + phy_val = ipq_mdio_read( + gmac_cfg->switch_port_phy_address[port], + 0xb, + NULL + ); + phy_val &= ~0x2400; + ipq_mdio_write( + gmac_cfg->switch_port_phy_address[port], + 0xb, + phy_val + ); + mdelay(100); + } + if (ipq_athrs17_init(gmac_cfg) != 0){ + printf("QCA_8337 switch init failed \n"); + return 0; + } + for (int port = 0; + port < gmac_cfg->switch_port_count; + ++port) { + ipq_mdio_write( + gmac_cfg->switch_port_phy_address[port], + MII_ADVERTISE, + ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM + ); + /* phy reg 0x9, b10,1 = Prefer multi-port device (master) */ + ipq_mdio_write( + gmac_cfg->switch_port_phy_address[port], + MII_CTRL1000, + (0x0400|ADVERTISE_1000FULL) + ); + ipq_mdio_write( + gmac_cfg->switch_port_phy_address[port], + MII_BMCR, + BMCR_RESET | BMCR_ANENABLE + ); + mdelay(100); + } + return 1; +} + +static void gephy_mdac_edac_config(ipq_gmac_board_cfg_t *gmac_cfg) +{ + uint16_t phy_data; + uint32_t phy_dac = PHY_DAC(0x10); + uint32_t C45_id = QCA808X_REG_C45_ADDRESS(MPGE_PHY_MMD1_NUM, + MPGE_PHY_MMD1_DAC); + /*set mdac value*/ + phy_data = ipq5018_mdio_read( + gmac_cfg->phy_addr, + C45_id, + NULL + ); + phy_data &= ~(MPGE_PHY_MMD1_DAC_MASK); + ipq5018_mdio_write( + gmac_cfg->phy_addr, + C45_id, + (phy_data | phy_dac) + ); + mdelay(1); + /* + || set edac value debug register write follows indirect + || adressing so first write address in port address and + || write value in data register + */ + ipq5018_mdio_write(gmac_cfg->phy_addr, + QCA808X_DEBUG_PORT_ADDRESS, + MPGE_PHY_DEBUG_EDAC); + phy_data = ipq5018_mdio_read( + gmac_cfg->phy_addr, + QCA808X_DEBUG_PORT_DATA, + NULL); + + phy_data &= ~(MPGE_PHY_MMD1_DAC_MASK); + + ipq5018_mdio_write(gmac_cfg->phy_addr, + QCA808X_DEBUG_PORT_ADDRESS, + MPGE_PHY_DEBUG_EDAC); + ipq5018_mdio_write(gmac_cfg->phy_addr, + QCA808X_DEBUG_PORT_DATA, + (phy_data | phy_dac)); + mdelay(1); +} + +static void mdio_init(void) +{ + if(ipq5018_sw_mdio_init("IPQ MDIO0")) + printf("MDIO Failed to init for GMAC0\n"); + + if(ipq_sw_mdio_init("IPQ MDIO1")) + printf("MDIO Failed to init for GMAC1\n"); +} + +int ipq_gmac_init(ipq_gmac_board_cfg_t *gmac_cfg) +{ + struct eth_device *dev[CONFIG_IPQ_NO_MACS]; + uchar enet_addr[CONFIG_IPQ_NO_MACS * 6]; + int i; + uint32_t phy_chip_id, phy_chip_id1, phy_chip_id2; + uint32_t phy_mode = 0x70; + int ret; + + memset(enet_addr, 0, sizeof(enet_addr)); + + /* Mdio init */ + mdio_init(); + + /* Getting the MAC address from ART partition */ + ret = get_eth_mac_address(enet_addr, CONFIG_IPQ_NO_MACS); + + for (i = 0; gmac_cfg_is_valid(gmac_cfg); gmac_cfg++, i++) { + + dev[i] = malloc(sizeof(struct eth_device)); + if (dev[i] == NULL) + goto init_failed; + + ipq_gmac_macs[i] = malloc(sizeof(struct ipq_eth_dev)); + if (ipq_gmac_macs[i] == NULL) + goto init_failed; + + memset(dev[i], 0, sizeof(struct eth_device)); + memset(ipq_gmac_macs[i], 0, sizeof(struct ipq_eth_dev)); + + dev[i]->iobase = gmac_cfg->base; + dev[i]->init = ipq_eth_init; + dev[i]->halt = ipq_eth_halt; + dev[i]->recv = ipq_eth_recv; + dev[i]->send = ipq_eth_send; + dev[i]->write_hwaddr = ipq_eth_wr_macaddr; + dev[i]->priv = (void *) ipq_gmac_macs[i]; + /* + * Setting the Default MAC address + * if the MAC read from ART partition is invalid + */ + if ((ret < 0) || + (!is_valid_ethaddr(&enet_addr[i * 6]))) { + memcpy(&dev[i]->enetaddr[0], ipq_def_enetaddr, 6); + dev[i]->enetaddr[5] = dev[i]->enetaddr[5] + i; + } else { + memcpy(&dev[i]->enetaddr[0], &enet_addr[i * 6], 6); + } + + ipq_info("MAC%x addr:%x:%x:%x:%x:%x:%x\n", + gmac_cfg->unit, dev[i]->enetaddr[0], + dev[i]->enetaddr[1], + dev[i]->enetaddr[2], + dev[i]->enetaddr[3], + dev[i]->enetaddr[4], + dev[i]->enetaddr[5]); + + snprintf(dev[i]->name, sizeof(dev[i]->name), "eth%d", i); + + ipq_gmac_macs[i]->dev = dev[i]; + ipq_gmac_macs[i]->mac_unit = gmac_cfg->unit; + ipq_gmac_macs[i]->mac_regs_p = + (struct eth_mac_regs *)(gmac_cfg->base); + ipq_gmac_macs[i]->dma_regs_p = + (struct eth_dma_regs *)(gmac_cfg->base + DW_DMA_BASE_OFFSET); + ipq_gmac_macs[i]->phy_address = gmac_cfg->phy_addr; + ipq_gmac_macs[i]->gmac_board_cfg = gmac_cfg; + ipq_gmac_macs[i]->interface = gmac_cfg->phy_interface_mode; + ipq_gmac_macs[i]->phy_type = gmac_cfg->phy_type; + ipq_gmac_macs[i]->phy_external_link = gmac_cfg->phy_external_link; + ipq_gmac_macs[i]->sfp_tx_gpio = gmac_cfg->sfp_tx_gpio; + ipq_gmac_macs[i]->sfp_rx_gpio = gmac_cfg->sfp_rx_gpio; + ipq_gmac_macs[i]->sfp_mode = gmac_cfg->sfp_mode; + + if (gmac_cfg->sfp_mode == PORT_WRAPPER_SGMII_PLUS) + phy_mode = 0x50; + else if (gmac_cfg->sfp_mode == PORT_WRAPPER_SGMII_FIBER) + phy_mode = 0x30; + + snprintf((char *)ipq_gmac_macs[i]->phy_name, + sizeof(ipq_gmac_macs[i]->phy_name), "IPQ MDIO%d", i); + + if (gmac_cfg->unit){ + phy_chip_id1 = ipq_mdio_read( + ipq_gmac_macs[i]->phy_address, + QCA_PHY_ID1, + NULL); + phy_chip_id2 = ipq_mdio_read( + ipq_gmac_macs[i]->phy_address, + QCA_PHY_ID2, + NULL); + phy_chip_id = (phy_chip_id1 << 16) | phy_chip_id2; + } else { + phy_chip_id1 = ipq5018_mdio_read( + ipq_gmac_macs[i]->phy_address, + QCA_PHY_ID1, + NULL); + phy_chip_id2 = ipq5018_mdio_read( + ipq_gmac_macs[i]->phy_address, + QCA_PHY_ID2, + NULL); + phy_chip_id = (phy_chip_id1 << 16) | phy_chip_id2; + } + switch(phy_chip_id) { +#ifdef CONFIG_QCA8081_PHY + /* NAPA PHY For GMAC1 */ + case QCA8081_PHY: + case QCA8081_1_1_PHY: + ipq_gmac_macs[i]->phy_type = QCA8081_1_1_PHY; + ipq_qca8081_phy_init( + &ipq_gmac_macs[i]->ops, + ipq_gmac_macs[i]->phy_address); + break; +#endif + /* Internel GEPHY only for GMAC0 */ + case GEPHY: + ipq_gmac_macs[i]->phy_type = GEPHY; + ipq_gephy_phy_init( + &ipq_gmac_macs[i]->ops, + ipq_gmac_macs[i]->phy_address); + if(ipq_gmac_macs[i]->phy_external_link) + gephy_mdac_edac_config(gmac_cfg); + break; +#ifdef CONFIG_QCA8033_PHY + /* 1G PHY */ + case QCA8033_PHY: + ipq_gmac_macs[i]->phy_type = QCA8033_PHY; + ipq_qca8033_phy_init( + &ipq_gmac_macs[i]->ops, + ipq_gmac_macs[i]->phy_address); + break; +#endif + case QCA_8337: + if(gmac_cfg->ipq_swith){ + ipq_gmac_macs[i]->ipq_swith = + QCA8337_switch_init(gmac_cfg); + } + break; + default: + if (gmac_cfg->sfp_tx_gpio) { + ppe_uniphy_mode_set(gmac_cfg->sfp_mode, + phy_mode); + } else { + printf("GMAC%d:Invalid PHY ID \n", i); + } + break; + } + /* Initialize 8337 switch */ + if (gmac_cfg->ipq_swith && + ipq_gmac_macs[i]->phy_external_link && + !ipq_gmac_macs[i]->ipq_swith){ + ipq_gmac_macs[i]->ipq_swith = + QCA8337_switch_init(gmac_cfg); + } + /* Tx/Rx Descriptor initialization */ + if (ipq_gmac_tx_rx_desc_ring(dev[i]->priv) == -1) + goto init_failed; + + eth_register(dev[i]); + } + return 0; + +init_failed: + for (i = 0; i < IPQ5018_GMAC_PORT; i++) { + if (dev[i]) { + free(dev[i]); + } + if (ipq_gmac_macs[i]) + free(ipq_gmac_macs[i]); + } + + return -ENOMEM; +} + diff --git a/sources/uboot-be550/drivers/net/ipq5018/ipq5018_mdio.c b/sources/uboot-be550/drivers/net/ipq5018/ipq5018_mdio.c new file mode 100644 index 00000000..8f4bf24d --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq5018/ipq5018_mdio.c @@ -0,0 +1,227 @@ +/* + * Copyright (c) 2015-2017, 2020 The Linux Foundation. All rights reserved. + + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. +*/ + +#include +#include +#include +#include +#include +#include +#include "ipq5018_mdio.h" + +struct ipq5018_mdio_data { + struct mii_bus *bus; + int phy_irq[PHY_MAX_ADDR]; +}; + +static int ipq5018_mdio_wait_busy(void) +{ + int i; + u32 busy; + for (i = 0; i < IPQ5018_MDIO_RETRY; i++) { + udelay(IPQ5018_MDIO_DELAY); + busy = readl(IPQ5018_MDIO_BASE + + MDIO_CTRL_4_REG) & + MDIO_CTRL_4_ACCESS_BUSY; + + if (!busy) + return 0; + udelay(IPQ5018_MDIO_DELAY); + } + printf("%s: MDIO operation timed out\n", + __func__); + return -ETIMEDOUT; +} + +int ipq5018_mdio_write(int mii_id, int regnum, u16 value) +{ + u32 cmd; + if (ipq5018_mdio_wait_busy()) + return -ETIMEDOUT; + + + if (regnum & MII_ADDR_C45) { + unsigned int mmd = (regnum >> 16) & 0x1F; + unsigned int reg = regnum & 0xFFFF; + + writel(CTRL_0_REG_C45_DEFAULT_VALUE, + IPQ5018_MDIO_BASE + MDIO_CTRL_0_REG); + + /* Issue the phy address and reg */ + writel((mii_id << 8) | mmd, + IPQ5018_MDIO_BASE + MDIO_CTRL_1_REG); + + writel(reg, IPQ5018_MDIO_BASE + MDIO_CTRL_2_REG); + + /* issue read command */ + cmd = MDIO_CTRL_4_ACCESS_START | MDIO_CTRL_4_ACCESS_CODE_C45_ADDR; + + writel(cmd, IPQ5018_MDIO_BASE + MDIO_CTRL_4_REG); + + if (ipq5018_mdio_wait_busy()) + return -ETIMEDOUT; + } else { + writel(CTRL_0_REG_DEFAULT_VALUE, + IPQ5018_MDIO_BASE + MDIO_CTRL_0_REG); + + /* Issue the phy addreass and reg */ + writel((mii_id << 8 | regnum), + IPQ5018_MDIO_BASE + MDIO_CTRL_1_REG); + } + + /* Issue a write data */ + writel(value, IPQ5018_MDIO_BASE + MDIO_CTRL_2_REG); + + if (regnum & MII_ADDR_C45) { + cmd = MDIO_CTRL_4_ACCESS_START | MDIO_CTRL_4_ACCESS_CODE_C45_WRITE ; + } else { + cmd = MDIO_CTRL_4_ACCESS_START | MDIO_CTRL_4_ACCESS_CODE_WRITE ; + } + + writel(cmd, IPQ5018_MDIO_BASE + MDIO_CTRL_4_REG); + /* Wait for write complete */ + + if (ipq5018_mdio_wait_busy()) + return -ETIMEDOUT; + + return 0; +} + +int ipq5018_mdio_read(int mii_id, int regnum, ushort *data) +{ + u32 val,cmd; + if (ipq5018_mdio_wait_busy()) + return -ETIMEDOUT; + + if (regnum & MII_ADDR_C45) { + + unsigned int mmd = (regnum >> 16) & 0x1F; + unsigned int reg = regnum & 0xFFFF; + + writel(CTRL_0_REG_C45_DEFAULT_VALUE, + IPQ5018_MDIO_BASE + MDIO_CTRL_0_REG); + + /* Issue the phy address and reg */ + writel((mii_id << 8) | mmd, + IPQ5018_MDIO_BASE + MDIO_CTRL_1_REG); + + + writel(reg, IPQ5018_MDIO_BASE + MDIO_CTRL_2_REG); + + /* issue read command */ + cmd = MDIO_CTRL_4_ACCESS_START | MDIO_CTRL_4_ACCESS_CODE_C45_ADDR; + } else { + + writel(CTRL_0_REG_DEFAULT_VALUE, + IPQ5018_MDIO_BASE + MDIO_CTRL_0_REG); + + /* Issue the phy address and reg */ + writel((mii_id << 8 | regnum ) , + IPQ5018_MDIO_BASE + MDIO_CTRL_1_REG); + + /* issue read command */ + cmd = MDIO_CTRL_4_ACCESS_START | MDIO_CTRL_4_ACCESS_CODE_READ ; + } + + /* issue read command */ + writel(cmd, IPQ5018_MDIO_BASE + MDIO_CTRL_4_REG); + + if (ipq5018_mdio_wait_busy()) + return -ETIMEDOUT; + + + if (regnum & MII_ADDR_C45) { + cmd = MDIO_CTRL_4_ACCESS_START | MDIO_CTRL_4_ACCESS_CODE_C45_READ; + writel(cmd, IPQ5018_MDIO_BASE + MDIO_CTRL_4_REG); + + if (ipq5018_mdio_wait_busy()) + return -ETIMEDOUT; + } + + /* Read data */ + val = readl(IPQ5018_MDIO_BASE + MDIO_CTRL_3_REG); + + if (data != NULL) + *data = val; + + return val; +} + +int ipq5018_phy_write(struct mii_dev *bus, + int addr, int dev_addr, + int regnum, ushort value) +{ + return ipq5018_mdio_write(addr, regnum, value); +} + +int ipq5018_phy_read(struct mii_dev *bus, + int addr, int dev_addr, int regnum) +{ + return ipq5018_mdio_read(addr, regnum, NULL); +} + +int ipq5018_sw_mdio_init(const char *name) +{ + struct mii_dev *bus = mdio_alloc(); + if(!bus) { + printf("Failed to allocate IPQ5018 MDIO bus\n"); + return -1; + } + bus->read = ipq5018_phy_read; + bus->write = ipq5018_phy_write; + bus->reset = NULL; + snprintf(bus->name, MDIO_NAME_LEN, name); + return mdio_register(bus); +} + +static int do_ipq5018_mdio(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + char op[2]; + unsigned int addr = 0, reg = 0; + unsigned short data = 0; + + if (argc < 2) + return CMD_RET_USAGE; + + op[0] = argv[1][0]; + if (strlen(argv[1]) > 1) + op[1] = argv[1][1]; + else + op[1] = '\0'; + + if (argc >= 3) + addr = simple_strtoul(argv[2], NULL, 16); + if (argc >= 4) + reg = simple_strtoul(argv[3], NULL, 16); + if (argc >= 5) + data = simple_strtoul(argv[4], NULL, 16); + + if (op[0] == 'r') { + data = ipq5018_mdio_read(addr, reg, NULL); + printf("0x%x\n", data); + } else if (op[0] == 'w') { + ipq5018_mdio_write(addr, reg, data); + } else { + return CMD_RET_USAGE; + } + + return 0; +} + +U_BOOT_CMD( + ipq5018_mdio, 5, 1, do_ipq5018_mdio, + "IPQ5018 mdio utility commands", + "ipq5018_mdio read - read IPQ5018 MDIO PHY register \n" + "ipq5018_mdio write - write IPQ5018 MDIO PHY register \n" + "Addr and/or reg may be ranges, e.g. 0-7." +); diff --git a/sources/uboot-be550/drivers/net/ipq5018/ipq5018_mdio.h b/sources/uboot-be550/drivers/net/ipq5018/ipq5018_mdio.h new file mode 100644 index 00000000..857dfe16 --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq5018/ipq5018_mdio.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2015-2017, 2020 The Linux Foundation. All rights reserved. + + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. +*/ +#ifndef _IPQ5018_MDIO_H +#define _IPQ5018_MDIO_H + +#define IPQ5018_MDIO_BASE 0x88000 +#define MDIO_CTRL_0_REG 0x40 +#define MDIO_CTRL_1_REG 0x44 +#define MDIO_CTRL_2_REG 0x48 +#define MDIO_CTRL_3_REG 0x4c +#define MDIO_CTRL_4_REG 0x50 +#define MDIO_CTRL_4_ACCESS_BUSY (1 << 16) +#define MDIO_CTRL_4_ACCESS_START (1 << 8) +#define MDIO_CTRL_4_ACCESS_CODE_READ 0 +#define MDIO_CTRL_4_ACCESS_CODE_WRITE 1 +#define MDIO_CTRL_4_ACCESS_CODE_C45_ADDR 0 +#define MDIO_CTRL_4_ACCESS_CODE_C45_WRITE 1 +#define MDIO_CTRL_4_ACCESS_CODE_C45_READ 2 +#define CTRL_0_REG_DEFAULT_VALUE 0x1500F +#ifdef MDIO_12_5_MHZ +#define CTRL_0_REG_C45_DEFAULT_VALUE 0x15107 +#else +#define CTRL_0_REG_C45_DEFAULT_VALUE 0x1510F +#endif +#define IPQ5018_MDIO_RETRY 1000 +#define IPQ5018_MDIO_DELAY 5 +#endif /* End _IPQ5018_MDIO_H */ diff --git a/sources/uboot-be550/drivers/net/ipq5018/ipq5018_uniphy.c b/sources/uboot-be550/drivers/net/ipq5018/ipq5018_uniphy.c new file mode 100644 index 00000000..41ed0185 --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq5018/ipq5018_uniphy.c @@ -0,0 +1,221 @@ +/* + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include "ipq5018_uniphy.h" +#include "ipq_phy.h" + +static uint32_t cur_mode; + +static int ppe_uniphy_calibration(void) +{ + int retries = 100, calibration_done = 0; + uint32_t reg_value = 0; + + while(calibration_done != UNIPHY_CALIBRATION_DONE) { + mdelay(1); + if (retries-- == 0) { + printf("uniphy callibration time out!\n"); + return -1; + } + reg_value = readl(PPE_UNIPHY_BASE + PPE_UNIPHY_OFFSET_CALIB_4); + calibration_done = (reg_value >> 0x7) & 0x1; + } + + return 0; +} + +static void ppe_gcc_uniphy_soft_reset(void) +{ + uint32_t reg_value; + + reg_value = readl(GCC_UNIPHY0_MISC); + + reg_value |= GCC_UNIPHY_SGMII_SOFT_RESET; + + writel(reg_value, GCC_UNIPHY0_MISC); + + udelay(500); + + reg_value &= ~GCC_UNIPHY_SGMII_SOFT_RESET; + + writel(reg_value, GCC_UNIPHY0_MISC); +} + +void uniphy_channel0_input_output_6_get(int mode, u32 gpio, u8 *status, + fal_port_speed_t *speed, + fal_port_duplex_t *duplex) +{ + uint32_t reg_value; + int val; + + *status = 1; + *speed = FAL_SPEED_BUTT; + *duplex = FAL_DUPLEX_BUTT; + + reg_value = readl(PPE_UNIPHY_BASE + UNIPHY_DEC_CHANNEL_0_INPUT_OUTPUT_6); + + val = reg_value & CH0_LINK_MAC; + + if (val) { + switch(mode) { + case PORT_WRAPPER_SGMII_FIBER: + *status = 0; /* LINK UP */ + break; + case PORT_WRAPPER_SGMII_PLUS: + /* + * get rx_los status + * if, rx_los = 0, link up + * else, link down + */ + if (gpio && !gpio_get_value(gpio)) { + *status = 0; + *speed = FAL_SPEED_2500; + *duplex = FAL_FULL_DUPLEX; + } + return; + default: + printf("%s: Invalid mode\n", __func__); + break; + } + } + + val = (reg_value & CH0_SPEED_MODE_MAC) >> 4; + + switch(val) { + case UNIPHY_SPEED_1000M: + *speed = FAL_SPEED_1000; + break; + case UNIPHY_SPEED_100M: + *speed = FAL_SPEED_100; + break; + case UNIPHY_SPEED_10M: + *speed = FAL_SPEED_10; + break; + default: + *speed = FAL_SPEED_BUTT; + break; + + } + + val = (reg_value & CH0_DUPLEX_MODE_MAC) >> 6; + + if (val) + *duplex = FAL_FULL_DUPLEX; + else + *duplex = FAL_HALF_DUPLEX; + + return; +} + +static void ppe_uniphy_sgmii_mode_set(uint32_t mode, uint32_t phy_mode) +{ + writel(UNIPHY_MISC2_REG_SGMII_MODE, + PPE_UNIPHY_BASE + UNIPHY_MISC2_REG_OFFSET); + + writel(UNIPHY_PLL_RESET_REG_VALUE, PPE_UNIPHY_BASE + + UNIPHY_PLL_RESET_REG_OFFSET); + mdelay(10); + writel(UNIPHY_PLL_RESET_REG_DEFAULT_VALUE, PPE_UNIPHY_BASE + + UNIPHY_PLL_RESET_REG_OFFSET); + mdelay(10); + + writel(0x0, GCC_UNIPHY_RX_CBCR); + udelay(500); + writel(0x0, GCC_UNIPHY_TX_CBCR); + udelay(500); + writel(0x0, GCC_GMAC1_RX_CBCR); + udelay(500); + writel(0x0, GCC_GMAC1_TX_CBCR); + udelay(500); + + switch (mode) { + case PORT_WRAPPER_SGMII_FIBER: + writel(UNIPHY_SG_MODE, PPE_UNIPHY_BASE + PPE_UNIPHY_MODE_CONTROL); + break; + + case PORT_WRAPPER_SGMII0_RGMII4: + case PORT_WRAPPER_SGMII1_RGMII4: + case PORT_WRAPPER_SGMII4_RGMII4: + writel((UNIPHY_SG_MODE | UNIPHY_PSGMII_MAC_MODE), + PPE_UNIPHY_BASE + PPE_UNIPHY_MODE_CONTROL); + break; + + case PORT_WRAPPER_SGMII_PLUS: + writel((UNIPHY_SG_PLUS_MODE | UNIPHY_PSGMII_MAC_MODE), + PPE_UNIPHY_BASE + PPE_UNIPHY_MODE_CONTROL); + break; + + default: + printf("SGMII Config. wrongly"); + break; + } + if ((cur_mode == PORT_WRAPPER_SGMII_PLUS) || + (mode == PORT_WRAPPER_SGMII_PLUS)){ + cur_mode = mode; + ppe_gcc_uniphy_soft_reset(); + } + + writel(phy_mode, PPE_UNIPHY_BASE + PPE_UNIPHY_ALLREG_DEC_MISC2); + + writel(0x1, GCC_UNIPHY_RX_CBCR); + udelay(500); + writel(0x1, GCC_UNIPHY_TX_CBCR); + udelay(500); + writel(0x1, GCC_GMAC1_RX_CBCR); + udelay(500); + writel(0x1, GCC_GMAC1_TX_CBCR); + udelay(500); + + ppe_uniphy_calibration(); +} + +void ppe_uniphy_mode_set(uint32_t mode, uint32_t phy_mode) +{ + /* + * SGMII and SHMII plus confugure in same function + */ + ppe_uniphy_sgmii_mode_set(mode, phy_mode); +} + +void ppe_uniphy_set_forceMode(void) +{ + uint32_t reg_value; + + reg_value = readl(PPE_UNIPHY_BASE + UNIPHY_DEC_CHANNEL_0_INPUT_OUTPUT_4); + reg_value |= UNIPHY_FORCE_SPEED_25M; + + writel(reg_value, PPE_UNIPHY_BASE + UNIPHY_DEC_CHANNEL_0_INPUT_OUTPUT_4); + +} + +void ppe_uniphy_refclk_set(void) +{ +/* + * This function drive the uniphy ref clock + * DEC_REFCLKOUTPUTCONTROLREGISTERS + * Its is configured as 25 MHZ + */ + + u32 reg_val = readl(PPE_UNIPHY_BASE | UNIPHY_REF_CLK_CTRL_REG); + reg_val |= 0x2; + writel(reg_val, PPE_UNIPHY_BASE | UNIPHY_REF_CLK_CTRL_REG); + mdelay(200); +} diff --git a/sources/uboot-be550/drivers/net/ipq5018/ipq5018_uniphy.h b/sources/uboot-be550/drivers/net/ipq5018/ipq5018_uniphy.h new file mode 100644 index 00000000..cd47f274 --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq5018/ipq5018_uniphy.h @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef _IPQ5018_UNIPHY_H_ +#define _IPQ5018_UNIPHY_H +#include "ipq_phy.h" + +#define PPE_UNIPHY_INSTANCE0 0 + +#define GCC_UNIPHY_RX_CBCR 0x01856110 +#define GCC_UNIPHY_TX_CBCR 0x01856114 + +#define GCC_GMAC1_RX_CBCR 0x01868248 +#define GCC_GMAC1_TX_CBCR 0x0186824C + +#define GCC_UNIPHY0_MISC 0x01856104 + +#define PPE_UNIPHY_OFFSET_CALIB_4 0x1E0 +#define UNIPHY_CALIBRATION_DONE 0x1 + +#define GCC_UNIPHY_PSGMII_SOFT_RESET 0x3ff2 +#define GCC_UNIPHY_SGMII_SOFT_RESET 0x32 + +#define PPE_UNIPHY_BASE 0x00098000 +#define PPE_UNIPHY_MODE_CONTROL 0x46C +#define PPE_UNIPHY_ALLREG_DEC_MISC2 0x218 +#define UNIPHY_XPCS_MODE (1 << 12) +#define UNIPHY_SG_PLUS_MODE (1 << 11) +#define UNIPHY_SG_MODE (1 << 10) +#define UNIPHY_CH0_PSGMII_QSGMII (1 << 9) +#define UNIPHY_CH0_QSGMII_SGMII (1 << 8) +#define UNIPHY_PSGMII_MAC_MODE (1 << 5) +#define UNIPHY_CH4_CH1_0_SGMII (1 << 2) +#define UNIPHY_CH1_CH0_SGMII (1 << 1) +#define UNIPHY_CH0_ATHR_CSCO_MODE_25M (1 << 0) + +#define UNIPHY_DEC_CHANNEL_0_INPUT_OUTPUT_4 0x480 +#define UNIPHY_FORCE_SPEED_25M (1 << 3) + +#define UNIPHY_DEC_CHANNEL_0_INPUT_OUTPUT_6 0x488 +#define CH0_LINK_MAC (1 << 7) +#define CH0_DUPLEX_MODE_MAC (1 << 6) +#define CH0_SPEED_MODE_MAC (3 << 4) + +#define UNIPHY_REF_CLK_CTRL_REG 0x74 + +#define UNIPHY_INSTANCE_LINK_DETECT 0x570 + +#define UNIPHY_MISC2_REG_OFFSET 0x218 +#define UNIPHY_MISC2_REG_SGMII_MODE 0x30 +#define UNIPHY_MISC2_REG_SGMII_PLUS_MODE 0x50 + +#define UNIPHY_MISC2_REG_VALUE 0x70 + +#define UNIPHY_PLL_RESET_REG_OFFSET 0x780 +#define UNIPHY_PLL_RESET_REG_VALUE 0x02bf +#define UNIPHY_PLL_RESET_REG_DEFAULT_VALUE 0x02ff + +#define UNIPHY_SPEED_10M 0 +#define UNIPHY_SPEED_100M 1 +#define UNIPHY_SPEED_1000M 2 + +void ppe_uniphy_mode_set(uint32_t mode, uint32_t phy_mode); +void ppe_uniphy_set_forceMode(void); +void ppe_uniphy_refclk_set(void); +void uniphy_channel0_input_output_6_get(int mode, u32 gpio, u8 *status, + fal_port_speed_t *speed, + fal_port_duplex_t *duplex); +#endif diff --git a/sources/uboot-be550/drivers/net/ipq5332/ipq5332_edma.c b/sources/uboot-be550/drivers/net/ipq5332/ipq5332_edma.c new file mode 100755 index 00000000..647cedab --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq5332/ipq5332_edma.c @@ -0,0 +1,3305 @@ +/* + ************************************************************************** + * Copyright (c) 2016-2019, 2021, The Linux Foundation. All rights reserved. + * + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + ************************************************************************** +*/ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "ipq5332_edma.h" +#include "ipq_phy.h" +#include "ipq_qca8084.h" + +#ifdef CONFIG_TP_EXT_PHY_RTL8221B +#include "../rtl8221b/rtl8226_typedef.h" +#include "../rtl8221b/nic_rtl8226b_init.h" +#include "../rtl8221b/nic_rtl8226b.h" +#endif + +#ifdef CONFIG_TP_EXT_SWITCH +#ifdef CONFIG_TP_EXT_SWITCH_RTL8367_ALL +#include "../rtl8367_common_V1_4_2/chip.h" +#include "../rtl8367_common_V1_4_2/port.h" +#include "../rtl8367_common_V1_4_2/rtk_switch.h" +#include "../rtl8367_common_V1_4_2/vlan.h" +#include "../rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_port.h" +#include "../rtl8367_common_V1_4_2/dal/rtl8367d/rtl8367d_smi.h" +#include "../rtl8367_common_V1_4_2/dal/rtl8367d/rtl8367d_asicdrv.h" + +switch_chip_t g_switch_chip = CHIP_END; + +#endif +#ifdef CONFIG_TP_EXT_SWITCH_RTL8372 +#include "../rtl8372/rtk_types.h" +#include "../rtl8372/rtk_error.h" +#include "../rtl8372/rtk_switch.h" +#include "../rtl8372/port.h" +#include "../rtl8372/dal/rtl8373/dal_rtl8373_switch.h" +#include "../rtl8372/dal/rtl8373/dal_rtl8373_port.h" +#include "../rtl8372/dal/rtl8373/dal_rtl8373_drv.h" +#endif +#endif + +#ifdef CONFIG_TP_EXT_PHY_RTL8251B +#include "../rtl8251b/rtl8251b_typedef.h" +#include "../rtl8251b/nic_rtl8251b_init.h" +#include "../rtl8251b/nic_rtl8251b.h" +#endif + +DECLARE_GLOBAL_DATA_PTR; +#ifdef DEBUG +#define pr_debug(fmt, args...) printf(fmt, ##args); +#else +#define pr_debug(fmt, args...) +#endif + +#define pr_info(fmt, args...) printf(fmt, ##args); +#define pr_warn(fmt, args...) printf(fmt, ##args); + +#ifndef CONFIG_IPQ5332_BRIDGED_MODE +#define IPQ5332_EDMA_MAC_PORT_NO 3 +#endif + +static struct ipq5332_eth_dev *ipq5332_edma_dev[IPQ5332_EDMA_DEV]; +typedef struct { + phy_info_t *phy_info; + int port_id; + int uniphy_id; + int mode; +} ipq5332_edma_port_info_t; + +uchar ipq5332_def_enetaddr[6] = {0x00, 0x03, 0x7F, 0xBA, 0xDB, 0xAD}; +phy_info_t *swt_info[QCA8084_MAX_PORTS] = {0}; +ipq5332_edma_port_info_t *port_info[IPQ5332_PHY_MAX] = {0}; +mdio_info_t *mdio_info[IPQ5332_PHY_MAX] = {0}; +int sgmii_mode[2] = {0}; + +extern void ipq_phy_addr_fixup(void); +extern void ipq_clock_init(void); +extern int ipq_sw_mdio_init(const char *); +extern int ipq_mdio_read(int mii_id, int regnum, ushort *data); +extern void ipq5332_qca8075_phy_map_ops(struct phy_ops **ops); +extern int ipq5332_qca8075_phy_init(struct phy_ops **ops, u32 phy_id); +extern void ipq5332_qca8075_phy_interface_set_mode(uint32_t phy_id, + uint32_t mode); +extern int ipq_qca8033_phy_init(struct phy_ops **ops, u32 phy_id); +extern int ipq_qca8081_phy_init(struct phy_ops **ops, u32 phy_id); +extern int ipq_qca_aquantia_phy_init(struct phy_ops **ops, u32 phy_id); +extern int ipq_board_fw_download(unsigned int phy_addr); +extern int ipq_qca8084_hw_init(phy_info_t * phy_info[]); +extern int ipq_qca8084_link_update(phy_info_t * phy_info[]); +extern void ipq_qca8084_switch_hw_reset(int gpio); +extern void ipq5332_xgmac_sgmiiplus_speed_set(int port, int speed, int status); +extern void ppe_uniphy_refclk_set_25M(uint32_t uniphy_index); +extern void qca8033_phy_reset(void); +extern void ipq5332_gmac_port_disable(int port); +extern void ipq_set_mdio_mode(const int mode, const int bus); +#ifdef CONFIG_ATHRS17C_SWITCH +extern void ppe_uniphy_set_forceMode(uint32_t uniphy_index); +extern int ipq_qca8337_switch_init(ipq_s17c_swt_cfg_t *s17c_swt_cfg); +extern int ipq_qca8337_link_update(ipq_s17c_swt_cfg_t *s17c_swt_cfg); +extern void ipq_s17c_switch_reset(int gpio); +ipq_s17c_swt_cfg_t s17c_swt_cfg[IPQ5332_PHY_MAX]; +#endif + +static int tftp_acl_our_port; + +#ifdef CONFIG_QCA8084_BYPASS_MODE +extern void qca8084_bypass_interface_mode_set(u32 interface_mode); +extern void qca8084_phy_sgmii_mode_set(uint32_t phy_addr, u32 interface_mode, + u32 link, fal_port_speed_t speed); +static int qca8084_bypass_enb = 0; +#endif /* CONFIG_QCA8084_BYPASS_MODE */ + +extern void ipq_qca8084_phy_hw_init(struct phy_ops **ops, u32 phy_addr); + +#ifdef CONFIG_TP_EXT_PHY_RTL8221B + +HANDLE g_handle = { + .unit = 0, + .port = 0 +}; + +#define MII_ADDR_C45 (1<<30) + +#define ERR_PRINT(ret) \ + do { \ + if ( ret != SUCCESS ) printf("[rtl8221b] %s[%d]: error, return: %d. \n", __FUNCTION__, __LINE__, ret); \ + } while(0) + +extern int ipq_mdio_read(int mii_id, int regnum, unsigned short *data); +extern int ipq_mdio_write(int mii_id, int regnum, unsigned short value); + +int g_mdio_num = 7; + +static int rtl8221b_mdio_write(unsigned short devad, int regnum, unsigned short val) +{ + int ret = 0; + regnum = MII_ADDR_C45 | ((devad & 0x1f) << 16) | (regnum & 0xffff); + + ret = ipq_mdio_write(g_mdio_num, regnum, val); + if (ret == -ETIMEDOUT) + { + printf("ipq_mdio_write ETIMEDOUT\n"); + return FAILURE; + } + return SUCCESS; +} + +static int rtl8221b_mdio_read(unsigned short devad, int regnum, unsigned short *data) +{ + int ret = 0; + regnum = MII_ADDR_C45 | (devad << 16) | (regnum & 0xffff); + + ret = ipq_mdio_read(g_mdio_num, regnum, data); + if (ret == -ETIMEDOUT) + { + printf("ipq_mdio_read ETIMEDOUT\n"); + return FAILURE; + } + return SUCCESS; +} + +BOOLEAN +MmdPhyRead( IN HANDLE hDevice, IN UINT16 dev, IN UINT16 addr, OUT UINT16 *data) +{ + return rtl8221b_mdio_read(dev, (int)addr, data); +} + +BOOLEAN +MmdPhyWrite( IN HANDLE hDevice, IN UINT16 dev, IN UINT16 addr, IN UINT16 data) +{ + return rtl8221b_mdio_write(dev, (int)addr, data); +} + +static void rtl8221b_gpio_reset(int gpio_num) +{ + gpio_direction_output(gpio_num, 1); + mdelay(500); + gpio_set_value(gpio_num, 0); + mdelay(200); + gpio_set_value(gpio_num, 1); + mdelay(200); + + return; +} + +static int status_get(void) +{ + UINT16 phydata = 0; + int ret = FAILURE; + + ret = MmdPhyRead(g_handle, MMD_VEND2, 0xA434, &phydata); + if (ret != SUCCESS) + { + printf("get rtl8221b phy 0xA434 failed\n"); + } + else + { + printf("get rtl8221b phy 0xA434 phydata=0x%x\n", phydata); + } + + ret = MmdPhyRead(g_handle, MMD_VEND1, 0x7580, &phydata); + if (ret != SUCCESS) + { + printf("get rtl8221b phy 0x7580 failed\n"); + } + else + { + printf("get rtl8221b phy 0x7580 phydata=0x%x\n", phydata); + } + + ret = MmdPhyRead(g_handle, MMD_VEND1, 0x7582, &phydata); + if (ret != SUCCESS) + { + printf("get rtl8221b phy 0x7582 failed\n"); + } + else + { + printf("get rtl8221b phy 0x7582 phydata=0x%x\n", phydata); + } + + ret = MmdPhyRead(g_handle, MMD_VEND1, 0x758D, &phydata); + if (ret != SUCCESS) + { + printf("get rtl8221b phy 0x758D failed\n"); + } + else + { + printf("get rtl8221b phy 0x758D phydata=0x%x\n", phydata); + } + + ret = MmdPhyRead(g_handle, MMD_VEND1, 0x758C, &phydata); + if (ret != SUCCESS) + { + printf("get rtl8221b phy 0x758C failed\n"); + } + else + { + printf("get rtl8221b phy 0x758C phydata=0x%x\n", phydata); + } + + ret = MmdPhyRead(g_handle, MMD_VEND1, 0x697A, &phydata); + if (ret != SUCCESS) + { + printf("get rtl8221b phy 0x697A failed\n"); + } + else + { + printf("get rtl8221b phy 0x697A phydata=0x%x\n", phydata); + } + + return ret; +} + +static int rtl8221b_init_common(void) +{ + BOOL ret; + PHY_LINK_ABILITY phy_ability; + PHY_EEE_ENABLE eee_enable; + + struct device_node *mdio; + struct mii_bus *mdio_bus; + + ret = Rtl8226b_phy_init(g_handle, &phy_ability, TRUE); + ERR_PRINT(ret); + + ret = Rtl8226b_serdes_autoNego_set(g_handle, FALSE); + ERR_PRINT(ret); + + ret = Rtl8226b_serdes_option_set(g_handle, PHY_SERDES_OPTION_HiSGMII); + ERR_PRINT(ret); + + ret = Rtl8226b_phy_reset(g_handle); + ERR_PRINT(ret); + + phy_ability.Half_10 = 1; + phy_ability.Full_10 = 1; + phy_ability.Half_100 = 1; + phy_ability.Full_100 = 1; + phy_ability.Full_1000 = 1; + phy_ability.adv_2_5G = 1; + phy_ability.FC = 1; + phy_ability.AsyFC = 1; + ret = Rtl8226b_autoNegoAbility_set(g_handle, &phy_ability); + ERR_PRINT(ret); + + ret = Rtl8226b_autoNegoEnable_set(g_handle, TRUE); + ERR_PRINT(ret); + + eee_enable.EEE_100 = 0; + eee_enable.EEE_1000 = 0; + eee_enable.EEE_2_5G = 0; + ret = Rtl8226b_eeeEnable_set(g_handle, &eee_enable); + ERR_PRINT(ret); + + ret = Rtl8226b_greenEnable_set(g_handle, FALSE); + ERR_PRINT(ret); + + Rtl8226b_enable_set(g_handle, TRUE); + + status_get(); + + return 0; +} + +#ifdef CONFIG_TP_EXT_PHY_RTL8221B_LAN +static int rtl8221b_lan_init(int mdio_num) +{ + g_mdio_num = mdio_num; + rtl8221b_init_common(); + return 0; +} +#endif + +static int rtl8221b_wan_init(int mdio_num) +{ + g_mdio_num = mdio_num; + rtl8221b_init_common(); + return 0; +} + +static int rtl8221b_init(void) +{ +#ifdef CONFIG_TP_EXT_PHY_RTL8221B_LAN + rtl8221b_gpio_reset(43); //lan hardware reset + printf("Init RTL8221, phy_reset_gpio 43 \n"); + rtl8221b_lan_init(6); +#endif + + rtl8221b_gpio_reset(39); //wan hardware reset + printf("Init RTL8221, phy_reset_gpio 39 \n"); + rtl8221b_wan_init(7); + + return 0; +} + +static int ipq_rtl8221_Link_Update(int mdio_num) +{ + BOOL status = FAILURE; + BOOL linkOK = FALSE; + + g_mdio_num = mdio_num; + + status = Rtl8226b_is_link(g_handle, &linkOK); + if (status != 1) + { + printf("Rtl8226b_is_link error\n"); + return 1; + } + + if (!linkOK) + { + if (mdio_num == 7) + { + printf("RTL8221B WAN not link!!!\n"); + } + else + { + printf("RTL8221B LAN not link!!!\n"); + } + return 1; + } + + if (mdio_num == 7) + { + printf("RTL8221B WAN link!!!\n"); + } + else + { + printf("RTL8221B LAN link!!!\n"); + } + + return 0; +} +#endif + +#ifdef CONFIG_TP_EXT_PHY_RTL8251B + +#define PHY_DAC(val) (val<<8) + +#define RTL8211_STATUS_LINK_MASK 0x0004 +#define RTL8211_STATUS_DUPLEX_MASK 0x0008 +#define RTL8211_STATUS_SPEED_MASK 0x2040 +#define RTL8211_STATUS_FULL_DUPLEX 0x2000 + +#define RTL8251B_LAN_MDIO_NUM 2 +#define RTL8251B_WAN_MDIO_NUM 3 +#define RTL8251B_LAN_RST_GPIO 45 +#define RTL8251B_WAN_RST_GPIO 39 +#define MII_ADDR_C45 (1<<30) + +#define PROC_DIR_LAN "rtl8251b_lan" +#define PROC_DIR_WAN "rtl8251b_wan" + +#define LOG_ERR(fmt, ...) \ + do { \ + printf("[rtl8251b] %s[%d]: "fmt, __func__, __LINE__, ##__VA_ARGS__); \ + } while(0) +#define ERR_PRINT(ret) \ + do { \ + if ( ret != SUCCESS ) printf("[rtl8251b] %s[%d]: error, return. ", __FUNCTION__, __LINE__); \ + } while(0) + +extern int ipq_mdio_read(int mii_id, int regnum, unsigned short *data); +extern int ipq_mdio_write(int mii_id, int regnum, unsigned short value); + +HANDLE g_handle = { + .unit = 0, + .port = 0 +}; + +static int lw_flip = 0; +static int g_mdio_num = 0; + +static int rtl8251b_mdio_write(unsigned short devad, int regnum, unsigned short val) +{ + int ret = 0; + regnum = MII_ADDR_C45 | ((devad & 0x1f) << 16) | (regnum & 0xffff); + + ret = ipq_mdio_write(g_mdio_num, regnum, val); + if (ret == -ETIMEDOUT) + { + printf("ipq_mdio_write ETIMEDOUT\n"); + return FAILURE; + } + return SUCCESS; +} + +static int rtl8251b_mdio_read(unsigned short devad, int regnum, unsigned short *data) +{ + int ret = 0; + regnum = MII_ADDR_C45 | (devad << 16) | (regnum & 0xffff); + + ret = ipq_mdio_read(g_mdio_num, regnum, data); + if (ret == -ETIMEDOUT) + { + printf("ipq_mdio_read ETIMEDOUT\n"); + return FAILURE; + } + return SUCCESS; +} + +#ifdef GE550V2_RTL8372_RTL8251B +static int rtl8211_phy_read_by_switch(uint32_t dev_id, uint32_t phy_id, uint16_t reg_id, uint16_t *reg_val) +{ + rtk_uint32 pvalue = 0; + + if (RT_ERR_OK != dal_rtl8373_phy_regbits_read(phy_id, dev_id, reg_id, 0xffff, &pvalue)) + { + printf("rtk_rtl8373_phy_regbits_read failed!\n"); + return FAILURE; + } + + *reg_val = (uint16_t)(pvalue & 0xffff); + + return SUCCESS; +} + +static int rtl8211_phy_write_by_switch(uint32_t dev_id, uint32_t phy_id, uint16_t reg_id, uint16_t reg_val) +{ + if (RT_ERR_OK != dal_rtl8373_phy_regbits_write(1<link_status = (phydata & RTL8211_STATUS_LINK_MASK)?TRUE:FALSE; + phy_status->duplex = (phydata & RTL8211_STATUS_DUPLEX_MASK)?FAL_FULL_DUPLEX:FAL_HALF_DUPLEX; + if (phy_status->link_status) + { + speed_grp = (phydata & (BIT_9 | BIT_10)) >> 9; + speed = (phydata & (BIT_4 | BIT_5)) >> 4; + switch(speed_grp) + { + case 0: + { + switch(speed) + { + case 0: + phy_status->speed = FAL_SPEED_10; + break; + case 1: + phy_status->speed = FAL_SPEED_100; + break; + case 2: + phy_status->speed = FAL_SPEED_1000; + break; + case 3: + phy_status->speed = FAL_SPEED_100; // 1G lite + break; + + default: + phy_status->speed = FAL_SPEED_10; + break; + } + break; + } + case 1: + { + switch(speed) + { + case 1: + phy_status->speed = FAL_SPEED_2500; + break; + case 2: + phy_status->speed = FAL_SPEED_5000; //5G + break; + case 3: + phy_status->speed = FAL_SPEED_1000; // 2.5G lite + break; + default: + phy_status->speed = FAL_SPEED_10; + break; + } + break; + } + default: + phy_status->speed = FAL_SPEED_10; + break; + } + } + else + { + phy_status->speed = FAL_SPEED_10; + } + + // printf("get rtl8251 %u linkstatus: %u, speed: %d, duplex: %d\n", phy_id, phy_status->link_status, phy_status->speed, phy_status->duplex); + return 0; +} + + +u8 rtl8251_phy_get_link_status(uint32_t dev_id, uint32_t phy_id) +{ + struct port_phy_status phy_status; + rtl8251_phy_get_status( dev_id, phy_id, &phy_status); + if (phy_status.link_status) + { + return 0; //up + } + return 1; //down + +} + +u32 rtl8251_phy_get_speed(uint32_t dev_id, uint32_t phy_id, + fal_port_speed_t * speed) +{ + struct port_phy_status phy_status; + rtl8251_phy_get_status( dev_id, phy_id, &phy_status); + *speed = phy_status.speed; + return TRUE; +} + +u32 rtl8251_phy_get_duplex(uint32_t dev_id, uint32_t phy_id, + fal_port_duplex_t * duplex) + { + struct port_phy_status phy_status; + rtl8251_phy_get_status( dev_id, phy_id, &phy_status); + *duplex = phy_status.duplex; + return TRUE; + } + +static int _status_get(void) +{ + UINT16 phydata = 0; + int ret = -1; + + ret = MmdPhyRead(g_handle, MMD_VEND2, 0xA434, &phydata); + LOG_ERR("get rtl8251b phy 0xA434 phydata=0x%x\n", phydata); + + ret = MmdPhyRead(g_handle, MMD_VEND1, 0x7580, &phydata); + LOG_ERR("get rtl8251b phy 0x7580 phydata=0x%x\n", phydata); + + ret = MmdPhyRead(g_handle, MMD_VEND1, 0x758D, &phydata); + LOG_ERR("get rtl8251b phy 0x758D phydata=0x%x\n", phydata); + + ret = MmdPhyRead(g_handle, MMD_VEND1, 0x6973, &phydata); + LOG_ERR("get rtl8251b phy 0x6973 phydata=0x%x\n", phydata); + + return 0; +} + + + +/****************************************************************************** +* +* rtl8251_phy_init - +* +*******************************************************************************/ + + +int rtl8251b_init_common(a_uint32_t dev_id, a_uint32_t port_bmp) +{ + BOOL ret; + PHY_LINK_ABILITY phy_ability; + PHY_EEE_ENABLE eee_enable; + +#ifdef GE550V2_RTL8372_RTL8251B + ret = Rtl8251b_phy_init(g_handle, &phy_ability, TRUE); + ERR_PRINT(ret); + + if (g_mdio_num == RTL8251B_WAN_MDIO_NUM) + { + ret = Rtl8251b_serdes_autoNego_set(g_handle, TRUE); + ERR_PRINT(ret); + + // ret = Rtl8251b_serdes_option_set(g_handle, PHY_SERDES_SPEED_USXGMII); + // ERR_PRINT(ret); + } + else + { + ret = Rtl8251b_serdes_autoNego_set(g_handle, FALSE); + ERR_PRINT(ret); + + ret = Rtl8251b_serdes_option_set(g_handle, PHY_SERDES_SPEED_USXGMII); + ERR_PRINT(ret); + } + + ret = Rtl8251b_phy_reset(g_handle); + ERR_PRINT(ret); +#else + ret = Rtl8251b_phy_init(g_handle, &phy_ability, TRUE); + ERR_PRINT(ret); +#endif + + phy_ability.Half_10 = 1; + phy_ability.Full_10 = 1; + phy_ability.Half_100 = 1; + phy_ability.Full_100 = 1; + phy_ability.Full_1000 = 1; + phy_ability.adv_2_5G = 1; + phy_ability.adv_5G = 1; + phy_ability.FC = 1; + phy_ability.AsyFC = 1; + ret = Rtl8251b_autoNegoAbility_set(g_handle, &phy_ability); + ERR_PRINT(ret); + + ret = Rtl8251b_autoNegoEnable_set(g_handle, TRUE); + ERR_PRINT(ret); + + eee_enable.EEE_100 = 0; + eee_enable.EEE_1000 = 0; + eee_enable.EEE_2_5G = 0; + eee_enable.EEE_5G = 0; + ret = Rtl8251b_eeeEnable_set(g_handle, &eee_enable); + ERR_PRINT(ret); + + ret = Rtl8251b_greenEnable_set(g_handle, FALSE); + ERR_PRINT(ret); + + Rtl8251b_enable_set(g_handle, TRUE); + + // _status_get(); + + return 0; +} + +int rtl8251b_lan_init(a_uint32_t dev_id, a_uint32_t port_bmp, int mdio_num) +{ + g_mdio_num = mdio_num; + rtl8251b_init_common(dev_id,port_bmp); + return 0; +} +int rtl8251b_wan_init(a_uint32_t dev_id, a_uint32_t port_bmp, int mdio_num) +{ + g_mdio_num = mdio_num; + rtl8251b_init_common(dev_id,port_bmp); + return 0; +} + +int rtl8251b_init(struct phy_ops **ops, u32 phy_addr) +{ + static int rtl8251_is_init = 0; + struct phy_ops *rtl8251_phy_ops; + rtl8251_phy_ops = (struct phy_ops *)malloc(sizeof(struct phy_ops)); + if (!rtl8251_phy_ops) + return -ENOMEM; + rtl8251_phy_ops->phy_get_link_status = rtl8251_phy_get_link_status; + rtl8251_phy_ops->phy_get_speed = rtl8251_phy_get_speed; + rtl8251_phy_ops->phy_get_duplex = rtl8251_phy_get_duplex; + *ops = rtl8251_phy_ops; + + if (rtl8251_is_init == 0) + { + rtl8251b_gpio_reset(RTL8251B_LAN_RST_GPIO); //LAN hardware reset + rtl8251b_lan_init(0,0, RTL8251B_LAN_MDIO_NUM); + rtl8251b_gpio_reset(RTL8251B_WAN_RST_GPIO); //LAN hardware reset + rtl8251b_lan_init(0,0, RTL8251B_WAN_MDIO_NUM); + rtl8251_is_init = 1; + } + + return 0; +} + +#endif /* CONFIG_TP_EXT_PHY_RTL8251B */ + +/* + * EDMA hardware instance + */ +static u32 ipq5332_edma_hw_addr; + +/* + * ipq5332_edma_reg_read() + * Read EDMA register + */ +uint32_t ipq5332_edma_reg_read(uint32_t reg_off) +{ + return (uint32_t)readl(ipq5332_edma_hw_addr + reg_off); +} + +/* + * ipq5332_edma_reg_write() + * Write EDMA register + */ +void ipq5332_edma_reg_write(uint32_t reg_off, uint32_t val) +{ + writel(val, (ipq5332_edma_hw_addr + reg_off)); +} + +/* + * ipq5332_edma_alloc_rx_buffer() + * Alloc Rx buffers for one RxFill ring + */ +int ipq5332_edma_alloc_rx_buffer(struct ipq5332_edma_hw *ehw, + struct ipq5332_edma_rxfill_ring *rxfill_ring) +{ + uint16_t num_alloc = 0; + uint16_t cons, next, counter; + struct ipq5332_edma_rxfill_desc *rxfill_desc; + uint32_t reg_data; + + /* + * Read RXFILL ring producer index + */ + reg_data = ipq5332_edma_reg_read(IPQ5332_EDMA_REG_RXFILL_PROD_IDX( + rxfill_ring->id)); + + next = reg_data & IPQ5332_EDMA_RXFILL_PROD_IDX_MASK & + (rxfill_ring->count - 1); + + /* + * Read RXFILL ring consumer index + */ + reg_data = ipq5332_edma_reg_read(IPQ5332_EDMA_REG_RXFILL_CONS_IDX( + rxfill_ring->id)); + + cons = reg_data & IPQ5332_EDMA_RXFILL_CONS_IDX_MASK; + + while (1) { + counter = next; + + if (++counter == rxfill_ring->count) + counter = 0; + + if (counter == cons) + break; + + /* + * Get RXFILL descriptor + */ + rxfill_desc = IPQ5332_EDMA_RXFILL_DESC(rxfill_ring, next); + + /* + * Fill the opaque value + */ + rxfill_desc->rdes2 = next; + + /* + * Save buffer size in RXFILL descriptor + */ + rxfill_desc->rdes1 |= cpu_to_le32((IPQ5332_EDMA_RX_BUFF_SIZE << + IPQ5332_EDMA_RXFILL_BUF_SIZE_SHIFT) & + IPQ5332_EDMA_RXFILL_BUF_SIZE_MASK); + num_alloc++; + next = counter; + } + + if (num_alloc) { + /* + * Update RXFILL ring producer index + */ + reg_data = next & IPQ5332_EDMA_RXFILL_PROD_IDX_MASK; + + /* + * make sure the producer index updated before + * updating the hardware + */ + ipq5332_edma_reg_write(IPQ5332_EDMA_REG_RXFILL_PROD_IDX( + rxfill_ring->id), reg_data); + + pr_debug("%s: num_alloc = %d\n", __func__, num_alloc); + } + + return num_alloc; +} + +/* + * ipq5332_edma_clean_tx() + * Reap Tx descriptors + */ +uint32_t ipq5332_edma_clean_tx(struct ipq5332_edma_hw *ehw, + struct ipq5332_edma_txcmpl_ring *txcmpl_ring) +{ + struct ipq5332_edma_txcmpl_desc *txcmpl_desc; + uint16_t prod_idx, cons_idx; + uint32_t data; + uint32_t txcmpl_consumed = 0; + uchar *skb; + + /* + * Get TXCMPL ring producer index + */ + data = ipq5332_edma_reg_read(IPQ5332_EDMA_REG_TXCMPL_PROD_IDX( + txcmpl_ring->id)); + prod_idx = data & IPQ5332_EDMA_TXCMPL_PROD_IDX_MASK; + + /* + * Get TXCMPL ring consumer index + */ + data = ipq5332_edma_reg_read(IPQ5332_EDMA_REG_TXCMPL_CONS_IDX( + txcmpl_ring->id)); + cons_idx = data & IPQ5332_EDMA_TXCMPL_CONS_IDX_MASK; + + while (cons_idx != prod_idx) { + + txcmpl_desc = IPQ5332_EDMA_TXCMPL_DESC(txcmpl_ring, cons_idx); + + skb = (uchar *)txcmpl_desc->tdes0; + + if (unlikely(!skb)) { + printf("Invalid skb: cons_idx:%u prod_idx:%u\n", + cons_idx, prod_idx); + } + + if (++cons_idx == txcmpl_ring->count) + cons_idx = 0; + + txcmpl_consumed++; + } + + pr_debug("%s :%u txcmpl_consumed:%u prod_idx:%u cons_idx:%u\n", + __func__, txcmpl_ring->id, txcmpl_consumed, prod_idx, + cons_idx); + + if (txcmpl_consumed == 0) + return 0; + + /* + * Update TXCMPL ring consumer index + */ + ipq5332_edma_reg_write(IPQ5332_EDMA_REG_TXCMPL_CONS_IDX( + txcmpl_ring->id), cons_idx); + + return txcmpl_consumed; +} + +/* + * ipq5332_edma_clean_rx() + * Reap Rx descriptors + */ +uint32_t ipq5332_edma_clean_rx(struct ipq5332_edma_common_info *c_info, + struct ipq5332_edma_rxdesc_ring *rxdesc_ring) +{ + void *skb; + struct ipq5332_edma_rxdesc_desc *rxdesc_desc; + uint16_t prod_idx, cons_idx; + int src_port_num; + int pkt_length; + int rx = CONFIG_SYS_RX_ETH_BUFFER; + u16 cleaned_count = 0; + struct ipq5332_edma_hw *ehw = &c_info->hw; + + pr_debug("%s: rxdesc_ring->id = %d\n", __func__, rxdesc_ring->id); + /* + * Read Rx ring consumer index + */ + cons_idx = ipq5332_edma_reg_read(IPQ5332_EDMA_REG_RXDESC_CONS_IDX( + rxdesc_ring->id)) & + IPQ5332_EDMA_RXDESC_CONS_IDX_MASK; + + while (rx) { + /* + * Read Rx ring producer index + */ + prod_idx = ipq5332_edma_reg_read( + IPQ5332_EDMA_REG_RXDESC_PROD_IDX(rxdesc_ring->id)) + & IPQ5332_EDMA_RXDESC_PROD_IDX_MASK; + + if (cons_idx == prod_idx) { + pr_debug("%s: cons idx = %u, prod idx = %u\n", + __func__, cons_idx, prod_idx); + break; + } + + rxdesc_desc = IPQ5332_EDMA_RXDESC_DESC(rxdesc_ring, cons_idx); + + skb = (void *)rxdesc_desc->rdes0; + + rx--; + + /* + * Check src_info from Rx Descriptor + */ + src_port_num = + IPQ5332_EDMA_RXDESC_SRC_INFO_GET(rxdesc_desc->rdes4); + if ((src_port_num & IPQ5332_EDMA_RXDESC_SRCINFO_TYPE_MASK) == + IPQ5332_EDMA_RXDESC_SRCINFO_TYPE_PORTID) { + src_port_num &= IPQ5332_EDMA_RXDESC_PORTNUM_BITS; + } else { + pr_warn("WARN: src_info_type:0x%x. Drop skb:%p\n", + (src_port_num & + IPQ5332_EDMA_RXDESC_SRCINFO_TYPE_MASK), + skb); + goto next_rx_desc; + } + + /* + * Get packet length + */ + pkt_length = (rxdesc_desc->rdes5 & + IPQ5332_EDMA_RXDESC_PKT_SIZE_MASK) >> + IPQ5332_EDMA_RXDESC_PKT_SIZE_SHIFT; + + if (unlikely((src_port_num < IPQ5332_NSS_DP_START_PHY_PORT) || + (src_port_num > IPQ5332_NSS_DP_MAX_PHY_PORTS))) { + pr_warn("WARN: Port number error :%d. Drop skb:%p\n", + src_port_num, skb); + goto next_rx_desc; + } + + cleaned_count++; + + pr_debug("%s: received pkt %p with length %d\n", + __func__, skb, pkt_length); + + net_process_received_packet(skb, pkt_length); +next_rx_desc: + /* + * Update consumer index + */ + if (++cons_idx == rxdesc_ring->count) + cons_idx = 0; + } + + if (cleaned_count) { + ipq5332_edma_alloc_rx_buffer(ehw, rxdesc_ring->rxfill); + ipq5332_edma_reg_write(IPQ5332_EDMA_REG_RXDESC_CONS_IDX( + rxdesc_ring->id), cons_idx); + } + + return 0; +} + +/* + * ipq5332_edma_rx_complete() + */ +static int ipq5332_edma_rx_complete(struct ipq5332_edma_common_info *c_info) +{ + struct ipq5332_edma_hw *ehw = &c_info->hw; + struct ipq5332_edma_txcmpl_ring *txcmpl_ring; + struct ipq5332_edma_rxdesc_ring *rxdesc_ring; + struct ipq5332_edma_rxfill_ring *rxfill_ring; + uint32_t misc_intr_status, reg_data; + int i; + + for (i = 0; i < ehw->rxdesc_rings; i++) { + rxdesc_ring = &ehw->rxdesc_ring[i]; + ipq5332_edma_clean_rx(c_info, rxdesc_ring); + } + + for (i = 0; i < ehw->txcmpl_rings; i++) { + txcmpl_ring = &ehw->txcmpl_ring[i]; + ipq5332_edma_clean_tx(ehw, txcmpl_ring); + } + + for (i = 0; i < ehw->rxfill_rings; i++) { + rxfill_ring = &ehw->rxfill_ring[i]; + ipq5332_edma_alloc_rx_buffer(ehw, rxfill_ring); + } + + /* + * Enable RXDESC EDMA ring interrupt masks + */ + for (i = 0; i < ehw->rxdesc_rings; i++) { + rxdesc_ring = &ehw->rxdesc_ring[i]; + ipq5332_edma_reg_write( + IPQ5332_EDMA_REG_RXDESC_INT_MASK(rxdesc_ring->id), + ehw->rxdesc_intr_mask); + } + + /* + * Enable TX EDMA ring interrupt masks + */ + for (i = 0; i < ehw->txcmpl_rings; i++) { + txcmpl_ring = &ehw->txcmpl_ring[i]; + ipq5332_edma_reg_write(IPQ5332_EDMA_REG_TX_INT_MASK( + txcmpl_ring->id), + ehw->txcmpl_intr_mask); + } + + /* + * Enable RXFILL EDMA ring interrupt masks + */ + for (i = 0; i < ehw->rxfill_rings; i++) { + rxfill_ring = &ehw->rxfill_ring[i]; + ipq5332_edma_reg_write(IPQ5332_EDMA_REG_RXFILL_INT_MASK( + rxfill_ring->id), + ehw->rxfill_intr_mask); + } + + /* + * Read Misc intr status + */ + reg_data = ipq5332_edma_reg_read(IPQ5332_EDMA_REG_MISC_INT_STAT); + misc_intr_status = reg_data & ehw->misc_intr_mask; + + if (misc_intr_status != 0) { + pr_info("%s: misc_intr_status = 0x%x\n", __func__, + misc_intr_status); + ipq5332_edma_reg_write(IPQ5332_EDMA_REG_MISC_INT_MASK, + IPQ5332_EDMA_MASK_INT_DISABLE); + } + + return 0; +} + +/* + * ipq5332_eth_snd() + * Transmit a packet using an EDMA ring + */ +static int ipq5332_eth_snd(struct eth_device *dev, void *packet, int length) +{ + struct ipq5332_eth_dev *priv = dev->priv; + struct ipq5332_edma_common_info *c_info = priv->c_info; + struct ipq5332_edma_hw *ehw = &c_info->hw; + struct ipq5332_edma_txdesc_desc *txdesc; + struct ipq5332_edma_txdesc_ring *txdesc_ring; + uint16_t hw_next_to_use, hw_next_to_clean, chk_idx; + uint32_t data; + uchar *skb; + + txdesc_ring = ehw->txdesc_ring; + + if (tftp_acl_our_port != tftp_our_port) { + /* Allowing tftp packets */ + ipq5332_ppe_acl_set(3, 0x4, 0x1, tftp_our_port, 0xffff, 0, 0); + tftp_acl_our_port = tftp_our_port; + } + /* + * Read TXDESC ring producer index + */ + data = ipq5332_edma_reg_read(IPQ5332_EDMA_REG_TXDESC_PROD_IDX( + txdesc_ring->id)); + + hw_next_to_use = data & IPQ5332_EDMA_TXDESC_PROD_IDX_MASK; + + pr_debug("%s: txdesc_ring->id = %d\n", __func__, txdesc_ring->id); + + /* + * Read TXDESC ring consumer index + */ + /* + * TODO - read to local variable to optimize uncached access + */ + data = ipq5332_edma_reg_read( + IPQ5332_EDMA_REG_TXDESC_CONS_IDX(txdesc_ring->id)); + + hw_next_to_clean = data & IPQ5332_EDMA_TXDESC_CONS_IDX_MASK; + + /* + * Check for available Tx descriptor + */ + chk_idx = (hw_next_to_use + 1) & (txdesc_ring->count - 1); + + if (chk_idx == hw_next_to_clean) { + pr_info("netdev tx busy"); + return NETDEV_TX_BUSY; + } + + /* + * Get Tx descriptor + */ + txdesc = IPQ5332_EDMA_TXDESC_DESC(txdesc_ring, hw_next_to_use); + + txdesc->tdes1 = 0; + txdesc->tdes2 = 0; + txdesc->tdes3 = 0; + txdesc->tdes4 = 0; + txdesc->tdes5 = 0; + txdesc->tdes6 = 0; + txdesc->tdes7 = 0; + skb = (uchar *)txdesc->tdes0; + + pr_debug("%s: txdesc->tdes0 (buffer addr) = 0x%x length = %d \ + prod_idx = %d cons_idx = %d\n", + __func__, txdesc->tdes0, length, + hw_next_to_use, hw_next_to_clean); + +#ifdef CONFIG_IPQ5332_BRIDGED_MODE + /* VP 0x0 share vsi 2 with port 1-4 */ + /* src is 0x2000, dest is 0x0 */ + txdesc->tdes4 = 0x00002000; +#else + /* + * Populate Tx dst info, port id is macid in dp_dev + * We have separate netdev for each port in Kernel but that is not the + * case in U-Boot. + * This part needs to be fixed to support multiple ports in non bridged + * mode during when all the ports are currently under same netdev. + * + * Currently mac port no. is fixed as 3 for the purpose of testing + */ + txdesc->tdes4 |= + (IPQ5332_EDMA_DST_PORT_TYPE_SET(IPQ5332_EDMA_DST_PORT_TYPE) | + IPQ5332_EDMA_DST_PORT_ID_SET(IPQ5332_EDMA_MAC_PORT_NO)); +#endif + + /* + * Set opaque field + */ + txdesc->tdes2 = cpu_to_le32(skb); + + /* + * copy the packet + */ + memcpy(skb, packet, length); + + /* + * Populate Tx descriptor + */ + txdesc->tdes5 |= ((length << IPQ5332_EDMA_TXDESC_DATA_LENGTH_SHIFT) & + IPQ5332_EDMA_TXDESC_DATA_LENGTH_MASK); + + /* + * Update producer index + */ + hw_next_to_use = (hw_next_to_use + 1) & (txdesc_ring->count - 1); + + /* + * make sure the hw_next_to_use is updated before the + * write to hardware + */ + + ipq5332_edma_reg_write(IPQ5332_EDMA_REG_TXDESC_PROD_IDX( + txdesc_ring->id), hw_next_to_use & + IPQ5332_EDMA_TXDESC_PROD_IDX_MASK); + + pr_debug("%s: successfull\n", __func__); + + return EDMA_TX_OK; +} + +static int ipq5332_eth_recv(struct eth_device *dev) +{ + struct ipq5332_eth_dev *priv = dev->priv; + struct ipq5332_edma_common_info *c_info = priv->c_info; + struct ipq5332_edma_rxdesc_ring *rxdesc_ring; + struct ipq5332_edma_txcmpl_ring *txcmpl_ring; + struct ipq5332_edma_rxfill_ring *rxfill_ring; + struct ipq5332_edma_hw *ehw = &c_info->hw; + volatile u32 reg_data; + u32 rxdesc_intr_status = 0; + u32 txcmpl_intr_status = 0, rxfill_intr_status = 0; + int i; + + /* + * Read RxDesc intr status + */ + for (i = 0; i < ehw->rxdesc_rings; i++) { + rxdesc_ring = &ehw->rxdesc_ring[i]; + + reg_data = ipq5332_edma_reg_read( + IPQ5332_EDMA_REG_RXDESC_INT_STAT( + rxdesc_ring->id)); + rxdesc_intr_status |= reg_data & + IPQ5332_EDMA_RXDESC_RING_INT_STATUS_MASK; + + /* + * Disable RxDesc intr + */ + ipq5332_edma_reg_write(IPQ5332_EDMA_REG_RXDESC_INT_MASK( + rxdesc_ring->id), + IPQ5332_EDMA_MASK_INT_DISABLE); + } + + /* + * Read TxCmpl intr status + */ + for (i = 0; i < ehw->txcmpl_rings; i++) { + txcmpl_ring = &ehw->txcmpl_ring[i]; + + reg_data = ipq5332_edma_reg_read( + IPQ5332_EDMA_REG_TX_INT_STAT( + txcmpl_ring->id)); + txcmpl_intr_status |= reg_data & + IPQ5332_EDMA_TXCMPL_RING_INT_STATUS_MASK; + + /* + * Disable TxCmpl intr + */ + ipq5332_edma_reg_write(IPQ5332_EDMA_REG_TX_INT_MASK( + txcmpl_ring->id), + IPQ5332_EDMA_MASK_INT_DISABLE); + } + + /* + * Read RxFill intr status + */ + for (i = 0; i < ehw->rxfill_rings; i++) { + rxfill_ring = &ehw->rxfill_ring[i]; + + reg_data = ipq5332_edma_reg_read( + IPQ5332_EDMA_REG_RXFILL_INT_STAT( + rxfill_ring->id)); + rxfill_intr_status |= reg_data & + IPQ5332_EDMA_RXFILL_RING_INT_STATUS_MASK; + + /* + * Disable RxFill intr + */ + ipq5332_edma_reg_write(IPQ5332_EDMA_REG_RXFILL_INT_MASK( + rxfill_ring->id), + IPQ5332_EDMA_MASK_INT_DISABLE); + } + + if ((rxdesc_intr_status != 0) || (txcmpl_intr_status != 0) || + (rxfill_intr_status != 0)) { + for (i = 0; i < ehw->rxdesc_rings; i++) { + rxdesc_ring = &ehw->rxdesc_ring[i]; + ipq5332_edma_reg_write(IPQ5332_EDMA_REG_RXDESC_INT_MASK( + rxdesc_ring->id), + IPQ5332_EDMA_MASK_INT_DISABLE); + } + ipq5332_edma_rx_complete(c_info); + } + + return 0; +} + +/* + * ipq5332_edma_setup_ring_resources() + * Allocate/setup resources for EDMA rings + */ +static int ipq5332_edma_setup_ring_resources(struct ipq5332_edma_hw *ehw) +{ + struct ipq5332_edma_txcmpl_ring *txcmpl_ring; + struct ipq5332_edma_txdesc_ring *txdesc_ring; + struct ipq5332_edma_rxfill_ring *rxfill_ring; + struct ipq5332_edma_rxdesc_ring *rxdesc_ring; + struct ipq5332_edma_txdesc_desc *txdesc_desc; + struct ipq5332_edma_rxfill_desc *rxfill_desc; + int i, j, index; + void *tx_buf; + void *rx_buf; + + /* + * Allocate Rx fill ring descriptors + */ + for (i = 0; i < ehw->rxfill_rings; i++) { + rxfill_ring = &ehw->rxfill_ring[i]; + rxfill_ring->count = IPQ5332_EDMA_RX_RING_SIZE; + rxfill_ring->id = ehw->rxfill_ring_start + i; + rxfill_ring->desc = (void *)noncached_alloc( + IPQ5332_EDMA_RXFILL_DESC_SIZE * + rxfill_ring->count, + CONFIG_SYS_CACHELINE_SIZE); + + if (rxfill_ring->desc == NULL) { + pr_info("%s: rxfill_ring->desc alloc error\n", + __func__); + return -ENOMEM; + } + rxfill_ring->dma = virt_to_phys(rxfill_ring->desc); + pr_debug("rxfill ring id = %d, rxfill ring ptr = %p," + "rxfill ring dma = %u\n", + rxfill_ring->id, rxfill_ring->desc, (unsigned int) + rxfill_ring->dma); + + rx_buf = (void *)noncached_alloc(IPQ5332_EDMA_RX_BUFF_SIZE * + rxfill_ring->count, + CONFIG_SYS_CACHELINE_SIZE); + + if (rx_buf == NULL) { + pr_info("%s: rxfill_ring->desc buffer alloc error\n", + __func__); + return -ENOMEM; + } + + /* + * Allocate buffers for each of the desc + */ + for (j = 0; j < rxfill_ring->count; j++) { + rxfill_desc = IPQ5332_EDMA_RXFILL_DESC(rxfill_ring, j); + rxfill_desc->rdes0 = virt_to_phys(rx_buf); + rxfill_desc->rdes1 = 0; + rxfill_desc->rdes2 = 0; + rxfill_desc->rdes3 = 0; + rx_buf += IPQ5332_EDMA_RX_BUFF_SIZE; + } + } + + /* + * Allocate RxDesc ring descriptors + */ + for (i = 0; i < ehw->rxdesc_rings; i++) { + rxdesc_ring = &ehw->rxdesc_ring[i]; + rxdesc_ring->count = IPQ5332_EDMA_RX_RING_SIZE; + rxdesc_ring->id = ehw->rxdesc_ring_start + i; + + /* + * Create a mapping between RX Desc ring and Rx fill ring. + * Number of fill rings are lesser than the descriptor rings + * Share the fill rings across descriptor rings. + */ + index = ehw->rxfill_ring_start + (i % ehw->rxfill_rings); + rxdesc_ring->rxfill = + &ehw->rxfill_ring[index - ehw->rxfill_ring_start]; + rxdesc_ring->rxfill = ehw->rxfill_ring; + + rxdesc_ring->desc = (void *)noncached_alloc( + IPQ5332_EDMA_RXDESC_DESC_SIZE * + rxdesc_ring->count, + CONFIG_SYS_CACHELINE_SIZE); + if (rxdesc_ring->desc == NULL) { + pr_info("%s: rxdesc_ring->desc alloc error\n", + __func__); + return -ENOMEM; + } + rxdesc_ring->dma = virt_to_phys(rxdesc_ring->desc); + + /* + * Allocate secondary Rx ring descriptors + */ + rxdesc_ring->sdesc = (void *)noncached_alloc( + IPQ5332_EDMA_RX_SEC_DESC_SIZE * + rxdesc_ring->count, + CONFIG_SYS_CACHELINE_SIZE); + if (rxdesc_ring->sdesc == NULL) { + pr_info("%s: rxdesc_ring->sdesc alloc error\n", + __func__); + return -ENOMEM; + } + rxdesc_ring->sdma = virt_to_phys(rxdesc_ring->sdesc); + } + + /* + * Allocate TxDesc ring descriptors + */ + for (i = 0; i < ehw->txdesc_rings; i++) { + txdesc_ring = &ehw->txdesc_ring[i]; + txdesc_ring->count = IPQ5332_EDMA_TX_RING_SIZE; + txdesc_ring->id = ehw->txdesc_ring_start + i; + txdesc_ring->desc = (void *)noncached_alloc( + IPQ5332_EDMA_TXDESC_DESC_SIZE * + txdesc_ring->count, + CONFIG_SYS_CACHELINE_SIZE); + if (txdesc_ring->desc == NULL) { + pr_info("%s: txdesc_ring->desc alloc error\n", + __func__); + return -ENOMEM; + } + txdesc_ring->dma = virt_to_phys(txdesc_ring->desc); + + tx_buf = (void *)noncached_alloc(IPQ5332_EDMA_TX_BUFF_SIZE * + txdesc_ring->count, + CONFIG_SYS_CACHELINE_SIZE); + if (tx_buf == NULL) { + pr_info("%s: txdesc_ring->desc buffer alloc error\n", + __func__); + return -ENOMEM; + } + + /* + * Allocate buffers for each of the desc + */ + for (j = 0; j < txdesc_ring->count; j++) { + txdesc_desc = IPQ5332_EDMA_TXDESC_DESC(txdesc_ring, j); + txdesc_desc->tdes0 = virt_to_phys(tx_buf); + txdesc_desc->tdes1 = 0; + txdesc_desc->tdes2 = 0; + txdesc_desc->tdes3 = 0; + txdesc_desc->tdes4 = 0; + txdesc_desc->tdes5 = 0; + txdesc_desc->tdes6 = 0; + txdesc_desc->tdes7 = 0; + tx_buf += IPQ5332_EDMA_TX_BUFF_SIZE; + } + + /* + * Allocate secondary Tx ring descriptors + */ + txdesc_ring->sdesc = (void *)noncached_alloc( + IPQ5332_EDMA_TX_SEC_DESC_SIZE * + txdesc_ring->count, + CONFIG_SYS_CACHELINE_SIZE); + if (txdesc_ring->sdesc == NULL) { + pr_info("%s: txdesc_ring->sdesc alloc error\n", + __func__); + return -ENOMEM; + } + txdesc_ring->sdma = virt_to_phys(txdesc_ring->sdesc); + } + + /* + * Allocate TxCmpl ring descriptors + */ + for (i = 0; i < ehw->txcmpl_rings; i++) { + txcmpl_ring = &ehw->txcmpl_ring[i]; + txcmpl_ring->count = IPQ5332_EDMA_TX_RING_SIZE; + txcmpl_ring->id = ehw->txcmpl_ring_start + i; + txcmpl_ring->desc = (void *)noncached_alloc( + IPQ5332_EDMA_TXCMPL_DESC_SIZE * + txcmpl_ring->count, + CONFIG_SYS_CACHELINE_SIZE); + + if (txcmpl_ring->desc == NULL) { + pr_info("%s: txcmpl_ring->desc alloc error\n", + __func__); + return -ENOMEM; + } + txcmpl_ring->dma = virt_to_phys(txcmpl_ring->desc); + } + + pr_info("%s: successfull\n", __func__); + + return 0; +} + +static void ipq5332_edma_disable_rings(struct ipq5332_edma_hw *edma_hw) +{ + int i, desc_index; + u32 data; + + /* + * Disable Rx rings + */ + for (i = 0; i < IPQ5332_EDMA_MAX_RXDESC_RINGS; i++) { + data = ipq5332_edma_reg_read(IPQ5332_EDMA_REG_RXDESC_CTRL(i)); + data &= ~IPQ5332_EDMA_RXDESC_RX_EN; + ipq5332_edma_reg_write(IPQ5332_EDMA_REG_RXDESC_CTRL(i), data); + } + + /* + * Disable RxFill Rings + */ + for (i = 0; i < IPQ5332_EDMA_MAX_RXFILL_RINGS; i++) { + data = ipq5332_edma_reg_read( + IPQ5332_EDMA_REG_RXFILL_RING_EN(i)); + data &= ~IPQ5332_EDMA_RXFILL_RING_EN; + ipq5332_edma_reg_write( + IPQ5332_EDMA_REG_RXFILL_RING_EN(i), data); + } + + /* + * Disable Tx rings + */ + for (desc_index = 0; desc_index < + IPQ5332_EDMA_MAX_TXDESC_RINGS; desc_index++) { + data = ipq5332_edma_reg_read( + IPQ5332_EDMA_REG_TXDESC_CTRL(desc_index)); + data &= ~IPQ5332_EDMA_TXDESC_TX_EN; + ipq5332_edma_reg_write( + IPQ5332_EDMA_REG_TXDESC_CTRL(desc_index), data); + } +} + +static void ipq5332_edma_disable_intr(struct ipq5332_edma_hw *ehw) +{ + int i; + + /* + * Disable interrupts + */ + for (i = 0; i < IPQ5332_EDMA_MAX_RXDESC_RINGS; i++) + ipq5332_edma_reg_write(IPQ5332_EDMA_REG_RX_INT_CTRL(i), 0); + + for (i = 0; i < IPQ5332_EDMA_MAX_RXFILL_RINGS; i++) + ipq5332_edma_reg_write(IPQ5332_EDMA_REG_RXFILL_INT_MASK(i), 0); + + for (i = 0; i < IPQ5332_EDMA_MAX_TXCMPL_RINGS; i++) + ipq5332_edma_reg_write(IPQ5332_EDMA_REG_TX_INT_MASK(i), 0); + + /* + * Clear MISC interrupt mask + */ + ipq5332_edma_reg_write(IPQ5332_EDMA_REG_MISC_INT_MASK, + IPQ5332_EDMA_MASK_INT_DISABLE); +} + +void print_eth_info(int mac_unit, int phy_id, char *status, int speed, + char *duplex) +{ + printf("eth%d PHY%d %s Speed :%d %s duplex\n",mac_unit, phy_id, + status, speed, duplex); +} + +#ifdef CONFIG_TP_EXT_SWITCH +#ifdef CONFIG_TP_EXT_SWITCH_RTL8367_ALL +static int ipq_rtl8367_Link_Update(void) +{ + rtk_port_linkStatus_t linkStatus = 0; + rtk_port_speed_t speed = 0; + rtk_port_duplex_t duplex = 0; + int status = 1; + + for(int i = UTP_PORT0; i < UTP_PORT5; ++i) + { + if (0 != rtk_port_phyStatus_get(i, &linkStatus, &speed, &duplex)) + { + printf("rtk_port_phyStatus_get error"); + continue; + } + + if (!linkStatus) + { + printf("RTL8367sc port%d not link!!!\n", i); + continue; + } + status = 0; + printf("RTL8367SSC Port%d %s \n", i, LINK_RTL8367(portStatus.link)); + } + return status; +} +#endif +#ifdef CONFIG_TP_EXT_SWITCH_RTL8372 +static int ipq_rtl8372_Link_Update(void) +{ + rtk_port_status_t port_status; + int status = 1; +#ifdef GE550V2_RTL8372_RTL8251B + for(int i = UTP_PORT4; i <= UTP_PORT8; ++i) +#else + for(int i = UTP_PORT4; i <= UTP_PORT7; ++i) +#endif + { + if (0 != dal_rtl8373_portStatus_get(i, &port_status)) + { + printf("dal_rtl8373_portStatus_get error"); + continue; + } + + if (!(port_status.link)) + { + printf("RTL8372 port%d not link!!!\n", i); + continue; + } + status = 0; + printf("RTL8372 Port%d %s \n", i, LINK_RTL8372(ability.link)); + } + return status; +} +#endif +#endif + +static int ipq5332_eth_init(struct eth_device *eth_dev, bd_t *this) +{ + int i; + u8 status = 0; + int mac_speed = 0x1; + struct ipq5332_eth_dev *priv = eth_dev->priv; + struct phy_ops *phy_get_ops; + static fal_port_speed_t old_speed[IPQ5332_PHY_MAX] = + {[0 ... IPQ5332_PHY_MAX-1] = FAL_SPEED_BUTT}; + static fal_port_speed_t curr_speed[IPQ5332_PHY_MAX]; + static int current_active_port = -1, previous_active_port = -1; + fal_port_duplex_t duplex; + char *lstatus[] = {"up", "Down"}; + char *dp[] = {"Half", "Full"}; + int linkup = 0; + int clk[4] = {0}; + int phy_addr = -1, ret = -1; + phy_info_t *phy_info; + int sgmii_mode = EPORT_WRAPPER_SGMII0_RGMII4, sfp_mode = -1; + char *active_port = NULL; + + active_port = getenv("active_port"); + if (active_port != NULL) { + current_active_port = simple_strtol(active_port, NULL, 10); + if (current_active_port < 0 || current_active_port > 1) + printf("active_port must be either 0 or 1\n"); + } else { + current_active_port = -1; + } + + if (previous_active_port != current_active_port && current_active_port != -1) { + previous_active_port = current_active_port; + printf("Port%d has been set as the active_port\n", current_active_port); + } + + /* + * Check PHY link, speed, Duplex on all phys. + * we will proceed even if single link is up + * else we will return with -1; + */ + for (i = 0; i < IPQ5332_PHY_MAX; i++) { + if (current_active_port != -1 && i != current_active_port) { + ipq5332_gmac_port_disable(i); + ppe_port_bridge_txmac_set(i + 1, 1); + old_speed[i] = FAL_SPEED_BUTT; + /* + * Old speed has been set as FAL_SPEED_BUTT here so that + * if again the previous active_port is made as active, + * the configurations required will be done again and MAC + * would be enabled. + * + * Note that only for the active port TX/RX MAC would be + * enabled and for all other ports, the same would be + * disabled. + */ + continue; + } + /* + * set mdio mode and bus no + */ + ipq_set_mdio_mode(mdio_info[i]->mode, mdio_info[i]->bus_no); + + phy_info = port_info[i]->phy_info; + if (phy_info->phy_type == UNUSED_PHY_TYPE) + continue; +#ifdef CONFIG_QCA8084_SWT_MODE + else if ((phy_info->phy_type == QCA8084_PHY_TYPE) && + (priv->ops[i] == NULL)) { + printf("eth0 PHY%d ", i); + if (!ipq_qca8084_link_update(swt_info)) + linkup++; + continue; + } +#endif +#ifdef CONFIG_ATHRS17C_SWITCH + else if (phy_info->phy_type == ATHRS17C_SWITCH_TYPE) { + if (s17c_swt_cfg[i].chip_detect) { + if (!ipq_qca8337_link_update(&s17c_swt_cfg[i])) + linkup++; + continue; + } + } +#endif +#ifdef CONFIG_TP_EXT_SWITCH +#ifdef CONFIG_TP_EXT_SWITCH_RTL8367_ALL + else if ((i == 1) && (priv->rtl8367_switch_enable == 1)) + { + if (!ipq_rtl8367_Link_Update()) + linkup++; + continue; + } +#endif +#ifdef CONFIG_TP_EXT_SWITCH_RTL8372 + else if ((i == 1) && (priv->rtl8372_switch_enable == 1)) + { + if (!ipq_rtl8372_Link_Update()) + linkup++; + continue; + } +#endif +#endif +#ifdef CONFIG_TP_EXT_PHY_RTL8221B + else if ((i == 0) && (priv->rtl8221_enable == 1)) + { +#ifdef CONFIG_TP_EXT_PHY_RTL8221B_LAN + if (!ipq_rtl8221_Link_Update(6)) + { + linkup++; + status_get(); + } +#endif + if (!ipq_rtl8221_Link_Update(7)) + { + linkup++; + status_get(); + } + + continue; + } +#endif + else if (phy_info->phy_type == SFP_PHY_TYPE) { + status = phy_status_get_from_ppe(i); + duplex = FAL_FULL_DUPLEX; + sfp_mode = port_info[i]->mode; + + if (sfp_mode == EPORT_WRAPPER_SGMII_FIBER) { + curr_speed[i] = FAL_SPEED_1000; + } else if (sfp_mode == EPORT_WRAPPER_10GBASE_R) { + curr_speed[i] = FAL_SPEED_10000; + } else if (sfp_mode == EPORT_WRAPPER_SGMII_PLUS) { + curr_speed[i] = FAL_SPEED_2500; + } else { + printf("Error: Unsupported SPF mode \n"); + return ret; + } + } else { + if (!priv->ops[i]) { + printf("Phy ops not mapped\n"); + continue; + } + phy_get_ops = priv->ops[i]; + phy_addr = phy_info->phy_address; + + if (!phy_get_ops->phy_get_link_status || + !phy_get_ops->phy_get_speed || + !phy_get_ops->phy_get_duplex) { + printf("Error:Link status/Get speed/" + "Get duplex not mapped\n"); + return ret; + } + + status = phy_get_ops->phy_get_link_status( + priv->mac_unit, phy_addr); + phy_get_ops->phy_get_speed(priv->mac_unit, + phy_addr, &curr_speed[i]); + phy_get_ops->phy_get_duplex(priv->mac_unit, + phy_addr, &duplex); + } + + if (status == 0) { + linkup++; + if (old_speed[i] == curr_speed[i]) { + print_eth_info(priv->mac_unit, i, + lstatus[status], + curr_speed[i], + dp[duplex]); + continue; + } else { + old_speed[i] = curr_speed[i]; + } + } else { + print_eth_info(priv->mac_unit, i, + lstatus[status], + curr_speed[i], + dp[duplex]); + continue; + } + /* + * Note: If the current port link is up and its speed is + * different from its initially configured speed, only then + * below re-configuration is done. + * + * These conditions are checked above and if any of it + * fails, then no config is done for that eth port. + * clk[0-3] = { RX_RCGR, RX_DIV, TX_RCGR, TX_DIV} + */ + switch (curr_speed[i]) { + case FAL_SPEED_10: + mac_speed = 0x0; + clk[0] = 0x318; + clk[1] = 9; + clk[2] = 0x418; + clk[3] = 9; + if ((phy_info->phy_type == QCA8081_PHY_TYPE) || + (phy_info->phy_type == QCA8033_PHY_TYPE)) { + clk[1] = 3; + clk[3] = 3; + } + + if (phy_info->phy_type == QCA8084_PHY_TYPE) { + clk[0] = 0x309; + clk[2] = 0x409; + } + break; + case FAL_SPEED_100: + mac_speed = 0x1; + clk[0] = 0x318; + clk[1] = 1; + clk[2] = 0x418; + clk[3] = 1; + if ((phy_info->phy_type == QCA8081_PHY_TYPE) || + (phy_info->phy_type == QCA8084_PHY_TYPE) || + (phy_info->phy_type == QCA8033_PHY_TYPE)) { + clk[0] = 0x309; + clk[1] = 0; + clk[2] = 0x409; + clk[3] = 0; + } + break; + case FAL_SPEED_1000: + mac_speed = 0x2; + clk[0] = 0x304; + clk[1] = 0x0; + clk[2] = 0x404; + clk[3] = 0x0; + if ((phy_info->phy_type == QCA8081_PHY_TYPE) || + (phy_info->phy_type == QCA8084_PHY_TYPE) || + (phy_info->phy_type == QCA8033_PHY_TYPE)) { + clk[0] = 0x301; + clk[2] = 0x401; + } + break; + case FAL_SPEED_2500: + mac_speed = 0x4; + clk[0] = 0x307; + clk[1] = 0x0; + clk[2] = 0x407; + clk[3] = 0x0; + if ((phy_info->phy_type == SFP_PHY_TYPE) || + (phy_info->phy_type == QCA8081_PHY_TYPE) || + (phy_info->phy_type == QCA8084_PHY_TYPE)) { + clk[0] = 0x301; + clk[2] = 0x401; + } + + if ((phy_info->phy_type == QCA8081_PHY_TYPE) || + (phy_info->phy_type == QCA8084_PHY_TYPE)) { + sgmii_mode = EPORT_WRAPPER_SGMII_PLUS; + } + break; + case FAL_SPEED_5000: + mac_speed = 0x5; + clk[0] = 0x303; + clk[1] = 0x0; + clk[2] = 0x403; + clk[3] = 0x0; + break; + case FAL_SPEED_10000: + mac_speed = 0x3; + clk[1] = 0x0; + clk[3] = 0x0; + clk[0] = 0x301; + clk[2] = 0x401; + break; + default: + ret = FAL_SPEED_BUTT; + break; + } + + if (ret == FAL_SPEED_BUTT) { + printf("Unknown speed\n"); + ret = -1; + } else { + print_eth_info(priv->mac_unit, i, lstatus[status], + curr_speed[i], dp[duplex]); + } + + if ((phy_info->phy_type == QCA8081_PHY_TYPE) || + (phy_info->phy_type == QCA8033_PHY_TYPE) || + (phy_info->phy_type == QCA8084_PHY_TYPE)) { + ppe_port_bridge_txmac_set(i, 1); + ppe_uniphy_mode_set(port_info[i]->uniphy_id, + sgmii_mode); + ppe_port_mux_mac_type_set(i + 1, sgmii_mode); + } + + if (phy_info->phy_type == SFP_PHY_TYPE) { + if (sfp_mode == EPORT_WRAPPER_SGMII_FIBER) { + /* SGMII Fiber mode */ + ppe_port_bridge_txmac_set(i, 1); + ppe_uniphy_mode_set(port_info[i]->uniphy_id, + EPORT_WRAPPER_SGMII_FIBER); + ppe_port_mux_mac_type_set(i + 1, + EPORT_WRAPPER_SGMII_FIBER); + } else if (sfp_mode == EPORT_WRAPPER_10GBASE_R) { + /* 10GBASE_R mode */ + ppe_uniphy_mode_set(port_info[i]->uniphy_id, + EPORT_WRAPPER_10GBASE_R); + ppe_port_mux_mac_type_set(i + 1, + EPORT_WRAPPER_10GBASE_R); + } else { /* SGMII Plus Mode */ + ppe_port_bridge_txmac_set(i, 1); + ppe_uniphy_mode_set(port_info[i]->uniphy_id, + EPORT_WRAPPER_SGMII_PLUS); + } + } + +#ifdef CONFIG_QCA8084_BYPASS_MODE + if (phy_info->phy_type == QCA8084_PHY_TYPE) { + if (curr_speed[i] == FAL_SPEED_2500) { + qca8084_phy_sgmii_mode_set(PORT4, + PORT_SGMII_PLUS, status, curr_speed[i]); + } + else { + qca8084_phy_sgmii_mode_set(PORT4, + PHY_SGMII_BASET, status, curr_speed[i]); + } + } +#endif /* CONFIG_QCA8084_BYPASS_MODE */ + + ipq5332_port_mac_clock_reset(i); + +#ifdef CONFIG_TP_EXT_PHY_RTL8251B + if (phy_info->phy_type == AQ_PHY_TYPE || phy_info->phy_type == RTL8251B_PHY_TYPE){ +#else + if (phy_info->phy_type == AQ_PHY_TYPE){ +#endif + ipq5332_uxsgmii_speed_set(i, mac_speed, duplex, status); + } else if ((phy_info->phy_type == SFP_PHY_TYPE) && + (sfp_mode != EPORT_WRAPPER_SGMII_FIBER)) { + ipq5332_10g_r_speed_set(i, status); + } else { + if (curr_speed[i] == FAL_SPEED_2500) { + ipq5332_xgmac_sgmiiplus_speed_set(i, + mac_speed, status); + } else { + ipq5332_pqsgmii_speed_set(i, + mac_speed, status); + } + } + + ipq5332_speed_clock_set(i, clk); + } + + if (linkup <= 0) { + /* No PHY link is alive */ + return -1; + } + + pr_info("%s: done\n", __func__); + + return 0; +} + +static int ipq5332_edma_wr_macaddr(struct eth_device *dev) +{ + return 0; +} + +static void ipq5332_eth_halt(struct eth_device *dev) +{ + pr_debug("\n\n*****GMAC0 info*****\n"); + pr_debug("GMAC0 RXPAUSE(0x3a001044):%x\n", readl(0x3a001044)); + pr_debug("GMAC0 TXPAUSE(0x3a0010A4):%x\n", readl(0x3a0010A4)); + pr_debug("GMAC0 RXGOODBYTE_L(0x3a001084):%x\n", readl(0x3a001084)); + pr_debug("GMAC0 RXGOODBYTE_H(0x3a001088):%x\n", readl(0x3a001088)); + pr_debug("GMAC0 RXBADBYTE_L(0x3a00108c):%x\n", readl(0x3a00108c)); + pr_debug("GMAC0 RXBADBYTE_H(0x3a001090):%x\n", readl(0x3a001090)); + + pr_debug("\n\n*****GMAC1 info*****\n"); + pr_debug("GMAC1 RXPAUSE(0x3a001244):%x\n", readl(0x3a001244)); + pr_debug("GMAC1 TXPAUSE(0x3a0012A4):%x\n", readl(0x3a0012A4)); + pr_debug("GMAC1 RXGOODBYTE_L(0x3a001284):%x\n", readl(0x3a001284)); + pr_debug("GMAC1 RXGOODBYTE_H(0x3a001288):%x\n", readl(0x3a001288)); + pr_debug("GMAC1 RXBADBYTE_L(0x3a00128c):%x\n", readl(0x3a00128c)); + pr_debug("GMAC1 RXBADBYTE_H(0x3a001290):%x\n", readl(0x3a001290)); + + pr_info("%s: done\n", __func__); +} + +static void ipq5332_edma_set_ring_values(struct ipq5332_edma_hw *edma_hw) +{ + edma_hw->txdesc_ring_start = IPQ5332_EDMA_TX_DESC_RING_START; + edma_hw->txdesc_rings = IPQ5332_EDMA_TX_DESC_RING_NOS; + edma_hw->txdesc_ring_end = IPQ5332_EDMA_TX_DESC_RING_SIZE; + + edma_hw->txcmpl_ring_start = IPQ5332_EDMA_TX_CMPL_RING_START; + edma_hw->txcmpl_rings = IPQ5332_EDMA_TX_CMPL_RING_NOS; + edma_hw->txcmpl_ring_end = IPQ5332_EDMA_TX_CMPL_RING_SIZE; + + edma_hw->rxfill_ring_start = IPQ5332_EDMA_RX_FILL_RING_START; + edma_hw->rxfill_rings = IPQ5332_EDMA_RX_FILL_RING_NOS; + edma_hw->rxfill_ring_end = IPQ5332_EDMA_RX_FILL_RING_SIZE; + + edma_hw->rxdesc_ring_start = IPQ5332_EDMA_RX_DESC_RING_START; + edma_hw->rxdesc_rings = IPQ5332_EDMA_RX_DESC_RING_NOS; + edma_hw->rxdesc_ring_end = IPQ5332_EDMA_RX_DESC_RING_SIZE; + + pr_info("Num rings - TxDesc:%u (%u-%u) TxCmpl:%u (%u-%u)\n", + edma_hw->txdesc_rings, edma_hw->txdesc_ring_start, + (edma_hw->txdesc_ring_start + edma_hw->txdesc_rings - 1), + edma_hw->txcmpl_rings, edma_hw->txcmpl_ring_start, + (edma_hw->txcmpl_ring_start + edma_hw->txcmpl_rings - 1)); + + pr_info("RxDesc:%u (%u-%u) RxFill:%u (%u-%u)\n", + edma_hw->rxdesc_rings, edma_hw->rxdesc_ring_start, + (edma_hw->rxdesc_ring_start + edma_hw->rxdesc_rings - 1), + edma_hw->rxfill_rings, edma_hw->rxfill_ring_start, + (edma_hw->rxfill_ring_start + edma_hw->rxfill_rings - 1)); +} + +/* + * ipq5332_edma_alloc_rings() + * Allocate EDMA software rings + */ +static int ipq5332_edma_alloc_rings(struct ipq5332_edma_hw *ehw) +{ + ehw->rxfill_ring = (void *)noncached_alloc((sizeof( + struct ipq5332_edma_rxfill_ring) * + ehw->rxfill_rings), + CONFIG_SYS_CACHELINE_SIZE); + if (!ehw->rxfill_ring) { + pr_info("%s: rxfill_ring alloc error\n", __func__); + return -ENOMEM; + } + + ehw->rxdesc_ring = (void *)noncached_alloc((sizeof( + struct ipq5332_edma_rxdesc_ring) * + ehw->rxdesc_rings), + CONFIG_SYS_CACHELINE_SIZE); + if (!ehw->rxdesc_ring) { + pr_info("%s: rxdesc_ring alloc error\n", __func__); + return -ENOMEM; + } + + ehw->txdesc_ring = (void *)noncached_alloc((sizeof( + struct ipq5332_edma_txdesc_ring) * + ehw->txdesc_rings), + CONFIG_SYS_CACHELINE_SIZE); + if (!ehw->txdesc_ring) { + pr_info("%s: txdesc_ring alloc error\n", __func__); + return -ENOMEM; + } + + ehw->txcmpl_ring = (void *)noncached_alloc((sizeof( + struct ipq5332_edma_txcmpl_ring) * + ehw->txcmpl_rings), + CONFIG_SYS_CACHELINE_SIZE); + if (!ehw->txcmpl_ring) { + pr_info("%s: txcmpl_ring alloc error\n", __func__); + return -ENOMEM; + } + + pr_info("%s: successfull\n", __func__); + + return 0; + +} + + +/* + * ipq5332_edma_init_rings() + * Initialize EDMA rings + */ +static int ipq5332_edma_init_rings(struct ipq5332_edma_hw *ehw) +{ + int ret; + + /* + * Setup ring values + */ + ipq5332_edma_set_ring_values(ehw); + + /* + * Allocate desc rings + */ + ret = ipq5332_edma_alloc_rings(ehw); + if (ret) + return ret; + + /* + * Setup ring resources + */ + ret = ipq5332_edma_setup_ring_resources(ehw); + if (ret) + return ret; + + return 0; +} + +/* + * ipq5332_edma_configure_txdesc_ring() + * Configure one TxDesc ring + */ +static void ipq5332_edma_configure_txdesc_ring(struct ipq5332_edma_hw *ehw, + struct ipq5332_edma_txdesc_ring *txdesc_ring) +{ + /* + * Configure TXDESC ring + */ + ipq5332_edma_reg_write(IPQ5332_EDMA_REG_TXDESC_BA(txdesc_ring->id), + (uint32_t)(txdesc_ring->dma & + IPQ5332_EDMA_RING_DMA_MASK)); + + ipq5332_edma_reg_write(IPQ5332_EDMA_REG_TXDESC_BA2(txdesc_ring->id), + (uint32_t)(txdesc_ring->sdma & + IPQ5332_EDMA_RING_DMA_MASK)); + + ipq5332_edma_reg_write(IPQ5332_EDMA_REG_TXDESC_RING_SIZE( + txdesc_ring->id), (uint32_t)(txdesc_ring->count & + IPQ5332_EDMA_TXDESC_RING_SIZE_MASK)); + + ipq5332_edma_reg_write(IPQ5332_EDMA_REG_TXDESC_PROD_IDX( + txdesc_ring->id), + IPQ5332_EDMA_TX_INITIAL_PROD_IDX); +} + +/* + * ipq5332_edma_configure_txcmpl_ring() + * Configure one TxCmpl ring + */ +static void ipq5332_edma_configure_txcmpl_ring(struct ipq5332_edma_hw *ehw, + struct ipq5332_edma_txcmpl_ring *txcmpl_ring) +{ + /* + * Configure TxCmpl ring base address + */ + ipq5332_edma_reg_write(IPQ5332_EDMA_REG_TXCMPL_BA(txcmpl_ring->id), + (uint32_t)(txcmpl_ring->dma & + IPQ5332_EDMA_RING_DMA_MASK)); + + ipq5332_edma_reg_write(IPQ5332_EDMA_REG_TXCMPL_RING_SIZE( + txcmpl_ring->id), (uint32_t)(txcmpl_ring->count & + IPQ5332_EDMA_TXDESC_RING_SIZE_MASK)); + + /* + * Set TxCmpl ret mode to opaque + */ + ipq5332_edma_reg_write(IPQ5332_EDMA_REG_TXCMPL_CTRL(txcmpl_ring->id), + IPQ5332_EDMA_TXCMPL_RETMODE_OPAQUE); + + /* + * Enable ring. Set ret mode to 'opaque'. + */ + ipq5332_edma_reg_write(IPQ5332_EDMA_REG_TX_INT_CTRL(txcmpl_ring->id), + IPQ5332_EDMA_TX_NE_INT_EN); +} + +/* + * ipq5332_edma_configure_rxdesc_ring() + * Configure one RxDesc ring + */ +static void ipq5332_edma_configure_rxdesc_ring(struct ipq5332_edma_hw *ehw, + struct ipq5332_edma_rxdesc_ring *rxdesc_ring) +{ + uint32_t data; + + ipq5332_edma_reg_write(IPQ5332_EDMA_REG_RXDESC_BA(rxdesc_ring->id), + (uint32_t)(rxdesc_ring->dma & IPQ5332_EDMA_RING_DMA_MASK)); + + ipq5332_edma_reg_write(IPQ5332_EDMA_REG_RXDESC_BA2(rxdesc_ring->id), + (uint32_t)(rxdesc_ring->sdma & IPQ5332_EDMA_RING_DMA_MASK)); + + data = rxdesc_ring->count & IPQ5332_EDMA_RXDESC_RING_SIZE_MASK; + data |= (ehw->rx_payload_offset & IPQ5332_EDMA_RXDESC_PL_OFFSET_MASK) << + IPQ5332_EDMA_RXDESC_PL_OFFSET_SHIFT; + + ipq5332_edma_reg_write(IPQ5332_EDMA_REG_RXDESC_RING_SIZE( + rxdesc_ring->id), data); + + /* + * Enable ring. Set ret mode to 'opaque'. + */ + ipq5332_edma_reg_write(IPQ5332_EDMA_REG_RX_INT_CTRL(rxdesc_ring->id), + IPQ5332_EDMA_RX_NE_INT_EN); +} + +/* + * ipq5332_edma_configure_rxfill_ring() + * Configure one RxFill ring + */ +static void ipq5332_edma_configure_rxfill_ring(struct ipq5332_edma_hw *ehw, + struct ipq5332_edma_rxfill_ring *rxfill_ring) +{ + uint32_t data; + + ipq5332_edma_reg_write(IPQ5332_EDMA_REG_RXFILL_BA(rxfill_ring->id), + (uint32_t)(rxfill_ring->dma & + IPQ5332_EDMA_RING_DMA_MASK)); + + data = rxfill_ring->count & IPQ5332_EDMA_RXFILL_RING_SIZE_MASK; + + ipq5332_edma_reg_write( + IPQ5332_EDMA_REG_RXFILL_RING_SIZE(rxfill_ring->id), data); +} + + +/* + * ipq5332_edma_configure_rings() + * Configure EDMA rings + */ +static void ipq5332_edma_configure_rings(struct ipq5332_edma_hw *ehw) +{ + int i; + + /* + * Configure TXDESC ring + */ + for (i = 0; i < ehw->txdesc_rings; i++) + ipq5332_edma_configure_txdesc_ring(ehw, &ehw->txdesc_ring[i]); + + /* + * Configure TXCMPL ring + */ + for (i = 0; i < ehw->txcmpl_rings; i++) + ipq5332_edma_configure_txcmpl_ring(ehw, &ehw->txcmpl_ring[i]); + + /* + * Configure RXFILL rings + */ + for (i = 0; i < ehw->rxfill_rings; i++) + ipq5332_edma_configure_rxfill_ring(ehw, &ehw->rxfill_ring[i]); + + /* + * Configure RXDESC ring + */ + for (i = 0; i < ehw->rxdesc_rings; i++) + ipq5332_edma_configure_rxdesc_ring(ehw, &ehw->rxdesc_ring[i]); + + pr_info("%s: successfull\n", __func__); +} +/* + * ipq5332_edma_hw_init() + * EDMA hw init + */ +int ipq5332_edma_hw_init(struct ipq5332_edma_hw *ehw) +{ + int ret, desc_index; + uint32_t i, reg, reg_idx, ring_id; + volatile uint32_t data; + + struct ipq5332_edma_rxdesc_ring *rxdesc_ring = NULL; + + ipq5332_ppe_provision_init(); + + data = ipq5332_edma_reg_read(IPQ5332_EDMA_REG_MAS_CTRL); + printf("EDMA ver %d hw init\n", data); + + /* + * Setup private data structure + */ + ehw->rxfill_intr_mask = IPQ5332_EDMA_RXFILL_INT_MASK; + ehw->rxdesc_intr_mask = IPQ5332_EDMA_RXDESC_INT_MASK_PKT_INT; + ehw->txcmpl_intr_mask = IPQ5332_EDMA_TX_INT_MASK_PKT_INT; + ehw->misc_intr_mask = 0xff; + ehw->rx_payload_offset = 0x0; + + /* + * Disable interrupts + */ + ipq5332_edma_disable_intr(ehw); + + /* + * Disable rings + */ + ipq5332_edma_disable_rings(ehw); + + ret = ipq5332_edma_init_rings(ehw); + if (ret) + return ret; + + ipq5332_edma_configure_rings(ehw); + + /* + * Clear the TXDESC2CMPL_MAP_xx reg before setting up + * the mapping. This register holds TXDESC to TXFILL ring + * mapping. + */ + ipq5332_edma_reg_write(IPQ5332_EDMA_REG_TXDESC2CMPL_MAP_0, 0); + ipq5332_edma_reg_write(IPQ5332_EDMA_REG_TXDESC2CMPL_MAP_1, 0); + ipq5332_edma_reg_write(IPQ5332_EDMA_REG_TXDESC2CMPL_MAP_2, 0); + ipq5332_edma_reg_write(IPQ5332_EDMA_REG_TXDESC2CMPL_MAP_3, 0); + desc_index = ehw->txcmpl_ring_start; + + /* + * 6 registers to hold the completion mapping for total 32 + * TX desc rings (0-5, 6-11, 12-17, 18-23, 24-29 & rest). + * In each entry 5 bits hold the mapping for a particular TX desc ring. + */ + for (i = ehw->txdesc_ring_start; + i < ehw->txdesc_ring_end; i++) { + if ((i >= 0) && (i <= 5)) + reg = IPQ5332_EDMA_REG_TXDESC2CMPL_MAP_0; + else if ((i >= 6) && (i <= 11)) + reg = IPQ5332_EDMA_REG_TXDESC2CMPL_MAP_1; + else if ((i >= 12) && (i <= 17)) + reg = IPQ5332_EDMA_REG_TXDESC2CMPL_MAP_2; + else + reg = IPQ5332_EDMA_REG_TXDESC2CMPL_MAP_3; + + pr_debug("Configure TXDESC:%u to use TXCMPL:%u\n", + i, desc_index); + + /* + * Set the Tx complete descriptor ring number in the mapping + * register. + * E.g. If (txcmpl ring)desc_index = 31, (txdesc ring)i = 28. + * reg = IPQ5332_EDMA_REG_TXDESC2CMPL_MAP_4 + * data |= (desc_index & 0x1F) << ((i % 6) * 5); + * data |= (0x1F << 20); - This sets 11111 at 20th bit of + * register IPQ5332_EDMA_REG_TXDESC2CMPL_MAP_4 + */ + + data = ipq5332_edma_reg_read(reg); + data |= (desc_index & 0x1F) << ((i % 6) * 5); + ipq5332_edma_reg_write(reg, data); + + desc_index++; + if (desc_index == ehw->txcmpl_ring_end) + desc_index = ehw->txcmpl_ring_start; + } + + pr_debug("EDMA_REG_TXDESC2CMPL_MAP_0: 0x%x\n", + ipq5332_edma_reg_read(IPQ5332_EDMA_REG_TXDESC2CMPL_MAP_0)); + pr_debug("EDMA_REG_TXDESC2CMPL_MAP_1: 0x%x\n", + ipq5332_edma_reg_read(IPQ5332_EDMA_REG_TXDESC2CMPL_MAP_1)); + pr_debug("EDMA_REG_TXDESC2CMPL_MAP_2: 0x%x\n", + ipq5332_edma_reg_read(IPQ5332_EDMA_REG_TXDESC2CMPL_MAP_2)); + pr_debug("EDMA_REG_TXDESC2CMPL_MAP_3: 0x%x\n", + ipq5332_edma_reg_read(IPQ5332_EDMA_REG_TXDESC2CMPL_MAP_3)); + + /* + * Set PPE QID to EDMA Rx ring mapping. + * Each entry can hold mapping for 4 PPE queues and entry size is + * 4 bytes + */ + desc_index = (ehw->rxdesc_ring_start & 0x1f); + + reg = IPQ5332_EDMA_QID2RID_TABLE_MEM(0); + data = ((desc_index << 0) & 0xff) | + (((desc_index + 1) << 8) & 0xff00) | + (((desc_index + 2) << 16) & 0xff0000) | + (((desc_index + 3) << 24) & 0xff000000); + + ipq5332_edma_reg_write(reg, data); + pr_debug("Configure QID2RID(0) reg:0x%x to 0x%x\n", reg, data); + + /* + * Map PPE multicast queues to the first Rx ring. + */ + desc_index = (ehw->rxdesc_ring_start & 0x1f); + + for (i = IPQ5332_EDMA_CPU_PORT_MC_QID_MIN; + i <= IPQ5332_EDMA_CPU_PORT_MC_QID_MAX; + i += IPQ5332_EDMA_QID2RID_NUM_PER_REG) { + reg_idx = i/IPQ5332_EDMA_QID2RID_NUM_PER_REG; + + reg = IPQ5332_EDMA_QID2RID_TABLE_MEM(reg_idx); + data = ((desc_index << 0) & 0xff) | + ((desc_index << 8) & 0xff00) | + ((desc_index << 16) & 0xff0000) | + ((desc_index << 24) & 0xff000000); + + ipq5332_edma_reg_write(reg, data); + pr_debug("Configure QID2RID(%d) reg:0x%x to 0x%x\n", + reg_idx, reg, data); + } + + /* + * Set RXDESC2FILL_MAP_xx reg. + * There are 3 registers RXDESC2FILL_0, RXDESC2FILL_1 and RXDESC2FILL_2 + * 3 bits holds the rx fill ring mapping for each of the + * rx descriptor ring. + */ + ipq5332_edma_reg_write(IPQ5332_EDMA_REG_RXDESC2FILL_MAP_0, 0); + ipq5332_edma_reg_write(IPQ5332_EDMA_REG_RXDESC2FILL_MAP_1, 0); + + for (i = 0; i < ehw->rxdesc_rings; i++) { + rxdesc_ring = &ehw->rxdesc_ring[i]; + + ring_id = rxdesc_ring->id; + if ((ring_id >= 0) && (ring_id <= 9)) + reg = IPQ5332_EDMA_REG_RXDESC2FILL_MAP_0; + else + reg = IPQ5332_EDMA_REG_RXDESC2FILL_MAP_1; + + + pr_debug("Configure RXDESC:%u to use RXFILL:%u\n", + ring_id, rxdesc_ring->rxfill->id); + + /* + * Set the Rx fill descriptor ring number in the mapping + * register. + */ + data = ipq5332_edma_reg_read(reg); + data |= (rxdesc_ring->rxfill->id & 0x7) << ((ring_id % 10) * 3); + ipq5332_edma_reg_write(reg, data); + } + + pr_debug("EDMA_REG_RXDESC2FILL_MAP_0: 0x%x\n", + ipq5332_edma_reg_read(IPQ5332_EDMA_REG_RXDESC2FILL_MAP_0)); + pr_debug("EDMA_REG_RXDESC2FILL_MAP_1: 0x%x\n", + ipq5332_edma_reg_read(IPQ5332_EDMA_REG_RXDESC2FILL_MAP_1)); + + /* + * Configure DMA request priority, DMA read burst length, + * and AXI write size. + */ + data = IPQ5332_EDMA_DMAR_BURST_LEN_SET(IPQ5332_EDMA_BURST_LEN_ENABLE) + | IPQ5332_EDMA_DMAR_REQ_PRI_SET(0) + | IPQ5332_EDMA_DMAR_TXDATA_OUTSTANDING_NUM_SET(31) + | IPQ5332_EDMA_DMAR_TXDESC_OUTSTANDING_NUM_SET(7) + | IPQ5332_EDMA_DMAR_RXFILL_OUTSTANDING_NUM_SET(7); + ipq5332_edma_reg_write(IPQ5332_EDMA_REG_DMAR_CTRL, data); + + /* + * Global EDMA and padding enable + */ + ipq5332_edma_reg_write(IPQ5332_EDMA_REG_PORT_CTRL, + IPQ5332_EDMA_PORT_CTRL_EN); + + /* + * Enable Rx rings + */ + for (i = ehw->rxdesc_ring_start; i < ehw->rxdesc_ring_end; i++) { + data = ipq5332_edma_reg_read(IPQ5332_EDMA_REG_RXDESC_CTRL(i)); + data |= IPQ5332_EDMA_RXDESC_RX_EN; + ipq5332_edma_reg_write(IPQ5332_EDMA_REG_RXDESC_CTRL(i), data); + } + + for (i = ehw->rxfill_ring_start; i < ehw->rxfill_ring_end; i++) { + data = ipq5332_edma_reg_read(IPQ5332_EDMA_REG_RXFILL_RING_EN(i)); + data |= IPQ5332_EDMA_RXFILL_RING_EN; + ipq5332_edma_reg_write(IPQ5332_EDMA_REG_RXFILL_RING_EN(i), data); + } + + /* + * Enable Tx rings + */ + for (i = ehw->txdesc_ring_start; i < ehw->txdesc_ring_end; i++) { + data = ipq5332_edma_reg_read(IPQ5332_EDMA_REG_TXDESC_CTRL(i)); + data |= IPQ5332_EDMA_TXDESC_TX_EN; + ipq5332_edma_reg_write(IPQ5332_EDMA_REG_TXDESC_CTRL(i), data); + } + + /* + * Enable MISC interrupt mask + */ + ipq5332_edma_reg_write(IPQ5332_EDMA_REG_MISC_INT_MASK, + ehw->misc_intr_mask); + + pr_info("%s: successfull\n", __func__); + return 0; +} + +void ipq5332_prepare_phy_info(int offset, phy_info_t * phy_info) +{ + phy_info->phy_address = fdtdec_get_uint(gd->fdt_blob, + offset, "phy_address", 0); + phy_info->phy_type = fdtdec_get_uint(gd->fdt_blob, + offset, "phy_type", 0); + phy_info->forced_speed = fdtdec_get_uint(gd->fdt_blob, + offset, "forced-speed", 0); + phy_info->forced_duplex = fdtdec_get_uint(gd->fdt_blob, + offset, "forced-duplex", 0); +} + +void ipq5332_prepare_port_info(int offset, int max_phy_ports) +{ + int i; + + for (i = 0, offset = fdt_first_subnode(gd->fdt_blob, offset); + offset > 0 && i < max_phy_ports; ++i, + offset = fdt_next_subnode(gd->fdt_blob, offset)) { + port_info[i] = ipq5332_alloc_mem( + sizeof(ipq5332_edma_port_info_t)); + port_info[i]->phy_info = ipq5332_alloc_mem(sizeof(phy_info_t)); + ipq5332_prepare_phy_info(offset, port_info[i]->phy_info); + port_info[i]->port_id = i; + port_info[i]->uniphy_id = fdtdec_get_uint(gd->fdt_blob, + offset, "uniphy_id", 0); + port_info[i]->mode = fdtdec_get_uint(gd->fdt_blob, + offset, "uniphy_mode", 0); + } +} + +void ipq5332_prepare_switch_info(int offset, phy_info_t * phy_info[], + int max_phy_ports) +{ + int i; + + for (i = 0, offset = fdt_first_subnode(gd->fdt_blob, offset); + offset > 0 && i < max_phy_ports; ++i, + offset = fdt_next_subnode(gd->fdt_blob, offset)) { + phy_info[i] = ipq5332_alloc_mem(sizeof(phy_info_t)); + ipq5332_prepare_phy_info(offset, phy_info[i]); + } +} + +void get_mdio_info(int offset, mdio_info_t * mdio_info[], int max_phy_ports) +{ + int mode; + int bus_no; + int i; + + for (i = 0; i < max_phy_ports; i++) + mdio_info[i] = ipq5332_alloc_mem(sizeof(mdio_info_t)); + i = 0; + for (offset = fdt_first_subnode(gd->fdt_blob, offset); offset > 0; + offset = fdt_next_subnode(gd->fdt_blob, offset)) { + mode = fdtdec_get_uint(gd->fdt_blob, + offset, "mdio_mode", 0); + bus_no = fdtdec_get_uint(gd->fdt_blob, + offset, "bus_no", 0); + mdio_info[i]->mode = mode; + mdio_info[i]->bus_no = bus_no; + ++i; + } +} + +#ifdef CONFIG_ATHRS17C_SWITCH +void ipq5332_prepare_qca8337_info(int phy_node, int max_phy_ports) +{ + int i, s17c_rst_gpio; + + for (i = 0, phy_node = fdt_first_subnode(gd->fdt_blob, phy_node); + phy_node > 0 && i < max_phy_ports; ++i, + phy_node = fdt_next_subnode(gd->fdt_blob, phy_node)) { + + s17c_swt_cfg[i].chip_detect = 0; + + s17c_rst_gpio = fdtdec_get_uint(gd->fdt_blob, phy_node, + "qca8337_rst_gpio", 0); + + ipq_s17c_switch_reset(s17c_rst_gpio); + + s17c_swt_cfg[i].update = fdtdec_get_uint(gd->fdt_blob, + phy_node, "update", 0); + s17c_swt_cfg[i].skip_vlan = fdtdec_get_uint(gd->fdt_blob, + phy_node, "skip_vlan", 0); + s17c_swt_cfg[i].pad0_mode = fdtdec_get_uint(gd->fdt_blob, + phy_node, "pad0_mode", 0); + s17c_swt_cfg[i].pad5_mode = fdtdec_get_uint(gd->fdt_blob, + phy_node, "pad5_mode", 0); + s17c_swt_cfg[i].pad6_mode = fdtdec_get_uint(gd->fdt_blob, + phy_node, "pad6_mode", 0); + s17c_swt_cfg[i].port0 = fdtdec_get_uint(gd->fdt_blob, + phy_node, "port0", 0); + s17c_swt_cfg[i].sgmii_ctrl = fdtdec_get_uint(gd->fdt_blob, + phy_node, "sgmii_ctrl", 0); + s17c_swt_cfg[i].port0_status = fdtdec_get_uint(gd->fdt_blob, + phy_node, "port0_status", 0); + s17c_swt_cfg[i].port6_status = fdtdec_get_uint(gd->fdt_blob, + phy_node, "port6_status", 0); + s17c_swt_cfg[i].port_count = fdtdec_get_uint(gd->fdt_blob, + phy_node, "port_count", 0); + s17c_swt_cfg[i].mac_pwr = fdtdec_get_uint(gd->fdt_blob, + phy_node, "mac_pwr", 0); + fdtdec_get_int_array(gd->fdt_blob, phy_node, + "port_phy_address", + s17c_swt_cfg[i].port_phy_address, + s17c_swt_cfg[i].port_count); + } +} +#endif + +#ifdef CONFIG_TP_EXT_SWITCH +#ifdef CONFIG_DAL_RTL8367C +static rtk_api_ret_t rtk_phyPatch_set(rtk_uint32 opt) +{ +#define RTL8367C_PHY_CONTROL 0 + + rtk_api_ret_t retVal = -1; + rtk_uint32 port = 0; + rtk_uint32 data = 0; + + if (opt != 0 && opt != 1) + return RT_ERR_FAILED; + + for (port = 0; port <= 4; port++) { + if ((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xA42C, &data)) != RT_ERR_OK) + return retVal; + + data |= 0x0010; + if ((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xA42C, data)) != RT_ERR_OK) + return retVal; + + /*According to rtk AE, these ops have been included in 1.4.2 dirver + if (opt == 0) { + if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xBC02, 0x00D0)) != RT_ERR_OK) + return retVal; + } + else { + if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xBC02, 0x00F0)) != RT_ERR_OK) + return retVal; + } + */ + + if ((retVal = rtl8367c_getAsicPHYReg(port, RTL8367C_PHY_CONTROL, &data)) != RT_ERR_OK) + return retVal; + + data |= (0x0001 << 9); + if ((retVal = rtl8367c_setAsicPHYReg(port, RTL8367C_PHY_CONTROL, data)) != RT_ERR_OK) + return retVal; + } + + return RT_ERR_OK; +} +#endif +#ifdef CONFIG_TP_EXT_SWITCH_RTL8367_ALL +static void reset_rtl8367s_switch_gpio(int gpio) +{ + unsigned int *switch_gpio_base = + (unsigned int *)GPIO_CONFIG_ADDR(gpio); +/* + * Set ref clock 25MHZ and enable Force mode + */ + writel(0x203, switch_gpio_base); + writel(0x0, GPIO_IN_OUT_ADDR(gpio)); + mdelay(500); + writel(0x2, GPIO_IN_OUT_ADDR(gpio)); + mdelay(500); +} + +static void rtl8367_sw_init(void) +{ + int ret = 100; + + reset_rtl8367s_switch_gpio(CONFIG_SWITCH_RESET); + + ret = rtk_switch_init(); + printf("rtk_switch_init ret = %d!!!!!!!!!!!!\n", ret); + mdelay(500); + + /*if (g_switch_chip == CHIP_RTL8367C) + { + rtk_phyPatch_set(0); + printf("phyPatch set Done.\n"); + }*/ + + ret = rtk_vlan_init(); + printf("rtk_vlan_init ret = %d!!!!!!!!!!!!\n", ret); + mdelay(500); + + printf("Set RTL8367S SGMII 2.5Gbps\n"); + rtk_port_mac_ability_t mac_cfg ; + rtk_mode_ext_t mode ; + + mode = MODE_EXT_HSGMII; + mac_cfg.forcemode = PORT_MAC_FORCE; + mac_cfg.speed = PORT_SPEED_2500M; + mac_cfg.duplex = PORT_FULL_DUPLEX; + mac_cfg.link = PORT_LINKUP; + mac_cfg.nway = DISABLED; + mac_cfg.txpause = DISABLED; + mac_cfg.rxpause = DISABLED; + + ret = rtk_port_macForceLinkExt_set(EXT_PORT0, mode,&mac_cfg); + printf("rtk_port_macForceLinkExt_set port [%d] ret = %d!!!!!!!!!!!!\n", EXT_PORT0, ret); + + ret = rtk_port_sgmiiNway_set(EXT_PORT0, DISABLED); + printf("rtk_port_sgmiiNway_set port [%d] ret = %d!!!!!!!!!!!!\n", EXT_PORT0, ret); + + ret = rtk_port_macForceLinkExt_set(EXT_PORT1, mode,&mac_cfg); + printf("rtk_port_macForceLinkExt_set port [%d] ret = %d!!!!!!!!!!!!\n", EXT_PORT1, ret); + + ret = rtk_port_sgmiiNway_set(EXT_PORT1, DISABLED); + printf("rtk_port_sgmiiNway_set port [%d] ret = %d!!!!!!!!!!!!\n", EXT_PORT1, ret); +} +#endif + +#ifdef CONFIG_TP_EXT_SWITCH_RTL8372 +static void reset_rtl8372_switch_gpio(int gpio_num) +{ + gpio_direction_output(gpio_num, 1); + mdelay(500); + gpio_set_value(gpio_num, 0); + mdelay(200); + gpio_set_value(gpio_num, 1); + mdelay(200); + return; +} + +static void rtl8372_sw_init(void) +{ + int ret = 0; + rtk_port_ability_t ability; + + reset_rtl8372_switch_gpio(CONFIG_SWITCH_RESET); + + if ((ret = rtk_switch_init()) != RT_ERR_OK) { + printf("!!!rtk_switch_init failed...ret=%d\n", ret); + } + + if ((ret = rtk_sdsMode_set(SERDES_ID0, SERDES_10GR) != RT_ERR_OK)) { + printf("!!!sdsMode set failed...ret=%d\n", ret); + } + + if ((ret = dal_rtl8373_port_sdsNway_set(SERDES_ID0, SERDES_10GR, 0)) != RT_ERR_OK) + { + printf("!!!sdsNway set failed...ret=%d\n", ret); + } + +#ifdef GE550V2_RTL8372_RTL8251B + if (RT_ERR_OK != dal_rtl8373_port_extphyid_set(SERDES_ID1, 0x2)) + { + printf("!!!dal_rtl8373_port_extphyid_set set failed...ret=%d\n", ret); + } + + if ((ret = rtk_sdsMode_set(SERDES_ID1, SERDES_10GUSXG)) != RT_ERR_OK) { + printf("!!!sdsMode set 1 failed...ret=%d\n", ret); + } + + if (dal_rtl8373_port_sdsNway_set(SERDES_ID1, SERDES_10GUSXG, 0) != RT_ERR_OK) + { + printf("!!!sdsNway set failed...ret=%d\n", ret); + } +#endif + /* + if(RT_ERR_OK != dal_rtl8373_portFrcAbility_get(UTP_PORT3, &ability)) + { + printf("dal_rtl8373_portFrcAbility_get error!!\n"); + } + + ability.forcemode = ENABLED; + ability.link = PORT_LINKUP; + ability.duplex = PORT_FULL_DUPLEX; + ability.speed = PORT_SPEED_10G; + ability.txpause = ENABLED; + ability.rxpause = ENABLED; + + if(RT_ERR_OK != dal_rtl8373_portFrcAbility_set(UTP_PORT3, &ability)) + { + printf("dal_rtl8373_portFrcAbility_set error!!\n"); + } + */ + printf("rtl8372 init OK!!!!\n"); +} +#endif + +#endif + +int ipq5332_edma_init(void *edma_board_cfg) +{ + struct eth_device *dev[IPQ5332_EDMA_DEV]; + struct ipq5332_edma_common_info *c_info[IPQ5332_EDMA_DEV]; + struct ipq5332_edma_hw *hw[IPQ5332_EDMA_DEV]; + uchar enet_addr[IPQ5332_EDMA_DEV * 6]; + int i; + int ret = -1; + ipq5332_edma_board_cfg_t ledma_cfg, *edma_cfg; + phy_info_t *phy_info; + int phy_id; + uint32_t phy_chip_id = 0, phy_chip_id1, phy_chip_id2; + int clk[4] = {0}; + int qca8084_swt_enb = 0; + int qca8084_chip_detect = 0; + +#ifdef CONFIG_IPQ5332_QCA8075_PHY + static int sw_init_done = 0; +#endif +#ifdef CONFIG_ATHRS17C_SWITCH + int s17c_swt_enb = 0; +#endif +#ifdef CONFIG_TP_EXT_SWITCH +#ifdef CONFIG_TP_EXT_SWITCH_RTL8367_ALL + int rtl8367_switch_enable = 0; +#endif +#ifdef CONFIG_TP_EXT_SWITCH_RTL8372 + int rtl8372_switch_enable = 0; +#endif +#endif +#ifdef CONFIG_TP_EXT_PHY_RTL8221B + int rtl8221_enable = 0; +#endif + int node, phy_addr, mode, phy_node = -1; + /* + * Init non cache buffer + */ + noncached_init(); + + node = fdt_path_offset(gd->fdt_blob, "/ess-switch"); +#ifdef CONFIG_QCA8084_SWT_MODE +#ifdef CONFIG_QCA8084_BYPASS_MODE + qca8084_bypass_enb = fdtdec_get_uint(gd->fdt_blob, node, + "qca8084_bypass_enable", 0); +#endif /* CONFIG_QCA8084_BYPASS_MODE */ + qca8084_swt_enb = fdtdec_get_uint(gd->fdt_blob, node, + "qca8084_switch_enable", 0); + + phy_node = fdt_path_offset(gd->fdt_blob, + "/ess-switch/qca8084_swt_info"); + if (phy_node >= 0) + ipq5332_prepare_switch_info(phy_node, swt_info, + QCA8084_MAX_PORTS); +#endif + +#ifdef CONFIG_ATHRS17C_SWITCH + s17c_swt_enb = fdtdec_get_uint(gd->fdt_blob, node, + "qca8337_switch_enable", 0); + if (s17c_swt_enb) { + phy_node = fdt_path_offset(gd->fdt_blob, + "/ess-switch/qca8337_swt_info"); + + ipq5332_prepare_qca8337_info(phy_node, IPQ5332_PHY_MAX); + } +#endif +#ifdef CONFIG_TP_EXT_SWITCH +#ifdef CONFIG_TP_EXT_SWITCH_RTL8367_ALL + rtl8367_switch_enable = fdtdec_get_uint(gd->fdt_blob, node, "rtl8367_switch_enable", 0); + printf("rtl8367_switch_enable:%d\n", rtl8367_switch_enable); +#endif +#ifdef CONFIG_TP_EXT_SWITCH_RTL8372 + rtl8372_switch_enable = fdtdec_get_uint(gd->fdt_blob, node, "rtl8372_switch_enable", 0); + printf("rtl8372_switch_enable:%d\n", rtl8372_switch_enable); +#endif +#endif +#ifdef CONFIG_TP_EXT_PHY_RTL8221B + rtl8221_enable = fdtdec_get_uint(gd->fdt_blob, node, "rtl8221_enable", 0); + printf("rtl8221_enable:%d\n", rtl8221_enable); +#endif + phy_node = fdt_path_offset(gd->fdt_blob, "/ess-switch/port_phyinfo"); + if (phy_node >= 0) { + ipq5332_prepare_port_info(phy_node, IPQ5332_PHY_MAX); + get_mdio_info(phy_node, mdio_info, IPQ5332_PHY_MAX); + } + + mode = fdtdec_get_uint(gd->fdt_blob, node, "switch_mac_mode0", -1); + if (mode < 0) { + printf("Error:switch_mac_mode0 not specified in dts"); + return mode; + } + + memset(c_info, 0, (sizeof(c_info) * IPQ5332_EDMA_DEV)); + memset(enet_addr, 0, sizeof(enet_addr)); + memset(&ledma_cfg, 0, sizeof(ledma_cfg)); + edma_cfg = &ledma_cfg; + strlcpy(edma_cfg->phy_name, "IPQ MDIO0", sizeof(edma_cfg->phy_name)); + + /* Getting the MAC address from ART partition */ + ret = get_eth_mac_address(enet_addr, IPQ5332_EDMA_DEV); + + /* + * Register EDMA as single ethernet + * interface. + */ + for (i = 0; i < IPQ5332_EDMA_DEV; edma_cfg++, i++) { + dev[i] = ipq5332_alloc_mem(sizeof(struct eth_device)); + + if (!dev[i]) + goto init_failed; + + memset(dev[i], 0, sizeof(struct eth_device)); + + c_info[i] = ipq5332_alloc_mem( + sizeof(struct ipq5332_edma_common_info)); + + if (!c_info[i]) + goto init_failed; + + memset(c_info[i], 0, + sizeof(struct ipq5332_edma_common_info)); + + hw[i] = &c_info[i]->hw; + + c_info[i]->hw.hw_addr = (unsigned long __iomem *) + IPQ5332_EDMA_CFG_BASE; + + ipq5332_edma_dev[i] = ipq5332_alloc_mem( + sizeof(struct ipq5332_eth_dev)); + + if (!ipq5332_edma_dev[i]) + goto init_failed; + + memset (ipq5332_edma_dev[i], 0, + sizeof(struct ipq5332_eth_dev)); + + dev[i]->iobase = IPQ5332_EDMA_CFG_BASE; + dev[i]->init = ipq5332_eth_init; + dev[i]->halt = ipq5332_eth_halt; + dev[i]->recv = ipq5332_eth_recv; + dev[i]->send = ipq5332_eth_snd; + dev[i]->write_hwaddr = ipq5332_edma_wr_macaddr; + dev[i]->priv = (void *)ipq5332_edma_dev[i]; + + if ((ret < 0) || + (!is_valid_ethaddr(&enet_addr[edma_cfg->unit * 6]))) { + memcpy(&dev[i]->enetaddr[0], ipq5332_def_enetaddr, 6); + } else { + memcpy(&dev[i]->enetaddr[0], + &enet_addr[edma_cfg->unit * 6], 6); + } + + printf("MAC%x addr:%x:%x:%x:%x:%x:%x\n", + edma_cfg->unit, dev[i]->enetaddr[0], + dev[i]->enetaddr[1], + dev[i]->enetaddr[2], + dev[i]->enetaddr[3], + dev[i]->enetaddr[4], + dev[i]->enetaddr[5]); + + snprintf(dev[i]->name, sizeof(dev[i]->name), "eth%d", i); + + ipq5332_edma_dev[i]->dev = dev[i]; + ipq5332_edma_dev[i]->mac_unit = edma_cfg->unit; + ipq5332_edma_dev[i]->c_info = c_info[i]; +#ifdef CONFIG_TP_EXT_SWITCH +#ifdef CONFIG_TP_EXT_SWITCH_RTL8367_ALL + ipq5332_edma_dev[i]->rtl8367_switch_enable = rtl8367_switch_enable; + printf("ipq5332_edma_dev[%d]->rtl8367_switch_enable:%d\n", i, ipq5332_edma_dev[i]->rtl8367_switch_enable); +#endif +#ifdef CONFIG_TP_EXT_SWITCH_RTL8372 + ipq5332_edma_dev[i]->rtl8372_switch_enable = rtl8372_switch_enable; + printf("ipq5332_edma_dev[%d]->rtl8372_switch_enable:%d\n", i, ipq5332_edma_dev[i]->rtl8372_switch_enable); +#endif + +#endif +#ifdef CONFIG_TP_EXT_PHY_RTL8221B + ipq5332_edma_dev[i]->rtl8221_enable = rtl8221_enable; + printf("ipq5332_edma_dev[%d]->rtl8221_enable:%d\n", i, ipq5332_edma_dev[i]->rtl8221_enable); +#endif + ipq5332_edma_hw_addr = IPQ5332_EDMA_CFG_BASE; + + ret = ipq_sw_mdio_init(edma_cfg->phy_name); + if (ret) + goto init_failed; + + ret = ipq5332_edma_hw_init(hw[i]); + + if (ret) + goto init_failed; + + /* + * setup force mode clk for QCA8084 & QCA8337 + */ + clk[0] = 0x301; + clk[1] = 0x0; + clk[2] = 0x401; + clk[3] = 0x0; + +/* For GE550V2, because the RTL8251 MDIO bus is connected to the RTL8372, +RTL8372 need to be initialized before RTL8251, so the order is reversed. */ +#ifdef GE550V2_RTL8372_RTL8251B + for (phy_id = IPQ5332_PHY_MAX - 1 ; phy_id >= 0; phy_id--) { +#else + for (phy_id = 0; phy_id < IPQ5332_PHY_MAX; phy_id++) { +#endif + phy_info = port_info[phy_id]->phy_info; + phy_addr = phy_info->phy_address; + + ipq_set_mdio_mode(mdio_info[phy_id]->mode, + mdio_info[phy_id]->bus_no); + + if(phy_info->phy_type == UNUSED_PHY_TYPE) + continue; + +#ifdef CONFIG_QCA8084_SWT_MODE + if (phy_info->phy_type == QCA8084_PHY_TYPE && + phy_addr == PORT1) { + ipq_phy_addr_fixup(); + ipq_clock_init(); + } +#endif +#ifdef CONFIG_QCA8033_PHY + if (phy_info->phy_type == QCA8033_PHY_TYPE) { + ppe_uniphy_refclk_set_25M( + port_info[phy_id]->uniphy_id); + mdelay(10); + qca8033_phy_reset(); + mdelay(100); + } +#endif +#ifdef CONFIG_TP_EXT_PHY_RTL8221B + printf("phy_id:%d\n", phy_id); + if (0 == phy_id && rtl8221_enable){ + phy_info->phy_type = RTL8221B_PHY_TYPE; + phy_chip_id = RTL8221; + + ipq5332_port_mac_clock_reset(phy_id); + /* Force Link-speed: 2500M + * Force Link-status: enable + */ + ipq5332_xgmac_sgmiiplus_speed_set(phy_id, 0x4, 0); + + ipq5332_speed_clock_set(phy_id, clk); + rtl8221b_init(); + } +#endif +#ifdef CONFIG_TP_EXT_SWITCH +#ifdef CONFIG_TP_EXT_SWITCH_RTL8367_ALL + printf("phy_id:%d\n", phy_id); + if (1 == phy_id && rtl8367_switch_enable){ + phy_info->phy_type = RTL8367S_SWITCH_TYPE; + phy_chip_id = RTL8367; + + ipq5332_port_mac_clock_reset(phy_id); + /* Force Link-speed: 2500M + * Force Link-status: enable + */ + ipq5332_xgmac_sgmiiplus_speed_set(phy_id, 0x4, 0); + + ipq5332_speed_clock_set(phy_id, clk); + + rtl8367_sw_init(); + printf("..............probe rtk switch %d\n", g_switch_chip); + rtk_port_phyEnableAll_set(ENABLED); + } +#endif +#ifdef CONFIG_TP_EXT_SWITCH_RTL8372 + printf("phy_id:%d\n", phy_id); + if (1 == phy_id && rtl8372_switch_enable){ + phy_info->phy_type = RTL8372_SWITCH_TYPE; + phy_chip_id = RTL8372; + + ipq5332_port_mac_clock_reset(phy_id); + /* Force Link-speed: 10000M + * Force Link-status: enable + */ + ipq5332_10g_r_speed_set(phy_id, 0); + clk[1] = 0x0; + clk[3] = 0x0; + clk[0] = 0x301; + clk[2] = 0x401; + + ipq5332_speed_clock_set(phy_id, clk); + rtl8372_sw_init(); + } +#endif +#ifdef CONFIG_TP_EXT_PHY_RTL8251B + if (phy_info->phy_type == RTL8251B_PHY_TYPE) { + phy_chip_id1 = ipq_mdio_read(phy_addr, + QCA_PHY_ID1, NULL); + phy_chip_id2 = ipq_mdio_read(phy_addr, + QCA_PHY_ID2, NULL); + phy_chip_id = (phy_chip_id1 << 16) | + phy_chip_id2; + printf("phy_id is: 0x%x, phy_addr = 0x%x," + "phy_chip_id1 = 0x%x," + "phy_chip_id2 = 0x%x," + "phy_chip_id = 0x%x," + "RTL8251 = 0x%x \n", + phy_id, phy_addr, phy_chip_id1, + phy_chip_id2, phy_chip_id, RTL8251B_PHY); + } +#endif +#else + if (phy_info->phy_type == AQ_PHY_TYPE) { + phy_chip_id1 = ipq_mdio_read(phy_addr, + (1<<30) |(1<<16) | + QCA_PHY_ID1, NULL); + phy_chip_id2 = ipq_mdio_read(phy_addr, + (1<<30) |(1<<16) | + QCA_PHY_ID2, NULL); + phy_chip_id = (phy_chip_id1 << 16) | + phy_chip_id2; + } else { + phy_chip_id1 = ipq_mdio_read(phy_addr, + QCA_PHY_ID1, NULL); + phy_chip_id2 = ipq_mdio_read(phy_addr, + QCA_PHY_ID2, NULL); + phy_chip_id = (phy_chip_id1 << 16) | + phy_chip_id2; + } + pr_debug("phy_id is: 0x%x, phy_addr = 0x%x," + "phy_chip_id1 = 0x%x," + "phy_chip_id2 = 0x%x," + "phy_chip_id = 0x%x\n", + phy_id, phy_addr, phy_chip_id1, + phy_chip_id2, phy_chip_id); +#endif + switch(phy_chip_id) { +#ifdef CONFIG_IPQ5332_QCA8075_PHY + case QCA8075_PHY_V1_0_5P: + case QCA8075_PHY_V1_1_5P: + case QCA8075_PHY_V1_1_2P: + if (!sw_init_done) { + if (ipq5332_qca8075_phy_init( + &ipq5332_edma_dev[i]->ops[phy_id], + phy_addr) == 0) { + sw_init_done = 1; + } + } else { + ipq5332_qca8075_phy_map_ops( + &ipq5332_edma_dev[i]->ops[phy_id]); + } + if (mode == EPORT_WRAPPER_PSGMII) + ipq5332_qca8075_phy_interface_set_mode( + phy_addr, 0x0); + else if (mode == EPORT_WRAPPER_QSGMII) + ipq5332_qca8075_phy_interface_set_mode( + phy_addr, 0x4); + break; +#endif +#ifdef CONFIG_QCA8033_PHY + case QCA8033_PHY: + ipq_qca8033_phy_init( + &ipq5332_edma_dev[i]->ops[phy_id], + phy_addr); + break; +#endif +#ifdef CONFIG_QCA8081_PHY + case QCA8081_PHY: + case QCA8081_1_1_PHY: + ipq_qca8081_phy_init( + &ipq5332_edma_dev[i]->ops[phy_id], + phy_addr); + break; +#endif +#ifdef CONFIG_QCA8084_SWT_MODE + case QCA8084_PHY: +#ifdef CONFIG_QCA8084_BYPASS_MODE + if (qca8084_bypass_enb && + (phy_addr == PORT4)) { + ipq_qca8084_phy_hw_init( + &ipq5332_edma_dev[i]->ops[phy_id], + phy_addr); + + qca8084_bypass_interface_mode_set( + PHY_SGMII_BASET); + } else +#endif /* CONFIG_QCA8084_BYPASS_MODE */ + { + if (qca8084_swt_enb) + ++qca8084_chip_detect; + } + break; +#endif +#ifdef CONFIG_ATHRS17C_SWITCH + case QCA8337_PHY: + if (s17c_swt_enb) { + ppe_uniphy_set_forceMode( + port_info[phy_id]->uniphy_id); + ppe_uniphy_refclk_set_25M( + port_info[phy_id]->uniphy_id); + ++s17c_swt_cfg[phy_id].chip_detect; + ipq5332_port_mac_clock_reset(phy_id); + /*Force Link-speed: 1000M */ + ipq5332_pqsgmii_speed_set(phy_id, + 0x2, 0); + ipq5332_speed_clock_set(phy_id, clk); + ret = ipq_qca8337_switch_init( + &s17c_swt_cfg[phy_id]); + if (ret < 0) { + printf("qca8337 init failed" + "_%d\n", phy_id); + } + } + break; +#endif +#ifdef CONFIG_TP_EXT_SWITCH +#ifdef CONFIG_TP_EXT_SWITCH_RTL8367_ALL + case RTL8367: + break; +#endif +#ifdef CONFIG_TP_EXT_SWITCH_RTL8372 + case RTL8372: + break; +#endif +#endif +#ifdef CONFIG_TP_EXT_PHY_RTL8221B + case RTL8221: + break; +#endif +#ifdef CONFIG_IPQ_QCA_AQUANTIA_PHY + case AQUANTIA_PHY_107: + case AQUANTIA_PHY_109: + case AQUANTIA_PHY_111: + case AQUANTIA_PHY_111B0: + case AQUANTIA_PHY_112: + case AQUANTIA_PHY_112C: + case AQUANTIA_PHY_113C_A0: + case AQUANTIA_PHY_113C_A1: + case AQUANTIA_PHY_113C_B0: + case AQUANTIA_PHY_113C_B1: + ipq_board_fw_download(phy_addr); + mdelay(100); + ipq_qca_aquantia_phy_init( + &ipq5332_edma_dev[i]->ops[phy_id], + phy_addr); + break; +#endif +#ifdef CONFIG_TP_EXT_PHY_RTL8251B + case RTL8251B_PHY: + rtl8251b_init(&ipq5332_edma_dev[i]->ops[phy_id], phy_addr); + break; +#endif + default: + if (phy_info->phy_type != SFP_PHY_TYPE) + printf("Port%d Invalid Phy Id 0x%x" + "Type 0x%x add 0x%x\n", + phy_id, phy_chip_id, + phy_info->phy_type, + phy_info->phy_address); + break; + } + } + + for (phy_id = 0; phy_id < qca8084_chip_detect; ++phy_id) { + + ipq_set_mdio_mode(mdio_info[phy_id]->mode, + mdio_info[phy_id]->bus_no); + + ipq5332_port_mac_clock_reset(phy_id); + /* Force Link-speed: 2500M + * Force Link-status: enable + */ + ipq5332_xgmac_sgmiiplus_speed_set(phy_id, 0x4, 0); + + ipq5332_speed_clock_set(phy_id, clk); + + ret = ipq_qca8084_hw_init(swt_info); + if (ret < 0) { + printf("qca8084 switch mode hw" + "_init failed %d\n", + phy_id); + } + + } + + eth_register(dev[i]); + } + + return 0; + +init_failed: + printf("Error in allocating Mem\n"); + + for (i = 0; i < IPQ5332_EDMA_DEV; i++) { + if (dev[i]) { + eth_unregister(dev[i]); + ipq5332_free_mem(dev[i]); + } + if (c_info[i]) { + ipq5332_free_mem(c_info[i]); + } + if (ipq5332_edma_dev[i]) { + ipq5332_free_mem(ipq5332_edma_dev[i]); + } + } + + return -1; +} diff --git a/sources/uboot-be550/drivers/net/ipq5332/ipq5332_edma.h b/sources/uboot-be550/drivers/net/ipq5332/ipq5332_edma.h new file mode 100755 index 00000000..5dc5d2dd --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq5332/ipq5332_edma.h @@ -0,0 +1,353 @@ +/* + ************************************************************************** + * Copyright (c) 2016-2019, 2021, The Linux Foundation. All rights reserved. + * + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + ************************************************************************** +*/ +#ifndef __IPQ5332_EDMA__ +#define __IPQ5332_EDMA__ + +#define IPQ5332_NSS_DP_START_PHY_PORT 1 +#define IPQ5332_NSS_DP_MAX_PHY_PORTS 2 + +#define IPQ5332_EDMA_DEVICE_NODE_NAME "edma" + +/* Number of descriptors in each ring is defined with below macro */ +#define IPQ5332_EDMA_TX_RING_SIZE 128 +#define IPQ5332_EDMA_RX_RING_SIZE 128 + +/* Number of byte in a descriptor is defined with below macros for each of + * the rings respectively */ +#define IPQ5332_EDMA_TXDESC_DESC_SIZE (sizeof(struct ipq5332_edma_txdesc_desc)) +#define IPQ5332_EDMA_TXCMPL_DESC_SIZE (sizeof(struct ipq5332_edma_txcmpl_desc)) +#define IPQ5332_EDMA_RXDESC_DESC_SIZE (sizeof(struct ipq5332_edma_rxdesc_desc)) +#define IPQ5332_EDMA_RXFILL_DESC_SIZE (sizeof(struct ipq5332_edma_rxfill_desc)) +#define IPQ5332_EDMA_RX_SEC_DESC_SIZE (sizeof(struct ipq5332_edma_rx_sec_desc)) +#define IPQ5332_EDMA_TX_SEC_DESC_SIZE (sizeof(struct ipq5332_edma_tx_sec_desc)) + +#define IPQ5332_EDMA_START_GMACS IPQ5332_NSS_DP_START_PHY_PORT +#define IPQ5332_EDMA_MAX_GMACS IPQ5332_NSS_DP_MAX_PHY_PORTS + +#define IPQ5332_EDMA_TX_BUFF_SIZE 2048 +#define IPQ5332_EDMA_RX_BUFF_SIZE 2048 + +/* Max number of rings of each type is defined with below macro */ +#define IPQ5332_EDMA_MAX_TXCMPL_RINGS 24 /* Max TxCmpl rings */ +#define IPQ5332_EDMA_MAX_TXDESC_RINGS 24 /* Max TxDesc rings */ +#define IPQ5332_EDMA_MAX_RXDESC_RINGS 16 /* Max RxDesc rings */ +#define IPQ5332_EDMA_MAX_RXFILL_RINGS 8 /* Max RxFill rings */ + +#define IPQ5332_EDMA_GET_DESC(R, i, type) (&(((type *)((R)->desc))[i])) +#define IPQ5332_EDMA_RXFILL_DESC(R, i) IPQ5332_EDMA_GET_DESC(R, i, struct ipq5332_edma_rxfill_desc) +#define IPQ5332_EDMA_RXDESC_DESC(R, i) IPQ5332_EDMA_GET_DESC(R, i, struct ipq5332_edma_rxdesc_desc) +#define IPQ5332_EDMA_TXDESC_DESC(R, i) IPQ5332_EDMA_GET_DESC(R, i, struct ipq5332_edma_txdesc_desc) +#define IPQ5332_EDMA_TXCMPL_DESC(R, i) IPQ5332_EDMA_GET_DESC(R, i, struct ipq5332_edma_txcmpl_desc) + +#define IPQ5332_EDMA_DEV 1 + +/* Only 1 ring of each type will be used in U-Boot which is defined with + * below macros */ +#define IPQ5332_EDMA_TX_DESC_RING_START 23 +#define IPQ5332_EDMA_TX_DESC_RING_NOS 1 +#define IPQ5332_EDMA_TX_DESC_RING_SIZE \ +(IPQ5332_EDMA_TX_DESC_RING_START + IPQ5332_EDMA_TX_DESC_RING_NOS) + +#define IPQ5332_EDMA_TX_CMPL_RING_START 23 +#define IPQ5332_EDMA_TX_CMPL_RING_NOS 1 +#define IPQ5332_EDMA_TX_CMPL_RING_SIZE \ +(IPQ5332_EDMA_TX_CMPL_RING_START + IPQ5332_EDMA_TX_CMPL_RING_NOS) + +#define IPQ5332_EDMA_RX_DESC_RING_START 15 +#define IPQ5332_EDMA_RX_DESC_RING_NOS 1 +#define IPQ5332_EDMA_RX_DESC_RING_SIZE \ +(IPQ5332_EDMA_RX_DESC_RING_START + IPQ5332_EDMA_RX_DESC_RING_NOS) + +#define IPQ5332_EDMA_RX_FILL_RING_START 7 +#define IPQ5332_EDMA_RX_FILL_RING_NOS 1 +#define IPQ5332_EDMA_RX_FILL_RING_SIZE \ +(IPQ5332_EDMA_RX_FILL_RING_START + IPQ5332_EDMA_RX_FILL_RING_NOS) + +#define NETDEV_TX_BUSY 1 + +/* + * RxDesc descriptor + */ +struct ipq5332_edma_rxdesc_desc { + uint32_t rdes0; /* Contains buffer address */ + uint32_t rdes1; /* Contains more bit, priority bit, service code */ + uint32_t rdes2; /* Contains opaque */ + uint32_t rdes3; /* Contains opaque high bits */ + uint32_t rdes4; /* Contains destination and source information */ + uint32_t rdes5; /* Contains WiFi QoS, data length */ + uint32_t rdes6; /* Contains hash value, check sum status */ + uint32_t rdes7; /* Contains DSCP, packet offsets */ +}; + +/* + * EDMA Rx Secondary Descriptor + */ +struct ipq5332_edma_rx_sec_desc { + uint32_t rx_sec0; /* Contains timestamp */ + uint32_t rx_sec1; /* Contains secondary checksum status */ + uint32_t rx_sec2; /* Contains QoS tag */ + uint32_t rx_sec3; /* Contains flow index details */ + uint32_t rx_sec4; /* Contains secondary packet offsets */ + uint32_t rx_sec5; /* Contains multicast bit, checksum */ + uint32_t rx_sec6; /* Contains SVLAN, CVLAN */ + uint32_t rx_sec7; /* Contains secondary SVLAN, CVLAN */ +}; + +/* + * RxFill descriptor + */ +struct ipq5332_edma_rxfill_desc { + uint32_t rdes0; /* Contains buffer address */ + uint32_t rdes1; /* Contains buffer size */ + uint32_t rdes2; /* Contains opaque */ + uint32_t rdes3; /* Contains opaque high bits */ +}; + +/* + * TxDesc descriptor + */ +struct ipq5332_edma_txdesc_desc { + uint32_t tdes0; /* Low 32-bit of buffer address */ + uint32_t tdes1; /* Buffer recycling, PTP tag flag, PRI valid flag */ + uint32_t tdes2; /* Low 32-bit of opaque value */ + uint32_t tdes3; /* High 32-bit of opaque value */ + uint32_t tdes4; /* Source/Destination port info */ + uint32_t tdes5; /* VLAN offload, csum_mode, ip_csum_en, tso_en, data length */ + uint32_t tdes6; /* MSS/hash_value/PTP tag, data offset */ + uint32_t tdes7; /* L4/L3 offset, PROT type, L2 type, CVLAN/SVLAN tag, service code */ +}; + +/* + * EDMA Tx Secondary Descriptor + */ +struct ipq5332_edma_tx_sec_desc { + uint32_t tx_sec0; /* Reserved */ + uint32_t tx_sec1; /* Custom csum offset, payload offset, TTL/NAT action */ + uint32_t rx_sec2; /* NAPT translated port, DSCP value, TTL value */ + uint32_t rx_sec3; /* Flow index value and valid flag */ + uint32_t rx_sec4; /* Reserved */ + uint32_t rx_sec5; /* Reserved */ + uint32_t rx_sec6; /* CVLAN/SVLAN command */ + uint32_t rx_sec7; /* CVLAN/SVLAN tag value */ +}; + +/* + * TxCmpl descriptor + */ +struct ipq5332_edma_txcmpl_desc { + uint32_t tdes0; /* Low 32-bit opaque value */ + uint32_t tdes1; /* High 32-bit opaque value */ + uint32_t tdes2; /* More fragment, transmit ring id, pool id */ + uint32_t tdes3; /* Error indications */ +}; + +/* + * Tx descriptor ring + */ +struct ipq5332_edma_txdesc_ring { + uint32_t prod_idx; /* Producer index */ + uint32_t avail_desc; /* Number of available descriptor to process */ + uint32_t id; /* TXDESC ring number */ + struct ipq5332_edma_txdesc_desc *desc; /* descriptor ring virtual address */ + dma_addr_t dma; /* descriptor ring physical address */ + struct ipq5332_edma_tx_sec_desc *sdesc; /* Secondary descriptor ring virtual addr */ + dma_addr_t sdma; /* Secondary descriptor ring physical address */ + uint16_t count; /* number of descriptors */ +}; + +/* + * TxCmpl ring + */ +struct ipq5332_edma_txcmpl_ring { + uint32_t cons_idx; /* Consumer index */ + uint32_t avail_pkt; /* Number of available packets to process */ + struct ipq5332_edma_txcmpl_desc *desc; /* descriptor ring virtual address */ + uint32_t id; /* TXCMPL ring number */ + dma_addr_t dma; /* descriptor ring physical address */ + uint32_t count; /* Number of descriptors in the ring */ +}; + +/* + * RxFill ring + */ +struct ipq5332_edma_rxfill_ring { + uint32_t id; /* RXFILL ring number */ + uint32_t count; /* number of descriptors in the ring */ + uint32_t prod_idx; /* Ring producer index */ + struct ipq5332_edma_rxfill_desc *desc; /* descriptor ring virtual address */ + dma_addr_t dma; /* descriptor ring physical address */ +}; + +/* + * RxDesc ring + */ +struct ipq5332_edma_rxdesc_ring { + uint32_t id; /* RXDESC ring number */ + uint32_t count; /* number of descriptors in the ring */ + uint32_t cons_idx; /* Ring consumer index */ + struct ipq5332_edma_rxdesc_desc *desc; /* Primary descriptor ring virtual addr */ + struct ipq5332_edma_sec_rxdesc_ring *sdesc; /* Secondary desc ring VA */ + struct ipq5332_edma_rxfill_ring *rxfill; /* RXFILL ring used */ + dma_addr_t dma; /* Primary descriptor ring physical address */ + dma_addr_t sdma; /* Secondary descriptor ring physical address */ +}; + +enum ipq5332_edma_tx { + EDMA_TX_OK = 0, /* Tx success */ + EDMA_TX_DESC = 1, /* Not enough descriptors */ + EDMA_TX_FAIL = 2, /* Tx failure */ +}; + + +/* per core queue related information */ +struct queue_per_cpu_info { + u32 tx_mask; /* tx interrupt mask */ + u32 rx_mask; /* rx interrupt mask */ + u32 tx_status; /* tx interrupt status */ + u32 rx_status; /* rx interrupt status */ + u32 tx_start; /* tx queue start */ + u32 rx_start; /* rx queue start */ + struct ipq5332_edma_common_info *c_info; /* edma common info */ +}; + +/* edma hw specific data */ +struct ipq5332_edma_hw { + unsigned long __iomem *hw_addr; /* inner register address */ + u8 intr_clear_type; /* interrupt clear */ + u8 intr_sw_idx_w; /* To do chk type interrupt software index */ + u16 rx_buff_size; /* To do chk type Rx buffer size */ + u8 rss_type; /* rss protocol type */ + uint16_t rx_payload_offset; /* start of the payload offset */ + uint32_t flags; /* internal flags */ + int active; /* status */ + struct ipq5332_edma_txdesc_ring *txdesc_ring; /* Tx Descriptor Ring, SW is producer */ + struct ipq5332_edma_txcmpl_ring *txcmpl_ring; /* Tx Completion Ring, SW is consumer */ + struct ipq5332_edma_rxdesc_ring *rxdesc_ring; /* Rx Descriptor Ring, SW is consumer */ + struct ipq5332_edma_rxfill_ring *rxfill_ring; /* Rx Fill Ring, SW is producer */ + uint32_t txdesc_rings; /* Number of TxDesc rings */ + uint32_t txdesc_ring_start; /* Id of first TXDESC ring */ + uint32_t txdesc_ring_end; /* Id of the last TXDESC ring */ + uint32_t txcmpl_rings; /* Number of TxCmpl rings */ + uint32_t txcmpl_ring_start; /* Id of first TXCMPL ring */ + uint32_t txcmpl_ring_end; /* Id of last TXCMPL ring */ + uint32_t rxfill_rings; /* Number of RxFill rings */ + uint32_t rxfill_ring_start; /* Id of first RxFill ring */ + uint32_t rxfill_ring_end; /* Id of last RxFill ring */ + uint32_t rxdesc_rings; /* Number of RxDesc rings */ + uint32_t rxdesc_ring_start; /* Id of first RxDesc ring */ + uint32_t rxdesc_ring_end; /* Id of last RxDesc ring */ + uint32_t tx_intr_mask; /* tx interrupt mask */ + uint32_t rx_intr_mask; /* rx interrupt mask */ + uint32_t rxfill_intr_mask; /* Rx fill ring interrupt mask */ + uint32_t rxdesc_intr_mask; /* Rx Desc ring interrupt mask */ + uint32_t txcmpl_intr_mask; /* Tx Cmpl ring interrupt mask */ + uint32_t misc_intr_mask; /* misc interrupt interrupt mask */ +}; + +struct ipq5332_edma_common_info { + struct ipq5332_edma_hw hw; +}; + +#define MAX_PHY 6 +struct ipq5332_eth_dev { + u8 *phy_address; + uint no_of_phys; + uint interface; + uint speed; + uint duplex; + uint sw_configured; + uint mac_unit; + uint mac_ps; +#ifdef CONFIG_TP_EXT_SWITCH +#ifdef CONFIG_TP_EXT_SWITCH_RTL8367_ALL + uint rtl8367_switch_enable; +#endif +#ifdef CONFIG_TP_EXT_SWITCH_RTL8372 + uint rtl8372_switch_enable; +#endif + +#endif +#ifdef CONFIG_TP_EXT_PHY_RTL8221B + uint rtl8221_enable; +#endif + int link_printed; + u32 padding; + struct eth_device *dev; + struct ipq5332_edma_common_info *c_info; + struct phy_ops *ops[MAX_PHY]; + const char phy_name[MDIO_NAME_LEN]; +} __attribute__ ((aligned(8))); + +static inline void* ipq5332_alloc_mem(u32 size) +{ + void *p = malloc(size); + if (p != NULL) + memset(p, 0, size); + return p; +} + +static inline void* ipq5332_alloc_memalign(u32 size) +{ + void *p = memalign(CONFIG_SYS_CACHELINE_SIZE, size); + if (p != NULL) + memset(p, 0, size); + return p; +} + +static inline void ipq5332_free_mem(void *ptr) +{ + if (ptr) + free(ptr); +} + +uint32_t ipq5332_edma_reg_read(uint32_t reg_off); +void ipq5332_edma_reg_write(uint32_t reg_off, uint32_t val); + + +extern int get_eth_mac_address(uchar *enetaddr, uint no_of_macs); + +typedef struct { + uint count; + u8 addr[7]; +} ipq5332_edma_phy_addr_t; + +/* ipq5332 edma Paramaters */ +typedef struct { + uint base; + int unit; + uint mac_conn_to_phy; + phy_interface_t phy; + ipq5332_edma_phy_addr_t phy_addr; + char phy_name[MDIO_NAME_LEN]; +} ipq5332_edma_board_cfg_t; + +extern void ipq5332_ppe_provision_init(void); +extern void ipq5332_port_mac_clock_reset(int port); +extern void ipq5332_speed_clock_set(int port, int clk[4]); +extern void ipq5332_pqsgmii_speed_set(int port, int speed, int status); +extern void ipq5332_uxsgmii_speed_set(int port, int speed, int duplex, int status); +extern void ppe_port_mux_mac_type_set(int port_id, int mode); +extern void ppe_port_bridge_txmac_set(int port, int status); +extern void ipq5332_10g_r_speed_set(int port, int status); +extern int phy_status_get_from_ppe(int port_id); + +extern void ipq5332_ppe_acl_set(int rule_id, int rule_type, int pkt_type, int l4_port_no, int l4_port_mask, int permit, int deny); +extern void ppe_uniphy_mode_set(uint32_t uniphy_index, uint32_t mode); +#endif /* ___IPQ5332_EDMA__ */ diff --git a/sources/uboot-be550/drivers/net/ipq5332/ipq5332_ppe.c b/sources/uboot-be550/drivers/net/ipq5332/ipq5332_ppe.c new file mode 100644 index 00000000..e1f0e99e --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq5332/ipq5332_ppe.c @@ -0,0 +1,883 @@ +/* + ************************************************************************** + * Copyright (c) 2016-2019, 2021, The Linux Foundation. All rights reserved. + * + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + ************************************************************************** +*/ + +#include +#include +#include "ipq5332_ppe.h" +#include "ipq5332_uniphy.h" +#include +#include "ipq_phy.h" + +DECLARE_GLOBAL_DATA_PTR; +#ifdef DEBUG +#define pr_debug(fmt, args...) printf(fmt, ##args); +#else +#define pr_debug(fmt, args...) +#endif + +#define pr_info(fmt, args...) printf(fmt, ##args); + +/* + * ipq5332_ppe_reg_read() + */ +static inline void ipq5332_ppe_reg_read(u32 reg, u32 *val) +{ + *val = readl((void *)(IPQ5332_PPE_BASE_ADDR + reg)); +} + +/* + * ipq5332_ppe_reg_write() + */ +static inline void ipq5332_ppe_reg_write(u32 reg, u32 val) +{ + writel(val, (void *)(IPQ5332_PPE_BASE_ADDR + reg)); +} + +void ppe_ipo_rule_reg_set(union ipo_rule_reg_u *hw_reg, int rule_id) +{ + int i; + + for (i = 0; i < 3; i++) { + ipq5332_ppe_reg_write(IPO_CSR_BASE_ADDR + IPO_RULE_REG_ADDRESS + + (rule_id * IPO_RULE_REG_INC) + (i * 4), hw_reg->val[i]); + } +} + +void ppe_ipo_mask_reg_set(union ipo_mask_reg_u *hw_mask, int rule_id) +{ + int i; + + for (i = 0; i < 2; i++) { + ipq5332_ppe_reg_write((IPO_CSR_BASE_ADDR + IPO_MASK_REG_ADDRESS + + (rule_id * IPO_MASK_REG_INC) + (i * 4)), hw_mask->val[i]); + } +} + +void ppe_ipo_action_set(union ipo_action_u *hw_act, int rule_id) +{ + int i; + + for (i = 0; i < 5; i++) { + ipq5332_ppe_reg_write((IPE_L2_BASE_ADDR + IPO_ACTION_ADDRESS + + (rule_id * IPO_ACTION_INC) + (i * 4)), hw_act->val[i]); + } +} + +void ipq5332_ppe_acl_set(int rule_id, int rule_type, int field0, int field1, + int mask, int permit, int deny) +{ + union ipo_rule_reg_u hw_reg = {0}; + union ipo_mask_reg_u hw_mask = {0}; + union ipo_action_u hw_act = {0}; + + memset(&hw_reg, 0, sizeof(hw_reg)); + memset(&hw_mask, 0, sizeof(hw_mask)); + memset(&hw_act, 0, sizeof(hw_act)); + + if (rule_id < MAX_RULE) { + hw_act.bf.dest_info_change_en = 1; + hw_mask.bf.maskfield_0 = mask; + hw_reg.bf.rule_type = rule_type; + if (rule_type == ADPT_ACL_HPPE_IPV4_DIP_RULE) { + hw_reg.bf.rule_field_0 = field1; + hw_reg.bf.rule_field_1 = field0<<17; + hw_mask.bf.maskfield_1 = 7<<17; + if (permit == 0x0) { + hw_act.bf.fwd_cmd = 0;/* forward */ + hw_reg.bf.pri = 0x1; + } + if (deny == 0x1) { + hw_act.bf.fwd_cmd = 1;/* drop */ + hw_reg.bf.pri = 0x0; + } + } else if (rule_type == ADPT_ACL_HPPE_MAC_SA_RULE) { + /* src mac AC rule */ + hw_reg.bf.rule_field_0 = field1; + hw_reg.bf.rule_field_1 = field0; + hw_mask.bf.maskfield_1 = 0xffff; + hw_act.bf.fwd_cmd = 1;/* drop */ + hw_reg.bf.pri = 0x2; + /* bypass fdb lean and fdb freash */ + hw_act.bf.bypass_bitmap_0 = 0x1800; + } else if (rule_type == ADPT_ACL_HPPE_MAC_DA_RULE) { + /* dest mac AC rule */ + hw_reg.bf.rule_field_0 = field1; + hw_reg.bf.rule_field_1 = field0; + hw_mask.bf.maskfield_1 = 0xffff; + hw_act.bf.fwd_cmd = 1;/* drop */ + hw_reg.bf.pri = 0x2; + } + /* bind port1-port6 */ + hw_reg.bf.src_0 = 0x0; + hw_reg.bf.src_1 = 0x3F; + ppe_ipo_rule_reg_set(&hw_reg, rule_id); + ppe_ipo_mask_reg_set(&hw_mask, rule_id); + ppe_ipo_action_set(&hw_act, rule_id); + } +} + +/* + * ipq5332_ppe_vp_port_tbl_set() + */ +static void ipq5332_ppe_vp_port_tbl_set(int port, int vsi) +{ + u32 addr = IPQ5332_PPE_L3_VP_PORT_TBL_ADDR + + (port * IPQ5332_PPE_L3_VP_PORT_TBL_INC); + ipq5332_ppe_reg_write(addr, 0x0); + ipq5332_ppe_reg_write(addr + 0x4 , 1 << 9 | vsi << 10); + ipq5332_ppe_reg_write(addr + 0x8, 0x0); + ipq5332_ppe_reg_write(addr + 0xc, 0x0); +} + +/* + * ipq5332_ppe_ucast_queue_map_tbl_queue_id_set() + */ +static void ipq5332_ppe_ucast_queue_map_tbl_queue_id_set(int queue, int port) +{ + uint32_t val; + + ipq5332_ppe_reg_read(IPQ5332_PPE_QM_UQM_TBL + + (port * IPQ5332_PPE_UCAST_QUEUE_MAP_TBL_INC), &val); + + val |= queue << 4; + + ipq5332_ppe_reg_write(IPQ5332_PPE_QM_UQM_TBL + + (port * IPQ5332_PPE_UCAST_QUEUE_MAP_TBL_INC), val); +} + +/* + * ipq5332_vsi_setup() + */ +static void ipq5332_vsi_setup(int vsi, uint8_t group_mask) +{ + uint32_t val = (group_mask << 24 | group_mask << 16 | group_mask << 8 + | group_mask); + + /* Set mask */ + ipq5332_ppe_reg_write(0x063800 + (vsi * 0x10), val); + + /* new addr lrn en | station move lrn en */ + ipq5332_ppe_reg_write(0x063804 + (vsi * 0x10), 0x9); +} + +/* + * ipq5332_gmac_port_disable() + */ +void ipq5332_gmac_port_disable(int port) +{ + ipq5332_ppe_reg_write(IPQ5332_PPE_MAC_ENABLE + (0x200 * port), 0x70); + ipq5332_ppe_reg_write(IPQ5332_PPE_MAC_SPEED + (0x200 * port), 0x2); + ipq5332_ppe_reg_write(IPQ5332_PPE_MAC_MIB_CTL + (0x200 * port), 0x1); +} + +/* + * ppe_port_bridge_txmac_set() + * TXMAC should be disabled for all ports by default + * TXMAC should be enabled for all ports that are link up alone + */ +void ppe_port_bridge_txmac_set(int port_id, int status) +{ + uint32_t reg_value = 0; + + ipq5332_ppe_reg_read(IPE_L2_BASE_ADDR + PORT_BRIDGE_CTRL_ADDRESS + + ((port_id * PORT_BRIDGE_CTRL_INC) + PORT_BRIDGE_CTRL_INC), + ®_value); + if (status == 0) + reg_value |= TX_MAC_EN; + else + reg_value &= ~TX_MAC_EN; + + ipq5332_ppe_reg_write(IPE_L2_BASE_ADDR + PORT_BRIDGE_CTRL_ADDRESS + + ((port_id * PORT_BRIDGE_CTRL_INC) + PORT_BRIDGE_CTRL_INC), + reg_value); + +} + +void ppe_port_txmac_status_set(uint32_t port) +{ + uint32_t reg_value = 0; + + pr_debug("DEBUGGING txmac_status_set......... PORTID = %d\n", port); + ipq5332_ppe_reg_read(PPE_SWITCH_NSS_SWITCH_XGMAC0 + + (port * NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION), ®_value); + + reg_value |=TE; + ipq5332_ppe_reg_write(PPE_SWITCH_NSS_SWITCH_XGMAC0 + + (port * NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION), reg_value); + + pr_debug("NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION Address" + " = 0x%x -> Value = %u\n", + PPE_SWITCH_NSS_SWITCH_XGMAC0 + + (port * NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION), + reg_value); +} + +void ppe_port_rxmac_status_set(uint32_t port) +{ + uint32_t reg_value = 0; + + pr_debug("DEBUGGING rxmac_status_set......... PORTID = %d\n", port); + ipq5332_ppe_reg_read(PPE_SWITCH_NSS_SWITCH_XGMAC0 + + MAC_RX_CONFIGURATION_ADDRESS + + (port * NSS_SWITCH_XGMAC_MAC_RX_CONFIGURATION), + ®_value); + + reg_value |= 0x300000c0; + reg_value |=RE; + reg_value |=ACS; + reg_value |=CST; + ipq5332_ppe_reg_write(PPE_SWITCH_NSS_SWITCH_XGMAC0 + + MAC_RX_CONFIGURATION_ADDRESS + + (port * NSS_SWITCH_XGMAC_MAC_RX_CONFIGURATION), + reg_value); + + pr_debug("NSS_SWITCH_XGMAC_MAC_RX_CONFIGURATION Address" + " = 0x%x -> Value = %u\n", + PPE_SWITCH_NSS_SWITCH_XGMAC0 + MAC_RX_CONFIGURATION_ADDRESS + + (port * NSS_SWITCH_XGMAC_MAC_RX_CONFIGURATION), + reg_value); +} + +void ppe_mac_packet_filter_set(uint32_t port) +{ + pr_debug("DEBUGGING mac_packet_filter_set...... PORTID = %d\n", port); + ipq5332_ppe_reg_write(PPE_SWITCH_NSS_SWITCH_XGMAC0 + + MAC_PACKET_FILTER_ADDRESS + + (port * MAC_PACKET_FILTER_INC), 0x80000081); + pr_debug("NSS_SWITCH_XGMAC_MAC_PACKET_FILTER Address" + " = 0x%x -> Value = %u\n", + PPE_SWITCH_NSS_SWITCH_XGMAC0 + MAC_PACKET_FILTER_ADDRESS + + (port * MAC_PACKET_FILTER_ADDRESS), + 0x80000081); +} +/* + * ipq5332_port_mac_clock_reset() + */ +void ipq5332_port_mac_clock_reset(int port) +{ + int reg_val; + + reg_val = readl(NSS_CC_UNIPHY_PORT1_RX_CBCR + (port * 0x8)); + reg_val |= GCC_PORT1_ARES; + writel(reg_val, NSS_CC_UNIPHY_PORT1_RX_CBCR + (port * 0x8)); + mdelay(10); + reg_val = readl(NSS_CC_UNIPHY_PORT1_RX_CBCR + (port * 0x8)); + reg_val &= ~GCC_PORT1_ARES; + writel(reg_val, NSS_CC_UNIPHY_PORT1_RX_CBCR + (port * 0x8)); + + reg_val = readl(NSS_CC_UNIPHY_PORT1_RX_CBCR + 0x4 + (port * 0x8)); + reg_val |= GCC_PORT1_ARES; + writel(reg_val, NSS_CC_UNIPHY_PORT1_RX_CBCR + 0x4 + (port * 0x8)); + mdelay(10); + reg_val = readl(NSS_CC_UNIPHY_PORT1_RX_CBCR + 0x4 + (port * 0x8)); + reg_val &= ~GCC_PORT1_ARES; + writel(reg_val, NSS_CC_UNIPHY_PORT1_RX_CBCR + 0x4 + (port * 0x8)); +} + +void ipq5332_speed_clock_set(int port_id, int clk[4]) +{ + int i; + int reg_val[6]; + + for (i = 0; i < 6; i++) + { + reg_val[i] = readl(NSS_CC_PORT1_RX_CMD_RCGR + (i * 0x4) + + (port_id * 0x18)); + } + reg_val[0] &= ~0x1; + reg_val[1] &= ~0x71f; + reg_val[2] &= ~0xf; + reg_val[3] &= ~0x1; + reg_val[4] &= ~0x71f; + reg_val[5] &= ~0xf; + + reg_val[1] |= clk[0]; + reg_val[2] |= clk[1]; + reg_val[4] |= clk[2]; + reg_val[5] |= clk[3]; + + /* Port Rx direction speed clock cfg */ + writel(reg_val[1], NSS_CC_PORT1_RX_CMD_RCGR + 0x4 + (port_id * 0x18)); + writel(reg_val[2], NSS_CC_PORT1_RX_CMD_RCGR + 0x8 + (port_id * 0x18)); + writel(reg_val[0] | 0x1 , NSS_CC_PORT1_RX_CMD_RCGR + (port_id * 0x18)); + /* Port Tx direction speed clock cfg */ + writel(reg_val[4], NSS_CC_PORT1_RX_CMD_RCGR + 0x10 + (port_id * 0x18)); + writel(reg_val[5], NSS_CC_PORT1_RX_CMD_RCGR + 0x14 + (port_id * 0x18)); + writel(reg_val[3] | 0x1, NSS_CC_PORT1_RX_CMD_RCGR + 0xc + + (port_id * 0x18)); + + /* Enable UNIPHY port clk */ + mdelay(100); + writel(BIT(0), (NSS_CC_UNIPHY_PORT1_RX_CBCR + (port_id * 0x8))); + mdelay(100); + writel(BIT(0), (NSS_CC_UNIPHY_PORT1_TX_CBCR + (port_id * 0x8))); + mdelay(100); +} + +int phy_status_get_from_ppe(int port_id) +{ + uint32_t reg_field = 0; + + ipq5332_ppe_reg_read(PORT_PHY_STATUS_ADDRESS, ®_field); + + if (port_id == 1) + reg_field >>= PORT_PHY_STATUS_PORT2_OFFSET; + + return ((reg_field >> 7) & 0x1) ? 0 : 1; +} + +void ppe_xgmac_10g_r_speed_set(uint32_t port) +{ + uint32_t reg_value = 0; + + pr_debug("DEBUGGING 10g_r_speed_set......... PORTID = %d\n", port); + ipq5332_ppe_reg_read(PPE_SWITCH_NSS_SWITCH_XGMAC0 + + (port * NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION), ®_value); + + reg_value |=JD; + ipq5332_ppe_reg_write(PPE_SWITCH_NSS_SWITCH_XGMAC0 + + (port * NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION), reg_value); + + pr_debug("NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION Address = 0x%x" + "-> Value = %u\n", + PPE_SWITCH_NSS_SWITCH_XGMAC0 + + (port * NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION), + reg_value); +} + +void ipq5332_10g_r_speed_set(int port, int status) +{ + ppe_xgmac_10g_r_speed_set(port); + ppe_port_bridge_txmac_set(port, status); + ppe_port_txmac_status_set(port); + ppe_port_rxmac_status_set(port); + ppe_mac_packet_filter_set(port); +} + +void ppe_xgmac_speed_set(uint32_t port, int speed) +{ + uint32_t reg_value = 0; + + pr_debug("\nDEBUGGING xgmac_speed_set......... PORTID = %d\n", port); + ipq5332_ppe_reg_read(PPE_SWITCH_NSS_SWITCH_XGMAC0 + + (port * NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION), ®_value); + + switch(speed) { + case 0: + case 1: + case 2: + reg_value &=~USS; + reg_value |=SS(XGMAC_SPEED_SELECT_1000M); + break; + case 3: + reg_value |=USS; + reg_value |=SS(XGMAC_SPEED_SELECT_10000M); + break; + case 4: + reg_value |=USS; + reg_value |=SS(XGMAC_SPEED_SELECT_2500M); + break; + case 5: + reg_value |=USS; + reg_value |=SS(XGMAC_SPEED_SELECT_5000M); + break; + } + reg_value |=JD; + ipq5332_ppe_reg_write(PPE_SWITCH_NSS_SWITCH_XGMAC0 + + (port * NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION), reg_value); + pr_debug("NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION Address = 0x%x" + " -> Value = %u\n", + PPE_SWITCH_NSS_SWITCH_XGMAC0 + + (port * NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION), + reg_value); +} + +void ipq5332_xgmac_sgmiiplus_speed_set(int port, int speed, int status) +{ + uint32_t reg_value = 0; + + pr_debug("\nDEBUGGING xgmac_sgmiiplus speed_set..PORTID = %d\n", port); + ipq5332_ppe_reg_read(PPE_SWITCH_NSS_SWITCH_XGMAC0 + + (port * NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION), ®_value); + + switch(speed) { + case 0: + case 1: + case 2: + reg_value |=SS(XGMAC_SPEED_SELECT_1000M); + break; + case 3: + reg_value |=SS(XGMAC_SPEED_SELECT_10000M); + break; + case 4: + reg_value |=SS(XGMAC_SPEED_SELECT_2500M); + break; + case 5: + reg_value |=SS(XGMAC_SPEED_SELECT_5000M); + break; + } + reg_value |=JD; + ipq5332_ppe_reg_write(PPE_SWITCH_NSS_SWITCH_XGMAC0 + + (port * NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION), reg_value); + pr_debug("NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION Address = 0x%x" + " -> Value = %u\n", + PPE_SWITCH_NSS_SWITCH_XGMAC0 + + (port * NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION), + reg_value); + + ppe_port_bridge_txmac_set(port, status); + ppe_port_txmac_status_set(port); + ppe_port_rxmac_status_set(port); + ppe_mac_packet_filter_set(port); +} + +void ipq5332_uxsgmii_speed_set(int port, int speed, int duplex, + int status) +{ + uint32_t uniphy_index; + + if (port == PORT0) + uniphy_index = PPE_UNIPHY_INSTANCE0; + else + uniphy_index = PPE_UNIPHY_INSTANCE1; + + ppe_uniphy_usxgmii_autoneg_completed(uniphy_index); + ppe_uniphy_usxgmii_speed_set(uniphy_index, speed); + ppe_xgmac_speed_set(port, speed); + ppe_uniphy_usxgmii_duplex_set(uniphy_index, duplex); + ppe_uniphy_usxgmii_port_reset(uniphy_index); + ppe_port_bridge_txmac_set(port, status); + ppe_port_txmac_status_set(port); + ppe_port_rxmac_status_set(port); + ppe_mac_packet_filter_set(port); +} + +void ipq5332_pqsgmii_speed_set(int port, int speed, int status) +{ + ppe_port_bridge_txmac_set(port, status); + ipq5332_ppe_reg_write(IPQ5332_PPE_MAC_SPEED + (0x200 * port), speed); + ipq5332_ppe_reg_write(IPQ5332_PPE_MAC_ENABLE + (0x200 * port), 0x73); + ipq5332_ppe_reg_write(IPQ5332_PPE_MAC_MIB_CTL + (0x200 * port), 0x1); +} + +/* + * ipq5332_ppe_flow_port_map_tbl_port_num_set() + */ +static void ipq5332_ppe_flow_port_map_tbl_port_num_set(int queue, int port) +{ + ipq5332_ppe_reg_write(IPQ5332_PPE_L0_FLOW_PORT_MAP_TBL + + queue * IPQ5332_PPE_L0_FLOW_PORT_MAP_TBL_INC, port); + ipq5332_ppe_reg_write(IPQ5332_PPE_L1_FLOW_PORT_MAP_TBL + + port * IPQ5332_PPE_L1_FLOW_PORT_MAP_TBL_INC, port); +} + +/* + * ipq5332_ppe_flow_map_tbl_set() + */ +static void ipq5332_ppe_flow_map_tbl_set(int queue, int port) +{ + uint32_t val = port | 0x401000; /* c_drr_wt = 1, e_drr_wt = 1 */ + ipq5332_ppe_reg_write(IPQ5332_PPE_L0_FLOW_MAP_TBL + queue * + IPQ5332_PPE_L0_FLOW_MAP_TBL_INC, val); + + val = port | 0x100400; /* c_drr_wt = 1, e_drr_wt = 1 */ + ipq5332_ppe_reg_write(IPQ5332_PPE_L1_FLOW_MAP_TBL + port * + IPQ5332_PPE_L1_FLOW_MAP_TBL_INC, val); +} + +/* + * ipq5332_ppe_tdm_configuration + */ +static void ipq5332_ppe_tdm_configuration(void) +{ + ipq5332_ppe_reg_write(0xc000, 0x22); + ipq5332_ppe_reg_write(0xc010, 0x30); + ipq5332_ppe_reg_write(0xc020, 0x21); + ipq5332_ppe_reg_write(0xc030, 0x31); + ipq5332_ppe_reg_write(0xc040, 0x22); + ipq5332_ppe_reg_write(0xc050, 0x32); + ipq5332_ppe_reg_write(0xc060, 0x20); + ipq5332_ppe_reg_write(0xc070, 0x30); + ipq5332_ppe_reg_write(0xc080, 0x22); + ipq5332_ppe_reg_write(0xc090, 0x31); + ipq5332_ppe_reg_write(0xc0a0, 0x21); + ipq5332_ppe_reg_write(0xc0b0, 0x32); + ipq5332_ppe_reg_write(0xc0c0, 0x20); + ipq5332_ppe_reg_write(0xc0d0, 0x30); + ipq5332_ppe_reg_write(0xc0e0, 0x20); + ipq5332_ppe_reg_write(0xc0f0, 0x31); + ipq5332_ppe_reg_write(0xc100, 0x22); + ipq5332_ppe_reg_write(0xc110, 0x32); + ipq5332_ppe_reg_write(0xc120, 0x21); + ipq5332_ppe_reg_write(0xc130, 0x30); + ipq5332_ppe_reg_write(0xc140, 0x22); + ipq5332_ppe_reg_write(0xc150, 0x31); + ipq5332_ppe_reg_write(0xc160, 0x20); + ipq5332_ppe_reg_write(0xc170, 0x32); + ipq5332_ppe_reg_write(0xc180, 0x22); + ipq5332_ppe_reg_write(0xc190, 0x30); + ipq5332_ppe_reg_write(0xc1a0, 0x21); + ipq5332_ppe_reg_write(0xc1b0, 0x31); + ipq5332_ppe_reg_write(0xc1c0, 0x20); + ipq5332_ppe_reg_write(0xc1d0, 0x32); + ipq5332_ppe_reg_write(0xb000, 0x80000020); + + writel(0x20,(void *)0x3a47a000); + writel(0x12,(void *)0x3a47a010); + writel(0x1 ,(void *)0x3a47a020); + writel(0x2 ,(void *)0x3a47a030); + writel(0x10,(void *)0x3a47a040); + writel(0x21,(void *)0x3a47a050); + writel(0x2 ,(void *)0x3a47a060); + writel(0x10,(void *)0x3a47a070); + writel(0x12,(void *)0x3a47a080); + writel(0x1 ,(void *)0x3a47a090); + writel(0xa ,(void *)0x3a400000); + + writel(0x303,(void *)0x3a026100); + writel(0x303,(void *)0x3a026104); + writel(0x303,(void *)0x3a026108); +} + +/* + * ipq5332_ppe_queue_ac_enable + */ +static void ipq5332_ppe_queue_ac_enable(void) +{ + int i; + + /* ucast queue */ + for (i = 0; i < 256; i++) { + ipq5332_ppe_reg_write(IPQ5332_PPE_UCAST_QUEUE_AC_EN_BASE_ADDR + + (i * 0x10), 0x32120001); + ipq5332_ppe_reg_write(IPQ5332_PPE_UCAST_QUEUE_AC_EN_BASE_ADDR + + (i * 0x10) + 0x4, 0x0); + ipq5332_ppe_reg_write(IPQ5332_PPE_UCAST_QUEUE_AC_EN_BASE_ADDR + + (i * 0x10) + 0x8, 0x0); + ipq5332_ppe_reg_write(IPQ5332_PPE_UCAST_QUEUE_AC_EN_BASE_ADDR + + (i * 0x10) + 0xc, 0x48000); + } + + /* mcast queue */ + for (i = 0; i < 44; i++) { + ipq5332_ppe_reg_write(IPQ5332_PPE_MCAST_QUEUE_AC_EN_BASE_ADDR + + (i * 0x10), 0x00fa0001); + ipq5332_ppe_reg_write(IPQ5332_PPE_MCAST_QUEUE_AC_EN_BASE_ADDR + + (i * 0x10) + 0x4, 0x0); + ipq5332_ppe_reg_write(IPQ5332_PPE_MCAST_QUEUE_AC_EN_BASE_ADDR + + (i * 0x10) + 0x8, 0x1200); + } +} + +/* + * ipq5332_ppe_enable_port_counter + */ +static void ipq5332_ppe_enable_port_counter(void) +{ + int i; + uint32_t reg = 0; + + for (i = 0; i < 7; i++) { + /* MRU_MTU_CTRL_TBL.rx_cnt_en, MRU_MTU_CTRL_TBL.tx_cnt_en */ + ipq5332_ppe_reg_read(IPQ5332_PPE_MRU_MTU_CTRL_TBL_ADDR + + (i * 0x10), ®); + ipq5332_ppe_reg_write(IPQ5332_PPE_MRU_MTU_CTRL_TBL_ADDR + + (i * 0x10), reg); + ipq5332_ppe_reg_read(IPQ5332_PPE_MRU_MTU_CTRL_TBL_ADDR + + (i * 0x10) + 0x4, ®); + ipq5332_ppe_reg_write(IPQ5332_PPE_MRU_MTU_CTRL_TBL_ADDR + + (i * 0x10) + 0x4, reg | 0x284303); + ipq5332_ppe_reg_read(IPQ5332_PPE_MRU_MTU_CTRL_TBL_ADDR + + (i * 0x10) + 0x8, ®); + ipq5332_ppe_reg_write(IPQ5332_PPE_MRU_MTU_CTRL_TBL_ADDR + + (i * 0x10) + 0x8, reg); + ipq5332_ppe_reg_read(IPQ5332_PPE_MRU_MTU_CTRL_TBL_ADDR + + (i * 0x10) + 0xc, ®); + ipq5332_ppe_reg_write(IPQ5332_PPE_MRU_MTU_CTRL_TBL_ADDR + + (i * 0x10) + 0xc, reg); + + /* MC_MTU_CTRL_TBL.tx_cnt_en */ + ipq5332_ppe_reg_read(IPQ5332_PPE_MC_MTU_CTRL_TBL_ADDR + + (i * 0x4), ®); + ipq5332_ppe_reg_write(IPQ5332_PPE_MC_MTU_CTRL_TBL_ADDR + + (i * 0x4), reg | 0x10000); + + /* PORT_EG_VLAN.tx_counting_en */ + ipq5332_ppe_reg_read(IPQ5332_PPE_PORT_EG_VLAN_TBL_ADDR + + (i * 0x4), ®); + ipq5332_ppe_reg_write(IPQ5332_PPE_PORT_EG_VLAN_TBL_ADDR + + (i * 0x4), reg | 0x100); + + /* TL_PORT_VP_TBL.rx_cnt_en */ + ipq5332_ppe_reg_read(IPQ5332_PPE_TL_PORT_VP_TBL_ADDR + + (i * 0x10), ®); + ipq5332_ppe_reg_write(IPQ5332_PPE_TL_PORT_VP_TBL_ADDR + + (i * 0x10), reg); + ipq5332_ppe_reg_read(IPQ5332_PPE_TL_PORT_VP_TBL_ADDR + + (i * 0x10) + 0x4, ®); + ipq5332_ppe_reg_write(IPQ5332_PPE_TL_PORT_VP_TBL_ADDR + + (i * 0x10) + 0x4, reg); + ipq5332_ppe_reg_read(IPQ5332_PPE_TL_PORT_VP_TBL_ADDR + + (i * 0x10) + 0x8, ®); + ipq5332_ppe_reg_write(IPQ5332_PPE_TL_PORT_VP_TBL_ADDR + + (i * 0x10) + 0x8, reg | 0x20000); + ipq5332_ppe_reg_read(IPQ5332_PPE_TL_PORT_VP_TBL_ADDR + + (i * 0x10) + 0xc, ®); + ipq5332_ppe_reg_write(IPQ5332_PPE_TL_PORT_VP_TBL_ADDR + + (i * 0x10) + 0xc, reg); + } +} + +/* + * ipq5332_ppe_c_sp_cfg_tbl_drr_id_set + */ +static void ipq5332_ppe_c_sp_cfg_tbl_drr_id_set(int id) +{ + ipq5332_ppe_reg_write(IPQ5332_PPE_L0_C_SP_CFG_TBL + + (id * 0x80), id * 2); + ipq5332_ppe_reg_write(IPQ5332_PPE_L1_C_SP_CFG_TBL + + (id * 0x80), id * 2); +} + +/* + * ipq5332_ppe_e_sp_cfg_tbl_drr_id_set + */ +static void ipq5332_ppe_e_sp_cfg_tbl_drr_id_set(int id) +{ + ipq5332_ppe_reg_write(IPQ5332_PPE_L0_E_SP_CFG_TBL + + (id * 0x80), id * 2 + 1); + ipq5332_ppe_reg_write(IPQ5332_PPE_L1_E_SP_CFG_TBL + + (id * 0x80), id * 2 + 1); +} + +static void ppe_port_mux_set(int port_id, int port_type, int mode) +{ + uint32_t mux_mac_type = 0; + union port_mux_ctrl_u port_mux_ctrl; + + pr_debug("\nport id is: %d, port type is %d, mode is %d", + port_id, port_type, mode); + + if (port_type == PORT_GMAC_TYPE) + mux_mac_type = IPQ5332_PORT_MUX_MAC_TYPE; + else if (port_type == PORT_XGMAC_TYPE) + mux_mac_type = IPQ5332_PORT_MUX_XMAC_TYPE; + else + printf("\nAttention!!!..Port type configured wrongly.." + "port_id = %d, mode = %d, port_type = %d", + port_id, mode, port_type); + + port_mux_ctrl.val = 0; + ipq5332_ppe_reg_read(IPQ5332_PORT_MUX_CTRL, &(port_mux_ctrl.val)); + pr_debug("\nBEFORE UPDATE: Port MUX CTRL value is %u", + port_mux_ctrl.val); + + switch (port_id) { + case PORT1: + port_mux_ctrl.bf.port1_mac_sel = mux_mac_type; + port_mux_ctrl.bf.port1_pcs_sel = 0; + break; + case PORT2: + port_mux_ctrl.bf.port2_mac_sel = mux_mac_type; + port_mux_ctrl.bf.port2_pcs_sel = 0; + break; + default: + break; + } + + ipq5332_ppe_reg_write(IPQ5332_PORT_MUX_CTRL, port_mux_ctrl.val); + pr_debug("\nAFTER UPDATE: Port MUX CTRL value is %u", + port_mux_ctrl.val); +} + +void ppe_port_mux_mac_type_set(int port_id, int mode) +{ + uint32_t port_type; + + switch(mode) + { + case EPORT_WRAPPER_PSGMII: + case EPORT_WRAPPER_SGMII0_RGMII4: + case EPORT_WRAPPER_SGMII_FIBER: + port_type = PORT_GMAC_TYPE; + break; + case EPORT_WRAPPER_SGMII_PLUS: + case EPORT_WRAPPER_USXGMII: + case EPORT_WRAPPER_10GBASE_R: + port_type = PORT_XGMAC_TYPE; + break; + default: + printf("\nError during port_type set: mode is %d, " + "port_id is: %d", + mode, port_id); + return; + } + ppe_port_mux_set(port_id, port_type, mode); +} + +void ipq5332_ppe_interface_mode_init(void) +{ + uint32_t mode0, mode1; + int node; + node = fdt_path_offset(gd->fdt_blob, "/ess-switch"); + if (node < 0) { + printf("\nError: ess-switch not specified in dts"); + return; + } + + mode0 = fdtdec_get_uint(gd->fdt_blob, node, "switch_mac_mode0", -1); + if (mode0 < 0) { + printf("\nError: switch_mac_mode0 not specified in dts"); + return; + } + + mode1 = fdtdec_get_uint(gd->fdt_blob, node, "switch_mac_mode1", -1); + if (mode1 < 0) { + printf("\nError: switch_mac_mode1 not specified in dts"); + return; + } + + ppe_uniphy_mode_set(PPE_UNIPHY_INSTANCE0, mode0); + ppe_uniphy_mode_set(PPE_UNIPHY_INSTANCE1, mode1); + /* + * Port1 and Port2 can be used as GMAC or XGMAC. + */ + ppe_port_mux_mac_type_set(PORT1, mode0); + ppe_port_mux_mac_type_set(PORT2, mode1); +} + +/* + * ipq5332_ppe_provision_init() + */ +void ipq5332_ppe_provision_init(void) +{ + int i; + uint32_t queue; + uint32_t bridge_ctrl; + + /* tdm/sched configuration */ + ipq5332_ppe_tdm_configuration(); + +#ifdef CONFIG_IPQ5332_BRIDGED_MODE + /* Add CPU port 0 to VSI 2 */ + ipq5332_ppe_vp_port_tbl_set(0, 2); + + /* Add port 1 - 2 to VSI 2 */ + ipq5332_ppe_vp_port_tbl_set(1, 2); + ipq5332_ppe_vp_port_tbl_set(2, 2); + +#else + ipq5332_ppe_vp_port_tbl_set(1, 2); + ipq5332_ppe_vp_port_tbl_set(2, 3); +#endif + + /* Unicast priority map */ + ipq5332_ppe_reg_write(IPQ5332_PPE_QM_UPM_TBL, 0); + + /* Port0 - 3 unicast queue settings */ + for (i = 0; i < 3; i++) { + if (i == 0) + queue = 0; + else + queue = ((i * 0x10) + 0x70); + + ipq5332_ppe_ucast_queue_map_tbl_queue_id_set(queue, i); + ipq5332_ppe_flow_port_map_tbl_port_num_set(queue, i); + ipq5332_ppe_flow_map_tbl_set(queue, i); + ipq5332_ppe_c_sp_cfg_tbl_drr_id_set(i); + ipq5332_ppe_e_sp_cfg_tbl_drr_id_set(i); + } + + /* Port0 multicast queue */ + ipq5332_ppe_reg_write(0x409000, 0x00000000); + ipq5332_ppe_reg_write(0x403000, 0x00401000); + + /* Port1 - 7 multicast queue */ + for (i = 1; i < 3; i++) { + ipq5332_ppe_reg_write(0x409100 + ((i - 1) * 0x40), i); + ipq5332_ppe_reg_write(0x403100 + ((i - 1) * 0x40), 0x401000 | i); + } + + /* ac enable for queues - disable queue tail drop */ + ipq5332_ppe_queue_ac_enable(); + + /* enable queue counter */ + ipq5332_ppe_reg_write(0x020044,0x4); + + /* assign the ac group 0 with buffer number */ + ipq5332_ppe_reg_write(0x84c000, 0x0); + ipq5332_ppe_reg_write(0x84c004, 0x7D00); + ipq5332_ppe_reg_write(0x84c008, 0x0); + ipq5332_ppe_reg_write(0x84c00c, 0x0); + + /* enable physical/virtual port TX/RX counters for all ports (0-6) */ + ipq5332_ppe_enable_port_counter(); + + /* + * Port0 - TX_EN is set by default, Port1 - LRN_EN is set + * Port0 -> CPU Port + * Port1-2 -> Ethernet Ports + */ + for (i = 0; i < 3; i++) { + bridge_ctrl = IPQ5332_PPE_PORT_BRIDGE_CTRL_OFFSET; + if (i == 0) { + ipq5332_ppe_reg_write(bridge_ctrl + (i * 4), + IPQ5332_PPE_PORT_BRIDGE_CTRL_PROMISC_EN | + IPQ5332_PPE_PORT_BRIDGE_CTRL_TXMAC_EN | + IPQ5332_PPE_PORT_BRIDGE_CTRL_PORT_ISOLATION_BMP | + IPQ5332_PPE_PORT_BRIDGE_CTRL_STATION_LRN_EN | + IPQ5332_PPE_PORT_BRIDGE_CTRL_NEW_ADDR_LRN_EN); + } else { + ipq5332_ppe_reg_write(bridge_ctrl + (i * 4), + IPQ5332_PPE_PORT_BRIDGE_CTRL_PROMISC_EN | + IPQ5332_PPE_PORT_BRIDGE_CTRL_PORT_ISOLATION_BMP); + } + } + + /* Global learning */ + ipq5332_ppe_reg_write(0x060038, 0xc0); + +#ifdef CONFIG_IPQ5332_BRIDGED_MODE + ipq5332_vsi_setup(2, 0x7); +#else + ipq5332_vsi_setup(2, 0x03); + ipq5332_vsi_setup(3, 0x05); +#endif + + /* Port 0-3 STP */ + for (i = 0; i < 3; i++) + ipq5332_ppe_reg_write(IPQ5332_PPE_STP_BASE + (0x4 * i), 0x3); + + ipq5332_ppe_interface_mode_init(); + /* Port 1-2 disable */ + for (i = 0; i < 2; i++) { + ipq5332_gmac_port_disable(i); + ppe_port_bridge_txmac_set(i, 1); + } + + /* Allowing DHCP packets */ + ipq5332_ppe_acl_set(0, ADPT_ACL_HPPE_IPV4_DIP_RULE, UDP_PKT, 67, + 0xffff, 0, 0); + ipq5332_ppe_acl_set(1, ADPT_ACL_HPPE_IPV4_DIP_RULE, UDP_PKT, 68, + 0xffff, 0, 0); + /* Dropping all the UDP packets */ + ipq5332_ppe_acl_set(2, ADPT_ACL_HPPE_IPV4_DIP_RULE, UDP_PKT, 0, 0, 0, + 1); +} diff --git a/sources/uboot-be550/drivers/net/ipq5332/ipq5332_ppe.h b/sources/uboot-be550/drivers/net/ipq5332/ipq5332_ppe.h new file mode 100644 index 00000000..6d557a57 --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq5332/ipq5332_ppe.h @@ -0,0 +1,268 @@ +/* + ************************************************************************** + * Copyright (c) 2016-2019, 2021, The Linux Foundation. All rights reserved. + * + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + ************************************************************************** +*/ + +#include +#include +#include +#include +#include +#include +#include + +#define IPQ5332_PPE_BASE_ADDR 0x3a000000 + +#define IPQ5332_PORT5_MUX_PCS_UNIPHY0 0x0 +#define IPQ5332_PORT5_MUX_PCS_UNIPHY1 0x1 + +#define PORT_GMAC_TYPE 1 +#define PORT_XGMAC_TYPE 2 + +#define IPQ5332_PORT_MUX_MAC_TYPE 0 +#define IPQ5332_PORT_MUX_XMAC_TYPE 1 + +struct port_mux_ctrl { + uint32_t port1_pcs_sel:1; + uint32_t port2_pcs_sel:1; + uint32_t _reserved0:6; + uint32_t port1_mac_sel:1; + uint32_t port2_mac_sel:1; + uint32_t _reserved1:22; +}; + +union port_mux_ctrl_u { + uint32_t val; + struct port_mux_ctrl bf; +}; + +enum { + TCP_PKT, + UDP_PKT, +}; + +#define ADPT_ACL_HPPE_IPV4_DIP_RULE 4 +#define ADPT_ACL_HPPE_MAC_SA_RULE 1 +#define ADPT_ACL_HPPE_MAC_DA_RULE 0 +#define MAX_RULE 512 + +struct ipo_rule_reg { + uint32_t rule_field_0:32; + uint32_t rule_field_1:20; + uint32_t fake_mac_header:1; + uint32_t range_en:1; + uint32_t inverse_en:1; + uint32_t rule_type:5; + uint32_t src_type:3; + uint32_t src_0:1; + uint32_t src_1:7; + uint32_t pri:9; + uint32_t res_chain:1; + uint32_t post_routing_en:1; + uint32_t _reserved0:14; +}; + +union ipo_rule_reg_u { + uint32_t val[3]; + struct ipo_rule_reg bf; +}; + +struct ipo_mask_reg { + uint32_t maskfield_0:32; + uint32_t maskfield_1:21; + uint32_t _reserved0:11; +}; + +union ipo_mask_reg_u { + uint32_t val[2]; + struct ipo_mask_reg bf; +}; + +struct ipo_action { + uint32_t dest_info_change_en:1; + uint32_t fwd_cmd:2; + uint32_t _reserved0:15; + uint32_t bypass_bitmap_0:14; + uint32_t bypass_bitmap_1:18; + uint32_t _reserved1:14; + uint32_t _reserved2:32; + uint32_t _reserved3:32; + uint32_t _reserved4:32; +}; + +union ipo_action_u { + uint32_t val[5]; + struct ipo_action bf; +}; + +#define IPQ5332_PORT_MUX_CTRL 0x10 +#define IPQ5332_PORT_MUX_CTRL_NUM 1 +#define IPQ5332_PORT_MUX_CTRL_INC 0x4 +#define IPQ5332_PORT_MUX_CTRL_DEFAULT 0x0 + +#define PORT_PHY_STATUS_ADDRESS 0x40 +#define PORT_PHY_STATUS_PORT2_OFFSET 8 + +#define IPQ5332_PPE_IPE_L3_BASE_ADDR 0x200000 +#define IPQ5332_PPE_L3_VP_PORT_TBL_ADDR (IPQ5332_PPE_IPE_L3_BASE_ADDR + 0x4000) +#define IPQ5332_PPE_L3_VP_PORT_TBL_INC 0x10 + +#define IPQ5332_PPE_TL_PORT_VP_TBL_ADDR 0x302000 +#define IPQ5332_PPE_MRU_MTU_CTRL_TBL_ADDR 0x65000 +#define IPQ5332_PPE_MC_MTU_CTRL_TBL_ADDR 0x60a00 +#define IPQ5332_PPE_PORT_EG_VLAN_TBL_ADDR 0x20020 + +#define IPQ5332_PPE_UCAST_QUEUE_AC_EN_BASE_ADDR 0x848000 +#define IPQ5332_PPE_MCAST_QUEUE_AC_EN_BASE_ADDR 0x84a000 +#define IPQ5332_PPE_QUEUE_MANAGER_BASE_ADDR 0x800000 +#define IPQ5332_PPE_UCAST_QUEUE_MAP_TBL_ADDR 0x10000 +#define IPQ5332_PPE_UCAST_QUEUE_MAP_TBL_INC 0x10 +#define IPQ5332_PPE_QM_UQM_TBL (IPQ5332_PPE_QUEUE_MANAGER_BASE_ADDR +\ + IPQ5332_PPE_UCAST_QUEUE_MAP_TBL_ADDR) +#define IPQ5332_PPE_UCAST_PRIORITY_MAP_TBL_ADDR 0x42000 +#define IPQ5332_PPE_QM_UPM_TBL (IPQ5332_PPE_QUEUE_MANAGER_BASE_ADDR +\ + IPQ5332_PPE_UCAST_PRIORITY_MAP_TBL_ADDR) + +#define IPQ5332_PPE_STP_BASE 0x060100 +#define IPQ5332_PPE_MAC_ENABLE 0x001000 +#define IPQ5332_PPE_MAC_SPEED 0x001004 +#define IPQ5332_PPE_MAC_MIB_CTL 0x001034 + +#define IPQ5332_PPE_TRAFFIC_MANAGER_BASE_ADDR 0x400000 +#define IPQ5332_PPE_TM_SHP_CFG_L0_OFFSET 0x00000030 +#define IPQ5332_PPE_TM_SHP_CFG_L1_OFFSET 0x00000034 +#define IPQ5332_PPE_TM_SHP_CFG_L0 IPQ5332_PPE_TRAFFIC_MANAGER_BASE_ADDR +\ + IPQ5332_PPE_TM_SHP_CFG_L0_OFFSET +#define IPQ5332_PPE_TM_SHP_CFG_L1 IPQ5332_PPE_TRAFFIC_MANAGER_BASE_ADDR +\ + IPQ5332_PPE_TM_SHP_CFG_L1_OFFSET + +#define IPQ5332_PPE_L0_FLOW_PORT_MAP_TBL_ADDR 0x10000 +#define IPQ5332_PPE_L0_FLOW_PORT_MAP_TBL_INC 0x10 +#define IPQ5332_PPE_L0_FLOW_PORT_MAP_TBL (IPQ5332_PPE_TRAFFIC_MANAGER_BASE_ADDR +\ + IPQ5332_PPE_L0_FLOW_PORT_MAP_TBL_ADDR) + +#define IPQ5332_PPE_L0_FLOW_MAP_TBL_ADDR 0x2000 +#define IPQ5332_PPE_L0_FLOW_MAP_TBL_INC 0x10 +#define IPQ5332_PPE_L0_FLOW_MAP_TBL (IPQ5332_PPE_TRAFFIC_MANAGER_BASE_ADDR +\ + IPQ5332_PPE_L0_FLOW_MAP_TBL_ADDR) + +#define IPQ5332_PPE_L1_FLOW_PORT_MAP_TBL_ADDR 0x46000 +#define IPQ5332_PPE_L1_FLOW_PORT_MAP_TBL_INC 0x10 +#define IPQ5332_PPE_L1_FLOW_PORT_MAP_TBL (IPQ5332_PPE_TRAFFIC_MANAGER_BASE_ADDR +\ + IPQ5332_PPE_L1_FLOW_PORT_MAP_TBL_ADDR) + +#define IPQ5332_PPE_L1_FLOW_MAP_TBL_ADDR 0x40000 +#define IPQ5332_PPE_L1_FLOW_MAP_TBL_INC 0x10 +#define IPQ5332_PPE_L1_FLOW_MAP_TBL (IPQ5332_PPE_TRAFFIC_MANAGER_BASE_ADDR +\ + IPQ5332_PPE_L1_FLOW_MAP_TBL_ADDR) + +#define IPQ5332_PPE_L0_C_SP_CFG_TBL_ADDR 0x4000 +#define IPQ5332_PPE_L0_C_SP_CFG_TBL (IPQ5332_PPE_TRAFFIC_MANAGER_BASE_ADDR +\ + IPQ5332_PPE_L0_C_SP_CFG_TBL_ADDR) + +#define IPQ5332_PPE_L1_C_SP_CFG_TBL_ADDR 0x42000 +#define IPQ5332_PPE_L1_C_SP_CFG_TBL (IPQ5332_PPE_TRAFFIC_MANAGER_BASE_ADDR +\ + IPQ5332_PPE_L1_C_SP_CFG_TBL_ADDR) + +#define IPQ5332_PPE_L0_E_SP_CFG_TBL_ADDR 0x6000 +#define IPQ5332_PPE_L0_E_SP_CFG_TBL (IPQ5332_PPE_TRAFFIC_MANAGER_BASE_ADDR +\ + IPQ5332_PPE_L0_E_SP_CFG_TBL_ADDR) + +#define IPQ5332_PPE_L1_E_SP_CFG_TBL_ADDR 0x44000 +#define IPQ5332_PPE_L1_E_SP_CFG_TBL (IPQ5332_PPE_TRAFFIC_MANAGER_BASE_ADDR +\ + IPQ5332_PPE_L1_E_SP_CFG_TBL_ADDR) + +#define IPQ5332_PPE_FPGA_GPIO_BASE_ADDR 0x01008000 + +#define IPQ5332_PPE_MAC_PORT_MUX_OFFSET 0x10 +#define IPQ5332_PPE_FPGA_GPIO_OFFSET 0xc000 +#define IPQ5332_PPE_FPGA_SCHED_OFFSET 0x47a000 +#define IPQ5332_PPE_TDM_CFG_DEPTH_OFFSET 0xb000 +#define IPQ5332_PPE_TDM_SCHED_DEPTH_OFFSET 0x400000 +#define IPQ5332_PPE_PORT_BRIDGE_CTRL_OFFSET 0x060300 + +#define IPQ5332_PPE_TDM_CFG_DEPTH_VAL 0x80000064 +#define IPQ5332_PPE_MAC_PORT_MUX_OFFSET_VAL 0x15 +#define IPQ5332_PPE_TDM_SCHED_DEPTH_VAL 0x32 +#define IPQ5332_PPE_TDM_CFG_VALID 0x20 +#define IPQ5332_PPE_TDM_CFG_DIR_INGRESS 0x0 +#define IPQ5332_PPE_TDM_CFG_DIR_EGRESS 0x10 +#define IPQ5332_PPE_PORT_EDMA 0x0 +#define IPQ5332_PPE_PORT_QTI1 0x1 +#define IPQ5332_PPE_PORT_QTI2 0x2 +#define IPQ5332_PPE_PORT_QTI3 0x3 +#define IPQ5332_PPE_PORT_QTI4 0x4 +#define IPQ5332_PPE_PORT_XGMAC1 0x5 +#define IPQ5332_PPE_PORT_XGMAC2 0x6 +#define IPQ5332_PPE_PORT_CRYPTO1 0x7 +#define IPQ5332_PPE_PORT_BRIDGE_CTRL_PROMISC_EN 0x20000 +#define IPQ5332_PPE_PORT_BRIDGE_CTRL_TXMAC_EN 0x10000 +#define IPQ5332_PPE_PORT_BRIDGE_CTRL_PORT_ISOLATION_BMP 0x7f00 +#define IPQ5332_PPE_PORT_BRIDGE_CTRL_STATION_LRN_EN 0x8 +#define IPQ5332_PPE_PORT_BRIDGE_CTRL_NEW_ADDR_LRN_EN 0x1 + +#define IPQ5332_PPE_PORT_EDMA_BITPOS 0x1 +#define IPQ5332_PPE_PORT_QTI1_BITPOS (1 << IPQ5332_PPE_PORT_QTI1) +#define IPQ5332_PPE_PORT_QTI2_BITPOS (1 << IPQ5332_PPE_PORT_QTI2) +#define IPQ5332_PPE_PORT_QTI3_BITPOS (1 << IPQ5332_PPE_PORT_QTI3) +#define IPQ5332_PPE_PORT_QTI4_BITPOS (1 << IPQ5332_PPE_PORT_QTI4) +#define IPQ5332_PPE_PORT_XGMAC1_BITPOS (1 << IPQ5332_PPE_PORT_XGMAC1) +#define IPQ5332_PPE_PORT_XGMAC2_BITPOS (1 << IPQ5332_PPE_PORT_XGMAC2) +#define IPQ5332_PPE_PORT_CRYPTO1_BITPOS (1 << IPQ5332_PPE_PORT_CRYPTO1) + +#define PPE_SWITCH_NSS_SWITCH_XGMAC0 0x500000 +#define NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION 0x4000 +#define USS (1 << 31) +#define SS(i) (i << 29) +#define JD (1 << 16) +#define TE (1 << 0) +#define NSS_SWITCH_XGMAC_MAC_RX_CONFIGURATION 0x4000 +#define MAC_RX_CONFIGURATION_ADDRESS 0x4 +#define RE (1 << 0) +#define ACS (1 << 1) +#define CST (1 << 2) +#define MAC_PACKET_FILTER_INC 0x4000 +#define MAC_PACKET_FILTER_ADDRESS 0x8 + +#define XGMAC_SPEED_SELECT_10000M 0 +#define XGMAC_SPEED_SELECT_5000M 1 +#define XGMAC_SPEED_SELECT_2500M 2 +#define XGMAC_SPEED_SELECT_1000M 3 + +#define IPE_L2_BASE_ADDR 0x060000 +#define PORT_BRIDGE_CTRL_ADDRESS 0x300 +#define PORT_BRIDGE_CTRL_INC 0x4 +#define TX_MAC_EN (1 << 16) + +#define IPO_CSR_BASE_ADDR 0x0b0000 + +#define IPO_RULE_REG_ADDRESS 0x0 +#define IPO_RULE_REG_INC 0x10 + +#define IPO_MASK_REG_ADDRESS 0x2000 +#define IPO_MASK_REG_INC 0x10 + +#define IPO_ACTION_ADDRESS 0x8000 +#define IPO_ACTION_INC 0x20 + +#define NSS_CC_PORT1_RX_CMD_RCGR 0x39B00450 +#define GCC_PORT1_ARES 1 << 2 +#define NSS_CC_PPE_BCR 0x39B003E4 + +#define NSS_CC_UNIPHY_PORT1_RX_CBCR 0x39B004B4 +#define NSS_CC_UNIPHY_PORT1_TX_CBCR 0x39B004B8 diff --git a/sources/uboot-be550/drivers/net/ipq5332/ipq5332_uniphy.c b/sources/uboot-be550/drivers/net/ipq5332/ipq5332_uniphy.c new file mode 100644 index 00000000..89a4b0c5 --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq5332/ipq5332_uniphy.c @@ -0,0 +1,521 @@ +/* + * Copyright (c) 2017-2019, 2021, The Linux Foundation. All rights reserved. + * + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "ipq5332_edma.h" +#include "ipq5332_uniphy.h" +#include "ipq5332_ppe.h" +#include +#include "ipq_phy.h" + + +DECLARE_GLOBAL_DATA_PTR; +extern int ipq_mdio_write(int mii_id, + int regnum, u16 value); +extern int ipq_mdio_read(int mii_id, + int regnum, ushort *data); +extern void ipq5332_qca8075_phy_serdes_reset(u32 phy_id); + +void csr1_write(int phy_id, int addr, int value) +{ + int addr_h, addr_l, ahb_h, ahb_l, phy; + phy=phy_id<<(0x10); + addr_h=(addr&0xffffff)>>8; + addr_l=((addr&0xff)<<2)|(0x20<<(0xa)); + ahb_l=(addr_l&0xffff)|(0x7A00000|phy); + ahb_h=(0x7A083FC|phy); + writel(addr_h,ahb_h); + writel(value,ahb_l); +} + +int csr1_read(int phy_id, int addr ) +{ + int addr_h ,addr_l,ahb_h, ahb_l, phy; + phy=phy_id<<(0x10); + addr_h=(addr&0xffffff)>>8; + addr_l=((addr&0xff)<<2)|(0x20<<(0xa)); + ahb_l=(addr_l&0xffff)|(0x7A00000|phy); + ahb_h=(0x7A083FC|phy); + writel(addr_h, ahb_h); + return readl(ahb_l); +} + +static int ppe_uniphy_calibration(uint32_t uniphy_index) +{ + int retries = 100, calibration_done = 0; + uint32_t reg_value = 0; + + while(calibration_done != UNIPHY_CALIBRATION_DONE) { + mdelay(1); + if (retries-- == 0) { + printf("uniphy callibration time out!\n"); + return -1; + } + reg_value = readl(PPE_UNIPHY_BASE + + (uniphy_index * PPE_UNIPHY_REG_INC) + + PPE_UNIPHY_OFFSET_CALIB_4); + calibration_done = (reg_value >> 0x7) & 0x1; + } + + return 0; +} + +static void ppe_uniphy_reset(enum uniphy_reset_type rst_type, bool enable) +{ + uint32_t reg_val; + + switch(rst_type) { + case UNIPHY0_SOFT_RESET: + reg_val = readl(GCC_UNIPHY0_SYS_CBCR); + if (enable) { + reg_val |= 0x4; + } else { + reg_val &= ~0x4; + } + writel(reg_val, GCC_UNIPHY0_SYS_CBCR); + break; + case UNIPHY0_XPCS_RESET: + reg_val = readl(GCC_UNIPHY0_MISC); + if (enable) + reg_val |= 0x1; + else + reg_val &= ~0x1; + writel(reg_val, GCC_UNIPHY0_MISC); + break; + case UNIPHY1_SOFT_RESET: + reg_val = readl(GCC_UNIPHY1_SYS_CBCR); + if (enable) { + reg_val |= 0x4; + } else { + reg_val &= ~0x4; + } + writel(reg_val, GCC_UNIPHY1_SYS_CBCR); + break; + case UNIPHY1_XPCS_RESET: + reg_val = readl(GCC_UNIPHY0_MISC + GCC_UNIPHY_REG_INC); + if (enable) + reg_val |= 0x1; + else + reg_val &= ~0x1; + writel(reg_val, GCC_UNIPHY0_MISC + GCC_UNIPHY_REG_INC); + break; + default: + break; + } +} + +static void ppe_uniphy_psgmii_mode_set(uint32_t uniphy_index) +{ + if (uniphy_index == 0) + ppe_uniphy_reset(UNIPHY0_XPCS_RESET, true); + else + ppe_uniphy_reset(UNIPHY1_XPCS_RESET, true); + mdelay(100); + + writel(0x220, PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC) + + PPE_UNIPHY_MODE_CONTROL); + + if (uniphy_index == 0) { + ppe_uniphy_reset(UNIPHY0_SOFT_RESET, true); + mdelay(100); + ppe_uniphy_reset(UNIPHY0_SOFT_RESET, false); + } else { + ppe_uniphy_reset(UNIPHY1_SOFT_RESET, true); + mdelay(100); + ppe_uniphy_reset(UNIPHY1_SOFT_RESET, false); + } + mdelay(100); + ppe_uniphy_calibration(uniphy_index); +#ifdef CONFIG_IPQ5332_QCA8075_PHY + ipq5332_qca8075_phy_serdes_reset(0x10); +#endif +} + +static void ppe_uniphy_qsgmii_mode_set(uint32_t uniphy_index) +{ + if (uniphy_index == 0) + ppe_uniphy_reset(UNIPHY0_XPCS_RESET, true); + else + ppe_uniphy_reset(UNIPHY1_XPCS_RESET, true); + mdelay(100); + + writel(0x120, PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC) + + PPE_UNIPHY_MODE_CONTROL); + if (uniphy_index == 0) { + ppe_uniphy_reset(UNIPHY0_SOFT_RESET, true); + mdelay(100); + ppe_uniphy_reset(UNIPHY0_SOFT_RESET, false); + } else { + ppe_uniphy_reset(UNIPHY1_SOFT_RESET, true); + mdelay(100); + ppe_uniphy_reset(UNIPHY1_SOFT_RESET, false); + } + mdelay(100); +} + +void ppe_uniphy_set_forceMode(uint32_t uniphy_index) +{ + uint32_t reg_value; + + reg_value = readl(PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC) + + UNIPHY_DEC_CHANNEL_0_INPUT_OUTPUT_4); + reg_value |= UNIPHY_FORCE_SPEED_25M; + + writel(reg_value, PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC) + + UNIPHY_DEC_CHANNEL_0_INPUT_OUTPUT_4); +} + +void ppe_uniphy_refclk_set_25M(uint32_t uniphy_index) +{ + uint32_t reg_value; + + reg_value = readl(PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC) + + UNIPHY1_CLKOUT_50M_CTRL_OPTION); + reg_value |= (UNIPHY1_CLKOUT_50M_CTRL_CLK50M_DIV2_SEL | + UNIPHY1_CLKOUT_50M_CTRL_50M_25M_EN); + + writel(reg_value, PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC) + + UNIPHY1_CLKOUT_50M_CTRL_OPTION); +} + +static void ppe_uniphy_sgmii_mode_set(uint32_t uniphy_index, uint32_t mode) +{ + uint32_t reg_value; + + writel(UNIPHY_MISC_SRC_PHY_MODE, PPE_UNIPHY_BASE + + (uniphy_index * PPE_UNIPHY_REG_INC) + + UNIPHY_MISC_SOURCE_SELECTION_REG_OFFSET); + + if (mode == EPORT_WRAPPER_SGMII_PLUS) { + writel(UNIPHY_MISC2_REG_SGMII_PLUS_MODE, PPE_UNIPHY_BASE + + (uniphy_index * PPE_UNIPHY_REG_INC) + + UNIPHY_MISC2_REG_OFFSET); + } else { + writel(UNIPHY_MISC2_REG_SGMII_MODE, PPE_UNIPHY_BASE + + (uniphy_index * PPE_UNIPHY_REG_INC) + + UNIPHY_MISC2_REG_OFFSET); + } + + writel(UNIPHY_PLL_RESET_REG_VALUE, PPE_UNIPHY_BASE + + (uniphy_index * PPE_UNIPHY_REG_INC) + + UNIPHY_PLL_RESET_REG_OFFSET); + mdelay(500); + writel(UNIPHY_PLL_RESET_REG_DEFAULT_VALUE, PPE_UNIPHY_BASE + + (uniphy_index * PPE_UNIPHY_REG_INC) + + UNIPHY_PLL_RESET_REG_OFFSET); + mdelay(500); + if (uniphy_index == 0) + ppe_uniphy_reset(UNIPHY0_XPCS_RESET, true); + else + ppe_uniphy_reset(UNIPHY1_XPCS_RESET, true); + mdelay(100); + + writel(0x0, NSS_CC_UNIPHY_PORT1_RX_CBCR + (uniphy_index * 0x8)); + writel(0x0, NSS_CC_UNIPHY_PORT1_RX_CBCR + 0x4 + (uniphy_index * 0x8)); + + mdelay(10); + reg_value = readl(NSS_CC_PORT1_RX_CBCR + (uniphy_index * 0x8)); + reg_value &= ~BIT(0); + mdelay(10); + writel(reg_value, NSS_CC_PORT1_RX_CBCR + (uniphy_index * 0x8)); + + mdelay(10); + reg_value = readl(NSS_CC_PORT1_RX_CBCR + 0x8 + (uniphy_index * 0x8)); + reg_value &= ~BIT(0); + mdelay(10); + writel(reg_value, NSS_CC_PORT1_RX_CBCR + 0x8 + (uniphy_index * 0x8)); + + switch (mode) { + case EPORT_WRAPPER_SGMII_FIBER: + writel(0x400, PPE_UNIPHY_BASE + + (uniphy_index * PPE_UNIPHY_REG_INC) + + PPE_UNIPHY_MODE_CONTROL); + break; + + case EPORT_WRAPPER_SGMII0_RGMII4: + case EPORT_WRAPPER_SGMII1_RGMII4: + case EPORT_WRAPPER_SGMII4_RGMII4: + writel(0x420, PPE_UNIPHY_BASE + + (uniphy_index * PPE_UNIPHY_REG_INC) + + PPE_UNIPHY_MODE_CONTROL); + break; + + case EPORT_WRAPPER_SGMII_PLUS: + writel(0x820, PPE_UNIPHY_BASE + + (uniphy_index * PPE_UNIPHY_REG_INC) + + PPE_UNIPHY_MODE_CONTROL); + break; + + default: + printf("SGMII Config. wrongly"); + break; + } + + if (uniphy_index == 0) { + ppe_uniphy_reset(UNIPHY0_SOFT_RESET, true); + mdelay(100); + ppe_uniphy_reset(UNIPHY0_SOFT_RESET, false); + } else { + ppe_uniphy_reset(UNIPHY1_SOFT_RESET, true); + mdelay(100); + ppe_uniphy_reset(UNIPHY1_SOFT_RESET, false); + } + mdelay(100); + + writel(0x1, NSS_CC_UNIPHY_PORT1_RX_CBCR + (uniphy_index * 0x8)); + mdelay(10); + writel(0x1, NSS_CC_UNIPHY_PORT1_RX_CBCR + 0x4 + (uniphy_index * 0x8)); + + mdelay(10); + reg_value = readl(NSS_CC_PORT1_RX_CBCR + (uniphy_index * 0x8)); + reg_value |= BIT(0); + mdelay(10); + writel(reg_value, NSS_CC_PORT1_RX_CBCR + (uniphy_index * 0x8)); + + mdelay(10); + reg_value = readl(NSS_CC_PORT1_RX_CBCR + 0x8 + (uniphy_index * 0x8)); + reg_value |= BIT(0); + mdelay(10); + writel(reg_value, NSS_CC_PORT1_RX_CBCR + 0x8 + (uniphy_index * 0x8)); + + mdelay(10); + ppe_uniphy_calibration(uniphy_index); +} + +static int ppe_uniphy_10g_r_linkup(uint32_t uniphy_index) +{ + uint32_t reg_value = 0; + uint32_t retries = 100, linkup = 0; + + while (linkup != UNIPHY_10GR_LINKUP) { + mdelay(1); + if (retries-- == 0) + return -1; + reg_value = csr1_read(uniphy_index, SR_XS_PCS_KR_STS1_ADDRESS); + linkup = (reg_value >> 12) & UNIPHY_10GR_LINKUP; + } + mdelay(10); + return 0; +} + +static void ppe_uniphy_10g_r_mode_set(uint32_t uniphy_index) +{ + if (uniphy_index == 0) + ppe_uniphy_reset(UNIPHY0_XPCS_RESET, true); + else + ppe_uniphy_reset(UNIPHY1_XPCS_RESET, true); + + writel(0x1021, PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC) + + PPE_UNIPHY_MODE_CONTROL); + writel(0x1C0, PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC) + + UNIPHY_INSTANCE_LINK_DETECT); + + if (uniphy_index == 0) { + ppe_uniphy_reset(UNIPHY0_SOFT_RESET, true); + mdelay(100); + ppe_uniphy_reset(UNIPHY0_SOFT_RESET, false); + } else { + ppe_uniphy_reset(UNIPHY1_SOFT_RESET, true); + mdelay(100); + ppe_uniphy_reset(UNIPHY1_SOFT_RESET, false); + } + mdelay(100); + + ppe_uniphy_calibration(uniphy_index); + + if (uniphy_index == 0) + ppe_uniphy_reset(UNIPHY0_XPCS_RESET, false); + else + ppe_uniphy_reset(UNIPHY1_XPCS_RESET, false); +} + + +static void ppe_uniphy_usxgmii_mode_set(uint32_t uniphy_index) +{ + uint32_t reg_value = 0; + + writel(UNIPHY_MISC2_REG_VALUE, PPE_UNIPHY_BASE + + (uniphy_index * PPE_UNIPHY_REG_INC) + UNIPHY_MISC2_REG_OFFSET); + writel(UNIPHY_PLL_RESET_REG_VALUE, PPE_UNIPHY_BASE + + (uniphy_index * PPE_UNIPHY_REG_INC) + + UNIPHY_PLL_RESET_REG_OFFSET); + mdelay(500); + writel(UNIPHY_PLL_RESET_REG_DEFAULT_VALUE, PPE_UNIPHY_BASE + + (uniphy_index * PPE_UNIPHY_REG_INC) + + UNIPHY_PLL_RESET_REG_OFFSET); + mdelay(500); + + if (uniphy_index == 0) + ppe_uniphy_reset(UNIPHY0_XPCS_RESET, true); + else + ppe_uniphy_reset(UNIPHY1_XPCS_RESET, true); + mdelay(100); + + writel(0x1021, PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC) + + PPE_UNIPHY_MODE_CONTROL); + + if (uniphy_index == 0) { + ppe_uniphy_reset(UNIPHY0_SOFT_RESET, true); + mdelay(100); + ppe_uniphy_reset(UNIPHY0_SOFT_RESET, false); + } else { + ppe_uniphy_reset(UNIPHY1_SOFT_RESET, true); + mdelay(100); + ppe_uniphy_reset(UNIPHY1_SOFT_RESET, false); + } + mdelay(100); + + ppe_uniphy_calibration(uniphy_index); + + if (uniphy_index == 0) + ppe_uniphy_reset(UNIPHY0_XPCS_RESET, false); + else + ppe_uniphy_reset(UNIPHY1_XPCS_RESET, false); + mdelay(100); + + ppe_uniphy_10g_r_linkup(uniphy_index); + reg_value = csr1_read(uniphy_index, VR_XS_PCS_DIG_CTRL1_ADDRESS); + reg_value |= USXG_EN; + csr1_write(uniphy_index, VR_XS_PCS_DIG_CTRL1_ADDRESS, reg_value); + reg_value = csr1_read(uniphy_index, VR_MII_AN_CTRL_ADDRESS); + reg_value |= MII_AN_INTR_EN; + reg_value |= MII_CTRL; + csr1_write(uniphy_index, VR_MII_AN_CTRL_ADDRESS, reg_value); + reg_value = csr1_read(uniphy_index, SR_MII_CTRL_ADDRESS); + reg_value |= AN_ENABLE; + reg_value &= ~SS5; + reg_value |= SS6 | SS13 | DUPLEX_MODE; + csr1_write(uniphy_index, SR_MII_CTRL_ADDRESS, reg_value); +} + +void ppe_uniphy_mode_set(uint32_t uniphy_index, uint32_t mode) +{ + switch(mode) { + case EPORT_WRAPPER_PSGMII: + ppe_uniphy_psgmii_mode_set(uniphy_index); + break; + case EPORT_WRAPPER_QSGMII: + ppe_uniphy_qsgmii_mode_set(uniphy_index); + break; + case EPORT_WRAPPER_SGMII0_RGMII4: + case EPORT_WRAPPER_SGMII1_RGMII4: + case EPORT_WRAPPER_SGMII4_RGMII4: + case EPORT_WRAPPER_SGMII_PLUS: + case EPORT_WRAPPER_SGMII_FIBER: + ppe_uniphy_sgmii_mode_set(uniphy_index, mode); + break; + case EPORT_WRAPPER_USXGMII: + ppe_uniphy_usxgmii_mode_set(uniphy_index); + break; + case EPORT_WRAPPER_10GBASE_R: + ppe_uniphy_10g_r_mode_set(uniphy_index); + break; + default: + break; + } +} + +void ppe_uniphy_usxgmii_autoneg_completed(uint32_t uniphy_index) +{ + uint32_t autoneg_complete = 0, retries = 100; + uint32_t reg_value = 0; + + while (autoneg_complete != 0x1) { + mdelay(1); + if (retries-- == 0) + { + return; + } + reg_value = csr1_read(uniphy_index, VR_MII_AN_INTR_STS); + autoneg_complete = reg_value & 0x1; + } + reg_value &= ~CL37_ANCMPLT_INTR; + csr1_write(uniphy_index, VR_MII_AN_INTR_STS, reg_value); +} + +void ppe_uniphy_usxgmii_speed_set(uint32_t uniphy_index, int speed) +{ + uint32_t reg_value = 0; + + reg_value = csr1_read(uniphy_index, SR_MII_CTRL_ADDRESS); + reg_value |= DUPLEX_MODE; + + switch(speed) { + case 0: + reg_value &=~SS5; + reg_value &=~SS6; + reg_value &=~SS13; + break; + case 1: + reg_value &=~SS5; + reg_value &=~SS6; + reg_value |=SS13; + break; + case 2: + reg_value &=~SS5; + reg_value |=SS6; + reg_value &=~SS13; + break; + case 3: + reg_value &=~SS5; + reg_value |=SS6; + reg_value |=SS13; + break; + case 4: + reg_value |=SS5; + reg_value &=~SS6; + reg_value &=~SS13; + break; + case 5: + reg_value |=SS5; + reg_value &=~SS6; + reg_value |=SS13; + break; + } + csr1_write(uniphy_index, SR_MII_CTRL_ADDRESS, reg_value); + +} + +void ppe_uniphy_usxgmii_duplex_set(uint32_t uniphy_index, int duplex) +{ + uint32_t reg_value = 0; + + reg_value = csr1_read(uniphy_index, SR_MII_CTRL_ADDRESS); + + if (duplex & 0x1) + reg_value |= DUPLEX_MODE; + else + reg_value &= ~DUPLEX_MODE; + + csr1_write(uniphy_index, SR_MII_CTRL_ADDRESS, reg_value); +} + +void ppe_uniphy_usxgmii_port_reset(uint32_t uniphy_index) +{ + uint32_t reg_value = 0; + + reg_value = csr1_read(uniphy_index, VR_XS_PCS_DIG_CTRL1_ADDRESS); + reg_value |= USRA_RST; + csr1_write(uniphy_index, VR_XS_PCS_DIG_CTRL1_ADDRESS, reg_value); +} diff --git a/sources/uboot-be550/drivers/net/ipq5332/ipq5332_uniphy.h b/sources/uboot-be550/drivers/net/ipq5332/ipq5332_uniphy.h new file mode 100644 index 00000000..b6303d27 --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq5332/ipq5332_uniphy.h @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2017-2019, 2021, The Linux Foundation. All rights reserved. + * + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#define PPE_UNIPHY_INSTANCE0 0 +#define PPE_UNIPHY_INSTANCE1 1 + +#define GCC_UNIPHY_REG_INC 0x10 + +#define PPE_UNIPHY_OFFSET_CALIB_4 0x1E0 +#define UNIPHY_CALIBRATION_DONE 0x1 + +#define PPE_UNIPHY_BASE 0X07A00000 +#define PPE_UNIPHY_REG_INC 0x10000 +#define PPE_UNIPHY_MODE_CONTROL 0x46C +#define UNIPHY_XPCS_MODE (1 << 12) +#define UNIPHY_SG_PLUS_MODE (1 << 11) +#define UNIPHY_SG_MODE (1 << 10) +#define UNIPHY_CH0_PSGMII_QSGMII (1 << 9) +#define UNIPHY_CH0_QSGMII_SGMII (1 << 8) +#define UNIPHY_CH4_CH1_0_SGMII (1 << 2) +#define UNIPHY_CH1_CH0_SGMII (1 << 1) +#define UNIPHY_CH0_ATHR_CSCO_MODE_25M (1 << 0) + +#define UNIPHY_INSTANCE_LINK_DETECT 0x570 + +#define UNIPHY_MISC2_REG_OFFSET 0x218 +#define UNIPHY_MISC2_REG_SGMII_MODE 0x30 +#define UNIPHY_MISC2_REG_SGMII_PLUS_MODE 0x50 + +#define UNIPHY_MISC2_REG_VALUE 0x70 + +#define UNIPHY_MISC_SOURCE_SELECTION_REG_OFFSET 0x21c +#define UNIPHY_MISC_SRC_PHY_MODE 0xa882 + +#define UNIPHY_DEC_CHANNEL_0_INPUT_OUTPUT_4 0x480 +#define UNIPHY_FORCE_SPEED_25M (1 << 3) + +#ifdef CONFIG_TP_EXT_SWITCH +#define UNIPHY_ADP_SW_RESET (1 << 11) +#endif + +#define UNIPHY1_CLKOUT_50M_CTRL_OPTION 0x610 +#define UNIPHY1_CLKOUT_50M_CTRL_CLK50M_DIV2_SEL (1 << 5) +#define UNIPHY1_CLKOUT_50M_CTRL_50M_25M_EN 0x1 + +#define UNIPHY_PLL_RESET_REG_OFFSET 0x780 +#define UNIPHY_PLL_RESET_REG_VALUE 0x02bf +#define UNIPHY_PLL_RESET_REG_DEFAULT_VALUE 0x02ff + +#define SR_XS_PCS_KR_STS1_ADDRESS 0x30020 +#define UNIPHY_10GR_LINKUP 0x1 + +#define VR_XS_PCS_DIG_CTRL1_ADDRESS 0x38000 +#define USXG_EN (1 << 9) +#define USRA_RST (1 << 10) + +#define VR_MII_AN_CTRL_ADDRESS 0x1f8001 +#define MII_AN_INTR_EN (1 << 0) +#define MII_CTRL (1 << 8) + +#define SR_MII_CTRL_ADDRESS 0x1f0000 +#define AN_ENABLE (1 << 12) +#define SS5 (1 << 5) +#define SS6 (1 << 6) +#define SS13 (1 << 13) +#define DUPLEX_MODE (1 << 8) + +#define VR_MII_AN_INTR_STS 0x1f8002 +#define CL37_ANCMPLT_INTR (1 << 0) + +#define GCC_UNIPHY0_MISC 0x1816050 + +enum uniphy_reset_type { + UNIPHY0_SOFT_RESET = 0, + UNIPHY0_XPCS_RESET, + UNIPHY1_SOFT_RESET, + UNIPHY1_XPCS_RESET, + UNIPHY2_SOFT_RESET, + UNIPHY2_XPCS_RESET, + UNIPHY_RST_MAX +}; + +void ppe_uniphy_mode_set(uint32_t uniphy_index, uint32_t mode); +void ppe_uniphy_usxgmii_port_reset(uint32_t uniphy_index); +void ppe_uniphy_usxgmii_duplex_set(uint32_t uniphy_index, int duplex); +void ppe_uniphy_usxgmii_speed_set(uint32_t uniphy_index, int speed); +void ppe_uniphy_usxgmii_autoneg_completed(uint32_t uniphy_index); diff --git a/sources/uboot-be550/drivers/net/ipq6018/ipq6018_aquantia_phy.c b/sources/uboot-be550/drivers/net/ipq6018/ipq6018_aquantia_phy.c new file mode 100644 index 00000000..e46970f9 --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq6018/ipq6018_aquantia_phy.c @@ -0,0 +1,597 @@ +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include "ipq_phy.h" +#include "ipq6018_aquantia_phy.h" +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; +typedef struct { + unsigned int image_type; + unsigned int header_vsn_num; + unsigned int image_src; + unsigned char *image_dest_ptr; + unsigned int image_size; + unsigned int code_size; + unsigned char *signature_ptr; + unsigned int signature_size; + unsigned char *cert_chain_ptr; + unsigned int cert_chain_size; +} mbn_header_t; + +mbn_header_t *fwimg_header; +static int debug = 0; + +#ifdef CONFIG_QCA_MMC +extern qca_mmc mmc_host; +static qca_mmc *host = &mmc_host; +#endif + +extern int ipq_mdio_write(int mii_id, + int regnum, u16 value); +extern int ipq_mdio_read(int mii_id, + int regnum, ushort *data); + +extern int ipq_sw_mdio_init(const char *); +extern void eth_clock_enable(void); +static int program_ethphy_fw(unsigned int phy_addr, + uint32_t load_addr,uint32_t file_size ); +static qca_smem_flash_info_t *sfi = &qca_smem_flash_info; + +u16 aq_phy_reg_write(u32 dev_id, u32 phy_id, + u32 reg_id, u16 reg_val) +{ + ipq_mdio_write(phy_id, reg_id, reg_val); + return 0; +} + +u16 aq_phy_reg_read(u32 dev_id, u32 phy_id, u32 reg_id) +{ + return ipq_mdio_read(phy_id, reg_id, NULL); +} + +u8 aq_phy_get_link_status(u32 dev_id, u32 phy_id) +{ + u16 phy_data; + uint32_t reg; + + reg = AQ_PHY_AUTO_STATUS_REG | AQUANTIA_MII_ADDR_C45; + phy_data = aq_phy_reg_read(dev_id, phy_id, reg); + phy_data = aq_phy_reg_read(dev_id, phy_id, reg); + + if (((phy_data >> 2) & 0x1) & PORT_LINK_UP) + return 0; + + return 1; +} + +u32 aq_phy_get_duplex(u32 dev_id, u32 phy_id, fal_port_duplex_t *duplex) +{ + u16 phy_data; + uint32_t reg; + + reg = AQ_PHY_LINK_STATUS_REG | AQUANTIA_MII_ADDR_C45; + phy_data = aq_phy_reg_read(dev_id, phy_id, reg); + + /* + * Read duplex + */ + phy_data = phy_data & 0x1; + if (phy_data & 0x1) + *duplex = FAL_FULL_DUPLEX; + else + *duplex = FAL_HALF_DUPLEX; + + return 0; +} + +u32 aq_phy_get_speed(u32 dev_id, u32 phy_id, fal_port_speed_t *speed) +{ + u16 phy_data; + uint32_t reg; + + reg = AQ_PHY_LINK_STATUS_REG | AQUANTIA_MII_ADDR_C45; + phy_data = aq_phy_reg_read(dev_id, phy_id, reg); + + switch ((phy_data >> 1) & 0x7) { + case SPEED_10G: + *speed = FAL_SPEED_10000; + break; + case SPEED_5G: + *speed = FAL_SPEED_5000; + break; + case SPEED_2_5G: + *speed = FAL_SPEED_2500; + break; + case SPEED_1000MBS: + *speed = FAL_SPEED_1000; + break; + case SPEED_100MBS: + *speed = FAL_SPEED_100; + break; + case SPEED_10MBS: + *speed = FAL_SPEED_10; + break; + default: + return -EINVAL; + } + return 0; +} + +void aquantia_phy_restart_autoneg(u32 phy_id) +{ + u16 phy_data; + + phy_data = aq_phy_reg_read(0x0, phy_id, AQUANTIA_REG_ADDRESS(AQUANTIA_MMD_PHY_XS_REGISTERS, + AQUANTIA_PHY_XS_USX_TRANSMIT)); + if (!(phy_data & AQUANTIA_PHY_USX_AUTONEG_ENABLE)) + aq_phy_reg_write(0x0, phy_id,AQUANTIA_REG_ADDRESS( + AQUANTIA_MMD_PHY_XS_REGISTERS, + AQUANTIA_PHY_XS_USX_TRANSMIT), + phy_data | AQUANTIA_PHY_USX_AUTONEG_ENABLE); + + phy_data = aq_phy_reg_read(0x0, phy_id, AQUANTIA_REG_ADDRESS(AQUANTIA_MMD_AUTONEG, + AQUANTIA_AUTONEG_STANDARD_CONTROL1)); + + phy_data |= AQUANTIA_CTRL_AUTONEGOTIATION_ENABLE; + aq_phy_reg_write(0x0, phy_id, AQUANTIA_REG_ADDRESS(AQUANTIA_MMD_AUTONEG, + AQUANTIA_AUTONEG_STANDARD_CONTROL1), + phy_data | AQUANTIA_CTRL_RESTART_AUTONEGOTIATION); +} + +int ipq_qca_aquantia_phy_init(struct phy_ops **ops, u32 phy_id) +{ + u16 phy_data; + struct phy_ops *aq_phy_ops; + aq_phy_ops = (struct phy_ops *)malloc(sizeof(struct phy_ops)); + if (!aq_phy_ops) + return -ENOMEM; + aq_phy_ops->phy_get_link_status = aq_phy_get_link_status; + aq_phy_ops->phy_get_speed = aq_phy_get_speed; + aq_phy_ops->phy_get_duplex = aq_phy_get_duplex; + *ops = aq_phy_ops; + + phy_data = aq_phy_reg_read(0x0, phy_id, AQUANTIA_REG_ADDRESS(1, QCA_PHY_ID1)); + printf ("PHY ID1: 0x%x\n", phy_data); + phy_data = aq_phy_reg_read(0x0, phy_id, AQUANTIA_REG_ADDRESS(1, QCA_PHY_ID2)); + printf ("PHY ID2: 0x%x\n", phy_data); + phy_data = aq_phy_reg_read(0x0, phy_id, AQUANTIA_REG_ADDRESS(AQUANTIA_MMD_PHY_XS_REGISTERS, + AQUANTIA_PHY_XS_USX_TRANSMIT)); + phy_data |= AQUANTIA_PHY_USX_AUTONEG_ENABLE; + aq_phy_reg_write(0x0, phy_id, AQUANTIA_REG_ADDRESS(AQUANTIA_MMD_PHY_XS_REGISTERS, + AQUANTIA_PHY_XS_USX_TRANSMIT), phy_data); + phy_data = aq_phy_reg_read(0x0, phy_id, AQUANTIA_REG_ADDRESS(AQUANTIA_MMD_AUTONEG, + AQUANTIA_AUTONEG_TRANSMIT_VENDOR_INTR_MASK)); + phy_data |= AQUANTIA_INTR_LINK_STATUS_CHANGE; + aq_phy_reg_write(0x0, phy_id, AQUANTIA_REG_ADDRESS(AQUANTIA_MMD_AUTONEG, + AQUANTIA_AUTONEG_TRANSMIT_VENDOR_INTR_MASK), phy_data); + phy_data = aq_phy_reg_read(0x0, phy_id, AQUANTIA_REG_ADDRESS(AQUANTIA_MMD_GLOABLE_REGISTERS, + AQUANTIA_GLOBAL_INTR_STANDARD_MASK)); + phy_data |= AQUANTIA_ALL_VENDOR_ALARMS_INTERRUPT_MASK; + aq_phy_reg_write(0x0, phy_id, AQUANTIA_REG_ADDRESS(AQUANTIA_MMD_GLOABLE_REGISTERS, + AQUANTIA_GLOBAL_INTR_STANDARD_MASK), phy_data); + phy_data = aq_phy_reg_read(0x0, phy_id, AQUANTIA_REG_ADDRESS(AQUANTIA_MMD_GLOABLE_REGISTERS, + AQUANTIA_GLOBAL_INTR_VENDOR_MASK)); + phy_data |= AQUANTIA_AUTO_AND_ALARMS_INTR_MASK; + aq_phy_reg_write(0x0, phy_id, AQUANTIA_REG_ADDRESS(AQUANTIA_MMD_GLOABLE_REGISTERS, + AQUANTIA_GLOBAL_INTR_VENDOR_MASK), phy_data); + return 0; +} + +static int do_aq_phy_restart(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + unsigned int phy_addr = AQU_PHY_ADDR; + if (argc > 2) + return CMD_RET_USAGE; + + if (argc == 2) + phy_addr = simple_strtoul(argv[1], NULL, 16); + + aquantia_phy_restart_autoneg(phy_addr); + return 0; +} + +int ipq_board_fw_download(unsigned int phy_addr) +{ + char runcmd[256]; + int ret,i=0; + uint32_t start; /* block number */ + uint32_t size; /* no. of blocks */ + qca_part_entry_t ethphyfw; + unsigned int *ethphyfw_load_addr = NULL; + struct { char *name; qca_part_entry_t *part; } entries[] = { + { "0:ETHPHYFW", ðphyfw }, + }; +#ifdef CONFIG_QCA_MMC + block_dev_desc_t *blk_dev; + disk_partition_t disk_info; +#endif + /* check the smem info to see which flash used for booting */ + if (sfi->flash_type == SMEM_BOOT_SPI_FLASH) { + if (debug) { + printf("Using nor device \n"); + } + } else if (sfi->flash_type == SMEM_BOOT_NAND_FLASH) { + if (debug) { + printf("Using nand device 0\n"); + } + } else if (sfi->flash_type == SMEM_BOOT_MMC_FLASH) { + if (debug) { + printf("Using MMC device\n"); + } + } else { + printf("Unsupported BOOT flash type\n"); + return -1; + } + + ret = smem_getpart(entries[i].name, &start, &size); + if (ret < 0) { + debug("cdp: get part failed for %s\n", entries[i].name); + } else { + qca_set_part_entry(entries[i].name, sfi, entries[i].part, start, size); + } + + if ((sfi->flash_type == SMEM_BOOT_NAND_FLASH) || + (sfi->flash_type == SMEM_BOOT_SPI_FLASH)) { + ethphyfw_load_addr = (uint *)malloc(ethphyfw.size); + if (ethphyfw_load_addr == NULL) { + printf("ETHPHYFW Loading failed\n"); + return -1; + } else { + memset(ethphyfw_load_addr, 0, ethphyfw.size); + } + } + + if (sfi->flash_type == SMEM_BOOT_NAND_FLASH) { + /* + * Kernel is in a separate partition + */ + snprintf(runcmd, sizeof(runcmd), + /* NOR is treated as psuedo NAND */ + "nand read 0x%p 0x%llx 0x%llx && ", + ethphyfw_load_addr, ethphyfw.offset, ethphyfw.size); + + if (debug) + printf("%s", runcmd); + + if (run_command(runcmd, 0) != CMD_RET_SUCCESS) { + free(ethphyfw_load_addr); + return CMD_RET_FAILURE; + } + } else if (sfi->flash_type == SMEM_BOOT_SPI_FLASH) { + snprintf(runcmd, sizeof(runcmd), + "sf probe && " "sf read 0x%p 0x%llx 0x%llx && ", + ethphyfw_load_addr, ethphyfw.offset, ethphyfw.size); + + if (debug) + printf("%s", runcmd); + + if (run_command(runcmd, 0) != CMD_RET_SUCCESS) { + free(ethphyfw_load_addr); + return CMD_RET_FAILURE; + } +#ifdef CONFIG_QCA_MMC + } else if (sfi->flash_type == SMEM_BOOT_MMC_FLASH ) { + blk_dev = mmc_get_dev(host->dev_num); + ret = get_partition_info_efi_by_name(blk_dev, + "0:ETHPHYFW", &disk_info); + + ethphyfw_load_addr = (uint *)malloc(((uint)disk_info.size) * + ((uint)disk_info.blksz)); + if (ethphyfw_load_addr == NULL) { + printf("ETHPHYFW Loading failed\n"); + return -1; + } else { + memset(ethphyfw_load_addr, 0, + (((uint)disk_info.size) * + ((uint)disk_info.blksz))); + } + + if (ret == 0) { + snprintf(runcmd, sizeof(runcmd), + "mmc read 0x%p 0x%X 0x%X", + ethphyfw_load_addr, + (uint)disk_info.start, (uint)disk_info.size); + + if (run_command(runcmd, 0) != CMD_RET_SUCCESS) { + free(ethphyfw_load_addr); + return CMD_RET_FAILURE; + } + } +#endif + } + + fwimg_header = (mbn_header_t *)(ethphyfw_load_addr); + + if (fwimg_header->image_type == 0x13 && + fwimg_header->header_vsn_num == 0x3) { + program_ethphy_fw(phy_addr, + (uint32_t)(((uint32_t)ethphyfw_load_addr) + + sizeof(mbn_header_t)), + (uint32_t)(fwimg_header->image_size)); + } else { + printf("bad magic on ETHPHYFW partition\n"); + free(ethphyfw_load_addr); + return -1; + } + free(ethphyfw_load_addr); + return 0; +} + + +#define AQ_PHY_IMAGE_HEADER_CONTENT_OFFSET_HHD 0x300 +static int program_ethphy_fw(unsigned int phy_addr, uint32_t load_addr, uint32_t file_size) +{ + int i; + uint8_t *buf; + uint16_t file_crc; + uint16_t computed_crc; + uint32_t reg1, reg2; + uint16_t recorded_ggp8_val; + uint16_t daisy_chain_dis; + uint32_t primary_header_ptr = 0x00000000; + uint32_t primary_iram_ptr = 0x00000000; + uint32_t primary_dram_ptr = 0x00000000; + uint32_t primary_iram_sz = 0x00000000; + uint32_t primary_dram_sz = 0x00000000; + uint32_t phy_img_hdr_off; + uint32_t byte_sz; + uint32_t dword_sz; + uint32_t byte_ptr; + uint16_t msw = 0; + uint16_t lsw = 0; + uint8_t msb1; + uint8_t msb2; + uint8_t lsb1; + uint8_t lsb2; + uint16_t mailbox_crc; + + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x300), 0xdead); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x301), 0xbeaf); + reg1 = aq_phy_reg_read(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x300)); + reg2 = aq_phy_reg_read(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x301)); + + if(reg1 != 0xdead && reg2 != 0xbeaf) { + printf("PHY::Scratchpad Read/Write test fail\n"); + return 0; + } + buf = (uint8_t *)load_addr; + file_crc = buf[file_size - 2] << 8 | buf[file_size - 1]; + computed_crc = cyg_crc16(buf, file_size - 2); + + if (file_crc != computed_crc) { + printf("CRC check failed on phy fw file\n"); + return 0; + } else { + printf ("CRC check good on phy fw file (0x%04X)\n",computed_crc); + } + + daisy_chain_dis = aq_phy_reg_read(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0xc452)); + if (!(daisy_chain_dis & 0x1)) + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0xc452), 0x1); + + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0xc471), 0x40); + recorded_ggp8_val = aq_phy_reg_read(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0xc447)); + if ((recorded_ggp8_val & 0x1f) != phy_addr) + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0xc447), phy_addr); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0xc441), 0x4000); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0xc001), 0x41); + primary_header_ptr = (((buf[0x9] & 0x0F) << 8) | buf[0x8]) << 12; + phy_img_hdr_off = AQ_PHY_IMAGE_HEADER_CONTENT_OFFSET_HHD; + primary_iram_ptr = (buf[primary_header_ptr + phy_img_hdr_off + 0x4 + 2] << 16) | + (buf[primary_header_ptr + phy_img_hdr_off + 0x4 + 1] << 8) | + buf[primary_header_ptr + phy_img_hdr_off + 0x4]; + primary_iram_sz = (buf[primary_header_ptr + phy_img_hdr_off + 0x7 + 2] << 16) | + (buf[primary_header_ptr + phy_img_hdr_off + 0x7 + 1] << 8) | + buf[primary_header_ptr + phy_img_hdr_off + 0x7]; + primary_dram_ptr = (buf[primary_header_ptr + phy_img_hdr_off + 0xA + 2] << 16) | + (buf[primary_header_ptr + phy_img_hdr_off + 0xA + 1] << 8) | + buf[primary_header_ptr + phy_img_hdr_off + 0xA]; + primary_dram_sz = (buf[primary_header_ptr + phy_img_hdr_off + 0xD + 2] << 16) | + (buf[primary_header_ptr + phy_img_hdr_off + 0xD + 1] << 8) | + buf[primary_header_ptr + phy_img_hdr_off + 0xD]; + primary_iram_ptr += primary_header_ptr; + primary_dram_ptr += primary_header_ptr; + + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x200), 0x1000); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x200), 0x0); + computed_crc = 0; + printf("PHYFW:Loading IRAM..........."); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x202), 0x4000); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x203), 0x0); + byte_sz = primary_iram_sz; + dword_sz = byte_sz >> 2; + byte_ptr = primary_iram_ptr; + for (i = 0; i < dword_sz; i++) { + lsw = (buf[byte_ptr + 1] << 8) | buf[byte_ptr]; + byte_ptr += 2; + msw = (buf[byte_ptr + 1] << 8) | buf[byte_ptr]; + byte_ptr += 2; + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x204), msw); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x205), lsw); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x200), 0xc000); + msb1 = msw >> 8; + msb2 = msw & 0xFF; + lsb1 = lsw >> 8; + lsb2 = lsw & 0xFF; + computed_crc = cyg_crc16_computed(&msb1, 0x1, computed_crc); + computed_crc = cyg_crc16_computed(&msb2, 0x1, computed_crc); + computed_crc = cyg_crc16_computed(&lsb1, 0x1, computed_crc); + computed_crc = cyg_crc16_computed(&lsb2, 0x1, computed_crc); + } + + switch (byte_sz & 0x3) { + case 0x1: + lsw = buf[byte_ptr++]; + msw = 0x0000; + break; + case 0x2: + lsw = (buf[byte_ptr + 1] << 8) | buf[byte_ptr]; + byte_ptr += 2; + msw = 0x0000; + break; + case 0x3: + lsw = (buf[byte_ptr + 1] << 8) | buf[byte_ptr]; + byte_ptr += 2; + msw = buf[byte_ptr++]; + break; + } + + if (byte_sz & 0x3) { + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x204), msw); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x205), lsw); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x200), 0xc000); + msb1 = msw >> 8; + msb2 = msw & 0xFF; + lsb1 = lsw >> 8; + lsb2 = lsw & 0xFF; + computed_crc = cyg_crc16_computed(&msb1, 0x1, computed_crc); + computed_crc = cyg_crc16_computed(&msb2, 0x1, computed_crc); + computed_crc = cyg_crc16_computed(&lsb1, 0x1, computed_crc); + computed_crc = cyg_crc16_computed(&lsb2, 0x1, computed_crc); + } + printf("done.\n"); + printf("PHYFW:Loading DRAM.............."); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x202), 0x3ffe); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x203), 0x0); + byte_sz = primary_dram_sz; + dword_sz = byte_sz >> 2; + byte_ptr = primary_dram_ptr; + for (i = 0; i < dword_sz; i++) { + lsw = (buf[byte_ptr + 1] << 8) | buf[byte_ptr]; + byte_ptr += 2; + msw = (buf[byte_ptr + 1] << 8) | buf[byte_ptr]; + byte_ptr += 2; + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x204), msw); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x205), lsw); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x200), 0xc000); + msb1 = msw >> 8; + msb2 = msw & 0xFF; + lsb1 = lsw >> 8; + lsb2 = lsw & 0xFF; + computed_crc = cyg_crc16_computed(&msb1, 0x1, computed_crc); + computed_crc = cyg_crc16_computed(&msb2, 0x1, computed_crc); + computed_crc = cyg_crc16_computed(&lsb1, 0x1, computed_crc); + computed_crc = cyg_crc16_computed(&lsb2, 0x1, computed_crc); + } + + switch (byte_sz & 0x3) { + case 0x1: + lsw = buf[byte_ptr++]; + msw = 0x0000; + break; + case 0x2: + lsw = (buf[byte_ptr + 1] << 8) | buf[byte_ptr]; + byte_ptr += 2; + msw = 0x0000; + break; + case 0x3: + lsw = (buf[byte_ptr + 1] << 8) | buf[byte_ptr]; + byte_ptr += 2; + msw = buf[byte_ptr++]; + break; + } + + if (byte_sz & 0x3) { + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x204), msw); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x205), lsw); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x200), 0xc000); + msb1 = msw >> 8; + msb2 = msw & 0xFF; + lsb1 = lsw >> 8; + lsb2 = lsw & 0xFF; + computed_crc = cyg_crc16_computed(&msb1, 0x1, computed_crc); + computed_crc = cyg_crc16_computed(&msb2, 0x1, computed_crc); + computed_crc = cyg_crc16_computed(&lsb1, 0x1, computed_crc); + computed_crc = cyg_crc16_computed(&lsb2, 0x1, computed_crc); + } + printf("done.\n"); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0xc441), 0x2010); + mailbox_crc = aq_phy_reg_read(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x201)); + if (mailbox_crc != computed_crc) { + printf("phy fw image load CRC-16 (0x%X) does not match calculated CRC-16 (0x%X)\n", mailbox_crc, computed_crc); + return 0; + } else + printf("phy fw image load good CRC-16 matches (0x%X)\n", mailbox_crc); + + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x0), 0x0); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0xc001), 0x41); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0xc001), 0x8041); + mdelay(100); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0xc001), 0x40); + mdelay(100); + aquantia_phy_restart_autoneg(phy_addr); + return 0; +} + +static int do_load_fw(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + unsigned int phy_addr = AQU_PHY_ADDR; + int node, aquantia_port; + + if (argc > 2) + return CMD_RET_USAGE; + + if (argc == 2) + phy_addr = simple_strtoul(argv[1], NULL, 16); + + node = fdt_path_offset(gd->fdt_blob, "/ess-switch"); + if (node < 0) { + printf("Error: ess-switch not specified in dts"); + return 0; + } + + aquantia_port = fdtdec_get_uint(gd->fdt_blob, node, "aquantia_port", -1); + if (aquantia_port < 0) { + printf("Error: aquantia_port not specified in dts"); + return 0; + } + + aquantia_port = fdtdec_get_uint(gd->fdt_blob, node, "aquantia_gpio", -1); + if (aquantia_port < 0) { + printf("Error: aquantia_gpio not specified in dts"); + return 0; + } + + miiphy_init(); + eth_clock_enable(); + ipq_sw_mdio_init("IPQ MDIO0"); + ipq_board_fw_download(phy_addr); + return 0; +} + +U_BOOT_CMD( + aq_load_fw, 5, 1, do_load_fw, + "LOAD aq-fw-binary", + "" +); + +U_BOOT_CMD( + aq_phy_restart, 5, 1, do_aq_phy_restart, + "Restart Aquantia phy", + "" +); diff --git a/sources/uboot-be550/drivers/net/ipq6018/ipq6018_aquantia_phy.h b/sources/uboot-be550/drivers/net/ipq6018/ipq6018_aquantia_phy.h new file mode 100644 index 00000000..75560bc8 --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq6018/ipq6018_aquantia_phy.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#define AQUANTIA_MII_ADDR_C45 (1<<30) +#define AQUANTIA_REG_ADDRESS(dev_ad, reg_num) (AQUANTIA_MII_ADDR_C45 |\ + ((dev_ad & 0x1f) << 16) | (reg_num & 0xFFFF)) + +#define AQUANTIA_MMD_PHY_XS_REGISTERS 4 +#define AQUANTIA_PHY_XS_USX_TRANSMIT 0xc441 +#define AQUANTIA_PHY_USX_AUTONEG_ENABLE 0x8 + +#define AQUANTIA_MMD_AUTONEG 0x7 +#define AQUANTIA_AUTONEG_TRANSMIT_VENDOR_INTR_MASK 0xD401 +#define AQUANTIA_INTR_LINK_STATUS_CHANGE 0x0001 + +#define AQUANTIA_MMD_GLOABLE_REGISTERS 0x1E +#define AQUANTIA_GLOBAL_INTR_STANDARD_MASK 0xff00 +#define AQUANTIA_ALL_VENDOR_ALARMS_INTERRUPT_MASK 0x0001 + +#define AQUANTIA_GLOBAL_INTR_VENDOR_MASK 0xff01 +#define AQUANTIA_AUTO_AND_ALARMS_INTR_MASK 0x1001 + +#define AQUANTIA_AUTONEG_STANDARD_CONTROL1 0 +#define AQUANTIA_CTRL_AUTONEGOTIATION_ENABLE 0x1000 +#define AQUANTIA_CTRL_RESTART_AUTONEGOTIATION 0x0200 + +#define AQ_PHY_AUTO_STATUS_REG 0x70001 +#define PORT_LINK_DOWN 0 +#define PORT_LINK_UP 1 + +#define AQ_PHY_LINK_STATUS_REG 0x7c800 +#define SPEED_5G 5 +#define SPEED_2_5G 4 +#define SPEED_10G 3 +#define SPEED_1000MBS 2 +#define SPEED_100MBS 1 +#define SPEED_10MBS 0 diff --git a/sources/uboot-be550/drivers/net/ipq6018/ipq6018_edma.c b/sources/uboot-be550/drivers/net/ipq6018/ipq6018_edma.c new file mode 100755 index 00000000..4735df9b --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq6018/ipq6018_edma.c @@ -0,0 +1,1918 @@ +/* + * Copyright (c) 2016-2019 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER + * RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT + * NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE + * USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "ipq6018_edma.h" +#include "ipq_phy.h" + +DECLARE_GLOBAL_DATA_PTR; +#ifdef DEBUG +#define pr_debug(fmt, args...) printf(fmt, ##args); +#else +#define pr_debug(fmt, args...) +#endif + +#define pr_info(fmt, args...) printf(fmt, ##args); +#define pr_warn(fmt, args...) printf(fmt, ##args); + +#ifndef CONFIG_IPQ6018_BRIDGED_MODE +#define IPQ6018_EDMA_MAC_PORT_NO 3 +#endif + +static struct ipq6018_eth_dev *ipq6018_edma_dev[IPQ6018_EDMA_DEV]; + +uchar ipq6018_def_enetaddr[6] = {0x00, 0x03, 0x7F, 0xBA, 0xDB, 0xAD}; +phy_info_t *phy_info[IPQ6018_PHY_MAX] = {0}; +int sgmii_mode[2] = {0}; + +extern void qca8075_ess_reset(void); +extern void psgmii_self_test(void); +extern void clear_self_test_config(void); +extern int ipq_sw_mdio_init(const char *); +extern void ipq_qca8075_dump_phy_regs(u32); +extern int ipq_mdio_read(int mii_id, + int regnum, ushort *data); +extern void ipq_qca8075_phy_map_ops(struct phy_ops **ops); +extern int ipq_qca8075_phy_init(struct phy_ops **ops); +extern void qca8075_phy_interface_set_mode(uint32_t phy_id, + uint32_t mode); +extern int ipq_qca8033_phy_init(struct phy_ops **ops, u32 phy_id); +extern int ipq_qca8081_phy_init(struct phy_ops **ops, u32 phy_id); +extern int ipq_qca_aquantia_phy_init(struct phy_ops **ops, u32 phy_id); +extern int ipq_board_fw_download(unsigned int phy_addr); +static int tftp_acl_our_port; + +/* + * EDMA hardware instance + */ +static u32 ipq6018_edma_hw_addr; + +void ipq6018_edma_dump_data(uchar *data, int len) +{ + int i; + + if (data == NULL) + return; + + pr_info("data address = 0x%x, len = %d \n", (unsigned int)data, len); + + for (i = 0; i < len; i++) { + if ((i % 16) == 0) + printf("\n"); + pr_info("%02x ", (unsigned int)data[i]); + } + + pr_info("\n\n"); +} + +/* + * ipq6018_edma_reg_read() + * Read EDMA register + */ +uint32_t ipq6018_edma_reg_read(uint32_t reg_off) +{ + return (uint32_t)readl(ipq6018_edma_hw_addr + reg_off); +} + +/* + * ipq6018_edma_reg_write() + * Write EDMA register + */ +void ipq6018_edma_reg_write(uint32_t reg_off, uint32_t val) +{ + pr_debug("%s: reg_off = %x, val =%x\n", __func__, reg_off, val); + writel(val, (ipq6018_edma_hw_addr + reg_off)); +} + +/* + * ipq6018_edma_alloc_rx_buffer() + * Alloc Rx buffers for one RxFill ring + */ +int ipq6018_edma_alloc_rx_buffer(struct ipq6018_edma_hw *ehw, + struct ipq6018_edma_rxfill_ring *rxfill_ring) +{ + uint16_t num_alloc = 0; + uint16_t cons, next, counter; + struct ipq6018_edma_rxfill_desc *rxfill_desc; + uint32_t reg_data; + struct ipq6018_edma_rx_preheader *rxph; + + /* + * Read RXFILL ring producer index + */ + reg_data = ipq6018_edma_reg_read(IPQ6018_EDMA_REG_RXFILL_PROD_IDX( + rxfill_ring->id)); + + next = reg_data & IPQ6018_EDMA_RXFILL_PROD_IDX_MASK & (rxfill_ring->count - 1); + + /* + * Read RXFILL ring consumer index + */ + reg_data = ipq6018_edma_reg_read(IPQ6018_EDMA_REG_RXFILL_CONS_IDX( + rxfill_ring->id)); + + cons = reg_data & IPQ6018_EDMA_RXFILL_CONS_IDX_MASK; + + while (1) { + + counter = next; + + if (++counter == rxfill_ring->count) + counter = 0; + + if (counter == cons) + break; + + if (counter >= CONFIG_SYS_RX_ETH_BUFFER) { + pr_info("%s: counter >= CONFIG_SYS_RX_ETH_BUFFER counter = %d\n", + __func__, counter); + break; + } + /* + * Get RXFILL descriptor + */ + rxfill_desc = IPQ6018_EDMA_RXFILL_DESC(rxfill_ring, next); + + /* + * Make room for Rx preheader + */ + rxph = (struct ipq6018_edma_rx_preheader *)rxfill_desc->buffer_addr; + + /* + * Fill the opaque value + */ + rxph->opaque = next; + + /* + * Save buffer size in RXFILL descriptor + */ + rxfill_desc->word1 = cpu_to_le32(IPQ6018_EDMA_RX_BUFF_SIZE & + IPQ6018_EDMA_RXFILL_BUF_SIZE_MASK); + + num_alloc++; + next = counter; + } + + if (num_alloc) { + /* + * Update RXFILL ring producer index + */ + reg_data = next & IPQ6018_EDMA_RXFILL_PROD_IDX_MASK; + + /* + * make sure the producer index updated before + * updating the hardware + */ + ipq6018_edma_reg_write(IPQ6018_EDMA_REG_RXFILL_PROD_IDX( + rxfill_ring->id), reg_data); + + pr_debug("%s: num_alloc = %d\n", __func__, num_alloc); + } + + return num_alloc; +} + +/* + * ipq6018_edma_clean_tx() + * Reap Tx descriptors + */ +uint32_t ipq6018_edma_clean_tx(struct ipq6018_edma_hw *ehw, + struct ipq6018_edma_txcmpl_ring *txcmpl_ring) +{ + struct ipq6018_edma_txcmpl_desc *txcmpl_desc; + uint16_t prod_idx, cons_idx; + uint32_t data; + uint32_t txcmpl_consumed = 0; + uchar *skb; + + /* + * Get TXCMPL ring producer index + */ + data = ipq6018_edma_reg_read(IPQ6018_EDMA_REG_TXCMPL_PROD_IDX( + txcmpl_ring->id)); + prod_idx = data & IPQ6018_EDMA_TXCMPL_PROD_IDX_MASK; + + /* + * Get TXCMPL ring consumer index + */ + data = ipq6018_edma_reg_read(IPQ6018_EDMA_REG_TXCMPL_CONS_IDX( + txcmpl_ring->id)); + cons_idx = data & IPQ6018_EDMA_TXCMPL_CONS_IDX_MASK; + + while (cons_idx != prod_idx) { + + txcmpl_desc = IPQ6018_EDMA_TXCMPL_DESC(txcmpl_ring, cons_idx); + + skb = (uchar *)txcmpl_desc->buffer_addr; + + if (unlikely(!skb)) { + pr_debug("Invalid skb: cons_idx:%u prod_idx:%u status %x\n", + cons_idx, prod_idx, txcmpl_desc->status); + } + + if (++cons_idx == txcmpl_ring->count) + cons_idx = 0; + + txcmpl_consumed++; + } + + pr_debug("%s :%u txcmpl_consumed:%u prod_idx:%u cons_idx:%u\n", + __func__, txcmpl_ring->id, txcmpl_consumed, prod_idx, + cons_idx); + + if (txcmpl_consumed == 0) + return 0; + + /* + * Update TXCMPL ring consumer index + */ + ipq6018_edma_reg_write(IPQ6018_EDMA_REG_TXCMPL_CONS_IDX( + txcmpl_ring->id), cons_idx); + + return txcmpl_consumed; +} + +/* + * ipq6018_edma_clean_rx() + * Reap Rx descriptors + */ +uint32_t ipq6018_edma_clean_rx(struct ipq6018_edma_common_info *c_info, + struct ipq6018_edma_rxdesc_ring *rxdesc_ring) +{ + void *skb; + struct ipq6018_edma_rxdesc_desc *rxdesc_desc; + struct ipq6018_edma_rx_preheader *rxph; + uint16_t prod_idx, cons_idx; + int src_port_num; + int pkt_length; + int rx = CONFIG_SYS_RX_ETH_BUFFER; + u16 cleaned_count = 0; + + pr_debug("%s: rxdesc_ring->id = %d\n", __func__, rxdesc_ring->id); + /* + * Read Rx ring consumer index + */ + cons_idx = ipq6018_edma_reg_read(IPQ6018_EDMA_REG_RXDESC_CONS_IDX( + rxdesc_ring->id)) & + IPQ6018_EDMA_RXDESC_CONS_IDX_MASK; + + while (rx) { + /* + * Read Rx ring producer index + */ + prod_idx = ipq6018_edma_reg_read( + IPQ6018_EDMA_REG_RXDESC_PROD_IDX(rxdesc_ring->id)) + & IPQ6018_EDMA_RXDESC_PROD_IDX_MASK; + + if (cons_idx == prod_idx) { + pr_debug("%s: cons = prod \n", __func__); + break; + } + + rxdesc_desc = IPQ6018_EDMA_RXDESC_DESC(rxdesc_ring, cons_idx); + + skb = (void *)rxdesc_desc->buffer_addr; + + /* + * Get Rx preheader + */ + rxph = (struct ipq6018_edma_rx_preheader *)skb; + + rx--; + + /* + * Check src_info from Rx preheader + */ + if (IPQ6018_EDMA_RXPH_SRC_INFO_TYPE_GET(rxph) == + IPQ6018_EDMA_PREHDR_DSTINFO_PORTID_IND) { + src_port_num = rxph->src_info & + IPQ6018_EDMA_PREHDR_PORTNUM_BITS; + } else { + pr_warn("WARN: src_info_type:0x%x. Drop skb:%p\n", + IPQ6018_EDMA_RXPH_SRC_INFO_TYPE_GET(rxph), + skb); + goto next_rx_desc; + } + + /* + * Get packet length + */ + pkt_length = rxdesc_desc->status & + IPQ6018_EDMA_RXDESC_PACKET_LEN_MASK; + + if (unlikely((src_port_num < IPQ6018_NSS_DP_START_PHY_PORT) || + (src_port_num > IPQ6018_NSS_DP_MAX_PHY_PORTS))) { + pr_warn("WARN: Port number error :%d. Drop skb:%p\n", + src_port_num, skb); + goto next_rx_desc; + } + + cleaned_count++; + + /* + * Remove Rx preheader + */ + skb = skb + IPQ6018_EDMA_RX_PREHDR_SIZE; + + pr_debug("%s: received pkt %p with length %d\n", + __func__, skb, pkt_length); + + net_process_received_packet(skb, pkt_length); +next_rx_desc: + /* + * Update consumer index + */ + if (++cons_idx == rxdesc_ring->count) + cons_idx = 0; + } + + if (cleaned_count) { + ipq6018_edma_reg_write(IPQ6018_EDMA_REG_RXDESC_CONS_IDX( + rxdesc_ring->id), cons_idx); + } + + return 0; +} + +/* + * ip6018_edma_rx_complete() + */ +static int ipq6018_edma_rx_complete(struct ipq6018_edma_common_info *c_info) +{ + struct ipq6018_edma_hw *ehw = &c_info->hw; + struct ipq6018_edma_txcmpl_ring *txcmpl_ring; + struct ipq6018_edma_rxdesc_ring *rxdesc_ring; + struct ipq6018_edma_rxfill_ring *rxfill_ring; + uint32_t misc_intr_status, reg_data; + int i; + + for (i = 0; i < ehw->rxdesc_rings; i++) { + rxdesc_ring = &ehw->rxdesc_ring[i]; + ipq6018_edma_clean_rx(c_info, rxdesc_ring); + } + + for (i = 0; i < ehw->txcmpl_rings; i++) { + txcmpl_ring = &ehw->txcmpl_ring[i]; + ipq6018_edma_clean_tx(ehw, txcmpl_ring); + } + + for (i = 0; i < ehw->rxfill_rings; i++) { + rxfill_ring = &ehw->rxfill_ring[i]; + ipq6018_edma_alloc_rx_buffer(ehw, rxfill_ring); + } + + /* + * Set RXDESC ring interrupt mask + */ + for (i = 0; i < ehw->rxdesc_rings; i++) { + rxdesc_ring = &ehw->rxdesc_ring[i]; + ipq6018_edma_reg_write( + IPQ6018_EDMA_REG_RXDESC_INT_MASK(rxdesc_ring->id), + ehw->rxdesc_intr_mask); + } + + /* + * Set TXCMPL ring interrupt mask + */ + for (i = 0; i < ehw->txcmpl_rings; i++) { + txcmpl_ring = &ehw->txcmpl_ring[i]; + ipq6018_edma_reg_write(IPQ6018_EDMA_REG_TX_INT_MASK( + txcmpl_ring->id), + ehw->txcmpl_intr_mask); + } + + /* + * Set RXFILL ring interrupt mask + */ + for (i = 0; i < ehw->rxfill_rings; i++) { + rxfill_ring = &ehw->rxfill_ring[i]; + ipq6018_edma_reg_write(IPQ6018_EDMA_REG_RXFILL_INT_MASK( + rxfill_ring->id), + ehw->rxfill_intr_mask); + } + + /* + * Read Misc intr status + */ + reg_data = ipq6018_edma_reg_read(IPQ6018_EDMA_REG_MISC_INT_STAT); + misc_intr_status = reg_data & ehw->misc_intr_mask; + + if (misc_intr_status != 0) { + pr_info("%s: misc_intr_status = 0x%x\n", __func__, + misc_intr_status); + ipq6018_edma_reg_write(IPQ6018_EDMA_REG_MISC_INT_MASK, + IPQ6018_EDMA_MASK_INT_DISABLE); + } + + return 0; +} + +/* + * ipq6018_eth_snd() + * Transmit a packet using an EDMA ring + */ +static int ipq6018_eth_snd(struct eth_device *dev, void *packet, int length) +{ + struct ipq6018_eth_dev *priv = dev->priv; + struct ipq6018_edma_common_info *c_info = priv->c_info; + struct ipq6018_edma_hw *ehw = &c_info->hw; + struct ipq6018_edma_txdesc_desc *txdesc; + struct ipq6018_edma_tx_preheader *txph; + struct ipq6018_edma_txdesc_ring *txdesc_ring; + uint16_t hw_next_to_use, hw_next_to_clean, chk_idx; + uint32_t data; + uchar *skb; + + txdesc_ring = ehw->txdesc_ring; + + if (tftp_acl_our_port != tftp_our_port) { + /* Allowing tftp packets */ + ipq6018_ppe_acl_set(3, 0x4, 0x1, tftp_our_port, 0xffff, 0, 0); + tftp_acl_our_port = tftp_our_port; + } + /* + * Read TXDESC ring producer index + */ + data = ipq6018_edma_reg_read(IPQ6018_EDMA_REG_TXDESC_PROD_IDX( + txdesc_ring->id)); + + hw_next_to_use = data & IPQ6018_EDMA_TXDESC_PROD_IDX_MASK; + + pr_debug("%s: txdesc_ring->id = %d\n", __func__, txdesc_ring->id); + + /* + * Read TXDESC ring consumer index + */ + /* + * TODO - read to local variable to optimize uncached access + */ + data = ipq6018_edma_reg_read( + IPQ6018_EDMA_REG_TXDESC_CONS_IDX(txdesc_ring->id)); + + hw_next_to_clean = data & IPQ6018_EDMA_TXDESC_CONS_IDX_MASK; + + /* + * Check for available Tx descriptor + */ + chk_idx = (hw_next_to_use + 1) & (txdesc_ring->count-1); + + if (chk_idx == hw_next_to_clean) { + return NETDEV_TX_BUSY; + } + + /* + * Get Tx descriptor + */ + txdesc = IPQ6018_EDMA_TXDESC_DESC(txdesc_ring, hw_next_to_use); + + txdesc->word1 = 0; + + skb = (uchar *)txdesc->buffer_addr; + + pr_debug("%s: txdesc->buffer_addr = 0x%x length = %d \ + prod_idx = %d cons_idx = %d\n", + __func__, txdesc->buffer_addr, length, + hw_next_to_use, hw_next_to_clean); + + /* + * Make room for Tx preheader + */ + txph = (struct ipq6018_edma_tx_preheader *)skb; + + memset((void *)txph, 0, IPQ6018_EDMA_TX_PREHDR_SIZE); + +#ifdef CONFIG_IPQ6018_BRIDGED_MODE + /* VP 0x0 share vsi 2 with port 1-4 */ + txph->src_info = 0x2000; + txph->dst_info = 0x0; +#else + /* + * Populate Tx preheader dst info, port id is macid in dp_dev + */ + + txph->dst_info = (IPQ6018_EDMA_PREHDR_DSTINFO_PORTID_IND << 8) | + (IPQ6018_EDMA_MAC_PORT_NO & 0x0fff); + +#endif + + /* + * Set opaque field in preheader + */ + txph->opaque = cpu_to_le32(skb); + + /* + * copy the packet + */ + memcpy(skb + IPQ6018_EDMA_TX_PREHDR_SIZE, packet, length); + + /* + * Populate Tx descriptor + */ + txdesc->word1 |= (1 << IPQ6018_EDMA_TXDESC_PREHEADER_SHIFT) + | ((IPQ6018_EDMA_TX_PREHDR_SIZE & + IPQ6018_EDMA_TXDESC_DATA_OFFSET_MASK) + << IPQ6018_EDMA_TXDESC_DATA_OFFSET_SHIFT); + txdesc->word1 |= ((length & IPQ6018_EDMA_TXDESC_DATA_LENGTH_MASK) + << IPQ6018_EDMA_TXDESC_DATA_LENGTH_SHIFT); + + /* + * Update producer index + */ + hw_next_to_use = (hw_next_to_use + 1) & (txdesc_ring->count - 1); + + /* + * make sure the hw_next_to_use is updated before the + * write to hardware + */ + + ipq6018_edma_reg_write(IPQ6018_EDMA_REG_TXDESC_PROD_IDX( + txdesc_ring->id), hw_next_to_use & + IPQ6018_EDMA_TXDESC_PROD_IDX_MASK); + + pr_debug("%s: successfull\n", __func__); + + return EDMA_TX_OK; +} + +static int ipq6018_eth_recv(struct eth_device *dev) +{ + struct ipq6018_eth_dev *priv = dev->priv; + struct ipq6018_edma_common_info *c_info = priv->c_info; + struct ipq6018_edma_rxdesc_ring *rxdesc_ring; + struct ipq6018_edma_txcmpl_ring *txcmpl_ring; + struct ipq6018_edma_rxfill_ring *rxfill_ring; + struct ipq6018_edma_hw *ehw = &c_info->hw; + volatile u32 reg_data; + u32 rxdesc_intr_status = 0, txcmpl_intr_status = 0, rxfill_intr_status = 0; + int i; + + /* + * Read RxDesc intr status + */ + for (i = 0; i < ehw->rxdesc_rings; i++) { + rxdesc_ring = &ehw->rxdesc_ring[i]; + + reg_data = ipq6018_edma_reg_read( + IPQ6018_EDMA_REG_RXDESC_INT_STAT( + rxdesc_ring->id)); + rxdesc_intr_status |= reg_data & + IPQ6018_EDMA_RXDESC_RING_INT_STATUS_MASK; + + /* + * Disable RxDesc intr + */ + ipq6018_edma_reg_write(IPQ6018_EDMA_REG_RXDESC_INT_MASK( + rxdesc_ring->id), + IPQ6018_EDMA_MASK_INT_DISABLE); + } + + /* + * Read TxCmpl intr status + */ + for (i = 0; i < ehw->txcmpl_rings; i++) { + txcmpl_ring = &ehw->txcmpl_ring[i]; + + reg_data = ipq6018_edma_reg_read( + IPQ6018_EDMA_REG_TX_INT_STAT( + txcmpl_ring->id)); + txcmpl_intr_status |= reg_data & + IPQ6018_EDMA_TXCMPL_RING_INT_STATUS_MASK; + + /* + * Disable TxCmpl intr + */ + ipq6018_edma_reg_write(IPQ6018_EDMA_REG_TX_INT_MASK( + txcmpl_ring->id), + IPQ6018_EDMA_MASK_INT_DISABLE); + } + + /* + * Read RxFill intr status + */ + for (i = 0; i < ehw->rxfill_rings; i++) { + rxfill_ring = &ehw->rxfill_ring[i]; + + reg_data = ipq6018_edma_reg_read( + IPQ6018_EDMA_REG_RXFILL_INT_STAT( + rxfill_ring->id)); + rxfill_intr_status |= reg_data & + IPQ6018_EDMA_RXFILL_RING_INT_STATUS_MASK; + + /* + * Disable RxFill intr + */ + ipq6018_edma_reg_write(IPQ6018_EDMA_REG_RXFILL_INT_MASK( + rxfill_ring->id), + IPQ6018_EDMA_MASK_INT_DISABLE); + } + + if ((rxdesc_intr_status != 0) || (txcmpl_intr_status != 0) || + (rxfill_intr_status != 0)) { + for (i = 0; i < ehw->rxdesc_rings; i++) { + rxdesc_ring = &ehw->rxdesc_ring[i]; + ipq6018_edma_reg_write(IPQ6018_EDMA_REG_RXDESC_INT_MASK( + rxdesc_ring->id), + IPQ6018_EDMA_MASK_INT_DISABLE); + } + ipq6018_edma_rx_complete(c_info); + } + + return 0; +} + +/* + * ipq6018_edma_setup_ring_resources() + * Allocate/setup resources for EDMA rings + */ +static int ipq6018_edma_setup_ring_resources(struct ipq6018_edma_hw *ehw) +{ + struct ipq6018_edma_txcmpl_ring *txcmpl_ring; + struct ipq6018_edma_txdesc_ring *txdesc_ring; + struct ipq6018_edma_rxfill_ring *rxfill_ring; + struct ipq6018_edma_rxdesc_ring *rxdesc_ring; + struct ipq6018_edma_txdesc_desc *tx_desc; + struct ipq6018_edma_rxfill_desc *rxfill_desc; + int i, j, index; + void *tx_buf; + void *rx_buf; + + /* + * Allocate Rx fill ring descriptors + */ + for (i = 0; i < ehw->rxfill_rings; i++) { + rxfill_ring = &ehw->rxfill_ring[i]; + rxfill_ring->count = IPQ6018_EDMA_RXFILL_RING_SIZE; + rxfill_ring->id = ehw->rxfill_ring_start + i; + rxfill_ring->desc = (void *)noncached_alloc( + sizeof(struct ipq6018_edma_rxfill_desc) * + rxfill_ring->count, + CONFIG_SYS_CACHELINE_SIZE); + + if (rxfill_ring->desc == NULL) { + pr_info("%s: rxfill_ring->desc alloc error\n", __func__); + return -ENOMEM; + } + rxfill_ring->dma = virt_to_phys(rxfill_ring->desc); + rx_buf = (void *)noncached_alloc(PKTSIZE_ALIGN * + rxfill_ring->count, + CONFIG_SYS_CACHELINE_SIZE); + + if (rx_buf == NULL) { + pr_info("%s: rxfill_ring->desc buffer alloc error\n", + __func__); + return -ENOMEM; + } + + for (j = 0; j < rxfill_ring->count; j++) { + rxfill_desc = IPQ6018_EDMA_RXFILL_DESC(rxfill_ring, j); + rxfill_desc->buffer_addr = virt_to_phys(rx_buf); + rx_buf += PKTSIZE_ALIGN; + } + } + + /* + * Allocate RxDesc ring descriptors + */ + for (i = 0; i < ehw->rxdesc_rings; i++) { + rxdesc_ring = &ehw->rxdesc_ring[i]; + rxdesc_ring->count = IPQ6018_EDMA_RXDESC_RING_SIZE; + rxdesc_ring->id = ehw->rxdesc_ring_start + i; + + /* + * Create a mapping between RX Desc ring and Rx fill ring. + * Number of fill rings are lesser than the descriptor rings + * Share the fill rings across descriptor rings. + */ + + index = ehw->rxfill_ring_start + (i % ehw->rxfill_rings); + rxdesc_ring->rxfill = + &ehw->rxfill_ring[index - ehw->rxfill_ring_start]; + rxdesc_ring->rxfill = ehw->rxfill_ring; + + rxdesc_ring->desc = (void *)noncached_alloc( + sizeof(struct ipq6018_edma_rxdesc_desc) * + rxdesc_ring->count, + CONFIG_SYS_CACHELINE_SIZE); + + if (rxdesc_ring->desc == NULL) { + pr_info("%s: rxdesc_ring->desc alloc error\n", __func__); + return -ENOMEM; + } + rxdesc_ring->dma = virt_to_phys(rxdesc_ring->desc); + } + + /* + * Allocate TxCmpl ring descriptors + */ + for (i = 0; i < ehw->txcmpl_rings; i++) { + txcmpl_ring = &ehw->txcmpl_ring[i]; + txcmpl_ring->count = IPQ6018_EDMA_TXCMPL_RING_SIZE; + txcmpl_ring->id = ehw->txcmpl_ring_start + i; + txcmpl_ring->desc = (void *)noncached_alloc( + sizeof(struct ipq6018_edma_txcmpl_desc) * + txcmpl_ring->count, + CONFIG_SYS_CACHELINE_SIZE); + + if (txcmpl_ring->desc == NULL) { + pr_info("%s: txcmpl_ring->desc alloc error\n", __func__); + return -ENOMEM; + } + txcmpl_ring->dma = virt_to_phys(txcmpl_ring->desc); + } + + + /* + * Allocate TxDesc ring descriptors + */ + for (i = 0; i < ehw->txdesc_rings; i++) { + txdesc_ring = &ehw->txdesc_ring[i]; + txdesc_ring->count = IPQ6018_EDMA_TXDESC_RING_SIZE; + txdesc_ring->id = ehw->txdesc_ring_start + i; + txdesc_ring->desc = (void *)noncached_alloc( + sizeof(struct ipq6018_edma_txdesc_desc) * + txdesc_ring->count, + CONFIG_SYS_CACHELINE_SIZE); + + if (txdesc_ring->desc == NULL) { + pr_info("%s: txdesc_ring->desc alloc error\n", __func__); + return -ENOMEM; + } + + txdesc_ring->dma = virt_to_phys(txdesc_ring->desc); + tx_buf = (void *)noncached_alloc(IPQ6018_EDMA_TX_BUF_SIZE * + txdesc_ring->count, + CONFIG_SYS_CACHELINE_SIZE); + + if (tx_buf == NULL) { + pr_info("%s: txdesc_ring->desc buffer alloc error\n", + __func__); + return -ENOMEM; + } + + for (j = 0; j < txdesc_ring->count; j++) { + tx_desc = IPQ6018_EDMA_TXDESC_DESC(txdesc_ring, j); + tx_desc->buffer_addr = virt_to_phys(tx_buf); + tx_buf += IPQ6018_EDMA_TX_BUF_SIZE; + } + } + + pr_info("%s: successfull\n", __func__); + + return 0; + +} + +/* + * ipq6018_edma_free_desc() + * Free EDMA desc memory + */ +static void ipq6018_edma_free_desc(struct ipq6018_edma_common_info *c_info) +{ + struct ipq6018_edma_hw *ehw = &c_info->hw; + struct ipq6018_edma_txcmpl_ring *txcmpl_ring; + struct ipq6018_edma_txdesc_ring *txdesc_ring; + struct ipq6018_edma_rxfill_ring *rxfill_ring; + struct ipq6018_edma_rxdesc_ring *rxdesc_ring; + struct ipq6018_edma_txdesc_desc *tx_desc; + int i; + + for (i = 0; i < ehw->rxfill_rings; i++) { + rxfill_ring = &ehw->rxfill_ring[i]; + if (rxfill_ring->desc) + ipq6018_free_mem(rxfill_ring->desc); + } + + for (i = 0; i < ehw->rxdesc_rings; i++) { + rxdesc_ring = &ehw->rxdesc_ring[i]; + if (rxdesc_ring->desc) + ipq6018_free_mem(rxdesc_ring->desc); + } + + for (i = 0; i < ehw->txcmpl_rings; i++) { + txcmpl_ring = &ehw->txcmpl_ring[i]; + if (txcmpl_ring->desc) { + ipq6018_free_mem(txcmpl_ring->desc); + } + } + + for (i = 0; i < ehw->txdesc_rings; i++) { + txdesc_ring = &ehw->txdesc_ring[i]; + if (txdesc_ring->desc) { + tx_desc = IPQ6018_EDMA_TXDESC_DESC(txdesc_ring, 0); + if (tx_desc->buffer_addr) + ipq6018_free_mem((void *)tx_desc->buffer_addr); + ipq6018_free_mem(txdesc_ring->desc); + } + } +} + +/* + * ipq6018_edma_free_rings() + * Free EDMA software rings + */ +static void ipq6018_edma_free_rings(struct ipq6018_edma_common_info *c_info) +{ + struct ipq6018_edma_hw *ehw = &c_info->hw; + ipq6018_free_mem(ehw->rxfill_ring); + ipq6018_free_mem(ehw->rxdesc_ring); + ipq6018_free_mem(ehw->txdesc_ring); + ipq6018_free_mem(ehw->txcmpl_ring); +} + +static void ipq6018_edma_disable_rings(struct ipq6018_edma_hw *edma_hw) +{ + int i, desc_index; + u32 data; + + /* + * Disable Rx rings + */ + for (i = 0; i < IPQ6018_EDMA_MAX_RXDESC_RINGS; i++) { + data = ipq6018_edma_reg_read(IPQ6018_EDMA_REG_RXDESC_CTRL(i)); + data &= ~IPQ6018_EDMA_RXDESC_RX_EN; + ipq6018_edma_reg_write(IPQ6018_EDMA_REG_RXDESC_CTRL(i), data); + } + + /* + * Disable RxFill Rings + */ + for (i = 0; i < IPQ6018_EDMA_MAX_RXFILL_RINGS; i++) { + data = ipq6018_edma_reg_read( + IPQ6018_EDMA_REG_RXFILL_RING_EN(i)); + data &= ~IPQ6018_EDMA_RXFILL_RING_EN; + ipq6018_edma_reg_write( + IPQ6018_EDMA_REG_RXFILL_RING_EN(i), data); + } + + /* + * Disable Tx rings + */ + for (desc_index = 0; desc_index < + IPQ6018_EDMA_MAX_TXDESC_RINGS; desc_index++) { + data = ipq6018_edma_reg_read( + IPQ6018_EDMA_REG_TXDESC_CTRL(desc_index)); + data &= ~IPQ6018_EDMA_TXDESC_TX_EN; + ipq6018_edma_reg_write( + IPQ6018_EDMA_REG_TXDESC_CTRL(desc_index), data); + } +} + +static void ipq6018_edma_disable_intr(struct ipq6018_edma_hw *ehw) +{ + int i; + + /* + * Disable interrupts + */ + for (i = 0; i < IPQ6018_EDMA_MAX_TXCMPL_RINGS; i++) + ipq6018_edma_reg_write(IPQ6018_EDMA_REG_TX_INT_MASK(i), 0); + + for (i = 0; i < IPQ6018_EDMA_MAX_RXFILL_RINGS; i++) + ipq6018_edma_reg_write(IPQ6018_EDMA_REG_RXFILL_INT_MASK(i), 0); + + for (i = 0; i < IPQ6018_EDMA_MAX_RXDESC_RINGS; i++) + ipq6018_edma_reg_write(IPQ6018_EDMA_REG_RX_INT_CTRL(i), 0); + + ipq6018_edma_reg_write(IPQ6018_EDMA_REG_MISC_INT_MASK, + IPQ6018_EDMA_MASK_INT_DISABLE); +} + +static void set_sgmii_mode(int port_id, int sg_mode) +{ + if (port_id == 3) + sgmii_mode[0] = sg_mode; + else if (port_id == 4) + sgmii_mode[1] = sg_mode; +} + +static int get_sgmii_mode(int port_id) +{ + if (port_id == 3) + return sgmii_mode[0]; + else if (port_id == 4) + return sgmii_mode[1]; + else + return -1; +} + +static int ipq6018_eth_init(struct eth_device *eth_dev, bd_t *this) +{ + struct ipq6018_eth_dev *priv = eth_dev->priv; + int i; + u8 status; + struct phy_ops *phy_get_ops; + static fal_port_speed_t old_speed[IPQ6018_PHY_MAX] = {[0 ... IPQ6018_PHY_MAX-1] = FAL_SPEED_BUTT}; + static fal_port_speed_t curr_speed[IPQ6018_PHY_MAX]; + static int current_active_port = -1, previous_active_port = -1; + fal_port_duplex_t duplex; + char *lstatus[] = {"up", "Down"}; + char *dp[] = {"Half", "Full"}; + int linkup=0; + int mac_speed = 0, speed_clock1 = 0, speed_clock2 = 0; + int phy_addr, port_8033 = -1, node, aquantia_port = -1; + int sfp_port = -1; + int phy_node = -1; + int ret_sgmii_mode; + int sfp_mode, sgmii_fiber = -1; + char *active_port = NULL; + + node = fdt_path_offset(gd->fdt_blob, "/ess-switch"); + if (node >= 0) + port_8033 = fdtdec_get_uint(gd->fdt_blob, node, "8033_port", -1); + + if (node >= 0) + aquantia_port = fdtdec_get_uint(gd->fdt_blob, node, "aquantia_port", -1); + + if (node >= 0) + sfp_port = fdtdec_get_uint(gd->fdt_blob, node, "sfp_port", -1); + + phy_node = fdt_path_offset(gd->fdt_blob, "/ess-switch/port_phyinfo"); + + active_port = getenv("active_port"); + if (active_port != NULL) { + current_active_port = simple_strtol(active_port, NULL, 10); + if (current_active_port < 0 || current_active_port > 4) + printf("active_port must be in the range of 0 to 4 in ipq6018 platform\n"); + } else { + current_active_port = -1; + } + + if (previous_active_port != current_active_port && current_active_port != -1) { + previous_active_port = current_active_port; + printf("Port%d has been set as the active_port\n", current_active_port); + } + + /* + * Check PHY link, speed, Duplex on all phys. + * we will proceed even if single link is up + * else we will return with -1; + */ + for (i = 0; i < IPQ6018_PHY_MAX; i++) { + if (current_active_port != -1 && i != current_active_port) { + ipq6018_gmac_port_disable(i); + ppe_port_bridge_txmac_set(i + 1, 1); + old_speed[i] = FAL_SPEED_BUTT; + /* + * Old speed has been set as FAL_SPEED_BUTT here so that + * if again the previous active_port is made as active, + * the configurations required will be done again and MAC + * would be enabled. + * + * Note that only for the active port TX/RX MAC would be + * enabled and for all other ports, the same would be + * disabled. + */ + continue; + } + + if (i == sfp_port) { + status = phy_status_get_from_ppe(i); + duplex = FAL_FULL_DUPLEX; + sfp_mode = fdtdec_get_uint(gd->fdt_blob, node, "switch_mac_mode1", -1); + if (sfp_mode < 0) { + printf("\nError: switch_mac_mode1 not specified in dts"); + return sfp_mode; + } + if (sfp_mode == PORT_WRAPPER_SGMII_FIBER) { + sgmii_fiber = 1; + curr_speed[i] = FAL_SPEED_1000; + } else if (sfp_mode == PORT_WRAPPER_10GBASE_R) { + sgmii_fiber = 0; + curr_speed[i] = FAL_SPEED_10000; + } else { + + printf("\nError: wrong mode specified for SFP Port"); + return sfp_mode; + } + } else { + if (!priv->ops[i]) { + printf ("Phy ops not mapped\n"); + continue; + } + phy_get_ops = priv->ops[i]; + + if (!phy_get_ops->phy_get_link_status || + !phy_get_ops->phy_get_speed || + !phy_get_ops->phy_get_duplex) { + printf ("Link status/Get speed/Get duplex not mapped\n"); + return -1; + } + + if (phy_node >= 0) { + phy_addr = phy_info[i]->phy_address; + } else { + + if (i == port_8033) + phy_addr = QCA8033_PHY_ADDR; + else if (i == aquantia_port) + phy_addr = AQU_PHY_ADDR; + else + phy_addr = i; + } + status = phy_get_ops->phy_get_link_status(priv->mac_unit, phy_addr); + phy_get_ops->phy_get_speed(priv->mac_unit, phy_addr, &curr_speed[i]); + phy_get_ops->phy_get_duplex(priv->mac_unit, phy_addr, &duplex); + } + + if (status == 0) { + linkup++; + if (old_speed[i] == curr_speed[i]) { + printf ("eth%d PHY%d %s Speed :%d %s duplex\n", + priv->mac_unit, i, lstatus[status], curr_speed[i], + dp[duplex]); + continue; + } else { + old_speed[i] = curr_speed[i]; + } + } else { + printf ("eth%d PHY%d %s Speed :%d %s duplex\n", + priv->mac_unit, i, lstatus[status], curr_speed[i], + dp[duplex]); + continue; + } + + switch (curr_speed[i]) { + case FAL_SPEED_10: + mac_speed = 0x0; + if (i == aquantia_port) { + printf("10M speed not supported\n"); + ppe_port_bridge_txmac_set(i + 1, status); + continue; + } + speed_clock1 = 0x109; + speed_clock2 = 0x9; + printf ("eth%d PHY%d %s Speed :%d %s duplex\n", + priv->mac_unit, i, lstatus[status], curr_speed[i], + dp[duplex]); + if (phy_node >= 0) { + if (phy_info[i]->phy_type == QCA8081_PHY_TYPE) { + set_sgmii_mode(i, 1); + if (i == 4) + speed_clock1 = 0x309; + } + } + break; + case FAL_SPEED_100: + mac_speed = 0x1; + if (i == aquantia_port) { + speed_clock1 = 0x309; + speed_clock2 = 0x4; + } else { + speed_clock1 = 0x109; + speed_clock2 = 0x0; + } + printf ("eth%d PHY%d %s Speed :%d %s duplex\n", + priv->mac_unit, i, lstatus[status], curr_speed[i], + dp[duplex]); + if (phy_node >= 0) { + if (phy_info[i]->phy_type == QCA8081_PHY_TYPE) { + set_sgmii_mode(i, 1); + if (i == 4) + speed_clock1 = 0x309; + } + } + break; + case FAL_SPEED_1000: + mac_speed = 0x2; + if (i == aquantia_port) + speed_clock1 = 0x304; + else if (i == sfp_port) + speed_clock1 = 0x301; + else + speed_clock1 = 0x101; + speed_clock2 = 0x0; + printf ("eth%d PHY%d %s Speed :%d %s duplex\n", + priv->mac_unit, i, lstatus[status], curr_speed[i], + dp[duplex]); + if (phy_node >= 0) { + if (phy_info[i]->phy_type == QCA8081_PHY_TYPE) { + set_sgmii_mode(i, 1); + if (i == 4) + speed_clock1 = 0x301; + } + } + break; + case FAL_SPEED_2500: + if (i == aquantia_port) { + mac_speed = 0x4; + speed_clock1 = 0x307; + speed_clock2 = 0x0; + } + if (phy_node >= 0) { + if (phy_info[i]->phy_type == QCA8081_PHY_TYPE) { + mac_speed = 0x2; + set_sgmii_mode(i, 0); + if (i == 4) + speed_clock1 = 0x301; + else if (i == 3) + speed_clock1 = 0x101; + speed_clock2 = 0x0; + } + } + printf ("eth%d PHY%d %s Speed :%d %s duplex\n", + priv->mac_unit, i, lstatus[status], curr_speed[i], + dp[duplex]); + break; + case FAL_SPEED_5000: + mac_speed = 0x5; + speed_clock1 = 0x303; + speed_clock2 = 0x0; + printf ("eth%d PHY%d %s Speed :%d %s duplex\n", + priv->mac_unit, i, lstatus[status], curr_speed[i], + dp[duplex]); + break; + case FAL_SPEED_10000: + mac_speed = 0x3; + speed_clock1 = 0x301; + speed_clock2 = 0x0; + printf ("eth%d PHY%d %s Speed :%d %s duplex\n", + priv->mac_unit, i, lstatus[status], curr_speed[i], + dp[duplex]); + break; + default: + printf("Unknown speed\n"); + break; + } + + if (phy_node >= 0) { + if (phy_info[i]->phy_type == QCA8081_PHY_TYPE) { + ret_sgmii_mode = get_sgmii_mode(i); + ppe_port_bridge_txmac_set(i + 1, 1); + if (ret_sgmii_mode == 1) { + if (i == 4) + ppe_uniphy_mode_set(0x1, PORT_WRAPPER_SGMII0_RGMII4); + else if (i == 3) + ppe_uniphy_mode_set(0x0, PORT_WRAPPER_SGMII0_RGMII4); + + } else if (ret_sgmii_mode == 0) { + if (i == 4) + ppe_uniphy_mode_set(0x1, PORT_WRAPPER_SGMII_PLUS); + else if (i == 3) + ppe_uniphy_mode_set(0x0, PORT_WRAPPER_SGMII_PLUS); + } + } + } + + if (i == sfp_port) { + if (sgmii_fiber) { + ppe_port_bridge_txmac_set(i + 1, 1); + ppe_uniphy_mode_set(0x1, PORT_WRAPPER_SGMII_FIBER); + ppe_port_mux_mac_type_set(i + 1, PORT_WRAPPER_SGMII_FIBER); + } else { + ppe_uniphy_mode_set(0x1, PORT_WRAPPER_10GBASE_R); + ppe_port_mux_mac_type_set(i + 1, PORT_WRAPPER_10GBASE_R); + } + } + + ipq6018_speed_clock_set(i, speed_clock1, speed_clock2); + + ipq6018_port_mac_clock_reset(i); + + if (i == aquantia_port) + ipq6018_uxsgmii_speed_set(i, mac_speed, duplex, status); + else if (i == sfp_port && sgmii_fiber == 0) + ipq6018_10g_r_speed_set(i, status); + else + ipq6018_pqsgmii_speed_set(i, mac_speed, status); + } + + if (linkup <= 0) { + /* No PHY link is alive */ + return -1; + } + + pr_info("%s: done\n", __func__); + + return 0; +} + +static int ipq6018_edma_wr_macaddr(struct eth_device *dev) +{ + return 0; +} + +static void ipq6018_eth_halt(struct eth_device *dev) +{ + pr_info("%s: done\n", __func__); +} + +static void ipq6018_edma_set_ring_values(struct ipq6018_edma_hw *edma_hw) +{ + edma_hw->txdesc_ring_start = IPQ6018_EDMA_TX_DESC_RING_START; + edma_hw->txdesc_rings = IPQ6018_EDMA_TX_DESC_RING_NOS; + edma_hw->txdesc_ring_end = IPQ6018_EDMA_TX_DESC_RING_SIZE; + + edma_hw->txcmpl_ring_start = IPQ6018_EDMA_TX_CMPL_RING_START; + edma_hw->txcmpl_rings = IPQ6018_EDMA_RX_FILL_RING_NOS; + edma_hw->txcmpl_ring_end = IPQ6018_EDMA_TX_CMPL_RING_SIZE; + + edma_hw->rxfill_ring_start = IPQ6018_EDMA_RX_FILL_RING_START; + edma_hw->rxfill_rings = IPQ6018_EDMA_RX_FILL_RING_NOS; + edma_hw->rxfill_ring_end = IPQ6018_EDMA_RX_FILL_RING_SIZE; + + edma_hw->rxdesc_ring_start = IPQ6018_EDMA_RX_DESC_RING_START; + edma_hw->rxdesc_rings = IPQ6018_EDMA_RX_DESC_RING_NOS; + edma_hw->rxdesc_ring_end = IPQ6018_EDMA_RX_DESC_RING_SIZE; + + pr_info("Num rings - TxDesc:%u (%u-%u) TxCmpl:%u (%u-%u)\n", + edma_hw->txdesc_rings, edma_hw->txdesc_ring_start, + (edma_hw->txdesc_ring_start + edma_hw->txdesc_rings - 1), + edma_hw->txcmpl_rings, edma_hw->txcmpl_ring_start, + (edma_hw->txcmpl_ring_start + edma_hw->txcmpl_rings - 1)); + + pr_info("RxDesc:%u (%u-%u) RxFill:%u (%u-%u)\n", + edma_hw->rxdesc_rings, edma_hw->rxdesc_ring_start, + (edma_hw->rxdesc_ring_start + edma_hw->rxdesc_rings - 1), + edma_hw->rxfill_rings, edma_hw->rxfill_ring_start, + (edma_hw->rxfill_ring_start + edma_hw->rxfill_rings - 1)); +} + +/* + * ipq6018_edma_alloc_rings() + * Allocate EDMA software rings + */ +static int ipq6018_edma_alloc_rings(struct ipq6018_edma_hw *ehw) +{ + ehw->rxfill_ring = (void *)noncached_alloc((sizeof( + struct ipq6018_edma_rxfill_ring) * + ehw->rxfill_rings), + CONFIG_SYS_CACHELINE_SIZE); + + if (!ehw->rxfill_ring) { + pr_info("%s: rxfill_ring alloc error\n", __func__); + return -ENOMEM; + } + + ehw->rxdesc_ring = (void *)noncached_alloc((sizeof( + struct ipq6018_edma_rxdesc_ring) * + ehw->rxdesc_rings), + CONFIG_SYS_CACHELINE_SIZE); + + if (!ehw->rxdesc_ring) { + pr_info("%s: rxdesc_ring alloc error\n", __func__); + return -ENOMEM; + } + + ehw->txdesc_ring = (void *)noncached_alloc((sizeof( + struct ipq6018_edma_txdesc_ring) * + ehw->txdesc_rings), + CONFIG_SYS_CACHELINE_SIZE); + if (!ehw->txdesc_ring) { + pr_info("%s: txdesc_ring alloc error\n", __func__); + return -ENOMEM; + } + + ehw->txcmpl_ring = (void *)noncached_alloc((sizeof( + struct ipq6018_edma_txcmpl_ring) * + ehw->txcmpl_rings), + CONFIG_SYS_CACHELINE_SIZE); + + if (!ehw->txcmpl_ring) { + pr_info("%s: txcmpl_ring alloc error\n", __func__); + return -ENOMEM; + } + + pr_info("%s: successfull\n", __func__); + + return 0; + +} + + +/* + * ipq6018_edma_init_rings() + * Initialize EDMA rings + */ +static int ipq6018_edma_init_rings(struct ipq6018_edma_hw *ehw) +{ + int ret; + + /* + * Setup ring values + */ + ipq6018_edma_set_ring_values(ehw); + + /* + * Allocate desc rings + */ + ret = ipq6018_edma_alloc_rings(ehw); + if (ret) + return ret; + + /* + * Setup ring resources + */ + ret = ipq6018_edma_setup_ring_resources(ehw); + if (ret) + return ret; + + return 0; +} + +/* + * ipq6018_edma_configure_txdesc_ring() + * Configure one TxDesc ring + */ +static void ipq6018_edma_configure_txdesc_ring(struct ipq6018_edma_hw *ehw, + struct ipq6018_edma_txdesc_ring *txdesc_ring) +{ + uint32_t data; + uint16_t hw_cons_idx; + + /* + * Configure TXDESC ring + */ + ipq6018_edma_reg_write(IPQ6018_EDMA_REG_TXDESC_BA(txdesc_ring->id), + (uint32_t)(txdesc_ring->dma & + IPQ6018_EDMA_RING_DMA_MASK)); + + ipq6018_edma_reg_write(IPQ6018_EDMA_REG_TXDESC_RING_SIZE( + txdesc_ring->id), (uint32_t)(txdesc_ring->count & + IPQ6018_EDMA_TXDESC_RING_SIZE_MASK)); + + data = ipq6018_edma_reg_read(IPQ6018_EDMA_REG_TXDESC_CONS_IDX( + txdesc_ring->id)); + + data &= ~(IPQ6018_EDMA_TXDESC_CONS_IDX_MASK); + hw_cons_idx = data; + + data = ipq6018_edma_reg_read(IPQ6018_EDMA_REG_TXDESC_PROD_IDX( + txdesc_ring->id)); + + data &= ~(IPQ6018_EDMA_TXDESC_PROD_IDX_MASK); + data |= hw_cons_idx & IPQ6018_EDMA_TXDESC_PROD_IDX_MASK; + + ipq6018_edma_reg_write(IPQ6018_EDMA_REG_TXDESC_PROD_IDX( + txdesc_ring->id), data); +} + +/* + * ipq6018_edma_configure_txcmpl_ring() + * Configure one TxCmpl ring + */ +static void ipq6018_edma_configure_txcmpl_ring(struct ipq6018_edma_hw *ehw, + struct ipq6018_edma_txcmpl_ring *txcmpl_ring) +{ + uint32_t txcmpl_ugt_thre, low_thre = 0, txcmpl_fc_thre = 0; + uint32_t tx_mod_timer; + + /* + * Configure TxCmpl ring base address + */ + ipq6018_edma_reg_write(IPQ6018_EDMA_REG_TXCMPL_BA(txcmpl_ring->id), + (uint32_t)(txcmpl_ring->dma & + IPQ6018_EDMA_RING_DMA_MASK)); + + ipq6018_edma_reg_write(IPQ6018_EDMA_REG_TXCMPL_RING_SIZE( + txcmpl_ring->id), (uint32_t)(txcmpl_ring->count & + IPQ6018_EDMA_TXDESC_RING_SIZE_MASK)); + + /* + * Set TxCmpl ret mode to opaque + */ + ipq6018_edma_reg_write(IPQ6018_EDMA_REG_TXCMPL_CTRL(txcmpl_ring->id), + IPQ6018_EDMA_TXCMPL_RETMODE_OPAQUE); + + txcmpl_ugt_thre = (low_thre & IPQ6018_EDMA_TXCMPL_LOW_THRE_MASK) << + IPQ6018_EDMA_TXCMPL_LOW_THRE_SHIFT; + + txcmpl_ugt_thre |= (txcmpl_fc_thre & IPQ6018_EDMA_TXCMPL_FC_THRE_MASK) + << IPQ6018_EDMA_TXCMPL_FC_THRE_SHIFT; + + ipq6018_edma_reg_write(IPQ6018_EDMA_REG_TXCMPL_UGT_THRE( + txcmpl_ring->id), txcmpl_ugt_thre); + + tx_mod_timer = (IPQ6018_EDMA_TX_MOD_TIMER & + IPQ6018_EDMA_TX_MOD_TIMER_INIT_MASK) << + IPQ6018_EDMA_TX_MOD_TIMER_INIT_SHIFT; + + ipq6018_edma_reg_write(IPQ6018_EDMA_REG_TX_MOD_TIMER(txcmpl_ring->id), + tx_mod_timer); + + ipq6018_edma_reg_write(IPQ6018_EDMA_REG_TX_INT_CTRL(txcmpl_ring->id), + 0x2); +} + +/* + * ipq6018_edma_configure_rxdesc_ring() + * Configure one RxDesc ring + */ +static void ipq6018_edma_configure_rxdesc_ring(struct ipq6018_edma_hw *ehw, + struct ipq6018_edma_rxdesc_ring *rxdesc_ring) +{ + uint32_t data; + + ipq6018_edma_reg_write(IPQ6018_EDMA_REG_RXDESC_BA(rxdesc_ring->id), + (uint32_t)(rxdesc_ring->dma & 0xffffffff)); + + data = rxdesc_ring->count & IPQ6018_EDMA_RXDESC_RING_SIZE_MASK; + data |= (ehw->rx_payload_offset & + IPQ6018_EDMA_RXDESC_PL_OFFSET_MASK) << + IPQ6018_EDMA_RXDESC_PL_OFFSET_SHIFT; + + ipq6018_edma_reg_write(IPQ6018_EDMA_REG_RXDESC_RING_SIZE( + rxdesc_ring->id), data); + + data = (IPQ6018_EDMA_RXDESC_XON_THRE & + IPQ6018_EDMA_RXDESC_FC_XON_THRE_MASK) << + IPQ6018_EDMA_RXDESC_FC_XON_THRE_SHIFT; + + data |= (IPQ6018_EDMA_RXDESC_XOFF_THRE & + IPQ6018_EDMA_RXDESC_FC_XOFF_THRE_MASK) << + IPQ6018_EDMA_RXDESC_FC_XOFF_THRE_SHIFT; + + ipq6018_edma_reg_write(IPQ6018_EDMA_REG_RXDESC_FC_THRE( + rxdesc_ring->id), data); + + data = (IPQ6018_EDMA_RXDESC_LOW_THRE & + IPQ6018_EDMA_RXDESC_LOW_THRE_MASK) << + IPQ6018_EDMA_RXDESC_LOW_THRE_SHIFT; + + ipq6018_edma_reg_write(IPQ6018_EDMA_REG_RXDESC_UGT_THRE( + rxdesc_ring->id), data); + + data = (IPQ6018_EDMA_RX_MOD_TIMER_INIT & + IPQ6018_EDMA_RX_MOD_TIMER_INIT_MASK) << + IPQ6018_EDMA_RX_MOD_TIMER_INIT_SHIFT; + + ipq6018_edma_reg_write(IPQ6018_EDMA_REG_RX_MOD_TIMER( + rxdesc_ring->id), data); + + /* + * Enable ring. Set ret mode to 'opaque'. + */ + ipq6018_edma_reg_write(IPQ6018_EDMA_REG_RX_INT_CTRL( + rxdesc_ring->id), 0x2); +} + +/* + * ipq6018_edma_configure_rxfill_ring() + * Configure one RxFill ring + */ +static void ipq6018_edma_configure_rxfill_ring(struct ipq6018_edma_hw *ehw, + struct ipq6018_edma_rxfill_ring *rxfill_ring) +{ + uint32_t rxfill_low_thre = (rxfill_ring->count / 4); + uint32_t rxfill_xon_thre = (rxfill_ring->count / 8); + uint32_t rxfill_xoff_thre = (rxfill_ring->count / 16); + uint32_t rxfill_fc_thre; + uint32_t rxfill_ugt_thre; + uint32_t data; + + ipq6018_edma_reg_write(IPQ6018_EDMA_REG_RXFILL_BA(rxfill_ring->id), + (uint32_t)(rxfill_ring->dma & IPQ6018_EDMA_RING_DMA_MASK)); + + data = rxfill_ring->count & IPQ6018_EDMA_RXFILL_RING_SIZE_MASK; + + ipq6018_edma_reg_write(IPQ6018_EDMA_REG_RXFILL_RING_SIZE(rxfill_ring->id), data); + + rxfill_fc_thre = (rxfill_xon_thre & IPQ6018_EDMA_RXFILL_FC_XON_THRE_MASK) + << IPQ6018_EDMA_RXFILL_FC_XON_THRE_SHIFT; + rxfill_fc_thre |= (rxfill_xoff_thre & IPQ6018_EDMA_RXFILL_FC_XOFF_THRE_MASK) + << IPQ6018_EDMA_RXFILL_FC_XOFF_THRE_SHIFT; + + ipq6018_edma_reg_write(IPQ6018_EDMA_REG_RXFILL_FC_THRE(rxfill_ring->id), + rxfill_fc_thre); + + rxfill_ugt_thre = (rxfill_low_thre & IPQ6018_EDMA_RXFILL_LOW_THRE_MASK) + << IPQ6018_EDMA_RXFILL_LOW_THRE_SHIFT; + + ipq6018_edma_reg_write(IPQ6018_EDMA_REG_RXFILL_UGT_THRE(rxfill_ring->id), + rxfill_ugt_thre); + +} + + +/* + * ipq6018_edma_configure_rings() + * Configure EDMA rings + */ +static void ipq6018_edma_configure_rings(struct ipq6018_edma_hw *ehw) +{ + int i; + + /* + * Configure TXDESC ring + */ + for (i = 0; i < ehw->txdesc_rings; i++) + ipq6018_edma_configure_txdesc_ring(ehw, &ehw->txdesc_ring[i]); + + /* + * Configure TXCMPL ring + */ + for (i = 0; i < ehw->txcmpl_rings; i++) + ipq6018_edma_configure_txcmpl_ring(ehw, &ehw->txcmpl_ring[i]); + + /* + * Configure RXFILL rings + */ + for (i = 0; i < ehw->rxfill_rings; i++) + ipq6018_edma_configure_rxfill_ring(ehw, &ehw->rxfill_ring[i]); + + /* + * Configure RXDESC ring + */ + for (i = 0; i < ehw->rxdesc_rings; i++) + ipq6018_edma_configure_rxdesc_ring(ehw, &ehw->rxdesc_ring[i]); + + pr_info("%s: successfull\n", __func__); +} + +/* + * ipq6018_edma_hw_reset() + * EDMA hw reset + */ +void ipq6018_edma_hw_reset(void) +{ + writel(GCC_EDMA_HW_RESET_ASSERT, GCC_NSS_PPE_RESET); + udelay(100); + writel(GCC_EDMA_HW_RESET_DEASSERT, GCC_NSS_PPE_RESET); + udelay(100); +} + +/* + * ipq6018_edma_hw_init() + * EDMA hw init + */ +int ipq6018_edma_hw_init(struct ipq6018_edma_hw *ehw) +{ + int ret, desc_index; + uint32_t i, reg; + volatile uint32_t data; + + struct ipq6018_edma_rxdesc_ring *rxdesc_ring = NULL; + + ipq6018_ppe_provision_init(); + + data = ipq6018_edma_reg_read(IPQ6018_EDMA_REG_MAS_CTRL); + printf("EDMA ver %d hw init\n", data); + + /* + * Setup private data structure + */ + ehw->rxfill_intr_mask = IPQ6018_EDMA_RXFILL_INT_MASK; + ehw->rxdesc_intr_mask = IPQ6018_EDMA_RXDESC_INT_MASK_PKT_INT; + ehw->txcmpl_intr_mask = IPQ6018_EDMA_TX_INT_MASK_PKT_INT | + IPQ6018_EDMA_TX_INT_MASK_UGT_INT; + ehw->misc_intr_mask = 0; + ehw->rx_payload_offset = IPQ6018_EDMA_RX_PREHDR_SIZE; + + /* + * Reset EDMA + */ + ipq6018_edma_hw_reset(); + + /* + * Disable interrupts + */ + ipq6018_edma_disable_intr(ehw); + + /* + * Disable rings + */ + ipq6018_edma_disable_rings(ehw); + + ret = ipq6018_edma_init_rings(ehw); + + if (ret) + return ret; + + ipq6018_edma_configure_rings(ehw); + + /* + * Set PPE QID to EDMA Rx ring mapping. + * When coming up use only queue 0. + * HOST EDMA rings. FW EDMA comes up and overwrites as required. + * Each entry can hold mapping for 8 PPE queues and entry size is + * 4 bytes + */ + desc_index = ehw->rxdesc_ring_start; + reg = IPQ6018_EDMA_QID2RID_TABLE_MEM(0); + data = 0; + data |= (desc_index & 0xF); + ipq6018_edma_reg_write(reg, data); + pr_debug("Configure QID2RID reg:0x%x to 0x%x\n", reg, data); + + /* + * Set RXDESC2FILL_MAP_xx reg. + * There are two registers RXDESC2FILL_0 and RXDESC2FILL_1 + * 3 bits holds the rx fill ring mapping for each of the + * rx descriptor ring. + */ + ipq6018_edma_reg_write(IPQ6018_EDMA_REG_RXDESC2FILL_MAP_0, 0); + ipq6018_edma_reg_write(IPQ6018_EDMA_REG_RXDESC2FILL_MAP_1, 0); + + for (i = ehw->rxdesc_ring_start; + i < ehw->rxdesc_ring_end; i++) { + if ((i >= 0) && (i <= 9)) + reg = IPQ6018_EDMA_REG_RXDESC2FILL_MAP_0; + else + reg = IPQ6018_EDMA_REG_RXDESC2FILL_MAP_1; + + rxdesc_ring = &ehw->rxdesc_ring[i - ehw->rxdesc_ring_start]; + + pr_debug("Configure RXDESC:%u to use RXFILL:%u\n", + rxdesc_ring->id, rxdesc_ring->rxfill->id); + + data = ipq6018_edma_reg_read(reg); + data |= (rxdesc_ring->rxfill->id & 0x7) << ((i % 10) * 3); + ipq6018_edma_reg_write(reg, data); + } + + reg = IPQ6018_EDMA_REG_RXDESC2FILL_MAP_0; + pr_debug("EDMA_REG_RXDESC2FILL_MAP_0: 0x%x\n", + ipq6018_edma_reg_read(reg)); + reg = IPQ6018_EDMA_REG_RXDESC2FILL_MAP_1; + pr_debug("EDMA_REG_RXDESC2FILL_MAP_1: 0x%x\n", + ipq6018_edma_reg_read(reg)); + + /* + * Enable EDMA + */ + ipq6018_edma_reg_write(IPQ6018_EDMA_REG_PORT_CTRL, + IPQ6018_EDMA_PORT_CTRL_EN); + + /* + * Enable Rx rings + */ + for (i = ehw->rxdesc_ring_start; i < ehw->rxdesc_ring_end; i++) { + data = ipq6018_edma_reg_read(IPQ6018_EDMA_REG_RXDESC_CTRL(i)); + data |= IPQ6018_EDMA_RXDESC_RX_EN; + ipq6018_edma_reg_write(IPQ6018_EDMA_REG_RXDESC_CTRL(i), data); + } + + for (i = ehw->rxfill_ring_start; i < ehw->rxfill_ring_end; i++) { + data = ipq6018_edma_reg_read(IPQ6018_EDMA_REG_RXFILL_RING_EN(i)); + data |= IPQ6018_EDMA_RXFILL_RING_EN; + ipq6018_edma_reg_write(IPQ6018_EDMA_REG_RXFILL_RING_EN(i), data); + } + + /* + * Enable Tx rings + */ + for (i = ehw->txdesc_ring_start; i < ehw->txdesc_ring_end; i++) { + data = ipq6018_edma_reg_read(IPQ6018_EDMA_REG_TXDESC_CTRL(i)); + data |= IPQ6018_EDMA_TXDESC_TX_EN; + ipq6018_edma_reg_write(IPQ6018_EDMA_REG_TXDESC_CTRL(i), data); + } + + /* + * Enable MISC interrupt + */ + ipq6018_edma_reg_write(IPQ6018_EDMA_REG_MISC_INT_MASK, + ehw->misc_intr_mask); + + pr_info("%s: successfull\n", __func__); + return 0; +} + +void get_phy_address(int offset) +{ + int phy_type; + int phy_address; + int i; + + for (i = 0; i < IPQ6018_PHY_MAX; i++) + phy_info[i] = ipq6018_alloc_mem(sizeof(phy_info_t)); + i = 0; + for (offset = fdt_first_subnode(gd->fdt_blob, offset); offset > 0; + offset = fdt_next_subnode(gd->fdt_blob, offset)) { + + phy_address = fdtdec_get_uint(gd->fdt_blob, + offset, "phy_address", 0); + phy_type = fdtdec_get_uint(gd->fdt_blob, + offset, "phy_type", 0); + phy_info[i]->phy_address = phy_address; + phy_info[i++]->phy_type = phy_type; + } +} + +int ipq6018_edma_init(void *edma_board_cfg) +{ + struct eth_device *dev[IPQ6018_EDMA_DEV]; + struct ipq6018_edma_common_info *c_info[IPQ6018_EDMA_DEV]; + struct ipq6018_edma_hw *hw[IPQ6018_EDMA_DEV]; + uchar enet_addr[IPQ6018_EDMA_DEV * 6]; + int i, phy_id; + uint32_t phy_chip_id, phy_chip_id1, phy_chip_id2; + int ret = -1; + ipq6018_edma_board_cfg_t ledma_cfg, *edma_cfg; + static int sw_init_done = 0; + int port_8033 = -1, node, phy_addr, aquantia_port = -1; + int mode, phy_node = -1; + + node = fdt_path_offset(gd->fdt_blob, "/ess-switch"); + if (node >= 0) + port_8033 = fdtdec_get_uint(gd->fdt_blob, node, "8033_port", -1); + + if (node >= 0) + aquantia_port = fdtdec_get_uint(gd->fdt_blob, node, "aquantia_port", -1); + + phy_node = fdt_path_offset(gd->fdt_blob, "/ess-switch/port_phyinfo"); + if (phy_node >= 0) + get_phy_address(phy_node); + + mode = fdtdec_get_uint(gd->fdt_blob, node, "switch_mac_mode", -1); + if (mode < 0) { + printf("Error: switch_mac_mode not specified in dts"); + return mode; + } + + memset(c_info, 0, (sizeof(c_info) * IPQ6018_EDMA_DEV)); + memset(enet_addr, 0, sizeof(enet_addr)); + memset(&ledma_cfg, 0, sizeof(ledma_cfg)); + edma_cfg = &ledma_cfg; + strlcpy(edma_cfg->phy_name, "IPQ MDIO0", sizeof(edma_cfg->phy_name)); + + /* Getting the MAC address from ART partition */ + ret = get_eth_mac_address(enet_addr, IPQ6018_EDMA_DEV); + + /* + * Register EDMA as single ethernet + * interface. + */ + for (i = 0; i < IPQ6018_EDMA_DEV; edma_cfg++, i++) { + dev[i] = ipq6018_alloc_mem(sizeof(struct eth_device)); + + if (!dev[i]) + goto init_failed; + + memset(dev[i], 0, sizeof(struct eth_device)); + + c_info[i] = ipq6018_alloc_mem( + sizeof(struct ipq6018_edma_common_info)); + + if (!c_info[i]) + goto init_failed; + + memset(c_info[i], 0, + sizeof(struct ipq6018_edma_common_info)); + + hw[i] = &c_info[i]->hw; + + c_info[i]->hw.hw_addr = (unsigned long __iomem *) + IPQ6018_EDMA_CFG_BASE; + + ipq6018_edma_dev[i] = ipq6018_alloc_mem( + sizeof(struct ipq6018_eth_dev)); + + if (!ipq6018_edma_dev[i]) + goto init_failed; + + memset (ipq6018_edma_dev[i], 0, + sizeof(struct ipq6018_eth_dev)); + + dev[i]->iobase = IPQ6018_EDMA_CFG_BASE; + dev[i]->init = ipq6018_eth_init; + dev[i]->halt = ipq6018_eth_halt; + dev[i]->recv = ipq6018_eth_recv; + dev[i]->send = ipq6018_eth_snd; + dev[i]->write_hwaddr = ipq6018_edma_wr_macaddr; + dev[i]->priv = (void *)ipq6018_edma_dev[i]; + + if ((ret < 0) || + (!is_valid_ethaddr(&enet_addr[edma_cfg->unit * 6]))) { + memcpy(&dev[i]->enetaddr[0], ipq6018_def_enetaddr, 6); + } else { + memcpy(&dev[i]->enetaddr[0], + &enet_addr[edma_cfg->unit * 6], 6); + } + + printf("MAC%x addr:%x:%x:%x:%x:%x:%x\n", + edma_cfg->unit, dev[i]->enetaddr[0], + dev[i]->enetaddr[1], + dev[i]->enetaddr[2], + dev[i]->enetaddr[3], + dev[i]->enetaddr[4], + dev[i]->enetaddr[5]); + + snprintf(dev[i]->name, sizeof(dev[i]->name), "eth%d", i); + + ipq6018_edma_dev[i]->dev = dev[i]; + ipq6018_edma_dev[i]->mac_unit = edma_cfg->unit; + ipq6018_edma_dev[i]->c_info = c_info[i]; + ipq6018_edma_hw_addr = IPQ6018_EDMA_CFG_BASE; + + ret = ipq_sw_mdio_init(edma_cfg->phy_name); + if (ret) + goto init_failed; + + for (phy_id = 0; phy_id < IPQ6018_PHY_MAX; phy_id++) { + if (phy_node >= 0) { + phy_addr = phy_info[phy_id]->phy_address; + } else { + if (phy_id == port_8033) + phy_addr = QCA8033_PHY_ADDR; + else if (phy_id == aquantia_port) + phy_addr = AQU_PHY_ADDR; + else + phy_addr = phy_id; + } + + phy_chip_id1 = ipq_mdio_read(phy_addr, QCA_PHY_ID1, NULL); + phy_chip_id2 = ipq_mdio_read(phy_addr, QCA_PHY_ID2, NULL); + phy_chip_id = (phy_chip_id1 << 16) | phy_chip_id2; + if (phy_id == aquantia_port) { + phy_chip_id1 = ipq_mdio_read(phy_addr, (1<<30) |(1<<16) | QCA_PHY_ID1, NULL); + phy_chip_id2 = ipq_mdio_read(phy_addr, (1<<30) |(1<<16) | QCA_PHY_ID2, NULL); + phy_chip_id = (phy_chip_id1 << 16) | phy_chip_id2; + } + switch(phy_chip_id) { + case QCA8075_PHY_V1_0_5P: + case QCA8075_PHY_V1_1_5P: + case QCA8075_PHY_V1_1_2P: + + if (!sw_init_done) { + if (ipq_qca8075_phy_init(&ipq6018_edma_dev[i]->ops[phy_id]) == 0) { + sw_init_done = 1; + } + } else { + ipq_qca8075_phy_map_ops(&ipq6018_edma_dev[i]->ops[phy_id]); + } + + if (mode == PORT_WRAPPER_PSGMII) + qca8075_phy_interface_set_mode(0x0, 0x0); + else if ( mode == PORT_WRAPPER_QSGMII) + qca8075_phy_interface_set_mode(0x0, 0x4); + break; +#ifdef CONFIG_QCA8033_PHY + case QCA8033_PHY: + ipq_qca8033_phy_init(&ipq6018_edma_dev[i]->ops[phy_id], phy_addr); + break; +#endif +#ifdef CONFIG_QCA8081_PHY + case QCA8081_PHY: + case QCA8081_1_1_PHY: + ipq_qca8081_phy_init(&ipq6018_edma_dev[i]->ops[phy_id], phy_addr); + break; +#endif +#ifdef CONFIG_IPQ6018_QCA_AQUANTIA_PHY + case AQUANTIA_PHY_107: + case AQUANTIA_PHY_109: + case AQUANTIA_PHY_111: + case AQUANTIA_PHY_112: + case AQUANTIA_PHY_111B0: + case AQUANTIA_PHY_112C: + ipq_board_fw_download(phy_addr); + ipq_qca_aquantia_phy_init(&ipq6018_edma_dev[i]->ops[phy_id], phy_addr); + break; +#endif + default: + ipq_qca8075_phy_map_ops(&ipq6018_edma_dev[i]->ops[phy_id]); + break; + } + } + + ret = ipq6018_edma_hw_init(hw[i]); + + if (ret) + goto init_failed; + + eth_register(dev[i]); + } + + return 0; + +init_failed: + printf("Error in allocating Mem\n"); + + for (i = 0; i < IPQ6018_EDMA_DEV; i++) { + if (dev[i]) { + eth_unregister(dev[i]); + ipq6018_free_mem(dev[i]); + } + if (c_info[i]) { + ipq6018_edma_free_desc(c_info[i]); + ipq6018_edma_free_rings(c_info[i]); + ipq6018_free_mem(c_info[i]); + } + if (ipq6018_edma_dev[i]) { + ipq6018_free_mem(ipq6018_edma_dev[i]); + } + } + + return -1; +} diff --git a/sources/uboot-be550/drivers/net/ipq6018/ipq6018_edma.h b/sources/uboot-be550/drivers/net/ipq6018/ipq6018_edma.h new file mode 100644 index 00000000..cb051793 --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq6018/ipq6018_edma.h @@ -0,0 +1,327 @@ +/* + ************************************************************************** + * Copyright (c) 2016-2019 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT + * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + ************************************************************************** +*/ +#ifndef __IPQ6018_EDMA__ +#define __IPQ6018_EDMA__ + +#define IPQ6018_NSS_DP_START_PHY_PORT 1 +#define IPQ6018_NSS_DP_MAX_PHY_PORTS 5 + +#define IPQ6018_EDMA_BUF_SIZE 2000 +#define IPQ6018_EDMA_DEVICE_NODE_NAME "edma" +#define IPQ6018_EDMA_RX_BUFF_SIZE (IPQ6018_EDMA_BUF_SIZE + IPQ6018_EDMA_RX_PREHDR_SIZE) +#define IPQ6018_EDMA_RX_PREHDR_SIZE (sizeof(struct ipq6018_edma_rx_preheader)) +#define IPQ6018_EDMA_TX_PREHDR_SIZE (sizeof(struct ipq6018_edma_tx_preheader)) + +#define IPQ6018_EDMA_TXDESC_RING_SIZE 8 +#define IPQ6018_EDMA_TXCMPL_RING_SIZE 8 +#define IPQ6018_EDMA_RXDESC_RING_SIZE 16 +#define IPQ6018_EDMA_RXFILL_RING_SIZE 16 + +#define IPQ6018_EDMA_START_GMACS IPQ6018_NSS_DP_START_PHY_PORT +#define IPQ6018_EDMA_MAX_GMACS IPQ6018_NSS_DP_MAX_PHY_PORTS +#define IPQ6018_EDMA_TX_BUF_SIZE (1540 + IPQ6018_EDMA_TX_PREHDR_SIZE) + +#define IPQ6018_EDMA_MAX_TXCMPL_RINGS 24 /* Max TxCmpl rings */ +#define IPQ6018_EDMA_MAX_RXDESC_RINGS 16 /* Max RxDesc rings */ +#define IPQ6018_EDMA_MAX_RXFILL_RINGS 8 /* Max RxFill rings */ +#define IPQ6018_EDMA_MAX_TXDESC_RINGS 24 /* Max TxDesc rings */ + +#define IPQ6018_EDMA_GET_DESC(R, i, type) (&(((type *)((R)->desc))[i])) +#define IPQ6018_EDMA_RXFILL_DESC(R, i) IPQ6018_EDMA_GET_DESC(R, i, struct ipq6018_edma_rxfill_desc) +#define IPQ6018_EDMA_RXDESC_DESC(R, i) IPQ6018_EDMA_GET_DESC(R, i, struct ipq6018_edma_rxdesc_desc) +#define IPQ6018_EDMA_TXDESC_DESC(R, i) IPQ6018_EDMA_GET_DESC(R, i, struct ipq6018_edma_txdesc_desc) +#define IPQ6018_EDMA_TXCMPL_DESC(R, i) IPQ6018_EDMA_GET_DESC(R, i, struct ipq6018_edma_txcmpl_desc) +#define IPQ6018_EDMA_RXPH_SRC_INFO_TYPE_GET(rxph) (((rxph)->src_info >> 8) & 0xf0) + +#define IPQ6018_EDMA_DEV 1 +#define IPQ6018_EDMA_TX_QUEUE 1 +#define IPQ6018_EDMA_RX_QUEUE 1 + +#define IPQ6018_EDMA_TX_DESC_RING_START 0 +#define IPQ6018_EDMA_TX_DESC_RING_NOS 1 +#define IPQ6018_EDMA_TX_DESC_RING_SIZE \ +(IPQ6018_EDMA_TX_DESC_RING_START + IPQ6018_EDMA_TX_DESC_RING_NOS) + +#define IPQ6018_EDMA_TX_CMPL_RING_START 0 +#define IPQ6018_EDMA_TX_CMPL_RING_NOS 8 +#define IPQ6018_EDMA_TX_CMPL_RING_SIZE \ +(IPQ6018_EDMA_TX_CMPL_RING_START + IPQ6018_EDMA_TX_CMPL_RING_NOS) + +#define IPQ6018_EDMA_RX_DESC_RING_START 15 +#define IPQ6018_EDMA_RX_DESC_RING_NOS 1 +#define IPQ6018_EDMA_RX_DESC_RING_SIZE \ +(IPQ6018_EDMA_RX_DESC_RING_START + IPQ6018_EDMA_RX_DESC_RING_NOS) + +#define IPQ6018_EDMA_RX_FILL_RING_START 7 +#define IPQ6018_EDMA_RX_FILL_RING_NOS 1 +#define IPQ6018_EDMA_RX_FILL_RING_SIZE \ +(IPQ6018_EDMA_RX_FILL_RING_START + IPQ6018_EDMA_RX_FILL_RING_NOS) + +#define IPQ6018_EDMA_TX_IMR_NORMAL_MASK 1 +#define IPQ6018_EDMA_RX_IMR_NORMAL_MASK 1 +#define IPQ6018_EDMA_INTR_CLEAR_TYPE 0 +#define IPQ6018_EDMA_INTR_SW_IDX_W_TYPE 0 +#define IPQ6018_EDMA_RSS_TYPE_NONE 0x1 + +#define NETDEV_TX_BUSY 1 + +#define PSGMIIPHY_PLL_VCO_RELATED_CTRL 0x0009878c +#define PSGMIIPHY_PLL_VCO_VAL 0x2803 + +#define PSGMIIPHY_VCO_CALIBRATION_CTRL 0x0009809c +#define PSGMIIPHY_VCO_VAL 0x4ADA +#define PSGMIIPHY_VCO_RST_VAL 0xADA + +#define RGMII_TCSR_ESS_CFG 0x01953000 +#define ESS_RGMII_CTRL 0x0C000004 +/* + * Tx descriptor + */ +struct ipq6018_edma_txdesc_desc { + uint32_t buffer_addr; + /* buffer address */ + uint32_t word1; + /* more bit, TSO, preheader, pool, offset and length */ +}; + +/* + * TxCmpl descriptor + */ +struct ipq6018_edma_txcmpl_desc { + uint32_t buffer_addr; /* buffer address/opaque */ + uint32_t status; /* status */ +}; + +/* + * Rx descriptor + */ +struct ipq6018_edma_rxdesc_desc { + uint32_t buffer_addr; /* buffer address */ + uint32_t status; /* status */ +}; + +/* + * RxFill descriptor + */ +struct ipq6018_edma_rxfill_desc { + uint32_t buffer_addr; /* Buffer address */ + uint32_t word1; /* opaque_ind and buffer size */ +}; + +/* + * Tx descriptor ring + */ +struct ipq6018_edma_txdesc_ring { + uint32_t id; /* TXDESC ring number */ + void *desc; /* descriptor ring virtual address */ + dma_addr_t dma; /* descriptor ring physical address */ + uint16_t count; /* number of descriptors */ +}; + +/* + * TxCmpl ring + */ +struct ipq6018_edma_txcmpl_ring { + uint32_t id; /* TXCMPL ring number */ + void *desc; /* descriptor ring virtual address */ + dma_addr_t dma; /* descriptor ring physical address */ + uint16_t count; /* number of descriptors in the ring */ +}; + +/* + * RxFill ring + */ +struct ipq6018_edma_rxfill_ring { + uint32_t id; /* RXFILL ring number */ + void *desc; /* descriptor ring virtual address */ + dma_addr_t dma; /* descriptor ring physical address */ + uint16_t count; /* number of descriptors in the ring */ +}; + +/* + * RxDesc ring + */ +struct ipq6018_edma_rxdesc_ring { + uint32_t id; /* RXDESC ring number */ + struct ipq6018_edma_rxfill_ring *rxfill; /* RXFILL ring used */ + void *desc; /* descriptor ring virtual address */ + dma_addr_t dma; /* descriptor ring physical address */ + uint16_t count; /* number of descriptors in the ring */ +}; + +/* + * EDMA Tx Preheader + */ +struct ipq6018_edma_tx_preheader { + uint32_t opaque; /* Opaque, contains skb pointer */ + uint16_t src_info; /* Src information */ + uint16_t dst_info; /* Dest information */ + uint32_t tx_pre2; /* SVLAN & CVLAN flag, drop prec, hash value */ + uint32_t tx_pre3; /* STAG, CTAG */ + uint32_t tx_pre4; /* CPU code, L3 & L4 offset, service code */ + uint32_t tx_pre5; /* IP addr index, ACL index */ + uint32_t tx_pre6; /* IP payload checksum, copy2cpu, timestamp, dscp */ + uint32_t tx_pre7; /* Timestamp, QoS TAG */ +}; + +/* + * EDMA Rx Preheader + */ +struct ipq6018_edma_rx_preheader { + uint32_t opaque; /* Opaque, contains skb pointer*/ + uint16_t src_info; /* Src information */ + uint16_t dst_info; /* Dest information */ + uint32_t rx_pre2; /* SVLAN & CVLAN flag, drop prec, hash value */ + uint32_t rx_pre3; /* STAG, CTAG */ + uint32_t rx_pre4; /* CPU code, L3 & L4 offset, service code */ + uint32_t rx_pre5; /* IP addr index, ACL index */ + uint32_t rx_pre6; /* IP payload checksum, copy2cpu, timestamp, dscp */ + uint32_t rx_pre7; /* Timestamp, QoS TAG */ +}; + +enum ipq6018_edma_tx { + EDMA_TX_OK = 0, /* Tx success */ + EDMA_TX_DESC = 1, /* Not enough descriptors */ + EDMA_TX_FAIL = 2, /* Tx failure */ +}; + + +/* per core queue related information */ +struct queue_per_cpu_info { + u32 tx_mask; /* tx interrupt mask */ + u32 rx_mask; /* rx interrupt mask */ + u32 tx_status; /* tx interrupt status */ + u32 rx_status; /* rx interrupt status */ + u32 tx_start; /* tx queue start */ + u32 rx_start; /* rx queue start */ + struct ipq6018_edma_common_info *c_info; /* edma common info */ +}; + +/* edma hw specific data */ +struct ipq6018_edma_hw { + unsigned long __iomem *hw_addr; /* inner register address */ + u8 intr_clear_type; /* interrupt clear */ + u8 intr_sw_idx_w; /* To do chk type interrupt software index */ + u16 rx_buff_size; /* To do chk type Rx buffer size */ + u8 rss_type; /* rss protocol type */ + uint16_t rx_payload_offset; /* start of the payload offset */ + uint32_t flags; /* internal flags */ + int active; /* status */ + struct ipq6018_edma_txdesc_ring *txdesc_ring; /* Tx Descriptor Ring, SW is producer */ + struct ipq6018_edma_txcmpl_ring *txcmpl_ring; /* Tx Completion Ring, SW is consumer */ + struct ipq6018_edma_rxdesc_ring *rxdesc_ring; /* Rx Descriptor Ring, SW is consumer */ + struct ipq6018_edma_rxfill_ring *rxfill_ring; /* Rx Fill Ring, SW is producer */ + uint32_t txdesc_rings; /* Number of TxDesc rings */ + uint32_t txdesc_ring_start; /* Id of first TXDESC ring */ + uint32_t txdesc_ring_end; /* Id of the last TXDESC ring */ + uint32_t txcmpl_rings; /* Number of TxCmpl rings */ + uint32_t txcmpl_ring_start; /* Id of first TXCMPL ring */ + uint32_t txcmpl_ring_end; /* Id of last TXCMPL ring */ + uint32_t rxfill_rings; /* Number of RxFill rings */ + uint32_t rxfill_ring_start; /* Id of first RxFill ring */ + uint32_t rxfill_ring_end; /* Id of last RxFill ring */ + uint32_t rxdesc_rings; /* Number of RxDesc rings */ + uint32_t rxdesc_ring_start; /* Id of first RxDesc ring */ + uint32_t rxdesc_ring_end; /* Id of last RxDesc ring */ + uint32_t tx_intr_mask; /* tx interrupt mask */ + uint32_t rx_intr_mask; /* rx interrupt mask */ + uint32_t rxfill_intr_mask; /* Rx fill ring interrupt mask */ + uint32_t rxdesc_intr_mask; /* Rx Desc ring interrupt mask */ + uint32_t txcmpl_intr_mask; /* Tx Cmpl ring interrupt mask */ + uint32_t misc_intr_mask; /* misc interrupt interrupt mask */ +}; + +struct ipq6018_edma_common_info { + struct ipq6018_edma_hw hw; +}; + +#define MAX_PHY 6 +struct ipq6018_eth_dev { + u8 *phy_address; + uint no_of_phys; + uint interface; + uint speed; + uint duplex; + uint sw_configured; + uint mac_unit; + uint mac_ps; + int link_printed; + u32 padding; + struct eth_device *dev; + struct ipq6018_edma_common_info *c_info; + struct phy_ops *ops[MAX_PHY]; + const char phy_name[MDIO_NAME_LEN]; +} __attribute__ ((aligned(8))); + +static inline void* ipq6018_alloc_mem(u32 size) +{ + void *p = malloc(size); + if (p != NULL) + memset(p, 0, size); + return p; +} + +static inline void* ipq6018_alloc_memalign(u32 size) +{ + void *p = memalign(CONFIG_SYS_CACHELINE_SIZE, size); + if (p != NULL) + memset(p, 0, size); + return p; +} + +static inline void ipq6018_free_mem(void *ptr) +{ + if (ptr) + free(ptr); +} + +uint32_t ipq6018_edma_reg_read(uint32_t reg_off); +void ipq6018_edma_reg_write(uint32_t reg_off, uint32_t val); + + +extern int get_eth_mac_address(uchar *enetaddr, uint no_of_macs); + +typedef struct { + uint count; + u8 addr[7]; +} ipq6018_edma_phy_addr_t; + +/* ipq6018 edma Paramaters */ +typedef struct { + uint base; + int unit; + uint mac_conn_to_phy; + phy_interface_t phy; + ipq6018_edma_phy_addr_t phy_addr; + char phy_name[MDIO_NAME_LEN]; +} ipq6018_edma_board_cfg_t; + +extern void ipq6018_ppe_provision_init(void); +extern void ipq6018_port_mac_clock_reset(int port); +extern void ipq6018_speed_clock_set(int port, int speed_clock1, int speed_clock2); +extern void ipq6018_gmac_port_disable(int port); +extern void ipq6018_pqsgmii_speed_set(int port, int speed, int status); +extern void ipq6018_uxsgmii_speed_set(int port, int speed, int duplex, int status); +extern void ppe_port_mux_mac_type_set(int port_id, int mode); +extern void ppe_port_bridge_txmac_set(int port, int status); +extern void ipq6018_10g_r_speed_set(int port, int status); +extern int phy_status_get_from_ppe(int port_id); + +extern void ipq6018_ppe_acl_set(int rule_id, int rule_type, int pkt_type, int l4_port_no, int l4_port_mask, int permit, int deny); +extern void ppe_uniphy_mode_set(uint32_t uniphy_index, uint32_t mode); +#endif /* ___IPQ6018_EDMA__ */ diff --git a/sources/uboot-be550/drivers/net/ipq6018/ipq6018_ppe.c b/sources/uboot-be550/drivers/net/ipq6018/ipq6018_ppe.c new file mode 100644 index 00000000..6c49b228 --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq6018/ipq6018_ppe.c @@ -0,0 +1,1352 @@ +/* + ************************************************************************** + * Copyright (c) 2016-2019 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT + * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + ************************************************************************** + */ + +#include +#include +#include "ipq6018_ppe.h" +#include "ipq6018_uniphy.h" +#include +#include "ipq_phy.h" + +DECLARE_GLOBAL_DATA_PTR; +#define pr_info(fmt, args...) printf(fmt, ##args); +/* + * ipq6018_ppe_gpio_reg_write() + */ +static inline void ipq6018_ppe_gpio_reg_write(u32 reg, u32 val) +{ + writel(val, IPQ6018_PPE_FPGA_GPIO_BASE_ADDR + reg); +} + +/* + * ipq6018_ppe_reg_read() + */ +static inline void ipq6018_ppe_reg_read(u32 reg, u32 *val) +{ + *val = readl((void *)(IPQ6018_PPE_BASE_ADDR + reg)); +} + +/* + * ipq6018_ppe_reg_write() + */ +static inline void ipq6018_ppe_reg_write(u32 reg, u32 val) +{ + writel(val, (void *)(IPQ6018_PPE_BASE_ADDR + reg)); +} + +void ppe_ipo_rule_reg_set(union ipo_rule_reg_u *hw_reg, int rule_id) +{ + int i; + + for (i = 0; i < 3; i++) { + ipq6018_ppe_reg_write(IPO_CSR_BASE_ADDR + IPO_RULE_REG_ADDRESS + + (rule_id * IPO_RULE_REG_INC) + (i * 4), hw_reg->val[i]); + } +} + +void ppe_ipo_mask_reg_set(union ipo_mask_reg_u *hw_mask, int rule_id) +{ + int i; + + for (i = 0; i < 2; i++) { + ipq6018_ppe_reg_write((IPO_CSR_BASE_ADDR + IPO_MASK_REG_ADDRESS + + (rule_id * IPO_MASK_REG_INC) + (i * 4)), hw_mask->val[i]); + } +} + +void ppe_ipo_action_set(union ipo_action_u *hw_act, int rule_id) +{ + int i; + + for (i = 0; i < 5; i++) { + ipq6018_ppe_reg_write((IPE_L2_BASE_ADDR + IPO_ACTION_ADDRESS + + (rule_id * IPO_ACTION_INC) + (i * 4)), hw_act->val[i]); + } +} + +void ipq6018_ppe_acl_set(int rule_id, int rule_type, int pkt_type, int l4_port_no, int l4_port_mask, int permit, int deny) +{ + union ipo_rule_reg_u hw_reg = {0}; + union ipo_mask_reg_u hw_mask = {0}; + union ipo_action_u hw_act = {0}; + + memset(&hw_reg, 0, sizeof(hw_reg)); + memset(&hw_mask, 0, sizeof(hw_mask)); + memset(&hw_act, 0, sizeof(hw_act)); + + if (rule_id < MAX_RULE) { + if (rule_type == ADPT_ACL_HPPE_IPV4_DIP_RULE) { + hw_reg.bf.rule_type = ADPT_ACL_HPPE_IPV4_DIP_RULE; + hw_reg.bf.rule_field_0 = l4_port_no; + hw_reg.bf.rule_field_1 = pkt_type<<17; + hw_mask.bf.maskfield_0 = l4_port_mask; + hw_mask.bf.maskfield_1 = 7<<17; + if (permit == 0x0) { + hw_act.bf.dest_info_change_en = 1; + hw_act.bf.fwd_cmd = 0;/*forward*/ + hw_reg.bf.pri = 0x1; + } + + if (deny == 0x1) { + hw_act.bf.dest_info_change_en = 1; + hw_act.bf.fwd_cmd = 1;/*drop*/ + hw_reg.bf.pri = 0x0; + + } + hw_reg.bf.src_0 = 0x6; + hw_reg.bf.src_1 = 0x7; + ppe_ipo_rule_reg_set(&hw_reg, rule_id); + ppe_ipo_mask_reg_set(&hw_mask, rule_id); + ppe_ipo_action_set(&hw_act, rule_id); + } + } +} + +/* + * ipq6018_ppe_vp_port_tbl_set() + */ +static void ipq6018_ppe_vp_port_tbl_set(int port, int vsi) +{ + u32 addr = IPQ6018_PPE_L3_VP_PORT_TBL_ADDR + + (port * IPQ6018_PPE_L3_VP_PORT_TBL_INC); + ipq6018_ppe_reg_write(addr, 0x0); + ipq6018_ppe_reg_write(addr + 0x4 , 1 << 9 | vsi << 10); + ipq6018_ppe_reg_write(addr + 0x8, 0x0); +} + +/* + * ipq6018_ppe_ucast_queue_map_tbl_queue_id_set() + */ +static void ipq6018_ppe_ucast_queue_map_tbl_queue_id_set(int queue, int port) +{ + uint32_t val; + + ipq6018_ppe_reg_read(IPQ6018_PPE_QM_UQM_TBL + + (port * IPQ6018_PPE_UCAST_QUEUE_MAP_TBL_INC), &val); + + val |= queue << 4; + + ipq6018_ppe_reg_write(IPQ6018_PPE_QM_UQM_TBL + + (port * IPQ6018_PPE_UCAST_QUEUE_MAP_TBL_INC), val); +} + +/* + * ipq6018_vsi_setup() + */ +static void ipq6018_vsi_setup(int vsi, uint8_t group_mask) +{ + uint32_t val = (group_mask << 24 | group_mask << 16 | group_mask << 8 + | group_mask); + + /* Set mask */ + ipq6018_ppe_reg_write(0x061800 + (vsi * 0x10), val); + + /* new addr lrn en | station move lrn en */ + ipq6018_ppe_reg_write(0x061804 + (vsi * 0x10), 0x9); +} + +/* + * ipq6018_gmac_port_disable() + */ +void ipq6018_gmac_port_disable(int port) +{ + ipq6018_ppe_reg_write(IPQ6018_PPE_MAC_ENABLE + (0x200 * port), 0x70); + ipq6018_ppe_reg_write(IPQ6018_PPE_MAC_SPEED + (0x200 * port), 0x2); + ipq6018_ppe_reg_write(IPQ6018_PPE_MAC_MIB_CTL + (0x200 * port), 0x1); +} + +/* + * ipq6018_port_mac_clock_reset() + */ +void ipq6018_port_mac_clock_reset(int port) +{ + switch(port) { + case 0: + writel(NSS_PORT1_ASSERT, GCC_NSS_PPE_RESET); + mdelay(150); + writel(PPE_DEASSERT, GCC_NSS_PPE_RESET); + break; + case 1: + writel(NSS_PORT2_ASSERT, GCC_NSS_PPE_RESET); + mdelay(150); + writel(PPE_DEASSERT, GCC_NSS_PPE_RESET); + break; + case 2: + writel(NSS_PORT3_ASSERT, GCC_NSS_PPE_RESET); + mdelay(150); + writel(PPE_DEASSERT, GCC_NSS_PPE_RESET); + break; + case 3: + writel(NSS_PORT4_ASSERT, GCC_NSS_PPE_RESET); + mdelay(150); + writel(PPE_DEASSERT, GCC_NSS_PPE_RESET); + break; + case 4: + writel(NSS_PORT5_ASSERT, GCC_NSS_PPE_RESET); + mdelay(150); + writel(PPE_DEASSERT, GCC_NSS_PPE_RESET); + break; + } +} + +void ipq6018_speed_clock_set(int port, int speed_clock1, int speed_clock2) +{ + int i; + uint32_t reg_value; + + for (i = 0; i < 2; i++) + { + /* gcc port first clock divider */ + reg_value = 0; + reg_value = readl(GCC_NSS_PORT1_RX_CFG_RCGR + i*8 + port*0x10); + reg_value &= ~0x71f; + reg_value |= speed_clock1; + writel(reg_value, GCC_NSS_PORT1_RX_CFG_RCGR + i*8 + port*0x10); + /* gcc port second clock divider */ + reg_value = 0; + reg_value = readl(GCC_NSS_PORT1_RX_MISC + i*4 + port*0x10); + reg_value &= ~0xf; + reg_value |= speed_clock2; + writel(reg_value, GCC_NSS_PORT1_RX_MISC + i*4 + port*0x10); + /* update above clock configuration */ + reg_value = 0; + reg_value = readl(GCC_NSS_PORT1_RX_CMD_RCGR + i*8 + port*0x10); + reg_value &= ~0x1; + reg_value |= 0x1; + writel(reg_value, GCC_NSS_PORT1_RX_CMD_RCGR + i*8 + port*0x10); + } +} + +int phy_status_get_from_ppe(int port_id) +{ + uint32_t reg_field = 0; + + ipq6018_ppe_reg_read(PORT_PHY_STATUS_ADDRESS, ®_field); + if (port_id == (PORT5 - PPE_UNIPHY_INSTANCE1)) + reg_field >>= PORT_PHY_STATUS_PORT5_1_OFFSET; + + return ((reg_field >> 7) & 0x1) ? 0 : 1; +} + +void ppe_port_bridge_txmac_set(int port_id, int status) +{ + uint32_t reg_value = 0; + + ipq6018_ppe_reg_read(IPE_L2_BASE_ADDR + PORT_BRIDGE_CTRL_ADDRESS + + (port_id * PORT_BRIDGE_CTRL_INC), ®_value); + if (status == 0) + reg_value |= TX_MAC_EN; + else + reg_value &= ~TX_MAC_EN; + + ipq6018_ppe_reg_write(IPE_L2_BASE_ADDR + PORT_BRIDGE_CTRL_ADDRESS + + (port_id * PORT_BRIDGE_CTRL_INC), reg_value); + +} + +void ipq6018_pqsgmii_speed_set(int port, int speed, int status) +{ + ppe_port_bridge_txmac_set(port + 1, status); + ipq6018_ppe_reg_write(IPQ6018_PPE_MAC_SPEED + (0x200 * port), speed); + ipq6018_ppe_reg_write(IPQ6018_PPE_MAC_ENABLE + (0x200 * port), 0x73); +} + +void ppe_xgmac_speed_set(uint32_t uniphy_index, int speed) +{ + uint32_t reg_value = 0; + + ipq6018_ppe_reg_read(PPE_SWITCH_NSS_SWITCH_XGMAC0 + + (uniphy_index * NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION), ®_value); + + switch(speed) { + case 0: + case 1: + case 2: + reg_value &=~USS; + reg_value |=SS(XGMAC_SPEED_SELECT_1000M); + break; + case 3: + reg_value |=USS; + reg_value |=SS(XGMAC_SPEED_SELECT_10000M); + break; + case 4: + reg_value |=USS; + reg_value |=SS(XGMAC_SPEED_SELECT_2500M); + break; + case 5: + reg_value |=USS; + reg_value |=SS(XGMAC_SPEED_SELECT_5000M); + break; + } + reg_value |=JD; + ipq6018_ppe_reg_write(PPE_SWITCH_NSS_SWITCH_XGMAC0 + + (uniphy_index * NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION), reg_value); + +} + +void ppe_xgmac_10g_r_speed_set(uint32_t uniphy_index) +{ + uint32_t reg_value = 0; + + ipq6018_ppe_reg_read(PPE_SWITCH_NSS_SWITCH_XGMAC0 + + (uniphy_index * NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION), ®_value); + + reg_value |=JD; + ipq6018_ppe_reg_write(PPE_SWITCH_NSS_SWITCH_XGMAC0 + + (uniphy_index * NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION), reg_value); + +} + +void ppe_port_txmac_status_set(uint32_t uniphy_index) +{ + uint32_t reg_value = 0; + + ipq6018_ppe_reg_read(PPE_SWITCH_NSS_SWITCH_XGMAC0 + + (uniphy_index * NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION), ®_value); + + reg_value |=TE; + ipq6018_ppe_reg_write(PPE_SWITCH_NSS_SWITCH_XGMAC0 + + (uniphy_index * NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION), reg_value); + +} + +void ppe_port_rxmac_status_set(uint32_t uniphy_index) +{ + uint32_t reg_value = 0; + + ipq6018_ppe_reg_read(PPE_SWITCH_NSS_SWITCH_XGMAC0 + + MAC_RX_CONFIGURATION_ADDRESS + + (uniphy_index * NSS_SWITCH_XGMAC_MAC_RX_CONFIGURATION), ®_value); + + reg_value |= 0x5ee00c0; + reg_value |=RE; + reg_value |=ACS; + reg_value |=CST; + ipq6018_ppe_reg_write(PPE_SWITCH_NSS_SWITCH_XGMAC0 + + MAC_RX_CONFIGURATION_ADDRESS + + (uniphy_index * NSS_SWITCH_XGMAC_MAC_RX_CONFIGURATION), reg_value); + +} + +void ppe_mac_packet_filter_set(uint32_t uniphy_index) +{ + ipq6018_ppe_reg_write(PPE_SWITCH_NSS_SWITCH_XGMAC0 + + MAC_PACKET_FILTER_ADDRESS + + (uniphy_index * MAC_PACKET_FILTER_INC), 0x81); +} + +void ipq6018_10g_r_speed_set(int port, int status) +{ + uint32_t uniphy_index; + + /* Setting the speed only for PORT5 */ + uniphy_index = PPE_UNIPHY_INSTANCE1; + ppe_xgmac_10g_r_speed_set(uniphy_index - 1); + ppe_port_bridge_txmac_set(port + 1, status); + ppe_port_txmac_status_set(uniphy_index - 1); + ppe_port_rxmac_status_set(uniphy_index - 1); + ppe_mac_packet_filter_set(uniphy_index - 1); +} + +void ipq6018_uxsgmii_speed_set(int port, int speed, int duplex, + int status) +{ + uint32_t uniphy_index; + + /* Setting the speed only for PORT5 */ + uniphy_index = PPE_UNIPHY_INSTANCE1; + ppe_uniphy_usxgmii_autoneg_completed(uniphy_index); + ppe_uniphy_usxgmii_speed_set(uniphy_index, speed); + ppe_xgmac_speed_set(uniphy_index - 1, speed); + ppe_uniphy_usxgmii_duplex_set(uniphy_index, duplex); + ppe_uniphy_usxgmii_port_reset(uniphy_index); + ppe_port_bridge_txmac_set(port + 1, status); + ppe_port_txmac_status_set(uniphy_index - 1); + ppe_port_rxmac_status_set(uniphy_index - 1); + ppe_mac_packet_filter_set(uniphy_index - 1); +} +/* + * ipq6018_ppe_flow_port_map_tbl_port_num_set() + */ +static void ipq6018_ppe_flow_port_map_tbl_port_num_set(int queue, int port) +{ + ipq6018_ppe_reg_write(IPQ6018_PPE_L0_FLOW_PORT_MAP_TBL + + queue * IPQ6018_PPE_L0_FLOW_PORT_MAP_TBL_INC, port); + ipq6018_ppe_reg_write(IPQ6018_PPE_L1_FLOW_PORT_MAP_TBL + + port * IPQ6018_PPE_L1_FLOW_PORT_MAP_TBL_INC, port); +} + +/* + * ipq6018_ppe_flow_map_tbl_set() + */ +static void ipq6018_ppe_flow_map_tbl_set(int queue, int port) +{ + uint32_t val = port | 0x401000; /* c_drr_wt = 1, e_drr_wt = 1 */ + ipq6018_ppe_reg_write(IPQ6018_PPE_L0_FLOW_MAP_TBL + queue * IPQ6018_PPE_L0_FLOW_MAP_TBL_INC, + val); + + val = port | 0x100400; /* c_drr_wt = 1, e_drr_wt = 1 */ + ipq6018_ppe_reg_write(IPQ6018_PPE_L1_FLOW_MAP_TBL + port * IPQ6018_PPE_L1_FLOW_MAP_TBL_INC, + val); +} + +/* + * ipq6018_ppe_tdm_configuration + */ +static void ipq6018_ppe_tdm_configuration(void) +{ + int i = 0; + + /* + * TDM is configured with instructions for each tick + * Port/action are configured as given below + * + * 0x5:0x5 TDM_CFG_VALID 0:idle tick + * 0x4:0x4 TDM_CFG_DIR 0:ingress wr + * 1:egress rd + * 0x3:0x0 TDM_CFG_PORT_NUM 0:DMA + * 1~4:Ethernet 1G + * 5~6:Ethernet 5G + * 7~8:Security0/1 + */ + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_INGRESS | + IPQ6018_PPE_PORT_XGMAC1); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_EGRESS | + IPQ6018_PPE_PORT_XGMAC1); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_INGRESS | + IPQ6018_PPE_PORT_EDMA); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_EGRESS | + IPQ6018_PPE_PORT_EDMA); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_INGRESS | + IPQ6018_PPE_PORT_XGMAC2); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_EGRESS | + IPQ6018_PPE_PORT_XGMAC2); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_INGRESS | + IPQ6018_PPE_PORT_QCOM1); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_EGRESS | + IPQ6018_PPE_PORT_EDMA); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_INGRESS | + IPQ6018_PPE_PORT_CRYPTO1); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_EGRESS | + IPQ6018_PPE_PORT_CRYPTO1); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_INGRESS | + IPQ6018_PPE_PORT_XGMAC1); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_EGRESS | + IPQ6018_PPE_PORT_XGMAC1); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_INGRESS | + IPQ6018_PPE_PORT_EDMA); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_EGRESS | + IPQ6018_PPE_PORT_EDMA); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_INGRESS | + IPQ6018_PPE_PORT_XGMAC2); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_EGRESS | + IPQ6018_PPE_PORT_XGMAC2); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_INGRESS | + IPQ6018_PPE_PORT_EDMA); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_EGRESS | + IPQ6018_PPE_PORT_QCOM3); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_INGRESS | + IPQ6018_PPE_PORT_CRYPTO1); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_EGRESS | + IPQ6018_PPE_PORT_CRYPTO1); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_INGRESS | + IPQ6018_PPE_PORT_XGMAC1); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_EGRESS | + IPQ6018_PPE_PORT_XGMAC1); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_INGRESS | + IPQ6018_PPE_PORT_EDMA); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_EGRESS | + IPQ6018_PPE_PORT_EDMA); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_INGRESS | + IPQ6018_PPE_PORT_XGMAC2); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_EGRESS | + IPQ6018_PPE_PORT_XGMAC2); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_INGRESS | + IPQ6018_PPE_PORT_EDMA); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_EGRESS | + IPQ6018_PPE_PORT_EDMA); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_INGRESS | + IPQ6018_PPE_PORT_CRYPTO1); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_EGRESS | + IPQ6018_PPE_PORT_CRYPTO1); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_INGRESS | + IPQ6018_PPE_PORT_XGMAC1); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_EGRESS | + IPQ6018_PPE_PORT_XGMAC1); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_INGRESS | + IPQ6018_PPE_PORT_EDMA); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_EGRESS | + IPQ6018_PPE_PORT_EDMA); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_INGRESS | + IPQ6018_PPE_PORT_XGMAC2); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_EGRESS | + IPQ6018_PPE_PORT_XGMAC2); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_INGRESS | + IPQ6018_PPE_PORT_QCOM2); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_EGRESS | + IPQ6018_PPE_PORT_EDMA); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_INGRESS | + IPQ6018_PPE_PORT_CRYPTO1); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_EGRESS | + IPQ6018_PPE_PORT_CRYPTO1); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_INGRESS | + IPQ6018_PPE_PORT_XGMAC1); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_EGRESS | + IPQ6018_PPE_PORT_XGMAC1); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_INGRESS | + IPQ6018_PPE_PORT_EDMA); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_EGRESS | + IPQ6018_PPE_PORT_QCOM4); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_INGRESS | + IPQ6018_PPE_PORT_XGMAC2); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_EGRESS | + IPQ6018_PPE_PORT_XGMAC2); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_INGRESS | + IPQ6018_PPE_PORT_EDMA); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_EGRESS | + IPQ6018_PPE_PORT_EDMA); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_INGRESS | + IPQ6018_PPE_PORT_CRYPTO1); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_EGRESS | + IPQ6018_PPE_PORT_CRYPTO1); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_INGRESS | + IPQ6018_PPE_PORT_XGMAC1); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_EGRESS | + IPQ6018_PPE_PORT_XGMAC1); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_INGRESS | + IPQ6018_PPE_PORT_EDMA); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID + | IPQ6018_PPE_TDM_CFG_DIR_EGRESS + | IPQ6018_PPE_PORT_EDMA); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_INGRESS | + IPQ6018_PPE_PORT_XGMAC2); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_EGRESS | + IPQ6018_PPE_PORT_XGMAC2); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_INGRESS | + IPQ6018_PPE_PORT_EDMA); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_EGRESS | + IPQ6018_PPE_PORT_QCOM1); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_INGRESS | + IPQ6018_PPE_PORT_CRYPTO1); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_INGRESS | + IPQ6018_PPE_PORT_XGMAC1); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_EGRESS | + IPQ6018_PPE_PORT_XGMAC1); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_INGRESS | + IPQ6018_PPE_PORT_EDMA); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_EGRESS | + IPQ6018_PPE_PORT_EDMA); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_INGRESS | + IPQ6018_PPE_PORT_XGMAC2); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_EGRESS | + IPQ6018_PPE_PORT_XGMAC2); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_INGRESS | + IPQ6018_PPE_PORT_QCOM3); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_EGRESS | + IPQ6018_PPE_PORT_EDMA); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_INGRESS | + IPQ6018_PPE_PORT_CRYPTO1); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_EGRESS | + IPQ6018_PPE_PORT_CRYPTO1); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_INGRESS | + IPQ6018_PPE_PORT_XGMAC1); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_EGRESS | + IPQ6018_PPE_PORT_XGMAC1); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_INGRESS | + IPQ6018_PPE_PORT_EDMA); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_EGRESS | + IPQ6018_PPE_PORT_EDMA); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_INGRESS | + IPQ6018_PPE_PORT_XGMAC2); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_EGRESS | + IPQ6018_PPE_PORT_XGMAC2); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_INGRESS | + IPQ6018_PPE_PORT_EDMA); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_EGRESS | + IPQ6018_PPE_PORT_EDMA); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_EGRESS | + IPQ6018_PPE_PORT_EDMA); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_INGRESS | + IPQ6018_PPE_PORT_CRYPTO1); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_EGRESS | + IPQ6018_PPE_PORT_CRYPTO1); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_INGRESS | + IPQ6018_PPE_PORT_XGMAC1); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_EGRESS | + IPQ6018_PPE_PORT_XGMAC1); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_INGRESS | + IPQ6018_PPE_PORT_EDMA); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_EGRESS | + IPQ6018_PPE_PORT_EDMA); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_INGRESS | + IPQ6018_PPE_PORT_XGMAC2); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_EGRESS | + IPQ6018_PPE_PORT_XGMAC2); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_INGRESS | + IPQ6018_PPE_PORT_EDMA); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_EGRESS | + IPQ6018_PPE_PORT_QCOM2); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_INGRESS | + IPQ6018_PPE_PORT_CRYPTO1); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_EGRESS | + IPQ6018_PPE_PORT_CRYPTO1); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_INGRESS | + IPQ6018_PPE_PORT_XGMAC1); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_EGRESS | + IPQ6018_PPE_PORT_XGMAC1); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_INGRESS | + IPQ6018_PPE_PORT_QCOM4); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_EGRESS | + IPQ6018_PPE_PORT_EDMA); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_INGRESS | + IPQ6018_PPE_PORT_XGMAC2); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_EGRESS | + IPQ6018_PPE_PORT_XGMAC2); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_INGRESS | + IPQ6018_PPE_PORT_EDMA); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_EGRESS | + IPQ6018_PPE_PORT_EDMA); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_INGRESS | + IPQ6018_PPE_PORT_CRYPTO1); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ6018_PPE_TDM_CFG_VALID | + IPQ6018_PPE_TDM_CFG_DIR_EGRESS | + IPQ6018_PPE_PORT_CRYPTO1); + + /* Set TDM Depth to 100 entries */ + ipq6018_ppe_reg_write(IPQ6018_PPE_TDM_CFG_DEPTH_OFFSET, IPQ6018_PPE_TDM_CFG_DEPTH_VAL); +} + +/* + * ipq6018_ppe_sched_configuration + */ +static void ipq6018_ppe_sched_configuration(void) +{ + int i = 0; + + /* + * PSCH_TDM_CFG_TBL_DES_PORT : determine which egress port traffic + * will be selected and transmitted out + * PSCH_TDM_CFG_TBL_ENS_PORT : determine which port’s queue need + * to be linked to scheduler at the current tick + * PSCH_TDM_CFG_TBL_ENS_PORT_BITMAP : determine port bitmap + * for source of queue + * + * 0xf:0x8 PSCH_TDM_CFG_TBL_ENS_PORT_BITMAP 1110_1110 + * (Port:765-432) + * + * 0x7:0x4 PSCH_TDM_CFG_TBL_ENS_PORT 0:DMA + * 1~4:Ethernet 1G + * 5~6:Ethernet 5G + * 7~8:Security0/1 + * + * 0x3:0x0 PSCH_TDM_CFG_TBL_DES_PORT 0:DMA + * 1~4:Ethernet 1G + * 5~6:Ethernet 5G + * 7~8:Security0/1 + * + * For eg, 0xee60 =((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_XGMAC2_BITPOS | + * IPQ6018_PPE_PORT_XGMAC1_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS | + * IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) | + * IPQ6018_PPE_PORT_XGMAC2 | IPQ6018_PPE_PORT_EDMA); + */ + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_XGMAC2_BITPOS | + IPQ6018_PPE_PORT_XGMAC1_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS | + IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ6018_PPE_PORT_XGMAC2 << 4) | IPQ6018_PPE_PORT_EDMA); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_XGMAC2_BITPOS | + IPQ6018_PPE_PORT_QCOM3_BITPOS | IPQ6018_PPE_PORT_QCOM2_BITPOS | + IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ6018_PPE_PORT_QCOM4 << 4) | IPQ6018_PPE_PORT_XGMAC1); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_QCOM4_BITPOS | + IPQ6018_PPE_PORT_QCOM3_BITPOS | IPQ6018_PPE_PORT_QCOM2_BITPOS | + IPQ6018_PPE_PORT_QCOM1_BITPOS | IPQ6018_PPE_PORT_EDMA_BITPOS) << 8) | + (IPQ6018_PPE_PORT_EDMA << 4) | IPQ6018_PPE_PORT_XGMAC2); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_XGMAC1_BITPOS | + IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS | + IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ6018_PPE_PORT_XGMAC1 << 4) | IPQ6018_PPE_PORT_EDMA); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ6018_PPE_PORT_XGMAC2_BITPOS | IPQ6018_PPE_PORT_XGMAC1_BITPOS | + IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS | + IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ6018_PPE_PORT_XGMAC2 << 4) | IPQ6018_PPE_PORT_CRYPTO1); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ6018_PPE_PORT_EDMA_BITPOS | IPQ6018_PPE_PORT_XGMAC2_BITPOS | + IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS | + IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ6018_PPE_PORT_EDMA << 4) | IPQ6018_PPE_PORT_XGMAC1); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_EDMA_BITPOS | + IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS | + IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ6018_PPE_PORT_CRYPTO1 << 4) | IPQ6018_PPE_PORT_XGMAC2); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_XGMAC1_BITPOS | + IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS | + IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ6018_PPE_PORT_XGMAC1 << 4) | IPQ6018_PPE_PORT_EDMA); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_XGMAC1_BITPOS | + IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS | + IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_XGMAC2_BITPOS) << 8) | + (IPQ6018_PPE_PORT_XGMAC2 << 4) | IPQ6018_PPE_PORT_QCOM1); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_XGMAC2_BITPOS | + IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS | + IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_EDMA_BITPOS) << 8) | + (IPQ6018_PPE_PORT_EDMA << 4) | IPQ6018_PPE_PORT_XGMAC1); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_XGMAC2_BITPOS | + IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS | + IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ6018_PPE_PORT_QCOM1 << 4) | IPQ6018_PPE_PORT_EDMA); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_XGMAC1_BITPOS | + IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS | + IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ6018_PPE_PORT_XGMAC1 << 4) | IPQ6018_PPE_PORT_XGMAC2); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_XGMAC1_BITPOS | + IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS | + IPQ6018_PPE_PORT_EDMA_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ6018_PPE_PORT_EDMA << 4) | IPQ6018_PPE_PORT_QCOM2); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_XGMAC2_BITPOS | + IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS | + IPQ6018_PPE_PORT_EDMA_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ6018_PPE_PORT_XGMAC2 << 4) | IPQ6018_PPE_PORT_XGMAC1); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_XGMAC2_BITPOS | + IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS | + IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ6018_PPE_PORT_QCOM2 << 4) | IPQ6018_PPE_PORT_EDMA); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_XGMAC1_BITPOS | + IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS | + IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ6018_PPE_PORT_XGMAC1 << 4) | IPQ6018_PPE_PORT_XGMAC2); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ6018_PPE_PORT_XGMAC1_BITPOS | IPQ6018_PPE_PORT_EDMA_BITPOS | + IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS | + IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ6018_PPE_PORT_EDMA << 4) | IPQ6018_PPE_PORT_CRYPTO1); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ6018_PPE_PORT_XGMAC2_BITPOS | IPQ6018_PPE_PORT_XGMAC1_BITPOS | + IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS | + IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ6018_PPE_PORT_XGMAC2 << 4) | IPQ6018_PPE_PORT_EDMA); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_XGMAC2_BITPOS | + IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS | + IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ6018_PPE_PORT_CRYPTO1 << 4) | IPQ6018_PPE_PORT_XGMAC1); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_EDMA_BITPOS | + IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS | + IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ6018_PPE_PORT_EDMA << 4) | IPQ6018_PPE_PORT_XGMAC2); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_XGMAC1_BITPOS | + IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_EDMA_BITPOS | + IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ6018_PPE_PORT_XGMAC1 << 4) | IPQ6018_PPE_PORT_QCOM3); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_XGMAC2_BITPOS | + IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_XGMAC1_BITPOS | + IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ6018_PPE_PORT_XGMAC2 << 4) | IPQ6018_PPE_PORT_EDMA); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_XGMAC2_BITPOS | + IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS | + IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ6018_PPE_PORT_QCOM3 << 4) | IPQ6018_PPE_PORT_XGMAC1); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_EDMA_BITPOS | + IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS | + IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ6018_PPE_PORT_EDMA << 4) | IPQ6018_PPE_PORT_XGMAC2); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_XGMAC1_BITPOS | + IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS | + IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ6018_PPE_PORT_XGMAC1 << 4) | IPQ6018_PPE_PORT_EDMA); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_XGMAC2_BITPOS | + IPQ6018_PPE_PORT_XGMAC1_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS | + IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ6018_PPE_PORT_XGMAC2 << 4) | IPQ6018_PPE_PORT_QCOM4); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_EDMA_BITPOS | + IPQ6018_PPE_PORT_XGMAC2_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS | + IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ6018_PPE_PORT_EDMA << 4) | IPQ6018_PPE_PORT_XGMAC1); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_EDMA_BITPOS | + IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS | + IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ6018_PPE_PORT_QCOM4 << 4) | IPQ6018_PPE_PORT_XGMAC2); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_XGMAC1_BITPOS | + IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS | + IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ6018_PPE_PORT_XGMAC1 << 4) | IPQ6018_PPE_PORT_EDMA); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ6018_PPE_PORT_XGMAC2_BITPOS | IPQ6018_PPE_PORT_XGMAC1_BITPOS | + IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS | + IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ6018_PPE_PORT_XGMAC2 << 4) | IPQ6018_PPE_PORT_CRYPTO1); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ6018_PPE_PORT_EDMA_BITPOS | IPQ6018_PPE_PORT_XGMAC2_BITPOS | + IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS | + IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ6018_PPE_PORT_EDMA << 4) | IPQ6018_PPE_PORT_XGMAC1); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_XGMAC2_BITPOS | + IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS | + IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ6018_PPE_PORT_CRYPTO1 << 4) | IPQ6018_PPE_PORT_EDMA); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_XGMAC1_BITPOS | + IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS | + IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ6018_PPE_PORT_XGMAC1 << 4) | IPQ6018_PPE_PORT_XGMAC2); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_XGMAC1_BITPOS | + IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS | + IPQ6018_PPE_PORT_EDMA_BITPOS | IPQ6018_PPE_PORT_QCOM2_BITPOS) << 8) | + (IPQ6018_PPE_PORT_EDMA << 4) | IPQ6018_PPE_PORT_QCOM1); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_XGMAC2_BITPOS | + IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS | + IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_EDMA_BITPOS) << 8) | + (IPQ6018_PPE_PORT_XGMAC2 << 4) | IPQ6018_PPE_PORT_XGMAC1); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_XGMAC2_BITPOS | + IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS | + IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ6018_PPE_PORT_QCOM1 << 4) | IPQ6018_PPE_PORT_EDMA); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_XGMAC1_BITPOS | + IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS | + IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ6018_PPE_PORT_XGMAC1 << 4) | IPQ6018_PPE_PORT_XGMAC2); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_XGMAC1_BITPOS | + IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS | + IPQ6018_PPE_PORT_EDMA_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ6018_PPE_PORT_EDMA << 4) | IPQ6018_PPE_PORT_QCOM2); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_XGMAC1_BITPOS | + IPQ6018_PPE_PORT_XGMAC2_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS | + IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ6018_PPE_PORT_XGMAC2 << 4) | IPQ6018_PPE_PORT_EDMA); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_XGMAC2_BITPOS | + IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS | + IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ6018_PPE_PORT_QCOM2 << 4) | IPQ6018_PPE_PORT_XGMAC1); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_EDMA_BITPOS | + IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS | + IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ6018_PPE_PORT_EDMA << 4) | IPQ6018_PPE_PORT_XGMAC2); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ6018_PPE_PORT_XGMAC1_BITPOS | IPQ6018_PPE_PORT_EDMA_BITPOS | + IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS | + IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ6018_PPE_PORT_XGMAC1 << 4) | IPQ6018_PPE_PORT_CRYPTO1); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ6018_PPE_PORT_XGMAC2_BITPOS | IPQ6018_PPE_PORT_XGMAC1_BITPOS | + IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS | + IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ6018_PPE_PORT_XGMAC2 << 4) | IPQ6018_PPE_PORT_EDMA); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_XGMAC2_BITPOS | + IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS | + IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ6018_PPE_PORT_CRYPTO1 << 4) | IPQ6018_PPE_PORT_XGMAC1); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_EDMA_BITPOS | + IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS | + IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ6018_PPE_PORT_EDMA << 4) | IPQ6018_PPE_PORT_XGMAC2); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_XGMAC1_BITPOS | + IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_EDMA_BITPOS | + IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ6018_PPE_PORT_XGMAC1 << 4) | IPQ6018_PPE_PORT_QCOM3); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_XGMAC2_BITPOS | + IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_XGMAC1_BITPOS | + IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ6018_PPE_PORT_XGMAC2 << 4) | IPQ6018_PPE_PORT_EDMA); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_XGMAC2_BITPOS | + IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS | + IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ6018_PPE_PORT_QCOM3 << 4) | IPQ6018_PPE_PORT_XGMAC1); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_EDMA_BITPOS | + IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS | + IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ6018_PPE_PORT_EDMA << 4) | IPQ6018_PPE_PORT_XGMAC2); + ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_XGMAC1_BITPOS | + IPQ6018_PPE_PORT_EDMA_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS | + IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ6018_PPE_PORT_XGMAC1 << 4) | IPQ6018_PPE_PORT_QCOM4); + + /* Set Sched Depth to 50 entries */ + ipq6018_ppe_reg_write(IPQ6018_PPE_TDM_SCHED_DEPTH_OFFSET, IPQ6018_PPE_TDM_SCHED_DEPTH_VAL); +} + +/* + * ipq6018_ppe_c_sp_cfg_tbl_drr_id_set + */ +static void ipq6018_ppe_c_sp_cfg_tbl_drr_id_set(int id) +{ + ipq6018_ppe_reg_write(IPQ6018_PPE_L0_C_SP_CFG_TBL + (id * 0x80), id * 2); + ipq6018_ppe_reg_write(IPQ6018_PPE_L1_C_SP_CFG_TBL + (id * 0x80), id * 2); +} + +/* + * ipq6018_ppe_e_sp_cfg_tbl_drr_id_set + */ +static void ipq6018_ppe_e_sp_cfg_tbl_drr_id_set(int id) +{ + ipq6018_ppe_reg_write(IPQ6018_PPE_L0_E_SP_CFG_TBL + (id * 0x80), id * 2 + 1); + ipq6018_ppe_reg_write(IPQ6018_PPE_L1_E_SP_CFG_TBL + (id * 0x80), id * 2 + 1); +} + +static void ppe_port_mux_set(int port_id, int port_type, int mode) +{ + union port_mux_ctrl_u port_mux_ctrl; + int nodeoff; + + nodeoff = fdt_path_offset(gd->fdt_blob, "/ess-switch"); + + ipq6018_ppe_reg_read(IPQ6018_PORT_MUX_CTRL, &(port_mux_ctrl.val)); + + switch (port_id) { + case 3: + case 4: + if (mode == PORT_WRAPPER_SGMII_PLUS || mode == PORT_WRAPPER_SGMII0_RGMII4) { + port_mux_ctrl.bf.port3_pcs_sel = CPPE_PORT3_PCS_SEL_PCS0_CHANNEL2; + port_mux_ctrl.bf.port4_pcs_sel = CPPE_PORT4_PCS_SEL_PCS0_SGMIIPLUS; + port_mux_ctrl.bf.pcs0_ch0_sel = CPPE_PCS0_CHANNEL0_SEL_SGMIIPLUS; + port_mux_ctrl.bf.pcs0_ch4_sel = CPPE_PCS0_CHANNEL4_SEL_PORT5_CLOCK; + } else if (mode == PORT_WRAPPER_PSGMII || mode == PORT_WRAPPER_QSGMII) { + if (fdtdec_get_int(gd->fdt_blob, nodeoff, "malibu2port_phy", 0)) { + port_mux_ctrl.bf.port3_pcs_sel = CPPE_PORT3_PCS_SEL_PCS0_CHANNEL4; + port_mux_ctrl.bf.port4_pcs_sel = CPPE_PORT4_PCS_SEL_PCS0_CHANNEL3; + port_mux_ctrl.bf.pcs0_ch4_sel = CPPE_PCS0_CHANNEL4_SEL_PORT3_CLOCK; + } else { + port_mux_ctrl.bf.port3_pcs_sel = CPPE_PORT3_PCS_SEL_PCS0_CHANNEL2; + port_mux_ctrl.bf.port4_pcs_sel = CPPE_PORT4_PCS_SEL_PCS0_CHANNEL3; + port_mux_ctrl.bf.pcs0_ch0_sel = CPPE_PCS0_CHANNEL0_SEL_PSGMII; + port_mux_ctrl.bf.pcs0_ch4_sel = CPPE_PCS0_CHANNEL4_SEL_PORT5_CLOCK; + } + } + break; + case 5: + if (mode == PORT_WRAPPER_SGMII_PLUS || mode == PORT_WRAPPER_SGMII0_RGMII4 || + mode == PORT_WRAPPER_SGMII_FIBER) { + port_mux_ctrl.bf.port5_pcs_sel = CPPE_PORT5_PCS_SEL_PCS1_CHANNEL0; + port_mux_ctrl.bf.port5_gmac_sel = CPPE_PORT5_GMAC_SEL_GMAC; + } else if (mode == PORT_WRAPPER_PSGMII) { + port_mux_ctrl.bf.port5_pcs_sel = CPPE_PORT5_PCS_SEL_PCS0_CHANNEL4; + port_mux_ctrl.bf.port5_gmac_sel = CPPE_PORT5_GMAC_SEL_GMAC; + } else if (mode == PORT_WRAPPER_USXGMII || mode == PORT_WRAPPER_10GBASE_R) { + port_mux_ctrl.bf.port5_pcs_sel = CPPE_PORT5_PCS_SEL_PCS1_CHANNEL0; + port_mux_ctrl.bf.port5_gmac_sel = CPPE_PORT5_GMAC_SEL_XGMAC; + } + break; + default: + break; + } + + ipq6018_ppe_reg_write(IPQ6018_PORT_MUX_CTRL, port_mux_ctrl.val); +} + +void ppe_port_mux_mac_type_set(int port_id, int mode) +{ + uint32_t port_type; + + switch(mode) + { + case PORT_WRAPPER_PSGMII: + case PORT_WRAPPER_SGMII0_RGMII4: + case PORT_WRAPPER_SGMII_PLUS: + case PORT_WRAPPER_SGMII_FIBER: + port_type = PORT_GMAC_TYPE; + break; + case PORT_WRAPPER_USXGMII: + case PORT_WRAPPER_10GBASE_R: + port_type = PORT_XGMAC_TYPE; + break; + default: + return; + } + ppe_port_mux_set(port_id, port_type, mode); +} + + + +void ipq6018_ppe_interface_mode_init(void) +{ + uint32_t mode0, mode1; + int node; + + node = fdt_path_offset(gd->fdt_blob, "/ess-switch"); + if (node < 0) { + printf("Error: ess-switch not specified in dts"); + return; + } + + mode0 = fdtdec_get_uint(gd->fdt_blob, node, "switch_mac_mode", -1); + if (mode0 < 0) { + printf("Error: switch_mac_mode not specified in dts"); + return; + } + + mode1 = fdtdec_get_uint(gd->fdt_blob, node, "switch_mac_mode1", -1); + if (mode1 < 0) { + printf("Error: switch_mac_mode1 not specified in dts"); + return; + } + + ppe_uniphy_mode_set(PPE_UNIPHY_INSTANCE0, mode0); + ppe_uniphy_mode_set(PPE_UNIPHY_INSTANCE1, mode1); + + ppe_port_mux_mac_type_set(4, mode0); + ppe_port_mux_mac_type_set(5, mode1); +} + +/* + * ipq6018_ppe_provision_init() + */ +void ipq6018_ppe_provision_init(void) +{ + int i; + uint32_t queue; + + /* tdm/sched configuration */ + ipq6018_ppe_tdm_configuration(); + ipq6018_ppe_sched_configuration(); + + /* disable clock gating */ + ipq6018_ppe_reg_write(0x000008, 0x0); + + /* flow ctrl disable */ + ipq6018_ppe_reg_write(0x200368, 0xc88); + +#ifdef CONFIG_IPQ6018_BRIDGED_MODE + /* Add CPU port 0 to VSI 2 */ + ipq6018_ppe_vp_port_tbl_set(0, 2); + + /* Add port 1 - 4 to VSI 2 */ + ipq6018_ppe_vp_port_tbl_set(1, 2); + ipq6018_ppe_vp_port_tbl_set(2, 2); + ipq6018_ppe_vp_port_tbl_set(3, 2); + ipq6018_ppe_vp_port_tbl_set(4, 2); + ipq6018_ppe_vp_port_tbl_set(5, 2); + +#else + ipq6018_ppe_vp_port_tbl_set(1, 2); + ipq6018_ppe_vp_port_tbl_set(2, 3); + ipq6018_ppe_vp_port_tbl_set(3, 4); + ipq6018_ppe_vp_port_tbl_set(4, 5); + ipq6018_ppe_vp_port_tbl_set(5, 6); +#endif + + /* Unicast priority map */ + ipq6018_ppe_reg_write(IPQ6018_PPE_QM_UPM_TBL, 0); + + /* Port0 - 7 unicast queue settings */ + for (i = 0; i < 8; i++) { + if (i == 0) + queue = 0; + else + queue = ((i * 0x10) + 0x70); + + ipq6018_ppe_ucast_queue_map_tbl_queue_id_set(queue, i); + ipq6018_ppe_flow_port_map_tbl_port_num_set(queue, i); + ipq6018_ppe_flow_map_tbl_set(queue, i); + ipq6018_ppe_c_sp_cfg_tbl_drr_id_set(i); + ipq6018_ppe_e_sp_cfg_tbl_drr_id_set(i); + } + + /* Port0 multicast queue */ + ipq6018_ppe_reg_write(0x409000, 0x00000000); + ipq6018_ppe_reg_write(0x403000, 0x00401000); + + /* Port1 - 7 multicast queue */ + for (i = 1; i < 8; i++) { + ipq6018_ppe_reg_write(0x409100 + ((i - 1) * 0x40), i); + ipq6018_ppe_reg_write(0x403100 + ((i - 1) * 0x40), 0x401000 | i); + } + + /* + * Port0 - Port7 learn enable and isolation port bitmap and TX_EN + * Here please pay attention on bit16 (TX_EN) is not set on port7 + */ + for (i = 0; i < 7; i++) + ipq6018_ppe_reg_write(IPQ6018_PPE_PORT_BRIDGE_CTRL_OFFSET + (i * 4), + IPQ6018_PPE_PORT_BRIDGE_CTRL_PROMISC_EN | + IPQ6018_PPE_PORT_BRIDGE_CTRL_TXMAC_EN | + IPQ6018_PPE_PORT_BRIDGE_CTRL_PORT_ISOLATION_BMP | + IPQ6018_PPE_PORT_BRIDGE_CTRL_STATION_LRN_EN | + IPQ6018_PPE_PORT_BRIDGE_CTRL_NEW_ADDR_LRN_EN); + + ipq6018_ppe_reg_write(IPQ6018_PPE_PORT_BRIDGE_CTRL_OFFSET + (7 * 4), + IPQ6018_PPE_PORT_BRIDGE_CTRL_PROMISC_EN | + IPQ6018_PPE_PORT_BRIDGE_CTRL_PORT_ISOLATION_BMP | + IPQ6018_PPE_PORT_BRIDGE_CTRL_STATION_LRN_EN | + IPQ6018_PPE_PORT_BRIDGE_CTRL_NEW_ADDR_LRN_EN); + + /* Global learning */ + ipq6018_ppe_reg_write(0x060038, 0xc0); + +#ifdef CONFIG_IPQ6018_BRIDGED_MODE + ipq6018_vsi_setup(2, 0x3f); +#else + ipq6018_vsi_setup(2, 0x03); + ipq6018_vsi_setup(3, 0x05); + ipq6018_vsi_setup(4, 0x09); + ipq6018_vsi_setup(5, 0x11); +#endif + + /* Port 0-7 STP */ + for (i = 0; i < 8; i++) + ipq6018_ppe_reg_write(IPQ6018_PPE_STP_BASE + (0x4 * i), 0x3); + + ipq6018_ppe_interface_mode_init(); + /* Port 0-4 disable */ + for (i = 0; i < 5; i++) { + ipq6018_gmac_port_disable(i); + ppe_port_bridge_txmac_set(i + 1, 1); + } + + /* Allowing DHCP packets */ + ipq6018_ppe_acl_set(0, ADPT_ACL_HPPE_IPV4_DIP_RULE, UDP_PKT, 67, 0xffff, 0, 0); + ipq6018_ppe_acl_set(1, ADPT_ACL_HPPE_IPV4_DIP_RULE, UDP_PKT, 68, 0xffff, 0, 0); + /* Dropping all the UDP packets */ + ipq6018_ppe_acl_set(2, ADPT_ACL_HPPE_IPV4_DIP_RULE, UDP_PKT, 0, 0, 0, 1); +} diff --git a/sources/uboot-be550/drivers/net/ipq6018/ipq6018_ppe.h b/sources/uboot-be550/drivers/net/ipq6018/ipq6018_ppe.h new file mode 100644 index 00000000..cd8130e3 --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq6018/ipq6018_ppe.h @@ -0,0 +1,255 @@ +/* + ************************************************************************** + * Copyright (c) 2016-2019 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT + * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + ************************************************************************** + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define GCC_NSS_PORT1_RX_CMD_RCGR 0x01868020 +#define GCC_NSS_PORT1_RX_CFG_RCGR 0x01868024 +#define GCC_NSS_PORT1_RX_MISC 0x01868400 + +#define IPQ6018_PPE_BASE_ADDR 0x3a000000 +#define IPQ6018_PPE_REG_SIZE 0x1000000 + +#define PORT4 4 +#define PORT5 5 +#define PORT_GMAC_TYPE 1 +#define PORT_XGMAC_TYPE 2 + +struct port_mux_ctrl { + uint32_t port3_pcs_sel:2; + uint32_t port4_pcs_sel:2; + uint32_t port5_pcs_sel:2; + uint32_t port5_gmac_sel:1; + uint32_t pcs0_ch4_sel:1; + uint32_t pcs0_ch0_sel:1; + uint32_t _reserved0:23; +}; + +union port_mux_ctrl_u { + uint32_t val; + struct port_mux_ctrl bf; +}; + +enum { + TCP_PKT, + UDP_PKT, +}; + +#define ADPT_ACL_HPPE_IPV4_DIP_RULE 4 +#define MAX_RULE 512 + +struct ipo_rule_reg { + uint32_t rule_field_0:32; + uint32_t rule_field_1:20; + uint32_t fake_mac_header:1; + uint32_t range_en:1; + uint32_t inverse_en:1; + uint32_t rule_type:4; + uint32_t src_type:2; + uint32_t src_0:3; + uint32_t src_1:5; + uint32_t pri:9; + uint32_t res_chain:1; + uint32_t post_routing_en:1; + uint32_t _reserved0:16; +}; + +union ipo_rule_reg_u { + uint32_t val[3]; + struct ipo_rule_reg bf; +}; + +struct ipo_mask_reg { + uint32_t maskfield_0:32; + uint32_t maskfield_1:21; + uint32_t _reserved0:11; +}; + +union ipo_mask_reg_u { + uint32_t val[2]; + struct ipo_mask_reg bf; +}; + +struct ipo_action { + uint32_t dest_info_change_en:1; + uint32_t fwd_cmd:2; + uint32_t _reserved0:29; + uint32_t _reserved1:32; + uint32_t _reserved2:32; + uint32_t _reserved3:32; + uint32_t _reserved4:32; +}; + +union ipo_action_u { + uint32_t val[5]; + struct ipo_action bf; +}; + +#define IPQ6018_PORT_MUX_CTRL 0x10 +#define CPPE_PORT3_PCS_SEL_PCS0_CHANNEL2 0 +#define CPPE_PORT3_PCS_SEL_PCS0_CHANNEL4 1 +#define CPPE_PORT4_PCS_SEL_PCS0_CHANNEL3 0 +#define CPPE_PORT4_PCS_SEL_PCS0_SGMIIPLUS 1 +#define CPPE_PORT5_PCS_SEL_PCS0_CHANNEL4 0 +#define CPPE_PORT5_PCS_SEL_PCS1_CHANNEL0 1 +#define CPPE_PORT5_GMAC_SEL_GMAC 0 +#define CPPE_PORT5_GMAC_SEL_XGMAC 1 +#define CPPE_PCS0_CHANNEL4_SEL_PORT5_CLOCK 0x0 +#define CPPE_PCS0_CHANNEL4_SEL_PORT3_CLOCK 0x1 +#define CPPE_PCS0_CHANNEL0_SEL_PSGMII 0x0 +#define CPPE_PCS0_CHANNEL0_SEL_SGMIIPLUS 0x1 +#define CPPE_DETECTION_PHY_FAILURE 0xFFFF + +#define PORT_PHY_STATUS_ADDRESS 0x44 +#define PORT_PHY_STATUS_PORT5_1_OFFSET 16 + +#define IPQ6018_PPE_IPE_L3_BASE_ADDR 0x200000 +#define IPQ6018_PPE_L3_VP_PORT_TBL_ADDR (IPQ6018_PPE_IPE_L3_BASE_ADDR + 0x1000) +#define IPQ6018_PPE_L3_VP_PORT_TBL_INC 0x10 + +#define IPQ6018_PPE_QUEUE_MANAGER_BASE_ADDR 0x800000 +#define IPQ6018_PPE_UCAST_QUEUE_MAP_TBL_ADDR 0x10000 +#define IPQ6018_PPE_UCAST_QUEUE_MAP_TBL_INC 0x10 +#define IPQ6018_PPE_QM_UQM_TBL (IPQ6018_PPE_QUEUE_MANAGER_BASE_ADDR +\ + IPQ6018_PPE_UCAST_QUEUE_MAP_TBL_ADDR) +#define IPQ6018_PPE_UCAST_PRIORITY_MAP_TBL_ADDR 0x42000 +#define IPQ6018_PPE_QM_UPM_TBL (IPQ6018_PPE_QUEUE_MANAGER_BASE_ADDR +\ + IPQ6018_PPE_UCAST_PRIORITY_MAP_TBL_ADDR) + +#define IPQ6018_PPE_STP_BASE 0x060100 +#define IPQ6018_PPE_MAC_ENABLE 0x001000 +#define IPQ6018_PPE_MAC_SPEED 0x001004 +#define IPQ6018_PPE_MAC_MIB_CTL 0x001034 + +#define IPQ6018_PPE_TRAFFIC_MANAGER_BASE_ADDR 0x400000 + +#define IPQ6018_PPE_L0_FLOW_PORT_MAP_TBL_ADDR 0x8000 +#define IPQ6018_PPE_L0_FLOW_PORT_MAP_TBL_INC 0x10 +#define IPQ6018_PPE_L0_FLOW_PORT_MAP_TBL (IPQ6018_PPE_TRAFFIC_MANAGER_BASE_ADDR +\ + IPQ6018_PPE_L0_FLOW_PORT_MAP_TBL_ADDR) + +#define IPQ6018_PPE_L0_FLOW_MAP_TBL_ADDR 0x2000 +#define IPQ6018_PPE_L0_FLOW_MAP_TBL_INC 0x10 +#define IPQ6018_PPE_L0_FLOW_MAP_TBL (IPQ6018_PPE_TRAFFIC_MANAGER_BASE_ADDR +\ + IPQ6018_PPE_L0_FLOW_MAP_TBL_ADDR) + +#define IPQ6018_PPE_L1_FLOW_PORT_MAP_TBL_ADDR 0x46000 +#define IPQ6018_PPE_L1_FLOW_PORT_MAP_TBL_INC 0x10 +#define IPQ6018_PPE_L1_FLOW_PORT_MAP_TBL (IPQ6018_PPE_TRAFFIC_MANAGER_BASE_ADDR +\ + IPQ6018_PPE_L1_FLOW_PORT_MAP_TBL_ADDR) + +#define IPQ6018_PPE_L1_FLOW_MAP_TBL_ADDR 0x40000 +#define IPQ6018_PPE_L1_FLOW_MAP_TBL_INC 0x10 +#define IPQ6018_PPE_L1_FLOW_MAP_TBL (IPQ6018_PPE_TRAFFIC_MANAGER_BASE_ADDR +\ + IPQ6018_PPE_L1_FLOW_MAP_TBL_ADDR) + +#define IPQ6018_PPE_L0_C_SP_CFG_TBL_ADDR 0x4000 +#define IPQ6018_PPE_L0_C_SP_CFG_TBL (IPQ6018_PPE_TRAFFIC_MANAGER_BASE_ADDR +\ + IPQ6018_PPE_L0_C_SP_CFG_TBL_ADDR) + +#define IPQ6018_PPE_L1_C_SP_CFG_TBL_ADDR 0x42000 +#define IPQ6018_PPE_L1_C_SP_CFG_TBL (IPQ6018_PPE_TRAFFIC_MANAGER_BASE_ADDR +\ + IPQ6018_PPE_L1_C_SP_CFG_TBL_ADDR) + +#define IPQ6018_PPE_L0_E_SP_CFG_TBL_ADDR 0x6000 +#define IPQ6018_PPE_L0_E_SP_CFG_TBL (IPQ6018_PPE_TRAFFIC_MANAGER_BASE_ADDR +\ + IPQ6018_PPE_L0_E_SP_CFG_TBL_ADDR) + +#define IPQ6018_PPE_L1_E_SP_CFG_TBL_ADDR 0x44000 +#define IPQ6018_PPE_L1_E_SP_CFG_TBL (IPQ6018_PPE_TRAFFIC_MANAGER_BASE_ADDR +\ + IPQ6018_PPE_L1_E_SP_CFG_TBL_ADDR) + +#define IPQ6018_PPE_FPGA_GPIO_BASE_ADDR 0x01008000 + +#define IPQ6018_PPE_MAC_PORT_MUX_OFFSET 0x10 +#define IPQ6018_PPE_FPGA_GPIO_OFFSET 0xc000 +#define IPQ6018_PPE_FPGA_SCHED_OFFSET 0x47a000 +#define IPQ6018_PPE_TDM_CFG_DEPTH_OFFSET 0xb000 +#define IPQ6018_PPE_TDM_SCHED_DEPTH_OFFSET 0x400000 +#define IPQ6018_PPE_PORT_BRIDGE_CTRL_OFFSET 0x060300 + +#define IPQ6018_PPE_TDM_CFG_DEPTH_VAL 0x80000064 +#define IPQ6018_PPE_MAC_PORT_MUX_OFFSET_VAL 0x15 +#define IPQ6018_PPE_TDM_SCHED_DEPTH_VAL 0x32 +#define IPQ6018_PPE_TDM_CFG_VALID 0x20 +#define IPQ6018_PPE_TDM_CFG_DIR_INGRESS 0x0 +#define IPQ6018_PPE_TDM_CFG_DIR_EGRESS 0x10 +#define IPQ6018_PPE_PORT_EDMA 0x0 +#define IPQ6018_PPE_PORT_QCOM1 0x1 +#define IPQ6018_PPE_PORT_QCOM2 0x2 +#define IPQ6018_PPE_PORT_QCOM3 0x3 +#define IPQ6018_PPE_PORT_QCOM4 0x6 +#define IPQ6018_PPE_PORT_XGMAC1 0x4 +#define IPQ6018_PPE_PORT_XGMAC2 0x5 +#define IPQ6018_PPE_PORT_CRYPTO1 0x7 +#define IPQ6018_PPE_PORT_BRIDGE_CTRL_PROMISC_EN 0x20000 +#define IPQ6018_PPE_PORT_BRIDGE_CTRL_TXMAC_EN 0x10000 +#define IPQ6018_PPE_PORT_BRIDGE_CTRL_PORT_ISOLATION_BMP 0x7f00 +#define IPQ6018_PPE_PORT_BRIDGE_CTRL_STATION_LRN_EN 0x8 +#define IPQ6018_PPE_PORT_BRIDGE_CTRL_NEW_ADDR_LRN_EN 0x1 + +#define IPQ6018_PPE_PORT_EDMA_BITPOS 0x1 +#define IPQ6018_PPE_PORT_QCOM1_BITPOS (1 << IPQ6018_PPE_PORT_QCOM1) +#define IPQ6018_PPE_PORT_QCOM2_BITPOS (1 << IPQ6018_PPE_PORT_QCOM2) +#define IPQ6018_PPE_PORT_QCOM3_BITPOS (1 << IPQ6018_PPE_PORT_QCOM3) +#define IPQ6018_PPE_PORT_QCOM4_BITPOS (1 << IPQ6018_PPE_PORT_QCOM4) +#define IPQ6018_PPE_PORT_XGMAC1_BITPOS (1 << IPQ6018_PPE_PORT_XGMAC1) +#define IPQ6018_PPE_PORT_XGMAC2_BITPOS (1 << IPQ6018_PPE_PORT_XGMAC2) +#define IPQ6018_PPE_PORT_CRYPTO1_BITPOS (1 << IPQ6018_PPE_PORT_CRYPTO1) + +#define PPE_SWITCH_NSS_SWITCH_XGMAC0 0x3000 +#define NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION 0x4000 +#define USS (1 << 31) +#define SS(i) (i << 29) +#define JD (1 << 16) +#define TE (1 << 0) +#define NSS_SWITCH_XGMAC_MAC_RX_CONFIGURATION 0x4000 +#define MAC_RX_CONFIGURATION_ADDRESS 0x4 +#define RE (1 << 0) +#define ACS (1 << 1) +#define CST (1 << 2) +#define MAC_PACKET_FILTER_INC 0x4000 +#define MAC_PACKET_FILTER_ADDRESS 0x8 + +#define XGMAC_SPEED_SELECT_10000M 0 +#define XGMAC_SPEED_SELECT_5000M 1 +#define XGMAC_SPEED_SELECT_2500M 2 +#define XGMAC_SPEED_SELECT_1000M 3 + +#define IPE_L2_BASE_ADDR 0x060000 +#define PORT_BRIDGE_CTRL_ADDRESS 0x300 +#define PORT_BRIDGE_CTRL_INC 0x4 +#define TX_MAC_EN (1 << 16) + +#define IPO_CSR_BASE_ADDR 0x0b0000 + +#define IPO_RULE_REG_ADDRESS 0x0 +#define IPO_RULE_REG_INC 0x10 + +#define IPO_MASK_REG_ADDRESS 0x2000 +#define IPO_MASK_REG_INC 0x10 + +#define IPO_ACTION_ADDRESS 0x8000 +#define IPO_ACTION_INC 0x20 diff --git a/sources/uboot-be550/drivers/net/ipq6018/ipq6018_uniphy.c b/sources/uboot-be550/drivers/net/ipq6018/ipq6018_uniphy.c new file mode 100644 index 00000000..47812a6e --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq6018/ipq6018_uniphy.c @@ -0,0 +1,367 @@ +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "ipq6018_edma.h" +#include "ipq6018_uniphy.h" +#include "ipq_phy.h" + +extern int ipq_mdio_write(int mii_id, + int regnum, u16 value); +extern int ipq_mdio_read(int mii_id, + int regnum, ushort *data); +extern void qca8075_phy_serdes_reset(u32 phy_id); + +void csr1_write(int phy_id, int addr, int value) +{ + int addr_h, addr_l, ahb_h, ahb_l, phy; + phy=phy_id<<(0x10); + addr_h=(addr&0xffffff)>>8; + addr_l=((addr&0xff)<<2)|(0x20<<(0xa)); + ahb_l=(addr_l&0xffff)|(0x7A00000|phy); + ahb_h=(0x7A083FC|phy); + writel(addr_h,ahb_h); + writel(value,ahb_l); +} + +int csr1_read(int phy_id, int addr ) +{ + int addr_h ,addr_l,ahb_h, ahb_l, phy; + phy=phy_id<<(0x10); + addr_h=(addr&0xffffff)>>8; + addr_l=((addr&0xff)<<2)|(0x20<<(0xa)); + ahb_l=(addr_l&0xffff)|(0x7A00000|phy); + ahb_h=(0x7A083FC|phy); + writel(addr_h, ahb_h); + return readl(ahb_l); +} + +static int ppe_uniphy_calibration(uint32_t uniphy_index) +{ + int retries = 100, calibration_done = 0; + uint32_t reg_value = 0; + + while(calibration_done != UNIPHY_CALIBRATION_DONE) { + mdelay(1); + if (retries-- == 0) { + printf("uniphy callibration time out!\n"); + return -1; + } + reg_value = readl(PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC) + + PPE_UNIPHY_OFFSET_CALIB_4); + calibration_done = (reg_value >> 0x7) & 0x1; + } + + return 0; +} + +static void ppe_gcc_uniphy_xpcs_reset(uint32_t uniphy_index, bool enable) +{ + uint32_t reg_value; + + reg_value = readl(GCC_UNIPHY0_MISC + (uniphy_index * GCC_UNIPHY_REG_INC)); + + if(enable) + reg_value |= GCC_UNIPHY_USXGMII_XPCS_RESET; + else + reg_value &= ~GCC_UNIPHY_USXGMII_XPCS_RESET; + + writel(reg_value, GCC_UNIPHY0_MISC + (uniphy_index * GCC_UNIPHY_REG_INC)); +} + +static void ppe_gcc_uniphy_soft_reset(uint32_t uniphy_index) +{ + uint32_t reg_value; + + reg_value = readl(GCC_UNIPHY0_MISC + (uniphy_index * GCC_UNIPHY_REG_INC)); + + if (uniphy_index == 0) + reg_value |= GCC_UNIPHY_PSGMII_SOFT_RESET; + else + reg_value |= GCC_UNIPHY_SGMII_SOFT_RESET; + + writel(reg_value, GCC_UNIPHY0_MISC + (uniphy_index * GCC_UNIPHY_REG_INC)); + + udelay(500); + + if (uniphy_index == 0) + reg_value &= ~GCC_UNIPHY_PSGMII_SOFT_RESET; + else + reg_value &= ~GCC_UNIPHY_SGMII_SOFT_RESET; + + writel(reg_value, GCC_UNIPHY0_MISC + (uniphy_index * GCC_UNIPHY_REG_INC)); +} + +static void ppe_uniphy_psgmii_mode_set(uint32_t uniphy_index) +{ + ppe_gcc_uniphy_xpcs_reset(uniphy_index, true); + writel(0x220, PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC) + + PPE_UNIPHY_MODE_CONTROL); + ppe_gcc_uniphy_soft_reset(uniphy_index); + ppe_uniphy_calibration(uniphy_index); + qca8075_phy_serdes_reset(0); +} + +static void ppe_uniphy_qsgmii_mode_set(uint32_t uniphy_index) +{ + ppe_gcc_uniphy_xpcs_reset(uniphy_index, true); + writel(0x120, PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC) + + PPE_UNIPHY_MODE_CONTROL); + ppe_gcc_uniphy_soft_reset(uniphy_index); +} + +static void ppe_uniphy_sgmii_mode_set(uint32_t uniphy_index, uint32_t mode) +{ + writel(UNIPHY_MISC2_REG_SGMII_MODE, PPE_UNIPHY_BASE + + (uniphy_index * PPE_UNIPHY_REG_INC) + UNIPHY_MISC2_REG_OFFSET); + + writel(UNIPHY_PLL_RESET_REG_VALUE, PPE_UNIPHY_BASE + + (uniphy_index * PPE_UNIPHY_REG_INC) + UNIPHY_PLL_RESET_REG_OFFSET); + mdelay(500); + writel(UNIPHY_PLL_RESET_REG_DEFAULT_VALUE, PPE_UNIPHY_BASE + + (uniphy_index * PPE_UNIPHY_REG_INC) + UNIPHY_PLL_RESET_REG_OFFSET); + mdelay(500); + ppe_gcc_uniphy_xpcs_reset(uniphy_index, true); + + if (uniphy_index == 0) { + writel(0x0, GCC_UNIPHY0_PORT4_RX_CBCR); + writel(0x0, GCC_UNIPHY0_PORT4_TX_CBCR); + writel(0x0, GCC_NSS_PORT4_RX_CBCR); + writel(0x0, GCC_NSS_PORT4_TX_CBCR); + } else { + writel(0x0, GCC_UNIPHY1_PORT5_RX_CBCR); + writel(0x0, GCC_UNIPHY1_PORT5_TX_CBCR); + writel(0x0, GCC_NSS_PORT5_RX_CBCR); + writel(0x0, GCC_NSS_PORT5_RX_CBCR); + } + + switch (mode) { + case PORT_WRAPPER_SGMII_FIBER: + writel(0x400, PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC) + + PPE_UNIPHY_MODE_CONTROL); + break; + + case PORT_WRAPPER_SGMII0_RGMII4: + case PORT_WRAPPER_SGMII1_RGMII4: + case PORT_WRAPPER_SGMII4_RGMII4: + writel(0x420, PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC) + + PPE_UNIPHY_MODE_CONTROL); + break; + + case PORT_WRAPPER_SGMII_PLUS: + writel(0x820, PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC) + + PPE_UNIPHY_MODE_CONTROL); + break; + + default: + printf("SGMII Config. wrongly"); + break; + } + + ppe_gcc_uniphy_soft_reset(uniphy_index); + + if (uniphy_index == 0) { + writel(0x1, GCC_UNIPHY0_PORT4_RX_CBCR); + writel(0x1, GCC_UNIPHY0_PORT4_TX_CBCR); + writel(0x1, GCC_NSS_PORT4_RX_CBCR); + writel(0x1, GCC_NSS_PORT4_TX_CBCR); + } else { + writel(0x1, GCC_UNIPHY1_PORT5_RX_CBCR); + writel(0x1, GCC_UNIPHY1_PORT5_TX_CBCR); + writel(0x1, GCC_NSS_PORT5_RX_CBCR); + writel(0x1, GCC_NSS_PORT5_RX_CBCR); + } + + ppe_uniphy_calibration(uniphy_index); +} + +static int ppe_uniphy_10g_r_linkup(uint32_t uniphy_index) +{ + uint32_t reg_value = 0; + uint32_t retries = 100, linkup = 0; + + while (linkup != UNIPHY_10GR_LINKUP) { + mdelay(1); + if (retries-- == 0) + return -1; + reg_value = csr1_read(uniphy_index, SR_XS_PCS_KR_STS1_ADDRESS); + linkup = (reg_value >> 12) & UNIPHY_10GR_LINKUP; + } + mdelay(10); + return 0; +} + +static void ppe_uniphy_10g_r_mode_set(uint32_t uniphy_index) +{ + ppe_gcc_uniphy_xpcs_reset(uniphy_index, true); + writel(0x1021, PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC) + + PPE_UNIPHY_MODE_CONTROL); + writel(0x1C0, PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC) + + UNIPHY_INSTANCE_LINK_DETECT); + ppe_gcc_uniphy_soft_reset(uniphy_index); + ppe_uniphy_calibration(uniphy_index); + ppe_gcc_uniphy_xpcs_reset(uniphy_index, false); +} + + +static void ppe_uniphy_usxgmii_mode_set(uint32_t uniphy_index) +{ + uint32_t reg_value = 0; + + writel(UNIPHY_MISC2_REG_VALUE, PPE_UNIPHY_BASE + + (uniphy_index * PPE_UNIPHY_REG_INC) + UNIPHY_MISC2_REG_OFFSET); + writel(UNIPHY_PLL_RESET_REG_VALUE, PPE_UNIPHY_BASE + + (uniphy_index * PPE_UNIPHY_REG_INC) + UNIPHY_PLL_RESET_REG_OFFSET); + mdelay(500); + writel(UNIPHY_PLL_RESET_REG_DEFAULT_VALUE, PPE_UNIPHY_BASE + + (uniphy_index * PPE_UNIPHY_REG_INC) + UNIPHY_PLL_RESET_REG_OFFSET); + mdelay(500); + ppe_gcc_uniphy_xpcs_reset(uniphy_index, true); + writel(0x1021, PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC) + + PPE_UNIPHY_MODE_CONTROL); + ppe_gcc_uniphy_soft_reset(uniphy_index); + ppe_uniphy_calibration(uniphy_index); + ppe_gcc_uniphy_xpcs_reset(uniphy_index, false); + ppe_uniphy_10g_r_linkup(uniphy_index); + reg_value = csr1_read(uniphy_index, VR_XS_PCS_DIG_CTRL1_ADDRESS); + reg_value |= USXG_EN; + csr1_write(uniphy_index, VR_XS_PCS_DIG_CTRL1_ADDRESS, reg_value); + reg_value = csr1_read(uniphy_index, VR_MII_AN_CTRL_ADDRESS); + reg_value |= MII_AN_INTR_EN; + reg_value |= MII_CTRL; + csr1_write(uniphy_index, VR_MII_AN_CTRL_ADDRESS, reg_value); + reg_value = csr1_read(uniphy_index, SR_MII_CTRL_ADDRESS); + reg_value |= AN_ENABLE; + reg_value &= ~SS5; + reg_value |= SS6 | SS13 | DUPLEX_MODE; + csr1_write(uniphy_index, SR_MII_CTRL_ADDRESS, reg_value); +} + +void ppe_uniphy_mode_set(uint32_t uniphy_index, uint32_t mode) +{ + switch(mode) { + case PORT_WRAPPER_PSGMII: + ppe_uniphy_psgmii_mode_set(uniphy_index); + break; + case PORT_WRAPPER_QSGMII: + ppe_uniphy_qsgmii_mode_set(uniphy_index); + break; + case PORT_WRAPPER_SGMII0_RGMII4: + case PORT_WRAPPER_SGMII1_RGMII4: + case PORT_WRAPPER_SGMII4_RGMII4: + case PORT_WRAPPER_SGMII_PLUS: + case PORT_WRAPPER_SGMII_FIBER: + ppe_uniphy_sgmii_mode_set(uniphy_index, mode); + break; + case PORT_WRAPPER_USXGMII: + ppe_uniphy_usxgmii_mode_set(uniphy_index); + break; + case PORT_WRAPPER_10GBASE_R: + ppe_uniphy_10g_r_mode_set(uniphy_index); + break; + default: + break; + } +} + +void ppe_uniphy_usxgmii_autoneg_completed(uint32_t uniphy_index) +{ + uint32_t autoneg_complete = 0, retries = 100; + uint32_t reg_value = 0; + + while (autoneg_complete != 0x1) { + mdelay(1); + if (retries-- == 0) + { + return; + } + reg_value = csr1_read(uniphy_index, VR_MII_AN_INTR_STS); + autoneg_complete = reg_value & 0x1; + } + reg_value &= ~CL37_ANCMPLT_INTR; + csr1_write(uniphy_index, VR_MII_AN_INTR_STS, reg_value); +} + +void ppe_uniphy_usxgmii_speed_set(uint32_t uniphy_index, int speed) +{ + uint32_t reg_value = 0; + + reg_value = csr1_read(uniphy_index, SR_MII_CTRL_ADDRESS); + reg_value |= DUPLEX_MODE; + + switch(speed) { + case 0: + reg_value &=~SS5; + reg_value &=~SS6; + reg_value &=~SS13; + break; + case 1: + reg_value &=~SS5; + reg_value &=~SS6; + reg_value |=SS13; + break; + case 2: + reg_value &=~SS5; + reg_value |=SS6; + reg_value &=~SS13; + break; + case 3: + reg_value &=~SS5; + reg_value |=SS6; + reg_value |=SS13; + break; + case 4: + reg_value |=SS5; + reg_value &=~SS6; + reg_value &=~SS13; + break; + case 5: + reg_value |=SS5; + reg_value &=~SS6; + reg_value |=SS13; + break; + } + csr1_write(uniphy_index, SR_MII_CTRL_ADDRESS, reg_value); + +} + +void ppe_uniphy_usxgmii_duplex_set(uint32_t uniphy_index, int duplex) +{ + uint32_t reg_value = 0; + + reg_value = csr1_read(uniphy_index, SR_MII_CTRL_ADDRESS); + + if (duplex & 0x1) + reg_value |= DUPLEX_MODE; + else + reg_value &= ~DUPLEX_MODE; + + csr1_write(uniphy_index, SR_MII_CTRL_ADDRESS, reg_value); +} + +void ppe_uniphy_usxgmii_port_reset(uint32_t uniphy_index) +{ + uint32_t reg_value = 0; + + reg_value = csr1_read(uniphy_index, VR_XS_PCS_DIG_CTRL1_ADDRESS); + reg_value |= USRA_RST; + csr1_write(uniphy_index, VR_XS_PCS_DIG_CTRL1_ADDRESS, reg_value); +} diff --git a/sources/uboot-be550/drivers/net/ipq6018/ipq6018_uniphy.h b/sources/uboot-be550/drivers/net/ipq6018/ipq6018_uniphy.h new file mode 100644 index 00000000..4763fd23 --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq6018/ipq6018_uniphy.h @@ -0,0 +1,86 @@ +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#define PPE_UNIPHY_INSTANCE0 0 +#define PPE_UNIPHY_INSTANCE1 1 + +#define GCC_UNIPHY1_PORT5_RX_CBCR 0x1856110 +#define GCC_UNIPHY1_PORT5_TX_CBCR 0x1856114 +#define GCC_NSS_PORT5_RX_CBCR 0x1868260 +#define GCC_NSS_PORT5_TX_CBCR 0x1868264 + +#define GCC_UNIPHY0_PORT4_RX_CBCR 0x1856028 +#define GCC_UNIPHY0_PORT4_TX_CBCR 0x185602C +#define GCC_NSS_PORT4_RX_CBCR 0x1868258 +#define GCC_NSS_PORT4_TX_CBCR 0x186825C + +#define GCC_UNIPHY0_MISC 0x01856004 +#define GCC_UNIPHY_REG_INC 0x100 +#define GCC_UNIPHY_USXGMII_XPCS_RESET 0x4 + +#define PPE_UNIPHY_OFFSET_CALIB_4 0x1E0 +#define UNIPHY_CALIBRATION_DONE 0x1 + +#define GCC_UNIPHY_PSGMII_SOFT_RESET 0x3ff2 +#define GCC_UNIPHY_SGMII_SOFT_RESET 0x32 + +#define PPE_UNIPHY_BASE 0X07A00000 +#define PPE_UNIPHY_REG_INC 0x10000 +#define PPE_UNIPHY_MODE_CONTROL 0x46C +#define UNIPHY_XPCS_MODE (1 << 12) +#define UNIPHY_SG_PLUS_MODE (1 << 11) +#define UNIPHY_SG_MODE (1 << 10) +#define UNIPHY_CH0_PSGMII_QSGMII (1 << 9) +#define UNIPHY_CH0_QSGMII_SGMII (1 << 8) +#define UNIPHY_CH4_CH1_0_SGMII (1 << 2) +#define UNIPHY_CH1_CH0_SGMII (1 << 1) +#define UNIPHY_CH0_ATHR_CSCO_MODE_25M (1 << 0) + +#define UNIPHY_INSTANCE_LINK_DETECT 0x570 + +#define UNIPHY_MISC2_REG_OFFSET 0x218 +#define UNIPHY_MISC2_REG_SGMII_MODE 0x30 +#define UNIPHY_MISC2_REG_SGMII_PLUS_MODE 0x50 + +#define UNIPHY_MISC2_REG_VALUE 0x70 + +#define UNIPHY_PLL_RESET_REG_OFFSET 0x780 +#define UNIPHY_PLL_RESET_REG_VALUE 0x02bf +#define UNIPHY_PLL_RESET_REG_DEFAULT_VALUE 0x02ff + +#define SR_XS_PCS_KR_STS1_ADDRESS 0x30020 +#define UNIPHY_10GR_LINKUP 0x1 + +#define VR_XS_PCS_DIG_CTRL1_ADDRESS 0x38000 +#define USXG_EN (1 << 9) +#define USRA_RST (1 << 10) + +#define VR_MII_AN_CTRL_ADDRESS 0x1f8001 +#define MII_AN_INTR_EN (1 << 0) +#define MII_CTRL (1 << 8) + +#define SR_MII_CTRL_ADDRESS 0x1f0000 +#define AN_ENABLE (1 << 12) +#define SS5 (1 << 5) +#define SS6 (1 << 6) +#define SS13 (1 << 13) +#define DUPLEX_MODE (1 << 8) + +#define VR_MII_AN_INTR_STS 0x1f8002 +#define CL37_ANCMPLT_INTR (1 << 0) + +void ppe_uniphy_mode_set(uint32_t uniphy_index, uint32_t mode); +void ppe_uniphy_usxgmii_port_reset(uint32_t uniphy_index); +void ppe_uniphy_usxgmii_duplex_set(uint32_t uniphy_index, int duplex); +void ppe_uniphy_usxgmii_speed_set(uint32_t uniphy_index, int speed); +void ppe_uniphy_usxgmii_autoneg_completed(uint32_t uniphy_index); diff --git a/sources/uboot-be550/drivers/net/ipq806x/athrs17_phy.c b/sources/uboot-be550/drivers/net/ipq806x/athrs17_phy.c new file mode 100644 index 00000000..ad4c1439 --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq806x/athrs17_phy.c @@ -0,0 +1,313 @@ +/* + * Copyright (c) 2015-2016 The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Manage the atheros ethernet PHY. + * + * All definitions in this file are operating system independent! + */ + +#include +#include +#include +#include + +/****************************************************************************** + * FUNCTION DESCRIPTION: Read switch internal register. + * Switch internal register is accessed through the + * MDIO interface. MDIO access is only 16 bits wide so + * it needs the two time access to complete the internal + * register access. + * INPUT : register address + * OUTPUT : Register value + * + *****************************************************************************/ +static uint32_t +athrs17_reg_read(ipq_gmac_board_cfg_t *gmac_cfg, uint32_t reg_addr) +{ + uint32_t reg_word_addr; + uint32_t phy_addr, reg_val; + uint16_t phy_val; + uint16_t tmp_val; + uint8_t phy_reg; + + /* change reg_addr to 16-bit word address, 32-bit aligned */ + reg_word_addr = (reg_addr & 0xfffffffc) >> 1; + + /* configure register high address */ + phy_addr = 0x18; + phy_reg = 0x0; + phy_val = (uint16_t) ((reg_word_addr >> 8) & 0x1ff); /* bit16-8 of reg address */ + miiphy_write(gmac_cfg->phy_name, phy_addr, phy_reg, phy_val); + + /* + * For some registers such as MIBs, since it is read/clear, we should + * read the lower 16-bit register then the higher one + */ + + /* read register in lower address */ + phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */ + phy_reg = (uint8_t) (reg_word_addr & 0x1f); /* bit4-0 of reg address */ + miiphy_read(gmac_cfg->phy_name, phy_addr, phy_reg, &phy_val); + + /* read register in higher address */ + reg_word_addr++; + phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */ + phy_reg = (uint8_t) (reg_word_addr & 0x1f); /* bit4-0 of reg address */ + miiphy_read(gmac_cfg->phy_name, phy_addr, phy_reg, &tmp_val); + reg_val = (tmp_val << 16 | phy_val); + + return reg_val; +} + +/****************************************************************************** + * FUNCTION DESCRIPTION: Write switch internal register. + * Switch internal register is accessed through the + * MDIO interface. MDIO access is only 16 bits wide so + * it needs the two time access to complete the internal + * register access. + * INPUT : register address, value to be written + * OUTPUT : NONE + * + *****************************************************************************/ +static void +athrs17_reg_write(ipq_gmac_board_cfg_t *gmac_cfg, uint32_t reg_addr, + uint32_t reg_val) +{ + uint32_t reg_word_addr; + uint32_t phy_addr; + uint16_t phy_val; + uint8_t phy_reg; + + /* change reg_addr to 16-bit word address, 32-bit aligned */ + reg_word_addr = (reg_addr & 0xfffffffc) >> 1; + + /* configure register high address */ + phy_addr = 0x18; + phy_reg = 0x0; + phy_val = (uint16_t) ((reg_word_addr >> 8) & 0x1ff); /* bit16-8 of reg address */ + miiphy_write(gmac_cfg->phy_name, phy_addr, phy_reg, phy_val); + + /* + * For some registers such as ARL and VLAN, since they include BUSY bit + * in lower address, we should write the higher 16-bit register then the + * lower one + */ + + /* read register in higher address */ + reg_word_addr++; + phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */ + phy_reg = (uint8_t) (reg_word_addr & 0x1f); /* bit4-0 of reg address */ + phy_val = (uint16_t) ((reg_val >> 16) & 0xffff); + miiphy_write(gmac_cfg->phy_name, phy_addr, phy_reg, phy_val); + + /* write register in lower address */ + reg_word_addr--; + phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */ + phy_reg = (uint8_t) (reg_word_addr & 0x1f); /* bit4-0 of reg address */ + phy_val = (uint16_t) (reg_val & 0xffff); + miiphy_write(gmac_cfg->phy_name, phy_addr, phy_reg, phy_val); +} + +/********************************************************************* + * FUNCTION DESCRIPTION: V-lan configuration given by Switch team + Vlan 1:PHY0,1,2,3 and Mac 6 of s17c + Vlan 2:PHY4 and Mac 0 of s17c + * INPUT : NONE + * OUTPUT: NONE + *********************************************************************/ +void athrs17_vlan_config(ipq_gmac_board_cfg_t *gmac_cfg) +{ + athrs17_reg_write(gmac_cfg, S17_P0LOOKUP_CTRL_REG, 0x00140020); + athrs17_reg_write(gmac_cfg, S17_P0VLAN_CTRL0_REG, 0x20001); + + athrs17_reg_write(gmac_cfg, S17_P1LOOKUP_CTRL_REG, 0x0014005c); + athrs17_reg_write(gmac_cfg, S17_P1VLAN_CTRL0_REG, 0x10001); + + athrs17_reg_write(gmac_cfg, S17_P2LOOKUP_CTRL_REG, 0x0014005a); + athrs17_reg_write(gmac_cfg, S17_P2VLAN_CTRL0_REG, 0x10001); + + athrs17_reg_write(gmac_cfg, S17_P3LOOKUP_CTRL_REG, 0x00140056); + athrs17_reg_write(gmac_cfg, S17_P3VLAN_CTRL0_REG, 0x10001); + + athrs17_reg_write(gmac_cfg, S17_P4LOOKUP_CTRL_REG, 0x0014004e); + athrs17_reg_write(gmac_cfg, S17_P4VLAN_CTRL0_REG, 0x10001); + + athrs17_reg_write(gmac_cfg, S17_P5LOOKUP_CTRL_REG, 0x00140001); + athrs17_reg_write(gmac_cfg, S17_P5VLAN_CTRL0_REG, 0x20001); + + athrs17_reg_write(gmac_cfg, S17_P6LOOKUP_CTRL_REG, 0x0014001e); + athrs17_reg_write(gmac_cfg, S17_P6VLAN_CTRL0_REG, 0x10001); + printf("%s ...done\n", __func__); +} + +/******************************************************************* +* FUNCTION DESCRIPTION: Reset S17 register +* INPUT: NONE +* OUTPUT: NONE +*******************************************************************/ +int athrs17_init_switch(ipq_gmac_board_cfg_t *gmac_cfg) +{ + uint32_t data; + uint32_t i = 0; + + /* Reset the switch before initialization */ + athrs17_reg_write(gmac_cfg, S17_MASK_CTRL_REG, S17_MASK_CTRL_SOFT_RET); + do { + udelay(10); + data = athrs17_reg_read(gmac_cfg, S17_MASK_CTRL_REG); + } while (data & S17_MASK_CTRL_SOFT_RET); + + do { + udelay(10); + data = athrs17_reg_read(gmac_cfg, S17_GLOBAL_INT0_REG); + i++; + if (i == 10) + return -1; + } while ((data & S17_GLOBAL_INITIALIZED_STATUS) != S17_GLOBAL_INITIALIZED_STATUS); + + return 0; +} + +/********************************************************************* + * FUNCTION DESCRIPTION: Configure S17 register + * INPUT : NONE + * OUTPUT: NONE + *********************************************************************/ +void athrs17_reg_init(ipq_gmac_board_cfg_t *gmac_cfg) +{ + uint32_t data; + + data = athrs17_reg_read(gmac_cfg, S17_MAC_PWR_REG) | gmac_cfg->mac_pwr0; + athrs17_reg_write(gmac_cfg, S17_MAC_PWR_REG, data); + + athrs17_reg_write(gmac_cfg, S17_P0STATUS_REG, (S17_SPEED_1000M | S17_TXMAC_EN | + S17_RXMAC_EN | S17_TX_FLOW_EN | + S17_RX_FLOW_EN | S17_DUPLEX_FULL)); + + athrs17_reg_write(gmac_cfg, S17_GLOFW_CTRL1_REG, (S17_IGMP_JOIN_LEAVE_DPALL | + S17_BROAD_DPALL | + S17_MULTI_FLOOD_DPALL | + S17_UNI_FLOOD_DPALL)); + + athrs17_reg_write(gmac_cfg, S17_P5PAD_MODE_REG, S17_MAC0_RGMII_RXCLK_DELAY); + athrs17_reg_write(gmac_cfg, S17_P0PAD_MODE_REG, (S17_MAC0_RGMII_EN | \ + S17_MAC0_RGMII_TXCLK_DELAY | S17_MAC0_RGMII_RXCLK_DELAY | \ + (0x1 << S17_MAC0_RGMII_TXCLK_SHIFT) | \ + (0x3 << S17_MAC0_RGMII_RXCLK_SHIFT))); + + printf("%s: complete\n", __func__); +} + +/********************************************************************* + * FUNCTION DESCRIPTION: Configure S17 register + * INPUT : NONE + * OUTPUT: NONE + *********************************************************************/ +void athrs17_reg_init_lan(ipq_gmac_board_cfg_t *gmac_cfg) +{ + uint32_t reg_val; + + athrs17_reg_write(gmac_cfg, S17_P6STATUS_REG, (S17_SPEED_1000M | S17_TXMAC_EN | + S17_RXMAC_EN | + S17_DUPLEX_FULL)); + + reg_val = athrs17_reg_read(gmac_cfg, S17_MAC_PWR_REG) | gmac_cfg->mac_pwr1; + athrs17_reg_write(gmac_cfg, S17_MAC_PWR_REG, reg_val); + + reg_val = athrs17_reg_read(gmac_cfg, S17_P6PAD_MODE_REG); + athrs17_reg_write(gmac_cfg, S17_P6PAD_MODE_REG, (reg_val | S17_MAC6_SGMII_EN)); + + reg_val = athrs17_reg_read(gmac_cfg, S17_PWS_REG); + athrs17_reg_write(gmac_cfg, S17_PWS_REG, (reg_val | + S17c_PWS_SERDES_ANEG_DISABLE)); + + athrs17_reg_write(gmac_cfg, S17_SGMII_CTRL_REG,(S17c_SGMII_EN_PLL | + S17c_SGMII_EN_RX | + S17c_SGMII_EN_TX | + S17c_SGMII_EN_SD | + S17c_SGMII_BW_HIGH | + S17c_SGMII_SEL_CLK125M | + S17c_SGMII_TXDR_CTRL_600mV | + S17c_SGMII_CDR_BW_8 | + S17c_SGMII_DIS_AUTO_LPI_25M | + S17c_SGMII_MODE_CTRL_SGMII_PHY | + S17c_SGMII_PAUSE_SG_TX_EN_25M | + S17c_SGMII_ASYM_PAUSE_25M | + S17c_SGMII_PAUSE_25M | + S17c_SGMII_HALF_DUPLEX_25M | + S17c_SGMII_FULL_DUPLEX_25M)); +} + +struct athrs17_regmap { + uint32_t start; + uint32_t end; +}; + +struct athrs17_regmap regmap[] = { + { 0x000, 0x0e0 }, + { 0x100, 0x168 }, + { 0x200, 0x270 }, + { 0x400, 0x454 }, + { 0x600, 0x718 }, + { 0x800, 0xb70 }, + { 0xC00, 0xC80 }, +}; + +int do_ar8xxx_dump(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { + int i; + + for (i = 0; i < ARRAY_SIZE(regmap); i++) { + uint32_t reg; + struct athrs17_regmap *section = ®map[i]; + + for (reg = section->start; reg <= section->end; reg += sizeof(uint32_t)) { + ipq_gmac_board_cfg_t *gmac_tmp_cfg = gmac_cfg; + uint32_t val = athrs17_reg_read(gmac_tmp_cfg, reg); + printf("%03zx: %08zx\n", reg, val); + } + } + + return 0; +}; +U_BOOT_CMD( + ar8xxx_dump, 1, 1, do_ar8xxx_dump, + "Dump ar8xxx registers", + "\n - print all ar8xxx registers\n" +); + +/********************************************************************* + * + * FUNCTION DESCRIPTION: This function invokes RGMII, + * SGMII switch init routines. + * INPUT : ipq_gmac_board_cfg_t * + * OUTPUT: NONE + * +**********************************************************************/ +int ipq_athrs17_init(ipq_gmac_board_cfg_t *gmac_cfg) +{ + int ret; + + if (gmac_cfg == NULL) + return -1; + + ret = athrs17_init_switch(gmac_cfg); + if (ret != -1) { + athrs17_reg_init(gmac_cfg); + athrs17_reg_init_lan(gmac_cfg); + athrs17_vlan_config(gmac_cfg); + printf ("S17c init done\n"); + } + + return ret; +} diff --git a/sources/uboot-be550/drivers/net/ipq806x/ipq_gmac_eth.c b/sources/uboot-be550/drivers/net/ipq806x/ipq_gmac_eth.c new file mode 100644 index 00000000..877d9be6 --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq806x/ipq_gmac_eth.c @@ -0,0 +1,1223 @@ +/* + * Copyright (c) 2012 - 2013, 2016-2017 The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define ipq_info printf +#define ipq_dbg printf +#define DESC_SIZE (sizeof(ipq_gmac_desc_t)) +#define DESC_FLUSH_SIZE (((DESC_SIZE + (CONFIG_SYS_CACHELINE_SIZE - 1)) \ + / CONFIG_SYS_CACHELINE_SIZE) * \ + (CONFIG_SYS_CACHELINE_SIZE)) + +uchar ipq_def_enetaddr[6] = {0x00, 0x03, 0x7F, 0xAB, 0xBD, 0xDA}; + +static struct ipq_eth_dev *ipq_gmac_macs[CONFIG_IPQ_NO_MACS]; +static int (*ipq_switch_init)(ipq_gmac_board_cfg_t *cfg); +static struct ipq_forced_mode get_params; +static struct bitbang_nodes *bb_nodes[CONFIG_IPQ_NO_MACS]; +static void ipq_gmac_mii_clk_init(struct ipq_eth_dev *priv, uint clk_div, + ipq_gmac_board_cfg_t *gmac_cfg); + +extern ipq_gmac_board_cfg_t gmac_cfg[]; + +DECLARE_GLOBAL_DATA_PTR; + +void ipq_register_switch(int(*sw_init)(ipq_gmac_board_cfg_t *cfg)) +{ + ipq_switch_init = sw_init; +} + +static void config_auto_neg(struct eth_device *dev) +{ + struct ipq_eth_dev *priv = dev->priv; + u8 phy_addr; + + if (priv->forced_params->is_forced) { + if (priv->forced_params->miiwrite_done) { + phy_addr = priv->forced_params->phy_addr; + if (priv->forced_params->speed == SPEED_10M) { + miiphy_write(priv->phy_name, phy_addr, + PHY_CONTROL_REG, FORCE_RATE_10); + } else if (priv->forced_params->speed == SPEED_100M) { + miiphy_write(priv->phy_name, phy_addr, + PHY_CONTROL_REG, FORCE_RATE_100); + } else if (priv->forced_params->speed == SPEED_1000M) { + miiphy_write(priv->phy_name, phy_addr, + PHY_CONTROL_REG, AUTO_NEG_ENABLE); + } + priv->forced_params->miiwrite_done = 0; + mdelay(200); + } + } else { + miiphy_write(priv->phy_name, priv->phy_address[0], + PHY_CONTROL_REG, AUTO_NEG_ENABLE); + } +} + +static int ipq_phy_link_status(struct eth_device *dev) +{ + struct ipq_eth_dev *priv = dev->priv; + int port_status; + ushort phy_status; + uint i; + + udelay(1000); + + for (i = 0; i < priv->no_of_phys; i++) { + + miiphy_read(priv->phy_name, priv->phy_address[i], + PHY_SPECIFIC_STATUS_REG, &phy_status); + + port_status = ((phy_status & Mii_phy_status_link_up) >> + (MII_PHY_STAT_SHIFT)); + if (port_status == 1) + return 0; + } + + return -1; +} + +static void get_phy_speed_duplexity(struct eth_device *dev) +{ + struct ipq_eth_dev *priv = dev->priv; + uint phy_status; + uint start; + const uint timeout = 2000; + + start = get_timer(0); + while (get_timer(start) < timeout) { + + phy_status = readl(QSGMII_REG_BASE + + PCS_QSGMII_MAC_STAT); + + if (PCS_QSGMII_MAC_LINK(phy_status, priv->mac_unit)) { + + priv->speed = + PCS_QSGMII_MAC_SPEED(phy_status, + priv->mac_unit); + + priv->duplex = + PCS_QSGMII_MAC_DUPLEX(phy_status, + priv->mac_unit); + + if (priv->duplex) + ipq_info("Full duplex link\n"); + else + ipq_info("Half duplex link\n"); + + ipq_info("Link %x up, Phy_status = %x\n", + priv->mac_unit,phy_status); + + break; + } + + udelay(10); + } +} + +static int ipq_eth_wr_macaddr(struct eth_device *dev) +{ + struct ipq_eth_dev *priv = dev->priv; + struct eth_mac_regs *mac_p = (struct eth_mac_regs *)priv->mac_regs_p; + u32 macid_lo, macid_hi; + u8 *mac_id = &dev->enetaddr[0]; + + macid_lo = mac_id[0] + (mac_id[1] << 8) + + (mac_id[2] << 16) + (mac_id[3] << 24); + macid_hi = mac_id[4] + (mac_id[5] << 8); + + writel(macid_hi, &mac_p->macaddr0hi); + writel(macid_lo, &mac_p->macaddr0lo); + + return 0; +} + +static void ipq_mac_reset(struct eth_device *dev) +{ + struct ipq_eth_dev *priv = dev->priv; + struct eth_dma_regs *dma_reg = (struct eth_dma_regs *)priv->dma_regs_p; + u32 val; + + writel(DMAMAC_SRST, &dma_reg->busmode); + do { + udelay(10); + val = readl(&dma_reg->busmode); + } while (val & DMAMAC_SRST); + +} + +static void ipq_eth_mac_cfg(struct eth_device *dev) +{ + struct ipq_eth_dev *priv = dev->priv; + struct eth_mac_regs *mac_reg = (struct eth_mac_regs *)priv->mac_regs_p; + + uint ipq_mac_cfg; + + if (priv->mac_unit > GMAC_UNIT1) { + ipq_mac_cfg = (priv->mac_ps | FULL_DUPLEX_ENABLE); + } else { + ipq_mac_cfg = (GMII_PORT_SELECT | FULL_DUPLEX_ENABLE); + } + + ipq_mac_cfg |= (FRAME_BURST_ENABLE | TX_ENABLE | RX_ENABLE); + + writel(ipq_mac_cfg, &mac_reg->conf); +} + +static void ipq_eth_dma_cfg(struct eth_device *dev) +{ + struct ipq_eth_dev *priv = dev->priv; + struct eth_dma_regs *dma_reg = (struct eth_dma_regs *)priv->dma_regs_p; + uint ipq_dma_bus_mode; + uint ipq_dma_op_mode; + + ipq_dma_op_mode = DmaStoreAndForward | DmaRxThreshCtrl128 | + DmaTxSecondFrame; + ipq_dma_bus_mode = DmaFixedBurstEnable | DmaBurstLength16 | + DmaDescriptorSkip0 | DmaDescriptor8Words | + DmaArbitPr; + + writel(ipq_dma_bus_mode, &dma_reg->busmode); + writel(ipq_dma_op_mode, &dma_reg->opmode); +} + +static void ipq_eth_flw_cntl_cfg(struct eth_device *dev) +{ + struct ipq_eth_dev *priv = dev->priv; + struct eth_mac_regs *mac_reg = (struct eth_mac_regs *)priv->mac_regs_p; + struct eth_dma_regs *dma_reg = (struct eth_dma_regs *)priv->dma_regs_p; + uint ipq_dma_flw_cntl; + uint ipq_mac_flw_cntl; + + ipq_dma_flw_cntl = DmaRxFlowCtrlAct3K | DmaRxFlowCtrlDeact4K | + DmaEnHwFlowCtrl; + ipq_mac_flw_cntl = GmacRxFlowControl | GmacTxFlowControl | 0xFFFF0000; + + setbits_le32(&dma_reg->opmode, ipq_dma_flw_cntl); + setbits_le32(&mac_reg->flowcontrol, ipq_mac_flw_cntl); +} + +static int ipq_gmac_alloc_fifo(int ndesc, ipq_gmac_desc_t **fifo) +{ + int i; + void *addr; + + addr = memalign((CONFIG_SYS_CACHELINE_SIZE), + (ndesc * DESC_FLUSH_SIZE)); + + for (i = 0; i < ndesc; i++) { + fifo[i] = (ipq_gmac_desc_t *)((unsigned long)addr + + (i * DESC_FLUSH_SIZE)); + if (fifo[i] == NULL) { + ipq_info("Can't allocate desc fifos\n"); + return -1; + } + } + return 0; +} + +static int ipq_gmac_rx_desc_setup(struct ipq_eth_dev *priv) +{ + struct eth_dma_regs *dma_reg = (struct eth_dma_regs *)priv->dma_regs_p; + ipq_gmac_desc_t *rxdesc; + int i; + + for (i = 0; i < NO_OF_RX_DESC; i++) { + rxdesc = priv->desc_rx[i]; + rxdesc->length |= ((ETH_MAX_FRAME_LEN << DescSize1Shift) & + DescSize1Mask); + rxdesc->buffer1 = virt_to_phys(net_rx_packets[i]); + rxdesc->data1 = (unsigned long)priv->desc_rx[(i + 1) % + NO_OF_RX_DESC]; + + rxdesc->extstatus = 0; + rxdesc->reserved1 = 0; + rxdesc->timestamplow = 0; + rxdesc->timestamphigh = 0; + rxdesc->status = DescOwnByDma; + + + flush_dcache_range((unsigned long)rxdesc, + (unsigned long)rxdesc + DESC_SIZE); + + } + /* Assign Descriptor base address to dmadesclist addr reg */ + writel((uint)priv->desc_rx[0], &dma_reg->rxdesclistaddr); + + return 0; +} + +static int ipq_gmac_tx_rx_desc_ring(struct ipq_eth_dev *priv) +{ + int i; + ipq_gmac_desc_t *desc; + + if (ipq_gmac_alloc_fifo(NO_OF_TX_DESC, priv->desc_tx)) + return -1; + + for (i = 0; i < NO_OF_TX_DESC; i++) { + desc = priv->desc_tx[i]; + memset(desc, 0, DESC_SIZE); + + desc->status = + (i == (NO_OF_TX_DESC - 1)) ? TxDescEndOfRing : 0; + + desc->status |= TxDescChain; + + desc->data1 = (unsigned long)priv->desc_tx[(i + 1) % + NO_OF_TX_DESC ]; + + flush_dcache_range((unsigned long)desc, + (unsigned long)desc + DESC_SIZE); + + } + + if (ipq_gmac_alloc_fifo(NO_OF_RX_DESC, priv->desc_rx)) + return -1; + + for (i = 0; i < NO_OF_RX_DESC; i++) { + desc = priv->desc_rx[i]; + memset(desc, 0, DESC_SIZE); + desc->length = + (i == (NO_OF_RX_DESC - 1)) ? RxDescEndOfRing : 0; + desc->length |= RxDescChain; + + desc->data1 = (unsigned long)priv->desc_rx[(i + 1) % + NO_OF_RX_DESC]; + + flush_dcache_range((unsigned long)desc, + (unsigned long)desc + DESC_SIZE); + + } + + priv->next_tx = 0; + priv->next_rx = 0; + + return 0; +} + +static inline void ipq_gmac_give_to_dma(ipq_gmac_desc_t *fr) +{ + fr->status |= DescOwnByDma; +} + +static inline u32 ipq_gmac_owned_by_dma(ipq_gmac_desc_t *fr) +{ + return (fr->status & DescOwnByDma); +} + +static inline u32 ipq_gmac_is_desc_empty(ipq_gmac_desc_t *fr) +{ + return ((fr->length & DescSize1Mask) == 0); +} + +static int ipq_eth_update(struct eth_device *dev, bd_t *this) +{ + struct ipq_eth_dev *priv = dev->priv; + uint clk_div_val; + uint phy_status; + uint cur_speed; + uint cur_duplex; + + phy_status = readl(QSGMII_REG_BASE + + PCS_QSGMII_MAC_STAT); + + if (PCS_QSGMII_MAC_LINK(phy_status, priv->mac_unit)) { + cur_speed = PCS_QSGMII_MAC_SPEED(phy_status, + priv->mac_unit); + cur_duplex = PCS_QSGMII_MAC_DUPLEX(phy_status, + priv->mac_unit); + + if (cur_speed != priv->speed || cur_duplex != priv->duplex) { + ipq_info("Link %x status changed\n", priv->mac_unit); + if (priv->duplex) + ipq_info("Full duplex link\n"); + else + ipq_info("Half duplex link\n"); + + ipq_info("Link %x up, Phy_status = %x\n", + priv->mac_unit, phy_status); + + switch (cur_speed) { + case SPEED_1000M: + ipq_info("Port:%d speed 1000Mbps\n", + priv->mac_unit); + priv->mac_ps = GMII_PORT_SELECT; + clk_div_val = (CLK_DIV_SGMII_1000M - 1); + break; + + case SPEED_100M: + ipq_info("Port:%d speed 100Mbps\n", + priv->mac_unit); + priv->mac_ps = MII_PORT_SELECT; + clk_div_val = (CLK_DIV_SGMII_100M - 1); + break; + + case SPEED_10M: + ipq_info("Port:%d speed 10Mbps\n", + priv->mac_unit); + priv->mac_ps = MII_PORT_SELECT; + clk_div_val = (CLK_DIV_SGMII_10M - 1); + break; + + default: + ipq_info("Port speed unknown\n"); + return -1; + } + + priv->speed = cur_speed; + priv->duplex = cur_duplex; + + ipq_gmac_mii_clk_init(priv, clk_div_val, + priv->gmac_board_cfg); + } + } else { + return -1; + } + + return 0; +} + +int ipq_eth_init(struct eth_device *dev, bd_t *this) +{ + struct ipq_eth_dev *priv = dev->priv; + struct eth_dma_regs *dma_reg = (struct eth_dma_regs *)priv->dma_regs_p; + u32 data; + + if (!(priv->forced_params->is_forced && (priv->mac_unit == GMAC_UNIT2 || + priv->mac_unit == GMAC_UNIT3))) { + if (ipq_phy_link_status(dev) != 0) { + ipq_info("Mac%x unit failed\n", priv->mac_unit); + return -1; + } + + if (priv->gmac_board_cfg->mac_conn_to_phy) { + /* Check the current speed and duplex mode and change + the MAC settings according to it */ + if (ipq_eth_update(dev, this) != 0) { + ipq_info("Mac%x settings update failed\n", + priv->mac_unit); + return -1; + } + } + } + + priv->next_rx = 0; + priv->next_tx = 0; + + ipq_mac_reset(dev); + + if ((priv->mac_unit == GMAC_UNIT2) || (priv->mac_unit == GMAC_UNIT3)) + config_auto_neg(dev); + + ipq_eth_wr_macaddr(dev); + + + /* DMA, MAC configuration for Synopsys GMAC */ + ipq_eth_dma_cfg(dev); + ipq_eth_mac_cfg(dev); + ipq_eth_flw_cntl_cfg(dev); + + /* clear all pending interrupts if any */ + data = readl(&dma_reg->status); + writel(data, &dma_reg->status); + + /* Setup Rx fifos and assign base address to */ + ipq_gmac_rx_desc_setup(priv); + + writel((uint)priv->desc_tx[0], &dma_reg->txdesclistaddr); + setbits_le32(&dma_reg->opmode, (RXSTART)); + setbits_le32(&dma_reg->opmode, (TXSTART)); + + return 1; +} + +static int ipq_eth_send(struct eth_device *dev, void *packet, int length) +{ + struct ipq_eth_dev *priv = dev->priv; + struct eth_dma_regs *dma_p = (struct eth_dma_regs *)priv->dma_regs_p; + ipq_gmac_desc_t *txdesc = priv->desc_tx[priv->next_tx]; + int i; + + + + invalidate_dcache_range((unsigned long)txdesc, + (unsigned long)txdesc + DESC_FLUSH_SIZE); + + + /* Check if the dma descriptor is still owned by DMA */ + if (ipq_gmac_owned_by_dma(txdesc)) { + ipq_info("BUG: Tx descriptor is owned by DMA %p\n", txdesc); + return NETDEV_TX_BUSY; + } + + txdesc->length |= ((length <status |= (DescTxFirst | DescTxLast | DescTxIntEnable); + txdesc->buffer1 = virt_to_phys(packet); + ipq_gmac_give_to_dma(txdesc); + + + flush_dcache_range((unsigned long)txdesc, + (unsigned long)txdesc + DESC_SIZE); + + flush_dcache_range((unsigned long)(txdesc->buffer1), + (unsigned long)(txdesc->buffer1) + PKTSIZE_ALIGN); + + /* Start the transmission */ + writel(POLL_DATA, &dma_p->txpolldemand); + + for (i = 0; i < MAX_WAIT; i++) { + + udelay(10); + + + invalidate_dcache_range((unsigned long)txdesc, + (unsigned long)txdesc + DESC_FLUSH_SIZE); + + if (!ipq_gmac_owned_by_dma(txdesc)) + break; + } + + if (i == MAX_WAIT) { + ipq_info("Tx Timed out\n"); + } + + /* reset the descriptors */ + txdesc->status = (priv->next_tx == (NO_OF_TX_DESC - 1)) ? + TxDescEndOfRing : 0; + txdesc->status |= TxDescChain; + txdesc->length = 0; + txdesc->buffer1 = 0; + + priv->next_tx = (priv->next_tx + 1) % NO_OF_TX_DESC; + + txdesc->data1 = (unsigned long)priv->desc_tx[priv->next_tx]; + + + flush_dcache_range((unsigned long)txdesc, + (unsigned long)txdesc + DESC_SIZE); + + return 0; +} + +static int ipq_eth_recv(struct eth_device *dev) +{ + struct ipq_eth_dev *priv = dev->priv; + struct eth_dma_regs *dma_p = (struct eth_dma_regs *)priv->dma_regs_p; + int length = 0; + ipq_gmac_desc_t *rxdesc = priv->desc_rx[priv->next_rx]; + uint status; + + invalidate_dcache_range((unsigned long)(priv->desc_rx[0]), + (unsigned long)(priv->desc_rx[NO_OF_RX_DESC - 1]) + + DESC_FLUSH_SIZE); + + for (rxdesc = priv->desc_rx[priv->next_rx]; + !ipq_gmac_owned_by_dma(rxdesc); + rxdesc = priv->desc_rx[priv->next_rx]) { + + status = rxdesc->status; + length = ((status & DescFrameLengthMask) >> + DescFrameLengthShift); + + + invalidate_dcache_range( + (unsigned long)(net_rx_packets[priv->next_rx]), + (unsigned long)(net_rx_packets[priv->next_rx]) + + PKTSIZE_ALIGN); + net_process_received_packet(net_rx_packets[priv->next_rx], length - 4); + + + rxdesc->length = ((ETH_MAX_FRAME_LEN << DescSize1Shift) & + DescSize1Mask); + + rxdesc->length |= (priv->next_rx == (NO_OF_RX_DESC - 1)) ? + RxDescEndOfRing : 0; + rxdesc->length |= RxDescChain; + + rxdesc->buffer1 = virt_to_phys(net_rx_packets[priv->next_rx]); + + priv->next_rx = (priv->next_rx + 1) % NO_OF_RX_DESC; + + rxdesc->data1 = (unsigned long)priv->desc_rx[priv->next_rx]; + + rxdesc->extstatus = 0; + rxdesc->reserved1 = 0; + rxdesc->timestamplow = 0; + rxdesc->timestamphigh = 0; + rxdesc->status = DescOwnByDma; + + + flush_dcache_range((unsigned long)rxdesc, + (unsigned long)rxdesc + DESC_SIZE); + + + writel(POLL_DATA, &dma_p->rxpolldemand); + } + + return length; +} + +static void ipq_eth_halt(struct eth_device *dev) +{ + if (dev->state != ETH_STATE_ACTIVE) + return; + /* reset the mac */ + ipq_mac_reset(dev); +} + +static void +gmac_sgmii_clk_init(uint mac_unit, uint clk_div, ipq_gmac_board_cfg_t *gmac_cfg) +{ + uint gmac_ctl_val; + uint nss_eth_clk_gate_val; + + gmac_ctl_val = (NSS_ETH_GMAC_PHY_INTF_SEL | + NSS_ETH_GMAC_PHY_IFG_LIMIT | + NSS_ETH_GMAC_PHY_IFG); + + + nss_eth_clk_gate_val = (GMACn_GMII_RX_CLK(mac_unit) | + GMACn_GMII_TX_CLK(mac_unit) | + GMACn_PTP_CLK(mac_unit)); + + writel(gmac_ctl_val, (NSS_REG_BASE + NSS_GMACn_CTL(mac_unit))); + + if (gmac_cfg->phy == PHY_INTERFACE_MODE_QSGMII) { + nss_eth_clk_gate_val = GMACn_GMII_RX_CLK(mac_unit) | + GMACn_GMII_TX_CLK(mac_unit); + clrbits_le32((NSS_REG_BASE + NSS_ETH_CLK_SRC_CTL), + (1 << mac_unit)); + writel(NSS_QSGMII_CLK_CTL_CLR_MSK, + (NSS_REG_BASE + NSS_QSGMII_CLK_CTL)); + setbits_le32((NSS_REG_BASE + NSS_ETH_CLK_DIV0), + GMACn_CLK_DIV(mac_unit, 1)); + } + + switch (mac_unit) { + case GMAC_UNIT0: + case GMAC_UNIT1: + setbits_le32((QSGMII_REG_BASE + PCS_ALL_CH_CTL), + PCS_CHn_FORCE_SPEED(mac_unit)); + clrbits_le32((QSGMII_REG_BASE + PCS_ALL_CH_CTL), + PCS_CHn_SPEED_MASK(mac_unit)); + setbits_le32((QSGMII_REG_BASE + PCS_ALL_CH_CTL), + PCS_CHn_SPEED(mac_unit, + PCS_CH_SPEED_1000)); + setbits_le32((NSS_REG_BASE + NSS_ETH_CLK_GATE_CTL), + nss_eth_clk_gate_val); + break; + case GMAC_UNIT2: + case GMAC_UNIT3: + setbits_le32((NSS_REG_BASE + NSS_ETH_CLK_SRC_CTL), + (1 << mac_unit)); + if (gmac_cfg->mac_conn_to_phy) { + + setbits_le32((QSGMII_REG_BASE + PCS_ALL_CH_CTL), + (PCS_CHn_SPEED_FORCE_OUTSIDE(mac_unit) | + PCS_DEBUG_SELECT)); + + + if (clk_div == 0) { + clrbits_le32((NSS_REG_BASE + + NSS_ETH_CLK_DIV0), + (NSS_ETH_CLK_DIV( + NSS_ETH_CLK_DIV_MASK, + mac_unit))); + } else { + clrsetbits_le32((NSS_REG_BASE + + NSS_ETH_CLK_DIV0), + (NSS_ETH_CLK_DIV( + NSS_ETH_CLK_DIV_MASK, + mac_unit)), + (NSS_ETH_CLK_DIV(clk_div, + mac_unit))); + } + setbits_le32((NSS_REG_BASE + NSS_ETH_CLK_GATE_CTL), + nss_eth_clk_gate_val); + } else { + /* this part of code forces the speed of MAC 2 to + * 1000Mbps disabling the Autoneg in case + * of AP148/DB147 since it is connected to switch + */ + setbits_le32((QSGMII_REG_BASE + PCS_ALL_CH_CTL), + PCS_CHn_FORCE_SPEED(mac_unit)); + + clrbits_le32((QSGMII_REG_BASE + PCS_ALL_CH_CTL), + PCS_CHn_SPEED_MASK(mac_unit)); + + setbits_le32((QSGMII_REG_BASE + PCS_ALL_CH_CTL), + PCS_CHn_SPEED(mac_unit, + PCS_CH_SPEED_1000)); + + setbits_le32((NSS_REG_BASE + NSS_ETH_CLK_GATE_CTL), + nss_eth_clk_gate_val); + } + break; + } +} + +static void ipq_gmac_mii_clk_init(struct ipq_eth_dev *priv, uint clk_div, + ipq_gmac_board_cfg_t *gmac_cfg) +{ + u32 nss_gmac_ctl_val; + u32 nss_eth_clk_gate_ctl_val; + int gmac_idx = priv->mac_unit; + u32 interface = priv->interface; + + switch (interface) { + case PHY_INTERFACE_MODE_RGMII: + nss_gmac_ctl_val = (GMAC_PHY_RGMII | GMAC_IFG | + GMAC_IFG_LIMIT(GMAC_IFG)); + nss_eth_clk_gate_ctl_val = + (GMACn_RGMII_RX_CLK(gmac_idx) | + GMACn_RGMII_TX_CLK(gmac_idx) | + GMACn_PTP_CLK(gmac_idx)); + setbits_le32((NSS_REG_BASE + NSS_GMACn_CTL(gmac_idx)), + nss_gmac_ctl_val); + setbits_le32((NSS_REG_BASE + NSS_ETH_CLK_GATE_CTL), + nss_eth_clk_gate_ctl_val); + setbits_le32((NSS_REG_BASE + NSS_ETH_CLK_SRC_CTL), + (0x1 << gmac_idx)); + writel((NSS_ETH_CLK_DIV(1, gmac_idx)), + (NSS_REG_BASE + NSS_ETH_CLK_DIV0)); + break; + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_QSGMII: + gmac_sgmii_clk_init(gmac_idx, clk_div, gmac_cfg); + break; + default : + ipq_info(" default : no rgmii sgmii for gmac %d \n", gmac_idx); + return; + } +} + +int ipq_gmac_init(ipq_gmac_board_cfg_t *gmac_cfg) +{ + static int sw_init_done = 0; + struct eth_device *dev[CONFIG_IPQ_NO_MACS]; + uint clk_div_val; + uchar enet_addr[CONFIG_IPQ_NO_MACS * 6]; + uchar *mac_addr; + char ethaddr[32] = "ethaddr"; + char mac[64]; + int i, phy_idx; + int ret; + int gmac_gpio_node = 0, ar8033_gpio_node = 0, offset = 0; + memset(enet_addr, 0, sizeof(enet_addr)); + + /* Getting the MAC address from ART partition */ + ret = get_eth_mac_address(enet_addr, CONFIG_IPQ_NO_MACS); + + for (i = 0; gmac_cfg_is_valid(gmac_cfg); gmac_cfg++, i++) { + + dev[i] = malloc(sizeof(struct eth_device)); + if (dev[i] == NULL) + goto failed; + + ipq_gmac_macs[i] = malloc(sizeof(struct ipq_eth_dev)); + if (ipq_gmac_macs[i] == NULL) + goto failed; + + memset(dev[i], 0, sizeof(struct eth_device)); + memset(ipq_gmac_macs[i], 0, sizeof(struct ipq_eth_dev)); + + dev[i]->iobase = gmac_cfg->base; + dev[i]->init = ipq_eth_init; + dev[i]->halt = ipq_eth_halt; + dev[i]->recv = ipq_eth_recv; + dev[i]->send = ipq_eth_send; + dev[i]->write_hwaddr = ipq_eth_wr_macaddr; + dev[i]->priv = (void *) ipq_gmac_macs[i]; + + snprintf(dev[i]->name, sizeof(dev[i]->name), "eth%d", i); + + /* + * Setting the Default MAC address if the MAC read from ART partition + * is invalid. + */ + if ((ret < 0) || + (!is_valid_ethaddr(&enet_addr[i * 6]))) { + memcpy(&dev[i]->enetaddr[0], ipq_def_enetaddr, 6); + dev[i]->enetaddr[5] = gmac_cfg->unit & 0xff; + } else { + memcpy(&dev[i]->enetaddr[0], &enet_addr[i * 6], 6); + + /* + * Populate the environment with these MAC addresses. + * U-Boot uses these to patch the 'local-mac-address' + * dts entry for the ethernet entries, which in turn + * will be picked up by the HLOS driver + */ + snprintf(mac, sizeof(mac), "%x:%x:%x:%x:%x:%x", + dev[i]->enetaddr[0], dev[i]->enetaddr[1], + dev[i]->enetaddr[2], dev[i]->enetaddr[3], + dev[i]->enetaddr[4], dev[i]->enetaddr[5]); + + setenv(ethaddr, mac); + + } + + ipq_info("MAC%x addr:%x:%x:%x:%x:%x:%x\n", + gmac_cfg->unit, dev[i]->enetaddr[0], + dev[i]->enetaddr[1], + dev[i]->enetaddr[2], + dev[i]->enetaddr[3], + dev[i]->enetaddr[4], + dev[i]->enetaddr[5]); + + + snprintf(ethaddr, sizeof(ethaddr), "eth%daddr", (i + 1)); + + ipq_gmac_macs[i]->dev = dev[i]; + ipq_gmac_macs[i]->mac_unit = gmac_cfg->unit; + ipq_gmac_macs[i]->mac_regs_p = + (struct eth_mac_regs *)(gmac_cfg->base); + ipq_gmac_macs[i]->dma_regs_p = + (struct eth_dma_regs *)(gmac_cfg->base + DW_DMA_BASE_OFFSET); + ipq_gmac_macs[i]->interface = gmac_cfg->phy; + ipq_gmac_macs[i]->phy_address = gmac_cfg->phy_addr.addr; + ipq_gmac_macs[i]->no_of_phys = gmac_cfg->phy_addr.count; + ipq_gmac_macs[i]->gmac_board_cfg = gmac_cfg; + + if (get_params.gmac_port == gmac_cfg->unit) { + ipq_gmac_macs[i]->forced_params = &get_params; + } + /* tx/rx Descriptor initialization */ + if (ipq_gmac_tx_rx_desc_ring(dev[i]->priv) == -1) + goto failed; + + if ((gmac_cfg->unit == GMAC_UNIT2 || + gmac_cfg->unit == GMAC_UNIT3) && + (gmac_cfg->mac_conn_to_phy)) { + if (ipq_gmac_macs[i]->forced_params->is_forced) { + ipq_gmac_macs[i]->speed = ipq_gmac_macs[i]->forced_params->speed; + } else { + get_phy_speed_duplexity(dev[i]); + } + switch (ipq_gmac_macs[i]->speed) { + case SPEED_1000M: + ipq_info("Port:%d speed 1000Mbps\n", + gmac_cfg->unit); + ipq_gmac_macs[i]->mac_ps = GMII_PORT_SELECT; + clk_div_val = (CLK_DIV_SGMII_1000M - 1); + break; + case SPEED_100M: + ipq_info("Port:%d speed 100Mbps\n", + gmac_cfg->unit); + ipq_gmac_macs[i]->mac_ps = MII_PORT_SELECT; + clk_div_val = (CLK_DIV_SGMII_100M - 1); + break; + case SPEED_10M: + ipq_info("Port:%d speed 10Mbps\n", + gmac_cfg->unit); + ipq_gmac_macs[i]->mac_ps = MII_PORT_SELECT; + clk_div_val = (CLK_DIV_SGMII_10M - 1); + break; + default: + ipq_info("Port speed unknown\n"); + goto failed; + } + } else { + /* Force it to zero for GMAC 0 & 1 */ + clk_div_val = 0; + } + + ipq_gmac_mii_clk_init(ipq_gmac_macs[i], clk_div_val, gmac_cfg); + + strlcpy((char *)ipq_gmac_macs[i]->phy_name, gmac_cfg->phy_name, + sizeof(ipq_gmac_macs[i]->phy_name)); + bb_nodes[i] = malloc(sizeof(struct bitbang_nodes)); + if (bb_nodes[i] == NULL) + goto failed; + memset(bb_nodes[i], 0, sizeof(struct bitbang_nodes)); + + gmac_gpio_node = fdt_path_offset(gd->fdt_blob, "gmac_gpio"); + if (gmac_gpio_node >= 0) { + offset = fdt_first_subnode(gd->fdt_blob, gmac_gpio_node); + bb_nodes[i]->mdio = fdtdec_get_uint(gd->fdt_blob, offset, "gpio", 0); + + offset = fdt_next_subnode(gd->fdt_blob, offset); + bb_nodes[i]->mdc = fdtdec_get_uint(gd->fdt_blob, offset, "gpio", 0); + bb_miiphy_buses[i].priv = bb_nodes[i]; + strncpy(bb_miiphy_buses[i].name, gmac_cfg->phy_name, + sizeof(bb_miiphy_buses[i].name)); + miiphy_register(bb_miiphy_buses[i].name, bb_miiphy_read, bb_miiphy_write); + for (phy_idx = 0; phy_idx < ipq_gmac_macs[i]->no_of_phys; phy_idx++) { + miiphy_write(bb_miiphy_buses[i].name, + ipq_gmac_macs[i]->phy_address[phy_idx], PHY_CONTROL_REG, + BMCR_RESET | AUTO_NEG_ENABLE); + mdelay(100); + } + } + + eth_register(dev[i]); + + if (!sw_init_done && ipq_switch_init) { + if (ipq_switch_init(gmac_cfg) == 0) { + sw_init_done = 1; + } else { + ipq_info("Switch inits failed\n"); + goto failed; + } + } + } + + ar8033_gpio_node = fdt_path_offset(gd->fdt_blob, "/ar8033_gpio"); + + if (ar8033_gpio_node >= 0) { + bb_nodes[i] = malloc(sizeof(struct bitbang_nodes)); + memset(bb_nodes[i], 0, sizeof(struct bitbang_nodes)); + + offset = fdt_first_subnode(gd->fdt_blob, ar8033_gpio_node); + bb_nodes[i]->mdio = fdtdec_get_uint(gd->fdt_blob, offset, "gpio", 0); + + offset = fdt_next_subnode(gd->fdt_blob, offset); + bb_nodes[i]->mdc = fdtdec_get_uint(gd->fdt_blob, offset, "gpio", 0); + + bb_miiphy_buses[i].priv = bb_nodes[i]; + strlcpy(bb_miiphy_buses[i].name, "8033", + sizeof(bb_miiphy_buses[i].name)); + miiphy_register(bb_miiphy_buses[i].name, bb_miiphy_read, bb_miiphy_write); + } + + /* set the mac address in environment for unconfigured GMAC */ + if (ret >= 0) { + for (; i < CONFIG_IPQ_NO_MACS; i++) { + mac_addr = &enet_addr[i * 6]; + if (is_valid_ethaddr(mac_addr)) { + /* + * U-Boot uses these to patch the 'local-mac-address' + * dts entry for the ethernet entries, which in turn + * will be picked up by the HLOS driver + */ + sprintf(mac, "%x:%x:%x:%x:%x:%x", + mac_addr[0], mac_addr[1], + mac_addr[2], mac_addr[3], + mac_addr[4], mac_addr[5]); + setenv(ethaddr, mac); + } + sprintf(ethaddr, "eth%daddr", (i + 1)); + } + } + + return 0; + +failed: + for (i = 0; i < CONFIG_IPQ_NO_MACS; i++) { + if (bb_nodes[i]) + free(bb_nodes[i]); + if (dev[i]) { + eth_unregister(dev[i]); + free(dev[i]); + } + if (ipq_gmac_macs[i]) + free(ipq_gmac_macs[i]); + } + + return -ENOMEM; +} + + + +static void ipq_gmac_core_reset(ipq_gmac_board_cfg_t *gmac_cfg) +{ + for (; gmac_cfg_is_valid(gmac_cfg); gmac_cfg++) { + writel(0, GMAC_CORE_RESET(gmac_cfg->unit)); + if (gmac_cfg->is_macsec) + writel(0, GMACSEC_CORE_RESET(gmac_cfg->unit)); + } + + writel(0, (void *)GMAC_AHB_RESET); +} + +void ipq_gmac_common_init(ipq_gmac_board_cfg_t *gmac_cfg) +{ + uint pcs_qsgmii_ctl_val; + uint pcs_mode_ctl_val; + uint i; + ipq_gmac_board_cfg_t *gmac_tmp_cfg = gmac_cfg; + + pcs_mode_ctl_val = (PCS_CHn_ANEG_EN(GMAC_UNIT1) | + PCS_CHn_ANEG_EN(GMAC_UNIT2) | + PCS_CHn_ANEG_EN(GMAC_UNIT3) | + PCS_CHn_ANEG_EN(GMAC_UNIT0) | + PCS_SGMII_MAC); + + pcs_qsgmii_ctl_val = (PCS_QSGMII_ATHR_CSCO_AUTONEG | + PCS_QSGMII_SW_VER_1_7 | + PCS_QSGMII_SHORT_THRESH | + PCS_QSGMII_SHORT_LATENCY | + PCS_QSGMII_DEPTH_THRESH(1) | + PCS_CHn_SERDES_SN_DETECT(0) | + PCS_CHn_SERDES_SN_DETECT(1) | + PCS_CHn_SERDES_SN_DETECT(2) | + PCS_CHn_SERDES_SN_DETECT(3) | + PCS_CHn_SERDES_SN_DETECT_2(0) | + PCS_CHn_SERDES_SN_DETECT_2(1) | + PCS_CHn_SERDES_SN_DETECT_2(2) | + PCS_CHn_SERDES_SN_DETECT_2(3)); + + for (i = 0; gmac_cfg_is_valid(gmac_tmp_cfg); gmac_tmp_cfg++, i++) { + switch(gmac_tmp_cfg->phy) { + case PHY_INTERFACE_MODE_SGMII: + writel(QSGMII_PHY_MODE_SGMII, + (QSGMII_REG_BASE + QSGMII_PHY_MODE_CTL)); + writel(PCS_QSGMII_MODE_SGMII, + (QSGMII_REG_BASE + PCS_QSGMII_SGMII_MODE)); + break; + case PHY_INTERFACE_MODE_QSGMII: + pcs_mode_ctl_val = (PCS_SGMII_MAC); + writel(QSGMII_PHY_MODE_QSGMII, + (QSGMII_REG_BASE + QSGMII_PHY_MODE_CTL)); + writel(PCS_QSGMII_MODE_QSGMII, + (QSGMII_REG_BASE + PCS_QSGMII_SGMII_MODE)); + clrbits_le32((QSGMII_REG_BASE + QSGMII_PHY_QSGMII_CTL), + QSGMII_TX_SLC_CTL(3)); + break; + default: + break; + } + } + + writel(MACSEC_BYPASS_EXT_EN, (NSS_REG_BASE + NSS_MACSEC_CTL)); + writel(pcs_mode_ctl_val, (QSGMII_REG_BASE + NSS_PCS_MODE_CTL)); + writel(pcs_qsgmii_ctl_val, (QSGMII_REG_BASE + PCS_QSGMII_CTL)); + + /* + * MDIO lines for all the MACs are connected through MAC0. + * Regardless of MAC 0 being used or not, it has to be pulled + * out of reset. Else, MDIO writes to configure other MACs + * will fail. + */ + writel(0, GMAC_CORE_RESET(0)); + + /* + * Pull out of reset the MACs that are applicable to the + * current board. + */ + ipq_gmac_core_reset(gmac_cfg); +} + +static int ipq_eth_bb_init(struct bb_miiphy_bus *bus) +{ + return 0; +} + +static int ipq_eth_bb_mdio_active(struct bb_miiphy_bus *bus) +{ + struct bitbang_nodes *bb_node = bus->priv; + struct qca_gpio_config gmac_gpio_config = {0}; + + gmac_gpio_config.gpio = bb_node->mdio; + gmac_gpio_config.func = 0; + gmac_gpio_config.out = GPIO_OUTPUT; + gmac_gpio_config.pull = GPIO_NO_PULL; + gmac_gpio_config.drvstr = GPIO_8MA; + gmac_gpio_config.oe = 1; + + gpio_tlmm_config(&gmac_gpio_config); + + gmac_gpio_config.gpio = bb_node->mdc; + + gpio_tlmm_config(&gmac_gpio_config); + + return 0; +} + +static int ipq_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus) +{ + struct bitbang_nodes *bb_node = bus->priv; + struct qca_gpio_config gmac_gpio_config = {0}; + + gmac_gpio_config.gpio = bb_node->mdio; + gmac_gpio_config.func = 0; + gmac_gpio_config.out = GPIO_INPUT; + gmac_gpio_config.pull = GPIO_NO_PULL; + gmac_gpio_config.drvstr = GPIO_8MA; + gmac_gpio_config.oe = 0; + + gpio_tlmm_config(&gmac_gpio_config); + + + gmac_gpio_config.gpio = bb_node->mdc; + gmac_gpio_config.out = GPIO_OUTPUT; + gmac_gpio_config.oe = 1; + + gpio_tlmm_config(&gmac_gpio_config); + return 0; +} + +static int ipq_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v) +{ + struct bitbang_nodes *bb_node = bus->priv; + + gpio_set_value(bb_node->mdio, v); + + return 0; +} + +static int ipq_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v) +{ + struct bitbang_nodes *bb_node = bus->priv; + + *v = gpio_get_value(bb_node->mdio); + + return 0; +} + +static int ipq_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v) +{ + struct bitbang_nodes *bb_node = bus->priv; + + gpio_set_value(bb_node->mdc, v); + + return 0; +} + +static int ipq_eth_bb_delay(struct bb_miiphy_bus *bus) +{ + ndelay(350); + + return 0; +} + +struct bb_miiphy_bus bb_miiphy_buses[] = { + { + .init = ipq_eth_bb_init, + .mdio_active = ipq_eth_bb_mdio_active, + .mdio_tristate = ipq_eth_bb_mdio_tristate, + .set_mdio = ipq_eth_bb_set_mdio, + .get_mdio = ipq_eth_bb_get_mdio, + .set_mdc = ipq_eth_bb_set_mdc, + .delay = ipq_eth_bb_delay, + }, + { + .init = ipq_eth_bb_init, + .mdio_active = ipq_eth_bb_mdio_active, + .mdio_tristate = ipq_eth_bb_mdio_tristate, + .set_mdio = ipq_eth_bb_set_mdio, + .get_mdio = ipq_eth_bb_get_mdio, + .set_mdc = ipq_eth_bb_set_mdc, + .delay = ipq_eth_bb_delay, + }, + { + .init = ipq_eth_bb_init, + .mdio_active = ipq_eth_bb_mdio_active, + .mdio_tristate = ipq_eth_bb_mdio_tristate, + .set_mdio = ipq_eth_bb_set_mdio, + .get_mdio = ipq_eth_bb_get_mdio, + .set_mdc = ipq_eth_bb_set_mdc, + .delay = ipq_eth_bb_delay, + }, + { + .init = ipq_eth_bb_init, + .mdio_active = ipq_eth_bb_mdio_active, + .mdio_tristate = ipq_eth_bb_mdio_tristate, + .set_mdio = ipq_eth_bb_set_mdio, + .get_mdio = ipq_eth_bb_get_mdio, + .set_mdc = ipq_eth_bb_set_mdc, + .delay = ipq_eth_bb_delay, + }, +}; +int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses); + +static int ipq_eth_unregister(void) +{ + int i; + struct eth_device *dev; + + for (i = 0; i < CONFIG_IPQ_NO_MACS; i++) { + if (bb_nodes[i]) + free(bb_nodes[i]); + if (ipq_gmac_macs[i]) { + dev = ipq_gmac_macs[i]->dev; + eth_unregister(dev); + } + if (ipq_gmac_macs[i]) + free(ipq_gmac_macs[i]); + } + + return 0; +} + +static int do_force_eth_speed(cmd_tbl_t *cmdtp, int flag, int argc, + char *const argv[]) +{ + int status; + int i; + int j; + int phyaddrfound = 0; + int phy_addr; + + if (argc != 3) + return CMD_RET_USAGE; + + ipq_gmac_board_cfg_t *gmac_tmp_cfg = gmac_cfg; + + if (strict_strtoul(argv[1], 16, (unsigned long *)&phy_addr) < 0) { + ipq_info("Invalid Phy addr configured\n"); + return CMD_RET_USAGE; + } + get_params.phy_addr = phy_addr; + for (i = 0; gmac_cfg_is_valid(gmac_tmp_cfg); gmac_tmp_cfg++, i++) { + for (j = 0; j < gmac_tmp_cfg->phy_addr.count; j++) { + if (gmac_tmp_cfg->phy_addr.addr[j] == get_params.phy_addr) { + get_params.gmac_port = gmac_tmp_cfg->unit; + phyaddrfound = 1; + break; + } + } + } + if (phyaddrfound == 0) { + ipq_info("Invalid Phy addr configured\n"); + return CMD_RET_USAGE; + } + + if (strcmp(argv[2], "10") == 0) { + get_params.speed = SPEED_10M; + } else if (strcmp(argv[2], "100") == 0) { + get_params.speed = SPEED_100M; + } else if (strcmp(argv[2], "autoneg") == 0) { + get_params.speed = SPEED_1000M; + } else { + ipq_info("Invalid speed settings configured\n"); + return CMD_RET_USAGE; + } + + get_params.is_forced = 1; + get_params.miiwrite_done = 1; + ipq_eth_unregister(); + status = ipq_gmac_init(gmac_cfg); + + return status; +} + +U_BOOT_CMD(ethspeed, 3, 0, do_force_eth_speed, + "Force ethernet speed to 10/100/autoneg", + "ethspeed {phy addr} {10|100|autoneg} - Force ethernet speed to 10/100/autoneg\n"); + diff --git a/sources/uboot-be550/drivers/net/ipq806x/qca8511.c b/sources/uboot-be550/drivers/net/ipq806x/qca8511.c new file mode 100644 index 00000000..68a78660 --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq806x/qca8511.c @@ -0,0 +1,558 @@ +/* + * Copyright (c) 2015-2016 The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Manage the QCA8511 Music Switch. + * + * All definitions in this file are operating system independent! + */ + +#include +#include +#include +#include +#include +#undef DEBUG +#ifdef DEBUG +#define dbg(format, arg...) dbg("DEBUG: " format "\n", ## arg) +#else +#define dbg(format, arg...) do {} while(0) +#endif /* DEBUG */ +ipq_gmac_board_cfg_t *gmac_cfg_qca8511; + +static uint32_t +qca8511_pp_reg_read(ipq_gmac_board_cfg_t *gmac_cfg, uint32_t reg_addr) +{ + uint32_t reg_word_addr; + uint32_t phy_addr, reg_val; + uint16_t phy_val; + uint16_t tmp_val; + uint8_t phy_reg; + + /* + * Change reg_addr to 16-bit word address, 32-bit aligned. + */ + reg_word_addr = (reg_addr & 0xfffffffc) ; + dbg("WJL %s: 0-reg_addr=0x%08x, reg_word_addr=0x%08x.\n\n", + __func__, reg_addr, reg_word_addr); + + /* + * configure register high address; + */ + phy_addr = 0x18 | (reg_word_addr >> 29); + phy_reg = (reg_word_addr & 0x1f000000) >> 24; + /* + * Bit23-8 of reg address + */ + phy_val = (uint16_t) ((reg_word_addr >> 8) & 0xffff); + miiphy_write(gmac_cfg->phy_name, phy_addr, phy_reg, phy_val); + dbg("WJL %s: 1-w.phy_addr=0x%04x, phy_reg=0x%04x," + "phy_val=0x%04x.\n\n", + __func__, phy_addr, phy_reg, phy_val); + + /* + * For some registers such as MIBs, since it is read/clear, + * we should read the lower 16-bit register then the higher one + */ + + /* + * Read register in lower address + * Bit7-5 of reg address + */ + phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); + /* + * Bit4-0 of reg address. + */ + phy_reg = (uint8_t) (reg_word_addr & 0x1f); + miiphy_read(gmac_cfg->phy_name, phy_addr, phy_reg, &phy_val); + dbg("WJL %s: 2-r.phy_addr=0x%04x, phy_reg=0x%04x," + "phy_val=0x%04x, reg_val=0x%04x.\n\n", + __func__, phy_addr, phy_reg, phy_val, reg_val); + + /* + * Read register in higher address + * bit7-5 of reg address + */ + + phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); + /* + * Bit4-0 of reg address. + */ + phy_reg = (uint8_t) ((reg_word_addr & 0x1f) | 0x2); + miiphy_read(gmac_cfg->phy_name, phy_addr, phy_reg, &tmp_val); + reg_val = (tmp_val << 16 | phy_val); + + dbg("WJL %s: 3-r.phy_addr=0x%04x, phy_reg=0x%04x," + "phy_val=0x%04x, reg_val=0x%04x.\n\n", + __func__, phy_addr, phy_reg, phy_val, reg_val); + + + return reg_val; +} + +static void qca8511_pp_reg_write(ipq_gmac_board_cfg_t *gmac_cfg, + uint32_t reg_addr, uint32_t reg_val) +{ + uint32_t reg_word_addr; + uint32_t phy_addr; + uint16_t phy_val; + uint8_t phy_reg; + + /* + * change reg_addr to 16-bit word address, + * 32-bit aligned + */ + reg_word_addr = (reg_addr & 0xfffffffc); + dbg("WJL %s: 0-reg_addr=0x%08x, reg_word_addr=0x%08x.\n\n", + __func__, reg_addr, reg_word_addr); + + /* + * configure register high address + */ + phy_addr = 0x18 | (reg_word_addr >> 29); + phy_reg = (reg_word_addr & 0x1f000000) >> 24; + /* + * Bit23-8 of reg address. + */ + phy_val = (uint16_t) ((reg_word_addr >> 8) & 0xffff); + miiphy_write(gmac_cfg->phy_name, phy_addr, phy_reg, phy_val); + dbg("WJL %s: 1-w.phy_addr=0x%04x, phy_reg=0x%04x," + "phy_val=0x%04x.\n\n", + __func__, phy_addr, phy_reg, phy_val); + /* + * For some registers such as ARL and VLAN, since they include BUSY bit + * in lower address, we should write the higher 16-bit register then the + * lower one + */ + + /* + * write register in higher address + * bit7-5 of reg address + */ + phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); + /* + * bit4-0 of reg address + */ + phy_reg = (uint8_t) (reg_word_addr & 0x1f); + /* + * lowest 16bit data + */ + phy_val = (uint16_t) (reg_val & 0xffff); + miiphy_write(gmac_cfg->phy_name, phy_addr, phy_reg, phy_val); + + dbg("WJL %s: 2-w.phy_addr=0x%04x, phy_reg=0x%04x," + "phy_val=0x%04x, reg_val=0x%04x.\n\n", + __func__, phy_addr, phy_reg, phy_val, reg_val); + + /* + * write register in lower address + * bit7-5 of reg address + */ + phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); + /* + * Bit4-0 of reg address + */ + phy_reg = (uint8_t) ((reg_word_addr & 0x1f) | 0x2); + /* + * Highest 16bit data + */ + phy_val = (uint16_t) ((reg_val >> 16) & 0xffff); + miiphy_write(gmac_cfg->phy_name, phy_addr, phy_reg, phy_val); + + dbg("WJL %s: 3-w.phy_addr=0x%04x, phy_reg=0x%04x," + "phy_val=0x%04x, reg_val=0x%04x.\n\n", + __func__, phy_addr, phy_reg, phy_val, reg_val); + +} + +static uint32_t qca8511_pp_phy_reg_read(ipq_gmac_board_cfg_t *gmac_cfg, + uint32_t phy_sel, uint32_t phy_addr, + uint8_t reg_addr) +{ + uint32_t reg_val; + /* + * B31,MDIO_BUSY + */ + reg_val = (1 << 31); + /* + * B27, MDIO_CMD 0 = Write;1 = Read + */ + reg_val |= (1 << 27); + /* + * B29:28, PHY_SEL MDIO channel for MDIO master. + * It is used to specify PHY group that to be operated. + */ + reg_val |= ((phy_sel & 0x3) << 28); + /* + * B25:21 R/W 0 PHY_ADDR PHY address. + */ + reg_val |= ((phy_addr & 0x1f) << 21); + /* + * b20:16 R/W 0 REG_ADDR PHY register address. + */ + reg_val |= ((reg_addr & 0x1f) << 16); + + dbg("WJL %s: 1. phy_sel=0x%x, phy_addr=0x%x," + "reg_addr=0x%x, reg_val=0x%08x.\n", + __func__, phy_sel, phy_addr,reg_addr, reg_val); + + qca8511_pp_reg_write(gmac_cfg, 0x15004, reg_val); + + udelay(10); + + reg_val = qca8511_pp_reg_read(gmac_cfg, 0x15004); + + dbg("WJL %s: 2. phy_sel=0x%x, phy_addr=0x%x," + "reg_addr=0x%x, reg_val=0x%08x.\n", + __func__, phy_sel, phy_addr,reg_addr, reg_val); + + + return reg_val; +} + +static void qca8511_pp_phy_reg_write(ipq_gmac_board_cfg_t *gmac_cfg, + uint32_t phy_sel, uint32_t phy_addr, + uint32_t reg_addr, uint32_t reg_data) +{ + uint32_t reg_val; + + /* B31,MDIO_BUSY */ + reg_val = (1 << 31); + + /* + * b27, MDIO_CMD 0 = Write; 1 = Read; + */ + reg_val |= (0 << 27); + /* + * B29:28, PHY_SEL MDIO channel for MDIO master. + * It is used to specify PHY group that to be operated. + */ + reg_val |= ((phy_sel & 0x3) << 28); + /* + * B25:21 R/W 0 PHY_ADDR PHY address + */ + reg_val |= ((phy_addr & 0x1f) << 21); + /* + * B20:16 R/W 0 REG_ADDR PHY register address + */ + reg_val |= ((reg_addr & 0x1f) << 16); + + /* + * b15:0 R/WW 0 MDIO_DATA When write, these bits are data written + * to PHY register. When read, these bits are data read + * out from PHY register. + */ + reg_val |= (reg_data & 0xffff); + + dbg("WJL %s: 1. phy_sel=0x%x, phy_addr=0x%x," + "reg_addr=0x%x, reg_val=0x%08x.\n", + __func__, phy_sel, phy_addr,reg_addr, reg_val); + + qca8511_pp_reg_write(gmac_cfg, 0x15004, reg_val); + + udelay(10); + /* + * if b31-MDIO_BUSY is reset to 0? + */ + reg_val = qca8511_pp_reg_read(gmac_cfg, 0x15004); + + dbg("WJL %s: 2. phy_sel=0x%x, phy_addr=0x%x," + "reg_addr=0x%x, reg_val=0x%08x.\n", + __func__, phy_sel, phy_addr,reg_addr, reg_val); + + + return ; +} + + +static int do_qca8511_pp_reg_read(cmd_tbl_t *cmdtp, int flag, + int argc, char * const argv[]) +{ + ulong addr, readval; + int size; + + if ((argc < 2) || (argc > 3)) + return CMD_RET_USAGE; + + /* + * Check for size specification. + */ + if ((size = cmd_get_data_size(argv[0], 4)) < 1) + return 1; + + /* + * Address is specified since argc > 1 + */ + addr = simple_strtoul(argv[1], NULL, 16); + + readval = qca8511_pp_reg_read(gmac_cfg_qca8511, addr); + + printf("WJL %s: addr=0x%08lx, readval=0x%08lx.\n\n", + __func__, addr, readval); + + return 0; +} + +static int do_qca8511_pp_reg_write( cmd_tbl_t *cmdtp, int flag, + int argc, char * const argv[]) +{ + ulong addr, writeval; + int size; + + if ((argc < 3) || (argc > 4)) + return CMD_RET_USAGE; + + /* + * Check for size specification. + */ + if ((size = cmd_get_data_size(argv[0], 4)) < 1) + return 1; + + /* + * Address is specified since argc > 1 + */ + addr = simple_strtoul(argv[1], NULL, 16); + + /* + * Get the value to write. + */ + writeval = simple_strtoul(argv[2], NULL, 16); + + if (argc == 4) + simple_strtoul(argv[3], NULL, 16); + + printf("WJL %s: addr=0x%08lx, writeval=0x%08lx.\n\n", + __func__,addr, writeval); + + qca8511_pp_reg_write(gmac_cfg_qca8511, addr, writeval); + dbg("\n"); + return 0; +} + +static int do_qca8511_pp_phy_reg_read( cmd_tbl_t *cmdtp, int flag, + int argc, char * const argv[]) +{ + ulong phy_sel, phy_addr, reg_addr, reg_val; + int size; + + if (argc != 4) + return CMD_RET_USAGE; + + /* + * Check for size specification. + */ + if ((size = cmd_get_data_size(argv[0], 4)) < 1) + return 1; + + /* + * Address is specified since argc > 1 + */ + phy_sel = simple_strtoul(argv[1], NULL, 16); + phy_addr = simple_strtoul(argv[2], NULL, 16); + reg_addr = simple_strtoul(argv[3], NULL, 16); + + reg_val = qca8511_pp_phy_reg_read(gmac_cfg_qca8511, phy_sel, + phy_addr, reg_addr); + + printf("WJL %s: phy_sel=0x%lx, phy_addr=0x%lx, reg_addr=0x%lx," + "reg_val=0x%08lx, size=%d.\n\n", + __func__, phy_sel, phy_addr, reg_addr, reg_val, size); + + return 0; +} + +static int do_qca8511_pp_phy_reg_write( cmd_tbl_t *cmdtp, + int flag, int argc, char * const argv[]) +{ + ulong phy_sel, phy_addr, reg_addr, reg_data; + int size; + + if (argc != 5) + return CMD_RET_USAGE; + + /* + * Check for size specification. + */ + if ((size = cmd_get_data_size(argv[0], 4)) < 1) + return 1; + + /* + * Address is specified since argc > 1 + */ + phy_sel = simple_strtoul(argv[1], NULL, 16); + phy_addr = simple_strtoul(argv[2], NULL, 16); + reg_addr = simple_strtoul(argv[3], NULL, 16); + reg_data = simple_strtoul(argv[4], NULL, 16); + + printf("WJL %s: phy_sel=0x%lx, phy_addr=0x%lx, reg_addr=0x%lx," + "reg_data=0x%08lx, size=%d.\n", + __func__, phy_sel, phy_addr, reg_addr, reg_data, size); + + qca8511_pp_phy_reg_write(gmac_cfg_qca8511, phy_sel, phy_addr, + reg_addr, reg_data); + dbg("\n"); + return 0; +} + +/********************************************************************* + * + * FUNCTION DESCRIPTION: This function invokes RGMII, + * SGMII switch init routines. + * INPUT : ipq_gmac_board_cfg_t * + * OUTPUT: NONE + * +**********************************************************************/ +int ipq_qca8511_init(ipq_gmac_board_cfg_t *gmac_cfg) +{ + uint i; + + gmac_cfg_qca8511 = gmac_cfg; + qca8511_pp_reg_write(gmac_cfg, QCA8511_QSGMII_1_CTRL(QSGMII_1_CTRL0), + QSGMII_1_CH0_DUPLEX_MODE | + QSGMII_1_CH0_LINK | + QSGMII_1_CH0_SPEED_MODE(FORCE_1000) | + QSGMII_1_CH0_MR_AN_EN | + QSGMII_1_RSVD16 | + QSGMII_1_CH0_FORCED_MODE | + QSGMII_1_CH_MODE_CTRL(QSGMII_MAC)| + QSGMII_1_CH0_PAUSE_SG_TX_EN | + QSGMII_1_CH0_ASYM_PAUSE | + QSGMII_1_CH0_PAUSE | + QSGMII_1_RSVD30 | + QSGMII_1_RSVD31); + + qca8511_pp_reg_write(gmac_cfg, QCA8511_QSGMII_2_CTRL(QSGMII_2_CTRL0), + QSGMII_2_CH1_DUPLEX_MODE | + QSGMII_2_CH1_LINK | + QSGMII_2_CH1_SPEED_MODE(FORCE_1000) | + QSGMII_2_CH1_MR_AN_EN | + QSGMII_2_RSVD16 | + QSGMII_2_CH1_FORCED_MODE | + QSGMII_2_CH_RSVD(2) | + QSGMII_2_CH1_PAUSE_SG_TX_EN | + QSGMII_2_CH1_ASYM_PAUSE | + QSGMII_2_CH1_PAUSE | + QSGMII_2_RSVD30 | + QSGMII_2_RSVD31); + + qca8511_pp_reg_write(gmac_cfg, QCA8511_QSGMII_3_CTRL(QSGMII_3_CTRL0), + QSGMII_3_CH2_DUPLEX_MODE | + QSGMII_3_CH2_LINK | + QSGMII_3_CH2_SPEED_MODE(FORCE_1000) | + QSGMII_3_CH2_MR_AN_EN | + QSGMII_3_RSVD16 | + QSGMII_3_CH2_FORCED_MODE | + QSGMII_2_CH_RSVD(2) | + QSGMII_3_CH2_PAUSE_SG_TX_EN | + QSGMII_3_CH2_ASYM_PAUSE | + QSGMII_3_CH2_PAUSE | + QSGMII_2_RSVD30 | + QSGMII_2_RSVD31); + + qca8511_pp_reg_write(gmac_cfg, QCA8511_QSGMII_4_CTRL(QSGMII_3_CTRL0), + QSGMII_4_CH3_DUPLEX_MODE | + QSGMII_4_CH3_LINK | + QSGMII_4_CH3_SPEED_MODE(FORCE_1000) | + QSGMII_4_CH3_MR_AN_EN | + QSGMII_4_RSVD16 | + QSGMII_4_CH3_FORCED_MODE | + QSGMII_4_CH_RSVD(2) | + QSGMII_4_CH3_PAUSE_SG_TX_EN | + QSGMII_4_CH3_ASYM_PAUSE | + QSGMII_4_CH3_PAUSE | + QSGMII_4_RSVD30 | + QSGMII_4_RSVD31); + + qca8511_pp_reg_write(gmac_cfg, QCA8511_SGMII_CTRL0(SGMII_CTRL0_PORT8), + SGMII_CTRL0_DUPLEX(1) | + SGMII_CTRL0_SPEED_MODE(2) | + SGMII_CTRL0_MR_AN_EN | + SGMII_CTRL0_RSVD16 | + SGMII_CTRL0_MODECTRL(2) | + SGMII_CTRL0_PAUSE_SG_TX_EN | + SGMII_CTRL0_ASYM_PAUSE_EN | + SGMII_CTRL0_PAUSE_EN | + SGMII_CTRL0_HALF_DUPLEX_EN | + SGMII_CTRL0_FULL_DUPLEX_EN); + + /* + * Configure 8511 Ports + */ + + for (i = STATUS_PORT1; i < STATUS_PORT5; i++) { + qca8511_pp_reg_write(gmac_cfg, QCA8511_PORT_STATUS_CFG(i), + QCA8511_PORT_CFG_SPEED(FORCE_1000) | + QCA8511_PORT_CFG_TX_MAC_EN | + QCA8511_PORT_CFG_RX_MAC_EN | + QCA8511_PORT_CFG_DUPLEX_MODE); + } + + qca8511_pp_reg_write(gmac_cfg, QCA8511_GLOBAL_CTRL1, + GLOBAL_CTL1_MAC25XG_4P3G_EN | + GLOBAL_CTL1_MAC25XG_3P125G_EN | + GLOBAL_CTL1_MAC26SG_1P25G_EN | + GLOBAL_CTL1_MAC27SG_3P125G_EN | + GLOBAL_CTL1_MAC28SG_3P125G_EN | + GLOBAL_CTL1_MAC29SG_3P125G_EN | + GLOBAL_CTL1_RSVD22 | + GLOBAL_CTL1_SPI1_EN | + GLOBAL_CTL1_TO_EXT_INT_EN | + GLOBAL_CTL1_LED_CLK_EN_CFG | + GLOBAL_CTL1_RSVD28 | + GLOBAL_CTL1_RSVD29 | + GLOBAL_CTL1_TWO_WIRE_LED_EN); + + qca8511_pp_reg_write(gmac_cfg, QCA8511_XAUI_SGMII_SERDES13_CTRL0, + SGMII_CTRL0_RSVD(3) | + SGMII_CTRL0_XAUI_EN_PLL(3) | + SGMII_CTRL0_XAUI_DEEMP_CH0(1) | + SGMII_CTRL0_XAUI_DEEMP_CH2(1) | + SGMII_CTRL0_XAUI_DEEMP_CH3(1) | + SGMII_CTRL0_XAUI_EN_SD(0xf)); + + qca8511_pp_reg_write(gmac_cfg, QCA8511_XAUI_SGMII_SERDES13_CTRL1, + SGMII_CTRL1_RSVD4(3) | + SGMII_CTRL1_XAUI_EN_RX(0xf) | + SGMII_CTRL1_XAUI_EN_TX(0xf) | + SGMII_CTRL1_XAUI_DEEMP_CH1(1) | + SGMII_CTRL1_XAUI_REG(9) | + SGMII_CTRL1_RSVD23(1) | + SGMII_CTRL1_RSVD25(2)); + + printf("QCA8511 Init done....\n"); + return 0; +} + +U_BOOT_CMD( + mprd, 3, 1, do_qca8511_pp_reg_read, + "qca8511 packet processor register display", + "[.b, .w, .l] address [# of objects]" +); + +U_BOOT_CMD( + mprw, 4, 1, do_qca8511_pp_reg_write, + "qca8511 packet processor register write (fill)", + "[.b, .w, .l] address value [count]" +); + +U_BOOT_CMD( + mphyrd, 5, 1, do_qca8511_pp_phy_reg_read, + "qca8511 packet processor PHY register display", + "[.b, .w, .l] phy_sel phy_addr reg_addr [# of objects]" +); + +U_BOOT_CMD( + mphyrw, 6, 1, do_qca8511_pp_phy_reg_write, + "qca8511 packet processor PHY register write (fill)", + "[.b, .w, .l] phy_sel phy_addr reg_addr reg_data [count]" +); diff --git a/sources/uboot-be550/drivers/net/ipq807x/ipq807x_aquantia_phy.c b/sources/uboot-be550/drivers/net/ipq807x/ipq807x_aquantia_phy.c new file mode 100644 index 00000000..97825a44 --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq807x/ipq807x_aquantia_phy.c @@ -0,0 +1,597 @@ +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include "ipq_phy.h" +#include "ipq807x_aquantia_phy.h" +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; +typedef struct { + unsigned int image_type; + unsigned int header_vsn_num; + unsigned int image_src; + unsigned char *image_dest_ptr; + unsigned int image_size; + unsigned int code_size; + unsigned char *signature_ptr; + unsigned int signature_size; + unsigned char *cert_chain_ptr; + unsigned int cert_chain_size; +} mbn_header_t; + +mbn_header_t *fwimg_header; +static int debug = 0; + +#ifdef CONFIG_QCA_MMC +extern qca_mmc mmc_host; +static qca_mmc *host = &mmc_host; +#endif + +extern int ipq_mdio_write(int mii_id, + int regnum, u16 value); +extern int ipq_mdio_read(int mii_id, + int regnum, ushort *data); + +extern int ipq_sw_mdio_init(const char *); +extern void eth_clock_enable(void); +static int program_ethphy_fw(unsigned int phy_addr, + uint32_t load_addr,uint32_t file_size ); +static qca_smem_flash_info_t *sfi = &qca_smem_flash_info; + +u16 aq_phy_reg_write(u32 dev_id, u32 phy_id, + u32 reg_id, u16 reg_val) +{ + ipq_mdio_write(phy_id, reg_id, reg_val); + return 0; +} + +u16 aq_phy_reg_read(u32 dev_id, u32 phy_id, u32 reg_id) +{ + return ipq_mdio_read(phy_id, reg_id, NULL); +} + +u8 aq_phy_get_link_status(u32 dev_id, u32 phy_id) +{ + u16 phy_data; + uint32_t reg; + + reg = AQ_PHY_AUTO_STATUS_REG | AQUANTIA_MII_ADDR_C45; + phy_data = aq_phy_reg_read(dev_id, phy_id, reg); + phy_data = aq_phy_reg_read(dev_id, phy_id, reg); + + if (((phy_data >> 2) & 0x1) & PORT_LINK_UP) + return 0; + + return 1; +} + +u32 aq_phy_get_duplex(u32 dev_id, u32 phy_id, fal_port_duplex_t *duplex) +{ + u16 phy_data; + uint32_t reg; + + reg = AQ_PHY_LINK_STATUS_REG | AQUANTIA_MII_ADDR_C45; + phy_data = aq_phy_reg_read(dev_id, phy_id, reg); + + /* + * Read duplex + */ + phy_data = phy_data & 0x1; + if (phy_data & 0x1) + *duplex = FAL_FULL_DUPLEX; + else + *duplex = FAL_HALF_DUPLEX; + + return 0; +} + +u32 aq_phy_get_speed(u32 dev_id, u32 phy_id, fal_port_speed_t *speed) +{ + u16 phy_data; + uint32_t reg; + + reg = AQ_PHY_LINK_STATUS_REG | AQUANTIA_MII_ADDR_C45; + phy_data = aq_phy_reg_read(dev_id, phy_id, reg); + + switch ((phy_data >> 1) & 0x7) { + case SPEED_10G: + *speed = FAL_SPEED_10000; + break; + case SPEED_5G: + *speed = FAL_SPEED_5000; + break; + case SPEED_2_5G: + *speed = FAL_SPEED_2500; + break; + case SPEED_1000MBS: + *speed = FAL_SPEED_1000; + break; + case SPEED_100MBS: + *speed = FAL_SPEED_100; + break; + case SPEED_10MBS: + *speed = FAL_SPEED_10; + break; + default: + return -EINVAL; + } + return 0; +} + +void aquantia_phy_restart_autoneg(u32 phy_id) +{ + u16 phy_data; + + phy_data = aq_phy_reg_read(0x0, phy_id, AQUANTIA_REG_ADDRESS(AQUANTIA_MMD_PHY_XS_REGISTERS, + AQUANTIA_PHY_XS_USX_TRANSMIT)); + if (!(phy_data & AQUANTIA_PHY_USX_AUTONEG_ENABLE)) + aq_phy_reg_write(0x0, phy_id,AQUANTIA_REG_ADDRESS( + AQUANTIA_MMD_PHY_XS_REGISTERS, + AQUANTIA_PHY_XS_USX_TRANSMIT), + phy_data | AQUANTIA_PHY_USX_AUTONEG_ENABLE); + + phy_data = aq_phy_reg_read(0x0, phy_id, AQUANTIA_REG_ADDRESS(AQUANTIA_MMD_AUTONEG, + AQUANTIA_AUTONEG_STANDARD_CONTROL1)); + + phy_data |= AQUANTIA_CTRL_AUTONEGOTIATION_ENABLE; + aq_phy_reg_write(0x0, phy_id, AQUANTIA_REG_ADDRESS(AQUANTIA_MMD_AUTONEG, + AQUANTIA_AUTONEG_STANDARD_CONTROL1), + phy_data | AQUANTIA_CTRL_RESTART_AUTONEGOTIATION); +} + +int ipq_qca_aquantia_phy_init(struct phy_ops **ops, u32 phy_id) +{ + u16 phy_data; + struct phy_ops *aq_phy_ops; + aq_phy_ops = (struct phy_ops *)malloc(sizeof(struct phy_ops)); + if (!aq_phy_ops) + return -ENOMEM; + aq_phy_ops->phy_get_link_status = aq_phy_get_link_status; + aq_phy_ops->phy_get_speed = aq_phy_get_speed; + aq_phy_ops->phy_get_duplex = aq_phy_get_duplex; + *ops = aq_phy_ops; + + phy_data = aq_phy_reg_read(0x0, phy_id, AQUANTIA_REG_ADDRESS(1, QCA_PHY_ID1)); + printf ("PHY ID1: 0x%x\n", phy_data); + phy_data = aq_phy_reg_read(0x0, phy_id, AQUANTIA_REG_ADDRESS(1, QCA_PHY_ID2)); + printf ("PHY ID2: 0x%x\n", phy_data); + phy_data = aq_phy_reg_read(0x0, phy_id, AQUANTIA_REG_ADDRESS(AQUANTIA_MMD_PHY_XS_REGISTERS, + AQUANTIA_PHY_XS_USX_TRANSMIT)); + phy_data |= AQUANTIA_PHY_USX_AUTONEG_ENABLE; + aq_phy_reg_write(0x0, phy_id, AQUANTIA_REG_ADDRESS(AQUANTIA_MMD_PHY_XS_REGISTERS, + AQUANTIA_PHY_XS_USX_TRANSMIT), phy_data); + phy_data = aq_phy_reg_read(0x0, phy_id, AQUANTIA_REG_ADDRESS(AQUANTIA_MMD_AUTONEG, + AQUANTIA_AUTONEG_TRANSMIT_VENDOR_INTR_MASK)); + phy_data |= AQUANTIA_INTR_LINK_STATUS_CHANGE; + aq_phy_reg_write(0x0, phy_id, AQUANTIA_REG_ADDRESS(AQUANTIA_MMD_AUTONEG, + AQUANTIA_AUTONEG_TRANSMIT_VENDOR_INTR_MASK), phy_data); + phy_data = aq_phy_reg_read(0x0, phy_id, AQUANTIA_REG_ADDRESS(AQUANTIA_MMD_GLOABLE_REGISTERS, + AQUANTIA_GLOBAL_INTR_STANDARD_MASK)); + phy_data |= AQUANTIA_ALL_VENDOR_ALARMS_INTERRUPT_MASK; + aq_phy_reg_write(0x0, phy_id, AQUANTIA_REG_ADDRESS(AQUANTIA_MMD_GLOABLE_REGISTERS, + AQUANTIA_GLOBAL_INTR_STANDARD_MASK), phy_data); + phy_data = aq_phy_reg_read(0x0, phy_id, AQUANTIA_REG_ADDRESS(AQUANTIA_MMD_GLOABLE_REGISTERS, + AQUANTIA_GLOBAL_INTR_VENDOR_MASK)); + phy_data |= AQUANTIA_AUTO_AND_ALARMS_INTR_MASK; + aq_phy_reg_write(0x0, phy_id, AQUANTIA_REG_ADDRESS(AQUANTIA_MMD_GLOABLE_REGISTERS, + AQUANTIA_GLOBAL_INTR_VENDOR_MASK), phy_data); + return 0; +} + +static int do_aq_phy_restart(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + unsigned int phy_addr = AQU_PHY_ADDR; + if (argc > 2) + return CMD_RET_USAGE; + + if (argc == 2) + phy_addr = simple_strtoul(argv[1], NULL, 16); + + aquantia_phy_restart_autoneg(phy_addr); + return 0; +} + +int ipq_board_fw_download(unsigned int phy_addr) +{ + char runcmd[256]; + int ret,i=0; + uint32_t start; /* block number */ + uint32_t size; /* no. of blocks */ + qca_part_entry_t ethphyfw; + unsigned int *ethphyfw_load_addr = NULL; + struct { char *name; qca_part_entry_t *part; } entries[] = { + { "0:ETHPHYFW", ðphyfw }, + }; +#ifdef CONFIG_QCA_MMC + block_dev_desc_t *blk_dev; + disk_partition_t disk_info; +#endif + /* check the smem info to see which flash used for booting */ + if (sfi->flash_type == SMEM_BOOT_SPI_FLASH) { + if (debug) { + printf("Using nor device \n"); + } + } else if (sfi->flash_type == SMEM_BOOT_NAND_FLASH) { + if (debug) { + printf("Using nand device 0\n"); + } + } else if (sfi->flash_type == SMEM_BOOT_MMC_FLASH) { + if (debug) { + printf("Using MMC device\n"); + } + } else { + printf("Unsupported BOOT flash type\n"); + return -1; + } + + ret = smem_getpart(entries[i].name, &start, &size); + if (ret < 0) { + debug("cdp: get part failed for %s\n", entries[i].name); + } else { + qca_set_part_entry(entries[i].name, sfi, entries[i].part, start, size); + } + + if ((sfi->flash_type == SMEM_BOOT_NAND_FLASH) || + (sfi->flash_type == SMEM_BOOT_SPI_FLASH)) { + ethphyfw_load_addr = (uint *)malloc(ethphyfw.size); + if (ethphyfw_load_addr == NULL) { + printf("ETHPHYFW Loading failed\n"); + return -1; + } else { + memset(ethphyfw_load_addr, 0, ethphyfw.size); + } + } + + if (sfi->flash_type == SMEM_BOOT_NAND_FLASH) { + /* + * Kernel is in a separate partition + */ + snprintf(runcmd, sizeof(runcmd), + /* NOR is treated as psuedo NAND */ + "nand read 0x%p 0x%llx 0x%llx && ", + ethphyfw_load_addr, ethphyfw.offset, ethphyfw.size); + + if (debug) + printf("%s", runcmd); + + if (run_command(runcmd, 0) != CMD_RET_SUCCESS) { + free(ethphyfw_load_addr); + return CMD_RET_FAILURE; + } + } else if (sfi->flash_type == SMEM_BOOT_SPI_FLASH) { + snprintf(runcmd, sizeof(runcmd), + "sf probe && " "sf read 0x%p 0x%llx 0x%llx && ", + ethphyfw_load_addr, ethphyfw.offset, ethphyfw.size); + + if (debug) + printf("%s", runcmd); + + if (run_command(runcmd, 0) != CMD_RET_SUCCESS) { + free(ethphyfw_load_addr); + return CMD_RET_FAILURE; + } +#ifdef CONFIG_QCA_MMC + } else if (sfi->flash_type == SMEM_BOOT_MMC_FLASH ) { + blk_dev = mmc_get_dev(host->dev_num); + ret = get_partition_info_efi_by_name(blk_dev, + "0:ETHPHYFW", &disk_info); + + ethphyfw_load_addr = (uint *)malloc(((uint)disk_info.size) * + ((uint)disk_info.blksz)); + if (ethphyfw_load_addr == NULL) { + printf("ETHPHYFW Loading failed\n"); + return -1; + } else { + memset(ethphyfw_load_addr, 0, + (((uint)disk_info.size) * + ((uint)disk_info.blksz))); + } + + if (ret == 0) { + snprintf(runcmd, sizeof(runcmd), + "mmc read 0x%p 0x%X 0x%X", + ethphyfw_load_addr, + (uint)disk_info.start, (uint)disk_info.size); + + if (run_command(runcmd, 0) != CMD_RET_SUCCESS) { + free(ethphyfw_load_addr); + return CMD_RET_FAILURE; + } + } +#endif + } + + fwimg_header = (mbn_header_t *)(ethphyfw_load_addr); + + if (fwimg_header->image_type == 0x13 && + fwimg_header->header_vsn_num == 0x3) { + program_ethphy_fw(phy_addr, + (uint32_t)(((uint32_t)ethphyfw_load_addr) + + sizeof(mbn_header_t)), + (uint32_t)(fwimg_header->image_size)); + } else { + printf("bad magic on ETHPHYFW partition\n"); + free(ethphyfw_load_addr); + return -1; + } + free(ethphyfw_load_addr); + return 0; +} + + +#define AQ_PHY_IMAGE_HEADER_CONTENT_OFFSET_HHD 0x300 +static int program_ethphy_fw(unsigned int phy_addr, uint32_t load_addr, uint32_t file_size) +{ + int i; + uint8_t *buf; + uint16_t file_crc; + uint16_t computed_crc; + uint32_t reg1, reg2; + uint16_t recorded_ggp8_val; + uint16_t daisy_chain_dis; + uint32_t primary_header_ptr = 0x00000000; + uint32_t primary_iram_ptr = 0x00000000; + uint32_t primary_dram_ptr = 0x00000000; + uint32_t primary_iram_sz = 0x00000000; + uint32_t primary_dram_sz = 0x00000000; + uint32_t phy_img_hdr_off; + uint32_t byte_sz; + uint32_t dword_sz; + uint32_t byte_ptr; + uint16_t msw = 0; + uint16_t lsw = 0; + uint8_t msb1; + uint8_t msb2; + uint8_t lsb1; + uint8_t lsb2; + uint16_t mailbox_crc; + + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x300), 0xdead); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x301), 0xbeaf); + reg1 = aq_phy_reg_read(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x300)); + reg2 = aq_phy_reg_read(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x301)); + + if(reg1 != 0xdead && reg2 != 0xbeaf) { + printf("PHY::Scratchpad Read/Write test fail\n"); + return 0; + } + buf = (uint8_t *)load_addr; + file_crc = buf[file_size - 2] << 8 | buf[file_size - 1]; + computed_crc = cyg_crc16(buf, file_size - 2); + + if (file_crc != computed_crc) { + printf("CRC check failed on phy fw file\n"); + return 0; + } else { + printf ("CRC check good on phy fw file (0x%04X)\n",computed_crc); + } + + daisy_chain_dis = aq_phy_reg_read(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0xc452)); + if (!(daisy_chain_dis & 0x1)) + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0xc452), 0x1); + + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0xc471), 0x40); + recorded_ggp8_val = aq_phy_reg_read(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0xc447)); + if ((recorded_ggp8_val & 0x1f) != phy_addr) + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0xc447), phy_addr); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0xc441), 0x4000); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0xc001), 0x41); + primary_header_ptr = (((buf[0x9] & 0x0F) << 8) | buf[0x8]) << 12; + phy_img_hdr_off = AQ_PHY_IMAGE_HEADER_CONTENT_OFFSET_HHD; + primary_iram_ptr = (buf[primary_header_ptr + phy_img_hdr_off + 0x4 + 2] << 16) | + (buf[primary_header_ptr + phy_img_hdr_off + 0x4 + 1] << 8) | + buf[primary_header_ptr + phy_img_hdr_off + 0x4]; + primary_iram_sz = (buf[primary_header_ptr + phy_img_hdr_off + 0x7 + 2] << 16) | + (buf[primary_header_ptr + phy_img_hdr_off + 0x7 + 1] << 8) | + buf[primary_header_ptr + phy_img_hdr_off + 0x7]; + primary_dram_ptr = (buf[primary_header_ptr + phy_img_hdr_off + 0xA + 2] << 16) | + (buf[primary_header_ptr + phy_img_hdr_off + 0xA + 1] << 8) | + buf[primary_header_ptr + phy_img_hdr_off + 0xA]; + primary_dram_sz = (buf[primary_header_ptr + phy_img_hdr_off + 0xD + 2] << 16) | + (buf[primary_header_ptr + phy_img_hdr_off + 0xD + 1] << 8) | + buf[primary_header_ptr + phy_img_hdr_off + 0xD]; + primary_iram_ptr += primary_header_ptr; + primary_dram_ptr += primary_header_ptr; + + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x200), 0x1000); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x200), 0x0); + computed_crc = 0; + printf("PHYFW:Loading IRAM..........."); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x202), 0x4000); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x203), 0x0); + byte_sz = primary_iram_sz; + dword_sz = byte_sz >> 2; + byte_ptr = primary_iram_ptr; + for (i = 0; i < dword_sz; i++) { + lsw = (buf[byte_ptr + 1] << 8) | buf[byte_ptr]; + byte_ptr += 2; + msw = (buf[byte_ptr + 1] << 8) | buf[byte_ptr]; + byte_ptr += 2; + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x204), msw); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x205), lsw); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x200), 0xc000); + msb1 = msw >> 8; + msb2 = msw & 0xFF; + lsb1 = lsw >> 8; + lsb2 = lsw & 0xFF; + computed_crc = cyg_crc16_computed(&msb1, 0x1, computed_crc); + computed_crc = cyg_crc16_computed(&msb2, 0x1, computed_crc); + computed_crc = cyg_crc16_computed(&lsb1, 0x1, computed_crc); + computed_crc = cyg_crc16_computed(&lsb2, 0x1, computed_crc); + } + + switch (byte_sz & 0x3) { + case 0x1: + lsw = buf[byte_ptr++]; + msw = 0x0000; + break; + case 0x2: + lsw = (buf[byte_ptr + 1] << 8) | buf[byte_ptr]; + byte_ptr += 2; + msw = 0x0000; + break; + case 0x3: + lsw = (buf[byte_ptr + 1] << 8) | buf[byte_ptr]; + byte_ptr += 2; + msw = buf[byte_ptr++]; + break; + } + + if (byte_sz & 0x3) { + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x204), msw); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x205), lsw); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x200), 0xc000); + msb1 = msw >> 8; + msb2 = msw & 0xFF; + lsb1 = lsw >> 8; + lsb2 = lsw & 0xFF; + computed_crc = cyg_crc16_computed(&msb1, 0x1, computed_crc); + computed_crc = cyg_crc16_computed(&msb2, 0x1, computed_crc); + computed_crc = cyg_crc16_computed(&lsb1, 0x1, computed_crc); + computed_crc = cyg_crc16_computed(&lsb2, 0x1, computed_crc); + } + printf("done.\n"); + printf("PHYFW:Loading DRAM.............."); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x202), 0x3ffe); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x203), 0x0); + byte_sz = primary_dram_sz; + dword_sz = byte_sz >> 2; + byte_ptr = primary_dram_ptr; + for (i = 0; i < dword_sz; i++) { + lsw = (buf[byte_ptr + 1] << 8) | buf[byte_ptr]; + byte_ptr += 2; + msw = (buf[byte_ptr + 1] << 8) | buf[byte_ptr]; + byte_ptr += 2; + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x204), msw); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x205), lsw); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x200), 0xc000); + msb1 = msw >> 8; + msb2 = msw & 0xFF; + lsb1 = lsw >> 8; + lsb2 = lsw & 0xFF; + computed_crc = cyg_crc16_computed(&msb1, 0x1, computed_crc); + computed_crc = cyg_crc16_computed(&msb2, 0x1, computed_crc); + computed_crc = cyg_crc16_computed(&lsb1, 0x1, computed_crc); + computed_crc = cyg_crc16_computed(&lsb2, 0x1, computed_crc); + } + + switch (byte_sz & 0x3) { + case 0x1: + lsw = buf[byte_ptr++]; + msw = 0x0000; + break; + case 0x2: + lsw = (buf[byte_ptr + 1] << 8) | buf[byte_ptr]; + byte_ptr += 2; + msw = 0x0000; + break; + case 0x3: + lsw = (buf[byte_ptr + 1] << 8) | buf[byte_ptr]; + byte_ptr += 2; + msw = buf[byte_ptr++]; + break; + } + + if (byte_sz & 0x3) { + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x204), msw); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x205), lsw); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x200), 0xc000); + msb1 = msw >> 8; + msb2 = msw & 0xFF; + lsb1 = lsw >> 8; + lsb2 = lsw & 0xFF; + computed_crc = cyg_crc16_computed(&msb1, 0x1, computed_crc); + computed_crc = cyg_crc16_computed(&msb2, 0x1, computed_crc); + computed_crc = cyg_crc16_computed(&lsb1, 0x1, computed_crc); + computed_crc = cyg_crc16_computed(&lsb2, 0x1, computed_crc); + } + printf("done.\n"); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0xc441), 0x2010); + mailbox_crc = aq_phy_reg_read(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x201)); + if (mailbox_crc != computed_crc) { + printf("phy fw image load CRC-16 (0x%X) does not match calculated CRC-16 (0x%X)\n", mailbox_crc, computed_crc); + return 0; + } else + printf("phy fw image load good CRC-16 matches (0x%X)\n", mailbox_crc); + + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x0), 0x0); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0xc001), 0x41); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0xc001), 0x8041); + mdelay(100); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0xc001), 0x40); + mdelay(100); + aquantia_phy_restart_autoneg(phy_addr); + return 0; +} + +static int do_load_fw(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + unsigned int phy_addr = AQU_PHY_ADDR; + int node, aquantia_port; + + if (argc > 2) + return CMD_RET_USAGE; + + if (argc == 2) + phy_addr = simple_strtoul(argv[1], NULL, 16); + + node = fdt_path_offset(gd->fdt_blob, "/ess-switch"); + if (node < 0) { + printf("Error: ess-switch not specified in dts"); + return 0; + } + + aquantia_port = fdtdec_get_uint(gd->fdt_blob, node, "aquantia_port", -1); + if (aquantia_port < 0) { + printf("Error: aquantia_port not specified in dts"); + return 0; + } + + aquantia_port = fdtdec_get_uint(gd->fdt_blob, node, "aquantia_gpio", -1); + if (aquantia_port < 0) { + printf("Error: aquantia_gpio not specified in dts"); + return 0; + } + + miiphy_init(); + eth_clock_enable(); + ipq_sw_mdio_init("IPQ MDIO0"); + ipq_board_fw_download(phy_addr); + return 0; +} + +U_BOOT_CMD( + aq_load_fw, 5, 1, do_load_fw, + "LOAD aq-fw-binary", + "" +); + +U_BOOT_CMD( + aq_phy_restart, 5, 1, do_aq_phy_restart, + "Restart Aquantia phy", + "" +); diff --git a/sources/uboot-be550/drivers/net/ipq807x/ipq807x_aquantia_phy.h b/sources/uboot-be550/drivers/net/ipq807x/ipq807x_aquantia_phy.h new file mode 100644 index 00000000..a59b5f78 --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq807x/ipq807x_aquantia_phy.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#define AQUANTIA_MII_ADDR_C45 (1<<30) +#define AQUANTIA_REG_ADDRESS(dev_ad, reg_num) (AQUANTIA_MII_ADDR_C45 |\ + ((dev_ad & 0x1f) << 16) | (reg_num & 0xFFFF)) + +#define AQUANTIA_MMD_PHY_XS_REGISTERS 4 +#define AQUANTIA_PHY_XS_USX_TRANSMIT 0xc441 +#define AQUANTIA_PHY_USX_AUTONEG_ENABLE 0x8 + +#define AQUANTIA_MMD_AUTONEG 0x7 +#define AQUANTIA_AUTONEG_TRANSMIT_VENDOR_INTR_MASK 0xD401 +#define AQUANTIA_INTR_LINK_STATUS_CHANGE 0x0001 + +#define AQUANTIA_MMD_GLOABLE_REGISTERS 0x1E +#define AQUANTIA_GLOBAL_INTR_STANDARD_MASK 0xff00 +#define AQUANTIA_ALL_VENDOR_ALARMS_INTERRUPT_MASK 0x0001 + +#define AQUANTIA_GLOBAL_INTR_VENDOR_MASK 0xff01 +#define AQUANTIA_AUTO_AND_ALARMS_INTR_MASK 0x1001 + +#define AQUANTIA_AUTONEG_STANDARD_CONTROL1 0 +#define AQUANTIA_CTRL_AUTONEGOTIATION_ENABLE 0x1000 +#define AQUANTIA_CTRL_RESTART_AUTONEGOTIATION 0x0200 + +#define AQ_PHY_AUTO_STATUS_REG 0x70001 +#define PORT_LINK_DOWN 0 +#define PORT_LINK_UP 1 + +#define AQ_PHY_LINK_STATUS_REG 0x7c800 +#define SPEED_5G 5 +#define SPEED_2_5G 4 +#define SPEED_10G 3 +#define SPEED_1000MBS 2 +#define SPEED_100MBS 1 +#define SPEED_10MBS 0 + diff --git a/sources/uboot-be550/drivers/net/ipq807x/ipq807x_edma.c b/sources/uboot-be550/drivers/net/ipq807x/ipq807x_edma.c new file mode 100755 index 00000000..163c12c1 --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq807x/ipq807x_edma.c @@ -0,0 +1,1958 @@ +/* + * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER + * RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT + * NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE + * USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "ipq807x_edma.h" +#include "ipq_phy.h" + +DECLARE_GLOBAL_DATA_PTR; +#ifdef DEBUG +#define pr_debug(fmt, args...) printf(fmt, ##args); +#else +#define pr_debug(fmt, args...) +#endif + +#define pr_info(fmt, args...) printf(fmt, ##args); +#define pr_warn(fmt, args...) printf(fmt, ##args); + +#ifndef CONFIG_IPQ807X_BRIDGED_MODE +#define IPQ807X_EDMA_MAC_PORT_NO 3 +#endif + +static struct ipq807x_eth_dev *ipq807x_edma_dev[IPQ807X_EDMA_DEV]; + +uchar ipq807x_def_enetaddr[6] = {0x00, 0x03, 0x7F, 0xBA, 0xDB, 0xAD}; +phy_info_t *phy_info[PHY_MAX] = {0}; +int sgmii_mode[2] = {0}; + +extern void qca8075_ess_reset(void); +extern void psgmii_self_test(void); +extern void clear_self_test_config(void); +extern int ipq_sw_mdio_init(const char *); +extern void ipq_qca8075_dump_phy_regs(u32); +extern int ipq_mdio_read(int mii_id, + int regnum, ushort *data); +extern void ipq_qca8075_phy_map_ops(struct phy_ops **ops); +extern int ipq_qca8075_phy_init(struct phy_ops **ops); +extern void qca8075_phy_interface_set_mode(uint32_t phy_id, + uint32_t mode); +extern int ipq_qca8033_phy_init(struct phy_ops **ops, u32 phy_id); +extern int ipq_qca8081_phy_init(struct phy_ops **ops, u32 phy_id); +extern int ipq_qca_aquantia_phy_init(struct phy_ops **ops, u32 phy_id); +extern int ipq_board_fw_download(unsigned int phy_addr); +static int tftp_acl_our_port; + +/* + * EDMA hardware instance + */ +static u32 ipq807x_edma_hw_addr; + +void ipq807x_edma_dump_data(uchar *data, int len) +{ + int i; + + if (data == NULL) + return; + + pr_info("data address = 0x%x, len = %d \n", (unsigned int)data, len); + + for (i = 0; i < len; i++) { + if ((i % 16) == 0) + printf("\n"); + pr_info("%02x ", (unsigned int)data[i]); + } + + pr_info("\n\n"); +} + +/* + * ipq807x_edma_reg_read() + * Read EDMA register + */ +uint32_t ipq807x_edma_reg_read(uint32_t reg_off) +{ + return (uint32_t)readl(ipq807x_edma_hw_addr + reg_off); +} + +/* + * ipq807x_edma_reg_write() + * Write EDMA register + */ +void ipq807x_edma_reg_write(uint32_t reg_off, uint32_t val) +{ + pr_debug("%s: reg_off = %x, val =%x\n", __func__, reg_off, val); + writel(val, (ipq807x_edma_hw_addr + reg_off)); +} + +/* + * ipq807x_edma_alloc_rx_buffer() + * Alloc Rx buffers for one RxFill ring + */ +int ipq807x_edma_alloc_rx_buffer(struct ipq807x_edma_hw *ehw, + struct ipq807x_edma_rxfill_ring *rxfill_ring) +{ + uint16_t num_alloc = 0; + uint16_t cons, next, counter; + struct ipq807x_edma_rxfill_desc *rxfill_desc; + uint32_t reg_data; + struct ipq807x_edma_rx_preheader *rxph; + + /* + * Read RXFILL ring producer index + */ + reg_data = ipq807x_edma_reg_read(IPQ807X_EDMA_REG_RXFILL_PROD_IDX( + rxfill_ring->id)); + + next = reg_data & IPQ807X_EDMA_RXFILL_PROD_IDX_MASK; + + /* + * Read RXFILL ring consumer index + */ + reg_data = ipq807x_edma_reg_read(IPQ807X_EDMA_REG_RXFILL_CONS_IDX( + rxfill_ring->id)); + + cons = reg_data & IPQ807X_EDMA_RXFILL_CONS_IDX_MASK; + + while (1) { + + counter = next; + + if (++counter == rxfill_ring->count) + counter = 0; + + if (counter == cons) + break; + + if (counter >= CONFIG_SYS_RX_ETH_BUFFER) { + pr_info("%s: counter >= CONFIG_SYS_RX_ETH_BUFFER counter = %d\n", + __func__, counter); + break; + } + /* + * Get RXFILL descriptor + */ + rxfill_desc = IPQ807X_EDMA_RXFILL_DESC(rxfill_ring, next); + + /* + * Make room for Rx preheader + */ + rxph = (struct ipq807x_edma_rx_preheader *)rxfill_desc->buffer_addr; + + /* + * Fill the opaque value + */ + rxph->opaque = next; + + /* + * Save buffer size in RXFILL descriptor + */ + rxfill_desc->word1 = cpu_to_le32(IPQ807X_EDMA_RX_BUFF_SIZE & + IPQ807X_EDMA_RXFILL_BUF_SIZE_MASK); + + num_alloc++; + next = counter; + } + + if (num_alloc) { + /* + * Update RXFILL ring producer index + */ + reg_data = next & IPQ807X_EDMA_RXFILL_PROD_IDX_MASK; + + /* + * make sure the producer index updated before + * updating the hardware + */ + ipq807x_edma_reg_write(IPQ807X_EDMA_REG_RXFILL_PROD_IDX( + rxfill_ring->id), reg_data); + + pr_debug("%s: num_alloc = %d\n", __func__, num_alloc); + } + + return num_alloc; +} + +/* + * ipq807x_edma_clean_tx() + * Reap Tx descriptors + */ +uint32_t ipq807x_edma_clean_tx(struct ipq807x_edma_hw *ehw, + struct ipq807x_edma_txcmpl_ring *txcmpl_ring) +{ + struct ipq807x_edma_txcmpl_desc *txcmpl_desc; + uint16_t prod_idx, cons_idx; + uint32_t data; + uint32_t txcmpl_consumed = 0; + uchar *skb; + + /* + * Get TXCMPL ring producer index + */ + data = ipq807x_edma_reg_read(IPQ807X_EDMA_REG_TXCMPL_PROD_IDX( + txcmpl_ring->id)); + prod_idx = data & IPQ807X_EDMA_TXCMPL_PROD_IDX_MASK; + + /* + * Get TXCMPL ring consumer index + */ + data = ipq807x_edma_reg_read(IPQ807X_EDMA_REG_TXCMPL_CONS_IDX( + txcmpl_ring->id)); + cons_idx = data & IPQ807X_EDMA_TXCMPL_CONS_IDX_MASK; + + while (cons_idx != prod_idx) { + + txcmpl_desc = IPQ807X_EDMA_TXCMPL_DESC(txcmpl_ring, cons_idx); + + skb = (uchar *)txcmpl_desc->buffer_addr; + + if (unlikely(!skb)) { + pr_debug("Invalid skb: cons_idx:%u prod_idx:%u status %x\n", + cons_idx, prod_idx, txcmpl->status); + } + + if (++cons_idx == txcmpl_ring->count) + cons_idx = 0; + + txcmpl_consumed++; + } + + pr_debug("%s :%u txcmpl_consumed:%u prod_idx:%u cons_idx:%u\n", + __func__, txcmpl_ring->id, txcmpl_consumed, prod_idx, + cons_idx); + + if (txcmpl_consumed == 0) + return 0; + + /* + * Update TXCMPL ring consumer index + */ + ipq807x_edma_reg_write(IPQ807X_EDMA_REG_TXCMPL_CONS_IDX( + txcmpl_ring->id), cons_idx); + + return txcmpl_consumed; +} + +/* + * ipq807x_edma_clean_rx() + * Reap Rx descriptors + */ +uint32_t ipq807x_edma_clean_rx(struct ipq807x_edma_common_info *c_info, + struct ipq807x_edma_rxdesc_ring *rxdesc_ring) +{ + void *skb; + struct ipq807x_edma_rxdesc_desc *rxdesc_desc; + struct ipq807x_edma_rx_preheader *rxph; + uint16_t prod_idx, cons_idx; + int src_port_num; + int pkt_length; + int rx = CONFIG_SYS_RX_ETH_BUFFER; + u16 cleaned_count = 0; + struct ipq807x_edma_hw *ehw = &c_info->hw; + + pr_debug("%s: rxdesc_ring->id = %d\n", __func__, rxdesc_ring->id); + /* + * Read Rx ring consumer index + */ + cons_idx = ipq807x_edma_reg_read(IPQ807X_EDMA_REG_RXDESC_CONS_IDX( + rxdesc_ring->id)) & + IPQ807X_EDMA_RXDESC_CONS_IDX_MASK; + + while (rx) { + /* + * Read Rx ring producer index + */ + prod_idx = ipq807x_edma_reg_read( + IPQ807X_EDMA_REG_RXDESC_PROD_IDX(rxdesc_ring->id)) + & IPQ807X_EDMA_RXDESC_PROD_IDX_MASK; + + if (cons_idx == prod_idx) { + pr_debug("%s: cons = prod \n", __func__); + break; + } + + rxdesc_desc = IPQ807X_EDMA_RXDESC_DESC(rxdesc_ring, cons_idx); + + skb = (void *)rxdesc_desc->buffer_addr; + + /* + * Get Rx preheader + */ + rxph = (struct ipq807x_edma_rx_preheader *)skb; + + rx--; + + /* + * Check src_info from Rx preheader + */ + if (IPQ807X_EDMA_RXPH_SRC_INFO_TYPE_GET(rxph) == + IPQ807X_EDMA_PREHDR_DSTINFO_PORTID_IND) { + src_port_num = rxph->src_info & + IPQ807X_EDMA_PREHDR_PORTNUM_BITS; + } else { + pr_warn("WARN: src_info_type:0x%x. Drop skb:%p\n", + IPQ807X_EDMA_RXPH_SRC_INFO_TYPE_GET(rxph), + skb); + goto next_rx_desc; + } + + /* + * Get packet length + */ + pkt_length = rxdesc_desc->status & + IPQ807X_EDMA_RXDESC_PACKET_LEN_MASK; + + if (unlikely((src_port_num < IPQ807X_NSS_DP_START_PHY_PORT) || + (src_port_num > IPQ807X_NSS_DP_MAX_PHY_PORTS))) { + pr_warn("WARN: Port number error :%d. Drop skb:%p\n", + src_port_num, skb); + goto next_rx_desc; + } + + cleaned_count++; + + /* + * Remove Rx preheader + */ + skb = skb + IPQ807X_EDMA_RX_PREHDR_SIZE; + + pr_debug("%s: received pkt %p with length %d\n", + __func__, skb, pkt_length); + + net_process_received_packet(skb, pkt_length); +next_rx_desc: + /* + * Update consumer index + */ + if (++cons_idx == rxdesc_ring->count) + cons_idx = 0; + } + + if (cleaned_count) { + ipq807x_edma_alloc_rx_buffer(ehw, rxdesc_ring->rxfill); + ipq807x_edma_reg_write(IPQ807X_EDMA_REG_RXDESC_CONS_IDX( + rxdesc_ring->id), cons_idx); + } + + return 0; +} + +/* + * ip807x_edma_rx_complete() + */ +static int ipq807x_edma_rx_complete(struct ipq807x_edma_common_info *c_info) +{ + struct ipq807x_edma_hw *ehw = &c_info->hw; + struct ipq807x_edma_txcmpl_ring *txcmpl_ring; + struct ipq807x_edma_rxdesc_ring *rxdesc_ring; + struct ipq807x_edma_rxfill_ring *rxfill_ring; + uint32_t misc_intr_status, reg_data; + int i; + + for (i = 0; i < ehw->rxdesc_rings; i++) { + rxdesc_ring = &ehw->rxdesc_ring[i]; + ipq807x_edma_clean_rx(c_info, rxdesc_ring); + } + + for (i = 0; i < ehw->txcmpl_rings; i++) { + txcmpl_ring = &ehw->txcmpl_ring[i]; + ipq807x_edma_clean_tx(ehw, txcmpl_ring); + } + + for (i = 0; i < ehw->rxfill_rings; i++) { + rxfill_ring = &ehw->rxfill_ring[i]; + ipq807x_edma_alloc_rx_buffer(ehw, rxfill_ring); + } + + /* + * Set RXDESC ring interrupt mask + */ + for (i = 0; i < ehw->rxdesc_rings; i++) { + rxdesc_ring = &ehw->rxdesc_ring[i]; + ipq807x_edma_reg_write( + IPQ807X_EDMA_REG_RXDESC_INT_MASK(rxdesc_ring->id), + ehw->rxdesc_intr_mask); + } + + /* + * Set TXCMPL ring interrupt mask + */ + for (i = 0; i < ehw->txcmpl_rings; i++) { + txcmpl_ring = &ehw->txcmpl_ring[i]; + ipq807x_edma_reg_write(IPQ807X_EDMA_REG_TX_INT_MASK( + txcmpl_ring->id), + ehw->txcmpl_intr_mask); + } + + /* + * Set RXFILL ring interrupt mask + */ + for (i = 0; i < ehw->rxfill_rings; i++) { + rxfill_ring = &ehw->rxfill_ring[i]; + ipq807x_edma_reg_write(IPQ807X_EDMA_REG_RXFILL_INT_MASK( + rxfill_ring->id), + ehw->rxfill_intr_mask); + } + + /* + * Read Misc intr status + */ + reg_data = ipq807x_edma_reg_read(IPQ807X_EDMA_REG_MISC_INT_STAT); + misc_intr_status = reg_data & ehw->misc_intr_mask; + + if (misc_intr_status != 0) { + pr_info("%s: misc_intr_status = 0x%x\n", __func__, + misc_intr_status); + ipq807x_edma_reg_write(IPQ807X_EDMA_REG_MISC_INT_MASK, + IPQ807X_EDMA_MASK_INT_DISABLE); + } + + return 0; +} + +#define MIN_PKT_SIZE 33 +/* + * ipq807x_eth_snd() + * Transmit a packet using an EDMA ring + */ +static int ipq807x_eth_snd(struct eth_device *dev, void *packet, int length) +{ + struct ipq807x_eth_dev *priv = dev->priv; + struct ipq807x_edma_common_info *c_info = priv->c_info; + struct ipq807x_edma_hw *ehw = &c_info->hw; + struct ipq807x_edma_txdesc_desc *txdesc; + struct ipq807x_edma_tx_preheader *txph; + struct ipq807x_edma_txdesc_ring *txdesc_ring; + uint16_t hw_next_to_use, hw_next_to_clean, chk_idx; + uint32_t data; + uchar *skb; + + txdesc_ring = ehw->txdesc_ring; + + if (tftp_acl_our_port != tftp_our_port) { + /* Allowing tftp packets */ + ipq807x_ppe_acl_set(3, 0x4, 0x1, tftp_our_port, 0xffff, 0, 0); + tftp_acl_our_port = tftp_our_port; + } + /* + * Read TXDESC ring producer index + */ + data = ipq807x_edma_reg_read(IPQ807X_EDMA_REG_TXDESC_PROD_IDX( + txdesc_ring->id)); + + hw_next_to_use = data & IPQ807X_EDMA_TXDESC_PROD_IDX_MASK; + + pr_debug("%s: txdesc_ring->id = %d\n", __func__, txdesc_ring->id); + + /* + * Read TXDESC ring consumer index + */ + /* + * TODO - read to local variable to optimize uncached access + */ + data = ipq807x_edma_reg_read( + IPQ807X_EDMA_REG_TXDESC_CONS_IDX(txdesc_ring->id)); + + hw_next_to_clean = data & IPQ807X_EDMA_TXDESC_CONS_IDX_MASK; + + /* + * Check for available Tx descriptor + */ + chk_idx = (hw_next_to_use + 1) & (txdesc_ring->count-1); + + if (chk_idx == hw_next_to_clean) { + return NETDEV_TX_BUSY; + } + + /* + * Get Tx descriptor + */ + txdesc = IPQ807X_EDMA_TXDESC_DESC(txdesc_ring, hw_next_to_use); + + txdesc->word1 = 0; + + skb = (uchar *)txdesc->buffer_addr; + + pr_debug("%s: txdesc->buffer_addr = 0x%x length = %d \ + prod_idx = %d cons_idx = %d\n", + __func__, txdesc->buffer_addr, length, + hw_next_to_use, hw_next_to_clean); + + /* + * Make room for Tx preheader + */ + txph = (struct ipq807x_edma_tx_preheader *)skb; + + memset((void *)txph, 0, IPQ807X_EDMA_TX_PREHDR_SIZE); + +#ifdef CONFIG_IPQ807X_BRIDGED_MODE + /* VP 0x0 share vsi 2 with port 1-4 */ + txph->src_info = 0x2000; + txph->dst_info = 0x0; +#else + /* + * Populate Tx preheader dst info, port id is macid in dp_dev + */ + + txph->dst_info = (IPQ807X_EDMA_PREHDR_DSTINFO_PORTID_IND << 8) | + (IPQ807X_EDMA_MAC_PORT_NO & 0x0fff); + +#endif + + /* + * Set opaque field in preheader + */ + txph->opaque = cpu_to_le32(skb); + + /* + * copy the packet + */ + memcpy(skb + IPQ807X_EDMA_TX_PREHDR_SIZE, packet, length); + /* + * The EDMA HW is unable to process packets less than MIN_PKT_SIZE(33) bytes, + * then the EDMA stalls. This is to pad the packets up to MIN_PKT_SIZE. + */ + if (length < MIN_PKT_SIZE) { + memset(skb + IPQ807X_EDMA_TX_PREHDR_SIZE + length, 0x00, (MIN_PKT_SIZE - length)); + length = MIN_PKT_SIZE; + } + /* + * Populate Tx descriptor + */ + txdesc->word1 |= (1 << IPQ807X_EDMA_TXDESC_PREHEADER_SHIFT) + | ((IPQ807X_EDMA_TX_PREHDR_SIZE & + IPQ807X_EDMA_TXDESC_DATA_OFFSET_MASK) + << IPQ807X_EDMA_TXDESC_DATA_OFFSET_SHIFT); + txdesc->word1 |= ((length & IPQ807X_EDMA_TXDESC_DATA_LENGTH_MASK) + << IPQ807X_EDMA_TXDESC_DATA_LENGTH_SHIFT); + + /* + * Update producer index + */ + hw_next_to_use = (hw_next_to_use + 1) & (txdesc_ring->count - 1); + + /* + * make sure the hw_next_to_use is updated before the + * write to hardware + */ + + ipq807x_edma_reg_write(IPQ807X_EDMA_REG_TXDESC_PROD_IDX( + txdesc_ring->id), hw_next_to_use & + IPQ807X_EDMA_TXDESC_PROD_IDX_MASK); + + pr_debug("%s: successfull\n", __func__); + + return EDMA_TX_OK; +} + +static int ipq807x_eth_recv(struct eth_device *dev) +{ + struct ipq807x_eth_dev *priv = dev->priv; + struct ipq807x_edma_common_info *c_info = priv->c_info; + struct ipq807x_edma_rxdesc_ring *rxdesc_ring; + struct ipq807x_edma_hw *ehw = &c_info->hw; + volatile u32 reg_data; + u32 rxdesc_intr_status = 0; + int i; + + /* + * Read RxDesc intr status + */ + for (i = 0; i < ehw->rxdesc_rings; i++) { + rxdesc_ring = &ehw->rxdesc_ring[i]; + + reg_data = ipq807x_edma_reg_read( + IPQ807X_EDMA_REG_RXDESC_INT_STAT( + rxdesc_ring->id)); + rxdesc_intr_status |= reg_data & + IPQ807X_EDMA_RXDESC_RING_INT_STATUS_MASK; + + /* + * Disable RxDesc intr + */ + ipq807x_edma_reg_write(IPQ807X_EDMA_REG_RXDESC_INT_MASK( + rxdesc_ring->id), + IPQ807X_EDMA_MASK_INT_DISABLE); + } + + ipq807x_edma_rx_complete(c_info); + + return 0; +} + +/* + * ipq807x_edma_setup_ring_resources() + * Allocate/setup resources for EDMA rings + */ +static int ipq807x_edma_setup_ring_resources(struct ipq807x_edma_hw *ehw) +{ + struct ipq807x_edma_txcmpl_ring *txcmpl_ring; + struct ipq807x_edma_txdesc_ring *txdesc_ring; + struct ipq807x_edma_rxfill_ring *rxfill_ring; + struct ipq807x_edma_rxdesc_ring *rxdesc_ring; + struct ipq807x_edma_txdesc_desc *tx_desc; + struct ipq807x_edma_rxfill_desc *rxfill_desc; + int i, j, index; + void *tx_buf; + void *rx_buf; + + /* + * Allocate Rx fill ring descriptors + */ + for (i = 0; i < ehw->rxfill_rings; i++) { + rxfill_ring = &ehw->rxfill_ring[i]; + rxfill_ring->count = IPQ807X_EDMA_RXFILL_RING_SIZE; + rxfill_ring->id = ehw->rxfill_ring_start + i; + rxfill_ring->desc = (void *)noncached_alloc( + sizeof(struct ipq807x_edma_rxfill_desc) * + rxfill_ring->count, + CONFIG_SYS_CACHELINE_SIZE); + + if (rxfill_ring->desc == NULL) { + pr_info("%s: rxfill_ring->desc alloc error\n", __func__); + return -ENOMEM; + } + rxfill_ring->dma = virt_to_phys(rxfill_ring->desc); + rx_buf = (void *)noncached_alloc(PKTSIZE_ALIGN * + rxfill_ring->count, + CONFIG_SYS_CACHELINE_SIZE); + + if (rx_buf == NULL) { + pr_info("%s: rxfill_ring->desc buffer alloc error\n", + __func__); + return -ENOMEM; + } + + for (j = 0; j < rxfill_ring->count; j++) { + rxfill_desc = IPQ807X_EDMA_RXFILL_DESC(rxfill_ring, j); + rxfill_desc->buffer_addr = virt_to_phys(rx_buf); + rx_buf += PKTSIZE_ALIGN; + } + } + + /* + * Allocate RxDesc ring descriptors + */ + for (i = 0; i < ehw->rxdesc_rings; i++) { + rxdesc_ring = &ehw->rxdesc_ring[i]; + rxdesc_ring->count = IPQ807X_EDMA_RXDESC_RING_SIZE; + rxdesc_ring->id = ehw->rxdesc_ring_start + i; + + /* + * Create a mapping between RX Desc ring and Rx fill ring. + * Number of fill rings are lesser than the descriptor rings + * Share the fill rings across descriptor rings. + */ + + index = ehw->rxfill_ring_start + (i % ehw->rxfill_rings); + rxdesc_ring->rxfill = + &ehw->rxfill_ring[index - ehw->rxfill_ring_start]; + rxdesc_ring->rxfill = ehw->rxfill_ring; + + rxdesc_ring->desc = (void *)noncached_alloc( + sizeof(struct ipq807x_edma_rxdesc_desc) * + rxdesc_ring->count, + CONFIG_SYS_CACHELINE_SIZE); + + if (rxdesc_ring->desc == NULL) { + pr_info("%s: rxdesc_ring->desc alloc error\n", __func__); + return -ENOMEM; + } + rxdesc_ring->dma = virt_to_phys(rxdesc_ring->desc); + } + + /* + * Allocate TxCmpl ring descriptors + */ + for (i = 0; i < ehw->txcmpl_rings; i++) { + txcmpl_ring = &ehw->txcmpl_ring[i]; + txcmpl_ring->count = IPQ807X_EDMA_TXCMPL_RING_SIZE; + txcmpl_ring->id = ehw->txcmpl_ring_start + i; + txcmpl_ring->desc = (void *)noncached_alloc( + sizeof(struct ipq807x_edma_txcmpl_desc) * + txcmpl_ring->count, + CONFIG_SYS_CACHELINE_SIZE); + + if (txcmpl_ring->desc == NULL) { + pr_info("%s: txcmpl_ring->desc alloc error\n", __func__); + return -ENOMEM; + } + txcmpl_ring->dma = virt_to_phys(txcmpl_ring->desc); + } + + + /* + * Allocate TxDesc ring descriptors + */ + for (i = 0; i < ehw->txdesc_rings; i++) { + txdesc_ring = &ehw->txdesc_ring[i]; + txdesc_ring->count = IPQ807X_EDMA_TXDESC_RING_SIZE; + txdesc_ring->id = ehw->txdesc_ring_start + i; + txdesc_ring->desc = (void *)noncached_alloc( + sizeof(struct ipq807x_edma_txdesc_desc) * + txdesc_ring->count, + CONFIG_SYS_CACHELINE_SIZE); + + if (txdesc_ring->desc == NULL) { + pr_info("%s: txdesc_ring->desc alloc error\n", __func__); + return -ENOMEM; + } + + txdesc_ring->dma = virt_to_phys(txdesc_ring->desc); + tx_buf = (void *)noncached_alloc(IPQ807X_EDMA_TX_BUF_SIZE * + txdesc_ring->count, + CONFIG_SYS_CACHELINE_SIZE); + + if (tx_buf == NULL) { + pr_info("%s: txdesc_ring->desc buffer alloc error\n", + __func__); + return -ENOMEM; + } + + for (j = 0; j < txdesc_ring->count; j++) { + tx_desc = IPQ807X_EDMA_TXDESC_DESC(txdesc_ring, j); + tx_desc->buffer_addr = virt_to_phys(tx_buf); + tx_buf += IPQ807X_EDMA_TX_BUF_SIZE; + } + } + + pr_info("%s: successfull\n", __func__); + + return 0; + +} + +/* + * ipq807x_edma_free_desc() + * Free EDMA desc memory + */ +static void ipq807x_edma_free_desc(struct ipq807x_edma_common_info *c_info) +{ + struct ipq807x_edma_hw *ehw = &c_info->hw; + struct ipq807x_edma_txcmpl_ring *txcmpl_ring; + struct ipq807x_edma_txdesc_ring *txdesc_ring; + struct ipq807x_edma_rxfill_ring *rxfill_ring; + struct ipq807x_edma_rxdesc_ring *rxdesc_ring; + struct ipq807x_edma_txdesc_desc *tx_desc; + int i; + + for (i = 0; i < ehw->rxfill_rings; i++) { + rxfill_ring = &ehw->rxfill_ring[i]; + if (rxfill_ring->desc) + ipq807x_free_mem(rxfill_ring->desc); + } + + for (i = 0; i < ehw->rxdesc_rings; i++) { + rxdesc_ring = &ehw->rxdesc_ring[i]; + if (rxdesc_ring->desc) + ipq807x_free_mem(rxdesc_ring->desc); + } + + for (i = 0; i < ehw->txcmpl_rings; i++) { + txcmpl_ring = &ehw->txcmpl_ring[i]; + if (txcmpl_ring->desc) { + ipq807x_free_mem(txcmpl_ring->desc); + } + } + + for (i = 0; i < ehw->txdesc_rings; i++) { + txdesc_ring = &ehw->txdesc_ring[i]; + if (txdesc_ring->desc) { + tx_desc = IPQ807X_EDMA_TXDESC_DESC(txdesc_ring, 0); + if (tx_desc->buffer_addr) + ipq807x_free_mem((void *)tx_desc->buffer_addr); + ipq807x_free_mem(txdesc_ring->desc); + } + } +} + +/* + * ipq807x_edma_free_rings() + * Free EDMA software rings + */ +static void ipq807x_edma_free_rings(struct ipq807x_edma_common_info *c_info) +{ + struct ipq807x_edma_hw *ehw = &c_info->hw; + ipq807x_free_mem(ehw->rxfill_ring); + ipq807x_free_mem(ehw->rxdesc_ring); + ipq807x_free_mem(ehw->txdesc_ring); + ipq807x_free_mem(ehw->txcmpl_ring); +} + +static void ipq807x_edma_disable_rings(struct ipq807x_edma_hw *edma_hw) +{ + int i, desc_index; + u32 data; + + /* + * Disable Rx rings + */ + for (i = 0; i < IPQ807X_EDMA_MAX_RXDESC_RINGS; i++) { + data = ipq807x_edma_reg_read(IPQ807X_EDMA_REG_RXDESC_CTRL(i)); + data &= ~IPQ807X_EDMA_RXDESC_RX_EN; + ipq807x_edma_reg_write(IPQ807X_EDMA_REG_RXDESC_CTRL(i), data); + } + + /* + * Disable RxFill Rings + */ + for (i = 0; i < IPQ807X_EDMA_MAX_RXFILL_RINGS; i++) { + data = ipq807x_edma_reg_read( + IPQ807X_EDMA_REG_RXFILL_RING_EN(i)); + data &= ~IPQ807X_EDMA_RXFILL_RING_EN; + ipq807x_edma_reg_write( + IPQ807X_EDMA_REG_RXFILL_RING_EN(i), data); + } + + /* + * Disable Tx rings + */ + for (desc_index = 0; desc_index < + IPQ807X_EDMA_MAX_TXDESC_RINGS; desc_index++) { + data = ipq807x_edma_reg_read( + IPQ807X_EDMA_REG_TXDESC_CTRL(desc_index)); + data &= ~IPQ807X_EDMA_TXDESC_TX_EN; + ipq807x_edma_reg_write( + IPQ807X_EDMA_REG_TXDESC_CTRL(desc_index), data); + } +} + +static void ipq807x_edma_disable_intr(struct ipq807x_edma_hw *ehw) +{ + int i; + + /* + * Disable interrupts + */ + for (i = 0; i < IPQ807X_EDMA_MAX_TXCMPL_RINGS; i++) + ipq807x_edma_reg_write(IPQ807X_EDMA_REG_TX_INT_MASK(i), 0); + + for (i = 0; i < IPQ807X_EDMA_MAX_RXFILL_RINGS; i++) + ipq807x_edma_reg_write(IPQ807X_EDMA_REG_RXFILL_INT_MASK(i), 0); + + for (i = 0; i < IPQ807X_EDMA_MAX_RXDESC_RINGS; i++) + ipq807x_edma_reg_write(IPQ807X_EDMA_REG_RX_INT_CTRL(i), 0); + + ipq807x_edma_reg_write(IPQ807X_EDMA_REG_MISC_INT_MASK, + IPQ807X_EDMA_MASK_INT_DISABLE); +} + +static void set_sgmii_mode(int port_id, int sg_mode) +{ + if (port_id == 4) + sgmii_mode[0] = sg_mode; + else if (port_id == 5) + sgmii_mode[1] = sg_mode; +} + +static int get_sgmii_mode(int port_id) +{ + if (port_id == 4) + return sgmii_mode[0]; + else if (port_id == 5) + return sgmii_mode[1]; + else + return -1; +} + +static int ipq807x_eth_init(struct eth_device *eth_dev, bd_t *this) +{ + struct ipq807x_eth_dev *priv = eth_dev->priv; + struct ipq807x_edma_common_info *c_info = priv->c_info; + struct ipq807x_edma_hw *ehw = &c_info->hw; + static int current_active_port = -1, previous_active_port = -1; + int i; + uint32_t data; + u8 status; + struct phy_ops *phy_get_ops; + fal_port_speed_t speed; + fal_port_duplex_t duplex; + char *lstatus[] = {"up", "Down"}; + char *dp[] = {"Half", "Full"}; + int linkup=0; + int mac_speed = 0, speed_clock1 = 0, speed_clock2 = 0; + int phy_addr, port_8033 = -1, node, aquantia_port = -1; + int sfp_port = -1; + int phy_node = -1; + int ret_sgmii_mode; + char *active_port = NULL; + + node = fdt_path_offset(gd->fdt_blob, "/ess-switch"); + if (node >= 0) + port_8033 = fdtdec_get_uint(gd->fdt_blob, node, "8033_port", -1); + + if (node >= 0) + aquantia_port = fdtdec_get_uint(gd->fdt_blob, node, "aquantia_port", -1); + + if (node >= 0) + sfp_port = fdtdec_get_uint(gd->fdt_blob, node, "sfp_port", -1); + + phy_node = fdt_path_offset(gd->fdt_blob, "/ess-switch/port_phyinfo"); + + active_port = getenv("active_port"); + if (active_port != NULL) { + current_active_port = simple_strtol(active_port, NULL, 10); + if (current_active_port < 0 || current_active_port > 5) + printf("active_port must be in the range of 0 to 5 in ipq807x platform\n"); + } else { + current_active_port = -1; + } + + if (previous_active_port != current_active_port && current_active_port != -1) { + previous_active_port = current_active_port; + printf("Port%d has been set as the active_port\n", current_active_port); + } + + /* + * Check PHY link, speed, Duplex on all phys. + * we will proceed even if single link is up + * else we will return with -1; + */ + for (i = 0; i < PHY_MAX; i++) { + if (current_active_port != -1 && i != current_active_port) { + ipq807x_gmac_port_disable(i); + ppe_port_bridge_txmac_set(i + 1, 1); + + /* + * Note that only for the active port TX/RX MAC would be + * enabled and for all other ports, the same would be + * disabled. + */ + continue; + } + + if (i == sfp_port) { + status = phy_status_get_from_ppe(i); + speed = FAL_SPEED_10000; + duplex = FAL_FULL_DUPLEX; + } else { + if (!priv->ops[i]) { + printf ("Phy ops not mapped\n"); + continue; + } + phy_get_ops = priv->ops[i]; + + if (!phy_get_ops->phy_get_link_status || + !phy_get_ops->phy_get_speed || + !phy_get_ops->phy_get_duplex) { + printf ("Link status/Get speed/Get duplex not mapped\n"); + return -1; + } + + if (phy_node >= 0) { + phy_addr = phy_info[i]->phy_address; + } else { + + if (i == port_8033) + phy_addr = QCA8033_PHY_ADDR; + else if (i == aquantia_port) + phy_addr = AQU_PHY_ADDR; + else + phy_addr = i; + } + status = phy_get_ops->phy_get_link_status(priv->mac_unit, phy_addr); + phy_get_ops->phy_get_speed(priv->mac_unit, phy_addr, &speed); + phy_get_ops->phy_get_duplex(priv->mac_unit, phy_addr, &duplex); + } + + if (status == 0) + linkup++; + + switch (speed) { + case FAL_SPEED_10: + if (i == aquantia_port) { + printf("10M speed not supported\n"); + ppe_port_bridge_txmac_set(i + 1, status); + continue; + } + mac_speed = 0x0; + speed_clock1 = 0x109; + speed_clock2 = 0x9; + printf ("eth%d PHY%d %s Speed :%d %s duplex\n", + priv->mac_unit, i, lstatus[status], speed, + dp[duplex]); + if (phy_node >= 0) { + if (phy_info[i]->phy_type == QCA8081_PHY_TYPE) + set_sgmii_mode(i, 1); + } + break; + case FAL_SPEED_100: + mac_speed = 0x1; + if (i == aquantia_port) { + if (i == 4) + speed_clock1 = 0x309; + else + speed_clock1 = 0x109; + } else if (i == port_8033) + speed_clock1 = 0x109; + else + speed_clock1 = 0x101; + if (i == port_8033) + speed_clock2 = 0x0; + else + speed_clock2 = 0x4; + printf ("eth%d PHY%d %s Speed :%d %s duplex\n", + priv->mac_unit, i, lstatus[status], speed, + dp[duplex]); + if (phy_node >= 0) { + if (phy_info[i]->phy_type == QCA8081_PHY_TYPE) + set_sgmii_mode(i, 1); + } + break; + case FAL_SPEED_1000: + mac_speed = 0x2; + if (i == aquantia_port) { + if (i == 4) + speed_clock1 = 0x304; + else + speed_clock1 = 0x104; + } else + speed_clock1 = 0x101; + speed_clock2 = 0x0; + printf ("eth%d PHY%d %s Speed :%d %s duplex\n", + priv->mac_unit, i, lstatus[status], speed, + dp[duplex]); + if (phy_node >= 0) { + if (phy_info[i]->phy_type == QCA8081_PHY_TYPE) + set_sgmii_mode(i, 1); + if ((phy_info[i]->phy_type == QCA8081_PHY_TYPE) && (i == 4)) + speed_clock1 = 0x301; + } + break; + case FAL_SPEED_10000: + mac_speed = 0x3; + if (i == 4) + speed_clock1 = 0x301; + else + speed_clock1 = 0x101; + speed_clock2 = 0x0; + printf ("eth%d PHY%d %s Speed :%d %s duplex\n", + priv->mac_unit, i, lstatus[status], speed, + dp[duplex]); + break; + case FAL_SPEED_2500: + if (phy_node >= 0) { + if (phy_info[i]->phy_type == QCA8081_PHY_TYPE) { + mac_speed = 0x2; + if (i == 4) + speed_clock1 = 0x301; + else if (i == 5) + speed_clock1 = 0x101; + set_sgmii_mode(i, 0); + speed_clock2 = 0x0; + } + if (phy_info[i]->phy_type == AQ_PHY_TYPE) { + mac_speed = 0x4; + if (i == 4) { + speed_clock1 = 0x301; + speed_clock2 = 0x3; + } else if (i == 5) { + speed_clock1 = 0x107; + speed_clock2 = 0x0; + } + } + } else { + speed_clock1 = 0x107; + mac_speed = 0x4; + speed_clock2 = 0x0; + } + printf ("eth%d PHY%d %s Speed :%d %s duplex\n", + priv->mac_unit, i, lstatus[status], speed, + dp[duplex]); + break; + case FAL_SPEED_5000: + mac_speed = 0x5; + if (i == 4) { + speed_clock1 = 0x301; + speed_clock2 = 0x1; + } else { + speed_clock1 = 0x103; + speed_clock2 = 0x0; + } + printf ("eth%d PHY%d %s Speed :%d %s duplex\n", + priv->mac_unit, i, lstatus[status], speed, + dp[duplex]); + break; + default: + printf("Unknown speed\n"); + break; + } + + if (phy_node >= 0) { + if (phy_info[i]->phy_type == QCA8081_PHY_TYPE) { + ret_sgmii_mode = get_sgmii_mode(i); + if (ret_sgmii_mode == 1) { + ppe_port_bridge_txmac_set(i + 1, 1); + if (i == 4) + ppe_uniphy_mode_set(0x1, PORT_WRAPPER_SGMII0_RGMII4); + else if (i == 5) + ppe_uniphy_mode_set(0x2, PORT_WRAPPER_SGMII0_RGMII4); + + } else if (ret_sgmii_mode == 0) { + ppe_port_bridge_txmac_set(i + 1, 1); + if (i == 4) + ppe_uniphy_mode_set(0x1, PORT_WRAPPER_SGMII_PLUS); + else if (i == 5) + ppe_uniphy_mode_set(0x2, PORT_WRAPPER_SGMII_PLUS); + } + } + } + ipq807x_speed_clock_set(i, speed_clock1, speed_clock2); + if (i == aquantia_port) + ipq807x_uxsgmii_speed_set(i, mac_speed, duplex, status); + else if (i == sfp_port) + ipq807x_10g_r_speed_set(i, status); + else + ipq807x_pqsgmii_speed_set(i, mac_speed, status); + } + + if (linkup <= 0) { + /* No PHY link is alive */ + return -1; + } + + /* + * Alloc Rx buffers + */ + ipq807x_edma_alloc_rx_buffer(ehw, ehw->rxfill_ring); + + /* + * Set DMA request priority + */ + ipq807x_edma_reg_write(IPQ807X_EDMA_REG_DMAR_CTRL, + (1 & IPQ807X_EDMA_DMAR_REQ_PRI_MASK) << + IPQ807X_EDMA_DMAR_REQ_PRI_SHIFT); + + /* + * Enable EDMA + */ + ipq807x_edma_reg_write(IPQ807X_EDMA_REG_PORT_CTRL, + IPQ807X_EDMA_PORT_CTRL_EN); + + /* + * Enable Rx rings + */ + for (i = ehw->rxdesc_ring_start; i < ehw->rxdesc_ring_end; i++) { + data = ipq807x_edma_reg_read(IPQ807X_EDMA_REG_RXDESC_CTRL(i)); + data |= IPQ807X_EDMA_RXDESC_RX_EN; + ipq807x_edma_reg_write(IPQ807X_EDMA_REG_RXDESC_CTRL(i), data); + } + + for (i = ehw->rxfill_ring_start; i < ehw->rxfill_ring_end; i++) { + data = ipq807x_edma_reg_read(IPQ807X_EDMA_REG_RXFILL_RING_EN(i)); + data |= IPQ807X_EDMA_RXFILL_RING_EN; + ipq807x_edma_reg_write(IPQ807X_EDMA_REG_RXFILL_RING_EN(i), data); + } + + /* + * Enable Tx rings + */ + for (i = ehw->txdesc_ring_start; i < ehw->txdesc_ring_end; i++) { + data = ipq807x_edma_reg_read(IPQ807X_EDMA_REG_TXDESC_CTRL(i)); + data |= IPQ807X_EDMA_TXDESC_TX_EN; + ipq807x_edma_reg_write(IPQ807X_EDMA_REG_TXDESC_CTRL(i), data); + } + + pr_info("%s: done\n", __func__); + + return 0; +} + +static int ipq807x_edma_wr_macaddr(struct eth_device *dev) +{ + return 0; +} + +static void ipq807x_eth_halt(struct eth_device *dev) +{ + struct ipq807x_eth_dev *priv = dev->priv; + struct ipq807x_edma_common_info *c_info = priv->c_info; + struct ipq807x_edma_hw *ehw = &c_info->hw; + + ipq807x_edma_disable_intr(ehw); + ipq807x_edma_disable_rings(ehw); + + /* + * Disable EDMA + */ + ipq807x_edma_reg_write(IPQ807X_EDMA_REG_PORT_CTRL, IPQ807X_EDMA_DISABLE); + pr_info("%s: done\n", __func__); +} + +static void ipq807x_edma_set_ring_values(struct ipq807x_edma_hw *edma_hw) +{ + edma_hw->txdesc_ring_start = IPQ807X_EDMA_TX_DESC_RING_START; + edma_hw->txdesc_rings = IPQ807X_EDMA_TX_DESC_RING_NOS; + edma_hw->txdesc_ring_end = IPQ807X_EDMA_TX_DESC_RING_SIZE; + + edma_hw->txcmpl_ring_start = IPQ807X_EDMA_TX_CMPL_RING_START; + edma_hw->txcmpl_rings = IPQ807X_EDMA_RX_FILL_RING_NOS; + edma_hw->txcmpl_ring_end = IPQ807X_EDMA_TX_CMPL_RING_SIZE; + + edma_hw->rxfill_ring_start = IPQ807X_EDMA_RX_FILL_RING_START; + edma_hw->rxfill_rings = IPQ807X_EDMA_RX_FILL_RING_NOS; + edma_hw->rxfill_ring_end = IPQ807X_EDMA_RX_FILL_RING_SIZE; + + edma_hw->rxdesc_ring_start = IPQ807X_EDMA_RX_DESC_RING_START; + edma_hw->rxdesc_rings = IPQ807X_EDMA_RX_DESC_RING_NOS; + edma_hw->rxdesc_ring_end = IPQ807X_EDMA_RX_DESC_RING_SIZE; + + pr_info("Num rings - TxDesc:%u (%u-%u) TxCmpl:%u (%u-%u)\n", + edma_hw->txdesc_rings, edma_hw->txdesc_ring_start, + (edma_hw->txdesc_ring_start + edma_hw->txdesc_rings - 1), + edma_hw->txcmpl_rings, edma_hw->txcmpl_ring_start, + (edma_hw->txcmpl_ring_start + edma_hw->txcmpl_rings - 1)); + + pr_info("RxDesc:%u (%u-%u) RxFill:%u (%u-%u)\n", + edma_hw->rxdesc_rings, edma_hw->rxdesc_ring_start, + (edma_hw->rxdesc_ring_start + edma_hw->rxdesc_rings - 1), + edma_hw->rxfill_rings, edma_hw->rxfill_ring_start, + (edma_hw->rxfill_ring_start + edma_hw->rxfill_rings - 1)); +} + +/* + * ipq807x_edma_alloc_rings() + * Allocate EDMA software rings + */ +static int ipq807x_edma_alloc_rings(struct ipq807x_edma_hw *ehw) +{ + ehw->rxfill_ring = (void *)noncached_alloc((sizeof( + struct ipq807x_edma_rxfill_ring) * + ehw->rxfill_rings), + CONFIG_SYS_CACHELINE_SIZE); + + if (!ehw->rxfill_ring) { + pr_info("%s: rxfill_ring alloc error\n", __func__); + return -ENOMEM; + } + + ehw->rxdesc_ring = (void *)noncached_alloc((sizeof( + struct ipq807x_edma_rxdesc_ring) * + ehw->rxdesc_rings), + CONFIG_SYS_CACHELINE_SIZE); + + if (!ehw->rxdesc_ring) { + pr_info("%s: rxdesc_ring alloc error\n", __func__); + return -ENOMEM; + } + + ehw->txdesc_ring = (void *)noncached_alloc((sizeof( + struct ipq807x_edma_txdesc_ring) * + ehw->txdesc_rings), + CONFIG_SYS_CACHELINE_SIZE); + if (!ehw->txdesc_ring) { + pr_info("%s: txdesc_ring alloc error\n", __func__); + return -ENOMEM; + } + + ehw->txcmpl_ring = (void *)noncached_alloc((sizeof( + struct ipq807x_edma_txcmpl_ring) * + ehw->txcmpl_rings), + CONFIG_SYS_CACHELINE_SIZE); + + if (!ehw->txcmpl_ring) { + pr_info("%s: txcmpl_ring alloc error\n", __func__); + return -ENOMEM; + } + + pr_info("%s: successfull\n", __func__); + + return 0; + +} + + +/* + * ipq807x_edma_init_rings() + * Initialize EDMA rings + */ +static int ipq807x_edma_init_rings(struct ipq807x_edma_hw *ehw) +{ + int ret; + + /* + * Setup ring values + */ + ipq807x_edma_set_ring_values(ehw); + + /* + * Allocate desc rings + */ + ret = ipq807x_edma_alloc_rings(ehw); + if (ret) + return ret; + + /* + * Setup ring resources + */ + ret = ipq807x_edma_setup_ring_resources(ehw); + if (ret) + return ret; + + return 0; +} + +/* + * ipq807x_edma_configure_rx_threshold() + * Configure Rx threshold parameters + */ +static void ipq807x_edma_configure_rx_threshold(void) +{ + uint32_t rxq_fc_thre, rxq_ctrl; + + rxq_fc_thre = (IPQ807X_EDMA_RXFILL_FIFO_XOFF_THRE & + IPQ807X_EDMA_RXFILL_FIFO_XOFF_THRE_MASK) + << IPQ807X_EDMA_RXFILL_FIFO_XOFF_THRE_SHIFT; + + rxq_fc_thre |= (IPQ807X_EDMA_RXFILL_FIFO_XOFF_THRE & + IPQ807X_EDMA_DESC_FIFO_XOFF_THRE_MASK) + << IPQ807X_EDMA_DESC_FIFO_XOFF_THRE_SHIFT; + + ipq807x_edma_reg_write(IPQ807X_EDMA_REG_RXQ_FC_THRE, rxq_fc_thre); + + rxq_ctrl = (IPQ807X_EDMA_RXFILL_PF_THRE & + IPQ807X_EDMA_RXFILL_PF_THRE_MASK) << + IPQ807X_EDMA_RXFILL_PF_THRE_SHIFT; + + rxq_ctrl |= (IPQ807X_EDMA_RXDESC_WB_THRE & + IPQ807X_EDMA_RXDESC_WB_THRE_MASK) << + IPQ807X_EDMA_RXDESC_WB_THRE_SHIFT; + + rxq_ctrl |= (IPQ807X_EDMA_RXDESC_WB_TIMER & + IPQ807X_EDMA_RXDESC_WB_TIMER_MASK) << + IPQ807X_EDMA_RXDESC_WB_TIMER_SHIFT; + + ipq807x_edma_reg_write(IPQ807X_EDMA_REG_RXQ_CTRL, rxq_ctrl); +} + +/* + * ipq807x_edma_configure_tx_threshold() + * Configure global Tx threshold parameters + */ +static void ipq807x_edma_configure_tx_threshold(void) +{ + uint32_t txq_ctrl; + + txq_ctrl = (IPQ807X_EDMA_TXDESC_PF_THRE & + IPQ807X_EDMA_TXDESC_PF_THRE_MASK) << + IPQ807X_EDMA_TXDESC_PF_THRE_SHIFT; + + txq_ctrl |= (IPQ807X_EDMA_TXCMPL_WB_THRE & + IPQ807X_EDMA_TXCMPL_WB_THRE_MASK) << + IPQ807X_EDMA_TXCMPL_WB_THRE_SHIFT; + + txq_ctrl |= (IPQ807X_EDMA_TXDESC_PKT_SRAM_THRE & + IPQ807X_EDMA_TXDESC_PKT_SRAM_THRE_MASK) << + IPQ807X_EDMA_TXDESC_PKT_SRAM_THRE_SHIFT; + + txq_ctrl |= (IPQ807X_EDMA_TXCMPL_WB_TIMER & + IPQ807X_EDMA_TXCMPL_WB_TIMER_MASK) << + IPQ807X_EDMA_TXCMPL_WB_TIMER_SHIFT; + + ipq807x_edma_reg_write(IPQ807X_EDMA_REG_TXQ_CTRL, txq_ctrl); +} + +/* + * ipq807x_edma_configure_txdesc_ring() + * Configure one TxDesc ring + */ +static void ipq807x_edma_configure_txdesc_ring(struct ipq807x_edma_hw *ehw, + struct ipq807x_edma_txdesc_ring *txdesc_ring) +{ + uint32_t data; + uint16_t hw_cons_idx; + + /* + * Configure TXDESC ring + */ + ipq807x_edma_reg_write(IPQ807X_EDMA_REG_TXDESC_BA(txdesc_ring->id), + (uint32_t)(txdesc_ring->dma & + IPQ807X_EDMA_RING_DMA_MASK)); + + ipq807x_edma_reg_write(IPQ807X_EDMA_REG_TXDESC_RING_SIZE( + txdesc_ring->id), (uint32_t)(txdesc_ring->count & + IPQ807X_EDMA_TXDESC_RING_SIZE_MASK)); + + data = ipq807x_edma_reg_read(IPQ807X_EDMA_REG_TXDESC_CONS_IDX( + txdesc_ring->id)); + + data &= ~(IPQ807X_EDMA_TXDESC_CONS_IDX_MASK); + hw_cons_idx = data; + + data = ipq807x_edma_reg_read(IPQ807X_EDMA_REG_TXDESC_PROD_IDX( + txdesc_ring->id)); + + data &= ~(IPQ807X_EDMA_TXDESC_PROD_IDX_MASK); + data |= hw_cons_idx & IPQ807X_EDMA_TXDESC_PROD_IDX_MASK; + + ipq807x_edma_reg_write(IPQ807X_EDMA_REG_TXDESC_PROD_IDX( + txdesc_ring->id), data); +} + +/* + * ipq807x_edma_configure_txcmpl_ring() + * Configure one TxCmpl ring + */ +static void ipq807x_edma_configure_txcmpl_ring(struct ipq807x_edma_hw *ehw, + struct ipq807x_edma_txcmpl_ring *txcmpl_ring) +{ + uint32_t txcmpl_ugt_thre, low_thre = 0, txcmpl_fc_thre = 0; + uint32_t tx_mod_timer; + + /* + * Configure TxCmpl ring base address + */ + ipq807x_edma_reg_write(IPQ807X_EDMA_REG_TXCMPL_BA(txcmpl_ring->id), + (uint32_t)(txcmpl_ring->dma & + IPQ807X_EDMA_RING_DMA_MASK)); + + ipq807x_edma_reg_write(IPQ807X_EDMA_REG_TXCMPL_RING_SIZE( + txcmpl_ring->id), (uint32_t)(txcmpl_ring->count & + IPQ807X_EDMA_TXDESC_RING_SIZE_MASK)); + + /* + * Set TxCmpl ret mode to opaque + */ + ipq807x_edma_reg_write(IPQ807X_EDMA_REG_TXCMPL_CTRL(txcmpl_ring->id), + IPQ807X_EDMA_TXCMPL_RETMODE_OPAQUE); + + txcmpl_ugt_thre = (low_thre & IPQ807X_EDMA_TXCMPL_LOW_THRE_MASK) << + IPQ807X_EDMA_TXCMPL_LOW_THRE_SHIFT; + + txcmpl_ugt_thre |= (txcmpl_fc_thre & IPQ807X_EDMA_TXCMPL_FC_THRE_MASK) + << IPQ807X_EDMA_TXCMPL_FC_THRE_SHIFT; + + ipq807x_edma_reg_write(IPQ807X_EDMA_REG_TXCMPL_UGT_THRE( + txcmpl_ring->id), txcmpl_ugt_thre); + + tx_mod_timer = (IPQ807X_EDMA_TX_MOD_TIMER & + IPQ807X_EDMA_TX_MOD_TIMER_INIT_MASK) << + IPQ807X_EDMA_TX_MOD_TIMER_INIT_SHIFT; + + ipq807x_edma_reg_write(IPQ807X_EDMA_REG_TX_MOD_TIMER(txcmpl_ring->id), + tx_mod_timer); + + ipq807x_edma_reg_write(IPQ807X_EDMA_REG_TX_INT_CTRL(txcmpl_ring->id), + 0x2); +} + +/* + * ipq807x_edma_configure_rxdesc_ring() + * Configure one RxDesc ring + */ +static void ipq807x_edma_configure_rxdesc_ring(struct ipq807x_edma_hw *ehw, + struct ipq807x_edma_rxdesc_ring *rxdesc_ring) +{ + uint32_t data; + + ipq807x_edma_reg_write(IPQ807X_EDMA_REG_RXDESC_BA(rxdesc_ring->id), + (uint32_t)(rxdesc_ring->dma & 0xffffffff)); + + data = rxdesc_ring->count & IPQ807X_EDMA_RXDESC_RING_SIZE_MASK; + data |= (ehw->rx_payload_offset & + IPQ807X_EDMA_RXDESC_PL_OFFSET_MASK) << + IPQ807X_EDMA_RXDESC_PL_OFFSET_SHIFT; + + ipq807x_edma_reg_write(IPQ807X_EDMA_REG_RXDESC_RING_SIZE( + rxdesc_ring->id), data); + + data = (IPQ807X_EDMA_RXDESC_XON_THRE & + IPQ807X_EDMA_RXDESC_FC_XON_THRE_MASK) << + IPQ807X_EDMA_RXDESC_FC_XON_THRE_SHIFT; + + data |= (IPQ807X_EDMA_RXDESC_XOFF_THRE & + IPQ807X_EDMA_RXDESC_FC_XOFF_THRE_MASK) << + IPQ807X_EDMA_RXDESC_FC_XOFF_THRE_SHIFT; + + ipq807x_edma_reg_write(IPQ807X_EDMA_REG_RXDESC_FC_THRE( + rxdesc_ring->id), data); + + data = (IPQ807X_EDMA_RXDESC_LOW_THRE & + IPQ807X_EDMA_RXDESC_LOW_THRE_MASK) << + IPQ807X_EDMA_RXDESC_LOW_THRE_SHIFT; + + ipq807x_edma_reg_write(IPQ807X_EDMA_REG_RXDESC_UGT_THRE( + rxdesc_ring->id), data); + + data = (IPQ807X_EDMA_RX_MOD_TIMER_INIT & + IPQ807X_EDMA_RX_MOD_TIMER_INIT_MASK) << + IPQ807X_EDMA_RX_MOD_TIMER_INIT_SHIFT; + + ipq807x_edma_reg_write(IPQ807X_EDMA_REG_RX_MOD_TIMER( + rxdesc_ring->id), data); + + /* + * Enable ring. Set ret mode to 'opaque'. + */ + ipq807x_edma_reg_write(IPQ807X_EDMA_REG_RX_INT_CTRL( + rxdesc_ring->id), 0x2); +} + +/* + * ipq807x_edma_configure_rxfill_ring() + * Configure one RxFill ring + */ +static void ipq807x_edma_configure_rxfill_ring(struct ipq807x_edma_hw *ehw, + struct ipq807x_edma_rxfill_ring *rxfill_ring) +{ + uint32_t rxfill_low_thre = (rxfill_ring->count / 4); + uint32_t rxfill_xon_thre = (rxfill_ring->count / 8); + uint32_t rxfill_xoff_thre = (rxfill_ring->count / 16); + uint32_t rxfill_fc_thre; + uint32_t rxfill_ugt_thre; + uint32_t data; + + ipq807x_edma_reg_write(IPQ807X_EDMA_REG_RXFILL_BA(rxfill_ring->id), + (uint32_t)(rxfill_ring->dma & IPQ807X_EDMA_RING_DMA_MASK)); + + data = rxfill_ring->count & IPQ807X_EDMA_RXFILL_RING_SIZE_MASK; + + ipq807x_edma_reg_write(IPQ807X_EDMA_REG_RXFILL_RING_SIZE(rxfill_ring->id), data); + + rxfill_fc_thre = (rxfill_xon_thre & IPQ807X_EDMA_RXFILL_FC_XON_THRE_MASK) + << IPQ807X_EDMA_RXFILL_FC_XON_THRE_SHIFT; + rxfill_fc_thre |= (rxfill_xoff_thre & IPQ807X_EDMA_RXFILL_FC_XOFF_THRE_MASK) + << IPQ807X_EDMA_RXFILL_FC_XOFF_THRE_SHIFT; + + ipq807x_edma_reg_write(IPQ807X_EDMA_REG_RXFILL_FC_THRE(rxfill_ring->id), + rxfill_fc_thre); + + rxfill_ugt_thre = (rxfill_low_thre & IPQ807X_EDMA_RXFILL_LOW_THRE_MASK) + << IPQ807X_EDMA_RXFILL_LOW_THRE_SHIFT; + + ipq807x_edma_reg_write(IPQ807X_EDMA_REG_RXFILL_UGT_THRE(rxfill_ring->id), + rxfill_ugt_thre); + +} + + +/* + * ipq807x_edma_configure_rings() + * Configure EDMA rings + */ +static void ipq807x_edma_configure_rings(struct ipq807x_edma_hw *ehw) +{ + int i; + + /* + * Configure TXDESC ring + */ + for (i = 0; i < ehw->txdesc_rings; i++) + ipq807x_edma_configure_txdesc_ring(ehw, &ehw->txdesc_ring[i]); + + /* + * Configure TXCMPL ring + */ + for (i = 0; i < ehw->txcmpl_rings; i++) + ipq807x_edma_configure_txcmpl_ring(ehw, &ehw->txcmpl_ring[i]); + + /* + * Configure RXFILL rings + */ + for (i = 0; i < ehw->rxfill_rings; i++) + ipq807x_edma_configure_rxfill_ring(ehw, &ehw->rxfill_ring[i]); + + /* + * Configure RXDESC ring + */ + for (i = 0; i < ehw->rxdesc_rings; i++) + ipq807x_edma_configure_rxdesc_ring(ehw, &ehw->rxdesc_ring[i]); + + pr_info("%s: successfull\n", __func__); +} + + +/* + * ipq807x_edma_hw_init() + * EDMA hw init + */ +int ipq807x_edma_hw_init(struct ipq807x_edma_hw *ehw) +{ + int ret, desc_index; + uint32_t i, reg; + volatile uint32_t data; + + struct ipq807x_edma_rxdesc_ring *rxdesc_ring = NULL; + + ipq807x_ppe_provision_init(); + + data = ipq807x_edma_reg_read(IPQ807X_EDMA_REG_MAS_CTRL); + printf("EDMA ver %d hw init\n", data); + + /* + * Setup private data structure + */ + ehw->rxfill_intr_mask = IPQ807X_EDMA_RXFILL_INT_MASK; + ehw->rxdesc_intr_mask = IPQ807X_EDMA_RXDESC_INT_MASK_PKT_INT; + ehw->txcmpl_intr_mask = IPQ807X_EDMA_TX_INT_MASK_PKT_INT | + IPQ807X_EDMA_TX_INT_MASK_UGT_INT; + ehw->misc_intr_mask = 0; + ehw->rx_payload_offset = IPQ807X_EDMA_RX_PREHDR_SIZE; + + ipq807x_edma_disable_intr(ehw); + ipq807x_edma_disable_rings(ehw); + + ret = ipq807x_edma_init_rings(ehw); + + if (ret) + return ret; + + ipq807x_edma_configure_rings(ehw); + + /* + * Clear the TXDESC2CMPL_MAP_xx reg before setting up + * the mapping. This register holds TXDESC to TXFILL ring + * mapping. + */ + ipq807x_edma_reg_write(IPQ807X_EDMA_REG_TXDESC2CMPL_MAP_0, 0); + ipq807x_edma_reg_write(IPQ807X_EDMA_REG_TXDESC2CMPL_MAP_1, 0); + ipq807x_edma_reg_write(IPQ807X_EDMA_REG_TXDESC2CMPL_MAP_2, 0); + desc_index = ehw->txcmpl_ring_start; + + /* + * 3 registers to hold the completion mapping for total 24 + * TX desc rings (0-9,10-19 and rest). In each entry 3 bits hold + * the mapping for a particular TX desc ring. + */ + for (i = ehw->txdesc_ring_start; + i < ehw->txdesc_ring_end; i++) { + if (i >= 0 && i <= 9) + reg = IPQ807X_EDMA_REG_TXDESC2CMPL_MAP_0; + else if (i >= 10 && i <= 19) + reg = IPQ807X_EDMA_REG_TXDESC2CMPL_MAP_1; + else + reg = IPQ807X_EDMA_REG_TXDESC2CMPL_MAP_2; + + pr_debug("Configure TXDESC:%u to use TXCMPL:%u\n", + i, desc_index); + + data = ipq807x_edma_reg_read(reg); + data |= (desc_index & 0x7) << ((i % 10) * 3); + ipq807x_edma_reg_write(reg, data); + + desc_index++; + if (desc_index == ehw->txcmpl_ring_end) + desc_index = ehw->txcmpl_ring_start; + } + + /* + * Set PPE QID to EDMA Rx ring mapping. + * When coming up use only queue 0. + * HOST EDMA rings. FW EDMA comes up and overwrites as required. + * Each entry can hold mapping for 8 PPE queues and entry size is + * 4 bytes + */ + desc_index = ehw->rxdesc_ring_start; + data = 0; + data |= (desc_index & 0xF); + ipq807x_edma_reg_write(IPQ807X_EDMA_QID2RID_TABLE_MEM(0), data); + pr_debug("Configure QID2RID reg:0x%x to 0x%x\n", reg, data); + + /* + * Configure Tx/Rx queue threshold parameters + */ + ipq807x_edma_configure_tx_threshold(); + ipq807x_edma_configure_rx_threshold(); + + /* + * Set RXDESC2FILL_MAP_xx reg. + * There are two registers RXDESC2FILL_0 and RXDESC2FILL_1 + * 3 bits holds the rx fill ring mapping for each of the + * rx descriptor ring. + */ + ipq807x_edma_reg_write(IPQ807X_EDMA_REG_RXDESC2FILL_MAP_0, 0); + ipq807x_edma_reg_write(IPQ807X_EDMA_REG_RXDESC2FILL_MAP_1, 0); + + for (i = ehw->rxdesc_ring_start; + i < ehw->rxdesc_ring_end; i++) { + if ((i >= 0) && (i <= 9)) + reg = IPQ807X_EDMA_REG_RXDESC2FILL_MAP_0; + else + reg = IPQ807X_EDMA_REG_RXDESC2FILL_MAP_1; + + rxdesc_ring = &ehw->rxdesc_ring[i - ehw->rxdesc_ring_start]; + + pr_debug("Configure RXDESC:%u to use RXFILL:%u\n", + rxdesc_ring->id, rxdesc_ring->rxfill->id); + + data = ipq807x_edma_reg_read(reg); + data |= (rxdesc_ring->rxfill->id & 0x7) << ((i % 10) * 3); + ipq807x_edma_reg_write(reg, data); + } + + reg = IPQ807X_EDMA_REG_RXDESC2FILL_MAP_0; + pr_debug("EDMA_REG_RXDESC2FILL_MAP_0: 0x%x\n", + ipq807x_edma_reg_read(reg)); + reg = IPQ807X_EDMA_REG_RXDESC2FILL_MAP_1; + pr_debug("EDMA_REG_RXDESC2FILL_MAP_1: 0x%x\n", + ipq807x_edma_reg_read(reg)); + + reg = IPQ807X_EDMA_REG_TXDESC2CMPL_MAP_0; + pr_debug("EDMA_REG_TXDESC2CMPL_MAP_0: 0x%x\n", + ipq807x_edma_reg_read(reg)); + reg = IPQ807X_EDMA_REG_TXDESC2CMPL_MAP_1; + pr_debug("EDMA_REG_TXDESC2CMPL_MAP_1: 0x%x\n", + ipq807x_edma_reg_read(reg)); + reg = IPQ807X_EDMA_REG_TXDESC2CMPL_MAP_2; + pr_debug("EDMA_REG_TXDESC2CMPL_MAP_2: 0x%x\n", + ipq807x_edma_reg_read(reg)); + + /* + * Enable MISC interrupt + */ + ipq807x_edma_reg_write(IPQ807X_EDMA_REG_MISC_INT_MASK, + ehw->misc_intr_mask); + + pr_info("%s: successfull\n", __func__); + return 0; +} + +void get_phy_address(int offset) +{ + int phy_type; + int phy_address; + int i; + + for (i = 0; i < PHY_MAX; i++) + phy_info[i] = ipq807x_alloc_mem(sizeof(phy_info_t)); + i = 0; + for (offset = fdt_first_subnode(gd->fdt_blob, offset); offset > 0; + offset = fdt_next_subnode(gd->fdt_blob, offset)) { + + phy_address = fdtdec_get_uint(gd->fdt_blob, + offset, "phy_address", 0); + phy_type = fdtdec_get_uint(gd->fdt_blob, + offset, "phy_type", 0); + phy_info[i]->phy_address = phy_address; + phy_info[i++]->phy_type = phy_type; + } +} + +int ipq807x_edma_init(void *edma_board_cfg) +{ + struct eth_device *dev[IPQ807X_EDMA_DEV]; + struct ipq807x_edma_common_info *c_info[IPQ807X_EDMA_DEV]; + struct ipq807x_edma_hw *hw[IPQ807X_EDMA_DEV]; + uchar enet_addr[IPQ807X_EDMA_DEV * 6]; + int i, phy_id; + uint32_t phy_chip_id, phy_chip_id1, phy_chip_id2; + int ret = -1; + ipq807x_edma_board_cfg_t ledma_cfg, *edma_cfg; + static int sw_init_done = 0; + int port_8033 = -1, node, phy_addr, aquantia_port = -1; + int mode, phy_node = -1; + + node = fdt_path_offset(gd->fdt_blob, "/ess-switch"); + if (node >= 0) + port_8033 = fdtdec_get_uint(gd->fdt_blob, node, "8033_port", -1); + + if (node >= 0) + aquantia_port = fdtdec_get_uint(gd->fdt_blob, node, "aquantia_port", -1); + + phy_node = fdt_path_offset(gd->fdt_blob, "/ess-switch/port_phyinfo"); + if (phy_node >= 0) + get_phy_address(phy_node); + + mode = fdtdec_get_uint(gd->fdt_blob, node, "switch_mac_mode", -1); + if (mode < 0) { + printf("Error: switch_mac_mode not specified in dts"); + return mode; + } + + memset(c_info, 0, (sizeof(c_info) * IPQ807X_EDMA_DEV)); + memset(enet_addr, 0, sizeof(enet_addr)); + memset(&ledma_cfg, 0, sizeof(ledma_cfg)); + edma_cfg = &ledma_cfg; + strlcpy(edma_cfg->phy_name, "IPQ MDIO0", sizeof(edma_cfg->phy_name)); + + /* Getting the MAC address from ART partition */ + ret = get_eth_mac_address(enet_addr, IPQ807X_EDMA_DEV); + + /* + * Register EDMA as single ethernet + * interface. + */ + for (i = 0; i < IPQ807X_EDMA_DEV; edma_cfg++, i++) { + dev[i] = ipq807x_alloc_mem(sizeof(struct eth_device)); + + if (!dev[i]) + goto init_failed; + + memset(dev[i], 0, sizeof(struct eth_device)); + + c_info[i] = ipq807x_alloc_mem( + sizeof(struct ipq807x_edma_common_info)); + + if (!c_info[i]) + goto init_failed; + + memset(c_info[i], 0, + sizeof(struct ipq807x_edma_common_info)); + + hw[i] = &c_info[i]->hw; + + c_info[i]->hw.hw_addr = (unsigned long __iomem *) + IPQ807X_EDMA_CFG_BASE; + + ipq807x_edma_dev[i] = ipq807x_alloc_mem( + sizeof(struct ipq807x_eth_dev)); + + if (!ipq807x_edma_dev[i]) + goto init_failed; + + memset (ipq807x_edma_dev[i], 0, + sizeof(struct ipq807x_eth_dev)); + + dev[i]->iobase = IPQ807X_EDMA_CFG_BASE; + dev[i]->init = ipq807x_eth_init; + dev[i]->halt = ipq807x_eth_halt; + dev[i]->recv = ipq807x_eth_recv; + dev[i]->send = ipq807x_eth_snd; + dev[i]->write_hwaddr = ipq807x_edma_wr_macaddr; + dev[i]->priv = (void *)ipq807x_edma_dev[i]; + + if ((ret < 0) || + (!is_valid_ethaddr(&enet_addr[edma_cfg->unit * 6]))) { + memcpy(&dev[i]->enetaddr[0], ipq807x_def_enetaddr, 6); + } else { + memcpy(&dev[i]->enetaddr[0], + &enet_addr[edma_cfg->unit * 6], 6); + } + + printf("MAC%x addr:%x:%x:%x:%x:%x:%x\n", + edma_cfg->unit, dev[i]->enetaddr[0], + dev[i]->enetaddr[1], + dev[i]->enetaddr[2], + dev[i]->enetaddr[3], + dev[i]->enetaddr[4], + dev[i]->enetaddr[5]); + + snprintf(dev[i]->name, sizeof(dev[i]->name), "eth%d", i); + + ipq807x_edma_dev[i]->dev = dev[i]; + ipq807x_edma_dev[i]->mac_unit = edma_cfg->unit; + ipq807x_edma_dev[i]->c_info = c_info[i]; + ipq807x_edma_hw_addr = IPQ807X_EDMA_CFG_BASE; + + ret = ipq_sw_mdio_init(edma_cfg->phy_name); + if (ret) + goto init_failed; + + for (phy_id = 0; phy_id < PHY_MAX; phy_id++) { + if (phy_node >= 0) { + phy_addr = phy_info[phy_id]->phy_address; + } else { + if (phy_id == port_8033) + phy_addr = QCA8033_PHY_ADDR; + else if (phy_id == aquantia_port) + phy_addr = AQU_PHY_ADDR; + else + phy_addr = phy_id; + } + + phy_chip_id1 = ipq_mdio_read(phy_addr, QCA_PHY_ID1, NULL); + phy_chip_id2 = ipq_mdio_read(phy_addr, QCA_PHY_ID2, NULL); + phy_chip_id = (phy_chip_id1 << 16) | phy_chip_id2; + if (phy_id == aquantia_port) { + phy_chip_id1 = ipq_mdio_read(phy_addr, (1<<30) |(1<<16) | QCA_PHY_ID1, NULL); + phy_chip_id2 = ipq_mdio_read(phy_addr, (1<<30) |(1<<16) | QCA_PHY_ID2, NULL); + phy_chip_id = (phy_chip_id1 << 16) | phy_chip_id2; + } + switch(phy_chip_id) { + case QCA8075_PHY_V1_0_5P: + case QCA8075_PHY_V1_1_5P: + case QCA8075_PHY_V1_1_2P: + + if (!sw_init_done) { + if (ipq_qca8075_phy_init(&ipq807x_edma_dev[i]->ops[phy_id]) == 0) { + sw_init_done = 1; + } + } else { + ipq_qca8075_phy_map_ops(&ipq807x_edma_dev[i]->ops[phy_id]); + } + + if (mode == PORT_WRAPPER_PSGMII) + qca8075_phy_interface_set_mode(0x0, 0x0); + else if ( mode == PORT_WRAPPER_QSGMII) + qca8075_phy_interface_set_mode(0x0, 0x4); + break; +#ifdef CONFIG_QCA8033_PHY + case QCA8033_PHY: + ipq_qca8033_phy_init(&ipq807x_edma_dev[i]->ops[phy_id], phy_addr); + break; +#endif +#ifdef CONFIG_QCA8081_PHY + case QCA8081_PHY: + case QCA8081_1_1_PHY: + ipq_qca8081_phy_init(&ipq807x_edma_dev[i]->ops[phy_id], phy_addr); + break; +#endif +#ifdef CONFIG_QCA_AQUANTIA_PHY + case AQUANTIA_PHY_107: + case AQUANTIA_PHY_109: + case AQUANTIA_PHY_111: + case AQUANTIA_PHY_112: + case AQUANTIA_PHY_111B0: + case AQUANTIA_PHY_112C: + ipq_board_fw_download(phy_addr); + ipq_qca_aquantia_phy_init(&ipq807x_edma_dev[i]->ops[phy_id], phy_addr); + break; +#endif + default: + ipq_qca8075_phy_map_ops(&ipq807x_edma_dev[i]->ops[phy_id]); + break; + } + } + + ret = ipq807x_edma_hw_init(hw[i]); + + if (ret) + goto init_failed; + + eth_register(dev[i]); + } + + return 0; + +init_failed: + printf("Error in allocating Mem\n"); + + for (i = 0; i < IPQ807X_EDMA_DEV; i++) { + if (dev[i]) { + eth_unregister(dev[i]); + ipq807x_free_mem(dev[i]); + } + if (c_info[i]) { + ipq807x_edma_free_desc(c_info[i]); + ipq807x_edma_free_rings(c_info[i]); + ipq807x_free_mem(c_info[i]); + } + if (ipq807x_edma_dev[i]) { + ipq807x_free_mem(ipq807x_edma_dev[i]); + } + } + + return -1; +} diff --git a/sources/uboot-be550/drivers/net/ipq807x/ipq807x_edma.h b/sources/uboot-be550/drivers/net/ipq807x/ipq807x_edma.h new file mode 100644 index 00000000..51d59921 --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq807x/ipq807x_edma.h @@ -0,0 +1,328 @@ +/* + ************************************************************************** + * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT + * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + ************************************************************************** +*/ +#ifndef __IPQ807X_EDMA__ +#define __IPQ807X_EDMA__ + +#define IPQ807X_NSS_DP_START_PHY_PORT 1 +#define IPQ807X_NSS_DP_MAX_PHY_PORTS 6 + +#define IPQ807X_EDMA_BUF_SIZE 2000 +#define IPQ807X_EDMA_DEVICE_NODE_NAME "edma" +#define IPQ807X_EDMA_RX_BUFF_SIZE (IPQ807X_EDMA_BUF_SIZE + IPQ807X_EDMA_RX_PREHDR_SIZE) +#define IPQ807X_EDMA_RX_PREHDR_SIZE (sizeof(struct ipq807x_edma_rx_preheader)) +#define IPQ807X_EDMA_TX_PREHDR_SIZE (sizeof(struct ipq807x_edma_tx_preheader)) + +#define IPQ807X_EDMA_TXDESC_RING_SIZE 8 +#define IPQ807X_EDMA_TXCMPL_RING_SIZE 8 +#define IPQ807X_EDMA_RXDESC_RING_SIZE 16 +#define IPQ807X_EDMA_RXFILL_RING_SIZE 16 + +#define IPQ807X_EDMA_START_GMACS IPQ807X_NSS_DP_START_PHY_PORT +#define IPQ807X_EDMA_MAX_GMACS IPQ807X_NSS_DP_MAX_PHY_PORTS +#define IPQ807X_EDMA_TX_BUF_SIZE (1540 + IPQ807X_EDMA_TX_PREHDR_SIZE) + +#define IPQ807X_EDMA_MAX_TXCMPL_RINGS 8 /* Max TxCmpl rings */ +#define IPQ807X_EDMA_MAX_RXDESC_RINGS 16 /* Max RxDesc rings */ +#define IPQ807X_EDMA_MAX_RXFILL_RINGS 8 /* Max RxFill rings */ +#define IPQ807X_EDMA_MAX_TXDESC_RINGS 24 /* Max TxDesc rings */ + +#define IPQ807X_EDMA_GET_DESC(R, i, type) (&(((type *)((R)->desc))[i])) +#define IPQ807X_EDMA_RXFILL_DESC(R, i) IPQ807X_EDMA_GET_DESC(R, i, struct ipq807x_edma_rxfill_desc) +#define IPQ807X_EDMA_RXDESC_DESC(R, i) IPQ807X_EDMA_GET_DESC(R, i, struct ipq807x_edma_rxdesc_desc) +#define IPQ807X_EDMA_TXDESC_DESC(R, i) IPQ807X_EDMA_GET_DESC(R, i, struct ipq807x_edma_txdesc_desc) +#define IPQ807X_EDMA_TXCMPL_DESC(R, i) IPQ807X_EDMA_GET_DESC(R, i, struct ipq807x_edma_txcmpl_desc) +#define IPQ807X_EDMA_RXPH_SRC_INFO_TYPE_GET(rxph) (((rxph)->src_info >> 8) & 0xf0) + +#define IPQ807X_EDMA_DEV 1 +#define IPQ807X_EDMA_TX_QUEUE 1 +#define IPQ807X_EDMA_RX_QUEUE 1 + +//#define IPQ807X_EDMA_TX_DESC_RING_START 23 +#define IPQ807X_EDMA_TX_DESC_RING_START 0 +#define IPQ807X_EDMA_TX_DESC_RING_NOS 1 +#define IPQ807X_EDMA_TX_DESC_RING_SIZE \ +(IPQ807X_EDMA_TX_DESC_RING_START + IPQ807X_EDMA_TX_DESC_RING_NOS) + +#define IPQ807X_EDMA_TX_CMPL_RING_START 7 +#define IPQ807X_EDMA_TX_CMPL_RING_NOS 1 +#define IPQ807X_EDMA_TX_CMPL_RING_SIZE \ +(IPQ807X_EDMA_TX_CMPL_RING_START + IPQ807X_EDMA_TX_CMPL_RING_NOS) + +#define IPQ807X_EDMA_RX_DESC_RING_START 15 +#define IPQ807X_EDMA_RX_DESC_RING_NOS 1 +#define IPQ807X_EDMA_RX_DESC_RING_SIZE \ +(IPQ807X_EDMA_RX_DESC_RING_START + IPQ807X_EDMA_RX_DESC_RING_NOS) + +#define IPQ807X_EDMA_RX_FILL_RING_START 7 +#define IPQ807X_EDMA_RX_FILL_RING_NOS 1 +#define IPQ807X_EDMA_RX_FILL_RING_SIZE \ +(IPQ807X_EDMA_RX_FILL_RING_START + IPQ807X_EDMA_RX_FILL_RING_NOS) + +#define IPQ807X_EDMA_TX_IMR_NORMAL_MASK 1 +#define IPQ807X_EDMA_RX_IMR_NORMAL_MASK 1 +#define IPQ807X_EDMA_INTR_CLEAR_TYPE 0 +#define IPQ807X_EDMA_INTR_SW_IDX_W_TYPE 0 +#define IPQ807X_EDMA_RSS_TYPE_NONE 0x1 + +#define NETDEV_TX_BUSY 1 + +#define PSGMIIPHY_PLL_VCO_RELATED_CTRL 0x0009878c +#define PSGMIIPHY_PLL_VCO_VAL 0x2803 + +#define PSGMIIPHY_VCO_CALIBRATION_CTRL 0x0009809c +#define PSGMIIPHY_VCO_VAL 0x4ADA +#define PSGMIIPHY_VCO_RST_VAL 0xADA + +#define RGMII_TCSR_ESS_CFG 0x01953000 +#define ESS_RGMII_CTRL 0x0C000004 +/* + * Tx descriptor + */ +struct ipq807x_edma_txdesc_desc { + uint32_t buffer_addr; + /* buffer address */ + uint32_t word1; + /* more bit, TSO, preheader, pool, offset and length */ +}; + +/* + * TxCmpl descriptor + */ +struct ipq807x_edma_txcmpl_desc { + uint32_t buffer_addr; /* buffer address/opaque */ + uint32_t status; /* status */ +}; + +/* + * Rx descriptor + */ +struct ipq807x_edma_rxdesc_desc { + uint32_t buffer_addr; /* buffer address */ + uint32_t status; /* status */ +}; + +/* + * RxFill descriptor + */ +struct ipq807x_edma_rxfill_desc { + uint32_t buffer_addr; /* Buffer address */ + uint32_t word1; /* opaque_ind and buffer size */ +}; + +/* + * Tx descriptor ring + */ +struct ipq807x_edma_txdesc_ring { + uint32_t id; /* TXDESC ring number */ + void *desc; /* descriptor ring virtual address */ + dma_addr_t dma; /* descriptor ring physical address */ + uint16_t count; /* number of descriptors */ +}; + +/* + * TxCmpl ring + */ +struct ipq807x_edma_txcmpl_ring { + uint32_t id; /* TXCMPL ring number */ + void *desc; /* descriptor ring virtual address */ + dma_addr_t dma; /* descriptor ring physical address */ + uint16_t count; /* number of descriptors in the ring */ +}; + +/* + * RxFill ring + */ +struct ipq807x_edma_rxfill_ring { + uint32_t id; /* RXFILL ring number */ + void *desc; /* descriptor ring virtual address */ + dma_addr_t dma; /* descriptor ring physical address */ + uint16_t count; /* number of descriptors in the ring */ +}; + +/* + * RxDesc ring + */ +struct ipq807x_edma_rxdesc_ring { + uint32_t id; /* RXDESC ring number */ + struct ipq807x_edma_rxfill_ring *rxfill; /* RXFILL ring used */ + void *desc; /* descriptor ring virtual address */ + dma_addr_t dma; /* descriptor ring physical address */ + uint16_t count; /* number of descriptors in the ring */ +}; + +/* + * EDMA Tx Preheader + */ +struct ipq807x_edma_tx_preheader { + uint32_t opaque; /* Opaque, contains skb pointer */ + uint16_t src_info; /* Src information */ + uint16_t dst_info; /* Dest information */ + uint32_t tx_pre2; /* SVLAN & CVLAN flag, drop prec, hash value */ + uint32_t tx_pre3; /* STAG, CTAG */ + uint32_t tx_pre4; /* CPU code, L3 & L4 offset, service code */ + uint32_t tx_pre5; /* IP addr index, ACL index */ + uint32_t tx_pre6; /* IP payload checksum, copy2cpu, timestamp, dscp */ + uint32_t tx_pre7; /* Timestamp, QoS TAG */ +}; + +/* + * EDMA Rx Preheader + */ +struct ipq807x_edma_rx_preheader { + uint32_t opaque; /* Opaque, contains skb pointer*/ + uint16_t src_info; /* Src information */ + uint16_t dst_info; /* Dest information */ + uint32_t rx_pre2; /* SVLAN & CVLAN flag, drop prec, hash value */ + uint32_t rx_pre3; /* STAG, CTAG */ + uint32_t rx_pre4; /* CPU code, L3 & L4 offset, service code */ + uint32_t rx_pre5; /* IP addr index, ACL index */ + uint32_t rx_pre6; /* IP payload checksum, copy2cpu, timestamp, dscp */ + uint32_t rx_pre7; /* Timestamp, QoS TAG */ +}; + +enum ipq807x_edma_tx { + EDMA_TX_OK = 0, /* Tx success */ + EDMA_TX_DESC = 1, /* Not enough descriptors */ + EDMA_TX_FAIL = 2, /* Tx failure */ +}; + + +/* per core queue related information */ +struct queue_per_cpu_info { + u32 tx_mask; /* tx interrupt mask */ + u32 rx_mask; /* rx interrupt mask */ + u32 tx_status; /* tx interrupt status */ + u32 rx_status; /* rx interrupt status */ + u32 tx_start; /* tx queue start */ + u32 rx_start; /* rx queue start */ + struct ipq807x_edma_common_info *c_info; /* edma common info */ +}; + +/* edma hw specific data */ +struct ipq807x_edma_hw { + unsigned long __iomem *hw_addr; /* inner register address */ + u8 intr_clear_type; /* interrupt clear */ + u8 intr_sw_idx_w; /* To do chk type interrupt software index */ + u16 rx_buff_size; /* To do chk type Rx buffer size */ + u8 rss_type; /* rss protocol type */ + uint16_t rx_payload_offset; /* start of the payload offset */ + uint32_t flags; /* internal flags */ + int active; /* status */ + struct ipq807x_edma_txdesc_ring *txdesc_ring; /* Tx Descriptor Ring, SW is producer */ + struct ipq807x_edma_txcmpl_ring *txcmpl_ring; /* Tx Completion Ring, SW is consumer */ + struct ipq807x_edma_rxdesc_ring *rxdesc_ring; /* Rx Descriptor Ring, SW is consumer */ + struct ipq807x_edma_rxfill_ring *rxfill_ring; /* Rx Fill Ring, SW is producer */ + uint32_t txdesc_rings; /* Number of TxDesc rings */ + uint32_t txdesc_ring_start; /* Id of first TXDESC ring */ + uint32_t txdesc_ring_end; /* Id of the last TXDESC ring */ + uint32_t txcmpl_rings; /* Number of TxCmpl rings */ + uint32_t txcmpl_ring_start; /* Id of first TXCMPL ring */ + uint32_t txcmpl_ring_end; /* Id of last TXCMPL ring */ + uint32_t rxfill_rings; /* Number of RxFill rings */ + uint32_t rxfill_ring_start; /* Id of first RxFill ring */ + uint32_t rxfill_ring_end; /* Id of last RxFill ring */ + uint32_t rxdesc_rings; /* Number of RxDesc rings */ + uint32_t rxdesc_ring_start; /* Id of first RxDesc ring */ + uint32_t rxdesc_ring_end; /* Id of last RxDesc ring */ + uint32_t tx_intr_mask; /* tx interrupt mask */ + uint32_t rx_intr_mask; /* rx interrupt mask */ + uint32_t rxfill_intr_mask; /* Rx fill ring interrupt mask */ + uint32_t rxdesc_intr_mask; /* Rx Desc ring interrupt mask */ + uint32_t txcmpl_intr_mask; /* Tx Cmpl ring interrupt mask */ + uint32_t misc_intr_mask; /* misc interrupt interrupt mask */ +}; + +struct ipq807x_edma_common_info { + struct ipq807x_edma_hw hw; +}; + +#define MAX_PHY 6 +struct ipq807x_eth_dev { + u8 *phy_address; + uint no_of_phys; + uint interface; + uint speed; + uint duplex; + uint sw_configured; + uint mac_unit; + uint mac_ps; + int link_printed; + u32 padding; + struct eth_device *dev; + struct ipq807x_edma_common_info *c_info; + struct phy_ops *ops[MAX_PHY]; + const char phy_name[MDIO_NAME_LEN]; +} __attribute__ ((aligned(8))); + +static inline void* ipq807x_alloc_mem(u32 size) +{ + void *p = malloc(size); + if (p != NULL) + memset(p, 0, size); + return p; +} + +static inline void* ipq807x_alloc_memalign(u32 size) +{ + void *p = memalign(CONFIG_SYS_CACHELINE_SIZE, size); + if (p != NULL) + memset(p, 0, size); + return p; +} + +static inline void ipq807x_free_mem(void *ptr) +{ + if (ptr) + free(ptr); +} + +//extern struct ipq807x_edma_hw ipq807x_edma_hw; + +uint32_t ipq807x_edma_reg_read(uint32_t reg_off); +void ipq807x_edma_reg_write(uint32_t reg_off, uint32_t val); + + +extern int get_eth_mac_address(uchar *enetaddr, uint no_of_macs); + +typedef struct { + uint count; + u8 addr[7]; +} ipq807x_edma_phy_addr_t; + +/* ipq807x edma Paramaters */ +typedef struct { + uint base; + int unit; + uint mac_conn_to_phy; + phy_interface_t phy; + ipq807x_edma_phy_addr_t phy_addr; + char phy_name[MDIO_NAME_LEN]; +} ipq807x_edma_board_cfg_t; + +extern void ipq807x_ppe_provision_init(void); +extern void ipq807x_speed_clock_set(int port, int speed_clock1, int speed_clock2); +extern void ipq807x_gmac_port_disable(int port); +extern void ipq807x_pqsgmii_speed_set(int port, int speed, int status); +extern void ipq807x_uxsgmii_speed_set(int port, int speed, int duplex, int status); +extern void ppe_port_bridge_txmac_set(int port, int status); +extern void ipq807x_10g_r_speed_set(int port, int status); +extern int phy_status_get_from_ppe(int port_id); + +extern void ipq807x_ppe_acl_set(int rule_id, int rule_type, int pkt_type, int l4_port_no, int l4_port_mask, int permit, int deny); +extern void ppe_uniphy_mode_set(uint32_t uniphy_index, uint32_t mode); +#endif /* ___IPQ807X_EDMA__ */ diff --git a/sources/uboot-be550/drivers/net/ipq807x/ipq807x_ppe.c b/sources/uboot-be550/drivers/net/ipq807x/ipq807x_ppe.c new file mode 100644 index 00000000..ae34a42b --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq807x/ipq807x_ppe.c @@ -0,0 +1,1323 @@ +/* + ************************************************************************** + * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT + * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + ************************************************************************** + */ + +#include +#include +#include "ipq807x_ppe.h" +#include "ipq807x_uniphy.h" +#include +#include "ipq_phy.h" + +DECLARE_GLOBAL_DATA_PTR; +#define pr_info(fmt, args...) printf(fmt, ##args); +/* + * ipq807x_ppe_gpio_reg_write() + */ +static inline void ipq807x_ppe_gpio_reg_write(u32 reg, u32 val) +{ + writel(val, IPQ807X_PPE_FPGA_GPIO_BASE_ADDR + reg); +} + +/* + * ipq807x_ppe_reg_read() + */ +static inline void ipq807x_ppe_reg_read(u32 reg, u32 *val) +{ + *val = readl((void *)(IPQ807X_PPE_BASE_ADDR + reg)); +} + +/* + * ipq807x_ppe_reg_write() + */ +static inline void ipq807x_ppe_reg_write(u32 reg, u32 val) +{ + writel(val, (void *)(IPQ807X_PPE_BASE_ADDR + reg)); +} + +void ppe_ipo_rule_reg_set(union ipo_rule_reg_u *hw_reg, int rule_id) +{ + int i; + + for (i = 0; i < 3; i++) { + ipq807x_ppe_reg_write(IPO_CSR_BASE_ADDR + IPO_RULE_REG_ADDRESS + + (rule_id * IPO_RULE_REG_INC) + (i * 4), hw_reg->val[i]); + } +} + +void ppe_ipo_mask_reg_set(union ipo_mask_reg_u *hw_mask, int rule_id) +{ + int i; + + for (i = 0; i < 2; i++) { + ipq807x_ppe_reg_write((IPO_CSR_BASE_ADDR + IPO_MASK_REG_ADDRESS + + (rule_id * IPO_MASK_REG_INC) + (i * 4)), hw_mask->val[i]); + } +} + +void ppe_ipo_action_set(union ipo_action_u *hw_act, int rule_id) +{ + int i; + + for (i = 0; i < 5; i++) { + ipq807x_ppe_reg_write((IPE_L2_BASE_ADDR + IPO_ACTION_ADDRESS + + (rule_id * IPO_ACTION_INC) + (i * 4)), hw_act->val[i]); + } +} + +void ipq807x_ppe_acl_set(int rule_id, int rule_type, int pkt_type, int l4_port_no, int l4_port_mask, int permit, int deny) +{ + union ipo_rule_reg_u hw_reg = {0}; + union ipo_mask_reg_u hw_mask = {0}; + union ipo_action_u hw_act = {0}; + + memset(&hw_reg, 0, sizeof(hw_reg)); + memset(&hw_mask, 0, sizeof(hw_mask)); + memset(&hw_act, 0, sizeof(hw_act)); + + if (rule_id < MAX_RULE) { + if (rule_type == ADPT_ACL_HPPE_IPV4_DIP_RULE) { + hw_reg.bf.rule_type = ADPT_ACL_HPPE_IPV4_DIP_RULE; + hw_reg.bf.rule_field_0 = l4_port_no; + hw_reg.bf.rule_field_1 = pkt_type<<17; + hw_mask.bf.maskfield_0 = l4_port_mask; + hw_mask.bf.maskfield_1 = 7<<17; + if (permit == 0x0) { + hw_act.bf.dest_info_change_en = 1; + hw_act.bf.fwd_cmd = 0;/*forward*/ + hw_reg.bf.pri = 0x1; + } + + if (deny == 0x1) { + hw_act.bf.dest_info_change_en = 1; + hw_act.bf.fwd_cmd = 1;/*drop*/ + hw_reg.bf.pri = 0x0; + + } + hw_reg.bf.src_0 = 0x6; + hw_reg.bf.src_1 = 0x7; + ppe_ipo_rule_reg_set(&hw_reg, rule_id); + ppe_ipo_mask_reg_set(&hw_mask, rule_id); + ppe_ipo_action_set(&hw_act, rule_id); + } + } +} + +/* + * ipq807x_ppe_vp_port_tbl_set() + */ +static void ipq807x_ppe_vp_port_tbl_set(int port, int vsi) +{ + u32 addr = IPQ807X_PPE_L3_VP_PORT_TBL_ADDR + + (port * IPQ807X_PPE_L3_VP_PORT_TBL_INC); + ipq807x_ppe_reg_write(addr, 0x0); + ipq807x_ppe_reg_write(addr + 0x4 , 1 << 9 | vsi << 10); + ipq807x_ppe_reg_write(addr + 0x8, 0x0); +} + +/* + * ipq807x_ppe_ucast_queue_map_tbl_queue_id_set() + */ +static void ipq807x_ppe_ucast_queue_map_tbl_queue_id_set(int queue, int port) +{ + uint32_t val; + + ipq807x_ppe_reg_read(IPQ807X_PPE_QM_UQM_TBL + + (port * IPQ807X_PPE_UCAST_QUEUE_MAP_TBL_INC), &val); + + val |= queue << 4; + + ipq807x_ppe_reg_write(IPQ807X_PPE_QM_UQM_TBL + + (port * IPQ807X_PPE_UCAST_QUEUE_MAP_TBL_INC), val); +} + +/* + * ipq807x_vsi_setup() + */ +static void ipq807x_vsi_setup(int vsi, uint8_t group_mask) +{ + uint32_t val = (group_mask << 24 | group_mask << 16 | group_mask << 8 + | group_mask); + + /* Set mask */ + ipq807x_ppe_reg_write(0x061800 + (vsi * 0x10), val); + + /* new addr lrn en | station move lrn en */ + ipq807x_ppe_reg_write(0x061804 + (vsi * 0x10), 0x9); +} + +/* + * ipq807x_gmac_enable() + */ + +static void ipq807x_gmac_enable(void) +{ + writel(0x0, 0x1008004); +} + +/* + * ipq807x_gmac_port_disable() + */ +void ipq807x_gmac_port_disable(int port) +{ + ipq807x_ppe_reg_write(IPQ807X_PPE_MAC_ENABLE + (0x200 * port), 0x70); + ipq807x_ppe_reg_write(IPQ807X_PPE_MAC_SPEED + (0x200 * port), 0x2); + ipq807x_ppe_reg_write(IPQ807X_PPE_MAC_MIB_CTL + (0x200 * port), 0x1); +} + +void ipq807x_speed_clock_set(int port, int speed_clock1, int speed_clock2) +{ + int i; + + for (i = 0; i < 2; i++) + { + writel(speed_clock2, GCC_NSS_PORT1_RX_MISC + i*4 + port*0x10); + writel(speed_clock1, GCC_NSS_PORT1_RX_CFG_RCGR + i*8 + port*0x10); + writel(0x1, GCC_NSS_PORT1_RX_CMD_RCGR + i*8 + port*0x10); + } +} + +int phy_status_get_from_ppe(int port_id) +{ + uint32_t reg_field = 0; + + ipq807x_ppe_reg_read(PORT_PHY_STATUS_ADDRESS, ®_field); + if (port_id == (PORT5 - PPE_UNIPHY_INSTANCE1)) + reg_field >>= PORT_PHY_STATUS_PORT5_1_OFFSET; + else + reg_field >>= PORT_PHY_STATUS_PORT6_OFFSET; + + return ((reg_field >> 7) & 0x1) ? 0 : 1; +} + +void ppe_port_bridge_txmac_set(int port_id, int status) +{ + uint32_t reg_value = 0; + + ipq807x_ppe_reg_read(IPE_L2_BASE_ADDR + PORT_BRIDGE_CTRL_ADDRESS + + (port_id * PORT_BRIDGE_CTRL_INC), ®_value); + if (status == 0) + reg_value |= TX_MAC_EN; + else + reg_value &= ~TX_MAC_EN; + + ipq807x_ppe_reg_write(IPE_L2_BASE_ADDR + PORT_BRIDGE_CTRL_ADDRESS + + (port_id * PORT_BRIDGE_CTRL_INC), reg_value); + +} + +void ipq807x_pqsgmii_speed_set(int port, int speed, int status) +{ + ppe_port_bridge_txmac_set(port + 1, status); + ipq807x_ppe_reg_write(IPQ807X_PPE_MAC_SPEED + (0x200 * port), speed); + ipq807x_ppe_reg_write(IPQ807X_PPE_MAC_ENABLE + (0x200 * port), 0x73); +} + + + +void ppe_xgmac_speed_set(uint32_t uniphy_index, int speed) +{ + uint32_t reg_value = 0; + + ipq807x_ppe_reg_read(PPE_SWITCH_NSS_SWITCH_XGMAC0 + + (uniphy_index * NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION), ®_value); + + switch(speed) { + case 0: + case 1: + case 2: + reg_value &=~USS; + reg_value |=SS(XGMAC_SPEED_SELECT_1000M); + break; + case 3: + reg_value |=USS; + reg_value |=SS(XGMAC_SPEED_SELECT_10000M); + break; + case 4: + reg_value |=USS; + reg_value |=SS(XGMAC_SPEED_SELECT_2500M); + break; + case 5: + reg_value |=USS; + reg_value |=SS(XGMAC_SPEED_SELECT_5000M); + break; + } + reg_value |=JD; + ipq807x_ppe_reg_write(PPE_SWITCH_NSS_SWITCH_XGMAC0 + + (uniphy_index * NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION), reg_value); + +} + +void ppe_xgmac_10g_r_speed_set(uint32_t uniphy_index) +{ + uint32_t reg_value = 0; + + ipq807x_ppe_reg_read(PPE_SWITCH_NSS_SWITCH_XGMAC0 + + (uniphy_index * NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION), ®_value); + + reg_value |=JD; + ipq807x_ppe_reg_write(PPE_SWITCH_NSS_SWITCH_XGMAC0 + + (uniphy_index * NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION), reg_value); + +} + +void ppe_port_txmac_status_set(uint32_t uniphy_index) +{ + uint32_t reg_value = 0; + + ipq807x_ppe_reg_read(PPE_SWITCH_NSS_SWITCH_XGMAC0 + + (uniphy_index * NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION), ®_value); + + reg_value |=TE; + ipq807x_ppe_reg_write(PPE_SWITCH_NSS_SWITCH_XGMAC0 + + (uniphy_index * NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION), reg_value); + +} + +void ppe_port_rxmac_status_set(uint32_t uniphy_index) +{ + uint32_t reg_value = 0; + + ipq807x_ppe_reg_read(PPE_SWITCH_NSS_SWITCH_XGMAC0 + + MAC_RX_CONFIGURATION_ADDRESS + + (uniphy_index * NSS_SWITCH_XGMAC_MAC_RX_CONFIGURATION), ®_value); + + reg_value |= 0x5ee00c0; + reg_value |=RE; + reg_value |=ACS; + reg_value |=CST; + ipq807x_ppe_reg_write(PPE_SWITCH_NSS_SWITCH_XGMAC0 + + MAC_RX_CONFIGURATION_ADDRESS + + (uniphy_index * NSS_SWITCH_XGMAC_MAC_RX_CONFIGURATION), reg_value); + +} + +void ppe_mac_packet_filter_set(uint32_t uniphy_index) +{ + ipq807x_ppe_reg_write(PPE_SWITCH_NSS_SWITCH_XGMAC0 + + MAC_PACKET_FILTER_ADDRESS + + (uniphy_index * MAC_PACKET_FILTER_INC), 0x81); +} + +void ipq807x_10g_r_speed_set(int port, int status) +{ + uint32_t uniphy_index; + + /* Setting the speed only for PORT5 and PORT6 */ + if (port == (PORT5 - PPE_UNIPHY_INSTANCE1)) + uniphy_index = PPE_UNIPHY_INSTANCE1; + else if (port == (PORT6 - PPE_UNIPHY_INSTANCE1)) + uniphy_index = PPE_UNIPHY_INSTANCE2; + else + return; + + ppe_xgmac_10g_r_speed_set(uniphy_index - 1); + ppe_port_bridge_txmac_set(port + 1, status); + ppe_port_txmac_status_set(uniphy_index - 1); + ppe_port_rxmac_status_set(uniphy_index - 1); + ppe_mac_packet_filter_set(uniphy_index - 1); +} + +void ipq807x_uxsgmii_speed_set(int port, int speed, int duplex, + int status) +{ + uint32_t uniphy_index; + + /* Setting the speed only for PORT5 and PORT6 */ + if (port == (PORT5 - PPE_UNIPHY_INSTANCE1)) + uniphy_index = PPE_UNIPHY_INSTANCE1; + else if (port == (PORT6 - PPE_UNIPHY_INSTANCE1)) + uniphy_index = PPE_UNIPHY_INSTANCE2; + else + return; + + ppe_uniphy_usxgmii_autoneg_completed(uniphy_index); + ppe_uniphy_usxgmii_speed_set(uniphy_index, speed); + ppe_xgmac_speed_set(uniphy_index - 1, speed); + ppe_uniphy_usxgmii_duplex_set(uniphy_index, duplex); + ppe_uniphy_usxgmii_port_reset(uniphy_index); + ppe_port_bridge_txmac_set(port + 1, status); + ppe_port_txmac_status_set(uniphy_index - 1); + ppe_port_rxmac_status_set(uniphy_index - 1); + ppe_mac_packet_filter_set(uniphy_index - 1); +} +/* + * ipq807x_ppe_flow_port_map_tbl_port_num_set() + */ +static void ipq807x_ppe_flow_port_map_tbl_port_num_set(int queue, int port) +{ + ipq807x_ppe_reg_write(IPQ807X_PPE_L0_FLOW_PORT_MAP_TBL + + queue * IPQ807X_PPE_L0_FLOW_PORT_MAP_TBL_INC, port); + ipq807x_ppe_reg_write(IPQ807X_PPE_L1_FLOW_PORT_MAP_TBL + + port * IPQ807X_PPE_L1_FLOW_PORT_MAP_TBL_INC, port); +} + +/* + * ipq807x_ppe_flow_map_tbl_set() + */ +static void ipq807x_ppe_flow_map_tbl_set(int queue, int port) +{ + uint32_t val = port | 0x401000; /* c_drr_wt = 1, e_drr_wt = 1 */ + ipq807x_ppe_reg_write(IPQ807X_PPE_L0_FLOW_MAP_TBL + queue * IPQ807X_PPE_L0_FLOW_MAP_TBL_INC, + val); + + val = port | 0x100400; /* c_drr_wt = 1, e_drr_wt = 1 */ + ipq807x_ppe_reg_write(IPQ807X_PPE_L1_FLOW_MAP_TBL + port * IPQ807X_PPE_L1_FLOW_MAP_TBL_INC, + val); +} + +/* + * ipq807x_ppe_tdm_configuration + */ +static void ipq807x_ppe_tdm_configuration(void) +{ + int i = 0; + + /* + * TDM is configured with instructions for each tick + * Port/action are configured as given below + * + * 0x5:0x5 TDM_CFG_VALID 0:idle tick + * 0x4:0x4 TDM_CFG_DIR 0:ingress wr + * 1:egress rd + * 0x3:0x0 TDM_CFG_PORT_NUM 0:DMA + * 1~4:Ethernet 1G + * 5~6:Ethernet 5G + * 7~8:Security0/1 + */ + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_INGRESS | + IPQ807X_PPE_PORT_XGMAC1); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_EGRESS | + IPQ807X_PPE_PORT_XGMAC1); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_INGRESS | + IPQ807X_PPE_PORT_EDMA); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_EGRESS | + IPQ807X_PPE_PORT_EDMA); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_INGRESS | + IPQ807X_PPE_PORT_XGMAC2); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_EGRESS | + IPQ807X_PPE_PORT_XGMAC2); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_INGRESS | + IPQ807X_PPE_PORT_QCOM1); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_EGRESS | + IPQ807X_PPE_PORT_EDMA); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_INGRESS | + IPQ807X_PPE_PORT_CRYPTO1); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_EGRESS | + IPQ807X_PPE_PORT_CRYPTO1); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_INGRESS | + IPQ807X_PPE_PORT_XGMAC1); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_EGRESS | + IPQ807X_PPE_PORT_XGMAC1); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_INGRESS | + IPQ807X_PPE_PORT_EDMA); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_EGRESS | + IPQ807X_PPE_PORT_EDMA); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_INGRESS | + IPQ807X_PPE_PORT_XGMAC2); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_EGRESS | + IPQ807X_PPE_PORT_XGMAC2); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_INGRESS | + IPQ807X_PPE_PORT_EDMA); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_EGRESS | + IPQ807X_PPE_PORT_QCOM3); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_INGRESS | + IPQ807X_PPE_PORT_CRYPTO1); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_EGRESS | + IPQ807X_PPE_PORT_CRYPTO1); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_INGRESS | + IPQ807X_PPE_PORT_XGMAC1); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_EGRESS | + IPQ807X_PPE_PORT_XGMAC1); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_INGRESS | + IPQ807X_PPE_PORT_EDMA); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_EGRESS | + IPQ807X_PPE_PORT_EDMA); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_INGRESS | + IPQ807X_PPE_PORT_XGMAC2); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_EGRESS | + IPQ807X_PPE_PORT_XGMAC2); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_INGRESS | + IPQ807X_PPE_PORT_EDMA); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_EGRESS | + IPQ807X_PPE_PORT_EDMA); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_INGRESS | + IPQ807X_PPE_PORT_CRYPTO1); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_EGRESS | + IPQ807X_PPE_PORT_CRYPTO1); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_INGRESS | + IPQ807X_PPE_PORT_XGMAC1); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_EGRESS | + IPQ807X_PPE_PORT_XGMAC1); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_INGRESS | + IPQ807X_PPE_PORT_EDMA); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_EGRESS | + IPQ807X_PPE_PORT_EDMA); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_INGRESS | + IPQ807X_PPE_PORT_XGMAC2); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_EGRESS | + IPQ807X_PPE_PORT_XGMAC2); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_INGRESS | + IPQ807X_PPE_PORT_QCOM2); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_EGRESS | + IPQ807X_PPE_PORT_EDMA); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_INGRESS | + IPQ807X_PPE_PORT_CRYPTO1); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_EGRESS | + IPQ807X_PPE_PORT_CRYPTO1); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_INGRESS | + IPQ807X_PPE_PORT_XGMAC1); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_EGRESS | + IPQ807X_PPE_PORT_XGMAC1); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_INGRESS | + IPQ807X_PPE_PORT_EDMA); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_EGRESS | + IPQ807X_PPE_PORT_QCOM4); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_INGRESS | + IPQ807X_PPE_PORT_XGMAC2); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_EGRESS | + IPQ807X_PPE_PORT_XGMAC2); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_INGRESS | + IPQ807X_PPE_PORT_EDMA); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_EGRESS | + IPQ807X_PPE_PORT_EDMA); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_INGRESS | + IPQ807X_PPE_PORT_CRYPTO1); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_EGRESS | + IPQ807X_PPE_PORT_CRYPTO1); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_INGRESS | + IPQ807X_PPE_PORT_XGMAC1); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_EGRESS | + IPQ807X_PPE_PORT_XGMAC1); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_INGRESS | + IPQ807X_PPE_PORT_EDMA); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID + | IPQ807X_PPE_TDM_CFG_DIR_EGRESS + | IPQ807X_PPE_PORT_EDMA); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_INGRESS | + IPQ807X_PPE_PORT_XGMAC2); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_EGRESS | + IPQ807X_PPE_PORT_XGMAC2); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_INGRESS | + IPQ807X_PPE_PORT_EDMA); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_EGRESS | + IPQ807X_PPE_PORT_QCOM1); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_INGRESS | + IPQ807X_PPE_PORT_CRYPTO1); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_INGRESS | + IPQ807X_PPE_PORT_XGMAC1); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_EGRESS | + IPQ807X_PPE_PORT_XGMAC1); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_INGRESS | + IPQ807X_PPE_PORT_EDMA); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_EGRESS | + IPQ807X_PPE_PORT_EDMA); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_INGRESS | + IPQ807X_PPE_PORT_XGMAC2); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_EGRESS | + IPQ807X_PPE_PORT_XGMAC2); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_INGRESS | + IPQ807X_PPE_PORT_QCOM3); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_EGRESS | + IPQ807X_PPE_PORT_EDMA); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_INGRESS | + IPQ807X_PPE_PORT_CRYPTO1); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_EGRESS | + IPQ807X_PPE_PORT_CRYPTO1); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_INGRESS | + IPQ807X_PPE_PORT_XGMAC1); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_EGRESS | + IPQ807X_PPE_PORT_XGMAC1); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_INGRESS | + IPQ807X_PPE_PORT_EDMA); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_EGRESS | + IPQ807X_PPE_PORT_EDMA); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_INGRESS | + IPQ807X_PPE_PORT_XGMAC2); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_EGRESS | + IPQ807X_PPE_PORT_XGMAC2); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_INGRESS | + IPQ807X_PPE_PORT_EDMA); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_EGRESS | + IPQ807X_PPE_PORT_EDMA); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_EGRESS | + IPQ807X_PPE_PORT_EDMA); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_INGRESS | + IPQ807X_PPE_PORT_CRYPTO1); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_EGRESS | + IPQ807X_PPE_PORT_CRYPTO1); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_INGRESS | + IPQ807X_PPE_PORT_XGMAC1); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_EGRESS | + IPQ807X_PPE_PORT_XGMAC1); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_INGRESS | + IPQ807X_PPE_PORT_EDMA); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_EGRESS | + IPQ807X_PPE_PORT_EDMA); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_INGRESS | + IPQ807X_PPE_PORT_XGMAC2); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_EGRESS | + IPQ807X_PPE_PORT_XGMAC2); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_INGRESS | + IPQ807X_PPE_PORT_EDMA); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_EGRESS | + IPQ807X_PPE_PORT_QCOM2); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_INGRESS | + IPQ807X_PPE_PORT_CRYPTO1); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_EGRESS | + IPQ807X_PPE_PORT_CRYPTO1); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_INGRESS | + IPQ807X_PPE_PORT_XGMAC1); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_EGRESS | + IPQ807X_PPE_PORT_XGMAC1); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_INGRESS | + IPQ807X_PPE_PORT_QCOM4); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_EGRESS | + IPQ807X_PPE_PORT_EDMA); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_INGRESS | + IPQ807X_PPE_PORT_XGMAC2); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_EGRESS | + IPQ807X_PPE_PORT_XGMAC2); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_INGRESS | + IPQ807X_PPE_PORT_EDMA); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_EGRESS | + IPQ807X_PPE_PORT_EDMA); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_INGRESS | + IPQ807X_PPE_PORT_CRYPTO1); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), + IPQ807X_PPE_TDM_CFG_VALID | + IPQ807X_PPE_TDM_CFG_DIR_EGRESS | + IPQ807X_PPE_PORT_CRYPTO1); + + /* Set TDM Depth to 100 entries */ + ipq807x_ppe_reg_write(IPQ807X_PPE_TDM_CFG_DEPTH_OFFSET, IPQ807X_PPE_TDM_CFG_DEPTH_VAL); +} + +/* + * ipq807x_ppe_sched_configuration + */ +static void ipq807x_ppe_sched_configuration(void) +{ + int i = 0; + + /* + * PSCH_TDM_CFG_TBL_DES_PORT : determine which egress port traffic + * will be selected and transmitted out + * PSCH_TDM_CFG_TBL_ENS_PORT : determine which port’s queue need + * to be linked to scheduler at the current tick + * PSCH_TDM_CFG_TBL_ENS_PORT_BITMAP : determine port bitmap + * for source of queue + * + * 0xf:0x8 PSCH_TDM_CFG_TBL_ENS_PORT_BITMAP 1110_1110 + * (Port:765-432) + * + * 0x7:0x4 PSCH_TDM_CFG_TBL_ENS_PORT 0:DMA + * 1~4:Ethernet 1G + * 5~6:Ethernet 5G + * 7~8:Security0/1 + * + * 0x3:0x0 PSCH_TDM_CFG_TBL_DES_PORT 0:DMA + * 1~4:Ethernet 1G + * 5~6:Ethernet 5G + * 7~8:Security0/1 + * + * For eg, 0xee60 =((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_XGMAC2_BITPOS | + * IPQ807X_PPE_PORT_XGMAC1_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS | + * IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) | + * IPQ807X_PPE_PORT_XGMAC2 | IPQ807X_PPE_PORT_EDMA); + */ + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_XGMAC2_BITPOS | + IPQ807X_PPE_PORT_XGMAC1_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS | + IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ807X_PPE_PORT_XGMAC2 << 4) | IPQ807X_PPE_PORT_EDMA); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_XGMAC2_BITPOS | + IPQ807X_PPE_PORT_QCOM3_BITPOS | IPQ807X_PPE_PORT_QCOM2_BITPOS | + IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ807X_PPE_PORT_QCOM4 << 4) | IPQ807X_PPE_PORT_XGMAC1); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_QCOM4_BITPOS | + IPQ807X_PPE_PORT_QCOM3_BITPOS | IPQ807X_PPE_PORT_QCOM2_BITPOS | + IPQ807X_PPE_PORT_QCOM1_BITPOS | IPQ807X_PPE_PORT_EDMA_BITPOS) << 8) | + (IPQ807X_PPE_PORT_EDMA << 4) | IPQ807X_PPE_PORT_XGMAC2); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_XGMAC1_BITPOS | + IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS | + IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ807X_PPE_PORT_XGMAC1 << 4) | IPQ807X_PPE_PORT_EDMA); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ807X_PPE_PORT_XGMAC2_BITPOS | IPQ807X_PPE_PORT_XGMAC1_BITPOS | + IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS | + IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ807X_PPE_PORT_XGMAC2 << 4) | IPQ807X_PPE_PORT_CRYPTO1); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ807X_PPE_PORT_EDMA_BITPOS | IPQ807X_PPE_PORT_XGMAC2_BITPOS | + IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS | + IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ807X_PPE_PORT_EDMA << 4) | IPQ807X_PPE_PORT_XGMAC1); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_EDMA_BITPOS | + IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS | + IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ807X_PPE_PORT_CRYPTO1 << 4) | IPQ807X_PPE_PORT_XGMAC2); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_XGMAC1_BITPOS | + IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS | + IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ807X_PPE_PORT_XGMAC1 << 4) | IPQ807X_PPE_PORT_EDMA); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_XGMAC1_BITPOS | + IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS | + IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_XGMAC2_BITPOS) << 8) | + (IPQ807X_PPE_PORT_XGMAC2 << 4) | IPQ807X_PPE_PORT_QCOM1); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_XGMAC2_BITPOS | + IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS | + IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_EDMA_BITPOS) << 8) | + (IPQ807X_PPE_PORT_EDMA << 4) | IPQ807X_PPE_PORT_XGMAC1); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_XGMAC2_BITPOS | + IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS | + IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ807X_PPE_PORT_QCOM1 << 4) | IPQ807X_PPE_PORT_EDMA); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_XGMAC1_BITPOS | + IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS | + IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ807X_PPE_PORT_XGMAC1 << 4) | IPQ807X_PPE_PORT_XGMAC2); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_XGMAC1_BITPOS | + IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS | + IPQ807X_PPE_PORT_EDMA_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ807X_PPE_PORT_EDMA << 4) | IPQ807X_PPE_PORT_QCOM2); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_XGMAC2_BITPOS | + IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS | + IPQ807X_PPE_PORT_EDMA_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ807X_PPE_PORT_XGMAC2 << 4) | IPQ807X_PPE_PORT_XGMAC1); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_XGMAC2_BITPOS | + IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS | + IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ807X_PPE_PORT_QCOM2 << 4) | IPQ807X_PPE_PORT_EDMA); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_XGMAC1_BITPOS | + IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS | + IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ807X_PPE_PORT_XGMAC1 << 4) | IPQ807X_PPE_PORT_XGMAC2); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ807X_PPE_PORT_XGMAC1_BITPOS | IPQ807X_PPE_PORT_EDMA_BITPOS | + IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS | + IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ807X_PPE_PORT_EDMA << 4) | IPQ807X_PPE_PORT_CRYPTO1); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ807X_PPE_PORT_XGMAC2_BITPOS | IPQ807X_PPE_PORT_XGMAC1_BITPOS | + IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS | + IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ807X_PPE_PORT_XGMAC2 << 4) | IPQ807X_PPE_PORT_EDMA); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_XGMAC2_BITPOS | + IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS | + IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ807X_PPE_PORT_CRYPTO1 << 4) | IPQ807X_PPE_PORT_XGMAC1); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_EDMA_BITPOS | + IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS | + IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ807X_PPE_PORT_EDMA << 4) | IPQ807X_PPE_PORT_XGMAC2); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_XGMAC1_BITPOS | + IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_EDMA_BITPOS | + IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ807X_PPE_PORT_XGMAC1 << 4) | IPQ807X_PPE_PORT_QCOM3); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_XGMAC2_BITPOS | + IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_XGMAC1_BITPOS | + IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ807X_PPE_PORT_XGMAC2 << 4) | IPQ807X_PPE_PORT_EDMA); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_XGMAC2_BITPOS | + IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS | + IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ807X_PPE_PORT_QCOM3 << 4) | IPQ807X_PPE_PORT_XGMAC1); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_EDMA_BITPOS | + IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS | + IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ807X_PPE_PORT_EDMA << 4) | IPQ807X_PPE_PORT_XGMAC2); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_XGMAC1_BITPOS | + IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS | + IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ807X_PPE_PORT_XGMAC1 << 4) | IPQ807X_PPE_PORT_EDMA); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_XGMAC2_BITPOS | + IPQ807X_PPE_PORT_XGMAC1_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS | + IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ807X_PPE_PORT_XGMAC2 << 4) | IPQ807X_PPE_PORT_QCOM4); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_EDMA_BITPOS | + IPQ807X_PPE_PORT_XGMAC2_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS | + IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ807X_PPE_PORT_EDMA << 4) | IPQ807X_PPE_PORT_XGMAC1); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_EDMA_BITPOS | + IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS | + IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ807X_PPE_PORT_QCOM4 << 4) | IPQ807X_PPE_PORT_XGMAC2); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_XGMAC1_BITPOS | + IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS | + IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ807X_PPE_PORT_XGMAC1 << 4) | IPQ807X_PPE_PORT_EDMA); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ807X_PPE_PORT_XGMAC2_BITPOS | IPQ807X_PPE_PORT_XGMAC1_BITPOS | + IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS | + IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ807X_PPE_PORT_XGMAC2 << 4) | IPQ807X_PPE_PORT_CRYPTO1); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ807X_PPE_PORT_EDMA_BITPOS | IPQ807X_PPE_PORT_XGMAC2_BITPOS | + IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS | + IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ807X_PPE_PORT_EDMA << 4) | IPQ807X_PPE_PORT_XGMAC1); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_XGMAC2_BITPOS | + IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS | + IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ807X_PPE_PORT_CRYPTO1 << 4) | IPQ807X_PPE_PORT_EDMA); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_XGMAC1_BITPOS | + IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS | + IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ807X_PPE_PORT_XGMAC1 << 4) | IPQ807X_PPE_PORT_XGMAC2); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_XGMAC1_BITPOS | + IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS | + IPQ807X_PPE_PORT_EDMA_BITPOS | IPQ807X_PPE_PORT_QCOM2_BITPOS) << 8) | + (IPQ807X_PPE_PORT_EDMA << 4) | IPQ807X_PPE_PORT_QCOM1); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_XGMAC2_BITPOS | + IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS | + IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_EDMA_BITPOS) << 8) | + (IPQ807X_PPE_PORT_XGMAC2 << 4) | IPQ807X_PPE_PORT_XGMAC1); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_XGMAC2_BITPOS | + IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS | + IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ807X_PPE_PORT_QCOM1 << 4) | IPQ807X_PPE_PORT_EDMA); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_XGMAC1_BITPOS | + IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS | + IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ807X_PPE_PORT_XGMAC1 << 4) | IPQ807X_PPE_PORT_XGMAC2); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_XGMAC1_BITPOS | + IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS | + IPQ807X_PPE_PORT_EDMA_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ807X_PPE_PORT_EDMA << 4) | IPQ807X_PPE_PORT_QCOM2); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_XGMAC1_BITPOS | + IPQ807X_PPE_PORT_XGMAC2_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS | + IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ807X_PPE_PORT_XGMAC2 << 4) | IPQ807X_PPE_PORT_EDMA); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_XGMAC2_BITPOS | + IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS | + IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ807X_PPE_PORT_QCOM2 << 4) | IPQ807X_PPE_PORT_XGMAC1); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_EDMA_BITPOS | + IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS | + IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ807X_PPE_PORT_EDMA << 4) | IPQ807X_PPE_PORT_XGMAC2); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ807X_PPE_PORT_XGMAC1_BITPOS | IPQ807X_PPE_PORT_EDMA_BITPOS | + IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS | + IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ807X_PPE_PORT_XGMAC1 << 4) | IPQ807X_PPE_PORT_CRYPTO1); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ807X_PPE_PORT_XGMAC2_BITPOS | IPQ807X_PPE_PORT_XGMAC1_BITPOS | + IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS | + IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ807X_PPE_PORT_XGMAC2 << 4) | IPQ807X_PPE_PORT_EDMA); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_XGMAC2_BITPOS | + IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS | + IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ807X_PPE_PORT_CRYPTO1 << 4) | IPQ807X_PPE_PORT_XGMAC1); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_EDMA_BITPOS | + IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS | + IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ807X_PPE_PORT_EDMA << 4) | IPQ807X_PPE_PORT_XGMAC2); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_XGMAC1_BITPOS | + IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_EDMA_BITPOS | + IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ807X_PPE_PORT_XGMAC1 << 4) | IPQ807X_PPE_PORT_QCOM3); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_XGMAC2_BITPOS | + IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_XGMAC1_BITPOS | + IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ807X_PPE_PORT_XGMAC2 << 4) | IPQ807X_PPE_PORT_EDMA); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_XGMAC2_BITPOS | + IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS | + IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ807X_PPE_PORT_QCOM3 << 4) | IPQ807X_PPE_PORT_XGMAC1); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_EDMA_BITPOS | + IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS | + IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ807X_PPE_PORT_EDMA << 4) | IPQ807X_PPE_PORT_XGMAC2); + ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), + ((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_XGMAC1_BITPOS | + IPQ807X_PPE_PORT_EDMA_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS | + IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) | + (IPQ807X_PPE_PORT_XGMAC1 << 4) | IPQ807X_PPE_PORT_QCOM4); + + /* Set Sched Depth to 50 entries */ + ipq807x_ppe_reg_write(IPQ807X_PPE_TDM_SCHED_DEPTH_OFFSET, IPQ807X_PPE_TDM_SCHED_DEPTH_VAL); +} + +/* + * ipq807x_ppe_c_sp_cfg_tbl_drr_id_set + */ +static void ipq807x_ppe_c_sp_cfg_tbl_drr_id_set(int id) +{ + ipq807x_ppe_reg_write(IPQ807X_PPE_L0_C_SP_CFG_TBL + (id * 0x80), id * 2); + ipq807x_ppe_reg_write(IPQ807X_PPE_L1_C_SP_CFG_TBL + (id * 0x80), id * 2); +} + +/* + * ipq807x_ppe_e_sp_cfg_tbl_drr_id_set + */ +static void ipq807x_ppe_e_sp_cfg_tbl_drr_id_set(int id) +{ + ipq807x_ppe_reg_write(IPQ807X_PPE_L0_E_SP_CFG_TBL + (id * 0x80), id * 2 + 1); + ipq807x_ppe_reg_write(IPQ807X_PPE_L1_E_SP_CFG_TBL + (id * 0x80), id * 2 + 1); +} + +static void ppe_port_mux_set(int port_id, int port_type, int mode) +{ + union port_mux_ctrl_u port_mux_ctrl; + + ipq807x_ppe_reg_read(IPQ807X_PORT_MUX_CTRL, &(port_mux_ctrl.val)); + port_mux_ctrl.bf.port4_pcs_sel = PORT4_PCS_SEL_GMII_FROM_PCS0; + if (port_id == PORT5) { + if (port_type == PORT_GMAC_TYPE) { + if (mode == PORT_WRAPPER_SGMII_PLUS || mode == PORT_WRAPPER_SGMII0_RGMII4) + port_mux_ctrl.bf.port5_pcs_sel = PORT5_PCS_SEL_GMII_FROM_PCS1; + else + port_mux_ctrl.bf.port5_pcs_sel = PORT5_PCS_SEL_GMII_FROM_PCS0; + port_mux_ctrl.bf.port5_gmac_sel = PORT5_GMAC_SEL_GMAC; + } else if (port_type == PORT_XGMAC_TYPE) { + port_mux_ctrl.bf.port5_pcs_sel = PORT5_PCS_SEL_GMII_FROM_PCS1; + port_mux_ctrl.bf.port5_gmac_sel = PORT5_GMAC_SEL_XGMAC; + } + } else if (port_id == PORT6) { + if (port_type == PORT_GMAC_TYPE) { + port_mux_ctrl.bf.port6_pcs_sel = PORT6_PCS_SEL_GMII_FROM_PCS2; + port_mux_ctrl.bf.port6_gmac_sel = PORT6_GMAC_SEL_GMAC; + } else if (port_type == PORT_XGMAC_TYPE) { + port_mux_ctrl.bf.port6_pcs_sel = PORT6_PCS_SEL_GMII_FROM_PCS2; + port_mux_ctrl.bf.port6_gmac_sel = PORT6_GMAC_SEL_XGMAC; + } + } else + return; + + ipq807x_ppe_reg_write(IPQ807X_PORT_MUX_CTRL, port_mux_ctrl.val); +} + +static void ppe_port_mux_mac_type_set(int port_id, int mode) +{ + uint32_t port_type; + + switch(mode) + { + case PORT_WRAPPER_SGMII0_RGMII4: + port_type = PORT_GMAC_TYPE; + break; + case PORT_WRAPPER_SGMII_PLUS: + port_type = PORT_GMAC_TYPE; + break; + case PORT_WRAPPER_USXGMII: + port_type = PORT_XGMAC_TYPE; + break; + case PORT_WRAPPER_10GBASE_R: + port_type = PORT_XGMAC_TYPE; + break; + default: + return; + } + ppe_port_mux_set(port_id, port_type, mode); +} + + + +void ipq807x_ppe_interface_mode_init(void) +{ + uint32_t mode0, mode1, mode2; + int node; + + node = fdt_path_offset(gd->fdt_blob, "/ess-switch"); + if (node < 0) { + printf("Error: ess-switch not specified in dts"); + return; + } + + mode0 = fdtdec_get_uint(gd->fdt_blob, node, "switch_mac_mode", -1); + if (mode0 < 0) { + printf("Error: switch_mac_mode not specified in dts"); + return; + } + + mode1 = fdtdec_get_uint(gd->fdt_blob, node, "switch_mac_mode1", -1); + if (mode1 < 0) { + printf("Error: switch_mac_mode1 not specified in dts"); + return; + } + mode2 = fdtdec_get_uint(gd->fdt_blob, node, "switch_mac_mode2", -1); + if (mode2 < 0) { + printf("Error: switch_mac_mode2 not specified in dts"); + return; + } + + ppe_uniphy_mode_set(PPE_UNIPHY_INSTANCE0, mode0); + ppe_uniphy_mode_set(PPE_UNIPHY_INSTANCE1, mode1); + ppe_uniphy_mode_set(PPE_UNIPHY_INSTANCE2, mode2); + + /* Port 1-4 are used mac type as GMAC by default but Port5 and Port6 + * can be used as GMAC or XGMAC */ + ppe_port_mux_mac_type_set(PORT5, mode1); + ppe_port_mux_mac_type_set(PORT6, mode2); +} + +/* + * ipq807x_ppe_provision_init() + */ +void ipq807x_ppe_provision_init(void) +{ + int i; + uint32_t queue; + + /* Port4 Port5, Port6 port mux configuration, all GMAC */ + writel(0x3b, 0x3a000010); + + /* tdm/sched configuration */ + ipq807x_ppe_tdm_configuration(); + ipq807x_ppe_sched_configuration(); + + ipq807x_gmac_enable(); + + /* disable clock gating */ + ipq807x_ppe_reg_write(0x000008, 0x0); + + /* flow ctrl disable */ + ipq807x_ppe_reg_write(0x200368, 0xc88); + +#ifdef CONFIG_IPQ807X_BRIDGED_MODE + /* Add CPU port 0 to VSI 2 */ + ipq807x_ppe_vp_port_tbl_set(0, 2); + + /* Add port 1 - 4 to VSI 2 */ + ipq807x_ppe_vp_port_tbl_set(1, 2); + ipq807x_ppe_vp_port_tbl_set(2, 2); + ipq807x_ppe_vp_port_tbl_set(3, 2); + ipq807x_ppe_vp_port_tbl_set(4, 2); + ipq807x_ppe_vp_port_tbl_set(5, 2); + ipq807x_ppe_vp_port_tbl_set(6, 2); + +#else + ipq807x_ppe_vp_port_tbl_set(1, 2); + ipq807x_ppe_vp_port_tbl_set(2, 3); + ipq807x_ppe_vp_port_tbl_set(3, 4); + ipq807x_ppe_vp_port_tbl_set(4, 5); +#endif + + /* Unicast priority map */ + ipq807x_ppe_reg_write(IPQ807X_PPE_QM_UPM_TBL, 0); + + /* Port0 - 7 unicast queue settings */ + for (i = 0; i < 8; i++) { + if (i == 0) + queue = 0; + else + queue = ((i * 0x10) + 0x70); + + ipq807x_ppe_ucast_queue_map_tbl_queue_id_set(queue, i); + ipq807x_ppe_flow_port_map_tbl_port_num_set(queue, i); + ipq807x_ppe_flow_map_tbl_set(queue, i); + ipq807x_ppe_c_sp_cfg_tbl_drr_id_set(i); + ipq807x_ppe_e_sp_cfg_tbl_drr_id_set(i); + } + + /* Port0 multicast queue */ + ipq807x_ppe_reg_write(0x409000, 0x00000000); + ipq807x_ppe_reg_write(0x403000, 0x00401000); + + /* Port1 - 7 multicast queue */ + for (i = 1; i < 8; i++) { + ipq807x_ppe_reg_write(0x409100 + ((i - 1) * 0x40), i); + ipq807x_ppe_reg_write(0x403100 + ((i - 1) * 0x40), 0x401000 | i); + } + + /* + * Port0 - Port7 learn enable and isolation port bitmap and TX_EN + * Here please pay attention on bit16 (TX_EN) is not set on port7 + */ + for (i = 0; i < 7; i++) + ipq807x_ppe_reg_write(IPQ807X_PPE_PORT_BRIDGE_CTRL_OFFSET + (i * 4), + IPQ807X_PPE_PORT_BRIDGE_CTRL_PROMISC_EN | + IPQ807X_PPE_PORT_BRIDGE_CTRL_TXMAC_EN | + IPQ807X_PPE_PORT_BRIDGE_CTRL_PORT_ISOLATION_BMP | + IPQ807X_PPE_PORT_BRIDGE_CTRL_STATION_LRN_EN | + IPQ807X_PPE_PORT_BRIDGE_CTRL_NEW_ADDR_LRN_EN); + + ipq807x_ppe_reg_write(IPQ807X_PPE_PORT_BRIDGE_CTRL_OFFSET + (7 * 4), + IPQ807X_PPE_PORT_BRIDGE_CTRL_PROMISC_EN | + IPQ807X_PPE_PORT_BRIDGE_CTRL_PORT_ISOLATION_BMP | + IPQ807X_PPE_PORT_BRIDGE_CTRL_STATION_LRN_EN | + IPQ807X_PPE_PORT_BRIDGE_CTRL_NEW_ADDR_LRN_EN); + + /* Global learning */ + ipq807x_ppe_reg_write(0x060038, 0xc0); + +#ifdef CONFIG_IPQ807X_BRIDGED_MODE + ipq807x_vsi_setup(2, 0x7f); +#else + ipq807x_vsi_setup(2, 0x03); + ipq807x_vsi_setup(3, 0x05); + ipq807x_vsi_setup(4, 0x09); + ipq807x_vsi_setup(5, 0x11); +#endif + + /* Port 0-7 STP */ + for (i = 0; i < 8; i++) + ipq807x_ppe_reg_write(IPQ807X_PPE_STP_BASE + (0x4 * i), 0x3); + + ipq807x_ppe_interface_mode_init(); + /* Port 0-5 enable */ + for (i = 0; i < 6; i++) { + ipq807x_gmac_port_disable(i); + ppe_port_bridge_txmac_set(i + 1, 1); + } + + /* Allowing DHCP packets */ + ipq807x_ppe_acl_set(0, ADPT_ACL_HPPE_IPV4_DIP_RULE, UDP_PKT, 67, 0xffff, 0, 0); + ipq807x_ppe_acl_set(1, ADPT_ACL_HPPE_IPV4_DIP_RULE, UDP_PKT, 68, 0xffff, 0, 0); + /* Dropping all the UDP packets */ + ipq807x_ppe_acl_set(2, ADPT_ACL_HPPE_IPV4_DIP_RULE, UDP_PKT, 0, 0, 0, 1); +} diff --git a/sources/uboot-be550/drivers/net/ipq807x/ipq807x_ppe.h b/sources/uboot-be550/drivers/net/ipq807x/ipq807x_ppe.h new file mode 100644 index 00000000..c5febe46 --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq807x/ipq807x_ppe.h @@ -0,0 +1,251 @@ +/* + ************************************************************************** + * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT + * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + ************************************************************************** + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define GCC_NSS_PORT1_RX_CMD_RCGR 0x01868020 +#define GCC_NSS_PORT1_RX_CFG_RCGR 0x01868024 +#define GCC_NSS_PORT1_RX_MISC 0x01868400 + +#define IPQ807X_PPE_BASE_ADDR 0x3a000000 +#define IPQ807X_PPE_REG_SIZE 0x1000000 + +#define PORT5 5 +#define PORT6 6 +#define PORT_GMAC_TYPE 1 +#define PORT_XGMAC_TYPE 2 +struct port_mux_ctrl { + uint32_t port4_pcs_sel:1; + uint32_t port5_pcs_sel:2; + uint32_t port5_gmac_sel:1; + uint32_t port6_pcs_sel:1; + uint32_t port6_gmac_sel:1; + uint32_t _reserved0:26; +}; +union port_mux_ctrl_u { + uint32_t val; + struct port_mux_ctrl bf; +}; + +enum { + TCP_PKT, + UDP_PKT, +}; + +#define ADPT_ACL_HPPE_IPV4_DIP_RULE 4 +#define MAX_RULE 512 + +struct ipo_rule_reg { + uint32_t rule_field_0:32; + uint32_t rule_field_1:20; + uint32_t fake_mac_header:1; + uint32_t range_en:1; + uint32_t inverse_en:1; + uint32_t rule_type:4; + uint32_t src_type:2; + uint32_t src_0:3; + uint32_t src_1:5; + uint32_t pri:9; + uint32_t res_chain:1; + uint32_t post_routing_en:1; + uint32_t _reserved0:16; +}; + +union ipo_rule_reg_u { + uint32_t val[3]; + struct ipo_rule_reg bf; +}; + +struct ipo_mask_reg { + uint32_t maskfield_0:32; + uint32_t maskfield_1:21; + uint32_t _reserved0:11; +}; + +union ipo_mask_reg_u { + uint32_t val[2]; + struct ipo_mask_reg bf; +}; + +struct ipo_action { + uint32_t dest_info_change_en:1; + uint32_t fwd_cmd:2; + uint32_t _reserved0:29; + uint32_t _reserved1:32; + uint32_t _reserved2:32; + uint32_t _reserved3:32; + uint32_t _reserved4:32; +}; + +union ipo_action_u { + uint32_t val[5]; + struct ipo_action bf; +}; + +#define IPQ807X_PORT_MUX_CTRL 0x10 +#define PORT4_PCS_SEL_GMII_FROM_PCS0 1 +#define PORT4_PCS_SEL_RGMII 0 +#define PORT5_PCS_SEL_RGMII 0 +#define PORT5_PCS_SEL_GMII_FROM_PCS0 1 +#define PORT5_PCS_SEL_GMII_FROM_PCS1 2 +#define PORT5_GMAC_SEL_GMAC 1 +#define PORT5_GMAC_SEL_XGMAC 0 +#define PORT6_PCS_SEL_RGMII 0 +#define PORT6_PCS_SEL_GMII_FROM_PCS2 1 +#define PORT6_GMAC_SEL_GMAC 1 +#define PORT6_GMAC_SEL_XGMAC 0 + +#define PORT_PHY_STATUS_ADDRESS 0x44 +#define PORT_PHY_STATUS_PORT5_1_OFFSET 8 +#define PORT_PHY_STATUS_PORT6_OFFSET 16 + +#define IPQ807X_PPE_IPE_L3_BASE_ADDR 0x200000 +#define IPQ807X_PPE_L3_VP_PORT_TBL_ADDR (IPQ807X_PPE_IPE_L3_BASE_ADDR + 0x1000) +#define IPQ807X_PPE_L3_VP_PORT_TBL_INC 0x10 + +#define IPQ807X_PPE_QUEUE_MANAGER_BASE_ADDR 0x800000 +#define IPQ807X_PPE_UCAST_QUEUE_MAP_TBL_ADDR 0x10000 +#define IPQ807X_PPE_UCAST_QUEUE_MAP_TBL_INC 0x10 +#define IPQ807X_PPE_QM_UQM_TBL (IPQ807X_PPE_QUEUE_MANAGER_BASE_ADDR +\ + IPQ807X_PPE_UCAST_QUEUE_MAP_TBL_ADDR) +#define IPQ807X_PPE_UCAST_PRIORITY_MAP_TBL_ADDR 0x42000 +#define IPQ807X_PPE_QM_UPM_TBL (IPQ807X_PPE_QUEUE_MANAGER_BASE_ADDR +\ + IPQ807X_PPE_UCAST_PRIORITY_MAP_TBL_ADDR) + +#define IPQ807X_PPE_STP_BASE 0x060100 +#define IPQ807X_PPE_MAC_ENABLE 0x001000 +#define IPQ807X_PPE_MAC_SPEED 0x001004 +#define IPQ807X_PPE_MAC_MIB_CTL 0x001034 + +#define IPQ807X_PPE_TRAFFIC_MANAGER_BASE_ADDR 0x400000 + +#define IPQ807X_PPE_L0_FLOW_PORT_MAP_TBL_ADDR 0x8000 +#define IPQ807X_PPE_L0_FLOW_PORT_MAP_TBL_INC 0x10 +#define IPQ807X_PPE_L0_FLOW_PORT_MAP_TBL (IPQ807X_PPE_TRAFFIC_MANAGER_BASE_ADDR +\ + IPQ807X_PPE_L0_FLOW_PORT_MAP_TBL_ADDR) + +#define IPQ807X_PPE_L0_FLOW_MAP_TBL_ADDR 0x2000 +#define IPQ807X_PPE_L0_FLOW_MAP_TBL_INC 0x10 +#define IPQ807X_PPE_L0_FLOW_MAP_TBL (IPQ807X_PPE_TRAFFIC_MANAGER_BASE_ADDR +\ + IPQ807X_PPE_L0_FLOW_MAP_TBL_ADDR) + +#define IPQ807X_PPE_L1_FLOW_PORT_MAP_TBL_ADDR 0x46000 +#define IPQ807X_PPE_L1_FLOW_PORT_MAP_TBL_INC 0x10 +#define IPQ807X_PPE_L1_FLOW_PORT_MAP_TBL (IPQ807X_PPE_TRAFFIC_MANAGER_BASE_ADDR +\ + IPQ807X_PPE_L1_FLOW_PORT_MAP_TBL_ADDR) + +#define IPQ807X_PPE_L1_FLOW_MAP_TBL_ADDR 0x40000 +#define IPQ807X_PPE_L1_FLOW_MAP_TBL_INC 0x10 +#define IPQ807X_PPE_L1_FLOW_MAP_TBL (IPQ807X_PPE_TRAFFIC_MANAGER_BASE_ADDR +\ + IPQ807X_PPE_L1_FLOW_MAP_TBL_ADDR) + +#define IPQ807X_PPE_L0_C_SP_CFG_TBL_ADDR 0x4000 +#define IPQ807X_PPE_L0_C_SP_CFG_TBL (IPQ807X_PPE_TRAFFIC_MANAGER_BASE_ADDR +\ + IPQ807X_PPE_L0_C_SP_CFG_TBL_ADDR) + +#define IPQ807X_PPE_L1_C_SP_CFG_TBL_ADDR 0x42000 +#define IPQ807X_PPE_L1_C_SP_CFG_TBL (IPQ807X_PPE_TRAFFIC_MANAGER_BASE_ADDR +\ + IPQ807X_PPE_L1_C_SP_CFG_TBL_ADDR) + +#define IPQ807X_PPE_L0_E_SP_CFG_TBL_ADDR 0x6000 +#define IPQ807X_PPE_L0_E_SP_CFG_TBL (IPQ807X_PPE_TRAFFIC_MANAGER_BASE_ADDR +\ + IPQ807X_PPE_L0_E_SP_CFG_TBL_ADDR) + +#define IPQ807X_PPE_L1_E_SP_CFG_TBL_ADDR 0x44000 +#define IPQ807X_PPE_L1_E_SP_CFG_TBL (IPQ807X_PPE_TRAFFIC_MANAGER_BASE_ADDR +\ + IPQ807X_PPE_L1_E_SP_CFG_TBL_ADDR) + +#define IPQ807X_PPE_FPGA_GPIO_BASE_ADDR 0x01008000 + +#define IPQ807X_PPE_MAC_PORT_MUX_OFFSET 0x10 +#define IPQ807X_PPE_FPGA_GPIO_OFFSET 0xc000 +#define IPQ807X_PPE_FPGA_SCHED_OFFSET 0x47a000 +#define IPQ807X_PPE_TDM_CFG_DEPTH_OFFSET 0xb000 +#define IPQ807X_PPE_TDM_SCHED_DEPTH_OFFSET 0x400000 +#define IPQ807X_PPE_PORT_BRIDGE_CTRL_OFFSET 0x060300 + +#define IPQ807X_PPE_TDM_CFG_DEPTH_VAL 0x80000064 +#define IPQ807X_PPE_MAC_PORT_MUX_OFFSET_VAL 0x15 +#define IPQ807X_PPE_TDM_SCHED_DEPTH_VAL 0x32 +#define IPQ807X_PPE_TDM_CFG_VALID 0x20 +#define IPQ807X_PPE_TDM_CFG_DIR_INGRESS 0x0 +#define IPQ807X_PPE_TDM_CFG_DIR_EGRESS 0x10 +#define IPQ807X_PPE_PORT_EDMA 0x0 +#define IPQ807X_PPE_PORT_QCOM1 0x1 +#define IPQ807X_PPE_PORT_QCOM2 0x2 +#define IPQ807X_PPE_PORT_QCOM3 0x3 +#define IPQ807X_PPE_PORT_QCOM4 0x4 +#define IPQ807X_PPE_PORT_XGMAC1 0x5 +#define IPQ807X_PPE_PORT_XGMAC2 0x6 +#define IPQ807X_PPE_PORT_CRYPTO1 0x7 +#define IPQ807X_PPE_PORT_BRIDGE_CTRL_PROMISC_EN 0x20000 +#define IPQ807X_PPE_PORT_BRIDGE_CTRL_TXMAC_EN 0x10000 +#define IPQ807X_PPE_PORT_BRIDGE_CTRL_PORT_ISOLATION_BMP 0x7f00 +#define IPQ807X_PPE_PORT_BRIDGE_CTRL_STATION_LRN_EN 0x8 +#define IPQ807X_PPE_PORT_BRIDGE_CTRL_NEW_ADDR_LRN_EN 0x1 + +#define IPQ807X_PPE_PORT_EDMA_BITPOS 0x1 +#define IPQ807X_PPE_PORT_QCOM1_BITPOS (1 << IPQ807X_PPE_PORT_QCOM1) +#define IPQ807X_PPE_PORT_QCOM2_BITPOS (1 << IPQ807X_PPE_PORT_QCOM2) +#define IPQ807X_PPE_PORT_QCOM3_BITPOS (1 << IPQ807X_PPE_PORT_QCOM3) +#define IPQ807X_PPE_PORT_QCOM4_BITPOS (1 << IPQ807X_PPE_PORT_QCOM4) +#define IPQ807X_PPE_PORT_XGMAC1_BITPOS (1 << IPQ807X_PPE_PORT_XGMAC1) +#define IPQ807X_PPE_PORT_XGMAC2_BITPOS (1 << IPQ807X_PPE_PORT_XGMAC2) +#define IPQ807X_PPE_PORT_CRYPTO1_BITPOS (1 << IPQ807X_PPE_PORT_CRYPTO1) + +#define PPE_SWITCH_NSS_SWITCH_XGMAC0 0x3000 +#define NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION 0x4000 +#define USS (1 << 31) +#define SS(i) (i << 29) +#define JD (1 << 16) +#define TE (1 << 0) +#define NSS_SWITCH_XGMAC_MAC_RX_CONFIGURATION 0x4000 +#define MAC_RX_CONFIGURATION_ADDRESS 0x4 +#define RE (1 << 0) +#define ACS (1 << 1) +#define CST (1 << 2) +#define MAC_PACKET_FILTER_INC 0x4000 +#define MAC_PACKET_FILTER_ADDRESS 0x8 + +#define XGMAC_SPEED_SELECT_10000M 0 +#define XGMAC_SPEED_SELECT_5000M 1 +#define XGMAC_SPEED_SELECT_2500M 2 +#define XGMAC_SPEED_SELECT_1000M 3 + +#define IPE_L2_BASE_ADDR 0x060000 +#define PORT_BRIDGE_CTRL_ADDRESS 0x300 +#define PORT_BRIDGE_CTRL_INC 0x4 +#define TX_MAC_EN (1 << 16) + +#define IPO_CSR_BASE_ADDR 0x0b0000 + +#define IPO_RULE_REG_ADDRESS 0x0 +#define IPO_RULE_REG_INC 0x10 + +#define IPO_MASK_REG_ADDRESS 0x2000 +#define IPO_MASK_REG_INC 0x10 + +#define IPO_ACTION_ADDRESS 0x8000 +#define IPO_ACTION_INC 0x20 diff --git a/sources/uboot-be550/drivers/net/ipq807x/ipq807x_uniphy.c b/sources/uboot-be550/drivers/net/ipq807x/ipq807x_uniphy.c new file mode 100644 index 00000000..1a22cf29 --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq807x/ipq807x_uniphy.c @@ -0,0 +1,356 @@ +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "ipq807x_edma.h" +#include "ipq807x_uniphy.h" +#include "ipq_phy.h" + +extern int ipq_mdio_write(int mii_id, + int regnum, u16 value); +extern int ipq_mdio_read(int mii_id, + int regnum, ushort *data); +extern void qca8075_phy_serdes_reset(u32 phy_id); + +void csr1_write(int phy_id, int addr, int value) +{ + int addr_h, addr_l, ahb_h, ahb_l, phy; + phy=phy_id<<(0x10); + addr_h=(addr&0xffffff)>>8; + addr_l=((addr&0xff)<<2)|(0x20<<(0xa)); + ahb_l=(addr_l&0xffff)|(0x7A00000|phy); + ahb_h=(0x7A083FC|phy); + writel(addr_h,ahb_h); + writel(value,ahb_l); +} + +int csr1_read(int phy_id, int addr ) +{ + int addr_h ,addr_l,ahb_h, ahb_l, phy; + phy=phy_id<<(0x10); + addr_h=(addr&0xffffff)>>8; + addr_l=((addr&0xff)<<2)|(0x20<<(0xa)); + ahb_l=(addr_l&0xffff)|(0x7A00000|phy); + ahb_h=(0x7A083FC|phy); + writel(addr_h, ahb_h); + return readl(ahb_l); +} + +static int ppe_uniphy_calibration(uint32_t uniphy_index) +{ + int retries = 100, calibration_done = 0; + uint32_t reg_value = 0; + + while(calibration_done != UNIPHY_CALIBRATION_DONE) { + mdelay(1); + if (retries-- == 0) { + printf("uniphy callibration time out!\n"); + return -1; + } + reg_value = readl(PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC) + + PPE_UNIPHY_OFFSET_CALIB_4); + calibration_done = (reg_value >> 0x7) & 0x1; + } + + return 0; +} + +static void ppe_gcc_uniphy_xpcs_reset(uint32_t uniphy_index, bool enable) +{ + uint32_t reg_value; + + if(enable) + reg_value = GCC_UNIPHY_USXGMII_XPCS_RESET; + else + reg_value = GCC_UNIPHY_USXGMII_XPCS_RELEASE_RESET; + + writel(reg_value, GCC_UNIPHY0_MISC + (uniphy_index * GCC_UNIPHY_REG_INC)); +} + +static void ppe_gcc_uniphy_soft_reset(uint32_t uniphy_index) +{ + uint32_t reg_value; + + reg_value = readl(GCC_UNIPHY0_MISC + (uniphy_index * GCC_UNIPHY_REG_INC)); + if (uniphy_index == PPE_UNIPHY_INSTANCE0) + reg_value |= GCC_UNIPHY_PSGMII_SOFT_RESET; + else + reg_value = GCC_UNIPHY_USXGMII_SOFT_RESET; + + writel(reg_value, GCC_UNIPHY0_MISC + (uniphy_index * GCC_UNIPHY_REG_INC)); + udelay(500); + if (uniphy_index == PPE_UNIPHY_INSTANCE0) + reg_value &= ~GCC_UNIPHY_PSGMII_SOFT_RESET; + else + reg_value = GCC_UNIPHY_USXGMII_XPCS_RESET; + + writel(reg_value, GCC_UNIPHY0_MISC + (uniphy_index * GCC_UNIPHY_REG_INC)); +} + +static void ppe_uniphy_psgmii_mode_set(uint32_t uniphy_index) +{ + ppe_gcc_uniphy_xpcs_reset(uniphy_index, true); + writel(0x220, PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC) + + PPE_UNIPHY_MODE_CONTROL); + ppe_gcc_uniphy_soft_reset(uniphy_index); + ppe_uniphy_calibration(uniphy_index); + qca8075_phy_serdes_reset(0); +} + +static void ppe_uniphy_qsgmii_mode_set(uint32_t uniphy_index) +{ + ppe_gcc_uniphy_xpcs_reset(uniphy_index, true); + writel(0x120, PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC) + + PPE_UNIPHY_MODE_CONTROL); + ppe_gcc_uniphy_soft_reset(uniphy_index); +} + +static void ppe_uniphy_sgmii_mode_set(uint32_t uniphy_index, uint32_t channel) +{ + uint32_t reg_value; + + writel(UNIPHY_MISC2_REG_SGMII_MODE, PPE_UNIPHY_BASE + + (uniphy_index * PPE_UNIPHY_REG_INC) + UNIPHY_MISC2_REG_OFFSET); + writel(UNIPHY_PLL_RESET_REG_VALUE, PPE_UNIPHY_BASE + + (uniphy_index * PPE_UNIPHY_REG_INC) + UNIPHY_PLL_RESET_REG_OFFSET); + udelay(500); + writel(UNIPHY_PLL_RESET_REG_DEFAULT_VALUE, PPE_UNIPHY_BASE + + (uniphy_index * PPE_UNIPHY_REG_INC) + UNIPHY_PLL_RESET_REG_OFFSET); + ppe_gcc_uniphy_xpcs_reset(uniphy_index, true); + + reg_value = readl( PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC) + + PPE_UNIPHY_MODE_CONTROL); + reg_value &= ~(UNIPHY_CH0_ATHR_CSCO_MODE_25M | UNIPHY_CH0_PSGMII_QSGMII); + if (uniphy_index == PPE_UNIPHY_INSTANCE0) { + reg_value &= ~UNIPHY_SG_MODE; + if (channel == 0) { + reg_value &= ~UNIPHY_CH1_CH0_SGMII; + reg_value &= ~UNIPHY_CH4_CH1_0_SGMII; + } else if (channel == 1) { + reg_value |= UNIPHY_CH1_CH0_SGMII; + reg_value &= ~UNIPHY_CH4_CH1_0_SGMII; + } else if (channel == 4) { + reg_value &= ~UNIPHY_CH1_CH0_SGMII; + reg_value |= UNIPHY_CH4_CH1_0_SGMII; + } + } else { + reg_value &= ~UNIPHY_SG_PLUS_MODE; + reg_value |= UNIPHY_SG_MODE; + } + writel(reg_value, PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC) + + PPE_UNIPHY_MODE_CONTROL); + ppe_gcc_uniphy_soft_reset(uniphy_index); +} + +static void ppe_uniphy_sgmii_plus_mode_set(uint32_t uniphy_index) +{ + writel(UNIPHY_MISC2_REG_SGMII_PLUS_MODE, PPE_UNIPHY_BASE + + (uniphy_index * PPE_UNIPHY_REG_INC) + UNIPHY_MISC2_REG_OFFSET); + writel(UNIPHY_PLL_RESET_REG_VALUE, PPE_UNIPHY_BASE + + (uniphy_index * PPE_UNIPHY_REG_INC) + UNIPHY_PLL_RESET_REG_OFFSET); + udelay(500); + writel(UNIPHY_PLL_RESET_REG_DEFAULT_VALUE, PPE_UNIPHY_BASE + + (uniphy_index * PPE_UNIPHY_REG_INC) + UNIPHY_PLL_RESET_REG_OFFSET); + ppe_gcc_uniphy_xpcs_reset(uniphy_index, true); + + writel(0x820, PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC) + + PPE_UNIPHY_MODE_CONTROL); + ppe_gcc_uniphy_soft_reset(uniphy_index); + ppe_uniphy_calibration(uniphy_index); +} + +static int ppe_uniphy_10g_r_linkup(uint32_t uniphy_index) +{ + uint32_t reg_value = 0; + uint32_t retries = 100, linkup = 0; + + while (linkup != UNIPHY_10GR_LINKUP) { + mdelay(1); + if (retries-- == 0) + return -1; + reg_value = csr1_read(uniphy_index, SR_XS_PCS_KR_STS1_ADDRESS); + linkup = (reg_value >> 12) & UNIPHY_10GR_LINKUP; + } + mdelay(10); + return 0; +} + +static void ppe_uniphy_10g_r_mode_set(uint32_t uniphy_index) +{ + ppe_gcc_uniphy_xpcs_reset(uniphy_index, true); + writel(0x1021, PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC) + + PPE_UNIPHY_MODE_CONTROL); + writel(0x1C0, PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC) + + UNIPHY_INSTANCE_LINK_DETECT); + ppe_gcc_uniphy_soft_reset(uniphy_index); + ppe_uniphy_calibration(uniphy_index); + ppe_gcc_uniphy_xpcs_reset(uniphy_index, false); +} + + +static void ppe_uniphy_usxgmii_mode_set(uint32_t uniphy_index) +{ + uint32_t reg_value = 0; + + writel(UNIPHY_MISC2_REG_VALUE, PPE_UNIPHY_BASE + + (uniphy_index * PPE_UNIPHY_REG_INC) + UNIPHY_MISC2_REG_OFFSET); + writel(UNIPHY_PLL_RESET_REG_VALUE, PPE_UNIPHY_BASE + + (uniphy_index * PPE_UNIPHY_REG_INC) + UNIPHY_PLL_RESET_REG_OFFSET); + mdelay(500); + writel(UNIPHY_PLL_RESET_REG_DEFAULT_VALUE, PPE_UNIPHY_BASE + + (uniphy_index * PPE_UNIPHY_REG_INC) + UNIPHY_PLL_RESET_REG_OFFSET); + mdelay(500); + ppe_gcc_uniphy_xpcs_reset(uniphy_index, true); + writel(0x1021, PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC) + + PPE_UNIPHY_MODE_CONTROL); + ppe_gcc_uniphy_soft_reset(uniphy_index); + ppe_uniphy_calibration(uniphy_index); + ppe_gcc_uniphy_xpcs_reset(uniphy_index, false); + ppe_uniphy_10g_r_linkup(uniphy_index); + reg_value = csr1_read(uniphy_index, VR_XS_PCS_DIG_CTRL1_ADDRESS); + reg_value |= USXG_EN; + csr1_write(uniphy_index, VR_XS_PCS_DIG_CTRL1_ADDRESS, reg_value); + reg_value = csr1_read(uniphy_index, VR_MII_AN_CTRL_ADDRESS); + reg_value |= MII_AN_INTR_EN; + reg_value |= MII_CTRL; + csr1_write(uniphy_index, VR_MII_AN_CTRL_ADDRESS, reg_value); + reg_value = csr1_read(uniphy_index, SR_MII_CTRL_ADDRESS); + reg_value |= AN_ENABLE; + reg_value &= ~SS5; + reg_value |= SS6 | SS13 | DUPLEX_MODE; + csr1_write(uniphy_index, SR_MII_CTRL_ADDRESS, reg_value); +} + +void ppe_uniphy_mode_set(uint32_t uniphy_index, uint32_t mode) +{ + switch(mode) { + case PORT_WRAPPER_PSGMII: + ppe_uniphy_psgmii_mode_set(uniphy_index); + break; + case PORT_WRAPPER_QSGMII: + ppe_uniphy_qsgmii_mode_set(uniphy_index); + break; + case PORT_WRAPPER_SGMII0_RGMII4: + ppe_uniphy_sgmii_mode_set(uniphy_index, 0); + break; + case PORT_WRAPPER_SGMII1_RGMII4: + ppe_uniphy_sgmii_mode_set(uniphy_index, 1); + break; + case PORT_WRAPPER_SGMII4_RGMII4: + ppe_uniphy_sgmii_mode_set(uniphy_index, 4); + break; + case PORT_WRAPPER_SGMII_PLUS: + ppe_uniphy_sgmii_plus_mode_set(uniphy_index); + break; + case PORT_WRAPPER_USXGMII: + ppe_uniphy_usxgmii_mode_set(uniphy_index); + break; + case PORT_WRAPPER_10GBASE_R: + ppe_uniphy_10g_r_mode_set(uniphy_index); + break; + default: + break; + } +} + +void ppe_uniphy_usxgmii_autoneg_completed(uint32_t uniphy_index) +{ + uint32_t autoneg_complete = 0, retries = 100; + uint32_t reg_value = 0; + + while (autoneg_complete != 0x1) { + mdelay(1); + if (retries-- == 0) + { + return; + } + reg_value = csr1_read(uniphy_index, VR_MII_AN_INTR_STS); + autoneg_complete = reg_value & 0x1; + } + reg_value &= ~CL37_ANCMPLT_INTR; + csr1_write(uniphy_index, VR_MII_AN_INTR_STS, reg_value); +} + +void ppe_uniphy_usxgmii_speed_set(uint32_t uniphy_index, int speed) +{ + uint32_t reg_value = 0; + + reg_value = csr1_read(uniphy_index, SR_MII_CTRL_ADDRESS); + reg_value |= DUPLEX_MODE; + + switch(speed) { + case 0: + reg_value &=~SS5; + reg_value &=~SS6; + reg_value &=~SS13; + break; + case 1: + reg_value &=~SS5; + reg_value &=~SS6; + reg_value |=SS13; + break; + case 2: + reg_value &=~SS5; + reg_value |=SS6; + reg_value &=~SS13; + break; + case 3: + reg_value &=~SS5; + reg_value |=SS6; + reg_value |=SS13; + break; + case 4: + reg_value |=SS5; + reg_value &=~SS6; + reg_value &=~SS13; + break; + case 5: + reg_value |=SS5; + reg_value &=~SS6; + reg_value |=SS13; + break; + } + csr1_write(uniphy_index, SR_MII_CTRL_ADDRESS, reg_value); + +} + +void ppe_uniphy_usxgmii_duplex_set(uint32_t uniphy_index, int duplex) +{ + uint32_t reg_value = 0; + + reg_value = csr1_read(uniphy_index, SR_MII_CTRL_ADDRESS); + + if (duplex & 0x1) + reg_value |= DUPLEX_MODE; + else + reg_value &= ~DUPLEX_MODE; + + csr1_write(uniphy_index, SR_MII_CTRL_ADDRESS, reg_value); +} + +void ppe_uniphy_usxgmii_port_reset(uint32_t uniphy_index) +{ + uint32_t reg_value = 0; + + reg_value = csr1_read(uniphy_index, VR_XS_PCS_DIG_CTRL1_ADDRESS); + reg_value |= USRA_RST; + csr1_write(uniphy_index, VR_XS_PCS_DIG_CTRL1_ADDRESS, reg_value); +} diff --git a/sources/uboot-be550/drivers/net/ipq807x/ipq807x_uniphy.h b/sources/uboot-be550/drivers/net/ipq807x/ipq807x_uniphy.h new file mode 100644 index 00000000..4d8bac94 --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq807x/ipq807x_uniphy.h @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#define PPE_UNIPHY_INSTANCE0 0 +#define PPE_UNIPHY_INSTANCE1 1 +#define PPE_UNIPHY_INSTANCE2 2 + +#define GCC_UNIPHY0_MISC 0x01856004 +#define GCC_UNIPHY_REG_INC 0x100 +#define GCC_UNIPHY_USXGMII_XPCS_RESET 0x4 +#define GCC_UNIPHY_USXGMII_XPCS_RELEASE_RESET 0x0 + +#define PPE_UNIPHY_OFFSET_CALIB_4 0x1E0 +#define UNIPHY_CALIBRATION_DONE 0x1 + +#define GCC_UNIPHY_PSGMII_SOFT_RESET 0x3ff2 +#define GCC_UNIPHY_USXGMII_SOFT_RESET 0x36 + +#define PPE_UNIPHY_BASE 0X07A00000 +#define PPE_UNIPHY_REG_INC 0x10000 +#define PPE_UNIPHY_MODE_CONTROL 0x46C +#define UNIPHY_XPCS_MODE (1 << 12) +#define UNIPHY_SG_PLUS_MODE (1 << 11) +#define UNIPHY_SG_MODE (1 << 10) +#define UNIPHY_CH0_PSGMII_QSGMII (1 << 9) +#define UNIPHY_CH0_QSGMII_SGMII (1 << 8) +#define UNIPHY_CH4_CH1_0_SGMII (1 << 2) +#define UNIPHY_CH1_CH0_SGMII (1 << 1) +#define UNIPHY_CH0_ATHR_CSCO_MODE_25M (1 << 0) + +#define UNIPHY_INSTANCE_LINK_DETECT 0x570 + +#define UNIPHY_MISC2_REG_OFFSET 0x218 +#define UNIPHY_MISC2_REG_SGMII_MODE 0x30 +#define UNIPHY_MISC2_REG_SGMII_PLUS_MODE 0x50 + +#define UNIPHY_MISC2_REG_VALUE 0x70 + +#define UNIPHY_PLL_RESET_REG_OFFSET 0x780 +#define UNIPHY_PLL_RESET_REG_VALUE 0x02bf +#define UNIPHY_PLL_RESET_REG_DEFAULT_VALUE 0x02ff + +#define SR_XS_PCS_KR_STS1_ADDRESS 0x30020 +#define UNIPHY_10GR_LINKUP 0x1 + +#define VR_XS_PCS_DIG_CTRL1_ADDRESS 0x38000 +#define USXG_EN (1 << 9) +#define USRA_RST (1 << 10) + +#define VR_MII_AN_CTRL_ADDRESS 0x1f8001 +#define MII_AN_INTR_EN (1 << 0) +#define MII_CTRL (1 << 8) + +#define SR_MII_CTRL_ADDRESS 0x1f0000 +#define AN_ENABLE (1 << 12) +#define SS5 (1 << 5) +#define SS6 (1 << 6) +#define SS13 (1 << 13) +#define DUPLEX_MODE (1 << 8) + +#define VR_MII_AN_INTR_STS 0x1f8002 +#define CL37_ANCMPLT_INTR (1 << 0) + +void ppe_uniphy_mode_set(uint32_t uniphy_index, uint32_t mode); +void ppe_uniphy_usxgmii_port_reset(uint32_t uniphy_index); +void ppe_uniphy_usxgmii_duplex_set(uint32_t uniphy_index, int duplex); +void ppe_uniphy_usxgmii_speed_set(uint32_t uniphy_index, int speed); +void ppe_uniphy_usxgmii_autoneg_completed(uint32_t uniphy_index); diff --git a/sources/uboot-be550/drivers/net/ipq9574/ipq9574_aquantia_phy.c b/sources/uboot-be550/drivers/net/ipq9574/ipq9574_aquantia_phy.c new file mode 100644 index 00000000..66ae3f35 --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq9574/ipq9574_aquantia_phy.c @@ -0,0 +1,595 @@ +/* + * Copyright (c) 2017-2019, 2021, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include "ipq_phy.h" +#include "ipq9574_aquantia_phy.h" +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; +typedef struct { + unsigned int image_type; + unsigned int header_vsn_num; + unsigned int image_src; + unsigned char *image_dest_ptr; + unsigned int image_size; + unsigned int code_size; + unsigned char *signature_ptr; + unsigned int signature_size; + unsigned char *cert_chain_ptr; + unsigned int cert_chain_size; +} mbn_header_t; + +mbn_header_t *fwimg_header; +static int debug = 0; + +#ifdef CONFIG_QCA_MMC +extern qca_mmc mmc_host; +static qca_mmc *host = &mmc_host; +#endif + +extern int ipq_mdio_write(int mii_id, + int regnum, u16 value); +extern int ipq_mdio_read(int mii_id, + int regnum, ushort *data); + +extern int ipq_sw_mdio_init(const char *); +extern void ipq9574_eth_initialize(void); +static int program_ethphy_fw(unsigned int phy_addr, + uint32_t load_addr,uint32_t file_size ); +static qca_smem_flash_info_t *sfi = &qca_smem_flash_info; + +u16 aq_phy_reg_write(u32 dev_id, u32 phy_id, + u32 reg_id, u16 reg_val) +{ + ipq_mdio_write(phy_id, reg_id, reg_val); + return 0; +} + +u16 aq_phy_reg_read(u32 dev_id, u32 phy_id, u32 reg_id) +{ + return ipq_mdio_read(phy_id, reg_id, NULL); +} + +u8 aq_phy_get_link_status(u32 dev_id, u32 phy_id) +{ + u16 phy_data; + uint32_t reg; + + reg = AQ_PHY_AUTO_STATUS_REG | AQUANTIA_MII_ADDR_C45; + phy_data = aq_phy_reg_read(dev_id, phy_id, reg); + phy_data = aq_phy_reg_read(dev_id, phy_id, reg); + + if (((phy_data >> 2) & 0x1) & PORT_LINK_UP) + return 0; + + return 1; +} + +u32 aq_phy_get_duplex(u32 dev_id, u32 phy_id, fal_port_duplex_t *duplex) +{ + u16 phy_data; + uint32_t reg; + + reg = AQ_PHY_LINK_STATUS_REG | AQUANTIA_MII_ADDR_C45; + phy_data = aq_phy_reg_read(dev_id, phy_id, reg); + + /* + * Read duplex + */ + phy_data = phy_data & 0x1; + if (phy_data & 0x1) + *duplex = FAL_FULL_DUPLEX; + else + *duplex = FAL_HALF_DUPLEX; + + return 0; +} + +u32 aq_phy_get_speed(u32 dev_id, u32 phy_id, fal_port_speed_t *speed) +{ + u16 phy_data; + uint32_t reg; + + reg = AQ_PHY_LINK_STATUS_REG | AQUANTIA_MII_ADDR_C45; + phy_data = aq_phy_reg_read(dev_id, phy_id, reg); + + switch ((phy_data >> 1) & 0x7) { + case SPEED_10G: + *speed = FAL_SPEED_10000; + break; + case SPEED_5G: + *speed = FAL_SPEED_5000; + break; + case SPEED_2_5G: + *speed = FAL_SPEED_2500; + break; + case SPEED_1000MBS: + *speed = FAL_SPEED_1000; + break; + case SPEED_100MBS: + *speed = FAL_SPEED_100; + break; + case SPEED_10MBS: + *speed = FAL_SPEED_10; + break; + default: + return -EINVAL; + } + return 0; +} + +void aquantia_phy_restart_autoneg(u32 phy_id) +{ + u16 phy_data; + + phy_data = aq_phy_reg_read(0x0, phy_id, AQUANTIA_REG_ADDRESS(AQUANTIA_MMD_PHY_XS_REGISTERS, + AQUANTIA_PHY_XS_USX_TRANSMIT)); + if (!(phy_data & AQUANTIA_PHY_USX_AUTONEG_ENABLE)) + aq_phy_reg_write(0x0, phy_id,AQUANTIA_REG_ADDRESS( + AQUANTIA_MMD_PHY_XS_REGISTERS, + AQUANTIA_PHY_XS_USX_TRANSMIT), + phy_data | AQUANTIA_PHY_USX_AUTONEG_ENABLE); + + phy_data = aq_phy_reg_read(0x0, phy_id, AQUANTIA_REG_ADDRESS(AQUANTIA_MMD_AUTONEG, + AQUANTIA_AUTONEG_STANDARD_CONTROL1)); + + phy_data |= AQUANTIA_CTRL_AUTONEGOTIATION_ENABLE; + aq_phy_reg_write(0x0, phy_id, AQUANTIA_REG_ADDRESS(AQUANTIA_MMD_AUTONEG, + AQUANTIA_AUTONEG_STANDARD_CONTROL1), + phy_data | AQUANTIA_CTRL_RESTART_AUTONEGOTIATION); +} + +int ipq_qca_aquantia_phy_init(struct phy_ops **ops, u32 phy_id) +{ + u16 phy_data; + struct phy_ops *aq_phy_ops; + aq_phy_ops = (struct phy_ops *)malloc(sizeof(struct phy_ops)); + if (!aq_phy_ops) + return -ENOMEM; + aq_phy_ops->phy_get_link_status = aq_phy_get_link_status; + aq_phy_ops->phy_get_speed = aq_phy_get_speed; + aq_phy_ops->phy_get_duplex = aq_phy_get_duplex; + *ops = aq_phy_ops; + + phy_data = aq_phy_reg_read(0x0, phy_id, AQUANTIA_REG_ADDRESS(AQUANTIA_MMD_PHY_XS_REGISTERS, + AQUANTIA_PHY_XS_USX_TRANSMIT)); + + phy_data = aq_phy_reg_read(0x0, phy_id, AQUANTIA_REG_ADDRESS(1, QCA_PHY_ID1)); + printf ("PHY ID1: 0x%x\n", phy_data); + phy_data = aq_phy_reg_read(0x0, phy_id, AQUANTIA_REG_ADDRESS(1, QCA_PHY_ID2)); + printf ("PHY ID2: 0x%x\n", phy_data); + phy_data = aq_phy_reg_read(0x0, phy_id, AQUANTIA_REG_ADDRESS(AQUANTIA_MMD_PHY_XS_REGISTERS, + AQUANTIA_PHY_XS_USX_TRANSMIT)); + phy_data |= AQUANTIA_PHY_USX_AUTONEG_ENABLE; + aq_phy_reg_write(0x0, phy_id, AQUANTIA_REG_ADDRESS(AQUANTIA_MMD_PHY_XS_REGISTERS, + AQUANTIA_PHY_XS_USX_TRANSMIT), phy_data); + phy_data = aq_phy_reg_read(0x0, phy_id, AQUANTIA_REG_ADDRESS(AQUANTIA_MMD_AUTONEG, + AQUANTIA_AUTONEG_TRANSMIT_VENDOR_INTR_MASK)); + phy_data |= AQUANTIA_INTR_LINK_STATUS_CHANGE; + aq_phy_reg_write(0x0, phy_id, AQUANTIA_REG_ADDRESS(AQUANTIA_MMD_AUTONEG, + AQUANTIA_AUTONEG_TRANSMIT_VENDOR_INTR_MASK), phy_data); + phy_data = aq_phy_reg_read(0x0, phy_id, AQUANTIA_REG_ADDRESS(AQUANTIA_MMD_GLOABLE_REGISTERS, + AQUANTIA_GLOBAL_INTR_STANDARD_MASK)); + phy_data |= AQUANTIA_ALL_VENDOR_ALARMS_INTERRUPT_MASK; + aq_phy_reg_write(0x0, phy_id, AQUANTIA_REG_ADDRESS(AQUANTIA_MMD_GLOABLE_REGISTERS, + AQUANTIA_GLOBAL_INTR_STANDARD_MASK), phy_data); + phy_data = aq_phy_reg_read(0x0, phy_id, AQUANTIA_REG_ADDRESS(AQUANTIA_MMD_GLOABLE_REGISTERS, + AQUANTIA_GLOBAL_INTR_VENDOR_MASK)); + phy_data |= AQUANTIA_AUTO_AND_ALARMS_INTR_MASK; + aq_phy_reg_write(0x0, phy_id, AQUANTIA_REG_ADDRESS(AQUANTIA_MMD_GLOABLE_REGISTERS, + AQUANTIA_GLOBAL_INTR_VENDOR_MASK), phy_data); + + phy_data = aq_phy_reg_read(0x0, phy_id, AQUANTIA_REG_ADDRESS(AQUANTIA_MMD_PHY_XS_REGISTERS, + AQUANTIA_PHY_XS_USX_TRANSMIT)); + return 0; +} + +static int do_aq_phy_restart(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + unsigned int phy_addr = AQU_PHY_ADDR; + if (argc > 2) + return CMD_RET_USAGE; + + if (argc == 2) + phy_addr = simple_strtoul(argv[1], NULL, 16); + + aquantia_phy_restart_autoneg(phy_addr); + return 0; +} + +int ipq_board_fw_download(unsigned int phy_addr) +{ + char runcmd[256]; + int ret,i=0; + uint32_t start; /* block number */ + uint32_t size; /* no. of blocks */ + qca_part_entry_t ethphyfw; + unsigned int *ethphyfw_load_addr = NULL; + struct { char *name; qca_part_entry_t *part; } entries[] = { + { "0:ETHPHYFW", ðphyfw }, + }; +#ifdef CONFIG_QCA_MMC + block_dev_desc_t *blk_dev; + disk_partition_t disk_info; +#endif + /* check the smem info to see which flash used for booting */ + if (sfi->flash_type == SMEM_BOOT_SPI_FLASH) { + if (debug) { + printf("Using nor device \n"); + } + } else if (sfi->flash_type == SMEM_BOOT_NAND_FLASH) { + if (debug) { + printf("Using nand device 0\n"); + } + } else if (sfi->flash_type == SMEM_BOOT_MMC_FLASH) { + if (debug) { + printf("Using MMC device\n"); + } + } else if (sfi->flash_type == SMEM_BOOT_QSPI_NAND_FLASH) { + if (debug) { + printf("Using qspi nand device 0\n"); + } + } else { + printf("Unsupported BOOT flash type\n"); + return -1; + } + + ret = smem_getpart(entries[i].name, &start, &size); + if (ret < 0) { + debug("cdp: get part failed for %s\n", entries[i].name); + } else { + qca_set_part_entry(entries[i].name, sfi, entries[i].part, start, size); + } + + if ((sfi->flash_type == SMEM_BOOT_NAND_FLASH) || + (sfi->flash_type == SMEM_BOOT_QSPI_NAND_FLASH) || + (sfi->flash_type == SMEM_BOOT_SPI_FLASH)) { + ethphyfw_load_addr = (uint *)malloc(AQ_ETHPHYFW_IMAGE_SIZE); + /* We only need memory equivalent to max size ETHPHYFW + * which is currently assumed as 512 KB. + */ + if (ethphyfw_load_addr == NULL) { + printf("ETHPHYFW Loading failed, size = %llu\n", + ethphyfw.size); + return -1; + } else { + memset(ethphyfw_load_addr, 0, AQ_ETHPHYFW_IMAGE_SIZE); + } + } + + if ((sfi->flash_type == SMEM_BOOT_NAND_FLASH) || + (sfi->flash_type == SMEM_BOOT_QSPI_NAND_FLASH)) { + /* + * Kernel is in a separate partition + */ + snprintf(runcmd, sizeof(runcmd), + /* NOR is treated as psuedo NAND */ + "nand read 0x%p 0x%llx 0x%llx && ", + ethphyfw_load_addr, ethphyfw.offset, (long long unsigned int) AQ_ETHPHYFW_IMAGE_SIZE); + + if (debug) + printf("%s", runcmd); + + if (run_command(runcmd, 0) != CMD_RET_SUCCESS) { + free(ethphyfw_load_addr); + return CMD_RET_FAILURE; + } + } else if (sfi->flash_type == SMEM_BOOT_SPI_FLASH) { + snprintf(runcmd, sizeof(runcmd), + "sf probe && " "sf read 0x%p 0x%llx 0x%llx && ", + ethphyfw_load_addr, ethphyfw.offset, (long long unsigned int) AQ_ETHPHYFW_IMAGE_SIZE); + + if (debug) + printf("%s", runcmd); + + if (run_command(runcmd, 0) != CMD_RET_SUCCESS) { + free(ethphyfw_load_addr); + return CMD_RET_FAILURE; + } +#ifdef CONFIG_QCA_MMC + } else if (sfi->flash_type == SMEM_BOOT_MMC_FLASH ) { + blk_dev = mmc_get_dev(host->dev_num); + ret = get_partition_info_efi_by_name(blk_dev, + "0:ETHPHYFW", &disk_info); + + ethphyfw_load_addr = (uint *)malloc(((uint)disk_info.size) * + ((uint)disk_info.blksz)); + if (ethphyfw_load_addr == NULL) { + printf("ETHPHYFW Loading failed, size = %lu\n", + ((long unsigned int)(uint)disk_info.size) * ((uint)disk_info.blksz)); + return -1; + } else { + memset(ethphyfw_load_addr, 0, + (((uint)disk_info.size) * + ((uint)disk_info.blksz))); + } + + if (ret == 0) { + snprintf(runcmd, sizeof(runcmd), + "mmc read 0x%p 0x%X 0x%X", + ethphyfw_load_addr, + (uint)disk_info.start, (uint)disk_info.size); + + if (run_command(runcmd, 0) != CMD_RET_SUCCESS) { + free(ethphyfw_load_addr); + return CMD_RET_FAILURE; + } + } +#endif + } + + fwimg_header = (mbn_header_t *)(ethphyfw_load_addr); + + if (fwimg_header->image_type == 0x13 && + fwimg_header->header_vsn_num == 0x3) { + program_ethphy_fw(phy_addr, + (uint32_t)(((uint32_t)ethphyfw_load_addr) + + sizeof(mbn_header_t)), + (uint32_t)(fwimg_header->image_size)); + } else { + printf("bad magic on ETHPHYFW partition\n"); + free(ethphyfw_load_addr); + return -1; + } + free(ethphyfw_load_addr); + return 0; +} + + +#define AQ_PHY_IMAGE_HEADER_CONTENT_OFFSET_HHD 0x300 +static int program_ethphy_fw(unsigned int phy_addr, uint32_t load_addr, uint32_t file_size) +{ + int i; + uint8_t *buf; + uint16_t file_crc; + uint16_t computed_crc; + uint32_t reg1, reg2; + uint16_t recorded_ggp8_val; + uint16_t daisy_chain_dis; + uint32_t primary_header_ptr = 0x00000000; + uint32_t primary_iram_ptr = 0x00000000; + uint32_t primary_dram_ptr = 0x00000000; + uint32_t primary_iram_sz = 0x00000000; + uint32_t primary_dram_sz = 0x00000000; + uint32_t phy_img_hdr_off; + uint32_t byte_sz; + uint32_t dword_sz; + uint32_t byte_ptr; + uint16_t msw = 0; + uint16_t lsw = 0; + uint8_t msb1; + uint8_t msb2; + uint8_t lsb1; + uint8_t lsb2; + uint16_t mailbox_crc; + + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x300), 0xdead); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x301), 0xbeaf); + reg1 = aq_phy_reg_read(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x300)); + reg2 = aq_phy_reg_read(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x301)); + + if(reg1 != 0xdead && reg2 != 0xbeaf) { + printf("PHY::Scratchpad Read/Write test fail\n"); + return 0; + } + buf = (uint8_t *)load_addr; + file_crc = buf[file_size - 2] << 8 | buf[file_size - 1]; + computed_crc = cyg_crc16(buf, file_size - 2); + + if (file_crc != computed_crc) { + printf("CRC check failed on phy fw file\n"); + return 0; + } else { + printf("CRC check good on phy fw file (0x%04X)\n",computed_crc); + } + + daisy_chain_dis = aq_phy_reg_read(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0xc452)); + if (!(daisy_chain_dis & 0x1)) + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0xc452), 0x1); + + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0xc471), 0x40); + recorded_ggp8_val = aq_phy_reg_read(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0xc447)); + if ((recorded_ggp8_val & 0x1f) != phy_addr) + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0xc447), phy_addr); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0xc441), 0x4000); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0xc001), 0x41); + primary_header_ptr = (((buf[0x9] & 0x0F) << 8) | buf[0x8]) << 12; + phy_img_hdr_off = AQ_PHY_IMAGE_HEADER_CONTENT_OFFSET_HHD; + primary_iram_ptr = (buf[primary_header_ptr + phy_img_hdr_off + 0x4 + 2] << 16) | + (buf[primary_header_ptr + phy_img_hdr_off + 0x4 + 1] << 8) | + buf[primary_header_ptr + phy_img_hdr_off + 0x4]; + primary_iram_sz = (buf[primary_header_ptr + phy_img_hdr_off + 0x7 + 2] << 16) | + (buf[primary_header_ptr + phy_img_hdr_off + 0x7 + 1] << 8) | + buf[primary_header_ptr + phy_img_hdr_off + 0x7]; + primary_dram_ptr = (buf[primary_header_ptr + phy_img_hdr_off + 0xA + 2] << 16) | + (buf[primary_header_ptr + phy_img_hdr_off + 0xA + 1] << 8) | + buf[primary_header_ptr + phy_img_hdr_off + 0xA]; + primary_dram_sz = (buf[primary_header_ptr + phy_img_hdr_off + 0xD + 2] << 16) | + (buf[primary_header_ptr + phy_img_hdr_off + 0xD + 1] << 8) | + buf[primary_header_ptr + phy_img_hdr_off + 0xD]; + primary_iram_ptr += primary_header_ptr; + primary_dram_ptr += primary_header_ptr; + + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x200), 0x1000); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x200), 0x0); + computed_crc = 0; + printf("PHYFW:Loading IRAM..........."); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x202), 0x4000); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x203), 0x0); + byte_sz = primary_iram_sz; + dword_sz = byte_sz >> 2; + byte_ptr = primary_iram_ptr; + for (i = 0; i < dword_sz; i++) { + lsw = (buf[byte_ptr + 1] << 8) | buf[byte_ptr]; + byte_ptr += 2; + msw = (buf[byte_ptr + 1] << 8) | buf[byte_ptr]; + byte_ptr += 2; + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x204), msw); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x205), lsw); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x200), 0xc000); + msb1 = msw >> 8; + msb2 = msw & 0xFF; + lsb1 = lsw >> 8; + lsb2 = lsw & 0xFF; + computed_crc = cyg_crc16_computed(&msb1, 0x1, computed_crc); + computed_crc = cyg_crc16_computed(&msb2, 0x1, computed_crc); + computed_crc = cyg_crc16_computed(&lsb1, 0x1, computed_crc); + computed_crc = cyg_crc16_computed(&lsb2, 0x1, computed_crc); + } + + switch (byte_sz & 0x3) { + case 0x1: + lsw = buf[byte_ptr++]; + msw = 0x0000; + break; + case 0x2: + lsw = (buf[byte_ptr + 1] << 8) | buf[byte_ptr]; + byte_ptr += 2; + msw = 0x0000; + break; + case 0x3: + lsw = (buf[byte_ptr + 1] << 8) | buf[byte_ptr]; + byte_ptr += 2; + msw = buf[byte_ptr++]; + break; + } + + if (byte_sz & 0x3) { + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x204), msw); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x205), lsw); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x200), 0xc000); + msb1 = msw >> 8; + msb2 = msw & 0xFF; + lsb1 = lsw >> 8; + lsb2 = lsw & 0xFF; + computed_crc = cyg_crc16_computed(&msb1, 0x1, computed_crc); + computed_crc = cyg_crc16_computed(&msb2, 0x1, computed_crc); + computed_crc = cyg_crc16_computed(&lsb1, 0x1, computed_crc); + computed_crc = cyg_crc16_computed(&lsb2, 0x1, computed_crc); + } + printf("done.\n"); + printf("PHYFW:Loading DRAM.............."); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x202), 0x3ffe); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x203), 0x0); + byte_sz = primary_dram_sz; + dword_sz = byte_sz >> 2; + byte_ptr = primary_dram_ptr; + for (i = 0; i < dword_sz; i++) { + lsw = (buf[byte_ptr + 1] << 8) | buf[byte_ptr]; + byte_ptr += 2; + msw = (buf[byte_ptr + 1] << 8) | buf[byte_ptr]; + byte_ptr += 2; + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x204), msw); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x205), lsw); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x200), 0xc000); + msb1 = msw >> 8; + msb2 = msw & 0xFF; + lsb1 = lsw >> 8; + lsb2 = lsw & 0xFF; + computed_crc = cyg_crc16_computed(&msb1, 0x1, computed_crc); + computed_crc = cyg_crc16_computed(&msb2, 0x1, computed_crc); + computed_crc = cyg_crc16_computed(&lsb1, 0x1, computed_crc); + computed_crc = cyg_crc16_computed(&lsb2, 0x1, computed_crc); + } + + switch (byte_sz & 0x3) { + case 0x1: + lsw = buf[byte_ptr++]; + msw = 0x0000; + break; + case 0x2: + lsw = (buf[byte_ptr + 1] << 8) | buf[byte_ptr]; + byte_ptr += 2; + msw = 0x0000; + break; + case 0x3: + lsw = (buf[byte_ptr + 1] << 8) | buf[byte_ptr]; + byte_ptr += 2; + msw = buf[byte_ptr++]; + break; + } + + if (byte_sz & 0x3) { + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x204), msw); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x205), lsw); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x200), 0xc000); + msb1 = msw >> 8; + msb2 = msw & 0xFF; + lsb1 = lsw >> 8; + lsb2 = lsw & 0xFF; + computed_crc = cyg_crc16_computed(&msb1, 0x1, computed_crc); + computed_crc = cyg_crc16_computed(&msb2, 0x1, computed_crc); + computed_crc = cyg_crc16_computed(&lsb1, 0x1, computed_crc); + computed_crc = cyg_crc16_computed(&lsb2, 0x1, computed_crc); + } + printf("done.\n"); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0xc441), 0x2010); + mailbox_crc = aq_phy_reg_read(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x201)); + if (mailbox_crc != computed_crc) { + printf("phy fw image load CRC-16 (0x%X) does not match calculated CRC-16 (0x%X)\n", mailbox_crc, computed_crc); + return 0; + } else + printf("phy fw image load good CRC-16 matches (0x%X)\n", mailbox_crc); + + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x0), 0x0); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0xc001), 0x41); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0xc001), 0x8041); + mdelay(100); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0xc001), 0x40); + mdelay(100); + aquantia_phy_restart_autoneg(phy_addr); + return 0; +} + +static int do_load_fw(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + unsigned int phy_addr = AQU_PHY_ADDR; + + if (argc > 2) + return CMD_RET_USAGE; + + if (argc == 2) + phy_addr = simple_strtoul(argv[1], NULL, 16); + + miiphy_init(); + ipq9574_eth_initialize(); + ipq_sw_mdio_init("IPQ MDIO0"); + ipq_board_fw_download(phy_addr); + return 0; +} + +U_BOOT_CMD( + aq_load_fw, 5, 1, do_load_fw, + "LOAD aq-fw-binary", + "" +); + +U_BOOT_CMD( + aq_phy_restart, 5, 1, do_aq_phy_restart, + "Restart Aquantia phy", + "" +); diff --git a/sources/uboot-be550/drivers/net/ipq9574/ipq9574_aquantia_phy.h b/sources/uboot-be550/drivers/net/ipq9574/ipq9574_aquantia_phy.h new file mode 100644 index 00000000..9ddd6c27 --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq9574/ipq9574_aquantia_phy.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2017-2019, 2021, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#define AQ_ETHPHYFW_IMAGE_SIZE 0x80000 + +#define AQUANTIA_MII_ADDR_C45 (1<<30) +#define AQUANTIA_REG_ADDRESS(dev_ad, reg_num) (AQUANTIA_MII_ADDR_C45 |\ + ((dev_ad & 0x1f) << 16) | (reg_num & 0xFFFF)) + +#define AQUANTIA_MMD_PHY_XS_REGISTERS 4 +#define AQUANTIA_PHY_XS_USX_TRANSMIT 0xc441 +#define AQUANTIA_PHY_USX_AUTONEG_ENABLE 0x8 + +#define AQUANTIA_MMD_AUTONEG 0x7 +#define AQUANTIA_AUTONEG_TRANSMIT_VENDOR_INTR_MASK 0xD401 +#define AQUANTIA_INTR_LINK_STATUS_CHANGE 0x0001 + +#define AQUANTIA_MMD_GLOABLE_REGISTERS 0x1E +#define AQUANTIA_GLOBAL_INTR_STANDARD_MASK 0xff00 +#define AQUANTIA_ALL_VENDOR_ALARMS_INTERRUPT_MASK 0x0001 + +#define AQUANTIA_GLOBAL_INTR_VENDOR_MASK 0xff01 +#define AQUANTIA_AUTO_AND_ALARMS_INTR_MASK 0x1001 + +#define AQUANTIA_AUTONEG_STANDARD_CONTROL1 0 +#define AQUANTIA_CTRL_AUTONEGOTIATION_ENABLE 0x1000 +#define AQUANTIA_CTRL_RESTART_AUTONEGOTIATION 0x0200 + +#define AQ_PHY_AUTO_STATUS_REG 0x70001 + +#define AQ_PHY_LINK_STATUS_REG 0x7c800 +#define SPEED_5G 5 +#define SPEED_2_5G 4 +#define SPEED_10G 3 +#define SPEED_1000MBS 2 +#define SPEED_100MBS 1 +#define SPEED_10MBS 0 diff --git a/sources/uboot-be550/drivers/net/ipq9574/ipq9574_edma.c b/sources/uboot-be550/drivers/net/ipq9574/ipq9574_edma.c new file mode 100644 index 00000000..a5d11cbf --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq9574/ipq9574_edma.c @@ -0,0 +1,2619 @@ +/* + ************************************************************************** + * Copyright (c) 2016-2019, 2021, The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + ************************************************************************** +*/ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "ipq9574_edma.h" +#include "ipq_phy.h" +#include "ipq_qca8084.h" +#ifdef CONFIG_TP_EXT_PHY_RTL8251B +#include "../rtl8251b/rtl8251b_typedef.h" +#include "../rtl8251b/nic_rtl8251b_init.h" +#include "../rtl8251b/nic_rtl8251b.h" +#endif + +DECLARE_GLOBAL_DATA_PTR; +#ifdef DEBUG +#define pr_debug(fmt, args...) printf(fmt, ##args); +#else +#define pr_debug(fmt, args...) +#endif + +#define pr_info(fmt, args...) printf(fmt, ##args); +#define pr_warn(fmt, args...) printf(fmt, ##args); + +#ifndef CONFIG_IPQ9574_BRIDGED_MODE +#define IPQ9574_EDMA_MAC_PORT_NO 3 +#endif + +static struct ipq9574_eth_dev *ipq9574_edma_dev[IPQ9574_EDMA_DEV]; + +uchar ipq9574_def_enetaddr[6] = {0x00, 0x03, 0x7F, 0xBA, 0xDB, 0xAD}; +phy_info_t *phy_info[IPQ9574_PHY_MAX] = {0}; +phy_info_t *swt_info[QCA8084_MAX_PORTS] = {0}; +mdio_info_t *mdio_info[IPQ9574_PHY_MAX] = {0}; +int sgmii_mode[2] = {0}; + +extern void ipq_phy_addr_fixup(void); +extern void ipq_clock_init(void); +extern int ipq_sw_mdio_init(const char *); +extern int ipq_mdio_read(int mii_id, int regnum, ushort *data); +extern void ipq9574_qca8075_phy_map_ops(struct phy_ops **ops); +extern int ipq9574_qca8075_phy_init(struct phy_ops **ops, u32 phy_id); +extern void ipq9574_qca8075_phy_interface_set_mode(uint32_t phy_id, uint32_t mode); +extern int ipq_qca8033_phy_init(struct phy_ops **ops, u32 phy_id); +extern int ipq_qca8081_phy_init(struct phy_ops **ops, u32 phy_id); +extern int ipq_qca_aquantia_phy_init(struct phy_ops **ops, u32 phy_id); +extern int ipq_board_fw_download(unsigned int phy_addr); +extern void ipq_set_mdio_mode(const int mode, const int bus); + +#ifdef CONFIG_TP_EXT_PHY_RTL8261B +extern int rtl8261_phy_init(struct phy_ops **ops, u32 phy_id); +#endif + +#ifdef CONFIG_QCA8084_PHY_MODE +extern void ipq_qca8084_phy_hw_init(struct phy_ops **ops, u32 phy_addr); +extern void qca8084_phy_uqxgmii_speed_fixup(uint32_t phy_addr, uint32_t qca8084_port_id, + uint32_t status, fal_port_speed_t new_speed); +#endif /* CONFIG_QCA8084_PHY_MODE */ + +#ifdef CONFIG_QCA8084_SWT_MODE +extern int ipq_qca8084_hw_init(phy_info_t * phy_info[]); +extern int ipq_qca8084_link_update(phy_info_t * phy_info[]); +extern void ipq_qca8084_switch_hw_reset(int gpio); +#endif /* CONFIG_QCA8084_SWT_MODE */ + +static int tftp_acl_our_port; +static int qca8084_swt_port = -1; + +#ifdef CONFIG_TP_EXT_PHY_RTL8251B + +#define PHY_DAC(val) (val<<8) + +#define RTL8211_STATUS_LINK_MASK 0x0004 +#define RTL8211_STATUS_DUPLEX_MASK 0x0008 +#define RTL8211_STATUS_SPEED_MASK 0x2040 +#define RTL8211_STATUS_FULL_DUPLEX 0x2000 + +#define RTL8251B_LAN_MDIO_NUM 0 +#define RTL8251B_WAN_MDIO_NUM 3 +#define RTL8251B_LAN_RST_GPIO 57 +#define RTL8251B_WAN_RST_GPIO 36 +#define MII_ADDR_C45 (1<<30) + +#define PROC_DIR_LAN "rtl8251b_lan" +#define PROC_DIR_WAN "rtl8251b_wan" + +#define LOG_ERR(fmt, ...) \ + do { \ + printf("[rtl8251b] %s[%d]: "fmt, __func__, __LINE__, ##__VA_ARGS__); \ + } while(0) +#define ERR_PRINT(ret) \ + do { \ + if ( ret != SUCCESS ) printf("[rtl8251b] %s[%d]: error, return. ", __FUNCTION__, __LINE__); \ + } while(0) + +extern int ipq_mdio_read(int mii_id, int regnum, unsigned short *data); +extern int ipq_mdio_write(int mii_id, int regnum, unsigned short value); + +HANDLE g_handle = { + .unit = 0, + .port = 0 +}; + +static int lw_flip = 0; +static int g_mdio_num = 0; + +static int rtl8251b_mdio_write(unsigned short devad, int regnum, unsigned short val) +{ + int ret = 0; + regnum = MII_ADDR_C45 | ((devad & 0x1f) << 16) | (regnum & 0xffff); + + ret = ipq_mdio_write(g_mdio_num, regnum, val); + if (ret == -ETIMEDOUT) + { + printf("ipq_mdio_write ETIMEDOUT\n"); + return FAILURE; + } + return SUCCESS; +} + +static int rtl8251b_mdio_read(unsigned short devad, int regnum, unsigned short *data) +{ + int ret = 0; + regnum = MII_ADDR_C45 | (devad << 16) | (regnum & 0xffff); + + ret = ipq_mdio_read(g_mdio_num, regnum, data); + if (ret == -ETIMEDOUT) + { + printf("ipq_mdio_read ETIMEDOUT\n"); + return FAILURE; + } + return SUCCESS; +} + +BOOLEAN +MmdPhyRead( IN HANDLE hDevice, IN UINT16 dev, IN UINT16 addr, OUT UINT16 *data) +{ + return rtl8251b_mdio_read(dev, (int)addr, data); +} + +BOOLEAN +MmdPhyWrite( IN HANDLE hDevice, IN UINT16 dev, IN UINT16 addr, IN UINT16 data) +{ + return rtl8251b_mdio_write(dev, (int)addr, data); +} + +static void rtl8251b_gpio_reset(int gpio_num) +{ + // int ret; + // gpio_num += 447; + // ret = gpio_request(gpio_num , "phy8251_reset"); + // if(ret < 0) + // { + // printf("gpio request failed, ret:%d\n", ret); + // } + gpio_direction_output(gpio_num, 1); + mdelay(200); + gpio_set_value(gpio_num, 0); + mdelay(200); + gpio_set_value(gpio_num, 1); + mdelay(200); + printf("GPIO%d reset switch done\n", gpio_num); + // gpio_free(gpio_num); + return; +} + + + +static int +rtl8251_phy_get_status(uint32_t dev_id, uint32_t phy_id, + struct port_phy_status *phy_status) +{ + g_mdio_num = phy_id; + UINT8 speed_grp = 0; + UINT8 speed = NO_LINK; + uint16_t phydata = 0xffff; + MmdPhyRead(g_handle, MMD_VEND2, 0xA434, &phydata); + phy_status->link_status = (phydata & RTL8211_STATUS_LINK_MASK)?TRUE:FALSE; + phy_status->duplex = (phydata & RTL8211_STATUS_DUPLEX_MASK)?FAL_FULL_DUPLEX:FAL_HALF_DUPLEX; + if (phy_status->link_status) + { + speed_grp = (phydata & (BIT_9 | BIT_10)) >> 9; + speed = (phydata & (BIT_4 | BIT_5)) >> 4; + switch(speed_grp) + { + case 0: + { + switch(speed) + { + case 0: + phy_status->speed = FAL_SPEED_10; + break; + case 1: + phy_status->speed = FAL_SPEED_100; + break; + case 2: + phy_status->speed = FAL_SPEED_1000; + break; + case 3: + phy_status->speed = FAL_SPEED_100; // 1G lite + break; + + default: + phy_status->speed = FAL_SPEED_10; + break; + } + break; + } + case 1: + { + switch(speed) + { + case 1: + phy_status->speed = FAL_SPEED_2500; + break; + case 2: + phy_status->speed = FAL_SPEED_5000; //5G + break; + case 3: + phy_status->speed = FAL_SPEED_1000; // 2.5G lite + break; + default: + phy_status->speed = FAL_SPEED_10; + break; + } + break; + } + default: + phy_status->speed = FAL_SPEED_10; + break; + } + } + else + { + phy_status->speed = FAL_SPEED_10; + } + + // printf("get rtl8251 %u linkstatus: %u, speed: %d, duplex: %d\n", phy_id, phy_status->link_status, phy_status->speed, phy_status->duplex); + return 0; +} + + +u8 rtl8251_phy_get_link_status(uint32_t dev_id, uint32_t phy_id) +{ + struct port_phy_status phy_status; + rtl8251_phy_get_status( dev_id, phy_id, &phy_status); + if (phy_status.link_status) + { + return 0; //up + } + return 1; //down + +} + +u32 rtl8251_phy_get_speed(uint32_t dev_id, uint32_t phy_id, + fal_port_speed_t * speed) +{ + struct port_phy_status phy_status; + rtl8251_phy_get_status( dev_id, phy_id, &phy_status); + *speed = phy_status.speed; + return TRUE; +} + +u32 rtl8251_phy_get_duplex(uint32_t dev_id, uint32_t phy_id, + fal_port_duplex_t * duplex) + { + struct port_phy_status phy_status; + rtl8251_phy_get_status( dev_id, phy_id, &phy_status); + *duplex = phy_status.duplex; + return TRUE; + } + +static int _status_get(void) +{ + UINT16 phydata = 0; + int ret = -1; + + ret = MmdPhyRead(g_handle, MMD_VEND2, 0xA434, &phydata); + LOG_ERR("get rtl8251b phy 0xA434 phydata=0x%x\n", phydata); + + ret = MmdPhyRead(g_handle, MMD_VEND1, 0x7580, &phydata); + LOG_ERR("get rtl8251b phy 0x7580 phydata=0x%x\n", phydata); + + ret = MmdPhyRead(g_handle, MMD_VEND1, 0x758D, &phydata); + LOG_ERR("get rtl8251b phy 0x758D phydata=0x%x\n", phydata); + + ret = MmdPhyRead(g_handle, MMD_VEND1, 0x6973, &phydata); + LOG_ERR("get rtl8251b phy 0x6973 phydata=0x%x\n", phydata); + + return 0; +} + + + +/****************************************************************************** +* +* rtl8251_phy_init - +* +*******************************************************************************/ + + +int rtl8251b_init_common(a_uint32_t dev_id, a_uint32_t port_bmp) +{ + BOOL ret; + PHY_LINK_ABILITY phy_ability; + PHY_EEE_ENABLE eee_enable; + + ret = Rtl8251b_phy_init(g_handle, &phy_ability, TRUE); + ERR_PRINT(ret); + + // ret = Rtl8251b_serdes_autoNego_set(g_handle, TRUE); + // ERR_PRINT(ret); + + // ret = Rtl8251b_serdes_option_set(g_handle, PHY_SERDES_SPEED_USXGMII); + // ERR_PRINT(ret); + + // ret = Rtl8251b_phy_reset(g_handle); + // ERR_PRINT(ret); + + phy_ability.Half_10 = 1; + phy_ability.Full_10 = 1; + phy_ability.Half_100 = 1; + phy_ability.Full_100 = 1; + phy_ability.Full_1000 = 1; + phy_ability.adv_2_5G = 1; + phy_ability.adv_5G = 1; + phy_ability.FC = 1; + phy_ability.AsyFC = 1; + ret = Rtl8251b_autoNegoAbility_set(g_handle, &phy_ability); + ERR_PRINT(ret); + + ret = Rtl8251b_autoNegoEnable_set(g_handle, TRUE); + ERR_PRINT(ret); + + eee_enable.EEE_100 = 0; + eee_enable.EEE_1000 = 0; + eee_enable.EEE_2_5G = 0; + eee_enable.EEE_5G = 0; + ret = Rtl8251b_eeeEnable_set(g_handle, &eee_enable); + ERR_PRINT(ret); + + ret = Rtl8251b_greenEnable_set(g_handle, FALSE); + ERR_PRINT(ret); + + Rtl8251b_enable_set(g_handle, TRUE); + + // _status_get(); + + return 0; +} + +int rtl8251b_lan_init(a_uint32_t dev_id, a_uint32_t port_bmp, int mdio_num) +{ + g_mdio_num = mdio_num; + rtl8251b_init_common(dev_id,port_bmp); + return 0; +} +int rtl8251b_wan_init(a_uint32_t dev_id, a_uint32_t port_bmp, int mdio_num) +{ + g_mdio_num = mdio_num; + rtl8251b_init_common(dev_id,port_bmp); + return 0; +} + +int rtl8251b_init(struct phy_ops **ops, u32 phy_addr) +{ + static int rtl8251_is_init = 0; + struct phy_ops *rtl8251_phy_ops; + rtl8251_phy_ops = (struct phy_ops *)malloc(sizeof(struct phy_ops)); + if (!rtl8251_phy_ops) + return -ENOMEM; + rtl8251_phy_ops->phy_get_link_status = rtl8251_phy_get_link_status; + rtl8251_phy_ops->phy_get_speed = rtl8251_phy_get_speed; + rtl8251_phy_ops->phy_get_duplex = rtl8251_phy_get_duplex; + *ops = rtl8251_phy_ops; + + if (rtl8251_is_init == 0) + { + rtl8251b_gpio_reset(RTL8251B_LAN_RST_GPIO); //LAN hardware reset + rtl8251b_lan_init(0,0, RTL8251B_LAN_MDIO_NUM); + rtl8251b_gpio_reset(RTL8251B_WAN_RST_GPIO); //LAN hardware reset + rtl8251b_lan_init(0,0, RTL8251B_WAN_MDIO_NUM); + rtl8251_is_init = 1; + } + + return 0; +} + +#endif + +/* + * EDMA hardware instance + */ +static u32 ipq9574_edma_hw_addr; + +/* + * ipq9574_edma_reg_read() + * Read EDMA register + */ +uint32_t ipq9574_edma_reg_read(uint32_t reg_off) +{ + return (uint32_t)readl(ipq9574_edma_hw_addr + reg_off); +} + +/* + * ipq9574_edma_reg_write() + * Write EDMA register + */ +void ipq9574_edma_reg_write(uint32_t reg_off, uint32_t val) +{ + writel(val, (ipq9574_edma_hw_addr + reg_off)); +} + +/* + * ipq9574_edma_alloc_rx_buffer() + * Alloc Rx buffers for one RxFill ring + */ +int ipq9574_edma_alloc_rx_buffer(struct ipq9574_edma_hw *ehw, + struct ipq9574_edma_rxfill_ring *rxfill_ring) +{ + uint16_t num_alloc = 0; + uint16_t cons, next, counter; + struct ipq9574_edma_rxfill_desc *rxfill_desc; + uint32_t reg_data; + + /* + * Read RXFILL ring producer index + */ + reg_data = ipq9574_edma_reg_read(IPQ9574_EDMA_REG_RXFILL_PROD_IDX( + rxfill_ring->id)); + + next = reg_data & IPQ9574_EDMA_RXFILL_PROD_IDX_MASK & (rxfill_ring->count - 1); + + /* + * Read RXFILL ring consumer index + */ + reg_data = ipq9574_edma_reg_read(IPQ9574_EDMA_REG_RXFILL_CONS_IDX( + rxfill_ring->id)); + + cons = reg_data & IPQ9574_EDMA_RXFILL_CONS_IDX_MASK; + + while (1) { + counter = next; + + if (++counter == rxfill_ring->count) + counter = 0; + + if (counter == cons) + break; + + /* + * Get RXFILL descriptor + */ + rxfill_desc = IPQ9574_EDMA_RXFILL_DESC(rxfill_ring, next); + + /* + * Fill the opaque value + */ + rxfill_desc->rdes2 = next; + + /* + * Save buffer size in RXFILL descriptor + */ + rxfill_desc->rdes1 |= cpu_to_le32((IPQ9574_EDMA_RX_BUFF_SIZE << + IPQ9574_EDMA_RXFILL_BUF_SIZE_SHIFT) & + IPQ9574_EDMA_RXFILL_BUF_SIZE_MASK); + num_alloc++; + next = counter; + } + + if (num_alloc) { + /* + * Update RXFILL ring producer index + */ + reg_data = next & IPQ9574_EDMA_RXFILL_PROD_IDX_MASK; + + /* + * make sure the producer index updated before + * updating the hardware + */ + ipq9574_edma_reg_write(IPQ9574_EDMA_REG_RXFILL_PROD_IDX( + rxfill_ring->id), reg_data); + + pr_debug("%s: num_alloc = %d\n", __func__, num_alloc); + } + + return num_alloc; +} + +/* + * ipq9574_edma_clean_tx() + * Reap Tx descriptors + */ +uint32_t ipq9574_edma_clean_tx(struct ipq9574_edma_hw *ehw, + struct ipq9574_edma_txcmpl_ring *txcmpl_ring) +{ + struct ipq9574_edma_txcmpl_desc *txcmpl_desc; + uint16_t prod_idx, cons_idx; + uint32_t data; + uint32_t txcmpl_consumed = 0; + uchar *skb; + + /* + * Get TXCMPL ring producer index + */ + data = ipq9574_edma_reg_read(IPQ9574_EDMA_REG_TXCMPL_PROD_IDX( + txcmpl_ring->id)); + prod_idx = data & IPQ9574_EDMA_TXCMPL_PROD_IDX_MASK; + + /* + * Get TXCMPL ring consumer index + */ + data = ipq9574_edma_reg_read(IPQ9574_EDMA_REG_TXCMPL_CONS_IDX( + txcmpl_ring->id)); + cons_idx = data & IPQ9574_EDMA_TXCMPL_CONS_IDX_MASK; + + while (cons_idx != prod_idx) { + + txcmpl_desc = IPQ9574_EDMA_TXCMPL_DESC(txcmpl_ring, cons_idx); + + skb = (uchar *)txcmpl_desc->tdes0; + + if (unlikely(!skb)) { + printf("Invalid skb: cons_idx:%u prod_idx:%u\n", + cons_idx, prod_idx); + } + + if (++cons_idx == txcmpl_ring->count) + cons_idx = 0; + + txcmpl_consumed++; + } + + pr_debug("%s :%u txcmpl_consumed:%u prod_idx:%u cons_idx:%u\n", + __func__, txcmpl_ring->id, txcmpl_consumed, prod_idx, + cons_idx); + + if (txcmpl_consumed == 0) + return 0; + + /* + * Update TXCMPL ring consumer index + */ + ipq9574_edma_reg_write(IPQ9574_EDMA_REG_TXCMPL_CONS_IDX( + txcmpl_ring->id), cons_idx); + + return txcmpl_consumed; +} + +/* + * ipq9574_edma_clean_rx() + * Reap Rx descriptors + */ +uint32_t ipq9574_edma_clean_rx(struct ipq9574_edma_common_info *c_info, + struct ipq9574_edma_rxdesc_ring *rxdesc_ring) +{ + void *skb; + struct ipq9574_edma_rxdesc_desc *rxdesc_desc; + uint16_t prod_idx, cons_idx; + int src_port_num; + int pkt_length; + int rx = CONFIG_SYS_RX_ETH_BUFFER; + u16 cleaned_count = 0; + + pr_debug("%s: rxdesc_ring->id = %d\n", __func__, rxdesc_ring->id); + /* + * Read Rx ring consumer index + */ + cons_idx = ipq9574_edma_reg_read(IPQ9574_EDMA_REG_RXDESC_CONS_IDX( + rxdesc_ring->id)) & + IPQ9574_EDMA_RXDESC_CONS_IDX_MASK; + + while (rx) { + /* + * Read Rx ring producer index + */ + prod_idx = ipq9574_edma_reg_read( + IPQ9574_EDMA_REG_RXDESC_PROD_IDX(rxdesc_ring->id)) + & IPQ9574_EDMA_RXDESC_PROD_IDX_MASK; + + if (cons_idx == prod_idx) { + pr_debug("%s: cons idx = %u, prod idx = %u\n", + __func__, cons_idx, prod_idx); + break; + } + + rxdesc_desc = IPQ9574_EDMA_RXDESC_DESC(rxdesc_ring, cons_idx); + + skb = (void *)rxdesc_desc->rdes0; + + rx--; + + /* + * Check src_info from Rx Descriptor + */ + src_port_num = IPQ9574_EDMA_RXDESC_SRC_INFO_GET(rxdesc_desc->rdes4); + if ((src_port_num & IPQ9574_EDMA_RXDESC_SRCINFO_TYPE_MASK) == + IPQ9574_EDMA_RXDESC_SRCINFO_TYPE_PORTID) { + src_port_num &= IPQ9574_EDMA_RXDESC_PORTNUM_BITS; + } else { + pr_warn("WARN: src_info_type:0x%x. Drop skb:%p\n", + (src_port_num & IPQ9574_EDMA_RXDESC_SRCINFO_TYPE_MASK), + skb); + goto next_rx_desc; + } + + /* + * Get packet length + */ + pkt_length = (rxdesc_desc->rdes5 & + IPQ9574_EDMA_RXDESC_PKT_SIZE_MASK) >> + IPQ9574_EDMA_RXDESC_PKT_SIZE_SHIFT; + + if (unlikely((src_port_num < IPQ9574_NSS_DP_START_PHY_PORT) || + (src_port_num > IPQ9574_NSS_DP_MAX_PHY_PORTS))) { + pr_warn("WARN: Port number error :%d. Drop skb:%p\n", + src_port_num, skb); + goto next_rx_desc; + } + + cleaned_count++; + + pr_debug("%s: received pkt %p with length %d\n", + __func__, skb, pkt_length); + + net_process_received_packet(skb, pkt_length); +next_rx_desc: + /* + * Update consumer index + */ + if (++cons_idx == rxdesc_ring->count) + cons_idx = 0; + } + + if (cleaned_count) { + ipq9574_edma_reg_write(IPQ9574_EDMA_REG_RXDESC_CONS_IDX( + rxdesc_ring->id), cons_idx); + } + + return 0; +} + +/* + * ip9574_edma_rx_complete() + */ +static int ipq9574_edma_rx_complete(struct ipq9574_edma_common_info *c_info) +{ + struct ipq9574_edma_hw *ehw = &c_info->hw; + struct ipq9574_edma_txcmpl_ring *txcmpl_ring; + struct ipq9574_edma_rxdesc_ring *rxdesc_ring; + struct ipq9574_edma_rxfill_ring *rxfill_ring; + uint32_t misc_intr_status, reg_data; + int i; + + for (i = 0; i < ehw->rxdesc_rings; i++) { + rxdesc_ring = &ehw->rxdesc_ring[i]; + ipq9574_edma_clean_rx(c_info, rxdesc_ring); + } + + for (i = 0; i < ehw->txcmpl_rings; i++) { + txcmpl_ring = &ehw->txcmpl_ring[i]; + ipq9574_edma_clean_tx(ehw, txcmpl_ring); + } + + for (i = 0; i < ehw->rxfill_rings; i++) { + rxfill_ring = &ehw->rxfill_ring[i]; + ipq9574_edma_alloc_rx_buffer(ehw, rxfill_ring); + } + + /* + * Enable RXDESC EDMA ring interrupt masks + */ + for (i = 0; i < ehw->rxdesc_rings; i++) { + rxdesc_ring = &ehw->rxdesc_ring[i]; + ipq9574_edma_reg_write( + IPQ9574_EDMA_REG_RXDESC_INT_MASK(rxdesc_ring->id), + ehw->rxdesc_intr_mask); + } + + /* + * Enable TX EDMA ring interrupt masks + */ + for (i = 0; i < ehw->txcmpl_rings; i++) { + txcmpl_ring = &ehw->txcmpl_ring[i]; + ipq9574_edma_reg_write(IPQ9574_EDMA_REG_TX_INT_MASK( + txcmpl_ring->id), + ehw->txcmpl_intr_mask); + } + + /* + * Enable RXFILL EDMA ring interrupt masks + */ + for (i = 0; i < ehw->rxfill_rings; i++) { + rxfill_ring = &ehw->rxfill_ring[i]; + ipq9574_edma_reg_write(IPQ9574_EDMA_REG_RXFILL_INT_MASK( + rxfill_ring->id), + ehw->rxfill_intr_mask); + } + + /* + * Read Misc intr status + */ + reg_data = ipq9574_edma_reg_read(IPQ9574_EDMA_REG_MISC_INT_STAT); + misc_intr_status = reg_data & ehw->misc_intr_mask; + + if (misc_intr_status != 0) { + pr_info("%s: misc_intr_status = 0x%x\n", __func__, + misc_intr_status); + ipq9574_edma_reg_write(IPQ9574_EDMA_REG_MISC_INT_MASK, + IPQ9574_EDMA_MASK_INT_DISABLE); + } + + return 0; +} + +/* + * ipq9574_eth_snd() + * Transmit a packet using an EDMA ring + */ +static int ipq9574_eth_snd(struct eth_device *dev, void *packet, int length) +{ + struct ipq9574_eth_dev *priv = dev->priv; + struct ipq9574_edma_common_info *c_info = priv->c_info; + struct ipq9574_edma_hw *ehw = &c_info->hw; + struct ipq9574_edma_txdesc_desc *txdesc; + struct ipq9574_edma_txdesc_ring *txdesc_ring; + uint16_t hw_next_to_use, hw_next_to_clean, chk_idx; + uint32_t data; + uchar *skb; + + txdesc_ring = ehw->txdesc_ring; + + if (tftp_acl_our_port != tftp_our_port) { + /* Allowing tftp packets */ + ipq9574_ppe_acl_set(3, 0x4, 0x1, tftp_our_port, 0xffff, 0, 0); + tftp_acl_our_port = tftp_our_port; + } + /* + * Read TXDESC ring producer index + */ + data = ipq9574_edma_reg_read(IPQ9574_EDMA_REG_TXDESC_PROD_IDX( + txdesc_ring->id)); + + hw_next_to_use = data & IPQ9574_EDMA_TXDESC_PROD_IDX_MASK; + + pr_debug("%s: txdesc_ring->id = %d\n", __func__, txdesc_ring->id); + + /* + * Read TXDESC ring consumer index + */ + /* + * TODO - read to local variable to optimize uncached access + */ + data = ipq9574_edma_reg_read( + IPQ9574_EDMA_REG_TXDESC_CONS_IDX(txdesc_ring->id)); + + hw_next_to_clean = data & IPQ9574_EDMA_TXDESC_CONS_IDX_MASK; + + /* + * Check for available Tx descriptor + */ + chk_idx = (hw_next_to_use + 1) & (txdesc_ring->count - 1); + + if (chk_idx == hw_next_to_clean) { + pr_info("netdev tx busy"); + return NETDEV_TX_BUSY; + } + + /* + * Get Tx descriptor + */ + txdesc = IPQ9574_EDMA_TXDESC_DESC(txdesc_ring, hw_next_to_use); + + txdesc->tdes1 = 0; + txdesc->tdes2 = 0; + txdesc->tdes3 = 0; + txdesc->tdes4 = 0; + txdesc->tdes5 = 0; + txdesc->tdes6 = 0; + txdesc->tdes7 = 0; + skb = (uchar *)txdesc->tdes0; + + pr_debug("%s: txdesc->tdes0 (buffer addr) = 0x%x length = %d \ + prod_idx = %d cons_idx = %d\n", + __func__, txdesc->tdes0, length, + hw_next_to_use, hw_next_to_clean); + +#ifdef CONFIG_IPQ9574_BRIDGED_MODE + /* VP 0x0 share vsi 2 with port 1-4 */ + /* src is 0x2000, dest is 0x0 */ + txdesc->tdes4 = 0x00002000; +#else + /* + * Populate Tx dst info, port id is macid in dp_dev + * We have separate netdev for each port in Kernel but that is not the + * case in U-Boot. + * This part needs to be fixed to support multiple ports in non bridged + * mode during when all the ports are currently under same netdev. + * + * Currently mac port no. is fixed as 3 for the purpose of testing + */ + txdesc->tdes4 |= (IPQ9574_EDMA_DST_PORT_TYPE_SET(IPQ9574_EDMA_DST_PORT_TYPE) | + IPQ9574_EDMA_DST_PORT_ID_SET(IPQ9574_EDMA_MAC_PORT_NO)); +#endif + + /* + * Set opaque field + */ + txdesc->tdes2 = cpu_to_le32(skb); + + /* + * copy the packet + */ + memcpy(skb, packet, length); + + /* + * Populate Tx descriptor + */ + txdesc->tdes5 |= ((length << IPQ9574_EDMA_TXDESC_DATA_LENGTH_SHIFT) & + IPQ9574_EDMA_TXDESC_DATA_LENGTH_MASK); + + /* + * Update producer index + */ + hw_next_to_use = (hw_next_to_use + 1) & (txdesc_ring->count - 1); + + /* + * make sure the hw_next_to_use is updated before the + * write to hardware + */ + + ipq9574_edma_reg_write(IPQ9574_EDMA_REG_TXDESC_PROD_IDX( + txdesc_ring->id), hw_next_to_use & + IPQ9574_EDMA_TXDESC_PROD_IDX_MASK); + + pr_debug("%s: successfull\n", __func__); + + return EDMA_TX_OK; +} + +static int ipq9574_eth_recv(struct eth_device *dev) +{ + struct ipq9574_eth_dev *priv = dev->priv; + struct ipq9574_edma_common_info *c_info = priv->c_info; + struct ipq9574_edma_rxdesc_ring *rxdesc_ring; + struct ipq9574_edma_txcmpl_ring *txcmpl_ring; + struct ipq9574_edma_rxfill_ring *rxfill_ring; + struct ipq9574_edma_hw *ehw = &c_info->hw; + volatile u32 reg_data; + u32 rxdesc_intr_status = 0, txcmpl_intr_status = 0, rxfill_intr_status = 0; + int i; + + /* + * Read RxDesc intr status + */ + for (i = 0; i < ehw->rxdesc_rings; i++) { + rxdesc_ring = &ehw->rxdesc_ring[i]; + + reg_data = ipq9574_edma_reg_read( + IPQ9574_EDMA_REG_RXDESC_INT_STAT( + rxdesc_ring->id)); + rxdesc_intr_status |= reg_data & + IPQ9574_EDMA_RXDESC_RING_INT_STATUS_MASK; + + /* + * Disable RxDesc intr + */ + ipq9574_edma_reg_write(IPQ9574_EDMA_REG_RXDESC_INT_MASK( + rxdesc_ring->id), + IPQ9574_EDMA_MASK_INT_DISABLE); + } + + /* + * Read TxCmpl intr status + */ + for (i = 0; i < ehw->txcmpl_rings; i++) { + txcmpl_ring = &ehw->txcmpl_ring[i]; + + reg_data = ipq9574_edma_reg_read( + IPQ9574_EDMA_REG_TX_INT_STAT( + txcmpl_ring->id)); + txcmpl_intr_status |= reg_data & + IPQ9574_EDMA_TXCMPL_RING_INT_STATUS_MASK; + + /* + * Disable TxCmpl intr + */ + ipq9574_edma_reg_write(IPQ9574_EDMA_REG_TX_INT_MASK( + txcmpl_ring->id), + IPQ9574_EDMA_MASK_INT_DISABLE); + } + + /* + * Read RxFill intr status + */ + for (i = 0; i < ehw->rxfill_rings; i++) { + rxfill_ring = &ehw->rxfill_ring[i]; + + reg_data = ipq9574_edma_reg_read( + IPQ9574_EDMA_REG_RXFILL_INT_STAT( + rxfill_ring->id)); + rxfill_intr_status |= reg_data & + IPQ9574_EDMA_RXFILL_RING_INT_STATUS_MASK; + + /* + * Disable RxFill intr + */ + ipq9574_edma_reg_write(IPQ9574_EDMA_REG_RXFILL_INT_MASK( + rxfill_ring->id), + IPQ9574_EDMA_MASK_INT_DISABLE); + } + + if ((rxdesc_intr_status != 0) || (txcmpl_intr_status != 0) || + (rxfill_intr_status != 0)) { + for (i = 0; i < ehw->rxdesc_rings; i++) { + rxdesc_ring = &ehw->rxdesc_ring[i]; + ipq9574_edma_reg_write(IPQ9574_EDMA_REG_RXDESC_INT_MASK( + rxdesc_ring->id), + IPQ9574_EDMA_MASK_INT_DISABLE); + } + ipq9574_edma_rx_complete(c_info); + } + + return 0; +} + +/* + * ipq9574_edma_setup_ring_resources() + * Allocate/setup resources for EDMA rings + */ +static int ipq9574_edma_setup_ring_resources(struct ipq9574_edma_hw *ehw) +{ + struct ipq9574_edma_txcmpl_ring *txcmpl_ring; + struct ipq9574_edma_txdesc_ring *txdesc_ring; + struct ipq9574_edma_rxfill_ring *rxfill_ring; + struct ipq9574_edma_rxdesc_ring *rxdesc_ring; + struct ipq9574_edma_txdesc_desc *txdesc_desc; + struct ipq9574_edma_rxfill_desc *rxfill_desc; + int i, j, index; + void *tx_buf; + void *rx_buf; + + /* + * Allocate Rx fill ring descriptors + */ + for (i = 0; i < ehw->rxfill_rings; i++) { + rxfill_ring = &ehw->rxfill_ring[i]; + rxfill_ring->count = IPQ9574_EDMA_RX_RING_SIZE; + rxfill_ring->id = ehw->rxfill_ring_start + i; + rxfill_ring->desc = (void *)noncached_alloc( + IPQ9574_EDMA_RXFILL_DESC_SIZE * rxfill_ring->count, + CONFIG_SYS_CACHELINE_SIZE); + + if (rxfill_ring->desc == NULL) { + pr_info("%s: rxfill_ring->desc alloc error\n", __func__); + return -ENOMEM; + } + rxfill_ring->dma = virt_to_phys(rxfill_ring->desc); + pr_debug("rxfill ring id = %d, rxfill ring ptr = %p, rxfill ring dma = %u\n", + rxfill_ring->id, rxfill_ring->desc, (unsigned int) + rxfill_ring->dma); + + rx_buf = (void *)noncached_alloc(IPQ9574_EDMA_RX_BUFF_SIZE * + rxfill_ring->count, + CONFIG_SYS_CACHELINE_SIZE); + + if (rx_buf == NULL) { + pr_info("%s: rxfill_ring->desc buffer alloc error\n", + __func__); + return -ENOMEM; + } + + /* + * Allocate buffers for each of the desc + */ + for (j = 0; j < rxfill_ring->count; j++) { + rxfill_desc = IPQ9574_EDMA_RXFILL_DESC(rxfill_ring, j); + rxfill_desc->rdes0 = virt_to_phys(rx_buf); + rxfill_desc->rdes1 = 0; + rxfill_desc->rdes2 = 0; + rxfill_desc->rdes3 = 0; + rx_buf += IPQ9574_EDMA_RX_BUFF_SIZE; + } + } + + /* + * Allocate RxDesc ring descriptors + */ + for (i = 0; i < ehw->rxdesc_rings; i++) { + rxdesc_ring = &ehw->rxdesc_ring[i]; + rxdesc_ring->count = IPQ9574_EDMA_RX_RING_SIZE; + rxdesc_ring->id = ehw->rxdesc_ring_start + i; + + /* + * Create a mapping between RX Desc ring and Rx fill ring. + * Number of fill rings are lesser than the descriptor rings + * Share the fill rings across descriptor rings. + */ + index = ehw->rxfill_ring_start + (i % ehw->rxfill_rings); + rxdesc_ring->rxfill = + &ehw->rxfill_ring[index - ehw->rxfill_ring_start]; + rxdesc_ring->rxfill = ehw->rxfill_ring; + + rxdesc_ring->desc = (void *)noncached_alloc( + IPQ9574_EDMA_RXDESC_DESC_SIZE * rxdesc_ring->count, + CONFIG_SYS_CACHELINE_SIZE); + if (rxdesc_ring->desc == NULL) { + pr_info("%s: rxdesc_ring->desc alloc error\n", __func__); + return -ENOMEM; + } + rxdesc_ring->dma = virt_to_phys(rxdesc_ring->desc); + + /* + * Allocate secondary Rx ring descriptors + */ + rxdesc_ring->sdesc = (void *)noncached_alloc( + IPQ9574_EDMA_RX_SEC_DESC_SIZE * rxdesc_ring->count, + CONFIG_SYS_CACHELINE_SIZE); + if (rxdesc_ring->sdesc == NULL) { + pr_info("%s: rxdesc_ring->sdesc alloc error\n", __func__); + return -ENOMEM; + } + rxdesc_ring->sdma = virt_to_phys(rxdesc_ring->sdesc); + } + + /* + * Allocate TxDesc ring descriptors + */ + for (i = 0; i < ehw->txdesc_rings; i++) { + txdesc_ring = &ehw->txdesc_ring[i]; + txdesc_ring->count = IPQ9574_EDMA_TX_RING_SIZE; + txdesc_ring->id = ehw->txdesc_ring_start + i; + txdesc_ring->desc = (void *)noncached_alloc( + IPQ9574_EDMA_TXDESC_DESC_SIZE * txdesc_ring->count, + CONFIG_SYS_CACHELINE_SIZE); + if (txdesc_ring->desc == NULL) { + pr_info("%s: txdesc_ring->desc alloc error\n", __func__); + return -ENOMEM; + } + txdesc_ring->dma = virt_to_phys(txdesc_ring->desc); + + tx_buf = (void *)noncached_alloc(IPQ9574_EDMA_TX_BUFF_SIZE * + txdesc_ring->count, + CONFIG_SYS_CACHELINE_SIZE); + if (tx_buf == NULL) { + pr_info("%s: txdesc_ring->desc buffer alloc error\n", + __func__); + return -ENOMEM; + } + + /* + * Allocate buffers for each of the desc + */ + for (j = 0; j < txdesc_ring->count; j++) { + txdesc_desc = IPQ9574_EDMA_TXDESC_DESC(txdesc_ring, j); + txdesc_desc->tdes0 = virt_to_phys(tx_buf); + txdesc_desc->tdes1 = 0; + txdesc_desc->tdes2 = 0; + txdesc_desc->tdes3 = 0; + txdesc_desc->tdes4 = 0; + txdesc_desc->tdes5 = 0; + txdesc_desc->tdes6 = 0; + txdesc_desc->tdes7 = 0; + tx_buf += IPQ9574_EDMA_TX_BUFF_SIZE; + } + + /* + * Allocate secondary Tx ring descriptors + */ + txdesc_ring->sdesc = (void *)noncached_alloc( + IPQ9574_EDMA_TX_SEC_DESC_SIZE * txdesc_ring->count, + CONFIG_SYS_CACHELINE_SIZE); + if (txdesc_ring->sdesc == NULL) { + pr_info("%s: txdesc_ring->sdesc alloc error\n", __func__); + return -ENOMEM; + } + txdesc_ring->sdma = virt_to_phys(txdesc_ring->sdesc); + } + + /* + * Allocate TxCmpl ring descriptors + */ + for (i = 0; i < ehw->txcmpl_rings; i++) { + txcmpl_ring = &ehw->txcmpl_ring[i]; + txcmpl_ring->count = IPQ9574_EDMA_TX_RING_SIZE; + txcmpl_ring->id = ehw->txcmpl_ring_start + i; + txcmpl_ring->desc = (void *)noncached_alloc( + IPQ9574_EDMA_TXCMPL_DESC_SIZE * txcmpl_ring->count, + CONFIG_SYS_CACHELINE_SIZE); + + if (txcmpl_ring->desc == NULL) { + pr_info("%s: txcmpl_ring->desc alloc error\n", __func__); + return -ENOMEM; + } + txcmpl_ring->dma = virt_to_phys(txcmpl_ring->desc); + } + + pr_info("%s: successfull\n", __func__); + + return 0; +} + +static void ipq9574_edma_disable_rings(struct ipq9574_edma_hw *edma_hw) +{ + int i, desc_index; + u32 data; + + /* + * Disable Rx rings + */ + for (i = 0; i < IPQ9574_EDMA_MAX_RXDESC_RINGS; i++) { + data = ipq9574_edma_reg_read(IPQ9574_EDMA_REG_RXDESC_CTRL(i)); + data &= ~IPQ9574_EDMA_RXDESC_RX_EN; + ipq9574_edma_reg_write(IPQ9574_EDMA_REG_RXDESC_CTRL(i), data); + } + + /* + * Disable RxFill Rings + */ + for (i = 0; i < IPQ9574_EDMA_MAX_RXFILL_RINGS; i++) { + data = ipq9574_edma_reg_read( + IPQ9574_EDMA_REG_RXFILL_RING_EN(i)); + data &= ~IPQ9574_EDMA_RXFILL_RING_EN; + ipq9574_edma_reg_write( + IPQ9574_EDMA_REG_RXFILL_RING_EN(i), data); + } + + /* + * Disable Tx rings + */ + for (desc_index = 0; desc_index < + IPQ9574_EDMA_MAX_TXDESC_RINGS; desc_index++) { + data = ipq9574_edma_reg_read( + IPQ9574_EDMA_REG_TXDESC_CTRL(desc_index)); + data &= ~IPQ9574_EDMA_TXDESC_TX_EN; + ipq9574_edma_reg_write( + IPQ9574_EDMA_REG_TXDESC_CTRL(desc_index), data); + } +} + +static void ipq9574_edma_disable_intr(struct ipq9574_edma_hw *ehw) +{ + int i; + + /* + * Disable interrupts + */ + for (i = 0; i < IPQ9574_EDMA_MAX_RXDESC_RINGS; i++) + ipq9574_edma_reg_write(IPQ9574_EDMA_REG_RX_INT_CTRL(i), 0); + + for (i = 0; i < IPQ9574_EDMA_MAX_RXFILL_RINGS; i++) + ipq9574_edma_reg_write(IPQ9574_EDMA_REG_RXFILL_INT_MASK(i), 0); + + for (i = 0; i < IPQ9574_EDMA_MAX_TXCMPL_RINGS; i++) + ipq9574_edma_reg_write(IPQ9574_EDMA_REG_TX_INT_MASK(i), 0); + + /* + * Clear MISC interrupt mask + */ + ipq9574_edma_reg_write(IPQ9574_EDMA_REG_MISC_INT_MASK, + IPQ9574_EDMA_MASK_INT_DISABLE); +} + +static void set_sgmii_mode(int port_id, int sg_mode) +{ + if (port_id == 4) + sgmii_mode[0] = sg_mode; + else if (port_id == 5) + sgmii_mode[1] = sg_mode; +} + +static int get_sgmii_mode(int port_id) +{ + if (port_id == 4) + return sgmii_mode[0]; + else if (port_id == 5) + return sgmii_mode[1]; + else + return -1; +} + +static int ipq9574_eth_init(struct eth_device *eth_dev, bd_t *this) +{ + int i; + u8 status = 0; + int mac_speed = 0x0; + struct ipq9574_eth_dev *priv = eth_dev->priv; + struct phy_ops *phy_get_ops; + static fal_port_speed_t old_speed[IPQ9574_PHY_MAX] = {[0 ... IPQ9574_PHY_MAX-1] = FAL_SPEED_BUTT}; + static fal_port_speed_t curr_speed[IPQ9574_PHY_MAX]; + static int current_active_port = -1, previous_active_port = -1; + fal_port_duplex_t duplex; + char *lstatus[] = {"up", "Down"}; + char *dp[] = {"Half", "Full"}; + int linkup = 0; + int clk[4] = {0}; + int phy_addr = -1, node = -1; + int aquantia_port[3] = {-1, -1, -1}, aquantia_port_cnt = -1; + int sfp_port[3] = {-1, -1, -1}, sfp_port_cnt = -1; + int sgmii_mode = -1, sfp_mode = -1, sgmii_fiber = -1; + int phy_node = -1, res = -1; + int uniphy_index = 0; + char *active_port = NULL; + + node = fdt_path_offset(gd->fdt_blob, "/ess-switch"); + + if (node >= 0) { + aquantia_port_cnt = fdtdec_get_uint(gd->fdt_blob, node, "aquantia_port_cnt", -1); + + if (aquantia_port_cnt >= 1) { + res = fdtdec_get_int_array(gd->fdt_blob, node, "aquantia_port", + (u32 *)aquantia_port, aquantia_port_cnt); + if (res < 0) + printf("Error: Aquantia port details not provided in DT\n"); + } + + sfp_port_cnt = fdtdec_get_uint(gd->fdt_blob, node, "sfp_port_cnt", -1); + + if (sfp_port_cnt >= 1) { + res = fdtdec_get_int_array(gd->fdt_blob, node, "sfp_port", + (u32 *)sfp_port, sfp_port_cnt); + if (res < 0) + printf("Error: SFP port details not provided in DT\n"); + } + } + + phy_node = fdt_path_offset(gd->fdt_blob, "/ess-switch/port_phyinfo"); + + active_port = getenv("active_port"); + if (active_port != NULL) { + current_active_port = simple_strtol(active_port, NULL, 10); + if (current_active_port < 0 || current_active_port > 5) + printf("active_port must be in the range of 0 to 5 in ipq9574 platform\n"); + } else { + current_active_port = -1; + } + + if (previous_active_port != current_active_port && current_active_port != -1) { + previous_active_port = current_active_port; + printf("Port%d has been set as the active_port\n", current_active_port); + } + + /* + * Check PHY link, speed, Duplex on all phys. + * we will proceed even if single link is up + * else we will return with -1; + */ + for (i = 0; i < IPQ9574_PHY_MAX; i++) { + /* + * set mdio mode and bus no + */ + ipq_set_mdio_mode(mdio_info[i]->mode, mdio_info[i]->bus_no); + + if (current_active_port != -1 && i != current_active_port) { + ipq9574_gmac_port_disable(i); + ppe_port_bridge_txmac_set(i + 1, 1); + old_speed[i] = FAL_SPEED_BUTT; + /* + * Old speed has been set as FAL_SPEED_BUTT here so that + * if again the previous active_port is made as active, + * the configurations required will be done again and MAC + * would be enabled. + * + * Note that only for the active port TX/RX MAC would be + * enabled and for all other ports, the same would be + * disabled. + */ + continue; + } + if(phy_info[i]->phy_type == UNUSED_PHY_TYPE) + continue; + if (i == sfp_port[0] || i == sfp_port[1] || i == sfp_port[2]) { + status = phy_status_get_from_ppe(i); + duplex = FAL_FULL_DUPLEX; + /* SFP Port can be enabled in USXGMIIx x=0-2i.e + * SFP Port can be port5 or port6 or port0 + * (with port id - 0, 4 or 5). + * Port0 (port id - 0) -> Serdes0 + * Port5 (port id - 4) -> Serdes1 + * Port6 (port id - 5) -> Serdes2 + */ + if (i == 4) { + sfp_mode = fdtdec_get_uint(gd->fdt_blob, node, "switch_mac_mode1", -1); + if (sfp_mode < 0) { + printf("Error: switch_mac_mode1 not specified in dts\n"); + return sfp_mode; + } + } else if (i == 5) { + sfp_mode = fdtdec_get_uint(gd->fdt_blob, node, "switch_mac_mode2", -1); + if (sfp_mode < 0) { + printf("Error: switch_mac_mode2 not specified in dts\n"); + return sfp_mode; + } + } else { + sfp_mode = fdtdec_get_uint(gd->fdt_blob, node, "switch_mac_mode0", -1); + if (sfp_mode < 0) { + printf("Error: switch_mac_mode0 not specified in dts\n"); + return sfp_mode; + } + } + + if (sfp_mode == EPORT_WRAPPER_SGMII_FIBER) { + sgmii_fiber = 1; + curr_speed[i] = FAL_SPEED_1000; + } else if (sfp_mode == EPORT_WRAPPER_10GBASE_R) { + sgmii_fiber = 0; + curr_speed[i] = FAL_SPEED_10000; + } else if (sfp_mode == EPORT_WRAPPER_SGMII_PLUS) { + sgmii_fiber = 0; + curr_speed[i] = FAL_SPEED_2500; + } else { + printf("Error: Wrong mode specified for SFP Port in DT\n"); + return sfp_mode; + } +#ifdef CONFIG_QCA8084_SWT_MODE + } else if ((qca8084_swt_port == i)&& (phy_info[i]->phy_type == QCA8084_PHY_TYPE)) { + if (!ipq_qca8084_link_update(swt_info)) + linkup++; + continue; +#endif /* CONFIG_QCA8084_SWT_MODE */ + } else { + if (!priv->ops[i]) { + printf("Phy ops not mapped\n"); + continue; + } + phy_get_ops = priv->ops[i]; + + if (!phy_get_ops->phy_get_link_status || + !phy_get_ops->phy_get_speed || + !phy_get_ops->phy_get_duplex) { + printf("Error:Link status/Get speed/Get duplex not mapped\n"); + return -1; + } + + if (phy_node >= 0) { + /* + * For each ethernet port, one node should be added + * inside port_phyinfo with appropriate phy address + */ + phy_addr = phy_info[i]->phy_address; + } else { + printf("Error:Phy addresses not configured in DT\n"); + return -1; + } + + status = phy_get_ops->phy_get_link_status(priv->mac_unit, phy_addr); + phy_get_ops->phy_get_speed(priv->mac_unit, phy_addr, &curr_speed[i]); + phy_get_ops->phy_get_duplex(priv->mac_unit, phy_addr, &duplex); + } + + if (status == 0) { + linkup++; + if (old_speed[i] == curr_speed[i]) { + printf("eth%d PHY%d %s Speed :%d %s duplex\n", + priv->mac_unit, i, lstatus[status], curr_speed[i], + dp[duplex]); + continue; + } else { + old_speed[i] = curr_speed[i]; + } + } else { + printf("eth%d PHY%d %s Speed :%d %s duplex\n", + priv->mac_unit, i, lstatus[status], curr_speed[i], + dp[duplex]); + continue; + } + + /* + * Note: If the current port link is up and its speed is + * different from its initially configured speed, only then + * below re-configuration is done. + * + * These conditions are checked above and if any of it + * fails, then no config is done for that eth port. + */ + switch (curr_speed[i]) { + case FAL_SPEED_10: + mac_speed = 0x0; + clk[0] = 0x209; + clk[1] = 0x9; + clk[2] = 0x309; + clk[3] = 0x9; + if (i == aquantia_port[0] || + i == aquantia_port[1] || + i == aquantia_port[2]) { + clk[1] = 0x18; + clk[3] = 0x18; + if (i == 4) { + clk[0] = 0x413; + clk[2] = 0x513; + } else { + clk[0] = 0x213; + clk[2] = 0x313; + } + } + if (phy_node >= 0) { + if (phy_info[i]->phy_type == QCA8081_PHY_TYPE) { + set_sgmii_mode(i, 1); + if (i == 4) { + clk[0] = 0x409; + clk[2] = 0x509; + } +#ifdef CONFIG_QCA8084_PHY_MODE + } else if (phy_info[i]->phy_type == QCA8084_PHY_TYPE) { + clk[0] = 0x213; + clk[1] = 0x18; + clk[2] = 0x313; + clk[3] = 0x18; +#endif /* CONFIG_QCA8084_PHY_MODE */ + } + } + printf("eth%d PHY%d %s Speed :%d %s duplex\n", + priv->mac_unit, i, lstatus[status], curr_speed[i], + dp[duplex]); + break; + case FAL_SPEED_100: + mac_speed = 0x1; + clk[0] = 0x209; + clk[1] = 0x0; + clk[2] = 0x309; + clk[3] = 0x0; + if (i == aquantia_port[0] || + i == aquantia_port[1] || + i == aquantia_port[2] ) { + clk[1] = 0x4; + clk[3] = 0x4; + if (i == 4) { + clk[0] = 0x409; + clk[2] = 0x509; + } + } + if (phy_node >= 0) { + if (phy_info[i]->phy_type == QCA8081_PHY_TYPE) { + set_sgmii_mode(i, 1); + if (i == 4) { + clk[0] = 0x409; + clk[2] = 0x509; + } +#ifdef CONFIG_QCA8084_PHY_MODE + } else if (phy_info[i]->phy_type == QCA8084_PHY_TYPE) { + clk[0] = 0x204; + clk[1] = 0x9; + clk[2] = 0x304; + clk[3] = 0x9; +#endif /* CONFIG_QCA8084_PHY_MODE */ + } + } + printf("eth%d PHY%d %s Speed :%d %s duplex\n", + priv->mac_unit, i, lstatus[status], curr_speed[i], + dp[duplex]); + break; + case FAL_SPEED_1000: + mac_speed = 0x2; + clk[0] = 0x201; + clk[1] = 0x0; + clk[2] = 0x301; + clk[3] = 0x0; + if (i == aquantia_port[0] || + i == aquantia_port[1] || + i == aquantia_port[2] ) { + if (i == 4) { + clk[0] = 0x404; + clk[2] = 0x504; + } else { + clk[0] = 0x204; + clk[2] = 0x304; + } + } else if (i == sfp_port[0] || i == sfp_port[1] + || i == sfp_port[2]) { + if (i == 4) { + clk[0] = 0x401; + clk[2] = 0x501; + } + } + if (phy_node >= 0) { + if (phy_info[i]->phy_type == QCA8081_PHY_TYPE) { + set_sgmii_mode(i, 1); + if (i == 4) { + clk[0] = 0x401; + clk[2] = 0x501; + } +#ifdef CONFIG_QCA8084_PHY_MODE + } else if (phy_info[i]->phy_type == QCA8084_PHY_TYPE) { + clk[0] = 0x204; + clk[2] = 0x304; +#endif /* CONFIG_QCA8084_PHY_MODE */ + } + } + printf("eth%d PHY%d %s Speed :%d %s duplex\n", + priv->mac_unit, i, lstatus[status], curr_speed[i], + dp[duplex]); + break; + case FAL_SPEED_2500: + clk[1] = 0x0; + clk[3] = 0x0; + if (i == aquantia_port[0] || + i == aquantia_port[1] || + i == aquantia_port[2] ) { + mac_speed = 0x4; + if (i == 4) { + clk[0] = 0x407; + clk[2] = 0x507; + } else { + clk[0] = 0x207; + clk[2] = 0x307; + } + } else if (i == sfp_port[0] || i == sfp_port[1] + || i == sfp_port[2]) { + mac_speed = 0x2; + if (i == 4) { + clk[0] = 0x401; + clk[2] = 0x501; + } else { + clk[0] = 0x201; + clk[2] = 0x301; + } + } + if (phy_node >= 0) { + if (phy_info[i]->phy_type == QCA8081_PHY_TYPE) { + mac_speed = 0x2; + set_sgmii_mode(i, 0); + if (i == 4) { + clk[0] = 0x401; + clk[2] = 0x501; + } else { + clk[0] = 0x201; + clk[2] = 0x301; + } +#ifdef CONFIG_QCA8084_PHY_MODE + } else if (phy_info[i]->phy_type == QCA8084_PHY_TYPE) { + mac_speed = 0x4; + clk[0] = 0x207; + clk[2] = 0x307; +#endif /* CONFIG_QCA8084_PHY_MODE */ + } + } + printf("eth%d PHY%d %s Speed :%d %s duplex\n", + priv->mac_unit, i, lstatus[status], curr_speed[i], + dp[duplex]); + break; + case FAL_SPEED_5000: + mac_speed = 0x5; + clk[1] = 0x0; + clk[3] = 0x0; + if (i == 4) { + clk[0] = 0x403; + clk[2] = 0x503; + } else { + clk[0] = 0x203; + clk[2] = 0x303; + } + printf("eth%d PHY%d %s Speed :%d %s duplex\n", + priv->mac_unit, i, lstatus[status], curr_speed[i], + dp[duplex]); + break; + case FAL_SPEED_10000: + mac_speed = 0x3; + clk[1] = 0x0; + clk[3] = 0x0; + if (i == 4) { + clk[0] = 0x401; + clk[2] = 0x501; + } else { + clk[0] = 0x201; + clk[2] = 0x301; + } + printf("eth%d PHY%d %s Speed :%d %s duplex\n", + priv->mac_unit, i, lstatus[status], curr_speed[i], + dp[duplex]); + break; + default: + printf("Unknown speed\n"); + break; + } + + if (phy_node >= 0) { + if (phy_info[i]->phy_type == QCA8081_PHY_TYPE) { + sgmii_mode = get_sgmii_mode(i); + ppe_port_bridge_txmac_set(i + 1, 1); + if (sgmii_mode == 1) { /* SGMII Mode */ + if (i == 4) + ppe_uniphy_mode_set(0x1, EPORT_WRAPPER_SGMII0_RGMII4); + else if (i == 5) + ppe_uniphy_mode_set(0x2, EPORT_WRAPPER_SGMII0_RGMII4); + + } else if (sgmii_mode == 0) { /* SGMII Plus Mode */ + if (i == 4) + ppe_uniphy_mode_set(0x1, EPORT_WRAPPER_SGMII_PLUS); + else if (i == 5) + ppe_uniphy_mode_set(0x2, EPORT_WRAPPER_SGMII_PLUS); + } + } + } + if (i == sfp_port[0] || i == sfp_port[1] || i == sfp_port[2]) { + switch(i) { + case 0: + uniphy_index = 0; + break; + case 4: + uniphy_index = 0x1; + break; + case 5: + uniphy_index = 0x2; + break; + } + if (sgmii_fiber) { /* SGMII Fiber mode */ + ppe_port_bridge_txmac_set(i + 1, 1); + ppe_uniphy_mode_set(uniphy_index, + EPORT_WRAPPER_SGMII_FIBER); + ppe_port_mux_mac_type_set(i + 1, + EPORT_WRAPPER_SGMII_FIBER); + } else if (sfp_mode == EPORT_WRAPPER_10GBASE_R) { /* 10GBASE_R mode */ + ppe_uniphy_mode_set(uniphy_index, + EPORT_WRAPPER_10GBASE_R); + ppe_port_mux_mac_type_set(i + 1, + EPORT_WRAPPER_10GBASE_R); + } else { /* SGMII Plus Mode */ + ppe_port_bridge_txmac_set(i + 1, 1); + ppe_uniphy_mode_set(uniphy_index, + EPORT_WRAPPER_SGMII_PLUS); + } + } + + ipq9574_speed_clock_set(i, clk); + +#ifdef CONFIG_QCA8084_PHY_MODE + if ((qca8084_swt_port != i) && (phy_info[i]->phy_type == QCA8084_PHY_TYPE)) + qca8084_phy_uqxgmii_speed_fixup(phy_info[i]->phy_address, + i + 1, status, curr_speed[i]); +#endif /* CONFIG_QCA8084_PHY_MODE */ + + ipq9574_port_mac_clock_reset(i); + + if (i == aquantia_port[0] || i == aquantia_port[1] || + i == aquantia_port[2] || + ((phy_info[i]->phy_type == QCA8084_PHY_TYPE) && + (qca8084_swt_port != i))) { + ipq9574_uxsgmii_speed_set(i, mac_speed, duplex, status); + } + else if ((i == sfp_port[0] || i == sfp_port[1] || i == sfp_port[2]) && sgmii_fiber == 0) + ipq9574_10g_r_speed_set(i, status); + else + ipq9574_pqsgmii_speed_set(i, mac_speed, status); + } + + if (linkup <= 0) { + /* No PHY link is alive */ + return -1; + } + + pr_info("%s: done\n", __func__); + + return 0; +} + +static int ipq9574_edma_wr_macaddr(struct eth_device *dev) +{ + return 0; +} + +static void ipq9574_eth_halt(struct eth_device *dev) +{ + pr_debug("\n\n*****GMAC0 info*****\n"); + pr_debug("GMAC0 RXPAUSE(0x3a001044):%x\n", readl(0x3a001044)); + pr_debug("GMAC0 TXPAUSE(0x3a0010A4):%x\n", readl(0x3a0010A4)); + pr_debug("GMAC0 RXGOODBYTE_L(0x3a001084):%x\n", readl(0x3a001084)); + pr_debug("GMAC0 RXGOODBYTE_H(0x3a001088):%x\n", readl(0x3a001088)); + pr_debug("GMAC0 RXBADBYTE_L(0x3a00108c):%x\n", readl(0x3a00108c)); + pr_debug("GMAC0 RXBADBYTE_H(0x3a001090):%x\n", readl(0x3a001090)); + + pr_debug("\n\n*****GMAC1 info*****\n"); + pr_debug("GMAC1 RXPAUSE(0x3a001244):%x\n", readl(0x3a001244)); + pr_debug("GMAC1 TXPAUSE(0x3a0012A4):%x\n", readl(0x3a0012A4)); + pr_debug("GMAC1 RXGOODBYTE_L(0x3a001284):%x\n", readl(0x3a001284)); + pr_debug("GMAC1 RXGOODBYTE_H(0x3a001288):%x\n", readl(0x3a001288)); + pr_debug("GMAC1 RXBADBYTE_L(0x3a00128c):%x\n", readl(0x3a00128c)); + pr_debug("GMAC1 RXBADBYTE_H(0x3a001290):%x\n", readl(0x3a001290)); + + pr_debug("\n\n*****GMAC2 info*****\n"); + pr_debug("GMAC2 RXPAUSE(0x3a001444):%x\n", readl(0x3a001444)); + pr_debug("GMAC2 TXPAUSE(0x3a0014A4):%x\n", readl(0x3a0014A4)); + pr_debug("GMAC2 RXGOODBYTE_L(0x3a001484):%x\n", readl(0x3a001484)); + pr_debug("GMAC2 RXGOODBYTE_H(0x3a001488):%x\n", readl(0x3a001488)); + pr_debug("GMAC2 RXBADBYTE_L(0x3a00148c):%x\n", readl(0x3a00148c)); + pr_debug("GMAC2 RXBADBYTE_H(0x3a001490):%x\n", readl(0x3a001490)); + + pr_debug("\n\n*****GMAC3 info*****\n"); + pr_debug("GMAC3 RXPAUSE(0x3a001644):%x\n", readl(0x3a001644)); + pr_debug("GMAC3 TXPAUSE(0x3a0016A4):%x\n", readl(0x3a0016A4)); + pr_debug("GMAC3 RXGOODBYTE_L(0x3a001684):%x\n", readl(0x3a001684)); + pr_debug("GMAC3 RXGOODBYTE_H(0x3a001688):%x\n", readl(0x3a001688)); + pr_debug("GMAC3 RXBADBYTE_L(0x3a00168c):%x\n", readl(0x3a00168c)); + pr_debug("GMAC3 RXBADBYTE_H(0x3a001690):%x\n", readl(0x3a001690)); + pr_info("%s: done\n", __func__); +} + +static void ipq9574_edma_set_ring_values(struct ipq9574_edma_hw *edma_hw) +{ + edma_hw->txdesc_ring_start = IPQ9574_EDMA_TX_DESC_RING_START; + edma_hw->txdesc_rings = IPQ9574_EDMA_TX_DESC_RING_NOS; + edma_hw->txdesc_ring_end = IPQ9574_EDMA_TX_DESC_RING_SIZE; + + edma_hw->txcmpl_ring_start = IPQ9574_EDMA_TX_CMPL_RING_START; + edma_hw->txcmpl_rings = IPQ9574_EDMA_TX_CMPL_RING_NOS; + edma_hw->txcmpl_ring_end = IPQ9574_EDMA_TX_CMPL_RING_SIZE; + + edma_hw->rxfill_ring_start = IPQ9574_EDMA_RX_FILL_RING_START; + edma_hw->rxfill_rings = IPQ9574_EDMA_RX_FILL_RING_NOS; + edma_hw->rxfill_ring_end = IPQ9574_EDMA_RX_FILL_RING_SIZE; + + edma_hw->rxdesc_ring_start = IPQ9574_EDMA_RX_DESC_RING_START; + edma_hw->rxdesc_rings = IPQ9574_EDMA_RX_DESC_RING_NOS; + edma_hw->rxdesc_ring_end = IPQ9574_EDMA_RX_DESC_RING_SIZE; + + pr_info("Num rings - TxDesc:%u (%u-%u) TxCmpl:%u (%u-%u)\n", + edma_hw->txdesc_rings, edma_hw->txdesc_ring_start, + (edma_hw->txdesc_ring_start + edma_hw->txdesc_rings - 1), + edma_hw->txcmpl_rings, edma_hw->txcmpl_ring_start, + (edma_hw->txcmpl_ring_start + edma_hw->txcmpl_rings - 1)); + + pr_info("RxDesc:%u (%u-%u) RxFill:%u (%u-%u)\n", + edma_hw->rxdesc_rings, edma_hw->rxdesc_ring_start, + (edma_hw->rxdesc_ring_start + edma_hw->rxdesc_rings - 1), + edma_hw->rxfill_rings, edma_hw->rxfill_ring_start, + (edma_hw->rxfill_ring_start + edma_hw->rxfill_rings - 1)); +} + +/* + * ipq9574_edma_alloc_rings() + * Allocate EDMA software rings + */ +static int ipq9574_edma_alloc_rings(struct ipq9574_edma_hw *ehw) +{ + ehw->rxfill_ring = (void *)noncached_alloc((sizeof( + struct ipq9574_edma_rxfill_ring) * + ehw->rxfill_rings), + CONFIG_SYS_CACHELINE_SIZE); + if (!ehw->rxfill_ring) { + pr_info("%s: rxfill_ring alloc error\n", __func__); + return -ENOMEM; + } + + ehw->rxdesc_ring = (void *)noncached_alloc((sizeof( + struct ipq9574_edma_rxdesc_ring) * + ehw->rxdesc_rings), + CONFIG_SYS_CACHELINE_SIZE); + if (!ehw->rxdesc_ring) { + pr_info("%s: rxdesc_ring alloc error\n", __func__); + return -ENOMEM; + } + + ehw->txdesc_ring = (void *)noncached_alloc((sizeof( + struct ipq9574_edma_txdesc_ring) * + ehw->txdesc_rings), + CONFIG_SYS_CACHELINE_SIZE); + if (!ehw->txdesc_ring) { + pr_info("%s: txdesc_ring alloc error\n", __func__); + return -ENOMEM; + } + + ehw->txcmpl_ring = (void *)noncached_alloc((sizeof( + struct ipq9574_edma_txcmpl_ring) * + ehw->txcmpl_rings), + CONFIG_SYS_CACHELINE_SIZE); + if (!ehw->txcmpl_ring) { + pr_info("%s: txcmpl_ring alloc error\n", __func__); + return -ENOMEM; + } + + pr_info("%s: successfull\n", __func__); + + return 0; + +} + + +/* + * ipq9574_edma_init_rings() + * Initialize EDMA rings + */ +static int ipq9574_edma_init_rings(struct ipq9574_edma_hw *ehw) +{ + int ret; + + /* + * Setup ring values + */ + ipq9574_edma_set_ring_values(ehw); + + /* + * Allocate desc rings + */ + ret = ipq9574_edma_alloc_rings(ehw); + if (ret) + return ret; + + /* + * Setup ring resources + */ + ret = ipq9574_edma_setup_ring_resources(ehw); + if (ret) + return ret; + + return 0; +} + +/* + * ipq9574_edma_configure_txdesc_ring() + * Configure one TxDesc ring + */ +static void ipq9574_edma_configure_txdesc_ring(struct ipq9574_edma_hw *ehw, + struct ipq9574_edma_txdesc_ring *txdesc_ring) +{ + /* + * Configure TXDESC ring + */ + ipq9574_edma_reg_write(IPQ9574_EDMA_REG_TXDESC_BA(txdesc_ring->id), + (uint32_t)(txdesc_ring->dma & + IPQ9574_EDMA_RING_DMA_MASK)); + + ipq9574_edma_reg_write(IPQ9574_EDMA_REG_TXDESC_BA2(txdesc_ring->id), + (uint32_t)(txdesc_ring->sdma & + IPQ9574_EDMA_RING_DMA_MASK)); + + ipq9574_edma_reg_write(IPQ9574_EDMA_REG_TXDESC_RING_SIZE( + txdesc_ring->id), (uint32_t)(txdesc_ring->count & + IPQ9574_EDMA_TXDESC_RING_SIZE_MASK)); + + ipq9574_edma_reg_write(IPQ9574_EDMA_REG_TXDESC_PROD_IDX( + txdesc_ring->id), + IPQ9574_EDMA_TX_INITIAL_PROD_IDX); +} + +/* + * ipq9574_edma_configure_txcmpl_ring() + * Configure one TxCmpl ring + */ +static void ipq9574_edma_configure_txcmpl_ring(struct ipq9574_edma_hw *ehw, + struct ipq9574_edma_txcmpl_ring *txcmpl_ring) +{ + /* + * Configure TxCmpl ring base address + */ + ipq9574_edma_reg_write(IPQ9574_EDMA_REG_TXCMPL_BA(txcmpl_ring->id), + (uint32_t)(txcmpl_ring->dma & + IPQ9574_EDMA_RING_DMA_MASK)); + + ipq9574_edma_reg_write(IPQ9574_EDMA_REG_TXCMPL_RING_SIZE( + txcmpl_ring->id), (uint32_t)(txcmpl_ring->count & + IPQ9574_EDMA_TXDESC_RING_SIZE_MASK)); + + /* + * Set TxCmpl ret mode to opaque + */ + ipq9574_edma_reg_write(IPQ9574_EDMA_REG_TXCMPL_CTRL(txcmpl_ring->id), + IPQ9574_EDMA_TXCMPL_RETMODE_OPAQUE); + + /* + * Enable ring. Set ret mode to 'opaque'. + */ + ipq9574_edma_reg_write(IPQ9574_EDMA_REG_TX_INT_CTRL(txcmpl_ring->id), + IPQ9574_EDMA_TX_NE_INT_EN); +} + +/* + * ipq9574_edma_configure_rxdesc_ring() + * Configure one RxDesc ring + */ +static void ipq9574_edma_configure_rxdesc_ring(struct ipq9574_edma_hw *ehw, + struct ipq9574_edma_rxdesc_ring *rxdesc_ring) +{ + uint32_t data; + + ipq9574_edma_reg_write(IPQ9574_EDMA_REG_RXDESC_BA(rxdesc_ring->id), + (uint32_t)(rxdesc_ring->dma & IPQ9574_EDMA_RING_DMA_MASK)); + + ipq9574_edma_reg_write(IPQ9574_EDMA_REG_RXDESC_BA2(rxdesc_ring->id), + (uint32_t)(rxdesc_ring->sdma & IPQ9574_EDMA_RING_DMA_MASK)); + + data = rxdesc_ring->count & IPQ9574_EDMA_RXDESC_RING_SIZE_MASK; + data |= (ehw->rx_payload_offset & IPQ9574_EDMA_RXDESC_PL_OFFSET_MASK) << + IPQ9574_EDMA_RXDESC_PL_OFFSET_SHIFT; + + ipq9574_edma_reg_write(IPQ9574_EDMA_REG_RXDESC_RING_SIZE( + rxdesc_ring->id), data); + + /* + * Enable ring. Set ret mode to 'opaque'. + */ + ipq9574_edma_reg_write(IPQ9574_EDMA_REG_RX_INT_CTRL(rxdesc_ring->id), + IPQ9574_EDMA_RX_NE_INT_EN); +} + +/* + * ipq9574_edma_configure_rxfill_ring() + * Configure one RxFill ring + */ +static void ipq9574_edma_configure_rxfill_ring(struct ipq9574_edma_hw *ehw, + struct ipq9574_edma_rxfill_ring *rxfill_ring) +{ + uint32_t data; + + ipq9574_edma_reg_write(IPQ9574_EDMA_REG_RXFILL_BA(rxfill_ring->id), + (uint32_t)(rxfill_ring->dma & IPQ9574_EDMA_RING_DMA_MASK)); + + data = rxfill_ring->count & IPQ9574_EDMA_RXFILL_RING_SIZE_MASK; + + ipq9574_edma_reg_write(IPQ9574_EDMA_REG_RXFILL_RING_SIZE(rxfill_ring->id), data); +} + + +/* + * ipq9574_edma_configure_rings() + * Configure EDMA rings + */ +static void ipq9574_edma_configure_rings(struct ipq9574_edma_hw *ehw) +{ + int i; + + /* + * Configure TXDESC ring + */ + for (i = 0; i < ehw->txdesc_rings; i++) + ipq9574_edma_configure_txdesc_ring(ehw, &ehw->txdesc_ring[i]); + + /* + * Configure TXCMPL ring + */ + for (i = 0; i < ehw->txcmpl_rings; i++) + ipq9574_edma_configure_txcmpl_ring(ehw, &ehw->txcmpl_ring[i]); + + /* + * Configure RXFILL rings + */ + for (i = 0; i < ehw->rxfill_rings; i++) + ipq9574_edma_configure_rxfill_ring(ehw, &ehw->rxfill_ring[i]); + + /* + * Configure RXDESC ring + */ + for (i = 0; i < ehw->rxdesc_rings; i++) + ipq9574_edma_configure_rxdesc_ring(ehw, &ehw->rxdesc_ring[i]); + + pr_info("%s: successfull\n", __func__); +} + +/* + * ipq9574_edma_hw_reset() + * EDMA hw reset + */ +void ipq9574_edma_hw_reset(void) +{ + writel(NSS_CC_EDMA_HW_RESET_ASSERT, NSS_CC_PPE_RESET_ADDR); + mdelay(500); + writel(NSS_CC_EDMA_HW_RESET_DEASSERT, NSS_CC_PPE_RESET_ADDR); + mdelay(100); +} + +/* + * ipq9574_edma_hw_init() + * EDMA hw init + */ +int ipq9574_edma_hw_init(struct ipq9574_edma_hw *ehw) +{ + int ret, desc_index; + uint32_t i, reg, reg_idx, ring_id; + volatile uint32_t data; + + struct ipq9574_edma_rxdesc_ring *rxdesc_ring = NULL; + + ipq9574_ppe_provision_init(); + + data = ipq9574_edma_reg_read(IPQ9574_EDMA_REG_MAS_CTRL); + printf("EDMA ver %d hw init\n", data); + + /* + * Setup private data structure + */ + ehw->rxfill_intr_mask = IPQ9574_EDMA_RXFILL_INT_MASK; + ehw->rxdesc_intr_mask = IPQ9574_EDMA_RXDESC_INT_MASK_PKT_INT; + ehw->txcmpl_intr_mask = IPQ9574_EDMA_TX_INT_MASK_PKT_INT; + ehw->misc_intr_mask = 0xff; + ehw->rx_payload_offset = 0x0; + + /* + * Reset EDMA + */ + ipq9574_edma_hw_reset(); + + /* + * Disable interrupts + */ + ipq9574_edma_disable_intr(ehw); + + /* + * Disable rings + */ + ipq9574_edma_disable_rings(ehw); + + ret = ipq9574_edma_init_rings(ehw); + if (ret) + return ret; + + ipq9574_edma_configure_rings(ehw); + + /* + * Clear the TXDESC2CMPL_MAP_xx reg before setting up + * the mapping. This register holds TXDESC to TXFILL ring + * mapping. + */ + ipq9574_edma_reg_write(IPQ9574_EDMA_REG_TXDESC2CMPL_MAP_0, 0); + ipq9574_edma_reg_write(IPQ9574_EDMA_REG_TXDESC2CMPL_MAP_1, 0); + ipq9574_edma_reg_write(IPQ9574_EDMA_REG_TXDESC2CMPL_MAP_2, 0); + ipq9574_edma_reg_write(IPQ9574_EDMA_REG_TXDESC2CMPL_MAP_3, 0); + ipq9574_edma_reg_write(IPQ9574_EDMA_REG_TXDESC2CMPL_MAP_4, 0); + ipq9574_edma_reg_write(IPQ9574_EDMA_REG_TXDESC2CMPL_MAP_5, 0); + desc_index = ehw->txcmpl_ring_start; + + /* + * 6 registers to hold the completion mapping for total 32 + * TX desc rings (0-5, 6-11, 12-17, 18-23, 24-29 & rest). + * In each entry 5 bits hold the mapping for a particular TX desc ring. + */ + for (i = ehw->txdesc_ring_start; + i < ehw->txdesc_ring_end; i++) { + if ((i >= 0) && (i <= 5)) + reg = IPQ9574_EDMA_REG_TXDESC2CMPL_MAP_0; + else if ((i >= 6) && (i <= 11)) + reg = IPQ9574_EDMA_REG_TXDESC2CMPL_MAP_1; + else if ((i >= 12) && (i <= 17)) + reg = IPQ9574_EDMA_REG_TXDESC2CMPL_MAP_2; + else if ((i >= 18) && (i <= 23)) + reg = IPQ9574_EDMA_REG_TXDESC2CMPL_MAP_3; + else if ((i >= 24) && (i <= 29)) + reg = IPQ9574_EDMA_REG_TXDESC2CMPL_MAP_4; + else + reg = IPQ9574_EDMA_REG_TXDESC2CMPL_MAP_5; + + pr_debug("Configure TXDESC:%u to use TXCMPL:%u\n", + i, desc_index); + + /* + * Set the Tx complete descriptor ring number in the mapping + * register. + * E.g. If (txcmpl ring)desc_index = 31, (txdesc ring)i = 28. + * reg = IPQ9574_EDMA_REG_TXDESC2CMPL_MAP_4 + * data |= (desc_index & 0x1F) << ((i % 6) * 5); + * data |= (0x1F << 20); - This sets 11111 at 20th bit of + * register IPQ9574_EDMA_REG_TXDESC2CMPL_MAP_4 + */ + + data = ipq9574_edma_reg_read(reg); + data |= (desc_index & 0x1F) << ((i % 6) * 5); + ipq9574_edma_reg_write(reg, data); + + desc_index++; + if (desc_index == ehw->txcmpl_ring_end) + desc_index = ehw->txcmpl_ring_start; + } + + pr_debug("EDMA_REG_TXDESC2CMPL_MAP_0: 0x%x\n", + ipq9574_edma_reg_read(IPQ9574_EDMA_REG_TXDESC2CMPL_MAP_0)); + pr_debug("EDMA_REG_TXDESC2CMPL_MAP_1: 0x%x\n", + ipq9574_edma_reg_read(IPQ9574_EDMA_REG_TXDESC2CMPL_MAP_1)); + pr_debug("EDMA_REG_TXDESC2CMPL_MAP_2: 0x%x\n", + ipq9574_edma_reg_read(IPQ9574_EDMA_REG_TXDESC2CMPL_MAP_2)); + pr_debug("EDMA_REG_TXDESC2CMPL_MAP_3: 0x%x\n", + ipq9574_edma_reg_read(IPQ9574_EDMA_REG_TXDESC2CMPL_MAP_3)); + pr_debug("EDMA_REG_TXDESC2CMPL_MAP_4: 0x%x\n", + ipq9574_edma_reg_read(IPQ9574_EDMA_REG_TXDESC2CMPL_MAP_4)); + pr_debug("EDMA_REG_TXDESC2CMPL_MAP_5: 0x%x\n", + ipq9574_edma_reg_read(IPQ9574_EDMA_REG_TXDESC2CMPL_MAP_5)); + + /* + * Set PPE QID to EDMA Rx ring mapping. + * Each entry can hold mapping for 4 PPE queues and entry size is + * 4 bytes + */ + desc_index = (ehw->rxdesc_ring_start & 0x1f); + + reg = IPQ9574_EDMA_QID2RID_TABLE_MEM(0); + data = ((desc_index << 0) & 0xff) | + (((desc_index + 1) << 8) & 0xff00) | + (((desc_index + 2) << 16) & 0xff0000) | + (((desc_index + 3) << 24) & 0xff000000); + + ipq9574_edma_reg_write(reg, data); + pr_debug("Configure QID2RID(0) reg:0x%x to 0x%x\n", reg, data); + + /* + * Map PPE multicast queues to the first Rx ring. + */ + desc_index = (ehw->rxdesc_ring_start & 0x1f); + + for (i = IPQ9574_EDMA_CPU_PORT_MC_QID_MIN; + i <= IPQ9574_EDMA_CPU_PORT_MC_QID_MAX; + i += IPQ9574_EDMA_QID2RID_NUM_PER_REG) { + reg_idx = i/IPQ9574_EDMA_QID2RID_NUM_PER_REG; + + reg = IPQ9574_EDMA_QID2RID_TABLE_MEM(reg_idx); + data = ((desc_index << 0) & 0xff) | + ((desc_index << 8) & 0xff00) | + ((desc_index << 16) & 0xff0000) | + ((desc_index << 24) & 0xff000000); + + ipq9574_edma_reg_write(reg, data); + pr_debug("Configure QID2RID(%d) reg:0x%x to 0x%x\n", + reg_idx, reg, data); + } + + /* + * Set RXDESC2FILL_MAP_xx reg. + * There are 3 registers RXDESC2FILL_0, RXDESC2FILL_1 and RXDESC2FILL_2 + * 3 bits holds the rx fill ring mapping for each of the + * rx descriptor ring. + */ + ipq9574_edma_reg_write(IPQ9574_EDMA_REG_RXDESC2FILL_MAP_0, 0); + ipq9574_edma_reg_write(IPQ9574_EDMA_REG_RXDESC2FILL_MAP_1, 0); + ipq9574_edma_reg_write(IPQ9574_EDMA_REG_RXDESC2FILL_MAP_2, 0); + + for (i = 0; i < ehw->rxdesc_rings; i++) { + rxdesc_ring = &ehw->rxdesc_ring[i]; + + ring_id = rxdesc_ring->id; + if ((ring_id >= 0) && (ring_id <= 9)) + reg = IPQ9574_EDMA_REG_RXDESC2FILL_MAP_0; + else if ((ring_id >= 10) && (ring_id <= 19)) + reg = IPQ9574_EDMA_REG_RXDESC2FILL_MAP_1; + else + reg = IPQ9574_EDMA_REG_RXDESC2FILL_MAP_2; + + + pr_debug("Configure RXDESC:%u to use RXFILL:%u\n", + ring_id, rxdesc_ring->rxfill->id); + + /* + * Set the Rx fill descriptor ring number in the mapping + * register. + */ + data = ipq9574_edma_reg_read(reg); + data |= (rxdesc_ring->rxfill->id & 0x7) << ((ring_id % 10) * 3); + ipq9574_edma_reg_write(reg, data); + } + + pr_debug("EDMA_REG_RXDESC2FILL_MAP_0: 0x%x\n", + ipq9574_edma_reg_read(IPQ9574_EDMA_REG_RXDESC2FILL_MAP_0)); + pr_debug("EDMA_REG_RXDESC2FILL_MAP_1: 0x%x\n", + ipq9574_edma_reg_read(IPQ9574_EDMA_REG_RXDESC2FILL_MAP_1)); + pr_debug("EDMA_REG_RXDESC2FILL_MAP_2: 0x%x\n", + ipq9574_edma_reg_read(IPQ9574_EDMA_REG_RXDESC2FILL_MAP_2)); + + /* + * Configure DMA request priority, DMA read burst length, + * and AXI write size. + */ + data = IPQ9574_EDMA_DMAR_BURST_LEN_SET(IPQ9574_EDMA_BURST_LEN_ENABLE) + | IPQ9574_EDMA_DMAR_REQ_PRI_SET(0) + | IPQ9574_EDMA_DMAR_TXDATA_OUTSTANDING_NUM_SET(31) + | IPQ9574_EDMA_DMAR_TXDESC_OUTSTANDING_NUM_SET(7) + | IPQ9574_EDMA_DMAR_RXFILL_OUTSTANDING_NUM_SET(7); + ipq9574_edma_reg_write(IPQ9574_EDMA_REG_DMAR_CTRL, data); + + /* + * Global EDMA and padding enable + */ + ipq9574_edma_reg_write(IPQ9574_EDMA_REG_PORT_CTRL, + IPQ9574_EDMA_PORT_CTRL_EN); + + /* + * Enable Rx rings + */ + for (i = ehw->rxdesc_ring_start; i < ehw->rxdesc_ring_end; i++) { + data = ipq9574_edma_reg_read(IPQ9574_EDMA_REG_RXDESC_CTRL(i)); + data |= IPQ9574_EDMA_RXDESC_RX_EN; + ipq9574_edma_reg_write(IPQ9574_EDMA_REG_RXDESC_CTRL(i), data); + } + + for (i = ehw->rxfill_ring_start; i < ehw->rxfill_ring_end; i++) { + data = ipq9574_edma_reg_read(IPQ9574_EDMA_REG_RXFILL_RING_EN(i)); + data |= IPQ9574_EDMA_RXFILL_RING_EN; + ipq9574_edma_reg_write(IPQ9574_EDMA_REG_RXFILL_RING_EN(i), data); + } + + /* + * Enable Tx rings + */ + for (i = ehw->txdesc_ring_start; i < ehw->txdesc_ring_end; i++) { + data = ipq9574_edma_reg_read(IPQ9574_EDMA_REG_TXDESC_CTRL(i)); + data |= IPQ9574_EDMA_TXDESC_TX_EN; + ipq9574_edma_reg_write(IPQ9574_EDMA_REG_TXDESC_CTRL(i), data); + } + + /* + * Enable MISC interrupt mask + */ + ipq9574_edma_reg_write(IPQ9574_EDMA_REG_MISC_INT_MASK, + ehw->misc_intr_mask); + + pr_info("%s: successfull\n", __func__); + return 0; +} + +void get_phy_address(int offset, phy_info_t * phy_info[]) +{ + int phy_type; + int phy_address; + int forced_speed, forced_duplex; + int i; + + for (i = 0; i < IPQ9574_PHY_MAX; i++) + phy_info[i] = ipq9574_alloc_mem(sizeof(phy_info_t)); + i = 0; + for (offset = fdt_first_subnode(gd->fdt_blob, offset); offset > 0; + offset = fdt_next_subnode(gd->fdt_blob, offset)) { + phy_address = fdtdec_get_uint(gd->fdt_blob, + offset, "phy_address", 0); + phy_type = fdtdec_get_uint(gd->fdt_blob, + offset, "phy_type", 0); + forced_speed = fdtdec_get_uint(gd->fdt_blob, + offset, "forced-speed", 0); + forced_duplex = fdtdec_get_uint(gd->fdt_blob, + offset, "forced-duplex", 0); + phy_info[i]->phy_address = phy_address; + phy_info[i]->forced_speed = forced_speed; + phy_info[i]->forced_duplex = forced_duplex; + phy_info[i++]->phy_type = phy_type; + } +} + +void get_mdio_info(int offset, mdio_info_t * mdio_info[]) +{ + int mode; + int bus_no; + int i; + + for (i = 0; i < IPQ9574_PHY_MAX; i++) + mdio_info[i] = ipq9574_alloc_mem(sizeof(mdio_info_t)); + i = 0; + for (offset = fdt_first_subnode(gd->fdt_blob, offset); offset > 0; + offset = fdt_next_subnode(gd->fdt_blob, offset)) { + mode = fdtdec_get_uint(gd->fdt_blob, + offset, "mdio_mode", 0); + bus_no = fdtdec_get_uint(gd->fdt_blob, + offset, "bus_no", 0); + mdio_info[i]->mode = mode; + mdio_info[i]->bus_no = bus_no; + ++i; + } +} + +int ipq9574_edma_init(void *edma_board_cfg) +{ + struct eth_device *dev[IPQ9574_EDMA_DEV]; + char octets[16]; + int field0, field1; + struct ipq9574_edma_common_info *c_info[IPQ9574_EDMA_DEV]; + struct ipq9574_edma_hw *hw[IPQ9574_EDMA_DEV]; + uchar enet_addr[IPQ9574_EDMA_DEV * 6]; + int i; + int ret = -1; + ipq9574_edma_board_cfg_t ledma_cfg, *edma_cfg; + int phy_id; + uint32_t phy_chip_id, phy_chip_id1, phy_chip_id2; +#ifdef CONFIG_IPQ9574_QCA8075_PHY + static int sw_init_done = 0; +#endif +#ifdef CONFIG_QCA8084_PHY + static int qca8084_init_done = 0; + int phy_type; +#ifdef CONFIG_QCA8084_SWT_MODE + int qca8084_gpio, swt_node = -1, clk[4] = {0}; +#endif /* CONFIG_QCA8084_SWT_MODE */ +#endif + int node, phy_addr, mode, phy_node = -1, res = -1; + int aquantia_port[3] = {-1, -1, -1}, aquantia_port_cnt = -1; + + /* + * Init non cache buffer + */ + noncached_init(); + + node = fdt_path_offset(gd->fdt_blob, "/ess-switch"); + + if (node >= 0) { + aquantia_port_cnt = fdtdec_get_uint(gd->fdt_blob, node, "aquantia_port_cnt", -1); + + if (aquantia_port_cnt >= 1) { + res = fdtdec_get_int_array(gd->fdt_blob, node, "aquantia_port", + (u32 *)aquantia_port, aquantia_port_cnt); + if (res < 0) + printf("Error: Aquantia port details not provided in DT"); + } + } + +#ifdef CONFIG_QCA8084_SWT_MODE + qca8084_swt_port = fdtdec_get_uint(gd->fdt_blob, node, "qca8084_swt_port", -1); + qca8084_gpio = fdtdec_get_uint(gd->fdt_blob, node, "qca808x_gpio", 0); + if (qca8084_swt_port != -1) { + if (qca8084_gpio) + ipq_qca8084_switch_hw_reset(qca8084_gpio); + } + + swt_node = fdt_path_offset(gd->fdt_blob, "/ess-switch/qca8084_swt_info"); + if (swt_node >= 0) + get_phy_address(swt_node, swt_info); +#endif + + phy_node = fdt_path_offset(gd->fdt_blob, "/ess-switch/port_phyinfo"); + if (phy_node >= 0) { + get_phy_address(phy_node, phy_info); + } + + phy_node = fdt_path_offset(gd->fdt_blob, "/ess-switch/port_phyinfo"); + if (phy_node >= 0) { + get_mdio_info(phy_node, mdio_info); + } + + mode = fdtdec_get_uint(gd->fdt_blob, node, "switch_mac_mode0", -1); + if (mode < 0) { + printf("Error:switch_mac_mode0 not specified in dts"); + return mode; + } + + memset(c_info, 0, (sizeof(c_info) * IPQ9574_EDMA_DEV)); + memset(enet_addr, 0, sizeof(enet_addr)); + memset(&ledma_cfg, 0, sizeof(ledma_cfg)); + edma_cfg = &ledma_cfg; + strlcpy(edma_cfg->phy_name, "IPQ MDIO0", sizeof(edma_cfg->phy_name)); + + /* Getting the MAC address from ART partition */ + ret = get_eth_mac_address(enet_addr, IPQ9574_EDMA_DEV); + + /* + * Register EDMA as single ethernet + * interface. + */ + for (i = 0; i < IPQ9574_EDMA_DEV; edma_cfg++, i++) { + dev[i] = ipq9574_alloc_mem(sizeof(struct eth_device)); + + if (!dev[i]) + goto init_failed; + + memset(dev[i], 0, sizeof(struct eth_device)); + + c_info[i] = ipq9574_alloc_mem( + sizeof(struct ipq9574_edma_common_info)); + + if (!c_info[i]) + goto init_failed; + + memset(c_info[i], 0, + sizeof(struct ipq9574_edma_common_info)); + + hw[i] = &c_info[i]->hw; + + c_info[i]->hw.hw_addr = (unsigned long __iomem *) + IPQ9574_EDMA_CFG_BASE; + + ipq9574_edma_dev[i] = ipq9574_alloc_mem( + sizeof(struct ipq9574_eth_dev)); + + if (!ipq9574_edma_dev[i]) + goto init_failed; + + memset (ipq9574_edma_dev[i], 0, + sizeof(struct ipq9574_eth_dev)); + + dev[i]->iobase = IPQ9574_EDMA_CFG_BASE; + dev[i]->init = ipq9574_eth_init; + dev[i]->halt = ipq9574_eth_halt; + dev[i]->recv = ipq9574_eth_recv; + dev[i]->send = ipq9574_eth_snd; + dev[i]->write_hwaddr = ipq9574_edma_wr_macaddr; + dev[i]->priv = (void *)ipq9574_edma_dev[i]; + + if ((ret < 0) || + (!is_valid_ethaddr(&enet_addr[edma_cfg->unit * 6]))) { + memcpy(&dev[i]->enetaddr[0], ipq9574_def_enetaddr, 6); + } else { + memcpy(&dev[i]->enetaddr[0], + &enet_addr[edma_cfg->unit * 6], 6); + } + + printf("MAC%x addr:%x:%x:%x:%x:%x:%x\n", + edma_cfg->unit, dev[i]->enetaddr[0], + dev[i]->enetaddr[1], + dev[i]->enetaddr[2], + dev[i]->enetaddr[3], + dev[i]->enetaddr[4], + dev[i]->enetaddr[5]); + + snprintf(octets, sizeof(octets), "%x%x", + dev[i]->enetaddr[0], dev[i]->enetaddr[1]); + field0 = simple_strtoul(octets, NULL, 16); + snprintf(octets, sizeof(octets), "%x%x%x%x", + dev[i]->enetaddr[2], dev[i]->enetaddr[3], + dev[i]->enetaddr[4], dev[i]->enetaddr[5]); + field1 = simple_strtoul(octets, NULL, 16); + + /* Drop packets with DUT's mac addr */ + ipq9574_ppe_acl_set(4, 0x1, field0, field1, 0xffffffff, 0x0, 0x1); + + snprintf(dev[i]->name, sizeof(dev[i]->name), "eth%d", i); + + ipq9574_edma_dev[i]->dev = dev[i]; + ipq9574_edma_dev[i]->mac_unit = edma_cfg->unit; + ipq9574_edma_dev[i]->c_info = c_info[i]; + ipq9574_edma_hw_addr = IPQ9574_EDMA_CFG_BASE; + + ret = ipq_sw_mdio_init(edma_cfg->phy_name); + if (ret) + goto init_failed; + + for (phy_id = 0; phy_id < IPQ9574_PHY_MAX; phy_id++) { + + ipq_set_mdio_mode(mdio_info[phy_id]->mode, + mdio_info[phy_id]->bus_no); + + if(phy_info[phy_id]->phy_type == UNUSED_PHY_TYPE) + continue; + + if (phy_node >= 0) { + phy_addr = phy_info[phy_id]->phy_address; +#ifdef CONFIG_QCA8084_PHY + phy_type = phy_info[phy_id]->phy_type; +#endif + } else { + printf("Error:Phy addresses not configured in DT\n"); + goto init_failed; + } +#ifdef CONFIG_QCA8084_PHY + if (phy_type == QCA8084_PHY_TYPE) { + if ((qca8084_swt_port == phy_id) || + !qca8084_init_done) { + ipq_phy_addr_fixup(); + ipq_clock_init(); + if (qca8084_swt_port != phy_id) + qca8084_init_done = 1; + } + } +#endif + + phy_chip_id1 = ipq_mdio_read(phy_addr, QCA_PHY_ID1, NULL); + phy_chip_id2 = ipq_mdio_read(phy_addr, QCA_PHY_ID2, NULL); + phy_chip_id = (phy_chip_id1 << 16) | phy_chip_id2; + if (phy_id == aquantia_port[0] || + phy_id == aquantia_port[1] || + phy_id == aquantia_port[2]) { + phy_chip_id1 = ipq_mdio_read(phy_addr, (1<<30) |(1<<16) | QCA_PHY_ID1, NULL); + phy_chip_id2 = ipq_mdio_read(phy_addr, (1<<30) |(1<<16) | QCA_PHY_ID2, NULL); + phy_chip_id = (phy_chip_id1 << 16) | phy_chip_id2; + } + pr_debug("phy_id is: 0x%x, phy_addr = 0x%x, phy_chip_id1 = 0x%x, phy_chip_id2 = 0x%x, phy_chip_id = 0x%x\n", + phy_id, phy_addr, phy_chip_id1, phy_chip_id2, phy_chip_id); + switch(phy_chip_id) { +#ifdef CONFIG_IPQ9574_QCA8075_PHY + case QCA8075_PHY_V1_0_5P: + case QCA8075_PHY_V1_1_5P: + case QCA8075_PHY_V1_1_2P: + if (!sw_init_done) { + if (ipq9574_qca8075_phy_init(&ipq9574_edma_dev[i]->ops[phy_id], phy_addr) == 0) { + sw_init_done = 1; + } + } else { + ipq9574_qca8075_phy_map_ops(&ipq9574_edma_dev[i]->ops[phy_id]); + } + + if (mode == EPORT_WRAPPER_PSGMII) + ipq9574_qca8075_phy_interface_set_mode(phy_addr, 0x0); + else if (mode == EPORT_WRAPPER_QSGMII) + ipq9574_qca8075_phy_interface_set_mode(phy_addr, 0x4); + break; +#endif +#ifdef CONFIG_QCA8033_PHY + case QCA8033_PHY: + ipq_qca8033_phy_init(&ipq9574_edma_dev[i]->ops[phy_id], phy_addr); + break; +#endif +#ifdef CONFIG_QCA8081_PHY + case QCA8081_PHY: + case QCA8081_1_1_PHY: + ipq_qca8081_phy_init(&ipq9574_edma_dev[i]->ops[phy_id], phy_addr); + break; +#endif +#ifdef CONFIG_QCA8084_PHY_MODE + case QCA8084_PHY: + if (qca8084_swt_port != phy_id) + ipq_qca8084_phy_hw_init(&ipq9574_edma_dev[i]->ops[phy_id], phy_addr); + break; +#endif +#ifdef CONFIG_IPQ9574_QCA_AQUANTIA_PHY + case AQUANTIA_PHY_107: + case AQUANTIA_PHY_109: + case AQUANTIA_PHY_111: + case AQUANTIA_PHY_111B0: + case AQUANTIA_PHY_112: + case AQUANTIA_PHY_112C: + case AQUANTIA_PHY_113C_A0: + case AQUANTIA_PHY_113C_A1: + case AQUANTIA_PHY_113C_B0: + case AQUANTIA_PHY_113C_B1: + ipq_board_fw_download(phy_addr); + mdelay(100); + ipq_qca_aquantia_phy_init(&ipq9574_edma_dev[i]->ops[phy_id], phy_addr); + break; +#endif +#ifdef CONFIG_TP_EXT_PHY_RTL8251B + case RTL8251B_PHY: + rtl8251b_init(&ipq9574_edma_dev[i]->ops[phy_id], phy_addr); + break; +#endif +#ifdef CONFIG_TP_EXT_PHY_RTL8261B + case RTL8261B_PHY: + printf("Loading RTL8261BE PHY_ID:%d... \n",phy_addr); + rtl8261_phy_init(&ipq9574_edma_dev[i]->ops[phy_id], phy_addr); + break; +#endif + default: + if (phy_info[phy_id]->phy_type != SFP_PHY_TYPE) + pr_debug("\nphy chip id: 0x%x id not matching for phy id: 0x%x with phy_type: 0x%x and phy address: 0x%x", + phy_chip_id, phy_id, phy_info[phy_id]->phy_type, phy_info[phy_id]->phy_address); + break; + } + } + + ret = ipq9574_edma_hw_init(hw[i]); + + if (ret) + goto init_failed; + +#ifdef CONFIG_QCA8084_SWT_MODE + /** QCA8084 switch specific configurations */ + if (qca8084_swt_port != -1) { + ipq_set_mdio_mode(mdio_info[qca8084_swt_port]->mode, + mdio_info[qca8084_swt_port]->bus_no); + /** Force speed alder 1st port for QCA8084 switch mode */ + switch (swt_info[0]->forced_speed) { + case FAL_SPEED_1000: + case FAL_SPEED_2500: + if (qca8084_swt_port == 4) { + clk[0] = 0x401; + clk[1] = 0x0; + clk[2] = 0x501; + clk[3] = 0x0; + } else { + clk[0] = 0x201; + clk[1] = 0x0; + clk[2] = 0x301; + clk[3] = 0x0; + } + pr_debug("Force speed Alder 1st PORT for QCA8084 switch mode \n"); + ipq9574_speed_clock_set( + qca8084_swt_port, clk); + + /** Force Link-speed: 1000M + * Force Link-status: enable */ + ipq9574_pqsgmii_speed_set( + qca8084_swt_port, + 0x2, 0x0); + break; + + default: + printf("Error: Unsupported speed configuraiton for QCA8084 switch \n"); + break; + } + + ret = ipq_qca8084_hw_init(swt_info); + if (ret < 0) { + printf("Error: ipq_qca8084_hw_init failed \n"); + qca8084_swt_port = -1; + } + } +#endif + + eth_register(dev[i]); + } + + return 0; + +init_failed: + printf("Error in allocating Mem\n"); + + for (i = 0; i < IPQ9574_EDMA_DEV; i++) { + if (dev[i]) { + eth_unregister(dev[i]); + ipq9574_free_mem(dev[i]); + } + if (c_info[i]) { + ipq9574_free_mem(c_info[i]); + } + if (ipq9574_edma_dev[i]) { + ipq9574_free_mem(ipq9574_edma_dev[i]); + } + } + + return -1; +} diff --git a/sources/uboot-be550/drivers/net/ipq9574/ipq9574_edma.h b/sources/uboot-be550/drivers/net/ipq9574/ipq9574_edma.h new file mode 100644 index 00000000..baef2c8f --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq9574/ipq9574_edma.h @@ -0,0 +1,340 @@ +/* + ************************************************************************** + * Copyright (c) 2016-2019, 2021, The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + ************************************************************************** +*/ +#ifndef __IPQ9574_EDMA__ +#define __IPQ9574_EDMA__ + +#define IPQ9574_NSS_DP_START_PHY_PORT 1 +#define IPQ9574_NSS_DP_MAX_PHY_PORTS 6 + +#define IPQ9574_EDMA_DEVICE_NODE_NAME "edma" + +/* Number of descriptors in each ring is defined with below macro */ +#define IPQ9574_EDMA_TX_RING_SIZE 128 +#define IPQ9574_EDMA_RX_RING_SIZE 128 + +/* Number of byte in a descriptor is defined with below macros for each of + * the rings respectively */ +#define IPQ9574_EDMA_TXDESC_DESC_SIZE (sizeof(struct ipq9574_edma_txdesc_desc)) +#define IPQ9574_EDMA_TXCMPL_DESC_SIZE (sizeof(struct ipq9574_edma_txcmpl_desc)) +#define IPQ9574_EDMA_RXDESC_DESC_SIZE (sizeof(struct ipq9574_edma_rxdesc_desc)) +#define IPQ9574_EDMA_RXFILL_DESC_SIZE (sizeof(struct ipq9574_edma_rxfill_desc)) +#define IPQ9574_EDMA_RX_SEC_DESC_SIZE (sizeof(struct ipq9574_edma_rx_sec_desc)) +#define IPQ9574_EDMA_TX_SEC_DESC_SIZE (sizeof(struct ipq9574_edma_tx_sec_desc)) + +#define IPQ9574_EDMA_START_GMACS IPQ9574_NSS_DP_START_PHY_PORT +#define IPQ9574_EDMA_MAX_GMACS IPQ9574_NSS_DP_MAX_PHY_PORTS + +#define IPQ9574_EDMA_TX_BUFF_SIZE 2048 +#define IPQ9574_EDMA_RX_BUFF_SIZE 2048 + +/* Max number of rings of each type is defined with below macro */ +#define IPQ9574_EDMA_MAX_TXCMPL_RINGS 32 /* Max TxCmpl rings */ +#define IPQ9574_EDMA_MAX_TXDESC_RINGS 32 /* Max TxDesc rings */ +#define IPQ9574_EDMA_MAX_RXDESC_RINGS 24 /* Max RxDesc rings */ +#define IPQ9574_EDMA_MAX_RXFILL_RINGS 8 /* Max RxFill rings */ + +#define IPQ9574_EDMA_GET_DESC(R, i, type) (&(((type *)((R)->desc))[i])) +#define IPQ9574_EDMA_RXFILL_DESC(R, i) IPQ9574_EDMA_GET_DESC(R, i, struct ipq9574_edma_rxfill_desc) +#define IPQ9574_EDMA_RXDESC_DESC(R, i) IPQ9574_EDMA_GET_DESC(R, i, struct ipq9574_edma_rxdesc_desc) +#define IPQ9574_EDMA_TXDESC_DESC(R, i) IPQ9574_EDMA_GET_DESC(R, i, struct ipq9574_edma_txdesc_desc) +#define IPQ9574_EDMA_TXCMPL_DESC(R, i) IPQ9574_EDMA_GET_DESC(R, i, struct ipq9574_edma_txcmpl_desc) + +#define IPQ9574_EDMA_DEV 1 + +/* Only 1 ring of each type will be used in U-Boot which is defined with + * below macros */ +#define IPQ9574_EDMA_TX_DESC_RING_START 0 +#define IPQ9574_EDMA_TX_DESC_RING_NOS 1 +#define IPQ9574_EDMA_TX_DESC_RING_SIZE \ +(IPQ9574_EDMA_TX_DESC_RING_START + IPQ9574_EDMA_TX_DESC_RING_NOS) + +#define IPQ9574_EDMA_TX_CMPL_RING_START 0 +#define IPQ9574_EDMA_TX_CMPL_RING_NOS 1 +#define IPQ9574_EDMA_TX_CMPL_RING_SIZE \ +(IPQ9574_EDMA_TX_CMPL_RING_START + IPQ9574_EDMA_TX_CMPL_RING_NOS) + +#define IPQ9574_EDMA_RX_DESC_RING_START 0 +#define IPQ9574_EDMA_RX_DESC_RING_NOS 1 +#define IPQ9574_EDMA_RX_DESC_RING_SIZE \ +(IPQ9574_EDMA_RX_DESC_RING_START + IPQ9574_EDMA_RX_DESC_RING_NOS) + +#define IPQ9574_EDMA_RX_FILL_RING_START 0 +#define IPQ9574_EDMA_RX_FILL_RING_NOS 1 +#define IPQ9574_EDMA_RX_FILL_RING_SIZE \ +(IPQ9574_EDMA_RX_FILL_RING_START + IPQ9574_EDMA_RX_FILL_RING_NOS) + +#define NETDEV_TX_BUSY 1 + +/* + * RxDesc descriptor + */ +struct ipq9574_edma_rxdesc_desc { + uint32_t rdes0; /* Contains buffer address */ + uint32_t rdes1; /* Contains more bit, priority bit, service code */ + uint32_t rdes2; /* Contains opaque */ + uint32_t rdes3; /* Contains opaque high bits */ + uint32_t rdes4; /* Contains destination and source information */ + uint32_t rdes5; /* Contains WiFi QoS, data length */ + uint32_t rdes6; /* Contains hash value, check sum status */ + uint32_t rdes7; /* Contains DSCP, packet offsets */ +}; + +/* + * EDMA Rx Secondary Descriptor + */ +struct ipq9574_edma_rx_sec_desc { + uint32_t rx_sec0; /* Contains timestamp */ + uint32_t rx_sec1; /* Contains secondary checksum status */ + uint32_t rx_sec2; /* Contains QoS tag */ + uint32_t rx_sec3; /* Contains flow index details */ + uint32_t rx_sec4; /* Contains secondary packet offsets */ + uint32_t rx_sec5; /* Contains multicast bit, checksum */ + uint32_t rx_sec6; /* Contains SVLAN, CVLAN */ + uint32_t rx_sec7; /* Contains secondary SVLAN, CVLAN */ +}; + +/* + * RxFill descriptor + */ +struct ipq9574_edma_rxfill_desc { + uint32_t rdes0; /* Contains buffer address */ + uint32_t rdes1; /* Contains buffer size */ + uint32_t rdes2; /* Contains opaque */ + uint32_t rdes3; /* Contains opaque high bits */ +}; + +/* + * TxDesc descriptor + */ +struct ipq9574_edma_txdesc_desc { + uint32_t tdes0; /* Low 32-bit of buffer address */ + uint32_t tdes1; /* Buffer recycling, PTP tag flag, PRI valid flag */ + uint32_t tdes2; /* Low 32-bit of opaque value */ + uint32_t tdes3; /* High 32-bit of opaque value */ + uint32_t tdes4; /* Source/Destination port info */ + uint32_t tdes5; /* VLAN offload, csum_mode, ip_csum_en, tso_en, data length */ + uint32_t tdes6; /* MSS/hash_value/PTP tag, data offset */ + uint32_t tdes7; /* L4/L3 offset, PROT type, L2 type, CVLAN/SVLAN tag, service code */ +}; + +/* + * EDMA Tx Secondary Descriptor + */ +struct ipq9574_edma_tx_sec_desc { + uint32_t tx_sec0; /* Reserved */ + uint32_t tx_sec1; /* Custom csum offset, payload offset, TTL/NAT action */ + uint32_t rx_sec2; /* NAPT translated port, DSCP value, TTL value */ + uint32_t rx_sec3; /* Flow index value and valid flag */ + uint32_t rx_sec4; /* Reserved */ + uint32_t rx_sec5; /* Reserved */ + uint32_t rx_sec6; /* CVLAN/SVLAN command */ + uint32_t rx_sec7; /* CVLAN/SVLAN tag value */ +}; + +/* + * TxCmpl descriptor + */ +struct ipq9574_edma_txcmpl_desc { + uint32_t tdes0; /* Low 32-bit opaque value */ + uint32_t tdes1; /* High 32-bit opaque value */ + uint32_t tdes2; /* More fragment, transmit ring id, pool id */ + uint32_t tdes3; /* Error indications */ +}; + +/* + * Tx descriptor ring + */ +struct ipq9574_edma_txdesc_ring { + uint32_t prod_idx; /* Producer index */ + uint32_t avail_desc; /* Number of available descriptor to process */ + uint32_t id; /* TXDESC ring number */ + struct ipq9574_edma_txdesc_desc *desc; /* descriptor ring virtual address */ + dma_addr_t dma; /* descriptor ring physical address */ + struct ipq9574_edma_tx_sec_desc *sdesc; /* Secondary descriptor ring virtual addr */ + dma_addr_t sdma; /* Secondary descriptor ring physical address */ + uint16_t count; /* number of descriptors */ +}; + +/* + * TxCmpl ring + */ +struct ipq9574_edma_txcmpl_ring { + uint32_t cons_idx; /* Consumer index */ + uint32_t avail_pkt; /* Number of available packets to process */ + struct ipq9574_edma_txcmpl_desc *desc; /* descriptor ring virtual address */ + uint32_t id; /* TXCMPL ring number */ + dma_addr_t dma; /* descriptor ring physical address */ + uint32_t count; /* Number of descriptors in the ring */ +}; + +/* + * RxFill ring + */ +struct ipq9574_edma_rxfill_ring { + uint32_t id; /* RXFILL ring number */ + uint32_t count; /* number of descriptors in the ring */ + uint32_t prod_idx; /* Ring producer index */ + struct ipq9574_edma_rxfill_desc *desc; /* descriptor ring virtual address */ + dma_addr_t dma; /* descriptor ring physical address */ +}; + +/* + * RxDesc ring + */ +struct ipq9574_edma_rxdesc_ring { + uint32_t id; /* RXDESC ring number */ + uint32_t count; /* number of descriptors in the ring */ + uint32_t cons_idx; /* Ring consumer index */ + struct ipq9574_edma_rxdesc_desc *desc; /* Primary descriptor ring virtual addr */ + struct ipq9574_edma_sec_rxdesc_ring *sdesc; /* Secondary desc ring VA */ + struct ipq9574_edma_rxfill_ring *rxfill; /* RXFILL ring used */ + dma_addr_t dma; /* Primary descriptor ring physical address */ + dma_addr_t sdma; /* Secondary descriptor ring physical address */ +}; + +enum ipq9574_edma_tx { + EDMA_TX_OK = 0, /* Tx success */ + EDMA_TX_DESC = 1, /* Not enough descriptors */ + EDMA_TX_FAIL = 2, /* Tx failure */ +}; + + +/* per core queue related information */ +struct queue_per_cpu_info { + u32 tx_mask; /* tx interrupt mask */ + u32 rx_mask; /* rx interrupt mask */ + u32 tx_status; /* tx interrupt status */ + u32 rx_status; /* rx interrupt status */ + u32 tx_start; /* tx queue start */ + u32 rx_start; /* rx queue start */ + struct ipq9574_edma_common_info *c_info; /* edma common info */ +}; + +/* edma hw specific data */ +struct ipq9574_edma_hw { + unsigned long __iomem *hw_addr; /* inner register address */ + u8 intr_clear_type; /* interrupt clear */ + u8 intr_sw_idx_w; /* To do chk type interrupt software index */ + u16 rx_buff_size; /* To do chk type Rx buffer size */ + u8 rss_type; /* rss protocol type */ + uint16_t rx_payload_offset; /* start of the payload offset */ + uint32_t flags; /* internal flags */ + int active; /* status */ + struct ipq9574_edma_txdesc_ring *txdesc_ring; /* Tx Descriptor Ring, SW is producer */ + struct ipq9574_edma_txcmpl_ring *txcmpl_ring; /* Tx Completion Ring, SW is consumer */ + struct ipq9574_edma_rxdesc_ring *rxdesc_ring; /* Rx Descriptor Ring, SW is consumer */ + struct ipq9574_edma_rxfill_ring *rxfill_ring; /* Rx Fill Ring, SW is producer */ + uint32_t txdesc_rings; /* Number of TxDesc rings */ + uint32_t txdesc_ring_start; /* Id of first TXDESC ring */ + uint32_t txdesc_ring_end; /* Id of the last TXDESC ring */ + uint32_t txcmpl_rings; /* Number of TxCmpl rings */ + uint32_t txcmpl_ring_start; /* Id of first TXCMPL ring */ + uint32_t txcmpl_ring_end; /* Id of last TXCMPL ring */ + uint32_t rxfill_rings; /* Number of RxFill rings */ + uint32_t rxfill_ring_start; /* Id of first RxFill ring */ + uint32_t rxfill_ring_end; /* Id of last RxFill ring */ + uint32_t rxdesc_rings; /* Number of RxDesc rings */ + uint32_t rxdesc_ring_start; /* Id of first RxDesc ring */ + uint32_t rxdesc_ring_end; /* Id of last RxDesc ring */ + uint32_t tx_intr_mask; /* tx interrupt mask */ + uint32_t rx_intr_mask; /* rx interrupt mask */ + uint32_t rxfill_intr_mask; /* Rx fill ring interrupt mask */ + uint32_t rxdesc_intr_mask; /* Rx Desc ring interrupt mask */ + uint32_t txcmpl_intr_mask; /* Tx Cmpl ring interrupt mask */ + uint32_t misc_intr_mask; /* misc interrupt interrupt mask */ +}; + +struct ipq9574_edma_common_info { + struct ipq9574_edma_hw hw; +}; + +#define MAX_PHY 6 +struct ipq9574_eth_dev { + u8 *phy_address; + uint no_of_phys; + uint interface; + uint speed; + uint duplex; + uint sw_configured; + uint mac_unit; + uint mac_ps; + int link_printed; + u32 padding; + struct eth_device *dev; + struct ipq9574_edma_common_info *c_info; + struct phy_ops *ops[MAX_PHY]; + const char phy_name[MDIO_NAME_LEN]; +} __attribute__ ((aligned(8))); + +static inline void* ipq9574_alloc_mem(u32 size) +{ + void *p = malloc(size); + if (p != NULL) + memset(p, 0, size); + return p; +} + +static inline void* ipq9574_alloc_memalign(u32 size) +{ + void *p = memalign(CONFIG_SYS_CACHELINE_SIZE, size); + if (p != NULL) + memset(p, 0, size); + return p; +} + +static inline void ipq9574_free_mem(void *ptr) +{ + if (ptr) + free(ptr); +} + +uint32_t ipq9574_edma_reg_read(uint32_t reg_off); +void ipq9574_edma_reg_write(uint32_t reg_off, uint32_t val); + + +extern int get_eth_mac_address(uchar *enetaddr, uint no_of_macs); + +typedef struct { + uint count; + u8 addr[7]; +} ipq9574_edma_phy_addr_t; + +/* ipq9574 edma Paramaters */ +typedef struct { + uint base; + int unit; + uint mac_conn_to_phy; + phy_interface_t phy; + ipq9574_edma_phy_addr_t phy_addr; + char phy_name[MDIO_NAME_LEN]; +} ipq9574_edma_board_cfg_t; + +extern void ipq9574_ppe_provision_init(void); +extern void ipq9574_port_mac_clock_reset(int port); +extern void ipq9574_speed_clock_set(int port, int clk[4]); +extern void ipq9574_gmac_port_disable(int port); +extern void ipq9574_pqsgmii_speed_set(int port, int speed, int status); +extern void ipq9574_uxsgmii_speed_set(int port, int speed, int duplex, int status); +extern void ppe_port_mux_mac_type_set(int port_id, int mode); +extern void ppe_port_bridge_txmac_set(int port, int status); +extern void ipq9574_10g_r_speed_set(int port, int status); +extern int phy_status_get_from_ppe(int port_id); + +extern void ipq9574_ppe_acl_set(int rule_id, int rule_type, int pkt_type, int l4_port_no, int l4_port_mask, int permit, int deny); +extern void ppe_uniphy_mode_set(uint32_t uniphy_index, uint32_t mode); +#endif /* ___IPQ9574_EDMA__ */ diff --git a/sources/uboot-be550/drivers/net/ipq9574/ipq9574_ppe.c b/sources/uboot-be550/drivers/net/ipq9574/ipq9574_ppe.c new file mode 100644 index 00000000..75226c9d --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq9574/ipq9574_ppe.c @@ -0,0 +1,1191 @@ +/* + ************************************************************************** + * Copyright (c) 2016-2019, 2021, The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + ************************************************************************** +*/ + +#include +#include +#include "ipq9574_ppe.h" +#include "ipq9574_uniphy.h" +#include +#include "ipq_phy.h" + +DECLARE_GLOBAL_DATA_PTR; +#ifdef DEBUG +#define pr_debug(fmt, args...) printf(fmt, ##args); +#else +#define pr_debug(fmt, args...) +#endif + +#define pr_info(fmt, args...) printf(fmt, ##args); + +int uniphy_force_mode; + +extern int is_uniphy_enabled(int uniphy_index); +extern void uniphy_port5_clock_source_set(void); + +/* + * ipq9574_ppe_reg_read() + */ +static inline void ipq9574_ppe_reg_read(u32 reg, u32 *val) +{ + *val = readl((void *)(IPQ9574_PPE_BASE_ADDR + reg)); +} + +/* + * ipq9574_ppe_reg_write() + */ +static inline void ipq9574_ppe_reg_write(u32 reg, u32 val) +{ + writel(val, (void *)(IPQ9574_PPE_BASE_ADDR + reg)); +} + +void ppe_ipo_rule_reg_set(union ipo_rule_reg_u *hw_reg, int rule_id) +{ + int i; + + for (i = 0; i < 3; i++) { + ipq9574_ppe_reg_write(IPO_CSR_BASE_ADDR + IPO_RULE_REG_ADDRESS + + (rule_id * IPO_RULE_REG_INC) + (i * 4), hw_reg->val[i]); + } +} + +void ppe_ipo_mask_reg_set(union ipo_mask_reg_u *hw_mask, int rule_id) +{ + int i; + + for (i = 0; i < 2; i++) { + ipq9574_ppe_reg_write((IPO_CSR_BASE_ADDR + IPO_MASK_REG_ADDRESS + + (rule_id * IPO_MASK_REG_INC) + (i * 4)), hw_mask->val[i]); + } +} + +void ppe_ipo_action_set(union ipo_action_u *hw_act, int rule_id) +{ + int i; + + for (i = 0; i < 5; i++) { + ipq9574_ppe_reg_write((IPE_L2_BASE_ADDR + IPO_ACTION_ADDRESS + + (rule_id * IPO_ACTION_INC) + (i * 4)), hw_act->val[i]); + } +} + +void ipq9574_ppe_acl_set(int rule_id, int rule_type, int field0, int field1, int mask, int permit, int deny) +{ + union ipo_rule_reg_u hw_reg = {0}; + union ipo_mask_reg_u hw_mask = {0}; + union ipo_action_u hw_act = {0}; + + memset(&hw_reg, 0, sizeof(hw_reg)); + memset(&hw_mask, 0, sizeof(hw_mask)); + memset(&hw_act, 0, sizeof(hw_act)); + + if (rule_id < MAX_RULE) { + hw_act.bf.dest_info_change_en = 1; + hw_mask.bf.maskfield_0 = mask; + hw_reg.bf.rule_type = rule_type; + if (rule_type == ADPT_ACL_HPPE_IPV4_DIP_RULE) { + hw_reg.bf.rule_field_0 = field1; + hw_reg.bf.rule_field_1 = field0<<17; + hw_mask.bf.maskfield_1 = 7<<17; + if (permit == 0x0) { + hw_act.bf.fwd_cmd = 0;/* forward */ + hw_reg.bf.pri = 0x1; + } + if (deny == 0x1) { + hw_act.bf.fwd_cmd = 1;/* drop */ + hw_reg.bf.pri = 0x0; + } + } else if (rule_type == ADPT_ACL_HPPE_MAC_SA_RULE) { + /* src mac AC rule */ + hw_reg.bf.rule_field_0 = field1; + hw_reg.bf.rule_field_1 = field0; + hw_mask.bf.maskfield_1 = 0xffff; + hw_act.bf.fwd_cmd = 1;/* drop */ + hw_reg.bf.pri = 0x2; + /* bypass fdb lean and fdb freash */ + hw_act.bf.bypass_bitmap_0 = 0x1800; + } else if (rule_type == ADPT_ACL_HPPE_MAC_DA_RULE) { + /* dest mac AC rule */ + hw_reg.bf.rule_field_0 = field1; + hw_reg.bf.rule_field_1 = field0; + hw_mask.bf.maskfield_1 = 0xffff; + hw_act.bf.fwd_cmd = 1;/* drop */ + hw_reg.bf.pri = 0x2; + } + /* bind port1-port6 */ + hw_reg.bf.src_0 = 0x0; + hw_reg.bf.src_1 = 0x3F; + ppe_ipo_rule_reg_set(&hw_reg, rule_id); + ppe_ipo_mask_reg_set(&hw_mask, rule_id); + ppe_ipo_action_set(&hw_act, rule_id); + } +} + +/* + * ipq9574_ppe_vp_port_tbl_set() + */ +static void ipq9574_ppe_vp_port_tbl_set(int port, int vsi) +{ + u32 addr = IPQ9574_PPE_L3_VP_PORT_TBL_ADDR + + (port * IPQ9574_PPE_L3_VP_PORT_TBL_INC); + ipq9574_ppe_reg_write(addr, 0x0); + ipq9574_ppe_reg_write(addr + 0x4 , 1 << 9 | vsi << 10); + ipq9574_ppe_reg_write(addr + 0x8, 0x0); + ipq9574_ppe_reg_write(addr + 0xc, 0x0); +} + +/* + * ipq9574_ppe_ucast_queue_map_tbl_queue_id_set() + */ +static void ipq9574_ppe_ucast_queue_map_tbl_queue_id_set(int queue, int port) +{ + uint32_t val; + + ipq9574_ppe_reg_read(IPQ9574_PPE_QM_UQM_TBL + + (port * IPQ9574_PPE_UCAST_QUEUE_MAP_TBL_INC), &val); + + val |= queue << 4; + + ipq9574_ppe_reg_write(IPQ9574_PPE_QM_UQM_TBL + + (port * IPQ9574_PPE_UCAST_QUEUE_MAP_TBL_INC), val); +} + +/* + * ipq9574_vsi_setup() + */ +static void ipq9574_vsi_setup(int vsi, uint8_t group_mask) +{ + uint32_t val = (group_mask << 24 | group_mask << 16 | group_mask << 8 + | group_mask); + + /* Set mask */ + ipq9574_ppe_reg_write(0x063800 + (vsi * 0x10), val); + + /* new addr lrn en | station move lrn en */ + ipq9574_ppe_reg_write(0x063804 + (vsi * 0x10), 0x9); +} + +/* + * ipq9574_gmac_port_disable() + */ +void ipq9574_gmac_port_disable(int port) +{ + ipq9574_ppe_reg_write(IPQ9574_PPE_MAC_ENABLE + (0x200 * port), 0x70); + ipq9574_ppe_reg_write(IPQ9574_PPE_MAC_SPEED + (0x200 * port), 0x2); + ipq9574_ppe_reg_write(IPQ9574_PPE_MAC_MIB_CTL + (0x200 * port), 0x1); +} + +/* + * ppe_port_bridge_txmac_set() + * TXMAC should be disabled for all ports by default + * TXMAC should be enabled for all ports that are link up alone + */ +void ppe_port_bridge_txmac_set(int port_id, int status) +{ + uint32_t reg_value = 0; + + ipq9574_ppe_reg_read(IPE_L2_BASE_ADDR + PORT_BRIDGE_CTRL_ADDRESS + + (port_id * PORT_BRIDGE_CTRL_INC), ®_value); + if (status == 0) + reg_value |= TX_MAC_EN; + else + reg_value &= ~TX_MAC_EN; + + ipq9574_ppe_reg_write(IPE_L2_BASE_ADDR + PORT_BRIDGE_CTRL_ADDRESS + + (port_id * PORT_BRIDGE_CTRL_INC), reg_value); + +} + +/* + * ipq9574_port_mac_clock_reset() + */ +void ipq9574_port_mac_clock_reset(int port) +{ + int reg_val, reg_val1; + + reg_val = readl(NSS_CC_PPE_RESET_ADDR); + reg_val1 = readl(NSS_CC_UNIPHY_MISC_RESET); + switch(port) { + case 0: + /* Assert */ + reg_val |= GCC_PPE_PORT1_MAC_ARES; + reg_val1 |= GCC_PORT1_ARES; + writel(reg_val, NSS_CC_PPE_RESET_ADDR); + writel(reg_val1, NSS_CC_UNIPHY_MISC_RESET); + mdelay(150); + /* De-Assert */ + reg_val = readl(NSS_CC_PPE_RESET_ADDR); + reg_val1 = readl(NSS_CC_UNIPHY_MISC_RESET); + reg_val &= ~GCC_PPE_PORT1_MAC_ARES; + reg_val1 &= ~GCC_PORT1_ARES; + break; + case 1: + /* Assert */ + reg_val |= GCC_PPE_PORT2_MAC_ARES; + reg_val1 |= GCC_PORT2_ARES; + writel(reg_val, NSS_CC_PPE_RESET_ADDR); + writel(reg_val1, NSS_CC_UNIPHY_MISC_RESET); + mdelay(150); + /* De-Assert */ + reg_val = readl(NSS_CC_PPE_RESET_ADDR); + reg_val1 = readl(NSS_CC_UNIPHY_MISC_RESET); + reg_val &= ~GCC_PPE_PORT2_MAC_ARES; + reg_val1 &= ~GCC_PORT2_ARES; + break; + case 2: + /* Assert */ + reg_val |= GCC_PPE_PORT3_MAC_ARES; + reg_val1 |= GCC_PORT3_ARES; + writel(reg_val, NSS_CC_PPE_RESET_ADDR); + writel(reg_val1, NSS_CC_UNIPHY_MISC_RESET); + mdelay(150); + /* De-Assert */ + reg_val = readl(NSS_CC_PPE_RESET_ADDR); + reg_val1 = readl(NSS_CC_UNIPHY_MISC_RESET); + reg_val &= ~GCC_PPE_PORT3_MAC_ARES; + reg_val1 &= ~GCC_PORT3_ARES; + break; + case 3: + /* Assert */ + reg_val |= GCC_PPE_PORT4_MAC_ARES; + reg_val1 |= GCC_PORT4_ARES; + writel(reg_val, NSS_CC_PPE_RESET_ADDR); + writel(reg_val1, NSS_CC_UNIPHY_MISC_RESET); + mdelay(150); + /* De-Assert */ + reg_val = readl(NSS_CC_PPE_RESET_ADDR); + reg_val1 = readl(NSS_CC_UNIPHY_MISC_RESET); + reg_val &= ~GCC_PPE_PORT4_MAC_ARES; + reg_val1 &= ~GCC_PORT4_ARES; + break; + case 4: + /* Assert */ + reg_val |= GCC_PPE_PORT5_MAC_ARES; + reg_val1 |= GCC_PORT5_ARES; + writel(reg_val, NSS_CC_PPE_RESET_ADDR); + writel(reg_val1, NSS_CC_UNIPHY_MISC_RESET); + mdelay(150); + /* De-Assert */ + reg_val = readl(NSS_CC_PPE_RESET_ADDR); + reg_val1 = readl(NSS_CC_UNIPHY_MISC_RESET); + reg_val &= ~GCC_PPE_PORT5_MAC_ARES; + reg_val1 &= ~GCC_PORT5_ARES; + break; + case 5: + /* Assert */ + reg_val |= GCC_PPE_PORT6_MAC_ARES; + reg_val1 |= GCC_PORT6_ARES; + writel(reg_val, NSS_CC_PPE_RESET_ADDR); + writel(reg_val1, NSS_CC_UNIPHY_MISC_RESET); + mdelay(150); + /* De-Assert */ + reg_val = readl(NSS_CC_PPE_RESET_ADDR); + reg_val1 = readl(NSS_CC_UNIPHY_MISC_RESET); + reg_val &= ~GCC_PPE_PORT6_MAC_ARES; + reg_val1 &= ~GCC_PORT6_ARES; + break; + default: + break; + } + writel(reg_val, NSS_CC_PPE_RESET_ADDR); + writel(reg_val1, NSS_CC_UNIPHY_MISC_RESET); + mdelay(150); +} + +void ipq9574_speed_clock_set(int port_id, int clk[4]) +{ + int i; + int reg_val[6]; + + for (i = 0; i < 6; i++) + { + reg_val[i] = readl(NSS_CC_PORT1_RX_CMD_RCGR + (i * 0x4) + (port_id * 0x18)); + } + reg_val[0] &= ~0x1; + reg_val[1] &= ~0x71f; + reg_val[2] &= ~0x1ff; + reg_val[3] &= ~0x1; + reg_val[4] &= ~0x71f; + reg_val[5] &= ~0x1ff; + + reg_val[1] |= clk[0]; + reg_val[2] |= clk[1]; + reg_val[4] |= clk[2]; + reg_val[5] |= clk[3]; + + /* Port Rx direction speed clock cfg */ + writel(reg_val[1], NSS_CC_PORT1_RX_CMD_RCGR + 0x4 + (port_id * 0x18)); + writel(reg_val[2], NSS_CC_PORT1_RX_CMD_RCGR + 0x8 + (port_id * 0x18)); + writel(reg_val[0] | 0x1 , NSS_CC_PORT1_RX_CMD_RCGR + (port_id * 0x18)); + /* Port Tx direction speed clock cfg */ + writel(reg_val[4], NSS_CC_PORT1_RX_CMD_RCGR + 0x10 + (port_id * 0x18)); + writel(reg_val[5], NSS_CC_PORT1_RX_CMD_RCGR + 0x14 + (port_id * 0x18)); + writel(reg_val[3] | 0x1, NSS_CC_PORT1_RX_CMD_RCGR + 0xc + (port_id * 0x18)); +} + +int phy_status_get_from_ppe(int port_id) +{ + uint32_t reg_field = 0; + + if (port_id == 0) { + ipq9574_ppe_reg_read(PORT_PHY_STATUS0_ADDRESS, ®_field); + } else { + ipq9574_ppe_reg_read(PORT_PHY_STATUS_ADDRESS, ®_field); + + if (port_id == (PORT5 - PPE_UNIPHY_INSTANCE1)) + reg_field >>= PORT_PHY_STATUS_PORT5_1_OFFSET; + else + reg_field >>= PORT_PHY_STATUS_PORT6_OFFSET; + } + + return ((reg_field >> 7) & 0x1) ? 0 : 1; +} + +void ppe_xgmac_speed_set(uint32_t port, int speed) +{ + uint32_t reg_value = 0; + + pr_debug("\nDEBUGGING xgmac_speed_set......... PORTID = %d\n", port); + ipq9574_ppe_reg_read(PPE_SWITCH_NSS_SWITCH_XGMAC0 + + (port * NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION), ®_value); + + switch(speed) { + case 0: + case 1: + case 2: + reg_value &=~USS; + reg_value |=SS(XGMAC_SPEED_SELECT_1000M); + break; + case 3: + reg_value |=USS; + reg_value |=SS(XGMAC_SPEED_SELECT_10000M); + break; + case 4: + reg_value |=USS; + reg_value |=SS(XGMAC_SPEED_SELECT_2500M); + break; + case 5: + reg_value |=USS; + reg_value |=SS(XGMAC_SPEED_SELECT_5000M); + break; + } + reg_value |=JD; + ipq9574_ppe_reg_write(PPE_SWITCH_NSS_SWITCH_XGMAC0 + + (port * NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION), reg_value); + pr_debug("NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION Address = 0x%x -> Value = %u\n", + PPE_SWITCH_NSS_SWITCH_XGMAC0 + (port * NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION), + reg_value); + +} + +void ppe_xgmac_10g_r_speed_set(uint32_t port) +{ + uint32_t reg_value = 0; + + pr_debug("DEBUGGING 10g_r_speed_set......... PORTID = %d\n", port); + ipq9574_ppe_reg_read(PPE_SWITCH_NSS_SWITCH_XGMAC0 + + (port * NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION), ®_value); + + reg_value |=JD; + ipq9574_ppe_reg_write(PPE_SWITCH_NSS_SWITCH_XGMAC0 + + (port * NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION), reg_value); + + pr_debug("NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION Address = 0x%x -> Value = %u\n", + PPE_SWITCH_NSS_SWITCH_XGMAC0 + (port * NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION), + reg_value); +} + +void ppe_port_txmac_status_set(uint32_t port) +{ + uint32_t reg_value = 0; + + pr_debug("DEBUGGING txmac_status_set......... PORTID = %d\n", port); + ipq9574_ppe_reg_read(PPE_SWITCH_NSS_SWITCH_XGMAC0 + + (port * NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION), ®_value); + + reg_value |=TE; + ipq9574_ppe_reg_write(PPE_SWITCH_NSS_SWITCH_XGMAC0 + + (port * NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION), reg_value); + + pr_debug("NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION Address = 0x%x -> Value = %u\n", + PPE_SWITCH_NSS_SWITCH_XGMAC0 + (port * NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION), + reg_value); +} + +void ppe_port_rxmac_status_set(uint32_t port) +{ + uint32_t reg_value = 0; + + pr_debug("DEBUGGING rxmac_status_set......... PORTID = %d\n", port); + ipq9574_ppe_reg_read(PPE_SWITCH_NSS_SWITCH_XGMAC0 + + MAC_RX_CONFIGURATION_ADDRESS + + (port * NSS_SWITCH_XGMAC_MAC_RX_CONFIGURATION), ®_value); + + reg_value |= 0x300000c0; + reg_value |=RE; + reg_value |=ACS; + reg_value |=CST; + ipq9574_ppe_reg_write(PPE_SWITCH_NSS_SWITCH_XGMAC0 + + MAC_RX_CONFIGURATION_ADDRESS + + (port * NSS_SWITCH_XGMAC_MAC_RX_CONFIGURATION), reg_value); + + pr_debug("NSS_SWITCH_XGMAC_MAC_RX_CONFIGURATION Address = 0x%x -> Value = %u\n", + PPE_SWITCH_NSS_SWITCH_XGMAC0 + MAC_RX_CONFIGURATION_ADDRESS + + (port * NSS_SWITCH_XGMAC_MAC_RX_CONFIGURATION), + reg_value); +} + +void ppe_mac_packet_filter_set(uint32_t port) +{ + pr_debug("DEBUGGING mac_packet_filter_set......... PORTID = %d\n", port); + ipq9574_ppe_reg_write(PPE_SWITCH_NSS_SWITCH_XGMAC0 + + MAC_PACKET_FILTER_ADDRESS + + (port * MAC_PACKET_FILTER_INC), 0x80000081); + pr_debug("NSS_SWITCH_XGMAC_MAC_PACKET_FILTER Address = 0x%x -> Value = %u\n", + PPE_SWITCH_NSS_SWITCH_XGMAC0 + MAC_PACKET_FILTER_ADDRESS + + (port * MAC_PACKET_FILTER_ADDRESS), + 0x80000081); +} + +void ipq9574_10g_r_speed_set(int port, int status) +{ + ppe_xgmac_10g_r_speed_set(port); + ppe_port_bridge_txmac_set(port + 1, status); + ppe_port_txmac_status_set(port); + ppe_port_rxmac_status_set(port); + ppe_mac_packet_filter_set(port); +} + +void ipq9574_uxsgmii_speed_set(int port, int speed, int duplex, + int status) +{ + uint32_t uniphy_index = 0; + + switch(port) { + case 0: + case 1: + case 2: + case 3: + uniphy_index = PPE_UNIPHY_INSTANCE0; + break; + case 4: + uniphy_index = PPE_UNIPHY_INSTANCE1; + break; + case 5: + uniphy_index = PPE_UNIPHY_INSTANCE2; + break; + default: + printf("Invalid port id , using UNIPHY0 as default \n"); + break; + } + + ppe_uniphy_usxgmii_autoneg_completed(uniphy_index); + ppe_uniphy_usxgmii_speed_set(uniphy_index, port + 1, speed); + ppe_xgmac_speed_set(port, speed); + ppe_uniphy_usxgmii_duplex_set(uniphy_index, duplex); + ppe_uniphy_usxgmii_port_reset(uniphy_index); + ppe_port_bridge_txmac_set(port + 1, status); + ppe_port_txmac_status_set(port); + ppe_port_rxmac_status_set(port); + ppe_mac_packet_filter_set(port); +} + +void ipq9574_pqsgmii_speed_set(int port, int speed, int status) +{ + ppe_port_bridge_txmac_set(port + 1, status); + ipq9574_ppe_reg_write(IPQ9574_PPE_MAC_SPEED + (0x200 * port), speed); + ipq9574_ppe_reg_write(IPQ9574_PPE_MAC_ENABLE + (0x200 * port), 0x73); + ipq9574_ppe_reg_write(IPQ9574_PPE_MAC_MIB_CTL + (0x200 * port), 0x1); +} + +/* + * ipq9574_ppe_flow_port_map_tbl_port_num_set() + */ +static void ipq9574_ppe_flow_port_map_tbl_port_num_set(int queue, int port) +{ + ipq9574_ppe_reg_write(IPQ9574_PPE_L0_FLOW_PORT_MAP_TBL + + queue * IPQ9574_PPE_L0_FLOW_PORT_MAP_TBL_INC, port); + ipq9574_ppe_reg_write(IPQ9574_PPE_L1_FLOW_PORT_MAP_TBL + + port * IPQ9574_PPE_L1_FLOW_PORT_MAP_TBL_INC, port); +} + +/* + * ipq9574_ppe_flow_map_tbl_set() + */ +static void ipq9574_ppe_flow_map_tbl_set(int queue, int port) +{ + uint32_t val = port | 0x401000; /* c_drr_wt = 1, e_drr_wt = 1 */ + ipq9574_ppe_reg_write(IPQ9574_PPE_L0_FLOW_MAP_TBL + queue * IPQ9574_PPE_L0_FLOW_MAP_TBL_INC, + val); + + val = port | 0x100400; /* c_drr_wt = 1, e_drr_wt = 1 */ + ipq9574_ppe_reg_write(IPQ9574_PPE_L1_FLOW_MAP_TBL + port * IPQ9574_PPE_L1_FLOW_MAP_TBL_INC, + val); +} + +/* + * ipq9574_ppe_tdm_configuration + */ +static void ipq9574_ppe_tdm_configuration(void) +{ + ipq9574_ppe_reg_write(0xc000, 0x26); + ipq9574_ppe_reg_write(0xc010, 0x34); + ipq9574_ppe_reg_write(0xc020, 0x25); + ipq9574_ppe_reg_write(0xc030, 0x30); + ipq9574_ppe_reg_write(0xc040, 0x21); + ipq9574_ppe_reg_write(0xc050, 0x36); + ipq9574_ppe_reg_write(0xc060, 0x20); + ipq9574_ppe_reg_write(0xc070, 0x35); + ipq9574_ppe_reg_write(0xc080, 0x26); + ipq9574_ppe_reg_write(0xc090, 0x31); + ipq9574_ppe_reg_write(0xc0a0, 0x22); + ipq9574_ppe_reg_write(0xc0b0, 0x36); + ipq9574_ppe_reg_write(0xc0c0, 0x27); + ipq9574_ppe_reg_write(0xc0d0, 0x30); + ipq9574_ppe_reg_write(0xc0e0, 0x25); + ipq9574_ppe_reg_write(0xc0f0, 0x32); + ipq9574_ppe_reg_write(0xc100, 0x26); + ipq9574_ppe_reg_write(0xc110, 0x36); + ipq9574_ppe_reg_write(0xc120, 0x20); + ipq9574_ppe_reg_write(0xc130, 0x37); + ipq9574_ppe_reg_write(0xc140, 0x24); + ipq9574_ppe_reg_write(0xc150, 0x30); + ipq9574_ppe_reg_write(0xc160, 0x23); + ipq9574_ppe_reg_write(0xc170, 0x36); + ipq9574_ppe_reg_write(0xc180, 0x26); + ipq9574_ppe_reg_write(0xc190, 0x34); + ipq9574_ppe_reg_write(0xc1a0, 0x25); + ipq9574_ppe_reg_write(0xc1b0, 0x33); + ipq9574_ppe_reg_write(0xc1c0, 0x20); + ipq9574_ppe_reg_write(0xc1d0, 0x36); + ipq9574_ppe_reg_write(0xc1e0, 0x21); + ipq9574_ppe_reg_write(0xc1f0, 0x35); + ipq9574_ppe_reg_write(0xc200, 0x26); + ipq9574_ppe_reg_write(0xc210, 0x30); + ipq9574_ppe_reg_write(0xc220, 0x27); + ipq9574_ppe_reg_write(0xc230, 0x31); + ipq9574_ppe_reg_write(0xc240, 0x20); + ipq9574_ppe_reg_write(0xc250, 0x36); + ipq9574_ppe_reg_write(0xc260, 0x25); + ipq9574_ppe_reg_write(0xc270, 0x37); + ipq9574_ppe_reg_write(0xc280, 0x26); + ipq9574_ppe_reg_write(0xc290, 0x30); + ipq9574_ppe_reg_write(0xc2a0, 0x22); + ipq9574_ppe_reg_write(0xc2b0, 0x35); + ipq9574_ppe_reg_write(0xc2c0, 0x20); + ipq9574_ppe_reg_write(0xc2d0, 0x36); + ipq9574_ppe_reg_write(0xc2e0, 0x23); + ipq9574_ppe_reg_write(0xc2f0, 0x32); + ipq9574_ppe_reg_write(0xc300, 0x26); + ipq9574_ppe_reg_write(0xc310, 0x30); + ipq9574_ppe_reg_write(0xc320, 0x25); + ipq9574_ppe_reg_write(0xc330, 0x33); + ipq9574_ppe_reg_write(0xc340, 0x20); + ipq9574_ppe_reg_write(0xc350, 0x36); + ipq9574_ppe_reg_write(0xc360, 0x27); + ipq9574_ppe_reg_write(0xc370, 0x35); + ipq9574_ppe_reg_write(0xc380, 0x26); + ipq9574_ppe_reg_write(0xc390, 0x30); + ipq9574_ppe_reg_write(0xc3a0, 0x24); + ipq9574_ppe_reg_write(0xc3b0, 0x37); + ipq9574_ppe_reg_write(0xc3c0, 0x20); + ipq9574_ppe_reg_write(0xc3d0, 0x36); + ipq9574_ppe_reg_write(0xc3e0, 0x25); + ipq9574_ppe_reg_write(0xc3f0, 0x34); + ipq9574_ppe_reg_write(0xc400, 0x26); + ipq9574_ppe_reg_write(0xc410, 0x30); + ipq9574_ppe_reg_write(0xc420, 0x21); + ipq9574_ppe_reg_write(0xc430, 0x35); + ipq9574_ppe_reg_write(0xc440, 0x20); + ipq9574_ppe_reg_write(0xc450, 0x36); + ipq9574_ppe_reg_write(0xc460, 0x22); + ipq9574_ppe_reg_write(0xc470, 0x31); + ipq9574_ppe_reg_write(0xc480, 0x26); + ipq9574_ppe_reg_write(0xc490, 0x30); + ipq9574_ppe_reg_write(0xc4a0, 0x25); + ipq9574_ppe_reg_write(0xc4b0, 0x32); + ipq9574_ppe_reg_write(0xc4c0, 0x20); + ipq9574_ppe_reg_write(0xc4d0, 0x36); + ipq9574_ppe_reg_write(0xc4e0, 0x27); + ipq9574_ppe_reg_write(0xc4f0, 0x35); + ipq9574_ppe_reg_write(0xc500, 0x26); + ipq9574_ppe_reg_write(0xc510, 0x30); + ipq9574_ppe_reg_write(0xc520, 0x23); + ipq9574_ppe_reg_write(0xc530, 0x37); + ipq9574_ppe_reg_write(0xc540, 0x20); + ipq9574_ppe_reg_write(0xc550, 0x36); + ipq9574_ppe_reg_write(0xc560, 0x25); + ipq9574_ppe_reg_write(0xc570, 0x33); + ipq9574_ppe_reg_write(0xc580, 0x26); + ipq9574_ppe_reg_write(0xc590, 0x30); + ipq9574_ppe_reg_write(0xc5a0, 0x24); + ipq9574_ppe_reg_write(0xc5b0, 0x35); + ipq9574_ppe_reg_write(0xc5c0, 0x20); + ipq9574_ppe_reg_write(0xc5d0, 0x36); + ipq9574_ppe_reg_write(0xc5e0, 0x21); + ipq9574_ppe_reg_write(0xc5f0, 0x34); + ipq9574_ppe_reg_write(0xc600, 0x26); + ipq9574_ppe_reg_write(0xc610, 0x30); + ipq9574_ppe_reg_write(0xc620, 0x25); + ipq9574_ppe_reg_write(0xc630, 0x31); + ipq9574_ppe_reg_write(0xc640, 0x20); + ipq9574_ppe_reg_write(0xc650, 0x36); + ipq9574_ppe_reg_write(0xc660, 0x22); + ipq9574_ppe_reg_write(0xc670, 0x35); + ipq9574_ppe_reg_write(0xc680, 0x26); + ipq9574_ppe_reg_write(0xc690, 0x30); + ipq9574_ppe_reg_write(0xc6a0, 0x23); + ipq9574_ppe_reg_write(0xc6b0, 0x32); + ipq9574_ppe_reg_write(0xc6c0, 0x20); + ipq9574_ppe_reg_write(0xc6d0, 0x36); + ipq9574_ppe_reg_write(0xc6e0, 0x25); + ipq9574_ppe_reg_write(0xc6f0, 0x33); + ipq9574_ppe_reg_write(0xc700, 0x26); + ipq9574_ppe_reg_write(0xc710, 0x30); + ipq9574_ppe_reg_write(0xc720, 0x24); + ipq9574_ppe_reg_write(0xc730, 0x35); + ipq9574_ppe_reg_write(0xc740, 0x20); + ipq9574_ppe_reg_write(0xc750, 0x36); + ipq9574_ppe_reg_write(0xb000, 0x80000076); +} + +static void ipq9574_ppe_tdm1_configuration(void) +{ + ipq9574_ppe_reg_write(0xc000, 0x26); + ipq9574_ppe_reg_write(0xc010, 0x36); + ipq9574_ppe_reg_write(0xc020, 0x20); + ipq9574_ppe_reg_write(0xc030, 0x30); + ipq9574_ppe_reg_write(0xc040, 0x25); + ipq9574_ppe_reg_write(0xc050, 0x35); + ipq9574_ppe_reg_write(0xc060, 0x21); + ipq9574_ppe_reg_write(0xc070, 0x31); + ipq9574_ppe_reg_write(0xc080, 0x22); + ipq9574_ppe_reg_write(0xc090, 0x32); + ipq9574_ppe_reg_write(0xc0a0, 0x20); + ipq9574_ppe_reg_write(0xc0b0, 0x30); + ipq9574_ppe_reg_write(0xc0c0, 0x26); + ipq9574_ppe_reg_write(0xc0d0, 0x36); + ipq9574_ppe_reg_write(0xc0e0, 0x23); + ipq9574_ppe_reg_write(0xc0f0, 0x33); + ipq9574_ppe_reg_write(0xc100, 0x25); + ipq9574_ppe_reg_write(0xc110, 0x35); + ipq9574_ppe_reg_write(0xc120, 0x21); + ipq9574_ppe_reg_write(0xc130, 0x31); + ipq9574_ppe_reg_write(0xc140, 0x20); + ipq9574_ppe_reg_write(0xc150, 0x30); + ipq9574_ppe_reg_write(0xc160, 0x24); + ipq9574_ppe_reg_write(0xc170, 0x34); + ipq9574_ppe_reg_write(0xc180, 0x26); + ipq9574_ppe_reg_write(0xc190, 0x36); + ipq9574_ppe_reg_write(0xc1a0, 0x25); + ipq9574_ppe_reg_write(0xc1b0, 0x35); + ipq9574_ppe_reg_write(0xc1c0, 0x20); + ipq9574_ppe_reg_write(0xc1d0, 0x30); + ipq9574_ppe_reg_write(0xc1e0, 0x21); + ipq9574_ppe_reg_write(0xc1f0, 0x31); + ipq9574_ppe_reg_write(0xc200, 0x27); + ipq9574_ppe_reg_write(0xc210, 0x37); + ipq9574_ppe_reg_write(0xc220, 0x22); + ipq9574_ppe_reg_write(0xc230, 0x32); + ipq9574_ppe_reg_write(0xc240, 0x26); + ipq9574_ppe_reg_write(0xc250, 0x36); + ipq9574_ppe_reg_write(0xc260, 0x20); + ipq9574_ppe_reg_write(0xc270, 0x30); + ipq9574_ppe_reg_write(0xc280, 0x25); + ipq9574_ppe_reg_write(0xc290, 0x35); + ipq9574_ppe_reg_write(0xc2a0, 0x21); + ipq9574_ppe_reg_write(0xc2b0, 0x31); + ipq9574_ppe_reg_write(0xc2c0, 0x23); + ipq9574_ppe_reg_write(0xc2d0, 0x33); + ipq9574_ppe_reg_write(0xc2e0, 0x20); + ipq9574_ppe_reg_write(0xc2f0, 0x30); + ipq9574_ppe_reg_write(0xc300, 0x26); + ipq9574_ppe_reg_write(0xc310, 0x36); + ipq9574_ppe_reg_write(0xc320, 0x24); + ipq9574_ppe_reg_write(0xc330, 0x34); + ipq9574_ppe_reg_write(0xc340, 0x25); + ipq9574_ppe_reg_write(0xc350, 0x35); + ipq9574_ppe_reg_write(0xc360, 0x21); + ipq9574_ppe_reg_write(0xc370, 0x31); + ipq9574_ppe_reg_write(0xc380, 0x20); + ipq9574_ppe_reg_write(0xc390, 0x30); + ipq9574_ppe_reg_write(0xc3a0, 0x27); + ipq9574_ppe_reg_write(0xc3b0, 0x37); + ipq9574_ppe_reg_write(0xc3c0, 0x26); + ipq9574_ppe_reg_write(0xc3d0, 0x36); + ipq9574_ppe_reg_write(0xc3e0, 0x22); + ipq9574_ppe_reg_write(0xc3f0, 0x32); + ipq9574_ppe_reg_write(0xc400, 0x25); + ipq9574_ppe_reg_write(0xc410, 0x35); + ipq9574_ppe_reg_write(0xc420, 0x20); + ipq9574_ppe_reg_write(0xc430, 0x30); + ipq9574_ppe_reg_write(0xc440, 0x21); + ipq9574_ppe_reg_write(0xc450, 0x31); + ipq9574_ppe_reg_write(0xc460, 0x23); + ipq9574_ppe_reg_write(0xc470, 0x33); + ipq9574_ppe_reg_write(0xc480, 0x26); + ipq9574_ppe_reg_write(0xc490, 0x36); + ipq9574_ppe_reg_write(0xc4a0, 0x25); + ipq9574_ppe_reg_write(0xc4b0, 0x35); + ipq9574_ppe_reg_write(0xc4c0, 0x20); + ipq9574_ppe_reg_write(0xc4d0, 0x30); + ipq9574_ppe_reg_write(0xc4e0, 0x21); + ipq9574_ppe_reg_write(0xc4f0, 0x31); + ipq9574_ppe_reg_write(0xc500, 0x24); + ipq9574_ppe_reg_write(0xc510, 0x34); + ipq9574_ppe_reg_write(0xc520, 0x26); + ipq9574_ppe_reg_write(0xc530, 0x36); + ipq9574_ppe_reg_write(0xc540, 0x20); + ipq9574_ppe_reg_write(0xc550, 0x30); + ipq9574_ppe_reg_write(0xc560, 0x25); + ipq9574_ppe_reg_write(0xc570, 0x35); + ipq9574_ppe_reg_write(0xc580, 0x27); + ipq9574_ppe_reg_write(0xc590, 0x37); + ipq9574_ppe_reg_write(0xc5a0, 0x21); + ipq9574_ppe_reg_write(0xc5b0, 0x31); + ipq9574_ppe_reg_write(0xc5c0, 0x22); + ipq9574_ppe_reg_write(0xc5d0, 0x32); + ipq9574_ppe_reg_write(0xc5e0, 0x20); + ipq9574_ppe_reg_write(0xc5f0, 0x30); + ipq9574_ppe_reg_write(0xc600, 0x26); + ipq9574_ppe_reg_write(0xc610, 0x36); + ipq9574_ppe_reg_write(0xc620, 0x25); + ipq9574_ppe_reg_write(0xc630, 0x35); + ipq9574_ppe_reg_write(0xc640, 0x23); + ipq9574_ppe_reg_write(0xc650, 0x33); + ipq9574_ppe_reg_write(0xc660, 0x21); + ipq9574_ppe_reg_write(0xc670, 0x31); + ipq9574_ppe_reg_write(0xc680, 0x20); + ipq9574_ppe_reg_write(0xc690, 0x30); + ipq9574_ppe_reg_write(0xc6a0, 0x24); + ipq9574_ppe_reg_write(0xc6b0, 0x34); + ipq9574_ppe_reg_write(0xc6c0, 0x27); + ipq9574_ppe_reg_write(0xc6d0, 0x37); + ipq9574_ppe_reg_write(0xc6e0, 0x25); + ipq9574_ppe_reg_write(0xc6f0, 0x35); + ipq9574_ppe_reg_write(0xc700, 0x26); + ipq9574_ppe_reg_write(0xc710, 0x36); + ipq9574_ppe_reg_write(0xc720, 0x20); + ipq9574_ppe_reg_write(0xc730, 0x30); + ipq9574_ppe_reg_write(0xc740, 0x21); + ipq9574_ppe_reg_write(0xc750, 0x31); + ipq9574_ppe_reg_write(0xb000, 0x80000076); +} +/* + * ipq9574_ppe_queue_ac_enable + */ +static void ipq9574_ppe_queue_ac_enable(void) +{ + int i; + + /* ucast queue */ + for (i = 0; i < 256; i++) { + ipq9574_ppe_reg_write(IPQ9574_PPE_UCAST_QUEUE_AC_EN_BASE_ADDR + + (i * 0x10), 0x32120001); + ipq9574_ppe_reg_write(IPQ9574_PPE_UCAST_QUEUE_AC_EN_BASE_ADDR + + (i * 0x10) + 0x4, 0x0); + ipq9574_ppe_reg_write(IPQ9574_PPE_UCAST_QUEUE_AC_EN_BASE_ADDR + + (i * 0x10) + 0x8, 0x0); + ipq9574_ppe_reg_write(IPQ9574_PPE_UCAST_QUEUE_AC_EN_BASE_ADDR + + (i * 0x10) + 0xc, 0x48000); + } + + /* mcast queue */ + for (i = 0; i < 44; i++) { + ipq9574_ppe_reg_write(IPQ9574_PPE_MCAST_QUEUE_AC_EN_BASE_ADDR + + (i * 0x10), 0x00fa0001); + ipq9574_ppe_reg_write(IPQ9574_PPE_MCAST_QUEUE_AC_EN_BASE_ADDR + + (i * 0x10) + 0x4, 0x0); + ipq9574_ppe_reg_write(IPQ9574_PPE_MCAST_QUEUE_AC_EN_BASE_ADDR + + (i * 0x10) + 0x8, 0x1200); + } +} + +/* + * ipq9574_ppe_enable_port_counter + */ +static void ipq9574_ppe_enable_port_counter(void) +{ + int i; + uint32_t reg = 0; + + for (i = 0; i < 7; i++) { + /* MRU_MTU_CTRL_TBL.rx_cnt_en, MRU_MTU_CTRL_TBL.tx_cnt_en */ + ipq9574_ppe_reg_read(IPQ9574_PPE_MRU_MTU_CTRL_TBL_ADDR + + (i * 0x10), ®); + ipq9574_ppe_reg_write(IPQ9574_PPE_MRU_MTU_CTRL_TBL_ADDR + + (i * 0x10), reg); + ipq9574_ppe_reg_read(IPQ9574_PPE_MRU_MTU_CTRL_TBL_ADDR + + (i * 0x10) + 0x4, ®); + ipq9574_ppe_reg_write(IPQ9574_PPE_MRU_MTU_CTRL_TBL_ADDR + + (i * 0x10) + 0x4, reg | 0x284303); + ipq9574_ppe_reg_read(IPQ9574_PPE_MRU_MTU_CTRL_TBL_ADDR + + (i * 0x10) + 0x8, ®); + ipq9574_ppe_reg_write(IPQ9574_PPE_MRU_MTU_CTRL_TBL_ADDR + + (i * 0x10) + 0x8, reg); + ipq9574_ppe_reg_read(IPQ9574_PPE_MRU_MTU_CTRL_TBL_ADDR + + (i * 0x10) + 0xc, ®); + ipq9574_ppe_reg_write(IPQ9574_PPE_MRU_MTU_CTRL_TBL_ADDR + + (i * 0x10) + 0xc, reg); + + /* MC_MTU_CTRL_TBL.tx_cnt_en */ + ipq9574_ppe_reg_read(IPQ9574_PPE_MC_MTU_CTRL_TBL_ADDR + + (i * 0x4), ®); + ipq9574_ppe_reg_write(IPQ9574_PPE_MC_MTU_CTRL_TBL_ADDR + + (i * 0x4), reg | 0x10000); + + /* PORT_EG_VLAN.tx_counting_en */ + ipq9574_ppe_reg_read(IPQ9574_PPE_PORT_EG_VLAN_TBL_ADDR + + (i * 0x4), ®); + ipq9574_ppe_reg_write(IPQ9574_PPE_PORT_EG_VLAN_TBL_ADDR + + (i * 0x4), reg | 0x100); + + /* TL_PORT_VP_TBL.rx_cnt_en */ + ipq9574_ppe_reg_read(IPQ9574_PPE_TL_PORT_VP_TBL_ADDR + + (i * 0x10), ®); + ipq9574_ppe_reg_write(IPQ9574_PPE_TL_PORT_VP_TBL_ADDR + + (i * 0x10), reg); + ipq9574_ppe_reg_read(IPQ9574_PPE_TL_PORT_VP_TBL_ADDR + + (i * 0x10) + 0x4, ®); + ipq9574_ppe_reg_write(IPQ9574_PPE_TL_PORT_VP_TBL_ADDR + + (i * 0x10) + 0x4, reg); + ipq9574_ppe_reg_read(IPQ9574_PPE_TL_PORT_VP_TBL_ADDR + + (i * 0x10) + 0x8, ®); + ipq9574_ppe_reg_write(IPQ9574_PPE_TL_PORT_VP_TBL_ADDR + + (i * 0x10) + 0x8, reg | 0x20000); + ipq9574_ppe_reg_read(IPQ9574_PPE_TL_PORT_VP_TBL_ADDR + + (i * 0x10) + 0xc, ®); + ipq9574_ppe_reg_write(IPQ9574_PPE_TL_PORT_VP_TBL_ADDR + + (i * 0x10) + 0xc, reg); + } +} + +/* + * ipq9574_ppe_c_sp_cfg_tbl_drr_id_set + */ +static void ipq9574_ppe_c_sp_cfg_tbl_drr_id_set(int id) +{ + ipq9574_ppe_reg_write(IPQ9574_PPE_L0_C_SP_CFG_TBL + (id * 0x80), id * 2); + ipq9574_ppe_reg_write(IPQ9574_PPE_L1_C_SP_CFG_TBL + (id * 0x80), id * 2); +} + +/* + * ipq9574_ppe_e_sp_cfg_tbl_drr_id_set + */ +static void ipq9574_ppe_e_sp_cfg_tbl_drr_id_set(int id) +{ + ipq9574_ppe_reg_write(IPQ9574_PPE_L0_E_SP_CFG_TBL + (id * 0x80), id * 2 + 1); + ipq9574_ppe_reg_write(IPQ9574_PPE_L1_E_SP_CFG_TBL + (id * 0x80), id * 2 + 1); +} + +static void ppe_port_mux_set(int port_id, int port_type, int mode) +{ + uint32_t mux_mac_type = 0; + union port_mux_ctrl_u port_mux_ctrl; + int node; + uint32_t mode1; + + pr_debug("\nport id is: %d, port type is %d, mode is %d", + port_id, port_type, mode); + node = fdt_path_offset(gd->fdt_blob, "/ess-switch"); + + if (port_type == PORT_GMAC_TYPE) + mux_mac_type = IPQ9574_PORT_MUX_MAC_TYPE; + else if (port_type == PORT_XGMAC_TYPE) + mux_mac_type = IPQ9574_PORT_MUX_XMAC_TYPE; + else + printf("\nAttention!!!..Port type configured wrongly..port_id = %d, mode = %d, port_type = %d", + port_id, mode, port_type); + + port_mux_ctrl.val = 0; + ipq9574_ppe_reg_read(IPQ9574_PORT_MUX_CTRL, &(port_mux_ctrl.val)); + pr_debug("\nBEFORE UPDATE: Port MUX CTRL value is %u", port_mux_ctrl.val); + + + switch (port_id) { + case PORT1: + port_mux_ctrl.bf.port1_mac_sel = mux_mac_type; + port_mux_ctrl.bf.port1_pcs_sel = 0; + break; + case PORT2: + port_mux_ctrl.bf.port2_mac_sel = mux_mac_type; + port_mux_ctrl.bf.port2_pcs_sel = 0; + break; + case PORT3: + port_mux_ctrl.bf.port3_mac_sel = mux_mac_type; + port_mux_ctrl.bf.port3_pcs_sel = 0; + break; + case PORT4: + port_mux_ctrl.bf.port4_mac_sel = mux_mac_type; + port_mux_ctrl.bf.port4_pcs_sel = 0; + break; + case PORT5: + port_mux_ctrl.bf.port5_mac_sel = mux_mac_type; + /* + * If port 5 is part of uniphy0, then uniphy1 should be + * given as 0xFF (EPORT_WRAPPER_MAX) in DT since uniphy1 + * will not be used in that case + */ + mode1 = fdtdec_get_uint(gd->fdt_blob, node, "switch_mac_mode1", -1); + if (mode1 == EPORT_WRAPPER_MAX) + port_mux_ctrl.bf.port5_pcs_sel = + IPQ9574_PORT5_MUX_PCS_UNIPHY0; + else + port_mux_ctrl.bf.port5_pcs_sel = + IPQ9574_PORT5_MUX_PCS_UNIPHY1; + break; + case PORT6: + port_mux_ctrl.bf.port6_mac_sel = mux_mac_type; + port_mux_ctrl.bf.port6_pcs_sel = 0; + break; + default: + break; + } + + ipq9574_ppe_reg_write(IPQ9574_PORT_MUX_CTRL, port_mux_ctrl.val); + pr_debug("\nAFTER UPDATE: Port MUX CTRL value is %u", port_mux_ctrl.val); +} + +void ppe_port_mux_mac_type_set(int port_id, int mode) +{ + uint32_t port_type; + + switch(mode) + { + case EPORT_WRAPPER_PSGMII: + case EPORT_WRAPPER_SGMII0_RGMII4: + case EPORT_WRAPPER_SGMII_PLUS: + case EPORT_WRAPPER_SGMII_FIBER: + case EPORT_WRAPPER_SGMII_CHANNEL0: + port_type = PORT_GMAC_TYPE; + break; + case EPORT_WRAPPER_USXGMII: + case EPORT_WRAPPER_10GBASE_R: + case EPORT_WRAPPER_UQXGMII: + port_type = PORT_XGMAC_TYPE; + break; + default: + printf("\nError during port_type set: mode is %d, port_id is: %d", + mode, port_id); + return; + } + ppe_port_mux_set(port_id, port_type, mode); +} + +void ipq9574_ppe_interface_mode_init(void) +{ + uint32_t mode0, mode1, mode2; + int node; + node = fdt_path_offset(gd->fdt_blob, "/ess-switch"); + if (node < 0) { + printf("\nError: ess-switch not specified in dts"); + return; + } + + mode0 = fdtdec_get_uint(gd->fdt_blob, node, "switch_mac_mode0", -1); + if (mode0 < 0) { + printf("\nError: switch_mac_mode0 not specified in dts"); + return; + } + + mode1 = fdtdec_get_uint(gd->fdt_blob, node, "switch_mac_mode1", -1); + if (mode1 < 0) { + printf("\nError: switch_mac_mode1 not specified in dts"); + return; + } + + mode2 = fdtdec_get_uint(gd->fdt_blob, node, "switch_mac_mode2", -1); + if (mode1 < 0) { + printf("\nError: switch_mac_mode2 not specified in dts"); + return; + } + + uniphy_force_mode = fdtdec_get_uint(gd->fdt_blob, node, + "uniphy_force_mode", -1); + + ppe_uniphy_mode_set(PPE_UNIPHY_INSTANCE0, mode0); + ppe_uniphy_mode_set(PPE_UNIPHY_INSTANCE1, mode1); + ppe_uniphy_mode_set(PPE_UNIPHY_INSTANCE2, mode2); + + /* + * + * Port 1-4 are used mac type as GMAC by default but + * Port5 and Port6 can be used as GMAC or XGMAC. + */ + ppe_port_mux_mac_type_set(PORT1, mode0); + ppe_port_mux_mac_type_set(PORT2, mode0); + ppe_port_mux_mac_type_set(PORT3, mode0); + ppe_port_mux_mac_type_set(PORT4, mode0); + if (mode1 == EPORT_WRAPPER_MAX) { + if (mode0 != EPORT_WRAPPER_UQXGMII) { + ppe_port_mux_mac_type_set(PORT5, mode0); + uniphy_port5_clock_source_set(); + } + } else if (is_uniphy_enabled(PPE_UNIPHY_INSTANCE1)) { + ppe_port_mux_mac_type_set(PORT5, mode1); + } + if (is_uniphy_enabled(PPE_UNIPHY_INSTANCE2)) { + ppe_port_mux_mac_type_set(PORT6, mode2); + } +} + +/* + * ipq9574_ppe_provision_init() + */ +void ipq9574_ppe_provision_init(void) +{ + int i; + uint32_t queue; + int node, tdm_mode = 0; + + node = fdt_path_offset(gd->fdt_blob, "/ess-switch"); + if (node < 0) { + printf("\nError: ess-switch not specified in dts"); + return; + } + + tdm_mode = fdtdec_get_uint(gd->fdt_blob, node, "tdm_mode", 0); + if (tdm_mode < 0) { + printf("\nError:tdm mode not specified in dts assume tdm 0"); + } + + /* tdm/sched configuration */ + if (tdm_mode == 1) + ipq9574_ppe_tdm1_configuration(); + else + ipq9574_ppe_tdm_configuration(); + +#ifdef CONFIG_IPQ9574_BRIDGED_MODE + /* Add CPU port 0 to VSI 2 */ + ipq9574_ppe_vp_port_tbl_set(0, 2); + + /* Add port 1 - 4 to VSI 2 */ + ipq9574_ppe_vp_port_tbl_set(1, 2); + ipq9574_ppe_vp_port_tbl_set(2, 2); + ipq9574_ppe_vp_port_tbl_set(3, 2); + ipq9574_ppe_vp_port_tbl_set(4, 2); + ipq9574_ppe_vp_port_tbl_set(5, 2); + ipq9574_ppe_vp_port_tbl_set(6, 2); + +#else + ipq9574_ppe_vp_port_tbl_set(1, 2); + ipq9574_ppe_vp_port_tbl_set(2, 3); + ipq9574_ppe_vp_port_tbl_set(3, 4); + ipq9574_ppe_vp_port_tbl_set(4, 5); + ipq9574_ppe_vp_port_tbl_set(5, 6); + ipq9574_ppe_vp_port_tbl_set(6, 7); +#endif + + /* Unicast priority map */ + ipq9574_ppe_reg_write(IPQ9574_PPE_QM_UPM_TBL, 0); + + /* Port0 - 7 unicast queue settings */ + for (i = 0; i < 8; i++) { + if (i == 0) + queue = 0; + else + queue = ((i * 0x10) + 0x70); + + ipq9574_ppe_ucast_queue_map_tbl_queue_id_set(queue, i); + ipq9574_ppe_flow_port_map_tbl_port_num_set(queue, i); + ipq9574_ppe_flow_map_tbl_set(queue, i); + ipq9574_ppe_c_sp_cfg_tbl_drr_id_set(i); + ipq9574_ppe_e_sp_cfg_tbl_drr_id_set(i); + } + + /* Port0 multicast queue */ + ipq9574_ppe_reg_write(0x409000, 0x00000000); + ipq9574_ppe_reg_write(0x403000, 0x00401000); + + /* Port1 - 7 multicast queue */ + for (i = 1; i < 8; i++) { + ipq9574_ppe_reg_write(0x409100 + ((i - 1) * 0x40), i); + ipq9574_ppe_reg_write(0x403100 + ((i - 1) * 0x40), 0x401000 | i); + } + + /* ac enable for queues - disable queue tail drop */ + ipq9574_ppe_queue_ac_enable(); + + /* enable queue counter */ + ipq9574_ppe_reg_write(0x020044,0x4); + + /* assign the ac group 0 with buffer number */ + ipq9574_ppe_reg_write(0x84c000, 0x0); + ipq9574_ppe_reg_write(0x84c004, 0x7D00); + ipq9574_ppe_reg_write(0x84c008, 0x0); + ipq9574_ppe_reg_write(0x84c00c, 0x0); + + /* enable physical/virtual port TX/RX counters for all ports (0-6) */ + ipq9574_ppe_enable_port_counter(); + + /* + * Port0 - TX_EN is set by default, Port1 - LRN_EN is set + * Port0 -> CPU Port + * Port1-6 -> Ethernet Ports + * Port7 -> EIP197 + */ + for (i = 0; i < 8; i++) { + if (i == 0) + ipq9574_ppe_reg_write(IPQ9574_PPE_PORT_BRIDGE_CTRL_OFFSET + (i * 4), + IPQ9574_PPE_PORT_BRIDGE_CTRL_PROMISC_EN | + IPQ9574_PPE_PORT_BRIDGE_CTRL_TXMAC_EN | + IPQ9574_PPE_PORT_BRIDGE_CTRL_PORT_ISOLATION_BMP | + IPQ9574_PPE_PORT_BRIDGE_CTRL_STATION_LRN_EN | + IPQ9574_PPE_PORT_BRIDGE_CTRL_NEW_ADDR_LRN_EN); + else if (i == 7) + ipq9574_ppe_reg_write(IPQ9574_PPE_PORT_BRIDGE_CTRL_OFFSET + (i * 4), + IPQ9574_PPE_PORT_BRIDGE_CTRL_PROMISC_EN | + IPQ9574_PPE_PORT_BRIDGE_CTRL_PORT_ISOLATION_BMP | + IPQ9574_PPE_PORT_BRIDGE_CTRL_STATION_LRN_EN | + IPQ9574_PPE_PORT_BRIDGE_CTRL_NEW_ADDR_LRN_EN); + else + ipq9574_ppe_reg_write(IPQ9574_PPE_PORT_BRIDGE_CTRL_OFFSET + (i * 4), + IPQ9574_PPE_PORT_BRIDGE_CTRL_PROMISC_EN | + IPQ9574_PPE_PORT_BRIDGE_CTRL_PORT_ISOLATION_BMP); + } + + /* Global learning */ + ipq9574_ppe_reg_write(0x060038, 0xc0); + +#ifdef CONFIG_IPQ9574_BRIDGED_MODE + ipq9574_vsi_setup(2, 0x7f); +#else + ipq9574_vsi_setup(2, 0x03); + ipq9574_vsi_setup(3, 0x05); + ipq9574_vsi_setup(4, 0x09); + ipq9574_vsi_setup(5, 0x11); + ipq9574_vsi_setup(6, 0x21); + ipq9574_vsi_setup(7, 0x41); +#endif + + /* Port 0-7 STP */ + for (i = 0; i < 8; i++) + ipq9574_ppe_reg_write(IPQ9574_PPE_STP_BASE + (0x4 * i), 0x3); + + ipq9574_ppe_interface_mode_init(); + /* Port 1-6 disable */ + for (i = 0; i < 6; i++) { + ipq9574_gmac_port_disable(i); + ppe_port_bridge_txmac_set(i + 1, 1); + } + + /* Allowing DHCP packets */ + ipq9574_ppe_acl_set(0, ADPT_ACL_HPPE_IPV4_DIP_RULE, UDP_PKT, 67, 0xffff, 0, 0); + ipq9574_ppe_acl_set(1, ADPT_ACL_HPPE_IPV4_DIP_RULE, UDP_PKT, 68, 0xffff, 0, 0); + /* Dropping all the UDP packets */ + ipq9574_ppe_acl_set(2, ADPT_ACL_HPPE_IPV4_DIP_RULE, UDP_PKT, 0, 0, 0, 1); +} diff --git a/sources/uboot-be550/drivers/net/ipq9574/ipq9574_ppe.h b/sources/uboot-be550/drivers/net/ipq9574/ipq9574_ppe.h new file mode 100644 index 00000000..1f39125e --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq9574/ipq9574_ppe.h @@ -0,0 +1,267 @@ +/* + ************************************************************************** + * Copyright (c) 2016-2019, 2021, The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + ************************************************************************** +*/ + +#include +#include +#include +#include +#include +#include +#include + +#define IPQ9574_PORT5_MUX_PCS_UNIPHY0 0x0 +#define IPQ9574_PORT5_MUX_PCS_UNIPHY1 0x1 + +#define PORT_GMAC_TYPE 1 +#define PORT_XGMAC_TYPE 2 + +#define IPQ9574_PORT_MUX_MAC_TYPE 0 +#define IPQ9574_PORT_MUX_XMAC_TYPE 1 + +struct port_mux_ctrl { + uint32_t port1_pcs_sel:1; + uint32_t port2_pcs_sel:1; + uint32_t port3_pcs_sel:1; + uint32_t port4_pcs_sel:1; + uint32_t port5_pcs_sel:1; + uint32_t port6_pcs_sel:1; + uint32_t _reserved0:2; + uint32_t port1_mac_sel:1; + uint32_t port2_mac_sel:1; + uint32_t port3_mac_sel:1; + uint32_t port4_mac_sel:1; + uint32_t port5_mac_sel:1; + uint32_t port6_mac_sel:1; + uint32_t _reserved1:18; +}; + +union port_mux_ctrl_u { + uint32_t val; + struct port_mux_ctrl bf; +}; + +enum { + TCP_PKT, + UDP_PKT, +}; + +#define ADPT_ACL_HPPE_IPV4_DIP_RULE 4 +#define ADPT_ACL_HPPE_MAC_SA_RULE 1 +#define ADPT_ACL_HPPE_MAC_DA_RULE 0 +#define MAX_RULE 512 + +struct ipo_rule_reg { + uint32_t rule_field_0:32; + uint32_t rule_field_1:20; + uint32_t fake_mac_header:1; + uint32_t range_en:1; + uint32_t inverse_en:1; + uint32_t rule_type:5; + uint32_t src_type:3; + uint32_t src_0:1; + uint32_t src_1:7; + uint32_t pri:9; + uint32_t res_chain:1; + uint32_t post_routing_en:1; + uint32_t _reserved0:14; +}; + +union ipo_rule_reg_u { + uint32_t val[3]; + struct ipo_rule_reg bf; +}; + +struct ipo_mask_reg { + uint32_t maskfield_0:32; + uint32_t maskfield_1:21; + uint32_t _reserved0:11; +}; + +union ipo_mask_reg_u { + uint32_t val[2]; + struct ipo_mask_reg bf; +}; + +struct ipo_action { + uint32_t dest_info_change_en:1; + uint32_t fwd_cmd:2; + uint32_t _reserved0:15; + uint32_t bypass_bitmap_0:14; + uint32_t bypass_bitmap_1:18; + uint32_t _reserved1:14; + uint32_t _reserved2:32; + uint32_t _reserved3:32; + uint32_t _reserved4:32; +}; + +union ipo_action_u { + uint32_t val[5]; + struct ipo_action bf; +}; + +#define IPQ9574_PORT_MUX_CTRL 0x10 +#define IPQ9574_PORT_MUX_CTRL_NUM 1 +#define IPQ9574_PORT_MUX_CTRL_INC 0x4 +#define IPQ9574_PORT_MUX_CTRL_DEFAULT 0x0 + +#define PORT_PHY_STATUS0_ADDRESS 0x40 +#define PORT_PHY_STATUS_ADDRESS 0x44 +#define PORT_PHY_STATUS_PORT5_1_OFFSET 8 +#define PORT_PHY_STATUS_PORT6_OFFSET 16 + +#define IPQ9574_PPE_IPE_L3_BASE_ADDR 0x200000 +#define IPQ9574_PPE_L3_VP_PORT_TBL_ADDR (IPQ9574_PPE_IPE_L3_BASE_ADDR + 0x4000) +#define IPQ9574_PPE_L3_VP_PORT_TBL_INC 0x10 + +#define IPQ9574_PPE_TL_PORT_VP_TBL_ADDR 0x302000 +#define IPQ9574_PPE_MRU_MTU_CTRL_TBL_ADDR 0x65000 +#define IPQ9574_PPE_MC_MTU_CTRL_TBL_ADDR 0x60a00 +#define IPQ9574_PPE_PORT_EG_VLAN_TBL_ADDR 0x20020 + +#define IPQ9574_PPE_UCAST_QUEUE_AC_EN_BASE_ADDR 0x848000 +#define IPQ9574_PPE_MCAST_QUEUE_AC_EN_BASE_ADDR 0x84a000 +#define IPQ9574_PPE_QUEUE_MANAGER_BASE_ADDR 0x800000 +#define IPQ9574_PPE_UCAST_QUEUE_MAP_TBL_ADDR 0x10000 +#define IPQ9574_PPE_UCAST_QUEUE_MAP_TBL_INC 0x10 +#define IPQ9574_PPE_QM_UQM_TBL (IPQ9574_PPE_QUEUE_MANAGER_BASE_ADDR +\ + IPQ9574_PPE_UCAST_QUEUE_MAP_TBL_ADDR) +#define IPQ9574_PPE_UCAST_PRIORITY_MAP_TBL_ADDR 0x42000 +#define IPQ9574_PPE_QM_UPM_TBL (IPQ9574_PPE_QUEUE_MANAGER_BASE_ADDR +\ + IPQ9574_PPE_UCAST_PRIORITY_MAP_TBL_ADDR) + +#define IPQ9574_PPE_STP_BASE 0x060100 +#define IPQ9574_PPE_MAC_ENABLE 0x001000 +#define IPQ9574_PPE_MAC_SPEED 0x001004 +#define IPQ9574_PPE_MAC_MIB_CTL 0x001034 + +#define IPQ9574_PPE_TRAFFIC_MANAGER_BASE_ADDR 0x400000 +#define IPQ9574_PPE_TM_SHP_CFG_L0_OFFSET 0x00000030 +#define IPQ9574_PPE_TM_SHP_CFG_L1_OFFSET 0x00000034 +#define IPQ9574_PPE_TM_SHP_CFG_L0 IPQ9574_PPE_TRAFFIC_MANAGER_BASE_ADDR +\ + IPQ9574_PPE_TM_SHP_CFG_L0_OFFSET +#define IPQ9574_PPE_TM_SHP_CFG_L1 IPQ9574_PPE_TRAFFIC_MANAGER_BASE_ADDR +\ + IPQ9574_PPE_TM_SHP_CFG_L1_OFFSET + +#define IPQ9574_PPE_L0_FLOW_PORT_MAP_TBL_ADDR 0x10000 +#define IPQ9574_PPE_L0_FLOW_PORT_MAP_TBL_INC 0x10 +#define IPQ9574_PPE_L0_FLOW_PORT_MAP_TBL (IPQ9574_PPE_TRAFFIC_MANAGER_BASE_ADDR +\ + IPQ9574_PPE_L0_FLOW_PORT_MAP_TBL_ADDR) + +#define IPQ9574_PPE_L0_FLOW_MAP_TBL_ADDR 0x2000 +#define IPQ9574_PPE_L0_FLOW_MAP_TBL_INC 0x10 +#define IPQ9574_PPE_L0_FLOW_MAP_TBL (IPQ9574_PPE_TRAFFIC_MANAGER_BASE_ADDR +\ + IPQ9574_PPE_L0_FLOW_MAP_TBL_ADDR) + +#define IPQ9574_PPE_L1_FLOW_PORT_MAP_TBL_ADDR 0x46000 +#define IPQ9574_PPE_L1_FLOW_PORT_MAP_TBL_INC 0x10 +#define IPQ9574_PPE_L1_FLOW_PORT_MAP_TBL (IPQ9574_PPE_TRAFFIC_MANAGER_BASE_ADDR +\ + IPQ9574_PPE_L1_FLOW_PORT_MAP_TBL_ADDR) + +#define IPQ9574_PPE_L1_FLOW_MAP_TBL_ADDR 0x40000 +#define IPQ9574_PPE_L1_FLOW_MAP_TBL_INC 0x10 +#define IPQ9574_PPE_L1_FLOW_MAP_TBL (IPQ9574_PPE_TRAFFIC_MANAGER_BASE_ADDR +\ + IPQ9574_PPE_L1_FLOW_MAP_TBL_ADDR) + +#define IPQ9574_PPE_L0_C_SP_CFG_TBL_ADDR 0x4000 +#define IPQ9574_PPE_L0_C_SP_CFG_TBL (IPQ9574_PPE_TRAFFIC_MANAGER_BASE_ADDR +\ + IPQ9574_PPE_L0_C_SP_CFG_TBL_ADDR) + +#define IPQ9574_PPE_L1_C_SP_CFG_TBL_ADDR 0x42000 +#define IPQ9574_PPE_L1_C_SP_CFG_TBL (IPQ9574_PPE_TRAFFIC_MANAGER_BASE_ADDR +\ + IPQ9574_PPE_L1_C_SP_CFG_TBL_ADDR) + +#define IPQ9574_PPE_L0_E_SP_CFG_TBL_ADDR 0x6000 +#define IPQ9574_PPE_L0_E_SP_CFG_TBL (IPQ9574_PPE_TRAFFIC_MANAGER_BASE_ADDR +\ + IPQ9574_PPE_L0_E_SP_CFG_TBL_ADDR) + +#define IPQ9574_PPE_L1_E_SP_CFG_TBL_ADDR 0x44000 +#define IPQ9574_PPE_L1_E_SP_CFG_TBL (IPQ9574_PPE_TRAFFIC_MANAGER_BASE_ADDR +\ + IPQ9574_PPE_L1_E_SP_CFG_TBL_ADDR) + +#define IPQ9574_PPE_FPGA_GPIO_BASE_ADDR 0x01008000 + +#define IPQ9574_PPE_MAC_PORT_MUX_OFFSET 0x10 +#define IPQ9574_PPE_FPGA_GPIO_OFFSET 0xc000 +#define IPQ9574_PPE_FPGA_SCHED_OFFSET 0x47a000 +#define IPQ9574_PPE_TDM_CFG_DEPTH_OFFSET 0xb000 +#define IPQ9574_PPE_TDM_SCHED_DEPTH_OFFSET 0x400000 +#define IPQ9574_PPE_PORT_BRIDGE_CTRL_OFFSET 0x060300 + +#define IPQ9574_PPE_TDM_CFG_DEPTH_VAL 0x80000064 +#define IPQ9574_PPE_MAC_PORT_MUX_OFFSET_VAL 0x15 +#define IPQ9574_PPE_TDM_SCHED_DEPTH_VAL 0x32 +#define IPQ9574_PPE_TDM_CFG_VALID 0x20 +#define IPQ9574_PPE_TDM_CFG_DIR_INGRESS 0x0 +#define IPQ9574_PPE_TDM_CFG_DIR_EGRESS 0x10 +#define IPQ9574_PPE_PORT_EDMA 0x0 +#define IPQ9574_PPE_PORT_QTI1 0x1 +#define IPQ9574_PPE_PORT_QTI2 0x2 +#define IPQ9574_PPE_PORT_QTI3 0x3 +#define IPQ9574_PPE_PORT_QTI4 0x4 +#define IPQ9574_PPE_PORT_XGMAC1 0x5 +#define IPQ9574_PPE_PORT_XGMAC2 0x6 +#define IPQ9574_PPE_PORT_CRYPTO1 0x7 +#define IPQ9574_PPE_PORT_BRIDGE_CTRL_PROMISC_EN 0x20000 +#define IPQ9574_PPE_PORT_BRIDGE_CTRL_TXMAC_EN 0x10000 +#define IPQ9574_PPE_PORT_BRIDGE_CTRL_PORT_ISOLATION_BMP 0x7f00 +#define IPQ9574_PPE_PORT_BRIDGE_CTRL_STATION_LRN_EN 0x8 +#define IPQ9574_PPE_PORT_BRIDGE_CTRL_NEW_ADDR_LRN_EN 0x1 + +#define IPQ9574_PPE_PORT_EDMA_BITPOS 0x1 +#define IPQ9574_PPE_PORT_QTI1_BITPOS (1 << IPQ9574_PPE_PORT_QTI1) +#define IPQ9574_PPE_PORT_QTI2_BITPOS (1 << IPQ9574_PPE_PORT_QTI2) +#define IPQ9574_PPE_PORT_QTI3_BITPOS (1 << IPQ9574_PPE_PORT_QTI3) +#define IPQ9574_PPE_PORT_QTI4_BITPOS (1 << IPQ9574_PPE_PORT_QTI4) +#define IPQ9574_PPE_PORT_XGMAC1_BITPOS (1 << IPQ9574_PPE_PORT_XGMAC1) +#define IPQ9574_PPE_PORT_XGMAC2_BITPOS (1 << IPQ9574_PPE_PORT_XGMAC2) +#define IPQ9574_PPE_PORT_CRYPTO1_BITPOS (1 << IPQ9574_PPE_PORT_CRYPTO1) + +#define PPE_SWITCH_NSS_SWITCH_XGMAC0 0x500000 +#define NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION 0x4000 +#define USS (1 << 31) +#define SS(i) (i << 29) +#define JD (1 << 16) +#define TE (1 << 0) +#define NSS_SWITCH_XGMAC_MAC_RX_CONFIGURATION 0x4000 +#define MAC_RX_CONFIGURATION_ADDRESS 0x4 +#define RE (1 << 0) +#define ACS (1 << 1) +#define CST (1 << 2) +#define MAC_PACKET_FILTER_INC 0x4000 +#define MAC_PACKET_FILTER_ADDRESS 0x8 + +#define XGMAC_SPEED_SELECT_10000M 0 +#define XGMAC_SPEED_SELECT_5000M 1 +#define XGMAC_SPEED_SELECT_2500M 2 +#define XGMAC_SPEED_SELECT_1000M 3 + +#define IPE_L2_BASE_ADDR 0x060000 +#define PORT_BRIDGE_CTRL_ADDRESS 0x300 +#define PORT_BRIDGE_CTRL_INC 0x4 +#define TX_MAC_EN (1 << 16) + +#define IPO_CSR_BASE_ADDR 0x0b0000 + +#define IPO_RULE_REG_ADDRESS 0x0 +#define IPO_RULE_REG_INC 0x10 + +#define IPO_MASK_REG_ADDRESS 0x2000 +#define IPO_MASK_REG_INC 0x10 + +#define IPO_ACTION_ADDRESS 0x8000 +#define IPO_ACTION_INC 0x20 diff --git a/sources/uboot-be550/drivers/net/ipq9574/ipq9574_qca8075.c b/sources/uboot-be550/drivers/net/ipq9574/ipq9574_qca8075.c new file mode 100644 index 00000000..25a91351 --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq9574/ipq9574_qca8075.c @@ -0,0 +1,584 @@ +/* + * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. + + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. +*/ +#include +#include +#include +#include +#include +#include +#include +#include "ipq_phy.h" +#include "ipq9574_qca8075.h" + +extern int ipq_mdio_write(int mii_id, + int regnum, u16 value); +extern int ipq_mdio_read(int mii_id, + int regnum, ushort *data); + +struct phy_ops *ipq9574_qca8075_ops; +static u32 ipq9574_qca8075_id; +static u16 ipq9574_qca8075_phy_reg_write(u32 dev_id, u32 phy_id, + u32 reg_id, u16 reg_val) +{ + ipq_mdio_write(phy_id, reg_id, reg_val); + return 0; +} + +static u16 ipq9574_qca8075_phy_reg_read(u32 dev_id, u32 phy_id, u32 reg_id) +{ + return ipq_mdio_read(phy_id, reg_id, NULL); +} + +/* + * phy4 prfer medium + * get phy4 prefer medum, fiber or copper; + */ +static qca8075_phy_medium_t __phy_prefer_medium_get(u32 dev_id, + u32 phy_id) +{ + u16 phy_medium; + phy_medium = + ipq9574_qca8075_phy_reg_read(dev_id, phy_id, + QCA8075_PHY_CHIP_CONFIG); + + return ((phy_medium & QCA8075_PHY4_PREFER_FIBER) ? + QCA8075_PHY_MEDIUM_FIBER : QCA8075_PHY_MEDIUM_COPPER); +} + +/* + * phy4 activer medium + * get phy4 current active medium, fiber or copper; + */ +static qca8075_phy_medium_t __phy_active_medium_get(u32 dev_id, + u32 phy_id) +{ + u16 phy_data = 0; + u32 phy_mode; + + phy_mode = ipq9574_qca8075_phy_reg_read(dev_id, phy_id, + QCA8075_PHY_CHIP_CONFIG); + phy_mode &= 0x000f; + + if (phy_mode == QCA8075_PHY_PSGMII_AMDET) { + phy_data = ipq9574_qca8075_phy_reg_read(dev_id, + phy_id, QCA8075_PHY_SGMII_STATUS); + + if ((phy_data & QCA8075_PHY4_AUTO_COPPER_SELECT)) { + return QCA8075_PHY_MEDIUM_COPPER; + } else if ((phy_data & QCA8075_PHY4_AUTO_BX1000_SELECT)) { + /* PHY_MEDIUM_FIBER_BX1000 */ + return QCA8075_PHY_MEDIUM_FIBER; + } else if ((phy_data & QCA8075_PHY4_AUTO_FX100_SELECT)) { + /* PHY_MEDIUM_FIBER_FX100 */ + return QCA8075_PHY_MEDIUM_FIBER; + } + /* link down */ + return __phy_prefer_medium_get(dev_id, phy_id); + } else if ((phy_mode == QCA8075_PHY_PSGMII_BASET) || + (phy_mode == QCA8075_PHY_SGMII_BASET)) { + return QCA8075_PHY_MEDIUM_COPPER; + } else if ((phy_mode == QCA8075_PHY_PSGMII_BX1000) || + (phy_mode == QCA8075_PHY_PSGMII_FX100)) { + return QCA8075_PHY_MEDIUM_FIBER; + } else { + return QCA8075_PHY_MEDIUM_COPPER; + } +} + +/* + * phy4 copper page or fiber page select + * set phy4 copper or fiber page + */ + +static u8 __phy_reg_pages_sel(u32 dev_id, u32 phy_id, + qca8075_phy_reg_pages_t phy_reg_pages) +{ + u16 reg_pages; + reg_pages = ipq9574_qca8075_phy_reg_read(dev_id, + phy_id, QCA8075_PHY_CHIP_CONFIG); + + if (phy_reg_pages == QCA8075_PHY_COPPER_PAGES) { + reg_pages |= 0x8000; + } else if (phy_reg_pages == QCA8075_PHY_SGBX_PAGES) { + reg_pages &= ~0x8000; + } else + return -EINVAL; + + ipq9574_qca8075_phy_reg_write(dev_id, phy_id, + QCA8075_PHY_CHIP_CONFIG, reg_pages); + return 0; +} + +/* + * phy4 reg pages selection by active medium + * phy4 reg pages selection + */ +static u32 __phy_reg_pages_sel_by_active_medium(u32 dev_id, + u32 phy_id) +{ + qca8075_phy_medium_t phy_medium; + qca8075_phy_reg_pages_t reg_pages; + + phy_medium = __phy_active_medium_get(dev_id, phy_id); + if (phy_medium == QCA8075_PHY_MEDIUM_FIBER) { + reg_pages = QCA8075_PHY_SGBX_PAGES; + } else if (phy_medium == QCA8075_PHY_MEDIUM_COPPER) { + reg_pages = QCA8075_PHY_COPPER_PAGES; + } else { + return -1; + } + + return __phy_reg_pages_sel(dev_id, phy_id, reg_pages); +} + +static u8 ipq9574_qca8075_phy_get_link_status(u32 dev_id, u32 phy_id) +{ + u16 phy_data; + if (phy_id == COMBO_PHY_ID) + __phy_reg_pages_sel_by_active_medium(dev_id, phy_id); + phy_data = ipq9574_qca8075_phy_reg_read(dev_id, + phy_id, QCA8075_PHY_SPEC_STATUS); + if (phy_data & QCA8075_STATUS_LINK_PASS) + return 0; + + return 1; +} + +static u32 ipq9574_qca8075_phy_get_duplex(u32 dev_id, u32 phy_id, + fal_port_duplex_t * duplex) +{ + u16 phy_data; + + if (phy_id == COMBO_PHY_ID) { + __phy_reg_pages_sel_by_active_medium(dev_id, phy_id); + } + + phy_data = ipq9574_qca8075_phy_reg_read(dev_id, phy_id, + QCA8075_PHY_SPEC_STATUS); + + /* + * Read duplex + */ + if (phy_data & QCA8075_STATUS_FULL_DUPLEX) + *duplex = FAL_FULL_DUPLEX; + else + *duplex = FAL_HALF_DUPLEX; + + return 0; +} + +static u32 ipq9574_qca8075_phy_get_speed(u32 dev_id, u32 phy_id, + fal_port_speed_t * speed) +{ + u16 phy_data; + + if (phy_id == COMBO_PHY_ID) { + __phy_reg_pages_sel_by_active_medium(dev_id, phy_id); + } + phy_data = ipq9574_qca8075_phy_reg_read(dev_id, + phy_id, QCA8075_PHY_SPEC_STATUS); + + switch (phy_data & QCA8075_STATUS_SPEED_MASK) { + case QCA8075_STATUS_SPEED_1000MBS: + *speed = FAL_SPEED_1000; + break; + case QCA8075_STATUS_SPEED_100MBS: + *speed = FAL_SPEED_100; + break; + case QCA8075_STATUS_SPEED_10MBS: + *speed = FAL_SPEED_10; + break; + default: + return -EINVAL; + } + return 0; +} + +static u32 ipq9574_qca8075_phy_mmd_write(u32 dev_id, u32 phy_id, + u16 mmd_num, u16 reg_id, u16 reg_val) +{ + ipq9574_qca8075_phy_reg_write(dev_id, phy_id, + QCA8075_MMD_CTRL_REG, mmd_num); + ipq9574_qca8075_phy_reg_write(dev_id, phy_id, + QCA8075_MMD_DATA_REG, reg_id); + ipq9574_qca8075_phy_reg_write(dev_id, phy_id, + QCA8075_MMD_CTRL_REG, + 0x4000 | mmd_num); + ipq9574_qca8075_phy_reg_write(dev_id, phy_id, + QCA8075_MMD_DATA_REG, reg_val); + + return 0; +} + +static u16 ipq9574_qca8075_phy_mmd_read(u32 dev_id, u32 phy_id, + u16 mmd_num, u16 reg_id) +{ + ipq9574_qca8075_phy_reg_write(dev_id, phy_id, + QCA8075_MMD_CTRL_REG, mmd_num); + ipq9574_qca8075_phy_reg_write(dev_id, phy_id, + QCA8075_MMD_DATA_REG, reg_id); + ipq9574_qca8075_phy_reg_write(dev_id, phy_id, + QCA8075_MMD_CTRL_REG, + 0x4000 | mmd_num); + return ipq9574_qca8075_phy_reg_read(dev_id, phy_id, + QCA8075_MMD_DATA_REG); +} + +/* + * get phy4 medium is 100fx + */ +static u8 __medium_is_fiber_100fx(u32 dev_id, u32 phy_id) +{ + u16 phy_data; + phy_data = ipq9574_qca8075_phy_reg_read(dev_id, phy_id, + QCA8075_PHY_SGMII_STATUS); + + if (phy_data & QCA8075_PHY4_AUTO_FX100_SELECT) { + return 1; + } + /* Link down */ + if ((!(phy_data & QCA8075_PHY4_AUTO_COPPER_SELECT)) && + (!(phy_data & QCA8075_PHY4_AUTO_BX1000_SELECT)) && + (!(phy_data & QCA8075_PHY4_AUTO_SGMII_SELECT))) { + + phy_data = ipq9574_qca8075_phy_reg_read(dev_id, phy_id, + QCA8075_PHY_CHIP_CONFIG); + if ((phy_data & QCA8075_PHY4_PREFER_FIBER) + && (!(phy_data & QCA8075_PHY4_FIBER_MODE_1000BX))) { + return 1; + } + } + return 0; +} + +/* + * ipq9574_qca8075_phy_set_hibernate - set hibernate status + * set hibernate status + */ +static u32 ipq9574_qca8075_phy_set_hibernate(u32 dev_id, u32 phy_id, u8 enable) +{ + u16 phy_data; + + ipq9574_qca8075_phy_reg_write(dev_id, phy_id, QCA8075_DEBUG_PORT_ADDRESS, + QCA8075_DEBUG_PHY_HIBERNATION_CTRL); + + phy_data = ipq9574_qca8075_phy_reg_read(dev_id, phy_id, + QCA8075_DEBUG_PORT_DATA); + + if (enable) { + phy_data |= 0x8000; + } else { + phy_data &= ~0x8000; + } + + ipq9574_qca8075_phy_reg_write(dev_id, phy_id, QCA8075_DEBUG_PORT_DATA, phy_data); + return 0; +} + +/* + * ipq9574_qca8075_restart_autoneg - restart the phy autoneg + */ +static u32 ipq9574_qca8075_phy_restart_autoneg(u32 dev_id, u32 phy_id) +{ + u16 phy_data; + + if (phy_id == COMBO_PHY_ID) { + if (__medium_is_fiber_100fx(dev_id, phy_id)) + return -1; + __phy_reg_pages_sel_by_active_medium(dev_id, phy_id); + } + phy_data = ipq9574_qca8075_phy_reg_read(dev_id, phy_id, QCA8075_PHY_CONTROL); + phy_data |= QCA8075_CTRL_AUTONEGOTIATION_ENABLE; + ipq9574_qca8075_phy_reg_write(dev_id, phy_id, QCA8075_PHY_CONTROL, + phy_data | QCA8075_CTRL_RESTART_AUTONEGOTIATION); + + return 0; +} + +/* + * ipq9574_qca8075_phy_get_8023az status + * get 8023az status + */ +static u32 ipq9574_qca8075_phy_get_8023az(u32 dev_id, u32 phy_id, u8 *enable) +{ + u16 phy_data; + if (phy_id == COMBO_PHY_ID) { + if (QCA8075_PHY_MEDIUM_COPPER != + __phy_active_medium_get(dev_id, phy_id)) + return -1; + } + *enable = 0; + + phy_data = ipq9574_qca8075_phy_mmd_read(dev_id, phy_id, QCA8075_PHY_MMD7_NUM, + QCA8075_PHY_MMD7_ADDR_8023AZ_EEE_CTRL); + + if ((phy_data & 0x0004) && (phy_data & 0x0002)) + *enable = 1; + + return 0; +} + +/* + * ipq9574_qca8075_phy_set_powersave - set power saving status + */ +static u32 ipq9574_qca8075_phy_set_powersave(u32 dev_id, u32 phy_id, u8 enable) +{ + u16 phy_data; + u8 status = 0; + + if (phy_id == COMBO_PHY_ID) { + if (QCA8075_PHY_MEDIUM_COPPER != + __phy_active_medium_get(dev_id, phy_id)) + return -1; + } + + if (enable) { + ipq9574_qca8075_phy_get_8023az(dev_id, phy_id, &status); + if (!status) { + phy_data = ipq9574_qca8075_phy_mmd_read(dev_id, phy_id, + QCA8075_PHY_MMD3_NUM, + QCA8075_PHY_MMD3_ADDR_8023AZ_TIMER_CTRL); + phy_data &= ~(1 << 14); + ipq9574_qca8075_phy_mmd_write(dev_id, phy_id, + QCA8075_PHY_MMD3_NUM, + QCA8075_PHY_MMD3_ADDR_8023AZ_TIMER_CTRL, + phy_data); + } + phy_data = ipq9574_qca8075_phy_mmd_read(dev_id, phy_id, + QCA8075_PHY_MMD3_NUM, + QCA8075_PHY_MMD3_ADDR_CLD_CTRL5); + phy_data &= ~(1 << 14); + ipq9574_qca8075_phy_mmd_write(dev_id, phy_id, QCA8075_PHY_MMD3_NUM, + QCA8075_PHY_MMD3_ADDR_CLD_CTRL5, + phy_data); + + phy_data = ipq9574_qca8075_phy_mmd_read(dev_id, phy_id, + QCA8075_PHY_MMD3_NUM, + QCA8075_PHY_MMD3_ADDR_CLD_CTRL3); + phy_data &= ~(1 << 15); + ipq9574_qca8075_phy_mmd_write(dev_id, phy_id, QCA8075_PHY_MMD3_NUM, + QCA8075_PHY_MMD3_ADDR_CLD_CTRL3, phy_data); + + } else { + phy_data = ipq9574_qca8075_phy_mmd_read(dev_id, phy_id, + QCA8075_PHY_MMD3_NUM, + QCA8075_PHY_MMD3_ADDR_8023AZ_TIMER_CTRL); + phy_data |= (1 << 14); + ipq9574_qca8075_phy_mmd_write(dev_id, phy_id, QCA8075_PHY_MMD3_NUM, + QCA8075_PHY_MMD3_ADDR_8023AZ_TIMER_CTRL, + phy_data); + + phy_data = ipq9574_qca8075_phy_mmd_read(dev_id, phy_id, + QCA8075_PHY_MMD3_NUM, + QCA8075_PHY_MMD3_ADDR_CLD_CTRL5); + phy_data |= (1 << 14); + ipq9574_qca8075_phy_mmd_write(dev_id, phy_id, QCA8075_PHY_MMD3_NUM, + QCA8075_PHY_MMD3_ADDR_CLD_CTRL5, phy_data); + + phy_data = ipq9574_qca8075_phy_mmd_read(dev_id, phy_id, + QCA8075_PHY_MMD3_NUM, + QCA8075_PHY_MMD3_ADDR_CLD_CTRL3); + phy_data |= (1 << 15); + ipq9574_qca8075_phy_mmd_write(dev_id, phy_id, QCA8075_PHY_MMD3_NUM, + QCA8075_PHY_MMD3_ADDR_CLD_CTRL3, phy_data); + + } + ipq9574_qca8075_phy_reg_write(dev_id, phy_id, QCA8075_PHY_CONTROL, 0x9040); + return 0; +} + +/* + * ipq9574_qca8075_phy_set_802.3az + */ + static u32 ipq9574_qca8075_phy_set_8023az(u32 dev_id, u32 phy_id, u8 enable) +{ + u16 phy_data; + + if (phy_id == COMBO_PHY_ID) { + if (QCA8075_PHY_MEDIUM_COPPER != + __phy_active_medium_get(dev_id, phy_id)) + return -1; + } + phy_data = ipq9574_qca8075_phy_mmd_read(dev_id, phy_id, QCA8075_PHY_MMD7_NUM, + QCA8075_PHY_MMD7_ADDR_8023AZ_EEE_CTRL); + if (enable) { + phy_data |= 0x0006; + + ipq9574_qca8075_phy_mmd_write(dev_id, phy_id, QCA8075_PHY_MMD7_NUM, + QCA8075_PHY_MMD7_ADDR_8023AZ_EEE_CTRL, phy_data); + if (ipq9574_qca8075_id == QCA8075_PHY_V1_0_5P) { + /* + * Workaround to avoid packet loss and < 10m cable + * 1000M link not stable under az enable + */ + ipq9574_qca8075_phy_mmd_write(dev_id, phy_id, + QCA8075_PHY_MMD3_NUM, + QCA8075_PHY_MMD3_ADDR_8023AZ_TIMER_CTRL, + AZ_TIMER_CTRL_ADJUST_VALUE); + + ipq9574_qca8075_phy_mmd_write(dev_id, phy_id, + QCA8075_PHY_MMD3_NUM, + QCA8075_PHY_MMD3_ADDR_8023AZ_CLD_CTRL, + AZ_CLD_CTRL_ADJUST_VALUE); + } + } else { + phy_data &= ~0x0006; + ipq9574_qca8075_phy_mmd_write(dev_id, phy_id, QCA8075_PHY_MMD7_NUM, + QCA8075_PHY_MMD7_ADDR_8023AZ_EEE_CTRL, phy_data); + if (ipq9574_qca8075_id == QCA8075_PHY_V1_0_5P) { + ipq9574_qca8075_phy_mmd_write(dev_id, phy_id, + QCA8075_PHY_MMD3_NUM, + QCA8075_PHY_MMD3_ADDR_8023AZ_TIMER_CTRL, + AZ_TIMER_CTRL_DEFAULT_VALUE); + } + } + ipq9574_qca8075_phy_restart_autoneg(dev_id, phy_id); + return 0; +} + +void ipq9574_qca8075_phy_map_ops(struct phy_ops **ops) +{ + *ops = ipq9574_qca8075_ops; +} + +void ipq9574_qca8075_phy_serdes_reset(u32 phy_id) +{ + ipq9574_qca8075_phy_reg_write(0, + phy_id + QCA8075_PHY_PSGMII_ADDR_INC, + QCA8075_MODE_RESET_REG, + QCA8075_MODE_CHANAGE_RESET); + mdelay(100); + ipq9574_qca8075_phy_reg_write(0, + phy_id + QCA8075_PHY_PSGMII_ADDR_INC, + QCA8075_MODE_RESET_REG, + QCA8075_MODE_RESET_DEFAULT_VALUE); + +} + +static u16 ipq9574_qca8075_phy_interface_get_mode(u32 phy_id) +{ + u16 phy_data; + + phy_data = ipq9574_qca8075_phy_reg_read(0, + phy_id + QCA8075_PHY_MAX_ADDR_INC, + QCA8075_PHY_CHIP_CONFIG); + phy_data &= 0x000f; + return phy_data; +} + +void ipq9574_qca8075_phy_interface_set_mode(u32 phy_id, u32 mode) +{ + u16 phy_data; + + phy_data = ipq9574_qca8075_phy_interface_get_mode(phy_id); + if (phy_data != mode) { + phy_data = ipq9574_qca8075_phy_reg_read(0, + phy_id + QCA8075_PHY_MAX_ADDR_INC, + QCA8075_PHY_CHIP_CONFIG); + phy_data &= 0xfff0; + ipq9574_qca8075_phy_reg_write(0, + phy_id + QCA8075_PHY_MAX_ADDR_INC, + QCA8075_PHY_CHIP_CONFIG, + phy_data | mode); + ipq9574_qca8075_phy_serdes_reset(phy_id); + } +} + +int ipq9574_qca8075_phy_init(struct phy_ops **ops, u32 phy_id) +{ + u16 phy_data; + u32 port_id = 0; + u32 first_phy_id; + + first_phy_id = phy_id; + ipq9574_qca8075_ops = (struct phy_ops *)malloc(sizeof(struct phy_ops)); + if (!ipq9574_qca8075_ops) + return -ENOMEM; + + ipq9574_qca8075_ops->phy_get_link_status = ipq9574_qca8075_phy_get_link_status; + ipq9574_qca8075_ops->phy_get_speed = ipq9574_qca8075_phy_get_speed; + ipq9574_qca8075_ops->phy_get_duplex = ipq9574_qca8075_phy_get_duplex; + *ops = ipq9574_qca8075_ops; + + ipq9574_qca8075_id = phy_data = ipq9574_qca8075_phy_reg_read(0x0, phy_id, QCA8075_PHY_ID1); + printf ("PHY ID1: 0x%x\n", phy_data); + phy_data = ipq9574_qca8075_phy_reg_read(0x0, phy_id, QCA8075_PHY_ID2); + printf ("PHY ID2: 0x%x\n", phy_data); + ipq9574_qca8075_id = (ipq9574_qca8075_id << 16) | phy_data; + + if (ipq9574_qca8075_id == QCA8075_PHY_V1_0_5P) { + phy_data = ipq9574_qca8075_phy_mmd_read(0, PSGMII_ID, + QCA8075_PHY_MMD1_NUM, QCA8075_PSGMII_FIFI_CTRL); + phy_data &= 0xbfff; + ipq9574_qca8075_phy_mmd_write(0, PSGMII_ID, QCA8075_PHY_MMD1_NUM, + QCA8075_PSGMII_FIFI_CTRL, phy_data); + } + + /* + * Enable phy power saving function by default + */ + if ((ipq9574_qca8075_id == QCA8075_PHY_V1_0_5P) || + (ipq9574_qca8075_id == QCA8075_PHY_V1_1_5P) || + (ipq9574_qca8075_id == QCA8075_PHY_V1_1_2P)) { + for (port_id = 0; port_id < 5; port_id++) { + /*enable phy power saving function by default */ + phy_id = first_phy_id + port_id; + ipq9574_qca8075_phy_set_8023az(0x0, phy_id, 0x1); + ipq9574_qca8075_phy_set_powersave(0x0, phy_id, 0x1); + ipq9574_qca8075_phy_set_hibernate(0x0, phy_id, 0x1); + + /* + * change malibu control_dac[2:0] of MMD7 0x801A bit[9:7] + * from 111 to 101 + */ + phy_data = ipq9574_qca8075_phy_mmd_read(0, phy_id, + QCA8075_PHY_MMD7_NUM, QCA8075_PHY_MMD7_DAC_CTRL); + phy_data &= ~QCA8075_DAC_CTRL_MASK; + phy_data |= QCA8075_DAC_CTRL_VALUE; + ipq9574_qca8075_phy_mmd_write(0, phy_id, QCA8075_PHY_MMD7_NUM, + QCA8075_PHY_MMD7_DAC_CTRL, phy_data); + + /* add 10M and 100M link LED behavior for QFN board*/ + phy_data = ipq9574_qca8075_phy_mmd_read(0, phy_id, QCA8075_PHY_MMD7_NUM, + QCA8075_PHY_MMD7_LED_1000_CTRL1); + phy_data &= ~QCA8075_LED_1000_CTRL1_100_10_MASK; + phy_data |= QCA8075_LED_1000_CTRL1_100_10_MASK; + ipq9574_qca8075_phy_mmd_write(0 , phy_id, QCA8075_PHY_MMD7_NUM, + QCA8075_PHY_MMD7_LED_1000_CTRL1, phy_data); + } + } + if ((ipq9574_qca8075_id == QCA8075_PHY_V1_1_2P) && (first_phy_id >= 0x3)) { + phy_id = first_phy_id - 0x3; + } + else { + phy_id = first_phy_id; + } + + /* + * Enable AZ transmitting ability + */ + ipq9574_qca8075_phy_mmd_write(0, phy_id + 5, QCA8075_PHY_MMD1_NUM, + QCA8075_PSGMII_MODE_CTRL, + QCA8075_PHY_PSGMII_MODE_CTRL_ADJUST_VALUE); + + /* adjust psgmii serdes tx amp */ + ipq9574_qca8075_phy_reg_write(0, phy_id + 5, QCA8075_PSGMII_TX_DRIVER_1_CTRL, + QCA8075_PHY_PSGMII_REDUCE_SERDES_TX_AMP); + + /* to avoid psgmii module goes into hibernation, work with psgmii self test*/ + phy_data = ipq9574_qca8075_phy_mmd_read(0, phy_id + 4, QCA8075_PHY_MMD3_NUM, 0x805a); + phy_data &= (~(1 << 1)); + ipq9574_qca8075_phy_mmd_write(0, phy_id + 4, QCA8075_PHY_MMD3_NUM, 0x805a, phy_data); + + return 0; +} diff --git a/sources/uboot-be550/drivers/net/ipq9574/ipq9574_qca8075.h b/sources/uboot-be550/drivers/net/ipq9574/ipq9574_qca8075.h new file mode 100644 index 00000000..1b263268 --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq9574/ipq9574_qca8075.h @@ -0,0 +1,491 @@ +/* + * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. + + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. +*/ + +#ifndef _QCA8075_PHY_H_ +#define _QCA8075_PHY_H_ + +#define QCA8075_PHY_CONTROL 0 +#define QCA8075_PHY_STATUS 1 +#define QCA8075_PHY_ID1 2 +#define QCA8075_PHY_ID2 3 +#define QCA8075_AUTONEG_ADVERT 4 +#define QCA8075_LINK_PARTNER_ABILITY 5 +#define QCA8075_AUTONEG_EXPANSION 6 +#define QCA8075_NEXT_PAGE_TRANSMIT 7 +#define QCA8075_LINK_PARTNER_NEXT_PAGE 8 +#define QCA8075_1000BASET_CONTROL 9 +#define QCA8075_1000BASET_STATUS 10 +#define QCA8075_MMD_CTRL_REG 13 +#define QCA8075_MMD_DATA_REG 14 +#define QCA8075_EXTENDED_STATUS 15 +#define QCA8075_PHY_SPEC_CONTROL 16 +#define QCA8075_PHY_SPEC_STATUS 17 +#define QCA8075_PHY_INTR_MASK 18 +#define QCA8075_PHY_INTR_STATUS 19 +#define QCA8075_PHY_CDT_CONTROL 22 +#define QCA8075_PHY_CDT_STATUS 28 +#define QCA8075_DEBUG_PORT_ADDRESS 29 +#define QCA8075_DEBUG_PORT_DATA 30 +#define COMBO_PHY_ID 4 +#define PSGMII_ID 5 + +#define QCA8075_DEBUG_PHY_HIBERNATION_CTRL 0xb +#define QCA8075_DEBUG_PHY_POWER_SAVING_CTRL 0x29 +#define QCA8075_PHY_MMD7_ADDR_8023AZ_EEE_CTRL 0x3c +#define QCA8075_PHY_MMD3_ADDR_REMOTE_LOOPBACK_CTRL 0x805a +#define QCA8075_PHY_MMD3_WOL_MAGIC_MAC_CTRL1 0x804a +#define QCA8075_PHY_MMD3_WOL_MAGIC_MAC_CTRL2 0x804b +#define QCA8075_PHY_MMD3_WOL_MAGIC_MAC_CTRL3 0x804c +#define QCA8075_PHY_MMD3_WOL_CTRL 0x8012 + +#define QCA8075_PSGMII_FIFI_CTRL 0x6e +#define QCA8075_PSGMII_CALIB_CTRL 0x27 +#define QCA8075_PSGMII_MODE_CTRL 0x6d +#define QCA8075_PHY_PSGMII_MODE_CTRL_ADJUST_VALUE 0x220c + +#define QCA8075_PHY_MMD7_NUM 7 +#define QCA8075_PHY_MMD3_NUM 3 +#define QCA8075_PHY_MMD1_NUM 1 + +#define QCA8075_PHY_SGMII_STATUS 0x1a /* sgmii_status Register */ +#define QCA8075_PHY4_AUTO_SGMII_SELECT 0x40 +#define QCA8075_PHY4_AUTO_COPPER_SELECT 0x20 +#define QCA8075_PHY4_AUTO_BX1000_SELECT 0x10 +#define QCA8075_PHY4_AUTO_FX100_SELECT 0x8 + +#define QCA8075_MODE_RESET_REG 0x0 +#define QCA8075_MODE_CHANAGE_RESET 0x0 +#define QCA8075_MODE_RESET_DEFAULT_VALUE 0x5f +#define QCA8075_PHY_MAX_ADDR_INC 0x4 +#define QCA8075_PHY_PSGMII_ADDR_INC 0x5 + +#define QCA8075_PHY_CHIP_CONFIG 0x1f /* Chip Configuration Register */ +#define BT_BX_SG_REG_SELECT BIT_15 +#define BT_BX_SG_REG_SELECT_OFFSET 15 +#define BT_BX_SG_REG_SELECT_LEN 1 +#define QCA8075_SG_BX_PAGES 0x0 +#define QCA8075_SG_COPPER_PAGES 0x1 + +#define QCA8075_PHY_PSGMII_BASET 0x0 +#define QCA8075_PHY_PSGMII_BX1000 0x1 +#define QCA8075_PHY_PSGMII_FX100 0x2 +#define QCA8075_PHY_PSGMII_AMDET 0x3 +#define QCA8075_PHY_SGMII_BASET 0x4 + +#define QCA8075_PHY4_PREFER_FIBER 0x400 +#define PHY4_PREFER_COPPER 0x0 +#define PHY4_PREFER_FIBER 0x1 + +#define QCA8075_PHY4_FIBER_MODE_1000BX 0x100 +#define AUTO_100FX_FIBER 0x0 +#define AUTO_1000BX_FIBER 0x1 + +#define QCA8075_PHY_MDIX 0x0020 +#define QCA8075_PHY_MDIX_AUTO 0x0060 +#define QCA8075_PHY_MDIX_STATUS 0x0040 + +#define MODE_CFG_QUAL BIT_4 +#define MODE_CFG_QUAL_OFFSET 4 +#define MODE_CFG_QUAL_LEN 4 + +#define MODE_CFG BIT_0 +#define MODE_CFG_OFFSET 0 +#define MODE_CFG_LEN 4 + +#define QCA8075_PHY_MMD3_ADDR_8023AZ_CLD_CTRL 0x8007 +#define QCA8075_PHY_MMD3_ADDR_8023AZ_TIMER_CTRL 0x804e +#define QCA8075_PHY_MMD3_ADDR_CLD_CTRL5 0x8005 +#define QCA8075_PHY_MMD3_ADDR_CLD_CTRL3 0x8003 + +#define AZ_TIMER_CTRL_DEFAULT_VALUE 0x3062 +#define AZ_CLD_CTRL_DEFAULT_VALUE 0x83f6 +#define AZ_TIMER_CTRL_ADJUST_VALUE 0x7062 +#define AZ_CLD_CTRL_ADJUST_VALUE 0x8396 + + /*debug port */ +#define QCA8075_DEBUG_PORT_RGMII_MODE 18 +#define QCA8075_DEBUG_PORT_RGMII_MODE_EN 0x0008 + +#define QCA8075_DEBUG_PORT_RX_DELAY 0 +#define QCA8075_DEBUG_PORT_RX_DELAY_EN 0x8000 + +#define QCA8075_DEBUG_PORT_TX_DELAY 5 +#define QCA8075_DEBUG_PORT_TX_DELAY_EN 0x0100 + + /* PHY Registers Field */ + + /* Control Register fields offset:0 */ + /* bits 6,13: 10=1000, 01=100, 00=10 */ +#define QCA8075_CTRL_SPEED_MSB 0x0040 + + /* Collision test enable */ +#define QCA8075_CTRL_COLL_TEST_ENABLE 0x0080 + + /* FDX =1, half duplex =0 */ +#define QCA8075_CTRL_FULL_DUPLEX 0x0100 + + /* Restart auto negotiation */ +#define QCA8075_CTRL_RESTART_AUTONEGOTIATION 0x0200 + + /* Isolate PHY from MII */ +#define QCA8075_CTRL_ISOLATE 0x0400 + + /* Power down */ +#define QCA8075_CTRL_POWER_DOWN 0x0800 + + /* Auto Neg Enable */ +#define QCA8075_CTRL_AUTONEGOTIATION_ENABLE 0x1000 + + /* Local Loopback Enable */ +#define QCA8075_LOCAL_LOOPBACK_ENABLE 0x4000 + + /* bits 6,13: 10=1000, 01=100, 00=10 */ +#define QCA8075_CTRL_SPEED_LSB 0x2000 + + /* 0 = normal, 1 = loopback */ +#define QCA8075_CTRL_LOOPBACK 0x4000 +#define QCA8075_CTRL_SOFTWARE_RESET 0x8000 + +#define QCA8075_CTRL_SPEED_MASK 0x2040 +#define QCA8075_CTRL_SPEED_1000 0x0040 +#define QCA8075_CTRL_SPEED_100 0x2000 +#define QCA8075_CTRL_SPEED_10 0x0000 + +#define QCA8075_RESET_DONE(phy_control) \ + (((phy_control) & (QCA8075_CTRL_SOFTWARE_RESET)) == 0) + + /* Status Register fields offset:1 */ + /* Extended register capabilities */ +#define QCA8075_STATUS_EXTENDED_CAPS 0x0001 + + /* Jabber Detected */ +#define QCA8075_STATUS_JABBER_DETECT 0x0002 + + /* Link Status 1 = link */ +#define QCA8075_STATUS_LINK_STATUS_UP 0x0004 + + /* Auto Neg Capable */ +#define QCA8075_STATUS_AUTONEG_CAPS 0x0008 + + /* Remote Fault Detect */ +#define QCA8075_STATUS_REMOTE_FAULT 0x0010 + + /* Auto Neg Complete */ +#define QCA8075_STATUS_AUTO_NEG_DONE 0x0020 + + /* Preamble may be suppressed */ +#define QCA8075_STATUS_PREAMBLE_SUPPRESS 0x0040 + + /* Ext. status info in Reg 0x0F */ +#define QCA8075_STATUS_EXTENDED_STATUS 0x0100 + + /* 100T2 Half Duplex Capable */ +#define QCA8075_STATUS_100T2_HD_CAPS 0x0200 + + /* 100T2 Full Duplex Capable */ +#define QCA8075_STATUS_100T2_FD_CAPS 0x0400 + + /* 10T Half Duplex Capable */ +#define QCA8075_STATUS_10T_HD_CAPS 0x0800 + + /* 10T Full Duplex Capable */ +#define QCA8075_STATUS_10T_FD_CAPS 0x1000 + + /* 100X Half Duplex Capable */ +#define QCA8075_STATUS_100X_HD_CAPS 0x2000 + + /* 100X Full Duplex Capable */ +#define QCA8075_STATUS_100X_FD_CAPS 0x4000 + + /* 100T4 Capable */ +#define QCA8075_STATUS_100T4_CAPS 0x8000 + + /* extended status register capabilities */ + +#define QCA8075_STATUS_1000T_HD_CAPS 0x1000 + +#define QCA8075_STATUS_1000T_FD_CAPS 0x2000 + +#define QCA8075_STATUS_1000X_HD_CAPS 0x4000 + +#define QCA8075_STATUS_1000X_FD_CAPS 0x8000 + +#define QCA8075_AUTONEG_DONE(ip_phy_status) \ + (((ip_phy_status) & (QCA8075_STATUS_AUTO_NEG_DONE)) == \ + (QCA8075_STATUS_AUTO_NEG_DONE)) + + /* PHY identifier1 offset:2 */ +//Organizationally Unique Identifier bits 3:18 + + /* PHY identifier2 offset:3 */ +//Organizationally Unique Identifier bits 19:24 + + /* Auto-Negotiation Advertisement register. offset:4 */ + /* indicates IEEE 802.3 CSMA/CD */ +#define QCA8075_ADVERTISE_SELECTOR_FIELD 0x0001 + + /* 10T Half Duplex Capable */ +#define QCA8075_ADVERTISE_10HALF 0x0020 + + /* 10T Full Duplex Capable */ +#define QCA8075_ADVERTISE_10FULL 0x0040 + + /* 100TX Half Duplex Capable */ +#define QCA8075_ADVERTISE_100HALF 0x0080 + + /* 100TX Full Duplex Capable */ +#define QCA8075_ADVERTISE_100FULL 0x0100 + + /* 100T4 Capable */ +#define QCA8075_ADVERTISE_100T4 0x0200 + + /* Pause operation desired */ +#define QCA8075_ADVERTISE_PAUSE 0x0400 + + /* Asymmetric Pause Direction bit */ +#define QCA8075_ADVERTISE_ASYM_PAUSE 0x0800 + + /* Remote Fault detected */ +#define QCA8075_ADVERTISE_REMOTE_FAULT 0x2000 + + /* Next Page ability supported */ +#define QCA8075_ADVERTISE_NEXT_PAGE 0x8000 + + /* 100TX Half Duplex Capable */ +#define QCA8075_ADVERTISE_1000HALF 0x0100 + + /* 100TX Full Duplex Capable */ +#define QCA8075_ADVERTISE_1000FULL 0x0200 + +#define QCA8075_ADVERTISE_ALL \ + (QCA8075_ADVERTISE_10HALF | QCA8075_ADVERTISE_10FULL | \ + QCA8075_ADVERTISE_100HALF | QCA8075_ADVERTISE_100FULL | \ + QCA8075_ADVERTISE_1000FULL) + +#define QCA8075_ADVERTISE_MEGA_ALL \ + (QCA8075_ADVERTISE_10HALF | QCA8075_ADVERTISE_10FULL | \ + QCA8075_ADVERTISE_100HALF | QCA8075_ADVERTISE_100FULL) + +#define QCA8075_BX_ADVERTISE_1000FULL 0x0020 +#define QCA8075_BX_ADVERTISE_1000HALF 0x0040 +#define QCA8075_BX_ADVERTISE_PAUSE 0x0080 +#define QCA8075_BX_ADVERTISE_ASYM_PAUSE 0x0100 + +#define QCA8075_BX_ADVERTISE_ALL \ + (QCA8075_BX_ADVERTISE_ASYM_PAUSE | QCA8075_BX_ADVERTISE_PAUSE | \ + QCA8075_BX_ADVERTISE_1000HALF | QCA8075_BX_ADVERTISE_1000FULL) + + /* Link Partner ability offset:5 */ + /* Same as advertise selector */ +#define QCA8075_LINK_SLCT 0x001f + + /* Can do 10mbps half-duplex */ +#define QCA8075_LINK_10BASETX_HALF_DUPLEX 0x0020 + + /* Can do 10mbps full-duplex */ +#define QCA8075_LINK_10BASETX_FULL_DUPLEX 0x0040 + + /* Can do 100mbps half-duplex */ +#define QCA8075_LINK_100BASETX_HALF_DUPLEX 0x0080 + + /* Can do 100mbps full-duplex */ +#define QCA8075_LINK_100BASETX_FULL_DUPLEX 0x0100 + + /* Can do 1000mbps full-duplex */ +#define QCA8075_LINK_1000BASETX_FULL_DUPLEX 0x0800 + + /* Can do 1000mbps half-duplex */ +#define QCA8075_LINK_1000BASETX_HALF_DUPLEX 0x0400 + + /* 100BASE-T4 */ +#define QCA8075_LINK_100BASE4 0x0200 + + /* PAUSE */ +#define QCA8075_LINK_PAUSE 0x0400 + + /* Asymmetrical PAUSE */ +#define QCA8075_LINK_ASYPAUSE 0x0800 + + /* Link partner faulted */ +#define QCA8075_LINK_RFAULT 0x2000 + + /* Link partner acked us */ +#define QCA8075_LINK_LPACK 0x4000 + + /* Next page bit */ +#define QCA8075_LINK_NPAGE 0x8000 + + /* Auto-Negotiation Expansion Register offset:6 */ + + /* Next Page Transmit Register offset:7 */ + + /* Link partner Next Page Register offset:8 */ + + /* 1000BASE-T Control Register offset:9 */ + /* Advertise 1000T HD capability */ +#define QCA8075_CTL_1000T_HD_CAPS 0x0100 + + /* Advertise 1000T FD capability */ +#define QCA8075_CTL_1000T_FD_CAPS 0x0200 + + /* 1=Repeater/switch device port 0=DTE device */ +#define QCA8075_CTL_1000T_REPEATER_DTE 0x0400 + + /* 1=Configure PHY as Master 0=Configure PHY as Slave */ +#define QCA8075_CTL_1000T_MS_VALUE 0x0800 + + /* 1=Master/Slave manual config value 0=Automatic Master/Slave config */ +#define QCA8075_CTL_1000T_MS_ENABLE 0x1000 + + /* Normal Operation */ +#define QCA8075_CTL_1000T_TEST_MODE_NORMAL 0x0000 + + /* Transmit Waveform test */ +#define QCA8075_CTL_1000T_TEST_MODE_1 0x2000 + + /* Master Transmit Jitter test */ +#define QCA8075_CTL_1000T_TEST_MODE_2 0x4000 + + /* Slave Transmit Jitter test */ +#define QCA8075_CTL_1000T_TEST_MODE_3 0x6000 + + /* Transmitter Distortion test */ +#define QCA8075_CTL_1000T_TEST_MODE_4 0x8000 +#define QCA8075_CTL_1000T_SPEED_MASK 0x0300 +#define QCA8075_CTL_1000T_DEFAULT_CAP_MASK 0x0300 + + /* 1000BASE-T Status Register offset:10 */ + /* LP is 1000T HD capable */ +#define QCA8075_STATUS_1000T_LP_HD_CAPS 0x0400 + + /* LP is 1000T FD capable */ +#define QCA8075_STATUS_1000T_LP_FD_CAPS 0x0800 + + /* Remote receiver OK */ +#define QCA8075_STATUS_1000T_REMOTE_RX_STATUS 0x1000 + + /* Local receiver OK */ +#define QCA8075_STATUS_1000T_LOCAL_RX_STATUS 0x2000 + + /* 1=Local TX is Master, 0=Slave */ +#define QCA8075_STATUS_1000T_MS_CONFIG_RES 0x4000 + +#define QCA8075_STATUS_1000T_MS_CONFIG_FAULT 0x8000 + + /* Master/Slave config fault */ +#define QCA8075_STATUS_1000T_REMOTE_RX_STATUS_SHIFT 12 +#define QCA8075_STATUS_1000T_LOCAL_RX_STATUS_SHIFT 13 + + /* Phy Specific Control Register offset:16 */ + /* 1=Jabber Function disabled */ +#define QCA8075_CTL_JABBER_DISABLE 0x0001 + + /* 1=Polarity Reversal enabled */ +#define QCA8075_CTL_POLARITY_REVERSAL 0x0002 + + /* 1=SQE Test enabled */ +#define QCA8075_CTL_SQE_TEST 0x0004 +#define QCA8075_CTL_MAC_POWERDOWN 0x0008 + + /* 1=CLK125 low, 0=CLK125 toggling + #define QCA8075_CTL_CLK125_DISABLE 0x0010 + */ + /* MDI Crossover Mode bits 6:5 */ + /* Manual MDI configuration */ +#define QCA8075_CTL_MDI_MANUAL_MODE 0x0000 + + /* Manual MDIX configuration */ +#define QCA8075_CTL_MDIX_MANUAL_MODE 0x0020 + + /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */ +#define QCA8075_CTL_AUTO_X_1000T 0x0040 + + /* Auto crossover enabled all speeds */ +#define QCA8075_CTL_AUTO_X_MODE 0x0060 + + /* 1=Enable Extended 10BASE-T distance + * (Lower 10BASE-T RX Threshold) + * 0=Normal 10BASE-T RX Threshold */ +#define QCA8075_CTL_10BT_EXT_DIST_ENABLE 0x0080 + + /* 1=5-Bit interface in 100BASE-TX + * 0=MII interface in 100BASE-TX */ +#define QCA8075_CTL_MII_5BIT_ENABLE 0x0100 + + /* 1=Scrambler disable */ +#define QCA8075_CTL_SCRAMBLER_DISABLE 0x0200 + + /* 1=Force link good */ +#define QCA8075_CTL_FORCE_LINK_GOOD 0x0400 + + /* 1=Assert CRS on Transmit */ +#define QCA8075_CTL_ASSERT_CRS_ON_TX 0x0800 + +#define QCA8075_CTL_POLARITY_REVERSAL_SHIFT 1 +#define QCA8075_CTL_AUTO_X_MODE_SHIFT 5 +#define QCA8075_CTL_10BT_EXT_DIST_ENABLE_SHIFT 7 + + + /* Phy Specific status fields offset:17 */ + /* 1=Speed & Duplex resolved */ +#define QCA8075_STATUS_LINK_PASS 0x0400 +#define QCA8075_STATUS_RESOVLED 0x0800 + + /* 1=Duplex 0=Half Duplex */ +#define QCA8075_STATUS_FULL_DUPLEX 0x2000 + + /* Speed, bits 14:15 */ +#define QCA8075_STATUS_SPEED 0xC000 +#define QCA8075_STATUS_SPEED_MASK 0xC000 + + /* 00=10Mbs */ +#define QCA8075_STATUS_SPEED_10MBS 0x0000 + + /* 01=100Mbs */ +#define QCA8075_STATUS_SPEED_100MBS 0x4000 + + /* 10=1000Mbs */ +#define QCA8075_STATUS_SPEED_1000MBS 0x8000 +#define QCA8075_SPEED_DUPLEX_RESOVLED(phy_status) \ + (((phy_status) & \ + (QCA8075_STATUS_RESOVLED)) == \ + (QCA8075_STATUS_RESOVLED)) + + /*phy debug port1 register offset:29 */ + /*phy debug port2 register offset:30 */ + + /*QCA8075 interrupt flag */ +#define QCA8075_INTR_SPEED_CHANGE 0x4000 +#define QCA8075_INTR_DUPLEX_CHANGE 0x2000 +#define QCA8075_INTR_STATUS_UP_CHANGE 0x0400 +#define QCA8075_INTR_STATUS_DOWN_CHANGE 0x0800 +#define QCA8075_INTR_BX_FX_STATUS_DOWN_CHANGE 0x0100 +#define QCA8075_INTR_BX_FX_STATUS_UP_CHANGE 0x0080 +#define QCA8075_INTR_MEDIA_STATUS_CHANGE 0x1000 +#define QCA8075_INTR_WOL 0x0001 +#define QCA8075_INTR_POE 0x0002 + +#define QCA8075_PHY_PSGMII_REDUCE_SERDES_TX_AMP 0x8a +#define QCA8075_DAC_CTRL_MASK 0x380 +#define QCA8075_PHY_MMD7_DAC_CTRL 0x801a +#define QCA8075_DAC_CTRL_VALUE 0x280 +#define QCA8075_PHY_MMD7_NUM 7 +#define QCA8075_PSGMII_TX_DRIVER_1_CTRL 0xb +#define QCA8075_PHY_MMD7_LED_1000_CTRL1 0x8076 +#define QCA8075_LED_1000_CTRL1_100_10_MASK 0x30 + +#define RUN_CDT 0x8000 +#define CABLE_LENGTH_UNIT 0x0400 +#define QCA8075_MAX_TRIES 100 + +#endif /* _QCA8075_PHY_H_ */ diff --git a/sources/uboot-be550/drivers/net/ipq9574/ipq9574_uniphy.c b/sources/uboot-be550/drivers/net/ipq9574/ipq9574_uniphy.c new file mode 100644 index 00000000..bd477e93 --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq9574/ipq9574_uniphy.c @@ -0,0 +1,766 @@ +/* + * Copyright (c) 2017-2019, 2021, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "ipq9574_edma.h" +#include "ipq9574_uniphy.h" +#include "ipq9574_ppe.h" +#include +#include "ipq_phy.h" + +extern int uniphy_force_mode; + +extern int is_uniphy_enabled(int uniphy_index); + +DECLARE_GLOBAL_DATA_PTR; +extern int ipq_mdio_write(int mii_id, + int regnum, u16 value); +extern int ipq_mdio_read(int mii_id, + int regnum, ushort *data); +extern void ipq9574_qca8075_phy_serdes_reset(u32 phy_id); +extern void qca8084_phy_interface_mode_set(void); + +void csr1_write(int phy_id, int addr, int value) +{ + int addr_h, addr_l, ahb_h, ahb_l, phy; + phy=phy_id<<(0x10); + addr_h=(addr&0xffffff)>>8; + addr_l=((addr&0xff)<<2)|(0x20<<(0xa)); + ahb_l=(addr_l&0xffff)|(0x7A00000|phy); + ahb_h=(0x7A083FC|phy); + writel(addr_h,ahb_h); + writel(value,ahb_l); +} + +int csr1_read(int phy_id, int addr ) +{ + int addr_h ,addr_l,ahb_h, ahb_l, phy; + phy=phy_id<<(0x10); + addr_h=(addr&0xffffff)>>8; + addr_l=((addr&0xff)<<2)|(0x20<<(0xa)); + ahb_l=(addr_l&0xffff)|(0x7A00000|phy); + ahb_h=(0x7A083FC|phy); + writel(addr_h, ahb_h); + return readl(ahb_l); +} + +static int ppe_uniphy_calibration(uint32_t uniphy_index) +{ + int retries = 100, calibration_done = 0; + uint32_t reg_value = 0; + + while(calibration_done != UNIPHY_CALIBRATION_DONE) { + mdelay(1); + if (retries-- == 0) { + printf("uniphy callibration time out!\n"); + return -1; + } + reg_value = readl(PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC) + + PPE_UNIPHY_OFFSET_CALIB_4); + calibration_done = (reg_value >> 0x7) & 0x1; + } + + return 0; +} + +static void ppe_uniphy_reset(enum uniphy_reset_type rst_type, bool enable) +{ + uint32_t mode, node; + uint32_t reg_val, reg_val1; + + switch(rst_type) { + case UNIPHY0_SOFT_RESET: + node = fdt_path_offset(gd->fdt_blob, "/ess-switch"); + if (node < 0) { + printf("\nError: ess-switch not specified in dts"); + return; + } + mode = fdtdec_get_uint(gd->fdt_blob, node, "switch_mac_mode1", -1); + if (mode < 0) { + printf("\nError: switch_mac_mode1 not specified in dts"); + return; + } + reg_val = readl(GCC_UNIPHY0_MISC); + reg_val1 = readl(NSS_CC_UNIPHY_MISC_RESET); + if (mode == EPORT_WRAPPER_MAX) { + if (enable) { + reg_val |= 0x1; + reg_val1 |= 0xffc000; + } else { + reg_val &= ~0x1; + reg_val1 &= ~0xffc000; + } + } else { + if (enable) { + reg_val |= 0x1; + reg_val1 |= 0xff0000; + } else { + reg_val &= ~0x1; + reg_val1 &= ~0xff0000; + } + } + writel(reg_val, GCC_UNIPHY0_MISC); + writel(reg_val1, NSS_CC_UNIPHY_MISC_RESET); + break; + case UNIPHY0_XPCS_RESET: + reg_val = readl(GCC_UNIPHY0_MISC); + if (enable) + reg_val |= 0x4; + else + reg_val &= ~0x4; + writel(reg_val, GCC_UNIPHY0_MISC); + break; + case UNIPHY1_SOFT_RESET: + reg_val = readl(GCC_UNIPHY0_MISC + GCC_UNIPHY_REG_INC); + reg_val1 = readl(NSS_CC_UNIPHY_MISC_RESET); + if (enable) { + reg_val |= 0x1; + reg_val1 |= 0xC000; + } else { + reg_val &= ~0x1; + reg_val1 &= ~0xC000; + } + writel(reg_val, GCC_UNIPHY0_MISC + GCC_UNIPHY_REG_INC); + writel(reg_val1, NSS_CC_UNIPHY_MISC_RESET); + break; + case UNIPHY1_XPCS_RESET: + reg_val = readl(GCC_UNIPHY0_MISC + GCC_UNIPHY_REG_INC); + if (enable) + reg_val |= 0x4; + else + reg_val &= ~0x4; + writel(reg_val, GCC_UNIPHY0_MISC + GCC_UNIPHY_REG_INC); + break; + case UNIPHY2_SOFT_RESET: + reg_val = readl(GCC_UNIPHY0_MISC + (2 * GCC_UNIPHY_REG_INC)); + reg_val1 = readl(NSS_CC_UNIPHY_MISC_RESET); + if (enable) { + reg_val |= 0x1; + reg_val1 |= 0x3000; + } else { + reg_val &= ~0x1; + reg_val1 &= ~0x3000; + } + writel(reg_val, GCC_UNIPHY0_MISC + (2 * GCC_UNIPHY_REG_INC)); + writel(reg_val1, NSS_CC_UNIPHY_MISC_RESET); + break; + case UNIPHY2_XPCS_RESET: + reg_val = readl(GCC_UNIPHY0_MISC + (2 * GCC_UNIPHY_REG_INC)); + if (enable) + reg_val |= 0x4; + else + reg_val &= ~0x4; + writel(reg_val, GCC_UNIPHY0_MISC + (2 * GCC_UNIPHY_REG_INC)); + break; + default: + break; + } +} + +static void ppe_uniphy_psgmii_mode_set(uint32_t uniphy_index) +{ + if (uniphy_index == 0) + ppe_uniphy_reset(UNIPHY0_XPCS_RESET, true); + else if (uniphy_index == 1) + ppe_uniphy_reset(UNIPHY1_XPCS_RESET, true); + else + ppe_uniphy_reset(UNIPHY2_XPCS_RESET, true); + mdelay(100); + + writel(0x220, PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC) + + PPE_UNIPHY_MODE_CONTROL); + + if (uniphy_index == 0) { + ppe_uniphy_reset(UNIPHY0_SOFT_RESET, true); + mdelay(100); + ppe_uniphy_reset(UNIPHY0_SOFT_RESET, false); + } else if (uniphy_index == 1) { + ppe_uniphy_reset(UNIPHY1_SOFT_RESET, true); + mdelay(100); + ppe_uniphy_reset(UNIPHY1_SOFT_RESET, false); + } else { + ppe_uniphy_reset(UNIPHY2_SOFT_RESET, true); + mdelay(100); + ppe_uniphy_reset(UNIPHY2_SOFT_RESET, false); + } + mdelay(100); + ppe_uniphy_calibration(uniphy_index); +#ifdef CONFIG_IPQ9574_QCA8075_PHY + ipq9574_qca8075_phy_serdes_reset(0x10); +#endif +} + +static void ppe_uniphy_qsgmii_mode_set(uint32_t uniphy_index) +{ + if (uniphy_index == 0) + ppe_uniphy_reset(UNIPHY0_XPCS_RESET, true); + else if (uniphy_index == 1) + ppe_uniphy_reset(UNIPHY1_XPCS_RESET, true); + else + ppe_uniphy_reset(UNIPHY2_XPCS_RESET, true); + mdelay(100); + + writel(0x120, PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC) + + PPE_UNIPHY_MODE_CONTROL); + if (uniphy_index == 0) { + ppe_uniphy_reset(UNIPHY0_SOFT_RESET, true); + mdelay(100); + ppe_uniphy_reset(UNIPHY0_SOFT_RESET, false); + } else if (uniphy_index == 1) { + ppe_uniphy_reset(UNIPHY1_SOFT_RESET, true); + mdelay(100); + ppe_uniphy_reset(UNIPHY1_SOFT_RESET, false); + } else { + ppe_uniphy_reset(UNIPHY2_SOFT_RESET, true); + mdelay(100); + ppe_uniphy_reset(UNIPHY2_SOFT_RESET, false); + } + mdelay(100); +} + +void ppe_uniphy_set_forceMode(uint32_t uniphy_index) +{ + uint32_t reg_value; + + reg_value = readl(PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC) + + UNIPHY_DEC_CHANNEL_0_INPUT_OUTPUT_4); + reg_value |= UNIPHY_FORCE_SPEED_25M; + + writel(reg_value, PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC) + + UNIPHY_DEC_CHANNEL_0_INPUT_OUTPUT_4); +} + +static void ppe_uniphy_sgmii_mode_set(uint32_t uniphy_index, uint32_t mode) +{ + writel(UNIPHY_MISC_SRC_PHY_MODE, PPE_UNIPHY_BASE + + (uniphy_index * PPE_UNIPHY_REG_INC) + + UNIPHY_MISC_SOURCE_SELECTION_REG_OFFSET); + + if (uniphy_force_mode == uniphy_index) + ppe_uniphy_set_forceMode(uniphy_index); + + if (mode == EPORT_WRAPPER_SGMII_PLUS) { + writel(UNIPHY_MISC2_REG_SGMII_PLUS_MODE, PPE_UNIPHY_BASE + + (uniphy_index * PPE_UNIPHY_REG_INC) + + UNIPHY_MISC2_REG_OFFSET); + } else { + writel(UNIPHY_MISC2_REG_SGMII_MODE, PPE_UNIPHY_BASE + + (uniphy_index * PPE_UNIPHY_REG_INC) + + UNIPHY_MISC2_REG_OFFSET); + } + + writel(UNIPHY_PLL_RESET_REG_VALUE, PPE_UNIPHY_BASE + + (uniphy_index * PPE_UNIPHY_REG_INC) + UNIPHY_PLL_RESET_REG_OFFSET); + mdelay(500); + writel(UNIPHY_PLL_RESET_REG_DEFAULT_VALUE, PPE_UNIPHY_BASE + + (uniphy_index * PPE_UNIPHY_REG_INC) + UNIPHY_PLL_RESET_REG_OFFSET); + mdelay(500); + if (uniphy_index == 0) + ppe_uniphy_reset(UNIPHY0_XPCS_RESET, true); + else if (uniphy_index == 1) + ppe_uniphy_reset(UNIPHY1_XPCS_RESET, true); + else + ppe_uniphy_reset(UNIPHY2_XPCS_RESET, true); + mdelay(100); + + if (uniphy_index == 0) { + writel(0x0, NSS_CC_UNIPHY_PORT1_RX_CBCR); + writel(0x0, NSS_CC_UNIPHY_PORT1_RX_CBCR + 0x4); + writel(0x0, NSS_CC_PORT1_RX_CBCR); + writel(0x0, NSS_CC_PORT1_RX_CBCR + 0x4); + } else if (uniphy_index == 1) { + writel(0x0, NSS_CC_UNIPHY_PORT1_RX_CBCR + (PORT5 - 1) * 0x8); + writel(0x0, NSS_CC_UNIPHY_PORT1_RX_CBCR + 0x4 + (PORT5 - 1) * 0x8); + writel(0x0, NSS_CC_PORT1_RX_CBCR + (PORT5 - 1) * 0x8); + writel(0x0, NSS_CC_PORT1_RX_CBCR + 0x4 + (PORT5 - 1) * 0x8); + } else if (uniphy_index == 2) { + writel(0x0, NSS_CC_UNIPHY_PORT1_RX_CBCR + (PORT6 - 1) * 0x8); + writel(0x0, NSS_CC_UNIPHY_PORT1_RX_CBCR + 0x4 + (PORT6 - 1) * 8); + writel(0x0, NSS_CC_PORT1_RX_CBCR + (PORT6 - 1) * 0x8); + writel(0x0, NSS_CC_PORT1_RX_CBCR + 0x4 + (PORT6 - 1) * 0x8); + } + + switch (mode) { + case EPORT_WRAPPER_SGMII_FIBER: + writel(0x400, PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC) + + PPE_UNIPHY_MODE_CONTROL); + break; + + case EPORT_WRAPPER_SGMII0_RGMII4: + case EPORT_WRAPPER_SGMII1_RGMII4: + case EPORT_WRAPPER_SGMII4_RGMII4: + writel(0x420, PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC) + + PPE_UNIPHY_MODE_CONTROL); + break; + + case EPORT_WRAPPER_SGMII_PLUS: + if (uniphy_index == 0) + writel(0x20, PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC) + + PPE_UNIPHY_MODE_CONTROL); + else + writel(0x820, PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC) + + PPE_UNIPHY_MODE_CONTROL); + break; + + default: + printf("SGMII Config. wrongly"); + break; + } + + if (uniphy_index == 0) { + ppe_uniphy_reset(UNIPHY0_SOFT_RESET, true); + mdelay(100); + ppe_uniphy_reset(UNIPHY0_SOFT_RESET, false); + } else if (uniphy_index == 1) { + ppe_uniphy_reset(UNIPHY1_SOFT_RESET, true); + mdelay(100); + ppe_uniphy_reset(UNIPHY1_SOFT_RESET, false); + } else { + ppe_uniphy_reset(UNIPHY2_SOFT_RESET, true); + mdelay(100); + ppe_uniphy_reset(UNIPHY2_SOFT_RESET, false); + } + mdelay(100); + + if (uniphy_index == 0) { + writel(0x1, NSS_CC_UNIPHY_PORT1_RX_CBCR); + writel(0x1, NSS_CC_UNIPHY_PORT1_RX_CBCR + 0x4); + writel(0x1, NSS_CC_PORT1_RX_CBCR); + writel(0x1, NSS_CC_PORT1_RX_CBCR + 0x4); + } else if (uniphy_index == 1) { + writel(0x1, NSS_CC_UNIPHY_PORT1_RX_CBCR + (PORT5 - 1) * 0x8); + writel(0x1, NSS_CC_UNIPHY_PORT1_RX_CBCR + 0x4 + (PORT5 - 1) * 0x8); + writel(0x1, NSS_CC_PORT1_RX_CBCR + (PORT5 - 1) * 0x8); + writel(0x1, NSS_CC_PORT1_RX_CBCR + 0x4 + (PORT5 - 1) * 0x8); + } else if (uniphy_index == 2) { + writel(0x1, NSS_CC_UNIPHY_PORT1_RX_CBCR + (PORT6 - 1) * 0x8); + writel(0x1, NSS_CC_UNIPHY_PORT1_RX_CBCR + 0x4 + (PORT6 - 1) * 8); + writel(0x1, NSS_CC_PORT1_RX_CBCR + (PORT6 - 1) * 0x8); + writel(0x1, NSS_CC_PORT1_RX_CBCR + 0x4 + (PORT6 - 1) * 0x8); + } + + ppe_uniphy_calibration(uniphy_index); +} + +static int ppe_uniphy_10g_r_linkup(uint32_t uniphy_index) +{ + uint32_t reg_value = 0; + uint32_t retries = 100, linkup = 0; + + while (linkup != UNIPHY_10GR_LINKUP) { + mdelay(1); + if (retries-- == 0) + return -1; + reg_value = csr1_read(uniphy_index, SR_XS_PCS_KR_STS1_ADDRESS); + linkup = (reg_value >> 12) & UNIPHY_10GR_LINKUP; + } + mdelay(10); + return 0; +} + +static void ppe_uniphy_10g_r_mode_set(uint32_t uniphy_index) +{ + if (uniphy_index == 0) + ppe_uniphy_reset(UNIPHY0_XPCS_RESET, true); + else if (uniphy_index == 1) + ppe_uniphy_reset(UNIPHY1_XPCS_RESET, true); + else + ppe_uniphy_reset(UNIPHY2_XPCS_RESET, true); + + writel(0x1021, PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC) + + PPE_UNIPHY_MODE_CONTROL); + writel(0x1C0, PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC) + + UNIPHY_INSTANCE_LINK_DETECT); + + if (uniphy_index == 0) { + ppe_uniphy_reset(UNIPHY0_SOFT_RESET, true); + mdelay(100); + ppe_uniphy_reset(UNIPHY0_SOFT_RESET, false); + } else if (uniphy_index == 1) { + ppe_uniphy_reset(UNIPHY1_SOFT_RESET, true); + mdelay(100); + ppe_uniphy_reset(UNIPHY1_SOFT_RESET, false); + } else { + ppe_uniphy_reset(UNIPHY2_SOFT_RESET, true); + mdelay(100); + ppe_uniphy_reset(UNIPHY2_SOFT_RESET, false); + } + mdelay(100); + + ppe_uniphy_calibration(uniphy_index); + + if (uniphy_index == 0) + ppe_uniphy_reset(UNIPHY0_XPCS_RESET, false); + else if (uniphy_index == 1) + ppe_uniphy_reset(UNIPHY1_XPCS_RESET, false); + else + ppe_uniphy_reset(UNIPHY2_XPCS_RESET, false); +} + +static void ppe_uniphy_uqxgmii_eee_set(uint32_t uniphy_index) +{ + uint32_t reg_value = 0; + + /* configure eee related timer value */ + reg_value = csr1_read(uniphy_index, VR_XS_PCS_EEE_MCTRL0_ADDRESS); + reg_value |= SIGN_BIT | MULT_FACT_100NS; + csr1_write(uniphy_index, VR_XS_PCS_EEE_MCTRL0_ADDRESS, reg_value); + + reg_value = csr1_read(uniphy_index, VR_XS_PCS_EEE_TXTIMER_ADDRESS); + reg_value |= UNIPHY_XPCS_TSL_TIMER | UNIPHY_XPCS_TLU_TIMER + | UNIPHY_XPCS_TWL_TIMER; + csr1_write(uniphy_index, VR_XS_PCS_EEE_TXTIMER_ADDRESS, reg_value); + + reg_value = csr1_read(uniphy_index, VR_XS_PCS_EEE_RXTIMER_ADDRESS); + reg_value |= UNIPHY_XPCS_100US_TIMER | UNIPHY_XPCS_TWR_TIMER; + csr1_write(uniphy_index, VR_XS_PCS_EEE_RXTIMER_ADDRESS, reg_value); + + /* Transparent LPI mode and LPI pattern enable */ + reg_value = csr1_read(uniphy_index, VR_XS_PCS_EEE_MCTRL1_ADDRESS); + reg_value |= TRN_LPI | TRN_RXLPI; + csr1_write(uniphy_index, VR_XS_PCS_EEE_MCTRL1_ADDRESS, reg_value); + + reg_value = csr1_read(uniphy_index, VR_XS_PCS_EEE_MCTRL0_ADDRESS); + reg_value |= LRX_EN | LTX_EN; + csr1_write(uniphy_index, VR_XS_PCS_EEE_MCTRL0_ADDRESS, reg_value); +} + +static void ppe_uniphy_uqxgmii_mode_set(uint32_t uniphy_index) +{ + uint32_t reg_value = 0; + + writel(UNIPHY_MISC2_REG_VALUE, PPE_UNIPHY_BASE + + (uniphy_index * PPE_UNIPHY_REG_INC) + UNIPHY_MISC2_REG_OFFSET); + + /* reset uniphy */ + writel(UNIPHY_PLL_RESET_REG_VALUE, PPE_UNIPHY_BASE + + (uniphy_index * PPE_UNIPHY_REG_INC) + UNIPHY_PLL_RESET_REG_OFFSET); + mdelay(500); + writel(UNIPHY_PLL_RESET_REG_DEFAULT_VALUE, PPE_UNIPHY_BASE + + (uniphy_index * PPE_UNIPHY_REG_INC) + UNIPHY_PLL_RESET_REG_OFFSET); + mdelay(500); + + /* keep xpcs to reset status */ + if (uniphy_index == 0) + ppe_uniphy_reset(UNIPHY0_XPCS_RESET, true); + else if (uniphy_index == 1) + ppe_uniphy_reset(UNIPHY1_XPCS_RESET, true); + else + ppe_uniphy_reset(UNIPHY2_XPCS_RESET, true); + mdelay(100); + + /* configure uniphy to usxgmii mode */ + writel(0x1021, PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC) + + PPE_UNIPHY_MODE_CONTROL); + + reg_value = readl(PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC) + + UNIPHYQP_USXG_OPITON1); + reg_value |= GMII_SRC_SEL; + writel(reg_value, PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC) + + UNIPHYQP_USXG_OPITON1); + + /* configure uniphy usxgmii gcc software reset */ + if (uniphy_index == 0) { + ppe_uniphy_reset(UNIPHY0_SOFT_RESET, true); + mdelay(100); + ppe_uniphy_reset(UNIPHY0_SOFT_RESET, false); + } else if (uniphy_index == 1) { + ppe_uniphy_reset(UNIPHY1_SOFT_RESET, true); + mdelay(100); + ppe_uniphy_reset(UNIPHY1_SOFT_RESET, false); + } else { + ppe_uniphy_reset(UNIPHY2_SOFT_RESET, true); + mdelay(100); + ppe_uniphy_reset(UNIPHY2_SOFT_RESET, false); + } + mdelay(100); + + /* wait calibration done to uniphy */ + ppe_uniphy_calibration(uniphy_index); + + /* release xpcs reset status */ + if (uniphy_index == 0) + ppe_uniphy_reset(UNIPHY0_XPCS_RESET, false); + else if (uniphy_index == 1) + ppe_uniphy_reset(UNIPHY1_XPCS_RESET, false); + else + ppe_uniphy_reset(UNIPHY2_XPCS_RESET, false); + mdelay(100); + + /* wait 10g base_r link up */ + ppe_uniphy_10g_r_linkup(uniphy_index); + + /* enable uniphy usxgmii */ + reg_value = csr1_read(uniphy_index, VR_XS_PCS_DIG_CTRL1_ADDRESS); + reg_value |= USXG_EN; + csr1_write(uniphy_index, VR_XS_PCS_DIG_CTRL1_ADDRESS, reg_value); + + /* set qxgmii mode */ + reg_value = csr1_read(uniphy_index, VR_XS_PCS_KR_CTRL_ADDRESS); + reg_value |= USXG_MODE; + csr1_write(uniphy_index, VR_XS_PCS_KR_CTRL_ADDRESS, reg_value); + + /* set AM interval mode */ + reg_value = csr1_read(uniphy_index, VR_XS_PCS_DIG_STS_ADDRESS); + reg_value |= AM_COUNT; + csr1_write(uniphy_index, VR_XS_PCS_DIG_STS_ADDRESS, reg_value); + + /* xpcs software reset */ + reg_value = csr1_read(uniphy_index, VR_XS_PCS_DIG_CTRL1_ADDRESS); + reg_value |= VR_RST; + csr1_write(uniphy_index, VR_XS_PCS_DIG_CTRL1_ADDRESS, reg_value); + + /* enable uniphy autoneg complete interrupt and 10M/100M 8-bits MII width */ + reg_value = csr1_read(uniphy_index, VR_MII_AN_CTRL_ADDRESS); + reg_value |= MII_AN_INTR_EN; + reg_value |= MII_CTRL; + csr1_write(uniphy_index, VR_MII_AN_CTRL_ADDRESS, reg_value); + csr1_write(uniphy_index, VR_MII_AN_CTRL_CHANNEL1_ADDRESS, reg_value); + csr1_write(uniphy_index, VR_MII_AN_CTRL_CHANNEL2_ADDRESS, reg_value); + csr1_write(uniphy_index, VR_MII_AN_CTRL_CHANNEL3_ADDRESS, reg_value); + + /* disable TICD */ + reg_value = csr1_read(uniphy_index, VR_XAUI_MODE_CTRL_ADDRESS); + reg_value |= IPG_CHECK; + csr1_write(uniphy_index, VR_XAUI_MODE_CTRL_ADDRESS, reg_value); + csr1_write(uniphy_index, VR_XAUI_MODE_CTRL_CHANNEL1_ADDRESS, reg_value); + csr1_write(uniphy_index, VR_XAUI_MODE_CTRL_CHANNEL2_ADDRESS, reg_value); + csr1_write(uniphy_index, VR_XAUI_MODE_CTRL_CHANNEL3_ADDRESS, reg_value); + + /* enable uniphy autoneg ability and usxgmii 10g speed and full duplex */ + reg_value = csr1_read(uniphy_index, SR_MII_CTRL_ADDRESS); + reg_value |= AN_ENABLE; + reg_value &= ~SS5; + reg_value |= SS6 | SS13 | DUPLEX_MODE; + csr1_write(uniphy_index, SR_MII_CTRL_ADDRESS, reg_value); + csr1_write(uniphy_index, SR_MII_CTRL_CHANNEL1_ADDRESS, reg_value); + csr1_write(uniphy_index, SR_MII_CTRL_CHANNEL2_ADDRESS, reg_value); + csr1_write(uniphy_index, SR_MII_CTRL_CHANNEL3_ADDRESS, reg_value); + + /* enable uniphy eee transparent mode*/ + ppe_uniphy_uqxgmii_eee_set(uniphy_index); + +#ifdef CONFIG_QCA8084_PHY_MODE + /* phy interface mode configuration for qca8084 */ + qca8084_phy_interface_mode_set(); +#endif +} + +static void ppe_uniphy_usxgmii_mode_set(uint32_t uniphy_index) +{ + uint32_t reg_value = 0; + + writel(UNIPHY_MISC2_REG_VALUE, PPE_UNIPHY_BASE + + (uniphy_index * PPE_UNIPHY_REG_INC) + UNIPHY_MISC2_REG_OFFSET); + writel(UNIPHY_PLL_RESET_REG_VALUE, PPE_UNIPHY_BASE + + (uniphy_index * PPE_UNIPHY_REG_INC) + UNIPHY_PLL_RESET_REG_OFFSET); + mdelay(500); + writel(UNIPHY_PLL_RESET_REG_DEFAULT_VALUE, PPE_UNIPHY_BASE + + (uniphy_index * PPE_UNIPHY_REG_INC) + UNIPHY_PLL_RESET_REG_OFFSET); + mdelay(500); + + if (uniphy_index == 0) + ppe_uniphy_reset(UNIPHY0_XPCS_RESET, true); + else if (uniphy_index == 1) + ppe_uniphy_reset(UNIPHY1_XPCS_RESET, true); + else + ppe_uniphy_reset(UNIPHY2_XPCS_RESET, true); + mdelay(100); + + writel(0x1021, PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC) + + PPE_UNIPHY_MODE_CONTROL); + + if (uniphy_index == 0) { + ppe_uniphy_reset(UNIPHY0_SOFT_RESET, true); + mdelay(100); + ppe_uniphy_reset(UNIPHY0_SOFT_RESET, false); + } else if (uniphy_index == 1) { + ppe_uniphy_reset(UNIPHY1_SOFT_RESET, true); + mdelay(100); + ppe_uniphy_reset(UNIPHY1_SOFT_RESET, false); + } else { + ppe_uniphy_reset(UNIPHY2_SOFT_RESET, true); + mdelay(100); + ppe_uniphy_reset(UNIPHY2_SOFT_RESET, false); + } + mdelay(100); + + ppe_uniphy_calibration(uniphy_index); + + if (uniphy_index == 0) + ppe_uniphy_reset(UNIPHY0_XPCS_RESET, false); + else if (uniphy_index == 1) + ppe_uniphy_reset(UNIPHY1_XPCS_RESET, false); + else + ppe_uniphy_reset(UNIPHY2_XPCS_RESET, false); + mdelay(100); + + ppe_uniphy_10g_r_linkup(uniphy_index); + reg_value = csr1_read(uniphy_index, VR_XS_PCS_DIG_CTRL1_ADDRESS); + reg_value |= USXG_EN; + csr1_write(uniphy_index, VR_XS_PCS_DIG_CTRL1_ADDRESS, reg_value); + reg_value = csr1_read(uniphy_index, VR_MII_AN_CTRL_ADDRESS); + reg_value |= MII_AN_INTR_EN; + reg_value |= MII_CTRL; + csr1_write(uniphy_index, VR_MII_AN_CTRL_ADDRESS, reg_value); + reg_value = csr1_read(uniphy_index, SR_MII_CTRL_ADDRESS); + reg_value |= AN_ENABLE; + reg_value &= ~SS5; + reg_value |= SS6 | SS13 | DUPLEX_MODE; + csr1_write(uniphy_index, SR_MII_CTRL_ADDRESS, reg_value); +} + +void ppe_uniphy_mode_set(uint32_t uniphy_index, uint32_t mode) +{ + if (!is_uniphy_enabled(uniphy_index)) { + printf("Uniphy %u is disabled\n", uniphy_index); + return; + } + + switch(mode) { + case EPORT_WRAPPER_PSGMII: + ppe_uniphy_psgmii_mode_set(uniphy_index); + break; + case EPORT_WRAPPER_QSGMII: + ppe_uniphy_qsgmii_mode_set(uniphy_index); + break; + case EPORT_WRAPPER_SGMII0_RGMII4: + case EPORT_WRAPPER_SGMII1_RGMII4: + case EPORT_WRAPPER_SGMII4_RGMII4: + case EPORT_WRAPPER_SGMII_PLUS: + case EPORT_WRAPPER_SGMII_FIBER: + ppe_uniphy_sgmii_mode_set(uniphy_index, mode); + break; + case EPORT_WRAPPER_USXGMII: + ppe_uniphy_usxgmii_mode_set(uniphy_index); + break; + case EPORT_WRAPPER_10GBASE_R: + ppe_uniphy_10g_r_mode_set(uniphy_index); + break; + case EPORT_WRAPPER_UQXGMII: + case EPORT_WRAPPER_UQXGMII_3CHANNELS: + ppe_uniphy_uqxgmii_mode_set(uniphy_index); + break; + default: + break; + } +} + +void ppe_uniphy_usxgmii_autoneg_completed(uint32_t uniphy_index) +{ + uint32_t autoneg_complete = 0, retries = 100; + uint32_t reg_value = 0; + + while (autoneg_complete != 0x1) { + mdelay(1); + if (retries-- == 0) + { + return; + } + reg_value = csr1_read(uniphy_index, VR_MII_AN_INTR_STS); + autoneg_complete = reg_value & 0x1; + } + reg_value &= ~CL37_ANCMPLT_INTR; + csr1_write(uniphy_index, VR_MII_AN_INTR_STS, reg_value); +} + +void ppe_uniphy_usxgmii_speed_set(uint32_t uniphy_index, uint32_t port_id, + int speed) +{ + uint32_t reg_value = 0; + + if (port_id == PORT2) + reg_value = csr1_read(uniphy_index, SR_MII_CTRL_CHANNEL1_ADDRESS); + else if (port_id == PORT3) + reg_value = csr1_read(uniphy_index, SR_MII_CTRL_CHANNEL2_ADDRESS); + else if (port_id == PORT4) + reg_value = csr1_read(uniphy_index, SR_MII_CTRL_CHANNEL3_ADDRESS); + else + reg_value = csr1_read(uniphy_index, SR_MII_CTRL_ADDRESS); + + reg_value |= DUPLEX_MODE; + + switch(speed) { + case 0: + reg_value &=~SS5; + reg_value &=~SS6; + reg_value &=~SS13; + break; + case 1: + reg_value &=~SS5; + reg_value &=~SS6; + reg_value |=SS13; + break; + case 2: + reg_value &=~SS5; + reg_value |=SS6; + reg_value &=~SS13; + break; + case 3: + reg_value &=~SS5; + reg_value |=SS6; + reg_value |=SS13; + break; + case 4: + reg_value |=SS5; + reg_value &=~SS6; + reg_value &=~SS13; + break; + case 5: + reg_value |=SS5; + reg_value &=~SS6; + reg_value |=SS13; + break; + } + + if (port_id == PORT2) + csr1_write(uniphy_index, SR_MII_CTRL_CHANNEL1_ADDRESS, reg_value); + else if (port_id == PORT3) + csr1_write(uniphy_index, SR_MII_CTRL_CHANNEL2_ADDRESS, reg_value); + else if (port_id == PORT4) + csr1_write(uniphy_index, SR_MII_CTRL_CHANNEL3_ADDRESS, reg_value); + else + csr1_write(uniphy_index, SR_MII_CTRL_ADDRESS, reg_value); +} + +void ppe_uniphy_usxgmii_duplex_set(uint32_t uniphy_index, int duplex) +{ + uint32_t reg_value = 0; + + reg_value = csr1_read(uniphy_index, SR_MII_CTRL_ADDRESS); + + if (duplex & 0x1) + reg_value |= DUPLEX_MODE; + else + reg_value &= ~DUPLEX_MODE; + + csr1_write(uniphy_index, SR_MII_CTRL_ADDRESS, reg_value); +} + +void ppe_uniphy_usxgmii_port_reset(uint32_t uniphy_index) +{ + uint32_t reg_value = 0; + + reg_value = csr1_read(uniphy_index, VR_XS_PCS_DIG_CTRL1_ADDRESS); + reg_value |= USRA_RST; + csr1_write(uniphy_index, VR_XS_PCS_DIG_CTRL1_ADDRESS, reg_value); +} diff --git a/sources/uboot-be550/drivers/net/ipq9574/ipq9574_uniphy.h b/sources/uboot-be550/drivers/net/ipq9574/ipq9574_uniphy.h new file mode 100644 index 00000000..4f885800 --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq9574/ipq9574_uniphy.h @@ -0,0 +1,123 @@ +/* + * Copyright (c) 2017-2019, 2021, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#define PPE_UNIPHY_INSTANCE0 0 +#define PPE_UNIPHY_INSTANCE1 1 +#define PPE_UNIPHY_INSTANCE2 2 + +#define GCC_UNIPHY_REG_INC 0x10 + +#define PPE_UNIPHY_OFFSET_CALIB_4 0x1E0 +#define UNIPHY_CALIBRATION_DONE 0x1 + +#define PPE_UNIPHY_BASE 0X07A00000 +#define PPE_UNIPHY_REG_INC 0x10000 +#define PPE_UNIPHY_MODE_CONTROL 0x46C +#define UNIPHY_XPCS_MODE (1 << 12) +#define UNIPHY_SG_PLUS_MODE (1 << 11) +#define UNIPHY_SG_MODE (1 << 10) +#define UNIPHY_CH0_PSGMII_QSGMII (1 << 9) +#define UNIPHY_CH0_QSGMII_SGMII (1 << 8) +#define UNIPHY_CH4_CH1_0_SGMII (1 << 2) +#define UNIPHY_CH1_CH0_SGMII (1 << 1) +#define UNIPHY_CH0_ATHR_CSCO_MODE_25M (1 << 0) + +#define UNIPHY_INSTANCE_LINK_DETECT 0x570 +#define UNIPHYQP_USXG_OPITON1 0x584 + +#define UNIPHY_MISC2_REG_OFFSET 0x218 +#define UNIPHY_MISC2_REG_SGMII_MODE 0x30 +#define UNIPHY_MISC2_REG_SGMII_PLUS_MODE 0x50 + +#define UNIPHY_MISC2_REG_VALUE 0x70 + +#define UNIPHY_MISC_SOURCE_SELECTION_REG_OFFSET 0x21c +#define UNIPHY_MISC_SRC_PHY_MODE 0xa882 + +#define UNIPHY_DEC_CHANNEL_0_INPUT_OUTPUT_4 0x480 +#define UNIPHY_FORCE_SPEED_25M (1 << 3) + +#define UNIPHY_PLL_RESET_REG_OFFSET 0x780 +#define UNIPHY_PLL_RESET_REG_VALUE 0x02bf +#define UNIPHY_PLL_RESET_REG_DEFAULT_VALUE 0x02ff + +#define SR_XS_PCS_KR_STS1_ADDRESS 0x30020 +#define UNIPHY_10GR_LINKUP 0x1 + +#define VR_XS_PCS_DIG_CTRL1_ADDRESS 0x38000 +#define VR_XS_PCS_EEE_MCTRL0_ADDRESS 0x38006 +#define VR_XS_PCS_KR_CTRL_ADDRESS 0x38007 +#define VR_XS_PCS_EEE_TXTIMER_ADDRESS 0x38008 +#define VR_XS_PCS_EEE_RXTIMER_ADDRESS 0x38009 +#define VR_XS_PCS_DIG_STS_ADDRESS 0x3800a +#define VR_XS_PCS_EEE_MCTRL1_ADDRESS 0x3800b + +#define SIGN_BIT (1 << 6) +#define MULT_FACT_100NS (1 << 8) +#define GMII_SRC_SEL (1 << 0) +#define USXG_EN (1 << 9) +#define USXG_MODE (5 << 10) +#define USRA_RST (1 << 10) +#define AM_COUNT (0x6018 << 0) +#define VR_RST (1 << 15) +#define UNIPHY_XPCS_TSL_TIMER (0xa << 0) +#define UNIPHY_XPCS_TLU_TIMER (0x3 << 6) +#define UNIPHY_XPCS_TWL_TIMER (0x16 << 8) +#define UNIPHY_XPCS_100US_TIMER (0xc8 << 0) +#define UNIPHY_XPCS_TWR_TIMER (0x1c << 8) +#define TRN_LPI (1 << 0) +#define TRN_RXLPI (1 << 8) +#define LRX_EN (1 << 0) +#define LTX_EN (1 << 1) + +#define VR_MII_AN_CTRL_CHANNEL1_ADDRESS 0x1a8001 +#define VR_MII_AN_CTRL_CHANNEL2_ADDRESS 0x1b8001 +#define VR_MII_AN_CTRL_CHANNEL3_ADDRESS 0x1c8001 +#define VR_MII_AN_CTRL_ADDRESS 0x1f8001 +#define MII_AN_INTR_EN (1 << 0) +#define MII_CTRL (1 << 8) + +#define VR_XAUI_MODE_CTRL_CHANNEL1_ADDRESS 0x1a8004 +#define VR_XAUI_MODE_CTRL_CHANNEL2_ADDRESS 0x1b8004 +#define VR_XAUI_MODE_CTRL_CHANNEL3_ADDRESS 0x1c8004 +#define VR_XAUI_MODE_CTRL_ADDRESS 0x1f8004 +#define IPG_CHECK 0x1 + +#define SR_MII_CTRL_CHANNEL1_ADDRESS 0x1a0000 +#define SR_MII_CTRL_CHANNEL2_ADDRESS 0x1b0000 +#define SR_MII_CTRL_CHANNEL3_ADDRESS 0x1c0000 +#define SR_MII_CTRL_ADDRESS 0x1f0000 +#define AN_ENABLE (1 << 12) +#define SS5 (1 << 5) +#define SS6 (1 << 6) +#define SS13 (1 << 13) +#define DUPLEX_MODE (1 << 8) + +#define VR_MII_AN_INTR_STS 0x1f8002 +#define CL37_ANCMPLT_INTR (1 << 0) + +enum uniphy_reset_type { + UNIPHY0_SOFT_RESET = 0, + UNIPHY0_XPCS_RESET, + UNIPHY1_SOFT_RESET, + UNIPHY1_XPCS_RESET, + UNIPHY2_SOFT_RESET, + UNIPHY2_XPCS_RESET, + UNIPHY_RST_MAX +}; + +void ppe_uniphy_mode_set(uint32_t uniphy_index, uint32_t mode); +void ppe_uniphy_usxgmii_port_reset(uint32_t uniphy_index); +void ppe_uniphy_usxgmii_duplex_set(uint32_t uniphy_index, int duplex); +void ppe_uniphy_usxgmii_speed_set(uint32_t uniphy_index, uint32_t port_id, int speed); +void ppe_uniphy_usxgmii_autoneg_completed(uint32_t uniphy_index); diff --git a/sources/uboot-be550/drivers/net/ipq_common/athrs17_phy.c b/sources/uboot-be550/drivers/net/ipq_common/athrs17_phy.c new file mode 100644 index 00000000..b4ef78b2 --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq_common/athrs17_phy.c @@ -0,0 +1,434 @@ +/* + * Copyright (c) 2015-2016, 2020 The Linux Foundation. All rights reserved. + * + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Manage the QTI S17C ethernet PHY. + * + * All definitions in this file are operating system independent! + */ + +#include +#include "athrs17_phy.h" + +/* + * Externel Common mdio read, PHY Name : IPQ MDIO1 + */ + +extern int ipq_mdio_write(int mii_id, int regnum, u16 value); +extern int ipq_mdio_read(int mii_id, int regnum, ushort *data); + +/****************************************************************************** + * FUNCTION DESCRIPTION: Read switch internal register. + * Switch internal register is accessed through the + * MDIO interface. MDIO access is only 16 bits wide so + * it needs the two time access to complete the internal + * register access. + * INPUT : register address + * OUTPUT : Register value + * + *****************************************************************************/ +static uint32_t athrs17_reg_read(uint32_t reg_addr) +{ + uint32_t reg_word_addr; + uint32_t phy_addr, reg_val; + uint16_t phy_val; + uint16_t tmp_val; + uint8_t phy_reg; + + /* change reg_addr to 16-bit word address, 32-bit aligned */ + reg_word_addr = (reg_addr & 0xfffffffc) >> 1; + + /* configure register high address */ + phy_addr = 0x18; + phy_reg = 0x0; + phy_val = (uint16_t) ((reg_word_addr >> 8) & 0x1ff); /* bit16-8 of reg address */ + ipq_mdio_write(phy_addr, phy_reg, phy_val); + /* + * For some registers such as MIBs, since it is read/clear, we should + * read the lower 16-bit register then the higher one + */ + + /* read register in lower address */ + phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */ + phy_reg = (uint8_t) (reg_word_addr & 0x1f); /* bit4-0 of reg address */ + ipq_mdio_read(phy_addr, phy_reg, &phy_val); + + /* read register in higher address */ + reg_word_addr++; + phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */ + phy_reg = (uint8_t) (reg_word_addr & 0x1f); /* bit4-0 of reg address */ + ipq_mdio_read(phy_addr, phy_reg, &tmp_val); + reg_val = (tmp_val << 16 | phy_val); + + return reg_val; +} + +/****************************************************************************** + * FUNCTION DESCRIPTION: Write switch internal register. + * Switch internal register is accessed through the + * MDIO interface. MDIO access is only 16 bits wide so + * it needs the two time access to complete the internal + * register access. + * INPUT : register address, value to be written + * OUTPUT : NONE + * + *****************************************************************************/ +static void athrs17_reg_write(uint32_t reg_addr, uint32_t reg_val) +{ + uint32_t reg_word_addr; + uint32_t phy_addr; + uint16_t phy_val; + uint8_t phy_reg; + + /* change reg_addr to 16-bit word address, 32-bit aligned */ + reg_word_addr = (reg_addr & 0xfffffffc) >> 1; + + /* configure register high address */ + phy_addr = 0x18; + phy_reg = 0x0; + phy_val = (uint16_t) ((reg_word_addr >> 8) & 0x1ff); /* bit16-8 of reg address */ + ipq_mdio_write(phy_addr, phy_reg, phy_val); + + /* + * For some registers such as ARL and VLAN, since they include BUSY bit + * in lower address, we should write the higher 16-bit register then the + * lower one + */ + + /* read register in higher address */ + reg_word_addr++; + phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */ + phy_reg = (uint8_t) (reg_word_addr & 0x1f); /* bit4-0 of reg address */ + phy_val = (uint16_t) ((reg_val >> 16) & 0xffff); + ipq_mdio_write(phy_addr, phy_reg, phy_val); + + /* write register in lower address */ + reg_word_addr--; + phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */ + phy_reg = (uint8_t) (reg_word_addr & 0x1f); /* bit4-0 of reg address */ + phy_val = (uint16_t) (reg_val & 0xffff); + ipq_mdio_write(phy_addr, phy_reg, phy_val); +} + +/********************************************************************* + * FUNCTION DESCRIPTION: V-lan configuration given by Switch team + Vlan 1:PHY0,1,2,3 and Mac 6 of s17c + Vlan 2:PHY4 and Mac 0 of s17c + * INPUT : NONE + * OUTPUT: NONE + *********************************************************************/ +void athrs17_vlan_config(void) +{ + athrs17_reg_write(S17_P0LOOKUP_CTRL_REG, 0x00140020); + athrs17_reg_write(S17_P0VLAN_CTRL0_REG, 0x20001); + + athrs17_reg_write(S17_P1LOOKUP_CTRL_REG, 0x0014005c); + athrs17_reg_write(S17_P1VLAN_CTRL0_REG, 0x10001); + + athrs17_reg_write(S17_P2LOOKUP_CTRL_REG, 0x0014005a); + athrs17_reg_write(S17_P2VLAN_CTRL0_REG, 0x10001); + + athrs17_reg_write(S17_P3LOOKUP_CTRL_REG, 0x00140056); + athrs17_reg_write(S17_P3VLAN_CTRL0_REG, 0x10001); + + athrs17_reg_write(S17_P4LOOKUP_CTRL_REG, 0x0014004e); + athrs17_reg_write(S17_P4VLAN_CTRL0_REG, 0x10001); + + athrs17_reg_write(S17_P5LOOKUP_CTRL_REG, 0x00140001); + athrs17_reg_write(S17_P5VLAN_CTRL0_REG, 0x20001); + + athrs17_reg_write(S17_P6LOOKUP_CTRL_REG, 0x0014001e); + athrs17_reg_write(S17_P6VLAN_CTRL0_REG, 0x10001); + printf("%s ...done\n", __func__); +} + +/******************************************************************* +* FUNCTION DESCRIPTION: Reset S17 register +* INPUT: NONE +* OUTPUT: NONE +*******************************************************************/ +int athrs17_init_switch(void) +{ + uint32_t data; + uint32_t i = 0; + + /* Reset the switch before initialization */ + athrs17_reg_write(S17_MASK_CTRL_REG, S17_MASK_CTRL_SOFT_RET); + do { + udelay(10); + data = athrs17_reg_read(S17_MASK_CTRL_REG); + i++; + if (i == 10){ + printf("QCA_8337: Failed to reset\n"); + return -1; + } + } while (data & S17_MASK_CTRL_SOFT_RET); + + i = 0; + + do { + udelay(10); + data = athrs17_reg_read(S17_GLOBAL_INT0_REG); + i++; + if (i == 10) + return -1; + } while ((data & S17_GLOBAL_INITIALIZED_STATUS) != S17_GLOBAL_INITIALIZED_STATUS); + + return 0; +} + +/********************************************************************* + * FUNCTION DESCRIPTION: Configure S17 register + * INPUT : NONE + * OUTPUT: NONE + *********************************************************************/ +void athrs17_reg_init(ipq_s17c_swt_cfg_t *swt_cfg) +{ + athrs17_reg_write(S17_MAC_PWR_REG, swt_cfg->mac_pwr); + + athrs17_reg_write(S17_GLOFW_CTRL1_REG, (S17_IGMP_JOIN_LEAVE_DPALL | + S17_BROAD_DPALL | + S17_MULTI_FLOOD_DPALL | + S17_UNI_FLOOD_DPALL)); + + if (swt_cfg->update) { + athrs17_reg_write(S17_P0STATUS_REG, swt_cfg->port0_status); + athrs17_reg_write(S17_P5PAD_MODE_REG, swt_cfg->pad5_mode); + athrs17_reg_write(S17_P0PAD_MODE_REG, swt_cfg->pad0_mode); + } else { + athrs17_reg_write(S17_P0STATUS_REG, (S17_SPEED_1000M | + S17_TXMAC_EN | + S17_RXMAC_EN | + S17_DUPLEX_FULL)); + + athrs17_reg_write(S17_P5PAD_MODE_REG, S17_MAC0_RGMII_RXCLK_DELAY); + + athrs17_reg_write(S17_P0PAD_MODE_REG, (S17_MAC0_RGMII_EN | + S17_MAC0_RGMII_TXCLK_DELAY | + S17_MAC0_RGMII_RXCLK_DELAY | + (0x1 << S17_MAC0_RGMII_TXCLK_SHIFT) | + (0x2 << S17_MAC0_RGMII_RXCLK_SHIFT))); + } + + printf("%s: complete\n", __func__); +} + +/********************************************************************* + * FUNCTION DESCRIPTION: Configure S17 register + * INPUT : NONE + * OUTPUT: NONE + *********************************************************************/ +void athrs17_reg_init_lan(ipq_s17c_swt_cfg_t *swt_cfg) +{ + uint32_t reg_val; + + if (swt_cfg->update) { + athrs17_reg_write(S17_P6STATUS_REG, swt_cfg->port6_status); + athrs17_reg_write(S17_MAC_PWR_REG, swt_cfg->mac_pwr); + athrs17_reg_write(S17_P6PAD_MODE_REG, swt_cfg->pad6_mode); + athrs17_reg_write(S17_PWS_REG, swt_cfg->port0); + athrs17_reg_write(S17_SGMII_CTRL_REG, swt_cfg->sgmii_ctrl); + } else { + + athrs17_reg_write(S17_P6STATUS_REG, (S17_SPEED_1000M | + S17_TXMAC_EN | + S17_RXMAC_EN | + S17_DUPLEX_FULL)); + + athrs17_reg_write(S17_MAC_PWR_REG, swt_cfg->mac_pwr); + reg_val = athrs17_reg_read(S17_P6PAD_MODE_REG); + athrs17_reg_write(S17_P6PAD_MODE_REG, (reg_val | S17_MAC6_SGMII_EN)); + + athrs17_reg_write(S17_PWS_REG, 0x2613a0); + + athrs17_reg_write(S17_SGMII_CTRL_REG,(S17c_SGMII_EN_PLL | + S17c_SGMII_EN_RX | + S17c_SGMII_EN_TX | + S17c_SGMII_EN_SD | + S17c_SGMII_BW_HIGH | + S17c_SGMII_SEL_CLK125M | + S17c_SGMII_TXDR_CTRL_600mV | + S17c_SGMII_CDR_BW_8 | + S17c_SGMII_DIS_AUTO_LPI_25M | + S17c_SGMII_MODE_CTRL_SGMII_PHY | + S17c_SGMII_PAUSE_SG_TX_EN_25M | + S17c_SGMII_ASYM_PAUSE_25M | + S17c_SGMII_PAUSE_25M | + S17c_SGMII_HALF_DUPLEX_25M | + S17c_SGMII_FULL_DUPLEX_25M)); + } + athrs17_reg_write(S17_MODULE_EN_REG, S17_MIB_COUNTER_ENABLE); +} + +struct athrs17_regmap { + uint32_t start; + uint32_t end; +}; + +struct athrs17_regmap regmap[] = { + { 0x000, 0x0e4 }, + { 0x100, 0x168 }, + { 0x200, 0x270 }, + { 0x400, 0x454 }, + { 0x600, 0x718 }, + { 0x800, 0xb70 }, + { 0xC00, 0xC80 }, + { 0x1100, 0x11a7 }, + { 0x1200, 0x12a7 }, + { 0x1300, 0x13a7 }, + { 0x1400, 0x14a7 }, + { 0x1600, 0x16a7 }, +}; + +int do_ar8xxx_dump(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { + int i; + + for (i = 0; i < ARRAY_SIZE(regmap); i++) { + uint32_t reg; + struct athrs17_regmap *section = ®map[i]; + + for (reg = section->start; reg <= section->end; reg += sizeof(uint32_t)) { + uint32_t val = athrs17_reg_read(reg); + printf("%03zx: %08zx\n", reg, val); + } + } + + return 0; +}; +U_BOOT_CMD( + ar8xxx_dump, 1, 1, do_ar8xxx_dump, + "Dump ar8xxx registers", + "\n - print all ar8xxx registers\n" +); + +/********************************************************************* + * + * FUNCTION DESCRIPTION: This function invokes RGMII, + * SGMII switch init routines. + * INPUT : ipq_s17c_swt_cfg_t * + * OUTPUT: NONE + * +**********************************************************************/ +int ipq_athrs17_init(ipq_s17c_swt_cfg_t *swt_cfg) +{ + int ret; + + if (swt_cfg == NULL) + return -1; + + ret = athrs17_init_switch(); + if (ret != -1) { + athrs17_reg_init(swt_cfg); + athrs17_reg_init_lan(swt_cfg); + if (!(swt_cfg->skip_vlan)) + athrs17_vlan_config(); + printf ("S17c init done\n"); + } + + return ret; +} + +int ipq_qca8337_switch_init(ipq_s17c_swt_cfg_t *s17c_swt_cfg) +{ + int port; + for (port = 0; port < s17c_swt_cfg->port_count; ++port) { + u32 phy_val; + + /* phy powerdown */ + ipq_mdio_write(s17c_swt_cfg->port_phy_address[port], 0x0, + 0x0800); + phy_val = ipq_mdio_read(s17c_swt_cfg->port_phy_address[port], + 0x3d, NULL); + phy_val &= ~0x0040; + ipq_mdio_write(s17c_swt_cfg->port_phy_address[port], 0x3d, + phy_val); + + /* + * PHY will stop the tx clock for a while when link is down + * en_anychange debug port 0xb bit13 = 0 //speed up link down tx_clk + * sel_rst_80us debug port 0xb bit10 = 0 //speed up speed mode change to 2'b10 tx_clk + */ + phy_val = ipq_mdio_read(s17c_swt_cfg->port_phy_address[port], + 0xb, NULL); + phy_val &= ~0x2400; + ipq_mdio_write(s17c_swt_cfg->port_phy_address[port], 0xb, + phy_val); + mdelay(100); + } + + if (ipq_athrs17_init(s17c_swt_cfg) != 0) { + printf("QCA_8337 switch init failed \n"); + return -1; + } + + for (port = 0; port < s17c_swt_cfg->port_count; ++port) { + ipq_mdio_write(s17c_swt_cfg->port_phy_address[port], + MII_ADVERTISE, ADVERTISE_ALL | + ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); + /* phy reg 0x9, b10,1 = Prefer multi-port device (master) */ + ipq_mdio_write(s17c_swt_cfg->port_phy_address[port], + MII_CTRL1000, (0x0400|ADVERTISE_1000FULL)); + ipq_mdio_write(s17c_swt_cfg->port_phy_address[port], + MII_BMCR, BMCR_RESET | BMCR_ANENABLE); + mdelay(100); + } + + return 0; +} + +int ipq_qca8337_link_update(ipq_s17c_swt_cfg_t *s17c_swt_cfg) +{ + uint16_t phy_data; + int status = 1; + + for(int i = 0; i < s17c_swt_cfg->port_count; ++i){ + phy_data = ipq_mdio_read(s17c_swt_cfg->port_phy_address[i], + 0x11, NULL); + + if (phy_data == 0x50) + continue; + + /* Atleast one port should be link up*/ + if (phy_data & LINK_UP) + status = 0; + + printf("QCA8337: Port%d %s ", i + 1, LINK(phy_data)); + + switch(SPEED(phy_data)){ + case SPEED_1000M: + printf("Speed :1000M "); + break; + case SPEED_100M: + printf("Speed :100M "); + break; + default: + printf("Speed :10M "); + } + + printf ("%s \n", DUPLEX(phy_data)); + } + return status; +} + +void ipq_s17c_switch_reset(int gpio) +{ + unsigned int *switch_gpio_base = + (unsigned int *)GPIO_CONFIG_ADDR(gpio); + + writel(0x203, switch_gpio_base); + writel(0x0, GPIO_IN_OUT_ADDR(gpio)); + mdelay(500); + writel(0x2, GPIO_IN_OUT_ADDR(gpio)); +} diff --git a/sources/uboot-be550/drivers/net/ipq_common/athrs17_phy.h b/sources/uboot-be550/drivers/net/ipq_common/athrs17_phy.h new file mode 100644 index 00000000..7b473e48 --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq_common/athrs17_phy.h @@ -0,0 +1,630 @@ +/* + * Copyright (c) 2015-2016, 2020 The Linux Foundation. All rights reserved. + * + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _ATHRS17_PHY_H +#define _ATHRS17_PHY_H + +/*****************/ +/* PHY Registers */ +/*****************/ +#define ATHR_PHY_CONTROL 0 +#define ATHR_PHY_STATUS 1 +#define ATHR_PHY_ID1 2 +#define ATHR_PHY_ID2 3 +#define ATHR_AUTONEG_ADVERT 4 +#define ATHR_LINK_PARTNER_ABILITY 5 +#define ATHR_AUTONEG_EXPANSION 6 +#define ATHR_NEXT_PAGE_TRANSMIT 7 +#define ATHR_LINK_PARTNER_NEXT_PAGE 8 +#define ATHR_1000BASET_CONTROL 9 +#define ATHR_1000BASET_STATUS 10 +#define ATHR_PHY_SPEC_CONTROL 16 +#define ATHR_PHY_SPEC_STATUS 17 +#define ATHR_DEBUG_PORT_ADDRESS 29 +#define ATHR_DEBUG_PORT_DATA 30 + +/* ATHR_PHY_CONTROL fields */ +#define ATHR_CTRL_SOFTWARE_RESET 0x8000 +#define ATHR_CTRL_SPEED_LSB 0x2000 +#define ATHR_CTRL_AUTONEGOTIATION_ENABLE 0x1000 +#define ATHR_CTRL_RESTART_AUTONEGOTIATION 0x0200 +#define ATHR_CTRL_SPEED_FULL_DUPLEX 0x0100 +#define ATHR_CTRL_SPEED_MSB 0x0040 + +#define ATHR_RESET_DONE(phy_control) \ + (((phy_control) & (ATHR_CTRL_SOFTWARE_RESET)) == 0) + +/* Phy status fields */ +#define ATHR_STATUS_AUTO_NEG_DONE 0x0020 + +#define ATHR_AUTONEG_DONE(ip_phy_status) \ + (((ip_phy_status) & \ + (ATHR_STATUS_AUTO_NEG_DONE)) == \ + (ATHR_STATUS_AUTO_NEG_DONE)) + +/* Link Partner ability */ +#define ATHR_LINK_100BASETX_FULL_DUPLEX 0x0100 +#define ATHR_LINK_100BASETX 0x0080 +#define ATHR_LINK_10BASETX_FULL_DUPLEX 0x0040 +#define ATHR_LINK_10BASETX 0x0020 + +/* Advertisement register. */ +#define ATHR_ADVERTISE_NEXT_PAGE 0x8000 +#define ATHR_ADVERTISE_ASYM_PAUSE 0x0800 +#define ATHR_ADVERTISE_PAUSE 0x0400 +#define ATHR_ADVERTISE_100FULL 0x0100 +#define ATHR_ADVERTISE_100HALF 0x0080 +#define ATHR_ADVERTISE_10FULL 0x0040 +#define ATHR_ADVERTISE_10HALF 0x0020 + +#define ATHR_ADVERTISE_ALL (ATHR_ADVERTISE_ASYM_PAUSE | ATHR_ADVERTISE_PAUSE | \ + ATHR_ADVERTISE_10HALF | ATHR_ADVERTISE_10FULL | \ + ATHR_ADVERTISE_100HALF | ATHR_ADVERTISE_100FULL) + +/* 1000BASET_CONTROL */ +#define ATHR_ADVERTISE_1000FULL 0x0200 + +/* Phy Specific status fields */ +#define ATHER_STATUS_LINK_MASK 0xC000 +#define ATHER_STATUS_LINK_SHIFT 14 +#define ATHER_STATUS_FULL_DEPLEX 0x2000 +#define ATHR_STATUS_LINK_PASS 0x0400 +#define ATHR_STATUS_RESOVLED 0x0800 + +/*phy debug port register */ +#define ATHER_DEBUG_SERDES_REG 5 + +/* Serdes debug fields */ +#define ATHER_SERDES_BEACON 0x0100 + +/* S17 CSR Registers */ + +#define S17_ENABLE_CPU_BROADCAST (1 << 26) + +#define S17_PHY_LINK_CHANGE_REG 0x4 +#define S17_PHY_LINK_UP 0x400 +#define S17_PHY_LINK_DOWN 0x800 +#define S17_PHY_LINK_DUPLEX_CHANGE 0x2000 +#define S17_PHY_LINK_SPEED_CHANGE 0x4000 +#define S17_PHY_LINK_INTRS (PHY_LINK_UP | PHY_LINK_DOWN | PHY_LINK_DUPLEX_CHANGE | PHY_LINK_SPEED_CHANGE) + +#define S17_MASK_CTRL_REG 0x0000 +#define S17_P0PAD_MODE_REG 0x0004 +#define S17_P5PAD_MODE_REG 0x0008 +#define S17_P6PAD_MODE_REG 0x000c +#define S17_PWS_REG 0x0010 +#define S17_GLOBAL_INT0_REG 0x0020 +#define S17_GLOBAL_INT1_REG 0x0024 +#define S17_GLOBAL_INTMASK0 0x0028 +#define S17_GLOBAL_INTMASK1 0x002c +#define S17_MODULE_EN_REG 0x0030 +#define S17_MIB_REG 0x0034 +#define S17_INTF_HIADDR_REG 0x0038 +#define S17_MDIO_CTRL_REG 0x003c +#define S17_BIST_CTRL_REG 0x0040 +#define S17_BIST_REC_REG 0x0044 +#define S17_SERVICE_REG 0x0048 +#define S17_LED_CTRL0_REG 0x0050 +#define S17_LED_CTRL1_REG 0x0054 +#define S17_LED_CTRL2_REG 0x0058 +#define S17_LED_CTRL3_REG 0x005c +#define S17_MACADDR0_REG 0x0060 +#define S17_MACADDR1_REG 0x0064 +#define S17_MAX_FRAME_SIZE_REG 0x0078 +#define S17_P0STATUS_REG 0x007c +#define S17_P1STATUS_REG 0x0080 +#define S17_P2STATUS_REG 0x0084 +#define S17_P3STATUS_REG 0x0088 +#define S17_P4STATUS_REG 0x008c +#define S17_P5STATUS_REG 0x0090 +#define S17_P6STATUS_REG 0x0094 +#define S17_HDRCTRL_REG 0x0098 +#define S17_P0HDRCTRL_REG 0x009c +#define S17_P1HDRCTRL_REG 0x00A0 +#define S17_P2HDRCTRL_REG 0x00a4 +#define S17_P3HDRCTRL_REG 0x00a8 +#define S17_P4HDRCTRL_REG 0x00ac +#define S17_P5HDRCTRL_REG 0x00b0 +#define S17_P6HDRCTRL_REG 0x00b4 +#define S17_SGMII_CTRL_REG 0x00e0 +#define S17_MAC_PWR_REG 0x00e4 +#define S17_EEE_CTRL_REG 0x0100 + +/* ACL Registers */ +#define S17_ACL_FUNC0_REG 0x0400 +#define S17_ACL_FUNC1_REG 0x0404 +#define S17_ACL_FUNC2_REG 0x0408 +#define S17_ACL_FUNC3_REG 0x040c +#define S17_ACL_FUNC4_REG 0x0410 +#define S17_ACL_FUNC5_REG 0x0414 +#define S17_PRIVATE_IP_REG 0x0418 +#define S17_P0VLAN_CTRL0_REG 0x0420 +#define S17_P0VLAN_CTRL1_REG 0x0424 +#define S17_P1VLAN_CTRL0_REG 0x0428 +#define S17_P1VLAN_CTRL1_REG 0x042c +#define S17_P2VLAN_CTRL0_REG 0x0430 +#define S17_P2VLAN_CTRL1_REG 0x0434 +#define S17_P3VLAN_CTRL0_REG 0x0438 +#define S17_P3VLAN_CTRL1_REG 0x043c +#define S17_P4VLAN_CTRL0_REG 0x0440 +#define S17_P4VLAN_CTRL1_REG 0x0444 +#define S17_P5VLAN_CTRL0_REG 0x0448 +#define S17_P5VLAN_CTRL1_REG 0x044c +#define S17_P6VLAN_CTRL0_REG 0x0450 +#define S17_P6VLAN_CTRL1_REG 0x0454 + +/* Table Lookup Registers */ +#define S17_ATU_DATA0_REG 0x0600 +#define S17_ATU_DATA1_REG 0x0604 +#define S17_ATU_DATA2_REG 0x0608 +#define S17_ATU_FUNC_REG 0x060C +#define S17_VTU_FUNC0_REG 0x0610 +#define S17_VTU_FUNC1_REG 0x0614 +#define S17_ARL_CTRL_REG 0x0618 +#define S17_GLOFW_CTRL0_REG 0x0620 +#define S17_GLOFW_CTRL1_REG 0x0624 +#define S17_GLOLEARN_LIMIT_REG 0x0628 +#define S17_TOS_PRIMAP_REG0 0x0630 +#define S17_TOS_PRIMAP_REG1 0x0634 +#define S17_TOS_PRIMAP_REG2 0x0638 +#define S17_TOS_PRIMAP_REG3 0x063c +#define S17_TOS_PRIMAP_REG4 0x0640 +#define S17_TOS_PRIMAP_REG5 0x0644 +#define S17_TOS_PRIMAP_REG6 0x0648 +#define S17_TOS_PRIMAP_REG7 0x064c +#define S17_VLAN_PRIMAP_REG0 0x0650 +#define S17_LOOP_CHECK_REG 0x0654 +#define S17_P0LOOKUP_CTRL_REG 0x0660 +#define S17_P0PRI_CTRL_REG 0x0664 +#define S17_P0LEARN_LMT_REG 0x0668 +#define S17_P1LOOKUP_CTRL_REG 0x066c +#define S17_P1PRI_CTRL_REG 0x0670 +#define S17_P1LEARN_LMT_REG 0x0674 +#define S17_P2LOOKUP_CTRL_REG 0x0678 +#define S17_P2PRI_CTRL_REG 0x067c +#define S17_P2LEARN_LMT_REG 0x0680 +#define S17_P3LOOKUP_CTRL_REG 0x0684 +#define S17_P3PRI_CTRL_REG 0x0688 +#define S17_P3LEARN_LMT_REG 0x068c +#define S17_P4LOOKUP_CTRL_REG 0x0690 +#define S17_P4PRI_CTRL_REG 0x0694 +#define S17_P4LEARN_LMT_REG 0x0698 +#define S17_P5LOOKUP_CTRL_REG 0x069c +#define S17_P5PRI_CTRL_REG 0x06a0 +#define S17_P5LEARN_LMT_REG 0x06a4 +#define S17_P6LOOKUP_CTRL_REG 0x06a8 +#define S17_P6PRI_CTRL_REG 0x06ac +#define S17_P6LEARN_LMT_REG 0x06b0 +#define S17_GLO_TRUNK_CTRL0_REG 0x0700 +#define S17_GLO_TRUNK_CTRL1_REG 0x0704 +#define S17_GLO_TRUNK_CTRL2_REG 0x0708 + +/* Queue Management Registers */ +#define S17_PORT0_HOL_CTRL0 0x0970 +#define S17_PORT0_HOL_CTRL1 0x0974 +#define S17_PORT1_HOL_CTRL0 0x0978 +#define S17_PORT1_HOL_CTRL1 0x097c +#define S17_PORT2_HOL_CTRL0 0x0980 +#define S17_PORT2_HOL_CTRL1 0x0984 +#define S17_PORT3_HOL_CTRL0 0x0988 +#define S17_PORT3_HOL_CTRL1 0x098c +#define S17_PORT4_HOL_CTRL0 0x0990 +#define S17_PORT4_HOL_CTRL1 0x0994 +#define S17_PORT5_HOL_CTRL0 0x0998 +#define S17_PORT5_HOL_CTRL1 0x099c +#define S17_PORT6_HOL_CTRL0 0x09a0 +#define S17_PORT6_HOL_CTRL1 0x09a4 + +/* Port flow control registers */ +#define S17_P0_FLCTL_REG 0x09b0 +#define S17_P1_FLCTL_REG 0x09b4 +#define S17_P2_FLCTL_REG 0x09b8 +#define S17_P3_FLCTL_REG 0x09bc +#define S17_P4_FLCTL_REG 0x09c0 +#define S17_P5_FLCTL_REG 0x09c4 + +/* Packet Edit registers */ +#define S17_PKT_EDIT_CTRL 0x0c00 +#define S17_P0Q_REMAP_REG0 0x0c40 +#define S17_P0Q_REMAP_REG1 0x0c44 +#define S17_P1Q_REMAP_REG0 0x0c48 +#define S17_P2Q_REMAP_REG0 0x0c4c +#define S17_P3Q_REMAP_REG0 0x0c50 +#define S17_P4Q_REMAP_REG0 0x0c54 +#define S17_P5Q_REMAP_REG0 0x0c58 +#define S17_P5Q_REMAP_REG1 0x0c5c +#define S17_P6Q_REMAP_REG0 0x0c60 +#define S17_P6Q_REMAP_REG1 0x0c64 +#define S17_ROUTER_VID0 0x0c70 +#define S17_ROUTER_VID1 0x0c74 +#define S17_ROUTER_VID2 0x0c78 +#define S17_ROUTER_VID3 0x0c7c +#define S17_ROUTER_EG_VLAN_MODE 0x0c80 + +/* L3 Registers */ +#define S17_HROUTER_CTRL_REG 0x0e00 +#define S17_HROUTER_PBCTRL0_REG 0x0e04 +#define S17_HROUTER_PBCTRL1_REG 0x0e08 +#define S17_HROUTER_PBCTRL2_REG 0x0e0c +#define S17_WCMP_HASH_TABLE0_REG 0x0e10 +#define S17_WCMP_HASH_TABLE1_REG 0x0e14 +#define S17_WCMP_HASH_TABLE2_REG 0x0e18 +#define S17_WCMP_HASH_TABLE3_REG 0x0e1c +#define S17_WCMP_NHOP_TABLE0_REG 0x0e20 +#define S17_WCMP_NHOP_TABLE1_REG 0x0e24 +#define S17_WCMP_NHOP_TABLE2_REG 0x0e28 +#define S17_WCMP_NHOP_TABLE3_REG 0x0e2c +#define S17_ARP_ENTRY_CTRL_REG 0x0e30 +#define S17_ARP_USECNT_REG 0x0e34 +#define S17_HNAT_CTRL_REG 0x0e38 +#define S17_NAPT_ENTRY_CTRL0_REG 0x0e3c +#define S17_NAPT_ENTRY_CTRL1_REG 0x0e40 +#define S17_NAPT_USECNT_REG 0x0e44 +#define S17_ENTRY_EDIT_DATA0_REG 0x0e48 +#define S17_ENTRY_EDIT_DATA1_REG 0x0e4c +#define S17_ENTRY_EDIT_DATA2_REG 0x0e50 +#define S17_ENTRY_EDIT_DATA3_REG 0x0e54 +#define S17_ENTRY_EDIT_CTRL_REG 0x0e58 +#define S17_HNAT_PRIVATE_IP_REG 0x0e5c + +/* MIB counters */ +#define S17_MIB_PORT0 0x1000 +#define S17_MIB_PORT1 0x1100 +#define S17_MIB_PORT2 0x1200 +#define S17_MIB_PORT3 0x1300 +#define S17_MIB_PORT4 0x1400 +#define S17_MIB_PORT5 0x1500 +#define S17_MIB_PORT6 0x1600 + +#define S17_MIB_COUNTER_ENABLE (1 << 0) +#define S17_MIB_NON_CLEAR (1 << 20) + +#define S17_MIB_RXBROAD 0x0 +#define S17_MIB_RXPAUSE 0x4 +#define S17_MIB_RXMULTI 0x8 +#define S17_MIB_RXFCSERR 0xC +#define S17_MIB_RXALIGNERR 0x10 +#define S17_MIB_RXUNDERSIZE 0x14 +#define S17_MIB_RXFRAG 0x18 +#define S17_MIB_RX64B 0x1C +#define S17_MIB_RX128B 0x20 +#define S17_MIB_RX256B 0x24 +#define S17_MIB_RX512B 0x28 +#define S17_MIB_RX1024B 0x2C +#define S17_MIB_RX1518B 0x30 +#define S17_MIB_RXMAXB 0x34 +#define S17_MIB_RXTOOLONG 0x38 +#define S17_MIB_RXBYTE1 0x3C +#define S17_MIB_RXBYTE2 0x40 +#define S17_MIB_RXOVERFLOW 0x4C +#define S17_MIB_FILTERED 0x50 +#define S17_MIB_TXBROAD 0x54 +#define S17_MIB_TXPAUSE 0x58 +#define S17_MIB_TXMULTI 0x5C +#define S17_MIB_TXUNDERRUN 0x60 +#define S17_MIB_TX64B 0x64 +#define S17_MIB_TX128B 0x68 +#define S17_MIB_TX256B 0x6c +#define S17_MIB_TX512B 0x70 +#define S17_MIB_TX1024B 0x74 +#define S17_MIB_TX1518B 0x78 +#define S17_MIB_TXMAXB 0x7C +#define S17_MIB_TXOVERSIZE 0x80 +#define S17_MIB_TXBYTE1 0x84 +#define S17_MIB_TXBYTE2 0x88 +#define S17_MIB_TXCOL 0x8C +#define S17_MIB_TXABORTCOL 0x90 +#define S17_MIB_TXMULTICOL 0x94 +#define S17_MIB_TXSINGLECOL 0x98 +#define S17_MIB_TXEXCDEFER 0x9C +#define S17_MIB_TXDEFER 0xA0 +#define S17_MIB_TXLATECOL 0xA4 + +/* Register fields */ +#define S17_CHIPID_V1_0 0x1201 +#define S17_CHIPID_V1_1 0x1202 + +#define S17_MASK_CTRL_SOFT_RET (1 << 31) + +#define S17_GLOBAL_INT0_ACL_INI_INT (1<<29) +#define S17_GLOBAL_INT0_LOOKUP_INI_INT (1<<28) +#define S17_GLOBAL_INT0_QM_INI_INT (1<<27) +#define S17_GLOBAL_INT0_MIB_INI_INT (1<<26) +#define S17_GLOBAL_INT0_OFFLOAD_INI_INT (1<<25) +#define S17_GLOBAL_INT0_HARDWARE_INI_DONE (1<<24) + +#define S17_GLOBAL_INITIALIZED_STATUS \ + ( \ + S17_GLOBAL_INT0_ACL_INI_INT | \ + S17_GLOBAL_INT0_LOOKUP_INI_INT | \ + S17_GLOBAL_INT0_QM_INI_INT | \ + S17_GLOBAL_INT0_MIB_INI_INT | \ + S17_GLOBAL_INT0_OFFLOAD_INI_INT | \ + S17_GLOBAL_INT0_HARDWARE_INI_DONE \ + ) + +#define S17_MAC0_MAC_MII_RXCLK_SEL (1 << 0) +#define S17_MAC0_MAC_MII_TXCLK_SEL (1 << 1) +#define S17_MAC0_MAC_MII_EN (1 << 2) +#define S17_MAC0_MAC_GMII_RXCLK_SEL (1 << 4) +#define S17_MAC0_MAC_GMII_TXCLK_SEL (1 << 5) +#define S17_MAC0_MAC_GMII_EN (1 << 6) +#define S17_MAC0_SGMII_EN (1 << 7) +#define S17_MAC0_PHY_MII_RXCLK_SEL (1 << 8) +#define S17_MAC0_PHY_MII_TXCLK_SEL (1 << 9) +#define S17_MAC0_PHY_MII_EN (1 << 10) +#define S17_MAC0_PHY_MII_PIPE_SEL (1 << 11) +#define S17_MAC0_PHY_GMII_RXCLK_SEL (1 << 12) +#define S17_MAC0_PHY_GMII_TXCLK_SEL (1 << 13) +#define S17_MAC0_PHY_GMII_EN (1 << 14) +#define S17_MAC0_RGMII_RXCLK_SHIFT 20 +#define S17_MAC0_RGMII_TXCLK_SHIFT 22 +#define S17_MAC0_RGMII_RXCLK_DELAY (1 << 24) +#define S17_MAC0_RGMII_TXCLK_DELAY (1 << 25) +#define S17_MAC0_RGMII_EN (1 << 26) + +#define S17_MAC5_MAC_MII_RXCLK_SEL (1 << 0) +#define S17_MAC5_MAC_MII_TXCLK_SEL (1 << 1) +#define S17_MAC5_MAC_MII_EN (1 << 2) +#define S17_MAC5_PHY_MII_RXCLK_SEL (1 << 8) +#define S17_MAC5_PHY_MII_TXCLK_SEL (1 << 9) +#define S17_MAC5_PHY_MII_EN (1 << 10) +#define S17_MAC5_PHY_MII_PIPE_SEL (1 << 11) +#define S17_MAC5_RGMII_RXCLK_SHIFT 20 +#define S17_MAC5_RGMII_TXCLK_SHIFT 22 +#define S17_MAC5_RGMII_RXCLK_DELAY (1 << 24) +#define S17_MAC5_RGMII_TXCLK_DELAY (1 << 25) +#define S17_MAC5_RGMII_EN (1 << 26) + +#define S17_MAC6_MAC_MII_RXCLK_SEL (1 << 0) +#define S17_MAC6_MAC_MII_TXCLK_SEL (1 << 1) +#define S17_MAC6_MAC_MII_EN (1 << 2) +#define S17_MAC6_MAC_GMII_RXCLK_SEL (1 << 4) +#define S17_MAC6_MAC_GMII_TXCLK_SEL (1 << 5) +#define S17_MAC6_MAC_GMII_EN (1 << 6) +#define S17_MAC6_SGMII_EN (1 << 7) +#define S17_MAC6_PHY_MII_RXCLK_SEL (1 << 8) +#define S17_MAC6_PHY_MII_TXCLK_SEL (1 << 9) +#define S17_MAC6_PHY_MII_EN (1 << 10) +#define S17_MAC6_PHY_MII_PIPE_SEL (1 << 11) +#define S17_MAC6_PHY_GMII_RXCLK_SEL (1 << 12) +#define S17_MAC6_PHY_GMII_TXCLK_SEL (1 << 13) +#define S17_MAC6_PHY_GMII_EN (1 << 14) +#define S17_PHY4_GMII_EN (1 << 16) +#define S17_PHY4_RGMII_EN (1 << 17) +#define S17_PHY4_MII_EN (1 << 18) +#define S17_MAC6_RGMII_RXCLK_SHIFT 20 +#define S17_MAC6_RGMII_TXCLK_SHIFT 22 +#define S17_MAC6_RGMII_RXCLK_DELAY (1 << 24) +#define S17_MAC6_RGMII_TXCLK_DELAY (1 << 25) +#define S17_MAC6_RGMII_EN (1 << 26) + +#define S17_SPEED_10M (0 << 0) +#define S17_SPEED_100M (1 << 0) +#define S17_SPEED_1000M (2 << 0) +#define S17_TXMAC_EN (1 << 2) +#define S17_RXMAC_EN (1 << 3) +#define S17_TX_FLOW_EN (1 << 4) +#define S17_RX_FLOW_EN (1 << 5) +#define S17_DUPLEX_FULL (1 << 6) +#define S17_DUPLEX_HALF (0 << 6) +#define S17_TX_HALF_FLOW_EN (1 << 7) +#define S17_LINK_EN (1 << 9) +#define S17_FLOW_LINK_EN (1 << 12) +#define S17_PORT_STATUS_DEFAULT (S17_SPEED_1000M | S17_TXMAC_EN | \ + S17_RXMAC_EN | S17_TX_FLOW_EN | \ + S17_RX_FLOW_EN | S17_DUPLEX_FULL | \ + S17_TX_HALF_FLOW_EN) + +#define S17_PORT_STATUS_AZ_DEFAULT (S17_SPEED_1000M | S17_TXMAC_EN | \ + S17_RXMAC_EN | S17_TX_FLOW_EN | \ + S17_RX_FLOW_EN | S17_DUPLEX_FULL) + + +#define S17_HDRLENGTH_SEL (1 << 16) +#define S17_HDR_VALUE 0xAAAA + +#define S17_TXHDR_MODE_NO 0 +#define S17_TXHDR_MODE_MGM 1 +#define S17_TXHDR_MODE_ALL 2 +#define S17_RXHDR_MODE_NO (0 << 2) +#define S17_RXHDR_MODE_MGM (1 << 2) +#define S17_RXHDR_MODE_ALL (2 << 2) + +#define S17_CPU_PORT_EN (1 << 10) +#define S17_PPPOE_REDIR_EN (1 << 8) +#define S17_MIRROR_PORT_SHIFT 4 +#define S17_IGMP_COPY_EN (1 << 3) +#define S17_RIP_COPY_EN (1 << 2) +#define S17_EAPOL_REDIR_EN (1 << 0) + +#define S17_IGMP_JOIN_LEAVE_DP_SHIFT 24 +#define S17_BROAD_DP_SHIFT 16 +#define S17_MULTI_FLOOD_DP_SHIFT 8 +#define S17_UNI_FLOOD_DP_SHIFT 0 +#define S17_IGMP_JOIN_LEAVE_DPALL (0x7f << S17_IGMP_JOIN_LEAVE_DP_SHIFT) +#define S17_BROAD_DPALL (0x7f << S17_BROAD_DP_SHIFT) +#define S17_MULTI_FLOOD_DPALL (0x7f << S17_MULTI_FLOOD_DP_SHIFT) +#define S17_UNI_FLOOD_DPALL (0x7f << S17_UNI_FLOOD_DP_SHIFT) + +#define S17_PWS_CHIP_AR8327 (1 << 30) +#define S17c_PWS_SERDES_ANEG_DISABLE (1 << 7) + +/* S17_PHY_CONTROL fields */ +#define S17_CTRL_SOFTWARE_RESET 0x8000 +#define S17_CTRL_SPEED_LSB 0x2000 +#define S17_CTRL_AUTONEGOTIATION_ENABLE 0x1000 +#define S17_CTRL_RESTART_AUTONEGOTIATION 0x0200 +#define S17_CTRL_SPEED_FULL_DUPLEX 0x0100 +#define S17_CTRL_SPEED_MSB 0x0040 + +/* For EEE_CTRL_REG */ +#define S17_LPI_DISABLE_P1 (1 << 4) +#define S17_LPI_DISABLE_P2 (1 << 6) +#define S17_LPI_DISABLE_P3 (1 << 8) +#define S17_LPI_DISABLE_P4 (1 << 10) +#define S17_LPI_DISABLE_P5 (1 << 12) +#define S17_LPI_DISABLE_ALL 0x1550 + +/* For MMD register control */ +#define S17_MMD_FUNC_ADDR (0 << 14) +#define S17_MMD_FUNC_DATA (1 << 14) +#define S17_MMD_FUNC_DATA_2 (2 << 14) +#define S17_MMD_FUNC_DATA_3 (3 << 14) + +/* For phyInfo_t azFeature */ +#define S17_8023AZ_PHY_ENABLED (1 << 0) +#define S17_8023AZ_PHY_LINKED (1 << 1) + +/* Queue Management registe fields */ +#define S17_HOL_CTRL0_LAN 0x2a008888 /* egress priority 8, eg_portq = 0x2a */ +#define S17_HOL_CTRL0_WAN 0x2a666666 /* egress priority 6, eg_portq = 0x2a */ +#define S17_HOL_CTRL1_DEFAULT 0xc6 /* enable HOL control */ + +/* Packet Edit register fields */ +#define S17_ROUTER_EG_UNMOD 0x0 /* unmodified */ +#define S17_ROUTER_EG_WOVLAN 0x1 /* without VLAN */ +#define S17_ROUTER_EG_WVLAN 0x2 /* with VLAN */ +#define S17_ROUTER_EG_UNTOUCH 0x3 /* untouched */ +#define S17_ROUTER_EG_MODE_DEFAULT 0x01111111 /* all ports without VLAN */ + +#define S17_RESET_DONE(phy_control) \ + (((phy_control) & (S17_CTRL_SOFTWARE_RESET)) == 0) + +/* Phy status fields */ +#define S17_STATUS_AUTO_NEG_DONE 0x0020 + +#define S17_AUTONEG_DONE(ip_phy_status) \ + (((ip_phy_status) & \ + (S17_STATUS_AUTO_NEG_DONE)) == \ + (S17_STATUS_AUTO_NEG_DONE)) + +/* Link Partner ability */ +#define S17_LINK_100BASETX_FULL_DUPLEX 0x0100 +#define S17_LINK_100BASETX 0x0080 +#define S17_LINK_10BASETX_FULL_DUPLEX 0x0040 +#define S17_LINK_10BASETX 0x0020 + +/* Advertisement register. */ +#define S17_ADVERTISE_NEXT_PAGE 0x8000 +#define S17_ADVERTISE_ASYM_PAUSE 0x0800 +#define S17_ADVERTISE_PAUSE 0x0400 +#define S17_ADVERTISE_100FULL 0x0100 +#define S17_ADVERTISE_100HALF 0x0080 +#define S17_ADVERTISE_10FULL 0x0040 +#define S17_ADVERTISE_10HALF 0x0020 + +#define S17_ADVERTISE_ALL (S17_ADVERTISE_ASYM_PAUSE | S17_ADVERTISE_PAUSE | \ + S17_ADVERTISE_10HALF | S17_ADVERTISE_10FULL | \ + S17_ADVERTISE_100HALF | S17_ADVERTISE_100FULL) + +/* 1000BASET_CONTROL */ +#define S17_ADVERTISE_1000FULL 0x0200 + +/* Phy Specific status fields */ +#define S17_STATUS_LINK_MASK 0xC000 +#define S17_STATUS_LINK_SHIFT 14 +#define S17_STATUS_FULL_DEPLEX 0x2000 +#define S17_STATUS_LINK_PASS 0x0400 +#define S17_STATUS_RESOLVED 0x0800 +#define S17_STATUS_LINK_10M 0 +#define S17_STATUS_LINK_100M 1 +#define S17_STATUS_LINK_1000M 2 + +#define S17_GLOBAL_INT_PHYMASK (1 << 15) + +#define S17_PHY_LINK_UP 0x400 +#define S17_PHY_LINK_DOWN 0x800 +#define S17_PHY_LINK_DUPLEX_CHANGE 0x2000 +#define S17_PHY_LINK_SPEED_CHANGE 0x4000 + +/* For Port flow control registers */ +#define S17_PORT_FLCTL_XON_DEFAULT (0x3a << 16) +#define S17_PORT_FLCTL_XOFF_DEFAULT (0x4a) + +/* Module enable Register */ +#define S17_MODULE_L3_EN (1 << 2) +#define S17_MODULE_ACL_EN (1 << 1) +#define S17_MODULE_MIB_EN (1 << 0) + +/* MIB Function Register 1 */ +#define S17_MIB_FUNC_ALL (3 << 24) +#define S17_MIB_CPU_KEEP (1 << 20) +#define S17_MIB_BUSY (1 << 17) +#define S17_MIB_AT_HALF_EN (1 << 16) +#define S17_MIB_TIMER_DEFAULT 0x100 + +#define S17_MAC_MAX 7 + +/* MAC power selector bit definitions */ +#define S17_RGMII0_1_8V (1 << 19) +#define S17_RGMII1_1_8V (1 << 18) + +/* SGMII_CTRL bit definitions */ +#define S17c_SGMII_EN_LCKDT (1 << 0) +#define S17c_SGMII_EN_PLL (1 << 1) +#define S17c_SGMII_EN_RX (1 << 2) +#define S17c_SGMII_EN_TX (1 << 3) +#define S17c_SGMII_EN_SD (1 << 4) +#define S17c_SGMII_BW_HIGH (1 << 6) +#define S17c_SGMII_SEL_CLK125M (1 << 7) +#define S17c_SGMII_TXDR_CTRL_600mV (1 << 10) +#define S17c_SGMII_CDR_BW_8 (3 << 13) +#define S17c_SGMII_DIS_AUTO_LPI_25M (1 << 16) +#define S17c_SGMII_MODE_CTRL_SGMII_PHY (1 << 22) +#define S17c_SGMII_PAUSE_SG_TX_EN_25M (1 << 24) +#define S17c_SGMII_ASYM_PAUSE_25M (1 << 25) +#define S17c_SGMII_PAUSE_25M (1 << 26) +#define S17c_SGMII_HALF_DUPLEX_25M (1 << 30) +#define S17c_SGMII_FULL_DUPLEX_25M (1 << 31) + +#ifndef BOOL +#define BOOL int +#endif + +/*add feature define here*/ + +#ifdef CONFIG_AR7242_S17_PHY +#undef HEADER_REG_CONF +#undef HEADER_EN +#endif + +#define LINK_UP 0x400 +#define LINK(_data) (_data & LINK_UP)? "Up" : "Down" +#define DUPLEX(_data) (_data & 0x2000)?\ + "Full duplex" : "Half duplex" +#define SPEED(_data) ((_data & 0xC000) >> 12) +#define SPEED_1000M (1 << 3) +#define SPEED_100M (1 << 2) + +#define S17C_MAX_PORT 4 +typedef struct { + u32 mac_pwr; + int port_count; + int chip_detect; + u32 port_phy_address[S17C_MAX_PORT]; + bool update; + bool skip_vlan; + u32 pad0_mode; + u32 pad5_mode; + u32 pad6_mode; + u32 port0; + u32 sgmii_ctrl; + u32 port0_status; + u32 port6_status; +} ipq_s17c_swt_cfg_t; + +#endif + diff --git a/sources/uboot-be550/drivers/net/ipq_common/construct/conf_rtl8261n_c.c b/sources/uboot-be550/drivers/net/ipq_common/construct/conf_rtl8261n_c.c new file mode 100644 index 00000000..702250d8 --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq_common/construct/conf_rtl8261n_c.c @@ -0,0 +1,1900 @@ +/* + * SPDX-License-Identifier: GPL-2.0-only + * + * Copyright (c) 2023 Realtek Semiconductor Corp. All rights reserved. + */ +//Date: Fri Aug 18 14:15:49 2023 + +rtk_hwpatch_t rtl8261n_c_top_conf[17] = { + {RTK_PATCH_OP_TOP , 0xf , 2 , 20 , 15, 0 , 0x5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 2 , 21 , 15, 0 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 2 , 22 , 15, 0 , 0x280 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 2 , 23 , 15, 0 , 0x0014, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 3 , 16 , 15, 0 , 0x0300, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 3 , 17 , 15, 0 , 0x01ff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 3 , 18 , 15, 0 , 0x000c, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 3 , 19 , 15, 0 , 0x01ff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 3 , 20 , 15, 0 , 0x0200, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 3 , 21 , 15, 0 , 0x0015, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 3 , 22 , 15, 0 , 0x0200, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 3 , 23 , 15, 0 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 4 , 16 , 15, 0 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 13 , 23 , 8 , 5 , 0x6 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 90 , 18 , 15, 0 , 0x11 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 90 , 19 , 15, 0 , 0x11 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 90 , 20 , 15, 8 , 0x01 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, +}; + +rtk_hwpatch_t rtl8261n_c_sds_conf[103] = { + {RTK_PATCH_OP_TOP , 0xf , 24 , 18 , 15, 0 , 0x881F, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 24 , 19 , 15, 0 , 0x003F, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 24 , 20 , 15, 0 , 0x003F, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 24 , 21 , 15, 0 , 0x003F, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 24 , 22 , 15, 0 , 0x001F, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x06 , 0x0D , 15, 0 , 0x0F00, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x06 , 0x0E , 15, 0 , 0x3F5A, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x07 , 0x10 , 15, 12, 0x8 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x07 , 0x10 , 7 , 0 , 0x3 , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x06 , 0x1D , 15, 0 , 0x0600, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x21 , 0x00 , 15, 0 , 0x4902, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x21 , 0x08 , 15, 0 , 0x0FC0, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x21 , 0x09 , 15, 0 , 0x33F0, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x21 , 0x0C , 15, 0 , 0x08BF, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x21 , 0x12 , 15, 0 , 0x8000, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x36 , 0x07 , 15, 0 , 0x04C0, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x36 , 0x08 , 15, 0 , 0x2000, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2E , 0x0B , 15, 0 , 0x2390, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2E , 0x0C , 15, 0 , 0xAA17, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2E , 0x0D , 15, 0 , 0xFE40, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2E , 0x0E , 15, 0 , 0x12F4, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2E , 0x11 , 15, 0 , 0xF2AD, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2E , 0x15 , 15, 0 , 0x7A41, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2E , 0x16 , 15, 0 , 0x0041, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2F , 0x00 , 15, 0 , 0x1F00, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2F , 0x01 , 15, 0 , 0x2800, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2F , 0x02 , 15, 0 , 0x0FC8, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2F , 0x11 , 15, 0 , 0x3000, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2F , 0x13 , 15, 0 , 0xF400, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2F , 0x1E , 15, 0 , 0x0500, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x34 , 0x0B , 15, 0 , 0x2390, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x34 , 0x0C , 15, 0 , 0xA517, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x34 , 0x0D , 15, 0 , 0xFE41, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x34 , 0x0E , 15, 0 , 0x12F4, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x34 , 0x11 , 15, 0 , 0xF2AD, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x34 , 0x15 , 15, 0 , 0x7A41, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x34 , 0x16 , 15, 0 , 0x0041, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x35 , 0x00 , 15, 0 , 0x1F80, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x35 , 0x01 , 15, 0 , 0x0800, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x35 , 0x02 , 15, 0 , 0x0FC8, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x35 , 0x11 , 15, 0 , 0x3001, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x35 , 0x13 , 15, 0 , 0xF400, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x35 , 0x1E , 15, 0 , 0x0100, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2C , 0x0B , 15, 0 , 0x2390, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2C , 0x0C , 15, 0 , 0xA517, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2C , 0x0D , 15, 0 , 0xFE41, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2C , 0x0E , 15, 0 , 0x12F4, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2C , 0x11 , 15, 0 , 0xF2AD, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2C , 0x15 , 15, 0 , 0x7A61, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2C , 0x16 , 15, 0 , 0x0041, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2D , 0x00 , 15, 0 , 0x1F80, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2D , 0x01 , 15, 0 , 0x0800, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2D , 0x02 , 15, 0 , 0x0FC8, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2D , 0x11 , 15, 0 , 0x3001, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2D , 0x13 , 15, 0 , 0xF400, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2D , 0x1E , 15, 0 , 0x0100, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x28 , 0x0B , 15, 0 , 0x2390, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x28 , 0x0C , 15, 0 , 0xA514, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x28 , 0x0D , 15, 0 , 0xFE43, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x28 , 0x0E , 15, 0 , 0x12F4, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x28 , 0x11 , 15, 0 , 0xF2AD, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x28 , 0x15 , 15, 0 , 0x7A61, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x28 , 0x16 , 15, 0 , 0x0041, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x29 , 0x00 , 15, 0 , 0x1F80, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x29 , 0x01 , 15, 0 , 0x0800, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x29 , 0x02 , 15, 0 , 0x0FC8, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x29 , 0x11 , 15, 0 , 0x3001, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x29 , 0x13 , 15, 0 , 0xF400, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x29 , 0x1E , 15, 0 , 0x0100, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x26 , 0x0B , 15, 0 , 0x2390, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x26 , 0x0C , 15, 0 , 0xA514, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x26 , 0x0D , 15, 0 , 0xFE43, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x26 , 0x0E , 15, 0 , 0x12F4, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x26 , 0x11 , 15, 0 , 0xF2AD, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x26 , 0x15 , 15, 0 , 0x7A41, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x26 , 0x16 , 15, 0 , 0x0041, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x27 , 0x00 , 15, 0 , 0x1F80, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x27 , 0x01 , 15, 0 , 0x0800, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x27 , 0x02 , 15, 0 , 0x0FC8, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x27 , 0x11 , 15, 0 , 0x3001, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x27 , 0x13 , 15, 0 , 0xF400, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x27 , 0x1E , 15, 0 , 0x0100, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x24 , 0x0B , 15, 0 , 0x2390, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x24 , 0x0C , 15, 0 , 0xA514, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x24 , 0x0D , 15, 0 , 0xFE43, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x24 , 0x0E , 15, 0 , 0x12F4, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x24 , 0x11 , 15, 0 , 0xF2AD, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x24 , 0x15 , 15, 0 , 0x7A41, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x24 , 0x16 , 15, 0 , 0x0041, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x25 , 0x00 , 15, 0 , 0x1F80, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x25 , 0x01 , 15, 0 , 0x0800, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x25 , 0x02 , 15, 0 , 0x0FC8, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x25 , 0x11 , 15, 0 , 0x3001, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x25 , 0x13 , 15, 0 , 0xF400, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x25 , 0x1E , 15, 0 , 0x0100, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 24 , 18 , 15, 0 , 0x880D, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 24 , 19 , 15, 0 , 0x0024, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 24 , 20 , 15, 0 , 0x0036, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 24 , 21 , 15, 0 , 0x0035, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 24 , 22 , 15, 0 , 0x001A, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x1F , 0x00 , 15, 0 , 0x001B, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x1F , 0x00 , 15, 0 , 0x0000, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 90 , 20 , 7 , 0 , 0x01 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, +}; + +rtk_hwpatch_t rtl8261n_c_afe_conf[2] = { + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbf1a, 3 , 2 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 90 , 21 , 15, 8 , 0x01 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, +}; + +rtk_hwpatch_t rtl8261n_c_uc_conf[10] = { + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb820, 7 , 7 , 0x0 , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbd8a, 5 , 3 , 0x3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbd8c, 6 , 4 , 0x5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8060, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 12, 10, 0x3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8061, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 13, 0x5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa466, 1 , 1 , 0x1 , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8491, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x3D , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, +}; + +rtk_hwpatch_t rtl8261n_c_uc2_conf[282] = { + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb820, 7 , 7 , 0x1 , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb87c, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8af6, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb87e, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xaf8b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8af6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0eaf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8af8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8b41, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8afa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xaf8b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8afc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4faf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8afe}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8b5b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b00}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xaf8b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b02}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xb4af, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b04}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8bc0, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b06}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xaf8b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b08}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xdaaf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b0a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8c2d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b0c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf8ef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b0e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x49f8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b10}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf70, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b12}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3f02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b14}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6772, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b16}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xad28, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b18}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13e1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b1a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8a55, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b1c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xad28, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b1e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0502, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b20}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5ee2, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b22}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xae0e, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b24}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x025d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b26}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8f02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b28}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8c2d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b2a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xae06, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b2c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x025d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b2e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x7002, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b30}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8c75, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b32}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe087, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b34}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1ef6, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b36}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x27e4, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b38}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x871e, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b3a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xfcef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b3c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x94fc, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b3e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x04a1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b40}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0103, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b42}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x028c, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b44}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x51e0, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b46}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8a09, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b48}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xef23, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b4a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xaf5e, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b4c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5bac, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b4e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5003, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b50}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xaf62, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b52}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8a02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b54}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8c75, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b56}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xaf62, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b58}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xb0bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b5a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x68e0, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b5c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0267, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b5e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x72ef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b60}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x31bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b62}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x68dd, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b64}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0267, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b66}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x721e, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b68}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x31ac, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b6a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3819, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b6c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf68, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b6e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe902, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b70}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6772, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b72}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xef31, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b74}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf68, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b76}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe602, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b78}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6772, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b7a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1e31, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b7c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xac38, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b7e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0cee, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b80}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8933, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b82}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x02ae, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b84}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0aee, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b86}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8933, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b88}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x00ae, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b8a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x04ee, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b8c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8933, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b8e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x01bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b90}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8ff9, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b92}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe189, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b94}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x331a, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b96}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x91db, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b98}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf69, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b9a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4c02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b9c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6772, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b9e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1f00, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ba0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1f22, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ba2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1b45, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ba4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xad27, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ba6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x05e1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ba8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x870d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8baa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xae03, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bac}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe187, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bae}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0eaf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bb0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2d1a, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bb2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0248, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bb4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf702, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bb6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8c99, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bb8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0222, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bba}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4faf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bbc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4176, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bbe}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf8c, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bc0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe302, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bc2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x70eb, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bc4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf8c, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bc6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf202, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bc8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x70eb, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bca}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf8c, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bcc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf802, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bce}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x70eb, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bd0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd300, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bd2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0241, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bd4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x7caf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bd6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x46b2, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bd8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf69, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bda}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x7f02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bdc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6772, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bde}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe58f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8be0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf8d0, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8be2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x00d1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8be4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x00bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8be6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x697f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8be8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0267, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bea}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x53bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bec}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6f0a, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bee}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0270, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bf0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xebbf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bf2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6f0a, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bf4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0270, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bf6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf4d6, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bf8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bfa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bfc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0d02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bfe}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x70f4, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c00}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c02}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0d02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c04}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x70eb, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c06}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa600, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c08}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x7f07, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c0a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd001, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c0c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe489, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c0e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xfeae, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c10}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0cbf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c12}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6f52, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c14}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0267, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c16}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x72ad, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c18}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2803, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c1a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x16ae, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c1c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xddd0, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c1e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x00e1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c20}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8ff8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c22}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf69, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c24}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x7f02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c26}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6753, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c28}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xaf53, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c2a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa2f8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c2c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xef49, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c2e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf8bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c30}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6f3a, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c32}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0267, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c34}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x72ac, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c36}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2812, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c38}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c3a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6302, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c3c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6772, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c3e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe58f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c40}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xfcbf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c42}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6d6f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c44}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0267, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c46}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x72e5, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c48}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8ffd, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c4a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xfcef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c4c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x94fc, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c4e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x04f8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c50}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xef49, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c52}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf8bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c54}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6f3a, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c56}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0267, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c58}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x72ac, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c5a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2812, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c5c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe18f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c5e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xfebf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c60}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6d63, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c62}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0267, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c64}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x53e1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c66}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8fff, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c68}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c6a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6f02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c6c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6753, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c6e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xfcef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c70}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x94fc, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c72}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x04f8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c74}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xef49, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c76}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf8bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c78}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6f3a, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c7a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0267, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c7c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x72ac, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c7e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2812, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c80}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe18f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c82}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xfcbf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c84}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6d63, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c86}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0267, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c88}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x53e1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c8a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8ffd, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c8c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c8e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6f02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c90}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6753, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c92}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xfcef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c94}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x94fc, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c96}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x04f8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c98}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xfaef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c9a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x69bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c9c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6f3a, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c9e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0267, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ca0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x72ad, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ca2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x280e, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ca4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf8c, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ca6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe602, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ca8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x70f4, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8caa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf8c, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cac}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe302, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cae}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x70f4, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cb0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xae2a, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cb2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd10f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cb4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf8c, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cb6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe902, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cb8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6753, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cba}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf8c, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cbc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xec02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cbe}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x70eb, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cc0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd100, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cc2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf8c, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cc4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xef02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cc6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6753, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cc8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf8c, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cca}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf202, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ccc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x70f4, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cce}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd100, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cd0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf8c, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cd2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf502, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cd4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6753, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cd6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf8c, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cd8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf802, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cda}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x70f4, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cdc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xef96, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cde}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xfefc, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ce0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0477, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ce2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbd6c, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ce4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x66bd, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ce6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6c30, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ce8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbd54, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cea}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x44bd, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cec}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5485, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cee}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbd5e, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cf0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x55bd, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cf2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x54a7, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cf4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbd5c, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cf6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbbbd, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cf8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5c00, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cfa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb85e, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x62ba, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb860, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5e56, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb862, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6287, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb864, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2d07, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb886, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4170, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb888, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x46ad, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb88a, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5370, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb88c, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb838, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x007f, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb820, 7 , 7 , 0x0 , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, +}; + +rtk_hwpatch_t rtl8261n_c_nctl0_conf[60] = { + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb820, 7 , 7 , 0x1 , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA016, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA012, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA014, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8010, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x801a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8023, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8023, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8023, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8023, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8023, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8023, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd719, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3bb7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8014, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd704, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x406e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x12db, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1301, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2a69, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8020, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9f01, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0d45, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf01, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0d43, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA026, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA024, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA022, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA020, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA006, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA004, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA002, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd42 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA000, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x12d7, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA008, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0300, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb820, 7 , 7 , 0x0 , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, +}; + +rtk_hwpatch_t rtl8261n_c_nctl1_conf[72] = { + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb820, 7 , 7 , 0x1 , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA016, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0010, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA012, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA014, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8010, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x801f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x802f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x802f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x802f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x802f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x802f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x802f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x38c1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8019, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd73e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6122, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0241, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x801d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd501, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce01, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa50f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd500, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x02e7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x38c1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8029, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd73e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6142, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0288, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8a0f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x802d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd501, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce01, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa50f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd500, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x00d3, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA08E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA08C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA08A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA088, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA086, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA084, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA082, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x00ce, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA080, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x02e3, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA090, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0003, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb820, 7 , 7 , 0x0 , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, +}; + +rtk_hwpatch_t rtl8261n_c_nctl2_conf[878] = { + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb820, 7 , 7 , 0x1 , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA016, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0020, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA012, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA014, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8010, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8029, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8217, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x82d0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x82f9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8322, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8336, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8336, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcb0a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0cc7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4127, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c0f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b05, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c38, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0d28, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf008, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c0f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b0a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c38, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0d18, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0f73, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8034, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8031, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1bf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd06d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x30}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1dd, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x31}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd06d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x32}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x33}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x34}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd06e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x35}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x36}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x37}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x38}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5fba, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x39}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd05a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x60cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x60f1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6113, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6135, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x40}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6157, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x41}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x42}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x43}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x44}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x45}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf008, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x46}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x47}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x48}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x49}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf004, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf002, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x142d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x50}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x51}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0ccf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x52}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b40, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x53}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c3f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x54}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c24, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x55}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x56}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa340, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x57}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x58}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x147c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x59}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa110, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1435, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8110, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1485, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa304, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x60}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa8c0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x61}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8810, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x62}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x63}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x64}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa310, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x65}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0cfc, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x66}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0224, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x67}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0ca0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x68}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0480, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x69}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa340, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd162, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x70}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x71}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x72}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5fba, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x73}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8840, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x74}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1c4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x75}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd045, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x76}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x77}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x78}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x79}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5fba, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6127, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f3b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x88c0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x800a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x80}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x81}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8350, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x82}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x84a0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x83}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffb6, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x84}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xb920, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x85}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcd33, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x86}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x87}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x88}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x89}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x7fb4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9920, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6065, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f94, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x90}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffee, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x91}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xb820, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x92}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x93}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x94}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x95}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x7fa5, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x96}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9820, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x97}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x800a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x98}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x99}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x147c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa108, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1435, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8108, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1485, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa2fc, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa304, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8880, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0cc0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0440, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcd34, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0cc0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xaa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b80, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xab}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xac3f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xac}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c38, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xad}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0d08, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xae}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xaf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa810, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa480, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa604, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x80bb, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xba}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd19f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xbb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xbc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xbd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xbe}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xbf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x63f4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f7a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4368, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0cc0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b40, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8c3f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8d38, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xca}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xcb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xcc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xcd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x80d7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xce}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xcf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x80d4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1f4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1b7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1c6, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xda}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xdb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6074, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xdc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xdd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f7a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xde}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xdf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4056, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf004, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x61fc, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xfff9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xea}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4070, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xeb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xec}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x81a4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xed}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xee}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xef}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xae80, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x81a4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd05a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x60cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x60f1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6113, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6135, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xfa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6157, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xfb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xfc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xfd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xfe}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xff}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf008, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x100}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x101}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x102}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x103}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf004, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x104}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x105}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf002, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x106}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x107}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x108}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x142d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x109}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0ccf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b40, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c3f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c24, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x110}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa340, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x111}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x112}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x147c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x113}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa110, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x114}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x115}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1435, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x116}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8110, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x117}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x118}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1485, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x119}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa304, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa8c0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8810, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa310, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0cfc, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x120}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0224, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x121}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0ca0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x122}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0480, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x123}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8604, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x124}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcd35, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x125}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd162, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x126}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x127}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x128}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x129}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5fba, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8840, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1c4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd045, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x130}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x131}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5fba, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x132}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x133}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6127, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x134}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x135}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f3b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x136}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x88c0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x137}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x800a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x138}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x139}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8350, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x84a0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffb8, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbb80, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x140}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5fb4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x141}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xb920, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x142}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcd36, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x143}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x144}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x145}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x146}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x7fb4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x147}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9920, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x148}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9b80, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x149}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6065, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f94, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffe8, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xb820, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x150}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x151}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x152}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x153}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x7fa5, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x154}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9820, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x155}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x800a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x156}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x157}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x158}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x147c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x159}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa108, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1435, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8108, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1485, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa2fc, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x160}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa304, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x161}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8880, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x162}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0cc0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x163}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0440, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x164}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcd37, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x165}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x166}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x167}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0cc0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x168}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b80, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x169}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xac3f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c38, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0d08, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa810, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x170}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa480, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x171}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa604, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x172}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x173}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x174}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x817e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x175}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x176}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x817b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x177}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x178}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x179}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x180}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x181}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x182}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1463, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x183}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x184}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f7a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x185}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x186}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f28, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x187}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x188}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x189}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0cc0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b40, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8c3f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8d38, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x190}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x819a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x191}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x192}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8197, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x193}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x194}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x195}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x196}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x197}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x198}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x199}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd189, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1463, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f7a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f28, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c0f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b05, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x60cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1aa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x60f1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ab}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6113, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ac}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6135, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ad}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6157, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ae}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1af}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce08, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce08, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf008, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce08, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce08, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf004, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce08, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf002, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce08, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ba}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1bb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x142d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1bc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa180, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1bd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcd38, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1be}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1bf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x81d4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x81cc, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf013, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd100, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ca}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf010, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1cb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1cc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1cd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1b7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ce}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1cf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd100, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf008, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1da}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd13b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1db}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd055, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1dc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1dd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1de}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1df}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1463, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f7b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa302, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1463, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f7a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ea}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f28, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1eb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ec}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ed}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c3f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ee}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c12, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ef}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8206, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x81fe, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf013, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1fa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd100, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1fb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1fc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf010, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1fd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1fe}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ff}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x200}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x201}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x202}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd100, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x203}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd040, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x204}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf008, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x205}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x206}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x207}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x208}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x209}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd16b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1463, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x210}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x211}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f7a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x212}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x213}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f2a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x214}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x215}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x087a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x216}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x217}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x646d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x218}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x219}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8231, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8227, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x40c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x220}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd100, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x221}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x222}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf01a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x223}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x224}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x225}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf017, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x226}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x227}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x40c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x228}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x229}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd100, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf010, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x230}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x231}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x40c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x232}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x233}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x234}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x235}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x236}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x237}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x238}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x239}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1463, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x240}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x241}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f7a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x242}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x243}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f29, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x244}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x245}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x60cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x246}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x60f1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x247}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6113, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x248}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6135, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x249}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6157, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf008, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x250}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x251}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x252}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf004, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x253}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x254}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf002, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x255}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x256}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x257}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x142d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x258}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x259}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8bc0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c3f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c09, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa310, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x260}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa420, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x261}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcd3b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x262}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x263}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x65ad, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x264}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x43c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x265}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x266}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x267}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x827b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x268}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x269}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8273, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf024, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd15d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x270}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x271}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf021, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x272}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x273}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x274}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1c6, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x275}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x276}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf01c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x277}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd15d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x278}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x279}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf019, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf014, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x280}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x281}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf011, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x282}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x283}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x284}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x828e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x285}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x286}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x828b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x287}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1e5, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x288}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x289}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf009, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd191, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x290}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd16b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x291}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x292}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x293}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x294}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x295}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1463, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x296}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x297}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f7a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x298}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x299}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f2c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x40e7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c0f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b05, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c0f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b0a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcd3c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x644d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2aa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x43c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ab}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ac}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ad}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x82c1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ae}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2af}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x82b9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf019, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf016, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ba}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2bb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2bc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf011, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2bd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd13e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2be}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2bf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf009, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ca}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2cb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2cc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2cd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ce}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0956, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2cf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2969, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x82f5, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x82eb, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x82e1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x40c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2da}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd15c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2db}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2dc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf01a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2dd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2de}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2df}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf017, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x40c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd13e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf010, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ea}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2eb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x40c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ec}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ed}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ee}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ef}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x09a0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2969, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2fa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x831e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2fb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2fc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8314, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2fd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2fe}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x830a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ff}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x300}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x40c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x301}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x302}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x303}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd15d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x304}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x305}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf01a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x306}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x307}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x308}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf017, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x309}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x30a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x40c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x30b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x30c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x30d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd16b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x30e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x30f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf010, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x310}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x311}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x312}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x313}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x314}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x40c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x315}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x316}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x317}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x318}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x319}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x31a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x31b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x31c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x31d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1b7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x31e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x31f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x320}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0a39, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x321}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x322}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2969, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x323}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8332, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x324}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x325}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x832f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x326}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x327}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x832c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x328}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd18a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x329}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x32a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf009, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x32b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x32c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x32d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x32e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1c6, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x32f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x330}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x331}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1b7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x332}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x333}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x334}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0506, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x335}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA10E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA10C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA10A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x04f4, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA108, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0a12, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA106, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0979, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA104, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x089f, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA102, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0692, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA100, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0f60, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA110, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x003f, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA016, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0020, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA012, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1ff8, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA014, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b0e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ff8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b0e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ff9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b0e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ffa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ffb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ffc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ffd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ffe}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1fff}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA164, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0baa, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA166, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c19, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA168, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1293, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA16A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3fff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA16C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3fff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA16E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3fff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA170, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3fff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA172, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3fff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA162, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0007, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb820, 7 , 7 , 0x0 , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, +}; + +rtk_hwpatch_t rtl8261n_c_algxg_conf[80] = { + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8165, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x22 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8167, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x33 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x827E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x68 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8013, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x39 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8ffb, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x14 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8ff9, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x1e , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x82D9, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x20 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x82DA, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x816E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0xab , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8159, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x58 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x815A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x99 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8139, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x25 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8125, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x67 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8126, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x89 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x827D, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x4c , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8205, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x4d , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8FFA, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x78 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8159, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x58 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x815A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x99 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x815B, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x77 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x815C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0xfb , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8125, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x67 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8126, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x89 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8127, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x77 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8128, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0xf7 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x80DF, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x51 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x80E0, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x94 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x80F1, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x99 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x80F2, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x97 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x80F4, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0xF9 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x80F7, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x99 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x80F8, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x9A , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x80FA, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x39 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x817B, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x40 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x817C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0xCC , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8149, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x28 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x814A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0xE3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x816D, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0xAA , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x80F3, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x75 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x80F9, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x73 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, +}; + +rtk_hwpatch_t rtl8261n_c_alg_giga_conf[5] = { + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa836, 15, 15, 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa85c, 7 , 7 , 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa85c, 6 , 3 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8367, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x5d , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, +}; + +rtk_hwpatch_t rtl8261n_c_normal_conf[21] = { + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x817d, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x07 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb516, 6 , 0 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8ffe, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x04 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8fff, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x05 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8132, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x77 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8134, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x88 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x80ca, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x77 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x80cc, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x88 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8062, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x77 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8064, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x88 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x801E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0011, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, +}; + +rtk_hwpatch_t rtl8261n_c_dataram_conf[148] = { + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb820, 7 , 7 , 0x0 , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb896, 0 , 0 , 0x0 , RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb892, 15, 8 , 0x0 , RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC10B, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xD5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC10C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xD5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC10D, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xD5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC10E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xD5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC10F, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xD5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC110, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xD5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC149, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x08 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC14A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x08 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC14B, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x08 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC14C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x08 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC14D, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x08 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC14E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x08 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC166, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xEE , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC167, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xEE , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC168, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x07 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC169, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x09 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC16A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x0B , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC16B, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x0D , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC16C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x13 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC16D, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x0E , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC16E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x11 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC16F, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x14 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC170, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x17 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC171, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x15 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC172, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x10 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC173, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x0B , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC128, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xF7 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC129, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xF7 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC12A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xF8 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC12B, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xF7 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC12C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xF6 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC12D, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xF5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC12E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xF2 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC12F, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xF7 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC130, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xF5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC131, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xF2 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC132, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xF0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC133, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xF1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC134, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xF4 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC135, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xF7 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC118, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xEC , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC119, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xEB , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC11A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xEB , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC11B, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xE8 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC11C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xE8 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC11D, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xEA , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC11E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xE9 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC11F, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xE7 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC120, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xE6 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC121, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xE7 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC122, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xE6 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC123, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xEA , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC124, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xEB , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC125, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xED , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC126, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xE3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC127, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xE0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC156, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x19 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC157, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x1B , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC158, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x1B , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC159, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x1F , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC15A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x1E , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC15B, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x1C , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC15C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x1D , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC15D, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x20 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC15E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x22 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC15F, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x21 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC160, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x25 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC161, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x20 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC162, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x21 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC163, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x27 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC164, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x57 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC165, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x74 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb896, 0 , 0 , 0x1 , RTK_PATCH_CMP_W , 0, 0, 0, 0}, +}; + +rtk_hwpatch_t rtl8261n_c_rtct_conf[176] = { + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa468, 1 , 0 , 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa422, 0 , 0 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xc010, 9 , 9 , 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xc010, 10, 10, 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xc010, 14, 13, 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xc000, 0 , 0 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_DELAY_MS, 0 , 0 , 0 , 0 , 0 , 1000 , RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8260, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x25 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8270, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x8 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8271, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x1D , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8280, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x20 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8281, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8278, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x02 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8279, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8274, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x01 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8275, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x01 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8276, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8277, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x827C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x827D, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x04 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x827E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x827F, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x25 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x827A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x1F , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x827B, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x40 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8263, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x34 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8264, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xBC , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8261, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x32 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8262, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8265, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8273, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xE4 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8266, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x45 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8267, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xE0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8282, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8283, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x0b , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8284, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8285, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x1D , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8286, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xFF , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8287, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xFA , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8288, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8289, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x03 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x828A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x05 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x828B, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xE7 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x828C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xFF , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x828D, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x5F , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x828E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x828F, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x3E , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8290, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xFF , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8291, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xF4 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8292, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x06 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8293, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xF5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8294, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xFF , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8295, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x12 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8296, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8297, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x59 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8298, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xFF , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8299, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xF2 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x829A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xF8 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x829B, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xEA , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x829C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x829D, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x35 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x829E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xFF , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x829F, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xBE , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82A0, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82A1, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x36 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82A2, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xFA , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82A3, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x30 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82A4, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82A5, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x35 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82A6, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xFF , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82A7, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xBE , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82A8, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82A9, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x36 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82AA, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x06 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82AB, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x10 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82AC, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xFF , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82AD, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x98 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82AE, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82AF, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x10 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82B0, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82B1, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x06 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82B2, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x02 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82B3, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x60 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82B4, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82B5, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82B6, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82B7, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82B8, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82B9, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x826D, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x2B , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x826E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x03 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa422, 1 , 1 , 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa422, 7 , 4 , 0xf , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 90 , 21 , 7 , 0 , 0x3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, +}; + diff --git a/sources/uboot-be550/drivers/net/ipq_common/construct/conf_rtl8261n_c_lp.c b/sources/uboot-be550/drivers/net/ipq_common/construct/conf_rtl8261n_c_lp.c new file mode 100644 index 00000000..ef654477 --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq_common/construct/conf_rtl8261n_c_lp.c @@ -0,0 +1,2001 @@ +/* + * SPDX-License-Identifier: GPL-2.0-only + * + * Copyright (c) 2023 Realtek Semiconductor Corp. All rights reserved. + */ +//Date: Fri Aug 18 14:53:38 2023 + +rtk_hwpatch_t rtl8261n_c_top_conf[17] = { + {RTK_PATCH_OP_TOP , 0xf , 2 , 20 , 15, 0 , 0x5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 2 , 21 , 15, 0 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 2 , 22 , 15, 0 , 0x280 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 2 , 23 , 15, 0 , 0x0014, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 3 , 16 , 15, 0 , 0x0300, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 3 , 17 , 15, 0 , 0x01ff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 3 , 18 , 15, 0 , 0x000c, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 3 , 19 , 15, 0 , 0x01ff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 3 , 20 , 15, 0 , 0x0200, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 3 , 21 , 15, 0 , 0x0015, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 3 , 22 , 15, 0 , 0x0200, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 3 , 23 , 15, 0 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 4 , 16 , 15, 0 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 13 , 23 , 8 , 5 , 0x6 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 90 , 18 , 15, 0 , 0x11 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 90 , 19 , 15, 0 , 0x11 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 90 , 20 , 15, 8 , 0x01 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, +}; + +rtk_hwpatch_t rtl8261n_c_sds_conf[103] = { + {RTK_PATCH_OP_TOP , 0xf , 24 , 18 , 15, 0 , 0x881F, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 24 , 19 , 15, 0 , 0x003F, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 24 , 20 , 15, 0 , 0x003F, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 24 , 21 , 15, 0 , 0x003F, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 24 , 22 , 15, 0 , 0x001F, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x06 , 0x0D , 15, 0 , 0x0F00, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x06 , 0x0E , 15, 0 , 0x3F5A, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x07 , 0x10 , 15, 12, 0x8 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x07 , 0x10 , 7 , 0 , 0x3 , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x06 , 0x1D , 15, 0 , 0x0600, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x21 , 0x00 , 15, 0 , 0x4902, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x21 , 0x08 , 15, 0 , 0x0FC0, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x21 , 0x09 , 15, 0 , 0x33F0, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x21 , 0x0C , 15, 0 , 0x08BF, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x21 , 0x12 , 15, 0 , 0x8000, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x36 , 0x07 , 15, 0 , 0x04C0, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x36 , 0x08 , 15, 0 , 0x2000, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2E , 0x0B , 15, 0 , 0x2390, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2E , 0x0C , 15, 0 , 0xAA17, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2E , 0x0D , 15, 0 , 0xFE40, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2E , 0x0E , 15, 0 , 0x12F4, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2E , 0x11 , 15, 0 , 0xF2AD, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2E , 0x15 , 15, 0 , 0x7A41, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2E , 0x16 , 15, 0 , 0x0041, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2F , 0x00 , 15, 0 , 0x1F00, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2F , 0x01 , 15, 0 , 0x2800, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2F , 0x02 , 15, 0 , 0x0FC8, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2F , 0x11 , 15, 0 , 0x3000, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2F , 0x13 , 15, 0 , 0xF400, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2F , 0x1E , 15, 0 , 0x0500, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x34 , 0x0B , 15, 0 , 0x2390, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x34 , 0x0C , 15, 0 , 0xA517, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x34 , 0x0D , 15, 0 , 0xFE41, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x34 , 0x0E , 15, 0 , 0x12F4, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x34 , 0x11 , 15, 0 , 0xF2AD, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x34 , 0x15 , 15, 0 , 0x7A41, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x34 , 0x16 , 15, 0 , 0x0041, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x35 , 0x00 , 15, 0 , 0x1F80, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x35 , 0x01 , 15, 0 , 0x0800, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x35 , 0x02 , 15, 0 , 0x0FC8, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x35 , 0x11 , 15, 0 , 0x3001, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x35 , 0x13 , 15, 0 , 0xF400, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x35 , 0x1E , 15, 0 , 0x0100, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2C , 0x0B , 15, 0 , 0x2390, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2C , 0x0C , 15, 0 , 0xA517, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2C , 0x0D , 15, 0 , 0xFE41, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2C , 0x0E , 15, 0 , 0x12F4, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2C , 0x11 , 15, 0 , 0xF2AD, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2C , 0x15 , 15, 0 , 0x7A61, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2C , 0x16 , 15, 0 , 0x0041, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2D , 0x00 , 15, 0 , 0x1F80, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2D , 0x01 , 15, 0 , 0x0800, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2D , 0x02 , 15, 0 , 0x0FC8, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2D , 0x11 , 15, 0 , 0x3001, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2D , 0x13 , 15, 0 , 0xF400, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2D , 0x1E , 15, 0 , 0x0100, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x28 , 0x0B , 15, 0 , 0x2390, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x28 , 0x0C , 15, 0 , 0xA514, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x28 , 0x0D , 15, 0 , 0xFE43, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x28 , 0x0E , 15, 0 , 0x12F4, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x28 , 0x11 , 15, 0 , 0xF2AD, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x28 , 0x15 , 15, 0 , 0x7A61, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x28 , 0x16 , 15, 0 , 0x0041, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x29 , 0x00 , 15, 0 , 0x1F80, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x29 , 0x01 , 15, 0 , 0x0800, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x29 , 0x02 , 15, 0 , 0x0FC8, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x29 , 0x11 , 15, 0 , 0x3001, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x29 , 0x13 , 15, 0 , 0xF400, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x29 , 0x1E , 15, 0 , 0x0100, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x26 , 0x0B , 15, 0 , 0x2390, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x26 , 0x0C , 15, 0 , 0xA514, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x26 , 0x0D , 15, 0 , 0xFE43, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x26 , 0x0E , 15, 0 , 0x12F4, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x26 , 0x11 , 15, 0 , 0xF2AD, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x26 , 0x15 , 15, 0 , 0x7A41, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x26 , 0x16 , 15, 0 , 0x0041, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x27 , 0x00 , 15, 0 , 0x1F80, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x27 , 0x01 , 15, 0 , 0x0800, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x27 , 0x02 , 15, 0 , 0x0FC8, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x27 , 0x11 , 15, 0 , 0x3001, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x27 , 0x13 , 15, 0 , 0xF400, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x27 , 0x1E , 15, 0 , 0x0100, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x24 , 0x0B , 15, 0 , 0x2390, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x24 , 0x0C , 15, 0 , 0xA514, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x24 , 0x0D , 15, 0 , 0xFE43, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x24 , 0x0E , 15, 0 , 0x12F4, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x24 , 0x11 , 15, 0 , 0xF2AD, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x24 , 0x15 , 15, 0 , 0x7A41, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x24 , 0x16 , 15, 0 , 0x0041, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x25 , 0x00 , 15, 0 , 0x1F80, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x25 , 0x01 , 15, 0 , 0x0800, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x25 , 0x02 , 15, 0 , 0x0FC8, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x25 , 0x11 , 15, 0 , 0x3001, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x25 , 0x13 , 15, 0 , 0xF400, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x25 , 0x1E , 15, 0 , 0x0100, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 24 , 18 , 15, 0 , 0x880D, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 24 , 19 , 15, 0 , 0x0024, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 24 , 20 , 15, 0 , 0x0036, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 24 , 21 , 15, 0 , 0x0035, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 24 , 22 , 15, 0 , 0x001A, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x1F , 0x00 , 15, 0 , 0x001B, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x1F , 0x00 , 15, 0 , 0x0000, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 90 , 20 , 7 , 0 , 0x01 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, +}; + +rtk_hwpatch_t rtl8261n_c_afe_conf[31] = { + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbf1a, 3 , 2 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbfb0, 15, 13, 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbf9c, 15, 13, 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbfb0, 12, 10, 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbf9c, 12, 10, 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbfb0, 9 , 7 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbfb0, 6 , 4 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbfa0, 15, 13, 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbf14, 15, 13, 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbf14, 4 , 2 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbfb0, 1 , 0 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbf9c, 9 , 8 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbf9c, 7 , 6 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbf14, 12, 10, 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbf14, 9 , 7 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbf12, 5 , 3 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbf10, 2 , 0 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbf14, 1 , 0 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbf14, 6 , 5 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbf8e, 3 , 3 , 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbfa8, 2 , 2 , 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbfa8, 3 , 3 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbf1c, 4 , 4 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8061, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 10, 8 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbc3c, 15, 0 , 0x100 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbf18, 15, 13, 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbf18, 12, 11, 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbd5c, 6 , 4 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbd80, 15, 0 , 0x280 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 90 , 21 , 15, 8 , 0x02 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, +}; + +rtk_hwpatch_t rtl8261n_c_uc_conf[10] = { + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb820, 7 , 7 , 0x0 , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbd8a, 5 , 3 , 0x3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbd8c, 6 , 4 , 0x5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8060, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 12, 10, 0x3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8061, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 13, 0x5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa466, 1 , 1 , 0x1 , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8491, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x3D , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, +}; + +rtk_hwpatch_t rtl8261n_c_uc2_conf[282] = { + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb820, 7 , 7 , 0x1 , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb87c, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8af6, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb87e, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xaf8b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8af6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0eaf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8af8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8b41, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8afa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xaf8b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8afc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4faf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8afe}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8b5b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b00}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xaf8b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b02}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xb4af, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b04}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8bc0, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b06}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xaf8b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b08}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xdaaf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b0a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8c2d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b0c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf8ef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b0e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x49f8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b10}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf70, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b12}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3f02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b14}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6772, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b16}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xad28, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b18}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13e1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b1a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8a55, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b1c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xad28, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b1e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0502, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b20}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5ee2, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b22}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xae0e, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b24}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x025d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b26}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8f02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b28}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8c2d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b2a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xae06, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b2c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x025d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b2e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x7002, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b30}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8c75, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b32}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe087, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b34}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1ef6, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b36}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x27e4, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b38}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x871e, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b3a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xfcef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b3c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x94fc, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b3e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x04a1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b40}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0103, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b42}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x028c, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b44}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x51e0, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b46}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8a09, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b48}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xef23, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b4a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xaf5e, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b4c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5bac, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b4e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5003, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b50}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xaf62, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b52}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8a02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b54}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8c75, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b56}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xaf62, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b58}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xb0bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b5a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x68e0, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b5c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0267, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b5e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x72ef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b60}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x31bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b62}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x68dd, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b64}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0267, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b66}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x721e, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b68}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x31ac, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b6a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3819, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b6c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf68, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b6e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe902, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b70}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6772, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b72}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xef31, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b74}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf68, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b76}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe602, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b78}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6772, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b7a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1e31, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b7c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xac38, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b7e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0cee, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b80}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8933, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b82}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x02ae, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b84}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0aee, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b86}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8933, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b88}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x00ae, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b8a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x04ee, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b8c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8933, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b8e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x01bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b90}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8ff9, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b92}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe189, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b94}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x331a, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b96}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x91db, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b98}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf69, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b9a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4c02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b9c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6772, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b9e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1f00, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ba0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1f22, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ba2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1b45, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ba4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xad27, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ba6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x05e1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ba8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x870d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8baa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xae03, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bac}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe187, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bae}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0eaf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bb0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2d1a, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bb2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0248, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bb4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf702, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bb6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8c99, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bb8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0222, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bba}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4faf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bbc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4176, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bbe}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf8c, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bc0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe302, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bc2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x70eb, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bc4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf8c, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bc6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf202, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bc8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x70eb, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bca}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf8c, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bcc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf802, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bce}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x70eb, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bd0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd300, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bd2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0241, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bd4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x7caf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bd6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x46b2, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bd8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf69, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bda}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x7f02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bdc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6772, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bde}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe58f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8be0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf8d0, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8be2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x00d1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8be4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x00bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8be6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x697f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8be8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0267, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bea}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x53bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bec}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6f0a, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bee}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0270, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bf0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xebbf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bf2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6f0a, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bf4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0270, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bf6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf4d6, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bf8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bfa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bfc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0d02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bfe}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x70f4, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c00}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c02}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0d02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c04}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x70eb, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c06}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa600, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c08}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x7f07, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c0a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd001, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c0c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe489, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c0e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xfeae, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c10}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0cbf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c12}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6f52, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c14}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0267, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c16}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x72ad, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c18}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2803, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c1a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x16ae, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c1c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xddd0, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c1e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x00e1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c20}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8ff8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c22}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf69, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c24}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x7f02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c26}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6753, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c28}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xaf53, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c2a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa2f8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c2c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xef49, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c2e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf8bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c30}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6f3a, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c32}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0267, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c34}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x72ac, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c36}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2812, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c38}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c3a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6302, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c3c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6772, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c3e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe58f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c40}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xfcbf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c42}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6d6f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c44}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0267, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c46}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x72e5, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c48}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8ffd, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c4a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xfcef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c4c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x94fc, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c4e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x04f8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c50}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xef49, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c52}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf8bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c54}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6f3a, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c56}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0267, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c58}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x72ac, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c5a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2812, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c5c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe18f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c5e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xfebf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c60}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6d63, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c62}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0267, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c64}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x53e1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c66}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8fff, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c68}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c6a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6f02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c6c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6753, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c6e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xfcef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c70}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x94fc, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c72}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x04f8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c74}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xef49, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c76}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf8bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c78}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6f3a, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c7a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0267, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c7c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x72ac, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c7e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2812, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c80}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe18f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c82}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xfcbf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c84}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6d63, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c86}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0267, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c88}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x53e1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c8a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8ffd, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c8c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c8e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6f02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c90}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6753, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c92}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xfcef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c94}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x94fc, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c96}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x04f8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c98}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xfaef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c9a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x69bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c9c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6f3a, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c9e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0267, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ca0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x72ad, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ca2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x280e, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ca4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf8c, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ca6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe602, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ca8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x70f4, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8caa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf8c, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cac}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe302, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cae}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x70f4, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cb0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xae2a, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cb2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd10f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cb4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf8c, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cb6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe902, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cb8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6753, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cba}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf8c, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cbc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xec02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cbe}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x70eb, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cc0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd100, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cc2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf8c, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cc4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xef02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cc6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6753, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cc8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf8c, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cca}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf202, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ccc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x70f4, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cce}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd100, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cd0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf8c, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cd2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf502, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cd4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6753, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cd6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf8c, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cd8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf802, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cda}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x70f4, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cdc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xef96, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cde}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xfefc, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ce0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0477, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ce2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbd6c, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ce4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x66bd, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ce6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6c30, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ce8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbd54, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cea}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x44bd, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cec}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5485, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cee}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbd5e, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cf0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x55bd, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cf2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x54a7, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cf4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbd5c, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cf6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbbbd, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cf8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5c00, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cfa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb85e, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x62ba, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb860, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5e56, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb862, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6287, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb864, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2d07, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb886, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4170, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb888, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x46ad, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb88a, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5370, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb88c, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb838, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x007f, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb820, 7 , 7 , 0x0 , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, +}; + +rtk_hwpatch_t rtl8261n_c_nctl0_conf[60] = { + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb820, 7 , 7 , 0x1 , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA016, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA012, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA014, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8010, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x801a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8023, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8023, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8023, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8023, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8023, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8023, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd719, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3bb7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8014, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd704, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x406e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x12db, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1301, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2a69, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8020, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9f01, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0d45, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf01, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0d43, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA026, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA024, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA022, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA020, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA006, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA004, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA002, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd42 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA000, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x12d7, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA008, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0300, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb820, 7 , 7 , 0x0 , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, +}; + +rtk_hwpatch_t rtl8261n_c_nctl1_conf[72] = { + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb820, 7 , 7 , 0x1 , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA016, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0010, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA012, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA014, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8010, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x801f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x802f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x802f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x802f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x802f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x802f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x802f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x38c1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8019, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd73e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6122, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0241, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x801d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd501, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce01, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa50f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd500, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x02e7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x38c1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8029, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd73e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6142, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0288, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8a0f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x802d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd501, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce01, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa50f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd500, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x00d3, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA08E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA08C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA08A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA088, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA086, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA084, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA082, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x00ce, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA080, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x02e3, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA090, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0003, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb820, 7 , 7 , 0x0 , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, +}; + +rtk_hwpatch_t rtl8261n_c_nctl2_conf[878] = { + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb820, 7 , 7 , 0x1 , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA016, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0020, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA012, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA014, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8010, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8029, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8217, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x82d0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x82f9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8322, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8336, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8336, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcb0a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0cc7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4127, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c0f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b05, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c38, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0d28, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf008, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c0f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b0a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c38, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0d18, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0f73, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8034, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8031, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1bf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd06d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x30}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1dd, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x31}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd06d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x32}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x33}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x34}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd06e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x35}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x36}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x37}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x38}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5fba, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x39}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd05a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x60cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x60f1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6113, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6135, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x40}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6157, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x41}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x42}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x43}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x44}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x45}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf008, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x46}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x47}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x48}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x49}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf004, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf002, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x142d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x50}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x51}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0ccf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x52}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b40, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x53}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c3f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x54}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c24, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x55}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x56}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa340, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x57}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x58}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x147c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x59}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa110, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1435, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8110, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1485, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa304, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x60}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa8c0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x61}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8810, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x62}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x63}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x64}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa310, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x65}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0cfc, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x66}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0224, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x67}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0ca0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x68}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0480, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x69}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa340, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd162, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x70}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x71}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x72}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5fba, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x73}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8840, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x74}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1c4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x75}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd045, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x76}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x77}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x78}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x79}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5fba, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6127, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f3b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x88c0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x800a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x80}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x81}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8350, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x82}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x84a0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x83}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffb6, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x84}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xb920, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x85}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcd33, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x86}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x87}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x88}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x89}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x7fb4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9920, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6065, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f94, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x90}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffee, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x91}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xb820, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x92}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x93}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x94}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x95}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x7fa5, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x96}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9820, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x97}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x800a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x98}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x99}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x147c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa108, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1435, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8108, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1485, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa2fc, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa304, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8880, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0cc0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0440, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcd34, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0cc0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xaa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b80, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xab}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xac3f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xac}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c38, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xad}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0d08, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xae}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xaf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa810, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa480, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa604, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x80bb, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xba}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd19f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xbb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xbc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xbd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xbe}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xbf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x63f4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f7a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4368, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0cc0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b40, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8c3f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8d38, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xca}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xcb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xcc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xcd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x80d7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xce}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xcf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x80d4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1f4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1b7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1c6, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xda}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xdb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6074, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xdc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xdd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f7a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xde}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xdf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4056, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf004, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x61fc, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xfff9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xea}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4070, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xeb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xec}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x81a4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xed}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xee}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xef}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xae80, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x81a4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd05a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x60cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x60f1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6113, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6135, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xfa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6157, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xfb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xfc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xfd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xfe}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xff}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf008, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x100}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x101}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x102}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x103}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf004, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x104}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x105}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf002, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x106}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x107}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x108}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x142d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x109}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0ccf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b40, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c3f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c24, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x110}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa340, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x111}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x112}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x147c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x113}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa110, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x114}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x115}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1435, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x116}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8110, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x117}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x118}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1485, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x119}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa304, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa8c0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8810, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa310, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0cfc, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x120}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0224, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x121}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0ca0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x122}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0480, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x123}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8604, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x124}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcd35, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x125}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd162, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x126}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x127}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x128}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x129}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5fba, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8840, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1c4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd045, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x130}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x131}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5fba, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x132}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x133}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6127, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x134}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x135}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f3b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x136}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x88c0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x137}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x800a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x138}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x139}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8350, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x84a0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffb8, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbb80, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x140}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5fb4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x141}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xb920, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x142}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcd36, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x143}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x144}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x145}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x146}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x7fb4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x147}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9920, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x148}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9b80, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x149}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6065, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f94, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffe8, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xb820, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x150}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x151}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x152}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x153}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x7fa5, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x154}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9820, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x155}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x800a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x156}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x157}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x158}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x147c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x159}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa108, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1435, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8108, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1485, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa2fc, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x160}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa304, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x161}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8880, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x162}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0cc0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x163}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0440, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x164}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcd37, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x165}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x166}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x167}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0cc0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x168}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b80, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x169}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xac3f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c38, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0d08, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa810, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x170}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa480, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x171}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa604, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x172}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x173}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x174}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x817e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x175}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x176}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x817b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x177}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x178}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x179}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x180}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x181}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x182}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1463, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x183}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x184}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f7a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x185}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x186}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f28, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x187}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x188}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x189}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0cc0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b40, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8c3f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8d38, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x190}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x819a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x191}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x192}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8197, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x193}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x194}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x195}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x196}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x197}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x198}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x199}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd189, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1463, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f7a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f28, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c0f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b05, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x60cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1aa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x60f1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ab}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6113, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ac}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6135, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ad}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6157, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ae}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1af}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce08, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce08, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf008, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce08, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce08, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf004, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce08, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf002, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce08, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ba}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1bb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x142d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1bc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa180, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1bd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcd38, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1be}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1bf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x81d4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x81cc, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf013, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd100, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ca}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf010, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1cb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1cc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1cd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1b7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ce}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1cf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd100, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf008, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1da}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd13b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1db}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd055, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1dc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1dd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1de}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1df}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1463, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f7b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa302, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1463, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f7a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ea}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f28, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1eb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ec}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ed}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c3f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ee}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c12, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ef}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8206, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x81fe, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf013, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1fa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd100, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1fb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1fc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf010, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1fd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1fe}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ff}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x200}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x201}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x202}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd100, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x203}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd040, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x204}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf008, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x205}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x206}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x207}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x208}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x209}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd16b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1463, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x210}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x211}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f7a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x212}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x213}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f2a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x214}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x215}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x087a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x216}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x217}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x646d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x218}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x219}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8231, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8227, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x40c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x220}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd100, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x221}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x222}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf01a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x223}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x224}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x225}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf017, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x226}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x227}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x40c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x228}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x229}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd100, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf010, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x230}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x231}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x40c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x232}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x233}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x234}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x235}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x236}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x237}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x238}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x239}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1463, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x240}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x241}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f7a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x242}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x243}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f29, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x244}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x245}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x60cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x246}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x60f1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x247}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6113, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x248}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6135, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x249}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6157, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf008, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x250}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x251}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x252}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf004, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x253}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x254}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf002, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x255}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x256}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x257}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x142d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x258}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x259}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8bc0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c3f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c09, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa310, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x260}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa420, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x261}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcd3b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x262}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x263}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x65ad, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x264}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x43c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x265}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x266}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x267}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x827b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x268}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x269}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8273, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf024, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd15d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x270}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x271}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf021, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x272}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x273}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x274}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1c6, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x275}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x276}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf01c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x277}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd15d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x278}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x279}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf019, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf014, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x280}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x281}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf011, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x282}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x283}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x284}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x828e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x285}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x286}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x828b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x287}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1e5, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x288}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x289}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf009, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd191, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x290}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd16b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x291}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x292}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x293}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x294}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x295}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1463, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x296}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x297}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f7a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x298}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x299}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f2c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x40e7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c0f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b05, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c0f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b0a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcd3c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x644d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2aa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x43c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ab}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ac}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ad}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x82c1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ae}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2af}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x82b9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf019, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf016, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ba}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2bb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2bc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf011, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2bd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd13e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2be}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2bf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf009, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ca}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2cb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2cc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2cd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ce}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0956, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2cf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2969, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x82f5, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x82eb, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x82e1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x40c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2da}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd15c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2db}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2dc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf01a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2dd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2de}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2df}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf017, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x40c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd13e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf010, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ea}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2eb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x40c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ec}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ed}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ee}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ef}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x09a0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2969, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2fa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x831e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2fb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2fc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8314, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2fd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2fe}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x830a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ff}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x300}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x40c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x301}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x302}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x303}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd15d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x304}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x305}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf01a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x306}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x307}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x308}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf017, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x309}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x30a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x40c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x30b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x30c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x30d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd16b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x30e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x30f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf010, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x310}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x311}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x312}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x313}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x314}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x40c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x315}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x316}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x317}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x318}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x319}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x31a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x31b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x31c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x31d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1b7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x31e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x31f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x320}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0a39, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x321}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x322}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2969, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x323}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8332, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x324}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x325}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x832f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x326}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x327}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x832c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x328}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd18a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x329}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x32a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf009, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x32b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x32c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x32d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x32e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1c6, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x32f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x330}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x331}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1b7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x332}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x333}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x334}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0506, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x335}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA10E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA10C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA10A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x04f4, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA108, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0a12, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA106, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0979, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA104, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x089f, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA102, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0692, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA100, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0f60, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA110, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x003f, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA016, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0020, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA012, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1ff8, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA014, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b0e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ff8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b0e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ff9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b0e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ffa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ffb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ffc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ffd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ffe}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1fff}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA164, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0baa, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA166, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c19, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA168, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1293, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA16A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3fff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA16C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3fff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA16E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3fff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA170, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3fff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA172, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3fff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA162, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0007, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb820, 7 , 7 , 0x0 , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, +}; + +rtk_hwpatch_t rtl8261n_c_algxg_conf[80] = { + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8165, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x22 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8167, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x33 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x827E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x68 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8013, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x39 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8ffb, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x14 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8ff9, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x1e , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x82D9, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x20 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x82DA, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x816E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0xab , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8159, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x58 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x815A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x99 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8139, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x25 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8125, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x67 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8126, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x89 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x827D, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x4c , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8205, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x4d , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8FFA, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x78 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8159, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x58 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x815A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x99 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x815B, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x77 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x815C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0xfb , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8125, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x67 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8126, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x89 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8127, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x77 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8128, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0xf7 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x80DF, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x51 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x80E0, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x94 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x80F1, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x99 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x80F2, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x97 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x80F4, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0xF9 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x80F7, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x99 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x80F8, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x9A , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x80FA, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x39 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x817B, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x40 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x817C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0xCC , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8149, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x28 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x814A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0xE3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x816D, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0xAA , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x80F3, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x75 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x80F9, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x73 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, +}; + +rtk_hwpatch_t rtl8261n_c_alg_giga_conf[5] = { + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa836, 15, 15, 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa85c, 7 , 7 , 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa85c, 6 , 3 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8367, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x5d , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, +}; + +rtk_hwpatch_t rtl8261n_c_normal_conf[93] = { + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x817d, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x07 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb516, 6 , 0 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8ffe, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x04 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8fff, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x05 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8132, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x77 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8134, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x88 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x80ca, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x77 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x80cc, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x88 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8062, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x77 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8064, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x88 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x801E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0011, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xac1c, 8 , 7 , 0x3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xac1e, 13, 12, 0x3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xad96, 7 , 6 , 0x3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xad96, 5 , 4 , 0x3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xad96, 3 , 2 , 0x3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xad96, 1 , 0 , 0x3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xad98, 3 , 2 , 0x3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xad98, 1 , 0 , 0x3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xae38, 3 , 2 , 0x3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xae38, 1 , 0 , 0x3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb00a, 14, 14, 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb006, 13, 12, 0x3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb00a, 10, 10, 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb00a, 9 , 9 , 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb00a, 8 , 8 , 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb008, 13, 12, 0x3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb008, 9 , 8 , 0x3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb008, 5 , 4 , 0x3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb00a, 6 , 6 , 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb00a, 4 , 4 , 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb00a, 2 , 2 , 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb10a, 14, 14, 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb106, 13, 12, 0x3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb10a, 10, 10, 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb10a, 9 , 9 , 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb10a, 8 , 8 , 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb108, 13, 12, 0x3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb108, 9 , 8 , 0x3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb108, 5 , 4 , 0x3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb10a, 6 , 6 , 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb10a, 4 , 4 , 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb10a, 2 , 2 , 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb20a, 14, 14, 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb206, 13, 12, 0x3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb20a, 10, 10, 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb20a, 9 , 9 , 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb20a, 8 , 8 , 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb208, 13, 12, 0x3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb208, 9 , 8 , 0x3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb208, 5 , 4 , 0x3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb20a, 6 , 6 , 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb20a, 4 , 4 , 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb20a, 2 , 2 , 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb30a, 14, 14, 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb306, 13, 12, 0x3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb30a, 10, 10, 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb30a, 9 , 9 , 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb30a, 8 , 8 , 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb308, 13, 12, 0x3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb308, 9 , 8 , 0x3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb308, 5 , 4 , 0x3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb30a, 6 , 6 , 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb30a, 4 , 4 , 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb30a, 2 , 2 , 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x82DF, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8267, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x81EF, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x829A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8222, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x81AA, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x829B, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x7 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8223, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x7 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x81AB, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x7 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, +}; + +rtk_hwpatch_t rtl8261n_c_dataram_conf[148] = { + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb820, 7 , 7 , 0x0 , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb896, 0 , 0 , 0x0 , RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb892, 15, 8 , 0x0 , RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC10B, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xD5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC10C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xD5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC10D, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xD5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC10E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xD5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC10F, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xD5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC110, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xD5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC149, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x08 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC14A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x08 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC14B, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x08 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC14C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x08 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC14D, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x08 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC14E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x08 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC166, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xEE , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC167, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xEE , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC168, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x07 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC169, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x09 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC16A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x0B , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC16B, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x0D , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC16C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x13 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC16D, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x0E , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC16E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x11 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC16F, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x14 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC170, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x17 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC171, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x15 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC172, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x10 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC173, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x0B , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC128, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xF7 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC129, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xF7 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC12A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xF8 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC12B, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xF7 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC12C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xF6 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC12D, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xF5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC12E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xF2 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC12F, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xF7 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC130, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xF5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC131, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xF2 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC132, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xF0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC133, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xF1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC134, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xF4 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC135, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xF7 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC118, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xEC , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC119, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xEB , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC11A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xEB , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC11B, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xE8 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC11C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xE8 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC11D, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xEA , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC11E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xE9 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC11F, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xE7 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC120, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xE6 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC121, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xE7 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC122, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xE6 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC123, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xEA , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC124, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xEB , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC125, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xED , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC126, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xE3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC127, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xE0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC156, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x19 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC157, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x1B , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC158, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x1B , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC159, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x1F , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC15A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x1E , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC15B, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x1C , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC15C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x1D , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC15D, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x20 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC15E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x22 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC15F, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x21 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC160, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x25 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC161, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x20 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC162, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x21 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC163, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x27 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC164, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x57 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC165, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x74 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb896, 0 , 0 , 0x1 , RTK_PATCH_CMP_W , 0, 0, 0, 0}, +}; + +rtk_hwpatch_t rtl8261n_c_rtct_conf[176] = { + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa468, 1 , 0 , 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa422, 0 , 0 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xc010, 9 , 9 , 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xc010, 10, 10, 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xc010, 14, 13, 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xc000, 0 , 0 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_DELAY_MS, 0 , 0 , 0 , 0 , 0 , 1000 , RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8260, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x25 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8270, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x8 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8271, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x1D , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8280, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x20 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8281, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8278, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x02 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8279, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8274, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x01 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8275, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x01 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8276, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8277, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x827C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x827D, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x04 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x827E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x827F, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x25 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x827A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x1F , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x827B, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x40 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8263, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x34 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8264, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xBC , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8261, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x32 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8262, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8265, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8273, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xE4 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8266, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x45 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8267, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xE0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8282, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8283, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x0b , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8284, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8285, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x1D , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8286, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xFF , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8287, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xFA , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8288, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8289, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x03 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x828A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x05 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x828B, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xE7 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x828C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xFF , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x828D, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x5F , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x828E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x828F, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x3E , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8290, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xFF , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8291, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xF4 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8292, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x06 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8293, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xF5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8294, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xFF , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8295, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x12 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8296, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8297, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x59 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8298, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xFF , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8299, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xF2 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x829A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xF8 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x829B, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xEA , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x829C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x829D, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x35 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x829E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xFF , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x829F, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xBE , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82A0, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82A1, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x36 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82A2, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xFA , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82A3, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x30 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82A4, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82A5, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x35 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82A6, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xFF , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82A7, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xBE , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82A8, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82A9, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x36 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82AA, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x06 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82AB, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x10 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82AC, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xFF , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82AD, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x98 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82AE, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82AF, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x10 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82B0, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82B1, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x06 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82B2, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x02 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82B3, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x60 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82B4, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82B5, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82B6, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82B7, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82B8, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x82B9, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x826D, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x2B , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x826E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x03 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa422, 1 , 1 , 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa422, 7 , 4 , 0xf , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 90 , 21 , 7 , 0 , 0x3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, +}; + diff --git a/sources/uboot-be550/drivers/net/ipq_common/construct/conf_rtl8264b.c b/sources/uboot-be550/drivers/net/ipq_common/construct/conf_rtl8264b.c new file mode 100644 index 00000000..8f61054e --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq_common/construct/conf_rtl8264b.c @@ -0,0 +1,2331 @@ +/* + * SPDX-License-Identifier: GPL-2.0-only + * + * Copyright (c) 2023 Realtek Semiconductor Corp. All rights reserved. + */ +//Date: Tue Jan 31 11:51:10 2023 + +rtk_hwpatch_t rtl8264b_top_conf[] = { + {RTK_PATCH_OP_TOP , 0xf , 2 , 20 , 15, 0 , 0x5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 2 , 21 , 15, 0 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 2 , 22 , 15, 0 , 0x280 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 2 , 23 , 15, 0 , 0x0014, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 3 , 16 , 15, 0 , 0x0300, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 3 , 17 , 15, 0 , 0x01ff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 3 , 18 , 15, 0 , 0x000c, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 3 , 19 , 15, 0 , 0x01ff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 3 , 20 , 15, 0 , 0x0200, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 3 , 21 , 15, 0 , 0x0015, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 3 , 22 , 15, 0 , 0x0200, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 3 , 23 , 15, 0 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 4 , 16 , 15, 0 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 13 , 23 , 8 , 5 , 0x6 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 90 , 18 , 15, 0 , 0xd , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 90 , 19 , 15, 0 , 0xd , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 90 , 20 , 15, 8 , 0x02 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, +}; + +rtk_hwpatch_t rtl8264b_sds_conf[] = { + {RTK_PATCH_OP_TOP , 0xf , 24 , 18 , 15, 0 , 0x881F, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 24 , 19 , 15, 0 , 0x003F, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 24 , 20 , 15, 0 , 0x003F, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 24 , 21 , 15, 0 , 0x003F, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 24 , 22 , 15, 0 , 0x001F, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x06 , 0x0D , 15, 0 , 0x0F00, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x06 , 0x0E , 15, 0 , 0x3F5A, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x07 , 0x10 , 15, 12, 0x8 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x07 , 0x10 , 7 , 0 , 0x3 , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x06 , 0x1D , 15, 0 , 0x0600, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x21 , 0x00 , 15, 0 , 0x4902, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x21 , 0x08 , 15, 0 , 0x0FC0, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x21 , 0x09 , 15, 0 , 0x33F0, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x21 , 0x0C , 15, 0 , 0x08BF, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x21 , 0x12 , 15, 0 , 0x8000, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x36 , 0x07 , 15, 0 , 0x04C0, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x36 , 0x08 , 15, 0 , 0x2000, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2E , 0x0B , 15, 0 , 0x2390, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2E , 0x0C , 15, 0 , 0xAA17, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2E , 0x0D , 15, 0 , 0xFE40, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2E , 0x0E , 15, 0 , 0x12F4, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2E , 0x11 , 15, 0 , 0xF2AD, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2E , 0x15 , 15, 0 , 0x7A41, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2E , 0x16 , 15, 0 , 0x0041, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2F , 0x00 , 15, 0 , 0x1F00, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2F , 0x01 , 15, 0 , 0x2800, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2F , 0x02 , 15, 0 , 0x0FC8, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2F , 0x11 , 15, 0 , 0x3000, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2F , 0x13 , 15, 0 , 0xF400, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2F , 0x1E , 15, 0 , 0x0500, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x34 , 0x0B , 15, 0 , 0x2390, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x34 , 0x0C , 15, 0 , 0xA517, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x34 , 0x0D , 15, 0 , 0xFE41, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x34 , 0x0E , 15, 0 , 0x12F4, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x34 , 0x11 , 15, 0 , 0xF2AD, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x34 , 0x15 , 15, 0 , 0x7A41, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x34 , 0x16 , 15, 0 , 0x0041, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x35 , 0x00 , 15, 0 , 0x1F80, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x35 , 0x01 , 15, 0 , 0x0800, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x35 , 0x02 , 15, 0 , 0x0FC8, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x35 , 0x11 , 15, 0 , 0x3001, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x35 , 0x13 , 15, 0 , 0xF400, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x35 , 0x1E , 15, 0 , 0x0100, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2C , 0x0B , 15, 0 , 0x2390, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2C , 0x0C , 15, 0 , 0xA517, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2C , 0x0D , 15, 0 , 0xFE41, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2C , 0x0E , 15, 0 , 0x12F4, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2C , 0x11 , 15, 0 , 0xF2AD, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2C , 0x15 , 15, 0 , 0x7A61, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2C , 0x16 , 15, 0 , 0x0041, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2D , 0x00 , 15, 0 , 0x1F80, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2D , 0x01 , 15, 0 , 0x0800, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2D , 0x02 , 15, 0 , 0x0FC8, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2D , 0x11 , 15, 0 , 0x3001, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2D , 0x13 , 15, 0 , 0xF400, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x2D , 0x1E , 15, 0 , 0x0100, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x28 , 0x0B , 15, 0 , 0x2390, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x28 , 0x0C , 15, 0 , 0xA514, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x28 , 0x0D , 15, 0 , 0xFE43, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x28 , 0x0E , 15, 0 , 0x12F4, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x28 , 0x11 , 15, 0 , 0xF2AD, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x28 , 0x15 , 15, 0 , 0x7A61, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x28 , 0x16 , 15, 0 , 0x0041, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x29 , 0x00 , 15, 0 , 0x1F80, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x29 , 0x01 , 15, 0 , 0x0800, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x29 , 0x02 , 15, 0 , 0x0FC8, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x29 , 0x11 , 15, 0 , 0x3001, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x29 , 0x13 , 15, 0 , 0xF400, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x29 , 0x1E , 15, 0 , 0x0100, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x26 , 0x0B , 15, 0 , 0x2390, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x26 , 0x0C , 15, 0 , 0xA514, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x26 , 0x0D , 15, 0 , 0xFE43, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x26 , 0x0E , 15, 0 , 0x12F4, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x26 , 0x11 , 15, 0 , 0xF2AD, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x26 , 0x15 , 15, 0 , 0x7A41, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x26 , 0x16 , 15, 0 , 0x0041, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x27 , 0x00 , 15, 0 , 0x1F80, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x27 , 0x01 , 15, 0 , 0x0800, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x27 , 0x02 , 15, 0 , 0x0FC8, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x27 , 0x11 , 15, 0 , 0x3001, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x27 , 0x13 , 15, 0 , 0xF400, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x27 , 0x1E , 15, 0 , 0x0100, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x24 , 0x0B , 15, 0 , 0x2390, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x24 , 0x0C , 15, 0 , 0xA514, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x24 , 0x0D , 15, 0 , 0xFE43, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x24 , 0x0E , 15, 0 , 0x12F4, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x24 , 0x11 , 15, 0 , 0xF2AD, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x24 , 0x15 , 15, 0 , 0x7A41, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x24 , 0x16 , 15, 0 , 0x0041, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x25 , 0x00 , 15, 0 , 0x1F80, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x25 , 0x01 , 15, 0 , 0x0800, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x25 , 0x02 , 15, 0 , 0x0FC8, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x25 , 0x11 , 15, 0 , 0x3001, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x25 , 0x13 , 15, 0 , 0xF400, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x25 , 0x1E , 15, 0 , 0x0100, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 24 , 18 , 15, 0 , 0x880D, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 24 , 19 , 15, 0 , 0x0024, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 24 , 20 , 15, 0 , 0x0036, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 24 , 21 , 15, 0 , 0x0035, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 24 , 22 , 15, 0 , 0x001A, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x1F , 0x00 , 15, 0 , 0x001B, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PSDS0 , 0xf , 0x1F , 0x00 , 15, 0 , 0x0000, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 90 , 20 , 7 , 0 , 0x04 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, +}; + +rtk_hwpatch_t rtl8264b_afe_conf[] = { + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbf92, 15, 11, 0x1C , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbfaa, 10, 8 , 0x5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbfae, 8 , 6 , 0x5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbfaa, 12, 11, 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbf1c, 4 , 4 , 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbf0e, 5 , 4 , 0x3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbf1c, 15, 13, 0x5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbf16, 12, 12, 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbc24, 3 , 2 , 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbc24, 1 , 0 , 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbf08, 2 , 0 , 0x6 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbf0c, 5 , 3 , 0x7 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbf0c, 8 , 6 , 0x7 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbf0c, 11, 9 , 0x7 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbf0c, 14, 12, 0x7 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbf1a, 3 , 2 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_TOP , 0xf , 90 , 21 , 15, 8 , 0x04 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, +}; + +rtk_hwpatch_t rtl8264b_uc_conf[] = { + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb820, 7 , 7 , 0x0 , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbd8a, 5 , 3 , 0x3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbd8c, 6 , 4 , 0x5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8060, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 12, 10, 0x3 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8061, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 13, 0x5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa466, 1 , 1 , 0x1 , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8491, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x1D , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8018, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 12, 12, 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x85af, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xaf85, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85af}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xc7af, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85b1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x85df, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85b3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xaf86, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85b5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1baf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85b7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8674, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85b9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xaf86, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85bb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x7daf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85bd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x875b, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85bf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xaf87, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85c1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x67af, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85c3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8774, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85c5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf85, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85c7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xdc02, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85c9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6957, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85cb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe48f, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85cd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2ce5, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85cf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8f2d, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85d1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe084, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85d3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x11e1, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85d5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8412, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85d7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xaf5d, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85d9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x73f6, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85db}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xb01a, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85dd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe08f, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85df}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2ce1, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85e1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8f2d, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85e3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6d, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85e5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6802, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85e7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6938, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85e9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6d, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85eb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6b02, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85ed}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6938, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85ef}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6d, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85f1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6e02, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85f3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6938, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85f5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6d, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85f7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x7102, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85f9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6938, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85fb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6d, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85fd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x7402, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85ff}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x70e5, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8601}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6d, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8603}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x7702, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8605}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x70e5, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8607}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6d, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8609}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x7a02, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x860b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x70e5, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x860d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6d, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x860f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x7d02, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8611}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x70e5, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8613}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd784, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8615}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa2af, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8617}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5eed, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8619}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0286, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x861b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x21af, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x861d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x07ad, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x861f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf8f9, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8621}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xfaef, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8623}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x69e0, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8625}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8018, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8627}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xad24, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8629}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x39d4, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x862b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x002e, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x862d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6e, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x862f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0402, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8631}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6938, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8633}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd480, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8635}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x03bf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8637}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x866e, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8639}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0269, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x863b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x38d4, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x863d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x000f, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x863f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf86, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8641}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x7102, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8643}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6938, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8645}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf86, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8647}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x7102, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8649}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x70dc, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x864b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd480, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x864d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0bbf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x864f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x866e, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8651}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0269, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8653}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x38d4, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8655}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x000f, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8657}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf86, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8659}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x7102, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x865b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6938, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x865d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf86, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x865f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x7102, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8661}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x70dc, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8663}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0208, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8665}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1eef, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8667}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x96fe, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8669}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xfdfc, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x866b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x04f0, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x866d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbd94, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x866f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x30bd, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8671}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9602, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8673}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8621, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8675}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0254, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8677}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xdcaf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8679}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x03c1, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x867b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0286, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x867d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2102, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x867f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8686, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8681}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xaf04, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8683}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x41f8, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8685}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xfbef, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8687}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x79e0, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8689}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8018, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x868b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xac20, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x868d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x03af, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x868f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8756, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8691}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6b, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8693}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3402, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8695}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x70dc, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8697}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6b, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8699}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3102, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x869b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x70e5, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x869d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6f, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x869f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4902, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86a1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x70dc, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86a3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6f, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86a5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4c02, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86a7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x70e5, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86a9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6f, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86ab}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4f02, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86ad}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x70e5, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86af}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6b, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86b1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3702, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86b3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x70dc, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86b5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6c, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86b7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c02, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86b9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x70dc, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86bb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6b, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86bd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3402, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86bf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x70e5, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86c1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1f00, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86c3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe183, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86c5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd4bf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86c7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6bcd, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86c9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0269, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86cb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x38bf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86cd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6bd0, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86cf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0269, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86d1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x38bf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86d3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6bd3, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86d5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0269, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86d7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x38bf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86d9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6bd6, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86db}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0269, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86dd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x38bf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86df}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6bd9, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86e1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0270, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86e3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe5bf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86e5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6bdc, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86e7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0270, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86e9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe5bf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86eb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6bdf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86ed}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0270, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86ef}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe5bf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86f1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6be2, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86f3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0270, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86f5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe5bf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86f7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6f46, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86f9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0270, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86fb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xdce1, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86fd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x83d3, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86ff}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6f, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8701}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3a02, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8703}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6938, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8705}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0d14, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8707}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6f, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8709}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4002, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x870b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6938, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x870d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0d12, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x870f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6f, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8711}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3d02, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8713}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6938, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8715}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6f, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8717}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4302, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8719}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x70dc, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x871b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0238, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x871d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xb5bf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x871f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6bd9, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8721}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0270, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8723}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xdcbf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8725}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6bdc, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8727}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0270, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8729}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xdcbf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x872b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6bdf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x872d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0270, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x872f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xdcbf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8731}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6be2, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8733}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0270, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8735}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xdcbf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8737}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6b34, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8739}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0270, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x873b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xdcbf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x873d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6b37, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x873f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0270, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8741}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe5bf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8743}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6f4f, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8745}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0270, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8747}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xdcbf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8749}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6b31, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x874b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0270, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x874d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xdcbf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x874f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6f4c, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8751}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0270, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8753}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xdcef, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8755}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x97ff, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8757}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xfc04, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8759}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xac2f, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x875b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x03af, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x875d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b2a, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x875f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x020e, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8761}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x95af, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8763}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b3f, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8765}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xee84, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8767}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3c00, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8769}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6c, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x876b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c02, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x876d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x70e5, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x876f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xaf01, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8771}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0300, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8773}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb818, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5d6d, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb81a, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5eea, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb81c, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x07aa, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb81e, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x03be, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb850, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x043e, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb852, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b26, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb878, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x00fd, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb884, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb832, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x007f, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, +}; + +rtk_hwpatch_t rtl8264b_uc2_conf[] = { + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb820, 7 , 7 , 0x1 , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb87c, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8acf, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb87e, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xaf8a, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8acf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe7af, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ad1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8b40, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ad3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xaf8b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ad5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4caf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ad7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8b6a, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ad9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xaf8b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8adb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xb5af, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8add}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8bd1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8adf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xaf8c, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ae1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x04af, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ae3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8c12, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ae5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf67, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ae7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6302, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ae9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x65f5, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8aeb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xef31, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8aed}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf67, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8aef}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6002, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8af1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x65f5, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8af3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1e31, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8af5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xac38, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8af7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x19bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8af9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x676c, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8afb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0265, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8afd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf5ef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8aff}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x31bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b01}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6769, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b03}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0265, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b05}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf51e, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b07}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x31ac, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b09}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x380c, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b0b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xee89, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b0d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2c02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b0f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xae0a, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b11}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xee89, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b13}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2c00, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b15}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xae04, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b17}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xee89, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b19}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2c01, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b1b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf8f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b1d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd5e1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b1f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x892c, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b21}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1a91, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b23}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xdbbf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b25}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x67cf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b27}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0265, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b29}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf51f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b2b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x001f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b2d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x221b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b2f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x45ad, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b31}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2705, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b33}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe187, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b35}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x06ae, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b37}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x03e1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b39}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8707, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b3b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xaf2d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b3d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1a02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b3f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8c1e, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b41}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x028c, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b43}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x7b02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b45}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x224f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b47}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xaf40, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b49}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xb8ac, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b4b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2f0f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b4d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0210, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b4f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x62bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b51}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6d36, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b53}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0265, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b55}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf5e5, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b57}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8fde, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b59}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xaf10, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b5b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4ae1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b5d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8fde, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b5f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b61}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3602, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b63}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x65d6, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b65}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xaf10, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b67}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x59e1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b69}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8fdd, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b6b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa100, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b6d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0dbf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b6f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6d36, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b71}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0265, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b73}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf5e5, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b75}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8fdc, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b77}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xee8f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b79}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xdd01, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b7b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b7d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3602, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b7f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6f77, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b81}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf86, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b83}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xc7e1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b85}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x892c, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b87}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4903, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b89}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1a91, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b8b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xef69, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b8d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xdbbf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b8f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x67cf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b91}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0265, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b93}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf51f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b95}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x001f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b97}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x22ef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b99}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x741b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b9b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x45ad, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b9d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2711, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b9f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf86, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ba1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd0d0, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ba3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x00e1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ba5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8fdc, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ba7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ba9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3602, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bab}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x65d6, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bad}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xaf35, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8baf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x46af, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bb1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3527, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bb3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x026f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bb5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6eee, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bb7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8fdd, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bb9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x00bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bbb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8d31, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bbd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x026f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bbf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6ebf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bc1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8d40, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bc3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x026f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bc5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6ebf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bc7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8d46, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bc9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x026f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bcb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6eaf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bcd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x36a9, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bcf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf8ef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bd1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x49f8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bd3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6e, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bd5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xc202, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bd7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x65f5, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bd9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xad28, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bdb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13e1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bdd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8a4e, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bdf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xad28, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8be1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0502, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8be3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5d65, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8be5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xae0e, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8be7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x025c, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8be9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1202, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8beb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8cc5, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bed}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xae06, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bef}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x025b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bf1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf302, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bf3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8d0d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bf5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe087, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bf7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x17f6, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bf9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x27e4, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bfb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8717, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bfd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xfcef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bff}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x94fc, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c01}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x04a1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c03}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0103, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c05}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x028c, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c07}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe9e0, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c09}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8a02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c0b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xef23, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c0d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xaf5c, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c0f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xdeac, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c11}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5003, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c13}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xaf61, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c15}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0d02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c17}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8d0d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c19}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xaf61, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c1b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33f8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c1d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xfafb, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c1f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xef79, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c21}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xfbbf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c23}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6766, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c25}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0265, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c27}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf5ad, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c29}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2810, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c2b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xad30, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c2d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x05d7, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c2f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0002, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c31}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xae16, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c33}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xad32, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c35}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x24d7, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c37}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0003, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c39}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xae0e, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c3b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xad31, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c3d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x05d7, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c3f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c41}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xae06, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c43}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xad33, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c45}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x14d7, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c47}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0001, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c49}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf8f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c4b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xdf4f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c4d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0008, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c4f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1a97, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c51}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd78c, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c53}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x63d6, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c55}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8c7b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c57}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0265, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c59}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3bff, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c5b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xef97, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c5d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xfffe, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c5f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xfc04, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c61}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x206b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c63}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0e20, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c65}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6b11, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c67}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x206b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c69}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1420, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c6b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6b17, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c6d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x206b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c6f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2020, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c71}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6b23, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c73}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x206b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c75}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2600, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c77}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6b29, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c79}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf8fa, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c7b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xef69, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c7d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c7f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbd02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c81}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x65f5, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c83}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xad28, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c85}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0ebf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c87}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8d34, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c89}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x026f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c8b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x77bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c8d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8d31, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c8f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x026f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c91}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x77ae, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c93}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2ad1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c95}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0fbf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c97}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8d37, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c99}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0265, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c9b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd6bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c9d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8d3a, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c9f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x026f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ca1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6ed1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ca3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x00bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ca5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8d3d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ca7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0265, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ca9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd6bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cab}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8d40, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cad}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x026f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8caf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x77d1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cb1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x00bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cb3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8d43, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cb5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0265, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cb7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd6bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cb9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8d46, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cbb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x026f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cbd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x77ef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cbf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x96fe, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cc1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xfc04, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cc3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf8ef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cc5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x49f8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cc7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cc9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbd02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ccb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x65f5, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ccd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xac28, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ccf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x12bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cd1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6be6, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cd3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0265, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cd5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf5e5, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cd7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8fd8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cd9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cdb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf202, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cdd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x65f5, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cdf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe58f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ce1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd9fc, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ce3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xef94, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ce5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xfc04, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ce7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf8ef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ce9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x49f8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ceb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ced}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbd02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cef}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x65f5, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cf1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xac28, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cf3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x12e1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cf5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8fda, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cf7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cf9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe602, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cfb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x65d6, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cfd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe18f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cff}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xdbbf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d01}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6bf2, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d03}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0265, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d05}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd6fc, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d07}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xef94, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d09}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xfc04, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d0b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf8ef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d0d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x49f8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d0f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d11}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbd02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d13}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x65f5, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d15}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xac28, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d17}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x12e1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d19}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8fd8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d1b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf6b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d1d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe602, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d1f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x65d6, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d21}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xe18f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d23}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd9bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d25}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6bf2, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d27}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0265, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d29}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd6fc, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d2b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xef94, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d2d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xfc04, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d2f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x77bd, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d31}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6c66, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d33}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbd6c, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d35}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x30bd, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d37}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5444, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d39}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbd54, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d3b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x85bd, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d3d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5e55, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d3f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbd54, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d41}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa7bd, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d43}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5cbb, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d45}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbd5c, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d47}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb85e, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2d07, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb860, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x40b5, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb862, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1047, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb864, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3504, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb886, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x36A6, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb888, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x613d, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb88a, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5cd9, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb88c, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x610a, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xb838, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x00ff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb820, 7 , 7 , 0x0 , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, +}; + +rtk_hwpatch_t rtl8264b_nctl0_conf[] = { + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb820, 7 , 7 , 0x1 , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA016, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA012, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA014, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8010, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8015, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8020, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x802a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8030, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8035, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8046, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x806b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd707, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x606f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x801a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd707, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x606f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x801a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce10, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcf01, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd705, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4004, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcf02, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd719, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3bb7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8024, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd704, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x406e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x12bd, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x12e3, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xab80, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd500, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xc402, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x004a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x30}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8b80, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x31}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd500, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x32}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x33}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0108, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x34}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c0f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x35}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x090f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x36}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c0f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x37}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0a03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x38}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd004, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x39}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1c1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x401c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce00, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd500, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x801a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x40}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd501, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x41}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce01, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x42}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x43}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x44}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0aa9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x45}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd500, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x46}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x47}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2a69, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x48}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8056, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x49}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3f48, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8058, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3f4b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x805a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x618c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3f40, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x805c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x50}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3f43, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x51}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x805e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x52}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x616b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x53}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6187, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x54}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x55}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcc8f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x56}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x57}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcc8d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x58}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf008, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x59}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcc8b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcc89, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf004, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcc87, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf002, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcc91, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x60}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x61}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b9a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x62}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x63}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xca80, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x64}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x65}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0ba0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x66}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xca00, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x67}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd504, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x68}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x69}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1658, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa208, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0a88, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0d91, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA026, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0d90, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA024, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1657, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA022, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0aa1, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA020, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0047, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA006, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0049, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA004, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x12b9, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA002, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0be5, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA000, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1811, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA008, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xff00, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA016, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA012, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0ff8, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA014, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xc483, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x0ff8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xc483, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xff9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xffa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xffb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xffc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xffd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xffe}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xfff}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA152, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1a83, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA154, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1d29, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA156, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3fff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA158, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3fff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA15A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3fff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA15C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3fff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA15E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3fff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA160, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3fff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA150, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0003, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb820, 7 , 7 , 0x0 , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, +}; + +rtk_hwpatch_t rtl8264b_nctl1_conf[] = { +}; + +rtk_hwpatch_t rtl8264b_nctl2_conf[] = { + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb820, 7 , 7 , 0x1 , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA016, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0020, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA012, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA014, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8010, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8022, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x809f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x80fb, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x810f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8116, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8304, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x831d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8370, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd707, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x416f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd05a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa501, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd701, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5fbd, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8501, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0427, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x040b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa610, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcd16, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa501, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd701, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5fbd, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8501, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd707, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x406f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x803d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x30}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x31}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x32}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x33}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5fbe, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x34}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x35}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x36}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8380, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x37}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x38}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd403, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x39}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13c5, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa340, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1433, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa108, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x40}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x41}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13ec, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x42}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8108, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x43}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x44}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x143c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x45}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa304, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x46}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa8c0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x47}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa2fc, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x48}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x49}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0ca0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0480, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x14a5, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcd17, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1c4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd057, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x50}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1c4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x51}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd066, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x52}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1c4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x53}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd076, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x54}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x55}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x56}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x57}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x607c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x58}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x613d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x59}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xfffb, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa310, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5fbd, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa607, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x60}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf007, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x61}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa607, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x62}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x63}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x64}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x65}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5fbc, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x66}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa310, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x67}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x68}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x69}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5fbb, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8840, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0cf8, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0d48, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x70}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x71}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1c4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x72}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd055, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x73}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x74}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x75}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x76}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5fbb, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x77}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x78}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x61e7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x79}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f3a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x88c0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x82fc, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8350, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x84a0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x80}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8607, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x81}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x82}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x83}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8df8, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x84}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8370, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x85}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x86}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xff9b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x87}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8510, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x88}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa508, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x89}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8508, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcd18, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5fb4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xb920, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x90}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x91}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x92}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x93}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x7fb4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x94}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9920, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x95}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9a20, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x96}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x97}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x98}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x99}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6065, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f94, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffe0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0233, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd705, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3fa7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x80a6, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd75f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x699c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1340, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd704, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4066, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x800a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf002, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xaa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd705, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xab}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x61b4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xac}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd704, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xad}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x609f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xae}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6150, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xaf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2d71, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x80b9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0cf0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x05a0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13b1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xba}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8220, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xbb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c30, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xbc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0410, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xbd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xbe}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x800a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xbf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x81a0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8302, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8480, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8684, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8203, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8340, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xaa10, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8b07, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xca}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xcb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x60cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xcc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x60f1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xcd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6113, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xce}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6135, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xcf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6157, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce0b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce0b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf008, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce0a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce0a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf004, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce09, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xda}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf002, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xdb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce09, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xdc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xdd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xde}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa204, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xdf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13e4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xab08, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcda0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd705, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x40de, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd162, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd045, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbf10, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xea}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13b1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xeb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9f10, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xec}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xed}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13b1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xee}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xef}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x607a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13b1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9f10, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8210, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa210, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1340, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xfa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xfb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x2969, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xfc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x810b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xfd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xfe}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8108, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xff}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x100}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8105, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x101}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd18a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x102}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x103}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf009, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x104}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x105}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x106}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x107}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1c6, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x108}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x109}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1b7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x04eb, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x110}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8df8, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x111}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8370, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x112}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x113}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x114}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x009e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x115}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x116}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x117}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8121, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x118}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x119}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x811e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1bf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd06d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1dd, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd06d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x120}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x121}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd06e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x122}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x123}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x124}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x125}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5fba, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x126}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x127}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd05a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x128}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x129}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x60cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x60f1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6113, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6135, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6157, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x130}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x131}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x132}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf008, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x133}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x134}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x135}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x136}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf004, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x137}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x138}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf002, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x139}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13e4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0ccf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b40, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x140}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c3f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x141}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c24, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x142}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x143}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa340, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x144}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x145}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1433, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x146}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa110, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x147}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x148}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13ec, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x149}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8110, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x143c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa304, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa8c0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8810, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x150}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x151}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa310, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x152}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0cfc, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x153}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0224, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x154}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0ca0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x155}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0480, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x156}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x157}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x158}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa340, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x159}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd162, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5fba, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x160}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8840, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x161}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1c4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x162}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd045, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x163}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x164}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x165}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x166}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5fba, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x167}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x168}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6127, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x169}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f3b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x88c0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x800a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8350, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x84a0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x170}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffb6, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x171}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xb920, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x172}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcd33, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x173}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x174}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x175}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x176}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x7fb4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x177}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9920, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x178}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x179}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6065, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f94, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffee, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xb820, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x180}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x181}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x182}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x7fa5, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x183}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9820, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x184}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x800a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x185}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x186}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x187}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1433, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x188}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa108, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x189}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13ec, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8108, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x143c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa2fc, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa304, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x190}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8880, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x191}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0cc0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x192}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0440, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x193}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcd34, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x194}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x195}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x196}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0cc0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x197}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b80, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x198}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xac3f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x199}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c38, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0d08, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa810, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa480, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa604, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x81a8, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd19f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1aa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ab}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ac}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x63f4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ad}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ae}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f7a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1af}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4368, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0cc0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b40, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8c3f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8d38, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ba}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x81c4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1bb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1bc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x81c1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1bd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1f4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1be}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1bf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1b7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1c6, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6074, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ca}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f7a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1cb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1cc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1cd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ce}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4056, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1cf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf004, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x61fc, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xfff9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4070, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8291, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1da}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1db}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1dc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xae80, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1dd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1de}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1df}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8291, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd05a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x60cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x60f1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6113, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6135, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6157, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ea}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1eb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ec}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf008, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ed}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ee}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ef}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf004, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf002, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13e4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0ccf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b40, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1fa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c3f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1fb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c24, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1fc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1fd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa340, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1fe}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ff}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1433, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x200}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa110, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x201}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x202}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13ec, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x203}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8110, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x204}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x205}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x143c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x206}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa304, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x207}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa8c0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x208}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8810, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x209}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa310, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0cfc, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0224, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0ca0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0480, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x210}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8604, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x211}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcd35, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x212}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd162, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x213}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x214}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x215}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x216}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x217}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5fba, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x218}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8840, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x219}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1c4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd045, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5fba, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x220}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6127, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x221}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x222}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f3b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x223}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x88c0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x224}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x800a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x225}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x226}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8350, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x227}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x84a0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x228}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffb8, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x229}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xbb80, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5fb4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xb920, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcd36, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x230}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x231}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x232}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x233}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x7fb4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x234}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9920, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x235}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9b80, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x236}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x237}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x238}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x239}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6065, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f94, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xffe8, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xb820, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x240}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x7fa5, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x241}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9820, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x242}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x800a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x243}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x244}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x245}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1433, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x246}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa108, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x247}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x248}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13ec, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x249}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8108, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x143c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa2fc, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa304, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8880, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0cc0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x250}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0440, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x251}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcd37, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x252}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x253}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x254}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0cc0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x255}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b80, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x256}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xac3f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x257}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c38, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x258}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0d08, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x259}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa810, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa480, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa604, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x260}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x261}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x826b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x262}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x263}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8268, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x264}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x265}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x266}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x267}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x268}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x269}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x141a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x270}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x271}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f7a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x272}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x273}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f28, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x274}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x275}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x276}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0cc0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x277}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b40, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x278}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8c3f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x279}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8d38, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8287, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8284, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x280}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x281}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x282}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x283}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x284}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x285}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x286}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd189, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x287}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x288}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x289}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x141a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f7a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f28, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x290}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x291}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x292}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c0f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x293}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b05, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x294}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x295}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x296}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x60cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x297}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x60f1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x298}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6113, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x299}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6135, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6157, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce08, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce08, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf008, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce08, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce08, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf004, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce08, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf002, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce08, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13e4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa180, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2aa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcd38, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ab}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ac}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ad}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x82c1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ae}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2af}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x82b9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf013, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd100, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf010, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ba}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1b7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2bb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2bc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2bd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd100, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2be}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2bf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf008, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd13b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd055, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ca}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2cb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2cc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x141a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2cd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ce}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f7b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2cf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa302, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x141a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f7a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f28, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2da}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c3f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2db}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c12, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2dc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2dd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2de}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2df}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x82f3, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x82eb, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf013, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd100, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf010, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ea}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2eb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ec}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ed}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ee}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ef}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd100, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd040, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf008, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd16b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2fa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2fb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2fc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x141a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2fd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2fe}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f7a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ff}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x300}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f2a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x301}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x302}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x085e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x303}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x304}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x305}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcb0a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x306}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0cc7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x307}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x308}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x309}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x30a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4127, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x30b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x30c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x30d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c0f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x30e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b05, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x30f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c38, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x310}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0d28, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x311}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x312}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf008, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x313}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x314}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x315}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c0f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x316}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b0a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x317}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c38, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x318}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0d18, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x319}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x31a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x31b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0f45, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x31c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x31d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x646d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x31e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x31f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8337, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x320}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x321}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x832d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x322}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x323}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x40c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x324}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x325}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x326}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd100, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x327}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x328}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf01a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x329}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x32a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x32b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf017, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x32c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x32d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x40c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x32e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x32f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x330}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd100, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x331}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x332}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf010, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x333}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x334}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x335}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x336}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x337}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x40c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x338}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x339}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x33a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x33b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x33c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x33d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x33e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x33f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x340}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x341}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x342}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x343}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x344}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x345}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x141a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x346}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x347}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f7a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x348}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x349}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f29, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x34a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x34b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x60cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x34c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x60f1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x34d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6113, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x34e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6135, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x34f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x6157, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x350}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x351}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x352}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x353}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x354}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf008, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x355}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x356}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x357}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x358}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf004, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x359}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x35a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf002, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x35b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x35c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x35d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13e4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x35e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x35f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x360}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8bc0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x361}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c3f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x362}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c09, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x363}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x364}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x365}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa310, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x366}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xa420, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x367}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcd3b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x368}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x369}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x65ad, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x36a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x43c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x36b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x36c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x36d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8381, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x36e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x36f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8379, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x370}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x371}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x372}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x373}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x374}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf024, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x375}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd15d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x376}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x377}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf021, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x378}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x379}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x37a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1c6, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x37b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x37c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf01c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x37d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd15d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x37e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x37f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf019, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x380}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x381}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x382}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x383}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x384}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf014, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x385}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x386}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x387}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf011, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x388}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x389}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x38a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8394, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x38b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x38c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x8391, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x38d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd1e5, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x38e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x38f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf009, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x390}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd191, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x391}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x392}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x393}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x394}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x395}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x396}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd16b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x397}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x398}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x399}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x39a}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x39b}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x141a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x39c}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x39d}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f7a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x39e}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x39f}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x5f2c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3a0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3a1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x40e7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3a2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3a3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3a4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c0f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3a5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b05, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3a6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3a7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3a8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3a9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3aa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0c0f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3ab}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b0a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3ac}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3ad}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xcd3c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3ae}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3af}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x644d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3b0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x43c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3b1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3b2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3b3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x83c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3b4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3b5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x83bf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3b6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3b7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3b8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3b9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3ba}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf019, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3bb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3bc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3bd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf016, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3be}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3bf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3c0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3c1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3c2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf011, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3c3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd13e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3c4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3c5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf00e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3c6}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3c7}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3c8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3c9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3ca}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf009, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3cb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3cc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3cd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3ce}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3cf}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3d0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3d1}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3d2}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3d3}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3d4}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x093a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3d5}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA10E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0883, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA10C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0f32, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA10A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0676, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA108, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x00fa, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA106, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x04d9, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA104, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x12fe, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA102, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x01c1, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA100, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x047f, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA110, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x00ff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA016, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0020, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA012, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x1ff8, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA014, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd13e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ff8}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd15c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ff9}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd16b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ffa}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xd15d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ffb}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b0e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ffc}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b0e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ffd}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b0e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ffe}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1fff}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA164, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0972, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA166, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0968, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA168, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0a0b, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA16A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0a01, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA16C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0b8a, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA16E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0bf9, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA170, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x125c, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA172, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x3fff, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0xA162, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x007F, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb820, 7 , 7 , 0x0 , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, +}; + +rtk_hwpatch_t rtl8264b_algxg_conf[] = { + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x80CD, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x25 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8065, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x15 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8175, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0xa2 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8176, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0xc5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8077, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x40 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8078, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0xcc , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8969, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x0f , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8957, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x2C , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8959, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x15 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x895A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x3E , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x895F, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x1E , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8165, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x22 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x827E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x68 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8167, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x33 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8013, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x39 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8fd7, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x14 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8fd5, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x1e , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x82D9, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x20 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x82DA, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x00 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x816E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0xab , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8159, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x58 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x815A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x99 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8139, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x25 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8125, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x67 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8126, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x89 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x827D, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x4c , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8205, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x4d , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8FD6, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x78 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8159, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x58 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x815A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x99 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x815B, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x77 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x815C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0xfb , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8125, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x67 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8126, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x89 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8127, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x77 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8128, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0xf7 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x80DF, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x51 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x80E0, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x94 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, +}; + +rtk_hwpatch_t rtl8264b_alg_giga_conf[] = { + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x80b8, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x4d , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x80b9, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xcc , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x80ba, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x80bb, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 13, 8 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x80bc, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x37 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x80bd, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 12, 8 , 0x0c , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x80be, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xBB , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x80bf, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xca , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x80c0, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x45 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x80c2, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x3b , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x80cc, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x16 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x80cd, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 10, 8 , 0x4 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x80ce, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x80cf, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 13, 8 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x80d0, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x53 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x80d1, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 12, 8 , 0x0a , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x80d2, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xB9 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x80d3, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xd0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x80d4, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x4a , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x80d6, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x35 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x80a4, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x0d , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x80a5, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xa4 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x80a6, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x59 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x80a7, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 13, 8 , 0x05 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x80a8, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xab , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x80a9, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 12, 8 , 0x0b , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x80aa, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xef , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x80ab, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xae , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x80ac, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0xdf , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x80ae, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x28 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa836, 15, 15, 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa85c, 7 , 7 , 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa85c, 6 , 3 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8367, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x5d , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, +}; + +rtk_hwpatch_t rtl8264b_normal_conf[] = { + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbd92, 15, 0 , 0x002e, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbd94, 15, 0 , 0x8003, RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbd96, 3 , 0 , 0xf , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbd96, 3 , 0 , 0x0 , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbd94, 15, 0 , 0x800b, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbd96, 3 , 0 , 0xf , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xbd96, 3 , 0 , 0x0 , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x817D, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x07 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8426, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x46 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8428, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x46 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x84de, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x84e0, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x00fc, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x84e2, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf61a, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x84e4, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x58 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x84e6, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x84e8, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x00fc, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x84ea, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf61a, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x84ec, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x58 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x84ee, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x84f0, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x00fc, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x84f2, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0xf61a, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x84f4, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 8 , 0x58 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xae32, 5 , 5 , 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x8018, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 12, 12, 0x1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8fdf, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 0 , 0x0496, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8fe1, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 0 , 0x03a5, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8fe3, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 0 , 0x02e5, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8fe5, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 0 , 0x020d, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8fe7, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 0 , 0x0496, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8fe9, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 0 , 0x03a5, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8feb, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 0 , 0x02e5, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8fed, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 0 , 0x020d, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8fef, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 0 , 0x0496, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8ff1, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 0 , 0x03a5, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8ff3, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 0 , 0x02e5, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8ff5, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 0 , 0x020d, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8ff7, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 0 , 0x0496, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8ff9, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 0 , 0x03a5, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8ffb, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 0 , 0x02e5, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8ffd, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 0 , 0x020d, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb516, 6 , 0 , 0x0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8fda, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x04 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8fdb, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x05 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8132, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x77 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8134, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x88 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x80ca, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x77 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x80cc, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x88 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8062, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x77 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87c, 15, 0 , 0x8064, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb87e, 15, 8 , 0x88 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa436, 15, 0 , 0x801E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xa438, 15, 0 , 0x0013, RTK_PATCH_CMP_WC , 0, 0, 0, 0}, +}; + +rtk_hwpatch_t rtl8264b_dataram_conf[] = { + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb820, 7 , 7 , 0x0 , RTK_PATCH_CMP_WS , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb896, 0 , 0 , 0x0 , RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb892, 15, 8 , 0x0 , RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC037, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x33 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC038, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x2A , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC039, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x25 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC03A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x20 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC03B, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x1C , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC03C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x17 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC03D, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x13 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC075, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xA1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC076, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xB1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC077, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x2E , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC078, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x55 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC079, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x19 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC07A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xDC , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC07B, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xA0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC10B, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xD5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC10C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xD5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC10D, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xD5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC10E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xD5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC10F, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xD5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC110, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xD5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC149, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x08 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC14A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x08 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC14B, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x08 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC14C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x08 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC14D, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x08 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC14E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x08 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC166, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xEE , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC167, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xEE , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC168, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x07 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC169, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x09 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC16A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x0B , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC16B, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x0D , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC16C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x13 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC16D, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x0E , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC16E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x11 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC16F, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x14 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC170, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x17 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC171, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x15 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC172, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0x10 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC173, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0x0B , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC128, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xF7 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC129, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xF7 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC12A, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xF8 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC12B, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xF7 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC12C, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xF6 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC12D, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xF5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC12E, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xF2 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC12F, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xF7 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC130, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xF5 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC131, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xF2 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC132, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xF0 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC133, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xF1 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC134, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 15, 8 , 0xF4 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb88e, 15, 0 , 0xC135, RTK_PATCH_CMP_W , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb890, 7 , 0 , 0xF7 , RTK_PATCH_CMP_WC , 0, 0, 0, 0}, + {RTK_PATCH_OP_PHYOCP , 0xf , 0 , 0xb896, 0 , 0 , 0x1 , RTK_PATCH_CMP_W , 0, 0, 0, 0}, +}; + +rtk_hwpatch_t rtl8264b_rtct_conf[] = { +}; + diff --git a/sources/uboot-be550/drivers/net/ipq_common/ipq_aquantia_phy.c b/sources/uboot-be550/drivers/net/ipq_common/ipq_aquantia_phy.c new file mode 100644 index 00000000..46de163b --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq_common/ipq_aquantia_phy.c @@ -0,0 +1,611 @@ +/* + * Copyright (c) 2017-2019, 2021, The Linux Foundation. All rights reserved. + * + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include "ipq_phy.h" +#include "ipq_aquantia_phy.h" +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; +typedef struct { + unsigned int image_type; + unsigned int header_vsn_num; + unsigned int image_src; + unsigned char *image_dest_ptr; + unsigned int image_size; + unsigned int code_size; + unsigned char *signature_ptr; + unsigned int signature_size; + unsigned char *cert_chain_ptr; + unsigned int cert_chain_size; +} mbn_header_t; + +mbn_header_t *fwimg_header; +static int debug = 0; + +#ifdef CONFIG_QCA_MMC +extern qca_mmc mmc_host; +static qca_mmc *host = &mmc_host; +#endif + +extern int ipq_mdio_write(int mii_id, + int regnum, u16 value); +extern int ipq_mdio_read(int mii_id, + int regnum, ushort *data); + +extern int ipq_mdio_write1(int mii_id, + int regnum, u16 value); +extern int ipq_mdio_read1(int mii_id, + int regnum, ushort *data); + + +extern int ipq_sw_mdio_init(const char *); +extern void ipq5332_eth_initialize(void); +static int program_ethphy_fw(unsigned int phy_addr, + uint32_t load_addr,uint32_t file_size ); +static qca_smem_flash_info_t *sfi = &qca_smem_flash_info; + +u16 aq_phy_reg_write(u32 dev_id, u32 phy_id, + u32 reg_id, u16 reg_val) +{ +#ifdef MDIO_IO_CLK_315M + ipq_mdio_write1(phy_id, reg_id, reg_val); +#else + ipq_mdio_write(phy_id, reg_id, reg_val); +#endif + return 0; +} + +u16 aq_phy_reg_read(u32 dev_id, u32 phy_id, u32 reg_id) +{ +#ifdef MDIO_IO_CLK_315M + return ipq_mdio_read1(phy_id, reg_id, NULL); +#else + return ipq_mdio_read(phy_id, reg_id, NULL); +#endif +} + +u8 aq_phy_get_link_status(u32 dev_id, u32 phy_id) +{ + u16 phy_data; + uint32_t reg; + + reg = AQ_PHY_AUTO_STATUS_REG | AQUANTIA_MII_ADDR_C45; + phy_data = aq_phy_reg_read(dev_id, phy_id, reg); + phy_data = aq_phy_reg_read(dev_id, phy_id, reg); + + if (((phy_data >> 2) & 0x1) & PORT_LINK_UP) + return 0; + + return 1; +} + +u32 aq_phy_get_duplex(u32 dev_id, u32 phy_id, fal_port_duplex_t *duplex) +{ + u16 phy_data; + uint32_t reg; + + reg = AQ_PHY_LINK_STATUS_REG | AQUANTIA_MII_ADDR_C45; + phy_data = aq_phy_reg_read(dev_id, phy_id, reg); + + /* + * Read duplex + */ + phy_data = phy_data & 0x1; + if (phy_data & 0x1) + *duplex = FAL_FULL_DUPLEX; + else + *duplex = FAL_HALF_DUPLEX; + + return 0; +} + +u32 aq_phy_get_speed(u32 dev_id, u32 phy_id, fal_port_speed_t *speed) +{ + u16 phy_data; + uint32_t reg; + + reg = AQ_PHY_LINK_STATUS_REG | AQUANTIA_MII_ADDR_C45; + phy_data = aq_phy_reg_read(dev_id, phy_id, reg); + + switch ((phy_data >> 1) & 0x7) { + case SPEED_10G: + *speed = FAL_SPEED_10000; + break; + case SPEED_5G: + *speed = FAL_SPEED_5000; + break; + case SPEED_2_5G: + *speed = FAL_SPEED_2500; + break; + case SPEED_1000MBS: + *speed = FAL_SPEED_1000; + break; + case SPEED_100MBS: + *speed = FAL_SPEED_100; + break; + case SPEED_10MBS: + *speed = FAL_SPEED_10; + break; + default: + return -EINVAL; + } + return 0; +} + +void aquantia_phy_restart_autoneg(u32 phy_id) +{ + u16 phy_data; + + phy_data = aq_phy_reg_read(0x0, phy_id, AQUANTIA_REG_ADDRESS(AQUANTIA_MMD_PHY_XS_REGISTERS, + AQUANTIA_PHY_XS_USX_TRANSMIT)); + if (!(phy_data & AQUANTIA_PHY_USX_AUTONEG_ENABLE)) + aq_phy_reg_write(0x0, phy_id,AQUANTIA_REG_ADDRESS( + AQUANTIA_MMD_PHY_XS_REGISTERS, + AQUANTIA_PHY_XS_USX_TRANSMIT), + phy_data | AQUANTIA_PHY_USX_AUTONEG_ENABLE); + + phy_data = aq_phy_reg_read(0x0, phy_id, AQUANTIA_REG_ADDRESS(AQUANTIA_MMD_AUTONEG, + AQUANTIA_AUTONEG_STANDARD_CONTROL1)); + + phy_data |= AQUANTIA_CTRL_AUTONEGOTIATION_ENABLE; + aq_phy_reg_write(0x0, phy_id, AQUANTIA_REG_ADDRESS(AQUANTIA_MMD_AUTONEG, + AQUANTIA_AUTONEG_STANDARD_CONTROL1), + phy_data | AQUANTIA_CTRL_RESTART_AUTONEGOTIATION); +} + +int ipq_qca_aquantia_phy_init(struct phy_ops **ops, u32 phy_id) +{ + u16 phy_data; + struct phy_ops *aq_phy_ops; + aq_phy_ops = (struct phy_ops *)malloc(sizeof(struct phy_ops)); + if (!aq_phy_ops) + return -ENOMEM; + aq_phy_ops->phy_get_link_status = aq_phy_get_link_status; + aq_phy_ops->phy_get_speed = aq_phy_get_speed; + aq_phy_ops->phy_get_duplex = aq_phy_get_duplex; + *ops = aq_phy_ops; + + phy_data = aq_phy_reg_read(0x0, phy_id, AQUANTIA_REG_ADDRESS(AQUANTIA_MMD_PHY_XS_REGISTERS, + AQUANTIA_PHY_XS_USX_TRANSMIT)); + + phy_data = aq_phy_reg_read(0x0, phy_id, AQUANTIA_REG_ADDRESS(1, QCA_PHY_ID1)); + printf ("PHY ID1: 0x%x\n", phy_data); + phy_data = aq_phy_reg_read(0x0, phy_id, AQUANTIA_REG_ADDRESS(1, QCA_PHY_ID2)); + printf ("PHY ID2: 0x%x\n", phy_data); + phy_data = aq_phy_reg_read(0x0, phy_id, AQUANTIA_REG_ADDRESS(AQUANTIA_MMD_PHY_XS_REGISTERS, + AQUANTIA_PHY_XS_USX_TRANSMIT)); + phy_data |= AQUANTIA_PHY_USX_AUTONEG_ENABLE; + aq_phy_reg_write(0x0, phy_id, AQUANTIA_REG_ADDRESS(AQUANTIA_MMD_PHY_XS_REGISTERS, + AQUANTIA_PHY_XS_USX_TRANSMIT), phy_data); + phy_data = aq_phy_reg_read(0x0, phy_id, AQUANTIA_REG_ADDRESS(AQUANTIA_MMD_AUTONEG, + AQUANTIA_AUTONEG_TRANSMIT_VENDOR_INTR_MASK)); + phy_data |= AQUANTIA_INTR_LINK_STATUS_CHANGE; + aq_phy_reg_write(0x0, phy_id, AQUANTIA_REG_ADDRESS(AQUANTIA_MMD_AUTONEG, + AQUANTIA_AUTONEG_TRANSMIT_VENDOR_INTR_MASK), phy_data); + phy_data = aq_phy_reg_read(0x0, phy_id, AQUANTIA_REG_ADDRESS(AQUANTIA_MMD_GLOABLE_REGISTERS, + AQUANTIA_GLOBAL_INTR_STANDARD_MASK)); + phy_data |= AQUANTIA_ALL_VENDOR_ALARMS_INTERRUPT_MASK; + aq_phy_reg_write(0x0, phy_id, AQUANTIA_REG_ADDRESS(AQUANTIA_MMD_GLOABLE_REGISTERS, + AQUANTIA_GLOBAL_INTR_STANDARD_MASK), phy_data); + phy_data = aq_phy_reg_read(0x0, phy_id, AQUANTIA_REG_ADDRESS(AQUANTIA_MMD_GLOABLE_REGISTERS, + AQUANTIA_GLOBAL_INTR_VENDOR_MASK)); + phy_data |= AQUANTIA_AUTO_AND_ALARMS_INTR_MASK; + aq_phy_reg_write(0x0, phy_id, AQUANTIA_REG_ADDRESS(AQUANTIA_MMD_GLOABLE_REGISTERS, + AQUANTIA_GLOBAL_INTR_VENDOR_MASK), phy_data); + + phy_data = aq_phy_reg_read(0x0, phy_id, AQUANTIA_REG_ADDRESS(AQUANTIA_MMD_PHY_XS_REGISTERS, + AQUANTIA_PHY_XS_USX_TRANSMIT)); + return 0; +} + +static int do_aq_phy_restart(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + unsigned int phy_addr = AQU_PHY_ADDR; + if (argc > 2) + return CMD_RET_USAGE; + + if (argc == 2) + phy_addr = simple_strtoul(argv[1], NULL, 16); + + aquantia_phy_restart_autoneg(phy_addr); + return 0; +} + +int ipq_board_fw_download(unsigned int phy_addr) +{ + char runcmd[256]; + int ret,i=0; + uint32_t start; /* block number */ + uint32_t size; /* no. of blocks */ + qca_part_entry_t ethphyfw; + unsigned int *ethphyfw_load_addr = NULL; + struct { char *name; qca_part_entry_t *part; } entries[] = { + { "0:ETHPHYFW", ðphyfw }, + }; +#ifdef CONFIG_QCA_MMC + block_dev_desc_t *blk_dev; + disk_partition_t disk_info; +#endif + /* check the smem info to see which flash used for booting */ + if (sfi->flash_type == SMEM_BOOT_SPI_FLASH) { + if (debug) { + printf("Using nor device \n"); + } + } else if (sfi->flash_type == SMEM_BOOT_NAND_FLASH) { + if (debug) { + printf("Using nand device 0\n"); + } + } else if (sfi->flash_type == SMEM_BOOT_MMC_FLASH) { + if (debug) { + printf("Using MMC device\n"); + } + } else if (sfi->flash_type == SMEM_BOOT_QSPI_NAND_FLASH) { + if (debug) { + printf("Using qspi nand device 0\n"); + } + } else { + printf("Unsupported BOOT flash type\n"); + return -1; + } + + ret = smem_getpart(entries[i].name, &start, &size); + if (ret < 0) { + debug("cdp: get part failed for %s\n", entries[i].name); + } else { + qca_set_part_entry(entries[i].name, sfi, entries[i].part, start, size); + } + + if ((sfi->flash_type == SMEM_BOOT_NAND_FLASH) || + (sfi->flash_type == SMEM_BOOT_QSPI_NAND_FLASH) || + (sfi->flash_type == SMEM_BOOT_SPI_FLASH)) { + ethphyfw_load_addr = (uint *)malloc(AQ_ETHPHYFW_IMAGE_SIZE); + /* We only need memory equivalent to max size ETHPHYFW + * which is currently assumed as 512 KB. + */ + if (ethphyfw_load_addr == NULL) { + printf("ETHPHYFW Loading failed, size = %llu\n", + ethphyfw.size); + return -1; + } else { + memset(ethphyfw_load_addr, 0, AQ_ETHPHYFW_IMAGE_SIZE); + } + } + + if ((sfi->flash_type == SMEM_BOOT_NAND_FLASH) || + (sfi->flash_type == SMEM_BOOT_QSPI_NAND_FLASH)) { + /* + * Kernel is in a separate partition + */ + snprintf(runcmd, sizeof(runcmd), + /* NOR is treated as psuedo NAND */ + "nand read 0x%p 0x%llx 0x%llx && ", + ethphyfw_load_addr, ethphyfw.offset, (long long unsigned int) AQ_ETHPHYFW_IMAGE_SIZE); + + if (debug) + printf("%s", runcmd); + + if (run_command(runcmd, 0) != CMD_RET_SUCCESS) { + free(ethphyfw_load_addr); + return CMD_RET_FAILURE; + } + } else if (sfi->flash_type == SMEM_BOOT_SPI_FLASH) { + snprintf(runcmd, sizeof(runcmd), + "sf probe && " "sf read 0x%p 0x%llx 0x%llx && ", + ethphyfw_load_addr, ethphyfw.offset, (long long unsigned int) AQ_ETHPHYFW_IMAGE_SIZE); + + if (debug) + printf("%s", runcmd); + + if (run_command(runcmd, 0) != CMD_RET_SUCCESS) { + free(ethphyfw_load_addr); + return CMD_RET_FAILURE; + } +#ifdef CONFIG_QCA_MMC + } else if (sfi->flash_type == SMEM_BOOT_MMC_FLASH ) { + blk_dev = mmc_get_dev(host->dev_num); + ret = get_partition_info_efi_by_name(blk_dev, + "0:ETHPHYFW", &disk_info); + + ethphyfw_load_addr = (uint *)malloc(((uint)disk_info.size) * + ((uint)disk_info.blksz)); + if (ethphyfw_load_addr == NULL) { + printf("ETHPHYFW Loading failed, size = %lu\n", + ((long unsigned int)(uint)disk_info.size) * ((uint)disk_info.blksz)); + return -1; + } else { + memset(ethphyfw_load_addr, 0, + (((uint)disk_info.size) * + ((uint)disk_info.blksz))); + } + + if (ret == 0) { + snprintf(runcmd, sizeof(runcmd), + "mmc read 0x%p 0x%X 0x%X", + ethphyfw_load_addr, + (uint)disk_info.start, (uint)disk_info.size); + + if (run_command(runcmd, 0) != CMD_RET_SUCCESS) { + free(ethphyfw_load_addr); + return CMD_RET_FAILURE; + } + } +#endif + } + + fwimg_header = (mbn_header_t *)(ethphyfw_load_addr); + + if (fwimg_header->image_type == 0x13 && + fwimg_header->header_vsn_num == 0x3) { + program_ethphy_fw(phy_addr, + (uint32_t)(((uint32_t)ethphyfw_load_addr) + + sizeof(mbn_header_t)), + (uint32_t)(fwimg_header->image_size)); + } else { + printf("bad magic on ETHPHYFW partition\n"); + free(ethphyfw_load_addr); + return -1; + } + free(ethphyfw_load_addr); + return 0; +} + + +#define AQ_PHY_IMAGE_HEADER_CONTENT_OFFSET_HHD 0x300 +static int program_ethphy_fw(unsigned int phy_addr, uint32_t load_addr, uint32_t file_size) +{ + int i; + uint8_t *buf; + uint16_t file_crc; + uint16_t computed_crc; + uint32_t reg1, reg2; + uint16_t recorded_ggp8_val; + uint16_t daisy_chain_dis; + uint32_t primary_header_ptr = 0x00000000; + uint32_t primary_iram_ptr = 0x00000000; + uint32_t primary_dram_ptr = 0x00000000; + uint32_t primary_iram_sz = 0x00000000; + uint32_t primary_dram_sz = 0x00000000; + uint32_t phy_img_hdr_off; + uint32_t byte_sz; + uint32_t dword_sz; + uint32_t byte_ptr; + uint16_t msw = 0; + uint16_t lsw = 0; + uint8_t msb1; + uint8_t msb2; + uint8_t lsb1; + uint8_t lsb2; + uint16_t mailbox_crc; + + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x300), 0xdead); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x301), 0xbeaf); + reg1 = aq_phy_reg_read(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x300)); + reg2 = aq_phy_reg_read(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x301)); + + if(reg1 != 0xdead && reg2 != 0xbeaf) { + printf("PHY::Scratchpad Read/Write test fail\n"); + return 0; + } + buf = (uint8_t *)load_addr; + file_crc = buf[file_size - 2] << 8 | buf[file_size - 1]; + computed_crc = cyg_crc16(buf, file_size - 2); + + if (file_crc != computed_crc) { + printf("CRC check failed on phy fw file\n"); + return 0; + } else { + printf("CRC check good on phy fw file (0x%04X)\n",computed_crc); + } + + daisy_chain_dis = aq_phy_reg_read(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0xc452)); + if (!(daisy_chain_dis & 0x1)) + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0xc452), 0x1); + + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0xc471), 0x40); + recorded_ggp8_val = aq_phy_reg_read(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0xc447)); + if ((recorded_ggp8_val & 0x1f) != phy_addr) + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0xc447), phy_addr); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0xc441), 0x4000); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0xc001), 0x41); + primary_header_ptr = (((buf[0x9] & 0x0F) << 8) | buf[0x8]) << 12; + phy_img_hdr_off = AQ_PHY_IMAGE_HEADER_CONTENT_OFFSET_HHD; + primary_iram_ptr = (buf[primary_header_ptr + phy_img_hdr_off + 0x4 + 2] << 16) | + (buf[primary_header_ptr + phy_img_hdr_off + 0x4 + 1] << 8) | + buf[primary_header_ptr + phy_img_hdr_off + 0x4]; + primary_iram_sz = (buf[primary_header_ptr + phy_img_hdr_off + 0x7 + 2] << 16) | + (buf[primary_header_ptr + phy_img_hdr_off + 0x7 + 1] << 8) | + buf[primary_header_ptr + phy_img_hdr_off + 0x7]; + primary_dram_ptr = (buf[primary_header_ptr + phy_img_hdr_off + 0xA + 2] << 16) | + (buf[primary_header_ptr + phy_img_hdr_off + 0xA + 1] << 8) | + buf[primary_header_ptr + phy_img_hdr_off + 0xA]; + primary_dram_sz = (buf[primary_header_ptr + phy_img_hdr_off + 0xD + 2] << 16) | + (buf[primary_header_ptr + phy_img_hdr_off + 0xD + 1] << 8) | + buf[primary_header_ptr + phy_img_hdr_off + 0xD]; + primary_iram_ptr += primary_header_ptr; + primary_dram_ptr += primary_header_ptr; + + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x200), 0x1000); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x200), 0x0); + computed_crc = 0; + printf("PHYFW:Loading IRAM..........."); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x202), 0x4000); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x203), 0x0); + byte_sz = primary_iram_sz; + dword_sz = byte_sz >> 2; + byte_ptr = primary_iram_ptr; + for (i = 0; i < dword_sz; i++) { + lsw = (buf[byte_ptr + 1] << 8) | buf[byte_ptr]; + byte_ptr += 2; + msw = (buf[byte_ptr + 1] << 8) | buf[byte_ptr]; + byte_ptr += 2; + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x204), msw); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x205), lsw); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x200), 0xc000); + msb1 = msw >> 8; + msb2 = msw & 0xFF; + lsb1 = lsw >> 8; + lsb2 = lsw & 0xFF; + computed_crc = cyg_crc16_computed(&msb1, 0x1, computed_crc); + computed_crc = cyg_crc16_computed(&msb2, 0x1, computed_crc); + computed_crc = cyg_crc16_computed(&lsb1, 0x1, computed_crc); + computed_crc = cyg_crc16_computed(&lsb2, 0x1, computed_crc); + } + + switch (byte_sz & 0x3) { + case 0x1: + lsw = buf[byte_ptr++]; + msw = 0x0000; + break; + case 0x2: + lsw = (buf[byte_ptr + 1] << 8) | buf[byte_ptr]; + byte_ptr += 2; + msw = 0x0000; + break; + case 0x3: + lsw = (buf[byte_ptr + 1] << 8) | buf[byte_ptr]; + byte_ptr += 2; + msw = buf[byte_ptr++]; + break; + } + + if (byte_sz & 0x3) { + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x204), msw); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x205), lsw); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x200), 0xc000); + msb1 = msw >> 8; + msb2 = msw & 0xFF; + lsb1 = lsw >> 8; + lsb2 = lsw & 0xFF; + computed_crc = cyg_crc16_computed(&msb1, 0x1, computed_crc); + computed_crc = cyg_crc16_computed(&msb2, 0x1, computed_crc); + computed_crc = cyg_crc16_computed(&lsb1, 0x1, computed_crc); + computed_crc = cyg_crc16_computed(&lsb2, 0x1, computed_crc); + } + printf("done.\n"); + printf("PHYFW:Loading DRAM.............."); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x202), 0x3ffe); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x203), 0x0); + byte_sz = primary_dram_sz; + dword_sz = byte_sz >> 2; + byte_ptr = primary_dram_ptr; + for (i = 0; i < dword_sz; i++) { + lsw = (buf[byte_ptr + 1] << 8) | buf[byte_ptr]; + byte_ptr += 2; + msw = (buf[byte_ptr + 1] << 8) | buf[byte_ptr]; + byte_ptr += 2; + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x204), msw); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x205), lsw); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x200), 0xc000); + msb1 = msw >> 8; + msb2 = msw & 0xFF; + lsb1 = lsw >> 8; + lsb2 = lsw & 0xFF; + computed_crc = cyg_crc16_computed(&msb1, 0x1, computed_crc); + computed_crc = cyg_crc16_computed(&msb2, 0x1, computed_crc); + computed_crc = cyg_crc16_computed(&lsb1, 0x1, computed_crc); + computed_crc = cyg_crc16_computed(&lsb2, 0x1, computed_crc); + } + + switch (byte_sz & 0x3) { + case 0x1: + lsw = buf[byte_ptr++]; + msw = 0x0000; + break; + case 0x2: + lsw = (buf[byte_ptr + 1] << 8) | buf[byte_ptr]; + byte_ptr += 2; + msw = 0x0000; + break; + case 0x3: + lsw = (buf[byte_ptr + 1] << 8) | buf[byte_ptr]; + byte_ptr += 2; + msw = buf[byte_ptr++]; + break; + } + + if (byte_sz & 0x3) { + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x204), msw); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x205), lsw); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x200), 0xc000); + msb1 = msw >> 8; + msb2 = msw & 0xFF; + lsb1 = lsw >> 8; + lsb2 = lsw & 0xFF; + computed_crc = cyg_crc16_computed(&msb1, 0x1, computed_crc); + computed_crc = cyg_crc16_computed(&msb2, 0x1, computed_crc); + computed_crc = cyg_crc16_computed(&lsb1, 0x1, computed_crc); + computed_crc = cyg_crc16_computed(&lsb2, 0x1, computed_crc); + } + printf("done.\n"); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0xc441), 0x2010); + mailbox_crc = aq_phy_reg_read(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x201)); + if (mailbox_crc != computed_crc) { + printf("phy fw image load CRC-16 (0x%X) does not match calculated CRC-16 (0x%X)\n", mailbox_crc, computed_crc); + return 0; + } else + printf("phy fw image load good CRC-16 matches (0x%X)\n", mailbox_crc); + + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x0), 0x0); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0xc001), 0x41); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0xc001), 0x8041); + mdelay(100); + aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0xc001), 0x40); + mdelay(100); + aquantia_phy_restart_autoneg(phy_addr); + return 0; +} + +static int do_load_fw(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + unsigned int phy_addr = AQU_PHY_ADDR; + + if (argc > 2) + return CMD_RET_USAGE; + + if (argc == 2) + phy_addr = simple_strtoul(argv[1], NULL, 16); + + miiphy_init(); + ipq5332_eth_initialize(); + ipq_sw_mdio_init("IPQ MDIO0"); + ipq_board_fw_download(phy_addr); + return 0; +} + +U_BOOT_CMD( + aq_load_fw, 5, 1, do_load_fw, + "LOAD aq-fw-binary", + "" +); + +U_BOOT_CMD( + aq_phy_restart, 5, 1, do_aq_phy_restart, + "Restart Aquantia phy", + "" +); diff --git a/sources/uboot-be550/drivers/net/ipq_common/ipq_aquantia_phy.h b/sources/uboot-be550/drivers/net/ipq_common/ipq_aquantia_phy.h new file mode 100644 index 00000000..d7eec1e5 --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq_common/ipq_aquantia_phy.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2017-2019, 2021, The Linux Foundation. All rights reserved. + * + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#define AQ_ETHPHYFW_IMAGE_SIZE 0x80000 + +#define AQUANTIA_MII_ADDR_C45 (1<<30) +#define AQUANTIA_REG_ADDRESS(dev_ad, reg_num) (AQUANTIA_MII_ADDR_C45 |\ + ((dev_ad & 0x1f) << 16) | (reg_num & 0xFFFF)) + +#define AQUANTIA_MMD_PHY_XS_REGISTERS 4 +#define AQUANTIA_PHY_XS_USX_TRANSMIT 0xc441 +#define AQUANTIA_PHY_USX_AUTONEG_ENABLE 0x8 + +#define AQUANTIA_MMD_AUTONEG 0x7 +#define AQUANTIA_AUTONEG_TRANSMIT_VENDOR_INTR_MASK 0xD401 +#define AQUANTIA_INTR_LINK_STATUS_CHANGE 0x0001 + +#define AQUANTIA_MMD_GLOABLE_REGISTERS 0x1E +#define AQUANTIA_GLOBAL_INTR_STANDARD_MASK 0xff00 +#define AQUANTIA_ALL_VENDOR_ALARMS_INTERRUPT_MASK 0x0001 + +#define AQUANTIA_GLOBAL_INTR_VENDOR_MASK 0xff01 +#define AQUANTIA_AUTO_AND_ALARMS_INTR_MASK 0x1001 + +#define AQUANTIA_AUTONEG_STANDARD_CONTROL1 0 +#define AQUANTIA_CTRL_AUTONEGOTIATION_ENABLE 0x1000 +#define AQUANTIA_CTRL_RESTART_AUTONEGOTIATION 0x0200 + +#define AQ_PHY_AUTO_STATUS_REG 0x70001 + +#define AQ_PHY_LINK_STATUS_REG 0x7c800 +#define SPEED_5G 5 +#define SPEED_2_5G 4 +#define SPEED_10G 3 +#define SPEED_1000MBS 2 +#define SPEED_100MBS 1 +#define SPEED_10MBS 0 diff --git a/sources/uboot-be550/drivers/net/ipq_common/ipq_bitbangmii.c b/sources/uboot-be550/drivers/net/ipq_common/ipq_bitbangmii.c new file mode 100644 index 00000000..6d85219e --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq_common/ipq_bitbangmii.c @@ -0,0 +1,154 @@ +/* + * Copyright (c) 2012 - 2013,2016-2017, The Linux Foundation. All rights reserved. + * + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +struct bitbang_nodes { + int mdio; + int mdc; +} __attribute__ ((aligned(8))); + +#define MAX_MDIO_BUS 2 + +struct bitbang_nodes ipq_mdio_gpio[MAX_MDIO_BUS]; + +static int ipq_mii_init(struct bb_miiphy_bus *bus) +{ + struct bitbang_nodes *bb_node = bus->priv; + struct bitbang_nodes *bb_node_base = &ipq_mdio_gpio[0]; + int gpio_node, i = 0; + + if (bb_node_base == bb_node) { + gpio_node = fdt_path_offset(gd->fdt_blob, + "/ess-switch/mdiobitbang0"); + if (gpio_node >= 0) + qca_gpio_init(gpio_node); + + } else { + gpio_node = fdt_path_offset(gd->fdt_blob, + "/ess-switch/mdiobitbang1"); + if (gpio_node >= 0) + qca_gpio_init(gpio_node); + } + + for (gpio_node = fdt_first_subnode(gd->fdt_blob, gpio_node); + gpio_node > 0; + gpio_node = fdt_next_subnode(gd->fdt_blob, gpio_node), ++i) { + + if (i) + bb_node->mdio = fdtdec_get_uint(gd->fdt_blob, + gpio_node, "gpio", 0); + else + bb_node->mdc = fdtdec_get_uint(gd->fdt_blob, + gpio_node, "gpio", 0); + } + + return 0; +} + +static int ipq_mii_mdio_active(struct bb_miiphy_bus *bus) +{ + struct bitbang_nodes *bb_node = bus->priv; + unsigned int *gpio_base; + + gpio_base = (unsigned int *)GPIO_CONFIG_ADDR(bb_node->mdio); + + writel((readl(gpio_base) | (1 << GPIO_IN_OUT_BIT)), gpio_base); + gpio_set_value(bb_node->mdio, 1); + + return 0; +} + +static int ipq_mii_mdio_tristate(struct bb_miiphy_bus *bus) +{ + struct bitbang_nodes *bb_node = bus->priv; + unsigned int *gpio_base; + + gpio_base = (unsigned int *)GPIO_CONFIG_ADDR(bb_node->mdio); + + writel((readl(gpio_base) & ~(1 << GPIO_IN_OUT_BIT)), gpio_base); + gpio_set_value(bb_node->mdio, 0); + + return 0; +} + +static int ipq_mii_set_mdio(struct bb_miiphy_bus *bus, int v) +{ + struct bitbang_nodes *bb_node = bus->priv; + + gpio_set_value(bb_node->mdio, v); + + return 0; +} + +static int ipq_mii_get_mdio(struct bb_miiphy_bus *bus, int *v) +{ + struct bitbang_nodes *bb_node = bus->priv; + + *v = gpio_get_value(bb_node->mdio); + + return 0; +} + +static int ipq_mii_set_mdc(struct bb_miiphy_bus *bus, int v) +{ + struct bitbang_nodes *bb_node = bus->priv; + + gpio_set_value(bb_node->mdc, v); + + return 0; +} + +static int ipq_mii_delay(struct bb_miiphy_bus *bus) +{ + ndelay(350); + + return 0; +} + +struct bb_miiphy_bus bb_miiphy_buses[] = { + { + .name = "MDIO0", + .init = ipq_mii_init, + .mdio_active = ipq_mii_mdio_active, + .mdio_tristate = ipq_mii_mdio_tristate, + .set_mdio = ipq_mii_set_mdio, + .get_mdio = ipq_mii_get_mdio, + .set_mdc = ipq_mii_set_mdc, + .delay = ipq_mii_delay, + .priv = &ipq_mdio_gpio[0], + }, + + { + .name = "MDIO1", + .init = ipq_mii_init, + .mdio_active = ipq_mii_mdio_active, + .mdio_tristate = ipq_mii_mdio_tristate, + .set_mdio = ipq_mii_set_mdio, + .get_mdio = ipq_mii_get_mdio, + .set_mdc = ipq_mii_set_mdc, + .delay = ipq_mii_delay, + .priv = &ipq_mdio_gpio[1], + }, + +}; + +int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) / + sizeof(bb_miiphy_buses[0]); diff --git a/sources/uboot-be550/drivers/net/ipq_common/ipq_gephy.c b/sources/uboot-be550/drivers/net/ipq_common/ipq_gephy.c new file mode 100644 index 00000000..90b1c130 --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq_common/ipq_gephy.c @@ -0,0 +1,123 @@ +/* + * Copyright (c) 2018, 2020 The Linux Foundation. All rights reserved. + + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. +*/ +#include +#include +#include +#include +#include +#include +#include "ipq_gephy.h" +#include "ipq_phy.h" + +extern int ipq5018_mdio_read(int mii_id, + int regnum, ushort *data); +extern int ipq5018_mdio_write(int mii_id, + int regnum, u16 data); + +u16 gephy_phy_reg_read(u32 dev_id, u32 phy_id, u32 reg_id) +{ + return ipq5018_mdio_read(phy_id, reg_id, NULL); +} + +u16 gephy_phy_reg_write(u32 dev_id, u32 phy_id, u32 reg_id, u16 value) +{ + return ipq5018_mdio_write(phy_id, reg_id, value); +} + +u8 gephy_phy_get_link_status(u32 dev_id, u32 phy_id) +{ + u16 phy_data; + phy_data = gephy_phy_reg_read(dev_id, + phy_id, GEPHY_PHY_SPEC_STATUS); + if (phy_data & GEPHY_STATUS_LINK_PASS) + return 0; + + return 1; +} + +u32 gephy_phy_get_duplex(u32 dev_id, u32 phy_id, fal_port_duplex_t *duplex) +{ + u16 phy_data; + + phy_data = gephy_phy_reg_read(dev_id, phy_id, + GEPHY_PHY_SPEC_STATUS); + + /* + * Read duplex + */ + if (phy_data & GEPHY_STATUS_FULL_DUPLEX) + *duplex = FAL_FULL_DUPLEX; + else + *duplex = FAL_HALF_DUPLEX; + + return 0; +} + +u32 gephy_phy_get_speed(u32 dev_id, u32 phy_id, fal_port_speed_t *speed) +{ + u16 phy_data; + + phy_data = gephy_phy_reg_read(dev_id, + phy_id, GEPHY_PHY_SPEC_STATUS); + + switch (phy_data & GEPHY_STATUS_SPEED_MASK) { + case GEPHY_STATUS_SPEED_2500MBS: + *speed = FAL_SPEED_2500; + break; + case GEPHY_STATUS_SPEED_1000MBS: + *speed = FAL_SPEED_1000; + break; + case GEPHY_STATUS_SPEED_100MBS: + *speed = FAL_SPEED_100; + break; + case GEPHY_STATUS_SPEED_10MBS: + *speed = FAL_SPEED_10; + break; + default: + return -EINVAL; + } + return 0; +} + +int ipq_gephy_phy_init(struct phy_ops **ops, u32 phy_id) +{ + u16 phy_data; + struct phy_ops *gephy_ops; + + gephy_ops = (struct phy_ops *)malloc(sizeof(struct phy_ops)); + if (!gephy_ops) + return -ENOMEM; + gephy_ops->phy_get_link_status = gephy_phy_get_link_status; + gephy_ops->phy_get_speed = gephy_phy_get_speed; + gephy_ops->phy_get_duplex = gephy_phy_get_duplex; + *ops = gephy_ops; + + phy_data = gephy_phy_reg_read(0x0, phy_id, GEPHY_PHY_ID1); + printf ("PHY ID1: 0x%x\n", phy_data); + phy_data = gephy_phy_reg_read(0x0, phy_id, GEPHY_PHY_ID2); + printf ("PHY ID2: 0x%x\n", phy_data); + + /*enable vga when init napa to fix 8023az issue*/ + phy_data = gephy_phy_reg_read(0x0, phy_id, QCA808X_8023AZ_ENABLE_VGA); + phy_data &= (~QCA808X_PHY_8023AZ_AFE_CTRL_MASK); + phy_data |= QCA808X_PHY_8023AZ_AFE_EN; + phy_data = gephy_phy_reg_write(0x0, phy_id, QCA808X_8023AZ_ENABLE_VGA, phy_data); + if (phy_data != 0) + return phy_data; + + /*special configuration for AZ under 1G speed mode*/ + phy_data = QCA808X_PHY_MMD3_AZ_TRAINING_VAL; + phy_data = gephy_phy_reg_write(0x0, phy_id, QCA808X_AZ_CONFIG_UNDER_1G_SPEED, + phy_data); + return phy_data; +} diff --git a/sources/uboot-be550/drivers/net/ipq_common/ipq_gephy.h b/sources/uboot-be550/drivers/net/ipq_common/ipq_gephy.h new file mode 100644 index 00000000..1491bfd4 --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq_common/ipq_gephy.h @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2018, 2020 The Linux Foundation. All rights reserved. + + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. +*/ + +#ifndef _IPQ_GEPHY_H_ +#define _IPQ_GEPHY_H_ + +/* PHY Registers */ +#define GEPHY_PHY_CONTROL 0 +#define GEPHY_PHY_STATUS 1 +#define GEPHY_PHY_SPEC_STATUS 17 + +#define GEPHY_PHY_ID1 2 +#define GEPHY_PHY_ID2 3 +#define GEPHY_AUTONEG_ADVERT 4 +#define GEPHY_LINK_PARTNER_ABILITY 5 +#define GEPHY_1000BASET_CONTROL 9 +#define GEPHY_1000BASET_STATUS 10 +#define GEPHY_MMD_CTRL_REG 13 +#define GEPHY_MMD_DATA_REG 14 +#define GEPHY_EXTENDED_STATUS 15 +#define GEPHY_PHY_SPEC_CONTROL 16 +#define GEPHY_PHY_INTR_MASK 18 +#define GEPHY_PHY_INTR_STATUS 19 +#define GEPHY_PHY_CDT_CONTROL 22 +#define GEPHY_DEBUG_PORT_ADDRESS 29 +#define GEPHY_DEBUG_PORT_DATA 30 + +#define GEPHY_STATUS_LINK_PASS 0x0400 + +#define GEPHY_STATUS_FULL_DUPLEX 0x2000 + +#define GEPHY_STATUS_SPEED_MASK 0x380 +#define GEPHY_STATUS_SPEED_2500MBS 0x200 +#define GEPHY_STATUS_SPEED_1000MBS 0x100 +#define GEPHY_STATUS_SPEED_100MBS 0x80 +#define GEPHY_STATUS_SPEED_10MBS 0x0000 + +#define QCA808X_PHY_MMD3_AZ_TRAINING_VAL 0x1c32 +#define QCA808X_PHY_MMD3_NUM 3 +#define QCA808X_PHY_MMD3_ADDR_CLD_CTRL7 0x8007 +#define QCA808X_PHY_MMD3_AZ_TRAINING_CTRL 0x8008 +#define QCA808X_PHY_8023AZ_AFE_CTRL_MASK 0x01f0 +#define QCA808X_PHY_8023AZ_AFE_EN 0x0090 +#define QCA808X_MII_ADDR_C45 (1<<30) +#define QCA808X_REG_C45_ADDRESS(dev_type, reg_num) (QCA808X_MII_ADDR_C45 | \ + ((dev_type & 0x1f) << 16) | (reg_num & 0xffff)) +#define QCA808X_8023AZ_ENABLE_VGA QCA808X_REG_C45_ADDRESS(QCA808X_PHY_MMD3_NUM, \ + QCA808X_PHY_MMD3_ADDR_CLD_CTRL7) +#define QCA808X_AZ_CONFIG_UNDER_1G_SPEED QCA808X_REG_C45_ADDRESS(QCA808X_PHY_MMD3_NUM, \ + QCA808X_PHY_MMD3_AZ_TRAINING_CTRL) + +#endif /* _GEPHY_PHY_H_ */ diff --git a/sources/uboot-be550/drivers/net/ipq_common/ipq_mdio.c b/sources/uboot-be550/drivers/net/ipq_common/ipq_mdio.c new file mode 100644 index 00000000..d3165460 --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq_common/ipq_mdio.c @@ -0,0 +1,677 @@ +/* + * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. + + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "ipq_mdio.h" + +#ifdef DEBUG +#define pr_debug(fmt, args...) printf(fmt, ##args); +#else +#define pr_debug(fmt, args...) +#endif + +#define MDIO_DEFAULT 0 +#define MDIO_BITBANG 1 + +static int mdio_mode = 0; +static int bus_no = 0; + +struct ipq_mdio_data { + struct mii_bus *bus; + int phy_irq[PHY_MAX_ADDR]; +}; + +void ipq_set_mdio_mode(const int mode, const int bus) +{ + mdio_mode = mode; + bus_no = bus; +} + +static int ipq_mdio_wait_busy(void) +{ + int i; + u32 busy; + for (i = 0; i < IPQ_MDIO_RETRY; i++) { + busy = readl(IPQ_MDIO_BASE + + MDIO_CTRL_4_REG) & + MDIO_CTRL_4_ACCESS_BUSY; + if (!busy) + return 0; + } + printf("%s: MDIO operation timed out\n", + __func__); + return -ETIMEDOUT; +} + +int ipq_mdio_write1(int mii_id, int regnum, u16 value) +{ + u32 cmd; + + if (regnum & MII_ADDR_C45) { + unsigned int mmd = (regnum >> 16) & 0x1F; + unsigned int reg = regnum & 0xFFFF; + + writel(CTRL_0_REG_C45_DEFAULT_VALUE_3_1M, + IPQ_MDIO_BASE + MDIO_CTRL_0_REG); + + /* Issue the phy address and reg */ + writel((mii_id << 8) | mmd, + IPQ_MDIO_BASE + MDIO_CTRL_1_REG); + + writel(reg, IPQ_MDIO_BASE + MDIO_CTRL_2_REG); + + /* issue read command */ + cmd = MDIO_CTRL_4_ACCESS_START | MDIO_CTRL_4_ACCESS_CODE_C45_ADDR; + + writel(cmd, IPQ_MDIO_BASE + MDIO_CTRL_4_REG); + + if (ipq_mdio_wait_busy()) + return -ETIMEDOUT; + } else { + writel(CTRL_0_REG_DEFAULT_VALUE, + IPQ_MDIO_BASE + MDIO_CTRL_0_REG); + + /* Issue the phy addreass and reg */ + writel((mii_id << 8 | regnum), + IPQ_MDIO_BASE + MDIO_CTRL_1_REG); + } + + /* Issue a write data */ + writel(value, IPQ_MDIO_BASE + MDIO_CTRL_2_REG); + + if (regnum & MII_ADDR_C45) { + cmd = MDIO_CTRL_4_ACCESS_START | MDIO_CTRL_4_ACCESS_CODE_C45_WRITE ; + } else { + cmd = MDIO_CTRL_4_ACCESS_START | MDIO_CTRL_4_ACCESS_CODE_WRITE ; + } + + writel(cmd, IPQ_MDIO_BASE + MDIO_CTRL_4_REG); + /* Wait for write complete */ + + if (ipq_mdio_wait_busy()) + return -ETIMEDOUT; + + return 0; +} + +int ipq_mdio_read1(int mii_id, int regnum, ushort *data) +{ + u32 val,cmd; + + if (regnum & MII_ADDR_C45) { + + unsigned int mmd = (regnum >> 16) & 0x1F; + unsigned int reg = regnum & 0xFFFF; + + writel(CTRL_0_REG_C45_DEFAULT_VALUE_3_1M, + IPQ_MDIO_BASE + MDIO_CTRL_0_REG); + + /* Issue the phy address and reg */ + writel((mii_id << 8) | mmd, + IPQ_MDIO_BASE + MDIO_CTRL_1_REG); + + + writel(reg, IPQ_MDIO_BASE + MDIO_CTRL_2_REG); + + /* issue read command */ + cmd = MDIO_CTRL_4_ACCESS_START | MDIO_CTRL_4_ACCESS_CODE_C45_ADDR; + } else { + + writel(CTRL_0_REG_DEFAULT_VALUE, + IPQ_MDIO_BASE + MDIO_CTRL_0_REG); + + /* Issue the phy address and reg */ + writel((mii_id << 8 | regnum ) , + IPQ_MDIO_BASE + MDIO_CTRL_1_REG); + + /* issue read command */ + cmd = MDIO_CTRL_4_ACCESS_START | MDIO_CTRL_4_ACCESS_CODE_READ ; + } + + /* issue read command */ + writel(cmd, IPQ_MDIO_BASE + MDIO_CTRL_4_REG); + + if (ipq_mdio_wait_busy()) + return -ETIMEDOUT; + + + if (regnum & MII_ADDR_C45) { + cmd = MDIO_CTRL_4_ACCESS_START | MDIO_CTRL_4_ACCESS_CODE_C45_READ; + writel(cmd, IPQ_MDIO_BASE + MDIO_CTRL_4_REG); + + if (ipq_mdio_wait_busy()) + return -ETIMEDOUT; + } + + /* Read data */ + val = readl(IPQ_MDIO_BASE + MDIO_CTRL_3_REG); + + if (data != NULL) + *data = val; + + return val; +} + +int ipq_mdio_write(int mii_id, int regnum, u16 value) +{ + u32 cmd; +#ifdef CONFIG_BITBANGMII + char name[16]; + + if (mdio_mode == MDIO_BITBANG) { + snprintf(name, sizeof(name), "MDIO%d", bus_no); + + bb_miiphy_write_v2(name, mii_id, regnum, value); + } else +#endif + { + if (regnum & MII_ADDR_C45) { + unsigned int mmd = (regnum >> 16) & 0x1F; + unsigned int reg = regnum & 0xFFFF; + + writel(CTRL_0_REG_C45_DEFAULT_VALUE, + IPQ_MDIO_BASE + MDIO_CTRL_0_REG); + + /* Issue the phy address and reg */ + writel((mii_id << 8) | mmd, + IPQ_MDIO_BASE + MDIO_CTRL_1_REG); + + writel(reg, IPQ_MDIO_BASE + MDIO_CTRL_2_REG); + + /* issue read command */ + cmd = MDIO_CTRL_4_ACCESS_START | + MDIO_CTRL_4_ACCESS_CODE_C45_ADDR; + + writel(cmd, IPQ_MDIO_BASE + MDIO_CTRL_4_REG); + + if (ipq_mdio_wait_busy()) + return -ETIMEDOUT; + } else { + writel(CTRL_0_REG_DEFAULT_VALUE, + IPQ_MDIO_BASE + MDIO_CTRL_0_REG); + + /* Issue the phy addreass and reg */ + writel((mii_id << 8 | regnum), + IPQ_MDIO_BASE + MDIO_CTRL_1_REG); + } + + /* Issue a write data */ + writel(value, IPQ_MDIO_BASE + MDIO_CTRL_2_REG); + + if (regnum & MII_ADDR_C45) { + cmd = MDIO_CTRL_4_ACCESS_START | + MDIO_CTRL_4_ACCESS_CODE_C45_WRITE ; + } else { + cmd = MDIO_CTRL_4_ACCESS_START | + MDIO_CTRL_4_ACCESS_CODE_WRITE ; + } + + writel(cmd, IPQ_MDIO_BASE + MDIO_CTRL_4_REG); + /* Wait for write complete */ + + if (ipq_mdio_wait_busy()) + return -ETIMEDOUT; + } + + return 0; +} + +int ipq_mdio_read(int mii_id, int regnum, ushort *data) +{ + u32 val,cmd; +#ifdef CONFIG_BITBANGMII + char name[16]; + if (mdio_mode == MDIO_BITBANG) { + + snprintf(name, sizeof(name), "MDIO%d", bus_no); + + bb_miiphy_read_v2(name, mii_id, regnum, + (unsigned short *)&val); + } else +#endif + { + if (regnum & MII_ADDR_C45) { + + unsigned int mmd = (regnum >> 16) & 0x1F; + unsigned int reg = regnum & 0xFFFF; + + writel(CTRL_0_REG_C45_DEFAULT_VALUE, + IPQ_MDIO_BASE + MDIO_CTRL_0_REG); + + /* Issue the phy address and reg */ + writel((mii_id << 8) | mmd, + IPQ_MDIO_BASE + MDIO_CTRL_1_REG); + + + writel(reg, IPQ_MDIO_BASE + MDIO_CTRL_2_REG); + + /* issue read command */ + cmd = MDIO_CTRL_4_ACCESS_START | + MDIO_CTRL_4_ACCESS_CODE_C45_ADDR; + } else { + + writel(CTRL_0_REG_DEFAULT_VALUE, + IPQ_MDIO_BASE + MDIO_CTRL_0_REG); + + /* Issue the phy address and reg */ + writel((mii_id << 8 | regnum ) , + IPQ_MDIO_BASE + MDIO_CTRL_1_REG); + + /* issue read command */ + cmd = MDIO_CTRL_4_ACCESS_START | + MDIO_CTRL_4_ACCESS_CODE_READ ; + } + + /* issue read command */ + writel(cmd, IPQ_MDIO_BASE + MDIO_CTRL_4_REG); + + if (ipq_mdio_wait_busy()) + return -ETIMEDOUT; + + + if (regnum & MII_ADDR_C45) { + cmd = MDIO_CTRL_4_ACCESS_START | + MDIO_CTRL_4_ACCESS_CODE_C45_READ; + writel(cmd, IPQ_MDIO_BASE + MDIO_CTRL_4_REG); + + if (ipq_mdio_wait_busy()) + return -ETIMEDOUT; + } + + /* Read data */ + val = readl(IPQ_MDIO_BASE + MDIO_CTRL_3_REG); + } + if (data != NULL) + *data = val; + + return val; +} + +int ipq_phy_write(struct mii_dev *bus, + int addr, int dev_addr, + int regnum, ushort value) +{ + return ipq_mdio_write(addr, regnum, value); +} + +int ipq_phy_read(struct mii_dev *bus, + int addr, int dev_addr, int regnum) +{ + return ipq_mdio_read(addr, regnum, NULL); +} + +#ifdef CONFIG_QCA8084_PHY +static void split_addr(uint32_t regaddr, uint16_t *r1, uint16_t *r2, + uint16_t *page, uint16_t *switch_phy_id) +{ + *r1 = regaddr & 0x1c; + + regaddr >>= 5; + *r2 = regaddr & 0x7; + + regaddr >>= 3; + *page = regaddr & 0xffff; + + regaddr >>= 16; + *switch_phy_id = regaddr & 0xff; +} + +uint32_t ipq_mii_read(uint32_t reg) +{ + uint16_t r1, r2, page, switch_phy_id; + uint16_t lo, hi; + + split_addr((uint32_t) reg, &r1, &r2, &page, &switch_phy_id); + + mutex_lock(&switch_mdio_lock); + ipq_mdio_write(0x18 | (switch_phy_id >> 5), switch_phy_id & 0x1f, page); + udelay(100); + lo = ipq_mdio_read(0x10 | r2, r1, NULL); + hi = ipq_mdio_read(0x10 | r2, r1 + 2, NULL); + mutex_unlock(&switch_mdio_lock); + + return (hi << 16) | lo; +} + +void ipq_mii_write(uint32_t reg, uint32_t val) +{ + uint16_t r1, r2, page, switch_phy_id; + uint16_t lo, hi; + + split_addr((uint32_t) reg, &r1, &r2, &page, &switch_phy_id); + lo = val & 0xffff; + hi = (uint16_t) (val >> 16); + + mutex_lock(&switch_mdio_lock); + ipq_mdio_write(0x18 | (switch_phy_id >> 5), switch_phy_id & 0x1f, page); + udelay(100); + ipq_mdio_write(0x10 | r2, r1, lo); + ipq_mdio_write(0x10 | r2, r1 + 2, hi); + mutex_unlock(&switch_mdio_lock); +} + +void ipq_mii_update(uint32_t reg, uint32_t mask, uint32_t val) +{ + uint32_t new_val = 0, org_val = 0; + + org_val = ipq_mii_read(reg); + + new_val = org_val & ~mask; + new_val |= val & mask; + + if (new_val != org_val) + ipq_mii_write(reg, new_val); +} + +static void ipq_clk_enable(uint32_t reg) +{ + u32 val; + + val = ipq_mii_read(reg); + val |= BIT(0); + ipq_mii_write(reg, val); +} + +static void ipq_clk_disable(uint32_t reg) +{ + u32 val; + + val = ipq_mii_read(reg); + val &= ~BIT(0); + ipq_mii_write(reg, val); +} + +static void ipq_clk_reset(uint32_t reg) +{ + u32 val; + + val = ipq_mii_read(reg); + val |= BIT(2); + ipq_mii_write(reg, val); + + udelay(21000); + + val &= ~BIT(2); + ipq_mii_write(reg, val); +} + +static u16 ipq_phy_dbg_read(u32 phy_addr, u32 reg_id) +{ + ipq_mdio_write(phy_addr, PHY_DEBUG_PORT_ADDR, reg_id); + + return ipq_mdio_read(phy_addr, PHY_DEBUG_PORT_DATA, NULL); +} + +static void ipq_phy_dbg_write(u32 phy_addr, u32 reg_id, u16 reg_val) +{ + + ipq_mdio_write(phy_addr, PHY_DEBUG_PORT_ADDR, reg_id); + + ipq_mdio_write(phy_addr, PHY_DEBUG_PORT_DATA, reg_val); +} + +static void ipq_qca8084_efuse_loading(u8 ethphy) +{ + u32 val = 0, ldo_efuse = 0, icc_efuse = 0, phy_addr = 0; + u16 reg_val = 0; + + phy_addr = ipq_mii_read(EPHY_CFG) >> (ethphy * PHY_ADDR_LENGTH) + & GENMASK(4, 0); + switch(ethphy) { + case 0: + val = ipq_mii_read(QFPROM_RAW_CALIBRATION_ROW4_LSB); + ldo_efuse = (val & GENMASK(21, 18)) >> 18; + icc_efuse = (val & GENMASK(26, 22)) >> 22; + break; + case 1: + val = ipq_mii_read(QFPROM_RAW_CALIBRATION_ROW7_LSB); + ldo_efuse = (val & GENMASK(26, 23)) >> 23; + icc_efuse = (val & GENMASK(31, 27)) >> 27; + break; + case 2: + val = ipq_mii_read(QFPROM_RAW_CALIBRATION_ROW8_LSB); + ldo_efuse = (val & GENMASK(26, 23)) >> 23; + icc_efuse = (val & GENMASK(31, 27)) >> 27; + break; + case 3: + val = ipq_mii_read(QFPROM_RAW_CALIBRATION_ROW6_MSB); + ldo_efuse = (val & GENMASK(17, 14)) >> 14; + icc_efuse = (val & GENMASK(22, 18)) >> 18; + break; + } + reg_val = ipq_phy_dbg_read(phy_addr, PHY_LDO_EFUSE_REG); + reg_val = (reg_val & ~GENMASK(7, 4)) | (ldo_efuse << 4); + ipq_phy_dbg_write(phy_addr, PHY_LDO_EFUSE_REG, reg_val); + + reg_val = ipq_phy_dbg_read(phy_addr, PHY_ICC_EFUSE_REG); + reg_val = (reg_val & ~GENMASK(4, 0)) | icc_efuse; + ipq_phy_dbg_write(phy_addr, PHY_ICC_EFUSE_REG, reg_val); +} + +void ipq_clock_init(void) +{ + u32 val = 0; + int i; + + /* Enable serdes */ + ipq_clk_enable(SRDS0_SYS_CBCR); + ipq_clk_enable(SRDS1_SYS_CBCR); + + /* Reset serdes */ + ipq_clk_reset(SRDS0_SYS_CBCR); + ipq_clk_reset(SRDS1_SYS_CBCR); + + /* Disable EPHY GMII clock */ + i = 0; + while (i < 2 * PHY_ADDR_NUM) { + ipq_clk_disable(GEPHY0_TX_CBCR + i*0x20); + i++; + } + + /* Enable ephy */ + ipq_clk_enable(EPHY0_SYS_CBCR); + ipq_clk_enable(EPHY1_SYS_CBCR); + ipq_clk_enable(EPHY2_SYS_CBCR); + ipq_clk_enable(EPHY3_SYS_CBCR); + + /* Reset ephy */ + ipq_clk_reset(EPHY0_SYS_CBCR); + ipq_clk_reset(EPHY1_SYS_CBCR); + ipq_clk_reset(EPHY2_SYS_CBCR); + ipq_clk_reset(EPHY3_SYS_CBCR); + + /* Deassert EPHY DSP */ + val = ipq_mii_read(QCA8084_GCC_GEPHY_MISC); + val &= ~GENMASK(4, 0); + ipq_mii_write(QCA8084_GCC_GEPHY_MISC, val); + + /*for ES chips, need to load efuse manually*/ + val = ipq_mii_read(QFPROM_RAW_PTE_ROW2_MSB); + val = (val & GENMASK(23, 16)) >> 16; + if(val == 1 || val == 2) { + for(i = 0; i < 4; i++) + ipq_qca8084_efuse_loading(i); + } + + /* Enable efuse loading into analog circuit */ + val = ipq_mii_read(EPHY_CFG); + /* BIT20 for PHY0 and PHY1, BIT21 for PHY2 and PHY3 */ + val &= ~GENMASK(21, 20); + ipq_mii_write(EPHY_CFG, val); + + udelay(11000); +} + +void ipq_phy_addr_fixup(void) +{ + int phy_index, addr; + u32 val; + unsigned long phyaddr_mask = 0; + + val = ipq_mii_read(EPHY_CFG); +#ifdef CONFIG_TP_EXT_PHY_RTL8251B + for (phy_index = 0, addr = 8; addr <= 11; phy_index++, addr++) +#else + for (phy_index = 0, addr = 1; addr <= 4; phy_index++, addr++) +#endif +{ + phyaddr_mask |= BIT(addr); + addr &= GENMASK(4, 0); + val &= ~(GENMASK(4, 0) << (phy_index * PHY_ADDR_LENGTH)); + val |= addr << (phy_index * PHY_ADDR_LENGTH); + } + + pr_debug("programme EPHY reg 0x%x with 0x%x\n", EPHY_CFG, val); + ipq_mii_write(EPHY_CFG, val); + + /* Programe the UNIPHY address if uniphyaddr_fixup specified. + * the UNIPHY address will select three MDIO address from + * unoccupied MDIO address space. + */ + val = ipq_mii_read(UNIPHY_CFG); + + /* For qca8386, the switch occupies the other 16 MDIO address, + * for example, if the phy address is in the range of 0 to 15, + * the switch will occupy the MDIO address from 16 to 31. + */ + phyaddr_mask |= GENMASK(31, 16); + + phy_index = 0; + + for_each_clear_bit_from(addr, &phyaddr_mask, PHY_MAX_ADDR) { + if (phy_index >= UNIPHY_ADDR_NUM) + break; + val &= ~(GENMASK(4, 0) << (phy_index * PHY_ADDR_LENGTH)); + val |= addr << (phy_index * PHY_ADDR_LENGTH); + phy_index++; + } + + if (phy_index < UNIPHY_ADDR_NUM) { + for_each_clear_bit(addr, &phyaddr_mask, PHY_MAX_ADDR) { + if (phy_index >= UNIPHY_ADDR_NUM) + break; + val &= ~(GENMASK(4, 0) << (phy_index * PHY_ADDR_LENGTH)); + val |= addr << (phy_index * PHY_ADDR_LENGTH); + phy_index++; + } + } + + pr_debug("programme UNIPHY reg 0x%x with 0x%x\n", UNIPHY_CFG, val); + ipq_mii_write(UNIPHY_CFG, val); +} +#endif + +int ipq_sw_mdio_init(const char *name) +{ + struct mii_dev *bus = mdio_alloc(); + if(!bus) { + printf("Failed to allocate IPQ MDIO bus\n"); + return -1; + } + + bus->read = ipq_phy_read; + bus->write = ipq_phy_write; + bus->reset = NULL; + snprintf(bus->name, MDIO_NAME_LEN, name); + return mdio_register(bus); +} + +#ifdef CONFIG_QCA8084_PHY +static int do_ipq_mii(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + char op[2]; + unsigned int reg = 0; + unsigned int data = 0; + + if (argc < 2) + return CMD_RET_USAGE; + + op[0] = argv[1][0]; + if (strlen(argv[1]) > 1) + op[1] = argv[1][1]; + else + op[1] = '\0'; + + if (argc >= 3) + reg = simple_strtoul(argv[2], NULL, 16); + if (argc >= 4) + data = simple_strtoul(argv[3], NULL, 16); + + if (op[0] == 'r') { + data = ipq_mii_read(reg); + printf("0x%x\n", data); + } else if (op[0] == 'w') { + ipq_mii_write(reg, data); + } else { + return CMD_RET_USAGE; + } + + return 0; +} + +U_BOOT_CMD( + ipq_mii, 4, 1, do_ipq_mii, + "IPQ mii utility commands", + "ipq_mii read - read IPQ MII register \n" + "ipq_mii write - write IPQ MII register with \n" +); +#endif + +static int do_ipq_mdio(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + char op[2]; + unsigned int addr = 0, reg = 0; + unsigned int data = 0; + + if (argc < 2) + return CMD_RET_USAGE; + + op[0] = argv[1][0]; + if (strlen(argv[1]) > 1) + op[1] = argv[1][1]; + else + op[1] = '\0'; + + if (argc >= 3) + addr = simple_strtoul(argv[2], NULL, 16); + if (argc >= 4) + reg = simple_strtoul(argv[3], NULL, 16); + if (argc >= 5) + data = simple_strtoul(argv[4], NULL, 16); + + if (op[0] == 'r') { + data = ipq_mdio_read(addr, reg, NULL); + printf("0x%x\n", data); + } else if (op[0] == 'w') { + ipq_mdio_write(addr, reg, data); + } else { + return CMD_RET_USAGE; + } + + return 0; +} + +U_BOOT_CMD( + ipq_mdio, 5, 1, do_ipq_mdio, + "IPQ mdio utility commands", + "ipq_mdio read - read IPQ MDIO PHY register \n" + "ipq_mdio write - write IPQ MDIO PHY register \n" + "Addr and/or reg may be ranges, e.g. 0-7." +); diff --git a/sources/uboot-be550/drivers/net/ipq_common/ipq_mdio.h b/sources/uboot-be550/drivers/net/ipq_common/ipq_mdio.h new file mode 100644 index 00000000..abb7ebd7 --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq_common/ipq_mdio.h @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. + + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. +*/ +#ifndef _IPQ_MDIO_H +#define _IPQ_MDIO_H + +#define IPQ_MDIO_BASE 0x90000 +#define MDIO_CTRL_0_REG 0x40 +#define MDIO_CTRL_1_REG 0x44 +#define MDIO_CTRL_2_REG 0x48 +#define MDIO_CTRL_3_REG 0x4c +#define MDIO_CTRL_4_REG 0x50 +#define MDIO_CTRL_4_ACCESS_BUSY (1 << 16) +#define MDIO_CTRL_4_ACCESS_START (1 << 8) +#define MDIO_CTRL_4_ACCESS_CODE_READ 0 +#define MDIO_CTRL_4_ACCESS_CODE_WRITE 1 +#define MDIO_CTRL_4_ACCESS_CODE_C45_ADDR 0 +#define MDIO_CTRL_4_ACCESS_CODE_C45_WRITE 1 +#define MDIO_CTRL_4_ACCESS_CODE_C45_READ 2 +#define CTRL_0_REG_DEFAULT_VALUE 0x1500F +#ifdef MDIO_12_5_MHZ +#define CTRL_0_REG_C45_DEFAULT_VALUE 0x15107 +#else +#define CTRL_0_REG_C45_DEFAULT_VALUE 0x1510F +#endif +#define CTRL_0_REG_C45_DEFAULT_VALUE_3_1M 0x1511F +#define IPQ_MDIO_RETRY 1000 +#define IPQ_MDIO_DELAY 5 + +#ifdef CONFIG_QCA8084_PHY +/* QCA8084 related MDIO Init macros */ +#define UNIPHY_CFG 0xC90F014 +#define EPHY_CFG 0xC90F018 +#define GEPHY0_TX_CBCR 0xC800058 +#define SRDS0_SYS_CBCR 0xC8001A8 +#define SRDS1_SYS_CBCR 0xC8001AC +#define EPHY0_SYS_CBCR 0xC8001B0 +#define EPHY1_SYS_CBCR 0xC8001B4 +#define EPHY2_SYS_CBCR 0xC8001B8 +#define EPHY3_SYS_CBCR 0xC8001BC +#define QCA8084_GCC_GEPHY_MISC 0xC800304 +#define QFPROM_RAW_PTE_ROW2_MSB 0xC900014 +#define QFPROM_RAW_CALIBRATION_ROW4_LSB 0xC900048 +#define QFPROM_RAW_CALIBRATION_ROW6_MSB 0xC90005C +#define QFPROM_RAW_CALIBRATION_ROW7_LSB 0xC900060 +#define QFPROM_RAW_CALIBRATION_ROW8_LSB 0xC900068 +#define PHY_ADDR_LENGTH 5 +#define PHY_ADDR_NUM 4 +#define UNIPHY_ADDR_NUM 3 +#define MII_HIGH_ADDR_PREFIX 0x18 +#define MII_LOW_ADDR_PREFIX 0x10 +#define PHY_DEBUG_PORT_ADDR 0x1d +#define PHY_DEBUG_PORT_DATA 0x1e +#define PHY_LDO_EFUSE_REG 0x180 +#define PHY_ICC_EFUSE_REG 0x280 + +DEFINE_MUTEX(switch_mdio_lock); +#endif /* End QCA8084_PHY */ + +#endif /* End _IPQ_MDIO_H */ diff --git a/sources/uboot-be550/drivers/net/ipq_common/ipq_phy.h b/sources/uboot-be550/drivers/net/ipq_common/ipq_phy.h new file mode 100755 index 00000000..f609fbae --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq_common/ipq_phy.h @@ -0,0 +1,216 @@ +/* + * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. + + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. +*/ + +#ifndef _IPQ_EDMA_H +#define _IPQ_EDMA_H + +#include +#include +#ifdef CONFIG_ATHRS17C_SWITCH +#include "athrs17_phy.h" +#endif + +#define PHY_MAX 6 +#define IPQ9574_PHY_MAX 6 +#define IPQ6018_PHY_MAX 5 +#define IPQ5332_PHY_MAX 2 + +#define QCA8084_MAX_PORTS 6 + +#define MDIO_CTRL_0_REG 0x00090040 +#define MDIO_CTRL_0_DIV(x) (x << 0) +#define MDIO_CTRL_0_MODE (1 << 8) +#define MDIO_CTRL_0_RES(x) (x << 9) +#define MDIO_CTRL_0_MDC_MODE (1 << 12) +#define MDIO_CTRL_0_GPHY(x) (x << 13) +#define MDIO_CTRL_0_RES1(x) (x << 17) + +#define PORT_LINK_DOWN 0 +#define PORT_LINK_UP 1 +#define GP_PULL_DOWN 1 +#define GP_OE_EN (1 << 9) +#define GP_VM_EN (1 << 11) +#define GP_PU_RES(x) (x << 13) +#define QCA8075_RST_VAL (GP_PULL_DOWN | GP_OE_EN | \ + GP_VM_EN | GP_PU_RES(2)) +#define QCA8337_PHY 0x004DD036 +#define QCA8075_PHY_V1_0_5P 0x004DD0B0 +#define QCA8075_PHY_V1_1_5P 0x004DD0B1 +#define QCA8075_PHY_V1_1_2P 0x004DD0B2 +#define QCA8033_PHY 0x004DD074 +#define QCA8033_PHY_ADDR 0x6 +#define QCA8081_PHY 0x004DD100 +#define QCA8081_1_1_PHY 0x004DD101 +#define QCA8084_PHY 0x004DD180 +#define AQUANTIA_PHY_107 0x03a1b4e2 +#define AQUANTIA_PHY_109 0x03a1b502 +#define AQUANTIA_PHY_111 0x03a1b610 +#define AQUANTIA_PHY_111B0 0x03a1b612 +#define AQUANTIA_PHY_112 0x03a1b660 +#define AQUANTIA_PHY_112C 0x03a1b792 +#define AQUANTIA_PHY_113C_A0 0x31c31C10 +#define AQUANTIA_PHY_113C_A1 0x31c31C11 +#define AQUANTIA_PHY_113C_B0 0x31c31C12 +#define AQUANTIA_PHY_113C_B1 0x31c31C13 +#define AQU_PHY_ADDR 0x7 +#define QCA_PHY_ID1 0x2 +#define QCA_PHY_ID2 0x3 + +#ifdef CONFIG_TP_EXT_PHY_RTL8251B +#define RTL8251B_PHY 0x001cc86a +#endif + +#ifdef CONFIG_TP_EXT_PHY_RTL8261B +#define RTL8261B_PHY 0x001CCAF3 +#endif + +#ifdef CONFIG_TP_EXT_SWITCH +#ifdef CONFIG_TP_EXT_SWITCH_RTL8367_ALL +#define RTL8367 0x8367 +#define LINK_RTL8367(_data) " test link" +#endif +#ifdef CONFIG_TP_EXT_SWITCH_RTL8372 +#define RTL8372 0x8372 +#define LINK_RTL8372(_data) " test link" +#endif +#endif +#ifdef CONFIG_TP_EXT_PHY_RTL8221B +#define RTL8221 0x8221 +#endif + + +/* Phy preferred medium type */ +typedef enum { + QCA8075_PHY_MEDIUM_COPPER = 0, + QCA8075_PHY_MEDIUM_FIBER = 1, /**< Fiber */ +} qca8075_phy_medium_t; + +/* Phy pages */ +typedef enum { + QCA8075_PHY_SGBX_PAGES = 0, /* sgbx pages */ + QCA8075_PHY_COPPER_PAGES = 1 /* copper pages */ +} qca8075_phy_reg_pages_t; + +typedef enum { + FAL_HALF_DUPLEX = 0, + FAL_FULL_DUPLEX, + FAL_DUPLEX_BUTT = 0xffff +} fal_port_duplex_t; + +typedef enum { + FAL_SPEED_10 = 10, + FAL_SPEED_100 = 100, + FAL_SPEED_1000 = 1000, + FAL_SPEED_2500 = 2500, + FAL_SPEED_5000 = 5000, + FAL_SPEED_10000 = 10000, + FAL_SPEED_BUTT = 0xffff, +} fal_port_speed_t; + +typedef enum { + FAL_CABLE_STATUS_NORMAL = 0, + FAL_CABLE_STATUS_SHORT = 1, + FAL_CABLE_STATUS_OPENED = 2, + FAL_CABLE_STATUS_INVALID = 3, + FAL_CABLE_STATUS_BUTT = 0xffff, +} fal_cable_status_t; + +enum eport_wrapper_cfg { + EPORT_WRAPPER_PSGMII = 0, + EPORT_WRAPPER_PSGMII_RGMII5, + EPORT_WRAPPER_SGMII0_RGMII5, + EPORT_WRAPPER_SGMII1_RGMII5, + EPORT_WRAPPER_PSGMII_RMII0, + EPORT_WRAPPER_PSGMII_RMII1, + EPORT_WRAPPER_PSGMII_RMII0_RMII1, + EPORT_WRAPPER_PSGMII_RGMII4, + EPORT_WRAPPER_SGMII0_RGMII4, + EPORT_WRAPPER_SGMII1_RGMII4, + EPORT_WRAPPER_SGMII4_RGMII4, + EPORT_WRAPPER_QSGMII, + EPORT_WRAPPER_SGMII_PLUS, + EPORT_WRAPPER_USXGMII, + EPORT_WRAPPER_10GBASE_R, + EPORT_WRAPPER_SGMII_CHANNEL0, + EPORT_WRAPPER_SGMII_CHANNEL1, + EPORT_WRAPPER_SGMII_CHANNEL4, + EPORT_WRAPPER_RGMII, + EPORT_WRAPPER_PSGMII_FIBER, + EPORT_WRAPPER_SGMII_FIBER, + EPORT_WRAPPER_UQXGMII, /* for four channels qca8084 phy mode*/ + EPORT_WRAPPER_UQXGMII_3CHANNELS, /* for three channels qca8084 phy mode */ + EPORT_WRAPPER_MAX = 0xFF +}; + +enum port_wrapper_cfg { + PORT_WRAPPER_PSGMII = 0, + PORT_WRAPPER_SGMII0_RGMII4, + PORT_WRAPPER_USXGMII, + PORT_WRAPPER_SGMII1_RGMII4, + PORT_WRAPPER_SGMII4_RGMII4, + PORT_WRAPPER_QSGMII, + PORT_WRAPPER_SGMII_PLUS, + PORT_WRAPPER_10GBASE_R, + PORT_WRAPPER_SGMII_FIBER, +}; + +enum phy_mode { + MALIBU_PHY_TYPE = 1, + QCA8081_PHY_TYPE = 2, + AQ_PHY_TYPE = 3, + QCA8033_PHY_TYPE = 4, + SFP_PHY_TYPE = 5, + QCA8084_PHY_TYPE = 6, + ATHRS17C_SWITCH_TYPE = 7, +#ifdef CONFIG_TP_EXT_SWITCH +#ifdef CONFIG_TP_EXT_SWITCH_RTL8367_ALL + RTL8367S_SWITCH_TYPE = 8, +#endif +#endif +#ifdef CONFIG_TP_EXT_PHY_RTL8221B + RTL8221B_PHY_TYPE = 9, +#endif +#ifdef CONFIG_TP_EXT_SWITCH +#ifdef CONFIG_TP_EXT_SWITCH_RTL8372 + RTL8372_SWITCH_TYPE = 10, +#endif +#endif +#ifdef CONFIG_TP_EXT_PHY_RTL8251B + RTL8251B_PHY_TYPE = 11, +#endif +#ifdef CONFIG_TP_EXT_PHY_RTL8261B + RTL8261B_PHY_TYPE = 12, +#endif + UNUSED_PHY_TYPE = 0xFF, +}; + +typedef struct { + u32 phy_address; + u32 phy_type; + u32 forced_speed; + u32 forced_duplex; +}phy_info_t; + +typedef struct { + u32 mode; + u32 bus_no; +}mdio_info_t; + +struct phy_ops { + u8 (*phy_get_link_status) (u32 dev_id, u32 phy_id); + u32 (*phy_get_duplex) (u32 dev_id, u32 phy_id, + fal_port_duplex_t * duplex); + u32 (*phy_get_speed) (u32 dev_id, u32 phy_id, + fal_port_speed_t * speed); +}; +#endif /* _IPQ_EDMA_H */ diff --git a/sources/uboot-be550/drivers/net/ipq_common/ipq_qca8033.c b/sources/uboot-be550/drivers/net/ipq_common/ipq_qca8033.c new file mode 100644 index 00000000..d7968d4f --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq_common/ipq_qca8033.c @@ -0,0 +1,114 @@ +/* + * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. + + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. +*/ +#include +#include +#include +#include +#include +#include +#include "ipq_qca8033.h" +#include "ipq_phy.h" + +extern int ipq_mdio_write(int mii_id, + int regnum, u16 value); +extern int ipq_mdio_read(int mii_id, + int regnum, ushort *data); + +static u16 qca8033_phy_reg_write(u32 dev_id, u32 phy_id, + u32 reg_id, u16 reg_val) +{ + ipq_mdio_write(phy_id, reg_id, reg_val); + return 0; +} + +u16 qca8033_phy_reg_read(u32 dev_id, u32 phy_id, u32 reg_id) +{ + return ipq_mdio_read(phy_id, reg_id, NULL); +} + +u8 qca8033_phy_get_link_status(u32 dev_id, u32 phy_id) +{ + u16 phy_data; + phy_data = qca8033_phy_reg_read(dev_id, + phy_id, QCA8033_PHY_SPEC_STATUS); + if (phy_data & QCA8033_STATUS_LINK_PASS) + return 0; + + return 1; +} + +u32 qca8033_phy_get_duplex(u32 dev_id, u32 phy_id, fal_port_duplex_t *duplex) +{ + u16 phy_data; + + phy_data = qca8033_phy_reg_read(dev_id, phy_id, + QCA8033_PHY_SPEC_STATUS); + + /* + * Read duplex + */ + if (phy_data & QCA8033_STATUS_FULL_DUPLEX) + *duplex = FAL_FULL_DUPLEX; + else + *duplex = FAL_HALF_DUPLEX; + + return 0; +} + +u32 qca8033_phy_get_speed(u32 dev_id, u32 phy_id, fal_port_speed_t *speed) +{ + u16 phy_data; + + phy_data = qca8033_phy_reg_read(dev_id, + phy_id, QCA8033_PHY_SPEC_STATUS); + + switch (phy_data & QCA8033_STATUS_SPEED_MASK) { + case QCA8033_STATUS_SPEED_1000MBS: + *speed = FAL_SPEED_1000; + break; + case QCA8033_STATUS_SPEED_100MBS: + *speed = FAL_SPEED_100; + break; + case QCA8033_STATUS_SPEED_10MBS: + *speed = FAL_SPEED_10; + break; + default: + return -EINVAL; + } + return 0; +} + +int ipq_qca8033_phy_init(struct phy_ops **ops, u32 phy_id) +{ + u16 phy_data; + struct phy_ops *qca8033_ops; + qca8033_ops = (struct phy_ops *)malloc(sizeof(struct phy_ops)); + if (!qca8033_ops) + return -ENOMEM; + qca8033_ops->phy_get_link_status = qca8033_phy_get_link_status; + qca8033_ops->phy_get_speed = qca8033_phy_get_speed; + qca8033_ops->phy_get_duplex = qca8033_phy_get_duplex; + *ops = qca8033_ops; + + phy_data = qca8033_phy_reg_read(0x0, phy_id, QCA8033_PHY_ID1); + printf ("PHY ID1: 0x%x\n", phy_data); + phy_data = qca8033_phy_reg_read(0x0, phy_id, QCA8033_PHY_ID2); + printf ("PHY ID2: 0x%x\n", phy_data); + qca8033_phy_reg_write(0x0, phy_id, 0x1d, 0x5); + qca8033_phy_reg_write(0x0, phy_id, 0x1e, 0x2d47); + qca8033_phy_reg_write(0x0, phy_id, 0x1d, 0xb); + qca8033_phy_reg_write(0x0, phy_id, 0x1e, 0xbc40); + qca8033_phy_reg_write(0x0, phy_id, 0x1d, 0x0); + qca8033_phy_reg_write(0x0, phy_id, 0x1e, 0x82ee); + return 0; +} diff --git a/sources/uboot-be550/drivers/net/ipq_common/ipq_qca8033.h b/sources/uboot-be550/drivers/net/ipq_common/ipq_qca8033.h new file mode 100644 index 00000000..edc14ce8 --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq_common/ipq_qca8033.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. + + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. +*/ + +#ifndef _QCA8033_PHY_H_ +#define _QCA8033_PHY_H_ + +#define QCA8033_PHY_CONTROL 0 +#define QCA8033_PHY_STATUS 1 +#define QCA8033_PHY_ID1 2 +#define QCA8033_PHY_ID2 3 +#define QCA8033_AUTONEG_ADVERT 4 +#define QCA8033_LINK_PARTNER_ABILITY 5 +#define QCA8033_AUTONEG_EXPANSION 6 +#define QCA8033_NEXT_PAGE_TRANSMIT 7 +#define QCA8033_LINK_PARTNER_NEXT_PAGE 8 +#define QCA8033_1000BASET_CONTROL 9 +#define QCA8033_1000BASET_STATUS 10 +#define QCA8033_MMD_CTRL_REG 13 +#define QCA8033_MMD_DATA_REG 14 +#define QCA8033_EXTENDED_STATUS 15 +#define QCA8033_PHY_SPEC_CONTROL 16 +#define QCA8033_PHY_SPEC_STATUS 17 +#define QCA8033_PHY_INTR_MASK 18 +#define QCA8033_PHY_INTR_STATUS 19 +#define QCA8033_PHY_CDT_CONTROL 22 +#define QCA8033_PHY_CDT_STATUS 28 +#define QCA8033_DEBUG_PORT_ADDRESS 29 +#define QCA8033_DEBUG_PORT_DATA 30 + + /* Phy Specific status fields offset:17 */ + /* 1=Speed & Duplex resolved */ +#define QCA8033_STATUS_LINK_PASS 0x0400 +#define QCA8033_STATUS_RESOVLED 0x0800 + /* 1=Duplex 0=Half Duplex */ +#define QCA8033_STATUS_FULL_DUPLEX 0x2000 + /* Speed, bits 14:15 */ +#define QCA8033_STATUS_SPEED 0xC000 +#define QCA8033_STATUS_SPEED_MASK 0xC000 + /* 00=10Mbs */ +#define QCA8033_STATUS_SPEED_10MBS 0x0000 + /* 01=100Mbs */ +#define QCA8033_STATUS_SPEED_100MBS 0x4000 + + /* 10=1000Mbs */ +#define QCA8033_STATUS_SPEED_1000MBS 0x8000 + +#endif /* _QCA8033_PHY_H_ */ diff --git a/sources/uboot-be550/drivers/net/ipq_common/ipq_qca8075.c b/sources/uboot-be550/drivers/net/ipq_common/ipq_qca8075.c new file mode 100644 index 00000000..d1bddcca --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq_common/ipq_qca8075.c @@ -0,0 +1,861 @@ +/* + * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. + + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. +*/ +#include +#include +#include +#include +#include +#include +#include +#include "ipq_phy.h" +#include "ipq_qca8075.h" + +extern int ipq_mdio_write(int mii_id, + int regnum, u16 value); +extern int ipq_mdio_read(int mii_id, + int regnum, ushort *data); + +struct phy_ops *qca8075_ops; +static u32 qca8075_id; +static u16 qca8075_phy_reg_write(u32 dev_id, u32 phy_id, + u32 reg_id, u16 reg_val) +{ + ipq_mdio_write(phy_id, reg_id, reg_val); + return 0; +} + +static u16 qca8075_phy_reg_read(u32 dev_id, u32 phy_id, u32 reg_id) +{ + return ipq_mdio_read(phy_id, reg_id, NULL); +} + +/* + * phy4 prfer medium + * get phy4 prefer medum, fiber or copper; + */ +static qca8075_phy_medium_t __phy_prefer_medium_get(u32 dev_id, + u32 phy_id) +{ + u16 phy_medium; + phy_medium = + qca8075_phy_reg_read(dev_id, phy_id, + QCA8075_PHY_CHIP_CONFIG); + + return ((phy_medium & QCA8075_PHY4_PREFER_FIBER) ? + QCA8075_PHY_MEDIUM_FIBER : QCA8075_PHY_MEDIUM_COPPER); +} + +/* + * phy4 activer medium + * get phy4 current active medium, fiber or copper; + */ +static qca8075_phy_medium_t __phy_active_medium_get(u32 dev_id, + u32 phy_id) +{ + u16 phy_data = 0; + u32 phy_mode; + + phy_mode = qca8075_phy_reg_read(dev_id, phy_id, + QCA8075_PHY_CHIP_CONFIG); + phy_mode &= 0x000f; + + if (phy_mode == QCA8075_PHY_PSGMII_AMDET) { + phy_data = qca8075_phy_reg_read(dev_id, + phy_id, QCA8075_PHY_SGMII_STATUS); + + if ((phy_data & QCA8075_PHY4_AUTO_COPPER_SELECT)) { + return QCA8075_PHY_MEDIUM_COPPER; + } else if ((phy_data & QCA8075_PHY4_AUTO_BX1000_SELECT)) { + /* PHY_MEDIUM_FIBER_BX1000 */ + return QCA8075_PHY_MEDIUM_FIBER; + } else if ((phy_data & QCA8075_PHY4_AUTO_FX100_SELECT)) { + /* PHY_MEDIUM_FIBER_FX100 */ + return QCA8075_PHY_MEDIUM_FIBER; + } + /* link down */ + return __phy_prefer_medium_get(dev_id, phy_id); + } else if ((phy_mode == QCA8075_PHY_PSGMII_BASET) || + (phy_mode == QCA8075_PHY_SGMII_BASET)) { + return QCA8075_PHY_MEDIUM_COPPER; + } else if ((phy_mode == QCA8075_PHY_PSGMII_BX1000) || + (phy_mode == QCA8075_PHY_PSGMII_FX100)) { + return QCA8075_PHY_MEDIUM_FIBER; + } else { + return QCA8075_PHY_MEDIUM_COPPER; + } +} + +/* + * phy4 copper page or fiber page select + * set phy4 copper or fiber page + */ + +static u8 __phy_reg_pages_sel(u32 dev_id, u32 phy_id, + qca8075_phy_reg_pages_t phy_reg_pages) +{ + u16 reg_pages; + reg_pages = qca8075_phy_reg_read(dev_id, + phy_id, QCA8075_PHY_CHIP_CONFIG); + + if (phy_reg_pages == QCA8075_PHY_COPPER_PAGES) { + reg_pages |= 0x8000; + } else if (phy_reg_pages == QCA8075_PHY_SGBX_PAGES) { + reg_pages &= ~0x8000; + } else + return -EINVAL; + + qca8075_phy_reg_write(dev_id, phy_id, + QCA8075_PHY_CHIP_CONFIG, reg_pages); + return 0; +} + +/* + * phy4 reg pages selection by active medium + * phy4 reg pages selection + */ +static u32 __phy_reg_pages_sel_by_active_medium(u32 dev_id, + u32 phy_id) +{ + qca8075_phy_medium_t phy_medium; + qca8075_phy_reg_pages_t reg_pages; + + phy_medium = __phy_active_medium_get(dev_id, phy_id); + if (phy_medium == QCA8075_PHY_MEDIUM_FIBER) { + reg_pages = QCA8075_PHY_SGBX_PAGES; + } else if (phy_medium == QCA8075_PHY_MEDIUM_COPPER) { + reg_pages = QCA8075_PHY_COPPER_PAGES; + } else { + return -1; + } + + return __phy_reg_pages_sel(dev_id, phy_id, reg_pages); +} + +static u8 qca8075_phy_get_link_status(u32 dev_id, u32 phy_id) +{ + u16 phy_data; + if (phy_id == COMBO_PHY_ID) + __phy_reg_pages_sel_by_active_medium(dev_id, phy_id); + phy_data = qca8075_phy_reg_read(dev_id, + phy_id, QCA8075_PHY_SPEC_STATUS); + if (phy_data & QCA8075_STATUS_LINK_PASS) + return 0; + + return 1; +} + +static u32 qca8075_phy_get_duplex(u32 dev_id, u32 phy_id, + fal_port_duplex_t * duplex) +{ + u16 phy_data; + + if (phy_id == COMBO_PHY_ID) { + __phy_reg_pages_sel_by_active_medium(dev_id, phy_id); + } + + phy_data = qca8075_phy_reg_read(dev_id, phy_id, + QCA8075_PHY_SPEC_STATUS); + + /* + * Read duplex + */ + if (phy_data & QCA8075_STATUS_FULL_DUPLEX) + *duplex = FAL_FULL_DUPLEX; + else + *duplex = FAL_HALF_DUPLEX; + + return 0; +} + +static u32 qca8075_phy_get_speed(u32 dev_id, u32 phy_id, + fal_port_speed_t * speed) +{ + u16 phy_data; + + if (phy_id == COMBO_PHY_ID) { + __phy_reg_pages_sel_by_active_medium(dev_id, phy_id); + } + phy_data = qca8075_phy_reg_read(dev_id, + phy_id, QCA8075_PHY_SPEC_STATUS); + + switch (phy_data & QCA8075_STATUS_SPEED_MASK) { + case QCA8075_STATUS_SPEED_1000MBS: + *speed = FAL_SPEED_1000; + break; + case QCA8075_STATUS_SPEED_100MBS: + *speed = FAL_SPEED_100; + break; + case QCA8075_STATUS_SPEED_10MBS: + *speed = FAL_SPEED_10; + break; + default: + return -EINVAL; + } + return 0; +} + +static u32 qca8075_phy_mmd_write(u32 dev_id, u32 phy_id, + u16 mmd_num, u16 reg_id, u16 reg_val) +{ + qca8075_phy_reg_write(dev_id, phy_id, + QCA8075_MMD_CTRL_REG, mmd_num); + qca8075_phy_reg_write(dev_id, phy_id, + QCA8075_MMD_DATA_REG, reg_id); + qca8075_phy_reg_write(dev_id, phy_id, + QCA8075_MMD_CTRL_REG, + 0x4000 | mmd_num); + qca8075_phy_reg_write(dev_id, phy_id, + QCA8075_MMD_DATA_REG, reg_val); + + return 0; +} + +static u16 qca8075_phy_mmd_read(u32 dev_id, u32 phy_id, + u16 mmd_num, u16 reg_id) +{ + qca8075_phy_reg_write(dev_id, phy_id, + QCA8075_MMD_CTRL_REG, mmd_num); + qca8075_phy_reg_write(dev_id, phy_id, + QCA8075_MMD_DATA_REG, reg_id); + qca8075_phy_reg_write(dev_id, phy_id, + QCA8075_MMD_CTRL_REG, + 0x4000 | mmd_num); + return qca8075_phy_reg_read(dev_id, phy_id, + QCA8075_MMD_DATA_REG); +} + +/* + * get phy4 medium is 100fx + */ +static u8 __medium_is_fiber_100fx(u32 dev_id, u32 phy_id) +{ + u16 phy_data; + phy_data = qca8075_phy_reg_read(dev_id, phy_id, + QCA8075_PHY_SGMII_STATUS); + + if (phy_data & QCA8075_PHY4_AUTO_FX100_SELECT) { + return 1; + } + /* Link down */ + if ((!(phy_data & QCA8075_PHY4_AUTO_COPPER_SELECT)) && + (!(phy_data & QCA8075_PHY4_AUTO_BX1000_SELECT)) && + (!(phy_data & QCA8075_PHY4_AUTO_SGMII_SELECT))) { + + phy_data = qca8075_phy_reg_read(dev_id, phy_id, + QCA8075_PHY_CHIP_CONFIG); + if ((phy_data & QCA8075_PHY4_PREFER_FIBER) + && (!(phy_data & QCA8075_PHY4_FIBER_MODE_1000BX))) { + return 1; + } + } + return 0; +} + +/* + * qca8075_phy_set_hibernate - set hibernate status + * set hibernate status + */ +static u32 qca8075_phy_set_hibernate(u32 dev_id, u32 phy_id, u8 enable) +{ + u16 phy_data; + + qca8075_phy_reg_write(dev_id, phy_id, QCA8075_DEBUG_PORT_ADDRESS, + QCA8075_DEBUG_PHY_HIBERNATION_CTRL); + + phy_data = qca8075_phy_reg_read(dev_id, phy_id, + QCA8075_DEBUG_PORT_DATA); + + if (enable) { + phy_data |= 0x8000; + } else { + phy_data &= ~0x8000; + } + + qca8075_phy_reg_write(dev_id, phy_id, QCA8075_DEBUG_PORT_DATA, phy_data); + return 0; +} + +/* + * qca8075_restart_autoneg - restart the phy autoneg + */ +static u32 qca8075_phy_restart_autoneg(u32 dev_id, u32 phy_id) +{ + u16 phy_data; + + if (phy_id == COMBO_PHY_ID) { + if (__medium_is_fiber_100fx(dev_id, phy_id)) + return -1; + __phy_reg_pages_sel_by_active_medium(dev_id, phy_id); + } + phy_data = qca8075_phy_reg_read(dev_id, phy_id, QCA8075_PHY_CONTROL); + phy_data |= QCA8075_CTRL_AUTONEGOTIATION_ENABLE; + qca8075_phy_reg_write(dev_id, phy_id, QCA8075_PHY_CONTROL, + phy_data | QCA8075_CTRL_RESTART_AUTONEGOTIATION); + + return 0; +} + +/* + * qca8075_phy_get_8023az status + * get 8023az status + */ +static u32 qca8075_phy_get_8023az(u32 dev_id, u32 phy_id, u8 *enable) +{ + u16 phy_data; + if (phy_id == COMBO_PHY_ID) { + if (QCA8075_PHY_MEDIUM_COPPER != + __phy_active_medium_get(dev_id, phy_id)) + return -1; + } + *enable = 0; + + phy_data = qca8075_phy_mmd_read(dev_id, phy_id, QCA8075_PHY_MMD7_NUM, + QCA8075_PHY_MMD7_ADDR_8023AZ_EEE_CTRL); + + if ((phy_data & 0x0004) && (phy_data & 0x0002)) + *enable = 1; + + return 0; +} + +/* + * qca8075_phy_set_powersave - set power saving status + */ +static u32 qca8075_phy_set_powersave(u32 dev_id, u32 phy_id, u8 enable) +{ + u16 phy_data; + u8 status = 0; + + if (phy_id == COMBO_PHY_ID) { + if (QCA8075_PHY_MEDIUM_COPPER != + __phy_active_medium_get(dev_id, phy_id)) + return -1; + } + + if (enable) { + qca8075_phy_get_8023az(dev_id, phy_id, &status); + if (!status) { + phy_data = qca8075_phy_mmd_read(dev_id, phy_id, + QCA8075_PHY_MMD3_NUM, + QCA8075_PHY_MMD3_ADDR_8023AZ_TIMER_CTRL); + phy_data &= ~(1 << 14); + qca8075_phy_mmd_write(dev_id, phy_id, + QCA8075_PHY_MMD3_NUM, + QCA8075_PHY_MMD3_ADDR_8023AZ_TIMER_CTRL, + phy_data); + } + phy_data = qca8075_phy_mmd_read(dev_id, phy_id, + QCA8075_PHY_MMD3_NUM, + QCA8075_PHY_MMD3_ADDR_CLD_CTRL5); + phy_data &= ~(1 << 14); + qca8075_phy_mmd_write(dev_id, phy_id, QCA8075_PHY_MMD3_NUM, + QCA8075_PHY_MMD3_ADDR_CLD_CTRL5, + phy_data); + + phy_data = qca8075_phy_mmd_read(dev_id, phy_id, + QCA8075_PHY_MMD3_NUM, + QCA8075_PHY_MMD3_ADDR_CLD_CTRL3); + phy_data &= ~(1 << 15); + qca8075_phy_mmd_write(dev_id, phy_id, QCA8075_PHY_MMD3_NUM, + QCA8075_PHY_MMD3_ADDR_CLD_CTRL3, phy_data); + + } else { + phy_data = qca8075_phy_mmd_read(dev_id, phy_id, + QCA8075_PHY_MMD3_NUM, + QCA8075_PHY_MMD3_ADDR_8023AZ_TIMER_CTRL); + phy_data |= (1 << 14); + qca8075_phy_mmd_write(dev_id, phy_id, QCA8075_PHY_MMD3_NUM, + QCA8075_PHY_MMD3_ADDR_8023AZ_TIMER_CTRL, + phy_data); + + phy_data = qca8075_phy_mmd_read(dev_id, phy_id, + QCA8075_PHY_MMD3_NUM, + QCA8075_PHY_MMD3_ADDR_CLD_CTRL5); + phy_data |= (1 << 14); + qca8075_phy_mmd_write(dev_id, phy_id, QCA8075_PHY_MMD3_NUM, + QCA8075_PHY_MMD3_ADDR_CLD_CTRL5, phy_data); + + phy_data = qca8075_phy_mmd_read(dev_id, phy_id, + QCA8075_PHY_MMD3_NUM, + QCA8075_PHY_MMD3_ADDR_CLD_CTRL3); + phy_data |= (1 << 15); + qca8075_phy_mmd_write(dev_id, phy_id, QCA8075_PHY_MMD3_NUM, + QCA8075_PHY_MMD3_ADDR_CLD_CTRL3, phy_data); + + } + qca8075_phy_reg_write(dev_id, phy_id, QCA8075_PHY_CONTROL, 0x9040); + return 0; +} + +/* + * qca8075_phy_set_802.3az + */ + static u32 qca8075_phy_set_8023az(u32 dev_id, u32 phy_id, u8 enable) +{ + u16 phy_data; + + if (phy_id == COMBO_PHY_ID) { + if (QCA8075_PHY_MEDIUM_COPPER != + __phy_active_medium_get(dev_id, phy_id)) + return -1; + } + phy_data = qca8075_phy_mmd_read(dev_id, phy_id, QCA8075_PHY_MMD7_NUM, + QCA8075_PHY_MMD7_ADDR_8023AZ_EEE_CTRL); + if (enable) { + phy_data |= 0x0006; + + qca8075_phy_mmd_write(dev_id, phy_id, QCA8075_PHY_MMD7_NUM, + QCA8075_PHY_MMD7_ADDR_8023AZ_EEE_CTRL, phy_data); + if (qca8075_id == QCA8075_PHY_V1_0_5P) { + /* + * Workaround to avoid packet loss and < 10m cable + * 1000M link not stable under az enable + */ + qca8075_phy_mmd_write(dev_id, phy_id, + QCA8075_PHY_MMD3_NUM, + QCA8075_PHY_MMD3_ADDR_8023AZ_TIMER_CTRL, + AZ_TIMER_CTRL_ADJUST_VALUE); + + qca8075_phy_mmd_write(dev_id, phy_id, + QCA8075_PHY_MMD3_NUM, + QCA8075_PHY_MMD3_ADDR_8023AZ_CLD_CTRL, + AZ_CLD_CTRL_ADJUST_VALUE); + } + } else { + phy_data &= ~0x0006; + qca8075_phy_mmd_write(dev_id, phy_id, QCA8075_PHY_MMD7_NUM, + QCA8075_PHY_MMD7_ADDR_8023AZ_EEE_CTRL, phy_data); + if (qca8075_id == QCA8075_PHY_V1_0_5P) { + qca8075_phy_mmd_write(dev_id, phy_id, + QCA8075_PHY_MMD3_NUM, + QCA8075_PHY_MMD3_ADDR_8023AZ_TIMER_CTRL, + AZ_TIMER_CTRL_DEFAULT_VALUE); + } + } + qca8075_phy_restart_autoneg(dev_id, phy_id); + return 0; +} + +void ess_reset(void) +{ + writel(0x1, 0x1812008); + mdelay(10); + writel(0x0, 0x1812008); + mdelay(100); +} + +void qca8075_ess_reset(void) +{ + int i; + u32 status; + /* + * Fix phy psgmii RX 20bit + */ + qca8075_phy_reg_write(0, 5, 0x0, 0x005b); + /* + * Reset phy psgmii + */ + qca8075_phy_reg_write(0, 5, 0x0, 0x001b); + /* + * Release reset phy psgmii + */ + qca8075_phy_reg_write(0, 5, 0x0, 0x005b); + for (i = 0; i < QCA8075_MAX_TRIES; i++) { + status = qca8075_phy_mmd_read(0, 5, 1, 0x28); + if(status & 0x1) + break; + mdelay(10); + } + if (i >= QCA8075_MAX_TRIES) + printf("qca8075 PSGMII PLL_VCO_CALIB Not Ready\n"); + mdelay(50); + /* + * Check qca8075 psgmii calibration done end. + * Freeze phy psgmii RX CDR + */ + qca8075_phy_reg_write(0, 5, 0x1a, 0x2230); + + ess_reset(); + /* + * Check ipq psgmii calibration done start + */ + for (i = 0; i < QCA8075_MAX_TRIES; i++) { + status = readl(0x000980A0); + if (status & 0x1) + break; + mdelay(10); + } + if (i >= QCA8075_MAX_TRIES) + printf("PSGMII PLL_VCO_CALIB Not Ready\n"); + mdelay(50); + /* + * Check ipq psgmii calibration done end. + * Relesae phy psgmii RX CDR + */ + qca8075_phy_reg_write(0, 5, 0x1a, 0x3230); + /* + * Release phy psgmii RX 20bit + */ + qca8075_phy_reg_write(0, 5, 0x0, 0x005f); + mdelay(200); +} + +void psgmii_self_test(void) +{ + int i, phy, j; + u32 value; + u32 phy_t_status; + u16 status; + u32 tx_counter_ok, tx_counter_error; + u32 rx_counter_ok, rx_counter_error; + u32 tx_counter_ok_high16; + u32 rx_counter_ok_high16; + u32 tx_ok, rx_ok; + + /* + * Switch to access MII reg for copper + */ + qca8075_phy_reg_write(0, 4, 0x1f, 0x8500); + for (phy = 0; phy < 5; phy++) { + /* + * Enable phy mdio broadcast write + */ + qca8075_phy_mmd_write(0, phy, 7, 0x8028, 0x801f); + } + /* + * Force no link by power down + */ + qca8075_phy_reg_write(0, 0x1f, 0x0, 0x1840); + /* + * Packet number + */ + qca8075_phy_mmd_write(0, 0x1f, 7, 0x8021, 0x3000); + qca8075_phy_mmd_write(0, 0x1f, 7, 0x8062, 0x05e0); + /* + * Fix mdi status + */ + qca8075_phy_reg_write(0, 0x1f, 0x10, 0x6800); + + for (i = 0; i < 100; i++) { + phy_t_status = 0; + for (phy = 0; phy < 5; phy++) { + value = readl(0xc00066c + (phy * 0xc)); + /* + * Enable mac loop back + */ + writel((value | (1 << 21)), (0xc00066c + (phy * 0xc))); + } + /* + * Phy single test + */ + for (phy = 0; phy < 5; phy++) { + /* + * Enable loopback + */ + qca8075_phy_reg_write(0, phy, 0x0, 0x9000); + qca8075_phy_reg_write(0, phy, 0x0, 0x4140); + /* + * Check link + */ + j = 0; + while (j < 100) { + status = qca8075_phy_reg_read(0, phy, 0x11); + if (status & (1 << 10)) + break; + mdelay(10); + j++; + } + /* + * Enable check + */ + qca8075_phy_mmd_write(0, phy, 7, 0x8029, 0x0000); + qca8075_phy_mmd_write(0, phy, 7, 0x8029, 0x0003); + /* + * Start traffic + */ + qca8075_phy_mmd_write(0, phy, 7, 0x8020, 0xa000); + mdelay(200); + /* + * check counter + */ + tx_counter_ok = qca8075_phy_mmd_read(0, phy, 7, 0x802e); + tx_counter_ok_high16 = qca8075_phy_mmd_read(0, phy, 7, 0x802d); + tx_counter_error = qca8075_phy_mmd_read(0, phy, 7, 0x802f); + rx_counter_ok = qca8075_phy_mmd_read(0, phy, 7, 0x802b); + rx_counter_ok_high16 = qca8075_phy_mmd_read(0, phy, 7, 0x802a); + rx_counter_error = qca8075_phy_mmd_read(0, phy, 7, 0x802c); + tx_ok = tx_counter_ok + (tx_counter_ok_high16 << 16); + rx_ok = rx_counter_ok + (rx_counter_ok_high16 << 16); + /* + * Success + */ + if((tx_ok == 0x3000) && (tx_counter_error == 0)) { + phy_t_status &= (~(1 << phy)); + } else { + phy_t_status |= (1 << phy); + } + /* + * Power down + */ + qca8075_phy_reg_write(0, phy, 0x0, 0x1840); + } + /* + * Reset 5-phy + */ + qca8075_phy_reg_write(0, 0x1f, 0x0, 0x9000); + /* + * Enable 5-phy loopback + */ + qca8075_phy_reg_write(0, 0x1f, 0x0, 0x4140); + /* + * check link + */ + j = 0; + while (j < 100) { + for (phy = 0; phy < 5; phy++) { + status = qca8075_phy_reg_read(0, phy, 0x11); + if (!(status & (1 << 10))) + break; + } + if (phy >= 5) + break; + mdelay(10); + j++; + } + /* + * Enable check + */ + qca8075_phy_mmd_write(0, 0x1f, 7, 0x8029, 0x0000); + qca8075_phy_mmd_write(0, 0x1f, 7, 0x8029, 0x0003); + /* + * Start traffic + */ + qca8075_phy_mmd_write(0, 0x1f, 7, 0x8020, 0xa000); + mdelay(200); + for (phy = 0; phy < 5; phy++) { + /* + * Check counter + */ + tx_counter_ok = qca8075_phy_mmd_read(0, phy, 7, 0x802e); + tx_counter_ok_high16 = qca8075_phy_mmd_read(0, phy, 7, 0x802d); + tx_counter_error = qca8075_phy_mmd_read(0, phy, 7, 0x802f); + rx_counter_ok = qca8075_phy_mmd_read(0, phy, 7, 0x802b); + rx_counter_ok_high16 = qca8075_phy_mmd_read(0, phy, 7, 0x802a); + rx_counter_error = qca8075_phy_mmd_read(0, phy, 7, 0x802c); + tx_ok = tx_counter_ok + (tx_counter_ok_high16 << 16); + rx_ok = rx_counter_ok + (rx_counter_ok_high16 << 16); + debug("rx_ok: %d, tx_ok: %d", rx_ok, tx_ok); + debug("rx_counter_error: %d, tx_counter_error: %d", + rx_counter_error, tx_counter_error); + /* + * Success + */ + if ((tx_ok == 0x3000) && (tx_counter_error == 0)) { + phy_t_status &= (~(1 << (phy + 8))); + } else { + phy_t_status |= (1 << (phy + 8)); + } + } + if (phy_t_status) { + qca8075_ess_reset(); + } else { + break; + } + } + /* + * Configuration recover + */ + /* + * Packet number + */ + qca8075_phy_mmd_write(0, 0x1f, 7, 0x8021, 0x0); + /* + * Disable check + */ + qca8075_phy_mmd_write(0, 0x1f, 7, 0x8029, 0x0); + /* + * Disable traffic + */ + qca8075_phy_mmd_write(0, 0x1f, 7, 0x8020, 0x0); +} + +void clear_self_test_config(void) +{ + int phy = 0; + u32 value = 0; + + /* + * Disable phy internal loopback + */ + qca8075_phy_reg_write(0, 0x1f, 0x10, 0x6860); + qca8075_phy_reg_write(0, 0x1f, 0x0, 0x9040); + + for (phy = 0; phy < 5; phy++) { + value = readl(0xc00066c + (phy * 0xc)); + /* + * Disable mac loop back + */ + writel((value&(~(1 << 21))), (0xc00066c + (phy * 0xc))); + /* + * Disable phy mdio broadcast writei + */ + qca8075_phy_mmd_write(0, phy, 7, 0x8028, 0x001f); + } + +} + + +void ipq_qca8075_dump_phy_regs(u32 phy_id) +{ + u16 phy_data; +#define REG_LEN 9 + u32 regs[REG_LEN] = { 0, 1, 2, 3, 4, 5, 6, 9, 10 }; + int i; + + for (i=0; i < REG_LEN; i++) { + phy_data = qca8075_phy_reg_read(0x0, phy_id, regs[i]); + printf("phy[%d] reg [%d] = 0x%x\n", phy_id, regs[i], phy_data); + } +#undef REG_LEN +} + +void ipq_qca8075_phy_map_ops(struct phy_ops **ops) +{ + *ops = qca8075_ops; +} + +void qca8075_phy_serdes_reset(u32 phy_id) +{ + qca8075_phy_reg_write(0, + phy_id + QCA8075_PHY_PSGMII_ADDR_INC, + QCA8075_MODE_RESET_REG, + QCA8075_MODE_CHANAGE_RESET); + mdelay(100); + qca8075_phy_reg_write(0, + phy_id + QCA8075_PHY_PSGMII_ADDR_INC, + QCA8075_MODE_RESET_REG, + QCA8075_MODE_RESET_DEFAULT_VALUE); + +} + +static u16 qca8075_phy_interface_get_mode(u32 phy_id) +{ + u16 phy_data; + + phy_data = qca8075_phy_reg_read(0, + phy_id + QCA8075_PHY_MAX_ADDR_INC, + QCA8075_PHY_CHIP_CONFIG); + phy_data &= 0x000f; + return phy_data; +} + +void qca8075_phy_interface_set_mode(u32 phy_id, u32 mode) +{ + u16 phy_data; + + phy_data = qca8075_phy_interface_get_mode(phy_id); + if (phy_data != mode) { + phy_data = qca8075_phy_reg_read(0, + phy_id + QCA8075_PHY_MAX_ADDR_INC, + QCA8075_PHY_CHIP_CONFIG); + phy_data &= 0xfff0; + qca8075_phy_reg_write(0, + phy_id + QCA8075_PHY_MAX_ADDR_INC, + QCA8075_PHY_CHIP_CONFIG, + phy_data | mode); + qca8075_phy_serdes_reset(0); + } +} + +int ipq_qca8075_phy_init(struct phy_ops **ops) +{ + u16 phy_data; + u32 phy_id = 0; + + qca8075_ops = (struct phy_ops *)malloc(sizeof(struct phy_ops)); + if (!qca8075_ops) + return -ENOMEM; + + qca8075_ops->phy_get_link_status = qca8075_phy_get_link_status; + qca8075_ops->phy_get_speed = qca8075_phy_get_speed; + qca8075_ops->phy_get_duplex = qca8075_phy_get_duplex; + *ops = qca8075_ops; + + qca8075_id = phy_data = qca8075_phy_reg_read(0x0, 0x0, QCA8075_PHY_ID1); + printf ("PHY ID1: 0x%x\n", phy_data); + phy_data = qca8075_phy_reg_read(0x0, 0x0, QCA8075_PHY_ID2); + printf ("PHY ID2: 0x%x\n", phy_data); + qca8075_id = (qca8075_id << 16) | phy_data; + + if (qca8075_id == QCA8075_PHY_V1_0_5P) { + phy_data = qca8075_phy_mmd_read(0, PSGMII_ID, + QCA8075_PHY_MMD1_NUM, QCA8075_PSGMII_FIFI_CTRL); + phy_data &= 0xbfff; + qca8075_phy_mmd_write(0, PSGMII_ID, QCA8075_PHY_MMD1_NUM, + QCA8075_PSGMII_FIFI_CTRL, phy_data); + } + + /* + * Enable phy power saving function by default + */ + if (qca8075_id == QCA8075_PHY_V1_1_2P) + phy_id = 3; + + if ((qca8075_id == QCA8075_PHY_V1_0_5P) || + (qca8075_id == QCA8075_PHY_V1_1_5P) || + (qca8075_id == QCA8075_PHY_V1_1_2P)) { + for (; phy_id < 5; phy_id++) { + /*enable phy power saving function by default */ + qca8075_phy_set_8023az(0x0, phy_id, 0x1); + qca8075_phy_set_powersave(0x0, phy_id, 0x1); + qca8075_phy_set_hibernate(0x0, phy_id, 0x1); + + /* + * change malibu control_dac[2:0] of MMD7 0x801A bit[9:7] + * from 111 to 101 + */ + phy_data = qca8075_phy_mmd_read(0, phy_id, + QCA8075_PHY_MMD7_NUM, QCA8075_PHY_MMD7_DAC_CTRL); + phy_data &= ~QCA8075_DAC_CTRL_MASK; + phy_data |= QCA8075_DAC_CTRL_VALUE; + qca8075_phy_mmd_write(0, phy_id, QCA8075_PHY_MMD7_NUM, + QCA8075_PHY_MMD7_DAC_CTRL, phy_data); + + /* add 10M and 100M link LED behavior for QFN board*/ + phy_data = qca8075_phy_mmd_read(0, phy_id, QCA8075_PHY_MMD7_NUM, + QCA8075_PHY_MMD7_LED_1000_CTRL1); + phy_data &= ~QCA8075_LED_1000_CTRL1_100_10_MASK; + phy_data |= QCA8075_LED_1000_CTRL1_100_10_MASK; + qca8075_phy_mmd_write(0 , phy_id, QCA8075_PHY_MMD7_NUM, + QCA8075_PHY_MMD7_LED_1000_CTRL1, phy_data); + } + } + + /* + * Enable AZ transmitting ability + */ + qca8075_phy_mmd_write(0, PSGMII_ID, QCA8075_PHY_MMD1_NUM, + QCA8075_PSGMII_MODE_CTRL, + QCA8075_PHY_PSGMII_MODE_CTRL_ADJUST_VALUE); + + /* adjust psgmii serdes tx amp */ + qca8075_phy_reg_write(0, 5, QCA8075_PSGMII_TX_DRIVER_1_CTRL, + QCA8075_PHY_PSGMII_REDUCE_SERDES_TX_AMP); + + /* to avoid psgmii module goes into hibernation, work with psgmii self test*/ + phy_data = qca8075_phy_mmd_read(0, 4, QCA8075_PHY_MMD3_NUM, 0x805a); + phy_data &= (~(1 << 1)); + qca8075_phy_mmd_write(0, 4, QCA8075_PHY_MMD3_NUM, 0x805a, phy_data); + + return 0; +} diff --git a/sources/uboot-be550/drivers/net/ipq_common/ipq_qca8075.h b/sources/uboot-be550/drivers/net/ipq_common/ipq_qca8075.h new file mode 100644 index 00000000..1b263268 --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq_common/ipq_qca8075.h @@ -0,0 +1,491 @@ +/* + * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. + + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. +*/ + +#ifndef _QCA8075_PHY_H_ +#define _QCA8075_PHY_H_ + +#define QCA8075_PHY_CONTROL 0 +#define QCA8075_PHY_STATUS 1 +#define QCA8075_PHY_ID1 2 +#define QCA8075_PHY_ID2 3 +#define QCA8075_AUTONEG_ADVERT 4 +#define QCA8075_LINK_PARTNER_ABILITY 5 +#define QCA8075_AUTONEG_EXPANSION 6 +#define QCA8075_NEXT_PAGE_TRANSMIT 7 +#define QCA8075_LINK_PARTNER_NEXT_PAGE 8 +#define QCA8075_1000BASET_CONTROL 9 +#define QCA8075_1000BASET_STATUS 10 +#define QCA8075_MMD_CTRL_REG 13 +#define QCA8075_MMD_DATA_REG 14 +#define QCA8075_EXTENDED_STATUS 15 +#define QCA8075_PHY_SPEC_CONTROL 16 +#define QCA8075_PHY_SPEC_STATUS 17 +#define QCA8075_PHY_INTR_MASK 18 +#define QCA8075_PHY_INTR_STATUS 19 +#define QCA8075_PHY_CDT_CONTROL 22 +#define QCA8075_PHY_CDT_STATUS 28 +#define QCA8075_DEBUG_PORT_ADDRESS 29 +#define QCA8075_DEBUG_PORT_DATA 30 +#define COMBO_PHY_ID 4 +#define PSGMII_ID 5 + +#define QCA8075_DEBUG_PHY_HIBERNATION_CTRL 0xb +#define QCA8075_DEBUG_PHY_POWER_SAVING_CTRL 0x29 +#define QCA8075_PHY_MMD7_ADDR_8023AZ_EEE_CTRL 0x3c +#define QCA8075_PHY_MMD3_ADDR_REMOTE_LOOPBACK_CTRL 0x805a +#define QCA8075_PHY_MMD3_WOL_MAGIC_MAC_CTRL1 0x804a +#define QCA8075_PHY_MMD3_WOL_MAGIC_MAC_CTRL2 0x804b +#define QCA8075_PHY_MMD3_WOL_MAGIC_MAC_CTRL3 0x804c +#define QCA8075_PHY_MMD3_WOL_CTRL 0x8012 + +#define QCA8075_PSGMII_FIFI_CTRL 0x6e +#define QCA8075_PSGMII_CALIB_CTRL 0x27 +#define QCA8075_PSGMII_MODE_CTRL 0x6d +#define QCA8075_PHY_PSGMII_MODE_CTRL_ADJUST_VALUE 0x220c + +#define QCA8075_PHY_MMD7_NUM 7 +#define QCA8075_PHY_MMD3_NUM 3 +#define QCA8075_PHY_MMD1_NUM 1 + +#define QCA8075_PHY_SGMII_STATUS 0x1a /* sgmii_status Register */ +#define QCA8075_PHY4_AUTO_SGMII_SELECT 0x40 +#define QCA8075_PHY4_AUTO_COPPER_SELECT 0x20 +#define QCA8075_PHY4_AUTO_BX1000_SELECT 0x10 +#define QCA8075_PHY4_AUTO_FX100_SELECT 0x8 + +#define QCA8075_MODE_RESET_REG 0x0 +#define QCA8075_MODE_CHANAGE_RESET 0x0 +#define QCA8075_MODE_RESET_DEFAULT_VALUE 0x5f +#define QCA8075_PHY_MAX_ADDR_INC 0x4 +#define QCA8075_PHY_PSGMII_ADDR_INC 0x5 + +#define QCA8075_PHY_CHIP_CONFIG 0x1f /* Chip Configuration Register */ +#define BT_BX_SG_REG_SELECT BIT_15 +#define BT_BX_SG_REG_SELECT_OFFSET 15 +#define BT_BX_SG_REG_SELECT_LEN 1 +#define QCA8075_SG_BX_PAGES 0x0 +#define QCA8075_SG_COPPER_PAGES 0x1 + +#define QCA8075_PHY_PSGMII_BASET 0x0 +#define QCA8075_PHY_PSGMII_BX1000 0x1 +#define QCA8075_PHY_PSGMII_FX100 0x2 +#define QCA8075_PHY_PSGMII_AMDET 0x3 +#define QCA8075_PHY_SGMII_BASET 0x4 + +#define QCA8075_PHY4_PREFER_FIBER 0x400 +#define PHY4_PREFER_COPPER 0x0 +#define PHY4_PREFER_FIBER 0x1 + +#define QCA8075_PHY4_FIBER_MODE_1000BX 0x100 +#define AUTO_100FX_FIBER 0x0 +#define AUTO_1000BX_FIBER 0x1 + +#define QCA8075_PHY_MDIX 0x0020 +#define QCA8075_PHY_MDIX_AUTO 0x0060 +#define QCA8075_PHY_MDIX_STATUS 0x0040 + +#define MODE_CFG_QUAL BIT_4 +#define MODE_CFG_QUAL_OFFSET 4 +#define MODE_CFG_QUAL_LEN 4 + +#define MODE_CFG BIT_0 +#define MODE_CFG_OFFSET 0 +#define MODE_CFG_LEN 4 + +#define QCA8075_PHY_MMD3_ADDR_8023AZ_CLD_CTRL 0x8007 +#define QCA8075_PHY_MMD3_ADDR_8023AZ_TIMER_CTRL 0x804e +#define QCA8075_PHY_MMD3_ADDR_CLD_CTRL5 0x8005 +#define QCA8075_PHY_MMD3_ADDR_CLD_CTRL3 0x8003 + +#define AZ_TIMER_CTRL_DEFAULT_VALUE 0x3062 +#define AZ_CLD_CTRL_DEFAULT_VALUE 0x83f6 +#define AZ_TIMER_CTRL_ADJUST_VALUE 0x7062 +#define AZ_CLD_CTRL_ADJUST_VALUE 0x8396 + + /*debug port */ +#define QCA8075_DEBUG_PORT_RGMII_MODE 18 +#define QCA8075_DEBUG_PORT_RGMII_MODE_EN 0x0008 + +#define QCA8075_DEBUG_PORT_RX_DELAY 0 +#define QCA8075_DEBUG_PORT_RX_DELAY_EN 0x8000 + +#define QCA8075_DEBUG_PORT_TX_DELAY 5 +#define QCA8075_DEBUG_PORT_TX_DELAY_EN 0x0100 + + /* PHY Registers Field */ + + /* Control Register fields offset:0 */ + /* bits 6,13: 10=1000, 01=100, 00=10 */ +#define QCA8075_CTRL_SPEED_MSB 0x0040 + + /* Collision test enable */ +#define QCA8075_CTRL_COLL_TEST_ENABLE 0x0080 + + /* FDX =1, half duplex =0 */ +#define QCA8075_CTRL_FULL_DUPLEX 0x0100 + + /* Restart auto negotiation */ +#define QCA8075_CTRL_RESTART_AUTONEGOTIATION 0x0200 + + /* Isolate PHY from MII */ +#define QCA8075_CTRL_ISOLATE 0x0400 + + /* Power down */ +#define QCA8075_CTRL_POWER_DOWN 0x0800 + + /* Auto Neg Enable */ +#define QCA8075_CTRL_AUTONEGOTIATION_ENABLE 0x1000 + + /* Local Loopback Enable */ +#define QCA8075_LOCAL_LOOPBACK_ENABLE 0x4000 + + /* bits 6,13: 10=1000, 01=100, 00=10 */ +#define QCA8075_CTRL_SPEED_LSB 0x2000 + + /* 0 = normal, 1 = loopback */ +#define QCA8075_CTRL_LOOPBACK 0x4000 +#define QCA8075_CTRL_SOFTWARE_RESET 0x8000 + +#define QCA8075_CTRL_SPEED_MASK 0x2040 +#define QCA8075_CTRL_SPEED_1000 0x0040 +#define QCA8075_CTRL_SPEED_100 0x2000 +#define QCA8075_CTRL_SPEED_10 0x0000 + +#define QCA8075_RESET_DONE(phy_control) \ + (((phy_control) & (QCA8075_CTRL_SOFTWARE_RESET)) == 0) + + /* Status Register fields offset:1 */ + /* Extended register capabilities */ +#define QCA8075_STATUS_EXTENDED_CAPS 0x0001 + + /* Jabber Detected */ +#define QCA8075_STATUS_JABBER_DETECT 0x0002 + + /* Link Status 1 = link */ +#define QCA8075_STATUS_LINK_STATUS_UP 0x0004 + + /* Auto Neg Capable */ +#define QCA8075_STATUS_AUTONEG_CAPS 0x0008 + + /* Remote Fault Detect */ +#define QCA8075_STATUS_REMOTE_FAULT 0x0010 + + /* Auto Neg Complete */ +#define QCA8075_STATUS_AUTO_NEG_DONE 0x0020 + + /* Preamble may be suppressed */ +#define QCA8075_STATUS_PREAMBLE_SUPPRESS 0x0040 + + /* Ext. status info in Reg 0x0F */ +#define QCA8075_STATUS_EXTENDED_STATUS 0x0100 + + /* 100T2 Half Duplex Capable */ +#define QCA8075_STATUS_100T2_HD_CAPS 0x0200 + + /* 100T2 Full Duplex Capable */ +#define QCA8075_STATUS_100T2_FD_CAPS 0x0400 + + /* 10T Half Duplex Capable */ +#define QCA8075_STATUS_10T_HD_CAPS 0x0800 + + /* 10T Full Duplex Capable */ +#define QCA8075_STATUS_10T_FD_CAPS 0x1000 + + /* 100X Half Duplex Capable */ +#define QCA8075_STATUS_100X_HD_CAPS 0x2000 + + /* 100X Full Duplex Capable */ +#define QCA8075_STATUS_100X_FD_CAPS 0x4000 + + /* 100T4 Capable */ +#define QCA8075_STATUS_100T4_CAPS 0x8000 + + /* extended status register capabilities */ + +#define QCA8075_STATUS_1000T_HD_CAPS 0x1000 + +#define QCA8075_STATUS_1000T_FD_CAPS 0x2000 + +#define QCA8075_STATUS_1000X_HD_CAPS 0x4000 + +#define QCA8075_STATUS_1000X_FD_CAPS 0x8000 + +#define QCA8075_AUTONEG_DONE(ip_phy_status) \ + (((ip_phy_status) & (QCA8075_STATUS_AUTO_NEG_DONE)) == \ + (QCA8075_STATUS_AUTO_NEG_DONE)) + + /* PHY identifier1 offset:2 */ +//Organizationally Unique Identifier bits 3:18 + + /* PHY identifier2 offset:3 */ +//Organizationally Unique Identifier bits 19:24 + + /* Auto-Negotiation Advertisement register. offset:4 */ + /* indicates IEEE 802.3 CSMA/CD */ +#define QCA8075_ADVERTISE_SELECTOR_FIELD 0x0001 + + /* 10T Half Duplex Capable */ +#define QCA8075_ADVERTISE_10HALF 0x0020 + + /* 10T Full Duplex Capable */ +#define QCA8075_ADVERTISE_10FULL 0x0040 + + /* 100TX Half Duplex Capable */ +#define QCA8075_ADVERTISE_100HALF 0x0080 + + /* 100TX Full Duplex Capable */ +#define QCA8075_ADVERTISE_100FULL 0x0100 + + /* 100T4 Capable */ +#define QCA8075_ADVERTISE_100T4 0x0200 + + /* Pause operation desired */ +#define QCA8075_ADVERTISE_PAUSE 0x0400 + + /* Asymmetric Pause Direction bit */ +#define QCA8075_ADVERTISE_ASYM_PAUSE 0x0800 + + /* Remote Fault detected */ +#define QCA8075_ADVERTISE_REMOTE_FAULT 0x2000 + + /* Next Page ability supported */ +#define QCA8075_ADVERTISE_NEXT_PAGE 0x8000 + + /* 100TX Half Duplex Capable */ +#define QCA8075_ADVERTISE_1000HALF 0x0100 + + /* 100TX Full Duplex Capable */ +#define QCA8075_ADVERTISE_1000FULL 0x0200 + +#define QCA8075_ADVERTISE_ALL \ + (QCA8075_ADVERTISE_10HALF | QCA8075_ADVERTISE_10FULL | \ + QCA8075_ADVERTISE_100HALF | QCA8075_ADVERTISE_100FULL | \ + QCA8075_ADVERTISE_1000FULL) + +#define QCA8075_ADVERTISE_MEGA_ALL \ + (QCA8075_ADVERTISE_10HALF | QCA8075_ADVERTISE_10FULL | \ + QCA8075_ADVERTISE_100HALF | QCA8075_ADVERTISE_100FULL) + +#define QCA8075_BX_ADVERTISE_1000FULL 0x0020 +#define QCA8075_BX_ADVERTISE_1000HALF 0x0040 +#define QCA8075_BX_ADVERTISE_PAUSE 0x0080 +#define QCA8075_BX_ADVERTISE_ASYM_PAUSE 0x0100 + +#define QCA8075_BX_ADVERTISE_ALL \ + (QCA8075_BX_ADVERTISE_ASYM_PAUSE | QCA8075_BX_ADVERTISE_PAUSE | \ + QCA8075_BX_ADVERTISE_1000HALF | QCA8075_BX_ADVERTISE_1000FULL) + + /* Link Partner ability offset:5 */ + /* Same as advertise selector */ +#define QCA8075_LINK_SLCT 0x001f + + /* Can do 10mbps half-duplex */ +#define QCA8075_LINK_10BASETX_HALF_DUPLEX 0x0020 + + /* Can do 10mbps full-duplex */ +#define QCA8075_LINK_10BASETX_FULL_DUPLEX 0x0040 + + /* Can do 100mbps half-duplex */ +#define QCA8075_LINK_100BASETX_HALF_DUPLEX 0x0080 + + /* Can do 100mbps full-duplex */ +#define QCA8075_LINK_100BASETX_FULL_DUPLEX 0x0100 + + /* Can do 1000mbps full-duplex */ +#define QCA8075_LINK_1000BASETX_FULL_DUPLEX 0x0800 + + /* Can do 1000mbps half-duplex */ +#define QCA8075_LINK_1000BASETX_HALF_DUPLEX 0x0400 + + /* 100BASE-T4 */ +#define QCA8075_LINK_100BASE4 0x0200 + + /* PAUSE */ +#define QCA8075_LINK_PAUSE 0x0400 + + /* Asymmetrical PAUSE */ +#define QCA8075_LINK_ASYPAUSE 0x0800 + + /* Link partner faulted */ +#define QCA8075_LINK_RFAULT 0x2000 + + /* Link partner acked us */ +#define QCA8075_LINK_LPACK 0x4000 + + /* Next page bit */ +#define QCA8075_LINK_NPAGE 0x8000 + + /* Auto-Negotiation Expansion Register offset:6 */ + + /* Next Page Transmit Register offset:7 */ + + /* Link partner Next Page Register offset:8 */ + + /* 1000BASE-T Control Register offset:9 */ + /* Advertise 1000T HD capability */ +#define QCA8075_CTL_1000T_HD_CAPS 0x0100 + + /* Advertise 1000T FD capability */ +#define QCA8075_CTL_1000T_FD_CAPS 0x0200 + + /* 1=Repeater/switch device port 0=DTE device */ +#define QCA8075_CTL_1000T_REPEATER_DTE 0x0400 + + /* 1=Configure PHY as Master 0=Configure PHY as Slave */ +#define QCA8075_CTL_1000T_MS_VALUE 0x0800 + + /* 1=Master/Slave manual config value 0=Automatic Master/Slave config */ +#define QCA8075_CTL_1000T_MS_ENABLE 0x1000 + + /* Normal Operation */ +#define QCA8075_CTL_1000T_TEST_MODE_NORMAL 0x0000 + + /* Transmit Waveform test */ +#define QCA8075_CTL_1000T_TEST_MODE_1 0x2000 + + /* Master Transmit Jitter test */ +#define QCA8075_CTL_1000T_TEST_MODE_2 0x4000 + + /* Slave Transmit Jitter test */ +#define QCA8075_CTL_1000T_TEST_MODE_3 0x6000 + + /* Transmitter Distortion test */ +#define QCA8075_CTL_1000T_TEST_MODE_4 0x8000 +#define QCA8075_CTL_1000T_SPEED_MASK 0x0300 +#define QCA8075_CTL_1000T_DEFAULT_CAP_MASK 0x0300 + + /* 1000BASE-T Status Register offset:10 */ + /* LP is 1000T HD capable */ +#define QCA8075_STATUS_1000T_LP_HD_CAPS 0x0400 + + /* LP is 1000T FD capable */ +#define QCA8075_STATUS_1000T_LP_FD_CAPS 0x0800 + + /* Remote receiver OK */ +#define QCA8075_STATUS_1000T_REMOTE_RX_STATUS 0x1000 + + /* Local receiver OK */ +#define QCA8075_STATUS_1000T_LOCAL_RX_STATUS 0x2000 + + /* 1=Local TX is Master, 0=Slave */ +#define QCA8075_STATUS_1000T_MS_CONFIG_RES 0x4000 + +#define QCA8075_STATUS_1000T_MS_CONFIG_FAULT 0x8000 + + /* Master/Slave config fault */ +#define QCA8075_STATUS_1000T_REMOTE_RX_STATUS_SHIFT 12 +#define QCA8075_STATUS_1000T_LOCAL_RX_STATUS_SHIFT 13 + + /* Phy Specific Control Register offset:16 */ + /* 1=Jabber Function disabled */ +#define QCA8075_CTL_JABBER_DISABLE 0x0001 + + /* 1=Polarity Reversal enabled */ +#define QCA8075_CTL_POLARITY_REVERSAL 0x0002 + + /* 1=SQE Test enabled */ +#define QCA8075_CTL_SQE_TEST 0x0004 +#define QCA8075_CTL_MAC_POWERDOWN 0x0008 + + /* 1=CLK125 low, 0=CLK125 toggling + #define QCA8075_CTL_CLK125_DISABLE 0x0010 + */ + /* MDI Crossover Mode bits 6:5 */ + /* Manual MDI configuration */ +#define QCA8075_CTL_MDI_MANUAL_MODE 0x0000 + + /* Manual MDIX configuration */ +#define QCA8075_CTL_MDIX_MANUAL_MODE 0x0020 + + /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */ +#define QCA8075_CTL_AUTO_X_1000T 0x0040 + + /* Auto crossover enabled all speeds */ +#define QCA8075_CTL_AUTO_X_MODE 0x0060 + + /* 1=Enable Extended 10BASE-T distance + * (Lower 10BASE-T RX Threshold) + * 0=Normal 10BASE-T RX Threshold */ +#define QCA8075_CTL_10BT_EXT_DIST_ENABLE 0x0080 + + /* 1=5-Bit interface in 100BASE-TX + * 0=MII interface in 100BASE-TX */ +#define QCA8075_CTL_MII_5BIT_ENABLE 0x0100 + + /* 1=Scrambler disable */ +#define QCA8075_CTL_SCRAMBLER_DISABLE 0x0200 + + /* 1=Force link good */ +#define QCA8075_CTL_FORCE_LINK_GOOD 0x0400 + + /* 1=Assert CRS on Transmit */ +#define QCA8075_CTL_ASSERT_CRS_ON_TX 0x0800 + +#define QCA8075_CTL_POLARITY_REVERSAL_SHIFT 1 +#define QCA8075_CTL_AUTO_X_MODE_SHIFT 5 +#define QCA8075_CTL_10BT_EXT_DIST_ENABLE_SHIFT 7 + + + /* Phy Specific status fields offset:17 */ + /* 1=Speed & Duplex resolved */ +#define QCA8075_STATUS_LINK_PASS 0x0400 +#define QCA8075_STATUS_RESOVLED 0x0800 + + /* 1=Duplex 0=Half Duplex */ +#define QCA8075_STATUS_FULL_DUPLEX 0x2000 + + /* Speed, bits 14:15 */ +#define QCA8075_STATUS_SPEED 0xC000 +#define QCA8075_STATUS_SPEED_MASK 0xC000 + + /* 00=10Mbs */ +#define QCA8075_STATUS_SPEED_10MBS 0x0000 + + /* 01=100Mbs */ +#define QCA8075_STATUS_SPEED_100MBS 0x4000 + + /* 10=1000Mbs */ +#define QCA8075_STATUS_SPEED_1000MBS 0x8000 +#define QCA8075_SPEED_DUPLEX_RESOVLED(phy_status) \ + (((phy_status) & \ + (QCA8075_STATUS_RESOVLED)) == \ + (QCA8075_STATUS_RESOVLED)) + + /*phy debug port1 register offset:29 */ + /*phy debug port2 register offset:30 */ + + /*QCA8075 interrupt flag */ +#define QCA8075_INTR_SPEED_CHANGE 0x4000 +#define QCA8075_INTR_DUPLEX_CHANGE 0x2000 +#define QCA8075_INTR_STATUS_UP_CHANGE 0x0400 +#define QCA8075_INTR_STATUS_DOWN_CHANGE 0x0800 +#define QCA8075_INTR_BX_FX_STATUS_DOWN_CHANGE 0x0100 +#define QCA8075_INTR_BX_FX_STATUS_UP_CHANGE 0x0080 +#define QCA8075_INTR_MEDIA_STATUS_CHANGE 0x1000 +#define QCA8075_INTR_WOL 0x0001 +#define QCA8075_INTR_POE 0x0002 + +#define QCA8075_PHY_PSGMII_REDUCE_SERDES_TX_AMP 0x8a +#define QCA8075_DAC_CTRL_MASK 0x380 +#define QCA8075_PHY_MMD7_DAC_CTRL 0x801a +#define QCA8075_DAC_CTRL_VALUE 0x280 +#define QCA8075_PHY_MMD7_NUM 7 +#define QCA8075_PSGMII_TX_DRIVER_1_CTRL 0xb +#define QCA8075_PHY_MMD7_LED_1000_CTRL1 0x8076 +#define QCA8075_LED_1000_CTRL1_100_10_MASK 0x30 + +#define RUN_CDT 0x8000 +#define CABLE_LENGTH_UNIT 0x0400 +#define QCA8075_MAX_TRIES 100 + +#endif /* _QCA8075_PHY_H_ */ diff --git a/sources/uboot-be550/drivers/net/ipq_common/ipq_qca8081.c b/sources/uboot-be550/drivers/net/ipq_common/ipq_qca8081.c new file mode 100644 index 00000000..0fe92f6d --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq_common/ipq_qca8081.c @@ -0,0 +1,123 @@ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. +*/ +#include +#include +#include +#include +#include +#include +#include "ipq_qca8081.h" +#include "ipq_phy.h" + +extern int ipq_mdio_read(int mii_id, + int regnum, ushort *data); +extern int ipq_mdio_write(int mii_id, + int regnum, u16 data); + +u16 qca8081_phy_reg_read(u32 dev_id, u32 phy_id, u32 reg_id) +{ + return ipq_mdio_read(phy_id, reg_id, NULL); +} + +u16 qca8081_phy_reg_write(u32 dev_id, u32 phy_id, u32 reg_id, u16 value) +{ + return ipq_mdio_write(phy_id, reg_id, value); +} + +u8 qca8081_phy_get_link_status(u32 dev_id, u32 phy_id) +{ + u16 phy_data; + phy_data = qca8081_phy_reg_read(dev_id, + phy_id, QCA8081_PHY_SPEC_STATUS); + if (phy_data & QCA8081_STATUS_LINK_PASS) + return 0; + + return 1; +} + +u32 qca8081_phy_get_duplex(u32 dev_id, u32 phy_id, fal_port_duplex_t *duplex) +{ + u16 phy_data; + + phy_data = qca8081_phy_reg_read(dev_id, phy_id, + QCA8081_PHY_SPEC_STATUS); + + /* + * Read duplex + */ + if (phy_data & QCA8081_STATUS_FULL_DUPLEX) + *duplex = FAL_FULL_DUPLEX; + else + *duplex = FAL_HALF_DUPLEX; + + return 0; +} + +u32 qca8081_phy_get_speed(u32 dev_id, u32 phy_id, fal_port_speed_t *speed) +{ + u16 phy_data; + + phy_data = qca8081_phy_reg_read(dev_id, + phy_id, QCA8081_PHY_SPEC_STATUS); + + switch (phy_data & QCA8081_STATUS_SPEED_MASK) { + case QCA8081_STATUS_SPEED_2500MBS: + *speed = FAL_SPEED_2500; + break; + case QCA8081_STATUS_SPEED_1000MBS: + *speed = FAL_SPEED_1000; + break; + case QCA8081_STATUS_SPEED_100MBS: + *speed = FAL_SPEED_100; + break; + case QCA8081_STATUS_SPEED_10MBS: + *speed = FAL_SPEED_10; + break; + default: + return -EINVAL; + } + return 0; +} + +int ipq_qca8081_phy_init(struct phy_ops **ops, u32 phy_id) +{ + u16 phy_data; + struct phy_ops *qca8081_ops; + + qca8081_ops = (struct phy_ops *)malloc(sizeof(struct phy_ops)); + if (!qca8081_ops) + return -ENOMEM; + qca8081_ops->phy_get_link_status = qca8081_phy_get_link_status; + qca8081_ops->phy_get_speed = qca8081_phy_get_speed; + qca8081_ops->phy_get_duplex = qca8081_phy_get_duplex; + *ops = qca8081_ops; + + phy_data = qca8081_phy_reg_read(0x0, phy_id, QCA8081_PHY_ID1); + printf ("PHY ID1: 0x%x\n", phy_data); + phy_data = qca8081_phy_reg_read(0x0, phy_id, QCA8081_PHY_ID2); + printf ("PHY ID2: 0x%x\n", phy_data); + + /*enable vga when init napa to fix 8023az issue*/ + phy_data = qca8081_phy_reg_read(0x0, phy_id, QCA808X_8023AZ_ENABLE_VGA); + phy_data &= (~QCA808X_PHY_8023AZ_AFE_CTRL_MASK); + phy_data |= QCA808X_PHY_8023AZ_AFE_EN; + phy_data = qca8081_phy_reg_write(0x0, phy_id, QCA808X_8023AZ_ENABLE_VGA, phy_data); + if (phy_data != 0) + return phy_data; + + /*special configuration for AZ under 1G speed mode*/ + phy_data = QCA808X_PHY_MMD3_AZ_TRAINING_VAL; + phy_data = qca8081_phy_reg_write(0x0, phy_id, QCA808X_AZ_CONFIG_UNDER_1G_SPEED, + phy_data); + return phy_data; +} diff --git a/sources/uboot-be550/drivers/net/ipq_common/ipq_qca8081.h b/sources/uboot-be550/drivers/net/ipq_common/ipq_qca8081.h new file mode 100644 index 00000000..a2a6228c --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq_common/ipq_qca8081.h @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. +*/ + +#ifndef _QCA8081_PHY_H_ +#define _QCA8081_PHY_H_ + +/* PHY Registers */ +#define QCA8081_PHY_CONTROL 0 +#define QCA8081_PHY_STATUS 1 +#define QCA8081_PHY_SPEC_STATUS 17 + +#define QCA8081_PHY_ID1 2 +#define QCA8081_PHY_ID2 3 +#define QCA8081_AUTONEG_ADVERT 4 +#define QCA8081_LINK_PARTNER_ABILITY 5 +#define QCA8081_1000BASET_CONTROL 9 +#define QCA8081_1000BASET_STATUS 10 +#define QCA8081_MMD_CTRL_REG 13 +#define QCA8081_MMD_DATA_REG 14 +#define QCA8081_EXTENDED_STATUS 15 +#define QCA8081_PHY_SPEC_CONTROL 16 +#define QCA8081_PHY_INTR_MASK 18 +#define QCA8081_PHY_INTR_STATUS 19 +#define QCA8081_PHY_CDT_CONTROL 22 +#define QCA8081_DEBUG_PORT_ADDRESS 29 +#define QCA8081_DEBUG_PORT_DATA 30 + +#define QCA8081_STATUS_LINK_PASS 0x0400 + +#define QCA8081_STATUS_FULL_DUPLEX 0x2000 + +#define QCA8081_STATUS_SPEED_MASK 0x380 +#define QCA8081_STATUS_SPEED_2500MBS 0x200 +#define QCA8081_STATUS_SPEED_1000MBS 0x100 +#define QCA8081_STATUS_SPEED_100MBS 0x80 +#define QCA8081_STATUS_SPEED_10MBS 0x0000 + +#define QCA808X_PHY_MMD3_AZ_TRAINING_VAL 0x1c32 +#define QCA808X_PHY_MMD3_NUM 3 +#define QCA808X_PHY_MMD3_ADDR_CLD_CTRL7 0x8007 +#define QCA808X_PHY_MMD3_AZ_TRAINING_CTRL 0x8008 +#define QCA808X_PHY_8023AZ_AFE_CTRL_MASK 0x01f0 +#define QCA808X_PHY_8023AZ_AFE_EN 0x0090 +#define QCA808X_MII_ADDR_C45 (1<<30) +#define QCA808X_REG_C45_ADDRESS(dev_type, reg_num) (QCA808X_MII_ADDR_C45 | \ + ((dev_type & 0x1f) << 16) | (reg_num & 0xffff)) +#define QCA808X_8023AZ_ENABLE_VGA QCA808X_REG_C45_ADDRESS(QCA808X_PHY_MMD3_NUM, \ + QCA808X_PHY_MMD3_ADDR_CLD_CTRL7) +#define QCA808X_AZ_CONFIG_UNDER_1G_SPEED QCA808X_REG_C45_ADDRESS(QCA808X_PHY_MMD3_NUM, \ + QCA808X_PHY_MMD3_AZ_TRAINING_CTRL) + +#endif /* _QCA8081_PHY_H_ */ diff --git a/sources/uboot-be550/drivers/net/ipq_common/ipq_qca8084.c b/sources/uboot-be550/drivers/net/ipq_common/ipq_qca8084.c new file mode 100644 index 00000000..a3710905 --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq_common/ipq_qca8084.c @@ -0,0 +1,1594 @@ +/* + * Copyright (c) 2022, The Linux Foundation. All rights reserved. + + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. +*/ +#include "ipq_phy.h" +#include "ipq_qca8081.h" +#include "ipq_qca8084.h" +#include "ipq_qca8084_clk.h" +#include "ipq_qca8084_interface_ctrl.h" +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; +#ifdef DEBUG +#define pr_debug(fmt, args...) printf(fmt, ##args); +#else +#define pr_debug(fmt, args...) +#endif + +extern uint32_t ipq_mii_read(uint32_t reg); +extern void ipq_mii_write(uint32_t reg, uint32_t val); +extern int ipq_mdio_read(int mii_id, + int regnum, ushort *data); +extern int ipq_mdio_write(int mii_id, + int regnum, u16 data); +extern void qca8084_gcc_clock_init(qca8084_work_mode_t clk_mode, u32 pbmp); +extern void qca8084_port_speed_clock_set(uint32_t qca8084_port_id, + fal_port_speed_t speed); +extern void qca8084_port_clk_en_set(uint32_t qca8084_port_id, uint8_t mask, + uint8_t enable); +extern void qca8084_port_clk_reset(uint32_t qca8084_port_id, uint8_t mask); + +extern u8 qca8081_phy_get_link_status(u32 dev_id, u32 phy_id); +extern u32 qca8081_phy_get_duplex(u32 dev_id, u32 phy_id, fal_port_duplex_t *duplex); +extern u32 qca8081_phy_get_speed(u32 dev_id, u32 phy_id, fal_port_speed_t *speed); + +#ifdef CONFIG_QCA8084_PHY_MODE +extern void qca8084_uniphy_xpcs_autoneg_restart(uint32_t qca8084_port_id); +extern void qca8084_uniphy_xpcs_speed_set(uint32_t qca8084_port_id, + fal_port_speed_t speed); +extern void qca8084_interface_uqxgmii_mode_set(void); +extern void qca8084_uniphy_uqxgmii_function_reset(uint32_t qca8084_port_id); +#endif /* CONFIG_QCA8084_PHY_MODE */ + +#ifdef CONFIG_QCA8084_SWT_MODE +extern void qca8084_gcc_port_clk_parent_set(qca8084_work_mode_t clk_mode, + uint32_t qca8084_port_id); +extern void qca8084_uniphy_sgmii_function_reset(u32 uniphy_index); +extern void qca8084_interface_sgmii_mode_set(u32 uniphy_index, u32 + qca8084_port_id, mac_config_t *config); +extern uint8_t qca8084_uniphy_mode_check(uint32_t uniphy_index, + qca8084_uniphy_mode_t uniphy_mode); +extern void qca8084_clk_disable(const char *clock_id); +extern void qca8084_clk_reset(const char *clock_id); + +bool qca8084_port_txfc_forcemode[QCA8084_MAX_PORTS] = {}; +bool qca8084_port_rxfc_forcemode[QCA8084_MAX_PORTS] = {}; +#endif /* CONFIG_QCA8084_SWT_MODE */ + +#ifdef CONFIG_QCA8084_BYPASS_MODE +extern void qca8084_phy_sgmii_mode_set(uint32_t phy_addr, u32 interface_mode, + u32 link, fal_port_speed_t speed); +#endif /* CONFIG_QCA8084_BYPASS_MODE */ + +static int qca8084_reg_field_get(u32 reg_addr, u32 bit_offset, + u32 field_len, u8 value[]); +static int qca8084_reg_field_set(u32 reg_addr, u32 bit_offset, + u32 field_len, const u8 value[]); + +u16 qca8084_phy_reg_read(u32 phy_addr, u32 reg_id) +{ + return ipq_mdio_read(phy_addr, reg_id, NULL); +} + +u16 qca8084_phy_reg_write(u32 phy_addr, u32 reg_id, u16 value) +{ + return ipq_mdio_write(phy_addr, reg_id, value); +} + +u16 qca8084_phy_mmd_read(u32 phy_addr, u16 mmd_num, u16 reg_id) +{ + uint32_t reg_id_c45 = QCA8084_REG_C45_ADDRESS(mmd_num, reg_id); + + return ipq_mdio_read(phy_addr, reg_id_c45, NULL); +} + +u16 qca8084_phy_mmd_write(u32 phy_addr, u16 mmd_num, u16 reg_id, u16 value) +{ + uint32_t reg_id_c45 = QCA8084_REG_C45_ADDRESS(mmd_num, reg_id); + + return ipq_mdio_write(phy_addr, reg_id_c45, value); +} + +void qca8084_phy_modify_mii(uint32_t phy_addr, uint32_t mii_reg, uint32_t mask, + uint32_t value) +{ + uint16_t phy_data = 0, new_phy_data = 0; + + phy_data = qca8084_phy_reg_read(phy_addr, mii_reg); + new_phy_data = (phy_data & ~mask) | value; + qca8084_phy_reg_write(phy_addr, mii_reg, new_phy_data); + /*check the mii register value*/ + phy_data = qca8084_phy_reg_read(phy_addr, mii_reg); + pr_debug("phy_addr:0x%x, mii_reg:0x%x, phy_data:0x%x\n", + phy_addr, mii_reg, phy_data); +} + +void qca8084_phy_modify_mmd(uint32_t phy_addr, uint32_t mmd_num, + uint32_t mmd_reg, uint32_t mask, uint32_t value) +{ + uint16_t phy_data = 0, new_phy_data = 0; + + phy_data = qca8084_phy_mmd_read(phy_addr, mmd_num, mmd_reg); + new_phy_data = (phy_data & ~mask) | value; + qca8084_phy_mmd_write(phy_addr, mmd_num, mmd_reg, new_phy_data); + /* check the mmd register value */ + phy_data = qca8084_phy_mmd_read(phy_addr, mmd_num, mmd_reg); + pr_debug("phy_addr:0x%x, mmd_reg:0x%x, phy_data:0x%x\n", + phy_addr, mmd_reg, phy_data); +} + +void qca8084_phy_function_reset(uint32_t phy_id) +{ + uint16_t phy_data = 0; + + phy_data = qca8084_phy_reg_read(phy_id, QCA8084_PHY_FIFO_CONTROL); + + qca8084_phy_reg_write(phy_id, QCA8084_PHY_FIFO_CONTROL, + phy_data & (~QCA8084_PHY_FIFO_RESET)); + + mdelay(50); + + qca8084_phy_reg_write(phy_id, QCA8084_PHY_FIFO_CONTROL, + phy_data | QCA8084_PHY_FIFO_RESET); +} + +/***************************** QCA8084 Pinctrl APIs *************************/ +/**************************************************************************** + * + * 1) PINs default Setting + * + ****************************************************************************/ +#ifdef IN_PINCTRL_DEF_CONFIG +static u64 pin_configs[] = { + QCA8084_PIN_CONFIG_OUTPUT_ENABLE, + QCA8084_PIN_CONFIG_BIAS_PULL_DOWN, +}; +#endif + +static struct qca8084_pinctrl_setting qca8084_pin_settings[] = { + /*PINs default MUX Setting*/ + QCA8084_PIN_SETTING_MUX(0, QCA8084_PIN_FUNC_INTN_WOL), + QCA8084_PIN_SETTING_MUX(1, QCA8084_PIN_FUNC_INTN), + QCA8084_PIN_SETTING_MUX(2, QCA8084_PIN_FUNC_P0_LED_0), + QCA8084_PIN_SETTING_MUX(3, QCA8084_PIN_FUNC_P1_LED_0), + QCA8084_PIN_SETTING_MUX(4, QCA8084_PIN_FUNC_P2_LED_0), + QCA8084_PIN_SETTING_MUX(5, QCA8084_PIN_FUNC_P3_LED_0), + QCA8084_PIN_SETTING_MUX(6, QCA8084_PIN_FUNC_PPS_IN), + QCA8084_PIN_SETTING_MUX(7, QCA8084_PIN_FUNC_TOD_IN), + QCA8084_PIN_SETTING_MUX(8, QCA8084_PIN_FUNC_RTC_REFCLK_IN), + QCA8084_PIN_SETTING_MUX(9, QCA8084_PIN_FUNC_P0_PPS_OUT), + QCA8084_PIN_SETTING_MUX(10, QCA8084_PIN_FUNC_P1_PPS_OUT), + QCA8084_PIN_SETTING_MUX(11, QCA8084_PIN_FUNC_P2_PPS_OUT), + QCA8084_PIN_SETTING_MUX(12, QCA8084_PIN_FUNC_P3_PPS_OUT), + QCA8084_PIN_SETTING_MUX(13, QCA8084_PIN_FUNC_P0_TOD_OUT), + QCA8084_PIN_SETTING_MUX(14, QCA8084_PIN_FUNC_P0_CLK125_TDI), + QCA8084_PIN_SETTING_MUX(15, QCA8084_PIN_FUNC_P0_SYNC_CLKO_PTP), + QCA8084_PIN_SETTING_MUX(16, QCA8084_PIN_FUNC_P0_LED_1), + QCA8084_PIN_SETTING_MUX(17, QCA8084_PIN_FUNC_P1_LED_1), + QCA8084_PIN_SETTING_MUX(18, QCA8084_PIN_FUNC_P2_LED_1), + QCA8084_PIN_SETTING_MUX(19, QCA8084_PIN_FUNC_P3_LED_1), + QCA8084_PIN_SETTING_MUX(20, QCA8084_PIN_FUNC_MDC_M), + QCA8084_PIN_SETTING_MUX(21, QCA8084_PIN_FUNC_MDC_M), + +#ifdef IN_PINCTRL_DEF_CONFIG + /*PINs default Config Setting*/ + QCA8084_PIN_SETTING_CONFIG(0, pin_configs), + QCA8084_PIN_SETTING_CONFIG(1, pin_configs), + QCA8084_PIN_SETTING_CONFIG(2, pin_configs), + QCA8084_PIN_SETTING_CONFIG(3, pin_configs), + QCA8084_PIN_SETTING_CONFIG(4, pin_configs), + QCA8084_PIN_SETTING_CONFIG(5, pin_configs), + QCA8084_PIN_SETTING_CONFIG(6, pin_configs), + QCA8084_PIN_SETTING_CONFIG(7, pin_configs), + QCA8084_PIN_SETTING_CONFIG(8, pin_configs), + QCA8084_PIN_SETTING_CONFIG(9, pin_configs), + QCA8084_PIN_SETTING_CONFIG(10, pin_configs), + QCA8084_PIN_SETTING_CONFIG(11, pin_configs), + QCA8084_PIN_SETTING_CONFIG(12, pin_configs), + QCA8084_PIN_SETTING_CONFIG(13, pin_configs), + QCA8084_PIN_SETTING_CONFIG(14, pin_configs), + QCA8084_PIN_SETTING_CONFIG(15, pin_configs), + QCA8084_PIN_SETTING_CONFIG(16, pin_configs), + QCA8084_PIN_SETTING_CONFIG(17, pin_configs), + QCA8084_PIN_SETTING_CONFIG(18, pin_configs), + QCA8084_PIN_SETTING_CONFIG(19, pin_configs), + QCA8084_PIN_SETTING_CONFIG(20, pin_configs), + QCA8084_PIN_SETTING_CONFIG(21, pin_configs), +#endif +}; + +/**************************************************************************** + * + * 2) PINs Operations + * + ****************************************************************************/ +int qca8084_gpio_set_bit(u32 pin, u32 value) +{ + int rv = 0; + + QCA8084_REG_FIELD_SET(TLMM_GPIO_IN_OUTN, pin, GPIO_OUTE, (u8 *) (&value)); + pr_debug("[%s] select pin:%d value:%d\n", __func__, pin, value); + + return rv; +} + +int qca8084_gpio_get_bit(u32 pin, u32 *data) +{ + int rv = 0; + + QCA8084_REG_FIELD_GET(TLMM_GPIO_IN_OUTN, pin, GPIO_IN, (u8 *) (data)); + pr_debug("[%s] select pin:%d value:%d\n", __func__, pin, *data); + + return rv; +} + +int qca8084_gpio_pin_mux_set(u32 pin, u32 func) +{ + int rv = 0; + + pr_debug("[%s] select pin:%d func:%d\n", __func__, pin, func); + QCA8084_REG_FIELD_SET(TLMM_GPIO_CFGN, pin, FUNC_SEL, (u8 *) (&func)); + + return rv; +} + +int qca8084_gpio_pin_cfg_set_bias(u32 pin, enum qca8084_pin_config_param bias) +{ + int rv = 0; + u32 data = 0; + + switch (bias) + { + case QCA8084_PIN_CONFIG_BIAS_DISABLE: + data = QCA8084_TLMM_GPIO_CFGN_GPIO_PULL_DISABLE; + break; + case QCA8084_PIN_CONFIG_BIAS_PULL_DOWN: + data = QCA8084_TLMM_GPIO_CFGN_GPIO_PULL_DOWN; + break; + case QCA8084_PIN_CONFIG_BIAS_BUS_HOLD: + data = QCA8084_TLMM_GPIO_CFGN_GPIO_PULL_BUS_HOLD; + break; + case QCA8084_PIN_CONFIG_BIAS_PULL_UP: + data = QCA8084_TLMM_GPIO_CFGN_GPIO_PULL_UP; + break; + default: + printf("[%s] doesn't support bias:%d\n", __func__, bias); + return -1; + } + + QCA8084_REG_FIELD_SET(TLMM_GPIO_CFGN, pin, GPIO_PULL, + (u8 *) (&data)); + pr_debug("[%s]pin:%d bias:%d", __func__, pin, bias); + + return rv; +} + +int qca8084_gpio_pin_cfg_get_bias(u32 pin, enum qca8084_pin_config_param *bias) +{ + int rv = 0; + u32 data = 0; + + QCA8084_REG_FIELD_GET(TLMM_GPIO_CFGN, pin, GPIO_PULL, + (u8 *) (&data)); + switch (data) + { + case QCA8084_TLMM_GPIO_CFGN_GPIO_PULL_DISABLE: + *bias = QCA8084_PIN_CONFIG_BIAS_DISABLE; + break; + case QCA8084_TLMM_GPIO_CFGN_GPIO_PULL_DOWN: + *bias = QCA8084_PIN_CONFIG_BIAS_PULL_DOWN; + break; + case QCA8084_TLMM_GPIO_CFGN_GPIO_PULL_BUS_HOLD: + *bias = QCA8084_PIN_CONFIG_BIAS_BUS_HOLD; + break; + case QCA8084_TLMM_GPIO_CFGN_GPIO_PULL_UP: + *bias = QCA8084_PIN_CONFIG_BIAS_PULL_UP; + break; + default: + printf("[%s] doesn't support bias:%d\n", __func__, data); + return -1; + } + pr_debug("[%s]pin:%d bias:%d", __func__, pin, *bias); + + return rv; +} + +int qca8084_gpio_pin_cfg_set_drvs(u32 pin, u32 drvs) +{ + int rv = 0; + + if((drvs < QCA8084_TLMM_GPIO_CFGN_DRV_STRENGTH_2_MA) || + (drvs > QCA8084_TLMM_GPIO_CFGN_DRV_STRENGTH_16_MA)) { + printf("[%s] doesn't support drvs:%d\n", __func__, drvs); + return -1; + } + + QCA8084_REG_FIELD_SET(TLMM_GPIO_CFGN, pin, DRV_STRENGTH, + (u8 *) (&drvs)); + pr_debug("[%s]%d", __func__, pin); + + return rv; +} + +int qca8084_gpio_pin_cfg_get_drvs(u32 pin, u32 *drvs) +{ + int rv = 0; + + QCA8084_REG_FIELD_GET(TLMM_GPIO_CFGN, pin, DRV_STRENGTH, + (u8 *) (drvs)); + pr_debug("[%s]%d", __func__, pin); + + return rv; +} + +int qca8084_gpio_pin_cfg_set_oe(u32 pin, bool oe) +{ + int rv = 0; + + pr_debug("[%s]%d oe:%d", __func__, pin, oe); + + QCA8084_REG_FIELD_SET(TLMM_GPIO_CFGN, pin, GPIO_OEA, + (u8 *) (&oe)); + + return rv; +} + +int qca8084_gpio_pin_cfg_get_oe(u32 pin, bool *oe) +{ + int rv = 0; + u32 data = 0; + + QCA8084_REG_FIELD_GET(TLMM_GPIO_CFGN, pin, GPIO_OEA, + (u8 *) (&data)); + *oe = data ? true : false; + + pr_debug("[%s]%d oe:%d", __func__, pin, *oe); + + return rv; +} + +static enum qca8084_pin_config_param pinconf_to_config_param(unsigned long config) +{ + return (enum qca8084_pin_config_param) (config & 0xffUL); +} + +static u32 pinconf_to_config_argument(unsigned long config) +{ + return (u32) ((config >> 8) & 0xffffffUL); +} + +static int qca8084_gpio_pin_cfg_set(u32 pin, + u64 *configs, u32 num_configs) +{ + enum qca8084_pin_config_param param; + u32 i, arg; + int rv = 0; + + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(configs[i]); + arg = pinconf_to_config_argument(configs[i]); + + switch (param) { + case QCA8084_PIN_CONFIG_BIAS_BUS_HOLD: + case QCA8084_PIN_CONFIG_BIAS_DISABLE: + case QCA8084_PIN_CONFIG_BIAS_PULL_DOWN: + case QCA8084_PIN_CONFIG_BIAS_PULL_UP: + rv = qca8084_gpio_pin_cfg_set_bias(pin, param); + break; + + case QCA8084_PIN_CONFIG_DRIVE_STRENGTH: + rv = qca8084_gpio_pin_cfg_set_drvs(pin, arg); + break; + + case QCA8084_PIN_CONFIG_OUTPUT: + rv = qca8084_gpio_pin_cfg_set_oe(pin, true); + rv = qca8084_gpio_set_bit(pin, arg); + break; + + case QCA8084_PIN_CONFIG_INPUT_ENABLE: + rv = qca8084_gpio_pin_cfg_set_oe(pin, false); + break; + + case QCA8084_PIN_CONFIG_OUTPUT_ENABLE: + rv = qca8084_gpio_pin_cfg_set_oe(pin, true); + break; + + default: + printf("%s %d doesn't support:%d \n", __func__, __LINE__, param); + return -1; + } + } + + return rv; +} + + +/**************************************************************************** + * + * 3) PINs Init + * + ****************************************************************************/ +int qca8084_pinctrl_clk_gate_set(bool gate_en) +{ + int rv = 0; + + QCA8084_REG_FIELD_SET(TLMM_CLK_GATE_EN, 0, AHB_HCLK_EN, + (u8 *) (&gate_en)); + QCA8084_REG_FIELD_SET(TLMM_CLK_GATE_EN, 0, SUMMARY_INTR_EN, + (u8 *) (&gate_en)); + QCA8084_REG_FIELD_SET(TLMM_CLK_GATE_EN, 0, CRIF_READ_EN, + (u8 *) (&gate_en)); + + pr_debug("[%s] gate_en:%d", __func__, gate_en); + + return rv; +} + +static int qca8084_pinctrl_rev_check(void) +{ + int rv = 0; + u32 version_id = 0, mfg_id = 0, start_bit = 0; + + QCA8084_REG_FIELD_GET(TLMM_HW_REVISION_NUMBER, 0, VERSION_ID, + (u8 *) (&version_id)); + QCA8084_REG_FIELD_GET(TLMM_HW_REVISION_NUMBER, 0, MFG_ID, + (u8 *) (&mfg_id)); + QCA8084_REG_FIELD_GET(TLMM_HW_REVISION_NUMBER, 0, START_BIT, + (u8 *) (&start_bit)); + + pr_debug("[%s] version_id:0x%x mfg_id:0x%x start_bit:0x%x", + __func__, version_id, mfg_id, start_bit); + + if((version_id == 0x0) && (mfg_id == 0x70) && (start_bit == 0x1)) { + pr_debug(" Pinctrl Version Check Pass\n"); + } else { + printf("Error: Pinctrl Version Check Fail\n"); + rv = -1; + } + + return rv; +} + +static int qca8084_pinctrl_hw_init(void) +{ + int rv = 0; + + rv = qca8084_pinctrl_clk_gate_set(true); + rv = qca8084_pinctrl_rev_check(); + + return rv; +} + +static int qca8084_pinctrl_setting_init(const struct qca8084_pinctrl_setting *pin_settings, + u32 num_setting) +{ + int rv = 0; + u32 i; + + for(i = 0; i < num_setting; i++) { + const struct qca8084_pinctrl_setting *setting = &pin_settings[i]; + if (setting->type == QCA8084_PIN_MAP_TYPE_MUX_GROUP) { + rv = qca8084_gpio_pin_mux_set(setting->data.mux.pin, setting->data.mux.func); + + } else if (setting->type == QCA8084_PIN_MAP_TYPE_CONFIGS_PIN) { + rv = qca8084_gpio_pin_cfg_set(setting->data.configs.pin, + setting->data.configs.configs, + setting->data.configs.num_configs); + } + } + + return rv; +} + +int ipq_qca8084_pinctrl_init(void) +{ + qca8084_pinctrl_hw_init(); + qca8084_pinctrl_setting_init(qca8084_pin_settings, ARRAY_SIZE(qca8084_pin_settings)); + return 0; +} + +void qca8084_phy_reset(u32 phy_addr) +{ + u16 phy_data; + + phy_data = qca8084_phy_reg_read(phy_addr, QCA8084_PHY_CONTROL); + qca8084_phy_reg_write(phy_addr, QCA8084_PHY_CONTROL, + phy_data | QCA8084_CTRL_SOFTWARE_RESET); +} + +#ifdef CONFIG_QCA8084_PHY_MODE +void qca8084_phy_ipg_config(uint32_t phy_id, fal_port_speed_t speed) +{ + uint16_t phy_data = 0; + + phy_data = qca8084_phy_mmd_read(phy_id, QCA8084_PHY_MMD7_NUM, + QCA8084_PHY_MMD7_IPG_10_11_ENABLE); + + phy_data &= ~QCA8084_PHY_MMD7_IPG_11_EN; + + /*If speed is 1G, enable 11 ipg tuning*/ + pr_debug("if speed is 1G, enable 11 ipg tuning\n"); + if (speed == FAL_SPEED_1000) + phy_data |= QCA8084_PHY_MMD7_IPG_11_EN; + + qca8084_phy_mmd_write(phy_id, QCA8084_PHY_MMD7_NUM, + QCA8084_PHY_MMD7_IPG_10_11_ENABLE, phy_data); +} + +void qca8084_phy_uqxgmii_speed_fixup(uint32_t phy_addr, uint32_t qca8084_port_id, + uint32_t status, fal_port_speed_t new_speed) +{ + uint32_t port_clock_en = 0; + + /*Restart the auto-neg of uniphy*/ + pr_debug("Restart the auto-neg of uniphy\n"); + qca8084_uniphy_xpcs_autoneg_restart(qca8084_port_id); + + /*set gmii+ clock to uniphy1 and ethphy*/ + pr_debug("set gmii,xgmii clock to uniphy and gmii to ethphy\n"); + qca8084_port_speed_clock_set(qca8084_port_id, new_speed); + + /*set xpcs speed*/ + pr_debug("set xpcs speed\n"); + qca8084_uniphy_xpcs_speed_set(qca8084_port_id, new_speed); + + /*GMII/XGMII clock and ETHPHY GMII clock enable/disable*/ + pr_debug("GMII/XGMII clock and ETHPHY GMII clock enable/disable\n"); + if (status == 0) + port_clock_en = 1; + qca8084_port_clk_en_set(qca8084_port_id, + QCA8084_CLK_TYPE_UNIPHY | QCA8084_CLK_TYPE_EPHY, + port_clock_en); + + pr_debug("UNIPHY GMII/XGMII interface and ETHPHY GMII interface reset and release\n"); + qca8084_port_clk_reset(qca8084_port_id, + QCA8084_CLK_TYPE_UNIPHY | QCA8084_CLK_TYPE_EPHY); + + pr_debug("ipg_tune and xgmii2gmii reset for uniphy and ETHPHY, function reset\n"); + qca8084_uniphy_uqxgmii_function_reset(qca8084_port_id); + + /*do ethphy function reset: PHY_FIFO_RESET*/ + pr_debug("do ethphy function reset\n"); + qca8084_phy_function_reset(phy_addr); + + /*change IPG from 10 to 11 for 1G speed*/ + qca8084_phy_ipg_config(phy_addr, new_speed); +} + +void qca8084_phy_interface_mode_set(void) +{ + pr_debug("Configure QCA8084 as PORT_UQXGMII..\n"); + /*the work mode is PORT_UQXGMII in default*/ + qca8084_interface_uqxgmii_mode_set(); + + /*init clock for PORT_UQXGMII*/ + qca8084_gcc_clock_init(QCA8084_PHY_UQXGMII_MODE, 0); + + /*init pinctrl for phy mode to be added later*/ +} +#endif /* CONFIG_QCA8084_PHY_MODE */ + +void qca8084_cdt_thresh_init(u32 phy_id) +{ + qca8084_phy_mmd_write(phy_id, QCA8084_PHY_MMD3_NUM, + QCA8084_PHY_MMD3_CDT_THRESH_CTRL3, + QCA8084_PHY_MMD3_CDT_THRESH_CTRL3_VAL); + qca8084_phy_mmd_write(phy_id, QCA8084_PHY_MMD3_NUM, + QCA8084_PHY_MMD3_CDT_THRESH_CTRL4, + QCA8084_PHY_MMD3_CDT_THRESH_CTRL4_VAL); + qca8084_phy_mmd_write(phy_id, QCA8084_PHY_MMD3_NUM, + QCA8084_PHY_MMD3_CDT_THRESH_CTRL5, + QCA8084_PHY_MMD3_CDT_THRESH_CTRL5_VAL); + qca8084_phy_mmd_write(phy_id, QCA8084_PHY_MMD3_NUM, + QCA8084_PHY_MMD3_CDT_THRESH_CTRL6, + QCA8084_PHY_MMD3_CDT_THRESH_CTRL6_VAL); + qca8084_phy_mmd_write(phy_id, QCA8084_PHY_MMD3_NUM, + QCA8084_PHY_MMD3_CDT_THRESH_CTRL7, + QCA8084_PHY_MMD3_CDT_THRESH_CTRL7_VAL); + qca8084_phy_mmd_write(phy_id, QCA8084_PHY_MMD3_NUM, + QCA8084_PHY_MMD3_CDT_THRESH_CTRL9, + QCA8084_PHY_MMD3_CDT_THRESH_CTRL9_VAL); + qca8084_phy_mmd_write(phy_id, QCA8084_PHY_MMD3_NUM, + QCA8084_PHY_MMD3_CDT_THRESH_CTRL13, + QCA8084_PHY_MMD3_CDT_THRESH_CTRL13_VAL); + qca8084_phy_mmd_write(phy_id, QCA8084_PHY_MMD3_NUM, + QCA8084_PHY_MMD3_CDT_THRESH_CTRL14, + QCA8084_PHY_MMD3_NEAR_ECHO_THRESH_VAL); +} + +void qca8084_phy_modify_debug(u32 phy_addr, u32 debug_reg, + u32 mask, u32 value) +{ + u16 phy_data = 0, new_phy_data = 0; + + qca8084_phy_reg_write(phy_addr, QCA8084_DEBUG_PORT_ADDRESS, debug_reg); + phy_data = qca8084_phy_reg_read(phy_addr, QCA8084_DEBUG_PORT_DATA); + if (phy_data == PHY_INVALID_DATA) + pr_debug("qca8084_phy_reg_read failed\n"); + + new_phy_data = (phy_data & ~mask) | value; + qca8084_phy_reg_write(phy_addr, QCA8084_DEBUG_PORT_ADDRESS, debug_reg); + qca8084_phy_reg_write(phy_addr, QCA8084_DEBUG_PORT_DATA, new_phy_data); + + /* check debug register value */ + qca8084_phy_reg_write(phy_addr, QCA8084_DEBUG_PORT_ADDRESS, debug_reg); + phy_data = qca8084_phy_reg_read(phy_addr, QCA8084_DEBUG_PORT_DATA); + pr_debug("phy_addr:0x%x, debug_reg:0x%x, phy_data:0x%x\n", + phy_addr, debug_reg, phy_data); +} + +void qca8084_phy_adc_edge_set(u32 phy_addr, u32 adc_edge) +{ + qca8084_phy_modify_debug(phy_addr, + QCA8084_PHY_DEBUG_ANA_INTERFACE_CLK_SEL, 0xf0, adc_edge); + qca8084_phy_reset(phy_addr); +} + +void ipq_qca8084_phy_hw_init(struct phy_ops **ops, u32 phy_addr) +{ +#ifdef DEBUG + u16 phy_data; +#endif + struct phy_ops *qca8084_ops; + + qca8084_ops = (struct phy_ops *)malloc(sizeof(struct phy_ops)); + if (!qca8084_ops) { + pr_debug("Error allocating memory for phy ops\n"); + return; + } + + /* Note that qca8084 PHY is based on qca8081 PHY and so the following + * ops functions required would be re-used from qca8081 */ + + qca8084_ops->phy_get_link_status = qca8081_phy_get_link_status; + qca8084_ops->phy_get_speed = qca8081_phy_get_speed; + qca8084_ops->phy_get_duplex = qca8081_phy_get_duplex; + *ops = qca8084_ops; + +#ifdef DEBUG + phy_data = qca8084_phy_reg_read(phy_addr, QCA8081_PHY_ID1); + printf("PHY ID1: 0x%x\n", phy_data); + phy_data = qca8084_phy_reg_read(phy_addr, QCA8081_PHY_ID2); + printf("PHY ID2: 0x%x\n", phy_data); +#endif + + /* adjust CDT threshold */ + qca8084_cdt_thresh_init(phy_addr); + + /* invert ADC clock edge as falling edge to fix link issue */ + qca8084_phy_adc_edge_set(phy_addr, ADC_FALLING); +} + +static int qca8084_reg_field_get(u32 reg_addr, u32 bit_offset, + u32 field_len, u8 value[]) +{ + u32 reg_val = ipq_mii_read(reg_addr); + + *((u32 *) value) = SW_REG_2_FIELD(reg_val, bit_offset, field_len); + return 0; +} + +static int qca8084_reg_field_set(u32 reg_addr, u32 bit_offset, + u32 field_len, const u8 value[]) +{ + u32 field_val = *((u32 *) value); + u32 reg_val = ipq_mii_read(reg_addr); + + SW_REG_SET_BY_FIELD_U32(reg_val, field_val, bit_offset, field_len); + + ipq_mii_write(reg_addr, reg_val); + return 0; +} + +#ifdef CONFIG_QCA8084_SWT_MODE +static void ipq_qca8084_switch_reset(void) +{ + /* Reset switch core */ + qca8084_clk_reset(QCA8084_SWITCH_CORE_CLK); + + /* Reset MAC ports */ + qca8084_clk_reset(QCA8084_MAC0_TX_CLK); + qca8084_clk_reset(QCA8084_MAC0_RX_CLK); + qca8084_clk_reset(QCA8084_MAC1_TX_CLK); + qca8084_clk_reset(QCA8084_MAC1_RX_CLK); + qca8084_clk_reset(QCA8084_MAC2_TX_CLK); + qca8084_clk_reset(QCA8084_MAC2_RX_CLK); + qca8084_clk_reset(QCA8084_MAC3_TX_CLK); + qca8084_clk_reset(QCA8084_MAC3_RX_CLK); + qca8084_clk_reset(QCA8084_MAC4_TX_CLK); + qca8084_clk_reset(QCA8084_MAC4_RX_CLK); + qca8084_clk_reset(QCA8084_MAC5_TX_CLK); + qca8084_clk_reset(QCA8084_MAC5_RX_CLK); + return; +} + +static void ipq_qca8084_work_mode_set(qca8084_work_mode_t work_mode) +{ + u32 data = 0; + + data = ipq_mii_read(WORK_MODE_OFFSET); + data &= ~QCA8084_WORK_MODE_MASK; + data |= work_mode; + + ipq_mii_write(WORK_MODE_OFFSET, data); + return; +} + +static void ipq_qca8084_work_mode_get(qca8084_work_mode_t *work_mode) +{ + u32 data = 0; + + data = ipq_mii_read(WORK_MODE_OFFSET); + pr_debug("work mode reg is 0x%x\n", data); + + *work_mode = data & QCA8084_WORK_MODE_MASK; + return; +} + +static int ipq_qca8084_work_mode_init(int mac_mode0, int mac_mode1) +{ + int ret = 0; + + switch (mac_mode0) { + case EPORT_WRAPPER_SGMII_PLUS: + case EPORT_WRAPPER_SGMII_CHANNEL0: + break; + default: + /** not supported */ + printf("%s %d Error: Unsupported mac_mode0 \n", __func__, __LINE__); + return -1; + } + + if (qca8084_uniphy_mode_check(QCA8084_UNIPHY_SGMII_0, QCA8084_UNIPHY_PHY)){ + pr_debug("%s %d QCA8084 Uniphy 0 is in SGMII Mode \n", + __func__, __LINE__); + ipq_qca8084_work_mode_set(QCA8084_SWITCH_BYPASS_PORT5_MODE); + return ret; + } + + switch (mac_mode1) { + case EPORT_WRAPPER_SGMII_PLUS: + case EPORT_WRAPPER_MAX: + ipq_qca8084_work_mode_set(QCA8084_SWITCH_MODE); + break; + default: + printf("%s %d Error: Unsupported mac_mode1 \n", __func__, __LINE__); + return -1; + } + + return ret; +} + +static int chip_ver_get(void) +{ + int ret = 0; + u8 chip_ver; + u32 reg_val = ipq_mii_read(0); + + chip_ver = (reg_val & 0xFF00) >> 8; + + /*qca8084_start*/ + switch (chip_ver) { + case QCA_VER_QCA8084: + ret = CHIP_QCA8084; + break; + default: + printf("Error: Unsupported chip \n"); + ret = -1; + break; + } + + return ret; +} + +bool qca8084_port_phy_connected(u32 port_id) +{ + u32 cpu_bmp = 0x1; + if ((cpu_bmp & BIT(port_id)) || (port_id == PORT0) || + (port_id == PORT5)) + return false; + + return true; +} + + +static void qca8084_port_txmac_status_set(u32 port_id, bool enable) +{ + u32 reg, force, val = 0, tmp; + + QCA8084_REG_ENTRY_GET(PORT_STATUS, port_id, (u8 *) (®)); + + if (true == enable) + { + val = 1; + } + else if (false == enable) + { + val = 0; + } + tmp = reg; + + /* for those ports without PHY device we set MAC register */ + if (false == qca8084_port_phy_connected(port_id)) + { + SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg); + SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN, val, reg); + } + else + { + SW_GET_FIELD_BY_REG(PORT_STATUS, LINK_EN, force, reg); + if (force) + { + /* link isn't in force mode so can't set */ + printf("%s %d Error: SW disable \n", __func__, __LINE__); + return; + } + else + { + SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN, val, reg); + } + } + + if (tmp == reg) + return; + + QCA8084_REG_ENTRY_SET(PORT_STATUS, port_id, (u8 *) (®)); + return; +} + +static void qca8084_port_rxmac_status_set(u32 port_id, bool enable) +{ + u32 reg = 0, force, val = 0, tmp; + + QCA8084_REG_ENTRY_GET(PORT_STATUS, port_id, (u8 *) (®)); + + if (true == enable) + { + val = 1; + } + else if (false == enable) + { + val = 0; + } + tmp = reg; + + /* for those ports without PHY device we set MAC register */ + if (false == qca8084_port_phy_connected(port_id)) + { + SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg); + SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, val, reg); + } + else + { + SW_GET_FIELD_BY_REG(PORT_STATUS, LINK_EN, force, reg); + if (force) + { + /* link isn't in force mode so can't set */ + printf("%s %d Error: SW disable \n", __func__, __LINE__); + return; + } + else + { + SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, val, reg); + } + } + if (tmp == reg) + return; + QCA8084_REG_ENTRY_SET(PORT_STATUS, port_id, (u8 *) (®)); + return; +} + +static void qca8084_port_rxfc_status_set(u32 port_id, bool enable) +{ + u32 val = 0, reg, tmp; + + if (true == enable) + { + val = 1; + } + else if (false == enable) + { + val = 0; + } + + QCA8084_REG_ENTRY_GET(PORT_STATUS, port_id, (u8 *) (®)); + tmp = reg; + + SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN, val, reg); + + if ( tmp == reg) + return; + + QCA8084_REG_ENTRY_SET(PORT_STATUS, port_id, (u8 *) (®)); + return; +} + +static void qca8084_port_txfc_status_set(u32 port_id, bool enable) +{ + u32 val, reg = 0, tmp; + + if (true == enable) + { + val = 1; + } + else if (false == enable) + { + val = 0; + } + + QCA8084_REG_ENTRY_GET(PORT_STATUS, port_id, (u8 *) (®)); + tmp = reg; + + SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN, val, reg); + SW_SET_REG_BY_FIELD(PORT_STATUS, TX_HALF_FLOW_EN, val, reg); + + if (tmp == reg) + return; + QCA8084_REG_ENTRY_SET(PORT_STATUS, port_id, (u8 *) (®)); + + return; +} + +static void qca8084_port_flowctrl_set(u32 port_id, bool enable) +{ + qca8084_port_txfc_status_set(port_id, enable); + qca8084_port_rxfc_status_set(port_id, enable); + return; +} + +static void qca8084_port_flowctrl_forcemode_set(u32 port_id, bool enable) +{ + qca8084_port_txfc_forcemode[port_id] = enable; + qca8084_port_rxfc_forcemode[port_id] = enable; + return; +} + +static void header_type_set(bool enable, u32 type) +{ + u32 reg = 0; + + QCA8084_REG_ENTRY_GET(HEADER_CTL, 0, (u8 *) (®)); + + if (true == enable) + { + if (0xffff < type) + { + printf("%s %d Error: Bad param \n", __func__, __LINE__); + return; + } + SW_SET_REG_BY_FIELD(HEADER_CTL, TYPE_LEN, 1, reg); + SW_SET_REG_BY_FIELD(HEADER_CTL, TYPE_VAL, type, reg); + } + else if (false == enable) + { + SW_SET_REG_BY_FIELD(HEADER_CTL, TYPE_LEN, 0, reg); + SW_SET_REG_BY_FIELD(HEADER_CTL, TYPE_VAL, 0, reg); + } + + QCA8084_REG_ENTRY_SET(HEADER_CTL, 0, (u8 *) (®)); + return; +} + +static void port_rxhdr_mode_set(u32 port_id, port_header_mode_t mode) +{ + u32 val = 0; + if (FAL_NO_HEADER_EN == mode) + { + val = 0; + } + else if (FAL_ONLY_MANAGE_FRAME_EN == mode) + { + val = 1; + } + else if (FAL_ALL_TYPE_FRAME_EN == mode) + { + val = 2; + } + else + { + printf("%s %d Error: Bad param \n", __func__, __LINE__); + return; + } + + QCA8084_REG_FIELD_SET(PORT_HDR_CTL, port_id, RXHDR_MODE,(u8 *) (&val)); + return; +} + +static void port_txhdr_mode_set(u32 port_id, port_header_mode_t mode) +{ + u32 val = 0; + if (FAL_NO_HEADER_EN == mode) + { + val = 0; + } + else if (FAL_ONLY_MANAGE_FRAME_EN == mode) + { + val = 1; + } + else if (FAL_ALL_TYPE_FRAME_EN == mode) + { + val = 2; + } + else + { + printf("%s %d Error: Bad param \n", __func__, __LINE__); + return; + } + + QCA8084_REG_FIELD_SET(PORT_HDR_CTL, port_id, TXHDR_MODE, (u8 *) (&val)); + return; +} + + +int qca8084_phy_get_status(u32 phy_id, struct port_phy_status *phy_status) +{ + u16 phy_data; + + phy_data = qca8084_phy_reg_read(phy_id, QCA8084_PHY_SPEC_STATUS); + + /*get phy link status*/ + if (phy_data & QCA8084_STATUS_LINK_PASS) { + phy_status->link_status = true; + } + else { + phy_status->link_status = false; + + /*when link down, phy speed is set as 10M*/ + phy_status->speed = FAL_SPEED_10; + return 0; + } + + /*get phy speed*/ + switch (phy_data & QCA8084_STATUS_SPEED_MASK) { + case QCA8084_STATUS_SPEED_2500MBS: + phy_status->speed = FAL_SPEED_2500; + break; + case QCA8084_STATUS_SPEED_1000MBS: + phy_status->speed = FAL_SPEED_1000; + break; + case QCA8084_STATUS_SPEED_100MBS: + phy_status->speed = FAL_SPEED_100; + break; + case QCA8084_STATUS_SPEED_10MBS: + phy_status->speed = FAL_SPEED_10; + break; + default: + return -1; + } + + /*get phy duplex*/ + if (phy_data & QCA8084_STATUS_FULL_DUPLEX) { + phy_status->duplex = FAL_FULL_DUPLEX; + } else { + phy_status->duplex = FAL_HALF_DUPLEX; + } + + /* get phy flowctrl resolution status */ + if (phy_data & QCA8084_PHY_RX_FLOWCTRL_STATUS) { + phy_status->rx_flowctrl = true; + } else { + phy_status->rx_flowctrl = false; + } + + if (phy_data & QCA8084_PHY_TX_FLOWCTRL_STATUS) { + phy_status->tx_flowctrl = true; + } else { + phy_status->tx_flowctrl = false; + } + + return 0; +} + + +static void qca8084_port_mac_dupex_set(u32 port_id, u32 duplex) +{ + u32 reg_val = 0, tmp; + u32 duplex_val; + + QCA8084_REG_ENTRY_GET(PORT_STATUS, port_id, (u8 *) (®_val)); + tmp = reg_val; + + if (FAL_HALF_DUPLEX == duplex) { + duplex_val = QCA8084_PORT_HALF_DUPLEX; + } else { + duplex_val = QCA8084_PORT_FULL_DUPLEX; + } + SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE, duplex_val, reg_val); + + if (tmp == reg_val) + return; + + QCA8084_REG_ENTRY_SET(PORT_STATUS, port_id, (u8 *) (®_val)); + return; +} + +static void qca8084_port_duplex_set(u32 port_id, fal_port_duplex_t duplex, + phy_info_t * phy_info) +{ + /* for those ports without PHY device we set MAC register */ + if (false == qca8084_port_phy_connected(port_id)) + { + qca8084_port_mac_dupex_set(port_id, duplex); + } + else + { + printf("%s %d Error: Duplex/Speed set for QCA8084 PORT1-4" + "is not implemented \n", __func__, __LINE__); + } + return; +} + +static void qca8084_port_mac_speed_set(u32 port_id, u32 speed) +{ + u32 reg_val = 0, tmp; + u32 speed_val; + + QCA8084_REG_ENTRY_GET(PORT_STATUS, port_id, (u8 *) (®_val)); + tmp = reg_val; + + if (FAL_SPEED_10 == speed) { + speed_val = QCA8084_PORT_SPEED_10M; + } else if (FAL_SPEED_100 == speed) { + speed_val = QCA8084_PORT_SPEED_100M; + } else if (FAL_SPEED_1000 == speed) { + speed_val = QCA8084_PORT_SPEED_1000M; + } else if (FAL_SPEED_2500 == speed) { + speed_val = QCA8084_PORT_SPEED_2500M; + } else { + printf("%s %d Bad param \n",__func__, __LINE__); + return; + } + SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, speed_val, reg_val); + + if (tmp == reg_val) + return; + + QCA8084_REG_ENTRY_SET(PORT_STATUS, port_id, (u8 *) (®_val)); + return; +} + +static void qca8084_port_speed_set(u32 port_id, fal_port_speed_t speed, + phy_info_t * phy_info) +{ + /* for those ports without PHY device we set MAC register */ + if (false == qca8084_port_phy_connected(port_id)) + { + qca8084_port_mac_speed_set(port_id, speed); + } + else + { + printf("%s %d Error: Duplex/Speed set for QCA8084 PORT1-4" + "is not implemented \n", __func__, __LINE__); + } + return; +} + +static int _qca8084_interface_mode_init(u32 port_id, u32 mac_mode, + phy_info_t * phy_info) +{ + u32 uniphy_index = 0; + mac_config_t config; + u32 force_speed = FAL_SPEED_BUTT; + qca8084_work_mode_t work_mode = QCA8084_SWITCH_MODE; + + if (phy_info->forced_speed) { + force_speed = phy_info->forced_speed; + + qca8084_port_speed_set(port_id, force_speed, phy_info); + + qca8084_port_duplex_set(port_id, FAL_FULL_DUPLEX, phy_info); + + /* The clock parent need to be configured before initializing + * the interface mode. */ + ipq_qca8084_work_mode_get(&work_mode); + qca8084_gcc_port_clk_parent_set(work_mode, port_id); + } + + + if(mac_mode == EPORT_WRAPPER_SGMII_PLUS) + config.mac_mode = QCA8084_MAC_MODE_SGMII_PLUS; + else if (mac_mode == EPORT_WRAPPER_SGMII_CHANNEL0) + config.mac_mode = QCA8084_MAC_MODE_SGMII; + else if (mac_mode == EPORT_WRAPPER_MAX) + config.mac_mode = QCA8084_MAC_MODE_MAX; + else { + printf("%s %d Unsupported mac mode \n", __func__, __LINE__); + return -1; + } + + /*get uniphy index*/ + if(port_id == PORT0) + uniphy_index = QCA8084_UNIPHY_SGMII_1; + else if(port_id == PORT5) + uniphy_index = QCA8084_UNIPHY_SGMII_0; + else { + printf("%s %d Unsupported mac_mode \n", __func__, __LINE__); + return -1; + } + + config.clock_mode = QCA8084_INTERFACE_CLOCK_MAC_MODE; + config.auto_neg = !(phy_info->forced_speed); + config.force_speed = force_speed; + + + if (port_id == PORT5) { + if (qca8084_uniphy_mode_check(QCA8084_UNIPHY_SGMII_0, QCA8084_UNIPHY_PHY)) + pr_debug("%s %d QCA8084 Uniphy 0 is in SGMII Mode \n", + __func__, __LINE__); + else { + if (config.mac_mode == QCA8084_MAC_MODE_MAX) { + pr_debug("%s %d QCA8084 Port 5 clk disable \n", + __func__, __LINE__); + qca8084_clk_disable(QCA8084_SRDS0_SYS_CLK); + } + } + } else { + qca8084_interface_sgmii_mode_set(uniphy_index, port_id, &config); + + /*do sgmii function reset*/ + pr_debug("ipg_tune reset and function reset\n"); + qca8084_uniphy_sgmii_function_reset(uniphy_index); + } + return 0; +} + +static int ipq_qca8084_interface_mode_init(u32 mac_mode0, u32 mac_mode1, phy_info_t * phy_info[]) +{ + int ret = 0; + + ret = _qca8084_interface_mode_init(PORT0, mac_mode0, phy_info[PORT0]); + if (ret < 0) + return ret; + + ret = _qca8084_interface_mode_init(PORT5, mac_mode1, phy_info[PORT5]); + if (ret < 0) + return ret; + + if (phy_info[PORT0]->forced_speed) { + qca8084_port_txmac_status_set(PORT0, true); + qca8084_port_rxmac_status_set(PORT0, true); + } + + if (phy_info[PORT5]->forced_speed) { + qca8084_port_txmac_status_set(PORT5, true); + qca8084_port_rxmac_status_set(PORT5, true); + } + return ret; +} + + +void port_link_update(u32 port_id, struct port_phy_status phy_status) +{ + /* configure gcc uniphy and mac speed frequency*/ + qca8084_port_speed_clock_set(port_id, phy_status.speed); + + /* configure mac speed and duplex */ + qca8084_port_mac_speed_set(port_id, phy_status.speed); + qca8084_port_mac_dupex_set(port_id, phy_status.duplex); + pr_debug("mht port %d link %d update speed %d duplex %d\n", + port_id, phy_status.speed, + phy_status.speed, phy_status.duplex); + if (phy_status.link_status == PORT_LINK_UP) + { + /* sync mac flowctrl */ + if (qca8084_port_txfc_forcemode[port_id] != true) { + qca8084_port_txfc_status_set(port_id, phy_status.tx_flowctrl); + pr_debug("mht port %d link up update txfc %d\n", + port_id, phy_status.tx_flowctrl); + } + if (qca8084_port_rxfc_forcemode[port_id] != true) { + qca8084_port_rxfc_status_set(port_id, phy_status.rx_flowctrl); + pr_debug("mht port %d link up update rxfc %d\n", + port_id, phy_status.rx_flowctrl); + } + if (port_id != PORT5) { + /* enable eth phy clock */ + qca8084_port_clk_en_set(port_id, QCA8084_CLK_TYPE_EPHY, true); + } + } + if (port_id != PORT5) { + if (phy_status.link_status == PORT_LINK_DOWN) { + /* disable eth phy clock */ + qca8084_port_clk_en_set(port_id, QCA8084_CLK_TYPE_EPHY, false); + } + /* reset eth phy clock */ + qca8084_port_clk_reset(port_id, QCA8084_CLK_TYPE_EPHY); + /* reset eth phy fifo */ + qca8084_phy_function_reset(port_id); + } + return; +} + +static void port_3az_status_set(u32 port_id, bool enable) +{ + u32 reg = 0, field, offset, device_id, reverse = 0; + u32 eee_mask = 0; + + QCA8084_REG_ENTRY_GET(MASK_CTL, 0, (u8 *) (®)); + + SW_GET_FIELD_BY_REG(MASK_CTL, DEVICE_ID, device_id, reg); + switch (device_id) { + case QCA_VER_QCA8084: + eee_mask = 3; + reverse = 0; + break; + default: + printf("%s %d Unsupported DEV_ID \n", __func__, __LINE__); + return; + } + + QCA8084_REG_ENTRY_GET(EEE_CTL, 0, (u8 *) (®)); + + if (true == enable) + { + field = eee_mask; + } + else if (false == enable) + { + field = 0; + } + + if (reverse) + { + field = (~field) & eee_mask; + } + + offset = (port_id - 1) * ISISC_LPI_BIT_STEP + ISISC_LPI_PORT1_OFFSET; + reg &= (~(eee_mask << offset)); + reg |= (field << offset); + + QCA8084_REG_ENTRY_SET(EEE_CTL, 0, (u8 *) (®)); + return; +} + +static void qos_port_tx_buf_nr_set(u32 port_id, u32 * number) +{ + u32 val = 0; + if (ISISC_QOS_PORT_TX_BUFFER_MAX < *number) + { + printf("%s %d Bad param \n", __func__, __LINE__); + return; + } + + val = *number / ISISC_QOS_HOL_STEP; + *number = val << ISISC_QOS_HOL_MOD; + QCA8084_REG_FIELD_SET(PORT_HOL_CTL0, port_id, PORT_DESC_NR, + (u8 *) (&val)); + return; +} + +static void qos_port_rx_buf_nr_set(u32 port_id, u32 * number) +{ + u32 val = 0; + if (ISISC_QOS_PORT_RX_BUFFER_MAX < *number) + { + printf("%s %d Bad param \n", __func__, __LINE__); + return; + } + + val = *number / ISISC_QOS_HOL_STEP; + *number = val << ISISC_QOS_HOL_MOD; + QCA8084_REG_FIELD_SET(PORT_HOL_CTL1, port_id, PORT_IN_DESC_EN, + (u8 *) (&val)); + return; +} + +void qca_switch_init(u32 port_bmp, u32 cpu_bmp, phy_info_t * phy_info[]) +{ + u32 port_hol_ctrl[2] = {0}; + int i = 0; + u32 temp; + + port_bmp |= cpu_bmp; + while (port_bmp) { + pr_debug("configuring port: %d \n", i); + if (port_bmp & 1) { + temp = 0; + QCA8084_REG_FIELD_GET(FORWARD_CTL1, 0, BC_FLOOD_DP, (u8 *) (&temp)); + temp |= (0x1 << i); + QCA8084_REG_FIELD_SET(FORWARD_CTL1, 0, BC_FLOOD_DP, (u8 *) (&temp)); + + qca8084_port_txmac_status_set(i, false); + qca8084_port_rxmac_status_set(i, false); + + if (cpu_bmp & BIT(i)) { + qca8084_port_flowctrl_set(i, false); + qca8084_port_flowctrl_forcemode_set(i, true); + + header_type_set(true, QCA8084_HEADER_TYPE_VAL); + port_rxhdr_mode_set(i, FAL_ONLY_MANAGE_FRAME_EN); + port_txhdr_mode_set(i, FAL_NO_HEADER_EN); + + /* port tx buf number */ + port_hol_ctrl[0] = 600; + /* port rx buf number */ + port_hol_ctrl[1] = 48; + } else { + qca8084_port_flowctrl_set(i, true); + qca8084_port_flowctrl_forcemode_set(i, false); + } + + port_3az_status_set(i, false); + + temp=1; + QCA8084_REG_FIELD_SET(PORT_HOL_CTL1, i, PORT_RED_EN, (u8 *) (&temp)); + + qos_port_tx_buf_nr_set(i, &port_hol_ctrl[0]); + qos_port_rx_buf_nr_set(i, &port_hol_ctrl[1]); + + } + port_bmp >>=1; + i++; + } + return; +} + +int ipq_qca8084_link_update(phy_info_t * phy_info[]) +{ + struct port_phy_status phy_status = {0}; + int rv, port_id, status = 1; + + printf("QCA8084-switch status:\n"); + for (int i=PORT1; iphy_address; + if (phy_info[i]->phy_type == UNUSED_PHY_TYPE) + continue; + + rv = qca8084_phy_get_status(port_id, &phy_status); + if (rv < 0) { + printf("%s %d failed get phy status of idx %d \n", + __func__, __LINE__, port_id); + return status; + } + + printf("PORT%d %s Speed :%d %s duplex\n", port_id, + (phy_status.link_status?"Up":"Down"), + phy_status.speed, (phy_status.duplex?"Full":"Half")); + + if (phy_status.link_status == PORT_LINK_DOWN) { + /* enable mac rx function */ + qca8084_port_rxmac_status_set(port_id, false); + /* enable mac tx function */ + qca8084_port_txmac_status_set(port_id, false); + /* update gcc, mac speed, mac duplex and phy stauts */ + port_link_update(port_id, phy_status); + } + + if (phy_status.link_status == PORT_LINK_UP) { + /* update gcc, mac speed, mac duplex and phy stauts */ + port_link_update(port_id, phy_status); + /* enable mac tx function */ + qca8084_port_txmac_status_set(port_id, true); + /* enable mac rx function */ + qca8084_port_rxmac_status_set(port_id, true); + + status = 0; + } + } + + return status; +} + +int ipq_qca8084_hw_init(phy_info_t * phy_info[]) +{ + int ret = 0; + int mode0 = -1, mode1 = -1, node = -1; + qca8084_work_mode_t work_mode; + u32 port_bmp, cpu_bmp; + + int chip_type = chip_ver_get(); + + if (chip_type != CHIP_QCA8084) { + printf("Error: Unsupported chip_type \n"); + return -1; + } + + node = fdt_path_offset(gd->fdt_blob, "/ess-switch/qca8084_swt_info"); + mode0 = fdtdec_get_uint(gd->fdt_blob, node, "switch_mac_mode0", -1); + if (mode0 < 0) { + printf("Error: switch_mac_mode0 not specified in dts\n"); + return mode0; + } + + mode1 = fdtdec_get_uint(gd->fdt_blob, node, "switch_mac_mode1", -1); + if (mode1 < 0) { + printf("Error: switch_mac_mode1 not specified in dts\n"); + return mode1; + } + + port_bmp = fdtdec_get_uint(gd->fdt_blob, node, "switch_lan_bmp", 0x3e); + + cpu_bmp = fdtdec_get_uint(gd->fdt_blob, node, "switch_cpu_bmp", 0x1); + + ipq_qca8084_switch_reset(); + + ret = ipq_qca8084_work_mode_init(mode0, mode1); + if (ret < 0) + return ret; + + qca_switch_init(port_bmp, cpu_bmp, phy_info); + + ret = ipq_qca8084_interface_mode_init(mode0, mode1, phy_info); + if (ret < 0) + return ret; + + port_bmp |= cpu_bmp; + + ipq_qca8084_work_mode_get(&work_mode); + qca8084_gcc_clock_init(work_mode, port_bmp); + + return ret; +} + +void ipq_qca8084_switch_hw_reset(int gpio) +{ + unsigned int *switch_gpio_base = + (unsigned int *)GPIO_CONFIG_ADDR(gpio); + + writel(0x203, switch_gpio_base); + writel(0x0, GPIO_IN_OUT_ADDR(gpio)); + mdelay(500); + writel(0x2, GPIO_IN_OUT_ADDR(gpio)); +} +#endif /* CONFIG_QCA8084_SWT_MODE */ + +#ifdef CONFIG_QCA8084_BYPASS_MODE +void qca8084_phy_sgmii_speed_fixup (u32 phy_addr, u32 link, + fal_port_speed_t new_speed) +{ + /*disable ethphy3 and uniphy0 clock*/ + pr_debug("disable ethphy3 and uniphy0 clock\n"); + qca8084_port_clk_en_set(PORT4, QCA8084_CLK_TYPE_EPHY, false); + qca8084_port_clk_en_set(PORT5, QCA8084_CLK_TYPE_UNIPHY, false); + + /*set gmii clock for ethphy3 and uniphy0*/ + pr_debug("set speed clock for eth3 and uniphy0\n"); + qca8084_port_speed_clock_set(PORT4, new_speed); + + /*uniphy and ethphy gmii clock enable/disable*/ + pr_debug("uniphy and ethphy GMII clock enable/disable\n"); + if(!link) + { + pr_debug("enable ethphy3 and uniphy0 clock\n"); + qca8084_port_clk_en_set(PORT4, QCA8084_CLK_TYPE_EPHY, true); + qca8084_port_clk_en_set(PORT5, QCA8084_CLK_TYPE_UNIPHY, true); + } + /*uniphy and ethphy gmii reset and release*/ + pr_debug("uniphy and ethphy GMII interface reset and release\n"); + qca8084_port_clk_reset(PORT4, QCA8084_CLK_TYPE_EPHY); + qca8084_port_clk_reset(PORT5, QCA8084_CLK_TYPE_UNIPHY); + + /*uniphy and ethphy ipg_tune reset, function reset*/ + pr_debug("uniphy and ethphy ipg_tune reset, function reset\n"); + qca8084_uniphy_sgmii_function_reset(QCA8084_UNIPHY_SGMII_0); + + /*do ethphy function reset*/ + pr_debug("do ethphy function reset\n"); + qca8084_phy_function_reset(phy_addr); + return; +} + +void qca8084_bypass_interface_mode_set(u32 interface_mode) +{ + ipq_qca8084_work_mode_set(QCA8084_PHY_SGMII_UQXGMII_MODE); + qca8084_phy_sgmii_mode_set(PORT4, interface_mode, false, FAL_SPEED_1000); + + pr_debug("ethphy3 software reset\n"); + qca8084_phy_reset(PORT4); + + /*init pinctrl for phy mode to be added later*/ +} +#endif /* CONFIG_QCA8084_BYPASS_MODE */ + diff --git a/sources/uboot-be550/drivers/net/ipq_common/ipq_qca8084.h b/sources/uboot-be550/drivers/net/ipq_common/ipq_qca8084.h new file mode 100644 index 00000000..dfe7a27a --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq_common/ipq_qca8084.h @@ -0,0 +1,794 @@ +/* + * Copyright (c) 2022, The Linux Foundation. All rights reserved. + + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. +*/ + +#ifndef _QCA8084_PHY_H_ +#define _QCA8084_PHY_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*QCA8084 PHY Fixup definitions */ +#define PORT_UQXGMII 0x1 +#define PHY_SGMII_BASET 0x2 +#define PORT_SGMII_PLUS 0x3 + +/*MII register*/ +#define QCA8084_PHY_FIFO_CONTROL 0x19 + +/*MII register field*/ +#define QCA8084_PHY_FIFO_RESET 0x3 + +/*MMD1 register*/ +#define QCA8084_PHY_MMD1_NUM 0x1 + +/*MMD3 register*/ +#define QCA8084_PHY_MMD3_NUM 0x3 +#define QCA8084_PHY_MMD3_ADDR_8023AZ_EEE_2500M_CAPABILITY 0x15 +#define QCA8084_PHY_MMD3_CDT_THRESH_CTRL3 0x8074 +#define QCA8084_PHY_MMD3_CDT_THRESH_CTRL4 0x8075 +#define QCA8084_PHY_MMD3_CDT_THRESH_CTRL5 0x8076 +#define QCA8084_PHY_MMD3_CDT_THRESH_CTRL6 0x8077 +#define QCA8084_PHY_MMD3_CDT_THRESH_CTRL7 0x8078 +#define QCA8084_PHY_MMD3_CDT_THRESH_CTRL9 0x807a +#define QCA8084_PHY_MMD3_CDT_THRESH_CTRL13 0x807e +#define QCA8084_PHY_MMD3_CDT_THRESH_CTRL14 0x807f + +/*MMD3 register field*/ +#define QCA8084_PHY_EEE_CAPABILITY_2500M 0x1 +#define QCA8084_PHY_MMD3_CDT_THRESH_CTRL3_VAL 0xc040 +#define QCA8084_PHY_MMD3_CDT_THRESH_CTRL4_VAL 0xa060 +#define QCA8084_PHY_MMD3_CDT_THRESH_CTRL5_VAL 0xc040 +#define QCA8084_PHY_MMD3_CDT_THRESH_CTRL6_VAL 0xa060 +#define QCA8084_PHY_MMD3_CDT_THRESH_CTRL7_VAL 0xc050 +#define QCA8084_PHY_MMD3_CDT_THRESH_CTRL9_VAL 0xc060 +#define QCA8084_PHY_MMD3_CDT_THRESH_CTRL13_VAL 0xb060 +#define QCA8084_PHY_MMD3_NEAR_ECHO_THRESH_VAL 0x1eb0 + +/*MMD7 register*/ +#define QCA8084_PHY_MMD7_NUM 0x7 +#define QCA8084_PHY_MMD7_ADDR_8023AZ_EEE_2500M_CTRL 0x3e +#define QCA8084_PHY_MMD7_ADDR_8023AZ_EEE_2500M_PARTNER 0x3f +#define QCA8084_PHY_MMD7_IPG_10_11_ENABLE 0x901d + +/*MMD7 register field*/ +#define QCA8084_PHY_8023AZ_EEE_2500BT 0x1 +#define QCA8084_PHY_MMD7_IPG_10_EN 0 +#define QCA8084_PHY_MMD7_IPG_11_EN 0x1 + +/*DEBUG port analog register*/ +#define QCA8084_PHY_DEBUG_ANA_INTERFACE_CLK_SEL 0x8b80 +#define QCA8084_DEBUG_PORT_ADDRESS 29 +#define QCA8084_DEBUG_PORT_DATA 30 + +#define QCA8084_PHY_CONTROL 0 +#define QCA8084_AUTONEG_ADVERT 4 +#define QCA8084_LINK_PARTNER_ABILITY 5 +#define QCA8084_1000BASET_CONTROL 9 +#define QCA8084_1000BASET_STATUS 10 +#define QCA8084_PHY_SPEC_STATUS 17 +#define QCA8084_CTRL_AUTONEGOTIATION_ENABLE 0x1000 +#define QCA8084_CTRL_SOFTWARE_RESET 0x8000 + + +#define QCA8084_STATUS_LINK_PASS 0x0400 +#define PHY_INVALID_DATA 0xffff + +#define QCA8084_PHY_MMD7_AUTONEGOTIATION_CONTROL 0x20 +#define QCA8084_PHY_MMD7_LP_2500M_ABILITY 0x21 + + /* Auto-Negotiation Advertisement register. offset:4 */ +#define QCA8084_ADVERTISE_SELECTOR_FIELD 0x0001 + + /* 10T Half Duplex Capable */ +#define QCA8084_ADVERTISE_10HALF 0x0020 + + /* 10T Full Duplex Capable */ +#define QCA8084_ADVERTISE_10FULL 0x0040 + + /* 100TX Half Duplex Capable */ +#define QCA8084_ADVERTISE_100HALF 0x0080 + + /* 100TX Full Duplex Capable */ +#define QCA8084_ADVERTISE_100FULL 0x0100 + + /* 100T4 Capable */ +#define QCA8084_ADVERTISE_100T4 0x0200 + + /* Pause operation desired */ +#define QCA8084_ADVERTISE_PAUSE 0x0400 + + /* Asymmetric Pause Direction bit */ +#define QCA8084_ADVERTISE_ASYM_PAUSE 0x0800 + + /* Remote Fault detected */ +#define QCA8084_ADVERTISE_REMOTE_FAULT 0x2000 + + /* 1000TX Half Duplex Capable */ +#define QCA8084_ADVERTISE_1000HALF 0x0100 + + /* 1000TX Full Duplex Capable */ +#define QCA8084_ADVERTISE_1000FULL 0x0200 + + /* 2500TX Full Duplex Capable */ +#define QCA8084_ADVERTISE_2500FULL 0x80 + +#define QCA8084_ADVERTISE_ALL \ + (QCA8084_ADVERTISE_10HALF | QCA8084_ADVERTISE_10FULL | \ + QCA8084_ADVERTISE_100HALF | QCA8084_ADVERTISE_100FULL | \ + QCA8084_ADVERTISE_1000FULL) + +#define QCA8084_ADVERTISE_MEGA_ALL \ + (QCA8084_ADVERTISE_10HALF | QCA8084_ADVERTISE_10FULL | \ + QCA8084_ADVERTISE_100HALF | QCA8084_ADVERTISE_100FULL | \ + QCA8084_ADVERTISE_PAUSE | QCA8084_ADVERTISE_ASYM_PAUSE) + +/* FDX =1, half duplex =0 */ +#define QCA8084_CTRL_FULL_DUPLEX 0x0100 + + /* Restart auto negotiation */ +#define QCA8084_CTRL_RESTART_AUTONEGOTIATION 0x0200 + + /* 1=Duplex 0=Half Duplex */ +#define QCA8084_STATUS_FULL_DUPLEX 0x2000 +#define QCA8084_PHY_RX_FLOWCTRL_STATUS 0x4 +#define QCA8084_PHY_TX_FLOWCTRL_STATUS 0x8 + + /* Speed, bits 9:7 */ +#define QCA8084_STATUS_SPEED_MASK 0x380 + + + /* 000=10Mbs */ +#define QCA8084_STATUS_SPEED_10MBS 0x0000 + + /* 001=100Mbs */ +#define QCA8084_STATUS_SPEED_100MBS 0x80 + + /* 010=1000Mbs */ +#define QCA8084_STATUS_SPEED_1000MBS 0x100 + + /* 100=2500Mbs */ +#define QCA8084_STATUS_SPEED_2500MBS 0x200 + + +#define QCA8084_MII_ADDR_C45 (1<<30) +#define QCA8084_REG_C45_ADDRESS(dev_type, reg_num) (QCA8084_MII_ADDR_C45 | \ + ((dev_type & 0x1f) << 16) | (reg_num & 0xffff)) + +typedef enum { + ADC_RISING = 0, + ADC_FALLING = 0xf0, +} +qca8084_adc_edge_t; + +//phy autoneg adv +#define FAL_PHY_ADV_10T_HD 0x01 +#define FAL_PHY_ADV_10T_FD 0x02 +#define FAL_PHY_ADV_100TX_HD 0x04 +#define FAL_PHY_ADV_100TX_FD 0x08 +//#define FAL_PHY_ADV_1000T_HD 0x100 +#define FAL_PHY_ADV_1000T_FD 0x200 +#define FAL_PHY_ADV_1000BX_HD 0x400 +#define FAL_PHY_ADV_1000BX_FD 0x800 +#define FAL_PHY_ADV_2500T_FD 0x1000 +#define FAL_PHY_ADV_5000T_FD 0x2000 +#define FAL_PHY_ADV_10000T_FD 0x4000 +#define FAL_PHY_ADV_10G_R_FD 0x8000 + +#define FAL_DEFAULT_MAX_FRAME_SIZE 0x5ee + +#define FAL_PHY_ADV_PAUSE 0x10 +#define FAL_PHY_ADV_ASY_PAUSE 0x20 + + +/** Bit manipulation macros */ +#ifndef BITSM +#define BITSM(_s, _n) (((1UL << (_n)) - 1) << _s) +#endif + +#define SW_BIT_MASK_U32(nr) (~(0xFFFFFFFF << (nr))) + +#define SW_FIELD_MASK_U32(offset, len) \ + ((SW_BIT_MASK_U32(len) << (offset))) + +#define SW_FIELD_MASK_NOT_U32(offset,len) \ + (~(SW_BIT_MASK_U32(len) << (offset))) + +#define SW_FIELD_2_REG(field_val, bit_offset) \ + (field_val << (bit_offset) ) + +#define SW_REG_2_FIELD(reg_val, bit_offset, field_len) \ + (((reg_val) >> (bit_offset)) & ((1 << (field_len)) - 1)) + +#define SW_FIELD_GET_BY_REG_U32(reg_value, field_value, bit_offset, field_len)\ + do { \ + (field_value) = \ + (((reg_value) >> (bit_offset)) & SW_BIT_MASK_U32(field_len)); \ + } while (0) + +#define SW_REG_SET_BY_FIELD_U32(reg_value, field_value, bit_offset, field_len)\ + do { \ + (reg_value) = \ + (((reg_value) & SW_FIELD_MASK_NOT_U32((bit_offset),(field_len))) \ + | (((field_value) & SW_BIT_MASK_U32(field_len)) << (bit_offset)));\ + } while (0) + +#define SW_GET_FIELD_BY_REG(reg, field, field_value, reg_value) \ + SW_FIELD_GET_BY_REG_U32(reg_value, field_value, reg##_##field##_BOFFSET, \ + reg##_##field##_BLEN) + +#define SW_SET_REG_BY_FIELD(reg, field, field_value, reg_value) \ + SW_REG_SET_BY_FIELD_U32(reg_value, field_value, reg##_##field##_BOFFSET, \ + reg##_##field##_BLEN) + +#define QCA8084_REG_ENTRY_GET(reg, index, value) \ + *((u32 *) value) = ipq_mii_read(reg##_OFFSET + ((u32)index) * reg##_E_OFFSET); + +#define QCA8084_REG_ENTRY_SET(reg, index, value) \ + ipq_mii_write(reg##_OFFSET + ((u32)index) * reg##_E_OFFSET, *((u32 *) value)); + +#define QCA8084_REG_FIELD_GET(reg, index, field, value) \ + do { \ + qca8084_reg_field_get(reg##_OFFSET + ((u32)index) * reg##_E_OFFSET,\ + reg##_##field##_BOFFSET, \ + reg##_##field##_BLEN, (u8*)value);\ + } while (0); + +#define QCA8084_REG_FIELD_SET(reg, index, field, value) \ + do { \ + qca8084_reg_field_set(reg##_OFFSET + ((u32)index) * reg##_E_OFFSET,\ + reg##_##field##_BOFFSET, \ + reg##_##field##_BLEN, (u8*)value);\ + } while (0); + + +/* Chip information */ +#define QCA_VER_QCA8084 0x17 +#define CHIP_QCA8084 0x13 + +/* Port Status Register */ +#define PORT_STATUS +#define PORT_STATUS_OFFSET 0x007c +#define PORT_STATUS_E_LENGTH 4 +#define PORT_STATUS_E_OFFSET 0x0004 +#define PORT_STATUS_NR_E 7 + +#define DUPLEX_MODE +#define PORT_STATUS_DUPLEX_MODE_BOFFSET 6 +#define PORT_STATUS_DUPLEX_MODE_BLEN 1 +#define PORT_STATUS_DUPLEX_MODE_FLAG HSL_RW + +#define SPEED_MODE +#define PORT_STATUS_SPEED_MODE_BOFFSET 0 +#define PORT_STATUS_SPEED_MODE_BLEN 2 +#define PORT_STATUS_SPEED_MODE_FLAG HSL_RW + +#define LINK_EN +#define PORT_STATUS_LINK_EN_BOFFSET 9 +#define PORT_STATUS_LINK_EN_BLEN 1 +#define PORT_STATUS_LINK_EN_FLAG HSL_RW + +#define RXMAC_EN +#define PORT_STATUS_RXMAC_EN_BOFFSET 3 +#define PORT_STATUS_RXMAC_EN_BLEN 1 +#define PORT_STATUS_RXMAC_EN_FLAG HSL_RW + +#define TXMAC_EN +#define PORT_STATUS_TXMAC_EN_BOFFSET 2 +#define PORT_STATUS_TXMAC_EN_BLEN 1 +#define PORT_STATUS_TXMAC_EN_FLAG HSL_RW + +#define RX_FLOW_EN +#define PORT_STATUS_RX_FLOW_EN_BOFFSET 5 +#define PORT_STATUS_RX_FLOW_EN_BLEN 1 +#define PORT_STATUS_RX_FLOW_EN_FLAG HSL_RW + +#define TX_FLOW_EN +#define PORT_STATUS_TX_FLOW_EN_BOFFSET 4 +#define PORT_STATUS_TX_FLOW_EN_BLEN 1 +#define PORT_STATUS_TX_FLOW_EN_FLAG HSL_RW + +#define TX_HALF_FLOW_EN +#define PORT_STATUS_TX_HALF_FLOW_EN_BOFFSET 7 +#define PORT_STATUS_TX_HALF_FLOW_EN_BLEN 1 +#define PORT_STATUS_TX_HALF_FLOW_EN_FLAG HSL_RW + +#define QCA8084_PORT_SPEED_10M 0 +#define QCA8084_PORT_SPEED_100M 1 +#define QCA8084_PORT_SPEED_1000M 2 +#define QCA8084_PORT_SPEED_2500M QCA8084_PORT_SPEED_1000M +#define QCA8084_PORT_HALF_DUPLEX 0 +#define QCA8084_PORT_FULL_DUPLEX 1 + +/* Header Ctl Register */ +#define HEADER_CTL +#define HEADER_CTL_OFFSET 0x0098 +#define HEADER_CTL_E_LENGTH 4 +#define HEADER_CTL_E_OFFSET 0x0004 +#define HEADER_CTL_NR_E 1 + +#define TYPE_LEN +#define HEADER_CTL_TYPE_LEN_BOFFSET 16 +#define HEADER_CTL_TYPE_LEN_BLEN 1 +#define HEADER_CTL_TYPE_LEN_FLAG HSL_RW + +#define TYPE_VAL +#define HEADER_CTL_TYPE_VAL_BOFFSET 0 +#define HEADER_CTL_TYPE_VAL_BLEN 16 +#define HEADER_CTL_TYPE_VAL_FLAG HSL_RW + + +/* Port Header Ctl Register */ +#define PORT_HDR_CTL +#define PORT_HDR_CTL_OFFSET 0x009c +#define PORT_HDR_CTL_E_LENGTH 4 +#define PORT_HDR_CTL_E_OFFSET 0x0004 +#define PORT_HDR_CTL_NR_E 7 + +#define RXHDR_MODE +#define PORT_HDR_CTL_RXHDR_MODE_BOFFSET 2 +#define PORT_HDR_CTL_RXHDR_MODE_BLEN 2 +#define PORT_HDR_CTL_RXHDR_MODE_FLAG HSL_RW + +#define TXHDR_MODE +#define PORT_HDR_CTL_TXHDR_MODE_BOFFSET 0 +#define PORT_HDR_CTL_TXHDR_MODE_BLEN 2 +#define PORT_HDR_CTL_TXHDR_MODE_FLAG HSL_RW + +#define QCA8084_HEADER_TYPE_VAL 0xaaaa + +/* Global Forward Control1 Register */ +#define FORWARD_CTL1 +#define FORWARD_CTL1_OFFSET 0x0624 +#define FORWARD_CTL1_E_LENGTH 4 +#define FORWARD_CTL1_E_OFFSET 0 +#define FORWARD_CTL1_NR_E 1 + +#define BC_FLOOD_DP +#define FORWARD_CTL1_BC_FLOOD_DP_BOFFSET 16 +#define FORWARD_CTL1_BC_FLOOD_DP_BLEN 7 +#define FORWARD_CTL1_BC_FLOOD_DP_FLAG HSL_RW + +//####### +#define ISISC_PHY_MODE_PHY_ID 4 +#define ISISC_LPI_PORT1_OFFSET 4 +#define ISISC_LPI_BIT_STEP 2 + +/* ISIS Mask Control Register */ +#define MASK_CTL +#define MASK_CTL_ID 0 +#define MASK_CTL_OFFSET 0x0000 +#define MASK_CTL_E_LENGTH 4 +#define MASK_CTL_E_OFFSET 0 +#define MASK_CTL_NR_E 1 + +#define DEVICE_ID +#define MASK_CTL_DEVICE_ID_BOFFSET 8 +#define MASK_CTL_DEVICE_ID_BLEN 8 +#define MASK_CTL_DEVICE_ID_FLAG HSL_RO + +#define REV_ID +#define MASK_CTL_REV_ID_BOFFSET 0 +#define MASK_CTL_REV_ID_BLEN 8 +#define MASK_CTL_REV_ID_FLAG HSL_RO + +/* EEE control Register */ +#define EEE_CTL +#define EEE_CTL_OFFSET 0x0100 +#define EEE_CTL_E_LENGTH 4 +#define EEE_CTL_E_OFFSET 0 +#define EEE_CTL_NR_E 1 + +/* Port Status Register */ +#define PORT_STATUS +#define PORT_STATUS_OFFSET 0x007c +#define PORT_STATUS_E_LENGTH 4 +#define PORT_STATUS_E_OFFSET 0x0004 +#define PORT_STATUS_NR_E 7 + +#define FLOW_LINK_EN +#define PORT_STATUS_FLOW_LINK_EN_BOFFSET 12 +#define PORT_STATUS_FLOW_LINK_EN_BLEN 1 +#define PORT_STATUS_FLOW_LINK_EN_FLAG HSL_RW + +#define DUPLEX_MODE +#define PORT_STATUS_DUPLEX_MODE_BOFFSET 6 +#define PORT_STATUS_DUPLEX_MODE_BLEN 1 +#define PORT_STATUS_DUPLEX_MODE_FLAG HSL_RW + +#define SPEED_MODE +#define PORT_STATUS_SPEED_MODE_BOFFSET 0 +#define PORT_STATUS_SPEED_MODE_BLEN 2 +#define PORT_STATUS_SPEED_MODE_FLAG HSL_RW + +#define LEAVE_EN_OFFSET 2 +#define JOIN_EN_OFFSET 1 +#define IGMP_MLD_EN_OFFSET 0 + +/* Port HOL CTL0 Register */ +#define PORT_HOL_CTL0 +#define PORT_HOL_CTL0_OFFSET 0x0970 +#define PORT_HOL_CTL0_E_LENGTH 4 +#define PORT_HOL_CTL0_E_OFFSET 0x0008 +#define PORT_HOL_CTL0_NR_E 7 + +#define PORT_DESC_NR +#define PORT_HOL_CTL0_PORT_DESC_NR_BOFFSET 24 +#define PORT_HOL_CTL0_PORT_DESC_NR_BLEN 8 +#define PORT_HOL_CTL0_PORT_DESC_NR_FLAG HSL_RW + +/* Port HOL CTL1 Register */ +#define PORT_HOL_CTL1 +#define PORT_HOL_CTL1_OFFSET 0x0974 +#define PORT_HOL_CTL1_E_LENGTH 4 +#define PORT_HOL_CTL1_E_OFFSET 0x0008 +#define PORT_HOL_CTL1_NR_E 7 + +#define PORT_RED_EN +#define PORT_HOL_CTL1_PORT_RED_EN_BOFFSET 8 +#define PORT_HOL_CTL1_PORT_RED_EN_BLEN 1 +#define PORT_HOL_CTL1_PORT_RED_EN_FLAG HSL_RW + +#define PORT_IN_DESC_EN +#define PORT_HOL_CTL1_PORT_IN_DESC_EN_BOFFSET 0 +#define PORT_HOL_CTL1_PORT_IN_DESC_EN_BLEN 6 +#define PORT_HOL_CTL1_PORT_IN_DESC_EN_FLAG HSL_RW + +#define ISISC_QOS_PORT_RX_BUFFER_MAX 504 +#define ISISC_QOS_PORT_TX_BUFFER_MAX 2040 +#define ISISC_QOS_HOL_STEP 8 +#define ISISC_QOS_HOL_MOD 3 + +typedef enum { + FAL_NO_HEADER_EN = 0, + FAL_ONLY_MANAGE_FRAME_EN, + FAL_ALL_TYPE_FRAME_EN +} port_header_mode_t; + +struct port_phy_status +{ + u32 link_status; + fal_port_speed_t speed; + fal_port_duplex_t duplex; + bool tx_flowctrl; + bool rx_flowctrl; +}; + + +/**************************************************************************** + * + * 1) PinCtrl/TLMM Register Definition + * + ****************************************************************************/ +/* TLMM_GPIO_CFGn */ +#define TLMM_GPIO_CFGN +#define TLMM_GPIO_CFGN_OFFSET 0xC400000 +#define TLMM_GPIO_CFGN_E_LENGTH 4 +#define TLMM_GPIO_CFGN_E_OFFSET 0x1000 +#define TLMM_GPIO_CFGN_NR_E 80 + +#define GPIO_HIHYS_EN +#define TLMM_GPIO_CFGN_GPIO_HIHYS_EN_BOFFSET 10 +#define TLMM_GPIO_CFGN_GPIO_HIHYS_EN_BLEN 1 +#define TLMM_GPIO_CFGN_GPIO_HIHYS_EN_FLAG HSL_RW + +#define GPIO_OEA +#define TLMM_GPIO_CFGN_GPIO_OEA_BOFFSET 9 +#define TLMM_GPIO_CFGN_GPIO_OEA_BLEN 1 +#define TLMM_GPIO_CFGN_GPIO_OEA_FLAG HSL_RW + +#define DRV_STRENGTH +#define TLMM_GPIO_CFGN_DRV_STRENGTH_BOFFSET 6 +#define TLMM_GPIO_CFGN_DRV_STRENGTH_BLEN 3 +#define TLMM_GPIO_CFGN_DRV_STRENGTH_FLAG HSL_RW + +enum QCA8084_TLMM_GPIO_CFGN_DRV_STRENGTH { + QCA8084_TLMM_GPIO_CFGN_DRV_STRENGTH_2_MA, + QCA8084_TLMM_GPIO_CFGN_DRV_STRENGTH_4_MA, + QCA8084_TLMM_GPIO_CFGN_DRV_STRENGTH_6_MA, + QCA8084_TLMM_GPIO_CFGN_DRV_STRENGTH_8_MA, + QCA8084_TLMM_GPIO_CFGN_DRV_STRENGTH_10_MA, + QCA8084_TLMM_GPIO_CFGN_DRV_STRENGTH_12_MA, + QCA8084_TLMM_GPIO_CFGN_DRV_STRENGTH_14_MA, + QCA8084_TLMM_GPIO_CFGN_DRV_STRENGTH_16_MA, +}; + +#define FUNC_SEL +#define TLMM_GPIO_CFGN_FUNC_SEL_BOFFSET 2 +#define TLMM_GPIO_CFGN_FUNC_SEL_BLEN 4 +#define TLMM_GPIO_CFGN_FUNC_SEL_FLAG HSL_RW + +#define GPIO_PULL +#define TLMM_GPIO_CFGN_GPIO_PULL_BOFFSET 0 +#define TLMM_GPIO_CFGN_GPIO_PULL_BLEN 2 +#define TLMM_GPIO_CFGN_GPIO_PULL_FLAG HSL_RW + +enum QCA8084_QCA8084_PIN_CONFIG_PARAM { + QCA8084_TLMM_GPIO_CFGN_GPIO_PULL_DISABLE, //Disables all pull + QCA8084_TLMM_GPIO_CFGN_GPIO_PULL_DOWN, + QCA8084_TLMM_GPIO_CFGN_GPIO_PULL_BUS_HOLD, //Weak Keepers + QCA8084_TLMM_GPIO_CFGN_GPIO_PULL_UP, +}; + + +/* TLMM_GPIO_IN_OUTn */ +#define TLMM_GPIO_IN_OUTN +#define TLMM_GPIO_IN_OUTN_OFFSET 0xC400004 +#define TLMM_GPIO_IN_OUTN_E_LENGTH 4 +#define TLMM_GPIO_IN_OUTN_E_OFFSET 0x1000 +#define TLMM_GPIO_IN_OUTN_NR_E 80 + +#define GPIO_OUTE +#define TLMM_GPIO_IN_OUTN_GPIO_OUTE_BOFFSET 1 +#define TLMM_GPIO_IN_OUTN_GPIO_OUTE_BLEN 1 +#define TLMM_GPIO_IN_OUTN_GPIO_OUTE_FLAG HSL_RW + +#define GPIO_IN +#define TLMM_GPIO_IN_OUTN_GPIO_IN_BOFFSET 0 +#define TLMM_GPIO_IN_OUTN_GPIO_IN_BLEN 1 +#define TLMM_GPIO_IN_OUTN_GPIO_IN_FLAG HSL_R + +/* TLMM_CLK_GATE_EN */ +#define TLMM_CLK_GATE_EN +#define TLMM_CLK_GATE_EN_OFFSET 0xC500000 +#define TLMM_CLK_GATE_EN_E_LENGTH 4 +#define TLMM_CLK_GATE_EN_E_OFFSET 0 +#define TLMM_CLK_GATE_EN_NR_E 1 + +#define AHB_HCLK_EN +#define TLMM_CLK_GATE_EN_AHB_HCLK_EN_BOFFSET 2 +#define TLMM_CLK_GATE_EN_AHB_HCLK_EN_BLEN 1 +#define TLMM_CLK_GATE_EN_AHB_HCLK_EN_FLAG HSL_RW + +#define SUMMARY_INTR_EN +#define TLMM_CLK_GATE_EN_SUMMARY_INTR_EN_BOFFSET 1 +#define TLMM_CLK_GATE_EN_SUMMARY_INTR_EN_BLEN 1 +#define TLMM_CLK_GATE_EN_SUMMARY_INTR_EN_FLAG HSL_RW + +#define CRIF_READ_EN +#define TLMM_CLK_GATE_EN_CRIF_READ_EN_BOFFSET 0 +#define TLMM_CLK_GATE_EN_CRIF_READ_EN_BLEN 1 +#define TLMM_CLK_GATE_EN_CRIF_READ_EN_FLAG HSL_RW + +/* TLMM_HW_REVISION_NUMBER */ +#define TLMM_HW_REVISION_NUMBER +#define TLMM_HW_REVISION_NUMBER_OFFSET 0xC510010 +#define TLMM_HW_REVISION_NUMBER_E_LENGTH 4 +#define TLMM_HW_REVISION_NUMBER_E_OFFSET 0 +#define TLMM_HW_REVISION_NUMBER_NR_E 1 + +#define VERSION_ID +#define TLMM_HW_REVISION_NUMBER_VERSION_ID_BOFFSET 28 +#define TLMM_HW_REVISION_NUMBER_VERSION_ID_BLEN 4 +#define TLMM_HW_REVISION_NUMBER_VERSION_ID_FLAG HSL_R + +#define PARTNUM +#define TLMM_HW_REVISION_NUMBER_PARTNUM_BOFFSET 12 +#define TLMM_HW_REVISION_NUMBER_PARTNUM_BLEN 16 +#define TLMM_HW_REVISION_NUMBER_PARTNUM_FLAG HSL_R + +#define MFG_ID +#define TLMM_HW_REVISION_NUMBER_MFG_ID_BOFFSET 1 +#define TLMM_HW_REVISION_NUMBER_MFG_ID_BLEN 11 +#define TLMM_HW_REVISION_NUMBER_MFG_ID_FLAG HSL_R + +#define START_BIT +#define TLMM_HW_REVISION_NUMBER_START_BIT_BOFFSET 0 +#define TLMM_HW_REVISION_NUMBER_START_BIT_BLEN 1 +#define TLMM_HW_REVISION_NUMBER_START_BIT_FLAG HSL_R + + +/**************************************************************************** + * + * 2) PINs Functions Selection GPIO_CFG[5:2] (FUNC_SEL) + * + ****************************************************************************/ +/*GPIO*/ +#define QCA8084_PIN_FUNC_GPIO0 0 +#define QCA8084_PIN_FUNC_GPIO1 0 +#define QCA8084_PIN_FUNC_GPIO2 0 +#define QCA8084_PIN_FUNC_GPIO3 0 +#define QCA8084_PIN_FUNC_GPIO4 0 +#define QCA8084_PIN_FUNC_GPIO5 0 +#define QCA8084_PIN_FUNC_GPIO6 0 +#define QCA8084_PIN_FUNC_GPIO7 0 +#define QCA8084_PIN_FUNC_GPIO8 0 +#define QCA8084_PIN_FUNC_GPIO9 0 +#define QCA8084_PIN_FUNC_GPIO10 0 +#define QCA8084_PIN_FUNC_GPIO11 0 +#define QCA8084_PIN_FUNC_GPIO12 0 +#define QCA8084_PIN_FUNC_GPIO13 0 +#define QCA8084_PIN_FUNC_GPIO14 0 +#define QCA8084_PIN_FUNC_GPIO15 0 +#define QCA8084_PIN_FUNC_GPIO16 0 +#define QCA8084_PIN_FUNC_GPIO17 0 +#define QCA8084_PIN_FUNC_GPIO18 0 +#define QCA8084_PIN_FUNC_GPIO19 0 +#define QCA8084_PIN_FUNC_GPIO20 0 +#define QCA8084_PIN_FUNC_GPIO21 0 + +/*MINIMUM CONCURRENCY SET FUNCTION*/ +#define QCA8084_PIN_FUNC_INTN_WOL 1 +#define QCA8084_PIN_FUNC_INTN 1 +#define QCA8084_PIN_FUNC_P0_LED_0 1 +#define QCA8084_PIN_FUNC_P1_LED_0 1 +#define QCA8084_PIN_FUNC_P2_LED_0 1 +#define QCA8084_PIN_FUNC_P3_LED_0 1 +#define QCA8084_PIN_FUNC_PPS_IN 1 +#define QCA8084_PIN_FUNC_TOD_IN 1 +#define QCA8084_PIN_FUNC_RTC_REFCLK_IN 1 +#define QCA8084_PIN_FUNC_P0_PPS_OUT 1 +#define QCA8084_PIN_FUNC_P1_PPS_OUT 1 +#define QCA8084_PIN_FUNC_P2_PPS_OUT 1 +#define QCA8084_PIN_FUNC_P3_PPS_OUT 1 +#define QCA8084_PIN_FUNC_P0_TOD_OUT 1 +#define QCA8084_PIN_FUNC_P0_CLK125_TDI 1 +#define QCA8084_PIN_FUNC_P0_SYNC_CLKO_PTP 1 +#define QCA8084_PIN_FUNC_P0_LED_1 1 +#define QCA8084_PIN_FUNC_P1_LED_1 1 +#define QCA8084_PIN_FUNC_P2_LED_1 1 +#define QCA8084_PIN_FUNC_P3_LED_1 1 +#define QCA8084_PIN_FUNC_MDC_M 1 +#define QCA8084_PIN_FUNC_MDO_M 1 + +/*ALT FUNCTION K*/ +#define QCA8084_PIN_FUNC_EVENT_TRG_I 2 +#define QCA8084_PIN_FUNC_P0_EVENT_TRG_O 2 +#define QCA8084_PIN_FUNC_P1_EVENT_TRG_O 2 +#define QCA8084_PIN_FUNC_P2_EVENT_TRG_O 2 +#define QCA8084_PIN_FUNC_P3_EVENT_TRG_O 2 +#define QCA8084_PIN_FUNC_P1_TOD_OUT 2 +#define QCA8084_PIN_FUNC_P1_CLK125_TDI 2 +#define QCA8084_PIN_FUNC_P1_SYNC_CLKO_PTP 2 +#define QCA8084_PIN_FUNC_P0_INTN_WOL 2 +#define QCA8084_PIN_FUNC_P1_INTN_WOL 2 +#define QCA8084_PIN_FUNC_P2_INTN_WOL 2 +#define QCA8084_PIN_FUNC_P3_INTN_WOL 2 + +/*ALT FUNCTION L*/ +#define QCA8084_PIN_FUNC_P2_TOD_OUT 3 +#define QCA8084_PIN_FUNC_P2_CLK125_TDI 3 +#define QCA8084_PIN_FUNC_P2_SYNC_CLKO_PTP 3 + +/*ALT FUNCTION M*/ +#define QCA8084_PIN_FUNC_P3_TOD_OUT 4 +#define QCA8084_PIN_FUNC_P3_CLK125_TDI 4 +#define QCA8084_PIN_FUNC_P3_SYNC_CLKO_PTP 4 + +/*ALT FUNCTION N*/ +#define QCA8084_PIN_FUNC_P0_LED_2 3 +#define QCA8084_PIN_FUNC_P1_LED_2 2 +#define QCA8084_PIN_FUNC_P2_LED_2 2 +#define QCA8084_PIN_FUNC_P3_LED_2 3 + +/*ALT FUNCTION O*/ + + +/*ALT FUNCTION DEBUG BUS OUT*/ +#define QCA8084_PIN_FUNC_DBG_OUT_CLK 2 +#define QCA8084_PIN_FUNC_DBG_BUS_OUT0 2 +#define QCA8084_PIN_FUNC_DBG_BUS_OUT1 2 +#define QCA8084_PIN_FUNC_DBG_BUS_OUT12 2 +#define QCA8084_PIN_FUNC_DBG_BUS_OUT13 2 +#define QCA8084_PIN_FUNC_DBG_BUS_OUT2 3 +#define QCA8084_PIN_FUNC_DBG_BUS_OUT3 4 +#define QCA8084_PIN_FUNC_DBG_BUS_OUT4 3 +#define QCA8084_PIN_FUNC_DBG_BUS_OUT5 3 +#define QCA8084_PIN_FUNC_DBG_BUS_OUT6 3 +#define QCA8084_PIN_FUNC_DBG_BUS_OUT7 5 +#define QCA8084_PIN_FUNC_DBG_BUS_OUT8 5 +#define QCA8084_PIN_FUNC_DBG_BUS_OUT9 5 +#define QCA8084_PIN_FUNC_DBG_BUS_OUT10 3 +#define QCA8084_PIN_FUNC_DBG_BUS_OUT11 3 +#define QCA8084_PIN_FUNC_DBG_BUS_OUT14 2 +#define QCA8084_PIN_FUNC_DBG_BUS_OUT15 2 + + +/**************************************************************************** + * + * 2) PINs Functions Selection GPIO_CFG[5:2] (FUNC_SEL) + * + ****************************************************************************/ +struct qca8084_pinctrl_setting_mux { + u32 pin; + u32 func; +}; + +struct qca8084_pinctrl_setting_configs { + u32 pin; + u32 num_configs; + u64 *configs; +}; + +enum qca8084_pin_config_param { + QCA8084_PIN_CONFIG_BIAS_BUS_HOLD, + QCA8084_PIN_CONFIG_BIAS_DISABLE, + QCA8084_PIN_CONFIG_BIAS_HIGH_IMPEDANCE, + QCA8084_PIN_CONFIG_BIAS_PULL_DOWN, + QCA8084_PIN_CONFIG_BIAS_PULL_PIN_DEFAULT, + QCA8084_PIN_CONFIG_BIAS_PULL_UP, + QCA8084_PIN_CONFIG_DRIVE_OPEN_DRAIN, + QCA8084_PIN_CONFIG_DRIVE_OPEN_SOURCE, + QCA8084_PIN_CONFIG_DRIVE_PUSH_PULL, + QCA8084_PIN_CONFIG_DRIVE_STRENGTH, + QCA8084_PIN_CONFIG_DRIVE_STRENGTH_UA, + QCA8084_PIN_CONFIG_INPUT_DEBOUNCE, + QCA8084_PIN_CONFIG_INPUT_ENABLE, + QCA8084_PIN_CONFIG_INPUT_SCHMITT, + QCA8084_PIN_CONFIG_INPUT_SCHMITT_ENABLE, + QCA8084_PIN_CONFIG_LOW_POWER_MODE, + QCA8084_PIN_CONFIG_OUTPUT_ENABLE, + QCA8084_PIN_CONFIG_OUTPUT, + QCA8084_PIN_CONFIG_POWER_SOURCE, + QCA8084_PIN_CONFIG_SLEEP_HARDWARE_STATE, + QCA8084_PIN_CONFIG_SLEW_RATE, + QCA8084_PIN_CONFIG_SKEW_DELAY, + QCA8084_PIN_CONFIG_PERSIST_STATE, + QCA8084_PIN_CONFIG_END = 0x7F, + QCA8084_PIN_CONFIG_MAX = 0xFF, +}; + +enum qca8084_pinctrl_map_type { + QCA8084_PIN_MAP_TYPE_INVALID, + QCA8084_PIN_MAP_TYPE_DUMMY_STATE, + QCA8084_PIN_MAP_TYPE_MUX_GROUP, + QCA8084_PIN_MAP_TYPE_CONFIGS_PIN, + QCA8084_PIN_MAP_TYPE_CONFIGS_GROUP, +}; + +struct qca8084_pinctrl_setting { + enum qca8084_pinctrl_map_type type; + union { + struct qca8084_pinctrl_setting_mux mux; + struct qca8084_pinctrl_setting_configs configs; + } data; +}; + +#define QCA8084_PIN_SETTING_MUX(pin_id, function) \ + { \ + .type = QCA8084_PIN_MAP_TYPE_MUX_GROUP, \ + .data.mux = { \ + .pin = pin_id, \ + .func = function \ + }, \ + } + +#define QCA8084_PIN_SETTING_CONFIG(pin_id, cfgs) \ + { \ + .type = QCA8084_PIN_MAP_TYPE_CONFIGS_PIN, \ + .data.configs = { \ + .pin = pin_id, \ + .configs = cfgs, \ + .num_configs = ARRAY_SIZE(cfgs) \ + }, \ + } + +int qca8084_gpio_set_bit( u32 pin, u32 value); +int qca8084_gpio_get_bit( u32 pin, u32 *data); +int qca8084_gpio_pin_mux_set( u32 pin, u32 func); +int qca8084_gpio_pin_cfg_set_bias( u32 pin, u32 bias); +int qca8084_gpio_pin_cfg_get_bias( u32 pin, u32 *bias); +int qca8084_gpio_pin_cfg_set_drvs( u32 pin, u32 drvs); +int qca8084_gpio_pin_cfg_get_drvs( u32 pin, u32 *drvs); +int qca8084_gpio_pin_cfg_set_oe( u32 pin, bool oe); +int qca8084_gpio_pin_cfg_get_oe( u32 pin, bool *oe); +int ipq_qca8084_pinctrl_init(void); + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* _QCA8084_PHY_H_ */ diff --git a/sources/uboot-be550/drivers/net/ipq_common/ipq_qca8084_clk.c b/sources/uboot-be550/drivers/net/ipq_common/ipq_qca8084_clk.c new file mode 100644 index 00000000..b11df733 --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq_common/ipq_qca8084_clk.c @@ -0,0 +1,1299 @@ +/* + * Copyright (c) 2022, The Linux Foundation. All rights reserved. + + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. +*/ +#include "ipq_phy.h" +#include "ipq_qca8084_clk.h" +#include +#include +#include +#include + +#define QCA8084_PORT_CLK_CBC_MAX 8 +/* 2 uniphy with rx and tx */ +#define QCA8084_UNIPHY_INSTANCE 2 + +#ifdef DEBUG +#define pr_debug(fmt, args...) printf(fmt, ##args); +#else +#define pr_debug(fmt, args...) +#endif + +extern uint32_t ipq_mii_read(uint32_t reg); +extern void ipq_mii_write(uint32_t reg, uint32_t val); +extern void ipq_mii_update(uint32_t reg, uint32_t mask, uint32_t val); + +static uint64_t qca8084_uniphy_raw_clock[QCA8084_UNIPHY_INSTANCE * 2] = {0}; + +static const unsigned long qca8084_switch_core_support_rates[] = { + UQXGMII_SPEED_2500M_CLK, +}; + +static const unsigned long qca8084_cpuport_clk_support_rates[] = { + UQXGMII_SPEED_10M_CLK, + UQXGMII_SPEED_100M_CLK, + UQXGMII_SPEED_1000M_CLK, + UQXGMII_SPEED_2500M_CLK, +}; + +static const unsigned long qca8084_phyport_clk_support_rates[] = { + UQXGMII_SPEED_10M_CLK, + UQXGMII_SPEED_100M_CLK, + UQXGMII_SPEED_1000M_CLK, + UQXGMII_SPEED_2500M_CLK, + UQXGMII_XPCS_SPEED_2500M_CLK, +}; + +static const unsigned long qca8084_ahb_clk_support_rates[] = { + QCA8084_AHB_CLK_RATE_104P17M +}; + +static const unsigned long qca8084_sys_clk_support_rates[] = { + QCA8084_SYS_CLK_RATE_25M, +}; + +static const struct qca8084_parent_data qca8084_switch_core_pdata[] = { + { QCA8084_XO_CLK_RATE_50M, QCA8084_P_XO, 0 }, + { UQXGMII_SPEED_2500M_CLK, QCA8084_P_UNIPHY1_TX312P5M, 1 }, +}; + +static const struct qca8084_parent_data qca8084_mac0_tx_clk_pdata[] = { + { QCA8084_XO_CLK_RATE_50M, QCA8084_P_XO, 0 } , + { UQXGMII_SPEED_1000M_CLK, QCA8084_P_UNIPHY1_TX, 2 }, + { UQXGMII_SPEED_2500M_CLK, QCA8084_P_UNIPHY1_TX, 2 }, +}; + +static const struct qca8084_parent_data qca8084_mac0_rx_clk_pdata[] = { + { QCA8084_XO_CLK_RATE_50M, QCA8084_P_XO, 0 } , + { UQXGMII_SPEED_1000M_CLK, QCA8084_P_UNIPHY1_RX, 1 }, + { UQXGMII_SPEED_1000M_CLK, QCA8084_P_UNIPHY1_TX, 2 }, + { UQXGMII_SPEED_2500M_CLK, QCA8084_P_UNIPHY1_RX, 1 }, + { UQXGMII_SPEED_2500M_CLK, QCA8084_P_UNIPHY1_TX, 2 }, +}; + +/* port 1, 2, 3 rx/tx clock have the same parents */ +static const struct qca8084_parent_data qca8084_mac1_tx_clk_pdata[] = { + { QCA8084_XO_CLK_RATE_50M, QCA8084_P_XO, 0 } , + { UQXGMII_SPEED_2500M_CLK, QCA8084_P_UNIPHY1_TX312P5M, 6 }, + { UQXGMII_SPEED_2500M_CLK, QCA8084_P_UNIPHY1_RX312P5M, 7 }, +}; + +static const struct qca8084_parent_data qca8084_mac1_rx_clk_pdata[] = { + { QCA8084_XO_CLK_RATE_50M, QCA8084_P_XO, 0 }, + { UQXGMII_SPEED_2500M_CLK, QCA8084_P_UNIPHY1_TX312P5M, 6 }, +}; + +static const struct qca8084_parent_data qca8084_mac4_tx_clk_pdata[] = { + { QCA8084_XO_CLK_RATE_50M, QCA8084_P_XO, 0 }, + { UQXGMII_SPEED_1000M_CLK, QCA8084_P_UNIPHY0_RX, 1 }, + { UQXGMII_SPEED_2500M_CLK, QCA8084_P_UNIPHY0_RX, 1 }, + { UQXGMII_SPEED_2500M_CLK, QCA8084_P_UNIPHY1_TX312P5M, 3 }, + { UQXGMII_SPEED_2500M_CLK, QCA8084_P_UNIPHY1_RX312P5M, 7 }, +}; + +static const struct qca8084_parent_data qca8084_mac4_rx_clk_pdata[] = { + { QCA8084_XO_CLK_RATE_50M, QCA8084_P_XO, 0 }, + { UQXGMII_SPEED_1000M_CLK, QCA8084_P_UNIPHY0_TX, 2 }, + { UQXGMII_SPEED_2500M_CLK, QCA8084_P_UNIPHY0_TX, 2 }, + { UQXGMII_SPEED_2500M_CLK, QCA8084_P_UNIPHY1_TX312P5M, 3 }, +}; + +static const struct qca8084_parent_data qca8084_mac5_tx_clk_pdata[] = { + { QCA8084_XO_CLK_RATE_50M, QCA8084_P_XO, 0 }, + { UQXGMII_SPEED_1000M_CLK, QCA8084_P_UNIPHY0_TX, 2 }, + { UQXGMII_SPEED_2500M_CLK, QCA8084_P_UNIPHY0_TX, 2 }, +}; + +static const struct qca8084_parent_data qca8084_mac5_rx_clk_pdata[] = { + { QCA8084_XO_CLK_RATE_50M, QCA8084_P_XO, 0 }, + { UQXGMII_SPEED_1000M_CLK, QCA8084_P_UNIPHY0_RX, 1 }, + { UQXGMII_SPEED_1000M_CLK, QCA8084_P_UNIPHY0_TX, 2 }, + { UQXGMII_SPEED_2500M_CLK, QCA8084_P_UNIPHY0_RX, 1 }, + { UQXGMII_SPEED_2500M_CLK, QCA8084_P_UNIPHY0_TX, 2 }, +}; + +static const struct qca8084_parent_data qca8084_ahb_clk_pdata[] = { + { QCA8084_XO_CLK_RATE_50M, QCA8084_P_XO, 0 }, + { UQXGMII_SPEED_2500M_CLK, QCA8084_P_UNIPHY1_TX312P5M, 2 }, +}; + +static const struct qca8084_parent_data qca8084_sys_clk_pdata[] = { + { QCA8084_XO_CLK_RATE_50M, QCA8084_P_XO, 0 }, +}; + +static struct clk_lookup qca8084_clk_lookup_table[] = { + /* switch core clock */ + CLK_LOOKUP(4, 0, 8, CBCR_CLK_RESET, + QCA8084_SWITCH_CORE_CLK, + qca8084_switch_core_support_rates, ARRAY_SIZE(qca8084_switch_core_support_rates), + qca8084_switch_core_pdata, ARRAY_SIZE(qca8084_switch_core_pdata)), + CLK_LOOKUP(4, 0, 0x10, CBCR_CLK_RESET, + QCA8084_APB_BRIDGE_CLK, + qca8084_switch_core_support_rates, ARRAY_SIZE(qca8084_switch_core_support_rates), + qca8084_switch_core_pdata, ARRAY_SIZE(qca8084_switch_core_pdata)), + /* port 0 tx clock */ + CLK_LOOKUP(0x18, 0x1c, 0x20, CBCR_CLK_RESET, + QCA8084_MAC0_TX_CLK, + qca8084_cpuport_clk_support_rates, ARRAY_SIZE(qca8084_cpuport_clk_support_rates), + qca8084_mac0_tx_clk_pdata, ARRAY_SIZE(qca8084_mac0_tx_clk_pdata)), + CLK_LOOKUP(0x18, 0x1c, 0x24, CBCR_CLK_RESET, + QCA8084_MAC0_TX_UNIPHY1_CLK, + qca8084_cpuport_clk_support_rates, ARRAY_SIZE(qca8084_cpuport_clk_support_rates), + qca8084_mac0_tx_clk_pdata, ARRAY_SIZE(qca8084_mac0_tx_clk_pdata)), + /* port 0 rx clock */ + CLK_LOOKUP(0x2c, 0x30, 0x34, CBCR_CLK_RESET, + QCA8084_MAC0_RX_CLK, + qca8084_cpuport_clk_support_rates, ARRAY_SIZE(qca8084_cpuport_clk_support_rates), + qca8084_mac0_rx_clk_pdata, ARRAY_SIZE(qca8084_mac0_rx_clk_pdata)), + CLK_LOOKUP(0x2c, 0x30, 0x3c, CBCR_CLK_RESET, + QCA8084_MAC0_RX_UNIPHY1_CLK, + qca8084_cpuport_clk_support_rates, ARRAY_SIZE(qca8084_cpuport_clk_support_rates), + qca8084_mac0_rx_clk_pdata, ARRAY_SIZE(qca8084_mac0_rx_clk_pdata)), + /* port 1 tx clock */ + CLK_LOOKUP(0x44, 0x48, 0x50, CBCR_CLK_RESET, + QCA8084_MAC1_UNIPHY1_CH0_RX_CLK, + qca8084_phyport_clk_support_rates, ARRAY_SIZE(qca8084_phyport_clk_support_rates), + qca8084_mac1_tx_clk_pdata, ARRAY_SIZE(qca8084_mac1_tx_clk_pdata)), + CLK_LOOKUP(0x44, 0x48, 0x54, CBCR_CLK_RESET, + QCA8084_MAC1_TX_CLK, + qca8084_phyport_clk_support_rates, ARRAY_SIZE(qca8084_phyport_clk_support_rates), + qca8084_mac1_tx_clk_pdata, ARRAY_SIZE(qca8084_mac1_tx_clk_pdata)), + CLK_LOOKUP(0x44, 0x48, 0x58, CBCR_CLK_RESET, + QCA8084_MAC1_GEPHY0_TX_CLK, + qca8084_phyport_clk_support_rates, ARRAY_SIZE(qca8084_phyport_clk_support_rates), + qca8084_mac1_tx_clk_pdata, ARRAY_SIZE(qca8084_mac1_tx_clk_pdata)), + CLK_LOOKUP(0x44, 0x4c, 0x5c, CBCR_CLK_RESET, + QCA8084_MAC1_UNIPHY1_CH0_XGMII_RX_CLK, + qca8084_phyport_clk_support_rates, ARRAY_SIZE(qca8084_phyport_clk_support_rates), + qca8084_mac1_tx_clk_pdata, ARRAY_SIZE(qca8084_mac1_tx_clk_pdata)), + /* port 1 rx clock */ + CLK_LOOKUP(0x64, 0x68, 0x70, CBCR_CLK_RESET, + QCA8084_MAC1_UNIPHY1_CH0_TX_CLK, + qca8084_phyport_clk_support_rates, ARRAY_SIZE(qca8084_phyport_clk_support_rates), + qca8084_mac1_rx_clk_pdata, ARRAY_SIZE(qca8084_mac1_rx_clk_pdata)), + CLK_LOOKUP(0x64, 0x68, 0x74, CBCR_CLK_RESET, + QCA8084_MAC1_RX_CLK, + qca8084_phyport_clk_support_rates, ARRAY_SIZE(qca8084_phyport_clk_support_rates), + qca8084_mac1_rx_clk_pdata, ARRAY_SIZE(qca8084_mac1_rx_clk_pdata)), + CLK_LOOKUP(0x64, 0x68, 0x78, CBCR_CLK_RESET, + QCA8084_MAC1_GEPHY0_RX_CLK, + qca8084_phyport_clk_support_rates, ARRAY_SIZE(qca8084_phyport_clk_support_rates), + qca8084_mac1_rx_clk_pdata, ARRAY_SIZE(qca8084_mac1_rx_clk_pdata)), + CLK_LOOKUP(0x64, 0x6c, 0x7c, CBCR_CLK_RESET, + QCA8084_MAC1_UNIPHY1_CH0_XGMII_TX_CLK, + qca8084_phyport_clk_support_rates, ARRAY_SIZE(qca8084_phyport_clk_support_rates), + qca8084_mac1_rx_clk_pdata, ARRAY_SIZE(qca8084_mac1_rx_clk_pdata)), + /* port 2 tx clock */ + CLK_LOOKUP(0x84, 0x88, 0x90, CBCR_CLK_RESET, + QCA8084_MAC2_UNIPHY1_CH1_RX_CLK, + qca8084_phyport_clk_support_rates, ARRAY_SIZE(qca8084_phyport_clk_support_rates), + qca8084_mac1_tx_clk_pdata, ARRAY_SIZE(qca8084_mac1_tx_clk_pdata)), + CLK_LOOKUP(0x84, 0x88, 0x94, CBCR_CLK_RESET, + QCA8084_MAC2_TX_CLK, + qca8084_phyport_clk_support_rates, ARRAY_SIZE(qca8084_phyport_clk_support_rates), + qca8084_mac1_tx_clk_pdata, ARRAY_SIZE(qca8084_mac1_tx_clk_pdata)), + CLK_LOOKUP(0x84, 0x88, 0x98, CBCR_CLK_RESET, + QCA8084_MAC2_GEPHY1_TX_CLK, + qca8084_phyport_clk_support_rates, ARRAY_SIZE(qca8084_phyport_clk_support_rates), + qca8084_mac1_tx_clk_pdata, ARRAY_SIZE(qca8084_mac1_tx_clk_pdata)), + CLK_LOOKUP(0x84, 0x8c, 0x9c, CBCR_CLK_RESET, + QCA8084_MAC2_UNIPHY1_CH1_XGMII_RX_CLK, + qca8084_phyport_clk_support_rates, ARRAY_SIZE(qca8084_phyport_clk_support_rates), + qca8084_mac1_tx_clk_pdata, ARRAY_SIZE(qca8084_mac1_tx_clk_pdata)), + /* port 2 rx clock */ + CLK_LOOKUP(0xa4, 0xa8, 0xb0, CBCR_CLK_RESET, + QCA8084_MAC2_UNIPHY1_CH1_TX_CLK, + qca8084_phyport_clk_support_rates, ARRAY_SIZE(qca8084_phyport_clk_support_rates), + qca8084_mac1_rx_clk_pdata, ARRAY_SIZE(qca8084_mac1_rx_clk_pdata)), + CLK_LOOKUP(0xa4, 0xa8, 0xb4, CBCR_CLK_RESET, + QCA8084_MAC2_RX_CLK, + qca8084_phyport_clk_support_rates, ARRAY_SIZE(qca8084_phyport_clk_support_rates), + qca8084_mac1_rx_clk_pdata, ARRAY_SIZE(qca8084_mac1_rx_clk_pdata)), + CLK_LOOKUP(0xa4, 0xa8, 0xb8, CBCR_CLK_RESET, + QCA8084_MAC2_GEPHY1_RX_CLK, + qca8084_phyport_clk_support_rates, ARRAY_SIZE(qca8084_phyport_clk_support_rates), + qca8084_mac1_rx_clk_pdata, ARRAY_SIZE(qca8084_mac1_rx_clk_pdata)), + CLK_LOOKUP(0xa4, 0xac, 0xbc, CBCR_CLK_RESET, + QCA8084_MAC2_UNIPHY1_CH1_XGMII_TX_CLK, + qca8084_phyport_clk_support_rates, ARRAY_SIZE(qca8084_phyport_clk_support_rates), + qca8084_mac1_rx_clk_pdata, ARRAY_SIZE(qca8084_mac1_rx_clk_pdata)), + /* port 3 tx clock */ + CLK_LOOKUP(0xc4, 0xc8, 0xd0, CBCR_CLK_RESET, + QCA8084_MAC3_UNIPHY1_CH2_RX_CLK, + qca8084_phyport_clk_support_rates, ARRAY_SIZE(qca8084_phyport_clk_support_rates), + qca8084_mac1_tx_clk_pdata, ARRAY_SIZE(qca8084_mac1_tx_clk_pdata)), + CLK_LOOKUP(0xc4, 0xc8, 0xd4, CBCR_CLK_RESET, + QCA8084_MAC3_TX_CLK, + qca8084_phyport_clk_support_rates, ARRAY_SIZE(qca8084_phyport_clk_support_rates), + qca8084_mac1_tx_clk_pdata, ARRAY_SIZE(qca8084_mac1_tx_clk_pdata)), + CLK_LOOKUP(0xc4, 0xc8, 0xd8, CBCR_CLK_RESET, + QCA8084_MAC3_GEPHY2_TX_CLK, + qca8084_phyport_clk_support_rates, ARRAY_SIZE(qca8084_phyport_clk_support_rates), + qca8084_mac1_tx_clk_pdata, ARRAY_SIZE(qca8084_mac1_tx_clk_pdata)), + CLK_LOOKUP(0xc4, 0xcc, 0xdc, CBCR_CLK_RESET, + QCA8084_MAC3_UNIPHY1_CH2_XGMII_RX_CLK, + qca8084_phyport_clk_support_rates, ARRAY_SIZE(qca8084_phyport_clk_support_rates), + qca8084_mac1_tx_clk_pdata, ARRAY_SIZE(qca8084_mac1_tx_clk_pdata)), + /* port 3 rx clock */ + CLK_LOOKUP(0xe4, 0xe8, 0xf0, CBCR_CLK_RESET, + QCA8084_MAC3_UNIPHY1_CH2_TX_CLK, + qca8084_phyport_clk_support_rates, ARRAY_SIZE(qca8084_phyport_clk_support_rates), + qca8084_mac1_rx_clk_pdata, ARRAY_SIZE(qca8084_mac1_rx_clk_pdata)), + CLK_LOOKUP(0xe4, 0xe8, 0xf4, CBCR_CLK_RESET, + QCA8084_MAC3_RX_CLK, + qca8084_phyport_clk_support_rates, ARRAY_SIZE(qca8084_phyport_clk_support_rates), + qca8084_mac1_rx_clk_pdata, ARRAY_SIZE(qca8084_mac1_rx_clk_pdata)), + CLK_LOOKUP(0xe4, 0xe8, 0xf8, CBCR_CLK_RESET, + QCA8084_MAC3_GEPHY2_RX_CLK, + qca8084_phyport_clk_support_rates, ARRAY_SIZE(qca8084_phyport_clk_support_rates), + qca8084_mac1_rx_clk_pdata, ARRAY_SIZE(qca8084_mac1_rx_clk_pdata)), + CLK_LOOKUP(0xe4, 0xec, 0xfc, CBCR_CLK_RESET, + QCA8084_MAC3_UNIPHY1_CH2_XGMII_TX_CLK, + qca8084_phyport_clk_support_rates, ARRAY_SIZE(qca8084_phyport_clk_support_rates), + qca8084_mac1_rx_clk_pdata, ARRAY_SIZE(qca8084_mac1_rx_clk_pdata)), + /* port 4 tx clock */ + CLK_LOOKUP(0x104, 0x108, 0x110, CBCR_CLK_RESET, + QCA8084_MAC4_UNIPHY1_CH3_RX_CLK, + qca8084_phyport_clk_support_rates, ARRAY_SIZE(qca8084_phyport_clk_support_rates), + qca8084_mac4_tx_clk_pdata, ARRAY_SIZE(qca8084_mac4_tx_clk_pdata)), + CLK_LOOKUP(0x104, 0x108, 0x114, CBCR_CLK_RESET, + QCA8084_MAC4_TX_CLK, + qca8084_phyport_clk_support_rates, ARRAY_SIZE(qca8084_phyport_clk_support_rates), + qca8084_mac4_tx_clk_pdata, ARRAY_SIZE(qca8084_mac4_tx_clk_pdata)), + CLK_LOOKUP(0x104, 0x108, 0x118, CBCR_CLK_RESET, + QCA8084_MAC4_GEPHY3_TX_CLK, + qca8084_phyport_clk_support_rates, ARRAY_SIZE(qca8084_phyport_clk_support_rates), + qca8084_mac4_tx_clk_pdata, ARRAY_SIZE(qca8084_mac4_tx_clk_pdata)), + CLK_LOOKUP(0x104, 0x10c, 0x11c, CBCR_CLK_RESET, + QCA8084_MAC4_UNIPHY1_CH3_XGMII_RX_CLK, + qca8084_phyport_clk_support_rates, ARRAY_SIZE(qca8084_phyport_clk_support_rates), + qca8084_mac4_tx_clk_pdata, ARRAY_SIZE(qca8084_mac4_tx_clk_pdata)), + /* port 4 rx clock */ + CLK_LOOKUP(0x124, 0x128, 0x130, CBCR_CLK_RESET, + QCA8084_MAC4_UNIPHY1_CH3_TX_CLK, + qca8084_phyport_clk_support_rates, ARRAY_SIZE(qca8084_phyport_clk_support_rates), + qca8084_mac4_rx_clk_pdata, ARRAY_SIZE(qca8084_mac4_rx_clk_pdata)), + CLK_LOOKUP(0x124, 0x128, 0x134, CBCR_CLK_RESET, + QCA8084_MAC4_RX_CLK, + qca8084_phyport_clk_support_rates, ARRAY_SIZE(qca8084_phyport_clk_support_rates), + qca8084_mac4_rx_clk_pdata, ARRAY_SIZE(qca8084_mac4_rx_clk_pdata)), + CLK_LOOKUP(0x124, 0x128, 0x138, CBCR_CLK_RESET, + QCA8084_MAC4_GEPHY3_RX_CLK, + qca8084_phyport_clk_support_rates, ARRAY_SIZE(qca8084_phyport_clk_support_rates), + qca8084_mac4_rx_clk_pdata, ARRAY_SIZE(qca8084_mac4_rx_clk_pdata)), + CLK_LOOKUP(0x124, 0x12c, 0x13c, CBCR_CLK_RESET, + QCA8084_MAC4_UNIPHY1_CH3_XGMII_TX_CLK, + qca8084_phyport_clk_support_rates, ARRAY_SIZE(qca8084_phyport_clk_support_rates), + qca8084_mac4_rx_clk_pdata, ARRAY_SIZE(qca8084_mac4_rx_clk_pdata)), + /* port 5 tx clock */ + CLK_LOOKUP(0x144, 0x148, 0x14c, CBCR_CLK_RESET, + QCA8084_MAC5_TX_CLK, + qca8084_cpuport_clk_support_rates, ARRAY_SIZE(qca8084_cpuport_clk_support_rates), + qca8084_mac5_tx_clk_pdata, ARRAY_SIZE(qca8084_mac5_tx_clk_pdata)), + CLK_LOOKUP(0x144, 0x148, 0x150, CBCR_CLK_RESET, + QCA8084_MAC5_TX_UNIPHY0_CLK, + qca8084_cpuport_clk_support_rates, ARRAY_SIZE(qca8084_cpuport_clk_support_rates), + qca8084_mac5_tx_clk_pdata, ARRAY_SIZE(qca8084_mac5_tx_clk_pdata)), + /* port 5 rx clock */ + CLK_LOOKUP(0x158, 0x15c, 0x160, CBCR_CLK_RESET, + QCA8084_MAC5_RX_CLK, + qca8084_cpuport_clk_support_rates, ARRAY_SIZE(qca8084_cpuport_clk_support_rates), + qca8084_mac5_rx_clk_pdata, ARRAY_SIZE(qca8084_mac5_rx_clk_pdata)), + CLK_LOOKUP(0x158, 0x15c, 0x164, CBCR_CLK_RESET, + QCA8084_MAC5_RX_UNIPHY0_CLK, + qca8084_cpuport_clk_support_rates, ARRAY_SIZE(qca8084_cpuport_clk_support_rates), + qca8084_mac5_rx_clk_pdata, ARRAY_SIZE(qca8084_mac5_rx_clk_pdata)), + /* AHB bridge clock */ + CLK_LOOKUP(0x16c, 0, 0x170, CBCR_CLK_RESET, + QCA8084_AHB_CLK, + qca8084_ahb_clk_support_rates, ARRAY_SIZE(qca8084_ahb_clk_support_rates), + qca8084_ahb_clk_pdata, ARRAY_SIZE(qca8084_ahb_clk_pdata)), + CLK_LOOKUP(0x16c, 0, 0x174, CBCR_CLK_RESET, + QCA8084_SEC_CTRL_AHB_CLK, + qca8084_ahb_clk_support_rates, ARRAY_SIZE(qca8084_ahb_clk_support_rates), + qca8084_ahb_clk_pdata, ARRAY_SIZE(qca8084_ahb_clk_pdata)), + CLK_LOOKUP(0x16c, 0, 0x178, CBCR_CLK_RESET, + QCA8084_TLMM_CLK, + qca8084_ahb_clk_support_rates, ARRAY_SIZE(qca8084_ahb_clk_support_rates), + qca8084_ahb_clk_pdata, ARRAY_SIZE(qca8084_ahb_clk_pdata)), + CLK_LOOKUP(0x16c, 0, 0x190, CBCR_CLK_RESET, + QCA8084_TLMM_AHB_CLK, + qca8084_ahb_clk_support_rates, ARRAY_SIZE(qca8084_ahb_clk_support_rates), + qca8084_ahb_clk_pdata, ARRAY_SIZE(qca8084_ahb_clk_pdata)), + CLK_LOOKUP(0x16c, 0, 0x194, CBCR_CLK_RESET, + QCA8084_CNOC_AHB_CLK, + qca8084_ahb_clk_support_rates, ARRAY_SIZE(qca8084_ahb_clk_support_rates), + qca8084_ahb_clk_pdata, ARRAY_SIZE(qca8084_ahb_clk_pdata)), + CLK_LOOKUP(0x16c, 0, 0x198, CBCR_CLK_RESET, + QCA8084_MDIO_AHB_CLK, + qca8084_ahb_clk_support_rates, ARRAY_SIZE(qca8084_ahb_clk_support_rates), + qca8084_ahb_clk_pdata, ARRAY_SIZE(qca8084_ahb_clk_pdata)), + CLK_LOOKUP(0x16c, 0, 0x19c, CBCR_CLK_RESET, + QCA8084_MDIO_MASTER_AHB_CLK, + qca8084_ahb_clk_support_rates, ARRAY_SIZE(qca8084_ahb_clk_support_rates), + qca8084_ahb_clk_pdata, ARRAY_SIZE(qca8084_ahb_clk_pdata)), + /* SYS clock */ + CLK_LOOKUP(0x1a4, 0, 0x1a8, CBCR_CLK_RESET, + QCA8084_SRDS0_SYS_CLK, + qca8084_sys_clk_support_rates, ARRAY_SIZE(qca8084_sys_clk_support_rates), + qca8084_sys_clk_pdata, ARRAY_SIZE(qca8084_sys_clk_pdata)), + CLK_LOOKUP(0x1a4, 0, 0x1ac, CBCR_CLK_RESET, + QCA8084_SRDS1_SYS_CLK, + qca8084_sys_clk_support_rates, ARRAY_SIZE(qca8084_sys_clk_support_rates), + qca8084_sys_clk_pdata, ARRAY_SIZE(qca8084_sys_clk_pdata)), + CLK_LOOKUP(0x1a4, 0, 0x1b0, CBCR_CLK_RESET, + QCA8084_GEPHY0_SYS_CLK, + qca8084_sys_clk_support_rates, ARRAY_SIZE(qca8084_sys_clk_support_rates), + qca8084_sys_clk_pdata, ARRAY_SIZE(qca8084_sys_clk_pdata)), + CLK_LOOKUP(0x1a4, 0, 0x1b4, CBCR_CLK_RESET, + QCA8084_GEPHY1_SYS_CLK, + qca8084_sys_clk_support_rates, ARRAY_SIZE(qca8084_sys_clk_support_rates), + qca8084_sys_clk_pdata, ARRAY_SIZE(qca8084_sys_clk_pdata)), + CLK_LOOKUP(0x1a4, 0, 0x1b8, CBCR_CLK_RESET, + QCA8084_GEPHY2_SYS_CLK, + qca8084_sys_clk_support_rates, ARRAY_SIZE(qca8084_sys_clk_support_rates), + qca8084_sys_clk_pdata, ARRAY_SIZE(qca8084_sys_clk_pdata)), + CLK_LOOKUP(0x1a4, 0, 0x1bc, CBCR_CLK_RESET, + QCA8084_GEPHY3_SYS_CLK, + qca8084_sys_clk_support_rates, ARRAY_SIZE(qca8084_sys_clk_support_rates), + qca8084_sys_clk_pdata, ARRAY_SIZE(qca8084_sys_clk_pdata)), + + /* SEC control clock */ + CLK_LOOKUP(0x1c4, 0, 0x1c8, CBCR_CLK_RESET, + QCA8084_SEC_CTRL_CLK, + qca8084_sys_clk_support_rates, ARRAY_SIZE(qca8084_sys_clk_support_rates), + qca8084_sys_clk_pdata, ARRAY_SIZE(qca8084_sys_clk_pdata)), + CLK_LOOKUP(0x1c4, 0, 0x1d0, CBCR_CLK_RESET, + QCA8084_SEC_CTRL_SENSE_CLK, + qca8084_sys_clk_support_rates, ARRAY_SIZE(qca8084_sys_clk_support_rates), + qca8084_sys_clk_pdata, ARRAY_SIZE(qca8084_sys_clk_pdata)), + + /* GEPHY reset */ + CLK_LOOKUP(0, 0, 0x304, BIT(0), QCA8084_GEPHY_P0_MDC_SW_RST, NULL, 0, NULL, 0), + CLK_LOOKUP(0, 0, 0x304, BIT(1), QCA8084_GEPHY_P1_MDC_SW_RST, NULL, 0, NULL, 0), + CLK_LOOKUP(0, 0, 0x304, BIT(2), QCA8084_GEPHY_P2_MDC_SW_RST, NULL, 0, NULL, 0), + CLK_LOOKUP(0, 0, 0x304, BIT(3), QCA8084_GEPHY_P3_MDC_SW_RST, NULL, 0, NULL, 0), + CLK_LOOKUP(0, 0, 0x304, BIT(4), QCA8084_GEPHY_DSP_HW_RST, NULL, 0, NULL, 0), + + /* Global reset */ + CLK_LOOKUP(0, 0, 0x308, BIT(0), QCA8084_GLOBAL_RST, NULL, 0, NULL, 0), + + /* XPCS reset */ + CLK_LOOKUP(0, 0, 0x30c, BIT(0), QCA8084_UNIPHY_XPCS_RST, NULL, 0, NULL, 0), +}; + +static struct clk_lookup *qca8084_clk_find(const char *clock_id) +{ + int i; + struct clk_lookup *clk; + + for (i = 0; i < ARRAY_SIZE(qca8084_clk_lookup_table); i++) { + clk = &qca8084_clk_lookup_table[i]; + if (!strncmp(clock_id, clk->clk_name, strlen(clock_id))) + return clk; + } + + return NULL; +} + +static void qca8084_clk_update(uint32_t cmd_reg) +{ + uint32_t i, reg_val; + + /* update RCG to the new programmed configuration */ + reg_val = ipq_mii_read(cmd_reg); + reg_val |= RCGR_CMD_UPDATE; + ipq_mii_write(cmd_reg, reg_val); + + for (i = 1000; i > 0; i--) { + reg_val = ipq_mii_read(cmd_reg); + if (!(reg_val & RCGR_CMD_UPDATE)) + return; + + udelay(1); + } + + pr_debug("CLK cmd reg 0x%x fails updating to new configurations\n", cmd_reg); + return; +} + +void qca8084_clk_assert(const char *clock_id) +{ + struct clk_lookup *clk; + uint32_t cbc_reg = 0; + + clk = qca8084_clk_find(clock_id); + if (!clk) { + pr_debug("CLK %s is not found!\n", clock_id); + return; + } + + cbc_reg = QCA8084_CLK_BASE_REG + clk->cbc; + + ipq_mii_update(cbc_reg, clk->rst_bit, clk->rst_bit); + return; +} + +void qca8084_clk_deassert(const char *clock_id) +{ + struct clk_lookup *clk; + uint32_t cbc_reg = 0; + + clk = qca8084_clk_find(clock_id); + if (!clk) { + pr_debug("CLK %s is not found!\n", clock_id); + return; + } + + cbc_reg = QCA8084_CLK_BASE_REG + clk->cbc; + + ipq_mii_update(cbc_reg, clk->rst_bit, 0); + return; +} + +void qca8084_clk_reset(const char *clock_id) +{ + qca8084_clk_assert(clock_id); + + /* Time required by HW to complete assert */ + udelay(10); + + qca8084_clk_deassert(clock_id); + + return; +} + +uint8_t qca8084_clk_is_enabled(const char *clock_id) +{ + struct clk_lookup *clk; + uint32_t reg_val = 0; + + clk = qca8084_clk_find(clock_id); + if (!clk) { + pr_debug("CLK %s is not found!\n", clock_id); + return 0; + } + + reg_val = ipq_mii_read(QCA8084_CLK_BASE_REG + clk->rcg - 4); + return (reg_val & RCGR_CMD_ROOT_OFF) == 0; +} + +void qca8084_clk_enable(const char *clock_id) +{ + struct clk_lookup *clk; + uint32_t cbc_reg = 0, reg_val = 0; + + clk = qca8084_clk_find(clock_id); + if (!clk) { + pr_debug("CLK %s is not found!\n", clock_id); + return; + } + + cbc_reg = QCA8084_CLK_BASE_REG + clk->cbc; + ipq_mii_update(cbc_reg, CBCR_CLK_ENABLE, CBCR_CLK_ENABLE); + + udelay(1); + reg_val = ipq_mii_read(cbc_reg); + if (reg_val & CBCR_CLK_OFF) { + pr_debug("CLK %s is not enabled!\n", clock_id); + return; + } + + return; +} + +void qca8084_clk_disable(const char *clock_id) +{ + struct clk_lookup *clk; + uint32_t cbc_reg = 0; + + clk = qca8084_clk_find(clock_id); + if (!clk) { + pr_debug("CLK %s is not found!\n", clock_id); + return; + } + + cbc_reg = QCA8084_CLK_BASE_REG + clk->cbc; + + ipq_mii_update(cbc_reg, CBCR_CLK_ENABLE, 0); + return; +} + +void qca8084_clk_parent_set(const char *clock_id, qca8084_clk_parent_t parent) +{ + struct clk_lookup *clk; + uint32_t i, reg_val; + uint32_t rcg_reg = 0, cmd_reg = 0, cfg = 0, cur_cfg = 0; + const struct qca8084_parent_data *pdata = NULL; + + clk = qca8084_clk_find(clock_id); + if (!clk) { + pr_debug("CLK %s is not found!\n", clock_id); + return; + } + + for (i = 0; i < clk->num_parent; i++) { + pdata = &(clk->pdata[i]); + if (pdata->parent == parent) + break; + } + + if (i == clk->num_parent) { + pr_debug("CLK %s is configured as incorrect parent %d\n", clock_id, parent); + return; + } + + rcg_reg = QCA8084_CLK_BASE_REG + clk->rcg; + cmd_reg = QCA8084_CLK_BASE_REG + clk->rcg - 4; + + reg_val = ipq_mii_read(rcg_reg); + cur_cfg = (reg_val & RCGR_SRC_SEL) >> RCGR_SRC_SEL_SHIFT; + cfg = pdata->cfg; + + if (cfg == cur_cfg) { + pr_debug("CLK %s parent %d is already configured correctly\n", clock_id, parent); + return; + } + + /* update clock parent */ + reg_val &= ~RCGR_SRC_SEL; + reg_val |= cfg << RCGR_SRC_SEL_SHIFT; + ipq_mii_write(rcg_reg, reg_val); + + /* update RCG to the new programmed configuration */ + qca8084_clk_update(cmd_reg); +} + +void qca8084_uniphy_raw_clock_set(qca8084_clk_parent_t uniphy_clk, uint64_t rate) +{ + switch (uniphy_clk) { + case QCA8084_P_UNIPHY0_RX: + case QCA8084_P_UNIPHY0_TX: + case QCA8084_P_UNIPHY1_RX: + case QCA8084_P_UNIPHY1_TX: + break; + default: + pr_debug("Invalid uniphy_clk %d\n", uniphy_clk); + return; + } + + qca8084_uniphy_raw_clock[uniphy_clk - QCA8084_P_UNIPHY0_RX] = rate; + return; +} + +uint64_t qca8084_uniphy_raw_clock_get(qca8084_clk_parent_t uniphy_clk) +{ + switch (uniphy_clk) { + case QCA8084_P_UNIPHY0_RX: + case QCA8084_P_UNIPHY0_TX: + case QCA8084_P_UNIPHY1_RX: + case QCA8084_P_UNIPHY1_TX: + break; + default: + pr_debug("Invalid uniphy_clk %d\n", uniphy_clk); + return QCA8084_XO_CLK_RATE_50M; + } + + return qca8084_uniphy_raw_clock[uniphy_clk - QCA8084_P_UNIPHY0_RX]; +} + +void qca8084_clk_rate_set(const char *clock_id, uint32_t rate) +{ + struct clk_lookup *clk; + uint64_t div, prate = 0; + uint32_t i, reg_val, parent_index = 0; + uint32_t rcg_reg = 0, cmd_reg = 0, cdiv_reg = 0, cdiv_val = 0; + const struct qca8084_parent_data *pdata = NULL; + + clk = qca8084_clk_find(clock_id); + if (!clk) { + pr_debug("CLK %s is not found!\n", clock_id); + return; + } + + for (i = 0; i < clk->num_rate; i++) + if (rate == clk->support_rate[i]) + break; + + if (i == clk->num_rate) { + pr_debug("CLK %s does not support to configure rate %d\n", clock_id, rate); + return; + } + + rcg_reg = QCA8084_CLK_BASE_REG + clk->rcg; + cmd_reg = QCA8084_CLK_BASE_REG + clk->rcg - 4; + if (clk->cdiv != 0) + cdiv_reg = QCA8084_CLK_BASE_REG + clk->cdiv; + + reg_val = ipq_mii_read(rcg_reg); + + /* get the parent rate of clock */ + parent_index = (reg_val & RCGR_SRC_SEL) >> RCGR_SRC_SEL_SHIFT; + for (i = 0; i < clk->num_parent; i++) { + pdata = &(clk->pdata[i]); + if (pdata->cfg == parent_index) { + /* uniphy0 rx, tx and unphy1 rx, tx clock can be 125M or 312.5M, which + * depends on the current link speed, the clock rate needs to be acquired + * dynamically. + */ + switch (pdata->parent) { + case QCA8084_P_UNIPHY0_RX: + case QCA8084_P_UNIPHY0_TX: + case QCA8084_P_UNIPHY1_RX: + case QCA8084_P_UNIPHY1_TX: + prate = qca8084_uniphy_raw_clock_get(pdata->parent); + break; + default: + /* XO 50M or 315P5M fix clock rate */ + prate = pdata->prate; + break; + } + /* find the parent clock rate */ + break; + } + } + + if (i == clk->num_parent || prate == 0) { + pr_debug("CLK %s is configured as unsupported parent value %d\n", + clock_id, parent_index); + return; + } + + /* when configuring XPSC clock to UQXGMII_XPCS_SPEED_2500M_CLK, the RCGR divider + * need to be bypassed, since there are two dividers from the same RCGR, one is + * for XPCS clock, the other is for EPHY port clock. + */ + if (rate == UQXGMII_XPCS_SPEED_2500M_CLK) { + if (prate != UQXGMII_SPEED_2500M_CLK) { + pr_debug("CLK %s parent(%lld) needs to be updated to %d\n", + clock_id, prate, UQXGMII_SPEED_2500M_CLK); + return; + } + div = RCGR_DIV_BYPASS; + cdiv_val = (UQXGMII_SPEED_2500M_CLK / UQXGMII_XPCS_SPEED_2500M_CLK) - 1; + } else { + + /* calculate the RCGR divider prate/rate = (rcg_divider + 1)/2 */ + div = prate * 2; + do_div(div, rate); + div--; + + /* if the RCG divider can't meet the requirement, the CDIV reg can be simply + * divided by 10 to satisfy the required clock rate. + */ + if (div > RCGR_DIV_MAX) { + /* update CDIV Reg to be divided by 10(N+1) */ + cdiv_val = CDIVR_DIVIDER_10; + + /* caculate the new RCG divider */ + do_div(prate, CDIVR_DIVIDER_10 + 1); + div = prate * 2; + do_div(div, rate); + div--; + } + } + + /* update CDIV Reg to be divided by N(N-1 for reg value) */ + if (cdiv_reg != 0) + ipq_mii_update(cdiv_reg, + CDIVR_DIVIDER, cdiv_val << CDIVR_DIVIDER_SHIFT); + + if (cdiv_reg == 0 && cdiv_val > 0) { + pr_debug("CLK %s needs CDIVR to generate rate %d from prate %lld\n", + clock_id, rate, prate); + return; + } + + /* update RCGR */ + reg_val &= ~RCGR_HDIV; + reg_val |= div << RCGR_HDIV_SHIFT; + ipq_mii_write(rcg_reg, reg_val); + + /* update RCG to the new programmed configuration */ + qca8084_clk_update(cmd_reg); +} + +#ifdef CONFIG_QCA8084_DEBUG +void qca8084_port5_uniphy0_clk_src_get(uint8_t *bypass_en) +{ + uint32_t reg_val = 0; + + /* In switch mode, uniphy0 rx clock is from mac5 rx, uniphy0 tx clock is from mac5 tx; + * In bypass mode, uniphy0 rx clock is from mac4 tx, uniphy0 tx clock is from mac4 rx; + */ + reg_val = ipq_mii_read(QCA8084_CLK_BASE_REG + QCA8084_CLK_MUX_SEL); + *bypass_en = (reg_val & QCA8084_UNIPHY0_SEL_MAC5) ? 0 : 1; + + return; +} + +int qca8084_clk_rate_get(const char *clock_id, + struct qca8084_clk_data *clk_data) +{ + struct clk_lookup *clk; + uint64_t div, prate = 0; + uint32_t i, reg_val, parent_index = 0; + const struct qca8084_parent_data *pdata = NULL; + char clk_id[64] = {0}; + uint8_t bypass_en = 0; + + strlcpy(clk_id, clock_id, sizeof(clk_id)); + + qca8084_port5_uniphy0_clk_src_get(&bypass_en); + if (bypass_en == 1) { + if (strncasecmp(clock_id, QCA8084_MAC5_TX_UNIPHY0_CLK, + strlen(QCA8084_MAC5_TX_UNIPHY0_CLK)) == 0) + strlcpy(clk_id, QCA8084_MAC4_RX_CLK, sizeof(clk_id)); + else if (strncasecmp(clock_id, QCA8084_MAC5_RX_UNIPHY0_CLK, + strlen(QCA8084_MAC5_RX_UNIPHY0_CLK)) == 0) + strlcpy(clk_id, QCA8084_MAC4_TX_CLK, sizeof(clk_id)); + } + + clk = qca8084_clk_find(clk_id); + if (!clk) { + pr_debug("CLK %s is not found!\n", clk_id); + return -1; + } + + reg_val = ipq_mii_read(QCA8084_CLK_BASE_REG + clk->rcg); + + /* get the parent rate of clock */ + parent_index = (reg_val & RCGR_SRC_SEL) >> RCGR_SRC_SEL_SHIFT; + for (i = 0; i < clk->num_parent; i++) { + pdata = &(clk->pdata[i]); + if (pdata->cfg == parent_index) { + /* uniphy0 rx, tx and unphy1 rx, tx clock can be 125M or 312.5M, which + * depends on the current link speed, the clock rate needs to be acquired + * dynamically. + */ + switch (pdata->parent) { + case QCA8084_P_UNIPHY0_RX: + case QCA8084_P_UNIPHY0_TX: + case QCA8084_P_UNIPHY1_RX: + case QCA8084_P_UNIPHY1_TX: + prate = qca8084_uniphy_raw_clock_get(pdata->parent); + break; + default: + /* XO 50M or 315P5M fix clock rate */ + prate = pdata->prate; + break; + } + /* find the parent clock rate */ + break; + } + } + + if (i == clk->num_parent || prate == 0) { + pr_debug("CLK %s is configured as unsupported parent value %d\n", + clk_id, parent_index); + return -1; + } + + /* calculate the current clock rate */ + div = (reg_val >> RCGR_HDIV_SHIFT) & RCGR_HDIV; + if (div != 0) { + /* RCG divider is bypassed if the div value is 0 */ + prate *= 2; + do_div(prate, div + 1); + } + + clk_data->rcg_val = reg_val; + + reg_val = ipq_mii_read(QCA8084_CLK_BASE_REG + clk->cbc); + clk_data->cbc_val = reg_val; + + if (clk->cdiv != 0) { + reg_val = ipq_mii_read(QCA8084_CLK_BASE_REG + clk->cdiv); + clk_data->cdiv_val = reg_val; + do_div(prate, ((reg_val >> CDIVR_DIVIDER_SHIFT) & CDIVR_DIVIDER) + 1); + } + + clk_data->rate = prate; + + return 0; +} + +void qca8084_clk_dump(void) +{ + uint32_t i; + struct clk_lookup *clk; + struct qca8084_clk_data clk_data; + int ret; + + printf("%-31s Frequency RCG_VAL CDIV_VAL CBC_VAL\n", "Clock Name"); + + for (i = 0; i < ARRAY_SIZE(qca8084_clk_lookup_table); i++) { + clk = &qca8084_clk_lookup_table[i]; + if (clk->rcg != 0) { + ret = qca8084_clk_rate_get(clk->clk_name, &clk_data); + if (ret != 0) + continue; + printf("%-31s %-9ld 0x%-5x 0x%-6x 0x%-5x\n", + clk->clk_name, clk_data.rate, + clk_data.rcg_val, clk_data.cdiv_val, clk_data.cbc_val); + } + } +} + +static int do_qca8084_clk_dump(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + qca8084_clk_dump(); + + return 0; +} + +U_BOOT_CMD( + qca8084_clk_dump, 1, 1, do_qca8084_clk_dump, + "QCA8084 utility command to dump clocks\n", + "qca8084_clk_dump - dump all the qca8084 clocks\n" + "This command can be used to check if clocks are all as expected\n" +); +#endif /* CONFIG_QCA8084_DEBUG */ + +void qca8084_port5_uniphy0_clk_src_set(uint8_t bypass_en) +{ + uint32_t mux_sel = 0; + + /* In switch mode, uniphy0 rx clock is from mac5 rx, uniphy0 tx clock is from mac5 tx; + * In bypass mode, uniphy0 rx clock is from mac4 tx, uniphy0 tx clock is from mac4 rx; + */ + + if (bypass_en) + mux_sel = QCA8084_UNIPHY0_SEL_MAC4; + else + mux_sel = QCA8084_UNIPHY0_SEL_MAC5; + + ipq_mii_update(QCA8084_CLK_BASE_REG + QCA8084_CLK_MUX_SEL, + QCA8084_UNIPHY0_MUX_SEL_MASK, mux_sel); + return; +} + +void qca8084_port_clk_rate_set(uint32_t qca8084_port_id, uint32_t rate) +{ + char *mac_rx_clk = NULL, *mac_tx_clk = NULL; + char *xgmii_tx_clk = NULL, *xgmii_rx_clk = NULL; + + switch (qca8084_port_id) { + case PORT0: + mac_rx_clk = QCA8084_MAC0_RX_CLK; + mac_tx_clk = QCA8084_MAC0_TX_CLK; + break; + case PORT1: + mac_rx_clk = QCA8084_MAC1_RX_CLK; + mac_tx_clk = QCA8084_MAC1_TX_CLK; + xgmii_rx_clk = QCA8084_MAC1_UNIPHY1_CH0_XGMII_RX_CLK; + xgmii_tx_clk = QCA8084_MAC1_UNIPHY1_CH0_XGMII_TX_CLK; + break; + case PORT2: + mac_rx_clk = QCA8084_MAC2_RX_CLK; + mac_tx_clk = QCA8084_MAC2_TX_CLK; + xgmii_rx_clk = QCA8084_MAC2_UNIPHY1_CH1_XGMII_RX_CLK; + xgmii_tx_clk = QCA8084_MAC2_UNIPHY1_CH1_XGMII_TX_CLK; + break; + case PORT3: + mac_rx_clk = QCA8084_MAC3_RX_CLK; + mac_tx_clk = QCA8084_MAC3_TX_CLK; + xgmii_rx_clk = QCA8084_MAC3_UNIPHY1_CH2_XGMII_RX_CLK; + xgmii_tx_clk = QCA8084_MAC3_UNIPHY1_CH2_XGMII_TX_CLK; + break; + case PORT4: + mac_rx_clk = QCA8084_MAC4_RX_CLK; + mac_tx_clk = QCA8084_MAC4_TX_CLK; + xgmii_rx_clk = QCA8084_MAC4_UNIPHY1_CH3_XGMII_RX_CLK; + xgmii_tx_clk = QCA8084_MAC4_UNIPHY1_CH3_XGMII_TX_CLK; + break; + case PORT5: + mac_rx_clk = QCA8084_MAC5_RX_CLK; + mac_tx_clk = QCA8084_MAC5_TX_CLK; + break; + default: + pr_debug("Unsupported qca8084_port_id %d\n", qca8084_port_id); + return; + } + + qca8084_clk_rate_set(mac_rx_clk, rate); + qca8084_clk_rate_set(mac_tx_clk, rate); + + if (xgmii_rx_clk != NULL && xgmii_tx_clk != NULL) { + /* XGMII take the different clock rate from MAC clock when the link + * speed is 2.5G. + */ + if (rate == UQXGMII_SPEED_2500M_CLK) + rate = UQXGMII_XPCS_SPEED_2500M_CLK; + qca8084_clk_rate_set(xgmii_rx_clk, rate); + qca8084_clk_rate_set(xgmii_tx_clk, rate); + } + + return; +} + +static void qca8084_clk_ids_get(uint32_t qca8084_port_id, + uint8_t mask, char **clk_ids) +{ + switch (qca8084_port_id) { + case PORT0: + if (mask & QCA8084_CLK_TYPE_MAC) { + *clk_ids++ = QCA8084_MAC0_TX_CLK; + *clk_ids++ = QCA8084_MAC0_RX_CLK; + } + + if (mask & QCA8084_CLK_TYPE_UNIPHY) { + *clk_ids++ = QCA8084_MAC0_TX_UNIPHY1_CLK; + *clk_ids++ = QCA8084_MAC0_RX_UNIPHY1_CLK; + } + break; + case PORT1: + if (mask & QCA8084_CLK_TYPE_MAC) { + *clk_ids++ = QCA8084_MAC1_TX_CLK; + *clk_ids++ = QCA8084_MAC1_RX_CLK; + } + + if (mask & QCA8084_CLK_TYPE_UNIPHY) { + *clk_ids++ = QCA8084_MAC1_UNIPHY1_CH0_RX_CLK; + *clk_ids++ = QCA8084_MAC1_UNIPHY1_CH0_TX_CLK; + *clk_ids++ = QCA8084_MAC1_UNIPHY1_CH0_XGMII_RX_CLK; + *clk_ids++ = QCA8084_MAC1_UNIPHY1_CH0_XGMII_TX_CLK; + } + + if (mask & QCA8084_CLK_TYPE_EPHY) { + *clk_ids++ = QCA8084_MAC1_GEPHY0_TX_CLK; + *clk_ids++ = QCA8084_MAC1_GEPHY0_RX_CLK; + } + break; + case PORT2: + if (mask & QCA8084_CLK_TYPE_MAC) { + *clk_ids++ = QCA8084_MAC2_TX_CLK; + *clk_ids++ = QCA8084_MAC2_RX_CLK; + } + + if (mask & QCA8084_CLK_TYPE_UNIPHY) { + *clk_ids++ = QCA8084_MAC2_UNIPHY1_CH1_RX_CLK; + *clk_ids++ = QCA8084_MAC2_UNIPHY1_CH1_TX_CLK; + *clk_ids++ = QCA8084_MAC2_UNIPHY1_CH1_XGMII_RX_CLK; + *clk_ids++ = QCA8084_MAC2_UNIPHY1_CH1_XGMII_TX_CLK; + } + + if (mask & QCA8084_CLK_TYPE_EPHY) { + *clk_ids++ = QCA8084_MAC2_GEPHY1_TX_CLK; + *clk_ids++ = QCA8084_MAC2_GEPHY1_RX_CLK; + } + break; + case PORT3: + if (mask & QCA8084_CLK_TYPE_MAC) { + *clk_ids++ = QCA8084_MAC3_TX_CLK; + *clk_ids++ = QCA8084_MAC3_RX_CLK; + } + + if (mask & QCA8084_CLK_TYPE_UNIPHY) { + *clk_ids++ = QCA8084_MAC3_UNIPHY1_CH2_RX_CLK; + *clk_ids++ = QCA8084_MAC3_UNIPHY1_CH2_TX_CLK; + *clk_ids++ = QCA8084_MAC3_UNIPHY1_CH2_XGMII_RX_CLK; + *clk_ids++ = QCA8084_MAC3_UNIPHY1_CH2_XGMII_TX_CLK; + } + + if (mask & QCA8084_CLK_TYPE_EPHY) { + *clk_ids++ = QCA8084_MAC3_GEPHY2_TX_CLK; + *clk_ids++ = QCA8084_MAC3_GEPHY2_RX_CLK; + } + break; + case PORT4: + if (mask & QCA8084_CLK_TYPE_MAC) { + *clk_ids++ = QCA8084_MAC4_TX_CLK; + *clk_ids++ = QCA8084_MAC4_RX_CLK; + } + + if (mask & QCA8084_CLK_TYPE_UNIPHY) { + *clk_ids++ = QCA8084_MAC4_UNIPHY1_CH3_RX_CLK; + *clk_ids++ = QCA8084_MAC4_UNIPHY1_CH3_TX_CLK; + *clk_ids++ = QCA8084_MAC4_UNIPHY1_CH3_XGMII_RX_CLK; + *clk_ids++ = QCA8084_MAC4_UNIPHY1_CH3_XGMII_TX_CLK; + } + + if (mask & QCA8084_CLK_TYPE_EPHY) { + *clk_ids++ = QCA8084_MAC4_GEPHY3_TX_CLK; + *clk_ids++ = QCA8084_MAC4_GEPHY3_RX_CLK; + } + break; + case PORT5: + if (mask & QCA8084_CLK_TYPE_MAC) { + *clk_ids++ = QCA8084_MAC5_TX_CLK; + *clk_ids++ = QCA8084_MAC5_RX_CLK; + } + + if (mask & QCA8084_CLK_TYPE_UNIPHY) { + *clk_ids++ = QCA8084_MAC5_TX_UNIPHY0_CLK; + *clk_ids++ = QCA8084_MAC5_RX_UNIPHY0_CLK; + } + break; + default: + pr_debug("Unsupported qca8084_port_id %d\n", qca8084_port_id); + return; + } + + return; +} + +void qca8084_port_clk_reset(uint32_t qca8084_port_id, uint8_t mask) +{ + char *clk_ids[QCA8084_PORT_CLK_CBC_MAX + 1] = {NULL}; + uint32_t i = 0; + + qca8084_clk_ids_get(qca8084_port_id, mask, clk_ids); + + while(clk_ids[i] != NULL) { + qca8084_clk_reset(clk_ids[i]); + i++; + } + + return; +} + +void qca8084_port_clk_en_set(uint32_t qca8084_port_id, uint8_t mask, + uint8_t enable) +{ + char *clk_ids[QCA8084_PORT_CLK_CBC_MAX + 1] = {NULL}; + uint32_t i = 0; + + qca8084_clk_ids_get(qca8084_port_id, mask, clk_ids); + + while(clk_ids[i] != NULL) { + if (enable) + qca8084_clk_enable(clk_ids[i]); + else + qca8084_clk_disable(clk_ids[i]); + i++; + } + + return; +} + +void qca8084_gcc_common_clk_parent_enable(qca8084_work_mode_t clk_mode) +{ + /* Switch core */ + qca8084_clk_parent_set(QCA8084_SWITCH_CORE_CLK, QCA8084_P_UNIPHY1_TX312P5M); + qca8084_clk_rate_set(QCA8084_SWITCH_CORE_CLK, UQXGMII_SPEED_2500M_CLK); + + /* Disable switch core clock to save power in phy mode */ + if (QCA8084_PHY_UQXGMII_MODE == clk_mode || QCA8084_PHY_SGMII_UQXGMII_MODE == clk_mode) + qca8084_clk_disable(QCA8084_SWITCH_CORE_CLK); + else + qca8084_clk_enable(QCA8084_SWITCH_CORE_CLK); + + qca8084_clk_enable(QCA8084_APB_BRIDGE_CLK); + + /* AHB bridge */ + qca8084_clk_parent_set(QCA8084_AHB_CLK, QCA8084_P_UNIPHY1_TX312P5M); + qca8084_clk_rate_set(QCA8084_AHB_CLK, QCA8084_AHB_CLK_RATE_104P17M); + qca8084_clk_enable(QCA8084_AHB_CLK); + qca8084_clk_enable(QCA8084_SEC_CTRL_AHB_CLK); + qca8084_clk_enable(QCA8084_TLMM_CLK); + qca8084_clk_enable(QCA8084_TLMM_AHB_CLK); + qca8084_clk_enable(QCA8084_CNOC_AHB_CLK); + qca8084_clk_enable(QCA8084_MDIO_AHB_CLK); + qca8084_clk_enable(QCA8084_MDIO_MASTER_AHB_CLK); + + /* System */ + qca8084_clk_parent_set(QCA8084_SRDS0_SYS_CLK, QCA8084_P_XO); + qca8084_clk_rate_set(QCA8084_SRDS0_SYS_CLK, QCA8084_SYS_CLK_RATE_25M); + + /* Disable serdes0 clock to save power in phy mode */ + if (QCA8084_PHY_UQXGMII_MODE == clk_mode || QCA8084_PHY_SGMII_UQXGMII_MODE == clk_mode) + qca8084_clk_disable(QCA8084_SRDS0_SYS_CLK); + else + qca8084_clk_enable(QCA8084_SRDS0_SYS_CLK); + + qca8084_clk_enable(QCA8084_SRDS1_SYS_CLK); + qca8084_clk_enable(QCA8084_GEPHY0_SYS_CLK); + qca8084_clk_enable(QCA8084_GEPHY1_SYS_CLK); + qca8084_clk_enable(QCA8084_GEPHY2_SYS_CLK); + qca8084_clk_enable(QCA8084_GEPHY3_SYS_CLK); + + /* Sec control */ + qca8084_clk_parent_set(QCA8084_SEC_CTRL_CLK, QCA8084_P_XO); + qca8084_clk_rate_set(QCA8084_SEC_CTRL_CLK, QCA8084_SYS_CLK_RATE_25M); + qca8084_clk_enable(QCA8084_SEC_CTRL_CLK); + qca8084_clk_enable(QCA8084_SEC_CTRL_SENSE_CLK); +} + +void qca8084_gcc_port_clk_parent_set(qca8084_work_mode_t clk_mode, uint32_t qca8084_port_id) +{ + qca8084_clk_parent_t port_tx_parent, port_rx_parent; + char *tx_clk_id, *rx_clk_id; + + /* Initialize the clock parent with port 1, 2, 3, clock parent is same for these ports; + * the clock parent will be updated for port 0, 4, 5. + */ + switch(clk_mode) { + case QCA8084_SWITCH_MODE: + case QCA8084_SWITCH_BYPASS_PORT5_MODE: + port_tx_parent = QCA8084_P_UNIPHY1_TX312P5M; + break; + case QCA8084_PHY_UQXGMII_MODE: + case QCA8084_PHY_SGMII_UQXGMII_MODE: + port_tx_parent = QCA8084_P_UNIPHY1_RX312P5M; + break; + default: + pr_debug("Unsupported clock mode %d\n", clk_mode); + return; + } + port_rx_parent = QCA8084_P_UNIPHY1_TX312P5M; + + switch (qca8084_port_id) { + case PORT0: + port_tx_parent = QCA8084_P_UNIPHY1_TX; + port_rx_parent = QCA8084_P_UNIPHY1_RX; + tx_clk_id = QCA8084_MAC0_TX_CLK; + rx_clk_id = QCA8084_MAC0_RX_CLK; + break; + case PORT1: + tx_clk_id = QCA8084_MAC1_TX_CLK; + rx_clk_id = QCA8084_MAC1_RX_CLK; + break; + case PORT2: + tx_clk_id = QCA8084_MAC2_TX_CLK; + rx_clk_id = QCA8084_MAC2_RX_CLK; + break; + case PORT3: + tx_clk_id = QCA8084_MAC3_TX_CLK; + rx_clk_id = QCA8084_MAC3_RX_CLK; + break; + case PORT4: + switch(clk_mode) { + case QCA8084_SWITCH_BYPASS_PORT5_MODE: + case QCA8084_PHY_SGMII_UQXGMII_MODE: + port_tx_parent = QCA8084_P_UNIPHY0_RX; + port_rx_parent = QCA8084_P_UNIPHY0_TX; + break; + case QCA8084_SWITCH_MODE: + port_tx_parent = QCA8084_P_UNIPHY1_TX312P5M; + port_rx_parent = QCA8084_P_UNIPHY1_TX312P5M; + break; + case QCA8084_PHY_UQXGMII_MODE: + port_tx_parent = QCA8084_P_UNIPHY1_RX312P5M; + port_rx_parent = QCA8084_P_UNIPHY1_TX312P5M; + break; + default: + pr_debug("Unsupported clock mode %d\n", clk_mode); + return; + } + tx_clk_id = QCA8084_MAC4_TX_CLK; + rx_clk_id = QCA8084_MAC4_RX_CLK; + break; + case PORT5: + port_tx_parent = QCA8084_P_UNIPHY0_TX; + port_rx_parent = QCA8084_P_UNIPHY0_RX; + tx_clk_id = QCA8084_MAC5_TX_CLK; + rx_clk_id = QCA8084_MAC5_RX_CLK; + switch (clk_mode) { + case QCA8084_SWITCH_BYPASS_PORT5_MODE: + case QCA8084_PHY_SGMII_UQXGMII_MODE: + qca8084_port5_uniphy0_clk_src_set(1); + break; + case QCA8084_SWITCH_MODE: + case QCA8084_PHY_UQXGMII_MODE: + qca8084_port5_uniphy0_clk_src_set(0); + break; + default: + pr_debug("Unsupported clock mode %d\n", clk_mode); + return; + } + break; + default: + pr_debug("Unsupported qca8084_port_id %d\n", qca8084_port_id); + return; + } + + qca8084_clk_parent_set(tx_clk_id, port_tx_parent); + qca8084_clk_parent_set(rx_clk_id, port_rx_parent); +} + +void qca8084_gcc_clock_init(qca8084_work_mode_t clk_mode, u32 pbmp) +{ + uint32_t qca8084_port_id = 0; + /* clock type mask value for 6 manhattan ports */ + uint8_t clk_mask[PORT5 + 1] = {0}; + uint8_t switch_flag = 0; + qca8084_clk_parent_t uniphy_index = QCA8084_P_UNIPHY0_RX; + + switch (clk_mode) { + case QCA8084_SWITCH_MODE: + case QCA8084_SWITCH_BYPASS_PORT5_MODE: + while (pbmp) { + if (pbmp & 1) { + if (qca8084_port_id == PORT0 || + qca8084_port_id == PORT5) { + clk_mask[qca8084_port_id] = QCA8084_CLK_TYPE_MAC | + QCA8084_CLK_TYPE_UNIPHY; + } else { + clk_mask[qca8084_port_id] = QCA8084_CLK_TYPE_MAC | + QCA8084_CLK_TYPE_EPHY; + } + } + pbmp >>= 1; + qca8084_port_id++; + } + + if (clk_mode == QCA8084_SWITCH_BYPASS_PORT5_MODE) { + /* For phy port 4 in switch bypass mode */ + clk_mask[PORT4] = QCA8084_CLK_TYPE_EPHY; + clk_mask[PORT5] = QCA8084_CLK_TYPE_UNIPHY; + } + + switch_flag = 1; + break; + case QCA8084_PHY_UQXGMII_MODE: + case QCA8084_PHY_SGMII_UQXGMII_MODE: + clk_mask[PORT1] = QCA8084_CLK_TYPE_UNIPHY | QCA8084_CLK_TYPE_EPHY; + clk_mask[PORT2] = QCA8084_CLK_TYPE_UNIPHY | QCA8084_CLK_TYPE_EPHY; + clk_mask[PORT3] = QCA8084_CLK_TYPE_UNIPHY | QCA8084_CLK_TYPE_EPHY; + clk_mask[PORT4] = QCA8084_CLK_TYPE_UNIPHY | QCA8084_CLK_TYPE_EPHY; + if (clk_mode == QCA8084_PHY_SGMII_UQXGMII_MODE) { + /* For phy port4 in PHY bypass mode */ + clk_mask[PORT4] = QCA8084_CLK_TYPE_EPHY; + clk_mask[PORT5] = QCA8084_CLK_TYPE_UNIPHY; + } + break; + default: + pr_debug("Unsupported clock mode %d\n", clk_mode); + return; + } + + qca8084_gcc_common_clk_parent_enable(clk_mode); + + /* Initialize the uniphy raw clock, if the port4 is in bypass mode, the uniphy0 + * raw clock need to be dynamically updated between UQXGMII_SPEED_2500M_CLK and + * UQXGMII_SPEED_1000M_CLK according to the realtime link speed. + */ + uniphy_index = QCA8084_P_UNIPHY0_RX; + while (uniphy_index <= QCA8084_P_UNIPHY1_TX) { + /* the uniphy raw clock may be already initialized. */ + if (0 == qca8084_uniphy_raw_clock_get(uniphy_index)) + qca8084_uniphy_raw_clock_set(uniphy_index, + UQXGMII_SPEED_2500M_CLK); + uniphy_index++; + } + + qca8084_port_id = 0; + while (qca8084_port_id < ARRAY_SIZE(clk_mask)) { + if (clk_mask[qca8084_port_id] != 0) { + qca8084_gcc_port_clk_parent_set(clk_mode, qca8084_port_id); + if (clk_mask[qca8084_port_id] & QCA8084_CLK_TYPE_MAC) + qca8084_port_clk_en_set(qca8084_port_id, QCA8084_CLK_TYPE_MAC, 1); + if (clk_mask[qca8084_port_id] & QCA8084_CLK_TYPE_UNIPHY && switch_flag == 1) + qca8084_port_clk_en_set(qca8084_port_id, QCA8084_CLK_TYPE_UNIPHY, 1); + pbmp |= BIT(qca8084_port_id); + } + qca8084_port_id++; + } + + pr_debug("QCA8084 GCC CLK initialization with clock mode %d on port bmp 0x%x\n", + clk_mode, pbmp); +} diff --git a/sources/uboot-be550/drivers/net/ipq_common/ipq_qca8084_clk.h b/sources/uboot-be550/drivers/net/ipq_common/ipq_qca8084_clk.h new file mode 100644 index 00000000..7ae9efea --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq_common/ipq_qca8084_clk.h @@ -0,0 +1,253 @@ +/* + * Copyright (c) 2022, The Linux Foundation. All rights reserved. + + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. +*/ +#ifndef _QCA8084_CLK_H_ +#define _QCA8084_CLK_H_ + +#define QCA8084_SWITCH_CORE_CLK "switch_clk" +#define QCA8084_APB_BRIDGE_CLK "apb_clk" + +#define QCA8084_MAC0_TX_CLK "m0_tx_clk" +#define QCA8084_MAC0_TX_UNIPHY1_CLK "m0_tx_srds1_clk" + +#define QCA8084_MAC0_RX_CLK "m0_rx_clk" +#define QCA8084_MAC0_RX_UNIPHY1_CLK "m0_rx_srds1_clk" + +#define QCA8084_MAC1_TX_CLK "m1_tx_clk" +#define QCA8084_MAC1_GEPHY0_TX_CLK "m1_gp0_tx_clk" +#define QCA8084_MAC1_UNIPHY1_CH0_RX_CLK "m1_srds1_ch0_rx_clk" +#define QCA8084_MAC1_UNIPHY1_CH0_XGMII_RX_CLK "m1_srds1_ch0_xgmii_rx_clk" + +#define QCA8084_MAC1_RX_CLK "m1_rx_clk" +#define QCA8084_MAC1_GEPHY0_RX_CLK "m1_gp0_rx_clk" +#define QCA8084_MAC1_UNIPHY1_CH0_TX_CLK "m1_srds1_ch0_tx_clk" +#define QCA8084_MAC1_UNIPHY1_CH0_XGMII_TX_CLK "m1_srds1_ch0_xgmii_tx_clk" + +#define QCA8084_MAC2_TX_CLK "m2_tx_clk" +#define QCA8084_MAC2_GEPHY1_TX_CLK "m2_gp1_tx_clk" +#define QCA8084_MAC2_UNIPHY1_CH1_RX_CLK "m2_srds1_ch1_rx_clk" +#define QCA8084_MAC2_UNIPHY1_CH1_XGMII_RX_CLK "m2_srds1_ch1_xgmii_rx_clk" + +#define QCA8084_MAC2_RX_CLK "m2_rx_clk" +#define QCA8084_MAC2_GEPHY1_RX_CLK "m2_gp1_rx_clk" +#define QCA8084_MAC2_UNIPHY1_CH1_TX_CLK "m2_srds1_ch1_tx_clk" +#define QCA8084_MAC2_UNIPHY1_CH1_XGMII_TX_CLK "m2_srds1_ch1_xgmii_tx_clk" + +#define QCA8084_MAC3_TX_CLK "m3_tx_clk" +#define QCA8084_MAC3_GEPHY2_TX_CLK "m3_gp2_tx_clk" +#define QCA8084_MAC3_UNIPHY1_CH2_RX_CLK "m3_srds1_ch2_rx_clk" +#define QCA8084_MAC3_UNIPHY1_CH2_XGMII_RX_CLK "m3_srds1_ch2_xgmii_rx_clk" + +#define QCA8084_MAC3_RX_CLK "m3_rx_clk" +#define QCA8084_MAC3_GEPHY2_RX_CLK "m3_gp2_rx_clk" +#define QCA8084_MAC3_UNIPHY1_CH2_TX_CLK "m3_srds1_ch2_tx_clk" +#define QCA8084_MAC3_UNIPHY1_CH2_XGMII_TX_CLK "m3_srds1_ch2_xgmii_tx_clk" + +#define QCA8084_MAC4_TX_CLK "m4_tx_clk" +#define QCA8084_MAC4_GEPHY3_TX_CLK "m4_gp3_tx_clk" +#define QCA8084_MAC4_UNIPHY1_CH3_RX_CLK "m4_srds1_ch3_rx_clk" +#define QCA8084_MAC4_UNIPHY1_CH3_XGMII_RX_CLK "m4_srds1_ch3_xgmii_rx_clk" + +#define QCA8084_MAC4_RX_CLK "m4_rx_clk" +#define QCA8084_MAC4_GEPHY3_RX_CLK "m4_gp3_rx_clk" +#define QCA8084_MAC4_UNIPHY1_CH3_TX_CLK "m4_srds1_ch3_tx_clk" +#define QCA8084_MAC4_UNIPHY1_CH3_XGMII_TX_CLK "m4_srds1_ch3_xgmii_tx_clk" + +#define QCA8084_MAC5_TX_CLK "m5_tx_clk" +#define QCA8084_MAC5_TX_UNIPHY0_CLK "m5_tx_srds0_clk" +#define QCA8084_MAC5_TX_SRDS0_CLK_SRC "m5_tx_srds0_clk_src" + +#define QCA8084_MAC5_RX_CLK "m5_rx_clk" +#define QCA8084_MAC5_RX_UNIPHY0_CLK "m5_rx_srds0_clk" +#define QCA8084_MAC5_RX_SRDS0_CLK_SRC "m5_rx_srds0_clk_src" + +#define QCA8084_SEC_CTRL_CLK "sec_ctrl_clk" +#define QCA8084_SEC_CTRL_SENSE_CLK "sec_ctrl_sense_clk" + +#define QCA8084_SRDS0_SYS_CLK "srds0_sys_clk" +#define QCA8084_SRDS1_SYS_CLK "srds1_sys_clk" +#define QCA8084_GEPHY0_SYS_CLK "gp0_sys_clk" +#define QCA8084_GEPHY1_SYS_CLK "gp1_sys_clk" +#define QCA8084_GEPHY2_SYS_CLK "gp2_sys_clk" +#define QCA8084_GEPHY3_SYS_CLK "gp3_sys_clk" + +#define QCA8084_AHB_CLK "ahb_clk" +#define QCA8084_SEC_CTRL_AHB_CLK "sec_ctrl_ahb_clk" +#define QCA8084_TLMM_CLK "tlmm_clk" +#define QCA8084_TLMM_AHB_CLK "tlmm_ahb_clk" +#define QCA8084_CNOC_AHB_CLK "cnoc_ahb_clk" +#define QCA8084_MDIO_AHB_CLK "mdio_ahb_clk" +#define QCA8084_MDIO_MASTER_AHB_CLK "mdio_master_ahb_clk" + +#define QCA8084_GLOBAL_RST "global_rst" +#define QCA8084_UNIPHY_XPCS_RST "xpcs_rst" +#define QCA8084_GEPHY_DSP_HW_RST "dsp_hw_rst" +#define QCA8084_GEPHY_P3_MDC_SW_RST "p3_mdc_sw_rst" +#define QCA8084_GEPHY_P2_MDC_SW_RST "p2_mdc_sw_rst" +#define QCA8084_GEPHY_P1_MDC_SW_RST "p1_mdc_sw_rst" +#define QCA8084_GEPHY_P0_MDC_SW_RST "p0_mdc_sw_rst" + + + +typedef enum { + QCA8084_P_XO, + QCA8084_P_UNIPHY0_RX, + QCA8084_P_UNIPHY0_TX, + QCA8084_P_UNIPHY1_RX, + QCA8084_P_UNIPHY1_TX, + QCA8084_P_UNIPHY1_RX312P5M, + QCA8084_P_UNIPHY1_TX312P5M, + QCA8084_P_MAX, +} qca8084_clk_parent_t; + +struct qca8084_clk_data { + unsigned long rate; + unsigned int rcg_val; + unsigned int cdiv_val; + unsigned int cbc_val; +}; + +struct qca8084_parent_data { + unsigned long prate; /* RCG input clock rate */ + qca8084_clk_parent_t parent; /* RCG parent clock id */ + int cfg; /* RCG clock src value */ +}; + +struct clk_lookup { + unsigned int rcg; + unsigned int cdiv; + unsigned int cbc; + unsigned int rst_bit; + const char *clk_name; + const unsigned long *support_rate; + unsigned int num_rate; + const struct qca8084_parent_data *pdata; + unsigned int num_parent; +}; + +#define CLK_LOOKUP(_rcg, _cdiv, _cbc, _rst_bit, _clk_name, \ + _rate, _num_rate, _pdata, _num_parent) \ +{ \ + .rcg = _rcg, \ + .cdiv = _cdiv, \ + .cbc = _cbc, \ + .rst_bit = _rst_bit, \ + .clk_name = _clk_name, \ + .support_rate = _rate, \ + .num_rate = _num_rate, \ + .pdata = _pdata, \ + .num_parent = _num_parent, \ +} + +#define QCA8084_CLK_TYPE_EPHY BIT(0) +#define QCA8084_CLK_TYPE_UNIPHY BIT(1) +#define QCA8084_CLK_TYPE_MAC BIT(2) + +#define UQXGMII_SPEED_2500M_CLK 312500000 +#define UQXGMII_SPEED_1000M_CLK 125000000 +#define UQXGMII_SPEED_100M_CLK 25000000 +#define UQXGMII_SPEED_10M_CLK 2500000 +#define UQXGMII_XPCS_SPEED_2500M_CLK 78125000 +#define QCA8084_AHB_CLK_RATE_104P17M 104160000 +#define QCA8084_SYS_CLK_RATE_25M 25000000 +#define QCA8084_XO_CLK_RATE_50M 50000000 + +#define QCA8084_CLK_BASE_REG 0x0c800000 +#define QCA8084_CLK_MUX_SEL 0x300 +#define QCA8084_UNIPHY0_MUX_SEL_MASK BITS_MASK(0, 2) +#define QCA8084_UNIPHY0_SEL_MAC5 0x3 +#define QCA8084_UNIPHY0_SEL_MAC4 0 + +#define RCGR_CMD_ROOT_OFF BIT(31) +#define RCGR_CMD_UPDATE BIT(0) +#define RCGR_SRC_SEL BITS_MASK(8, 3) +#define RCGR_SRC_SEL_SHIFT 8 +#define RCGR_HDIV BITS_MASK(0, 5) +#define RCGR_HDIV_SHIFT 0 +#define RCGR_DIV_BYPASS 0 +#define RCGR_DIV_MAX 0x1f +#define CDIVR_DIVIDER_10 9 /* CDIVR divided by N + 1 */ +#define CDIVR_DIVIDER BITS_MASK(0, 4) +#define CDIVR_DIVIDER_SHIFT 0 +#define CBCR_CLK_OFF BIT(31) +#define CBCR_CLK_RESET BIT(2) +#define CBCR_CLK_ENABLE BIT(0) + + +/* work mode */ +#define WORK_MODE +#define WORK_MODE_ID 0 +#define WORK_MODE_OFFSET 0xC90F030 +#define WORK_MODE_E_LENGTH 4 +#define WORK_MODE_E_OFFSET 0 +#define WORK_MODE_NR_E 1 + +/* port5 sel */ +#define WORK_MODE_PORT5_SEL +#define WORK_MODE_PORT5_SEL_BOFFSET 5 +#define WORK_MODE_PORT5_SEL_BLEN 1 +#define WORK_MODE_PORT5_SEL_FLAG HSL_RW + +/* phy3 sel1 */ +#define WORK_MODE_PHY3_SEL1 +#define WORK_MODE_PHY3_SEL1_BOFFSET 4 +#define WORK_MODE_PHY3_SEL1_BLEN 1 +#define WORK_MODE_PHY3_SEL1_FLAG HSL_RW + +/* phy3 sel0 */ +#define WORK_MODE_PHY3_SEL0 +#define WORK_MODE_PHY3_SEL0_BOFFSET 3 +#define WORK_MODE_PHY3_SEL0_BLEN 1 +#define WORK_MODE_PHY3_SEL0_FLAG HSL_RW + +/* phy2 sel */ +#define WORK_MODE_PHY2_SEL +#define WORK_MODE_PHY2_SEL_BOFFSET 2 +#define WORK_MODE_PHY2_SEL_BLEN 1 +#define WORK_MODE_PHY2_SEL_FLAG HSL_RW + +/* phy1 sel */ +#define WORK_MODE_PHY1_SEL +#define WORK_MODE_PHY1_SEL_BOFFSET 1 +#define WORK_MODE_PHY1_SEL_BLEN 1 +#define WORK_MODE_PHY1_SEL_FLAG HSL_RW + +/* phy0 sel */ +#define WORK_MODE_PHY0_SEL +#define WORK_MODE_PHY0_SEL_BOFFSET 0 +#define WORK_MODE_PHY0_SEL_BLEN 1 +#define WORK_MODE_PHY0_SEL_FLAG HSL_RW + +#define QCA8084_WORK_MODE_MASK \ + (BITSM(WORK_MODE_PHY0_SEL_BOFFSET, WORK_MODE_PORT5_SEL_BOFFSET + 1)) + +typedef enum { + QCA8084_SWITCH_MODE = + (BIT(WORK_MODE_PHY3_SEL1_BOFFSET)), + QCA8084_SWITCH_BYPASS_PORT5_MODE = + (BIT(WORK_MODE_PORT5_SEL_BOFFSET)), + QCA8084_PHY_UQXGMII_MODE = + (BIT(WORK_MODE_PORT5_SEL_BOFFSET) | + BIT(WORK_MODE_PHY3_SEL0_BOFFSET) | + BIT(WORK_MODE_PHY2_SEL_BOFFSET) | + BIT(WORK_MODE_PHY1_SEL_BOFFSET) | + BIT(WORK_MODE_PHY0_SEL_BOFFSET)), + QCA8084_PHY_SGMII_UQXGMII_MODE = + (BIT(WORK_MODE_PORT5_SEL_BOFFSET) | + BIT(WORK_MODE_PHY2_SEL_BOFFSET) | + BIT(WORK_MODE_PHY1_SEL_BOFFSET) | + BIT(WORK_MODE_PHY0_SEL_BOFFSET)), + QCA8084_WORK_MODE_MAX, +} qca8084_work_mode_t; + + +#endif /* _QCA8084_CLK_H_ */ diff --git a/sources/uboot-be550/drivers/net/ipq_common/ipq_qca8084_interface_ctrl.c b/sources/uboot-be550/drivers/net/ipq_common/ipq_qca8084_interface_ctrl.c new file mode 100644 index 00000000..05af73fa --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq_common/ipq_qca8084_interface_ctrl.c @@ -0,0 +1,706 @@ +/* + * Copyright (c) 2022, The Linux Foundation. All rights reserved. + + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. +*/ +#include "ipq_phy.h" +#include "ipq_qca8084.h" +#include "ipq_qca8084_clk.h" +#include "ipq_qca8084_interface_ctrl.h" +#include + +#ifdef DEBUG +#define pr_debug(fmt, args...) printf(fmt, ##args); +#else +#define pr_debug(fmt, args...) +#endif + +extern void qca8084_phy_reset(u32 phy_id); +extern u16 qca8084_phy_reg_read(u32 phy_id, u32 reg_id); +extern u16 qca8084_phy_reg_write(u32 phy_id, u32 reg_id, u16 value); +extern u16 qca8084_phy_mmd_read(u32 phy_id, u16 mmd_num, u16 reg_id); +extern u16 qca8084_phy_mmd_write(u32 phy_id, u16 mmd_num, u16 reg_id, + u16 value); +extern void qca8084_phy_modify_mmd(uint32_t phy_addr, uint32_t mmd_num, + uint32_t mmd_reg, uint32_t mask, uint32_t value); +extern void qca8084_phy_modify_mii(uint32_t phy_addr, uint32_t mii_reg, + uint32_t mask, uint32_t value); +extern uint32_t ipq_mii_read(uint32_t reg); +extern void ipq_mii_write(uint32_t reg, uint32_t val); +extern void ipq_mii_update(uint32_t reg, uint32_t mask, uint32_t val); +extern void qca8084_port_clk_en_set(uint32_t qca8084_port_id, uint8_t mask, + uint8_t enable); +extern void qca8084_clk_assert(const char *clock_id); +extern void qca8084_port_clk_reset(uint32_t qca8084_port_id, uint8_t mask); +extern void qca8084_port_clk_rate_set(uint32_t qca8084_port_id, uint32_t rate); + +#ifdef CONFIG_QCA8084_PHY_MODE +extern void qca8084_clk_deassert(const char *clock_id); +#endif + +#ifdef CONFIG_QCA8084_SWT_MODE +extern void qca8084_uniphy_raw_clock_set(qca8084_clk_parent_t uniphy_clk, + uint64_t rate); +#endif + +#ifdef CONFIG_QCA8084_BYPASS_MODE +extern void qca8084_phy_sgmii_speed_fixup (u32 phy_addr, u32 link, + fal_port_speed_t new_speed); +#endif + +void qca8084_serdes_addr_get(uint32_t serdes_id, uint32_t *address) +{ + uint32_t data = 0; + + data = ipq_mii_read(SERDES_CFG_OFFSET); + switch(serdes_id) + { + case QCA8084_UNIPHY_SGMII_0: + *address = (data >> SERDES_CFG_S0_ADDR_BOFFSET) & 0x1f; + break; + case QCA8084_UNIPHY_SGMII_1: + *address = (data >> SERDES_CFG_S1_ADDR_BOFFSET) & 0x1f; + break; + case QCA8084_UNIPHY_XPCS: + *address = (data >> SERDES_CFG_S1_XPCS_ADDR_BOFFSET) & 0x1f; + break; + default: + pr_debug("Serdes id not matching\n"); + break; + } +} + +static void qca8084_uniphy_calibration(uint32_t uniphy_addr) +{ + uint16_t uniphy_data = 0; + uint32_t retries = 100, calibration_done = 0; + + /* wait calibration done to uniphy*/ + while (calibration_done != QCA8084_UNIPHY_MMD1_CALIBRATION_DONE) { + mdelay(1); + if (retries-- == 0) + pr_debug("uniphy callibration time out!\n"); + uniphy_data = qca8084_phy_mmd_read(uniphy_addr, QCA8084_UNIPHY_MMD1, + QCA8084_UNIPHY_MMD1_CALIBRATION4); + + calibration_done = (uniphy_data & QCA8084_UNIPHY_MMD1_CALIBRATION_DONE); + } +} + +void qca8084_port_speed_clock_set(uint32_t qca8084_port_id, + fal_port_speed_t speed) +{ + uint32_t clk_rate = 0; + + switch(speed) + { + case FAL_SPEED_2500: + clk_rate = UQXGMII_SPEED_2500M_CLK; + break; + case FAL_SPEED_1000: + clk_rate = UQXGMII_SPEED_1000M_CLK; + break; + case FAL_SPEED_100: + clk_rate = UQXGMII_SPEED_100M_CLK; + break; + case FAL_SPEED_10: + clk_rate = UQXGMII_SPEED_10M_CLK; + break; + default: + pr_debug("Unknown speed\n"); + return; + } + + qca8084_port_clk_rate_set(qca8084_port_id, clk_rate); +} + +void qca8084_ephy_addr_get(uint32_t qca8084_port_id, uint32_t *phy_addr) +{ + uint32_t data = 0; + + data = ipq_mii_read(EPHY_CFG_OFFSET); + switch(qca8084_port_id) + { + case PORT1: + *phy_addr = (data >> EPHY_CFG_EPHY0_ADDR_BOFFSET) & 0x1f; + break; + case PORT2: + *phy_addr = (data >> EPHY_CFG_EPHY1_ADDR_BOFFSET) & 0x1f; + break; + case PORT3: + *phy_addr = (data >> EPHY_CFG_EPHY2_ADDR_BOFFSET) & 0x1f; + break; + case PORT4: + *phy_addr = (data >> EPHY_CFG_EPHY3_ADDR_BOFFSET) & 0x1f; + break; + default: + pr_debug("qca8084_port_id not matching\n"); + break; + } +} + +#ifdef CONFIG_QCA8084_PHY_MODE +static uint16_t qca8084_uniphy_xpcs_mmd_read(uint16_t mmd_num, uint16_t mmd_reg) +{ + uint32_t uniphy_xpcs_addr = 0; + + qca8084_serdes_addr_get(QCA8084_UNIPHY_XPCS, &uniphy_xpcs_addr); + + return qca8084_phy_mmd_read(uniphy_xpcs_addr, mmd_num, mmd_reg); +} + +static void qca8084_uniphy_xpcs_mmd_write(uint16_t mmd_num, uint16_t mmd_reg, + uint16_t reg_val) +{ + uint32_t uniphy_xpcs_addr = 0; +#ifdef DEBUG + uint16_t phy_data = 0; +#endif + + qca8084_serdes_addr_get(QCA8084_UNIPHY_XPCS, &uniphy_xpcs_addr); + + qca8084_phy_mmd_write(uniphy_xpcs_addr, mmd_num, mmd_reg, reg_val); + /*check the mmd register value*/ +#ifdef DEBUG + phy_data = +#endif + qca8084_uniphy_xpcs_mmd_read(mmd_num, mmd_reg); + + pr_debug("phy_addr:0x%x, mmd_num:0x%x, mmd_reg:0x%x, phy_data:0x%x\n", + uniphy_xpcs_addr, mmd_num, mmd_reg, phy_data); +} + +static void qca8084_uniphy_xpcs_modify_mmd(uint32_t mmd_num, uint32_t mmd_reg, + uint32_t mask, uint32_t value) +{ + uint16_t phy_data = 0, new_phy_data = 0; + + phy_data = qca8084_uniphy_xpcs_mmd_read(mmd_num, mmd_reg); + new_phy_data = (phy_data & ~mask) | value; + qca8084_uniphy_xpcs_mmd_write(mmd_num, mmd_reg, new_phy_data); +} + +static uint32_t qca8084_uniphy_xpcs_port_to_mmd(uint32_t qca8084_port_id) +{ + uint32_t mmd_id = 0; + + switch(qca8084_port_id) + { + case PORT1: + mmd_id = QCA8084_UNIPHY_MMD31; + break; + case PORT2: + mmd_id = QCA8084_UNIPHY_MMD26; + break; + case PORT3: + mmd_id = QCA8084_UNIPHY_MMD27; + break; + case PORT4: + mmd_id = QCA8084_UNIPHY_MMD28; + break; + default: + pr_debug("Port not matching qca8084 ports\n"); + } + + return mmd_id; +} + +static void qca8084_uniphy_xpcs_modify_port_mmd(uint32_t qca8084_port_id, + uint32_t mmd_reg, uint32_t mask, + uint32_t value) +{ + uint32_t mmd_id = 0; + + mmd_id = qca8084_uniphy_xpcs_port_to_mmd(qca8084_port_id); + + qca8084_uniphy_xpcs_modify_mmd(mmd_id, mmd_reg, mask, value); +} + +static void qca8084_uniphy_xpcs_8023az_enable(void) +{ + uint16_t uniphy_data = 0; + + uniphy_data = qca8084_uniphy_xpcs_mmd_read(QCA8084_UNIPHY_MMD3, + QCA8084_UNIPHY_MMD3_AN_LP_BASE_ABL2); + if(!(uniphy_data & QCA8084_UNIPHY_MMD3_XPCS_EEE_CAP)) + return; + + /*Configure the EEE related timer*/ + qca8084_uniphy_xpcs_modify_mmd(QCA8084_UNIPHY_MMD3, + QCA8084_UNIPHY_MMD3_EEE_MODE_CTRL, + 0x0f40, QCA8084_UNIPHY_MMD3_EEE_RES_REGS | + QCA8084_UNIPHY_MMD3_EEE_SIGN_BIT_REGS); + + qca8084_uniphy_xpcs_modify_mmd(QCA8084_UNIPHY_MMD3, + QCA8084_UNIPHY_MMD3_EEE_TX_TIMER, + 0x1fff, QCA8084_UNIPHY_MMD3_EEE_TSL_REGS| + QCA8084_UNIPHY_MMD3_EEE_TLU_REGS | + QCA8084_UNIPHY_MMD3_EEE_TWL_REGS); + + qca8084_uniphy_xpcs_modify_mmd(QCA8084_UNIPHY_MMD3, + QCA8084_UNIPHY_MMD3_EEE_RX_TIMER, + 0x1fff, QCA8084_UNIPHY_MMD3_EEE_100US_REG_REGS| + QCA8084_UNIPHY_MMD3_EEE_RWR_REG_REGS); + + /*enable TRN_LPI*/ + qca8084_uniphy_xpcs_modify_mmd(QCA8084_UNIPHY_MMD3, + QCA8084_UNIPHY_MMD3_EEE_MODE_CTRL1, + 0x101, QCA8084_UNIPHY_MMD3_EEE_TRANS_LPI_MODE| + QCA8084_UNIPHY_MMD3_EEE_TRANS_RX_LPI_MODE); + + /*enable TX/RX LPI pattern*/ + qca8084_uniphy_xpcs_modify_mmd(QCA8084_UNIPHY_MMD3, + QCA8084_UNIPHY_MMD3_EEE_MODE_CTRL, + 0x3, QCA8084_UNIPHY_MMD3_EEE_EN); +} + +static void qca8084_uniphy_xpcs_10g_r_linkup(void) +{ + uint16_t uniphy_data = 0; + uint32_t retries = 100, linkup = 0; + + /* wait 10G_R link up */ + while (linkup != QCA8084_UNIPHY_MMD3_10GBASE_R_UP) { + mdelay(1); + if (retries-- == 0) + pr_debug("10g_r link up timeout\n"); + uniphy_data = qca8084_uniphy_xpcs_mmd_read(QCA8084_UNIPHY_MMD3, + QCA8084_UNIPHY_MMD3_10GBASE_R_PCS_STATUS1); + + linkup = (uniphy_data & QCA8084_UNIPHY_MMD3_10GBASE_R_UP); + } +} + +static void qca8084_uniphy_xpcs_soft_reset(void) +{ + uint16_t uniphy_data = 0; + uint32_t retries = 100, reset_done = QCA8084_UNIPHY_MMD3_XPCS_SOFT_RESET; + + qca8084_uniphy_xpcs_modify_mmd(QCA8084_UNIPHY_MMD3, + QCA8084_UNIPHY_MMD3_DIG_CTRL1, 0x8000, + QCA8084_UNIPHY_MMD3_XPCS_SOFT_RESET); + + while (reset_done) { + mdelay(1); + if (retries-- == 0) + pr_debug("xpcs soft reset timeout\n"); + uniphy_data = qca8084_uniphy_xpcs_mmd_read(QCA8084_UNIPHY_MMD3, + QCA8084_UNIPHY_MMD3_DIG_CTRL1); + + reset_done = (uniphy_data & QCA8084_UNIPHY_MMD3_XPCS_SOFT_RESET); + } +} + +void qca8084_uniphy_xpcs_speed_set(uint32_t qca8084_port_id, + fal_port_speed_t speed) +{ + uint32_t xpcs_speed = 0; + + switch(speed) + { + case FAL_SPEED_2500: + xpcs_speed = QCA8084_UNIPHY_MMD_XPC_SPEED_2500; + break; + case FAL_SPEED_1000: + xpcs_speed = QCA8084_UNIPHY_MMD_XPC_SPEED_1000; + break; + case FAL_SPEED_100: + xpcs_speed = QCA8084_UNIPHY_MMD_XPC_SPEED_100; + break; + case FAL_SPEED_10: + xpcs_speed = QCA8084_UNIPHY_MMD_XPC_SPEED_10; + break; + default: + pr_debug("Unknown speed\n"); + return; + } + qca8084_uniphy_xpcs_modify_port_mmd(qca8084_port_id, + QCA8084_UNIPHY_MMD_MII_CTRL, + QCA8084_UNIPHY_MMD_XPC_SPEED_MASK, + xpcs_speed); +} + +void qca8084_uniphy_uqxgmii_function_reset(uint32_t qca8084_port_id) +{ + uint32_t uniphy_addr = 0; + + qca8084_serdes_addr_get(QCA8084_UNIPHY_SGMII_1, &uniphy_addr); + + qca8084_phy_modify_mmd(uniphy_addr, QCA8084_UNIPHY_MMD1, + QCA8084_UNIPHY_MMD1_USXGMII_RESET, BIT(qca8084_port_id-1), 0); + mdelay(1); + qca8084_phy_modify_mmd(uniphy_addr, QCA8084_UNIPHY_MMD1, + QCA8084_UNIPHY_MMD1_USXGMII_RESET, BIT(qca8084_port_id-1), + BIT(qca8084_port_id-1)); + if(qca8084_port_id == PORT1) + qca8084_uniphy_xpcs_modify_mmd(QCA8084_UNIPHY_MMD3, + QCA8084_UNIPHY_MMD_MII_DIG_CTRL, + 0x400, QCA8084_UNIPHY_MMD3_USXG_FIFO_RESET); + else + qca8084_uniphy_xpcs_modify_port_mmd(qca8084_port_id, + QCA8084_UNIPHY_MMD_MII_DIG_CTRL, + 0x20, QCA8084_UNIPHY_MMD_USXG_FIFO_RESET); +} + +void qca8084_uniphy_xpcs_autoneg_restart(uint32_t qca8084_port_id) +{ + uint32_t retries = 500, uniphy_data = 0, mmd_id = 0; + + mmd_id = qca8084_uniphy_xpcs_port_to_mmd(qca8084_port_id); + qca8084_uniphy_xpcs_modify_mmd(mmd_id, QCA8084_UNIPHY_MMD_MII_CTRL, + QCA8084_UNIPHY_MMD_MII_AN_RESTART, QCA8084_UNIPHY_MMD_MII_AN_RESTART); + mdelay(1); + uniphy_data = qca8084_uniphy_xpcs_mmd_read(mmd_id, + QCA8084_UNIPHY_MMD_MII_ERR_SEL); + while(!(uniphy_data & QCA8084_UNIPHY_MMD_MII_AN_COMPLETE_INT)) + { + mdelay(1); + if (retries-- == 0) + { + pr_debug("xpcs uniphy autoneg restart timeout\n"); + } + uniphy_data = qca8084_uniphy_xpcs_mmd_read(mmd_id, + QCA8084_UNIPHY_MMD_MII_ERR_SEL); + } +} + +static void _qca8084_interface_uqxgmii_mode_set(uint32_t uniphy_addr) +{ + uint32_t qca8084_port_id = 0, phy_addr = 0; + + /*reset xpcs*/ + pr_debug("reset xpcs\n"); + qca8084_clk_assert(QCA8084_UNIPHY_XPCS_RST); + /*select xpcs mode*/ + pr_debug("select xpcs mode\n"); + qca8084_phy_modify_mmd(uniphy_addr, QCA8084_UNIPHY_MMD1, + QCA8084_UNIPHY_MMD1_MODE_CTRL, 0x1f00, QCA8084_UNIPHY_MMD1_XPCS_MODE); + /*config dapa pass as usxgmii*/ + pr_debug("config dapa pass as usxgmii\n"); + qca8084_phy_modify_mmd(uniphy_addr, QCA8084_UNIPHY_MMD1, + QCA8084_UNIPHY_MMD1_GMII_DATAPASS_SEL, QCA8084_UNIPHY_MMD1_DATAPASS_MASK, + QCA8084_UNIPHY_MMD1_DATAPASS_USXGMII); + /*reset and release uniphy GMII/XGMII and ethphy GMII*/ + pr_debug("reset and release uniphy GMII/XGMII and ethphy GMII\n"); + for(qca8084_port_id = PORT1; qca8084_port_id <= PORT4; + qca8084_port_id++) + { + qca8084_port_clk_reset(qca8084_port_id, + QCA8084_CLK_TYPE_UNIPHY|QCA8084_CLK_TYPE_EPHY); + } + + /*ana sw reset and release*/ + pr_debug("ana sw reset and release\n"); + qca8084_phy_modify_mii(uniphy_addr, + QCA8084_UNIPHY_PLL_POWER_ON_AND_RESET, 0x40, QCA8084_UNIPHY_ANA_SOFT_RESET); + mdelay(10); + qca8084_phy_modify_mii(uniphy_addr, + QCA8084_UNIPHY_PLL_POWER_ON_AND_RESET, 0x40, QCA8084_UNIPHY_ANA_SOFT_RELEASE); + + /*Wait calibration done*/ + pr_debug("Wait calibration done\n"); + qca8084_uniphy_calibration(uniphy_addr); + /*Enable SSCG(Spread Spectrum Clock Generator)*/ + pr_debug("enable uniphy sscg\n"); + qca8084_phy_modify_mmd(uniphy_addr, QCA8084_UNIPHY_MMD1, + QCA8084_UNIPHY_MMD1_CDA_CONTROL1, 0x8, QCA8084_UNIPHY_MMD1_SSCG_ENABLE); + /*release XPCS*/ + pr_debug("release XPCS\n"); + qca8084_clk_deassert(QCA8084_UNIPHY_XPCS_RST); + /*ethphy software reset*/ + pr_debug("ethphy software reset\n"); + for(qca8084_port_id = PORT1; qca8084_port_id <= PORT4; + qca8084_port_id++) + { + qca8084_ephy_addr_get(qca8084_port_id, &phy_addr); + qca8084_phy_reset(phy_addr); + } + /*Set BaseR mode*/ + pr_debug("Set BaseR mode\n"); + qca8084_uniphy_xpcs_modify_mmd(QCA8084_UNIPHY_MMD3, + QCA8084_UNIPHY_MMD3_PCS_CTRL2, 0xf, QCA8084_UNIPHY_MMD3_PCS_TYPE_10GBASE_R); + /*wait 10G base_r link up*/ + pr_debug("wait 10G base_r link up\n"); + qca8084_uniphy_xpcs_10g_r_linkup(); + /*enable UQXGMII mode*/ + pr_debug("enable UQSXGMII mode\n"); + qca8084_uniphy_xpcs_modify_mmd(QCA8084_UNIPHY_MMD3, + QCA8084_UNIPHY_MMD3_DIG_CTRL1, 0x200, QCA8084_UNIPHY_MMD3_USXGMII_EN); + /*set UQXGMII mode*/ + pr_debug("set QXGMII mode\n"); + qca8084_uniphy_xpcs_modify_mmd(QCA8084_UNIPHY_MMD3, + QCA8084_UNIPHY_MMD3_VR_RPCS_TPC, 0x1c00, QCA8084_UNIPHY_MMD3_QXGMII_EN); + /*set AM interval*/ + pr_debug("set AM interval\n"); + qca8084_uniphy_xpcs_mmd_write(QCA8084_UNIPHY_MMD3, + QCA8084_UNIPHY_MMD3_MII_AM_INTERVAL, QCA8084_UNIPHY_MMD3_MII_AM_INTERVAL_VAL); + /*xpcs software reset*/ + pr_debug("xpcs software reset\n"); + qca8084_uniphy_xpcs_soft_reset(); +} + +void qca8084_interface_uqxgmii_mode_set(void) +{ + uint32_t uniphy_addr = 0, qca8084_port_id = 0; + + qca8084_serdes_addr_get(QCA8084_UNIPHY_SGMII_1, &uniphy_addr); + + /*disable IPG_tuning bypass*/ + pr_debug("disable IPG_tuning bypass\n"); + qca8084_phy_modify_mmd(uniphy_addr, QCA8084_UNIPHY_MMD1, + QCA8084_UNIPHY_MMD1_BYPASS_TUNING_IPG, + QCA8084_UNIPHY_MMD1_BYPASS_TUNING_IPG_EN, 0); + /*disable uniphy GMII/XGMII clock and disable ethphy GMII clock*/ + pr_debug("disable uniphy GMII/XGMII clock and ethphy GMII clock\n"); + for(qca8084_port_id = PORT1; qca8084_port_id <= PORT4; + qca8084_port_id++) + { + qca8084_port_clk_en_set(qca8084_port_id, + QCA8084_CLK_TYPE_UNIPHY|QCA8084_CLK_TYPE_EPHY, 0); + } + /*configure uqxgmii mode*/ + pr_debug("configure uqxgmii mode\n"); + _qca8084_interface_uqxgmii_mode_set(uniphy_addr); + /*enable auto-neg complete interrupt,Mii using mii-4bits, + configure as PHY mode, enable autoneg ability*/ + pr_debug("enable auto-neg complete interrupt, Mii using mii-4bits," + " configure as PHY mode, enable autoneg ability, disable TICD\n"); + for (qca8084_port_id = PORT1; qca8084_port_id <= PORT4; + qca8084_port_id++) + { + /*enable auto-neg complete interrupt,Mii using mii-4bits,configure as PHY mode*/ + qca8084_uniphy_xpcs_modify_port_mmd(qca8084_port_id, + QCA8084_UNIPHY_MMD_MII_AN_INT_MSK, 0x109, + QCA8084_UNIPHY_MMD_AN_COMPLETE_INT | + QCA8084_UNIPHY_MMD_MII_4BITS_CTRL | + QCA8084_UNIPHY_MMD_TX_CONFIG_CTRL); + + /*enable autoneg ability*/ + qca8084_uniphy_xpcs_modify_port_mmd(qca8084_port_id, + QCA8084_UNIPHY_MMD_MII_CTRL, 0x3060, QCA8084_UNIPHY_MMD_MII_AN_ENABLE | + QCA8084_UNIPHY_MMD_XPC_SPEED_1000); + + /*disable TICD*/ + qca8084_uniphy_xpcs_modify_port_mmd(qca8084_port_id, + QCA8084_UNIPHY_MMD_MII_XAUI_MODE_CTRL, 0x1, + QCA8084_UNIPHY_MMD_TX_IPG_CHECK_DISABLE); + } + + /*enable EEE for xpcs*/ + pr_debug("enable EEE for xpcs\n"); + qca8084_uniphy_xpcs_8023az_enable(); +} +#endif /* CONFIG_QCA8084_PHY_MODE */ + +#ifdef CONFIG_QCA8084_SWT_MODE +void qca8084_uniphy_sgmii_function_reset(u32 uniphy_index) +{ + u32 uniphy_addr = 0; + + qca8084_serdes_addr_get(uniphy_index, &uniphy_addr); + + /*sgmii channel0 adpt reset*/ + qca8084_phy_modify_mmd(uniphy_addr, QCA8084_UNIPHY_MMD1, + QCA8084_UNIPHY_MMD1_CHANNEL0_CFG, QCA8084_UNIPHY_MMD1_SGMII_ADPT_RESET, 0); + mdelay(1); + qca8084_phy_modify_mmd(uniphy_addr, QCA8084_UNIPHY_MMD1, + QCA8084_UNIPHY_MMD1_CHANNEL0_CFG, QCA8084_UNIPHY_MMD1_SGMII_ADPT_RESET, + QCA8084_UNIPHY_MMD1_SGMII_ADPT_RESET); + /*ipg tune reset*/ + qca8084_phy_modify_mmd(uniphy_addr, QCA8084_UNIPHY_MMD1, + QCA8084_UNIPHY_MMD1_USXGMII_RESET, QCA8084_UNIPHY_MMD1_SGMII_FUNC_RESET, 0); + mdelay(1); + qca8084_phy_modify_mmd(uniphy_addr, QCA8084_UNIPHY_MMD1, + QCA8084_UNIPHY_MMD1_USXGMII_RESET, QCA8084_UNIPHY_MMD1_SGMII_FUNC_RESET, + QCA8084_UNIPHY_MMD1_SGMII_FUNC_RESET); + +} + +void qca8084_interface_sgmii_mode_set(u32 uniphy_index, u32 qca8084_port_id, mac_config_t *config) +{ + u32 uniphy_addr = 0, mode_ctrl = 0, speed_mode = 0; + u32 uniphy_port_id = 0, ethphy_clk_mask = 0; + u64 raw_clk = 0; + + /*get the uniphy address*/ + qca8084_serdes_addr_get(uniphy_index, &uniphy_addr); + + if(config->mac_mode == QCA8084_MAC_MODE_SGMII) + { + mode_ctrl = QCA8084_UNIPHY_MMD1_SGMII_MODE; + raw_clk = UNIPHY_CLK_RATE_125M; + } + else + { + mode_ctrl = QCA8084_UNIPHY_MMD1_SGMII_PLUS_MODE; + raw_clk = UNIPHY_CLK_RATE_312M; + } + + if(config->clock_mode == QCA8084_INTERFACE_CLOCK_MAC_MODE) + mode_ctrl |= QCA8084_UNIPHY_MMD1_SGMII_MAC_MODE; + else + { + mode_ctrl |= QCA8084_UNIPHY_MMD1_SGMII_PHY_MODE; + /*eththy clock should be accessed for phy mode*/ + ethphy_clk_mask = QCA8084_CLK_TYPE_EPHY; + } + + pr_debug("uniphy:%d,mode:%s,autoneg_en:%d,force_speed:%d,clk_mask:0x%x\n", + uniphy_index, (config->mac_mode == QCA8084_MAC_MODE_SGMII)?"sgmii":"sgmii plus", + config->auto_neg, config->force_speed, + ethphy_clk_mask); + + /*GMII interface clock disable*/ + pr_debug("GMII interface clock disable\n"); + qca8084_port_clk_en_set(qca8084_port_id, ethphy_clk_mask, 0); + + /*when access uniphy0 clock, port5 should be used, but for phy mode, + the port 4 connect to uniphy0, so need to change the port id*/ + if(uniphy_index == QCA8084_UNIPHY_SGMII_0) + uniphy_port_id = PORT5; + else + uniphy_port_id = qca8084_port_id; + qca8084_port_clk_en_set(uniphy_port_id, QCA8084_CLK_TYPE_UNIPHY, 0); + + /*uniphy1 xpcs reset, and configure raw clk*/ + if(uniphy_index == QCA8084_UNIPHY_SGMII_1) + { + pr_debug("uniphy1 xpcs reset, confiugre raw clock as:%lld\n", + raw_clk); + qca8084_clk_assert(QCA8084_UNIPHY_XPCS_RST); + qca8084_uniphy_raw_clock_set(QCA8084_P_UNIPHY1_RX, raw_clk); + qca8084_uniphy_raw_clock_set(QCA8084_P_UNIPHY1_TX, raw_clk); + } + else + { + pr_debug("uniphy0 configure raw clock as %lld\n", raw_clk); + qca8084_uniphy_raw_clock_set(QCA8084_P_UNIPHY0_RX, raw_clk); + qca8084_uniphy_raw_clock_set(QCA8084_P_UNIPHY0_TX, raw_clk); + } + + /*configure SGMII mode or SGMII+ mode*/ + qca8084_phy_modify_mmd(uniphy_addr, QCA8084_UNIPHY_MMD1, + QCA8084_UNIPHY_MMD1_MODE_CTRL, QCA8084_UNIPHY_MMD1_SGMII_MODE_CTRL_MASK, + mode_ctrl); + + /*GMII datapass selection, 0 is for SGMII, 1 is for USXGMII*/ + qca8084_phy_modify_mmd(uniphy_addr, QCA8084_UNIPHY_MMD1, + QCA8084_UNIPHY_MMD1_GMII_DATAPASS_SEL, QCA8084_UNIPHY_MMD1_DATAPASS_MASK, QCA8084_UNIPHY_MMD1_DATAPASS_SGMII); + /*configue force or autoneg*/ + if(!config->auto_neg) + { + qca8084_port_speed_clock_set(qca8084_port_id, + config->force_speed); + switch (config->force_speed) + { + case FAL_SPEED_10: + speed_mode = QCA8084_UNIPHY_MMD1_CH0_FORCE_ENABLE | + QCA8084_UNIPHY_MMD1_CH0_FORCE_SPEED_10M; + break; + case FAL_SPEED_100: + speed_mode = QCA8084_UNIPHY_MMD1_CH0_FORCE_ENABLE | + QCA8084_UNIPHY_MMD1_CH0_FORCE_SPEED_100M; + break; + case FAL_SPEED_1000: + case FAL_SPEED_2500: + speed_mode = QCA8084_UNIPHY_MMD1_CH0_FORCE_ENABLE | + QCA8084_UNIPHY_MMD1_CH0_FORCE_SPEED_1G; + break; + default: + break; + } + } + else + { + speed_mode = QCA8084_UNIPHY_MMD1_CH0_AUTONEG_ENABLE; + } + qca8084_phy_modify_mmd(uniphy_addr, QCA8084_UNIPHY_MMD1, + QCA8084_UNIPHY_MMD1_CHANNEL0_CFG, QCA8084_UNIPHY_MMD1_CH0_FORCE_SPEED_MASK, speed_mode); + + /*GMII interface clock reset and release\n*/ + pr_debug("GMII interface clock reset and release\n"); + qca8084_port_clk_reset(qca8084_port_id, ethphy_clk_mask); + qca8084_port_clk_reset(uniphy_port_id, QCA8084_CLK_TYPE_UNIPHY); + + /*analog software reset and release*/ + pr_debug("analog software reset and release\n"); + qca8084_phy_modify_mii(uniphy_addr, + QCA8084_UNIPHY_PLL_POWER_ON_AND_RESET, 0x40, QCA8084_UNIPHY_ANA_SOFT_RESET); + mdelay(1); + qca8084_phy_modify_mii(uniphy_addr, + QCA8084_UNIPHY_PLL_POWER_ON_AND_RESET, 0x40, QCA8084_UNIPHY_ANA_SOFT_RELEASE); + + /*wait uniphy calibration done*/ + pr_debug("wait uniphy calibration done\n"); + qca8084_uniphy_calibration(uniphy_addr); + + /*GMII interface clock enable*/ + pr_debug("GMII interface clock enable\n"); + qca8084_port_clk_en_set(qca8084_port_id, ethphy_clk_mask, 1); + qca8084_port_clk_en_set(uniphy_port_id, QCA8084_CLK_TYPE_UNIPHY, 1); + + return; +} + +uint8_t qca8084_uniphy_mode_check(uint32_t uniphy_index, + qca8084_uniphy_mode_t uniphy_mode) +{ + uint32_t uniphy_addr = 0; + uint16_t uniphy_mode_ctrl_data = 0; + + qca8084_serdes_addr_get(uniphy_index, &uniphy_addr); + + uniphy_mode_ctrl_data = qca8084_phy_mmd_read(uniphy_addr, + QCA8084_UNIPHY_MMD1, QCA8084_UNIPHY_MMD1_MODE_CTRL); + if(uniphy_mode_ctrl_data == PHY_INVALID_DATA) + return 0; + + if(!(uniphy_mode & uniphy_mode_ctrl_data)) + return 0; + + return 1; +} +#endif /* CONFIG_QCA8084_SWT_MODE */ + +#ifdef CONFIG_QCA8084_BYPASS_MODE +void qca8084_phy_sgmii_mode_set(uint32_t phy_addr, u32 interface_mode, + u32 link, fal_port_speed_t speed) +{ + uint32_t phy_addr_tmp = 0; + mac_config_t config = {0}; + + if(interface_mode == PHY_SGMII_BASET) + config.mac_mode = QCA8084_MAC_MODE_SGMII; + else if(interface_mode == PORT_SGMII_PLUS) + config.mac_mode = QCA8084_MAC_MODE_SGMII_PLUS; + else { + printf("Unsupported interface mode \n"); + return; + } + + config.clock_mode = QCA8084_INTERFACE_CLOCK_PHY_MODE; + config.auto_neg = 1; + + qca8084_ephy_addr_get(PORT4, &phy_addr_tmp); + if(phy_addr_tmp != phy_addr) + { + printf("phy_addr:0x%x is not matched with port4 phy addr:0x%x\n", + phy_addr, phy_addr_tmp); + return; + } + + qca8084_interface_sgmii_mode_set(QCA8084_UNIPHY_SGMII_0, + PORT4, &config); + + qca8084_phy_sgmii_speed_fixup(phy_addr, link, speed); + return; +} +#endif /* CONFIG_QCA8084_BYPASS_MODE */ + diff --git a/sources/uboot-be550/drivers/net/ipq_common/ipq_qca8084_interface_ctrl.h b/sources/uboot-be550/drivers/net/ipq_common/ipq_qca8084_interface_ctrl.h new file mode 100644 index 00000000..491d715c --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq_common/ipq_qca8084_interface_ctrl.h @@ -0,0 +1,172 @@ +/* + * Copyright (c) 2022, The Linux Foundation. All rights reserved. + + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. +*/ +#ifndef __QCA8084_IF_CTRL_H_ +#define __QCA8084_IF_CTRL_H_ + +#define EPHY_CFG_OFFSET 0xC90F018 +#define EPHY_CFG_EPHY0_ADDR_BOFFSET 0 +#define EPHY_CFG_EPHY1_ADDR_BOFFSET 5 +#define EPHY_CFG_EPHY2_ADDR_BOFFSET 10 +#define EPHY_CFG_EPHY3_ADDR_BOFFSET 15 + +#define SERDES_CFG_OFFSET 0xC90F014 +#define SERDES_CFG_S0_ADDR_BOFFSET 0 +#define SERDES_CFG_S1_ADDR_BOFFSET 5 +#define SERDES_CFG_S1_XPCS_ADDR_BOFFSET 10 + +#define QCA8084_UNIPHY_SGMII_0 0 +#define QCA8084_UNIPHY_SGMII_1 1 +#define QCA8084_UNIPHY_XPCS 2 + +/*UNIPHY MII registers*/ +#define QCA8084_UNIPHY_PLL_POWER_ON_AND_RESET 0 + +/*UNIPHY MII register field*/ +#define QCA8084_UNIPHY_ANA_SOFT_RESET 0 +#define QCA8084_UNIPHY_ANA_SOFT_RELEASE 0x40 + +/*UNIPHY MMD*/ +#define QCA8084_UNIPHY_MMD1 0x1 +#define QCA8084_UNIPHY_MMD3 0x3 +#define QCA8084_UNIPHY_MMD26 0x1a +#define QCA8084_UNIPHY_MMD27 0x1b +#define QCA8084_UNIPHY_MMD28 0x1c +#define QCA8084_UNIPHY_MMD31 0x1f + +/*UNIPHY MMD1 registers*/ +#define QCA8084_UNIPHY_MMD1_CDA_CONTROL1 0x20 +#define QCA8084_UNIPHY_MMD1_CALIBRATION4 0x78 +#define QCA8084_UNIPHY_MMD1_BYPASS_TUNING_IPG 0x189 +#define QCA8084_UNIPHY_MMD1_MODE_CTRL 0x11b +#define QCA8084_UNIPHY_MMD1_CHANNEL0_CFG 0x120 +#define QCA8084_UNIPHY_MMD1_GMII_DATAPASS_SEL 0x180 +#define QCA8084_UNIPHY_MMD1_USXGMII_RESET 0x18c + +/*UNIPHY MMD1 register field*/ +#define QCA8084_UNIPHY_MMD1_BYPASS_TUNING_IPG_EN 0x0fff +#define QCA8084_UNIPHY_MMD1_XPCS_MODE 0x1000 +#define QCA8084_UNIPHY_MMD1_SGMII_MODE 0x400 +#define QCA8084_UNIPHY_MMD1_SGMII_PLUS_MODE 0x800 +#define QCA8084_UNIPHY_MMD1_1000BASE_X 0x0 +#define QCA8084_UNIPHY_MMD1_SGMII_PHY_MODE 0x10 +#define QCA8084_UNIPHY_MMD1_SGMII_MAC_MODE 0x20 +#define QCA8084_UNIPHY_MMD1_SGMII_MODE_CTRL_MASK 0x1f70 +#define QCA8084_UNIPHY_MMD1_CH0_FORCE_SPEED_MASK 0xe +#define QCA8084_UNIPHY_MMD1_CH0_AUTONEG_ENABLE 0x0 +#define QCA8084_UNIPHY_MMD1_CH0_FORCE_ENABLE 0x8 +#define QCA8084_UNIPHY_MMD1_CH0_FORCE_SPEED_1G 0x4 +#define QCA8084_UNIPHY_MMD1_CH0_FORCE_SPEED_100M 0x2 +#define QCA8084_UNIPHY_MMD1_CH0_FORCE_SPEED_10M 0x0 +#define QCA8084_UNIPHY_MMD1_DATAPASS_MASK 0x1 +#define QCA8084_UNIPHY_MMD1_DATAPASS_USXGMII 0x1 +#define QCA8084_UNIPHY_MMD1_DATAPASS_SGMII 0x0 +#define QCA8084_UNIPHY_MMD1_CALIBRATION_DONE 0x80 +#define QCA8084_UNIPHY_MMD1_SGMII_FUNC_RESET 0x10 +#define QCA8084_UNIPHY_MMD1_SGMII_ADPT_RESET 0x800 +#define QCA8084_UNIPHY_MMD1_SSCG_ENABLE 0x8 + +/*UNIPHY MMD3 registers*/ +#define QCA8084_UNIPHY_MMD3_PCS_CTRL2 0x7 +#define QCA8084_UNIPHY_MMD3_AN_LP_BASE_ABL2 0x14 +#define QCA8084_UNIPHY_MMD3_10GBASE_R_PCS_STATUS1 0x20 +#define QCA8084_UNIPHY_MMD3_DIG_CTRL1 0x8000 +#define QCA8084_UNIPHY_MMD3_EEE_MODE_CTRL 0x8006 +#define QCA8084_UNIPHY_MMD3_VR_RPCS_TPC 0x8007 +#define QCA8084_UNIPHY_MMD3_EEE_TX_TIMER 0x8008 +#define QCA8084_UNIPHY_MMD3_EEE_RX_TIMER 0x8009 +#define QCA8084_UNIPHY_MMD3_MII_AM_INTERVAL 0x800a +#define QCA8084_UNIPHY_MMD3_EEE_MODE_CTRL1 0x800b + +/*UNIPHY MMD3 register field*/ +#define QCA8084_UNIPHY_MMD3_PCS_TYPE_10GBASE_R 0 +#define QCA8084_UNIPHY_MMD3_10GBASE_R_UP 0x1000 +#define QCA8084_UNIPHY_MMD3_USXGMII_EN 0x200 +#define QCA8084_UNIPHY_MMD3_QXGMII_EN 0x1400 +#define QCA8084_UNIPHY_MMD3_MII_AM_INTERVAL_VAL 0x6018 +#define QCA8084_UNIPHY_MMD3_XPCS_SOFT_RESET 0x8000 +#define QCA8084_UNIPHY_MMD3_XPCS_EEE_CAP 0x40 +#define QCA8084_UNIPHY_MMD3_EEE_RES_REGS 0x100 +#define QCA8084_UNIPHY_MMD3_EEE_SIGN_BIT_REGS 0x40 +#define QCA8084_UNIPHY_MMD3_EEE_EN 0x3 +#define QCA8084_UNIPHY_MMD3_EEE_TSL_REGS 0xa +#define QCA8084_UNIPHY_MMD3_EEE_TLU_REGS 0xc0 +#define QCA8084_UNIPHY_MMD3_EEE_TWL_REGS 0x1600 +#define QCA8084_UNIPHY_MMD3_EEE_100US_REG_REGS 0xc8 +#define QCA8084_UNIPHY_MMD3_EEE_RWR_REG_REGS 0x1c00 +#define QCA8084_UNIPHY_MMD3_EEE_TRANS_LPI_MODE 0x1 +#define QCA8084_UNIPHY_MMD3_EEE_TRANS_RX_LPI_MODE 0x100 +#define QCA8084_UNIPHY_MMD3_USXG_FIFO_RESET 0x400 + +/*UNIPHY MMD26 27 28 31 registers*/ +#define QCA8084_UNIPHY_MMD_MII_CTRL 0 +#define QCA8084_UNIPHY_MMD_MII_DIG_CTRL 0x8000 +#define QCA8084_UNIPHY_MMD_MII_AN_INT_MSK 0x8001 +#define QCA8084_UNIPHY_MMD_MII_ERR_SEL 0x8002 +#define QCA8084_UNIPHY_MMD_MII_XAUI_MODE_CTRL 0x8004 + +/*UNIPHY MMD26 27 28 31 register field*/ +#define QCA8084_UNIPHY_MMD_AN_COMPLETE_INT 0x1 +#define QCA8084_UNIPHY_MMD_MII_4BITS_CTRL 0x0 +#define QCA8084_UNIPHY_MMD_TX_CONFIG_CTRL 0x8 +#define QCA8084_UNIPHY_MMD_MII_AN_ENABLE 0x1000 +#define QCA8084_UNIPHY_MMD_MII_AN_RESTART 0x200 +#define QCA8084_UNIPHY_MMD_MII_AN_COMPLETE_INT 0x1 +#define QCA8084_UNIPHY_MMD_USXG_FIFO_RESET 0x20 +#define QCA8084_UNIPHY_MMD_XPC_SPEED_MASK 0x2060 +#define QCA8084_UNIPHY_MMD_XPC_SPEED_2500 0x20 +#define QCA8084_UNIPHY_MMD_XPC_SPEED_1000 0x40 +#define QCA8084_UNIPHY_MMD_XPC_SPEED_100 0x2000 +#define QCA8084_UNIPHY_MMD_XPC_SPEED_10 0 +#define QCA8084_UNIPHY_MMD_TX_IPG_CHECK_DISABLE 0x1 + +#define UNIPHY_CLK_RATE_25M 25000000 +#define UNIPHY_CLK_RATE_50M 50000000 +#define UNIPHY_CLK_RATE_125M 125000000 +#define UNIPHY_CLK_RATE_312M 312500000 +#define UNIPHY_DEFAULT_RATE UNIPHY_CLK_RATE_125M + +typedef enum { + QCA8084_UNIPHY_MAC = QCA8084_UNIPHY_MMD1_SGMII_MAC_MODE, + QCA8084_UNIPHY_PHY = QCA8084_UNIPHY_MMD1_SGMII_PHY_MODE, + QCA8084_UNIPHY_SGMII = QCA8084_UNIPHY_MMD1_SGMII_MODE, + QCA8084_UNIPHY_SGMII_PLUS = QCA8084_UNIPHY_MMD1_SGMII_PLUS_MODE, + QCA8084_UNIPHY_UQXGMII = QCA8084_UNIPHY_MMD1_XPCS_MODE, +} qca8084_uniphy_mode_t; + +typedef enum { + QCA8084_INTERFACE_CLOCK_MAC_MODE = 0, + QCA8084_INTERFACE_CLOCK_PHY_MODE = 1, +} qca8084_clock_mode_t; + +typedef enum { + QCA8084_MAC_MODE_RGMII = 0, + QCA8084_MAC_MODE_GMII, + QCA8084_MAC_MODE_MII, + QCA8084_MAC_MODE_SGMII, + QCA8084_MAC_MODE_FIBER, + QCA8084_MAC_MODE_RMII, + QCA8084_MAC_MODE_SGMII_PLUS, + QCA8084_MAC_MODE_DEFAULT, + QCA8084_MAC_MODE_MAX = 0xFF, +} qca8084_mac_mode_t; + +typedef struct { + qca8084_mac_mode_t mac_mode; + qca8084_clock_mode_t clock_mode; + bool auto_neg; + u32 force_speed; + bool prbs_enable; + bool rem_phy_lpbk; +} mac_config_t; + +#endif diff --git a/sources/uboot-be550/drivers/net/ipq_common/rtl8261_error.h b/sources/uboot-be550/drivers/net/ipq_common/rtl8261_error.h new file mode 100644 index 00000000..7fc186da --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq_common/rtl8261_error.h @@ -0,0 +1,158 @@ +/* + * SPDX-License-Identifier: GPL-2.0-only + * + * Copyright (c) 2023 Realtek Semiconductor Corp. All rights reserved. + */ + +#ifndef __COMMON_ERROR_H__ +#define __COMMON_ERROR_H__ + +/* + * Data Type Declaration + */ +typedef enum rt_error_common_e +{ + RT_ERR_FAILED = -1, /* General Error */ + + /* 0x0000xxxx for common error code */ + RT_ERR_OK = 0, /* 0x00000000, OK */ + RT_ERR_INPUT = 0xF001, /* 0x0000F001, invalid input parameter */ + RT_ERR_UNIT_ID, /* 0x0000F002, invalid unit id */ + RT_ERR_PORT_ID, /* 0x0000F003, invalid port id */ + RT_ERR_PORT_MASK, /* 0x0000F004, invalid port mask */ + RT_ERR_PORT_LINKDOWN, /* 0x0000F005, link down port status */ + RT_ERR_ENTRY_INDEX, /* 0x0000F006, invalid entry index */ + RT_ERR_NULL_POINTER, /* 0x0000F007, input parameter is null pointer */ + RT_ERR_QUEUE_ID, /* 0x0000F008, invalid queue id */ + RT_ERR_QUEUE_NUM, /* 0x0000F009, invalid queue number */ + RT_ERR_BUSYWAIT_TIMEOUT, /* 0x0000F00a, busy watting time out */ + RT_ERR_MAC, /* 0x0000F00b, invalid mac address */ + RT_ERR_OUT_OF_RANGE, /* 0x0000F00c, input parameter out of range */ + RT_ERR_CHIP_NOT_SUPPORTED, /* 0x0000F00d, functions not supported by this chip model */ + RT_ERR_SMI, /* 0x0000F00e, SMI error */ + RT_ERR_NOT_INIT, /* 0x0000F00f, The module is not initial */ + RT_ERR_CHIP_NOT_FOUND, /* 0x0000F010, The chip can not found */ + RT_ERR_NOT_ALLOWED, /* 0x0000F011, actions not allowed by the function */ + RT_ERR_DRIVER_NOT_FOUND, /* 0x0000F012, The driver can not found */ + RT_ERR_SEM_LOCK_FAILED, /* 0x0000F013, Failed to lock semaphore */ + RT_ERR_SEM_UNLOCK_FAILED, /* 0x0000F014, Failed to unlock semaphore */ + RT_ERR_THREAD_EXIST, /* 0x0000F015, Thread exist */ + RT_ERR_THREAD_CREATE_FAILED, /* 0x0000F016, Thread create fail */ + RT_ERR_FWD_ACTION, /* 0x0000F017, Invalid forwarding Action */ + RT_ERR_IPV4_ADDRESS, /* 0x0000F018, Invalid IPv4 address */ + RT_ERR_IPV6_ADDRESS, /* 0x0000F019, Invalid IPv6 address */ + RT_ERR_PRIORITY, /* 0x0000F01a, Invalid Priority value */ + RT_ERR_FID, /* 0x0000F01b, invalid fid */ + RT_ERR_ENTRY_NOTFOUND, /* 0x0000F01c, specified entry not found */ + RT_ERR_DROP_PRECEDENCE, /* 0x0000F01d, invalid drop precedence */ + RT_ERR_NOT_FINISH, /* 0x0000F01e, Action not finish, still need to wait */ + RT_ERR_TIMEOUT, /* 0x0000F01f, Time out */ + RT_ERR_REG_ARRAY_INDEX_1, /* 0x0000F020, invalid index 1 of register array */ + RT_ERR_REG_ARRAY_INDEX_2, /* 0x0000F021, invalid index 2 of register array */ + RT_ERR_ETHER_TYPE, /* 0x0000F022, invalid ether type */ + RT_ERR_MBUF_PKT_NOT_AVAILABLE, /* 0x0000F023, mbuf->packet is not available */ + RT_ERR_QOS_INVLD_RSN, /* 0x0000F024, invalid pkt to CPU reason */ + RT_ERR_CB_FUNCTION_EXIST, /* 0x0000F025, Callback function exist */ + RT_ERR_CB_FUNCTION_FULL, /* 0x0000F026, Callback function number is full */ + RT_ERR_CB_FUNCTION_NOT_FOUND, /* 0x0000F027, Callback function can not found */ + RT_ERR_TBL_FULL, /* 0x0000F028, The table is full */ + RT_ERR_TRUNK_ID, /* 0x0000F029, invalid trunk id */ + RT_ERR_TYPE, /* 0x0000F02a, invalid type */ + RT_ERR_ENTRY_EXIST, /* 0x0000F02b, entry exists */ + RT_ERR_CHIP_UNDEFINED_VALUE, /* 0x0000F02c, chip returned an undefined value */ + RT_ERR_EXCEEDS_CAPACITY, /* 0x0000F02d, exceeds the capacity of hardware */ + RT_ERR_ENTRY_REFERRED, /* 0x0000F02e, entry is still being referred */ + RT_ERR_OPER_DENIED, /* 0x0000F02f, operation denied */ + RT_ERR_PORT_NOT_SUPPORTED, /* 0x0000F030, functions not supported by this port */ + RT_ERR_SOCKET, /* 0x0000F031, socket error */ + RT_ERR_MEM_ALLOC, /* 0x0000F032, insufficient memory resource */ + RT_ERR_ABORT, /* 0x0000F033, operation aborted */ + RT_ERR_DEV_ID, /* 0x0000F034, invalid device id */ + RT_ERR_DRIVER_NOT_SUPPORTED, /* 0x0000F035, functions not supported by this driver */ + RT_ERR_NOT_SUPPORTED, /* 0x0000F036, functions not supported */ + RT_ERR_SER, /* 0x0000F037, ECC or parity error */ + RT_ERR_MEM_NOT_ALIGN, /* 0x0000F038, memory address is not aligned */ + RT_ERR_SEM_FAKELOCK_OK, /* 0x0000F039, attach thread lock a semaphore which was already locked */ + RT_ERR_CHECK_FAILED, /* 0x0000F03a, check result is failed */ + + RT_ERR_COMMON_END = 0xFFFF /* The symbol is the latest symbol of common error */ +} rt_error_common_t; + +/* + * Macro Definition + */ +#define RT_PARAM_CHK(expr, errCode)\ +do {\ + if ((int32_t)(expr)) {\ + return errCode; \ + }\ +} while (0) + +#define RT_PARAM_CHK_EHDL(expr, errCode, err_hdl)\ +do {\ + if ((int32)(expr)) {\ + {err_hdl}\ + return errCode; \ + }\ +} while (0) + +#define RT_INIT_CHK(state)\ +do {\ + if (INIT_COMPLETED != (state)) {\ + return RT_ERR_NOT_INIT;\ + }\ +} while (0) + +#define RT_INIT_REENTRY_CHK(state)\ +do {\ + if (INIT_COMPLETED == (state)) {\ + printf(" %s had already been initialized!\n", __FUNCTION__);\ + return RT_ERR_OK;\ + }\ +} while (0) + +#define RT_INIT_REENTRY_CHK_NO_WARNING(state)\ + do {\ + if (INIT_COMPLETED == (state)) {\ + return RT_ERR_OK;\ + }\ + } while (0) + +#define RT_ERR_CHK(op, ret)\ +do {\ + if ((ret = (op)) != RT_ERR_OK)\ + return ret;\ +} while(0) + +#define RT_ERR_HDL(op, errHandle, ret)\ +do {\ + if ((ret = (op)) != RT_ERR_OK)\ + goto errHandle;\ +} while(0) + +#define RT_ERR_CHK_EHDL(op, ret, err_hdl)\ +do {\ + if ((ret = (op)) != RT_ERR_OK)\ + {\ + {err_hdl}\ + return ret;\ + }\ +} while(0) + +#define RT_NULL_HDL(pointer, err_label)\ +do {\ + if (NULL == (pointer)) {\ + goto err_label;\ + }\ +} while (0) + +#define RT_ERR_VOID_CHK(op, ret)\ +do {\ + if ((ret = (op)) != RT_ERR_OK) {\ + printf("Fail in %s %d, ret %x!\n", __FUNCTION__, __LINE__, ret);\ + return ;}\ +} while(0) + +#endif /* __COMMON_ERROR_H__ */ + + diff --git a/sources/uboot-be550/drivers/net/ipq_common/rtl8261_patch.c b/sources/uboot-be550/drivers/net/ipq_common/rtl8261_patch.c new file mode 100644 index 00000000..e4cdd3a0 --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq_common/rtl8261_patch.c @@ -0,0 +1,1156 @@ +#include +#include +#include +#include "rtl8261_patch.h" +#include "ipq_phy.h" +#include "rtl8261_error.h" +#include "construct/conf_rtl8264b.c" +#include "construct/conf_rtl8261n_c.c" + +u8 phy_patch_op_translate(u8 patch_mode, u8 patch_op, u8 compare_op) +{ + if (patch_mode != PHY_PATCH_MODE_CMP) + { + return patch_op; + } + else + { + switch (compare_op) + { + case RTK_PATCH_CMP_WS: + return RTK_PATCH_OP_SKIP; + case RTK_PATCH_CMP_W: + case RTK_PATCH_CMP_WC: + case RTK_PATCH_CMP_SWC: + default: + return RTK_PATCH_OP_TO_CMP(patch_op, compare_op); + } + } +} + +static uint16 _phy_rtl826xb_mmd_convert(uint16 page, uint16 addr) +{ + uint16 reg = 0; + if (addr < 16) + { + reg = 0xA400 + (page * 2); + } + else if (addr < 24) + { + reg = (16*page) + ((addr - 16) * 2); + } + else + { + reg = 0xA430 + ((addr - 24) * 2); + } + return reg; +} + +int32_t _phy_rtl826xb_patch_top_get(u32 phy_id, u32 topPage, u32 topReg, u32 *pData) +{ + int32_t ret = 0; + u32 rData = 0; + u32 topAddr = (topPage * 8) + (topReg - 16); + + if ((ret = phy_common_general_reg_mmd_get(phy_id, PHY_MMD_VEND1, topAddr, &rData)) != RT_ERR_OK) + return ret; + *pData = rData; + return RT_ERR_OK; +} + +int32_t _phy_rtl826xb_patch_top_set(u32 phy_id, u32 topPage, u32 topReg, u32 wData) +{ + int32_t ret = 0; + u32 topAddr = (topPage * 8) + (topReg - 16); + if ((ret = phy_common_general_reg_mmd_set(phy_id, PHY_MMD_VEND1, topAddr, wData)) != RT_ERR_OK) + return ret; + return RT_ERR_OK; +} + +int32_t _phy_rtl826xb_patch_wait(u32 phy_id, u32 mmdAddr, u32 mmdReg, u32 data, u32 mask, u8 patch_mode) +{ + int32_t ret = 0; + u32 rData = 0; + u32 cnt = 0; + int32_t count = 1000; + int32_t i = 0; + + void* p = NULL; + uint8 smiBus = HWP_PORT_SMI(phy_id); + uint32 phyChip = HWP_PHY_MODEL_BY_PORT(phy_id); + uint8 bcast_phyad = HWP_PHY_ADDR(phy_id); + + if (patch_mode == PHY_PATCH_MODE_BCAST_BUS) + { + if ((ret = phy_826xb_ctrl_set(phy_id, RTK_PHY_CTRL_MIIM_BCAST, 0)) != RT_ERR_OK) + { + printf("826XB patch wait disable broadcast failed! 0x%X\n", ret); + return ret; + } + + HWP_PORT_TRAVS_EXCEPT_CPU(phy_id, p) + { + if ((HWP_PORT_SMI(phy_id) == smiBus) && (HWP_PHY_MODEL_BY_PORT(phy_id) == phyChip)) + { + for (i = 0; i < count; i++) + { + if ((ret = phy_common_general_reg_mmd_get(phy_id, mmdAddr, mmdReg, &rData)) != RT_ERR_OK) + { + return ret; + } + ++cnt; + + if ((rData & mask) == data) + break; + + mdelay(3); + } + + if (i == count) + { + printf("826XB patch wait[%u,0x%X,0x%X,0x%X]:0x%X cnt:%u\n", mmdAddr, mmdReg, data, mask, rData, cnt); + return RT_ERR_TIMEOUT; + } + } + } + + mdelay(1); + //for port in same SMI bus, set mdio broadcast ENABLE + HWP_PORT_TRAVS_EXCEPT_CPU(phy_id, p) + { + if ((HWP_PORT_SMI(phy_id) == smiBus) && (HWP_PHY_MODEL_BY_PORT(phy_id) == phyChip)) + { + if ((ret = phy_826xb_ctrl_set(phy_id, RTK_PHY_CTRL_MIIM_BCAST_PHYAD, (uint32)bcast_phyad)) != RT_ERR_OK) + { + printf("826XB patch wait set broadcast PHYAD failed! 0x%X\n", ret); + return ret; + } + + if ((ret = phy_826xb_ctrl_set(phy_id, RTK_PHY_CTRL_MIIM_BCAST, 1)) != RT_ERR_OK) + { + printf("826XB patch wait enable broadcast failed! 0x%X\n", ret); + return ret; + } + } + } + } + else if (patch_mode == PHY_PATCH_MODE_BCAST) + { + if ((ret = phy_826xb_ctrl_set(phy_id, RTK_PHY_CTRL_MIIM_BCAST, 0)) != RT_ERR_OK) + { + printf("826x patch wait disable broadcast failed! 0x%X\n", ret); + return ret; + } + + HWP_PORT_TRAVS_EXCEPT_CPU(phy_id, p) + { + if (HWP_PHY_BASE_MACID(phy_id) == HWP_PHY_BASE_MACID(phy_id)) + { + for (i = 0; i < count; i++) + { + if ((ret = phy_common_general_reg_mmd_get(phy_id, mmdAddr, mmdReg, &rData)) != RT_ERR_OK) + { + return ret; + } + ++cnt; + + if ((rData & mask) == data) + break; + mdelay(3); + } + + if (i == count) + { + printf("826x patch wait[%u,0x%X,0x%X,0x%X]:0x%X cnt:%u\n", mmdAddr, mmdReg, data, mask, rData, cnt); + return RT_ERR_TIMEOUT; + } + } + } + + mdelay(1); + //for port in same PHY, set mdio broadcast ENABLE + HWP_PORT_TRAVS_EXCEPT_CPU(unit, p) + { + if (HWP_PHY_BASE_MACID(phy_id) == HWP_PHY_BASE_MACID(phy_id)) + { + if ((ret = phy_826xb_ctrl_set(phy_id, RTK_PHY_CTRL_MIIM_BCAST_PHYAD, (uint32)bcast_phyad)) != RT_ERR_OK) + { + printf("826XB patch wait set broadcast PHYAD failed! 0x%X\n", ret); + return ret; + } + + if ((ret = phy_826xb_ctrl_set(phy_id, RTK_PHY_CTRL_MIIM_BCAST, 1)) != RT_ERR_OK) + { + printf("826XB patch wait enable broadcast failed! 0x%X\n", ret); + return ret; + } + } + } + } + else + { + for (i = 0; i < count; i++) + { + if ((ret = phy_common_general_reg_mmd_get(phy_id, mmdAddr, mmdReg, &rData)) != RT_ERR_OK) + return ret; + + ++cnt; + if ((rData & mask) == data) + break; + + mdelay(1); + } + + if (i == count) + { + printf("826XB patch wait[%u,0x%X,0x%X,0x%X]:0x%X cnt:%u\n", mmdAddr, mmdReg, data, mask, rData, cnt); + return RT_ERR_TIMEOUT; + } + } + + return RT_ERR_OK; +} + +int32_t _phy_rtl826xb_patch_wait_not_equal(u32 phy_id, u32 mmdAddr, u32 mmdReg, u32 data, u32 mask, u8 patch_mode) +{ + int32_t ret = 0; + u32 rData = 0; + u32 cnt = 0; + int count = 1000; + int i = 0; + + void* p = NULL; + u8 smiBus = HWP_PORT_SMI(phy_id); + u32 phyChip = HWP_PHY_MODEL_BY_PORT(phy_id); + u8 bcast_phyad = HWP_PHY_ADDR(phy_id); + + if (patch_mode == PHY_PATCH_MODE_BCAST_BUS) + { + if ((ret = phy_826xb_ctrl_set(phy_id, RTK_PHY_CTRL_MIIM_BCAST, 0)) != RT_ERR_OK) + { + printf("826XB patch wait disable broadcast failed! 0x%X\n", ret); + return ret; + } + + HWP_PORT_TRAVS_EXCEPT_CPU(phy_id, p) + { + if ((HWP_PORT_SMI(phy_id) == smiBus) && (HWP_PHY_MODEL_BY_PORT(phy_id) == phyChip)) + { + for (i = 0; i < count; i++) + { + if ((ret = phy_common_general_reg_mmd_get(phy_id, mmdAddr, mmdReg, &rData)) != RT_ERR_OK) + { + return ret; + } + ++cnt; + + if ((rData & mask) != data) + break; + + mdelay(3); + } + if (i == count) + { + printf("826XB patch wait[%u,0x%X,0x%X,0x%X]:0x%X cnt:%u\n", mmdAddr, mmdReg, data, mask, rData, cnt); + return RT_ERR_TIMEOUT; + } + } + } + + mdelay(1); + //for port in same SMI bus, set mdio broadcast ENABLE + HWP_PORT_TRAVS_EXCEPT_CPU(unit, p) + { + if ((HWP_PORT_SMI(phy_id) == smiBus) && (HWP_PHY_MODEL_BY_PORT(phy_id) == phyChip)) + { + if ((ret = phy_826xb_ctrl_set(phy_id, RTK_PHY_CTRL_MIIM_BCAST_PHYAD, (uint32)bcast_phyad)) != RT_ERR_OK) + { + printf("826XB patch wait set broadcast PHYAD failed! 0x%X\n", ret); + return ret; + } + + if ((ret = phy_826xb_ctrl_set(phy_id, RTK_PHY_CTRL_MIIM_BCAST, 1)) != RT_ERR_OK) + { + printf("826XB patch wait enable broadcast failed! 0x%X\n", ret); + return ret; + } + } + } + } + else if (patch_mode == PHY_PATCH_MODE_BCAST) + { + if ((ret = phy_826xb_ctrl_set(phy_id, RTK_PHY_CTRL_MIIM_BCAST, 0)) != RT_ERR_OK) + { + printf("826x patch wait disable broadcast failed! 0x%X\n", ret); + return ret; + } + + HWP_PORT_TRAVS_EXCEPT_CPU(phy_id, p) + { + if (HWP_PHY_BASE_MACID(phy_id) == HWP_PHY_BASE_MACID(phy_id)) + { + for (i = 0; i < count; i++) + { + if ((ret = phy_common_general_reg_mmd_get(phy_id, mmdAddr, mmdReg, &rData)) != RT_ERR_OK) + { + return ret; + } + ++cnt; + + if (((rData & mask) != data)) + break; + + mdelay(3); + } + + if (i == count) + { + printf("826XB patch wait[%u,0x%X,0x%X,0x%X]:0x%X cnt:%u\n", mmdAddr, mmdReg, data, mask, rData, cnt); + return RT_ERR_TIMEOUT; + } + } + } + + mdelay(1); + //for port in same PHY, set mdio broadcast ENABLE + HWP_PORT_TRAVS_EXCEPT_CPU(phy_id, p) + { + if (HWP_PHY_BASE_MACID(phy_id) == HWP_PHY_BASE_MACID(phy_id)) + { + if ((ret = phy_826xb_ctrl_set(phy_id, RTK_PHY_CTRL_MIIM_BCAST_PHYAD, (uint32)bcast_phyad)) != RT_ERR_OK) + { + printf("826XB patch wait set broadcast PHYAD failed! 0x%X\n", ret); + return ret; + } + + if ((ret = phy_826xb_ctrl_set(phy_id, RTK_PHY_CTRL_MIIM_BCAST, 1)) != RT_ERR_OK) + { + printf("826XB patch wait enable broadcast failed! 0x%X\n", ret); + return ret; + } + } + } + } + else + { + for (i = 0; i < count; i++) + { + if ((ret = phy_common_general_reg_mmd_get(phy_id, mmdAddr, mmdReg, &rData)) != RT_ERR_OK) + return ret; + + ++cnt; + if ((rData & mask) != data) + break; + + mdelay(1); + } + if (i == count) + { + printf("826xb patch wait[%u,0x%X,0x%X,0x%X]:0x%X cnt:%u\n", mmdAddr, mmdReg, data, mask, rData, cnt); + return RT_ERR_TIMEOUT; + } + + } + + return RT_ERR_OK; +} + + +int32_t _phy_rtl826xb_patch_sds_get(u32 phy_id, u32 sdsPage, u32 sdsReg, u32 *pData) +{ + int32_t ret = 0; + u32 rData = 0; + u32 sdsAddr = 0x8000 + (sdsReg << 6) + sdsPage; + + if ((ret = _phy_rtl826xb_patch_top_set(phy_id, 40, 19, sdsAddr)) != RT_ERR_OK) + return ret; + if ((ret = _phy_rtl826xb_patch_top_get(phy_id, 40, 18, &rData)) != RT_ERR_OK) + return ret; + *pData = rData; + return _phy_rtl826xb_patch_wait(phy_id, PHY_MMD_VEND1, 0x143, 0, BIT_15, PHY_PATCH_MODE_NORMAL); +} + +int32_t _phy_rtl826xb_patch_sds_set(u32 phy_id, u32 sdsPage, u32 sdsReg, u32 wData, u8 patch_mode) +{ + int32_t ret = 0; + u32 sdsAddr = 0x8800 + (sdsReg << 6) + sdsPage; + + if ((ret = _phy_rtl826xb_patch_top_set(phy_id, 40, 17, wData)) != RT_ERR_OK) + return ret; + if ((ret = _phy_rtl826xb_patch_top_set(phy_id, 40, 19, sdsAddr)) != RT_ERR_OK) + return ret; + return _phy_rtl826xb_patch_wait(phy_id, PHY_MMD_VEND1, 0x143, 0, BIT_15, patch_mode); +} + +int32_t phy_rtl826xb_patch_op(u32 phy_id, u8 portOffset, rtk_hwpatch_t *pPatch_data, u8 patch_mode) +{ + int32_t ret = RT_ERR_OK; + u32 rData = 0, wData = 0; + u16 reg = 0; + u8 patch_op = 0; + u32 mask = 0; + + if ((pPatch_data->portmask & (1 << portOffset)) == 0) + { + return RT_ERR_ABORT; + } + mask = UINT32_BITS_MASK(pPatch_data->msb, pPatch_data->lsb); + patch_op = phy_patch_op_translate(patch_mode, pPatch_data->patch_op, pPatch_data->compare_op); + + #if 0 + osal_printf("[%s,%d]u%up%u, patch_mode:%u/patch_op:%u/compare_op:%u => op: %u\n", __FUNCTION__, __LINE__, unit, port, + patch_mode, pPatch_data->patch_op, pPatch_data->compare_op, + patch_op); + #endif + + switch (patch_op) + { + case RTK_PATCH_OP_PHY: + reg = _phy_rtl826xb_mmd_convert(pPatch_data->pagemmd, pPatch_data->addr); + if ((pPatch_data->msb != 15) || (pPatch_data->lsb != 0)) + { + RT_ERR_CHK(phy_common_general_reg_mmd_get(phy_id, 31, reg, &rData), ret); + } + wData = REG32_FIELD_SET(rData, pPatch_data->data, pPatch_data->lsb, mask); + RT_ERR_CHK(phy_common_general_reg_mmd_set(phy_id, 31, reg, wData), ret); + break; + case RTK_PATCH_OP_CMP_PHY: + reg = _phy_rtl826xb_mmd_convert(pPatch_data->pagemmd, pPatch_data->addr); + RT_ERR_CHK(phy_common_general_reg_mmd_get(phy_id, 31, reg, &rData), ret); + PHYPATCH_COMPARE(pPatch_data->pagemmd, pPatch_data->addr, pPatch_data->msb, pPatch_data->lsb, pPatch_data->data, rData, mask); + break; + case RTK_PATCH_OP_CMP_SRAM_PHY: + reg = _phy_rtl826xb_mmd_convert(pPatch_data->sram_p, pPatch_data->sram_rw); + RT_ERR_CHK(phy_common_general_reg_mmd_set(phy_id, 31, reg, pPatch_data->sram_a), ret); + reg = _phy_rtl826xb_mmd_convert(pPatch_data->sram_p, pPatch_data->sram_rr); + RT_ERR_CHK(phy_common_general_reg_mmd_get(phy_id, 31, reg, &rData), ret); + PHYPATCH_COMPARE(pPatch_data->pagemmd, pPatch_data->addr, pPatch_data->msb, pPatch_data->lsb, pPatch_data->data, rData, mask); + break; + + case RTK_PATCH_OP_PHYOCP: + if ((pPatch_data->msb != 15) || (pPatch_data->lsb != 0)) + { + RT_ERR_CHK(phy_common_general_reg_mmd_get(phy_id, 31, pPatch_data->addr, &rData), ret); + } + wData = REG32_FIELD_SET(rData, pPatch_data->data, pPatch_data->lsb, mask); + RT_ERR_CHK(phy_common_general_reg_mmd_set(phy_id, 31, pPatch_data->addr, wData), ret); + break; + case RTK_PATCH_OP_CMP_PHYOCP: + RT_ERR_CHK(phy_common_general_reg_mmd_get(phy_id, 31, pPatch_data->addr, &rData), ret); + PHYPATCH_COMPARE(pPatch_data->pagemmd, pPatch_data->addr, pPatch_data->msb, pPatch_data->lsb, pPatch_data->data, rData, mask); + break; + case RTK_PATCH_OP_CMP_SRAM_PHYOCP: + RT_ERR_CHK(phy_common_general_reg_mmd_set(phy_id, 31, pPatch_data->sram_rw, pPatch_data->sram_a), ret); + RT_ERR_CHK(phy_common_general_reg_mmd_get(phy_id, 31, pPatch_data->sram_rr, &rData), ret); + PHYPATCH_COMPARE(pPatch_data->pagemmd, pPatch_data->addr, pPatch_data->msb, pPatch_data->lsb, pPatch_data->data, rData, mask); + break; + + case RTK_PATCH_OP_TOP: + if ((pPatch_data->msb != 15) || (pPatch_data->lsb != 0)) + { + RT_ERR_CHK(_phy_rtl826xb_patch_top_get(phy_id, pPatch_data->pagemmd, pPatch_data->addr, &rData), ret); + } + wData = REG32_FIELD_SET(rData, pPatch_data->data, pPatch_data->lsb, mask); + RT_ERR_CHK(_phy_rtl826xb_patch_top_set(phy_id, pPatch_data->pagemmd, pPatch_data->addr, wData), ret); + break; + case RTK_PATCH_OP_CMP_TOP: + RT_ERR_CHK(_phy_rtl826xb_patch_top_get(phy_id, pPatch_data->pagemmd, pPatch_data->addr, &rData), ret); + PHYPATCH_COMPARE(pPatch_data->pagemmd, pPatch_data->addr, pPatch_data->msb, pPatch_data->lsb, pPatch_data->data, rData, mask); + break; + case RTK_PATCH_OP_CMP_SRAM_TOP: + RT_ERR_CHK(_phy_rtl826xb_patch_top_set(phy_id, pPatch_data->sram_p, pPatch_data->sram_rw, pPatch_data->sram_a), ret); + RT_ERR_CHK(_phy_rtl826xb_patch_top_get(phy_id, pPatch_data->sram_p, pPatch_data->sram_rr, &rData), ret); + PHYPATCH_COMPARE(pPatch_data->pagemmd, pPatch_data->addr, pPatch_data->msb, pPatch_data->lsb, pPatch_data->data, rData, mask); + break; + + case RTK_PATCH_OP_PSDS0: + if ((pPatch_data->msb != 15) || (pPatch_data->lsb != 0)) + { + RT_ERR_CHK(_phy_rtl826xb_patch_sds_get(phy_id, pPatch_data->pagemmd, pPatch_data->addr, &rData), ret); + } + wData = REG32_FIELD_SET(rData, pPatch_data->data, pPatch_data->lsb, mask); + RT_ERR_CHK(_phy_rtl826xb_patch_sds_set(phy_id, pPatch_data->pagemmd, pPatch_data->addr, wData, patch_mode), ret); + break; + case RTK_PATCH_OP_CMP_PSDS0: + RT_ERR_CHK(_phy_rtl826xb_patch_sds_get(phy_id, pPatch_data->pagemmd, pPatch_data->addr, &rData), ret); + PHYPATCH_COMPARE(pPatch_data->pagemmd, pPatch_data->addr, pPatch_data->msb, pPatch_data->lsb, pPatch_data->data, rData, mask); + break; + case RTK_PATCH_OP_CMP_SRAM_PSDS0: + RT_ERR_CHK(_phy_rtl826xb_patch_sds_set(phy_id, pPatch_data->sram_p, pPatch_data->sram_rw, pPatch_data->sram_a, patch_mode), ret); + RT_ERR_CHK(_phy_rtl826xb_patch_sds_get(phy_id, pPatch_data->sram_p, pPatch_data->sram_rr, &rData), ret); + PHYPATCH_COMPARE(pPatch_data->pagemmd, pPatch_data->addr, pPatch_data->msb, pPatch_data->lsb, pPatch_data->data, rData, mask); + break; + + case RTK_PATCH_OP_DELAY_MS: + mdelay(pPatch_data->data); + break; + + case RTK_PATCH_OP_SKIP: + return RT_ERR_ABORT; + + default: + printf("P%u patch_op:%u not implemented yet!\n", phy_id, pPatch_data->patch_op); + return RT_ERR_DRIVER_NOT_SUPPORTED; + } + + return ret; +} + +int32_t phy_patch_op(rt_phy_patch_db_t *pPhy_patchDb, uint32 phy_id, uint8 portOffset, uint8 patch_op, uint16 portmask, uint16 pagemmd, uint16 addr, uint8 msb, uint8 lsb, uint16 data, uint8 patch_mode) +{ + rtk_hwpatch_t op; + + op.patch_op = patch_op; + op.portmask = portmask; + op.pagemmd = pagemmd; + op.addr = addr; + op.msb = msb; + op.lsb = lsb; + op.data = data; + op.compare_op = RTK_PATCH_CMP_W; + + return pPhy_patchDb->fPatch_op(phy_id, portOffset, &op, patch_mode); +} + +static int32_t _phy_rtl826xb_flow_r1(u32 phy_id, u8 portOffset, u8 patch_mode) +{ + int32_t ret = RT_ERR_OK; + rt_phy_patch_db_t *pPatchDb = NULL; + + PHYPATCH_DB_GET(phy_id, pPatchDb); + + //PHYReg_bit w $PHYID 0xb82 16 4 4 0x1 + RT_ERR_CHK(phy_patch_op(pPatchDb, phy_id, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xb82, 16, 4, 4, 0x1, patch_mode), ret); + //PHYReg_bit w $PHYID 0xb82 16 4 4 0x1 + RT_ERR_CHK(phy_patch_op(pPatchDb, phy_id, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xb82, 16, 4, 4, 0x1, patch_mode), ret); + + //set patch_rdy [PHYReg_bit r $PHYID 0xb80 16 6 6] ; Wait for patch ready = 1 + RT_ERR_CHK(_phy_rtl826xb_patch_wait(phy_id, 31, _phy_rtl826xb_mmd_convert(0xb80, 16), BIT_6, BIT_6, patch_mode), ret); + + //PHYReg w $PHYID 0xa43 27 $0x8023 + RT_ERR_CHK(phy_patch_op(pPatchDb, phy_id, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa43, 27, 15, 0, 0x8023, patch_mode), ret); + //PHYReg w $PHYID 0xa43 28 $0x3802 + RT_ERR_CHK(phy_patch_op(pPatchDb, phy_id, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa43, 28, 15, 0, 0x3802, patch_mode), ret); + //PHYReg w $PHYID 0xa43 27 0xB82E + RT_ERR_CHK(phy_patch_op(pPatchDb, phy_id, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa43, 27, 15, 0, 0xB82E, patch_mode), ret); + //PHYReg w $PHYID 0xa43 28 0x1 + RT_ERR_CHK(phy_patch_op(pPatchDb, phy_id, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa43, 28, 15, 0, 0x1, patch_mode), ret); + + return RT_ERR_OK; +} + +static int32_t _phy_rtl826xb_flow_r12(u32 phy_id, u8 portOffset, u8 patch_mode) +{ + int32_t ret = RT_ERR_OK; + rt_phy_patch_db_t *pPatchDb = NULL; + + PHYPATCH_DB_GET(phy_id, pPatchDb); + + //PHYReg_bit w $PHYID 0xb82 16 4 4 0x1 + //RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xb82, 16, 4, 4, 0x1, patch_mode), ret); + //PHYReg_bit w $PHYID 0xb82 16 4 4 0x1 + RT_ERR_CHK(phy_patch_op(pPatchDb, phy_id, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xb82, 16, 4, 4, 0x1, patch_mode), ret); + + //set patch_rdy [PHYReg_bit r $PHYID 0xb80 16 6 6] ; Wait for patch ready = 1 + RT_ERR_CHK(_phy_rtl826xb_patch_wait(phy_id, 31, _phy_rtl826xb_mmd_convert(0xb80, 16), BIT_6, BIT_6, patch_mode), ret); + + //PHYReg w $PHYID 0xa43 27 $0x8023 + RT_ERR_CHK(phy_patch_op(pPatchDb, phy_id, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa43, 27, 15, 0, 0x8023, patch_mode), ret); + //PHYReg w $PHYID 0xa43 28 $0x3800 + RT_ERR_CHK(phy_patch_op(pPatchDb, phy_id, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa43, 28, 15, 0, 0x3800, patch_mode), ret); + //PHYReg w $PHYID 0xa43 27 0xB82E + RT_ERR_CHK(phy_patch_op(pPatchDb, phy_id, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa43, 27, 15, 0, 0xB82E, patch_mode), ret); + //PHYReg w $PHYID 0xa43 28 0x1 + RT_ERR_CHK(phy_patch_op(pPatchDb, phy_id, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa43, 28, 15, 0, 0x1, patch_mode), ret); + + return RT_ERR_OK; +} + +static int32_t _phy_rtl826xb_flow_r2(u32 phy_id, u8 portOffset, u8 patch_mode) +{ + int32_t ret = RT_ERR_OK; + rt_phy_patch_db_t *pPatchDb = NULL; + + PHYPATCH_DB_GET(phy_id, pPatchDb); + + //PHYReg w $PHYID 0xa43 27 0x0000 + RT_ERR_CHK(phy_patch_op(pPatchDb, phy_id, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa43, 27, 15, 0, 0x0000, patch_mode), ret); + //PHYReg w $PHYID 0xa43 28 0x0000 + RT_ERR_CHK(phy_patch_op(pPatchDb, phy_id, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa43, 28, 15, 0, 0x0000, patch_mode), ret); + //PHYReg_bit w $PHYID 0xB82 23 0 0 0x0 + RT_ERR_CHK(phy_patch_op(pPatchDb, phy_id, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xB82, 23, 0, 0, 0x0, patch_mode), ret); + //PHYReg w $PHYID 0xa43 27 $0x8023 + RT_ERR_CHK(phy_patch_op(pPatchDb, phy_id, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa43, 27, 15, 0, 0x8023, patch_mode), ret); + //PHYReg w $PHYID 0xa43 28 0x0000 + RT_ERR_CHK(phy_patch_op(pPatchDb, phy_id, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa43, 28, 15, 0, 0x0000, patch_mode), ret); + + //PHYReg_bit w $PHYID 0xb82 16 4 4 0x0 + RT_ERR_CHK(phy_patch_op(pPatchDb, phy_id, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xb82, 16, 4, 4, 0x0, patch_mode), ret); + //set patch_rdy [PHYReg_bit r $PHYID 0xb80 16 6 6] ; Wait for patch ready != 1 + RT_ERR_CHK( _phy_rtl826xb_patch_wait_not_equal(phy_id, 31, _phy_rtl826xb_mmd_convert(0xb80, 16), BIT_6, BIT_6, patch_mode), ret); + + return RT_ERR_OK; +} + +static int32_t _phy_rtl826xb_flow_l1(u32 phy_id, u8 portOffset, u8 patch_mode) +{ + int32_t ret = RT_ERR_OK; + rt_phy_patch_db_t *pPatchDb = NULL; + + PHYPATCH_DB_GET(phy_id, pPatchDb); + + //PHYReg_bit w $PHYID 0xa4a 16 10 10 0x1 + RT_ERR_CHK(phy_patch_op(pPatchDb, phy_id, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa4a, 16, 10, 10, 0x1, patch_mode), ret); + //PHYReg_bit w $PHYID 0xa4a 16 10 10 0x1 + RT_ERR_CHK(phy_patch_op(pPatchDb, phy_id, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa4a, 16, 10, 10, 0x1, patch_mode), ret); + + //set pcs_state [PHYReg_bit r $PHYID 0xa60 16 7 0] ; Wait for pcs state = 1 + RT_ERR_CHK( _phy_rtl826xb_patch_wait(phy_id, 31, _phy_rtl826xb_mmd_convert(0xa60, 16), 0x1, 0xFF, patch_mode), ret); + + return RT_ERR_OK; +} + +static int32_t _phy_rtl826xb_flow_l2(u32 phy_id, u8 portOffset, u8 patch_mode) +{ + int32_t ret = RT_ERR_OK; + rt_phy_patch_db_t *pPatchDb = NULL; + + PHYPATCH_DB_GET(phy_id, pPatchDb); + + //PHYReg_bit w $PHYID 0xa4a 16 10 10 0x0 + RT_ERR_CHK(phy_patch_op(pPatchDb, phy_id, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa4a, 16, 10, 10, 0x0, patch_mode), ret); + + //set pcs_state [PHYReg_bit r $PHYID 0xa60 16 7 0] ; Wait for pcs state != 1 + RT_ERR_CHK( _phy_rtl826xb_patch_wait_not_equal(phy_id, 31, _phy_rtl826xb_mmd_convert(0xa60, 16), 0x1, 0xFF, patch_mode), ret); + + return RT_ERR_OK; +} + +static int32_t _phy_rtl826xb_flow_n01(u32 phy_id, u8 portOffset, u8 patch_mode) +{ + int32_t ret = RT_ERR_OK; + rt_phy_patch_db_t *pPatchDb = NULL; + + PHYPATCH_DB_GET(phy_id, pPatchDb); + + //PHYReg_bit w $PHYID 0xa01 21 15 0 0x1 + RT_ERR_CHK(phy_patch_op(pPatchDb, phy_id, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa01, 21, 15, 0, 0x1, patch_mode), ret); + //PHYReg_bit w $PHYID 0xa01 19 15 0 0x0000 + RT_ERR_CHK(phy_patch_op(pPatchDb, phy_id, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa01, 19, 15, 0, 0x0000, patch_mode), ret); + //# PHYReg_bit w $PHYID 0xa01 17 15 0 0x0000 + //RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa01, 17, 15, 0, 0x0000, patch_mode), ret); + + return RT_ERR_OK; +} + +static int32_t _phy_rtl826xb_flow_n02(u32 phy_id, u8 portOffset, u8 patch_mode) +{ + int32_t ret = RT_ERR_OK; + rt_phy_patch_db_t *pPatchDb = NULL; + + PHYPATCH_DB_GET(phy_id, pPatchDb); + + //PHYReg_bit w $PHYID 0xa01 21 15 0 0x0 + RT_ERR_CHK(phy_patch_op(pPatchDb, phy_id, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa01, 21, 15, 0, 0x0, patch_mode), ret); + //PHYReg_bit w $PHYID 0xa01 19 15 0 0x0000 + RT_ERR_CHK(phy_patch_op(pPatchDb, phy_id, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa01, 19, 15, 0, 0x0000, patch_mode), ret); + //PHYReg_bit w $PHYID 0xa01 17 15 0 0x0000 + RT_ERR_CHK(phy_patch_op(pPatchDb, phy_id, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa01, 17, 15, 0, 0x0000, patch_mode), ret); + return RT_ERR_OK; +} + +static int32_t _phy_rtl826xb_flow_n11(u32 phy_id, u8 portOffset, u8 patch_mode) +{ + int32_t ret = RT_ERR_OK; + rt_phy_patch_db_t *pPatchDb = NULL; + + PHYPATCH_DB_GET(phy_id, pPatchDb); + + //PHYReg_bit w $PHYID 0xa01 21 15 0 0x1 + RT_ERR_CHK(phy_patch_op(pPatchDb, phy_id, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa01, 21, 15, 0, 0x1, patch_mode), ret); + //PHYReg_bit w $PHYID 0xa01 19 15 0 0x0010 + RT_ERR_CHK(phy_patch_op(pPatchDb, phy_id, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa01, 19, 15, 0, 0x0010, patch_mode), ret); + //# PHYReg_bit w $PHYID 0xa01 17 15 0 0x0000 + //RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa01, 17, 15, 0, 0x0000, patch_mode), ret); + + return RT_ERR_OK; +} + +static int32_t _phy_rtl826xb_flow_n12(u32 phy_id, u8 portOffset, u8 patch_mode) +{ + int32_t ret = RT_ERR_OK; + rt_phy_patch_db_t *pPatchDb = NULL; + + PHYPATCH_DB_GET(phy_id, pPatchDb); + + //PHYReg_bit w $PHYID 0xa01 21 15 0 0x0 + RT_ERR_CHK(phy_patch_op(pPatchDb, phy_id, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa01, 21, 15, 0, 0x0, patch_mode), ret); + //PHYReg_bit w $PHYID 0xa01 19 15 0 0x0010 + RT_ERR_CHK(phy_patch_op(pPatchDb, phy_id, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa01, 19, 15, 0, 0x0010, patch_mode), ret); + //PHYReg_bit w $PHYID 0xa01 17 15 0 0x0000 + RT_ERR_CHK(phy_patch_op(pPatchDb, phy_id, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa01, 17, 15, 0, 0x0000, patch_mode), ret); + + return RT_ERR_OK; +} + +static int32_t _phy_rtl826xb_flow_n21(u32 phy_id, u8 portOffset, u8 patch_mode) +{ + int32_t ret = RT_ERR_OK; + rt_phy_patch_db_t *pPatchDb = NULL; + + PHYPATCH_DB_GET(phy_id, pPatchDb); + + //PHYReg_bit w $PHYID 0xa01 21 15 0 0x1 + RT_ERR_CHK(phy_patch_op(pPatchDb, phy_id, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa01, 21, 15, 0, 0x1, patch_mode), ret); + //PHYReg_bit w $PHYID 0xa01 19 15 0 0x0020 + RT_ERR_CHK(phy_patch_op(pPatchDb, phy_id, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa01, 19, 15, 0, 0x0020, patch_mode), ret); + //# PHYReg_bit w $PHYID 0xa01 17 15 0 0x0000 + //RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa01, 17, 15, 0, 0x0000, patch_mode), ret); + + return RT_ERR_OK; +} + +static int32_t _phy_rtl826xb_flow_n22(u32 phy_id, u8 portOffset, u8 patch_mode) +{ + int32_t ret = RT_ERR_OK; + rt_phy_patch_db_t *pPatchDb = NULL; + + PHYPATCH_DB_GET(phy_id, pPatchDb); + + //PHYReg_bit w $PHYID 0xa01 21 15 0 0x0 + RT_ERR_CHK(phy_patch_op(pPatchDb, phy_id, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa01, 21, 15, 0, 0x0, patch_mode), ret); + //PHYReg_bit w $PHYID 0xa01 19 15 0 0x0020 + RT_ERR_CHK(phy_patch_op(pPatchDb, phy_id, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa01, 19, 15, 0, 0x0020, patch_mode), ret); + //PHYReg_bit w $PHYID 0xa01 17 15 0 0x0000 + RT_ERR_CHK(phy_patch_op(pPatchDb, phy_id, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa01, 17, 15, 0, 0x0000, patch_mode), ret); + + return RT_ERR_OK; +} + +#define PHYPATCH_IS_RTKSDS(_unit) 0 + +static int32_t _phy_rtl826xb_flow_s(u32 phy_id, u8 portOffset, u8 patch_mode) +{ + int32_t ret = RT_ERR_OK; + rt_phy_patch_db_t *pPatchDb = NULL; + + if (PHYPATCH_IS_RTKSDS(phy_id)) + { + PHYPATCH_DB_GET(phy_id, pPatchDb); + + RT_ERR_CHK(phy_patch_op(pPatchDb, phy_id, portOffset, RTK_PATCH_OP_PSDS0, 0xff, 0x07, 0x10, 15, 0, 0x80aa, patch_mode), ret); + RT_ERR_CHK(phy_patch_op(pPatchDb, phy_id, portOffset, RTK_PATCH_OP_PSDS0, 0xff, 0x06, 0x12, 15, 0, 0x5078, patch_mode), ret); + } + + return RT_ERR_OK; +} + +static int32_t _phy_rtl826xb_flow_pi(u32 phy_id, u8 portOffset, u8 patch_mode) +{ + int32_t ret = RT_ERR_OK; + rt_phy_patch_db_t *pPatchDb = NULL; + uint32_t rData = 0, cnt = 0; + + PHYPATCH_DB_GET(phy_id, pPatchDb); + + _phy_rtl826xb_flow_l1(phy_id, portOffset, patch_mode); + + // PP_PHYReg_bit w $PHYID 0xbf86 9 9 0x1; #SS_EN_XG = 1 + RT_ERR_CHK(phy_patch_op(pPatchDb, phy_id, portOffset, RTK_PATCH_OP_PHYOCP, 0xFF, 31, 0xbf86, 9, 9, 0x1, patch_mode), ret); + // PP_PHYReg_bit w $PHYID 0xbf86 8 8 0x0; + RT_ERR_CHK(phy_patch_op(pPatchDb, phy_id, portOffset, RTK_PATCH_OP_PHYOCP, 0xFF, 31, 0xbf86, 8, 8, 0x0, patch_mode), ret); + // PP_PHYReg_bit w $PHYID 0xbf86 7 7 0x1; + RT_ERR_CHK(phy_patch_op(pPatchDb, phy_id, portOffset, RTK_PATCH_OP_PHYOCP, 0xFF, 31, 0xbf86, 7, 7, 0x1, patch_mode), ret); + // PP_PHYReg_bit w $PHYID 0xbf86 6 6 0x1; + RT_ERR_CHK(phy_patch_op(pPatchDb, phy_id, portOffset, RTK_PATCH_OP_PHYOCP, 0xFF, 31, 0xbf86, 6, 6, 0x1, patch_mode), ret); + // PP_PHYReg_bit w $PHYID 0xbf86 5 5 0x1; + RT_ERR_CHK(phy_patch_op(pPatchDb, phy_id, portOffset, RTK_PATCH_OP_PHYOCP, 0xFF, 31, 0xbf86, 5, 5, 0x1, patch_mode), ret); + // PP_PHYReg_bit w $PHYID 0xbf86 4 4 0x1; + RT_ERR_CHK(phy_patch_op(pPatchDb, phy_id, portOffset, RTK_PATCH_OP_PHYOCP, 0xFF, 31, 0xbf86, 4, 4, 0x1, patch_mode), ret); + // PP_PHYReg_bit w $PHYID 0xbf86 6 6 0x0; + RT_ERR_CHK(phy_patch_op(pPatchDb, phy_id, portOffset, RTK_PATCH_OP_PHYOCP, 0xFF, 31, 0xbf86, 6, 6, 0x0, patch_mode), ret); + // PP_PHYReg_bit w $PHYID 0xbf86 9 9 0x0; + RT_ERR_CHK(phy_patch_op(pPatchDb, phy_id, portOffset, RTK_PATCH_OP_PHYOCP, 0xFF, 31, 0xbf86, 9, 9, 0x0, patch_mode), ret); + // PP_PHYReg_bit w $PHYID 0xbf86 7 7 0x0; + RT_ERR_CHK(phy_patch_op(pPatchDb, phy_id, portOffset, RTK_PATCH_OP_PHYOCP, 0xFF, 31, 0xbf86, 7, 7, 0x0, patch_mode), ret); + + //PP_PHYReg_bit r $PHYID 0xbc62 12 8 + if ((ret = phy_common_general_reg_mmd_get(phy_id, PHY_MMD_VEND2, 0xbc62, &rData)) != RT_ERR_OK) + return ret; + rData = REG32_FIELD_GET(rData, 8, 0x1F00); + for (cnt = 0; cnt <= rData; cnt++) + { + //PP_PHYReg_bit w $PHYID 0xbc62 12 8 $t + RT_ERR_CHK(phy_patch_op(pPatchDb, phy_id, portOffset, RTK_PATCH_OP_PHYOCP, 0xFF, 31, 0xbc62, 12, 8, cnt, patch_mode), ret); + } + + // PP_PHYReg_bit w $PHYID 0xbc02 2 2 0x1 + RT_ERR_CHK(phy_patch_op(pPatchDb, phy_id, portOffset, RTK_PATCH_OP_PHYOCP, 0xFF, 31, 0xbc02, 2, 2, 0x1, patch_mode), ret); + // PP_PHYReg_bit w $PHYID 0xbc02 3 3 0x1 + RT_ERR_CHK(phy_patch_op(pPatchDb, phy_id, portOffset, RTK_PATCH_OP_PHYOCP, 0xFF, 31, 0xbc02, 3, 3, 0x1, patch_mode), ret); + // PP_PHYReg_bit w $PHYID 0xbf86 6 6 0x1 + RT_ERR_CHK(phy_patch_op(pPatchDb, phy_id, portOffset, RTK_PATCH_OP_PHYOCP, 0xFF, 31, 0xbf86, 6, 6, 0x1, patch_mode), ret); + // PP_PHYReg_bit w $PHYID 0xbf86 9 9 0x1 + RT_ERR_CHK(phy_patch_op(pPatchDb, phy_id, portOffset, RTK_PATCH_OP_PHYOCP, 0xFF, 31, 0xbf86, 9, 9, 0x1, patch_mode), ret); + // PP_PHYReg_bit w $PHYID 0xbf86 7 7 0x1 + RT_ERR_CHK(phy_patch_op(pPatchDb, phy_id, portOffset, RTK_PATCH_OP_PHYOCP, 0xFF, 31, 0xbf86, 7, 7, 0x1, patch_mode), ret); + // PP_PHYReg_bit w $PHYID 0xbc04 9 2 0xff + RT_ERR_CHK(phy_patch_op(pPatchDb, phy_id, portOffset, RTK_PATCH_OP_PHYOCP, 0xFF, 31, 0xbc04, 9, 2, 0xff, patch_mode), ret); + + _phy_rtl826xb_flow_l2(phy_id, portOffset, patch_mode); + return RT_ERR_OK; +} + +static int32_t _phy_rtl826xb_flow_cmpstart(u32 phy_id, u8 portOffset, u8 patch_mode) +{ + int32_t ret = RT_ERR_OK; + rt_phy_patch_db_t *pPatchDb = NULL; + + PHYPATCH_DB_GET(phy_id, pPatchDb); + RT_ERR_CHK(phy_patch_op(pPatchDb, phy_id, portOffset, RTK_PATCH_OP_PHYOCP, 0xFF, 1, 0, 11, 11, 0x0, patch_mode), ret); + return RT_ERR_OK; +} + +static int32_t _phy_rtl826xb_flow_cmpend(u32 phy_id, u8 portOffset, u8 patch_mode) +{ + int32_t ret = RT_ERR_OK; + rt_phy_patch_db_t *pPatchDb = NULL; + + PHYPATCH_DB_GET(phy_id, pPatchDb); + RT_ERR_CHK(phy_patch_op(pPatchDb, phy_id, portOffset, RTK_PATCH_OP_PHYOCP, 0xFF, 1, 0, 11, 11, 0x1, patch_mode), ret); + return RT_ERR_OK; +} + +int32_t phy_rtl826xb_patch_flow(u32 phy_id, u8 portOffset, u8 patch_flow, u8 patch_mode) +{ + int32_t ret = RT_ERR_OK; + + RT_LOG(LOG_INFO, (MOD_HAL | MOD_PHY), "flow%u\n", __FUNCTION__, (patch_flow - PHY_PATCH_TYPE_END)); + switch (patch_flow) + { + case RTK_PATCH_TYPE_FLOW(0): + RT_ERR_CHK(_phy_rtl826xb_flow_r1(phy_id, portOffset, patch_mode), ret); + break; + case RTK_PATCH_TYPE_FLOW(1): + RT_ERR_CHK(_phy_rtl826xb_flow_r2(phy_id, portOffset, patch_mode), ret); + break; + + case RTK_PATCH_TYPE_FLOW(2): + RT_ERR_CHK(_phy_rtl826xb_flow_l1(phy_id, portOffset, patch_mode), ret); + break; + case RTK_PATCH_TYPE_FLOW(3): + RT_ERR_CHK(_phy_rtl826xb_flow_l2(phy_id, portOffset, patch_mode), ret); + break; + + case RTK_PATCH_TYPE_FLOW(4): + RT_ERR_CHK(_phy_rtl826xb_flow_n01(phy_id, portOffset, patch_mode), ret); + break; + case RTK_PATCH_TYPE_FLOW(5): + RT_ERR_CHK(_phy_rtl826xb_flow_n02(phy_id, portOffset, patch_mode), ret); + break; + + case RTK_PATCH_TYPE_FLOW(6): + RT_ERR_CHK(_phy_rtl826xb_flow_n11(phy_id, portOffset, patch_mode), ret); + break; + case RTK_PATCH_TYPE_FLOW(7): + RT_ERR_CHK(_phy_rtl826xb_flow_n12(phy_id, portOffset, patch_mode), ret); + break; + + case RTK_PATCH_TYPE_FLOW(8): + RT_ERR_CHK(_phy_rtl826xb_flow_n21(phy_id, portOffset, patch_mode), ret); + break; + case RTK_PATCH_TYPE_FLOW(9): + RT_ERR_CHK(_phy_rtl826xb_flow_n22(phy_id, portOffset, patch_mode), ret); + break; + + case RTK_PATCH_TYPE_FLOW(10): + RT_ERR_CHK(_phy_rtl826xb_flow_s(phy_id, portOffset, patch_mode), ret); + break; + + case RTK_PATCH_TYPE_FLOW(11): + RT_ERR_CHK(_phy_rtl826xb_flow_pi(phy_id, portOffset, patch_mode), ret); + break; + case RTK_PATCH_TYPE_FLOW(12): + RT_ERR_CHK(_phy_rtl826xb_flow_r12(phy_id, portOffset, patch_mode), ret); + break; + + case RTK_PATCH_TYPE_FLOW(13): + RT_ERR_CHK(_phy_rtl826xb_flow_cmpstart(phy_id, portOffset, patch_mode), ret); + break; + case RTK_PATCH_TYPE_FLOW(14): + RT_ERR_CHK(_phy_rtl826xb_flow_cmpend(phy_id, portOffset, patch_mode), ret); + break; + + default: + return RT_ERR_INPUT; + } + return RT_ERR_OK; +} + +int32_t phy_rtl826xb_patch_db_init(u32 phy_id, rt_phy_patch_db_t **pPhy_patchDb) +{ + int32_t ret = 0; + rt_phy_patch_db_t *patch_db = NULL; + u32 rData = 0; + + patch_db = (rt_phy_patch_db_t *)malloc(sizeof(rt_phy_patch_db_t)); + RT_PARAM_CHK(NULL == patch_db, RT_ERR_MEM_ALLOC); + memset(patch_db, 0x0, sizeof(rt_phy_patch_db_t)); + + /* patch callback */ + patch_db->fPatch_op = phy_rtl826xb_patch_op; + patch_db->fPatch_flow = phy_rtl826xb_patch_flow; + + /* patch table */ + RT_ERR_CHK(phy_common_general_reg_mmd_get(phy_id, 30, 0x104, &rData), ret); + if ((rData & 0xFFC0) == 0x1140) /* RTL8261BE */ + { + printf("patch db RTL8261BE\n"); + /* patch */ + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 0, RTK_PATCH_TYPE_FLOW(0), NULL); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 1, PHY_PATCH_TYPE_NCTL0, rtl8261n_c_nctl0_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 2, PHY_PATCH_TYPE_NCTL1, rtl8261n_c_nctl1_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 3, PHY_PATCH_TYPE_NCTL2, rtl8261n_c_nctl2_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 4, PHY_PATCH_TYPE_UC2, rtl8261n_c_uc2_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 5, PHY_PATCH_TYPE_UC, rtl8261n_c_uc_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 6, PHY_PATCH_TYPE_DATARAM, rtl8261n_c_dataram_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 7, RTK_PATCH_TYPE_FLOW(1), NULL); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 8, RTK_PATCH_TYPE_FLOW(2), NULL); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 9, PHY_PATCH_TYPE_ALGXG, rtl8261n_c_algxg_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 10, PHY_PATCH_TYPE_ALG1G, rtl8261n_c_alg_giga_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 11, PHY_PATCH_TYPE_NORMAL, rtl8261n_c_normal_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 12, PHY_PATCH_TYPE_TOP, rtl8261n_c_top_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 13, PHY_PATCH_TYPE_SDS, rtl8261n_c_sds_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 14, PHY_PATCH_TYPE_AFE, rtl8261n_c_afe_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 15, PHY_PATCH_TYPE_RTCT, rtl8261n_c_rtct_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 16, RTK_PATCH_TYPE_FLOW(3), NULL); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 17, RTK_PATCH_TYPE_FLOW(10), NULL); + + /* compare */ + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 0, RTK_PATCH_TYPE_FLOW(13), NULL); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 1, PHY_PATCH_TYPE_TOP, rtl8261n_c_top_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 2, PHY_PATCH_TYPE_SDS, rtl8261n_c_sds_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 3, PHY_PATCH_TYPE_AFE, rtl8261n_c_afe_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 4, RTK_PATCH_TYPE_FLOW(4), NULL); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 5, PHY_PATCH_TYPE_NCTL0, rtl8261n_c_nctl0_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 6, RTK_PATCH_TYPE_FLOW(5), NULL); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 7, RTK_PATCH_TYPE_FLOW(6), NULL); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 8, PHY_PATCH_TYPE_NCTL1, rtl8261n_c_nctl1_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 9, RTK_PATCH_TYPE_FLOW(7), NULL); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 10, RTK_PATCH_TYPE_FLOW(8), NULL); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 11, PHY_PATCH_TYPE_NCTL2, rtl8261n_c_nctl2_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 12, RTK_PATCH_TYPE_FLOW(9), NULL); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 13, PHY_PATCH_TYPE_UC, rtl8261n_c_uc_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 14, PHY_PATCH_TYPE_UC2, rtl8261n_c_uc2_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 15, RTK_PATCH_TYPE_FLOW(0), NULL); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 16, PHY_PATCH_TYPE_DATARAM, rtl8261n_c_dataram_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 17, RTK_PATCH_TYPE_FLOW(1), NULL); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 18, PHY_PATCH_TYPE_ALGXG, rtl8261n_c_algxg_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 19, PHY_PATCH_TYPE_ALG1G, rtl8261n_c_alg_giga_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 20, PHY_PATCH_TYPE_NORMAL, rtl8261n_c_normal_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 21, PHY_PATCH_TYPE_RTCT, rtl8261n_c_rtct_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 22, RTK_PATCH_TYPE_FLOW(14), NULL); + } + else if ((rData & 0xF) == 0x0) + { + /* patch */ + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 0, RTK_PATCH_TYPE_FLOW(12), NULL); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 1, PHY_PATCH_TYPE_NCTL0, rtl8264b_nctl0_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 2, PHY_PATCH_TYPE_NCTL1, rtl8264b_nctl1_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 3, PHY_PATCH_TYPE_NCTL2, rtl8264b_nctl2_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 4, PHY_PATCH_TYPE_UC2, rtl8264b_uc2_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 5, PHY_PATCH_TYPE_UC, rtl8264b_uc_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 6, PHY_PATCH_TYPE_DATARAM, rtl8264b_dataram_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 7, RTK_PATCH_TYPE_FLOW(1), NULL); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 8, RTK_PATCH_TYPE_FLOW(2), NULL); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 9, PHY_PATCH_TYPE_ALGXG, rtl8264b_algxg_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 10, PHY_PATCH_TYPE_ALG1G, rtl8264b_alg_giga_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 11, PHY_PATCH_TYPE_NORMAL, rtl8264b_normal_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 12, PHY_PATCH_TYPE_TOP, rtl8264b_top_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 13, PHY_PATCH_TYPE_SDS, rtl8264b_sds_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 14, PHY_PATCH_TYPE_AFE, rtl8264b_afe_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 15, PHY_PATCH_TYPE_RTCT, rtl8264b_rtct_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 16, RTK_PATCH_TYPE_FLOW(3), NULL); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 17, RTK_PATCH_TYPE_FLOW(11), NULL); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 18, RTK_PATCH_TYPE_FLOW(10), NULL); + + /* compare */ + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 0, RTK_PATCH_TYPE_FLOW(13), NULL); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 1, PHY_PATCH_TYPE_TOP, rtl8264b_top_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 2, PHY_PATCH_TYPE_SDS, rtl8264b_sds_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 3, PHY_PATCH_TYPE_AFE, rtl8264b_afe_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 4, RTK_PATCH_TYPE_FLOW(4), NULL); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 5, PHY_PATCH_TYPE_NCTL0, rtl8264b_nctl0_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 6, RTK_PATCH_TYPE_FLOW(5), NULL); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 7, RTK_PATCH_TYPE_FLOW(6), NULL); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 8, PHY_PATCH_TYPE_NCTL1, rtl8264b_nctl1_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 9, RTK_PATCH_TYPE_FLOW(7), NULL); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 10, RTK_PATCH_TYPE_FLOW(8), NULL); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 11, PHY_PATCH_TYPE_NCTL2, rtl8264b_nctl2_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 12, RTK_PATCH_TYPE_FLOW(9), NULL); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 13, PHY_PATCH_TYPE_UC, rtl8264b_uc_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 14, PHY_PATCH_TYPE_UC2, rtl8264b_uc2_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 15, RTK_PATCH_TYPE_FLOW(12), NULL); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 16, PHY_PATCH_TYPE_DATARAM, rtl8264b_dataram_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 17, RTK_PATCH_TYPE_FLOW(1), NULL); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 18, PHY_PATCH_TYPE_ALGXG, rtl8264b_algxg_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 19, PHY_PATCH_TYPE_ALG1G, rtl8264b_alg_giga_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 20, PHY_PATCH_TYPE_NORMAL, rtl8264b_normal_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 21, PHY_PATCH_TYPE_RTCT, rtl8264b_rtct_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 22, RTK_PATCH_TYPE_FLOW(14), NULL); + } + else + { + /* patch */ + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 0, RTK_PATCH_TYPE_FLOW(0), NULL); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 1, PHY_PATCH_TYPE_NCTL0, rtl8261n_c_nctl0_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 2, PHY_PATCH_TYPE_NCTL1, rtl8261n_c_nctl1_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 3, PHY_PATCH_TYPE_NCTL2, rtl8261n_c_nctl2_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 4, PHY_PATCH_TYPE_UC2, rtl8261n_c_uc2_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 5, PHY_PATCH_TYPE_UC, rtl8261n_c_uc_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 6, PHY_PATCH_TYPE_DATARAM, rtl8261n_c_dataram_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 7, RTK_PATCH_TYPE_FLOW(1), NULL); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 8, RTK_PATCH_TYPE_FLOW(2), NULL); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 9, PHY_PATCH_TYPE_ALGXG, rtl8261n_c_algxg_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 10, PHY_PATCH_TYPE_ALG1G, rtl8261n_c_alg_giga_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 11, PHY_PATCH_TYPE_NORMAL, rtl8261n_c_normal_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 12, PHY_PATCH_TYPE_TOP, rtl8261n_c_top_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 13, PHY_PATCH_TYPE_SDS, rtl8261n_c_sds_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 14, PHY_PATCH_TYPE_AFE, rtl8261n_c_afe_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 15, PHY_PATCH_TYPE_RTCT, rtl8261n_c_rtct_conf); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 16, RTK_PATCH_TYPE_FLOW(3), NULL); + PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 17, RTK_PATCH_TYPE_FLOW(10), NULL); + + /* compare */ + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 0, RTK_PATCH_TYPE_FLOW(13), NULL); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 1, PHY_PATCH_TYPE_TOP, rtl8261n_c_top_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 2, PHY_PATCH_TYPE_SDS, rtl8261n_c_sds_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 3, PHY_PATCH_TYPE_AFE, rtl8261n_c_afe_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 4, RTK_PATCH_TYPE_FLOW(4), NULL); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 5, PHY_PATCH_TYPE_NCTL0, rtl8261n_c_nctl0_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 6, RTK_PATCH_TYPE_FLOW(5), NULL); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 7, RTK_PATCH_TYPE_FLOW(6), NULL); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 8, PHY_PATCH_TYPE_NCTL1, rtl8261n_c_nctl1_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 9, RTK_PATCH_TYPE_FLOW(7), NULL); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 10, RTK_PATCH_TYPE_FLOW(8), NULL); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 11, PHY_PATCH_TYPE_NCTL2, rtl8261n_c_nctl2_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 12, RTK_PATCH_TYPE_FLOW(9), NULL); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 13, PHY_PATCH_TYPE_UC, rtl8261n_c_uc_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 14, PHY_PATCH_TYPE_UC2, rtl8261n_c_uc2_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 15, RTK_PATCH_TYPE_FLOW(0), NULL); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 16, PHY_PATCH_TYPE_DATARAM, rtl8261n_c_dataram_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 17, RTK_PATCH_TYPE_FLOW(1), NULL); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 18, PHY_PATCH_TYPE_ALGXG, rtl8261n_c_algxg_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 19, PHY_PATCH_TYPE_ALG1G, rtl8261n_c_alg_giga_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 20, PHY_PATCH_TYPE_NORMAL, rtl8261n_c_normal_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 21, PHY_PATCH_TYPE_RTCT, rtl8261n_c_rtct_conf); + PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 22, RTK_PATCH_TYPE_FLOW(14), NULL); + } + *pPhy_patchDb = patch_db; + printf ("patch_db address: 0x%p\n", patch_db); + return ret; +} + +static int32 _phy_patch_process(uint32 phy_id, uint8 portOffset, rtk_hwpatch_t *pPatch, int32 size, uint8 patch_mode) +{ + int32 i = 0; + int32 ret = 0; + int32 chk_ret = RT_ERR_OK; + int32 n; + rtk_hwpatch_t *patch = pPatch; + rt_phy_patch_db_t *pPatchDb = NULL; + + PHYPATCH_DB_GET(phy_id, pPatchDb); + + if (size <= 0) + { + return RT_ERR_OK; + } + n = size / sizeof(rtk_hwpatch_t); + + for (i = 0; i < n; i++) + { + ret = pPatchDb->fPatch_op(phy_id, portOffset, &patch[i], patch_mode); + if ((ret != RT_ERR_ABORT) && (ret != RT_ERR_OK)) + { + if ((ret == RT_ERR_CHECK_FAILED) && (patch_mode == PHY_PATCH_MODE_CMP)) + { + printf("PATCH CHECK: Failed entry:%u|%u|0x%X|0x%X|%u|%u|0x%X\n", + i + 1, patch[i].patch_op, patch[i].pagemmd, patch[i].addr, patch[i].msb, patch[i].lsb, patch[i].data); + chk_ret = RT_ERR_CHECK_FAILED; + continue; + } + else + { + printf("P%u %s failed! %u[%u][0x%X][0x%X][0x%X] ret=0x%X\n", phy_id, __FUNCTION__, + i+1, patch[i].patch_op, patch[i].pagemmd, patch[i].addr, patch[i].data, ret); + return ret; + } + } + + } + return (chk_ret == RT_ERR_CHECK_FAILED) ? chk_ret : RT_ERR_OK; +} + +int32 phy_patch(uint32 phy_id, uint8 portOffset, uint8 patch_mode) +{ + int32 ret = RT_ERR_OK; + int32 chk_ret = RT_ERR_OK; + uint32 i = 0; + uint8 patch_type = 0; + rt_phy_patch_db_t *pPatchDb = NULL; + rtk_hwpatch_seq_t *table = NULL; + + PHYPATCH_DB_GET(phy_id, pPatchDb); + + if ((pPatchDb == NULL) || (pPatchDb->fPatch_op == NULL) || (pPatchDb->fPatch_flow == NULL)) + { + printf("phy_patch, db is NULL\n"); + return RT_ERR_DRIVER_NOT_SUPPORTED; + } + + if (patch_mode == PHY_PATCH_MODE_CMP) + { + table = pPatchDb->cmp_table; + } + else + { + table = pPatchDb->seq_table; + } + // printf("phy_patch: portOffset:%u patch_mode:%u\n", portOffset, patch_mode); + + for (i = 0; i < RTK_PATCH_SEQ_MAX; i++) + { + patch_type = table[i].patch_type; + //printf("phy_patch: table[%u] patch_type:%u\n", i, patch_type); + + if (RTK_PATCH_TYPE_IS_DATA(patch_type)) + { + ret = _phy_patch_process(phy_id, portOffset, table[i].patch.data.conf, table[i].patch.data.size, patch_mode); + + if (ret == RT_ERR_CHECK_FAILED) + { + printf("RT_ERR_CHECK_FAILED\n"); + chk_ret = ret; + } + else if (ret != RT_ERR_OK) + { + printf("patch_mode:%u id:%u patch-%u failed. ret:0x%X\n", patch_mode, i, patch_type, ret); + return ret; + } + } + else if (RTK_PATCH_TYPE_IS_FLOW(patch_type)) + { + RT_ERR_CHK_EHDL(pPatchDb->fPatch_flow(phy_id, portOffset, table[i].patch.flow_id, patch_mode), + ret, printf("patch_mode:%u id:%u patch-%u failed. ret:0x%X\n", patch_mode, i, patch_type, ret);); + } + else + { + printf("patch type is not supported\n"); + break; + } + } + + return (chk_ret == RT_ERR_CHECK_FAILED) ? chk_ret : RT_ERR_OK; +} + diff --git a/sources/uboot-be550/drivers/net/ipq_common/rtl8261_patch.h b/sources/uboot-be550/drivers/net/ipq_common/rtl8261_patch.h new file mode 100644 index 00000000..84f00f58 --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq_common/rtl8261_patch.h @@ -0,0 +1,86 @@ +#ifndef _RTL8261_PATCH_H_ +#define _RTL8261_PATCH_H_ + +#include "rtl8261_phy.h" + +#define PHYPATCH_PHYCTRL_IN_HALCTRL 0 /* 3.6.x: 1 ,4.0.x: 1, 4.1.x+: 0 */ +#define PHYPATCH_FMAILY_IN_HWP 0 /* 3.6.x: 1 ,4.0.x: 0, 4.1.x+: 0 */ +#define PHY_PATCH_MODE_BCAST_DEFAULT PHY_PATCH_MODE_BCAST /* 3.6.x: PHY_PATCH_MODE_BCAST_BUS ,4.0.x+: PHY_PATCH_MODE_BCAST */ + +#define PHY_PATCH_MODE_NORMAL 0 +#define PHY_PATCH_MODE_CMP 1 +#define PHY_PATCH_MODE_BCAST 2 +#define PHY_PATCH_MODE_BCAST_BUS 3 + +#define RTK_PATCH_CMP_W 0 /* write */ +#define RTK_PATCH_CMP_WC 1 /* compare */ +#define RTK_PATCH_CMP_SWC 2 /* sram compare */ +#define RTK_PATCH_CMP_WS 3 /* skip */ + +#define RTK_PATCH_OP_SECTION_SIZE 50 +#define RTK_PATCH_OP_TO_CMP(_op, _cmp) (_op + (RTK_PATCH_OP_SECTION_SIZE * _cmp)) + +#define RTK_PATCH_OP_PHY 0 +#define RTK_PATCH_OP_PHYOCP 1 +#define RTK_PATCH_OP_TOP 2 +#define RTK_PATCH_OP_TOPOCP 3 +#define RTK_PATCH_OP_PSDS0 4 +#define RTK_PATCH_OP_PSDS1 5 +#define RTK_PATCH_OP_MSDS 6 +#define RTK_PATCH_OP_MAC 7 + +/* 50~99 normal op for compare */ +#define RTK_PATCH_OP_CMP_PHY RTK_PATCH_OP_TO_CMP(RTK_PATCH_OP_PHY , RTK_PATCH_CMP_WC) +#define RTK_PATCH_OP_CMP_PHYOCP RTK_PATCH_OP_TO_CMP(RTK_PATCH_OP_PHYOCP , RTK_PATCH_CMP_WC) +#define RTK_PATCH_OP_CMP_TOP RTK_PATCH_OP_TO_CMP(RTK_PATCH_OP_TOP , RTK_PATCH_CMP_WC) +#define RTK_PATCH_OP_CMP_TOPOCP RTK_PATCH_OP_TO_CMP(RTK_PATCH_OP_TOPOCP , RTK_PATCH_CMP_WC) +#define RTK_PATCH_OP_CMP_PSDS0 RTK_PATCH_OP_TO_CMP(RTK_PATCH_OP_PSDS0 , RTK_PATCH_CMP_WC) +#define RTK_PATCH_OP_CMP_PSDS1 RTK_PATCH_OP_TO_CMP(RTK_PATCH_OP_PSDS1 , RTK_PATCH_CMP_WC) +#define RTK_PATCH_OP_CMP_MSDS RTK_PATCH_OP_TO_CMP(RTK_PATCH_OP_MSDS , RTK_PATCH_CMP_WC) +#define RTK_PATCH_OP_CMP_MAC RTK_PATCH_OP_TO_CMP(RTK_PATCH_OP_MAC , RTK_PATCH_CMP_WC) + +/* 100~149 normal op for sram compare */ +#define RTK_PATCH_OP_CMP_SRAM_PHY RTK_PATCH_OP_TO_CMP(RTK_PATCH_OP_PHY , RTK_PATCH_CMP_SWC) +#define RTK_PATCH_OP_CMP_SRAM_PHYOCP RTK_PATCH_OP_TO_CMP(RTK_PATCH_OP_PHYOCP , RTK_PATCH_CMP_SWC) +#define RTK_PATCH_OP_CMP_SRAM_TOP RTK_PATCH_OP_TO_CMP(RTK_PATCH_OP_TOP , RTK_PATCH_CMP_SWC) +#define RTK_PATCH_OP_CMP_SRAM_TOPOCP RTK_PATCH_OP_TO_CMP(RTK_PATCH_OP_TOPOCP , RTK_PATCH_CMP_SWC) +#define RTK_PATCH_OP_CMP_SRAM_PSDS0 RTK_PATCH_OP_TO_CMP(RTK_PATCH_OP_PSDS0 , RTK_PATCH_CMP_SWC) +#define RTK_PATCH_OP_CMP_SRAM_PSDS1 RTK_PATCH_OP_TO_CMP(RTK_PATCH_OP_PSDS1 , RTK_PATCH_CMP_SWC) +#define RTK_PATCH_OP_CMP_SRAM_MSDS RTK_PATCH_OP_TO_CMP(RTK_PATCH_OP_MSDS , RTK_PATCH_CMP_SWC) +#define RTK_PATCH_OP_CMP_SRAM_MAC RTK_PATCH_OP_TO_CMP(RTK_PATCH_OP_MAC , RTK_PATCH_CMP_SWC) + +#define RTK_PATCH_OP_DELAY_MS 200 +#define RTK_PATCH_OP_SKIP 255 + +#define RTK_PATCH_TYPE_IS_DATA(_patch_type) (_patch_type > PHY_PATCH_TYPE_NONE && _patch_type < PHY_PATCH_TYPE_END) +#define RTK_PATCH_TYPE_IS_FLOW(_patch_type) (_patch_type >= PHY_PATCH_TYPE_END && _patch_type <= (PHY_PATCH_TYPE_END + RTK_PATCH_TYPE_FLOWID_MAX)) + +#define PHYPATCH_TABLE_ASSIGN(_pPatchDb, _table, _idx, _patch_type, _para) \ + do {\ + if (RTK_PATCH_TYPE_IS_DATA(_patch_type)) {\ + _pPatchDb->_table[_idx].patch_type = _patch_type;\ + _pPatchDb->_table[_idx].patch.data.conf = _para;\ + _pPatchDb->_table[_idx].patch.data.size = sizeof(_para);\ + }\ + else if (RTK_PATCH_TYPE_IS_FLOW(_patch_type)) {\ + _pPatchDb->_table[_idx].patch_type = _patch_type;\ + _pPatchDb->_table[_idx].patch.flow_id = _patch_type;\ + }\ + else {\ + _pPatchDb->_table[_idx].patch_type = PHY_PATCH_TYPE_NONE;\ + }\ + } while(0) +#define PHYPATCH_SEQ_TABLE_ASSIGN(_pPatchDb, _idx, _patch_type, _para) PHYPATCH_TABLE_ASSIGN(_pPatchDb, seq_table, _idx, _patch_type, _para) +#define PHYPATCH_CMP_TABLE_ASSIGN(_pPatchDb, _idx, _patch_type, _para) PHYPATCH_TABLE_ASSIGN(_pPatchDb, cmp_table, _idx, _patch_type, _para) + +#define PHYPATCH_COMPARE(_mmdpage, _reg, _msb, _lsb, _exp, _real, _mask) \ + do {\ + uint32 _rData = REG32_FIELD_GET(_real, _lsb, _mask);\ + if (_exp != _rData) {\ + printf("PATCH CHECK: %u(0x%X).%u(0x%X)[%u:%u] = 0x%X (!= 0x%X)\n", _mmdpage, _mmdpage, _reg, _reg, _msb, _lsb, _rData, _exp);\ + return RT_ERR_CHECK_FAILED;\ + }\ + } while (0) + +#endif /* _RTL8261_PATCH_H_ */ + diff --git a/sources/uboot-be550/drivers/net/ipq_common/rtl8261_phy.c b/sources/uboot-be550/drivers/net/ipq_common/rtl8261_phy.c new file mode 100644 index 00000000..564375d1 --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq_common/rtl8261_phy.c @@ -0,0 +1,435 @@ +#include +#include +#include +#include +#include +#include +#include "rtl8261_phy.h" +#include "ipq_phy.h" + +extern int ipq_mdio_read(int mii_id, + int regnum, ushort *data); +extern int ipq_mdio_write(int mii_id, + int regnum, u16 data); + +u16 rtl8261_phy_reg_read(u32 dev_id, u32 phy_id, u32 reg_id) +{ + return ipq_mdio_read(phy_id, reg_id, NULL); +} + +u16 rtl8261_phy_reg_write(u32 dev_id, u32 phy_id, u32 reg_id, u16 value) +{ + return ipq_mdio_write(phy_id, reg_id, value); +} + +u8 rtl8261_phy_get_link_status(u32 dev_id, u32 phy_id) +{ + u16 phy_data; + phy_data = rtl8261_phy_reg_read(dev_id, phy_id, + RTL8261_REG_ADDRESS(RTL8261_MMD_AUTONEG, RTL8261_MMD_AN_STAT)); + phy_data = rtl8261_phy_reg_read(dev_id, phy_id, + RTL8261_REG_ADDRESS(RTL8261_MMD_AUTONEG, RTL8261_MMD_AN_STAT)); + + if (((phy_data >> 2) & 0x1) & PORT_LINK_UP) + return 0; + + + return 1; +} + +u32 rtl8261_phy_get_duplex(u32 dev_id, u32 phy_id, fal_port_duplex_t *duplex) +{ + + u16 phy_data = rtl8261_phy_reg_read(dev_id, phy_id, RTL8261_REG_ADDRESS(0x1f, 0xa434)); + *duplex = (phy_data & BIT_3) ? (FAL_FULL_DUPLEX) : (FAL_HALF_DUPLEX); + + return 0; +} + +u32 rtl8261_phy_get_speed(u32 dev_id, u32 phy_id, fal_port_speed_t *speed) +{ + uint32_t rData = 0; + + rData = rtl8261_phy_reg_read(0, phy_id, RTL8261_REG_ADDRESS(0x1F, 0xa434)); + switch (rData & SPEED_MASK) + { + case SPEED_10M: + *speed = FAL_SPEED_10; + break; + case SPEED_100M: + *speed = FAL_SPEED_100; + break; + case SPEED_1000M: + *speed = FAL_SPEED_1000; + break; + case SPEED_2500M: + *speed = FAL_SPEED_2500; + break; + case SPEED_5000M: + *speed = FAL_SPEED_5000; + break; + case SPEED_10000M: + *speed = FAL_SPEED_10000; + break; + default: + *speed = FAL_SPEED_10; + break; + } + return 0; +} + + +int32_t rtk_phylib_mmd_read(u32 phy_id, uint32_t mmd, uint32_t reg, uint8_t msb, uint8_t lsb, uint32_t *pData) +{ + int32_t ret = 0; + uint32_t rData = 0; + uint32_t mask = 0; + mask = UINT32_BITS_MASK(msb,lsb); + +// rData = phy_read_mmd(phydev, mmd, reg); + + rData = rtl8261_phy_reg_read(0, phy_id, RTL8261_REG_ADDRESS(mmd, reg)); + + *pData = REG32_FIELD_GET(rData, lsb, mask); + return ret; +} + +int32_t rtk_phylib_mmd_write(u32 phy_id, uint32_t mmd, uint32_t reg, uint8_t msb, uint8_t lsb, uint32_t data) +{ + int32_t ret = 0; + uint32_t mask = 0; + mask = UINT32_BITS_MASK(msb,lsb); + + uint32_t rData = 0, wData = 0; + +// phy_modify_mmd(phydev, mmd, reg, mask, (data << lsb)); + if ((msb != 15) || (lsb != 0)) + { + rData = rtl8261_phy_reg_read(0, phy_id, RTL8261_REG_ADDRESS(mmd, reg)); + } + + wData = REG32_FIELD_SET(rData, data, lsb, mask); + + rtl8261_phy_reg_write(0, phy_id, RTL8261_REG_ADDRESS(mmd, reg), wData); + + return ret; +} + +/* Indirect Register Access APIs */ +int rtk_phylib_826xb_sds_read(u32 phy_id, uint32_t page, uint32_t reg, uint8_t msb, uint8_t lsb, uint32_t *pData) +{ + int32_t ret = 0; + uint32_t rData = 0; + uint32_t op = (page & 0x3f) | ((reg & 0x1f) << 6) | (0x8000); + uint32_t i = 0; + uint32_t mask = 0; + mask = UINT32_BITS_MASK(msb,lsb); + + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phy_id, 30, 323, 15, 0, op)); + + for (i = 0; i < 10; i++) + { + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_read(phy_id, 30, 323, 15, 15, &rData)); + if (rData == 0) + { + break; + } + udelay(10); + } + if (i == 10) + { + return -1; + } + + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_read(phy_id, 30, 322, 15, 0, &rData)); + *pData = REG32_FIELD_GET(rData, lsb, mask); + + return ret; +} + +int rtk_phylib_826xb_sds_write(u32 phy_id, uint32_t page, uint32_t reg, uint8_t msb, uint8_t lsb, uint32_t data) +{ + int32_t ret = 0; + uint32_t wData = 0, rData = 0; + uint32_t op = (page & 0x3f) | ((reg & 0x1f) << 6) | (0x8800); + uint32_t mask = 0; + mask = UINT32_BITS_MASK(msb,lsb); + + RTK_PHYLIB_ERR_CHK(rtk_phylib_826xb_sds_read(phy_id, page, reg, 15, 0, &rData)); + + wData = REG32_FIELD_SET(rData, data, lsb, mask); + + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phy_id, 30, 321, 15, 0, wData)); + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phy_id, 30, 323, 15, 0, op)); + + return ret; +} + +int32_t phy_common_general_reg_mmd_get(u32 phy_id, u32 mmdAddr, u32 mmdReg, u32 *pData) +{ + u32 phy_data = 0; + phy_data = rtl8261_phy_reg_read(0x0, phy_id, + RTL8261_REG_ADDRESS(mmdAddr, mmdReg)); + *pData = (u32)phy_data; + return 0; +} + +int32_t phy_common_general_reg_mmd_set(u32 phy_id, u32 mmdAddr, u32 mmdReg, u32 data) +{ + rtl8261_phy_reg_write(0, phy_id, RTL8261_REG_ADDRESS(mmdAddr, mmdReg), data); + return 0; +} + +/* +int32_t rtk_phylib_time_usecs_get(ulong *pUsec) +{ + if(NULL == pUsec) + return RTK_PHYLIB_ERR_INPUT; + + *pUsec = get_timer(); + return 0; +} +*/ + +extern int32_t phy_rtl826xb_patch_db_init(u32 phy_id, rt_phy_patch_db_t **pPhy_patchDb); +extern int32 phy_patch(uint32 phy_id, uint8 portOffset, uint8 patch_mode); +#define PHY_PATCH_MODE_NORMAL 0 +#define PHY_PATCH_MODE_CMP 1 + +rt_phy_patch_db_t * patch[2] = {NULL, NULL}; +rt_phy_patch_db_t * get_patch_db(int32_t phy_id) +{ + + return (1 == phy_id) ? patch[0]:patch[1]; +} + +int rtk_phylib_826xb_intr_read_clear(u32 phy_id, uint32 *status) +{ + int32 ret = 0; + uint32 rData = 0; + uint32 rStatus = 0; + + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_read(phy_id, 31, 0xA43A, 15, 0, &rData)); + if(rData & BIT_2) + rStatus |= RTK_PHY_INTR_NEXT_PAGE_RECV; + if(rData & BIT_3) + rStatus |= RTK_PHY_INTR_AN_COMPLETE; + if(rData & BIT_4) + rStatus |= RTK_PHY_INTR_LINK_CHANGE; + if(rData & BIT_9) + rStatus |= RTK_PHY_INTR_ALDPS_STATE_CHANGE; + if(rData & BIT_11) + rStatus |= RTK_PHY_INTR_FATAL_ERROR; + if(rData & BIT_7) + rStatus |= RTK_PHY_INTR_WOL; + + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_read(phy_id, 31, 0xE2, 15, 0, &rData)); + if(rData & BIT_1) + rStatus |= RTK_PHY_INTR_RLFD; + if(rData & BIT_3) + rStatus |= RTK_PHY_INTR_TM_LOW; + if(rData & BIT_4) + rStatus |= RTK_PHY_INTR_TM_HIGH; + if(rData & BIT_6) + rStatus |= RTK_PHY_INTR_MACSEC; + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phy_id, 30, 0xE2, 15, 0, 0xFF)); + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phy_id, 30, 0x2DC, 15, 0, 0xFF)); + + *status = rStatus; + return ret; +} + +int rtk_phylib_826xb_intr_init(u32 phy_id) +{ + int32 ret = 0; + uint32 status = 0; + + /* Disable all IMR*/ + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phy_id, 30, 0xE1, 15, 0, 0)); + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phy_id, 30, 0xE3, 15, 0, 0)); + + /* source */ + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phy_id, 30, 0xE4, 15, 0, 0x1)); + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phy_id, 30, 0xE0, 15, 0, 0x2F)); + + /* init common link change */ + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phy_id, 31, 0xA424, 15, 0, 0x10)); + /* init rlfd */ + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phy_id, 31, 0xA442, 15, 15, 0x1)); + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phy_id, 31, 0xA448, 7, 7, 0x1)); + /* init tm */ + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phy_id, 30, 0x1A0, 11, 11, 0x1)); + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phy_id, 30, 0x19D, 11, 11, 0x1)); + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phy_id, 30, 0x1A1, 11, 11, 0x1)); + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phy_id, 30, 0x19F, 11, 11, 0x1)); + /* init WOL */ + RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phy_id, 31, 0xA424, 7, 7, 0x1)); + + /* clear status */ + RTK_PHYLIB_ERR_CHK(rtk_phylib_826xb_intr_read_clear(phy_id, &status)); + + return ret; +} + +int rtl8261_phy_init(struct phy_ops **ops, u32 phy_id) +{ + u16 phy_data; + struct phy_ops *rtl8261_ops; + rt_phy_patch_db_t *pPatchDb = NULL; + int32 ret = 0; + + rtl8261_ops = (struct phy_ops *)malloc(sizeof(struct phy_ops)); + if (!rtl8261_ops) + return -ENOMEM; + rtl8261_ops->phy_get_link_status = rtl8261_phy_get_link_status; + rtl8261_ops->phy_get_speed = rtl8261_phy_get_speed; + rtl8261_ops->phy_get_duplex = rtl8261_phy_get_duplex; + *ops = rtl8261_ops; + + if (0 == phy_id) + { + phy_rtl826xb_patch_db_init(phy_id, &patch[0]); + printf ("patch address: 0x%p\n", patch[0]); + } + else + { + phy_rtl826xb_patch_db_init(phy_id, &patch[1]); + printf ("patch address: 0x%p\n", patch[1]); + } + + PHYPATCH_DB_GET(phy_id, pPatchDb); + printf ("PHYPATCH_DB_GET: 0x%p\n", pPatchDb); + + phy_data = rtl8261_phy_reg_read(0x0, phy_id, + RTL8261_REG_ADDRESS(RTL8261_MMD_PMAPMD, RTL8261_MMD_PMAPMD_PHY_ID1)); + printf ("PHY ID1: 0x%x\n", phy_data); + phy_data = rtl8261_phy_reg_read(0x0, phy_id, + RTL8261_REG_ADDRESS(RTL8261_MMD_PMAPMD, RTL8261_MMD_PMAPMD_PHY_ID2)); + printf ("PHY ID2: 0x%x\n", phy_data); + + rtl8261_phy_reg_write(0, phy_id, RTL8261_REG_ADDRESS(30, 0x145), 0x0001); + rtl8261_phy_reg_write(0, phy_id, RTL8261_REG_ADDRESS(30, 0x145), 0x0000); + mdelay(30); + ret = phy_patch(phy_id, 0, PHY_PATCH_MODE_NORMAL); + if (ret) + { + printf("patch failed.\n"); + } + +#if 0 + ret = phy_patch(phy_id, 0, PHY_PATCH_MODE_CMP); + if (ret) + { + printf("patch check failed ret 0X%X.\n",ret); + } + printf("patch check ok ret=%d\n", ret); +#endif + +#if 0 + ret = rtk_phylib_826xb_intr_init(phy_id); + if (ret) + { + printf("intrrupt init failed\n"); + } +#endif + + rtk_phylib_826xb_sds_write(phy_id, 6, 3, 15, 0, 0x88C6); + + phy_data = rtl8261_phy_reg_read(0, phy_id, RTL8261_REG_ADDRESS(1, 0x00)); + rtl8261_phy_reg_write(0, phy_id, RTL8261_REG_ADDRESS(1, 0x00), phy_data&(~BIT_11) ); +#if 0 + phy_data = rtl8261_phy_reg_read(0x0, phy_id, + RTL8261_REG_ADDRESS(0x1, 0x0)); + printf ("phy_id(%d) mmd-aadr(0x1) mmd-reg(0x0) value = 0x%x\n", phy_id, phy_data); + + phy_data = rtl8261_phy_reg_read(0x0, phy_id, + RTL8261_REG_ADDRESS(31, 0xa434)); + printf ("phy_id(%d) mmd-aadr(31) mmd-reg(0xa434) value = 0x%x\n", phy_id, phy_data); + + phy_data = rtl8261_phy_reg_read(0x0, phy_id, + RTL8261_REG_ADDRESS(30, 0x105)); + printf ("phy_id(%d) mmd-aadr(30) mmd-reg(0x105) value = 0x%x\n", phy_id, phy_data); + + rtl8261_phy_reg_write(0, phy_id, RTL8261_REG_ADDRESS(30, 0x143), 0x859f); + phy_data = rtl8261_phy_reg_read(0x0, phy_id, + RTL8261_REG_ADDRESS(30, 0x142)); + printf ("phy_id(%d) mmd-aadr(30) mmd-reg(0x142) value = 0x%x\n", phy_id, phy_data); + + rtl8261_phy_reg_write(0, phy_id, RTL8261_REG_ADDRESS(30, 0x143), 0x8005); + phy_data = rtl8261_phy_reg_read(0x0, phy_id, + RTL8261_REG_ADDRESS(30, 0x142)); + printf ("phy_id(%d) mmd-aadr(30) mmd-reg(0x142) value = 0x%x\n", phy_id, phy_data); + + phy_data = rtl8261_phy_reg_read(0x0, phy_id, + RTL8261_REG_ADDRESS(30, 0xc1)); + printf ("phy_id(%d) mmd-aadr(30) mmd-reg(0xc1) value = 0x%x\n", phy_id, phy_data); + + phy_data = rtl8261_phy_reg_read(0x0, phy_id, + RTL8261_REG_ADDRESS(31, 0xa5d4)); + printf ("phy_id(%d) mmd-aadr(31) mmd-reg(0xa5d4) value = 0x%x\n", phy_id, phy_data); + + phy_data = rtl8261_phy_reg_read(0x0, phy_id, + RTL8261_REG_ADDRESS(30, 0x2d2)); + printf ("phy_id(%d) mmd-aadr(30) mmd-reg(0x2d2) value = 0x%x\n", phy_id, phy_data); + + phy_data = rtl8261_phy_reg_read(0x0, phy_id, + RTL8261_REG_ADDRESS(30, 0x2d3)); + printf ("phy_id(%d) mmd-aadr(30) mmd-reg(0x2d3) value = 0x%x\n", phy_id, phy_data); + + phy_data = rtl8261_phy_reg_read(0x0, phy_id, + RTL8261_REG_ADDRESS(30, 0x2d4)); + printf ("phy_id(%d) mmd-aadr(30) mmd-reg(0x2d4) value = 0x%x\n", phy_id, phy_data); + + phy_data = rtl8261_phy_reg_read(0x0, phy_id, + RTL8261_REG_ADDRESS(30, 0x2d5)); + printf ("phy_id(%d) mmd-aadr(30) mmd-reg(0x2d5) value = 0x%x\n", phy_id, phy_data); +#endif + return 0; +} + +static int do_rtl8261_mdio(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + char op[2]; + unsigned int phy_id = 0, addr = 0, reg = 0; + unsigned int data = 0; + + if (argc < 2) + return CMD_RET_USAGE; + + op[0] = argv[1][0]; + if (strlen(argv[1]) > 1) + op[1] = argv[1][1]; + else + op[1] = '\0'; + + if (argc >= 3) + phy_id = simple_strtoul(argv[2], NULL, 16); + if (argc >= 4) + addr = simple_strtoul(argv[3], NULL, 16); + if (argc >= 5) + reg = simple_strtoul(argv[4], NULL, 16); + if (argc >= 6) + data = simple_strtoul(argv[5], NULL, 16); + + if (op[0] == 'r') { + data = rtl8261_phy_reg_read(0x0, phy_id,RTL8261_REG_ADDRESS(addr, reg)); + printf("read phy_id(0x%x) mmd(0x%x) reg(0x%x) value(0x%x)\n", phy_id, addr, reg, data); + } else if (op[0] == 'w') { + rtl8261_phy_reg_write(0, phy_id, RTL8261_REG_ADDRESS(addr, reg), data); + printf("write phy_id(0x%x) mmd(0x%x) reg(0x%x) value(0x%x)\n", phy_id, addr, reg, data); + } else { + return CMD_RET_USAGE; + } + + return 0; +} + +U_BOOT_CMD( + rtl8261_mdio, 6, 1, do_rtl8261_mdio, + "rtl8261 mdio utility commands", + "rtl8261_mdio read - read RTL8361 MDIO PHY \n" + "rtl8261_mdio write - write RTL8361 MDIO PHY \n" + "Addr and/or reg may be ranges, e.g. 0-7." +); + + diff --git a/sources/uboot-be550/drivers/net/ipq_common/rtl8261_phy.h b/sources/uboot-be550/drivers/net/ipq_common/rtl8261_phy.h new file mode 100644 index 00000000..06cb303f --- /dev/null +++ b/sources/uboot-be550/drivers/net/ipq_common/rtl8261_phy.h @@ -0,0 +1,203 @@ +#ifndef _RTL8261_PHY_H_ +#define _RTL8261_PHY_H_ + +#define BIT_0 0x00000001U +#define BIT_1 0x00000002U +#define BIT_2 0x00000004U +#define BIT_3 0x00000008U +#define BIT_4 0x00000010U +#define BIT_5 0x00000020U +#define BIT_6 0x00000040U +#define BIT_7 0x00000080U +#define BIT_8 0x00000100U +#define BIT_9 0x00000200U +#define BIT_10 0x00000400U +#define BIT_11 0x00000800U +#define BIT_12 0x00001000U +#define BIT_13 0x00002000U +#define BIT_14 0x00004000U +#define BIT_15 0x00008000U +#define BIT_16 0x00010000U +#define BIT_17 0x00020000U +#define BIT_18 0x00040000U +#define BIT_19 0x00080000U +#define BIT_20 0x00100000U +#define BIT_21 0x00200000U +#define BIT_22 0x00400000U +#define BIT_23 0x00800000U +#define BIT_24 0x01000000U +#define BIT_25 0x02000000U +#define BIT_26 0x04000000U +#define BIT_27 0x08000000U +#define BIT_28 0x10000000U +#define BIT_29 0x20000000U +#define BIT_30 0x40000000U +#define BIT_31 0x80000000U + +#define SPEED_MASK 0x00000630U +#define SPEED_10M 0x00000000U +#define SPEED_100M 0x00000010U +#define SPEED_1000M 0x00000020U +#define SPEED_2500M 0x00000210U +#define SPEED_5000M 0x00000220U +#define SPEED_10000M 0x00000200U + +#define RTK_PHY_INTR_NEXT_PAGE_RECV (BIT_0) +#define RTK_PHY_INTR_AN_COMPLETE (BIT_1) +#define RTK_PHY_INTR_LINK_CHANGE (BIT_2) +#define RTK_PHY_INTR_ALDPS_STATE_CHANGE (BIT_3) +#define RTK_PHY_INTR_RLFD (BIT_4) +#define RTK_PHY_INTR_TM_LOW (BIT_5) +#define RTK_PHY_INTR_TM_HIGH (BIT_6) +#define RTK_PHY_INTR_FATAL_ERROR (BIT_7) +#define RTK_PHY_INTR_MACSEC (BIT_8) +#define RTK_PHY_INTR_PTP1588 (BIT_9) +#define RTK_PHY_INTR_WOL (BIT_10) + +#define RTL8261_MII_ADDR_C45 (1<<30) +#define RTL8261_REG_ADDRESS(dev_ad, reg_num) (RTL8261_MII_ADDR_C45 |\ + ((dev_ad & 0x1f) << 16) | (reg_num & 0xFFFF)) + + +#define RTL8261_MMD_PMAPMD 0x1 +#define RTL8261_MMD_PMAPMD_PHY_ID1 0x2 +#define RTL8261_MMD_PMAPMD_PHY_ID2 0x3 + +#define RTL8261_MMD_AUTONEG 0x7 + +#define RTL8261_MMD_AUTONEG 0x7 +#define RTL8261_MMD_AN_CTRL 0x0 +#define RTL8261_MMD_AN_STAT 0x1 + +#define PHY_MMD_PCS 3 +#define PHY_MMD_AN 7 +#define PHY_MMD_VEND1 30 /* Vendor specific 1 */ +#define PHY_MMD_VEND2 31 /* Vendor specific 2 */ + +#define REG32_FIELD_SET(_data, _val, _fOffset, _fMask) ((_data & ~(_fMask)) | ((_val << (_fOffset)) & (_fMask))) +#define REG32_FIELD_GET(_data, _fOffset, _fMask) ((_data & (_fMask)) >> (_fOffset)) +#define UINT32_BITS_MASK(_mBit, _lBit) ((0xFFFFFFFF >> (31 - _mBit)) ^ ((1 << _lBit) - 1)) +#define RTK_PHYLIB_ERR_CHK(op)\ +do {\ + if ((ret = (op)) != 0)\ + { \ + printf("error ret(%d) %s, %d\n", ret, __FUNCTION__, __LINE__); \ + return ret;\ + } \ +} while(0) + +typedef enum rtk_phypatch_type_e +{ + PHY_PATCH_TYPE_NONE = 0, + PHY_PATCH_TYPE_TOP = 1, + PHY_PATCH_TYPE_SDS, + PHY_PATCH_TYPE_AFE, + PHY_PATCH_TYPE_UC, + PHY_PATCH_TYPE_UC2, + PHY_PATCH_TYPE_NCTL0, + PHY_PATCH_TYPE_NCTL1, + PHY_PATCH_TYPE_NCTL2, + PHY_PATCH_TYPE_ALGXG, + PHY_PATCH_TYPE_ALG1G, + PHY_PATCH_TYPE_NORMAL, + PHY_PATCH_TYPE_DATARAM, + PHY_PATCH_TYPE_RTCT, + PHY_PATCH_TYPE_END +} rtk_phypatch_type_t; + +#define RTK_PATCH_TYPE_FLOW(_id) (PHY_PATCH_TYPE_END + _id) +#define RTK_PATCH_TYPE_FLOWID_MAX PHY_PATCH_TYPE_END +#define RTK_PATCH_SEQ_MAX ( PHY_PATCH_TYPE_END + RTK_PATCH_TYPE_FLOWID_MAX -1) + +#define uint8 u8 +#define uint16 u16 +#define uint32 u32 +#define int32 int32_t + +typedef struct rtk_hwpatch_s +{ + uint8 patch_op; + uint8 portmask; + uint16 pagemmd; + uint16 addr; + uint8 msb; + uint8 lsb; + uint16 data; + uint8 compare_op; + uint16 sram_p; + uint16 sram_rr; + uint16 sram_rw; + uint16 sram_a; +} rtk_hwpatch_t; + +typedef struct rtk_hwpatch_data_s +{ + rtk_hwpatch_t *conf; + uint32 size; +} rtk_hwpatch_data_t; + +typedef struct rtk_hwpatch_seq_s +{ + uint8 patch_type; + union + { + rtk_hwpatch_data_t data; + uint8 flow_id; + } patch; +} rtk_hwpatch_seq_t; + +typedef struct rt_phy_patch_db_s +{ + /* patch operation */ + int32_t (*fPatch_op)(u32 phy_id, u8 portOffset, rtk_hwpatch_t *pPatch_data, u8 patch_mode); + int32_t (*fPatch_flow)(u32 phy_id, u8 portOffset, u8 patch_flow, u8 patch_mode); + + /* patch data */ + rtk_hwpatch_seq_t seq_table[RTK_PATCH_SEQ_MAX]; + rtk_hwpatch_seq_t cmp_table[RTK_PATCH_SEQ_MAX]; + +} rt_phy_patch_db_t; + +int32_t phy_common_general_reg_mmd_get(u32 phy_id, u32 mmdAddr, u32 mmdReg, u32 *pData); +int32_t phy_common_general_reg_mmd_set(u32 phy_id, u32 mmdAddr, u32 mmdReg, u32 data); + +int32_t rtk_phylib_time_usecs_get(ulong *pUsec); + +rt_phy_patch_db_t * get_patch_db(int32_t phy_id); + +#ifndef WAIT_COMPLETE_VAR +#define WAIT_COMPLETE_VAR() \ + ulong _t, _now, _t_wait=0, _timeout; \ + int32 _chkCnt=0; + +#define WAIT_COMPLETE(_timeout_us) \ + _timeout = _timeout_us; \ + for(rtk_phylib_time_usecs_get(&_t),rtk_phylib_time_usecs_get(&_now),_t_wait=0,_chkCnt=0 ; \ + (_t_wait <= _timeout); \ + rtk_phylib_time_usecs_get(&_now), _chkCnt++, _t_wait += ((_now >= _t) ? (_now - _t) : (0xFFFFFFFF - _t + _now)),_t = _now \ + ) + +#define WAIT_COMPLETE_IS_TIMEOUT() (_t_wait > _timeout) +#endif + +#define HWP_PORT_SMI(phy_id) 0 +#define HWP_PHY_MODEL_BY_PORT(phy_id) 0 +#define HWP_PHY_ADDR(phy_id) 0 +#define HWP_PHY_BASE_MACID(phy_id) 0 +#define HWP_PORT_TRAVS_EXCEPT_CPU(phy_id, p) if (bcast_phyad < 0x1F && p != NULL) + +#define RT_LOG(level, module, fmt, args...) do {} while(0) +#define RT_ERR(error_code, module, fmt, args...) do {} while(0) +#define RT_INIT_ERR(error_code, module, fmt, args...) do {} while(0) +#define RT_INIT_MSG(fmt, args...) do {} while(0) + +#define phy_826xb_ctrl_set(phy_id, RTK_PHY_CTRL_MIIM_BCAST_PHYAD, bcast_phyad) 0 + +#define PHYPATCH_DB_GET(phy_id, _pPatchDb) \ + do { \ + _pPatchDb = get_patch_db(phy_id); \ + /*printk("[PHYPATCH_DB_GET] ? [%s]\n", (_pDb != NULL) ? "E":"N");*/ \ + } while(0) + +#endif /* _RTL8261_PHY_H_ */ + diff --git a/sources/uboot-be550/drivers/net/keystone_net.c b/sources/uboot-be550/drivers/net/keystone_net.c new file mode 100644 index 00000000..24ca52e2 --- /dev/null +++ b/sources/uboot-be550/drivers/net/keystone_net.c @@ -0,0 +1,639 @@ +/* + * Ethernet driver for TI K2HK EVM. + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +unsigned int emac_open; +static struct mii_dev *mdio_bus; +static unsigned int sys_has_mdio = 1; + +#ifdef KEYSTONE2_EMAC_GIG_ENABLE +#define emac_gigabit_enable(x) keystone2_eth_gigabit_enable(x) +#else +#define emac_gigabit_enable(x) /* no gigabit to enable */ +#endif + +#define RX_BUFF_NUMS 24 +#define RX_BUFF_LEN 1520 +#define MAX_SIZE_STREAM_BUFFER RX_BUFF_LEN +#define SGMII_ANEG_TIMEOUT 4000 + +static u8 rx_buffs[RX_BUFF_NUMS * RX_BUFF_LEN] __aligned(16); + +struct rx_buff_desc net_rx_buffs = { + .buff_ptr = rx_buffs, + .num_buffs = RX_BUFF_NUMS, + .buff_len = RX_BUFF_LEN, + .rx_flow = 22, +}; + +#ifndef CONFIG_SOC_K2G +static void keystone2_net_serdes_setup(void); +#endif + +int keystone2_eth_read_mac_addr(struct eth_device *dev) +{ + struct eth_priv_t *eth_priv; + u32 maca = 0; + u32 macb = 0; + + eth_priv = (struct eth_priv_t *)dev->priv; + + /* Read the e-fuse mac address */ + if (eth_priv->slave_port == 1) { + maca = __raw_readl(MAC_ID_BASE_ADDR); + macb = __raw_readl(MAC_ID_BASE_ADDR + 4); + } + + dev->enetaddr[0] = (macb >> 8) & 0xff; + dev->enetaddr[1] = (macb >> 0) & 0xff; + dev->enetaddr[2] = (maca >> 24) & 0xff; + dev->enetaddr[3] = (maca >> 16) & 0xff; + dev->enetaddr[4] = (maca >> 8) & 0xff; + dev->enetaddr[5] = (maca >> 0) & 0xff; + + return 0; +} + +/* MDIO */ + +static int keystone2_mdio_reset(struct mii_dev *bus) +{ + u_int32_t clkdiv; + struct mdio_regs *adap_mdio = bus->priv; + + clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1; + + writel((clkdiv & 0xffff) | MDIO_CONTROL_ENABLE | + MDIO_CONTROL_FAULT | MDIO_CONTROL_FAULT_ENABLE, + &adap_mdio->control); + + while (readl(&adap_mdio->control) & MDIO_CONTROL_IDLE) + ; + + return 0; +} + +/** + * keystone2_mdio_read - read a PHY register via MDIO interface. + * Blocks until operation is complete. + */ +static int keystone2_mdio_read(struct mii_dev *bus, + int addr, int devad, int reg) +{ + int tmp; + struct mdio_regs *adap_mdio = bus->priv; + + while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO) + ; + + writel(MDIO_USERACCESS0_GO | MDIO_USERACCESS0_WRITE_READ | + ((reg & 0x1f) << 21) | ((addr & 0x1f) << 16), + &adap_mdio->useraccess0); + + /* Wait for command to complete */ + while ((tmp = readl(&adap_mdio->useraccess0)) & MDIO_USERACCESS0_GO) + ; + + if (tmp & MDIO_USERACCESS0_ACK) + return tmp & 0xffff; + + return -1; +} + +/** + * keystone2_mdio_write - write to a PHY register via MDIO interface. + * Blocks until operation is complete. + */ +static int keystone2_mdio_write(struct mii_dev *bus, + int addr, int devad, int reg, u16 val) +{ + struct mdio_regs *adap_mdio = bus->priv; + + while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO) + ; + + writel(MDIO_USERACCESS0_GO | MDIO_USERACCESS0_WRITE_WRITE | + ((reg & 0x1f) << 21) | ((addr & 0x1f) << 16) | + (val & 0xffff), &adap_mdio->useraccess0); + + /* Wait for command to complete */ + while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO) + ; + + return 0; +} + +static void __attribute__((unused)) + keystone2_eth_gigabit_enable(struct eth_device *dev) +{ + u_int16_t data; + struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv; + + if (sys_has_mdio) { + data = keystone2_mdio_read(mdio_bus, eth_priv->phy_addr, + MDIO_DEVAD_NONE, 0); + /* speed selection MSB */ + if (!(data & (1 << 6))) + return; + } + + /* + * Check if link detected is giga-bit + * If Gigabit mode detected, enable gigbit in MAC + */ + writel(readl(DEVICE_EMACSL_BASE(eth_priv->slave_port - 1) + + CPGMACSL_REG_CTL) | + EMAC_MACCONTROL_GIGFORCE | EMAC_MACCONTROL_GIGABIT_ENABLE, + DEVICE_EMACSL_BASE(eth_priv->slave_port - 1) + CPGMACSL_REG_CTL); +} + +#ifdef CONFIG_SOC_K2G +int keystone_rgmii_config(struct phy_device *phy_dev) +{ + unsigned int i, status; + + i = 0; + do { + if (i > SGMII_ANEG_TIMEOUT) { + puts(" TIMEOUT !\n"); + phy_dev->link = 0; + return 0; + } + + if (ctrlc()) { + puts("user interrupt!\n"); + phy_dev->link = 0; + return -EINTR; + } + + if ((i++ % 500) == 0) + printf("."); + + udelay(1000); /* 1 ms */ + status = readl(RGMII_STATUS_REG); + } while (!(status & RGMII_REG_STATUS_LINK)); + + puts(" done\n"); + + return 0; +} +#else +int keystone_sgmii_config(struct phy_device *phy_dev, int port, int interface) +{ + unsigned int i, status, mask; + unsigned int mr_adv_ability, control; + + switch (interface) { + case SGMII_LINK_MAC_MAC_AUTONEG: + mr_adv_ability = (SGMII_REG_MR_ADV_ENABLE | + SGMII_REG_MR_ADV_LINK | + SGMII_REG_MR_ADV_FULL_DUPLEX | + SGMII_REG_MR_ADV_GIG_MODE); + control = (SGMII_REG_CONTROL_MASTER | + SGMII_REG_CONTROL_AUTONEG); + + break; + case SGMII_LINK_MAC_PHY: + case SGMII_LINK_MAC_PHY_FORCED: + mr_adv_ability = SGMII_REG_MR_ADV_ENABLE; + control = SGMII_REG_CONTROL_AUTONEG; + + break; + case SGMII_LINK_MAC_MAC_FORCED: + mr_adv_ability = (SGMII_REG_MR_ADV_ENABLE | + SGMII_REG_MR_ADV_LINK | + SGMII_REG_MR_ADV_FULL_DUPLEX | + SGMII_REG_MR_ADV_GIG_MODE); + control = SGMII_REG_CONTROL_MASTER; + + break; + case SGMII_LINK_MAC_FIBER: + mr_adv_ability = 0x20; + control = SGMII_REG_CONTROL_AUTONEG; + + break; + default: + mr_adv_ability = SGMII_REG_MR_ADV_ENABLE; + control = SGMII_REG_CONTROL_AUTONEG; + } + + __raw_writel(0, SGMII_CTL_REG(port)); + + /* + * Wait for the SerDes pll to lock, + * but don't trap if lock is never read + */ + for (i = 0; i < 1000; i++) { + udelay(2000); + status = __raw_readl(SGMII_STATUS_REG(port)); + if ((status & SGMII_REG_STATUS_LOCK) != 0) + break; + } + + __raw_writel(mr_adv_ability, SGMII_MRADV_REG(port)); + __raw_writel(control, SGMII_CTL_REG(port)); + + + mask = SGMII_REG_STATUS_LINK; + + if (control & SGMII_REG_CONTROL_AUTONEG) + mask |= SGMII_REG_STATUS_AUTONEG; + + status = __raw_readl(SGMII_STATUS_REG(port)); + if ((status & mask) == mask) + return 0; + + printf("\n%s Waiting for SGMII auto negotiation to complete", + phy_dev->dev->name); + while ((status & mask) != mask) { + /* + * Timeout reached ? + */ + if (i > SGMII_ANEG_TIMEOUT) { + puts(" TIMEOUT !\n"); + phy_dev->link = 0; + return 0; + } + + if (ctrlc()) { + puts("user interrupt!\n"); + phy_dev->link = 0; + return -EINTR; + } + + if ((i++ % 500) == 0) + printf("."); + + udelay(1000); /* 1 ms */ + status = __raw_readl(SGMII_STATUS_REG(port)); + } + puts(" done\n"); + + return 0; +} +#endif + +int mac_sl_reset(u32 port) +{ + u32 i, v; + + if (port >= DEVICE_N_GMACSL_PORTS) + return GMACSL_RET_INVALID_PORT; + + /* Set the soft reset bit */ + writel(CPGMAC_REG_RESET_VAL_RESET, + DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET); + + /* Wait for the bit to clear */ + for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) { + v = readl(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET); + if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) != + CPGMAC_REG_RESET_VAL_RESET) + return GMACSL_RET_OK; + } + + /* Timeout on the reset */ + return GMACSL_RET_WARN_RESET_INCOMPLETE; +} + +int mac_sl_config(u_int16_t port, struct mac_sl_cfg *cfg) +{ + u32 v, i; + int ret = GMACSL_RET_OK; + + if (port >= DEVICE_N_GMACSL_PORTS) + return GMACSL_RET_INVALID_PORT; + + if (cfg->max_rx_len > CPGMAC_REG_MAXLEN_LEN) { + cfg->max_rx_len = CPGMAC_REG_MAXLEN_LEN; + ret = GMACSL_RET_WARN_MAXLEN_TOO_BIG; + } + + /* Must wait if the device is undergoing reset */ + for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) { + v = readl(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET); + if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) != + CPGMAC_REG_RESET_VAL_RESET) + break; + } + + if (i == DEVICE_EMACSL_RESET_POLL_COUNT) + return GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE; + + writel(cfg->max_rx_len, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_MAXLEN); + writel(cfg->ctl, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_CTL); + +#ifndef CONFIG_SOC_K2HK + /* Map RX packet flow priority to 0 */ + writel(0, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RX_PRI_MAP); +#endif + + return ret; +} + +int ethss_config(u32 ctl, u32 max_pkt_size) +{ + u32 i; + + /* Max length register */ + writel(max_pkt_size, DEVICE_CPSW_BASE + CPSW_REG_MAXLEN); + + /* Control register */ + writel(ctl, DEVICE_CPSW_BASE + CPSW_REG_CTL); + + /* All statistics enabled by default */ + writel(CPSW_REG_VAL_STAT_ENABLE_ALL, + DEVICE_CPSW_BASE + CPSW_REG_STAT_PORT_EN); + + /* Reset and enable the ALE */ + writel(CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE | + CPSW_REG_VAL_ALE_CTL_BYPASS, + DEVICE_CPSW_BASE + CPSW_REG_ALE_CONTROL); + + /* All ports put into forward mode */ + for (i = 0; i < DEVICE_CPSW_NUM_PORTS; i++) + writel(CPSW_REG_VAL_PORTCTL_FORWARD_MODE, + DEVICE_CPSW_BASE + CPSW_REG_ALE_PORTCTL(i)); + + return 0; +} + +int ethss_start(void) +{ + int i; + struct mac_sl_cfg cfg; + + cfg.max_rx_len = MAX_SIZE_STREAM_BUFFER; + cfg.ctl = GMACSL_ENABLE | GMACSL_RX_ENABLE_EXT_CTL; + + for (i = 0; i < DEVICE_N_GMACSL_PORTS; i++) { + mac_sl_reset(i); + mac_sl_config(i, &cfg); + } + + return 0; +} + +int ethss_stop(void) +{ + int i; + + for (i = 0; i < DEVICE_N_GMACSL_PORTS; i++) + mac_sl_reset(i); + + return 0; +} + +int32_t cpmac_drv_send(u32 *buffer, int num_bytes, int slave_port_num) +{ + if (num_bytes < EMAC_MIN_ETHERNET_PKT_SIZE) + num_bytes = EMAC_MIN_ETHERNET_PKT_SIZE; + + return ksnav_send(&netcp_pktdma, buffer, + num_bytes, (slave_port_num) << 16); +} + +/* Eth device open */ +static int keystone2_eth_open(struct eth_device *dev, bd_t *bis) +{ + struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv; + struct phy_device *phy_dev = eth_priv->phy_dev; + + debug("+ emac_open\n"); + + net_rx_buffs.rx_flow = eth_priv->rx_flow; + + sys_has_mdio = + (eth_priv->sgmii_link_type == SGMII_LINK_MAC_PHY) ? 1 : 0; + + if (sys_has_mdio) + keystone2_mdio_reset(mdio_bus); + +#ifdef CONFIG_SOC_K2G + keystone_rgmii_config(phy_dev); +#else + keystone_sgmii_config(phy_dev, eth_priv->slave_port - 1, + eth_priv->sgmii_link_type); +#endif + + udelay(10000); + + /* On chip switch configuration */ + ethss_config(target_get_switch_ctl(), SWITCH_MAX_PKT_SIZE); + + /* TODO: add error handling code */ + if (qm_init()) { + printf("ERROR: qm_init()\n"); + return -1; + } + if (ksnav_init(&netcp_pktdma, &net_rx_buffs)) { + qm_close(); + printf("ERROR: netcp_init()\n"); + return -1; + } + + /* + * Streaming switch configuration. If not present this + * statement is defined to void in target.h. + * If present this is usually defined to a series of register writes + */ + hw_config_streaming_switch(); + + if (sys_has_mdio) { + keystone2_mdio_reset(mdio_bus); + + phy_startup(phy_dev); + if (phy_dev->link == 0) { + ksnav_close(&netcp_pktdma); + qm_close(); + return -1; + } + } + + emac_gigabit_enable(dev); + + ethss_start(); + + debug("- emac_open\n"); + + emac_open = 1; + + return 0; +} + +/* Eth device close */ +void keystone2_eth_close(struct eth_device *dev) +{ + struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv; + struct phy_device *phy_dev = eth_priv->phy_dev; + + debug("+ emac_close\n"); + + if (!emac_open) + return; + + ethss_stop(); + + ksnav_close(&netcp_pktdma); + qm_close(); + phy_shutdown(phy_dev); + + emac_open = 0; + + debug("- emac_close\n"); +} + +/* + * This function sends a single packet on the network and returns + * positive number (number of bytes transmitted) or negative for error + */ +static int keystone2_eth_send_packet(struct eth_device *dev, + void *packet, int length) +{ + int ret_status = -1; + struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv; + struct phy_device *phy_dev = eth_priv->phy_dev; + + genphy_update_link(phy_dev); + if (phy_dev->link == 0) + return -1; + + if (cpmac_drv_send((u32 *)packet, length, eth_priv->slave_port) != 0) + return ret_status; + + return length; +} + +/* + * This function handles receipt of a packet from the network + */ +static int keystone2_eth_rcv_packet(struct eth_device *dev) +{ + void *hd; + int pkt_size; + u32 *pkt; + + hd = ksnav_recv(&netcp_pktdma, &pkt, &pkt_size); + if (hd == NULL) + return 0; + + net_process_received_packet((uchar *)pkt, pkt_size); + + ksnav_release_rxhd(&netcp_pktdma, hd); + + return pkt_size; +} + +#ifdef CONFIG_MCAST_TFTP +static int keystone2_eth_bcast_addr(struct eth_device *dev, u32 ip, u8 set) +{ + return 0; +} +#endif + +/* + * This function initializes the EMAC hardware. + */ +int keystone2_emac_initialize(struct eth_priv_t *eth_priv) +{ + int res; + struct eth_device *dev; + struct phy_device *phy_dev; + + dev = malloc(sizeof(struct eth_device)); + if (dev == NULL) + return -1; + + memset(dev, 0, sizeof(struct eth_device)); + + strcpy(dev->name, eth_priv->int_name); + dev->priv = eth_priv; + + keystone2_eth_read_mac_addr(dev); + + dev->iobase = 0; + dev->init = keystone2_eth_open; + dev->halt = keystone2_eth_close; + dev->send = keystone2_eth_send_packet; + dev->recv = keystone2_eth_rcv_packet; +#ifdef CONFIG_MCAST_TFTP + dev->mcast = keystone2_eth_bcast_addr; +#endif + + eth_register(dev); + + /* Register MDIO bus if it's not registered yet */ + if (!mdio_bus) { + mdio_bus = mdio_alloc(); + mdio_bus->read = keystone2_mdio_read; + mdio_bus->write = keystone2_mdio_write; + mdio_bus->reset = keystone2_mdio_reset; + mdio_bus->priv = (void *)EMAC_MDIO_BASE_ADDR; + sprintf(mdio_bus->name, "ethernet-mdio"); + + res = mdio_register(mdio_bus); + if (res) + return res; + } + +#ifndef CONFIG_SOC_K2G + keystone2_net_serdes_setup(); +#endif + + /* Create phy device and bind it with driver */ +#ifdef CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE + phy_dev = phy_connect(mdio_bus, eth_priv->phy_addr, + dev, eth_priv->phy_if); + phy_config(phy_dev); +#else + phy_dev = phy_find_by_mask(mdio_bus, 1 << eth_priv->phy_addr, + eth_priv->phy_if); + phy_dev->dev = dev; +#endif + eth_priv->phy_dev = phy_dev; + + return 0; +} + +struct ks2_serdes ks2_serdes_sgmii_156p25mhz = { + .clk = SERDES_CLOCK_156P25M, + .rate = SERDES_RATE_5G, + .rate_mode = SERDES_QUARTER_RATE, + .intf = SERDES_PHY_SGMII, + .loopback = 0, +}; + +#ifndef CONFIG_SOC_K2G +static void keystone2_net_serdes_setup(void) +{ + ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII_BASE, + &ks2_serdes_sgmii_156p25mhz, + CONFIG_KSNET_SERDES_LANES_PER_SGMII); + +#if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L) + ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII2_BASE, + &ks2_serdes_sgmii_156p25mhz, + CONFIG_KSNET_SERDES_LANES_PER_SGMII); +#endif + + /* wait till setup */ + udelay(5000); +} +#endif diff --git a/sources/uboot-be550/drivers/net/ks8851_mll.c b/sources/uboot-be550/drivers/net/ks8851_mll.c new file mode 100644 index 00000000..5b4c5b0d --- /dev/null +++ b/sources/uboot-be550/drivers/net/ks8851_mll.c @@ -0,0 +1,633 @@ +/* + * Micrel KS8851_MLL 16bit Network driver + * Copyright (c) 2011 Roberto Cerati + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +#include "ks8851_mll.h" + +#define DRIVERNAME "ks8851_mll" + +#define MAX_RECV_FRAMES 32 +#define MAX_BUF_SIZE 2048 +#define TX_BUF_SIZE 2000 +#define RX_BUF_SIZE 2000 + +static const struct chip_id chip_ids[] = { + {CIDER_ID, "KSZ8851"}, + {0, NULL}, +}; + +/* + * union ks_tx_hdr - tx header data + * @txb: The header as bytes + * @txw: The header as 16bit, little-endian words + * + * A dual representation of the tx header data to allow + * access to individual bytes, and to allow 16bit accesses + * with 16bit alignment. + */ +union ks_tx_hdr { + u8 txb[4]; + __le16 txw[2]; +}; + +/* + * struct ks_net - KS8851 driver private data + * @net_device : The network device we're bound to + * @txh : temporaly buffer to save status/length. + * @frame_head_info : frame header information for multi-pkt rx. + * @statelock : Lock on this structure for tx list. + * @msg_enable : The message flags controlling driver output (see ethtool). + * @frame_cnt : number of frames received. + * @bus_width : i/o bus width. + * @irq : irq number assigned to this device. + * @rc_rxqcr : Cached copy of KS_RXQCR. + * @rc_txcr : Cached copy of KS_TXCR. + * @rc_ier : Cached copy of KS_IER. + * @sharedbus : Multipex(addr and data bus) mode indicator. + * @cmd_reg_cache : command register cached. + * @cmd_reg_cache_int : command register cached. Used in the irq handler. + * @promiscuous : promiscuous mode indicator. + * @all_mcast : mutlicast indicator. + * @mcast_lst_size : size of multicast list. + * @mcast_lst : multicast list. + * @mcast_bits : multicast enabed. + * @mac_addr : MAC address assigned to this device. + * @fid : frame id. + * @extra_byte : number of extra byte prepended rx pkt. + * @enabled : indicator this device works. + */ + +/* Receive multiplex framer header info */ +struct type_frame_head { + u16 sts; /* Frame status */ + u16 len; /* Byte count */ +} fr_h_i[MAX_RECV_FRAMES]; + +struct ks_net { + struct net_device *netdev; + union ks_tx_hdr txh; + struct type_frame_head *frame_head_info; + u32 msg_enable; + u32 frame_cnt; + int bus_width; + int irq; + u16 rc_rxqcr; + u16 rc_txcr; + u16 rc_ier; + u16 sharedbus; + u16 cmd_reg_cache; + u16 cmd_reg_cache_int; + u16 promiscuous; + u16 all_mcast; + u16 mcast_lst_size; + u8 mcast_lst[MAX_MCAST_LST][MAC_ADDR_LEN]; + u8 mcast_bits[HW_MCAST_SIZE]; + u8 mac_addr[6]; + u8 fid; + u8 extra_byte; + u8 enabled; +} ks_str, *ks; + +#define BE3 0x8000 /* Byte Enable 3 */ +#define BE2 0x4000 /* Byte Enable 2 */ +#define BE1 0x2000 /* Byte Enable 1 */ +#define BE0 0x1000 /* Byte Enable 0 */ + +static u8 ks_rdreg8(struct eth_device *dev, u16 offset) +{ + u8 shift_bit = offset & 0x03; + u8 shift_data = (offset & 1) << 3; + + writew(offset | (BE0 << shift_bit), dev->iobase + 2); + + return (u8)(readw(dev->iobase) >> shift_data); +} + +static u16 ks_rdreg16(struct eth_device *dev, u16 offset) +{ + writew(offset | ((BE1 | BE0) << (offset & 0x02)), dev->iobase + 2); + + return readw(dev->iobase); +} + +static void ks_wrreg8(struct eth_device *dev, u16 offset, u8 val) +{ + u8 shift_bit = (offset & 0x03); + u16 value_write = (u16)(val << ((offset & 1) << 3)); + + writew(offset | (BE0 << shift_bit), dev->iobase + 2); + writew(value_write, dev->iobase); +} + +static void ks_wrreg16(struct eth_device *dev, u16 offset, u16 val) +{ + writew(offset | ((BE1 | BE0) << (offset & 0x02)), dev->iobase + 2); + writew(val, dev->iobase); +} + +/* + * ks_inblk - read a block of data from QMU. This is called after sudo DMA mode + * enabled. + * @ks: The chip state + * @wptr: buffer address to save data + * @len: length in byte to read + */ +static inline void ks_inblk(struct eth_device *dev, u16 *wptr, u32 len) +{ + len >>= 1; + + while (len--) + *wptr++ = readw(dev->iobase); +} + +/* + * ks_outblk - write data to QMU. This is called after sudo DMA mode enabled. + * @ks: The chip information + * @wptr: buffer address + * @len: length in byte to write + */ +static inline void ks_outblk(struct eth_device *dev, u16 *wptr, u32 len) +{ + len >>= 1; + + while (len--) + writew(*wptr++, dev->iobase); +} + +static void ks_enable_int(struct eth_device *dev) +{ + ks_wrreg16(dev, KS_IER, ks->rc_ier); +} + +static void ks_set_powermode(struct eth_device *dev, unsigned pwrmode) +{ + unsigned pmecr; + + ks_rdreg16(dev, KS_GRR); + pmecr = ks_rdreg16(dev, KS_PMECR); + pmecr &= ~PMECR_PM_MASK; + pmecr |= pwrmode; + + ks_wrreg16(dev, KS_PMECR, pmecr); +} + +/* + * ks_read_config - read chip configuration of bus width. + * @ks: The chip information + */ +static void ks_read_config(struct eth_device *dev) +{ + u16 reg_data = 0; + + /* Regardless of bus width, 8 bit read should always work. */ + reg_data = ks_rdreg8(dev, KS_CCR) & 0x00FF; + reg_data |= ks_rdreg8(dev, KS_CCR + 1) << 8; + + /* addr/data bus are multiplexed */ + ks->sharedbus = (reg_data & CCR_SHARED) == CCR_SHARED; + + /* + * There are garbage data when reading data from QMU, + * depending on bus-width. + */ + if (reg_data & CCR_8BIT) { + ks->bus_width = ENUM_BUS_8BIT; + ks->extra_byte = 1; + } else if (reg_data & CCR_16BIT) { + ks->bus_width = ENUM_BUS_16BIT; + ks->extra_byte = 2; + } else { + ks->bus_width = ENUM_BUS_32BIT; + ks->extra_byte = 4; + } +} + +/* + * ks_soft_reset - issue one of the soft reset to the device + * @ks: The device state. + * @op: The bit(s) to set in the GRR + * + * Issue the relevant soft-reset command to the device's GRR register + * specified by @op. + * + * Note, the delays are in there as a caution to ensure that the reset + * has time to take effect and then complete. Since the datasheet does + * not currently specify the exact sequence, we have chosen something + * that seems to work with our device. + */ +static void ks_soft_reset(struct eth_device *dev, unsigned op) +{ + /* Disable interrupt first */ + ks_wrreg16(dev, KS_IER, 0x0000); + ks_wrreg16(dev, KS_GRR, op); + mdelay(10); /* wait a short time to effect reset */ + ks_wrreg16(dev, KS_GRR, 0); + mdelay(1); /* wait for condition to clear */ +} + +void ks_enable_qmu(struct eth_device *dev) +{ + u16 w; + + w = ks_rdreg16(dev, KS_TXCR); + + /* Enables QMU Transmit (TXCR). */ + ks_wrreg16(dev, KS_TXCR, w | TXCR_TXE); + + /* Enable RX Frame Count Threshold and Auto-Dequeue RXQ Frame */ + w = ks_rdreg16(dev, KS_RXQCR); + ks_wrreg16(dev, KS_RXQCR, w | RXQCR_RXFCTE); + + /* Enables QMU Receive (RXCR1). */ + w = ks_rdreg16(dev, KS_RXCR1); + ks_wrreg16(dev, KS_RXCR1, w | RXCR1_RXE); +} + +static void ks_disable_qmu(struct eth_device *dev) +{ + u16 w; + + w = ks_rdreg16(dev, KS_TXCR); + + /* Disables QMU Transmit (TXCR). */ + w &= ~TXCR_TXE; + ks_wrreg16(dev, KS_TXCR, w); + + /* Disables QMU Receive (RXCR1). */ + w = ks_rdreg16(dev, KS_RXCR1); + w &= ~RXCR1_RXE; + ks_wrreg16(dev, KS_RXCR1, w); +} + +static inline void ks_read_qmu(struct eth_device *dev, u16 *buf, u32 len) +{ + u32 r = ks->extra_byte & 0x1; + u32 w = ks->extra_byte - r; + + /* 1. set sudo DMA mode */ + ks_wrreg16(dev, KS_RXFDPR, RXFDPR_RXFPAI); + ks_wrreg8(dev, KS_RXQCR, (ks->rc_rxqcr | RXQCR_SDA) & 0xff); + + /* + * 2. read prepend data + * + * read 4 + extra bytes and discard them. + * extra bytes for dummy, 2 for status, 2 for len + */ + + if (r) + ks_rdreg8(dev, 0); + + ks_inblk(dev, buf, w + 2 + 2); + + /* 3. read pkt data */ + ks_inblk(dev, buf, ALIGN(len, 4)); + + /* 4. reset sudo DMA Mode */ + ks_wrreg8(dev, KS_RXQCR, (ks->rc_rxqcr & ~RXQCR_SDA) & 0xff); +} + +static void ks_rcv(struct eth_device *dev, uchar **pv_data) +{ + struct type_frame_head *frame_hdr = ks->frame_head_info; + int i; + + ks->frame_cnt = ks_rdreg16(dev, KS_RXFCTR) >> 8; + + /* read all header information */ + for (i = 0; i < ks->frame_cnt; i++) { + /* Checking Received packet status */ + frame_hdr->sts = ks_rdreg16(dev, KS_RXFHSR); + /* Get packet len from hardware */ + frame_hdr->len = ks_rdreg16(dev, KS_RXFHBCR); + frame_hdr++; + } + + frame_hdr = ks->frame_head_info; + while (ks->frame_cnt--) { + if ((frame_hdr->sts & RXFSHR_RXFV) && + (frame_hdr->len < RX_BUF_SIZE) && + frame_hdr->len) { + /* read data block including CRC 4 bytes */ + ks_read_qmu(dev, (u16 *)(*pv_data), frame_hdr->len); + + /* net_rx_packets buffer size is ok (*pv_data) */ + net_process_received_packet(*pv_data, frame_hdr->len); + pv_data++; + } else { + ks_wrreg16(dev, KS_RXQCR, (ks->rc_rxqcr | RXQCR_RRXEF)); + printf(DRIVERNAME ": bad packet\n"); + } + frame_hdr++; + } +} + +/* + * ks_read_selftest - read the selftest memory info. + * @ks: The device state + * + * Read and check the TX/RX memory selftest information. + */ +static int ks_read_selftest(struct eth_device *dev) +{ + u16 both_done = MBIR_TXMBF | MBIR_RXMBF; + u16 mbir; + int ret = 0; + + mbir = ks_rdreg16(dev, KS_MBIR); + + if ((mbir & both_done) != both_done) { + printf(DRIVERNAME ": Memory selftest not finished\n"); + return 0; + } + + if (mbir & MBIR_TXMBFA) { + printf(DRIVERNAME ": TX memory selftest fails\n"); + ret |= 1; + } + + if (mbir & MBIR_RXMBFA) { + printf(DRIVERNAME ": RX memory selftest fails\n"); + ret |= 2; + } + + debug(DRIVERNAME ": the selftest passes\n"); + + return ret; +} + +static void ks_setup(struct eth_device *dev) +{ + u16 w; + + /* Setup Transmit Frame Data Pointer Auto-Increment (TXFDPR) */ + ks_wrreg16(dev, KS_TXFDPR, TXFDPR_TXFPAI); + + /* Setup Receive Frame Data Pointer Auto-Increment */ + ks_wrreg16(dev, KS_RXFDPR, RXFDPR_RXFPAI); + + /* Setup Receive Frame Threshold - 1 frame (RXFCTFC) */ + ks_wrreg16(dev, KS_RXFCTR, 1 & RXFCTR_THRESHOLD_MASK); + + /* Setup RxQ Command Control (RXQCR) */ + ks->rc_rxqcr = RXQCR_CMD_CNTL; + ks_wrreg16(dev, KS_RXQCR, ks->rc_rxqcr); + + /* + * set the force mode to half duplex, default is full duplex + * because if the auto-negotiation fails, most switch uses + * half-duplex. + */ + w = ks_rdreg16(dev, KS_P1MBCR); + w &= ~P1MBCR_FORCE_FDX; + ks_wrreg16(dev, KS_P1MBCR, w); + + w = TXCR_TXFCE | TXCR_TXPE | TXCR_TXCRC | TXCR_TCGIP; + ks_wrreg16(dev, KS_TXCR, w); + + w = RXCR1_RXFCE | RXCR1_RXBE | RXCR1_RXUE | RXCR1_RXME | RXCR1_RXIPFCC; + + /* Normal mode */ + w |= RXCR1_RXPAFMA; + + ks_wrreg16(dev, KS_RXCR1, w); +} + +static void ks_setup_int(struct eth_device *dev) +{ + ks->rc_ier = 0x00; + + /* Clear the interrupts status of the hardware. */ + ks_wrreg16(dev, KS_ISR, 0xffff); + + /* Enables the interrupts of the hardware. */ + ks->rc_ier = (IRQ_LCI | IRQ_TXI | IRQ_RXI); +} + +static int ks8851_mll_detect_chip(struct eth_device *dev) +{ + unsigned short val, i; + + ks_read_config(dev); + + val = ks_rdreg16(dev, KS_CIDER); + + if (val == 0xffff) { + /* Special case -- no chip present */ + printf(DRIVERNAME ": is chip mounted ?\n"); + return -1; + } else if ((val & 0xfff0) != CIDER_ID) { + printf(DRIVERNAME ": Invalid chip id 0x%04x\n", val); + return -1; + } + + debug("Read back KS8851 id 0x%x\n", val); + + /* only one entry in the table */ + val &= 0xfff0; + for (i = 0; chip_ids[i].id != 0; i++) { + if (chip_ids[i].id == val) + break; + } + if (!chip_ids[i].id) { + printf(DRIVERNAME ": Unknown chip ID %04x\n", val); + return -1; + } + + dev->priv = (void *)&chip_ids[i]; + + return 0; +} + +static void ks8851_mll_reset(struct eth_device *dev) +{ + /* wake up powermode to normal mode */ + ks_set_powermode(dev, PMECR_PM_NORMAL); + mdelay(1); /* wait for normal mode to take effect */ + + /* Disable interrupt and reset */ + ks_soft_reset(dev, GRR_GSR); + + /* turn off the IRQs and ack any outstanding */ + ks_wrreg16(dev, KS_IER, 0x0000); + ks_wrreg16(dev, KS_ISR, 0xffff); + + /* shutdown RX/TX QMU */ + ks_disable_qmu(dev); +} + +static void ks8851_mll_phy_configure(struct eth_device *dev) +{ + u16 data; + + ks_setup(dev); + ks_setup_int(dev); + + /* Probing the phy */ + data = ks_rdreg16(dev, KS_OBCR); + ks_wrreg16(dev, KS_OBCR, data | OBCR_ODS_16MA); + + debug(DRIVERNAME ": phy initialized\n"); +} + +static void ks8851_mll_enable(struct eth_device *dev) +{ + ks_wrreg16(dev, KS_ISR, 0xffff); + ks_enable_int(dev); + ks_enable_qmu(dev); +} + +static int ks8851_mll_init(struct eth_device *dev, bd_t *bd) +{ + struct chip_id *id = dev->priv; + + debug(DRIVERNAME ": detected %s controller\n", id->name); + + if (ks_read_selftest(dev)) { + printf(DRIVERNAME ": Selftest failed\n"); + return -1; + } + + ks8851_mll_reset(dev); + + /* Configure the PHY, initialize the link state */ + ks8851_mll_phy_configure(dev); + + /* static allocation of private informations */ + ks->frame_head_info = fr_h_i; + + /* Turn on Tx + Rx */ + ks8851_mll_enable(dev); + + return 0; +} + +static void ks_write_qmu(struct eth_device *dev, u8 *pdata, u16 len) +{ + /* start header at txb[0] to align txw entries */ + ks->txh.txw[0] = 0; + ks->txh.txw[1] = cpu_to_le16(len); + + /* 1. set sudo-DMA mode */ + ks_wrreg16(dev, KS_TXFDPR, TXFDPR_TXFPAI); + ks_wrreg8(dev, KS_RXQCR, (ks->rc_rxqcr | RXQCR_SDA) & 0xff); + /* 2. write status/lenth info */ + ks_outblk(dev, ks->txh.txw, 4); + /* 3. write pkt data */ + ks_outblk(dev, (u16 *)pdata, ALIGN(len, 4)); + /* 4. reset sudo-DMA mode */ + ks_wrreg8(dev, KS_RXQCR, (ks->rc_rxqcr & ~RXQCR_SDA) & 0xff); + /* 5. Enqueue Tx(move the pkt from TX buffer into TXQ) */ + ks_wrreg16(dev, KS_TXQCR, TXQCR_METFE); + /* 6. wait until TXQCR_METFE is auto-cleared */ + do { } while (ks_rdreg16(dev, KS_TXQCR) & TXQCR_METFE); +} + +static int ks8851_mll_send(struct eth_device *dev, void *packet, int length) +{ + u8 *data = (u8 *)packet; + u16 tmplen = (u16)length; + u16 retv; + + /* + * Extra space are required: + * 4 byte for alignment, 4 for status/length, 4 for CRC + */ + retv = ks_rdreg16(dev, KS_TXMIR) & 0x1fff; + if (retv >= tmplen + 12) { + ks_write_qmu(dev, data, tmplen); + return 0; + } else { + printf(DRIVERNAME ": failed to send packet: No buffer\n"); + return -1; + } +} + +static void ks8851_mll_halt(struct eth_device *dev) +{ + ks8851_mll_reset(dev); +} + +/* + * Maximum receive ring size; that is, the number of packets + * we can buffer before overflow happens. Basically, this just + * needs to be enough to prevent a packet being discarded while + * we are processing the previous one. + */ +static int ks8851_mll_recv(struct eth_device *dev) +{ + u16 status; + + status = ks_rdreg16(dev, KS_ISR); + + ks_wrreg16(dev, KS_ISR, status); + + if ((status & IRQ_RXI)) + ks_rcv(dev, (uchar **)net_rx_packets); + + if ((status & IRQ_LDI)) { + u16 pmecr = ks_rdreg16(dev, KS_PMECR); + pmecr &= ~PMECR_WKEVT_MASK; + ks_wrreg16(dev, KS_PMECR, pmecr | PMECR_WKEVT_LINK); + } + + return 0; +} + +static int ks8851_mll_write_hwaddr(struct eth_device *dev) +{ + u16 addrl, addrm, addrh; + + addrh = (dev->enetaddr[0] << 8) | dev->enetaddr[1]; + addrm = (dev->enetaddr[2] << 8) | dev->enetaddr[3]; + addrl = (dev->enetaddr[4] << 8) | dev->enetaddr[5]; + + ks_wrreg16(dev, KS_MARH, addrh); + ks_wrreg16(dev, KS_MARM, addrm); + ks_wrreg16(dev, KS_MARL, addrl); + + return 0; +} + +int ks8851_mll_initialize(u8 dev_num, int base_addr) +{ + struct eth_device *dev; + + dev = malloc(sizeof(*dev)); + if (!dev) { + printf("Error: Failed to allocate memory\n"); + return -1; + } + memset(dev, 0, sizeof(*dev)); + + dev->iobase = base_addr; + + ks = &ks_str; + + /* Try to detect chip. Will fail if not present. */ + if (ks8851_mll_detect_chip(dev)) { + free(dev); + return -1; + } + + dev->init = ks8851_mll_init; + dev->halt = ks8851_mll_halt; + dev->send = ks8851_mll_send; + dev->recv = ks8851_mll_recv; + dev->write_hwaddr = ks8851_mll_write_hwaddr; + sprintf(dev->name, "%s-%hu", DRIVERNAME, dev_num); + + eth_register(dev); + + return 0; +} diff --git a/sources/uboot-be550/drivers/net/ks8851_mll.h b/sources/uboot-be550/drivers/net/ks8851_mll.h new file mode 100644 index 00000000..7f90ae4e --- /dev/null +++ b/sources/uboot-be550/drivers/net/ks8851_mll.h @@ -0,0 +1,357 @@ +/* + * drivers/net/ks8851_mll.c + * + * Supports: + * KS8851 16bit MLL chip from Micrel Inc. + * + * Copyright (c) 2009 Micrel Inc. + * + * modified by + * (c) 2011 Bticino s.p.a, Roberto Cerati + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#ifndef _KS8851_MLL_H_ +#define _KS8851_MLL_H_ + +#include + +#define KS_CCR 0x08 +#define CCR_EEPROM (1 << 9) +#define CCR_SPI (1 << 8) +#define CCR_8BIT (1 << 7) +#define CCR_16BIT (1 << 6) +#define CCR_32BIT (1 << 5) +#define CCR_SHARED (1 << 4) +#define CCR_32PIN (1 << 0) + +/* MAC address registers */ +#define KS_MARL 0x10 +#define KS_MARM 0x12 +#define KS_MARH 0x14 + +#define KS_OBCR 0x20 +#define OBCR_ODS_16MA (1 << 6) + +#define KS_EEPCR 0x22 +#define EEPCR_EESA (1 << 4) +#define EEPCR_EESB (1 << 3) +#define EEPCR_EEDO (1 << 2) +#define EEPCR_EESCK (1 << 1) +#define EEPCR_EECS (1 << 0) + +#define KS_MBIR 0x24 +#define MBIR_TXMBF (1 << 12) +#define MBIR_TXMBFA (1 << 11) +#define MBIR_RXMBF (1 << 4) +#define MBIR_RXMBFA (1 << 3) + +#define KS_GRR 0x26 +#define GRR_QMU (1 << 1) +#define GRR_GSR (1 << 0) + +#define KS_WFCR 0x2A +#define WFCR_MPRXE (1 << 7) +#define WFCR_WF3E (1 << 3) +#define WFCR_WF2E (1 << 2) +#define WFCR_WF1E (1 << 1) +#define WFCR_WF0E (1 << 0) + +#define KS_WF0CRC0 0x30 +#define KS_WF0CRC1 0x32 +#define KS_WF0BM0 0x34 +#define KS_WF0BM1 0x36 +#define KS_WF0BM2 0x38 +#define KS_WF0BM3 0x3A + +#define KS_WF1CRC0 0x40 +#define KS_WF1CRC1 0x42 +#define KS_WF1BM0 0x44 +#define KS_WF1BM1 0x46 +#define KS_WF1BM2 0x48 +#define KS_WF1BM3 0x4A + +#define KS_WF2CRC0 0x50 +#define KS_WF2CRC1 0x52 +#define KS_WF2BM0 0x54 +#define KS_WF2BM1 0x56 +#define KS_WF2BM2 0x58 +#define KS_WF2BM3 0x5A + +#define KS_WF3CRC0 0x60 +#define KS_WF3CRC1 0x62 +#define KS_WF3BM0 0x64 +#define KS_WF3BM1 0x66 +#define KS_WF3BM2 0x68 +#define KS_WF3BM3 0x6A + +#define KS_TXCR 0x70 +#define TXCR_TCGICMP (1 << 8) +#define TXCR_TCGUDP (1 << 7) +#define TXCR_TCGTCP (1 << 6) +#define TXCR_TCGIP (1 << 5) +#define TXCR_FTXQ (1 << 4) +#define TXCR_TXFCE (1 << 3) +#define TXCR_TXPE (1 << 2) +#define TXCR_TXCRC (1 << 1) +#define TXCR_TXE (1 << 0) + +#define KS_TXSR 0x72 +#define TXSR_TXLC (1 << 13) +#define TXSR_TXMC (1 << 12) +#define TXSR_TXFID_MASK (0x3f << 0) +#define TXSR_TXFID_SHIFT (0) +#define TXSR_TXFID_GET(_v) (((_v) >> 0) & 0x3f) + + +#define KS_RXCR1 0x74 +#define RXCR1_FRXQ (1 << 15) +#define RXCR1_RXUDPFCC (1 << 14) +#define RXCR1_RXTCPFCC (1 << 13) +#define RXCR1_RXIPFCC (1 << 12) +#define RXCR1_RXPAFMA (1 << 11) +#define RXCR1_RXFCE (1 << 10) +#define RXCR1_RXEFE (1 << 9) +#define RXCR1_RXMAFMA (1 << 8) +#define RXCR1_RXBE (1 << 7) +#define RXCR1_RXME (1 << 6) +#define RXCR1_RXUE (1 << 5) +#define RXCR1_RXAE (1 << 4) +#define RXCR1_RXINVF (1 << 1) +#define RXCR1_RXE (1 << 0) +#define RXCR1_FILTER_MASK (RXCR1_RXINVF | RXCR1_RXAE | \ + RXCR1_RXMAFMA | RXCR1_RXPAFMA) + +#define KS_RXCR2 0x76 +#define RXCR2_SRDBL_MASK (0x7 << 5) +#define RXCR2_SRDBL_SHIFT (5) +#define RXCR2_SRDBL_4B (0x0 << 5) +#define RXCR2_SRDBL_8B (0x1 << 5) +#define RXCR2_SRDBL_16B (0x2 << 5) +#define RXCR2_SRDBL_32B (0x3 << 5) +/* #define RXCR2_SRDBL_FRAME (0x4 << 5) */ +#define RXCR2_IUFFP (1 << 4) +#define RXCR2_RXIUFCEZ (1 << 3) +#define RXCR2_UDPLFE (1 << 2) +#define RXCR2_RXICMPFCC (1 << 1) +#define RXCR2_RXSAF (1 << 0) + +#define KS_TXMIR 0x78 + +#define KS_RXFHSR 0x7C +#define RXFSHR_RXFV (1 << 15) +#define RXFSHR_RXICMPFCS (1 << 13) +#define RXFSHR_RXIPFCS (1 << 12) +#define RXFSHR_RXTCPFCS (1 << 11) +#define RXFSHR_RXUDPFCS (1 << 10) +#define RXFSHR_RXBF (1 << 7) +#define RXFSHR_RXMF (1 << 6) +#define RXFSHR_RXUF (1 << 5) +#define RXFSHR_RXMR (1 << 4) +#define RXFSHR_RXFT (1 << 3) +#define RXFSHR_RXFTL (1 << 2) +#define RXFSHR_RXRF (1 << 1) +#define RXFSHR_RXCE (1 << 0) +#define RXFSHR_ERR (RXFSHR_RXCE | RXFSHR_RXRF |\ + RXFSHR_RXFTL | RXFSHR_RXMR |\ + RXFSHR_RXICMPFCS | RXFSHR_RXIPFCS |\ + RXFSHR_RXTCPFCS) +#define KS_RXFHBCR 0x7E +#define RXFHBCR_CNT_MASK 0x0FFF + +#define KS_TXQCR 0x80 +#define TXQCR_AETFE (1 << 2) +#define TXQCR_TXQMAM (1 << 1) +#define TXQCR_METFE (1 << 0) + +#define KS_RXQCR 0x82 +#define RXQCR_RXDTTS (1 << 12) +#define RXQCR_RXDBCTS (1 << 11) +#define RXQCR_RXFCTS (1 << 10) +#define RXQCR_RXIPHTOE (1 << 9) +#define RXQCR_RXDTTE (1 << 7) +#define RXQCR_RXDBCTE (1 << 6) +#define RXQCR_RXFCTE (1 << 5) +#define RXQCR_ADRFE (1 << 4) +#define RXQCR_SDA (1 << 3) +#define RXQCR_RRXEF (1 << 0) +#define RXQCR_CMD_CNTL (RXQCR_RXFCTE|RXQCR_ADRFE) + +#define KS_TXFDPR 0x84 +#define TXFDPR_TXFPAI (1 << 14) +#define TXFDPR_TXFP_MASK (0x7ff << 0) +#define TXFDPR_TXFP_SHIFT (0) + +#define KS_RXFDPR 0x86 +#define RXFDPR_RXFPAI (1 << 14) + +#define KS_RXDTTR 0x8C +#define KS_RXDBCTR 0x8E + +#define KS_IER 0x90 +#define KS_ISR 0x92 +#define IRQ_LCI (1 << 15) +#define IRQ_TXI (1 << 14) +#define IRQ_RXI (1 << 13) +#define IRQ_RXOI (1 << 11) +#define IRQ_TXPSI (1 << 9) +#define IRQ_RXPSI (1 << 8) +#define IRQ_TXSAI (1 << 6) +#define IRQ_RXWFDI (1 << 5) +#define IRQ_RXMPDI (1 << 4) +#define IRQ_LDI (1 << 3) +#define IRQ_EDI (1 << 2) +#define IRQ_SPIBEI (1 << 1) +#define IRQ_DEDI (1 << 0) + +#define KS_RXFCTR 0x9C +#define RXFCTR_THRESHOLD_MASK 0x00FF + +#define KS_RXFC 0x9D +#define RXFCTR_RXFC_MASK (0xff << 8) +#define RXFCTR_RXFC_SHIFT (8) +#define RXFCTR_RXFC_GET(_v) (((_v) >> 8) & 0xff) +#define RXFCTR_RXFCT_MASK (0xff << 0) +#define RXFCTR_RXFCT_SHIFT (0) + +#define KS_TXNTFSR 0x9E + +#define KS_MAHTR0 0xA0 +#define KS_MAHTR1 0xA2 +#define KS_MAHTR2 0xA4 +#define KS_MAHTR3 0xA6 + +#define KS_FCLWR 0xB0 +#define KS_FCHWR 0xB2 +#define KS_FCOWR 0xB4 + +#define KS_CIDER 0xC0 +#define CIDER_ID 0x8870 +#define CIDER_REV_MASK (0x7 << 1) +#define CIDER_REV_SHIFT (1) +#define CIDER_REV_GET(_v) (((_v) >> 1) & 0x7) + +#define KS_CGCR 0xC6 +#define KS_IACR 0xC8 +#define IACR_RDEN (1 << 12) +#define IACR_TSEL_MASK (0x3 << 10) +#define IACR_TSEL_SHIFT (10) +#define IACR_TSEL_MIB (0x3 << 10) +#define IACR_ADDR_MASK (0x1f << 0) +#define IACR_ADDR_SHIFT (0) + +#define KS_IADLR 0xD0 +#define KS_IAHDR 0xD2 + +#define KS_PMECR 0xD4 +#define PMECR_PME_DELAY (1 << 14) +#define PMECR_PME_POL (1 << 12) +#define PMECR_WOL_WAKEUP (1 << 11) +#define PMECR_WOL_MAGICPKT (1 << 10) +#define PMECR_WOL_LINKUP (1 << 9) +#define PMECR_WOL_ENERGY (1 << 8) +#define PMECR_AUTO_WAKE_EN (1 << 7) +#define PMECR_WAKEUP_NORMAL (1 << 6) +#define PMECR_WKEVT_MASK (0xf << 2) +#define PMECR_WKEVT_SHIFT (2) +#define PMECR_WKEVT_GET(_v) (((_v) >> 2) & 0xf) +#define PMECR_WKEVT_ENERGY (0x1 << 2) +#define PMECR_WKEVT_LINK (0x2 << 2) +#define PMECR_WKEVT_MAGICPKT (0x4 << 2) +#define PMECR_WKEVT_FRAME (0x8 << 2) +#define PMECR_PM_MASK (0x3 << 0) +#define PMECR_PM_SHIFT (0) +#define PMECR_PM_NORMAL (0x0 << 0) +#define PMECR_PM_ENERGY (0x1 << 0) +#define PMECR_PM_SOFTDOWN (0x2 << 0) +#define PMECR_PM_POWERSAVE (0x3 << 0) + +/* Standard MII PHY data */ +#define KS_P1MBCR 0xE4 +#define P1MBCR_FORCE_FDX (1 << 8) + +#define KS_P1MBSR 0xE6 +#define P1MBSR_AN_COMPLETE (1 << 5) +#define P1MBSR_AN_CAPABLE (1 << 3) +#define P1MBSR_LINK_UP (1 << 2) + +#define KS_PHY1ILR 0xE8 +#define KS_PHY1IHR 0xEA +#define KS_P1ANAR 0xEC +#define KS_P1ANLPR 0xEE + +#define KS_P1SCLMD 0xF4 +#define P1SCLMD_LEDOFF (1 << 15) +#define P1SCLMD_TXIDS (1 << 14) +#define P1SCLMD_RESTARTAN (1 << 13) +#define P1SCLMD_DISAUTOMDIX (1 << 10) +#define P1SCLMD_FORCEMDIX (1 << 9) +#define P1SCLMD_AUTONEGEN (1 << 7) +#define P1SCLMD_FORCE100 (1 << 6) +#define P1SCLMD_FORCEFDX (1 << 5) +#define P1SCLMD_ADV_FLOW (1 << 4) +#define P1SCLMD_ADV_100BT_FDX (1 << 3) +#define P1SCLMD_ADV_100BT_HDX (1 << 2) +#define P1SCLMD_ADV_10BT_FDX (1 << 1) +#define P1SCLMD_ADV_10BT_HDX (1 << 0) + +#define KS_P1CR 0xF6 +#define P1CR_HP_MDIX (1 << 15) +#define P1CR_REV_POL (1 << 13) +#define P1CR_OP_100M (1 << 10) +#define P1CR_OP_FDX (1 << 9) +#define P1CR_OP_MDI (1 << 7) +#define P1CR_AN_DONE (1 << 6) +#define P1CR_LINK_GOOD (1 << 5) +#define P1CR_PNTR_FLOW (1 << 4) +#define P1CR_PNTR_100BT_FDX (1 << 3) +#define P1CR_PNTR_100BT_HDX (1 << 2) +#define P1CR_PNTR_10BT_FDX (1 << 1) +#define P1CR_PNTR_10BT_HDX (1 << 0) + +/* TX Frame control */ +#define TXFR_TXIC (1 << 15) +#define TXFR_TXFID_MASK (0x3f << 0) +#define TXFR_TXFID_SHIFT (0) + +#define KS_P1SR 0xF8 +#define P1SR_HP_MDIX (1 << 15) +#define P1SR_REV_POL (1 << 13) +#define P1SR_OP_100M (1 << 10) +#define P1SR_OP_FDX (1 << 9) +#define P1SR_OP_MDI (1 << 7) +#define P1SR_AN_DONE (1 << 6) +#define P1SR_LINK_GOOD (1 << 5) +#define P1SR_PNTR_FLOW (1 << 4) +#define P1SR_PNTR_100BT_FDX (1 << 3) +#define P1SR_PNTR_100BT_HDX (1 << 2) +#define P1SR_PNTR_10BT_FDX (1 << 1) +#define P1SR_PNTR_10BT_HDX (1 << 0) + +#define ENUM_BUS_NONE 0 +#define ENUM_BUS_8BIT 1 +#define ENUM_BUS_16BIT 2 +#define ENUM_BUS_32BIT 3 + +#define MAX_MCAST_LST 32 +#define HW_MCAST_SIZE 8 +#define MAC_ADDR_LEN 6 + +/* Chip ID values */ +struct chip_id { + u16 id; + char *name; +}; + +#endif diff --git a/sources/uboot-be550/drivers/net/lan91c96.c b/sources/uboot-be550/drivers/net/lan91c96.c new file mode 100644 index 00000000..c4dd01ec --- /dev/null +++ b/sources/uboot-be550/drivers/net/lan91c96.c @@ -0,0 +1,798 @@ +/*------------------------------------------------------------------------ + * lan91c96.c + * This is a driver for SMSC's LAN91C96 single-chip Ethernet device, based + * on the SMC91111 driver from U-boot. + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Rolf Offermanns + * + * Copyright (C) 2001 Standard Microsystems Corporation (SMSC) + * Developed by Simple Network Magic Corporation (SNMC) + * Copyright (C) 1996 by Erik Stahlman (ES) + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Information contained in this file was obtained from the LAN91C96 + * manual from SMC. To get a copy, if you really want one, you can find + * information under www.smsc.com. + * + * "Features" of the SMC chip: + * 6144 byte packet memory. ( for the 91C96 ) + * EEPROM for configuration + * AUI/TP selection ( mine has 10Base2/10BaseT select ) + * + * Arguments: + * io = for the base address + * irq = for the IRQ + * + * author: + * Erik Stahlman ( erik@vt.edu ) + * Daris A Nevil ( dnevil@snmc.com ) + * + * + * Hardware multicast code from Peter Cammaert ( pc@denkart.be ) + * + * Sources: + * o SMSC LAN91C96 databook (www.smsc.com) + * o smc91111.c (u-boot driver) + * o smc9194.c (linux kernel driver) + * o lan91c96.c (Intel Diagnostic Manager driver) + * + * History: + * 04/30/03 Mathijs Haarman Modified smc91111.c (u-boot version) + * for lan91c96 + *--------------------------------------------------------------------------- + */ + +#include +#include +#include +#include "lan91c96.h" +#include +#include + +/*------------------------------------------------------------------------ + * + * Configuration options, for the experienced user to change. + * + -------------------------------------------------------------------------*/ + +/* Use power-down feature of the chip */ +#define POWER_DOWN 0 + +/* + * Wait time for memory to be free. This probably shouldn't be + * tuned that much, as waiting for this means nothing else happens + * in the system +*/ +#define MEMORY_WAIT_TIME 16 + +#define SMC_DEBUG 0 + +#if (SMC_DEBUG > 2 ) +#define PRINTK3(args...) printf(args) +#else +#define PRINTK3(args...) +#endif + +#if SMC_DEBUG > 1 +#define PRINTK2(args...) printf(args) +#else +#define PRINTK2(args...) +#endif + +#ifdef SMC_DEBUG +#define PRINTK(args...) printf(args) +#else +#define PRINTK(args...) +#endif + + +/*------------------------------------------------------------------------ + * + * The internal workings of the driver. If you are changing anything + * here with the SMC stuff, you should have the datasheet and know + * what you are doing. + * + *------------------------------------------------------------------------ + */ +#define DRIVER_NAME "LAN91C96" +#define SMC_ALLOC_MAX_TRY 5 +#define SMC_TX_TIMEOUT 30 + +#define ETH_ZLEN 60 + +#ifdef CONFIG_LAN91C96_USE_32_BIT +#define USE_32_BIT 1 +#else +#undef USE_32_BIT +#endif + +/* See if a MAC address is defined in the current environment. If so use it. If not + . print a warning and set the environment and other globals with the default. + . If an EEPROM is present it really should be consulted. +*/ +static int smc_get_ethaddr(bd_t *bd, struct eth_device *dev); +static int get_rom_mac(struct eth_device *dev, unsigned char *v_rom_mac); + +/* ------------------------------------------------------------ + * Internal routines + * ------------------------------------------------------------ + */ + +static unsigned char smc_mac_addr[] = { 0xc0, 0x00, 0x00, 0x1b, 0x62, 0x9c }; + +/* + * This function must be called before smc_open() if you want to override + * the default mac address. + */ + +static void smc_set_mac_addr(const unsigned char *addr) +{ + int i; + + for (i = 0; i < sizeof (smc_mac_addr); i++) { + smc_mac_addr[i] = addr[i]; + } +} + +/*********************************************** + * Show available memory * + ***********************************************/ +void dump_memory_info(struct eth_device *dev) +{ + __maybe_unused word mem_info; + word old_bank; + + old_bank = SMC_inw(dev, LAN91C96_BANK_SELECT) & 0xF; + + SMC_SELECT_BANK(dev, 0); + mem_info = SMC_inw(dev, LAN91C96_MIR); + PRINTK2 ("Memory: %4d available\n", (mem_info >> 8) * 2048); + + SMC_SELECT_BANK(dev, old_bank); +} + +/* + * A rather simple routine to print out a packet for debugging purposes. + */ +#if SMC_DEBUG > 2 +static void print_packet (byte *, int); +#endif + +static int poll4int (struct eth_device *dev, byte mask, int timeout) +{ + int tmo = get_timer (0) + timeout * CONFIG_SYS_HZ; + int is_timeout = 0; + word old_bank = SMC_inw(dev, LAN91C96_BANK_SELECT); + + PRINTK2 ("Polling...\n"); + SMC_SELECT_BANK(dev, 2); + while ((SMC_inw(dev, LAN91C96_INT_STATS) & mask) == 0) { + if (get_timer (0) >= tmo) { + is_timeout = 1; + break; + } + } + + /* restore old bank selection */ + SMC_SELECT_BANK(dev, old_bank); + + if (is_timeout) + return 1; + else + return 0; +} + +/* + * Function: smc_reset + * Purpose: + * This sets the SMC91111 chip to its normal state, hopefully from whatever + * mess that any other DOS driver has put it in. + * + * Maybe I should reset more registers to defaults in here? SOFTRST should + * do that for me. + * + * Method: + * 1. send a SOFT RESET + * 2. wait for it to finish + * 3. enable autorelease mode + * 4. reset the memory management unit + * 5. clear all interrupts + * +*/ +static void smc_reset(struct eth_device *dev) +{ + PRINTK2("%s:smc_reset\n", dev->name); + + /* This resets the registers mostly to defaults, but doesn't + affect EEPROM. That seems unnecessary */ + SMC_SELECT_BANK(dev, 0); + SMC_outw(dev, LAN91C96_RCR_SOFT_RST, LAN91C96_RCR); + + udelay (10); + + /* Disable transmit and receive functionality */ + SMC_outw(dev, 0, LAN91C96_RCR); + SMC_outw(dev, 0, LAN91C96_TCR); + + /* set the control register */ + SMC_SELECT_BANK(dev, 1); + SMC_outw(dev, SMC_inw(dev, LAN91C96_CONTROL) | LAN91C96_CTR_BIT_8, + LAN91C96_CONTROL); + + /* Disable all interrupts */ + SMC_outb(dev, 0, LAN91C96_INT_MASK); +} + +/* + * Function: smc_enable + * Purpose: let the chip talk to the outside work + * Method: + * 1. Initialize the Memory Configuration Register + * 2. Enable the transmitter + * 3. Enable the receiver +*/ +static void smc_enable(struct eth_device *dev) +{ + PRINTK2("%s:smc_enable\n", dev->name); + SMC_SELECT_BANK(dev, 0); + + /* Initialize the Memory Configuration Register. See page + 49 of the LAN91C96 data sheet for details. */ + SMC_outw(dev, LAN91C96_MCR_TRANSMIT_PAGES, LAN91C96_MCR); + + /* Initialize the Transmit Control Register */ + SMC_outw(dev, LAN91C96_TCR_TXENA, LAN91C96_TCR); + /* Initialize the Receive Control Register + * FIXME: + * The promiscuous bit set because I could not receive ARP reply + * packets from the server when I send a ARP request. It only works + * when I set the promiscuous bit + */ + SMC_outw(dev, LAN91C96_RCR_RXEN | LAN91C96_RCR_PRMS, LAN91C96_RCR); +} + +/* + * Function: smc_shutdown + * Purpose: closes down the SMC91xxx chip. + * Method: + * 1. zero the interrupt mask + * 2. clear the enable receive flag + * 3. clear the enable xmit flags + * + * TODO: + * (1) maybe utilize power down mode. + * Why not yet? Because while the chip will go into power down mode, + * the manual says that it will wake up in response to any I/O requests + * in the register space. Empirical results do not show this working. + */ +static void smc_shutdown(struct eth_device *dev) +{ + PRINTK2("%s:smc_shutdown\n", dev->name); + + /* no more interrupts for me */ + SMC_SELECT_BANK(dev, 2); + SMC_outb(dev, 0, LAN91C96_INT_MASK); + + /* and tell the card to stay away from that nasty outside world */ + SMC_SELECT_BANK(dev, 0); + SMC_outb(dev, 0, LAN91C96_RCR); + SMC_outb(dev, 0, LAN91C96_TCR); +} + + +/* + * Function: smc_hardware_send_packet(struct net_device * ) + * Purpose: + * This sends the actual packet to the SMC9xxx chip. + * + * Algorithm: + * First, see if a saved_skb is available. + * ( this should NOT be called if there is no 'saved_skb' + * Now, find the packet number that the chip allocated + * Point the data pointers at it in memory + * Set the length word in the chip's memory + * Dump the packet to chip memory + * Check if a last byte is needed ( odd length packet ) + * if so, set the control flag right + * Tell the card to send it + * Enable the transmit interrupt, so I know if it failed + * Free the kernel data if I actually sent it. + */ +static int smc_send_packet(struct eth_device *dev, void *packet, + int packet_length) +{ + byte packet_no; + byte *buf; + int length; + int numPages; + int try = 0; + int time_out; + byte status; + + + PRINTK3("%s:smc_hardware_send_packet\n", dev->name); + + length = ETH_ZLEN < packet_length ? packet_length : ETH_ZLEN; + + /* allocate memory + ** The MMU wants the number of pages to be the number of 256 bytes + ** 'pages', minus 1 ( since a packet can't ever have 0 pages :) ) + ** + ** The 91C111 ignores the size bits, but the code is left intact + ** for backwards and future compatibility. + ** + ** Pkt size for allocating is data length +6 (for additional status + ** words, length and ctl!) + ** + ** If odd size then last byte is included in this header. + */ + numPages = ((length & 0xfffe) + 6); + numPages >>= 8; /* Divide by 256 */ + + if (numPages > 7) { + printf("%s: Far too big packet error. \n", dev->name); + return 0; + } + + /* now, try to allocate the memory */ + + SMC_SELECT_BANK(dev, 2); + SMC_outw(dev, LAN91C96_MMUCR_ALLOC_TX | numPages, LAN91C96_MMU); + + again: + try++; + time_out = MEMORY_WAIT_TIME; + do { + status = SMC_inb(dev, LAN91C96_INT_STATS); + if (status & LAN91C96_IST_ALLOC_INT) { + + SMC_outb(dev, LAN91C96_IST_ALLOC_INT, + LAN91C96_INT_STATS); + break; + } + } while (--time_out); + + if (!time_out) { + PRINTK2 ("%s: memory allocation, try %d failed ...\n", + dev->name, try); + if (try < SMC_ALLOC_MAX_TRY) + goto again; + else + return 0; + } + + PRINTK2 ("%s: memory allocation, try %d succeeded ...\n", + dev->name, try); + + /* I can send the packet now.. */ + buf = (byte *) packet; + + /* If I get here, I _know_ there is a packet slot waiting for me */ + packet_no = SMC_inb(dev, LAN91C96_ARR); + if (packet_no & LAN91C96_ARR_FAILED) { + /* or isn't there? BAD CHIP! */ + printf("%s: Memory allocation failed. \n", dev->name); + return 0; + } + + /* we have a packet address, so tell the card to use it */ + SMC_outb(dev, packet_no, LAN91C96_PNR); + + /* point to the beginning of the packet */ + SMC_outw(dev, LAN91C96_PTR_AUTO_INCR, LAN91C96_POINTER); + + PRINTK3("%s: Trying to xmit packet of length %x\n", + dev->name, length); + +#if SMC_DEBUG > 2 + printf ("Transmitting Packet\n"); + print_packet (buf, length); +#endif + + /* send the packet length ( +6 for status, length and ctl byte ) + and the status word ( set to zeros ) */ +#ifdef USE_32_BIT + SMC_outl(dev, (length + 6) << 16, LAN91C96_DATA_HIGH); +#else + SMC_outw(dev, 0, LAN91C96_DATA_HIGH); + /* send the packet length ( +6 for status words, length, and ctl */ + SMC_outw(dev, (length + 6), LAN91C96_DATA_HIGH); +#endif /* USE_32_BIT */ + + /* send the actual data + * I _think_ it's faster to send the longs first, and then + * mop up by sending the last word. It depends heavily + * on alignment, at least on the 486. Maybe it would be + * a good idea to check which is optimal? But that could take + * almost as much time as is saved? + */ +#ifdef USE_32_BIT + SMC_outsl(dev, LAN91C96_DATA_HIGH, buf, length >> 2); + if (length & 0x2) + SMC_outw(dev, *((word *) (buf + (length & 0xFFFFFFFC))), + LAN91C96_DATA_HIGH); +#else + SMC_outsw(dev, LAN91C96_DATA_HIGH, buf, (length) >> 1); +#endif /* USE_32_BIT */ + + /* Send the last byte, if there is one. */ + if ((length & 1) == 0) { + SMC_outw(dev, 0, LAN91C96_DATA_HIGH); + } else { + SMC_outw(dev, buf[length - 1] | 0x2000, LAN91C96_DATA_HIGH); + } + + /* and let the chipset deal with it */ + SMC_outw(dev, LAN91C96_MMUCR_ENQUEUE, LAN91C96_MMU); + + /* poll for TX INT */ + if (poll4int (dev, LAN91C96_MSK_TX_INT, SMC_TX_TIMEOUT)) { + /* sending failed */ + PRINTK2("%s: TX timeout, sending failed...\n", dev->name); + + /* release packet */ + SMC_outw(dev, LAN91C96_MMUCR_RELEASE_TX, LAN91C96_MMU); + + /* wait for MMU getting ready (low) */ + while (SMC_inw(dev, LAN91C96_MMU) & LAN91C96_MMUCR_NO_BUSY) + udelay (10); + + PRINTK2("MMU ready\n"); + + + return 0; + } else { + /* ack. int */ + SMC_outw(dev, LAN91C96_IST_TX_INT, LAN91C96_INT_STATS); + + PRINTK2("%s: Sent packet of length %d \n", dev->name, length); + + /* release packet */ + SMC_outw(dev, LAN91C96_MMUCR_RELEASE_TX, LAN91C96_MMU); + + /* wait for MMU getting ready (low) */ + while (SMC_inw(dev, LAN91C96_MMU) & LAN91C96_MMUCR_NO_BUSY) + udelay (10); + + PRINTK2 ("MMU ready\n"); + } + + return length; +} + + +/* + * Open and Initialize the board + * + * Set up everything, reset the card, etc .. + * + */ +static int smc_open(bd_t *bd, struct eth_device *dev) +{ + int i, err; /* used to set hw ethernet address */ + + PRINTK2("%s:smc_open\n", dev->name); + + /* reset the hardware */ + + smc_reset(dev); + smc_enable(dev); + + SMC_SELECT_BANK(dev, 1); + /* set smc_mac_addr, and sync it with u-boot globals */ + err = smc_get_ethaddr(bd, dev); + if (err < 0) + return -1; +#ifdef USE_32_BIT + for (i = 0; i < 6; i += 2) { + word address; + + address = smc_mac_addr[i + 1] << 8; + address |= smc_mac_addr[i]; + SMC_outw(dev, address, LAN91C96_IA0 + i); + } +#else + for (i = 0; i < 6; i++) + SMC_outb(dev, smc_mac_addr[i], LAN91C96_IA0 + i); +#endif + return 0; +} + +/*------------------------------------------------------------- + * + * smc_rcv - receive a packet from the card + * + * There is ( at least ) a packet waiting to be read from + * chip-memory. + * + * o Read the status + * o If an error, record it + * o otherwise, read in the packet + *------------------------------------------------------------- + */ +static int smc_rcv(struct eth_device *dev) +{ + int packet_number; + word status; + word packet_length; + int is_error = 0; + +#ifdef USE_32_BIT + dword stat_len; +#endif + + + SMC_SELECT_BANK(dev, 2); + packet_number = SMC_inw(dev, LAN91C96_FIFO); + + if (packet_number & LAN91C96_FIFO_RXEMPTY) { + return 0; + } + + PRINTK3("%s:smc_rcv\n", dev->name); + /* start reading from the start of the packet */ + SMC_outw(dev, LAN91C96_PTR_READ | LAN91C96_PTR_RCV | + LAN91C96_PTR_AUTO_INCR, LAN91C96_POINTER); + + /* First two words are status and packet_length */ +#ifdef USE_32_BIT + stat_len = SMC_inl(dev, LAN91C96_DATA_HIGH); + status = stat_len & 0xffff; + packet_length = stat_len >> 16; +#else + status = SMC_inw(dev, LAN91C96_DATA_HIGH); + packet_length = SMC_inw(dev, LAN91C96_DATA_HIGH); +#endif + + packet_length &= 0x07ff; /* mask off top bits */ + + PRINTK2 ("RCV: STATUS %4x LENGTH %4x\n", status, packet_length); + + if (!(status & FRAME_FILTER)) { + /* Adjust for having already read the first two words */ + packet_length -= 4; /*4; */ + + + /* set odd length for bug in LAN91C111, */ + /* which never sets RS_ODDFRAME */ + /* TODO ? */ + + +#ifdef USE_32_BIT + PRINTK3 (" Reading %d dwords (and %d bytes) \n", + packet_length >> 2, packet_length & 3); + /* QUESTION: Like in the TX routine, do I want + to send the DWORDs or the bytes first, or some + mixture. A mixture might improve already slow PIO + performance */ + SMC_insl(dev, LAN91C96_DATA_HIGH, net_rx_packets[0], + packet_length >> 2); + /* read the left over bytes */ + if (packet_length & 3) { + int i; + + byte *tail = (byte *)(net_rx_packets[0] + + (packet_length & ~3)); + dword leftover = SMC_inl(dev, LAN91C96_DATA_HIGH); + + for (i = 0; i < (packet_length & 3); i++) + *tail++ = (byte) (leftover >> (8 * i)) & 0xff; + } +#else + PRINTK3(" Reading %d words and %d byte(s)\n", + (packet_length >> 1), packet_length & 1); + SMC_insw(dev, LAN91C96_DATA_HIGH, net_rx_packets[0], + packet_length >> 1); + +#endif /* USE_32_BIT */ + +#if SMC_DEBUG > 2 + printf ("Receiving Packet\n"); + print_packet((byte *)net_rx_packets[0], packet_length); +#endif + } else { + /* error ... */ + /* TODO ? */ + is_error = 1; + } + + while (SMC_inw(dev, LAN91C96_MMU) & LAN91C96_MMUCR_NO_BUSY) + udelay (1); /* Wait until not busy */ + + /* error or good, tell the card to get rid of this packet */ + SMC_outw(dev, LAN91C96_MMUCR_RELEASE_RX, LAN91C96_MMU); + + while (SMC_inw(dev, LAN91C96_MMU) & LAN91C96_MMUCR_NO_BUSY) + udelay (1); /* Wait until not busy */ + + if (!is_error) { + /* Pass the packet up to the protocol layers. */ + net_process_received_packet(net_rx_packets[0], packet_length); + return packet_length; + } else { + return 0; + } + +} + +/*---------------------------------------------------- + * smc_close + * + * this makes the board clean up everything that it can + * and not talk to the outside world. Caused by + * an 'ifconfig ethX down' + * + -----------------------------------------------------*/ +static int smc_close(struct eth_device *dev) +{ + PRINTK2("%s:smc_close\n", dev->name); + + /* clear everything */ + smc_shutdown(dev); + + return 0; +} + +#if SMC_DEBUG > 2 +static void print_packet(byte *buf, int length) +{ +#if 0 + int i; + int remainder; + int lines; + + printf ("Packet of length %d \n", length); + + lines = length / 16; + remainder = length % 16; + + for (i = 0; i < lines; i++) { + int cur; + + for (cur = 0; cur < 8; cur++) { + byte a, b; + + a = *(buf++); + b = *(buf++); + printf ("%02x%02x ", a, b); + } + printf ("\n"); + } + for (i = 0; i < remainder / 2; i++) { + byte a, b; + + a = *(buf++); + b = *(buf++); + printf ("%02x%02x ", a, b); + } + printf ("\n"); +#endif /* 0 */ +} +#endif /* SMC_DEBUG > 2 */ + +static int lan91c96_init(struct eth_device *dev, bd_t *bd) +{ + return smc_open(bd, dev); +} + +static void lan91c96_halt(struct eth_device *dev) +{ + smc_close(dev); +} + +static int lan91c96_recv(struct eth_device *dev) +{ + return smc_rcv(dev); +} + +static int lan91c96_send(struct eth_device *dev, void *packet, + int length) +{ + return smc_send_packet(dev, packet, length); +} + +/* smc_get_ethaddr + * + * This checks both the environment and the ROM for an ethernet address. If + * found, the environment takes precedence. + */ + +static int smc_get_ethaddr(bd_t *bd, struct eth_device *dev) +{ + uchar v_mac[6]; + + if (!eth_getenv_enetaddr("ethaddr", v_mac)) { + /* get ROM mac value if any */ + if (!get_rom_mac(dev, v_mac)) { + printf("\n*** ERROR: ethaddr is NOT set !!\n"); + return -1; + } + eth_setenv_enetaddr("ethaddr", v_mac); + } + + smc_set_mac_addr(v_mac); /* use old function to update smc default */ + PRINTK("Using MAC Address %pM\n", v_mac); + return 0; +} + +/* + * get_rom_mac() + * Note, this has omly been tested for the OMAP730 P2. + */ + +static int get_rom_mac(struct eth_device *dev, unsigned char *v_rom_mac) +{ + int i; + SMC_SELECT_BANK(dev, 1); + for (i=0; i<6; i++) + { + v_rom_mac[i] = SMC_inb(dev, LAN91C96_IA0 + i); + } + return (1); +} + +/* Structure to detect the device IDs */ +struct id_type { + u8 id; + char *name; +}; +static struct id_type supported_chips[] = { + {0, ""}, /* Dummy entry to prevent id check failure */ + {9, "LAN91C110"}, + {8, "LAN91C100FD"}, + {7, "LAN91C100"}, + {5, "LAN91C95"}, + {4, "LAN91C94/96"}, + {3, "LAN91C90/92"}, +}; +/* lan91c96_detect_chip + * See: + * http://www.embeddedsys.com/subpages/resources/images/documents/LAN91C96_datasheet.pdf + * page 71 - that is the closest we get to detect this device + */ +static int lan91c96_detect_chip(struct eth_device *dev) +{ + u8 chip_id; + int r; + SMC_SELECT_BANK(dev, 3); + chip_id = (SMC_inw(dev, 0xA) & LAN91C96_REV_CHIPID) >> 4; + SMC_SELECT_BANK(dev, 0); + for (r = 0; r < ARRAY_SIZE(supported_chips); r++) + if (chip_id == supported_chips[r].id) + return r; + return 0; +} + +int lan91c96_initialize(u8 dev_num, int base_addr) +{ + struct eth_device *dev; + int r = 0; + + dev = malloc(sizeof(*dev)); + if (!dev) { + return 0; + } + memset(dev, 0, sizeof(*dev)); + + dev->iobase = base_addr; + + /* Try to detect chip. Will fail if not present. */ + r = lan91c96_detect_chip(dev); + if (!r) { + free(dev); + return 0; + } + get_rom_mac(dev, dev->enetaddr); + + dev->init = lan91c96_init; + dev->halt = lan91c96_halt; + dev->send = lan91c96_send; + dev->recv = lan91c96_recv; + sprintf(dev->name, "%s-%hu", supported_chips[r].name, dev_num); + + eth_register(dev); + return 0; +} diff --git a/sources/uboot-be550/drivers/net/lan91c96.h b/sources/uboot-be550/drivers/net/lan91c96.h new file mode 100644 index 00000000..3e914ce5 --- /dev/null +++ b/sources/uboot-be550/drivers/net/lan91c96.h @@ -0,0 +1,617 @@ +/*------------------------------------------------------------------------ + * lan91c96.h + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Rolf Offermanns + * Copyright (C) 2001 Standard Microsystems Corporation (SMSC) + * Developed by Simple Network Magic Corporation (SNMC) + * Copyright (C) 1996 by Erik Stahlman (ES) + * + * SPDX-License-Identifier: GPL-2.0+ + * + * This file contains register information and access macros for + * the LAN91C96 single chip ethernet controller. It is a modified + * version of the smc9111.h file. + * + * Information contained in this file was obtained from the LAN91C96 + * manual from SMC. To get a copy, if you really want one, you can find + * information under www.smsc.com. + * + * Authors + * Erik Stahlman ( erik@vt.edu ) + * Daris A Nevil ( dnevil@snmc.com ) + * + * History + * 04/30/03 Mathijs Haarman Modified smc91111.h (u-boot version) + * for lan91c96 + *------------------------------------------------------------------------- + */ +#ifndef _LAN91C96_H_ +#define _LAN91C96_H_ + +#include +#include +#include + +/* I want some simple types */ + +typedef unsigned char byte; +typedef unsigned short word; +typedef unsigned long int dword; + +/* + * DEBUGGING LEVELS + * + * 0 for normal operation + * 1 for slightly more details + * >2 for various levels of increasingly useless information + * 2 for interrupt tracking, status flags + * 3 for packet info + * 4 for complete packet dumps + */ +/*#define SMC_DEBUG 0 */ + +/* Because of bank switching, the LAN91xxx uses only 16 I/O ports */ + +#define SMC_IO_EXTENT 16 + +#ifdef CONFIG_CPU_PXA25X + +#define SMC_IO_SHIFT 0 + +#define SMCREG(edev, r) ((edev)->iobase+((r)<>= 8; \ + else __v &= 0xff; \ + __v; }) + +#define SMC_outl(edev, d, r) (*((volatile dword *)SMCREG(edev, r)) = d) +#define SMC_outw(edev, d, r) (*((volatile word *)SMCREG(edev, r)) = d) +#define SMC_outb(edev, d, r) ({ word __d = (byte)(d); \ + word __w = SMC_inw(edev, (r)&~1); \ + __w &= ((r)&1) ? 0x00FF : 0xFF00; \ + __w |= ((r)&1) ? __d<<8 : __d; \ + SMC_outw(edev, __w, (r)&~1); \ + }) + +#define SMC_outsl(edev, r, b, l) ({ int __i; \ + dword *__b2; \ + __b2 = (dword *) b; \ + for (__i = 0; __i < l; __i++) { \ + SMC_outl(edev, *(__b2 + __i),\ + r); \ + } \ + }) + +#define SMC_outsw(edev, r, b, l) ({ int __i; \ + word *__b2; \ + __b2 = (word *) b; \ + for (__i = 0; __i < l; __i++) { \ + SMC_outw(edev, *(__b2 + __i),\ + r); \ + } \ + }) + +#define SMC_insl(edev, r, b, l) ({ int __i ; \ + dword *__b2; \ + __b2 = (dword *) b; \ + for (__i = 0; __i < l; __i++) { \ + *(__b2 + __i) = SMC_inl(edev,\ + r); \ + SMC_inl(edev, 0); \ + }; \ + }) + +#define SMC_insw(edev, r, b, l) ({ int __i ; \ + word *__b2; \ + __b2 = (word *) b; \ + for (__i = 0; __i < l; __i++) { \ + *(__b2 + __i) = SMC_inw(edev,\ + r); \ + SMC_inw(edev, 0); \ + }; \ + }) + +#define SMC_insb(edev, r, b, l) ({ int __i ; \ + byte *__b2; \ + __b2 = (byte *) b; \ + for (__i = 0; __i < l; __i++) { \ + *(__b2 + __i) = SMC_inb(edev,\ + r); \ + SMC_inb(edev, 0); \ + }; \ + }) + +#else /* if not CONFIG_CPU_PXA25X */ + +/* + * We have only 16 Bit PCMCIA access on Socket 0 + */ + +#define SMC_inw(edev, r) (*((volatile word *)((edev)->iobase+(r)))) +#define SMC_inb(edev, r) (((r)&1) ? SMC_inw(edev, (r)&~1)>>8 :\ + SMC_inw(edev, r)&0xFF) + +#define SMC_outw(edev, d, r) (*((volatile word *)((edev)->iobase+(r))) = d) +#define SMC_outb(edev, d, r) ({ word __d = (byte)(d); \ + word __w = SMC_inw(edev, (r)&~1); \ + __w &= ((r)&1) ? 0x00FF : 0xFF00; \ + __w |= ((r)&1) ? __d<<8 : __d; \ + SMC_outw(edev, __w, (r)&~1); \ + }) +#define SMC_outsw(edev, r, b, l) ({ int __i; \ + word *__b2; \ + __b2 = (word *) b; \ + for (__i = 0; __i < l; __i++) { \ + SMC_outw(edev, *(__b2 + __i),\ + r); \ + } \ + }) + +#define SMC_insw(edev, r, b, l) ({ int __i ; \ + word *__b2; \ + __b2 = (word *) b; \ + for (__i = 0; __i < l; __i++) { \ + *(__b2 + __i) = SMC_inw(edev,\ + r); \ + SMC_inw(edev, 0); \ + }; \ + }) + +#endif + +/* + **************************************************************************** + * Bank Select Field + **************************************************************************** + */ +#define LAN91C96_BANK_SELECT 14 /* Bank Select Register */ +#define LAN91C96_BANKSELECT (0x3UC << 0) +#define BANK0 0x00 +#define BANK1 0x01 +#define BANK2 0x02 +#define BANK3 0x03 +#define BANK4 0x04 + +/* + **************************************************************************** + * EEPROM Addresses. + **************************************************************************** + */ +#define EEPROM_MAC_OFFSET_1 0x6020 +#define EEPROM_MAC_OFFSET_2 0x6021 +#define EEPROM_MAC_OFFSET_3 0x6022 + +/* + **************************************************************************** + * Bank 0 Register Map in I/O Space + **************************************************************************** + */ +#define LAN91C96_TCR 0 /* Transmit Control Register */ +#define LAN91C96_EPH_STATUS 2 /* EPH Status Register */ +#define LAN91C96_RCR 4 /* Receive Control Register */ +#define LAN91C96_COUNTER 6 /* Counter Register */ +#define LAN91C96_MIR 8 /* Memory Information Register */ +#define LAN91C96_MCR 10 /* Memory Configuration Register */ + +/* + **************************************************************************** + * Transmit Control Register - Bank 0 - Offset 0 + **************************************************************************** + */ +#define LAN91C96_TCR_TXENA (0x1U << 0) +#define LAN91C96_TCR_LOOP (0x1U << 1) +#define LAN91C96_TCR_FORCOL (0x1U << 2) +#define LAN91C96_TCR_TXP_EN (0x1U << 3) +#define LAN91C96_TCR_PAD_EN (0x1U << 7) +#define LAN91C96_TCR_NOCRC (0x1U << 8) +#define LAN91C96_TCR_MON_CSN (0x1U << 10) +#define LAN91C96_TCR_FDUPLX (0x1U << 11) +#define LAN91C96_TCR_STP_SQET (0x1U << 12) +#define LAN91C96_TCR_EPH_LOOP (0x1U << 13) +#define LAN91C96_TCR_ETEN_TYPE (0x1U << 14) +#define LAN91C96_TCR_FDSE (0x1U << 15) + +/* + **************************************************************************** + * EPH Status Register - Bank 0 - Offset 2 + **************************************************************************** + */ +#define LAN91C96_EPHSR_TX_SUC (0x1U << 0) +#define LAN91C96_EPHSR_SNGL_COL (0x1U << 1) +#define LAN91C96_EPHSR_MUL_COL (0x1U << 2) +#define LAN91C96_EPHSR_LTX_MULT (0x1U << 3) +#define LAN91C96_EPHSR_16COL (0x1U << 4) +#define LAN91C96_EPHSR_SQET (0x1U << 5) +#define LAN91C96_EPHSR_LTX_BRD (0x1U << 6) +#define LAN91C96_EPHSR_TX_DEFR (0x1U << 7) +#define LAN91C96_EPHSR_WAKEUP (0x1U << 8) +#define LAN91C96_EPHSR_LATCOL (0x1U << 9) +#define LAN91C96_EPHSR_LOST_CARR (0x1U << 10) +#define LAN91C96_EPHSR_EXC_DEF (0x1U << 11) +#define LAN91C96_EPHSR_CTR_ROL (0x1U << 12) + +#define LAN91C96_EPHSR_LINK_OK (0x1U << 14) +#define LAN91C96_EPHSR_TX_UNRN (0x1U << 15) + +#define LAN91C96_EPHSR_ERRORS (LAN91C96_EPHSR_SNGL_COL | \ + LAN91C96_EPHSR_MUL_COL | \ + LAN91C96_EPHSR_16COL | \ + LAN91C96_EPHSR_SQET | \ + LAN91C96_EPHSR_TX_DEFR | \ + LAN91C96_EPHSR_LATCOL | \ + LAN91C96_EPHSR_LOST_CARR | \ + LAN91C96_EPHSR_EXC_DEF | \ + LAN91C96_EPHSR_LINK_OK | \ + LAN91C96_EPHSR_TX_UNRN) + +/* + **************************************************************************** + * Receive Control Register - Bank 0 - Offset 4 + **************************************************************************** + */ +#define LAN91C96_RCR_RX_ABORT (0x1U << 0) +#define LAN91C96_RCR_PRMS (0x1U << 1) +#define LAN91C96_RCR_ALMUL (0x1U << 2) +#define LAN91C96_RCR_RXEN (0x1U << 8) +#define LAN91C96_RCR_STRIP_CRC (0x1U << 9) +#define LAN91C96_RCR_FILT_CAR (0x1U << 14) +#define LAN91C96_RCR_SOFT_RST (0x1U << 15) + +/* + **************************************************************************** + * Counter Register - Bank 0 - Offset 6 + **************************************************************************** + */ +#define LAN91C96_ECR_SNGL_COL (0xFU << 0) +#define LAN91C96_ECR_MULT_COL (0xFU << 5) +#define LAN91C96_ECR_DEF_TX (0xFU << 8) +#define LAN91C96_ECR_EXC_DEF_TX (0xFU << 12) + +/* + **************************************************************************** + * Memory Information Register - Bank 0 - OFfset 8 + **************************************************************************** + */ +#define LAN91C96_MIR_SIZE (0x18 << 0) /* 6144 bytes */ + +/* + **************************************************************************** + * Memory Configuration Register - Bank 0 - Offset 10 + **************************************************************************** + */ +#define LAN91C96_MCR_MEM_RES (0xFFU << 0) +#define LAN91C96_MCR_MEM_MULT (0x3U << 9) +#define LAN91C96_MCR_HIGH_ID (0x3U << 12) + +#define LAN91C96_MCR_TRANSMIT_PAGES 0x6 + +/* + **************************************************************************** + * Bank 1 Register Map in I/O Space + **************************************************************************** + */ +#define LAN91C96_CONFIG 0 /* Configuration Register */ +#define LAN91C96_BASE 2 /* Base Address Register */ +#define LAN91C96_IA0 4 /* Individual Address Register - 0 */ +#define LAN91C96_IA1 5 /* Individual Address Register - 1 */ +#define LAN91C96_IA2 6 /* Individual Address Register - 2 */ +#define LAN91C96_IA3 7 /* Individual Address Register - 3 */ +#define LAN91C96_IA4 8 /* Individual Address Register - 4 */ +#define LAN91C96_IA5 9 /* Individual Address Register - 5 */ +#define LAN91C96_GEN_PURPOSE 10 /* General Address Registers */ +#define LAN91C96_CONTROL 12 /* Control Register */ + +/* + **************************************************************************** + * Configuration Register - Bank 1 - Offset 0 + **************************************************************************** + */ +#define LAN91C96_CR_INT_SEL0 (0x1U << 1) +#define LAN91C96_CR_INT_SEL1 (0x1U << 2) +#define LAN91C96_CR_RES (0x3U << 3) +#define LAN91C96_CR_DIS_LINK (0x1U << 6) +#define LAN91C96_CR_16BIT (0x1U << 7) +#define LAN91C96_CR_AUI_SELECT (0x1U << 8) +#define LAN91C96_CR_SET_SQLCH (0x1U << 9) +#define LAN91C96_CR_FULL_STEP (0x1U << 10) +#define LAN91C96_CR_NO_WAIT (0x1U << 12) + +/* + **************************************************************************** + * Base Address Register - Bank 1 - Offset 2 + **************************************************************************** + */ +#define LAN91C96_BAR_RA_BITS (0x27U << 0) +#define LAN91C96_BAR_ROM_SIZE (0x1U << 6) +#define LAN91C96_BAR_A_BITS (0xFFU << 8) + +/* + **************************************************************************** + * Control Register - Bank 1 - Offset 12 + **************************************************************************** + */ +#define LAN91C96_CTR_STORE (0x1U << 0) +#define LAN91C96_CTR_RELOAD (0x1U << 1) +#define LAN91C96_CTR_EEPROM (0x1U << 2) +#define LAN91C96_CTR_TE_ENABLE (0x1U << 5) +#define LAN91C96_CTR_CR_ENABLE (0x1U << 6) +#define LAN91C96_CTR_LE_ENABLE (0x1U << 7) +#define LAN91C96_CTR_BIT_8 (0x1U << 8) +#define LAN91C96_CTR_AUTO_RELEASE (0x1U << 11) +#define LAN91C96_CTR_WAKEUP_EN (0x1U << 12) +#define LAN91C96_CTR_PWRDN (0x1U << 13) +#define LAN91C96_CTR_RCV_BAD (0x1U << 14) + +/* + **************************************************************************** + * Bank 2 Register Map in I/O Space + **************************************************************************** + */ +#define LAN91C96_MMU 0 /* MMU Command Register */ +#define LAN91C96_AUTO_TX_START 1 /* Auto Tx Start Register */ +#define LAN91C96_PNR 2 /* Packet Number Register */ +#define LAN91C96_ARR 3 /* Allocation Result Register */ +#define LAN91C96_FIFO 4 /* FIFO Ports Register */ +#define LAN91C96_POINTER 6 /* Pointer Register */ +#define LAN91C96_DATA_HIGH 8 /* Data High Register */ +#define LAN91C96_DATA_LOW 10 /* Data Low Register */ +#define LAN91C96_INT_STATS 12 /* Interrupt Status Register - RO */ +#define LAN91C96_INT_ACK 12 /* Interrupt Acknowledge Register -WO */ +#define LAN91C96_INT_MASK 13 /* Interrupt Mask Register */ + +/* + **************************************************************************** + * MMU Command Register - Bank 2 - Offset 0 + **************************************************************************** + */ +#define LAN91C96_MMUCR_NO_BUSY (0x1U << 0) +#define LAN91C96_MMUCR_N1 (0x1U << 1) +#define LAN91C96_MMUCR_N2 (0x1U << 2) +#define LAN91C96_MMUCR_COMMAND (0xFU << 4) +#define LAN91C96_MMUCR_ALLOC_TX (0x2U << 4) /* WXYZ = 0010 */ +#define LAN91C96_MMUCR_RESET_MMU (0x4U << 4) /* WXYZ = 0100 */ +#define LAN91C96_MMUCR_REMOVE_RX (0x6U << 4) /* WXYZ = 0110 */ +#define LAN91C96_MMUCR_REMOVE_TX (0x7U << 4) /* WXYZ = 0111 */ +#define LAN91C96_MMUCR_RELEASE_RX (0x8U << 4) /* WXYZ = 1000 */ +#define LAN91C96_MMUCR_RELEASE_TX (0xAU << 4) /* WXYZ = 1010 */ +#define LAN91C96_MMUCR_ENQUEUE (0xCU << 4) /* WXYZ = 1100 */ +#define LAN91C96_MMUCR_RESET_TX (0xEU << 4) /* WXYZ = 1110 */ + +/* + **************************************************************************** + * Auto Tx Start Register - Bank 2 - Offset 1 + **************************************************************************** + */ +#define LAN91C96_AUTOTX (0xFFU << 0) + +/* + **************************************************************************** + * Packet Number Register - Bank 2 - Offset 2 + **************************************************************************** + */ +#define LAN91C96_PNR_TX (0x1FU << 0) + +/* + **************************************************************************** + * Allocation Result Register - Bank 2 - Offset 3 + **************************************************************************** + */ +#define LAN91C96_ARR_ALLOC_PN (0x7FU << 0) +#define LAN91C96_ARR_FAILED (0x1U << 7) + +/* + **************************************************************************** + * FIFO Ports Register - Bank 2 - Offset 4 + **************************************************************************** + */ +#define LAN91C96_FIFO_TX_DONE_PN (0x1FU << 0) +#define LAN91C96_FIFO_TEMPTY (0x1U << 7) +#define LAN91C96_FIFO_RX_DONE_PN (0x1FU << 8) +#define LAN91C96_FIFO_RXEMPTY (0x1U << 15) + +/* + **************************************************************************** + * Pointer Register - Bank 2 - Offset 6 + **************************************************************************** + */ +#define LAN91C96_PTR_LOW (0xFFU << 0) +#define LAN91C96_PTR_HIGH (0x7U << 8) +#define LAN91C96_PTR_AUTO_TX (0x1U << 11) +#define LAN91C96_PTR_ETEN (0x1U << 12) +#define LAN91C96_PTR_READ (0x1U << 13) +#define LAN91C96_PTR_AUTO_INCR (0x1U << 14) +#define LAN91C96_PTR_RCV (0x1U << 15) + +#define LAN91C96_PTR_RX_FRAME (LAN91C96_PTR_RCV | \ + LAN91C96_PTR_AUTO_INCR | \ + LAN91C96_PTR_READ) + +/* + **************************************************************************** + * Data Register - Bank 2 - Offset 8 + **************************************************************************** + */ +#define LAN91C96_CONTROL_CRC (0x1U << 4) /* CRC bit */ +#define LAN91C96_CONTROL_ODD (0x1U << 5) /* ODD bit */ + +/* + **************************************************************************** + * Interrupt Status Register - Bank 2 - Offset 12 + **************************************************************************** + */ +#define LAN91C96_IST_RCV_INT (0x1U << 0) +#define LAN91C96_IST_TX_INT (0x1U << 1) +#define LAN91C96_IST_TX_EMPTY_INT (0x1U << 2) +#define LAN91C96_IST_ALLOC_INT (0x1U << 3) +#define LAN91C96_IST_RX_OVRN_INT (0x1U << 4) +#define LAN91C96_IST_EPH_INT (0x1U << 5) +#define LAN91C96_IST_ERCV_INT (0x1U << 6) +#define LAN91C96_IST_RX_IDLE_INT (0x1U << 7) + +/* + **************************************************************************** + * Interrupt Acknowledge Register - Bank 2 - Offset 12 + **************************************************************************** + */ +#define LAN91C96_ACK_TX_INT (0x1U << 1) +#define LAN91C96_ACK_TX_EMPTY_INT (0x1U << 2) +#define LAN91C96_ACK_RX_OVRN_INT (0x1U << 4) +#define LAN91C96_ACK_ERCV_INT (0x1U << 6) + +/* + **************************************************************************** + * Interrupt Mask Register - Bank 2 - Offset 13 + **************************************************************************** + */ +#define LAN91C96_MSK_RCV_INT (0x1U << 0) +#define LAN91C96_MSK_TX_INT (0x1U << 1) +#define LAN91C96_MSK_TX_EMPTY_INT (0x1U << 2) +#define LAN91C96_MSK_ALLOC_INT (0x1U << 3) +#define LAN91C96_MSK_RX_OVRN_INT (0x1U << 4) +#define LAN91C96_MSK_EPH_INT (0x1U << 5) +#define LAN91C96_MSK_ERCV_INT (0x1U << 6) +#define LAN91C96_MSK_TX_IDLE_INT (0x1U << 7) + +/* + **************************************************************************** + * Bank 3 Register Map in I/O Space + ************************************************************************** + */ +#define LAN91C96_MGMT_MDO (0x1U << 0) +#define LAN91C96_MGMT_MDI (0x1U << 1) +#define LAN91C96_MGMT_MCLK (0x1U << 2) +#define LAN91C96_MGMT_MDOE (0x1U << 3) +#define LAN91C96_MGMT_LOW_ID (0x3U << 4) +#define LAN91C96_MGMT_IOS0 (0x1U << 8) +#define LAN91C96_MGMT_IOS1 (0x1U << 9) +#define LAN91C96_MGMT_IOS2 (0x1U << 10) +#define LAN91C96_MGMT_nXNDEC (0x1U << 11) +#define LAN91C96_MGMT_HIGH_ID (0x3U << 12) + +/* + **************************************************************************** + * Revision Register - Bank 3 - Offset 10 + **************************************************************************** + */ +#define LAN91C96_REV_REVID (0xFU << 0) +#define LAN91C96_REV_CHIPID (0xFU << 4) + +/* + **************************************************************************** + * Early RCV Register - Bank 3 - Offset 12 + **************************************************************************** + */ +#define LAN91C96_ERCV_THRESHOLD (0x1FU << 0) +#define LAN91C96_ERCV_RCV_DISCRD (0x1U << 7) + +/* + **************************************************************************** + * PCMCIA Configuration Registers + **************************************************************************** + */ +#define LAN91C96_ECOR 0x8000 /* Ethernet Configuration Register */ +#define LAN91C96_ECSR 0x8002 /* Ethernet Configuration and Status */ + +/* + **************************************************************************** + * PCMCIA Ethernet Configuration Option Register (ECOR) + **************************************************************************** + */ +#define LAN91C96_ECOR_ENABLE (0x1U << 0) +#define LAN91C96_ECOR_WR_ATTRIB (0x1U << 2) +#define LAN91C96_ECOR_LEVEL_REQ (0x1U << 6) +#define LAN91C96_ECOR_SRESET (0x1U << 7) + +/* + **************************************************************************** + * PCMCIA Ethernet Configuration and Status Register (ECSR) + **************************************************************************** + */ +#define LAN91C96_ECSR_INTR (0x1U << 1) +#define LAN91C96_ECSR_PWRDWN (0x1U << 2) +#define LAN91C96_ECSR_IOIS8 (0x1U << 5) + +/* + **************************************************************************** + * Receive Frame Status Word - See page 38 of the LAN91C96 specification. + **************************************************************************** + */ +#define LAN91C96_TOO_SHORT (0x1U << 10) +#define LAN91C96_TOO_LONG (0x1U << 11) +#define LAN91C96_ODD_FRM (0x1U << 12) +#define LAN91C96_BAD_CRC (0x1U << 13) +#define LAN91C96_BROD_CAST (0x1U << 14) +#define LAN91C96_ALGN_ERR (0x1U << 15) + +#define FRAME_FILTER (LAN91C96_TOO_SHORT | LAN91C96_TOO_LONG | LAN91C96_BAD_CRC | LAN91C96_ALGN_ERR) + +/* + **************************************************************************** + * Default MAC Address + **************************************************************************** + */ +#define MAC_DEF_HI 0x0800 +#define MAC_DEF_MED 0x3333 +#define MAC_DEF_LO 0x0100 + +/* + **************************************************************************** + * Default I/O Signature - 0x33 + **************************************************************************** + */ +#define LAN91C96_LOW_SIGNATURE (0x33U << 0) +#define LAN91C96_HIGH_SIGNATURE (0x33U << 8) +#define LAN91C96_SIGNATURE (LAN91C96_HIGH_SIGNATURE | LAN91C96_LOW_SIGNATURE) + +#define LAN91C96_MAX_PAGES 6 /* Maximum number of 256 pages. */ +#define ETHERNET_MAX_LENGTH 1514 + + +/*------------------------------------------------------------------------- + * I define some macros to make it easier to do somewhat common + * or slightly complicated, repeated tasks. + *------------------------------------------------------------------------- + */ + +/* select a register bank, 0 to 3 */ + +#define SMC_SELECT_BANK(edev, x) { SMC_outw(edev, x, LAN91C96_BANK_SELECT); } + +/* this enables an interrupt in the interrupt mask register */ +#define SMC_ENABLE_INT(edev, x) {\ + unsigned char mask;\ + SMC_SELECT_BANK(edev, 2);\ + mask = SMC_inb(edev, LAN91C96_INT_MASK);\ + mask |= (x);\ + SMC_outb(edev, mask, LAN91C96_INT_MASK); \ +} + +/* this disables an interrupt from the interrupt mask register */ + +#define SMC_DISABLE_INT(edev, x) {\ + unsigned char mask;\ + SMC_SELECT_BANK(edev, 2);\ + mask = SMC_inb(edev, LAN91C96_INT_MASK);\ + mask &= ~(x);\ + SMC_outb(edev, mask, LAN91C96_INT_MASK); \ +} + +/*---------------------------------------------------------------------- + * Define the interrupts that I want to receive from the card + * + * I want: + * LAN91C96_IST_EPH_INT, for nasty errors + * LAN91C96_IST_RCV_INT, for happy received packets + * LAN91C96_IST_RX_OVRN_INT, because I have to kick the receiver + *------------------------------------------------------------------------- + */ +#define SMC_INTERRUPT_MASK (LAN91C96_IST_EPH_INT | LAN91C96_IST_RX_OVRN_INT | LAN91C96_IST_RCV_INT) + +#endif /* _LAN91C96_H_ */ diff --git a/sources/uboot-be550/drivers/net/ldpaa_eth/Makefile b/sources/uboot-be550/drivers/net/ldpaa_eth/Makefile new file mode 100644 index 00000000..74c49165 --- /dev/null +++ b/sources/uboot-be550/drivers/net/ldpaa_eth/Makefile @@ -0,0 +1,10 @@ +# +# Copyright 2014 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += ldpaa_wriop.o +obj-y += ldpaa_eth.o +obj-$(CONFIG_LS2080A) += ls2080a.o +obj-$(CONFIG_LS2085A) += ls2080a.o diff --git a/sources/uboot-be550/drivers/net/ldpaa_eth/ldpaa_eth.c b/sources/uboot-be550/drivers/net/ldpaa_eth/ldpaa_eth.c new file mode 100644 index 00000000..69530b11 --- /dev/null +++ b/sources/uboot-be550/drivers/net/ldpaa_eth/ldpaa_eth.c @@ -0,0 +1,861 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ldpaa_eth.h" + +#undef CONFIG_PHYLIB +static int init_phy(struct eth_device *dev) +{ + /*TODO for external PHY */ + + return 0; +} + +#ifdef DEBUG +static void ldpaa_eth_get_dpni_counter(void) +{ + int err = 0; + u64 value; + + err = dpni_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS, + dflt_dpni->dpni_handle, + DPNI_CNT_ING_FRAME, + &value); + if (err < 0) { + printf("dpni_get_counter: DPNI_CNT_ING_FRAME failed\n"); + return; + } + printf("DPNI_CNT_ING_FRAME=%lld\n", value); + + err = dpni_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS, + dflt_dpni->dpni_handle, + DPNI_CNT_ING_BYTE, + &value); + if (err < 0) { + printf("dpni_get_counter: DPNI_CNT_ING_BYTE failed\n"); + return; + } + printf("DPNI_CNT_ING_BYTE=%lld\n", value); + + err = dpni_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS, + dflt_dpni->dpni_handle, + DPNI_CNT_ING_FRAME_DROP , + &value); + if (err < 0) { + printf("dpni_get_counter: DPNI_CNT_ING_FRAME_DROP failed\n"); + return; + } + printf("DPNI_CNT_ING_FRAME_DROP =%lld\n", value); + + err = dpni_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS, + dflt_dpni->dpni_handle, + DPNI_CNT_ING_FRAME_DISCARD, + &value); + if (err < 0) { + printf("dpni_get_counter: DPNI_CNT_ING_FRAME_DISCARD failed\n"); + return; + } + printf("DPNI_CNT_ING_FRAME_DISCARD=%lld\n", value); + + err = dpni_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS, + dflt_dpni->dpni_handle, + DPNI_CNT_EGR_FRAME, + &value); + if (err < 0) { + printf("dpni_get_counter: DPNI_CNT_EGR_FRAME failed\n"); + return; + } + printf("DPNI_CNT_EGR_FRAME=%lld\n", value); + + err = dpni_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS, + dflt_dpni->dpni_handle, + DPNI_CNT_EGR_BYTE , + &value); + if (err < 0) { + printf("dpni_get_counter: DPNI_CNT_EGR_BYTE failed\n"); + return; + } + printf("DPNI_CNT_EGR_BYTE =%lld\n", value); + + err = dpni_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS, + dflt_dpni->dpni_handle, + DPNI_CNT_EGR_FRAME_DISCARD , + &value); + if (err < 0) { + printf("dpni_get_counter: DPNI_CNT_EGR_FRAME_DISCARD failed\n"); + return; + } + printf("DPNI_CNT_EGR_FRAME_DISCARD =%lld\n", value); +} +#endif + +static void ldpaa_eth_rx(struct ldpaa_eth_priv *priv, + const struct dpaa_fd *fd) +{ + u64 fd_addr; + uint16_t fd_offset; + uint32_t fd_length; + struct ldpaa_fas *fas; + uint32_t status, err; + u32 timeo = (CONFIG_SYS_HZ * 2) / 1000; + u32 time_start; + struct qbman_release_desc releasedesc; + struct qbman_swp *swp = dflt_dpio->sw_portal; + + fd_addr = ldpaa_fd_get_addr(fd); + fd_offset = ldpaa_fd_get_offset(fd); + fd_length = ldpaa_fd_get_len(fd); + + debug("Rx frame:data addr=0x%p size=0x%x\n", (u64 *)fd_addr, fd_length); + + if (fd->simple.frc & LDPAA_FD_FRC_FASV) { + /* Read the frame annotation status word and check for errors */ + fas = (struct ldpaa_fas *) + ((uint8_t *)(fd_addr) + + dflt_dpni->buf_layout.private_data_size); + status = le32_to_cpu(fas->status); + if (status & LDPAA_ETH_RX_ERR_MASK) { + printf("Rx frame error(s): 0x%08x\n", + status & LDPAA_ETH_RX_ERR_MASK); + goto error; + } else if (status & LDPAA_ETH_RX_UNSUPP_MASK) { + printf("Unsupported feature in bitmask: 0x%08x\n", + status & LDPAA_ETH_RX_UNSUPP_MASK); + goto error; + } + } + + debug("Rx frame: To Upper layer\n"); + net_process_received_packet((uint8_t *)(fd_addr) + fd_offset, + fd_length); + +error: + flush_dcache_range(fd_addr, fd_addr + LDPAA_ETH_RX_BUFFER_SIZE); + qbman_release_desc_clear(&releasedesc); + qbman_release_desc_set_bpid(&releasedesc, dflt_dpbp->dpbp_attr.bpid); + time_start = get_timer(0); + do { + /* Release buffer into the QBMAN */ + err = qbman_swp_release(swp, &releasedesc, &fd_addr, 1); + } while (get_timer(time_start) < timeo && err == -EBUSY); + + if (err == -EBUSY) + printf("Rx frame: QBMAN buffer release fails\n"); + + return; +} + +static int ldpaa_eth_pull_dequeue_rx(struct eth_device *dev) +{ + struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)dev->priv; + const struct ldpaa_dq *dq; + const struct dpaa_fd *fd; + int i = 5, err = 0, status; + u32 timeo = (CONFIG_SYS_HZ * 2) / 1000; + u32 time_start; + static struct qbman_pull_desc pulldesc; + struct qbman_swp *swp = dflt_dpio->sw_portal; + + while (--i) { + qbman_pull_desc_clear(&pulldesc); + qbman_pull_desc_set_numframes(&pulldesc, 1); + qbman_pull_desc_set_fq(&pulldesc, priv->rx_dflt_fqid); + + err = qbman_swp_pull(swp, &pulldesc); + if (err < 0) { + printf("Dequeue frames error:0x%08x\n", err); + continue; + } + + time_start = get_timer(0); + + do { + dq = qbman_swp_dqrr_next(swp); + } while (get_timer(time_start) < timeo && !dq); + + if (dq) { + /* Check for valid frame. If not sent a consume + * confirmation to QBMAN otherwise give it to NADK + * application and then send consume confirmation to + * QBMAN. + */ + status = (uint8_t)ldpaa_dq_flags(dq); + if ((status & LDPAA_DQ_STAT_VALIDFRAME) == 0) { + debug("Dequeue RX frames:"); + debug("No frame delivered\n"); + + qbman_swp_dqrr_consume(swp, dq); + continue; + } + + fd = ldpaa_dq_fd(dq); + + /* Obtain FD and process it */ + ldpaa_eth_rx(priv, fd); + qbman_swp_dqrr_consume(swp, dq); + break; + } else { + err = -ENODATA; + debug("No DQRR entries\n"); + break; + } + } + + return err; +} + +static int ldpaa_eth_tx(struct eth_device *net_dev, void *buf, int len) +{ + struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)net_dev->priv; + struct dpaa_fd fd; + u64 buffer_start; + int data_offset, err; + u32 timeo = (CONFIG_SYS_HZ * 10) / 1000; + u32 time_start; + struct qbman_swp *swp = dflt_dpio->sw_portal; + struct qbman_eq_desc ed; + struct qbman_release_desc releasedesc; + + /* Setup the FD fields */ + memset(&fd, 0, sizeof(fd)); + + data_offset = priv->tx_data_offset; + + do { + err = qbman_swp_acquire(dflt_dpio->sw_portal, + dflt_dpbp->dpbp_attr.bpid, + &buffer_start, 1); + } while (err == -EBUSY); + + if (err < 0) { + printf("qbman_swp_acquire() failed\n"); + return -ENOMEM; + } + + debug("TX data: malloc buffer start=0x%p\n", (u64 *)buffer_start); + + memcpy(((uint8_t *)(buffer_start) + data_offset), buf, len); + + flush_dcache_range(buffer_start, buffer_start + + LDPAA_ETH_RX_BUFFER_SIZE); + + ldpaa_fd_set_addr(&fd, (u64)buffer_start); + ldpaa_fd_set_offset(&fd, (uint16_t)(data_offset)); + ldpaa_fd_set_bpid(&fd, dflt_dpbp->dpbp_attr.bpid); + ldpaa_fd_set_len(&fd, len); + + fd.simple.ctrl = LDPAA_FD_CTRL_ASAL | LDPAA_FD_CTRL_PTA | + LDPAA_FD_CTRL_PTV1; + + qbman_eq_desc_clear(&ed); + qbman_eq_desc_set_no_orp(&ed, 0); + qbman_eq_desc_set_qd(&ed, priv->tx_qdid, priv->tx_flow_id, 0); + + time_start = get_timer(0); + + while (get_timer(time_start) < timeo) { + err = qbman_swp_enqueue(swp, &ed, + (const struct qbman_fd *)(&fd)); + if (err != -EBUSY) + break; + } + + if (err < 0) { + printf("error enqueueing Tx frame\n"); + goto error; + } + + return err; + +error: + qbman_release_desc_clear(&releasedesc); + qbman_release_desc_set_bpid(&releasedesc, dflt_dpbp->dpbp_attr.bpid); + time_start = get_timer(0); + do { + /* Release buffer into the QBMAN */ + err = qbman_swp_release(swp, &releasedesc, &buffer_start, 1); + } while (get_timer(time_start) < timeo && err == -EBUSY); + + if (err == -EBUSY) + printf("TX data: QBMAN buffer release fails\n"); + + return err; +} + +static int ldpaa_eth_open(struct eth_device *net_dev, bd_t *bd) +{ + struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)net_dev->priv; + struct dpni_queue_attr rx_queue_attr; + struct dpmac_link_state dpmac_link_state = { 0 }; +#ifdef DEBUG + struct dpni_link_state link_state; +#endif + int err; + + if (net_dev->state == ETH_STATE_ACTIVE) + return 0; + + if (get_mc_boot_status() != 0) { + printf("ERROR (MC is not booted)\n"); + return -ENODEV; + } + + if (get_dpl_apply_status() == 0) { + printf("ERROR (DPL is deployed. No device available)\n"); + return -ENODEV; + } + /* DPMAC initialization */ + err = ldpaa_dpmac_setup(priv); + if (err < 0) + goto err_dpmac_setup; + + /* DPMAC binding DPNI */ + err = ldpaa_dpmac_bind(priv); + if (err) + goto err_dpamc_bind; + + /* DPNI initialization */ + err = ldpaa_dpni_setup(priv); + if (err < 0) + goto err_dpni_setup; + + err = ldpaa_dpbp_setup(); + if (err < 0) + goto err_dpbp_setup; + + /* DPNI binding DPBP */ + err = ldpaa_dpni_bind(priv); + if (err) + goto err_dpni_bind; + + err = dpni_add_mac_addr(dflt_mc_io, MC_CMD_NO_FLAGS, + dflt_dpni->dpni_handle, net_dev->enetaddr); + if (err) { + printf("dpni_add_mac_addr() failed\n"); + return err; + } + +#ifdef CONFIG_PHYLIB + /* TODO Check this path */ + err = phy_startup(priv->phydev); + if (err) { + printf("%s: Could not initialize\n", priv->phydev->dev->name); + return err; + } +#else + priv->phydev->speed = SPEED_1000; + priv->phydev->link = 1; + priv->phydev->duplex = DUPLEX_FULL; +#endif + + err = dpni_enable(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle); + if (err < 0) { + printf("dpni_enable() failed\n"); + return err; + } + + dpmac_link_state.rate = SPEED_1000; + dpmac_link_state.options = DPMAC_LINK_OPT_AUTONEG; + dpmac_link_state.up = 1; + err = dpmac_set_link_state(dflt_mc_io, MC_CMD_NO_FLAGS, + priv->dpmac_handle, &dpmac_link_state); + if (err < 0) { + printf("dpmac_set_link_state() failed\n"); + return err; + } + +#ifdef DEBUG + err = dpni_get_link_state(dflt_mc_io, MC_CMD_NO_FLAGS, + dflt_dpni->dpni_handle, &link_state); + if (err < 0) { + printf("dpni_get_link_state() failed\n"); + return err; + } + + printf("link status: %d - ", link_state.up); + link_state.up == 0 ? printf("down\n") : + link_state.up == 1 ? printf("up\n") : printf("error state\n"); +#endif + + /* TODO: support multiple Rx flows */ + err = dpni_get_rx_flow(dflt_mc_io, MC_CMD_NO_FLAGS, + dflt_dpni->dpni_handle, 0, 0, &rx_queue_attr); + if (err) { + printf("dpni_get_rx_flow() failed\n"); + goto err_rx_flow; + } + + priv->rx_dflt_fqid = rx_queue_attr.fqid; + + err = dpni_get_qdid(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle, + &priv->tx_qdid); + if (err) { + printf("dpni_get_qdid() failed\n"); + goto err_qdid; + } + + if (!priv->phydev->link) + printf("%s: No link.\n", priv->phydev->dev->name); + + return priv->phydev->link ? 0 : -1; + +err_qdid: +err_rx_flow: + dpni_disable(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle); +err_dpni_bind: + ldpaa_dpbp_free(); +err_dpbp_setup: +err_dpamc_bind: + dpni_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle); +err_dpni_setup: +err_dpmac_setup: + return err; +} + +static void ldpaa_eth_stop(struct eth_device *net_dev) +{ + struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)net_dev->priv; + int err = 0; + + if ((net_dev->state == ETH_STATE_PASSIVE) || + (net_dev->state == ETH_STATE_INIT)) + return; + +#ifdef DEBUG + ldpaa_eth_get_dpni_counter(); +#endif + + err = dprc_disconnect(dflt_mc_io, MC_CMD_NO_FLAGS, + dflt_dprc_handle, &dpmac_endpoint); + if (err < 0) + printf("dprc_disconnect() failed dpmac_endpoint\n"); + + err = dpmac_destroy(dflt_mc_io, MC_CMD_NO_FLAGS, priv->dpmac_handle); + if (err < 0) + printf("dpmac_destroy() failed\n"); + + /* Stop Tx and Rx traffic */ + err = dpni_disable(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle); + if (err < 0) + printf("dpni_disable() failed\n"); + +#ifdef CONFIG_PHYLIB + phy_shutdown(priv->phydev); +#endif + + ldpaa_dpbp_free(); + dpni_reset(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle); + dpni_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle); +} + +static void ldpaa_dpbp_drain_cnt(int count) +{ + uint64_t buf_array[7]; + void *addr; + int ret, i; + + BUG_ON(count > 7); + + do { + ret = qbman_swp_acquire(dflt_dpio->sw_portal, + dflt_dpbp->dpbp_attr.bpid, + buf_array, count); + if (ret < 0) { + printf("qbman_swp_acquire() failed\n"); + return; + } + for (i = 0; i < ret; i++) { + addr = (void *)buf_array[i]; + debug("Free: buffer addr =0x%p\n", addr); + free(addr); + } + } while (ret); +} + +static void ldpaa_dpbp_drain(void) +{ + int i; + for (i = 0; i < LDPAA_ETH_NUM_BUFS; i += 7) + ldpaa_dpbp_drain_cnt(7); +} + +static int ldpaa_bp_add_7(uint16_t bpid) +{ + uint64_t buf_array[7]; + u8 *addr; + int i; + struct qbman_release_desc rd; + + for (i = 0; i < 7; i++) { + addr = memalign(LDPAA_ETH_BUF_ALIGN, LDPAA_ETH_RX_BUFFER_SIZE); + if (!addr) { + printf("addr allocation failed\n"); + goto err_alloc; + } + memset(addr, 0x00, LDPAA_ETH_RX_BUFFER_SIZE); + flush_dcache_range((u64)addr, + (u64)(addr + LDPAA_ETH_RX_BUFFER_SIZE)); + + buf_array[i] = (uint64_t)addr; + debug("Release: buffer addr =0x%p\n", addr); + } + +release_bufs: + /* In case the portal is busy, retry until successful. + * This function is guaranteed to succeed in a reasonable amount + * of time. + */ + + do { + mdelay(1); + qbman_release_desc_clear(&rd); + qbman_release_desc_set_bpid(&rd, bpid); + } while (qbman_swp_release(dflt_dpio->sw_portal, &rd, buf_array, i)); + + return i; + +err_alloc: + if (i) + goto release_bufs; + + return 0; +} + +static int ldpaa_dpbp_seed(uint16_t bpid) +{ + int i; + int count; + + for (i = 0; i < LDPAA_ETH_NUM_BUFS; i += 7) { + count = ldpaa_bp_add_7(bpid); + if (count < 7) + printf("Buffer Seed= %d\n", count); + } + + return 0; +} + +static int ldpaa_dpbp_setup(void) +{ + int err; + + err = dpbp_open(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpbp->dpbp_attr.id, + &dflt_dpbp->dpbp_handle); + if (err) { + printf("dpbp_open() failed\n"); + goto err_open; + } + + err = dpbp_enable(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpbp->dpbp_handle); + if (err) { + printf("dpbp_enable() failed\n"); + goto err_enable; + } + + err = dpbp_get_attributes(dflt_mc_io, MC_CMD_NO_FLAGS, + dflt_dpbp->dpbp_handle, + &dflt_dpbp->dpbp_attr); + if (err) { + printf("dpbp_get_attributes() failed\n"); + goto err_get_attr; + } + + err = ldpaa_dpbp_seed(dflt_dpbp->dpbp_attr.bpid); + if (err) { + printf("Buffer seeding failed for DPBP %d (bpid=%d)\n", + dflt_dpbp->dpbp_attr.id, dflt_dpbp->dpbp_attr.bpid); + goto err_seed; + } + + return 0; + +err_seed: +err_get_attr: + dpbp_disable(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpbp->dpbp_handle); +err_enable: + dpbp_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpbp->dpbp_handle); +err_open: + return err; +} + +static void ldpaa_dpbp_free(void) +{ + ldpaa_dpbp_drain(); + dpbp_disable(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpbp->dpbp_handle); + dpbp_reset(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpbp->dpbp_handle); + dpbp_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpbp->dpbp_handle); +} + +static int ldpaa_dpmac_setup(struct ldpaa_eth_priv *priv) +{ + int err = 0; + struct dpmac_cfg dpmac_cfg; + + dpmac_cfg.mac_id = priv->dpmac_id; + err = dpmac_create(dflt_mc_io, MC_CMD_NO_FLAGS, &dpmac_cfg, + &priv->dpmac_handle); + if (err) + printf("dpmac_create() failed\n"); + return err; +} + +static int ldpaa_dpmac_bind(struct ldpaa_eth_priv *priv) +{ + int err = 0; + struct dprc_connection_cfg dprc_connection_cfg = { + /* If both rates are zero the connection */ + /* will be configured in "best effort" mode. */ + .committed_rate = 0, + .max_rate = 0 + }; + +#ifdef DEBUG + struct dprc_endpoint dbg_endpoint; + int state = 0; +#endif + + memset(&dpmac_endpoint, 0, sizeof(struct dprc_endpoint)); + sprintf(dpmac_endpoint.type, "dpmac"); + dpmac_endpoint.id = priv->dpmac_id; + + memset(&dpni_endpoint, 0, sizeof(struct dprc_endpoint)); + sprintf(dpni_endpoint.type, "dpni"); + dpni_endpoint.id = dflt_dpni->dpni_id; + + err = dprc_connect(dflt_mc_io, MC_CMD_NO_FLAGS, + dflt_dprc_handle, + &dpmac_endpoint, + &dpni_endpoint, + &dprc_connection_cfg); + if (err) + printf("dprc_connect() failed\n"); + +#ifdef DEBUG + err = dprc_get_connection(dflt_mc_io, MC_CMD_NO_FLAGS, + dflt_dprc_handle, &dpni_endpoint, + &dbg_endpoint, &state); + printf("%s, DPMAC Type= %s\n", __func__, dbg_endpoint.type); + printf("%s, DPMAC ID= %d\n", __func__, dbg_endpoint.id); + printf("%s, DPMAC State= %d\n", __func__, state); + + memset(&dbg_endpoint, 0, sizeof(struct dprc_endpoint)); + err = dprc_get_connection(dflt_mc_io, MC_CMD_NO_FLAGS, + dflt_dprc_handle, &dpmac_endpoint, + &dbg_endpoint, &state); + printf("%s, DPNI Type= %s\n", __func__, dbg_endpoint.type); + printf("%s, DPNI ID= %d\n", __func__, dbg_endpoint.id); + printf("%s, DPNI State= %d\n", __func__, state); +#endif + return err; +} + +static int ldpaa_dpni_setup(struct ldpaa_eth_priv *priv) +{ + int err; + + /* and get a handle for the DPNI this interface is associate with */ + err = dpni_open(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_id, + &dflt_dpni->dpni_handle); + if (err) { + printf("dpni_open() failed\n"); + goto err_open; + } + + err = dpni_get_attributes(dflt_mc_io, MC_CMD_NO_FLAGS, + dflt_dpni->dpni_handle, + &dflt_dpni->dpni_attrs); + if (err) { + printf("dpni_get_attributes() failed (err=%d)\n", err); + goto err_get_attr; + } + + /* Configure our buffers' layout */ + dflt_dpni->buf_layout.options = DPNI_BUF_LAYOUT_OPT_PARSER_RESULT | + DPNI_BUF_LAYOUT_OPT_FRAME_STATUS | + DPNI_BUF_LAYOUT_OPT_PRIVATE_DATA_SIZE | + DPNI_BUF_LAYOUT_OPT_DATA_ALIGN; + dflt_dpni->buf_layout.pass_parser_result = true; + dflt_dpni->buf_layout.pass_frame_status = true; + dflt_dpni->buf_layout.private_data_size = LDPAA_ETH_SWA_SIZE; + /* HW erratum mandates data alignment in multiples of 256 */ + dflt_dpni->buf_layout.data_align = LDPAA_ETH_BUF_ALIGN; + /* ...rx, ... */ + err = dpni_set_rx_buffer_layout(dflt_mc_io, MC_CMD_NO_FLAGS, + dflt_dpni->dpni_handle, + &dflt_dpni->buf_layout); + if (err) { + printf("dpni_set_rx_buffer_layout() failed"); + goto err_buf_layout; + } + + /* ... tx, ... */ + /* remove Rx-only options */ + dflt_dpni->buf_layout.options &= ~(DPNI_BUF_LAYOUT_OPT_DATA_ALIGN | + DPNI_BUF_LAYOUT_OPT_PARSER_RESULT); + err = dpni_set_tx_buffer_layout(dflt_mc_io, MC_CMD_NO_FLAGS, + dflt_dpni->dpni_handle, + &dflt_dpni->buf_layout); + if (err) { + printf("dpni_set_tx_buffer_layout() failed"); + goto err_buf_layout; + } + + /* ... tx-confirm. */ + dflt_dpni->buf_layout.options &= ~DPNI_BUF_LAYOUT_OPT_PRIVATE_DATA_SIZE; + err = dpni_set_tx_conf_buffer_layout(dflt_mc_io, MC_CMD_NO_FLAGS, + dflt_dpni->dpni_handle, + &dflt_dpni->buf_layout); + if (err) { + printf("dpni_set_tx_conf_buffer_layout() failed"); + goto err_buf_layout; + } + + /* Now that we've set our tx buffer layout, retrieve the minimum + * required tx data offset. + */ + err = dpni_get_tx_data_offset(dflt_mc_io, MC_CMD_NO_FLAGS, + dflt_dpni->dpni_handle, + &priv->tx_data_offset); + if (err) { + printf("dpni_get_tx_data_offset() failed\n"); + goto err_data_offset; + } + + /* Warn in case TX data offset is not multiple of 64 bytes. */ + WARN_ON(priv->tx_data_offset % 64); + + /* Accomodate SWA space. */ + priv->tx_data_offset += LDPAA_ETH_SWA_SIZE; + debug("priv->tx_data_offset=%d\n", priv->tx_data_offset); + + return 0; + +err_data_offset: +err_buf_layout: +err_get_attr: + dpni_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle); +err_open: + return err; +} + +static int ldpaa_dpni_bind(struct ldpaa_eth_priv *priv) +{ + struct dpni_pools_cfg pools_params; + struct dpni_tx_flow_cfg dflt_tx_flow; + int err = 0; + + pools_params.num_dpbp = 1; + pools_params.pools[0].dpbp_id = (uint16_t)dflt_dpbp->dpbp_attr.id; + pools_params.pools[0].buffer_size = LDPAA_ETH_RX_BUFFER_SIZE; + err = dpni_set_pools(dflt_mc_io, MC_CMD_NO_FLAGS, + dflt_dpni->dpni_handle, &pools_params); + if (err) { + printf("dpni_set_pools() failed\n"); + return err; + } + + priv->tx_flow_id = DPNI_NEW_FLOW_ID; + memset(&dflt_tx_flow, 0, sizeof(dflt_tx_flow)); + + dflt_tx_flow.options = DPNI_TX_FLOW_OPT_ONLY_TX_ERROR; + dflt_tx_flow.conf_err_cfg.use_default_queue = 0; + dflt_tx_flow.conf_err_cfg.errors_only = 1; + err = dpni_set_tx_flow(dflt_mc_io, MC_CMD_NO_FLAGS, + dflt_dpni->dpni_handle, &priv->tx_flow_id, + &dflt_tx_flow); + if (err) { + printf("dpni_set_tx_flow() failed\n"); + return err; + } + + return 0; +} + +static int ldpaa_eth_netdev_init(struct eth_device *net_dev, + phy_interface_t enet_if) +{ + int err; + struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)net_dev->priv; + + sprintf(net_dev->name, "DPMAC%d@%s", priv->dpmac_id, + phy_interface_strings[enet_if]); + + net_dev->iobase = 0; + net_dev->init = ldpaa_eth_open; + net_dev->halt = ldpaa_eth_stop; + net_dev->send = ldpaa_eth_tx; + net_dev->recv = ldpaa_eth_pull_dequeue_rx; +/* + TODO: PHY MDIO information + priv->bus = info->bus; + priv->phyaddr = info->phy_addr; + priv->enet_if = info->enet_if; +*/ + + if (init_phy(net_dev)) + return 0; + + err = eth_register(net_dev); + if (err < 0) { + printf("eth_register() = %d\n", err); + return err; + } + + return 0; +} + +int ldpaa_eth_init(int dpmac_id, phy_interface_t enet_if) +{ + struct eth_device *net_dev = NULL; + struct ldpaa_eth_priv *priv = NULL; + int err = 0; + + + /* Net device */ + net_dev = (struct eth_device *)malloc(sizeof(struct eth_device)); + if (!net_dev) { + printf("eth_device malloc() failed\n"); + return -ENOMEM; + } + memset(net_dev, 0, sizeof(struct eth_device)); + + /* alloc the ldpaa ethernet private struct */ + priv = (struct ldpaa_eth_priv *)malloc(sizeof(struct ldpaa_eth_priv)); + if (!priv) { + printf("ldpaa_eth_priv malloc() failed\n"); + return -ENOMEM; + } + memset(priv, 0, sizeof(struct ldpaa_eth_priv)); + + net_dev->priv = (void *)priv; + priv->net_dev = (struct eth_device *)net_dev; + priv->dpmac_id = dpmac_id; + debug("%s dpmac_id=%d\n", __func__, dpmac_id); + + err = ldpaa_eth_netdev_init(net_dev, enet_if); + if (err) + goto err_netdev_init; + + debug("ldpaa ethernet: Probed interface %s\n", net_dev->name); + return 0; + +err_netdev_init: + free(priv); + net_dev->priv = NULL; + free(net_dev); + + return err; +} diff --git a/sources/uboot-be550/drivers/net/ldpaa_eth/ldpaa_eth.h b/sources/uboot-be550/drivers/net/ldpaa_eth/ldpaa_eth.h new file mode 100644 index 00000000..af41b278 --- /dev/null +++ b/sources/uboot-be550/drivers/net/ldpaa_eth/ldpaa_eth.h @@ -0,0 +1,151 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __LDPAA_ETH_H +#define __LDPAA_ETH_H + +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +enum ldpaa_eth_type { + LDPAA_ETH_1G_E, + LDPAA_ETH_10G_E, +}; + +/* Arbitrary values for now, but we'll need to tune */ +#define LDPAA_ETH_NUM_BUFS (2 * 7) +#define LDPAA_ETH_REFILL_THRESH (LDPAA_ETH_NUM_BUFS/2) +#define LDPAA_ETH_RX_BUFFER_SIZE 2048 + +/* Hardware requires alignment for buffer address and length: 256-byte + * for ingress, 64-byte for egress. Using 256 for both. + */ +#define LDPAA_ETH_BUF_ALIGN 256 + +/* So far we're only accomodating a skb backpointer in the frame's + * software annotation, but the hardware options are either 0 or 64. + */ +#define LDPAA_ETH_SWA_SIZE 64 + +/* Annotation valid bits in FD FRC */ +#define LDPAA_FD_FRC_FASV 0x8000 +#define LDPAA_FD_FRC_FAEADV 0x4000 +#define LDPAA_FD_FRC_FAPRV 0x2000 +#define LDPAA_FD_FRC_FAIADV 0x1000 +#define LDPAA_FD_FRC_FASWOV 0x0800 +#define LDPAA_FD_FRC_FAICFDV 0x0400 + +/* Annotation bits in FD CTRL */ +#define LDPAA_FD_CTRL_ASAL 0x00020000 /* ASAL = 128 */ +#define LDPAA_FD_CTRL_PTA 0x00800000 +#define LDPAA_FD_CTRL_PTV1 0x00400000 + +/* TODO: we may want to move this and other WRIOP related defines + * to a separate header + */ +/* Frame annotation status */ +struct ldpaa_fas { + u8 reserved; + u8 ppid; + __le16 ifpid; + __le32 status; +} __packed; + +/* Debug frame, otherwise supposed to be discarded */ +#define LDPAA_ETH_FAS_DISC 0x80000000 +/* MACSEC frame */ +#define LDPAA_ETH_FAS_MS 0x40000000 +#define LDPAA_ETH_FAS_PTP 0x08000000 +/* Ethernet multicast frame */ +#define LDPAA_ETH_FAS_MC 0x04000000 +/* Ethernet broadcast frame */ +#define LDPAA_ETH_FAS_BC 0x02000000 +#define LDPAA_ETH_FAS_KSE 0x00040000 +#define LDPAA_ETH_FAS_EOFHE 0x00020000 +#define LDPAA_ETH_FAS_MNLE 0x00010000 +#define LDPAA_ETH_FAS_TIDE 0x00008000 +#define LDPAA_ETH_FAS_PIEE 0x00004000 +/* Frame length error */ +#define LDPAA_ETH_FAS_FLE 0x00002000 +/* Frame physical error; our favourite pastime */ +#define LDPAA_ETH_FAS_FPE 0x00001000 +#define LDPAA_ETH_FAS_PTE 0x00000080 +#define LDPAA_ETH_FAS_ISP 0x00000040 +#define LDPAA_ETH_FAS_PHE 0x00000020 +#define LDPAA_ETH_FAS_BLE 0x00000010 +/* L3 csum validation performed */ +#define LDPAA_ETH_FAS_L3CV 0x00000008 +/* L3 csum error */ +#define LDPAA_ETH_FAS_L3CE 0x00000004 +/* L4 csum validation performed */ +#define LDPAA_ETH_FAS_L4CV 0x00000002 +/* L4 csum error */ +#define LDPAA_ETH_FAS_L4CE 0x00000001 +/* These bits always signal errors */ +#define LDPAA_ETH_RX_ERR_MASK (LDPAA_ETH_FAS_DISC | \ + LDPAA_ETH_FAS_KSE | \ + LDPAA_ETH_FAS_EOFHE | \ + LDPAA_ETH_FAS_MNLE | \ + LDPAA_ETH_FAS_TIDE | \ + LDPAA_ETH_FAS_PIEE | \ + LDPAA_ETH_FAS_FLE | \ + LDPAA_ETH_FAS_FPE | \ + LDPAA_ETH_FAS_PTE | \ + LDPAA_ETH_FAS_ISP | \ + LDPAA_ETH_FAS_PHE | \ + LDPAA_ETH_FAS_BLE | \ + LDPAA_ETH_FAS_L3CE | \ + LDPAA_ETH_FAS_L4CE) +/* Unsupported features in the ingress */ +#define LDPAA_ETH_RX_UNSUPP_MASK LDPAA_ETH_FAS_MS +/* TODO trim down the bitmask; not all of them apply to Tx-confirm */ +#define LDPAA_ETH_TXCONF_ERR_MASK (LDPAA_ETH_FAS_KSE | \ + LDPAA_ETH_FAS_EOFHE | \ + LDPAA_ETH_FAS_MNLE | \ + LDPAA_ETH_FAS_TIDE) + +struct ldpaa_eth_priv { + struct eth_device *net_dev; + int dpmac_id; + uint16_t dpmac_handle; + + uint16_t tx_data_offset; + + uint32_t rx_dflt_fqid; + uint16_t tx_qdid; + uint16_t tx_flow_id; + + enum ldpaa_eth_type type; /* 1G or 10G ethernet */ + struct phy_device *phydev; +}; + +struct dprc_endpoint dpmac_endpoint; +struct dprc_endpoint dpni_endpoint; + +extern struct fsl_mc_io *dflt_mc_io; +extern struct fsl_dpbp_obj *dflt_dpbp; +extern struct fsl_dpio_obj *dflt_dpio; +extern struct fsl_dpni_obj *dflt_dpni; +extern uint16_t dflt_dprc_handle; + +static void ldpaa_dpbp_drain_cnt(int count); +static void ldpaa_dpbp_drain(void); +static int ldpaa_dpbp_seed(uint16_t bpid); +static void ldpaa_dpbp_free(void); +static int ldpaa_dpni_setup(struct ldpaa_eth_priv *priv); +static int ldpaa_dpbp_setup(void); +static int ldpaa_dpni_bind(struct ldpaa_eth_priv *priv); +static int ldpaa_dpmac_setup(struct ldpaa_eth_priv *priv); +static int ldpaa_dpmac_bind(struct ldpaa_eth_priv *priv); +#endif /* __LDPAA_H */ diff --git a/sources/uboot-be550/drivers/net/ldpaa_eth/ldpaa_wriop.c b/sources/uboot-be550/drivers/net/ldpaa_eth/ldpaa_wriop.c new file mode 100644 index 00000000..f7f26c27 --- /dev/null +++ b/sources/uboot-be550/drivers/net/ldpaa_eth/ldpaa_wriop.c @@ -0,0 +1,157 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +struct wriop_dpmac_info dpmac_info[NUM_WRIOP_PORTS]; + +__weak phy_interface_t wriop_dpmac_enet_if(int dpmac_id, int lane_prtc) +{ + return PHY_INTERFACE_MODE_NONE; +} + +void wriop_init_dpmac(int sd, int dpmac_id, int lane_prtcl) +{ + phy_interface_t enet_if; + + dpmac_info[dpmac_id].enabled = 0; + dpmac_info[dpmac_id].id = 0; + dpmac_info[dpmac_id].phy_addr = -1; + dpmac_info[dpmac_id].enet_if = PHY_INTERFACE_MODE_NONE; + + enet_if = wriop_dpmac_enet_if(dpmac_id, lane_prtcl); + if (enet_if != PHY_INTERFACE_MODE_NONE) { + dpmac_info[dpmac_id].enabled = 1; + dpmac_info[dpmac_id].id = dpmac_id; + dpmac_info[dpmac_id].enet_if = enet_if; + } +} + +/*TODO what it do */ +static int wriop_dpmac_to_index(int dpmac_id) +{ + int i; + + for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) { + if (dpmac_info[i].id == dpmac_id) + return i; + } + + return -1; +} + +void wriop_disable_dpmac(int dpmac_id) +{ + int i = wriop_dpmac_to_index(dpmac_id); + + if (i == -1) + return; + + dpmac_info[i].enabled = 0; + wriop_dpmac_disable(dpmac_id); +} + +void wriop_enable_dpmac(int dpmac_id) +{ + int i = wriop_dpmac_to_index(dpmac_id); + + if (i == -1) + return; + + dpmac_info[i].enabled = 1; + wriop_dpmac_enable(dpmac_id); +} + +u8 wriop_is_enabled_dpmac(int dpmac_id) +{ + int i = wriop_dpmac_to_index(dpmac_id); + + if (i == -1) + return -1; + + return dpmac_info[i].enabled; +} + + +void wriop_set_mdio(int dpmac_id, struct mii_dev *bus) +{ + int i = wriop_dpmac_to_index(dpmac_id); + + if (i == -1) + return; + + dpmac_info[i].bus = bus; +} + +struct mii_dev *wriop_get_mdio(int dpmac_id) +{ + int i = wriop_dpmac_to_index(dpmac_id); + + if (i == -1) + return NULL; + + return dpmac_info[i].bus; +} + +void wriop_set_phy_address(int dpmac_id, int address) +{ + int i = wriop_dpmac_to_index(dpmac_id); + + if (i == -1) + return; + + dpmac_info[i].phy_addr = address; +} + +int wriop_get_phy_address(int dpmac_id) +{ + int i = wriop_dpmac_to_index(dpmac_id); + + if (i == -1) + return -1; + + return dpmac_info[i].phy_addr; +} + +void wriop_set_phy_dev(int dpmac_id, struct phy_device *phydev) +{ + int i = wriop_dpmac_to_index(dpmac_id); + + if (i == -1) + return; + + dpmac_info[i].phydev = phydev; +} + +struct phy_device *wriop_get_phy_dev(int dpmac_id) +{ + int i = wriop_dpmac_to_index(dpmac_id); + + if (i == -1) + return NULL; + + return dpmac_info[i].phydev; +} + +phy_interface_t wriop_get_enet_if(int dpmac_id) +{ + int i = wriop_dpmac_to_index(dpmac_id); + + if (i == -1) + return PHY_INTERFACE_MODE_NONE; + + if (dpmac_info[i].enabled) + return dpmac_info[i].enet_if; + + return PHY_INTERFACE_MODE_NONE; +} diff --git a/sources/uboot-be550/drivers/net/ldpaa_eth/ls2080a.c b/sources/uboot-be550/drivers/net/ldpaa_eth/ls2080a.c new file mode 100644 index 00000000..93ed4f18 --- /dev/null +++ b/sources/uboot-be550/drivers/net/ldpaa_eth/ls2080a.c @@ -0,0 +1,81 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include + +u32 dpmac_to_devdisr[] = { + [WRIOP1_DPMAC1] = FSL_CHASSIS3_DEVDISR2_DPMAC1, + [WRIOP1_DPMAC2] = FSL_CHASSIS3_DEVDISR2_DPMAC2, + [WRIOP1_DPMAC3] = FSL_CHASSIS3_DEVDISR2_DPMAC3, + [WRIOP1_DPMAC4] = FSL_CHASSIS3_DEVDISR2_DPMAC4, + [WRIOP1_DPMAC5] = FSL_CHASSIS3_DEVDISR2_DPMAC5, + [WRIOP1_DPMAC6] = FSL_CHASSIS3_DEVDISR2_DPMAC6, + [WRIOP1_DPMAC7] = FSL_CHASSIS3_DEVDISR2_DPMAC7, + [WRIOP1_DPMAC8] = FSL_CHASSIS3_DEVDISR2_DPMAC8, + [WRIOP1_DPMAC9] = FSL_CHASSIS3_DEVDISR2_DPMAC9, + [WRIOP1_DPMAC10] = FSL_CHASSIS3_DEVDISR2_DPMAC10, + [WRIOP1_DPMAC11] = FSL_CHASSIS3_DEVDISR2_DPMAC11, + [WRIOP1_DPMAC12] = FSL_CHASSIS3_DEVDISR2_DPMAC12, + [WRIOP1_DPMAC13] = FSL_CHASSIS3_DEVDISR2_DPMAC13, + [WRIOP1_DPMAC14] = FSL_CHASSIS3_DEVDISR2_DPMAC14, + [WRIOP1_DPMAC15] = FSL_CHASSIS3_DEVDISR2_DPMAC15, + [WRIOP1_DPMAC16] = FSL_CHASSIS3_DEVDISR2_DPMAC16, + [WRIOP1_DPMAC17] = FSL_CHASSIS3_DEVDISR2_DPMAC17, + [WRIOP1_DPMAC18] = FSL_CHASSIS3_DEVDISR2_DPMAC18, + [WRIOP1_DPMAC19] = FSL_CHASSIS3_DEVDISR2_DPMAC19, + [WRIOP1_DPMAC20] = FSL_CHASSIS3_DEVDISR2_DPMAC20, + [WRIOP1_DPMAC21] = FSL_CHASSIS3_DEVDISR2_DPMAC21, + [WRIOP1_DPMAC22] = FSL_CHASSIS3_DEVDISR2_DPMAC22, + [WRIOP1_DPMAC23] = FSL_CHASSIS3_DEVDISR2_DPMAC23, + [WRIOP1_DPMAC24] = FSL_CHASSIS3_DEVDISR2_DPMAC24, +}; + +static int is_device_disabled(int dpmac_id) +{ + struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + u32 devdisr2 = in_le32(&gur->devdisr2); + + return dpmac_to_devdisr[dpmac_id] & devdisr2; +} + +void wriop_dpmac_disable(int dpmac_id) +{ + struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + + setbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]); +} + +void wriop_dpmac_enable(int dpmac_id) +{ + struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + + clrbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]); +} + +phy_interface_t wriop_dpmac_enet_if(int dpmac_id, int lane_prtcl) +{ + enum srds_prtcl; + + if (is_device_disabled(dpmac_id + 1)) + return PHY_INTERFACE_MODE_NONE; + + if (lane_prtcl >= SGMII1 && lane_prtcl <= SGMII16) + return PHY_INTERFACE_MODE_SGMII; + + if (lane_prtcl >= XFI1 && lane_prtcl <= XFI8) + return PHY_INTERFACE_MODE_XGMII; + + if (lane_prtcl >= XAUI1 && lane_prtcl <= XAUI2) + return PHY_INTERFACE_MODE_XGMII; + + if (lane_prtcl >= QSGMII_A && lane_prtcl <= QSGMII_D) + return PHY_INTERFACE_MODE_QSGMII; + + return PHY_INTERFACE_MODE_NONE; +} diff --git a/sources/uboot-be550/drivers/net/lpc32xx_eth.c b/sources/uboot-be550/drivers/net/lpc32xx_eth.c new file mode 100644 index 00000000..e76e9bc2 --- /dev/null +++ b/sources/uboot-be550/drivers/net/lpc32xx_eth.c @@ -0,0 +1,652 @@ +/* + * LPC32xx Ethernet MAC interface driver + * + * (C) Copyright 2014 DENX Software Engineering GmbH + * Written-by: Albert ARIBAUD - 3ADEV + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * Notes: + * + * 1. Unless specified otherwise, all references to tables or paragraphs + * are to UM10326, "LPC32x0 and LPC32x0/01 User manual". + * + * 2. Only bitfield masks/values which are actually used by the driver + * are defined. + */ + +/* a single RX descriptor. The controller has an array of these */ +struct lpc32xx_eth_rxdesc { + u32 packet; /* Receive packet pointer */ + u32 control; /* Descriptor command status */ +}; + +#define LPC32XX_ETH_RX_DESC_SIZE (sizeof(struct lpc32xx_eth_rxdesc)) + +/* RX control bitfields/masks (see Table 330) */ +#define LPC32XX_ETH_RX_CTRL_SIZE_MASK 0x000007FF +#define LPC32XX_ETH_RX_CTRL_UNUSED 0x7FFFF800 +#define LPC32XX_ETH_RX_CTRL_INTERRUPT 0x80000000 + +/* a single RX status. The controller has an array of these */ +struct lpc32xx_eth_rxstat { + u32 statusinfo; /* Transmit Descriptor status */ + u32 statushashcrc; /* Transmit Descriptor CRCs */ +}; + +#define LPC32XX_ETH_RX_STAT_SIZE (sizeof(struct lpc32xx_eth_rxstat)) + +/* RX statusinfo bitfields/masks (see Table 333) */ +#define RX_STAT_RXSIZE 0x000007FF +/* Helper: OR of all errors except RANGE */ +#define RX_STAT_ERRORS 0x1B800000 + +/* a single TX descriptor. The controller has an array of these */ +struct lpc32xx_eth_txdesc { + u32 packet; /* Transmit packet pointer */ + u32 control; /* Descriptor control */ +}; + +#define LPC32XX_ETH_TX_DESC_SIZE (sizeof(struct lpc32xx_eth_txdesc)) + +/* TX control bitfields/masks (see Table 335) */ +#define TX_CTRL_TXSIZE 0x000007FF +#define TX_CTRL_LAST 0x40000000 + +/* a single TX status. The controller has an array of these */ +struct lpc32xx_eth_txstat { + u32 statusinfo; /* Transmit Descriptor status */ +}; + +#define LPC32XX_ETH_TX_STAT_SIZE (sizeof(struct lpc32xx_eth_txstat)) + +/* Ethernet MAC interface registers (see Table 283) */ +struct lpc32xx_eth_registers { + /* MAC registers - 0x3106_0000 to 0x3106_01FC */ + u32 mac1; /* MAC configuration register 1 */ + u32 mac2; /* MAC configuration register 2 */ + u32 ipgt; /* Back-to-back Inter-Packet Gap reg. */ + u32 ipgr; /* Non-back-to-back IPG register */ + u32 clrt; /* Collision Window / Retry register */ + u32 maxf; /* Maximum Frame register */ + u32 supp; /* Phy Support register */ + u32 test; + u32 mcfg; /* MII management configuration reg. */ + u32 mcmd; /* MII management command register */ + u32 madr; /* MII management address register */ + u32 mwtd; /* MII management wite data register */ + u32 mrdd; /* MII management read data register */ + u32 mind; /* MII management indicators register */ + u32 reserved1[2]; + u32 sa0; /* Station address register 0 */ + u32 sa1; /* Station address register 1 */ + u32 sa2; /* Station address register 2 */ + u32 reserved2[45]; + /* Control registers */ + u32 command; + u32 status; + u32 rxdescriptor; + u32 rxstatus; + u32 rxdescriptornumber; /* actually, number MINUS ONE */ + u32 rxproduceindex; /* head of rx desc fifo */ + u32 rxconsumeindex; /* tail of rx desc fifo */ + u32 txdescriptor; + u32 txstatus; + u32 txdescriptornumber; /* actually, number MINUS ONE */ + u32 txproduceindex; /* head of rx desc fifo */ + u32 txconsumeindex; /* tail of rx desc fifo */ + u32 reserved3[10]; + u32 tsv0; /* Transmit status vector register 0 */ + u32 tsv1; /* Transmit status vector register 1 */ + u32 rsv; /* Receive status vector register */ + u32 reserved4[3]; + u32 flowcontrolcounter; + u32 flowcontrolstatus; + u32 reserved5[34]; + /* RX filter registers - 0x3106_0200 to 0x3106_0FDC */ + u32 rxfilterctrl; + u32 rxfilterwolstatus; + u32 rxfilterwolclear; + u32 reserved6; + u32 hashfilterl; + u32 hashfilterh; + u32 reserved7[882]; + /* Module control registers - 0x3106_0FE0 to 0x3106_0FF8 */ + u32 intstatus; /* Interrupt status register */ + u32 intenable; + u32 intclear; + u32 intset; + u32 reserved8; + u32 powerdown; + u32 reserved9; +}; + +/* MAC1 register bitfields/masks and offsets (see Table 283) */ +#define MAC1_RECV_ENABLE 0x00000001 +#define MAC1_PASS_ALL_RX_FRAMES 0x00000002 +#define MAC1_SOFT_RESET 0x00008000 +/* Helper: general reset */ +#define MAC1_RESETS 0x0000CF00 + +/* MAC2 register bitfields/masks and offsets (see Table 284) */ +#define MAC2_FULL_DUPLEX 0x00000001 +#define MAC2_CRC_ENABLE 0x00000010 +#define MAC2_PAD_CRC_ENABLE 0x00000020 + +/* SUPP register bitfields/masks and offsets (see Table 290) */ +#define SUPP_SPEED 0x00000100 + +/* MCFG register bitfields/masks and offsets (see Table 292) */ +#define MCFG_RESET_MII_MGMT 0x00008000 +/* divide clock by 28 (see Table 293) */ +#define MCFG_CLOCK_SELECT_DIV28 0x0000001C + +/* MADR register bitfields/masks and offsets (see Table 295) */ +#define MADR_REG_MASK 0x0000001F +#define MADR_PHY_MASK 0x00001F00 +#define MADR_REG_OFFSET 0 +#define MADR_PHY_OFFSET 8 + +/* MIND register bitfields/masks (see Table 298) */ +#define MIND_BUSY 0x00000001 + +/* COMMAND register bitfields/masks and offsets (see Table 283) */ +#define COMMAND_RXENABLE 0x00000001 +#define COMMAND_TXENABLE 0x00000002 +#define COMMAND_PASSRUNTFRAME 0x00000040 +#define COMMAND_RMII 0x00000200 +#define COMMAND_FULL_DUPLEX 0x00000400 +/* Helper: general reset */ +#define COMMAND_RESETS 0x00000038 + +/* STATUS register bitfields/masks and offsets (see Table 283) */ +#define STATUS_RXSTATUS 0x00000001 +#define STATUS_TXSTATUS 0x00000002 + +/* RXFILTERCTRL register bitfields/masks (see Table 319) */ +#define RXFILTERCTRL_ACCEPTBROADCAST 0x00000002 +#define RXFILTERCTRL_ACCEPTPERFECT 0x00000020 + +/* Buffers and descriptors */ + +#define ATTRS(n) __aligned(n) + +#define TX_BUF_COUNT 4 +#define RX_BUF_COUNT 4 + +struct lpc32xx_eth_buffers { + ATTRS(4) struct lpc32xx_eth_txdesc tx_desc[TX_BUF_COUNT]; + ATTRS(4) struct lpc32xx_eth_txstat tx_stat[TX_BUF_COUNT]; + ATTRS(PKTALIGN) u8 tx_buf[TX_BUF_COUNT*PKTSIZE_ALIGN]; + ATTRS(4) struct lpc32xx_eth_rxdesc rx_desc[RX_BUF_COUNT]; + ATTRS(8) struct lpc32xx_eth_rxstat rx_stat[RX_BUF_COUNT]; + ATTRS(PKTALIGN) u8 rx_buf[RX_BUF_COUNT*PKTSIZE_ALIGN]; +}; + +/* port device data struct */ +struct lpc32xx_eth_device { + struct eth_device dev; + struct lpc32xx_eth_registers *regs; + struct lpc32xx_eth_buffers *bufs; + bool phy_rmii; +}; + +#define LPC32XX_ETH_DEVICE_SIZE (sizeof(struct lpc32xx_eth_device)) + +/* generic macros */ +#define to_lpc32xx_eth(_d) container_of(_d, struct lpc32xx_eth_device, dev) + +/* timeout for MII polling */ +#define MII_TIMEOUT 10000000 + +/* limits for PHY and register addresses */ +#define MII_MAX_REG (MADR_REG_MASK >> MADR_REG_OFFSET) + +#define MII_MAX_PHY (MADR_PHY_MASK >> MADR_PHY_OFFSET) + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_PHYLIB) || defined(CONFIG_MII) || defined(CONFIG_CMD_MII) +/* + * mii_reg_read - miiphy_read callback function. + * + * Returns 16bit phy register value, or 0xffff on error + */ +static int mii_reg_read(const char *devname, u8 phy_adr, u8 reg_ofs, u16 *data) +{ + struct eth_device *dev = eth_get_dev_by_name(devname); + struct lpc32xx_eth_device *dlpc32xx_eth = to_lpc32xx_eth(dev); + struct lpc32xx_eth_registers *regs = dlpc32xx_eth->regs; + u32 mind_reg; + u32 timeout; + + /* check parameters */ + if (phy_adr > MII_MAX_PHY) { + printf("%s:%u: Invalid PHY address %d\n", + __func__, __LINE__, phy_adr); + return -EFAULT; + } + if (reg_ofs > MII_MAX_REG) { + printf("%s:%u: Invalid register offset %d\n", + __func__, __LINE__, reg_ofs); + return -EFAULT; + } + + /* write the phy and reg addressse into the MII address reg */ + writel((phy_adr << MADR_PHY_OFFSET) | (reg_ofs << MADR_REG_OFFSET), + ®s->madr); + + /* write 1 to the MII command register to cause a read */ + writel(1, ®s->mcmd); + + /* wait till the MII is not busy */ + timeout = MII_TIMEOUT; + do { + /* read MII indicators register */ + mind_reg = readl(®s->mind); + if (--timeout == 0) + break; + } while (mind_reg & MIND_BUSY); + + /* write 0 to the MII command register to finish the read */ + writel(0, ®s->mcmd); + + if (timeout == 0) { + printf("%s:%u: MII busy timeout\n", __func__, __LINE__); + return -EFAULT; + } + + *data = (u16) readl(®s->mrdd); + + debug("%s:(adr %d, off %d) => %04x\n", __func__, phy_adr, + reg_ofs, *data); + + return 0; +} + +/* + * mii_reg_write - imiiphy_write callback function. + * + * Returns 0 if write succeed, -EINVAL on bad parameters + * -ETIME on timeout + */ +static int mii_reg_write(const char *devname, u8 phy_adr, u8 reg_ofs, u16 data) +{ + struct eth_device *dev = eth_get_dev_by_name(devname); + struct lpc32xx_eth_device *dlpc32xx_eth = to_lpc32xx_eth(dev); + struct lpc32xx_eth_registers *regs = dlpc32xx_eth->regs; + u32 mind_reg; + u32 timeout; + + /* check parameters */ + if (phy_adr > MII_MAX_PHY) { + printf("%s:%u: Invalid PHY address %d\n", + __func__, __LINE__, phy_adr); + return -EFAULT; + } + if (reg_ofs > MII_MAX_REG) { + printf("%s:%u: Invalid register offset %d\n", + __func__, __LINE__, reg_ofs); + return -EFAULT; + } + + /* wait till the MII is not busy */ + timeout = MII_TIMEOUT; + do { + /* read MII indicators register */ + mind_reg = readl(®s->mind); + if (--timeout == 0) + break; + } while (mind_reg & MIND_BUSY); + + if (timeout == 0) { + printf("%s:%u: MII busy timeout\n", __func__, + __LINE__); + return -EFAULT; + } + + /* write the phy and reg addressse into the MII address reg */ + writel((phy_adr << MADR_PHY_OFFSET) | (reg_ofs << MADR_REG_OFFSET), + ®s->madr); + + /* write data to the MII write register */ + writel(data, ®s->mwtd); + + /*debug("%s:(adr %d, off %d) <= %04x\n", __func__, phy_adr, + reg_ofs, data);*/ + + return 0; +} +#endif + +#if defined(CONFIG_PHYLIB) +int lpc32xx_eth_phy_read(struct mii_dev *bus, int phy_addr, int dev_addr, + int reg_addr) +{ + u16 data; + int ret; + ret = mii_reg_read(bus->name, phy_addr, reg_addr, &data); + if (ret) + return ret; + return data; +} + +int lpc32xx_eth_phy_write(struct mii_dev *bus, int phy_addr, int dev_addr, + int reg_addr, u16 data) +{ + return mii_reg_write(bus->name, phy_addr, reg_addr, data); +} +#endif + +/* + * Provide default Ethernet buffers base address if target did not. + * Locate buffers in SRAM at 0x00001000 to avoid cache issues and + * maximize throughput. + */ +#if !defined(CONFIG_LPC32XX_ETH_BUFS_BASE) +#define CONFIG_LPC32XX_ETH_BUFS_BASE 0x00001000 +#endif + +static struct lpc32xx_eth_device lpc32xx_eth = { + .regs = (struct lpc32xx_eth_registers *)LPC32XX_ETH_BASE, + .bufs = (struct lpc32xx_eth_buffers *)CONFIG_LPC32XX_ETH_BUFS_BASE, +#if defined(CONFIG_RMII) + .phy_rmii = true, +#endif +}; + +#define TX_TIMEOUT 10000 + +static int lpc32xx_eth_send(struct eth_device *dev, void *dataptr, int datasize) +{ + struct lpc32xx_eth_device *lpc32xx_eth_device = + container_of(dev, struct lpc32xx_eth_device, dev); + struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs; + struct lpc32xx_eth_buffers *bufs = lpc32xx_eth_device->bufs; + int timeout, tx_index; + + /* time out if transmit descriptor array remains full too long */ + timeout = TX_TIMEOUT; + while ((readl(®s->status) & STATUS_TXSTATUS) && + (readl(®s->txconsumeindex) + == readl(®s->txproduceindex))) { + if (timeout-- == 0) + return -1; + } + + /* determine next transmit packet index to use */ + tx_index = readl(®s->txproduceindex); + + /* set up transmit packet */ + writel((u32)dataptr, &bufs->tx_desc[tx_index].packet); + writel(TX_CTRL_LAST | ((datasize - 1) & TX_CTRL_TXSIZE), + &bufs->tx_desc[tx_index].control); + writel(0, &bufs->tx_stat[tx_index].statusinfo); + + /* pass transmit packet to DMA engine */ + tx_index = (tx_index + 1) % TX_BUF_COUNT; + writel(tx_index, ®s->txproduceindex); + + /* transmission succeeded */ + return 0; +} + +#define RX_TIMEOUT 1000000 + +static int lpc32xx_eth_recv(struct eth_device *dev) +{ + struct lpc32xx_eth_device *lpc32xx_eth_device = + container_of(dev, struct lpc32xx_eth_device, dev); + struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs; + struct lpc32xx_eth_buffers *bufs = lpc32xx_eth_device->bufs; + int timeout, rx_index; + + /* time out if receive descriptor array remains empty too long */ + timeout = RX_TIMEOUT; + while (readl(®s->rxproduceindex) == readl(®s->rxconsumeindex)) { + if (timeout-- == 0) + return -1; + } + + /* determine next receive packet index to use */ + rx_index = readl(®s->rxconsumeindex); + + /* if data was valid, pass it on */ + if (!(bufs->rx_stat[rx_index].statusinfo & RX_STAT_ERRORS)) { + net_process_received_packet( + &(bufs->rx_buf[rx_index * PKTSIZE_ALIGN]), + (bufs->rx_stat[rx_index].statusinfo + & RX_STAT_RXSIZE) + 1); + } + + /* pass receive slot back to DMA engine */ + rx_index = (rx_index + 1) % RX_BUF_COUNT; + writel(rx_index, ®s->rxconsumeindex); + + /* reception successful */ + return 0; +} + +static int lpc32xx_eth_write_hwaddr(struct eth_device *dev) +{ + struct lpc32xx_eth_device *lpc32xx_eth_device = + container_of(dev, struct lpc32xx_eth_device, dev); + struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs; + + /* Save station address */ + writel((unsigned long) (dev->enetaddr[0] | + (dev->enetaddr[1] << 8)), ®s->sa2); + writel((unsigned long) (dev->enetaddr[2] | + (dev->enetaddr[3] << 8)), ®s->sa1); + writel((unsigned long) (dev->enetaddr[4] | + (dev->enetaddr[5] << 8)), ®s->sa0); + + return 0; +} + +static int lpc32xx_eth_init(struct eth_device *dev) +{ + struct lpc32xx_eth_device *lpc32xx_eth_device = + container_of(dev, struct lpc32xx_eth_device, dev); + struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs; + struct lpc32xx_eth_buffers *bufs = lpc32xx_eth_device->bufs; + int index; + + /* Initial MAC initialization */ + writel(MAC1_PASS_ALL_RX_FRAMES, ®s->mac1); + writel(MAC2_PAD_CRC_ENABLE | MAC2_CRC_ENABLE, ®s->mac2); + writel(PKTSIZE_ALIGN, ®s->maxf); + + /* Retries: 15 (0xF). Collision window: 57 (0x37). */ + writel(0x370F, ®s->clrt); + + /* Set IP gap pt 2 to default 0x12 but pt 1 to non-default 0 */ + writel(0x0012, ®s->ipgr); + + /* pass runt (smaller than 64 bytes) frames */ + if (lpc32xx_eth_device->phy_rmii) + writel(COMMAND_PASSRUNTFRAME | COMMAND_RMII, ®s->command); + else + writel(COMMAND_PASSRUNTFRAME, ®s->command); + + /* Configure Full/Half Duplex mode */ + if (miiphy_duplex(dev->name, CONFIG_PHY_ADDR) == FULL) { + setbits_le32(®s->mac2, MAC2_FULL_DUPLEX); + setbits_le32(®s->command, COMMAND_FULL_DUPLEX); + writel(0x15, ®s->ipgt); + } else { + writel(0x12, ®s->ipgt); + } + + /* Configure 100MBit/10MBit mode */ + if (miiphy_speed(dev->name, CONFIG_PHY_ADDR) == _100BASET) + writel(SUPP_SPEED, ®s->supp); + else + writel(0, ®s->supp); + + /* Save station address */ + writel((unsigned long) (dev->enetaddr[0] | + (dev->enetaddr[1] << 8)), ®s->sa2); + writel((unsigned long) (dev->enetaddr[2] | + (dev->enetaddr[3] << 8)), ®s->sa1); + writel((unsigned long) (dev->enetaddr[4] | + (dev->enetaddr[5] << 8)), ®s->sa0); + + /* set up transmit buffers */ + for (index = 0; index < TX_BUF_COUNT; index++) { + bufs->tx_desc[index].control = 0; + bufs->tx_stat[index].statusinfo = 0; + } + writel((u32)(&bufs->tx_desc), (u32 *)®s->txdescriptor); + writel((u32)(&bufs->tx_stat), ®s->txstatus); + writel(TX_BUF_COUNT-1, ®s->txdescriptornumber); + + /* set up receive buffers */ + for (index = 0; index < RX_BUF_COUNT; index++) { + bufs->rx_desc[index].packet = + (u32) (bufs->rx_buf+index*PKTSIZE_ALIGN); + bufs->rx_desc[index].control = PKTSIZE_ALIGN - 1; + bufs->rx_stat[index].statusinfo = 0; + bufs->rx_stat[index].statushashcrc = 0; + } + writel((u32)(&bufs->rx_desc), ®s->rxdescriptor); + writel((u32)(&bufs->rx_stat), ®s->rxstatus); + writel(RX_BUF_COUNT-1, ®s->rxdescriptornumber); + + /* Enable broadcast and matching address packets */ + writel(RXFILTERCTRL_ACCEPTBROADCAST | + RXFILTERCTRL_ACCEPTPERFECT, ®s->rxfilterctrl); + + /* Clear and disable interrupts */ + writel(0xFFFF, ®s->intclear); + writel(0, ®s->intenable); + + /* Enable receive and transmit mode of MAC ethernet core */ + setbits_le32(®s->command, COMMAND_RXENABLE | COMMAND_TXENABLE); + setbits_le32(®s->mac1, MAC1_RECV_ENABLE); + + /* + * Perform a 'dummy' first send to work around Ethernet.1 + * erratum (see ES_LPC3250 rev. 9 dated 1 June 2011). + * Use zeroed "index" variable as the dummy. + */ + + index = 0; + lpc32xx_eth_send(dev, &index, 4); + + return 0; +} + +static int lpc32xx_eth_halt(struct eth_device *dev) +{ + struct lpc32xx_eth_device *lpc32xx_eth_device = + container_of(dev, struct lpc32xx_eth_device, dev); + struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs; + + /* Reset all MAC logic */ + writel(MAC1_RESETS, ®s->mac1); + writel(COMMAND_RESETS, ®s->command); + /* Let reset condition settle */ + udelay(2000); + + return 0; +} + +#if defined(CONFIG_PHYLIB) +int lpc32xx_eth_phylib_init(struct eth_device *dev, int phyid) +{ + struct lpc32xx_eth_device *lpc32xx_eth_device = + container_of(dev, struct lpc32xx_eth_device, dev); + struct mii_dev *bus; + struct phy_device *phydev; + int ret; + + bus = mdio_alloc(); + if (!bus) { + printf("mdio_alloc failed\n"); + return -ENOMEM; + } + bus->read = lpc32xx_eth_phy_read; + bus->write = lpc32xx_eth_phy_write; + sprintf(bus->name, dev->name); + + ret = mdio_register(bus); + if (ret) { + printf("mdio_register failed\n"); + free(bus); + return -ENOMEM; + } + + if (lpc32xx_eth_device->phy_rmii) + phydev = phy_connect(bus, phyid, dev, PHY_INTERFACE_MODE_RMII); + else + phydev = phy_connect(bus, phyid, dev, PHY_INTERFACE_MODE_MII); + + if (!phydev) { + printf("phy_connect failed\n"); + return -ENODEV; + } + + phy_config(phydev); + phy_startup(phydev); + + return 0; +} +#endif + +int lpc32xx_eth_initialize(bd_t *bis) +{ + struct eth_device *dev = &lpc32xx_eth.dev; + struct lpc32xx_eth_registers *regs = lpc32xx_eth.regs; + + /* + * Set RMII management clock rate. With HCLK at 104 MHz and + * a divider of 28, this will be 3.72 MHz. + */ + writel(MCFG_RESET_MII_MGMT, ®s->mcfg); + writel(MCFG_CLOCK_SELECT_DIV28, ®s->mcfg); + + /* Reset all MAC logic */ + writel(MAC1_RESETS, ®s->mac1); + writel(COMMAND_RESETS, ®s->command); + + /* wait 10 ms for the whole I/F to reset */ + udelay(10000); + + /* must be less than sizeof(dev->name) */ + strcpy(dev->name, "eth0"); + + dev->init = (void *)lpc32xx_eth_init; + dev->halt = (void *)lpc32xx_eth_halt; + dev->send = (void *)lpc32xx_eth_send; + dev->recv = (void *)lpc32xx_eth_recv; + dev->write_hwaddr = (void *)lpc32xx_eth_write_hwaddr; + + /* Release SOFT reset to let MII talk to PHY */ + clrbits_le32(®s->mac1, MAC1_SOFT_RESET); + + /* register driver before talking to phy */ + eth_register(dev); + +#if defined(CONFIG_PHYLIB) + lpc32xx_eth_phylib_init(dev, CONFIG_PHY_ADDR); +#elif defined(CONFIG_MII) || defined(CONFIG_CMD_MII) + miiphy_register(dev->name, mii_reg_read, mii_reg_write); +#endif + + return 0; +} diff --git a/sources/uboot-be550/drivers/net/macb.c b/sources/uboot-be550/drivers/net/macb.c new file mode 100644 index 00000000..a5c18806 --- /dev/null +++ b/sources/uboot-be550/drivers/net/macb.c @@ -0,0 +1,787 @@ +/* + * Copyright (C) 2005-2006 Atmel Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include + +/* + * The u-boot networking stack is a little weird. It seems like the + * networking core allocates receive buffers up front without any + * regard to the hardware that's supposed to actually receive those + * packets. + * + * The MACB receives packets into 128-byte receive buffers, so the + * buffers allocated by the core isn't very practical to use. We'll + * allocate our own, but we need one such buffer in case a packet + * wraps around the DMA ring so that we have to copy it. + * + * Therefore, define CONFIG_SYS_RX_ETH_BUFFER to 1 in the board-specific + * configuration header. This way, the core allocates one RX buffer + * and one TX buffer, each of which can hold a ethernet packet of + * maximum size. + * + * For some reason, the networking core unconditionally specifies a + * 32-byte packet "alignment" (which really should be called + * "padding"). MACB shouldn't need that, but we'll refrain from any + * core modifications here... + */ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "macb.h" + +#define MACB_RX_BUFFER_SIZE 4096 +#define MACB_RX_RING_SIZE (MACB_RX_BUFFER_SIZE / 128) +#define MACB_TX_RING_SIZE 16 +#define MACB_TX_TIMEOUT 1000 +#define MACB_AUTONEG_TIMEOUT 5000000 + +struct macb_dma_desc { + u32 addr; + u32 ctrl; +}; + +#define DMA_DESC_BYTES(n) (n * sizeof(struct macb_dma_desc)) +#define MACB_TX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_TX_RING_SIZE)) +#define MACB_RX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_RX_RING_SIZE)) +#define MACB_TX_DUMMY_DMA_DESC_SIZE (DMA_DESC_BYTES(1)) + +#define RXADDR_USED 0x00000001 +#define RXADDR_WRAP 0x00000002 + +#define RXBUF_FRMLEN_MASK 0x00000fff +#define RXBUF_FRAME_START 0x00004000 +#define RXBUF_FRAME_END 0x00008000 +#define RXBUF_TYPEID_MATCH 0x00400000 +#define RXBUF_ADDR4_MATCH 0x00800000 +#define RXBUF_ADDR3_MATCH 0x01000000 +#define RXBUF_ADDR2_MATCH 0x02000000 +#define RXBUF_ADDR1_MATCH 0x04000000 +#define RXBUF_BROADCAST 0x80000000 + +#define TXBUF_FRMLEN_MASK 0x000007ff +#define TXBUF_FRAME_END 0x00008000 +#define TXBUF_NOCRC 0x00010000 +#define TXBUF_EXHAUSTED 0x08000000 +#define TXBUF_UNDERRUN 0x10000000 +#define TXBUF_MAXRETRY 0x20000000 +#define TXBUF_WRAP 0x40000000 +#define TXBUF_USED 0x80000000 + +struct macb_device { + void *regs; + + unsigned int rx_tail; + unsigned int tx_head; + unsigned int tx_tail; + + void *rx_buffer; + void *tx_buffer; + struct macb_dma_desc *rx_ring; + struct macb_dma_desc *tx_ring; + + unsigned long rx_buffer_dma; + unsigned long rx_ring_dma; + unsigned long tx_ring_dma; + + struct macb_dma_desc *dummy_desc; + unsigned long dummy_desc_dma; + + const struct device *dev; + struct eth_device netdev; + unsigned short phy_addr; + struct mii_dev *bus; +}; +#define to_macb(_nd) container_of(_nd, struct macb_device, netdev) + +static int macb_is_gem(struct macb_device *macb) +{ + return MACB_BFEXT(IDNUM, macb_readl(macb, MID)) == 0x2; +} + +static void macb_mdio_write(struct macb_device *macb, u8 reg, u16 value) +{ + unsigned long netctl; + unsigned long netstat; + unsigned long frame; + + netctl = macb_readl(macb, NCR); + netctl |= MACB_BIT(MPE); + macb_writel(macb, NCR, netctl); + + frame = (MACB_BF(SOF, 1) + | MACB_BF(RW, 1) + | MACB_BF(PHYA, macb->phy_addr) + | MACB_BF(REGA, reg) + | MACB_BF(CODE, 2) + | MACB_BF(DATA, value)); + macb_writel(macb, MAN, frame); + + do { + netstat = macb_readl(macb, NSR); + } while (!(netstat & MACB_BIT(IDLE))); + + netctl = macb_readl(macb, NCR); + netctl &= ~MACB_BIT(MPE); + macb_writel(macb, NCR, netctl); +} + +static u16 macb_mdio_read(struct macb_device *macb, u8 reg) +{ + unsigned long netctl; + unsigned long netstat; + unsigned long frame; + + netctl = macb_readl(macb, NCR); + netctl |= MACB_BIT(MPE); + macb_writel(macb, NCR, netctl); + + frame = (MACB_BF(SOF, 1) + | MACB_BF(RW, 2) + | MACB_BF(PHYA, macb->phy_addr) + | MACB_BF(REGA, reg) + | MACB_BF(CODE, 2)); + macb_writel(macb, MAN, frame); + + do { + netstat = macb_readl(macb, NSR); + } while (!(netstat & MACB_BIT(IDLE))); + + frame = macb_readl(macb, MAN); + + netctl = macb_readl(macb, NCR); + netctl &= ~MACB_BIT(MPE); + macb_writel(macb, NCR, netctl); + + return MACB_BFEXT(DATA, frame); +} + +void __weak arch_get_mdio_control(const char *name) +{ + return; +} + +#if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) + +int macb_miiphy_read(const char *devname, u8 phy_adr, u8 reg, u16 *value) +{ + struct eth_device *dev = eth_get_dev_by_name(devname); + struct macb_device *macb = to_macb(dev); + + if (macb->phy_addr != phy_adr) + return -1; + + arch_get_mdio_control(devname); + *value = macb_mdio_read(macb, reg); + + return 0; +} + +int macb_miiphy_write(const char *devname, u8 phy_adr, u8 reg, u16 value) +{ + struct eth_device *dev = eth_get_dev_by_name(devname); + struct macb_device *macb = to_macb(dev); + + if (macb->phy_addr != phy_adr) + return -1; + + arch_get_mdio_control(devname); + macb_mdio_write(macb, reg, value); + + return 0; +} +#endif + +#define RX 1 +#define TX 0 +static inline void macb_invalidate_ring_desc(struct macb_device *macb, bool rx) +{ + if (rx) + invalidate_dcache_range(macb->rx_ring_dma, macb->rx_ring_dma + + MACB_RX_DMA_DESC_SIZE); + else + invalidate_dcache_range(macb->tx_ring_dma, macb->tx_ring_dma + + MACB_TX_DMA_DESC_SIZE); +} + +static inline void macb_flush_ring_desc(struct macb_device *macb, bool rx) +{ + if (rx) + flush_dcache_range(macb->rx_ring_dma, macb->rx_ring_dma + + MACB_RX_DMA_DESC_SIZE); + else + flush_dcache_range(macb->tx_ring_dma, macb->tx_ring_dma + + MACB_TX_DMA_DESC_SIZE); +} + +static inline void macb_flush_rx_buffer(struct macb_device *macb) +{ + flush_dcache_range(macb->rx_buffer_dma, macb->rx_buffer_dma + + MACB_RX_BUFFER_SIZE); +} + +static inline void macb_invalidate_rx_buffer(struct macb_device *macb) +{ + invalidate_dcache_range(macb->rx_buffer_dma, macb->rx_buffer_dma + + MACB_RX_BUFFER_SIZE); +} + +#if defined(CONFIG_CMD_NET) + +static int macb_send(struct eth_device *netdev, void *packet, int length) +{ + struct macb_device *macb = to_macb(netdev); + unsigned long paddr, ctrl; + unsigned int tx_head = macb->tx_head; + int i; + + paddr = dma_map_single(packet, length, DMA_TO_DEVICE); + + ctrl = length & TXBUF_FRMLEN_MASK; + ctrl |= TXBUF_FRAME_END; + if (tx_head == (MACB_TX_RING_SIZE - 1)) { + ctrl |= TXBUF_WRAP; + macb->tx_head = 0; + } else { + macb->tx_head++; + } + + macb->tx_ring[tx_head].ctrl = ctrl; + macb->tx_ring[tx_head].addr = paddr; + barrier(); + macb_flush_ring_desc(macb, TX); + /* Do we need check paddr and length is dcache line aligned? */ + flush_dcache_range(paddr, paddr + length); + macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART)); + + /* + * I guess this is necessary because the networking core may + * re-use the transmit buffer as soon as we return... + */ + for (i = 0; i <= MACB_TX_TIMEOUT; i++) { + barrier(); + macb_invalidate_ring_desc(macb, TX); + ctrl = macb->tx_ring[tx_head].ctrl; + if (ctrl & TXBUF_USED) + break; + udelay(1); + } + + dma_unmap_single(packet, length, paddr); + + if (i <= MACB_TX_TIMEOUT) { + if (ctrl & TXBUF_UNDERRUN) + printf("%s: TX underrun\n", netdev->name); + if (ctrl & TXBUF_EXHAUSTED) + printf("%s: TX buffers exhausted in mid frame\n", + netdev->name); + } else { + printf("%s: TX timeout\n", netdev->name); + } + + /* No one cares anyway */ + return 0; +} + +static void reclaim_rx_buffers(struct macb_device *macb, + unsigned int new_tail) +{ + unsigned int i; + + i = macb->rx_tail; + + macb_invalidate_ring_desc(macb, RX); + while (i > new_tail) { + macb->rx_ring[i].addr &= ~RXADDR_USED; + i++; + if (i > MACB_RX_RING_SIZE) + i = 0; + } + + while (i < new_tail) { + macb->rx_ring[i].addr &= ~RXADDR_USED; + i++; + } + + barrier(); + macb_flush_ring_desc(macb, RX); + macb->rx_tail = new_tail; +} + +static int macb_recv(struct eth_device *netdev) +{ + struct macb_device *macb = to_macb(netdev); + unsigned int rx_tail = macb->rx_tail; + void *buffer; + int length; + int wrapped = 0; + u32 status; + + for (;;) { + macb_invalidate_ring_desc(macb, RX); + + if (!(macb->rx_ring[rx_tail].addr & RXADDR_USED)) + return -1; + + status = macb->rx_ring[rx_tail].ctrl; + if (status & RXBUF_FRAME_START) { + if (rx_tail != macb->rx_tail) + reclaim_rx_buffers(macb, rx_tail); + wrapped = 0; + } + + if (status & RXBUF_FRAME_END) { + buffer = macb->rx_buffer + 128 * macb->rx_tail; + length = status & RXBUF_FRMLEN_MASK; + + macb_invalidate_rx_buffer(macb); + if (wrapped) { + unsigned int headlen, taillen; + + headlen = 128 * (MACB_RX_RING_SIZE + - macb->rx_tail); + taillen = length - headlen; + memcpy((void *)net_rx_packets[0], + buffer, headlen); + memcpy((void *)net_rx_packets[0] + headlen, + macb->rx_buffer, taillen); + buffer = (void *)net_rx_packets[0]; + } + + net_process_received_packet(buffer, length); + if (++rx_tail >= MACB_RX_RING_SIZE) + rx_tail = 0; + reclaim_rx_buffers(macb, rx_tail); + } else { + if (++rx_tail >= MACB_RX_RING_SIZE) { + wrapped = 1; + rx_tail = 0; + } + } + barrier(); + } + + return 0; +} + +static void macb_phy_reset(struct macb_device *macb) +{ + struct eth_device *netdev = &macb->netdev; + int i; + u16 status, adv; + + adv = ADVERTISE_CSMA | ADVERTISE_ALL; + macb_mdio_write(macb, MII_ADVERTISE, adv); + printf("%s: Starting autonegotiation...\n", netdev->name); + macb_mdio_write(macb, MII_BMCR, (BMCR_ANENABLE + | BMCR_ANRESTART)); + + for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) { + status = macb_mdio_read(macb, MII_BMSR); + if (status & BMSR_ANEGCOMPLETE) + break; + udelay(100); + } + + if (status & BMSR_ANEGCOMPLETE) + printf("%s: Autonegotiation complete\n", netdev->name); + else + printf("%s: Autonegotiation timed out (status=0x%04x)\n", + netdev->name, status); +} + +#ifdef CONFIG_MACB_SEARCH_PHY +static int macb_phy_find(struct macb_device *macb) +{ + int i; + u16 phy_id; + + /* Search for PHY... */ + for (i = 0; i < 32; i++) { + macb->phy_addr = i; + phy_id = macb_mdio_read(macb, MII_PHYSID1); + if (phy_id != 0xffff) { + printf("%s: PHY present at %d\n", macb->netdev.name, i); + return 1; + } + } + + /* PHY isn't up to snuff */ + printf("%s: PHY not found\n", macb->netdev.name); + + return 0; +} +#endif /* CONFIG_MACB_SEARCH_PHY */ + + +static int macb_phy_init(struct macb_device *macb) +{ + struct eth_device *netdev = &macb->netdev; +#ifdef CONFIG_PHYLIB + struct phy_device *phydev; +#endif + u32 ncfgr; + u16 phy_id, status, adv, lpa; + int media, speed, duplex; + int i; + + arch_get_mdio_control(netdev->name); +#ifdef CONFIG_MACB_SEARCH_PHY + /* Auto-detect phy_addr */ + if (!macb_phy_find(macb)) + return 0; +#endif /* CONFIG_MACB_SEARCH_PHY */ + + /* Check if the PHY is up to snuff... */ + phy_id = macb_mdio_read(macb, MII_PHYSID1); + if (phy_id == 0xffff) { + printf("%s: No PHY present\n", netdev->name); + return 0; + } + +#ifdef CONFIG_PHYLIB + /* need to consider other phy interface mode */ + phydev = phy_connect(macb->bus, macb->phy_addr, netdev, + PHY_INTERFACE_MODE_RGMII); + if (!phydev) { + printf("phy_connect failed\n"); + return -ENODEV; + } + + phy_config(phydev); +#endif + + status = macb_mdio_read(macb, MII_BMSR); + if (!(status & BMSR_LSTATUS)) { + /* Try to re-negotiate if we don't have link already. */ + macb_phy_reset(macb); + + for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) { + status = macb_mdio_read(macb, MII_BMSR); + if (status & BMSR_LSTATUS) + break; + udelay(100); + } + } + + if (!(status & BMSR_LSTATUS)) { + printf("%s: link down (status: 0x%04x)\n", + netdev->name, status); + return 0; + } + + /* First check for GMAC */ + if (macb_is_gem(macb)) { + lpa = macb_mdio_read(macb, MII_STAT1000); + + if (lpa & (LPA_1000FULL | LPA_1000HALF)) { + duplex = ((lpa & LPA_1000FULL) ? 1 : 0); + + printf("%s: link up, 1000Mbps %s-duplex (lpa: 0x%04x)\n", + netdev->name, + duplex ? "full" : "half", + lpa); + + ncfgr = macb_readl(macb, NCFGR); + ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD)); + ncfgr |= GEM_BIT(GBE); + + if (duplex) + ncfgr |= MACB_BIT(FD); + + macb_writel(macb, NCFGR, ncfgr); + + return 1; + } + } + + /* fall back for EMAC checking */ + adv = macb_mdio_read(macb, MII_ADVERTISE); + lpa = macb_mdio_read(macb, MII_LPA); + media = mii_nway_result(lpa & adv); + speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) + ? 1 : 0); + duplex = (media & ADVERTISE_FULL) ? 1 : 0; + printf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n", + netdev->name, + speed ? "100" : "10", + duplex ? "full" : "half", + lpa); + + ncfgr = macb_readl(macb, NCFGR); + ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD) | GEM_BIT(GBE)); + if (speed) + ncfgr |= MACB_BIT(SPD); + if (duplex) + ncfgr |= MACB_BIT(FD); + macb_writel(macb, NCFGR, ncfgr); + + return 1; +} + +static int gmac_init_multi_queues(struct macb_device *macb) +{ + int i, num_queues = 1; + u32 queue_mask; + + /* bit 0 is never set but queue 0 always exists */ + queue_mask = gem_readl(macb, DCFG6) & 0xff; + queue_mask |= 0x1; + + for (i = 1; i < MACB_MAX_QUEUES; i++) + if (queue_mask & (1 << i)) + num_queues++; + + macb->dummy_desc->ctrl = TXBUF_USED; + macb->dummy_desc->addr = 0; + flush_dcache_range(macb->dummy_desc_dma, macb->dummy_desc_dma + + MACB_TX_DUMMY_DMA_DESC_SIZE); + + for (i = 1; i < num_queues; i++) + gem_writel_queue_TBQP(macb, macb->dummy_desc_dma, i - 1); + + return 0; +} + +static int macb_init(struct eth_device *netdev, bd_t *bd) +{ + struct macb_device *macb = to_macb(netdev); + unsigned long paddr; + int i; + + /* + * macb_halt should have been called at some point before now, + * so we'll assume the controller is idle. + */ + + /* initialize DMA descriptors */ + paddr = macb->rx_buffer_dma; + for (i = 0; i < MACB_RX_RING_SIZE; i++) { + if (i == (MACB_RX_RING_SIZE - 1)) + paddr |= RXADDR_WRAP; + macb->rx_ring[i].addr = paddr; + macb->rx_ring[i].ctrl = 0; + paddr += 128; + } + macb_flush_ring_desc(macb, RX); + macb_flush_rx_buffer(macb); + + for (i = 0; i < MACB_TX_RING_SIZE; i++) { + macb->tx_ring[i].addr = 0; + if (i == (MACB_TX_RING_SIZE - 1)) + macb->tx_ring[i].ctrl = TXBUF_USED | TXBUF_WRAP; + else + macb->tx_ring[i].ctrl = TXBUF_USED; + } + macb_flush_ring_desc(macb, TX); + + macb->rx_tail = 0; + macb->tx_head = 0; + macb->tx_tail = 0; + + macb_writel(macb, RBQP, macb->rx_ring_dma); + macb_writel(macb, TBQP, macb->tx_ring_dma); + + if (macb_is_gem(macb)) { + /* Check the multi queue and initialize the queue for tx */ + gmac_init_multi_queues(macb); + + /* + * When the GMAC IP with GE feature, this bit is used to + * select interface between RGMII and GMII. + * When the GMAC IP without GE feature, this bit is used + * to select interface between RMII and MII. + */ +#if defined(CONFIG_RGMII) || defined(CONFIG_RMII) + gem_writel(macb, UR, GEM_BIT(RGMII)); +#else + gem_writel(macb, UR, 0); +#endif + } else { + /* choose RMII or MII mode. This depends on the board */ +#ifdef CONFIG_RMII +#ifdef CONFIG_AT91FAMILY + macb_writel(macb, USRIO, MACB_BIT(RMII) | MACB_BIT(CLKEN)); +#else + macb_writel(macb, USRIO, 0); +#endif +#else +#ifdef CONFIG_AT91FAMILY + macb_writel(macb, USRIO, MACB_BIT(CLKEN)); +#else + macb_writel(macb, USRIO, MACB_BIT(MII)); +#endif +#endif /* CONFIG_RMII */ + } + + if (!macb_phy_init(macb)) + return -1; + + /* Enable TX and RX */ + macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE)); + + return 0; +} + +static void macb_halt(struct eth_device *netdev) +{ + struct macb_device *macb = to_macb(netdev); + u32 ncr, tsr; + + /* Halt the controller and wait for any ongoing transmission to end. */ + ncr = macb_readl(macb, NCR); + ncr |= MACB_BIT(THALT); + macb_writel(macb, NCR, ncr); + + do { + tsr = macb_readl(macb, TSR); + } while (tsr & MACB_BIT(TGO)); + + /* Disable TX and RX, and clear statistics */ + macb_writel(macb, NCR, MACB_BIT(CLRSTAT)); +} + +static int macb_write_hwaddr(struct eth_device *dev) +{ + struct macb_device *macb = to_macb(dev); + u32 hwaddr_bottom; + u16 hwaddr_top; + + /* set hardware address */ + hwaddr_bottom = dev->enetaddr[0] | dev->enetaddr[1] << 8 | + dev->enetaddr[2] << 16 | dev->enetaddr[3] << 24; + macb_writel(macb, SA1B, hwaddr_bottom); + hwaddr_top = dev->enetaddr[4] | dev->enetaddr[5] << 8; + macb_writel(macb, SA1T, hwaddr_top); + return 0; +} + +static u32 macb_mdc_clk_div(int id, struct macb_device *macb) +{ + u32 config; + unsigned long macb_hz = get_macb_pclk_rate(id); + + if (macb_hz < 20000000) + config = MACB_BF(CLK, MACB_CLK_DIV8); + else if (macb_hz < 40000000) + config = MACB_BF(CLK, MACB_CLK_DIV16); + else if (macb_hz < 80000000) + config = MACB_BF(CLK, MACB_CLK_DIV32); + else + config = MACB_BF(CLK, MACB_CLK_DIV64); + + return config; +} + +static u32 gem_mdc_clk_div(int id, struct macb_device *macb) +{ + u32 config; + unsigned long macb_hz = get_macb_pclk_rate(id); + + if (macb_hz < 20000000) + config = GEM_BF(CLK, GEM_CLK_DIV8); + else if (macb_hz < 40000000) + config = GEM_BF(CLK, GEM_CLK_DIV16); + else if (macb_hz < 80000000) + config = GEM_BF(CLK, GEM_CLK_DIV32); + else if (macb_hz < 120000000) + config = GEM_BF(CLK, GEM_CLK_DIV48); + else if (macb_hz < 160000000) + config = GEM_BF(CLK, GEM_CLK_DIV64); + else + config = GEM_BF(CLK, GEM_CLK_DIV96); + + return config; +} + +/* + * Get the DMA bus width field of the network configuration register that we + * should program. We find the width from decoding the design configuration + * register to find the maximum supported data bus width. + */ +static u32 macb_dbw(struct macb_device *macb) +{ + switch (GEM_BFEXT(DBWDEF, gem_readl(macb, DCFG1))) { + case 4: + return GEM_BF(DBW, GEM_DBW128); + case 2: + return GEM_BF(DBW, GEM_DBW64); + case 1: + default: + return GEM_BF(DBW, GEM_DBW32); + } +} + +int macb_eth_initialize(int id, void *regs, unsigned int phy_addr) +{ + struct macb_device *macb; + struct eth_device *netdev; + u32 ncfgr; + + macb = malloc(sizeof(struct macb_device)); + if (!macb) { + printf("Error: Failed to allocate memory for MACB%d\n", id); + return -1; + } + memset(macb, 0, sizeof(struct macb_device)); + + netdev = &macb->netdev; + + macb->rx_buffer = dma_alloc_coherent(MACB_RX_BUFFER_SIZE, + &macb->rx_buffer_dma); + macb->rx_ring = dma_alloc_coherent(MACB_RX_DMA_DESC_SIZE, + &macb->rx_ring_dma); + macb->tx_ring = dma_alloc_coherent(MACB_TX_DMA_DESC_SIZE, + &macb->tx_ring_dma); + macb->dummy_desc = dma_alloc_coherent(MACB_TX_DUMMY_DMA_DESC_SIZE, + &macb->dummy_desc_dma); + + /* TODO: we need check the rx/tx_ring_dma is dcache line aligned */ + + macb->regs = regs; + macb->phy_addr = phy_addr; + + if (macb_is_gem(macb)) + sprintf(netdev->name, "gmac%d", id); + else + sprintf(netdev->name, "macb%d", id); + + netdev->init = macb_init; + netdev->halt = macb_halt; + netdev->send = macb_send; + netdev->recv = macb_recv; + netdev->write_hwaddr = macb_write_hwaddr; + + /* + * Do some basic initialization so that we at least can talk + * to the PHY + */ + if (macb_is_gem(macb)) { + ncfgr = gem_mdc_clk_div(id, macb); + ncfgr |= macb_dbw(macb); + } else { + ncfgr = macb_mdc_clk_div(id, macb); + } + + macb_writel(macb, NCFGR, ncfgr); + + eth_register(netdev); + +#if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) + miiphy_register(netdev->name, macb_miiphy_read, macb_miiphy_write); + macb->bus = miiphy_get_dev_by_name(netdev->name); +#endif + return 0; +} + +#endif diff --git a/sources/uboot-be550/drivers/net/macb.h b/sources/uboot-be550/drivers/net/macb.h new file mode 100644 index 00000000..5bb48f44 --- /dev/null +++ b/sources/uboot-be550/drivers/net/macb.h @@ -0,0 +1,322 @@ +/* + * Copyright (C) 2005-2006 Atmel Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __DRIVERS_MACB_H__ +#define __DRIVERS_MACB_H__ + +/* MACB register offsets */ +#define MACB_NCR 0x0000 +#define MACB_NCFGR 0x0004 +#define MACB_NSR 0x0008 +#define GEM_UR 0x000c +#define MACB_TSR 0x0014 +#define MACB_RBQP 0x0018 +#define MACB_TBQP 0x001c +#define MACB_RSR 0x0020 +#define MACB_ISR 0x0024 +#define MACB_IER 0x0028 +#define MACB_IDR 0x002c +#define MACB_IMR 0x0030 +#define MACB_MAN 0x0034 +#define MACB_PTR 0x0038 +#define MACB_PFR 0x003c +#define MACB_FTO 0x0040 +#define MACB_SCF 0x0044 +#define MACB_MCF 0x0048 +#define MACB_FRO 0x004c +#define MACB_FCSE 0x0050 +#define MACB_ALE 0x0054 +#define MACB_DTF 0x0058 +#define MACB_LCOL 0x005c +#define MACB_EXCOL 0x0060 +#define MACB_TUND 0x0064 +#define MACB_CSE 0x0068 +#define MACB_RRE 0x006c +#define MACB_ROVR 0x0070 +#define MACB_RSE 0x0074 +#define MACB_ELE 0x0078 +#define MACB_RJA 0x007c +#define MACB_USF 0x0080 +#define MACB_STE 0x0084 +#define MACB_RLE 0x0088 +#define MACB_TPF 0x008c +#define MACB_HRB 0x0090 +#define MACB_HRT 0x0094 +#define MACB_SA1B 0x0098 +#define MACB_SA1T 0x009c +#define MACB_SA2B 0x00a0 +#define MACB_SA2T 0x00a4 +#define MACB_SA3B 0x00a8 +#define MACB_SA3T 0x00ac +#define MACB_SA4B 0x00b0 +#define MACB_SA4T 0x00b4 +#define MACB_TID 0x00b8 +#define MACB_TPQ 0x00bc +#define MACB_USRIO 0x00c0 +#define MACB_WOL 0x00c4 +#define MACB_MID 0x00fc + +/* GEM specific register offsets */ +#define GEM_DCFG1 0x0280 +#define GEM_DCFG6 0x0294 + +#define MACB_MAX_QUEUES 8 + +/* GEM specific multi queues register offset */ +/* hw_q can be 0~7 */ +#define GEM_TBQP(hw_q) (0x0440 + ((hw_q) << 2)) + +/* Bitfields in NCR */ +#define MACB_LB_OFFSET 0 +#define MACB_LB_SIZE 1 +#define MACB_LLB_OFFSET 1 +#define MACB_LLB_SIZE 1 +#define MACB_RE_OFFSET 2 +#define MACB_RE_SIZE 1 +#define MACB_TE_OFFSET 3 +#define MACB_TE_SIZE 1 +#define MACB_MPE_OFFSET 4 +#define MACB_MPE_SIZE 1 +#define MACB_CLRSTAT_OFFSET 5 +#define MACB_CLRSTAT_SIZE 1 +#define MACB_INCSTAT_OFFSET 6 +#define MACB_INCSTAT_SIZE 1 +#define MACB_WESTAT_OFFSET 7 +#define MACB_WESTAT_SIZE 1 +#define MACB_BP_OFFSET 8 +#define MACB_BP_SIZE 1 +#define MACB_TSTART_OFFSET 9 +#define MACB_TSTART_SIZE 1 +#define MACB_THALT_OFFSET 10 +#define MACB_THALT_SIZE 1 +#define MACB_NCR_TPF_OFFSET 11 +#define MACB_NCR_TPF_SIZE 1 +#define MACB_TZQ_OFFSET 12 +#define MACB_TZQ_SIZE 1 + +/* Bitfields in NCFGR */ +#define MACB_SPD_OFFSET 0 +#define MACB_SPD_SIZE 1 +#define MACB_FD_OFFSET 1 +#define MACB_FD_SIZE 1 +#define MACB_BIT_RATE_OFFSET 2 +#define MACB_BIT_RATE_SIZE 1 +#define MACB_JFRAME_OFFSET 3 +#define MACB_JFRAME_SIZE 1 +#define MACB_CAF_OFFSET 4 +#define MACB_CAF_SIZE 1 +#define MACB_NBC_OFFSET 5 +#define MACB_NBC_SIZE 1 +#define MACB_NCFGR_MTI_OFFSET 6 +#define MACB_NCFGR_MTI_SIZE 1 +#define MACB_UNI_OFFSET 7 +#define MACB_UNI_SIZE 1 +#define MACB_BIG_OFFSET 8 +#define MACB_BIG_SIZE 1 +#define MACB_EAE_OFFSET 9 +#define MACB_EAE_SIZE 1 +#define MACB_CLK_OFFSET 10 +#define MACB_CLK_SIZE 2 +#define MACB_RTY_OFFSET 12 +#define MACB_RTY_SIZE 1 +#define MACB_PAE_OFFSET 13 +#define MACB_PAE_SIZE 1 +#define MACB_RBOF_OFFSET 14 +#define MACB_RBOF_SIZE 2 +#define MACB_RLCE_OFFSET 16 +#define MACB_RLCE_SIZE 1 +#define MACB_DRFCS_OFFSET 17 +#define MACB_DRFCS_SIZE 1 +#define MACB_EFRHD_OFFSET 18 +#define MACB_EFRHD_SIZE 1 +#define MACB_IRXFCS_OFFSET 19 +#define MACB_IRXFCS_SIZE 1 + +#define GEM_GBE_OFFSET 10 +#define GEM_GBE_SIZE 1 +#define GEM_CLK_OFFSET 18 +#define GEM_CLK_SIZE 3 +#define GEM_DBW_OFFSET 21 +#define GEM_DBW_SIZE 2 + +/* Bitfields in NSR */ +#define MACB_NSR_LINK_OFFSET 0 +#define MACB_NSR_LINK_SIZE 1 +#define MACB_MDIO_OFFSET 1 +#define MACB_MDIO_SIZE 1 +#define MACB_IDLE_OFFSET 2 +#define MACB_IDLE_SIZE 1 + +/* Bitfields in UR */ +#define GEM_RGMII_OFFSET 0 +#define GEM_RGMII_SIZE 1 + +/* Bitfields in TSR */ +#define MACB_UBR_OFFSET 0 +#define MACB_UBR_SIZE 1 +#define MACB_COL_OFFSET 1 +#define MACB_COL_SIZE 1 +#define MACB_TSR_RLE_OFFSET 2 +#define MACB_TSR_RLE_SIZE 1 +#define MACB_TGO_OFFSET 3 +#define MACB_TGO_SIZE 1 +#define MACB_BEX_OFFSET 4 +#define MACB_BEX_SIZE 1 +#define MACB_COMP_OFFSET 5 +#define MACB_COMP_SIZE 1 +#define MACB_UND_OFFSET 6 +#define MACB_UND_SIZE 1 + +/* Bitfields in RSR */ +#define MACB_BNA_OFFSET 0 +#define MACB_BNA_SIZE 1 +#define MACB_REC_OFFSET 1 +#define MACB_REC_SIZE 1 +#define MACB_OVR_OFFSET 2 +#define MACB_OVR_SIZE 1 + +/* Bitfields in ISR/IER/IDR/IMR */ +#define MACB_MFD_OFFSET 0 +#define MACB_MFD_SIZE 1 +#define MACB_RCOMP_OFFSET 1 +#define MACB_RCOMP_SIZE 1 +#define MACB_RXUBR_OFFSET 2 +#define MACB_RXUBR_SIZE 1 +#define MACB_TXUBR_OFFSET 3 +#define MACB_TXUBR_SIZE 1 +#define MACB_ISR_TUND_OFFSET 4 +#define MACB_ISR_TUND_SIZE 1 +#define MACB_ISR_RLE_OFFSET 5 +#define MACB_ISR_RLE_SIZE 1 +#define MACB_TXERR_OFFSET 6 +#define MACB_TXERR_SIZE 1 +#define MACB_TCOMP_OFFSET 7 +#define MACB_TCOMP_SIZE 1 +#define MACB_ISR_LINK_OFFSET 9 +#define MACB_ISR_LINK_SIZE 1 +#define MACB_ISR_ROVR_OFFSET 10 +#define MACB_ISR_ROVR_SIZE 1 +#define MACB_HRESP_OFFSET 11 +#define MACB_HRESP_SIZE 1 +#define MACB_PFR_OFFSET 12 +#define MACB_PFR_SIZE 1 +#define MACB_PTZ_OFFSET 13 +#define MACB_PTZ_SIZE 1 + +/* Bitfields in MAN */ +#define MACB_DATA_OFFSET 0 +#define MACB_DATA_SIZE 16 +#define MACB_CODE_OFFSET 16 +#define MACB_CODE_SIZE 2 +#define MACB_REGA_OFFSET 18 +#define MACB_REGA_SIZE 5 +#define MACB_PHYA_OFFSET 23 +#define MACB_PHYA_SIZE 5 +#define MACB_RW_OFFSET 28 +#define MACB_RW_SIZE 2 +#define MACB_SOF_OFFSET 30 +#define MACB_SOF_SIZE 2 + +/* Bitfields in USRIO */ +#define MACB_MII_OFFSET 0 +#define MACB_MII_SIZE 1 +#define MACB_EAM_OFFSET 1 +#define MACB_EAM_SIZE 1 +#define MACB_TX_PAUSE_OFFSET 2 +#define MACB_TX_PAUSE_SIZE 1 +#define MACB_TX_PAUSE_ZERO_OFFSET 3 +#define MACB_TX_PAUSE_ZERO_SIZE 1 + +/* Bitfields in USRIO (AT91) */ +#define MACB_RMII_OFFSET 0 +#define MACB_RMII_SIZE 1 +#define MACB_CLKEN_OFFSET 1 +#define MACB_CLKEN_SIZE 1 + +/* Bitfields in WOL */ +#define MACB_IP_OFFSET 0 +#define MACB_IP_SIZE 16 +#define MACB_MAG_OFFSET 16 +#define MACB_MAG_SIZE 1 +#define MACB_ARP_OFFSET 17 +#define MACB_ARP_SIZE 1 +#define MACB_SA1_OFFSET 18 +#define MACB_SA1_SIZE 1 +#define MACB_WOL_MTI_OFFSET 19 +#define MACB_WOL_MTI_SIZE 1 + +/* Bitfields in MID */ +#define MACB_IDNUM_OFFSET 16 +#define MACB_IDNUM_SIZE 16 + +/* Bitfields in DCFG1 */ +#define GEM_DBWDEF_OFFSET 25 +#define GEM_DBWDEF_SIZE 3 + +/* constants for data bus width */ +#define GEM_DBW32 0 +#define GEM_DBW64 1 +#define GEM_DBW128 2 + +/* Constants for CLK */ +#define MACB_CLK_DIV8 0 +#define MACB_CLK_DIV16 1 +#define MACB_CLK_DIV32 2 +#define MACB_CLK_DIV64 3 + +/* GEM specific constants for CLK */ +#define GEM_CLK_DIV8 0 +#define GEM_CLK_DIV16 1 +#define GEM_CLK_DIV32 2 +#define GEM_CLK_DIV48 3 +#define GEM_CLK_DIV64 4 +#define GEM_CLK_DIV96 5 + +/* Constants for MAN register */ +#define MACB_MAN_SOF 1 +#define MACB_MAN_WRITE 1 +#define MACB_MAN_READ 2 +#define MACB_MAN_CODE 2 + +/* Bit manipulation macros */ +#define MACB_BIT(name) \ + (1 << MACB_##name##_OFFSET) +#define MACB_BF(name, value) \ + (((value) & ((1 << MACB_##name##_SIZE) - 1)) \ + << MACB_##name##_OFFSET) +#define MACB_BFEXT(name, value)\ + (((value) >> MACB_##name##_OFFSET) \ + & ((1 << MACB_##name##_SIZE) - 1)) +#define MACB_BFINS(name, value, old) \ + (((old) & ~(((1 << MACB_##name##_SIZE) - 1) \ + << MACB_##name##_OFFSET)) \ + | MACB_BF(name, value)) + +#define GEM_BIT(name) \ + (1 << GEM_##name##_OFFSET) +#define GEM_BF(name, value) \ + (((value) & ((1 << GEM_##name##_SIZE) - 1)) \ + << GEM_##name##_OFFSET) +#define GEM_BFEXT(name, value)\ + (((value) >> GEM_##name##_OFFSET) \ + & ((1 << GEM_##name##_SIZE) - 1)) +#define GEM_BFINS(name, value, old) \ + (((old) & ~(((1 << GEM_##name##_SIZE) - 1) \ + << GEM_##name##_OFFSET)) \ + | GEM_BF(name, value)) + +/* Register access macros */ +#define macb_readl(port, reg) \ + readl((port)->regs + MACB_##reg) +#define macb_writel(port, reg, value) \ + writel((value), (port)->regs + MACB_##reg) +#define gem_readl(port, reg) \ + readl((port)->regs + GEM_##reg) +#define gem_writel(port, reg, value) \ + writel((value), (port)->regs + GEM_##reg) +#define gem_writel_queue_TBQP(port, value, queue_num) \ + writel((value), (port)->regs + GEM_TBQP(queue_num)) + +#endif /* __DRIVERS_MACB_H__ */ diff --git a/sources/uboot-be550/drivers/net/mcffec.c b/sources/uboot-be550/drivers/net/mcffec.c new file mode 100644 index 00000000..fd730993 --- /dev/null +++ b/sources/uboot-be550/drivers/net/mcffec.c @@ -0,0 +1,610 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +#include +#include +#include +#include + +#include +#include + +#undef ET_DEBUG +#undef MII_DEBUG + +/* Ethernet Transmit and Receive Buffers */ +#define DBUF_LENGTH 1520 +#define TX_BUF_CNT 2 +#define PKT_MAXBUF_SIZE 1518 +#define PKT_MINBUF_SIZE 64 +#define PKT_MAXBLR_SIZE 1520 +#define LAST_PKTBUFSRX PKTBUFSRX - 1 +#define BD_ENET_RX_W_E (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY) +#define BD_ENET_TX_RDY_LST (BD_ENET_TX_READY | BD_ENET_TX_LAST) + +DECLARE_GLOBAL_DATA_PTR; + +struct fec_info_s fec_info[] = { +#ifdef CONFIG_SYS_FEC0_IOBASE + { + 0, /* index */ + CONFIG_SYS_FEC0_IOBASE, /* io base */ + CONFIG_SYS_FEC0_PINMUX, /* gpio pin muxing */ + CONFIG_SYS_FEC0_MIIBASE, /* mii base */ + -1, /* phy_addr */ + 0, /* duplex and speed */ + 0, /* phy name */ + 0, /* phyname init */ + 0, /* RX BD */ + 0, /* TX BD */ + 0, /* rx Index */ + 0, /* tx Index */ + 0, /* tx buffer */ + 0, /* initialized flag */ + (struct fec_info_s *)-1, + }, +#endif +#ifdef CONFIG_SYS_FEC1_IOBASE + { + 1, /* index */ + CONFIG_SYS_FEC1_IOBASE, /* io base */ + CONFIG_SYS_FEC1_PINMUX, /* gpio pin muxing */ + CONFIG_SYS_FEC1_MIIBASE, /* mii base */ + -1, /* phy_addr */ + 0, /* duplex and speed */ + 0, /* phy name */ + 0, /* phy name init */ +#ifdef CONFIG_SYS_FEC_BUF_USE_SRAM + (cbd_t *)DBUF_LENGTH, /* RX BD */ +#else + 0, /* RX BD */ +#endif + 0, /* TX BD */ + 0, /* rx Index */ + 0, /* tx Index */ + 0, /* tx buffer */ + 0, /* initialized flag */ + (struct fec_info_s *)-1, + } +#endif +}; + +int fec_recv(struct eth_device *dev); +int fec_init(struct eth_device *dev, bd_t * bd); +void fec_halt(struct eth_device *dev); +void fec_reset(struct eth_device *dev); + +void setFecDuplexSpeed(volatile fec_t * fecp, bd_t * bd, int dup_spd) +{ + if ((dup_spd >> 16) == FULL) { + /* Set maximum frame length */ + fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | FEC_RCR_MII_MODE | + FEC_RCR_PROM | 0x100; + fecp->tcr = FEC_TCR_FDEN; + } else { + /* Half duplex mode */ + fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | + FEC_RCR_MII_MODE | FEC_RCR_DRT; + fecp->tcr &= ~FEC_TCR_FDEN; + } + + if ((dup_spd & 0xFFFF) == _100BASET) { +#ifdef CONFIG_MCF5445x + fecp->rcr &= ~0x200; /* disabled 10T base */ +#endif +#ifdef MII_DEBUG + printf("100Mbps\n"); +#endif + bd->bi_ethspeed = 100; + } else { +#ifdef CONFIG_MCF5445x + fecp->rcr |= 0x200; /* enabled 10T base */ +#endif +#ifdef MII_DEBUG + printf("10Mbps\n"); +#endif + bd->bi_ethspeed = 10; + } +} + +static int fec_send(struct eth_device *dev, void *packet, int length) +{ + struct fec_info_s *info = dev->priv; + volatile fec_t *fecp = (fec_t *) (info->iobase); + int j, rc; + u16 phyStatus; + + miiphy_read(dev->name, info->phy_addr, MII_BMSR, &phyStatus); + + /* section 16.9.23.3 + * Wait for ready + */ + j = 0; + while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) && + (j < MCFFEC_TOUT_LOOP)) { + udelay(1); + j++; + } + if (j >= MCFFEC_TOUT_LOOP) { + printf("TX not ready\n"); + } + + info->txbd[info->txIdx].cbd_bufaddr = (uint) packet; + info->txbd[info->txIdx].cbd_datlen = length; + info->txbd[info->txIdx].cbd_sc |= BD_ENET_TX_RDY_LST; + + /* Activate transmit Buffer Descriptor polling */ + fecp->tdar = 0x01000000; /* Descriptor polling active */ + +#ifndef CONFIG_SYS_FEC_BUF_USE_SRAM + /* + * FEC unable to initial transmit data packet. + * A nop will ensure the descriptor polling active completed. + * CF Internal RAM has shorter cycle access than DRAM. If use + * DRAM as Buffer descriptor and data, a nop is a must. + * Affect only V2 and V3. + */ + __asm__ ("nop"); + +#endif + +#ifdef CONFIG_SYS_UNIFY_CACHE + icache_invalid(); +#endif + + j = 0; + while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) && + (j < MCFFEC_TOUT_LOOP)) { + udelay(1); + j++; + } + if (j >= MCFFEC_TOUT_LOOP) { + printf("TX timeout\n"); + } + +#ifdef ET_DEBUG + printf("%s[%d] %s: cycles: %d status: %x retry cnt: %d\n", + __FILE__, __LINE__, __FUNCTION__, j, + info->txbd[info->txIdx].cbd_sc, + (info->txbd[info->txIdx].cbd_sc & 0x003C) >> 2); +#endif + + /* return only status bits */ + rc = (info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_STATS); + info->txIdx = (info->txIdx + 1) % TX_BUF_CNT; + + return rc; +} + +int fec_recv(struct eth_device *dev) +{ + struct fec_info_s *info = dev->priv; + volatile fec_t *fecp = (fec_t *) (info->iobase); + int length; + + for (;;) { +#ifndef CONFIG_SYS_FEC_BUF_USE_SRAM +#endif +#ifdef CONFIG_SYS_UNIFY_CACHE + icache_invalid(); +#endif + /* section 16.9.23.2 */ + if (info->rxbd[info->rxIdx].cbd_sc & BD_ENET_RX_EMPTY) { + length = -1; + break; /* nothing received - leave for() loop */ + } + + length = info->rxbd[info->rxIdx].cbd_datlen; + + if (info->rxbd[info->rxIdx].cbd_sc & 0x003f) { + printf("%s[%d] err: %x\n", + __FUNCTION__, __LINE__, + info->rxbd[info->rxIdx].cbd_sc); +#ifdef ET_DEBUG + printf("%s[%d] err: %x\n", + __FUNCTION__, __LINE__, + info->rxbd[info->rxIdx].cbd_sc); +#endif + } else { + + length -= 4; + /* Pass the packet up to the protocol layers. */ + net_process_received_packet(net_rx_packets[info->rxIdx], + length); + + fecp->eir |= FEC_EIR_RXF; + } + + /* Give the buffer back to the FEC. */ + info->rxbd[info->rxIdx].cbd_datlen = 0; + + /* wrap around buffer index when necessary */ + if (info->rxIdx == LAST_PKTBUFSRX) { + info->rxbd[PKTBUFSRX - 1].cbd_sc = BD_ENET_RX_W_E; + info->rxIdx = 0; + } else { + info->rxbd[info->rxIdx].cbd_sc = BD_ENET_RX_EMPTY; + info->rxIdx++; + } + + /* Try to fill Buffer Descriptors */ + fecp->rdar = 0x01000000; /* Descriptor polling active */ + } + + return length; +} + +#ifdef ET_DEBUG +void dbgFecRegs(struct eth_device *dev) +{ + struct fec_info_s *info = dev->priv; + volatile fec_t *fecp = (fec_t *) (info->iobase); + + printf("=====\n"); + printf("ievent %x - %x\n", (int)&fecp->eir, fecp->eir); + printf("imask %x - %x\n", (int)&fecp->eimr, fecp->eimr); + printf("r_des_active %x - %x\n", (int)&fecp->rdar, fecp->rdar); + printf("x_des_active %x - %x\n", (int)&fecp->tdar, fecp->tdar); + printf("ecntrl %x - %x\n", (int)&fecp->ecr, fecp->ecr); + printf("mii_mframe %x - %x\n", (int)&fecp->mmfr, fecp->mmfr); + printf("mii_speed %x - %x\n", (int)&fecp->mscr, fecp->mscr); + printf("mii_ctrlstat %x - %x\n", (int)&fecp->mibc, fecp->mibc); + printf("r_cntrl %x - %x\n", (int)&fecp->rcr, fecp->rcr); + printf("x_cntrl %x - %x\n", (int)&fecp->tcr, fecp->tcr); + printf("padr_l %x - %x\n", (int)&fecp->palr, fecp->palr); + printf("padr_u %x - %x\n", (int)&fecp->paur, fecp->paur); + printf("op_pause %x - %x\n", (int)&fecp->opd, fecp->opd); + printf("iadr_u %x - %x\n", (int)&fecp->iaur, fecp->iaur); + printf("iadr_l %x - %x\n", (int)&fecp->ialr, fecp->ialr); + printf("gadr_u %x - %x\n", (int)&fecp->gaur, fecp->gaur); + printf("gadr_l %x - %x\n", (int)&fecp->galr, fecp->galr); + printf("x_wmrk %x - %x\n", (int)&fecp->tfwr, fecp->tfwr); + printf("r_bound %x - %x\n", (int)&fecp->frbr, fecp->frbr); + printf("r_fstart %x - %x\n", (int)&fecp->frsr, fecp->frsr); + printf("r_drng %x - %x\n", (int)&fecp->erdsr, fecp->erdsr); + printf("x_drng %x - %x\n", (int)&fecp->etdsr, fecp->etdsr); + printf("r_bufsz %x - %x\n", (int)&fecp->emrbr, fecp->emrbr); + + printf("\n"); + printf("rmon_t_drop %x - %x\n", (int)&fecp->rmon_t_drop, + fecp->rmon_t_drop); + printf("rmon_t_packets %x - %x\n", (int)&fecp->rmon_t_packets, + fecp->rmon_t_packets); + printf("rmon_t_bc_pkt %x - %x\n", (int)&fecp->rmon_t_bc_pkt, + fecp->rmon_t_bc_pkt); + printf("rmon_t_mc_pkt %x - %x\n", (int)&fecp->rmon_t_mc_pkt, + fecp->rmon_t_mc_pkt); + printf("rmon_t_crc_align %x - %x\n", (int)&fecp->rmon_t_crc_align, + fecp->rmon_t_crc_align); + printf("rmon_t_undersize %x - %x\n", (int)&fecp->rmon_t_undersize, + fecp->rmon_t_undersize); + printf("rmon_t_oversize %x - %x\n", (int)&fecp->rmon_t_oversize, + fecp->rmon_t_oversize); + printf("rmon_t_frag %x - %x\n", (int)&fecp->rmon_t_frag, + fecp->rmon_t_frag); + printf("rmon_t_jab %x - %x\n", (int)&fecp->rmon_t_jab, + fecp->rmon_t_jab); + printf("rmon_t_col %x - %x\n", (int)&fecp->rmon_t_col, + fecp->rmon_t_col); + printf("rmon_t_p64 %x - %x\n", (int)&fecp->rmon_t_p64, + fecp->rmon_t_p64); + printf("rmon_t_p65to127 %x - %x\n", (int)&fecp->rmon_t_p65to127, + fecp->rmon_t_p65to127); + printf("rmon_t_p128to255 %x - %x\n", (int)&fecp->rmon_t_p128to255, + fecp->rmon_t_p128to255); + printf("rmon_t_p256to511 %x - %x\n", (int)&fecp->rmon_t_p256to511, + fecp->rmon_t_p256to511); + printf("rmon_t_p512to1023 %x - %x\n", (int)&fecp->rmon_t_p512to1023, + fecp->rmon_t_p512to1023); + printf("rmon_t_p1024to2047 %x - %x\n", (int)&fecp->rmon_t_p1024to2047, + fecp->rmon_t_p1024to2047); + printf("rmon_t_p_gte2048 %x - %x\n", (int)&fecp->rmon_t_p_gte2048, + fecp->rmon_t_p_gte2048); + printf("rmon_t_octets %x - %x\n", (int)&fecp->rmon_t_octets, + fecp->rmon_t_octets); + + printf("\n"); + printf("ieee_t_drop %x - %x\n", (int)&fecp->ieee_t_drop, + fecp->ieee_t_drop); + printf("ieee_t_frame_ok %x - %x\n", (int)&fecp->ieee_t_frame_ok, + fecp->ieee_t_frame_ok); + printf("ieee_t_1col %x - %x\n", (int)&fecp->ieee_t_1col, + fecp->ieee_t_1col); + printf("ieee_t_mcol %x - %x\n", (int)&fecp->ieee_t_mcol, + fecp->ieee_t_mcol); + printf("ieee_t_def %x - %x\n", (int)&fecp->ieee_t_def, + fecp->ieee_t_def); + printf("ieee_t_lcol %x - %x\n", (int)&fecp->ieee_t_lcol, + fecp->ieee_t_lcol); + printf("ieee_t_excol %x - %x\n", (int)&fecp->ieee_t_excol, + fecp->ieee_t_excol); + printf("ieee_t_macerr %x - %x\n", (int)&fecp->ieee_t_macerr, + fecp->ieee_t_macerr); + printf("ieee_t_cserr %x - %x\n", (int)&fecp->ieee_t_cserr, + fecp->ieee_t_cserr); + printf("ieee_t_sqe %x - %x\n", (int)&fecp->ieee_t_sqe, + fecp->ieee_t_sqe); + printf("ieee_t_fdxfc %x - %x\n", (int)&fecp->ieee_t_fdxfc, + fecp->ieee_t_fdxfc); + printf("ieee_t_octets_ok %x - %x\n", (int)&fecp->ieee_t_octets_ok, + fecp->ieee_t_octets_ok); + + printf("\n"); + printf("rmon_r_drop %x - %x\n", (int)&fecp->rmon_r_drop, + fecp->rmon_r_drop); + printf("rmon_r_packets %x - %x\n", (int)&fecp->rmon_r_packets, + fecp->rmon_r_packets); + printf("rmon_r_bc_pkt %x - %x\n", (int)&fecp->rmon_r_bc_pkt, + fecp->rmon_r_bc_pkt); + printf("rmon_r_mc_pkt %x - %x\n", (int)&fecp->rmon_r_mc_pkt, + fecp->rmon_r_mc_pkt); + printf("rmon_r_crc_align %x - %x\n", (int)&fecp->rmon_r_crc_align, + fecp->rmon_r_crc_align); + printf("rmon_r_undersize %x - %x\n", (int)&fecp->rmon_r_undersize, + fecp->rmon_r_undersize); + printf("rmon_r_oversize %x - %x\n", (int)&fecp->rmon_r_oversize, + fecp->rmon_r_oversize); + printf("rmon_r_frag %x - %x\n", (int)&fecp->rmon_r_frag, + fecp->rmon_r_frag); + printf("rmon_r_jab %x - %x\n", (int)&fecp->rmon_r_jab, + fecp->rmon_r_jab); + printf("rmon_r_p64 %x - %x\n", (int)&fecp->rmon_r_p64, + fecp->rmon_r_p64); + printf("rmon_r_p65to127 %x - %x\n", (int)&fecp->rmon_r_p65to127, + fecp->rmon_r_p65to127); + printf("rmon_r_p128to255 %x - %x\n", (int)&fecp->rmon_r_p128to255, + fecp->rmon_r_p128to255); + printf("rmon_r_p256to511 %x - %x\n", (int)&fecp->rmon_r_p256to511, + fecp->rmon_r_p256to511); + printf("rmon_r_p512to1023 %x - %x\n", (int)&fecp->rmon_r_p512to1023, + fecp->rmon_r_p512to1023); + printf("rmon_r_p1024to2047 %x - %x\n", (int)&fecp->rmon_r_p1024to2047, + fecp->rmon_r_p1024to2047); + printf("rmon_r_p_gte2048 %x - %x\n", (int)&fecp->rmon_r_p_gte2048, + fecp->rmon_r_p_gte2048); + printf("rmon_r_octets %x - %x\n", (int)&fecp->rmon_r_octets, + fecp->rmon_r_octets); + + printf("\n"); + printf("ieee_r_drop %x - %x\n", (int)&fecp->ieee_r_drop, + fecp->ieee_r_drop); + printf("ieee_r_frame_ok %x - %x\n", (int)&fecp->ieee_r_frame_ok, + fecp->ieee_r_frame_ok); + printf("ieee_r_crc %x - %x\n", (int)&fecp->ieee_r_crc, + fecp->ieee_r_crc); + printf("ieee_r_align %x - %x\n", (int)&fecp->ieee_r_align, + fecp->ieee_r_align); + printf("ieee_r_macerr %x - %x\n", (int)&fecp->ieee_r_macerr, + fecp->ieee_r_macerr); + printf("ieee_r_fdxfc %x - %x\n", (int)&fecp->ieee_r_fdxfc, + fecp->ieee_r_fdxfc); + printf("ieee_r_octets_ok %x - %x\n", (int)&fecp->ieee_r_octets_ok, + fecp->ieee_r_octets_ok); + + printf("\n\n\n"); +} +#endif + +int fec_init(struct eth_device *dev, bd_t * bd) +{ + struct fec_info_s *info = dev->priv; + volatile fec_t *fecp = (fec_t *) (info->iobase); + int i; + uchar ea[6]; + + fecpin_setclear(dev, 1); + + fec_reset(dev); + +#if defined(CONFIG_CMD_MII) || defined (CONFIG_MII) || \ + defined (CONFIG_SYS_DISCOVER_PHY) + + mii_init(); + + setFecDuplexSpeed(fecp, bd, info->dup_spd); +#else +#ifndef CONFIG_SYS_DISCOVER_PHY + setFecDuplexSpeed(fecp, bd, (FECDUPLEX << 16) | FECSPEED); +#endif /* ifndef CONFIG_SYS_DISCOVER_PHY */ +#endif /* CONFIG_CMD_MII || CONFIG_MII */ + + /* We use strictly polling mode only */ + fecp->eimr = 0; + + /* Clear any pending interrupt */ + fecp->eir = 0xffffffff; + + /* Set station address */ + if ((u32) fecp == CONFIG_SYS_FEC0_IOBASE) { +#ifdef CONFIG_SYS_FEC1_IOBASE + volatile fec_t *fecp1 = (fec_t *) (CONFIG_SYS_FEC1_IOBASE); + eth_getenv_enetaddr("eth1addr", ea); + fecp1->palr = + (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]); + fecp1->paur = (ea[4] << 24) | (ea[5] << 16); +#endif + eth_getenv_enetaddr("ethaddr", ea); + fecp->palr = + (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]); + fecp->paur = (ea[4] << 24) | (ea[5] << 16); + } else { +#ifdef CONFIG_SYS_FEC0_IOBASE + volatile fec_t *fecp0 = (fec_t *) (CONFIG_SYS_FEC0_IOBASE); + eth_getenv_enetaddr("ethaddr", ea); + fecp0->palr = + (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]); + fecp0->paur = (ea[4] << 24) | (ea[5] << 16); +#endif +#ifdef CONFIG_SYS_FEC1_IOBASE + eth_getenv_enetaddr("eth1addr", ea); + fecp->palr = + (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]); + fecp->paur = (ea[4] << 24) | (ea[5] << 16); +#endif + } + + /* Clear unicast address hash table */ + fecp->iaur = 0; + fecp->ialr = 0; + + /* Clear multicast address hash table */ + fecp->gaur = 0; + fecp->galr = 0; + + /* Set maximum receive buffer size. */ + fecp->emrbr = PKT_MAXBLR_SIZE; + + /* + * Setup Buffers and Buffer Desriptors + */ + info->rxIdx = 0; + info->txIdx = 0; + + /* + * Setup Receiver Buffer Descriptors (13.14.24.18) + * Settings: + * Empty, Wrap + */ + for (i = 0; i < PKTBUFSRX; i++) { + info->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY; + info->rxbd[i].cbd_datlen = 0; /* Reset */ + info->rxbd[i].cbd_bufaddr = (uint) net_rx_packets[i]; + } + info->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP; + + /* + * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19) + * Settings: + * Last, Tx CRC + */ + for (i = 0; i < TX_BUF_CNT; i++) { + info->txbd[i].cbd_sc = BD_ENET_TX_LAST | BD_ENET_TX_TC; + info->txbd[i].cbd_datlen = 0; /* Reset */ + info->txbd[i].cbd_bufaddr = (uint) (&info->txbuf[0]); + } + info->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP; + + /* Set receive and transmit descriptor base */ + fecp->erdsr = (unsigned int)(&info->rxbd[0]); + fecp->etdsr = (unsigned int)(&info->txbd[0]); + + /* Now enable the transmit and receive processing */ + fecp->ecr |= FEC_ECR_ETHER_EN; + + /* And last, try to fill Rx Buffer Descriptors */ + fecp->rdar = 0x01000000; /* Descriptor polling active */ + + return 1; +} + +void fec_reset(struct eth_device *dev) +{ + struct fec_info_s *info = dev->priv; + volatile fec_t *fecp = (fec_t *) (info->iobase); + int i; + + fecp->ecr = FEC_ECR_RESET; + for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) { + udelay(1); + } + if (i == FEC_RESET_DELAY) { + printf("FEC_RESET_DELAY timeout\n"); + } +} + +void fec_halt(struct eth_device *dev) +{ + struct fec_info_s *info = dev->priv; + + fec_reset(dev); + + fecpin_setclear(dev, 0); + + info->rxIdx = info->txIdx = 0; + memset(info->rxbd, 0, PKTBUFSRX * sizeof(cbd_t)); + memset(info->txbd, 0, TX_BUF_CNT * sizeof(cbd_t)); + memset(info->txbuf, 0, DBUF_LENGTH); +} + +int mcffec_initialize(bd_t * bis) +{ + struct eth_device *dev; + int i; +#ifdef CONFIG_SYS_FEC_BUF_USE_SRAM + u32 tmp = CONFIG_SYS_INIT_RAM_ADDR + 0x1000; +#endif + + for (i = 0; i < ARRAY_SIZE(fec_info); i++) { + + dev = + (struct eth_device *)memalign(CONFIG_SYS_CACHELINE_SIZE, + sizeof *dev); + if (dev == NULL) + hang(); + + memset(dev, 0, sizeof(*dev)); + + sprintf(dev->name, "FEC%d", fec_info[i].index); + + dev->priv = &fec_info[i]; + dev->init = fec_init; + dev->halt = fec_halt; + dev->send = fec_send; + dev->recv = fec_recv; + + /* setup Receive and Transmit buffer descriptor */ +#ifdef CONFIG_SYS_FEC_BUF_USE_SRAM + fec_info[i].rxbd = (cbd_t *)((u32)fec_info[i].rxbd + tmp); + tmp = (u32)fec_info[i].rxbd; + fec_info[i].txbd = + (cbd_t *)((u32)fec_info[i].txbd + tmp + + (PKTBUFSRX * sizeof(cbd_t))); + tmp = (u32)fec_info[i].txbd; + fec_info[i].txbuf = + (char *)((u32)fec_info[i].txbuf + tmp + + (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t))); + tmp = (u32)fec_info[i].txbuf; +#else + fec_info[i].rxbd = + (cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE, + (PKTBUFSRX * sizeof(cbd_t))); + fec_info[i].txbd = + (cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE, + (TX_BUF_CNT * sizeof(cbd_t))); + fec_info[i].txbuf = + (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, DBUF_LENGTH); +#endif + +#ifdef ET_DEBUG + printf("rxbd %x txbd %x\n", + (int)fec_info[i].rxbd, (int)fec_info[i].txbd); +#endif + + fec_info[i].phy_name = (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, 32); + + eth_register(dev); + +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) + miiphy_register(dev->name, + mcffec_miiphy_read, mcffec_miiphy_write); +#endif + if (i > 0) + fec_info[i - 1].next = &fec_info[i]; + } + fec_info[i - 1].next = &fec_info[0]; + + /* default speed */ + bis->bi_ethspeed = 10; + + return 0; +} diff --git a/sources/uboot-be550/drivers/net/mcfmii.c b/sources/uboot-be550/drivers/net/mcfmii.c new file mode 100644 index 00000000..17a780c8 --- /dev/null +++ b/sources/uboot-be550/drivers/net/mcfmii.c @@ -0,0 +1,315 @@ +/* + * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +#ifdef CONFIG_MCF547x_8x +#include +#else +#include +#endif +#include + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_CMD_NET) +#undef MII_DEBUG +#undef ET_DEBUG + +/*extern int fecpin_setclear(struct eth_device *dev, int setclear);*/ + +#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII) +#include + +/* Make MII read/write commands for the FEC. */ +#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | \ + (REG & 0x1f) << 18)) +#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | \ + (REG & 0x1f) << 18) | (VAL & 0xffff)) + +#ifndef CONFIG_SYS_UNSPEC_PHYID +# define CONFIG_SYS_UNSPEC_PHYID 0 +#endif +#ifndef CONFIG_SYS_UNSPEC_STRID +# define CONFIG_SYS_UNSPEC_STRID 0 +#endif + +#ifdef CONFIG_MCF547x_8x +typedef struct fec_info_dma FEC_INFO_T; +#define FEC_T fecdma_t +#else +typedef struct fec_info_s FEC_INFO_T; +#define FEC_T fec_t +#endif + +typedef struct phy_info_struct { + u32 phyid; + char *strid; +} phy_info_t; + +phy_info_t phyinfo[] = { + {0x0022561B, "AMD79C784VC"}, /* AMD 79C784VC */ + {0x00406322, "BCM5222"}, /* Broadcom 5222 */ + {0x02a80150, "Intel82555"}, /* Intel 82555 */ + {0x0016f870, "LSI80225"}, /* LSI 80225 */ + {0x0016f880, "LSI80225/B"}, /* LSI 80225/B */ + {0x78100000, "LXT970"}, /* LXT970 */ + {0x001378e0, "LXT971"}, /* LXT971 and 972 */ + {0x00221619, "KS8721BL"}, /* Micrel KS8721BL/SL */ + {0x00221512, "KSZ8041NL"}, /* Micrel KSZ8041NL */ + {0x20005CE1, "N83640"}, /* National 83640 */ + {0x20005C90, "N83848"}, /* National 83848 */ + {0x20005CA2, "N83849"}, /* National 83849 */ + {0x01814400, "QS6612"}, /* QS6612 */ +#if defined(CONFIG_SYS_UNSPEC_PHYID) && defined(CONFIG_SYS_UNSPEC_STRID) + {CONFIG_SYS_UNSPEC_PHYID, CONFIG_SYS_UNSPEC_STRID}, +#endif + {0, 0} +}; + +/* + * mii_init -- Initialize the MII for MII command without ethernet + * This function is a subset of eth_init + */ +void mii_reset(FEC_INFO_T *info) +{ + volatile FEC_T *fecp = (FEC_T *) (info->miibase); + int i; + + fecp->ecr = FEC_ECR_RESET; + + for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) { + udelay(1); + } + if (i == FEC_RESET_DELAY) + printf("FEC_RESET_DELAY timeout\n"); +} + +/* send command to phy using mii, wait for result */ +uint mii_send(uint mii_cmd) +{ + FEC_INFO_T *info; + volatile FEC_T *ep; + struct eth_device *dev; + uint mii_reply; + int j = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + ep = (FEC_T *) info->miibase; + + ep->mmfr = mii_cmd; /* command to phy */ + + /* wait for mii complete */ + while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) { + udelay(1); + j++; + } + if (j >= MCFFEC_TOUT_LOOP) { + printf("MII not complete\n"); + return -1; + } + + mii_reply = ep->mmfr; /* result from phy */ + ep->eir = FEC_EIR_MII; /* clear MII complete */ +#ifdef ET_DEBUG + printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", + __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply); +#endif + + return (mii_reply & 0xffff); /* data read from phy */ +} +#endif /* CONFIG_SYS_DISCOVER_PHY || (CONFIG_MII) */ + +#if defined(CONFIG_SYS_DISCOVER_PHY) +int mii_discover_phy(struct eth_device *dev) +{ +#define MAX_PHY_PASSES 11 + FEC_INFO_T *info = dev->priv; + int phyaddr, pass; + uint phyno, phytype; + int i, found = 0; + + if (info->phyname_init) + return info->phy_addr; + + phyaddr = -1; /* didn't find a PHY yet */ + for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { + if (pass > 1) { + /* PHY may need more time to recover from reset. + * The LXT970 needs 50ms typical, no maximum is + * specified, so wait 10ms before try again. + * With 11 passes this gives it 100ms to wake up. + */ + udelay(10000); /* wait 10ms */ + } + + for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { + + phytype = mii_send(mk_mii_read(phyno, MII_PHYSID1)); +#ifdef ET_DEBUG + printf("PHY type 0x%x pass %d type\n", phytype, pass); +#endif + if (phytype == 0xffff) + continue; + phyaddr = phyno; + phytype <<= 16; + phytype |= + mii_send(mk_mii_read(phyno, MII_PHYSID2)); + +#ifdef ET_DEBUG + printf("PHY @ 0x%x pass %d\n", phyno, pass); +#endif + + for (i = 0; (i < ARRAY_SIZE(phyinfo)) + && (phyinfo[i].phyid != 0); i++) { + if (phyinfo[i].phyid == phytype) { +#ifdef ET_DEBUG + printf("phyid %x - %s\n", + phyinfo[i].phyid, + phyinfo[i].strid); +#endif + strcpy(info->phy_name, phyinfo[i].strid); + info->phyname_init = 1; + found = 1; + break; + } + } + + if (!found) { +#ifdef ET_DEBUG + printf("0x%08x\n", phytype); +#endif + strcpy(info->phy_name, "unknown"); + info->phyname_init = 1; + break; + } + } + } + + if (phyaddr < 0) + printf("No PHY device found.\n"); + + return phyaddr; +} +#endif /* CONFIG_SYS_DISCOVER_PHY */ + +void mii_init(void) __attribute__((weak,alias("__mii_init"))); + +void __mii_init(void) +{ + FEC_INFO_T *info; + volatile FEC_T *fecp; + struct eth_device *dev; + int miispd = 0, i = 0; + u16 status = 0; + u16 linkgood = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + fecp = (FEC_T *) info->miibase; + + fecpin_setclear(dev, 1); + + mii_reset(info); + + /* We use strictly polling mode only */ + fecp->eimr = 0; + + /* Clear any pending interrupt */ + fecp->eir = 0xffffffff; + + /* Set MII speed */ + miispd = (gd->bus_clk / 1000000) / 5; + fecp->mscr = miispd << 1; + + info->phy_addr = mii_discover_phy(dev); + + while (i < MCFFEC_TOUT_LOOP) { + status = 0; + i++; + /* Read PHY control register */ + miiphy_read(dev->name, info->phy_addr, MII_BMCR, &status); + + /* If phy set to autonegotiate, wait for autonegotiation done, + * if phy is not autonegotiating, just wait for link up. + */ + if ((status & BMCR_ANENABLE) == BMCR_ANENABLE) { + linkgood = (BMSR_ANEGCOMPLETE | BMSR_LSTATUS); + } else { + linkgood = BMSR_LSTATUS; + } + /* Read PHY status register */ + miiphy_read(dev->name, info->phy_addr, MII_BMSR, &status); + if ((status & linkgood) == linkgood) + break; + + udelay(1); + } + if (i >= MCFFEC_TOUT_LOOP) { + printf("Link UP timeout\n"); + } + + /* adapt to the duplex and speed settings of the phy */ + info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16; + info->dup_spd |= miiphy_speed(dev->name, info->phy_addr); +} + +/* + * Read and write a MII PHY register, routines used by MII Utilities + * + * FIXME: These routines are expected to return 0 on success, but mii_send + * does _not_ return an error code. Maybe 0xFFFF means error, i.e. + * no PHY connected... + * For now always return 0. + * FIXME: These routines only work after calling eth_init() at least once! + * Otherwise they hang in mii_send() !!! Sorry! + */ + +int mcffec_miiphy_read(const char *devname, unsigned char addr, unsigned char reg, + unsigned short *value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr); +#endif + rdreg = mii_send(mk_mii_read(addr, reg)); + + *value = rdreg; + +#ifdef MII_DEBUG + printf("0x%04x\n", *value); +#endif + + return 0; +} + +int mcffec_miiphy_write(const char *devname, unsigned char addr, unsigned char reg, + unsigned short value) +{ +#ifdef MII_DEBUG + printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr); +#endif + + mii_send(mk_mii_write(addr, reg, value)); + +#ifdef MII_DEBUG + printf("0x%04x\n", value); +#endif + + return 0; +} + +#endif /* CONFIG_CMD_NET */ diff --git a/sources/uboot-be550/drivers/net/mpc512x_fec.c b/sources/uboot-be550/drivers/net/mpc512x_fec.c new file mode 100644 index 00000000..22ea114f --- /dev/null +++ b/sources/uboot-be550/drivers/net/mpc512x_fec.c @@ -0,0 +1,755 @@ +/* + * (C) Copyright 2003-2010 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Derived from the MPC8xx FEC driver. + * Adapted for MPC512x by Grzegorz Bernacki + */ + +#include +#include +#include +#include +#include +#include +#include "mpc512x_fec.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define DEBUG 0 + +#if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) +#error "CONFIG_MII has to be defined!" +#endif + +int fec512x_miiphy_read(const char *devname, u8 phyAddr, u8 regAddr, u16 * retVal); +int fec512x_miiphy_write(const char *devname, u8 phyAddr, u8 regAddr, u16 data); +int mpc512x_fec_init_phy(struct eth_device *dev, bd_t * bis); + +static uchar rx_buff[FEC_BUFFER_SIZE]; +static int rx_buff_idx = 0; + +/********************************************************************/ +#if (DEBUG & 0x2) +static void mpc512x_fec_phydump (char *devname) +{ + u16 phyStatus, i; + u8 phyAddr = CONFIG_PHY_ADDR; + u8 reg_mask[] = { + /* regs to print: 0...8, 21,27,31 */ + 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, + }; + + for (i = 0; i < 32; i++) { + if (reg_mask[i]) { + miiphy_read (devname, phyAddr, i, &phyStatus); + printf ("Mii reg %d: 0x%04x\n", i, phyStatus); + } + } +} +#endif + +/********************************************************************/ +static int mpc512x_fec_bd_init (mpc512x_fec_priv *fec) +{ + int ix; + + /* + * Receive BDs init + */ + for (ix = 0; ix < FEC_RBD_NUM; ix++) { + fec->bdBase->rbd[ix].dataPointer = + (u32)&fec->bdBase->recv_frames[ix]; + fec->bdBase->rbd[ix].status = FEC_RBD_EMPTY; + fec->bdBase->rbd[ix].dataLength = 0; + } + + /* + * have the last RBD to close the ring + */ + fec->bdBase->rbd[ix - 1].status |= FEC_RBD_WRAP; + fec->rbdIndex = 0; + + /* + * Trasmit BDs init + */ + for (ix = 0; ix < FEC_TBD_NUM; ix++) { + fec->bdBase->tbd[ix].status = 0; + } + + /* + * Have the last TBD to close the ring + */ + fec->bdBase->tbd[ix - 1].status |= FEC_TBD_WRAP; + + /* + * Initialize some indices + */ + fec->tbdIndex = 0; + fec->usedTbdIndex = 0; + fec->cleanTbdNum = FEC_TBD_NUM; + + return 0; +} + +/********************************************************************/ +static void mpc512x_fec_rbd_clean (mpc512x_fec_priv *fec, volatile FEC_RBD * pRbd) +{ + /* + * Reset buffer descriptor as empty + */ + if ((fec->rbdIndex) == (FEC_RBD_NUM - 1)) + pRbd->status = (FEC_RBD_WRAP | FEC_RBD_EMPTY); + else + pRbd->status = FEC_RBD_EMPTY; + + pRbd->dataLength = 0; + + /* + * Increment BD count + */ + fec->rbdIndex = (fec->rbdIndex + 1) % FEC_RBD_NUM; + + /* + * Now, we have an empty RxBD, notify FEC + * Set Descriptor polling active + */ + out_be32(&fec->eth->r_des_active, 0x01000000); +} + +/********************************************************************/ +static void mpc512x_fec_tbd_scrub (mpc512x_fec_priv *fec) +{ + volatile FEC_TBD *pUsedTbd; + +#if (DEBUG & 0x1) + printf ("tbd_scrub: fec->cleanTbdNum = %d, fec->usedTbdIndex = %d\n", + fec->cleanTbdNum, fec->usedTbdIndex); +#endif + + /* + * process all the consumed TBDs + */ + while (fec->cleanTbdNum < FEC_TBD_NUM) { + pUsedTbd = &fec->bdBase->tbd[fec->usedTbdIndex]; + if (pUsedTbd->status & FEC_TBD_READY) { +#if (DEBUG & 0x20) + printf ("Cannot clean TBD %d, in use\n", fec->usedTbdIndex); +#endif + return; + } + + /* + * clean this buffer descriptor + */ + if (fec->usedTbdIndex == (FEC_TBD_NUM - 1)) + pUsedTbd->status = FEC_TBD_WRAP; + else + pUsedTbd->status = 0; + + /* + * update some indeces for a correct handling of the TBD ring + */ + fec->cleanTbdNum++; + fec->usedTbdIndex = (fec->usedTbdIndex + 1) % FEC_TBD_NUM; + } +} + +/********************************************************************/ +static void mpc512x_fec_set_hwaddr (mpc512x_fec_priv *fec, unsigned char *mac) +{ + u8 currByte; /* byte for which to compute the CRC */ + int byte; /* loop - counter */ + int bit; /* loop - counter */ + u32 crc = 0xffffffff; /* initial value */ + + /* + * The algorithm used is the following: + * we loop on each of the six bytes of the provided address, + * and we compute the CRC by left-shifting the previous + * value by one position, so that each bit in the current + * byte of the address may contribute the calculation. If + * the latter and the MSB in the CRC are different, then + * the CRC value so computed is also ex-ored with the + * "polynomium generator". The current byte of the address + * is also shifted right by one bit at each iteration. + * This is because the CRC generatore in hardware is implemented + * as a shift-register with as many ex-ores as the radixes + * in the polynomium. This suggests that we represent the + * polynomiumm itself as a 32-bit constant. + */ + for (byte = 0; byte < 6; byte++) { + currByte = mac[byte]; + for (bit = 0; bit < 8; bit++) { + if ((currByte & 0x01) ^ (crc & 0x01)) { + crc >>= 1; + crc = crc ^ 0xedb88320; + } else { + crc >>= 1; + } + currByte >>= 1; + } + } + + crc = crc >> 26; + + /* + * Set individual hash table register + */ + if (crc >= 32) { + out_be32(&fec->eth->iaddr1, (1 << (crc - 32))); + out_be32(&fec->eth->iaddr2, 0); + } else { + out_be32(&fec->eth->iaddr1, 0); + out_be32(&fec->eth->iaddr2, (1 << crc)); + } + + /* + * Set physical address + */ + out_be32(&fec->eth->paddr1, (mac[0] << 24) + (mac[1] << 16) + + (mac[2] << 8) + mac[3]); + out_be32(&fec->eth->paddr2, (mac[4] << 24) + (mac[5] << 16) + + 0x8808); +} + +/********************************************************************/ +static int mpc512x_fec_init (struct eth_device *dev, bd_t * bis) +{ + mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv; + +#if (DEBUG & 0x1) + printf ("mpc512x_fec_init... Begin\n"); +#endif + + mpc512x_fec_set_hwaddr (fec, dev->enetaddr); + out_be32(&fec->eth->gaddr1, 0x00000000); + out_be32(&fec->eth->gaddr2, 0x00000000); + + mpc512x_fec_init_phy (dev, bis); + + /* Set interrupt mask register */ + out_be32(&fec->eth->imask, 0x00000000); + + /* Clear FEC-Lite interrupt event register(IEVENT) */ + out_be32(&fec->eth->ievent, 0xffffffff); + + /* Set transmit fifo watermark register(X_WMRK), default = 64 */ + out_be32(&fec->eth->x_wmrk, 0x0); + + /* Set Opcode/Pause Duration Register */ + out_be32(&fec->eth->op_pause, 0x00010020); + + /* Frame length=1522; MII mode */ + out_be32(&fec->eth->r_cntrl, (FEC_MAX_FRAME_LEN << 16) | 0x24); + + /* Half-duplex, heartbeat disabled */ + out_be32(&fec->eth->x_cntrl, 0x00000000); + + /* Enable MIB counters */ + out_be32(&fec->eth->mib_control, 0x0); + + /* Setup recv fifo start and buff size */ + out_be32(&fec->eth->r_fstart, 0x500); + out_be32(&fec->eth->r_buff_size, FEC_BUFFER_SIZE); + + /* Setup BD base addresses */ + out_be32(&fec->eth->r_des_start, (u32)fec->bdBase->rbd); + out_be32(&fec->eth->x_des_start, (u32)fec->bdBase->tbd); + + /* DMA Control */ + out_be32(&fec->eth->dma_control, 0xc0000000); + + /* Enable FEC */ + setbits_be32(&fec->eth->ecntrl, 0x00000006); + + /* Initilize addresses and status words of BDs */ + mpc512x_fec_bd_init (fec); + + /* Descriptor polling active */ + out_be32(&fec->eth->r_des_active, 0x01000000); + +#if (DEBUG & 0x1) + printf("mpc512x_fec_init... Done \n"); +#endif + return 1; +} + +/********************************************************************/ +int mpc512x_fec_init_phy (struct eth_device *dev, bd_t * bis) +{ + mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv; + const u8 phyAddr = CONFIG_PHY_ADDR; /* Only one PHY */ + int timeout = 1; + u16 phyStatus; + +#if (DEBUG & 0x1) + printf ("mpc512x_fec_init_phy... Begin\n"); +#endif + + /* + * Clear FEC-Lite interrupt event register(IEVENT) + */ + out_be32(&fec->eth->ievent, 0xffffffff); + + /* + * Set interrupt mask register + */ + out_be32(&fec->eth->imask, 0x00000000); + + if (fec->xcv_type != SEVENWIRE) { + /* + * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock + * and do not drop the Preamble. + */ + out_be32(&fec->eth->mii_speed, + (((gd->arch.ips_clk / 1000000) / 5) + 1) << 1); + + /* + * Reset PHY, then delay 300ns + */ + miiphy_write (dev->name, phyAddr, 0x0, 0x8000); + udelay (1000); + + if (fec->xcv_type == MII10) { + /* + * Force 10Base-T, FDX operation + */ +#if (DEBUG & 0x2) + printf ("Forcing 10 Mbps ethernet link... "); +#endif + miiphy_read (dev->name, phyAddr, 0x1, &phyStatus); + + miiphy_write (dev->name, phyAddr, 0x0, 0x0180); + + timeout = 20; + do { /* wait for link status to go down */ + udelay (10000); + if ((timeout--) == 0) { +#if (DEBUG & 0x2) + printf ("hmmm, should not have waited..."); +#endif + break; + } + miiphy_read (dev->name, phyAddr, 0x1, &phyStatus); +#if (DEBUG & 0x2) + printf ("="); +#endif + } while ((phyStatus & 0x0004)); /* !link up */ + + timeout = 1000; + do { /* wait for link status to come back up */ + udelay (10000); + if ((timeout--) == 0) { + printf ("failed. Link is down.\n"); + break; + } + miiphy_read (dev->name, phyAddr, 0x1, &phyStatus); +#if (DEBUG & 0x2) + printf ("+"); +#endif + } while (!(phyStatus & 0x0004)); /* !link up */ + +#if (DEBUG & 0x2) + printf ("done.\n"); +#endif + } else { /* MII100 */ + /* + * Set the auto-negotiation advertisement register bits + */ + miiphy_write (dev->name, phyAddr, 0x4, 0x01e1); + + /* + * Set MDIO bit 0.12 = 1(&& bit 0.9=1?) to enable auto-negotiation + */ + miiphy_write (dev->name, phyAddr, 0x0, 0x1200); + + /* + * Wait for AN completion + */ + timeout = 2500; + do { + udelay (1000); + + if ((timeout--) == 0) { +#if (DEBUG & 0x2) + printf ("PHY auto neg 0 failed...\n"); +#endif + return -1; + } + + if (miiphy_read (dev->name, phyAddr, 0x1, &phyStatus) != 0) { +#if (DEBUG & 0x2) + printf ("PHY auto neg 1 failed 0x%04x...\n", phyStatus); +#endif + return -1; + } + } while (!(phyStatus & 0x0004)); + +#if (DEBUG & 0x2) + printf ("PHY auto neg complete! \n"); +#endif + } + } + +#if (DEBUG & 0x2) + if (fec->xcv_type != SEVENWIRE) + mpc512x_fec_phydump (dev->name); +#endif + +#if (DEBUG & 0x1) + printf ("mpc512x_fec_init_phy... Done \n"); +#endif + return 1; +} + +/********************************************************************/ +static void mpc512x_fec_halt (struct eth_device *dev) +{ + mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv; + int counter = 0xffff; + +#if (DEBUG & 0x2) + if (fec->xcv_type != SEVENWIRE) + mpc512x_fec_phydump (dev->name); +#endif + + /* + * mask FEC chip interrupts + */ + out_be32(&fec->eth->imask, 0); + + /* + * issue graceful stop command to the FEC transmitter if necessary + */ + setbits_be32(&fec->eth->x_cntrl, 0x00000001); + + /* + * wait for graceful stop to register + */ + while ((counter--) && (!(in_be32(&fec->eth->ievent) & 0x10000000))) + ; + + /* + * Disable the Ethernet Controller + */ + clrbits_be32(&fec->eth->ecntrl, 0x00000002); + + /* + * Issue a reset command to the FEC chip + */ + setbits_be32(&fec->eth->ecntrl, 0x1); + + /* + * wait at least 16 clock cycles + */ + udelay (10); +#if (DEBUG & 0x3) + printf ("Ethernet task stopped\n"); +#endif +} + +/********************************************************************/ + +static int mpc512x_fec_send(struct eth_device *dev, void *eth_data, + int data_length) +{ + /* + * This routine transmits one frame. This routine only accepts + * 6-byte Ethernet addresses. + */ + mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv; + volatile FEC_TBD *pTbd; + +#if (DEBUG & 0x20) + printf("tbd status: 0x%04x\n", fec->tbdBase[fec->tbdIndex].status); +#endif + + /* + * Clear Tx BD ring at first + */ + mpc512x_fec_tbd_scrub (fec); + + /* + * Check for valid length of data. + */ + if ((data_length > 1500) || (data_length <= 0)) { + return -1; + } + + /* + * Check the number of vacant TxBDs. + */ + if (fec->cleanTbdNum < 1) { +#if (DEBUG & 0x20) + printf ("No available TxBDs ...\n"); +#endif + return -1; + } + + /* + * Get the first TxBD to send the mac header + */ + pTbd = &fec->bdBase->tbd[fec->tbdIndex]; + pTbd->dataLength = data_length; + pTbd->dataPointer = (u32)eth_data; + pTbd->status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY; + fec->tbdIndex = (fec->tbdIndex + 1) % FEC_TBD_NUM; + + /* Activate transmit Buffer Descriptor polling */ + out_be32(&fec->eth->x_des_active, 0x01000000); + +#if (DEBUG & 0x8) + printf ( "+" ); +#endif + + fec->cleanTbdNum -= 1; + + /* + * wait until frame is sent . + */ + while (pTbd->status & FEC_TBD_READY) { + udelay (10); +#if (DEBUG & 0x8) + printf ("TDB status = %04x\n", pTbd->status); +#endif + } + + return 0; +} + + +/********************************************************************/ +static int mpc512x_fec_recv (struct eth_device *dev) +{ + /* + * This command pulls one frame from the card + */ + mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv; + volatile FEC_RBD *pRbd = &fec->bdBase->rbd[fec->rbdIndex]; + unsigned long ievent; + int frame_length = 0; + +#if (DEBUG & 0x1) + printf ("mpc512x_fec_recv %d Start...\n", fec->rbdIndex); +#endif +#if (DEBUG & 0x8) + printf( "-" ); +#endif + + /* + * Check if any critical events have happened + */ + ievent = in_be32(&fec->eth->ievent); + out_be32(&fec->eth->ievent, ievent); + if (ievent & 0x20060000) { + /* BABT, Rx/Tx FIFO errors */ + mpc512x_fec_halt (dev); + mpc512x_fec_init (dev, NULL); + return 0; + } + if (ievent & 0x80000000) { + /* Heartbeat error */ + setbits_be32(&fec->eth->x_cntrl, 0x00000001); + } + if (ievent & 0x10000000) { + /* Graceful stop complete */ + if (in_be32(&fec->eth->x_cntrl) & 0x00000001) { + mpc512x_fec_halt (dev); + clrbits_be32(&fec->eth->x_cntrl, 0x00000001);; + mpc512x_fec_init (dev, NULL); + } + } + + if (!(pRbd->status & FEC_RBD_EMPTY)) { + if (!(pRbd->status & FEC_RBD_ERR) && + ((pRbd->dataLength - 4) > 14)) { + + /* + * Get buffer size + */ + if (pRbd->status & FEC_RBD_LAST) + frame_length = pRbd->dataLength - 4; + else + frame_length = pRbd->dataLength; +#if (DEBUG & 0x20) + { + int i; + printf ("recv data length 0x%08x data hdr: ", + pRbd->dataLength); + for (i = 0; i < 14; i++) + printf ("%x ", *((u8*)pRbd->dataPointer + i)); + printf("\n"); + } +#endif + /* + * Fill the buffer and pass it to upper layers + */ + memcpy (&rx_buff[rx_buff_idx], (void*)pRbd->dataPointer, + frame_length - rx_buff_idx); + rx_buff_idx = frame_length; + + if (pRbd->status & FEC_RBD_LAST) { + net_process_received_packet((uchar *)rx_buff, + frame_length); + rx_buff_idx = 0; + } + } + + /* + * Reset buffer descriptor as empty + */ + mpc512x_fec_rbd_clean (fec, pRbd); + } + + /* Try to fill Buffer Descriptors */ + out_be32(&fec->eth->r_des_active, 0x01000000); + + return frame_length; +} + +/********************************************************************/ +int mpc512x_fec_initialize (bd_t * bis) +{ + volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; + mpc512x_fec_priv *fec; + struct eth_device *dev; + void * bd; + + fec = (mpc512x_fec_priv *) malloc (sizeof(*fec)); + dev = (struct eth_device *) malloc (sizeof(*dev)); + memset (dev, 0, sizeof *dev); + + fec->eth = &im->fec; + +# ifndef CONFIG_FEC_10MBIT + fec->xcv_type = MII100; +# else + fec->xcv_type = MII10; +# endif + dev->priv = (void *)fec; + dev->iobase = (int)&im->fec; + dev->init = mpc512x_fec_init; + dev->halt = mpc512x_fec_halt; + dev->send = mpc512x_fec_send; + dev->recv = mpc512x_fec_recv; + + sprintf (dev->name, "FEC"); + eth_register (dev); + +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) + miiphy_register (dev->name, + fec512x_miiphy_read, fec512x_miiphy_write); +#endif + + /* Clean up space FEC's MIB and FIFO RAM ...*/ + memset ((void *)&im->fec.mib, 0x00, sizeof(im->fec.mib)); + memset ((void *)&im->fec.fifo, 0x00, sizeof(im->fec.fifo)); + + /* + * Malloc space for BDs (must be quad word-aligned) + * this pointer is lost, so cannot be freed + */ + bd = malloc (sizeof(mpc512x_buff_descs) + 0x1f); + fec->bdBase = (mpc512x_buff_descs*)((u32)bd & 0xfffffff0); + memset ((void *) bd, 0x00, sizeof(mpc512x_buff_descs) + 0x1f); + + /* + * Set interrupt mask register + */ + out_be32(&fec->eth->imask, 0x00000000); + + /* + * Clear FEC-Lite interrupt event register(IEVENT) + */ + out_be32(&fec->eth->ievent, 0xffffffff); + + return 1; +} + +/* MII-interface related functions */ +/********************************************************************/ +int fec512x_miiphy_read(const char *devname, u8 phyAddr, u8 regAddr, u16 *retVal) +{ + volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; + volatile fec512x_t *eth = &im->fec; + u32 reg; /* convenient holder for the PHY register */ + u32 phy; /* convenient holder for the PHY */ + int timeout = 0xffff; + + /* + * reading from any PHY's register is done by properly + * programming the FEC's MII data register. + */ + reg = regAddr << FEC_MII_DATA_RA_SHIFT; + phy = phyAddr << FEC_MII_DATA_PA_SHIFT; + + out_be32(ð->mii_data, FEC_MII_DATA_ST | + FEC_MII_DATA_OP_RD | + FEC_MII_DATA_TA | + phy | reg); + + /* + * wait for the related interrupt + */ + while ((timeout--) && (!(in_be32(ð->ievent) & 0x00800000))) + ; + + if (timeout == 0) { +#if (DEBUG & 0x2) + printf ("Read MDIO failed...\n"); +#endif + return -1; + } + + /* + * clear mii interrupt bit + */ + out_be32(ð->ievent, 0x00800000); + + /* + * it's now safe to read the PHY's register + */ + *retVal = (u16) in_be32(ð->mii_data); + + return 0; +} + +/********************************************************************/ +int fec512x_miiphy_write(const char *devname, u8 phyAddr, u8 regAddr, u16 data) +{ + volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; + volatile fec512x_t *eth = &im->fec; + u32 reg; /* convenient holder for the PHY register */ + u32 phy; /* convenient holder for the PHY */ + int timeout = 0xffff; + + reg = regAddr << FEC_MII_DATA_RA_SHIFT; + phy = phyAddr << FEC_MII_DATA_PA_SHIFT; + + out_be32(ð->mii_data, FEC_MII_DATA_ST | + FEC_MII_DATA_OP_WR | + FEC_MII_DATA_TA | + phy | reg | data); + + /* + * wait for the MII interrupt + */ + while ((timeout--) && (!(in_be32(ð->ievent) & 0x00800000))) + ; + + if (timeout == 0) { +#if (DEBUG & 0x2) + printf ("Write MDIO failed...\n"); +#endif + return -1; + } + + /* + * clear MII interrupt bit + */ + out_be32(ð->ievent, 0x00800000); + + return 0; +} diff --git a/sources/uboot-be550/drivers/net/mpc512x_fec.h b/sources/uboot-be550/drivers/net/mpc512x_fec.h new file mode 100644 index 00000000..a083cca2 --- /dev/null +++ b/sources/uboot-be550/drivers/net/mpc512x_fec.h @@ -0,0 +1,98 @@ +/* + * (C) Copyright 2003 - 2009 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Derived from the MPC8xx driver's header file. + */ + +#ifndef __MPC512X_FEC_H +#define __MPC512X_FEC_H + +#include + +/* Receive & Transmit Buffer Descriptor definitions */ +typedef struct BufferDescriptor { + u16 status; + u16 dataLength; + u32 dataPointer; +} FEC_RBD; + +typedef struct { + u16 status; + u16 dataLength; + u32 dataPointer; +} FEC_TBD; + +/* private structure */ +typedef enum { + SEVENWIRE, /* 7-wire */ + MII10, /* MII 10Mbps */ + MII100 /* MII 100Mbps */ +} xceiver_type; + +/* BD Numer definitions */ +#define FEC_TBD_NUM 48 /* The user can adjust this value */ +#define FEC_RBD_NUM 32 /* The user can adjust this value */ + +/* packet size limit */ +#define FEC_MAX_FRAME_LEN 1522 /* recommended default value */ + +/* Buffer size must be evenly divisible by 16 */ +#define FEC_BUFFER_SIZE ((FEC_MAX_FRAME_LEN + 0x10) & (~0xf)) + +typedef struct { + u8 frame[FEC_BUFFER_SIZE]; +} mpc512x_frame; + +typedef struct { + FEC_RBD rbd[FEC_RBD_NUM]; /* RBD ring */ + FEC_TBD tbd[FEC_TBD_NUM]; /* TBD ring */ + mpc512x_frame recv_frames[FEC_RBD_NUM]; /* receive buff */ +} mpc512x_buff_descs; + +typedef struct { + volatile fec512x_t *eth; + xceiver_type xcv_type; /* transceiver type */ + mpc512x_buff_descs *bdBase; /* BD rings and recv buffer */ + u16 rbdIndex; /* next receive BD to read */ + u16 tbdIndex; /* next transmit BD to send */ + u16 usedTbdIndex; /* next transmit BD to clean */ + u16 cleanTbdNum; /* the number of available transmit BDs */ +} mpc512x_fec_priv; + +/* RBD bits definitions */ +#define FEC_RBD_EMPTY 0x8000 /* Buffer is empty */ +#define FEC_RBD_WRAP 0x2000 /* Last BD in ring */ +#define FEC_RBD_LAST 0x0800 /* Buffer is last in frame(useless) */ +#define FEC_RBD_MISS 0x0100 /* Miss bit for prom mode */ +#define FEC_RBD_BC 0x0080 /* The received frame is broadcast frame */ +#define FEC_RBD_MC 0x0040 /* The received frame is multicast frame */ +#define FEC_RBD_LG 0x0020 /* Frame length violation */ +#define FEC_RBD_NO 0x0010 /* Nonoctet align frame */ +#define FEC_RBD_SH 0x0008 /* Short frame */ +#define FEC_RBD_CR 0x0004 /* CRC error */ +#define FEC_RBD_OV 0x0002 /* Receive FIFO overrun */ +#define FEC_RBD_TR 0x0001 /* Frame is truncated */ +#define FEC_RBD_ERR (FEC_RBD_LG | FEC_RBD_NO | FEC_RBD_CR | \ + FEC_RBD_OV | FEC_RBD_TR) + +/* TBD bits definitions */ +#define FEC_TBD_READY 0x8000 /* Buffer is ready */ +#define FEC_TBD_WRAP 0x2000 /* Last BD in ring */ +#define FEC_TBD_LAST 0x0800 /* Buffer is last in frame */ +#define FEC_TBD_TC 0x0400 /* Transmit the CRC */ +#define FEC_TBD_ABC 0x0200 /* Append bad CRC */ + +/* MII-related definitios */ +#define FEC_MII_DATA_ST 0x40000000 /* Start of frame delimiter */ +#define FEC_MII_DATA_OP_RD 0x20000000 /* Perform a read operation */ +#define FEC_MII_DATA_OP_WR 0x10000000 /* Perform a write operation */ +#define FEC_MII_DATA_PA_MSK 0x0f800000 /* PHY Address field mask */ +#define FEC_MII_DATA_RA_MSK 0x007c0000 /* PHY Register field mask */ +#define FEC_MII_DATA_TA 0x00020000 /* Turnaround */ +#define FEC_MII_DATA_DATAMSK 0x0000ffff /* PHY data field */ + +#define FEC_MII_DATA_RA_SHIFT 18 /* MII Register address bits */ +#define FEC_MII_DATA_PA_SHIFT 23 /* MII PHY address bits */ + +#endif /* __MPC512X_FEC_H */ diff --git a/sources/uboot-be550/drivers/net/mpc5xxx_fec.c b/sources/uboot-be550/drivers/net/mpc5xxx_fec.c new file mode 100644 index 00000000..2ebd1761 --- /dev/null +++ b/sources/uboot-be550/drivers/net/mpc5xxx_fec.c @@ -0,0 +1,1017 @@ +/* + * (C) Copyright 2003-2010 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * This file is based on mpc4200fec.c, + * (C) Copyright Motorola, Inc., 2000 + */ + +#include +#include +#include +#include +#include +#include +#include +#include "mpc5xxx_fec.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* #define DEBUG 0x28 */ + +#if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) +#error "CONFIG_MII has to be defined!" +#endif + +#if (DEBUG & 0x60) +static void tfifo_print(char *devname, mpc5xxx_fec_priv *fec); +static void rfifo_print(char *devname, mpc5xxx_fec_priv *fec); +#endif /* DEBUG */ + +typedef struct { + uint8 data[1500]; /* actual data */ + int length; /* actual length */ + int used; /* buffer in use or not */ + uint8 head[16]; /* MAC header(6 + 6 + 2) + 2(aligned) */ +} NBUF; + +int fec5xxx_miiphy_read(const char *devname, uint8 phyAddr, uint8 regAddr, uint16 *retVal); +int fec5xxx_miiphy_write(const char *devname, uint8 phyAddr, uint8 regAddr, uint16 data); + +static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis); + +/********************************************************************/ +#if (DEBUG & 0x2) +static void mpc5xxx_fec_phydump (char *devname) +{ + uint16 phyStatus, i; + uint8 phyAddr = CONFIG_PHY_ADDR; + uint8 reg_mask[] = { +#if CONFIG_PHY_TYPE == 0x79c874 /* AMD Am79C874 */ + /* regs to print: 0...7, 16...19, 21, 23, 24 */ + 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 1, 1, 1, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, +#else + /* regs to print: 0...8, 16...20 */ + 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, + 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +#endif + }; + + for (i = 0; i < 32; i++) { + if (reg_mask[i]) { + miiphy_read(devname, phyAddr, i, &phyStatus); + printf("Mii reg %d: 0x%04x\n", i, phyStatus); + } + } +} +#endif + +/********************************************************************/ +static int mpc5xxx_fec_rbd_init(mpc5xxx_fec_priv *fec) +{ + int ix; + char *data; + static int once = 0; + + for (ix = 0; ix < FEC_RBD_NUM; ix++) { + if (!once) { + data = (char *)malloc(FEC_MAX_PKT_SIZE); + if (data == NULL) { + printf ("RBD INIT FAILED\n"); + return -1; + } + fec->rbdBase[ix].dataPointer = (uint32)data; + } + fec->rbdBase[ix].status = FEC_RBD_EMPTY; + fec->rbdBase[ix].dataLength = 0; + } + once ++; + + /* + * have the last RBD to close the ring + */ + fec->rbdBase[ix - 1].status |= FEC_RBD_WRAP; + fec->rbdIndex = 0; + + return 0; +} + +/********************************************************************/ +static void mpc5xxx_fec_tbd_init(mpc5xxx_fec_priv *fec) +{ + int ix; + + for (ix = 0; ix < FEC_TBD_NUM; ix++) { + fec->tbdBase[ix].status = 0; + } + + /* + * Have the last TBD to close the ring + */ + fec->tbdBase[ix - 1].status |= FEC_TBD_WRAP; + + /* + * Initialize some indices + */ + fec->tbdIndex = 0; + fec->usedTbdIndex = 0; + fec->cleanTbdNum = FEC_TBD_NUM; +} + +/********************************************************************/ +static void mpc5xxx_fec_rbd_clean(mpc5xxx_fec_priv *fec, volatile FEC_RBD * pRbd) +{ + /* + * Reset buffer descriptor as empty + */ + if ((fec->rbdIndex) == (FEC_RBD_NUM - 1)) + pRbd->status = (FEC_RBD_WRAP | FEC_RBD_EMPTY); + else + pRbd->status = FEC_RBD_EMPTY; + + pRbd->dataLength = 0; + + /* + * Now, we have an empty RxBD, restart the SmartDMA receive task + */ + SDMA_TASK_ENABLE(FEC_RECV_TASK_NO); + + /* + * Increment BD count + */ + fec->rbdIndex = (fec->rbdIndex + 1) % FEC_RBD_NUM; +} + +/********************************************************************/ +static void mpc5xxx_fec_tbd_scrub(mpc5xxx_fec_priv *fec) +{ + volatile FEC_TBD *pUsedTbd; + +#if (DEBUG & 0x1) + printf ("tbd_scrub: fec->cleanTbdNum = %d, fec->usedTbdIndex = %d\n", + fec->cleanTbdNum, fec->usedTbdIndex); +#endif + + /* + * process all the consumed TBDs + */ + while (fec->cleanTbdNum < FEC_TBD_NUM) { + pUsedTbd = &fec->tbdBase[fec->usedTbdIndex]; + if (pUsedTbd->status & FEC_TBD_READY) { +#if (DEBUG & 0x20) + printf("Cannot clean TBD %d, in use\n", fec->cleanTbdNum); +#endif + return; + } + + /* + * clean this buffer descriptor + */ + if (fec->usedTbdIndex == (FEC_TBD_NUM - 1)) + pUsedTbd->status = FEC_TBD_WRAP; + else + pUsedTbd->status = 0; + + /* + * update some indeces for a correct handling of the TBD ring + */ + fec->cleanTbdNum++; + fec->usedTbdIndex = (fec->usedTbdIndex + 1) % FEC_TBD_NUM; + } +} + +/********************************************************************/ +static void mpc5xxx_fec_set_hwaddr(mpc5xxx_fec_priv *fec, char *mac) +{ + uint8 currByte; /* byte for which to compute the CRC */ + int byte; /* loop - counter */ + int bit; /* loop - counter */ + uint32 crc = 0xffffffff; /* initial value */ + + /* + * The algorithm used is the following: + * we loop on each of the six bytes of the provided address, + * and we compute the CRC by left-shifting the previous + * value by one position, so that each bit in the current + * byte of the address may contribute the calculation. If + * the latter and the MSB in the CRC are different, then + * the CRC value so computed is also ex-ored with the + * "polynomium generator". The current byte of the address + * is also shifted right by one bit at each iteration. + * This is because the CRC generatore in hardware is implemented + * as a shift-register with as many ex-ores as the radixes + * in the polynomium. This suggests that we represent the + * polynomiumm itself as a 32-bit constant. + */ + for (byte = 0; byte < 6; byte++) { + currByte = mac[byte]; + for (bit = 0; bit < 8; bit++) { + if ((currByte & 0x01) ^ (crc & 0x01)) { + crc >>= 1; + crc = crc ^ 0xedb88320; + } else { + crc >>= 1; + } + currByte >>= 1; + } + } + + crc = crc >> 26; + + /* + * Set individual hash table register + */ + if (crc >= 32) { + fec->eth->iaddr1 = (1 << (crc - 32)); + fec->eth->iaddr2 = 0; + } else { + fec->eth->iaddr1 = 0; + fec->eth->iaddr2 = (1 << crc); + } + + /* + * Set physical address + */ + fec->eth->paddr1 = (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3]; + fec->eth->paddr2 = (mac[4] << 24) + (mac[5] << 16) + 0x8808; +} + +/********************************************************************/ +static int mpc5xxx_fec_init(struct eth_device *dev, bd_t * bis) +{ + mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv; + struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA; + +#if (DEBUG & 0x1) + printf ("mpc5xxx_fec_init... Begin\n"); +#endif + + mpc5xxx_fec_init_phy(dev, bis); + + /* + * Call board-specific PHY fixups (if any) + */ +#ifdef CONFIG_RESET_PHY_R + reset_phy(); +#endif + + /* + * Initialize RxBD/TxBD rings + */ + mpc5xxx_fec_rbd_init(fec); + mpc5xxx_fec_tbd_init(fec); + + /* + * Clear FEC-Lite interrupt event register(IEVENT) + */ + fec->eth->ievent = 0xffffffff; + + /* + * Set interrupt mask register + */ + fec->eth->imask = 0x00000000; + + /* + * Set FEC-Lite receive control register(R_CNTRL): + */ + if (fec->xcv_type == SEVENWIRE) { + /* + * Frame length=1518; 7-wire mode + */ + fec->eth->r_cntrl = 0x05ee0020; /*0x05ee0000;FIXME */ + } else { + /* + * Frame length=1518; MII mode; + */ + fec->eth->r_cntrl = 0x05ee0024; /*0x05ee0004;FIXME */ + } + + fec->eth->x_cntrl = 0x00000000; /* half-duplex, heartbeat disabled */ + + /* + * Set Opcode/Pause Duration Register + */ + fec->eth->op_pause = 0x00010020; /*FIXME 0xffff0020; */ + + /* + * Set Rx FIFO alarm and granularity value + */ + fec->eth->rfifo_cntrl = 0x0c000000 + | (fec->eth->rfifo_cntrl & ~0x0f000000); + fec->eth->rfifo_alarm = 0x0000030c; +#if (DEBUG & 0x22) + if (fec->eth->rfifo_status & 0x00700000 ) { + printf("mpc5xxx_fec_init() RFIFO error\n"); + } +#endif + + /* + * Set Tx FIFO granularity value + */ + fec->eth->tfifo_cntrl = 0x0c000000 + | (fec->eth->tfifo_cntrl & ~0x0f000000); +#if (DEBUG & 0x2) + printf("tfifo_status: 0x%08x\n", fec->eth->tfifo_status); + printf("tfifo_alarm: 0x%08x\n", fec->eth->tfifo_alarm); +#endif + + /* + * Set transmit fifo watermark register(X_WMRK), default = 64 + */ + fec->eth->tfifo_alarm = 0x00000080; + fec->eth->x_wmrk = 0x2; + + /* + * Set individual address filter for unicast address + * and set physical address registers. + */ + mpc5xxx_fec_set_hwaddr(fec, (char *)dev->enetaddr); + + /* + * Set multicast address filter + */ + fec->eth->gaddr1 = 0x00000000; + fec->eth->gaddr2 = 0x00000000; + + /* + * Turn ON cheater FSM: ???? + */ + fec->eth->xmit_fsm = 0x03000000; + + /* + * Turn off COMM bus prefetch in the MPC5200 BestComm. It doesn't + * work w/ the current receive task. + */ + sdma->PtdCntrl |= 0x00000001; + + /* + * Set priority of different initiators + */ + sdma->IPR0 = 7; /* always */ + sdma->IPR3 = 6; /* Eth RX */ + sdma->IPR4 = 5; /* Eth Tx */ + + /* + * Clear SmartDMA task interrupt pending bits + */ + SDMA_CLEAR_IEVENT(FEC_RECV_TASK_NO); + + /* + * Initialize SmartDMA parameters stored in SRAM + */ + *(volatile int *)FEC_TBD_BASE = (int)fec->tbdBase; + *(volatile int *)FEC_RBD_BASE = (int)fec->rbdBase; + *(volatile int *)FEC_TBD_NEXT = (int)fec->tbdBase; + *(volatile int *)FEC_RBD_NEXT = (int)fec->rbdBase; + + /* + * Enable FEC-Lite controller + */ + fec->eth->ecntrl |= 0x00000006; + +#if (DEBUG & 0x2) + if (fec->xcv_type != SEVENWIRE) + mpc5xxx_fec_phydump (dev->name); +#endif + + /* + * Enable SmartDMA receive task + */ + SDMA_TASK_ENABLE(FEC_RECV_TASK_NO); + +#if (DEBUG & 0x1) + printf("mpc5xxx_fec_init... Done \n"); +#endif + + return 1; +} + +/********************************************************************/ +static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis) +{ + mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv; + const uint8 phyAddr = CONFIG_PHY_ADDR; /* Only one PHY */ + static int initialized = 0; + + if(initialized) + return 0; + initialized = 1; + +#if (DEBUG & 0x1) + printf ("mpc5xxx_fec_init_phy... Begin\n"); +#endif + + /* + * Initialize GPIO pins + */ + if (fec->xcv_type == SEVENWIRE) { + /* 10MBit with 7-wire operation */ + /* 7-wire only */ + *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00020000; + } else { + /* 100MBit with MD operation */ + *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00050000; + } + + /* + * Clear FEC-Lite interrupt event register(IEVENT) + */ + fec->eth->ievent = 0xffffffff; + + /* + * Set interrupt mask register + */ + fec->eth->imask = 0x00000000; + +/* + * In original Promess-provided code PHY initialization is disabled with the + * following comment: "Phy initialization is DISABLED for now. There was a + * problem with running 100 Mbps on PRO board". Thus we temporarily disable + * PHY initialization for the Motion-PRO board, until a proper fix is found. + */ + + if (fec->xcv_type != SEVENWIRE) { + /* + * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock + * and do not drop the Preamble. + * No MII for 7-wire mode + */ + fec->eth->mii_speed = (((gd->arch.ipb_clk >> 20) / 5) << 1); + } + + if (fec->xcv_type != SEVENWIRE) { + /* + * Initialize PHY(LXT971A): + * + * Generally, on power up, the LXT971A reads its configuration + * pins to check for forced operation, If not cofigured for + * forced operation, it uses auto-negotiation/parallel detection + * to automatically determine line operating conditions. + * If the PHY device on the other side of the link supports + * auto-negotiation, the LXT971A auto-negotiates with it + * using Fast Link Pulse(FLP) Bursts. If the PHY partner does not + * support auto-negotiation, the LXT971A automatically detects + * the presence of either link pulses(10Mbps PHY) or Idle + * symbols(100Mbps) and sets its operating conditions accordingly. + * + * When auto-negotiation is controlled by software, the following + * steps are recommended. + * + * Note: + * The physical address is dependent on hardware configuration. + * + */ + int timeout = 1; + uint16 phyStatus; + + /* + * Reset PHY, then delay 300ns + */ + miiphy_write(dev->name, phyAddr, 0x0, 0x8000); + udelay(1000); + + if (fec->xcv_type == MII10) { + /* + * Force 10Base-T, FDX operation + */ +#if (DEBUG & 0x2) + printf("Forcing 10 Mbps ethernet link... "); +#endif + miiphy_read(dev->name, phyAddr, 0x1, &phyStatus); + /* + miiphy_write(dev->name, fec, phyAddr, 0x0, 0x0100); + */ + miiphy_write(dev->name, phyAddr, 0x0, 0x0180); + + timeout = 20; + do { /* wait for link status to go down */ + udelay(10000); + if ((timeout--) == 0) { +#if (DEBUG & 0x2) + printf("hmmm, should not have waited..."); +#endif + break; + } + miiphy_read(dev->name, phyAddr, 0x1, &phyStatus); +#if (DEBUG & 0x2) + printf("="); +#endif + } while ((phyStatus & 0x0004)); /* !link up */ + + timeout = 1000; + do { /* wait for link status to come back up */ + udelay(10000); + if ((timeout--) == 0) { + printf("failed. Link is down.\n"); + break; + } + miiphy_read(dev->name, phyAddr, 0x1, &phyStatus); +#if (DEBUG & 0x2) + printf("+"); +#endif + } while (!(phyStatus & 0x0004)); /* !link up */ + +#if (DEBUG & 0x2) + printf ("done.\n"); +#endif + } else { /* MII100 */ + /* + * Set the auto-negotiation advertisement register bits + */ + miiphy_write(dev->name, phyAddr, 0x4, 0x01e1); + + /* + * Set MDIO bit 0.12 = 1(&& bit 0.9=1?) to enable auto-negotiation + */ + miiphy_write(dev->name, phyAddr, 0x0, 0x1200); + + /* + * Wait for AN completion + */ + timeout = 5000; + do { + udelay(1000); + + if ((timeout--) == 0) { +#if (DEBUG & 0x2) + printf("PHY auto neg 0 failed...\n"); +#endif + return -1; + } + + if (miiphy_read(dev->name, phyAddr, 0x1, &phyStatus) != 0) { +#if (DEBUG & 0x2) + printf("PHY auto neg 1 failed 0x%04x...\n", phyStatus); +#endif + return -1; + } + } while (!(phyStatus & 0x0004)); + +#if (DEBUG & 0x2) + printf("PHY auto neg complete! \n"); +#endif + } + + } + +#if (DEBUG & 0x2) + if (fec->xcv_type != SEVENWIRE) + mpc5xxx_fec_phydump (dev->name); +#endif + + +#if (DEBUG & 0x1) + printf("mpc5xxx_fec_init_phy... Done \n"); +#endif + + return 1; +} + +/********************************************************************/ +static void mpc5xxx_fec_halt(struct eth_device *dev) +{ + struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA; + mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv; + int counter = 0xffff; + +#if (DEBUG & 0x2) + if (fec->xcv_type != SEVENWIRE) + mpc5xxx_fec_phydump (dev->name); +#endif + + /* + * mask FEC chip interrupts + */ + fec->eth->imask = 0; + + /* + * issue graceful stop command to the FEC transmitter if necessary + */ + fec->eth->x_cntrl |= 0x00000001; + + /* + * wait for graceful stop to register + */ + while ((counter--) && (!(fec->eth->ievent & 0x10000000))) ; + + /* + * Disable SmartDMA tasks + */ + SDMA_TASK_DISABLE (FEC_XMIT_TASK_NO); + SDMA_TASK_DISABLE (FEC_RECV_TASK_NO); + + /* + * Turn on COMM bus prefetch in the MPC5200 BestComm after we're + * done. It doesn't work w/ the current receive task. + */ + sdma->PtdCntrl &= ~0x00000001; + + /* + * Disable the Ethernet Controller + */ + fec->eth->ecntrl &= 0xfffffffd; + + /* + * Clear FIFO status registers + */ + fec->eth->rfifo_status &= 0x00700000; + fec->eth->tfifo_status &= 0x00700000; + + fec->eth->reset_cntrl = 0x01000000; + + /* + * Issue a reset command to the FEC chip + */ + fec->eth->ecntrl |= 0x1; + + /* + * wait at least 16 clock cycles + */ + udelay(10); + + /* don't leave the MII speed set to zero */ + if (fec->xcv_type != SEVENWIRE) { + /* + * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock + * and do not drop the Preamble. + * No MII for 7-wire mode + */ + fec->eth->mii_speed = (((gd->arch.ipb_clk >> 20) / 5) << 1); + } + +#if (DEBUG & 0x3) + printf("Ethernet task stopped\n"); +#endif +} + +#if (DEBUG & 0x60) +/********************************************************************/ + +static void tfifo_print(char *devname, mpc5xxx_fec_priv *fec) +{ + uint16 phyAddr = CONFIG_PHY_ADDR; + uint16 phyStatus; + + if ((fec->eth->tfifo_lrf_ptr != fec->eth->tfifo_lwf_ptr) + || (fec->eth->tfifo_rdptr != fec->eth->tfifo_wrptr)) { + + miiphy_read(devname, phyAddr, 0x1, &phyStatus); + printf("\nphyStatus: 0x%04x\n", phyStatus); + printf("ecntrl: 0x%08x\n", fec->eth->ecntrl); + printf("ievent: 0x%08x\n", fec->eth->ievent); + printf("x_status: 0x%08x\n", fec->eth->x_status); + printf("tfifo: status 0x%08x\n", fec->eth->tfifo_status); + + printf(" control 0x%08x\n", fec->eth->tfifo_cntrl); + printf(" lrfp 0x%08x\n", fec->eth->tfifo_lrf_ptr); + printf(" lwfp 0x%08x\n", fec->eth->tfifo_lwf_ptr); + printf(" alarm 0x%08x\n", fec->eth->tfifo_alarm); + printf(" readptr 0x%08x\n", fec->eth->tfifo_rdptr); + printf(" writptr 0x%08x\n", fec->eth->tfifo_wrptr); + } +} + +static void rfifo_print(char *devname, mpc5xxx_fec_priv *fec) +{ + uint16 phyAddr = CONFIG_PHY_ADDR; + uint16 phyStatus; + + if ((fec->eth->rfifo_lrf_ptr != fec->eth->rfifo_lwf_ptr) + || (fec->eth->rfifo_rdptr != fec->eth->rfifo_wrptr)) { + + miiphy_read(devname, phyAddr, 0x1, &phyStatus); + printf("\nphyStatus: 0x%04x\n", phyStatus); + printf("ecntrl: 0x%08x\n", fec->eth->ecntrl); + printf("ievent: 0x%08x\n", fec->eth->ievent); + printf("x_status: 0x%08x\n", fec->eth->x_status); + printf("rfifo: status 0x%08x\n", fec->eth->rfifo_status); + + printf(" control 0x%08x\n", fec->eth->rfifo_cntrl); + printf(" lrfp 0x%08x\n", fec->eth->rfifo_lrf_ptr); + printf(" lwfp 0x%08x\n", fec->eth->rfifo_lwf_ptr); + printf(" alarm 0x%08x\n", fec->eth->rfifo_alarm); + printf(" readptr 0x%08x\n", fec->eth->rfifo_rdptr); + printf(" writptr 0x%08x\n", fec->eth->rfifo_wrptr); + } +} +#endif /* DEBUG */ + +/********************************************************************/ + +static int mpc5xxx_fec_send(struct eth_device *dev, void *eth_data, + int data_length) +{ + /* + * This routine transmits one frame. This routine only accepts + * 6-byte Ethernet addresses. + */ + mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv; + volatile FEC_TBD *pTbd; + +#if (DEBUG & 0x20) + printf("tbd status: 0x%04x\n", fec->tbdBase[0].status); + tfifo_print(dev->name, fec); +#endif + + /* + * Clear Tx BD ring at first + */ + mpc5xxx_fec_tbd_scrub(fec); + + /* + * Check for valid length of data. + */ + if ((data_length > 1500) || (data_length <= 0)) { + return -1; + } + + /* + * Check the number of vacant TxBDs. + */ + if (fec->cleanTbdNum < 1) { +#if (DEBUG & 0x20) + printf("No available TxBDs ...\n"); +#endif + return -1; + } + + /* + * Get the first TxBD to send the mac header + */ + pTbd = &fec->tbdBase[fec->tbdIndex]; + pTbd->dataLength = data_length; + pTbd->dataPointer = (uint32)eth_data; + pTbd->status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY; + fec->tbdIndex = (fec->tbdIndex + 1) % FEC_TBD_NUM; + +#if (DEBUG & 0x100) + printf("SDMA_TASK_ENABLE, fec->tbdIndex = %d \n", fec->tbdIndex); +#endif + + /* + * Kick the MII i/f + */ + if (fec->xcv_type != SEVENWIRE) { + uint16 phyStatus; + miiphy_read(dev->name, 0, 0x1, &phyStatus); + } + + /* + * Enable SmartDMA transmit task + */ + +#if (DEBUG & 0x20) + tfifo_print(dev->name, fec); +#endif + SDMA_TASK_ENABLE (FEC_XMIT_TASK_NO); +#if (DEBUG & 0x20) + tfifo_print(dev->name, fec); +#endif +#if (DEBUG & 0x8) + printf( "+" ); +#endif + + fec->cleanTbdNum -= 1; + +#if (DEBUG & 0x129) && (DEBUG & 0x80000000) + printf ("smartDMA ethernet Tx task enabled\n"); +#endif + /* + * wait until frame is sent . + */ + while (pTbd->status & FEC_TBD_READY) { + udelay(10); +#if (DEBUG & 0x8) + printf ("TDB status = %04x\n", pTbd->status); +#endif + } + + return 0; +} + + +/********************************************************************/ +static int mpc5xxx_fec_recv(struct eth_device *dev) +{ + /* + * This command pulls one frame from the card + */ + mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv; + volatile FEC_RBD *pRbd = &fec->rbdBase[fec->rbdIndex]; + unsigned long ievent; + int frame_length, len = 0; + NBUF *frame; + uchar buff[FEC_MAX_PKT_SIZE]; + +#if (DEBUG & 0x1) + printf ("mpc5xxx_fec_recv %d Start...\n", fec->rbdIndex); +#endif +#if (DEBUG & 0x8) + printf( "-" ); +#endif + + /* + * Check if any critical events have happened + */ + ievent = fec->eth->ievent; + fec->eth->ievent = ievent; + if (ievent & 0x20060000) { + /* BABT, Rx/Tx FIFO errors */ + mpc5xxx_fec_halt(dev); + mpc5xxx_fec_init(dev, NULL); + return 0; + } + if (ievent & 0x80000000) { + /* Heartbeat error */ + fec->eth->x_cntrl |= 0x00000001; + } + if (ievent & 0x10000000) { + /* Graceful stop complete */ + if (fec->eth->x_cntrl & 0x00000001) { + mpc5xxx_fec_halt(dev); + fec->eth->x_cntrl &= ~0x00000001; + mpc5xxx_fec_init(dev, NULL); + } + } + + if (!(pRbd->status & FEC_RBD_EMPTY)) { + if ((pRbd->status & FEC_RBD_LAST) && !(pRbd->status & FEC_RBD_ERR) && + ((pRbd->dataLength - 4) > 14)) { + + /* + * Get buffer address and size + */ + frame = (NBUF *)pRbd->dataPointer; + frame_length = pRbd->dataLength - 4; + +#if (DEBUG & 0x20) + { + int i; + printf("recv data hdr:"); + for (i = 0; i < 14; i++) + printf("%x ", *(frame->head + i)); + printf("\n"); + } +#endif + /* + * Fill the buffer and pass it to upper layers + */ + memcpy(buff, frame->head, 14); + memcpy(buff + 14, frame->data, frame_length); + net_process_received_packet(buff, frame_length); + len = frame_length; + } + /* + * Reset buffer descriptor as empty + */ + mpc5xxx_fec_rbd_clean(fec, pRbd); + } + SDMA_CLEAR_IEVENT (FEC_RECV_TASK_NO); + return len; +} + + +/********************************************************************/ +int mpc5xxx_fec_initialize(bd_t * bis) +{ + mpc5xxx_fec_priv *fec; + struct eth_device *dev; + char *tmp, *end; + char env_enetaddr[6]; + int i; + + fec = (mpc5xxx_fec_priv *)malloc(sizeof(*fec)); + dev = (struct eth_device *)malloc(sizeof(*dev)); + memset(dev, 0, sizeof *dev); + + fec->eth = (ethernet_regs *)MPC5XXX_FEC; + fec->tbdBase = (FEC_TBD *)FEC_BD_BASE; + fec->rbdBase = (FEC_RBD *)(FEC_BD_BASE + FEC_TBD_NUM * sizeof(FEC_TBD)); +#if defined(CONFIG_MPC5xxx_FEC_MII100) + fec->xcv_type = MII100; +#elif defined(CONFIG_MPC5xxx_FEC_MII10) + fec->xcv_type = MII10; +#elif defined(CONFIG_MPC5xxx_FEC_SEVENWIRE) + fec->xcv_type = SEVENWIRE; +#else +#error fec->xcv_type not initialized. +#endif + if (fec->xcv_type != SEVENWIRE) { + /* + * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock + * and do not drop the Preamble. + * No MII for 7-wire mode + */ + fec->eth->mii_speed = (((gd->arch.ipb_clk >> 20) / 5) << 1); + } + + dev->priv = (void *)fec; + dev->iobase = MPC5XXX_FEC; + dev->init = mpc5xxx_fec_init; + dev->halt = mpc5xxx_fec_halt; + dev->send = mpc5xxx_fec_send; + dev->recv = mpc5xxx_fec_recv; + + sprintf(dev->name, "FEC"); + eth_register(dev); + +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) + miiphy_register (dev->name, + fec5xxx_miiphy_read, fec5xxx_miiphy_write); +#endif + + /* + * Try to set the mac address now. The fec mac address is + * a garbage after reset. When not using fec for booting + * the Linux fec driver will try to work with this garbage. + */ + tmp = getenv("ethaddr"); + if (tmp) { + for (i=0; i<6; i++) { + env_enetaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0; + if (tmp) + tmp = (*end) ? end+1 : end; + } + mpc5xxx_fec_set_hwaddr(fec, env_enetaddr); + } + + return 1; +} + +/* MII-interface related functions */ +/********************************************************************/ +int fec5xxx_miiphy_read(const char *devname, uint8 phyAddr, uint8 regAddr, uint16 * retVal) +{ + ethernet_regs *eth = (ethernet_regs *)MPC5XXX_FEC; + uint32 reg; /* convenient holder for the PHY register */ + uint32 phy; /* convenient holder for the PHY */ + int timeout = 0xffff; + + /* + * reading from any PHY's register is done by properly + * programming the FEC's MII data register. + */ + reg = regAddr << FEC_MII_DATA_RA_SHIFT; + phy = phyAddr << FEC_MII_DATA_PA_SHIFT; + + eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | phy | reg); + + /* + * wait for the related interrupt + */ + while ((timeout--) && (!(eth->ievent & 0x00800000))) ; + + if (timeout == 0) { +#if (DEBUG & 0x2) + printf ("Read MDIO failed...\n"); +#endif + return -1; + } + + /* + * clear mii interrupt bit + */ + eth->ievent = 0x00800000; + + /* + * it's now safe to read the PHY's register + */ + *retVal = (uint16) eth->mii_data; + + return 0; +} + +/********************************************************************/ +int fec5xxx_miiphy_write(const char *devname, uint8 phyAddr, uint8 regAddr, uint16 data) +{ + ethernet_regs *eth = (ethernet_regs *)MPC5XXX_FEC; + uint32 reg; /* convenient holder for the PHY register */ + uint32 phy; /* convenient holder for the PHY */ + int timeout = 0xffff; + + reg = regAddr << FEC_MII_DATA_RA_SHIFT; + phy = phyAddr << FEC_MII_DATA_PA_SHIFT; + + eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR | + FEC_MII_DATA_TA | phy | reg | data); + + /* + * wait for the MII interrupt + */ + while ((timeout--) && (!(eth->ievent & 0x00800000))) ; + + if (timeout == 0) { +#if (DEBUG & 0x2) + printf ("Write MDIO failed...\n"); +#endif + return -1; + } + + /* + * clear MII interrupt bit + */ + eth->ievent = 0x00800000; + + return 0; +} diff --git a/sources/uboot-be550/drivers/net/mpc5xxx_fec.h b/sources/uboot-be550/drivers/net/mpc5xxx_fec.h new file mode 100644 index 00000000..16c3e8e9 --- /dev/null +++ b/sources/uboot-be550/drivers/net/mpc5xxx_fec.h @@ -0,0 +1,282 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * This file is based on mpc4200fec.h + * (C) Copyright Motorola, Inc., 2000 + * + * odin ethernet header file + */ + +#ifndef __MPC5XXX_FEC_H +#define __MPC5XXX_FEC_H + +typedef unsigned long uint32; +typedef unsigned short uint16; +typedef unsigned char uint8; + +typedef struct ethernet_register_set { + +/* [10:2]addr = 00 */ + +/* Control and status Registers (offset 000-1FF) */ + + volatile uint32 fec_id; /* MBAR_ETH + 0x000 */ + volatile uint32 ievent; /* MBAR_ETH + 0x004 */ + volatile uint32 imask; /* MBAR_ETH + 0x008 */ + + volatile uint32 RES0[1]; /* MBAR_ETH + 0x00C */ + volatile uint32 r_des_active; /* MBAR_ETH + 0x010 */ + volatile uint32 x_des_active; /* MBAR_ETH + 0x014 */ + volatile uint32 r_des_active_cl; /* MBAR_ETH + 0x018 */ + volatile uint32 x_des_active_cl; /* MBAR_ETH + 0x01C */ + volatile uint32 ivent_set; /* MBAR_ETH + 0x020 */ + volatile uint32 ecntrl; /* MBAR_ETH + 0x024 */ + + volatile uint32 RES1[6]; /* MBAR_ETH + 0x028-03C */ + volatile uint32 mii_data; /* MBAR_ETH + 0x040 */ + volatile uint32 mii_speed; /* MBAR_ETH + 0x044 */ + volatile uint32 mii_status; /* MBAR_ETH + 0x048 */ + + volatile uint32 RES2[5]; /* MBAR_ETH + 0x04C-05C */ + volatile uint32 mib_data; /* MBAR_ETH + 0x060 */ + volatile uint32 mib_control; /* MBAR_ETH + 0x064 */ + + volatile uint32 RES3[6]; /* MBAR_ETH + 0x068-7C */ + volatile uint32 r_activate; /* MBAR_ETH + 0x080 */ + volatile uint32 r_cntrl; /* MBAR_ETH + 0x084 */ + volatile uint32 r_hash; /* MBAR_ETH + 0x088 */ + volatile uint32 r_data; /* MBAR_ETH + 0x08C */ + volatile uint32 ar_done; /* MBAR_ETH + 0x090 */ + volatile uint32 r_test; /* MBAR_ETH + 0x094 */ + volatile uint32 r_mib; /* MBAR_ETH + 0x098 */ + volatile uint32 r_da_low; /* MBAR_ETH + 0x09C */ + volatile uint32 r_da_high; /* MBAR_ETH + 0x0A0 */ + + volatile uint32 RES4[7]; /* MBAR_ETH + 0x0A4-0BC */ + volatile uint32 x_activate; /* MBAR_ETH + 0x0C0 */ + volatile uint32 x_cntrl; /* MBAR_ETH + 0x0C4 */ + volatile uint32 backoff; /* MBAR_ETH + 0x0C8 */ + volatile uint32 x_data; /* MBAR_ETH + 0x0CC */ + volatile uint32 x_status; /* MBAR_ETH + 0x0D0 */ + volatile uint32 x_mib; /* MBAR_ETH + 0x0D4 */ + volatile uint32 x_test; /* MBAR_ETH + 0x0D8 */ + volatile uint32 fdxfc_da1; /* MBAR_ETH + 0x0DC */ + volatile uint32 fdxfc_da2; /* MBAR_ETH + 0x0E0 */ + volatile uint32 paddr1; /* MBAR_ETH + 0x0E4 */ + volatile uint32 paddr2; /* MBAR_ETH + 0x0E8 */ + volatile uint32 op_pause; /* MBAR_ETH + 0x0EC */ + + volatile uint32 RES5[4]; /* MBAR_ETH + 0x0F0-0FC */ + volatile uint32 instr_reg; /* MBAR_ETH + 0x100 */ + volatile uint32 context_reg; /* MBAR_ETH + 0x104 */ + volatile uint32 test_cntrl; /* MBAR_ETH + 0x108 */ + volatile uint32 acc_reg; /* MBAR_ETH + 0x10C */ + volatile uint32 ones; /* MBAR_ETH + 0x110 */ + volatile uint32 zeros; /* MBAR_ETH + 0x114 */ + volatile uint32 iaddr1; /* MBAR_ETH + 0x118 */ + volatile uint32 iaddr2; /* MBAR_ETH + 0x11C */ + volatile uint32 gaddr1; /* MBAR_ETH + 0x120 */ + volatile uint32 gaddr2; /* MBAR_ETH + 0x124 */ + volatile uint32 random; /* MBAR_ETH + 0x128 */ + volatile uint32 rand1; /* MBAR_ETH + 0x12C */ + volatile uint32 tmp; /* MBAR_ETH + 0x130 */ + + volatile uint32 RES6[3]; /* MBAR_ETH + 0x134-13C */ + volatile uint32 fifo_id; /* MBAR_ETH + 0x140 */ + volatile uint32 x_wmrk; /* MBAR_ETH + 0x144 */ + volatile uint32 fcntrl; /* MBAR_ETH + 0x148 */ + volatile uint32 r_bound; /* MBAR_ETH + 0x14C */ + volatile uint32 r_fstart; /* MBAR_ETH + 0x150 */ + volatile uint32 r_count; /* MBAR_ETH + 0x154 */ + volatile uint32 r_lag; /* MBAR_ETH + 0x158 */ + volatile uint32 r_read; /* MBAR_ETH + 0x15C */ + volatile uint32 r_write; /* MBAR_ETH + 0x160 */ + volatile uint32 x_count; /* MBAR_ETH + 0x164 */ + volatile uint32 x_lag; /* MBAR_ETH + 0x168 */ + volatile uint32 x_retry; /* MBAR_ETH + 0x16C */ + volatile uint32 x_write; /* MBAR_ETH + 0x170 */ + volatile uint32 x_read; /* MBAR_ETH + 0x174 */ + + volatile uint32 RES7[2]; /* MBAR_ETH + 0x178-17C */ + volatile uint32 fm_cntrl; /* MBAR_ETH + 0x180 */ + volatile uint32 rfifo_data; /* MBAR_ETH + 0x184 */ + volatile uint32 rfifo_status; /* MBAR_ETH + 0x188 */ + volatile uint32 rfifo_cntrl; /* MBAR_ETH + 0x18C */ + volatile uint32 rfifo_lrf_ptr; /* MBAR_ETH + 0x190 */ + volatile uint32 rfifo_lwf_ptr; /* MBAR_ETH + 0x194 */ + volatile uint32 rfifo_alarm; /* MBAR_ETH + 0x198 */ + volatile uint32 rfifo_rdptr; /* MBAR_ETH + 0x19C */ + volatile uint32 rfifo_wrptr; /* MBAR_ETH + 0x1A0 */ + volatile uint32 tfifo_data; /* MBAR_ETH + 0x1A4 */ + volatile uint32 tfifo_status; /* MBAR_ETH + 0x1A8 */ + volatile uint32 tfifo_cntrl; /* MBAR_ETH + 0x1AC */ + volatile uint32 tfifo_lrf_ptr; /* MBAR_ETH + 0x1B0 */ + volatile uint32 tfifo_lwf_ptr; /* MBAR_ETH + 0x1B4 */ + volatile uint32 tfifo_alarm; /* MBAR_ETH + 0x1B8 */ + volatile uint32 tfifo_rdptr; /* MBAR_ETH + 0x1BC */ + volatile uint32 tfifo_wrptr; /* MBAR_ETH + 0x1C0 */ + + volatile uint32 reset_cntrl; /* MBAR_ETH + 0x1C4 */ + volatile uint32 xmit_fsm; /* MBAR_ETH + 0x1C8 */ + + volatile uint32 RES8[3]; /* MBAR_ETH + 0x1CC-1D4 */ + volatile uint32 rdes_data0; /* MBAR_ETH + 0x1D8 */ + volatile uint32 rdes_data1; /* MBAR_ETH + 0x1DC */ + volatile uint32 r_length; /* MBAR_ETH + 0x1E0 */ + volatile uint32 x_length; /* MBAR_ETH + 0x1E4 */ + volatile uint32 x_addr; /* MBAR_ETH + 0x1E8 */ + volatile uint32 cdes_data; /* MBAR_ETH + 0x1EC */ + volatile uint32 status; /* MBAR_ETH + 0x1F0 */ + volatile uint32 dma_control; /* MBAR_ETH + 0x1F4 */ + volatile uint32 des_cmnd; /* MBAR_ETH + 0x1F8 */ + volatile uint32 data; /* MBAR_ETH + 0x1FC */ + +/* MIB COUNTERS (Offset 200-2FF) */ + + volatile uint32 rmon_t_drop; /* MBAR_ETH + 0x200 */ + volatile uint32 rmon_t_packets; /* MBAR_ETH + 0x204 */ + volatile uint32 rmon_t_bc_pkt; /* MBAR_ETH + 0x208 */ + volatile uint32 rmon_t_mc_pkt; /* MBAR_ETH + 0x20C */ + volatile uint32 rmon_t_crc_align; /* MBAR_ETH + 0x210 */ + volatile uint32 rmon_t_undersize; /* MBAR_ETH + 0x214 */ + volatile uint32 rmon_t_oversize; /* MBAR_ETH + 0x218 */ + volatile uint32 rmon_t_frag; /* MBAR_ETH + 0x21C */ + volatile uint32 rmon_t_jab; /* MBAR_ETH + 0x220 */ + volatile uint32 rmon_t_col; /* MBAR_ETH + 0x224 */ + volatile uint32 rmon_t_p64; /* MBAR_ETH + 0x228 */ + volatile uint32 rmon_t_p65to127; /* MBAR_ETH + 0x22C */ + volatile uint32 rmon_t_p128to255; /* MBAR_ETH + 0x230 */ + volatile uint32 rmon_t_p256to511; /* MBAR_ETH + 0x234 */ + volatile uint32 rmon_t_p512to1023; /* MBAR_ETH + 0x238 */ + volatile uint32 rmon_t_p1024to2047; /* MBAR_ETH + 0x23C */ + volatile uint32 rmon_t_p_gte2048; /* MBAR_ETH + 0x240 */ + volatile uint32 rmon_t_octets; /* MBAR_ETH + 0x244 */ + volatile uint32 ieee_t_drop; /* MBAR_ETH + 0x248 */ + volatile uint32 ieee_t_frame_ok; /* MBAR_ETH + 0x24C */ + volatile uint32 ieee_t_1col; /* MBAR_ETH + 0x250 */ + volatile uint32 ieee_t_mcol; /* MBAR_ETH + 0x254 */ + volatile uint32 ieee_t_def; /* MBAR_ETH + 0x258 */ + volatile uint32 ieee_t_lcol; /* MBAR_ETH + 0x25C */ + volatile uint32 ieee_t_excol; /* MBAR_ETH + 0x260 */ + volatile uint32 ieee_t_macerr; /* MBAR_ETH + 0x264 */ + volatile uint32 ieee_t_cserr; /* MBAR_ETH + 0x268 */ + volatile uint32 ieee_t_sqe; /* MBAR_ETH + 0x26C */ + volatile uint32 t_fdxfc; /* MBAR_ETH + 0x270 */ + volatile uint32 ieee_t_octets_ok; /* MBAR_ETH + 0x274 */ + + volatile uint32 RES9[2]; /* MBAR_ETH + 0x278-27C */ + volatile uint32 rmon_r_drop; /* MBAR_ETH + 0x280 */ + volatile uint32 rmon_r_packets; /* MBAR_ETH + 0x284 */ + volatile uint32 rmon_r_bc_pkt; /* MBAR_ETH + 0x288 */ + volatile uint32 rmon_r_mc_pkt; /* MBAR_ETH + 0x28C */ + volatile uint32 rmon_r_crc_align; /* MBAR_ETH + 0x290 */ + volatile uint32 rmon_r_undersize; /* MBAR_ETH + 0x294 */ + volatile uint32 rmon_r_oversize; /* MBAR_ETH + 0x298 */ + volatile uint32 rmon_r_frag; /* MBAR_ETH + 0x29C */ + volatile uint32 rmon_r_jab; /* MBAR_ETH + 0x2A0 */ + + volatile uint32 rmon_r_resvd_0; /* MBAR_ETH + 0x2A4 */ + + volatile uint32 rmon_r_p64; /* MBAR_ETH + 0x2A8 */ + volatile uint32 rmon_r_p65to127; /* MBAR_ETH + 0x2AC */ + volatile uint32 rmon_r_p128to255; /* MBAR_ETH + 0x2B0 */ + volatile uint32 rmon_r_p256to511; /* MBAR_ETH + 0x2B4 */ + volatile uint32 rmon_r_p512to1023; /* MBAR_ETH + 0x2B8 */ + volatile uint32 rmon_r_p1024to2047; /* MBAR_ETH + 0x2BC */ + volatile uint32 rmon_r_p_gte2048; /* MBAR_ETH + 0x2C0 */ + volatile uint32 rmon_r_octets; /* MBAR_ETH + 0x2C4 */ + volatile uint32 ieee_r_drop; /* MBAR_ETH + 0x2C8 */ + volatile uint32 ieee_r_frame_ok; /* MBAR_ETH + 0x2CC */ + volatile uint32 ieee_r_crc; /* MBAR_ETH + 0x2D0 */ + volatile uint32 ieee_r_align; /* MBAR_ETH + 0x2D4 */ + volatile uint32 r_macerr; /* MBAR_ETH + 0x2D8 */ + volatile uint32 r_fdxfc; /* MBAR_ETH + 0x2DC */ + volatile uint32 ieee_r_octets_ok; /* MBAR_ETH + 0x2E0 */ + + volatile uint32 RES10[6]; /* MBAR_ETH + 0x2E4-2FC */ + + volatile uint32 RES11[64]; /* MBAR_ETH + 0x300-3FF */ +} ethernet_regs; + +/* Receive & Transmit Buffer Descriptor definitions */ +typedef struct BufferDescriptor { + uint16 status; + uint16 dataLength; + uint32 dataPointer; +} FEC_RBD; +typedef struct { + uint16 status; + uint16 dataLength; + uint32 dataPointer; +} FEC_TBD; + +/* private structure */ +typedef enum { + SEVENWIRE, /* 7-wire */ + MII10, /* MII 10Mbps */ + MII100 /* MII 100Mbps */ +} xceiver_type; + +typedef struct { + ethernet_regs *eth; + xceiver_type xcv_type; /* transceiver type */ + FEC_RBD *rbdBase; /* RBD ring */ + FEC_TBD *tbdBase; /* TBD ring */ + uint16 rbdIndex; /* next receive BD to read */ + uint16 tbdIndex; /* next transmit BD to send */ + uint16 usedTbdIndex; /* next transmit BD to clean */ + uint16 cleanTbdNum; /* the number of available transmit BDs */ +} mpc5xxx_fec_priv; + +/* Ethernet parameter area */ +#define FEC_TBD_BASE (FEC_PARAM_BASE + 0x00) +#define FEC_TBD_NEXT (FEC_PARAM_BASE + 0x04) +#define FEC_RBD_BASE (FEC_PARAM_BASE + 0x08) +#define FEC_RBD_NEXT (FEC_PARAM_BASE + 0x0c) + +/* BD Numer definitions */ +#define FEC_TBD_NUM 48 /* The user can adjust this value */ +#define FEC_RBD_NUM 32 /* The user can adjust this value */ + +/* packet size limit */ +#define FEC_MAX_PKT_SIZE 1536 + +/* RBD bits definitions */ +#define FEC_RBD_EMPTY 0x8000 /* Buffer is empty */ +#define FEC_RBD_WRAP 0x2000 /* Last BD in ring */ +#define FEC_RBD_INT 0x1000 /* Interrupt */ +#define FEC_RBD_LAST 0x0800 /* Buffer is last in frame(useless) */ +#define FEC_RBD_MISS 0x0100 /* Miss bit for prom mode */ +#define FEC_RBD_BC 0x0080 /* The received frame is broadcast frame */ +#define FEC_RBD_MC 0x0040 /* The received frame is multicast frame */ +#define FEC_RBD_LG 0x0020 /* Frame length violation */ +#define FEC_RBD_NO 0x0010 /* Nonoctet align frame */ +#define FEC_RBD_SH 0x0008 /* Short frame */ +#define FEC_RBD_CR 0x0004 /* CRC error */ +#define FEC_RBD_OV 0x0002 /* Receive FIFO overrun */ +#define FEC_RBD_TR 0x0001 /* Frame is truncated */ +#define FEC_RBD_ERR (FEC_RBD_LG | FEC_RBD_NO | FEC_RBD_CR | \ + FEC_RBD_OV | FEC_RBD_TR) + +/* TBD bits definitions */ +#define FEC_TBD_READY 0x8000 /* Buffer is ready */ +#define FEC_TBD_WRAP 0x2000 /* Last BD in ring */ +#define FEC_TBD_INT 0x1000 /* Interrupt */ +#define FEC_TBD_LAST 0x0800 /* Buffer is last in frame */ +#define FEC_TBD_TC 0x0400 /* Transmit the CRC */ +#define FEC_TBD_ABC 0x0200 /* Append bad CRC */ + +/* MII-related definitios */ +#define FEC_MII_DATA_ST 0x40000000 /* Start of frame delimiter */ +#define FEC_MII_DATA_OP_RD 0x20000000 /* Perform a read operation */ +#define FEC_MII_DATA_OP_WR 0x10000000 /* Perform a write operation */ +#define FEC_MII_DATA_PA_MSK 0x0f800000 /* PHY Address field mask */ +#define FEC_MII_DATA_RA_MSK 0x007c0000 /* PHY Register field mask */ +#define FEC_MII_DATA_TA 0x00020000 /* Turnaround */ +#define FEC_MII_DATA_DATAMSK 0x0000ffff /* PHY data field */ + +#define FEC_MII_DATA_RA_SHIFT 18 /* MII Register address bits */ +#define FEC_MII_DATA_PA_SHIFT 23 /* MII PHY address bits */ + +#endif /* __MPC5XXX_FEC_H */ diff --git a/sources/uboot-be550/drivers/net/mvgbe.c b/sources/uboot-be550/drivers/net/mvgbe.c new file mode 100644 index 00000000..ab5aa68f --- /dev/null +++ b/sources/uboot-be550/drivers/net/mvgbe.c @@ -0,0 +1,795 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + * + * (C) Copyright 2003 + * Ingo Assmus + * + * based on - Driver for MV64360X ethernet ports + * Copyright (C) 2002 rabeeh@galileo.co.il + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#if defined(CONFIG_KIRKWOOD) +#include +#elif defined(CONFIG_ORION5X) +#include +#elif defined(CONFIG_DOVE) +#include +#endif + +#include "mvgbe.h" + +DECLARE_GLOBAL_DATA_PTR; + +#ifndef CONFIG_MVGBE_PORTS +# define CONFIG_MVGBE_PORTS {0, 0} +#endif + +#define MV_PHY_ADR_REQUEST 0xee +#define MVGBE_SMI_REG (((struct mvgbe_registers *)MVGBE0_BASE)->smi) + +#if defined(CONFIG_PHYLIB) || defined(CONFIG_MII) || defined(CONFIG_CMD_MII) +/* + * smi_reg_read - miiphy_read callback function. + * + * Returns 16bit phy register value, or 0xffff on error + */ +static int smi_reg_read(const char *devname, u8 phy_adr, u8 reg_ofs, u16 * data) +{ + struct eth_device *dev = eth_get_dev_by_name(devname); + struct mvgbe_device *dmvgbe = to_mvgbe(dev); + struct mvgbe_registers *regs = dmvgbe->regs; + u32 smi_reg; + u32 timeout; + + /* Phyadr read request */ + if (phy_adr == MV_PHY_ADR_REQUEST && + reg_ofs == MV_PHY_ADR_REQUEST) { + /* */ + *data = (u16) (MVGBE_REG_RD(regs->phyadr) & PHYADR_MASK); + return 0; + } + /* check parameters */ + if (phy_adr > PHYADR_MASK) { + printf("Err..(%s) Invalid PHY address %d\n", + __func__, phy_adr); + return -EFAULT; + } + if (reg_ofs > PHYREG_MASK) { + printf("Err..(%s) Invalid register offset %d\n", + __func__, reg_ofs); + return -EFAULT; + } + + timeout = MVGBE_PHY_SMI_TIMEOUT; + /* wait till the SMI is not busy */ + do { + /* read smi register */ + smi_reg = MVGBE_REG_RD(MVGBE_SMI_REG); + if (timeout-- == 0) { + printf("Err..(%s) SMI busy timeout\n", __func__); + return -EFAULT; + } + } while (smi_reg & MVGBE_PHY_SMI_BUSY_MASK); + + /* fill the phy address and regiser offset and read opcode */ + smi_reg = (phy_adr << MVGBE_PHY_SMI_DEV_ADDR_OFFS) + | (reg_ofs << MVGBE_SMI_REG_ADDR_OFFS) + | MVGBE_PHY_SMI_OPCODE_READ; + + /* write the smi register */ + MVGBE_REG_WR(MVGBE_SMI_REG, smi_reg); + + /*wait till read value is ready */ + timeout = MVGBE_PHY_SMI_TIMEOUT; + + do { + /* read smi register */ + smi_reg = MVGBE_REG_RD(MVGBE_SMI_REG); + if (timeout-- == 0) { + printf("Err..(%s) SMI read ready timeout\n", + __func__); + return -EFAULT; + } + } while (!(smi_reg & MVGBE_PHY_SMI_READ_VALID_MASK)); + + /* Wait for the data to update in the SMI register */ + for (timeout = 0; timeout < MVGBE_PHY_SMI_TIMEOUT; timeout++) + ; + + *data = (u16) (MVGBE_REG_RD(MVGBE_SMI_REG) & MVGBE_PHY_SMI_DATA_MASK); + + debug("%s:(adr %d, off %d) value= %04x\n", __func__, phy_adr, reg_ofs, + *data); + + return 0; +} + +/* + * smi_reg_write - imiiphy_write callback function. + * + * Returns 0 if write succeed, -EINVAL on bad parameters + * -ETIME on timeout + */ +static int smi_reg_write(const char *devname, u8 phy_adr, u8 reg_ofs, u16 data) +{ + struct eth_device *dev = eth_get_dev_by_name(devname); + struct mvgbe_device *dmvgbe = to_mvgbe(dev); + struct mvgbe_registers *regs = dmvgbe->regs; + u32 smi_reg; + u32 timeout; + + /* Phyadr write request*/ + if (phy_adr == MV_PHY_ADR_REQUEST && + reg_ofs == MV_PHY_ADR_REQUEST) { + MVGBE_REG_WR(regs->phyadr, data); + return 0; + } + + /* check parameters */ + if (phy_adr > PHYADR_MASK) { + printf("Err..(%s) Invalid phy address\n", __func__); + return -EINVAL; + } + if (reg_ofs > PHYREG_MASK) { + printf("Err..(%s) Invalid register offset\n", __func__); + return -EINVAL; + } + + /* wait till the SMI is not busy */ + timeout = MVGBE_PHY_SMI_TIMEOUT; + do { + /* read smi register */ + smi_reg = MVGBE_REG_RD(MVGBE_SMI_REG); + if (timeout-- == 0) { + printf("Err..(%s) SMI busy timeout\n", __func__); + return -ETIME; + } + } while (smi_reg & MVGBE_PHY_SMI_BUSY_MASK); + + /* fill the phy addr and reg offset and write opcode and data */ + smi_reg = (data << MVGBE_PHY_SMI_DATA_OFFS); + smi_reg |= (phy_adr << MVGBE_PHY_SMI_DEV_ADDR_OFFS) + | (reg_ofs << MVGBE_SMI_REG_ADDR_OFFS); + smi_reg &= ~MVGBE_PHY_SMI_OPCODE_READ; + + /* write the smi register */ + MVGBE_REG_WR(MVGBE_SMI_REG, smi_reg); + + return 0; +} +#endif + +#if defined(CONFIG_PHYLIB) +int mvgbe_phy_read(struct mii_dev *bus, int phy_addr, int dev_addr, + int reg_addr) +{ + u16 data; + int ret; + ret = smi_reg_read(bus->name, phy_addr, reg_addr, &data); + if (ret) + return ret; + return data; +} + +int mvgbe_phy_write(struct mii_dev *bus, int phy_addr, int dev_addr, + int reg_addr, u16 data) +{ + return smi_reg_write(bus->name, phy_addr, reg_addr, data); +} +#endif + +/* Stop and checks all queues */ +static void stop_queue(u32 * qreg) +{ + u32 reg_data; + + reg_data = readl(qreg); + + if (reg_data & 0xFF) { + /* Issue stop command for active channels only */ + writel((reg_data << 8), qreg); + + /* Wait for all queue activity to terminate. */ + do { + /* + * Check port cause register that all queues + * are stopped + */ + reg_data = readl(qreg); + } + while (reg_data & 0xFF); + } +} + +/* + * set_access_control - Config address decode parameters for Ethernet unit + * + * This function configures the address decode parameters for the Gigabit + * Ethernet Controller according the given parameters struct. + * + * @regs Register struct pointer. + * @param Address decode parameter struct. + */ +static void set_access_control(struct mvgbe_registers *regs, + struct mvgbe_winparam *param) +{ + u32 access_prot_reg; + + /* Set access control register */ + access_prot_reg = MVGBE_REG_RD(regs->epap); + /* clear window permission */ + access_prot_reg &= (~(3 << (param->win * 2))); + access_prot_reg |= (param->access_ctrl << (param->win * 2)); + MVGBE_REG_WR(regs->epap, access_prot_reg); + + /* Set window Size reg (SR) */ + MVGBE_REG_WR(regs->barsz[param->win].size, + (((param->size / 0x10000) - 1) << 16)); + + /* Set window Base address reg (BA) */ + MVGBE_REG_WR(regs->barsz[param->win].bar, + (param->target | param->attrib | param->base_addr)); + /* High address remap reg (HARR) */ + if (param->win < 4) + MVGBE_REG_WR(regs->ha_remap[param->win], param->high_addr); + + /* Base address enable reg (BARER) */ + if (param->enable == 1) + MVGBE_REG_BITS_RESET(regs->bare, (1 << param->win)); + else + MVGBE_REG_BITS_SET(regs->bare, (1 << param->win)); +} + +static void set_dram_access(struct mvgbe_registers *regs) +{ + struct mvgbe_winparam win_param; + int i; + + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + /* Set access parameters for DRAM bank i */ + win_param.win = i; /* Use Ethernet window i */ + /* Window target - DDR */ + win_param.target = MVGBE_TARGET_DRAM; + /* Enable full access */ + win_param.access_ctrl = EWIN_ACCESS_FULL; + win_param.high_addr = 0; + /* Get bank base and size */ + win_param.base_addr = gd->bd->bi_dram[i].start; + win_param.size = gd->bd->bi_dram[i].size; + if (win_param.size == 0) + win_param.enable = 0; + else + win_param.enable = 1; /* Enable the access */ + + /* Enable DRAM bank */ + switch (i) { + case 0: + win_param.attrib = EBAR_DRAM_CS0; + break; + case 1: + win_param.attrib = EBAR_DRAM_CS1; + break; + case 2: + win_param.attrib = EBAR_DRAM_CS2; + break; + case 3: + win_param.attrib = EBAR_DRAM_CS3; + break; + default: + /* invalid bank, disable access */ + win_param.enable = 0; + win_param.attrib = 0; + break; + } + /* Set the access control for address window(EPAPR) RD/WR */ + set_access_control(regs, &win_param); + } +} + +/* + * port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables + * + * Go through all the DA filter tables (Unicast, Special Multicast & Other + * Multicast) and set each entry to 0. + */ +static void port_init_mac_tables(struct mvgbe_registers *regs) +{ + int table_index; + + /* Clear DA filter unicast table (Ex_dFUT) */ + for (table_index = 0; table_index < 4; ++table_index) + MVGBE_REG_WR(regs->dfut[table_index], 0); + + for (table_index = 0; table_index < 64; ++table_index) { + /* Clear DA filter special multicast table (Ex_dFSMT) */ + MVGBE_REG_WR(regs->dfsmt[table_index], 0); + /* Clear DA filter other multicast table (Ex_dFOMT) */ + MVGBE_REG_WR(regs->dfomt[table_index], 0); + } +} + +/* + * port_uc_addr - This function Set the port unicast address table + * + * This function locates the proper entry in the Unicast table for the + * specified MAC nibble and sets its properties according to function + * parameters. + * This function add/removes MAC addresses from the port unicast address + * table. + * + * @uc_nibble Unicast MAC Address last nibble. + * @option 0 = Add, 1 = remove address. + * + * RETURN: 1 if output succeeded. 0 if option parameter is invalid. + */ +static int port_uc_addr(struct mvgbe_registers *regs, u8 uc_nibble, + int option) +{ + u32 unicast_reg; + u32 tbl_offset; + u32 reg_offset; + + /* Locate the Unicast table entry */ + uc_nibble = (0xf & uc_nibble); + /* Register offset from unicast table base */ + tbl_offset = (uc_nibble / 4); + /* Entry offset within the above register */ + reg_offset = uc_nibble % 4; + + switch (option) { + case REJECT_MAC_ADDR: + /* + * Clear accepts frame bit at specified unicast + * DA table entry + */ + unicast_reg = MVGBE_REG_RD(regs->dfut[tbl_offset]); + unicast_reg &= (0xFF << (8 * reg_offset)); + MVGBE_REG_WR(regs->dfut[tbl_offset], unicast_reg); + break; + case ACCEPT_MAC_ADDR: + /* Set accepts frame bit at unicast DA filter table entry */ + unicast_reg = MVGBE_REG_RD(regs->dfut[tbl_offset]); + unicast_reg &= (0xFF << (8 * reg_offset)); + unicast_reg |= ((0x01 | (RXUQ << 1)) << (8 * reg_offset)); + MVGBE_REG_WR(regs->dfut[tbl_offset], unicast_reg); + break; + default: + return 0; + } + return 1; +} + +/* + * port_uc_addr_set - This function Set the port Unicast address. + */ +static void port_uc_addr_set(struct mvgbe_registers *regs, u8 * p_addr) +{ + u32 mac_h; + u32 mac_l; + + mac_l = (p_addr[4] << 8) | (p_addr[5]); + mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) | + (p_addr[3] << 0); + + MVGBE_REG_WR(regs->macal, mac_l); + MVGBE_REG_WR(regs->macah, mac_h); + + /* Accept frames of this address */ + port_uc_addr(regs, p_addr[5], ACCEPT_MAC_ADDR); +} + +/* + * mvgbe_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory. + */ +static void mvgbe_init_rx_desc_ring(struct mvgbe_device *dmvgbe) +{ + struct mvgbe_rxdesc *p_rx_desc; + int i; + + /* initialize the Rx descriptors ring */ + p_rx_desc = dmvgbe->p_rxdesc; + for (i = 0; i < RINGSZ; i++) { + p_rx_desc->cmd_sts = + MVGBE_BUFFER_OWNED_BY_DMA | MVGBE_RX_EN_INTERRUPT; + p_rx_desc->buf_size = PKTSIZE_ALIGN; + p_rx_desc->byte_cnt = 0; + p_rx_desc->buf_ptr = dmvgbe->p_rxbuf + i * PKTSIZE_ALIGN; + if (i == (RINGSZ - 1)) + p_rx_desc->nxtdesc_p = dmvgbe->p_rxdesc; + else { + p_rx_desc->nxtdesc_p = (struct mvgbe_rxdesc *) + ((u32) p_rx_desc + MV_RXQ_DESC_ALIGNED_SIZE); + p_rx_desc = p_rx_desc->nxtdesc_p; + } + } + dmvgbe->p_rxdesc_curr = dmvgbe->p_rxdesc; +} + +static int mvgbe_init(struct eth_device *dev) +{ + struct mvgbe_device *dmvgbe = to_mvgbe(dev); + struct mvgbe_registers *regs = dmvgbe->regs; +#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) && \ + !defined(CONFIG_PHYLIB) && \ + defined(CONFIG_SYS_FAULT_ECHO_LINK_DOWN) + int i; +#endif + /* setup RX rings */ + mvgbe_init_rx_desc_ring(dmvgbe); + + /* Clear the ethernet port interrupts */ + MVGBE_REG_WR(regs->ic, 0); + MVGBE_REG_WR(regs->ice, 0); + /* Unmask RX buffer and TX end interrupt */ + MVGBE_REG_WR(regs->pim, INT_CAUSE_UNMASK_ALL); + /* Unmask phy and link status changes interrupts */ + MVGBE_REG_WR(regs->peim, INT_CAUSE_UNMASK_ALL_EXT); + + set_dram_access(regs); + port_init_mac_tables(regs); + port_uc_addr_set(regs, dmvgbe->dev.enetaddr); + + /* Assign port configuration and command. */ + MVGBE_REG_WR(regs->pxc, PRT_CFG_VAL); + MVGBE_REG_WR(regs->pxcx, PORT_CFG_EXTEND_VALUE); + MVGBE_REG_WR(regs->psc0, PORT_SERIAL_CONTROL_VALUE); + + /* Assign port SDMA configuration */ + MVGBE_REG_WR(regs->sdc, PORT_SDMA_CFG_VALUE); + MVGBE_REG_WR(regs->tqx[0].qxttbc, QTKNBKT_DEF_VAL); + MVGBE_REG_WR(regs->tqx[0].tqxtbc, + (QMTBS_DEF_VAL << 16) | QTKNRT_DEF_VAL); + /* Turn off the port/RXUQ bandwidth limitation */ + MVGBE_REG_WR(regs->pmtu, 0); + + /* Set maximum receive buffer to 9700 bytes */ + MVGBE_REG_WR(regs->psc0, MVGBE_MAX_RX_PACKET_9700BYTE + | (MVGBE_REG_RD(regs->psc0) & MRU_MASK)); + + /* Enable port initially */ + MVGBE_REG_BITS_SET(regs->psc0, MVGBE_SERIAL_PORT_EN); + + /* + * Set ethernet MTU for leaky bucket mechanism to 0 - this will + * disable the leaky bucket mechanism . + */ + MVGBE_REG_WR(regs->pmtu, 0); + + /* Assignment of Rx CRDB of given RXUQ */ + MVGBE_REG_WR(regs->rxcdp[RXUQ], (u32) dmvgbe->p_rxdesc_curr); + /* ensure previous write is done before enabling Rx DMA */ + isb(); + /* Enable port Rx. */ + MVGBE_REG_WR(regs->rqc, (1 << RXUQ)); + +#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) && \ + !defined(CONFIG_PHYLIB) && \ + defined(CONFIG_SYS_FAULT_ECHO_LINK_DOWN) + /* Wait up to 5s for the link status */ + for (i = 0; i < 5; i++) { + u16 phyadr; + + miiphy_read(dev->name, MV_PHY_ADR_REQUEST, + MV_PHY_ADR_REQUEST, &phyadr); + /* Return if we get link up */ + if (miiphy_link(dev->name, phyadr)) + return 0; + udelay(1000000); + } + + printf("No link on %s\n", dev->name); + return -1; +#endif + return 0; +} + +static int mvgbe_halt(struct eth_device *dev) +{ + struct mvgbe_device *dmvgbe = to_mvgbe(dev); + struct mvgbe_registers *regs = dmvgbe->regs; + + /* Disable all gigE address decoder */ + MVGBE_REG_WR(regs->bare, 0x3f); + + stop_queue(®s->tqc); + stop_queue(®s->rqc); + + /* Disable port */ + MVGBE_REG_BITS_RESET(regs->psc0, MVGBE_SERIAL_PORT_EN); + /* Set port is not reset */ + MVGBE_REG_BITS_RESET(regs->psc1, 1 << 4); +#ifdef CONFIG_SYS_MII_MODE + /* Set MMI interface up */ + MVGBE_REG_BITS_RESET(regs->psc1, 1 << 3); +#endif + /* Disable & mask ethernet port interrupts */ + MVGBE_REG_WR(regs->ic, 0); + MVGBE_REG_WR(regs->ice, 0); + MVGBE_REG_WR(regs->pim, 0); + MVGBE_REG_WR(regs->peim, 0); + + return 0; +} + +static int mvgbe_write_hwaddr(struct eth_device *dev) +{ + struct mvgbe_device *dmvgbe = to_mvgbe(dev); + struct mvgbe_registers *regs = dmvgbe->regs; + + /* Programs net device MAC address after initialization */ + port_uc_addr_set(regs, dmvgbe->dev.enetaddr); + return 0; +} + +static int mvgbe_send(struct eth_device *dev, void *dataptr, int datasize) +{ + struct mvgbe_device *dmvgbe = to_mvgbe(dev); + struct mvgbe_registers *regs = dmvgbe->regs; + struct mvgbe_txdesc *p_txdesc = dmvgbe->p_txdesc; + void *p = (void *)dataptr; + u32 cmd_sts; + u32 txuq0_reg_addr; + + /* Copy buffer if it's misaligned */ + if ((u32) dataptr & 0x07) { + if (datasize > PKTSIZE_ALIGN) { + printf("Non-aligned data too large (%d)\n", + datasize); + return -1; + } + + memcpy(dmvgbe->p_aligned_txbuf, p, datasize); + p = dmvgbe->p_aligned_txbuf; + } + + p_txdesc->cmd_sts = MVGBE_ZERO_PADDING | MVGBE_GEN_CRC; + p_txdesc->cmd_sts |= MVGBE_TX_FIRST_DESC | MVGBE_TX_LAST_DESC; + p_txdesc->cmd_sts |= MVGBE_BUFFER_OWNED_BY_DMA; + p_txdesc->cmd_sts |= MVGBE_TX_EN_INTERRUPT; + p_txdesc->buf_ptr = (u8 *) p; + p_txdesc->byte_cnt = datasize; + + /* Set this tc desc as zeroth TXUQ */ + txuq0_reg_addr = (u32)®s->tcqdp[TXUQ]; + writel((u32) p_txdesc, txuq0_reg_addr); + + /* ensure tx desc writes above are performed before we start Tx DMA */ + isb(); + + /* Apply send command using zeroth TXUQ */ + MVGBE_REG_WR(regs->tqc, (1 << TXUQ)); + + /* + * wait for packet xmit completion + */ + cmd_sts = readl(&p_txdesc->cmd_sts); + while (cmd_sts & MVGBE_BUFFER_OWNED_BY_DMA) { + /* return fail if error is detected */ + if ((cmd_sts & (MVGBE_ERROR_SUMMARY | MVGBE_TX_LAST_FRAME)) == + (MVGBE_ERROR_SUMMARY | MVGBE_TX_LAST_FRAME) && + cmd_sts & (MVGBE_UR_ERROR | MVGBE_RL_ERROR)) { + printf("Err..(%s) in xmit packet\n", __func__); + return -1; + } + cmd_sts = readl(&p_txdesc->cmd_sts); + }; + return 0; +} + +static int mvgbe_recv(struct eth_device *dev) +{ + struct mvgbe_device *dmvgbe = to_mvgbe(dev); + struct mvgbe_rxdesc *p_rxdesc_curr = dmvgbe->p_rxdesc_curr; + u32 cmd_sts; + u32 timeout = 0; + u32 rxdesc_curr_addr; + + /* wait untill rx packet available or timeout */ + do { + if (timeout < MVGBE_PHY_SMI_TIMEOUT) + timeout++; + else { + debug("%s time out...\n", __func__); + return -1; + } + } while (readl(&p_rxdesc_curr->cmd_sts) & MVGBE_BUFFER_OWNED_BY_DMA); + + if (p_rxdesc_curr->byte_cnt != 0) { + debug("%s: Received %d byte Packet @ 0x%x (cmd_sts= %08x)\n", + __func__, (u32) p_rxdesc_curr->byte_cnt, + (u32) p_rxdesc_curr->buf_ptr, + (u32) p_rxdesc_curr->cmd_sts); + } + + /* + * In case received a packet without first/last bits on + * OR the error summary bit is on, + * the packets needs to be dropeed. + */ + cmd_sts = readl(&p_rxdesc_curr->cmd_sts); + + if ((cmd_sts & + (MVGBE_RX_FIRST_DESC | MVGBE_RX_LAST_DESC)) + != (MVGBE_RX_FIRST_DESC | MVGBE_RX_LAST_DESC)) { + + printf("Err..(%s) Dropping packet spread on" + " multiple descriptors\n", __func__); + + } else if (cmd_sts & MVGBE_ERROR_SUMMARY) { + + printf("Err..(%s) Dropping packet with errors\n", + __func__); + + } else { + /* !!! call higher layer processing */ + debug("%s: Sending Received packet to" + " upper layer (net_process_received_packet)\n", + __func__); + + /* let the upper layer handle the packet */ + net_process_received_packet((p_rxdesc_curr->buf_ptr + + RX_BUF_OFFSET), + (int)(p_rxdesc_curr->byte_cnt - + RX_BUF_OFFSET)); + } + /* + * free these descriptors and point next in the ring + */ + p_rxdesc_curr->cmd_sts = + MVGBE_BUFFER_OWNED_BY_DMA | MVGBE_RX_EN_INTERRUPT; + p_rxdesc_curr->buf_size = PKTSIZE_ALIGN; + p_rxdesc_curr->byte_cnt = 0; + + rxdesc_curr_addr = (u32)&dmvgbe->p_rxdesc_curr; + writel((unsigned)p_rxdesc_curr->nxtdesc_p, rxdesc_curr_addr); + + return 0; +} + +#if defined(CONFIG_PHYLIB) +int mvgbe_phylib_init(struct eth_device *dev, int phyid) +{ + struct mii_dev *bus; + struct phy_device *phydev; + int ret; + + bus = mdio_alloc(); + if (!bus) { + printf("mdio_alloc failed\n"); + return -ENOMEM; + } + bus->read = mvgbe_phy_read; + bus->write = mvgbe_phy_write; + sprintf(bus->name, dev->name); + + ret = mdio_register(bus); + if (ret) { + printf("mdio_register failed\n"); + free(bus); + return -ENOMEM; + } + + /* Set phy address of the port */ + mvgbe_phy_write(bus, MV_PHY_ADR_REQUEST, 0, MV_PHY_ADR_REQUEST, phyid); + + phydev = phy_connect(bus, phyid, dev, PHY_INTERFACE_MODE_RGMII); + if (!phydev) { + printf("phy_connect failed\n"); + return -ENODEV; + } + + phy_config(phydev); + phy_startup(phydev); + + return 0; +} +#endif + +int mvgbe_initialize(bd_t *bis) +{ + struct mvgbe_device *dmvgbe; + struct eth_device *dev; + int devnum; + u8 used_ports[MAX_MVGBE_DEVS] = CONFIG_MVGBE_PORTS; + + for (devnum = 0; devnum < MAX_MVGBE_DEVS; devnum++) { + /*skip if port is configured not to use */ + if (used_ports[devnum] == 0) + continue; + + dmvgbe = malloc(sizeof(struct mvgbe_device)); + + if (!dmvgbe) + goto error1; + + memset(dmvgbe, 0, sizeof(struct mvgbe_device)); + + dmvgbe->p_rxdesc = + (struct mvgbe_rxdesc *)memalign(PKTALIGN, + MV_RXQ_DESC_ALIGNED_SIZE*RINGSZ + 1); + + if (!dmvgbe->p_rxdesc) + goto error2; + + dmvgbe->p_rxbuf = (u8 *) memalign(PKTALIGN, + RINGSZ*PKTSIZE_ALIGN + 1); + + if (!dmvgbe->p_rxbuf) + goto error3; + + dmvgbe->p_aligned_txbuf = memalign(8, PKTSIZE_ALIGN); + + if (!dmvgbe->p_aligned_txbuf) + goto error4; + + dmvgbe->p_txdesc = (struct mvgbe_txdesc *) memalign( + PKTALIGN, sizeof(struct mvgbe_txdesc) + 1); + + if (!dmvgbe->p_txdesc) { + free(dmvgbe->p_aligned_txbuf); +error4: + free(dmvgbe->p_rxbuf); +error3: + free(dmvgbe->p_rxdesc); +error2: + free(dmvgbe); +error1: + printf("Err.. %s Failed to allocate memory\n", + __func__); + return -1; + } + + dev = &dmvgbe->dev; + + /* must be less than sizeof(dev->name) */ + sprintf(dev->name, "egiga%d", devnum); + + switch (devnum) { + case 0: + dmvgbe->regs = (void *)MVGBE0_BASE; + break; +#if defined(MVGBE1_BASE) + case 1: + dmvgbe->regs = (void *)MVGBE1_BASE; + break; +#endif + default: /* this should never happen */ + printf("Err..(%s) Invalid device number %d\n", + __func__, devnum); + return -1; + } + + dev->init = (void *)mvgbe_init; + dev->halt = (void *)mvgbe_halt; + dev->send = (void *)mvgbe_send; + dev->recv = (void *)mvgbe_recv; + dev->write_hwaddr = (void *)mvgbe_write_hwaddr; + + eth_register(dev); + +#if defined(CONFIG_PHYLIB) + mvgbe_phylib_init(dev, PHY_BASE_ADR + devnum); +#elif defined(CONFIG_MII) || defined(CONFIG_CMD_MII) + miiphy_register(dev->name, smi_reg_read, smi_reg_write); + /* Set phy address of the port */ + miiphy_write(dev->name, MV_PHY_ADR_REQUEST, + MV_PHY_ADR_REQUEST, PHY_BASE_ADR + devnum); +#endif + } + return 0; +} diff --git a/sources/uboot-be550/drivers/net/mvgbe.h b/sources/uboot-be550/drivers/net/mvgbe.h new file mode 100644 index 00000000..27a3f41e --- /dev/null +++ b/sources/uboot-be550/drivers/net/mvgbe.h @@ -0,0 +1,498 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + * + * based on - Driver for MV64360X ethernet ports + * Copyright (C) 2002 rabeeh@galileo.co.il + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MVGBE_H__ +#define __MVGBE_H__ + +/* PHY_BASE_ADR is board specific and can be configured */ +#if defined (CONFIG_PHY_BASE_ADR) +#define PHY_BASE_ADR CONFIG_PHY_BASE_ADR +#else +#define PHY_BASE_ADR 0x08 /* default phy base addr */ +#endif + +/* Constants */ +#define INT_CAUSE_UNMASK_ALL 0x0007ffff +#define INT_CAUSE_UNMASK_ALL_EXT 0x0011ffff +#define MRU_MASK 0xfff1ffff +#define PHYADR_MASK 0x0000001f +#define PHYREG_MASK 0x0000001f +#define QTKNBKT_DEF_VAL 0x3fffffff +#define QMTBS_DEF_VAL 0x000003ff +#define QTKNRT_DEF_VAL 0x0000fcff +#define RXUQ 0 /* Used Rx queue */ +#define TXUQ 0 /* Used Rx queue */ + +#define to_mvgbe(_d) container_of(_d, struct mvgbe_device, dev) +#define MVGBE_REG_WR(adr, val) writel(val, &adr) +#define MVGBE_REG_RD(adr) readl(&adr) +#define MVGBE_REG_BITS_RESET(adr, val) writel(readl(&adr) & ~(val), &adr) +#define MVGBE_REG_BITS_SET(adr, val) writel(readl(&adr) | val, &adr) + +/* Default port configuration value */ +#define PRT_CFG_VAL ( \ + MVGBE_UCAST_MOD_NRML | \ + MVGBE_DFLT_RXQ(RXUQ) | \ + MVGBE_DFLT_RX_ARPQ(RXUQ) | \ + MVGBE_RX_BC_IF_NOT_IP_OR_ARP | \ + MVGBE_RX_BC_IF_IP | \ + MVGBE_RX_BC_IF_ARP | \ + MVGBE_CPTR_TCP_FRMS_DIS | \ + MVGBE_CPTR_UDP_FRMS_DIS | \ + MVGBE_DFLT_RX_TCPQ(RXUQ) | \ + MVGBE_DFLT_RX_UDPQ(RXUQ) | \ + MVGBE_DFLT_RX_BPDUQ(RXUQ)) + +/* Default port extend configuration value */ +#define PORT_CFG_EXTEND_VALUE \ + MVGBE_SPAN_BPDU_PACKETS_AS_NORMAL | \ + MVGBE_PARTITION_DIS | \ + MVGBE_TX_CRC_GENERATION_EN + +#define GT_MVGBE_IPG_INT_RX(value) ((value & 0x3fff) << 8) + +/* Default sdma control value */ +#define PORT_SDMA_CFG_VALUE ( \ + MVGBE_RX_BURST_SIZE_16_64BIT | \ + MVGBE_BLM_RX_NO_SWAP | \ + MVGBE_BLM_TX_NO_SWAP | \ + GT_MVGBE_IPG_INT_RX(RXUQ) | \ + MVGBE_TX_BURST_SIZE_16_64BIT) + +/* Default port serial control value */ +#ifndef PORT_SERIAL_CONTROL_VALUE +#define PORT_SERIAL_CONTROL_VALUE ( \ + MVGBE_FORCE_LINK_PASS | \ + MVGBE_DIS_AUTO_NEG_FOR_DUPLX | \ + MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \ + MVGBE_ADV_NO_FLOW_CTRL | \ + MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \ + MVGBE_FORCE_BP_MODE_NO_JAM | \ + (1 << 9) /* Reserved bit has to be 1 */ | \ + MVGBE_DO_NOT_FORCE_LINK_FAIL | \ + MVGBE_EN_AUTO_NEG_SPEED_GMII | \ + MVGBE_DTE_ADV_0 | \ + MVGBE_MIIPHY_MAC_MODE | \ + MVGBE_AUTO_NEG_NO_CHANGE | \ + MVGBE_MAX_RX_PACKET_1552BYTE | \ + MVGBE_CLR_EXT_LOOPBACK | \ + MVGBE_SET_FULL_DUPLEX_MODE | \ + MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX) +#endif + +/* Tx WRR confoguration macros */ +#define PORT_MAX_TRAN_UNIT 0x24 /* MTU register (default) 9KByte */ +#define PORT_MAX_TOKEN_BUCKET_SIZE 0x_FFFF /* PMTBS reg (default) */ +#define PORT_TOKEN_RATE 1023 /* PTTBRC reg (default) */ +/* MAC accepet/reject macros */ +#define ACCEPT_MAC_ADDR 0 +#define REJECT_MAC_ADDR 1 +/* Size of a Tx/Rx descriptor used in chain list data structure */ +#define MV_RXQ_DESC_ALIGNED_SIZE \ + (((sizeof(struct mvgbe_rxdesc) / PKTALIGN) + 1) * PKTALIGN) +/* Buffer offset from buffer pointer */ +#define RX_BUF_OFFSET 0x2 + +/* Port serial status reg (PSR) */ +#define MVGBE_INTERFACE_GMII_MII 0 +#define MVGBE_INTERFACE_PCM 1 +#define MVGBE_LINK_IS_DOWN 0 +#define MVGBE_LINK_IS_UP (1 << 1) +#define MVGBE_PORT_AT_HALF_DUPLEX 0 +#define MVGBE_PORT_AT_FULL_DUPLEX (1 << 2) +#define MVGBE_RX_FLOW_CTRL_DISD 0 +#define MVGBE_RX_FLOW_CTRL_ENBALED (1 << 3) +#define MVGBE_GMII_SPEED_100_10 0 +#define MVGBE_GMII_SPEED_1000 (1 << 4) +#define MVGBE_MII_SPEED_10 0 +#define MVGBE_MII_SPEED_100 (1 << 5) +#define MVGBE_NO_TX 0 +#define MVGBE_TX_IN_PROGRESS (1 << 7) +#define MVGBE_BYPASS_NO_ACTIVE 0 +#define MVGBE_BYPASS_ACTIVE (1 << 8) +#define MVGBE_PORT_NOT_AT_PARTN_STT 0 +#define MVGBE_PORT_AT_PARTN_STT (1 << 9) +#define MVGBE_PORT_TX_FIFO_NOT_EMPTY 0 +#define MVGBE_PORT_TX_FIFO_EMPTY (1 << 10) + +/* These macros describes the Port configuration reg (Px_cR) bits */ +#define MVGBE_UCAST_MOD_NRML 0 +#define MVGBE_UNICAST_PROMISCUOUS_MODE 1 +#define MVGBE_DFLT_RXQ(_x) (_x << 1) +#define MVGBE_DFLT_RX_ARPQ(_x) (_x << 4) +#define MVGBE_RX_BC_IF_NOT_IP_OR_ARP 0 +#define MVGBE_REJECT_BC_IF_NOT_IP_OR_ARP (1 << 7) +#define MVGBE_RX_BC_IF_IP 0 +#define MVGBE_REJECT_BC_IF_IP (1 << 8) +#define MVGBE_RX_BC_IF_ARP 0 +#define MVGBE_REJECT_BC_IF_ARP (1 << 9) +#define MVGBE_TX_AM_NO_UPDATE_ERR_SMRY (1 << 12) +#define MVGBE_CPTR_TCP_FRMS_DIS 0 +#define MVGBE_CPTR_TCP_FRMS_EN (1 << 14) +#define MVGBE_CPTR_UDP_FRMS_DIS 0 +#define MVGBE_CPTR_UDP_FRMS_EN (1 << 15) +#define MVGBE_DFLT_RX_TCPQ(_x) (_x << 16) +#define MVGBE_DFLT_RX_UDPQ(_x) (_x << 19) +#define MVGBE_DFLT_RX_BPDUQ(_x) (_x << 22) +#define MVGBE_DFLT_RX_TCP_CHKSUM_MODE (1 << 25) + +/* These macros describes the Port configuration extend reg (Px_cXR) bits*/ +#define MVGBE_CLASSIFY_EN 1 +#define MVGBE_SPAN_BPDU_PACKETS_AS_NORMAL 0 +#define MVGBE_SPAN_BPDU_PACKETS_TO_RX_Q7 (1 << 1) +#define MVGBE_PARTITION_DIS 0 +#define MVGBE_PARTITION_EN (1 << 2) +#define MVGBE_TX_CRC_GENERATION_EN 0 +#define MVGBE_TX_CRC_GENERATION_DIS (1 << 3) + +/* These macros describes the Port Sdma configuration reg (SDCR) bits */ +#define MVGBE_RIFB 1 +#define MVGBE_RX_BURST_SIZE_1_64BIT 0 +#define MVGBE_RX_BURST_SIZE_2_64BIT (1 << 1) +#define MVGBE_RX_BURST_SIZE_4_64BIT (1 << 2) +#define MVGBE_RX_BURST_SIZE_8_64BIT ((1 << 2) | (1 << 1)) +#define MVGBE_RX_BURST_SIZE_16_64BIT (1 << 3) +#define MVGBE_BLM_RX_NO_SWAP (1 << 4) +#define MVGBE_BLM_RX_BYTE_SWAP 0 +#define MVGBE_BLM_TX_NO_SWAP (1 << 5) +#define MVGBE_BLM_TX_BYTE_SWAP 0 +#define MVGBE_DESCRIPTORS_BYTE_SWAP (1 << 6) +#define MVGBE_DESCRIPTORS_NO_SWAP 0 +#define MVGBE_TX_BURST_SIZE_1_64BIT 0 +#define MVGBE_TX_BURST_SIZE_2_64BIT (1 << 22) +#define MVGBE_TX_BURST_SIZE_4_64BIT (1 << 23) +#define MVGBE_TX_BURST_SIZE_8_64BIT ((1 << 23) | (1 << 22)) +#define MVGBE_TX_BURST_SIZE_16_64BIT (1 << 24) + +/* These macros describes the Port serial control reg (PSCR) bits */ +#define MVGBE_SERIAL_PORT_DIS 0 +#define MVGBE_SERIAL_PORT_EN 1 +#define MVGBE_FORCE_LINK_PASS (1 << 1) +#define MVGBE_DO_NOT_FORCE_LINK_PASS 0 +#define MVGBE_EN_AUTO_NEG_FOR_DUPLX 0 +#define MVGBE_DIS_AUTO_NEG_FOR_DUPLX (1 << 2) +#define MVGBE_EN_AUTO_NEG_FOR_FLOW_CTRL 0 +#define MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL (1 << 3) +#define MVGBE_ADV_NO_FLOW_CTRL 0 +#define MVGBE_ADV_SYMMETRIC_FLOW_CTRL (1 << 4) +#define MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0 +#define MVGBE_FORCE_FC_MODE_TX_PAUSE_DIS (1 << 5) +#define MVGBE_FORCE_BP_MODE_NO_JAM 0 +#define MVGBE_FORCE_BP_MODE_JAM_TX (1 << 7) +#define MVGBE_FORCE_BP_MODE_JAM_TX_ON_RX_ERR (1 << 8) +#define MVGBE_FORCE_LINK_FAIL 0 +#define MVGBE_DO_NOT_FORCE_LINK_FAIL (1 << 10) +#define MVGBE_DIS_AUTO_NEG_SPEED_GMII (1 << 13) +#define MVGBE_EN_AUTO_NEG_SPEED_GMII 0 +#define MVGBE_DTE_ADV_0 0 +#define MVGBE_DTE_ADV_1 (1 << 14) +#define MVGBE_MIIPHY_MAC_MODE 0 +#define MVGBE_MIIPHY_PHY_MODE (1 << 15) +#define MVGBE_AUTO_NEG_NO_CHANGE 0 +#define MVGBE_RESTART_AUTO_NEG (1 << 16) +#define MVGBE_MAX_RX_PACKET_1518BYTE 0 +#define MVGBE_MAX_RX_PACKET_1522BYTE (1 << 17) +#define MVGBE_MAX_RX_PACKET_1552BYTE (1 << 18) +#define MVGBE_MAX_RX_PACKET_9022BYTE ((1 << 18) | (1 << 17)) +#define MVGBE_MAX_RX_PACKET_9192BYTE (1 << 19) +#define MVGBE_MAX_RX_PACKET_9700BYTE ((1 << 19) | (1 << 17)) +#define MVGBE_SET_EXT_LOOPBACK (1 << 20) +#define MVGBE_CLR_EXT_LOOPBACK 0 +#define MVGBE_SET_FULL_DUPLEX_MODE (1 << 21) +#define MVGBE_SET_HALF_DUPLEX_MODE 0 +#define MVGBE_EN_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (1 << 22) +#define MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0 +#define MVGBE_SET_GMII_SPEED_TO_10_100 0 +#define MVGBE_SET_GMII_SPEED_TO_1000 (1 << 23) +#define MVGBE_SET_MII_SPEED_TO_10 0 +#define MVGBE_SET_MII_SPEED_TO_100 (1 << 24) + +/* SMI register fields */ +#define MVGBE_PHY_SMI_TIMEOUT 10000 +#define MVGBE_PHY_SMI_DATA_OFFS 0 /* Data */ +#define MVGBE_PHY_SMI_DATA_MASK (0xffff << MVGBE_PHY_SMI_DATA_OFFS) +#define MVGBE_PHY_SMI_DEV_ADDR_OFFS 16 /* PHY device address */ +#define MVGBE_PHY_SMI_DEV_ADDR_MASK \ + (PHYADR_MASK << MVGBE_PHY_SMI_DEV_ADDR_OFFS) +#define MVGBE_SMI_REG_ADDR_OFFS 21 /* PHY device reg addr */ +#define MVGBE_SMI_REG_ADDR_MASK \ + (PHYADR_MASK << MVGBE_SMI_REG_ADDR_OFFS) +#define MVGBE_PHY_SMI_OPCODE_OFFS 26 /* Write/Read opcode */ +#define MVGBE_PHY_SMI_OPCODE_MASK (3 << MVGBE_PHY_SMI_OPCODE_OFFS) +#define MVGBE_PHY_SMI_OPCODE_WRITE (0 << MVGBE_PHY_SMI_OPCODE_OFFS) +#define MVGBE_PHY_SMI_OPCODE_READ (1 << MVGBE_PHY_SMI_OPCODE_OFFS) +#define MVGBE_PHY_SMI_READ_VALID_MASK (1 << 27) /* Read Valid */ +#define MVGBE_PHY_SMI_BUSY_MASK (1 << 28) /* Busy */ + +/* SDMA command status fields macros */ +/* Tx & Rx descriptors status */ +#define MVGBE_ERROR_SUMMARY 1 +/* Tx & Rx descriptors command */ +#define MVGBE_BUFFER_OWNED_BY_DMA (1 << 31) +/* Tx descriptors status */ +#define MVGBE_LC_ERROR 0 +#define MVGBE_UR_ERROR (1 << 1) +#define MVGBE_RL_ERROR (1 << 2) +#define MVGBE_LLC_SNAP_FORMAT (1 << 9) +#define MVGBE_TX_LAST_FRAME (1 << 20) + +/* Rx descriptors status */ +#define MVGBE_CRC_ERROR 0 +#define MVGBE_OVERRUN_ERROR (1 << 1) +#define MVGBE_MAX_FRAME_LENGTH_ERROR (1 << 2) +#define MVGBE_RESOURCE_ERROR ((1 << 2) | (1 << 1)) +#define MVGBE_VLAN_TAGGED (1 << 19) +#define MVGBE_BPDU_FRAME (1 << 20) +#define MVGBE_TCP_FRAME_OVER_IP_V_4 0 +#define MVGBE_UDP_FRAME_OVER_IP_V_4 (1 << 21) +#define MVGBE_OTHER_FRAME_TYPE (1 << 22) +#define MVGBE_LAYER_2_IS_MVGBE_V_2 (1 << 23) +#define MVGBE_FRAME_TYPE_IP_V_4 (1 << 24) +#define MVGBE_FRAME_HEADER_OK (1 << 25) +#define MVGBE_RX_LAST_DESC (1 << 26) +#define MVGBE_RX_FIRST_DESC (1 << 27) +#define MVGBE_UNKNOWN_DESTINATION_ADDR (1 << 28) +#define MVGBE_RX_EN_INTERRUPT (1 << 29) +#define MVGBE_LAYER_4_CHECKSUM_OK (1 << 30) + +/* Rx descriptors byte count */ +#define MVGBE_FRAME_FRAGMENTED (1 << 2) + +/* Tx descriptors command */ +#define MVGBE_LAYER_4_CHECKSUM_FIRST_DESC (1 << 10) +#define MVGBE_FRAME_SET_TO_VLAN (1 << 15) +#define MVGBE_TCP_FRAME 0 +#define MVGBE_UDP_FRAME (1 << 16) +#define MVGBE_GEN_TCP_UDP_CHECKSUM (1 << 17) +#define MVGBE_GEN_IP_V_4_CHECKSUM (1 << 18) +#define MVGBE_ZERO_PADDING (1 << 19) +#define MVGBE_TX_LAST_DESC (1 << 20) +#define MVGBE_TX_FIRST_DESC (1 << 21) +#define MVGBE_GEN_CRC (1 << 22) +#define MVGBE_TX_EN_INTERRUPT (1 << 23) +#define MVGBE_AUTO_MODE (1 << 30) + +/* Address decode parameters */ +/* Ethernet Base Address Register bits */ +#define EBAR_TARGET_DRAM 0x00000000 +#define EBAR_TARGET_DEVICE 0x00000001 +#define EBAR_TARGET_CBS 0x00000002 +#define EBAR_TARGET_PCI0 0x00000003 +#define EBAR_TARGET_PCI1 0x00000004 +#define EBAR_TARGET_CUNIT 0x00000005 +#define EBAR_TARGET_AUNIT 0x00000006 +#define EBAR_TARGET_GUNIT 0x00000007 + +/* Window attrib */ +#if defined(CONFIG_DOVE) +#define EBAR_DRAM_CS0 0x00000000 +#define EBAR_DRAM_CS1 0x00000000 +#define EBAR_DRAM_CS2 0x00000000 +#define EBAR_DRAM_CS3 0x00000000 +#else +#define EBAR_DRAM_CS0 0x00000E00 +#define EBAR_DRAM_CS1 0x00000D00 +#define EBAR_DRAM_CS2 0x00000B00 +#define EBAR_DRAM_CS3 0x00000700 +#endif + +/* DRAM Target interface */ +#define EBAR_DRAM_NO_CACHE_COHERENCY 0x00000000 +#define EBAR_DRAM_CACHE_COHERENCY_WT 0x00001000 +#define EBAR_DRAM_CACHE_COHERENCY_WB 0x00002000 + +/* Device Bus Target interface */ +#define EBAR_DEVICE_DEVCS0 0x00001E00 +#define EBAR_DEVICE_DEVCS1 0x00001D00 +#define EBAR_DEVICE_DEVCS2 0x00001B00 +#define EBAR_DEVICE_DEVCS3 0x00001700 +#define EBAR_DEVICE_BOOTCS3 0x00000F00 + +/* PCI Target interface */ +#define EBAR_PCI_BYTE_SWAP 0x00000000 +#define EBAR_PCI_NO_SWAP 0x00000100 +#define EBAR_PCI_BYTE_WORD_SWAP 0x00000200 +#define EBAR_PCI_WORD_SWAP 0x00000300 +#define EBAR_PCI_NO_SNOOP_NOT_ASSERT 0x00000000 +#define EBAR_PCI_NO_SNOOP_ASSERT 0x00000400 +#define EBAR_PCI_IO_SPACE 0x00000000 +#define EBAR_PCI_MEMORY_SPACE 0x00000800 +#define EBAR_PCI_REQ64_FORCE 0x00000000 +#define EBAR_PCI_REQ64_SIZE 0x00001000 + +/* Window access control */ +#define EWIN_ACCESS_NOT_ALLOWED 0 +#define EWIN_ACCESS_READ_ONLY 1 +#define EWIN_ACCESS_FULL ((1 << 1) | 1) + +/* structures represents Controller registers */ +struct mvgbe_barsz { + u32 bar; + u32 size; +}; + +struct mvgbe_rxcdp { + struct mvgbe_rxdesc *rxcdp; + u32 rxcdp_pad[3]; +}; + +struct mvgbe_tqx { + u32 qxttbc; + u32 tqxtbc; + u32 tqxac; + u32 tqxpad; +}; + +struct mvgbe_registers { + u32 phyadr; + u32 smi; + u32 euda; + u32 eudid; + u8 pad1[0x080 - 0x00c - 4]; + u32 euic; + u32 euim; + u8 pad2[0x094 - 0x084 - 4]; + u32 euea; + u32 euiae; + u8 pad3[0x0b0 - 0x098 - 4]; + u32 euc; + u8 pad3a[0x200 - 0x0b0 - 4]; + struct mvgbe_barsz barsz[6]; + u8 pad4[0x280 - 0x22c - 4]; + u32 ha_remap[4]; + u32 bare; + u32 epap; + u8 pad5[0x400 - 0x294 - 4]; + u32 pxc; + u32 pxcx; + u32 mii_ser_params; + u8 pad6[0x410 - 0x408 - 4]; + u32 evlane; + u32 macal; + u32 macah; + u32 sdc; + u32 dscp[7]; + u32 psc0; + u32 vpt2p; + u32 ps0; + u32 tqc; + u32 psc1; + u32 ps1; + u32 mrvl_header; + u8 pad7[0x460 - 0x454 - 4]; + u32 ic; + u32 ice; + u32 pim; + u32 peim; + u8 pad8[0x474 - 0x46c - 4]; + u32 pxtfut; + u32 pad9; + u32 pxmfs; + u32 pad10; + u32 pxdfc; + u32 pxofc; + u8 pad11[0x494 - 0x488 - 4]; + u32 peuiae; + u8 pad12[0x4bc - 0x494 - 4]; + u32 eth_type_prio; + u8 pad13[0x4dc - 0x4bc - 4]; + u32 tqfpc; + u32 pttbrc; + u32 tqc1; + u32 pmtu; + u32 pmtbs; + u8 pad14[0x60c - 0x4ec - 4]; + struct mvgbe_rxcdp rxcdp[7]; + struct mvgbe_rxdesc *rxcdp7; + u32 rqc; + struct mvgbe_txdesc *tcsdp; + u8 pad15[0x6c0 - 0x684 - 4]; + struct mvgbe_txdesc *tcqdp[8]; + u8 pad16[0x700 - 0x6dc - 4]; + struct mvgbe_tqx tqx[8]; + u32 pttbc; + u8 pad17[0x7a8 - 0x780 - 4]; + u32 tqxipg0; + u32 pad18[3]; + u32 tqxipg1; + u8 pad19[0x7c0 - 0x7b8 - 4]; + u32 hitkninlopkt; + u32 hitkninasyncpkt; + u32 lotkninasyncpkt; + u32 pad20; + u32 ts; + u8 pad21[0x3000 - 0x27d0 - 4]; + u32 pad20_1[32]; /* mib counter registes */ + u8 pad22[0x3400 - 0x3000 - sizeof(u32) * 32]; + u32 dfsmt[64]; + u32 dfomt[64]; + u32 dfut[4]; + u8 pad23[0xe20c0 - 0x7360c - 4]; + u32 pmbus_top_arbiter; +}; + +/* structures/enums needed by driver */ +enum mvgbe_adrwin { + MVGBE_WIN0, + MVGBE_WIN1, + MVGBE_WIN2, + MVGBE_WIN3, + MVGBE_WIN4, + MVGBE_WIN5 +}; + +enum mvgbe_target { + MVGBE_TARGET_DRAM, + MVGBE_TARGET_DEV, + MVGBE_TARGET_CBS, + MVGBE_TARGET_PCI0, + MVGBE_TARGET_PCI1 +}; + +struct mvgbe_winparam { + enum mvgbe_adrwin win; /* Window number */ + enum mvgbe_target target; /* System targets */ + u16 attrib; /* BAR attrib. See above macros */ + u32 base_addr; /* Window base address in u32 form */ + u32 high_addr; /* Window high address in u32 form */ + u32 size; /* Size in MBytes. Must be % 64Kbyte. */ + int enable; /* Enable/disable access to the window. */ + u16 access_ctrl; /*Access ctrl register. see above macros */ +}; + +struct mvgbe_rxdesc { + u32 cmd_sts; /* Descriptor command status */ + u16 buf_size; /* Buffer size */ + u16 byte_cnt; /* Descriptor buffer byte count */ + u8 *buf_ptr; /* Descriptor buffer pointer */ + struct mvgbe_rxdesc *nxtdesc_p; /* Next descriptor pointer */ +}; + +struct mvgbe_txdesc { + u32 cmd_sts; /* Descriptor command status */ + u16 l4i_chk; /* CPU provided TCP Checksum */ + u16 byte_cnt; /* Descriptor buffer byte count */ + u8 *buf_ptr; /* Descriptor buffer ptr */ + struct mvgbe_txdesc *nxtdesc_p; /* Next descriptor ptr */ +}; + +/* port device data struct */ +struct mvgbe_device { + struct eth_device dev; + struct mvgbe_registers *regs; + struct mvgbe_txdesc *p_txdesc; + struct mvgbe_rxdesc *p_rxdesc; + struct mvgbe_rxdesc *p_rxdesc_curr; + u8 *p_rxbuf; + u8 *p_aligned_txbuf; +}; + +#endif /* __MVGBE_H__ */ diff --git a/sources/uboot-be550/drivers/net/mvneta.c b/sources/uboot-be550/drivers/net/mvneta.c new file mode 100644 index 00000000..38ad14ef --- /dev/null +++ b/sources/uboot-be550/drivers/net/mvneta.c @@ -0,0 +1,1652 @@ +/* + * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs. + * + * U-Boot version: + * Copyright (C) 2014 Stefan Roese + * + * Based on the Linux version which is: + * Copyright (C) 2012 Marvell + * + * Rami Rosen + * Thomas Petazzoni + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#if !defined(CONFIG_PHYLIB) +# error Marvell mvneta requires PHYLIB +#endif + +/* Some linux -> U-Boot compatibility stuff */ +#define netdev_err(dev, fmt, args...) \ + printf(fmt, ##args) +#define netdev_warn(dev, fmt, args...) \ + printf(fmt, ##args) +#define netdev_info(dev, fmt, args...) \ + printf(fmt, ##args) + +#define CONFIG_NR_CPUS 1 +#define ETH_HLEN 14 /* Total octets in header */ + +/* 2(HW hdr) 14(MAC hdr) 4(CRC) 32(extra for cache prefetch) */ +#define WRAP (2 + ETH_HLEN + 4 + 32) +#define MTU 1500 +#define RX_BUFFER_SIZE (ALIGN(MTU + WRAP, ARCH_DMA_MINALIGN)) + +#define MVNETA_SMI_TIMEOUT 10000 + +/* Registers */ +#define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2)) +#define MVNETA_RXQ_HW_BUF_ALLOC BIT(1) +#define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8) +#define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8) +#define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2)) +#define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16) +#define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2)) +#define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2)) +#define MVNETA_RXQ_BUF_SIZE_SHIFT 19 +#define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19) +#define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2)) +#define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff +#define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2)) +#define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16 +#define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255 +#define MVNETA_PORT_RX_RESET 0x1cc0 +#define MVNETA_PORT_RX_DMA_RESET BIT(0) +#define MVNETA_PHY_ADDR 0x2000 +#define MVNETA_PHY_ADDR_MASK 0x1f +#define MVNETA_SMI 0x2004 +#define MVNETA_PHY_REG_MASK 0x1f +/* SMI register fields */ +#define MVNETA_SMI_DATA_OFFS 0 /* Data */ +#define MVNETA_SMI_DATA_MASK (0xffff << MVNETA_SMI_DATA_OFFS) +#define MVNETA_SMI_DEV_ADDR_OFFS 16 /* PHY device address */ +#define MVNETA_SMI_REG_ADDR_OFFS 21 /* PHY device reg addr*/ +#define MVNETA_SMI_OPCODE_OFFS 26 /* Write/Read opcode */ +#define MVNETA_SMI_OPCODE_READ (1 << MVNETA_SMI_OPCODE_OFFS) +#define MVNETA_SMI_READ_VALID (1 << 27) /* Read Valid */ +#define MVNETA_SMI_BUSY (1 << 28) /* Busy */ +#define MVNETA_MBUS_RETRY 0x2010 +#define MVNETA_UNIT_INTR_CAUSE 0x2080 +#define MVNETA_UNIT_CONTROL 0x20B0 +#define MVNETA_PHY_POLLING_ENABLE BIT(1) +#define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3)) +#define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3)) +#define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2)) +#define MVNETA_BASE_ADDR_ENABLE 0x2290 +#define MVNETA_PORT_CONFIG 0x2400 +#define MVNETA_UNI_PROMISC_MODE BIT(0) +#define MVNETA_DEF_RXQ(q) ((q) << 1) +#define MVNETA_DEF_RXQ_ARP(q) ((q) << 4) +#define MVNETA_TX_UNSET_ERR_SUM BIT(12) +#define MVNETA_DEF_RXQ_TCP(q) ((q) << 16) +#define MVNETA_DEF_RXQ_UDP(q) ((q) << 19) +#define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22) +#define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25) +#define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \ + MVNETA_DEF_RXQ_ARP(q) | \ + MVNETA_DEF_RXQ_TCP(q) | \ + MVNETA_DEF_RXQ_UDP(q) | \ + MVNETA_DEF_RXQ_BPDU(q) | \ + MVNETA_TX_UNSET_ERR_SUM | \ + MVNETA_RX_CSUM_WITH_PSEUDO_HDR) +#define MVNETA_PORT_CONFIG_EXTEND 0x2404 +#define MVNETA_MAC_ADDR_LOW 0x2414 +#define MVNETA_MAC_ADDR_HIGH 0x2418 +#define MVNETA_SDMA_CONFIG 0x241c +#define MVNETA_SDMA_BRST_SIZE_16 4 +#define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1) +#define MVNETA_RX_NO_DATA_SWAP BIT(4) +#define MVNETA_TX_NO_DATA_SWAP BIT(5) +#define MVNETA_DESC_SWAP BIT(6) +#define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22) +#define MVNETA_PORT_STATUS 0x2444 +#define MVNETA_TX_IN_PRGRS BIT(1) +#define MVNETA_TX_FIFO_EMPTY BIT(8) +#define MVNETA_RX_MIN_FRAME_SIZE 0x247c +#define MVNETA_SERDES_CFG 0x24A0 +#define MVNETA_SGMII_SERDES_PROTO 0x0cc7 +#define MVNETA_QSGMII_SERDES_PROTO 0x0667 +#define MVNETA_TYPE_PRIO 0x24bc +#define MVNETA_FORCE_UNI BIT(21) +#define MVNETA_TXQ_CMD_1 0x24e4 +#define MVNETA_TXQ_CMD 0x2448 +#define MVNETA_TXQ_DISABLE_SHIFT 8 +#define MVNETA_TXQ_ENABLE_MASK 0x000000ff +#define MVNETA_ACC_MODE 0x2500 +#define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2)) +#define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff +#define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00 +#define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2)) + +/* Exception Interrupt Port/Queue Cause register */ + +#define MVNETA_INTR_NEW_CAUSE 0x25a0 +#define MVNETA_INTR_NEW_MASK 0x25a4 + +/* bits 0..7 = TXQ SENT, one bit per queue. + * bits 8..15 = RXQ OCCUP, one bit per queue. + * bits 16..23 = RXQ FREE, one bit per queue. + * bit 29 = OLD_REG_SUM, see old reg ? + * bit 30 = TX_ERR_SUM, one bit for 4 ports + * bit 31 = MISC_SUM, one bit for 4 ports + */ +#define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0) +#define MVNETA_TX_INTR_MASK_ALL (0xff << 0) +#define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8) +#define MVNETA_RX_INTR_MASK_ALL (0xff << 8) + +#define MVNETA_INTR_OLD_CAUSE 0x25a8 +#define MVNETA_INTR_OLD_MASK 0x25ac + +/* Data Path Port/Queue Cause Register */ +#define MVNETA_INTR_MISC_CAUSE 0x25b0 +#define MVNETA_INTR_MISC_MASK 0x25b4 +#define MVNETA_INTR_ENABLE 0x25b8 + +#define MVNETA_RXQ_CMD 0x2680 +#define MVNETA_RXQ_DISABLE_SHIFT 8 +#define MVNETA_RXQ_ENABLE_MASK 0x000000ff +#define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4)) +#define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4)) +#define MVNETA_GMAC_CTRL_0 0x2c00 +#define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2 +#define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc +#define MVNETA_GMAC0_PORT_ENABLE BIT(0) +#define MVNETA_GMAC_CTRL_2 0x2c08 +#define MVNETA_GMAC2_PCS_ENABLE BIT(3) +#define MVNETA_GMAC2_PORT_RGMII BIT(4) +#define MVNETA_GMAC2_PORT_RESET BIT(6) +#define MVNETA_GMAC_STATUS 0x2c10 +#define MVNETA_GMAC_LINK_UP BIT(0) +#define MVNETA_GMAC_SPEED_1000 BIT(1) +#define MVNETA_GMAC_SPEED_100 BIT(2) +#define MVNETA_GMAC_FULL_DUPLEX BIT(3) +#define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4) +#define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5) +#define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6) +#define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7) +#define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c +#define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0) +#define MVNETA_GMAC_FORCE_LINK_PASS BIT(1) +#define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5) +#define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6) +#define MVNETA_GMAC_AN_SPEED_EN BIT(7) +#define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12) +#define MVNETA_GMAC_AN_DUPLEX_EN BIT(13) +#define MVNETA_MIB_COUNTERS_BASE 0x3080 +#define MVNETA_MIB_LATE_COLLISION 0x7c +#define MVNETA_DA_FILT_SPEC_MCAST 0x3400 +#define MVNETA_DA_FILT_OTH_MCAST 0x3500 +#define MVNETA_DA_FILT_UCAST_BASE 0x3600 +#define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2)) +#define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2)) +#define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000 +#define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16) +#define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2)) +#define MVNETA_TXQ_DEC_SENT_SHIFT 16 +#define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2)) +#define MVNETA_TXQ_SENT_DESC_SHIFT 16 +#define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000 +#define MVNETA_PORT_TX_RESET 0x3cf0 +#define MVNETA_PORT_TX_DMA_RESET BIT(0) +#define MVNETA_TX_MTU 0x3e0c +#define MVNETA_TX_TOKEN_SIZE 0x3e14 +#define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff +#define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2)) +#define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff + +/* Descriptor ring Macros */ +#define MVNETA_QUEUE_NEXT_DESC(q, index) \ + (((index) < (q)->last_desc) ? ((index) + 1) : 0) + +/* Various constants */ + +/* Coalescing */ +#define MVNETA_TXDONE_COAL_PKTS 16 +#define MVNETA_RX_COAL_PKTS 32 +#define MVNETA_RX_COAL_USEC 100 + +/* The two bytes Marvell header. Either contains a special value used + * by Marvell switches when a specific hardware mode is enabled (not + * supported by this driver) or is filled automatically by zeroes on + * the RX side. Those two bytes being at the front of the Ethernet + * header, they allow to have the IP header aligned on a 4 bytes + * boundary automatically: the hardware skips those two bytes on its + * own. + */ +#define MVNETA_MH_SIZE 2 + +#define MVNETA_VLAN_TAG_LEN 4 + +#define MVNETA_CPU_D_CACHE_LINE_SIZE 32 +#define MVNETA_TX_CSUM_MAX_SIZE 9800 +#define MVNETA_ACC_MODE_EXT 1 + +/* Timeout constants */ +#define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000 +#define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000 +#define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000 + +#define MVNETA_TX_MTU_MAX 0x3ffff + +/* Max number of Rx descriptors */ +#define MVNETA_MAX_RXD 16 + +/* Max number of Tx descriptors */ +#define MVNETA_MAX_TXD 16 + +/* descriptor aligned size */ +#define MVNETA_DESC_ALIGNED_SIZE 32 + +struct mvneta_port { + void __iomem *base; + struct mvneta_rx_queue *rxqs; + struct mvneta_tx_queue *txqs; + + u8 mcast_count[256]; + u16 tx_ring_size; + u16 rx_ring_size; + + phy_interface_t phy_interface; + unsigned int link; + unsigned int duplex; + unsigned int speed; + + int init; + int phyaddr; + struct phy_device *phydev; + struct mii_dev *bus; +}; + +/* The mvneta_tx_desc and mvneta_rx_desc structures describe the + * layout of the transmit and reception DMA descriptors, and their + * layout is therefore defined by the hardware design + */ + +#define MVNETA_TX_L3_OFF_SHIFT 0 +#define MVNETA_TX_IP_HLEN_SHIFT 8 +#define MVNETA_TX_L4_UDP BIT(16) +#define MVNETA_TX_L3_IP6 BIT(17) +#define MVNETA_TXD_IP_CSUM BIT(18) +#define MVNETA_TXD_Z_PAD BIT(19) +#define MVNETA_TXD_L_DESC BIT(20) +#define MVNETA_TXD_F_DESC BIT(21) +#define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \ + MVNETA_TXD_L_DESC | \ + MVNETA_TXD_F_DESC) +#define MVNETA_TX_L4_CSUM_FULL BIT(30) +#define MVNETA_TX_L4_CSUM_NOT BIT(31) + +#define MVNETA_RXD_ERR_CRC 0x0 +#define MVNETA_RXD_ERR_SUMMARY BIT(16) +#define MVNETA_RXD_ERR_OVERRUN BIT(17) +#define MVNETA_RXD_ERR_LEN BIT(18) +#define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18)) +#define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18)) +#define MVNETA_RXD_L3_IP4 BIT(25) +#define MVNETA_RXD_FIRST_LAST_DESC (BIT(26) | BIT(27)) +#define MVNETA_RXD_L4_CSUM_OK BIT(30) + +struct mvneta_tx_desc { + u32 command; /* Options used by HW for packet transmitting.*/ + u16 reserverd1; /* csum_l4 (for future use) */ + u16 data_size; /* Data size of transmitted packet in bytes */ + u32 buf_phys_addr; /* Physical addr of transmitted buffer */ + u32 reserved2; /* hw_cmd - (for future use, PMT) */ + u32 reserved3[4]; /* Reserved - (for future use) */ +}; + +struct mvneta_rx_desc { + u32 status; /* Info about received packet */ + u16 reserved1; /* pnc_info - (for future use, PnC) */ + u16 data_size; /* Size of received packet in bytes */ + + u32 buf_phys_addr; /* Physical address of the buffer */ + u32 reserved2; /* pnc_flow_id (for future use, PnC) */ + + u32 buf_cookie; /* cookie for access to RX buffer in rx path */ + u16 reserved3; /* prefetch_cmd, for future use */ + u16 reserved4; /* csum_l4 - (for future use, PnC) */ + + u32 reserved5; /* pnc_extra PnC (for future use, PnC) */ + u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */ +}; + +struct mvneta_tx_queue { + /* Number of this TX queue, in the range 0-7 */ + u8 id; + + /* Number of TX DMA descriptors in the descriptor ring */ + int size; + + /* Index of last TX DMA descriptor that was inserted */ + int txq_put_index; + + /* Index of the TX DMA descriptor to be cleaned up */ + int txq_get_index; + + /* Virtual address of the TX DMA descriptors array */ + struct mvneta_tx_desc *descs; + + /* DMA address of the TX DMA descriptors array */ + dma_addr_t descs_phys; + + /* Index of the last TX DMA descriptor */ + int last_desc; + + /* Index of the next TX DMA descriptor to process */ + int next_desc_to_proc; +}; + +struct mvneta_rx_queue { + /* rx queue number, in the range 0-7 */ + u8 id; + + /* num of rx descriptors in the rx descriptor ring */ + int size; + + /* Virtual address of the RX DMA descriptors array */ + struct mvneta_rx_desc *descs; + + /* DMA address of the RX DMA descriptors array */ + dma_addr_t descs_phys; + + /* Index of the last RX DMA descriptor */ + int last_desc; + + /* Index of the next RX DMA descriptor to process */ + int next_desc_to_proc; +}; + +/* U-Boot doesn't use the queues, so set the number to 1 */ +static int rxq_number = 1; +static int txq_number = 1; +static int rxq_def; + +struct buffer_location { + struct mvneta_tx_desc *tx_descs; + struct mvneta_rx_desc *rx_descs; + u32 rx_buffers; +}; + +/* + * All 4 interfaces use the same global buffer, since only one interface + * can be enabled at once + */ +static struct buffer_location buffer_loc; + +/* + * Page table entries are set to 1MB, or multiples of 1MB + * (not < 1MB). driver uses less bd's so use 1MB bdspace. + */ +#define BD_SPACE (1 << 20) + +/* Utility/helper methods */ + +/* Write helper method */ +static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data) +{ + writel(data, pp->base + offset); +} + +/* Read helper method */ +static u32 mvreg_read(struct mvneta_port *pp, u32 offset) +{ + return readl(pp->base + offset); +} + +/* Clear all MIB counters */ +static void mvneta_mib_counters_clear(struct mvneta_port *pp) +{ + int i; + + /* Perform dummy reads from MIB counters */ + for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4) + mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i)); +} + +/* Rx descriptors helper methods */ + +/* Checks whether the RX descriptor having this status is both the first + * and the last descriptor for the RX packet. Each RX packet is currently + * received through a single RX descriptor, so not having each RX + * descriptor with its first and last bits set is an error + */ +static int mvneta_rxq_desc_is_first_last(u32 status) +{ + return (status & MVNETA_RXD_FIRST_LAST_DESC) == + MVNETA_RXD_FIRST_LAST_DESC; +} + +/* Add number of descriptors ready to receive new packets */ +static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp, + struct mvneta_rx_queue *rxq, + int ndescs) +{ + /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can + * be added at once + */ + while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) { + mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), + (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX << + MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); + ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX; + } + + mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), + (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); +} + +/* Get number of RX descriptors occupied by received packets */ +static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp, + struct mvneta_rx_queue *rxq) +{ + u32 val; + + val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id)); + return val & MVNETA_RXQ_OCCUPIED_ALL_MASK; +} + +/* Update num of rx desc called upon return from rx path or + * from mvneta_rxq_drop_pkts(). + */ +static void mvneta_rxq_desc_num_update(struct mvneta_port *pp, + struct mvneta_rx_queue *rxq, + int rx_done, int rx_filled) +{ + u32 val; + + if ((rx_done <= 0xff) && (rx_filled <= 0xff)) { + val = rx_done | + (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT); + mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); + return; + } + + /* Only 255 descriptors can be added at once */ + while ((rx_done > 0) || (rx_filled > 0)) { + if (rx_done <= 0xff) { + val = rx_done; + rx_done = 0; + } else { + val = 0xff; + rx_done -= 0xff; + } + if (rx_filled <= 0xff) { + val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; + rx_filled = 0; + } else { + val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; + rx_filled -= 0xff; + } + mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); + } +} + +/* Get pointer to next RX descriptor to be processed by SW */ +static struct mvneta_rx_desc * +mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq) +{ + int rx_desc = rxq->next_desc_to_proc; + + rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc); + return rxq->descs + rx_desc; +} + +/* Tx descriptors helper methods */ + +/* Update HW with number of TX descriptors to be sent */ +static void mvneta_txq_pend_desc_add(struct mvneta_port *pp, + struct mvneta_tx_queue *txq, + int pend_desc) +{ + u32 val; + + /* Only 255 descriptors can be added at once ; Assume caller + * process TX desriptors in quanta less than 256 + */ + val = pend_desc; + mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); +} + +/* Get pointer to next TX descriptor to be processed (send) by HW */ +static struct mvneta_tx_desc * +mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq) +{ + int tx_desc = txq->next_desc_to_proc; + + txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc); + return txq->descs + tx_desc; +} + +/* Set rxq buf size */ +static void mvneta_rxq_buf_size_set(struct mvneta_port *pp, + struct mvneta_rx_queue *rxq, + int buf_size) +{ + u32 val; + + val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id)); + + val &= ~MVNETA_RXQ_BUF_SIZE_MASK; + val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT); + + mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val); +} + +/* Start the Ethernet port RX and TX activity */ +static void mvneta_port_up(struct mvneta_port *pp) +{ + int queue; + u32 q_map; + + /* Enable all initialized TXs. */ + mvneta_mib_counters_clear(pp); + q_map = 0; + for (queue = 0; queue < txq_number; queue++) { + struct mvneta_tx_queue *txq = &pp->txqs[queue]; + if (txq->descs != NULL) + q_map |= (1 << queue); + } + mvreg_write(pp, MVNETA_TXQ_CMD, q_map); + + /* Enable all initialized RXQs. */ + q_map = 0; + for (queue = 0; queue < rxq_number; queue++) { + struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; + if (rxq->descs != NULL) + q_map |= (1 << queue); + } + mvreg_write(pp, MVNETA_RXQ_CMD, q_map); +} + +/* Stop the Ethernet port activity */ +static void mvneta_port_down(struct mvneta_port *pp) +{ + u32 val; + int count; + + /* Stop Rx port activity. Check port Rx activity. */ + val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK; + + /* Issue stop command for active channels only */ + if (val != 0) + mvreg_write(pp, MVNETA_RXQ_CMD, + val << MVNETA_RXQ_DISABLE_SHIFT); + + /* Wait for all Rx activity to terminate. */ + count = 0; + do { + if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) { + netdev_warn(pp->dev, + "TIMEOUT for RX stopped ! rx_queue_cmd: 0x08%x\n", + val); + break; + } + mdelay(1); + + val = mvreg_read(pp, MVNETA_RXQ_CMD); + } while (val & 0xff); + + /* Stop Tx port activity. Check port Tx activity. Issue stop + * command for active channels only + */ + val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK; + + if (val != 0) + mvreg_write(pp, MVNETA_TXQ_CMD, + (val << MVNETA_TXQ_DISABLE_SHIFT)); + + /* Wait for all Tx activity to terminate. */ + count = 0; + do { + if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) { + netdev_warn(pp->dev, + "TIMEOUT for TX stopped status=0x%08x\n", + val); + break; + } + mdelay(1); + + /* Check TX Command reg that all Txqs are stopped */ + val = mvreg_read(pp, MVNETA_TXQ_CMD); + + } while (val & 0xff); + + /* Double check to verify that TX FIFO is empty */ + count = 0; + do { + if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) { + netdev_warn(pp->dev, + "TX FIFO empty timeout status=0x08%x\n", + val); + break; + } + mdelay(1); + + val = mvreg_read(pp, MVNETA_PORT_STATUS); + } while (!(val & MVNETA_TX_FIFO_EMPTY) && + (val & MVNETA_TX_IN_PRGRS)); + + udelay(200); +} + +/* Enable the port by setting the port enable bit of the MAC control register */ +static void mvneta_port_enable(struct mvneta_port *pp) +{ + u32 val; + + /* Enable port */ + val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); + val |= MVNETA_GMAC0_PORT_ENABLE; + mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); +} + +/* Disable the port and wait for about 200 usec before retuning */ +static void mvneta_port_disable(struct mvneta_port *pp) +{ + u32 val; + + /* Reset the Enable bit in the Serial Control Register */ + val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); + val &= ~MVNETA_GMAC0_PORT_ENABLE; + mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); + + udelay(200); +} + +/* Multicast tables methods */ + +/* Set all entries in Unicast MAC Table; queue==-1 means reject all */ +static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue) +{ + int offset; + u32 val; + + if (queue == -1) { + val = 0; + } else { + val = 0x1 | (queue << 1); + val |= (val << 24) | (val << 16) | (val << 8); + } + + for (offset = 0; offset <= 0xc; offset += 4) + mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val); +} + +/* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */ +static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue) +{ + int offset; + u32 val; + + if (queue == -1) { + val = 0; + } else { + val = 0x1 | (queue << 1); + val |= (val << 24) | (val << 16) | (val << 8); + } + + for (offset = 0; offset <= 0xfc; offset += 4) + mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val); +} + +/* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */ +static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue) +{ + int offset; + u32 val; + + if (queue == -1) { + memset(pp->mcast_count, 0, sizeof(pp->mcast_count)); + val = 0; + } else { + memset(pp->mcast_count, 1, sizeof(pp->mcast_count)); + val = 0x1 | (queue << 1); + val |= (val << 24) | (val << 16) | (val << 8); + } + + for (offset = 0; offset <= 0xfc; offset += 4) + mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val); +} + +/* This method sets defaults to the NETA port: + * Clears interrupt Cause and Mask registers. + * Clears all MAC tables. + * Sets defaults to all registers. + * Resets RX and TX descriptor rings. + * Resets PHY. + * This method can be called after mvneta_port_down() to return the port + * settings to defaults. + */ +static void mvneta_defaults_set(struct mvneta_port *pp) +{ + int cpu; + int queue; + u32 val; + + /* Clear all Cause registers */ + mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0); + mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0); + mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); + + /* Mask all interrupts */ + mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); + mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0); + mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0); + mvreg_write(pp, MVNETA_INTR_ENABLE, 0); + + /* Enable MBUS Retry bit16 */ + mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20); + + /* Set CPU queue access map - all CPUs have access to all RX + * queues and to all TX queues + */ + for (cpu = 0; cpu < CONFIG_NR_CPUS; cpu++) + mvreg_write(pp, MVNETA_CPU_MAP(cpu), + (MVNETA_CPU_RXQ_ACCESS_ALL_MASK | + MVNETA_CPU_TXQ_ACCESS_ALL_MASK)); + + /* Reset RX and TX DMAs */ + mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); + mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); + + /* Disable Legacy WRR, Disable EJP, Release from reset */ + mvreg_write(pp, MVNETA_TXQ_CMD_1, 0); + for (queue = 0; queue < txq_number; queue++) { + mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0); + mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0); + } + + mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); + mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); + + /* Set Port Acceleration Mode */ + val = MVNETA_ACC_MODE_EXT; + mvreg_write(pp, MVNETA_ACC_MODE, val); + + /* Update val of portCfg register accordingly with all RxQueue types */ + val = MVNETA_PORT_CONFIG_DEFL_VALUE(rxq_def); + mvreg_write(pp, MVNETA_PORT_CONFIG, val); + + val = 0; + mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val); + mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64); + + /* Build PORT_SDMA_CONFIG_REG */ + val = 0; + + /* Default burst size */ + val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); + val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); + val |= MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP; + + /* Assign port SDMA configuration */ + mvreg_write(pp, MVNETA_SDMA_CONFIG, val); + + /* Enable PHY polling in hardware for U-Boot */ + val = mvreg_read(pp, MVNETA_UNIT_CONTROL); + val |= MVNETA_PHY_POLLING_ENABLE; + mvreg_write(pp, MVNETA_UNIT_CONTROL, val); + + mvneta_set_ucast_table(pp, -1); + mvneta_set_special_mcast_table(pp, -1); + mvneta_set_other_mcast_table(pp, -1); +} + +/* Set unicast address */ +static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble, + int queue) +{ + unsigned int unicast_reg; + unsigned int tbl_offset; + unsigned int reg_offset; + + /* Locate the Unicast table entry */ + last_nibble = (0xf & last_nibble); + + /* offset from unicast tbl base */ + tbl_offset = (last_nibble / 4) * 4; + + /* offset within the above reg */ + reg_offset = last_nibble % 4; + + unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset)); + + if (queue == -1) { + /* Clear accepts frame bit at specified unicast DA tbl entry */ + unicast_reg &= ~(0xff << (8 * reg_offset)); + } else { + unicast_reg &= ~(0xff << (8 * reg_offset)); + unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); + } + + mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg); +} + +/* Set mac address */ +static void mvneta_mac_addr_set(struct mvneta_port *pp, unsigned char *addr, + int queue) +{ + unsigned int mac_h; + unsigned int mac_l; + + if (queue != -1) { + mac_l = (addr[4] << 8) | (addr[5]); + mac_h = (addr[0] << 24) | (addr[1] << 16) | + (addr[2] << 8) | (addr[3] << 0); + + mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l); + mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h); + } + + /* Accept frames of this address */ + mvneta_set_ucast_addr(pp, addr[5], queue); +} + +/* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */ +static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc, + u32 phys_addr, u32 cookie) +{ + rx_desc->buf_cookie = cookie; + rx_desc->buf_phys_addr = phys_addr; +} + +/* Decrement sent descriptors counter */ +static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp, + struct mvneta_tx_queue *txq, + int sent_desc) +{ + u32 val; + + /* Only 255 TX descriptors can be updated at once */ + while (sent_desc > 0xff) { + val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT; + mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); + sent_desc = sent_desc - 0xff; + } + + val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT; + mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); +} + +/* Get number of TX descriptors already sent by HW */ +static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp, + struct mvneta_tx_queue *txq) +{ + u32 val; + int sent_desc; + + val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id)); + sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >> + MVNETA_TXQ_SENT_DESC_SHIFT; + + return sent_desc; +} + +/* Display more error info */ +static void mvneta_rx_error(struct mvneta_port *pp, + struct mvneta_rx_desc *rx_desc) +{ + u32 status = rx_desc->status; + + if (!mvneta_rxq_desc_is_first_last(status)) { + netdev_err(pp->dev, + "bad rx status %08x (buffer oversize), size=%d\n", + status, rx_desc->data_size); + return; + } + + switch (status & MVNETA_RXD_ERR_CODE_MASK) { + case MVNETA_RXD_ERR_CRC: + netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n", + status, rx_desc->data_size); + break; + case MVNETA_RXD_ERR_OVERRUN: + netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n", + status, rx_desc->data_size); + break; + case MVNETA_RXD_ERR_LEN: + netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n", + status, rx_desc->data_size); + break; + case MVNETA_RXD_ERR_RESOURCE: + netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n", + status, rx_desc->data_size); + break; + } +} + +static struct mvneta_rx_queue *mvneta_rxq_handle_get(struct mvneta_port *pp, + int rxq) +{ + return &pp->rxqs[rxq]; +} + + +/* Drop packets received by the RXQ and free buffers */ +static void mvneta_rxq_drop_pkts(struct mvneta_port *pp, + struct mvneta_rx_queue *rxq) +{ + int rx_done; + + rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); + if (rx_done) + mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); +} + +/* Handle rxq fill: allocates rxq skbs; called when initializing a port */ +static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq, + int num) +{ + int i; + + for (i = 0; i < num; i++) { + u32 addr; + + /* U-Boot special: Fill in the rx buffer addresses */ + addr = buffer_loc.rx_buffers + (i * RX_BUFFER_SIZE); + mvneta_rx_desc_fill(rxq->descs + i, addr, addr); + } + + /* Add this number of RX descriptors as non occupied (ready to + * get packets) + */ + mvneta_rxq_non_occup_desc_add(pp, rxq, i); + + return 0; +} + +/* Rx/Tx queue initialization/cleanup methods */ + +/* Create a specified RX queue */ +static int mvneta_rxq_init(struct mvneta_port *pp, + struct mvneta_rx_queue *rxq) + +{ + rxq->size = pp->rx_ring_size; + + /* Allocate memory for RX descriptors */ + rxq->descs_phys = (dma_addr_t)rxq->descs; + if (rxq->descs == NULL) + return -ENOMEM; + + rxq->last_desc = rxq->size - 1; + + /* Set Rx descriptors queue starting address */ + mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys); + mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size); + + /* Fill RXQ with buffers from RX pool */ + mvneta_rxq_buf_size_set(pp, rxq, RX_BUFFER_SIZE); + mvneta_rxq_fill(pp, rxq, rxq->size); + + return 0; +} + +/* Cleanup Rx queue */ +static void mvneta_rxq_deinit(struct mvneta_port *pp, + struct mvneta_rx_queue *rxq) +{ + mvneta_rxq_drop_pkts(pp, rxq); + + rxq->descs = NULL; + rxq->last_desc = 0; + rxq->next_desc_to_proc = 0; + rxq->descs_phys = 0; +} + +/* Create and initialize a tx queue */ +static int mvneta_txq_init(struct mvneta_port *pp, + struct mvneta_tx_queue *txq) +{ + txq->size = pp->tx_ring_size; + + /* Allocate memory for TX descriptors */ + txq->descs_phys = (u32)txq->descs; + if (txq->descs == NULL) + return -ENOMEM; + + txq->last_desc = txq->size - 1; + + /* Set maximum bandwidth for enabled TXQs */ + mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff); + mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff); + + /* Set Tx descriptors queue starting address */ + mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys); + mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size); + + return 0; +} + +/* Free allocated resources when mvneta_txq_init() fails to allocate memory*/ +static void mvneta_txq_deinit(struct mvneta_port *pp, + struct mvneta_tx_queue *txq) +{ + txq->descs = NULL; + txq->last_desc = 0; + txq->next_desc_to_proc = 0; + txq->descs_phys = 0; + + /* Set minimum bandwidth for disabled TXQs */ + mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0); + mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0); + + /* Set Tx descriptors queue starting address and size */ + mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0); + mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0); +} + +/* Cleanup all Tx queues */ +static void mvneta_cleanup_txqs(struct mvneta_port *pp) +{ + int queue; + + for (queue = 0; queue < txq_number; queue++) + mvneta_txq_deinit(pp, &pp->txqs[queue]); +} + +/* Cleanup all Rx queues */ +static void mvneta_cleanup_rxqs(struct mvneta_port *pp) +{ + int queue; + + for (queue = 0; queue < rxq_number; queue++) + mvneta_rxq_deinit(pp, &pp->rxqs[queue]); +} + + +/* Init all Rx queues */ +static int mvneta_setup_rxqs(struct mvneta_port *pp) +{ + int queue; + + for (queue = 0; queue < rxq_number; queue++) { + int err = mvneta_rxq_init(pp, &pp->rxqs[queue]); + if (err) { + netdev_err(pp->dev, "%s: can't create rxq=%d\n", + __func__, queue); + mvneta_cleanup_rxqs(pp); + return err; + } + } + + return 0; +} + +/* Init all tx queues */ +static int mvneta_setup_txqs(struct mvneta_port *pp) +{ + int queue; + + for (queue = 0; queue < txq_number; queue++) { + int err = mvneta_txq_init(pp, &pp->txqs[queue]); + if (err) { + netdev_err(pp->dev, "%s: can't create txq=%d\n", + __func__, queue); + mvneta_cleanup_txqs(pp); + return err; + } + } + + return 0; +} + +static void mvneta_start_dev(struct mvneta_port *pp) +{ + /* start the Rx/Tx activity */ + mvneta_port_enable(pp); +} + +static void mvneta_adjust_link(struct eth_device *dev) +{ + struct mvneta_port *pp = dev->priv; + struct phy_device *phydev = pp->phydev; + int status_change = 0; + + if (phydev->link) { + if ((pp->speed != phydev->speed) || + (pp->duplex != phydev->duplex)) { + u32 val; + + val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); + val &= ~(MVNETA_GMAC_CONFIG_MII_SPEED | + MVNETA_GMAC_CONFIG_GMII_SPEED | + MVNETA_GMAC_CONFIG_FULL_DUPLEX | + MVNETA_GMAC_AN_SPEED_EN | + MVNETA_GMAC_AN_DUPLEX_EN); + + if (phydev->duplex) + val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX; + + if (phydev->speed == SPEED_1000) + val |= MVNETA_GMAC_CONFIG_GMII_SPEED; + else + val |= MVNETA_GMAC_CONFIG_MII_SPEED; + + mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); + + pp->duplex = phydev->duplex; + pp->speed = phydev->speed; + } + } + + if (phydev->link != pp->link) { + if (!phydev->link) { + pp->duplex = -1; + pp->speed = 0; + } + + pp->link = phydev->link; + status_change = 1; + } + + if (status_change) { + if (phydev->link) { + u32 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); + val |= (MVNETA_GMAC_FORCE_LINK_PASS | + MVNETA_GMAC_FORCE_LINK_DOWN); + mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); + mvneta_port_up(pp); + } else { + mvneta_port_down(pp); + } + } +} + +static int mvneta_open(struct eth_device *dev) +{ + struct mvneta_port *pp = dev->priv; + int ret; + + ret = mvneta_setup_rxqs(pp); + if (ret) + return ret; + + ret = mvneta_setup_txqs(pp); + if (ret) + return ret; + + mvneta_adjust_link(dev); + + mvneta_start_dev(pp); + + return 0; +} + +/* Initialize hw */ +static int mvneta_init(struct mvneta_port *pp) +{ + int queue; + + /* Disable port */ + mvneta_port_disable(pp); + + /* Set port default values */ + mvneta_defaults_set(pp); + + pp->txqs = kzalloc(txq_number * sizeof(struct mvneta_tx_queue), + GFP_KERNEL); + if (!pp->txqs) + return -ENOMEM; + + /* U-Boot special: use preallocated area */ + pp->txqs[0].descs = buffer_loc.tx_descs; + + /* Initialize TX descriptor rings */ + for (queue = 0; queue < txq_number; queue++) { + struct mvneta_tx_queue *txq = &pp->txqs[queue]; + txq->id = queue; + txq->size = pp->tx_ring_size; + } + + pp->rxqs = kzalloc(rxq_number * sizeof(struct mvneta_rx_queue), + GFP_KERNEL); + if (!pp->rxqs) { + kfree(pp->txqs); + return -ENOMEM; + } + + /* U-Boot special: use preallocated area */ + pp->rxqs[0].descs = buffer_loc.rx_descs; + + /* Create Rx descriptor rings */ + for (queue = 0; queue < rxq_number; queue++) { + struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; + rxq->id = queue; + rxq->size = pp->rx_ring_size; + } + + return 0; +} + +/* platform glue : initialize decoding windows */ +static void mvneta_conf_mbus_windows(struct mvneta_port *pp) +{ + const struct mbus_dram_target_info *dram; + u32 win_enable; + u32 win_protect; + int i; + + dram = mvebu_mbus_dram_info(); + for (i = 0; i < 6; i++) { + mvreg_write(pp, MVNETA_WIN_BASE(i), 0); + mvreg_write(pp, MVNETA_WIN_SIZE(i), 0); + + if (i < 4) + mvreg_write(pp, MVNETA_WIN_REMAP(i), 0); + } + + win_enable = 0x3f; + win_protect = 0; + + for (i = 0; i < dram->num_cs; i++) { + const struct mbus_dram_window *cs = dram->cs + i; + mvreg_write(pp, MVNETA_WIN_BASE(i), (cs->base & 0xffff0000) | + (cs->mbus_attr << 8) | dram->mbus_dram_target_id); + + mvreg_write(pp, MVNETA_WIN_SIZE(i), + (cs->size - 1) & 0xffff0000); + + win_enable &= ~(1 << i); + win_protect |= 3 << (2 * i); + } + + mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable); +} + +/* Power up the port */ +static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode) +{ + u32 ctrl; + + /* MAC Cause register should be cleared */ + mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0); + + ctrl = mvreg_read(pp, MVNETA_GMAC_CTRL_2); + + /* Even though it might look weird, when we're configured in + * SGMII or QSGMII mode, the RGMII bit needs to be set. + */ + switch (phy_mode) { + case PHY_INTERFACE_MODE_QSGMII: + mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_QSGMII_SERDES_PROTO); + ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII; + break; + case PHY_INTERFACE_MODE_SGMII: + mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO); + ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII; + break; + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + ctrl |= MVNETA_GMAC2_PORT_RGMII; + break; + default: + return -EINVAL; + } + + /* Cancel Port Reset */ + ctrl &= ~MVNETA_GMAC2_PORT_RESET; + mvreg_write(pp, MVNETA_GMAC_CTRL_2, ctrl); + + while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) & + MVNETA_GMAC2_PORT_RESET) != 0) + continue; + + return 0; +} + +/* Device initialization routine */ +static int mvneta_probe(struct eth_device *dev) +{ + struct mvneta_port *pp = dev->priv; + int err; + + pp->tx_ring_size = MVNETA_MAX_TXD; + pp->rx_ring_size = MVNETA_MAX_RXD; + + err = mvneta_init(pp); + if (err < 0) { + dev_err(&pdev->dev, "can't init eth hal\n"); + return err; + } + + mvneta_conf_mbus_windows(pp); + + mvneta_mac_addr_set(pp, dev->enetaddr, rxq_def); + + err = mvneta_port_power_up(pp, pp->phy_interface); + if (err < 0) { + dev_err(&pdev->dev, "can't power up port\n"); + return err; + } + + /* Call open() now as it needs to be done before runing send() */ + mvneta_open(dev); + + return 0; +} + +/* U-Boot only functions follow here */ + +/* SMI / MDIO functions */ + +static int smi_wait_ready(struct mvneta_port *pp) +{ + u32 timeout = MVNETA_SMI_TIMEOUT; + u32 smi_reg; + + /* wait till the SMI is not busy */ + do { + /* read smi register */ + smi_reg = mvreg_read(pp, MVNETA_SMI); + if (timeout-- == 0) { + printf("Error: SMI busy timeout\n"); + return -EFAULT; + } + } while (smi_reg & MVNETA_SMI_BUSY); + + return 0; +} + +/* + * smi_reg_read - miiphy_read callback function. + * + * Returns 16bit phy register value, or 0xffff on error + */ +static int smi_reg_read(const char *devname, u8 phy_adr, u8 reg_ofs, u16 *data) +{ + struct eth_device *dev = eth_get_dev_by_name(devname); + struct mvneta_port *pp = dev->priv; + u32 smi_reg; + u32 timeout; + + /* check parameters */ + if (phy_adr > MVNETA_PHY_ADDR_MASK) { + printf("Error: Invalid PHY address %d\n", phy_adr); + return -EFAULT; + } + + if (reg_ofs > MVNETA_PHY_REG_MASK) { + printf("Err: Invalid register offset %d\n", reg_ofs); + return -EFAULT; + } + + /* wait till the SMI is not busy */ + if (smi_wait_ready(pp) < 0) + return -EFAULT; + + /* fill the phy address and regiser offset and read opcode */ + smi_reg = (phy_adr << MVNETA_SMI_DEV_ADDR_OFFS) + | (reg_ofs << MVNETA_SMI_REG_ADDR_OFFS) + | MVNETA_SMI_OPCODE_READ; + + /* write the smi register */ + mvreg_write(pp, MVNETA_SMI, smi_reg); + + /*wait till read value is ready */ + timeout = MVNETA_SMI_TIMEOUT; + + do { + /* read smi register */ + smi_reg = mvreg_read(pp, MVNETA_SMI); + if (timeout-- == 0) { + printf("Err: SMI read ready timeout\n"); + return -EFAULT; + } + } while (!(smi_reg & MVNETA_SMI_READ_VALID)); + + /* Wait for the data to update in the SMI register */ + for (timeout = 0; timeout < MVNETA_SMI_TIMEOUT; timeout++) + ; + + *data = (u16)(mvreg_read(pp, MVNETA_SMI) & MVNETA_SMI_DATA_MASK); + + return 0; +} + +/* + * smi_reg_write - imiiphy_write callback function. + * + * Returns 0 if write succeed, -EINVAL on bad parameters + * -ETIME on timeout + */ +static int smi_reg_write(const char *devname, u8 phy_adr, u8 reg_ofs, u16 data) +{ + struct eth_device *dev = eth_get_dev_by_name(devname); + struct mvneta_port *pp = dev->priv; + u32 smi_reg; + + /* check parameters */ + if (phy_adr > MVNETA_PHY_ADDR_MASK) { + printf("Error: Invalid PHY address %d\n", phy_adr); + return -EFAULT; + } + + if (reg_ofs > MVNETA_PHY_REG_MASK) { + printf("Err: Invalid register offset %d\n", reg_ofs); + return -EFAULT; + } + + /* wait till the SMI is not busy */ + if (smi_wait_ready(pp) < 0) + return -EFAULT; + + /* fill the phy addr and reg offset and write opcode and data */ + smi_reg = (data << MVNETA_SMI_DATA_OFFS); + smi_reg |= (phy_adr << MVNETA_SMI_DEV_ADDR_OFFS) + | (reg_ofs << MVNETA_SMI_REG_ADDR_OFFS); + smi_reg &= ~MVNETA_SMI_OPCODE_READ; + + /* write the smi register */ + mvreg_write(pp, MVNETA_SMI, smi_reg); + + return 0; +} + +static int mvneta_init_u_boot(struct eth_device *dev, bd_t *bis) +{ + struct mvneta_port *pp = dev->priv; + struct phy_device *phydev; + + mvneta_port_power_up(pp, pp->phy_interface); + + if (!pp->init || pp->link == 0) { + /* Set phy address of the port */ + mvreg_write(pp, MVNETA_PHY_ADDR, pp->phyaddr); + phydev = phy_connect(pp->bus, pp->phyaddr, dev, + pp->phy_interface); + + pp->phydev = phydev; + phy_config(phydev); + phy_startup(phydev); + if (!phydev->link) { + printf("%s: No link.\n", phydev->dev->name); + return -1; + } + + /* Full init on first call */ + mvneta_probe(dev); + pp->init = 1; + } else { + /* Upon all following calls, this is enough */ + mvneta_port_up(pp); + mvneta_port_enable(pp); + } + + return 0; +} + +static int mvneta_send(struct eth_device *dev, void *ptr, int len) +{ + struct mvneta_port *pp = dev->priv; + struct mvneta_tx_queue *txq = &pp->txqs[0]; + struct mvneta_tx_desc *tx_desc; + int sent_desc; + u32 timeout = 0; + + /* Get a descriptor for the first part of the packet */ + tx_desc = mvneta_txq_next_desc_get(txq); + + tx_desc->buf_phys_addr = (u32)ptr; + tx_desc->data_size = len; + flush_dcache_range((u32)ptr, (u32)ptr + len); + + /* First and Last descriptor */ + tx_desc->command = MVNETA_TX_L4_CSUM_NOT | MVNETA_TXD_FLZ_DESC; + mvneta_txq_pend_desc_add(pp, txq, 1); + + /* Wait for packet to be sent (queue might help with speed here) */ + sent_desc = mvneta_txq_sent_desc_num_get(pp, txq); + while (!sent_desc) { + if (timeout++ > 10000) { + printf("timeout: packet not sent\n"); + return -1; + } + sent_desc = mvneta_txq_sent_desc_num_get(pp, txq); + } + + /* txDone has increased - hw sent packet */ + mvneta_txq_sent_desc_dec(pp, txq, sent_desc); + return 0; + + return 0; +} + +static int mvneta_recv(struct eth_device *dev) +{ + struct mvneta_port *pp = dev->priv; + int rx_done; + int packets_done; + struct mvneta_rx_queue *rxq; + + /* get rx queue */ + rxq = mvneta_rxq_handle_get(pp, rxq_def); + rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); + packets_done = rx_done; + + while (packets_done--) { + struct mvneta_rx_desc *rx_desc; + unsigned char *data; + u32 rx_status; + int rx_bytes; + + /* + * No cache invalidation needed here, since the desc's are + * located in a uncached memory region + */ + rx_desc = mvneta_rxq_next_desc_get(rxq); + + rx_status = rx_desc->status; + if (!mvneta_rxq_desc_is_first_last(rx_status) || + (rx_status & MVNETA_RXD_ERR_SUMMARY)) { + mvneta_rx_error(pp, rx_desc); + /* leave the descriptor untouched */ + continue; + } + + /* 2 bytes for marvell header. 4 bytes for crc */ + rx_bytes = rx_desc->data_size - 6; + + /* give packet to stack - skip on first 2 bytes */ + data = (u8 *)rx_desc->buf_cookie + 2; + /* + * No cache invalidation needed here, since the rx_buffer's are + * located in a uncached memory region + */ + net_process_received_packet(data, rx_bytes); + } + + /* Update rxq management counters */ + if (rx_done) + mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); + + return 0; +} + +static void mvneta_halt(struct eth_device *dev) +{ + struct mvneta_port *pp = dev->priv; + + mvneta_port_down(pp); + mvneta_port_disable(pp); +} + +int mvneta_initialize(bd_t *bis, int base_addr, int devnum, int phy_addr) +{ + struct eth_device *dev; + struct mvneta_port *pp; + void *bd_space; + + dev = calloc(1, sizeof(*dev)); + if (dev == NULL) + return -ENOMEM; + + pp = calloc(1, sizeof(*pp)); + if (pp == NULL) + return -ENOMEM; + + dev->priv = pp; + + /* + * Allocate buffer area for descs and rx_buffers. This is only + * done once for all interfaces. As only one interface can + * be active. Make this area DMA save by disabling the D-cache + */ + if (!buffer_loc.tx_descs) { + /* Align buffer area for descs and rx_buffers to 1MiB */ + bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE); + mmu_set_region_dcache_behaviour((u32)bd_space, BD_SPACE, + DCACHE_OFF); + buffer_loc.tx_descs = (struct mvneta_tx_desc *)bd_space; + buffer_loc.rx_descs = (struct mvneta_rx_desc *) + ((u32)bd_space + + MVNETA_MAX_TXD * sizeof(struct mvneta_tx_desc)); + buffer_loc.rx_buffers = (u32) + (bd_space + + MVNETA_MAX_TXD * sizeof(struct mvneta_tx_desc) + + MVNETA_MAX_RXD * sizeof(struct mvneta_rx_desc)); + } + + sprintf(dev->name, "neta%d", devnum); + + pp->base = (void __iomem *)base_addr; + dev->iobase = base_addr; + dev->init = mvneta_init_u_boot; + dev->halt = mvneta_halt; + dev->send = mvneta_send; + dev->recv = mvneta_recv; + dev->write_hwaddr = NULL; + + /* + * The PHY interface type is configured via the + * board specific CONFIG_SYS_NETA_INTERFACE_TYPE + * define. + */ + pp->phy_interface = CONFIG_SYS_NETA_INTERFACE_TYPE; + + eth_register(dev); + + pp->phyaddr = phy_addr; + miiphy_register(dev->name, smi_reg_read, smi_reg_write); + pp->bus = miiphy_get_dev_by_name(dev->name); + + return 1; +} diff --git a/sources/uboot-be550/drivers/net/natsemi.c b/sources/uboot-be550/drivers/net/natsemi.c new file mode 100644 index 00000000..0ed9bb57 --- /dev/null +++ b/sources/uboot-be550/drivers/net/natsemi.c @@ -0,0 +1,883 @@ +/* + natsemi.c: A U-Boot driver for the NatSemi DP8381x series. + Author: Mark A. Rakes (mark_rakes@vivato.net) + + Adapted from an Etherboot driver written by: + + Copyright (C) 2001 Entity Cyber, Inc. + + This development of this Etherboot driver was funded by + + Sicom Systems: http://www.sicompos.com/ + + Author: Marty Connor (mdc@thinguin.org) + Adapted from a Linux driver which was written by Donald Becker + + This software may be used and distributed according to the terms + of the GNU Public License (GPL), incorporated herein by reference. + + Original Copyright Notice: + + Written/copyright 1999-2001 by Donald Becker. + + This software may be used and distributed according to the terms of + the GNU General Public License (GPL), incorporated herein by reference. + Drivers based on or derived from this code fall under the GPL and must + retain the authorship, copyright and license notice. This file is not + a complete program and may only be used when the entire operating + system is licensed under the GPL. License for under other terms may be + available. Contact the original author for details. + + The original author may be reached as becker@scyld.com, or at + Scyld Computing Corporation + 410 Severn Ave., Suite 210 + Annapolis MD 21403 + + Support information and updates available at + http://www.scyld.com/network/netsemi.html + + References: + http://www.scyld.com/expert/100mbps.html + http://www.scyld.com/expert/NWay.html + Datasheet is available from: + http://www.national.com/pf/DP/DP83815.html +*/ + +/* Revision History + * October 2002 mar 1.0 + * Initial U-Boot Release. Tested with Netgear FA311 board + * and dp83815 chipset on custom board +*/ + +/* Includes */ +#include +#include +#include +#include +#include +#include + +/* defines */ +#define EEPROM_SIZE 0xb /*12 16-bit chunks, or 24 bytes*/ + +#define DSIZE 0x00000FFF +#define ETH_ALEN 6 +#define CRC_SIZE 4 +#define TOUT_LOOP 500000 +#define TX_BUF_SIZE 1536 +#define RX_BUF_SIZE 1536 +#define NUM_RX_DESC 4 /* Number of Rx descriptor registers. */ + +/* Offsets to the device registers. + Unlike software-only systems, device drivers interact with complex hardware. + It's not useful to define symbolic names for every register bit in the + device. */ +enum register_offsets { + ChipCmd = 0x00, + ChipConfig = 0x04, + EECtrl = 0x08, + IntrMask = 0x14, + IntrEnable = 0x18, + TxRingPtr = 0x20, + TxConfig = 0x24, + RxRingPtr = 0x30, + RxConfig = 0x34, + ClkRun = 0x3C, + RxFilterAddr = 0x48, + RxFilterData = 0x4C, + SiliconRev = 0x58, + PCIPM = 0x44, + BasicControl = 0x80, + BasicStatus = 0x84, + /* These are from the spec, around page 78... on a separate table. */ + PGSEL = 0xCC, + PMDCSR = 0xE4, + TSTDAT = 0xFC, + DSPCFG = 0xF4, + SDCFG = 0x8C +}; + +/* Bit in ChipCmd. */ +enum ChipCmdBits { + ChipReset = 0x100, + RxReset = 0x20, + TxReset = 0x10, + RxOff = 0x08, + RxOn = 0x04, + TxOff = 0x02, + TxOn = 0x01 +}; + +enum ChipConfigBits { + LinkSts = 0x80000000, + HundSpeed = 0x40000000, + FullDuplex = 0x20000000, + TenPolarity = 0x10000000, + AnegDone = 0x08000000, + AnegEnBothBoth = 0x0000E000, + AnegDis100Full = 0x0000C000, + AnegEn100Both = 0x0000A000, + AnegDis100Half = 0x00008000, + AnegEnBothHalf = 0x00006000, + AnegDis10Full = 0x00004000, + AnegEn10Both = 0x00002000, + DuplexMask = 0x00008000, + SpeedMask = 0x00004000, + AnegMask = 0x00002000, + AnegDis10Half = 0x00000000, + ExtPhy = 0x00001000, + PhyRst = 0x00000400, + PhyDis = 0x00000200, + BootRomDisable = 0x00000004, + BEMode = 0x00000001, +}; + +enum TxConfig_bits { + TxDrthMask = 0x3f, + TxFlthMask = 0x3f00, + TxMxdmaMask = 0x700000, + TxMxdma_512 = 0x0, + TxMxdma_4 = 0x100000, + TxMxdma_8 = 0x200000, + TxMxdma_16 = 0x300000, + TxMxdma_32 = 0x400000, + TxMxdma_64 = 0x500000, + TxMxdma_128 = 0x600000, + TxMxdma_256 = 0x700000, + TxCollRetry = 0x800000, + TxAutoPad = 0x10000000, + TxMacLoop = 0x20000000, + TxHeartIgn = 0x40000000, + TxCarrierIgn = 0x80000000 +}; + +enum RxConfig_bits { + RxDrthMask = 0x3e, + RxMxdmaMask = 0x700000, + RxMxdma_512 = 0x0, + RxMxdma_4 = 0x100000, + RxMxdma_8 = 0x200000, + RxMxdma_16 = 0x300000, + RxMxdma_32 = 0x400000, + RxMxdma_64 = 0x500000, + RxMxdma_128 = 0x600000, + RxMxdma_256 = 0x700000, + RxAcceptLong = 0x8000000, + RxAcceptTx = 0x10000000, + RxAcceptRunt = 0x40000000, + RxAcceptErr = 0x80000000 +}; + +/* Bits in the RxMode register. */ +enum rx_mode_bits { + AcceptErr = 0x20, + AcceptRunt = 0x10, + AcceptBroadcast = 0xC0000000, + AcceptMulticast = 0x00200000, + AcceptAllMulticast = 0x20000000, + AcceptAllPhys = 0x10000000, + AcceptMyPhys = 0x08000000 +}; + +typedef struct _BufferDesc { + u32 link; + vu_long cmdsts; + u32 bufptr; + u32 software_use; +} BufferDesc; + +/* Bits in network_desc.status */ +enum desc_status_bits { + DescOwn = 0x80000000, DescMore = 0x40000000, DescIntr = 0x20000000, + DescNoCRC = 0x10000000, DescPktOK = 0x08000000, + DescSizeMask = 0xfff, + + DescTxAbort = 0x04000000, DescTxFIFO = 0x02000000, + DescTxCarrier = 0x01000000, DescTxDefer = 0x00800000, + DescTxExcDefer = 0x00400000, DescTxOOWCol = 0x00200000, + DescTxExcColl = 0x00100000, DescTxCollCount = 0x000f0000, + + DescRxAbort = 0x04000000, DescRxOver = 0x02000000, + DescRxDest = 0x01800000, DescRxLong = 0x00400000, + DescRxRunt = 0x00200000, DescRxInvalid = 0x00100000, + DescRxCRC = 0x00080000, DescRxAlign = 0x00040000, + DescRxLoop = 0x00020000, DesRxColl = 0x00010000, +}; + +/* Globals */ +#ifdef NATSEMI_DEBUG +static int natsemi_debug = 0; /* 1 verbose debugging, 0 normal */ +#endif +static u32 SavedClkRun; +static unsigned int cur_rx; +static unsigned int advertising; +static unsigned int rx_config; +static unsigned int tx_config; + +/* Note: transmit and receive buffers and descriptors must be + longword aligned */ +static BufferDesc txd __attribute__ ((aligned(4))); +static BufferDesc rxd[NUM_RX_DESC] __attribute__ ((aligned(4))); + +static unsigned char txb[TX_BUF_SIZE] __attribute__ ((aligned(4))); +static unsigned char rxb[NUM_RX_DESC * RX_BUF_SIZE] + __attribute__ ((aligned(4))); + +/* Function Prototypes */ +#if 0 +static void write_eeprom(struct eth_device *dev, long addr, int location, + short value); +#endif +static int read_eeprom(struct eth_device *dev, long addr, int location); +static int mdio_read(struct eth_device *dev, int phy_id, int location); +static int natsemi_init(struct eth_device *dev, bd_t * bis); +static void natsemi_reset(struct eth_device *dev); +static void natsemi_init_rxfilter(struct eth_device *dev); +static void natsemi_init_txd(struct eth_device *dev); +static void natsemi_init_rxd(struct eth_device *dev); +static void natsemi_set_rx_mode(struct eth_device *dev); +static void natsemi_check_duplex(struct eth_device *dev); +static int natsemi_send(struct eth_device *dev, void *packet, int length); +static int natsemi_poll(struct eth_device *dev); +static void natsemi_disable(struct eth_device *dev); + +static struct pci_device_id supported[] = { + {PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_83815}, + {} +}; + +#define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a) +#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a) + +static inline int +INW(struct eth_device *dev, u_long addr) +{ + return le16_to_cpu(*(vu_short *) (addr + dev->iobase)); +} + +static int +INL(struct eth_device *dev, u_long addr) +{ + return le32_to_cpu(*(vu_long *) (addr + dev->iobase)); +} + +static inline void +OUTW(struct eth_device *dev, int command, u_long addr) +{ + *(vu_short *) ((addr + dev->iobase)) = cpu_to_le16(command); +} + +static inline void +OUTL(struct eth_device *dev, int command, u_long addr) +{ + *(vu_long *) ((addr + dev->iobase)) = cpu_to_le32(command); +} + +/* + * Function: natsemi_initialize + * + * Description: Retrieves the MAC address of the card, and sets up some + * globals required by other routines, and initializes the NIC, making it + * ready to send and receive packets. + * + * Side effects: + * leaves the natsemi initialized, and ready to receive packets. + * + * Returns: struct eth_device *: pointer to NIC data structure + */ + +int +natsemi_initialize(bd_t * bis) +{ + pci_dev_t devno; + int card_number = 0; + struct eth_device *dev; + u32 iobase, status, chip_config; + int i, idx = 0; + int prev_eedata; + u32 tmp; + + while (1) { + /* Find PCI device(s) */ + if ((devno = pci_find_devices(supported, idx++)) < 0) { + break; + } + + pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &iobase); + iobase &= ~0x3; /* bit 1: unused and bit 0: I/O Space Indicator */ + + pci_write_config_dword(devno, PCI_COMMAND, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + + /* Check if I/O accesses and Bus Mastering are enabled. */ + pci_read_config_dword(devno, PCI_COMMAND, &status); + if (!(status & PCI_COMMAND_MEMORY)) { + printf("Error: Can not enable MEM access.\n"); + continue; + } else if (!(status & PCI_COMMAND_MASTER)) { + printf("Error: Can not enable Bus Mastering.\n"); + continue; + } + + dev = (struct eth_device *) malloc(sizeof *dev); + if (!dev) { + printf("natsemi: Can not allocate memory\n"); + break; + } + memset(dev, 0, sizeof(*dev)); + + sprintf(dev->name, "dp83815#%d", card_number); + dev->iobase = bus_to_phys(iobase); +#ifdef NATSEMI_DEBUG + printf("natsemi: NatSemi ns8381[56] @ %#x\n", dev->iobase); +#endif + dev->priv = (void *) devno; + dev->init = natsemi_init; + dev->halt = natsemi_disable; + dev->send = natsemi_send; + dev->recv = natsemi_poll; + + eth_register(dev); + + card_number++; + + /* Set the latency timer for value. */ + pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x20); + + udelay(10 * 1000); + + /* natsemi has a non-standard PM control register + * in PCI config space. Some boards apparently need + * to be brought to D0 in this manner. */ + pci_read_config_dword(devno, PCIPM, &tmp); + if (tmp & (0x03 | 0x100)) { + /* D0 state, disable PME assertion */ + u32 newtmp = tmp & ~(0x03 | 0x100); + pci_write_config_dword(devno, PCIPM, newtmp); + } + + printf("natsemi: EEPROM contents:\n"); + for (i = 0; i <= EEPROM_SIZE; i++) { + short eedata = read_eeprom(dev, EECtrl, i); + printf(" %04hx", eedata); + } + printf("\n"); + + /* get MAC address */ + prev_eedata = read_eeprom(dev, EECtrl, 6); + for (i = 0; i < 3; i++) { + int eedata = read_eeprom(dev, EECtrl, i + 7); + dev->enetaddr[i*2] = (eedata << 1) + (prev_eedata >> 15); + dev->enetaddr[i*2+1] = eedata >> 7; + prev_eedata = eedata; + } + + /* Reset the chip to erase any previous misconfiguration. */ + OUTL(dev, ChipReset, ChipCmd); + + advertising = mdio_read(dev, 1, 4); + chip_config = INL(dev, ChipConfig); +#ifdef NATSEMI_DEBUG + printf("%s: Transceiver status %#08X advertising %#08X\n", + dev->name, (int) INL(dev, BasicStatus), advertising); + printf("%s: Transceiver default autoneg. %s 10%s %s duplex.\n", + dev->name, chip_config & AnegMask ? "enabled, advertise" : + "disabled, force", chip_config & SpeedMask ? "0" : "", + chip_config & DuplexMask ? "full" : "half"); +#endif + chip_config |= AnegEnBothBoth; +#ifdef NATSEMI_DEBUG + printf("%s: changed to autoneg. %s 10%s %s duplex.\n", + dev->name, chip_config & AnegMask ? "enabled, advertise" : + "disabled, force", chip_config & SpeedMask ? "0" : "", + chip_config & DuplexMask ? "full" : "half"); +#endif + /*write new autoneg bits, reset phy*/ + OUTL(dev, (chip_config | PhyRst), ChipConfig); + /*un-reset phy*/ + OUTL(dev, chip_config, ChipConfig); + + /* Disable PME: + * The PME bit is initialized from the EEPROM contents. + * PCI cards probably have PME disabled, but motherboard + * implementations may have PME set to enable WakeOnLan. + * With PME set the chip will scan incoming packets but + * nothing will be written to memory. */ + SavedClkRun = INL(dev, ClkRun); + OUTL(dev, SavedClkRun & ~0x100, ClkRun); + } + return card_number; +} + +/* Read the EEPROM and MII Management Data I/O (MDIO) interfaces. + The EEPROM code is for common 93c06/46 EEPROMs w/ 6bit addresses. */ + +/* Delay between EEPROM clock transitions. + No extra delay is needed with 33MHz PCI, but future 66MHz + access may need a delay. */ +#define eeprom_delay(ee_addr) INL(dev, ee_addr) + +enum EEPROM_Ctrl_Bits { + EE_ShiftClk = 0x04, + EE_DataIn = 0x01, + EE_ChipSelect = 0x08, + EE_DataOut = 0x02 +}; + +#define EE_Write0 (EE_ChipSelect) +#define EE_Write1 (EE_ChipSelect | EE_DataIn) +/* The EEPROM commands include the alway-set leading bit. */ +enum EEPROM_Cmds { + EE_WrEnCmd = (4 << 6), EE_WriteCmd = (5 << 6), + EE_ReadCmd = (6 << 6), EE_EraseCmd = (7 << 6), +}; + +#if 0 +static void +write_eeprom(struct eth_device *dev, long addr, int location, short value) +{ + int i; + int ee_addr = (typeof(ee_addr))addr; + short wren_cmd = EE_WrEnCmd | 0x30; /*wren is 100 + 11XXXX*/ + short write_cmd = location | EE_WriteCmd; + +#ifdef NATSEMI_DEBUG + printf("write_eeprom: %08x, %04hx, %04hx\n", + dev->iobase + ee_addr, write_cmd, value); +#endif + /* Shift the write enable command bits out. */ + for (i = 9; i >= 0; i--) { + short cmdval = (wren_cmd & (1 << i)) ? EE_Write1 : EE_Write0; + OUTL(dev, cmdval, ee_addr); + eeprom_delay(ee_addr); + OUTL(dev, cmdval | EE_ShiftClk, ee_addr); + eeprom_delay(ee_addr); + } + + OUTL(dev, 0, ee_addr); /*bring chip select low*/ + OUTL(dev, EE_ShiftClk, ee_addr); + eeprom_delay(ee_addr); + + /* Shift the write command bits out. */ + for (i = 9; i >= 0; i--) { + short cmdval = (write_cmd & (1 << i)) ? EE_Write1 : EE_Write0; + OUTL(dev, cmdval, ee_addr); + eeprom_delay(ee_addr); + OUTL(dev, cmdval | EE_ShiftClk, ee_addr); + eeprom_delay(ee_addr); + } + + for (i = 0; i < 16; i++) { + short cmdval = (value & (1 << i)) ? EE_Write1 : EE_Write0; + OUTL(dev, cmdval, ee_addr); + eeprom_delay(ee_addr); + OUTL(dev, cmdval | EE_ShiftClk, ee_addr); + eeprom_delay(ee_addr); + } + + OUTL(dev, 0, ee_addr); /*bring chip select low*/ + OUTL(dev, EE_ShiftClk, ee_addr); + for (i = 0; i < 200000; i++) { + OUTL(dev, EE_Write0, ee_addr); /*poll for done*/ + if (INL(dev, ee_addr) & EE_DataOut) { + break; /*finished*/ + } + } + eeprom_delay(ee_addr); + + /* Terminate the EEPROM access. */ + OUTL(dev, EE_Write0, ee_addr); + OUTL(dev, 0, ee_addr); + return; +} +#endif + +static int +read_eeprom(struct eth_device *dev, long addr, int location) +{ + int i; + int retval = 0; + int ee_addr = (typeof(ee_addr))addr; + int read_cmd = location | EE_ReadCmd; + + OUTL(dev, EE_Write0, ee_addr); + + /* Shift the read command bits out. */ + for (i = 10; i >= 0; i--) { + short dataval = (read_cmd & (1 << i)) ? EE_Write1 : EE_Write0; + OUTL(dev, dataval, ee_addr); + eeprom_delay(ee_addr); + OUTL(dev, dataval | EE_ShiftClk, ee_addr); + eeprom_delay(ee_addr); + } + OUTL(dev, EE_ChipSelect, ee_addr); + eeprom_delay(ee_addr); + + for (i = 0; i < 16; i++) { + OUTL(dev, EE_ChipSelect | EE_ShiftClk, ee_addr); + eeprom_delay(ee_addr); + retval |= (INL(dev, ee_addr) & EE_DataOut) ? 1 << i : 0; + OUTL(dev, EE_ChipSelect, ee_addr); + eeprom_delay(ee_addr); + } + + /* Terminate the EEPROM access. */ + OUTL(dev, EE_Write0, ee_addr); + OUTL(dev, 0, ee_addr); +#ifdef NATSEMI_DEBUG + if (natsemi_debug) + printf("read_eeprom: %08x, %08x, retval %08x\n", + dev->iobase + ee_addr, read_cmd, retval); +#endif + return retval; +} + +/* MII transceiver control section. + The 83815 series has an internal transceiver, and we present the + management registers as if they were MII connected. */ + +static int +mdio_read(struct eth_device *dev, int phy_id, int location) +{ + if (phy_id == 1 && location < 32) + return INL(dev, BasicControl+(location<<2))&0xffff; + else + return 0xffff; +} + +/* Function: natsemi_init + * + * Description: resets the ethernet controller chip and configures + * registers and data structures required for sending and receiving packets. + * + * Arguments: struct eth_device *dev: NIC data structure + * + * returns: int. + */ + +static int +natsemi_init(struct eth_device *dev, bd_t * bis) +{ + + natsemi_reset(dev); + + /* Disable PME: + * The PME bit is initialized from the EEPROM contents. + * PCI cards probably have PME disabled, but motherboard + * implementations may have PME set to enable WakeOnLan. + * With PME set the chip will scan incoming packets but + * nothing will be written to memory. */ + OUTL(dev, SavedClkRun & ~0x100, ClkRun); + + natsemi_init_rxfilter(dev); + natsemi_init_txd(dev); + natsemi_init_rxd(dev); + + /* Configure the PCI bus bursts and FIFO thresholds. */ + tx_config = TxAutoPad | TxCollRetry | TxMxdma_256 | (0x1002); + rx_config = RxMxdma_256 | 0x20; + +#ifdef NATSEMI_DEBUG + printf("%s: Setting TxConfig Register %#08X\n", dev->name, tx_config); + printf("%s: Setting RxConfig Register %#08X\n", dev->name, rx_config); +#endif + OUTL(dev, tx_config, TxConfig); + OUTL(dev, rx_config, RxConfig); + + natsemi_check_duplex(dev); + natsemi_set_rx_mode(dev); + + OUTL(dev, (RxOn | TxOn), ChipCmd); + return 1; +} + +/* + * Function: natsemi_reset + * + * Description: soft resets the controller chip + * + * Arguments: struct eth_device *dev: NIC data structure + * + * Returns: void. + */ +static void +natsemi_reset(struct eth_device *dev) +{ + OUTL(dev, ChipReset, ChipCmd); + + /* On page 78 of the spec, they recommend some settings for "optimum + performance" to be done in sequence. These settings optimize some + of the 100Mbit autodetection circuitry. Also, we only want to do + this for rev C of the chip. */ + if (INL(dev, SiliconRev) == 0x302) { + OUTW(dev, 0x0001, PGSEL); + OUTW(dev, 0x189C, PMDCSR); + OUTW(dev, 0x0000, TSTDAT); + OUTW(dev, 0x5040, DSPCFG); + OUTW(dev, 0x008C, SDCFG); + } + /* Disable interrupts using the mask. */ + OUTL(dev, 0, IntrMask); + OUTL(dev, 0, IntrEnable); +} + +/* Function: natsemi_init_rxfilter + * + * Description: sets receive filter address to our MAC address + * + * Arguments: struct eth_device *dev: NIC data structure + * + * returns: void. + */ + +static void +natsemi_init_rxfilter(struct eth_device *dev) +{ + int i; + + for (i = 0; i < ETH_ALEN; i += 2) { + OUTL(dev, i, RxFilterAddr); + OUTW(dev, dev->enetaddr[i] + (dev->enetaddr[i + 1] << 8), + RxFilterData); + } +} + +/* + * Function: natsemi_init_txd + * + * Description: initializes the Tx descriptor + * + * Arguments: struct eth_device *dev: NIC data structure + * + * returns: void. + */ + +static void +natsemi_init_txd(struct eth_device *dev) +{ + txd.link = (u32) 0; + txd.cmdsts = (u32) 0; + txd.bufptr = (u32) & txb[0]; + + /* load Transmit Descriptor Register */ + OUTL(dev, (u32) & txd, TxRingPtr); +#ifdef NATSEMI_DEBUG + printf("natsemi_init_txd: TX descriptor reg loaded with: %#08X\n", + INL(dev, TxRingPtr)); +#endif +} + +/* Function: natsemi_init_rxd + * + * Description: initializes the Rx descriptor ring + * + * Arguments: struct eth_device *dev: NIC data structure + * + * Returns: void. + */ + +static void +natsemi_init_rxd(struct eth_device *dev) +{ + int i; + + cur_rx = 0; + + /* init RX descriptor */ + for (i = 0; i < NUM_RX_DESC; i++) { + rxd[i].link = + cpu_to_le32((i + 1 < + NUM_RX_DESC) ? (u32) & rxd[i + + 1] : (u32) & + rxd[0]); + rxd[i].cmdsts = cpu_to_le32((u32) RX_BUF_SIZE); + rxd[i].bufptr = cpu_to_le32((u32) & rxb[i * RX_BUF_SIZE]); +#ifdef NATSEMI_DEBUG + printf + ("natsemi_init_rxd: rxd[%d]=%p link=%X cmdsts=%lX bufptr=%X\n", + i, &rxd[i], le32_to_cpu(rxd[i].link), + rxd[i].cmdsts, rxd[i].bufptr); +#endif + } + + /* load Receive Descriptor Register */ + OUTL(dev, (u32) & rxd[0], RxRingPtr); + +#ifdef NATSEMI_DEBUG + printf("natsemi_init_rxd: RX descriptor register loaded with: %X\n", + INL(dev, RxRingPtr)); +#endif +} + +/* Function: natsemi_set_rx_mode + * + * Description: + * sets the receive mode to accept all broadcast packets and packets + * with our MAC address, and reject all multicast packets. + * + * Arguments: struct eth_device *dev: NIC data structure + * + * Returns: void. + */ + +static void +natsemi_set_rx_mode(struct eth_device *dev) +{ + u32 rx_mode = AcceptBroadcast | AcceptMyPhys; + + OUTL(dev, rx_mode, RxFilterAddr); +} + +static void +natsemi_check_duplex(struct eth_device *dev) +{ + int duplex = INL(dev, ChipConfig) & FullDuplex ? 1 : 0; + +#ifdef NATSEMI_DEBUG + printf("%s: Setting %s-duplex based on negotiated link" + " capability.\n", dev->name, duplex ? "full" : "half"); +#endif + if (duplex) { + rx_config |= RxAcceptTx; + tx_config |= (TxCarrierIgn | TxHeartIgn); + } else { + rx_config &= ~RxAcceptTx; + tx_config &= ~(TxCarrierIgn | TxHeartIgn); + } + OUTL(dev, tx_config, TxConfig); + OUTL(dev, rx_config, RxConfig); +} + +/* Function: natsemi_send + * + * Description: transmits a packet and waits for completion or timeout. + * + * Returns: void. */ +static int natsemi_send(struct eth_device *dev, void *packet, int length) +{ + u32 i, status = 0; + u32 tx_status = 0; + u32 *tx_ptr = &tx_status; + vu_long *res = (vu_long *)tx_ptr; + + /* Stop the transmitter */ + OUTL(dev, TxOff, ChipCmd); + +#ifdef NATSEMI_DEBUG + if (natsemi_debug) + printf("natsemi_send: sending %d bytes\n", (int) length); +#endif + + /* set the transmit buffer descriptor and enable Transmit State Machine */ + txd.link = cpu_to_le32(0); + txd.bufptr = cpu_to_le32(phys_to_bus((u32) packet)); + txd.cmdsts = cpu_to_le32(DescOwn | length); + + /* load Transmit Descriptor Register */ + OUTL(dev, phys_to_bus((u32) & txd), TxRingPtr); +#ifdef NATSEMI_DEBUG + if (natsemi_debug) + printf("natsemi_send: TX descriptor register loaded with: %#08X\n", + INL(dev, TxRingPtr)); +#endif + /* restart the transmitter */ + OUTL(dev, TxOn, ChipCmd); + + for (i = 0; + (*res = le32_to_cpu(txd.cmdsts)) & DescOwn; + i++) { + if (i >= TOUT_LOOP) { + printf + ("%s: tx error buffer not ready: txd.cmdsts == %#X\n", + dev->name, tx_status); + goto Done; + } + } + + if (!(tx_status & DescPktOK)) { + printf("natsemi_send: Transmit error, Tx status %X.\n", + tx_status); + goto Done; + } + + status = 1; + Done: + return status; +} + +/* Function: natsemi_poll + * + * Description: checks for a received packet and returns it if found. + * + * Arguments: struct eth_device *dev: NIC data structure + * + * Returns: 1 if packet was received. + * 0 if no packet was received. + * + * Side effects: + * Returns (copies) the packet to the array dev->packet. + * Returns the length of the packet. + */ + +static int +natsemi_poll(struct eth_device *dev) +{ + int retstat = 0; + int length = 0; + u32 rx_status = le32_to_cpu(rxd[cur_rx].cmdsts); + + if (!(rx_status & (u32) DescOwn)) + return retstat; +#ifdef NATSEMI_DEBUG + if (natsemi_debug) + printf("natsemi_poll: got a packet: cur_rx:%d, status:%X\n", + cur_rx, rx_status); +#endif + length = (rx_status & DSIZE) - CRC_SIZE; + + if ((rx_status & (DescMore | DescPktOK | DescRxLong)) != DescPktOK) { + printf + ("natsemi_poll: Corrupted packet received, buffer status = %X\n", + rx_status); + retstat = 0; + } else { /* give packet to higher level routine */ + net_process_received_packet((rxb + cur_rx * RX_BUF_SIZE), + length); + retstat = 1; + } + + /* return the descriptor and buffer to receive ring */ + rxd[cur_rx].cmdsts = cpu_to_le32(RX_BUF_SIZE); + rxd[cur_rx].bufptr = cpu_to_le32((u32) & rxb[cur_rx * RX_BUF_SIZE]); + + if (++cur_rx == NUM_RX_DESC) + cur_rx = 0; + + /* re-enable the potentially idle receive state machine */ + OUTL(dev, RxOn, ChipCmd); + + return retstat; +} + +/* Function: natsemi_disable + * + * Description: Turns off interrupts and stops Tx and Rx engines + * + * Arguments: struct eth_device *dev: NIC data structure + * + * Returns: void. + */ + +static void +natsemi_disable(struct eth_device *dev) +{ + /* Disable interrupts using the mask. */ + OUTL(dev, 0, IntrMask); + OUTL(dev, 0, IntrEnable); + + /* Stop the chip's Tx and Rx processes. */ + OUTL(dev, RxOff | TxOff, ChipCmd); + + /* Restore PME enable bit */ + OUTL(dev, SavedClkRun, ClkRun); +} diff --git a/sources/uboot-be550/drivers/net/ne2000.c b/sources/uboot-be550/drivers/net/ne2000.c new file mode 100644 index 00000000..e6cd3e9b --- /dev/null +++ b/sources/uboot-be550/drivers/net/ne2000.c @@ -0,0 +1,259 @@ +/* +Ported to U-Boot by Christian Pellegrin + +Based on sources from the Linux kernel (pcnet_cs.c, 8390.h) and +eCOS(if_dp83902a.c, if_dp83902a.h). Both of these 2 wonderful world +are GPL, so this is, of course, GPL. + +========================================================================== + +dev/if_dp83902a.c + +Ethernet device driver for NS DP83902a ethernet controller + +========================================================================== +####ECOSGPLCOPYRIGHTBEGIN#### +------------------------------------------- +This file is part of eCos, the Embedded Configurable Operating System. +Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. + +eCos is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 2 or (at your option) any later version. + +eCos is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +You should have received a copy of the GNU General Public License along +with eCos; if not, write to the Free Software Foundation, Inc., +59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. + +As a special exception, if other files instantiate templates or use macros +or inline functions from this file, or you compile this file and link it +with other works to produce a work based on this file, this file does not +by itself cause the resulting work to be covered by the GNU General Public +License. However the source code for this file must still be made available +in accordance with section (3) of the GNU General Public License. + +This exception does not invalidate any other reasons why a work based on +this file might be covered by the GNU General Public License. + +Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +at http://sources.redhat.com/ecos/ecos-license/ +------------------------------------------- +####ECOSGPLCOPYRIGHTEND#### +####BSDCOPYRIGHTBEGIN#### + +------------------------------------------- + +Portions of this software may have been derived from OpenBSD or other sources, +and are covered by the appropriate copyright disclaimers included herein. + +------------------------------------------- + +####BSDCOPYRIGHTEND#### +========================================================================== +#####DESCRIPTIONBEGIN#### + +Author(s): gthomas +Contributors: gthomas, jskov, rsandifo +Date: 2001-06-13 +Purpose: +Description: + +FIXME: Will fail if pinged with large packets (1520 bytes) +Add promisc config +Add SNMP + +####DESCRIPTIONEND#### + +========================================================================== +*/ + +#include +#include + +/* NE2000 base header file */ +#include "ne2000_base.h" + +/* find prom (taken from pc_net_cs.c from Linux) */ + +#include "8390.h" +/* +typedef struct hw_info_t { + u_int offset; + u_char a0, a1, a2; + u_int flags; +} hw_info_t; +*/ +#define DELAY_OUTPUT 0x01 +#define HAS_MISC_REG 0x02 +#define USE_BIG_BUF 0x04 +#define HAS_IBM_MISC 0x08 +#define IS_DL10019 0x10 +#define IS_DL10022 0x20 +#define HAS_MII 0x40 +#define USE_SHMEM 0x80 /* autodetected */ + +#define AM79C9XX_HOME_PHY 0x00006B90 /* HomePNA PHY */ +#define AM79C9XX_ETH_PHY 0x00006B70 /* 10baseT PHY */ +#define MII_PHYID_REV_MASK 0xfffffff0 +#define MII_PHYID_REG1 0x02 +#define MII_PHYID_REG2 0x03 + +static hw_info_t hw_info[] = { + { /* Accton EN2212 */ 0x0ff0, 0x00, 0x00, 0xe8, DELAY_OUTPUT }, + { /* Allied Telesis LA-PCM */ 0x0ff0, 0x00, 0x00, 0xf4, 0 }, + { /* APEX MultiCard */ 0x03f4, 0x00, 0x20, 0xe5, 0 }, + { /* ASANTE FriendlyNet */ 0x4910, 0x00, 0x00, 0x94, + DELAY_OUTPUT | HAS_IBM_MISC }, + { /* Danpex EN-6200P2 */ 0x0110, 0x00, 0x40, 0xc7, 0 }, + { /* DataTrek NetCard */ 0x0ff0, 0x00, 0x20, 0xe8, 0 }, + { /* Dayna CommuniCard E */ 0x0110, 0x00, 0x80, 0x19, 0 }, + { /* D-Link DE-650 */ 0x0040, 0x00, 0x80, 0xc8, 0 }, + { /* EP-210 Ethernet */ 0x0110, 0x00, 0x40, 0x33, 0 }, + { /* EP4000 Ethernet */ 0x01c0, 0x00, 0x00, 0xb4, 0 }, + { /* Epson EEN10B */ 0x0ff0, 0x00, 0x00, 0x48, + HAS_MISC_REG | HAS_IBM_MISC }, + { /* ELECOM Laneed LD-CDWA */ 0xb8, 0x08, 0x00, 0x42, 0 }, + { /* Hypertec Ethernet */ 0x01c0, 0x00, 0x40, 0x4c, 0 }, + { /* IBM CCAE */ 0x0ff0, 0x08, 0x00, 0x5a, + HAS_MISC_REG | HAS_IBM_MISC }, + { /* IBM CCAE */ 0x0ff0, 0x00, 0x04, 0xac, + HAS_MISC_REG | HAS_IBM_MISC }, + { /* IBM CCAE */ 0x0ff0, 0x00, 0x06, 0x29, + HAS_MISC_REG | HAS_IBM_MISC }, + { /* IBM FME */ 0x0374, 0x08, 0x00, 0x5a, + HAS_MISC_REG | HAS_IBM_MISC }, + { /* IBM FME */ 0x0374, 0x00, 0x04, 0xac, + HAS_MISC_REG | HAS_IBM_MISC }, + { /* Kansai KLA-PCM/T */ 0x0ff0, 0x00, 0x60, 0x87, + HAS_MISC_REG | HAS_IBM_MISC }, + { /* NSC DP83903 */ 0x0374, 0x08, 0x00, 0x17, + HAS_MISC_REG | HAS_IBM_MISC }, + { /* NSC DP83903 */ 0x0374, 0x00, 0xc0, 0xa8, + HAS_MISC_REG | HAS_IBM_MISC }, + { /* NSC DP83903 */ 0x0374, 0x00, 0xa0, 0xb0, + HAS_MISC_REG | HAS_IBM_MISC }, + { /* NSC DP83903 */ 0x0198, 0x00, 0x20, 0xe0, + HAS_MISC_REG | HAS_IBM_MISC }, + { /* I-O DATA PCLA/T */ 0x0ff0, 0x00, 0xa0, 0xb0, 0 }, + { /* Katron PE-520 */ 0x0110, 0x00, 0x40, 0xf6, 0 }, + { /* Kingston KNE-PCM/x */ 0x0ff0, 0x00, 0xc0, 0xf0, + HAS_MISC_REG | HAS_IBM_MISC }, + { /* Kingston KNE-PCM/x */ 0x0ff0, 0xe2, 0x0c, 0x0f, + HAS_MISC_REG | HAS_IBM_MISC }, + { /* Kingston KNE-PC2 */ 0x0180, 0x00, 0xc0, 0xf0, 0 }, + { /* Maxtech PCN2000 */ 0x5000, 0x00, 0x00, 0xe8, 0 }, + { /* NDC Instant-Link */ 0x003a, 0x00, 0x80, 0xc6, 0 }, + { /* NE2000 Compatible */ 0x0ff0, 0x00, 0xa0, 0x0c, 0 }, + { /* Network General Sniffer */ 0x0ff0, 0x00, 0x00, 0x65, + HAS_MISC_REG | HAS_IBM_MISC }, + { /* Panasonic VEL211 */ 0x0ff0, 0x00, 0x80, 0x45, + HAS_MISC_REG | HAS_IBM_MISC }, + { /* PreMax PE-200 */ 0x07f0, 0x00, 0x20, 0xe0, 0 }, + { /* RPTI EP400 */ 0x0110, 0x00, 0x40, 0x95, 0 }, + { /* SCM Ethernet */ 0x0ff0, 0x00, 0x20, 0xcb, 0 }, + { /* Socket EA */ 0x4000, 0x00, 0xc0, 0x1b, + DELAY_OUTPUT | HAS_MISC_REG | USE_BIG_BUF }, + { /* Socket LP-E CF+ */ 0x01c0, 0x00, 0xc0, 0x1b, 0 }, + { /* SuperSocket RE450T */ 0x0110, 0x00, 0xe0, 0x98, 0 }, + { /* Volktek NPL-402CT */ 0x0060, 0x00, 0x40, 0x05, 0 }, + { /* NEC PC-9801N-J12 */ 0x0ff0, 0x00, 0x00, 0x4c, 0 }, + { /* PCMCIA Technology OEM */ 0x01c8, 0x00, 0xa0, 0x0c, 0 }, + { /* Qemu */ 0x0, 0x52, 0x54, 0x00, 0 }, + { /* RTL8019AS */ 0x0, 0x0, 0x18, 0x5f, 0 } +}; + +#define NR_INFO (sizeof(hw_info)/sizeof(hw_info_t)) + +#define PCNET_CMD 0x00 +#define PCNET_DATAPORT 0x10 /* NatSemi-defined port window offset. */ +#define PCNET_RESET 0x1f /* Issue a read to reset, a write to clear. */ +#define PCNET_MISC 0x18 /* For IBM CCAE and Socket EA cards */ + +static void pcnet_reset_8390(u8* addr) +{ + int i, r; + + n2k_outb(E8390_NODMA + E8390_PAGE0+E8390_STOP, E8390_CMD); + PRINTK("cmd (at %lx) is %x\n", addr + E8390_CMD, n2k_inb(E8390_CMD)); + n2k_outb(E8390_NODMA+E8390_PAGE1+E8390_STOP, E8390_CMD); + PRINTK("cmd (at %lx) is %x\n", addr + E8390_CMD, n2k_inb(E8390_CMD)); + n2k_outb(E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD); + PRINTK("cmd (at %lx) is %x\n", addr + E8390_CMD, n2k_inb(E8390_CMD)); + n2k_outb(E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD); + + n2k_outb(n2k_inb(PCNET_RESET), PCNET_RESET); + + for (i = 0; i < 100; i++) { + if ((r = (n2k_inb(EN0_ISR) & ENISR_RESET)) != 0) + break; + PRINTK("got %x in reset\n", r); + udelay(100); + } + n2k_outb(ENISR_RESET, EN0_ISR); /* Ack intr. */ + + if (i == 100) + printf("pcnet_reset_8390() did not complete.\n"); +} /* pcnet_reset_8390 */ + +int get_prom(u8* mac_addr, u8* base_addr) +{ + u8 prom[32]; + int i, j; + struct { + u_char value, offset; + } program_seq[] = { + {E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD}, /* Select page 0*/ + {0x48, EN0_DCFG}, /* Set byte-wide (0x48) access. */ + {0x00, EN0_RCNTLO}, /* Clear the count regs. */ + {0x00, EN0_RCNTHI}, + {0x00, EN0_IMR}, /* Mask completion irq. */ + {0xFF, EN0_ISR}, + {E8390_RXOFF, EN0_RXCR}, /* 0x20 Set to monitor */ + {E8390_TXOFF, EN0_TXCR}, /* 0x02 and loopback mode. */ + {32, EN0_RCNTLO}, + {0x00, EN0_RCNTHI}, + {0x00, EN0_RSARLO}, /* DMA starting at 0x0000. */ + {0x00, EN0_RSARHI}, + {E8390_RREAD+E8390_START, E8390_CMD}, + }; + + PRINTK ("trying to get MAC via prom reading\n"); + + pcnet_reset_8390 (base_addr); + + mdelay (10); + + for (i = 0; i < ARRAY_SIZE(program_seq); i++) + n2k_outb (program_seq[i].value, program_seq[i].offset); + + PRINTK ("PROM:"); + for (i = 0; i < 32; i++) { + prom[i] = n2k_inb (PCNET_DATAPORT); + PRINTK (" %02x", prom[i]); + } + PRINTK ("\n"); + for (i = 0; i < NR_INFO; i++) { + if ((prom[0] == hw_info[i].a0) && + (prom[2] == hw_info[i].a1) && + (prom[4] == hw_info[i].a2)) { + PRINTK ("matched board %d\n", i); + break; + } + } + if ((i < NR_INFO) || ((prom[28] == 0x57) && (prom[30] == 0x57))) { + PRINTK ("on exit i is %d/%ld\n", i, NR_INFO); + PRINTK ("MAC address is "); + for (j = 0; j < 6; j++) { + mac_addr[j] = prom[j << 1]; + PRINTK ("%02x:", mac_addr[i]); + } + PRINTK ("\n"); + return (i < NR_INFO) ? i : 0; + } + return 0; +} diff --git a/sources/uboot-be550/drivers/net/ne2000.h b/sources/uboot-be550/drivers/net/ne2000.h new file mode 100644 index 00000000..2cde6be4 --- /dev/null +++ b/sources/uboot-be550/drivers/net/ne2000.h @@ -0,0 +1,94 @@ +/* +Ported to U-Boot by Christian Pellegrin + +Based on sources from the Linux kernel (pcnet_cs.c, 8390.h) and +eCOS(if_dp83902a.c, if_dp83902a.h). Both of these 2 wonderful world +are GPL, so this is, of course, GPL. + +========================================================================== + + dev/dp83902a.h + + National Semiconductor DP83902a ethernet chip + +========================================================================== +####ECOSGPLCOPYRIGHTBEGIN#### + ------------------------------------------- + This file is part of eCos, the Embedded Configurable Operating System. + Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. + + eCos is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License as published by the Free + Software Foundation; either version 2 or (at your option) any later version. + + eCos is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + for more details. + + You should have received a copy of the GNU General Public License along + with eCos; if not, write to the Free Software Foundation, Inc., + 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. + + As a special exception, if other files instantiate templates or use macros + or inline functions from this file, or you compile this file and link it + with other works to produce a work based on this file, this file does not + by itself cause the resulting work to be covered by the GNU General Public + License. However the source code for this file must still be made available + in accordance with section (3) of the GNU General Public License. + + This exception does not invalidate any other reasons why a work based on + this file might be covered by the GNU General Public License. + + Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. + at http://sources.redhat.com/ecos/ecos-license/ + ------------------------------------------- +####ECOSGPLCOPYRIGHTEND#### +####BSDCOPYRIGHTBEGIN#### + + ------------------------------------------- + + Portions of this software may have been derived from OpenBSD or other sources, + and are covered by the appropriate copyright disclaimers included herein. + + ------------------------------------------- + +####BSDCOPYRIGHTEND#### +========================================================================== +#####DESCRIPTIONBEGIN#### + + Author(s): gthomas + Contributors: gthomas, jskov + Date: 2001-06-13 + Purpose: + Description: + +####DESCRIPTIONEND#### + +========================================================================== +*/ + +/* + * NE2000 support header file. + * Created by Nobuhiro Iwamatsu + */ + +#ifndef __DRIVERS_NE2000_H__ +#define __DRIVERS_NE2000_H__ + +/* Enable NE2000 basic init function */ +#define NE2000_BASIC_INIT + +#define DP_DATA 0x10 +#define START_PG 0x50 /* First page of TX buffer */ +#define START_PG2 0x48 +#define STOP_PG 0x80 /* Last page +1 of RX ring */ + +#define RX_START 0x50 +#define RX_END 0x80 + +#define DP_IN(_b_, _o_, _d_) (_d_) = *( (vu_char *) ((_b_)+(_o_))) +#define DP_OUT(_b_, _o_, _d_) *( (vu_char *) ((_b_)+(_o_))) = (_d_) +#define DP_IN_DATA(_b_, _d_) (_d_) = *( (vu_char *) ((_b_))) +#define DP_OUT_DATA(_b_, _d_) *( (vu_char *) ((_b_))) = (_d_) +#endif /* __DRIVERS_NE2000_H__ */ diff --git a/sources/uboot-be550/drivers/net/ne2000_base.c b/sources/uboot-be550/drivers/net/ne2000_base.c new file mode 100644 index 00000000..07a7cec2 --- /dev/null +++ b/sources/uboot-be550/drivers/net/ne2000_base.c @@ -0,0 +1,800 @@ +/* +Ported to U-Boot by Christian Pellegrin + +Based on sources from the Linux kernel (pcnet_cs.c, 8390.h) and +eCOS(if_dp83902a.c, if_dp83902a.h). Both of these 2 wonderful world +are GPL, so this is, of course, GPL. + +========================================================================== + +dev/if_dp83902a.c + +Ethernet device driver for NS DP83902a ethernet controller + +========================================================================== +####ECOSGPLCOPYRIGHTBEGIN#### +------------------------------------------- +This file is part of eCos, the Embedded Configurable Operating System. +Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. + +eCos is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 2 or (at your option) any later version. + +eCos is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +You should have received a copy of the GNU General Public License along +with eCos; if not, write to the Free Software Foundation, Inc., +59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. + +As a special exception, if other files instantiate templates or use macros +or inline functions from this file, or you compile this file and link it +with other works to produce a work based on this file, this file does not +by itself cause the resulting work to be covered by the GNU General Public +License. However the source code for this file must still be made available +in accordance with section (3) of the GNU General Public License. + +This exception does not invalidate any other reasons why a work based on +this file might be covered by the GNU General Public License. + +Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +at http://sources.redhat.com/ecos/ecos-license/ +------------------------------------------- +####ECOSGPLCOPYRIGHTEND#### +####BSDCOPYRIGHTBEGIN#### + +------------------------------------------- + +Portions of this software may have been derived from OpenBSD or other sources, +and are covered by the appropriate copyright disclaimers included herein. + +------------------------------------------- + +####BSDCOPYRIGHTEND#### +========================================================================== +#####DESCRIPTIONBEGIN#### + +Author(s): gthomas +Contributors: gthomas, jskov, rsandifo +Date: 2001-06-13 +Purpose: +Description: + +FIXME: Will fail if pinged with large packets (1520 bytes) +Add promisc config +Add SNMP + +####DESCRIPTIONEND#### + +========================================================================== +*/ + +#include +#include +#include +#include +#include + +/* forward definition of function used for the uboot interface */ +void uboot_push_packet_len(int len); +void uboot_push_tx_done(int key, int val); + +/* NE2000 base header file */ +#include "ne2000_base.h" + +#if defined(CONFIG_DRIVER_AX88796L) +/* AX88796L support */ +#include "ax88796.h" +#else +/* Basic NE2000 chip support */ +#include "ne2000.h" +#endif + +static dp83902a_priv_data_t nic; /* just one instance of the card supported */ + +/** + * This function reads the MAC address from the serial EEPROM, + * used if PROM read fails. Does nothing for ax88796 chips (sh boards) + */ +static bool +dp83902a_init(unsigned char *enetaddr) +{ + dp83902a_priv_data_t *dp = &nic; + u8* base; +#if defined(NE2000_BASIC_INIT) + int i; +#endif + + DEBUG_FUNCTION(); + + base = dp->base; + if (!base) + return false; /* No device found */ + + DEBUG_LINE(); + +#if defined(NE2000_BASIC_INIT) + /* AX88796L doesn't need */ + /* Prepare ESA */ + DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE1); /* Select page 1 */ + /* Use the address from the serial EEPROM */ + for (i = 0; i < 6; i++) + DP_IN(base, DP_P1_PAR0+i, dp->esa[i]); + DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE0); /* Select page 0 */ + + printf("NE2000 - %s ESA: %02x:%02x:%02x:%02x:%02x:%02x\n", + "eeprom", + dp->esa[0], + dp->esa[1], + dp->esa[2], + dp->esa[3], + dp->esa[4], + dp->esa[5] ); + + memcpy(enetaddr, dp->esa, 6); /* Use MAC from serial EEPROM */ +#endif /* NE2000_BASIC_INIT */ + return true; +} + +static void +dp83902a_stop(void) +{ + dp83902a_priv_data_t *dp = &nic; + u8 *base = dp->base; + + DEBUG_FUNCTION(); + + DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_STOP); /* Brutal */ + DP_OUT(base, DP_ISR, 0xFF); /* Clear any pending interrupts */ + DP_OUT(base, DP_IMR, 0x00); /* Disable all interrupts */ + + dp->running = false; +} + +/* + * This function is called to "start up" the interface. It may be called + * multiple times, even when the hardware is already running. It will be + * called whenever something "hardware oriented" changes and should leave + * the hardware ready to send/receive packets. + */ +static void +dp83902a_start(u8 * enaddr) +{ + dp83902a_priv_data_t *dp = &nic; + u8 *base = dp->base; + int i; + + debug("The MAC is %pM\n", enaddr); + + DEBUG_FUNCTION(); + + DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_STOP); /* Brutal */ + DP_OUT(base, DP_DCR, DP_DCR_INIT); + DP_OUT(base, DP_RBCH, 0); /* Remote byte count */ + DP_OUT(base, DP_RBCL, 0); + DP_OUT(base, DP_RCR, DP_RCR_MON); /* Accept no packets */ + DP_OUT(base, DP_TCR, DP_TCR_LOCAL); /* Transmitter [virtually] off */ + DP_OUT(base, DP_TPSR, dp->tx_buf1); /* Transmitter start page */ + dp->tx1 = dp->tx2 = 0; + dp->tx_next = dp->tx_buf1; + dp->tx_started = false; + dp->running = true; + DP_OUT(base, DP_PSTART, dp->rx_buf_start); /* Receive ring start page */ + DP_OUT(base, DP_BNDRY, dp->rx_buf_end - 1); /* Receive ring boundary */ + DP_OUT(base, DP_PSTOP, dp->rx_buf_end); /* Receive ring end page */ + dp->rx_next = dp->rx_buf_start - 1; + dp->running = true; + DP_OUT(base, DP_ISR, 0xFF); /* Clear any pending interrupts */ + DP_OUT(base, DP_IMR, DP_IMR_All); /* Enable all interrupts */ + DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE1 | DP_CR_STOP); /* Select page 1 */ + DP_OUT(base, DP_P1_CURP, dp->rx_buf_start); /* Current page - next free page for Rx */ + dp->running = true; + for (i = 0; i < ETHER_ADDR_LEN; i++) { + /* FIXME */ + /*((vu_short*)( base + ((DP_P1_PAR0 + i) * 2) + + * 0x1400)) = enaddr[i];*/ + DP_OUT(base, DP_P1_PAR0+i, enaddr[i]); + } + /* Enable and start device */ + DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START); + DP_OUT(base, DP_TCR, DP_TCR_NORMAL); /* Normal transmit operations */ + DP_OUT(base, DP_RCR, DP_RCR_AB); /* Accept broadcast, no errors, no multicast */ + dp->running = true; +} + +/* + * This routine is called to start the transmitter. It is split out from the + * data handling routine so it may be called either when data becomes first + * available or when an Tx interrupt occurs + */ + +static void +dp83902a_start_xmit(int start_page, int len) +{ + dp83902a_priv_data_t *dp = (dp83902a_priv_data_t *) &nic; + u8 *base = dp->base; + + DEBUG_FUNCTION(); + +#if DEBUG & 1 + printf("Tx pkt %d len %d\n", start_page, len); + if (dp->tx_started) + printf("TX already started?!?\n"); +#endif + + DP_OUT(base, DP_ISR, (DP_ISR_TxP | DP_ISR_TxE)); + DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START); + DP_OUT(base, DP_TBCL, len & 0xFF); + DP_OUT(base, DP_TBCH, len >> 8); + DP_OUT(base, DP_TPSR, start_page); + DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_TXPKT | DP_CR_START); + + dp->tx_started = true; +} + +/* + * This routine is called to send data to the hardware. It is known a-priori + * that there is free buffer space (dp->tx_next). + */ +static void +dp83902a_send(u8 *data, int total_len, u32 key) +{ + struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic; + u8 *base = dp->base; + int len, start_page, pkt_len, i, isr; +#if DEBUG & 4 + int dx; +#endif + + DEBUG_FUNCTION(); + + len = pkt_len = total_len; + if (pkt_len < IEEE_8023_MIN_FRAME) + pkt_len = IEEE_8023_MIN_FRAME; + + start_page = dp->tx_next; + if (dp->tx_next == dp->tx_buf1) { + dp->tx1 = start_page; + dp->tx1_len = pkt_len; + dp->tx1_key = key; + dp->tx_next = dp->tx_buf2; + } else { + dp->tx2 = start_page; + dp->tx2_len = pkt_len; + dp->tx2_key = key; + dp->tx_next = dp->tx_buf1; + } + +#if DEBUG & 5 + printf("TX prep page %d len %d\n", start_page, pkt_len); +#endif + + DP_OUT(base, DP_ISR, DP_ISR_RDC); /* Clear end of DMA */ + { + /* + * Dummy read. The manual sez something slightly different, + * but the code is extended a bit to do what Hitachi's monitor + * does (i.e., also read data). + */ + + __maybe_unused u16 tmp; + int len = 1; + + DP_OUT(base, DP_RSAL, 0x100 - len); + DP_OUT(base, DP_RSAH, (start_page - 1) & 0xff); + DP_OUT(base, DP_RBCL, len); + DP_OUT(base, DP_RBCH, 0); + DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_RDMA | DP_CR_START); + DP_IN_DATA(dp->data, tmp); + } + +#ifdef CYGHWR_NS_DP83902A_PLF_BROKEN_TX_DMA + /* + * Stall for a bit before continuing to work around random data + * corruption problems on some platforms. + */ + CYGACC_CALL_IF_DELAY_US(1); +#endif + + /* Send data to device buffer(s) */ + DP_OUT(base, DP_RSAL, 0); + DP_OUT(base, DP_RSAH, start_page); + DP_OUT(base, DP_RBCL, pkt_len & 0xFF); + DP_OUT(base, DP_RBCH, pkt_len >> 8); + DP_OUT(base, DP_CR, DP_CR_WDMA | DP_CR_START); + + /* Put data into buffer */ +#if DEBUG & 4 + printf(" sg buf %08lx len %08x\n ", (u32)data, len); + dx = 0; +#endif + while (len > 0) { +#if DEBUG & 4 + printf(" %02x", *data); + if (0 == (++dx % 16)) printf("\n "); +#endif + + DP_OUT_DATA(dp->data, *data++); + len--; + } +#if DEBUG & 4 + printf("\n"); +#endif + if (total_len < pkt_len) { +#if DEBUG & 4 + printf(" + %d bytes of padding\n", pkt_len - total_len); +#endif + /* Padding to 802.3 length was required */ + for (i = total_len; i < pkt_len;) { + i++; + DP_OUT_DATA(dp->data, 0); + } + } + +#ifdef CYGHWR_NS_DP83902A_PLF_BROKEN_TX_DMA + /* + * After last data write, delay for a bit before accessing the + * device again, or we may get random data corruption in the last + * datum (on some platforms). + */ + CYGACC_CALL_IF_DELAY_US(1); +#endif + + /* Wait for DMA to complete */ + do { + DP_IN(base, DP_ISR, isr); + } while ((isr & DP_ISR_RDC) == 0); + + /* Then disable DMA */ + DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START); + + /* Start transmit if not already going */ + if (!dp->tx_started) { + if (start_page == dp->tx1) { + dp->tx_int = 1; /* Expecting interrupt from BUF1 */ + } else { + dp->tx_int = 2; /* Expecting interrupt from BUF2 */ + } + dp83902a_start_xmit(start_page, pkt_len); + } +} + +/* + * This function is called when a packet has been received. It's job is + * to prepare to unload the packet from the hardware. Once the length of + * the packet is known, the upper layer of the driver can be told. When + * the upper layer is ready to unload the packet, the internal function + * 'dp83902a_recv' will be called to actually fetch it from the hardware. + */ +static void +dp83902a_RxEvent(void) +{ + struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic; + u8 *base = dp->base; + __maybe_unused u8 rsr; + u8 rcv_hdr[4]; + int i, len, pkt, cur; + + DEBUG_FUNCTION(); + + DP_IN(base, DP_RSR, rsr); + while (true) { + /* Read incoming packet header */ + DP_OUT(base, DP_CR, DP_CR_PAGE1 | DP_CR_NODMA | DP_CR_START); + DP_IN(base, DP_P1_CURP, cur); + DP_OUT(base, DP_P1_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START); + DP_IN(base, DP_BNDRY, pkt); + + pkt += 1; + if (pkt == dp->rx_buf_end) + pkt = dp->rx_buf_start; + + if (pkt == cur) { + break; + } + DP_OUT(base, DP_RBCL, sizeof(rcv_hdr)); + DP_OUT(base, DP_RBCH, 0); + DP_OUT(base, DP_RSAL, 0); + DP_OUT(base, DP_RSAH, pkt); + if (dp->rx_next == pkt) { + if (cur == dp->rx_buf_start) + DP_OUT(base, DP_BNDRY, dp->rx_buf_end - 1); + else + DP_OUT(base, DP_BNDRY, cur - 1); /* Update pointer */ + return; + } + dp->rx_next = pkt; + DP_OUT(base, DP_ISR, DP_ISR_RDC); /* Clear end of DMA */ + DP_OUT(base, DP_CR, DP_CR_RDMA | DP_CR_START); +#ifdef CYGHWR_NS_DP83902A_PLF_BROKEN_RX_DMA + CYGACC_CALL_IF_DELAY_US(10); +#endif + + /* read header (get data size)*/ + for (i = 0; i < sizeof(rcv_hdr);) { + DP_IN_DATA(dp->data, rcv_hdr[i++]); + } + +#if DEBUG & 5 + printf("rx hdr %02x %02x %02x %02x\n", + rcv_hdr[0], rcv_hdr[1], rcv_hdr[2], rcv_hdr[3]); +#endif + len = ((rcv_hdr[3] << 8) | rcv_hdr[2]) - sizeof(rcv_hdr); + + /* data read */ + uboot_push_packet_len(len); + + if (rcv_hdr[1] == dp->rx_buf_start) + DP_OUT(base, DP_BNDRY, dp->rx_buf_end - 1); + else + DP_OUT(base, DP_BNDRY, rcv_hdr[1] - 1); /* Update pointer */ + } +} + +/* + * This function is called as a result of the "eth_drv_recv()" call above. + * It's job is to actually fetch data for a packet from the hardware once + * memory buffers have been allocated for the packet. Note that the buffers + * may come in pieces, using a scatter-gather list. This allows for more + * efficient processing in the upper layers of the stack. + */ +static void +dp83902a_recv(u8 *data, int len) +{ + struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic; + u8 *base = dp->base; + int i, mlen; + u8 saved_char = 0; + bool saved; +#if DEBUG & 4 + int dx; +#endif + + DEBUG_FUNCTION(); + +#if DEBUG & 5 + printf("Rx packet %d length %d\n", dp->rx_next, len); +#endif + + /* Read incoming packet data */ + DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START); + DP_OUT(base, DP_RBCL, len & 0xFF); + DP_OUT(base, DP_RBCH, len >> 8); + DP_OUT(base, DP_RSAL, 4); /* Past header */ + DP_OUT(base, DP_RSAH, dp->rx_next); + DP_OUT(base, DP_ISR, DP_ISR_RDC); /* Clear end of DMA */ + DP_OUT(base, DP_CR, DP_CR_RDMA | DP_CR_START); +#ifdef CYGHWR_NS_DP83902A_PLF_BROKEN_RX_DMA + CYGACC_CALL_IF_DELAY_US(10); +#endif + + saved = false; + for (i = 0; i < 1; i++) { + if (data) { + mlen = len; +#if DEBUG & 4 + printf(" sg buf %08lx len %08x \n", (u32) data, mlen); + dx = 0; +#endif + while (0 < mlen) { + /* Saved byte from previous loop? */ + if (saved) { + *data++ = saved_char; + mlen--; + saved = false; + continue; + } + + { + u8 tmp; + DP_IN_DATA(dp->data, tmp); +#if DEBUG & 4 + printf(" %02x", tmp); + if (0 == (++dx % 16)) printf("\n "); +#endif + *data++ = tmp;; + mlen--; + } + } +#if DEBUG & 4 + printf("\n"); +#endif + } + } +} + +static void +dp83902a_TxEvent(void) +{ + struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic; + u8 *base = dp->base; + __maybe_unused u8 tsr; + u32 key; + + DEBUG_FUNCTION(); + + DP_IN(base, DP_TSR, tsr); + if (dp->tx_int == 1) { + key = dp->tx1_key; + dp->tx1 = 0; + } else { + key = dp->tx2_key; + dp->tx2 = 0; + } + /* Start next packet if one is ready */ + dp->tx_started = false; + if (dp->tx1) { + dp83902a_start_xmit(dp->tx1, dp->tx1_len); + dp->tx_int = 1; + } else if (dp->tx2) { + dp83902a_start_xmit(dp->tx2, dp->tx2_len); + dp->tx_int = 2; + } else { + dp->tx_int = 0; + } + /* Tell higher level we sent this packet */ + uboot_push_tx_done(key, 0); +} + +/* + * Read the tally counters to clear them. Called in response to a CNT + * interrupt. + */ +static void +dp83902a_ClearCounters(void) +{ + struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic; + u8 *base = dp->base; + __maybe_unused u8 cnt1, cnt2, cnt3; + + DP_IN(base, DP_FER, cnt1); + DP_IN(base, DP_CER, cnt2); + DP_IN(base, DP_MISSED, cnt3); + DP_OUT(base, DP_ISR, DP_ISR_CNT); +} + +/* + * Deal with an overflow condition. This code follows the procedure set + * out in section 7.0 of the datasheet. + */ +static void +dp83902a_Overflow(void) +{ + struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *)&nic; + u8 *base = dp->base; + u8 isr; + + /* Issue a stop command and wait 1.6ms for it to complete. */ + DP_OUT(base, DP_CR, DP_CR_STOP | DP_CR_NODMA); + CYGACC_CALL_IF_DELAY_US(1600); + + /* Clear the remote byte counter registers. */ + DP_OUT(base, DP_RBCL, 0); + DP_OUT(base, DP_RBCH, 0); + + /* Enter loopback mode while we clear the buffer. */ + DP_OUT(base, DP_TCR, DP_TCR_LOCAL); + DP_OUT(base, DP_CR, DP_CR_START | DP_CR_NODMA); + + /* + * Read in as many packets as we can and acknowledge any and receive + * interrupts. Since the buffer has overflowed, a receive event of + * some kind will have occured. + */ + dp83902a_RxEvent(); + DP_OUT(base, DP_ISR, DP_ISR_RxP|DP_ISR_RxE); + + /* Clear the overflow condition and leave loopback mode. */ + DP_OUT(base, DP_ISR, DP_ISR_OFLW); + DP_OUT(base, DP_TCR, DP_TCR_NORMAL); + + /* + * If a transmit command was issued, but no transmit event has occured, + * restart it here. + */ + DP_IN(base, DP_ISR, isr); + if (dp->tx_started && !(isr & (DP_ISR_TxP|DP_ISR_TxE))) { + DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_TXPKT | DP_CR_START); + } +} + +static void +dp83902a_poll(void) +{ + struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic; + u8 *base = dp->base; + u8 isr; + + DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE0 | DP_CR_START); + DP_IN(base, DP_ISR, isr); + while (0 != isr) { + /* + * The CNT interrupt triggers when the MSB of one of the error + * counters is set. We don't much care about these counters, but + * we should read their values to reset them. + */ + if (isr & DP_ISR_CNT) { + dp83902a_ClearCounters(); + } + /* + * Check for overflow. It's a special case, since there's a + * particular procedure that must be followed to get back into + * a running state.a + */ + if (isr & DP_ISR_OFLW) { + dp83902a_Overflow(); + } else { + /* + * Other kinds of interrupts can be acknowledged simply by + * clearing the relevant bits of the ISR. Do that now, then + * handle the interrupts we care about. + */ + DP_OUT(base, DP_ISR, isr); /* Clear set bits */ + if (!dp->running) break; /* Is this necessary? */ + /* + * Check for tx_started on TX event since these may happen + * spuriously it seems. + */ + if (isr & (DP_ISR_TxP|DP_ISR_TxE) && dp->tx_started) { + dp83902a_TxEvent(); + } + if (isr & (DP_ISR_RxP|DP_ISR_RxE)) { + dp83902a_RxEvent(); + } + } + DP_IN(base, DP_ISR, isr); + } +} + + +/* U-boot specific routines */ +static u8 *pbuf = NULL; + +static int pkey = -1; +static int initialized = 0; + +void uboot_push_packet_len(int len) { + PRINTK("pushed len = %d\n", len); + if (len >= 2000) { + printf("NE2000: packet too big\n"); + return; + } + dp83902a_recv(&pbuf[0], len); + + /*Just pass it to the upper layer*/ + net_process_received_packet(&pbuf[0], len); +} + +void uboot_push_tx_done(int key, int val) { + PRINTK("pushed key = %d\n", key); + pkey = key; +} + +/** + * Setup the driver and init MAC address according to doc/README.enetaddr + * Called by ne2k_register() before registering the driver @eth layer + * + * @param struct ethdevice of this instance of the driver for dev->enetaddr + * @return 0 on success, -1 on error (causing caller to print error msg) + */ +static int ne2k_setup_driver(struct eth_device *dev) +{ + PRINTK("### ne2k_setup_driver\n"); + + if (!pbuf) { + pbuf = malloc(2000); + if (!pbuf) { + printf("Cannot allocate rx buffer\n"); + return -1; + } + } + +#ifdef CONFIG_DRIVER_NE2000_CCR + { + vu_char *p = (vu_char *) CONFIG_DRIVER_NE2000_CCR; + + PRINTK("CCR before is %x\n", *p); + *p = CONFIG_DRIVER_NE2000_VAL; + PRINTK("CCR after is %x\n", *p); + } +#endif + + nic.base = (u8 *) CONFIG_DRIVER_NE2000_BASE; + + nic.data = nic.base + DP_DATA; + nic.tx_buf1 = START_PG; + nic.tx_buf2 = START_PG2; + nic.rx_buf_start = RX_START; + nic.rx_buf_end = RX_END; + + /* + * According to doc/README.enetaddr, drivers shall give priority + * to the MAC address value in the environment, so we do not read + * it from the prom or eeprom if it is specified in the environment. + */ + if (!eth_getenv_enetaddr("ethaddr", dev->enetaddr)) { + /* If the MAC address is not in the environment, get it: */ + if (!get_prom(dev->enetaddr, nic.base)) /* get MAC from prom */ + dp83902a_init(dev->enetaddr); /* fallback: seeprom */ + /* And write it into the environment otherwise eth_write_hwaddr + * returns -1 due to eth_getenv_enetaddr_by_index() failing, + * and this causes "Warning: failed to set MAC address", and + * cmd_bdinfo has no ethaddr value which it can show: */ + eth_setenv_enetaddr("ethaddr", dev->enetaddr); + } + return 0; +} + +static int ne2k_init(struct eth_device *dev, bd_t *bd) +{ + dp83902a_start(dev->enetaddr); + initialized = 1; + return 0; +} + +static void ne2k_halt(struct eth_device *dev) +{ + debug("### ne2k_halt\n"); + if(initialized) + dp83902a_stop(); + initialized = 0; +} + +static int ne2k_recv(struct eth_device *dev) +{ + dp83902a_poll(); + return 1; +} + +static int ne2k_send(struct eth_device *dev, void *packet, int length) +{ + int tmo; + + debug("### ne2k_send\n"); + + pkey = -1; + + dp83902a_send((u8 *) packet, length, 666); + tmo = get_timer (0) + TOUT * CONFIG_SYS_HZ; + while(1) { + dp83902a_poll(); + if (pkey != -1) { + PRINTK("Packet sucesfully sent\n"); + return 0; + } + if (get_timer (0) >= tmo) { + printf("transmission error (timoeut)\n"); + return 0; + } + + } + return 0; +} + +/** + * Setup the driver for use and register it with the eth layer + * @return 0 on success, -1 on error (causing caller to print error msg) + */ +int ne2k_register(void) +{ + struct eth_device *dev; + + dev = calloc(sizeof(*dev), 1); + if (dev == NULL) + return -1; + + if (ne2k_setup_driver(dev)) + return -1; + + dev->init = ne2k_init; + dev->halt = ne2k_halt; + dev->send = ne2k_send; + dev->recv = ne2k_recv; + + sprintf(dev->name, "NE2000"); + + return eth_register(dev); +} diff --git a/sources/uboot-be550/drivers/net/ne2000_base.h b/sources/uboot-be550/drivers/net/ne2000_base.h new file mode 100644 index 00000000..eee0956f --- /dev/null +++ b/sources/uboot-be550/drivers/net/ne2000_base.h @@ -0,0 +1,304 @@ +/* +Ported to U-Boot by Christian Pellegrin + +Based on sources from the Linux kernel (pcnet_cs.c, 8390.h) and +eCOS(if_dp83902a.c, if_dp83902a.h). Both of these 2 wonderful world +are GPL, so this is, of course, GPL. + + +========================================================================== + + dev/dp83902a.h + + National Semiconductor DP83902a ethernet chip + +========================================================================== +####ECOSGPLCOPYRIGHTBEGIN#### + ------------------------------------------- + This file is part of eCos, the Embedded Configurable Operating System. + Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. + + eCos is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License as published by the Free + Software Foundation; either version 2 or (at your option) any later version. + + eCos is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + for more details. + + You should have received a copy of the GNU General Public License along + with eCos; if not, write to the Free Software Foundation, Inc., + 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. + + As a special exception, if other files instantiate templates or use macros + or inline functions from this file, or you compile this file and link it + with other works to produce a work based on this file, this file does not + by itself cause the resulting work to be covered by the GNU General Public + License. However the source code for this file must still be made available + in accordance with section (3) of the GNU General Public License. + + This exception does not invalidate any other reasons why a work based on + this file might be covered by the GNU General Public License. + + Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. + at http://sources.redhat.com/ecos/ecos-license/ + ------------------------------------------- +####ECOSGPLCOPYRIGHTEND#### +####BSDCOPYRIGHTBEGIN#### + + ------------------------------------------- + + Portions of this software may have been derived from OpenBSD or other sources, + and are covered by the appropriate copyright disclaimers included herein. + + ------------------------------------------- + +####BSDCOPYRIGHTEND#### +========================================================================== +#####DESCRIPTIONBEGIN#### + + Author(s): gthomas + Contributors: gthomas, jskov + Date: 2001-06-13 + Purpose: + Description: + +####DESCRIPTIONEND#### + +========================================================================== + +*/ + +/* + ------------------------------------------------------------------------ + Macros for accessing DP registers + These can be overridden by the platform header +*/ + +#ifndef __NE2000_BASE_H__ +#define __NE2000_BASE_H__ + +/* + * Debugging details + * + * Set to perms of: + * 0 disables all debug output + * 1 for process debug output + * 2 for added data IO output: get_reg, put_reg + * 4 for packet allocation/free output + * 8 for only startup status, so we can tell we're installed OK + */ +#if 0 +#define DEBUG 0xf +#else +#define DEBUG 0 +#endif + +#if DEBUG & 1 +#define DEBUG_FUNCTION() do { printf("%s\n", __FUNCTION__); } while (0) +#define DEBUG_LINE() do { printf("%d\n", __LINE__); } while (0) +#define PRINTK(args...) printf(args) +#else +#define DEBUG_FUNCTION() do {} while(0) +#define DEBUG_LINE() do {} while(0) +#define PRINTK(args...) +#endif + +/* timeout for tx/rx in s */ +#define TOUT 5 +/* Ether MAC address size */ +#define ETHER_ADDR_LEN 6 + + +#define CYGHWR_NS_DP83902A_PLF_BROKEN_TX_DMA 1 +#define CYGACC_CALL_IF_DELAY_US(X) udelay(X) + +/* H/W infomation struct */ +typedef struct hw_info_t { + u32 offset; + u8 a0, a1, a2; + u32 flags; +} hw_info_t; + +typedef struct dp83902a_priv_data { + u8* base; + u8* data; + u8* reset; + int tx_next; /* First free Tx page */ + int tx_int; /* Expecting interrupt from this buffer */ + int rx_next; /* First free Rx page */ + int tx1, tx2; /* Page numbers for Tx buffers */ + u32 tx1_key, tx2_key; /* Used to ack when packet sent */ + int tx1_len, tx2_len; + bool tx_started, running, hardwired_esa; + u8 esa[6]; + void* plf_priv; + + /* Buffer allocation */ + int tx_buf1, tx_buf2; + int rx_buf_start, rx_buf_end; +} dp83902a_priv_data_t; + +/* ------------------------------------------------------------------------ */ +/* Register offsets */ + +#define DP_CR 0x00 +#define DP_CLDA0 0x01 +#define DP_PSTART 0x01 /* write */ +#define DP_CLDA1 0x02 +#define DP_PSTOP 0x02 /* write */ +#define DP_BNDRY 0x03 +#define DP_TSR 0x04 +#define DP_TPSR 0x04 /* write */ +#define DP_NCR 0x05 +#define DP_TBCL 0x05 /* write */ +#define DP_FIFO 0x06 +#define DP_TBCH 0x06 /* write */ +#define DP_ISR 0x07 +#define DP_CRDA0 0x08 +#define DP_RSAL 0x08 /* write */ +#define DP_CRDA1 0x09 +#define DP_RSAH 0x09 /* write */ +#define DP_RBCL 0x0a /* write */ +#define DP_RBCH 0x0b /* write */ +#define DP_RSR 0x0c +#define DP_RCR 0x0c /* write */ +#define DP_FER 0x0d +#define DP_TCR 0x0d /* write */ +#define DP_CER 0x0e +#define DP_DCR 0x0e /* write */ +#define DP_MISSED 0x0f +#define DP_IMR 0x0f /* write */ +#define DP_DATAPORT 0x10 /* "eprom" data port */ + +#define DP_P1_CR 0x00 +#define DP_P1_PAR0 0x01 +#define DP_P1_PAR1 0x02 +#define DP_P1_PAR2 0x03 +#define DP_P1_PAR3 0x04 +#define DP_P1_PAR4 0x05 +#define DP_P1_PAR5 0x06 +#define DP_P1_CURP 0x07 +#define DP_P1_MAR0 0x08 +#define DP_P1_MAR1 0x09 +#define DP_P1_MAR2 0x0a +#define DP_P1_MAR3 0x0b +#define DP_P1_MAR4 0x0c +#define DP_P1_MAR5 0x0d +#define DP_P1_MAR6 0x0e +#define DP_P1_MAR7 0x0f + +#define DP_P2_CR 0x00 +#define DP_P2_PSTART 0x01 +#define DP_P2_CLDA0 0x01 /* write */ +#define DP_P2_PSTOP 0x02 +#define DP_P2_CLDA1 0x02 /* write */ +#define DP_P2_RNPP 0x03 +#define DP_P2_TPSR 0x04 +#define DP_P2_LNPP 0x05 +#define DP_P2_ACH 0x06 +#define DP_P2_ACL 0x07 +#define DP_P2_RCR 0x0c +#define DP_P2_TCR 0x0d +#define DP_P2_DCR 0x0e +#define DP_P2_IMR 0x0f + +/* Command register - common to all pages */ + +#define DP_CR_STOP 0x01 /* Stop: software reset */ +#define DP_CR_START 0x02 /* Start: initialize device */ +#define DP_CR_TXPKT 0x04 /* Transmit packet */ +#define DP_CR_RDMA 0x08 /* Read DMA (recv data from device) */ +#define DP_CR_WDMA 0x10 /* Write DMA (send data to device) */ +#define DP_CR_SEND 0x18 /* Send packet */ +#define DP_CR_NODMA 0x20 /* Remote (or no) DMA */ +#define DP_CR_PAGE0 0x00 /* Page select */ +#define DP_CR_PAGE1 0x40 +#define DP_CR_PAGE2 0x80 +#define DP_CR_PAGEMSK 0x3F /* Used to mask out page bits */ + +/* Data configuration register */ + +#define DP_DCR_WTS 0x01 /* 1=16 bit word transfers */ +#define DP_DCR_BOS 0x02 /* 1=Little Endian */ +#define DP_DCR_LAS 0x04 /* 1=Single 32 bit DMA mode */ +#define DP_DCR_LS 0x08 /* 1=normal mode, 0=loopback */ +#define DP_DCR_ARM 0x10 /* 0=no send command (program I/O) */ +#define DP_DCR_FIFO_1 0x00 /* FIFO threshold */ +#define DP_DCR_FIFO_2 0x20 +#define DP_DCR_FIFO_4 0x40 +#define DP_DCR_FIFO_6 0x60 + +#define DP_DCR_INIT (DP_DCR_LS|DP_DCR_FIFO_4) + +/* Interrupt status register */ + +#define DP_ISR_RxP 0x01 /* Packet received */ +#define DP_ISR_TxP 0x02 /* Packet transmitted */ +#define DP_ISR_RxE 0x04 /* Receive error */ +#define DP_ISR_TxE 0x08 /* Transmit error */ +#define DP_ISR_OFLW 0x10 /* Receive overflow */ +#define DP_ISR_CNT 0x20 /* Tally counters need emptying */ +#define DP_ISR_RDC 0x40 /* Remote DMA complete */ +#define DP_ISR_RESET 0x80 /* Device has reset (shutdown, error) */ + +/* Interrupt mask register */ + +#define DP_IMR_RxP 0x01 /* Packet received */ +#define DP_IMR_TxP 0x02 /* Packet transmitted */ +#define DP_IMR_RxE 0x04 /* Receive error */ +#define DP_IMR_TxE 0x08 /* Transmit error */ +#define DP_IMR_OFLW 0x10 /* Receive overflow */ +#define DP_IMR_CNT 0x20 /* Tall counters need emptying */ +#define DP_IMR_RDC 0x40 /* Remote DMA complete */ + +#define DP_IMR_All 0x3F /* Everything but remote DMA */ + +/* Receiver control register */ + +#define DP_RCR_SEP 0x01 /* Save bad(error) packets */ +#define DP_RCR_AR 0x02 /* Accept runt packets */ +#define DP_RCR_AB 0x04 /* Accept broadcast packets */ +#define DP_RCR_AM 0x08 /* Accept multicast packets */ +#define DP_RCR_PROM 0x10 /* Promiscuous mode */ +#define DP_RCR_MON 0x20 /* Monitor mode - 1=accept no packets */ + +/* Receiver status register */ + +#define DP_RSR_RxP 0x01 /* Packet received */ +#define DP_RSR_CRC 0x02 /* CRC error */ +#define DP_RSR_FRAME 0x04 /* Framing error */ +#define DP_RSR_FO 0x08 /* FIFO overrun */ +#define DP_RSR_MISS 0x10 /* Missed packet */ +#define DP_RSR_PHY 0x20 /* 0=pad match, 1=mad match */ +#define DP_RSR_DIS 0x40 /* Receiver disabled */ +#define DP_RSR_DFR 0x80 /* Receiver processing deferred */ + +/* Transmitter control register */ + +#define DP_TCR_NOCRC 0x01 /* 1=inhibit CRC */ +#define DP_TCR_NORMAL 0x00 /* Normal transmitter operation */ +#define DP_TCR_LOCAL 0x02 /* Internal NIC loopback */ +#define DP_TCR_INLOOP 0x04 /* Full internal loopback */ +#define DP_TCR_OUTLOOP 0x08 /* External loopback */ +#define DP_TCR_ATD 0x10 /* Auto transmit disable */ +#define DP_TCR_OFFSET 0x20 /* Collision offset adjust */ + +/* Transmit status register */ + +#define DP_TSR_TxP 0x01 /* Packet transmitted */ +#define DP_TSR_COL 0x04 /* Collision (at least one) */ +#define DP_TSR_ABT 0x08 /* Aborted because of too many collisions */ +#define DP_TSR_CRS 0x10 /* Lost carrier */ +#define DP_TSR_FU 0x20 /* FIFO underrun */ +#define DP_TSR_CDH 0x40 /* Collision Detect Heartbeat */ +#define DP_TSR_OWC 0x80 /* Collision outside normal window */ + +#define IEEE_8023_MAX_FRAME 1518 /* Largest possible ethernet frame */ +#define IEEE_8023_MIN_FRAME 64 /* Smallest possible ethernet frame */ + +/* Functions */ +int get_prom(u8* mac_addr, u8* base_addr); + +#endif /* __NE2000_BASE_H__ */ diff --git a/sources/uboot-be550/drivers/net/netconsole.c b/sources/uboot-be550/drivers/net/netconsole.c new file mode 100644 index 00000000..35000475 --- /dev/null +++ b/sources/uboot-be550/drivers/net/netconsole.c @@ -0,0 +1,343 @@ +/* + * (C) Copyright 2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#ifndef CONFIG_NETCONSOLE_BUFFER_SIZE +#define CONFIG_NETCONSOLE_BUFFER_SIZE 512 +#endif + +static char input_buffer[CONFIG_NETCONSOLE_BUFFER_SIZE]; +static int input_size; /* char count in input buffer */ +static int input_offset; /* offset to valid chars in input buffer */ +static int input_recursion; +static int output_recursion; +static int net_timeout; +static uchar nc_ether[6]; /* server enet address */ +static struct in_addr nc_ip; /* server ip */ +static short nc_out_port; /* target output port */ +static short nc_in_port; /* source input port */ +static const char *output_packet; /* used by first send udp */ +static int output_packet_len; +/* + * Start with a default last protocol. + * We are only interested in NETCONS or not. + */ +enum proto_t net_loop_last_protocol = BOOTP; + +static void nc_wait_arp_handler(uchar *pkt, unsigned dest, + struct in_addr sip, unsigned src, + unsigned len) +{ + net_set_state(NETLOOP_SUCCESS); /* got arp reply - quit net loop */ +} + +static void nc_handler(uchar *pkt, unsigned dest, struct in_addr sip, + unsigned src, unsigned len) +{ + if (input_size) + net_set_state(NETLOOP_SUCCESS); /* got input - quit net loop */ +} + +static void nc_timeout_handler(void) +{ + net_set_state(NETLOOP_SUCCESS); +} + +static int is_broadcast(struct in_addr ip) +{ + static struct in_addr netmask; + static struct in_addr our_ip; + static int env_changed_id; + int env_id = get_env_id(); + + /* update only when the environment has changed */ + if (env_changed_id != env_id) { + netmask = getenv_ip("netmask"); + our_ip = getenv_ip("ipaddr"); + + env_changed_id = env_id; + } + + return (ip.s_addr == ~0 || /* 255.255.255.255 (global bcast) */ + ((netmask.s_addr & our_ip.s_addr) == + (netmask.s_addr & ip.s_addr) && /* on the same net and */ + (netmask.s_addr | ip.s_addr) == ~0)); /* bcast to our net */ +} + +static int refresh_settings_from_env(void) +{ + const char *p; + static int env_changed_id; + int env_id = get_env_id(); + + /* update only when the environment has changed */ + if (env_changed_id != env_id) { + if (getenv("ncip")) { + nc_ip = getenv_ip("ncip"); + if (!nc_ip.s_addr) + return -1; /* ncip is 0.0.0.0 */ + p = strchr(getenv("ncip"), ':'); + if (p != NULL) { + nc_out_port = simple_strtoul(p + 1, NULL, 10); + nc_in_port = nc_out_port; + } + } else { + nc_ip.s_addr = ~0; /* ncip is not set, so broadcast */ + } + + p = getenv("ncoutport"); + if (p != NULL) + nc_out_port = simple_strtoul(p, NULL, 10); + p = getenv("ncinport"); + if (p != NULL) + nc_in_port = simple_strtoul(p, NULL, 10); + + if (is_broadcast(nc_ip)) + /* broadcast MAC address */ + memset(nc_ether, 0xff, sizeof(nc_ether)); + else + /* force arp request */ + memset(nc_ether, 0, sizeof(nc_ether)); + } + return 0; +} + +/** + * Called from net_loop in net/net.c before each packet + */ +void nc_start(void) +{ + refresh_settings_from_env(); + if (!output_packet_len || memcmp(nc_ether, net_null_ethaddr, 6)) { + /* going to check for input packet */ + net_set_udp_handler(nc_handler); + net_set_timeout_handler(net_timeout, nc_timeout_handler); + } else { + /* send arp request */ + uchar *pkt; + net_set_arp_handler(nc_wait_arp_handler); + pkt = (uchar *)net_tx_packet + net_eth_hdr_size() + + IP_UDP_HDR_SIZE; + memcpy(pkt, output_packet, output_packet_len); + net_send_udp_packet(nc_ether, nc_ip, nc_out_port, nc_in_port, + output_packet_len); + } +} + +int nc_input_packet(uchar *pkt, struct in_addr src_ip, unsigned dest_port, + unsigned src_port, unsigned len) +{ + int end, chunk; + + if (dest_port != nc_in_port || !len) + return 0; /* not for us */ + + if (src_ip.s_addr != nc_ip.s_addr && !is_broadcast(nc_ip)) + return 0; /* not from our client */ + + debug_cond(DEBUG_DEV_PKT, "input: \"%*.*s\"\n", len, len, pkt); + + if (input_size == sizeof(input_buffer)) + return 1; /* no space */ + if (len > sizeof(input_buffer) - input_size) + len = sizeof(input_buffer) - input_size; + + end = input_offset + input_size; + if (end > sizeof(input_buffer)) + end -= sizeof(input_buffer); + + chunk = len; + if (end + len > sizeof(input_buffer)) { + chunk = sizeof(input_buffer) - end; + memcpy(input_buffer, pkt + chunk, len - chunk); + } + memcpy(input_buffer + end, pkt, chunk); + + input_size += len; + + return 1; +} + +static void nc_send_packet(const char *buf, int len) +{ +#ifdef CONFIG_DM_ETH + struct udevice *eth; +#else + struct eth_device *eth; +#endif + int inited = 0; + uchar *pkt; + uchar *ether; + struct in_addr ip; + + debug_cond(DEBUG_DEV_PKT, "output: \"%*.*s\"\n", len, len, buf); + + eth = eth_get_dev(); + if (eth == NULL) + return; + + if (!memcmp(nc_ether, net_null_ethaddr, 6)) { + if (eth_is_active(eth)) + return; /* inside net loop */ + output_packet = buf; + output_packet_len = len; + input_recursion = 1; + net_loop(NETCONS); /* wait for arp reply and send packet */ + input_recursion = 0; + output_packet_len = 0; + return; + } + + if (!eth_is_active(eth)) { + if (eth_is_on_demand_init()) { + if (eth_init() < 0) + return; + eth_set_last_protocol(NETCONS); + } else { + eth_init_state_only(); + } + + inited = 1; + } + pkt = (uchar *)net_tx_packet + net_eth_hdr_size() + IP_UDP_HDR_SIZE; + memcpy(pkt, buf, len); + ether = nc_ether; + ip = nc_ip; + net_send_udp_packet(ether, ip, nc_out_port, nc_in_port, len); + + if (inited) { + if (eth_is_on_demand_init()) + eth_halt(); + else + eth_halt_state_only(); + } +} + +static int nc_stdio_start(struct stdio_dev *dev) +{ + int retval; + + nc_out_port = 6666; /* default port */ + nc_in_port = nc_out_port; + + retval = refresh_settings_from_env(); + if (retval != 0) + return retval; + + /* + * Initialize the static IP settings and buffer pointers + * incase we call net_send_udp_packet before net_loop + */ + net_init(); + + return 0; +} + +static void nc_stdio_putc(struct stdio_dev *dev, char c) +{ + if (output_recursion) + return; + output_recursion = 1; + + nc_send_packet(&c, 1); + + output_recursion = 0; +} + +static void nc_stdio_puts(struct stdio_dev *dev, const char *s) +{ + int len; + + if (output_recursion) + return; + output_recursion = 1; + + len = strlen(s); + while (len) { + int send_len = min(len, (int)sizeof(input_buffer)); + nc_send_packet(s, send_len); + len -= send_len; + s += send_len; + } + + output_recursion = 0; +} + +static int nc_stdio_getc(struct stdio_dev *dev) +{ + uchar c; + + input_recursion = 1; + + net_timeout = 0; /* no timeout */ + while (!input_size) + net_loop(NETCONS); + + input_recursion = 0; + + c = input_buffer[input_offset++]; + + if (input_offset >= sizeof(input_buffer)) + input_offset -= sizeof(input_buffer); + input_size--; + + return c; +} + +static int nc_stdio_tstc(struct stdio_dev *dev) +{ +#ifdef CONFIG_DM_ETH + struct udevice *eth; +#else + struct eth_device *eth; +#endif + + if (input_recursion) + return 0; + + if (input_size) + return 1; + + eth = eth_get_dev(); + if (eth_is_active(eth)) + return 0; /* inside net loop */ + + input_recursion = 1; + + net_timeout = 1; + net_loop(NETCONS); /* kind of poll */ + + input_recursion = 0; + + return input_size != 0; +} + +int drv_nc_init(void) +{ + struct stdio_dev dev; + int rc; + + memset(&dev, 0, sizeof(dev)); + + strcpy(dev.name, "nc"); + dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT; + dev.start = nc_stdio_start; + dev.putc = nc_stdio_putc; + dev.puts = nc_stdio_puts; + dev.getc = nc_stdio_getc; + dev.tstc = nc_stdio_tstc; + + rc = stdio_register(&dev); + + return (rc == 0) ? 1 : rc; +} diff --git a/sources/uboot-be550/drivers/net/ns8382x.c b/sources/uboot-be550/drivers/net/ns8382x.c new file mode 100644 index 00000000..f941c15b --- /dev/null +++ b/sources/uboot-be550/drivers/net/ns8382x.c @@ -0,0 +1,853 @@ +/* + ns8382x.c: A U-Boot driver for the NatSemi DP8382[01]. + ported by: Mark A. Rakes (mark_rakes@vivato.net) + + Adapted from: + 1. an Etherboot driver for DP8381[56] written by: + Copyright (C) 2001 Entity Cyber, Inc. + + This development of this Etherboot driver was funded by + Sicom Systems: http://www.sicompos.com/ + + Author: Marty Connor (mdc@thinguin.org) + Adapted from a Linux driver which was written by Donald Becker + + This software may be used and distributed according to the terms + of the GNU Public License (GPL), incorporated herein by reference. + + 2. A Linux driver by Donald Becker, ns820.c: + Written/copyright 1999-2002 by Donald Becker. + + This software may be used and distributed according to the terms of + the GNU General Public License (GPL), incorporated herein by reference. + Drivers based on or derived from this code fall under the GPL and must + retain the authorship, copyright and license notice. This file is not + a complete program and may only be used when the entire operating + system is licensed under the GPL. License for under other terms may be + available. Contact the original author for details. + + The original author may be reached as becker@scyld.com, or at + Scyld Computing Corporation + 410 Severn Ave., Suite 210 + Annapolis MD 21403 + + Support information and updates available at + http://www.scyld.com/network/netsemi.html + + Datasheets available from: + http://www.national.com/pf/DP/DP83820.html + http://www.national.com/pf/DP/DP83821.html +*/ + +/* Revision History + * October 2002 mar 1.0 + * Initial U-Boot Release. + * Tested with Netgear GA622T (83820) + * and SMC9452TX (83821) + * NOTE: custom boards with these chips may (likely) require + * a programmed EEPROM device (if present) in order to work + * correctly. +*/ + +/* Includes */ +#include +#include +#include +#include +#include +#include + +/* defines */ +#define DSIZE 0x00000FFF +#define ETH_ALEN 6 +#define CRC_SIZE 4 +#define TOUT_LOOP 500000 +#define TX_BUF_SIZE 1536 +#define RX_BUF_SIZE 1536 +#define NUM_RX_DESC 4 /* Number of Rx descriptor registers. */ + +enum register_offsets { + ChipCmd = 0x00, + ChipConfig = 0x04, + EECtrl = 0x08, + IntrMask = 0x14, + IntrEnable = 0x18, + TxRingPtr = 0x20, + TxRingPtrHi = 0x24, + TxConfig = 0x28, + RxRingPtr = 0x30, + RxRingPtrHi = 0x34, + RxConfig = 0x38, + PriQueue = 0x3C, + RxFilterAddr = 0x48, + RxFilterData = 0x4C, + ClkRun = 0xCC, + PCIPM = 0x44, +}; + +enum ChipCmdBits { + ChipReset = 0x100, + RxReset = 0x20, + TxReset = 0x10, + RxOff = 0x08, + RxOn = 0x04, + TxOff = 0x02, + TxOn = 0x01 +}; + +enum ChipConfigBits { + LinkSts = 0x80000000, + GigSpeed = 0x40000000, + HundSpeed = 0x20000000, + FullDuplex = 0x10000000, + TBIEn = 0x01000000, + Mode1000 = 0x00400000, + T64En = 0x00004000, + D64En = 0x00001000, + M64En = 0x00000800, + PhyRst = 0x00000400, + PhyDis = 0x00000200, + ExtStEn = 0x00000100, + BEMode = 0x00000001, +}; +#define SpeedStatus_Polarity ( GigSpeed | HundSpeed | FullDuplex) + +enum TxConfig_bits { + TxDrthMask = 0x000000ff, + TxFlthMask = 0x0000ff00, + TxMxdmaMask = 0x00700000, + TxMxdma_8 = 0x00100000, + TxMxdma_16 = 0x00200000, + TxMxdma_32 = 0x00300000, + TxMxdma_64 = 0x00400000, + TxMxdma_128 = 0x00500000, + TxMxdma_256 = 0x00600000, + TxMxdma_512 = 0x00700000, + TxMxdma_1024 = 0x00000000, + TxCollRetry = 0x00800000, + TxAutoPad = 0x10000000, + TxMacLoop = 0x20000000, + TxHeartIgn = 0x40000000, + TxCarrierIgn = 0x80000000 +}; + +enum RxConfig_bits { + RxDrthMask = 0x0000003e, + RxMxdmaMask = 0x00700000, + RxMxdma_8 = 0x00100000, + RxMxdma_16 = 0x00200000, + RxMxdma_32 = 0x00300000, + RxMxdma_64 = 0x00400000, + RxMxdma_128 = 0x00500000, + RxMxdma_256 = 0x00600000, + RxMxdma_512 = 0x00700000, + RxMxdma_1024 = 0x00000000, + RxAcceptLenErr = 0x04000000, + RxAcceptLong = 0x08000000, + RxAcceptTx = 0x10000000, + RxStripCRC = 0x20000000, + RxAcceptRunt = 0x40000000, + RxAcceptErr = 0x80000000, +}; + +/* Bits in the RxMode register. */ +enum rx_mode_bits { + RxFilterEnable = 0x80000000, + AcceptAllBroadcast = 0x40000000, + AcceptAllMulticast = 0x20000000, + AcceptAllUnicast = 0x10000000, + AcceptPerfectMatch = 0x08000000, +}; + +typedef struct _BufferDesc { + u32 link; + u32 bufptr; + vu_long cmdsts; + u32 extsts; /*not used here */ +} BufferDesc; + +/* Bits in network_desc.status */ +enum desc_status_bits { + DescOwn = 0x80000000, DescMore = 0x40000000, DescIntr = 0x20000000, + DescNoCRC = 0x10000000, DescPktOK = 0x08000000, + DescSizeMask = 0xfff, + + DescTxAbort = 0x04000000, DescTxFIFO = 0x02000000, + DescTxCarrier = 0x01000000, DescTxDefer = 0x00800000, + DescTxExcDefer = 0x00400000, DescTxOOWCol = 0x00200000, + DescTxExcColl = 0x00100000, DescTxCollCount = 0x000f0000, + + DescRxAbort = 0x04000000, DescRxOver = 0x02000000, + DescRxDest = 0x01800000, DescRxLong = 0x00400000, + DescRxRunt = 0x00200000, DescRxInvalid = 0x00100000, + DescRxCRC = 0x00080000, DescRxAlign = 0x00040000, + DescRxLoop = 0x00020000, DesRxColl = 0x00010000, +}; + +/* Bits in MEAR */ +enum mii_reg_bits { + MDIO_ShiftClk = 0x0040, + MDIO_EnbOutput = 0x0020, + MDIO_Data = 0x0010, +}; + +/* PHY Register offsets. */ +enum phy_reg_offsets { + BMCR = 0x00, + BMSR = 0x01, + PHYIDR1 = 0x02, + PHYIDR2 = 0x03, + ANAR = 0x04, + KTCR = 0x09, +}; + +/* basic mode control register bits */ +enum bmcr_bits { + Bmcr_Reset = 0x8000, + Bmcr_Loop = 0x4000, + Bmcr_Speed0 = 0x2000, + Bmcr_AutoNegEn = 0x1000, /*if set ignores Duplex, Speed[01] */ + Bmcr_RstAutoNeg = 0x0200, + Bmcr_Duplex = 0x0100, + Bmcr_Speed1 = 0x0040, + Bmcr_Force10H = 0x0000, + Bmcr_Force10F = 0x0100, + Bmcr_Force100H = 0x2000, + Bmcr_Force100F = 0x2100, + Bmcr_Force1000H = 0x0040, + Bmcr_Force1000F = 0x0140, +}; + +/* auto negotiation advertisement register */ +enum anar_bits { + anar_adv_100F = 0x0100, + anar_adv_100H = 0x0080, + anar_adv_10F = 0x0040, + anar_adv_10H = 0x0020, + anar_ieee_8023 = 0x0001, +}; + +/* 1K-base T control register */ +enum ktcr_bits { + ktcr_adv_1000H = 0x0100, + ktcr_adv_1000F = 0x0200, +}; + +/* Globals */ +static u32 SavedClkRun; +static unsigned int cur_rx; +static unsigned int rx_config; +static unsigned int tx_config; + +/* Note: transmit and receive buffers and descriptors must be + long long word aligned */ +static BufferDesc txd __attribute__ ((aligned(8))); +static BufferDesc rxd[NUM_RX_DESC] __attribute__ ((aligned(8))); +static unsigned char txb[TX_BUF_SIZE] __attribute__ ((aligned(8))); +static unsigned char rxb[NUM_RX_DESC * RX_BUF_SIZE] + __attribute__ ((aligned(8))); + +/* Function Prototypes */ +static int mdio_read(struct eth_device *dev, int phy_id, int addr); +static void mdio_write(struct eth_device *dev, int phy_id, int addr, int value); +static void mdio_sync(struct eth_device *dev, u32 offset); +static int ns8382x_init(struct eth_device *dev, bd_t * bis); +static void ns8382x_reset(struct eth_device *dev); +static void ns8382x_init_rxfilter(struct eth_device *dev); +static void ns8382x_init_txd(struct eth_device *dev); +static void ns8382x_init_rxd(struct eth_device *dev); +static void ns8382x_set_rx_mode(struct eth_device *dev); +static void ns8382x_check_duplex(struct eth_device *dev); +static int ns8382x_send(struct eth_device *dev, void *packet, int length); +static int ns8382x_poll(struct eth_device *dev); +static void ns8382x_disable(struct eth_device *dev); + +static struct pci_device_id supported[] = { + {PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_83820}, + {} +}; + +#define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a) +#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a) + +static inline int +INW(struct eth_device *dev, u_long addr) +{ + return le16_to_cpu(*(vu_short *) (addr + dev->iobase)); +} + +static int +INL(struct eth_device *dev, u_long addr) +{ + return le32_to_cpu(*(vu_long *) (addr + dev->iobase)); +} + +static inline void +OUTW(struct eth_device *dev, int command, u_long addr) +{ + *(vu_short *) ((addr + dev->iobase)) = cpu_to_le16(command); +} + +static inline void +OUTL(struct eth_device *dev, int command, u_long addr) +{ + *(vu_long *) ((addr + dev->iobase)) = cpu_to_le32(command); +} + +/* Function: ns8382x_initialize + * Description: Retrieves the MAC address of the card, and sets up some + * globals required by other routines, and initializes the NIC, making it + * ready to send and receive packets. + * Side effects: initializes ns8382xs, ready to receive packets. + * Returns: int: number of cards found + */ + +int +ns8382x_initialize(bd_t * bis) +{ + pci_dev_t devno; + int card_number = 0; + struct eth_device *dev; + u32 iobase, status; + int i, idx = 0; + u32 phyAddress; + u32 tmp; + u32 chip_config; + + while (1) { /* Find PCI device(s) */ + if ((devno = pci_find_devices(supported, idx++)) < 0) + break; + + pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase); + iobase &= ~0x3; /* 1: unused and 0:I/O Space Indicator */ + + debug("ns8382x: NatSemi dp8382x @ 0x%x\n", iobase); + + pci_write_config_dword(devno, PCI_COMMAND, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + + /* Check if I/O accesses and Bus Mastering are enabled. */ + pci_read_config_dword(devno, PCI_COMMAND, &status); + if (!(status & PCI_COMMAND_MEMORY)) { + printf("Error: Can not enable MEM access.\n"); + continue; + } else if (!(status & PCI_COMMAND_MASTER)) { + printf("Error: Can not enable Bus Mastering.\n"); + continue; + } + + dev = (struct eth_device *) malloc(sizeof *dev); + if (!dev) { + printf("ns8382x: Can not allocate memory\n"); + break; + } + memset(dev, 0, sizeof(*dev)); + + sprintf(dev->name, "dp8382x#%d", card_number); + dev->iobase = bus_to_phys(iobase); + dev->priv = (void *) devno; + dev->init = ns8382x_init; + dev->halt = ns8382x_disable; + dev->send = ns8382x_send; + dev->recv = ns8382x_poll; + + /* ns8382x has a non-standard PM control register + * in PCI config space. Some boards apparently need + * to be brought to D0 in this manner. */ + pci_read_config_dword(devno, PCIPM, &tmp); + if (tmp & (0x03 | 0x100)) { /* D0 state, disable PME assertion */ + u32 newtmp = tmp & ~(0x03 | 0x100); + pci_write_config_dword(devno, PCIPM, newtmp); + } + + /* get MAC address */ + for (i = 0; i < 3; i++) { + u32 data; + char *mac = (char *)&dev->enetaddr[i * 2]; + + OUTL(dev, i * 2, RxFilterAddr); + data = INL(dev, RxFilterData); + *mac++ = data; + *mac++ = data >> 8; + } + /* get PHY address, can't be zero */ + for (phyAddress = 1; phyAddress < 32; phyAddress++) { + u32 rev, phy1; + + phy1 = mdio_read(dev, phyAddress, PHYIDR1); + if (phy1 == 0x2000) { /*check for 83861/91 */ + rev = mdio_read(dev, phyAddress, PHYIDR2); + if ((rev & ~(0x000f)) == 0x00005c50 || + (rev & ~(0x000f)) == 0x00005c60) { + debug("phy rev is %x\n", rev); + debug("phy address is %x\n", + phyAddress); + break; + } + } + } + + /* set phy to autonegotiate && advertise everything */ + mdio_write(dev, phyAddress, KTCR, + (ktcr_adv_1000H | ktcr_adv_1000F)); + mdio_write(dev, phyAddress, ANAR, + (anar_adv_100F | anar_adv_100H | anar_adv_10H | + anar_adv_10F | anar_ieee_8023)); + mdio_write(dev, phyAddress, BMCR, 0x0); /*restore */ + mdio_write(dev, phyAddress, BMCR, + (Bmcr_AutoNegEn | Bmcr_RstAutoNeg)); + /* Reset the chip to erase any previous misconfiguration. */ + OUTL(dev, (ChipReset), ChipCmd); + + chip_config = INL(dev, ChipConfig); + /* reset the phy */ + OUTL(dev, (chip_config | PhyRst), ChipConfig); + /* power up and initialize transceiver */ + OUTL(dev, (chip_config & ~(PhyDis)), ChipConfig); + + mdio_sync(dev, EECtrl); + + { + u32 chpcfg = + INL(dev, ChipConfig) ^ SpeedStatus_Polarity; + + debug("%s: Transceiver 10%s %s duplex.\n", dev->name, + (chpcfg & GigSpeed) ? "00" : (chpcfg & HundSpeed) + ? "0" : "", + chpcfg & FullDuplex ? "full" : "half"); + debug("%s: %02x:%02x:%02x:%02x:%02x:%02x\n", dev->name, + dev->enetaddr[0], dev->enetaddr[1], + dev->enetaddr[2], dev->enetaddr[3], + dev->enetaddr[4], dev->enetaddr[5]); + } + + /* Disable PME: + * The PME bit is initialized from the EEPROM contents. + * PCI cards probably have PME disabled, but motherboard + * implementations may have PME set to enable WakeOnLan. + * With PME set the chip will scan incoming packets but + * nothing will be written to memory. */ + SavedClkRun = INL(dev, ClkRun); + OUTL(dev, SavedClkRun & ~0x100, ClkRun); + + eth_register(dev); + + card_number++; + + pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x60); + + udelay(10 * 1000); + } + return card_number; +} + +/* MII transceiver control section. + Read and write MII registers using software-generated serial MDIO + protocol. See the MII specifications or DP83840A data sheet for details. + + The maximum data clock rate is 2.5 MHz. To meet minimum timing we + must flush writes to the PCI bus with a PCI read. */ +#define mdio_delay(mdio_addr) INL(dev, mdio_addr) + +#define MDIO_EnbIn (0) +#define MDIO_WRITE0 (MDIO_EnbOutput) +#define MDIO_WRITE1 (MDIO_Data | MDIO_EnbOutput) + +/* Generate the preamble required for initial synchronization and + a few older transceivers. */ +static void +mdio_sync(struct eth_device *dev, u32 offset) +{ + int bits = 32; + + /* Establish sync by sending at least 32 logic ones. */ + while (--bits >= 0) { + OUTL(dev, MDIO_WRITE1, offset); + mdio_delay(offset); + OUTL(dev, MDIO_WRITE1 | MDIO_ShiftClk, offset); + mdio_delay(offset); + } +} + +static int +mdio_read(struct eth_device *dev, int phy_id, int addr) +{ + int mii_cmd = (0xf6 << 10) | (phy_id << 5) | addr; + int i, retval = 0; + + /* Shift the read command bits out. */ + for (i = 15; i >= 0; i--) { + int dataval = (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0; + + OUTL(dev, dataval, EECtrl); + mdio_delay(EECtrl); + OUTL(dev, dataval | MDIO_ShiftClk, EECtrl); + mdio_delay(EECtrl); + } + /* Read the two transition, 16 data, and wire-idle bits. */ + for (i = 19; i > 0; i--) { + OUTL(dev, MDIO_EnbIn, EECtrl); + mdio_delay(EECtrl); + retval = + (retval << 1) | ((INL(dev, EECtrl) & MDIO_Data) ? 1 : 0); + OUTL(dev, MDIO_EnbIn | MDIO_ShiftClk, EECtrl); + mdio_delay(EECtrl); + } + return (retval >> 1) & 0xffff; +} + +static void +mdio_write(struct eth_device *dev, int phy_id, int addr, int value) +{ + int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (addr << 18) | value; + int i; + + /* Shift the command bits out. */ + for (i = 31; i >= 0; i--) { + int dataval = (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0; + + OUTL(dev, dataval, EECtrl); + mdio_delay(EECtrl); + OUTL(dev, dataval | MDIO_ShiftClk, EECtrl); + mdio_delay(EECtrl); + } + /* Clear out extra bits. */ + for (i = 2; i > 0; i--) { + OUTL(dev, MDIO_EnbIn, EECtrl); + mdio_delay(EECtrl); + OUTL(dev, MDIO_EnbIn | MDIO_ShiftClk, EECtrl); + mdio_delay(EECtrl); + } + return; +} + +/* Function: ns8382x_init + * Description: resets the ethernet controller chip and configures + * registers and data structures required for sending and receiving packets. + * Arguments: struct eth_device *dev: NIC data structure + * returns: int. + */ + +static int +ns8382x_init(struct eth_device *dev, bd_t * bis) +{ + u32 config; + + ns8382x_reset(dev); + + /* Disable PME: + * The PME bit is initialized from the EEPROM contents. + * PCI cards probably have PME disabled, but motherboard + * implementations may have PME set to enable WakeOnLan. + * With PME set the chip will scan incoming packets but + * nothing will be written to memory. */ + OUTL(dev, SavedClkRun & ~0x100, ClkRun); + + ns8382x_init_rxfilter(dev); + ns8382x_init_txd(dev); + ns8382x_init_rxd(dev); + + /*set up ChipConfig */ + config = INL(dev, ChipConfig); + /*turn off 64 bit ops && Ten-bit interface + * && big-endian mode && extended status */ + config &= ~(TBIEn | Mode1000 | T64En | D64En | M64En | BEMode | PhyDis | ExtStEn); + OUTL(dev, config, ChipConfig); + + /* Configure the PCI bus bursts and FIFO thresholds. */ + tx_config = TxCarrierIgn | TxHeartIgn | TxAutoPad + | TxCollRetry | TxMxdma_1024 | (0x1002); + rx_config = RxMxdma_1024 | 0x20; + + debug("%s: Setting TxConfig Register %#08X\n", dev->name, tx_config); + debug("%s: Setting RxConfig Register %#08X\n", dev->name, rx_config); + + OUTL(dev, tx_config, TxConfig); + OUTL(dev, rx_config, RxConfig); + + /*turn off priority queueing */ + OUTL(dev, 0x0, PriQueue); + + ns8382x_check_duplex(dev); + ns8382x_set_rx_mode(dev); + + OUTL(dev, (RxOn | TxOn), ChipCmd); + return 1; +} + +/* Function: ns8382x_reset + * Description: soft resets the controller chip + * Arguments: struct eth_device *dev: NIC data structure + * Returns: void. + */ +static void +ns8382x_reset(struct eth_device *dev) +{ + OUTL(dev, ChipReset, ChipCmd); + while (INL(dev, ChipCmd)) + /*wait until done */ ; + OUTL(dev, 0, IntrMask); + OUTL(dev, 0, IntrEnable); +} + +/* Function: ns8382x_init_rxfilter + * Description: sets receive filter address to our MAC address + * Arguments: struct eth_device *dev: NIC data structure + * returns: void. + */ + +static void +ns8382x_init_rxfilter(struct eth_device *dev) +{ + int i; + + for (i = 0; i < ETH_ALEN; i += 2) { + OUTL(dev, i, RxFilterAddr); + OUTW(dev, dev->enetaddr[i] + (dev->enetaddr[i + 1] << 8), + RxFilterData); + } +} + +/* Function: ns8382x_init_txd + * Description: initializes the Tx descriptor + * Arguments: struct eth_device *dev: NIC data structure + * returns: void. + */ + +static void +ns8382x_init_txd(struct eth_device *dev) +{ + txd.link = (u32) 0; + txd.bufptr = cpu_to_le32((u32) & txb[0]); + txd.cmdsts = (u32) 0; + txd.extsts = (u32) 0; + + OUTL(dev, 0x0, TxRingPtrHi); + OUTL(dev, phys_to_bus((u32)&txd), TxRingPtr); + + debug("ns8382x_init_txd: TX descriptor register loaded with: %#08X (&txd: %p)\n", + INL(dev, TxRingPtr), &txd); +} + +/* Function: ns8382x_init_rxd + * Description: initializes the Rx descriptor ring + * Arguments: struct eth_device *dev: NIC data structure + * Returns: void. + */ + +static void +ns8382x_init_rxd(struct eth_device *dev) +{ + int i; + + OUTL(dev, 0x0, RxRingPtrHi); + + cur_rx = 0; + for (i = 0; i < NUM_RX_DESC; i++) { + rxd[i].link = + cpu_to_le32((i + 1 < + NUM_RX_DESC) ? (u32) & rxd[i + + 1] : (u32) & + rxd[0]); + rxd[i].extsts = cpu_to_le32((u32) 0x0); + rxd[i].cmdsts = cpu_to_le32((u32) RX_BUF_SIZE); + rxd[i].bufptr = cpu_to_le32((u32) & rxb[i * RX_BUF_SIZE]); + + debug + ("ns8382x_init_rxd: rxd[%d]=%p link=%X cmdsts=%X bufptr=%X\n", + i, &rxd[i], le32_to_cpu(rxd[i].link), + le32_to_cpu(rxd[i].cmdsts), le32_to_cpu(rxd[i].bufptr)); + } + OUTL(dev, phys_to_bus((u32) & rxd), RxRingPtr); + + debug("ns8382x_init_rxd: RX descriptor register loaded with: %X\n", + INL(dev, RxRingPtr)); +} + +/* Function: ns8382x_set_rx_mode + * Description: + * sets the receive mode to accept all broadcast packets and packets + * with our MAC address, and reject all multicast packets. + * Arguments: struct eth_device *dev: NIC data structure + * Returns: void. + */ + +static void +ns8382x_set_rx_mode(struct eth_device *dev) +{ + u32 rx_mode = 0x0; + /*spec says RxFilterEnable has to be 0 for rest of + * this stuff to be properly configured. Linux driver + * seems to support this*/ +/* OUTL(dev, rx_mode, RxFilterAddr);*/ + rx_mode = (RxFilterEnable | AcceptAllBroadcast | AcceptPerfectMatch); + OUTL(dev, rx_mode, RxFilterAddr); + printf("ns8382x_set_rx_mode: set to %X\n", rx_mode); + /*now we turn RxFilterEnable back on */ + /*rx_mode |= RxFilterEnable; + OUTL(dev, rx_mode, RxFilterAddr);*/ +} + +static void +ns8382x_check_duplex(struct eth_device *dev) +{ + int gig = 0; + int hun = 0; + int duplex = 0; + int config = (INL(dev, ChipConfig) ^ SpeedStatus_Polarity); + + duplex = (config & FullDuplex) ? 1 : 0; + gig = (config & GigSpeed) ? 1 : 0; + hun = (config & HundSpeed) ? 1 : 0; + + debug("%s: Setting 10%s %s-duplex based on negotiated link" + " capability.\n", dev->name, (gig) ? "00" : (hun) ? "0" : "", + duplex ? "full" : "half"); + + if (duplex) { + rx_config |= RxAcceptTx; + tx_config |= (TxCarrierIgn | TxHeartIgn); + } else { + rx_config &= ~RxAcceptTx; + tx_config &= ~(TxCarrierIgn | TxHeartIgn); + } + + debug("%s: Resetting TxConfig Register %#08X\n", dev->name, tx_config); + debug("%s: Resetting RxConfig Register %#08X\n", dev->name, rx_config); + + OUTL(dev, tx_config, TxConfig); + OUTL(dev, rx_config, RxConfig); + + /*if speed is 10 or 100, remove MODE1000, + * if it's 1000, then set it */ + config = INL(dev, ChipConfig); + if (gig) + config |= Mode1000; + else + config &= ~Mode1000; + + debug("%s: %setting Mode1000\n", dev->name, (gig) ? "S" : "Uns"); + + OUTL(dev, config, ChipConfig); +} + +/* Function: ns8382x_send + * Description: transmits a packet and waits for completion or timeout. + * Returns: void. */ +static int ns8382x_send(struct eth_device *dev, void *packet, int length) +{ + u32 i, status = 0; + vu_long tx_stat = 0; + + /* Stop the transmitter */ + OUTL(dev, TxOff, ChipCmd); + + debug("ns8382x_send: sending %d bytes\n", (int)length); + + /* set the transmit buffer descriptor and enable Transmit State Machine */ + txd.link = cpu_to_le32(0x0); + txd.bufptr = cpu_to_le32(phys_to_bus((u32)packet)); + txd.extsts = cpu_to_le32(0x0); + txd.cmdsts = cpu_to_le32(DescOwn | length); + + /* load Transmit Descriptor Register */ + OUTL(dev, phys_to_bus((u32) & txd), TxRingPtr); + + debug("ns8382x_send: TX descriptor register loaded with: %#08X\n", + INL(dev, TxRingPtr)); + debug("\ttxd.link:%X\tbufp:%X\texsts:%X\tcmdsts:%X\n", + le32_to_cpu(txd.link), le32_to_cpu(txd.bufptr), + le32_to_cpu(txd.extsts), le32_to_cpu(txd.cmdsts)); + + /* restart the transmitter */ + OUTL(dev, TxOn, ChipCmd); + + for (i = 0; (tx_stat = le32_to_cpu(txd.cmdsts)) & DescOwn; i++) { + if (i >= TOUT_LOOP) { + printf ("%s: tx error buffer not ready: txd.cmdsts %#lX\n", + dev->name, tx_stat); + goto Done; + } + } + + if (!(tx_stat & DescPktOK)) { + printf("ns8382x_send: Transmit error, Tx status %lX.\n", tx_stat); + goto Done; + } + + debug("ns8382x_send: tx_stat: %#08lX\n", tx_stat); + + status = 1; +Done: + return status; +} + +/* Function: ns8382x_poll + * Description: checks for a received packet and returns it if found. + * Arguments: struct eth_device *dev: NIC data structure + * Returns: 1 if packet was received. + * 0 if no packet was received. + * Side effects: + * Returns (copies) the packet to the array dev->packet. + * Returns the length of the packet. + */ + +static int +ns8382x_poll(struct eth_device *dev) +{ + int retstat = 0; + int length = 0; + vu_long rx_status = le32_to_cpu(rxd[cur_rx].cmdsts); + + if (!(rx_status & (u32) DescOwn)) + return retstat; + + debug("ns8382x_poll: got a packet: cur_rx:%u, status:%lx\n", + cur_rx, rx_status); + + length = (rx_status & DSIZE) - CRC_SIZE; + + if ((rx_status & (DescMore | DescPktOK | DescRxLong)) != DescPktOK) { + /* corrupted packet received */ + printf("ns8382x_poll: Corrupted packet, status:%lx\n", + rx_status); + retstat = 0; + } else { + /* give packet to higher level routine */ + net_process_received_packet((rxb + cur_rx * RX_BUF_SIZE), + length); + retstat = 1; + } + + /* return the descriptor and buffer to receive ring */ + rxd[cur_rx].cmdsts = cpu_to_le32(RX_BUF_SIZE); + rxd[cur_rx].bufptr = cpu_to_le32((u32) & rxb[cur_rx * RX_BUF_SIZE]); + + if (++cur_rx == NUM_RX_DESC) + cur_rx = 0; + + /* re-enable the potentially idle receive state machine */ + OUTL(dev, RxOn, ChipCmd); + + return retstat; +} + +/* Function: ns8382x_disable + * Description: Turns off interrupts and stops Tx and Rx engines + * Arguments: struct eth_device *dev: NIC data structure + * Returns: void. + */ + +static void +ns8382x_disable(struct eth_device *dev) +{ + /* Disable interrupts using the mask. */ + OUTL(dev, 0, IntrMask); + OUTL(dev, 0, IntrEnable); + + /* Stop the chip's Tx and Rx processes. */ + OUTL(dev, (RxOff | TxOff), ChipCmd); + + /* Restore PME enable bit */ + OUTL(dev, SavedClkRun, ClkRun); +} diff --git a/sources/uboot-be550/drivers/net/pch_gbe.c b/sources/uboot-be550/drivers/net/pch_gbe.c new file mode 100644 index 00000000..dfc01000 --- /dev/null +++ b/sources/uboot-be550/drivers/net/pch_gbe.c @@ -0,0 +1,491 @@ +/* + * Copyright (C) 2015, Bin Meng + * + * Intel Platform Controller Hub EG20T (codename Topcliff) GMAC Driver + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include "pch_gbe.h" + +#if !defined(CONFIG_PHYLIB) +# error "PCH Gigabit Ethernet driver requires PHYLIB - missing CONFIG_PHYLIB" +#endif + +static struct pci_device_id supported[] = { + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_GBE) }, + { } +}; + +static void pch_gbe_mac_read(struct pch_gbe_regs *mac_regs, u8 *addr) +{ + u32 macid_hi, macid_lo; + + macid_hi = readl(&mac_regs->mac_adr[0].high); + macid_lo = readl(&mac_regs->mac_adr[0].low) & 0xffff; + debug("pch_gbe: macid_hi %#x macid_lo %#x\n", macid_hi, macid_lo); + + addr[0] = (u8)(macid_hi & 0xff); + addr[1] = (u8)((macid_hi >> 8) & 0xff); + addr[2] = (u8)((macid_hi >> 16) & 0xff); + addr[3] = (u8)((macid_hi >> 24) & 0xff); + addr[4] = (u8)(macid_lo & 0xff); + addr[5] = (u8)((macid_lo >> 8) & 0xff); +} + +static int pch_gbe_mac_write(struct pch_gbe_regs *mac_regs, u8 *addr) +{ + u32 macid_hi, macid_lo; + ulong start; + + macid_hi = addr[0] + (addr[1] << 8) + (addr[2] << 16) + (addr[3] << 24); + macid_lo = addr[4] + (addr[5] << 8); + + writel(macid_hi, &mac_regs->mac_adr[0].high); + writel(macid_lo, &mac_regs->mac_adr[0].low); + writel(0xfffe, &mac_regs->addr_mask); + + start = get_timer(0); + while (get_timer(start) < PCH_GBE_TIMEOUT) { + if (!(readl(&mac_regs->addr_mask) & PCH_GBE_BUSY)) + return 0; + + udelay(10); + } + + return -ETIME; +} + +static int pch_gbe_reset(struct udevice *dev) +{ + struct pch_gbe_priv *priv = dev_get_priv(dev); + struct eth_pdata *plat = dev_get_platdata(dev); + struct pch_gbe_regs *mac_regs = priv->mac_regs; + ulong start; + + priv->rx_idx = 0; + priv->tx_idx = 0; + + writel(PCH_GBE_ALL_RST, &mac_regs->reset); + + /* + * Configure the MAC to RGMII mode after reset + * + * For some unknown reason, we must do the configuration here right + * after resetting the whole MAC, otherwise the reset bit in the RESET + * register will never be cleared by the hardware. And there is another + * way of having the same magic, that is to configure the MODE register + * to have the MAC work in MII/GMII mode, which is how current Linux + * pch_gbe driver does. Since anyway we need program the MAC to RGMII + * mode in the driver, we just do it here. + * + * Note: this behavior is not documented in the hardware manual. + */ + writel(PCH_GBE_RGMII_MODE_RGMII | PCH_GBE_CHIP_TYPE_INTERNAL, + &mac_regs->rgmii_ctrl); + + start = get_timer(0); + while (get_timer(start) < PCH_GBE_TIMEOUT) { + if (!(readl(&mac_regs->reset) & PCH_GBE_ALL_RST)) { + /* + * Soft reset clears hardware MAC address registers, + * so we have to reload MAC address here in order to + * make linux pch_gbe driver happy. + */ + return pch_gbe_mac_write(mac_regs, plat->enetaddr); + } + + udelay(10); + } + + debug("pch_gbe: reset timeout\n"); + return -ETIME; +} + +static void pch_gbe_rx_descs_init(struct udevice *dev) +{ + struct pch_gbe_priv *priv = dev_get_priv(dev); + struct pch_gbe_regs *mac_regs = priv->mac_regs; + struct pch_gbe_rx_desc *rx_desc = &priv->rx_desc[0]; + int i; + + memset(rx_desc, 0, sizeof(struct pch_gbe_rx_desc) * PCH_GBE_DESC_NUM); + for (i = 0; i < PCH_GBE_DESC_NUM; i++) + rx_desc->buffer_addr = pci_phys_to_mem(priv->bdf, + (u32)(priv->rx_buff[i])); + + writel(pci_phys_to_mem(priv->bdf, (u32)rx_desc), + &mac_regs->rx_dsc_base); + writel(sizeof(struct pch_gbe_rx_desc) * (PCH_GBE_DESC_NUM - 1), + &mac_regs->rx_dsc_size); + + writel(pci_phys_to_mem(priv->bdf, (u32)(rx_desc + 1)), + &mac_regs->rx_dsc_sw_p); +} + +static void pch_gbe_tx_descs_init(struct udevice *dev) +{ + struct pch_gbe_priv *priv = dev_get_priv(dev); + struct pch_gbe_regs *mac_regs = priv->mac_regs; + struct pch_gbe_tx_desc *tx_desc = &priv->tx_desc[0]; + + memset(tx_desc, 0, sizeof(struct pch_gbe_tx_desc) * PCH_GBE_DESC_NUM); + + writel(pci_phys_to_mem(priv->bdf, (u32)tx_desc), + &mac_regs->tx_dsc_base); + writel(sizeof(struct pch_gbe_tx_desc) * (PCH_GBE_DESC_NUM - 1), + &mac_regs->tx_dsc_size); + writel(pci_phys_to_mem(priv->bdf, (u32)(tx_desc + 1)), + &mac_regs->tx_dsc_sw_p); +} + +static void pch_gbe_adjust_link(struct pch_gbe_regs *mac_regs, + struct phy_device *phydev) +{ + if (!phydev->link) { + printf("%s: No link.\n", phydev->dev->name); + return; + } + + clrbits_le32(&mac_regs->rgmii_ctrl, + PCH_GBE_RGMII_RATE_2_5M | PCH_GBE_CRS_SEL); + clrbits_le32(&mac_regs->mode, + PCH_GBE_MODE_GMII_ETHER | PCH_GBE_MODE_FULL_DUPLEX); + + switch (phydev->speed) { + case 1000: + setbits_le32(&mac_regs->rgmii_ctrl, PCH_GBE_RGMII_RATE_125M); + setbits_le32(&mac_regs->mode, PCH_GBE_MODE_GMII_ETHER); + break; + case 100: + setbits_le32(&mac_regs->rgmii_ctrl, PCH_GBE_RGMII_RATE_25M); + setbits_le32(&mac_regs->mode, PCH_GBE_MODE_MII_ETHER); + break; + case 10: + setbits_le32(&mac_regs->rgmii_ctrl, PCH_GBE_RGMII_RATE_2_5M); + setbits_le32(&mac_regs->mode, PCH_GBE_MODE_MII_ETHER); + break; + } + + if (phydev->duplex) { + setbits_le32(&mac_regs->rgmii_ctrl, PCH_GBE_CRS_SEL); + setbits_le32(&mac_regs->mode, PCH_GBE_MODE_FULL_DUPLEX); + } + + printf("Speed: %d, %s duplex\n", phydev->speed, + (phydev->duplex) ? "full" : "half"); + + return; +} + +static int pch_gbe_start(struct udevice *dev) +{ + struct pch_gbe_priv *priv = dev_get_priv(dev); + struct pch_gbe_regs *mac_regs = priv->mac_regs; + + if (pch_gbe_reset(dev)) + return -1; + + pch_gbe_rx_descs_init(dev); + pch_gbe_tx_descs_init(dev); + + /* Enable frame bursting */ + writel(PCH_GBE_MODE_FR_BST, &mac_regs->mode); + /* Disable TCP/IP accelerator */ + writel(PCH_GBE_RX_TCPIPACC_OFF, &mac_regs->tcpip_acc); + /* Disable RX flow control */ + writel(0, &mac_regs->rx_fctrl); + /* Configure RX/TX mode */ + writel(PCH_GBE_RH_ALM_EMP_16 | PCH_GBE_RH_ALM_FULL_16 | + PCH_GBE_RH_RD_TRG_32, &mac_regs->rx_mode); + writel(PCH_GBE_TM_TH_TX_STRT_32 | PCH_GBE_TM_TH_ALM_EMP_16 | + PCH_GBE_TM_TH_ALM_FULL_32 | PCH_GBE_TM_ST_AND_FD | + PCH_GBE_TM_SHORT_PKT, &mac_regs->tx_mode); + + /* Start up the PHY */ + if (phy_startup(priv->phydev)) { + printf("Could not initialize PHY %s\n", + priv->phydev->dev->name); + return -1; + } + + pch_gbe_adjust_link(mac_regs, priv->phydev); + + if (!priv->phydev->link) + return -1; + + /* Enable TX & RX */ + writel(PCH_GBE_RX_DMA_EN | PCH_GBE_TX_DMA_EN, &mac_regs->dma_ctrl); + writel(PCH_GBE_MRE_MAC_RX_EN, &mac_regs->mac_rx_en); + + return 0; +} + +static void pch_gbe_stop(struct udevice *dev) +{ + struct pch_gbe_priv *priv = dev_get_priv(dev); + + pch_gbe_reset(dev); + + phy_shutdown(priv->phydev); +} + +static int pch_gbe_send(struct udevice *dev, void *packet, int length) +{ + struct pch_gbe_priv *priv = dev_get_priv(dev); + struct pch_gbe_regs *mac_regs = priv->mac_regs; + struct pch_gbe_tx_desc *tx_head, *tx_desc; + u16 frame_ctrl = 0; + u32 int_st; + ulong start; + + tx_head = &priv->tx_desc[0]; + tx_desc = &priv->tx_desc[priv->tx_idx]; + + if (length < 64) + frame_ctrl |= PCH_GBE_TXD_CTRL_APAD; + + tx_desc->buffer_addr = pci_phys_to_mem(priv->bdf, (u32)packet); + tx_desc->length = length; + tx_desc->tx_words_eob = length + 3; + tx_desc->tx_frame_ctrl = frame_ctrl; + tx_desc->dma_status = 0; + tx_desc->gbec_status = 0; + + /* Test the wrap-around condition */ + if (++priv->tx_idx >= PCH_GBE_DESC_NUM) + priv->tx_idx = 0; + + writel(pci_phys_to_mem(priv->bdf, (u32)(tx_head + priv->tx_idx)), + &mac_regs->tx_dsc_sw_p); + + start = get_timer(0); + while (get_timer(start) < PCH_GBE_TIMEOUT) { + int_st = readl(&mac_regs->int_st); + if (int_st & PCH_GBE_INT_TX_CMPLT) + return 0; + + udelay(10); + } + + debug("pch_gbe: sent failed\n"); + return -ETIME; +} + +static int pch_gbe_recv(struct udevice *dev, int flags, uchar **packetp) +{ + struct pch_gbe_priv *priv = dev_get_priv(dev); + struct pch_gbe_regs *mac_regs = priv->mac_regs; + struct pch_gbe_rx_desc *rx_desc; + u32 hw_desc, buffer_addr, length; + + rx_desc = &priv->rx_desc[priv->rx_idx]; + + readl(&mac_regs->int_st); + hw_desc = readl(&mac_regs->rx_dsc_hw_p_hld); + + /* Just return if not receiving any packet */ + if ((u32)rx_desc == hw_desc) + return -EAGAIN; + + buffer_addr = pci_mem_to_phys(priv->bdf, rx_desc->buffer_addr); + *packetp = (uchar *)buffer_addr; + length = rx_desc->rx_words_eob - 3 - ETH_FCS_LEN; + + return length; +} + +static int pch_gbe_free_pkt(struct udevice *dev, uchar *packet, int length) +{ + struct pch_gbe_priv *priv = dev_get_priv(dev); + struct pch_gbe_regs *mac_regs = priv->mac_regs; + struct pch_gbe_rx_desc *rx_head = &priv->rx_desc[0]; + int rx_swp; + + /* Test the wrap-around condition */ + if (++priv->rx_idx >= PCH_GBE_DESC_NUM) + priv->rx_idx = 0; + rx_swp = priv->rx_idx; + if (++rx_swp >= PCH_GBE_DESC_NUM) + rx_swp = 0; + + writel(pci_phys_to_mem(priv->bdf, (u32)(rx_head + rx_swp)), + &mac_regs->rx_dsc_sw_p); + + return 0; +} + +static int pch_gbe_mdio_ready(struct pch_gbe_regs *mac_regs) +{ + ulong start = get_timer(0); + + while (get_timer(start) < PCH_GBE_TIMEOUT) { + if (readl(&mac_regs->miim) & PCH_GBE_MIIM_OPER_READY) + return 0; + + udelay(10); + } + + return -ETIME; +} + +static int pch_gbe_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) +{ + struct pch_gbe_regs *mac_regs = bus->priv; + u32 miim; + + if (pch_gbe_mdio_ready(mac_regs)) + return -ETIME; + + miim = (addr << PCH_GBE_MIIM_PHY_ADDR_SHIFT) | + (reg << PCH_GBE_MIIM_REG_ADDR_SHIFT) | + PCH_GBE_MIIM_OPER_READ; + writel(miim, &mac_regs->miim); + + if (pch_gbe_mdio_ready(mac_regs)) + return -ETIME; + + return readl(&mac_regs->miim) & 0xffff; +} + +static int pch_gbe_mdio_write(struct mii_dev *bus, int addr, int devad, + int reg, u16 val) +{ + struct pch_gbe_regs *mac_regs = bus->priv; + u32 miim; + + if (pch_gbe_mdio_ready(mac_regs)) + return -ETIME; + + miim = (addr << PCH_GBE_MIIM_PHY_ADDR_SHIFT) | + (reg << PCH_GBE_MIIM_REG_ADDR_SHIFT) | + PCH_GBE_MIIM_OPER_WRITE | val; + writel(miim, &mac_regs->miim); + + if (pch_gbe_mdio_ready(mac_regs)) + return -ETIME; + else + return 0; +} + +static int pch_gbe_mdio_init(const char *name, struct pch_gbe_regs *mac_regs) +{ + struct mii_dev *bus; + + bus = mdio_alloc(); + if (!bus) { + debug("pch_gbe: failed to allocate MDIO bus\n"); + return -ENOMEM; + } + + bus->read = pch_gbe_mdio_read; + bus->write = pch_gbe_mdio_write; + sprintf(bus->name, name); + + bus->priv = (void *)mac_regs; + + return mdio_register(bus); +} + +static int pch_gbe_phy_init(struct udevice *dev) +{ + struct pch_gbe_priv *priv = dev_get_priv(dev); + struct eth_pdata *plat = dev_get_platdata(dev); + struct phy_device *phydev; + int mask = 0xffffffff; + + phydev = phy_find_by_mask(priv->bus, mask, plat->phy_interface); + if (!phydev) { + printf("pch_gbe: cannot find the phy\n"); + return -1; + } + + phy_connect_dev(phydev, dev); + + phydev->supported &= PHY_GBIT_FEATURES; + phydev->advertising = phydev->supported; + + priv->phydev = phydev; + phy_config(phydev); + + return 0; +} + +int pch_gbe_probe(struct udevice *dev) +{ + struct pch_gbe_priv *priv; + struct eth_pdata *plat = dev_get_platdata(dev); + pci_dev_t devno; + u32 iobase; + + devno = pci_get_bdf(dev); + + /* + * The priv structure contains the descriptors and frame buffers which + * need a strict buswidth alignment (64 bytes). This is guaranteed by + * DM_FLAG_ALLOC_PRIV_DMA flag in the U_BOOT_DRIVER. + */ + priv = dev_get_priv(dev); + + priv->bdf = devno; + + pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase); + iobase &= PCI_BASE_ADDRESS_MEM_MASK; + iobase = pci_mem_to_phys(devno, iobase); + + plat->iobase = iobase; + priv->mac_regs = (struct pch_gbe_regs *)iobase; + + /* Read MAC address from SROM and initialize dev->enetaddr with it */ + pch_gbe_mac_read(priv->mac_regs, plat->enetaddr); + + plat->phy_interface = PHY_INTERFACE_MODE_RGMII; + pch_gbe_mdio_init(dev->name, priv->mac_regs); + priv->bus = miiphy_get_dev_by_name(dev->name); + + return pch_gbe_phy_init(dev); +} + +int pch_gbe_remove(struct udevice *dev) +{ + struct pch_gbe_priv *priv = dev_get_priv(dev); + + free(priv->phydev); + mdio_unregister(priv->bus); + mdio_free(priv->bus); + + return 0; +} + +static const struct eth_ops pch_gbe_ops = { + .start = pch_gbe_start, + .send = pch_gbe_send, + .recv = pch_gbe_recv, + .free_pkt = pch_gbe_free_pkt, + .stop = pch_gbe_stop, +}; + +static const struct udevice_id pch_gbe_ids[] = { + { .compatible = "intel,pch-gbe" }, + { } +}; + +U_BOOT_DRIVER(eth_pch_gbe) = { + .name = "pch_gbe", + .id = UCLASS_ETH, + .of_match = pch_gbe_ids, + .probe = pch_gbe_probe, + .remove = pch_gbe_remove, + .ops = &pch_gbe_ops, + .priv_auto_alloc_size = sizeof(struct pch_gbe_priv), + .platdata_auto_alloc_size = sizeof(struct eth_pdata), + .flags = DM_FLAG_ALLOC_PRIV_DMA, +}; + +U_BOOT_PCI_DEVICE(eth_pch_gbe, supported); diff --git a/sources/uboot-be550/drivers/net/pch_gbe.h b/sources/uboot-be550/drivers/net/pch_gbe.h new file mode 100644 index 00000000..afcb03dd --- /dev/null +++ b/sources/uboot-be550/drivers/net/pch_gbe.h @@ -0,0 +1,298 @@ +/* + * Copyright (C) 2015, Bin Meng + * + * Intel Platform Controller Hub EG20T (codename Topcliff) GMAC Driver + * Adapted from linux drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _PCH_GBE_H_ +#define _PCH_GBE_H_ + +#define PCH_GBE_TIMEOUT (3 * CONFIG_SYS_HZ) + +#define PCH_GBE_DESC_NUM 4 +#define PCH_GBE_ALIGN_SIZE 64 + +/* + * Topcliff GBE MAC supports receiving ethernet frames with normal frame size + * (64-1518 bytes) as well as up to 10318 bytes, however it does not have a + * register bit to turn off receiving 'jumbo frame', so we have to allocate + * our own buffer to store the received frames instead of using U-Boot's own. + */ +#define PCH_GBE_RX_FRAME_LEN ROUND(10318, PCH_GBE_ALIGN_SIZE) + +/* Interrupt Status */ +/* Interrupt Status Hold */ +/* Interrupt Enable */ +#define PCH_GBE_INT_RX_DMA_CMPLT 0x00000001 +#define PCH_GBE_INT_RX_VALID 0x00000002 +#define PCH_GBE_INT_RX_FRAME_ERR 0x00000004 +#define PCH_GBE_INT_RX_FIFO_ERR 0x00000008 +#define PCH_GBE_INT_RX_DMA_ERR 0x00000010 +#define PCH_GBE_INT_RX_DSC_EMP 0x00000020 +#define PCH_GBE_INT_TX_CMPLT 0x00000100 +#define PCH_GBE_INT_TX_DMA_CMPLT 0x00000200 +#define PCH_GBE_INT_TX_FIFO_ERR 0x00000400 +#define PCH_GBE_INT_TX_DMA_ERR 0x00000800 +#define PCH_GBE_INT_PAUSE_CMPLT 0x00001000 +#define PCH_GBE_INT_MIIM_CMPLT 0x00010000 +#define PCH_GBE_INT_PHY_INT 0x00100000 +#define PCH_GBE_INT_WOL_DET 0x01000000 +#define PCH_GBE_INT_TCPIP_ERR 0x10000000 + +/* Mode */ +#define PCH_GBE_MODE_MII_ETHER 0x00000000 +#define PCH_GBE_MODE_GMII_ETHER 0x80000000 +#define PCH_GBE_MODE_HALF_DUPLEX 0x00000000 +#define PCH_GBE_MODE_FULL_DUPLEX 0x40000000 +#define PCH_GBE_MODE_FR_BST 0x04000000 + +/* Reset */ +#define PCH_GBE_ALL_RST 0x80000000 +#define PCH_GBE_TX_RST 0x00008000 +#define PCH_GBE_RX_RST 0x00004000 + +/* TCP/IP Accelerator Control */ +#define PCH_GBE_EX_LIST_EN 0x00000008 +#define PCH_GBE_RX_TCPIPACC_OFF 0x00000004 +#define PCH_GBE_TX_TCPIPACC_EN 0x00000002 +#define PCH_GBE_RX_TCPIPACC_EN 0x00000001 + +/* MAC RX Enable */ +#define PCH_GBE_MRE_MAC_RX_EN 0x00000001 + +/* RX Flow Control */ +#define PCH_GBE_FL_CTRL_EN 0x80000000 + +/* RX Mode */ +#define PCH_GBE_ADD_FIL_EN 0x80000000 +#define PCH_GBE_MLT_FIL_EN 0x40000000 +#define PCH_GBE_RH_ALM_EMP_4 0x00000000 +#define PCH_GBE_RH_ALM_EMP_8 0x00004000 +#define PCH_GBE_RH_ALM_EMP_16 0x00008000 +#define PCH_GBE_RH_ALM_EMP_32 0x0000c000 +#define PCH_GBE_RH_ALM_FULL_4 0x00000000 +#define PCH_GBE_RH_ALM_FULL_8 0x00001000 +#define PCH_GBE_RH_ALM_FULL_16 0x00002000 +#define PCH_GBE_RH_ALM_FULL_32 0x00003000 +#define PCH_GBE_RH_RD_TRG_4 0x00000000 +#define PCH_GBE_RH_RD_TRG_8 0x00000200 +#define PCH_GBE_RH_RD_TRG_16 0x00000400 +#define PCH_GBE_RH_RD_TRG_32 0x00000600 +#define PCH_GBE_RH_RD_TRG_64 0x00000800 +#define PCH_GBE_RH_RD_TRG_128 0x00000a00 +#define PCH_GBE_RH_RD_TRG_256 0x00000c00 +#define PCH_GBE_RH_RD_TRG_512 0x00000e00 + +/* TX Mode */ +#define PCH_GBE_TM_NO_RTRY 0x80000000 +#define PCH_GBE_TM_LONG_PKT 0x40000000 +#define PCH_GBE_TM_ST_AND_FD 0x20000000 +#define PCH_GBE_TM_SHORT_PKT 0x10000000 +#define PCH_GBE_TM_LTCOL_RETX 0x08000000 +#define PCH_GBE_TM_TH_TX_STRT_4 0x00000000 +#define PCH_GBE_TM_TH_TX_STRT_8 0x00004000 +#define PCH_GBE_TM_TH_TX_STRT_16 0x00008000 +#define PCH_GBE_TM_TH_TX_STRT_32 0x0000c000 +#define PCH_GBE_TM_TH_ALM_EMP_4 0x00000000 +#define PCH_GBE_TM_TH_ALM_EMP_8 0x00000800 +#define PCH_GBE_TM_TH_ALM_EMP_16 0x00001000 +#define PCH_GBE_TM_TH_ALM_EMP_32 0x00001800 +#define PCH_GBE_TM_TH_ALM_EMP_64 0x00002000 +#define PCH_GBE_TM_TH_ALM_EMP_128 0x00002800 +#define PCH_GBE_TM_TH_ALM_EMP_256 0x00003000 +#define PCH_GBE_TM_TH_ALM_EMP_512 0x00003800 +#define PCH_GBE_TM_TH_ALM_FULL_4 0x00000000 +#define PCH_GBE_TM_TH_ALM_FULL_8 0x00000200 +#define PCH_GBE_TM_TH_ALM_FULL_16 0x00000400 +#define PCH_GBE_TM_TH_ALM_FULL_32 0x00000600 + +/* MAC Address Mask */ +#define PCH_GBE_BUSY 0x80000000 + +/* MIIM */ +#define PCH_GBE_MIIM_OPER_WRITE 0x04000000 +#define PCH_GBE_MIIM_OPER_READ 0x00000000 +#define PCH_GBE_MIIM_OPER_READY 0x04000000 +#define PCH_GBE_MIIM_PHY_ADDR_SHIFT 21 +#define PCH_GBE_MIIM_REG_ADDR_SHIFT 16 + +/* RGMII Control */ +#define PCH_GBE_CRS_SEL 0x00000010 +#define PCH_GBE_RGMII_RATE_125M 0x00000000 +#define PCH_GBE_RGMII_RATE_25M 0x00000008 +#define PCH_GBE_RGMII_RATE_2_5M 0x0000000c +#define PCH_GBE_RGMII_MODE_GMII 0x00000000 +#define PCH_GBE_RGMII_MODE_RGMII 0x00000002 +#define PCH_GBE_CHIP_TYPE_EXTERNAL 0x00000000 +#define PCH_GBE_CHIP_TYPE_INTERNAL 0x00000001 + +/* DMA Control */ +#define PCH_GBE_RX_DMA_EN 0x00000002 +#define PCH_GBE_TX_DMA_EN 0x00000001 + +/* Receive Descriptor bit definitions */ +#define PCH_GBE_RXD_ACC_STAT_BCAST 0x00000400 +#define PCH_GBE_RXD_ACC_STAT_MCAST 0x00000200 +#define PCH_GBE_RXD_ACC_STAT_UCAST 0x00000100 +#define PCH_GBE_RXD_ACC_STAT_TCPIPOK 0x000000c0 +#define PCH_GBE_RXD_ACC_STAT_IPOK 0x00000080 +#define PCH_GBE_RXD_ACC_STAT_TCPOK 0x00000040 +#define PCH_GBE_RXD_ACC_STAT_IP6ERR 0x00000020 +#define PCH_GBE_RXD_ACC_STAT_OFLIST 0x00000010 +#define PCH_GBE_RXD_ACC_STAT_TYPEIP 0x00000008 +#define PCH_GBE_RXD_ACC_STAT_MACL 0x00000004 +#define PCH_GBE_RXD_ACC_STAT_PPPOE 0x00000002 +#define PCH_GBE_RXD_ACC_STAT_VTAGT 0x00000001 +#define PCH_GBE_RXD_GMAC_STAT_PAUSE 0x0200 +#define PCH_GBE_RXD_GMAC_STAT_MARBR 0x0100 +#define PCH_GBE_RXD_GMAC_STAT_MARMLT 0x0080 +#define PCH_GBE_RXD_GMAC_STAT_MARIND 0x0040 +#define PCH_GBE_RXD_GMAC_STAT_MARNOTMT 0x0020 +#define PCH_GBE_RXD_GMAC_STAT_TLONG 0x0010 +#define PCH_GBE_RXD_GMAC_STAT_TSHRT 0x0008 +#define PCH_GBE_RXD_GMAC_STAT_NOTOCTAL 0x0004 +#define PCH_GBE_RXD_GMAC_STAT_NBLERR 0x0002 +#define PCH_GBE_RXD_GMAC_STAT_CRCERR 0x0001 + +/* Transmit Descriptor bit definitions */ +#define PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF 0x0008 +#define PCH_GBE_TXD_CTRL_ITAG 0x0004 +#define PCH_GBE_TXD_CTRL_ICRC 0x0002 +#define PCH_GBE_TXD_CTRL_APAD 0x0001 +#define PCH_GBE_TXD_WORDS_SHIFT 2 +#define PCH_GBE_TXD_GMAC_STAT_CMPLT 0x2000 +#define PCH_GBE_TXD_GMAC_STAT_ABT 0x1000 +#define PCH_GBE_TXD_GMAC_STAT_EXCOL 0x0800 +#define PCH_GBE_TXD_GMAC_STAT_SNGCOL 0x0400 +#define PCH_GBE_TXD_GMAC_STAT_MLTCOL 0x0200 +#define PCH_GBE_TXD_GMAC_STAT_CRSER 0x0100 +#define PCH_GBE_TXD_GMAC_STAT_TLNG 0x0080 +#define PCH_GBE_TXD_GMAC_STAT_TSHRT 0x0040 +#define PCH_GBE_TXD_GMAC_STAT_LTCOL 0x0020 +#define PCH_GBE_TXD_GMAC_STAT_TFUNDFLW 0x0010 + +/** + * struct pch_gbe_rx_desc - Receive Descriptor + * @buffer_addr: RX Frame Buffer Address + * @tcp_ip_status: TCP/IP Accelerator Status + * @rx_words_eob: RX word count and Byte position + * @gbec_status: GMAC Status + * @dma_status: DMA Status + * @reserved1: Reserved + * @reserved2: Reserved + */ +struct pch_gbe_rx_desc { + u32 buffer_addr; + u32 tcp_ip_status; + u16 rx_words_eob; + u16 gbec_status; + u8 dma_status; + u8 reserved1; + u16 reserved2; +}; + +/** + * struct pch_gbe_tx_desc - Transmit Descriptor + * @buffer_addr: TX Frame Buffer Address + * @length: Data buffer length + * @reserved1: Reserved + * @tx_words_eob: TX word count and Byte position + * @tx_frame_ctrl: TX Frame Control + * @dma_status: DMA Status + * @reserved2: Reserved + * @gbec_status: GMAC Status + */ +struct pch_gbe_tx_desc { + u32 buffer_addr; + u16 length; + u16 reserved1; + u16 tx_words_eob; + u16 tx_frame_ctrl; + u8 dma_status; + u8 reserved2; + u16 gbec_status; +}; + +/** + * pch_gbe_regs_mac_adr - structure holding values of mac address registers + * + * @high Denotes the 1st to 4th byte from the initial of MAC address + * @low Denotes the 5th to 6th byte from the initial of MAC address + */ +struct pch_gbe_regs_mac_adr { + u32 high; + u32 low; +}; + +/** + * pch_gbe_regs - structure holding values of MAC registers + */ +struct pch_gbe_regs { + u32 int_st; + u32 int_en; + u32 mode; + u32 reset; + u32 tcpip_acc; + u32 ex_list; + u32 int_st_hold; + u32 phy_int_ctrl; + u32 mac_rx_en; + u32 rx_fctrl; + u32 pause_req; + u32 rx_mode; + u32 tx_mode; + u32 rx_fifo_st; + u32 tx_fifo_st; + u32 tx_fid; + u32 tx_result; + u32 pause_pkt1; + u32 pause_pkt2; + u32 pause_pkt3; + u32 pause_pkt4; + u32 pause_pkt5; + u32 reserve[2]; + struct pch_gbe_regs_mac_adr mac_adr[16]; + u32 addr_mask; + u32 miim; + u32 mac_addr_load; + u32 rgmii_st; + u32 rgmii_ctrl; + u32 reserve3[3]; + u32 dma_ctrl; + u32 reserve4[3]; + u32 rx_dsc_base; + u32 rx_dsc_size; + u32 rx_dsc_hw_p; + u32 rx_dsc_hw_p_hld; + u32 rx_dsc_sw_p; + u32 reserve5[3]; + u32 tx_dsc_base; + u32 tx_dsc_size; + u32 tx_dsc_hw_p; + u32 tx_dsc_hw_p_hld; + u32 tx_dsc_sw_p; + u32 reserve6[3]; + u32 rx_dma_st; + u32 tx_dma_st; + u32 reserve7[2]; + u32 wol_st; + u32 wol_ctrl; + u32 wol_addr_mask; +}; + +struct pch_gbe_priv { + struct pch_gbe_rx_desc rx_desc[PCH_GBE_DESC_NUM]; + struct pch_gbe_tx_desc tx_desc[PCH_GBE_DESC_NUM]; + char rx_buff[PCH_GBE_DESC_NUM][PCH_GBE_RX_FRAME_LEN]; + struct phy_device *phydev; + struct mii_dev *bus; + struct pch_gbe_regs *mac_regs; + pci_dev_t bdf; + int rx_idx; + int tx_idx; +}; + +#endif /* _PCH_GBE_H_ */ diff --git a/sources/uboot-be550/drivers/net/pcnet.c b/sources/uboot-be550/drivers/net/pcnet.c new file mode 100644 index 00000000..cfcb1b4e --- /dev/null +++ b/sources/uboot-be550/drivers/net/pcnet.c @@ -0,0 +1,542 @@ +/* + * (C) Copyright 2002 Wolfgang Grandegger, wg@denx.de. + * + * This driver for AMD PCnet network controllers is derived from the + * Linux driver pcnet32.c written 1996-1999 by Thomas Bogendoerfer. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +#define PCNET_DEBUG_LEVEL 0 /* 0=off, 1=init, 2=rx/tx */ + +#define PCNET_DEBUG1(fmt,args...) \ + debug_cond(PCNET_DEBUG_LEVEL > 0, fmt ,##args) +#define PCNET_DEBUG2(fmt,args...) \ + debug_cond(PCNET_DEBUG_LEVEL > 1, fmt ,##args) + +#if !defined(CONF_PCNET_79C973) && defined(CONF_PCNET_79C975) +#error "Macro for PCnet chip version is not defined!" +#endif + +/* + * Set the number of Tx and Rx buffers, using Log_2(# buffers). + * Reasonable default values are 4 Tx buffers, and 16 Rx buffers. + * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4). + */ +#define PCNET_LOG_TX_BUFFERS 0 +#define PCNET_LOG_RX_BUFFERS 2 + +#define TX_RING_SIZE (1 << (PCNET_LOG_TX_BUFFERS)) +#define TX_RING_LEN_BITS ((PCNET_LOG_TX_BUFFERS) << 12) + +#define RX_RING_SIZE (1 << (PCNET_LOG_RX_BUFFERS)) +#define RX_RING_LEN_BITS ((PCNET_LOG_RX_BUFFERS) << 4) + +#define PKT_BUF_SZ 1544 + +/* The PCNET Rx and Tx ring descriptors. */ +struct pcnet_rx_head { + u32 base; + s16 buf_length; + s16 status; + u32 msg_length; + u32 reserved; +}; + +struct pcnet_tx_head { + u32 base; + s16 length; + s16 status; + u32 misc; + u32 reserved; +}; + +/* The PCNET 32-Bit initialization block, described in databook. */ +struct pcnet_init_block { + u16 mode; + u16 tlen_rlen; + u8 phys_addr[6]; + u16 reserved; + u32 filter[2]; + /* Receive and transmit ring base, along with extra bits. */ + u32 rx_ring; + u32 tx_ring; + u32 reserved2; +}; + +struct pcnet_uncached_priv { + struct pcnet_rx_head rx_ring[RX_RING_SIZE]; + struct pcnet_tx_head tx_ring[TX_RING_SIZE]; + struct pcnet_init_block init_block; +}; + +typedef struct pcnet_priv { + struct pcnet_uncached_priv *uc; + /* Receive Buffer space */ + unsigned char (*rx_buf)[RX_RING_SIZE][PKT_BUF_SZ + 4]; + int cur_rx; + int cur_tx; +} pcnet_priv_t; + +static pcnet_priv_t *lp; + +/* Offsets from base I/O address for WIO mode */ +#define PCNET_RDP 0x10 +#define PCNET_RAP 0x12 +#define PCNET_RESET 0x14 +#define PCNET_BDP 0x16 + +static u16 pcnet_read_csr(struct eth_device *dev, int index) +{ + outw(index, dev->iobase + PCNET_RAP); + return inw(dev->iobase + PCNET_RDP); +} + +static void pcnet_write_csr(struct eth_device *dev, int index, u16 val) +{ + outw(index, dev->iobase + PCNET_RAP); + outw(val, dev->iobase + PCNET_RDP); +} + +static u16 pcnet_read_bcr(struct eth_device *dev, int index) +{ + outw(index, dev->iobase + PCNET_RAP); + return inw(dev->iobase + PCNET_BDP); +} + +static void pcnet_write_bcr(struct eth_device *dev, int index, u16 val) +{ + outw(index, dev->iobase + PCNET_RAP); + outw(val, dev->iobase + PCNET_BDP); +} + +static void pcnet_reset(struct eth_device *dev) +{ + inw(dev->iobase + PCNET_RESET); +} + +static int pcnet_check(struct eth_device *dev) +{ + outw(88, dev->iobase + PCNET_RAP); + return inw(dev->iobase + PCNET_RAP) == 88; +} + +static int pcnet_init (struct eth_device *dev, bd_t * bis); +static int pcnet_send(struct eth_device *dev, void *packet, int length); +static int pcnet_recv (struct eth_device *dev); +static void pcnet_halt (struct eth_device *dev); +static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_num); + +#define PCI_TO_MEM(d, a) pci_virt_to_mem((pci_dev_t)d->priv, (a)) +#define PCI_TO_MEM_LE(d,a) (u32)(cpu_to_le32(PCI_TO_MEM(d,a))) + +static struct pci_device_id supported[] = { + {PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE}, + {} +}; + + +int pcnet_initialize(bd_t *bis) +{ + pci_dev_t devbusfn; + struct eth_device *dev; + u16 command, status; + int dev_nr = 0; + + PCNET_DEBUG1("\npcnet_initialize...\n"); + + for (dev_nr = 0;; dev_nr++) { + + /* + * Find the PCnet PCI device(s). + */ + devbusfn = pci_find_devices(supported, dev_nr); + if (devbusfn < 0) + break; + + /* + * Allocate and pre-fill the device structure. + */ + dev = (struct eth_device *)malloc(sizeof(*dev)); + if (!dev) { + printf("pcnet: Can not allocate memory\n"); + break; + } + memset(dev, 0, sizeof(*dev)); + dev->priv = (void *)devbusfn; + sprintf(dev->name, "pcnet#%d", dev_nr); + + /* + * Setup the PCI device. + */ + pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, + (unsigned int *)&dev->iobase); + dev->iobase = pci_io_to_phys(devbusfn, dev->iobase); + dev->iobase &= ~0xf; + + PCNET_DEBUG1("%s: devbusfn=0x%x iobase=0x%x: ", + dev->name, devbusfn, dev->iobase); + + command = PCI_COMMAND_IO | PCI_COMMAND_MASTER; + pci_write_config_word(devbusfn, PCI_COMMAND, command); + pci_read_config_word(devbusfn, PCI_COMMAND, &status); + if ((status & command) != command) { + printf("%s: Couldn't enable IO access or Bus Mastering\n", + dev->name); + free(dev); + continue; + } + + pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x40); + + /* + * Probe the PCnet chip. + */ + if (pcnet_probe(dev, bis, dev_nr) < 0) { + free(dev); + continue; + } + + /* + * Setup device structure and register the driver. + */ + dev->init = pcnet_init; + dev->halt = pcnet_halt; + dev->send = pcnet_send; + dev->recv = pcnet_recv; + + eth_register(dev); + } + + udelay(10 * 1000); + + return dev_nr; +} + +static int pcnet_probe(struct eth_device *dev, bd_t *bis, int dev_nr) +{ + int chip_version; + char *chipname; + +#ifdef PCNET_HAS_PROM + int i; +#endif + + /* Reset the PCnet controller */ + pcnet_reset(dev); + + /* Check if register access is working */ + if (pcnet_read_csr(dev, 0) != 4 || !pcnet_check(dev)) { + printf("%s: CSR register access check failed\n", dev->name); + return -1; + } + + /* Identify the chip */ + chip_version = + pcnet_read_csr(dev, 88) | (pcnet_read_csr(dev, 89) << 16); + if ((chip_version & 0xfff) != 0x003) + return -1; + chip_version = (chip_version >> 12) & 0xffff; + switch (chip_version) { + case 0x2621: + chipname = "PCnet/PCI II 79C970A"; /* PCI */ + break; +#ifdef CONFIG_PCNET_79C973 + case 0x2625: + chipname = "PCnet/FAST III 79C973"; /* PCI */ + break; +#endif +#ifdef CONFIG_PCNET_79C975 + case 0x2627: + chipname = "PCnet/FAST III 79C975"; /* PCI */ + break; +#endif + default: + printf("%s: PCnet version %#x not supported\n", + dev->name, chip_version); + return -1; + } + + PCNET_DEBUG1("AMD %s\n", chipname); + +#ifdef PCNET_HAS_PROM + /* + * In most chips, after a chip reset, the ethernet address is read from + * the station address PROM at the base address and programmed into the + * "Physical Address Registers" CSR12-14. + */ + for (i = 0; i < 3; i++) { + unsigned int val; + + val = pcnet_read_csr(dev, i + 12) & 0x0ffff; + /* There may be endianness issues here. */ + dev->enetaddr[2 * i] = val & 0x0ff; + dev->enetaddr[2 * i + 1] = (val >> 8) & 0x0ff; + } +#endif /* PCNET_HAS_PROM */ + + return 0; +} + +static int pcnet_init(struct eth_device *dev, bd_t *bis) +{ + struct pcnet_uncached_priv *uc; + int i, val; + u32 addr; + + PCNET_DEBUG1("%s: pcnet_init...\n", dev->name); + + /* Switch pcnet to 32bit mode */ + pcnet_write_bcr(dev, 20, 2); + + /* Set/reset autoselect bit */ + val = pcnet_read_bcr(dev, 2) & ~2; + val |= 2; + pcnet_write_bcr(dev, 2, val); + + /* Enable auto negotiate, setup, disable fd */ + val = pcnet_read_bcr(dev, 32) & ~0x98; + val |= 0x20; + pcnet_write_bcr(dev, 32, val); + + /* + * Enable NOUFLO on supported controllers, with the transmit + * start point set to the full packet. This will cause entire + * packets to be buffered by the ethernet controller before + * transmission, eliminating underflows which are common on + * slower devices. Controllers which do not support NOUFLO will + * simply be left with a larger transmit FIFO threshold. + */ + val = pcnet_read_bcr(dev, 18); + val |= 1 << 11; + pcnet_write_bcr(dev, 18, val); + val = pcnet_read_csr(dev, 80); + val |= 0x3 << 10; + pcnet_write_csr(dev, 80, val); + + /* + * We only maintain one structure because the drivers will never + * be used concurrently. In 32bit mode the RX and TX ring entries + * must be aligned on 16-byte boundaries. + */ + if (lp == NULL) { + addr = (u32)malloc(sizeof(pcnet_priv_t) + 0x10); + addr = (addr + 0xf) & ~0xf; + lp = (pcnet_priv_t *)addr; + + addr = (u32)memalign(ARCH_DMA_MINALIGN, sizeof(*lp->uc)); + flush_dcache_range(addr, addr + sizeof(*lp->uc)); + addr = UNCACHED_SDRAM(addr); + lp->uc = (struct pcnet_uncached_priv *)addr; + + addr = (u32)memalign(ARCH_DMA_MINALIGN, sizeof(*lp->rx_buf)); + flush_dcache_range(addr, addr + sizeof(*lp->rx_buf)); + lp->rx_buf = (void *)addr; + } + + uc = lp->uc; + + uc->init_block.mode = cpu_to_le16(0x0000); + uc->init_block.filter[0] = 0x00000000; + uc->init_block.filter[1] = 0x00000000; + + /* + * Initialize the Rx ring. + */ + lp->cur_rx = 0; + for (i = 0; i < RX_RING_SIZE; i++) { + uc->rx_ring[i].base = PCI_TO_MEM_LE(dev, (*lp->rx_buf)[i]); + uc->rx_ring[i].buf_length = cpu_to_le16(-PKT_BUF_SZ); + uc->rx_ring[i].status = cpu_to_le16(0x8000); + PCNET_DEBUG1 + ("Rx%d: base=0x%x buf_length=0x%hx status=0x%hx\n", i, + uc->rx_ring[i].base, uc->rx_ring[i].buf_length, + uc->rx_ring[i].status); + } + + /* + * Initialize the Tx ring. The Tx buffer address is filled in as + * needed, but we do need to clear the upper ownership bit. + */ + lp->cur_tx = 0; + for (i = 0; i < TX_RING_SIZE; i++) { + uc->tx_ring[i].base = 0; + uc->tx_ring[i].status = 0; + } + + /* + * Setup Init Block. + */ + PCNET_DEBUG1("Init block at 0x%p: MAC", &lp->uc->init_block); + + for (i = 0; i < 6; i++) { + lp->uc->init_block.phys_addr[i] = dev->enetaddr[i]; + PCNET_DEBUG1(" %02x", lp->uc->init_block.phys_addr[i]); + } + + uc->init_block.tlen_rlen = cpu_to_le16(TX_RING_LEN_BITS | + RX_RING_LEN_BITS); + uc->init_block.rx_ring = PCI_TO_MEM_LE(dev, uc->rx_ring); + uc->init_block.tx_ring = PCI_TO_MEM_LE(dev, uc->tx_ring); + + PCNET_DEBUG1("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n", + uc->init_block.tlen_rlen, + uc->init_block.rx_ring, uc->init_block.tx_ring); + + /* + * Tell the controller where the Init Block is located. + */ + barrier(); + addr = PCI_TO_MEM(dev, &lp->uc->init_block); + pcnet_write_csr(dev, 1, addr & 0xffff); + pcnet_write_csr(dev, 2, (addr >> 16) & 0xffff); + + pcnet_write_csr(dev, 4, 0x0915); + pcnet_write_csr(dev, 0, 0x0001); /* start */ + + /* Wait for Init Done bit */ + for (i = 10000; i > 0; i--) { + if (pcnet_read_csr(dev, 0) & 0x0100) + break; + udelay(10); + } + if (i <= 0) { + printf("%s: TIMEOUT: controller init failed\n", dev->name); + pcnet_reset(dev); + return -1; + } + + /* + * Finally start network controller operation. + */ + pcnet_write_csr(dev, 0, 0x0002); + + return 0; +} + +static int pcnet_send(struct eth_device *dev, void *packet, int pkt_len) +{ + int i, status; + struct pcnet_tx_head *entry = &lp->uc->tx_ring[lp->cur_tx]; + + PCNET_DEBUG2("Tx%d: %d bytes from 0x%p ", lp->cur_tx, pkt_len, + packet); + + flush_dcache_range((unsigned long)packet, + (unsigned long)packet + pkt_len); + + /* Wait for completion by testing the OWN bit */ + for (i = 1000; i > 0; i--) { + status = readw(&entry->status); + if ((status & 0x8000) == 0) + break; + udelay(100); + PCNET_DEBUG2("."); + } + if (i <= 0) { + printf("%s: TIMEOUT: Tx%d failed (status = 0x%x)\n", + dev->name, lp->cur_tx, status); + pkt_len = 0; + goto failure; + } + + /* + * Setup Tx ring. Caution: the write order is important here, + * set the status with the "ownership" bits last. + */ + writew(-pkt_len, &entry->length); + writel(0, &entry->misc); + writel(PCI_TO_MEM(dev, packet), &entry->base); + writew(0x8300, &entry->status); + + /* Trigger an immediate send poll. */ + pcnet_write_csr(dev, 0, 0x0008); + + failure: + if (++lp->cur_tx >= TX_RING_SIZE) + lp->cur_tx = 0; + + PCNET_DEBUG2("done\n"); + return pkt_len; +} + +static int pcnet_recv (struct eth_device *dev) +{ + struct pcnet_rx_head *entry; + unsigned char *buf; + int pkt_len = 0; + u16 status, err_status; + + while (1) { + entry = &lp->uc->rx_ring[lp->cur_rx]; + /* + * If we own the next entry, it's a new packet. Send it up. + */ + status = readw(&entry->status); + if ((status & 0x8000) != 0) + break; + err_status = status >> 8; + + if (err_status != 0x03) { /* There was an error. */ + printf("%s: Rx%d", dev->name, lp->cur_rx); + PCNET_DEBUG1(" (status=0x%x)", err_status); + if (err_status & 0x20) + printf(" Frame"); + if (err_status & 0x10) + printf(" Overflow"); + if (err_status & 0x08) + printf(" CRC"); + if (err_status & 0x04) + printf(" Fifo"); + printf(" Error\n"); + status &= 0x03ff; + + } else { + pkt_len = (readl(&entry->msg_length) & 0xfff) - 4; + if (pkt_len < 60) { + printf("%s: Rx%d: invalid packet length %d\n", + dev->name, lp->cur_rx, pkt_len); + } else { + buf = (*lp->rx_buf)[lp->cur_rx]; + invalidate_dcache_range((unsigned long)buf, + (unsigned long)buf + pkt_len); + net_process_received_packet(buf, pkt_len); + PCNET_DEBUG2("Rx%d: %d bytes from 0x%p\n", + lp->cur_rx, pkt_len, buf); + } + } + + status |= 0x8000; + writew(status, &entry->status); + + if (++lp->cur_rx >= RX_RING_SIZE) + lp->cur_rx = 0; + } + return pkt_len; +} + +static void pcnet_halt(struct eth_device *dev) +{ + int i; + + PCNET_DEBUG1("%s: pcnet_halt...\n", dev->name); + + /* Reset the PCnet controller */ + pcnet_reset(dev); + + /* Wait for Stop bit */ + for (i = 1000; i > 0; i--) { + if (pcnet_read_csr(dev, 0) & 0x4) + break; + udelay(10); + } + if (i <= 0) + printf("%s: TIMEOUT: controller reset failed\n", dev->name); +} diff --git a/sources/uboot-be550/drivers/net/phy/Makefile b/sources/uboot-be550/drivers/net/phy/Makefile new file mode 100644 index 00000000..9e4d4927 --- /dev/null +++ b/sources/uboot-be550/drivers/net/phy/Makefile @@ -0,0 +1,28 @@ +# +# (C) Copyright 2008 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_BITBANGMII) += miiphybb.o +obj-$(CONFIG_MV88E61XX_SWITCH) += mv88e61xx.o +obj-$(CONFIG_MV88E6352_SWITCH) += mv88e6352.o + +obj-$(CONFIG_PHYLIB) += phy.o +obj-$(CONFIG_PHYLIB_10G) += generic_10g.o +obj-$(CONFIG_PHY_AQUANTIA) += aquantia.o +obj-$(CONFIG_PHY_ATHEROS) += atheros.o +obj-$(CONFIG_PHY_BROADCOM) += broadcom.o +obj-$(CONFIG_PHY_CORTINA) += cortina.o +obj-$(CONFIG_PHY_DAVICOM) += davicom.o +obj-$(CONFIG_PHY_ET1011C) += et1011c.o +obj-$(CONFIG_PHY_LXT) += lxt.o +obj-$(CONFIG_PHY_MARVELL) += marvell.o +obj-$(CONFIG_PHY_MICREL) += micrel.o +obj-$(CONFIG_PHY_NATSEMI) += natsemi.o +obj-$(CONFIG_PHY_REALTEK) += realtek.o +obj-$(CONFIG_PHY_SMSC) += smsc.o +obj-$(CONFIG_PHY_TERANETICS) += teranetics.o +obj-$(CONFIG_PHY_TI) += ti.o +obj-$(CONFIG_PHY_VITESSE) += vitesse.o diff --git a/sources/uboot-be550/drivers/net/phy/aquantia.c b/sources/uboot-be550/drivers/net/phy/aquantia.c new file mode 100644 index 00000000..f90c2ae3 --- /dev/null +++ b/sources/uboot-be550/drivers/net/phy/aquantia.c @@ -0,0 +1,171 @@ +/* + * Aquantia PHY drivers + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Copyright 2014 Freescale Semiconductor, Inc. + */ +#include +#include +#include + +#ifndef CONFIG_PHYLIB_10G +#error The Aquantia PHY needs 10G support +#endif + +#define AQUNTIA_10G_CTL 0x20 +#define AQUNTIA_VENDOR_P1 0xc400 + +#define AQUNTIA_SPEED_LSB_MASK 0x2000 +#define AQUNTIA_SPEED_MSB_MASK 0x40 + +int aquantia_config(struct phy_device *phydev) +{ + u32 val = phy_read(phydev, MDIO_MMD_PMAPMD, MII_BMCR); + + if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { + /* 1000BASE-T mode */ + phydev->advertising = SUPPORTED_1000baseT_Full; + phydev->supported = phydev->advertising; + + val = (val & ~AQUNTIA_SPEED_LSB_MASK) | AQUNTIA_SPEED_MSB_MASK; + phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, val); + } else if (phydev->interface == PHY_INTERFACE_MODE_XGMII) { + /* 10GBASE-T mode */ + phydev->advertising = SUPPORTED_10000baseT_Full; + phydev->supported = phydev->advertising; + + if (!(val & AQUNTIA_SPEED_LSB_MASK) || + !(val & AQUNTIA_SPEED_MSB_MASK)) + phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, + AQUNTIA_SPEED_LSB_MASK | + AQUNTIA_SPEED_MSB_MASK); + } else if (phydev->interface == PHY_INTERFACE_MODE_SGMII_2500) { + /* 2.5GBASE-T mode */ + phydev->advertising = SUPPORTED_1000baseT_Full; + phydev->supported = phydev->advertising; + + phy_write(phydev, MDIO_MMD_AN, AQUNTIA_10G_CTL, 1); + phy_write(phydev, MDIO_MMD_AN, AQUNTIA_VENDOR_P1, 0x9440); + } else if (phydev->interface == PHY_INTERFACE_MODE_MII) { + /* 100BASE-TX mode */ + phydev->advertising = SUPPORTED_100baseT_Full; + phydev->supported = phydev->advertising; + + val = (val & ~AQUNTIA_SPEED_MSB_MASK) | AQUNTIA_SPEED_LSB_MASK; + phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, val); + } + return 0; +} + +int aquantia_startup(struct phy_device *phydev) +{ + u32 reg, speed; + int i = 0; + + phydev->duplex = DUPLEX_FULL; + + /* if the AN is still in progress, wait till timeout. */ + phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1); + reg = phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1); + if (!(reg & MDIO_AN_STAT1_COMPLETE)) { + printf("%s Waiting for PHY auto negotiation to complete", + phydev->dev->name); + do { + udelay(1000); + reg = phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1); + if ((i++ % 500) == 0) + printf("."); + } while (!(reg & MDIO_AN_STAT1_COMPLETE) && + i < (4 * PHY_ANEG_TIMEOUT)); + + if (i > PHY_ANEG_TIMEOUT) + printf(" TIMEOUT !\n"); + } + + /* Read twice because link state is latched and a + * read moves the current state into the register */ + phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1); + reg = phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1); + if (reg < 0 || !(reg & MDIO_STAT1_LSTATUS)) + phydev->link = 0; + else + phydev->link = 1; + + speed = phy_read(phydev, MDIO_MMD_PMAPMD, MII_BMCR); + if (speed & AQUNTIA_SPEED_MSB_MASK) { + if (speed & AQUNTIA_SPEED_LSB_MASK) + phydev->speed = SPEED_10000; + else + phydev->speed = SPEED_1000; + } else { + if (speed & AQUNTIA_SPEED_LSB_MASK) + phydev->speed = SPEED_100; + else + phydev->speed = SPEED_10; + } + + return 0; +} + +struct phy_driver aq1202_driver = { + .name = "Aquantia AQ1202", + .uid = 0x3a1b445, + .mask = 0xfffffff0, + .features = PHY_10G_FEATURES, + .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS| + MDIO_MMD_PHYXS | MDIO_MMD_AN | + MDIO_MMD_VEND1), + .config = &aquantia_config, + .startup = &aquantia_startup, + .shutdown = &gen10g_shutdown, +}; + +struct phy_driver aq2104_driver = { + .name = "Aquantia AQ2104", + .uid = 0x3a1b460, + .mask = 0xfffffff0, + .features = PHY_10G_FEATURES, + .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS| + MDIO_MMD_PHYXS | MDIO_MMD_AN | + MDIO_MMD_VEND1), + .config = &aquantia_config, + .startup = &aquantia_startup, + .shutdown = &gen10g_shutdown, +}; + +struct phy_driver aqr105_driver = { + .name = "Aquantia AQR105", + .uid = 0x3a1b4a2, + .mask = 0xfffffff0, + .features = PHY_10G_FEATURES, + .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS| + MDIO_MMD_PHYXS | MDIO_MMD_AN | + MDIO_MMD_VEND1), + .config = &aquantia_config, + .startup = &aquantia_startup, + .shutdown = &gen10g_shutdown, +}; + +struct phy_driver aqr405_driver = { + .name = "Aquantia AQR405", + .uid = 0x3a1b4b2, + .mask = 0xfffffff0, + .features = PHY_10G_FEATURES, + .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS| + MDIO_MMD_PHYXS | MDIO_MMD_AN | + MDIO_MMD_VEND1), + .config = &aquantia_config, + .startup = &aquantia_startup, + .shutdown = &gen10g_shutdown, +}; + +int phy_aquantia_init(void) +{ + phy_register(&aq1202_driver); + phy_register(&aq2104_driver); + phy_register(&aqr105_driver); + phy_register(&aqr405_driver); + + return 0; +} diff --git a/sources/uboot-be550/drivers/net/phy/atheros.c b/sources/uboot-be550/drivers/net/phy/atheros.c new file mode 100644 index 00000000..ba57b1a4 --- /dev/null +++ b/sources/uboot-be550/drivers/net/phy/atheros.c @@ -0,0 +1,76 @@ +/* + * Atheros PHY drivers + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Copyright 2011, 2013 Freescale Semiconductor, Inc. + * author Andy Fleming + */ +#include + +static int ar8021_config(struct phy_device *phydev) +{ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47); + + phydev->supported = phydev->drv->features; + return 0; +} + +static int ar8035_config(struct phy_device *phydev) +{ + int regval; + + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x0007); + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); + regval = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, (regval|0x0018)); + + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); + regval = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, (regval|0x0100)); + + phydev->supported = phydev->drv->features; + + return 0; +} + +static struct phy_driver AR8021_driver = { + .name = "AR8021", + .uid = 0x4dd040, + .mask = 0x4ffff0, + .features = PHY_GBIT_FEATURES, + .config = ar8021_config, + .startup = genphy_startup, + .shutdown = genphy_shutdown, +}; + +static struct phy_driver AR8031_driver = { + .name = "AR8031/AR8033", + .uid = 0x4dd074, + .mask = 0xffffffef, + .features = PHY_GBIT_FEATURES, + .config = ar8035_config, + .startup = genphy_startup, + .shutdown = genphy_shutdown, +}; + +static struct phy_driver AR8035_driver = { + .name = "AR8035", + .uid = 0x4dd072, + .mask = 0xffffffef, + .features = PHY_GBIT_FEATURES, + .config = ar8035_config, + .startup = genphy_startup, + .shutdown = genphy_shutdown, +}; + +int phy_atheros_init(void) +{ + phy_register(&AR8021_driver); + phy_register(&AR8031_driver); + phy_register(&AR8035_driver); + + return 0; +} diff --git a/sources/uboot-be550/drivers/net/phy/broadcom.c b/sources/uboot-be550/drivers/net/phy/broadcom.c new file mode 100644 index 00000000..4b2808ef --- /dev/null +++ b/sources/uboot-be550/drivers/net/phy/broadcom.c @@ -0,0 +1,303 @@ +/* + * Broadcom PHY drivers + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Copyright 2010-2011 Freescale Semiconductor, Inc. + * author Andy Fleming + */ +#include +#include +#include + +/* Broadcom BCM54xx -- taken from linux sungem_phy */ +#define MIIM_BCM54xx_AUXCNTL 0x18 +#define MIIM_BCM54xx_AUXCNTL_ENCODE(val) (((val & 0x7) << 12)|(val & 0x7)) +#define MIIM_BCM54xx_AUXSTATUS 0x19 +#define MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK 0x0700 +#define MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT 8 + +#define MIIM_BCM54XX_SHD 0x1c +#define MIIM_BCM54XX_SHD_WRITE 0x8000 +#define MIIM_BCM54XX_SHD_VAL(x) ((x & 0x1f) << 10) +#define MIIM_BCM54XX_SHD_DATA(x) ((x & 0x3ff) << 0) +#define MIIM_BCM54XX_SHD_WR_ENCODE(val, data) \ + (MIIM_BCM54XX_SHD_WRITE | MIIM_BCM54XX_SHD_VAL(val) | \ + MIIM_BCM54XX_SHD_DATA(data)) + +#define MIIM_BCM54XX_EXP_DATA 0x15 /* Expansion register data */ +#define MIIM_BCM54XX_EXP_SEL 0x17 /* Expansion register select */ +#define MIIM_BCM54XX_EXP_SEL_SSD 0x0e00 /* Secondary SerDes select */ +#define MIIM_BCM54XX_EXP_SEL_ER 0x0f00 /* Expansion register select */ + +/* Broadcom BCM5461S */ +static int bcm5461_config(struct phy_device *phydev) +{ + genphy_config_aneg(phydev); + + phy_reset(phydev); + + return 0; +} + +static int bcm54xx_parse_status(struct phy_device *phydev) +{ + unsigned int mii_reg; + + mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXSTATUS); + + switch ((mii_reg & MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK) >> + MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT) { + case 1: + phydev->duplex = DUPLEX_HALF; + phydev->speed = SPEED_10; + break; + case 2: + phydev->duplex = DUPLEX_FULL; + phydev->speed = SPEED_10; + break; + case 3: + phydev->duplex = DUPLEX_HALF; + phydev->speed = SPEED_100; + break; + case 5: + phydev->duplex = DUPLEX_FULL; + phydev->speed = SPEED_100; + break; + case 6: + phydev->duplex = DUPLEX_HALF; + phydev->speed = SPEED_1000; + break; + case 7: + phydev->duplex = DUPLEX_FULL; + phydev->speed = SPEED_1000; + break; + default: + printf("Auto-neg error, defaulting to 10BT/HD\n"); + phydev->duplex = DUPLEX_HALF; + phydev->speed = SPEED_10; + break; + } + + return 0; +} + +static int bcm54xx_startup(struct phy_device *phydev) +{ + /* Read the Status (2x to make sure link is right) */ + genphy_update_link(phydev); + bcm54xx_parse_status(phydev); + + return 0; +} + +/* Broadcom BCM5482S */ +/* + * "Ethernet@Wirespeed" needs to be enabled to achieve link in certain + * circumstances. eg a gigabit TSEC connected to a gigabit switch with + * a 4-wire ethernet cable. Both ends advertise gigabit, but can't + * link. "Ethernet@Wirespeed" reduces advertised speed until link + * can be achieved. + */ +static u32 bcm5482_read_wirespeed(struct phy_device *phydev, u32 reg) +{ + return (phy_read(phydev, MDIO_DEVAD_NONE, reg) & 0x8FFF) | 0x8010; +} + +static int bcm5482_config(struct phy_device *phydev) +{ + unsigned int reg; + + /* reset the PHY */ + reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); + reg |= BMCR_RESET; + phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, reg); + + /* Setup read from auxilary control shadow register 7 */ + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL, + MIIM_BCM54xx_AUXCNTL_ENCODE(7)); + /* Read Misc Control register and or in Ethernet@Wirespeed */ + reg = bcm5482_read_wirespeed(phydev, MIIM_BCM54xx_AUXCNTL); + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL, reg); + + /* Initial config/enable of secondary SerDes interface */ + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_SHD, + MIIM_BCM54XX_SHD_WR_ENCODE(0x14, 0xf)); + /* Write intial value to secondary SerDes Contol */ + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_SEL, + MIIM_BCM54XX_EXP_SEL_SSD | 0); + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_DATA, + BMCR_ANRESTART); + /* Enable copper/fiber auto-detect */ + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_SHD, + MIIM_BCM54XX_SHD_WR_ENCODE(0x1e, 0x201)); + + genphy_config_aneg(phydev); + + return 0; +} + +static int bcm_cygnus_startup(struct phy_device *phydev) +{ + /* Read the Status (2x to make sure link is right) */ + genphy_update_link(phydev); + genphy_parse_link(phydev); + + return 0; +} + +static int bcm_cygnus_config(struct phy_device *phydev) +{ + genphy_config_aneg(phydev); + + phy_reset(phydev); + + return 0; +} + +/* + * Find out if PHY is in copper or serdes mode by looking at Expansion Reg + * 0x42 - "Operating Mode Status Register" + */ +static int bcm5482_is_serdes(struct phy_device *phydev) +{ + u16 val; + int serdes = 0; + + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_SEL, + MIIM_BCM54XX_EXP_SEL_ER | 0x42); + val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_DATA); + + switch (val & 0x1f) { + case 0x0d: /* RGMII-to-100Base-FX */ + case 0x0e: /* RGMII-to-SGMII */ + case 0x0f: /* RGMII-to-SerDes */ + case 0x12: /* SGMII-to-SerDes */ + case 0x13: /* SGMII-to-100Base-FX */ + case 0x16: /* SerDes-to-Serdes */ + serdes = 1; + break; + case 0x6: /* RGMII-to-Copper */ + case 0x14: /* SGMII-to-Copper */ + case 0x17: /* SerDes-to-Copper */ + break; + default: + printf("ERROR, invalid PHY mode (0x%x\n)", val); + break; + } + + return serdes; +} + +/* + * Determine SerDes link speed and duplex from Expansion reg 0x42 "Operating + * Mode Status Register" + */ +static u32 bcm5482_parse_serdes_sr(struct phy_device *phydev) +{ + u16 val; + int i = 0; + + /* Wait 1s for link - Clause 37 autonegotiation happens very fast */ + while (1) { + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_SEL, + MIIM_BCM54XX_EXP_SEL_ER | 0x42); + val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_DATA); + + if (val & 0x8000) + break; + + if (i++ > 1000) { + phydev->link = 0; + return 1; + } + + udelay(1000); /* 1 ms */ + } + + phydev->link = 1; + switch ((val >> 13) & 0x3) { + case (0x00): + phydev->speed = 10; + break; + case (0x01): + phydev->speed = 100; + break; + case (0x02): + phydev->speed = 1000; + break; + } + + phydev->duplex = (val & 0x1000) == 0x1000; + + return 0; +} + +/* + * Figure out if BCM5482 is in serdes or copper mode and determine link + * configuration accordingly + */ +static int bcm5482_startup(struct phy_device *phydev) +{ + if (bcm5482_is_serdes(phydev)) { + bcm5482_parse_serdes_sr(phydev); + phydev->port = PORT_FIBRE; + } else { + /* Wait for auto-negotiation to complete or fail */ + genphy_update_link(phydev); + /* Parse BCM54xx copper aux status register */ + bcm54xx_parse_status(phydev); + } + + return 0; +} + +static struct phy_driver BCM5461S_driver = { + .name = "Broadcom BCM5461S", + .uid = 0x2060c0, + .mask = 0xfffff0, + .features = PHY_GBIT_FEATURES, + .config = &bcm5461_config, + .startup = &bcm54xx_startup, + .shutdown = &genphy_shutdown, +}; + +static struct phy_driver BCM5464S_driver = { + .name = "Broadcom BCM5464S", + .uid = 0x2060b0, + .mask = 0xfffff0, + .features = PHY_GBIT_FEATURES, + .config = &bcm5461_config, + .startup = &bcm54xx_startup, + .shutdown = &genphy_shutdown, +}; + +static struct phy_driver BCM5482S_driver = { + .name = "Broadcom BCM5482S", + .uid = 0x143bcb0, + .mask = 0xffffff0, + .features = PHY_GBIT_FEATURES, + .config = &bcm5482_config, + .startup = &bcm5482_startup, + .shutdown = &genphy_shutdown, +}; + +static struct phy_driver BCM_CYGNUS_driver = { + .name = "Broadcom CYGNUS GPHY", + .uid = 0xae025200, + .mask = 0xfffff0, + .features = PHY_GBIT_FEATURES, + .config = &bcm_cygnus_config, + .startup = &bcm_cygnus_startup, + .shutdown = &genphy_shutdown, +}; + +int phy_broadcom_init(void) +{ + phy_register(&BCM5482S_driver); + phy_register(&BCM5464S_driver); + phy_register(&BCM5461S_driver); + phy_register(&BCM_CYGNUS_driver); + + return 0; +} diff --git a/sources/uboot-be550/drivers/net/phy/cortina.c b/sources/uboot-be550/drivers/net/phy/cortina.c new file mode 100644 index 00000000..3a2b3bba --- /dev/null +++ b/sources/uboot-be550/drivers/net/phy/cortina.c @@ -0,0 +1,333 @@ +/* + * Cortina CS4315/CS4340 10G PHY drivers + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Copyright 2014 Freescale Semiconductor, Inc. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_SYS_CORTINA_FW_IN_NAND +#include +#elif defined(CONFIG_SYS_CORTINA_FW_IN_SPIFLASH) +#include +#elif defined(CONFIG_SYS_CORTINA_FW_IN_MMC) +#include +#endif + +#ifndef CONFIG_PHYLIB_10G +#error The Cortina PHY needs 10G support +#endif + +struct cortina_reg_config cortina_reg_cfg[] = { + /* CS4315_enable_sr_mode */ + {VILLA_GLOBAL_MSEQCLKCTRL, 0x8004}, + {VILLA_MSEQ_OPTIONS, 0xf}, + {VILLA_MSEQ_PC, 0x0}, + {VILLA_MSEQ_BANKSELECT, 0x4}, + {VILLA_LINE_SDS_COMMON_SRX0_RX_CPA, 0x55}, + {VILLA_LINE_SDS_COMMON_SRX0_RX_LOOP_FILTER, 0x30}, + {VILLA_DSP_SDS_SERDES_SRX_DFE0_SELECT, 0x1}, + {VILLA_DSP_SDS_DSP_COEF_DFE0_SELECT, 0x2}, + {VILLA_LINE_SDS_COMMON_SRX0_RX_CPB, 0x2003}, + {VILLA_DSP_SDS_SERDES_SRX_FFE_DELAY_CTRL, 0xF047}, + {VILLA_MSEQ_ENABLE_MSB, 0x0000}, + {VILLA_MSEQ_SPARE21_LSB, 0x6}, + {VILLA_MSEQ_RESET_COUNT_LSB, 0x0}, + {VILLA_MSEQ_SPARE12_MSB, 0x0000}, + /* + * to invert the receiver path, uncomment the next line + * write (VILLA_MSEQ_SPARE12_MSB, 0x4000) + * + * SPARE2_LSB is used to configure the device while in sr mode to + * enable power savings and to use the optical module LOS signal. + * in power savings mode, the internal prbs checker can not be used. + * if the optical module LOS signal is used as an input to the micro + * code, then the micro code will wait until the optical module + * LOS = 0 before turning on the adaptive equalizer. + * Setting SPARE2_LSB bit 0 to 1 places the devie in power savings mode + * while setting bit 0 to 0 disables power savings mode. + * Setting SPARE2_LSB bit 2 to 0 configures the device to use the + * optical module LOS signal while setting bit 2 to 1 configures the + * device so that it will ignore the optical module LOS SPARE2_LSB = 0 + */ + + /* enable power savings, ignore optical module LOS */ + {VILLA_MSEQ_SPARE2_LSB, 0x5}, + + {VILLA_MSEQ_SPARE7_LSB, 0x1e}, + {VILLA_MSEQ_BANKSELECT, 0x4}, + {VILLA_MSEQ_SPARE9_LSB, 0x2}, + {VILLA_MSEQ_SPARE3_LSB, 0x0F53}, + {VILLA_MSEQ_SPARE3_MSB, 0x2006}, + {VILLA_MSEQ_SPARE8_LSB, 0x3FF7}, + {VILLA_MSEQ_SPARE8_MSB, 0x0A46}, + {VILLA_MSEQ_COEF8_FFE0_LSB, 0xD500}, + {VILLA_MSEQ_COEF8_FFE1_LSB, 0x0200}, + {VILLA_MSEQ_COEF8_FFE2_LSB, 0xBA00}, + {VILLA_MSEQ_COEF8_FFE3_LSB, 0x0100}, + {VILLA_MSEQ_COEF8_FFE4_LSB, 0x0300}, + {VILLA_MSEQ_COEF8_FFE5_LSB, 0x0300}, + {VILLA_MSEQ_COEF8_DFE0_LSB, 0x0700}, + {VILLA_MSEQ_COEF8_DFE0N_LSB, 0x0E00}, + {VILLA_MSEQ_COEF8_DFE1_LSB, 0x0B00}, + {VILLA_DSP_SDS_DSP_COEF_LARGE_LEAK, 0x2}, + {VILLA_DSP_SDS_SERDES_SRX_DAC_ENABLEB_LSB, 0xD000}, + {VILLA_MSEQ_POWER_DOWN_LSB, 0xFFFF}, + {VILLA_MSEQ_POWER_DOWN_MSB, 0x0}, + {VILLA_MSEQ_CAL_RX_SLICER, 0x80}, + {VILLA_DSP_SDS_SERDES_SRX_DAC_BIAS_SELECT1_MSB, 0x3f}, + {VILLA_GLOBAL_MSEQCLKCTRL, 0x4}, + {VILLA_MSEQ_OPTIONS, 0x7}, + + /* set up min value for ffe1 */ + {VILLA_MSEQ_COEF_INIT_SEL, 0x2}, + {VILLA_DSP_SDS_DSP_PRECODEDINITFFE21, 0x41}, + + /* CS4315_sr_rx_pre_eq_set_4in */ + {VILLA_GLOBAL_MSEQCLKCTRL, 0x8004}, + {VILLA_MSEQ_OPTIONS, 0xf}, + {VILLA_MSEQ_BANKSELECT, 0x4}, + {VILLA_MSEQ_PC, 0x0}, + + /* for lengths from 3.5 to 4.5inches */ + {VILLA_MSEQ_SERDES_PARAM_LSB, 0x0306}, + {VILLA_MSEQ_SPARE25_LSB, 0x0306}, + {VILLA_MSEQ_SPARE21_LSB, 0x2}, + {VILLA_MSEQ_SPARE23_LSB, 0x2}, + {VILLA_MSEQ_CAL_RX_DFE_EQ, 0x0}, + + {VILLA_GLOBAL_MSEQCLKCTRL, 0x4}, + {VILLA_MSEQ_OPTIONS, 0x7}, + + /* CS4315_rx_drive_4inch */ + /* for length 4inches */ + {VILLA_GLOBAL_VILLA2_COMPATIBLE, 0x0000}, + {VILLA_HOST_SDS_COMMON_STX0_TX_OUTPUT_CTRLA, 0x3023}, + {VILLA_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLB, 0xc01E}, + + /* CS4315_tx_drive_4inch */ + /* for length 4inches */ + {VILLA_GLOBAL_VILLA2_COMPATIBLE, 0x0000}, + {VILLA_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLA, 0x3023}, + {VILLA_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLB, 0xc01E}, +}; + +void cs4340_upload_firmware(struct phy_device *phydev) +{ + char line_temp[0x50] = {0}; + char reg_addr[0x50] = {0}; + char reg_data[0x50] = {0}; + int i, line_cnt = 0, column_cnt = 0; + struct cortina_reg_config fw_temp; + char *addr = NULL; + +#if defined(CONFIG_SYS_CORTINA_FW_IN_NOR) || \ + defined(CONFIG_SYS_CORTINA_FW_IN_REMOTE) + + addr = (char *)CONFIG_CORTINA_FW_ADDR; +#elif defined(CONFIG_SYS_CORTINA_FW_IN_NAND) + int ret; + size_t fw_length = CONFIG_CORTINA_FW_LENGTH; + + addr = malloc(CONFIG_CORTINA_FW_LENGTH); + ret = nand_read(&nand_info[0], (loff_t)CONFIG_CORTINA_FW_ADDR, + &fw_length, (u_char *)addr); + if (ret == -EUCLEAN) { + printf("NAND read of Cortina firmware at 0x%x failed %d\n", + CONFIG_CORTINA_FW_ADDR, ret); + } +#elif defined(CONFIG_SYS_CORTINA_FW_IN_SPIFLASH) + int ret; + struct spi_flash *ucode_flash; + + addr = malloc(CONFIG_CORTINA_FW_LENGTH); + ucode_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS, + CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE); + if (!ucode_flash) { + puts("SF: probe for Cortina ucode failed\n"); + } else { + ret = spi_flash_read(ucode_flash, CONFIG_CORTINA_FW_ADDR, + CONFIG_CORTINA_FW_LENGTH, addr); + if (ret) + puts("SF: read for Cortina ucode failed\n"); + spi_flash_free(ucode_flash); + } +#elif defined(CONFIG_SYS_CORTINA_FW_IN_MMC) + int dev = CONFIG_SYS_MMC_ENV_DEV; + u32 cnt = CONFIG_CORTINA_FW_LENGTH / 512; + u32 blk = CONFIG_CORTINA_FW_ADDR / 512; + struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV); + + if (!mmc) { + puts("Failed to find MMC device for Cortina ucode\n"); + } else { + addr = malloc(CONFIG_CORTINA_FW_LENGTH); + printf("MMC read: dev # %u, block # %u, count %u ...\n", + dev, blk, cnt); + mmc_init(mmc); + (void)mmc->block_dev.block_read(dev, blk, cnt, addr); + /* flush cache after read */ + flush_cache((ulong)addr, cnt * 512); + } +#endif + + while (*addr != 'Q') { + i = 0; + + while (*addr != 0x0a) { + line_temp[i++] = *addr++; + if (0x50 < i) { + printf("Not found Cortina PHY ucode at 0x%p\n", + (char *)CONFIG_CORTINA_FW_ADDR); + return; + } + } + + addr++; /* skip '\n' */ + line_cnt++; + column_cnt = i; + line_temp[column_cnt] = '\0'; + + if (CONFIG_CORTINA_FW_LENGTH < line_cnt) + return; + + for (i = 0; i < column_cnt; i++) { + if (isspace(line_temp[i++])) + break; + } + + memcpy(reg_addr, line_temp, i); + memcpy(reg_data, &line_temp[i], column_cnt - i); + strim(reg_addr); + strim(reg_data); + fw_temp.reg_addr = (simple_strtoul(reg_addr, NULL, 0)) & 0xffff; + fw_temp.reg_value = (simple_strtoul(reg_data, NULL, 0)) & + 0xffff; + phy_write(phydev, 0x00, fw_temp.reg_addr, fw_temp.reg_value); + } +} + +int cs4340_phy_init(struct phy_device *phydev) +{ + int timeout = 100; /* 100ms */ + int reg_value; + + /* step1: BIST test */ + phy_write(phydev, 0x00, VILLA_GLOBAL_MSEQCLKCTRL, 0x0004); + phy_write(phydev, 0x00, VILLA_GLOBAL_LINE_SOFT_RESET, 0x0000); + phy_write(phydev, 0x00, VILLA_GLOBAL_BIST_CONTROL, 0x0001); + while (--timeout) { + reg_value = phy_read(phydev, 0x00, VILLA_GLOBAL_BIST_STATUS); + if (reg_value & mseq_edc_bist_done) { + if (0 == (reg_value & mseq_edc_bist_fail)) + break; + } + udelay(1000); + } + + if (!timeout) { + printf("%s BIST mseq_edc_bist_done timeout!\n", __func__); + return -1; + } + + /* setp2: upload ucode */ + cs4340_upload_firmware(phydev); + reg_value = phy_read(phydev, 0x00, VILLA_GLOBAL_DWNLD_CHECKSUM_STATUS); + if (reg_value) { + debug("%s checksum status failed.\n", __func__); + return -1; + } + + return 0; +} + +int cs4340_config(struct phy_device *phydev) +{ + cs4340_phy_init(phydev); + return 0; +} + +int cs4340_startup(struct phy_device *phydev) +{ + phydev->link = 1; + + /* For now just lie and say it's 10G all the time */ + phydev->speed = SPEED_10000; + phydev->duplex = DUPLEX_FULL; + return 0; +} + +struct phy_driver cs4340_driver = { + .name = "Cortina CS4315/CS4340", + .uid = PHY_UID_CS4340, + .mask = 0xfffffff0, + .features = PHY_10G_FEATURES, + .mmds = (MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS | + MDIO_DEVS_PHYXS | MDIO_DEVS_AN | + MDIO_DEVS_VEND1 | MDIO_DEVS_VEND2), + .config = &cs4340_config, + .startup = &cs4340_startup, + .shutdown = &gen10g_shutdown, +}; + +int phy_cortina_init(void) +{ + phy_register(&cs4340_driver); + return 0; +} + +int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id) +{ + int phy_reg; + bool is_cortina_phy = false; + + switch (addr) { +#ifdef CORTINA_PHY_ADDR1 + case CORTINA_PHY_ADDR1: +#endif +#ifdef CORTINA_PHY_ADDR2 + case CORTINA_PHY_ADDR2: +#endif +#ifdef CORTINA_PHY_ADDR3 + case CORTINA_PHY_ADDR3: +#endif +#ifdef CORTINA_PHY_ADDR4 + case CORTINA_PHY_ADDR4: +#endif + is_cortina_phy = true; + break; + default: + break; + } + + /* Cortina PHY has non-standard offset of PHY ID registers */ + if (is_cortina_phy) + phy_reg = bus->read(bus, addr, 0, VILLA_GLOBAL_CHIP_ID_LSB); + else + phy_reg = bus->read(bus, addr, devad, MII_PHYSID1); + + if (phy_reg < 0) + return -EIO; + + *phy_id = (phy_reg & 0xffff) << 16; + if (is_cortina_phy) + phy_reg = bus->read(bus, addr, 0, VILLA_GLOBAL_CHIP_ID_MSB); + else + phy_reg = bus->read(bus, addr, devad, MII_PHYSID2); + + if (phy_reg < 0) + return -EIO; + + *phy_id |= (phy_reg & 0xffff); + + return 0; +} diff --git a/sources/uboot-be550/drivers/net/phy/davicom.c b/sources/uboot-be550/drivers/net/phy/davicom.c new file mode 100644 index 00000000..0c039fe7 --- /dev/null +++ b/sources/uboot-be550/drivers/net/phy/davicom.c @@ -0,0 +1,84 @@ +/* + * Davicom PHY drivers + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Copyright 2010-2011 Freescale Semiconductor, Inc. + * author Andy Fleming + */ +#include + +#define MIIM_DM9161_SCR 0x10 +#define MIIM_DM9161_SCR_INIT 0x0610 + +/* DM9161 Specified Configuration and Status Register */ +#define MIIM_DM9161_SCSR 0x11 +#define MIIM_DM9161_SCSR_100F 0x8000 +#define MIIM_DM9161_SCSR_100H 0x4000 +#define MIIM_DM9161_SCSR_10F 0x2000 +#define MIIM_DM9161_SCSR_10H 0x1000 + +/* DM9161 10BT Configuration/Status */ +#define MIIM_DM9161_10BTCSR 0x12 +#define MIIM_DM9161_10BTCSR_INIT 0x7800 + + +/* Davicom DM9161E */ +static int dm9161_config(struct phy_device *phydev) +{ + phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_ISOLATE); + /* Do not bypass the scrambler/descrambler */ + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_DM9161_SCR, + MIIM_DM9161_SCR_INIT); + /* Clear 10BTCSR to default */ + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_DM9161_10BTCSR, + MIIM_DM9161_10BTCSR_INIT); + + genphy_config_aneg(phydev); + + return 0; +} + +static int dm9161_parse_status(struct phy_device *phydev) +{ + int mii_reg; + + mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_DM9161_SCSR); + + if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_100H)) + phydev->speed = SPEED_100; + else + phydev->speed = SPEED_10; + + if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_10F)) + phydev->duplex = DUPLEX_FULL; + else + phydev->duplex = DUPLEX_HALF; + + return 0; +} + +static int dm9161_startup(struct phy_device *phydev) +{ + genphy_update_link(phydev); + dm9161_parse_status(phydev); + + return 0; +} + +static struct phy_driver DM9161_driver = { + .name = "Davicom DM9161E", + .uid = 0x181b880, + .mask = 0xffffff0, + .features = PHY_BASIC_FEATURES, + .config = &dm9161_config, + .startup = &dm9161_startup, + .shutdown = &genphy_shutdown, +}; + +int phy_davicom_init(void) +{ + phy_register(&DM9161_driver); + + return 0; +} diff --git a/sources/uboot-be550/drivers/net/phy/et1011c.c b/sources/uboot-be550/drivers/net/phy/et1011c.c new file mode 100644 index 00000000..70c15e2f --- /dev/null +++ b/sources/uboot-be550/drivers/net/phy/et1011c.c @@ -0,0 +1,101 @@ +/* + * ET1011C PHY driver + * + * Derived from Linux kernel driver by Chaithrika U S + * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include + +#define ET1011C_CONFIG_REG (0x16) +#define ET1011C_TX_FIFO_MASK (0x3 << 12) +#define ET1011C_TX_FIFO_DEPTH_8 (0x0 << 12) +#define ET1011C_TX_FIFO_DEPTH_16 (0x1 << 12) +#define ET1011C_INTERFACE_MASK (0x7 << 0) +#define ET1011C_GMII_INTERFACE (0x2 << 0) +#define ET1011C_SYS_CLK_EN (0x1 << 4) +#define ET1011C_TX_CLK_EN (0x1 << 5) + +#define ET1011C_STATUS_REG (0x1A) +#define ET1011C_DUPLEX_STATUS (0x1 << 7) +#define ET1011C_SPEED_MASK (0x3 << 8) +#define ET1011C_SPEED_1000 (0x2 << 8) +#define ET1011C_SPEED_100 (0x1 << 8) +#define ET1011C_SPEED_10 (0x0 << 8) + +static int et1011c_config(struct phy_device *phydev) +{ + int ctl = 0; + ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); + if (ctl < 0) + return ctl; + ctl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 | BMCR_SPEED1000 | + BMCR_ANENABLE); + /* First clear the PHY */ + phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, ctl | BMCR_RESET); + + return genphy_config_aneg(phydev); +} + +static int et1011c_parse_status(struct phy_device *phydev) +{ + int mii_reg; + int speed; + + mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, ET1011C_STATUS_REG); + + if (mii_reg & ET1011C_DUPLEX_STATUS) + phydev->duplex = DUPLEX_FULL; + else + phydev->duplex = DUPLEX_HALF; + + speed = mii_reg & ET1011C_SPEED_MASK; + switch (speed) { + case ET1011C_SPEED_1000: + phydev->speed = SPEED_1000; + mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, ET1011C_CONFIG_REG); + mii_reg &= ~ET1011C_TX_FIFO_MASK; + phy_write(phydev, MDIO_DEVAD_NONE, ET1011C_CONFIG_REG, + mii_reg | + ET1011C_GMII_INTERFACE | + ET1011C_SYS_CLK_EN | +#ifdef CONFIG_PHY_ET1011C_TX_CLK_FIX + ET1011C_TX_CLK_EN | +#endif + ET1011C_TX_FIFO_DEPTH_16); + break; + case ET1011C_SPEED_100: + phydev->speed = SPEED_100; + break; + case ET1011C_SPEED_10: + phydev->speed = SPEED_10; + break; + } + + return 0; +} + +static int et1011c_startup(struct phy_device *phydev) +{ + genphy_update_link(phydev); + et1011c_parse_status(phydev); + return 0; +} + +static struct phy_driver et1011c_driver = { + .name = "ET1011C", + .uid = 0x0282f014, + .mask = 0xfffffff0, + .features = PHY_GBIT_FEATURES, + .config = &et1011c_config, + .startup = &et1011c_startup, +}; + +int phy_et1011c_init(void) +{ + phy_register(&et1011c_driver); + + return 0; +} diff --git a/sources/uboot-be550/drivers/net/phy/generic_10g.c b/sources/uboot-be550/drivers/net/phy/generic_10g.c new file mode 100644 index 00000000..ed3dcd91 --- /dev/null +++ b/sources/uboot-be550/drivers/net/phy/generic_10g.c @@ -0,0 +1,94 @@ +/* + * Generic PHY Management code + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Copyright 2011 Freescale Semiconductor, Inc. + * author Andy Fleming + * + * Based loosely off of Linux's PHY Lib + */ + +#include +#include +#include +#include + +int gen10g_shutdown(struct phy_device *phydev) +{ + return 0; +} + +int gen10g_startup(struct phy_device *phydev) +{ + int devad, reg; + u32 mmd_mask = phydev->mmds & MDIO_DEVS_LINK; + + phydev->link = 1; + + /* For now just lie and say it's 10G all the time */ + phydev->speed = SPEED_10000; + phydev->duplex = DUPLEX_FULL; + + /* + * Go through all the link-reporting devices, and make sure + * they're all up and happy + */ + for (devad = 0; mmd_mask; devad++, mmd_mask = mmd_mask >> 1) { + if (!(mmd_mask & 1)) + continue; + + /* Read twice because link state is latched and a + * read moves the current state into the register */ + phy_read(phydev, devad, MDIO_STAT1); + reg = phy_read(phydev, devad, MDIO_STAT1); + if (reg < 0 || !(reg & MDIO_STAT1_LSTATUS)) + phydev->link = 0; + } + + return 0; +} + +int gen10g_discover_mmds(struct phy_device *phydev) +{ + int mmd, stat2, devs1, devs2; + + /* Assume PHY must have at least one of PMA/PMD, WIS, PCS, PHY + * XS or DTE XS; give up if none is present. */ + for (mmd = 1; mmd <= 5; mmd++) { + /* Is this MMD present? */ + stat2 = phy_read(phydev, mmd, MDIO_STAT2); + if (stat2 < 0 || + (stat2 & MDIO_STAT2_DEVPRST) != MDIO_STAT2_DEVPRST_VAL) + continue; + + /* It should tell us about all the other MMDs */ + devs1 = phy_read(phydev, mmd, MDIO_DEVS1); + devs2 = phy_read(phydev, mmd, MDIO_DEVS2); + if (devs1 < 0 || devs2 < 0) + continue; + + phydev->mmds = devs1 | (devs2 << 16); + return 0; + } + + return 0; +} + +int gen10g_config(struct phy_device *phydev) +{ + /* For now, assume 10000baseT. Fill in later */ + phydev->supported = phydev->advertising = SUPPORTED_10000baseT_Full; + + return gen10g_discover_mmds(phydev); +} + +struct phy_driver gen10g_driver = { + .uid = 0xffffffff, + .mask = 0xffffffff, + .name = "Generic 10G PHY", + .features = 0, + .config = gen10g_config, + .startup = gen10g_startup, + .shutdown = gen10g_shutdown, +}; diff --git a/sources/uboot-be550/drivers/net/phy/lxt.c b/sources/uboot-be550/drivers/net/phy/lxt.c new file mode 100644 index 00000000..91838ce5 --- /dev/null +++ b/sources/uboot-be550/drivers/net/phy/lxt.c @@ -0,0 +1,73 @@ +/* + * LXT PHY drivers + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Copyright 2010-2011 Freescale Semiconductor, Inc. + * author Andy Fleming + */ +#include + +/* LXT971 Status 2 registers */ +#define MIIM_LXT971_SR2 0x11 /* Status Register 2 */ +#define MIIM_LXT971_SR2_SPEED_MASK 0x4200 +#define MIIM_LXT971_SR2_10HDX 0x0000 /* 10 Mbit half duplex selected */ +#define MIIM_LXT971_SR2_10FDX 0x0200 /* 10 Mbit full duplex selected */ +#define MIIM_LXT971_SR2_100HDX 0x4000 /* 100 Mbit half duplex selected */ +#define MIIM_LXT971_SR2_100FDX 0x4200 /* 100 Mbit full duplex selected */ + + +/* LXT971 */ +static int lxt971_parse_status(struct phy_device *phydev) +{ + int mii_reg; + int speed; + + mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_LXT971_SR2); + speed = mii_reg & MIIM_LXT971_SR2_SPEED_MASK; + + switch (speed) { + case MIIM_LXT971_SR2_10HDX: + phydev->speed = SPEED_10; + phydev->duplex = DUPLEX_HALF; + break; + case MIIM_LXT971_SR2_10FDX: + phydev->speed = SPEED_10; + phydev->duplex = DUPLEX_FULL; + break; + case MIIM_LXT971_SR2_100HDX: + phydev->speed = SPEED_100; + phydev->duplex = DUPLEX_HALF; + break; + default: + phydev->speed = SPEED_100; + phydev->duplex = DUPLEX_FULL; + } + + return 0; +} + +static int lxt971_startup(struct phy_device *phydev) +{ + genphy_update_link(phydev); + lxt971_parse_status(phydev); + + return 0; +} + +static struct phy_driver LXT971_driver = { + .name = "LXT971", + .uid = 0x1378e0, + .mask = 0xfffff0, + .features = PHY_BASIC_FEATURES, + .config = &genphy_config_aneg, + .startup = &lxt971_startup, + .shutdown = &genphy_shutdown, +}; + +int phy_lxt_init(void) +{ + phy_register(&LXT971_driver); + + return 0; +} diff --git a/sources/uboot-be550/drivers/net/phy/marvell.c b/sources/uboot-be550/drivers/net/phy/marvell.c new file mode 100644 index 00000000..eab15585 --- /dev/null +++ b/sources/uboot-be550/drivers/net/phy/marvell.c @@ -0,0 +1,614 @@ +/* + * Marvell PHY drivers + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Copyright 2010-2011 Freescale Semiconductor, Inc. + * author Andy Fleming + */ +#include +#include +#include + +#define PHY_AUTONEGOTIATE_TIMEOUT 5000 + +/* 88E1011 PHY Status Register */ +#define MIIM_88E1xxx_PHY_STATUS 0x11 +#define MIIM_88E1xxx_PHYSTAT_SPEED 0xc000 +#define MIIM_88E1xxx_PHYSTAT_GBIT 0x8000 +#define MIIM_88E1xxx_PHYSTAT_100 0x4000 +#define MIIM_88E1xxx_PHYSTAT_DUPLEX 0x2000 +#define MIIM_88E1xxx_PHYSTAT_SPDDONE 0x0800 +#define MIIM_88E1xxx_PHYSTAT_LINK 0x0400 + +#define MIIM_88E1xxx_PHY_SCR 0x10 +#define MIIM_88E1xxx_PHY_MDI_X_AUTO 0x0060 + +/* 88E1111 PHY LED Control Register */ +#define MIIM_88E1111_PHY_LED_CONTROL 24 +#define MIIM_88E1111_PHY_LED_DIRECT 0x4100 +#define MIIM_88E1111_PHY_LED_COMBINE 0x411C + +/* 88E1111 Extended PHY Specific Control Register */ +#define MIIM_88E1111_PHY_EXT_CR 0x14 +#define MIIM_88E1111_RX_DELAY 0x80 +#define MIIM_88E1111_TX_DELAY 0x2 + +/* 88E1111 Extended PHY Specific Status Register */ +#define MIIM_88E1111_PHY_EXT_SR 0x1b +#define MIIM_88E1111_HWCFG_MODE_MASK 0xf +#define MIIM_88E1111_HWCFG_MODE_COPPER_RGMII 0xb +#define MIIM_88E1111_HWCFG_MODE_FIBER_RGMII 0x3 +#define MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK 0x4 +#define MIIM_88E1111_HWCFG_MODE_COPPER_RTBI 0x9 +#define MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO 0x8000 +#define MIIM_88E1111_HWCFG_FIBER_COPPER_RES 0x2000 + +#define MIIM_88E1111_COPPER 0 +#define MIIM_88E1111_FIBER 1 + +/* 88E1118 PHY defines */ +#define MIIM_88E1118_PHY_PAGE 22 +#define MIIM_88E1118_PHY_LED_PAGE 3 + +/* 88E1121 PHY LED Control Register */ +#define MIIM_88E1121_PHY_LED_CTRL 16 +#define MIIM_88E1121_PHY_LED_PAGE 3 +#define MIIM_88E1121_PHY_LED_DEF 0x0030 + +/* 88E1121 PHY IRQ Enable/Status Register */ +#define MIIM_88E1121_PHY_IRQ_EN 18 +#define MIIM_88E1121_PHY_IRQ_STATUS 19 + +#define MIIM_88E1121_PHY_PAGE 22 + +/* 88E1145 Extended PHY Specific Control Register */ +#define MIIM_88E1145_PHY_EXT_CR 20 +#define MIIM_M88E1145_RGMII_RX_DELAY 0x0080 +#define MIIM_M88E1145_RGMII_TX_DELAY 0x0002 + +#define MIIM_88E1145_PHY_LED_CONTROL 24 +#define MIIM_88E1145_PHY_LED_DIRECT 0x4100 + +#define MIIM_88E1145_PHY_PAGE 29 +#define MIIM_88E1145_PHY_CAL_OV 30 + +#define MIIM_88E1149_PHY_PAGE 29 + +/* 88E1310 PHY defines */ +#define MIIM_88E1310_PHY_LED_CTRL 16 +#define MIIM_88E1310_PHY_IRQ_EN 18 +#define MIIM_88E1310_PHY_RGMII_CTRL 21 +#define MIIM_88E1310_PHY_PAGE 22 + +/* Marvell 88E1011S */ +static int m88e1011s_config(struct phy_device *phydev) +{ + /* Reset and configure the PHY */ + phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); + + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x200c); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); + + phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); + + genphy_config_aneg(phydev); + + return 0; +} + +/* Parse the 88E1011's status register for speed and duplex + * information + */ +static uint m88e1xxx_parse_status(struct phy_device *phydev) +{ + unsigned int speed; + unsigned int mii_reg; + + mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1xxx_PHY_STATUS); + + if ((mii_reg & MIIM_88E1xxx_PHYSTAT_LINK) && + !(mii_reg & MIIM_88E1xxx_PHYSTAT_SPDDONE)) { + int i = 0; + + puts("Waiting for PHY realtime link"); + while (!(mii_reg & MIIM_88E1xxx_PHYSTAT_SPDDONE)) { + /* Timeout reached ? */ + if (i > PHY_AUTONEGOTIATE_TIMEOUT) { + puts(" TIMEOUT !\n"); + phydev->link = 0; + break; + } + + if ((i++ % 1000) == 0) + putc('.'); + udelay(1000); + mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, + MIIM_88E1xxx_PHY_STATUS); + } + puts(" done\n"); + udelay(500000); /* another 500 ms (results in faster booting) */ + } else { + if (mii_reg & MIIM_88E1xxx_PHYSTAT_LINK) + phydev->link = 1; + else + phydev->link = 0; + } + + if (mii_reg & MIIM_88E1xxx_PHYSTAT_DUPLEX) + phydev->duplex = DUPLEX_FULL; + else + phydev->duplex = DUPLEX_HALF; + + speed = mii_reg & MIIM_88E1xxx_PHYSTAT_SPEED; + + switch (speed) { + case MIIM_88E1xxx_PHYSTAT_GBIT: + phydev->speed = SPEED_1000; + break; + case MIIM_88E1xxx_PHYSTAT_100: + phydev->speed = SPEED_100; + break; + default: + phydev->speed = SPEED_10; + break; + } + + return 0; +} + +static int m88e1011s_startup(struct phy_device *phydev) +{ + genphy_update_link(phydev); + m88e1xxx_parse_status(phydev); + + return 0; +} + +/* Marvell 88E1111S */ +static int m88e1111s_config(struct phy_device *phydev) +{ + int reg; + int timeout; + + if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) || + (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) || + (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) || + (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) { + reg = phy_read(phydev, + MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR); + if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) || + (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)) { + reg |= (MIIM_88E1111_RX_DELAY | MIIM_88E1111_TX_DELAY); + } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) { + reg &= ~MIIM_88E1111_TX_DELAY; + reg |= MIIM_88E1111_RX_DELAY; + } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) { + reg &= ~MIIM_88E1111_RX_DELAY; + reg |= MIIM_88E1111_TX_DELAY; + } + + phy_write(phydev, + MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR, reg); + + reg = phy_read(phydev, + MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR); + + reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK); + + if (reg & MIIM_88E1111_HWCFG_FIBER_COPPER_RES) + reg |= MIIM_88E1111_HWCFG_MODE_FIBER_RGMII; + else + reg |= MIIM_88E1111_HWCFG_MODE_COPPER_RGMII; + + phy_write(phydev, + MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR, reg); + } + + if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { + reg = phy_read(phydev, + MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR); + + reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK); + reg |= MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK; + reg |= MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO; + + phy_write(phydev, MDIO_DEVAD_NONE, + MIIM_88E1111_PHY_EXT_SR, reg); + } + + if (phydev->interface == PHY_INTERFACE_MODE_RTBI) { + reg = phy_read(phydev, + MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR); + reg |= (MIIM_88E1111_RX_DELAY | MIIM_88E1111_TX_DELAY); + phy_write(phydev, + MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR, reg); + + reg = phy_read(phydev, MDIO_DEVAD_NONE, + MIIM_88E1111_PHY_EXT_SR); + reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK | + MIIM_88E1111_HWCFG_FIBER_COPPER_RES); + reg |= 0x7 | MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO; + phy_write(phydev, MDIO_DEVAD_NONE, + MIIM_88E1111_PHY_EXT_SR, reg); + + /* soft reset */ + timeout = 1000; + phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); + udelay(1000); + reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); + while ((reg & BMCR_RESET) && --timeout) { + udelay(1000); + reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); + } + if (!timeout) + printf("%s: phy soft reset timeout\n", __func__); + + reg = phy_read(phydev, MDIO_DEVAD_NONE, + MIIM_88E1111_PHY_EXT_SR); + reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK | + MIIM_88E1111_HWCFG_FIBER_COPPER_RES); + reg |= MIIM_88E1111_HWCFG_MODE_COPPER_RTBI | + MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO; + phy_write(phydev, MDIO_DEVAD_NONE, + MIIM_88E1111_PHY_EXT_SR, reg); + } + + /* soft reset */ + timeout = 1000; + phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); + udelay(1000); + reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); + while ((reg & BMCR_RESET) && --timeout) { + udelay(1000); + reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); + } + if (!timeout) + printf("%s: phy soft reset timeout\n", __func__); + + genphy_config_aneg(phydev); + + phy_reset(phydev); + + return 0; +} + +/** + * m88e1518_phy_writebits - write bits to a register + */ +void m88e1518_phy_writebits(struct phy_device *phydev, + u8 reg_num, u16 offset, u16 len, u16 data) +{ + u16 reg, mask; + + if ((len + offset) >= 16) + mask = 0 - (1 << offset); + else + mask = (1 << (len + offset)) - (1 << offset); + + reg = phy_read(phydev, MDIO_DEVAD_NONE, reg_num); + + reg &= ~mask; + reg |= data << offset; + + phy_write(phydev, MDIO_DEVAD_NONE, reg_num, reg); +} + +static int m88e1518_config(struct phy_device *phydev) +{ + /* + * As per Marvell Release Notes - Alaska 88E1510/88E1518/88E1512 + * /88E1514 Rev A0, Errata Section 3.1 + */ + + /* EEE initialization */ + phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x00ff); + phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x214B); + phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2144); + phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x0C28); + phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2146); + phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xB233); + phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x214D); + phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xCC0C); + phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2159); + phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x0000); + + /* SGMII-to-Copper mode initialization */ + if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { + /* Select page 18 */ + phy_write(phydev, MDIO_DEVAD_NONE, 22, 18); + + /* In reg 20, write MODE[2:0] = 0x1 (SGMII to Copper) */ + m88e1518_phy_writebits(phydev, 20, 0, 3, 1); + + /* PHY reset is necessary after changing MODE[2:0] */ + m88e1518_phy_writebits(phydev, 20, 15, 1, 1); + + /* Reset page selection */ + phy_write(phydev, MDIO_DEVAD_NONE, 22, 0); + + udelay(100); + } + + return m88e1111s_config(phydev); +} + +/* Marvell 88E1510 */ +static int m88e1510_config(struct phy_device *phydev) +{ + /* Select page 3 */ + phy_write(phydev, MDIO_DEVAD_NONE, 22, 3); + + /* Enable INTn output on LED[2] */ + m88e1518_phy_writebits(phydev, 18, 7, 1, 1); + + /* Configure LEDs */ + m88e1518_phy_writebits(phydev, 16, 0, 4, 3); /* LED[0]:0011 (ACT) */ + m88e1518_phy_writebits(phydev, 16, 4, 4, 6); /* LED[1]:0110 (LINK) */ + + /* Reset page selection */ + phy_write(phydev, MDIO_DEVAD_NONE, 22, 0); + + return m88e1518_config(phydev); +} + +/* Marvell 88E1118 */ +static int m88e1118_config(struct phy_device *phydev) +{ + /* Change Page Number */ + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0002); + /* Delay RGMII TX and RX */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x15, 0x1070); + /* Change Page Number */ + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0003); + /* Adjust LED control */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x10, 0x021e); + /* Change Page Number */ + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000); + + genphy_config_aneg(phydev); + + phy_reset(phydev); + + return 0; +} + +static int m88e1118_startup(struct phy_device *phydev) +{ + /* Change Page Number */ + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000); + + genphy_update_link(phydev); + m88e1xxx_parse_status(phydev); + + return 0; +} + +/* Marvell 88E1121R */ +static int m88e1121_config(struct phy_device *phydev) +{ + int pg; + + /* Configure the PHY */ + genphy_config_aneg(phydev); + + /* Switch the page to access the led register */ + pg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE); + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE, + MIIM_88E1121_PHY_LED_PAGE); + /* Configure leds */ + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_LED_CTRL, + MIIM_88E1121_PHY_LED_DEF); + /* Restore the page pointer */ + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE, pg); + + /* Disable IRQs and de-assert interrupt */ + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_IRQ_EN, 0); + phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_IRQ_STATUS); + + return 0; +} + +/* Marvell 88E1145 */ +static int m88e1145_config(struct phy_device *phydev) +{ + int reg; + + /* Errata E0, E1 */ + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_PAGE, 0x001b); + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_CAL_OV, 0x418f); + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_PAGE, 0x0016); + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_CAL_OV, 0xa2da); + + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1xxx_PHY_SCR, + MIIM_88E1xxx_PHY_MDI_X_AUTO); + + reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_EXT_CR); + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) + reg |= MIIM_M88E1145_RGMII_RX_DELAY | + MIIM_M88E1145_RGMII_TX_DELAY; + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_EXT_CR, reg); + + genphy_config_aneg(phydev); + + phy_reset(phydev); + + return 0; +} + +static int m88e1145_startup(struct phy_device *phydev) +{ + genphy_update_link(phydev); + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_LED_CONTROL, + MIIM_88E1145_PHY_LED_DIRECT); + m88e1xxx_parse_status(phydev); + + return 0; +} + +/* Marvell 88E1149S */ +static int m88e1149_config(struct phy_device *phydev) +{ + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1149_PHY_PAGE, 0x1f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x200c); + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1149_PHY_PAGE, 0x5); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x0); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); + + genphy_config_aneg(phydev); + + phy_reset(phydev); + + return 0; +} + +/* Marvell 88E1310 */ +static int m88e1310_config(struct phy_device *phydev) +{ + u16 reg; + + /* LED link and activity */ + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0003); + reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_LED_CTRL); + reg = (reg & ~0xf) | 0x1; + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_LED_CTRL, reg); + + /* Set LED2/INT to INT mode, low active */ + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0003); + reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_IRQ_EN); + reg = (reg & 0x77ff) | 0x0880; + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_IRQ_EN, reg); + + /* Set RGMII delay */ + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0002); + reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_RGMII_CTRL); + reg |= 0x0030; + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_RGMII_CTRL, reg); + + /* Ensure to return to page 0 */ + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0000); + + genphy_config_aneg(phydev); + phy_reset(phydev); + + return 0; +} + +static struct phy_driver M88E1011S_driver = { + .name = "Marvell 88E1011S", + .uid = 0x1410c60, + .mask = 0xffffff0, + .features = PHY_GBIT_FEATURES, + .config = &m88e1011s_config, + .startup = &m88e1011s_startup, + .shutdown = &genphy_shutdown, +}; + +static struct phy_driver M88E1111S_driver = { + .name = "Marvell 88E1111S", + .uid = 0x1410cc0, + .mask = 0xffffff0, + .features = PHY_GBIT_FEATURES, + .config = &m88e1111s_config, + .startup = &m88e1011s_startup, + .shutdown = &genphy_shutdown, +}; + +static struct phy_driver M88E1118_driver = { + .name = "Marvell 88E1118", + .uid = 0x1410e10, + .mask = 0xffffff0, + .features = PHY_GBIT_FEATURES, + .config = &m88e1118_config, + .startup = &m88e1118_startup, + .shutdown = &genphy_shutdown, +}; + +static struct phy_driver M88E1118R_driver = { + .name = "Marvell 88E1118R", + .uid = 0x1410e40, + .mask = 0xffffff0, + .features = PHY_GBIT_FEATURES, + .config = &m88e1118_config, + .startup = &m88e1118_startup, + .shutdown = &genphy_shutdown, +}; + +static struct phy_driver M88E1121R_driver = { + .name = "Marvell 88E1121R", + .uid = 0x1410cb0, + .mask = 0xffffff0, + .features = PHY_GBIT_FEATURES, + .config = &m88e1121_config, + .startup = &genphy_startup, + .shutdown = &genphy_shutdown, +}; + +static struct phy_driver M88E1145_driver = { + .name = "Marvell 88E1145", + .uid = 0x1410cd0, + .mask = 0xffffff0, + .features = PHY_GBIT_FEATURES, + .config = &m88e1145_config, + .startup = &m88e1145_startup, + .shutdown = &genphy_shutdown, +}; + +static struct phy_driver M88E1149S_driver = { + .name = "Marvell 88E1149S", + .uid = 0x1410ca0, + .mask = 0xffffff0, + .features = PHY_GBIT_FEATURES, + .config = &m88e1149_config, + .startup = &m88e1011s_startup, + .shutdown = &genphy_shutdown, +}; + +static struct phy_driver M88E1510_driver = { + .name = "Marvell 88E1510", + .uid = 0x1410dd0, + .mask = 0xffffff0, + .features = PHY_GBIT_FEATURES, + .config = &m88e1510_config, + .startup = &m88e1011s_startup, + .shutdown = &genphy_shutdown, +}; + +static struct phy_driver M88E1518_driver = { + .name = "Marvell 88E1518", + .uid = 0x1410dd1, + .mask = 0xffffff0, + .features = PHY_GBIT_FEATURES, + .config = &m88e1518_config, + .startup = &m88e1011s_startup, + .shutdown = &genphy_shutdown, +}; + +static struct phy_driver M88E1310_driver = { + .name = "Marvell 88E1310", + .uid = 0x01410e90, + .mask = 0xffffff0, + .features = PHY_GBIT_FEATURES, + .config = &m88e1310_config, + .startup = &m88e1011s_startup, + .shutdown = &genphy_shutdown, +}; + +int phy_marvell_init(void) +{ + phy_register(&M88E1310_driver); + phy_register(&M88E1149S_driver); + phy_register(&M88E1145_driver); + phy_register(&M88E1121R_driver); + phy_register(&M88E1118_driver); + phy_register(&M88E1118R_driver); + phy_register(&M88E1111S_driver); + phy_register(&M88E1011S_driver); + phy_register(&M88E1510_driver); + phy_register(&M88E1518_driver); + + return 0; +} diff --git a/sources/uboot-be550/drivers/net/phy/micrel.c b/sources/uboot-be550/drivers/net/phy/micrel.c new file mode 100644 index 00000000..19b6bc74 --- /dev/null +++ b/sources/uboot-be550/drivers/net/phy/micrel.c @@ -0,0 +1,478 @@ +/* + * Micrel PHY drivers + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Copyright 2010-2011 Freescale Semiconductor, Inc. + * author Andy Fleming + * (C) 2012 NetModule AG, David Andrey, added KSZ9031 + */ +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static struct phy_driver KSZ804_driver = { + .name = "Micrel KSZ804", + .uid = 0x221510, + .mask = 0xfffff0, + .features = PHY_BASIC_FEATURES, + .config = &genphy_config, + .startup = &genphy_startup, + .shutdown = &genphy_shutdown, +}; + +static struct phy_driver KSZ8031_driver = { + .name = "Micrel KSZ8021/KSZ8031", + .uid = 0x221550, + .mask = 0xfffff0, + .features = PHY_BASIC_FEATURES, + .config = &genphy_config, + .startup = &genphy_startup, + .shutdown = &genphy_shutdown, +}; + +/** + * KSZ8051 + */ +#define MII_KSZ8051_PHY_OMSO 0x16 +#define MII_KSZ8051_PHY_OMSO_NAND_TREE_ON (1 << 5) + +static int ksz8051_config(struct phy_device *phydev) +{ + unsigned val; + + /* Disable NAND-tree */ + val = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ8051_PHY_OMSO); + val &= ~MII_KSZ8051_PHY_OMSO_NAND_TREE_ON; + phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZ8051_PHY_OMSO, val); + + return genphy_config(phydev); +} + +static struct phy_driver KSZ8051_driver = { + .name = "Micrel KSZ8051", + .uid = 0x221550, + .mask = 0xfffff0, + .features = PHY_BASIC_FEATURES, + .config = &ksz8051_config, + .startup = &genphy_startup, + .shutdown = &genphy_shutdown, +}; + +static struct phy_driver KSZ8081_driver = { + .name = "Micrel KSZ8081", + .uid = 0x221560, + .mask = 0xfffff0, + .features = PHY_BASIC_FEATURES, + .config = &genphy_config, + .startup = &genphy_startup, + .shutdown = &genphy_shutdown, +}; + +/** + * KSZ8895 + */ + +static unsigned short smireg_to_phy(unsigned short reg) +{ + return ((reg & 0xc0) >> 3) + 0x06 + ((reg & 0x20) >> 5); +} + +static unsigned short smireg_to_reg(unsigned short reg) +{ + return reg & 0x1F; +} + +static void ksz8895_write_smireg(struct phy_device *phydev, int smireg, int val) +{ + phydev->bus->write(phydev->bus, smireg_to_phy(smireg), MDIO_DEVAD_NONE, + smireg_to_reg(smireg), val); +} + +#if 0 +static int ksz8895_read_smireg(struct phy_device *phydev, int smireg) +{ + return phydev->bus->read(phydev->bus, smireg_to_phy(smireg), + MDIO_DEVAD_NONE, smireg_to_reg(smireg)); +} +#endif + +int ksz8895_config(struct phy_device *phydev) +{ + /* we are connected directly to the switch without + * dedicated PHY. SCONF1 == 001 */ + phydev->link = 1; + phydev->duplex = DUPLEX_FULL; + phydev->speed = SPEED_100; + + /* Force the switch to start */ + ksz8895_write_smireg(phydev, 1, 1); + + return 0; +} + +static int ksz8895_startup(struct phy_device *phydev) +{ + return 0; +} + +static struct phy_driver ksz8895_driver = { + .name = "Micrel KSZ8895/KSZ8864", + .uid = 0x221450, + .mask = 0xffffe1, + .features = PHY_BASIC_FEATURES, + .config = &ksz8895_config, + .startup = &ksz8895_startup, + .shutdown = &genphy_shutdown, +}; + +#ifndef CONFIG_PHY_MICREL_KSZ9021 +/* + * I can't believe Micrel used the exact same part number + * for the KSZ9021. Shame Micrel, Shame! + */ +static struct phy_driver KS8721_driver = { + .name = "Micrel KS8721BL", + .uid = 0x221610, + .mask = 0xfffff0, + .features = PHY_BASIC_FEATURES, + .config = &genphy_config, + .startup = &genphy_startup, + .shutdown = &genphy_shutdown, +}; +#endif + + +/* + * KSZ9021 - KSZ9031 common + */ + +#define MII_KSZ90xx_PHY_CTL 0x1f +#define MIIM_KSZ90xx_PHYCTL_1000 (1 << 6) +#define MIIM_KSZ90xx_PHYCTL_100 (1 << 5) +#define MIIM_KSZ90xx_PHYCTL_10 (1 << 4) +#define MIIM_KSZ90xx_PHYCTL_DUPLEX (1 << 3) + +static int ksz90xx_startup(struct phy_device *phydev) +{ + unsigned phy_ctl; + genphy_update_link(phydev); + phy_ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ90xx_PHY_CTL); + + if (phy_ctl & MIIM_KSZ90xx_PHYCTL_DUPLEX) + phydev->duplex = DUPLEX_FULL; + else + phydev->duplex = DUPLEX_HALF; + + if (phy_ctl & MIIM_KSZ90xx_PHYCTL_1000) + phydev->speed = SPEED_1000; + else if (phy_ctl & MIIM_KSZ90xx_PHYCTL_100) + phydev->speed = SPEED_100; + else if (phy_ctl & MIIM_KSZ90xx_PHYCTL_10) + phydev->speed = SPEED_10; + return 0; +} + +/* Common OF config bits for KSZ9021 and KSZ9031 */ +#if defined(CONFIG_PHY_MICREL_KSZ9021) || defined(CONFIG_PHY_MICREL_KSZ9031) +#ifdef CONFIG_DM_ETH +struct ksz90x1_reg_field { + const char *name; + const u8 size; /* Size of the bitfield, in bits */ + const u8 off; /* Offset from bit 0 */ + const u8 dflt; /* Default value */ +}; + +struct ksz90x1_ofcfg { + const u16 reg; + const u16 devad; + const struct ksz90x1_reg_field *grp; + const u16 grpsz; +}; + +static const struct ksz90x1_reg_field ksz90x1_rxd_grp[] = { + { "rxd0-skew-ps", 4, 0, 0x7 }, { "rxd1-skew-ps", 4, 4, 0x7 }, + { "rxd2-skew-ps", 4, 8, 0x7 }, { "rxd3-skew-ps", 4, 12, 0x7 } +}; + +static const struct ksz90x1_reg_field ksz90x1_txd_grp[] = { + { "txd0-skew-ps", 4, 0, 0x7 }, { "txd1-skew-ps", 4, 4, 0x7 }, + { "txd2-skew-ps", 4, 8, 0x7 }, { "txd3-skew-ps", 4, 12, 0x7 }, +}; + +static int ksz90x1_of_config_group(struct phy_device *phydev, + struct ksz90x1_ofcfg *ofcfg) +{ + struct udevice *dev = phydev->dev; + struct phy_driver *drv = phydev->drv; + const int ps_to_regval = 200; + int val[4]; + int i, changed = 0, offset, max; + u16 regval = 0; + + if (!drv || !drv->writeext) + return -EOPNOTSUPP; + + for (i = 0; i < ofcfg->grpsz; i++) { + val[i] = fdtdec_get_uint(gd->fdt_blob, dev->of_offset, + ofcfg->grp[i].name, -1); + offset = ofcfg->grp[i].off; + if (val[i] == -1) { + /* Default register value for KSZ9021 */ + regval |= ofcfg->grp[i].dflt << offset; + } else { + changed = 1; /* Value was changed in OF */ + /* Calculate the register value and fix corner cases */ + if (val[i] > ps_to_regval * 0xf) { + max = (1 << ofcfg->grp[i].size) - 1; + regval |= max << offset; + } else { + regval |= (val[i] / ps_to_regval) << offset; + } + } + } + + if (!changed) + return 0; + + return drv->writeext(phydev, 0, ofcfg->devad, ofcfg->reg, regval); +} +#endif +#endif + +#ifdef CONFIG_PHY_MICREL_KSZ9021 +/* + * KSZ9021 + */ + +/* PHY Registers */ +#define MII_KSZ9021_EXTENDED_CTRL 0x0b +#define MII_KSZ9021_EXTENDED_DATAW 0x0c +#define MII_KSZ9021_EXTENDED_DATAR 0x0d + +#define CTRL1000_PREFER_MASTER (1 << 10) +#define CTRL1000_CONFIG_MASTER (1 << 11) +#define CTRL1000_MANUAL_CONFIG (1 << 12) + +#ifdef CONFIG_DM_ETH +static const struct ksz90x1_reg_field ksz9021_clk_grp[] = { + { "txen-skew-ps", 4, 0, 0x7 }, { "txc-skew-ps", 4, 4, 0x7 }, + { "rxdv-skew-ps", 4, 8, 0x7 }, { "rxc-skew-ps", 4, 12, 0x7 }, +}; + +static int ksz9021_of_config(struct phy_device *phydev) +{ + struct ksz90x1_ofcfg ofcfg[] = { + { MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0, ksz90x1_rxd_grp, 4 }, + { MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0, ksz90x1_txd_grp, 4 }, + { MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0, ksz9021_clk_grp, 4 }, + }; + int i, ret = 0; + + for (i = 0; i < ARRAY_SIZE(ofcfg); i++) + ret = ksz90x1_of_config_group(phydev, &(ofcfg[i])); + if (ret) + return ret; + + return 0; +} +#else +static int ksz9021_of_config(struct phy_device *phydev) +{ + return 0; +} +#endif + +int ksz9021_phy_extended_write(struct phy_device *phydev, int regnum, u16 val) +{ + /* extended registers */ + phy_write(phydev, MDIO_DEVAD_NONE, + MII_KSZ9021_EXTENDED_CTRL, regnum | 0x8000); + return phy_write(phydev, MDIO_DEVAD_NONE, + MII_KSZ9021_EXTENDED_DATAW, val); +} + +int ksz9021_phy_extended_read(struct phy_device *phydev, int regnum) +{ + /* extended registers */ + phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_CTRL, regnum); + return phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_DATAR); +} + + +static int ksz9021_phy_extread(struct phy_device *phydev, int addr, int devaddr, + int regnum) +{ + return ksz9021_phy_extended_read(phydev, regnum); +} + +static int ksz9021_phy_extwrite(struct phy_device *phydev, int addr, + int devaddr, int regnum, u16 val) +{ + return ksz9021_phy_extended_write(phydev, regnum, val); +} + +/* Micrel ksz9021 */ +static int ksz9021_config(struct phy_device *phydev) +{ + unsigned ctrl1000 = 0; + const unsigned master = CTRL1000_PREFER_MASTER | + CTRL1000_CONFIG_MASTER | CTRL1000_MANUAL_CONFIG; + unsigned features = phydev->drv->features; + int ret; + + ret = ksz9021_of_config(phydev); + if (ret) + return ret; + + if (getenv("disable_giga")) + features &= ~(SUPPORTED_1000baseT_Half | + SUPPORTED_1000baseT_Full); + /* force master mode for 1000BaseT due to chip errata */ + if (features & SUPPORTED_1000baseT_Half) + ctrl1000 |= ADVERTISE_1000HALF | master; + if (features & SUPPORTED_1000baseT_Full) + ctrl1000 |= ADVERTISE_1000FULL | master; + phydev->advertising = phydev->supported = features; + phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, ctrl1000); + genphy_config_aneg(phydev); + genphy_restart_aneg(phydev); + return 0; +} + +static struct phy_driver ksz9021_driver = { + .name = "Micrel ksz9021", + .uid = 0x221610, + .mask = 0xfffff0, + .features = PHY_GBIT_FEATURES, + .config = &ksz9021_config, + .startup = &ksz90xx_startup, + .shutdown = &genphy_shutdown, + .writeext = &ksz9021_phy_extwrite, + .readext = &ksz9021_phy_extread, +}; +#endif + +/** + * KSZ9031 + */ +/* PHY Registers */ +#define MII_KSZ9031_MMD_ACCES_CTRL 0x0d +#define MII_KSZ9031_MMD_REG_DATA 0x0e + +#ifdef CONFIG_DM_ETH +static const struct ksz90x1_reg_field ksz9031_ctl_grp[] = + { { "txen-skew-ps", 4, 0, 0x7 }, { "rxdv-skew-ps", 4, 4, 0x7 } }; +static const struct ksz90x1_reg_field ksz9031_clk_grp[] = + { { "rxc-skew-ps", 5, 0, 0xf }, { "txc-skew-ps", 5, 5, 0xf } }; + +static int ksz9031_of_config(struct phy_device *phydev) +{ + struct ksz90x1_ofcfg ofcfg[] = { + { MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, 2, ksz9031_ctl_grp, 2 }, + { MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, 2, ksz90x1_rxd_grp, 4 }, + { MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, 2, ksz90x1_txd_grp, 4 }, + { MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, 2, ksz9031_clk_grp, 2 }, + }; + int i, ret = 0; + + for (i = 0; i < ARRAY_SIZE(ofcfg); i++) + ret = ksz90x1_of_config_group(phydev, &(ofcfg[i])); + if (ret) + return ret; + + return 0; +} +#else +static int ksz9031_of_config(struct phy_device *phydev) +{ + return 0; +} +#endif + +/* Accessors to extended registers*/ +int ksz9031_phy_extended_write(struct phy_device *phydev, + int devaddr, int regnum, u16 mode, u16 val) +{ + /*select register addr for mmd*/ + phy_write(phydev, MDIO_DEVAD_NONE, + MII_KSZ9031_MMD_ACCES_CTRL, devaddr); + /*select register for mmd*/ + phy_write(phydev, MDIO_DEVAD_NONE, + MII_KSZ9031_MMD_REG_DATA, regnum); + /*setup mode*/ + phy_write(phydev, MDIO_DEVAD_NONE, + MII_KSZ9031_MMD_ACCES_CTRL, (mode | devaddr)); + /*write the value*/ + return phy_write(phydev, MDIO_DEVAD_NONE, + MII_KSZ9031_MMD_REG_DATA, val); +} + +int ksz9031_phy_extended_read(struct phy_device *phydev, int devaddr, + int regnum, u16 mode) +{ + phy_write(phydev, MDIO_DEVAD_NONE, + MII_KSZ9031_MMD_ACCES_CTRL, devaddr); + phy_write(phydev, MDIO_DEVAD_NONE, + MII_KSZ9031_MMD_REG_DATA, regnum); + phy_write(phydev, MDIO_DEVAD_NONE, + MII_KSZ9031_MMD_ACCES_CTRL, (devaddr | mode)); + return phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ9031_MMD_REG_DATA); +} + +static int ksz9031_phy_extread(struct phy_device *phydev, int addr, int devaddr, + int regnum) +{ + return ksz9031_phy_extended_read(phydev, devaddr, regnum, + MII_KSZ9031_MOD_DATA_NO_POST_INC); +}; + +static int ksz9031_phy_extwrite(struct phy_device *phydev, int addr, + int devaddr, int regnum, u16 val) +{ + return ksz9031_phy_extended_write(phydev, devaddr, regnum, + MII_KSZ9031_MOD_DATA_POST_INC_RW, val); +}; + +static int ksz9031_config(struct phy_device *phydev) +{ + int ret; + ret = ksz9031_of_config(phydev); + if (ret) + return ret; + return genphy_config(phydev); +} + +static struct phy_driver ksz9031_driver = { + .name = "Micrel ksz9031", + .uid = 0x221620, + .mask = 0xfffff0, + .features = PHY_GBIT_FEATURES, + .config = &ksz9031_config, + .startup = &ksz90xx_startup, + .shutdown = &genphy_shutdown, + .writeext = &ksz9031_phy_extwrite, + .readext = &ksz9031_phy_extread, +}; + +int phy_micrel_init(void) +{ + phy_register(&KSZ804_driver); + phy_register(&KSZ8031_driver); + phy_register(&KSZ8051_driver); + phy_register(&KSZ8081_driver); +#ifdef CONFIG_PHY_MICREL_KSZ9021 + phy_register(&ksz9021_driver); +#else + phy_register(&KS8721_driver); +#endif + phy_register(&ksz9031_driver); + phy_register(&ksz8895_driver); + return 0; +} diff --git a/sources/uboot-be550/drivers/net/phy/miiphybb.c b/sources/uboot-be550/drivers/net/phy/miiphybb.c new file mode 100644 index 00000000..8430dc4d --- /dev/null +++ b/sources/uboot-be550/drivers/net/phy/miiphybb.c @@ -0,0 +1,582 @@ +/* + * (C) Copyright 2009 Industrie Dial Face S.p.A. + * Luigi 'Comio' Mantellini + * + * (C) Copyright 2001 + * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com. + * + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * This provides a bit-banged interface to the ethernet MII management + * channel. + */ + +#include +#include +#include +#include + +#define BB_MII_RELOCATE(v,off) (v += (v?off:0)) + +#define MDIO_READ 2 +#define MDIO_WRITE 1 + +#define MDIO_C45 (1<<15) +#define MDIO_C45_ADDR (MDIO_C45 | 0) +#define MDIO_C45_READ (MDIO_C45 | 3) +#define MDIO_C45_WRITE (MDIO_C45 | 1) + +#define MDIO_SETUP_TIME 10 +#define MDIO_HOLD_TIME 10 + +DECLARE_GLOBAL_DATA_PTR; + +#ifndef CONFIG_BITBANGMII_MULTI + +/* + * If CONFIG_BITBANGMII_MULTI is not defined we use a + * compatibility layer with the previous miiphybb implementation + * based on macros usage. + * + */ +static int bb_mii_init_wrap(struct bb_miiphy_bus *bus) +{ +#ifdef MII_INIT + MII_INIT; +#endif + return 0; +} + +static int bb_mdio_active_wrap(struct bb_miiphy_bus *bus) +{ +#ifdef MDIO_DECLARE + MDIO_DECLARE; +#endif + MDIO_ACTIVE; + return 0; +} + +static int bb_mdio_tristate_wrap(struct bb_miiphy_bus *bus) +{ +#ifdef MDIO_DECLARE + MDIO_DECLARE; +#endif + MDIO_TRISTATE; + return 0; +} + +static int bb_set_mdio_wrap(struct bb_miiphy_bus *bus, int v) +{ +#ifdef MDIO_DECLARE + MDIO_DECLARE; +#endif + MDIO(v); + return 0; +} + +static int bb_get_mdio_wrap(struct bb_miiphy_bus *bus, int *v) +{ +#ifdef MDIO_DECLARE + MDIO_DECLARE; +#endif + *v = MDIO_READ; + return 0; +} + +static int bb_set_mdc_wrap(struct bb_miiphy_bus *bus, int v) +{ +#ifdef MDC_DECLARE + MDC_DECLARE; +#endif + MDC(v); + return 0; +} + +static int bb_delay_wrap(struct bb_miiphy_bus *bus) +{ + MIIDELAY; + return 0; +} + +struct bb_miiphy_bus bb_miiphy_buses[] = { + { + .name = BB_MII_DEVNAME, + .init = bb_mii_init_wrap, + .mdio_active = bb_mdio_active_wrap, + .mdio_tristate = bb_mdio_tristate_wrap, + .set_mdio = bb_set_mdio_wrap, + .get_mdio = bb_get_mdio_wrap, + .set_mdc = bb_set_mdc_wrap, + .delay = bb_delay_wrap, + } +}; + +int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) / + sizeof(bb_miiphy_buses[0]); +#endif + +void bb_miiphy_init(void) +{ + int i; + + for (i = 0; i < bb_miiphy_buses_num; i++) { +#if defined(CONFIG_NEEDS_MANUAL_RELOC) + /* Relocate the hook pointers*/ + BB_MII_RELOCATE(bb_miiphy_buses[i].init, gd->reloc_off); + BB_MII_RELOCATE(bb_miiphy_buses[i].mdio_active, gd->reloc_off); + BB_MII_RELOCATE(bb_miiphy_buses[i].mdio_tristate, gd->reloc_off); + BB_MII_RELOCATE(bb_miiphy_buses[i].set_mdio, gd->reloc_off); + BB_MII_RELOCATE(bb_miiphy_buses[i].get_mdio, gd->reloc_off); + BB_MII_RELOCATE(bb_miiphy_buses[i].set_mdc, gd->reloc_off); + BB_MII_RELOCATE(bb_miiphy_buses[i].delay, gd->reloc_off); +#endif + if (bb_miiphy_buses[i].init != NULL) { + bb_miiphy_buses[i].init(&bb_miiphy_buses[i]); + } + } +} + +static inline struct bb_miiphy_bus *bb_miiphy_getbus(const char *devname) +{ +#ifdef CONFIG_BITBANGMII_MULTI + int i; + + /* Search the correct bus */ + for (i = 0; i < bb_miiphy_buses_num; i++) { + if (!strcmp(bb_miiphy_buses[i].name, devname)) { + return &bb_miiphy_buses[i]; + } + } + return NULL; +#else + /* We have just one bitbanging bus */ + return &bb_miiphy_buses[0]; +#endif +} + +/***************************************************************************** + * + * Utility to send the preamble, address, and register (common to read + * and write). + */ +static void miiphy_pre(struct bb_miiphy_bus *bus, int read, + unsigned int addr, unsigned int reg) +{ + int j; + + /* + * Send a 32 bit preamble ('1's) with an extra '1' bit for good measure. + * The IEEE spec says this is a PHY optional requirement. The AMD + * 79C874 requires one after power up and one after a MII communications + * error. This means that we are doing more preambles than we need, + * but it is safer and will be much more robust. + */ + + bus->mdio_active(bus); + bus->set_mdio(bus, 1); + for (j = 0; j < 32; j++) { + bus->set_mdc(bus, 0); + bus->delay(bus); + bus->set_mdc(bus, 1); + bus->delay(bus); + } + + /* send the start bit (01) and the read opcode (10) or write (10) + * Clause 45 operation uses 00 for the start and 11, 10 for read/write + */ + bus->set_mdc(bus, 0); + bus->set_mdio(bus, 0); + bus->delay(bus); + bus->set_mdc(bus, 1); + bus->delay(bus); + bus->set_mdc(bus, 0); + if (read & MDIO_C45) + bus->set_mdio(bus, 0); + else + bus->set_mdio(bus, 1); + bus->delay(bus); + bus->set_mdc(bus, 1); + bus->delay(bus); + bus->set_mdc(bus, 0); + if (read & MDIO_C45) + bus->set_mdio(bus, ((read >> 1) & 1)); + else + bus->set_mdio(bus, read); + bus->delay(bus); + bus->set_mdc(bus, 1); + bus->delay(bus); + bus->set_mdc(bus, 0); + if (read & MDIO_C45) + bus->set_mdio(bus, ((read >> 0) & 1)); + else + bus->set_mdio(bus, !read); + bus->delay(bus); + bus->set_mdc(bus, 1); + bus->delay(bus); + + /* send the PHY address */ + for (j = 0; j < 5; j++) { + bus->set_mdc(bus, 0); + if ((addr & 0x10) == 0) { + bus->set_mdio(bus, 0); + } else { + bus->set_mdio(bus, 1); + } + bus->delay(bus); + bus->set_mdc(bus, 1); + bus->delay(bus); + addr <<= 1; + } + + /* send the register address */ + for (j = 0; j < 5; j++) { + bus->set_mdc(bus, 0); + if ((reg & 0x10) == 0) { + bus->set_mdio(bus, 0); + } else { + bus->set_mdio(bus, 1); + } + bus->delay(bus); + bus->set_mdc(bus, 1); + bus->delay(bus); + reg <<= 1; + } +} + +static int bb_miiphy_cmd_addr(struct bb_miiphy_bus *bus, unsigned phy_addr, + unsigned int reg_addr) +{ + unsigned int dev_reg = (reg_addr >> 16) & 0x1F; + unsigned int reg = reg_addr & 0xFFFF; + int v, i; + + miiphy_pre (bus, MDIO_C45_ADDR, phy_addr, dev_reg); + + /* send the turnaround (10) */ + bus->set_mdc(bus, 0); + bus->set_mdio(bus, 1); + bus->delay(bus); + bus->set_mdc(bus, 1); + bus->delay(bus); + bus->set_mdc(bus, 0); + bus->set_mdio(bus, 0); + bus->delay(bus); + bus->set_mdc(bus, 1); + bus->delay(bus); + + for (i = 15; i >= 0; i--) { + bus->set_mdc(bus, 0); + bus->set_mdio(bus, ((reg >> i) & 1)); + bus->delay(bus); + bus->set_mdc(bus, 1); + bus->delay(bus); + } + + /* tri-state our MDIO I/O pin so we can read */ + bus->set_mdc(bus, 0); + bus->mdio_tristate(bus); + bus->delay(bus); + bus->set_mdc(bus, 1); + bus->delay(bus); + bus->get_mdio(bus, &v); + bus->set_mdc(bus, 0); + + return dev_reg; +} + +/***************************************************************************** + * + * Read a MII PHY register V2. + * This API support C45 support + * Returns: + * 0 on success + */ + + +int bb_miiphy_read_v2(const char *devname, unsigned phy_addr, + unsigned int reg, unsigned short *value) +{ + short rdreg; /* register working value */ + int v; + int j; /* counter */ + struct bb_miiphy_bus *bus; + int phy_reg; + + bus = bb_miiphy_getbus(devname); + if (bus == NULL) { + return -1; + } + + if (value == NULL) { + puts("NULL value pointer\n"); + return -1; + } + + if (reg & MII_ADDR_C45) { + phy_reg = bb_miiphy_cmd_addr(bus, phy_addr, reg); + miiphy_pre(bus, MDIO_C45_READ, phy_addr, phy_reg); + } else { + miiphy_pre(bus, 1, phy_addr, reg); + } + + /* tri-state our MDIO I/O pin so we can read */ + bus->set_mdc(bus, 0); + bus->mdio_tristate(bus); + bus->delay(bus); + bus->set_mdc(bus, 1); + bus->delay(bus); + + /* check the turnaround bit: the PHY should be driving it to zero */ + bus->get_mdio(bus, &v); + if (v != 0) { + /* puts ("PHY didn't drive TA low\n"); */ + for (j = 0; j < 32; j++) { + bus->set_mdc(bus, 0); + bus->delay(bus); + bus->set_mdc(bus, 1); + bus->delay(bus); + } + /* There is no PHY, set value to 0xFFFF and return */ + *value = 0xFFFF; + return -1; + } + + bus->set_mdc(bus, 0); + bus->delay(bus); + + /* read 16 bits of register data, MSB first */ + rdreg = 0; + for (j = 0; j < 16; j++) { + bus->set_mdc(bus, 1); + bus->delay(bus); + rdreg <<= 1; + bus->get_mdio(bus, &v); + rdreg |= (v & 0x1); + bus->set_mdc(bus, 0); + bus->delay(bus); + } + + bus->set_mdc(bus, 1); + bus->delay(bus); + bus->set_mdc(bus, 0); + bus->delay(bus); + bus->set_mdc(bus, 1); + bus->delay(bus); + + *value = rdreg; + +#ifdef DEBUG + printf ("miiphy_read_v2(0x%x) @ 0x%x = 0x%04x\n", reg, addr, *value); +#endif + + return 0; +} + +/***************************************************************************** + * + * Read a MII PHY register. + * + * Returns: + * 0 on success + */ +int bb_miiphy_read(const char *devname, unsigned char addr, + unsigned char reg, unsigned short *value) +{ + short rdreg; /* register working value */ + int v; + int j; /* counter */ + struct bb_miiphy_bus *bus; + + bus = bb_miiphy_getbus(devname); + if (bus == NULL) { + return -1; + } + + if (value == NULL) { + puts("NULL value pointer\n"); + return -1; + } + + miiphy_pre (bus, 1, addr, reg); + + /* tri-state our MDIO I/O pin so we can read */ + bus->set_mdc(bus, 0); + bus->mdio_tristate(bus); + bus->delay(bus); + bus->set_mdc(bus, 1); + bus->delay(bus); + + /* check the turnaround bit: the PHY should be driving it to zero */ + bus->get_mdio(bus, &v); + if (v != 0) { + /* puts ("PHY didn't drive TA low\n"); */ + for (j = 0; j < 32; j++) { + bus->set_mdc(bus, 0); + bus->delay(bus); + bus->set_mdc(bus, 1); + bus->delay(bus); + } + /* There is no PHY, set value to 0xFFFF and return */ + *value = 0xFFFF; + return -1; + } + + bus->set_mdc(bus, 0); + bus->delay(bus); + + /* read 16 bits of register data, MSB first */ + rdreg = 0; + for (j = 0; j < 16; j++) { + bus->set_mdc(bus, 1); + bus->delay(bus); + rdreg <<= 1; + bus->get_mdio(bus, &v); + rdreg |= (v & 0x1); + bus->set_mdc(bus, 0); + bus->delay(bus); + } + + bus->set_mdc(bus, 1); + bus->delay(bus); + bus->set_mdc(bus, 0); + bus->delay(bus); + bus->set_mdc(bus, 1); + bus->delay(bus); + + *value = rdreg; + +#ifdef DEBUG + printf ("miiphy_read(0x%x) @ 0x%x = 0x%04x\n", reg, addr, *value); +#endif + + return 0; +} + + +/***************************************************************************** + * + * Write a MII PHY register V2. + * This API support C45 support + * Returns: + * 0 on success + */ +int bb_miiphy_write_v2(const char *devname, unsigned int phy_addr, + unsigned int reg, unsigned short value) +{ + struct bb_miiphy_bus *bus; + int j; /* counter */ + unsigned int phy_reg; + + bus = bb_miiphy_getbus(devname); + if (bus == NULL) { + /* Bus not found! */ + return -1; + } + + if (reg & MII_ADDR_C45) { + phy_reg = bb_miiphy_cmd_addr(bus, phy_addr, reg); + miiphy_pre(bus, MDIO_C45_WRITE, phy_addr, phy_reg); + } else { + miiphy_pre(bus, 0, phy_addr, reg); + } + + /* send the turnaround (10) */ + bus->set_mdc(bus, 0); + bus->set_mdio(bus, 1); + bus->delay(bus); + bus->set_mdc(bus, 1); + bus->delay(bus); + bus->set_mdc(bus, 0); + bus->set_mdio(bus, 0); + bus->delay(bus); + bus->set_mdc(bus, 1); + bus->delay(bus); + + /* write 16 bits of register data, MSB first */ + for (j = 0; j < 16; j++) { + bus->set_mdc(bus, 0); + if ((value & 0x00008000) == 0) { + bus->set_mdio(bus, 0); + } else { + bus->set_mdio(bus, 1); + } + bus->delay(bus); + bus->set_mdc(bus, 1); + bus->delay(bus); + value <<= 1; + } + + /* + * Tri-state the MDIO line. + */ + bus->mdio_tristate(bus); + bus->set_mdc(bus, 0); + bus->delay(bus); + bus->set_mdc(bus, 1); + bus->delay(bus); + + return 0; + +} +/***************************************************************************** + * + * Write a MII PHY register. + * + * Returns: + * 0 on success + */ +int bb_miiphy_write (const char *devname, unsigned char addr, + unsigned char reg, unsigned short value) +{ + struct bb_miiphy_bus *bus; + int j; /* counter */ + + bus = bb_miiphy_getbus(devname); + if (bus == NULL) { + /* Bus not found! */ + return -1; + } + + miiphy_pre (bus, 0, addr, reg); + + /* send the turnaround (10) */ + bus->set_mdc(bus, 0); + bus->set_mdio(bus, 1); + bus->delay(bus); + bus->set_mdc(bus, 1); + bus->delay(bus); + bus->set_mdc(bus, 0); + bus->set_mdio(bus, 0); + bus->delay(bus); + bus->set_mdc(bus, 1); + bus->delay(bus); + + /* write 16 bits of register data, MSB first */ + for (j = 0; j < 16; j++) { + bus->set_mdc(bus, 0); + if ((value & 0x00008000) == 0) { + bus->set_mdio(bus, 0); + } else { + bus->set_mdio(bus, 1); + } + bus->delay(bus); + bus->set_mdc(bus, 1); + bus->delay(bus); + value <<= 1; + } + + /* + * Tri-state the MDIO line. + */ + bus->mdio_tristate(bus); + bus->set_mdc(bus, 0); + bus->delay(bus); + bus->set_mdc(bus, 1); + bus->delay(bus); + + return 0; +} diff --git a/sources/uboot-be550/drivers/net/phy/mv88e61xx.c b/sources/uboot-be550/drivers/net/phy/mv88e61xx.c new file mode 100644 index 00000000..302abe86 --- /dev/null +++ b/sources/uboot-be550/drivers/net/phy/mv88e61xx.c @@ -0,0 +1,537 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor + * Prafulla Wadaskar + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include "mv88e61xx.h" + +/* + * Uncomment either of the following line for local debug control; + * otherwise global debug control will apply. + */ + +/* #undef DEBUG */ +/* #define DEBUG */ + +#ifdef CONFIG_MV88E61XX_MULTICHIP_ADRMODE +/* Chip Address mode + * The Switch support two modes of operation + * 1. single chip mode and + * 2. Multi-chip mode + * Refer section 9.2 &9.3 in chip datasheet-02 for more details + * + * By default single chip mode is configured + * multichip mode operation can be configured in board header + */ +static int mv88e61xx_busychk_multic(char *name, u32 devaddr) +{ + u16 reg = 0; + u32 timeout = MV88E61XX_PHY_TIMEOUT; + + /* Poll till SMIBusy bit is clear */ + do { + miiphy_read(name, devaddr, 0x0, ®); + if (timeout-- == 0) { + printf("SMI busy timeout\n"); + return -1; + } + } while (reg & (1 << 15)); + return 0; +} + +static void mv88e61xx_switch_write(char *name, u32 phy_adr, + u32 reg_ofs, u16 data) +{ + u16 mii_dev_addr; + + /* command to read PHY dev address */ + if (miiphy_read(name, 0xEE, 0xEE, &mii_dev_addr)) { + printf("Error..could not read PHY dev address\n"); + return; + } + mv88e61xx_busychk_multic(name, mii_dev_addr); + /* Write data to Switch indirect data register */ + miiphy_write(name, mii_dev_addr, 0x1, data); + /* Write command to Switch indirect command register (write) */ + miiphy_write(name, mii_dev_addr, 0x0, + reg_ofs | (phy_adr << 5) | (1 << 10) | (1 << 12) | (1 << + 15)); +} + +static void mv88e61xx_switch_read(char *name, u32 phy_adr, + u32 reg_ofs, u16 *data) +{ + u16 mii_dev_addr; + + /* command to read PHY dev address */ + if (miiphy_read(name, 0xEE, 0xEE, &mii_dev_addr)) { + printf("Error..could not read PHY dev address\n"); + return; + } + mv88e61xx_busychk_multic(name, mii_dev_addr); + /* Write command to Switch indirect command register (read) */ + miiphy_write(name, mii_dev_addr, 0x0, + reg_ofs | (phy_adr << 5) | (1 << 11) | (1 << 12) | (1 << + 15)); + mv88e61xx_busychk_multic(name, mii_dev_addr); + /* Read data from Switch indirect data register */ + miiphy_read(name, mii_dev_addr, 0x1, data); +} +#endif /* CONFIG_MV88E61XX_MULTICHIP_ADRMODE */ + +/* + * Convenience macros for switch device/port reads/writes + * These macros output valid 'mv88e61xx' U_BOOT_CMDs + */ + +#ifndef DEBUG +#define WR_SWITCH_REG wr_switch_reg +#define RD_SWITCH_REG rd_switch_reg +#define WR_SWITCH_PORT_REG(n, p, r, d) \ + WR_SWITCH_REG(n, (MV88E61XX_PRT_OFST+p), r, d) +#define RD_SWITCH_PORT_REG(n, p, r, d) \ + RD_SWITCH_REG(n, (MV88E61XX_PRT_OFST+p), r, d) +#else +static void WR_SWITCH_REG(char *name, u32 dev_adr, u32 reg_ofs, u16 data) +{ + printf("mv88e61xx %s dev %02x reg %02x write %04x\n", + name, dev_adr, reg_ofs, data); + wr_switch_reg(name, dev_adr, reg_ofs, data); +} +static void RD_SWITCH_REG(char *name, u32 dev_adr, u32 reg_ofs, u16 *data) +{ + rd_switch_reg(name, dev_adr, reg_ofs, data); + printf("mv88e61xx %s dev %02x reg %02x read %04x\n", + name, dev_adr, reg_ofs, *data); +} +static void WR_SWITCH_PORT_REG(char *name, u32 prt_adr, u32 reg_ofs, + u16 data) +{ + printf("mv88e61xx %s port %02x reg %02x write %04x\n", + name, prt_adr, reg_ofs, data); + wr_switch_reg(name, (MV88E61XX_PRT_OFST+prt_adr), reg_ofs, data); +} +static void RD_SWITCH_PORT_REG(char *name, u32 prt_adr, u32 reg_ofs, + u16 *data) +{ + rd_switch_reg(name, (MV88E61XX_PRT_OFST+prt_adr), reg_ofs, data); + printf("mv88e61xx %s port %02x reg %02x read %04x\n", + name, prt_adr, reg_ofs, *data); +} +#endif + +/* + * Local functions to read/write registers on the switch PHYs. + * NOTE! This goes through switch, not direct miiphy, writes and reads! + */ + +/* + * Make sure SMIBusy bit cleared before another + * SMI operation can take place + */ +static int mv88e61xx_busychk(char *name) +{ + u16 reg = 0; + u32 timeout = MV88E61XX_PHY_TIMEOUT; + do { + rd_switch_reg(name, MV88E61XX_GLB2REG_DEVADR, + MV88E61XX_PHY_CMD, ®); + if (timeout-- == 0) { + printf("SMI busy timeout\n"); + return -1; + } + } while (reg & 1 << 15); /* busy mask */ + return 0; +} + +static inline int mv88e61xx_switch_miiphy_write(char *name, u32 phy, + u32 reg, u16 data) +{ + /* write switch data reg then cmd reg then check completion */ + wr_switch_reg(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, + data); + wr_switch_reg(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_CMD, + (MV88E61XX_PHY_WRITE_CMD | (phy << 5) | reg)); + return mv88e61xx_busychk(name); +} + +static inline int mv88e61xx_switch_miiphy_read(char *name, u32 phy, + u32 reg, u16 *data) +{ + /* write switch cmd reg, check for completion */ + wr_switch_reg(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_CMD, + (MV88E61XX_PHY_READ_CMD | (phy << 5) | reg)); + if (mv88e61xx_busychk(name)) + return -1; + /* read switch data reg and return success */ + rd_switch_reg(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, data); + return 0; +} + +/* + * Convenience macros for switch PHY reads/writes + */ + +#ifndef DEBUG +#define WR_SWITCH_PHY_REG mv88e61xx_switch_miiphy_write +#define RD_SWITCH_PHY_REG mv88e61xx_switch_miiphy_read +#else +static inline int WR_SWITCH_PHY_REG(char *name, u32 phy_adr, + u32 reg_ofs, u16 data) +{ + int r = mv88e61xx_switch_miiphy_write(name, phy_adr, reg_ofs, data); + if (r) + printf("** ERROR writing mv88e61xx %s phy %02x reg %02x\n", + name, phy_adr, reg_ofs); + else + printf("mv88e61xx %s phy %02x reg %02x write %04x\n", + name, phy_adr, reg_ofs, data); + return r; +} +static inline int RD_SWITCH_PHY_REG(char *name, u32 phy_adr, + u32 reg_ofs, u16 *data) +{ + int r = mv88e61xx_switch_miiphy_read(name, phy_adr, reg_ofs, data); + if (r) + printf("** ERROR reading mv88e61xx %s phy %02x reg %02x\n", + name, phy_adr, reg_ofs); + else + printf("mv88e61xx %s phy %02x reg %02x read %04x\n", + name, phy_adr, reg_ofs, *data); + return r; +} +#endif + +static void mv88e61xx_port_vlan_config(struct mv88e61xx_config *swconfig) +{ + u32 prt; + u16 reg; + char *name = swconfig->name; + u32 port_mask = swconfig->ports_enabled; + + /* apply internal vlan config */ + for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) { + /* only for enabled ports */ + if ((1 << prt) & port_mask) { + /* take vlan map from swconfig */ + u8 vlanmap = swconfig->vlancfg[prt]; + /* remove disabled ports from vlan map */ + vlanmap &= swconfig->ports_enabled; + /* apply vlan map to port */ + RD_SWITCH_PORT_REG(name, prt, + MV88E61XX_PRT_VMAP_REG, ®); + reg &= ~((1 << MV88E61XX_MAX_PORTS_NUM) - 1); + reg |= vlanmap; + WR_SWITCH_PORT_REG(name, prt, + MV88E61XX_PRT_VMAP_REG, reg); + } + } +} + +/* + * Power up the specified port and reset PHY + */ +static int mv88361xx_powerup(struct mv88e61xx_config *swconfig, u32 phy) +{ + char *name = swconfig->name; + + /* Write Copper Specific control reg1 (0x10) for- + * Enable Phy power up + * Energy Detect on (sense&Xmit NLP Periodically + * reset other settings default + */ + if (WR_SWITCH_PHY_REG(name, phy, 0x10, 0x3360)) + return -1; + + /* Write PHY ctrl reg (0x0) to apply + * Phy reset (set bit 15 low) + * reset other default values + */ + if (WR_SWITCH_PHY_REG(name, phy, 0x00, 0x9140)) + return -1; + + return 0; +} + +/* + * Default Setup for LED[0]_Control (ref: Table 46 Datasheet-3) + * is set to "On-1000Mb/s Link, Off Else" + * This function sets it to "On-Link, Blink-Activity, Off-NoLink" + * + * This is optional settings may be needed on some boards + * to setup PHY LEDs default configuration to detect 10/100/1000Mb/s + * Link status + */ +static int mv88361xx_led_init(struct mv88e61xx_config *swconfig, u32 phy) +{ + char *name = swconfig->name; + + if (swconfig->led_init != MV88E61XX_LED_INIT_EN) + return 0; + + /* set page address to 3 */ + if (WR_SWITCH_PHY_REG(name, phy, 0x16, 0x0003)) + return -1; + + /* + * set LED Func Ctrl reg + * value 0x0001 = LED[0] On-Link, Blink-Activity, Off-NoLink + */ + if (WR_SWITCH_PHY_REG(name, phy, 0x10, 0x0001)) + return -1; + + /* set page address to 0 */ + if (WR_SWITCH_PHY_REG(name, phy, 0x16, 0x0000)) + return -1; + + return 0; +} + +/* + * Reverse Transmit polarity for Media Dependent Interface + * Pins (MDIP) bits in Copper Specific Control Register 3 + * (Page 0, Reg 20 for each phy (except cpu port) + * Reference: Section 1.1 Switch datasheet-3 + * + * This is optional settings may be needed on some boards + * for PHY<->magnetics h/w tuning + */ +static int mv88361xx_reverse_mdipn(struct mv88e61xx_config *swconfig, u32 phy) +{ + char *name = swconfig->name; + + if (swconfig->mdip != MV88E61XX_MDIP_REVERSE) + return 0; + + /*Reverse MDIP/N[3:0] bits */ + if (WR_SWITCH_PHY_REG(name, phy, 0x14, 0x000f)) + return -1; + + return 0; +} + +/* + * Marvell 88E61XX Switch initialization + */ +int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig) +{ + u32 prt; + u16 reg; + char *idstr; + char *name = swconfig->name; + int time; + + if (miiphy_set_current_dev(name)) { + printf("%s failed\n", __FUNCTION__); + return -1; + } + + if (!(swconfig->cpuport & ((1 << 4) | (1 << 5)))) { + swconfig->cpuport = (1 << 5); + printf("Invalid cpu port config, using default port5\n"); + } + + RD_SWITCH_PORT_REG(name, 0, MII_PHYSID2, ®); + switch (reg &= 0xfff0) { + case 0x1610: + idstr = "88E6161"; + break; + case 0x1650: + idstr = "88E6165"; + break; + case 0x1210: + idstr = "88E6123"; + /* ports 2,3,4 not available */ + swconfig->ports_enabled &= 0x023; + break; + default: + /* Could not detect switch id */ + idstr = "88E61??"; + break; + } + + /* be sure all ports are disabled */ + for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) { + RD_SWITCH_PORT_REG(name, prt, MV88E61XX_PRT_CTRL_REG, ®); + reg &= ~0x3; + WR_SWITCH_PORT_REG(name, prt, MV88E61XX_PRT_CTRL_REG, reg); + } + + /* wait 2 ms for queues to drain */ + udelay(2000); + + /* reset switch */ + RD_SWITCH_REG(name, MV88E61XX_GLBREG_DEVADR, MV88E61XX_SGCR, ®); + reg |= 0x8000; + WR_SWITCH_REG(name, MV88E61XX_GLBREG_DEVADR, MV88E61XX_SGCR, reg); + + /* wait up to 1 second for switch reset complete */ + for (time = 1000; time; time--) { + RD_SWITCH_REG(name, MV88E61XX_GLBREG_DEVADR, MV88E61XX_SGSR, + ®); + if ((reg & 0xc800) == 0xc800) + break; + udelay(1000); + } + if (!time) + return -1; + + /* Port based VLANs configuration */ + mv88e61xx_port_vlan_config(swconfig); + + if (swconfig->rgmii_delay == MV88E61XX_RGMII_DELAY_EN) { + /* + * Enable RGMII delay on Tx and Rx for CPU port + * Ref: sec 9.5 of chip datasheet-02 + */ + /*Force port link down */ + WR_SWITCH_PORT_REG(name, 5, MV88E61XX_PCS_CTRL_REG, 0x10); + /* configure port RGMII delay */ + WR_SWITCH_PORT_REG(name, 4, + MV88E61XX_RGMII_TIMECTRL_REG, 0x81e7); + RD_SWITCH_PORT_REG(name, 5, + MV88E61XX_RGMII_TIMECTRL_REG, ®); + WR_SWITCH_PORT_REG(name, 5, + MV88E61XX_RGMII_TIMECTRL_REG, reg | 0x18); + WR_SWITCH_PORT_REG(name, 4, + MV88E61XX_RGMII_TIMECTRL_REG, 0xc1e7); + /* Force port to RGMII FDX 1000Base then up */ + WR_SWITCH_PORT_REG(name, 5, MV88E61XX_PCS_CTRL_REG, 0x1e); + WR_SWITCH_PORT_REG(name, 5, MV88E61XX_PCS_CTRL_REG, 0x3e); + } + + for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) { + + /* configure port's PHY */ + if (!((1 << prt) & swconfig->cpuport)) { + /* port 4 has phy 6, not 4 */ + int phy = (prt == 4) ? 6 : prt; + if (mv88361xx_powerup(swconfig, phy)) + return -1; + if (mv88361xx_reverse_mdipn(swconfig, phy)) + return -1; + if (mv88361xx_led_init(swconfig, phy)) + return -1; + } + + /* set port VID to port+1 except for cpu port */ + if (!((1 << prt) & swconfig->cpuport)) { + RD_SWITCH_PORT_REG(name, prt, + MV88E61XX_PRT_VID_REG, ®); + WR_SWITCH_PORT_REG(name, prt, + MV88E61XX_PRT_VID_REG, + (reg & ~1023) | (prt+1)); + } + + /*Program port state */ + RD_SWITCH_PORT_REG(name, prt, + MV88E61XX_PRT_CTRL_REG, ®); + WR_SWITCH_PORT_REG(name, prt, + MV88E61XX_PRT_CTRL_REG, + reg | (swconfig->portstate & 0x03)); + + } + + printf("%s Initialized on %s\n", idstr, name); + return 0; +} + +#ifdef CONFIG_MV88E61XX_CMD +static int +do_switch(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + char *name, *endp; + int write = 0; + enum { dev, prt, phy } target = dev; + u32 addrlo, addrhi, addr; + u32 reglo, reghi, reg; + u16 data, rdata; + + if (argc < 7) + return -1; + + name = argv[1]; + + if (strcmp(argv[2], "phy") == 0) + target = phy; + else if (strcmp(argv[2], "port") == 0) + target = prt; + else if (strcmp(argv[2], "dev") != 0) + return 1; + + addrlo = simple_strtoul(argv[3], &endp, 16); + + if (!*endp) { + addrhi = addrlo; + } else { + while (*endp < '0' || *endp > '9') + endp++; + addrhi = simple_strtoul(endp, NULL, 16); + } + + reglo = simple_strtoul(argv[5], &endp, 16); + if (!*endp) { + reghi = reglo; + } else { + while (*endp < '0' || *endp > '9') + endp++; + reghi = simple_strtoul(endp, NULL, 16); + } + + if (strcmp(argv[6], "write") == 0) + write = 1; + else if (strcmp(argv[6], "read") != 0) + return 1; + + data = simple_strtoul(argv[7], NULL, 16); + + for (addr = addrlo; addr <= addrhi; addr++) { + for (reg = reglo; reg <= reghi; reg++) { + if (write) { + if (target == phy) + mv88e61xx_switch_miiphy_write( + name, addr, reg, data); + else if (target == prt) + wr_switch_reg(name, + addr+MV88E61XX_PRT_OFST, + reg, data); + else + wr_switch_reg(name, addr, reg, data); + } else { + if (target == phy) + mv88e61xx_switch_miiphy_read( + name, addr, reg, &rdata); + else if (target == prt) + rd_switch_reg(name, + addr+MV88E61XX_PRT_OFST, + reg, &rdata); + else + rd_switch_reg(name, addr, reg, &rdata); + printf("%s %s %s %02x %s %02x %s %04x\n", + argv[0], argv[1], argv[2], addr, + argv[4], reg, argv[6], rdata); + if (write && argc == 7 && rdata != data) + return 1; + } + } + } + return 0; +} + +U_BOOT_CMD(mv88e61xx, 8, 0, do_switch, + "Read or write mv88e61xx switch registers", + " dev|port|phy reg write \n" + " dev|port|phy reg read []\n" + " - read/write switch device, port or phy at (addr,reg)\n" + " addr=0..0x1C for dev, 0..5 for port or phy.\n" + " reg=0..0x1F.\n" + " data=0..0xFFFF (tested if present against actual read).\n" + " All numeric parameters are assumed to be hex.\n" + " and < arguments can be ranges (x..y)" +); +#endif /* CONFIG_MV88E61XX_CMD */ diff --git a/sources/uboot-be550/drivers/net/phy/mv88e61xx.h b/sources/uboot-be550/drivers/net/phy/mv88e61xx.h new file mode 100644 index 00000000..9c62e4a7 --- /dev/null +++ b/sources/uboot-be550/drivers/net/phy/mv88e61xx.h @@ -0,0 +1,61 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor + * Prafulla Wadaskar + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _MV88E61XX_H +#define _MV88E61XX_H + +#include + +#define MV88E61XX_CPU_PORT 0x5 + +#define MV88E61XX_PHY_TIMEOUT 100000 + +/* port dev-addr (= port + 0x10) */ +#define MV88E61XX_PRT_OFST 0x10 +/* port registers */ +#define MV88E61XX_PCS_CTRL_REG 0x1 +#define MV88E61XX_PRT_CTRL_REG 0x4 +#define MV88E61XX_PRT_VMAP_REG 0x6 +#define MV88E61XX_PRT_VID_REG 0x7 +#define MV88E61XX_RGMII_TIMECTRL_REG 0x1A + +/* global registers dev-addr */ +#define MV88E61XX_GLBREG_DEVADR 0x1B +/* global registers */ +#define MV88E61XX_SGSR 0x00 +#define MV88E61XX_SGCR 0x04 + +/* global 2 registers dev-addr */ +#define MV88E61XX_GLB2REG_DEVADR 0x1C +/* global 2 registers */ +#define MV88E61XX_PHY_CMD 0x18 +#define MV88E61XX_PHY_DATA 0x19 +/* global 2 phy commands */ +#define MV88E61XX_PHY_WRITE_CMD 0x9400 +#define MV88E61XX_PHY_READ_CMD 0x9800 + +#define MV88E61XX_BUSY_OFST 15 +#define MV88E61XX_MODE_OFST 12 +#define MV88E61XX_OP_OFST 10 +#define MV88E61XX_ADDR_OFST 5 + +#ifdef CONFIG_MV88E61XX_MULTICHIP_ADRMODE +static int mv88e61xx_busychk_multic(char *name, u32 devaddr); +static void mv88e61xx_switch_write(char *name, u32 phy_adr, + u32 reg_ofs, u16 data); +static void mv88e61xx_switch_read(char *name, u32 phy_adr, + u32 reg_ofs, u16 *data); +#define wr_switch_reg mv88e61xx_switch_write +#define rd_switch_reg mv88e61xx_switch_read +#else +/* switch appears a s simple PHY and can thus use miiphy */ +#define wr_switch_reg miiphy_write +#define rd_switch_reg miiphy_read +#endif /* CONFIG_MV88E61XX_MULTICHIP_ADRMODE */ + +#endif /* _MV88E61XX_H */ diff --git a/sources/uboot-be550/drivers/net/phy/mv88e6352.c b/sources/uboot-be550/drivers/net/phy/mv88e6352.c new file mode 100644 index 00000000..f639a42f --- /dev/null +++ b/sources/uboot-be550/drivers/net/phy/mv88e6352.c @@ -0,0 +1,302 @@ +/* + * (C) Copyright 2012 + * Valentin Lontgchamp, Keymile AG, valentin.longchamp@keymile.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +#define SMI_HDR ((0x8 | 0x1) << 12) +#define SMI_BUSY_MASK (0x8000) +#define SMIRD_OP (0x2 << 10) +#define SMIWR_OP (0x1 << 10) +#define SMI_MASK 0x1f +#define PORT_SHIFT 5 + +#define COMMAND_REG 0 +#define DATA_REG 1 + +/* global registers */ +#define GLOBAL 0x1b + +#define GLOBAL_STATUS 0x00 +#define PPU_STATE 0x8000 + +#define GLOBAL_CTRL 0x04 +#define SW_RESET 0x8000 +#define PPU_ENABLE 0x4000 + +static int sw_wait_rdy(const char *devname, u8 phy_addr) +{ + u16 command; + u32 timeout = 100; + int ret; + + /* wait till the SMI is not busy */ + do { + /* read command register */ + ret = miiphy_read(devname, phy_addr, COMMAND_REG, &command); + if (ret < 0) { + printf("%s: Error reading command register\n", + __func__); + return ret; + } + if (timeout-- == 0) { + printf("Err..(%s) SMI busy timeout\n", __func__); + return -EFAULT; + } + } while (command & SMI_BUSY_MASK); + + return 0; +} + +static int sw_reg_read(const char *devname, u8 phy_addr, u8 port, + u8 reg, u16 *data) +{ + int ret; + u16 command; + + ret = sw_wait_rdy(devname, phy_addr); + if (ret) + return ret; + + command = SMI_HDR | SMIRD_OP | ((port&SMI_MASK) << PORT_SHIFT) | + (reg & SMI_MASK); + debug("%s: write to command: %#x\n", __func__, command); + ret = miiphy_write(devname, phy_addr, COMMAND_REG, command); + if (ret) + return ret; + + ret = sw_wait_rdy(devname, phy_addr); + if (ret) + return ret; + + ret = miiphy_read(devname, phy_addr, DATA_REG, data); + + return ret; +} + +static int sw_reg_write(const char *devname, u8 phy_addr, u8 port, + u8 reg, u16 data) +{ + int ret; + u16 value; + + ret = sw_wait_rdy(devname, phy_addr); + if (ret) + return ret; + + debug("%s: write to data: %#x\n", __func__, data); + ret = miiphy_write(devname, phy_addr, DATA_REG, data); + if (ret) + return ret; + + value = SMI_HDR | SMIWR_OP | ((port & SMI_MASK) << PORT_SHIFT) | + (reg & SMI_MASK); + debug("%s: write to command: %#x\n", __func__, value); + ret = miiphy_write(devname, phy_addr, COMMAND_REG, value); + if (ret) + return ret; + + ret = sw_wait_rdy(devname, phy_addr); + if (ret) + return ret; + + return 0; +} + +static int ppu_enable(const char *devname, u8 phy_addr) +{ + int i, ret = 0; + u16 reg; + + ret = sw_reg_read(devname, phy_addr, GLOBAL, GLOBAL_CTRL, ®); + if (ret) { + printf("%s: Error reading global ctrl reg\n", __func__); + return ret; + } + + reg |= PPU_ENABLE; + + ret = sw_reg_write(devname, phy_addr, GLOBAL, GLOBAL_CTRL, reg); + if (ret) { + printf("%s: Error writing global ctrl reg\n", __func__); + return ret; + } + + for (i = 0; i < 1000; i++) { + sw_reg_read(devname, phy_addr, GLOBAL, GLOBAL_STATUS, + ®); + if ((reg & 0xc000) == 0xc000) + return 0; + udelay(1000); + } + + return -ETIMEDOUT; +} + +static int ppu_disable(const char *devname, u8 phy_addr) +{ + int i, ret = 0; + u16 reg; + + ret = sw_reg_read(devname, phy_addr, GLOBAL, GLOBAL_CTRL, ®); + if (ret) { + printf("%s: Error reading global ctrl reg\n", __func__); + return ret; + } + + reg &= ~PPU_ENABLE; + + ret = sw_reg_write(devname, phy_addr, GLOBAL, GLOBAL_CTRL, reg); + if (ret) { + printf("%s: Error writing global ctrl reg\n", __func__); + return ret; + } + + for (i = 0; i < 1000; i++) { + sw_reg_read(devname, phy_addr, GLOBAL, GLOBAL_STATUS, + ®); + if ((reg & 0xc000) != 0xc000) + return 0; + udelay(1000); + } + + return -ETIMEDOUT; +} + +int mv88e_sw_program(const char *devname, u8 phy_addr, + struct mv88e_sw_reg *regs, int regs_nb) +{ + int i, ret = 0; + + /* first we need to disable the PPU */ + ret = ppu_disable(devname, phy_addr); + if (ret) { + printf("%s: Error disabling PPU\n", __func__); + return ret; + } + + for (i = 0; i < regs_nb; i++) { + ret = sw_reg_write(devname, phy_addr, regs[i].port, + regs[i].reg, regs[i].value); + if (ret) { + printf("%s: Error configuring switch\n", __func__); + ppu_enable(devname, phy_addr); + return ret; + } + } + + /* re-enable the PPU */ + ret = ppu_enable(devname, phy_addr); + if (ret) { + printf("%s: Error enabling PPU\n", __func__); + return ret; + } + + return 0; +} + +int mv88e_sw_reset(const char *devname, u8 phy_addr) +{ + int i, ret = 0; + u16 reg; + + ret = sw_reg_read(devname, phy_addr, GLOBAL, GLOBAL_CTRL, ®); + if (ret) { + printf("%s: Error reading global ctrl reg\n", __func__); + return ret; + } + + reg = SW_RESET | PPU_ENABLE | 0x0400; + + ret = sw_reg_write(devname, phy_addr, GLOBAL, GLOBAL_CTRL, reg); + if (ret) { + printf("%s: Error writing global ctrl reg\n", __func__); + return ret; + } + + for (i = 0; i < 1000; i++) { + sw_reg_read(devname, phy_addr, GLOBAL, GLOBAL_STATUS, + ®); + if ((reg & 0xc800) != 0xc800) + return 0; + udelay(1000); + } + + return -ETIMEDOUT; +} + +int do_mvsw_reg_read(const char *name, int argc, char * const argv[]) +{ + u16 value = 0, phyaddr, reg, port; + int ret; + + phyaddr = simple_strtoul(argv[1], NULL, 10); + port = simple_strtoul(argv[2], NULL, 10); + reg = simple_strtoul(argv[3], NULL, 10); + + ret = sw_reg_read(name, phyaddr, port, reg, &value); + printf("%#x\n", value); + + return ret; +} + +int do_mvsw_reg_write(const char *name, int argc, char * const argv[]) +{ + u16 value = 0, phyaddr, reg, port; + int ret; + + phyaddr = simple_strtoul(argv[1], NULL, 10); + port = simple_strtoul(argv[2], NULL, 10); + reg = simple_strtoul(argv[3], NULL, 10); + value = simple_strtoul(argv[4], NULL, 16); + + ret = sw_reg_write(name, phyaddr, port, reg, value); + + return ret; +} + + +int do_mvsw_reg(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int ret; + const char *cmd, *ethname; + + if (argc < 2) + return cmd_usage(cmdtp); + + cmd = argv[1]; + --argc; + ++argv; + + if (strcmp(cmd, "read") == 0) { + if (argc < 5) + return cmd_usage(cmdtp); + ethname = argv[1]; + --argc; + ++argv; + ret = do_mvsw_reg_read(ethname, argc, argv); + } else if (strcmp(cmd, "write") == 0) { + if (argc < 6) + return cmd_usage(cmdtp); + ethname = argv[1]; + --argc; + ++argv; + ret = do_mvsw_reg_write(ethname, argc, argv); + } else + return cmd_usage(cmdtp); + + return ret; +} + +U_BOOT_CMD( + mvsw_reg, 7, 1, do_mvsw_reg, + "marvell 88e6352 switch register access", + "write ethname phyaddr port reg value\n" + "mvsw_reg read ethname phyaddr port reg\n" + ); diff --git a/sources/uboot-be550/drivers/net/phy/natsemi.c b/sources/uboot-be550/drivers/net/phy/natsemi.c new file mode 100644 index 00000000..d2e4c3c4 --- /dev/null +++ b/sources/uboot-be550/drivers/net/phy/natsemi.c @@ -0,0 +1,160 @@ +/* + * National Semiconductor PHY drivers + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Copyright 2010-2011 Freescale Semiconductor, Inc. + * author Andy Fleming + */ +#include + +/* NatSemi DP83630 */ + +#define DP83630_PHY_PAGESEL_REG 0x13 +#define DP83630_PHY_PTP_COC_REG 0x14 +#define DP83630_PHY_PTP_CLKOUT_EN (1<<15) +#define DP83630_PHY_RBR_REG 0x17 + +static int dp83630_config(struct phy_device *phydev) +{ + int ptp_coc_reg; + + phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); + phy_write(phydev, MDIO_DEVAD_NONE, DP83630_PHY_PAGESEL_REG, 0x6); + ptp_coc_reg = phy_read(phydev, MDIO_DEVAD_NONE, + DP83630_PHY_PTP_COC_REG); + ptp_coc_reg &= ~DP83630_PHY_PTP_CLKOUT_EN; + phy_write(phydev, MDIO_DEVAD_NONE, DP83630_PHY_PTP_COC_REG, + ptp_coc_reg); + phy_write(phydev, MDIO_DEVAD_NONE, DP83630_PHY_PAGESEL_REG, 0); + + genphy_config_aneg(phydev); + + return 0; +} + +static struct phy_driver DP83630_driver = { + .name = "NatSemi DP83630", + .uid = 0x20005ce1, + .mask = 0xfffffff0, + .features = PHY_BASIC_FEATURES, + .config = &dp83630_config, + .startup = &genphy_startup, + .shutdown = &genphy_shutdown, +}; + + +/* DP83865 Link and Auto-Neg Status Register */ +#define MIIM_DP83865_LANR 0x11 +#define MIIM_DP83865_SPD_MASK 0x0018 +#define MIIM_DP83865_SPD_1000 0x0010 +#define MIIM_DP83865_SPD_100 0x0008 +#define MIIM_DP83865_DPX_FULL 0x0002 + + +/* NatSemi DP83865 */ +static int dp838xx_config(struct phy_device *phydev) +{ + phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); + genphy_config_aneg(phydev); + + return 0; +} + +static int dp83865_parse_status(struct phy_device *phydev) +{ + int mii_reg; + + mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_DP83865_LANR); + + switch (mii_reg & MIIM_DP83865_SPD_MASK) { + + case MIIM_DP83865_SPD_1000: + phydev->speed = SPEED_1000; + break; + + case MIIM_DP83865_SPD_100: + phydev->speed = SPEED_100; + break; + + default: + phydev->speed = SPEED_10; + break; + + } + + if (mii_reg & MIIM_DP83865_DPX_FULL) + phydev->duplex = DUPLEX_FULL; + else + phydev->duplex = DUPLEX_HALF; + + return 0; +} + +static int dp83865_startup(struct phy_device *phydev) +{ + genphy_update_link(phydev); + dp83865_parse_status(phydev); + + return 0; +} + + +static struct phy_driver DP83865_driver = { + .name = "NatSemi DP83865", + .uid = 0x20005c70, + .mask = 0xfffffff0, + .features = PHY_GBIT_FEATURES, + .config = &dp838xx_config, + .startup = &dp83865_startup, + .shutdown = &genphy_shutdown, +}; + +/* NatSemi DP83848 */ +static int dp83848_parse_status(struct phy_device *phydev) +{ + int mii_reg; + + mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR); + + if(mii_reg & (BMSR_100FULL | BMSR_100HALF)) { + phydev->speed = SPEED_100; + } else { + phydev->speed = SPEED_10; + } + + if (mii_reg & (BMSR_10FULL | BMSR_100FULL)) { + phydev->duplex = DUPLEX_FULL; + } else { + phydev->duplex = DUPLEX_HALF; + } + + return 0; +} + +static int dp83848_startup(struct phy_device *phydev) +{ + genphy_update_link(phydev); + dp83848_parse_status(phydev); + + return 0; +} + +static struct phy_driver DP83848_driver = { + .name = "NatSemi DP83848", + .uid = 0x20005c90, + .mask = 0x2000ff90, + .features = PHY_BASIC_FEATURES, + .config = &dp838xx_config, + .startup = &dp83848_startup, + .shutdown = &genphy_shutdown, +}; + +int phy_natsemi_init(void) +{ + phy_register(&DP83630_driver); + phy_register(&DP83865_driver); + phy_register(&DP83848_driver); + + return 0; +} diff --git a/sources/uboot-be550/drivers/net/phy/phy.c b/sources/uboot-be550/drivers/net/phy/phy.c new file mode 100644 index 00000000..51b5746a --- /dev/null +++ b/sources/uboot-be550/drivers/net/phy/phy.c @@ -0,0 +1,867 @@ +/* + * Generic PHY Management code + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Copyright 2011 Freescale Semiconductor, Inc. + * author Andy Fleming + * + * Based loosely off of Linux's PHY Lib + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* Generic PHY support and helper functions */ + +/** + * genphy_config_advert - sanitize and advertise auto-negotation parameters + * @phydev: target phy_device struct + * + * Description: Writes MII_ADVERTISE with the appropriate values, + * after sanitizing the values to make sure we only advertise + * what is supported. Returns < 0 on error, 0 if the PHY's advertisement + * hasn't changed, and > 0 if it has changed. + */ +static int genphy_config_advert(struct phy_device *phydev) +{ + u32 advertise; + int oldadv, adv; + int err, changed = 0; + + /* Only allow advertising what + * this PHY supports */ + phydev->advertising &= phydev->supported; + advertise = phydev->advertising; + + /* Setup standard advertisement */ + oldadv = adv = phy_read(phydev, MDIO_DEVAD_NONE, MII_ADVERTISE); + + if (adv < 0) + return adv; + + adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | + ADVERTISE_PAUSE_ASYM); + if (advertise & ADVERTISED_10baseT_Half) + adv |= ADVERTISE_10HALF; + if (advertise & ADVERTISED_10baseT_Full) + adv |= ADVERTISE_10FULL; + if (advertise & ADVERTISED_100baseT_Half) + adv |= ADVERTISE_100HALF; + if (advertise & ADVERTISED_100baseT_Full) + adv |= ADVERTISE_100FULL; + if (advertise & ADVERTISED_Pause) + adv |= ADVERTISE_PAUSE_CAP; + if (advertise & ADVERTISED_Asym_Pause) + adv |= ADVERTISE_PAUSE_ASYM; + if (advertise & ADVERTISED_1000baseX_Half) + adv |= ADVERTISE_1000XHALF; + if (advertise & ADVERTISED_1000baseX_Full) + adv |= ADVERTISE_1000XFULL; + + if (adv != oldadv) { + err = phy_write(phydev, MDIO_DEVAD_NONE, MII_ADVERTISE, adv); + + if (err < 0) + return err; + changed = 1; + } + + /* Configure gigabit if it's supported */ + if (phydev->supported & (SUPPORTED_1000baseT_Half | + SUPPORTED_1000baseT_Full)) { + oldadv = adv = phy_read(phydev, MDIO_DEVAD_NONE, MII_CTRL1000); + + if (adv < 0) + return adv; + + adv &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); + if (advertise & SUPPORTED_1000baseT_Half) + adv |= ADVERTISE_1000HALF; + if (advertise & SUPPORTED_1000baseT_Full) + adv |= ADVERTISE_1000FULL; + + if (adv != oldadv) { + err = phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, + adv); + + if (err < 0) + return err; + changed = 1; + } + } + + return changed; +} + + +/** + * genphy_setup_forced - configures/forces speed/duplex from @phydev + * @phydev: target phy_device struct + * + * Description: Configures MII_BMCR to force speed/duplex + * to the values in phydev. Assumes that the values are valid. + */ +static int genphy_setup_forced(struct phy_device *phydev) +{ + int err; + int ctl = 0; + + phydev->pause = phydev->asym_pause = 0; + + if (SPEED_1000 == phydev->speed) + ctl |= BMCR_SPEED1000; + else if (SPEED_100 == phydev->speed) + ctl |= BMCR_SPEED100; + + if (DUPLEX_FULL == phydev->duplex) + ctl |= BMCR_FULLDPLX; + + err = phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, ctl); + + return err; +} + + +/** + * genphy_restart_aneg - Enable and Restart Autonegotiation + * @phydev: target phy_device struct + */ +int genphy_restart_aneg(struct phy_device *phydev) +{ + int ctl; + + ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); + + if (ctl < 0) + return ctl; + + ctl |= (BMCR_ANENABLE | BMCR_ANRESTART); + + /* Don't isolate the PHY if we're negotiating */ + ctl &= ~(BMCR_ISOLATE); + + ctl = phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, ctl); + + return ctl; +} + + +/** + * genphy_config_aneg - restart auto-negotiation or write BMCR + * @phydev: target phy_device struct + * + * Description: If auto-negotiation is enabled, we configure the + * advertising, and then restart auto-negotiation. If it is not + * enabled, then we write the BMCR. + */ +int genphy_config_aneg(struct phy_device *phydev) +{ + int result; + + if (AUTONEG_ENABLE != phydev->autoneg) + return genphy_setup_forced(phydev); + + result = genphy_config_advert(phydev); + + if (result < 0) /* error */ + return result; + + if (result == 0) { + /* Advertisment hasn't changed, but maybe aneg was never on to + * begin with? Or maybe phy was isolated? */ + int ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); + + if (ctl < 0) + return ctl; + + if (!(ctl & BMCR_ANENABLE) || (ctl & BMCR_ISOLATE)) + result = 1; /* do restart aneg */ + } + + /* Only restart aneg if we are advertising something different + * than we were before. */ + if (result > 0) + result = genphy_restart_aneg(phydev); + + return result; +} + +/** + * genphy_update_link - update link status in @phydev + * @phydev: target phy_device struct + * + * Description: Update the value in phydev->link to reflect the + * current link value. In order to do this, we need to read + * the status register twice, keeping the second value. + */ +int genphy_update_link(struct phy_device *phydev) +{ + unsigned int mii_reg; + + /* + * Wait if the link is up, and autonegotiation is in progress + * (ie - we're capable and it's not done) + */ + mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR); + + /* + * If we already saw the link up, and it hasn't gone down, then + * we don't need to wait for autoneg again + */ + if (phydev->link && mii_reg & BMSR_LSTATUS) + return 0; + + if ((mii_reg & BMSR_ANEGCAPABLE) && !(mii_reg & BMSR_ANEGCOMPLETE)) { + int i = 0; + + printf("%s Waiting for PHY auto negotiation to complete", + phydev->dev->name); + while (!(mii_reg & BMSR_ANEGCOMPLETE)) { + /* + * Timeout reached ? + */ + if (i > PHY_ANEG_TIMEOUT) { + printf(" TIMEOUT !\n"); + phydev->link = 0; + return 0; + } + + if (ctrlc()) { + puts("user interrupt!\n"); + phydev->link = 0; + return -EINTR; + } + + if ((i++ % 500) == 0) + printf("."); + + udelay(1000); /* 1 ms */ + mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR); + } + printf(" done\n"); + phydev->link = 1; + } else { + /* Read the link a second time to clear the latched state */ + mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR); + + if (mii_reg & BMSR_LSTATUS) + phydev->link = 1; + else + phydev->link = 0; + } + + return 0; +} + +/* + * Generic function which updates the speed and duplex. If + * autonegotiation is enabled, it uses the AND of the link + * partner's advertised capabilities and our advertised + * capabilities. If autonegotiation is disabled, we use the + * appropriate bits in the control register. + * + * Stolen from Linux's mii.c and phy_device.c + */ +int genphy_parse_link(struct phy_device *phydev) +{ + int mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR); + + /* We're using autonegotiation */ + if (phydev->supported & SUPPORTED_Autoneg) { + u32 lpa = 0; + int gblpa = 0; + u32 estatus = 0; + + /* Check for gigabit capability */ + if (phydev->supported & (SUPPORTED_1000baseT_Full | + SUPPORTED_1000baseT_Half)) { + /* We want a list of states supported by + * both PHYs in the link + */ + gblpa = phy_read(phydev, MDIO_DEVAD_NONE, MII_STAT1000); + if (gblpa < 0) { + debug("Could not read MII_STAT1000. Ignoring gigabit capability\n"); + gblpa = 0; + } + gblpa &= phy_read(phydev, + MDIO_DEVAD_NONE, MII_CTRL1000) << 2; + } + + /* Set the baseline so we only have to set them + * if they're different + */ + phydev->speed = SPEED_10; + phydev->duplex = DUPLEX_HALF; + + /* Check the gigabit fields */ + if (gblpa & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) { + phydev->speed = SPEED_1000; + + if (gblpa & PHY_1000BTSR_1000FD) + phydev->duplex = DUPLEX_FULL; + + /* We're done! */ + return 0; + } + + lpa = phy_read(phydev, MDIO_DEVAD_NONE, MII_ADVERTISE); + lpa &= phy_read(phydev, MDIO_DEVAD_NONE, MII_LPA); + + if (lpa & (LPA_100FULL | LPA_100HALF)) { + phydev->speed = SPEED_100; + + if (lpa & LPA_100FULL) + phydev->duplex = DUPLEX_FULL; + + } else if (lpa & LPA_10FULL) + phydev->duplex = DUPLEX_FULL; + + /* + * Extended status may indicate that the PHY supports + * 1000BASE-T/X even though the 1000BASE-T registers + * are missing. In this case we can't tell whether the + * peer also supports it, so we only check extended + * status if the 1000BASE-T registers are actually + * missing. + */ + if ((mii_reg & BMSR_ESTATEN) && !(mii_reg & BMSR_ERCAP)) + estatus = phy_read(phydev, MDIO_DEVAD_NONE, + MII_ESTATUS); + + if (estatus & (ESTATUS_1000_XFULL | ESTATUS_1000_XHALF | + ESTATUS_1000_TFULL | ESTATUS_1000_THALF)) { + phydev->speed = SPEED_1000; + if (estatus & (ESTATUS_1000_XFULL | ESTATUS_1000_TFULL)) + phydev->duplex = DUPLEX_FULL; + } + + } else { + u32 bmcr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); + + phydev->speed = SPEED_10; + phydev->duplex = DUPLEX_HALF; + + if (bmcr & BMCR_FULLDPLX) + phydev->duplex = DUPLEX_FULL; + + if (bmcr & BMCR_SPEED1000) + phydev->speed = SPEED_1000; + else if (bmcr & BMCR_SPEED100) + phydev->speed = SPEED_100; + } + + return 0; +} + +int genphy_config(struct phy_device *phydev) +{ + int val; + u32 features; + + /* For now, I'll claim that the generic driver supports + * all possible port types */ + features = (SUPPORTED_TP | SUPPORTED_MII + | SUPPORTED_AUI | SUPPORTED_FIBRE | + SUPPORTED_BNC); + + /* Do we support autonegotiation? */ + val = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR); + + if (val < 0) + return val; + + if (val & BMSR_ANEGCAPABLE) + features |= SUPPORTED_Autoneg; + + if (val & BMSR_100FULL) + features |= SUPPORTED_100baseT_Full; + if (val & BMSR_100HALF) + features |= SUPPORTED_100baseT_Half; + if (val & BMSR_10FULL) + features |= SUPPORTED_10baseT_Full; + if (val & BMSR_10HALF) + features |= SUPPORTED_10baseT_Half; + + if (val & BMSR_ESTATEN) { + val = phy_read(phydev, MDIO_DEVAD_NONE, MII_ESTATUS); + + if (val < 0) + return val; + + if (val & ESTATUS_1000_TFULL) + features |= SUPPORTED_1000baseT_Full; + if (val & ESTATUS_1000_THALF) + features |= SUPPORTED_1000baseT_Half; + if (val & ESTATUS_1000_XFULL) + features |= SUPPORTED_1000baseX_Full; + if (val & ESTATUS_1000_XHALF) + features |= SUPPORTED_1000baseX_Half; + } + + phydev->supported = features; + phydev->advertising = features; + + genphy_config_aneg(phydev); + + return 0; +} + +int genphy_startup(struct phy_device *phydev) +{ + genphy_update_link(phydev); + genphy_parse_link(phydev); + + return 0; +} + +int genphy_shutdown(struct phy_device *phydev) +{ + return 0; +} + +static struct phy_driver genphy_driver = { + .uid = 0xffffffff, + .mask = 0xffffffff, + .name = "Generic PHY", + .features = 0, + .config = genphy_config, + .startup = genphy_startup, + .shutdown = genphy_shutdown, +}; + +static LIST_HEAD(phy_drivers); + +int phy_init(void) +{ +#ifdef CONFIG_PHY_AQUANTIA + phy_aquantia_init(); +#endif +#ifdef CONFIG_PHY_ATHEROS + phy_atheros_init(); +#endif +#ifdef CONFIG_PHY_BROADCOM + phy_broadcom_init(); +#endif +#ifdef CONFIG_PHY_CORTINA + phy_cortina_init(); +#endif +#ifdef CONFIG_PHY_DAVICOM + phy_davicom_init(); +#endif +#ifdef CONFIG_PHY_ET1011C + phy_et1011c_init(); +#endif +#ifdef CONFIG_PHY_LXT + phy_lxt_init(); +#endif +#ifdef CONFIG_PHY_MARVELL + phy_marvell_init(); +#endif +#ifdef CONFIG_PHY_MICREL + phy_micrel_init(); +#endif +#ifdef CONFIG_PHY_NATSEMI + phy_natsemi_init(); +#endif +#ifdef CONFIG_PHY_REALTEK + phy_realtek_init(); +#endif +#ifdef CONFIG_PHY_SMSC + phy_smsc_init(); +#endif +#ifdef CONFIG_PHY_TERANETICS + phy_teranetics_init(); +#endif +#ifdef CONFIG_PHY_TI + phy_ti_init(); +#endif +#ifdef CONFIG_PHY_VITESSE + phy_vitesse_init(); +#endif + + return 0; +} + +int phy_register(struct phy_driver *drv) +{ + INIT_LIST_HEAD(&drv->list); + list_add_tail(&drv->list, &phy_drivers); + +#ifdef CONFIG_NEEDS_MANUAL_RELOC + if (drv->probe) + drv->probe += gd->reloc_off; + if (drv->config) + drv->config += gd->reloc_off; + if (drv->startup) + drv->startup += gd->reloc_off; + if (drv->shutdown) + drv->shutdown += gd->reloc_off; + if (drv->readext) + drv->readext += gd->reloc_off; + if (drv->writeext) + drv->writeext += gd->reloc_off; +#endif + return 0; +} + +static int phy_probe(struct phy_device *phydev) +{ + int err = 0; + + phydev->advertising = phydev->supported = phydev->drv->features; + phydev->mmds = phydev->drv->mmds; + + if (phydev->drv->probe) + err = phydev->drv->probe(phydev); + + return err; +} + +static struct phy_driver *generic_for_interface(phy_interface_t interface) +{ +#ifdef CONFIG_PHYLIB_10G + if (is_10g_interface(interface)) + return &gen10g_driver; +#endif + + return &genphy_driver; +} + +static struct phy_driver *get_phy_driver(struct phy_device *phydev, + phy_interface_t interface) +{ + struct list_head *entry; + int phy_id = phydev->phy_id; + struct phy_driver *drv = NULL; + + list_for_each(entry, &phy_drivers) { + drv = list_entry(entry, struct phy_driver, list); + if ((drv->uid & drv->mask) == (phy_id & drv->mask)) + return drv; + } + + /* If we made it here, there's no driver for this PHY */ + return generic_for_interface(interface); +} + +static struct phy_device *phy_device_create(struct mii_dev *bus, int addr, + u32 phy_id, + phy_interface_t interface) +{ + struct phy_device *dev; + + /* We allocate the device, and initialize the + * default values */ + dev = malloc(sizeof(*dev)); + if (!dev) { + printf("Failed to allocate PHY device for %s:%d\n", + bus->name, addr); + return NULL; + } + + memset(dev, 0, sizeof(*dev)); + + dev->duplex = -1; + dev->link = 0; + dev->interface = interface; + + dev->autoneg = AUTONEG_ENABLE; + + dev->addr = addr; + dev->phy_id = phy_id; + dev->bus = bus; + + dev->drv = get_phy_driver(dev, interface); + + phy_probe(dev); + + bus->phymap[addr] = dev; + + return dev; +} + +/** + * get_phy_id - reads the specified addr for its ID. + * @bus: the target MII bus + * @addr: PHY address on the MII bus + * @phy_id: where to store the ID retrieved. + * + * Description: Reads the ID registers of the PHY at @addr on the + * @bus, stores it in @phy_id and returns zero on success. + */ +int __weak get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id) +{ + int phy_reg; + + /* Grab the bits from PHYIR1, and put them + * in the upper half */ + phy_reg = bus->read(bus, addr, devad, MII_PHYSID1); + + if (phy_reg < 0) + return -EIO; + + *phy_id = (phy_reg & 0xffff) << 16; + + /* Grab the bits from PHYIR2, and put them in the lower half */ + phy_reg = bus->read(bus, addr, devad, MII_PHYSID2); + + if (phy_reg < 0) + return -EIO; + + *phy_id |= (phy_reg & 0xffff); + + return 0; +} + +static struct phy_device *create_phy_by_mask(struct mii_dev *bus, + unsigned phy_mask, int devad, phy_interface_t interface) +{ + u32 phy_id = 0xffffffff; + while (phy_mask) { + int addr = ffs(phy_mask) - 1; + int r = get_phy_id(bus, addr, devad, &phy_id); + /* If the PHY ID is mostly f's, we didn't find anything */ + if (r == 0 && (phy_id & 0x1fffffff) != 0x1fffffff) + return phy_device_create(bus, addr, phy_id, interface); + phy_mask &= ~(1 << addr); + } + return NULL; +} + +static struct phy_device *search_for_existing_phy(struct mii_dev *bus, + unsigned phy_mask, phy_interface_t interface) +{ + /* If we have one, return the existing device, with new interface */ + while (phy_mask) { + int addr = ffs(phy_mask) - 1; + if (bus->phymap[addr]) { + bus->phymap[addr]->interface = interface; + return bus->phymap[addr]; + } + phy_mask &= ~(1 << addr); + } + return NULL; +} + +static struct phy_device *get_phy_device_by_mask(struct mii_dev *bus, + unsigned phy_mask, phy_interface_t interface) +{ + int i; + struct phy_device *phydev; + + phydev = search_for_existing_phy(bus, phy_mask, interface); + if (phydev) + return phydev; + /* Try Standard (ie Clause 22) access */ + /* Otherwise we have to try Clause 45 */ + for (i = 0; i < 5; i++) { + phydev = create_phy_by_mask(bus, phy_mask, + i ? i : MDIO_DEVAD_NONE, interface); + if (IS_ERR(phydev)) + return NULL; + if (phydev) + return phydev; + } + + debug("\n%s PHY: ", bus->name); + while (phy_mask) { + int addr = ffs(phy_mask) - 1; + debug("%d ", addr); + phy_mask &= ~(1 << addr); + } + debug("not found\n"); + + return NULL; +} + +/** + * get_phy_device - reads the specified PHY device and returns its @phy_device struct + * @bus: the target MII bus + * @addr: PHY address on the MII bus + * + * Description: Reads the ID registers of the PHY at @addr on the + * @bus, then allocates and returns the phy_device to represent it. + */ +static struct phy_device *get_phy_device(struct mii_dev *bus, int addr, + phy_interface_t interface) +{ + return get_phy_device_by_mask(bus, 1 << addr, interface); +} + +int phy_reset(struct phy_device *phydev) +{ + int reg; + int timeout = 500; + int devad = MDIO_DEVAD_NONE; + +#ifdef CONFIG_PHYLIB_10G + /* If it's 10G, we need to issue reset through one of the MMDs */ + if (is_10g_interface(phydev->interface)) { + if (!phydev->mmds) + gen10g_discover_mmds(phydev); + + devad = ffs(phydev->mmds) - 1; + } +#endif + + reg = phy_read(phydev, devad, MII_BMCR); + if (reg < 0) { + debug("PHY status read failed\n"); + return -1; + } + + reg |= BMCR_RESET; + + if (phy_write(phydev, devad, MII_BMCR, reg) < 0) { + debug("PHY reset failed\n"); + return -1; + } + +#ifdef CONFIG_PHY_RESET_DELAY + udelay(CONFIG_PHY_RESET_DELAY); /* Intel LXT971A needs this */ +#endif + /* + * Poll the control register for the reset bit to go to 0 (it is + * auto-clearing). This should happen within 0.5 seconds per the + * IEEE spec. + */ + while ((reg & BMCR_RESET) && timeout--) { + reg = phy_read(phydev, devad, MII_BMCR); + + if (reg < 0) { + debug("PHY status read failed\n"); + return -1; + } + udelay(1000); + } + + if (reg & BMCR_RESET) { + puts("PHY reset timed out\n"); + return -1; + } + + return 0; +} + +int miiphy_reset(const char *devname, unsigned char addr) +{ + struct mii_dev *bus = miiphy_get_dev_by_name(devname); + struct phy_device *phydev; + + /* + * miiphy_reset was only used on standard PHYs, so we'll fake it here. + * If later code tries to connect with the right interface, this will + * be corrected by get_phy_device in phy_connect() + */ + phydev = get_phy_device(bus, addr, PHY_INTERFACE_MODE_MII); + + return phy_reset(phydev); +} + +struct phy_device *phy_find_by_mask(struct mii_dev *bus, unsigned phy_mask, + phy_interface_t interface) +{ + /* Reset the bus */ + if (bus->reset) { + bus->reset(bus); + + /* Wait 15ms to make sure the PHY has come out of hard reset */ + udelay(15000); + } + + return get_phy_device_by_mask(bus, phy_mask, interface); +} + +#ifdef CONFIG_DM_ETH +void phy_connect_dev(struct phy_device *phydev, struct udevice *dev) +#else +void phy_connect_dev(struct phy_device *phydev, struct eth_device *dev) +#endif +{ + /* Soft Reset the PHY */ + phy_reset(phydev); + if (phydev->dev && phydev->dev != dev) { + printf("%s:%d is connected to %s. Reconnecting to %s\n", + phydev->bus->name, phydev->addr, + phydev->dev->name, dev->name); + } + phydev->dev = dev; + debug("%s connected to %s\n", dev->name, phydev->drv->name); +} + +#ifdef CONFIG_DM_ETH +struct phy_device *phy_connect(struct mii_dev *bus, int addr, + struct udevice *dev, phy_interface_t interface) +#else +struct phy_device *phy_connect(struct mii_dev *bus, int addr, + struct eth_device *dev, phy_interface_t interface) +#endif +{ + struct phy_device *phydev; + + phydev = phy_find_by_mask(bus, 1 << addr, interface); + if (phydev) + phy_connect_dev(phydev, dev); + else + printf("Could not get PHY for %s: addr %d\n", bus->name, addr); + return phydev; +} + +/* + * Start the PHY. Returns 0 on success, or a negative error code. + */ +int phy_startup(struct phy_device *phydev) +{ + if (phydev->drv->startup) + return phydev->drv->startup(phydev); + + return 0; +} + +__weak int board_phy_config(struct phy_device *phydev) +{ + if (phydev->drv->config) + return phydev->drv->config(phydev); + return 0; +} + +int phy_config(struct phy_device *phydev) +{ + /* Invoke an optional board-specific helper */ + board_phy_config(phydev); + + return 0; +} + +int phy_shutdown(struct phy_device *phydev) +{ + if (phydev->drv->shutdown) + phydev->drv->shutdown(phydev); + + return 0; +} + +int phy_get_interface_by_name(const char *str) +{ + int i; + + for (i = 0; i < PHY_INTERFACE_MODE_COUNT; i++) { + if (!strcmp(str, phy_interface_strings[i])) + return i; + } + + return -1; +} diff --git a/sources/uboot-be550/drivers/net/phy/realtek.c b/sources/uboot-be550/drivers/net/phy/realtek.c new file mode 100644 index 00000000..bba48da4 --- /dev/null +++ b/sources/uboot-be550/drivers/net/phy/realtek.c @@ -0,0 +1,267 @@ +/* + * RealTek PHY drivers + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Copyright 2010-2011, 2015 Freescale Semiconductor, Inc. + * author Andy Fleming + */ +#include +#include +#include + +#define PHY_AUTONEGOTIATE_TIMEOUT 5000 + +/* RTL8211x PHY Status Register */ +#define MIIM_RTL8211x_PHY_STATUS 0x11 +#define MIIM_RTL8211x_PHYSTAT_SPEED 0xc000 +#define MIIM_RTL8211x_PHYSTAT_GBIT 0x8000 +#define MIIM_RTL8211x_PHYSTAT_100 0x4000 +#define MIIM_RTL8211x_PHYSTAT_DUPLEX 0x2000 +#define MIIM_RTL8211x_PHYSTAT_SPDDONE 0x0800 +#define MIIM_RTL8211x_PHYSTAT_LINK 0x0400 + +/* RTL8211x PHY Interrupt Enable Register */ +#define MIIM_RTL8211x_PHY_INER 0x12 +#define MIIM_RTL8211x_PHY_INTR_ENA 0x9f01 +#define MIIM_RTL8211x_PHY_INTR_DIS 0x0000 + +/* RTL8211x PHY Interrupt Status Register */ +#define MIIM_RTL8211x_PHY_INSR 0x13 + +/* RTL8211F PHY Status Register */ +#define MIIM_RTL8211F_PHY_STATUS 0x1a +#define MIIM_RTL8211F_AUTONEG_ENABLE 0x1000 +#define MIIM_RTL8211F_PHYSTAT_SPEED 0x0030 +#define MIIM_RTL8211F_PHYSTAT_GBIT 0x0020 +#define MIIM_RTL8211F_PHYSTAT_100 0x0010 +#define MIIM_RTL8211F_PHYSTAT_DUPLEX 0x0008 +#define MIIM_RTL8211F_PHYSTAT_SPDDONE 0x0800 +#define MIIM_RTL8211F_PHYSTAT_LINK 0x0004 + +#define MIIM_RTL8211F_PAGE_SELECT 0x1f +#define MIIM_RTL8211F_TX_DELAY 0x100 +#define MIIM_RTL8211F_LCR 0x10 + +/* RealTek RTL8211x */ +static int rtl8211x_config(struct phy_device *phydev) +{ + phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); + + /* mask interrupt at init; if the interrupt is + * needed indeed, it should be explicitly enabled + */ + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_INER, + MIIM_RTL8211x_PHY_INTR_DIS); + + /* read interrupt status just to clear it */ + phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_INER); + + genphy_config_aneg(phydev); + + return 0; +} + +static int rtl8211f_config(struct phy_device *phydev) +{ + u16 reg; + + phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); + + if (phydev->interface == PHY_INTERFACE_MODE_RGMII) { + /* enable TXDLY */ + phy_write(phydev, MDIO_DEVAD_NONE, + MIIM_RTL8211F_PAGE_SELECT, 0xd08); + reg = phy_read(phydev, MDIO_DEVAD_NONE, 0x11); + reg |= MIIM_RTL8211F_TX_DELAY; + phy_write(phydev, MDIO_DEVAD_NONE, 0x11, reg); + /* restore to default page 0 */ + phy_write(phydev, MDIO_DEVAD_NONE, + MIIM_RTL8211F_PAGE_SELECT, 0x0); + } + + /* Set green LED for Link, yellow LED for Active */ + phy_write(phydev, MDIO_DEVAD_NONE, + MIIM_RTL8211F_PAGE_SELECT, 0xd04); + phy_write(phydev, MDIO_DEVAD_NONE, 0x10, 0x617f); + phy_write(phydev, MDIO_DEVAD_NONE, + MIIM_RTL8211F_PAGE_SELECT, 0x0); + + genphy_config_aneg(phydev); + + return 0; +} + +static int rtl8211x_parse_status(struct phy_device *phydev) +{ + unsigned int speed; + unsigned int mii_reg; + + mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_STATUS); + + if (!(mii_reg & MIIM_RTL8211x_PHYSTAT_SPDDONE)) { + int i = 0; + + /* in case of timeout ->link is cleared */ + phydev->link = 1; + puts("Waiting for PHY realtime link"); + while (!(mii_reg & MIIM_RTL8211x_PHYSTAT_SPDDONE)) { + /* Timeout reached ? */ + if (i > PHY_AUTONEGOTIATE_TIMEOUT) { + puts(" TIMEOUT !\n"); + phydev->link = 0; + break; + } + + if ((i++ % 1000) == 0) + putc('.'); + udelay(1000); /* 1 ms */ + mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, + MIIM_RTL8211x_PHY_STATUS); + } + puts(" done\n"); + udelay(500000); /* another 500 ms (results in faster booting) */ + } else { + if (mii_reg & MIIM_RTL8211x_PHYSTAT_LINK) + phydev->link = 1; + else + phydev->link = 0; + } + + if (mii_reg & MIIM_RTL8211x_PHYSTAT_DUPLEX) + phydev->duplex = DUPLEX_FULL; + else + phydev->duplex = DUPLEX_HALF; + + speed = (mii_reg & MIIM_RTL8211x_PHYSTAT_SPEED); + + switch (speed) { + case MIIM_RTL8211x_PHYSTAT_GBIT: + phydev->speed = SPEED_1000; + break; + case MIIM_RTL8211x_PHYSTAT_100: + phydev->speed = SPEED_100; + break; + default: + phydev->speed = SPEED_10; + } + + return 0; +} + +static int rtl8211f_parse_status(struct phy_device *phydev) +{ + unsigned int speed; + unsigned int mii_reg; + int i = 0; + + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, 0xa43); + mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PHY_STATUS); + + phydev->link = 1; + while (!(mii_reg & MIIM_RTL8211F_PHYSTAT_LINK)) { + if (i > PHY_AUTONEGOTIATE_TIMEOUT) { + puts(" TIMEOUT !\n"); + phydev->link = 0; + break; + } + + if ((i++ % 1000) == 0) + putc('.'); + udelay(1000); + mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, + MIIM_RTL8211F_PHY_STATUS); + } + + if (mii_reg & MIIM_RTL8211F_PHYSTAT_DUPLEX) + phydev->duplex = DUPLEX_FULL; + else + phydev->duplex = DUPLEX_HALF; + + speed = (mii_reg & MIIM_RTL8211F_PHYSTAT_SPEED); + + switch (speed) { + case MIIM_RTL8211F_PHYSTAT_GBIT: + phydev->speed = SPEED_1000; + break; + case MIIM_RTL8211F_PHYSTAT_100: + phydev->speed = SPEED_100; + break; + default: + phydev->speed = SPEED_10; + } + + return 0; +} + +static int rtl8211x_startup(struct phy_device *phydev) +{ + /* Read the Status (2x to make sure link is right) */ + genphy_update_link(phydev); + rtl8211x_parse_status(phydev); + + return 0; +} + +static int rtl8211f_startup(struct phy_device *phydev) +{ + /* Read the Status (2x to make sure link is right) */ + genphy_update_link(phydev); + rtl8211f_parse_status(phydev); + + return 0; +} + +/* Support for RTL8211B PHY */ +static struct phy_driver RTL8211B_driver = { + .name = "RealTek RTL8211B", + .uid = 0x1cc910, + .mask = 0xffffff, + .features = PHY_GBIT_FEATURES, + .config = &rtl8211x_config, + .startup = &rtl8211x_startup, + .shutdown = &genphy_shutdown, +}; + +/* Support for RTL8211E-VB-CG, RTL8211E-VL-CG and RTL8211EG-VB-CG PHYs */ +static struct phy_driver RTL8211E_driver = { + .name = "RealTek RTL8211E", + .uid = 0x1cc915, + .mask = 0xffffff, + .features = PHY_GBIT_FEATURES, + .config = &rtl8211x_config, + .startup = &rtl8211x_startup, + .shutdown = &genphy_shutdown, +}; + +/* Support for RTL8211DN PHY */ +static struct phy_driver RTL8211DN_driver = { + .name = "RealTek RTL8211DN", + .uid = 0x1cc914, + .mask = 0xffffff, + .features = PHY_GBIT_FEATURES, + .config = &rtl8211x_config, + .startup = &rtl8211x_startup, + .shutdown = &genphy_shutdown, +}; + +/* Support for RTL8211F PHY */ +static struct phy_driver RTL8211F_driver = { + .name = "RealTek RTL8211F", + .uid = 0x1cc916, + .mask = 0xffffff, + .features = PHY_GBIT_FEATURES, + .config = &rtl8211f_config, + .startup = &rtl8211f_startup, + .shutdown = &genphy_shutdown, +}; + +int phy_realtek_init(void) +{ + phy_register(&RTL8211B_driver); + phy_register(&RTL8211E_driver); + phy_register(&RTL8211F_driver); + phy_register(&RTL8211DN_driver); + + return 0; +} diff --git a/sources/uboot-be550/drivers/net/phy/smsc.c b/sources/uboot-be550/drivers/net/phy/smsc.c new file mode 100644 index 00000000..bfd9815a --- /dev/null +++ b/sources/uboot-be550/drivers/net/phy/smsc.c @@ -0,0 +1,79 @@ +/* + * SMSC PHY drivers + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Base code from drivers/net/phy/davicom.c + * Copyright 2010-2011 Freescale Semiconductor, Inc. + * author Andy Fleming + * + * Some code copied from linux kernel + * Copyright (c) 2006 Herbert Valerio Riedel + */ +#include + +/* This code does not check the partner abilities. */ +static int smsc_parse_status(struct phy_device *phydev) +{ + int mii_reg; + + mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR); + + if (mii_reg & (BMSR_100FULL | BMSR_100HALF)) + phydev->speed = SPEED_100; + else + phydev->speed = SPEED_10; + + if (mii_reg & (BMSR_10FULL | BMSR_100FULL)) + phydev->duplex = DUPLEX_FULL; + else + phydev->duplex = DUPLEX_HALF; + + return 0; +} + +static int smsc_startup(struct phy_device *phydev) +{ + genphy_update_link(phydev); + smsc_parse_status(phydev); + return 0; +} + +static struct phy_driver lan8700_driver = { + .name = "SMSC LAN8700", + .uid = 0x0007c0c0, + .mask = 0xffff0, + .features = PHY_BASIC_FEATURES, + .config = &genphy_config_aneg, + .startup = &smsc_startup, + .shutdown = &genphy_shutdown, +}; + +static struct phy_driver lan911x_driver = { + .name = "SMSC LAN911x Internal PHY", + .uid = 0x0007c0d0, + .mask = 0xffff0, + .features = PHY_BASIC_FEATURES, + .config = &genphy_config_aneg, + .startup = &smsc_startup, + .shutdown = &genphy_shutdown, +}; + +static struct phy_driver lan8710_driver = { + .name = "SMSC LAN8710/LAN8720", + .uid = 0x0007c0f0, + .mask = 0xffff0, + .features = PHY_BASIC_FEATURES, + .config = &genphy_config_aneg, + .startup = &genphy_startup, + .shutdown = &genphy_shutdown, +}; + +int phy_smsc_init(void) +{ + phy_register(&lan8710_driver); + phy_register(&lan911x_driver); + phy_register(&lan8700_driver); + + return 0; +} diff --git a/sources/uboot-be550/drivers/net/phy/teranetics.c b/sources/uboot-be550/drivers/net/phy/teranetics.c new file mode 100644 index 00000000..93d5ac3d --- /dev/null +++ b/sources/uboot-be550/drivers/net/phy/teranetics.c @@ -0,0 +1,112 @@ +/* + * Teranetics PHY drivers + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Copyright 2010-2011 Freescale Semiconductor, Inc. + * author Andy Fleming + */ +#include +#include +#include + +#ifndef CONFIG_PHYLIB_10G +#error The Teranetics PHY needs 10G support +#endif + +int tn2020_config(struct phy_device *phydev) +{ + if (phydev->port == PORT_FIBRE) { + unsigned short restart_an = (MDIO_AN_CTRL1_RESTART | + MDIO_AN_CTRL1_ENABLE | + MDIO_AN_CTRL1_XNP); + u8 phy_hwversion; + + /* + * bit 15:12 of register 30.32 indicates PHY hardware + * version. It can be used to distinguish TN80xx from + * TN2020. TN2020 needs write 0x2 to 30.93, but TN80xx + * needs 0x1. + */ + phy_hwversion = (phy_read(phydev, 30, 32) >> 12) & 0xf; + if (phy_hwversion <= 3) { + phy_write(phydev, 30, 93, 2); + phy_write(phydev, MDIO_MMD_AN, MDIO_CTRL1, restart_an); + } else { + phy_write(phydev, 30, 93, 1); + } + } + + return 0; +} + +int tn2020_startup(struct phy_device *phydev) +{ + unsigned int timeout = 5 * 1000; /* 5 second timeout */ + +#define MDIO_PHYXS_LANE_READY (MDIO_PHYXS_LNSTAT_SYNC0 | \ + MDIO_PHYXS_LNSTAT_SYNC1 | \ + MDIO_PHYXS_LNSTAT_SYNC2 | \ + MDIO_PHYXS_LNSTAT_SYNC3 | \ + MDIO_PHYXS_LNSTAT_ALIGN) + + /* + * Wait for the XAUI-SERDES lanes to align first. Under normal + * circumstances, this can take up to three seconds. + */ + while (--timeout) { + int reg = phy_read(phydev, MDIO_MMD_PHYXS, MDIO_PHYXS_LNSTAT); + if (reg < 0) { + printf("TN2020: Error reading from PHY at " + "address %u\n", phydev->addr); + break; + } + if ((reg & MDIO_PHYXS_LANE_READY) == MDIO_PHYXS_LANE_READY) + break; + udelay(1000); + } + if (!timeout) { + /* + * A timeout is bad, but it may not be fatal, so don't + * return an error. Display a warning instead. + */ + printf("TN2020: Timeout waiting for PHY at address %u to " + "align.\n", phydev->addr); + } + + if (phydev->port != PORT_FIBRE) + return gen10g_startup(phydev); + + /* + * The TN2020 only pretends to support fiber. + * It works, but it doesn't look like it works, + * so the link status reports no link. + */ + phydev->link = 1; + + /* For now just lie and say it's 10G all the time */ + phydev->speed = SPEED_10000; + phydev->duplex = DUPLEX_FULL; + + return 0; +} + +struct phy_driver tn2020_driver = { + .name = "Teranetics TN2020", + .uid = PHY_UID_TN2020, + .mask = 0xfffffff0, + .features = PHY_10G_FEATURES, + .mmds = (MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS | + MDIO_DEVS_PHYXS | MDIO_DEVS_AN | + MDIO_DEVS_VEND1 | MDIO_DEVS_VEND2), + .config = &tn2020_config, + .startup = &tn2020_startup, + .shutdown = &gen10g_shutdown, +}; + +int phy_teranetics_init(void) +{ + phy_register(&tn2020_driver); + + return 0; +} diff --git a/sources/uboot-be550/drivers/net/phy/ti.c b/sources/uboot-be550/drivers/net/phy/ti.c new file mode 100644 index 00000000..541a57f9 --- /dev/null +++ b/sources/uboot-be550/drivers/net/phy/ti.c @@ -0,0 +1,200 @@ +/* + * TI PHY drivers + * + * SPDX-License-Identifier: GPL-2.0 + * + */ +#include +#include + +/* TI DP83867 */ +#define DP83867_DEVADDR 0x1f + +#define MII_DP83867_PHYCTRL 0x10 +#define MII_DP83867_MICR 0x12 +#define DP83867_CTRL 0x1f + +/* Extended Registers */ +#define DP83867_RGMIICTL 0x0032 +#define DP83867_RGMIIDCTL 0x0086 + +#define DP83867_SW_RESET BIT(15) +#define DP83867_SW_RESTART BIT(14) + +/* MICR Interrupt bits */ +#define MII_DP83867_MICR_AN_ERR_INT_EN BIT(15) +#define MII_DP83867_MICR_SPEED_CHNG_INT_EN BIT(14) +#define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN BIT(13) +#define MII_DP83867_MICR_PAGE_RXD_INT_EN BIT(12) +#define MII_DP83867_MICR_AUTONEG_COMP_INT_EN BIT(11) +#define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN BIT(10) +#define MII_DP83867_MICR_FALSE_CARRIER_INT_EN BIT(8) +#define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4) +#define MII_DP83867_MICR_WOL_INT_EN BIT(3) +#define MII_DP83867_MICR_XGMII_ERR_INT_EN BIT(2) +#define MII_DP83867_MICR_POL_CHNG_INT_EN BIT(1) +#define MII_DP83867_MICR_JABBER_INT_EN BIT(0) + +/* RGMIICTL bits */ +#define DP83867_RGMII_TX_CLK_DELAY_EN BIT(1) +#define DP83867_RGMII_RX_CLK_DELAY_EN BIT(0) + +/* PHY CTRL bits */ +#define DP83867_PHYCR_FIFO_DEPTH_SHIFT 14 + +/* RGMIIDCTL bits */ +#define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4 + +#define MII_MMD_CTRL 0x0d /* MMD Access Control Register */ +#define MII_MMD_DATA 0x0e /* MMD Access Data Register */ + +/* MMD Access Control register fields */ +#define MII_MMD_CTRL_DEVAD_MASK 0x1f /* Mask MMD DEVAD*/ +#define MII_MMD_CTRL_ADDR 0x0000 /* Address */ +#define MII_MMD_CTRL_NOINCR 0x4000 /* no post increment */ +#define MII_MMD_CTRL_INCR_RDWT 0x8000 /* post increment on reads & writes */ +#define MII_MMD_CTRL_INCR_ON_WT 0xC000 /* post increment on writes only */ + +/** + * phy_read_mmd_indirect - reads data from the MMD registers + * @phydev: The PHY device bus + * @prtad: MMD Address + * @devad: MMD DEVAD + * @addr: PHY address on the MII bus + * + * Description: it reads data from the MMD registers (clause 22 to access to + * clause 45) of the specified phy address. + * To read these registers we have: + * 1) Write reg 13 // DEVAD + * 2) Write reg 14 // MMD Address + * 3) Write reg 13 // MMD Data Command for MMD DEVAD + * 3) Read reg 14 // Read MMD data + */ +int phy_read_mmd_indirect(struct phy_device *phydev, int prtad, + int devad, int addr) +{ + int value = -1; + + /* Write the desired MMD Devad */ + phy_write(phydev, addr, MII_MMD_CTRL, devad); + + /* Write the desired MMD register address */ + phy_write(phydev, addr, MII_MMD_DATA, prtad); + + /* Select the Function : DATA with no post increment */ + phy_write(phydev, addr, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); + + /* Read the content of the MMD's selected register */ + value = phy_read(phydev, addr, MII_MMD_DATA); + return value; +} + +/** + * phy_write_mmd_indirect - writes data to the MMD registers + * @phydev: The PHY device + * @prtad: MMD Address + * @devad: MMD DEVAD + * @addr: PHY address on the MII bus + * @data: data to write in the MMD register + * + * Description: Write data from the MMD registers of the specified + * phy address. + * To write these registers we have: + * 1) Write reg 13 // DEVAD + * 2) Write reg 14 // MMD Address + * 3) Write reg 13 // MMD Data Command for MMD DEVAD + * 3) Write reg 14 // Write MMD data + */ +void phy_write_mmd_indirect(struct phy_device *phydev, int prtad, + int devad, int addr, u32 data) +{ + /* Write the desired MMD Devad */ + phy_write(phydev, addr, MII_MMD_CTRL, devad); + + /* Write the desired MMD register address */ + phy_write(phydev, addr, MII_MMD_DATA, prtad); + + /* Select the Function : DATA with no post increment */ + phy_write(phydev, addr, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); + + /* Write the data into MMD's selected register */ + phy_write(phydev, addr, MII_MMD_DATA, data); +} + +/** + * phy_interface_is_rgmii - Convenience function for testing if a PHY interface + * is RGMII (all variants) + * @phydev: the phy_device struct + */ +static inline bool phy_interface_is_rgmii(struct phy_device *phydev) +{ + return phydev->interface >= PHY_INTERFACE_MODE_RGMII && + phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID; +} + +/* User setting - can be taken from DTS */ +#define RX_ID_DELAY 8 +#define TX_ID_DELAY 0xa +#define FIFO_DEPTH 1 + +static int dp83867_config(struct phy_device *phydev) +{ + unsigned int val, delay; + int ret; + + /* Restart the PHY. */ + val = phy_read(phydev, MDIO_DEVAD_NONE, DP83867_CTRL); + phy_write(phydev, MDIO_DEVAD_NONE, DP83867_CTRL, + val | DP83867_SW_RESTART); + + if (phy_interface_is_rgmii(phydev)) { + ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL, + (FIFO_DEPTH << DP83867_PHYCR_FIFO_DEPTH_SHIFT)); + if (ret) + return ret; + } + + if ((phydev->interface >= PHY_INTERFACE_MODE_RGMII_ID) && + (phydev->interface <= PHY_INTERFACE_MODE_RGMII_RXID)) { + val = phy_read_mmd_indirect(phydev, DP83867_RGMIICTL, + DP83867_DEVADDR, phydev->addr); + + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) + val |= (DP83867_RGMII_TX_CLK_DELAY_EN | + DP83867_RGMII_RX_CLK_DELAY_EN); + + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) + val |= DP83867_RGMII_TX_CLK_DELAY_EN; + + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) + val |= DP83867_RGMII_RX_CLK_DELAY_EN; + + phy_write_mmd_indirect(phydev, DP83867_RGMIICTL, + DP83867_DEVADDR, phydev->addr, val); + + delay = (RX_ID_DELAY | + (TX_ID_DELAY << DP83867_RGMII_TX_CLK_DELAY_SHIFT)); + + phy_write_mmd_indirect(phydev, DP83867_RGMIIDCTL, + DP83867_DEVADDR, phydev->addr, delay); + } + + genphy_config_aneg(phydev); + return 0; +} + +static struct phy_driver DP83867_driver = { + .name = "TI DP83867", + .uid = 0x2000a231, + .mask = 0xfffffff0, + .features = PHY_GBIT_FEATURES, + .config = &dp83867_config, + .startup = &genphy_startup, + .shutdown = &genphy_shutdown, +}; + +int phy_ti_init(void) +{ + phy_register(&DP83867_driver); + return 0; +} diff --git a/sources/uboot-be550/drivers/net/phy/vitesse.c b/sources/uboot-be550/drivers/net/phy/vitesse.c new file mode 100644 index 00000000..941d0760 --- /dev/null +++ b/sources/uboot-be550/drivers/net/phy/vitesse.c @@ -0,0 +1,438 @@ +/* + * Vitesse PHY drivers + * + * Copyright 2010-2014 Freescale Semiconductor, Inc. + * Original Author: Andy Fleming + * Add vsc8662 phy support - Priyanka Jain + * SPDX-License-Identifier: GPL-2.0+ + */ +#include + +/* Cicada Auxiliary Control/Status Register */ +#define MIIM_CIS82xx_AUX_CONSTAT 0x1c +#define MIIM_CIS82xx_AUXCONSTAT_INIT 0x0004 +#define MIIM_CIS82xx_AUXCONSTAT_DUPLEX 0x0020 +#define MIIM_CIS82xx_AUXCONSTAT_SPEED 0x0018 +#define MIIM_CIS82xx_AUXCONSTAT_GBIT 0x0010 +#define MIIM_CIS82xx_AUXCONSTAT_100 0x0008 + +/* Cicada Extended Control Register 1 */ +#define MIIM_CIS82xx_EXT_CON1 0x17 +#define MIIM_CIS8201_EXTCON1_INIT 0x0000 + +/* Cicada 8204 Extended PHY Control Register 1 */ +#define MIIM_CIS8204_EPHY_CON 0x17 +#define MIIM_CIS8204_EPHYCON_INIT 0x0006 +#define MIIM_CIS8204_EPHYCON_RGMII 0x1100 + +/* Cicada 8204 Serial LED Control Register */ +#define MIIM_CIS8204_SLED_CON 0x1b +#define MIIM_CIS8204_SLEDCON_INIT 0x1115 + +/* Vitesse VSC8601 Extended PHY Control Register 1 */ +#define MIIM_VSC8601_EPHY_CON 0x17 +#define MIIM_VSC8601_EPHY_CON_INIT_SKEW 0x1120 +#define MIIM_VSC8601_SKEW_CTRL 0x1c + +#define PHY_EXT_PAGE_ACCESS 0x1f +#define PHY_EXT_PAGE_ACCESS_GENERAL 0x10 +#define PHY_EXT_PAGE_ACCESS_EXTENDED3 0x3 + +/* Vitesse VSC8574 control register */ +#define MIIM_VSC8574_MAC_SERDES_CON 0x10 +#define MIIM_VSC8574_MAC_SERDES_ANEG 0x80 +#define MIIM_VSC8574_GENERAL18 0x12 +#define MIIM_VSC8574_GENERAL19 0x13 + +/* Vitesse VSC8574 gerenal purpose register 18 */ +#define MIIM_VSC8574_18G_SGMII 0x80f0 +#define MIIM_VSC8574_18G_QSGMII 0x80e0 +#define MIIM_VSC8574_18G_CMDSTAT 0x8000 + +/* Vitesse VSC8514 control register */ +#define MIIM_VSC8514_MAC_SERDES_CON 0x10 +#define MIIM_VSC8514_GENERAL18 0x12 +#define MIIM_VSC8514_GENERAL19 0x13 +#define MIIM_VSC8514_GENERAL23 0x17 + +/* Vitesse VSC8514 gerenal purpose register 18 */ +#define MIIM_VSC8514_18G_QSGMII 0x80e0 +#define MIIM_VSC8514_18G_CMDSTAT 0x8000 + +/* Vitesse VSC8664 Control/Status Register */ +#define MIIM_VSC8664_SERDES_AND_SIGDET 0x13 +#define MIIM_VSC8664_ADDITIONAL_DEV 0x16 +#define MIIM_VSC8664_EPHY_CON 0x17 +#define MIIM_VSC8664_LED_CON 0x1E + +#define PHY_EXT_PAGE_ACCESS_EXTENDED 0x0001 + +/* CIS8201 */ +static int vitesse_config(struct phy_device *phydev) +{ + /* Override PHY config settings */ + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS82xx_AUX_CONSTAT, + MIIM_CIS82xx_AUXCONSTAT_INIT); + /* Set up the interface mode */ + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS82xx_EXT_CON1, + MIIM_CIS8201_EXTCON1_INIT); + + genphy_config_aneg(phydev); + + return 0; +} + +static int vitesse_parse_status(struct phy_device *phydev) +{ + int speed; + int mii_reg; + + mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_CIS82xx_AUX_CONSTAT); + + if (mii_reg & MIIM_CIS82xx_AUXCONSTAT_DUPLEX) + phydev->duplex = DUPLEX_FULL; + else + phydev->duplex = DUPLEX_HALF; + + speed = mii_reg & MIIM_CIS82xx_AUXCONSTAT_SPEED; + switch (speed) { + case MIIM_CIS82xx_AUXCONSTAT_GBIT: + phydev->speed = SPEED_1000; + break; + case MIIM_CIS82xx_AUXCONSTAT_100: + phydev->speed = SPEED_100; + break; + default: + phydev->speed = SPEED_10; + break; + } + + return 0; +} + +static int vitesse_startup(struct phy_device *phydev) +{ + genphy_update_link(phydev); + vitesse_parse_status(phydev); + + return 0; +} + +static int cis8204_config(struct phy_device *phydev) +{ + /* Override PHY config settings */ + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS82xx_AUX_CONSTAT, + MIIM_CIS82xx_AUXCONSTAT_INIT); + + genphy_config_aneg(phydev); + + if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) || + (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) || + (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)) + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS8204_EPHY_CON, + MIIM_CIS8204_EPHYCON_INIT | + MIIM_CIS8204_EPHYCON_RGMII); + else + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS8204_EPHY_CON, + MIIM_CIS8204_EPHYCON_INIT); + + return 0; +} + +/* Vitesse VSC8601 */ +static int vsc8601_config(struct phy_device *phydev) +{ + /* Configure some basic stuff */ +#ifdef CONFIG_SYS_VSC8601_SKEWFIX + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8601_EPHY_CON, + MIIM_VSC8601_EPHY_CON_INIT_SKEW); +#if defined(CONFIG_SYS_VSC8601_SKEW_TX) && defined(CONFIG_SYS_VSC8601_SKEW_RX) + phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, 1); +#define VSC8101_SKEW \ + ((CONFIG_SYS_VSC8601_SKEW_TX << 14) \ + | (CONFIG_SYS_VSC8601_SKEW_RX << 12)) + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8601_SKEW_CTRL, + VSC8101_SKEW); + phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, 0); +#endif +#endif + + genphy_config_aneg(phydev); + + return 0; +} + +static int vsc8574_config(struct phy_device *phydev) +{ + u32 val; + /* configure register 19G for MAC */ + phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, + PHY_EXT_PAGE_ACCESS_GENERAL); + + val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL19); + if (phydev->interface == PHY_INTERFACE_MODE_QSGMII) { + /* set bit 15:14 to '01' for QSGMII mode */ + val = (val & 0x3fff) | (1 << 14); + phy_write(phydev, MDIO_DEVAD_NONE, + MIIM_VSC8574_GENERAL19, val); + /* Enable 4 ports MAC QSGMII */ + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL18, + MIIM_VSC8574_18G_QSGMII); + } else { + /* set bit 15:14 to '00' for SGMII mode */ + val = val & 0x3fff; + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL19, val); + /* Enable 4 ports MAC SGMII */ + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL18, + MIIM_VSC8574_18G_SGMII); + } + val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL18); + /* When bit 15 is cleared the command has completed */ + while (val & MIIM_VSC8574_18G_CMDSTAT) + val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL18); + + /* Enable Serdes Auto-negotiation */ + phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, + PHY_EXT_PAGE_ACCESS_EXTENDED3); + val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_MAC_SERDES_CON); + val = val | MIIM_VSC8574_MAC_SERDES_ANEG; + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_MAC_SERDES_CON, val); + + phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, 0); + + genphy_config_aneg(phydev); + + return 0; +} + +static int vsc8514_config(struct phy_device *phydev) +{ + u32 val; + int timeout = 1000000; + + /* configure register to access 19G */ + phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, + PHY_EXT_PAGE_ACCESS_GENERAL); + + val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL19); + if (phydev->interface == PHY_INTERFACE_MODE_QSGMII) { + /* set bit 15:14 to '01' for QSGMII mode */ + val = (val & 0x3fff) | (1 << 14); + phy_write(phydev, MDIO_DEVAD_NONE, + MIIM_VSC8514_GENERAL19, val); + /* Enable 4 ports MAC QSGMII */ + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL18, + MIIM_VSC8514_18G_QSGMII); + } else { + /*TODO Add SGMII functionality once spec sheet + * for VSC8514 defines complete functionality + */ + } + + val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL18); + /* When bit 15 is cleared the command has completed */ + while ((val & MIIM_VSC8514_18G_CMDSTAT) && timeout--) + val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL18); + + if (0 == timeout) { + printf("PHY 8514 config failed\n"); + return -1; + } + + phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, 0); + + /* configure register to access 23 */ + val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL23); + /* set bits 10:8 to '000' */ + val = (val & 0xf8ff); + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL23, val); + + /* Enable Serdes Auto-negotiation */ + phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, + PHY_EXT_PAGE_ACCESS_EXTENDED3); + val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_MAC_SERDES_CON); + val = val | MIIM_VSC8574_MAC_SERDES_ANEG; + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_MAC_SERDES_CON, val); + phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, 0); + + genphy_config_aneg(phydev); + + return 0; +} + +static int vsc8664_config(struct phy_device *phydev) +{ + u32 val; + + /* Enable MAC interface auto-negotiation */ + phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, 0); + val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_EPHY_CON); + val |= (1 << 13); + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_EPHY_CON, val); + + phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, + PHY_EXT_PAGE_ACCESS_EXTENDED); + val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_SERDES_AND_SIGDET); + val |= (1 << 11); + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_SERDES_AND_SIGDET, val); + phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, 0); + + /* Enable LED blink */ + val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_LED_CON); + val &= ~(1 << 2); + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_LED_CON, val); + + genphy_config_aneg(phydev); + + return 0; +} + +static struct phy_driver VSC8211_driver = { + .name = "Vitesse VSC8211", + .uid = 0xfc4b0, + .mask = 0xffff0, + .features = PHY_GBIT_FEATURES, + .config = &vitesse_config, + .startup = &vitesse_startup, + .shutdown = &genphy_shutdown, +}; + +static struct phy_driver VSC8221_driver = { + .name = "Vitesse VSC8221", + .uid = 0xfc550, + .mask = 0xffff0, + .features = PHY_GBIT_FEATURES, + .config = &genphy_config_aneg, + .startup = &vitesse_startup, + .shutdown = &genphy_shutdown, +}; + +static struct phy_driver VSC8244_driver = { + .name = "Vitesse VSC8244", + .uid = 0xfc6c0, + .mask = 0xffff0, + .features = PHY_GBIT_FEATURES, + .config = &genphy_config_aneg, + .startup = &vitesse_startup, + .shutdown = &genphy_shutdown, +}; + +static struct phy_driver VSC8234_driver = { + .name = "Vitesse VSC8234", + .uid = 0xfc620, + .mask = 0xffff0, + .features = PHY_GBIT_FEATURES, + .config = &genphy_config_aneg, + .startup = &vitesse_startup, + .shutdown = &genphy_shutdown, +}; + +static struct phy_driver VSC8574_driver = { + .name = "Vitesse VSC8574", + .uid = 0x704a0, + .mask = 0xffff0, + .features = PHY_GBIT_FEATURES, + .config = &vsc8574_config, + .startup = &vitesse_startup, + .shutdown = &genphy_shutdown, +}; + +static struct phy_driver VSC8514_driver = { + .name = "Vitesse VSC8514", + .uid = 0x70670, + .mask = 0xffff0, + .features = PHY_GBIT_FEATURES, + .config = &vsc8514_config, + .startup = &vitesse_startup, + .shutdown = &genphy_shutdown, +}; + +static struct phy_driver VSC8584_driver = { + .name = "Vitesse VSC8584", + .uid = 0x707c0, + .mask = 0xffff0, + .features = PHY_GBIT_FEATURES, + .config = &vsc8574_config, + .startup = &vitesse_startup, + .shutdown = &genphy_shutdown, +}; + +static struct phy_driver VSC8601_driver = { + .name = "Vitesse VSC8601", + .uid = 0x70420, + .mask = 0xffff0, + .features = PHY_GBIT_FEATURES, + .config = &vsc8601_config, + .startup = &vitesse_startup, + .shutdown = &genphy_shutdown, +}; + +static struct phy_driver VSC8641_driver = { + .name = "Vitesse VSC8641", + .uid = 0x70430, + .mask = 0xffff0, + .features = PHY_GBIT_FEATURES, + .config = &genphy_config_aneg, + .startup = &vitesse_startup, + .shutdown = &genphy_shutdown, +}; + +static struct phy_driver VSC8662_driver = { + .name = "Vitesse VSC8662", + .uid = 0x70660, + .mask = 0xffff0, + .features = PHY_GBIT_FEATURES, + .config = &genphy_config_aneg, + .startup = &vitesse_startup, + .shutdown = &genphy_shutdown, +}; + +static struct phy_driver VSC8664_driver = { + .name = "Vitesse VSC8664", + .uid = 0x70660, + .mask = 0xffff0, + .features = PHY_GBIT_FEATURES, + .config = &vsc8664_config, + .startup = &vitesse_startup, + .shutdown = &genphy_shutdown, +}; + +/* Vitesse bought Cicada, so we'll put these here */ +static struct phy_driver cis8201_driver = { + .name = "CIS8201", + .uid = 0xfc410, + .mask = 0xffff0, + .features = PHY_GBIT_FEATURES, + .config = &vitesse_config, + .startup = &vitesse_startup, + .shutdown = &genphy_shutdown, +}; + +static struct phy_driver cis8204_driver = { + .name = "Cicada Cis8204", + .uid = 0xfc440, + .mask = 0xffff0, + .features = PHY_GBIT_FEATURES, + .config = &cis8204_config, + .startup = &vitesse_startup, + .shutdown = &genphy_shutdown, +}; + +int phy_vitesse_init(void) +{ + phy_register(&VSC8641_driver); + phy_register(&VSC8601_driver); + phy_register(&VSC8234_driver); + phy_register(&VSC8244_driver); + phy_register(&VSC8211_driver); + phy_register(&VSC8221_driver); + phy_register(&VSC8574_driver); + phy_register(&VSC8584_driver); + phy_register(&VSC8514_driver); + phy_register(&VSC8662_driver); + phy_register(&VSC8664_driver); + phy_register(&cis8201_driver); + phy_register(&cis8204_driver); + + return 0; +} diff --git a/sources/uboot-be550/drivers/net/rtl8139.c b/sources/uboot-be550/drivers/net/rtl8139.c new file mode 100644 index 00000000..ea523435 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8139.c @@ -0,0 +1,539 @@ +/* + * rtl8139.c : U-Boot driver for the RealTek RTL8139 + * + * Masami Komiya (mkomiya@sonare.it) + * + * Most part is taken from rtl8139.c of etherboot + * + */ + +/* rtl8139.c - etherboot driver for the Realtek 8139 chipset + + ported from the linux driver written by Donald Becker + by Rainer Bawidamann (Rainer.Bawidamann@informatik.uni-ulm.de) 1999 + + This software may be used and distributed according to the terms + of the GNU Public License, incorporated herein by reference. + + changes to the original driver: + - removed support for interrupts, switching to polling mode (yuck!) + - removed support for the 8129 chip (external MII) + +*/ + +/*********************************************************************/ +/* Revision History */ +/*********************************************************************/ + +/* + 28 Dec 2002 ken_yap@users.sourceforge.net (Ken Yap) + Put in virt_to_bus calls to allow Etherboot relocation. + + 06 Apr 2001 ken_yap@users.sourceforge.net (Ken Yap) + Following email from Hyun-Joon Cha, added a disable routine, otherwise + NIC remains live and can crash the kernel later. + + 4 Feb 2000 espenlaub@informatik.uni-ulm.de (Klaus Espenlaub) + Shuffled things around, removed the leftovers from the 8129 support + that was in the Linux driver and added a bit more 8139 definitions. + Moved the 8K receive buffer to a fixed, available address outside the + 0x98000-0x9ffff range. This is a bit of a hack, but currently the only + way to make room for the Etherboot features that need substantial amounts + of code like the ANSI console support. Currently the buffer is just below + 0x10000, so this even conforms to the tagged boot image specification, + which reserves the ranges 0x00000-0x10000 and 0x98000-0xA0000. My + interpretation of this "reserved" is that Etherboot may do whatever it + likes, as long as its environment is kept intact (like the BIOS + variables). Hopefully fixed rtl_poll() once and for all. The symptoms + were that if Etherboot was left at the boot menu for several minutes, the + first eth_poll failed. Seems like I am the only person who does this. + First of all I fixed the debugging code and then set out for a long bug + hunting session. It took me about a week full time work - poking around + various places in the driver, reading Don Becker's and Jeff Garzik's Linux + driver and even the FreeBSD driver (what a piece of crap!) - and + eventually spotted the nasty thing: the transmit routine was acknowledging + each and every interrupt pending, including the RxOverrun and RxFIFIOver + interrupts. This confused the RTL8139 thoroughly. It destroyed the + Rx ring contents by dumping the 2K FIFO contents right where we wanted to + get the next packet. Oh well, what fun. + + 18 Jan 2000 mdc@thinguin.org (Marty Connor) + Drastically simplified error handling. Basically, if any error + in transmission or reception occurs, the card is reset. + Also, pointed all transmit descriptors to the same buffer to + save buffer space. This should decrease driver size and avoid + corruption because of exceeding 32K during runtime. + + 28 Jul 1999 (Matthias Meixner - meixner@rbg.informatik.tu-darmstadt.de) + rtl_poll was quite broken: it used the RxOK interrupt flag instead + of the RxBufferEmpty flag which often resulted in very bad + transmission performace - below 1kBytes/s. + +*/ + +#include +#include +#include +#include +#include +#include + +#define RTL_TIMEOUT 100000 + +#define ETH_FRAME_LEN 1514 +#define ETH_ALEN 6 +#define ETH_ZLEN 60 + +/* PCI Tuning Parameters + Threshold is bytes transferred to chip before transmission starts. */ +#define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */ +#define RX_FIFO_THRESH 4 /* Rx buffer level before first PCI xfer. */ +#define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 bytes */ +#define TX_DMA_BURST 4 /* Calculate as 16<priv, a) +#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a) + +/* Symbolic offsets to registers. */ +enum RTL8139_registers { + MAC0=0, /* Ethernet hardware address. */ + MAR0=8, /* Multicast filter. */ + TxStatus0=0x10, /* Transmit status (four 32bit registers). */ + TxAddr0=0x20, /* Tx descriptors (also four 32bit). */ + RxBuf=0x30, RxEarlyCnt=0x34, RxEarlyStatus=0x36, + ChipCmd=0x37, RxBufPtr=0x38, RxBufAddr=0x3A, + IntrMask=0x3C, IntrStatus=0x3E, + TxConfig=0x40, RxConfig=0x44, + Timer=0x48, /* general-purpose counter. */ + RxMissed=0x4C, /* 24 bits valid, write clears. */ + Cfg9346=0x50, Config0=0x51, Config1=0x52, + TimerIntrReg=0x54, /* intr if gp counter reaches this value */ + MediaStatus=0x58, + Config3=0x59, + MultiIntr=0x5C, + RevisionID=0x5E, /* revision of the RTL8139 chip */ + TxSummary=0x60, + MII_BMCR=0x62, MII_BMSR=0x64, NWayAdvert=0x66, NWayLPAR=0x68, + NWayExpansion=0x6A, + DisconnectCnt=0x6C, FalseCarrierCnt=0x6E, + NWayTestReg=0x70, + RxCnt=0x72, /* packet received counter */ + CSCR=0x74, /* chip status and configuration register */ + PhyParm1=0x78,TwisterParm=0x7c,PhyParm2=0x80, /* undocumented */ + /* from 0x84 onwards are a number of power management/wakeup frame + * definitions we will probably never need to know about. */ +}; + +enum ChipCmdBits { + CmdReset=0x10, CmdRxEnb=0x08, CmdTxEnb=0x04, RxBufEmpty=0x01, }; + +/* Interrupt register bits, using my own meaningful names. */ +enum IntrStatusBits { + PCIErr=0x8000, PCSTimeout=0x4000, CableLenChange= 0x2000, + RxFIFOOver=0x40, RxUnderrun=0x20, RxOverflow=0x10, + TxErr=0x08, TxOK=0x04, RxErr=0x02, RxOK=0x01, +}; +enum TxStatusBits { + TxHostOwns=0x2000, TxUnderrun=0x4000, TxStatOK=0x8000, + TxOutOfWindow=0x20000000, TxAborted=0x40000000, + TxCarrierLost=0x80000000, +}; +enum RxStatusBits { + RxMulticast=0x8000, RxPhysical=0x4000, RxBroadcast=0x2000, + RxBadSymbol=0x0020, RxRunt=0x0010, RxTooLong=0x0008, RxCRCErr=0x0004, + RxBadAlign=0x0002, RxStatusOK=0x0001, +}; + +enum MediaStatusBits { + MSRTxFlowEnable=0x80, MSRRxFlowEnable=0x40, MSRSpeed10=0x08, + MSRLinkFail=0x04, MSRRxPauseFlag=0x02, MSRTxPauseFlag=0x01, +}; + +enum MIIBMCRBits { + BMCRReset=0x8000, BMCRSpeed100=0x2000, BMCRNWayEnable=0x1000, + BMCRRestartNWay=0x0200, BMCRDuplex=0x0100, +}; + +enum CSCRBits { + CSCR_LinkOKBit=0x0400, CSCR_LinkChangeBit=0x0800, + CSCR_LinkStatusBits=0x0f000, CSCR_LinkDownOffCmd=0x003c0, + CSCR_LinkDownCmd=0x0f3c0, +}; + +/* Bits in RxConfig. */ +enum rx_mode_bits { + RxCfgWrap=0x80, + AcceptErr=0x20, AcceptRunt=0x10, AcceptBroadcast=0x08, + AcceptMulticast=0x04, AcceptMyPhys=0x02, AcceptAllPhys=0x01, +}; + +static int ioaddr; +static unsigned int cur_rx,cur_tx; + +/* The RTL8139 can only transmit from a contiguous, aligned memory block. */ +static unsigned char tx_buffer[TX_BUF_SIZE] __attribute__((aligned(4))); +static unsigned char rx_ring[RX_BUF_LEN+16] __attribute__((aligned(4))); + +static int rtl8139_probe(struct eth_device *dev, bd_t *bis); +static int read_eeprom(int location, int addr_len); +static void rtl_reset(struct eth_device *dev); +static int rtl_transmit(struct eth_device *dev, void *packet, int length); +static int rtl_poll(struct eth_device *dev); +static void rtl_disable(struct eth_device *dev); +#ifdef CONFIG_MCAST_TFTP/* This driver already accepts all b/mcast */ +static int rtl_bcast_addr(struct eth_device *dev, const u8 *bcast_mac, u8 set) +{ + return (0); +} +#endif + +static struct pci_device_id supported[] = { + {PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139}, + {PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_8139}, + {} +}; + +int rtl8139_initialize(bd_t *bis) +{ + pci_dev_t devno; + int card_number = 0; + struct eth_device *dev; + u32 iobase; + int idx=0; + + while(1){ + /* Find RTL8139 */ + if ((devno = pci_find_devices(supported, idx++)) < 0) + break; + + pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase); + iobase &= ~0xf; + + debug ("rtl8139: REALTEK RTL8139 @0x%x\n", iobase); + + dev = (struct eth_device *)malloc(sizeof *dev); + if (!dev) { + printf("Can not allocate memory of rtl8139\n"); + break; + } + memset(dev, 0, sizeof(*dev)); + + sprintf (dev->name, "RTL8139#%d", card_number); + + dev->priv = (void *) devno; + dev->iobase = (int)bus_to_phys(iobase); + dev->init = rtl8139_probe; + dev->halt = rtl_disable; + dev->send = rtl_transmit; + dev->recv = rtl_poll; +#ifdef CONFIG_MCAST_TFTP + dev->mcast = rtl_bcast_addr; +#endif + + eth_register (dev); + + card_number++; + + pci_write_config_byte (devno, PCI_LATENCY_TIMER, 0x20); + + udelay (10 * 1000); + } + + return card_number; +} + +static int rtl8139_probe(struct eth_device *dev, bd_t *bis) +{ + int i; + int addr_len; + unsigned short *ap = (unsigned short *)dev->enetaddr; + + ioaddr = dev->iobase; + + /* Bring the chip out of low-power mode. */ + outb(0x00, ioaddr + Config1); + + addr_len = read_eeprom(0,8) == 0x8129 ? 8 : 6; + for (i = 0; i < 3; i++) + *ap++ = le16_to_cpu (read_eeprom(i + 7, addr_len)); + + rtl_reset(dev); + + if (inb(ioaddr + MediaStatus) & MSRLinkFail) { + printf("Cable not connected or other link failure\n"); + return -1 ; + } + + return 0; +} + +/* Serial EEPROM section. */ + +/* EEPROM_Ctrl bits. */ +#define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */ +#define EE_CS 0x08 /* EEPROM chip select. */ +#define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */ +#define EE_WRITE_0 0x00 +#define EE_WRITE_1 0x02 +#define EE_DATA_READ 0x01 /* EEPROM chip data out. */ +#define EE_ENB (0x80 | EE_CS) + +/* + Delay between EEPROM clock transitions. + No extra delay is needed with 33MHz PCI, but 66MHz may change this. +*/ + +#define eeprom_delay() inl(ee_addr) + +/* The EEPROM commands include the alway-set leading bit. */ +#define EE_WRITE_CMD (5) +#define EE_READ_CMD (6) +#define EE_ERASE_CMD (7) + +static int read_eeprom(int location, int addr_len) +{ + int i; + unsigned int retval = 0; + long ee_addr = ioaddr + Cfg9346; + int read_cmd = location | (EE_READ_CMD << addr_len); + + outb(EE_ENB & ~EE_CS, ee_addr); + outb(EE_ENB, ee_addr); + eeprom_delay(); + + /* Shift the read command bits out. */ + for (i = 4 + addr_len; i >= 0; i--) { + int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0; + outb(EE_ENB | dataval, ee_addr); + eeprom_delay(); + outb(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr); + eeprom_delay(); + } + outb(EE_ENB, ee_addr); + eeprom_delay(); + + for (i = 16; i > 0; i--) { + outb(EE_ENB | EE_SHIFT_CLK, ee_addr); + eeprom_delay(); + retval = (retval << 1) | ((inb(ee_addr) & EE_DATA_READ) ? 1 : 0); + outb(EE_ENB, ee_addr); + eeprom_delay(); + } + + /* Terminate the EEPROM access. */ + outb(~EE_CS, ee_addr); + eeprom_delay(); + return retval; +} + +static const unsigned int rtl8139_rx_config = + (RX_BUF_LEN_IDX << 11) | + (RX_FIFO_THRESH << 13) | + (RX_DMA_BURST << 8); + +static void set_rx_mode(struct eth_device *dev) { + unsigned int mc_filter[2]; + int rx_mode; + /* !IFF_PROMISC */ + rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; + mc_filter[1] = mc_filter[0] = 0xffffffff; + + outl(rtl8139_rx_config | rx_mode, ioaddr + RxConfig); + + outl(mc_filter[0], ioaddr + MAR0 + 0); + outl(mc_filter[1], ioaddr + MAR0 + 4); +} + +static void rtl_reset(struct eth_device *dev) +{ + int i; + + outb(CmdReset, ioaddr + ChipCmd); + + cur_rx = 0; + cur_tx = 0; + + /* Give the chip 10ms to finish the reset. */ + for (i=0; i<100; ++i){ + if ((inb(ioaddr + ChipCmd) & CmdReset) == 0) break; + udelay (100); /* wait 100us */ + } + + + for (i = 0; i < ETH_ALEN; i++) + outb(dev->enetaddr[i], ioaddr + MAC0 + i); + + /* Must enable Tx/Rx before setting transfer thresholds! */ + outb(CmdRxEnb | CmdTxEnb, ioaddr + ChipCmd); + outl((RX_FIFO_THRESH<<13) | (RX_BUF_LEN_IDX<<11) | (RX_DMA_BURST<<8), + ioaddr + RxConfig); /* accept no frames yet! */ + outl((TX_DMA_BURST<<8)|0x03000000, ioaddr + TxConfig); + + /* The Linux driver changes Config1 here to use a different LED pattern + * for half duplex or full/autodetect duplex (for full/autodetect, the + * outputs are TX/RX, Link10/100, FULL, while for half duplex it uses + * TX/RX, Link100, Link10). This is messy, because it doesn't match + * the inscription on the mounting bracket. It should not be changed + * from the configuration EEPROM default, because the card manufacturer + * should have set that to match the card. */ + + debug_cond(DEBUG_RX, + "rx ring address is %lX\n",(unsigned long)rx_ring); + flush_cache((unsigned long)rx_ring, RX_BUF_LEN); + outl(phys_to_bus((int)rx_ring), ioaddr + RxBuf); + + /* If we add multicast support, the MAR0 register would have to be + * initialized to 0xffffffffffffffff (two 32 bit accesses). Etherboot + * only needs broadcast (for ARP/RARP/BOOTP/DHCP) and unicast. */ + + outb(CmdRxEnb | CmdTxEnb, ioaddr + ChipCmd); + + outl(rtl8139_rx_config, ioaddr + RxConfig); + + /* Start the chip's Tx and Rx process. */ + outl(0, ioaddr + RxMissed); + + /* set_rx_mode */ + set_rx_mode(dev); + + /* Disable all known interrupts by setting the interrupt mask. */ + outw(0, ioaddr + IntrMask); +} + +static int rtl_transmit(struct eth_device *dev, void *packet, int length) +{ + unsigned int status; + unsigned long txstatus; + unsigned int len = length; + int i = 0; + + ioaddr = dev->iobase; + + memcpy((char *)tx_buffer, (char *)packet, (int)length); + + debug_cond(DEBUG_TX, "sending %d bytes\n", len); + + /* Note: RTL8139 doesn't auto-pad, send minimum payload (another 4 + * bytes are sent automatically for the FCS, totalling to 64 bytes). */ + while (len < ETH_ZLEN) { + tx_buffer[len++] = '\0'; + } + + flush_cache((unsigned long)tx_buffer, length); + outl(phys_to_bus((int)tx_buffer), ioaddr + TxAddr0 + cur_tx*4); + outl(((TX_FIFO_THRESH<<11) & 0x003f0000) | len, + ioaddr + TxStatus0 + cur_tx*4); + + do { + status = inw(ioaddr + IntrStatus); + /* Only acknlowledge interrupt sources we can properly handle + * here - the RxOverflow/RxFIFOOver MUST be handled in the + * rtl_poll() function. */ + outw(status & (TxOK | TxErr | PCIErr), ioaddr + IntrStatus); + if ((status & (TxOK | TxErr | PCIErr)) != 0) break; + udelay(10); + } while (i++ < RTL_TIMEOUT); + + txstatus = inl(ioaddr + TxStatus0 + cur_tx*4); + + if (status & TxOK) { + cur_tx = (cur_tx + 1) % NUM_TX_DESC; + + debug_cond(DEBUG_TX, + "tx done, status %hX txstatus %lX\n", + status, txstatus); + + return length; + } else { + + debug_cond(DEBUG_TX, + "tx timeout/error (%d usecs), status %hX txstatus %lX\n", + 10*i, status, txstatus); + + rtl_reset(dev); + + return 0; + } +} + +static int rtl_poll(struct eth_device *dev) +{ + unsigned int status; + unsigned int ring_offs; + unsigned int rx_size, rx_status; + int length=0; + + ioaddr = dev->iobase; + + if (inb(ioaddr + ChipCmd) & RxBufEmpty) { + return 0; + } + + status = inw(ioaddr + IntrStatus); + /* See below for the rest of the interrupt acknowledges. */ + outw(status & ~(RxFIFOOver | RxOverflow | RxOK), ioaddr + IntrStatus); + + debug_cond(DEBUG_RX, "rtl_poll: int %hX ", status); + + ring_offs = cur_rx % RX_BUF_LEN; + /* ring_offs is guaranteed being 4-byte aligned */ + rx_status = le32_to_cpu(*(unsigned int *)(rx_ring + ring_offs)); + rx_size = rx_status >> 16; + rx_status &= 0xffff; + + if ((rx_status & (RxBadSymbol|RxRunt|RxTooLong|RxCRCErr|RxBadAlign)) || + (rx_size < ETH_ZLEN) || (rx_size > ETH_FRAME_LEN + 4)) { + printf("rx error %hX\n", rx_status); + rtl_reset(dev); /* this clears all interrupts still pending */ + return 0; + } + + /* Received a good packet */ + length = rx_size - 4; /* no one cares about the FCS */ + if (ring_offs+4+rx_size-4 > RX_BUF_LEN) { + int semi_count = RX_BUF_LEN - ring_offs - 4; + unsigned char rxdata[RX_BUF_LEN]; + + memcpy(rxdata, rx_ring + ring_offs + 4, semi_count); + memcpy(&(rxdata[semi_count]), rx_ring, rx_size-4-semi_count); + + net_process_received_packet(rxdata, length); + debug_cond(DEBUG_RX, "rx packet %d+%d bytes", + semi_count, rx_size-4-semi_count); + } else { + net_process_received_packet(rx_ring + ring_offs + 4, length); + debug_cond(DEBUG_RX, "rx packet %d bytes", rx_size-4); + } + flush_cache((unsigned long)rx_ring, RX_BUF_LEN); + + cur_rx = (cur_rx + rx_size + 4 + 3) & ~3; + outw(cur_rx - 16, ioaddr + RxBufPtr); + /* See RTL8139 Programming Guide V0.1 for the official handling of + * Rx overflow situations. The document itself contains basically no + * usable information, except for a few exception handling rules. */ + outw(status & (RxFIFOOver | RxOverflow | RxOK), ioaddr + IntrStatus); + return length; +} + +static void rtl_disable(struct eth_device *dev) +{ + int i; + + ioaddr = dev->iobase; + + /* reset the chip */ + outb(CmdReset, ioaddr + ChipCmd); + + /* Give the chip 10ms to finish the reset. */ + for (i=0; i<100; ++i){ + if ((inb(ioaddr + ChipCmd) & CmdReset) == 0) break; + udelay (100); /* wait 100us */ + } +} diff --git a/sources/uboot-be550/drivers/net/rtl8169.c b/sources/uboot-be550/drivers/net/rtl8169.c new file mode 100644 index 00000000..19422c4a --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8169.c @@ -0,0 +1,1170 @@ +/* + * rtl8169.c : U-Boot driver for the RealTek RTL8169 + * + * Masami Komiya (mkomiya@sonare.it) + * + * Most part is taken from r8169.c of etherboot + * + */ + +/************************************************************************** +* r8169.c: Etherboot device driver for the RealTek RTL-8169 Gigabit +* Written 2003 by Timothy Legge +* + * SPDX-License-Identifier: GPL-2.0+ +* +* Portions of this code based on: +* r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver +* for Linux kernel 2.4.x. +* +* Written 2002 ShuChen +* See Linux Driver for full information +* +* Linux Driver Version 1.27a, 10.02.2002 +* +* Thanks to: +* Jean Chen of RealTek Semiconductor Corp. for +* providing the evaluation NIC used to develop +* this driver. RealTek's support for Etherboot +* is appreciated. +* +* REVISION HISTORY: +* ================ +* +* v1.0 11-26-2003 timlegge Initial port of Linux driver +* v1.5 01-17-2004 timlegge Initial driver output cleanup +* +* Indent Options: indent -kr -i8 +***************************************************************************/ +/* + * 26 August 2006 Mihai Georgian + * Modified to use le32_to_cpu and cpu_to_le32 properly + */ +#include +#include +#include +#include +#include +#include +#ifndef CONFIG_DM_ETH +#include +#endif +#include +#include + +#undef DEBUG_RTL8169 +#undef DEBUG_RTL8169_TX +#undef DEBUG_RTL8169_RX + +#define drv_version "v1.5" +#define drv_date "01-17-2004" + +static unsigned long ioaddr; + +/* Condensed operations for readability. */ +#define currticks() get_timer(0) + +/* media options */ +#define MAX_UNITS 8 +static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 }; + +/* MAC address length*/ +#define MAC_ADDR_LEN 6 + +/* max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4).*/ +#define MAX_ETH_FRAME_SIZE 1536 + +#define TX_FIFO_THRESH 256 /* In bytes */ + +#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */ +#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ +#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ +#define EarlyTxThld 0x3F /* 0x3F means NO early transmit */ +#define RxPacketMaxSize 0x0800 /* Maximum size supported is 16K-1 */ +#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ + +#define NUM_TX_DESC 1 /* Number of Tx descriptor registers */ +#ifdef CONFIG_SYS_RX_ETH_BUFFER + #define NUM_RX_DESC CONFIG_SYS_RX_ETH_BUFFER +#else + #define NUM_RX_DESC 4 /* Number of Rx descriptor registers */ +#endif +#define RX_BUF_SIZE 1536 /* Rx Buffer size */ +#define RX_BUF_LEN 8192 + +#define RTL_MIN_IO_SIZE 0x80 +#define TX_TIMEOUT (6*HZ) + +/* write/read MMIO register. Notice: {read,write}[wl] do the necessary swapping */ +#define RTL_W8(reg, val8) writeb((val8), ioaddr + (reg)) +#define RTL_W16(reg, val16) writew((val16), ioaddr + (reg)) +#define RTL_W32(reg, val32) writel((val32), ioaddr + (reg)) +#define RTL_R8(reg) readb(ioaddr + (reg)) +#define RTL_R16(reg) readw(ioaddr + (reg)) +#define RTL_R32(reg) readl(ioaddr + (reg)) + +#define ETH_FRAME_LEN MAX_ETH_FRAME_SIZE +#define ETH_ALEN MAC_ADDR_LEN +#define ETH_ZLEN 60 + +#define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)(unsigned long)dev->priv, \ + (pci_addr_t)(unsigned long)a) +#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)(unsigned long)dev->priv, \ + (phys_addr_t)a) + +enum RTL8169_registers { + MAC0 = 0, /* Ethernet hardware address. */ + MAR0 = 8, /* Multicast filter. */ + TxDescStartAddrLow = 0x20, + TxDescStartAddrHigh = 0x24, + TxHDescStartAddrLow = 0x28, + TxHDescStartAddrHigh = 0x2c, + FLASH = 0x30, + ERSR = 0x36, + ChipCmd = 0x37, + TxPoll = 0x38, + IntrMask = 0x3C, + IntrStatus = 0x3E, + TxConfig = 0x40, + RxConfig = 0x44, + RxMissed = 0x4C, + Cfg9346 = 0x50, + Config0 = 0x51, + Config1 = 0x52, + Config2 = 0x53, + Config3 = 0x54, + Config4 = 0x55, + Config5 = 0x56, + MultiIntr = 0x5C, + PHYAR = 0x60, + TBICSR = 0x64, + TBI_ANAR = 0x68, + TBI_LPAR = 0x6A, + PHYstatus = 0x6C, + RxMaxSize = 0xDA, + CPlusCmd = 0xE0, + RxDescStartAddrLow = 0xE4, + RxDescStartAddrHigh = 0xE8, + EarlyTxThres = 0xEC, + FuncEvent = 0xF0, + FuncEventMask = 0xF4, + FuncPresetState = 0xF8, + FuncForceEvent = 0xFC, +}; + +enum RTL8169_register_content { + /*InterruptStatusBits */ + SYSErr = 0x8000, + PCSTimeout = 0x4000, + SWInt = 0x0100, + TxDescUnavail = 0x80, + RxFIFOOver = 0x40, + RxUnderrun = 0x20, + RxOverflow = 0x10, + TxErr = 0x08, + TxOK = 0x04, + RxErr = 0x02, + RxOK = 0x01, + + /*RxStatusDesc */ + RxRES = 0x00200000, + RxCRC = 0x00080000, + RxRUNT = 0x00100000, + RxRWT = 0x00400000, + + /*ChipCmdBits */ + CmdReset = 0x10, + CmdRxEnb = 0x08, + CmdTxEnb = 0x04, + RxBufEmpty = 0x01, + + /*Cfg9346Bits */ + Cfg9346_Lock = 0x00, + Cfg9346_Unlock = 0xC0, + + /*rx_mode_bits */ + AcceptErr = 0x20, + AcceptRunt = 0x10, + AcceptBroadcast = 0x08, + AcceptMulticast = 0x04, + AcceptMyPhys = 0x02, + AcceptAllPhys = 0x01, + + /*RxConfigBits */ + RxCfgFIFOShift = 13, + RxCfgDMAShift = 8, + + /*TxConfigBits */ + TxInterFrameGapShift = 24, + TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ + + /*rtl8169_PHYstatus */ + TBI_Enable = 0x80, + TxFlowCtrl = 0x40, + RxFlowCtrl = 0x20, + _1000bpsF = 0x10, + _100bps = 0x08, + _10bps = 0x04, + LinkStatus = 0x02, + FullDup = 0x01, + + /*GIGABIT_PHY_registers */ + PHY_CTRL_REG = 0, + PHY_STAT_REG = 1, + PHY_AUTO_NEGO_REG = 4, + PHY_1000_CTRL_REG = 9, + + /*GIGABIT_PHY_REG_BIT */ + PHY_Restart_Auto_Nego = 0x0200, + PHY_Enable_Auto_Nego = 0x1000, + + /* PHY_STAT_REG = 1; */ + PHY_Auto_Nego_Comp = 0x0020, + + /* PHY_AUTO_NEGO_REG = 4; */ + PHY_Cap_10_Half = 0x0020, + PHY_Cap_10_Full = 0x0040, + PHY_Cap_100_Half = 0x0080, + PHY_Cap_100_Full = 0x0100, + + /* PHY_1000_CTRL_REG = 9; */ + PHY_Cap_1000_Full = 0x0200, + + PHY_Cap_Null = 0x0, + + /*_MediaType*/ + _10_Half = 0x01, + _10_Full = 0x02, + _100_Half = 0x04, + _100_Full = 0x08, + _1000_Full = 0x10, + + /*_TBICSRBit*/ + TBILinkOK = 0x02000000, +}; + +static struct { + const char *name; + u8 version; /* depend on RTL8169 docs */ + u32 RxConfigMask; /* should clear the bits supported by this chip */ +} rtl_chip_info[] = { + {"RTL-8169", 0x00, 0xff7e1880,}, + {"RTL-8169", 0x04, 0xff7e1880,}, + {"RTL-8169", 0x00, 0xff7e1880,}, + {"RTL-8169s/8110s", 0x02, 0xff7e1880,}, + {"RTL-8169s/8110s", 0x04, 0xff7e1880,}, + {"RTL-8169sb/8110sb", 0x10, 0xff7e1880,}, + {"RTL-8169sc/8110sc", 0x18, 0xff7e1880,}, + {"RTL-8168b/8111sb", 0x30, 0xff7e1880,}, + {"RTL-8168b/8111sb", 0x38, 0xff7e1880,}, + {"RTL-8168d/8111d", 0x28, 0xff7e1880,}, + {"RTL-8168evl/8111evl", 0x2e, 0xff7e1880,}, + {"RTL-8168/8111g", 0x4c, 0xff7e1880,}, + {"RTL-8101e", 0x34, 0xff7e1880,}, + {"RTL-8100e", 0x32, 0xff7e1880,}, +}; + +enum _DescStatusBit { + OWNbit = 0x80000000, + EORbit = 0x40000000, + FSbit = 0x20000000, + LSbit = 0x10000000, +}; + +struct TxDesc { + u32 status; + u32 vlan_tag; + u32 buf_addr; + u32 buf_Haddr; +}; + +struct RxDesc { + u32 status; + u32 vlan_tag; + u32 buf_addr; + u32 buf_Haddr; +}; + +static unsigned char rxdata[RX_BUF_LEN]; + +#define RTL8169_DESC_SIZE 16 + +#if ARCH_DMA_MINALIGN > 256 +# define RTL8169_ALIGN ARCH_DMA_MINALIGN +#else +# define RTL8169_ALIGN 256 +#endif + +/* + * Warn if the cache-line size is larger than the descriptor size. In such + * cases the driver will likely fail because the CPU needs to flush the cache + * when requeuing RX buffers, therefore descriptors written by the hardware + * may be discarded. + * + * This can be fixed by defining CONFIG_SYS_NONCACHED_MEMORY which will cause + * the driver to allocate descriptors from a pool of non-cached memory. + */ +#if RTL8169_DESC_SIZE < ARCH_DMA_MINALIGN +#if !defined(CONFIG_SYS_NONCACHED_MEMORY) && \ + !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_X86) +#warning cache-line size is larger than descriptor size +#endif +#endif + +/* + * Create a static buffer of size RX_BUF_SZ for each TX Descriptor. All + * descriptors point to a part of this buffer. + */ +DEFINE_ALIGN_BUFFER(u8, txb, NUM_TX_DESC * RX_BUF_SIZE, RTL8169_ALIGN); + +/* + * Create a static buffer of size RX_BUF_SZ for each RX Descriptor. All + * descriptors point to a part of this buffer. + */ +DEFINE_ALIGN_BUFFER(u8, rxb, NUM_RX_DESC * RX_BUF_SIZE, RTL8169_ALIGN); + +struct rtl8169_private { + ulong iobase; + void *mmio_addr; /* memory map physical address */ + int chipset; + unsigned long cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ + unsigned long cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ + unsigned long dirty_tx; + struct TxDesc *TxDescArray; /* Index of 256-alignment Tx Descriptor buffer */ + struct RxDesc *RxDescArray; /* Index of 256-alignment Rx Descriptor buffer */ + unsigned char *RxBufferRings; /* Index of Rx Buffer */ + unsigned char *RxBufferRing[NUM_RX_DESC]; /* Index of Rx Buffer array */ + unsigned char *Tx_skbuff[NUM_TX_DESC]; +} tpx; + +static struct rtl8169_private *tpc; + +static const u16 rtl8169_intr_mask = + SYSErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver | TxErr | + TxOK | RxErr | RxOK; +static const unsigned int rtl8169_rx_config = + (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift); + +static struct pci_device_id supported[] = { + { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167) }, + { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168) }, + { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169) }, + {} +}; + +void mdio_write(int RegAddr, int value) +{ + int i; + + RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value); + udelay(1000); + + for (i = 2000; i > 0; i--) { + /* Check if the RTL8169 has completed writing to the specified MII register */ + if (!(RTL_R32(PHYAR) & 0x80000000)) { + break; + } else { + udelay(100); + } + } +} + +int mdio_read(int RegAddr) +{ + int i, value = -1; + + RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16); + udelay(1000); + + for (i = 2000; i > 0; i--) { + /* Check if the RTL8169 has completed retrieving data from the specified MII register */ + if (RTL_R32(PHYAR) & 0x80000000) { + value = (int) (RTL_R32(PHYAR) & 0xFFFF); + break; + } else { + udelay(100); + } + } + return value; +} + +static int rtl8169_init_board(unsigned long dev_iobase, const char *name) +{ + int i; + u32 tmp; + +#ifdef DEBUG_RTL8169 + printf ("%s\n", __FUNCTION__); +#endif + ioaddr = dev_iobase; + + /* Soft reset the chip. */ + RTL_W8(ChipCmd, CmdReset); + + /* Check that the chip has finished the reset. */ + for (i = 1000; i > 0; i--) + if ((RTL_R8(ChipCmd) & CmdReset) == 0) + break; + else + udelay(10); + + /* identify chip attached to board */ + tmp = RTL_R32(TxConfig); + tmp = ((tmp & 0x7c000000) + ((tmp & 0x00800000) << 2)) >> 24; + + for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--){ + if (tmp == rtl_chip_info[i].version) { + tpc->chipset = i; + goto match; + } + } + + /* if unknown chip, assume array element #0, original RTL-8169 in this case */ + printf("PCI device %s: unknown chip version, assuming RTL-8169\n", + name); + printf("PCI device: TxConfig = 0x%lX\n", (unsigned long) RTL_R32(TxConfig)); + tpc->chipset = 0; + +match: + return 0; +} + +/* + * TX and RX descriptors are 16 bytes. This causes problems with the cache + * maintenance on CPUs where the cache-line size exceeds the size of these + * descriptors. What will happen is that when the driver receives a packet + * it will be immediately requeued for the hardware to reuse. The CPU will + * therefore need to flush the cache-line containing the descriptor, which + * will cause all other descriptors in the same cache-line to be flushed + * along with it. If one of those descriptors had been written to by the + * device those changes (and the associated packet) will be lost. + * + * To work around this, we make use of non-cached memory if available. If + * descriptors are mapped uncached there's no need to manually flush them + * or invalidate them. + * + * Note that this only applies to descriptors. The packet data buffers do + * not have the same constraints since they are 1536 bytes large, so they + * are unlikely to share cache-lines. + */ +static void *rtl_alloc_descs(unsigned int num) +{ + size_t size = num * RTL8169_DESC_SIZE; + +#ifdef CONFIG_SYS_NONCACHED_MEMORY + return (void *)noncached_alloc(size, RTL8169_ALIGN); +#else + return memalign(RTL8169_ALIGN, size); +#endif +} + +/* + * Cache maintenance functions. These are simple wrappers around the more + * general purpose flush_cache() and invalidate_dcache_range() functions. + */ + +static void rtl_inval_rx_desc(struct RxDesc *desc) +{ +#ifndef CONFIG_SYS_NONCACHED_MEMORY + unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1); + unsigned long end = ALIGN(start + sizeof(*desc), ARCH_DMA_MINALIGN); + + invalidate_dcache_range(start, end); +#endif +} + +static void rtl_flush_rx_desc(struct RxDesc *desc) +{ +#ifndef CONFIG_SYS_NONCACHED_MEMORY + flush_cache((unsigned long)desc, sizeof(*desc)); +#endif +} + +static void rtl_inval_tx_desc(struct TxDesc *desc) +{ +#ifndef CONFIG_SYS_NONCACHED_MEMORY + unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1); + unsigned long end = ALIGN(start + sizeof(*desc), ARCH_DMA_MINALIGN); + + invalidate_dcache_range(start, end); +#endif +} + +static void rtl_flush_tx_desc(struct TxDesc *desc) +{ +#ifndef CONFIG_SYS_NONCACHED_MEMORY + flush_cache((unsigned long)desc, sizeof(*desc)); +#endif +} + +static void rtl_inval_buffer(void *buf, size_t size) +{ + unsigned long start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1); + unsigned long end = ALIGN(start + size, ARCH_DMA_MINALIGN); + + invalidate_dcache_range(start, end); +} + +static void rtl_flush_buffer(void *buf, size_t size) +{ + flush_cache((unsigned long)buf, size); +} + +/************************************************************************** +RECV - Receive a frame +***************************************************************************/ +static int rtl_recv_common(pci_dev_t bdf, unsigned long dev_iobase, + uchar **packetp) +{ + /* return true if there's an ethernet packet ready to read */ + /* nic->packet should contain data on return */ + /* nic->packetlen should contain length of data */ + int cur_rx; + int length = 0; + +#ifdef DEBUG_RTL8169_RX + printf ("%s\n", __FUNCTION__); +#endif + ioaddr = dev_iobase; + + cur_rx = tpc->cur_rx; + + rtl_inval_rx_desc(&tpc->RxDescArray[cur_rx]); + + if ((le32_to_cpu(tpc->RxDescArray[cur_rx].status) & OWNbit) == 0) { + if (!(le32_to_cpu(tpc->RxDescArray[cur_rx].status) & RxRES)) { + length = (int) (le32_to_cpu(tpc->RxDescArray[cur_rx]. + status) & 0x00001FFF) - 4; + + rtl_inval_buffer(tpc->RxBufferRing[cur_rx], length); + memcpy(rxdata, tpc->RxBufferRing[cur_rx], length); + + if (cur_rx == NUM_RX_DESC - 1) + tpc->RxDescArray[cur_rx].status = + cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE); + else + tpc->RxDescArray[cur_rx].status = + cpu_to_le32(OWNbit + RX_BUF_SIZE); + tpc->RxDescArray[cur_rx].buf_addr = cpu_to_le32( + pci_mem_to_phys(bdf, (pci_addr_t)(unsigned long) + tpc->RxBufferRing[cur_rx])); + rtl_flush_rx_desc(&tpc->RxDescArray[cur_rx]); +#ifdef CONFIG_DM_ETH + *packetp = rxdata; +#else + net_process_received_packet(rxdata, length); +#endif + } else { + puts("Error Rx"); + length = -EIO; + } + cur_rx = (cur_rx + 1) % NUM_RX_DESC; + tpc->cur_rx = cur_rx; + return length; + + } else { + ushort sts = RTL_R8(IntrStatus); + RTL_W8(IntrStatus, sts & ~(TxErr | RxErr | SYSErr)); + udelay(100); /* wait */ + } + tpc->cur_rx = cur_rx; + return (0); /* initially as this is called to flush the input */ +} + +#ifdef CONFIG_DM_ETH +int rtl8169_eth_recv(struct udevice *dev, int flags, uchar **packetp) +{ + struct rtl8169_private *priv = dev_get_priv(dev); + + return rtl_recv_common(pci_get_bdf(dev), priv->iobase, packetp); +} +#else +static int rtl_recv(struct eth_device *dev) +{ + return rtl_recv_common((pci_dev_t)(unsigned long)dev->priv, + dev->iobase, NULL); +} +#endif /* nCONFIG_DM_ETH */ + +#define HZ 1000 +/************************************************************************** +SEND - Transmit a frame +***************************************************************************/ +static int rtl_send_common(pci_dev_t bdf, unsigned long dev_iobase, + void *packet, int length) +{ + /* send the packet to destination */ + + u32 to; + u8 *ptxb; + int entry = tpc->cur_tx % NUM_TX_DESC; + u32 len = length; + int ret; + +#ifdef DEBUG_RTL8169_TX + int stime = currticks(); + printf ("%s\n", __FUNCTION__); + printf("sending %d bytes\n", len); +#endif + + ioaddr = dev_iobase; + + /* point to the current txb incase multiple tx_rings are used */ + ptxb = tpc->Tx_skbuff[entry * MAX_ETH_FRAME_SIZE]; + memcpy(ptxb, (char *)packet, (int)length); + rtl_flush_buffer(ptxb, length); + + while (len < ETH_ZLEN) + ptxb[len++] = '\0'; + + tpc->TxDescArray[entry].buf_Haddr = 0; + tpc->TxDescArray[entry].buf_addr = cpu_to_le32( + pci_mem_to_phys(bdf, (pci_addr_t)(unsigned long)ptxb)); + if (entry != (NUM_TX_DESC - 1)) { + tpc->TxDescArray[entry].status = + cpu_to_le32((OWNbit | FSbit | LSbit) | + ((len > ETH_ZLEN) ? len : ETH_ZLEN)); + } else { + tpc->TxDescArray[entry].status = + cpu_to_le32((OWNbit | EORbit | FSbit | LSbit) | + ((len > ETH_ZLEN) ? len : ETH_ZLEN)); + } + rtl_flush_tx_desc(&tpc->TxDescArray[entry]); + RTL_W8(TxPoll, 0x40); /* set polling bit */ + + tpc->cur_tx++; + to = currticks() + TX_TIMEOUT; + do { + rtl_inval_tx_desc(&tpc->TxDescArray[entry]); + } while ((le32_to_cpu(tpc->TxDescArray[entry].status) & OWNbit) + && (currticks() < to)); /* wait */ + + if (currticks() >= to) { +#ifdef DEBUG_RTL8169_TX + puts("tx timeout/error\n"); + printf("%s elapsed time : %lu\n", __func__, currticks()-stime); +#endif + ret = 0; + } else { +#ifdef DEBUG_RTL8169_TX + puts("tx done\n"); +#endif + ret = length; + } + /* Delay to make net console (nc) work properly */ + udelay(20); + return ret; +} + +#ifdef CONFIG_DM_ETH +int rtl8169_eth_send(struct udevice *dev, void *packet, int length) +{ + struct rtl8169_private *priv = dev_get_priv(dev); + + return rtl_send_common(pci_get_bdf(dev), priv->iobase, packet, length); +} + +#else +static int rtl_send(struct eth_device *dev, void *packet, int length) +{ + return rtl_send_common((pci_dev_t)(unsigned long)dev->priv, + dev->iobase, packet, length); +} +#endif + +static void rtl8169_set_rx_mode(void) +{ + u32 mc_filter[2]; /* Multicast hash filter */ + int rx_mode; + u32 tmp = 0; + +#ifdef DEBUG_RTL8169 + printf ("%s\n", __FUNCTION__); +#endif + + /* IFF_ALLMULTI */ + /* Too many to filter perfectly -- accept all multicasts. */ + rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; + mc_filter[1] = mc_filter[0] = 0xffffffff; + + tmp = rtl8169_rx_config | rx_mode | (RTL_R32(RxConfig) & + rtl_chip_info[tpc->chipset].RxConfigMask); + + RTL_W32(RxConfig, tmp); + RTL_W32(MAR0 + 0, mc_filter[0]); + RTL_W32(MAR0 + 4, mc_filter[1]); +} + +static void rtl8169_hw_start(pci_dev_t bdf) +{ + u32 i; + +#ifdef DEBUG_RTL8169 + int stime = currticks(); + printf ("%s\n", __FUNCTION__); +#endif + +#if 0 + /* Soft reset the chip. */ + RTL_W8(ChipCmd, CmdReset); + + /* Check that the chip has finished the reset. */ + for (i = 1000; i > 0; i--) { + if ((RTL_R8(ChipCmd) & CmdReset) == 0) + break; + else + udelay(10); + } +#endif + + RTL_W8(Cfg9346, Cfg9346_Unlock); + + /* RTL-8169sb/8110sb or previous version */ + if (tpc->chipset <= 5) + RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); + + RTL_W8(EarlyTxThres, EarlyTxThld); + + /* For gigabit rtl8169 */ + RTL_W16(RxMaxSize, RxPacketMaxSize); + + /* Set Rx Config register */ + i = rtl8169_rx_config | (RTL_R32(RxConfig) & + rtl_chip_info[tpc->chipset].RxConfigMask); + RTL_W32(RxConfig, i); + + /* Set DMA burst size and Interframe Gap Time */ + RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | + (InterFrameGap << TxInterFrameGapShift)); + + + tpc->cur_rx = 0; + + RTL_W32(TxDescStartAddrLow, pci_mem_to_phys(bdf, + (pci_addr_t)(unsigned long)tpc->TxDescArray)); + RTL_W32(TxDescStartAddrHigh, (unsigned long)0); + RTL_W32(RxDescStartAddrLow, pci_mem_to_phys( + bdf, (pci_addr_t)(unsigned long)tpc->RxDescArray)); + RTL_W32(RxDescStartAddrHigh, (unsigned long)0); + + /* RTL-8169sc/8110sc or later version */ + if (tpc->chipset > 5) + RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); + + RTL_W8(Cfg9346, Cfg9346_Lock); + udelay(10); + + RTL_W32(RxMissed, 0); + + rtl8169_set_rx_mode(); + + /* no early-rx interrupts */ + RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); + +#ifdef DEBUG_RTL8169 + printf("%s elapsed time : %lu\n", __func__, currticks()-stime); +#endif +} + +static void rtl8169_init_ring(pci_dev_t bdf) +{ + int i; + +#ifdef DEBUG_RTL8169 + int stime = currticks(); + printf ("%s\n", __FUNCTION__); +#endif + + tpc->cur_rx = 0; + tpc->cur_tx = 0; + tpc->dirty_tx = 0; + memset(tpc->TxDescArray, 0x0, NUM_TX_DESC * sizeof(struct TxDesc)); + memset(tpc->RxDescArray, 0x0, NUM_RX_DESC * sizeof(struct RxDesc)); + + for (i = 0; i < NUM_TX_DESC; i++) { + tpc->Tx_skbuff[i] = &txb[i]; + } + + for (i = 0; i < NUM_RX_DESC; i++) { + if (i == (NUM_RX_DESC - 1)) + tpc->RxDescArray[i].status = + cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE); + else + tpc->RxDescArray[i].status = + cpu_to_le32(OWNbit + RX_BUF_SIZE); + + tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE]; + tpc->RxDescArray[i].buf_addr = cpu_to_le32(pci_mem_to_phys( + bdf, (pci_addr_t)(unsigned long)tpc->RxBufferRing[i])); + rtl_flush_rx_desc(&tpc->RxDescArray[i]); + } + +#ifdef DEBUG_RTL8169 + printf("%s elapsed time : %lu\n", __func__, currticks()-stime); +#endif +} + +static void rtl8169_common_start(pci_dev_t bdf, unsigned char *enetaddr) +{ + int i; + +#ifdef DEBUG_RTL8169 + int stime = currticks(); + printf ("%s\n", __FUNCTION__); +#endif + + rtl8169_init_ring(bdf); + rtl8169_hw_start(bdf); + /* Construct a perfect filter frame with the mac address as first match + * and broadcast for all others */ + for (i = 0; i < 192; i++) + txb[i] = 0xFF; + + txb[0] = enetaddr[0]; + txb[1] = enetaddr[1]; + txb[2] = enetaddr[2]; + txb[3] = enetaddr[3]; + txb[4] = enetaddr[4]; + txb[5] = enetaddr[5]; + +#ifdef DEBUG_RTL8169 + printf("%s elapsed time : %lu\n", __func__, currticks()-stime); +#endif +} + +#ifdef CONFIG_DM_ETH +static int rtl8169_eth_start(struct udevice *dev) +{ + struct eth_pdata *plat = dev_get_platdata(dev); + + rtl8169_common_start(pci_get_bdf(dev), plat->enetaddr); + + return 0; +} +#else +/************************************************************************** +RESET - Finish setting up the ethernet interface +***************************************************************************/ +static int rtl_reset(struct eth_device *dev, bd_t *bis) +{ + rtl8169_common_start((pci_dev_t)(unsigned long)dev->priv, + dev->enetaddr); + + return 0; +} +#endif /* nCONFIG_DM_ETH */ + +static void rtl_halt_common(unsigned long dev_iobase) +{ + int i; + +#ifdef DEBUG_RTL8169 + printf ("%s\n", __FUNCTION__); +#endif + + ioaddr = dev_iobase; + + /* Stop the chip's Tx and Rx DMA processes. */ + RTL_W8(ChipCmd, 0x00); + + /* Disable interrupts by clearing the interrupt mask. */ + RTL_W16(IntrMask, 0x0000); + + RTL_W32(RxMissed, 0); + + for (i = 0; i < NUM_RX_DESC; i++) { + tpc->RxBufferRing[i] = NULL; + } +} + +#ifdef CONFIG_DM_ETH +void rtl8169_eth_stop(struct udevice *dev) +{ + struct rtl8169_private *priv = dev_get_priv(dev); + + rtl_halt_common(priv->iobase); +} +#else +/************************************************************************** +HALT - Turn off ethernet interface +***************************************************************************/ +static void rtl_halt(struct eth_device *dev) +{ + rtl_halt_common(dev->iobase); +} +#endif + +/************************************************************************** +INIT - Look for an adapter, this routine's visible to the outside +***************************************************************************/ + +#define board_found 1 +#define valid_link 0 +static int rtl_init(unsigned long dev_ioaddr, const char *name, + unsigned char *enetaddr) +{ + static int board_idx = -1; + int i, rc; + int option = -1, Cap10_100 = 0, Cap1000 = 0; + +#ifdef DEBUG_RTL8169 + printf ("%s\n", __FUNCTION__); +#endif + ioaddr = dev_ioaddr; + + board_idx++; + + /* point to private storage */ + tpc = &tpx; + + rc = rtl8169_init_board(ioaddr, name); + if (rc) + return rc; + + /* Get MAC address. FIXME: read EEPROM */ + for (i = 0; i < MAC_ADDR_LEN; i++) + enetaddr[i] = RTL_R8(MAC0 + i); + +#ifdef DEBUG_RTL8169 + printf("chipset = %d\n", tpc->chipset); + printf("MAC Address"); + for (i = 0; i < MAC_ADDR_LEN; i++) + printf(":%02x", enetaddr[i]); + putc('\n'); +#endif + +#ifdef DEBUG_RTL8169 + /* Print out some hardware info */ + printf("%s: at ioaddr 0x%lx\n", name, ioaddr); +#endif + + /* if TBI is not endbled */ + if (!(RTL_R8(PHYstatus) & TBI_Enable)) { + int val = mdio_read(PHY_AUTO_NEGO_REG); + + option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx]; + /* Force RTL8169 in 10/100/1000 Full/Half mode. */ + if (option > 0) { +#ifdef DEBUG_RTL8169 + printf("%s: Force-mode Enabled.\n", dev->name); +#endif + Cap10_100 = 0, Cap1000 = 0; + switch (option) { + case _10_Half: + Cap10_100 = PHY_Cap_10_Half; + Cap1000 = PHY_Cap_Null; + break; + case _10_Full: + Cap10_100 = PHY_Cap_10_Full; + Cap1000 = PHY_Cap_Null; + break; + case _100_Half: + Cap10_100 = PHY_Cap_100_Half; + Cap1000 = PHY_Cap_Null; + break; + case _100_Full: + Cap10_100 = PHY_Cap_100_Full; + Cap1000 = PHY_Cap_Null; + break; + case _1000_Full: + Cap10_100 = PHY_Cap_Null; + Cap1000 = PHY_Cap_1000_Full; + break; + default: + break; + } + mdio_write(PHY_AUTO_NEGO_REG, Cap10_100 | (val & 0x1F)); /* leave PHY_AUTO_NEGO_REG bit4:0 unchanged */ + mdio_write(PHY_1000_CTRL_REG, Cap1000); + } else { +#ifdef DEBUG_RTL8169 + printf("%s: Auto-negotiation Enabled.\n", + dev->name); +#endif + /* enable 10/100 Full/Half Mode, leave PHY_AUTO_NEGO_REG bit4:0 unchanged */ + mdio_write(PHY_AUTO_NEGO_REG, + PHY_Cap_10_Half | PHY_Cap_10_Full | + PHY_Cap_100_Half | PHY_Cap_100_Full | + (val & 0x1F)); + + /* enable 1000 Full Mode */ + mdio_write(PHY_1000_CTRL_REG, PHY_Cap_1000_Full); + + } + + /* Enable auto-negotiation and restart auto-nigotiation */ + mdio_write(PHY_CTRL_REG, + PHY_Enable_Auto_Nego | PHY_Restart_Auto_Nego); + udelay(100); + + /* wait for auto-negotiation process */ + for (i = 10000; i > 0; i--) { + /* check if auto-negotiation complete */ + if (mdio_read(PHY_STAT_REG) & PHY_Auto_Nego_Comp) { + udelay(100); + option = RTL_R8(PHYstatus); + if (option & _1000bpsF) { +#ifdef DEBUG_RTL8169 + printf("%s: 1000Mbps Full-duplex operation.\n", + dev->name); +#endif + } else { +#ifdef DEBUG_RTL8169 + printf("%s: %sMbps %s-duplex operation.\n", + dev->name, + (option & _100bps) ? "100" : + "10", + (option & FullDup) ? "Full" : + "Half"); +#endif + } + break; + } else { + udelay(100); + } + } /* end for-loop to wait for auto-negotiation process */ + + } else { + udelay(100); +#ifdef DEBUG_RTL8169 + printf + ("%s: 1000Mbps Full-duplex operation, TBI Link %s!\n", + dev->name, + (RTL_R32(TBICSR) & TBILinkOK) ? "OK" : "Failed"); +#endif + } + + + tpc->RxDescArray = rtl_alloc_descs(NUM_RX_DESC); + if (!tpc->RxDescArray) + return -ENOMEM; + + tpc->TxDescArray = rtl_alloc_descs(NUM_TX_DESC); + if (!tpc->TxDescArray) + return -ENOMEM; + + return 0; +} + +#ifndef CONFIG_DM_ETH +int rtl8169_initialize(bd_t *bis) +{ + pci_dev_t devno; + int card_number = 0; + struct eth_device *dev; + u32 iobase; + int idx=0; + + while(1){ + unsigned int region; + u16 device; + int err; + + /* Find RTL8169 */ + if ((devno = pci_find_devices(supported, idx++)) < 0) + break; + + pci_read_config_word(devno, PCI_DEVICE_ID, &device); + switch (device) { + case 0x8168: + region = 2; + break; + + default: + region = 1; + break; + } + + pci_read_config_dword(devno, PCI_BASE_ADDRESS_0 + (region * 4), &iobase); + iobase &= ~0xf; + + debug ("rtl8169: REALTEK RTL8169 @0x%x\n", iobase); + + dev = (struct eth_device *)malloc(sizeof *dev); + if (!dev) { + printf("Can not allocate memory of rtl8169\n"); + break; + } + + memset(dev, 0, sizeof(*dev)); + sprintf (dev->name, "RTL8169#%d", card_number); + + dev->priv = (void *)(unsigned long)devno; + dev->iobase = (int)pci_mem_to_phys(devno, iobase); + + dev->init = rtl_reset; + dev->halt = rtl_halt; + dev->send = rtl_send; + dev->recv = rtl_recv; + + err = rtl_init(dev->iobase, dev->name, dev->enetaddr); + if (err < 0) { + printf(pr_fmt("failed to initialize card: %d\n"), err); + free(dev); + continue; + } + + eth_register (dev); + + card_number++; + } + return card_number; +} +#endif + +#ifdef CONFIG_DM_ETH +static int rtl8169_eth_probe(struct udevice *dev) +{ + struct pci_child_platdata *pplat = dev_get_parent_platdata(dev); + struct rtl8169_private *priv = dev_get_priv(dev); + struct eth_pdata *plat = dev_get_platdata(dev); + u32 iobase; + int region; + int ret; + + debug("rtl8169: REALTEK RTL8169 @0x%x\n", iobase); + switch (pplat->device) { + case 0x8168: + region = 2; + break; + default: + region = 1; + break; + } + pci_read_config32(pci_get_bdf(dev), PCI_BASE_ADDRESS_0 + region * 4, + &iobase); + iobase &= ~0xf; + priv->iobase = (int)pci_mem_to_phys(pci_get_bdf(dev), iobase); + + ret = rtl_init(priv->iobase, dev->name, plat->enetaddr); + if (ret < 0) { + printf(pr_fmt("failed to initialize card: %d\n"), ret); + return ret; + } + + return 0; +} + +static const struct eth_ops rtl8169_eth_ops = { + .start = rtl8169_eth_start, + .send = rtl8169_eth_send, + .recv = rtl8169_eth_recv, + .stop = rtl8169_eth_stop, +}; + +static const struct udevice_id rtl8169_eth_ids[] = { + { .compatible = "realtek,rtl8169" }, + { } +}; + +U_BOOT_DRIVER(eth_rtl8169) = { + .name = "eth_rtl8169", + .id = UCLASS_ETH, + .of_match = rtl8169_eth_ids, + .probe = rtl8169_eth_probe, + .ops = &rtl8169_eth_ops, + .priv_auto_alloc_size = sizeof(struct rtl8169_private), + .platdata_auto_alloc_size = sizeof(struct eth_pdata), +}; + +U_BOOT_PCI_DEVICE(eth_rtl8169, supported); +#endif diff --git a/sources/uboot-be550/drivers/net/rtl8221b/Makefile b/sources/uboot-be550/drivers/net/rtl8221b/Makefile new file mode 100644 index 00000000..a25c3485 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8221b/Makefile @@ -0,0 +1,15 @@ +LOC_DIR=/src/init/rtl8221b +LIB=INIT + +include $(PRJ_PATH)/make/config.mk + +SRC_LIST= nic_rtl8226b.c nic_rtl8226b_init.c rtl8226b_mdio.c + +EXTRA_CFLAGS += -Isrc/init/rtl8221b -D_LITTLE_ENDIAN -DMDC_MDIO_OPERATION +EXTRA_CFLAGS += -Iinclude/linux/ + +include $(PRJ_PATH)/make/components.mk +include $(PRJ_PATH)/make/defs.mk +include $(PRJ_PATH)/make/target.mk + +all: dep obj diff --git a/sources/uboot-be550/drivers/net/rtl8221b/nic_rtl8226b.c b/sources/uboot-be550/drivers/net/rtl8221b/nic_rtl8226b.c new file mode 100644 index 00000000..602b0e91 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8221b/nic_rtl8226b.c @@ -0,0 +1,2952 @@ +/* + * Copyright (C) 2019 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : PHY 8226 Driver + * + * Feature : PHY 8226 Driver + * + */ + +#if 0 +//#include "typedef.h" +//#include "rtl8156_mmd.h" +//#include "phy_rtl8226.h" +#include +#include +#include +#include +#include +//#include +#include +#else +#include "rtl8226_typedef.h" +#include "nic_rtl8226b.h" +#include "nic_rtl8226b_init.h" +#endif + + +BOOLEAN +Rtl8226b_phy_reset( + IN HANDLE hDevice + ) +{ + BOOL status = FAILURE; + UINT16 phydata0 = 0, phydata1 = 0; + UINT16 waitcount = 0; + + status = MmdPhyRead(hDevice, MMD_PMAPMD, 0x0, &phydata0); + if (status != SUCCESS) + goto exit; + + phydata1 |= BIT_15; + + status = MmdPhyWrite(hDevice, MMD_PMAPMD, 0x0, phydata1); + if (status != SUCCESS) + goto exit; + + while(TRUE) + { + status = MmdPhyRead(hDevice, MMD_PMAPMD, 0x0, &phydata1); + if (status != SUCCESS) + goto exit; + + if (!(phydata1 & BIT_15)) + break; + + if (++waitcount == 500) + { + status = FAILURE; + goto exit; + } + } + + status = MmdPhyWrite(hDevice, MMD_PMAPMD, 0x0, phydata0); + if (status != SUCCESS) + goto exit; + +exit: + return status; +} + +BOOLEAN +Rtl8226b_autoNegoEnable_get( + IN HANDLE hDevice, + OUT BOOL *pEnable + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + status = MmdPhyRead(hDevice, MMD_AN, 0, &phydata); + if (status != SUCCESS) + goto exit; + + *pEnable = (phydata & BIT_12) ? (TRUE) : (FALSE); + +exit: + return status; +} + +BOOLEAN +Rtl8226b_autoNegoEnable_set( + IN HANDLE hDevice, + IN BOOL Enable + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + // AutoNegotiationEnable + status = MmdPhyRead(hDevice, MMD_AN, 0, &phydata); + if (status != SUCCESS) + goto exit; + + if (Enable) + phydata |= BIT_12; + else + phydata &= (~BIT_12); + + status = MmdPhyWrite(hDevice, MMD_AN, 0, phydata); + if (status != SUCCESS) + goto exit; + + // RestartAutoNegotiation + status = MmdPhyRead(hDevice, MMD_AN, 0, &phydata); + if (status != SUCCESS) + goto exit; + + phydata |= BIT_9; + + status = MmdPhyWrite(hDevice, MMD_AN, 0, phydata); + if (status != SUCCESS) + goto exit; + +exit: + return status; +} + +BOOLEAN +Rtl8226b_autoNegoAbility_get( + IN HANDLE hDevice, + OUT PHY_LINK_ABILITY *pPhyAbility + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + status = MmdPhyRead(hDevice, MMD_AN, 16, &phydata); + if (status != SUCCESS) + goto exit; + + // 10M + pPhyAbility->Half_10 = (phydata & BIT_5) ? (1) : (0); + pPhyAbility->Full_10 = (phydata & BIT_6) ? (1) : (0); + + // 100M + pPhyAbility->Half_100 = (phydata & BIT_7) ? (1) : (0); + pPhyAbility->Full_100 = (phydata & BIT_8) ? (1) : (0); + + pPhyAbility->FC = (phydata & BIT_10) ? (1) : (0); + pPhyAbility->AsyFC = (phydata & BIT_11) ? (1) : (0); + + // 1G + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA412, &phydata); + if (status != SUCCESS) + goto exit; + + pPhyAbility->Full_1000 = (phydata & BIT_9) ? (1) : (0); + + // 2.5G + status = MmdPhyRead(hDevice, MMD_AN, 32, &phydata); + if (status != SUCCESS) + goto exit; + + pPhyAbility->adv_2_5G = (phydata & BIT_7) ? (1) : (0); + +exit: + return status; +} + +BOOLEAN +Rtl8226b_autoNegoAbility_set( + IN HANDLE hDevice, + IN PHY_LINK_ABILITY *pPhyAbility + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + status = MmdPhyRead(hDevice, MMD_AN, 16, &phydata); + if (status != SUCCESS) + goto exit; + + phydata &= (~(BIT_5 | BIT_6 | BIT_7 | BIT_8 | BIT_10 | BIT_11)); + + // 10M + phydata |= (pPhyAbility->Half_10 ? (BIT_5) : (0)); + phydata |= (pPhyAbility->Full_10 ? (BIT_6) : (0)); + + // 100M + phydata |= (pPhyAbility->Half_100 ? (BIT_7) : (0)); + phydata |= (pPhyAbility->Full_100 ? (BIT_8) : (0)); + + phydata |= (pPhyAbility->FC ? (BIT_10) : (0)); + phydata |= (pPhyAbility->AsyFC ? (BIT_11) : (0)); + + status = MmdPhyWrite(hDevice, MMD_AN, 16, phydata); + if (status != SUCCESS) + goto exit; + + // 1G + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA412, &phydata); + if (status != SUCCESS) + goto exit; + + phydata &= (~BIT_9); + + phydata |= (pPhyAbility->Full_1000 ? (BIT_9) : (0)); + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA412, phydata); + if (status != SUCCESS) + goto exit; + + // 2.5G + status = MmdPhyRead(hDevice, MMD_AN, 32, &phydata); + if (status != SUCCESS) + goto exit; + + phydata &= (~BIT_7); + + phydata |= (pPhyAbility->adv_2_5G ? (BIT_7) : (0)); + status = MmdPhyWrite(hDevice, MMD_AN, 32, phydata); + if (status != SUCCESS) + goto exit; + + if (MmdPhyRead(hDevice, MMD_AN, 0, &phydata) == SUCCESS) + { + if (phydata & BIT_12) /* AN_ENABLE */ + { + phydata |= BIT_9; /* RESTART_AN */ + MmdPhyWrite(hDevice, MMD_AN, 0, phydata); + } + } + +exit: + return status; +} + +BOOLEAN +Rtl8226b_duplex_get( + IN HANDLE hDevice, + OUT BOOL *pEnable + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA434, &phydata); + if (status != SUCCESS) + goto exit; + + *pEnable = (phydata & BIT_3) ? (TRUE) : (FALSE); + +exit: + return status; +} + + +BOOLEAN +Rtl8226b_duplex_set( // christy add 0430 + IN HANDLE hDevice, + IN BOOL Enable + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA400, &phydata); + if (status != SUCCESS) + goto exit; + + if (Enable) + phydata |= BIT_8; + else + phydata &= (~BIT_8); + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA400, phydata); + if (status != SUCCESS) + goto exit; + +exit: + return status; +} + + + +BOOLEAN +Rtl8226b_is_link( + IN HANDLE hDevice, + OUT BOOL *plinkOK + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + UINT8 i = 0; + + // must read twice + for(i=0;i<2;i++) + { + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA402, &phydata); + if (status != SUCCESS) + goto exit; + } + + *plinkOK = (phydata & BIT_2) ? (TRUE) : (FALSE); + +exit: + return status; +} + +BOOLEAN +Rtl8226b_speed_get( + IN HANDLE hDevice, + OUT UINT16 *pSpeed + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + UINT8 speed_grp = 0; + UINT8 speed = NO_LINK; + +// int i = 0; + + BOOL linkOK = FALSE; + + status = Rtl8226b_is_link(hDevice, &linkOK); + if (status != SUCCESS) + goto exit; + + if (linkOK) + { + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA434, &phydata); + if (status != SUCCESS) + goto exit; + + speed_grp = (phydata & (BIT_9 | BIT_10)) >> 9; + speed = (phydata & (BIT_4 | BIT_5)) >> 4; + + switch(speed_grp) + { + case 0: + { + switch(speed) + { + case 0: + *pSpeed = LINK_SPEED_10M; + break; + case 1: + *pSpeed = LINK_SPEED_100M; + break; + case 2: + *pSpeed = LINK_SPEED_1G; + break; + case 3: + *pSpeed = LINK_SPEED_500M; + break; + + default: + status = FAILURE; + break; + } + break; + } + + case 1: + { + switch(speed) + { + case 1: + *pSpeed = LINK_SPEED_2P5G; + break; + case 3: + *pSpeed = LINK_SPEED_1G; // 2.5G lite + break; + default: + status = FAILURE; + break; + } + break; + } + + default: + status = FAILURE; + break; + } + } + else + { + *pSpeed = NO_LINK; + } + +exit: + return status; +} + +BOOLEAN +Rtl8226b_enable_set( + IN HANDLE hDevice, + IN BOOL Enable + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + status = MmdPhyRead(hDevice, MMD_PMAPMD, 0, &phydata); + if (status != SUCCESS) + goto exit; + + if (Enable) + phydata &= (~BIT_11); // set as 0 + else + phydata |= BIT_11; // set as 1 + + + status = MmdPhyWrite(hDevice, MMD_PMAPMD, 0, phydata); + if (status != SUCCESS) + goto exit; + +exit: + return status; +} + +BOOLEAN +Rtl8226b_force_speed_set( + IN HANDLE hDevice, + IN UINT16 Speed + ) +{ + BOOL status = FAILURE; + UINT16 phydata0 = 0, phydata1 = 0; + BOOL support = 0; + + status = MmdPhyRead(hDevice, MMD_PMAPMD, 0, &phydata0); + if (status != SUCCESS) + goto exit; + + phydata0 &= (~(BIT_6 | BIT_13)); + + switch(Speed) + { + case 10: + support = TRUE; + phydata0 &= (~BIT_6); + phydata0 &= (~BIT_13); + break; + + case 100: + support = TRUE; + phydata0 &= (~BIT_6); + phydata0 |= BIT_13; + break; + + + + default: + status = FAILURE; + support = FALSE; + break; + } + + if (support) + { + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA5B4, &phydata1); + if (status != SUCCESS) + goto exit; + + phydata1 |= (BIT_15); + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA5B4, phydata1); + if (status != SUCCESS) + goto exit; + + status = MmdPhyWrite(hDevice, MMD_PMAPMD, 0, phydata0); + if (status != SUCCESS) + goto exit; + + status = Rtl8226b_autoNegoEnable_set(hDevice, FALSE); + if (status != SUCCESS) + goto exit; + } + else + status = FAILURE; + +exit: + return status; +} + +BOOLEAN +Rtl8226b_force_speed_get( + IN HANDLE hDevice, + OUT UINT16 *force_speed + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + BOOL AnEnable = 0; + + status = Rtl8226b_autoNegoEnable_get(hDevice, &AnEnable); + if (status != SUCCESS) + goto exit; + + + + if(AnEnable==0) + { + status = MmdPhyRead(hDevice, MMD_PMAPMD, 0, &phydata); + if (status != SUCCESS) + goto exit; + + if(((phydata & (BIT_6))==0 )&&((phydata & (BIT_13))==0)) + *force_speed = LINK_SPEED_10M; + + else if(((phydata &(BIT_6))==0 )&&((phydata & (BIT_13))==BIT_13)) + *force_speed = LINK_SPEED_100M; + else + *force_speed = NO_LINK; + + } + else + status = FAILURE; + +exit: + return status; +} + + + + + +BOOLEAN +Rtl8226b_greenEnable_get( + IN HANDLE hDevice, + OUT BOOL *pEnable + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA436, 0x8011); + if (status != SUCCESS) + goto exit; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA438, &phydata); + if (status != SUCCESS) + goto exit; + + *pEnable = (phydata & BIT_15) ? (TRUE) : (FALSE); + +exit: + return status; +} + +BOOLEAN +Rtl8226b_greenEnable_set( + IN HANDLE hDevice, + IN BOOL Enable + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA436, 0x8011); + if (status != SUCCESS) + goto exit; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA438, &phydata); + if (status != SUCCESS) + goto exit; + + if (Enable) + phydata |= (BIT_15); + else + phydata &= (~BIT_15); + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA438, phydata); + if (status != SUCCESS) + goto exit; + +exit: + return status; +} + + + + +BOOLEAN +Rtl8226b_eeeEnable_get( + IN HANDLE hDevice, + OUT PHY_EEE_ENABLE *pEeeEnable + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + status = MmdPhyRead(hDevice, MMD_AN, 60, &phydata); + if (status != SUCCESS) + goto exit; + + pEeeEnable->EEE_100 = (phydata & BIT_1) ? (TRUE) : (FALSE); + pEeeEnable->EEE_1000 = (phydata & BIT_2) ? (TRUE) : (FALSE); + + status = MmdPhyRead(hDevice, MMD_AN, 62, &phydata); + if (status != SUCCESS) + goto exit; + + pEeeEnable->EEE_2_5G = (phydata & BIT_0) ? (TRUE) : (FALSE); + +exit: + return status; +} + +BOOLEAN +Rtl8226b_eeeEnable_set( + IN HANDLE hDevice, + IN PHY_EEE_ENABLE *pEeeEnable + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + BOOL AnEnable = 0; + + status = Rtl8226b_autoNegoEnable_get(hDevice, &AnEnable); + if (status != SUCCESS) + goto exit; + + // 100M/1G EEE + status = MmdPhyRead(hDevice, MMD_AN, 60, &phydata); + if (status != SUCCESS) + goto exit; + + if (pEeeEnable->EEE_100) + phydata |= BIT_1; + else + phydata &= (~BIT_1); + + + if (pEeeEnable->EEE_1000) + phydata |= BIT_2; + else + phydata &= (~BIT_2); + + status = MmdPhyWrite(hDevice, MMD_AN, 60, phydata); + if (status != SUCCESS) + goto exit; + + // 2.5G EEE + status = MmdPhyRead(hDevice, MMD_AN, 62, &phydata); + if (status != SUCCESS) + goto exit; + + if (pEeeEnable->EEE_2_5G) + phydata |= BIT_0; + else + phydata &= (~BIT_0); + + status = MmdPhyWrite(hDevice, MMD_AN, 62, phydata); + if (status != SUCCESS) + goto exit; + + // RestartAutoNegotiation + if (AnEnable) + { + status = MmdPhyRead(hDevice, MMD_AN, 0, &phydata); + if (status != SUCCESS) + goto exit; + + phydata |= BIT_9; + + status = MmdPhyWrite(hDevice, MMD_AN, 0, phydata); + if (status != SUCCESS) + goto exit; + } + +exit: + return status; +} + + + + + +BOOLEAN +Rtl8226b_PHYmodeEEE_set(IN HANDLE hDevice,int on_off) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + if(on_off){ + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA432, &phydata); + if (status != SUCCESS) + goto exit; + + phydata |= BIT_5; + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA432, phydata); + if (status != SUCCESS) + goto exit; + + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA4A8, &phydata); + if (status != SUCCESS) + goto exit; + + phydata |= BIT_10; + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA4A8, phydata); + if (status != SUCCESS) + goto exit; + + + + + } + else{ + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA432, &phydata); + if (status != SUCCESS) + goto exit; + + phydata &= (~BIT_5); + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA432, phydata); + if (status != SUCCESS) + goto exit; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA4A8, &phydata); + if (status != SUCCESS) + goto exit; + + phydata &= (~ BIT_10); + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA4A8, phydata); + if (status != SUCCESS) + goto exit; + + + + } + + status = MmdPhyRead(hDevice, MMD_AN, 0, &phydata); + if (status != SUCCESS) + goto exit; + + phydata |= BIT_9; + + status = MmdPhyWrite(hDevice, MMD_AN, 0, phydata); + if (status != SUCCESS) + goto exit; + + + + +exit: + return status; + + +} + +BOOLEAN +Rtl8226b_10M_PHYmodeEEEP_set(IN HANDLE hDevice,int on_off) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + if(on_off){ + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA432, &phydata); + if (status != SUCCESS) + goto exit; + + phydata |= BIT_2; + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA432, phydata); + if (status != SUCCESS) + goto exit; + + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xC842, &phydata); + if (status != SUCCESS) + goto exit; + + phydata |= BIT_2; + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xC842, phydata); + if (status != SUCCESS) + goto exit; + + + + + + } + else{ + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA432, &phydata); + if (status != SUCCESS) + goto exit; + + phydata &= (~BIT_2); + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA432, phydata); + if (status != SUCCESS) + goto exit; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xC842, &phydata); + if (status != SUCCESS) + goto exit; + + phydata &= (~BIT_2); + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xC842, phydata); + if (status != SUCCESS) + goto exit; + + } + + status = MmdPhyRead(hDevice, MMD_AN, 0, &phydata); + if (status != SUCCESS) + goto exit; + + phydata |= BIT_9; + + status = MmdPhyWrite(hDevice, MMD_AN, 0, phydata); + if (status != SUCCESS) + goto exit; + + + + +exit: + return status; + + +} + + + + +BOOLEAN +Rtl8226b_crossOverMode_get( + IN HANDLE hDevice, + OUT PHY_CROSSPVER_MODE *CrossOverMode + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA430, &phydata); + if (status != SUCCESS) + goto exit; + + if((phydata & BIT_9) >> 9) + { + switch((phydata & BIT_8) >> 8) + { + case 1: + *CrossOverMode = PHY_CROSSPVER_MODE_MDI; + break; + case 0: + *CrossOverMode = PHY_CROSSPVER_MODE_MDIX; + break; + default: + status = FAILURE; + break; + } + } + else + *CrossOverMode = PHY_CROSSPVER_MODE_AUTO; + +exit: + return status; +} + +BOOLEAN +Rtl8226b_crossOverMode_set( + IN HANDLE hDevice, + IN PHY_CROSSPVER_MODE CrossOverMode + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA430, &phydata); + if (status != SUCCESS) + goto exit; + + phydata &= (~(BIT_8 | BIT_9)); + + switch(CrossOverMode) + { + case PHY_CROSSPVER_MODE_MDI: + phydata |= (BIT_8 | BIT_9); + break; + case PHY_CROSSPVER_MODE_MDIX: + phydata |= BIT_9; + break; + case PHY_CROSSPVER_MODE_AUTO: + break; + default: + status = FAILURE; + goto exit; + } + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA430, phydata); + if (status != SUCCESS) + goto exit; + if (CrossOverMode != PHY_CROSSPVER_MODE_AUTO) + { + // RestartAutoNegotiation + status = MmdPhyRead(hDevice, MMD_AN, 0, &phydata); + if (status != SUCCESS) + goto exit; + + phydata |= BIT_9; + + status = MmdPhyWrite(hDevice, MMD_AN, 0, phydata); + if (status != SUCCESS) + goto exit; + } +exit: + return status; +} + +BOOLEAN +Rtl8226b_crossOverStatus_get( + IN HANDLE hDevice, + OUT PHY_CROSSPVER_STATUS *pCrossOverStatus + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA434, &phydata); + if (status != SUCCESS) + goto exit; + + *pCrossOverStatus = (phydata & BIT_1) ? (PHY_CROSSPVER_STATUS_MDI) : (PHY_CROSSPVER_STATUS_MDIX); + +exit: + return status; +} + +BOOLEAN +Rtl8226b_masterSlave_get( + IN HANDLE hDevice, + OUT PHY_MASTERSLAVE_MODE *MasterSlaveMode + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + status = MmdPhyRead(hDevice, MMD_AN, 33, &phydata); + if (status != SUCCESS) + goto exit; + + switch((phydata >> 14) & 0x3) + { + case 0: // 0:Slave, 1:Master + *MasterSlaveMode = PHY_SLAVE_MODE; + break; + case 1: + *MasterSlaveMode = PHY_MASTER_MODE; + break; + default: + status = FAILURE; + break; + } + +exit: + return status; +} + +BOOLEAN +Rtl8226b_masterSlave_set( + IN HANDLE hDevice, + IN PHY_MASTERSLAVE_MODE MasterSlaveMode + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + status = MmdPhyRead(hDevice, MMD_AN, 32, &phydata); + if (status != SUCCESS) + goto exit; + + phydata &= (~(BIT_14 | BIT_15)); + + switch(MasterSlaveMode) + { + case PHY_AUTO_MODE: + break; + case PHY_SLAVE_MODE: + phydata |= BIT_15; + break; + case PHY_MASTER_MODE: + phydata |= (BIT_14 | BIT_15); + break; + default: + status = FAILURE; + goto exit; + } + + status = MmdPhyWrite(hDevice, MMD_AN, 32, phydata); + if (status != SUCCESS) + goto exit; + +exit: + return status; +} + +BOOLEAN +Rtl8226b_loopback_get( + IN HANDLE hDevice, + OUT BOOL *pEnable + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + status = MmdPhyRead(hDevice, MMD_PCS, 0x0, &phydata); + if (status != SUCCESS) + goto exit; + + *pEnable = (phydata & BIT_14) ? (TRUE) : (FALSE); + +exit: + return status; +} + +BOOLEAN +Rtl8226b_loopback_set( + IN HANDLE hDevice, + IN BOOL Enable + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + status = MmdPhyRead(hDevice, MMD_PCS, 0x0, &phydata); + if (status != SUCCESS) + goto exit; + + if (Enable) + phydata |= BIT_14; + else + phydata &= (~BIT_14); + + status = MmdPhyWrite(hDevice, MMD_PCS, 0x0, phydata); + if (status != SUCCESS) + goto exit; + +exit: + return status; +} + +BOOLEAN +Rtl8226b_downSpeedEnable_get( + IN HANDLE hDevice, + OUT BOOL *pEnable + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA442, &phydata); + if (status != SUCCESS) + goto exit; + + *pEnable = (phydata & BIT_3) ? (TRUE) : (FALSE); + +exit: + return status; +} + +BOOLEAN +Rtl8226b_downSpeedEnable_set( + IN HANDLE hDevice, + IN BOOL Enable + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA442, &phydata); + if (status != SUCCESS) + goto exit; + + phydata &= (~BIT_5); + + if (Enable) + phydata |= BIT_3; + else + phydata &= (~BIT_3); + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA442, phydata); + if (status != SUCCESS) + goto exit; + +exit: + return status; +} + +BOOLEAN +Rtl8226b_gigaLiteEnable_get( + IN HANDLE hDevice, + OUT BOOL *pEnable + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA428, &phydata); + if (status != SUCCESS) + goto exit; + + *pEnable = (phydata & BIT_9) ? (TRUE) : (FALSE); + +exit: + return status; +} + +BOOLEAN +Rtl8226b_gigaLiteEnable_set( + IN HANDLE hDevice, + IN BOOL Enable + ) +{ + BOOL status = FAILURE; + UINT16 phydata0 = 0, phydata1 = 0; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA442, &phydata0); + if (status != SUCCESS) + goto exit; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA428, &phydata1); + if (!status) + goto exit; + + if (Enable) + { + phydata0 |= (BIT_2 | BIT_9); + phydata1 |= BIT_9; + } + else + { + phydata0 &= (~(BIT_2 | BIT_9)); + phydata1 &= (~BIT_9); + } + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA442, phydata0); + if (status != SUCCESS) + goto exit; + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA428, phydata1); + if (status != SUCCESS) + goto exit; + +exit: + return status; +} + + + + +BOOLEAN +Rtl8226b_mdiSwapEnable_get( + IN HANDLE hDevice, + OUT BOOL *pEnable + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + status = MmdPhyRead(hDevice, MMD_VEND1, 0x6A21, &phydata); + if (status != SUCCESS) + goto exit; + + *pEnable = (phydata & BIT_5) ? (TRUE) : (FALSE); + +exit: + return status; +} + +BOOLEAN +Rtl8226b_mdiSwapEnable_set( + IN HANDLE hDevice, + IN BOOL Enable + ) +{ + BOOL status = FAILURE; + UINT16 phydata0 = 0; + + status = MmdPhyRead(hDevice, MMD_VEND1, 0x6A21, &phydata0); + if (status != SUCCESS) + goto exit; + + if (Enable) + { + phydata0 |= (BIT_5); + } + else + { + phydata0 &= (~(BIT_5)); + } + + status = MmdPhyWrite(hDevice, MMD_VEND1, 0x6A21, phydata0); + if (status != SUCCESS) + goto exit; + + +exit: + return status; +} + + + + +BOOLEAN +Rtl8226b_rtct_start( + IN HANDLE hDevice + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + BOOL linkOK; + UINT16 Speed; + + status = Rtl8226b_is_link(hDevice, &linkOK); + if (status != SUCCESS) + goto exit; + + if (linkOK) + { + status = Rtl8226b_speed_get(hDevice, &Speed); + if (status != SUCCESS) + goto exit; + + //RTCT is not supported when port link at 10M. + if (Speed == 10) + { +#if 0 + osal_printf("RTCT is not supported when port link at 10M.\n"); +#else + printf("RTCT is not supported when port link at 10M.\n"); +#endif + status = FAILURE; + goto exit; + } + } + else + { + // MMD 31.0xA422[15] = 0 // clear rtct_done + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA422, &phydata); + if (status != SUCCESS) + goto exit; + + phydata &= (~BIT_15); + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA422, phydata); + if (status != SUCCESS) + goto exit; + + // wait 1ms for chip reset the states +#if 0 + Sleep(1); +#else + SLEEP_1MS; +#endif + + // MMD 31.0xA422[4] = 1 // RTCT_CH_A + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA422, &phydata); + if (status != SUCCESS) + goto exit; + + phydata |= (BIT_4); + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA422, phydata); + if (status != SUCCESS) + goto exit; + + // MMD 31.0xA422[5] = 1 // RTCT_CH_B + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA422, &phydata); + if (status != SUCCESS) + goto exit; + + phydata |= (BIT_5); + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA422, phydata); + if (status != SUCCESS) + goto exit; + + // MMD 31.0xA422[6] = 1 // RTCT_CH_C + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA422, &phydata); + if (status != SUCCESS) + goto exit; + + phydata |= (BIT_6); + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA422, phydata); + if (status != SUCCESS) + goto exit; + + // MMD 31.0xA422[7] = 1 // RTCT_CH_D + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA422, &phydata); + if (status != SUCCESS) + goto exit; + + phydata |= (BIT_7); + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA422, phydata); + if (status != SUCCESS) + goto exit; + + // MMD 31.0xA422[0] = 1 // RTCT_ENABLE + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA422, &phydata); + if (status != SUCCESS) + goto exit; + + phydata |= (BIT_0); + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA422, phydata); + if (status != SUCCESS) + goto exit; + } + +exit: + return status; +} + +BOOLEAN +Rtl8226b_rtctResult_convert( + IN UINT16 phydata, + OUT PHY_RTCT_STATUS *pRtctStatus + ) +{ + BOOL status = SUCCESS; + + switch(phydata) + { + case 0x60: // Normal + break; + case 0x48: + pRtctStatus->Open = TRUE; + break; + case 0x50: + pRtctStatus->Short = TRUE; + break; + case 0x42: + pRtctStatus->Mismatch = MIS_MATCH_OPEN; + break; + case 0x44: + pRtctStatus->Mismatch = MIS_MATCH_SHORT; + break; + + default: + status = FAILURE; + break; + } + + return status; +} + +BOOLEAN +Rtl8226b_rtctResult_get( + IN HANDLE hDevice, + OUT PHY_RTCT_RESULT *pRtctResult + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + BOOL linkOK = FALSE; + + UINT16 Speed = NO_LINK; + + BOOL rtct_done; + + status = Rtl8226b_is_link(hDevice, &linkOK); + if (status != SUCCESS) + goto exit; + + if (linkOK) + { + status = Rtl8226b_speed_get(hDevice, &Speed); + if (status != SUCCESS) + goto exit; + + pRtctResult->linkType = Speed; + if (Speed == 10) + { +#if 0 + osal_printf("RTCT is not supported when port link at 10M.\n"); +#else + printf("RTCT is not supported when port link at 10M.\n"); +#endif + status = FAILURE; + goto exit; + } + switch(Speed) + { + case LINK_SPEED_100M: + // rxLen = MMD 31.0xA880[7:0] * 100 // unit is meter + // txLen = MMD 31.0xA880[7:0] * 100 + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA880, &phydata); + if (status != SUCCESS) + goto exit; + + pRtctResult->rxLen = (phydata & 0xff) * 100; + pRtctResult->txLen = (phydata & 0xff) * 100; + break; + + case LINK_SPEED_1G: + // channelALen = MMD 31.0xA880[7:0] * 100 // unit is meter + // channelBLen = MMD 31.0xA880[7:0] * 100 + // channelCLen = MMD 31.0xA880[7:0] * 100 + // channelDLen = MMD 31.0xA880[7:0] * 100 + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA880, &phydata); + if (status != SUCCESS) + goto exit; + + pRtctResult->channelALen = (phydata & 0xff) * 100; + pRtctResult->channelBLen = (phydata & 0xff) * 100; + pRtctResult->channelCLen = (phydata & 0xff) * 100; + pRtctResult->channelDLen = (phydata & 0xff) * 100; + break; + + case LINK_SPEED_2P5G: + //channelALen = MMD 31.0xACBA[9:2] * 100 // cablen for XG + status = MmdPhyRead(hDevice, MMD_VEND2, 0xACBA, &phydata); + if (status != SUCCESS) + goto exit; + + pRtctResult->channelALen = ((phydata & 0x3fc) >> 2 ) * 100; + pRtctResult->channelBLen = ((phydata & 0x3fc) >> 2 ) * 100; + pRtctResult->channelCLen = ((phydata & 0x3fc) >> 2 ) * 100; + pRtctResult->channelDLen = ((phydata & 0x3fc) >> 2 ) * 100; + break; + + //RTCT is not supported when port link at 10M. + default: + status = FAILURE; + break; + } + } + else + { + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA422, &phydata); + if (status != SUCCESS) + goto exit; + + rtct_done = (phydata & BIT_15) ? (TRUE) : (FALSE); + if (!rtct_done) + { + status = FAILURE; + goto exit; + } + + // MMD 31.0A436[15:0] = 0x8029 + // phyData = read MMD 31.0A438[15:0] + // channelALen = phyData * 100 / 80 + // channelALen (unit: cm) + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA436, 0x8029); + if (status != SUCCESS) + goto exit; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0x0A438, &phydata); + if (status != SUCCESS) + goto exit; + + pRtctResult->channelALen = (phydata * 100) / 80; + + // MMD 31.0A436[15:0] = 0x802D + // phyData = read MMD 31.0A438[15:0] + // channelBLen = phyData * 100 / 80 + // channelBLen (unit: cm) + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA436, 0x802D); + if (status != SUCCESS) + goto exit; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0x0A438, &phydata); + if (status != SUCCESS) + goto exit; + + pRtctResult->channelBLen = (phydata * 100) / 80; + + // MMD 31.0A436[15:0] = 0x8031 + // phyData = read MMD 31.0A438[15:0] + // channelCLen = phyData * 100 / 80 + // channelCLen (unit: cm) + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA436, 0x8031); + if (status != SUCCESS) + goto exit; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0x0A438, &phydata); + if (status != SUCCESS) + goto exit; + + pRtctResult->channelCLen = (phydata * 100) / 80; + + // MMD 31.0A436[15:0] = 0x8035 + // phyData = read MMD 31.0A438[15:0] + // channelDLen = phyData * 100 / 80 + // channelDLen (unit: cm) + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA436, 0x8035); + if (status != SUCCESS) + goto exit; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0x0A438, &phydata); + if (status != SUCCESS) + goto exit; + + pRtctResult->channelDLen = (phydata * 100) / 80; + + // channelA status + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA436, 0x8027); + if (status != SUCCESS) + goto exit; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0x0A438, &phydata); + if (status != SUCCESS) + goto exit; + + status = Rtl8226b_rtctResult_convert(phydata, &pRtctResult->channelAStatus); + if (status != SUCCESS) + goto exit; + + // channelA status + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA436, 0x802B); + if (status != SUCCESS) + goto exit; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0x0A438, &phydata); + if (status != SUCCESS) + goto exit; + + status = Rtl8226b_rtctResult_convert(phydata, &pRtctResult->channelBStatus); + if (status != SUCCESS) + goto exit; + + // channelC status + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA436, 0x802F); + if (status != SUCCESS) + goto exit; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0x0A438, &phydata); + if (status != SUCCESS) + goto exit; + + status = Rtl8226b_rtctResult_convert(phydata, &pRtctResult->channelCStatus); + if (status != SUCCESS) + goto exit; + + // channelD status + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA436, 0x8033); + if (status != SUCCESS) + goto exit; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0x0A438, &phydata); + if (status != SUCCESS) + goto exit; + + status = Rtl8226b_rtctResult_convert(phydata, &pRtctResult->channelDStatus); + if (status != SUCCESS) + goto exit; + } + +exit: + return status; +} + + + + +BOOLEAN +Rtl8226b_rtctdone_get( + IN HANDLE hDevice, + OUT BOOL *prtct_done + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA422, &phydata); + if (status != SUCCESS) + goto exit; + + *prtct_done = (phydata & BIT_15) ? (TRUE) : (FALSE); + +exit: + return status; +} + + + + +BOOLEAN +Rtl8226b_linkDownPowerSavingEnable_get( + IN HANDLE hDevice, + OUT BOOL *pEnable + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA430, &phydata); + if (status != SUCCESS) + goto exit; + + *pEnable = (phydata & BIT_2) ? (TRUE) : (FALSE); + +exit: + return status; +} + +BOOLEAN +Rtl8226b_linkDownPowerSavingEnable_set( + IN HANDLE hDevice, + IN BOOL Enable + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA430, &phydata); + if (status != SUCCESS) + goto exit; + + if (Enable) + phydata |= BIT_2; + else + phydata &= (~BIT_2); + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA430, phydata); + if (status != SUCCESS) + goto exit; + +exit: + return status; +} + +BOOLEAN +Rtl8226b_2p5gLiteEnable_get( + IN HANDLE hDevice, + OUT BOOL *pEnable + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA5EA, &phydata); + if (status != SUCCESS) + goto exit; + + *pEnable = (phydata & BIT_0) ? (TRUE) : (FALSE); + +exit: + return status; +} + +BOOLEAN +Rtl8226b_2p5gLiteEnable_set( + IN HANDLE hDevice, + IN BOOL Enable + ) +{ + BOOL status = FAILURE; + UINT16 phydata0 = 0, phydata1 = 0, phydata2 = 0; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA442, &phydata0); + if (status != SUCCESS) + goto exit; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA5FA, &phydata1); + if (status != SUCCESS) + goto exit; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA5EA, &phydata2); + if (status != SUCCESS) + goto exit; + + phydata0 &= (~BIT_2); + phydata1 &= (~BIT_1); + phydata2 &= (~BIT_0); + + if (Enable) + { + phydata0 |= BIT_2; + phydata1 |= BIT_1; + phydata2 |= BIT_0; + } + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA442, phydata0); + if (status != SUCCESS) + goto exit; + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA5FA, phydata1); + if (status != SUCCESS) + goto exit; + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA5EA, phydata2); + if (status != SUCCESS) + goto exit; + +exit: + return status; +} + +BOOLEAN +Rtl8226b_ThermalSensorEnable_get( + IN HANDLE hDevice, + OUT BOOL *pEnable + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA436, 0x817D); + if (status != SUCCESS) + goto exit; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA438, &phydata); + if (status != SUCCESS) + goto exit; + + *pEnable = (phydata & BIT_12) ? (TRUE) : (FALSE); + +exit: + return status; +} + +BOOLEAN +Rtl8226b_ThermalSensorEnable_set( + IN HANDLE hDevice, + IN BOOL Enable, + IN UINT16 threshold + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA436, 0x817D); + if (status != SUCCESS) + goto exit; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA438, &phydata); + if (status != SUCCESS) + goto exit; + + if (Enable) + phydata |= BIT_12; + else + phydata &= (~BIT_12); + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA438, phydata); + if (status != SUCCESS) + goto exit; + + //Set the thermal thershold, default = 120 degree C + if(threshold <= 120) + { + status = MmdPhyRead(hDevice, MMD_VEND2, 0xB54C, &phydata); + if (status != SUCCESS) + goto exit; + + phydata &= (~(BIT_15 | BIT_14 | BIT_13 | BIT_12 | BIT_11 | BIT_10 | BIT_9 | BIT_8 | BIT_7 | BIT_6)); + phydata |= ((threshold * 2) << 6); + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xB54C, phydata); + if (status != SUCCESS) + goto exit; + }else + { + status = FAILURE; + } + + +exit: + return status; +} + +BOOLEAN +Rtl8226b_ieeeTestMode_set( + IN HANDLE hDevice, + IN UINT16 Speed, + IN PHY_IEEE_TEST_MODE *pIEEEtestmode + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0, phydata_w = 0, phydata2 = 0; + + switch(Speed) + { + case LINK_SPEED_10M: + { + //initial setting + //Write MMD1, reg 0x0000, data=0x0000 + status = MmdPhyWrite(hDevice, MMD_PMAPMD, 0x0000, 0x0000); + if (status != SUCCESS) + goto exit; + + // wait 1ms +#if 0 + Sleep(1); +#else + SLEEP_1MS; +#endif + + //Write MMD7, reg 0x0000, bit[12]=0x0 + status = MmdPhyRead(hDevice, MMD_AN, 0x0000, &phydata); + if (status != SUCCESS) + goto exit; + + phydata &= (~BIT_12); + + status = MmdPhyWrite(hDevice, MMD_AN, 0x0000, phydata); + if (status != SUCCESS) + goto exit; + + // wait 1ms +#if 0 + Sleep(1); +#else + SLEEP_1MS; +#endif + + //Write MMD31, reg 0xA412, bit[15:13]=0x0 + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA412, &phydata); + if (status != SUCCESS) + goto exit; + + phydata &= (~(BIT_15 | BIT_14 | BIT_13)); + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA412, phydata); + if (status != SUCCESS) + goto exit; + + // wait 1ms +#if 0 + Sleep(1); +#else + SLEEP_1MS; +#endif + + if(pIEEEtestmode -> channel == TESTMODE_CHANNEL_A) + Rtl8226b_crossOverMode_set(hDevice,PHY_CROSSPVER_MODE_MDI); + else if(pIEEEtestmode -> channel == TESTMODE_CHANNEL_B) + Rtl8226b_crossOverMode_set(hDevice,PHY_CROSSPVER_MODE_MDIX); + + if(pIEEEtestmode -> NORMAL) + { + //Write MMD31, reg 0xC804, data=0x0115 + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xC804, 0x0115); + if (status != SUCCESS) + goto exit; + + //Write MMD31, reg 0xC800, data=0x5a21 + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xC800, 0x5a21); + if (status != SUCCESS) + goto exit; + } + + if(pIEEEtestmode -> HARMONIC) + { + //Write MMD31, reg 0xC804, data=0x0015 + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xC804, 0x0015); + if (status != SUCCESS) + goto exit; + + //Write MMD31, reg 0xC800, data=0xff21 + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xC800, 0xff21); + if (status != SUCCESS) + goto exit; + } + + if(pIEEEtestmode -> LINKPLUSE) + { + //Write MMD31, reg 0xC804, data=0x0115 + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xC804, 0x0115); + if (status != SUCCESS) + goto exit; + + //Write MMD31, reg 0xC800, data=0x5a00 + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xC800, 0x5a00); + if (status != SUCCESS) + goto exit; + } + + if (pIEEEtestmode->TMFINISH) + { + //MMD31, reg 0xA430, bit[9:8]=0x0 + Rtl8226b_crossOverMode_set(hDevice,PHY_CROSSPVER_MODE_AUTO); + + // wait 1ms +#if 0 + Sleep(1); +#else + SLEEP_1MS; +#endif + + //Write MMD31, reg 0xC804, data=0x0115 + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xC804, 0x0115); + if (status != SUCCESS) + goto exit; + + // wait 1ms +#if 0 + Sleep(1); +#else + SLEEP_1MS; +#endif + + //Write MMD31, reg 0xC800, data=0x5a00 + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xC800, 0x5a00); + if (status != SUCCESS) + goto exit; + + // wait 1ms +#if 0 + Sleep(1); +#else + SLEEP_1MS; +#endif + + //Write MMD7, reg 0x0000, bit[12]=0x1 + status = MmdPhyRead(hDevice, MMD_AN, 0x0000, &phydata); + if (status != SUCCESS) + goto exit; + + phydata |= BIT_12; + + status = MmdPhyWrite(hDevice, MMD_AN, 0x0000, phydata); + if (status != SUCCESS) + goto exit; + // wait 1ms +#if 0 + Sleep(1); +#else + SLEEP_1MS; +#endif + + //Write MMD1, reg 0x0000, bit[15]=0x1, PMA reset + status = MmdPhyRead(hDevice, MMD_PMAPMD, 0x0000, &phydata); + if (status != SUCCESS) + goto exit; + + phydata |= BIT_15; + + status = MmdPhyWrite(hDevice, MMD_PMAPMD, 0x0000, phydata); + if (status != SUCCESS) + goto exit; + } + + break; + } + case LINK_SPEED_100M: + { + //initial setting + //Write MMD1, reg 0x0000, data=0x2000 + status = MmdPhyWrite(hDevice, MMD_PMAPMD, 0x0000, 0x2000); + if (status != SUCCESS) + goto exit; + // wait 1ms +#if 0 + Sleep(1); +#else + SLEEP_1MS; +#endif + + //Write MMD7, reg 0x0000, bit[12]=0x0 + status = MmdPhyRead(hDevice, MMD_AN, 0x0000, &phydata); + if (status != SUCCESS) + goto exit; + + phydata &= (~BIT_12); + + status = MmdPhyWrite(hDevice, MMD_AN, 0x0000, phydata); + if (status != SUCCESS) + goto exit; + // wait 1ms +#if 0 + Sleep(1); +#else + SLEEP_1MS; +#endif + + //Write MMD31, reg 0xA412, bit[15:13]=0x0 + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA412, &phydata); + if (status != SUCCESS) + goto exit; + + phydata &= (~(BIT_15 | BIT_14 | BIT_13)); + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA412, phydata); + if (status != SUCCESS) + goto exit; + + // wait 1ms +#if 0 + Sleep(1); +#else + SLEEP_1MS; +#endif + + if(pIEEEtestmode -> channel == TESTMODE_CHANNEL_A) + Rtl8226b_crossOverMode_set(hDevice,PHY_CROSSPVER_MODE_MDI); + else if(pIEEEtestmode -> channel == TESTMODE_CHANNEL_B) + Rtl8226b_crossOverMode_set(hDevice,PHY_CROSSPVER_MODE_MDIX); + + + if (pIEEEtestmode->TMFINISH) + { + //MMD31, reg 0xA430, bit[9:8]=0x0 + Rtl8226b_crossOverMode_set(hDevice,PHY_CROSSPVER_MODE_AUTO); + + // wait 1ms +#if 0 + Sleep(1); +#else + SLEEP_1MS; +#endif + + //Write MMD7, reg 0x0000, bit[12]=0x1 + status = MmdPhyRead(hDevice, MMD_AN, 0x0000, &phydata); + if (status != SUCCESS) + goto exit; + + phydata |= BIT_12; + + status = MmdPhyWrite(hDevice, MMD_AN, 0x0000, phydata); + if (status != SUCCESS) + goto exit; + // wait 1ms +#if 0 + Sleep(1); +#else + SLEEP_1MS; +#endif + + //Write MMD1, reg 0x0000, bit[15]=0x1, PMA reset + status = MmdPhyRead(hDevice, MMD_PMAPMD, 0x0000, &phydata); + if (status != SUCCESS) + goto exit; + + phydata |= BIT_15; + + status = MmdPhyWrite(hDevice, MMD_PMAPMD, 0x0000, phydata); + if (status != SUCCESS) + goto exit; + } + + break; + } + case LINK_SPEED_1G: + { + //initial setting + //Write MMD1, reg 0x0000, bit[15]=0x1, PMA reset + status = MmdPhyRead(hDevice, MMD_PMAPMD, 0x0000, &phydata); + if (status != SUCCESS) + goto exit; + + phydata |= BIT_15; + + status = MmdPhyWrite(hDevice, MMD_PMAPMD, 0x0000, phydata); + if (status != SUCCESS) + goto exit; + // wait 1ms +#if 0 + Sleep(1); +#else + SLEEP_1MS; +#endif + + //Write MMD7, reg 0x0000, bit[12]=0x1 + status = MmdPhyRead(hDevice, MMD_AN, 0x0000, &phydata); + if (status != SUCCESS) + goto exit; + + phydata |= BIT_12; + + status = MmdPhyWrite(hDevice, MMD_AN, 0x0000, phydata); + if (status != SUCCESS) + goto exit; + // wait 1ms +#if 0 + Sleep(1); +#else + SLEEP_1MS; +#endif + + //Config channel + status = MmdPhyRead(hDevice, MMD_VEND2, 0xBD2C, &phydata); + if (status != SUCCESS) + goto exit; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xBD32, &phydata2); + if (status != SUCCESS) + goto exit; + + if(pIEEEtestmode -> channel == TESTMODE_CHANNEL_NONE){ + phydata &= (~(BIT_10)); + } + else{ + phydata |= BIT_10; + + if(pIEEEtestmode -> channel == TESTMODE_CHANNEL_A) + phydata_w = 1 << 8; + else if(pIEEEtestmode -> channel == TESTMODE_CHANNEL_B) + phydata_w = 2 << 8; + else if(pIEEEtestmode -> channel == TESTMODE_CHANNEL_C) + phydata_w = 4 << 8; + else if(pIEEEtestmode -> channel == TESTMODE_CHANNEL_D) + phydata_w = 8 << 8; + + phydata2 &= (~(BIT_11 | BIT_10 | BIT_9 | BIT_8)); + phydata2 |= phydata_w; + } + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xBD32, phydata2); + if (status != SUCCESS) + goto exit; + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xBD2C, phydata); + if (status != SUCCESS) + goto exit; + + //1G Test Mode + if (pIEEEtestmode->TM1) + { + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA412, 0x2000); + if (status != SUCCESS) + goto exit; + } + + if (pIEEEtestmode->TM2) + { + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA412, 0x4000); + if (status != SUCCESS) + goto exit; + } + + if (pIEEEtestmode->TM4) + { + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA412, 0x8000); + if (status != SUCCESS) + goto exit; + } + + if (pIEEEtestmode->TMFINISH) + { + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA412, 0x0000); + if (status != SUCCESS) + goto exit; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xBD2C, &phydata); + if (status != SUCCESS) + goto exit; + + phydata &= (~(BIT_10)); + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xBD2C, phydata); + if (status != SUCCESS) + goto exit; + } + + break; + } + + case LINK_SPEED_2P5G: + { + //initial setting + //Write MMD7, reg 0x0000, bit[12]=0x1 + status = MmdPhyRead(hDevice, MMD_AN, 0x0000, &phydata); + if (status != SUCCESS) + goto exit; + + phydata |= BIT_12; + + status = MmdPhyWrite(hDevice, MMD_AN, 0x0000, phydata); + if (status != SUCCESS) + goto exit; + // wait 1ms +#if 0 + Sleep(1); +#else + SLEEP_1MS; +#endif + + //Write MMD31, reg 0xA412, bit[15:13]=0x0 + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA412, &phydata); + if (status != SUCCESS) + goto exit; + + phydata &= (~(BIT_15 | BIT_14 | BIT_13)); + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA412, phydata); + if (status != SUCCESS) + goto exit; + // wait 1ms +#if 0 + Sleep(1); +#else + SLEEP_1MS; +#endif + + //Write MMD1, reg 0x0000, data 0x2058 + status = MmdPhyWrite(hDevice, MMD_PMAPMD, 0x0000, 0x2058); + if (status != SUCCESS) + goto exit; + + // wait 1ms +#if 0 + Sleep(1); +#else + SLEEP_1MS; +#endif + + //Config channel + status = MmdPhyRead(hDevice, MMD_VEND2, 0xBD2C, &phydata); + if (status != SUCCESS) + goto exit; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xBD32, &phydata2); + if (status != SUCCESS) + goto exit; + + if(pIEEEtestmode -> channel == TESTMODE_CHANNEL_NONE){ + phydata &= (~(BIT_8)); + } + else{ + phydata |= BIT_8; + + if(pIEEEtestmode -> channel == TESTMODE_CHANNEL_A) + phydata_w = 1; + else if(pIEEEtestmode -> channel == TESTMODE_CHANNEL_B) + phydata_w = 2; + else if(pIEEEtestmode -> channel == TESTMODE_CHANNEL_C) + phydata_w = 4; + else if(pIEEEtestmode -> channel == TESTMODE_CHANNEL_D) + phydata_w = 8; + + phydata2 &= (~(BIT_3 | BIT_2 | BIT_1 | BIT_0)); + phydata2 |= phydata_w; + } + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xBD32, phydata2); + if (status != SUCCESS) + goto exit; + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xBD2C, phydata); + if (status != SUCCESS) + goto exit; + + + // 2.5G Test Mode + if (pIEEEtestmode->TM1) + { + status = MmdPhyWrite(hDevice, MMD_PMAPMD, 132, 0x2400); + if (status != SUCCESS) + goto exit; + } + + if (pIEEEtestmode->TM2) + { + status = MmdPhyWrite(hDevice, MMD_PMAPMD, 132, 0x4400); + if (status != SUCCESS) + goto exit; + } + + if (pIEEEtestmode->TM3) + { + status = MmdPhyWrite(hDevice, MMD_PMAPMD, 132, 0x6400); + if (status != SUCCESS) + goto exit; + } + + if (pIEEEtestmode->TM4) + { + if (pIEEEtestmode->TONE1) + { + status = MmdPhyWrite(hDevice, MMD_PMAPMD, 132, 0x8400); + if (status != SUCCESS) + goto exit; + } + + if (pIEEEtestmode->TONE2) + { + status = MmdPhyWrite(hDevice, MMD_PMAPMD, 132, 0x8800); + if (status != SUCCESS) + goto exit; + } + + if (pIEEEtestmode->TONE3) + { + status = MmdPhyWrite(hDevice, MMD_PMAPMD, 132, 0x9000); + if (status != SUCCESS) + goto exit; + } + + if (pIEEEtestmode->TONE4) + { + status = MmdPhyWrite(hDevice, MMD_PMAPMD, 132, 0x9400); + if (status != SUCCESS) + goto exit; + } + + if (pIEEEtestmode->TONE5) + { + status = MmdPhyWrite(hDevice, MMD_PMAPMD, 132, 0x9800); + if (status != SUCCESS) + goto exit; + } + } + + if (pIEEEtestmode->TM5) + { + status = MmdPhyWrite(hDevice, MMD_PMAPMD, 132, 0xA400); + if (status != SUCCESS) + goto exit; + } + + if (pIEEEtestmode->TM6) + { + status = MmdPhyWrite(hDevice, MMD_PMAPMD, 132, 0xC400); + if (status != SUCCESS) + goto exit; + } + + if (pIEEEtestmode->TMFINISH) + { + status = MmdPhyRead(hDevice, MMD_VEND2, 0xBD2C, &phydata); + if (status != SUCCESS) + goto exit; + + phydata &= (~(BIT_8)); + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xBD2C, phydata); + if (status != SUCCESS) + goto exit; + + //re-nway and set phy_rst) + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA400, 0x9200); + if (status != SUCCESS) + goto exit; + } + + break; + } + default: + break; + } + + + + +exit: + return status; +} + +BOOLEAN +Rtl8226b_serdes_rst( + IN HANDLE hDevice + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + status = MmdPhyRead(hDevice, MMD_VEND1, 0x7581, &phydata); + if (status != SUCCESS) + goto exit; + + phydata &= (~BIT_4); + + status = MmdPhyWrite(hDevice, MMD_VEND1, 0x7581, phydata); + if (status != SUCCESS) + goto exit; + + // wait 1ms +#if 0 + Sleep(1); +#else + SLEEP_1MS; +#endif + + status = MmdPhyRead(hDevice, MMD_VEND1, 0x7581, &phydata); + if (status != SUCCESS) + goto exit; + + phydata |= BIT_4; + + status = MmdPhyWrite(hDevice, MMD_VEND1, 0x7581, phydata); + if (status != SUCCESS) + goto exit; + + // wait 1ms +#if 0 + Sleep(1); +#else + SLEEP_1MS; +#endif +exit: + return status; +} + +BOOLEAN +Rtl8226b_serdes_link_get( + IN HANDLE hDevice, + OUT BOOL *perdesLink, + OUT PHY_SERDES_MODE *SerdesMode + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + // serdes link + status = MmdPhyRead(hDevice, MMD_VEND1, 0x758D, &phydata); + if (status != SUCCESS) + goto exit; + + *perdesLink = (phydata & BIT_1) ? (TRUE) : (FALSE); + + status = MmdPhyRead(hDevice, MMD_VEND1, 0x758B, &phydata); + if (status != SUCCESS) + goto exit; + + phydata &= BIT_0; + + if (phydata == 1){ + + //serdes mode + status = MmdPhyRead(hDevice, MMD_VEND1, 0x7580, &phydata); + if (status != SUCCESS) + goto exit; + + phydata &= (BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0); + + if(phydata == 2) + *SerdesMode = PHY_SERDES_MODE_SGMII; + else if(phydata == 13) + *SerdesMode = PHY_SERDES_MODE_USXGMII; + else if(phydata == 18) + *SerdesMode = PHY_SERDES_MODE_HiSGMII; + else if(phydata == 22) + *SerdesMode = PHY_SERDES_MODE_2500BASEX; + else if(phydata == 31) + *SerdesMode = PHY_SERDES_MODE_NO_SDS; + else + *SerdesMode = PHY_SERDES_MODE_OTHER; + } + else{ + *SerdesMode = PHY_SERDES_MODE_NO_SDS; + } + +exit: + return status; +} + +BOOLEAN +Rtl8226b_serdes_option_set( + IN HANDLE hDevice, + IN UINT8 functioninput + ) +{ + BOOL status = FAILURE, blinkOk = FAILURE; + UINT16 phydata = 0, nTimeout = 100; + if ((functioninput >= 0) && (functioninput <= 3)) + { + status = MmdPhyRead(hDevice, MMD_VEND1, 0x75F3, &phydata); + if (status != SUCCESS) + goto exit; + + phydata &= ~BIT_0 ; + status = MmdPhyWrite(hDevice, MMD_VEND1, 0x75F3, phydata); + if (status != SUCCESS) + goto exit; + status = MmdPhyRead(hDevice, MMD_VEND1, 0x697A, &phydata); + if (status != SUCCESS) + goto exit; + + phydata &= (~(BIT_0 | BIT_1 | BIT_2 | BIT_3 | BIT_4 | BIT_5)); + phydata |= functioninput; + + status = MmdPhyWrite(hDevice, MMD_VEND1, 0x697A, phydata); + if (status != SUCCESS) + goto exit; + if ((functioninput == 0) || (functioninput == 2)) + { + status = MmdPhyWrite(hDevice, MMD_VEND1, 0x6A04, 0x0503); + if (status != SUCCESS) + goto exit; + status = MmdPhyWrite(hDevice, MMD_VEND1, 0x6F10, 0xD455); + if (status != SUCCESS) + goto exit; + status = MmdPhyWrite(hDevice, MMD_VEND1, 0x6F11, 0x8020); + if (status != SUCCESS) + goto exit; + } + else if ((functioninput == 1) || (functioninput == 3)) + { + status = MmdPhyWrite(hDevice, MMD_VEND1, 0x6A04, 0x0503); + if (status != SUCCESS) + goto exit; + status = MmdPhyWrite(hDevice, MMD_VEND1, 0x6F10, 0xD433); + if (status != SUCCESS) + goto exit; + status = MmdPhyWrite(hDevice, MMD_VEND1, 0x6F11, 0x8020); + if (status != SUCCESS) + goto exit; + } + // change link state + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA400, &phydata); + if (status != SUCCESS) + goto exit; + + phydata |= BIT_14 ; + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA400, phydata); + if (status != SUCCESS) + goto exit; + do { + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA434, &phydata); + if (status != SUCCESS) + goto exit; + blinkOk = (phydata & BIT_2) ? (TRUE) : (FALSE); + if (blinkOk) break; + SLEEP_100MS; + nTimeout --; + //printf("blinkOk %x, nTimeout = %d\n", phydata, nTimeout); + } while (nTimeout > 0); + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA400, &phydata); + if (status != SUCCESS) + goto exit; + + phydata &= ~BIT_14 ; + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA400, phydata); + if (status != SUCCESS) + goto exit; + } + +exit: + return status; +} + +BOOLEAN +Rtl8226b_serdes_option_set_for_init( + IN HANDLE hDevice, + IN UINT8 functioninput + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + if ((functioninput >= 0) && (functioninput <= 3)) + { + status = MmdPhyRead(hDevice, MMD_VEND1, 0x75F3, &phydata); + if (status != SUCCESS) + goto exit; + + phydata &= ~BIT_0 ; + status = MmdPhyWrite(hDevice, MMD_VEND1, 0x75F3, phydata); + if (status != SUCCESS) + goto exit; + status = MmdPhyRead(hDevice, MMD_VEND1, 0x697A, &phydata); + if (status != SUCCESS) + goto exit; + + phydata &= (~(BIT_0 | BIT_1 | BIT_2 | BIT_3 | BIT_4 | BIT_5)); + phydata |= functioninput; + + status = MmdPhyWrite(hDevice, MMD_VEND1, 0x697A, phydata); + if (status != SUCCESS) + goto exit; + if ((functioninput == 0) || (functioninput == 2)) + { + status = MmdPhyWrite(hDevice, MMD_VEND1, 0x6A04, 0x0503); + if (status != SUCCESS) + goto exit; + status = MmdPhyWrite(hDevice, MMD_VEND1, 0x6F10, 0xD455); + if (status != SUCCESS) + goto exit; + status = MmdPhyWrite(hDevice, MMD_VEND1, 0x6F11, 0x8020); + if (status != SUCCESS) + goto exit; + } + else if ((functioninput == 1) || (functioninput == 3)) + { + status = MmdPhyWrite(hDevice, MMD_VEND1, 0x6A04, 0x0503); + if (status != SUCCESS) + goto exit; + status = MmdPhyWrite(hDevice, MMD_VEND1, 0x6F10, 0xD433); + if (status != SUCCESS) + goto exit; + status = MmdPhyWrite(hDevice, MMD_VEND1, 0x6F11, 0x8020); + if (status != SUCCESS) + goto exit; + } + + } + +exit: + return status; +} + +BOOLEAN +Rtl8226b_serdes_option_get( + IN HANDLE hDevice, + OUT PHY_SERDES_OPTION *SerdesOption + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + //serdes option + status = MmdPhyRead(hDevice, MMD_VEND1, 0x697A, &phydata); + if (status != SUCCESS) + goto exit; + + phydata &= (BIT_5 |BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0); + + if(phydata == 0) + *SerdesOption = PHY_SERDES_OPTION_2500BASEX_SGMII; + else if(phydata == 1) + *SerdesOption = PHY_SERDES_OPTION_HiSGMII_SGMII; + else if(phydata == 2) + *SerdesOption = PHY_SERDES_OPTION_2500BASEX; + else if(phydata == 3) + *SerdesOption = PHY_SERDES_OPTION_HiSGMII; + else + *SerdesOption = PHY_SERDES_OPTION_OTHER; +exit: + return status; +} + +BOOLEAN +Rtl8226b_serdes_polarity_swap( + IN HANDLE hDevice, + IN PHY_SERDES_POLARITY_SWAP *ppolarityswap + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + status = MmdPhyWrite(hDevice, MMD_VEND1, 0x7588, 0x0); + if (status != SUCCESS) + goto exit; + + if (ppolarityswap->TX_SWAP && ppolarityswap->RX_SWAP) + phydata = 0x1703; + else if (ppolarityswap->TX_SWAP) + phydata = 0x1503; + else if (ppolarityswap->RX_SWAP) + phydata = 0x1603; + else + phydata = 0x1403; + + status = MmdPhyWrite(hDevice, MMD_VEND1, 0x7589, phydata); + if (status != SUCCESS) + goto exit; + + status = MmdPhyWrite(hDevice, MMD_VEND1, 0x7587, 0x0003); + if (status != SUCCESS) + goto exit; + +exit: + return status; +} + +BOOLEAN +Rtl8226b_serdes_autoNego_set( + IN HANDLE hDevice, + IN BOOL Enable + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + status = MmdPhyWrite(hDevice, MMD_VEND1, 0x7588, 0x0002); + if (status != SUCCESS) + goto exit; + + if (Enable) + phydata = 0x70D0; + else + phydata = 0x71D0; + + status = MmdPhyWrite(hDevice, MMD_VEND1, 0x7589, phydata); + if (status != SUCCESS) + goto exit; + + status = MmdPhyWrite(hDevice, MMD_VEND1, 0x7587, 0x0003); + if (status != SUCCESS) + goto exit; + +exit: + return status; +} + +BOOLEAN +Rtl8226b_wol_set( + IN HANDLE hDevice, + IN PHY_WOL_EVENT *pwolevent + ) +{ + BOOL status = FAILURE; + BOOL linkOK; + UINT16 speed; + UINT16 phydata = 0, phydata2=0; + + status = Rtl8226b_is_link(hDevice, &linkOK); + if (status != SUCCESS) + goto exit; + + if (linkOK) + { + status = Rtl8226b_speed_get(hDevice, &speed); + if (status != SUCCESS) + goto exit; + + //WOL is not supported when port link at 2.5G. + if (speed == LINK_SPEED_2P5G) + { +#if 0 + osal_printf("WOL/PME is not supported when port link at 2.5G.\n"); +#else + printf("WOL/PME is not supported when port link at 2.5G.\n"); +#endif + status = FAILURE; + goto exit; + } + } + + //Set INTB/PMEB pinas PMEB(optional) MMD31, reg 0xD05C, bit0=1 + status = MmdPhyRead(hDevice, MMD_VEND2, 0xD05C, &phydata); + if (status != SUCCESS) + goto exit; + + phydata |= BIT_0; + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xD05C, phydata); + if (status != SUCCESS) + goto exit; + + // wait 1ms +#if 0 + Sleep(1); +#else + SLEEP_1MS; +#endif + + //Set MAC address MMD31, reg 0xD8C0,0xD8C2,0xD8C4 + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xD8C0, pwolevent->macaddress.ADDR15_0); + if (status != SUCCESS) + goto exit; + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xD8C2, pwolevent->macaddress.ADDR31_16); + if (status != SUCCESS) + goto exit; + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xD8C4, pwolevent->macaddress.ADDR47_32); + if (status != SUCCESS) + goto exit; + + //Set Max packet length MMD31, reg 0xD8A2 + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xD8A2, pwolevent->MAXPKTLENGTH); + if (status != SUCCESS) + goto exit; + + //WOL event select and enable MMD31, reg 0xD8A0 + if(pwolevent->LINKCHG) + phydata2 |= BIT_13; + if(pwolevent->MAGIC) + phydata2 |= BIT_12; + if(pwolevent->ARBITRARY) + phydata2 |= BIT_11; + if(pwolevent->UNICAST) + phydata2 |= BIT_10; + if(pwolevent->MULTICAST) + phydata2 |= BIT_9; + if(pwolevent->BROADCAST) + phydata2 |= BIT_8; + if(pwolevent->FRAME7) + phydata2 |= BIT_7; + if(pwolevent->FRAME6) + phydata2 |= BIT_6; + if(pwolevent->FRAME5) + phydata2 |= BIT_5; + if(pwolevent->FRAME4) + phydata2 |= BIT_4; + if(pwolevent->FRAME3) + phydata2 |= BIT_3; + if(pwolevent->FRAME2) + phydata2 |= BIT_2; + if(pwolevent->FRAME1) + phydata2 |= BIT_1; + if(pwolevent->FRAME0) + phydata2 |= BIT_0; + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xD8A0, phydata2); + if (status != SUCCESS) + goto exit; + + if(pwolevent->MULTICAST) + { + //Set Multicast register MMD31, reg 0xD8C6,0xD8C8,0xD8CA,0xD8CC + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xD8C6, pwolevent->multicast.REG15_0); + if (status != SUCCESS) + goto exit; + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xD8C8, pwolevent->multicast.REG31_16); + if (status != SUCCESS) + goto exit; + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xD8CA, pwolevent->multicast.REG47_32); + if (status != SUCCESS) + goto exit; + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xD8CC, pwolevent->multicast.REG63_48); + if (status != SUCCESS) + goto exit; + } + + //Set Wakeup Frame #0 + if(pwolevent->FRAME0) + { + //Set Mask + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xD800, pwolevent->wakeframe0.MASK15_0); + if (status != SUCCESS) + goto exit; + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xD802, pwolevent->wakeframe0.MASK31_16); + if (status != SUCCESS) + goto exit; + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xD804, pwolevent->wakeframe0.MASK47_32); + if (status != SUCCESS) + goto exit; + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xD806, pwolevent->wakeframe0.MASK63_48); + if (status != SUCCESS) + goto exit; + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xD808, pwolevent->wakeframe0.MASK79_64); + if (status != SUCCESS) + goto exit; + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xD80A, pwolevent->wakeframe0.MASK95_80); + if (status != SUCCESS) + goto exit; + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xD80C, pwolevent->wakeframe0.MASK111_96); + if (status != SUCCESS) + goto exit; + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xD80E, pwolevent->wakeframe0.MASK127_112); + if (status != SUCCESS) + goto exit; + + //Set CRC + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xD880, pwolevent->wakeframe0.CRC); + if (status != SUCCESS) + goto exit; + } + +exit: + return status; +} + +BOOLEAN +Rtl8226b_wol_exit( + IN HANDLE hDevice + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + //Disable all WOL events + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xD8A0, 0x0000); + if (status != SUCCESS) + goto exit; + + //WOL reset + status = MmdPhyRead(hDevice, MMD_VEND2, 0xD8A2, &phydata); + if (status != SUCCESS) + goto exit; + + phydata &= (~BIT_15); + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xD8A2, phydata); + if (status != SUCCESS) + goto exit; + +exit: + return status; +} +BOOLEAN +Rtl8226b_ThermalSensor_get( + IN HANDLE hDevice, + OUT PHY_THERMAL_RESULT *pTsResult + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA436, 0x817D); + if (status != SUCCESS) + goto exit; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA438, &phydata); + if (status != SUCCESS) + goto exit; + + pTsResult->Enable = (phydata & BIT_12) ? (TRUE) : (FALSE); + + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xBD84, &phydata); + if (status != SUCCESS) + goto exit; + + pTsResult->Temperature = (phydata & 0x03ff)/2; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xB54C, &phydata); + if (status != SUCCESS) + goto exit; + + pTsResult->Temperature_threshold = ((phydata & 0xffc0)>>6)/2; + +exit: + return status; +} + +BOOLEAN +Rtl8226b_ThermalSensor_resume_2P5G( + IN HANDLE hDevice + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + status = MmdPhyRead(hDevice, MMD_VEND2,0xA662, &phydata); + if (status != SUCCESS) + goto exit; + + phydata &= (~(BIT_1 | BIT_0)); + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA662, phydata); + if (status != SUCCESS) + goto exit; + + //The setting will take effect after a link change event + Rtl8226b_enable_set(hDevice, FALSE); +#if 0 + Sleep(1); +#else + SLEEP_1MS; +#endif + Rtl8226b_enable_set(hDevice, TRUE); + + +exit: + return status; +} diff --git a/sources/uboot-be550/drivers/net/rtl8221b/nic_rtl8226b.h b/sources/uboot-be550/drivers/net/rtl8221b/nic_rtl8226b.h new file mode 100644 index 00000000..13ff7fca --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8221b/nic_rtl8226b.h @@ -0,0 +1,346 @@ +/* + * Copyright (C) 2019 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : PHY 8226 Driver + * + * Feature : PHY 8226 Driver + * + */ +#ifndef __NIC_RTL8226B_H__ +#define __NIC_RTL8226B_H__ + +#if 0 +#include +#else +#include "rtl8226_typedef.h" +#endif + +BOOLEAN +Rtl8226b_ThermalSensor_get( + IN HANDLE hDevice, + OUT PHY_THERMAL_RESULT *pTsResult + ); + +BOOLEAN +Rtl8226b_ThermalSensor_resume_2P5G( + IN HANDLE hDevice + ); + +BOOLEAN +Rtl8226b_wol_set( + IN HANDLE hDevice, + IN PHY_WOL_EVENT *pwolevent + ); + +BOOLEAN +Rtl8226b_wol_exit( + IN HANDLE hDevice + ); + +BOOLEAN +Rtl8226b_phy_reset( + IN HANDLE hDevice + ); + +BOOLEAN +Rtl8226b_autoNegoEnable_get( + IN HANDLE hDevice, + OUT BOOL *pEnable + ); + +BOOLEAN +Rtl8226b_autoNegoEnable_set( + IN HANDLE hDevice, + IN BOOL Enable + ); + +BOOLEAN +Rtl8226b_autoNegoAbility_get( + IN HANDLE hDevice, + OUT PHY_LINK_ABILITY *pPhyAbility + ); + +BOOLEAN +Rtl8226b_autoNegoAbility_set( + IN HANDLE hDevice, + IN PHY_LINK_ABILITY *pPhyAbility + ); + +BOOLEAN +Rtl8226b_duplex_get( + IN HANDLE hDevice, + OUT BOOL *pEnable + ); + +BOOLEAN +Rtl8226b_duplex_set( + IN HANDLE hDevice, + IN BOOL Enable + ); + +BOOLEAN +Rtl8226b_is_link( + IN HANDLE hDevice, + OUT BOOL *plinkok + ); + +BOOLEAN +Rtl8226b_speed_get( + IN HANDLE hDevice, + OUT UINT16 *pSpeed + ); + +BOOLEAN +Rtl8226b_force_speed_set( + IN HANDLE hDevice, + IN UINT16 Speed + ); + +BOOLEAN +Rtl8226b_force_speed_get( + IN HANDLE hDevice, + OUT UINT16 *force_speed + ); + + + +BOOLEAN +Rtl8226b_enable_set( + IN HANDLE hDevice, + IN BOOL Enable + ); + +BOOLEAN +Rtl8226b_greenEnable_get( + IN HANDLE hDevice, + OUT BOOL *pEnable + ); + +BOOLEAN +Rtl8226b_greenEnable_set( + IN HANDLE hDevice, + IN BOOL Enable + ); + +BOOLEAN +Rtl8226b_eeeEnable_get( + IN HANDLE hDevice, + OUT PHY_EEE_ENABLE *pEeeEnable + ); + +BOOLEAN +Rtl8226b_eeeEnable_set( + IN HANDLE hDevice, + IN PHY_EEE_ENABLE *pEeeEnable + ); + +BOOLEAN +Rtl8226b_PHYmodeEEE_set( + IN HANDLE hDevice, + int on_off + ); + +BOOLEAN +Rtl8226b_10M_PHYmodeEEEP_set( + IN HANDLE hDevice, + int on_off + ); + + + +BOOLEAN +Rtl8226b_crossOverMode_get( + IN HANDLE hDevice, + OUT PHY_CROSSPVER_MODE *CrossOverMode + ); + +BOOLEAN +Rtl8226b_crossOverMode_set( + IN HANDLE hDevice, + IN PHY_CROSSPVER_MODE CrossOverMode + ); + +BOOLEAN +Rtl8226b_crossOverStatus_get( + IN HANDLE hDevice, + OUT PHY_CROSSPVER_STATUS *pCrossOverStatus + ); + +BOOLEAN +Rtl8226b_masterSlave_get( + IN HANDLE hDevice, + OUT PHY_MASTERSLAVE_MODE *MasterSlaveMode + ); + +BOOLEAN +Rtl8226b_masterSlave_set( + IN HANDLE hDevice, + IN PHY_MASTERSLAVE_MODE MasterSlaveMode + ); + +BOOLEAN +Rtl8226b_loopback_get( + IN HANDLE hDevice, + OUT BOOL *pEnable + ); + +BOOLEAN +Rtl8226b_loopback_set( + IN HANDLE hDevice, + IN BOOL Enable + ); + +BOOLEAN +Rtl8226b_downSpeedEnable_get( + IN HANDLE hDevice, + OUT BOOL *pEnable + ); + +BOOLEAN +Rtl8226b_downSpeedEnable_set( + IN HANDLE hDevice, + IN BOOL Enable + ); + +BOOLEAN +Rtl8226b_gigaLiteEnable_get( + IN HANDLE hDevice, + OUT BOOL *pEnable + ); + +BOOLEAN +Rtl8226b_gigaLiteEnable_set( + IN HANDLE hDevice, + IN BOOL Enable + ); + +BOOLEAN +Rtl8226b_mdiSwapEnable_get( + IN HANDLE hDevice, + OUT BOOL *pEnable + ); + +BOOLEAN +Rtl8226b_mdiSwapEnable_set( + IN HANDLE hDevice, + IN BOOL Enable + ); + +BOOLEAN +Rtl8226b_rtct_start( + IN HANDLE hDevice + ); + +BOOLEAN +Rtl8226b_rtctResult_get( + IN HANDLE hDevice, + OUT PHY_RTCT_RESULT *pRtctResult + ); + +BOOLEAN +Rtl8226b_rtctdone_get( + IN HANDLE hDevice, + OUT BOOL *prtct_done + ); + + +BOOLEAN +Rtl8226b_linkDownPowerSavingEnable_get( + IN HANDLE hDevice, + OUT BOOL *pEnable + ); + +BOOLEAN +Rtl8226b_linkDownPowerSavingEnable_set( + IN HANDLE hDevice, + IN BOOL Enable + ); + +BOOLEAN +Rtl8226b_2p5gLiteEnable_get( + IN HANDLE hDevice, + OUT BOOL *pEnable + ); + +BOOLEAN +Rtl8226b_2p5gLiteEnable_set( + IN HANDLE hDevice, + IN BOOL Enable + ); + +BOOLEAN +Rtl8226b_ThermalSensorEnable_get( + IN HANDLE hDevice, + OUT BOOL *pEnable + ); + +BOOLEAN +Rtl8226b_ThermalSensorEnable_set( + IN HANDLE hDevice, + IN BOOL Enable, + IN UINT16 threshold + ); + +BOOLEAN +Rtl8226b_ieeeTestMode_set( + IN HANDLE hDevice, + IN UINT16 Speed, + IN PHY_IEEE_TEST_MODE *pIEEEtestmode + ); + +BOOLEAN +Rtl8226b_serdes_rst( + IN HANDLE hDevice + ); + +BOOLEAN +Rtl8226b_serdes_link_get( + IN HANDLE hDevice, + OUT BOOL *perdesLink, + OUT PHY_SERDES_MODE *SerdesMode + ); + +BOOLEAN +Rtl8226b_serdes_option_set( + IN HANDLE hDevice, + IN UINT8 functioninput + ); + +/* serdes option set for initial state */ +BOOLEAN +Rtl8226b_serdes_option_set_for_init( + IN HANDLE hDevice, + IN UINT8 functioninput + ); + +BOOLEAN +Rtl8226b_serdes_option_get( + IN HANDLE hDevice, + OUT PHY_SERDES_OPTION *SerdesOption + ); + +BOOLEAN +Rtl8226b_serdes_polarity_swap( + IN HANDLE hDevice, + IN PHY_SERDES_POLARITY_SWAP *ppolarityswap + ); + +BOOLEAN +Rtl8226b_serdes_autoNego_set( + IN HANDLE hDevice, + IN BOOL Enable + ); + + + + +#endif /* __NIC_RTL8226_H__ */ + diff --git a/sources/uboot-be550/drivers/net/rtl8221b/nic_rtl8226b_init.c b/sources/uboot-be550/drivers/net/rtl8221b/nic_rtl8226b_init.c new file mode 100644 index 00000000..ca3f5101 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8221b/nic_rtl8226b_init.c @@ -0,0 +1,1676 @@ + +/* SW_SDK: include files */ +#if 0 +#include +#include +#include +//#include +#include +#else +#include "rtl8226_typedef.h" +#include "nic_rtl8226b.h" +#include "nic_rtl8226b_init.h" +#endif + + +static const MMD_REG Rtl8226b_n0_ramcode[] = +{ + { 31, 0xa436, 0XA016, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa436, 0XA012, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa436, 0XA014, }, + { 31, 0xa438, 0X1800, }, + { 31, 0xa438, 0X8010, }, + { 31, 0xa438, 0X1800, }, + { 31, 0xa438, 0X801a, }, + { 31, 0xa438, 0X1800, }, + { 31, 0xa438, 0X803f, }, + { 31, 0xa438, 0X1800, }, + { 31, 0xa438, 0X8045, }, + { 31, 0xa438, 0X1800, }, + { 31, 0xa438, 0X8067, }, + { 31, 0xa438, 0X1800, }, + { 31, 0xa438, 0X806d, }, + { 31, 0xa438, 0X1800, }, + { 31, 0xa438, 0X8079, }, + { 31, 0xa438, 0X1800, }, + { 31, 0xa438, 0X807e, }, + { 31, 0xa438, 0Xd093, }, + { 31, 0xa438, 0Xd1c4, }, + { 31, 0xa438, 0X1000, }, + { 31, 0xa438, 0X135c, }, + { 31, 0xa438, 0Xd704, }, + { 31, 0xa438, 0X5fbc, }, + { 31, 0xa438, 0Xd504, }, + { 31, 0xa438, 0Xc9f1, }, + { 31, 0xa438, 0X1800, }, + { 31, 0xa438, 0X0fc9, }, + { 31, 0xa438, 0Xbb50, }, + { 31, 0xa438, 0Xd505, }, + { 31, 0xa438, 0Xa202, }, + { 31, 0xa438, 0Xd504, }, + { 31, 0xa438, 0X8c0f, }, + { 31, 0xa438, 0Xd500, }, + { 31, 0xa438, 0X1000, }, + { 31, 0xa438, 0X1519, }, + { 31, 0xa438, 0X1000, }, + { 31, 0xa438, 0X135c, }, + { 31, 0xa438, 0Xd75e, }, + { 31, 0xa438, 0X5fae, }, + { 31, 0xa438, 0X9b50, }, + { 31, 0xa438, 0X1000, }, + { 31, 0xa438, 0X135c, }, + { 31, 0xa438, 0Xd75e, }, + { 31, 0xa438, 0X7fae, }, + { 31, 0xa438, 0X1000, }, + { 31, 0xa438, 0X135c, }, + { 31, 0xa438, 0Xd707, }, + { 31, 0xa438, 0X40a7, }, + { 31, 0xa438, 0Xd719, }, + { 31, 0xa438, 0X4071, }, + { 31, 0xa438, 0X1800, }, + { 31, 0xa438, 0X1557, }, + { 31, 0xa438, 0Xd719, }, + { 31, 0xa438, 0X2f70, }, + { 31, 0xa438, 0X803b, }, + { 31, 0xa438, 0X2f73, }, + { 31, 0xa438, 0X156a, }, + { 31, 0xa438, 0X5e70, }, + { 31, 0xa438, 0X1800, }, + { 31, 0xa438, 0X155d, }, + { 31, 0xa438, 0Xd505, }, + { 31, 0xa438, 0Xa202, }, + { 31, 0xa438, 0Xd500, }, + { 31, 0xa438, 0Xffed, }, + { 31, 0xa438, 0Xd709, }, + { 31, 0xa438, 0X4054, }, + { 31, 0xa438, 0Xa788, }, + { 31, 0xa438, 0Xd70b, }, + { 31, 0xa438, 0X1800, }, + { 31, 0xa438, 0X172a, }, + { 31, 0xa438, 0Xc0c1, }, + { 31, 0xa438, 0Xc0c0, }, + { 31, 0xa438, 0Xd05a, }, + { 31, 0xa438, 0Xd1ba, }, + { 31, 0xa438, 0Xd701, }, + { 31, 0xa438, 0X2529, }, + { 31, 0xa438, 0X022a, }, + { 31, 0xa438, 0Xd0a7, }, + { 31, 0xa438, 0Xd1b9, }, + { 31, 0xa438, 0Xa208, }, + { 31, 0xa438, 0X1000, }, + { 31, 0xa438, 0X080e, }, + { 31, 0xa438, 0Xd701, }, + { 31, 0xa438, 0X408b, }, + { 31, 0xa438, 0X1000, }, + { 31, 0xa438, 0X0a65, }, + { 31, 0xa438, 0Xf003, }, + { 31, 0xa438, 0X1000, }, + { 31, 0xa438, 0X0a6b, }, + { 31, 0xa438, 0Xd701, }, + { 31, 0xa438, 0X1000, }, + { 31, 0xa438, 0X0920, }, + { 31, 0xa438, 0X1000, }, + { 31, 0xa438, 0X0915, }, + { 31, 0xa438, 0X1000, }, + { 31, 0xa438, 0X0909, }, + { 31, 0xa438, 0X228f, }, + { 31, 0xa438, 0X804e, }, + { 31, 0xa438, 0X9801, }, + { 31, 0xa438, 0Xd71e, }, + { 31, 0xa438, 0X5d61, }, + { 31, 0xa438, 0Xd701, }, + { 31, 0xa438, 0X1800, }, + { 31, 0xa438, 0X022a, }, + { 31, 0xa438, 0X2005, }, + { 31, 0xa438, 0X091a, }, + { 31, 0xa438, 0X3bd9, }, + { 31, 0xa438, 0X0919, }, + { 31, 0xa438, 0X1800, }, + { 31, 0xa438, 0X0916, }, + { 31, 0xa438, 0X1000, }, + { 31, 0xa438, 0X14c5, }, + { 31, 0xa438, 0Xd703, }, + { 31, 0xa438, 0X3181, }, + { 31, 0xa438, 0X8077, }, + { 31, 0xa438, 0X60ad, }, + { 31, 0xa438, 0X1000, }, + { 31, 0xa438, 0X135c, }, + { 31, 0xa438, 0Xd703, }, + { 31, 0xa438, 0X5fba, }, + { 31, 0xa438, 0X1800, }, + { 31, 0xa438, 0X0cc7, }, + { 31, 0xa438, 0Xd096, }, + { 31, 0xa438, 0Xd1a9, }, + { 31, 0xa438, 0Xd503, }, + { 31, 0xa438, 0X1800, }, + { 31, 0xa438, 0X0c94, }, + { 31, 0xa438, 0Xa802, }, + { 31, 0xa438, 0Xa301, }, + { 31, 0xa438, 0Xa801, }, + { 31, 0xa438, 0Xc004, }, + { 31, 0xa438, 0Xd710, }, + { 31, 0xa438, 0X4000, }, + { 31, 0xa438, 0X1800, }, + { 31, 0xa438, 0X1e79, }, + { 31, 0xa436, 0XA026, }, + { 31, 0xa438, 0X1e78, }, + { 31, 0xa436, 0XA024, }, + { 31, 0xa438, 0X0c93, }, + { 31, 0xa436, 0XA022, }, + { 31, 0xa438, 0X0cc5, }, + { 31, 0xa436, 0XA020, }, + { 31, 0xa438, 0X0915, }, + { 31, 0xa436, 0XA006, }, + { 31, 0xa438, 0X020a, }, + { 31, 0xa436, 0XA004, }, + { 31, 0xa438, 0X1726, }, + { 31, 0xa436, 0XA002, }, + { 31, 0xa438, 0X1542, }, + { 31, 0xa436, 0XA000, }, + { 31, 0xa438, 0X0fc7, }, + { 31, 0xa436, 0XA008, }, + { 31, 0xa438, 0Xff00, }, + + +}; + + +static const MMD_REG Rtl8226b_n1_ramcode[] = +{ + { 31, 0xa436, 0XA016, }, + { 31, 0xa438, 0X0010, }, + { 31, 0xa436, 0XA012, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa436, 0XA014, }, + { 31, 0xa438, 0X1800, }, + { 31, 0xa438, 0X8010, }, + { 31, 0xa438, 0X1800, }, + { 31, 0xa438, 0X801d, }, + { 31, 0xa438, 0X1800, }, + { 31, 0xa438, 0X802c, }, + { 31, 0xa438, 0X1800, }, + { 31, 0xa438, 0X802c, }, + { 31, 0xa438, 0X1800, }, + { 31, 0xa438, 0X802c, }, + { 31, 0xa438, 0X1800, }, + { 31, 0xa438, 0X802c, }, + { 31, 0xa438, 0X1800, }, + { 31, 0xa438, 0X802c, }, + { 31, 0xa438, 0X1800, }, + { 31, 0xa438, 0X802c, }, + { 31, 0xa438, 0Xd700, }, + { 31, 0xa438, 0X6090, }, + { 31, 0xa438, 0X60d1, }, + { 31, 0xa438, 0Xc95c, }, + { 31, 0xa438, 0Xf007, }, + { 31, 0xa438, 0X60b1, }, + { 31, 0xa438, 0Xc95a, }, + { 31, 0xa438, 0Xf004, }, + { 31, 0xa438, 0Xc956, }, + { 31, 0xa438, 0Xf002, }, + { 31, 0xa438, 0Xc94e, }, + { 31, 0xa438, 0X1800, }, + { 31, 0xa438, 0X00cd, }, + { 31, 0xa438, 0Xd700, }, + { 31, 0xa438, 0X6090, }, + { 31, 0xa438, 0X60d1, }, + { 31, 0xa438, 0Xc95c, }, + { 31, 0xa438, 0Xf007, }, + { 31, 0xa438, 0X60b1, }, + { 31, 0xa438, 0Xc95a, }, + { 31, 0xa438, 0Xf004, }, + { 31, 0xa438, 0Xc956, }, + { 31, 0xa438, 0Xf002, }, + { 31, 0xa438, 0Xc94e, }, + { 31, 0xa438, 0X1000, }, + { 31, 0xa438, 0X022a, }, + { 31, 0xa438, 0X1800, }, + { 31, 0xa438, 0X0132, }, + { 31, 0xa436, 0XA08E, }, + { 31, 0xa438, 0Xffff, }, + { 31, 0xa436, 0XA08C, }, + { 31, 0xa438, 0Xffff, }, + { 31, 0xa436, 0XA08A, }, + { 31, 0xa438, 0Xffff, }, + { 31, 0xa436, 0XA088, }, + { 31, 0xa438, 0Xffff, }, + { 31, 0xa436, 0XA086, }, + { 31, 0xa438, 0Xffff, }, + { 31, 0xa436, 0XA084, }, + { 31, 0xa438, 0Xffff, }, + { 31, 0xa436, 0XA082, }, + { 31, 0xa438, 0X012f, }, + { 31, 0xa436, 0XA080, }, + { 31, 0xa438, 0X00cc, }, + { 31, 0xa436, 0XA090, }, + { 31, 0xa438, 0X0103, }, +}; + + +static const MMD_REG Rtl8226b_n2_ramcode[] = +{ + { 31, 0xa436, 0XA016, }, + { 31, 0xa438, 0X0020, }, + { 31, 0xa436, 0XA012, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa436, 0XA014, }, + { 31, 0xa438, 0X1800, }, + { 31, 0xa438, 0X8010, }, + { 31, 0xa438, 0X1800, }, + { 31, 0xa438, 0X8020, }, + { 31, 0xa438, 0X1800, }, + { 31, 0xa438, 0X802a, }, + { 31, 0xa438, 0X1800, }, + { 31, 0xa438, 0X8035, }, + { 31, 0xa438, 0X1800, }, + { 31, 0xa438, 0X803c, }, + { 31, 0xa438, 0X1800, }, + { 31, 0xa438, 0X803c, }, + { 31, 0xa438, 0X1800, }, + { 31, 0xa438, 0X803c, }, + { 31, 0xa438, 0X1800, }, + { 31, 0xa438, 0X803c, }, + { 31, 0xa438, 0Xd107, }, + { 31, 0xa438, 0Xd042, }, + { 31, 0xa438, 0Xa404, }, + { 31, 0xa438, 0X1000, }, + { 31, 0xa438, 0X09df, }, + { 31, 0xa438, 0Xd700, }, + { 31, 0xa438, 0X5fb4, }, + { 31, 0xa438, 0X8280, }, + { 31, 0xa438, 0Xd700, }, + { 31, 0xa438, 0X6065, }, + { 31, 0xa438, 0Xd125, }, + { 31, 0xa438, 0Xf002, }, + { 31, 0xa438, 0Xd12b, }, + { 31, 0xa438, 0Xd040, }, + { 31, 0xa438, 0X1800, }, + { 31, 0xa438, 0X077f, }, + { 31, 0xa438, 0X0cf0, }, + { 31, 0xa438, 0X0c50, }, + { 31, 0xa438, 0Xd104, }, + { 31, 0xa438, 0Xd040, }, + { 31, 0xa438, 0X1000, }, + { 31, 0xa438, 0X0aa8, }, + { 31, 0xa438, 0Xd700, }, + { 31, 0xa438, 0X5fb4, }, + { 31, 0xa438, 0X1800, }, + { 31, 0xa438, 0X0a2e, }, + { 31, 0xa438, 0Xcb9b, }, + { 31, 0xa438, 0Xd110, }, + { 31, 0xa438, 0Xd040, }, + { 31, 0xa438, 0X1000, }, + { 31, 0xa438, 0X0b7b, }, + { 31, 0xa438, 0X1000, }, + { 31, 0xa438, 0X09df, }, + { 31, 0xa438, 0Xd700, }, + { 31, 0xa438, 0X5fb4, }, + { 31, 0xa438, 0X1800, }, + { 31, 0xa438, 0X081b, }, + { 31, 0xa438, 0X1000, }, + { 31, 0xa438, 0X09df, }, + { 31, 0xa438, 0Xd704, }, + { 31, 0xa438, 0X7fb8, }, + { 31, 0xa438, 0Xa718, }, + { 31, 0xa438, 0X1800, }, + { 31, 0xa438, 0X074e, }, + { 31, 0xa436, 0XA10E, }, + { 31, 0xa438, 0Xffff, }, + { 31, 0xa436, 0XA10C, }, + { 31, 0xa438, 0Xffff, }, + { 31, 0xa436, 0XA10A, }, + { 31, 0xa438, 0Xffff, }, + { 31, 0xa436, 0XA108, }, + { 31, 0xa438, 0Xffff, }, + { 31, 0xa436, 0XA106, }, + { 31, 0xa438, 0X074d, }, + { 31, 0xa436, 0XA104, }, + { 31, 0xa438, 0X0818, }, + { 31, 0xa436, 0XA102, }, + { 31, 0xa438, 0X0a2c, }, + { 31, 0xa436, 0XA100, }, + { 31, 0xa438, 0X077e, }, + { 31, 0xa436, 0XA110, }, + { 31, 0xa438, 0X000f, }, + +}; + +static const MMD_REG Rtl8226b_uc2_ramcode[] = +{ + { 31, 0xa436, 0Xb87c, }, + { 31, 0xa438, 0X8625, }, + { 31, 0xa436, 0Xb87e, }, + { 31, 0xa438, 0Xaf86, }, + { 31, 0xa438, 0X3daf, }, + { 31, 0xa438, 0X8689, }, + { 31, 0xa438, 0Xaf88, }, + { 31, 0xa438, 0X69af, }, + { 31, 0xa438, 0X8887, }, + { 31, 0xa438, 0Xaf88, }, + { 31, 0xa438, 0X9caf, }, + { 31, 0xa438, 0X889c, }, + { 31, 0xa438, 0Xaf88, }, + { 31, 0xa438, 0X9caf, }, + { 31, 0xa438, 0X889c, }, + { 31, 0xa438, 0Xbf86, }, + { 31, 0xa438, 0X49d7, }, + { 31, 0xa438, 0X0040, }, + { 31, 0xa438, 0X0277, }, + { 31, 0xa438, 0X7daf, }, + { 31, 0xa438, 0X2727, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X7205, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X7208, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X71f3, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X71f6, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X7229, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X722c, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X7217, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X721a, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X721d, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X7211, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X7220, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X7214, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X722f, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X7223, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X7232, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X7226, }, + { 31, 0xa438, 0Xf8f9, }, + { 31, 0xa438, 0Xfae0, }, + { 31, 0xa438, 0X85b3, }, + { 31, 0xa438, 0X3802, }, + { 31, 0xa438, 0Xad27, }, + { 31, 0xa438, 0X02ae, }, + { 31, 0xa438, 0X03af, }, + { 31, 0xa438, 0X8830, }, + { 31, 0xa438, 0X1f66, }, + { 31, 0xa438, 0Xef65, }, + { 31, 0xa438, 0Xbfc2, }, + { 31, 0xa438, 0X1f1a, }, + { 31, 0xa438, 0X96f7, }, + { 31, 0xa438, 0X05ee, }, + { 31, 0xa438, 0Xffd2, }, + { 31, 0xa438, 0X00da, }, + { 31, 0xa438, 0Xf605, }, + { 31, 0xa438, 0Xbfc2, }, + { 31, 0xa438, 0X2f1a, }, + { 31, 0xa438, 0X96f7, }, + { 31, 0xa438, 0X05ee, }, + { 31, 0xa438, 0Xffd2, }, + { 31, 0xa438, 0X00db, }, + { 31, 0xa438, 0Xf605, }, + { 31, 0xa438, 0Xef02, }, + { 31, 0xa438, 0X1f11, }, + { 31, 0xa438, 0X0d42, }, + { 31, 0xa438, 0Xbf88, }, + { 31, 0xa438, 0X4202, }, + { 31, 0xa438, 0X6e7d, }, + { 31, 0xa438, 0Xef02, }, + { 31, 0xa438, 0X1b03, }, + { 31, 0xa438, 0X1f11, }, + { 31, 0xa438, 0X0d42, }, + { 31, 0xa438, 0Xbf88, }, + { 31, 0xa438, 0X4502, }, + { 31, 0xa438, 0X6e7d, }, + { 31, 0xa438, 0Xef02, }, + { 31, 0xa438, 0X1a03, }, + { 31, 0xa438, 0X1f11, }, + { 31, 0xa438, 0X0d42, }, + { 31, 0xa438, 0Xbf88, }, + { 31, 0xa438, 0X4802, }, + { 31, 0xa438, 0X6e7d, }, + { 31, 0xa438, 0Xbfc2, }, + { 31, 0xa438, 0X3f1a, }, + { 31, 0xa438, 0X96f7, }, + { 31, 0xa438, 0X05ee, }, + { 31, 0xa438, 0Xffd2, }, + { 31, 0xa438, 0X00da, }, + { 31, 0xa438, 0Xf605, }, + { 31, 0xa438, 0Xbfc2, }, + { 31, 0xa438, 0X4f1a, }, + { 31, 0xa438, 0X96f7, }, + { 31, 0xa438, 0X05ee, }, + { 31, 0xa438, 0Xffd2, }, + { 31, 0xa438, 0X00db, }, + { 31, 0xa438, 0Xf605, }, + { 31, 0xa438, 0Xef02, }, + { 31, 0xa438, 0X1f11, }, + { 31, 0xa438, 0X0d42, }, + { 31, 0xa438, 0Xbf88, }, + { 31, 0xa438, 0X4b02, }, + { 31, 0xa438, 0X6e7d, }, + { 31, 0xa438, 0Xef02, }, + { 31, 0xa438, 0X1b03, }, + { 31, 0xa438, 0X1f11, }, + { 31, 0xa438, 0X0d42, }, + { 31, 0xa438, 0Xbf88, }, + { 31, 0xa438, 0X4e02, }, + { 31, 0xa438, 0X6e7d, }, + { 31, 0xa438, 0Xef02, }, + { 31, 0xa438, 0X1a03, }, + { 31, 0xa438, 0X1f11, }, + { 31, 0xa438, 0X0d42, }, + { 31, 0xa438, 0Xbf88, }, + { 31, 0xa438, 0X5102, }, + { 31, 0xa438, 0X6e7d, }, + { 31, 0xa438, 0Xef56, }, + { 31, 0xa438, 0Xd020, }, + { 31, 0xa438, 0X1f11, }, + { 31, 0xa438, 0Xbf88, }, + { 31, 0xa438, 0X5402, }, + { 31, 0xa438, 0X6e7d, }, + { 31, 0xa438, 0Xbf88, }, + { 31, 0xa438, 0X5702, }, + { 31, 0xa438, 0X6e7d, }, + { 31, 0xa438, 0Xbf88, }, + { 31, 0xa438, 0X5a02, }, + { 31, 0xa438, 0X6e7d, }, + { 31, 0xa438, 0Xe185, }, + { 31, 0xa438, 0Xa0ef, }, + { 31, 0xa438, 0X0348, }, + { 31, 0xa438, 0X0a28, }, + { 31, 0xa438, 0X05ef, }, + { 31, 0xa438, 0X201b, }, + { 31, 0xa438, 0X01ad, }, + { 31, 0xa438, 0X2735, }, + { 31, 0xa438, 0X1f44, }, + { 31, 0xa438, 0Xe085, }, + { 31, 0xa438, 0X88e1, }, + { 31, 0xa438, 0X8589, }, + { 31, 0xa438, 0Xbf88, }, + { 31, 0xa438, 0X5d02, }, + { 31, 0xa438, 0X6e7d, }, + { 31, 0xa438, 0Xe085, }, + { 31, 0xa438, 0X8ee1, }, + { 31, 0xa438, 0X858f, }, + { 31, 0xa438, 0Xbf88, }, + { 31, 0xa438, 0X6002, }, + { 31, 0xa438, 0X6e7d, }, + { 31, 0xa438, 0Xe085, }, + { 31, 0xa438, 0X94e1, }, + { 31, 0xa438, 0X8595, }, + { 31, 0xa438, 0Xbf88, }, + { 31, 0xa438, 0X6302, }, + { 31, 0xa438, 0X6e7d, }, + { 31, 0xa438, 0Xe085, }, + { 31, 0xa438, 0X9ae1, }, + { 31, 0xa438, 0X859b, }, + { 31, 0xa438, 0Xbf88, }, + { 31, 0xa438, 0X6602, }, + { 31, 0xa438, 0X6e7d, }, + { 31, 0xa438, 0Xaf88, }, + { 31, 0xa438, 0X3cbf, }, + { 31, 0xa438, 0X883f, }, + { 31, 0xa438, 0X026e, }, + { 31, 0xa438, 0X9cad, }, + { 31, 0xa438, 0X2835, }, + { 31, 0xa438, 0X1f44, }, + { 31, 0xa438, 0Xe08f, }, + { 31, 0xa438, 0Xf8e1, }, + { 31, 0xa438, 0X8ff9, }, + { 31, 0xa438, 0Xbf88, }, + { 31, 0xa438, 0X5d02, }, + { 31, 0xa438, 0X6e7d, }, + { 31, 0xa438, 0Xe08f, }, + { 31, 0xa438, 0Xfae1, }, + { 31, 0xa438, 0X8ffb, }, + { 31, 0xa438, 0Xbf88, }, + { 31, 0xa438, 0X6002, }, + { 31, 0xa438, 0X6e7d, }, + { 31, 0xa438, 0Xe08f, }, + { 31, 0xa438, 0Xfce1, }, + { 31, 0xa438, 0X8ffd, }, + { 31, 0xa438, 0Xbf88, }, + { 31, 0xa438, 0X6302, }, + { 31, 0xa438, 0X6e7d, }, + { 31, 0xa438, 0Xe08f, }, + { 31, 0xa438, 0Xfee1, }, + { 31, 0xa438, 0X8fff, }, + { 31, 0xa438, 0Xbf88, }, + { 31, 0xa438, 0X6602, }, + { 31, 0xa438, 0X6e7d, }, + { 31, 0xa438, 0Xaf88, }, + { 31, 0xa438, 0X3ce1, }, + { 31, 0xa438, 0X85a1, }, + { 31, 0xa438, 0X1b21, }, + { 31, 0xa438, 0Xad37, }, + { 31, 0xa438, 0X341f, }, + { 31, 0xa438, 0X44e0, }, + { 31, 0xa438, 0X858a, }, + { 31, 0xa438, 0Xe185, }, + { 31, 0xa438, 0X8bbf, }, + { 31, 0xa438, 0X885d, }, + { 31, 0xa438, 0X026e, }, + { 31, 0xa438, 0X7de0, }, + { 31, 0xa438, 0X8590, }, + { 31, 0xa438, 0Xe185, }, + { 31, 0xa438, 0X91bf, }, + { 31, 0xa438, 0X8860, }, + { 31, 0xa438, 0X026e, }, + { 31, 0xa438, 0X7de0, }, + { 31, 0xa438, 0X8596, }, + { 31, 0xa438, 0Xe185, }, + { 31, 0xa438, 0X97bf, }, + { 31, 0xa438, 0X8863, }, + { 31, 0xa438, 0X026e, }, + { 31, 0xa438, 0X7de0, }, + { 31, 0xa438, 0X859c, }, + { 31, 0xa438, 0Xe185, }, + { 31, 0xa438, 0X9dbf, }, + { 31, 0xa438, 0X8866, }, + { 31, 0xa438, 0X026e, }, + { 31, 0xa438, 0X7dae, }, + { 31, 0xa438, 0X401f, }, + { 31, 0xa438, 0X44e0, }, + { 31, 0xa438, 0X858c, }, + { 31, 0xa438, 0Xe185, }, + { 31, 0xa438, 0X8dbf, }, + { 31, 0xa438, 0X885d, }, + { 31, 0xa438, 0X026e, }, + { 31, 0xa438, 0X7de0, }, + { 31, 0xa438, 0X8592, }, + { 31, 0xa438, 0Xe185, }, + { 31, 0xa438, 0X93bf, }, + { 31, 0xa438, 0X8860, }, + { 31, 0xa438, 0X026e, }, + { 31, 0xa438, 0X7de0, }, + { 31, 0xa438, 0X8598, }, + { 31, 0xa438, 0Xe185, }, + { 31, 0xa438, 0X99bf, }, + { 31, 0xa438, 0X8863, }, + { 31, 0xa438, 0X026e, }, + { 31, 0xa438, 0X7de0, }, + { 31, 0xa438, 0X859e, }, + { 31, 0xa438, 0Xe185, }, + { 31, 0xa438, 0X9fbf, }, + { 31, 0xa438, 0X8866, }, + { 31, 0xa438, 0X026e, }, + { 31, 0xa438, 0X7dae, }, + { 31, 0xa438, 0X0ce1, }, + { 31, 0xa438, 0X85b3, }, + { 31, 0xa438, 0X3904, }, + { 31, 0xa438, 0Xac2f, }, + { 31, 0xa438, 0X04ee, }, + { 31, 0xa438, 0X85b3, }, + { 31, 0xa438, 0X00af, }, + { 31, 0xa438, 0X39d9, }, + { 31, 0xa438, 0X22ac, }, + { 31, 0xa438, 0Xeaf0, }, + { 31, 0xa438, 0Xacf6, }, + { 31, 0xa438, 0Xf0ac, }, + { 31, 0xa438, 0Xfaf0, }, + { 31, 0xa438, 0Xacf8, }, + { 31, 0xa438, 0Xf0ac, }, + { 31, 0xa438, 0Xfcf0, }, + { 31, 0xa438, 0Xad00, }, + { 31, 0xa438, 0Xf0ac, }, + { 31, 0xa438, 0Xfef0, }, + { 31, 0xa438, 0Xacf0, }, + { 31, 0xa438, 0Xf0ac, }, + { 31, 0xa438, 0Xf4f0, }, + { 31, 0xa438, 0Xacf2, }, + { 31, 0xa438, 0Xf0ac, }, + { 31, 0xa438, 0Xb0f0, }, + { 31, 0xa438, 0Xacae, }, + { 31, 0xa438, 0Xf0ac, }, + { 31, 0xa438, 0Xacf0, }, + { 31, 0xa438, 0Xacaa, }, + { 31, 0xa438, 0Xa100, }, + { 31, 0xa438, 0X0ce1, }, + { 31, 0xa438, 0X8ff7, }, + { 31, 0xa438, 0Xbf88, }, + { 31, 0xa438, 0X8402, }, + { 31, 0xa438, 0X6e7d, }, + { 31, 0xa438, 0Xaf26, }, + { 31, 0xa438, 0Xe9e1, }, + { 31, 0xa438, 0X8ff6, }, + { 31, 0xa438, 0Xbf88, }, + { 31, 0xa438, 0X8402, }, + { 31, 0xa438, 0X6e7d, }, + { 31, 0xa438, 0Xaf26, }, + { 31, 0xa438, 0Xf520, }, + { 31, 0xa438, 0Xac86, }, + { 31, 0xa438, 0Xbf88, }, + { 31, 0xa438, 0X3f02, }, + { 31, 0xa438, 0X6e9c, }, + { 31, 0xa438, 0Xad28, }, + { 31, 0xa438, 0X03af, }, + { 31, 0xa438, 0X3324, }, + { 31, 0xa438, 0Xad38, }, + { 31, 0xa438, 0X03af, }, + { 31, 0xa438, 0X32e6, }, + { 31, 0xa438, 0Xaf32, }, + { 31, 0xa438, 0Xfb00, }, + { 31, 0xa436, 0Xb87c, }, + { 31, 0xa438, 0X8ff6, }, + { 31, 0xa436, 0Xb87e, }, + { 31, 0xa438, 0X0705, }, + { 31, 0xa436, 0Xb87c, }, + { 31, 0xa438, 0X8ff8, }, + { 31, 0xa436, 0Xb87e, }, + { 31, 0xa438, 0X19cc, }, + { 31, 0xa436, 0Xb87c, }, + { 31, 0xa438, 0X8ffa, }, + { 31, 0xa436, 0Xb87e, }, + { 31, 0xa438, 0X28e3, }, + { 31, 0xa436, 0Xb87c, }, + { 31, 0xa438, 0X8ffc, }, + { 31, 0xa436, 0Xb87e, }, + { 31, 0xa438, 0X1047, }, + { 31, 0xa436, 0Xb87c, }, + { 31, 0xa438, 0X8ffe, }, + { 31, 0xa436, 0Xb87e, }, + { 31, 0xa438, 0X0a45, }, + { 31, 0xa436, 0Xb85e, }, + { 31, 0xa438, 0X271E, }, + { 31, 0xa436, 0Xb860, }, + { 31, 0xa438, 0X3846, }, + { 31, 0xa436, 0Xb862, }, + { 31, 0xa438, 0X26E6, }, + { 31, 0xa436, 0Xb864, }, + { 31, 0xa438, 0X32E3, }, + { 31, 0xa436, 0Xb886, }, + { 31, 0xa438, 0Xffff, }, + { 31, 0xa436, 0Xb888, }, + { 31, 0xa438, 0Xffff, }, + { 31, 0xa436, 0Xb88a, }, + { 31, 0xa438, 0Xffff, }, + { 31, 0xa436, 0Xb88c, }, + { 31, 0xa438, 0Xffff, }, + { 31, 0xa436, 0Xb838, }, + { 31, 0xa438, 0X000f, }, + +}; + +static const MMD_REG Rtl8226b_uc_ramcode[] = +{ + { 31, 0xa436, 0X846e, }, + { 31, 0xa438, 0Xaf84, }, + { 31, 0xa438, 0X86af, }, + { 31, 0xa438, 0X8690, }, + { 31, 0xa438, 0Xaf86, }, + { 31, 0xa438, 0Xa4af, }, + { 31, 0xa438, 0X86a4, }, + { 31, 0xa438, 0Xaf86, }, + { 31, 0xa438, 0Xa4af, }, + { 31, 0xa438, 0X86a4, }, + { 31, 0xa438, 0Xaf86, }, + { 31, 0xa438, 0Xa4af, }, + { 31, 0xa438, 0X86a4, }, + { 31, 0xa438, 0Xee82, }, + { 31, 0xa438, 0X5f00, }, + { 31, 0xa438, 0X0284, }, + { 31, 0xa438, 0X90af, }, + { 31, 0xa438, 0X0441, }, + { 31, 0xa438, 0Xf8e0, }, + { 31, 0xa438, 0X8ff3, }, + { 31, 0xa438, 0Xa000, }, + { 31, 0xa438, 0X0502, }, + { 31, 0xa438, 0X84a4, }, + { 31, 0xa438, 0Xae06, }, + { 31, 0xa438, 0Xa001, }, + { 31, 0xa438, 0X0302, }, + { 31, 0xa438, 0X84c8, }, + { 31, 0xa438, 0Xfc04, }, + { 31, 0xa438, 0Xf8f9, }, + { 31, 0xa438, 0Xef59, }, + { 31, 0xa438, 0Xe080, }, + { 31, 0xa438, 0X15ad, }, + { 31, 0xa438, 0X2702, }, + { 31, 0xa438, 0Xae03, }, + { 31, 0xa438, 0Xaf84, }, + { 31, 0xa438, 0Xc3bf, }, + { 31, 0xa438, 0X53ca, }, + { 31, 0xa438, 0X0252, }, + { 31, 0xa438, 0Xc8ad, }, + { 31, 0xa438, 0X2807, }, + { 31, 0xa438, 0X0285, }, + { 31, 0xa438, 0X2cee, }, + { 31, 0xa438, 0X8ff3, }, + { 31, 0xa438, 0X01ef, }, + { 31, 0xa438, 0X95fd, }, + { 31, 0xa438, 0Xfc04, }, + { 31, 0xa438, 0Xf8f9, }, + { 31, 0xa438, 0Xfaef, }, + { 31, 0xa438, 0X69bf, }, + { 31, 0xa438, 0X53ca, }, + { 31, 0xa438, 0X0252, }, + { 31, 0xa438, 0Xc8ac, }, + { 31, 0xa438, 0X2822, }, + { 31, 0xa438, 0Xd480, }, + { 31, 0xa438, 0X00bf, }, + { 31, 0xa438, 0X8684, }, + { 31, 0xa438, 0X0252, }, + { 31, 0xa438, 0Xa9bf, }, + { 31, 0xa438, 0X8687, }, + { 31, 0xa438, 0X0252, }, + { 31, 0xa438, 0Xa9bf, }, + { 31, 0xa438, 0X868a, }, + { 31, 0xa438, 0X0252, }, + { 31, 0xa438, 0Xa9bf, }, + { 31, 0xa438, 0X868d, }, + { 31, 0xa438, 0X0252, }, + { 31, 0xa438, 0Xa9ee, }, + { 31, 0xa438, 0X8ff3, }, + { 31, 0xa438, 0X00af, }, + { 31, 0xa438, 0X8526, }, + { 31, 0xa438, 0Xe08f, }, + { 31, 0xa438, 0Xf4e1, }, + { 31, 0xa438, 0X8ff5, }, + { 31, 0xa438, 0Xe28f, }, + { 31, 0xa438, 0Xf6e3, }, + { 31, 0xa438, 0X8ff7, }, + { 31, 0xa438, 0X1b45, }, + { 31, 0xa438, 0Xac27, }, + { 31, 0xa438, 0X0eee, }, + { 31, 0xa438, 0X8ff4, }, + { 31, 0xa438, 0X00ee, }, + { 31, 0xa438, 0X8ff5, }, + { 31, 0xa438, 0X0002, }, + { 31, 0xa438, 0X852c, }, + { 31, 0xa438, 0Xaf85, }, + { 31, 0xa438, 0X26e0, }, + { 31, 0xa438, 0X8ff4, }, + { 31, 0xa438, 0Xe18f, }, + { 31, 0xa438, 0Xf52c, }, + { 31, 0xa438, 0X0001, }, + { 31, 0xa438, 0Xe48f, }, + { 31, 0xa438, 0Xf4e5, }, + { 31, 0xa438, 0X8ff5, }, + { 31, 0xa438, 0Xef96, }, + { 31, 0xa438, 0Xfefd, }, + { 31, 0xa438, 0Xfc04, }, + { 31, 0xa438, 0Xf8f9, }, + { 31, 0xa438, 0Xef59, }, + { 31, 0xa438, 0Xbf53, }, + { 31, 0xa438, 0X2202, }, + { 31, 0xa438, 0X52c8, }, + { 31, 0xa438, 0Xa18b, }, + { 31, 0xa438, 0X02ae, }, + { 31, 0xa438, 0X03af, }, + { 31, 0xa438, 0X85da, }, + { 31, 0xa438, 0Xbf57, }, + { 31, 0xa438, 0X7202, }, + { 31, 0xa438, 0X52c8, }, + { 31, 0xa438, 0Xe48f, }, + { 31, 0xa438, 0Xf8e5, }, + { 31, 0xa438, 0X8ff9, }, + { 31, 0xa438, 0Xbf57, }, + { 31, 0xa438, 0X7502, }, + { 31, 0xa438, 0X52c8, }, + { 31, 0xa438, 0Xe48f, }, + { 31, 0xa438, 0Xfae5, }, + { 31, 0xa438, 0X8ffb, }, + { 31, 0xa438, 0Xbf57, }, + { 31, 0xa438, 0X7802, }, + { 31, 0xa438, 0X52c8, }, + { 31, 0xa438, 0Xe48f, }, + { 31, 0xa438, 0Xfce5, }, + { 31, 0xa438, 0X8ffd, }, + { 31, 0xa438, 0Xbf57, }, + { 31, 0xa438, 0X7b02, }, + { 31, 0xa438, 0X52c8, }, + { 31, 0xa438, 0Xe48f, }, + { 31, 0xa438, 0Xfee5, }, + { 31, 0xa438, 0X8fff, }, + { 31, 0xa438, 0Xbf57, }, + { 31, 0xa438, 0X6c02, }, + { 31, 0xa438, 0X52c8, }, + { 31, 0xa438, 0Xa102, }, + { 31, 0xa438, 0X13ee, }, + { 31, 0xa438, 0X8ffc, }, + { 31, 0xa438, 0X80ee, }, + { 31, 0xa438, 0X8ffd, }, + { 31, 0xa438, 0X00ee, }, + { 31, 0xa438, 0X8ffe, }, + { 31, 0xa438, 0X80ee, }, + { 31, 0xa438, 0X8fff, }, + { 31, 0xa438, 0X00af, }, + { 31, 0xa438, 0X8599, }, + { 31, 0xa438, 0Xa101, }, + { 31, 0xa438, 0X0cbf, }, + { 31, 0xa438, 0X534c, }, + { 31, 0xa438, 0X0252, }, + { 31, 0xa438, 0Xc8a1, }, + { 31, 0xa438, 0X0303, }, + { 31, 0xa438, 0Xaf85, }, + { 31, 0xa438, 0X77bf, }, + { 31, 0xa438, 0X5322, }, + { 31, 0xa438, 0X0252, }, + { 31, 0xa438, 0Xc8a1, }, + { 31, 0xa438, 0X8b02, }, + { 31, 0xa438, 0Xae03, }, + { 31, 0xa438, 0Xaf86, }, + { 31, 0xa438, 0X64e0, }, + { 31, 0xa438, 0X8ff8, }, + { 31, 0xa438, 0Xe18f, }, + { 31, 0xa438, 0Xf9bf, }, + { 31, 0xa438, 0X8684, }, + { 31, 0xa438, 0X0252, }, + { 31, 0xa438, 0Xa9e0, }, + { 31, 0xa438, 0X8ffa, }, + { 31, 0xa438, 0Xe18f, }, + { 31, 0xa438, 0Xfbbf, }, + { 31, 0xa438, 0X8687, }, + { 31, 0xa438, 0X0252, }, + { 31, 0xa438, 0Xa9e0, }, + { 31, 0xa438, 0X8ffc, }, + { 31, 0xa438, 0Xe18f, }, + { 31, 0xa438, 0Xfdbf, }, + { 31, 0xa438, 0X868a, }, + { 31, 0xa438, 0X0252, }, + { 31, 0xa438, 0Xa9e0, }, + { 31, 0xa438, 0X8ffe, }, + { 31, 0xa438, 0Xe18f, }, + { 31, 0xa438, 0Xffbf, }, + { 31, 0xa438, 0X868d, }, + { 31, 0xa438, 0X0252, }, + { 31, 0xa438, 0Xa9af, }, + { 31, 0xa438, 0X867f, }, + { 31, 0xa438, 0Xbf53, }, + { 31, 0xa438, 0X2202, }, + { 31, 0xa438, 0X52c8, }, + { 31, 0xa438, 0Xa144, }, + { 31, 0xa438, 0X3cbf, }, + { 31, 0xa438, 0X547b, }, + { 31, 0xa438, 0X0252, }, + { 31, 0xa438, 0Xc8e4, }, + { 31, 0xa438, 0X8ff8, }, + { 31, 0xa438, 0Xe58f, }, + { 31, 0xa438, 0Xf9bf, }, + { 31, 0xa438, 0X547e, }, + { 31, 0xa438, 0X0252, }, + { 31, 0xa438, 0Xc8e4, }, + { 31, 0xa438, 0X8ffa, }, + { 31, 0xa438, 0Xe58f, }, + { 31, 0xa438, 0Xfbbf, }, + { 31, 0xa438, 0X5481, }, + { 31, 0xa438, 0X0252, }, + { 31, 0xa438, 0Xc8e4, }, + { 31, 0xa438, 0X8ffc, }, + { 31, 0xa438, 0Xe58f, }, + { 31, 0xa438, 0Xfdbf, }, + { 31, 0xa438, 0X5484, }, + { 31, 0xa438, 0X0252, }, + { 31, 0xa438, 0Xc8e4, }, + { 31, 0xa438, 0X8ffe, }, + { 31, 0xa438, 0Xe58f, }, + { 31, 0xa438, 0Xffbf, }, + { 31, 0xa438, 0X5322, }, + { 31, 0xa438, 0X0252, }, + { 31, 0xa438, 0Xc8a1, }, + { 31, 0xa438, 0X4448, }, + { 31, 0xa438, 0Xaf85, }, + { 31, 0xa438, 0Xa7bf, }, + { 31, 0xa438, 0X5322, }, + { 31, 0xa438, 0X0252, }, + { 31, 0xa438, 0Xc8a1, }, + { 31, 0xa438, 0X313c, }, + { 31, 0xa438, 0Xbf54, }, + { 31, 0xa438, 0X7b02, }, + { 31, 0xa438, 0X52c8, }, + { 31, 0xa438, 0Xe48f, }, + { 31, 0xa438, 0Xf8e5, }, + { 31, 0xa438, 0X8ff9, }, + { 31, 0xa438, 0Xbf54, }, + { 31, 0xa438, 0X7e02, }, + { 31, 0xa438, 0X52c8, }, + { 31, 0xa438, 0Xe48f, }, + { 31, 0xa438, 0Xfae5, }, + { 31, 0xa438, 0X8ffb, }, + { 31, 0xa438, 0Xbf54, }, + { 31, 0xa438, 0X8102, }, + { 31, 0xa438, 0X52c8, }, + { 31, 0xa438, 0Xe48f, }, + { 31, 0xa438, 0Xfce5, }, + { 31, 0xa438, 0X8ffd, }, + { 31, 0xa438, 0Xbf54, }, + { 31, 0xa438, 0X8402, }, + { 31, 0xa438, 0X52c8, }, + { 31, 0xa438, 0Xe48f, }, + { 31, 0xa438, 0Xfee5, }, + { 31, 0xa438, 0X8fff, }, + { 31, 0xa438, 0Xbf53, }, + { 31, 0xa438, 0X2202, }, + { 31, 0xa438, 0X52c8, }, + { 31, 0xa438, 0Xa131, }, + { 31, 0xa438, 0X03af, }, + { 31, 0xa438, 0X85a7, }, + { 31, 0xa438, 0Xd480, }, + { 31, 0xa438, 0X00bf, }, + { 31, 0xa438, 0X8684, }, + { 31, 0xa438, 0X0252, }, + { 31, 0xa438, 0Xa9bf, }, + { 31, 0xa438, 0X8687, }, + { 31, 0xa438, 0X0252, }, + { 31, 0xa438, 0Xa9bf, }, + { 31, 0xa438, 0X868a, }, + { 31, 0xa438, 0X0252, }, + { 31, 0xa438, 0Xa9bf, }, + { 31, 0xa438, 0X868d, }, + { 31, 0xa438, 0X0252, }, + { 31, 0xa438, 0Xa9ef, }, + { 31, 0xa438, 0X95fd, }, + { 31, 0xa438, 0Xfc04, }, + { 31, 0xa438, 0Xf0d1, }, + { 31, 0xa438, 0X2af0, }, + { 31, 0xa438, 0Xd12c, }, + { 31, 0xa438, 0Xf0d1, }, + { 31, 0xa438, 0X44f0, }, + { 31, 0xa438, 0Xd146, }, + { 31, 0xa438, 0Xbf86, }, + { 31, 0xa438, 0Xa102, }, + { 31, 0xa438, 0X52c8, }, + { 31, 0xa438, 0Xbf86, }, + { 31, 0xa438, 0Xa102, }, + { 31, 0xa438, 0X52c8, }, + { 31, 0xa438, 0Xd101, }, + { 31, 0xa438, 0Xaf06, }, + { 31, 0xa438, 0Xa570, }, + { 31, 0xa438, 0Xce42, }, + { 31, 0xa436, 0Xb818, }, + { 31, 0xa438, 0X043d, }, + { 31, 0xa436, 0Xb81a, }, + { 31, 0xa438, 0X06a3, }, + { 31, 0xa436, 0Xb81c, }, + { 31, 0xa438, 0Xffff, }, + { 31, 0xa436, 0Xb81e, }, + { 31, 0xa438, 0Xffff, }, + { 31, 0xa436, 0Xb850, }, + { 31, 0xa438, 0Xffff, }, + { 31, 0xa436, 0Xb852, }, + { 31, 0xa438, 0Xffff, }, + { 31, 0xa436, 0Xb878, }, + { 31, 0xa438, 0Xffff, }, + { 31, 0xa436, 0Xb884, }, + { 31, 0xa438, 0Xffff, }, + { 31, 0xa436, 0Xb832, }, + { 31, 0xa438, 0X0003, }, + +}; + +static const MMD_REG Rtl8226b_data_ramcode[] = +{ + +}; + +static const MMD_REG Rtl8226b_isram_patch[] = +{ + +}; + +static BOOL +Rtl8226b_wait_for_bit( + IN HANDLE hDevice, + IN UINT16 dev, + IN UINT16 addr, + IN UINT16 mask, + IN BOOL set, + IN UINT16 timeoutms) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + while (--timeoutms) { + status = MmdPhyRead(hDevice, MMD_VEND2, addr, &phydata); + if (!status) + goto exit; + + if (!set) + phydata = ~phydata; + + if ((phydata & mask) == mask) + return SUCCESS; + SLEEP_1MS; + } + printf("Timeout (dev=%02x addr=0x%02x mask=0x%02x timeout=%d)\n", + dev, addr, mask, timeoutms); + +exit: + return FAILURE; +} + +BOOLEAN +Rtl8226b_phy_init( + IN HANDLE hDevice, + IN PHY_LINK_ABILITY *pphylinkability, + IN BOOL singlephy + ) +{ + BOOL status = FAILURE; + UINT16 i = 0; /* SW_SDK: use UINT16 instead of UINT8, for MMD_REG array may over 255 entries */ + UINT16 phydata = 0,rev_num,mod_num; + const UINT16 patchver = 0x0020, patchaddr = 0x8024; + UINT16 org_id = 0, rev_id = 0; + + MmdPhyRead(hDevice, MMD_PMAPMD, 0x02, &org_id); + MmdPhyRead(hDevice, MMD_PMAPMD, 0x03, &rev_id); + phydata = (org_id<<16) | rev_id; + printf("[rtl8221b] Rtl8226b_phy_init: phy_adress=%d, phy_id=0x%x\r\n", MMD_PMAPMD, phydata); + + // Polling PHY Status + status = Rtl8226b_wait_for_bit(hDevice, MMD_VEND2, 0xA420, 0x3, 1, 100); + if (status != SUCCESS) + goto exit; + + // Check phy id, no need to init 8221B_VB/VM + status = MmdPhyRead(hDevice, MMD_PMAPMD, 0x03, &phydata); + if (status != SUCCESS) + goto exit; + rev_num = phydata&0x000f; + mod_num = (phydata>>4)&0x003f; + if ((rev_num == 8) &&(mod_num == 4)) { + //printf("rtl8221b and go init flow...\n"); + } + else{ + //printf("Not rtl8221b and skip init flow...id = %x \n",phydata); + goto exit; + } + + // MMD 31.0xA436[15:0] = 0x801E + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA436, 0x801E); + if (status != SUCCESS) + goto exit; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA438, &phydata); + if (status != SUCCESS) + goto exit; + + // Already patched. + if (phydata == patchver) + { + status = 1; + goto exit; + } + else + { + // Patch request & wait patch_rdy (for normal patch flow - Driver Initialize) + // MMD 31.0xB820[4] = 1'b1 //(patch request) + status = MmdPhyRead(hDevice, MMD_VEND2, 0xB820, &phydata); + if (status != SUCCESS) + goto exit; + + phydata |= BIT_4; + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xB820, phydata); + if (status != SUCCESS) + goto exit; + + //wait for patch ready = 1 (MMD 31.0xB800[6]) + status = Rtl8226b_wait_for_bit(hDevice, MMD_VEND2, 0xB800, BIT_6, 1, 100); + if (status != SUCCESS) + goto exit; + + //Set patch_key & patch_lock + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA436, patchaddr); + if (status != SUCCESS) + goto exit; + + // MMD 31.0xA438[15:0] = 0x3701 + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA438, 0x3701); + if (status != SUCCESS) + goto exit; + + // MMD 31.0xA436[15:0] = 0xB82E + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA436, 0xB82E); + if (status != SUCCESS) + goto exit; + + // MMD 31.0xA438[15:0] = 0x0001 + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA438, 0x0001); + if (status != SUCCESS) + goto exit; + + // NC & UC patch + status = MmdPhyRead(hDevice, MMD_VEND2, 0xB820, &phydata); + if (status != SUCCESS) + goto exit; + + phydata |= BIT_7; + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xB820, phydata); + if (status != SUCCESS) + goto exit; + + // patch nc0 + for(i=0; i +#include +#endif + +#define BIT_0 0x0001 +#define BIT_1 0x0002 +#define BIT_2 0x0004 +#define BIT_3 0x0008 +#define BIT_4 0x0010 +#define BIT_5 0x0020 +#define BIT_6 0x0040 +#define BIT_7 0x0080 +#define BIT_8 0x0100 +#define BIT_9 0x0200 +#define BIT_10 0x0400 +#define BIT_11 0x0800 +#define BIT_12 0x1000 +#define BIT_13 0x2000 +#define BIT_14 0x4000 +#define BIT_15 0x8000 + +#define SUCCESS TRUE +#define FAILURE FALSE + + +#if 0 +typedef struct { + uint32 unit; + uint32 port; +} HANDLE; +#else +typedef struct { + unsigned int unit; + unsigned int port; +} HANDLE; +#endif + +#ifndef bool + #define bool int +#endif + +#if 0 +#define BOOLEAN bool +#define BOOL uint32 +#define UINT32 uint32 +#define UINT16 uint16 +#define UINT8 uint8 +#define Sleep(_t) osal_time_udelay(_t*1000) +#else +#define TRUE 1 +#define FALSE 0 + +#define BOOLEAN bool +#define BOOL unsigned int +#define UINT32 unsigned int +#define UINT16 unsigned short +#define UINT8 char +#define SLEEP_1MS udelay(1000) +#define SLEEP_100MS mdelay(100) +#endif +#define IN +#define OUT + + +#define MMD_PMAPMD 1 +#define MMD_PCS 3 +#define MMD_AN 7 +#define MMD_VEND1 30 /* Vendor specific 2 */ +#define MMD_VEND2 31 /* Vendor specific 2 */ + + +typedef struct +{ + UINT16 dev; + UINT16 addr; + UINT16 value; +} MMD_REG; + + +#define NO_LINK 0 +#define LINK_SPEED_10M 10 +#define LINK_SPEED_100M 100 +#define LINK_SPEED_500M 500 +#define LINK_SPEED_1G 1000 +#define LINK_SPEED_2P5G 2500 + +typedef enum +{ + PHY_CROSSPVER_MODE_AUTO = 0, + PHY_CROSSPVER_MODE_MDI, + PHY_CROSSPVER_MODE_MDIX, + PHY_CROSSPVER_MODE_END +} PHY_CROSSPVER_MODE; + +typedef enum +{ + PHY_CROSSPVER_STATUS_MDI = 0, + PHY_CROSSPVER_STATUS_MDIX, + PHY_CROSSPVER_STATUS_END +} PHY_CROSSPVER_STATUS; + +typedef enum +{ + PHY_AUTO_MODE = 0, + PHY_SLAVE_MODE, + PHY_MASTER_MODE, + PHY_MASTER_SLAVE_END +} PHY_MASTERSLAVE_MODE; + +typedef struct +{ + UINT32 Half_10:1; + UINT32 Full_10:1; + + UINT32 Half_100:1; + UINT32 Full_100:1; + + UINT32 Full_1000:1; + + UINT32 adv_2_5G:1; + + UINT32 FC:1; + UINT32 AsyFC:1; +} PHY_LINK_ABILITY; + +typedef struct +{ + UINT8 EEE_100:1; + UINT8 EEE_1000:1; + UINT8 EEE_2_5G:1; +} PHY_EEE_ENABLE; + +typedef struct +{ + UINT8 TX_SWAP:1; + UINT8 RX_SWAP:1; +} PHY_SERDES_POLARITY_SWAP; + +typedef enum +{ + TESTMODE_CHANNEL_NONE = 0, + TESTMODE_CHANNEL_A, + TESTMODE_CHANNEL_B, + TESTMODE_CHANNEL_C, + TESTMODE_CHANNEL_D, + TESTMODE_CHANNEL_END +} PHY_TESTMODE_CHANNEL; + +typedef struct +{ + UINT32 TM1:1; + UINT32 TM2:1; + UINT32 TM3:1; + UINT32 TM4:1; + UINT32 TM5:1; + UINT32 TM6:1; + + UINT32 TONE1:1; + UINT32 TONE2:1; + UINT32 TONE3:1; + UINT32 TONE4:1; + UINT32 TONE5:1; + + UINT32 TMFINISH:1; + + UINT32 NORMAL:1; + UINT32 HARMONIC:1; + UINT32 LINKPLUSE:1; + + PHY_TESTMODE_CHANNEL channel:3; +} PHY_IEEE_TEST_MODE; + +typedef enum +{ + MIS_MATCH_OPEN = 1, // Mis-Match_Open, larger_than_130ohm + MIS_MATCH_SHORT = 2, // Mis-Match_short, less_than_77ohm +} PHY_RTCT_STATUS_MISMATCH; + +typedef struct +{ + BOOL Open; + BOOL Short; + PHY_RTCT_STATUS_MISMATCH Mismatch; +} PHY_RTCT_STATUS; + +typedef struct +{ + + UINT16 linkType; + + UINT32 rxLen; + UINT32 txLen; + + UINT32 channelALen; + UINT32 channelBLen; + UINT32 channelCLen; + UINT32 channelDLen; + + PHY_RTCT_STATUS channelAStatus; + PHY_RTCT_STATUS channelBStatus; + PHY_RTCT_STATUS channelCStatus; + PHY_RTCT_STATUS channelDStatus; +} PHY_RTCT_RESULT; + +typedef enum +{ + PHY_SERDES_MODE_OTHER = 0, + PHY_SERDES_MODE_SGMII, + PHY_SERDES_MODE_HiSGMII, + PHY_SERDES_MODE_2500BASEX, + PHY_SERDES_MODE_USXGMII, + PHY_SERDES_MODE_NO_SDS, + PHY_SERDES_MODE_END +} PHY_SERDES_MODE; + +typedef enum +{ + PHY_SERDES_OPTION_2500BASEX_SGMII = 0, + PHY_SERDES_OPTION_HiSGMII_SGMII, + PHY_SERDES_OPTION_2500BASEX, + PHY_SERDES_OPTION_HiSGMII, + PHY_SERDES_OPTION_OTHER, +} PHY_SERDES_OPTION; + +typedef struct +{ + UINT16 MASK15_0; + UINT16 MASK31_16; + UINT16 MASK47_32; + UINT16 MASK63_48; + UINT16 MASK79_64; + UINT16 MASK95_80; + UINT16 MASK111_96; + UINT16 MASK127_112; + UINT16 CRC; +} PHY_WAKEUP_FRAME; + +typedef struct +{ + UINT16 REG15_0; + UINT16 REG31_16; + UINT16 REG47_32; + UINT16 REG63_48; +} PHY_MULTICAST_REG; + +typedef struct +{ + UINT16 ADDR15_0; + UINT16 ADDR31_16; + UINT16 ADDR47_32; +} PHY_MAC_ADDRESS; + +typedef struct +{ + UINT32 LINKCHG:1; + UINT32 MAGIC:1; + UINT32 ARBITRARY:1; + UINT32 UNICAST:1; + UINT32 MULTICAST:1; + UINT32 BROADCAST:1; + + UINT32 FRAME0:1; + UINT32 FRAME1:1; + UINT32 FRAME2:1; + UINT32 FRAME3:1; + UINT32 FRAME4:1; + UINT32 FRAME5:1; + UINT32 FRAME6:1; + UINT32 FRAME7:1; + + UINT32 MAXPKTLENGTH; + PHY_MAC_ADDRESS macaddress; + PHY_MULTICAST_REG multicast; + + PHY_WAKEUP_FRAME wakeframe0; + +} PHY_WOL_EVENT; + +typedef struct +{ + bool Enable; + UINT16 Temperature; + UINT16 Temperature_threshold; +}PHY_THERMAL_RESULT; + + +BOOLEAN +MmdPhyRead( + IN HANDLE hDevice, + IN UINT16 dev, + IN UINT16 addr, + OUT UINT16 *data); + +BOOLEAN +MmdPhyWrite( + IN HANDLE hDevice, + IN UINT16 dev, + IN UINT16 addr, + IN UINT16 data); + + + + +#endif /* __NIC_RTL8226_TYPEDEF_H__ */ + + diff --git a/sources/uboot-be550/drivers/net/rtl8221b/rtl8226b_mdio.c b/sources/uboot-be550/drivers/net/rtl8221b/rtl8226b_mdio.c new file mode 100644 index 00000000..46299330 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8221b/rtl8226b_mdio.c @@ -0,0 +1,78 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * Unless you and Realtek execute a separate written software license + * agreement governing use of this software, this software is licensed + * to you under the terms of the GNU General Public License version 2, + * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt + * + * Purpose : RTL8367C switch low-level function for access register + * Feature : SMI related functions + * + */ + #include + #include + #include "./rtl8226_typedef.h" + #include + //#include "./rtl8226b_mdio.h" + +/* default PHY ID 1 */ +#define MDC_MDIO_PHY_ID (6) + +#define MII_ADDR_C45 (1<<30) + +extern spinlock_t reg_access; + +extern int qca_mdio_read(unsigned int dev_id, unsigned int phy_addr, unsigned int reg, unsigned int *data); +extern int qca_mdio_write(unsigned int dev_id, unsigned int phy_addr, unsigned int reg, unsigned int data); + +/*mii_mgr_read/mii_mgr_write is the callback API for rtl8367 driver*/ +unsigned int mii_mgr_read(unsigned int phy_addr, unsigned int phy_register, unsigned int *read_data) +{ + spin_lock_bh(®_access); + qca_mdio_read(1, phy_addr, phy_register, read_data); + spin_unlock_bh(®_access); + + return 0; +} + +unsigned int mii_mgr_write(unsigned int phy_addr, unsigned int phy_register, unsigned int write_data) +{ + spin_lock_bh(®_access); + qca_mdio_write(1, phy_addr, phy_register, write_data); + spin_unlock_bh(®_access); + return 0; +} + +int rtl8226_mdio_write(unsigned short devad, int regnum, unsigned short val) +{ + regnum = MII_ADDR_C45 | ((devad & 0x1f) << 16) | (regnum & 0xffff); + + mii_mgr_write(MDC_MDIO_PHY_ID, regnum, val); + return SUCCESS; +} + +int rtl8226_mdio_read(unsigned short devad, int regnum, unsigned short *data) +{ + unsigned int temp_data = 0; + regnum = MII_ADDR_C45 | (devad << 16) | (regnum & 0xffff); + + mii_mgr_read(MDC_MDIO_PHY_ID, regnum, &temp_data); + if (data) + *data = temp_data; + + return SUCCESS; +} + +BOOLEAN +MmdPhyRead( IN HANDLE hDevice, IN UINT16 dev, IN UINT16 addr, OUT UINT16 *data) +{ + return rtl8226_mdio_read(dev, (int)addr, data); +} + +BOOLEAN +MmdPhyWrite( IN HANDLE hDevice, IN UINT16 dev, IN UINT16 addr, IN UINT16 data) +{ + return rtl8226_mdio_write(dev, addr, data); +} diff --git a/sources/uboot-be550/drivers/net/rtl8251b/Makefile b/sources/uboot-be550/drivers/net/rtl8251b/Makefile new file mode 100644 index 00000000..7d851609 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8251b/Makefile @@ -0,0 +1,17 @@ +LOC_DIR=/src/init/rtl8251b +LIB=HSL + +include $(PRJ_PATH)/make/config.mk + +SRC_LIST= + +ifeq (TRUE, $(IN_RTL8251B_PHY)) + SRC_LIST += nic_rtl8251b.c nic_rtl8251b_init.c rtl8251b.c + EXTRA_CFLAGS += -DMDC_MDIO_OPERATION +endif + +include $(PRJ_PATH)/make/components.mk +include $(PRJ_PATH)/make/defs.mk +include $(PRJ_PATH)/make/target.mk + +all: dep obj diff --git a/sources/uboot-be550/drivers/net/rtl8251b/nic_rtl8251b.c b/sources/uboot-be550/drivers/net/rtl8251b/nic_rtl8251b.c new file mode 100755 index 00000000..84cfaa86 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8251b/nic_rtl8251b.c @@ -0,0 +1,2556 @@ +/* + * Copyright (C) 2019 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : PHY 8251b Driver + * + * Feature : PHY 8251b Driver + * + */ + + +// #include +// #include +// #include +// #include +// #include +// #include +#include "rtl8251b_typedef.h" +#include "nic_rtl8251b.h" +#include "nic_rtl8251b_init.h" + + +BOOLEAN +Rtl8251b_phy_reset( + IN HANDLE hDevice + ) +{ + BOOL status = FAILURE; + UINT16 phydata0 = 0, phydata1 = 0; + UINT16 waitcount = 0; + + status = MmdPhyRead(hDevice, MMD_PMAPMD, 0x0, &phydata0); + if (status != SUCCESS) + goto exit; + + phydata1 |= BIT_15; + + status = MmdPhyWrite(hDevice, MMD_PMAPMD, 0x0, phydata1); + if (status != SUCCESS) + goto exit; + + while(TRUE) + { + status = MmdPhyRead(hDevice, MMD_PMAPMD, 0x0, &phydata1); + if (status != SUCCESS) + goto exit; + + if (!(phydata1 & BIT_15)) + break; + + if (++waitcount == 500) + { + status = FAILURE; + goto exit; + } + } + + status = MmdPhyWrite(hDevice, MMD_PMAPMD, 0x0, phydata0); + if (status != SUCCESS) + goto exit; + +exit: + return status; +} + +BOOLEAN +Rtl8251b_autoNegoEnable_get( + IN HANDLE hDevice, + OUT BOOL *pEnable + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + status = MmdPhyRead(hDevice, MMD_AN, 0, &phydata); + if (status != SUCCESS) + goto exit; + + *pEnable = (phydata & BIT_12) ? (TRUE) : (FALSE); + +exit: + return status; +} + +BOOLEAN +Rtl8251b_autoNegoEnable_set( + IN HANDLE hDevice, + IN BOOL Enable + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + // AutoNegotiationEnable + status = MmdPhyRead(hDevice, MMD_AN, 0, &phydata); + if (status != SUCCESS) + goto exit; + + if (Enable) + phydata |= BIT_12; + else + phydata &= (~BIT_12); + + status = MmdPhyWrite(hDevice, MMD_AN, 0, phydata); + if (status != SUCCESS) + goto exit; + + // RestartAutoNegotiation + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA400, &phydata); + if (status != SUCCESS) + goto exit; + + phydata |= BIT_9; + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA400, phydata); + if (status != SUCCESS) + goto exit; + +exit: + return status; +} + + +BOOLEAN +Rtl8251b_autoNegoRestart( + IN HANDLE hDevice + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + // RestartAutoNegotiation + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA400, &phydata); + if (status != SUCCESS) + goto exit; + + phydata |= BIT_9; + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA400, phydata); + if (status != SUCCESS) + goto exit; + +exit: + return status; +} + +BOOLEAN +Rtl8251b_autoNegoAbility_get( + IN HANDLE hDevice, + OUT PHY_LINK_ABILITY *pPhyAbility + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + status = MmdPhyRead(hDevice, MMD_AN, 16, &phydata); + if (status != SUCCESS) + goto exit; + + // 10M + pPhyAbility->Half_10 = (phydata & BIT_5) ? (1) : (0); + pPhyAbility->Full_10 = (phydata & BIT_6) ? (1) : (0); + + // 100M + pPhyAbility->Half_100 = (phydata & BIT_7) ? (1) : (0); + pPhyAbility->Full_100 = (phydata & BIT_8) ? (1) : (0); + + pPhyAbility->FC = (phydata & BIT_10) ? (1) : (0); + pPhyAbility->AsyFC = (phydata & BIT_11) ? (1) : (0); + + // 1G + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA412, &phydata); + if (status != SUCCESS) + goto exit; + + pPhyAbility->Full_1000 = (phydata & BIT_9) ? (1) : (0); + + // 2.5G + status = MmdPhyRead(hDevice, MMD_AN, 32, &phydata); + if (status != SUCCESS) + goto exit; + + pPhyAbility->adv_2_5G = (phydata & BIT_7) ? (1) : (0); + + // 5G + status = MmdPhyRead(hDevice, MMD_AN, 32, &phydata); + if (status != SUCCESS) + goto exit; + + pPhyAbility->adv_5G = (phydata & BIT_8) ? (1) : (0); + + +exit: + return status; +} + +BOOLEAN +Rtl8251b_autoNegoAbility_set( + IN HANDLE hDevice, + IN PHY_LINK_ABILITY *pPhyAbility + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + status = MmdPhyRead(hDevice, MMD_AN, 16, &phydata); + if (status != SUCCESS) + goto exit; + + phydata &= (~(BIT_5 | BIT_6 | BIT_7 | BIT_8 | BIT_10 | BIT_11)); + + // 10M + phydata |= (pPhyAbility->Half_10 ? (BIT_5) : (0)); + phydata |= (pPhyAbility->Full_10 ? (BIT_6) : (0)); + + // 100M + phydata |= (pPhyAbility->Half_100 ? (BIT_7) : (0)); + phydata |= (pPhyAbility->Full_100 ? (BIT_8) : (0)); + + phydata |= (pPhyAbility->FC ? (BIT_10) : (0)); + phydata |= (pPhyAbility->AsyFC ? (BIT_11) : (0)); + + status = MmdPhyWrite(hDevice, MMD_AN, 16, phydata); + if (status != SUCCESS) + goto exit; + + // 1G + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA412, &phydata); + if (status != SUCCESS) + goto exit; + + phydata &= (~BIT_9); + + phydata |= (pPhyAbility->Full_1000 ? (BIT_9) : (0)); + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA412, phydata); + if (status != SUCCESS) + goto exit; + + // 2.5G + status = MmdPhyRead(hDevice, MMD_AN, 32, &phydata); + if (status != SUCCESS) + goto exit; + + phydata &= (~BIT_7); + + phydata |= (pPhyAbility->adv_2_5G ? (BIT_7) : (0)); + status = MmdPhyWrite(hDevice, MMD_AN, 32, phydata); + if (status != SUCCESS) + goto exit; + + // 5G + status = MmdPhyRead(hDevice, MMD_AN, 32, &phydata); + if (status != SUCCESS) + goto exit; + + phydata &= (~BIT_8); + + phydata |= (pPhyAbility->adv_5G ? (BIT_8) : (0)); + status = MmdPhyWrite(hDevice, MMD_AN, 32, phydata); + if (status != SUCCESS) + goto exit; + + if (MmdPhyRead(hDevice, MMD_AN, 0, &phydata) == SUCCESS) + { + if (phydata & BIT_12) /* AN_ENABLE */ + { + phydata |= BIT_9; /* RESTART_AN */ + MmdPhyWrite(hDevice, MMD_AN, 0, phydata); + } + } + SLEEP_1MS; +exit: + return status; +} + +BOOLEAN +Rtl8251b_duplex_get( + IN HANDLE hDevice, + OUT BOOL *pEnable + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA434, &phydata); + if (status != SUCCESS) + goto exit; + + *pEnable = (phydata & BIT_3) ? (TRUE) : (FALSE); + +exit: + return status; +} + + +BOOLEAN +Rtl8251b_duplex_set( // christy add 0430 + IN HANDLE hDevice, + IN BOOL Enable + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA400, &phydata); + if (status != SUCCESS) + goto exit; + + if (Enable) + phydata |= BIT_8; + else + phydata &= (~BIT_8); + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA400, phydata); + if (status != SUCCESS) + goto exit; + +exit: + return status; +} + + + +BOOLEAN +Rtl8251b_is_link( + IN HANDLE hDevice, + OUT BOOL *plinkOK + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + UINT8 i = 0; + + // must read twice + for(i=0;i<2;i++) + { + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA402, &phydata); + if (status != SUCCESS) + goto exit; + } + + *plinkOK = (phydata & BIT_2) ? (TRUE) : (FALSE); + +exit: + return status; +} + +BOOLEAN +Rtl8251b_speed_get( + IN HANDLE hDevice, + OUT UINT16 *pSpeed + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + UINT8 speed_grp = 0; + UINT8 speed = NO_LINK; + +// int i = 0; + + BOOL linkOK = FALSE; + + status = Rtl8251b_is_link(hDevice, &linkOK); + if (status != SUCCESS) + goto exit; + + if (linkOK) + { + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA434, &phydata); + if (status != SUCCESS) + goto exit; + + speed_grp = (phydata & (BIT_9 | BIT_10)) >> 9; + speed = (phydata & (BIT_4 | BIT_5)) >> 4; + + switch(speed_grp) + { + case 0: + { + switch(speed) + { + case 0: + *pSpeed = LINK_SPEED_10M; + break; + case 1: + *pSpeed = LINK_SPEED_100M; + break; + case 2: + *pSpeed = LINK_SPEED_1G; + break; + case 3: + *pSpeed = LINK_SPEED_500M; + break; + + default: + status = FAILURE; + break; + } + break; + } + + case 1: + { + switch(speed) + { + case 1: + *pSpeed = LINK_SPEED_2P5G; + break; + case 2: + *pSpeed = LINK_SPEED_5G; //5G + break; + case 3: + *pSpeed = LINK_SPEED_1G; // 2.5G lite + break; + default: + status = FAILURE; + break; + } + break; + } + + default: + status = FAILURE; + break; + } + } + else + { + *pSpeed = NO_LINK; + } + +exit: + return status; +} + +BOOLEAN +Rtl8251b_enable_set( + IN HANDLE hDevice, + IN BOOL Enable + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + status = MmdPhyRead(hDevice, MMD_PMAPMD, 0, &phydata); + if (status != SUCCESS) + goto exit; + + if (Enable) + phydata &= (~BIT_11); // set as 0 + else + phydata |= BIT_11; // set as 1 + + + status = MmdPhyWrite(hDevice, MMD_PMAPMD, 0, phydata); + if (status != SUCCESS) + goto exit; + +exit: + return status; +} + +BOOLEAN +Rtl8251b_force_speed_set( + IN HANDLE hDevice, + IN UINT16 Speed + ) +{ + BOOL status = FAILURE; + UINT16 phydata0 = 0, phydata1 = 0; + BOOL support = 0; + + status = MmdPhyRead(hDevice, MMD_PMAPMD, 0, &phydata0); + if (status != SUCCESS) + goto exit; + + phydata0 &= (~(BIT_6 | BIT_13)); + + switch(Speed) + { + case 10: + support = TRUE; + phydata0 &= (~BIT_6); + phydata0 &= (~BIT_13); + break; + + case 100: + support = TRUE; + phydata0 &= (~BIT_6); + phydata0 |= BIT_13; + break; + + case 1000: + support = TRUE; + phydata0 |= BIT_6; + phydata0 &= (~BIT_13); + break; + + case 2500: + support = TRUE; + phydata0 &= (~(BIT_2 | BIT_3 | BIT_4 | BIT_5)); + phydata0 |= BIT_6; + phydata0 |= BIT_13; + phydata0 &= (~BIT_2); // 0 + phydata0 |= BIT_3; // 1 + phydata0 |= BIT_4; // 1 + phydata0 &= (~BIT_5); // 0 + break; + + case 5000: + support = TRUE; + phydata0 &= (~(BIT_2 | BIT_3 | BIT_4 | BIT_5)); + phydata0 |= BIT_6; + phydata0 |= BIT_13; + phydata0 |= BIT_2; // 1 + phydata0 |= BIT_3; // 1 + phydata0 |= BIT_4; // 1 + phydata0 &= (~BIT_5); // 0 + break; + + default: + status = FAILURE; + support = FALSE; + break; + } + + if (support) + { + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA5B4, &phydata1); + if (status != SUCCESS) + goto exit; + + phydata1 |= (BIT_15); + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA5B4, phydata1); + if (status != SUCCESS) + goto exit; + + status = MmdPhyWrite(hDevice, MMD_PMAPMD, 0, phydata0); + if (status != SUCCESS) + goto exit; + + status = Rtl8251b_autoNegoEnable_set(hDevice, FALSE); + if (status != SUCCESS) + goto exit; + } + else + status = FAILURE; + +exit: + return status; +} + +BOOLEAN +Rtl8251b_greenEnable_get( + IN HANDLE hDevice, + OUT BOOL *pEnable + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA436, 0x8011); + if (status != SUCCESS) + goto exit; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA438, &phydata); + if (status != SUCCESS) + goto exit; + + *pEnable = (phydata & BIT_15) ? (TRUE) : (FALSE); + +exit: + return status; +} + +BOOLEAN +Rtl8251b_greenEnable_set( + IN HANDLE hDevice, + IN BOOL Enable + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA436, 0x8011); + if (status != SUCCESS) + goto exit; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA438, &phydata); + if (status != SUCCESS) + goto exit; + + if (Enable) + phydata |= (BIT_15); + else + phydata &= (~BIT_15); + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA438, phydata); + if (status != SUCCESS) + goto exit; + +exit: + return status; +} + +BOOLEAN +Rtl8251b_eeeEnable_get( + IN HANDLE hDevice, + OUT PHY_EEE_ENABLE *pEeeEnable + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + status = MmdPhyRead(hDevice, MMD_AN, 60, &phydata); + if (status != SUCCESS) + goto exit; + + pEeeEnable->EEE_100 = (phydata & BIT_1) ? (TRUE) : (FALSE); + pEeeEnable->EEE_1000 = (phydata & BIT_2) ? (TRUE) : (FALSE); + + status = MmdPhyRead(hDevice, MMD_AN, 62, &phydata); + if (status != SUCCESS) + goto exit; + + pEeeEnable->EEE_2_5G = (phydata & BIT_0) ? (TRUE) : (FALSE); + pEeeEnable->EEE_5G = (phydata & BIT_1) ? (TRUE) : (FALSE); + +exit: + return status; +} + +BOOLEAN +Rtl8251b_eeeEnable_set( + IN HANDLE hDevice, + IN PHY_EEE_ENABLE *pEeeEnable + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + BOOL AnEnable = 0; + + status = Rtl8251b_autoNegoEnable_get(hDevice, &AnEnable); + if (status != SUCCESS) + goto exit; + + // 100M/1G EEE + status = MmdPhyRead(hDevice, MMD_AN, 60, &phydata); + if (status != SUCCESS) + goto exit; + + if (pEeeEnable->EEE_100) + phydata |= BIT_1; + else + phydata &= (~BIT_1); + + + if (pEeeEnable->EEE_1000) + phydata |= BIT_2; + else + phydata &= (~BIT_2); + + status = MmdPhyWrite(hDevice, MMD_AN, 60, phydata); + if (status != SUCCESS) + goto exit; + + // 2.5G EEE + status = MmdPhyRead(hDevice, MMD_AN, 62, &phydata); + if (status != SUCCESS) + goto exit; + + if (pEeeEnable->EEE_2_5G) + phydata |= BIT_0; + else + phydata &= (~BIT_0); + + status = MmdPhyWrite(hDevice, MMD_AN, 62, phydata); + if (status != SUCCESS) + goto exit; + + // 5G EEE + status = MmdPhyRead(hDevice, MMD_AN, 62, &phydata); + if (status != SUCCESS) + goto exit; + + if (pEeeEnable->EEE_5G) + phydata |= BIT_1; + else + phydata &= (~BIT_1); + + status = MmdPhyWrite(hDevice, MMD_AN, 62, phydata); + if (status != SUCCESS) + goto exit; + + // RestartAutoNegotiation + if (AnEnable) + { + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA400, &phydata); + if (status != SUCCESS) + goto exit; + + phydata |= BIT_9; + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA400, phydata); + if (status != SUCCESS) + goto exit; + } + +exit: + return status; +} + +BOOLEAN +Rtl8251b_crossOverMode_get( + IN HANDLE hDevice, + OUT PHY_CROSSPVER_MODE *CrossOverMode + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA430, &phydata); + if (status != SUCCESS) + goto exit; + + if((phydata & BIT_9) >> 9) + { + switch((phydata & BIT_8) >> 8) + { + case 1: + *CrossOverMode = PHY_CROSSPVER_MODE_MDI; + break; + case 0: + *CrossOverMode = PHY_CROSSPVER_MODE_MDIX; + break; + default: + status = FAILURE; + break; + } + } + else + *CrossOverMode = PHY_CROSSPVER_MODE_AUTO; + +exit: + return status; +} + +BOOLEAN +Rtl8251b_crossOverMode_set( + IN HANDLE hDevice, + IN PHY_CROSSPVER_MODE CrossOverMode + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA430, &phydata); + if (status != SUCCESS) + goto exit; + + phydata &= (~(BIT_8 | BIT_9)); + + switch(CrossOverMode) + { + case PHY_CROSSPVER_MODE_MDI: + phydata |= (BIT_8 | BIT_9); + break; + case PHY_CROSSPVER_MODE_MDIX: + phydata |= BIT_9; + break; + case PHY_CROSSPVER_MODE_AUTO: + break; + default: + status = FAILURE; + goto exit; + } + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA430, phydata); + if (status != SUCCESS) + goto exit; + +exit: + return status; +} + +BOOLEAN +Rtl8251b_crossOverStatus_get( + IN HANDLE hDevice, + OUT PHY_CROSSPVER_STATUS *pCrossOverStatus + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA434, &phydata); + if (status != SUCCESS) + goto exit; + + *pCrossOverStatus = (phydata & BIT_1) ? (PHY_CROSSPVER_STATUS_MDI) : (PHY_CROSSPVER_STATUS_MDIX); + +exit: + return status; +} + +BOOLEAN +Rtl8251b_masterSlave_get( + IN HANDLE hDevice, + OUT PHY_MASTERSLAVE_MODE *MasterSlaveMode + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + status = MmdPhyRead(hDevice, MMD_AN, 33, &phydata); + if (status != SUCCESS) + goto exit; + + switch((phydata >> 14) & 0x3) + { + case 0: // 0:Slave, 1:Master + *MasterSlaveMode = PHY_SLAVE_MODE; + break; + case 1: + *MasterSlaveMode = PHY_MASTER_MODE; + break; + default: + status = FAILURE; + break; + } + +exit: + return status; +} + +BOOLEAN +Rtl8251b_masterSlave_set( + IN HANDLE hDevice, + IN PHY_MASTERSLAVE_MODE MasterSlaveMode + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + status = MmdPhyRead(hDevice, MMD_AN, 32, &phydata); + if (status != SUCCESS) + goto exit; + + phydata &= (~(BIT_14 | BIT_15)); + + switch(MasterSlaveMode) + { + case PHY_AUTO_MODE: + break; + case PHY_SLAVE_MODE: + phydata |= BIT_15; + break; + case PHY_MASTER_MODE: + phydata |= (BIT_14 | BIT_15); + break; + default: + status = FAILURE; + goto exit; + } + + status = MmdPhyWrite(hDevice, MMD_AN, 32, phydata); + if (status != SUCCESS) + goto exit; + +exit: + return status; +} + +BOOLEAN +Rtl8251b_loopback_get( + IN HANDLE hDevice, + OUT BOOL *pEnable + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + status = MmdPhyRead(hDevice, MMD_PCS, 0x0, &phydata); + if (status != SUCCESS) + goto exit; + + *pEnable = (phydata & BIT_14) ? (TRUE) : (FALSE); + +exit: + return status; +} + +BOOLEAN +Rtl8251b_loopback_set( + IN HANDLE hDevice, + IN BOOL Enable + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + status = MmdPhyRead(hDevice, MMD_PCS, 0x0, &phydata); + if (status != SUCCESS) + goto exit; + + if (Enable) + phydata |= BIT_14; + else + phydata &= (~BIT_14); + + status = MmdPhyWrite(hDevice, MMD_PCS, 0x0, phydata); + if (status != SUCCESS) + goto exit; + +exit: + return status; +} + +BOOLEAN +Rtl8251b_PMA_loopback_get( + IN HANDLE hDevice, + OUT BOOL *pEnable + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + status = MmdPhyRead(hDevice, MMD_PMAPMD, 0x0, &phydata); + if (status != SUCCESS) + goto exit; + + *pEnable = (phydata & BIT_0) ? (TRUE) : (FALSE); + +exit: + return status; +} + +BOOLEAN +Rtl8251b_PMA_loopback_set( + IN HANDLE hDevice, + IN BOOL Enable + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + status = MmdPhyRead(hDevice, MMD_PMAPMD, 0x0, &phydata); + if (status != SUCCESS) + goto exit; + + if (Enable) + phydata |= BIT_0; + else + phydata &= (~BIT_0); + + status = MmdPhyWrite(hDevice, MMD_PMAPMD, 0x0, phydata); + if (status != SUCCESS) + goto exit; + +exit: + return status; +} + +BOOLEAN +Rtl8251b_downSpeedEnable_get( + IN HANDLE hDevice, + OUT BOOL *pEnable + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA442, &phydata); + if (status != SUCCESS) + goto exit; + + *pEnable = (phydata & BIT_3) ? (TRUE) : (FALSE); + +exit: + return status; +} + +BOOLEAN +Rtl8251b_downSpeedEnable_set( + IN HANDLE hDevice, + IN BOOL Enable + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA442, &phydata); + if (status != SUCCESS) + goto exit; + + phydata &= (~BIT_5); + + if (Enable) + phydata |= BIT_3; + else + phydata &= (~BIT_3); + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA442, phydata); + if (status != SUCCESS) + goto exit; + +exit: + return status; +} + +BOOLEAN +Rtl8251b_gigaLiteEnable_get( + IN HANDLE hDevice, + OUT BOOL *pEnable + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA428, &phydata); + if (status != SUCCESS) + goto exit; + + *pEnable = (phydata & BIT_9) ? (TRUE) : (FALSE); + +exit: + return status; +} + +BOOLEAN +Rtl8251b_gigaLiteEnable_set( + IN HANDLE hDevice, + IN BOOL Enable + ) +{ + BOOL status = FAILURE; + UINT16 phydata0 = 0, phydata1 = 0; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA442, &phydata0); + if (status != SUCCESS) + goto exit; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA428, &phydata1); + if (!status) + goto exit; + + if (Enable) + { + phydata0 |= (BIT_2 | BIT_9); + phydata1 |= BIT_9; + } + else + { + phydata0 &= (~(BIT_2 | BIT_9)); + phydata1 &= (~BIT_9); + } + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA442, phydata0); + if (status != SUCCESS) + goto exit; + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA428, phydata1); + if (status != SUCCESS) + goto exit; + +exit: + return status; +} + + + + +BOOLEAN +Rtl8251b_mdiSwapEnable_get( + IN HANDLE hDevice, + OUT BOOL *pEnable + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + status = MmdPhyRead(hDevice, MMD_VEND1, 0x6A21, &phydata); + if (status != SUCCESS) + goto exit; + + *pEnable = (phydata & BIT_5) ? (TRUE) : (FALSE); + +exit: + return status; +} + +BOOLEAN +Rtl8251b_mdiSwapEnable_set( + IN HANDLE hDevice, + IN BOOL Enable + ) +{ + BOOL status = FAILURE; + BOOL Flag_mdi_swap = 0; + UINT16 phydata = 0; + UINT16 phydata0 = 0; + UINT16 phydata1 = 0; + UINT16 phydata2 = 0; + UINT16 phydata3 = 0; + UINT16 _6A21_5 = 0; + UINT16 adccal_offset_p0 = 0; + UINT16 adccal_offset_p1 = 0; + UINT16 adccal_offset_p2 = 0; + UINT16 adccal_offset_p3 = 0; + UINT16 rg_lpf_cap_xg_p0 = 0; + UINT16 rg_lpf_cap_xg_p1 = 0; + UINT16 rg_lpf_cap_xg_p2 = 0; + UINT16 rg_lpf_cap_xg_p3 = 0; + UINT16 rg_lpf_cap_p0 = 0; + UINT16 rg_lpf_cap_p1 = 0; + UINT16 rg_lpf_cap_p2 = 0; + UINT16 rg_lpf_cap_p3 = 0; + + + status = MmdPhyRead(hDevice, MMD_VEND1, 0x6A21, &_6A21_5); + if (status != SUCCESS) + goto exit; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xD068, &phydata); + if (status != SUCCESS) + goto exit; + + Flag_mdi_swap = (phydata & 0x0002)? 1:0; + if (!Flag_mdi_swap){ + printf("MDI already swap \n"); + goto exit; + } + + phydata0 = phydata & 0xFFE0; + phydata0 |= 0x0001; + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xD068, phydata0); + if (status != SUCCESS) + goto exit; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xD06A, &adccal_offset_p0); + if (status != SUCCESS) + goto exit; + + phydata1 = phydata & 0xFFE0; + phydata1 |= 0x0009; + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xD068, phydata1); + if (status != SUCCESS) + goto exit; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xD06A, &adccal_offset_p1); + if (status != SUCCESS) + goto exit; + + phydata2 = phydata & 0xFFE0; + phydata2 |= 0x0011; + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xD068, phydata2); + if (status != SUCCESS) + goto exit; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xD06A, &adccal_offset_p2); + if (status != SUCCESS) + goto exit; + + phydata3 = phydata & 0xFFE0; + phydata3 |= 0x0019; + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xD068, phydata3); + if (status != SUCCESS) + goto exit; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xD06A, &adccal_offset_p3); + if (status != SUCCESS) + goto exit; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xBD5A, &phydata); + if (status != SUCCESS) + goto exit; + + rg_lpf_cap_xg_p0 = phydata & 0x001F; + rg_lpf_cap_xg_p1 = phydata & 0x1F00; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xBD5C, &phydata); + if (status != SUCCESS) + goto exit; + + rg_lpf_cap_xg_p2 = phydata & 0x001F; + rg_lpf_cap_xg_p3 = phydata & 0x1F00; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xBC18, &phydata); + if (status != SUCCESS) + goto exit; + + rg_lpf_cap_p0 = phydata & 0x001F; + rg_lpf_cap_p1 = phydata & 0x1F00; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xBC1A, &phydata); + if (status != SUCCESS) + goto exit; + + rg_lpf_cap_p2 = phydata & 0x001F; + rg_lpf_cap_p3 = phydata & 0x1F00; + + if (Enable) + { + _6A21_5 |= (BIT_5); + status = MmdPhyWrite(hDevice, MMD_VEND1, 0x6A21, _6A21_5); + if (status != SUCCESS) + goto exit; + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xD068, phydata0); + if (status != SUCCESS) + goto exit; + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xD06A, adccal_offset_p3); + if (status != SUCCESS) + goto exit; + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xD068, phydata1); + if (status != SUCCESS) + goto exit; + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xD06A, adccal_offset_p2); + if (status != SUCCESS) + goto exit; + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xD068, phydata2); + if (status != SUCCESS) + goto exit; + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xD06A, adccal_offset_p1); + if (status != SUCCESS) + goto exit; + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xD068, phydata3); + if (status != SUCCESS) + goto exit; + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xD06A, adccal_offset_p0); + if (status != SUCCESS) + goto exit; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xBD5A, &phydata); + if (status != SUCCESS) + goto exit; + + phydata &= 0xE0E0; + phydata = ( rg_lpf_cap_xg_p3 >>8 ) | (rg_lpf_cap_xg_p2 << 8) | phydata; + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xBD5A, phydata); + if (status != SUCCESS) + goto exit; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xBD5C, &phydata); + if (status != SUCCESS) + goto exit; + + phydata &= 0xE0E0; + phydata = (rg_lpf_cap_xg_p1 >>8) | (rg_lpf_cap_xg_p0 <<8)| phydata; + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xBD5C, phydata); + if (status != SUCCESS) + goto exit; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xBC18, &phydata); + if (status != SUCCESS) + goto exit; + + phydata &= 0xE0E0; + phydata = (rg_lpf_cap_p3 >>8) | (rg_lpf_cap_p2 <<8) | phydata; + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xBC18, phydata); + if (status != SUCCESS) + goto exit; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xBC1A, &phydata); + if (status != SUCCESS) + goto exit; + + phydata &= 0xE0E0; + phydata = (rg_lpf_cap_p1 >>8) | (rg_lpf_cap_p0 <<8) | phydata; + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xBC1A, phydata); + if (status != SUCCESS) + goto exit; + + } +/* else + { + _6A21_5 &= (~(BIT_5)); + status = MmdPhyWrite(hDevice, MMD_VEND1, 0x6A21, _6A21_5); + if (status != SUCCESS) + goto exit; + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xD068, phydata0); + if (status != SUCCESS) + goto exit; + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xD06A, adccal_offset_p0); + if (status != SUCCESS) + goto exit; + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xD068, phydata1); + if (status != SUCCESS) + goto exit; + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xD06A, adccal_offset_p1); + if (status != SUCCESS) + goto exit; + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xD068, phydata2); + if (status != SUCCESS) + goto exit; + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xD06A, adccal_offset_p2); + if (status != SUCCESS) + goto exit; + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xD068, phydata3); + if (status != SUCCESS) + goto exit; + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xD06A, adccal_offset_p3); + if (status != SUCCESS) + goto exit; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xBD5A, &phydata); + if (status != SUCCESS) + goto exit; + phydata &= 0xE0E0; + phydata = rg_lpf_cap_xg_p1 | rg_lpf_cap_xg_p0 | phydata; + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xBD5A, phydata); + if (status != SUCCESS) + goto exit; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xBD5C, &phydata); + if (status != SUCCESS) + goto exit; + phydata &= 0xE0E0; + phydata = rg_lpf_cap_xg_p2 | rg_lpf_cap_xg_p3 | phydata; + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xBD5C, phydata); + if (status != SUCCESS) + goto exit; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xBC18, &phydata); + if (status != SUCCESS) + goto exit; + phydata &= 0xE0E0; + phydata = rg_lpf_cap_p1 | rg_lpf_cap_p0 | phydata; + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xBC18, phydata); + if (status != SUCCESS) + goto exit; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xBC1A, &phydata); + if (status != SUCCESS) + goto exit; + phydata &= 0xE0E0; + phydata = rg_lpf_cap_p3 | rg_lpf_cap_p2 | phydata; + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xBC1A, phydata); + if (status != SUCCESS) + goto exit; + + }*/ + +exit: + return status; +} + + + + +BOOLEAN +Rtl8251b_rtct_start( + IN HANDLE hDevice + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + BOOL linkOK; + UINT16 Speed; + + status = Rtl8251b_is_link(hDevice, &linkOK); + if (status != SUCCESS) + goto exit; + + if (linkOK) + { + status = Rtl8251b_speed_get(hDevice, &Speed); + if (status != SUCCESS) + goto exit; + + //RTCT is not supported when port link at 10M. + if (Speed == 10) + { + printf("RTCT is not supported when port link at 10M.\n"); + status = FAILURE; + goto exit; + } + } + else + { + // MMD 31.0xA422[15] = 0 // clear rtct_done + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA422, &phydata); + if (status != SUCCESS) + goto exit; + + phydata &= (~BIT_15); + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA442, phydata); + if (status != SUCCESS) + goto exit; + + // wait 1ms for chip reset the states + SLEEP_1MS; + + // MMD 31.0xA422[4] = 1 // RTCT_CH_A + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA422, &phydata); + if (status != SUCCESS) + goto exit; + + phydata |= (BIT_4); + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA442, phydata); + if (status != SUCCESS) + goto exit; + + // MMD 31.0xA422[5] = 1 // RTCT_CH_B + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA422, &phydata); + if (status != SUCCESS) + goto exit; + + phydata |= (BIT_5); + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA442, phydata); + if (status != SUCCESS) + goto exit; + + // MMD 31.0xA422[6] = 1 // RTCT_CH_C + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA422, &phydata); + if (status != SUCCESS) + goto exit; + + phydata |= (BIT_6); + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA442, phydata); + if (status != SUCCESS) + goto exit; + + // MMD 31.0xA422[7] = 1 // RTCT_CH_D + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA422, &phydata); + if (status != SUCCESS) + goto exit; + + phydata |= (BIT_7); + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA442, phydata); + if (status != SUCCESS) + goto exit; + + // MMD 31.0xA422[0] = 1 // RTCT_ENABLE + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA422, &phydata); + if (status != SUCCESS) + goto exit; + + phydata |= (BIT_0); + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA442, phydata); + if (status != SUCCESS) + goto exit; + } + +exit: + return status; +} + +BOOLEAN +Rtl8251b_rtctResult_convert( + IN UINT16 phydata, + OUT PHY_RTCT_STATUS *pRtctStatus + ) +{ + BOOL status = SUCCESS; + + switch(phydata) + { + case 0x60: // Normal + break; + case 0x48: + pRtctStatus->Open = TRUE; + break; + case 0x50: + pRtctStatus->Short = TRUE; + break; + case 0x42: + pRtctStatus->Mismatch = MIS_MATCH_OPEN; + break; + case 0x44: + pRtctStatus->Mismatch = MIS_MATCH_SHORT; + break; + + default: + status = FAILURE; + break; + } + + return status; +} + +BOOLEAN +Rtl8251b_rtctResult_get( + IN HANDLE hDevice, + OUT PHY_RTCT_RESULT *pRtctResult + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + BOOL linkOK = FALSE; + + UINT16 Speed = NO_LINK; + + BOOL rtct_done; + + status = Rtl8251b_is_link(hDevice, &linkOK); + if (status != SUCCESS) + goto exit; + + if (linkOK) + { + status = Rtl8251b_speed_get(hDevice, &Speed); + if (status != SUCCESS) + goto exit; + + switch(Speed) + { + case LINK_SPEED_100M: + // rxLen = MMD 31.0xA880[7:0] * 100 // unit is meter + // txLen = MMD 31.0xA880[7:0] * 100 + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA880, &phydata); + if (status != SUCCESS) + goto exit; + + pRtctResult->rxLen = (phydata & 0xff) * 100; + pRtctResult->txLen = (phydata & 0xff) * 100; + break; + + case LINK_SPEED_1G: + // channelALen = MMD 31.0xA880[7:0] * 100 // unit is meter + // channelBLen = MMD 31.0xA880[7:0] * 100 + // channelCLen = MMD 31.0xA880[7:0] * 100 + // channelDLen = MMD 31.0xA880[7:0] * 100 + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA880, &phydata); + if (status != SUCCESS) + goto exit; + + pRtctResult->channelALen = (phydata & 0xff) * 100; + pRtctResult->channelBLen = (phydata & 0xff) * 100; + pRtctResult->channelCLen = (phydata & 0xff) * 100; + pRtctResult->channelDLen = (phydata & 0xff) * 100; + break; + + case LINK_SPEED_2P5G: + //channelALen = MMD 31.0xAC58[11:4] * 100 // cablen for XG + status = MmdPhyRead(hDevice, MMD_VEND2, 0xAC58, &phydata); + if (status != SUCCESS) + goto exit; + + pRtctResult->channelALen = ((phydata & 0xff0) >> 4 ) * 100; + pRtctResult->channelBLen = ((phydata & 0xff0) >> 4 ) * 100; + pRtctResult->channelCLen = ((phydata & 0xff0) >> 4 ) * 100; + pRtctResult->channelDLen = ((phydata & 0xff0) >> 4 ) * 100; + break; + + case LINK_SPEED_5G: + //channelALen = MMD 31.0xAC58[11:4] * 100 // cablen for XG + status = MmdPhyRead(hDevice, MMD_VEND2, 0xAC58, &phydata); + if (status != SUCCESS) + goto exit; + + pRtctResult->channelALen = ((phydata & 0xff0) >> 4 ) * 100; + pRtctResult->channelBLen = ((phydata & 0xff0) >> 4 ) * 100; + pRtctResult->channelCLen = ((phydata & 0xff0) >> 4 ) * 100; + pRtctResult->channelDLen = ((phydata & 0xff0) >> 4 ) * 100; + break; + + //RTCT is not supported when port link at 10M. + default: + status = FAILURE; + break; + } + } + else + { + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA422, &phydata); + if (status != SUCCESS) + goto exit; + + rtct_done = (phydata & BIT_15) ? (TRUE) : (FALSE); + if (!rtct_done) + { + status = FAILURE; + goto exit; + } + + // MMD 31.0A436[15:0] = 0x8029 + // phyData = read MMD 31.0A438[15:0] + // channelALen = phyData * 100 / 80 + // channelALen (unit: cm) + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA436, 0x8029); + if (status != SUCCESS) + goto exit; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0x0A438, &phydata); + if (status != SUCCESS) + goto exit; + + pRtctResult->channelALen = (phydata * 100) / 80; + + // MMD 31.0A436[15:0] = 0x802D + // phyData = read MMD 31.0A438[15:0] + // channelBLen = phyData * 100 / 80 + // channelBLen (unit: cm) + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA436, 0x802D); + if (status != SUCCESS) + goto exit; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0x0A438, &phydata); + if (status != SUCCESS) + goto exit; + + pRtctResult->channelBLen = (phydata * 100) / 80; + + // MMD 31.0A436[15:0] = 0x8031 + // phyData = read MMD 31.0A438[15:0] + // channelCLen = phyData * 100 / 80 + // channelCLen (unit: cm) + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA436, 0x8031); + if (status != SUCCESS) + goto exit; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0x0A438, &phydata); + if (status != SUCCESS) + goto exit; + + pRtctResult->channelCLen = (phydata * 100) / 80; + + // MMD 31.0A436[15:0] = 0x8035 + // phyData = read MMD 31.0A438[15:0] + // channelDLen = phyData * 100 / 80 + // channelDLen (unit: cm) + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA436, 0x8035); + if (status != SUCCESS) + goto exit; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0x0A438, &phydata); + if (status != SUCCESS) + goto exit; + + pRtctResult->channelDLen = (phydata * 100) / 80; + + // channelA status + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA436, 0x8027); + if (status != SUCCESS) + goto exit; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0x0A438, &phydata); + if (status != SUCCESS) + goto exit; + + status = Rtl8251b_rtctResult_convert(phydata, &pRtctResult->channelAStatus); + if (status != SUCCESS) + goto exit; + + // channelA status + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA436, 0x802B); + if (status != SUCCESS) + goto exit; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0x0A438, &phydata); + if (status != SUCCESS) + goto exit; + + status = Rtl8251b_rtctResult_convert(phydata, &pRtctResult->channelBStatus); + if (status != SUCCESS) + goto exit; + + // channelC status + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA436, 0x802F); + if (status != SUCCESS) + goto exit; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0x0A438, &phydata); + if (status != SUCCESS) + goto exit; + + status = Rtl8251b_rtctResult_convert(phydata, &pRtctResult->channelCStatus); + if (status != SUCCESS) + goto exit; + + // channelD status + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA436, 0x8033); + if (status != SUCCESS) + goto exit; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0x0A438, &phydata); + if (status != SUCCESS) + goto exit; + + status = Rtl8251b_rtctResult_convert(phydata, &pRtctResult->channelDStatus); + if (status != SUCCESS) + goto exit; + } + +exit: + return status; +} + +BOOLEAN +Rtl8251b_linkDownPowerSavingEnable_get( + IN HANDLE hDevice, + OUT BOOL *pEnable + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA430, &phydata); + if (status != SUCCESS) + goto exit; + + *pEnable = (phydata & BIT_2) ? (TRUE) : (FALSE); + +exit: + return status; +} + +BOOLEAN +Rtl8251b_linkDownPowerSavingEnable_set( + IN HANDLE hDevice, + IN BOOL Enable + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA430, &phydata); + if (status != SUCCESS) + goto exit; + + if (Enable) + phydata |= BIT_2; + else + phydata &= (~BIT_2); + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA430, phydata); + if (status != SUCCESS) + goto exit; + +exit: + return status; +} + +BOOLEAN +Rtl8251b_2p5gLiteEnable_get( + IN HANDLE hDevice, + OUT BOOL *pEnable + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA5EA, &phydata); + if (status != SUCCESS) + goto exit; + + *pEnable = (phydata & BIT_0) ? (TRUE) : (FALSE); + +exit: + return status; +} + +BOOLEAN +Rtl8251b_2p5gLiteEnable_set( + IN HANDLE hDevice, + IN BOOL Enable + ) +{ + BOOL status = FAILURE; + UINT16 phydata0 = 0, phydata1 = 0, phydata2 = 0; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA442, &phydata0); + if (status != SUCCESS) + goto exit; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA5FA, &phydata1); + if (status != SUCCESS) + goto exit; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA5EA, &phydata2); + if (status != SUCCESS) + goto exit; + + phydata0 &= (~BIT_2); + phydata1 &= (~BIT_1); + phydata2 &= (~BIT_0); + + if (Enable) + { + phydata0 |= BIT_2; + phydata1 |= BIT_1; + phydata2 |= BIT_0; + } + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA442, phydata0); + if (status != SUCCESS) + goto exit; + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA5FA, phydata1); + if (status != SUCCESS) + goto exit; + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA5EA, phydata2); + if (status != SUCCESS) + goto exit; + +exit: + return status; +} + +BOOLEAN +Rtl8251b_ThermalSensorEnable_get( + IN HANDLE hDevice, + OUT BOOL *pEnable + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA436, 0x81A2); + if (status != SUCCESS) + goto exit; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA438, &phydata); + if (status != SUCCESS) + goto exit; + + *pEnable = (phydata & BIT_8) ? (TRUE) : (FALSE); + +exit: + return status; +} + +BOOLEAN +Rtl8251b_ThermalSensorEnable_set( + IN HANDLE hDevice, + IN BOOL Enable + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA436, 0x81A2); + if (status != SUCCESS) + goto exit; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA438, &phydata); + if (status != SUCCESS) + goto exit; + + if (Enable) + phydata |= BIT_8; + else + phydata &= (~BIT_8); + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA438, phydata); + if (status != SUCCESS) + goto exit; + +exit: + return status; +} + +BOOLEAN +Rtl8251b_ieeeTestMode_set( + IN HANDLE hDevice, + IN UINT16 Speed, + IN PHY_IEEE_TEST_MODE *pIEEEtestmode + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0, phydata_w = 0, phydata2 = 0; + + switch(Speed) + { + case LINK_SPEED_1G: + { + // + status = MmdPhyRead(hDevice, MMD_VEND2, 0xBD2C, &phydata); + if (status != SUCCESS) + goto exit; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xBD32, &phydata2); + if (status != SUCCESS) + goto exit; + + if(pIEEEtestmode -> channel == TESTMODE_CHANNEL_NONE){ + phydata &= (~(BIT_10)); + } + else{ + phydata |= BIT_10; + + if(pIEEEtestmode -> channel == TESTMODE_CHANNEL_A) + phydata_w = 1 << 8; + else if(pIEEEtestmode -> channel == TESTMODE_CHANNEL_B) + phydata_w = 2 << 8; + else if(pIEEEtestmode -> channel == TESTMODE_CHANNEL_C) + phydata_w = 4 << 8; + else if(pIEEEtestmode -> channel == TESTMODE_CHANNEL_D) + phydata_w = 8 << 8; + + phydata2 &= (~(BIT_11 | BIT_10 | BIT_9 | BIT_8)); + phydata2 |= phydata_w; + } + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xBD32, phydata2); + if (status != SUCCESS) + goto exit; + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xBD2C, phydata); + if (status != SUCCESS) + goto exit; + + + if (pIEEEtestmode->TM1) + { + //printf("Giga TestMode 1 \n"); + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA412, 0x2000); + if (status != SUCCESS) + goto exit; + } + + if (pIEEEtestmode->TM2) + { + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA412, 0x4000); + if (status != SUCCESS) + goto exit; + } + + if (pIEEEtestmode->TM4) + { + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA412, 0x8000); + if (status != SUCCESS) + goto exit; + } + + if (pIEEEtestmode->TMFINISH) + { + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA412, 0x0000); + if (status != SUCCESS) + goto exit; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xBD2C, &phydata); + if (status != SUCCESS) + goto exit; + + phydata &= (~(BIT_10)); + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xBD2C, phydata); + if (status != SUCCESS) + goto exit; + } + + break; + } + + case LINK_SPEED_2P5G: + { + // + status = MmdPhyRead(hDevice, MMD_VEND2, 0xBD2C, &phydata); + if (status != SUCCESS) + goto exit; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xBD32, &phydata2); + if (status != SUCCESS) + goto exit; + + if(pIEEEtestmode -> channel == TESTMODE_CHANNEL_NONE){ + phydata &= (~(BIT_8)); + } + else{ + phydata |= BIT_8; + + if(pIEEEtestmode -> channel == TESTMODE_CHANNEL_A) + phydata_w = 1; + else if(pIEEEtestmode -> channel == TESTMODE_CHANNEL_B) + phydata_w = 2; + else if(pIEEEtestmode -> channel == TESTMODE_CHANNEL_C) + phydata_w = 4; + else if(pIEEEtestmode -> channel == TESTMODE_CHANNEL_D) + phydata_w = 8; + + phydata2 &= (~(BIT_3 | BIT_2 | BIT_1 | BIT_0)); + phydata2 |= phydata_w; + } + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xBD32, phydata2); + if (status != SUCCESS) + goto exit; + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xBD2C, phydata); + if (status != SUCCESS) + goto exit; + + + // 2.5G Test Mode + // MMD 1.0.15:0 = 0x2058 + status = MmdPhyWrite(hDevice, MMD_PMAPMD, 0, 0x2058); + if (status != SUCCESS) + goto exit; + + if (pIEEEtestmode->TM1) + { + status = MmdPhyWrite(hDevice, MMD_PMAPMD, 132, 0x2400); + if (status != SUCCESS) + goto exit; + } + + if (pIEEEtestmode->TM2) + { + status = MmdPhyWrite(hDevice, MMD_PMAPMD, 132, 0x4400); + if (status != SUCCESS) + goto exit; + } + + if (pIEEEtestmode->TM3) + { + status = MmdPhyWrite(hDevice, MMD_PMAPMD, 132, 0x6400); + if (status != SUCCESS) + goto exit; + } + + if (pIEEEtestmode->TM4) + { + if (pIEEEtestmode->TONE1) + { + status = MmdPhyWrite(hDevice, MMD_PMAPMD, 132, 0x8400); + if (status != SUCCESS) + goto exit; + } + + if (pIEEEtestmode->TONE2) + { + status = MmdPhyWrite(hDevice, MMD_PMAPMD, 132, 0x8800); + if (status != SUCCESS) + goto exit; + } + + if (pIEEEtestmode->TONE3) + { + status = MmdPhyWrite(hDevice, MMD_PMAPMD, 132, 0x9000); + if (status != SUCCESS) + goto exit; + } + + if (pIEEEtestmode->TONE4) + { + status = MmdPhyWrite(hDevice, MMD_PMAPMD, 132, 0x9400); + if (status != SUCCESS) + goto exit; + } + + if (pIEEEtestmode->TONE5) + { + status = MmdPhyWrite(hDevice, MMD_PMAPMD, 132, 0x9800); + if (status != SUCCESS) + goto exit; + } + } + + if (pIEEEtestmode->TM5) + { + status = MmdPhyWrite(hDevice, MMD_PMAPMD, 132, 0xA400); + if (status != SUCCESS) + goto exit; + } + + if (pIEEEtestmode->TM6) + { + status = MmdPhyWrite(hDevice, MMD_PMAPMD, 132, 0xC400); + if (status != SUCCESS) + goto exit; + } + + if (pIEEEtestmode->TMFINISH) + { + status = MmdPhyRead(hDevice, MMD_VEND2, 0xBD2C, &phydata); + if (status != SUCCESS) + goto exit; + + phydata &= (~(BIT_8)); + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xBD2C, phydata); + if (status != SUCCESS) + goto exit; + + //re-nway and set phy_rst) + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA400, 0x9200); + if (status != SUCCESS) + goto exit; + } + + break; + } + + case LINK_SPEED_5G: + { + // + status = MmdPhyRead(hDevice, MMD_VEND2, 0xBD2C, &phydata); + if (status != SUCCESS) + goto exit; + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xBD32, &phydata2); + if (status != SUCCESS) + goto exit; + + if(pIEEEtestmode -> channel == TESTMODE_CHANNEL_NONE){ + phydata &= (~(BIT_8)); + } + else{ + phydata |= BIT_8; + + if(pIEEEtestmode -> channel == TESTMODE_CHANNEL_A) + phydata_w = 1; + else if(pIEEEtestmode -> channel == TESTMODE_CHANNEL_B) + phydata_w = 2; + else if(pIEEEtestmode -> channel == TESTMODE_CHANNEL_C) + phydata_w = 4; + else if(pIEEEtestmode -> channel == TESTMODE_CHANNEL_D) + phydata_w = 8; + + phydata2 &= (~(BIT_3 | BIT_2 | BIT_1 | BIT_0)); + phydata2 |= phydata_w; + } + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xBD32, phydata2); + if (status != SUCCESS) + goto exit; + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xBD2C, phydata); + if (status != SUCCESS) + goto exit; + + + // 5G Test Mode + // MMD 1.0.15:0 = 0x205C + status = MmdPhyWrite(hDevice, MMD_PMAPMD, 0, 0x205C); + if (status != SUCCESS) + goto exit; + + if (pIEEEtestmode->TM1) + { + status = MmdPhyWrite(hDevice, MMD_PMAPMD, 132, 0x2400); + if (status != SUCCESS) + goto exit; + } + + if (pIEEEtestmode->TM2) + { + status = MmdPhyWrite(hDevice, MMD_PMAPMD, 132, 0x4400); + if (status != SUCCESS) + goto exit; + } + + if (pIEEEtestmode->TM3) + { + status = MmdPhyWrite(hDevice, MMD_PMAPMD, 132, 0x6400); + if (status != SUCCESS) + goto exit; + } + + if (pIEEEtestmode->TM4) + { + if (pIEEEtestmode->TONE1) + { + status = MmdPhyWrite(hDevice, MMD_PMAPMD, 132, 0x8400); + if (status != SUCCESS) + goto exit; + } + + if (pIEEEtestmode->TONE2) + { + status = MmdPhyWrite(hDevice, MMD_PMAPMD, 132, 0x8800); + if (status != SUCCESS) + goto exit; + } + + if (pIEEEtestmode->TONE3) + { + status = MmdPhyWrite(hDevice, MMD_PMAPMD, 132, 0x9000); + if (status != SUCCESS) + goto exit; + } + + if (pIEEEtestmode->TONE4) + { + status = MmdPhyWrite(hDevice, MMD_PMAPMD, 132, 0x9400); + if (status != SUCCESS) + goto exit; + } + + if (pIEEEtestmode->TONE5) + { + status = MmdPhyWrite(hDevice, MMD_PMAPMD, 132, 0x9800); + if (status != SUCCESS) + goto exit; + } + } + + if (pIEEEtestmode->TM5) + { + status = MmdPhyWrite(hDevice, MMD_PMAPMD, 132, 0xA400); + if (status != SUCCESS) + goto exit; + } + + if (pIEEEtestmode->TM6) + { + status = MmdPhyWrite(hDevice, MMD_PMAPMD, 132, 0xC400); + if (status != SUCCESS) + goto exit; + } + + if (pIEEEtestmode->TMFINISH) + { + status = MmdPhyRead(hDevice, MMD_VEND2, 0xBD2C, &phydata); + if (status != SUCCESS) + goto exit; + + phydata &= (~(BIT_8)); + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xBD2C, phydata); + if (status != SUCCESS) + goto exit; + + //re-nway and set phy_rst) + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA400, 0x9200); + if (status != SUCCESS) + goto exit; + } + + break; + } + + // only support 1G or 2.5G. + default: + break; + } + + +exit: + return status; +} + +BOOLEAN +Rtl8251b_serdes_rst( + IN HANDLE hDevice + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + status = MmdPhyRead(hDevice, MMD_VEND1, 0x7581, &phydata); + if (status != SUCCESS) + goto exit; + + phydata &= (~BIT_4); + + status = MmdPhyWrite(hDevice, MMD_VEND1, 0x7581, phydata); + if (status != SUCCESS) + goto exit; + + // wait 10 us + SLEEP_1MS; + + status = MmdPhyRead(hDevice, MMD_VEND1, 0x7581, &phydata); + if (status != SUCCESS) + goto exit; + + phydata |= BIT_4; + + status = MmdPhyWrite(hDevice, MMD_VEND1, 0x7581, phydata); + if (status != SUCCESS) + goto exit; + + // wait 10 us + SLEEP_1MS; +exit: + return status; +} + +BOOLEAN +Rtl8251b_serdes_link_get( + IN HANDLE hDevice, + OUT BOOL *perdesLink, + OUT PHY_SERDES_MODE *SerdesMode + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + UINT16 phydata1 = 0; + + // serdes link + status = MmdPhyRead(hDevice, MMD_VEND1, 0x758D, &phydata); + if (status != SUCCESS) + goto exit; + + *perdesLink = (phydata & BIT_1) ? (TRUE) : (FALSE); + + status = MmdPhyRead(hDevice, MMD_VEND1, 0x758B, &phydata); + if (status != SUCCESS) + goto exit; + + phydata &= BIT_0; + + if (phydata == 1){ + + //serdes mode + status = MmdPhyRead(hDevice, MMD_VEND1, 0x7580, &phydata); + if (status != SUCCESS) + goto exit; + + phydata1 = phydata; + phydata &= (BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0); + phydata1 &= (BIT_14 | BIT_13 | BIT_12 | BIT_11 | BIT_10); + + if(phydata == 2) + *SerdesMode = PHY_SERDES_MODE_SGMII; + else if(phydata == 21) + *SerdesMode = PHY_SERDES_MODE_5000BASEX; + else if(phydata == 13) + *SerdesMode = PHY_SERDES_MODE_USXGMII; + else if(phydata == 18) + *SerdesMode = PHY_SERDES_MODE_HiSGMII; + else if(phydata == 22) + *SerdesMode = PHY_SERDES_MODE_2500BASEX; + else if((phydata == 26)&&(phydata1 == 0)) + *SerdesMode = PHY_SERDES_MODE_SFI_10GBASER; + else if((phydata == 26)&&(phydata1 == 2)) + *SerdesMode = PHY_SERDES_MODE_5000BASER; + else if(phydata == 31) + *SerdesMode = PHY_SERDES_MODE_NO_SDS; + else + *SerdesMode = PHY_SERDES_MODE_OTHER; + } + else{ + *SerdesMode = PHY_SERDES_MODE_NO_SDS; + } + printf("Rtl8251b_serdes_link_get %d",*SerdesMode); + +exit: + return status; +} + +BOOLEAN +Rtl8251b_serdes_option_set( + IN HANDLE hDevice, + IN UINT8 functioninput + ) +{ + /* The RTL8251B supports SERDES setting options related to Link_down_option, Rate_adaptor_en, + and SERDES_speed at the different Ethernet speeds which is different from RTL8221. + According to the Ethernet speed, use a specific address to set SERDES Setting Options*/ + BOOL status = FAILURE; + UINT16 phydata = 0; + + if ((functioninput >= 0) && (functioninput <= 7)) + { + /* 5G-Lite: 30.0x6973.15:8 */ + status = MmdPhyRead(hDevice, MMD_VEND1, 0x6973, &phydata); + if (status != SUCCESS) + goto exit; + + phydata &= (~(BIT_11 | BIT_10 | BIT_9 | BIT_8 )); + phydata |= functioninput; + + status = MmdPhyWrite(hDevice, MMD_VEND1, 0x6973, phydata); + if (status != SUCCESS) + goto exit; + + /* 5G: 30.0x6973.7:0 */ + status = MmdPhyRead(hDevice, MMD_VEND1, 0x6973, &phydata); + if (status != SUCCESS) + goto exit; + + phydata &= (~(BIT_0 | BIT_1 | BIT_2 | BIT_3 )); + phydata |= functioninput; + + status = MmdPhyWrite(hDevice, MMD_VEND1, 0x6973, phydata); + if (status != SUCCESS) + goto exit; + + + /* 2.5G-Lite: 30.0x6974.15:8 */ + status = MmdPhyRead(hDevice, MMD_VEND1, 0x6974, &phydata); + if (status != SUCCESS) + goto exit; + + phydata &= (~(BIT_11 | BIT_10 | BIT_9 | BIT_8 )); + phydata |= functioninput; + + status = MmdPhyWrite(hDevice, MMD_VEND1, 0x6974, phydata); + if (status != SUCCESS) + goto exit; + + /* 2.5G: 30.0x6974.7:0 */ + status = MmdPhyRead(hDevice, MMD_VEND1, 0x6974, &phydata); + if (status != SUCCESS) + goto exit; + + phydata &= (~(BIT_0 | BIT_1 | BIT_2 | BIT_3 )); + phydata |= functioninput; + + status = MmdPhyWrite(hDevice, MMD_VEND1, 0x6974, phydata); + if (status != SUCCESS) + goto exit; + + + /* 1G-Lite: 30.0x6975.15:8 */ + status = MmdPhyRead(hDevice, MMD_VEND1, 0x6975, &phydata); + if (status != SUCCESS) + goto exit; + + phydata &= (~(BIT_11 | BIT_10 | BIT_9 | BIT_8 )); + phydata |= functioninput; + + status = MmdPhyWrite(hDevice, MMD_VEND1, 0x6975, phydata); + if (status != SUCCESS) + goto exit; + + /* 1G: 30.0x6975.7:0 */ + status = MmdPhyRead(hDevice, MMD_VEND1, 0x6975, &phydata); + if (status != SUCCESS) + goto exit; + + phydata &= (~(BIT_0 | BIT_1 | BIT_2 | BIT_3 )); + phydata |= functioninput; + + status = MmdPhyWrite(hDevice, MMD_VEND1, 0x6975, phydata); + if (status != SUCCESS) + goto exit; + + + /* 100M: 30.0x6976.7:0 */ + status = MmdPhyRead(hDevice, MMD_VEND1, 0x6976, &phydata); + if (status != SUCCESS) + goto exit; + + phydata &= (~(BIT_0 | BIT_1 | BIT_2 | BIT_3 )); + phydata |= functioninput; + + status = MmdPhyWrite(hDevice, MMD_VEND1, 0x6976, phydata); + if (status != SUCCESS) + goto exit; + + + /* 10M: 30.0x6977.7:0 */ + status = MmdPhyRead(hDevice, MMD_VEND1, 0x6977, &phydata); + if (status != SUCCESS) + goto exit; + + phydata &= (~(BIT_0 | BIT_1 | BIT_2 | BIT_3 )); + phydata |= functioninput; + + status = MmdPhyWrite(hDevice, MMD_VEND1, 0x6977, phydata); + if (status != SUCCESS) + goto exit; + } + +exit: + return status; +} + +BOOLEAN +Rtl8251b_serdes_polarity_swap( + IN HANDLE hDevice, + IN PHY_SERDES_POLARITY_SWAP *ppolarityswap + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + status = MmdPhyWrite(hDevice, MMD_VEND1, 0x7588, 0x0); + if (status != SUCCESS) + goto exit; + + if (ppolarityswap->TX_SWAP && ppolarityswap->RX_SWAP) + phydata = 0x1703; + else if (ppolarityswap->TX_SWAP) + phydata = 0x1503; + else if (ppolarityswap->RX_SWAP) + phydata = 0x1603; + else + phydata = 0x1403; + + status = MmdPhyWrite(hDevice, MMD_VEND1, 0x7589, phydata); + if (status != SUCCESS) + goto exit; + + status = MmdPhyWrite(hDevice, MMD_VEND1, 0x7587, 0x0003); + if (status != SUCCESS) + goto exit; + +exit: + return status; +} + +BOOLEAN +Rtl8251b_serdes_autoNego_set( + IN HANDLE hDevice, + IN BOOL Enable + ) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + status = MmdPhyWrite(hDevice, MMD_VEND1, 0x7588, 0x00f1); + if (status != SUCCESS) + goto exit; + + /* Enable/Disable USXGMII Auto-Negotiation */ + /* If you need to disable HiSGMII Auto-Negotiation, see 《SERDES Mode Setting Flow Application Note》 */ + if (Enable) + phydata = 0x854F; + else + phydata = 0x854E; + + status = MmdPhyWrite(hDevice, MMD_VEND1, 0x7589, phydata); + if (status != SUCCESS) + goto exit; + + status = MmdPhyWrite(hDevice, MMD_VEND1, 0x7587, 0x0003); + if (status != SUCCESS) + goto exit; + +exit: + return status; +} diff --git a/sources/uboot-be550/drivers/net/rtl8251b/nic_rtl8251b.h b/sources/uboot-be550/drivers/net/rtl8251b/nic_rtl8251b.h new file mode 100755 index 00000000..ddd90958 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8251b/nic_rtl8251b.h @@ -0,0 +1,297 @@ +/* + * Copyright (C) 2019 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : PHY 8251B Driver + * + * Feature : PHY 8251B Driver + * + */ +#ifndef __NIC_RTL8251B_H__ +#define __NIC_RTL8251B_H__ + +#include "rtl8251b_typedef.h" + +BOOLEAN +Rtl8251b_phy_reset( + IN HANDLE hDevice + ); + +BOOLEAN +Rtl8251b_autoNegoEnable_get( + IN HANDLE hDevice, + OUT BOOL *pEnable + ); + +BOOLEAN +Rtl8251b_autoNegoEnable_set( + IN HANDLE hDevice, + IN BOOL Enable + ); + +BOOLEAN +Rtl8251b_autoNegoRestart( + IN HANDLE hDevice + ); + +BOOLEAN +Rtl8251b_autoNegoAbility_get( + IN HANDLE hDevice, + OUT PHY_LINK_ABILITY *pPhyAbility + ); + +BOOLEAN +Rtl8251b_autoNegoAbility_set( + IN HANDLE hDevice, + IN PHY_LINK_ABILITY *pPhyAbility + ); + +BOOLEAN +Rtl8251b_duplex_get( + IN HANDLE hDevice, + OUT BOOL *pEnable + ); + +BOOLEAN +Rtl8251b_duplex_set( + IN HANDLE hDevice, + IN BOOL Enable + ); + +BOOLEAN +Rtl8251b_is_link( + IN HANDLE hDevice, + OUT BOOL *plinkOK + ); + +BOOLEAN +Rtl8251b_speed_get( + IN HANDLE hDevice, + OUT UINT16 *pSpeed + ); + +BOOLEAN +Rtl8251b_enable_set( + IN HANDLE hDevice, + IN BOOL Enable + ); + +BOOLEAN +Rtl8251b_force_speed_set( + IN HANDLE hDevice, + IN UINT16 Speed + ); + +BOOLEAN +Rtl8251b_greenEnable_get( + IN HANDLE hDevice, + OUT BOOL *pEnable + ); + +BOOLEAN +Rtl8251b_greenEnable_set( + IN HANDLE hDevice, + IN BOOL Enable + ); + +BOOLEAN +Rtl8251b_eeeEnable_get( + IN HANDLE hDevice, + OUT PHY_EEE_ENABLE *pEeeEnable + ); + +BOOLEAN +Rtl8251b_eeeEnable_set( + IN HANDLE hDevice, + IN PHY_EEE_ENABLE *pEeeEnable + ); + +BOOLEAN +Rtl8251b_crossOverMode_get( + IN HANDLE hDevice, + OUT PHY_CROSSPVER_MODE *CrossOverMode + ); + +BOOLEAN +Rtl8251b_crossOverMode_set( + IN HANDLE hDevice, + IN PHY_CROSSPVER_MODE CrossOverMode + ); + +BOOLEAN +Rtl8251b_crossOverStatus_get( + IN HANDLE hDevice, + OUT PHY_CROSSPVER_STATUS *pCrossOverStatus + ); + +BOOLEAN +Rtl8251b_masterSlave_get( + IN HANDLE hDevice, + OUT PHY_MASTERSLAVE_MODE *MasterSlaveMode + ); + +BOOLEAN +Rtl8251b_masterSlave_set( + IN HANDLE hDevice, + IN PHY_MASTERSLAVE_MODE MasterSlaveMode + ); + +BOOLEAN +Rtl8251b_loopback_get( + IN HANDLE hDevice, + OUT BOOL *pEnable + ); + +BOOLEAN +Rtl8251b_loopback_set( + IN HANDLE hDevice, + IN BOOL Enable + ); + +BOOLEAN +Rtl8251b_PMA_loopback_get( + IN HANDLE hDevice, + OUT BOOL *pEnable + ); + +BOOLEAN +Rtl8251b_PMA_loopback_set( + IN HANDLE hDevice, + IN BOOL Enable + ); + +BOOLEAN +Rtl8251b_downSpeedEnable_get( + IN HANDLE hDevice, + OUT BOOL *pEnable + ); + +BOOLEAN +Rtl8251b_downSpeedEnable_set( + IN HANDLE hDevice, + IN BOOL Enable + ); + +BOOLEAN +Rtl8251b_gigaLiteEnable_get( + IN HANDLE hDevice, + OUT BOOL *pEnable + ); + +BOOLEAN +Rtl8251b_gigaLiteEnable_set( + IN HANDLE hDevice, + IN BOOL Enable + ); + +BOOLEAN +Rtl8251b_mdiSwapEnable_get( + IN HANDLE hDevice, + OUT BOOL *pEnable + ); + +BOOLEAN +Rtl8251b_mdiSwapEnable_set( + IN HANDLE hDevice, + IN BOOL Enable + ); + +BOOLEAN +Rtl8251b_rtct_start( + IN HANDLE hDevice + ); + +BOOLEAN +Rtl8251b_rtctResult_convert( + IN UINT16 phydata, + OUT PHY_RTCT_STATUS *pRtctStatus + ); + +BOOLEAN +Rtl8251b_rtctResult_get( + IN HANDLE hDevice, + OUT PHY_RTCT_RESULT *pRtctResult + ); + +BOOLEAN +Rtl8251b_linkDownPowerSavingEnable_get( + IN HANDLE hDevice, + OUT BOOL *pEnable + ); + +BOOLEAN +Rtl8251b_linkDownPowerSavingEnable_set( + IN HANDLE hDevice, + IN BOOL Enable + ); + +BOOLEAN +Rtl8251b_2p5gLiteEnable_get( + IN HANDLE hDevice, + OUT BOOL *pEnable + ); + +BOOLEAN +Rtl8251b_2p5gLiteEnable_set( + IN HANDLE hDevice, + IN BOOL Enable + ); + +BOOLEAN +Rtl8251b_ThermalSensorEnable_get( + IN HANDLE hDevice, + OUT BOOL *pEnable + ); + +BOOLEAN +Rtl8251b_ThermalSensorEnable_set( + IN HANDLE hDevice, + IN BOOL Enable + ); + +BOOLEAN +Rtl8251b_ieeeTestMode_set( + IN HANDLE hDevice, + IN UINT16 Speed, + IN PHY_IEEE_TEST_MODE *pIEEEtestmode + ); + +BOOLEAN +Rtl8251b_serdes_rst( + IN HANDLE hDevice + ); + +BOOLEAN +Rtl8251b_serdes_link_get( + IN HANDLE hDevice, + OUT BOOL *perdesLink, + OUT PHY_SERDES_MODE *SerdesMode + ); + +BOOLEAN +Rtl8251b_serdes_option_set( + IN HANDLE hDevice, + IN UINT8 functioninput + ); + +BOOLEAN +Rtl8251b_serdes_polarity_swap( + IN HANDLE hDevice, + IN PHY_SERDES_POLARITY_SWAP *ppolarityswap + ); + +BOOLEAN +Rtl8251b_serdes_autoNego_set( + IN HANDLE hDevice, + IN BOOL Enable + ); + +#endif /* __NIC_RTL8251B_H__ */ + diff --git a/sources/uboot-be550/drivers/net/rtl8251b/nic_rtl8251b_init.c b/sources/uboot-be550/drivers/net/rtl8251b/nic_rtl8251b_init.c new file mode 100644 index 00000000..e9a3af1b --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8251b/nic_rtl8251b_init.c @@ -0,0 +1,3754 @@ + +/* SW_SDK: include files */ +// #include +// #include +// #include +// #include +// #include "hsl_phy.h" +// #include "ssdk_plat.h" +// #include "rtl8251b_typedef.h" +// #include "nic_rtl8251b.h" +// #include "nic_rtl8251b_init.h" + +#include "rtl8251b_typedef.h" +#include "nic_rtl8251b.h" +#include "nic_rtl8251b_init.h" + +static const MMD_REG Rtl8251b_n0_ramcode[] = +{ + { 31, 0xa436, 0XA016, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa436, 0XA012, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa436, 0XA014, }, + { 31, 0xa438, 0X1800, }, + { 31, 0xa438, 0X8010, }, + { 31, 0xa438, 0X1800, }, + { 31, 0xa438, 0X801e, }, + { 31, 0xa438, 0X1800, }, + { 31, 0xa438, 0X802c, }, + { 31, 0xa438, 0X1800, }, + { 31, 0xa438, 0X8030, }, + { 31, 0xa438, 0X1800, }, + { 31, 0xa438, 0X8030, }, + { 31, 0xa438, 0X1800, }, + { 31, 0xa438, 0X8030, }, + { 31, 0xa438, 0X1800, }, + { 31, 0xa438, 0X8030, }, + { 31, 0xa438, 0X1800, }, + { 31, 0xa438, 0X8030, }, + { 31, 0xa438, 0Xd504, }, + { 31, 0xa438, 0Xc994, }, + { 31, 0xa438, 0Xd500, }, + { 31, 0xa438, 0Xd707, }, + { 31, 0xa438, 0X60d0, }, + { 31, 0xa438, 0Xd701, }, + { 31, 0xa438, 0X252d, }, + { 31, 0xa438, 0X801c, }, + { 31, 0xa438, 0X1800, }, + { 31, 0xa438, 0X1064, }, + { 31, 0xa438, 0X1800, }, + { 31, 0xa438, 0X107a, }, + { 31, 0xa438, 0X1800, }, + { 31, 0xa438, 0X1052, }, + { 31, 0xa438, 0Xd504, }, + { 31, 0xa438, 0Xc9d0, }, + { 31, 0xa438, 0Xd500, }, + { 31, 0xa438, 0Xd707, }, + { 31, 0xa438, 0X60d0, }, + { 31, 0xa438, 0Xd701, }, + { 31, 0xa438, 0X252d, }, + { 31, 0xa438, 0X802a, }, + { 31, 0xa438, 0X1800, }, + { 31, 0xa438, 0X1171, }, + { 31, 0xa438, 0X1800, }, + { 31, 0xa438, 0X1187, }, + { 31, 0xa438, 0X1800, }, + { 31, 0xa438, 0X116a, }, + { 31, 0xa438, 0Xc0ff, }, + { 31, 0xa438, 0Xcaff, }, + { 31, 0xa438, 0X1800, }, + { 31, 0xa438, 0X00d6, }, + { 31, 0xa436, 0XA026, }, + { 31, 0xa438, 0Xffff, }, + { 31, 0xa436, 0XA024, }, + { 31, 0xa438, 0Xffff, }, + { 31, 0xa436, 0XA022, }, + { 31, 0xa438, 0Xffff, }, + { 31, 0xa436, 0XA020, }, + { 31, 0xa438, 0Xffff, }, + { 31, 0xa436, 0XA006, }, + { 31, 0xa438, 0Xffff, }, + { 31, 0xa436, 0XA004, }, + { 31, 0xa438, 0X00d5, }, + { 31, 0xa436, 0XA002, }, + { 31, 0xa438, 0X1182, }, + { 31, 0xa436, 0XA000, }, + { 31, 0xa438, 0X1075, }, + { 31, 0xa436, 0XA008, }, + { 31, 0xa438, 0X0700, }, + +}; + +/* +static const MMD_REG Rtl8251b_n1_ramcode[] = +{ + +}; +*/ + +static const MMD_REG Rtl8251b_n2_ramcode[] = +{ + { 31, 0xa436, 0XA016, }, + { 31, 0xa438, 0X0020, }, + { 31, 0xa436, 0XA012, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa436, 0XA014, }, + { 31, 0xa438, 0X1800, }, + { 31, 0xa438, 0X8010, }, + { 31, 0xa438, 0X1800, }, + { 31, 0xa438, 0X8017, }, + { 31, 0xa438, 0X1800, }, + { 31, 0xa438, 0X8048, }, + { 31, 0xa438, 0X1800, }, + { 31, 0xa438, 0X8053, }, + { 31, 0xa438, 0X1800, }, + { 31, 0xa438, 0X80d8, }, + { 31, 0xa438, 0X1800, }, + { 31, 0xa438, 0X8122, }, + { 31, 0xa438, 0X1800, }, + { 31, 0xa438, 0X815b, }, + { 31, 0xa438, 0X1800, }, + { 31, 0xa438, 0X8162, }, + { 31, 0xa438, 0Xbb20, }, + { 31, 0xa438, 0Xd706, }, + { 31, 0xa438, 0X607d, }, + { 31, 0xa438, 0X1800, }, + { 31, 0xa438, 0X0cbc, }, + { 31, 0xa438, 0X1800, }, + { 31, 0xa438, 0X0cc4, }, + { 31, 0xa438, 0X0c1f, }, + { 31, 0xa438, 0X0d04, }, + { 31, 0xa438, 0X8dc0, }, + { 31, 0xa438, 0X1000, }, + { 31, 0xa438, 0X11bd, }, + { 31, 0xa438, 0Xa00a, }, + { 31, 0xa438, 0Xa710, }, + { 31, 0xa438, 0Xd103, }, + { 31, 0xa438, 0Xd04c, }, + { 31, 0xa438, 0X1000, }, + { 31, 0xa438, 0X1175, }, + { 31, 0xa438, 0Xd700, }, + { 31, 0xa438, 0X5fb4, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0c1f, }, + { 31, 0xa438, 0X0d06, }, + { 31, 0xa438, 0X8dc0, }, + { 31, 0xa438, 0X1000, }, + { 31, 0xa438, 0X11bd, }, + { 31, 0xa438, 0X8710, }, + { 31, 0xa438, 0Xa190, }, + { 31, 0xa438, 0Xa204, }, + { 31, 0xa438, 0X8280, }, + { 31, 0xa438, 0Xa404, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X1800, }, + { 31, 0xa438, 0X0acd, }, + { 31, 0xa438, 0X0c1f, }, + { 31, 0xa438, 0X0d07, }, + { 31, 0xa438, 0X8dc0, }, + { 31, 0xa438, 0X1000, }, + { 31, 0xa438, 0X11bd, }, + { 31, 0xa438, 0Xd40d, }, + { 31, 0xa438, 0X1000, }, + { 31, 0xa438, 0X110d, }, + { 31, 0xa438, 0Xa208, }, + { 31, 0xa438, 0X1800, }, + { 31, 0xa438, 0X0bae, }, + { 31, 0xa438, 0X1000, }, + { 31, 0xa438, 0X1175, }, + { 31, 0xa438, 0Xd700, }, + { 31, 0xa438, 0X5fab, }, + { 31, 0xa438, 0X0c1f, }, + { 31, 0xa438, 0X0d06, }, + { 31, 0xa438, 0X8dc0, }, + { 31, 0xa438, 0X1000, }, + { 31, 0xa438, 0X11bd, }, + { 31, 0xa438, 0Xd418, }, + { 31, 0xa438, 0X1000, }, + { 31, 0xa438, 0X110d, }, + { 31, 0xa438, 0X0c1f, }, + { 31, 0xa438, 0X0d03, }, + { 31, 0xa438, 0X8dc0, }, + { 31, 0xa438, 0X1000, }, + { 31, 0xa438, 0X11bd, }, + { 31, 0xa438, 0X0c03, }, + { 31, 0xa438, 0X1502, }, + { 31, 0xa438, 0Xa780, }, + { 31, 0xa438, 0Xa20e, }, + { 31, 0xa438, 0X9503, }, + { 31, 0xa438, 0Xd704, }, + { 31, 0xa438, 0X409c, }, + { 31, 0xa438, 0Xd114, }, + { 31, 0xa438, 0Xd04d, }, + { 31, 0xa438, 0Xf003, }, + { 31, 0xa438, 0Xd114, }, + { 31, 0xa438, 0Xd04d, }, + { 31, 0xa438, 0X0c03, }, + { 31, 0xa438, 0X1502, }, + { 31, 0xa438, 0Xa003, }, + { 31, 0xa438, 0X9503, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0Xcb4c, }, + { 31, 0xa438, 0X1000, }, + { 31, 0xa438, 0X1175, }, + { 31, 0xa438, 0Xd700, }, + { 31, 0xa438, 0X5fb4, }, + { 31, 0xa438, 0X0c03, }, + { 31, 0xa438, 0X1502, }, + { 31, 0xa438, 0X0c60, }, + { 31, 0xa438, 0X0720, }, + { 31, 0xa438, 0Xa220, }, + { 31, 0xa438, 0X9503, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0Xcb4d, }, + { 31, 0xa438, 0Xd704, }, + { 31, 0xa438, 0X409c, }, + { 31, 0xa438, 0Xd128, }, + { 31, 0xa438, 0Xd04f, }, + { 31, 0xa438, 0Xf003, }, + { 31, 0xa438, 0Xd128, }, + { 31, 0xa438, 0Xd04f, }, + { 31, 0xa438, 0X1000, }, + { 31, 0xa438, 0X1175, }, + { 31, 0xa438, 0Xd700, }, + { 31, 0xa438, 0X5fb4, }, + { 31, 0xa438, 0X0c03, }, + { 31, 0xa438, 0X1502, }, + { 31, 0xa438, 0X0c60, }, + { 31, 0xa438, 0X0740, }, + { 31, 0xa438, 0Xa210, }, + { 31, 0xa438, 0X9503, }, + { 31, 0xa438, 0Xd704, }, + { 31, 0xa438, 0X409c, }, + { 31, 0xa438, 0Xd114, }, + { 31, 0xa438, 0Xd04e, }, + { 31, 0xa438, 0Xf003, }, + { 31, 0xa438, 0Xd114, }, + { 31, 0xa438, 0Xd04e, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0Xcb4e, }, + { 31, 0xa438, 0X1000, }, + { 31, 0xa438, 0X1175, }, + { 31, 0xa438, 0Xd700, }, + { 31, 0xa438, 0X5fb4, }, + { 31, 0xa438, 0X0c1f, }, + { 31, 0xa438, 0X0d06, }, + { 31, 0xa438, 0X8dc0, }, + { 31, 0xa438, 0X1000, }, + { 31, 0xa438, 0X11bd, }, + { 31, 0xa438, 0X0cc0, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0c07, }, + { 31, 0xa438, 0X0c01, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X1800, }, + { 31, 0xa438, 0X0c96, }, + { 31, 0xa438, 0X1000, }, + { 31, 0xa438, 0X1175, }, + { 31, 0xa438, 0X1000, }, + { 31, 0xa438, 0X1193, }, + { 31, 0xa438, 0Xd700, }, + { 31, 0xa438, 0X5f74, }, + { 31, 0xa438, 0Xd704, }, + { 31, 0xa438, 0X35ac, }, + { 31, 0xa438, 0X8120, }, + { 31, 0xa438, 0X0cc0, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0c03, }, + { 31, 0xa438, 0X0101, }, + { 31, 0xa438, 0X0ce0, }, + { 31, 0xa438, 0X0320, }, + { 31, 0xa438, 0Xcc21, }, + { 31, 0xa438, 0X0c1f, }, + { 31, 0xa438, 0X0d03, }, + { 31, 0xa438, 0X8dc0, }, + { 31, 0xa438, 0X1000, }, + { 31, 0xa438, 0X11bd, }, + { 31, 0xa438, 0X0cc0, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0c07, }, + { 31, 0xa438, 0X0c07, }, + { 31, 0xa438, 0X0c03, }, + { 31, 0xa438, 0X1502, }, + { 31, 0xa438, 0Xa280, }, + { 31, 0xa438, 0X8780, }, + { 31, 0xa438, 0X0c60, }, + { 31, 0xa438, 0X0700, }, + { 31, 0xa438, 0X9503, }, + { 31, 0xa438, 0Xd704, }, + { 31, 0xa438, 0X409c, }, + { 31, 0xa438, 0Xd110, }, + { 31, 0xa438, 0Xd04d, }, + { 31, 0xa438, 0Xf003, }, + { 31, 0xa438, 0Xd110, }, + { 31, 0xa438, 0Xd04d, }, + { 31, 0xa438, 0Xcb4a, }, + { 31, 0xa438, 0X1000, }, + { 31, 0xa438, 0X1175, }, + { 31, 0xa438, 0Xd700, }, + { 31, 0xa438, 0X5fb4, }, + { 31, 0xa438, 0X0c03, }, + { 31, 0xa438, 0X1502, }, + { 31, 0xa438, 0Xa240, }, + { 31, 0xa438, 0Xa180, }, + { 31, 0xa438, 0Xa201, }, + { 31, 0xa438, 0Xa780, }, + { 31, 0xa438, 0X9503, }, + { 31, 0xa438, 0Xd114, }, + { 31, 0xa438, 0Xd04a, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0Xcb4b, }, + { 31, 0xa438, 0X1000, }, + { 31, 0xa438, 0X1175, }, + { 31, 0xa438, 0Xd700, }, + { 31, 0xa438, 0X5fb4, }, + { 31, 0xa438, 0X1800, }, + { 31, 0xa438, 0X0bc3, }, + { 31, 0xa438, 0X1800, }, + { 31, 0xa438, 0X0bc3, }, + { 31, 0xa438, 0Xd702, }, + { 31, 0xa438, 0X4168, }, + { 31, 0xa438, 0Xd700, }, + { 31, 0xa438, 0X6121, }, + { 31, 0xa438, 0Xa402, }, + { 31, 0xa438, 0Xa480, }, + { 31, 0xa438, 0Xd120, }, + { 31, 0xa438, 0Xd04d, }, + { 31, 0xa438, 0X1000, }, + { 31, 0xa438, 0X1175, }, + { 31, 0xa438, 0Xd700, }, + { 31, 0xa438, 0X5fb4, }, + { 31, 0xa438, 0Xa190, }, + { 31, 0xa438, 0Xa2a0, }, + { 31, 0xa438, 0Xa00a, }, + { 31, 0xa438, 0Xa404, }, + { 31, 0xa438, 0Xd700, }, + { 31, 0xa438, 0X60a1, }, + { 31, 0xa438, 0Xa402, }, + { 31, 0xa438, 0Xd702, }, + { 31, 0xa438, 0X4048, }, + { 31, 0xa438, 0Xa480, }, + { 31, 0xa438, 0Xd417, }, + { 31, 0xa438, 0X1000, }, + { 31, 0xa438, 0X110d, }, + { 31, 0xa438, 0Xd702, }, + { 31, 0xa438, 0X41a9, }, + { 31, 0xa438, 0X8190, }, + { 31, 0xa438, 0X82a0, }, + { 31, 0xa438, 0X800a, }, + { 31, 0xa438, 0Xa404, }, + { 31, 0xa438, 0Xd700, }, + { 31, 0xa438, 0X6061, }, + { 31, 0xa438, 0Xa402, }, + { 31, 0xa438, 0Xcb4f, }, + { 31, 0xa438, 0X1000, }, + { 31, 0xa438, 0X1175, }, + { 31, 0xa438, 0Xd702, }, + { 31, 0xa438, 0X7faa, }, + { 31, 0xa438, 0Xa190, }, + { 31, 0xa438, 0Xa2a0, }, + { 31, 0xa438, 0Xa00a, }, + { 31, 0xa438, 0Xa404, }, + { 31, 0xa438, 0Xd700, }, + { 31, 0xa438, 0X6061, }, + { 31, 0xa438, 0Xa402, }, + { 31, 0xa438, 0X8480, }, + { 31, 0xa438, 0X1000, }, + { 31, 0xa438, 0X1175, }, + { 31, 0xa438, 0X1000, }, + { 31, 0xa438, 0X1193, }, + { 31, 0xa438, 0Xd700, }, + { 31, 0xa438, 0X5f7a, }, + { 31, 0xa438, 0Xd704, }, + { 31, 0xa438, 0X5f36, }, + { 31, 0xa438, 0X1800, }, + { 31, 0xa438, 0X0ce3, }, + { 31, 0xa438, 0X1000, }, + { 31, 0xa438, 0X110d, }, + { 31, 0xa438, 0Xd419, }, + { 31, 0xa438, 0X1000, }, + { 31, 0xa438, 0X110d, }, + { 31, 0xa438, 0X1800, }, + { 31, 0xa438, 0X01ae, }, + { 31, 0xa436, 0XA10E, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa436, 0XA10C, }, + { 31, 0xa438, 0X01ac, }, + { 31, 0xa436, 0XA10A, }, + { 31, 0xa438, 0X0cdb, }, + { 31, 0xa436, 0XA108, }, + { 31, 0xa438, 0X0bbd, }, + { 31, 0xa436, 0XA106, }, + { 31, 0xa438, 0X0c1a, }, + { 31, 0xa436, 0XA104, }, + { 31, 0xa438, 0X0bad, }, + { 31, 0xa436, 0XA102, }, + { 31, 0xa438, 0X0ac7, }, + { 31, 0xa436, 0XA100, }, + { 31, 0xa438, 0X0cba, }, + { 31, 0xa436, 0XA110, }, + { 31, 0xa438, 0X007f, }, + + { 31, 0xa436, 0XA016, }, + { 31, 0xa438, 0X0020, }, + { 31, 0xa436, 0XA012, }, + { 31, 0xa438, 0X1ff8, }, + { 31, 0xa436, 0XA014, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0Xa00a, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa438, 0X0000, }, + { 31, 0xa436, 0XA164, }, + { 31, 0xa438, 0X0CC1, }, + { 31, 0xa436, 0XA166, }, + { 31, 0xa438, 0X0CC2, }, + { 31, 0xa436, 0XA168, }, + { 31, 0xa438, 0X0CC3, }, + { 31, 0xa436, 0XA16A, }, + { 31, 0xa438, 0X106E, }, + { 31, 0xa436, 0XA16C, }, + { 31, 0xa438, 0X0F31, }, + { 31, 0xa436, 0XA16E, }, + { 31, 0xa438, 0X0FB5, }, + { 31, 0xa436, 0XA170, }, + { 31, 0xa438, 0X1009, }, + { 31, 0xa436, 0XA172, }, + { 31, 0xa438, 0X3fff, }, + { 31, 0xa436, 0XA162, }, + { 31, 0xa438, 0X007f, }, + +}; + +static const MMD_REG Rtl8251b_uc2_ramcode[] = +{ + { 31, 0xa436, 0Xb87c, }, + { 31, 0xa438, 0X8a45, }, + { 31, 0xa436, 0Xb87e, }, + { 31, 0xa438, 0Xaf8a, }, + { 31, 0xa438, 0X5daf, }, + { 31, 0xa438, 0X8a63, }, + { 31, 0xa438, 0Xaf8a, }, + { 31, 0xa438, 0X6caf, }, + { 31, 0xa438, 0X8a7e, }, + { 31, 0xa438, 0Xaf8a, }, + { 31, 0xa438, 0X8daf, }, + { 31, 0xa438, 0X8a96, }, + { 31, 0xa438, 0Xaf8a, }, + { 31, 0xa438, 0X9caf, }, + { 31, 0xa438, 0X8a9c, }, + { 31, 0xa438, 0X028a, }, + { 31, 0xa438, 0X9caf, }, + { 31, 0xa438, 0X211f, }, + { 31, 0xa438, 0X0265, }, + { 31, 0xa438, 0Xcb02, }, + { 31, 0xa438, 0X8f90, }, + { 31, 0xa438, 0Xaf21, }, + { 31, 0xa438, 0X6fa1, }, + { 31, 0xa438, 0X1909, }, + { 31, 0xa438, 0X028f, }, + { 31, 0xa438, 0X0a02, }, + { 31, 0xa438, 0X2261, }, + { 31, 0xa438, 0Xaf21, }, + { 31, 0xa438, 0X2e02, }, + { 31, 0xa438, 0X2261, }, + { 31, 0xa438, 0Xaf21, }, + { 31, 0xa438, 0X2ead, }, + { 31, 0xa438, 0X2109, }, + { 31, 0xa438, 0Xe08f, }, + { 31, 0xa438, 0Xffac, }, + { 31, 0xa438, 0X2503, }, + { 31, 0xa438, 0Xaf4b, }, + { 31, 0xa438, 0Xeeaf, }, + { 31, 0xa438, 0X4beb, }, + { 31, 0xa438, 0Xad35, }, + { 31, 0xa438, 0X03af, }, + { 31, 0xa438, 0X421b, }, + { 31, 0xa438, 0Xaf42, }, + { 31, 0xa438, 0X5ce1, }, + { 31, 0xa438, 0X8652, }, + { 31, 0xa438, 0Xaf49, }, + { 31, 0xa438, 0Xdcf8, }, + { 31, 0xa438, 0Xe08f, }, + { 31, 0xa438, 0Xe7a0, }, + { 31, 0xa438, 0X0005, }, + { 31, 0xa438, 0X028a, }, + { 31, 0xa438, 0Xbdae, }, + { 31, 0xa438, 0X13a0, }, + { 31, 0xa438, 0X0105, }, + { 31, 0xa438, 0X028b, }, + { 31, 0xa438, 0X4eae, }, + { 31, 0xa438, 0X0ba0, }, + { 31, 0xa438, 0X0205, }, + { 31, 0xa438, 0X028b, }, + { 31, 0xa438, 0X7aae, }, + { 31, 0xa438, 0X0302, }, + { 31, 0xa438, 0X8bd2, }, + { 31, 0xa438, 0Xfc04, }, + { 31, 0xa438, 0Xf8fa, }, + { 31, 0xa438, 0Xef69, }, + { 31, 0xa438, 0Xfafb, }, + { 31, 0xa438, 0Xe080, }, + { 31, 0xa438, 0X15ac, }, + { 31, 0xa438, 0X2302, }, + { 31, 0xa438, 0Xae45, }, + { 31, 0xa438, 0Xe08f, }, + { 31, 0xa438, 0Xfdad, }, + { 31, 0xa438, 0X2002, }, + { 31, 0xa438, 0Xae3d, }, + { 31, 0xa438, 0Xe08f, }, + { 31, 0xa438, 0Xe9a0, }, + { 31, 0xa438, 0X0002, }, + { 31, 0xa438, 0Xae35, }, + { 31, 0xa438, 0Xee8f, }, + { 31, 0xa438, 0Xe800, }, + { 31, 0xa438, 0X028c, }, + { 31, 0xa438, 0X86bf, }, + { 31, 0xa438, 0X8feb, }, + { 31, 0xa438, 0Xd819, }, + { 31, 0xa438, 0Xd9ef, }, + { 31, 0xa438, 0X64bf, }, + { 31, 0xa438, 0X8fef, }, + { 31, 0xa438, 0Xd819, }, + { 31, 0xa438, 0Xd9ef, }, + { 31, 0xa438, 0X7402, }, + { 31, 0xa438, 0X73a4, }, + { 31, 0xa438, 0Xad50, }, + { 31, 0xa438, 0X18ee, }, + { 31, 0xa438, 0X8fff, }, + { 31, 0xa438, 0X0102, }, + { 31, 0xa438, 0X8de1, }, + { 31, 0xa438, 0X0273, }, + { 31, 0xa438, 0Xd7ef, }, + { 31, 0xa438, 0X47e5, }, + { 31, 0xa438, 0X85a6, }, + { 31, 0xa438, 0Xe485, }, + { 31, 0xa438, 0Xa5ee, }, + { 31, 0xa438, 0X8fe7, }, + { 31, 0xa438, 0X01ae, }, + { 31, 0xa438, 0X37d1, }, + { 31, 0xa438, 0X00bf, }, + { 31, 0xa438, 0X8f63, }, + { 31, 0xa438, 0X0274, }, + { 31, 0xa438, 0X76bf, }, + { 31, 0xa438, 0X8f69, }, + { 31, 0xa438, 0X0274, }, + { 31, 0xa438, 0X76bf, }, + { 31, 0xa438, 0X8f6f, }, + { 31, 0xa438, 0X0274, }, + { 31, 0xa438, 0X76bf, }, + { 31, 0xa438, 0X8f75, }, + { 31, 0xa438, 0X0274, }, + { 31, 0xa438, 0X76d1, }, + { 31, 0xa438, 0X01bf, }, + { 31, 0xa438, 0X8f60, }, + { 31, 0xa438, 0X0274, }, + { 31, 0xa438, 0X76bf, }, + { 31, 0xa438, 0X8f66, }, + { 31, 0xa438, 0X0274, }, + { 31, 0xa438, 0X76bf, }, + { 31, 0xa438, 0X8f6c, }, + { 31, 0xa438, 0X0274, }, + { 31, 0xa438, 0X76bf, }, + { 31, 0xa438, 0X8f72, }, + { 31, 0xa438, 0X0274, }, + { 31, 0xa438, 0X7602, }, + { 31, 0xa438, 0X2261, }, + { 31, 0xa438, 0Xfffe, }, + { 31, 0xa438, 0Xef96, }, + { 31, 0xa438, 0Xfefc, }, + { 31, 0xa438, 0X04f8, }, + { 31, 0xa438, 0Xfafb, }, + { 31, 0xa438, 0Xe085, }, + { 31, 0xa438, 0Xa5e1, }, + { 31, 0xa438, 0X85a6, }, + { 31, 0xa438, 0Xef64, }, + { 31, 0xa438, 0Xd000, }, + { 31, 0xa438, 0Xe18f, }, + { 31, 0xa438, 0Xeaef, }, + { 31, 0xa438, 0X7402, }, + { 31, 0xa438, 0X73f2, }, + { 31, 0xa438, 0Xad50, }, + { 31, 0xa438, 0X10e0, }, + { 31, 0xa438, 0X8fe8, }, + { 31, 0xa438, 0Xac24, }, + { 31, 0xa438, 0X06ee, }, + { 31, 0xa438, 0X8fe7, }, + { 31, 0xa438, 0X02ae, }, + { 31, 0xa438, 0X04ee, }, + { 31, 0xa438, 0X8fe7, }, + { 31, 0xa438, 0X03ff, }, + { 31, 0xa438, 0Xfefc, }, + { 31, 0xa438, 0X04f8, }, + { 31, 0xa438, 0Xf9fa, }, + { 31, 0xa438, 0Xef69, }, + { 31, 0xa438, 0Xfafb, }, + { 31, 0xa438, 0X028c, }, + { 31, 0xa438, 0X86bf, }, + { 31, 0xa438, 0X8feb, }, + { 31, 0xa438, 0Xd819, }, + { 31, 0xa438, 0Xd9bf, }, + { 31, 0xa438, 0X8ff3, }, + { 31, 0xa438, 0Xe28f, }, + { 31, 0xa438, 0Xe8ef, }, + { 31, 0xa438, 0X324b, }, + { 31, 0xa438, 0X021a, }, + { 31, 0xa438, 0X93dc, }, + { 31, 0xa438, 0X19dd, }, + { 31, 0xa438, 0X12e6, }, + { 31, 0xa438, 0X8fe8, }, + { 31, 0xa438, 0Xe38f, }, + { 31, 0xa438, 0Xe91b, }, + { 31, 0xa438, 0X23ad, }, + { 31, 0xa438, 0X3707, }, + { 31, 0xa438, 0Xe08f, }, + { 31, 0xa438, 0Xff48, }, + { 31, 0xa438, 0X02ae, }, + { 31, 0xa438, 0X09ee, }, + { 31, 0xa438, 0X8fe8, }, + { 31, 0xa438, 0X101f, }, + { 31, 0xa438, 0X00e4, }, + { 31, 0xa438, 0X8ffe, }, + { 31, 0xa438, 0Xe48f, }, + { 31, 0xa438, 0Xff02, }, + { 31, 0xa438, 0X8de1, }, + { 31, 0xa438, 0X0273, }, + { 31, 0xa438, 0Xd7ef, }, + { 31, 0xa438, 0X47e5, }, + { 31, 0xa438, 0X85a6, }, + { 31, 0xa438, 0Xe485, }, + { 31, 0xa438, 0Xa5ee, }, + { 31, 0xa438, 0X8fe7, }, + { 31, 0xa438, 0X01ff, }, + { 31, 0xa438, 0Xfeef, }, + { 31, 0xa438, 0X96fe, }, + { 31, 0xa438, 0Xfdfc, }, + { 31, 0xa438, 0X04f8, }, + { 31, 0xa438, 0Xf9fa, }, + { 31, 0xa438, 0Xef69, }, + { 31, 0xa438, 0Xfafb, }, + { 31, 0xa438, 0X028c, }, + { 31, 0xa438, 0X86bf, }, + { 31, 0xa438, 0X8feb, }, + { 31, 0xa438, 0Xd819, }, + { 31, 0xa438, 0Xd9ef, }, + { 31, 0xa438, 0X64bf, }, + { 31, 0xa438, 0X8fef, }, + { 31, 0xa438, 0Xd819, }, + { 31, 0xa438, 0Xd9ef, }, + { 31, 0xa438, 0X7402, }, + { 31, 0xa438, 0X73a4, }, + { 31, 0xa438, 0Xad50, }, + { 31, 0xa438, 0X27bf, }, + { 31, 0xa438, 0X8fed, }, + { 31, 0xa438, 0Xd819, }, + { 31, 0xa438, 0Xd9ef, }, + { 31, 0xa438, 0X64bf, }, + { 31, 0xa438, 0X8ff1, }, + { 31, 0xa438, 0Xd819, }, + { 31, 0xa438, 0Xd9ef, }, + { 31, 0xa438, 0X7402, }, + { 31, 0xa438, 0X73a4, }, + { 31, 0xa438, 0Xad50, }, + { 31, 0xa438, 0X11e2, }, + { 31, 0xa438, 0X8fe8, }, + { 31, 0xa438, 0Xe38f, }, + { 31, 0xa438, 0Xe9ef, }, + { 31, 0xa438, 0X0258, }, + { 31, 0xa438, 0X0f1b, }, + { 31, 0xa438, 0X03ac, }, + { 31, 0xa438, 0X2748, }, + { 31, 0xa438, 0Xae09, }, + { 31, 0xa438, 0Xe08f, }, + { 31, 0xa438, 0Xfee4, }, + { 31, 0xa438, 0X8fff, }, + { 31, 0xa438, 0X028d, }, + { 31, 0xa438, 0Xe102, }, + { 31, 0xa438, 0X2261, }, + { 31, 0xa438, 0Xee8f, }, + { 31, 0xa438, 0Xe700, }, + { 31, 0xa438, 0Xd100, }, + { 31, 0xa438, 0Xbf8f, }, + { 31, 0xa438, 0X6302, }, + { 31, 0xa438, 0X7476, }, + { 31, 0xa438, 0Xbf8f, }, + { 31, 0xa438, 0X6902, }, + { 31, 0xa438, 0X7476, }, + { 31, 0xa438, 0Xbf8f, }, + { 31, 0xa438, 0X6f02, }, + { 31, 0xa438, 0X7476, }, + { 31, 0xa438, 0Xbf8f, }, + { 31, 0xa438, 0X7502, }, + { 31, 0xa438, 0X7476, }, + { 31, 0xa438, 0Xd101, }, + { 31, 0xa438, 0Xbf8f, }, + { 31, 0xa438, 0X6002, }, + { 31, 0xa438, 0X7476, }, + { 31, 0xa438, 0Xbf8f, }, + { 31, 0xa438, 0X6602, }, + { 31, 0xa438, 0X7476, }, + { 31, 0xa438, 0Xbf8f, }, + { 31, 0xa438, 0X6c02, }, + { 31, 0xa438, 0X7476, }, + { 31, 0xa438, 0Xbf8f, }, + { 31, 0xa438, 0X7202, }, + { 31, 0xa438, 0X7476, }, + { 31, 0xa438, 0Xae1f, }, + { 31, 0xa438, 0X12e6, }, + { 31, 0xa438, 0X8fe8, }, + { 31, 0xa438, 0Xe08f, }, + { 31, 0xa438, 0Xffe4, }, + { 31, 0xa438, 0X8ffe, }, + { 31, 0xa438, 0X028c, }, + { 31, 0xa438, 0Xfe02, }, + { 31, 0xa438, 0X8de1, }, + { 31, 0xa438, 0X0273, }, + { 31, 0xa438, 0Xd7ef, }, + { 31, 0xa438, 0X47e5, }, + { 31, 0xa438, 0X85a6, }, + { 31, 0xa438, 0Xe485, }, + { 31, 0xa438, 0Xa5ee, }, + { 31, 0xa438, 0X8fe7, }, + { 31, 0xa438, 0X01ff, }, + { 31, 0xa438, 0Xfeef, }, + { 31, 0xa438, 0X96fe, }, + { 31, 0xa438, 0Xfdfc, }, + { 31, 0xa438, 0X04f8, }, + { 31, 0xa438, 0Xf9fa, }, + { 31, 0xa438, 0Xef69, }, + { 31, 0xa438, 0Xfafb, }, + { 31, 0xa438, 0X1f22, }, + { 31, 0xa438, 0Xee8f, }, + { 31, 0xa438, 0Xeb00, }, + { 31, 0xa438, 0Xee8f, }, + { 31, 0xa438, 0Xec00, }, + { 31, 0xa438, 0Xee8f, }, + { 31, 0xa438, 0Xed00, }, + { 31, 0xa438, 0Xee8f, }, + { 31, 0xa438, 0Xee00, }, + { 31, 0xa438, 0X1f33, }, + { 31, 0xa438, 0Xee8f, }, + { 31, 0xa438, 0Xe500, }, + { 31, 0xa438, 0Xee8f, }, + { 31, 0xa438, 0Xe600, }, + { 31, 0xa438, 0Xbf53, }, + { 31, 0xa438, 0X7d02, }, + { 31, 0xa438, 0X7662, }, + { 31, 0xa438, 0Xef64, }, + { 31, 0xa438, 0Xbf8f, }, + { 31, 0xa438, 0Xe5d8, }, + { 31, 0xa438, 0X19d9, }, + { 31, 0xa438, 0Xef74, }, + { 31, 0xa438, 0X0273, }, + { 31, 0xa438, 0Xbfef, }, + { 31, 0xa438, 0X47dd, }, + { 31, 0xa438, 0X89dc, }, + { 31, 0xa438, 0X1f11, }, + { 31, 0xa438, 0X11a1, }, + { 31, 0xa438, 0Xfffc, }, + { 31, 0xa438, 0X13ad, }, + { 31, 0xa438, 0X3bde, }, + { 31, 0xa438, 0X0d73, }, + { 31, 0xa438, 0Xbf8f, }, + { 31, 0xa438, 0Xedd8, }, + { 31, 0xa438, 0X19d9, }, + { 31, 0xa438, 0Xef64, }, + { 31, 0xa438, 0Xef47, }, + { 31, 0xa438, 0X0273, }, + { 31, 0xa438, 0Xa4ad, }, + { 31, 0xa438, 0X5003, }, + { 31, 0xa438, 0Xdd89, }, + { 31, 0xa438, 0Xdcef, }, + { 31, 0xa438, 0X64bf, }, + { 31, 0xa438, 0X8feb, }, + { 31, 0xa438, 0Xd819, }, + { 31, 0xa438, 0Xd91a, }, + { 31, 0xa438, 0X46dd, }, + { 31, 0xa438, 0X89dc, }, + { 31, 0xa438, 0X12ad, }, + { 31, 0xa438, 0X32ae, }, + { 31, 0xa438, 0X0d42, }, + { 31, 0xa438, 0Xdc19, }, + { 31, 0xa438, 0Xddff, }, + { 31, 0xa438, 0Xfeef, }, + { 31, 0xa438, 0X96fe, }, + { 31, 0xa438, 0Xfdfc, }, + { 31, 0xa438, 0X04f8, }, + { 31, 0xa438, 0Xf9fa, }, + { 31, 0xa438, 0Xef69, }, + { 31, 0xa438, 0Xfafb, }, + { 31, 0xa438, 0X1f22, }, + { 31, 0xa438, 0Xd6ff, }, + { 31, 0xa438, 0Xffef, }, + { 31, 0xa438, 0X03bf, }, + { 31, 0xa438, 0X8ff3, }, + { 31, 0xa438, 0Xef32, }, + { 31, 0xa438, 0X4b02, }, + { 31, 0xa438, 0X1a93, }, + { 31, 0xa438, 0Xef30, }, + { 31, 0xa438, 0Xd819, }, + { 31, 0xa438, 0Xd9ef, }, + { 31, 0xa438, 0X7402, }, + { 31, 0xa438, 0X73a4, }, + { 31, 0xa438, 0Xac50, }, + { 31, 0xa438, 0X04ef, }, + { 31, 0xa438, 0X32ef, }, + { 31, 0xa438, 0X64e0, }, + { 31, 0xa438, 0X8fe9, }, + { 31, 0xa438, 0X12ef, }, + { 31, 0xa438, 0X121b, }, + { 31, 0xa438, 0X10ac, }, + { 31, 0xa438, 0X2fd9, }, + { 31, 0xa438, 0Xef03, }, + { 31, 0xa438, 0Xbf8f, }, + { 31, 0xa438, 0Xf348, }, + { 31, 0xa438, 0X021a, }, + { 31, 0xa438, 0X90ec, }, + { 31, 0xa438, 0Xff19, }, + { 31, 0xa438, 0Xecff, }, + { 31, 0xa438, 0Xd001, }, + { 31, 0xa438, 0X1f11, }, + { 31, 0xa438, 0Xef21, }, + { 31, 0xa438, 0X1b23, }, + { 31, 0xa438, 0Xad37, }, + { 31, 0xa438, 0X050c, }, + { 31, 0xa438, 0X0111, }, + { 31, 0xa438, 0Xaef4, }, + { 31, 0xa438, 0Xe18f, }, + { 31, 0xa438, 0Xff1e, }, + { 31, 0xa438, 0X10e5, }, + { 31, 0xa438, 0X8fff, }, + { 31, 0xa438, 0Xfffe, }, + { 31, 0xa438, 0Xef96, }, + { 31, 0xa438, 0Xfefd, }, + { 31, 0xa438, 0Xfc04, }, + { 31, 0xa438, 0X725a, }, + { 31, 0xa438, 0X725d, }, + { 31, 0xa438, 0X7260, }, + { 31, 0xa438, 0X7263, }, + { 31, 0xa438, 0X71fa, }, + { 31, 0xa438, 0X71fd, }, + { 31, 0xa438, 0X7200, }, + { 31, 0xa438, 0X7203, }, + { 31, 0xa438, 0X8f24, }, + { 31, 0xa438, 0X8f27, }, + { 31, 0xa438, 0X8f2a, }, + { 31, 0xa438, 0X8f2d, }, + { 31, 0xa438, 0X8f30, }, + { 31, 0xa438, 0X8f33, }, + { 31, 0xa438, 0X8f36, }, + { 31, 0xa438, 0X8f39, }, + { 31, 0xa438, 0X722a, }, + { 31, 0xa438, 0X722d, }, + { 31, 0xa438, 0X7230, }, + { 31, 0xa438, 0X7233, }, + { 31, 0xa438, 0X721e, }, + { 31, 0xa438, 0X7221, }, + { 31, 0xa438, 0X7224, }, + { 31, 0xa438, 0X7227, }, + { 31, 0xa438, 0X7212, }, + { 31, 0xa438, 0X7215, }, + { 31, 0xa438, 0X7218, }, + { 31, 0xa438, 0X721b, }, + { 31, 0xa438, 0X724e, }, + { 31, 0xa438, 0X7251, }, + { 31, 0xa438, 0X7254, }, + { 31, 0xa438, 0X7257, }, + { 31, 0xa438, 0X7242, }, + { 31, 0xa438, 0X7245, }, + { 31, 0xa438, 0X7248, }, + { 31, 0xa438, 0X724b, }, + { 31, 0xa438, 0X7236, }, + { 31, 0xa438, 0X7239, }, + { 31, 0xa438, 0X723c, }, + { 31, 0xa438, 0X723f, }, + { 31, 0xa438, 0X8f60, }, + { 31, 0xa438, 0X8f66, }, + { 31, 0xa438, 0X8f6c, }, + { 31, 0xa438, 0X8f72, }, + { 31, 0xa438, 0X8f78, }, + { 31, 0xa438, 0X8f7e, }, + { 31, 0xa438, 0X8f84, }, + { 31, 0xa438, 0X8f8a, }, + { 31, 0xa438, 0X8f63, }, + { 31, 0xa438, 0X8f69, }, + { 31, 0xa438, 0X8f6f, }, + { 31, 0xa438, 0X8f75, }, + { 31, 0xa438, 0X8f7b, }, + { 31, 0xa438, 0X8f81, }, + { 31, 0xa438, 0X8f87, }, + { 31, 0xa438, 0X8f8d, }, + { 31, 0xa438, 0X8f3c, }, + { 31, 0xa438, 0X8f3f, }, + { 31, 0xa438, 0X8f42, }, + { 31, 0xa438, 0X8f45, }, + { 31, 0xa438, 0X8f48, }, + { 31, 0xa438, 0X8f4b, }, + { 31, 0xa438, 0X8f4e, }, + { 31, 0xa438, 0X8f51, }, + { 31, 0xa438, 0X8f54, }, + { 31, 0xa438, 0Xf8f9, }, + { 31, 0xa438, 0Xfaef, }, + { 31, 0xa438, 0X69fa, }, + { 31, 0xa438, 0Xfbe2, }, + { 31, 0xa438, 0X8fff, }, + { 31, 0xa438, 0Xad30, }, + { 31, 0xa438, 0X06d1, }, + { 31, 0xa438, 0X00d3, }, + { 31, 0xa438, 0X00ae, }, + { 31, 0xa438, 0X04d1, }, + { 31, 0xa438, 0X01d3, }, + { 31, 0xa438, 0X0fbf, }, + { 31, 0xa438, 0X8d5f, }, + { 31, 0xa438, 0Xd700, }, + { 31, 0xa438, 0X0802, }, + { 31, 0xa438, 0X7677, }, + { 31, 0xa438, 0Xef13, }, + { 31, 0xa438, 0Xbf8d, }, + { 31, 0xa438, 0X67d7, }, + { 31, 0xa438, 0X0008, }, + { 31, 0xa438, 0X0276, }, + { 31, 0xa438, 0X77ad, }, + { 31, 0xa438, 0X3106, }, + { 31, 0xa438, 0Xd100, }, + { 31, 0xa438, 0Xd300, }, + { 31, 0xa438, 0Xae04, }, + { 31, 0xa438, 0Xd101, }, + { 31, 0xa438, 0Xd30f, }, + { 31, 0xa438, 0Xbf8d, }, + { 31, 0xa438, 0X6fd7, }, + { 31, 0xa438, 0X0008, }, + { 31, 0xa438, 0X0276, }, + { 31, 0xa438, 0X77ef, }, + { 31, 0xa438, 0X13bf, }, + { 31, 0xa438, 0X8d77, }, + { 31, 0xa438, 0Xd700, }, + { 31, 0xa438, 0X0802, }, + { 31, 0xa438, 0X7677, }, + { 31, 0xa438, 0Xad32, }, + { 31, 0xa438, 0X06d1, }, + { 31, 0xa438, 0X00d3, }, + { 31, 0xa438, 0X00ae, }, + { 31, 0xa438, 0X04d1, }, + { 31, 0xa438, 0X01d3, }, + { 31, 0xa438, 0X03bf, }, + { 31, 0xa438, 0X8d7f, }, + { 31, 0xa438, 0Xd700, }, + { 31, 0xa438, 0X1802, }, + { 31, 0xa438, 0X7677, }, + { 31, 0xa438, 0Xef13, }, + { 31, 0xa438, 0Xbf8d, }, + { 31, 0xa438, 0X97d7, }, + { 31, 0xa438, 0X0018, }, + { 31, 0xa438, 0X0276, }, + { 31, 0xa438, 0X77ad, }, + { 31, 0xa438, 0X3306, }, + { 31, 0xa438, 0Xd101, }, + { 31, 0xa438, 0Xd300, }, + { 31, 0xa438, 0Xae04, }, + { 31, 0xa438, 0Xd100, }, + { 31, 0xa438, 0Xd300, }, + { 31, 0xa438, 0Xbf8d, }, + { 31, 0xa438, 0Xafd7, }, + { 31, 0xa438, 0X0010, }, + { 31, 0xa438, 0X0276, }, + { 31, 0xa438, 0X77ef, }, + { 31, 0xa438, 0X13bf, }, + { 31, 0xa438, 0X8dbf, }, + { 31, 0xa438, 0Xd700, }, + { 31, 0xa438, 0X1002, }, + { 31, 0xa438, 0X7677, }, + { 31, 0xa438, 0X1f33, }, + { 31, 0xa438, 0Xe38f, }, + { 31, 0xa438, 0Xfdac, }, + { 31, 0xa438, 0X3803, }, + { 31, 0xa438, 0Xaf8f, }, + { 31, 0xa438, 0X02ad, }, + { 31, 0xa438, 0X3405, }, + { 31, 0xa438, 0Xe18f, }, + { 31, 0xa438, 0Xfbae, }, + { 31, 0xa438, 0X02d1, }, + { 31, 0xa438, 0X00bf, }, + { 31, 0xa438, 0X8dcf, }, + { 31, 0xa438, 0Xd700, }, + { 31, 0xa438, 0X1202, }, + { 31, 0xa438, 0X7677, }, + { 31, 0xa438, 0Xad35, }, + { 31, 0xa438, 0X07d1, }, + { 31, 0xa438, 0X01d3, }, + { 31, 0xa438, 0X04af, }, + { 31, 0xa438, 0X8e9b, }, + { 31, 0xa438, 0Xd100, }, + { 31, 0xa438, 0Xd300, }, + { 31, 0xa438, 0Xbf8f, }, + { 31, 0xa438, 0X5702, }, + { 31, 0xa438, 0X7476, }, + { 31, 0xa438, 0Xbf6b, }, + { 31, 0xa438, 0Xd002, }, + { 31, 0xa438, 0X7495, }, + { 31, 0xa438, 0X1a13, }, + { 31, 0xa438, 0Xbf6b, }, + { 31, 0xa438, 0Xd002, }, + { 31, 0xa438, 0X7476, }, + { 31, 0xa438, 0Xbf6d, }, + { 31, 0xa438, 0X2c02, }, + { 31, 0xa438, 0X7495, }, + { 31, 0xa438, 0Xac28, }, + { 31, 0xa438, 0X0bbf, }, + { 31, 0xa438, 0X6d2f, }, + { 31, 0xa438, 0X0274, }, + { 31, 0xa438, 0X95ac, }, + { 31, 0xa438, 0X2802, }, + { 31, 0xa438, 0Xae0b, }, + { 31, 0xa438, 0Xad35, }, + { 31, 0xa438, 0X04d1, }, + { 31, 0xa438, 0X01ae, }, + { 31, 0xa438, 0X0fd1, }, + { 31, 0xa438, 0X0fae, }, + { 31, 0xa438, 0X0bad, }, + { 31, 0xa438, 0X3504, }, + { 31, 0xa438, 0Xd105, }, + { 31, 0xa438, 0Xae04, }, + { 31, 0xa438, 0Xd10f, }, + { 31, 0xa438, 0Xae00, }, + { 31, 0xa438, 0Xbf8f, }, + { 31, 0xa438, 0X5a02, }, + { 31, 0xa438, 0X7476, }, + { 31, 0xa438, 0Xe38f, }, + { 31, 0xa438, 0Xfcac, }, + { 31, 0xa438, 0X3805, }, + { 31, 0xa438, 0Xad36, }, + { 31, 0xa438, 0X1aae, }, + { 31, 0xa438, 0X0ad1, }, + { 31, 0xa438, 0X00bf, }, + { 31, 0xa438, 0X719d, }, + { 31, 0xa438, 0X0274, }, + { 31, 0xa438, 0X76ae, }, + { 31, 0xa438, 0X0ed1, }, + { 31, 0xa438, 0X02bf, }, + { 31, 0xa438, 0X8f5d, }, + { 31, 0xa438, 0X0274, }, + { 31, 0xa438, 0X76bf, }, + { 31, 0xa438, 0X719d, }, + { 31, 0xa438, 0X0274, }, + { 31, 0xa438, 0X76ff, }, + { 31, 0xa438, 0Xfeef, }, + { 31, 0xa438, 0X96fe, }, + { 31, 0xa438, 0Xfdfc, }, + { 31, 0xa438, 0X04f8, }, + { 31, 0xa438, 0Xf9fa, }, + { 31, 0xa438, 0Xef69, }, + { 31, 0xa438, 0Xfafb, }, + { 31, 0xa438, 0X1f33, }, + { 31, 0xa438, 0Xe38f, }, + { 31, 0xa438, 0Xfdad, }, + { 31, 0xa438, 0X3803, }, + { 31, 0xa438, 0X028d, }, + { 31, 0xa438, 0Xe1ff, }, + { 31, 0xa438, 0Xfeef, }, + { 31, 0xa438, 0X96fe, }, + { 31, 0xa438, 0Xfdfc, }, + { 31, 0xa438, 0X0455, }, + { 31, 0xa438, 0Xb020, }, + { 31, 0xa438, 0X55b0, }, + { 31, 0xa438, 0Xa055, }, + { 31, 0xa438, 0Xb120, }, + { 31, 0xa438, 0X55b1, }, + { 31, 0xa438, 0Xa0fc, }, + { 31, 0xa438, 0Xb022, }, + { 31, 0xa438, 0Xfcb0, }, + { 31, 0xa438, 0Xa2fc, }, + { 31, 0xa438, 0Xb122, }, + { 31, 0xa438, 0Xfcb1, }, + { 31, 0xa438, 0Xa2fd, }, + { 31, 0xa438, 0Xadda, }, + { 31, 0xa438, 0Xcaad, }, + { 31, 0xa438, 0Xda97, }, + { 31, 0xa438, 0Xadda, }, + { 31, 0xa438, 0X64ad, }, + { 31, 0xa438, 0Xda20, }, + { 31, 0xa438, 0Xadda, }, + { 31, 0xa438, 0Xfdad, }, + { 31, 0xa438, 0Xdcca, }, + { 31, 0xa438, 0Xaddc, }, + { 31, 0xa438, 0X97ad, }, + { 31, 0xa438, 0Xdc64, }, + { 31, 0xa438, 0Xaddc, }, + { 31, 0xa438, 0Xaad0, }, + { 31, 0xa438, 0X98a7, }, + { 31, 0xa438, 0Xbf1e, }, + { 31, 0xa438, 0X20bc, }, + { 31, 0xa438, 0X3299, }, + { 31, 0xa438, 0Xadfe, }, + { 31, 0xa438, 0X85ad, }, + { 31, 0xa438, 0Xfe44, }, + { 31, 0xa438, 0Xadfe, }, + { 31, 0xa438, 0X30ad, }, + { 31, 0xa438, 0Xfeff, }, + { 31, 0xa438, 0Xae00, }, + { 31, 0xa438, 0Xebae, }, + { 31, 0xa438, 0X00aa, }, + { 31, 0xa438, 0Xae00, }, + { 31, 0xa438, 0X96ae, }, + { 31, 0xa438, 0X00dd, }, + { 31, 0xa438, 0Xad94, }, + { 31, 0xa438, 0Xccad, }, + { 31, 0xa438, 0X9499, }, + { 31, 0xa438, 0Xad94, }, + { 31, 0xa438, 0X88ad, }, + { 31, 0xa438, 0X94ff, }, + { 31, 0xa438, 0Xad94, }, + { 31, 0xa438, 0Xeead, }, + { 31, 0xa438, 0X94bb, }, + { 31, 0xa438, 0Xad94, }, + { 31, 0xa438, 0Xaaad, }, + { 31, 0xa438, 0X94f8, }, + { 31, 0xa438, 0Xf9fa, }, + { 31, 0xa438, 0Xef69, }, + { 31, 0xa438, 0Xfafb, }, + { 31, 0xa438, 0Xe28f, }, + { 31, 0xa438, 0Xffee, }, + { 31, 0xa438, 0X8fff, }, + { 31, 0xa438, 0X00e3, }, + { 31, 0xa438, 0X8ffd, }, + { 31, 0xa438, 0Xee8f, }, + { 31, 0xa438, 0Xfd01, }, + { 31, 0xa438, 0Xee8f, }, + { 31, 0xa438, 0Xfc01, }, + { 31, 0xa438, 0X028d, }, + { 31, 0xa438, 0Xe1e6, }, + { 31, 0xa438, 0X8fff, }, + { 31, 0xa438, 0Xe78f, }, + { 31, 0xa438, 0Xfdee, }, + { 31, 0xa438, 0X8ffc, }, + { 31, 0xa438, 0X00ee, }, + { 31, 0xa438, 0X8fe7, }, + { 31, 0xa438, 0X00ff, }, + { 31, 0xa438, 0Xfeef, }, + { 31, 0xa438, 0X96fe, }, + { 31, 0xa438, 0Xfdfc, }, + { 31, 0xa438, 0X0400, }, + { 31, 0xa436, 0Xb85e, }, + { 31, 0xa438, 0X211C, }, + { 31, 0xa436, 0Xb860, }, + { 31, 0xa438, 0X216C, }, + { 31, 0xa436, 0Xb862, }, + { 31, 0xa438, 0X212B, }, + { 31, 0xa436, 0Xb864, }, + { 31, 0xa438, 0X4BE8, }, + { 31, 0xa436, 0Xb886, }, + { 31, 0xa438, 0X4209, }, + { 31, 0xa436, 0Xb888, }, + { 31, 0xa438, 0X49DA, }, + { 31, 0xa436, 0Xb88a, }, + { 31, 0xa438, 0Xffff, }, + { 31, 0xa436, 0Xb88c, }, + { 31, 0xa438, 0Xffff, }, + { 31, 0xa436, 0Xb838, }, + { 31, 0xa438, 0X003f, }, +}; + +static const MMD_REG Rtl8251b_uc_ramcode[] = +{ + { 31, 0xa436, 0X85f8, }, + { 31, 0xa438, 0Xaf86, }, + { 31, 0xa438, 0X10af, }, + { 31, 0xa438, 0X8622, }, + { 31, 0xa438, 0Xaf86, }, + { 31, 0xa438, 0X4aaf, }, + { 31, 0xa438, 0X864a, }, + { 31, 0xa438, 0Xaf86, }, + { 31, 0xa438, 0X4aaf, }, + { 31, 0xa438, 0X864a, }, + { 31, 0xa438, 0Xaf86, }, + { 31, 0xa438, 0X4aaf, }, + { 31, 0xa438, 0X864a, }, + { 31, 0xa438, 0Xa104, }, + { 31, 0xa438, 0X0ce0, }, + { 31, 0xa438, 0X8394, }, + { 31, 0xa438, 0Xad20, }, + { 31, 0xa438, 0X03af, }, + { 31, 0xa438, 0X2b67, }, + { 31, 0xa438, 0Xaf2a, }, + { 31, 0xa438, 0Xf0af, }, + { 31, 0xa438, 0X2b8d, }, + { 31, 0xa438, 0Xbf6b, }, + { 31, 0xa438, 0X7202, }, + { 31, 0xa438, 0X72dc, }, + { 31, 0xa438, 0Xa106, }, + { 31, 0xa438, 0X19e1, }, + { 31, 0xa438, 0X8164, }, + { 31, 0xa438, 0Xbf6d, }, + { 31, 0xa438, 0X5b02, }, + { 31, 0xa438, 0X72bd, }, + { 31, 0xa438, 0X0d13, }, + { 31, 0xa438, 0Xbf6d, }, + { 31, 0xa438, 0X5802, }, + { 31, 0xa438, 0X72bd, }, + { 31, 0xa438, 0X0d13, }, + { 31, 0xa438, 0Xbf6d, }, + { 31, 0xa438, 0X6a02, }, + { 31, 0xa438, 0X72bd, }, + { 31, 0xa438, 0X0275, }, + { 31, 0xa438, 0X12af, }, + { 31, 0xa438, 0X380d, }, + { 31, 0xa436, 0Xb818, }, + { 31, 0xa438, 0X2ae4, }, + { 31, 0xa436, 0Xb81a, }, + { 31, 0xa438, 0X380A, }, + { 31, 0xa436, 0Xb81c, }, + { 31, 0xa438, 0Xffff, }, + { 31, 0xa436, 0Xb81e, }, + { 31, 0xa438, 0Xffff, }, + { 31, 0xa436, 0Xb850, }, + { 31, 0xa438, 0Xffff, }, + { 31, 0xa436, 0Xb852, }, + { 31, 0xa438, 0Xffff, }, + { 31, 0xa436, 0Xb878, }, + { 31, 0xa438, 0Xffff, }, + { 31, 0xa436, 0Xb884, }, + { 31, 0xa438, 0Xffff, }, + { 31, 0xa436, 0Xb832, }, + { 31, 0xa438, 0X0003, }, + +}; + +static const MMD_REG Rtl8251b_data_ramcode[] = +{ + + { 31, 0xB88E, 0XC15C, }, + { 31, 0xB890, 0X30B, }, + { 31, 0xB88E, 0XC15D, }, + { 31, 0xB890, 0X303, }, + { 31, 0xB88E, 0XC15E, }, + { 31, 0xB890, 0X512, }, + { 31, 0xB88E, 0XC15F, }, + { 31, 0xB890, 0X506, }, + { 31, 0xB88E, 0XC160, }, + { 31, 0xB890, 0X80D, }, + { 31, 0xB88E, 0XC161, }, + { 31, 0xB890, 0X807, }, + { 31, 0xB88E, 0XC162, }, + { 31, 0xB890, 0X914, }, + { 31, 0xB88E, 0XC163, }, + { 31, 0xB890, 0X90B, }, + { 31, 0xB88E, 0XC164, }, + { 31, 0xB890, 0XE1E, }, + { 31, 0xB88E, 0XC165, }, + { 31, 0xB890, 0XE12, }, + { 31, 0xB88E, 0XC166, }, + { 31, 0xB890, 0X1621, }, + { 31, 0xB88E, 0XC167, }, + { 31, 0xB890, 0X1617, }, + { 31, 0xB88E, 0XC168, }, + { 31, 0xB890, 0X1C34, }, + { 31, 0xB88E, 0XC169, }, + { 31, 0xB890, 0X1C24, }, + { 31, 0xB88E, 0XC16A, }, + { 31, 0xB890, 0X2B4C, }, + { 31, 0xB88E, 0XC16B, }, + { 31, 0xB890, 0X2B37, }, + { 31, 0xB88E, 0XC197, }, + { 31, 0xB890, 0X355E, }, + { 31, 0xB88E, 0XC198, }, + { 31, 0xB890, 0XF8BC, }, + { 31, 0xB88E, 0XC199, }, + { 31, 0xB890, 0XF834, }, + { 31, 0xB88E, 0XC19A, }, + { 31, 0xB890, 0X6C88, }, + { 31, 0xB88E, 0XC19B, }, + { 31, 0xB890, 0X6C01, }, + { 31, 0xB88E, 0XC19C, }, + { 31, 0xB890, 0XA676, }, + { 31, 0xB88E, 0XC19D, }, + { 31, 0xB890, 0XA67F, }, + { 31, 0xB88E, 0XC19E, }, + { 31, 0xB890, 0XA05D, }, + { 31, 0xB88E, 0XC19F, }, + { 31, 0xB890, 0XA06C, }, + { 31, 0xB88E, 0XC1A0, }, + { 31, 0xB890, 0X4BF, }, + { 31, 0xB88E, 0XC1A1, }, + { 31, 0xB890, 0X43B, }, + { 31, 0xB88E, 0XC1A2, }, + { 31, 0xB890, 0X61EC, }, + { 31, 0xB88E, 0XC1A3, }, + { 31, 0xB890, 0X6190, }, + { 31, 0xB88E, 0XC1A4, }, + { 31, 0xB890, 0X885B, }, + { 31, 0xB88E, 0XC1A5, }, + { 31, 0xB890, 0X88DB, }, + { 31, 0xB88E, 0XC1A6, }, + { 31, 0xB890, 0X9EA8, }, + { 31, 0xB88E, 0XC16C, }, + { 31, 0xB890, 0X206, }, + { 31, 0xB88E, 0XC16D, }, + { 31, 0xB890, 0X203, }, + { 31, 0xB88E, 0XC16E, }, + { 31, 0xB890, 0X309, }, + { 31, 0xB88E, 0XC16F, }, + { 31, 0xB890, 0X304, }, + { 31, 0xB88E, 0XC170, }, + { 31, 0xB890, 0X506, }, + { 31, 0xB88E, 0XC171, }, + { 31, 0xB890, 0X504, }, + { 31, 0xB88E, 0XC172, }, + { 31, 0xB890, 0X509, }, + { 31, 0xB88E, 0XC173, }, + { 31, 0xB890, 0X506, }, + { 31, 0xB88E, 0XC174, }, + { 31, 0xB890, 0X70C, }, + { 31, 0xB88E, 0XC175, }, + { 31, 0xB890, 0X708, }, + { 31, 0xB88E, 0XC176, }, + { 31, 0xB890, 0X90D, }, + { 31, 0xB88E, 0XC177, }, + { 31, 0xB890, 0X90A, }, + { 31, 0xB88E, 0XC178, }, + { 31, 0xB890, 0XB13, }, + { 31, 0xB88E, 0XC179, }, + { 31, 0xB890, 0XB0E, }, + { 31, 0xB88E, 0XC17A, }, + { 31, 0xB890, 0X101D, }, + { 31, 0xB88E, 0XC17B, }, + { 31, 0xB890, 0X1013, }, + { 31, 0xB88E, 0XC17C, }, + { 31, 0xB890, 0X1523, }, + { 31, 0xB88E, 0XC17D, }, + { 31, 0xB890, 0X1519, }, + { 31, 0xB88E, 0XC17E, }, + { 31, 0xB890, 0X1D29, }, + { 31, 0xB88E, 0XC17F, }, + { 31, 0xB890, 0X1D22, }, + { 31, 0xB88E, 0XC180, }, + { 31, 0xB890, 0X282F, }, + { 31, 0xB88E, 0XC181, }, + { 31, 0xB890, 0X282E, }, + { 31, 0xB88E, 0XC182, }, + { 31, 0xB890, 0X3634, }, + { 31, 0xB88E, 0XC183, }, + { 31, 0xB890, 0X363E, }, + { 31, 0xB88E, 0XC184, }, + { 31, 0xB890, 0X473A, }, + { 31, 0xB88E, 0XC185, }, + { 31, 0xB890, 0X474B, }, + { 31, 0xB88E, 0XC1A7, }, + { 31, 0xB890, 0X9ECD, }, + { 31, 0xB88E, 0XC1A8, }, + { 31, 0xB890, 0X4DD3, }, + { 31, 0xB88E, 0XC1A9, }, + { 31, 0xB890, 0X4DBC, }, + { 31, 0xB88E, 0XC1AA, }, + { 31, 0xB890, 0X6E97, }, + { 31, 0xB88E, 0XC1AB, }, + { 31, 0xB890, 0X6E0E, }, + { 31, 0xB88E, 0XC1AC, }, + { 31, 0xB890, 0X9FD6, }, + { 31, 0xB88E, 0XC1AD, }, + { 31, 0xB890, 0X9F2D, }, + { 31, 0xB88E, 0XC1AE, }, + { 31, 0xB890, 0X2C57, }, + { 31, 0xB88E, 0XC1AF, }, + { 31, 0xB890, 0X2C18, }, + { 31, 0xB88E, 0XC1B0, }, + { 31, 0xB890, 0X5E4E, }, + { 31, 0xB88E, 0XC1B1, }, + { 31, 0xB890, 0X5E8C, }, + { 31, 0xB88E, 0XC1B2, }, + { 31, 0xB890, 0X5BAF, }, + { 31, 0xB88E, 0XC1B3, }, + { 31, 0xB890, 0X5BFE, }, + { 31, 0xB88E, 0XC1B4, }, + { 31, 0xB890, 0X1801, }, + { 31, 0xB88E, 0XC1B5, }, + { 31, 0xB890, 0X183C, }, + { 31, 0xB88E, 0XC1B6, }, + { 31, 0xB890, 0X23CD, }, + { 31, 0xB88E, 0XC1B7, }, + { 31, 0xB890, 0X23C9, }, + { 31, 0xB88E, 0XC1B8, }, + { 31, 0xB890, 0X3E92, }, + { 31, 0xB88E, 0XC1B9, }, + { 31, 0xB890, 0X3E84, }, + { 31, 0xB88E, 0XC1BA, }, + { 31, 0xB890, 0X3C57, }, + { 31, 0xB88E, 0XC1BB, }, + { 31, 0xB890, 0X3C20, }, + { 31, 0xB88E, 0XC1BC, }, + { 31, 0xB890, 0XCC1C, }, + { 31, 0xB88E, 0XC1BD, }, + { 31, 0xB890, 0XCC56, }, + { 31, 0xB88E, 0XC1BE, }, + { 31, 0xB890, 0X34E1, }, + { 31, 0xB88E, 0XC1BF, }, + { 31, 0xB890, 0X3480, }, + { 31, 0xB88E, 0XC1C0, }, + { 31, 0xB890, 0X40, }, + + { 31, 0xB88E, 0XC00F, }, + { 31, 0xB890, 0X3502, }, + { 31, 0xB88E, 0XC010, }, + { 31, 0xB890, 0X204, }, + { 31, 0xB88E, 0XC011, }, + { 31, 0xB890, 0X203, }, + { 31, 0xB88E, 0XC012, }, + { 31, 0xB890, 0X305, }, + { 31, 0xB88E, 0XC013, }, + { 31, 0xB890, 0X303, }, + { 31, 0xB88E, 0XC014, }, + { 31, 0xB890, 0X406, }, + { 31, 0xB88E, 0XC015, }, + { 31, 0xB890, 0X404, }, + { 31, 0xB88E, 0XC016, }, + { 31, 0xB890, 0X508, }, + { 31, 0xB88E, 0XC017, }, + { 31, 0xB890, 0X506, }, + { 31, 0xB88E, 0XC018, }, + { 31, 0xB890, 0X60A, }, + { 31, 0xB88E, 0XC019, }, + { 31, 0xB890, 0X607, }, + { 31, 0xB88E, 0XC01A, }, + { 31, 0xB890, 0X80D, }, + { 31, 0xB88E, 0XC01B, }, + { 31, 0xB890, 0X80A, }, + { 31, 0xB88E, 0XC01C, }, + { 31, 0xB890, 0XB11, }, + { 31, 0xB88E, 0XC01D, }, + { 31, 0xB890, 0XB0D, }, + { 31, 0xB88E, 0XC01E, }, + { 31, 0xB890, 0XE15, }, + { 31, 0xB88E, 0XC01F, }, + { 31, 0xB890, 0XE10, }, + { 31, 0xB88E, 0XC020, }, + { 31, 0xB890, 0X111A, }, + { 31, 0xB88E, 0XC021, }, + { 31, 0xB890, 0X1114, }, + { 31, 0xB88E, 0XC022, }, + { 31, 0xB890, 0X1729, }, + { 31, 0xB88E, 0XC023, }, + { 31, 0xB890, 0X171B, }, + { 31, 0xB88E, 0XC024, }, + { 31, 0xB890, 0X1F36, }, + { 31, 0xB88E, 0XC025, }, + { 31, 0xB890, 0X1F22, }, + { 31, 0xB88E, 0XC026, }, + { 31, 0xB890, 0X2843, }, + { 31, 0xB88E, 0XC027, }, + { 31, 0xB890, 0X2832, }, + { 31, 0xB88E, 0XC047, }, + { 31, 0xB890, 0X365F, }, + { 31, 0xB88E, 0XC048, }, + { 31, 0xB890, 0XBE27, }, + { 31, 0xB88E, 0XC049, }, + { 31, 0xB890, 0XBE10, }, + { 31, 0xB88E, 0XC04A, }, + { 31, 0xB890, 0X8458, }, + { 31, 0xB88E, 0XC04B, }, + { 31, 0xB890, 0X84E4, }, + { 31, 0xB88E, 0XC04C, }, + { 31, 0xB890, 0X60C3, }, + { 31, 0xB88E, 0XC04D, }, + { 31, 0xB890, 0X60E9, }, + { 31, 0xB88E, 0XC04E, }, + { 31, 0xB890, 0XA885, }, + { 31, 0xB88E, 0XC04F, }, + { 31, 0xB890, 0XA86A, }, + { 31, 0xB88E, 0XC050, }, + { 31, 0xB890, 0XF1C5, }, + { 31, 0xB88E, 0XC051, }, + { 31, 0xB890, 0XF1E3, }, + { 31, 0xB88E, 0XC052, }, + { 31, 0xB890, 0XF791, }, + { 31, 0xB88E, 0XC053, }, + { 31, 0xB890, 0XF73F, }, + { 31, 0xB88E, 0XC054, }, + { 31, 0xB890, 0X5C79, }, + { 31, 0xB88E, 0XC055, }, + { 31, 0xB890, 0X5C02, }, + { 31, 0xB88E, 0XC056, }, + { 31, 0xB890, 0X9564, }, + { 31, 0xB88E, 0XC057, }, + { 31, 0xB890, 0X9547, }, + { 31, 0xB88E, 0XC058, }, + { 31, 0xB890, 0XC393, }, + { 31, 0xB88E, 0XC059, }, + { 31, 0xB890, 0XC30C, }, + { 31, 0xB88E, 0XC05A, }, + { 31, 0xB890, 0XB00D, }, + { 31, 0xB88E, 0XC05B, }, + { 31, 0xB890, 0XB064, }, + { 31, 0xB88E, 0XC05C, }, + { 31, 0xB890, 0X7B7, }, + { 31, 0xB88E, 0XC05D, }, + { 31, 0xB890, 0X79A, }, + { 31, 0xB88E, 0XC05E, }, + { 31, 0xB890, 0X1E62, }, + { 31, 0xB88E, 0XC05F, }, + { 31, 0xB890, 0X1E23, }, + { 31, 0xB88E, 0XC283, }, + { 31, 0xB890, 0X1611, }, + { 31, 0xB88E, 0XC284, }, + { 31, 0xB890, 0X1620, }, + { 31, 0xB88E, 0XC285, }, + { 31, 0xB890, 0X161C, }, + { 31, 0xB88E, 0XC286, }, + { 31, 0xB890, 0X212C, }, + { 31, 0xB88E, 0XC287, }, + { 31, 0xB890, 0X2127, }, + { 31, 0xB88E, 0XC288, }, + { 31, 0xB890, 0X2C37, }, + { 31, 0xB88E, 0XC289, }, + { 31, 0xB890, 0X2C32, }, + { 31, 0xB88E, 0XC28A, }, + { 31, 0xB890, 0X3741, }, + { 31, 0xB88E, 0XC28B, }, + { 31, 0xB890, 0X373D, }, + { 31, 0xB88E, 0XC28C, }, + { 31, 0xB890, 0X424B, }, + { 31, 0xB88E, 0XC28D, }, + { 31, 0xB890, 0X4247, }, + { 31, 0xB88E, 0XC28E, }, + { 31, 0xB890, 0X4D55, }, + { 31, 0xB88E, 0XC28F, }, + { 31, 0xB890, 0X4D52, }, + { 31, 0xB88E, 0XC290, }, + { 31, 0xB890, 0X585C, }, + { 31, 0xB88E, 0XC291, }, + { 31, 0xB890, 0X585A, }, + { 31, 0xB88E, 0XC2AB, }, + { 31, 0xB890, 0X5865, }, + { 31, 0xB88E, 0XC2AC, }, + { 31, 0xB890, 0XE776, }, + { 31, 0xB88E, 0XC2AD, }, + { 31, 0xB890, 0XE769, }, + { 31, 0xB88E, 0XC2AE, }, + { 31, 0xB890, 0XEB06, }, + { 31, 0xB88E, 0XC2AF, }, + { 31, 0xB890, 0XEB56, }, + { 31, 0xB88E, 0XC2B0, }, + { 31, 0xB890, 0XC0F4, }, + { 31, 0xB88E, 0XC2B1, }, + { 31, 0xB890, 0XC04B, }, + { 31, 0xB88E, 0XC2B2, }, + { 31, 0xB890, 0XD53C, }, + { 31, 0xB88E, 0XC2B3, }, + { 31, 0xB890, 0XD502, }, + { 31, 0xB88E, 0XC2B4, }, + { 31, 0xB890, 0X2F4C, }, + { 31, 0xB88E, 0XC2B5, }, + { 31, 0xB890, 0X2FB1, }, + { 31, 0xB88E, 0XC2B6, }, + { 31, 0xB890, 0X333A, }, + { 31, 0xB88E, 0XC2B7, }, + { 31, 0xB890, 0X33B5, }, + { 31, 0xB88E, 0XC2B8, }, + { 31, 0xB890, 0X377A, }, + { 31, 0xB88E, 0XC2B9, }, + { 31, 0xB890, 0X37F8, }, + { 31, 0xB88E, 0XC292, }, + { 31, 0xB890, 0XB, }, + { 31, 0xB88E, 0XC293, }, + { 31, 0xB890, 0X4, }, + { 31, 0xB88E, 0XC294, }, + { 31, 0xB890, 0X813, }, + { 31, 0xB88E, 0XC295, }, + { 31, 0xB890, 0X80C, }, + { 31, 0xB88E, 0XC296, }, + { 31, 0xB890, 0X101A, }, + { 31, 0xB88E, 0XC297, }, + { 31, 0xB890, 0X1014, }, + { 31, 0xB88E, 0XC298, }, + { 31, 0xB890, 0X1822, }, + { 31, 0xB88E, 0XC299, }, + { 31, 0xB890, 0X181B, }, + { 31, 0xB88E, 0XC29A, }, + { 31, 0xB890, 0X1F2B, }, + { 31, 0xB88E, 0XC29B, }, + { 31, 0xB890, 0X1F23, }, + { 31, 0xB88E, 0XC29C, }, + { 31, 0xB890, 0X2732, }, + { 31, 0xB88E, 0XC29D, }, + { 31, 0xB890, 0X272B, }, + { 31, 0xB88E, 0XC29E, }, + { 31, 0xB890, 0X2F39, }, + { 31, 0xB88E, 0XC29F, }, + { 31, 0xB890, 0X2F33, }, + { 31, 0xB88E, 0XC2A0, }, + { 31, 0xB890, 0X363F, }, + { 31, 0xB88E, 0XC2A1, }, + { 31, 0xB890, 0X363A, }, + { 31, 0xB88E, 0XC2A2, }, + { 31, 0xB890, 0X3E44, }, + { 31, 0xB88E, 0XC2A3, }, + { 31, 0xB890, 0X3E42, }, + { 31, 0xB88E, 0XC2A4, }, + { 31, 0xB890, 0X464A, }, + { 31, 0xB88E, 0XC2A5, }, + { 31, 0xB890, 0X464A, }, + { 31, 0xB88E, 0XC2A6, }, + { 31, 0xB890, 0X4D50, }, + { 31, 0xB88E, 0XC2A7, }, + { 31, 0xB890, 0X4D51, }, + { 31, 0xB88E, 0XC2A8, }, + { 31, 0xB890, 0X5556, }, + { 31, 0xB88E, 0XC2A9, }, + { 31, 0xB890, 0X5559, }, + { 31, 0xB88E, 0XC2AA, }, + { 31, 0xB890, 0X5D65, }, + { 31, 0xB88E, 0XC2BA, }, + { 31, 0xB890, 0XBB28, }, + { 31, 0xB88E, 0XC2BB, }, + { 31, 0xB890, 0XBB98, }, + { 31, 0xB88E, 0XC2BC, }, + { 31, 0xB890, 0X7416, }, + { 31, 0xB88E, 0XC2BD, }, + { 31, 0xB890, 0X7450, }, + { 31, 0xB88E, 0XC2BE, }, + { 31, 0xB890, 0X4CFA, }, + { 31, 0xB88E, 0XC2BF, }, + { 31, 0xB890, 0X4C48, }, + { 31, 0xB88E, 0XC2C0, }, + { 31, 0xB890, 0X124C, }, + { 31, 0xB88E, 0XC2C1, }, + { 31, 0xB890, 0X12DC, }, + { 31, 0xB88E, 0XC2C2, }, + { 31, 0xB890, 0XDCEA, }, + { 31, 0xB88E, 0XC2C3, }, + { 31, 0xB890, 0XDCDC, }, + { 31, 0xB88E, 0XC2C4, }, + { 31, 0xB890, 0X9354, }, + { 31, 0xB88E, 0XC2C5, }, + { 31, 0xB890, 0X934A, }, + { 31, 0xB88E, 0XC2C6, }, + { 31, 0xB890, 0X3E80, }, + { 31, 0xB88E, 0XC2C7, }, + { 31, 0xB890, 0X3E33, }, + { 31, 0xB88E, 0XC2C8, }, + { 31, 0xB890, 0XE431, }, + { 31, 0xB88E, 0XC2C9, }, + { 31, 0xB890, 0XE496, }, + { 31, 0xB88E, 0XC2CA, }, + { 31, 0xB890, 0X72E8, }, + { 31, 0xB88E, 0XC2CB, }, + { 31, 0xB890, 0X724E, }, + { 31, 0xB88E, 0XC2CC, }, + { 31, 0xB890, 0X2B9E, }, + { 31, 0xB88E, 0XC2CD, }, + { 31, 0xB890, 0X2B07, }, + { 31, 0xB88E, 0XC2CE, }, + { 31, 0xB890, 0XE454, }, + { 31, 0xB88E, 0XC2CF, }, + { 31, 0xB890, 0XE4C0, }, + { 31, 0xB88E, 0XC2D0, }, + { 31, 0xB890, 0X9C0B, }, + { 31, 0xB88E, 0XC2D1, }, + { 31, 0xB890, 0X9C79, }, + { 31, 0xB88E, 0XC2D2, }, + { 31, 0xB890, 0X5512, }, + { 31, 0xB88E, 0XC110, }, + { 31, 0xB890, 0XC10, }, + { 31, 0xB88E, 0XC111, }, + { 31, 0xB890, 0XC7F, }, + { 31, 0xB88E, 0XC112, }, + { 31, 0xB890, 0X1018, }, + { 31, 0xB88E, 0XC113, }, + { 31, 0xB890, 0X1014, }, + { 31, 0xB88E, 0XC114, }, + { 31, 0xB890, 0X2321, }, + { 31, 0xB88E, 0XC115, }, + { 31, 0xB890, 0X231D, }, + { 31, 0xB88E, 0XC116, }, + { 31, 0xB890, 0X2029, }, + { 31, 0xB88E, 0XC117, }, + { 31, 0xB890, 0X2023, }, + { 31, 0xB88E, 0XC118, }, + { 31, 0xB890, 0X2631, }, + { 31, 0xB88E, 0XC119, }, + { 31, 0xB890, 0X2628, }, + { 31, 0xB88E, 0XC11A, }, + { 31, 0xB890, 0X2A39, }, + { 31, 0xB88E, 0XC11B, }, + { 31, 0xB890, 0X2A2D, }, + { 31, 0xB88E, 0XC11C, }, + { 31, 0xB890, 0X2D40, }, + { 31, 0xB88E, 0XC11D, }, + { 31, 0xB890, 0X2D2C, }, + { 31, 0xB88E, 0XC11E, }, + { 31, 0xB890, 0X2C48, }, + { 31, 0xB88E, 0XC11F, }, + { 31, 0xB890, 0X2C2E, }, + { 31, 0xB88E, 0XC120, }, + { 31, 0xB890, 0X320D, }, + { 31, 0xB88E, 0XC028, }, + { 31, 0xB890, 0X101, }, + { 31, 0xB88E, 0XC029, }, + { 31, 0xB890, 0X101, }, + { 31, 0xB88E, 0XC02A, }, + { 31, 0xB890, 0X102, }, + { 31, 0xB88E, 0XC02B, }, + { 31, 0xB890, 0X101, }, + { 31, 0xB88E, 0XC02C, }, + { 31, 0xB890, 0X202, }, + { 31, 0xB88E, 0XC02D, }, + { 31, 0xB890, 0X202, }, + { 31, 0xB88E, 0XC02E, }, + { 31, 0xB890, 0X303, }, + { 31, 0xB88E, 0XC02F, }, + { 31, 0xB890, 0X303, }, + { 31, 0xB88E, 0XC030, }, + { 31, 0xB890, 0X405, }, + { 31, 0xB88E, 0XC031, }, + { 31, 0xB890, 0X404, }, + { 31, 0xB88E, 0XC032, }, + { 31, 0xB890, 0X507, }, + { 31, 0xB88E, 0XC033, }, + { 31, 0xB890, 0X506, }, + { 31, 0xB88E, 0XC034, }, + { 31, 0xB890, 0X70A, }, + { 31, 0xB88E, 0XC035, }, + { 31, 0xB890, 0X709, }, + { 31, 0xB88E, 0XC036, }, + { 31, 0xB890, 0XA0E, }, + { 31, 0xB88E, 0XC037, }, + { 31, 0xB890, 0XA0D, }, + { 31, 0xB88E, 0XC060, }, + { 31, 0xB890, 0X1B85, }, + { 31, 0xB88E, 0XC061, }, + { 31, 0xB890, 0X1B5D, }, + { 31, 0xB88E, 0XC062, }, + { 31, 0xB890, 0X9219, }, + { 31, 0xB88E, 0XC063, }, + { 31, 0xB890, 0X92E7, }, + { 31, 0xB88E, 0XC064, }, + { 31, 0xB890, 0X4BF3, }, + { 31, 0xB88E, 0XC065, }, + { 31, 0xB890, 0X4BAF, }, + { 31, 0xB88E, 0XC066, }, + { 31, 0xB890, 0X23FF, }, + { 31, 0xB88E, 0XC067, }, + { 31, 0xB890, 0X2386, }, + { 31, 0xB88E, 0XC068, }, + { 31, 0xB890, 0X19E, }, + { 31, 0xB88E, 0XC069, }, + { 31, 0xB890, 0X1B6, }, + { 31, 0xB88E, 0XC06A, }, + { 31, 0xB890, 0X6FD6, }, + { 31, 0xB88E, 0XC06B, }, + { 31, 0xB890, 0X6F82, }, + { 31, 0xB88E, 0XC06C, }, + { 31, 0xB890, 0XDCA4, }, + { 31, 0xB88E, 0XC06D, }, + { 31, 0xB890, 0XDC1C, }, + { 31, 0xB88E, 0XC06E, }, + { 31, 0xB890, 0X8CC5, }, + { 31, 0xB88E, 0XC06F, }, + { 31, 0xB890, 0X8C92, }, + { 31, 0xB88E, 0XC186, }, + { 31, 0xB890, 0X305, }, + { 31, 0xB88E, 0XC187, }, + { 31, 0xB890, 0X306, }, + { 31, 0xB88E, 0XC188, }, + { 31, 0xB890, 0X804, }, + { 31, 0xB88E, 0XC189, }, + { 31, 0xB890, 0X804, }, + { 31, 0xB88E, 0XC18A, }, + { 31, 0xB890, 0X406, }, + { 31, 0xB88E, 0XC18B, }, + { 31, 0xB890, 0X406, }, + { 31, 0xB88E, 0XC18C, }, + { 31, 0xB890, 0X706, }, + { 31, 0xB88E, 0XC18D, }, + { 31, 0xB890, 0X707, }, + { 31, 0xB88E, 0XC18E, }, + { 31, 0xB890, 0X70A, }, + { 31, 0xB88E, 0XC18F, }, + { 31, 0xB890, 0X709, }, + { 31, 0xB88E, 0XC190, }, + { 31, 0xB890, 0XB11, }, + { 31, 0xB88E, 0XC191, }, + { 31, 0xB890, 0XB0F, }, + { 31, 0xB88E, 0XC192, }, + { 31, 0xB890, 0X161C, }, + { 31, 0xB88E, 0XC193, }, + { 31, 0xB890, 0X161D, }, + { 31, 0xB88E, 0XC194, }, + { 31, 0xB890, 0X202C, }, + { 31, 0xB88E, 0XC195, }, + { 31, 0xB890, 0X202A, }, + { 31, 0xB88E, 0XC196, }, + { 31, 0xB890, 0X3F5E, }, + { 31, 0xB88E, 0XC1C1, }, + { 31, 0xB890, 0X40, }, + { 31, 0xB88E, 0XC1C2, }, + { 31, 0xB890, 0X5945, }, + { 31, 0xB88E, 0XC1C3, }, + { 31, 0xB890, 0X5920, }, + { 31, 0xB88E, 0XC1C4, }, + { 31, 0xB890, 0X8807, }, + { 31, 0xB88E, 0XC1C5, }, + { 31, 0xB890, 0X88CD, }, + { 31, 0xB88E, 0XC1C6, }, + { 31, 0xB890, 0X1CAE, }, + { 31, 0xB88E, 0XC1C7, }, + { 31, 0xB890, 0X1CA1, }, + { 31, 0xB88E, 0XC1C8, }, + { 31, 0xB890, 0X3D0D, }, + { 31, 0xB88E, 0XC1C9, }, + { 31, 0xB890, 0X3D20, }, + { 31, 0xB88E, 0XC1CA, }, + { 31, 0xB890, 0X3AB3, }, + { 31, 0xB88E, 0XC1CB, }, + { 31, 0xB890, 0X3AE4, }, + { 31, 0xB88E, 0XC1CC, }, + { 31, 0xB890, 0X6AA6, }, + { 31, 0xB88E, 0XC1CD, }, + { 31, 0xB890, 0X6A43, }, + { 31, 0xB88E, 0XC1CE, }, + { 31, 0xB890, 0X30C8, }, + { 31, 0xB88E, 0XC1CF, }, + { 31, 0xB890, 0X30AF, }, + { 31, 0xB88E, 0XC1D0, }, + { 31, 0xB890, 0XDDFA, }, + { 31, 0xB88E, 0XC1D1, }, + { 31, 0xB890, 0XDD16, }, + { 31, 0xB88E, 0XC212, }, + { 31, 0xB890, 0X202D, }, + { 31, 0xB88E, 0XC213, }, + { 31, 0xB890, 0X2020, }, + { 31, 0xB88E, 0XC214, }, + { 31, 0xB890, 0X202D, }, + { 31, 0xB88E, 0XC215, }, + { 31, 0xB890, 0X2020, }, + { 31, 0xB88E, 0XC216, }, + { 31, 0xB890, 0X202A, }, + { 31, 0xB88E, 0XC217, }, + { 31, 0xB890, 0X2020, }, + { 31, 0xB88E, 0XC218, }, + { 31, 0xB890, 0X202A, }, + { 31, 0xB88E, 0XC219, }, + { 31, 0xB890, 0X2020, }, + { 31, 0xB88E, 0XC21A, }, + { 31, 0xB890, 0X202A, }, + { 31, 0xB88E, 0XC21B, }, + { 31, 0xB890, 0X2020, }, + { 31, 0xB88E, 0XC21C, }, + { 31, 0xB890, 0X2019, }, + { 31, 0xB88E, 0XC24D, }, + { 31, 0xB890, 0X8400, }, + { 31, 0xB88E, 0XC24E, }, + { 31, 0xB890, 0XB4, }, + { 31, 0xB88E, 0XC24F, }, + { 31, 0xB890, 0X0, }, + { 31, 0xB88E, 0XC250, }, + { 31, 0xB890, 0XB4, }, + { 31, 0xB88E, 0XC251, }, + { 31, 0xB890, 0X0, }, + { 31, 0xB88E, 0XC252, }, + { 31, 0xB890, 0XF8, }, + { 31, 0xB88E, 0XC253, }, + { 31, 0xB890, 0X0, }, + { 31, 0xB88E, 0XC254, }, + { 31, 0xB890, 0XF8, }, + { 31, 0xB88E, 0XC255, }, + { 31, 0xB890, 0X0, }, + { 31, 0xB88E, 0XC256, }, + { 31, 0xB890, 0XF8, }, + { 31, 0xB88E, 0XC257, }, + { 31, 0xB890, 0X0, }, + +}; + +/* +static const MMD_REG Rtl8251b_isram_patch[] = +{ + +}; +*/ + +static BOOL +Rtl8251b_wait_for_bit( + IN HANDLE hDevice, + IN UINT16 dev, + IN UINT16 addr, + IN UINT16 mask, + IN BOOL set, + IN UINT16 timeoutms) +{ + BOOL status = FAILURE; + UINT16 phydata = 0; + + while (--timeoutms) { + status = MmdPhyRead(hDevice, MMD_VEND2, addr, &phydata); + if (!status) + goto exit; + + if (!set) + phydata = ~phydata; + + if ((phydata & mask) == mask) + return SUCCESS; + + SLEEP_1MS; + } + + printf("Timeout (dev=%02x addr=0x%02x mask=0x%02x timeout=%d)\n", + dev, addr, mask, timeoutms); + +exit: + return FAILURE; +} + +BOOLEAN +Rtl8251b_phy_init( + IN HANDLE hDevice, + IN PHY_LINK_ABILITY *pphylinkability, + IN BOOL singlephy + ) +{ + BOOL status = FAILURE; + UINT16 i = 0; /* SW_SDK: use UINT16 instead of UINT8, for MMD_REG array may over 255 entries */ + UINT16 phydata = 0,rev_num,mod_num; + const UINT16 patchver = 0x0014, patchaddr = 0x8023; + + // Polling PHY Status + status = Rtl8251b_wait_for_bit(hDevice, MMD_VEND2, 0xA420, 0x3, 1, 100); + if (status != SUCCESS) { + {printf("err");goto exit;} + } + + // Check phy id rev_num = 0xa /0xb, mod_num = 0x6 + status = MmdPhyRead(hDevice, MMD_PMAPMD, 0x03, &phydata); + if (status != SUCCESS) + {printf("err");goto exit;} + rev_num = phydata&0x000f; + mod_num = (phydata>>4)&0x003f; + + if (((rev_num == 2) && (mod_num == 6)) || ((rev_num == 3) && (mod_num == 6))||((rev_num == 10) &&(mod_num == 6))||((rev_num == 11) &&(mod_num == 6))) + { + printf("rtl8251b and go init flow...\n"); + } + else{ + printf("Not rtl8251b and skip init flow...id = %x \n",phydata); + goto exit; + } + + // MMD 31.0xA436[15:0] = 0x801E + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xA436, 0x801E); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyRead(hDevice, MMD_VEND2, 0xA438, &phydata); + if (status != SUCCESS) + {printf("err");goto exit;} + + // Already patched. + if (phydata == patchver) + { + status = 1; + {printf("err");goto exit;} + } + else + { + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xac90, 0x52A0); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xad2C, 0x8000); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87c, 0x8321); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87e, 0x1133); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xacf8, 0xCCCC); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xbd96, 0x0000); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xbd96, 0x1000); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xa436, 0x8183); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xa438, 0x5965); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87c, 0x80f3); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87e, 0x9980); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87c, 0x8126); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87e, 0xC180); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87c, 0x893a); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87e, 0x8050); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87c, 0x893b); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87e, 0x8000); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87c, 0x8647); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87e, 0xE680); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87c, 0x839E); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87e, 0x2F88); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87c, 0x83F2); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87e, 0x888); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xada0, 0x01A2); + if (status != SUCCESS) + {printf("err");goto exit;} + + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87c, 0x80a0); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87e, 0xB8B6); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87c, 0x805e); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87e, 0xB8B6); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87c, 0x8057); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87e, 0x305A); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87c, 0x8099); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87e, 0x305A); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87c, 0x809a); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87e, 0x5A59); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87c, 0x8058); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87e, 0x5A59); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87c, 0x80a1); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87e, 0xB6BA); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87c, 0x805f); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87e, 0xB6BA); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87c, 0x8052); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87e, 0x3333); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87c, 0x8094); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87e, 0x3333); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87c, 0x8053); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87e, 0x3306); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87c, 0x8095); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87e, 0x3305); + if (status != SUCCESS) + {printf("err");goto exit;} + + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87c, 0x8080); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87e, 0x756A); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87c, 0x803e); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87e, 0x756A); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87c, 0x807f); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87e, 0x7975); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87c, 0x803d); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87e, 0x7975); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87c, 0x8098); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87e, 0x3030); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87c, 0x8056); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87e, 0x3030); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87c, 0x8036); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87e, 0x305A); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87c, 0x8078); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87e, 0x305A); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87c, 0x8031); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87e, 0x3333); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87c, 0x8073); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87e, 0x3333); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb648, 0x7214); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xae06, 0x6C00); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xae06, 0x7C00); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87c, 0x89D1); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87e, 0x0); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87c, 0x89D2); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87e, 0x404); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87c, 0x89CD); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87e, 0xF07); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87c, 0x89CE); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87e, 0xF0B); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87c, 0x89CF); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87e, 0xF0B); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87c, 0x89D0); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87e, 0xF00); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xad94, 0x0032); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xa654, 0x8330); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87c, 0x83A4); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87e, 0x6600); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87c, 0x83A5); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87e, 0x66); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87c, 0x83A6); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87e, 0x6601); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87c, 0x83A7); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87e, 0x100); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87c, 0x83C0); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87e, 0x6600); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87c, 0x83C1); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87e, 0x66); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87c, 0x83C2); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87e, 0x6601); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87c, 0x83C3); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87e, 0x100); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87c, 0x8414); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87e, 0x6600); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87c, 0x8415); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87e, 0x66); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87c, 0x8416); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87e, 0x6601); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87c, 0x8417); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87e, 0x100); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87c, 0x83F8); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87e, 0x6600); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87c, 0x83F9); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87e, 0x66); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87c, 0x83FA); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87e, 0x6601); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87c, 0x83FB); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87e, 0x100); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87c, 0x8015); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87e, 0x800); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87c, 0x8ffd); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87e, 0x0); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87c, 0x8fff); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87e, 0x7F00); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87c, 0x8ffb); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87e, 0x100); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87c, 0x8FEA); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87e, 0x200); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87c, 0x8FE9); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87e, 0x402); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87c, 0x8fef); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87e, 0x100); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87c, 0x8ff0); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87e, 0x600); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87c, 0x8ff1); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87e, 0x100); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87c, 0x8ff2); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb87e, 0xA000); + if (status != SUCCESS) + {printf("err");goto exit;} + + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb820, 0x0010); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = Rtl8251b_wait_for_bit(hDevice, MMD_VEND2, 0xB800, BIT_6, 1, 100); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb896, 0x0000); + if (status != SUCCESS) + {printf("err");goto exit;} + + status = MmdPhyWrite(hDevice, MMD_VEND2, 0xb892, 0x0000); + if (status != SUCCESS) + {printf("err");goto exit;} + + //data_ram + // patch ram code + for(i=0; i +#include +#endif + +#define BIT_0 0x0001 +#define BIT_1 0x0002 +#define BIT_2 0x0004 +#define BIT_3 0x0008 +#define BIT_4 0x0010 +#define BIT_5 0x0020 +#define BIT_6 0x0040 +#define BIT_7 0x0080 +#define BIT_8 0x0100 +#define BIT_9 0x0200 +#define BIT_10 0x0400 +#define BIT_11 0x0800 +#define BIT_12 0x1000 +#define BIT_13 0x2000 +#define BIT_14 0x4000 +#define BIT_15 0x8000 + +#define TRUE 1 +#define FALSE 0 +#define SUCCESS TRUE +#define FAILURE FALSE + + +typedef struct { + unsigned int unit; + unsigned int port; +} HANDLE; + + +#ifndef bool + #define bool int +#endif + +#define a_uint32_t unsigned int +#define BOOLEAN bool +#define BOOL unsigned int//uint32_t +#define UINT32 unsigned int//uint32_t +#define UINT16 unsigned short +#define UINT8 char +#define SLEEP_1MS udelay(1000) +#define SLEEP_100MS mdelay(100) +//#define Sleep(_t) udelay(_t*1000)//osal_time_udelay(_t*1000) +#define IN +#define OUT + + +#define MMD_PMAPMD 1 +#define MMD_PCS 3 +#define MMD_AN 7 +#define MMD_VEND1 30 /* Vendor specific 2 */ +#define MMD_VEND2 31 /* Vendor specific 2 */ + + +typedef struct +{ + UINT16 dev; + UINT16 addr; + UINT16 value; +} MMD_REG; + + +#define NO_LINK 0 +#define LINK_SPEED_10M 10 +#define LINK_SPEED_100M 100 +#define LINK_SPEED_500M 500 +#define LINK_SPEED_1G 1000 +#define LINK_SPEED_2P5G 2500 +#define LINK_SPEED_5G 5000 + +typedef enum +{ + PHY_CROSSPVER_MODE_AUTO = 0, + PHY_CROSSPVER_MODE_MDI, + PHY_CROSSPVER_MODE_MDIX, + PHY_CROSSPVER_MODE_END +} PHY_CROSSPVER_MODE; + +typedef enum +{ + PHY_CROSSPVER_STATUS_MDI = 0, + PHY_CROSSPVER_STATUS_MDIX, + PHY_CROSSPVER_STATUS_END +} PHY_CROSSPVER_STATUS; + +typedef enum +{ + PHY_AUTO_MODE = 0, + PHY_SLAVE_MODE, + PHY_MASTER_MODE, + PHY_MASTER_SLAVE_END +} PHY_MASTERSLAVE_MODE; + +typedef struct +{ + UINT32 Half_10:1; + UINT32 Full_10:1; + + UINT32 Half_100:1; + UINT32 Full_100:1; + + UINT32 Full_1000:1; + + UINT32 adv_2_5G:1; + + UINT32 adv_5G:1; + + UINT32 FC:1; + UINT32 AsyFC:1; +} PHY_LINK_ABILITY; + +typedef struct +{ + UINT8 EEE_100:1; + UINT8 EEE_1000:1; + UINT8 EEE_2_5G:1; + UINT8 EEE_5G:1; +} PHY_EEE_ENABLE; + +typedef struct +{ + UINT8 TX_SWAP:1; + UINT8 RX_SWAP:1; +} PHY_SERDES_POLARITY_SWAP; + +typedef enum +{ + TESTMODE_CHANNEL_NONE = 0, + TESTMODE_CHANNEL_A, + TESTMODE_CHANNEL_B, + TESTMODE_CHANNEL_C, + TESTMODE_CHANNEL_D, + TESTMODE_CHANNEL_END +} PHY_TESTMODE_CHANNEL; + +typedef struct +{ + UINT32 TM1:1; + UINT32 TM2:1; + UINT32 TM3:1; + UINT32 TM4:1; + UINT32 TM5:1; + UINT32 TM6:1; + + UINT32 TONE1:1; + UINT32 TONE2:1; + UINT32 TONE3:1; + UINT32 TONE4:1; + UINT32 TONE5:1; + + UINT32 TMFINISH:1; + + UINT32 NORMAL:1; + UINT32 HARMONIC:1; + UINT32 LINKPLUSE:1; + + PHY_TESTMODE_CHANNEL channel:3; +} PHY_IEEE_TEST_MODE; + +typedef enum +{ + MIS_MATCH_OPEN = 1, // Mis-Match_Open, larger_than_130ohm + MIS_MATCH_SHORT = 2, // Mis-Match_short, less_than_77ohm +} PHY_RTCT_STATUS_MISMATCH; + +typedef struct +{ + BOOL Open; + BOOL Short; + PHY_RTCT_STATUS_MISMATCH Mismatch; +} PHY_RTCT_STATUS; + +typedef struct +{ + + UINT16 linkType; + + UINT32 rxLen; + UINT32 txLen; + + UINT32 channelALen; + UINT32 channelBLen; + UINT32 channelCLen; + UINT32 channelDLen; + + PHY_RTCT_STATUS channelAStatus; + PHY_RTCT_STATUS channelBStatus; + PHY_RTCT_STATUS channelCStatus; + PHY_RTCT_STATUS channelDStatus; +} PHY_RTCT_RESULT; + +typedef enum +{ + PHY_SERDES_MODE_OTHER = 0, + PHY_SERDES_MODE_SGMII, + PHY_SERDES_MODE_HiSGMII, + PHY_SERDES_MODE_2500BASEX, + PHY_SERDES_MODE_5000BASEX, + PHY_SERDES_MODE_USXGMII, + PHY_SERDES_MODE_SFI_10GBASER, + PHY_SERDES_MODE_5000BASER, + PHY_SERDES_MODE_NO_SDS, + PHY_SERDES_MODE_END, +} PHY_SERDES_MODE; + +typedef enum +{ + PHY_SERDES_SPEED_USXGMII = 0, + PHY_SERDES_SPEED_OTHER, + PHY_SERDES_SPEED_SFI, + PHY_SERDES_SPEED_5000BASEX, + PHY_SERDES_SPEED_5000BASER, + PHY_SERDES_SPEED_2500BASEX, + PHY_SERDES_SPEED_HiSGMII, + PHY_SERDES_SPEED_SGMII, +} PHY_SERDES_SPEED; + +typedef enum +{ + PHY_SERDES_OPTION_2500BASEX_SGMII = 0, + PHY_SERDES_OPTION_HiSGMII_SGMII, + PHY_SERDES_OPTION_2500BASEX, + PHY_SERDES_OPTION_HiSGMII, + PHY_SERDES_OPTION_OTHER, +} PHY_SERDES_OPTION; + +typedef struct +{ + UINT16 MASK15_0; + UINT16 MASK31_16; + UINT16 MASK47_32; + UINT16 MASK63_48; + UINT16 MASK79_64; + UINT16 MASK95_80; + UINT16 MASK111_96; + UINT16 MASK127_112; + UINT16 CRC; +} PHY_WAKEUP_FRAME; + +typedef struct +{ + UINT16 REG15_0; + UINT16 REG31_16; + UINT16 REG47_32; + UINT16 REG63_48; +} PHY_MULTICAST_REG; + +typedef struct +{ + UINT16 ADDR15_0; + UINT16 ADDR31_16; + UINT16 ADDR47_32; +} PHY_MAC_ADDRESS; + +typedef struct +{ + UINT32 LINKCHG:1; + UINT32 MAGIC:1; + UINT32 ARBITRARY:1; + UINT32 UNICAST:1; + UINT32 MULTICAST:1; + UINT32 BROADCAST:1; + + UINT32 FRAME0:1; + UINT32 FRAME1:1; + UINT32 FRAME2:1; + UINT32 FRAME3:1; + UINT32 FRAME4:1; + UINT32 FRAME5:1; + UINT32 FRAME6:1; + UINT32 FRAME7:1; + + UINT32 MAXPKTLENGTH; + PHY_MAC_ADDRESS macaddress; + PHY_MULTICAST_REG multicast; + + PHY_WAKEUP_FRAME wakeframe0; + +} PHY_WOL_EVENT; + +typedef struct +{ + bool Enable; + UINT16 Temperature; + UINT16 Temperature_threshold; +}PHY_THERMAL_RESULT; + + +BOOLEAN +MmdPhyRead( + IN HANDLE hDevice, + IN UINT16 dev, + IN UINT16 addr, + OUT UINT16 *data); + +BOOLEAN +MmdPhyWrite( + IN HANDLE hDevice, + IN UINT16 dev, + IN UINT16 addr, + IN UINT16 data); +#endif /* __NIC_RTL8251B_TYPEDEF_H__ */ + + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/Makefile b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/Makefile new file mode 100644 index 00000000..d4df0f6b --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/Makefile @@ -0,0 +1,15 @@ +LOC_DIR=src/hsl/phy/rtl8367_common_V1_4_2 +LIB=HSL + +include $(PRJ_PATH)/make/config.mk + +SRC_LIST += acl.c cpu.c dot1x.c eee.c gpio.c i2c.c igmp.c interrupt.c l2.c leaky.c led.c mirror.c oam.c port.c ptp.c \ + qos.c rate.c rldp.c rtk_switch.c stat.c storm.c svlan.c trap.c trunk.c vlan.c chip.c rtl8367s.c + +EXTRA_CFLAGS += -DMDC_MDIO_OPERATION + +include $(PRJ_PATH)/make/components.mk +include $(PRJ_PATH)/make/defs.mk +include $(PRJ_PATH)/make/target.mk + +all: dep obj diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/acl.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/acl.c new file mode 100644 index 00000000..d9a0a251 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/acl.c @@ -0,0 +1,724 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8367C + * Feature : Here is a list of all functions and variables in ACL module. + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +/* Function Name: + * rtk_filter_igrAcl_init + * Description: + * ACL initialization function + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Pointer pFilter_field or pFilter_cfg point to NULL. + * Note: + * This function enable and intialize ACL function + */ +rtk_api_ret_t rtk_filter_igrAcl_init(void) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->filter_igrAcl_init) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->filter_igrAcl_init(); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_filter_igrAcl_field_add + * Description: + * Add comparison rule to an ACL configuration + * Input: + * pFilter_cfg - The ACL configuration that this function will add comparison rule + * pFilter_field - The comparison rule that will be added. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Pointer pFilter_field or pFilter_cfg point to NULL. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This function add a comparison rule (*pFilter_field) to an ACL configuration (*pFilter_cfg). + * Pointer pFilter_cfg points to an ACL configuration structure, this structure keeps multiple ACL + * comparison rules by means of linked list. Pointer pFilter_field will be added to linked + * list keeped by structure that pFilter_cfg points to. + */ +rtk_api_ret_t rtk_filter_igrAcl_field_add(rtk_filter_cfg_t* pFilter_cfg, rtk_filter_field_t* pFilter_field) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->filter_igrAcl_field_add) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->filter_igrAcl_field_add(pFilter_cfg, pFilter_field); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_filter_igrAcl_cfg_add + * Description: + * Add an ACL configuration to ASIC + * Input: + * filter_id - Start index of ACL configuration. + * pFilter_cfg - The ACL configuration that this function will add comparison rule + * pFilter_action - Action(s) of ACL configuration. + * Output: + * ruleNum - number of rules written in acl table + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Pointer pFilter_field or pFilter_cfg point to NULL. + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_ENTRY_INDEX - Invalid filter_id . + * RT_ERR_NULL_POINTER - Pointer pFilter_action or pFilter_cfg point to NULL. + * RT_ERR_FILTER_INACL_ACT_NOT_SUPPORT - Action is not supported in this chip. + * RT_ERR_FILTER_INACL_RULE_NOT_SUPPORT - Rule is not supported. + * Note: + * This function store pFilter_cfg, pFilter_action into ASIC. The starting + * index(es) is filter_id. + */ +rtk_api_ret_t rtk_filter_igrAcl_cfg_add(rtk_filter_id_t filter_id, rtk_filter_cfg_t* pFilter_cfg, rtk_filter_action_t* pFilter_action, rtk_filter_number_t *ruleNum) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->filter_igrAcl_cfg_add) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->filter_igrAcl_cfg_add(filter_id, pFilter_cfg, pFilter_action, ruleNum); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_filter_igrAcl_cfg_del + * Description: + * Delete an ACL configuration from ASIC + * Input: + * filter_id - Start index of ACL configuration. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_ENTRYIDX - Invalid filter_id. + * Note: + * This function delete a group of ACL rules starting from filter_id. + */ +rtk_api_ret_t rtk_filter_igrAcl_cfg_del(rtk_filter_id_t filter_id) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->filter_igrAcl_cfg_del) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->filter_igrAcl_cfg_del(filter_id); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_filter_igrAcl_cfg_delAll + * Description: + * Delete all ACL entries from ASIC + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This function delete all ACL configuration from ASIC. + */ +rtk_api_ret_t rtk_filter_igrAcl_cfg_delAll(void) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->filter_igrAcl_cfg_delAll) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->filter_igrAcl_cfg_delAll(); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_filter_igrAcl_cfg_get + * Description: + * Get one ingress acl configuration from ASIC. + * Input: + * filter_id - Start index of ACL configuration. + * Output: + * pFilter_cfg - buffer pointer of ingress acl data + * pFilter_action - buffer pointer of ingress acl action + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Pointer pFilter_action or pFilter_cfg point to NULL. + * RT_ERR_FILTER_ENTRYIDX - Invalid entry index. + * Note: + * This function get configuration from ASIC. + */ +rtk_api_ret_t rtk_filter_igrAcl_cfg_get(rtk_filter_id_t filter_id, rtk_filter_cfg_raw_t *pFilter_cfg, rtk_filter_action_t *pAction) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->filter_igrAcl_cfg_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->filter_igrAcl_cfg_get(filter_id, pFilter_cfg, pAction); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_filter_igrAcl_unmatchAction_set + * Description: + * Set action to packets when no ACL configuration match + * Input: + * port - Port id. + * action - Action. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port id. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This function sets action of packets when no ACL configruation matches. + */ +rtk_api_ret_t rtk_filter_igrAcl_unmatchAction_set(rtk_port_t port, rtk_filter_unmatch_action_t action) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->filter_igrAcl_unmatchAction_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->filter_igrAcl_unmatchAction_set(port, action); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_filter_igrAcl_unmatchAction_get + * Description: + * Get action to packets when no ACL configuration match + * Input: + * port - Port id. + * Output: + * pAction - Action. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port id. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This function gets action of packets when no ACL configruation matches. + */ +rtk_api_ret_t rtk_filter_igrAcl_unmatchAction_get(rtk_port_t port, rtk_filter_unmatch_action_t* pAction) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->filter_igrAcl_unmatchAction_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->filter_igrAcl_unmatchAction_get(port, pAction); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_filter_igrAcl_state_set + * Description: + * Set state of ingress ACL. + * Input: + * port - Port id. + * state - Ingress ACL state. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port id. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This function gets action of packets when no ACL configruation matches. + */ +rtk_api_ret_t rtk_filter_igrAcl_state_set(rtk_port_t port, rtk_filter_state_t state) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->filter_igrAcl_state_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->filter_igrAcl_state_set(port, state); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_filter_igrAcl_state_get + * Description: + * Get state of ingress ACL. + * Input: + * port - Port id. + * Output: + * pState - Ingress ACL state. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port id. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This function gets action of packets when no ACL configruation matches. + */ +rtk_api_ret_t rtk_filter_igrAcl_state_get(rtk_port_t port, rtk_filter_state_t* pState) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->filter_igrAcl_state_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->filter_igrAcl_state_get(port, pState); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_filter_igrAcl_template_set + * Description: + * Set template of ingress ACL. + * Input: + * template - Ingress ACL template + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This function set ACL template. + */ +rtk_api_ret_t rtk_filter_igrAcl_template_set(rtk_filter_template_t *aclTemplate) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->filter_igrAcl_template_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->filter_igrAcl_template_set(aclTemplate); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_filter_igrAcl_template_get + * Description: + * Get template of ingress ACL. + * Input: + * template - Ingress ACL template + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This function gets template of ACL. + */ +rtk_api_ret_t rtk_filter_igrAcl_template_get(rtk_filter_template_t *aclTemplate) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->filter_igrAcl_template_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->filter_igrAcl_template_get(aclTemplate); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_filter_igrAcl_field_sel_set + * Description: + * Set user defined field selectors in HSB + * Input: + * index - index of field selector 0-15 + * format - Format of field selector + * offset - Retrieving data offset + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * System support 16 user defined field selctors. + * Each selector can be enabled or disable. + * User can defined retrieving 16-bits in many predefiend + * standard l2/l3/l4 payload. + */ +rtk_api_ret_t rtk_filter_igrAcl_field_sel_set(rtk_uint32 index, rtk_field_sel_t format, rtk_uint32 offset) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->filter_igrAcl_field_sel_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->filter_igrAcl_field_sel_set(index, format, offset); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_filter_igrAcl_field_sel_get + * Description: + * Get user defined field selectors in HSB + * Input: + * index - index of field selector 0-15 + * Output: + * pFormat - Format of field selector + * pOffset - Retrieving data offset + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * None. + */ +rtk_api_ret_t rtk_filter_igrAcl_field_sel_get(rtk_uint32 index, rtk_field_sel_t *pFormat, rtk_uint32 *pOffset) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->filter_igrAcl_field_sel_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->filter_igrAcl_field_sel_get(index, pFormat, pOffset); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_filter_iprange_set + * Description: + * Set IP Range check + * Input: + * index - index of IP Range 0-15 + * type - IP Range check type, 0:Delete a entry, 1: IPv4_SIP, 2: IPv4_DIP, 3:IPv6_SIP, 4:IPv6_DIP + * upperIp - The upper bound of IP range + * lowerIp - The lower Bound of IP range + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - The parameter is out of range + * RT_ERR_INPUT - Input error + * Note: + * upperIp must be larger or equal than lowerIp. + */ +rtk_api_ret_t rtk_filter_iprange_set(rtk_uint32 index, rtk_filter_iprange_t type, ipaddr_t upperIp, ipaddr_t lowerIp) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->filter_iprange_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->filter_iprange_set(index, type, upperIp, lowerIp); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_filter_iprange_get + * Description: + * Set IP Range check + * Input: + * index - index of IP Range 0-15 + * Output: + * pType - IP Range check type, 0:Delete a entry, 1: IPv4_SIP, 2: IPv4_DIP, 3:IPv6_SIP, 4:IPv6_DIP + * pUpperIp - The upper bound of IP range + * pLowerIp - The lower Bound of IP range + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - The parameter is out of range + * Note: + * None. + */ +rtk_api_ret_t rtk_filter_iprange_get(rtk_uint32 index, rtk_filter_iprange_t *pType, ipaddr_t *pUpperIp, ipaddr_t *pLowerIp) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->filter_iprange_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->filter_iprange_get(index, pType, pUpperIp, pLowerIp); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_filter_vidrange_set + * Description: + * Set VID Range check + * Input: + * index - index of VID Range 0-15 + * type - IP Range check type, 0:Delete a entry, 1: CVID, 2: SVID + * upperVid - The upper bound of VID range + * lowerVid - The lower Bound of VID range + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - The parameter is out of range + * RT_ERR_INPUT - Input error + * Note: + * upperVid must be larger or equal than lowerVid. + */ +rtk_api_ret_t rtk_filter_vidrange_set(rtk_uint32 index, rtk_filter_vidrange_t type, rtk_uint32 upperVid, rtk_uint32 lowerVid) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->filter_vidrange_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->filter_vidrange_set(index, type, upperVid, lowerVid); + RTK_API_UNLOCK(); + + return retVal; +} +/* Function Name: + * rtk_filter_vidrange_get + * Description: + * Get VID Range check + * Input: + * index - index of VID Range 0-15 + * Output: + * pType - IP Range check type, 0:Unused, 1: CVID, 2: SVID + * pUpperVid - The upper bound of VID range + * pLowerVid - The lower Bound of VID range + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - The parameter is out of range + * Note: + * None. + */ +rtk_api_ret_t rtk_filter_vidrange_get(rtk_uint32 index, rtk_filter_vidrange_t *pType, rtk_uint32 *pUpperVid, rtk_uint32 *pLowerVid) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->filter_vidrange_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->filter_vidrange_get(index, pType, pUpperVid, pLowerVid); + RTK_API_UNLOCK(); + + return retVal; +} +/* Function Name: + * rtk_filter_portrange_set + * Description: + * Set Port Range check + * Input: + * index - index of Port Range 0-15 + * type - IP Range check type, 0:Delete a entry, 1: Source Port, 2: Destnation Port + * upperPort - The upper bound of Port range + * lowerPort - The lower Bound of Port range + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - The parameter is out of range + * RT_ERR_INPUT - Input error + * Note: + * upperPort must be larger or equal than lowerPort. + */ +rtk_api_ret_t rtk_filter_portrange_set(rtk_uint32 index, rtk_filter_portrange_t type, rtk_uint32 upperPort, rtk_uint32 lowerPort) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->filter_portrange_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->filter_portrange_set(index, type, upperPort, lowerPort); + RTK_API_UNLOCK(); + + return retVal; +} +/* Function Name: + * rtk_filter_portrange_get + * Description: + * Set Port Range check + * Input: + * index - index of Port Range 0-15 + * Output: + * pType - IP Range check type, 0:Delete a entry, 1: Source Port, 2: Destnation Port + * pUpperPort - The upper bound of Port range + * pLowerPort - The lower Bound of Port range + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - The parameter is out of range + * RT_ERR_INPUT - Input error + * Note: + * None. + */ +rtk_api_ret_t rtk_filter_portrange_get(rtk_uint32 index, rtk_filter_portrange_t *pType, rtk_uint32 *pUpperPort, rtk_uint32 *pLowerPort) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->filter_portrange_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->filter_portrange_get(index, pType, pUpperPort, pLowerPort); + RTK_API_UNLOCK(); + + return retVal; + +} +/* Function Name: + * rtk_filter_igrAclPolarity_set + * Description: + * Set ACL Goip control palarity + * Input: + * polarity - 1: High, 0: Low + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * none + */ +rtk_api_ret_t rtk_filter_igrAclPolarity_set(rtk_uint32 polarity) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->filter_igrAclPolarity_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->filter_igrAclPolarity_set(polarity); + RTK_API_UNLOCK(); + + return retVal; +} +/* Function Name: + * rtk_filter_igrAclPolarity_get + * Description: + * Get ACL Goip control palarity + * Input: + * pPolarity - 1: High, 0: Low + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * none + */ +rtk_api_ret_t rtk_filter_igrAclPolarity_get(rtk_uint32* pPolarity) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->filter_igrAclPolarity_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->filter_igrAclPolarity_get(pPolarity); + RTK_API_UNLOCK(); + + return retVal; + +} + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/acl.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/acl.h new file mode 100644 index 00000000..5f06cb36 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/acl.h @@ -0,0 +1,995 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8367/RTL8367C switch high-level API + * + * Feature : The file includes ACL module high-layer API defination + * + */ + +#ifndef __RTK_API_ACL_H__ +#define __RTK_API_ACL_H__ + +/* + * Data Type Declaration + */ +#define RTK_FILTER_RAW_FIELD_NUMBER 8 + +#define ACL_DEFAULT_ABILITY 0 +#define ACL_DEFAULT_UNMATCH_PERMIT 1 + +#define ACL_RULE_FREE 0 +#define ACL_RULE_INAVAILABLE 1 +#define ACL_RULE_CARETAG_MASK 0x1F +#define FILTER_POLICING_MAX 4 +#define FILTER_LOGGING_MAX 8 +#define FILTER_PATTERN_MAX 4 + +#define FILTER_ENACT_CVLAN_MASK 0x01 +#define FILTER_ENACT_SVLAN_MASK 0x02 +#define FILTER_ENACT_PRIORITY_MASK 0x04 +#define FILTER_ENACT_POLICING_MASK 0x08 +#define FILTER_ENACT_FWD_MASK 0x10 +#define FILTER_ENACT_INTGPIO_MASK 0x20 +#define FILTER_ENACT_INIT_MASK 0x3F + +typedef enum rtk_filter_act_cactext_e +{ + FILTER_ENACT_CACTEXT_VLANONLY=0, + FILTER_ENACT_CACTEXT_BOTHVLANTAG, + FILTER_ENACT_CACTEXT_TAGONLY, + FILTER_ENACT_CACTEXT_END, + + +}rtk_filter_act_cactext_t; + +typedef enum rtk_filter_act_ctagfmt_e +{ + FILTER_CTAGFMT_UNTAG=0, + FILTER_CTAGFMT_TAG, + FILTER_CTAGFMT_KEEP, + FILTER_CTAGFMT_KEEP1PRMK, + + +}rtk_filter_act_ctag_t; + + + + + +#define RTK_MAX_NUM_OF_FILTER_TYPE 5 +#define RTK_MAX_NUM_OF_FILTER_FIELD 8 + +#define RTK_DOT_1AS_TIMESTAMP_UNIT_IN_WORD_LENGTH 3UL +#define RTK_IPV6_ADDR_WORD_LENGTH 4UL + +#define FILTER_ENACT_CVLAN_TYPE(type) (type - FILTER_ENACT_CVLAN_INGRESS) +#define FILTER_ENACT_SVLAN_TYPE(type) (type - FILTER_ENACT_SVLAN_INGRESS) +#define FILTER_ENACT_FWD_TYPE(type) (type - FILTER_ENACT_ADD_DSTPORT) +#define FILTER_ENACT_PRI_TYPE(type) (type - FILTER_ENACT_PRIORITY) + +#define RTK_FILTER_FIELD_USED_MAX 8 +#define RTK_FILTER_FIELD_INDEX(template, index) ((template << 4) + index) + + +typedef enum rtk_filter_act_enable_e +{ + /* CVLAN */ + FILTER_ENACT_CVLAN_INGRESS = 0, + FILTER_ENACT_CVLAN_EGRESS, + FILTER_ENACT_CVLAN_SVID, + FILTER_ENACT_POLICING_1, + + /* SVLAN */ + FILTER_ENACT_SVLAN_INGRESS, + FILTER_ENACT_SVLAN_EGRESS, + FILTER_ENACT_SVLAN_CVID, + FILTER_ENACT_POLICING_2, + + /* Policing and Logging */ + FILTER_ENACT_POLICING_0, + + /* Forward */ + FILTER_ENACT_COPY_CPU, + FILTER_ENACT_DROP, + FILTER_ENACT_ADD_DSTPORT, + FILTER_ENACT_REDIRECT, + FILTER_ENACT_MIRROR, + FILTER_ENACT_TRAP_CPU, + FILTER_ENACT_ISOLATION, + + /* QoS */ + FILTER_ENACT_PRIORITY, + FILTER_ENACT_DSCP_REMARK, + FILTER_ENACT_1P_REMARK, + FILTER_ENACT_POLICING_3, + + /* Interrutp and GPO */ + FILTER_ENACT_INTERRUPT, + FILTER_ENACT_GPO, + + /*VLAN tag*/ + FILTER_ENACT_EGRESSCTAG_UNTAG, + FILTER_ENACT_EGRESSCTAG_TAG, + FILTER_ENACT_EGRESSCTAG_KEEP, + FILTER_ENACT_EGRESSCTAG_KEEPAND1PRMK, + + FILTER_ENACT_END, +} rtk_filter_act_enable_t; + + +typedef struct +{ + rtk_filter_act_enable_t actEnable[FILTER_ENACT_END]; + + /* CVLAN acton */ + rtk_uint32 filterCvlanVid; + rtk_uint32 filterCvlanIdx; + /* SVLAN action */ + rtk_uint32 filterSvlanVid; + rtk_uint32 filterSvlanIdx; + + /* Policing action */ + rtk_uint32 filterPolicingIdx[FILTER_POLICING_MAX]; + + /* Forwarding action */ + rtk_portmask_t filterPortmask; + + /* QOS action */ + rtk_uint32 filterPriority; + + /*GPO*/ + rtk_uint32 filterPin; + +} rtk_filter_action_t; + +typedef struct rtk_filter_flag_s +{ + rtk_uint32 value; + rtk_uint32 mask; +} rtk_filter_flag_t; + +typedef enum rtk_filter_care_tag_index_e +{ + CARE_TAG_CTAG = 0, + CARE_TAG_STAG, + CARE_TAG_PPPOE, + CARE_TAG_IPV4, + CARE_TAG_IPV6, + CARE_TAG_TCP, + CARE_TAG_UDP, + CARE_TAG_ARP, + CARE_TAG_RSV1, + CARE_TAG_RSV2, + CARE_TAG_ICMP, + CARE_TAG_IGMP, + CARE_TAG_LLC, + CARE_TAG_RSV3, + CARE_TAG_HTTP, + CARE_TAG_RSV4, + CARE_TAG_RSV5, + CARE_TAG_DHCP, + CARE_TAG_DHCPV6, + CARE_TAG_SNMP, + CARE_TAG_OAM, + CARE_TAG_END, +} rtk_filter_care_tag_index_t; + +typedef struct rtk_filter_care_tag_s +{ + rtk_filter_flag_t tagType[CARE_TAG_END]; +} rtk_filter_care_tag_t; + +typedef struct rtk_filter_field rtk_filter_field_t; + +typedef struct +{ + rtk_uint32 value[RTK_DOT_1AS_TIMESTAMP_UNIT_IN_WORD_LENGTH]; +} rtk_filter_dot1as_timestamp_t; + +typedef enum rtk_filter_field_data_type_e +{ + FILTER_FIELD_DATA_MASK = 0, + FILTER_FIELD_DATA_RANGE, + FILTER_FIELD_DATA_END , +} rtk_filter_field_data_type_t; + +typedef struct rtk_filter_ip_s +{ + rtk_uint32 dataType; + rtk_uint32 rangeStart; + rtk_uint32 rangeEnd; + rtk_uint32 value; + rtk_uint32 mask; +} rtk_filter_ip_t; + +typedef struct rtk_filter_mac_s +{ + rtk_uint32 dataType; + rtk_mac_t value; + rtk_mac_t mask; + rtk_mac_t rangeStart; + rtk_mac_t rangeEnd; +} rtk_filter_mac_t; + +typedef rtk_uint32 rtk_filter_op_t; + +typedef struct rtk_filter_value_s +{ + rtk_uint32 dataType; + rtk_uint32 value; + rtk_uint32 mask; + rtk_uint32 rangeStart; + rtk_uint32 rangeEnd; + +} rtk_filter_value_t; + +typedef struct rtk_filter_activeport_s +{ + rtk_portmask_t value; + rtk_portmask_t mask; + +} rtk_filter_activeport_t; + + + +typedef struct rtk_filter_tag_s +{ + rtk_filter_value_t pri; + rtk_filter_flag_t cfi; + rtk_filter_value_t vid; +} rtk_filter_tag_t; + +typedef struct rtk_filter_ipFlag_s +{ + rtk_filter_flag_t xf; + rtk_filter_flag_t mf; + rtk_filter_flag_t df; +} rtk_filter_ipFlag_t; + +typedef struct +{ + rtk_uint32 addr[RTK_IPV6_ADDR_WORD_LENGTH]; +} rtk_filter_ip6_addr_t; + +typedef struct +{ + rtk_uint32 dataType; + rtk_filter_ip6_addr_t value; + rtk_filter_ip6_addr_t mask; + rtk_filter_ip6_addr_t rangeStart; + rtk_filter_ip6_addr_t rangeEnd; +} rtk_filter_ip6_t; + +typedef rtk_uint32 rtk_filter_number_t; + +typedef struct rtk_filter_pattern_s +{ + rtk_uint32 value[FILTER_PATTERN_MAX]; + rtk_uint32 mask[FILTER_PATTERN_MAX]; +} rtk_filter_pattern_t; + +typedef struct rtk_filter_tcpFlag_s +{ + rtk_filter_flag_t urg; + rtk_filter_flag_t ack; + rtk_filter_flag_t psh; + rtk_filter_flag_t rst; + rtk_filter_flag_t syn; + rtk_filter_flag_t fin; + rtk_filter_flag_t ns; + rtk_filter_flag_t cwr; + rtk_filter_flag_t ece; +} rtk_filter_tcpFlag_t; + +typedef rtk_uint32 rtk_filter_field_raw_t; + +typedef enum rtk_filter_field_temple_input_e +{ + FILTER_FIELD_TEMPLE_INPUT_TYPE = 0, + FILTER_FIELD_TEMPLE_INPUT_INDEX, + FILTER_FIELD_TEMPLE_INPUT_MAX , +} rtk_filter_field_temple_input_t; + +struct rtk_filter_field +{ + rtk_uint32 fieldType; + + union + { + /* L2 struct */ + rtk_filter_mac_t dmac; + rtk_filter_mac_t smac; + rtk_filter_value_t etherType; + rtk_filter_tag_t ctag; + rtk_filter_tag_t relayCtag; + rtk_filter_tag_t stag; + rtk_filter_tag_t l2tag; + rtk_filter_dot1as_timestamp_t dot1asTimeStamp; + rtk_filter_mac_t mac; + + /* L3 struct */ + rtk_filter_ip_t sip; + rtk_filter_ip_t dip; + rtk_filter_ip_t ip; + rtk_filter_value_t protocol; + rtk_filter_value_t ipTos; + rtk_filter_ipFlag_t ipFlag; + rtk_filter_value_t ipOffset; + rtk_filter_ip6_t sipv6; + rtk_filter_ip6_t dipv6; + rtk_filter_ip6_t ipv6; + rtk_filter_value_t ipv6TrafficClass; + rtk_filter_value_t ipv6NextHeader; + rtk_filter_value_t flowLabel; + + /* L4 struct */ + rtk_filter_value_t tcpSrcPort; + rtk_filter_value_t tcpDstPort; + rtk_filter_tcpFlag_t tcpFlag; + rtk_filter_value_t tcpSeqNumber; + rtk_filter_value_t tcpAckNumber; + rtk_filter_value_t udpSrcPort; + rtk_filter_value_t udpDstPort; + rtk_filter_value_t icmpCode; + rtk_filter_value_t icmpType; + rtk_filter_value_t igmpType; + + /* pattern match */ + rtk_filter_pattern_t pattern; + + rtk_filter_value_t inData; + + } filter_pattern_union; + + rtk_uint32 fieldTemplateNo; + rtk_uint32 fieldTemplateIdx[RTK_FILTER_FIELD_USED_MAX]; + + struct rtk_filter_field *next; +}; + +typedef enum rtk_filter_field_type_e +{ + FILTER_FIELD_DMAC = 0, + FILTER_FIELD_SMAC, + FILTER_FIELD_ETHERTYPE, + FILTER_FIELD_CTAG, + FILTER_FIELD_STAG, + + FILTER_FIELD_IPV4_SIP, + FILTER_FIELD_IPV4_DIP, + FILTER_FIELD_IPV4_TOS, + FILTER_FIELD_IPV4_PROTOCOL, + FILTER_FIELD_IPV4_FLAG, + FILTER_FIELD_IPV4_OFFSET, + FILTER_FIELD_IPV6_SIPV6, + FILTER_FIELD_IPV6_DIPV6, + FILTER_FIELD_IPV6_TRAFFIC_CLASS, + FILTER_FIELD_IPV6_NEXT_HEADER, + + FILTER_FIELD_TCP_SPORT, + FILTER_FIELD_TCP_DPORT, + FILTER_FIELD_TCP_FLAG, + FILTER_FIELD_UDP_SPORT, + FILTER_FIELD_UDP_DPORT, + FILTER_FIELD_ICMP_CODE, + FILTER_FIELD_ICMP_TYPE, + FILTER_FIELD_IGMP_TYPE, + + FILTER_FIELD_VID_RANGE, + FILTER_FIELD_IP_RANGE, + FILTER_FIELD_PORT_RANGE, + + FILTER_FIELD_USER_DEFINED00, + FILTER_FIELD_USER_DEFINED01, + FILTER_FIELD_USER_DEFINED02, + FILTER_FIELD_USER_DEFINED03, + FILTER_FIELD_USER_DEFINED04, + FILTER_FIELD_USER_DEFINED05, + FILTER_FIELD_USER_DEFINED06, + FILTER_FIELD_USER_DEFINED07, + FILTER_FIELD_USER_DEFINED08, + FILTER_FIELD_USER_DEFINED09, + FILTER_FIELD_USER_DEFINED10, + FILTER_FIELD_USER_DEFINED11, + FILTER_FIELD_USER_DEFINED12, + FILTER_FIELD_USER_DEFINED13, + FILTER_FIELD_USER_DEFINED14, + FILTER_FIELD_USER_DEFINED15, + + FILTER_FIELD_PATTERN_MATCH, + + FILTER_FIELD_END, +} rtk_filter_field_type_t; + + +typedef enum rtk_filter_field_type_raw_e +{ + FILTER_FIELD_RAW_UNUSED = 0, + FILTER_FIELD_RAW_DMAC_15_0, + FILTER_FIELD_RAW_DMAC_31_16, + FILTER_FIELD_RAW_DMAC_47_32, + FILTER_FIELD_RAW_SMAC_15_0, + FILTER_FIELD_RAW_SMAC_31_16, + FILTER_FIELD_RAW_SMAC_47_32, + FILTER_FIELD_RAW_ETHERTYPE, + FILTER_FIELD_RAW_STAG, + FILTER_FIELD_RAW_CTAG, + + FILTER_FIELD_RAW_IPV4_SIP_15_0 = 0x10, + FILTER_FIELD_RAW_IPV4_SIP_31_16, + FILTER_FIELD_RAW_IPV4_DIP_15_0, + FILTER_FIELD_RAW_IPV4_DIP_31_16, + + + FILTER_FIELD_RAW_IPV6_SIP_15_0 = 0x20, + FILTER_FIELD_RAW_IPV6_SIP_31_16, + FILTER_FIELD_RAW_IPV6_DIP_15_0 = 0x28, + FILTER_FIELD_RAW_IPV6_DIP_31_16, + + FILTER_FIELD_RAW_L4_DPORT = 0x2A, + FILTER_FIELD_RAW_L4_SPORT, + + FILTER_FIELD_RAW_VIDRANGE = 0x30, + FILTER_FIELD_RAW_IPRANGE, + FILTER_FIELD_RAW_PORTRANGE, + FILTER_FIELD_RAW_FIELD_VALID, + + FILTER_FIELD_RAW_FIELD_SELECT00 = 0x40, + FILTER_FIELD_RAW_FIELD_SELECT01, + FILTER_FIELD_RAW_FIELD_SELECT02, + FILTER_FIELD_RAW_FIELD_SELECT03, + FILTER_FIELD_RAW_FIELD_SELECT04, + FILTER_FIELD_RAW_FIELD_SELECT05, + FILTER_FIELD_RAW_FIELD_SELECT06, + FILTER_FIELD_RAW_FIELD_SELECT07, + FILTER_FIELD_RAW_FIELD_SELECT08, + FILTER_FIELD_RAW_FIELD_SELECT09, + FILTER_FIELD_RAW_FIELD_SELECT10, + FILTER_FIELD_RAW_FIELD_SELECT11, + FILTER_FIELD_RAW_FIELD_SELECT12, + FILTER_FIELD_RAW_FIELD_SELECT13, + FILTER_FIELD_RAW_FIELD_SELECT14, + FILTER_FIELD_RAW_FIELD_SELECT15, + + FILTER_FIELD_RAW_END, +} rtk_filter_field_type_raw_t; + +typedef enum rtk_filter_flag_care_type_e +{ + FILTER_FLAG_CARE_DONT_CARE = 0, + FILTER_FLAG_CARE_1, + FILTER_FLAG_CARE_0, + FILTER_FLAG_END +} rtk_filter_flag_care_type_t; + +typedef rtk_uint32 rtk_filter_id_t; /* filter id type */ + +typedef enum rtk_filter_invert_e +{ + FILTER_INVERT_DISABLE = 0, + FILTER_INVERT_ENABLE, + FILTER_INVERT_END, +} rtk_filter_invert_t; + +typedef rtk_uint32 rtk_filter_state_t; + +typedef rtk_uint32 rtk_filter_unmatch_action_t; + +typedef enum rtk_filter_unmatch_action_e +{ + FILTER_UNMATCH_DROP = 0, + FILTER_UNMATCH_PERMIT, + FILTER_UNMATCH_END, +} rtk_filter_unmatch_action_type_t; + +typedef struct +{ + rtk_filter_field_t *fieldHead; + rtk_filter_care_tag_t careTag; + rtk_filter_activeport_t activeport; + + rtk_filter_invert_t invert; +} rtk_filter_cfg_t; + +typedef struct +{ + rtk_filter_field_raw_t dataFieldRaw[RTK_FILTER_RAW_FIELD_NUMBER]; + rtk_filter_field_raw_t careFieldRaw[RTK_FILTER_RAW_FIELD_NUMBER]; + rtk_filter_field_type_raw_t fieldRawType[RTK_FILTER_RAW_FIELD_NUMBER]; + rtk_filter_care_tag_t careTag; + rtk_filter_activeport_t activeport; + + rtk_filter_invert_t invert; + rtk_enable_t valid; +} rtk_filter_cfg_raw_t; + +typedef struct +{ + rtk_uint32 index; + rtk_filter_field_type_raw_t fieldType[RTK_FILTER_RAW_FIELD_NUMBER]; +} rtk_filter_template_t; + +typedef enum rtk_field_sel_e +{ + FORMAT_DEFAULT = 0, + FORMAT_RAW, + FORMAT_LLC, + FORMAT_IPV4, + FORMAT_ARP, + FORMAT_IPV6, + FORMAT_IPPAYLOAD, + FORMAT_L4PAYLOAD, + FORMAT_END +}rtk_field_sel_t; + +typedef enum rtk_filter_iprange_e +{ + IPRANGE_UNUSED = 0, + IPRANGE_IPV4_SIP, + IPRANGE_IPV4_DIP, + IPRANGE_IPV6_SIP, + IPRANGE_IPV6_DIP, + IPRANGE_END +}rtk_filter_iprange_t; + +typedef enum rtk_filter_vidrange_e +{ + VIDRANGE_UNUSED = 0, + VIDRANGE_CVID, + VIDRANGE_SVID, + VIDRANGE_END +}rtk_filter_vidrange_t; + +typedef enum rtk_filter_portrange_e +{ + PORTRANGE_UNUSED = 0, + PORTRANGE_SPORT, + PORTRANGE_DPORT, + PORTRANGE_END +}rtk_filter_portrange_t; + +/* Function Name: + * rtk_filter_igrAcl_init + * Description: + * ACL initialization function + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Pointer pFilter_field or pFilter_cfg point to NULL. + * Note: + * This function enable and intialize ACL function + */ +extern rtk_api_ret_t rtk_filter_igrAcl_init(void); + +/* Function Name: + * rtk_filter_igrAcl_field_add + * Description: + * Add comparison rule to an ACL configuration + * Input: + * pFilter_cfg - The ACL configuration that this function will add comparison rule + * pFilter_field - The comparison rule that will be added. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Pointer pFilter_field or pFilter_cfg point to NULL. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This function add a comparison rule (*pFilter_field) to an ACL configuration (*pFilter_cfg). + * Pointer pFilter_cfg points to an ACL configuration structure, this structure keeps multiple ACL + * comparison rules by means of linked list. Pointer pFilter_field will be added to linked + * list keeped by structure that pFilter_cfg points to. + */ +extern rtk_api_ret_t rtk_filter_igrAcl_field_add(rtk_filter_cfg_t *pFilter_cfg, rtk_filter_field_t *pFilter_field); + +/* Function Name: + * rtk_filter_igrAcl_cfg_add + * Description: + * Add an ACL configuration to ASIC + * Input: + * filter_id - Start index of ACL configuration. + * pFilter_cfg - The ACL configuration that this function will add comparison rule + * pFilter_action - Action(s) of ACL configuration. + * Output: + * ruleNum - number of rules written in acl table + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Pointer pFilter_field or pFilter_cfg point to NULL. + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_ENTRY_INDEX - Invalid filter_id . + * RT_ERR_NULL_POINTER - Pointer pFilter_action or pFilter_cfg point to NULL. + * RT_ERR_FILTER_INACL_ACT_NOT_SUPPORT - Action is not supported in this chip. + * RT_ERR_FILTER_INACL_RULE_NOT_SUPPORT - Rule is not supported. + * Note: + * This function store pFilter_cfg, pFilter_action into ASIC. The starting + * index(es) is filter_id. + */ +extern rtk_api_ret_t rtk_filter_igrAcl_cfg_add(rtk_filter_id_t filter_id, rtk_filter_cfg_t *pFilter_cfg, rtk_filter_action_t *pAction, rtk_filter_number_t *ruleNum); + +/* Function Name: + * rtk_filter_igrAcl_cfg_del + * Description: + * Delete an ACL configuration from ASIC + * Input: + * filter_id - Start index of ACL configuration. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_ENTRYIDX - Invalid filter_id. + * Note: + * This function delete a group of ACL rules starting from filter_id. + */ +extern rtk_api_ret_t rtk_filter_igrAcl_cfg_del(rtk_filter_id_t filter_id); + +/* Function Name: + * rtk_filter_igrAcl_cfg_delAll + * Description: + * Delete all ACL entries from ASIC + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This function delete all ACL configuration from ASIC. + */ +extern rtk_api_ret_t rtk_filter_igrAcl_cfg_delAll(void); + +/* Function Name: + * rtk_filter_igrAcl_cfg_get + * Description: + * Get one ingress acl configuration from ASIC. + * Input: + * filter_id - Start index of ACL configuration. + * Output: + * pFilter_cfg - buffer pointer of ingress acl data + * pFilter_action - buffer pointer of ingress acl action + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Pointer pFilter_action or pFilter_cfg point to NULL. + * RT_ERR_FILTER_ENTRYIDX - Invalid entry index. + * Note: + * This function delete all ACL configuration from ASIC. + */ +extern rtk_api_ret_t rtk_filter_igrAcl_cfg_get(rtk_filter_id_t filter_id, rtk_filter_cfg_raw_t *pFilter_cfg, rtk_filter_action_t *pAction); + +/* Function Name: + * rtk_filter_igrAcl_unmatchAction_set + * Description: + * Set action to packets when no ACL configuration match + * Input: + * port - Port id. + * action - Action. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port id. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This function sets action of packets when no ACL configruation matches. + */ +extern rtk_api_ret_t rtk_filter_igrAcl_unmatchAction_set(rtk_port_t port, rtk_filter_unmatch_action_t action); + +/* Function Name: + * rtk_filter_igrAcl_unmatchAction_get + * Description: + * Get action to packets when no ACL configuration match + * Input: + * port - Port id. + * Output: + * pAction - Action. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port id. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This function gets action of packets when no ACL configruation matches. + */ +extern rtk_api_ret_t rtk_filter_igrAcl_unmatchAction_get(rtk_port_t port, rtk_filter_unmatch_action_t* action); + +/* Function Name: + * rtk_filter_igrAcl_state_set + * Description: + * Set state of ingress ACL. + * Input: + * port - Port id. + * state - Ingress ACL state. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port id. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This function gets action of packets when no ACL configruation matches. + */ +extern rtk_api_ret_t rtk_filter_igrAcl_state_set(rtk_port_t port, rtk_filter_state_t state); + +/* Function Name: + * rtk_filter_igrAcl_state_get + * Description: + * Get state of ingress ACL. + * Input: + * port - Port id. + * Output: + * pState - Ingress ACL state. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port id. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This function gets action of packets when no ACL configruation matches. + */ +extern rtk_api_ret_t rtk_filter_igrAcl_state_get(rtk_port_t port, rtk_filter_state_t* state); + +/* Function Name: + * rtk_filter_igrAcl_template_set + * Description: + * Set template of ingress ACL. + * Input: + * template - Ingress ACL template + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This function set ACL template. + */ +extern rtk_api_ret_t rtk_filter_igrAcl_template_set(rtk_filter_template_t *aclTemplate); + +/* Function Name: + * rtk_filter_igrAcl_template_get + * Description: + * Get template of ingress ACL. + * Input: + * template - Ingress ACL template + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This function gets template of ACL. + */ +extern rtk_api_ret_t rtk_filter_igrAcl_template_get(rtk_filter_template_t *aclTemplate); + +/* Function Name: + * rtk_filter_igrAcl_field_sel_set + * Description: + * Set user defined field selectors in HSB + * Input: + * index - index of field selector 0-15 + * format - Format of field selector + * offset - Retrieving data offset + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * System support 16 user defined field selctors. + * Each selector can be enabled or disable. + * User can defined retrieving 16-bits in many predefiend + * standard l2/l3/l4 payload. + */ +extern rtk_api_ret_t rtk_filter_igrAcl_field_sel_set(rtk_uint32 index, rtk_field_sel_t format, rtk_uint32 offset); + +/* Function Name: + * rtk_filter_igrAcl_field_sel_get + * Description: + * Get user defined field selectors in HSB + * Input: + * index - index of field selector 0-15 + * Output: + * pFormat - Format of field selector + * pOffset - Retrieving data offset + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * None. + */ +extern rtk_api_ret_t rtk_filter_igrAcl_field_sel_get(rtk_uint32 index, rtk_field_sel_t *pFormat, rtk_uint32 *pOffset); + +/* Function Name: + * rtk_filter_iprange_set + * Description: + * Set IP Range check + * Input: + * index - index of IP Range 0-15 + * type - IP Range check type, 0:Delete a entry, 1: IPv4_SIP, 2: IPv4_DIP, 3:IPv6_SIP, 4:IPv6_DIP + * upperIp - The upper bound of IP range + * lowerIp - The lower Bound of IP range + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - The parameter is out of range + * RT_ERR_INPUT - Input error + * Note: + * upperIp must be larger or equal than lowerIp. + */ +extern rtk_api_ret_t rtk_filter_iprange_set(rtk_uint32 index, rtk_filter_iprange_t type, ipaddr_t upperIp, ipaddr_t lowerIp); + +/* Function Name: + * rtk_filter_iprange_get + * Description: + * Set IP Range check + * Input: + * index - index of IP Range 0-15 + * Output: + * pType - IP Range check type, 0:Delete a entry, 1: IPv4_SIP, 2: IPv4_DIP, 3:IPv6_SIP, 4:IPv6_DIP + * pUpperIp - The upper bound of IP range + * pLowerIp - The lower Bound of IP range + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - The parameter is out of range + * Note: + * upperIp must be larger or equal than lowerIp. + */ +extern rtk_api_ret_t rtk_filter_iprange_get(rtk_uint32 index, rtk_filter_iprange_t *pType, ipaddr_t *pUpperIp, ipaddr_t *pLowerIp); + +/* Function Name: + * rtk_filter_vidrange_set + * Description: + * Set VID Range check + * Input: + * index - index of VID Range 0-15 + * type - IP Range check type, 0:Delete a entry, 1: CVID, 2: SVID + * upperVid - The upper bound of VID range + * lowerVid - The lower Bound of VID range + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - The parameter is out of range + * RT_ERR_INPUT - Input error + * Note: + * upperVid must be larger or equal than lowerVid. + */ +extern rtk_api_ret_t rtk_filter_vidrange_set(rtk_uint32 index, rtk_filter_vidrange_t type, rtk_uint32 upperVid, rtk_uint32 lowerVid); + +/* Function Name: + * rtk_filter_vidrange_get + * Description: + * Get VID Range check + * Input: + * index - index of VID Range 0-15 + * Output: + * pType - IP Range check type, 0:Unused, 1: CVID, 2: SVID + * pUpperVid - The upper bound of VID range + * pLowerVid - The lower Bound of VID range + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - The parameter is out of range + * Note: + * None. + */ +extern rtk_api_ret_t rtk_filter_vidrange_get(rtk_uint32 index, rtk_filter_vidrange_t *pType, rtk_uint32 *pUpperVid, rtk_uint32 *pLowerVid); + +/* Function Name: + * rtk_filter_portrange_set + * Description: + * Set Port Range check + * Input: + * index - index of Port Range 0-15 + * type - IP Range check type, 0:Delete a entry, 1: Source Port, 2: Destnation Port + * upperPort - The upper bound of Port range + * lowerPort - The lower Bound of Port range + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - The parameter is out of range + * RT_ERR_INPUT - Input error + * Note: + * upperPort must be larger or equal than lowerPort. + */ +extern rtk_api_ret_t rtk_filter_portrange_set(rtk_uint32 index, rtk_filter_portrange_t type, rtk_uint32 upperPort, rtk_uint32 lowerPort); + +/* Function Name: + * rtk_filter_portrange_get + * Description: + * Set Port Range check + * Input: + * index - index of Port Range 0-15 + * Output: + * pType - IP Range check type, 0:Delete a entry, 1: Source Port, 2: Destnation Port + * pUpperPort - The upper bound of Port range + * pLowerPort - The lower Bound of Port range + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - The parameter is out of range + * RT_ERR_INPUT - Input error + * Note: + * None. + */ +extern rtk_api_ret_t rtk_filter_portrange_get(rtk_uint32 index, rtk_filter_portrange_t *pType, rtk_uint32 *pUpperPort, rtk_uint32 *pLowerPort); + +/* Function Name: + * rtk_filter_igrAclPolarity_set + * Description: + * Set ACL Goip control palarity + * Input: + * polarity - 1: High, 0: Low + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * none + */ +extern rtk_api_ret_t rtk_filter_igrAclPolarity_set(rtk_uint32 polarity); + +/* Function Name: + * rtk_filter_igrAclPolarity_get + * Description: + * Get ACL Goip control palarity + * Input: + * pPolarity - 1: High, 0: Low + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * none + */ +extern rtk_api_ret_t rtk_filter_igrAclPolarity_get(rtk_uint32* pPolarity); + + +#endif /* __RTK_API_ACL_H__ */ diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/chip.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/chip.c new file mode 100644 index 00000000..cf06c0ee --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/chip.c @@ -0,0 +1,571 @@ +/* + * Copyright (C) 2018 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * Purpose : chip symbol and data type definition in the SDK. + * + * Feature : chip symbol and data type definition + * + */ + +#if (!defined(CONFIG_DAL_RTL8367C) && !defined(CONFIG_DAL_RTL8367D)) +#define CONFIG_DAL_ALL +#endif + +#include +#include +#if defined(CONFIG_DAL_RTL8367C) || defined(CONFIG_DAL_ALL) +#include +#endif +#if defined(CONFIG_DAL_RTL8367D) || defined(CONFIG_DAL_ALL) +#include +#endif +#include + +//#define FORCE_PROBE_RTL8367C +#define FORCE_PROBE_RTL8367D + +#if (!defined(FORCE_PROBE_RTL8367C) && !defined(FORCE_PROBE_RTL8370B) && !defined(FORCE_PROBE_RTL8364B) && !defined(FORCE_PROBE_RTL8363SC_VB) && !defined(FORCE_PROBE_RTL8367D)) +#define AUTO_PROBE 1 +#else +#define AUTO_PROBE 0 +#endif + +#if (AUTO_PROBE || defined(FORCE_PROBE_RTL8367C)) +static rtk_switch_halCtrl_t rtl8367c_hal_Ctrl = +{ + /* Switch Chip */ + CHIP_RTL8367C, + + /* Logical to Physical */ + {0, 1, 2, 3, 4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 6, 7, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, + + /* Physical to Logical */ + {UTP_PORT0, UTP_PORT1, UTP_PORT2, UTP_PORT3, UTP_PORT4, UNDEFINE_PORT, EXT_PORT0, EXT_PORT1, + UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, + UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, + UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT}, + + /* Port Type */ + {UTP_PORT, UTP_PORT, UTP_PORT, UTP_PORT, UTP_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, + UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, + EXT_PORT, EXT_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, + UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT}, + + /* PTP port */ + {1, 1, 1, 1, 1, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }, + + /* Valid port mask */ + ( (0x1 << UTP_PORT0) | (0x1 << UTP_PORT1) | (0x1 << UTP_PORT2) | (0x1 << UTP_PORT3) | (0x1 << UTP_PORT4) | (0x1 << EXT_PORT0) | (0x1 << EXT_PORT1) ), + + /* Valid UTP port mask */ + ( (0x1 << UTP_PORT0) | (0x1 << UTP_PORT1) | (0x1 << UTP_PORT2) | (0x1 << UTP_PORT3) | (0x1 << UTP_PORT4) ), + + /* Valid EXT port mask */ + ( (0x1 << EXT_PORT0) | (0x1 << EXT_PORT1) ), + + /* Valid CPU port mask */ + 0x00, + + /* Minimum physical port number */ + 0, + + /* Maxmum physical port number */ + 7, + + /* Physical port mask */ + 0xDF, + + /* Combo Logical port ID */ + 4, + + /* HSG Logical portmask */ + (0x1 << EXT_PORT0), + + /* SGMII Logical portmask */ + (0x1 << EXT_PORT0), + + /* Max Meter ID */ + 31, + + /* MAX LUT Address Number */ + 2112, + + /* Trunk Group Mask */ + 0x03, + + /* Packet buffer page number */ + 1024 +}; +#endif + +#if (AUTO_PROBE || defined(FORCE_PROBE_RTL8370B)) +static rtk_switch_halCtrl_t rtl8370b_hal_Ctrl = +{ + /* Switch Chip */ + CHIP_RTL8370B, + + /* Logical to Physical */ + {0, 1, 2, 3, 4, 5, 6, 7, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 8, 9, 10, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, + + /* Physical to Logical */ + {UTP_PORT0, UTP_PORT1, UTP_PORT2, UTP_PORT3, UTP_PORT4, UTP_PORT5, UTP_PORT6, UTP_PORT7, + EXT_PORT0, EXT_PORT1, EXT_PORT2, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, + UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, + UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT}, + + /* Port Type */ + {UTP_PORT, UTP_PORT, UTP_PORT, UTP_PORT, UTP_PORT, UTP_PORT, UTP_PORT, UTP_PORT, + UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, + EXT_PORT, EXT_PORT, EXT_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, + UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT}, + + /* PTP port */ + {1, 1, 1, 1, 1, 1, 1, 1, + 0, 0, 0, 0, 0, 0, 0, 0, + 1, 1, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }, + + /* Valid port mask */ + ( (0x1 << UTP_PORT0) | (0x1 << UTP_PORT1) | (0x1 << UTP_PORT2) | (0x1 << UTP_PORT3) | (0x1 << UTP_PORT4) | (0x1 << UTP_PORT5) | (0x1 << UTP_PORT6) | (0x1 << UTP_PORT7) | (0x1 << EXT_PORT0) | (0x1 << EXT_PORT1) | (0x1 << EXT_PORT2) ), + + /* Valid UTP port mask */ + ( (0x1 << UTP_PORT0) | (0x1 << UTP_PORT1) | (0x1 << UTP_PORT2) | (0x1 << UTP_PORT3) | (0x1 << UTP_PORT4) | (0x1 << UTP_PORT5) | (0x1 << UTP_PORT6) | (0x1 << UTP_PORT7) ), + + /* Valid EXT port mask */ + ( (0x1 << EXT_PORT0) | (0x1 << EXT_PORT1) | (0x1 << EXT_PORT2) ), + + /* Valid CPU port mask */ + (0x1 << EXT_PORT2), + + /* Minimum physical port number */ + 0, + + /* Maxmum physical port number */ + 10, + + /* Physical port mask */ + 0x7FF, + + /* Combo Logical port ID */ + 7, + + /* HSG Logical portmask */ + (0x1 << EXT_PORT1), + + /* SGMII Logical portmask */ + ( (0x1 << EXT_PORT0) | (0x1 << EXT_PORT1) ), + + /* Max Meter ID */ + 63, + + /* MAX LUT Address Number 4096 + 64*/ + 4160, + + /* Trunk Group Mask */ + 0x07, + + /* Packet buffer page number */ + 1536 +}; +#endif + +#if (AUTO_PROBE || defined(FORCE_PROBE_RTL8364B)) +static rtk_switch_halCtrl_t rtl8364b_hal_Ctrl = +{ + /* Switch Chip */ + CHIP_RTL8364B, + + /* Logical to Physical */ + {0xFF, 1, 0xFF, 3, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 6, 7, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, + + /* Physical to Logical */ + {UNDEFINE_PORT, UTP_PORT1, UNDEFINE_PORT, UTP_PORT3, UNDEFINE_PORT, UNDEFINE_PORT, EXT_PORT0, EXT_PORT1, + UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, + UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, + UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT}, + + /* Port Type */ + {UNKNOWN_PORT, UTP_PORT, UNKNOWN_PORT, UTP_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, + UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, + EXT_PORT, EXT_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, + UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT}, + + /* PTP port */ + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }, + + /* Valid port mask */ + ( (0x1 << UTP_PORT1) | (0x1 << UTP_PORT3) | (0x1 << EXT_PORT0) | (0x1 << EXT_PORT1) ), + + /* Valid UTP port mask */ + ( (0x1 << UTP_PORT1) | (0x1 << UTP_PORT3) ), + + /* Valid EXT port mask */ + ( (0x1 << EXT_PORT0) | (0x1 << EXT_PORT1) ), + + /* Valid CPU port mask */ + 0x00, + + /* Minimum physical port number */ + 0, + + /* Maxmum physical port number */ + 7, + + /* Physical port mask */ + 0xCA, + + /* Combo Logical port ID */ + 4, + + /* HSG Logical portmask */ + (0x1 << EXT_PORT0), + + /* SGMII Logical portmask */ + ( (0x1 << EXT_PORT0) | (0x1 << EXT_PORT1) ), + + /* Max Meter ID */ + 32, + + /* MAX LUT Address Number */ + 2112, + + /* Trunk Group Mask */ + 0x01, + + /* Packet buffer page number */ + 512 +}; +#endif + +#if (AUTO_PROBE || defined(FORCE_PROBE_RTL8363SC_VB)) +static rtk_switch_halCtrl_t rtl8363sc_vb_hal_Ctrl = +{ + /* Switch Chip */ + CHIP_RTL8363SC_VB, + + /* Logical to Physical */ + {0xFF, 0xFF, 1, 3, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 6, 7, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, + + /* Physical to Logical */ + {UNDEFINE_PORT, UTP_PORT2, UNDEFINE_PORT, UTP_PORT3, UNDEFINE_PORT, UNDEFINE_PORT, EXT_PORT0, EXT_PORT1, + UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, + UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, + UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT}, + + /* Port Type */ + {UNKNOWN_PORT, UNKNOWN_PORT, UTP_PORT, UTP_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, + UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, + EXT_PORT, EXT_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, + UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT}, + + /* PTP port */ + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }, + + /* Valid port mask */ + ( (0x1 << UTP_PORT2) | (0x1 << UTP_PORT3) | (0x1 << EXT_PORT0) | (0x1 << EXT_PORT1) ), + + /* Valid UTP port mask */ + ( (0x1 << UTP_PORT2) | (0x1 << UTP_PORT3) ), + + /* Valid EXT port mask */ + ( (0x1 << EXT_PORT0) | (0x1 << EXT_PORT1) ), + + /* Valid CPU port mask */ + 0x00, + + /* Minimum physical port number */ + 0, + + /* Maxmum physical port number */ + 7, + + /* Physical port mask */ + 0xCA, + + /* Combo Logical port ID */ + 4, + + /* HSG Logical portmask */ + (0x1 << EXT_PORT0), + + /* SGMII Logical portmask */ + ( (0x1 << EXT_PORT0) | (0x1 << EXT_PORT1) ), + + /* Max Meter ID */ + 32, + + /* MAX LUT Address Number */ + 2112, + + /* Trunk Group Mask */ + 0x01, + + /* Packet buffer page number */ + 512 +}; +#endif + +#if (AUTO_PROBE || defined(FORCE_PROBE_RTL8367D)) +static rtk_switch_halCtrl_t rtl8367d_hal_Ctrl = +{ + /* Switch Chip */ + CHIP_RTL8367D, + + /* Logical to Physical */ + {0, 1, 2, 3, 4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 6, 7, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, + + /* Physical to Logical */ + {UTP_PORT0, UTP_PORT1, UTP_PORT2, UTP_PORT3, UTP_PORT4, UNDEFINE_PORT, EXT_PORT0, EXT_PORT1, + UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, + UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, + UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT}, + + /* Port Type */ + {UTP_PORT, UTP_PORT, UTP_PORT, UTP_PORT, UTP_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, + UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, + EXT_PORT, EXT_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, + UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT}, + + /* PTP port */ + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }, + + /* Valid port mask */ + ( (0x1 << UTP_PORT0) | (0x1 << UTP_PORT1) | (0x1 << UTP_PORT2) | (0x1 << UTP_PORT3) | (0x1 << UTP_PORT4) | (0x1 << EXT_PORT0) | (0x1 << EXT_PORT1) ), + + /* Valid UTP port mask */ + ( (0x1 << UTP_PORT0) | (0x1 << UTP_PORT1) | (0x1 << UTP_PORT2) | (0x1 << UTP_PORT3) | (0x1 << UTP_PORT4) ), + + /* Valid EXT port mask */ + ( (0x1 << EXT_PORT0) | (0x1 << EXT_PORT1) ), + + /* Valid CPU port mask */ + 0x00, + + /* Minimum physical port number */ + 0, + + /* Maxmum physical port number */ + 7, + + /* Physical port mask */ + 0xFF, + + /* Combo Logical port ID */ + 4, + + /* HSG Logical portmask */ + ((0x1 << EXT_PORT0) | (0x1 << EXT_PORT1)), + + /* SGMII Logical portmask */ + ((0x1 << EXT_PORT0) | (0x1 << EXT_PORT1)), + + /* Max Meter ID */ + 39, + + /* MAX LUT Address Number */ + 2056, + + /* Trunk Group Mask */ + 0x03, + + /* Packet buffer page number */ + 2048 +}; +#endif + +/* Function Name: + * switch_probe + * Description: + * Probe switch + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - Switch probed + * RT_ERR_FAILED - Switch Unprobed. + * Note: + * + */ +rtk_api_ret_t switch_probe(switch_chip_t *pSwitchChip) +{ +#if defined(FORCE_PROBE_RTL8367C) + + *pSwitchChip = CHIP_RTL8367C; + return RT_ERR_OK; + +#elif defined(FORCE_PROBE_RTL8370B) + + *pSwitchChip = CHIP_RTL8370B; + return RT_ERR_OK; + +#elif defined(FORCE_PROBE_RTL8364B) + + *pSwitchChip = CHIP_RTL8364B; + return RT_ERR_OK; + +#elif defined(FORCE_PROBE_RTL8363SC_VB) + + *pSwitchChip = CHIP_RTL8363SC_VB; + return RT_ERR_OK; + +#elif defined(FORCE_PROBE_RTL8367D) + + *pSwitchChip = CHIP_RTL8367D; + return RT_ERR_OK; + +#else + rtk_uint32 retVal; + rtk_uint32 data; + rtk_uint32 regValue; + +#if defined(CONFIG_DAL_RTL8367C) || defined(CONFIG_DAL_ALL) + + if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0249)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_getAsicReg(0x1300, &data)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_getAsicReg(0x1301, ®Value)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0000)) != RT_ERR_OK) + return retVal; + + switch (data) + { + case 0x0276: + case 0x0597: + case 0x6367: + *pSwitchChip = CHIP_RTL8367C; + return RT_ERR_OK; + case 0x0652: + case 0x6368: + *pSwitchChip = CHIP_RTL8370B; + return RT_ERR_OK; + case 0x0801: + case 0x6511: + if( (regValue & 0x00F0) == 0x0080) + { + *pSwitchChip = CHIP_RTL8363SC_VB; + return RT_ERR_OK; + } + else + { + *pSwitchChip = CHIP_RTL8364B; + return RT_ERR_OK; + } + default: + break; + } +#endif + +#if defined(CONFIG_DAL_RTL8367D) || defined(CONFIG_DAL_ALL) + + if((retVal = rtl8367d_setAsicReg(0x13C2, 0x0249)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367d_getAsicReg(0x1300, &data)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367d_getAsicReg(0x1301, ®Value)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367d_setAsicReg(0x13C2, 0x0000)) != RT_ERR_OK) + return retVal; + + switch (data) + { + case 0x6642: + *pSwitchChip = CHIP_RTL8367D; + return RT_ERR_OK; + default: + break; + } +#endif +#endif + + return RT_ERR_CHIP_NOT_FOUND; +} + +/* Function Name: + * hal_find_device + * Description: + * Find the mac chip from SDK supported mac device lists. + * Input: + * None + * Output: + * None + * Return: + * NULL - Not found + * Otherwise - Pointer of mac chip HAL structure that found + * Note: + * + */ + +extern switch_chip_t g_switch_chip; +rtk_switch_halCtrl_t *hal_find_device(void) +{ + switch_chip_t switchChip; + rtk_uint32 retVal; + + /* probe switch */ + if((retVal = switch_probe(&switchChip)) != RT_ERR_OK) + return NULL; + + g_switch_chip = switchChip; + + switch (switchChip) + { +#if (AUTO_PROBE || defined(FORCE_PROBE_RTL8367C)) + case CHIP_RTL8367C: + return &rtl8367c_hal_Ctrl; +#endif +#if (AUTO_PROBE || defined(FORCE_PROBE_RTL8370B)) + case CHIP_RTL8370B: + return &rtl8370b_hal_Ctrl; +#endif +#if (AUTO_PROBE || defined(FORCE_PROBE_RTL8364B)) + case CHIP_RTL8364B: + return &rtl8364b_hal_Ctrl; +#endif +#if (AUTO_PROBE || defined(FORCE_PROBE_RTL8363SC_VB)) + case CHIP_RTL8363SC_VB: + return &rtl8363sc_vb_hal_Ctrl; +#endif +#if (AUTO_PROBE || defined(FORCE_PROBE_RTL8367D)) + case CHIP_RTL8367D: + return &rtl8367d_hal_Ctrl; +#endif + default: + return NULL; + } + + /* Not found */ + return NULL; +} diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/chip.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/chip.h new file mode 100644 index 00000000..06458ed9 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/chip.h @@ -0,0 +1,103 @@ +/* + * Copyright(c) Realtek Semiconductor Corporation, 2008 + * All rights reserved. + * + * $Revision$ + * $Date$ + * + * Purpose : Definition function prototype of RTK switch API. + * + * Feature : Function prototype definition + * + */ + +#ifndef __CHIP_H__ +#define __CHIP_H__ + + +#include + +#define UNDEFINE_PHY_PORT (0xFF) +#define RTK_SWITCH_PORT_NUM (32) + +typedef enum switch_chip_e +{ + CHIP_RTL8367C = 0, + CHIP_RTL8370B, + CHIP_RTL8364B, + CHIP_RTL8363SC_VB, + CHIP_RTL8367D, + CHIP_END +}switch_chip_t; + +typedef enum port_type_e +{ + UTP_PORT = 0, + EXT_PORT, + UNKNOWN_PORT = 0xFF, + PORT_TYPE_END +}port_type_t; + +typedef struct rtk_switch_halCtrl_s +{ + switch_chip_t switch_type; + rtk_uint32 l2p_port[RTK_SWITCH_PORT_NUM]; + rtk_uint32 p2l_port[RTK_SWITCH_PORT_NUM]; + port_type_t log_port_type[RTK_SWITCH_PORT_NUM]; + rtk_uint32 ptp_port[RTK_SWITCH_PORT_NUM]; + rtk_uint32 valid_portmask; + rtk_uint32 valid_utp_portmask; + rtk_uint32 valid_ext_portmask; + rtk_uint32 valid_cpu_portmask; + rtk_uint32 min_phy_port; + rtk_uint32 max_phy_port; + rtk_uint32 phy_portmask; + rtk_uint32 combo_logical_port; + rtk_uint32 hsg_logical_portmask; + rtk_uint32 sg_logical_portmask; + rtk_uint32 max_meter_id; + rtk_uint32 max_lut_addr_num; + rtk_uint32 trunk_group_mask; + rtk_uint32 packet_buffer_page_num; + +}rtk_switch_halCtrl_t; + +/* Function Name: + * switch_probe + * Description: + * Probe switch + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - Switch probed + * RT_ERR_FAILED - Switch Unprobed. + * Note: + * + */ +extern rtk_api_ret_t switch_probe(switch_chip_t *pSwitchChip); + +/* Function Name: + * hal_find_device + * Description: + * Find the mac chip from SDK supported mac device lists. + * Input: + * None + * Output: + * None + * Return: + * NULL - Not found + * Otherwise - Pointer of mac chip HAL structure that found + * Note: + * + */ + +extern rtk_switch_halCtrl_t *hal_find_device(void); + +/* + * chip type + */ +extern switch_chip_t g_switch_chip; + +#endif /* End of __CHIP_H__ */ diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/cpu.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/cpu.c new file mode 100644 index 00000000..eb29d1bc --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/cpu.c @@ -0,0 +1,466 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8367C + * Feature : Here is a list of all functions and variables in CPU module. + * + */ + +#include +#include +#include +#include + +#include + +/* Function Name: + * rtk_cpu_enable_set + * Description: + * Set CPU port function enable/disable. + * Input: + * enable - CPU port function enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can set CPU port function enable/disable. + */ +rtk_api_ret_t rtk_cpu_enable_set(rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->cpu_enable_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->cpu_enable_set(enable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_cpu_enable_get + * Description: + * Get CPU port and its setting. + * Input: + * None + * Output: + * pEnable - CPU port function enable + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_L2_NO_CPU_PORT - CPU port is not exist + * Note: + * The API can get CPU port function enable/disable. + */ +rtk_api_ret_t rtk_cpu_enable_get(rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->cpu_enable_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->cpu_enable_get(pEnable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_cpu_tagPort_set + * Description: + * Set CPU port and CPU tag insert mode. + * Input: + * port - Port id. + * mode - CPU tag insert for packets egress from CPU port. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can set CPU port and inserting proprietary CPU tag mode (Length/Type 0x8899) + * to the frame that transmitting to CPU port. + * The inset cpu tag mode is as following: + * - CPU_INSERT_TO_ALL + * - CPU_INSERT_TO_TRAPPING + * - CPU_INSERT_TO_NONE + */ +rtk_api_ret_t rtk_cpu_tagPort_set(rtk_port_t port, rtk_cpu_insert_t mode) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->cpu_tagPort_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->cpu_tagPort_set(port, mode); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_cpu_tagPort_get + * Description: + * Get CPU port and CPU tag insert mode. + * Input: + * None + * Output: + * pPort - Port id. + * pMode - CPU tag insert for packets egress from CPU port, 0:all insert 1:Only for trapped packets 2:no insert. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_L2_NO_CPU_PORT - CPU port is not exist + * Note: + * The API can get configured CPU port and its setting. + * The inset cpu tag mode is as following: + * - CPU_INSERT_TO_ALL + * - CPU_INSERT_TO_TRAPPING + * - CPU_INSERT_TO_NONE + */ +rtk_api_ret_t rtk_cpu_tagPort_get(rtk_port_t *pPort, rtk_cpu_insert_t *pMode) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->cpu_tagPort_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->cpu_tagPort_get(pPort, pMode); + RTK_API_UNLOCK(); + + return retVal; +} + + +/* Function Name: + * rtk_cpu_awarePort_set + * Description: + * Set CPU aware port mask. + * Input: + * portmask - Port mask. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Invalid port mask. + * Note: + * The API can set configured CPU aware port mask. + */ +rtk_api_ret_t rtk_cpu_awarePort_set(rtk_portmask_t *pPortmask) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->cpu_awarePort_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->cpu_awarePort_set(pPortmask); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_cpu_awarePort_get + * Description: + * Get CPU aware port mask. + * Input: + * None + * Output: + * pPortmask - Port mask. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can get configured CPU aware port mask. + */ +rtk_api_ret_t rtk_cpu_awarePort_get(rtk_portmask_t *pPortmask) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->cpu_awarePort_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->cpu_awarePort_get(pPortmask); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_cpu_tagPosition_set + * Description: + * Set CPU tag position. + * Input: + * position - CPU tag position. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input. + * Note: + * The API can set CPU tag position. + */ +rtk_api_ret_t rtk_cpu_tagPosition_set(rtk_cpu_position_t position) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->cpu_tagPosition_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->cpu_tagPosition_set(position); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_cpu_tagPosition_get + * Description: + * Get CPU tag position. + * Input: + * None + * Output: + * pPosition - CPU tag position. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input. + * Note: + * The API can get CPU tag position. + */ +rtk_api_ret_t rtk_cpu_tagPosition_get(rtk_cpu_position_t *pPosition) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->cpu_tagPosition_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->cpu_tagPosition_get(pPosition); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_cpu_tagLength_set + * Description: + * Set CPU tag length. + * Input: + * length - CPU tag length. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input. + * Note: + * The API can set CPU tag length. + */ +rtk_api_ret_t rtk_cpu_tagLength_set(rtk_cpu_tag_length_t length) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->cpu_tagLength_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->cpu_tagLength_set(length); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_cpu_tagLength_get + * Description: + * Get CPU tag length. + * Input: + * None + * Output: + * pLength - CPU tag length. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input. + * Note: + * The API can get CPU tag length. + */ +rtk_api_ret_t rtk_cpu_tagLength_get(rtk_cpu_tag_length_t *pLength) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->cpu_tagLength_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->cpu_tagLength_get(pLength); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_cpu_priRemap_set + * Description: + * Configure CPU priorities mapping to internal absolute priority. + * Input: + * int_pri - internal priority value. + * new_pri - new internal priority value. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_VLAN_PRIORITY - Invalid 1p priority. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * Priority of CPU tag assignment for internal asic priority, and it is used for queue usage and packet scheduling. + */ +rtk_api_ret_t rtk_cpu_priRemap_set(rtk_pri_t int_pri, rtk_pri_t new_pri) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->cpu_priRemap_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->cpu_priRemap_set(int_pri, new_pri); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_cpu_priRemap_get + * Description: + * Configure CPU priorities mapping to internal absolute priority. + * Input: + * int_pri - internal priority value. + * Output: + * pNew_pri - new internal priority value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_VLAN_PRIORITY - Invalid 1p priority. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * Priority of CPU tag assignment for internal asic priority, and it is used for queue usage and packet scheduling. + */ +rtk_api_ret_t rtk_cpu_priRemap_get(rtk_pri_t int_pri, rtk_pri_t *pNew_pri) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->cpu_priRemap_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->cpu_priRemap_get(int_pri, pNew_pri); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_cpu_acceptLength_set + * Description: + * Set CPU accept length. + * Input: + * length - CPU tag length. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input. + * Note: + * The API can set CPU accept length. + */ +rtk_api_ret_t rtk_cpu_acceptLength_set(rtk_cpu_rx_length_t length) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->cpu_acceptLength_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->cpu_acceptLength_set(length); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_cpu_acceptLength_get + * Description: + * Get CPU accept length. + * Input: + * None + * Output: + * pLength - CPU tag length. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input. + * Note: + * The API can get CPU accept length. + */ +rtk_api_ret_t rtk_cpu_acceptLength_get(rtk_cpu_rx_length_t *pLength) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->cpu_acceptLength_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->cpu_acceptLength_get(pLength); + RTK_API_UNLOCK(); + + return retVal; +} + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/cpu.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/cpu.h new file mode 100644 index 00000000..2d2f1666 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/cpu.h @@ -0,0 +1,330 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8367/RTL8367C switch high-level API + * + * Feature : The file includes CPU module high-layer API defination + * + */ + +#ifndef __RTK_API_CPU_H__ +#define __RTK_API_CPU_H__ + + +/* + * Data Type Declaration + */ +typedef enum rtk_cpu_insert_e +{ + CPU_INSERT_TO_ALL = 0, + CPU_INSERT_TO_TRAPPING, + CPU_INSERT_TO_NONE, + CPU_INSERT_END +}rtk_cpu_insert_t; + +typedef enum rtk_cpu_position_e +{ + CPU_POS_AFTER_SA = 0, + CPU_POS_BEFORE_CRC, + CPU_POS_END +}rtk_cpu_position_t; + +typedef enum rtk_cpu_tag_length_e +{ + CPU_LEN_8BYTES = 0, + CPU_LEN_4BYTES, + CPU_LEN_4BYTES_PRIORITY, + CPU_LEN_END +}rtk_cpu_tag_length_t; + + +typedef enum rtk_cpu_rx_length_e +{ + CPU_RX_72BYTES = 0, + CPU_RX_64BYTES, + CPU_RX_END +}rtk_cpu_rx_length_t; + + +/* Function Name: + * rtk_cpu_enable_set + * Description: + * Set CPU port function enable/disable. + * Input: + * enable - CPU port function enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can set CPU port function enable/disable. + */ +extern rtk_api_ret_t rtk_cpu_enable_set(rtk_enable_t enable); + +/* Function Name: + * rtk_cpu_enable_get + * Description: + * Get CPU port and its setting. + * Input: + * None + * Output: + * pEnable - CPU port function enable + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_L2_NO_CPU_PORT - CPU port is not exist + * Note: + * The API can get CPU port function enable/disable. + */ +extern rtk_api_ret_t rtk_cpu_enable_get(rtk_enable_t *pEnable); + +/* Function Name: + * rtk_cpu_tagPort_set + * Description: + * Set CPU port and CPU tag insert mode. + * Input: + * port - Port id. + * mode - CPU tag insert for packets egress from CPU port. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can set CPU port and inserting proprietary CPU tag mode (Length/Type 0x8899) + * to the frame that transmitting to CPU port. + * The inset cpu tag mode is as following: + * - CPU_INSERT_TO_ALL + * - CPU_INSERT_TO_TRAPPING + * - CPU_INSERT_TO_NONE + */ +extern rtk_api_ret_t rtk_cpu_tagPort_set(rtk_port_t port, rtk_cpu_insert_t mode); + +/* Function Name: + * rtk_cpu_tagPort_get + * Description: + * Get CPU port and CPU tag insert mode. + * Input: + * None + * Output: + * pPort - Port id. + * pMode - CPU tag insert for packets egress from CPU port, 0:all insert 1:Only for trapped packets 2:no insert. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_L2_NO_CPU_PORT - CPU port is not exist + * Note: + * The API can get configured CPU port and its setting. + * The inset cpu tag mode is as following: + * - CPU_INSERT_TO_ALL + * - CPU_INSERT_TO_TRAPPING + * - CPU_INSERT_TO_NONE + */ +extern rtk_api_ret_t rtk_cpu_tagPort_get(rtk_port_t *pPort, rtk_cpu_insert_t *pMode); + +/* Function Name: + * rtk_cpu_awarePort_set + * Description: + * Set CPU aware port mask. + * Input: + * portmask - Port mask. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Invalid port mask. + * Note: + * The API can set configured CPU aware port mask. + */ +extern rtk_api_ret_t rtk_cpu_awarePort_set(rtk_portmask_t *pPortmask); + + +/* Function Name: + * rtk_cpu_awarePort_get + * Description: + * Get CPU aware port mask. + * Input: + * None + * Output: + * pPortmask - Port mask. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can get configured CPU aware port mask. + */ +extern rtk_api_ret_t rtk_cpu_awarePort_get(rtk_portmask_t *pPortmask); + +/* Function Name: + * rtk_cpu_tagPosition_set + * Description: + * Set CPU tag position. + * Input: + * position - CPU tag position. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input. + * Note: + * The API can set CPU tag position. + */ +extern rtk_api_ret_t rtk_cpu_tagPosition_set(rtk_cpu_position_t position); + +/* Function Name: + * rtk_cpu_tagPosition_get + * Description: + * Get CPU tag position. + * Input: + * None + * Output: + * pPosition - CPU tag position. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input. + * Note: + * The API can get CPU tag position. + */ +extern rtk_api_ret_t rtk_cpu_tagPosition_get(rtk_cpu_position_t *pPosition); + +/* Function Name: + * rtk_cpu_tagLength_set + * Description: + * Set CPU tag length. + * Input: + * length - CPU tag length. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input. + * Note: + * The API can set CPU tag length. + */ +extern rtk_api_ret_t rtk_cpu_tagLength_set(rtk_cpu_tag_length_t length); + +/* Function Name: + * rtk_cpu_tagLength_get + * Description: + * Get CPU tag length. + * Input: + * None + * Output: + * pLength - CPU tag length. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input. + * Note: + * The API can get CPU tag length. + */ +extern rtk_api_ret_t rtk_cpu_tagLength_get(rtk_cpu_tag_length_t *pLength); + +/* Function Name: + * rtk_cpu_acceptLength_set + * Description: + * Set CPU accept length. + * Input: + * length - CPU tag length. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input. + * Note: + * The API can set CPU accept length. + */ +extern rtk_api_ret_t rtk_cpu_acceptLength_set(rtk_cpu_rx_length_t length); + +/* Function Name: + * rtk_cpu_acceptLength_get + * Description: + * Get CPU accept length. + * Input: + * None + * Output: + * pLength - CPU tag length. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input. + * Note: + * The API can get CPU accept length. + */ +extern rtk_api_ret_t rtk_cpu_acceptLength_get(rtk_cpu_rx_length_t *pLength); + +/* Function Name: + * rtk_cpu_priRemap_set + * Description: + * Configure CPU priorities mapping to internal absolute priority. + * Input: + * int_pri - internal priority value. + * new_pri - new internal priority value. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_VLAN_PRIORITY - Invalid 1p priority. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * Priority of CPU tag assignment for internal asic priority, and it is used for queue usage and packet scheduling. + */ +extern rtk_api_ret_t rtk_cpu_priRemap_set(rtk_pri_t int_pri, rtk_pri_t new_pri); + +/* Function Name: + * rtk_cpu_priRemap_get + * Description: + * Configure CPU priorities mapping to internal absolute priority. + * Input: + * int_pri - internal priority value. + * Output: + * pNew_pri - new internal priority value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_VLAN_PRIORITY - Invalid 1p priority. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * Priority of CPU tag assignment for internal asic priority, and it is used for queue usage and packet scheduling. + */ +extern rtk_api_ret_t rtk_cpu_priRemap_get(rtk_pri_t int_pri, rtk_pri_t *pNew_pri); + + +#endif /* __RTK_API_CPU_H__ */ diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/Makefile b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/Makefile new file mode 100644 index 00000000..b4bc9f85 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/Makefile @@ -0,0 +1,14 @@ +LOC_DIR=src/hsl/phy/rtl8367_common_V1_4_2/dal +LIB=HSL + +include $(PRJ_PATH)/make/config.mk + +SRC_LIST += dal_mgmt.c + +EXTRA_CFLAGS += -DMDC_MDIO_OPERATION + +include $(PRJ_PATH)/make/components.mk +include $(PRJ_PATH)/make/defs.mk +include $(PRJ_PATH)/make/target.mk + +all: dep obj diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/dal_mapper.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/dal_mapper.h new file mode 100644 index 00000000..5e79c563 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/dal_mapper.h @@ -0,0 +1,591 @@ +/* + * Copyright (C) 2011 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * Purpose : Mapper Layer is used to seperate different kind of software or hardware platform + * + * Feature : Just dispatch information to Multiplex layer + * + */ +#ifndef __DAL_MAPPER_H__ +#define __DAL_MAPPER_H__ + +/* + * Include Files + */ +#include +#include +#include +#include <../oam.h> +#include <../cpu.h> +#include <../stat.h> +#include <../l2.h> +#include <../interrupt.h> +#include <../acl.h> +#include <../mirror.h> +#include <../port.h> +#include <../trap.h> +#include <../igmp.h> +#include <../storm.h> +#include <../rate.h> +#include <../i2c.h> +#include <../ptp.h> +#include <../qos.h> +#include <../vlan.h> +#include <../dot1x.h> +#include <../svlan.h> +#include <../rldp.h> +#include <../trunk.h> +#include <../leaky.h> +#include <../gpio.h> +#include <../led.h> +/* + * Symbol Definition + */ + +/* + * Data Declaration + */ + +typedef struct dal_mapper_s { + + /* switch */ + rtk_api_ret_t (*switch_init)(void); + rtk_api_ret_t (*switch_portMaxPktLen_set)(rtk_port_t, rtk_switch_maxPktLen_linkSpeed_t, rtk_uint32); + rtk_api_ret_t (*switch_portMaxPktLen_get)(rtk_port_t, rtk_switch_maxPktLen_linkSpeed_t, rtk_uint32 *); + rtk_api_ret_t (*switch_maxPktLenCfg_set)(rtk_uint32, rtk_uint32); + rtk_api_ret_t (*switch_maxPktLenCfg_get)(rtk_uint32, rtk_uint32 *); + rtk_api_ret_t (*switch_greenEthernet_set)(rtk_enable_t); + rtk_api_ret_t (*switch_greenEthernet_get)(rtk_enable_t *); + + /* eee */ + rtk_api_ret_t (*eee_init)(void); + rtk_api_ret_t (*eee_portEnable_set)(rtk_port_t, rtk_enable_t); + rtk_api_ret_t (*eee_portEnable_get)(rtk_port_t, rtk_enable_t *); + + /* led */ + rtk_api_ret_t (*led_enable_set)(rtk_led_group_t, rtk_portmask_t *); + rtk_api_ret_t (*led_enable_get)(rtk_led_group_t, rtk_portmask_t *); + rtk_api_ret_t (*led_operation_set)(rtk_led_operation_t ); + rtk_api_ret_t (*led_operation_get)(rtk_led_operation_t *); + rtk_api_ret_t (*led_modeForce_set)(rtk_port_t, rtk_led_group_t, rtk_led_force_mode_t); + rtk_api_ret_t (*led_modeForce_get)(rtk_port_t, rtk_led_group_t, rtk_led_force_mode_t *); + rtk_api_ret_t (*led_blinkRate_set)(rtk_led_blink_rate_t); + rtk_api_ret_t (*led_blinkRate_get)(rtk_led_blink_rate_t *); + rtk_api_ret_t (*led_groupConfig_set)(rtk_led_group_t, rtk_led_congig_t); + rtk_api_ret_t (*led_groupConfig_get)(rtk_led_group_t, rtk_led_congig_t *); + rtk_api_ret_t (*led_groupAbility_set)(rtk_led_group_t, rtk_led_ability_t *); + rtk_api_ret_t (*led_groupAbility_get)(rtk_led_group_t, rtk_led_ability_t *); + rtk_api_ret_t (*led_serialMode_set)(rtk_led_active_t); + rtk_api_ret_t (*led_serialMode_get)(rtk_led_active_t *); + rtk_api_ret_t (*led_OutputEnable_set)(rtk_enable_t); + rtk_api_ret_t (*led_OutputEnable_get)(rtk_enable_t *); + rtk_api_ret_t (*led_serialModePortmask_set)(rtk_led_serialOutput_t, rtk_portmask_t *); + rtk_api_ret_t (*led_serialModePortmask_get)(rtk_led_serialOutput_t *, rtk_portmask_t *); + + /* oam */ + rtk_api_ret_t (*oam_init)(void); + rtk_api_ret_t (*oam_state_set)(rtk_enable_t); + rtk_api_ret_t (*oam_state_get)(rtk_enable_t *); + rtk_api_ret_t (*oam_parserAction_set)(rtk_port_t, rtk_oam_parser_act_t ); + rtk_api_ret_t (*oam_parserAction_get)(rtk_port_t, rtk_oam_parser_act_t *); + rtk_api_ret_t (*oam_multiplexerAction_set)(rtk_port_t, rtk_oam_multiplexer_act_t ); + rtk_api_ret_t (*oam_multiplexerAction_get)(rtk_port_t, rtk_oam_multiplexer_act_t *); + + /* cpu */ + rtk_api_ret_t (*cpu_enable_set)(rtk_enable_t); + rtk_api_ret_t (*cpu_enable_get)(rtk_enable_t *); + rtk_api_ret_t (*cpu_tagPort_set)(rtk_port_t, rtk_cpu_insert_t); + rtk_api_ret_t (*cpu_tagPort_get)(rtk_port_t *, rtk_cpu_insert_t *); + rtk_api_ret_t (*cpu_awarePort_set)(rtk_portmask_t *); + rtk_api_ret_t (*cpu_awarePort_get)(rtk_portmask_t *); + rtk_api_ret_t (*cpu_tagPosition_set)(rtk_cpu_position_t); + rtk_api_ret_t (*cpu_tagPosition_get)(rtk_cpu_position_t *); + rtk_api_ret_t (*cpu_tagLength_set)(rtk_cpu_tag_length_t); + rtk_api_ret_t (*cpu_tagLength_get)(rtk_cpu_tag_length_t *); + rtk_api_ret_t (*cpu_acceptLength_set)(rtk_cpu_rx_length_t); + rtk_api_ret_t (*cpu_acceptLength_get)(rtk_cpu_rx_length_t *); + rtk_api_ret_t (*cpu_priRemap_set)(rtk_pri_t, rtk_pri_t); + rtk_api_ret_t (*cpu_priRemap_get)(rtk_pri_t, rtk_pri_t *); + + /* stat */ + rtk_api_ret_t (*stat_global_reset)(void); + rtk_api_ret_t (*stat_port_reset)(rtk_port_t); + rtk_api_ret_t (*stat_queueManage_reset)(void); + rtk_api_ret_t (*stat_global_get)(rtk_stat_global_type_t, rtk_stat_counter_t *); + rtk_api_ret_t (*stat_global_getAll)(rtk_stat_global_cntr_t *); + rtk_api_ret_t (*stat_port_get)(rtk_port_t, rtk_stat_port_type_t, rtk_stat_counter_t *); + rtk_api_ret_t (*stat_port_getAll)(rtk_port_t, rtk_stat_port_cntr_t *); + rtk_api_ret_t (*stat_logging_counterCfg_set)(rtk_uint32, rtk_logging_counter_mode_t, rtk_logging_counter_type_t); + rtk_api_ret_t (*stat_logging_counterCfg_get)(rtk_uint32, rtk_logging_counter_mode_t *, rtk_logging_counter_type_t *); + rtk_api_ret_t (*stat_logging_counter_reset)(rtk_uint32); + rtk_api_ret_t (*stat_logging_counter_get)(rtk_uint32, rtk_uint32 *); + rtk_api_ret_t (*stat_lengthMode_set)(rtk_stat_lengthMode_t, rtk_stat_lengthMode_t); + rtk_api_ret_t (*stat_lengthMode_get)(rtk_stat_lengthMode_t *, rtk_stat_lengthMode_t *); + + /* l2 */ + rtk_api_ret_t (*l2_init)(void); + rtk_api_ret_t (*l2_addr_add)(rtk_mac_t *, rtk_l2_ucastAddr_t *); + rtk_api_ret_t (*l2_addr_get)(rtk_mac_t *, rtk_l2_ucastAddr_t *); + rtk_api_ret_t (*l2_addr_next_get)(rtk_l2_read_method_t, rtk_port_t, rtk_uint32 *, rtk_l2_ucastAddr_t *); + rtk_api_ret_t (*l2_addr_del)(rtk_mac_t *, rtk_l2_ucastAddr_t *); + rtk_api_ret_t (*l2_mcastAddr_add)(rtk_l2_mcastAddr_t *); + rtk_api_ret_t (*l2_mcastAddr_get)(rtk_l2_mcastAddr_t *); + rtk_api_ret_t (*l2_mcastAddr_next_get)(rtk_uint32 *, rtk_l2_mcastAddr_t *); + rtk_api_ret_t (*l2_mcastAddr_del)(rtk_l2_mcastAddr_t *); + rtk_api_ret_t (*l2_ipMcastAddr_add)(rtk_l2_ipMcastAddr_t *); + rtk_api_ret_t (*l2_ipMcastAddr_get)(rtk_l2_ipMcastAddr_t *); + rtk_api_ret_t (*l2_ipMcastAddr_next_get)(rtk_uint32 *, rtk_l2_ipMcastAddr_t *); + rtk_api_ret_t (*l2_ipMcastAddr_del)(rtk_l2_ipMcastAddr_t *); + rtk_api_ret_t (*l2_ipVidMcastAddr_add)(rtk_l2_ipVidMcastAddr_t *); + rtk_api_ret_t (*l2_ipVidMcastAddr_get)(rtk_l2_ipVidMcastAddr_t *); + rtk_api_ret_t (*l2_ipVidMcastAddr_next_get)(rtk_uint32 *, rtk_l2_ipVidMcastAddr_t *); + rtk_api_ret_t (*l2_ipVidMcastAddr_del)(rtk_l2_ipVidMcastAddr_t *); + rtk_api_ret_t (*l2_ucastAddr_flush)(rtk_l2_flushCfg_t *); + rtk_api_ret_t (*l2_table_clear)(void); + rtk_api_ret_t (*l2_table_clearStatus_get)(rtk_l2_clearStatus_t *); + rtk_api_ret_t (*l2_flushLinkDownPortAddrEnable_set)(rtk_port_t, rtk_enable_t); + rtk_api_ret_t (*l2_flushLinkDownPortAddrEnable_get)(rtk_port_t, rtk_enable_t *); + rtk_api_ret_t (*l2_agingEnable_set)(rtk_port_t, rtk_enable_t); + rtk_api_ret_t (*l2_agingEnable_get)(rtk_port_t, rtk_enable_t *); + rtk_api_ret_t (*l2_limitLearningCnt_set)(rtk_port_t, rtk_mac_cnt_t); + rtk_api_ret_t (*l2_limitLearningCnt_get)(rtk_port_t, rtk_mac_cnt_t *); + rtk_api_ret_t (*l2_limitSystemLearningCnt_set)(rtk_mac_cnt_t); + rtk_api_ret_t (*l2_limitSystemLearningCnt_get)(rtk_mac_cnt_t *); + rtk_api_ret_t (*l2_limitLearningCntAction_set)(rtk_port_t, rtk_l2_limitLearnCntAction_t); + rtk_api_ret_t (*l2_limitLearningCntAction_get)(rtk_port_t, rtk_l2_limitLearnCntAction_t *); + rtk_api_ret_t (*l2_limitSystemLearningCntAction_set)(rtk_l2_limitLearnCntAction_t); + rtk_api_ret_t (*l2_limitSystemLearningCntAction_get)(rtk_l2_limitLearnCntAction_t *); + rtk_api_ret_t (*l2_limitSystemLearningCntPortMask_set)(rtk_portmask_t *); + rtk_api_ret_t (*l2_limitSystemLearningCntPortMask_get)(rtk_portmask_t *); + rtk_api_ret_t (*l2_learningCnt_get)(rtk_port_t port, rtk_mac_cnt_t *); + rtk_api_ret_t (*l2_floodPortMask_set)(rtk_l2_flood_type_t, rtk_portmask_t *); + rtk_api_ret_t (*l2_floodPortMask_get)(rtk_l2_flood_type_t, rtk_portmask_t *); + rtk_api_ret_t (*l2_localPktPermit_set)(rtk_port_t, rtk_enable_t); + rtk_api_ret_t (*l2_localPktPermit_get)(rtk_port_t, rtk_enable_t *); + rtk_api_ret_t (*l2_aging_set)(rtk_l2_age_time_t); + rtk_api_ret_t (*l2_aging_get)(rtk_l2_age_time_t *); + rtk_api_ret_t (*l2_ipMcastAddrLookup_set)(rtk_l2_ipmc_lookup_type_t); + rtk_api_ret_t (*l2_ipMcastAddrLookup_get)(rtk_l2_ipmc_lookup_type_t *); + rtk_api_ret_t (*l2_ipMcastForwardRouterPort_set)(rtk_enable_t); + rtk_api_ret_t (*l2_ipMcastForwardRouterPort_get)(rtk_enable_t *); + rtk_api_ret_t (*l2_ipMcastGroupEntry_add)(ipaddr_t, rtk_uint32, rtk_portmask_t *); + rtk_api_ret_t (*l2_ipMcastGroupEntry_del)(ipaddr_t, rtk_uint32); + rtk_api_ret_t (*l2_ipMcastGroupEntry_get)(ipaddr_t, rtk_uint32, rtk_portmask_t *); + rtk_api_ret_t (*l2_entry_get)(rtk_l2_addr_table_t *); + rtk_api_ret_t (*l2_lookupHitIsolationAction_set)(rtk_l2_lookupHitIsolationAction_t); + rtk_api_ret_t (*l2_lookupHitIsolationAction_get)(rtk_l2_lookupHitIsolationAction_t *); + + /* interrupt */ + rtk_api_ret_t (*int_polarity_set)(rtk_int_polarity_t); + rtk_api_ret_t (*int_polarity_get)(rtk_int_polarity_t *); + rtk_api_ret_t (*int_control_set)(rtk_int_type_t, rtk_enable_t); + rtk_api_ret_t (*int_control_get)(rtk_int_type_t, rtk_enable_t *); + rtk_api_ret_t (*int_status_set)(rtk_int_status_t *); + rtk_api_ret_t (*int_status_get)(rtk_int_status_t *); + rtk_api_ret_t (*int_advanceInfo_get)(rtk_int_advType_t, rtk_int_info_t *); + + /* acl */ + rtk_api_ret_t (*filter_igrAcl_init)(void); + rtk_api_ret_t (*filter_igrAcl_field_add)(rtk_filter_cfg_t *, rtk_filter_field_t *); + rtk_api_ret_t (*filter_igrAcl_cfg_add)(rtk_filter_id_t, rtk_filter_cfg_t *, rtk_filter_action_t *, rtk_filter_number_t *); + rtk_api_ret_t (*filter_igrAcl_cfg_del)(rtk_filter_id_t); + rtk_api_ret_t (*filter_igrAcl_cfg_delAll)(void); + rtk_api_ret_t (*filter_igrAcl_cfg_get)(rtk_filter_id_t, rtk_filter_cfg_raw_t *, rtk_filter_action_t *); + rtk_api_ret_t (*filter_igrAcl_unmatchAction_set)(rtk_port_t, rtk_filter_unmatch_action_t); + rtk_api_ret_t (*filter_igrAcl_unmatchAction_get)(rtk_port_t, rtk_filter_unmatch_action_t *); + rtk_api_ret_t (*filter_igrAcl_state_set)(rtk_port_t, rtk_filter_state_t); + rtk_api_ret_t (*filter_igrAcl_state_get)(rtk_port_t, rtk_filter_state_t *); + rtk_api_ret_t (*filter_igrAcl_template_set)(rtk_filter_template_t *); + rtk_api_ret_t (*filter_igrAcl_template_get)(rtk_filter_template_t *); + rtk_api_ret_t (*filter_igrAcl_field_sel_set)(rtk_uint32, rtk_field_sel_t, rtk_uint32); + rtk_api_ret_t (*filter_igrAcl_field_sel_get)(rtk_uint32, rtk_field_sel_t *, rtk_uint32 *); + rtk_api_ret_t (*filter_iprange_set)(rtk_uint32, rtk_filter_iprange_t, ipaddr_t, ipaddr_t); + rtk_api_ret_t (*filter_iprange_get)(rtk_uint32, rtk_filter_iprange_t *, ipaddr_t *, ipaddr_t *); + rtk_api_ret_t (*filter_vidrange_set)(rtk_uint32, rtk_filter_vidrange_t, rtk_uint32, rtk_uint32); + rtk_api_ret_t (*filter_vidrange_get)(rtk_uint32, rtk_filter_vidrange_t *, rtk_uint32 *, rtk_uint32 *); + rtk_api_ret_t (*filter_portrange_set)(rtk_uint32, rtk_filter_portrange_t, rtk_uint32, rtk_uint32); + rtk_api_ret_t (*filter_portrange_get)(rtk_uint32, rtk_filter_portrange_t *, rtk_uint32 *, rtk_uint32 *); + rtk_api_ret_t (*filter_igrAclPolarity_set)(rtk_uint32); + rtk_api_ret_t (*filter_igrAclPolarity_get)(rtk_uint32 *); + + /* mirror */ + rtk_api_ret_t (*mirror_portBased_set)(rtk_port_t, rtk_portmask_t *, rtk_portmask_t *); + rtk_api_ret_t (*mirror_portBased_get)(rtk_port_t *, rtk_portmask_t *, rtk_portmask_t *); + rtk_api_ret_t (*mirror_portIso_set)(rtk_enable_t); + rtk_api_ret_t (*mirror_portIso_get)(rtk_enable_t *); + rtk_api_ret_t (*mirror_vlanLeaky_set)(rtk_enable_t , rtk_enable_t); + rtk_api_ret_t (*mirror_vlanLeaky_get)(rtk_enable_t *, rtk_enable_t *); + rtk_api_ret_t (*mirror_isolationLeaky_set)(rtk_enable_t, rtk_enable_t ); + rtk_api_ret_t (*mirror_isolationLeaky_get)(rtk_enable_t *, rtk_enable_t *); + rtk_api_ret_t (*mirror_keep_set)(rtk_mirror_keep_t); + rtk_api_ret_t (*mirror_keep_get)(rtk_mirror_keep_t *); + rtk_api_ret_t (*mirror_override_set)(rtk_enable_t, rtk_enable_t, rtk_enable_t); + rtk_api_ret_t (*mirror_override_get)(rtk_enable_t *, rtk_enable_t *, rtk_enable_t *); + + /* port */ + rtk_api_ret_t (*port_phyAutoNegoAbility_set)(rtk_port_t, rtk_port_phy_ability_t *); + rtk_api_ret_t (*port_phyAutoNegoAbility_get)(rtk_port_t, rtk_port_phy_ability_t *); + rtk_api_ret_t (*port_phyForceModeAbility_set)(rtk_port_t, rtk_port_phy_ability_t *); + rtk_api_ret_t (*port_phyForceModeAbility_get)(rtk_port_t, rtk_port_phy_ability_t *); + rtk_api_ret_t (*port_phyStatus_get)(rtk_port_t, rtk_port_linkStatus_t *, rtk_port_speed_t *, rtk_port_duplex_t *); + rtk_api_ret_t (*port_macForceLink_set)(rtk_port_t, rtk_port_mac_ability_t *); + rtk_api_ret_t (*port_macForceLink_get)(rtk_port_t, rtk_port_mac_ability_t *); + rtk_api_ret_t (*port_macForceLinkExt_set)(rtk_port_t, rtk_mode_ext_t, rtk_port_mac_ability_t *); + rtk_api_ret_t (*port_macForceLinkExt_get)(rtk_port_t, rtk_mode_ext_t *, rtk_port_mac_ability_t *); + rtk_api_ret_t (*port_macStatus_get)(rtk_port_t, rtk_port_mac_ability_t *); + rtk_api_ret_t (*port_macLocalLoopbackEnable_set)(rtk_port_t, rtk_enable_t); + rtk_api_ret_t (*port_macLocalLoopbackEnable_get)(rtk_port_t, rtk_enable_t *); + rtk_api_ret_t (*port_phyReg_set)(rtk_port_t, rtk_port_phy_reg_t, rtk_port_phy_data_t); + rtk_api_ret_t (*port_phyReg_get)(rtk_port_t, rtk_port_phy_reg_t, rtk_port_phy_data_t *); + rtk_api_ret_t (*port_phyOCPReg_set)(rtk_port_t, rtk_uint32, rtk_uint32); + rtk_api_ret_t (*port_phyOCPReg_get)(rtk_port_t, rtk_uint32, rtk_uint32 *); + rtk_api_ret_t (*port_backpressureEnable_set)(rtk_port_t, rtk_enable_t); + rtk_api_ret_t (*port_backpressureEnable_get)(rtk_port_t, rtk_enable_t *); + rtk_api_ret_t (*port_adminEnable_set)(rtk_port_t, rtk_enable_t); + rtk_api_ret_t (*port_adminEnable_get)(rtk_port_t, rtk_enable_t *); + rtk_api_ret_t (*port_isolation_set)(rtk_port_t, rtk_portmask_t *); + rtk_api_ret_t (*port_isolation_get)(rtk_port_t, rtk_portmask_t *); + rtk_api_ret_t (*port_rgmiiDelayExt_set)(rtk_port_t, rtk_data_t, rtk_data_t); + rtk_api_ret_t (*port_rgmiiDelayExt_get)(rtk_port_t, rtk_data_t *, rtk_data_t *); + rtk_api_ret_t (*port_phyEnableAll_set)(rtk_enable_t); + rtk_api_ret_t (*port_phyEnableAll_get)(rtk_enable_t *); + rtk_api_ret_t (*port_efid_set)(rtk_port_t, rtk_data_t); + rtk_api_ret_t (*port_efid_get)(rtk_port_t, rtk_data_t *); + rtk_api_ret_t (*port_phyComboPortMedia_set)(rtk_port_t, rtk_port_media_t); + rtk_api_ret_t (*port_phyComboPortMedia_get)(rtk_port_t, rtk_port_media_t *); + rtk_api_ret_t (*port_rtctEnable_set)(rtk_portmask_t *); + rtk_api_ret_t (*port_rtctDisable_set)(rtk_portmask_t *); + rtk_api_ret_t (*port_rtctResult_get)(rtk_port_t, rtk_rtctResult_t *); + rtk_api_ret_t (*port_sds_reset)(rtk_port_t); + rtk_api_ret_t (*port_sgmiiLinkStatus_get)(rtk_port_t, rtk_data_t *, rtk_data_t *, rtk_port_linkStatus_t *); + rtk_api_ret_t (*port_sgmiiNway_set)(rtk_port_t, rtk_enable_t); + rtk_api_ret_t (*port_sgmiiNway_get)(rtk_port_t, rtk_enable_t *); + rtk_api_ret_t (*port_fiberAbilityExt_set)(rtk_port_t, rtk_uint32, rtk_uint32); + rtk_api_ret_t (*port_fiberAbilityExt_get)(rtk_port_t, rtk_uint32 *, rtk_uint32 *); + rtk_api_ret_t (*port_autoDos_set)(rtk_port_autoDosType_t, rtk_enable_t); + rtk_api_ret_t (*port_autoDos_get)(rtk_port_autoDosType_t, rtk_enable_t *); + rtk_api_ret_t (*port_fiberAbility_set)(rtk_port_t, rtk_port_fiber_ability_t *); + rtk_api_ret_t (*port_fiberAbility_get)(rtk_port_t, rtk_port_fiber_ability_t *); + rtk_api_ret_t (*port_phyMdx_set)(rtk_port_t, rtk_port_phy_mdix_mode_t); + rtk_api_ret_t (*port_phyMdx_get)(rtk_port_t, rtk_port_phy_mdix_mode_t *); + rtk_api_ret_t (*port_phyMdxStatus_get)(rtk_port_t, rtk_port_phy_mdix_status_t *); + rtk_api_ret_t (*port_phyTestMode_set)(rtk_port_t, rtk_port_phy_test_mode_t); + rtk_api_ret_t (*port_phyTestMode_get)(rtk_port_t, rtk_port_phy_test_mode_t *); + + /* trap */ + rtk_api_ret_t (*trap_unknownUnicastPktAction_set)(rtk_port_t, rtk_trap_ucast_action_t); + rtk_api_ret_t (*trap_unknownUnicastPktAction_get)(rtk_port_t, rtk_trap_ucast_action_t *); + rtk_api_ret_t (*trap_unknownMacPktAction_set)(rtk_trap_ucast_action_t); + rtk_api_ret_t (*trap_unknownMacPktAction_get)(rtk_trap_ucast_action_t *); + rtk_api_ret_t (*trap_unmatchMacPktAction_set)(rtk_trap_ucast_action_t); + rtk_api_ret_t (*trap_unmatchMacPktAction_get)(rtk_trap_ucast_action_t *); + rtk_api_ret_t (*trap_unmatchMacMoving_set)(rtk_port_t, rtk_enable_t); + rtk_api_ret_t (*trap_unmatchMacMoving_get)(rtk_port_t, rtk_enable_t *); + rtk_api_ret_t (*trap_unknownMcastPktAction_set)(rtk_port_t, rtk_mcast_type_t, rtk_trap_mcast_action_t); + rtk_api_ret_t (*trap_unknownMcastPktAction_get)(rtk_port_t, rtk_mcast_type_t, rtk_trap_mcast_action_t *); + rtk_api_ret_t (*trap_lldpEnable_set)(rtk_enable_t); + rtk_api_ret_t (*trap_lldpEnable_get)(rtk_enable_t *); + rtk_api_ret_t (*trap_reasonTrapToCpuPriority_set)(rtk_trap_reason_type_t, rtk_pri_t); + rtk_api_ret_t (*trap_reasonTrapToCpuPriority_get)(rtk_trap_reason_type_t, rtk_pri_t *); + rtk_api_ret_t (*trap_rmaAction_set)(rtk_trap_type_t, rtk_trap_rma_action_t); + rtk_api_ret_t (*trap_rmaAction_get)(rtk_trap_type_t, rtk_trap_rma_action_t *); + rtk_api_ret_t (*trap_rmaKeepFormat_set)(rtk_trap_type_t, rtk_enable_t); + rtk_api_ret_t (*trap_rmaKeepFormat_get)(rtk_trap_type_t, rtk_enable_t *); + rtk_api_ret_t (*trap_portUnknownMacPktAction_set)(rtk_port_t, rtk_trap_ucast_action_t); + rtk_api_ret_t (*trap_portUnknownMacPktAction_get)(rtk_port_t, rtk_trap_ucast_action_t *); + rtk_api_ret_t (*trap_portUnmatchMacPktAction_set)(rtk_port_t, rtk_trap_ucast_action_t); + rtk_api_ret_t (*trap_portUnmatchMacPktAction_get)(rtk_port_t, rtk_trap_ucast_action_t *); + + /* IGMP */ + rtk_api_ret_t (*igmp_init)(void); + rtk_api_ret_t (*igmp_state_set)(rtk_enable_t); + rtk_api_ret_t (*igmp_state_get)(rtk_enable_t *); + rtk_api_ret_t (*igmp_static_router_port_set)(rtk_portmask_t *); + rtk_api_ret_t (*igmp_static_router_port_get)(rtk_portmask_t *); + rtk_api_ret_t (*igmp_protocol_set)(rtk_port_t, rtk_igmp_protocol_t, rtk_igmp_action_t); + rtk_api_ret_t (*igmp_protocol_get)(rtk_port_t, rtk_igmp_protocol_t, rtk_igmp_action_t *); + rtk_api_ret_t (*igmp_fastLeave_set)(rtk_enable_t); + rtk_api_ret_t (*igmp_fastLeave_get)(rtk_enable_t *); + rtk_api_ret_t (*igmp_maxGroup_set)(rtk_port_t, rtk_uint32); + rtk_api_ret_t (*igmp_maxGroup_get)(rtk_port_t, rtk_uint32 *); + rtk_api_ret_t (*igmp_currentGroup_get)(rtk_port_t, rtk_uint32 *); + rtk_api_ret_t (*igmp_tableFullAction_set)(rtk_igmp_tableFullAction_t); + rtk_api_ret_t (*igmp_tableFullAction_get)(rtk_igmp_tableFullAction_t *); + rtk_api_ret_t (*igmp_checksumErrorAction_set)(rtk_igmp_checksumErrorAction_t); + rtk_api_ret_t (*igmp_checksumErrorAction_get)(rtk_igmp_checksumErrorAction_t *); + rtk_api_ret_t (*igmp_leaveTimer_set)(rtk_uint32); + rtk_api_ret_t (*igmp_leaveTimer_get)(rtk_uint32 *); + rtk_api_ret_t (*igmp_queryInterval_set)(rtk_uint32); + rtk_api_ret_t (*igmp_queryInterval_get)(rtk_uint32 *); + rtk_api_ret_t (*igmp_robustness_set)(rtk_uint32); + rtk_api_ret_t (*igmp_robustness_get)(rtk_uint32 *); + rtk_api_ret_t (*igmp_dynamicRouterPortAllow_set)(rtk_portmask_t *); + rtk_api_ret_t (*igmp_dynamicRouterPortAllow_get)(rtk_portmask_t *); + rtk_api_ret_t (*igmp_dynamicRouterPort_get)(rtk_igmp_dynamicRouterPort_t *); + rtk_api_ret_t (*igmp_suppressionEnable_set)(rtk_enable_t, rtk_enable_t); + rtk_api_ret_t (*igmp_suppressionEnable_get)(rtk_enable_t *, rtk_enable_t *); + rtk_api_ret_t (*igmp_portRxPktEnable_set)(rtk_port_t, rtk_igmp_rxPktEnable_t *); + rtk_api_ret_t (*igmp_portRxPktEnable_get)(rtk_port_t, rtk_igmp_rxPktEnable_t *); + rtk_api_ret_t (*igmp_groupInfo_get)(rtk_uint32, rtk_igmp_groupInfo_t *); + rtk_api_ret_t (*igmp_ReportLeaveFwdAction_set)(rtk_igmp_ReportLeaveFwdAct_t); + rtk_api_ret_t (*igmp_ReportLeaveFwdAction_get)(rtk_igmp_ReportLeaveFwdAct_t *); + rtk_api_ret_t (*igmp_dropLeaveZeroEnable_set)(rtk_enable_t); + rtk_api_ret_t (*igmp_dropLeaveZeroEnable_get)(rtk_enable_t *); + rtk_api_ret_t (*igmp_bypassGroupRange_set)(rtk_igmp_bypassGroup_t, rtk_enable_t); + rtk_api_ret_t (*igmp_bypassGroupRange_get)(rtk_igmp_bypassGroup_t, rtk_enable_t *); + + /* Storm */ + rtk_api_ret_t (*rate_stormControlMeterIdx_set)(rtk_port_t, rtk_rate_storm_group_t, rtk_uint32); + rtk_api_ret_t (*rate_stormControlMeterIdx_get)(rtk_port_t, rtk_rate_storm_group_t, rtk_uint32 *); + rtk_api_ret_t (*rate_stormControlPortEnable_set)(rtk_port_t, rtk_rate_storm_group_t, rtk_enable_t); + rtk_api_ret_t (*rate_stormControlPortEnable_get)(rtk_port_t, rtk_rate_storm_group_t, rtk_enable_t *); + rtk_api_ret_t (*storm_bypass_set)(rtk_storm_bypass_t, rtk_enable_t); + rtk_api_ret_t (*storm_bypass_get)(rtk_storm_bypass_t, rtk_enable_t *); + rtk_api_ret_t (*rate_stormControlExtPortmask_set)(rtk_portmask_t *); + rtk_api_ret_t (*rate_stormControlExtPortmask_get)(rtk_portmask_t *); + rtk_api_ret_t (*rate_stormControlExtEnable_set)(rtk_rate_storm_group_t, rtk_enable_t); + rtk_api_ret_t (*rate_stormControlExtEnable_get)(rtk_rate_storm_group_t, rtk_enable_t *); + rtk_api_ret_t (*rate_stormControlExtMeterIdx_set)(rtk_rate_storm_group_t, rtk_uint32); + rtk_api_ret_t (*rate_stormControlExtMeterIdx_get)(rtk_rate_storm_group_t, rtk_uint32 *); + + /* Rate */ + rtk_api_ret_t (*rate_shareMeter_set)(rtk_meter_id_t, rtk_meter_type_t, rtk_rate_t, rtk_enable_t); + rtk_api_ret_t (*rate_shareMeter_get)(rtk_meter_id_t, rtk_meter_type_t *, rtk_rate_t *, rtk_enable_t *); + rtk_api_ret_t (*rate_shareMeterBucket_set)(rtk_meter_id_t, rtk_uint32); + rtk_api_ret_t (*rate_shareMeterBucket_get)(rtk_meter_id_t, rtk_uint32 *); + rtk_api_ret_t (*rate_igrBandwidthCtrlRate_set)(rtk_port_t, rtk_rate_t, rtk_enable_t, rtk_enable_t); + rtk_api_ret_t (*rate_igrBandwidthCtrlRate_get)(rtk_port_t, rtk_rate_t *, rtk_enable_t *, rtk_enable_t *); + rtk_api_ret_t (*rate_egrBandwidthCtrlRate_set)(rtk_port_t, rtk_rate_t, rtk_enable_t); + rtk_api_ret_t (*rate_egrBandwidthCtrlRate_get)(rtk_port_t, rtk_rate_t *, rtk_enable_t *); + rtk_api_ret_t (*rate_egrQueueBwCtrlEnable_set)(rtk_port_t, rtk_qid_t, rtk_enable_t); + rtk_api_ret_t (*rate_egrQueueBwCtrlEnable_get)(rtk_port_t, rtk_qid_t, rtk_enable_t *); + rtk_api_ret_t (*rate_egrQueueBwCtrlRate_set)(rtk_port_t, rtk_qid_t, rtk_meter_id_t); + rtk_api_ret_t (*rate_egrQueueBwCtrlRate_get)(rtk_port_t, rtk_qid_t, rtk_meter_id_t *); + + /* I2C */ + rtk_api_ret_t (*i2c_init)(void); + rtk_api_ret_t (*i2c_data_read)(rtk_uint8, rtk_uint32, rtk_uint32 *); + rtk_api_ret_t (*i2c_data_write)(rtk_uint8, rtk_uint32, rtk_uint32); + rtk_api_ret_t (*i2c_mode_set)(rtk_I2C_16bit_mode_t ); + rtk_api_ret_t (*i2c_mode_get)(rtk_I2C_16bit_mode_t *); + rtk_api_ret_t (*i2c_gpioPinGroup_set)(rtk_I2C_gpio_pin_t); + rtk_api_ret_t (*i2c_gpioPinGroup_get)(rtk_I2C_gpio_pin_t *); + + /*PTP*/ + rtk_api_ret_t (*ptp_init)(void); + rtk_api_ret_t (*ptp_mac_set)(rtk_mac_t ); + rtk_api_ret_t (*ptp_mac_get)(rtk_mac_t *); + rtk_api_ret_t (*ptp_tpid_set)(rtk_ptp_tpid_t, rtk_ptp_tpid_t); + rtk_api_ret_t (*ptp_tpid_get)(rtk_ptp_tpid_t *, rtk_ptp_tpid_t *); + rtk_api_ret_t (*ptp_refTime_set)(rtk_ptp_timeStamp_t ); + rtk_api_ret_t (*ptp_refTime_get)(rtk_ptp_timeStamp_t *); + rtk_api_ret_t (*ptp_refTimeAdjust_set)(rtk_ptp_sys_adjust_t, rtk_ptp_timeStamp_t); + rtk_api_ret_t (*ptp_refTimeEnable_set)(rtk_enable_t); + rtk_api_ret_t (*ptp_refTimeEnable_get)(rtk_enable_t *); + rtk_api_ret_t (*ptp_portEnable_set)(rtk_port_t, rtk_enable_t ); + rtk_api_ret_t (*ptp_portEnable_get)(rtk_port_t, rtk_enable_t *); + rtk_api_ret_t (*ptp_portTimestamp_get)( rtk_port_t, rtk_ptp_msgType_t, rtk_ptp_info_t *); + rtk_api_ret_t (*ptp_intControl_set)(rtk_ptp_intType_t, rtk_enable_t); + rtk_api_ret_t (*ptp_intControl_get)(rtk_ptp_intType_t, rtk_enable_t *); + rtk_api_ret_t (*ptp_intStatus_get)(rtk_ptp_intStatus_t *); + rtk_api_ret_t (*ptp_portIntStatus_set)(rtk_port_t, rtk_ptp_intStatus_t ); + rtk_api_ret_t (*ptp_portIntStatus_get)(rtk_port_t, rtk_ptp_intStatus_t *); + rtk_api_ret_t (*ptp_portTrap_set)(rtk_port_t, rtk_enable_t); + rtk_api_ret_t (*ptp_portTrap_get)(rtk_port_t, rtk_enable_t *); + + /*QoS*/ + rtk_api_ret_t (*qos_init)(rtk_queue_num_t); + rtk_api_ret_t (*qos_priSel_set)(rtk_qos_priDecTbl_t, rtk_priority_select_t *); + rtk_api_ret_t (*qos_priSel_get)(rtk_qos_priDecTbl_t, rtk_priority_select_t *); + rtk_api_ret_t (*qos_1pPriRemap_set)(rtk_pri_t, rtk_pri_t); + rtk_api_ret_t (*qos_1pPriRemap_get)(rtk_pri_t, rtk_pri_t *); + rtk_api_ret_t (*qos_1pRemarkSrcSel_set)(rtk_qos_1pRmkSrc_t ); + rtk_api_ret_t (*qos_1pRemarkSrcSel_get)(rtk_qos_1pRmkSrc_t *); + rtk_api_ret_t (*qos_dscpPriRemap_set)(rtk_dscp_t, rtk_pri_t ); + rtk_api_ret_t (*qos_dscpPriRemap_get)(rtk_dscp_t, rtk_pri_t *); + rtk_api_ret_t (*qos_portPri_set)(rtk_port_t, rtk_pri_t ) ; + rtk_api_ret_t (*qos_portPri_get)(rtk_port_t, rtk_pri_t *) ; + rtk_api_ret_t (*qos_queueNum_set)(rtk_port_t, rtk_queue_num_t); + rtk_api_ret_t (*qos_queueNum_get)(rtk_port_t, rtk_queue_num_t *); + rtk_api_ret_t (*qos_priMap_set)(rtk_queue_num_t, rtk_qos_pri2queue_t *); + rtk_api_ret_t (*qos_priMap_get)(rtk_queue_num_t, rtk_qos_pri2queue_t *); + rtk_api_ret_t (*qos_schedulingQueue_set)(rtk_port_t, rtk_qos_queue_weights_t *); + rtk_api_ret_t (*qos_schedulingQueue_get)(rtk_port_t, rtk_qos_queue_weights_t *); + rtk_api_ret_t (*qos_1pRemarkEnable_set)(rtk_port_t, rtk_enable_t); + rtk_api_ret_t (*qos_1pRemarkEnable_get)(rtk_port_t, rtk_enable_t *); + rtk_api_ret_t (*qos_1pRemark_set)(rtk_pri_t, rtk_pri_t); + rtk_api_ret_t (*qos_1pRemark_get)(rtk_pri_t, rtk_pri_t *); + rtk_api_ret_t (*qos_dscpRemarkEnable_set)(rtk_port_t, rtk_enable_t); + rtk_api_ret_t (*qos_dscpRemarkEnable_get)(rtk_port_t, rtk_enable_t *); + rtk_api_ret_t (*qos_dscpRemark_set)(rtk_pri_t, rtk_dscp_t); + rtk_api_ret_t (*qos_dscpRemark_get)(rtk_pri_t, rtk_dscp_t *); + rtk_api_ret_t (*qos_dscpRemarkSrcSel_set)(rtk_qos_dscpRmkSrc_t); + rtk_api_ret_t (*qos_dscpRemarkSrcSel_get)(rtk_qos_dscpRmkSrc_t *); + rtk_api_ret_t (*qos_dscpRemark2Dscp_set)(rtk_dscp_t, rtk_dscp_t); + rtk_api_ret_t (*qos_dscpRemark2Dscp_get)(rtk_dscp_t, rtk_dscp_t *); + rtk_api_ret_t (*qos_portPriSelIndex_set)(rtk_port_t, rtk_qos_priDecTbl_t); + rtk_api_ret_t (*qos_portPriSelIndex_get)(rtk_port_t, rtk_qos_priDecTbl_t *); + rtk_api_ret_t (*qos_schedulingType_set)(rtk_qos_scheduling_type_t); + rtk_api_ret_t (*qos_schedulingType_get)(rtk_qos_scheduling_type_t *); + + /*VLAN*/ + rtk_api_ret_t (*vlan_init)(void); + rtk_api_ret_t (*vlan_set)(rtk_vlan_t, rtk_vlan_cfg_t *); + rtk_api_ret_t (*vlan_get)(rtk_vlan_t, rtk_vlan_cfg_t *); + rtk_api_ret_t (*vlan_egrFilterEnable_set)(rtk_enable_t); + rtk_api_ret_t (*vlan_egrFilterEnable_get)(rtk_enable_t *); + rtk_api_ret_t (*vlan_mbrCfg_set)(rtk_uint32, rtk_vlan_mbrcfg_t *); + rtk_api_ret_t (*vlan_mbrCfg_get)(rtk_uint32, rtk_vlan_mbrcfg_t *); + rtk_api_ret_t (*vlan_portPvid_set)(rtk_port_t, rtk_vlan_t, rtk_pri_t); + rtk_api_ret_t (*vlan_portPvid_get)(rtk_port_t, rtk_vlan_t *, rtk_pri_t *); + rtk_api_ret_t (*vlan_portIgrFilterEnable_set)(rtk_port_t, rtk_enable_t); + rtk_api_ret_t (*vlan_portIgrFilterEnable_get)(rtk_port_t, rtk_enable_t *); + rtk_api_ret_t (*vlan_portAcceptFrameType_set)(rtk_port_t, rtk_vlan_acceptFrameType_t); + rtk_api_ret_t (*vlan_portAcceptFrameType_get)(rtk_port_t, rtk_vlan_acceptFrameType_t *); + rtk_api_ret_t (*vlan_tagMode_set)(rtk_port_t, rtk_vlan_tagMode_t); + rtk_api_ret_t (*vlan_tagMode_get)(rtk_port_t, rtk_vlan_tagMode_t *); + rtk_api_ret_t (*vlan_transparent_set)(rtk_port_t, rtk_portmask_t *); + rtk_api_ret_t (*vlan_transparent_get)(rtk_port_t , rtk_portmask_t *); + rtk_api_ret_t (*vlan_keep_set)(rtk_port_t, rtk_portmask_t *); + rtk_api_ret_t (*vlan_keep_get)(rtk_port_t, rtk_portmask_t *); + rtk_api_ret_t (*vlan_stg_set)(rtk_vlan_t, rtk_stp_msti_id_t); + rtk_api_ret_t (*vlan_stg_get)(rtk_vlan_t, rtk_stp_msti_id_t *); + rtk_api_ret_t (*vlan_protoAndPortBasedVlan_add)(rtk_port_t, rtk_vlan_protoAndPortInfo_t *); + rtk_api_ret_t (*vlan_protoAndPortBasedVlan_get)(rtk_port_t , rtk_vlan_proto_type_t, rtk_vlan_protoVlan_frameType_t, rtk_vlan_protoAndPortInfo_t *); + rtk_api_ret_t (*vlan_protoAndPortBasedVlan_del)(rtk_port_t , rtk_vlan_proto_type_t, rtk_vlan_protoVlan_frameType_t); + rtk_api_ret_t (*vlan_protoAndPortBasedVlan_delAll)(rtk_port_t); + rtk_api_ret_t (*vlan_portFid_set)(rtk_port_t port, rtk_enable_t, rtk_fid_t); + rtk_api_ret_t (*vlan_portFid_get)(rtk_port_t port, rtk_enable_t *, rtk_fid_t *); + rtk_api_ret_t (*vlan_UntagDscpPriorityEnable_set)(rtk_enable_t); + rtk_api_ret_t (*vlan_UntagDscpPriorityEnable_get)(rtk_enable_t *); + rtk_api_ret_t (*stp_mstpState_set)(rtk_stp_msti_id_t, rtk_port_t, rtk_stp_state_t); + rtk_api_ret_t (*stp_mstpState_get)(rtk_stp_msti_id_t, rtk_port_t, rtk_stp_state_t *); + rtk_api_ret_t (*vlan_reservedVidAction_set)(rtk_vlan_resVidAction_t, rtk_vlan_resVidAction_t); + rtk_api_ret_t (*vlan_reservedVidAction_get)(rtk_vlan_resVidAction_t *, rtk_vlan_resVidAction_t *); + rtk_api_ret_t (*vlan_realKeepRemarkEnable_set)(rtk_enable_t ); + rtk_api_ret_t (*vlan_realKeepRemarkEnable_get)(rtk_enable_t *); + rtk_api_ret_t (*vlan_reset)(void); + + /*dot1x*/ + rtk_api_ret_t (*dot1x_unauthPacketOper_set)(rtk_port_t, rtk_dot1x_unauth_action_t); + rtk_api_ret_t (*dot1x_unauthPacketOper_get)(rtk_port_t, rtk_dot1x_unauth_action_t *); + rtk_api_ret_t (*dot1x_eapolFrame2CpuEnable_set)(rtk_enable_t); + rtk_api_ret_t (*dot1x_eapolFrame2CpuEnable_get)(rtk_enable_t *); + rtk_api_ret_t (*dot1x_portBasedEnable_set)(rtk_port_t port, rtk_enable_t); + rtk_api_ret_t (*dot1x_portBasedEnable_get)(rtk_port_t port, rtk_enable_t *); + rtk_api_ret_t (*dot1x_portBasedAuthStatus_set)(rtk_port_t, rtk_dot1x_auth_status_t); + rtk_api_ret_t (*dot1x_portBasedAuthStatus_get)(rtk_port_t, rtk_dot1x_auth_status_t *); + rtk_api_ret_t (*dot1x_portBasedDirection_set)(rtk_port_t, rtk_dot1x_direction_t); + rtk_api_ret_t (*dot1x_portBasedDirection_get)(rtk_port_t, rtk_dot1x_direction_t *); + rtk_api_ret_t (*dot1x_macBasedEnable_set)(rtk_port_t, rtk_enable_t); + rtk_api_ret_t (*dot1x_macBasedEnable_get)(rtk_port_t , rtk_enable_t *); + rtk_api_ret_t (*dot1x_macBasedAuthMac_add)(rtk_port_t, rtk_mac_t *, rtk_fid_t); + rtk_api_ret_t (*dot1x_macBasedAuthMac_del)(rtk_port_t, rtk_mac_t *, rtk_fid_t); + rtk_api_ret_t (*dot1x_macBasedDirection_set)(rtk_dot1x_direction_t); + rtk_api_ret_t (*dot1x_macBasedDirection_get)(rtk_dot1x_direction_t *); + rtk_api_ret_t (*dot1x_guestVlan_set)(rtk_vlan_t ); + rtk_api_ret_t (*dot1x_guestVlan_get)(rtk_vlan_t *); + rtk_api_ret_t (*dot1x_guestVlan2Auth_set)(rtk_enable_t); + rtk_api_ret_t (*dot1x_guestVlan2Auth_get)(rtk_enable_t *); + + /*SVLAN*/ + rtk_api_ret_t (*svlan_init)(void); + rtk_api_ret_t (*svlan_servicePort_add)(rtk_port_t port); + rtk_api_ret_t (*svlan_servicePort_get)(rtk_portmask_t *); + rtk_api_ret_t (*svlan_servicePort_del)(rtk_port_t); + rtk_api_ret_t (*svlan_tpidEntry_set)(rtk_uint32); + rtk_api_ret_t (*svlan_tpidEntry_get)(rtk_uint32 *); + rtk_api_ret_t (*svlan_priorityRef_set)(rtk_svlan_pri_ref_t); + rtk_api_ret_t (*svlan_priorityRef_get)(rtk_svlan_pri_ref_t *); + rtk_api_ret_t (*svlan_memberPortEntry_set)(rtk_uint32, rtk_svlan_memberCfg_t *); + rtk_api_ret_t (*svlan_memberPortEntry_get)(rtk_uint32, rtk_svlan_memberCfg_t *); + rtk_api_ret_t (*svlan_memberPortEntry_adv_set)(rtk_uint32, rtk_svlan_memberCfg_t *); + rtk_api_ret_t (*svlan_memberPortEntry_adv_get)(rtk_uint32, rtk_svlan_memberCfg_t *); + rtk_api_ret_t (*svlan_defaultSvlan_set)(rtk_port_t, rtk_vlan_t); + rtk_api_ret_t (*svlan_defaultSvlan_get)(rtk_port_t, rtk_vlan_t *); + rtk_api_ret_t (*svlan_c2s_add)(rtk_vlan_t, rtk_port_t, rtk_vlan_t); + rtk_api_ret_t (*svlan_c2s_del)(rtk_vlan_t, rtk_port_t); + rtk_api_ret_t (*svlan_c2s_get)(rtk_vlan_t, rtk_port_t, rtk_vlan_t *); + rtk_api_ret_t (*svlan_untag_action_set)(rtk_svlan_untag_action_t, rtk_vlan_t); + rtk_api_ret_t (*svlan_untag_action_get)(rtk_svlan_untag_action_t *, rtk_vlan_t *); + rtk_api_ret_t (*svlan_unmatch_action_set)(rtk_svlan_unmatch_action_t, rtk_vlan_t); + rtk_api_ret_t (*svlan_unmatch_action_get)(rtk_svlan_unmatch_action_t *, rtk_vlan_t *); + rtk_api_ret_t (*svlan_dmac_vidsel_set)(rtk_port_t, rtk_enable_t); + rtk_api_ret_t (*svlan_dmac_vidsel_get)(rtk_port_t , rtk_enable_t *); + rtk_api_ret_t (*svlan_ipmc2s_add)(ipaddr_t, ipaddr_t, rtk_vlan_t); + rtk_api_ret_t (*svlan_ipmc2s_del)(ipaddr_t, ipaddr_t); + rtk_api_ret_t (*svlan_ipmc2s_get)(ipaddr_t, ipaddr_t, rtk_vlan_t *); + rtk_api_ret_t (*svlan_l2mc2s_add)(rtk_mac_t, rtk_mac_t, rtk_vlan_t); + rtk_api_ret_t (*svlan_l2mc2s_del)(rtk_mac_t, rtk_mac_t); + rtk_api_ret_t (*svlan_l2mc2s_get)(rtk_mac_t, rtk_mac_t, rtk_vlan_t *); + rtk_api_ret_t (*svlan_sp2c_add)(rtk_vlan_t, rtk_port_t, rtk_vlan_t); + rtk_api_ret_t (*svlan_sp2c_get)(rtk_vlan_t, rtk_port_t, rtk_vlan_t *); + rtk_api_ret_t (*svlan_sp2c_del)(rtk_vlan_t, rtk_port_t); + rtk_api_ret_t (*svlan_lookupType_set)(rtk_svlan_lookupType_t); + rtk_api_ret_t (*svlan_lookupType_get)(rtk_svlan_lookupType_t *); + rtk_api_ret_t (*svlan_trapPri_set)(rtk_pri_t); + rtk_api_ret_t (*svlan_trapPri_get)(rtk_pri_t *); + rtk_api_ret_t (*svlan_unassign_action_set)(rtk_svlan_unassign_action_t); + rtk_api_ret_t (*svlan_unassign_action_get)(rtk_svlan_unassign_action_t *); + + /*RLDP*/ + rtk_api_ret_t (*rldp_config_set)(rtk_rldp_config_t *); + rtk_api_ret_t (*rldp_config_get)(rtk_rldp_config_t *); + rtk_api_ret_t (*rldp_portConfig_set)(rtk_port_t, rtk_rldp_portConfig_t *); + rtk_api_ret_t (*rldp_portConfig_get)(rtk_port_t, rtk_rldp_portConfig_t *); + rtk_api_ret_t (*rldp_status_get)(rtk_rldp_status_t *); + rtk_api_ret_t (*rldp_portStatus_get)(rtk_port_t, rtk_rldp_portStatus_t *); + rtk_api_ret_t (*rldp_portStatus_set)(rtk_port_t, rtk_rldp_portStatus_t *); + rtk_api_ret_t (*rldp_portLoopPair_get)(rtk_port_t, rtk_portmask_t *); + + /*trunk*/ + rtk_api_ret_t (*trunk_port_set)(rtk_trunk_group_t, rtk_portmask_t *); + rtk_api_ret_t (*trunk_port_get)(rtk_trunk_group_t, rtk_portmask_t *); + rtk_api_ret_t (*trunk_distributionAlgorithm_set)(rtk_trunk_group_t, rtk_uint32); + rtk_api_ret_t (*trunk_distributionAlgorithm_get)(rtk_trunk_group_t, rtk_uint32 *); + rtk_api_ret_t (*trunk_trafficSeparate_set)(rtk_trunk_group_t, rtk_trunk_separateType_t); + rtk_api_ret_t (*trunk_trafficSeparate_get)(rtk_trunk_group_t, rtk_trunk_separateType_t *); + rtk_api_ret_t (*trunk_mode_set)(rtk_trunk_mode_t); + rtk_api_ret_t (*trunk_mode_get)(rtk_trunk_mode_t *); + rtk_api_ret_t (*trunk_trafficPause_set)(rtk_trunk_group_t, rtk_enable_t); + rtk_api_ret_t (*trunk_trafficPause_get)(rtk_trunk_group_t, rtk_enable_t *); + rtk_api_ret_t (*trunk_hashMappingTable_set)(rtk_trunk_group_t, rtk_trunk_hashVal2Port_t *); + rtk_api_ret_t (*trunk_hashMappingTable_get)(rtk_trunk_group_t, rtk_trunk_hashVal2Port_t *); + rtk_api_ret_t (*trunk_portQueueEmpty_get)(rtk_portmask_t *); + + /*leaky*/ + rtk_api_ret_t (*leaky_vlan_set)(rtk_leaky_type_t, rtk_enable_t); + rtk_api_ret_t (*leaky_vlan_get)(rtk_leaky_type_t, rtk_enable_t *); + rtk_api_ret_t (*leaky_portIsolation_set)(rtk_leaky_type_t, rtk_enable_t); + rtk_api_ret_t (*leaky_portIsolation_get)(rtk_leaky_type_t, rtk_enable_t *); + + /*GPIO*/ + rtk_api_ret_t (*gpio_input_get)(rtk_uint32, rtk_uint32 *); + rtk_api_ret_t (*gpio_output_set)(rtk_uint32, rtk_uint32); + rtk_api_ret_t (*gpio_output_get)(rtk_uint32, rtk_uint32 *); + rtk_api_ret_t (*gpio_state_set)(rtk_uint32, rtk_enable_t); + rtk_api_ret_t (*gpio_state_get)(rtk_uint32, rtk_enable_t *); + rtk_api_ret_t (*gpio_mode_set)(rtk_uint32, rtk_gpio_mode_t); + rtk_api_ret_t (*gpio_mode_get)(rtk_uint32, rtk_gpio_mode_t *); + rtk_api_ret_t (*gpio_aclEnClear_set)(rtk_uint32); + rtk_api_ret_t (*gpio_aclEnClear_get)(rtk_uint32, rtk_enable_t *); + + /*ASIC*/ + rtk_api_ret_t (*asic_setAsicReg)(rtk_uint32, rtk_uint32); + rtk_api_ret_t (*asic_getAsicReg)(rtk_uint32, rtk_uint32 *); + rtk_api_ret_t (*asic_setAsicPHYOCPReg)(rtk_uint32, rtk_uint32, rtk_uint32); + rtk_api_ret_t (*asic_getAsicPHYOCPReg)(rtk_uint32, rtk_uint32, rtk_uint32 *); + rtk_api_ret_t (*asic_setAsicPHYReg)(rtk_uint32, rtk_uint32, rtk_uint32); + rtk_api_ret_t (*asic_getAsicPHYReg)(rtk_uint32, rtk_uint32, rtk_uint32 *); + +} dal_mapper_t; + + +#endif /* __DAL_MAPPER_H __ */ diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/dal_mgmt.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/dal_mgmt.c new file mode 100644 index 00000000..d079b6c6 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/dal_mgmt.c @@ -0,0 +1,74 @@ +/* + * Copyright (C) 2009 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + */ + +/* + * Include Files + */ +#if (!defined(CONFIG_DAL_RTL8367C) && !defined(CONFIG_DAL_RTL8367D)) +#define CONFIG_DAL_ALL +#endif + +#include +#include +#if defined(CONFIG_DAL_RTL8367C) || defined(CONFIG_DAL_ALL) +#include +#endif +#if defined(CONFIG_DAL_RTL8367D) || defined(CONFIG_DAL_ALL) +#include +#endif +#include + +dal_mgmt_info_t Mgmt_node; +dal_mgmt_info_t *pMgmt_node = &Mgmt_node; + +static dal_mapper_info_t dal_mapper_database[] = +{ + + {CHIP_RTL8367C, NULL}, + {CHIP_RTL8370B, NULL}, + {CHIP_RTL8364B, NULL}, + {CHIP_RTL8363SC_VB, NULL}, + {CHIP_RTL8367D, NULL}, +}; + +rtk_int32 dal_mgmt_attachDevice(switch_chip_t switchChip) +{ + rtk_uint32 mapper_size = sizeof(dal_mapper_database)/sizeof(dal_mapper_info_t); + rtk_uint32 mapper_index; + + /*mapper init*/ + for (mapper_index = 0; mapper_index < mapper_size; mapper_index++) + { + if (switchChip == dal_mapper_database[mapper_index].switchChip) + { +#if defined(CONFIG_DAL_RTL8367C) || defined(CONFIG_DAL_ALL) + if ((switchChip == CHIP_RTL8367C) || (switchChip == CHIP_RTL8370B) || (switchChip == CHIP_RTL8364B) || (switchChip == CHIP_RTL8363SC_VB)) + { + dal_mapper_database[mapper_index].pMapper = dal_rtl8367c_mapper_get(); + pMgmt_node->pMapper = dal_mapper_database[mapper_index].pMapper; + return RT_ERR_OK; + } +#endif +#if defined(CONFIG_DAL_RTL8367D) || defined(CONFIG_DAL_ALL) + if (switchChip == CHIP_RTL8367D) + { + dal_mapper_database[mapper_index].pMapper = dal_rtl8367d_mapper_get(); + pMgmt_node->pMapper = dal_mapper_database[mapper_index].pMapper; + return RT_ERR_OK; + } +#endif + } + } + + return RT_ERR_CHIP_NOT_SUPPORTED; +} diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/dal_mgmt.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/dal_mgmt.h new file mode 100644 index 00000000..360ae00b --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/dal_mgmt.h @@ -0,0 +1,81 @@ + +/* + * Copyright (C) 2011 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : Use to Management each device + * + * Feature : The file have include the following module and sub-modules + * 1) Initialize system + * 2) Initialize device + * 3) Mangement Devices + * + */ +#ifndef __DAL_MGMT_H__ +#define __DAL_MGMT_H__ + +/* + * Include Files + */ +#include +#include +#include + +/* + * Symbol Definition + */ +typedef struct dal_mgmt_info_s +{ + dal_mapper_t *pMapper; +} dal_mgmt_info_t; + +typedef struct dal_mapper_info_s +{ + switch_chip_t switchChip; + dal_mapper_t *pMapper; +} dal_mapper_info_t; + +/* + * Data Declaration + */ +extern dal_mgmt_info_t *pMgmt_node; + +/* + * Macro Definition + */ +#define RT_MGMT pMgmt_node +#define RT_MAPPER RT_MGMT->pMapper + +/* + * Function Declaration + */ + +/* Module Name : */ + +/* Function Name: + * dal_mgmt_attachDevice + * Description: + * Attach device(semaphore, database clear) + * Input: + * switchChip - switch type + * Output: + * None + * Return: + * RT_ERR_FAILED - initialize fail + * RT_ERR_OK - initialize success + * Note: + * RTK must call this function before do other kind of action. + */ +extern rtk_int32 +dal_mgmt_attachDevice(switch_chip_t switchChip); + +#endif /* __DAL_MGMT_H__ */ + + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/Makefile b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/Makefile new file mode 100644 index 00000000..6d317fa1 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/Makefile @@ -0,0 +1,24 @@ +LOC_DIR=src/hsl/phy/rtl8367_common_V1_4_2/dal/rtl8367c +LIB=HSL + +include $(PRJ_PATH)/make/config.mk + +SRC_LIST += dal_rtl8367c_mapper.c dal_rtl8367c_acl.c dal_rtl8367c_cpu.c dal_rtl8367c_dot1x.c dal_rtl8367c_eee.c dal_rtl8367c_gpio.c \ + dal_rtl8367c_i2c.c dal_rtl8367c_igmp.c dal_rtl8367c_interrupt.c dal_rtl8367c_l2.c dal_rtl8367c_leaky.c dal_rtl8367c_led.c \ + dal_rtl8367c_mirror.c dal_rtl8367c_oam.c dal_rtl8367c_port.c dal_rtl8367c_ptp.c dal_rtl8367c_qos.c dal_rtl8367c_rate.c dal_rtl8367c_rldp.c \ + dal_rtl8367c_stat.c dal_rtl8367c_storm.c dal_rtl8367c_svlan.c dal_rtl8367c_switch.c dal_rtl8367c_trap.c dal_rtl8367c_trunk.c \ + dal_rtl8367c_vlan.c rtl8367c_asicdrv.c rtl8367c_asicdrv_acl.c rtl8367c_asicdrv_cputag.c rtl8367c_asicdrv_dot1x.c rtl8367c_asicdrv_eav.c \ + rtl8367c_asicdrv_eee.c rtl8367c_asicdrv_fc.c rtl8367c_asicdrv_green.c rtl8367c_asicdrv_hsb.c rtl8367c_asicdrv_i2c.c rtl8367c_asicdrv_igmp.c \ + rtl8367c_asicdrv_inbwctrl.c rtl8367c_asicdrv_interrupt.c rtl8367c_asicdrv_led.c rtl8367c_asicdrv_lut.c rtl8367c_asicdrv_meter.c \ + rtl8367c_asicdrv_mib.c rtl8367c_asicdrv_mirror.c rtl8367c_asicdrv_misc.c rtl8367c_asicdrv_oam.c rtl8367c_asicdrv_phy.c rtl8367c_asicdrv_port.c \ + rtl8367c_asicdrv_portIsolation.c rtl8367c_asicdrv_qos.c rtl8367c_asicdrv_rldp.c rtl8367c_asicdrv_rma.c rtl8367c_asicdrv_scheduling.c \ + rtl8367c_asicdrv_storm.c rtl8367c_asicdrv_svlan.c rtl8367c_asicdrv_trunking.c rtl8367c_asicdrv_unknownMulticast.c rtl8367c_asicdrv_vlan.c \ + rtl8367c_smi.c + +EXTRA_CFLAGS += -DMDC_MDIO_OPERATION + +include $(PRJ_PATH)/make/components.mk +include $(PRJ_PATH)/make/defs.mk +include $(PRJ_PATH)/make/target.mk + +all: dep obj diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_acl.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_acl.c new file mode 100644 index 00000000..09a1a3d7 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_acl.c @@ -0,0 +1,2061 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8367C + * Feature : Here is a list of all functions and variables in ACL module. + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +CONST_T rtk_uint8 filter_templateField[RTL8367C_ACLTEMPLATENO][RTL8367C_ACLRULEFIELDNO] = { + {ACL_DMAC0, ACL_DMAC1, ACL_DMAC2, ACL_SMAC0, ACL_SMAC1, ACL_SMAC2, ACL_ETHERTYPE, ACL_FIELD_SELECT15}, + {ACL_IP4SIP0, ACL_IP4SIP1, ACL_IP4DIP0, ACL_IP4DIP1, ACL_FIELD_SELECT13, ACL_FIELD_SELECT14, ACL_FIELD_SELECT02, ACL_FIELD_SELECT15}, + {ACL_IP6SIP0WITHIPV4, ACL_IP6SIP1WITHIPV4,ACL_FIELD_SELECT03, ACL_FIELD_SELECT04, ACL_FIELD_SELECT05, ACL_FIELD_SELECT06, ACL_FIELD_SELECT07, ACL_FIELD_SELECT08}, + {ACL_IP6DIP0WITHIPV4, ACL_IP6DIP1WITHIPV4,ACL_FIELD_SELECT09, ACL_FIELD_SELECT10, ACL_FIELD_SELECT11, ACL_FIELD_SELECT12, ACL_FIELD_SELECT13, ACL_FIELD_SELECT14}, + {ACL_VIDRANGE, ACL_IPRANGE, ACL_PORTRANGE, ACL_CTAG, ACL_STAG, ACL_FIELD_SELECT13, ACL_FIELD_SELECT14, ACL_FIELD_SELECT15} +}; + +CONST_T rtk_uint8 filter_advanceCaretagField[RTL8367C_ACLTEMPLATENO][2] = { + {TRUE, 7}, + {TRUE, 7}, + {FALSE, 0}, + {FALSE, 0}, + {TRUE, 7}, +}; + + +CONST_T rtk_uint8 filter_fieldTemplateIndex[FILTER_FIELD_END][RTK_FILTER_FIELD_USED_MAX] = { + {0x00, 0x01,0x02}, + {0x03, 0x04,0x05}, + {0x06}, + {0x43}, + {0x44}, + {0x10, 0x11}, + {0x12, 0x13}, + {0x24}, + {0x25}, + {0x35}, + {0x35}, + {0x20, 0x21,0x22,0x23}, + {0x30, 0x31,0x32,0x33}, + {0x26}, + {0x27}, + {0x14}, + {0x15}, + {0x16}, + {0x14}, + {0x15}, + {0x14}, + {0x14}, + {0x14}, + + {0x40}, + {0x41}, + {0x42}, + + {0x14}, + {0x15}, + {0x16}, + {0x22}, + {0x23}, + {0x24}, + {0x25}, + {0x26}, + {0x27}, + {0x32}, + {0x33}, + {0x34}, + {0x35}, + {0x36}, + {0x37}, + {0x47}, + + {0xFF} /* Pattern Match */ +}; + +CONST_T rtk_uint8 filter_fieldSize[FILTER_FIELD_END] = { + 3, 3, 1, 1, 1, + 2, 2, 1, 1, 1, 1, 4, 4, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 8 +}; + +CONST_T rtk_uint16 field_selector[RTL8367C_FIELDSEL_FORMAT_NUMBER][2] = +{ + {FIELDSEL_FORMAT_DEFAULT, 0}, /* Field Selector 0 */ + {FIELDSEL_FORMAT_DEFAULT, 0}, /* Field Selector 1 */ + {FIELDSEL_FORMAT_IPPAYLOAD, 12}, /* Field Selector 2 */ + {FIELDSEL_FORMAT_IPV6, 10}, /* Field Selector 3 */ + {FIELDSEL_FORMAT_IPV6, 8}, /* Field Selector 4 */ + {FIELDSEL_FORMAT_IPV4, 0}, /* Field Selector 5 */ + {FIELDSEL_FORMAT_IPV4, 8}, /* Field Selector 6 */ + {FIELDSEL_FORMAT_IPV6, 0}, /* Field Selector 7 */ + {FIELDSEL_FORMAT_IPV6, 6}, /* Field Selector 8 */ + {FIELDSEL_FORMAT_IPV6, 26}, /* Field Selector 9 */ + {FIELDSEL_FORMAT_IPV6, 24}, /* Field Selector 10 */ + {FIELDSEL_FORMAT_DEFAULT, 0}, /* Field Selector 11 */ + {FIELDSEL_FORMAT_IPV4, 6}, /* Field Selector 12 */ + {FIELDSEL_FORMAT_IPPAYLOAD, 0}, /* Field Selector 13 */ + {FIELDSEL_FORMAT_IPPAYLOAD, 2}, /* Field Selector 14 */ + {FIELDSEL_FORMAT_DEFAULT, 0} /* Field Selector 15 */ +}; + +/* Function Name: + * dal_rtl8367c_filter_igrAcl_cfg_delAll + * Description: + * Delete all ACL entries from ASIC + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This function delete all ACL configuration from ASIC. + */ +rtk_api_ret_t dal_rtl8367c_filter_igrAcl_cfg_delAll(void) +{ + rtk_uint32 i; + rtk_api_ret_t ret; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + for(i = 0; i < RTL8367C_ACLRULENO; i++) + { + if((ret = rtl8367c_setAsicAclActCtrl(i, FILTER_ENACT_INIT_MASK))!= RT_ERR_OK) + return ret; + if((ret = rtl8367c_setAsicAclNot(i, DISABLED)) != RT_ERR_OK ) + return ret; + } + + return rtl8367c_setAsicRegBit(RTL8367C_REG_ACL_RESET_CFG, RTL8367C_ACL_RESET_CFG_OFFSET, TRUE);; +} + + +/* Function Name: + * dal_rtl8367c_filter_igrAcl_init + * Description: + * ACL initialization function + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Pointer pFilter_field or pFilter_cfg point to NULL. + * Note: + * This function enable and intialize ACL function + */ +rtk_api_ret_t dal_rtl8367c_filter_igrAcl_init(void) +{ + rtl8367c_acltemplate_t aclTemp; + rtk_uint32 i, j; + rtk_api_ret_t ret; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if ((ret = dal_rtl8367c_filter_igrAcl_cfg_delAll()) != RT_ERR_OK) + return ret; + + for(i = 0; i < RTL8367C_ACLTEMPLATENO; i++) + { + for(j = 0; j < RTL8367C_ACLRULEFIELDNO;j++) + aclTemp.field[j] = filter_templateField[i][j]; + + if ((ret = rtl8367c_setAsicAclTemplate(i, &aclTemp)) != RT_ERR_OK) + return ret; + } + + for(i = 0; i < RTL8367C_FIELDSEL_FORMAT_NUMBER; i++) + { + if ((ret = rtl8367c_setAsicFieldSelector(i, field_selector[i][0], field_selector[i][1])) != RT_ERR_OK) + return ret; + } + + RTK_SCAN_ALL_PHY_PORTMASK(i) + { + if ((ret = rtl8367c_setAsicAcl(i, TRUE)) != RT_ERR_OK) + return ret; + + if ((ret = rtl8367c_setAsicAclUnmatchedPermit(i, TRUE)) != RT_ERR_OK) + return ret; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_filter_igrAcl_field_add + * Description: + * Add comparison rule to an ACL configuration + * Input: + * pFilter_cfg - The ACL configuration that this function will add comparison rule + * pFilter_field - The comparison rule that will be added. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Pointer pFilter_field or pFilter_cfg point to NULL. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This function add a comparison rule (*pFilter_field) to an ACL configuration (*pFilter_cfg). + * Pointer pFilter_cfg points to an ACL configuration structure, this structure keeps multiple ACL + * comparison rules by means of linked list. Pointer pFilter_field will be added to linked + * list keeped by structure that pFilter_cfg points to. + */ +rtk_api_ret_t dal_rtl8367c_filter_igrAcl_field_add(rtk_filter_cfg_t* pFilter_cfg, rtk_filter_field_t* pFilter_field) +{ + rtk_uint32 i; + rtk_filter_field_t *tailPtr; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pFilter_cfg || NULL == pFilter_field) + return RT_ERR_NULL_POINTER; + + if(pFilter_field->fieldType >= FILTER_FIELD_END) + return RT_ERR_ENTRY_INDEX; + + + if(0 == pFilter_field->fieldTemplateNo) + { + pFilter_field->fieldTemplateNo = filter_fieldSize[pFilter_field->fieldType]; + + for(i = 0; i < pFilter_field->fieldTemplateNo; i++) + { + pFilter_field->fieldTemplateIdx[i] = filter_fieldTemplateIndex[pFilter_field->fieldType][i]; + } + } + + if(NULL == pFilter_cfg->fieldHead) + { + pFilter_cfg->fieldHead = pFilter_field; + } + else + { + if (pFilter_cfg->fieldHead->next == NULL) + { + pFilter_cfg->fieldHead->next = pFilter_field; + } + else + { + tailPtr = pFilter_cfg->fieldHead->next; + while( tailPtr->next != NULL) + { + tailPtr = tailPtr->next; + } + tailPtr->next = pFilter_field; + } + } + + return RT_ERR_OK; +} + +static rtk_api_ret_t _rtk_filter_igrAcl_writeDataField(rtl8367c_aclrule *aclRule, rtk_filter_field_t *fieldPtr) +{ + rtk_uint32 i, tempIdx,fieldIdx, ipValue, ipMask; + rtk_uint32 ip6addr[RTK_IPV6_ADDR_WORD_LENGTH]; + rtk_uint32 ip6mask[RTK_IPV6_ADDR_WORD_LENGTH]; + + for(i = 0; i < fieldPtr->fieldTemplateNo; i++) + { + tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4; + + aclRule[tempIdx].valid = TRUE; + } + + switch (fieldPtr->fieldType) + { + /* use DMAC structure as representative for mac structure */ + case FILTER_FIELD_DMAC: + case FILTER_FIELD_SMAC: + + for(i = 0; i < fieldPtr->fieldTemplateNo; i++) + { + tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4; + fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F; + + aclRule[tempIdx].data_bits.field[fieldIdx] = fieldPtr->filter_pattern_union.mac.value.octet[5 - i*2] | (fieldPtr->filter_pattern_union.mac.value.octet[5 - (i*2 + 1)] << 8); + aclRule[tempIdx].care_bits.field[fieldIdx] = fieldPtr->filter_pattern_union.mac.mask.octet[5 - i*2] | (fieldPtr->filter_pattern_union.mac.mask.octet[5 - (i*2 + 1)] << 8); + } + break; + case FILTER_FIELD_ETHERTYPE: + for(i = 0; i < fieldPtr->fieldTemplateNo; i++) + { + tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4; + fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F; + + aclRule[tempIdx].data_bits.field[fieldIdx] = fieldPtr->filter_pattern_union.etherType.value; + aclRule[tempIdx].care_bits.field[fieldIdx] = fieldPtr->filter_pattern_union.etherType.mask; + } + break; + case FILTER_FIELD_IPV4_SIP: + case FILTER_FIELD_IPV4_DIP: + + ipValue = fieldPtr->filter_pattern_union.sip.value; + ipMask = fieldPtr->filter_pattern_union.sip.mask; + + for(i = 0; i < fieldPtr->fieldTemplateNo; i++) + { + tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4; + fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F; + + aclRule[tempIdx].data_bits.field[fieldIdx] = (0xFFFF & (ipValue >> (i*16))); + aclRule[tempIdx].care_bits.field[fieldIdx] = (0xFFFF & (ipMask >> (i*16))); + } + break; + case FILTER_FIELD_IPV4_TOS: + for(i = 0; i < fieldPtr->fieldTemplateNo; i++) + { + tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4; + fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F; + + aclRule[tempIdx].data_bits.field[fieldIdx] = fieldPtr->filter_pattern_union.ipTos.value & 0xFF; + aclRule[tempIdx].care_bits.field[fieldIdx] = fieldPtr->filter_pattern_union.ipTos.mask & 0xFF; + } + break; + case FILTER_FIELD_IPV4_PROTOCOL: + for(i = 0; i < fieldPtr->fieldTemplateNo; i++) + { + tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4; + fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F; + + aclRule[tempIdx].data_bits.field[fieldIdx] = fieldPtr->filter_pattern_union.protocol.value & 0xFF; + aclRule[tempIdx].care_bits.field[fieldIdx] = fieldPtr->filter_pattern_union.protocol.mask & 0xFF; + } + break; + case FILTER_FIELD_IPV6_SIPV6: + case FILTER_FIELD_IPV6_DIPV6: + for(i = 0; i < RTK_IPV6_ADDR_WORD_LENGTH; i++) + { + ip6addr[i] = fieldPtr->filter_pattern_union.sipv6.value.addr[i]; + ip6mask[i] = fieldPtr->filter_pattern_union.sipv6.mask.addr[i]; + } + + for(i = 0; i < fieldPtr->fieldTemplateNo; i++) + { + tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4; + fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F; + + if(i < 2) + { + aclRule[tempIdx].data_bits.field[fieldIdx] = ((ip6addr[0] & (0xFFFF << (i * 16))) >> (i * 16)); + aclRule[tempIdx].care_bits.field[fieldIdx] = ((ip6mask[0] & (0xFFFF << (i * 16))) >> (i * 16)); + } + else + { + /*default acl template for ipv6 address supports MSB 32-bits and LSB 32-bits only*/ + aclRule[tempIdx].data_bits.field[fieldIdx] = ((ip6addr[3] & (0xFFFF << ((i&1) * 16))) >> ((i&1) * 16)); + aclRule[tempIdx].care_bits.field[fieldIdx] = ((ip6mask[3] & (0xFFFF << ((i&1) * 16))) >> ((i&1) * 16)); + } + } + + break; + case FILTER_FIELD_CTAG: + case FILTER_FIELD_STAG: + + for(i = 0; i < fieldPtr->fieldTemplateNo; i++) + { + tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4; + fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F; + + aclRule[tempIdx].data_bits.field[fieldIdx] = (fieldPtr->filter_pattern_union.l2tag.pri.value << 13) | (fieldPtr->filter_pattern_union.l2tag.cfi.value << 12) | fieldPtr->filter_pattern_union.l2tag.vid.value; + aclRule[tempIdx].care_bits.field[fieldIdx] = (fieldPtr->filter_pattern_union.l2tag.pri.mask << 13) | (fieldPtr->filter_pattern_union.l2tag.cfi.mask << 12) | fieldPtr->filter_pattern_union.l2tag.vid.mask; + } + break; + case FILTER_FIELD_IPV4_FLAG: + + for(i = 0; i < fieldPtr->fieldTemplateNo; i++) + { + tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4; + fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F; + + aclRule[tempIdx].data_bits.field[fieldIdx] &= 0x1FFF; + aclRule[tempIdx].data_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.ipFlag.xf.value << 15); + aclRule[tempIdx].data_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.ipFlag.df.value << 14); + aclRule[tempIdx].data_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.ipFlag.mf.value << 13); + + aclRule[tempIdx].care_bits.field[fieldIdx] &= 0x1FFF; + aclRule[tempIdx].care_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.ipFlag.xf.mask << 15); + aclRule[tempIdx].care_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.ipFlag.df.mask << 14); + aclRule[tempIdx].care_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.ipFlag.mf.mask << 13); + } + + break; + case FILTER_FIELD_IPV4_OFFSET: + + for(i = 0; i < fieldPtr->fieldTemplateNo; i++) + { + tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4; + fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F; + + aclRule[tempIdx].data_bits.field[fieldIdx] &= 0xE000; + aclRule[tempIdx].data_bits.field[fieldIdx] |= fieldPtr->filter_pattern_union.inData.value; + + aclRule[tempIdx].care_bits.field[fieldIdx] &= 0xE000; + aclRule[tempIdx].care_bits.field[fieldIdx] |= fieldPtr->filter_pattern_union.inData.mask; + } + + break; + + case FILTER_FIELD_IPV6_TRAFFIC_CLASS: + for(i = 0; i < fieldPtr->fieldTemplateNo; i++) + { + tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4; + fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F; + + + aclRule[tempIdx].data_bits.field[fieldIdx] = (fieldPtr->filter_pattern_union.inData.value << 4)&0x0FF0; + aclRule[tempIdx].care_bits.field[fieldIdx] = (fieldPtr->filter_pattern_union.inData.mask << 4)&0x0FF0; + } + break; + case FILTER_FIELD_IPV6_NEXT_HEADER: + for(i = 0; i < fieldPtr->fieldTemplateNo; i++) + { + tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4; + fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F; + + aclRule[tempIdx].data_bits.field[fieldIdx] = fieldPtr->filter_pattern_union.inData.value << 8; + aclRule[tempIdx].care_bits.field[fieldIdx] = fieldPtr->filter_pattern_union.inData.mask << 8; + } + break; + case FILTER_FIELD_TCP_SPORT: + for(i = 0; i < fieldPtr->fieldTemplateNo; i++) + { + tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4; + fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F; + + aclRule[tempIdx].data_bits.field[fieldIdx] = fieldPtr->filter_pattern_union.tcpSrcPort.value; + aclRule[tempIdx].care_bits.field[fieldIdx] = fieldPtr->filter_pattern_union.tcpSrcPort.mask; + } + break; + case FILTER_FIELD_TCP_DPORT: + for(i = 0; i < fieldPtr->fieldTemplateNo; i++) + { + tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4; + fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F; + + aclRule[tempIdx].data_bits.field[fieldIdx] = fieldPtr->filter_pattern_union.tcpDstPort.value; + aclRule[tempIdx].care_bits.field[fieldIdx] = fieldPtr->filter_pattern_union.tcpDstPort.mask; + } + break; + case FILTER_FIELD_TCP_FLAG: + + for(i = 0; i < fieldPtr->fieldTemplateNo; i++) + { + tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4; + fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F; + + aclRule[tempIdx].data_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.tcpFlag.cwr.value << 7); + aclRule[tempIdx].data_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.tcpFlag.ece.value << 6); + aclRule[tempIdx].data_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.tcpFlag.urg.value << 5); + aclRule[tempIdx].data_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.tcpFlag.ack.value << 4); + aclRule[tempIdx].data_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.tcpFlag.psh.value << 3); + aclRule[tempIdx].data_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.tcpFlag.rst.value << 2); + aclRule[tempIdx].data_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.tcpFlag.syn.value << 1); + aclRule[tempIdx].data_bits.field[fieldIdx] |= fieldPtr->filter_pattern_union.tcpFlag.fin.value; + + aclRule[tempIdx].care_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.tcpFlag.cwr.mask << 7); + aclRule[tempIdx].care_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.tcpFlag.ece.mask << 6); + aclRule[tempIdx].care_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.tcpFlag.urg.mask << 5); + aclRule[tempIdx].care_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.tcpFlag.ack.mask << 4); + aclRule[tempIdx].care_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.tcpFlag.psh.mask << 3); + aclRule[tempIdx].care_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.tcpFlag.rst.mask << 2); + aclRule[tempIdx].care_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.tcpFlag.syn.mask << 1); + aclRule[tempIdx].care_bits.field[fieldIdx] |= fieldPtr->filter_pattern_union.tcpFlag.fin.mask; + } + break; + case FILTER_FIELD_UDP_SPORT: + for(i = 0; i < fieldPtr->fieldTemplateNo; i++) + { + tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4; + fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F; + + aclRule[tempIdx].data_bits.field[fieldIdx] = fieldPtr->filter_pattern_union.udpSrcPort.value; + aclRule[tempIdx].care_bits.field[fieldIdx] = fieldPtr->filter_pattern_union.udpSrcPort.mask; + } + break; + case FILTER_FIELD_UDP_DPORT: + for(i = 0; i < fieldPtr->fieldTemplateNo; i++) + { + tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4; + fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F; + + aclRule[tempIdx].data_bits.field[fieldIdx] = fieldPtr->filter_pattern_union.udpDstPort.value; + aclRule[tempIdx].care_bits.field[fieldIdx] = fieldPtr->filter_pattern_union.udpDstPort.mask; + } + break; + case FILTER_FIELD_ICMP_CODE: + for(i = 0; i < fieldPtr->fieldTemplateNo; i++) + { + tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4; + fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F; + + aclRule[tempIdx].data_bits.field[fieldIdx] &= 0xFF00; + aclRule[tempIdx].data_bits.field[fieldIdx] |= fieldPtr->filter_pattern_union.icmpCode.value; + aclRule[tempIdx].care_bits.field[fieldIdx] &= 0xFF00; + aclRule[tempIdx].care_bits.field[fieldIdx] |= fieldPtr->filter_pattern_union.icmpCode.mask; + } + break; + case FILTER_FIELD_ICMP_TYPE: + for(i = 0; i < fieldPtr->fieldTemplateNo; i++) + { + tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4; + fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F; + + aclRule[tempIdx].data_bits.field[fieldIdx] &= 0x00FF; + aclRule[tempIdx].data_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.icmpType.value << 8); + aclRule[tempIdx].care_bits.field[fieldIdx] &= 0x00FF; + aclRule[tempIdx].care_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.icmpType.mask << 8); + } + break; + case FILTER_FIELD_IGMP_TYPE: + for(i = 0; i < fieldPtr->fieldTemplateNo; i++) + { + tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4; + fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F; + + aclRule[tempIdx].data_bits.field[fieldIdx] = (fieldPtr->filter_pattern_union.igmpType.value << 8); + aclRule[tempIdx].care_bits.field[fieldIdx] = (fieldPtr->filter_pattern_union.igmpType.mask << 8); + } + break; + case FILTER_FIELD_PATTERN_MATCH: + for(i = 0; i < fieldPtr->fieldTemplateNo; i++) + { + tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4; + fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F; + + aclRule[tempIdx].data_bits.field[fieldIdx] = ((fieldPtr->filter_pattern_union.pattern.value[i/2] >> (16 * (i%2))) & 0x0000FFFF ); + aclRule[tempIdx].care_bits.field[fieldIdx] = ((fieldPtr->filter_pattern_union.pattern.mask[i/2] >> (16 * (i%2))) & 0x0000FFFF ); + } + break; + case FILTER_FIELD_VID_RANGE: + case FILTER_FIELD_IP_RANGE: + case FILTER_FIELD_PORT_RANGE: + default: + tempIdx = (fieldPtr->fieldTemplateIdx[0] & 0xF0) >> 4; + fieldIdx = fieldPtr->fieldTemplateIdx[0] & 0x0F; + + aclRule[tempIdx].data_bits.field[fieldIdx] = fieldPtr->filter_pattern_union.inData.value; + aclRule[tempIdx].care_bits.field[fieldIdx] = fieldPtr->filter_pattern_union.inData.mask; + break; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_filter_igrAcl_cfg_add + * Description: + * Add an ACL configuration to ASIC + * Input: + * filter_id - Start index of ACL configuration. + * pFilter_cfg - The ACL configuration that this function will add comparison rule + * pFilter_action - Action(s) of ACL configuration. + * Output: + * ruleNum - number of rules written in acl table + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Pointer pFilter_field or pFilter_cfg point to NULL. + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_ENTRY_INDEX - Invalid filter_id . + * RT_ERR_NULL_POINTER - Pointer pFilter_action or pFilter_cfg point to NULL. + * RT_ERR_FILTER_INACL_ACT_NOT_SUPPORT - Action is not supported in this chip. + * RT_ERR_FILTER_INACL_RULE_NOT_SUPPORT - Rule is not supported. + * Note: + * This function store pFilter_cfg, pFilter_action into ASIC. The starting + * index(es) is filter_id. + */ +rtk_api_ret_t dal_rtl8367c_filter_igrAcl_cfg_add(rtk_filter_id_t filter_id, rtk_filter_cfg_t* pFilter_cfg, rtk_filter_action_t* pFilter_action, rtk_filter_number_t *ruleNum) +{ + rtk_api_ret_t retVal; + rtk_uint32 careTagData, careTagMask; + rtk_uint32 i,vidx, svidx, actType, ruleId; + rtk_uint32 aclActCtrl; + rtk_uint32 cpuPort; + rtk_filter_field_t* fieldPtr; + rtl8367c_aclrule aclRule[RTL8367C_ACLTEMPLATENO]; + rtl8367c_aclrule tempRule; + rtl8367c_acl_act_t aclAct; + rtk_uint32 noRulesAdd; + rtk_uint32 portmask; + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(filter_id > RTL8367C_ACLRULEMAX ) + return RT_ERR_ENTRY_INDEX; + + if((NULL == pFilter_cfg) || (NULL == pFilter_action) || (NULL == ruleNum)) + return RT_ERR_NULL_POINTER; + + fieldPtr = pFilter_cfg->fieldHead; + + /* init RULE */ + for(i = 0; i < RTL8367C_ACLTEMPLATENO; i++) + { + memset(&aclRule[i], 0, sizeof(rtl8367c_aclrule)); + + aclRule[i].data_bits.type= i; + aclRule[i].care_bits.type= 0x7; + } + + while(NULL != fieldPtr) + { + _rtk_filter_igrAcl_writeDataField(aclRule, fieldPtr); + + fieldPtr = fieldPtr->next; + } + + /*set care tag mask in User Defined Field 15*/ + /*Follow care tag should not be used while ACL template and User defined fields are fully control by system designer*/ + /*those advanced packet type care tag is used in default template design structure only*/ + careTagData = 0; + careTagMask = 0; + + for(i = CARE_TAG_TCP; i < CARE_TAG_END; i++) + { + if(pFilter_cfg->careTag.tagType[i].mask) + careTagMask = careTagMask | (1 << (i-CARE_TAG_TCP)); + + if(pFilter_cfg->careTag.tagType[i].value) + careTagData = careTagData | (1 << (i-CARE_TAG_TCP)); + } + + if(careTagData || careTagMask) + { + i = 0; + while(i < RTL8367C_ACLTEMPLATENO) + { + if(aclRule[i].valid == 1 && filter_advanceCaretagField[i][0] == TRUE) + { + + aclRule[i].data_bits.field[filter_advanceCaretagField[i][1]] = careTagData & 0xFFFF; + aclRule[i].care_bits.field[filter_advanceCaretagField[i][1]] = careTagMask & 0xFFFF; + break; + } + i++; + } + /*none of previous used template containing field 15*/ + if(i == RTL8367C_ACLTEMPLATENO) + { + i = 0; + while(i < RTL8367C_ACLTEMPLATENO) + { + if(filter_advanceCaretagField[i][0] == TRUE) + { + aclRule[i].data_bits.field[filter_advanceCaretagField[i][1]] = careTagData & 0xFFFF; + aclRule[i].care_bits.field[filter_advanceCaretagField[i][1]] = careTagMask & 0xFFFF; + aclRule[i].valid = 1; + break; + } + i++; + } + } + } + + /*Check rule number*/ + noRulesAdd = 0; + for(i = 0; i < RTL8367C_ACLTEMPLATENO; i++) + { + if(1 == aclRule[i].valid) + { + noRulesAdd ++; + } + } + + *ruleNum = noRulesAdd; + + if((filter_id + noRulesAdd - 1) > RTL8367C_ACLRULEMAX) + { + return RT_ERR_ENTRY_INDEX; + } + + /*set care tag mask in TAG Indicator*/ + careTagData = 0; + careTagMask = 0; + + for(i = 0; i <= CARE_TAG_IPV6;i++) + { + if(0 == pFilter_cfg->careTag.tagType[i].mask ) + { + careTagMask &= ~(1 << i); + } + else + { + careTagMask |= (1 << i); + if(0 == pFilter_cfg->careTag.tagType[i].value ) + careTagData &= ~(1 << i); + else + careTagData |= (1 << i); + } + } + + for(i = 0; i < RTL8367C_ACLTEMPLATENO; i++) + { + aclRule[i].data_bits.tag_exist = (careTagData) & ACL_RULE_CARETAG_MASK; + aclRule[i].care_bits.tag_exist = (careTagMask) & ACL_RULE_CARETAG_MASK; + } + + RTK_CHK_PORTMASK_VALID(&pFilter_cfg->activeport.value); + RTK_CHK_PORTMASK_VALID(&pFilter_cfg->activeport.mask); + + for(i = 0; i < RTL8367C_ACLTEMPLATENO; i++) + { + if(TRUE == aclRule[i].valid) + { + if(rtk_switch_portmask_L2P_get(&pFilter_cfg->activeport.value, &portmask) != RT_ERR_OK) + return RT_ERR_PORT_MASK; + + aclRule[i].data_bits.active_portmsk = portmask; + + if(rtk_switch_portmask_L2P_get(&pFilter_cfg->activeport.mask, &portmask) != RT_ERR_OK) + return RT_ERR_PORT_MASK; + + aclRule[i].care_bits.active_portmsk = portmask; + } + } + + if(pFilter_cfg->invert >= FILTER_INVERT_END ) + return RT_ERR_INPUT; + + + /*Last action gets high priority if actions are the same*/ + memset(&aclAct, 0, sizeof(rtl8367c_acl_act_t)); + aclActCtrl = 0; + for(actType = 0; actType < FILTER_ENACT_END; actType ++) + { + if(pFilter_action->actEnable[actType]) + { + switch (actType) + { + case FILTER_ENACT_CVLAN_INGRESS: + if(pFilter_action->filterCvlanVid > RTL8367C_EVIDMAX) + return RT_ERR_INPUT; + + if((retVal = dal_rtl8367c_vlan_checkAndCreateMbr(pFilter_action->filterCvlanVid, &vidx)) != RT_ERR_OK) + { + return retVal; + } + aclAct.cact = FILTER_ENACT_CVLAN_TYPE(actType); + aclAct.cvidx_cact = vidx; + + if(aclActCtrl &(FILTER_ENACT_CVLAN_MASK)) + { + if(aclAct.cact_ext == FILTER_ENACT_CACTEXT_TAGONLY) + aclAct.cact_ext = FILTER_ENACT_CACTEXT_BOTHVLANTAG; + } + else + { + aclAct.cact_ext = FILTER_ENACT_CACTEXT_VLANONLY; + } + + aclActCtrl |= FILTER_ENACT_CVLAN_MASK; + break; + case FILTER_ENACT_CVLAN_EGRESS: + if(pFilter_action->filterCvlanVid > RTL8367C_EVIDMAX) + return RT_ERR_INPUT; + + if((retVal = dal_rtl8367c_vlan_checkAndCreateMbr(pFilter_action->filterCvlanVid, &vidx)) != RT_ERR_OK) + return retVal; + + aclAct.cact = FILTER_ENACT_CVLAN_TYPE(actType); + aclAct.cvidx_cact = vidx; + + if(aclActCtrl &(FILTER_ENACT_CVLAN_MASK)) + { + if(aclAct.cact_ext == FILTER_ENACT_CACTEXT_TAGONLY) + aclAct.cact_ext = FILTER_ENACT_CACTEXT_BOTHVLANTAG; + } + else + { + aclAct.cact_ext = FILTER_ENACT_CACTEXT_VLANONLY; + } + + aclActCtrl |= FILTER_ENACT_CVLAN_MASK; + break; + case FILTER_ENACT_CVLAN_SVID: + + aclAct.cact = FILTER_ENACT_CVLAN_TYPE(actType); + + if(aclActCtrl &(FILTER_ENACT_CVLAN_MASK)) + { + if(aclAct.cact_ext == FILTER_ENACT_CACTEXT_TAGONLY) + aclAct.cact_ext = FILTER_ENACT_CACTEXT_BOTHVLANTAG; + } + else + { + aclAct.cact_ext = FILTER_ENACT_CACTEXT_VLANONLY; + } + + aclActCtrl |= FILTER_ENACT_CVLAN_MASK; + break; + case FILTER_ENACT_POLICING_1: + if(pFilter_action->filterPolicingIdx[1] >= ((RTK_MAX_METER_ID + 1) + RTL8367C_MAX_LOG_CNT_NUM)) + return RT_ERR_INPUT; + + aclAct.cact = FILTER_ENACT_CVLAN_TYPE(actType); + aclAct.cvidx_cact = pFilter_action->filterPolicingIdx[1]; + + if(aclActCtrl &(FILTER_ENACT_CVLAN_MASK)) + { + if(aclAct.cact_ext == FILTER_ENACT_CACTEXT_TAGONLY) + aclAct.cact_ext = FILTER_ENACT_CACTEXT_BOTHVLANTAG; + } + else + { + aclAct.cact_ext = FILTER_ENACT_CACTEXT_VLANONLY; + } + + aclActCtrl |= FILTER_ENACT_CVLAN_MASK; + break; + + case FILTER_ENACT_SVLAN_INGRESS: + case FILTER_ENACT_SVLAN_EGRESS: + + if((retVal = dal_rtl8367c_svlan_checkAndCreateMbr(pFilter_action->filterSvlanVid, &svidx)) != RT_ERR_OK) + return retVal; + + aclAct.sact = FILTER_ENACT_SVLAN_TYPE(actType); + aclAct.svidx_sact = svidx; + aclActCtrl |= FILTER_ENACT_SVLAN_MASK; + break; + case FILTER_ENACT_SVLAN_CVID: + + aclAct.sact = FILTER_ENACT_SVLAN_TYPE(actType); + aclActCtrl |= FILTER_ENACT_SVLAN_MASK; + break; + case FILTER_ENACT_POLICING_2: + if(pFilter_action->filterPolicingIdx[2] >= ((RTK_MAX_METER_ID + 1) + RTL8367C_MAX_LOG_CNT_NUM)) + return RT_ERR_INPUT; + + aclAct.sact = FILTER_ENACT_SVLAN_TYPE(actType); + aclAct.svidx_sact = pFilter_action->filterPolicingIdx[2]; + aclActCtrl |= FILTER_ENACT_SVLAN_MASK; + break; + case FILTER_ENACT_POLICING_0: + if(pFilter_action->filterPolicingIdx[0] >= ((RTK_MAX_METER_ID + 1) + RTL8367C_MAX_LOG_CNT_NUM)) + return RT_ERR_INPUT; + + aclAct.aclmeteridx = pFilter_action->filterPolicingIdx[0]; + aclActCtrl |= FILTER_ENACT_POLICING_MASK; + break; + case FILTER_ENACT_PRIORITY: + case FILTER_ENACT_1P_REMARK: + if(pFilter_action->filterPriority > RTL8367C_PRIMAX) + return RT_ERR_INPUT; + + aclAct.priact = FILTER_ENACT_PRI_TYPE(actType); + aclAct.pridx = pFilter_action->filterPriority; + aclActCtrl |= FILTER_ENACT_PRIORITY_MASK; + break; + case FILTER_ENACT_DSCP_REMARK: + if(pFilter_action->filterPriority > RTL8367C_DSCPMAX) + return RT_ERR_INPUT; + + aclAct.priact = FILTER_ENACT_PRI_TYPE(actType); + aclAct.pridx = pFilter_action->filterPriority; + aclActCtrl |= FILTER_ENACT_PRIORITY_MASK; + break; + case FILTER_ENACT_POLICING_3: + if(pFilter_action->filterPriority >= ((RTK_MAX_METER_ID + 1) + RTL8367C_MAX_LOG_CNT_NUM)) + return RT_ERR_INPUT; + + aclAct.priact = FILTER_ENACT_PRI_TYPE(actType); + aclAct.pridx = pFilter_action->filterPolicingIdx[3]; + aclActCtrl |= FILTER_ENACT_PRIORITY_MASK; + break; + case FILTER_ENACT_DROP: + + aclAct.fwdact = FILTER_ENACT_FWD_TYPE(FILTER_ENACT_REDIRECT); + aclAct.fwdact_ext = FALSE; + + aclAct.fwdpmask = 0; + aclActCtrl |= FILTER_ENACT_FWD_MASK; + break; + case FILTER_ENACT_REDIRECT: + RTK_CHK_PORTMASK_VALID(&pFilter_action->filterPortmask); + + aclAct.fwdact = FILTER_ENACT_FWD_TYPE(actType); + aclAct.fwdact_ext = FALSE; + + if(rtk_switch_portmask_L2P_get(&pFilter_action->filterPortmask, &portmask) != RT_ERR_OK) + return RT_ERR_PORT_MASK; + aclAct.fwdpmask = portmask; + + aclActCtrl |= FILTER_ENACT_FWD_MASK; + break; + + case FILTER_ENACT_ADD_DSTPORT: + RTK_CHK_PORTMASK_VALID(&pFilter_action->filterPortmask); + + aclAct.fwdact = FILTER_ENACT_FWD_TYPE(actType); + aclAct.fwdact_ext = FALSE; + + if(rtk_switch_portmask_L2P_get(&pFilter_action->filterPortmask, &portmask) != RT_ERR_OK) + return RT_ERR_PORT_MASK; + aclAct.fwdpmask = portmask; + + aclActCtrl |= FILTER_ENACT_FWD_MASK; + break; + case FILTER_ENACT_MIRROR: + RTK_CHK_PORTMASK_VALID(&pFilter_action->filterPortmask); + + aclAct.fwdact = FILTER_ENACT_FWD_TYPE(actType); + aclAct.cact_ext = FALSE; + + if(rtk_switch_portmask_L2P_get(&pFilter_action->filterPortmask, &portmask) != RT_ERR_OK) + return RT_ERR_PORT_MASK; + aclAct.fwdpmask = portmask; + + aclActCtrl |= FILTER_ENACT_FWD_MASK; + break; + case FILTER_ENACT_TRAP_CPU: + + aclAct.fwdact = FILTER_ENACT_FWD_TYPE(actType); + aclAct.fwdact_ext = FALSE; + + aclActCtrl |= FILTER_ENACT_FWD_MASK; + break; + case FILTER_ENACT_COPY_CPU: + if((retVal = rtl8367c_getAsicCputagTrapPort(&cpuPort)) != RT_ERR_OK) + return retVal; + + aclAct.fwdact = FILTER_ENACT_FWD_TYPE(FILTER_ENACT_MIRROR); + aclAct.fwdact_ext = FALSE; + + aclAct.fwdpmask = 1 << cpuPort; + aclActCtrl |= FILTER_ENACT_FWD_MASK; + break; + case FILTER_ENACT_ISOLATION: + RTK_CHK_PORTMASK_VALID(&pFilter_action->filterPortmask); + + aclAct.fwdact_ext = TRUE; + + if(rtk_switch_portmask_L2P_get(&pFilter_action->filterPortmask, &portmask) != RT_ERR_OK) + return RT_ERR_PORT_MASK; + aclAct.fwdpmask = portmask; + + aclActCtrl |= FILTER_ENACT_FWD_MASK; + break; + + case FILTER_ENACT_INTERRUPT: + + aclAct.aclint = TRUE; + aclActCtrl |= FILTER_ENACT_INTGPIO_MASK; + break; + case FILTER_ENACT_GPO: + + aclAct.gpio_en = TRUE; + aclAct.gpio_pin = pFilter_action->filterPin; + aclActCtrl |= FILTER_ENACT_INTGPIO_MASK; + break; + case FILTER_ENACT_EGRESSCTAG_TAG: + + if(aclActCtrl &(FILTER_ENACT_CVLAN_MASK)) + { + if(aclAct.cact_ext == FILTER_ENACT_CACTEXT_VLANONLY) + aclAct.cact_ext = FILTER_ENACT_CACTEXT_BOTHVLANTAG; + } + else + { + aclAct.cact_ext = FILTER_ENACT_CACTEXT_TAGONLY; + } + aclAct.tag_fmt = FILTER_CTAGFMT_TAG; + aclActCtrl |= FILTER_ENACT_CVLAN_MASK; + break; + case FILTER_ENACT_EGRESSCTAG_UNTAG: + + if(aclActCtrl &(FILTER_ENACT_CVLAN_MASK)) + { + if(aclAct.cact_ext == FILTER_ENACT_CACTEXT_VLANONLY) + aclAct.cact_ext = FILTER_ENACT_CACTEXT_BOTHVLANTAG; + } + else + { + aclAct.cact_ext = FILTER_ENACT_CACTEXT_TAGONLY; + } + aclAct.tag_fmt = FILTER_CTAGFMT_UNTAG; + aclActCtrl |= FILTER_ENACT_CVLAN_MASK; + break; + case FILTER_ENACT_EGRESSCTAG_KEEP: + + if(aclActCtrl &(FILTER_ENACT_CVLAN_MASK)) + { + if(aclAct.cact_ext == FILTER_ENACT_CACTEXT_VLANONLY) + aclAct.cact_ext = FILTER_ENACT_CACTEXT_BOTHVLANTAG; + } + else + { + aclAct.cact_ext = FILTER_ENACT_CACTEXT_TAGONLY; + } + aclAct.tag_fmt = FILTER_CTAGFMT_KEEP; + aclActCtrl |= FILTER_ENACT_CVLAN_MASK; + break; + case FILTER_ENACT_EGRESSCTAG_KEEPAND1PRMK: + + if(aclActCtrl &(FILTER_ENACT_CVLAN_MASK)) + { + if(aclAct.cact_ext == FILTER_ENACT_CACTEXT_VLANONLY) + aclAct.cact_ext = FILTER_ENACT_CACTEXT_BOTHVLANTAG; + } + else + { + aclAct.cact_ext = FILTER_ENACT_CACTEXT_TAGONLY; + } + aclAct.tag_fmt = FILTER_CTAGFMT_KEEP1PRMK; + aclActCtrl |= FILTER_ENACT_CVLAN_MASK; + break; + default: + return RT_ERR_FILTER_INACL_ACT_NOT_SUPPORT; + } + } + } + + + /*check if free ACL rules are enough*/ + for(i = filter_id; i < (filter_id + noRulesAdd); i++) + { + if((retVal = rtl8367c_getAsicAclRule(i, &tempRule)) != RT_ERR_OK ) + return retVal; + + if(tempRule.valid == TRUE) + { + return RT_ERR_TBL_FULL; + } + } + + ruleId = 0; + for(i = 0; i < RTL8367C_ACLTEMPLATENO; i++) + { + if(aclRule[i].valid == TRUE) + { + /* write ACL action control */ + if((retVal = rtl8367c_setAsicAclActCtrl(filter_id + ruleId, aclActCtrl)) != RT_ERR_OK ) + return retVal; + /* write ACL action */ + if((retVal = rtl8367c_setAsicAclAct(filter_id + ruleId, &aclAct)) != RT_ERR_OK ) + return retVal; + + /* write ACL not */ + if((retVal = rtl8367c_setAsicAclNot(filter_id + ruleId, pFilter_cfg->invert)) != RT_ERR_OK ) + return retVal; + /* write ACL rule */ + if((retVal = rtl8367c_setAsicAclRule(filter_id + ruleId, &aclRule[i])) != RT_ERR_OK ) + return retVal; + + /* only the first rule will be written with input action control, aclActCtrl of other rules will be zero */ + aclActCtrl = 0; + memset(&aclAct, 0, sizeof(rtl8367c_acl_act_t)); + + ruleId ++; + } + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_filter_igrAcl_cfg_del + * Description: + * Delete an ACL configuration from ASIC + * Input: + * filter_id - Start index of ACL configuration. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_ENTRYIDX - Invalid filter_id. + * Note: + * This function delete a group of ACL rules starting from filter_id. + */ +rtk_api_ret_t dal_rtl8367c_filter_igrAcl_cfg_del(rtk_filter_id_t filter_id) +{ + rtl8367c_aclrule initRule; + rtl8367c_acl_act_t initAct; + rtk_api_ret_t ret; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(filter_id > RTL8367C_ACLRULEMAX ) + return RT_ERR_FILTER_ENTRYIDX; + + memset(&initRule, 0, sizeof(rtl8367c_aclrule)); + memset(&initAct, 0, sizeof(rtl8367c_acl_act_t)); + + if((ret = rtl8367c_setAsicAclRule(filter_id, &initRule)) != RT_ERR_OK) + return ret; + if((ret = rtl8367c_setAsicAclActCtrl(filter_id, FILTER_ENACT_INIT_MASK))!= RT_ERR_OK) + return ret; + if((ret = rtl8367c_setAsicAclAct(filter_id, &initAct)) != RT_ERR_OK) + return ret; + if((ret = rtl8367c_setAsicAclNot(filter_id, DISABLED)) != RT_ERR_OK ) + return ret; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8367c_filter_igrAcl_cfg_get + * Description: + * Get one ingress acl configuration from ASIC. + * Input: + * filter_id - Start index of ACL configuration. + * Output: + * pFilter_cfg - buffer pointer of ingress acl data + * pFilter_action - buffer pointer of ingress acl action + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Pointer pFilter_action or pFilter_cfg point to NULL. + * RT_ERR_FILTER_ENTRYIDX - Invalid entry index. + * Note: + * This function get configuration from ASIC. + */ +rtk_api_ret_t dal_rtl8367c_filter_igrAcl_cfg_get(rtk_filter_id_t filter_id, rtk_filter_cfg_raw_t *pFilter_cfg, rtk_filter_action_t *pAction) +{ + rtk_api_ret_t retVal; + rtk_uint32 i, tmp; + rtl8367c_aclrule aclRule; + rtl8367c_acl_act_t aclAct; + rtk_uint32 cpuPort; + rtl8367c_acltemplate_t type; + rtl8367c_svlan_memconf_t svlan_cfg; + rtl8367c_vlanconfiguser vlanMC; + rtk_uint32 phyPmask; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pFilter_cfg || NULL == pAction) + return RT_ERR_NULL_POINTER; + + if(filter_id > RTL8367C_ACLRULEMAX) + return RT_ERR_ENTRY_INDEX; + + if ((retVal = rtl8367c_getAsicAclRule(filter_id, &aclRule)) != RT_ERR_OK) + return retVal; + + /* Check valid */ + if(aclRule.valid == 0) + { + pFilter_cfg->valid = DISABLED; + return RT_ERR_OK; + } + + phyPmask = aclRule.data_bits.active_portmsk; + if(rtk_switch_portmask_P2L_get(phyPmask,&(pFilter_cfg->activeport.value)) != RT_ERR_OK) + return RT_ERR_FAILED; + + phyPmask = aclRule.care_bits.active_portmsk; + if(rtk_switch_portmask_P2L_get(phyPmask,&(pFilter_cfg->activeport.mask)) != RT_ERR_OK) + return RT_ERR_FAILED; + + for(i = 0; i <= CARE_TAG_IPV6; i++) + { + if(aclRule.data_bits.tag_exist & (1 << i)) + pFilter_cfg->careTag.tagType[i].value = 1; + else + pFilter_cfg->careTag.tagType[i].value = 0; + + if (aclRule.care_bits.tag_exist & (1 << i)) + pFilter_cfg->careTag.tagType[i].mask = 1; + else + pFilter_cfg->careTag.tagType[i].mask = 0; + } + + if(filter_advanceCaretagField[aclRule.data_bits.type][0] == TRUE) + { + /* Advanced Care tag setting */ + for(i = CARE_TAG_TCP; i < CARE_TAG_END; i++) + { + if(aclRule.data_bits.field[filter_advanceCaretagField[aclRule.data_bits.type][1]] & (0x0001 << (i-CARE_TAG_TCP)) ) + pFilter_cfg->careTag.tagType[i].value = 1; + else + pFilter_cfg->careTag.tagType[i].value = 0; + + if(aclRule.care_bits.field[filter_advanceCaretagField[aclRule.care_bits.type][1]] & (0x0001 << (i-CARE_TAG_TCP)) ) + pFilter_cfg->careTag.tagType[i].mask = 1; + else + pFilter_cfg->careTag.tagType[i].mask = 0; + } + } + + for(i = 0; i < RTL8367C_ACLRULEFIELDNO; i++) + { + pFilter_cfg->careFieldRaw[i] = aclRule.care_bits.field[i]; + pFilter_cfg->dataFieldRaw[i] = aclRule.data_bits.field[i]; + } + + if ((retVal = rtl8367c_getAsicAclNot(filter_id, &tmp))!= RT_ERR_OK) + return retVal; + + pFilter_cfg->invert = tmp; + + pFilter_cfg->valid = aclRule.valid; + + memset(pAction, 0, sizeof(rtk_filter_action_t)); + + if ((retVal = rtl8367c_getAsicAclActCtrl(filter_id, &tmp))!= RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_getAsicAclAct(filter_id, &aclAct)) != RT_ERR_OK) + return retVal; + + if(tmp & FILTER_ENACT_FWD_MASK) + { + if(TRUE == aclAct.fwdact_ext) + { + pAction->actEnable[FILTER_ENACT_ISOLATION] = TRUE; + + phyPmask = aclAct.fwdpmask; + if(rtk_switch_portmask_P2L_get(phyPmask,&(pAction->filterPortmask)) != RT_ERR_OK) + return RT_ERR_FAILED; + } + else if(aclAct.fwdact == RTL8367C_ACL_FWD_TRAP) + { + pAction->actEnable[FILTER_ENACT_TRAP_CPU] = TRUE; + } + else if (aclAct.fwdact == RTL8367C_ACL_FWD_MIRRORFUNTION ) + { + pAction->actEnable[FILTER_ENACT_MIRROR] = TRUE; + + phyPmask = aclAct.fwdpmask; + if(rtk_switch_portmask_P2L_get(phyPmask,&(pAction->filterPortmask)) != RT_ERR_OK) + return RT_ERR_FAILED; + } + else if (aclAct.fwdact == RTL8367C_ACL_FWD_REDIRECT) + { + if(aclAct.fwdpmask == 0 ) + pAction->actEnable[FILTER_ENACT_DROP] = TRUE; + else + { + pAction->actEnable[FILTER_ENACT_REDIRECT] = TRUE; + + phyPmask = aclAct.fwdpmask; + if(rtk_switch_portmask_P2L_get(phyPmask,&(pAction->filterPortmask)) != RT_ERR_OK) + return RT_ERR_FAILED; + } + } + else if (aclAct.fwdact == RTL8367C_ACL_FWD_MIRROR) + { + if((retVal = rtl8367c_getAsicCputagTrapPort(&cpuPort)) != RT_ERR_OK) + return retVal; + if (aclAct.fwdpmask == (1 << cpuPort)) + { + pAction->actEnable[FILTER_ENACT_COPY_CPU] = TRUE; + } + else + { + pAction->actEnable[FILTER_ENACT_ADD_DSTPORT] = TRUE; + + phyPmask = aclAct.fwdpmask; + if(rtk_switch_portmask_P2L_get(phyPmask,&(pAction->filterPortmask)) != RT_ERR_OK) + return RT_ERR_FAILED; + } + } + else + { + return RT_ERR_FAILED; + } + } + + if(tmp & FILTER_ENACT_POLICING_MASK) + { + pAction->actEnable[FILTER_ENACT_POLICING_0] = TRUE; + pAction->filterPolicingIdx[0] = aclAct.aclmeteridx; + } + + if(tmp & FILTER_ENACT_PRIORITY_MASK) + { + if(aclAct.priact == FILTER_ENACT_PRI_TYPE(FILTER_ENACT_PRIORITY)) + { + pAction->actEnable[FILTER_ENACT_PRIORITY] = TRUE; + pAction->filterPriority = aclAct.pridx; + } + else if(aclAct.priact == FILTER_ENACT_PRI_TYPE(FILTER_ENACT_1P_REMARK)) + { + pAction->actEnable[FILTER_ENACT_1P_REMARK] = TRUE; + pAction->filterPriority = aclAct.pridx; + } + else if(aclAct.priact == FILTER_ENACT_PRI_TYPE(FILTER_ENACT_DSCP_REMARK)) + { + pAction->actEnable[FILTER_ENACT_DSCP_REMARK] = TRUE; + pAction->filterPriority = aclAct.pridx; + } + else if(aclAct.priact == FILTER_ENACT_PRI_TYPE(FILTER_ENACT_POLICING_3)) + { + pAction->actEnable[FILTER_ENACT_POLICING_3] = TRUE; + pAction->filterPolicingIdx[3] = aclAct.pridx; + } + } + + if(tmp & FILTER_ENACT_SVLAN_MASK) + { + if(aclAct.sact == FILTER_ENACT_SVLAN_TYPE(FILTER_ENACT_SVLAN_INGRESS)) + { + if((retVal = rtl8367c_getAsicSvlanMemberConfiguration(aclAct.svidx_sact, &svlan_cfg)) != RT_ERR_OK) + return retVal; + + pAction->actEnable[FILTER_ENACT_SVLAN_INGRESS] = TRUE; + pAction->filterSvlanIdx = aclAct.svidx_sact; + pAction->filterSvlanVid = svlan_cfg.vs_svid; + } + else if(aclAct.sact == FILTER_ENACT_SVLAN_TYPE(FILTER_ENACT_SVLAN_EGRESS)) + { + if((retVal = rtl8367c_getAsicSvlanMemberConfiguration(aclAct.svidx_sact, &svlan_cfg)) != RT_ERR_OK) + return retVal; + + pAction->actEnable[FILTER_ENACT_SVLAN_EGRESS] = TRUE; + pAction->filterSvlanIdx = aclAct.svidx_sact; + pAction->filterSvlanVid = svlan_cfg.vs_svid; + } + else if(aclAct.sact == FILTER_ENACT_SVLAN_TYPE(FILTER_ENACT_SVLAN_CVID)) + pAction->actEnable[FILTER_ENACT_SVLAN_CVID] = TRUE; + else if(aclAct.sact == FILTER_ENACT_SVLAN_TYPE(FILTER_ENACT_POLICING_2)) + { + pAction->actEnable[FILTER_ENACT_POLICING_2] = TRUE; + pAction->filterPolicingIdx[2] = aclAct.svidx_sact; + } + } + + + if(tmp & FILTER_ENACT_CVLAN_MASK) + { + if(FILTER_ENACT_CACTEXT_TAGONLY == aclAct.cact_ext || + FILTER_ENACT_CACTEXT_BOTHVLANTAG == aclAct.cact_ext ) + { + if(FILTER_CTAGFMT_UNTAG == aclAct.tag_fmt) + { + pAction->actEnable[FILTER_ENACT_EGRESSCTAG_UNTAG] = TRUE; + } + else if(FILTER_CTAGFMT_TAG == aclAct.tag_fmt) + { + pAction->actEnable[FILTER_ENACT_EGRESSCTAG_TAG] = TRUE; + } + else if(FILTER_CTAGFMT_KEEP == aclAct.tag_fmt) + { + pAction->actEnable[FILTER_ENACT_EGRESSCTAG_KEEP] = TRUE; + } + else if(FILTER_CTAGFMT_KEEP1PRMK== aclAct.tag_fmt) + { + pAction->actEnable[FILTER_ENACT_EGRESSCTAG_KEEPAND1PRMK] = TRUE; + } + + } + + if(FILTER_ENACT_CACTEXT_VLANONLY == aclAct.cact_ext || + FILTER_ENACT_CACTEXT_BOTHVLANTAG == aclAct.cact_ext ) + { + if(aclAct.cact == FILTER_ENACT_CVLAN_TYPE(FILTER_ENACT_CVLAN_INGRESS)) + { + if((retVal = rtl8367c_getAsicVlanMemberConfig(aclAct.cvidx_cact, &vlanMC)) != RT_ERR_OK) + return retVal; + + pAction->actEnable[FILTER_ENACT_CVLAN_INGRESS] = TRUE; + pAction->filterCvlanIdx = aclAct.cvidx_cact; + pAction->filterCvlanVid = vlanMC.evid; + } + else if(aclAct.cact == FILTER_ENACT_CVLAN_TYPE(FILTER_ENACT_CVLAN_EGRESS)) + { + if((retVal = rtl8367c_getAsicVlanMemberConfig(aclAct.cvidx_cact, &vlanMC)) != RT_ERR_OK) + return retVal; + + pAction->actEnable[FILTER_ENACT_CVLAN_EGRESS] = TRUE; + pAction->filterCvlanIdx = aclAct.cvidx_cact; + pAction->filterCvlanVid = vlanMC.evid; + } + else if(aclAct.cact == FILTER_ENACT_CVLAN_TYPE(FILTER_ENACT_CVLAN_SVID)) + { + pAction->actEnable[FILTER_ENACT_CVLAN_SVID] = TRUE; + } + else if(aclAct.cact == FILTER_ENACT_CVLAN_TYPE(FILTER_ENACT_POLICING_1)) + { + pAction->actEnable[FILTER_ENACT_POLICING_1] = TRUE; + pAction->filterPolicingIdx[1] = aclAct.cvidx_cact; + } + } + } + + if(tmp & FILTER_ENACT_INTGPIO_MASK) + { + if(TRUE == aclAct.aclint) + { + pAction->actEnable[FILTER_ENACT_INTERRUPT] = TRUE; + } + + if(TRUE == aclAct.gpio_en) + { + pAction->actEnable[FILTER_ENACT_GPO] = TRUE; + pAction->filterPin = aclAct.gpio_pin; + } + } + + /* Get field type of RAW data */ + if ((retVal = rtl8367c_getAsicAclTemplate(aclRule.data_bits.type, &type))!= RT_ERR_OK) + return retVal; + + for(i = 0; i < RTL8367C_ACLRULEFIELDNO; i++) + { + pFilter_cfg->fieldRawType[i] = type.field[i]; + }/* end of for(i...) */ + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_filter_igrAcl_unmatchAction_set + * Description: + * Set action to packets when no ACL configuration match + * Input: + * port - Port id. + * action - Action. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port id. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This function sets action of packets when no ACL configruation matches. + */ +rtk_api_ret_t dal_rtl8367c_filter_igrAcl_unmatchAction_set(rtk_port_t port, rtk_filter_unmatch_action_t action) +{ + rtk_api_ret_t ret; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check port valid */ + RTK_CHK_PORT_VALID(port); + + if(action >= FILTER_UNMATCH_END) + return RT_ERR_INPUT; + + if((ret = rtl8367c_setAsicAclUnmatchedPermit(rtk_switch_port_L2P_get(port), action)) != RT_ERR_OK) + return ret; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_filter_igrAcl_unmatchAction_get + * Description: + * Get action to packets when no ACL configuration match + * Input: + * port - Port id. + * Output: + * pAction - Action. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port id. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This function gets action of packets when no ACL configruation matches. + */ +rtk_api_ret_t dal_rtl8367c_filter_igrAcl_unmatchAction_get(rtk_port_t port, rtk_filter_unmatch_action_t* pAction) +{ + rtk_api_ret_t ret; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pAction) + return RT_ERR_NULL_POINTER; + + /* Check port valid */ + RTK_CHK_PORT_VALID(port); + + if((ret = rtl8367c_getAsicAclUnmatchedPermit(rtk_switch_port_L2P_get(port), pAction)) != RT_ERR_OK) + return ret; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_filter_igrAcl_state_set + * Description: + * Set state of ingress ACL. + * Input: + * port - Port id. + * state - Ingress ACL state. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port id. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This function gets action of packets when no ACL configruation matches. + */ +rtk_api_ret_t dal_rtl8367c_filter_igrAcl_state_set(rtk_port_t port, rtk_filter_state_t state) +{ + rtk_api_ret_t ret; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check port valid */ + RTK_CHK_PORT_VALID(port); + + if(state >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if((ret = rtl8367c_setAsicAcl(rtk_switch_port_L2P_get(port), state)) != RT_ERR_OK) + return ret; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_filter_igrAcl_state_get + * Description: + * Get state of ingress ACL. + * Input: + * port - Port id. + * Output: + * pState - Ingress ACL state. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port id. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This function gets action of packets when no ACL configruation matches. + */ +rtk_api_ret_t dal_rtl8367c_filter_igrAcl_state_get(rtk_port_t port, rtk_filter_state_t* pState) +{ + rtk_api_ret_t ret; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pState) + return RT_ERR_NULL_POINTER; + + /* Check port valid */ + RTK_CHK_PORT_VALID(port); + + if((ret = rtl8367c_getAsicAcl(rtk_switch_port_L2P_get(port), pState)) != RT_ERR_OK) + return ret; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_filter_igrAcl_template_set + * Description: + * Set template of ingress ACL. + * Input: + * template - Ingress ACL template + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This function set ACL template. + */ +rtk_api_ret_t dal_rtl8367c_filter_igrAcl_template_set(rtk_filter_template_t *aclTemplate) +{ + rtk_api_ret_t retVal; + rtk_uint32 idxField; + rtl8367c_acltemplate_t aclType; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(aclTemplate->index >= RTK_MAX_NUM_OF_FILTER_TYPE) + return RT_ERR_INPUT; + + for(idxField = 0; idxField < RTK_MAX_NUM_OF_FILTER_FIELD; idxField++) + { + if(aclTemplate->fieldType[idxField] < FILTER_FIELD_RAW_DMAC_15_0 || + (aclTemplate->fieldType[idxField] > FILTER_FIELD_RAW_CTAG && aclTemplate->fieldType[idxField] < FILTER_FIELD_RAW_IPV4_SIP_15_0 ) || + (aclTemplate->fieldType[idxField] > FILTER_FIELD_RAW_IPV4_DIP_31_16 && aclTemplate->fieldType[idxField] < FILTER_FIELD_RAW_IPV6_SIP_15_0 ) || + (aclTemplate->fieldType[idxField] > FILTER_FIELD_RAW_IPV6_DIP_31_16 && aclTemplate->fieldType[idxField] < FILTER_FIELD_RAW_VIDRANGE ) || + (aclTemplate->fieldType[idxField] > FILTER_FIELD_RAW_FIELD_VALID && aclTemplate->fieldType[idxField] < FILTER_FIELD_RAW_FIELD_SELECT00 ) || + aclTemplate->fieldType[idxField] >= FILTER_FIELD_RAW_END) + { + return RT_ERR_INPUT; + } + } + + for(idxField = 0; idxField < RTK_MAX_NUM_OF_FILTER_FIELD; idxField++) + { + aclType.field[idxField] = aclTemplate->fieldType[idxField]; + } + + if((retVal = rtl8367c_setAsicAclTemplate(aclTemplate->index, &aclType)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_filter_igrAcl_template_get + * Description: + * Get template of ingress ACL. + * Input: + * template - Ingress ACL template + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This function gets template of ACL. + */ +rtk_api_ret_t dal_rtl8367c_filter_igrAcl_template_get(rtk_filter_template_t *aclTemplate) +{ + rtk_api_ret_t ret; + rtk_uint32 idxField; + rtl8367c_acltemplate_t aclType; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == aclTemplate) + return RT_ERR_NULL_POINTER; + + if(aclTemplate->index >= RTK_MAX_NUM_OF_FILTER_TYPE) + return RT_ERR_INPUT; + + if((ret = rtl8367c_getAsicAclTemplate(aclTemplate->index, &aclType)) != RT_ERR_OK) + return ret; + + for(idxField = 0; idxField < RTK_MAX_NUM_OF_FILTER_FIELD; idxField ++) + { + aclTemplate->fieldType[idxField] = aclType.field[idxField]; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_filter_igrAcl_field_sel_set + * Description: + * Set user defined field selectors in HSB + * Input: + * index - index of field selector 0-15 + * format - Format of field selector + * offset - Retrieving data offset + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * System support 16 user defined field selctors. + * Each selector can be enabled or disable. + * User can defined retrieving 16-bits in many predefiend + * standard l2/l3/l4 payload. + */ +rtk_api_ret_t dal_rtl8367c_filter_igrAcl_field_sel_set(rtk_uint32 index, rtk_field_sel_t format, rtk_uint32 offset) +{ + rtk_api_ret_t ret; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(index >= RTL8367C_FIELDSEL_FORMAT_NUMBER) + return RT_ERR_OUT_OF_RANGE; + + if(format >= FORMAT_END) + return RT_ERR_OUT_OF_RANGE; + + if(offset > RTL8367C_FIELDSEL_MAX_OFFSET) + return RT_ERR_OUT_OF_RANGE; + + if((ret = rtl8367c_setAsicFieldSelector(index, (rtk_uint32)format, offset)) != RT_ERR_OK) + return ret; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_filter_igrAcl_field_sel_get + * Description: + * Get user defined field selectors in HSB + * Input: + * index - index of field selector 0-15 + * Output: + * pFormat - Format of field selector + * pOffset - Retrieving data offset + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * None. + */ +rtk_api_ret_t dal_rtl8367c_filter_igrAcl_field_sel_get(rtk_uint32 index, rtk_field_sel_t *pFormat, rtk_uint32 *pOffset) +{ + rtk_api_ret_t ret; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pFormat || NULL == pOffset) + return RT_ERR_NULL_POINTER; + + if(index >= RTL8367C_FIELDSEL_FORMAT_NUMBER) + return RT_ERR_OUT_OF_RANGE; + + if((ret = rtl8367c_getAsicFieldSelector(index, pFormat, pOffset)) != RT_ERR_OK) + return ret; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_filter_iprange_set + * Description: + * Set IP Range check + * Input: + * index - index of IP Range 0-15 + * type - IP Range check type, 0:Delete a entry, 1: IPv4_SIP, 2: IPv4_DIP, 3:IPv6_SIP, 4:IPv6_DIP + * upperIp - The upper bound of IP range + * lowerIp - The lower Bound of IP range + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - The parameter is out of range + * RT_ERR_INPUT - Input error + * Note: + * upperIp must be larger or equal than lowerIp. + */ +rtk_api_ret_t dal_rtl8367c_filter_iprange_set(rtk_uint32 index, rtk_filter_iprange_t type, ipaddr_t upperIp, ipaddr_t lowerIp) +{ + rtk_api_ret_t ret; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(index > RTL8367C_ACLRANGEMAX) + return RT_ERR_OUT_OF_RANGE; + + if(type >= IPRANGE_END) + return RT_ERR_OUT_OF_RANGE; + + if(lowerIp > upperIp) + return RT_ERR_INPUT; + + if((ret = rtl8367c_setAsicAclIpRange(index, type, upperIp, lowerIp)) != RT_ERR_OK) + return ret; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_filter_iprange_get + * Description: + * Set IP Range check + * Input: + * index - index of IP Range 0-15 + * Output: + * pType - IP Range check type, 0:Delete a entry, 1: IPv4_SIP, 2: IPv4_DIP, 3:IPv6_SIP, 4:IPv6_DIP + * pUpperIp - The upper bound of IP range + * pLowerIp - The lower Bound of IP range + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - The parameter is out of range + * Note: + * None. + */ +rtk_api_ret_t dal_rtl8367c_filter_iprange_get(rtk_uint32 index, rtk_filter_iprange_t *pType, ipaddr_t *pUpperIp, ipaddr_t *pLowerIp) +{ + rtk_api_ret_t ret; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if((NULL == pType) || (NULL == pUpperIp) || (NULL == pLowerIp)) + return RT_ERR_NULL_POINTER; + + if(index > RTL8367C_ACLRANGEMAX) + return RT_ERR_OUT_OF_RANGE; + + if((ret = rtl8367c_getAsicAclIpRange(index, pType, pUpperIp, pLowerIp)) != RT_ERR_OK) + return ret; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_filter_vidrange_set + * Description: + * Set VID Range check + * Input: + * index - index of VID Range 0-15 + * type - IP Range check type, 0:Delete a entry, 1: CVID, 2: SVID + * upperVid - The upper bound of VID range + * lowerVid - The lower Bound of VID range + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - The parameter is out of range + * RT_ERR_INPUT - Input error + * Note: + * upperVid must be larger or equal than lowerVid. + */ +rtk_api_ret_t dal_rtl8367c_filter_vidrange_set(rtk_uint32 index, rtk_filter_vidrange_t type, rtk_uint32 upperVid, rtk_uint32 lowerVid) +{ + rtk_api_ret_t ret; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(index > RTL8367C_ACLRANGEMAX) + return RT_ERR_OUT_OF_RANGE; + + if(type >= VIDRANGE_END) + return RT_ERR_OUT_OF_RANGE; + + if(lowerVid > upperVid) + return RT_ERR_INPUT; + + if( (upperVid > RTL8367C_VIDMAX) || (lowerVid > RTL8367C_VIDMAX)) + return RT_ERR_OUT_OF_RANGE; + + if((ret = rtl8367c_setAsicAclVidRange(index, type, upperVid, lowerVid)) != RT_ERR_OK) + return ret; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_filter_vidrange_get + * Description: + * Get VID Range check + * Input: + * index - index of VID Range 0-15 + * Output: + * pType - IP Range check type, 0:Unused, 1: CVID, 2: SVID + * pUpperVid - The upper bound of VID range + * pLowerVid - The lower Bound of VID range + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - The parameter is out of range + * Note: + * None. + */ +rtk_api_ret_t dal_rtl8367c_filter_vidrange_get(rtk_uint32 index, rtk_filter_vidrange_t *pType, rtk_uint32 *pUpperVid, rtk_uint32 *pLowerVid) +{ + rtk_api_ret_t ret; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if((NULL == pType) || (NULL == pUpperVid) || (NULL == pLowerVid)) + return RT_ERR_NULL_POINTER; + + if(index > RTL8367C_ACLRANGEMAX) + return RT_ERR_OUT_OF_RANGE; + + if((ret = rtl8367c_getAsicAclVidRange(index, pType, pUpperVid, pLowerVid)) != RT_ERR_OK) + return ret; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_filter_portrange_set + * Description: + * Set Port Range check + * Input: + * index - index of Port Range 0-15 + * type - IP Range check type, 0:Delete a entry, 1: Source Port, 2: Destnation Port + * upperPort - The upper bound of Port range + * lowerPort - The lower Bound of Port range + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - The parameter is out of range + * RT_ERR_INPUT - Input error + * Note: + * upperPort must be larger or equal than lowerPort. + */ +rtk_api_ret_t dal_rtl8367c_filter_portrange_set(rtk_uint32 index, rtk_filter_portrange_t type, rtk_uint32 upperPort, rtk_uint32 lowerPort) +{ + rtk_api_ret_t ret; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(index > RTL8367C_ACLRANGEMAX) + return RT_ERR_OUT_OF_RANGE; + + if(type >= PORTRANGE_END) + return RT_ERR_OUT_OF_RANGE; + + if(lowerPort > upperPort) + return RT_ERR_INPUT; + + if(upperPort > RTL8367C_ACL_PORTRANGEMAX) + return RT_ERR_INPUT; + + if(lowerPort > RTL8367C_ACL_PORTRANGEMAX) + return RT_ERR_INPUT; + + if((ret = rtl8367c_setAsicAclPortRange(index, type, upperPort, lowerPort)) != RT_ERR_OK) + return ret; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_filter_portrange_get + * Description: + * Set Port Range check + * Input: + * index - index of Port Range 0-15 + * Output: + * pType - IP Range check type, 0:Delete a entry, 1: Source Port, 2: Destnation Port + * pUpperPort - The upper bound of Port range + * pLowerPort - The lower Bound of Port range + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - The parameter is out of range + * RT_ERR_INPUT - Input error + * Note: + * None. + */ +rtk_api_ret_t dal_rtl8367c_filter_portrange_get(rtk_uint32 index, rtk_filter_portrange_t *pType, rtk_uint32 *pUpperPort, rtk_uint32 *pLowerPort) +{ + rtk_api_ret_t ret; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if((NULL == pType) || (NULL == pUpperPort) || (NULL == pLowerPort)) + return RT_ERR_NULL_POINTER; + + if(index > RTL8367C_ACLRANGEMAX) + return RT_ERR_OUT_OF_RANGE; + + if((ret = rtl8367c_getAsicAclPortRange(index, pType, pUpperPort, pLowerPort)) != RT_ERR_OK) + return ret; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_filter_igrAclPolarity_set + * Description: + * Set ACL Goip control palarity + * Input: + * polarity - 1: High, 0: Low + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * none + */ +rtk_api_ret_t dal_rtl8367c_filter_igrAclPolarity_set(rtk_uint32 polarity) +{ + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(polarity > 1) + return RT_ERR_OUT_OF_RANGE; + + return rtl8367c_setAsicAclGpioPolarity(polarity); +} + +/* Function Name: + * dal_rtl8367c_filter_igrAclPolarity_get + * Description: + * Get ACL Goip control palarity + * Input: + * pPolarity - 1: High, 0: Low + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * none + */ +rtk_api_ret_t dal_rtl8367c_filter_igrAclPolarity_get(rtk_uint32* pPolarity) +{ + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pPolarity) + return RT_ERR_NULL_POINTER; + + return rtl8367c_getAsicAclGpioPolarity(pPolarity); +} + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_acl.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_acl.h new file mode 100644 index 00000000..121b81b4 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_acl.h @@ -0,0 +1,458 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8367/RTL8367C switch high-level API + * + * Feature : The file includes ACL module high-layer API defination + * + */ + +#ifndef __DAL_RTL8367C_ACL_H__ +#define __DAL_RTL8367C_ACL_H__ + +#include + +/* Function Name: + * dal_rtl8367c_filter_igrAcl_init + * Description: + * ACL initialization function + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Pointer pFilter_field or pFilter_cfg point to NULL. + * Note: + * This function enable and intialize ACL function + */ +extern rtk_api_ret_t dal_rtl8367c_filter_igrAcl_init(void); + +/* Function Name: + * dal_rtl8367c_filter_igrAcl_field_add + * Description: + * Add comparison rule to an ACL configuration + * Input: + * pFilter_cfg - The ACL configuration that this function will add comparison rule + * pFilter_field - The comparison rule that will be added. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Pointer pFilter_field or pFilter_cfg point to NULL. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This function add a comparison rule (*pFilter_field) to an ACL configuration (*pFilter_cfg). + * Pointer pFilter_cfg points to an ACL configuration structure, this structure keeps multiple ACL + * comparison rules by means of linked list. Pointer pFilter_field will be added to linked + * list keeped by structure that pFilter_cfg points to. + */ +extern rtk_api_ret_t dal_rtl8367c_filter_igrAcl_field_add(rtk_filter_cfg_t *pFilter_cfg, rtk_filter_field_t *pFilter_field); + +/* Function Name: + * dal_rtl8367c_filter_igrAcl_cfg_add + * Description: + * Add an ACL configuration to ASIC + * Input: + * filter_id - Start index of ACL configuration. + * pFilter_cfg - The ACL configuration that this function will add comparison rule + * pFilter_action - Action(s) of ACL configuration. + * Output: + * ruleNum - number of rules written in acl table + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Pointer pFilter_field or pFilter_cfg point to NULL. + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_ENTRY_INDEX - Invalid filter_id . + * RT_ERR_NULL_POINTER - Pointer pFilter_action or pFilter_cfg point to NULL. + * RT_ERR_FILTER_INACL_ACT_NOT_SUPPORT - Action is not supported in this chip. + * RT_ERR_FILTER_INACL_RULE_NOT_SUPPORT - Rule is not supported. + * Note: + * This function store pFilter_cfg, pFilter_action into ASIC. The starting + * index(es) is filter_id. + */ +extern rtk_api_ret_t dal_rtl8367c_filter_igrAcl_cfg_add(rtk_filter_id_t filter_id, rtk_filter_cfg_t *pFilter_cfg, rtk_filter_action_t *pAction, rtk_filter_number_t *ruleNum); + +/* Function Name: + * dal_rtl8367c_filter_igrAcl_cfg_del + * Description: + * Delete an ACL configuration from ASIC + * Input: + * filter_id - Start index of ACL configuration. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_ENTRYIDX - Invalid filter_id. + * Note: + * This function delete a group of ACL rules starting from filter_id. + */ +extern rtk_api_ret_t dal_rtl8367c_filter_igrAcl_cfg_del(rtk_filter_id_t filter_id); + +/* Function Name: + * dal_rtl8367c_filter_igrAcl_cfg_delAll + * Description: + * Delete all ACL entries from ASIC + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This function delete all ACL configuration from ASIC. + */ +extern rtk_api_ret_t dal_rtl8367c_filter_igrAcl_cfg_delAll(void); + +/* Function Name: + * dal_rtl8367c_filter_igrAcl_cfg_get + * Description: + * Get one ingress acl configuration from ASIC. + * Input: + * filter_id - Start index of ACL configuration. + * Output: + * pFilter_cfg - buffer pointer of ingress acl data + * pFilter_action - buffer pointer of ingress acl action + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Pointer pFilter_action or pFilter_cfg point to NULL. + * RT_ERR_FILTER_ENTRYIDX - Invalid entry index. + * Note: + * This function delete all ACL configuration from ASIC. + */ +extern rtk_api_ret_t dal_rtl8367c_filter_igrAcl_cfg_get(rtk_filter_id_t filter_id, rtk_filter_cfg_raw_t *pFilter_cfg, rtk_filter_action_t *pAction); + +/* Function Name: + * dal_rtl8367c_filter_igrAcl_unmatchAction_set + * Description: + * Set action to packets when no ACL configuration match + * Input: + * port - Port id. + * action - Action. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port id. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This function sets action of packets when no ACL configruation matches. + */ +extern rtk_api_ret_t dal_rtl8367c_filter_igrAcl_unmatchAction_set(rtk_port_t port, rtk_filter_unmatch_action_t action); + +/* Function Name: + * dal_rtl8367c_filter_igrAcl_unmatchAction_get + * Description: + * Get action to packets when no ACL configuration match + * Input: + * port - Port id. + * Output: + * pAction - Action. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port id. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This function gets action of packets when no ACL configruation matches. + */ +extern rtk_api_ret_t dal_rtl8367c_filter_igrAcl_unmatchAction_get(rtk_port_t port, rtk_filter_unmatch_action_t* action); + +/* Function Name: + * dal_rtl8367c_filter_igrAcl_state_set + * Description: + * Set state of ingress ACL. + * Input: + * port - Port id. + * state - Ingress ACL state. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port id. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This function gets action of packets when no ACL configruation matches. + */ +extern rtk_api_ret_t dal_rtl8367c_filter_igrAcl_state_set(rtk_port_t port, rtk_filter_state_t state); + +/* Function Name: + * dal_rtl8367c_filter_igrAcl_state_get + * Description: + * Get state of ingress ACL. + * Input: + * port - Port id. + * Output: + * pState - Ingress ACL state. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port id. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This function gets action of packets when no ACL configruation matches. + */ +extern rtk_api_ret_t dal_rtl8367c_filter_igrAcl_state_get(rtk_port_t port, rtk_filter_state_t* state); + +/* Function Name: + * dal_rtl8367c_filter_igrAcl_template_set + * Description: + * Set template of ingress ACL. + * Input: + * template - Ingress ACL template + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This function set ACL template. + */ +extern rtk_api_ret_t dal_rtl8367c_filter_igrAcl_template_set(rtk_filter_template_t *aclTemplate); + +/* Function Name: + * dal_rtl8367c_filter_igrAcl_template_get + * Description: + * Get template of ingress ACL. + * Input: + * template - Ingress ACL template + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This function gets template of ACL. + */ +extern rtk_api_ret_t dal_rtl8367c_filter_igrAcl_template_get(rtk_filter_template_t *aclTemplate); + +/* Function Name: + * dal_rtl8367c_filter_igrAcl_field_sel_set + * Description: + * Set user defined field selectors in HSB + * Input: + * index - index of field selector 0-15 + * format - Format of field selector + * offset - Retrieving data offset + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * System support 16 user defined field selctors. + * Each selector can be enabled or disable. + * User can defined retrieving 16-bits in many predefiend + * standard l2/l3/l4 payload. + */ +extern rtk_api_ret_t dal_rtl8367c_filter_igrAcl_field_sel_set(rtk_uint32 index, rtk_field_sel_t format, rtk_uint32 offset); + +/* Function Name: + * dal_rtl8367c_filter_igrAcl_field_sel_get + * Description: + * Get user defined field selectors in HSB + * Input: + * index - index of field selector 0-15 + * Output: + * pFormat - Format of field selector + * pOffset - Retrieving data offset + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * None. + */ +extern rtk_api_ret_t dal_rtl8367c_filter_igrAcl_field_sel_get(rtk_uint32 index, rtk_field_sel_t *pFormat, rtk_uint32 *pOffset); + +/* Function Name: + * dal_rtl8367c_filter_iprange_set + * Description: + * Set IP Range check + * Input: + * index - index of IP Range 0-15 + * type - IP Range check type, 0:Delete a entry, 1: IPv4_SIP, 2: IPv4_DIP, 3:IPv6_SIP, 4:IPv6_DIP + * upperIp - The upper bound of IP range + * lowerIp - The lower Bound of IP range + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - The parameter is out of range + * RT_ERR_INPUT - Input error + * Note: + * upperIp must be larger or equal than lowerIp. + */ +extern rtk_api_ret_t dal_rtl8367c_filter_iprange_set(rtk_uint32 index, rtk_filter_iprange_t type, ipaddr_t upperIp, ipaddr_t lowerIp); + +/* Function Name: + * dal_rtl8367c_filter_iprange_get + * Description: + * Set IP Range check + * Input: + * index - index of IP Range 0-15 + * Output: + * pType - IP Range check type, 0:Delete a entry, 1: IPv4_SIP, 2: IPv4_DIP, 3:IPv6_SIP, 4:IPv6_DIP + * pUpperIp - The upper bound of IP range + * pLowerIp - The lower Bound of IP range + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - The parameter is out of range + * Note: + * upperIp must be larger or equal than lowerIp. + */ +extern rtk_api_ret_t dal_rtl8367c_filter_iprange_get(rtk_uint32 index, rtk_filter_iprange_t *pType, ipaddr_t *pUpperIp, ipaddr_t *pLowerIp); + +/* Function Name: + * dal_rtl8367c_filter_vidrange_set + * Description: + * Set VID Range check + * Input: + * index - index of VID Range 0-15 + * type - IP Range check type, 0:Delete a entry, 1: CVID, 2: SVID + * upperVid - The upper bound of VID range + * lowerVid - The lower Bound of VID range + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - The parameter is out of range + * RT_ERR_INPUT - Input error + * Note: + * upperVid must be larger or equal than lowerVid. + */ +extern rtk_api_ret_t dal_rtl8367c_filter_vidrange_set(rtk_uint32 index, rtk_filter_vidrange_t type, rtk_uint32 upperVid, rtk_uint32 lowerVid); + +/* Function Name: + * dal_rtl8367c_filter_vidrange_get + * Description: + * Get VID Range check + * Input: + * index - index of VID Range 0-15 + * Output: + * pType - IP Range check type, 0:Unused, 1: CVID, 2: SVID + * pUpperVid - The upper bound of VID range + * pLowerVid - The lower Bound of VID range + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - The parameter is out of range + * Note: + * None. + */ +extern rtk_api_ret_t dal_rtl8367c_filter_vidrange_get(rtk_uint32 index, rtk_filter_vidrange_t *pType, rtk_uint32 *pUpperVid, rtk_uint32 *pLowerVid); + +/* Function Name: + * dal_rtl8367c_filter_portrange_set + * Description: + * Set Port Range check + * Input: + * index - index of Port Range 0-15 + * type - IP Range check type, 0:Delete a entry, 1: Source Port, 2: Destnation Port + * upperPort - The upper bound of Port range + * lowerPort - The lower Bound of Port range + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - The parameter is out of range + * RT_ERR_INPUT - Input error + * Note: + * upperPort must be larger or equal than lowerPort. + */ +extern rtk_api_ret_t dal_rtl8367c_filter_portrange_set(rtk_uint32 index, rtk_filter_portrange_t type, rtk_uint32 upperPort, rtk_uint32 lowerPort); + +/* Function Name: + * dal_rtl8367c_filter_portrange_get + * Description: + * Set Port Range check + * Input: + * index - index of Port Range 0-15 + * Output: + * pType - IP Range check type, 0:Delete a entry, 1: Source Port, 2: Destnation Port + * pUpperPort - The upper bound of Port range + * pLowerPort - The lower Bound of Port range + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - The parameter is out of range + * RT_ERR_INPUT - Input error + * Note: + * None. + */ +extern rtk_api_ret_t dal_rtl8367c_filter_portrange_get(rtk_uint32 index, rtk_filter_portrange_t *pType, rtk_uint32 *pUpperPort, rtk_uint32 *pLowerPort); + +/* Function Name: + * dal_rtl8367c_filter_igrAclPolarity_set + * Description: + * Set ACL Goip control palarity + * Input: + * polarity - 1: High, 0: Low + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * none + */ +extern rtk_api_ret_t dal_rtl8367c_filter_igrAclPolarity_set(rtk_uint32 polarity); + +/* Function Name: + * dal_rtl8367c_filter_igrAclPolarity_get + * Description: + * Get ACL Goip control palarity + * Input: + * pPolarity - 1: High, 0: Low + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * none + */ +extern rtk_api_ret_t dal_rtl8367c_filter_igrAclPolarity_get(rtk_uint32* pPolarity); + + +#endif /* __DAL_RTL8367C_ACL_H__ */ diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_cpu.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_cpu.c new file mode 100644 index 00000000..56fa5a82 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_cpu.c @@ -0,0 +1,544 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8367C + * Feature : Here is a list of all functions and variables in CPU module. + * + */ + +#include +#include +#include + +#include + +#include +#include + +/* Function Name: + * dal_rtl8367c_cpu_enable_set + * Description: + * Set CPU port function enable/disable. + * Input: + * enable - CPU port function enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can set CPU port function enable/disable. + */ +rtk_api_ret_t dal_rtl8367c_cpu_enable_set(rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (enable >= RTK_ENABLE_END) + return RT_ERR_ENABLE; + + if ((retVal = rtl8367c_setAsicCputagEnable(enable)) != RT_ERR_OK) + return retVal; + + if (DISABLED == enable) + { + if ((retVal = rtl8367c_setAsicCputagPortmask(0)) != RT_ERR_OK) + return retVal; + } + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8367c_cpu_enable_get + * Description: + * Get CPU port and its setting. + * Input: + * None + * Output: + * pEnable - CPU port function enable + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_L2_NO_CPU_PORT - CPU port is not exist + * Note: + * The API can get CPU port function enable/disable. + */ +rtk_api_ret_t dal_rtl8367c_cpu_enable_get(rtk_enable_t *pEnable) + +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pEnable) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicCputagEnable(pEnable)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_cpu_tagPort_set + * Description: + * Set CPU port and CPU tag insert mode. + * Input: + * port - Port id. + * mode - CPU tag insert for packets egress from CPU port. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can set CPU port and inserting proprietary CPU tag mode (Length/Type 0x8899) + * to the frame that transmitting to CPU port. + * The inset cpu tag mode is as following: + * - CPU_INSERT_TO_ALL + * - CPU_INSERT_TO_TRAPPING + * - CPU_INSERT_TO_NONE + */ +rtk_api_ret_t dal_rtl8367c_cpu_tagPort_set(rtk_port_t port, rtk_cpu_insert_t mode) +{ + rtk_api_ret_t retVal; + rtk_uint32 phyPort; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check port Valid */ + RTK_CHK_PORT_VALID(port); + + if (mode >= CPU_INSERT_END) + return RT_ERR_INPUT; + + phyPort = rtk_switch_port_L2P_get(port); + if (phyPort == UNDEFINE_PHY_PORT) + return RT_ERR_PORT_ID; + + if ((retVal = rtl8367c_setAsicCputagPortmask(1<= CPU_POS_END) + return RT_ERR_INPUT; + + if ((retVal = rtl8367c_setAsicCputagPosition(position)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_cpu_tagPosition_get + * Description: + * Get CPU tag position. + * Input: + * None + * Output: + * pPosition - CPU tag position. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input. + * Note: + * The API can get CPU tag position. + */ +rtk_api_ret_t dal_rtl8367c_cpu_tagPosition_get(rtk_cpu_position_t *pPosition) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pPosition) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicCputagPosition(pPosition)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_cpu_tagLength_set + * Description: + * Set CPU tag length. + * Input: + * length - CPU tag length. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input. + * Note: + * The API can set CPU tag length. + */ +rtk_api_ret_t dal_rtl8367c_cpu_tagLength_set(rtk_cpu_tag_length_t length) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (length >= CPU_LEN_4BYTES_PRIORITY) + return RT_ERR_INPUT; + + if ((retVal = rtl8367c_setAsicCputagMode(length)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_cpu_tagLength_get + * Description: + * Get CPU tag length. + * Input: + * None + * Output: + * pLength - CPU tag length. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input. + * Note: + * The API can get CPU tag length. + */ +rtk_api_ret_t dal_rtl8367c_cpu_tagLength_get(rtk_cpu_tag_length_t *pLength) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pLength) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicCputagMode(pLength)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_cpu_priRemap_set + * Description: + * Configure CPU priorities mapping to internal absolute priority. + * Input: + * int_pri - internal priority value. + * new_pri - new internal priority value. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_VLAN_PRIORITY - Invalid 1p priority. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * Priority of CPU tag assignment for internal asic priority, and it is used for queue usage and packet scheduling. + */ +rtk_api_ret_t dal_rtl8367c_cpu_priRemap_set(rtk_pri_t int_pri, rtk_pri_t new_pri) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (new_pri > RTL8367C_PRIMAX || int_pri > RTL8367C_PRIMAX) + return RT_ERR_VLAN_PRIORITY; + + if ((retVal = rtl8367c_setAsicCputagPriorityRemapping(int_pri, new_pri)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_cpu_priRemap_get + * Description: + * Configure CPU priorities mapping to internal absolute priority. + * Input: + * int_pri - internal priority value. + * Output: + * pNew_pri - new internal priority value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_VLAN_PRIORITY - Invalid 1p priority. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * Priority of CPU tag assignment for internal asic priority, and it is used for queue usage and packet scheduling. + */ +rtk_api_ret_t dal_rtl8367c_cpu_priRemap_get(rtk_pri_t int_pri, rtk_pri_t *pNew_pri) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pNew_pri) + return RT_ERR_NULL_POINTER; + + if (int_pri > RTL8367C_PRIMAX) + return RT_ERR_QOS_INT_PRIORITY; + + if ((retVal = rtl8367c_getAsicCputagPriorityRemapping(int_pri, pNew_pri)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_cpu_acceptLength_set + * Description: + * Set CPU accept length. + * Input: + * length - CPU tag length. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input. + * Note: + * The API can set CPU accept length. + */ +rtk_api_ret_t dal_rtl8367c_cpu_acceptLength_set(rtk_cpu_rx_length_t length) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (length >= CPU_RX_END) + return RT_ERR_INPUT; + + if ((retVal = rtl8367c_setAsicCputagRxMinLength(length)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_cpu_acceptLength_get + * Description: + * Get CPU accept length. + * Input: + * None + * Output: + * pLength - CPU tag length. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input. + * Note: + * The API can get CPU accept length. + */ +rtk_api_ret_t dal_rtl8367c_cpu_acceptLength_get(rtk_cpu_rx_length_t *pLength) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pLength) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicCputagRxMinLength(pLength)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_cpu.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_cpu.h new file mode 100644 index 00000000..77044b55 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_cpu.h @@ -0,0 +1,295 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8367/RTL8367C switch high-level API + * + * Feature : The file includes CPU module high-layer API defination + * + */ + +#ifndef __DAL_RTL8367C_CPU_H__ +#define __DAL_RTL8367C_CPU_H__ +#include <../../cpu.h> + +/* Function Name: + * dal_rtl8367c_cpu_enable_set + * Description: + * Set CPU port function enable/disable. + * Input: + * enable - CPU port function enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can set CPU port function enable/disable. + */ +extern rtk_api_ret_t dal_rtl8367c_cpu_enable_set(rtk_enable_t enable); + +/* Function Name: + * dal_rtl8367c_cpu_enable_get + * Description: + * Get CPU port and its setting. + * Input: + * None + * Output: + * pEnable - CPU port function enable + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_L2_NO_CPU_PORT - CPU port is not exist + * Note: + * The API can get CPU port function enable/disable. + */ +extern rtk_api_ret_t dal_rtl8367c_cpu_enable_get(rtk_enable_t *pEnable); + +/* Function Name: + * dal_rtl8367c_cpu_tagPort_set + * Description: + * Set CPU port and CPU tag insert mode. + * Input: + * port - Port id. + * mode - CPU tag insert for packets egress from CPU port. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can set CPU port and inserting proprietary CPU tag mode (Length/Type 0x8899) + * to the frame that transmitting to CPU port. + * The inset cpu tag mode is as following: + * - CPU_INSERT_TO_ALL + * - CPU_INSERT_TO_TRAPPING + * - CPU_INSERT_TO_NONE + */ +extern rtk_api_ret_t dal_rtl8367c_cpu_tagPort_set(rtk_port_t port, rtk_cpu_insert_t mode); + +/* Function Name: + * dal_rtl8367c_cpu_tagPort_get + * Description: + * Get CPU port and CPU tag insert mode. + * Input: + * None + * Output: + * pPort - Port id. + * pMode - CPU tag insert for packets egress from CPU port, 0:all insert 1:Only for trapped packets 2:no insert. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_L2_NO_CPU_PORT - CPU port is not exist + * Note: + * The API can get configured CPU port and its setting. + * The inset cpu tag mode is as following: + * - CPU_INSERT_TO_ALL + * - CPU_INSERT_TO_TRAPPING + * - CPU_INSERT_TO_NONE + */ +extern rtk_api_ret_t dal_rtl8367c_cpu_tagPort_get(rtk_port_t *pPort, rtk_cpu_insert_t *pMode); + +/* Function Name: + * dal_rtl8367c_cpu_awarePort_set + * Description: + * Set CPU aware port mask. + * Input: + * portmask - Port mask. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Invalid port mask. + * Note: + * The API can set configured CPU aware port mask. + */ +extern rtk_api_ret_t dal_rtl8367c_cpu_awarePort_set(rtk_portmask_t *pPortmask); + + +/* Function Name: + * dal_rtl8367c_cpu_awarePort_get + * Description: + * Get CPU aware port mask. + * Input: + * None + * Output: + * pPortmask - Port mask. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can get configured CPU aware port mask. + */ +extern rtk_api_ret_t dal_rtl8367c_cpu_awarePort_get(rtk_portmask_t *pPortmask); + +/* Function Name: + * dal_rtl8367c_cpu_tagPosition_set + * Description: + * Set CPU tag position. + * Input: + * position - CPU tag position. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input. + * Note: + * The API can set CPU tag position. + */ +extern rtk_api_ret_t dal_rtl8367c_cpu_tagPosition_set(rtk_cpu_position_t position); + +/* Function Name: + * dal_rtl8367c_cpu_tagPosition_get + * Description: + * Get CPU tag position. + * Input: + * None + * Output: + * pPosition - CPU tag position. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input. + * Note: + * The API can get CPU tag position. + */ +extern rtk_api_ret_t dal_rtl8367c_cpu_tagPosition_get(rtk_cpu_position_t *pPosition); + +/* Function Name: + * dal_rtl8367c_cpu_tagLength_set + * Description: + * Set CPU tag length. + * Input: + * length - CPU tag length. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input. + * Note: + * The API can set CPU tag length. + */ +extern rtk_api_ret_t dal_rtl8367c_cpu_tagLength_set(rtk_cpu_tag_length_t length); + +/* Function Name: + * dal_rtl8367c_cpu_tagLength_get + * Description: + * Get CPU tag length. + * Input: + * None + * Output: + * pLength - CPU tag length. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input. + * Note: + * The API can get CPU tag length. + */ +extern rtk_api_ret_t dal_rtl8367c_cpu_tagLength_get(rtk_cpu_tag_length_t *pLength); + +/* Function Name: + * dal_rtl8367c_cpu_acceptLength_set + * Description: + * Set CPU accept length. + * Input: + * length - CPU tag length. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input. + * Note: + * The API can set CPU accept length. + */ +extern rtk_api_ret_t dal_rtl8367c_cpu_acceptLength_set(rtk_cpu_rx_length_t length); + +/* Function Name: + * dal_rtl8367c_cpu_acceptLength_get + * Description: + * Get CPU accept length. + * Input: + * None + * Output: + * pLength - CPU tag length. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input. + * Note: + * The API can get CPU accept length. + */ +extern rtk_api_ret_t dal_rtl8367c_cpu_acceptLength_get(rtk_cpu_rx_length_t *pLength); + +/* Function Name: + * dal_rtl8367c_cpu_priRemap_set + * Description: + * Configure CPU priorities mapping to internal absolute priority. + * Input: + * int_pri - internal priority value. + * new_pri - new internal priority value. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_VLAN_PRIORITY - Invalid 1p priority. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * Priority of CPU tag assignment for internal asic priority, and it is used for queue usage and packet scheduling. + */ +extern rtk_api_ret_t dal_rtl8367c_cpu_priRemap_set(rtk_pri_t int_pri, rtk_pri_t new_pri); + +/* Function Name: + * dal_rtl8367c_cpu_priRemap_get + * Description: + * Configure CPU priorities mapping to internal absolute priority. + * Input: + * int_pri - internal priority value. + * Output: + * pNew_pri - new internal priority value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_VLAN_PRIORITY - Invalid 1p priority. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * Priority of CPU tag assignment for internal asic priority, and it is used for queue usage and packet scheduling. + */ +extern rtk_api_ret_t dal_rtl8367c_cpu_priRemap_get(rtk_pri_t int_pri, rtk_pri_t *pNew_pri); + + +#endif /* __DAL_RTL8367C_CPU_H__ */ diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_dot1x.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_dot1x.c new file mode 100644 index 00000000..50d7266e --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_dot1x.c @@ -0,0 +1,845 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8367C + * Feature : Here is a list of all functions and variables in 1X module. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +/* Function Name: + * dal_rtl8367c_dot1x_unauthPacketOper_set + * Description: + * Set 802.1x unauth action configuration. + * Input: + * port - Port id. + * unauth_action - 802.1X unauth action. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameter. + * Note: + * This API can set 802.1x unauth action configuration. + * The unauth action is as following: + * - DOT1X_ACTION_DROP + * - DOT1X_ACTION_TRAP2CPU + * - DOT1X_ACTION_GUESTVLAN + */ +extern rtk_api_ret_t dal_rtl8367c_dot1x_unauthPacketOper_set(rtk_port_t port, rtk_dot1x_unauth_action_t unauth_action) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check port Valid */ + RTK_CHK_PORT_VALID(port); + + if (unauth_action >= DOT1X_ACTION_END) + return RT_ERR_DOT1X_PROC; + + if ((retVal = rtl8367c_setAsic1xProcConfig(rtk_switch_port_L2P_get(port), unauth_action)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_dot1x_unauthPacketOper_get + * Description: + * Get 802.1x unauth action configuration. + * Input: + * port - Port id. + * Output: + * pUnauth_action - 802.1X unauth action. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can get 802.1x unauth action configuration. + * The unauth action is as following: + * - DOT1X_ACTION_DROP + * - DOT1X_ACTION_TRAP2CPU + * - DOT1X_ACTION_GUESTVLAN + */ +rtk_api_ret_t dal_rtl8367c_dot1x_unauthPacketOper_get(rtk_port_t port, rtk_dot1x_unauth_action_t *pUnauth_action) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check port Valid */ + RTK_CHK_PORT_VALID(port); + + if(NULL == pUnauth_action) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsic1xProcConfig(rtk_switch_port_L2P_get(port), pUnauth_action)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_dot1x_eapolFrame2CpuEnable_set + * Description: + * Set 802.1x EAPOL packet trap to CPU configuration + * Input: + * enable - The status of 802.1x EAPOL packet. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * To support 802.1x authentication functionality, EAPOL frame (ether type = 0x888E) has to + * be trapped to CPU. + * The status of EAPOL frame trap to CPU is as following: + * - DISABLED + * - ENABLED + */ +rtk_api_ret_t dal_rtl8367c_dot1x_eapolFrame2CpuEnable_set(rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + rtl8367c_rma_t rmacfg; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (enable >= RTK_ENABLE_END) + return RT_ERR_ENABLE; + + if ((retVal = rtl8367c_getAsicRma(3, &rmacfg)) != RT_ERR_OK) + return retVal; + + if (ENABLED == enable) + rmacfg.operation = RMAOP_TRAP_TO_CPU; + else if (DISABLED == enable) + rmacfg.operation = RMAOP_FORWARD; + + if ((retVal = rtl8367c_setAsicRma(3, &rmacfg)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_dot1x_eapolFrame2CpuEnable_get + * Description: + * Get 802.1x EAPOL packet trap to CPU configuration + * Input: + * None + * Output: + * pEnable - The status of 802.1x EAPOL packet. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * To support 802.1x authentication functionality, EAPOL frame (ether type = 0x888E) has to + * be trapped to CPU. + * The status of EAPOL frame trap to CPU is as following: + * - DISABLED + * - ENABLED + */ +rtk_api_ret_t dal_rtl8367c_dot1x_eapolFrame2CpuEnable_get(rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + rtl8367c_rma_t rmacfg; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pEnable) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicRma(3, &rmacfg)) != RT_ERR_OK) + return retVal; + + if (RMAOP_TRAP_TO_CPU == rmacfg.operation) + *pEnable = ENABLED; + else + *pEnable = DISABLED; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_dot1x_portBasedEnable_set + * Description: + * Set 802.1x port-based enable configuration + * Input: + * port - Port id. + * enable - The status of 802.1x port. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * RT_ERR_DOT1X_PORTBASEDPNEN - 802.1X port-based enable error + * Note: + * The API can update the port-based port enable register content. If a port is 802.1x + * port based network access control "enabled", it should be authenticated so packets + * from that port won't be dropped or trapped to CPU. + * The status of 802.1x port-based network access control is as following: + * - DISABLED + * - ENABLED + */ +rtk_api_ret_t dal_rtl8367c_dot1x_portBasedEnable_set(rtk_port_t port, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check port Valid */ + RTK_CHK_PORT_VALID(port); + + if (enable >= RTK_ENABLE_END) + return RT_ERR_ENABLE; + + if ((retVal = rtl8367c_setAsic1xPBEnConfig(rtk_switch_port_L2P_get(port),enable)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_dot1x_portBasedEnable_get + * Description: + * Get 802.1x port-based enable configuration + * Input: + * port - Port id. + * Output: + * pEnable - The status of 802.1x port. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get the 802.1x port-based port status. + */ +rtk_api_ret_t dal_rtl8367c_dot1x_portBasedEnable_get(rtk_port_t port, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check port Valid */ + RTK_CHK_PORT_VALID(port); + + if(NULL == pEnable) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsic1xPBEnConfig(rtk_switch_port_L2P_get(port), pEnable)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_dot1x_portBasedAuthStatus_set + * Description: + * Set 802.1x port-based auth. port configuration + * Input: + * port - Port id. + * port_auth - The status of 802.1x port. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_DOT1X_PORTBASEDAUTH - 802.1X port-based auth error + * Note: + * The authenticated status of 802.1x port-based network access control is as following: + * - UNAUTH + * - AUTH + */ +rtk_api_ret_t dal_rtl8367c_dot1x_portBasedAuthStatus_set(rtk_port_t port, rtk_dot1x_auth_status_t port_auth) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check port Valid */ + RTK_CHK_PORT_VALID(port); + + if (port_auth >= AUTH_STATUS_END) + return RT_ERR_DOT1X_PORTBASEDAUTH; + + if ((retVal = rtl8367c_setAsic1xPBAuthConfig(rtk_switch_port_L2P_get(port), port_auth)) != RT_ERR_OK) + return retVal; + + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_dot1x_portBasedAuthStatus_get + * Description: + * Get 802.1x port-based auth. port configuration + * Input: + * port - Port id. + * Output: + * pPort_auth - The status of 802.1x port. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get 802.1x port-based port auth.information. + */ +rtk_api_ret_t dal_rtl8367c_dot1x_portBasedAuthStatus_get(rtk_port_t port, rtk_dot1x_auth_status_t *pPort_auth) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pPort_auth) + return RT_ERR_NULL_POINTER; + + /* Check port Valid */ + RTK_CHK_PORT_VALID(port); + + if ((retVal = rtl8367c_getAsic1xPBAuthConfig(rtk_switch_port_L2P_get(port), pPort_auth)) != RT_ERR_OK) + return retVal; + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_dot1x_portBasedDirection_set + * Description: + * Set 802.1x port-based operational direction configuration + * Input: + * port - Port id. + * port_direction - Operation direction + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_DOT1X_PORTBASEDOPDIR - 802.1X port-based operation direction error + * Note: + * The operate controlled direction of 802.1x port-based network access control is as following: + * - BOTH + * - IN + */ +rtk_api_ret_t dal_rtl8367c_dot1x_portBasedDirection_set(rtk_port_t port, rtk_dot1x_direction_t port_direction) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check port Valid */ + RTK_CHK_PORT_VALID(port); + + if (port_direction >= DIRECTION_END) + return RT_ERR_DOT1X_PORTBASEDOPDIR; + + if ((retVal = rtl8367c_setAsic1xPBOpdirConfig(rtk_switch_port_L2P_get(port), port_direction)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_dot1x_portBasedDirection_get + * Description: + * Get 802.1X port-based operational direction configuration + * Input: + * port - Port id. + * Output: + * pPort_direction - Operation direction + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get 802.1x port-based operational direction information. + */ +rtk_api_ret_t dal_rtl8367c_dot1x_portBasedDirection_get(rtk_port_t port, rtk_dot1x_direction_t *pPort_direction) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pPort_direction) + return RT_ERR_NULL_POINTER; + + /* Check port Valid */ + RTK_CHK_PORT_VALID(port); + + if ((retVal = rtl8367c_getAsic1xPBOpdirConfig(rtk_switch_port_L2P_get(port), pPort_direction)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_dot1x_macBasedEnable_set + * Description: + * Set 802.1x mac-based port enable configuration + * Input: + * port - Port id. + * enable - The status of 802.1x port. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * RT_ERR_DOT1X_MACBASEDPNEN - 802.1X mac-based enable error + * Note: + * If a port is 802.1x MAC based network access control "enabled", the incoming packets should + * be authenticated so packets from that port won't be dropped or trapped to CPU. + * The status of 802.1x MAC-based network access control is as following: + * - DISABLED + * - ENABLED + */ +rtk_api_ret_t dal_rtl8367c_dot1x_macBasedEnable_set(rtk_port_t port, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check port Valid */ + RTK_CHK_PORT_VALID(port); + + if (enable >= RTK_ENABLE_END) + return RT_ERR_ENABLE; + + if ((retVal = rtl8367c_setAsic1xMBEnConfig(rtk_switch_port_L2P_get(port),enable)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_dot1x_macBasedEnable_get + * Description: + * Get 802.1x mac-based port enable configuration + * Input: + * port - Port id. + * Output: + * pEnable - The status of 802.1x port. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * If a port is 802.1x MAC based network access control "enabled", the incoming packets should + * be authenticated so packets from that port wont be dropped or trapped to CPU. + * The status of 802.1x MAC-based network access control is as following: + * - DISABLED + * - ENABLED + */ +rtk_api_ret_t dal_rtl8367c_dot1x_macBasedEnable_get(rtk_port_t port, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pEnable) + return RT_ERR_NULL_POINTER; + + /* Check port Valid */ + RTK_CHK_PORT_VALID(port); + + if ((retVal = rtl8367c_getAsic1xMBEnConfig(rtk_switch_port_L2P_get(port), pEnable)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_dot1x_macBasedAuthMac_add + * Description: + * Add an authenticated MAC to ASIC + * Input: + * port - Port id. + * pAuth_mac - The authenticated MAC. + * fid - filtering database. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * RT_ERR_DOT1X_MACBASEDPNEN - 802.1X mac-based enable error + * Note: + * The API can add a 802.1x authenticated MAC address to port. If the MAC does not exist in LUT, + * user can't add this MAC to auth status. + */ +rtk_api_ret_t dal_rtl8367c_dot1x_macBasedAuthMac_add(rtk_port_t port, rtk_mac_t *pAuth_mac, rtk_fid_t fid) +{ + rtk_api_ret_t retVal; + rtk_uint32 method; + rtl8367c_luttb l2Table; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* must be unicast address */ + if ((pAuth_mac == NULL) || (pAuth_mac->octet[0] & 0x1)) + return RT_ERR_MAC; + + /* Check port Valid */ + RTK_CHK_PORT_VALID(port); + + if (fid > RTL8367C_FIDMAX) + return RT_ERR_L2_FID; + + memset(&l2Table, 0, sizeof(rtl8367c_luttb)); + + /* fill key (MAC,FID) to get L2 entry */ + memcpy(l2Table.mac.octet, pAuth_mac->octet, ETHER_ADDR_LEN); + l2Table.fid = fid; + method = LUTREADMETHOD_MAC; + retVal = rtl8367c_getAsicL2LookupTb(method, &l2Table); + if ( RT_ERR_OK == retVal) + { + if (l2Table.spa != rtk_switch_port_L2P_get(port)) + return RT_ERR_DOT1X_MAC_PORT_MISMATCH; + + memcpy(l2Table.mac.octet, pAuth_mac->octet, ETHER_ADDR_LEN); + l2Table.fid = fid; + l2Table.efid = 0; + l2Table.auth = 1; + retVal = rtl8367c_setAsicL2LookupTb(&l2Table); + return retVal; + } + else + return retVal; + +} + +/* Function Name: + * dal_rtl8367c_dot1x_macBasedAuthMac_del + * Description: + * Delete an authenticated MAC to ASIC + * Input: + * port - Port id. + * pAuth_mac - The authenticated MAC. + * fid - filtering database. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can delete a 802.1x authenticated MAC address to port. It only change the auth status of + * the MAC and won't delete it from LUT. + */ +rtk_api_ret_t dal_rtl8367c_dot1x_macBasedAuthMac_del(rtk_port_t port, rtk_mac_t *pAuth_mac, rtk_fid_t fid) +{ + rtk_api_ret_t retVal; + rtk_uint32 method; + rtl8367c_luttb l2Table; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* must be unicast address */ + if ((pAuth_mac == NULL) || (pAuth_mac->octet[0] & 0x1)) + return RT_ERR_MAC; + + /* Check port Valid */ + RTK_CHK_PORT_VALID(port); + + if (fid > RTL8367C_FIDMAX) + return RT_ERR_L2_FID; + + memset(&l2Table, 0, sizeof(rtl8367c_luttb)); + + /* fill key (MAC,FID) to get L2 entry */ + memcpy(l2Table.mac.octet, pAuth_mac->octet, ETHER_ADDR_LEN); + l2Table.fid = fid; + method = LUTREADMETHOD_MAC; + retVal = rtl8367c_getAsicL2LookupTb(method, &l2Table); + if (RT_ERR_OK == retVal) + { + if (l2Table.spa != rtk_switch_port_L2P_get(port)) + return RT_ERR_DOT1X_MAC_PORT_MISMATCH; + + memcpy(l2Table.mac.octet, pAuth_mac->octet, ETHER_ADDR_LEN); + l2Table.fid = fid; + l2Table.auth = 0; + retVal = rtl8367c_setAsicL2LookupTb(&l2Table); + return retVal; + } + else + return retVal; + +} + +/* Function Name: + * dal_rtl8367c_dot1x_macBasedDirection_set + * Description: + * Set 802.1x mac-based operational direction configuration + * Input: + * mac_direction - Operation direction + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_DOT1X_MACBASEDOPDIR - 802.1X mac-based operation direction error + * Note: + * The operate controlled direction of 802.1x mac-based network access control is as following: + * - BOTH + * - IN + */ +rtk_api_ret_t dal_rtl8367c_dot1x_macBasedDirection_set(rtk_dot1x_direction_t mac_direction) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (mac_direction >= DIRECTION_END) + return RT_ERR_DOT1X_MACBASEDOPDIR; + + if ((retVal = rtl8367c_setAsic1xMBOpdirConfig(mac_direction)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_dot1x_macBasedDirection_get + * Description: + * Get 802.1x mac-based operational direction configuration + * Input: + * port - Port id. + * Output: + * pMac_direction - Operation direction + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get 802.1x mac-based operational direction information. + */ +rtk_api_ret_t dal_rtl8367c_dot1x_macBasedDirection_get(rtk_dot1x_direction_t *pMac_direction) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pMac_direction) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsic1xMBOpdirConfig(pMac_direction)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * Set 802.1x guest VLAN configuration + * Description: + * Set 802.1x mac-based operational direction configuration + * Input: + * vid - 802.1x guest VLAN ID + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * Note: + * The operate controlled 802.1x guest VLAN + */ +rtk_api_ret_t dal_rtl8367c_dot1x_guestVlan_set(rtk_vlan_t vid) +{ + rtk_api_ret_t retVal; + rtk_uint32 index; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* vid must be 0~4095 */ + if (vid > RTL8367C_VIDMAX) + return RT_ERR_VLAN_VID; + + if((retVal = dal_rtl8367c_vlan_checkAndCreateMbr(vid, &index)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsic1xGuestVidx(index)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_dot1x_guestVlan_get + * Description: + * Get 802.1x guest VLAN configuration + * Input: + * None + * Output: + * pVid - 802.1x guest VLAN ID + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get 802.1x guest VLAN information. + */ +rtk_api_ret_t dal_rtl8367c_dot1x_guestVlan_get(rtk_vlan_t *pVid) +{ + rtk_api_ret_t retVal; + rtk_uint32 gvidx; + rtl8367c_vlanconfiguser vlanMC; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pVid) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsic1xGuestVidx(&gvidx)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_getAsicVlanMemberConfig(gvidx, &vlanMC)) != RT_ERR_OK) + return retVal; + + *pVid = vlanMC.evid; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_dot1x_guestVlan2Auth_set + * Description: + * Set 802.1x guest VLAN to auth host configuration + * Input: + * enable - The status of guest VLAN to auth host. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * Note: + * The operational direction of 802.1x guest VLAN to auth host control is as following: + * - ENABLED + * - DISABLED + */ +rtk_api_ret_t dal_rtl8367c_dot1x_guestVlan2Auth_set(rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (enable >= RTK_ENABLE_END) + return RT_ERR_ENABLE; + + if ((retVal = rtl8367c_setAsic1xGVOpdir(enable)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_dot1x_guestVlan2Auth_get + * Description: + * Get 802.1x guest VLAN to auth host configuration + * Input: + * None + * Output: + * pEnable - The status of guest VLAN to auth host. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get 802.1x guest VLAN to auth host information. + */ +rtk_api_ret_t dal_rtl8367c_dot1x_guestVlan2Auth_get(rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pEnable) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsic1xGVOpdir(pEnable)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_dot1x.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_dot1x.h new file mode 100644 index 00000000..b85829c0 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_dot1x.h @@ -0,0 +1,449 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8367/RTL8367C switch high-level API + * + * Feature : The file includes 1X module high-layer API defination + * + */ + +#ifndef __DAL_RTL8367C_DOT1X_H__ +#define __DAL_RTL8367C_DOT1X_H__ + +#include + +/* Function Name: + * dal_rtl8367c_dot1x_unauthPacketOper_set + * Description: + * Set 802.1x unauth action configuration. + * Input: + * port - Port id. + * unauth_action - 802.1X unauth action. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameter. + * Note: + * This API can set 802.1x unauth action configuration. + * The unauth action is as following: + * - DOT1X_ACTION_DROP + * - DOT1X_ACTION_TRAP2CPU + * - DOT1X_ACTION_GUESTVLAN + */ +extern rtk_api_ret_t dal_rtl8367c_dot1x_unauthPacketOper_set(rtk_port_t port, rtk_dot1x_unauth_action_t unauth_action); + +/* Function Name: + * dal_rtl8367c_dot1x_unauthPacketOper_get + * Description: + * Get 802.1x unauth action configuration. + * Input: + * port - Port id. + * Output: + * pUnauth_action - 802.1X unauth action. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can get 802.1x unauth action configuration. + * The unauth action is as following: + * - DOT1X_ACTION_DROP + * - DOT1X_ACTION_TRAP2CPU + * - DOT1X_ACTION_GUESTVLAN + */ +extern rtk_api_ret_t dal_rtl8367c_dot1x_unauthPacketOper_get(rtk_port_t port, rtk_dot1x_unauth_action_t *pUnauth_action); + +/* Function Name: + * dal_rtl8367c_dot1x_eapolFrame2CpuEnable_set + * Description: + * Set 802.1x EAPOL packet trap to CPU configuration + * Input: + * enable - The status of 802.1x EAPOL packet. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * To support 802.1x authentication functionality, EAPOL frame (ether type = 0x888E) has to + * be trapped to CPU. + * The status of EAPOL frame trap to CPU is as following: + * - DISABLED + * - ENABLED + */ +extern rtk_api_ret_t dal_rtl8367c_dot1x_eapolFrame2CpuEnable_set(rtk_enable_t enable); + +/* Function Name: + * dal_rtl8367c_dot1x_eapolFrame2CpuEnable_get + * Description: + * Get 802.1x EAPOL packet trap to CPU configuration + * Input: + * None + * Output: + * pEnable - The status of 802.1x EAPOL packet. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * To support 802.1x authentication functionality, EAPOL frame (ether type = 0x888E) has to + * be trapped to CPU. + * The status of EAPOL frame trap to CPU is as following: + * - DISABLED + * - ENABLED + */ +extern rtk_api_ret_t dal_rtl8367c_dot1x_eapolFrame2CpuEnable_get(rtk_enable_t *pEnable); + +/* Function Name: + * dal_rtl8367c_dot1x_portBasedEnable_set + * Description: + * Set 802.1x port-based enable configuration + * Input: + * port - Port id. + * enable - The status of 802.1x port. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * RT_ERR_DOT1X_PORTBASEDPNEN - 802.1X port-based enable error + * Note: + * The API can update the port-based port enable register content. If a port is 802.1x + * port based network access control "enabled", it should be authenticated so packets + * from that port won't be dropped or trapped to CPU. + * The status of 802.1x port-based network access control is as following: + * - DISABLED + * - ENABLED + */ +extern rtk_api_ret_t dal_rtl8367c_dot1x_portBasedEnable_set(rtk_port_t port, rtk_enable_t enable); + +/* Function Name: + * dal_rtl8367c_dot1x_portBasedEnable_get + * Description: + * Get 802.1x port-based enable configuration + * Input: + * port - Port id. + * Output: + * pEnable - The status of 802.1x port. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get the 802.1x port-based port status. + */ +extern rtk_api_ret_t dal_rtl8367c_dot1x_portBasedEnable_get(rtk_port_t port, rtk_enable_t *pEnable); + +/* Function Name: + * dal_rtl8367c_dot1x_portBasedAuthStatus_set + * Description: + * Set 802.1x port-based auth. port configuration + * Input: + * port - Port id. + * port_auth - The status of 802.1x port. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_DOT1X_PORTBASEDAUTH - 802.1X port-based auth error + * Note: + * The authenticated status of 802.1x port-based network access control is as following: + * - UNAUTH + * - AUTH + */ +extern rtk_api_ret_t dal_rtl8367c_dot1x_portBasedAuthStatus_set(rtk_port_t port, rtk_dot1x_auth_status_t port_auth); + +/* Function Name: + * dal_rtl8367c_dot1x_portBasedAuthStatus_get + * Description: + * Get 802.1x port-based auth. port configuration + * Input: + * port - Port id. + * Output: + * pPort_auth - The status of 802.1x port. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get 802.1x port-based port auth.information. + */ +extern rtk_api_ret_t dal_rtl8367c_dot1x_portBasedAuthStatus_get(rtk_port_t port, rtk_dot1x_auth_status_t *pPort_auth); + +/* Function Name: + * dal_rtl8367c_dot1x_portBasedDirection_set + * Description: + * Set 802.1x port-based operational direction configuration + * Input: + * port - Port id. + * port_direction - Operation direction + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_DOT1X_PORTBASEDOPDIR - 802.1X port-based operation direction error + * Note: + * The operate controlled direction of 802.1x port-based network access control is as following: + * - BOTH + * - IN + */ +extern rtk_api_ret_t dal_rtl8367c_dot1x_portBasedDirection_set(rtk_port_t port, rtk_dot1x_direction_t port_direction); + +/* Function Name: + * dal_rtl8367c_dot1x_portBasedDirection_get + * Description: + * Get 802.1X port-based operational direction configuration + * Input: + * port - Port id. + * Output: + * pPort_direction - Operation direction + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get 802.1x port-based operational direction information. + */ +extern rtk_api_ret_t dal_rtl8367c_dot1x_portBasedDirection_get(rtk_port_t port, rtk_dot1x_direction_t *pPort_direction); + +/* Function Name: + * dal_rtl8367c_dot1x_macBasedEnable_set + * Description: + * Set 802.1x mac-based port enable configuration + * Input: + * port - Port id. + * enable - The status of 802.1x port. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * RT_ERR_DOT1X_MACBASEDPNEN - 802.1X mac-based enable error + * Note: + * If a port is 802.1x MAC based network access control "enabled", the incoming packets should + * be authenticated so packets from that port won't be dropped or trapped to CPU. + * The status of 802.1x MAC-based network access control is as following: + * - DISABLED + * - ENABLED + */ +extern rtk_api_ret_t dal_rtl8367c_dot1x_macBasedEnable_set(rtk_port_t port, rtk_enable_t enable); + +/* Function Name: + * dal_rtl8367c_dot1x_macBasedEnable_get + * Description: + * Get 802.1x mac-based port enable configuration + * Input: + * port - Port id. + * Output: + * pEnable - The status of 802.1x port. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * If a port is 802.1x MAC based network access control "enabled", the incoming packets should + * be authenticated so packets from that port wont be dropped or trapped to CPU. + * The status of 802.1x MAC-based network access control is as following: + * - DISABLED + * - ENABLED + */ +extern rtk_api_ret_t dal_rtl8367c_dot1x_macBasedEnable_get(rtk_port_t port, rtk_enable_t *pEnable); + +/* Function Name: + * dal_rtl8367c_dot1x_macBasedAuthMac_add + * Description: + * Add an authenticated MAC to ASIC + * Input: + * port - Port id. + * pAuth_mac - The authenticated MAC. + * fid - filtering database. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * RT_ERR_DOT1X_MACBASEDPNEN - 802.1X mac-based enable error + * Note: + * The API can add a 802.1x authenticated MAC address to port. If the MAC does not exist in LUT, + * user can't add this MAC to auth status. + */ +extern rtk_api_ret_t dal_rtl8367c_dot1x_macBasedAuthMac_add(rtk_port_t port, rtk_mac_t *pAuth_mac, rtk_fid_t fid); + +/* Function Name: + * dal_rtl8367c_dot1x_macBasedAuthMac_del + * Description: + * Delete an authenticated MAC to ASIC + * Input: + * port - Port id. + * pAuth_mac - The authenticated MAC. + * fid - filtering database. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can delete a 802.1x authenticated MAC address to port. It only change the auth status of + * the MAC and won't delete it from LUT. + */ +extern rtk_api_ret_t dal_rtl8367c_dot1x_macBasedAuthMac_del(rtk_port_t port, rtk_mac_t *pAuth_mac, rtk_fid_t fid); + +/* Function Name: + * dal_rtl8367c_dot1x_macBasedDirection_set + * Description: + * Set 802.1x mac-based operational direction configuration + * Input: + * mac_direction - Operation direction + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_DOT1X_MACBASEDOPDIR - 802.1X mac-based operation direction error + * Note: + * The operate controlled direction of 802.1x mac-based network access control is as following: + * - BOTH + * - IN + */ +extern rtk_api_ret_t dal_rtl8367c_dot1x_macBasedDirection_set(rtk_dot1x_direction_t mac_direction); + +/* Function Name: + * dal_rtl8367c_dot1x_macBasedDirection_get + * Description: + * Get 802.1x mac-based operational direction configuration + * Input: + * port - Port id. + * Output: + * pMac_direction - Operation direction + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get 802.1x mac-based operational direction information. + */ +extern rtk_api_ret_t dal_rtl8367c_dot1x_macBasedDirection_get(rtk_dot1x_direction_t *pMac_direction); + +/* Function Name: + * Set 802.1x guest VLAN configuration + * Description: + * Set 802.1x mac-based operational direction configuration + * Input: + * vid - 802.1x guest VLAN ID + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * Note: + * The operate controlled 802.1x guest VLAN + */ +extern rtk_api_ret_t dal_rtl8367c_dot1x_guestVlan_set(rtk_vlan_t vid); + +/* Function Name: + * dal_rtl8367c_dot1x_guestVlan_get + * Description: + * Get 802.1x guest VLAN configuration + * Input: + * None + * Output: + * pVid - 802.1x guest VLAN ID + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get 802.1x guest VLAN information. + */ +extern rtk_api_ret_t dal_rtl8367c_dot1x_guestVlan_get(rtk_vlan_t *pVid); + +/* Function Name: + * dal_rtl8367c_dot1x_guestVlan2Auth_set + * Description: + * Set 802.1x guest VLAN to auth host configuration + * Input: + * enable - The status of guest VLAN to auth host. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * Note: + * The operational direction of 802.1x guest VLAN to auth host control is as following: + * - ENABLED + * - DISABLED + */ +extern rtk_api_ret_t dal_rtl8367c_dot1x_guestVlan2Auth_set(rtk_enable_t enable); + +/* Function Name: + * dal_rtl8367c_dot1x_guestVlan2Auth_get + * Description: + * Get 802.1x guest VLAN to auth host configuration + * Input: + * None + * Output: + * pEnable - The status of guest VLAN to auth host. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get 802.1x guest VLAN to auth host information. + */ +extern rtk_api_ret_t dal_rtl8367c_dot1x_guestVlan2Auth_get(rtk_enable_t *pEnable); + + +#endif /* __DAL_RTL8367C_DOT1X_H__ */ + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_eee.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_eee.c new file mode 100644 index 00000000..a01b8df7 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_eee.c @@ -0,0 +1,162 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8367C + * Feature : Here is a list of all functions and variables in EEE module. + * + */ + +#include +#include +#include +#include + +#include +#include +#include + +/* Function Name: + * dal_rtl8367c_eee_init + * Description: + * EEE function initialization. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API is used to initialize EEE status. + */ +rtk_api_ret_t dal_rtl8367c_eee_init(void) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if((retVal = rtl8367c_setAsicRegBit(0x0018, 10, 1)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicRegBit(0x0018, 11, 1)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_eee_portEnable_set + * Description: + * Set enable status of EEE function. + * Input: + * port - port id. + * enable - enable EEE status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * This API can set EEE function to the specific port. + * The configuration of the port is as following: + * - DISABLE + * - ENABLE + */ +rtk_api_ret_t dal_rtl8367c_eee_portEnable_set(rtk_port_t port, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + rtk_uint32 phy_port; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check port is UTP port */ + RTK_CHK_PORT_IS_UTP(port); + + if (enable>=RTK_ENABLE_END) + return RT_ERR_INPUT; + + phy_port = rtk_switch_port_L2P_get(port); + + if ((retVal = rtl8367c_setAsicEee100M(phy_port,enable))!=RT_ERR_OK) + return retVal; + if ((retVal = rtl8367c_setAsicEeeGiga(phy_port,enable))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicPHYReg(phy_port, RTL8367C_PHY_PAGE_ADDRESS, 0))!=RT_ERR_OK) + return retVal; + if ((retVal = rtl8367c_getAsicPHYReg(phy_port, 0, ®Data))!=RT_ERR_OK) + return retVal; + regData |= 0x0200; + if ((retVal = rtl8367c_setAsicPHYReg(phy_port, 0, regData))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_eee_portEnable_get + * Description: + * Get enable status of EEE function + * Input: + * port - Port id. + * Output: + * pEnable - Back pressure status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can get EEE function to the specific port. + * The configuration of the port is as following: + * - DISABLE + * - ENABLE + */ +rtk_api_ret_t dal_rtl8367c_eee_portEnable_get(rtk_port_t port, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData1, regData2; + rtk_uint32 phy_port; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check port is UTP port */ + RTK_CHK_PORT_IS_UTP(port); + + if(NULL == pEnable) + return RT_ERR_NULL_POINTER; + + phy_port = rtk_switch_port_L2P_get(port); + + if ((retVal = rtl8367c_getAsicEee100M(phy_port,®Data1))!=RT_ERR_OK) + return retVal; + if ((retVal = rtl8367c_getAsicEeeGiga(phy_port,®Data2))!=RT_ERR_OK) + return retVal; + + if (regData1==1&®Data2==1) + *pEnable = ENABLED; + else + *pEnable = DISABLED; + + return RT_ERR_OK; +} + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_eee.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_eee.h new file mode 100644 index 00000000..3f0585aa --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_eee.h @@ -0,0 +1,84 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8367/RTL8367C switch high-level API + * + * Feature : The file includes EEE module high-layer API defination + * + */ + +#ifndef __DAL_RTL8367C_EEE_H__ +#define __DAL_RTL8367C_EEE_H__ + +/* Function Name: + * dal_rtl8367c_eee_init + * Description: + * EEE function initialization. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API is used to initialize EEE status. + */ +extern rtk_api_ret_t dal_rtl8367c_eee_init(void); + +/* Function Name: + * dal_rtl8367c_eee_portEnable_set + * Description: + * Set enable status of EEE function. + * Input: + * port - port id. + * enable - enable EEE status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * This API can set EEE function to the specific port. + * The configuration of the port is as following: + * - DISABLE + * - ENABLE + */ +extern rtk_api_ret_t dal_rtl8367c_eee_portEnable_set(rtk_port_t port, rtk_enable_t enable); + +/* Function Name: + * dal_rtl8367c_eee_portEnable_get + * Description: + * Get port admin configuration of the specific port. + * Input: + * port - Port id. + * Output: + * pEnable - Back pressure status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can set EEE function to the specific port. + * The configuration of the port is as following: + * - DISABLE + * - ENABLE + */ +extern rtk_api_ret_t dal_rtl8367c_eee_portEnable_get(rtk_port_t port, rtk_enable_t *pEnable); + + +#endif /* __DAL_RTL8367C_EEE_H__ */ + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_gpio.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_gpio.c new file mode 100644 index 00000000..478d0401 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_gpio.c @@ -0,0 +1,421 @@ +/* + * Copyright (C) 2019 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8367C + * Feature : Here is a list of all functions and variables in GPIO module. + * + */ + +#include +#include +#include +#include +#include + +/* Function Name: + * dal_rtl8367c_gpio_input_get + * Description: + * Get gpio input + * Input: + * pin - GPIO pin + * Output: + * pInput - GPIO input + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_NULL_POINTER - input parameter is null pointer. + * Note: + * None + */ +rtk_api_ret_t dal_rtl8367c_gpio_input_get(rtk_uint32 pin, rtk_uint32 *pInput) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(pin >= RTL8367C_GPIOPINNO) + return RT_ERR_OUT_OF_RANGE; + + if(NULL == pInput) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_GPIO_67C_I_X0 + (pin / 16), (pin % 16), pInput)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_gpio_output_set + * Description: + * Set GPIO output value. + * Input: + * pin - GPIO pin + * output - 1 or 0 + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_OUT_OF_RANGE - input parameter out of range. + * Note: + * The API can set GPIO pin output 1 or 0. + */ +rtk_api_ret_t dal_rtl8367c_gpio_output_set(rtk_uint32 pin, rtk_uint32 output) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(pin >= RTL8367C_GPIOPINNO) + return RT_ERR_OUT_OF_RANGE; + + if (output > 1) + return RT_ERR_INPUT; + + if ((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_GPIO_67C_O_X0 + (pin / 16), (pin % 16), output)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_gpio_output_get + * Description: + * Get GPIO output. + * Input: + * pin - GPIO pin + * Output: + * pOutput - GPIO output + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_OUT_OF_RANGE - input parameter out of range. + * RT_ERR_NULL_POINTER - input parameter is null pointer. + * Note: + * The API can get GPIO output. + */ +rtk_api_ret_t dal_rtl8367c_gpio_output_get(rtk_uint32 pin, rtk_uint32 *pOutput) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(pin >= RTL8367C_GPIOPINNO) + return RT_ERR_OUT_OF_RANGE; + + if(NULL == pOutput) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_GPIO_67C_O_X0 + (pin / 16), (pin % 16), pOutput)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_gpio_state_set + * Description: + * Set GPIO control. + * Input: + * pin - GPIO pin + * state - GPIO enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_OUT_OF_RANGE - input parameter out of range. + * RT_ERR_ENABLE - invalid enable parameter . + * Note: + * The API can set GPIO pin output 1 or 0. + */ +rtk_api_ret_t dal_rtl8367c_gpio_state_set(rtk_uint32 pin, rtk_enable_t state) +{ + rtk_api_ret_t retVal; + rtk_uint32 gpioState; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(pin >= RTL8367C_GPIOPINNO) + return RT_ERR_OUT_OF_RANGE; + + switch (state) + { + case DISABLED: + gpioState = 0; + break; + case ENABLED: + gpioState = 1; + break; + default: + return RT_ERR_ENABLE; + } + + if ((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_GPIO_MODE_67C_X0 + (pin / 16), (pin % 16), gpioState)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_gpio_state_get + * Description: + * Get GPIO enable state. + * Input: + * pin - GPIO pin + * Output: + * pState - GPIO enable + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_OUT_OF_RANGE - input parameter out of range. + * RT_ERR_NULL_POINTER - input parameter is null pointer. + * Note: + * The API can get GPIO enable state. + */ +rtk_api_ret_t dal_rtl8367c_gpio_state_get(rtk_uint32 pin, rtk_enable_t *pState) +{ + rtk_api_ret_t retVal; + rtk_uint32 gpioState; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(pin >= RTL8367C_GPIOPINNO) + return RT_ERR_OUT_OF_RANGE; + + if(NULL == pState) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_GPIO_MODE_67C_X0 + (pin / 16), (pin % 16), &gpioState)) != RT_ERR_OK) + return retVal; + + switch (gpioState) + { + case 0: + *pState = DISABLED; + break; + case 1: + *pState = ENABLED; + break; + default: + return RT_ERR_FAILED; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_gpio_mode_set + * Description: + * Set GPIO mode. + * Input: + * pin - GPIO pin + * mode - 1 or 0 + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_OUT_OF_RANGE - input parameter out of range. + * Note: + * The API can set GPIO to input or output mode. + */ +rtk_api_ret_t dal_rtl8367c_gpio_mode_set(rtk_uint32 pin, rtk_gpio_mode_t mode) +{ + rtk_api_ret_t retVal; + rtk_uint32 gpioMode; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(pin >= RTL8367C_GPIOPINNO) + return RT_ERR_OUT_OF_RANGE; + + switch (mode) + { + case GPIO_MODE_OUTPUT: + gpioMode = 0; + break; + case GPIO_MODE_INPUT: + gpioMode = 1; + break; + default: + return RT_ERR_INPUT; + } + + if ((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_GPIO_67C_OE_X0 + (pin / 16), (pin % 16), gpioMode)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_gpio_mode_get + * Description: + * Get GPIO mode. + * Input: + * pin - GPIO pin + * Output: + * pMode - GPIO mode + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_OUT_OF_RANGE - input parameter out of range. + * RT_ERR_NULL_POINTER - input parameter is null pointer. + * Note: + * The API can get GPIO mode. + */ +rtk_api_ret_t dal_rtl8367c_gpio_mode_get(rtk_uint32 pin, rtk_gpio_mode_t *pMode) +{ + rtk_api_ret_t retVal; + rtk_uint32 gpioMode; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(pin >= RTL8367C_GPIOPINNO) + return RT_ERR_OUT_OF_RANGE; + + if(NULL == pMode) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_GPIO_67C_OE_X0 + (pin / 16), (pin % 16), &gpioMode)) != RT_ERR_OK) + return retVal; + + switch (gpioMode) + { + case 0: + *pMode = GPIO_MODE_OUTPUT; + break; + case 1: + *pMode = GPIO_MODE_INPUT; + break; + default: + return RT_ERR_FAILED; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_gpio_aclEnClear_set + * Description: + * Set GPIO acl clear. + * Input: + * pin - GPIO pin + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_OUT_OF_RANGE - input parameter out of range. + * Note: + * The API can set GPIO ACL clear. + */ +rtk_api_ret_t dal_rtl8367c_gpio_aclEnClear_set(rtk_uint32 pin) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(pin > RTL8367C_ACLGPIOPINNO) + return RT_ERR_OUT_OF_RANGE; + + /* Enable */ + if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_EN_GPIO, pin, 1)) != RT_ERR_OK) + return retVal; + + /* ACL clear */ + if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_ACL_GPIO, pin, 1)) != RT_ERR_OK) + return retVal; + + /* Control by asic */ + if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_SEL_GPIO, pin, 0)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_gpio_aclEnClear_get + * Description: + * Get GPIO acl clear. + * Input: + * pin - GPIO pin + * Output: + * pAclEn - GPIO acl enable + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_OUT_OF_RANGE - input parameter out of range. + * RT_ERR_NULL_POINTER - input parameter is null pointer. + * Note: + * The API can get GPIO acl enable clear. + */ +rtk_api_ret_t dal_rtl8367c_gpio_aclEnClear_get(rtk_uint32 pin, rtk_enable_t *pAclEn) +{ + rtk_api_ret_t retVal; + rtk_uint32 data; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(pin >= RTL8367C_GPIOPINNO) + return RT_ERR_OUT_OF_RANGE; + + if(NULL == pAclEn) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_ACL_GPIO, pin, &data)) != RT_ERR_OK) + return retVal; + + switch (data) + { + case 0: + *pAclEn = DISABLED; + break; + case 1: + *pAclEn = ENABLED; + break; + default: + return RT_ERR_FAILED; + } + + return RT_ERR_OK; +} + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_gpio.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_gpio.h new file mode 100644 index 00000000..4f26b991 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_gpio.h @@ -0,0 +1,194 @@ + + +#ifndef __DAL_RTL8367C_GPIO_H__ +#define __DAL_RTL8367C_GPIO_H__ + +/* + * Include Files + */ +#include + +#define RTL8367C_GPIOPINNO 62 +#define RTL8367C_GPIOPINMAX (RTL8367C_GPIOPINNO-1) +#define RTL8367C_ACLGPIOPINNO 13 + +/* Function Name: + * dal_rtl8367c_gpio_input_get + * Description: + * Get gpio input + * Input: + * pin - GPIO pin + * Output: + * pInput - GPIO input + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_NULL_POINTER - input parameter is null pointer. + * Note: + * None + */ +extern rtk_api_ret_t dal_rtl8367c_gpio_input_get(rtk_uint32 pin, rtk_uint32 *pInput); + +/* Function Name: + * dal_rtl8367c_gpio_output_set + * Description: + * Set GPIO output value. + * Input: + * pin - GPIO pin + * output - 1 or 0 + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_OUT_OF_RANGE - input parameter out of range. + * Note: + * The API can set GPIO pin output 1 or 0. + */ +extern rtk_api_ret_t dal_rtl8367c_gpio_output_set(rtk_uint32 pin, rtk_uint32 output); + +/* Function Name: + * dal_rtl8367c_gpio_output_get + * Description: + * Get GPIO output. + * Input: + * pin - GPIO pin + * Output: + * pOutput - GPIO output + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_OUT_OF_RANGE - input parameter out of range. + * RT_ERR_NULL_POINTER - input parameter is null pointer. + * Note: + * The API can get GPIO output. + */ +extern rtk_api_ret_t dal_rtl8367c_gpio_output_get(rtk_uint32 pin, rtk_uint32 *pOutput); + +/* Function Name: + * dal_rtl8367c_gpio_state_set + * Description: + * Set GPIO control. + * Input: + * pin - GPIO pin + * state - GPIO enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_OUT_OF_RANGE - input parameter out of range. + * RT_ERR_ENABLE - invalid enable parameter . + * Note: + * The API can set GPIO pin output 1 or 0. + */ +extern rtk_api_ret_t dal_rtl8367c_gpio_state_set(rtk_uint32 pin, rtk_enable_t state); + +/* Function Name: + * dal_rtl8367c_gpio_state_get + * Description: + * Get GPIO enable state. + * Input: + * pin - GPIO pin + * Output: + * pState - GPIO enable + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_OUT_OF_RANGE - input parameter out of range. + * RT_ERR_NULL_POINTER - input parameter is null pointer. + * Note: + * The API can get GPIO enable state. + */ +extern rtk_api_ret_t dal_rtl8367c_gpio_state_get(rtk_uint32 pin, rtk_enable_t *pState); + +/* Function Name: + * dal_rtl8367c_gpio_mode_set + * Description: + * Set GPIO mode. + * Input: + * pin - GPIO pin + * mode - 1 or 0 + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_OUT_OF_RANGE - input parameter out of range. + * Note: + * The API can set GPIO to input or output mode. + */ +extern rtk_api_ret_t dal_rtl8367c_gpio_mode_set(rtk_uint32 pin, rtk_gpio_mode_t mode); + +/* Function Name: + * dal_rtl8367c_gpio_mode_get + * Description: + * Get GPIO mode. + * Input: + * pin - GPIO pin + * Output: + * pMode - GPIO mode + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_OUT_OF_RANGE - input parameter out of range. + * RT_ERR_NULL_POINTER - input parameter is null pointer. + * Note: + * The API can get GPIO mode. + */ +extern rtk_api_ret_t dal_rtl8367c_gpio_mode_get(rtk_uint32 pin, rtk_gpio_mode_t *pMode); + +/* Function Name: + * dal_rtl8367c_gpio_aclEnClear_set + * Description: + * Set GPIO acl clear. + * Input: + * pin - GPIO pin + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_OUT_OF_RANGE - input parameter out of range. + * Note: + * The API can set GPIO ACL clear. + */ +extern rtk_api_ret_t dal_rtl8367c_gpio_aclEnClear_set(rtk_uint32 pin); + +/* Function Name: + * dal_rtl8367c_gpio_aclEnClear_get + * Description: + * Get GPIO acl clear. + * Input: + * pin - GPIO pin + * Output: + * pAclEn - GPIO acl enable + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_OUT_OF_RANGE - input parameter out of range. + * RT_ERR_NULL_POINTER - input parameter is null pointer. + * Note: + * The API can get GPIO acl enable clear. + */ +extern rtk_api_ret_t dal_rtl8367c_gpio_aclEnClear_get(rtk_uint32 pin, rtk_enable_t *pAclEn); + +#endif /* __DAL_RTL8367C_GPIO_H__ */ + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_i2c.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_i2c.c new file mode 100644 index 00000000..a4044b29 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_i2c.c @@ -0,0 +1,415 @@ +/* Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision: 63932 $ + * $Date: 2015-12-08 14:06:29 +0800 (周二, 08 å二月 2015) $ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8367C + * Feature : Here is a list of all functions and variables in i2c module. + * + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + + +static rtk_I2C_16bit_mode_t rtk_i2c_mode = I2C_LSB_16BIT_MODE; + + +/* Function Name: + * dal_rtl8367c_i2c_init + * Description: + * I2C smart function initialization. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * Note: + * This API is used to initialize EEE status. + * need used GPIO pins + * OpenDrain and clock + */ +rtk_api_ret_t dal_rtl8367c_i2c_init(void) +{ + rtk_uint32 retVal; + + /* probe switch */ + if(rtk_switch_chipType_get() == CHIP_RTL8370B ) + { + /*set GPIO8, GPIO9, OpenDrain as I2C, clock = 124KHZ */ + if((retVal = rtl8367c_setAsicReg(RTL8367C_REG_M_I2C_SYS_CTL, 0x5c3f)) != RT_ERR_OK) + return retVal; + } + else + return RT_ERR_FAILED; + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_i2c_mode_set + * Description: + * Set I2C data byte-order. + * Input: + * i2cmode - byte-order mode + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_INPUT - Invalid input parameter. + * Note: + * This API can set I2c traffic's byte-order . + */ +rtk_api_ret_t dal_rtl8367c_i2c_mode_set( rtk_I2C_16bit_mode_t i2cmode ) +{ + if(i2cmode >= I2C_Mode_END) + return RT_ERR_INPUT; + + rtk_i2c_mode = i2cmode; + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_i2c_mode_get + * Description: + * Get i2c traffic byte-order setting. + * Input: + * None + * Output: + * pI2cMode - i2c byte-order + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_NULL_POINTER - input parameter is null pointer + * Note: + * The API can get i2c traffic byte-order setting. + */ +rtk_api_ret_t dal_rtl8367c_i2c_mode_get( rtk_I2C_16bit_mode_t * pI2cMode) +{ + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + if(NULL == pI2cMode) + return RT_ERR_NULL_POINTER; + if(rtk_i2c_mode == I2C_70B_LSB_16BIT_MODE) + *pI2cMode = 1; + else if ((rtk_i2c_mode == I2C_LSB_16BIT_MODE)) + *pI2cMode = 0; + else + return RT_ERR_FAILED; + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_i2c_gpioPinGroup_set + * Description: + * Set i2c SDA & SCL used GPIO pins group. + * Input: + * pins_group - GPIO pins group + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_INPUT - Invalid input parameter. + * Note: + * The API can set i2c used gpio pins group. + * There are three group pins could be used + */ +rtk_api_ret_t dal_rtl8367c_i2c_gpioPinGroup_set( rtk_I2C_gpio_pin_t pins_group ) +{ + rtk_uint32 retVal; + + + if( ( pins_group > I2C_GPIO_PIN_END )|| ( pins_group < I2C_GPIO_PIN_8_9) ) + return RT_ERR_INPUT; + + if( (retVal = rtl8367c_setAsicI2CGpioPinGroup(pins_group) ) != RT_ERR_OK ) + return retVal ; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_i2c_gpioPinGroup_get + * Description: + * Get i2c SDA & SCL used GPIO pins group. + * Input: + * None + * Output: + * pPins_group - GPIO pins group + * Return: + * RT_ERR_OK - OK + * RT_ERR_NULL_POINTER - input parameter is null pointer + * Note: + * The API can get i2c used gpio pins group. + * There are three group pins could be used + */ +rtk_api_ret_t dal_rtl8367c_i2c_gpioPinGroup_get( rtk_I2C_gpio_pin_t * pPins_group ) +{ + rtk_uint32 retVal; + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pPins_group) + return RT_ERR_NULL_POINTER; + if( (retVal = rtl8367c_getAsicI2CGpioPinGroup(pPins_group) ) != RT_ERR_OK ) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_i2c_data_read + * Description: + * read i2c slave device register. + * Input: + * deviceAddr - access Slave device address + * slaveRegAddr - access Slave register address + * Output: + * pRegData - read data + * Return: + * RT_ERR_OK - OK + * RT_ERR_NULL_POINTER - input parameter is null pointer + * Note: + * The API can access i2c slave and read i2c slave device register. + */ +rtk_api_ret_t dal_rtl8367c_i2c_data_read(rtk_uint8 deviceAddr, rtk_uint32 slaveRegAddr, rtk_uint32 *pRegData) +{ + rtk_uint32 retVal, counter=0; + rtk_uint8 controlByte_W, controlByte_R; + rtk_uint8 slaveRegAddr_L, slaveRegAddr_H = 0x0, temp; + rtk_uint8 regData_L, regData_H; + + /* control byte :deviceAddress + W, deviceAddress + R */ + controlByte_W = (rtk_uint8)(deviceAddr << 1) ; + controlByte_R = (rtk_uint8)(controlByte_W | 0x1); + + slaveRegAddr_L = (rtk_uint8) (slaveRegAddr & 0x00FF) ; + slaveRegAddr_H = (rtk_uint8) (slaveRegAddr >>8) ; + + if( rtk_i2c_mode == I2C_70B_LSB_16BIT_MODE) + { + temp = slaveRegAddr_L ; + slaveRegAddr_L = slaveRegAddr_H; + slaveRegAddr_H = temp; + } + + + /*check bus state: idle*/ + for(counter = 3000; counter>0; counter--) + { + if ( (retVal = rtl8367c_setAsicI2C_checkBusIdle() ) == RT_ERR_OK) + break; + } + if( counter ==0 ) + return retVal; /*i2c is busy*/ + + /*tx Start cmd*/ + if( (retVal = rtl8367c_setAsicI2CStartCmd() ) != RT_ERR_OK ) + return retVal ; + + + /*tx control _W*/ + if( (retVal = rtl8367c_setAsicI2CTxOneCharCmd(controlByte_W))!= RT_ERR_OK ) + return retVal ; + + + /*check if RX ack from slave*/ + if( (retVal = rtl8367c_setAsicI2CcheckRxAck()) != RT_ERR_OK ) + return retVal; + + /* tx slave buffer address low 8 bits */ + if( (retVal = rtl8367c_setAsicI2CTxOneCharCmd(slaveRegAddr_L))!= RT_ERR_OK ) + return retVal ; + + /*check if RX ack from slave*/ + if( (retVal = rtl8367c_setAsicI2CcheckRxAck()) != RT_ERR_OK ) + return retVal; + + + + /* tx slave buffer address high 8 bits */ + if( (retVal = rtl8367c_setAsicI2CTxOneCharCmd(slaveRegAddr_H))!= RT_ERR_OK ) + return retVal ; + + + /*check if RX ack from slave*/ + if( (retVal = rtl8367c_setAsicI2CcheckRxAck()) != RT_ERR_OK ) + return retVal; + + + /*tx Start cmd*/ + if( (retVal = rtl8367c_setAsicI2CStartCmd() ) != RT_ERR_OK ) + return retVal ; + + /*tx control _R*/ + if( (retVal = rtl8367c_setAsicI2CTxOneCharCmd(controlByte_R))!= RT_ERR_OK ) + return retVal ; + + + /*check if RX ack from slave*/ + if( (retVal = rtl8367c_setAsicI2CcheckRxAck()) != RT_ERR_OK ) + return retVal; + + + /* rx low 8bit data*/ + if( ( retVal = rtl8367c_setAsicI2CRxOneCharCmd( ®Data_L) ) != RT_ERR_OK ) + return retVal; + + + + /* tx ack to slave, keep receive */ + if( (retVal = rtl8367c_setAsicI2CTxAckCmd()) != RT_ERR_OK ) + return retVal; + + /* rx high 8bit data*/ + if( ( retVal = rtl8367c_setAsicI2CRxOneCharCmd( ®Data_H) ) != RT_ERR_OK ) + return retVal; + + + + /* tx Noack to slave, Stop receive */ + if( (retVal = rtl8367c_setAsicI2CTxNoAckCmd()) != RT_ERR_OK ) + return retVal; + + + /*tx Stop cmd */ + if( (retVal = rtl8367c_setAsicI2CStopCmd()) != RT_ERR_OK ) + return retVal; + + *pRegData = (regData_H << 8) | regData_L; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_i2c_data_write + * Description: + * write data to i2c slave device register + * Input: + * deviceAddr - access Slave device address + * slaveRegAddr - access Slave register address + * regData - data to set + * Output: + * None + * Return: + * RT_ERR_OK - OK + * Note: + * The API can access i2c slave and setting i2c slave device register. + */ +rtk_api_ret_t dal_rtl8367c_i2c_data_write(rtk_uint8 deviceAddr, rtk_uint32 slaveRegAddr, rtk_uint32 regData) +{ + rtk_uint32 retVal,counter; + rtk_uint8 controlByte_W; + rtk_uint8 slaveRegAddr_L, slaveRegAddr_H = 0x0, temp; + rtk_uint8 regData_L, regData_H; + + /* control byte :deviceAddress + W */ + controlByte_W = (rtk_uint8)(deviceAddr<< 1) ; + + slaveRegAddr_L = (rtk_uint8) (slaveRegAddr & 0x00FF) ; + slaveRegAddr_H = (rtk_uint8) (slaveRegAddr >>8) ; + + regData_H = (rtk_uint8) (regData>> 8); + regData_L = (rtk_uint8) (regData & 0x00FF); + + if( rtk_i2c_mode == I2C_70B_LSB_16BIT_MODE) + { + temp = slaveRegAddr_L ; + slaveRegAddr_L = slaveRegAddr_H; + slaveRegAddr_H = temp; + } + + + /*check bus state: idle*/ + for(counter = 3000; counter>0; counter--) + { + if ( (retVal = rtl8367c_setAsicI2C_checkBusIdle() ) == RT_ERR_OK) + break; + } + + if( counter ==0 ) + return retVal; /*i2c is busy*/ + + + /*tx Start cmd*/ + if( (retVal = rtl8367c_setAsicI2CStartCmd() ) != RT_ERR_OK ) + return retVal ; + + + /*tx control _W*/ + if( (retVal = rtl8367c_setAsicI2CTxOneCharCmd(controlByte_W))!= RT_ERR_OK ) + return retVal ; + + + /*check if RX ack from slave*/ + if( (retVal = rtl8367c_setAsicI2CcheckRxAck()) != RT_ERR_OK ) + return retVal; + + + /* tx slave buffer address low 8 bits */ + if( (retVal = rtl8367c_setAsicI2CTxOneCharCmd(slaveRegAddr_L))!= RT_ERR_OK ) + return retVal; + + + /*check if RX ack from slave*/ + if( (retVal = rtl8367c_setAsicI2CcheckRxAck()) != RT_ERR_OK ) + return retVal; + + + /* tx slave buffer address high 8 bits */ + if( (retVal = rtl8367c_setAsicI2CTxOneCharCmd(slaveRegAddr_H))!= RT_ERR_OK ) + return retVal; + + + /*check if RX ack from slave*/ + if( (retVal = rtl8367c_setAsicI2CcheckRxAck()) != RT_ERR_OK ) + return retVal; + + + /*tx Datavlue LSB*/ + if( (retVal = rtl8367c_setAsicI2CTxOneCharCmd(regData_L))!= RT_ERR_OK ) + return retVal; + + + /*check if RX ack from slave*/ + if( (retVal = rtl8367c_setAsicI2CcheckRxAck()) != RT_ERR_OK ) + return retVal; + + + /*tx Datavlue MSB*/ + if( (retVal = rtl8367c_setAsicI2CTxOneCharCmd(regData_H))!= RT_ERR_OK ) + return retVal; + + + /*check if RX ack from slave*/ + if( (retVal = rtl8367c_setAsicI2CcheckRxAck()) != RT_ERR_OK ) + return retVal; + + + /*tx Stop cmd */ + if( (retVal = rtl8367c_setAsicI2CStopCmd()) != RT_ERR_OK ) + return retVal; + + return RT_ERR_OK; +} + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_i2c.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_i2c.h new file mode 100644 index 00000000..35ee4ea0 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_i2c.h @@ -0,0 +1,157 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8367/RTL8367C switch high-level API + * + * Feature : The file includes I2C module high-layer API defination + * + */ + + +#ifndef __DAL_RTL8367C_I2C_H__ +#define __DAL_RTL8367C_I2C_H__ + +#include +#include <../../i2c.h> + +#define I2C_GPIO_MAX_GROUP (3) + +/* Function Name: + * dal_rtl8367c_i2c_data_read + * Description: + * read i2c slave device register. + * Input: + * deviceAddr - access Slave device address + * slaveRegAddr - access Slave register address + * Output: + * pRegData - read data + * Return: + * RT_ERR_OK - OK + * RT_ERR_NULL_POINTER - input parameter is null pointer + * Note: + * The API can access i2c slave and read i2c slave device register. + */ +extern rtk_api_ret_t dal_rtl8367c_i2c_data_read(rtk_uint8 deviceAddr, rtk_uint32 slaveRegAddr, rtk_uint32 *pRegData); + +/* Function Name: + * dal_rtl8367c_i2c_data_write + * Description: + * write data to i2c slave device register + * Input: + * deviceAddr - access Slave device address + * slaveRegAddr - access Slave register address + * regData - data to set + * Output: + * None + * Return: + * RT_ERR_OK - OK + * Note: + * The API can access i2c slave and setting i2c slave device register. + */ +extern rtk_api_ret_t dal_rtl8367c_i2c_data_write(rtk_uint8 deviceAddr, rtk_uint32 slaveRegAddr, rtk_uint32 regData); + + +/* Function Name: + * dal_rtl8367c_i2c_init + * Description: + * I2C smart function initialization. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * Note: + * This API is used to initialize EEE status. + * need used GPIO pins + * OpenDrain and clock + */ +extern rtk_api_ret_t dal_rtl8367c_i2c_init(void); + +/* Function Name: + * dal_rtl8367c_i2c_mode_set + * Description: + * Set I2C data byte-order. + * Input: + * i2cmode - byte-order mode + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_INPUT - Invalid input parameter. + * Note: + * This API can set I2c traffic's byte-order . + */ +extern rtk_api_ret_t dal_rtl8367c_i2c_mode_set( rtk_I2C_16bit_mode_t i2cmode); + +/* Function Name: + * dal_rtl8367c_i2c_mode_get + * Description: + * Get i2c traffic byte-order setting. + * Input: + * None + * Output: + * pI2cMode - i2c byte-order + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_NULL_POINTER - input parameter is null pointer + * Note: + * The API can get i2c traffic byte-order setting. + */ +extern rtk_api_ret_t dal_rtl8367c_i2c_mode_get( rtk_I2C_16bit_mode_t * pI2cMode); + + +/* Function Name: + * dal_rtl8367c_i2c_gpioPinGroup_set + * Description: + * Set i2c SDA & SCL used GPIO pins group. + * Input: + * pins_group - GPIO pins group + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_INPUT - Invalid input parameter. + * Note: + * The API can set i2c used gpio pins group. + * There are three group pins could be used + */ +extern rtk_api_ret_t dal_rtl8367c_i2c_gpioPinGroup_set( rtk_I2C_gpio_pin_t pins_group); + +/* Function Name: + * dal_rtl8367c_i2c_gpioPinGroup_get + * Description: + * Get i2c SDA & SCL used GPIO pins group. + * Input: + * None + * Output: + * pPins_group - GPIO pins group + * Return: + * RT_ERR_OK - OK + * RT_ERR_NULL_POINTER - input parameter is null pointer + * Note: + * The API can get i2c used gpio pins group. + * There are three group pins could be used + */ +extern rtk_api_ret_t dal_rtl8367c_i2c_gpioPinGroup_get(rtk_I2C_gpio_pin_t * pPins_group); + + + + + + + +#endif /* end of __DAL_RTL8367C_I2C_H__ */ + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_igmp.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_igmp.c new file mode 100644 index 00000000..a8497157 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_igmp.c @@ -0,0 +1,1556 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8367C + * Feature : Here is a list of all functions and variables in IGMP module. + * + */ + +#include +#include +#include +#include + +#include +#include +#include + +/* Function Name: + * rtk_igmp_init + * Description: + * This API enables H/W IGMP and set a default initial configuration. + * Input: + * None. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API enables H/W IGMP and set a default initial configuration. + */ +rtk_api_ret_t dal_rtl8367c_igmp_init(void) +{ + rtk_api_ret_t retVal; + rtk_port_t port; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if ((retVal = rtl8367c_setAsicLutIpMulticastLookup(ENABLED))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicLutIpLookupMethod(1))!=RT_ERR_OK) + return retVal; + + RTK_SCAN_ALL_PHY_PORTMASK(port) + { + if ((retVal = rtl8367c_setAsicIGMPv1Opeartion(port, PROTOCOL_OP_ASIC))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicIGMPv2Opeartion(port, PROTOCOL_OP_ASIC))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicIGMPv3Opeartion(port, PROTOCOL_OP_FLOOD))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicMLDv1Opeartion(port, PROTOCOL_OP_ASIC))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicMLDv2Opeartion(port, PROTOCOL_OP_FLOOD))!=RT_ERR_OK) + return retVal; + } + + if ((retVal = rtl8367c_setAsicIGMPAllowDynamicRouterPort(rtk_switch_phyPortMask_get()))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicIGMPFastLeaveEn(ENABLED))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicIGMPReportLeaveFlood(1))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicIgmp(ENABLED))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_igmp_state_set + * Description: + * This API set H/W IGMP state. + * Input: + * enabled - H/W IGMP state + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error parameter + * Note: + * This API set H/W IGMP state. + */ +rtk_api_ret_t dal_rtl8367c_igmp_state_set(rtk_enable_t enabled) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (enabled >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if ((retVal = rtl8367c_setAsicIgmp(enabled))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_igmp_state_get + * Description: + * This API get H/W IGMP state. + * Input: + * None. + * Output: + * pEnabled - H/W IGMP state + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error parameter + * Note: + * This API set current H/W IGMP state. + */ +rtk_api_ret_t dal_rtl8367c_igmp_state_get(rtk_enable_t *pEnabled) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(pEnabled == NULL) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicIgmp(pEnabled))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_igmp_static_router_port_set + * Description: + * Configure static router port + * Input: + * pPortmask - Static Port mask + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Error parameter + * Note: + * This API set static router port + */ +rtk_api_ret_t dal_rtl8367c_igmp_static_router_port_set(rtk_portmask_t *pPortmask) +{ + rtk_api_ret_t retVal; + rtk_uint32 pmask; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Valid port mask */ + if(pPortmask == NULL) + return RT_ERR_NULL_POINTER; + + RTK_CHK_PORTMASK_VALID(pPortmask); + + if ((retVal = rtk_switch_portmask_L2P_get(pPortmask, &pmask))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicIGMPStaticRouterPort(pmask))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_igmp_static_router_port_get + * Description: + * Get static router port + * Input: + * None. + * Output: + * pPortmask - Static port mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Error parameter + * Note: + * This API get static router port + */ +rtk_api_ret_t dal_rtl8367c_igmp_static_router_port_get(rtk_portmask_t *pPortmask) +{ + rtk_api_ret_t retVal; + rtk_uint32 pmask; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(pPortmask == NULL) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicIGMPStaticRouterPort(&pmask))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtk_switch_portmask_P2L_get(pmask, pPortmask))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_igmp_protocol_set + * Description: + * set IGMP/MLD protocol action + * Input: + * port - Port ID + * protocol - IGMP/MLD protocol + * action - Per-port and per-protocol IGMP action seeting + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Error parameter + * Note: + * This API set IGMP/MLD protocol action + */ +rtk_api_ret_t dal_rtl8367c_igmp_protocol_set(rtk_port_t port, rtk_igmp_protocol_t protocol, rtk_igmp_action_t action) +{ + rtk_uint32 operation; + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check port valid */ + RTK_CHK_PORT_VALID(port); + + if(protocol >= PROTOCOL_END) + return RT_ERR_INPUT; + + if(action >= IGMP_ACTION_END) + return RT_ERR_INPUT; + + switch(action) + { + case IGMP_ACTION_FORWARD: + operation = PROTOCOL_OP_FLOOD; + break; + case IGMP_ACTION_TRAP2CPU: + operation = PROTOCOL_OP_TRAP; + break; + case IGMP_ACTION_DROP: + operation = PROTOCOL_OP_DROP; + break; + case IGMP_ACTION_ASIC: + operation = PROTOCOL_OP_ASIC; + break; + default: + return RT_ERR_INPUT; + } + + switch(protocol) + { + case PROTOCOL_IGMPv1: + if ((retVal = rtl8367c_setAsicIGMPv1Opeartion(rtk_switch_port_L2P_get(port), operation))!=RT_ERR_OK) + return retVal; + + break; + case PROTOCOL_IGMPv2: + if ((retVal = rtl8367c_setAsicIGMPv2Opeartion(rtk_switch_port_L2P_get(port), operation))!=RT_ERR_OK) + return retVal; + + break; + case PROTOCOL_IGMPv3: + if ((retVal = rtl8367c_setAsicIGMPv3Opeartion(rtk_switch_port_L2P_get(port), operation))!=RT_ERR_OK) + return retVal; + + break; + case PROTOCOL_MLDv1: + if ((retVal = rtl8367c_setAsicMLDv1Opeartion(rtk_switch_port_L2P_get(port), operation))!=RT_ERR_OK) + return retVal; + + break; + case PROTOCOL_MLDv2: + if ((retVal = rtl8367c_setAsicMLDv2Opeartion(rtk_switch_port_L2P_get(port), operation))!=RT_ERR_OK) + return retVal; + + break; + default: + return RT_ERR_INPUT; + + } + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_igmp_protocol_get + * Description: + * set IGMP/MLD protocol action + * Input: + * port - Port ID + * protocol - IGMP/MLD protocol + * action - Per-port and per-protocol IGMP action seeting + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Error parameter + * Note: + * This API set IGMP/MLD protocol action + */ +rtk_api_ret_t dal_rtl8367c_igmp_protocol_get(rtk_port_t port, rtk_igmp_protocol_t protocol, rtk_igmp_action_t *pAction) +{ + rtk_uint32 operation; + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check port valid */ + RTK_CHK_PORT_VALID(port); + + if(protocol >= PROTOCOL_END) + return RT_ERR_INPUT; + + if(pAction == NULL) + return RT_ERR_NULL_POINTER; + + switch(protocol) + { + case PROTOCOL_IGMPv1: + if ((retVal = rtl8367c_getAsicIGMPv1Opeartion(rtk_switch_port_L2P_get(port), &operation))!=RT_ERR_OK) + return retVal; + + break; + case PROTOCOL_IGMPv2: + if ((retVal = rtl8367c_getAsicIGMPv2Opeartion(rtk_switch_port_L2P_get(port), &operation))!=RT_ERR_OK) + return retVal; + + break; + case PROTOCOL_IGMPv3: + if ((retVal = rtl8367c_getAsicIGMPv3Opeartion(rtk_switch_port_L2P_get(port), &operation))!=RT_ERR_OK) + return retVal; + + break; + case PROTOCOL_MLDv1: + if ((retVal = rtl8367c_getAsicMLDv1Opeartion(rtk_switch_port_L2P_get(port), &operation))!=RT_ERR_OK) + return retVal; + + break; + case PROTOCOL_MLDv2: + if ((retVal = rtl8367c_getAsicMLDv2Opeartion(rtk_switch_port_L2P_get(port), &operation))!=RT_ERR_OK) + return retVal; + + break; + default: + return RT_ERR_INPUT; + + } + + switch(operation) + { + case PROTOCOL_OP_FLOOD: + *pAction = IGMP_ACTION_FORWARD; + break; + case PROTOCOL_OP_TRAP: + *pAction = IGMP_ACTION_TRAP2CPU; + break; + case PROTOCOL_OP_DROP: + *pAction = IGMP_ACTION_DROP; + break; + case PROTOCOL_OP_ASIC: + *pAction = IGMP_ACTION_ASIC; + break; + default: + return RT_ERR_FAILED; + } + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_igmp_fastLeave_set + * Description: + * set IGMP/MLD FastLeave state + * Input: + * state - ENABLED: Enable FastLeave, DISABLED: disable FastLeave + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_INPUT - Error Input + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API set IGMP/MLD FastLeave state + */ +rtk_api_ret_t dal_rtl8367c_igmp_fastLeave_set(rtk_enable_t state) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(state >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if ((retVal = rtl8367c_setAsicIGMPFastLeaveEn((rtk_uint32)state))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_igmp_fastLeave_get + * Description: + * get IGMP/MLD FastLeave state + * Input: + * None + * Output: + * pState - ENABLED: Enable FastLeave, DISABLED: disable FastLeave + * Return: + * RT_ERR_OK - OK + * RT_ERR_NULL_POINTER - NULL pointer + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API get IGMP/MLD FastLeave state + */ +rtk_api_ret_t dal_rtl8367c_igmp_fastLeave_get(rtk_enable_t *pState) +{ + rtk_uint32 fast_leave; + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(pState == NULL) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicIGMPFastLeaveEn(&fast_leave))!=RT_ERR_OK) + return retVal; + + *pState = ((fast_leave == 1) ? ENABLED : DISABLED); + return RT_ERR_OK; +} + +/* Function Name: + * rtk_igmp_maxGroup_set + * Description: + * Set per port multicast group learning limit. + * Input: + * port - Port ID + * group - The number of multicast group learning limit. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_PORT_ID - Error Port ID + * RT_ERR_OUT_OF_RANGE - parameter out of range + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API set per port multicast group learning limit. + */ +rtk_api_ret_t dal_rtl8367c_igmp_maxGroup_set(rtk_port_t port, rtk_uint32 group) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check port valid */ + RTK_CHK_PORT_VALID(port); + + if(group > RTL8367C_IGMP_MAX_GOUP) + return RT_ERR_OUT_OF_RANGE; + + if ((retVal = rtl8367c_setAsicIGMPPortMAXGroup(rtk_switch_port_L2P_get(port), group))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_igmp_maxGroup_get + * Description: + * Get per port multicast group learning limit. + * Input: + * port - Port ID + * Output: + * pGroup - The number of multicast group learning limit. + * Return: + * RT_ERR_OK - OK + * RT_ERR_PORT_ID - Error Port ID + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API get per port multicast group learning limit. + */ +rtk_api_ret_t dal_rtl8367c_igmp_maxGroup_get(rtk_port_t port, rtk_uint32 *pGroup) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check port valid */ + RTK_CHK_PORT_VALID(port); + + if(pGroup == NULL) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicIGMPPortMAXGroup(rtk_switch_port_L2P_get(port), pGroup))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_igmp_currentGroup_get + * Description: + * Get per port multicast group learning count. + * Input: + * port - Port ID + * Output: + * pGroup - The number of multicast group learning count. + * Return: + * RT_ERR_OK - OK + * RT_ERR_PORT_ID - Error Port ID + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API get per port multicast group learning count. + */ +rtk_api_ret_t dal_rtl8367c_igmp_currentGroup_get(rtk_port_t port, rtk_uint32 *pGroup) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check port valid */ + RTK_CHK_PORT_VALID(port); + + if(pGroup == NULL) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicIGMPPortCurrentGroup(rtk_switch_port_L2P_get(port), pGroup))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_igmp_tableFullAction_set + * Description: + * set IGMP/MLD Table Full Action + * Input: + * action - Table Full Action + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_INPUT - Error Input + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +rtk_api_ret_t dal_rtl8367c_igmp_tableFullAction_set(rtk_igmp_tableFullAction_t action) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(action >= IGMP_TABLE_FULL_OP_END) + return RT_ERR_INPUT; + + if ((retVal = rtl8367c_setAsicIGMPTableFullOP((rtk_uint32)action))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_igmp_tableFullAction_get + * Description: + * get IGMP/MLD Table Full Action + * Input: + * None + * Output: + * pAction - Table Full Action + * Return: + * RT_ERR_OK - OK + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +rtk_api_ret_t dal_rtl8367c_igmp_tableFullAction_get(rtk_igmp_tableFullAction_t *pAction) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pAction) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicIGMPTableFullOP((rtk_uint32 *)pAction))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_igmp_checksumErrorAction_set + * Description: + * set IGMP/MLD Checksum Error Action + * Input: + * action - Checksum error Action + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_INPUT - Error Input + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +rtk_api_ret_t dal_rtl8367c_igmp_checksumErrorAction_set(rtk_igmp_checksumErrorAction_t action) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(action >= IGMP_CRC_ERR_OP_END) + return RT_ERR_INPUT; + + if ((retVal = rtl8367c_setAsicIGMPCRCErrOP((rtk_uint32)action))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_igmp_checksumErrorAction_get + * Description: + * get IGMP/MLD Checksum Error Action + * Input: + * None + * Output: + * pAction - Checksum error Action + * Return: + * RT_ERR_OK - OK + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +rtk_api_ret_t dal_rtl8367c_igmp_checksumErrorAction_get(rtk_igmp_checksumErrorAction_t *pAction) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pAction) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicIGMPCRCErrOP((rtk_uint32 *)pAction))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_igmp_leaveTimer_set + * Description: + * set IGMP/MLD Leave timer + * Input: + * timer - Leave timer + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_INPUT - Error Input + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +rtk_api_ret_t dal_rtl8367c_igmp_leaveTimer_set(rtk_uint32 timer) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(timer > RTL8367C_MAX_LEAVE_TIMER) + return RT_ERR_INPUT; + + if ((retVal = rtl8367c_setAsicIGMPLeaveTimer(timer))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_igmp_leaveTimer_get + * Description: + * get IGMP/MLD Leave timer + * Input: + * None + * Output: + * pTimer - Leave Timer. + * Return: + * RT_ERR_OK - OK + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +rtk_api_ret_t dal_rtl8367c_igmp_leaveTimer_get(rtk_uint32 *pTimer) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pTimer) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicIGMPLeaveTimer(pTimer))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_igmp_queryInterval_set + * Description: + * set IGMP/MLD Query Interval + * Input: + * interval - Query Interval + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_INPUT - Error Input + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +rtk_api_ret_t dal_rtl8367c_igmp_queryInterval_set(rtk_uint32 interval) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(interval > RTL8367C_MAX_QUERY_INT) + return RT_ERR_INPUT; + + if ((retVal = rtl8367c_setAsicIGMPQueryInterval(interval))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_igmp_queryInterval_get + * Description: + * get IGMP/MLD Query Interval + * Input: + * None. + * Output: + * pInterval - Query Interval + * Return: + * RT_ERR_OK - OK + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +rtk_api_ret_t dal_rtl8367c_igmp_queryInterval_get(rtk_uint32 *pInterval) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pInterval) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicIGMPQueryInterval(pInterval))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_igmp_robustness_set + * Description: + * set IGMP/MLD Robustness value + * Input: + * robustness - Robustness value + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_INPUT - Error Input + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +rtk_api_ret_t dal_rtl8367c_igmp_robustness_set(rtk_uint32 robustness) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(robustness > RTL8367C_MAX_ROB_VAR) + return RT_ERR_INPUT; + + if ((retVal = rtl8367c_setAsicIGMPRobVar(robustness))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_igmp_robustness_get + * Description: + * get IGMP/MLD Robustness value + * Input: + * None + * Output: + * pRobustness - Robustness value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +rtk_api_ret_t dal_rtl8367c_igmp_robustness_get(rtk_uint32 *pRobustness) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pRobustness) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicIGMPRobVar(pRobustness))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_igmp_dynamicRouterRortAllow_set + * Description: + * Configure dynamic router port allow option + * Input: + * pPortmask - Dynamic Port allow mask + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Error parameter + * Note: + * + */ +rtk_api_ret_t dal_rtl8367c_igmp_dynamicRouterPortAllow_set(rtk_portmask_t *pPortmask) +{ + rtk_api_ret_t retVal; + rtk_uint32 pmask; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pPortmask) + return RT_ERR_NULL_POINTER; + + RTK_CHK_PORTMASK_VALID(pPortmask); + + if ((retVal = rtk_switch_portmask_L2P_get(pPortmask, &pmask))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicIGMPAllowDynamicRouterPort(pmask))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_igmp_dynamicRouterRortAllow_get + * Description: + * Get dynamic router port allow option + * Input: + * None. + * Output: + * pPortmask - Dynamic Port allow mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Error parameter + * Note: + * + */ +rtk_api_ret_t dal_rtl8367c_igmp_dynamicRouterPortAllow_get(rtk_portmask_t *pPortmask) +{ + rtk_api_ret_t retVal; + rtk_uint32 pmask; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pPortmask) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicIGMPAllowDynamicRouterPort(&pmask))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtk_switch_portmask_P2L_get(pmask, pPortmask))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_igmp_dynamicRouterPort_get + * Description: + * Get dynamic router port + * Input: + * None. + * Output: + * pDynamicRouterPort - Dynamic Router Port + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Error parameter + * Note: + * + */ +rtk_api_ret_t dal_rtl8367c_igmp_dynamicRouterPort_get(rtk_igmp_dynamicRouterPort_t *pDynamicRouterPort) +{ + rtk_api_ret_t retVal; + rtk_uint32 port; + rtk_uint32 timer; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pDynamicRouterPort) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicIGMPdynamicRouterPort1(&port, &timer))!= RT_ERR_OK) + return retVal; + + if (port == RTL8367C_ROUTER_PORT_INVALID) + { + pDynamicRouterPort->dynamicRouterPort0Valid = DISABLED; + pDynamicRouterPort->dynamicRouterPort0 = 0; + pDynamicRouterPort->dynamicRouterPort0Timer = 0; + } + else + { + pDynamicRouterPort->dynamicRouterPort0Valid = ENABLED; + pDynamicRouterPort->dynamicRouterPort0 = rtk_switch_port_P2L_get(port); + pDynamicRouterPort->dynamicRouterPort0Timer = timer; + } + + if ((retVal = rtl8367c_getAsicIGMPdynamicRouterPort2(&port, &timer))!= RT_ERR_OK) + return retVal; + + if (port == RTL8367C_ROUTER_PORT_INVALID) + { + pDynamicRouterPort->dynamicRouterPort1Valid = DISABLED; + pDynamicRouterPort->dynamicRouterPort1 = 0; + pDynamicRouterPort->dynamicRouterPort1Timer = 0; + } + else + { + pDynamicRouterPort->dynamicRouterPort1Valid = ENABLED; + pDynamicRouterPort->dynamicRouterPort1 = rtk_switch_port_P2L_get(port); + pDynamicRouterPort->dynamicRouterPort1Timer = timer; + } + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_igmp_suppressionEnable_set + * Description: + * Configure IGMPv1/v2 & MLDv1 Report/Leave/Done suppression + * Input: + * reportSuppression - Report suppression + * leaveSuppression - Leave suppression + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + * + */ +rtk_api_ret_t dal_rtl8367c_igmp_suppressionEnable_set(rtk_enable_t reportSuppression, rtk_enable_t leaveSuppression) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(reportSuppression >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if(leaveSuppression >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if ((retVal = rtl8367c_setAsicIGMPSuppression((rtk_uint32)reportSuppression, (rtk_uint32)leaveSuppression))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_igmp_suppressionEnable_get + * Description: + * Get IGMPv1/v2 & MLDv1 Report/Leave/Done suppression + * Input: + * None + * Output: + * pReportSuppression - Report suppression + * pLeaveSuppression - Leave suppression + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * + */ +rtk_api_ret_t dal_rtl8367c_igmp_suppressionEnable_get(rtk_enable_t *pReportSuppression, rtk_enable_t *pLeaveSuppression) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pReportSuppression) + return RT_ERR_NULL_POINTER; + + if(NULL == pLeaveSuppression) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicIGMPSuppression((rtk_uint32 *)pReportSuppression, (rtk_uint32 *)pLeaveSuppression))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_igmp_portRxPktEnable_set + * Description: + * Configure IGMP/MLD RX Packet configuration + * Input: + * port - Port ID + * pRxCfg - RX Packet Configuration + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * + */ +rtk_api_ret_t dal_rtl8367c_igmp_portRxPktEnable_set(rtk_port_t port, rtk_igmp_rxPktEnable_t *pRxCfg) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check port valid */ + RTK_CHK_PORT_VALID(port); + + if(NULL == pRxCfg) + return RT_ERR_NULL_POINTER; + + if(pRxCfg->rxQuery >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if(pRxCfg->rxReport >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if(pRxCfg->rxLeave >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if(pRxCfg->rxMRP >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if(pRxCfg->rxMcast >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if ((retVal = rtl8367c_setAsicIGMPQueryRX(rtk_switch_port_L2P_get(port), (rtk_uint32)pRxCfg->rxQuery))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicIGMPReportRX(rtk_switch_port_L2P_get(port), (rtk_uint32)pRxCfg->rxReport))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicIGMPLeaveRX(rtk_switch_port_L2P_get(port), (rtk_uint32)pRxCfg->rxLeave))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicIGMPMRPRX(rtk_switch_port_L2P_get(port), (rtk_uint32)pRxCfg->rxMRP))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicIGMPMcDataRX(rtk_switch_port_L2P_get(port), (rtk_uint32)pRxCfg->rxMcast))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_igmp_portRxPktEnable_get + * Description: + * Get IGMP/MLD RX Packet configuration + * Input: + * port - Port ID + * pRxCfg - RX Packet Configuration + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * + */ +rtk_api_ret_t dal_rtl8367c_igmp_portRxPktEnable_get(rtk_port_t port, rtk_igmp_rxPktEnable_t *pRxCfg) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check port valid */ + RTK_CHK_PORT_VALID(port); + + if(NULL == pRxCfg) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicIGMPQueryRX(rtk_switch_port_L2P_get(port), (rtk_uint32 *)&(pRxCfg->rxQuery)))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_getAsicIGMPReportRX(rtk_switch_port_L2P_get(port), (rtk_uint32 *)&(pRxCfg->rxReport)))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_getAsicIGMPLeaveRX(rtk_switch_port_L2P_get(port), (rtk_uint32 *)&(pRxCfg->rxLeave)))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_getAsicIGMPMRPRX(rtk_switch_port_L2P_get(port), (rtk_uint32 *)&(pRxCfg->rxMRP)))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_getAsicIGMPMcDataRX(rtk_switch_port_L2P_get(port), (rtk_uint32 *)&(pRxCfg->rxMcast)))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_igmp_groupInfo_get + * Description: + * Get IGMP/MLD Group database + * Input: + * indes - Index (0~255) + * Output: + * pGroup - Group database information. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * + */ +rtk_api_ret_t dal_rtl8367c_igmp_groupInfo_get(rtk_uint32 index, rtk_igmp_groupInfo_t *pGroup) +{ + rtk_api_ret_t retVal; + rtk_uint32 valid; + rtl8367c_igmpgroup grp; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check index */ + if(index > RTL8367C_IGMP_MAX_GOUP) + return RT_ERR_INPUT; + + if(NULL == pGroup) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicIGMPGroup(index, &valid, &grp))!=RT_ERR_OK) + return retVal; + + memset(pGroup, 0x00, sizeof(rtk_igmp_groupInfo_t)); + pGroup->valid = valid; + pGroup->reportSuppFlag = grp.report_supp_flag; + + if(grp.p0_timer != 0) + { + RTK_PORTMASK_PORT_SET((pGroup->member), rtk_switch_port_P2L_get(0)); + pGroup->timer[rtk_switch_port_P2L_get(0)] = grp.p0_timer; + } + + if(grp.p1_timer != 0) + { + RTK_PORTMASK_PORT_SET((pGroup->member), rtk_switch_port_P2L_get(1)); + pGroup->timer[rtk_switch_port_P2L_get(1)] = grp.p1_timer; + } + + if(grp.p2_timer != 0) + { + RTK_PORTMASK_PORT_SET((pGroup->member), rtk_switch_port_P2L_get(2)); + pGroup->timer[rtk_switch_port_P2L_get(2)] = grp.p2_timer; + } + + if(grp.p3_timer != 0) + { + RTK_PORTMASK_PORT_SET((pGroup->member), rtk_switch_port_P2L_get(3)); + pGroup->timer[rtk_switch_port_P2L_get(3)] = grp.p3_timer; + } + + if(grp.p4_timer != 0) + { + RTK_PORTMASK_PORT_SET((pGroup->member), rtk_switch_port_P2L_get(4)); + pGroup->timer[rtk_switch_port_P2L_get(4)] = grp.p4_timer; + } + + if(grp.p5_timer != 0) + { + RTK_PORTMASK_PORT_SET((pGroup->member), rtk_switch_port_P2L_get(5)); + pGroup->timer[rtk_switch_port_P2L_get(5)] = grp.p5_timer; + } + + if(grp.p6_timer != 0) + { + RTK_PORTMASK_PORT_SET((pGroup->member), rtk_switch_port_P2L_get(6)); + pGroup->timer[rtk_switch_port_P2L_get(6)] = grp.p6_timer; + } + + if(grp.p7_timer != 0) + { + RTK_PORTMASK_PORT_SET((pGroup->member), rtk_switch_port_P2L_get(7)); + pGroup->timer[rtk_switch_port_P2L_get(7)] = grp.p7_timer; + } + + if(grp.p8_timer != 0) + { + RTK_PORTMASK_PORT_SET((pGroup->member), rtk_switch_port_P2L_get(8)); + pGroup->timer[rtk_switch_port_P2L_get(8)] = grp.p8_timer; + } + + if(grp.p9_timer != 0) + { + RTK_PORTMASK_PORT_SET((pGroup->member), rtk_switch_port_P2L_get(9)); + pGroup->timer[rtk_switch_port_P2L_get(9)] = grp.p9_timer; + } + + if(grp.p10_timer != 0) + { + RTK_PORTMASK_PORT_SET((pGroup->member), rtk_switch_port_P2L_get(10)); + pGroup->timer[rtk_switch_port_P2L_get(10)] = grp.p10_timer; + } + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_igmp_ReportLeaveFwdAction_set + * Description: + * Set Report Leave packet forwarding action + * Input: + * action - Action + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + * + */ +rtk_api_ret_t dal_rtl8367c_igmp_ReportLeaveFwdAction_set(rtk_igmp_ReportLeaveFwdAct_t action) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + switch(action) + { + case IGMP_REPORT_LEAVE_TO_ROUTER: + regData = 1; + break; + case IGMP_REPORT_LEAVE_TO_ALLPORT: + regData = 2; + break; + case IGMP_REPORT_LEAVE_TO_ROUTER_PORT_ADV: + regData = 3; + break; + default: + return RT_ERR_INPUT; + } + + if ((retVal = rtl8367c_setAsicIGMPReportLeaveFlood(regData))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_igmp_ReportLeaveFwdAction_get + * Description: + * Get Report Leave packet forwarding action + * Input: + * action - Action + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * RT_ERR_NULL_POINTER - Null Pointer + * Note: + * + */ +rtk_api_ret_t dal_rtl8367c_igmp_ReportLeaveFwdAction_get(rtk_igmp_ReportLeaveFwdAct_t *pAction) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pAction) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicIGMPReportLeaveFlood(®Data))!=RT_ERR_OK) + return retVal; + + switch(regData) + { + case 1: + *pAction = IGMP_REPORT_LEAVE_TO_ROUTER; + break; + case 2: + *pAction = IGMP_REPORT_LEAVE_TO_ALLPORT; + break; + case 3: + *pAction = IGMP_REPORT_LEAVE_TO_ROUTER_PORT_ADV; + break; + default: + return RT_ERR_FAILED; + } + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_igmp_dropLeaveZeroEnable_set + * Description: + * Set the function of droppping Leave packet with group IP = 0.0.0.0 + * Input: + * enabled - Action 1: drop, 0:pass + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + * + */ +rtk_api_ret_t dal_rtl8367c_igmp_dropLeaveZeroEnable_set(rtk_enable_t enabled) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(enabled >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if ((retVal = rtl8367c_setAsicIGMPDropLeaveZero(enabled))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; + +} + +/* Function Name: + * rtk_igmp_dropLeaveZeroEnable_get + * Description: + * Get the function of droppping Leave packet with group IP = 0.0.0.0 + * Input: + * None + * Output: + * pEnabled. - Action 1: drop, 0:pass + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * RT_ERR_NULL_POINTER - Null Pointer + * Note: + * + */ +rtk_api_ret_t dal_rtl8367c_igmp_dropLeaveZeroEnable_get(rtk_enable_t *pEnabled) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pEnabled) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicIGMPDropLeaveZero((rtk_uint32 *)pEnabled))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; + +} + +/* Function Name: + * rtk_igmp_bypassGroupRange_set + * Description: + * Set Bypass group + * Input: + * group - bypassed group + * enabled - enabled 1: Bypassed, 0: not bypass + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + * + */ +rtk_api_ret_t dal_rtl8367c_igmp_bypassGroupRange_set(rtk_igmp_bypassGroup_t group, rtk_enable_t enabled) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(group >= IGMP_BYPASS_GROUP_END) + return RT_ERR_INPUT; + + if(enabled >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if ((retVal = rtl8367c_setAsicIGMPBypassGroup(group, enabled))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_igmp_bypassGroupRange_get + * Description: + * get Bypass group + * Input: + * group - bypassed group + * Output: + * pEnable - enabled 1: Bypassed, 0: not bypass + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * RT_ERR_NULL_POINTER - Null Pointer + * Note: + * + */ +rtk_api_ret_t dal_rtl8367c_igmp_bypassGroupRange_get(rtk_igmp_bypassGroup_t group, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(group >= IGMP_BYPASS_GROUP_END) + return RT_ERR_INPUT; + + if(NULL == pEnable) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicIGMPBypassGroup(group, pEnable))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_igmp.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_igmp.h new file mode 100644 index 00000000..f2307494 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_igmp.h @@ -0,0 +1,680 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8367/RTL8367C switch high-level API + * + * Feature : The file includes IGMP module high-layer API defination + * + */ + +#ifndef __DAL_RTL8367C_IGMP_H__ +#define __DAL_RTL8367C_IGMP_H__ + +#include + +/* Function Name: + * dal_rtl8367c_igmp_init + * Description: + * This API enables H/W IGMP and set a default initial configuration. + * Input: + * None. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API enables H/W IGMP and set a default initial configuration. + */ +extern rtk_api_ret_t dal_rtl8367c_igmp_init(void); + +/* Function Name: + * dal_rtl8367c_igmp_state_set + * Description: + * This API set H/W IGMP state. + * Input: + * enabled - H/W IGMP state + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error parameter + * Note: + * This API set H/W IGMP state. + */ +extern rtk_api_ret_t dal_rtl8367c_igmp_state_set(rtk_enable_t enabled); + +/* Function Name: + * dal_rtl8367c_igmp_state_get + * Description: + * This API get H/W IGMP state. + * Input: + * None. + * Output: + * pEnabled - H/W IGMP state + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error parameter + * Note: + * This API set current H/W IGMP state. + */ +extern rtk_api_ret_t dal_rtl8367c_igmp_state_get(rtk_enable_t *pEnabled); + +/* Function Name: + * dal_rtl8367c_igmp_static_router_port_set + * Description: + * Configure static router port + * Input: + * pPortmask - Static Port mask + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Error parameter + * Note: + * This API set static router port + */ +extern rtk_api_ret_t dal_rtl8367c_igmp_static_router_port_set(rtk_portmask_t *pPortmask); + +/* Function Name: + * dal_rtl8367c_igmp_static_router_port_get + * Description: + * Get static router port + * Input: + * None. + * Output: + * pPortmask - Static port mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Error parameter + * Note: + * This API get static router port + */ +extern rtk_api_ret_t dal_rtl8367c_igmp_static_router_port_get(rtk_portmask_t *pPortmask); + +/* Function Name: + * dal_rtl8367c_igmp_protocol_set + * Description: + * set IGMP/MLD protocol action + * Input: + * port - Port ID + * protocol - IGMP/MLD protocol + * action - Per-port and per-protocol IGMP action seeting + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Error parameter + * Note: + * This API set IGMP/MLD protocol action + */ +extern rtk_api_ret_t dal_rtl8367c_igmp_protocol_set(rtk_port_t port, rtk_igmp_protocol_t protocol, rtk_igmp_action_t action); + +/* Function Name: + * dal_rtl8367c_igmp_protocol_get + * Description: + * set IGMP/MLD protocol action + * Input: + * port - Port ID + * protocol - IGMP/MLD protocol + * action - Per-port and per-protocol IGMP action seeting + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Error parameter + * Note: + * This API set IGMP/MLD protocol action + */ +extern rtk_api_ret_t dal_rtl8367c_igmp_protocol_get(rtk_port_t port, rtk_igmp_protocol_t protocol, rtk_igmp_action_t *pAction); + +/* Function Name: + * dal_rtl8367c_igmp_fastLeave_set + * Description: + * set IGMP/MLD FastLeave state + * Input: + * state - ENABLED: Enable FastLeave, DISABLED: disable FastLeave + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_INPUT - Error Input + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API set IGMP/MLD FastLeave state + */ +extern rtk_api_ret_t dal_rtl8367c_igmp_fastLeave_set(rtk_enable_t state); + +/* Function Name: + * dal_rtl8367c_igmp_fastLeave_get + * Description: + * get IGMP/MLD FastLeave state + * Input: + * None + * Output: + * pState - ENABLED: Enable FastLeave, DISABLED: disable FastLeave + * Return: + * RT_ERR_OK - OK + * RT_ERR_NULL_POINTER - NULL pointer + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API get IGMP/MLD FastLeave state + */ +extern rtk_api_ret_t dal_rtl8367c_igmp_fastLeave_get(rtk_enable_t *pState); + +/* Function Name: + * dal_rtl8367c_igmp_maxGroup_set + * Description: + * Set per port multicast group learning limit. + * Input: + * port - Port ID + * group - The number of multicast group learning limit. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_PORT_ID - Error Port ID + * RT_ERR_OUT_OF_RANGE - parameter out of range + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API set per port multicast group learning limit. + */ +extern rtk_api_ret_t dal_rtl8367c_igmp_maxGroup_set(rtk_port_t port, rtk_uint32 group); + +/* Function Name: + * dal_rtl8367c_igmp_maxGroup_get + * Description: + * Get per port multicast group learning limit. + * Input: + * port - Port ID + * Output: + * pGroup - The number of multicast group learning limit. + * Return: + * RT_ERR_OK - OK + * RT_ERR_PORT_ID - Error Port ID + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API get per port multicast group learning limit. + */ +extern rtk_api_ret_t dal_rtl8367c_igmp_maxGroup_get(rtk_port_t port, rtk_uint32 *pGroup); + +/* Function Name: + * dal_rtl8367c_igmp_currentGroup_get + * Description: + * Get per port multicast group learning count. + * Input: + * port - Port ID + * Output: + * pGroup - The number of multicast group learning count. + * Return: + * RT_ERR_OK - OK + * RT_ERR_PORT_ID - Error Port ID + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API get per port multicast group learning count. + */ +extern rtk_api_ret_t dal_rtl8367c_igmp_currentGroup_get(rtk_port_t port, rtk_uint32 *pGroup); + +/* Function Name: + * dal_rtl8367c_igmp_tableFullAction_set + * Description: + * set IGMP/MLD Table Full Action + * Input: + * action - Table Full Action + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_INPUT - Error Input + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +extern rtk_api_ret_t dal_rtl8367c_igmp_tableFullAction_set(rtk_igmp_tableFullAction_t action); + +/* Function Name: + * dal_rtl8367c_igmp_tableFullAction_get + * Description: + * get IGMP/MLD Table Full Action + * Input: + * None + * Output: + * pAction - Table Full Action + * Return: + * RT_ERR_OK - OK + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +extern rtk_api_ret_t dal_rtl8367c_igmp_tableFullAction_get(rtk_igmp_tableFullAction_t *pAction); + +/* Function Name: + * dal_rtl8367c_igmp_checksumErrorAction_set + * Description: + * set IGMP/MLD Checksum Error Action + * Input: + * action - Checksum error Action + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_INPUT - Error Input + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +extern rtk_api_ret_t dal_rtl8367c_igmp_checksumErrorAction_set(rtk_igmp_checksumErrorAction_t action); + +/* Function Name: + * dal_rtl8367c_igmp_checksumErrorAction_get + * Description: + * get IGMP/MLD Checksum Error Action + * Input: + * None + * Output: + * pAction - Checksum error Action + * Return: + * RT_ERR_OK - OK + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +extern rtk_api_ret_t dal_rtl8367c_igmp_checksumErrorAction_get(rtk_igmp_checksumErrorAction_t *pAction); + +/* Function Name: + * dal_rtl8367c_igmp_leaveTimer_set + * Description: + * set IGMP/MLD Leave timer + * Input: + * timer - Leave timer + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_INPUT - Error Input + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +extern rtk_api_ret_t dal_rtl8367c_igmp_leaveTimer_set(rtk_uint32 timer); + +/* Function Name: + * dal_rtl8367c_igmp_leaveTimer_get + * Description: + * get IGMP/MLD Leave timer + * Input: + * None + * Output: + * pTimer - Leave Timer. + * Return: + * RT_ERR_OK - OK + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +extern rtk_api_ret_t dal_rtl8367c_igmp_leaveTimer_get(rtk_uint32 *pTimer); + +/* Function Name: + * dal_rtl8367c_igmp_queryInterval_set + * Description: + * set IGMP/MLD Query Interval + * Input: + * interval - Query Interval + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_INPUT - Error Input + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +extern rtk_api_ret_t dal_rtl8367c_igmp_queryInterval_set(rtk_uint32 interval); + +/* Function Name: + * dal_rtl8367c_igmp_queryInterval_get + * Description: + * get IGMP/MLD Query Interval + * Input: + * None. + * Output: + * pInterval - Query Interval + * Return: + * RT_ERR_OK - OK + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +extern rtk_api_ret_t dal_rtl8367c_igmp_queryInterval_get(rtk_uint32 *pInterval); + +/* Function Name: + * dal_rtl8367c_igmp_robustness_set + * Description: + * set IGMP/MLD Robustness value + * Input: + * robustness - Robustness value + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_INPUT - Error Input + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +extern rtk_api_ret_t dal_rtl8367c_igmp_robustness_set(rtk_uint32 robustness); + +/* Function Name: + * dal_rtl8367c_igmp_robustness_get + * Description: + * get IGMP/MLD Robustness value + * Input: + * None + * Output: + * pRobustness - Robustness value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +extern rtk_api_ret_t dal_rtl8367c_igmp_robustness_get(rtk_uint32 *pRobustness); + +/* Function Name: + * dal_rtl8367c_igmp_dynamicRouterRortAllow_set + * Description: + * Configure dynamic router port allow option + * Input: + * pPortmask - Dynamic Port allow mask + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Error parameter + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367c_igmp_dynamicRouterPortAllow_set(rtk_portmask_t *pPortmask); + +/* Function Name: + * dal_rtl8367c_igmp_dynamicRouterRortAllow_get + * Description: + * Get dynamic router port allow option + * Input: + * None. + * Output: + * pPortmask - Dynamic Port allow mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Error parameter + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367c_igmp_dynamicRouterPortAllow_get(rtk_portmask_t *pPortmask); + +/* Function Name: + * dal_rtl8367c_igmp_dynamicRouterPort_get + * Description: + * Get dynamic router port + * Input: + * None. + * Output: + * pDynamicRouterPort - Dynamic Router Port + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Error parameter + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367c_igmp_dynamicRouterPort_get(rtk_igmp_dynamicRouterPort_t *pDynamicRouterPort); + +/* Function Name: + * dal_rtl8367c_igmp_suppressionEnable_set + * Description: + * Configure IGMPv1/v2 & MLDv1 Report/Leave/Done suppression + * Input: + * reportSuppression - Report suppression + * leaveSuppression - Leave suppression + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367c_igmp_suppressionEnable_set(rtk_enable_t reportSuppression, rtk_enable_t leaveSuppression); + +/* Function Name: + * dal_rtl8367c_igmp_suppressionEnable_get + * Description: + * Get IGMPv1/v2 & MLDv1 Report/Leave/Done suppression + * Input: + * None + * Output: + * pReportSuppression - Report suppression + * pLeaveSuppression - Leave suppression + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367c_igmp_suppressionEnable_get(rtk_enable_t *pReportSuppression, rtk_enable_t *pLeaveSuppression); + +/* Function Name: + * dal_rtl8367c_igmp_portRxPktEnable_set + * Description: + * Configure IGMP/MLD RX Packet configuration + * Input: + * port - Port ID + * pRxCfg - RX Packet Configuration + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367c_igmp_portRxPktEnable_set(rtk_port_t port, rtk_igmp_rxPktEnable_t *pRxCfg); + +/* Function Name: + * dal_rtl8367c_igmp_portRxPktEnable_get + * Description: + * Get IGMP/MLD RX Packet configuration + * Input: + * port - Port ID + * pRxCfg - RX Packet Configuration + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367c_igmp_portRxPktEnable_get(rtk_port_t port, rtk_igmp_rxPktEnable_t *pRxCfg); + +/* Function Name: + * dal_rtl8367c_igmp_groupInfo_get + * Description: + * Get IGMP/MLD Group database + * Input: + * indes - Index (0~255) + * Output: + * pGroup - Group database information. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367c_igmp_groupInfo_get(rtk_uint32 index, rtk_igmp_groupInfo_t *pGroup); + +/* Function Name: + * dal_rtl8367c_igmp_ReportLeaveFwdAction_set + * Description: + * Set Report Leave packet forwarding action + * Input: + * action - Action + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367c_igmp_ReportLeaveFwdAction_set(rtk_igmp_ReportLeaveFwdAct_t action); + +/* Function Name: + * dal_rtl8367c_igmp_ReportLeaveFwdAction_get + * Description: + * Get Report Leave packet forwarding action + * Input: + * action - Action + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * RT_ERR_NULL_POINTER - Null Pointer + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367c_igmp_ReportLeaveFwdAction_get(rtk_igmp_ReportLeaveFwdAct_t *pAction); + +/* Function Name: + * dal_rtl8367c_igmp_dropLeaveZeroEnable_set + * Description: + * Set the function of droppping Leave packet with group IP = 0.0.0.0 + * Input: + * enabled - Action 1: drop, 0:pass + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367c_igmp_dropLeaveZeroEnable_set(rtk_enable_t enabled); + +/* Function Name: + * dal_rtl8367c_igmp_dropLeaveZeroEnable_get + * Description: + * Get the function of droppping Leave packet with group IP = 0.0.0.0 + * Input: + * None + * Output: + * pEnabled. - Action 1: drop, 0:pass + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * RT_ERR_NULL_POINTER - Null Pointer + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367c_igmp_dropLeaveZeroEnable_get(rtk_enable_t *pEnabled); + +/* Function Name: + * dal_rtl8367c_igmp_bypassGroupRange_set + * Description: + * Set Bypass group + * Input: + * group - bypassed group + * enabled - enabled 1: Bypassed, 0: not bypass + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367c_igmp_bypassGroupRange_set(rtk_igmp_bypassGroup_t group, rtk_enable_t enabled); + +/* Function Name: + * dal_rtl8367c_igmp_bypassGroupRange_get + * Description: + * get Bypass group + * Input: + * group - bypassed group + * Output: + * pEnable - enabled 1: Bypassed, 0: not bypass + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * RT_ERR_NULL_POINTER - Null Pointer + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367c_igmp_bypassGroupRange_get(rtk_igmp_bypassGroup_t group, rtk_enable_t *pEnable); + +#endif /* __DAL_RTL8367C_IGMP_H__ */ diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_interrupt.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_interrupt.c new file mode 100644 index 00000000..42dadf2d --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_interrupt.c @@ -0,0 +1,436 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8367C + * Feature : Here is a list of all functions and variables in Interrupt module. + * + */ + +#include +#include +#include +#include + +#include +#include + +/* Function Name: + * dal_rtl8367c_int_polarity_set + * Description: + * Set interrupt polarity configuration. + * Input: + * type - Interruptpolarity type. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can set interrupt polarity configuration. + */ +rtk_api_ret_t dal_rtl8367c_int_polarity_set(rtk_int_polarity_t type) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(type >= INT_POLAR_END) + return RT_ERR_INPUT; + + if ((retVal = rtl8367c_setAsicInterruptPolarity(type)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_int_polarity_get + * Description: + * Get interrupt polarity configuration. + * Input: + * None + * Output: + * pType - Interruptpolarity type. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can get interrupt polarity configuration. + */ +rtk_api_ret_t dal_rtl8367c_int_polarity_get(rtk_int_polarity_t *pType) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pType) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicInterruptPolarity(pType)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_int_control_set + * Description: + * Set interrupt trigger status configuration. + * Input: + * type - Interrupt type. + * enable - Interrupt status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * The API can set interrupt status configuration. + * The interrupt trigger status is shown in the following: + * - INT_TYPE_LINK_STATUS + * - INT_TYPE_METER_EXCEED + * - INT_TYPE_LEARN_LIMIT + * - INT_TYPE_LINK_SPEED + * - INT_TYPE_CONGEST + * - INT_TYPE_GREEN_FEATURE + * - INT_TYPE_LOOP_DETECT + * - INT_TYPE_8051, + * - INT_TYPE_CABLE_DIAG, + * - INT_TYPE_ACL, + * - INT_TYPE_SLIENT + */ +rtk_api_ret_t dal_rtl8367c_int_control_set(rtk_int_type_t type, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + rtk_uint32 mask; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (type >= INT_TYPE_END) + return RT_ERR_INPUT; + + if (type == INT_TYPE_RESERVED) + return RT_ERR_INPUT; + + if ((retVal = rtl8367c_getAsicInterruptMask(&mask)) != RT_ERR_OK) + return retVal; + + if (ENABLED == enable) + mask = mask | (1<value[0] & (0x0001 << INT_TYPE_RESERVED)) + return RT_ERR_INPUT; + + if(pStatusMask->value[0] >= (0x0001 << INT_TYPE_END)) + return RT_ERR_INPUT; + + if ((retVal = rtl8367c_setAsicInterruptStatus((rtk_uint32)pStatusMask->value[0]))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_int_status_get + * Description: + * Get interrupt trigger status. + * Input: + * None + * Output: + * pStatusMask - Interrupt status bit mask. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get interrupt trigger status when interrupt happened. + * The interrupt trigger status is shown in the following: + * - INT_TYPE_LINK_STATUS (value[0] (Bit0)) + * - INT_TYPE_METER_EXCEED (value[0] (Bit1)) + * - INT_TYPE_LEARN_LIMIT (value[0] (Bit2)) + * - INT_TYPE_LINK_SPEED (value[0] (Bit3)) + * - INT_TYPE_CONGEST (value[0] (Bit4)) + * - INT_TYPE_GREEN_FEATURE (value[0] (Bit5)) + * - INT_TYPE_LOOP_DETECT (value[0] (Bit6)) + * - INT_TYPE_8051 (value[0] (Bit7)) + * - INT_TYPE_CABLE_DIAG (value[0] (Bit8)) + * - INT_TYPE_ACL (value[0] (Bit9)) + * - INT_TYPE_SLIENT (value[0] (Bit11)) + * + */ +rtk_api_ret_t dal_rtl8367c_int_status_get(rtk_int_status_t* pStatusMask) +{ + rtk_api_ret_t retVal; + rtk_uint32 ims_mask; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pStatusMask) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicInterruptStatus(&ims_mask)) != RT_ERR_OK) + return retVal; + + pStatusMask->value[0] = (ims_mask & 0x00000FFF); + return RT_ERR_OK; +} + +#define ADV_NOT_SUPPORT (0xFFFF) +static rtk_api_ret_t _rtk_int_Advidx_get(rtk_int_advType_t adv_type, rtk_uint32 *pAsic_idx) +{ + rtk_uint32 asic_idx[ADV_END] = + { + INTRST_L2_LEARN, + INTRST_SPEED_CHANGE, + INTRST_SPECIAL_CONGESTION, + INTRST_PORT_LINKDOWN, + INTRST_PORT_LINKUP, + ADV_NOT_SUPPORT, + INTRST_RLDP_LOOPED, + INTRST_RLDP_RELEASED, + }; + + if(adv_type >= ADV_END) + return RT_ERR_INPUT; + + if(asic_idx[adv_type] == ADV_NOT_SUPPORT) + return RT_ERR_CHIP_NOT_SUPPORTED; + + *pAsic_idx = asic_idx[adv_type]; + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_int_advanceInfo_get + * Description: + * Get interrupt advanced information. + * Input: + * adv_type - Advanced interrupt type. + * Output: + * info - Information per type. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can get advanced information when interrupt happened. + * The status will be cleared after execute this API. + */ +rtk_api_ret_t dal_rtl8367c_int_advanceInfo_get(rtk_int_advType_t adv_type, rtk_int_info_t *pInfo) +{ + rtk_api_ret_t retVal; + rtk_uint32 data; + rtk_uint32 intAdvType = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(adv_type >= ADV_END) + return RT_ERR_INPUT; + + if(NULL == pInfo) + return RT_ERR_NULL_POINTER; + + if(adv_type != ADV_METER_EXCEED_MASK) + { + if((retVal = _rtk_int_Advidx_get(adv_type, &intAdvType)) != RT_ERR_OK) + return retVal; + } + + switch(adv_type) + { + case ADV_L2_LEARN_PORT_MASK: + /* Get physical portmask */ + if((retVal = rtl8367c_getAsicInterruptRelatedStatus(intAdvType, &data)) != RT_ERR_OK) + return retVal; + + /* Clear Advanced Info */ + if((retVal = rtl8367c_setAsicInterruptRelatedStatus(intAdvType, 0xFFFF)) != RT_ERR_OK) + return retVal; + + /* Translate to logical portmask */ + if((retVal = rtk_switch_portmask_P2L_get(data, &(pInfo->portMask))) != RT_ERR_OK) + return retVal; + + /* Get system learn */ + if((retVal = rtl8367c_getAsicInterruptRelatedStatus(INTRST_SYS_LEARN, &data)) != RT_ERR_OK) + return retVal; + + /* Clear system learn */ + if((retVal = rtl8367c_setAsicInterruptRelatedStatus(INTRST_SYS_LEARN, 0x0001)) != RT_ERR_OK) + return retVal; + + pInfo->systemLearnOver = data; + break; + case ADV_SPEED_CHANGE_PORT_MASK: + case ADV_SPECIAL_CONGESTION_PORT_MASK: + case ADV_PORT_LINKDOWN_PORT_MASK: + case ADV_PORT_LINKUP_PORT_MASK: + case ADV_RLDP_LOOPED: + case ADV_RLDP_RELEASED: + /* Get physical portmask */ + if((retVal = rtl8367c_getAsicInterruptRelatedStatus(intAdvType, &data)) != RT_ERR_OK) + return retVal; + + /* Clear Advanced Info */ + if((retVal = rtl8367c_setAsicInterruptRelatedStatus(intAdvType, 0xFFFF)) != RT_ERR_OK) + return retVal; + + /* Translate to logical portmask */ + if((retVal = rtk_switch_portmask_P2L_get(data, &(pInfo->portMask))) != RT_ERR_OK) + return retVal; + + break; + case ADV_METER_EXCEED_MASK: + /* Get Meter Mask */ + if((retVal = rtl8367c_getAsicInterruptRelatedStatus(INTRST_METER0_15, &data)) != RT_ERR_OK) + return retVal; + + /* Clear Advanced Info */ + if((retVal = rtl8367c_setAsicInterruptRelatedStatus(INTRST_METER0_15, 0xFFFF)) != RT_ERR_OK) + return retVal; + + pInfo->meterMask[0] = data & 0xFFFF; + + /* Get Meter Mask */ + if((retVal = rtl8367c_getAsicInterruptRelatedStatus(INTRST_METER16_31, &data)) != RT_ERR_OK) + return retVal; + + /* Clear Advanced Info */ + if((retVal = rtl8367c_setAsicInterruptRelatedStatus(INTRST_METER16_31, 0xFFFF)) != RT_ERR_OK) + return retVal; + + pInfo->meterMask[0] = pInfo->meterMask[0] | ((data << 16) & 0xFFFF0000); + pInfo->meterMask[1] = 0x0000; + break; + default: + return RT_ERR_INPUT; + } + + return RT_ERR_OK; +} + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_interrupt.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_interrupt.h new file mode 100644 index 00000000..8a0a2ea3 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_interrupt.h @@ -0,0 +1,202 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8367/RTL8367C switch high-level API + * + * Feature : The file includes Interrupt module high-layer API defination + * + */ + +#ifndef __DAL_RTL8367C_INTERRUPT_H__ +#define __DAL_RTL8367C_INTERRUPT_H__ + +#include + +/* Function Name: + * dal_rtl8367c_int_polarity_set + * Description: + * Set interrupt polarity configuration. + * Input: + * type - Interruptpolarity type. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can set interrupt polarity configuration. + */ +extern rtk_api_ret_t dal_rtl8367c_int_polarity_set(rtk_int_polarity_t type); + +/* Function Name: + * dal_rtl8367c_int_polarity_get + * Description: + * Get interrupt polarity configuration. + * Input: + * None + * Output: + * pType - Interruptpolarity type. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can get interrupt polarity configuration. + */ +extern rtk_api_ret_t dal_rtl8367c_int_polarity_get(rtk_int_polarity_t *pType); + +/* Function Name: + * dal_rtl8367c_int_control_set + * Description: + * Set interrupt trigger status configuration. + * Input: + * type - Interrupt type. + * enable - Interrupt status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * The API can set interrupt status configuration. + * The interrupt trigger status is shown in the following: + * - INT_TYPE_LINK_STATUS + * - INT_TYPE_METER_EXCEED + * - INT_TYPE_LEARN_LIMIT + * - INT_TYPE_LINK_SPEED + * - INT_TYPE_CONGEST + * - INT_TYPE_GREEN_FEATURE + * - INT_TYPE_LOOP_DETECT + * - INT_TYPE_8051, + * - INT_TYPE_CABLE_DIAG, + * - INT_TYPE_ACL, + * - INT_TYPE_SLIENT + */ +extern rtk_api_ret_t dal_rtl8367c_int_control_set(rtk_int_type_t type, rtk_enable_t enable); + +/* Function Name: + * dal_rtl8367c_int_control_get + * Description: + * Get interrupt trigger status configuration. + * Input: + * type - Interrupt type. + * Output: + * pEnable - Interrupt status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get interrupt status configuration. + * The interrupt trigger status is shown in the following: + * - INT_TYPE_LINK_STATUS + * - INT_TYPE_METER_EXCEED + * - INT_TYPE_LEARN_LIMIT + * - INT_TYPE_LINK_SPEED + * - INT_TYPE_CONGEST + * - INT_TYPE_GREEN_FEATURE + * - INT_TYPE_LOOP_DETECT + * - INT_TYPE_8051, + * - INT_TYPE_CABLE_DIAG, + * - INT_TYPE_ACL, + * - INT_TYPE_SLIENT + */ +extern rtk_api_ret_t dal_rtl8367c_int_control_get(rtk_int_type_t type, rtk_enable_t* pEnable); + +/* Function Name: + * dal_rtl8367c_int_status_set + * Description: + * Set interrupt trigger status to clean. + * Input: + * None + * Output: + * pStatusMask - Interrupt status bit mask. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can clean interrupt trigger status when interrupt happened. + * The interrupt trigger status is shown in the following: + * - INT_TYPE_LINK_STATUS (value[0] (Bit0)) + * - INT_TYPE_METER_EXCEED (value[0] (Bit1)) + * - INT_TYPE_LEARN_LIMIT (value[0] (Bit2)) + * - INT_TYPE_LINK_SPEED (value[0] (Bit3)) + * - INT_TYPE_CONGEST (value[0] (Bit4)) + * - INT_TYPE_GREEN_FEATURE (value[0] (Bit5)) + * - INT_TYPE_LOOP_DETECT (value[0] (Bit6)) + * - INT_TYPE_8051 (value[0] (Bit7)) + * - INT_TYPE_CABLE_DIAG (value[0] (Bit8)) + * - INT_TYPE_ACL (value[0] (Bit9)) + * - INT_TYPE_SLIENT (value[0] (Bit11)) + * The status will be cleared after execute this API. + */ +extern rtk_api_ret_t dal_rtl8367c_int_status_set(rtk_int_status_t *pStatusMask); + +/* Function Name: + * dal_rtl8367c_int_status_get + * Description: + * Get interrupt trigger status. + * Input: + * None + * Output: + * pStatusMask - Interrupt status bit mask. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get interrupt trigger status when interrupt happened. + * The interrupt trigger status is shown in the following: + * - INT_TYPE_LINK_STATUS (value[0] (Bit0)) + * - INT_TYPE_METER_EXCEED (value[0] (Bit1)) + * - INT_TYPE_LEARN_LIMIT (value[0] (Bit2)) + * - INT_TYPE_LINK_SPEED (value[0] (Bit3)) + * - INT_TYPE_CONGEST (value[0] (Bit4)) + * - INT_TYPE_GREEN_FEATURE (value[0] (Bit5)) + * - INT_TYPE_LOOP_DETECT (value[0] (Bit6)) + * - INT_TYPE_8051 (value[0] (Bit7)) + * - INT_TYPE_CABLE_DIAG (value[0] (Bit8)) + * - INT_TYPE_ACL (value[0] (Bit9)) + * - INT_TYPE_SLIENT (value[0] (Bit11)) + * + */ +extern rtk_api_ret_t dal_rtl8367c_int_status_get(rtk_int_status_t* pStatusMask); + +/* Function Name: + * dal_rtl8367c_int_advanceInfo_get + * Description: + * Get interrupt advanced information. + * Input: + * adv_type - Advanced interrupt type. + * Output: + * info - Information per type. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can get advanced information when interrupt happened. + * The status will be cleared after execute this API. + */ +extern rtk_api_ret_t dal_rtl8367c_int_advanceInfo_get(rtk_int_advType_t adv_type, rtk_int_info_t* info); + + +#endif /* __DAL_RTL8367C_INTERRUPT_H__ */ diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_l2.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_l2.c new file mode 100644 index 00000000..8702a08e --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_l2.c @@ -0,0 +1,2928 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8367C + * Feature : Here is a list of all functions and variables in L2 module. + * + */ + +#include +#include +#include +#include + +#include +#include +#include + +/* Function Name: + * dal_rtl8367c_l2_init + * Description: + * Initialize l2 module of the specified device. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * Initialize l2 module before calling any l2 APIs. + */ +rtk_api_ret_t dal_rtl8367c_l2_init(void) +{ + rtk_api_ret_t retVal; + rtk_uint32 port; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if ((retVal = rtl8367c_setAsicLutIpMulticastLookup(DISABLED)) != RT_ERR_OK) + return retVal; + + /*Enable CAM Usage*/ + if ((retVal = rtl8367c_setAsicLutCamTbUsage(ENABLED)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicLutAgeTimerSpeed(6,2)) != RT_ERR_OK) + return retVal; + + RTK_SCAN_ALL_LOG_PORT(port) + { + if ((retVal = rtl8367c_setAsicLutLearnLimitNo(rtk_switch_port_L2P_get(port), rtk_switch_maxLutAddrNumber_get())) != RT_ERR_OK) + return retVal; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_l2_addr_add + * Description: + * Add LUT unicast entry. + * Input: + * pMac - 6 bytes unicast(I/G bit is 0) mac address to be written into LUT. + * pL2_data - Unicast entry parameter + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_L2_FID - Invalid FID . + * RT_ERR_L2_INDEXTBL_FULL - hashed index is full of entries. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * If the unicast mac address already existed in LUT, it will udpate the status of the entry. + * Otherwise, it will find an empty or asic auto learned entry to write. If all the entries + * with the same hash value can't be replaced, ASIC will return a RT_ERR_L2_INDEXTBL_FULL error. + */ +rtk_api_ret_t dal_rtl8367c_l2_addr_add(rtk_mac_t *pMac, rtk_l2_ucastAddr_t *pL2_data) +{ + rtk_api_ret_t retVal; + rtk_uint32 method; + rtl8367c_luttb l2Table; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* must be unicast address */ + if ((pMac == NULL) || (pMac->octet[0] & 0x1)) + return RT_ERR_MAC; + + if(pL2_data == NULL) + return RT_ERR_MAC; + + RTK_CHK_PORT_VALID(pL2_data->port); + + if (pL2_data->ivl >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if (pL2_data->cvid > RTL8367C_VIDMAX) + return RT_ERR_L2_VID; + + if (pL2_data->fid > RTL8367C_FIDMAX) + return RT_ERR_L2_FID; + + if (pL2_data->is_static>= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if (pL2_data->sa_block>= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if (pL2_data->da_block>= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if (pL2_data->auth>= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if (pL2_data->efid> RTL8367C_EFIDMAX) + return RT_ERR_INPUT; + + if (pL2_data->priority > RTL8367C_PRIMAX) + return RT_ERR_INPUT; + + if (pL2_data->sa_pri_en >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if (pL2_data->fwd_pri_en >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + memset(&l2Table, 0, sizeof(rtl8367c_luttb)); + + /* fill key (MAC,FID) to get L2 entry */ + memcpy(l2Table.mac.octet, pMac->octet, ETHER_ADDR_LEN); + l2Table.ivl_svl = pL2_data->ivl; + l2Table.fid = pL2_data->fid; + l2Table.cvid_fid = pL2_data->cvid; + l2Table.efid = pL2_data->efid; + method = LUTREADMETHOD_MAC; + retVal = rtl8367c_getAsicL2LookupTb(method, &l2Table); + if (RT_ERR_OK == retVal ) + { + memcpy(l2Table.mac.octet, pMac->octet, ETHER_ADDR_LEN); + l2Table.ivl_svl = pL2_data->ivl; + l2Table.cvid_fid = pL2_data->cvid; + l2Table.fid = pL2_data->fid; + l2Table.efid = pL2_data->efid; + l2Table.spa = rtk_switch_port_L2P_get(pL2_data->port); + l2Table.nosalearn = pL2_data->is_static; + l2Table.sa_block = pL2_data->sa_block; + l2Table.da_block = pL2_data->da_block; + l2Table.l3lookup = 0; + l2Table.auth = pL2_data->auth; + l2Table.age = 6; + l2Table.lut_pri = pL2_data->priority; + l2Table.sa_en = pL2_data->sa_pri_en; + l2Table.fwd_en = pL2_data->fwd_pri_en; + if((retVal = rtl8367c_setAsicL2LookupTb(&l2Table)) != RT_ERR_OK) + return retVal; + + pL2_data->address = l2Table.address; + return RT_ERR_OK; + } + else if (RT_ERR_L2_ENTRY_NOTFOUND == retVal ) + { + memset(&l2Table, 0, sizeof(rtl8367c_luttb)); + memcpy(l2Table.mac.octet, pMac->octet, ETHER_ADDR_LEN); + l2Table.ivl_svl = pL2_data->ivl; + l2Table.cvid_fid = pL2_data->cvid; + l2Table.fid = pL2_data->fid; + l2Table.efid = pL2_data->efid; + l2Table.spa = rtk_switch_port_L2P_get(pL2_data->port); + l2Table.nosalearn = pL2_data->is_static; + l2Table.sa_block = pL2_data->sa_block; + l2Table.da_block = pL2_data->da_block; + l2Table.l3lookup = 0; + l2Table.auth = pL2_data->auth; + l2Table.age = 6; + l2Table.lut_pri = pL2_data->priority; + l2Table.sa_en = pL2_data->sa_pri_en; + l2Table.fwd_en = pL2_data->fwd_pri_en; + + if ((retVal = rtl8367c_setAsicL2LookupTb(&l2Table)) != RT_ERR_OK) + return retVal; + + pL2_data->address = l2Table.address; + + method = LUTREADMETHOD_MAC; + retVal = rtl8367c_getAsicL2LookupTb(method, &l2Table); + if (RT_ERR_L2_ENTRY_NOTFOUND == retVal ) + return RT_ERR_L2_INDEXTBL_FULL; + else + return retVal; + } + else + return retVal; + +} + +/* Function Name: + * dal_rtl8367c_l2_addr_get + * Description: + * Get LUT unicast entry. + * Input: + * pMac - 6 bytes unicast(I/G bit is 0) mac address to be written into LUT. + * Output: + * pL2_data - Unicast entry parameter + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_L2_FID - Invalid FID . + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * If the unicast mac address existed in LUT, it will return the port and fid where + * the mac is learned. Otherwise, it will return a RT_ERR_L2_ENTRY_NOTFOUND error. + */ +rtk_api_ret_t dal_rtl8367c_l2_addr_get(rtk_mac_t *pMac, rtk_l2_ucastAddr_t *pL2_data) +{ + rtk_api_ret_t retVal; + rtk_uint32 method; + rtl8367c_luttb l2Table; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* must be unicast address */ + if ((pMac == NULL) || (pMac->octet[0] & 0x1)) + return RT_ERR_MAC; + + if (pL2_data->fid > RTL8367C_FIDMAX || pL2_data->efid > RTL8367C_EFIDMAX) + return RT_ERR_L2_FID; + + memset(&l2Table, 0, sizeof(rtl8367c_luttb)); + + memcpy(l2Table.mac.octet, pMac->octet, ETHER_ADDR_LEN); + l2Table.ivl_svl = pL2_data->ivl; + l2Table.cvid_fid = pL2_data->cvid; + l2Table.fid = pL2_data->fid; + l2Table.efid = pL2_data->efid; + method = LUTREADMETHOD_MAC; + + if ((retVal = rtl8367c_getAsicL2LookupTb(method, &l2Table)) != RT_ERR_OK) + return retVal; + + memcpy(pL2_data->mac.octet, pMac->octet,ETHER_ADDR_LEN); + pL2_data->port = rtk_switch_port_P2L_get(l2Table.spa); + pL2_data->fid = l2Table.fid; + pL2_data->efid = l2Table.efid; + pL2_data->ivl = l2Table.ivl_svl; + pL2_data->cvid = l2Table.cvid_fid; + pL2_data->is_static = l2Table.nosalearn; + pL2_data->auth = l2Table.auth; + pL2_data->sa_block = l2Table.sa_block; + pL2_data->da_block = l2Table.da_block; + pL2_data->priority = l2Table.lut_pri; + pL2_data->sa_pri_en = l2Table.sa_en; + pL2_data->fwd_pri_en= l2Table.fwd_en; + pL2_data->address = l2Table.address; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_l2_addr_next_get + * Description: + * Get Next LUT unicast entry. + * Input: + * read_method - The reading method. + * port - The port number if the read_metohd is READMETHOD_NEXT_L2UCSPA + * pAddress - The Address ID + * Output: + * pL2_data - Unicast entry parameter + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_L2_FID - Invalid FID . + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * Get the next unicast entry after the current entry pointed by pAddress. + * The address of next entry is returned by pAddress. User can use (address + 1) + * as pAddress to call this API again for dumping all entries is LUT. + */ +rtk_api_ret_t dal_rtl8367c_l2_addr_next_get(rtk_l2_read_method_t read_method, rtk_port_t port, rtk_uint32 *pAddress, rtk_l2_ucastAddr_t *pL2_data) +{ + rtk_api_ret_t retVal; + rtk_uint32 method; + rtl8367c_luttb l2Table; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Error Checking */ + if ((pL2_data == NULL) || (pAddress == NULL)) + return RT_ERR_MAC; + + if(read_method == READMETHOD_NEXT_L2UC) + method = LUTREADMETHOD_NEXT_L2UC; + else if(read_method == READMETHOD_NEXT_L2UCSPA) + method = LUTREADMETHOD_NEXT_L2UCSPA; + else + return RT_ERR_INPUT; + + if(read_method == READMETHOD_NEXT_L2UCSPA) + { + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + } + + if(*pAddress > RTK_MAX_LUT_ADDR_ID ) + return RT_ERR_L2_L2UNI_PARAM; + + memset(&l2Table, 0, sizeof(rtl8367c_luttb)); + l2Table.address = *pAddress; + + if(read_method == READMETHOD_NEXT_L2UCSPA) + l2Table.spa = rtk_switch_port_L2P_get(port); + + if ((retVal = rtl8367c_getAsicL2LookupTb(method, &l2Table)) != RT_ERR_OK) + return retVal; + + if(l2Table.address < *pAddress) + return RT_ERR_L2_ENTRY_NOTFOUND; + + memcpy(pL2_data->mac.octet, l2Table.mac.octet, ETHER_ADDR_LEN); + pL2_data->port = rtk_switch_port_P2L_get(l2Table.spa); + pL2_data->fid = l2Table.fid; + pL2_data->efid = l2Table.efid; + pL2_data->ivl = l2Table.ivl_svl; + pL2_data->cvid = l2Table.cvid_fid; + pL2_data->is_static = l2Table.nosalearn; + pL2_data->auth = l2Table.auth; + pL2_data->sa_block = l2Table.sa_block; + pL2_data->da_block = l2Table.da_block; + pL2_data->priority = l2Table.lut_pri; + pL2_data->sa_pri_en = l2Table.sa_en; + pL2_data->fwd_pri_en= l2Table.fwd_en; + pL2_data->address = l2Table.address; + + *pAddress = l2Table.address; + + return RT_ERR_OK; + +} + +/* Function Name: + * dal_rtl8367c_l2_addr_del + * Description: + * Delete LUT unicast entry. + * Input: + * pMac - 6 bytes unicast(I/G bit is 0) mac address to be written into LUT. + * fid - Filtering database + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_L2_FID - Invalid FID . + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * If the mac has existed in the LUT, it will be deleted. Otherwise, it will return RT_ERR_L2_ENTRY_NOTFOUND. + */ +rtk_api_ret_t dal_rtl8367c_l2_addr_del(rtk_mac_t *pMac, rtk_l2_ucastAddr_t *pL2_data) +{ + rtk_api_ret_t retVal; + rtk_uint32 method; + rtl8367c_luttb l2Table; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* must be unicast address */ + if ((pMac == NULL) || (pMac->octet[0] & 0x1)) + return RT_ERR_MAC; + + if (pL2_data->fid > RTL8367C_FIDMAX || pL2_data->efid > RTL8367C_EFIDMAX) + return RT_ERR_L2_FID; + + memset(&l2Table, 0, sizeof(rtl8367c_luttb)); + + /* fill key (MAC,FID) to get L2 entry */ + memcpy(l2Table.mac.octet, pMac->octet, ETHER_ADDR_LEN); + l2Table.ivl_svl = pL2_data->ivl; + l2Table.cvid_fid = pL2_data->cvid; + l2Table.fid = pL2_data->fid; + l2Table.efid = pL2_data->efid; + method = LUTREADMETHOD_MAC; + retVal = rtl8367c_getAsicL2LookupTb(method, &l2Table); + if (RT_ERR_OK == retVal) + { + memcpy(l2Table.mac.octet, pMac->octet, ETHER_ADDR_LEN); + l2Table.ivl_svl = pL2_data->ivl; + l2Table.cvid_fid = pL2_data->cvid; + l2Table.fid = pL2_data->fid; + l2Table.efid = pL2_data->efid; + l2Table.spa = 0; + l2Table.nosalearn = 0; + l2Table.sa_block = 0; + l2Table.da_block = 0; + l2Table.auth = 0; + l2Table.age = 0; + l2Table.lut_pri = 0; + l2Table.sa_en = 0; + l2Table.fwd_en = 0; + if((retVal = rtl8367c_setAsicL2LookupTb(&l2Table)) != RT_ERR_OK) + return retVal; + + pL2_data->address = l2Table.address; + return RT_ERR_OK; + } + else + return retVal; +} + +/* Function Name: + * dal_rtl8367c_l2_mcastAddr_add + * Description: + * Add LUT multicast entry. + * Input: + * pMcastAddr - L2 multicast entry structure + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_L2_FID - Invalid FID . + * RT_ERR_L2_VID - Invalid VID . + * RT_ERR_L2_INDEXTBL_FULL - hashed index is full of entries. + * RT_ERR_PORT_MASK - Invalid portmask. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * If the multicast mac address already existed in the LUT, it will udpate the + * port mask of the entry. Otherwise, it will find an empty or asic auto learned + * entry to write. If all the entries with the same hash value can't be replaced, + * ASIC will return a RT_ERR_L2_INDEXTBL_FULL error. + */ +rtk_api_ret_t dal_rtl8367c_l2_mcastAddr_add(rtk_l2_mcastAddr_t *pMcastAddr) +{ + rtk_api_ret_t retVal; + rtk_uint32 method; + rtl8367c_luttb l2Table; + rtk_uint32 pmask; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pMcastAddr) + return RT_ERR_NULL_POINTER; + + /* must be L2 multicast address */ + if( (pMcastAddr->mac.octet[0] & 0x01) != 0x01) + return RT_ERR_MAC; + + RTK_CHK_PORTMASK_VALID(&pMcastAddr->portmask); + + if(pMcastAddr->ivl == 1) + { + if (pMcastAddr->vid > RTL8367C_VIDMAX) + return RT_ERR_L2_VID; + } + else if(pMcastAddr->ivl == 0) + { + if (pMcastAddr->fid > RTL8367C_FIDMAX) + return RT_ERR_L2_FID; + } + else + return RT_ERR_INPUT; + + if(pMcastAddr->fwd_pri_en >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if(pMcastAddr->priority > RTL8367C_PRIMAX) + return RT_ERR_INPUT; + + /* Get physical port mask */ + if ((retVal = rtk_switch_portmask_L2P_get(&pMcastAddr->portmask, &pmask)) != RT_ERR_OK) + return retVal; + + memset(&l2Table, 0, sizeof(rtl8367c_luttb)); + + /* fill key (MAC,FID) to get L2 entry */ + memcpy(l2Table.mac.octet, pMcastAddr->mac.octet, ETHER_ADDR_LEN); + l2Table.ivl_svl = pMcastAddr->ivl; + + if(pMcastAddr->ivl) + l2Table.cvid_fid = pMcastAddr->vid; + else + l2Table.cvid_fid = pMcastAddr->fid; + + method = LUTREADMETHOD_MAC; + retVal = rtl8367c_getAsicL2LookupTb(method, &l2Table); + if (RT_ERR_OK == retVal) + { + memcpy(l2Table.mac.octet, pMcastAddr->mac.octet, ETHER_ADDR_LEN); + l2Table.ivl_svl = pMcastAddr->ivl; + + if(pMcastAddr->ivl) + l2Table.cvid_fid = pMcastAddr->vid; + else + l2Table.cvid_fid = pMcastAddr->fid; + + l2Table.mbr = pmask; + l2Table.nosalearn = 1; + l2Table.l3lookup = 0; + l2Table.lut_pri = pMcastAddr->priority; + l2Table.fwd_en = pMcastAddr->fwd_pri_en; + if((retVal = rtl8367c_setAsicL2LookupTb(&l2Table)) != RT_ERR_OK) + return retVal; + + pMcastAddr->address = l2Table.address; + return RT_ERR_OK; + } + else if (RT_ERR_L2_ENTRY_NOTFOUND == retVal) + { + memset(&l2Table, 0, sizeof(rtl8367c_luttb)); + memcpy(l2Table.mac.octet, pMcastAddr->mac.octet, ETHER_ADDR_LEN); + l2Table.ivl_svl = pMcastAddr->ivl; + if(pMcastAddr->ivl) + l2Table.cvid_fid = pMcastAddr->vid; + else + l2Table.cvid_fid = pMcastAddr->fid; + + l2Table.mbr = pmask; + l2Table.nosalearn = 1; + l2Table.l3lookup = 0; + l2Table.lut_pri = pMcastAddr->priority; + l2Table.fwd_en = pMcastAddr->fwd_pri_en; + if ((retVal = rtl8367c_setAsicL2LookupTb(&l2Table)) != RT_ERR_OK) + return retVal; + + pMcastAddr->address = l2Table.address; + + method = LUTREADMETHOD_MAC; + retVal = rtl8367c_getAsicL2LookupTb(method, &l2Table); + if (RT_ERR_L2_ENTRY_NOTFOUND == retVal) + return RT_ERR_L2_INDEXTBL_FULL; + else + return retVal; + } + else + return retVal; + +} + +/* Function Name: + * dal_rtl8367c_l2_mcastAddr_get + * Description: + * Get LUT multicast entry. + * Input: + * pMcastAddr - L2 multicast entry structure + * Output: + * pMcastAddr - L2 multicast entry structure + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_L2_FID - Invalid FID . + * RT_ERR_L2_VID - Invalid VID . + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * If the multicast mac address existed in the LUT, it will return the port where + * the mac is learned. Otherwise, it will return a RT_ERR_L2_ENTRY_NOTFOUND error. + */ +rtk_api_ret_t dal_rtl8367c_l2_mcastAddr_get(rtk_l2_mcastAddr_t *pMcastAddr) +{ + rtk_api_ret_t retVal; + rtk_uint32 method; + rtl8367c_luttb l2Table; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pMcastAddr) + return RT_ERR_NULL_POINTER; + + /* must be L2 multicast address */ + if( (pMcastAddr->mac.octet[0] & 0x01) != 0x01) + return RT_ERR_MAC; + + if(pMcastAddr->ivl == 1) + { + if (pMcastAddr->vid > RTL8367C_VIDMAX) + return RT_ERR_L2_VID; + } + else if(pMcastAddr->ivl == 0) + { + if (pMcastAddr->fid > RTL8367C_FIDMAX) + return RT_ERR_L2_FID; + } + else + return RT_ERR_INPUT; + + memset(&l2Table, 0, sizeof(rtl8367c_luttb)); + memcpy(l2Table.mac.octet, pMcastAddr->mac.octet, ETHER_ADDR_LEN); + l2Table.ivl_svl = pMcastAddr->ivl; + + if(pMcastAddr->ivl) + l2Table.cvid_fid = pMcastAddr->vid; + else + l2Table.cvid_fid = pMcastAddr->fid; + + method = LUTREADMETHOD_MAC; + + if ((retVal = rtl8367c_getAsicL2LookupTb(method, &l2Table)) != RT_ERR_OK) + return retVal; + + pMcastAddr->priority = l2Table.lut_pri; + pMcastAddr->fwd_pri_en = l2Table.fwd_en; + pMcastAddr->igmp_asic = l2Table.igmp_asic; + pMcastAddr->igmp_index = l2Table.igmpidx; + pMcastAddr->address = l2Table.address; + + /* Get Logical port mask */ + if ((retVal = rtk_switch_portmask_P2L_get(l2Table.mbr, &pMcastAddr->portmask)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_l2_mcastAddr_next_get + * Description: + * Get Next L2 Multicast entry. + * Input: + * pAddress - The Address ID + * Output: + * pMcastAddr - L2 multicast entry structure + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * Get the next L2 multicast entry after the current entry pointed by pAddress. + * The address of next entry is returned by pAddress. User can use (address + 1) + * as pAddress to call this API again for dumping all multicast entries is LUT. + */ +rtk_api_ret_t dal_rtl8367c_l2_mcastAddr_next_get(rtk_uint32 *pAddress, rtk_l2_mcastAddr_t *pMcastAddr) +{ + rtk_api_ret_t retVal; + rtl8367c_luttb l2Table; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Error Checking */ + if ((pAddress == NULL) || (pMcastAddr == NULL)) + return RT_ERR_INPUT; + + if(*pAddress > RTK_MAX_LUT_ADDR_ID ) + return RT_ERR_L2_L2UNI_PARAM; + + memset(&l2Table, 0, sizeof(rtl8367c_luttb)); + l2Table.address = *pAddress; + + if ((retVal = rtl8367c_getAsicL2LookupTb(LUTREADMETHOD_NEXT_L2MC, &l2Table)) != RT_ERR_OK) + return retVal; + + if(l2Table.address < *pAddress) + return RT_ERR_L2_ENTRY_NOTFOUND; + + memcpy(pMcastAddr->mac.octet, l2Table.mac.octet, ETHER_ADDR_LEN); + pMcastAddr->ivl = l2Table.ivl_svl; + + if(pMcastAddr->ivl) + pMcastAddr->vid = l2Table.cvid_fid; + else + pMcastAddr->fid = l2Table.cvid_fid; + + pMcastAddr->priority = l2Table.lut_pri; + pMcastAddr->fwd_pri_en = l2Table.fwd_en; + pMcastAddr->igmp_asic = l2Table.igmp_asic; + pMcastAddr->igmp_index = l2Table.igmpidx; + pMcastAddr->address = l2Table.address; + + /* Get Logical port mask */ + if ((retVal = rtk_switch_portmask_P2L_get(l2Table.mbr, &pMcastAddr->portmask)) != RT_ERR_OK) + return retVal; + + *pAddress = l2Table.address; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_l2_mcastAddr_del + * Description: + * Delete LUT multicast entry. + * Input: + * pMcastAddr - L2 multicast entry structure + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_L2_FID - Invalid FID . + * RT_ERR_L2_VID - Invalid VID . + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * If the mac has existed in the LUT, it will be deleted. Otherwise, it will return RT_ERR_L2_ENTRY_NOTFOUND. + */ +rtk_api_ret_t dal_rtl8367c_l2_mcastAddr_del(rtk_l2_mcastAddr_t *pMcastAddr) +{ + rtk_api_ret_t retVal; + rtk_uint32 method; + rtl8367c_luttb l2Table; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pMcastAddr) + return RT_ERR_NULL_POINTER; + + /* must be L2 multicast address */ + if( (pMcastAddr->mac.octet[0] & 0x01) != 0x01) + return RT_ERR_MAC; + + if(pMcastAddr->ivl == 1) + { + if (pMcastAddr->vid > RTL8367C_VIDMAX) + return RT_ERR_L2_VID; + } + else if(pMcastAddr->ivl == 0) + { + if (pMcastAddr->fid > RTL8367C_FIDMAX) + return RT_ERR_L2_FID; + } + else + return RT_ERR_INPUT; + + memset(&l2Table, 0, sizeof(rtl8367c_luttb)); + + /* fill key (MAC,FID) to get L2 entry */ + memcpy(l2Table.mac.octet, pMcastAddr->mac.octet, ETHER_ADDR_LEN); + l2Table.ivl_svl = pMcastAddr->ivl; + + if(pMcastAddr->ivl) + l2Table.cvid_fid = pMcastAddr->vid; + else + l2Table.cvid_fid = pMcastAddr->fid; + + method = LUTREADMETHOD_MAC; + retVal = rtl8367c_getAsicL2LookupTb(method, &l2Table); + if (RT_ERR_OK == retVal) + { + memcpy(l2Table.mac.octet, pMcastAddr->mac.octet, ETHER_ADDR_LEN); + l2Table.ivl_svl = pMcastAddr->ivl; + + if(pMcastAddr->ivl) + l2Table.cvid_fid = pMcastAddr->vid; + else + l2Table.cvid_fid = pMcastAddr->fid; + + l2Table.mbr = 0; + l2Table.nosalearn = 0; + l2Table.sa_block = 0; + l2Table.l3lookup = 0; + l2Table.lut_pri = 0; + l2Table.fwd_en = 0; + if((retVal = rtl8367c_setAsicL2LookupTb(&l2Table)) != RT_ERR_OK) + return retVal; + + pMcastAddr->address = l2Table.address; + return RT_ERR_OK; + } + else + return retVal; +} + +/* Function Name: + * dal_rtl8367c_l2_ipMcastAddr_add + * Description: + * Add Lut IP multicast entry + * Input: + * pIpMcastAddr - IP Multicast entry + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_L2_INDEXTBL_FULL - hashed index is full of entries. + * RT_ERR_PORT_MASK - Invalid portmask. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * System supports L2 entry with IP multicast DIP/SIP to forward IP multicasting frame as user + * desired. If this function is enabled, then system will be looked up L2 IP multicast entry to + * forward IP multicast frame directly without flooding. + */ +rtk_api_ret_t dal_rtl8367c_l2_ipMcastAddr_add(rtk_l2_ipMcastAddr_t *pIpMcastAddr) +{ + rtk_api_ret_t retVal; + rtk_uint32 method; + rtl8367c_luttb l2Table; + rtk_uint32 pmask; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pIpMcastAddr) + return RT_ERR_NULL_POINTER; + + /* check port mask */ + RTK_CHK_PORTMASK_VALID(&pIpMcastAddr->portmask); + + if( (pIpMcastAddr->dip & 0xF0000000) != 0xE0000000) + return RT_ERR_INPUT; + + if(pIpMcastAddr->fwd_pri_en >= RTK_ENABLE_END) + return RT_ERR_ENABLE; + + if(pIpMcastAddr->priority > RTL8367C_PRIMAX) + return RT_ERR_INPUT; + + /* Get Physical port mask */ + if ((retVal = rtk_switch_portmask_L2P_get(&pIpMcastAddr->portmask, &pmask)) != RT_ERR_OK) + return retVal; + + memset(&l2Table, 0x00, sizeof(rtl8367c_luttb)); + l2Table.sip = pIpMcastAddr->sip; + l2Table.dip = pIpMcastAddr->dip; + l2Table.l3lookup = 1; + l2Table.l3vidlookup = 0; + method = LUTREADMETHOD_MAC; + retVal = rtl8367c_getAsicL2LookupTb(method, &l2Table); + if (RT_ERR_OK == retVal) + { + l2Table.sip = pIpMcastAddr->sip; + l2Table.dip = pIpMcastAddr->dip; + l2Table.mbr = pmask; + l2Table.nosalearn = 1; + l2Table.l3lookup = 1; + l2Table.l3vidlookup = 0; + l2Table.lut_pri = pIpMcastAddr->priority; + l2Table.fwd_en = pIpMcastAddr->fwd_pri_en; + if((retVal = rtl8367c_setAsicL2LookupTb(&l2Table)) != RT_ERR_OK) + return retVal; + + pIpMcastAddr->address = l2Table.address; + return RT_ERR_OK; + } + else if (RT_ERR_L2_ENTRY_NOTFOUND == retVal) + { + memset(&l2Table, 0, sizeof(rtl8367c_luttb)); + l2Table.sip = pIpMcastAddr->sip; + l2Table.dip = pIpMcastAddr->dip; + l2Table.mbr = pmask; + l2Table.nosalearn = 1; + l2Table.l3lookup = 1; + l2Table.l3vidlookup = 0; + l2Table.lut_pri = pIpMcastAddr->priority; + l2Table.fwd_en = pIpMcastAddr->fwd_pri_en; + if ((retVal = rtl8367c_setAsicL2LookupTb(&l2Table)) != RT_ERR_OK) + return retVal; + + pIpMcastAddr->address = l2Table.address; + + method = LUTREADMETHOD_MAC; + retVal = rtl8367c_getAsicL2LookupTb(method, &l2Table); + if (RT_ERR_L2_ENTRY_NOTFOUND == retVal) + return RT_ERR_L2_INDEXTBL_FULL; + else + return retVal; + + } + else + return retVal; + +} + +/* Function Name: + * dal_rtl8367c_l2_ipMcastAddr_get + * Description: + * Get LUT IP multicast entry. + * Input: + * pIpMcastAddr - IP Multicast entry + * Output: + * pIpMcastAddr - IP Multicast entry + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get Lut table of IP multicast entry. + */ +rtk_api_ret_t dal_rtl8367c_l2_ipMcastAddr_get(rtk_l2_ipMcastAddr_t *pIpMcastAddr) +{ + rtk_api_ret_t retVal; + rtk_uint32 method; + rtl8367c_luttb l2Table; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pIpMcastAddr) + return RT_ERR_NULL_POINTER; + + if( (pIpMcastAddr->dip & 0xF0000000) != 0xE0000000) + return RT_ERR_INPUT; + + memset(&l2Table, 0x00, sizeof(rtl8367c_luttb)); + l2Table.sip = pIpMcastAddr->sip; + l2Table.dip = pIpMcastAddr->dip; + l2Table.l3lookup = 1; + l2Table.l3vidlookup = 0; + method = LUTREADMETHOD_MAC; + if ((retVal = rtl8367c_getAsicL2LookupTb(method, &l2Table)) != RT_ERR_OK) + return retVal; + + /* Get Logical port mask */ + if ((retVal = rtk_switch_portmask_P2L_get(l2Table.mbr, &pIpMcastAddr->portmask)) != RT_ERR_OK) + return retVal; + + pIpMcastAddr->priority = l2Table.lut_pri; + pIpMcastAddr->fwd_pri_en = l2Table.fwd_en; + pIpMcastAddr->igmp_asic = l2Table.igmp_asic; + pIpMcastAddr->igmp_index = l2Table.igmpidx; + pIpMcastAddr->address = l2Table.address; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_l2_ipMcastAddr_next_get + * Description: + * Get Next IP Multicast entry. + * Input: + * pAddress - The Address ID + * Output: + * pIpMcastAddr - IP Multicast entry + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * Get the next IP multicast entry after the current entry pointed by pAddress. + * The address of next entry is returned by pAddress. User can use (address + 1) + * as pAddress to call this API again for dumping all IP multicast entries is LUT. + */ +rtk_api_ret_t dal_rtl8367c_l2_ipMcastAddr_next_get(rtk_uint32 *pAddress, rtk_l2_ipMcastAddr_t *pIpMcastAddr) +{ + rtk_api_ret_t retVal; + rtl8367c_luttb l2Table; + rtk_uint32 tmpAddress; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Error Checking */ + if ((pAddress == NULL) || (pIpMcastAddr == NULL) ) + return RT_ERR_INPUT; + + if(*pAddress > RTK_MAX_LUT_ADDR_ID ) + return RT_ERR_L2_L2UNI_PARAM; + + memset(&l2Table, 0, sizeof(rtl8367c_luttb)); + tmpAddress = *pAddress; + + do + { + l2Table.address = tmpAddress; + if ((retVal = rtl8367c_getAsicL2LookupTb(LUTREADMETHOD_NEXT_L3MC, &l2Table)) != RT_ERR_OK) + return retVal; + + if(l2Table.address < tmpAddress) + return RT_ERR_L2_ENTRY_NOTFOUND; + + tmpAddress = l2Table.address + 1; + }while(l2Table.l3vidlookup == 1); + + pIpMcastAddr->sip = l2Table.sip; + pIpMcastAddr->dip = l2Table.dip; + + /* Get Logical port mask */ + if ((retVal = rtk_switch_portmask_P2L_get(l2Table.mbr, &pIpMcastAddr->portmask)) != RT_ERR_OK) + return retVal; + + pIpMcastAddr->priority = l2Table.lut_pri; + pIpMcastAddr->fwd_pri_en = l2Table.fwd_en; + pIpMcastAddr->igmp_asic = l2Table.igmp_asic; + pIpMcastAddr->igmp_index = l2Table.igmpidx; + pIpMcastAddr->address = l2Table.address; + *pAddress = l2Table.address; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_l2_ipMcastAddr_del + * Description: + * Delete a ip multicast address entry from the specified device. + * Input: + * pIpMcastAddr - IP Multicast entry + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can delete a IP multicast address entry from the specified device. + */ +rtk_api_ret_t dal_rtl8367c_l2_ipMcastAddr_del(rtk_l2_ipMcastAddr_t *pIpMcastAddr) +{ + rtk_api_ret_t retVal; + rtk_uint32 method; + rtl8367c_luttb l2Table; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Error Checking */ + if (pIpMcastAddr == NULL) + return RT_ERR_INPUT; + + if( (pIpMcastAddr->dip & 0xF0000000) != 0xE0000000) + return RT_ERR_INPUT; + + memset(&l2Table, 0x00, sizeof(rtl8367c_luttb)); + l2Table.sip = pIpMcastAddr->sip; + l2Table.dip = pIpMcastAddr->dip; + l2Table.l3lookup = 1; + l2Table.l3vidlookup = 0; + method = LUTREADMETHOD_MAC; + retVal = rtl8367c_getAsicL2LookupTb(method, &l2Table); + if (RT_ERR_OK == retVal) + { + l2Table.sip = pIpMcastAddr->sip; + l2Table.dip = pIpMcastAddr->dip; + l2Table.mbr = 0; + l2Table.nosalearn = 0; + l2Table.l3lookup = 1; + l2Table.l3vidlookup = 0; + l2Table.lut_pri = 0; + l2Table.fwd_en = 0; + if((retVal = rtl8367c_setAsicL2LookupTb(&l2Table)) != RT_ERR_OK) + return retVal; + + pIpMcastAddr->address = l2Table.address; + return RT_ERR_OK; + } + else + return retVal; +} + +/* Function Name: + * dal_rtl8367c_l2_ipVidMcastAddr_add + * Description: + * Add Lut IP multicast+VID entry + * Input: + * pIpVidMcastAddr - IP & VID multicast Entry + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_L2_INDEXTBL_FULL - hashed index is full of entries. + * RT_ERR_PORT_MASK - Invalid portmask. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * + */ +rtk_api_ret_t dal_rtl8367c_l2_ipVidMcastAddr_add(rtk_l2_ipVidMcastAddr_t *pIpVidMcastAddr) +{ + rtk_api_ret_t retVal; + rtk_uint32 method; + rtl8367c_luttb l2Table; + rtk_uint32 pmask; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pIpVidMcastAddr) + return RT_ERR_NULL_POINTER; + + /* check port mask */ + RTK_CHK_PORTMASK_VALID(&pIpVidMcastAddr->portmask); + + if (pIpVidMcastAddr->vid > RTL8367C_VIDMAX) + return RT_ERR_L2_VID; + + if( (pIpVidMcastAddr->dip & 0xF0000000) != 0xE0000000) + return RT_ERR_INPUT; + + /* Get Physical port mask */ + if ((retVal = rtk_switch_portmask_L2P_get(&pIpVidMcastAddr->portmask, &pmask)) != RT_ERR_OK) + return retVal; + + memset(&l2Table, 0x00, sizeof(rtl8367c_luttb)); + l2Table.sip = pIpVidMcastAddr->sip; + l2Table.dip = pIpVidMcastAddr->dip; + l2Table.l3lookup = 1; + l2Table.l3vidlookup = 1; + l2Table.l3_vid = pIpVidMcastAddr->vid; + method = LUTREADMETHOD_MAC; + retVal = rtl8367c_getAsicL2LookupTb(method, &l2Table); + if (RT_ERR_OK == retVal) + { + l2Table.sip = pIpVidMcastAddr->sip; + l2Table.dip = pIpVidMcastAddr->dip; + l2Table.mbr = pmask; + l2Table.nosalearn = 1; + l2Table.l3lookup = 1; + l2Table.l3vidlookup = 1; + l2Table.l3_vid = pIpVidMcastAddr->vid; + if((retVal = rtl8367c_setAsicL2LookupTb(&l2Table)) != RT_ERR_OK) + return retVal; + + pIpVidMcastAddr->address = l2Table.address; + return RT_ERR_OK; + } + else if (RT_ERR_L2_ENTRY_NOTFOUND == retVal) + { + memset(&l2Table, 0, sizeof(rtl8367c_luttb)); + l2Table.sip = pIpVidMcastAddr->sip; + l2Table.dip = pIpVidMcastAddr->dip; + l2Table.mbr = pmask; + l2Table.nosalearn = 1; + l2Table.l3lookup = 1; + l2Table.l3vidlookup = 1; + l2Table.l3_vid = pIpVidMcastAddr->vid; + if ((retVal = rtl8367c_setAsicL2LookupTb(&l2Table)) != RT_ERR_OK) + return retVal; + + pIpVidMcastAddr->address = l2Table.address; + + method = LUTREADMETHOD_MAC; + retVal = rtl8367c_getAsicL2LookupTb(method, &l2Table); + if (RT_ERR_L2_ENTRY_NOTFOUND == retVal) + return RT_ERR_L2_INDEXTBL_FULL; + else + return retVal; + + } + else + return retVal; +} + +/* Function Name: + * dal_rtl8367c_l2_ipVidMcastAddr_get + * Description: + * Get LUT IP multicast+VID entry. + * Input: + * pIpVidMcastAddr - IP & VID multicast Entry + * Output: + * pIpVidMcastAddr - IP & VID multicast Entry + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * + */ +rtk_api_ret_t dal_rtl8367c_l2_ipVidMcastAddr_get(rtk_l2_ipVidMcastAddr_t *pIpVidMcastAddr) +{ + rtk_api_ret_t retVal; + rtk_uint32 method; + rtl8367c_luttb l2Table; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pIpVidMcastAddr) + return RT_ERR_NULL_POINTER; + + if (pIpVidMcastAddr->vid > RTL8367C_VIDMAX) + return RT_ERR_L2_VID; + + if( (pIpVidMcastAddr->dip & 0xF0000000) != 0xE0000000) + return RT_ERR_INPUT; + + memset(&l2Table, 0x00, sizeof(rtl8367c_luttb)); + l2Table.sip = pIpVidMcastAddr->sip; + l2Table.dip = pIpVidMcastAddr->dip; + l2Table.l3lookup = 1; + l2Table.l3vidlookup = 1; + l2Table.l3_vid = pIpVidMcastAddr->vid; + method = LUTREADMETHOD_MAC; + if ((retVal = rtl8367c_getAsicL2LookupTb(method, &l2Table)) != RT_ERR_OK) + return retVal; + + pIpVidMcastAddr->address = l2Table.address; + + /* Get Logical port mask */ + if ((retVal = rtk_switch_portmask_P2L_get(l2Table.mbr, &pIpVidMcastAddr->portmask)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_l2_ipVidMcastAddr_next_get + * Description: + * Get Next IP Multicast+VID entry. + * Input: + * pAddress - The Address ID + * Output: + * pIpVidMcastAddr - IP & VID multicast Entry + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * Get the next IP multicast entry after the current entry pointed by pAddress. + * The address of next entry is returned by pAddress. User can use (address + 1) + * as pAddress to call this API again for dumping all IP multicast entries is LUT. + */ +rtk_api_ret_t dal_rtl8367c_l2_ipVidMcastAddr_next_get(rtk_uint32 *pAddress, rtk_l2_ipVidMcastAddr_t *pIpVidMcastAddr) +{ + rtk_api_ret_t retVal; + rtl8367c_luttb l2Table; + rtk_uint32 tmpAddress; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Error Checking */ + if ((pAddress == NULL) || (pIpVidMcastAddr == NULL)) + return RT_ERR_INPUT; + + if(*pAddress > RTK_MAX_LUT_ADDR_ID ) + return RT_ERR_L2_L2UNI_PARAM; + + memset(&l2Table, 0, sizeof(rtl8367c_luttb)); + tmpAddress = *pAddress; + + do + { + l2Table.address = tmpAddress; + if ((retVal = rtl8367c_getAsicL2LookupTb(LUTREADMETHOD_NEXT_L3MC, &l2Table)) != RT_ERR_OK) + return retVal; + + if(l2Table.address < tmpAddress) + return RT_ERR_L2_ENTRY_NOTFOUND; + + tmpAddress = l2Table.address + 1; + + }while(l2Table.l3vidlookup == 0); + + pIpVidMcastAddr->sip = l2Table.sip; + pIpVidMcastAddr->dip = l2Table.dip; + pIpVidMcastAddr->vid = l2Table.l3_vid; + pIpVidMcastAddr->address = l2Table.address; + + /* Get Logical port mask */ + if ((retVal = rtk_switch_portmask_P2L_get(l2Table.mbr, &pIpVidMcastAddr->portmask)) != RT_ERR_OK) + return retVal; + + *pAddress = l2Table.address; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_l2_ipVidMcastAddr_del + * Description: + * Delete a ip multicast+VID address entry from the specified device. + * Input: + * pIpVidMcastAddr - IP & VID multicast Entry + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * + */ +rtk_api_ret_t dal_rtl8367c_l2_ipVidMcastAddr_del(rtk_l2_ipVidMcastAddr_t *pIpVidMcastAddr) +{ + rtk_api_ret_t retVal; + rtk_uint32 method; + rtl8367c_luttb l2Table; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pIpVidMcastAddr) + return RT_ERR_NULL_POINTER; + + if (pIpVidMcastAddr->vid > RTL8367C_VIDMAX) + return RT_ERR_L2_VID; + + if( (pIpVidMcastAddr->dip & 0xF0000000) != 0xE0000000) + return RT_ERR_INPUT; + + memset(&l2Table, 0x00, sizeof(rtl8367c_luttb)); + l2Table.sip = pIpVidMcastAddr->sip; + l2Table.dip = pIpVidMcastAddr->dip; + l2Table.l3lookup = 1; + l2Table.l3vidlookup = 1; + l2Table.l3_vid = pIpVidMcastAddr->vid; + method = LUTREADMETHOD_MAC; + retVal = rtl8367c_getAsicL2LookupTb(method, &l2Table); + if (RT_ERR_OK == retVal) + { + l2Table.sip = pIpVidMcastAddr->sip; + l2Table.dip = pIpVidMcastAddr->dip; + l2Table.mbr= 0; + l2Table.nosalearn = 0; + l2Table.l3lookup = 1; + l2Table.l3vidlookup = 1; + l2Table.l3_vid = pIpVidMcastAddr->vid; + if((retVal = rtl8367c_setAsicL2LookupTb(&l2Table)) != RT_ERR_OK) + return retVal; + + pIpVidMcastAddr->address = l2Table.address; + return RT_ERR_OK; + } + else + return retVal; +} + +/* Function Name: + * dal_rtl8367c_l2_ucastAddr_flush + * Description: + * Flush L2 mac address by type in the specified device (both dynamic and static). + * Input: + * pConfig - flush configuration + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * flushByVid - 1: Flush by VID, 0: Don't flush by VID + * vid - VID (0 ~ 4095) + * flushByFid - 1: Flush by FID, 0: Don't flush by FID + * fid - FID (0 ~ 15) + * flushByPort - 1: Flush by Port, 0: Don't flush by Port + * port - Port ID + * flushByMac - Not Supported + * ucastAddr - Not Supported + * flushStaticAddr - 1: Flush both Static and Dynamic entries, 0: Flush only Dynamic entries + * flushAddrOnAllPorts - 1: Flush VID-matched entries at all ports, 0: Flush VID-matched entries per port. + */ +rtk_api_ret_t dal_rtl8367c_l2_ucastAddr_flush(rtk_l2_flushCfg_t *pConfig) +{ + rtk_api_ret_t retVal; + rtk_uint32 phyPort; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(pConfig == NULL) + return RT_ERR_NULL_POINTER; + + if(pConfig->flushByVid >= RTK_ENABLE_END) + return RT_ERR_ENABLE; + + if(pConfig->flushByFid >= RTK_ENABLE_END) + return RT_ERR_ENABLE; + + if(pConfig->flushByPort >= RTK_ENABLE_END) + return RT_ERR_ENABLE; + + if(pConfig->flushByMac >= RTK_ENABLE_END) + return RT_ERR_ENABLE; + + if(pConfig->flushStaticAddr >= RTK_ENABLE_END) + return RT_ERR_ENABLE; + + if(pConfig->flushAddrOnAllPorts >= RTK_ENABLE_END) + return RT_ERR_ENABLE; + + if(pConfig->vid > RTL8367C_VIDMAX) + return RT_ERR_VLAN_VID; + + if(pConfig->fid > RTL8367C_FIDMAX) + return RT_ERR_INPUT; + + /* check port valid */ + RTK_CHK_PORT_VALID(pConfig->port); + + phyPort = rtk_switch_port_L2P_get(pConfig->port); + if (phyPort == UNDEFINE_PHY_PORT) + return RT_ERR_PORT_ID; + + if(pConfig->flushByVid == ENABLED) + { + if ((retVal = rtl8367c_setAsicLutFlushMode(FLUSHMDOE_VID)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicLutFlushVid(pConfig->vid)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicLutFlushType((pConfig->flushStaticAddr == ENABLED) ? FLUSHTYPE_BOTH : FLUSHTYPE_DYNAMIC)) != RT_ERR_OK) + return retVal; + + if(pConfig->flushAddrOnAllPorts == ENABLED) + { + if ((retVal = rtl8367c_setAsicLutForceFlush(RTL8367C_PORTMASK)) != RT_ERR_OK) + return retVal; + } + else if(pConfig->flushByPort == ENABLED) + { + if ((retVal = rtl8367c_setAsicLutForceFlush(1 << phyPort)) != RT_ERR_OK) + return retVal; + } + else + return RT_ERR_INPUT; + } + else if(pConfig->flushByFid == ENABLED) + { + if ((retVal = rtl8367c_setAsicLutFlushMode(FLUSHMDOE_FID)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicLutFlushFid(pConfig->fid)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicLutFlushType((pConfig->flushStaticAddr == ENABLED) ? FLUSHTYPE_BOTH : FLUSHTYPE_DYNAMIC)) != RT_ERR_OK) + return retVal; + + if(pConfig->flushAddrOnAllPorts == ENABLED) + { + if ((retVal = rtl8367c_setAsicLutForceFlush(RTL8367C_PORTMASK)) != RT_ERR_OK) + return retVal; + } + else if(pConfig->flushByPort == ENABLED) + { + if ((retVal = rtl8367c_setAsicLutForceFlush(1 << phyPort)) != RT_ERR_OK) + return retVal; + } + else + return RT_ERR_INPUT; + } + else if(pConfig->flushByPort == ENABLED) + { + if ((retVal = rtl8367c_setAsicLutFlushType((pConfig->flushStaticAddr == ENABLED) ? FLUSHTYPE_BOTH : FLUSHTYPE_DYNAMIC)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicLutFlushMode(FLUSHMDOE_PORT)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicLutForceFlush(1 << phyPort)) != RT_ERR_OK) + return retVal; + } + else if(pConfig->flushByMac == ENABLED) + { + /* Should use API "rtk_l2_addr_del" to remove a specified entry*/ + return RT_ERR_CHIP_NOT_SUPPORTED; + } + else + return RT_ERR_INPUT; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_l2_table_clear + * Description: + * Flush all static & dynamic entries in LUT. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * + */ +rtk_api_ret_t dal_rtl8367c_l2_table_clear(void) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if ((retVal = rtl8367c_setAsicLutFlushAll()) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_l2_table_clearStatus_get + * Description: + * Get table clear status + * Input: + * None + * Output: + * pStatus - Clear status, 1:Busy, 0:finish + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * + */ +rtk_api_ret_t dal_rtl8367c_l2_table_clearStatus_get(rtk_l2_clearStatus_t *pStatus) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pStatus) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicLutFlushAllStatus((rtk_uint32 *)pStatus)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_l2_flushLinkDownPortAddrEnable_set + * Description: + * Set HW flush linkdown port mac configuration of the specified device. + * Input: + * port - Port id. + * enable - link down flush status + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * The status of flush linkdown port address is as following: + * - DISABLED + * - ENABLED + */ +rtk_api_ret_t dal_rtl8367c_l2_flushLinkDownPortAddrEnable_set(rtk_port_t port, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (port != RTK_WHOLE_SYSTEM) + return RT_ERR_PORT_ID; + + if (enable >= RTK_ENABLE_END) + return RT_ERR_ENABLE; + + if ((retVal = rtl8367c_setAsicLutLinkDownForceAging(enable)) != RT_ERR_OK) + return retVal; + + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_l2_flushLinkDownPortAddrEnable_get + * Description: + * Get HW flush linkdown port mac configuration of the specified device. + * Input: + * port - Port id. + * Output: + * pEnable - link down flush status + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The status of flush linkdown port address is as following: + * - DISABLED + * - ENABLED + */ +rtk_api_ret_t dal_rtl8367c_l2_flushLinkDownPortAddrEnable_get(rtk_port_t port, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (port != RTK_WHOLE_SYSTEM) + return RT_ERR_PORT_ID; + + if(NULL == pEnable) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicLutLinkDownForceAging(pEnable)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_l2_agingEnable_set + * Description: + * Set L2 LUT aging status per port setting. + * Input: + * port - Port id. + * enable - Aging status + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * This API can be used to set L2 LUT aging status per port. + */ +rtk_api_ret_t dal_rtl8367c_l2_agingEnable_set(rtk_port_t port, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* check port valid */ + RTK_CHK_PORT_VALID(port); + + if (enable >= RTK_ENABLE_END) + return RT_ERR_ENABLE; + + if(enable == 1) + enable = 0; + else + enable = 1; + + if ((retVal = rtl8367c_setAsicLutDisableAging(rtk_switch_port_L2P_get(port), enable)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_l2_agingEnable_get + * Description: + * Get L2 LUT aging status per port setting. + * Input: + * port - Port id. + * Output: + * pEnable - Aging status + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can be used to get L2 LUT aging function per port. + */ +rtk_api_ret_t dal_rtl8367c_l2_agingEnable_get(rtk_port_t port, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* check port valid */ + RTK_CHK_PORT_VALID(port); + + if(NULL == pEnable) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicLutDisableAging(rtk_switch_port_L2P_get(port), pEnable)) != RT_ERR_OK) + return retVal; + + if(*pEnable == 1) + *pEnable = 0; + else + *pEnable = 1; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_l2_limitLearningCnt_set + * Description: + * Set per-Port auto learning limit number + * Input: + * port - Port id. + * mac_cnt - Auto learning entries limit number + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_LIMITED_L2ENTRY_NUM - Invalid auto learning limit number + * Note: + * The API can set per-port ASIC auto learning limit number from 0(disable learning) + * to 2112. + */ +rtk_api_ret_t dal_rtl8367c_l2_limitLearningCnt_set(rtk_port_t port, rtk_mac_cnt_t mac_cnt) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* check port valid */ + RTK_CHK_PORT_VALID(port); + + if (mac_cnt > rtk_switch_maxLutAddrNumber_get()) + return RT_ERR_LIMITED_L2ENTRY_NUM; + + if ((retVal = rtl8367c_setAsicLutLearnLimitNo(rtk_switch_port_L2P_get(port), mac_cnt)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_l2_limitLearningCnt_get + * Description: + * Get per-Port auto learning limit number + * Input: + * port - Port id. + * Output: + * pMac_cnt - Auto learning entries limit number + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get per-port ASIC auto learning limit number. + */ +rtk_api_ret_t dal_rtl8367c_l2_limitLearningCnt_get(rtk_port_t port, rtk_mac_cnt_t *pMac_cnt) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* check port valid */ + RTK_CHK_PORT_VALID(port); + + if(NULL == pMac_cnt) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicLutLearnLimitNo(rtk_switch_port_L2P_get(port), pMac_cnt)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_l2_limitSystemLearningCnt_set + * Description: + * Set System auto learning limit number + * Input: + * mac_cnt - Auto learning entries limit number + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_LIMITED_L2ENTRY_NUM - Invalid auto learning limit number + * Note: + * The API can set system ASIC auto learning limit number from 0(disable learning) + * to 2112. + */ +rtk_api_ret_t dal_rtl8367c_l2_limitSystemLearningCnt_set(rtk_mac_cnt_t mac_cnt) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (mac_cnt > rtk_switch_maxLutAddrNumber_get()) + return RT_ERR_LIMITED_L2ENTRY_NUM; + + if ((retVal = rtl8367c_setAsicSystemLutLearnLimitNo(mac_cnt)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_l2_limitSystemLearningCnt_get + * Description: + * Get System auto learning limit number + * Input: + * None + * Output: + * pMac_cnt - Auto learning entries limit number + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get system ASIC auto learning limit number. + */ +rtk_api_ret_t dal_rtl8367c_l2_limitSystemLearningCnt_get(rtk_mac_cnt_t *pMac_cnt) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pMac_cnt) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicSystemLutLearnLimitNo(pMac_cnt)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_l2_limitLearningCntAction_set + * Description: + * Configure auto learn over limit number action. + * Input: + * port - Port id. + * action - Auto learning entries limit number + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_NOT_ALLOWED - Invalid learn over action + * Note: + * The API can set SA unknown packet action while auto learn limit number is over + * The action symbol as following: + * - LIMIT_LEARN_CNT_ACTION_DROP, + * - LIMIT_LEARN_CNT_ACTION_FORWARD, + * - LIMIT_LEARN_CNT_ACTION_TO_CPU, + */ +rtk_api_ret_t dal_rtl8367c_l2_limitLearningCntAction_set(rtk_port_t port, rtk_l2_limitLearnCntAction_t action) +{ + rtk_api_ret_t retVal; + rtk_uint32 data; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (port != RTK_WHOLE_SYSTEM) + return RT_ERR_PORT_ID; + + if ( LIMIT_LEARN_CNT_ACTION_DROP == action ) + data = 1; + else if ( LIMIT_LEARN_CNT_ACTION_FORWARD == action ) + data = 0; + else if ( LIMIT_LEARN_CNT_ACTION_TO_CPU == action ) + data = 2; + else + return RT_ERR_NOT_ALLOWED; + + if ((retVal = rtl8367c_setAsicLutLearnOverAct(data)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_l2_limitLearningCntAction_get + * Description: + * Get auto learn over limit number action. + * Input: + * port - Port id. + * Output: + * pAction - Learn over action + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get SA unknown packet action while auto learn limit number is over + * The action symbol as following: + * - LIMIT_LEARN_CNT_ACTION_DROP, + * - LIMIT_LEARN_CNT_ACTION_FORWARD, + * - LIMIT_LEARN_CNT_ACTION_TO_CPU, + */ +rtk_api_ret_t dal_rtl8367c_l2_limitLearningCntAction_get(rtk_port_t port, rtk_l2_limitLearnCntAction_t *pAction) +{ + rtk_api_ret_t retVal; + rtk_uint32 action; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (port != RTK_WHOLE_SYSTEM) + return RT_ERR_PORT_ID; + + if(NULL == pAction) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicLutLearnOverAct(&action)) != RT_ERR_OK) + return retVal; + + if ( 1 == action ) + *pAction = LIMIT_LEARN_CNT_ACTION_DROP; + else if ( 0 == action ) + *pAction = LIMIT_LEARN_CNT_ACTION_FORWARD; + else if ( 2 == action ) + *pAction = LIMIT_LEARN_CNT_ACTION_TO_CPU; + else + *pAction = action; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_l2_limitSystemLearningCntAction_set + * Description: + * Configure system auto learn over limit number action. + * Input: + * port - Port id. + * action - Auto learning entries limit number + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_NOT_ALLOWED - Invalid learn over action + * Note: + * The API can set SA unknown packet action while auto learn limit number is over + * The action symbol as following: + * - LIMIT_LEARN_CNT_ACTION_DROP, + * - LIMIT_LEARN_CNT_ACTION_FORWARD, + * - LIMIT_LEARN_CNT_ACTION_TO_CPU, + */ +rtk_api_ret_t dal_rtl8367c_l2_limitSystemLearningCntAction_set(rtk_l2_limitLearnCntAction_t action) +{ + rtk_api_ret_t retVal; + rtk_uint32 data; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if ( LIMIT_LEARN_CNT_ACTION_DROP == action ) + data = 1; + else if ( LIMIT_LEARN_CNT_ACTION_FORWARD == action ) + data = 0; + else if ( LIMIT_LEARN_CNT_ACTION_TO_CPU == action ) + data = 2; + else + return RT_ERR_NOT_ALLOWED; + + if ((retVal = rtl8367c_setAsicSystemLutLearnOverAct(data)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_l2_limitSystemLearningCntAction_get + * Description: + * Get system auto learn over limit number action. + * Input: + * None. + * Output: + * pAction - Learn over action + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get SA unknown packet action while auto learn limit number is over + * The action symbol as following: + * - LIMIT_LEARN_CNT_ACTION_DROP, + * - LIMIT_LEARN_CNT_ACTION_FORWARD, + * - LIMIT_LEARN_CNT_ACTION_TO_CPU, + */ +rtk_api_ret_t dal_rtl8367c_l2_limitSystemLearningCntAction_get(rtk_l2_limitLearnCntAction_t *pAction) +{ + rtk_api_ret_t retVal; + rtk_uint32 action; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pAction) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicSystemLutLearnOverAct(&action)) != RT_ERR_OK) + return retVal; + + if ( 1 == action ) + *pAction = LIMIT_LEARN_CNT_ACTION_DROP; + else if ( 0 == action ) + *pAction = LIMIT_LEARN_CNT_ACTION_FORWARD; + else if ( 2 == action ) + *pAction = LIMIT_LEARN_CNT_ACTION_TO_CPU; + else + *pAction = action; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_l2_limitSystemLearningCntPortMask_set + * Description: + * Configure system auto learn portmask + * Input: + * pPortmask - Port Mask + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Invalid port mask. + * Note: + * + */ +rtk_api_ret_t dal_rtl8367c_l2_limitSystemLearningCntPortMask_set(rtk_portmask_t *pPortmask) +{ + rtk_api_ret_t retVal; + rtk_uint32 pmask; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pPortmask) + return RT_ERR_NULL_POINTER; + + /* Check port mask */ + RTK_CHK_PORTMASK_VALID(pPortmask); + + if ((retVal = rtk_switch_portmask_L2P_get(pPortmask, &pmask)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicSystemLutLearnPortMask(pmask)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_l2_limitSystemLearningCntPortMask_get + * Description: + * get system auto learn portmask + * Input: + * None + * Output: + * pPortmask - Port Mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Null pointer. + * Note: + * + */ +rtk_api_ret_t dal_rtl8367c_l2_limitSystemLearningCntPortMask_get(rtk_portmask_t *pPortmask) +{ + rtk_api_ret_t retVal; + rtk_uint32 pmask; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pPortmask) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicSystemLutLearnPortMask(&pmask)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtk_switch_portmask_P2L_get(pmask, pPortmask)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_l2_learningCnt_get + * Description: + * Get per-Port current auto learning number + * Input: + * port - Port id. + * Output: + * pMac_cnt - ASIC auto learning entries number + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get per-port ASIC auto learning number + */ +rtk_api_ret_t dal_rtl8367c_l2_learningCnt_get(rtk_port_t port, rtk_mac_cnt_t *pMac_cnt) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* check port valid */ + RTK_CHK_PORT_VALID(port); + + if(NULL == pMac_cnt) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicLutLearnNo(rtk_switch_port_L2P_get(port), pMac_cnt)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_l2_floodPortMask_set + * Description: + * Set flooding portmask + * Input: + * type - flooding type. + * pFlood_portmask - flooding porkmask + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Invalid portmask. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can set the flooding mask. + * The flooding type is as following: + * - FLOOD_UNKNOWNDA + * - FLOOD_UNKNOWNMC + * - FLOOD_BC + */ +rtk_api_ret_t dal_rtl8367c_l2_floodPortMask_set(rtk_l2_flood_type_t floood_type, rtk_portmask_t *pFlood_portmask) +{ + rtk_api_ret_t retVal; + rtk_uint32 pmask; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (floood_type >= FLOOD_END) + return RT_ERR_INPUT; + + /* check port valid */ + RTK_CHK_PORTMASK_VALID(pFlood_portmask); + + /* Get Physical port mask */ + if ((retVal = rtk_switch_portmask_L2P_get(pFlood_portmask, &pmask))!=RT_ERR_OK) + return retVal; + + switch (floood_type) + { + case FLOOD_UNKNOWNDA: + if ((retVal = rtl8367c_setAsicPortUnknownDaFloodingPortmask(pmask)) != RT_ERR_OK) + return retVal; + break; + case FLOOD_UNKNOWNMC: + if ((retVal = rtl8367c_setAsicPortUnknownMulticastFloodingPortmask(pmask)) != RT_ERR_OK) + return retVal; + break; + case FLOOD_BC: + if ((retVal = rtl8367c_setAsicPortBcastFloodingPortmask(pmask)) != RT_ERR_OK) + return retVal; + break; + default: + break; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_l2_floodPortMask_get + * Description: + * Get flooding portmask + * Input: + * type - flooding type. + * Output: + * pFlood_portmask - flooding porkmask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can get the flooding mask. + * The flooding type is as following: + * - FLOOD_UNKNOWNDA + * - FLOOD_UNKNOWNMC + * - FLOOD_BC + */ +rtk_api_ret_t dal_rtl8367c_l2_floodPortMask_get(rtk_l2_flood_type_t floood_type, rtk_portmask_t *pFlood_portmask) +{ + rtk_api_ret_t retVal; + rtk_uint32 pmask; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (floood_type >= FLOOD_END) + return RT_ERR_INPUT; + + if(NULL == pFlood_portmask) + return RT_ERR_NULL_POINTER; + + switch (floood_type) + { + case FLOOD_UNKNOWNDA: + if ((retVal = rtl8367c_getAsicPortUnknownDaFloodingPortmask(&pmask)) != RT_ERR_OK) + return retVal; + break; + case FLOOD_UNKNOWNMC: + if ((retVal = rtl8367c_getAsicPortUnknownMulticastFloodingPortmask(&pmask)) != RT_ERR_OK) + return retVal; + break; + case FLOOD_BC: + if ((retVal = rtl8367c_getAsicPortBcastFloodingPortmask(&pmask)) != RT_ERR_OK) + return retVal; + break; + default: + break; + } + + /* Get Logical port mask */ + if ((retVal = rtk_switch_portmask_P2L_get(pmask, pFlood_portmask))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_l2_localPktPermit_set + * Description: + * Set permittion of frames if source port and destination port are the same. + * Input: + * port - Port id. + * permit - permittion status + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid permit value. + * Note: + * This API is setted to permit frame if its source port is equal to destination port. + */ +rtk_api_ret_t dal_rtl8367c_l2_localPktPermit_set(rtk_port_t port, rtk_enable_t permit) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* check port valid */ + RTK_CHK_PORT_VALID(port); + + if (permit >= RTK_ENABLE_END) + return RT_ERR_ENABLE; + + if ((retVal = rtl8367c_setAsicPortBlockSpa(rtk_switch_port_L2P_get(port), permit)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_l2_localPktPermit_get + * Description: + * Get permittion of frames if source port and destination port are the same. + * Input: + * port - Port id. + * Output: + * pPermit - permittion status + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API is to get permittion status for frames if its source port is equal to destination port. + */ +rtk_api_ret_t dal_rtl8367c_l2_localPktPermit_get(rtk_port_t port, rtk_enable_t *pPermit) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* check port valid */ + RTK_CHK_PORT_VALID(port); + + if(NULL == pPermit) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicPortBlockSpa(rtk_switch_port_L2P_get(port), pPermit)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_l2_aging_set + * Description: + * Set LUT agging out speed + * Input: + * aging_time - Agging out time. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - input out of range. + * Note: + * The API can set LUT agging out period for each entry and the range is from 45s to 458s. + */ +rtk_api_ret_t dal_rtl8367c_l2_aging_set(rtk_l2_age_time_t aging_time) +{ + rtk_uint32 i; + CONST_T rtk_uint32 agePara[10][3] = { + {45, 0, 1}, {88, 0, 2}, {133, 0, 3}, {177, 0, 4}, {221, 0, 5}, {266, 0, 6}, {310, 0, 7}, + {354, 2, 6}, {413, 2, 7}, {458, 3, 7}}; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (aging_time>agePara[9][0]) + return RT_ERR_OUT_OF_RANGE; + + for (i = 0; i<10; i++) + { + if (aging_time<=agePara[i][0]) + { + return rtl8367c_setAsicLutAgeTimerSpeed(agePara[i][2], agePara[i][1]); + } + } + + return RT_ERR_FAILED; +} + +/* Function Name: + * dal_rtl8367c_l2_aging_get + * Description: + * Get LUT agging out time + * Input: + * None + * Output: + * pEnable - Aging status + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get LUT agging out period for each entry. + */ +rtk_api_ret_t dal_rtl8367c_l2_aging_get(rtk_l2_age_time_t *pAging_time) +{ + rtk_api_ret_t retVal; + rtk_uint32 i,time, speed; + CONST_T rtk_uint32 agePara[10][3] = { + {45, 0, 1}, {88, 0, 2}, {133, 0, 3}, {177, 0, 4}, {221, 0, 5}, {266, 0, 6}, {310, 0, 7}, + {354, 2, 6}, {413, 2, 7}, {458, 3, 7}}; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pAging_time) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicLutAgeTimerSpeed(&time, &speed)) != RT_ERR_OK) + return retVal; + + for (i = 0; i<10; i++) + { + if (time==agePara[i][2]&&speed==agePara[i][1]) + { + *pAging_time = agePara[i][0]; + return RT_ERR_OK; + } + } + + return RT_ERR_FAILED; +} + +/* Function Name: + * dal_rtl8367c_l2_ipMcastAddrLookup_set + * Description: + * Set Lut IP multicast lookup function + * Input: + * type - Lookup type for IPMC packet. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * LOOKUP_MAC - Lookup by MAC address + * LOOKUP_IP - Lookup by IP address + * LOOKUP_IP_VID - Lookup by IP address & VLAN ID + */ +rtk_api_ret_t dal_rtl8367c_l2_ipMcastAddrLookup_set(rtk_l2_ipmc_lookup_type_t type) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(type == LOOKUP_MAC) + { + if((retVal = rtl8367c_setAsicLutIpMulticastLookup(DISABLED)) != RT_ERR_OK) + return retVal; + } + else if(type == LOOKUP_IP) + { + if((retVal = rtl8367c_setAsicLutIpMulticastLookup(ENABLED)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicLutIpMulticastVidLookup(DISABLED))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicLutIpLookupMethod(1))!=RT_ERR_OK) + return retVal; + } + else if(type == LOOKUP_IP_VID) + { + if((retVal = rtl8367c_setAsicLutIpMulticastLookup(ENABLED)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicLutIpMulticastVidLookup(ENABLED))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicLutIpLookupMethod(1))!=RT_ERR_OK) + return retVal; + } + else + return RT_ERR_INPUT; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_l2_ipMcastAddrLookup_get + * Description: + * Get Lut IP multicast lookup function + * Input: + * None. + * Output: + * pType - Lookup type for IPMC packet. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * None. + */ +rtk_api_ret_t dal_rtl8367c_l2_ipMcastAddrLookup_get(rtk_l2_ipmc_lookup_type_t *pType) +{ + rtk_api_ret_t retVal; + rtk_uint32 enabled, vid_lookup; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pType) + return RT_ERR_NULL_POINTER; + + if((retVal = rtl8367c_getAsicLutIpMulticastLookup(&enabled)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_getAsicLutIpMulticastVidLookup(&vid_lookup))!=RT_ERR_OK) + return retVal; + + if(enabled == ENABLED) + { + if(vid_lookup == ENABLED) + *pType = LOOKUP_IP_VID; + else + *pType = LOOKUP_IP; + } + else + *pType = LOOKUP_MAC; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_l2_ipMcastForwardRouterPort_set + * Description: + * Set IPMC packet forward to rounter port also or not + * Input: + * enabled - 1: Inlcude router port, 0, exclude router port + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * + */ +rtk_api_ret_t dal_rtl8367c_l2_ipMcastForwardRouterPort_set(rtk_enable_t enabled) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (enabled >= RTK_ENABLE_END) + return RT_ERR_ENABLE; + + if((retVal = rtl8367c_setAsicLutIpmcFwdRouterPort(enabled)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_l2_ipMcastForwardRouterPort_get + * Description: + * Get IPMC packet forward to rounter port also or not + * Input: + * None. + * Output: + * pEnabled - 1: Inlcude router port, 0, exclude router port + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * + */ +rtk_api_ret_t dal_rtl8367c_l2_ipMcastForwardRouterPort_get(rtk_enable_t *pEnabled) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (NULL == pEnabled) + return RT_ERR_NULL_POINTER; + + if((retVal = rtl8367c_getAsicLutIpmcFwdRouterPort(pEnabled)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_l2_ipMcastGroupEntry_add + * Description: + * Add an IP Multicast entry to group table + * Input: + * ip_addr - IP address + * vid - VLAN ID + * pPortmask - portmask + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_TBL_FULL - Table Full + * Note: + * Add an entry to IP Multicast Group table. + */ +rtk_api_ret_t dal_rtl8367c_l2_ipMcastGroupEntry_add(ipaddr_t ip_addr, rtk_uint32 vid, rtk_portmask_t *pPortmask) +{ + rtk_uint32 empty_idx = 0xFFFF; + rtk_int32 index; + ipaddr_t group_addr; + rtk_uint32 group_vid; + rtk_uint32 pmask; + rtk_uint32 valid; + rtk_uint32 physicalPortmask; + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (vid > RTL8367C_VIDMAX) + return RT_ERR_L2_VID; + + if(NULL == pPortmask) + return RT_ERR_NULL_POINTER; + + if((ip_addr & 0xF0000000) != 0xE0000000) + return RT_ERR_INPUT; + + /* Get Physical port mask */ + if ((retVal = rtk_switch_portmask_L2P_get(pPortmask, &physicalPortmask))!=RT_ERR_OK) + return retVal; + + for(index = 0; index <= RTL8367C_LUT_IPMCGRP_TABLE_MAX; index++) + { + if ((retVal = rtl8367c_getAsicLutIPMCGroup((rtk_uint32)index, &group_addr, &group_vid, &pmask, &valid))!=RT_ERR_OK) + return retVal; + + if( (valid == ENABLED) && (group_addr == ip_addr) && (group_vid == vid) ) + { + if(pmask != physicalPortmask) + { + pmask = physicalPortmask; + if ((retVal = rtl8367c_setAsicLutIPMCGroup(index, ip_addr, vid, pmask, valid))!=RT_ERR_OK) + return retVal; + } + + return RT_ERR_OK; + } + + if( (valid == DISABLED) && (empty_idx == 0xFFFF) ) /* Unused */ + empty_idx = (rtk_uint32)index; + } + + if(empty_idx == 0xFFFF) + return RT_ERR_TBL_FULL; + + pmask = physicalPortmask; + if ((retVal = rtl8367c_setAsicLutIPMCGroup(empty_idx, ip_addr, vid, pmask, ENABLED))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_l2_ipMcastGroupEntry_del + * Description: + * Delete an entry from IP Multicast group table + * Input: + * ip_addr - IP address + * vid - VLAN ID + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_TBL_FULL - Table Full + * Note: + * Delete an entry from IP Multicast group table. + */ +rtk_api_ret_t dal_rtl8367c_l2_ipMcastGroupEntry_del(ipaddr_t ip_addr, rtk_uint32 vid) +{ + rtk_int32 index; + ipaddr_t group_addr; + rtk_uint32 group_vid; + rtk_uint32 pmask; + rtk_uint32 valid; + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (vid > RTL8367C_VIDMAX) + return RT_ERR_L2_VID; + + if((ip_addr & 0xF0000000) != 0xE0000000) + return RT_ERR_INPUT; + + for(index = 0; index <= RTL8367C_LUT_IPMCGRP_TABLE_MAX; index++) + { + if ((retVal = rtl8367c_getAsicLutIPMCGroup((rtk_uint32)index, &group_addr, &group_vid, &pmask, &valid))!=RT_ERR_OK) + return retVal; + + if( (valid == ENABLED) && (group_addr == ip_addr) && (group_vid == vid) ) + { + group_addr = 0xE0000000; + group_vid = 0; + pmask = 0; + if ((retVal = rtl8367c_setAsicLutIPMCGroup(index, group_addr, group_vid, pmask, DISABLED))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; + } + } + + return RT_ERR_FAILED; +} + +/* Function Name: + * dal_rtl8367c_l2_ipMcastGroupEntry_get + * Description: + * get an entry from IP Multicast group table + * Input: + * ip_addr - IP address + * vid - VLAN ID + * Output: + * pPortmask - member port mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_TBL_FULL - Table Full + * Note: + * Delete an entry from IP Multicast group table. + */ +rtk_api_ret_t dal_rtl8367c_l2_ipMcastGroupEntry_get(ipaddr_t ip_addr, rtk_uint32 vid, rtk_portmask_t *pPortmask) +{ + rtk_int32 index; + ipaddr_t group_addr; + rtk_uint32 group_vid; + rtk_uint32 valid; + rtk_uint32 pmask; + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if((ip_addr & 0xF0000000) != 0xE0000000) + return RT_ERR_INPUT; + + if (vid > RTL8367C_VIDMAX) + return RT_ERR_L2_VID; + + if(NULL == pPortmask) + return RT_ERR_NULL_POINTER; + + for(index = 0; index <= RTL8367C_LUT_IPMCGRP_TABLE_MAX; index++) + { + if ((retVal = rtl8367c_getAsicLutIPMCGroup((rtk_uint32)index, &group_addr, &group_vid, &pmask, &valid))!=RT_ERR_OK) + return retVal; + + if( (valid == ENABLED) && (group_addr == ip_addr) && (group_vid == vid) ) + { + if ((retVal = rtk_switch_portmask_P2L_get(pmask, pPortmask))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; + } + } + + return RT_ERR_FAILED; +} + +/* Function Name: + * dal_rtl8367c_l2_entry_get + * Description: + * Get LUT unicast entry. + * Input: + * pL2_entry - Index field in the structure. + * Output: + * pL2_entry - other fields such as MAC, port, age... + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_EMPTY_ENTRY - Empty LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API is used to get address by index from 0~2111. + */ +rtk_api_ret_t dal_rtl8367c_l2_entry_get(rtk_l2_addr_table_t *pL2_entry) +{ + rtk_api_ret_t retVal; + rtk_uint32 method; + rtl8367c_luttb l2Table; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (pL2_entry->index >= rtk_switch_maxLutAddrNumber_get()) + return RT_ERR_INPUT; + + memset(&l2Table, 0x00, sizeof(rtl8367c_luttb)); + l2Table.address= pL2_entry->index; + method = LUTREADMETHOD_ADDRESS; + if ((retVal = rtl8367c_getAsicL2LookupTb(method, &l2Table)) != RT_ERR_OK) + return retVal; + + if ((pL2_entry->index>0x800)&&(l2Table.lookup_hit==0)) + return RT_ERR_L2_EMPTY_ENTRY; + + if(l2Table.l3lookup) + { + if(l2Table.l3vidlookup) + { + memset(&pL2_entry->mac, 0, sizeof(rtk_mac_t)); + pL2_entry->is_ipmul = l2Table.l3lookup; + pL2_entry->sip = l2Table.sip; + pL2_entry->dip = l2Table.dip; + pL2_entry->is_static = l2Table.nosalearn; + + /* Get Logical port mask */ + if ((retVal = rtk_switch_portmask_P2L_get(l2Table.mbr, &(pL2_entry->portmask)))!=RT_ERR_OK) + return retVal; + + pL2_entry->fid = 0; + pL2_entry->age = 0; + pL2_entry->auth = 0; + pL2_entry->sa_block = 0; + pL2_entry->is_ipvidmul = 1; + pL2_entry->l3_vid = l2Table.l3_vid; + } + else + { + memset(&pL2_entry->mac, 0, sizeof(rtk_mac_t)); + pL2_entry->is_ipmul = l2Table.l3lookup; + pL2_entry->sip = l2Table.sip; + pL2_entry->dip = l2Table.dip; + pL2_entry->is_static = l2Table.nosalearn; + + /* Get Logical port mask */ + if ((retVal = rtk_switch_portmask_P2L_get(l2Table.mbr, &(pL2_entry->portmask)))!=RT_ERR_OK) + return retVal; + + pL2_entry->fid = 0; + pL2_entry->age = 0; + pL2_entry->auth = 0; + pL2_entry->sa_block = 0; + pL2_entry->is_ipvidmul = 0; + pL2_entry->l3_vid = 0; + } + } + else if(l2Table.mac.octet[0]&0x01) + { + memset(&pL2_entry->sip, 0, sizeof(ipaddr_t)); + memset(&pL2_entry->dip, 0, sizeof(ipaddr_t)); + pL2_entry->mac.octet[0] = l2Table.mac.octet[0]; + pL2_entry->mac.octet[1] = l2Table.mac.octet[1]; + pL2_entry->mac.octet[2] = l2Table.mac.octet[2]; + pL2_entry->mac.octet[3] = l2Table.mac.octet[3]; + pL2_entry->mac.octet[4] = l2Table.mac.octet[4]; + pL2_entry->mac.octet[5] = l2Table.mac.octet[5]; + pL2_entry->is_ipmul = l2Table.l3lookup; + pL2_entry->is_static = l2Table.nosalearn; + + /* Get Logical port mask */ + if ((retVal = rtk_switch_portmask_P2L_get(l2Table.mbr, &(pL2_entry->portmask)))!=RT_ERR_OK) + return retVal; + + pL2_entry->ivl = l2Table.ivl_svl; + if(l2Table.ivl_svl == 1) /* IVL */ + { + pL2_entry->cvid = l2Table.cvid_fid; + pL2_entry->fid = 0; + } + else /* SVL*/ + { + pL2_entry->cvid = 0; + pL2_entry->fid = l2Table.cvid_fid; + } + pL2_entry->auth = l2Table.auth; + pL2_entry->sa_block = l2Table.sa_block; + pL2_entry->age = 0; + pL2_entry->is_ipvidmul = 0; + pL2_entry->l3_vid = 0; + } + else if((l2Table.age != 0)||(l2Table.nosalearn == 1)) + { + memset(&pL2_entry->sip, 0, sizeof(ipaddr_t)); + memset(&pL2_entry->dip, 0, sizeof(ipaddr_t)); + pL2_entry->mac.octet[0] = l2Table.mac.octet[0]; + pL2_entry->mac.octet[1] = l2Table.mac.octet[1]; + pL2_entry->mac.octet[2] = l2Table.mac.octet[2]; + pL2_entry->mac.octet[3] = l2Table.mac.octet[3]; + pL2_entry->mac.octet[4] = l2Table.mac.octet[4]; + pL2_entry->mac.octet[5] = l2Table.mac.octet[5]; + pL2_entry->is_ipmul = l2Table.l3lookup; + pL2_entry->is_static = l2Table.nosalearn; + + /* Get Logical port mask */ + if ((retVal = rtk_switch_portmask_P2L_get(1<<(l2Table.spa), &(pL2_entry->portmask)))!=RT_ERR_OK) + return retVal; + + pL2_entry->ivl = l2Table.ivl_svl; + pL2_entry->cvid = l2Table.cvid_fid; + pL2_entry->fid = l2Table.fid; + pL2_entry->auth = l2Table.auth; + pL2_entry->sa_block = l2Table.sa_block; + pL2_entry->age = l2Table.age; + pL2_entry->is_ipvidmul = 0; + pL2_entry->l3_vid = 0; + } + else + return RT_ERR_L2_EMPTY_ENTRY; + + return RT_ERR_OK; +} + + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_l2.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_l2.h new file mode 100644 index 00000000..9c52496f --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_l2.h @@ -0,0 +1,1037 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8367/RTL8367C switch high-level API + * + * Feature : The file includes L2 module high-layer API defination + * + */ + +#ifndef __DAL_RTL8367C_L2_H__ +#define __DAL_RTL8367C_L2_H__ + +#include + +/* + * Data Type Declaration + */ +#define RTK_MAX_NUM_OF_LEARN_LIMIT (rtk_switch_maxLutAddrNumber_get()) + +#define RTK_MAC_ADDR_LEN 6 +#define RTK_MAX_LUT_ADDRESS (RTK_MAX_NUM_OF_LEARN_LIMIT) +#define RTK_MAX_LUT_ADDR_ID (RTK_MAX_LUT_ADDRESS - 1) + +/* Function Name: + * dal_rtl8367c_l2_init + * Description: + * Initialize l2 module of the specified device. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * Initialize l2 module before calling any l2 APIs. + */ +extern rtk_api_ret_t dal_rtl8367c_l2_init(void); + +/* Function Name: + * dal_rtl8367c_l2_addr_add + * Description: + * Add LUT unicast entry. + * Input: + * pMac - 6 bytes unicast(I/G bit is 0) mac address to be written into LUT. + * pL2_data - Unicast entry parameter + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_L2_FID - Invalid FID . + * RT_ERR_L2_INDEXTBL_FULL - hashed index is full of entries. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * If the unicast mac address already existed in LUT, it will udpate the status of the entry. + * Otherwise, it will find an empty or asic auto learned entry to write. If all the entries + * with the same hash value can't be replaced, ASIC will return a RT_ERR_L2_INDEXTBL_FULL error. + */ +extern rtk_api_ret_t dal_rtl8367c_l2_addr_add(rtk_mac_t *pMac, rtk_l2_ucastAddr_t *pL2_data); + +/* Function Name: + * dal_rtl8367c_l2_addr_get + * Description: + * Get LUT unicast entry. + * Input: + * pMac - 6 bytes unicast(I/G bit is 0) mac address to be written into LUT. + * Output: + * pL2_data - Unicast entry parameter + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_L2_FID - Invalid FID . + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * If the unicast mac address existed in LUT, it will return the port and fid where + * the mac is learned. Otherwise, it will return a RT_ERR_L2_ENTRY_NOTFOUND error. + */ +extern rtk_api_ret_t dal_rtl8367c_l2_addr_get(rtk_mac_t *pMac, rtk_l2_ucastAddr_t *pL2_data); + +/* Function Name: + * dal_rtl8367c_l2_addr_next_get + * Description: + * Get Next LUT unicast entry. + * Input: + * read_method - The reading method. + * port - The port number if the read_metohd is READMETHOD_NEXT_L2UCSPA + * pAddress - The Address ID + * Output: + * pL2_data - Unicast entry parameter + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_L2_FID - Invalid FID . + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * Get the next unicast entry after the current entry pointed by pAddress. + * The address of next entry is returned by pAddress. User can use (address + 1) + * as pAddress to call this API again for dumping all entries is LUT. + */ +extern rtk_api_ret_t dal_rtl8367c_l2_addr_next_get(rtk_l2_read_method_t read_method, rtk_port_t port, rtk_uint32 *pAddress, rtk_l2_ucastAddr_t *pL2_data); + +/* Function Name: + * dal_rtl8367c_l2_addr_del + * Description: + * Delete LUT unicast entry. + * Input: + * pMac - 6 bytes unicast(I/G bit is 0) mac address to be written into LUT. + * fid - Filtering database + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_L2_FID - Invalid FID . + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * If the mac has existed in the LUT, it will be deleted. Otherwise, it will return RT_ERR_L2_ENTRY_NOTFOUND. + */ +extern rtk_api_ret_t dal_rtl8367c_l2_addr_del(rtk_mac_t *pMac, rtk_l2_ucastAddr_t *pL2_data); + +/* Function Name: + * dal_rtl8367c_l2_mcastAddr_add + * Description: + * Add LUT multicast entry. + * Input: + * pMcastAddr - L2 multicast entry structure + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_L2_FID - Invalid FID . + * RT_ERR_L2_VID - Invalid VID . + * RT_ERR_L2_INDEXTBL_FULL - hashed index is full of entries. + * RT_ERR_PORT_MASK - Invalid portmask. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * If the multicast mac address already existed in the LUT, it will udpate the + * port mask of the entry. Otherwise, it will find an empty or asic auto learned + * entry to write. If all the entries with the same hash value can't be replaced, + * ASIC will return a RT_ERR_L2_INDEXTBL_FULL error. + */ +extern rtk_api_ret_t dal_rtl8367c_l2_mcastAddr_add(rtk_l2_mcastAddr_t *pMcastAddr); + +/* Function Name: + * dal_rtl8367c_l2_mcastAddr_get + * Description: + * Get LUT multicast entry. + * Input: + * pMcastAddr - L2 multicast entry structure + * Output: + * pMcastAddr - L2 multicast entry structure + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_L2_FID - Invalid FID . + * RT_ERR_L2_VID - Invalid VID . + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * If the multicast mac address existed in the LUT, it will return the port where + * the mac is learned. Otherwise, it will return a RT_ERR_L2_ENTRY_NOTFOUND error. + */ +extern rtk_api_ret_t dal_rtl8367c_l2_mcastAddr_get(rtk_l2_mcastAddr_t *pMcastAddr); + +/* Function Name: + * dal_rtl8367c_l2_mcastAddr_next_get + * Description: + * Get Next L2 Multicast entry. + * Input: + * pAddress - The Address ID + * Output: + * pMcastAddr - L2 multicast entry structure + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * Get the next L2 multicast entry after the current entry pointed by pAddress. + * The address of next entry is returned by pAddress. User can use (address + 1) + * as pAddress to call this API again for dumping all multicast entries is LUT. + */ +extern rtk_api_ret_t dal_rtl8367c_l2_mcastAddr_next_get(rtk_uint32 *pAddress, rtk_l2_mcastAddr_t *pMcastAddr); + +/* Function Name: + * dal_rtl8367c_l2_mcastAddr_del + * Description: + * Delete LUT multicast entry. + * Input: + * pMcastAddr - L2 multicast entry structure + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_L2_FID - Invalid FID . + * RT_ERR_L2_VID - Invalid VID . + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * If the mac has existed in the LUT, it will be deleted. Otherwise, it will return RT_ERR_L2_ENTRY_NOTFOUND. + */ +extern rtk_api_ret_t dal_rtl8367c_l2_mcastAddr_del(rtk_l2_mcastAddr_t *pMcastAddr); + +/* Function Name: + * dal_rtl8367c_l2_ipMcastAddr_add + * Description: + * Add Lut IP multicast entry + * Input: + * pIpMcastAddr - IP Multicast entry + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_L2_INDEXTBL_FULL - hashed index is full of entries. + * RT_ERR_PORT_MASK - Invalid portmask. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * System supports L2 entry with IP multicast DIP/SIP to forward IP multicasting frame as user + * desired. If this function is enabled, then system will be looked up L2 IP multicast entry to + * forward IP multicast frame directly without flooding. + */ +extern rtk_api_ret_t dal_rtl8367c_l2_ipMcastAddr_add(rtk_l2_ipMcastAddr_t *pIpMcastAddr); + +/* Function Name: + * dal_rtl8367c_l2_ipMcastAddr_get + * Description: + * Get LUT IP multicast entry. + * Input: + * pIpMcastAddr - IP Multicast entry + * Output: + * pIpMcastAddr - IP Multicast entry + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get Lut table of IP multicast entry. + */ +extern rtk_api_ret_t dal_rtl8367c_l2_ipMcastAddr_get(rtk_l2_ipMcastAddr_t *pIpMcastAddr); + +/* Function Name: + * dal_rtl8367c_l2_ipMcastAddr_next_get + * Description: + * Get Next IP Multicast entry. + * Input: + * pAddress - The Address ID + * Output: + * pIpMcastAddr - IP Multicast entry + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * Get the next IP multicast entry after the current entry pointed by pAddress. + * The address of next entry is returned by pAddress. User can use (address + 1) + * as pAddress to call this API again for dumping all IP multicast entries is LUT. + */ +extern rtk_api_ret_t dal_rtl8367c_l2_ipMcastAddr_next_get(rtk_uint32 *pAddress, rtk_l2_ipMcastAddr_t *pIpMcastAddr); + +/* Function Name: + * dal_rtl8367c_l2_ipMcastAddr_del + * Description: + * Delete a ip multicast address entry from the specified device. + * Input: + * pIpMcastAddr - IP Multicast entry + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can delete a IP multicast address entry from the specified device. + */ +extern rtk_api_ret_t dal_rtl8367c_l2_ipMcastAddr_del(rtk_l2_ipMcastAddr_t *pIpMcastAddr); + +/* Function Name: + * dal_rtl8367c_l2_ipVidMcastAddr_add + * Description: + * Add Lut IP multicast+VID entry + * Input: + * pIpVidMcastAddr - IP & VID multicast Entry + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_L2_INDEXTBL_FULL - hashed index is full of entries. + * RT_ERR_PORT_MASK - Invalid portmask. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367c_l2_ipVidMcastAddr_add(rtk_l2_ipVidMcastAddr_t *pIpVidMcastAddr); + +/* Function Name: + * dal_rtl8367c_l2_ipVidMcastAddr_get + * Description: + * Get LUT IP multicast+VID entry. + * Input: + * pIpVidMcastAddr - IP & VID multicast Entry + * Output: + * pIpVidMcastAddr - IP & VID multicast Entry + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367c_l2_ipVidMcastAddr_get(rtk_l2_ipVidMcastAddr_t *pIpVidMcastAddr); + +/* Function Name: + * dal_rtl8367c_l2_ipVidMcastAddr_next_get + * Description: + * Get Next IP Multicast+VID entry. + * Input: + * pAddress - The Address ID + * Output: + * pIpVidMcastAddr - IP & VID multicast Entry + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * Get the next IP multicast entry after the current entry pointed by pAddress. + * The address of next entry is returned by pAddress. User can use (address + 1) + * as pAddress to call this API again for dumping all IP multicast entries is LUT. + */ +extern rtk_api_ret_t dal_rtl8367c_l2_ipVidMcastAddr_next_get(rtk_uint32 *pAddress, rtk_l2_ipVidMcastAddr_t *pIpVidMcastAddr); + +/* Function Name: + * dal_rtl8367c_l2_ipVidMcastAddr_del + * Description: + * Delete a ip multicast+VID address entry from the specified device. + * Input: + * pIpVidMcastAddr - IP & VID multicast Entry + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367c_l2_ipVidMcastAddr_del(rtk_l2_ipVidMcastAddr_t *pIpVidMcastAddr); + +/* Function Name: + * dal_rtl8367c_l2_ucastAddr_flush + * Description: + * Flush L2 mac address by type in the specified device (both dynamic and static). + * Input: + * pConfig - flush configuration + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * flushByVid - 1: Flush by VID, 0: Don't flush by VID + * vid - VID (0 ~ 4095) + * flushByFid - 1: Flush by FID, 0: Don't flush by FID + * fid - FID (0 ~ 15) + * flushByPort - 1: Flush by Port, 0: Don't flush by Port + * port - Port ID + * flushByMac - Not Supported + * ucastAddr - Not Supported + * flushStaticAddr - 1: Flush both Static and Dynamic entries, 0: Flush only Dynamic entries + * flushAddrOnAllPorts - 1: Flush VID-matched entries at all ports, 0: Flush VID-matched entries per port. + */ +extern rtk_api_ret_t dal_rtl8367c_l2_ucastAddr_flush(rtk_l2_flushCfg_t *pConfig); + +/* Function Name: + * dal_rtl8367c_l2_table_clear + * Description: + * Flush all static & dynamic entries in LUT. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367c_l2_table_clear(void); + +/* Function Name: + * dal_rtl8367c_l2_table_clearStatus_get + * Description: + * Get table clear status + * Input: + * None + * Output: + * pStatus - Clear status, 1:Busy, 0:finish + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367c_l2_table_clearStatus_get(rtk_l2_clearStatus_t *pStatus); + +/* Function Name: + * dal_rtl8367c_l2_flushLinkDownPortAddrEnable_set + * Description: + * Set HW flush linkdown port mac configuration of the specified device. + * Input: + * port - Port id. + * enable - link down flush status + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * The status of flush linkdown port address is as following: + * - DISABLED + * - ENABLED + */ +extern rtk_api_ret_t dal_rtl8367c_l2_flushLinkDownPortAddrEnable_set(rtk_port_t port, rtk_enable_t enable); + +/* Function Name: + * dal_rtl8367c_l2_flushLinkDownPortAddrEnable_get + * Description: + * Get HW flush linkdown port mac configuration of the specified device. + * Input: + * port - Port id. + * Output: + * pEnable - link down flush status + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The status of flush linkdown port address is as following: + * - DISABLED + * - ENABLED + */ +extern rtk_api_ret_t dal_rtl8367c_l2_flushLinkDownPortAddrEnable_get(rtk_port_t port, rtk_enable_t *pEnable); + +/* Function Name: + * dal_rtl8367c_l2_agingEnable_set + * Description: + * Set L2 LUT aging status per port setting. + * Input: + * port - Port id. + * enable - Aging status + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * This API can be used to set L2 LUT aging status per port. + */ +extern rtk_api_ret_t dal_rtl8367c_l2_agingEnable_set(rtk_port_t port, rtk_enable_t enable); + +/* Function Name: + * dal_rtl8367c_l2_agingEnable_get + * Description: + * Get L2 LUT aging status per port setting. + * Input: + * port - Port id. + * Output: + * pEnable - Aging status + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can be used to get L2 LUT aging function per port. + */ +extern rtk_api_ret_t dal_rtl8367c_l2_agingEnable_get(rtk_port_t port, rtk_enable_t *pEnable); + +/* Function Name: + * dal_rtl8367c_l2_limitLearningCnt_set + * Description: + * Set per-Port auto learning limit number + * Input: + * port - Port id. + * mac_cnt - Auto learning entries limit number + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_LIMITED_L2ENTRY_NUM - Invalid auto learning limit number + * Note: + * The API can set per-port ASIC auto learning limit number from 0(disable learning) + * to 8k. + */ +extern rtk_api_ret_t dal_rtl8367c_l2_limitLearningCnt_set(rtk_port_t port, rtk_mac_cnt_t mac_cnt); + +/* Function Name: + * dal_rtl8367c_l2_limitLearningCnt_get + * Description: + * Get per-Port auto learning limit number + * Input: + * port - Port id. + * Output: + * pMac_cnt - Auto learning entries limit number + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get per-port ASIC auto learning limit number. + */ +extern rtk_api_ret_t dal_rtl8367c_l2_limitLearningCnt_get(rtk_port_t port, rtk_mac_cnt_t *pMac_cnt); + +/* Function Name: + * dal_rtl8367c_l2_limitSystemLearningCnt_set + * Description: + * Set System auto learning limit number + * Input: + * mac_cnt - Auto learning entries limit number + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_LIMITED_L2ENTRY_NUM - Invalid auto learning limit number + * Note: + * The API can set system ASIC auto learning limit number from 0(disable learning) + * to 2112. + */ +extern rtk_api_ret_t dal_rtl8367c_l2_limitSystemLearningCnt_set(rtk_mac_cnt_t mac_cnt); + +/* Function Name: + * dal_rtl8367c_l2_limitSystemLearningCnt_get + * Description: + * Get System auto learning limit number + * Input: + * None + * Output: + * pMac_cnt - Auto learning entries limit number + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get system ASIC auto learning limit number. + */ +extern rtk_api_ret_t dal_rtl8367c_l2_limitSystemLearningCnt_get(rtk_mac_cnt_t *pMac_cnt); + +/* Function Name: + * dal_rtl8367c_l2_limitLearningCntAction_set + * Description: + * Configure auto learn over limit number action. + * Input: + * port - Port id. + * action - Auto learning entries limit number + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_NOT_ALLOWED - Invalid learn over action + * Note: + * The API can set SA unknown packet action while auto learn limit number is over + * The action symbol as following: + * - LIMIT_LEARN_CNT_ACTION_DROP, + * - LIMIT_LEARN_CNT_ACTION_FORWARD, + * - LIMIT_LEARN_CNT_ACTION_TO_CPU, + */ +extern rtk_api_ret_t dal_rtl8367c_l2_limitLearningCntAction_set(rtk_port_t port, rtk_l2_limitLearnCntAction_t action); + +/* Function Name: + * dal_rtl8367c_l2_limitLearningCntAction_get + * Description: + * Get auto learn over limit number action. + * Input: + * port - Port id. + * Output: + * pAction - Learn over action + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get SA unknown packet action while auto learn limit number is over + * The action symbol as following: + * - LIMIT_LEARN_CNT_ACTION_DROP, + * - LIMIT_LEARN_CNT_ACTION_FORWARD, + * - LIMIT_LEARN_CNT_ACTION_TO_CPU, + */ +extern rtk_api_ret_t dal_rtl8367c_l2_limitLearningCntAction_get(rtk_port_t port, rtk_l2_limitLearnCntAction_t *pAction); + +/* Function Name: + * dal_rtl8367c_l2_limitSystemLearningCntAction_set + * Description: + * Configure system auto learn over limit number action. + * Input: + * port - Port id. + * action - Auto learning entries limit number + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_NOT_ALLOWED - Invalid learn over action + * Note: + * The API can set SA unknown packet action while auto learn limit number is over + * The action symbol as following: + * - LIMIT_LEARN_CNT_ACTION_DROP, + * - LIMIT_LEARN_CNT_ACTION_FORWARD, + * - LIMIT_LEARN_CNT_ACTION_TO_CPU, + */ +extern rtk_api_ret_t dal_rtl8367c_l2_limitSystemLearningCntAction_set(rtk_l2_limitLearnCntAction_t action); + +/* Function Name: + * dal_rtl8367c_l2_limitSystemLearningCntAction_get + * Description: + * Get system auto learn over limit number action. + * Input: + * None. + * Output: + * pAction - Learn over action + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get SA unknown packet action while auto learn limit number is over + * The action symbol as following: + * - LIMIT_LEARN_CNT_ACTION_DROP, + * - LIMIT_LEARN_CNT_ACTION_FORWARD, + * - LIMIT_LEARN_CNT_ACTION_TO_CPU, + */ +extern rtk_api_ret_t dal_rtl8367c_l2_limitSystemLearningCntAction_get(rtk_l2_limitLearnCntAction_t *pAction); + +/* Function Name: + * dal_rtl8367c_l2_limitSystemLearningCntPortMask_set + * Description: + * Configure system auto learn portmask + * Input: + * pPortmask - Port Mask + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Invalid port mask. + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367c_l2_limitSystemLearningCntPortMask_set(rtk_portmask_t *pPortmask); + +/* Function Name: + * dal_rtl8367c_l2_limitSystemLearningCntPortMask_get + * Description: + * get system auto learn portmask + * Input: + * None + * Output: + * pPortmask - Port Mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Null pointer. + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367c_l2_limitSystemLearningCntPortMask_get(rtk_portmask_t *pPortmask); + +/* Function Name: + * dal_rtl8367c_l2_learningCnt_get + * Description: + * Get per-Port current auto learning number + * Input: + * port - Port id. + * Output: + * pMac_cnt - ASIC auto learning entries number + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get per-port ASIC auto learning number + */ +extern rtk_api_ret_t dal_rtl8367c_l2_learningCnt_get(rtk_port_t port, rtk_mac_cnt_t *pMac_cnt); + +/* Function Name: + * dal_rtl8367c_l2_floodPortMask_set + * Description: + * Set flooding portmask + * Input: + * type - flooding type. + * pFlood_portmask - flooding porkmask + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Invalid portmask. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can set the flooding mask. + * The flooding type is as following: + * - FLOOD_UNKNOWNDA + * - FLOOD_UNKNOWNMC + * - FLOOD_BC + */ +extern rtk_api_ret_t dal_rtl8367c_l2_floodPortMask_set(rtk_l2_flood_type_t floood_type, rtk_portmask_t *pFlood_portmask); + +/* Function Name: + * dal_rtl8367c_l2_floodPortMask_get + * Description: + * Get flooding portmask + * Input: + * type - flooding type. + * Output: + * pFlood_portmask - flooding porkmask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can get the flooding mask. + * The flooding type is as following: + * - FLOOD_UNKNOWNDA + * - FLOOD_UNKNOWNMC + * - FLOOD_BC + */ +extern rtk_api_ret_t dal_rtl8367c_l2_floodPortMask_get(rtk_l2_flood_type_t floood_type, rtk_portmask_t *pFlood_portmask); + +/* Function Name: + * dal_rtl8367c_l2_localPktPermit_set + * Description: + * Set permittion of frames if source port and destination port are the same. + * Input: + * port - Port id. + * permit - permittion status + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid permit value. + * Note: + * This API is setted to permit frame if its source port is equal to destination port. + */ +extern rtk_api_ret_t dal_rtl8367c_l2_localPktPermit_set(rtk_port_t port, rtk_enable_t permit); + +/* Function Name: + * dal_rtl8367c_l2_localPktPermit_get + * Description: + * Get permittion of frames if source port and destination port are the same. + * Input: + * port - Port id. + * Output: + * pPermit - permittion status + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API is to get permittion status for frames if its source port is equal to destination port. + */ +extern rtk_api_ret_t dal_rtl8367c_l2_localPktPermit_get(rtk_port_t port, rtk_enable_t *pPermit); + +/* Function Name: + * dal_rtl8367c_l2_aging_set + * Description: + * Set LUT agging out speed + * Input: + * aging_time - Agging out time. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - input out of range. + * Note: + * The API can set LUT agging out period for each entry and the range is from 14s to 800s. + */ +extern rtk_api_ret_t dal_rtl8367c_l2_aging_set(rtk_l2_age_time_t aging_time); + +/* Function Name: + * dal_rtl8367c_l2_aging_get + * Description: + * Get LUT agging out time + * Input: + * None + * Output: + * pEnable - Aging status + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get LUT agging out period for each entry. + */ +extern rtk_api_ret_t dal_rtl8367c_l2_aging_get(rtk_l2_age_time_t *pAging_time); + +/* Function Name: + * dal_rtl8367c_l2_ipMcastAddrLookup_set + * Description: + * Set Lut IP multicast lookup function + * Input: + * type - Lookup type for IPMC packet. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API can work with rtk_l2_ipMcastAddrLookupException_add. + * If users set the lookup type to DIP, the group in exception table + * will be lookup by DIP+SIP + * If users set the lookup type to DIP+SIP, the group in exception table + * will be lookup by only DIP + */ +extern rtk_api_ret_t dal_rtl8367c_l2_ipMcastAddrLookup_set(rtk_l2_ipmc_lookup_type_t type); + +/* Function Name: + * dal_rtl8367c_l2_ipMcastAddrLookup_get + * Description: + * Get Lut IP multicast lookup function + * Input: + * None. + * Output: + * pType - Lookup type for IPMC packet. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * None. + */ +extern rtk_api_ret_t dal_rtl8367c_l2_ipMcastAddrLookup_get(rtk_l2_ipmc_lookup_type_t *pType); + +/* Function Name: + * dal_rtl8367c_l2_ipMcastForwardRouterPort_set + * Description: + * Set IPMC packet forward to rounter port also or not + * Input: + * enabled - 1: Inlcude router port, 0, exclude router port + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367c_l2_ipMcastForwardRouterPort_set(rtk_enable_t enabled); + +/* Function Name: + * dal_rtl8367c_l2_ipMcastForwardRouterPort_get + * Description: + * Get IPMC packet forward to rounter port also or not + * Input: + * None. + * Output: + * pEnabled - 1: Inlcude router port, 0, exclude router port + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367c_l2_ipMcastForwardRouterPort_get(rtk_enable_t *pEnabled); + +/* Function Name: + * dal_rtl8367c_l2_ipMcastGroupEntry_add + * Description: + * Add an IP Multicast entry to group table + * Input: + * ip_addr - IP address + * vid - VLAN ID + * pPortmask - portmask + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_TBL_FULL - Table Full + * Note: + * Add an entry to IP Multicast Group table. + */ +extern rtk_api_ret_t dal_rtl8367c_l2_ipMcastGroupEntry_add(ipaddr_t ip_addr, rtk_uint32 vid, rtk_portmask_t *pPortmask); + +/* Function Name: + * dal_rtl8367c_l2_ipMcastGroupEntry_del + * Description: + * Delete an entry from IP Multicast group table + * Input: + * ip_addr - IP address + * vid - VLAN ID + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_TBL_FULL - Table Full + * Note: + * Delete an entry from IP Multicast group table. + */ +extern rtk_api_ret_t dal_rtl8367c_l2_ipMcastGroupEntry_del(ipaddr_t ip_addr, rtk_uint32 vid); + +/* Function Name: + * dal_rtl8367c_l2_ipMcastGroupEntry_get + * Description: + * get an entry from IP Multicast group table + * Input: + * ip_addr - IP address + * vid - VLAN ID + * Output: + * pPortmask - member port mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_TBL_FULL - Table Full + * Note: + * Delete an entry from IP Multicast group table. + */ +extern rtk_api_ret_t dal_rtl8367c_l2_ipMcastGroupEntry_get(ipaddr_t ip_addr, rtk_uint32 vid, rtk_portmask_t *pPortmask); + +/* Function Name: + * dal_rtl8367c_l2_entry_get + * Description: + * Get LUT unicast entry. + * Input: + * pL2_entry - Index field in the structure. + * Output: + * pL2_entry - other fields such as MAC, port, age... + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_EMPTY_ENTRY - Empty LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API is used to get address by index from 0~2111. + */ +extern rtk_api_ret_t dal_rtl8367c_l2_entry_get(rtk_l2_addr_table_t *pL2_entry); + + +#endif /* __DAL_RTL8367C_L2_H__ */ + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_leaky.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_leaky.c new file mode 100644 index 00000000..29d88622 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_leaky.c @@ -0,0 +1,593 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8367C + * Feature : Here is a list of all functions and variables in Leaky module. + * + */ + +#include +#include +#include +#include + +#include +#include +#include +#include + + +/* Function Name: + * dal_rtl8367c_leaky_vlan_set + * Description: + * Set VLAN leaky. + * Input: + * type - Packet type for VLAN leaky. + * enable - Leaky status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_ENABLE - Invalid enable input + * Note: + * This API can set VLAN leaky for RMA ,IGMP/MLD, CDP, CSSTP, and LLDP packets. + * The leaky frame types are as following: + * - LEAKY_BRG_GROUP, + * - LEAKY_FD_PAUSE, + * - LEAKY_SP_MCAST, + * - LEAKY_1X_PAE, + * - LEAKY_UNDEF_BRG_04, + * - LEAKY_UNDEF_BRG_05, + * - LEAKY_UNDEF_BRG_06, + * - LEAKY_UNDEF_BRG_07, + * - LEAKY_PROVIDER_BRIDGE_GROUP_ADDRESS, + * - LEAKY_UNDEF_BRG_09, + * - LEAKY_UNDEF_BRG_0A, + * - LEAKY_UNDEF_BRG_0B, + * - LEAKY_UNDEF_BRG_0C, + * - LEAKY_PROVIDER_BRIDGE_GVRP_ADDRESS, + * - LEAKY_8021AB, + * - LEAKY_UNDEF_BRG_0F, + * - LEAKY_BRG_MNGEMENT, + * - LEAKY_UNDEFINED_11, + * - LEAKY_UNDEFINED_12, + * - LEAKY_UNDEFINED_13, + * - LEAKY_UNDEFINED_14, + * - LEAKY_UNDEFINED_15, + * - LEAKY_UNDEFINED_16, + * - LEAKY_UNDEFINED_17, + * - LEAKY_UNDEFINED_18, + * - LEAKY_UNDEFINED_19, + * - LEAKY_UNDEFINED_1A, + * - LEAKY_UNDEFINED_1B, + * - LEAKY_UNDEFINED_1C, + * - LEAKY_UNDEFINED_1D, + * - LEAKY_UNDEFINED_1E, + * - LEAKY_UNDEFINED_1F, + * - LEAKY_GMRP, + * - LEAKY_GVRP, + * - LEAKY_UNDEF_GARP_22, + * - LEAKY_UNDEF_GARP_23, + * - LEAKY_UNDEF_GARP_24, + * - LEAKY_UNDEF_GARP_25, + * - LEAKY_UNDEF_GARP_26, + * - LEAKY_UNDEF_GARP_27, + * - LEAKY_UNDEF_GARP_28, + * - LEAKY_UNDEF_GARP_29, + * - LEAKY_UNDEF_GARP_2A, + * - LEAKY_UNDEF_GARP_2B, + * - LEAKY_UNDEF_GARP_2C, + * - LEAKY_UNDEF_GARP_2D, + * - LEAKY_UNDEF_GARP_2E, + * - LEAKY_UNDEF_GARP_2F, + * - LEAKY_IGMP, + * - LEAKY_IPMULTICAST. + * - LEAKY_CDP, + * - LEAKY_CSSTP, + * - LEAKY_LLDP. + */ +rtk_api_ret_t dal_rtl8367c_leaky_vlan_set(rtk_leaky_type_t type, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + rtk_uint32 port; + rtl8367c_rma_t rmacfg; + rtk_uint32 tmp; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (type >= LEAKY_END) + return RT_ERR_INPUT; + + if (enable >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if (type >= 0 && type <= LEAKY_UNDEF_GARP_2F) + { + if ((retVal = rtl8367c_getAsicRma(type, &rmacfg)) != RT_ERR_OK) + return retVal; + + rmacfg.vlan_leaky = enable; + + if ((retVal = rtl8367c_setAsicRma(type, &rmacfg)) != RT_ERR_OK) + return retVal; + } + else if (LEAKY_IPMULTICAST == type) + { + for (port = 0; port <= RTK_PORT_ID_MAX; port++) + { + if ((retVal = rtl8367c_setAsicIpMulticastVlanLeaky(port,enable)) != RT_ERR_OK) + return retVal; + } + } + else if (LEAKY_IGMP == type) + { + if ((retVal = rtl8367c_setAsicIGMPVLANLeaky(enable)) != RT_ERR_OK) + return retVal; + } + else if (LEAKY_CDP == type) + { + if ((retVal = rtl8367c_getAsicRmaCdp(&rmacfg)) != RT_ERR_OK) + return retVal; + + rmacfg.vlan_leaky = enable; + + if ((retVal = rtl8367c_setAsicRmaCdp(&rmacfg)) != RT_ERR_OK) + return retVal; + } + else if (LEAKY_CSSTP == type) + { + if ((retVal = rtl8367c_getAsicRmaCsstp(&rmacfg)) != RT_ERR_OK) + return retVal; + + rmacfg.vlan_leaky = enable; + + if ((retVal = rtl8367c_setAsicRmaCsstp(&rmacfg)) != RT_ERR_OK) + return retVal; + } + else if (LEAKY_LLDP == type) + { + if ((retVal = rtl8367c_getAsicRmaLldp(&tmp,&rmacfg)) != RT_ERR_OK) + return retVal; + + rmacfg.vlan_leaky = enable; + + if ((retVal = rtl8367c_setAsicRmaLldp(tmp, &rmacfg)) != RT_ERR_OK) + return retVal; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_leaky_vlan_get + * Description: + * Get VLAN leaky. + * Input: + * type - Packet type for VLAN leaky. + * Output: + * pEnable - Leaky status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can get VLAN leaky status for RMA ,IGMP/MLD, CDP, CSSTP, and LLDP packets. + * The leaky frame types are as following: + * - LEAKY_BRG_GROUP, + * - LEAKY_FD_PAUSE, + * - LEAKY_SP_MCAST, + * - LEAKY_1X_PAE, + * - LEAKY_UNDEF_BRG_04, + * - LEAKY_UNDEF_BRG_05, + * - LEAKY_UNDEF_BRG_06, + * - LEAKY_UNDEF_BRG_07, + * - LEAKY_PROVIDER_BRIDGE_GROUP_ADDRESS, + * - LEAKY_UNDEF_BRG_09, + * - LEAKY_UNDEF_BRG_0A, + * - LEAKY_UNDEF_BRG_0B, + * - LEAKY_UNDEF_BRG_0C, + * - LEAKY_PROVIDER_BRIDGE_GVRP_ADDRESS, + * - LEAKY_8021AB, + * - LEAKY_UNDEF_BRG_0F, + * - LEAKY_BRG_MNGEMENT, + * - LEAKY_UNDEFINED_11, + * - LEAKY_UNDEFINED_12, + * - LEAKY_UNDEFINED_13, + * - LEAKY_UNDEFINED_14, + * - LEAKY_UNDEFINED_15, + * - LEAKY_UNDEFINED_16, + * - LEAKY_UNDEFINED_17, + * - LEAKY_UNDEFINED_18, + * - LEAKY_UNDEFINED_19, + * - LEAKY_UNDEFINED_1A, + * - LEAKY_UNDEFINED_1B, + * - LEAKY_UNDEFINED_1C, + * - LEAKY_UNDEFINED_1D, + * - LEAKY_UNDEFINED_1E, + * - LEAKY_UNDEFINED_1F, + * - LEAKY_GMRP, + * - LEAKY_GVRP, + * - LEAKY_UNDEF_GARP_22, + * - LEAKY_UNDEF_GARP_23, + * - LEAKY_UNDEF_GARP_24, + * - LEAKY_UNDEF_GARP_25, + * - LEAKY_UNDEF_GARP_26, + * - LEAKY_UNDEF_GARP_27, + * - LEAKY_UNDEF_GARP_28, + * - LEAKY_UNDEF_GARP_29, + * - LEAKY_UNDEF_GARP_2A, + * - LEAKY_UNDEF_GARP_2B, + * - LEAKY_UNDEF_GARP_2C, + * - LEAKY_UNDEF_GARP_2D, + * - LEAKY_UNDEF_GARP_2E, + * - LEAKY_UNDEF_GARP_2F, + * - LEAKY_IGMP, + * - LEAKY_IPMULTICAST. + * - LEAKY_CDP, + * - LEAKY_CSSTP, + * - LEAKY_LLDP. + */ +rtk_api_ret_t dal_rtl8367c_leaky_vlan_get(rtk_leaky_type_t type, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + rtk_uint32 port,tmp; + rtl8367c_rma_t rmacfg; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (type >= LEAKY_END) + return RT_ERR_INPUT; + + if(NULL == pEnable) + return RT_ERR_NULL_POINTER; + + if (type >= 0 && type <= LEAKY_UNDEF_GARP_2F) + { + if ((retVal = rtl8367c_getAsicRma(type, &rmacfg)) != RT_ERR_OK) + return retVal; + + *pEnable = rmacfg.vlan_leaky; + + } + else if (LEAKY_IPMULTICAST == type) + { + for (port = 0; port <= RTK_PORT_ID_MAX; port++) + { + if ((retVal = rtl8367c_getAsicIpMulticastVlanLeaky(port, &tmp)) != RT_ERR_OK) + return retVal; + if (port>0&&(tmp!=*pEnable)) + return RT_ERR_FAILED; + *pEnable = tmp; + } + } + else if (LEAKY_IGMP == type) + { + if ((retVal = rtl8367c_getAsicIGMPVLANLeaky(&tmp)) != RT_ERR_OK) + return retVal; + + *pEnable = tmp; + } + else if (LEAKY_CDP == type) + { + if ((retVal = rtl8367c_getAsicRmaCdp(&rmacfg)) != RT_ERR_OK) + return retVal; + + *pEnable = rmacfg.vlan_leaky; + } + else if (LEAKY_CSSTP == type) + { + if ((retVal = rtl8367c_getAsicRmaCsstp(&rmacfg)) != RT_ERR_OK) + return retVal; + + *pEnable = rmacfg.vlan_leaky; + } + else if (LEAKY_LLDP == type) + { + if ((retVal = rtl8367c_getAsicRmaLldp(&tmp, &rmacfg)) != RT_ERR_OK) + return retVal; + + *pEnable = rmacfg.vlan_leaky; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_leaky_portIsolation_set + * Description: + * Set port isolation leaky. + * Input: + * type - Packet type for port isolation leaky. + * enable - Leaky status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_ENABLE - Invalid enable input + * Note: + * This API can set port isolation leaky for RMA ,IGMP/MLD, CDP, CSSTP, and LLDP packets. + * The leaky frame types are as following: + * - LEAKY_BRG_GROUP, + * - LEAKY_FD_PAUSE, + * - LEAKY_SP_MCAST, + * - LEAKY_1X_PAE, + * - LEAKY_UNDEF_BRG_04, + * - LEAKY_UNDEF_BRG_05, + * - LEAKY_UNDEF_BRG_06, + * - LEAKY_UNDEF_BRG_07, + * - LEAKY_PROVIDER_BRIDGE_GROUP_ADDRESS, + * - LEAKY_UNDEF_BRG_09, + * - LEAKY_UNDEF_BRG_0A, + * - LEAKY_UNDEF_BRG_0B, + * - LEAKY_UNDEF_BRG_0C, + * - LEAKY_PROVIDER_BRIDGE_GVRP_ADDRESS, + * - LEAKY_8021AB, + * - LEAKY_UNDEF_BRG_0F, + * - LEAKY_BRG_MNGEMENT, + * - LEAKY_UNDEFINED_11, + * - LEAKY_UNDEFINED_12, + * - LEAKY_UNDEFINED_13, + * - LEAKY_UNDEFINED_14, + * - LEAKY_UNDEFINED_15, + * - LEAKY_UNDEFINED_16, + * - LEAKY_UNDEFINED_17, + * - LEAKY_UNDEFINED_18, + * - LEAKY_UNDEFINED_19, + * - LEAKY_UNDEFINED_1A, + * - LEAKY_UNDEFINED_1B, + * - LEAKY_UNDEFINED_1C, + * - LEAKY_UNDEFINED_1D, + * - LEAKY_UNDEFINED_1E, + * - LEAKY_UNDEFINED_1F, + * - LEAKY_GMRP, + * - LEAKY_GVRP, + * - LEAKY_UNDEF_GARP_22, + * - LEAKY_UNDEF_GARP_23, + * - LEAKY_UNDEF_GARP_24, + * - LEAKY_UNDEF_GARP_25, + * - LEAKY_UNDEF_GARP_26, + * - LEAKY_UNDEF_GARP_27, + * - LEAKY_UNDEF_GARP_28, + * - LEAKY_UNDEF_GARP_29, + * - LEAKY_UNDEF_GARP_2A, + * - LEAKY_UNDEF_GARP_2B, + * - LEAKY_UNDEF_GARP_2C, + * - LEAKY_UNDEF_GARP_2D, + * - LEAKY_UNDEF_GARP_2E, + * - LEAKY_UNDEF_GARP_2F, + * - LEAKY_IGMP, + * - LEAKY_IPMULTICAST. + * - LEAKY_CDP, + * - LEAKY_CSSTP, + * - LEAKY_LLDP. + */ +rtk_api_ret_t dal_rtl8367c_leaky_portIsolation_set(rtk_leaky_type_t type, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + rtk_uint32 port; + rtl8367c_rma_t rmacfg; + rtk_uint32 tmp; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (type >= LEAKY_END) + return RT_ERR_INPUT; + + if (enable >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if (type >= 0 && type <= LEAKY_UNDEF_GARP_2F) + { + if ((retVal = rtl8367c_getAsicRma(type, &rmacfg)) != RT_ERR_OK) + return retVal; + + rmacfg.portiso_leaky = enable; + + if ((retVal = rtl8367c_setAsicRma(type, &rmacfg)) != RT_ERR_OK) + return retVal; + } + else if (LEAKY_IPMULTICAST == type) + { + for (port = 0; port < RTK_MAX_NUM_OF_PORT; port++) + { + if ((retVal = rtl8367c_setAsicIpMulticastPortIsoLeaky(port,enable)) != RT_ERR_OK) + return retVal; + } + } + else if (LEAKY_IGMP == type) + { + if ((retVal = rtl8367c_setAsicIGMPIsoLeaky(enable)) != RT_ERR_OK) + return retVal; + } + else if (LEAKY_CDP == type) + { + if ((retVal = rtl8367c_getAsicRmaCdp(&rmacfg)) != RT_ERR_OK) + return retVal; + + rmacfg.portiso_leaky = enable; + + if ((retVal = rtl8367c_setAsicRmaCdp(&rmacfg)) != RT_ERR_OK) + return retVal; + } + else if (LEAKY_CSSTP == type) + { + if ((retVal = rtl8367c_getAsicRmaCsstp(&rmacfg)) != RT_ERR_OK) + return retVal; + + rmacfg.portiso_leaky = enable; + + if ((retVal = rtl8367c_setAsicRmaCsstp(&rmacfg)) != RT_ERR_OK) + return retVal; + } + else if (LEAKY_LLDP == type) + { + if ((retVal = rtl8367c_getAsicRmaLldp(&tmp, &rmacfg)) != RT_ERR_OK) + return retVal; + + rmacfg.portiso_leaky = enable; + + if ((retVal = rtl8367c_setAsicRmaLldp(tmp, &rmacfg)) != RT_ERR_OK) + return retVal; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_leaky_portIsolation_get + * Description: + * Get port isolation leaky. + * Input: + * type - Packet type for port isolation leaky. + * Output: + * pEnable - Leaky status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can get port isolation leaky status for RMA ,IGMP/MLD, CDP, CSSTP, and LLDP packets. + * The leaky frame types are as following: + * - LEAKY_BRG_GROUP, + * - LEAKY_FD_PAUSE, + * - LEAKY_SP_MCAST, + * - LEAKY_1X_PAE, + * - LEAKY_UNDEF_BRG_04, + * - LEAKY_UNDEF_BRG_05, + * - LEAKY_UNDEF_BRG_06, + * - LEAKY_UNDEF_BRG_07, + * - LEAKY_PROVIDER_BRIDGE_GROUP_ADDRESS, + * - LEAKY_UNDEF_BRG_09, + * - LEAKY_UNDEF_BRG_0A, + * - LEAKY_UNDEF_BRG_0B, + * - LEAKY_UNDEF_BRG_0C, + * - LEAKY_PROVIDER_BRIDGE_GVRP_ADDRESS, + * - LEAKY_8021AB, + * - LEAKY_UNDEF_BRG_0F, + * - LEAKY_BRG_MNGEMENT, + * - LEAKY_UNDEFINED_11, + * - LEAKY_UNDEFINED_12, + * - LEAKY_UNDEFINED_13, + * - LEAKY_UNDEFINED_14, + * - LEAKY_UNDEFINED_15, + * - LEAKY_UNDEFINED_16, + * - LEAKY_UNDEFINED_17, + * - LEAKY_UNDEFINED_18, + * - LEAKY_UNDEFINED_19, + * - LEAKY_UNDEFINED_1A, + * - LEAKY_UNDEFINED_1B, + * - LEAKY_UNDEFINED_1C, + * - LEAKY_UNDEFINED_1D, + * - LEAKY_UNDEFINED_1E, + * - LEAKY_UNDEFINED_1F, + * - LEAKY_GMRP, + * - LEAKY_GVRP, + * - LEAKY_UNDEF_GARP_22, + * - LEAKY_UNDEF_GARP_23, + * - LEAKY_UNDEF_GARP_24, + * - LEAKY_UNDEF_GARP_25, + * - LEAKY_UNDEF_GARP_26, + * - LEAKY_UNDEF_GARP_27, + * - LEAKY_UNDEF_GARP_28, + * - LEAKY_UNDEF_GARP_29, + * - LEAKY_UNDEF_GARP_2A, + * - LEAKY_UNDEF_GARP_2B, + * - LEAKY_UNDEF_GARP_2C, + * - LEAKY_UNDEF_GARP_2D, + * - LEAKY_UNDEF_GARP_2E, + * - LEAKY_UNDEF_GARP_2F, + * - LEAKY_IGMP, + * - LEAKY_IPMULTICAST. + * - LEAKY_CDP, + * - LEAKY_CSSTP, + * - LEAKY_LLDP. + */ +rtk_api_ret_t dal_rtl8367c_leaky_portIsolation_get(rtk_leaky_type_t type, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + rtk_uint32 port, tmp; + rtl8367c_rma_t rmacfg; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (type >= LEAKY_END) + return RT_ERR_INPUT; + + if(NULL == pEnable) + return RT_ERR_NULL_POINTER; + + if (type >= 0 && type <= LEAKY_UNDEF_GARP_2F) + { + if ((retVal = rtl8367c_getAsicRma(type, &rmacfg)) != RT_ERR_OK) + return retVal; + + *pEnable = rmacfg.portiso_leaky; + + } + else if (LEAKY_IPMULTICAST == type) + { + for (port = 0; port < RTK_MAX_NUM_OF_PORT; port++) + { + if ((retVal = rtl8367c_getAsicIpMulticastPortIsoLeaky(port, &tmp)) != RT_ERR_OK) + return retVal; + if (port > 0 &&(tmp != *pEnable)) + return RT_ERR_FAILED; + *pEnable = tmp; + } + } + else if (LEAKY_IGMP == type) + { + if ((retVal = rtl8367c_getAsicIGMPIsoLeaky(&tmp)) != RT_ERR_OK) + return retVal; + + *pEnable = tmp; + } + else if (LEAKY_CDP == type) + { + if ((retVal = rtl8367c_getAsicRmaCdp(&rmacfg)) != RT_ERR_OK) + return retVal; + + *pEnable = rmacfg.portiso_leaky; + } + else if (LEAKY_CSSTP == type) + { + if ((retVal = rtl8367c_getAsicRmaCsstp(&rmacfg)) != RT_ERR_OK) + return retVal; + + *pEnable = rmacfg.portiso_leaky; + } + else if (LEAKY_LLDP == type) + { + if ((retVal = rtl8367c_getAsicRmaLldp(&tmp, &rmacfg)) != RT_ERR_OK) + return retVal; + + *pEnable = rmacfg.portiso_leaky; + } + + + return RT_ERR_OK; +} + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_leaky.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_leaky.h new file mode 100644 index 00000000..91054452 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_leaky.h @@ -0,0 +1,316 @@ + /* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8367/RTL8367C switch high-level API + * + * Feature : The file includes Leaky module high-layer API defination + * + */ + +#ifndef __DAL_RTL8367C_API_LEAKY_H__ +#define __DAL_RTL8367C_API_LEAKY_H__ + +#include + +/* Function Name: + * dal_rtl8367c_leaky_vlan_set + * Description: + * Set VLAN leaky. + * Input: + * type - Packet type for VLAN leaky. + * enable - Leaky status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_ENABLE - Invalid enable input + * Note: + * This API can set VLAN leaky for RMA ,IGMP/MLD, CDP, CSSTP, and LLDP packets. + * The leaky frame types are as following: + * - LEAKY_BRG_GROUP, + * - LEAKY_FD_PAUSE, + * - LEAKY_SP_MCAST, + * - LEAKY_1X_PAE, + * - LEAKY_UNDEF_BRG_04, + * - LEAKY_UNDEF_BRG_05, + * - LEAKY_UNDEF_BRG_06, + * - LEAKY_UNDEF_BRG_07, + * - LEAKY_PROVIDER_BRIDGE_GROUP_ADDRESS, + * - LEAKY_UNDEF_BRG_09, + * - LEAKY_UNDEF_BRG_0A, + * - LEAKY_UNDEF_BRG_0B, + * - LEAKY_UNDEF_BRG_0C, + * - LEAKY_PROVIDER_BRIDGE_GVRP_ADDRESS, + * - LEAKY_8021AB, + * - LEAKY_UNDEF_BRG_0F, + * - LEAKY_BRG_MNGEMENT, + * - LEAKY_UNDEFINED_11, + * - LEAKY_UNDEFINED_12, + * - LEAKY_UNDEFINED_13, + * - LEAKY_UNDEFINED_14, + * - LEAKY_UNDEFINED_15, + * - LEAKY_UNDEFINED_16, + * - LEAKY_UNDEFINED_17, + * - LEAKY_UNDEFINED_18, + * - LEAKY_UNDEFINED_19, + * - LEAKY_UNDEFINED_1A, + * - LEAKY_UNDEFINED_1B, + * - LEAKY_UNDEFINED_1C, + * - LEAKY_UNDEFINED_1D, + * - LEAKY_UNDEFINED_1E, + * - LEAKY_UNDEFINED_1F, + * - LEAKY_GMRP, + * - LEAKY_GVRP, + * - LEAKY_UNDEF_GARP_22, + * - LEAKY_UNDEF_GARP_23, + * - LEAKY_UNDEF_GARP_24, + * - LEAKY_UNDEF_GARP_25, + * - LEAKY_UNDEF_GARP_26, + * - LEAKY_UNDEF_GARP_27, + * - LEAKY_UNDEF_GARP_28, + * - LEAKY_UNDEF_GARP_29, + * - LEAKY_UNDEF_GARP_2A, + * - LEAKY_UNDEF_GARP_2B, + * - LEAKY_UNDEF_GARP_2C, + * - LEAKY_UNDEF_GARP_2D, + * - LEAKY_UNDEF_GARP_2E, + * - LEAKY_UNDEF_GARP_2F, + * - LEAKY_IGMP, + * - LEAKY_IPMULTICAST. + * - LEAKY_CDP, + * - LEAKY_CSSTP, + * - LEAKY_LLDP. + */ +extern rtk_api_ret_t dal_rtl8367c_leaky_vlan_set(rtk_leaky_type_t type, rtk_enable_t enable); + +/* Function Name: + * dal_rtl8367c_leaky_vlan_get + * Description: + * Get VLAN leaky. + * Input: + * type - Packet type for VLAN leaky. + * Output: + * pEnable - Leaky status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can get VLAN leaky status for RMA ,IGMP/MLD, CDP, CSSTP, and LLDP packets. + * The leaky frame types are as following: + * - LEAKY_BRG_GROUP, + * - LEAKY_FD_PAUSE, + * - LEAKY_SP_MCAST, + * - LEAKY_1X_PAE, + * - LEAKY_UNDEF_BRG_04, + * - LEAKY_UNDEF_BRG_05, + * - LEAKY_UNDEF_BRG_06, + * - LEAKY_UNDEF_BRG_07, + * - LEAKY_PROVIDER_BRIDGE_GROUP_ADDRESS, + * - LEAKY_UNDEF_BRG_09, + * - LEAKY_UNDEF_BRG_0A, + * - LEAKY_UNDEF_BRG_0B, + * - LEAKY_UNDEF_BRG_0C, + * - LEAKY_PROVIDER_BRIDGE_GVRP_ADDRESS, + * - LEAKY_8021AB, + * - LEAKY_UNDEF_BRG_0F, + * - LEAKY_BRG_MNGEMENT, + * - LEAKY_UNDEFINED_11, + * - LEAKY_UNDEFINED_12, + * - LEAKY_UNDEFINED_13, + * - LEAKY_UNDEFINED_14, + * - LEAKY_UNDEFINED_15, + * - LEAKY_UNDEFINED_16, + * - LEAKY_UNDEFINED_17, + * - LEAKY_UNDEFINED_18, + * - LEAKY_UNDEFINED_19, + * - LEAKY_UNDEFINED_1A, + * - LEAKY_UNDEFINED_1B, + * - LEAKY_UNDEFINED_1C, + * - LEAKY_UNDEFINED_1D, + * - LEAKY_UNDEFINED_1E, + * - LEAKY_UNDEFINED_1F, + * - LEAKY_GMRP, + * - LEAKY_GVRP, + * - LEAKY_UNDEF_GARP_22, + * - LEAKY_UNDEF_GARP_23, + * - LEAKY_UNDEF_GARP_24, + * - LEAKY_UNDEF_GARP_25, + * - LEAKY_UNDEF_GARP_26, + * - LEAKY_UNDEF_GARP_27, + * - LEAKY_UNDEF_GARP_28, + * - LEAKY_UNDEF_GARP_29, + * - LEAKY_UNDEF_GARP_2A, + * - LEAKY_UNDEF_GARP_2B, + * - LEAKY_UNDEF_GARP_2C, + * - LEAKY_UNDEF_GARP_2D, + * - LEAKY_UNDEF_GARP_2E, + * - LEAKY_UNDEF_GARP_2F, + * - LEAKY_IGMP, + * - LEAKY_IPMULTICAST. + * - LEAKY_CDP, + * - LEAKY_CSSTP, + * - LEAKY_LLDP. + */ +extern rtk_api_ret_t dal_rtl8367c_leaky_vlan_get(rtk_leaky_type_t type, rtk_enable_t *pEnable); + +/* Function Name: + * dal_rtl8367c_leaky_portIsolation_set + * Description: + * Set port isolation leaky. + * Input: + * type - Packet type for port isolation leaky. + * enable - Leaky status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_ENABLE - Invalid enable input + * Note: + * This API can set port isolation leaky for RMA ,IGMP/MLD, CDP, CSSTP, and LLDP packets. + * The leaky frame types are as following: + * - LEAKY_BRG_GROUP, + * - LEAKY_FD_PAUSE, + * - LEAKY_SP_MCAST, + * - LEAKY_1X_PAE, + * - LEAKY_UNDEF_BRG_04, + * - LEAKY_UNDEF_BRG_05, + * - LEAKY_UNDEF_BRG_06, + * - LEAKY_UNDEF_BRG_07, + * - LEAKY_PROVIDER_BRIDGE_GROUP_ADDRESS, + * - LEAKY_UNDEF_BRG_09, + * - LEAKY_UNDEF_BRG_0A, + * - LEAKY_UNDEF_BRG_0B, + * - LEAKY_UNDEF_BRG_0C, + * - LEAKY_PROVIDER_BRIDGE_GVRP_ADDRESS, + * - LEAKY_8021AB, + * - LEAKY_UNDEF_BRG_0F, + * - LEAKY_BRG_MNGEMENT, + * - LEAKY_UNDEFINED_11, + * - LEAKY_UNDEFINED_12, + * - LEAKY_UNDEFINED_13, + * - LEAKY_UNDEFINED_14, + * - LEAKY_UNDEFINED_15, + * - LEAKY_UNDEFINED_16, + * - LEAKY_UNDEFINED_17, + * - LEAKY_UNDEFINED_18, + * - LEAKY_UNDEFINED_19, + * - LEAKY_UNDEFINED_1A, + * - LEAKY_UNDEFINED_1B, + * - LEAKY_UNDEFINED_1C, + * - LEAKY_UNDEFINED_1D, + * - LEAKY_UNDEFINED_1E, + * - LEAKY_UNDEFINED_1F, + * - LEAKY_GMRP, + * - LEAKY_GVRP, + * - LEAKY_UNDEF_GARP_22, + * - LEAKY_UNDEF_GARP_23, + * - LEAKY_UNDEF_GARP_24, + * - LEAKY_UNDEF_GARP_25, + * - LEAKY_UNDEF_GARP_26, + * - LEAKY_UNDEF_GARP_27, + * - LEAKY_UNDEF_GARP_28, + * - LEAKY_UNDEF_GARP_29, + * - LEAKY_UNDEF_GARP_2A, + * - LEAKY_UNDEF_GARP_2B, + * - LEAKY_UNDEF_GARP_2C, + * - LEAKY_UNDEF_GARP_2D, + * - LEAKY_UNDEF_GARP_2E, + * - LEAKY_UNDEF_GARP_2F, + * - LEAKY_IGMP, + * - LEAKY_IPMULTICAST. + * - LEAKY_CDP, + * - LEAKY_CSSTP, + * - LEAKY_LLDP. + */ +extern rtk_api_ret_t dal_rtl8367c_leaky_portIsolation_set(rtk_leaky_type_t type, rtk_enable_t enable); + +/* Function Name: + * dal_rtl8367c_leaky_portIsolation_get + * Description: + * Get port isolation leaky. + * Input: + * type - Packet type for port isolation leaky. + * Output: + * pEnable - Leaky status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can get port isolation leaky status for RMA ,IGMP/MLD, CDP, CSSTP, and LLDP packets. + * The leaky frame types are as following: + * - LEAKY_BRG_GROUP, + * - LEAKY_FD_PAUSE, + * - LEAKY_SP_MCAST, + * - LEAKY_1X_PAE, + * - LEAKY_UNDEF_BRG_04, + * - LEAKY_UNDEF_BRG_05, + * - LEAKY_UNDEF_BRG_06, + * - LEAKY_UNDEF_BRG_07, + * - LEAKY_PROVIDER_BRIDGE_GROUP_ADDRESS, + * - LEAKY_UNDEF_BRG_09, + * - LEAKY_UNDEF_BRG_0A, + * - LEAKY_UNDEF_BRG_0B, + * - LEAKY_UNDEF_BRG_0C, + * - LEAKY_PROVIDER_BRIDGE_GVRP_ADDRESS, + * - LEAKY_8021AB, + * - LEAKY_UNDEF_BRG_0F, + * - LEAKY_BRG_MNGEMENT, + * - LEAKY_UNDEFINED_11, + * - LEAKY_UNDEFINED_12, + * - LEAKY_UNDEFINED_13, + * - LEAKY_UNDEFINED_14, + * - LEAKY_UNDEFINED_15, + * - LEAKY_UNDEFINED_16, + * - LEAKY_UNDEFINED_17, + * - LEAKY_UNDEFINED_18, + * - LEAKY_UNDEFINED_19, + * - LEAKY_UNDEFINED_1A, + * - LEAKY_UNDEFINED_1B, + * - LEAKY_UNDEFINED_1C, + * - LEAKY_UNDEFINED_1D, + * - LEAKY_UNDEFINED_1E, + * - LEAKY_UNDEFINED_1F, + * - LEAKY_GMRP, + * - LEAKY_GVRP, + * - LEAKY_UNDEF_GARP_22, + * - LEAKY_UNDEF_GARP_23, + * - LEAKY_UNDEF_GARP_24, + * - LEAKY_UNDEF_GARP_25, + * - LEAKY_UNDEF_GARP_26, + * - LEAKY_UNDEF_GARP_27, + * - LEAKY_UNDEF_GARP_28, + * - LEAKY_UNDEF_GARP_29, + * - LEAKY_UNDEF_GARP_2A, + * - LEAKY_UNDEF_GARP_2B, + * - LEAKY_UNDEF_GARP_2C, + * - LEAKY_UNDEF_GARP_2D, + * - LEAKY_UNDEF_GARP_2E, + * - LEAKY_UNDEF_GARP_2F, + * - LEAKY_IGMP, + * - LEAKY_IPMULTICAST. + * - LEAKY_CDP, + * - LEAKY_CSSTP, + * - LEAKY_LLDP. + */ +extern rtk_api_ret_t dal_rtl8367c_leaky_portIsolation_get(rtk_leaky_type_t type, rtk_enable_t *pEnable); + +#endif /* __DAL_RTL8367C_API_LEAKY_H__ */ + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_led.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_led.c new file mode 100644 index 00000000..0dbe34a1 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_led.c @@ -0,0 +1,808 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8367C + * Feature : Here is a list of all functions and variables in LED module. + * + */ + +#include +#include +#include +#include + +#include +#include + +/* Function Name: + * dal_rtl8367c_led_enable_set + * Description: + * Set Led enable congiuration + * Input: + * group - LED group id. + * pPortmask - LED enable port mask. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_MASK - Error portmask + * Note: + * The API can be used to enable LED per port per group. + */ +rtk_api_ret_t dal_rtl8367c_led_enable_set(rtk_led_group_t group, rtk_portmask_t *pPortmask) +{ + rtk_api_ret_t retVal; + rtk_uint32 pmask; + rtk_port_t port; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (group >= LED_GROUP_END) + return RT_ERR_INPUT; + + RTK_CHK_PORTMASK_VALID(pPortmask); + + RTK_PORTMASK_SCAN((*pPortmask), port) + { + if(rtk_switch_isCPUPort(port) == RT_ERR_OK) + return RT_ERR_PORT_MASK; + } + + if((retVal = rtk_switch_portmask_L2P_get(pPortmask, &pmask)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicLedGroupEnable(group, pmask)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_led_enable_get + * Description: + * Get Led enable congiuration + * Input: + * group - LED group id. + * Output: + * pPortmask - LED enable port mask. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can be used to get LED enable status. + */ +rtk_api_ret_t dal_rtl8367c_led_enable_get(rtk_led_group_t group, rtk_portmask_t *pPortmask) +{ + rtk_api_ret_t retVal; + rtk_uint32 pmask; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (group >= LED_GROUP_END) + return RT_ERR_INPUT; + + if ((retVal = rtl8367c_getAsicLedGroupEnable(group, &pmask)) != RT_ERR_OK) + return retVal; + + if((retVal = rtk_switch_portmask_P2L_get(pmask, pPortmask)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; + +} + +/* Function Name: + * dal_rtl8367c_led_operation_set + * Description: + * Set Led operation mode + * Input: + * mode - LED operation mode. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can set Led operation mode. + * The modes that can be set are as following: + * - LED_OP_SCAN, + * - LED_OP_PARALLEL, + * - LED_OP_SERIAL, + */ +rtk_api_ret_t dal_rtl8367c_led_operation_set(rtk_led_operation_t mode) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if ( mode >= LED_OP_END) + return RT_ERR_INPUT; + + switch (mode) + { + case LED_OP_PARALLEL: + regData = LEDOP_PARALLEL; + break; + case LED_OP_SERIAL: + regData = LEDOP_SERIAL; + break; + default: + return RT_ERR_CHIP_NOT_SUPPORTED; + break; + } + + if ((retVal = rtl8367c_setAsicLedOperationMode(regData)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_led_operation_get + * Description: + * Get Led operation mode + * Input: + * None + * Output: + * pMode - Support LED operation mode. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get Led operation mode. + * The modes that can be set are as following: + * - LED_OP_SCAN, + * - LED_OP_PARALLEL, + * - LED_OP_SERIAL, + */ +rtk_api_ret_t dal_rtl8367c_led_operation_get(rtk_led_operation_t *pMode) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pMode) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicLedOperationMode(®Data)) != RT_ERR_OK) + return retVal; + + if (regData == LEDOP_SERIAL) + *pMode = LED_OP_SERIAL; + else if (regData ==LEDOP_PARALLEL) + *pMode = LED_OP_PARALLEL; + else + return RT_ERR_FAILED; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_led_modeForce_set + * Description: + * Set Led group to congiuration force mode + * Input: + * port - port ID + * group - Support LED group id. + * mode - Support LED force mode. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Error Port ID + * Note: + * The API can force to one force mode. + * The force modes that can be set are as following: + * - LED_FORCE_NORMAL, + * - LED_FORCE_BLINK, + * - LED_FORCE_OFF, + * - LED_FORCE_ON. + */ +rtk_api_ret_t dal_rtl8367c_led_modeForce_set(rtk_port_t port, rtk_led_group_t group, rtk_led_force_mode_t mode) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + /* No LED for CPU port */ + if(rtk_switch_isCPUPort(port) == RT_ERR_OK) + return RT_ERR_PORT_ID; + + if (group >= LED_GROUP_END) + return RT_ERR_INPUT; + + if (mode >= LED_FORCE_END) + return RT_ERR_NOT_ALLOWED; + + if ((retVal = rtl8367c_setAsicForceLed(rtk_switch_port_L2P_get(port), group, mode)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_led_modeForce_get + * Description: + * Get Led group to congiuration force mode + * Input: + * port - port ID + * group - Support LED group id. + * pMode - Support LED force mode. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Error Port ID + * Note: + * The API can get forced Led group mode. + * The force modes that can be set are as following: + * - LED_FORCE_NORMAL, + * - LED_FORCE_BLINK, + * - LED_FORCE_OFF, + * - LED_FORCE_ON. + */ +rtk_api_ret_t dal_rtl8367c_led_modeForce_get(rtk_port_t port, rtk_led_group_t group, rtk_led_force_mode_t *pMode) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + /* No LED for CPU port */ + if(rtk_switch_isCPUPort(port) == RT_ERR_OK) + return RT_ERR_PORT_ID; + + if (group >= LED_GROUP_END) + return RT_ERR_INPUT; + + if (NULL == pMode) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicForceLed(rtk_switch_port_L2P_get(port), group, pMode)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_led_blinkRate_set + * Description: + * Set LED blinking rate + * Input: + * blinkRate - blinking rate. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API configure LED blinking rate: + * - LED_BLINKRATE_32MS + * - LED_BLINKRATE_64MS, + * - LED_BLINKRATE_128MS, + * - LED_BLINKRATE_256MS, + * - LED_BLINKRATE_512MS, + * - LED_BLINKRATE_1024MS, + * - LED_BLINKRATE_48MS, + * - LED_BLINKRATE_96MS, + */ +rtk_api_ret_t dal_rtl8367c_led_blinkRate_set(rtk_led_blink_rate_t blinkRate) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (blinkRate >= LED_BLINKRATE_END) + return RT_ERR_FAILED; + + if ((retVal = rtl8367c_setAsicLedBlinkRate(blinkRate)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_led_blinkRate_get + * Description: + * Get LED blinking rate at mode 0 to mode 3 + * Input: + * None + * Output: + * pBlinkRate - blinking rate. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API get LED blinking rate: + * - LED_BLINKRATE_32MS + * - LED_BLINKRATE_64MS, + * - LED_BLINKRATE_128MS, + * - LED_BLINKRATE_256MS, + * - LED_BLINKRATE_512MS, + * - LED_BLINKRATE_1024MS, + * - LED_BLINKRATE_48MS, + * - LED_BLINKRATE_96MS, + */ +rtk_api_ret_t dal_rtl8367c_led_blinkRate_get(rtk_led_blink_rate_t *pBlinkRate) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pBlinkRate) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicLedBlinkRate(pBlinkRate)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_led_groupConfig_set + * Description: + * Set per group Led to congiuration mode + * Input: + * group - LED group. + * config - LED configuration + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can set LED indicated information configuration for each LED group with 1 to 1 led mapping to each port. + * - Definition LED Statuses Description + * - 0000 LED_Off LED pin Tri-State. + * - 0001 Dup/Col Collision, Full duplex Indicator. + * - 0010 Link/Act Link, Activity Indicator. + * - 0011 Spd1000 1000Mb/s Speed Indicator. + * - 0100 Spd100 100Mb/s Speed Indicator. + * - 0101 Spd10 10Mb/s Speed Indicator. + * - 0110 Spd1000/Act 1000Mb/s Speed/Activity Indicator. + * - 0111 Spd100/Act 100Mb/s Speed/Activity Indicator. + * - 1000 Spd10/Act 10Mb/s Speed/Activity Indicator. + * - 1001 Spd100 (10)/Act 10/100Mb/s Speed/Activity Indicator. + * - 1010 LoopDetect LoopDetect Indicator. + * - 1011 EEE EEE Indicator. + * - 1100 Link/Rx Link, Activity Indicator. + * - 1101 Link/Tx Link, Activity Indicator. + * - 1110 Master Link on Master Indicator. + * - 1111 Act Activity Indicator. Low for link established. + */ +rtk_api_ret_t dal_rtl8367c_led_groupConfig_set(rtk_led_group_t group, rtk_led_congig_t config) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (LED_GROUP_END <= group) + return RT_ERR_FAILED; + + if (LED_CONFIG_END <= config) + return RT_ERR_FAILED; + + if ((retVal = rtl8367c_setAsicLedIndicateInfoConfig(group, config)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_led_groupConfig_get + * Description: + * Get Led group congiuration mode + * Input: + * group - LED group. + * Output: + * pConfig - LED configuration. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get LED indicated information configuration for each LED group. + */ +rtk_api_ret_t dal_rtl8367c_led_groupConfig_get(rtk_led_group_t group, rtk_led_congig_t *pConfig) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (LED_GROUP_END <= group) + return RT_ERR_FAILED; + + if(NULL == pConfig) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicLedIndicateInfoConfig(group, pConfig)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_led_groupAbility_set + * Description: + * Configure per group Led ability + * Input: + * group - LED group. + * pAbility - LED ability + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * None. + */ + +rtk_api_ret_t dal_rtl8367c_led_groupAbility_set(rtk_led_group_t group, rtk_led_ability_t *pAbility) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (LED_GROUP_END <= group) + return RT_ERR_FAILED; + + if(pAbility == NULL) + return RT_ERR_NULL_POINTER; + + if( (pAbility->link_10m >= RTK_ENABLE_END) || (pAbility->link_100m >= RTK_ENABLE_END) || + (pAbility->link_500m >= RTK_ENABLE_END) || (pAbility->link_1000m >= RTK_ENABLE_END) || (pAbility->link_2500m != DISABLED) || + (pAbility->act_rx >= RTK_ENABLE_END) || (pAbility->act_tx >= RTK_ENABLE_END) ) + { + return RT_ERR_INPUT; + } + + if ((retVal = rtl8367c_getAsicReg(RTL8367C_REG_LED0_DATA_CTRL + (rtk_uint32)group, ®Data)) != RT_ERR_OK) + return retVal; + + if(pAbility->link_10m == ENABLED) + regData |= 0x0001; + else + regData &= ~0x0001; + + if(pAbility->link_100m == ENABLED) + regData |= 0x0002; + else + regData &= ~0x0002; + + if(pAbility->link_500m == ENABLED) + regData |= 0x0004; + else + regData &= ~0x0004; + + if(pAbility->link_1000m == ENABLED) + regData |= 0x0008; + else + regData &= ~0x0008; + + if(pAbility->act_rx == ENABLED) + regData |= 0x0010; + else + regData &= ~0x0010; + + if(pAbility->act_tx == ENABLED) + regData |= 0x0020; + else + regData &= ~0x0020; + + regData |= (0x0001 << 6); + + if ((retVal = rtl8367c_setAsicReg(RTL8367C_REG_LED0_DATA_CTRL + (rtk_uint32)group, regData)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_led_groupAbility_get + * Description: + * Get per group Led ability + * Input: + * group - LED group. + * pAbility - LED ability + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * None. + */ + +rtk_api_ret_t dal_rtl8367c_led_groupAbility_get(rtk_led_group_t group, rtk_led_ability_t *pAbility) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (LED_GROUP_END <= group) + return RT_ERR_FAILED; + + if(pAbility == NULL) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicReg(RTL8367C_REG_LED0_DATA_CTRL + (rtk_uint32)group, ®Data)) != RT_ERR_OK) + return retVal; + + pAbility->link_10m = (regData & 0x0001) ? ENABLED : DISABLED; + pAbility->link_100m = (regData & 0x0002) ? ENABLED : DISABLED; + pAbility->link_500m = (regData & 0x0004) ? ENABLED : DISABLED; + pAbility->link_1000m = (regData & 0x0008) ? ENABLED : DISABLED; + pAbility->act_rx = (regData & 0x0010) ? ENABLED : DISABLED; + pAbility->act_tx = (regData & 0x0020) ? ENABLED : DISABLED; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_led_serialMode_set + * Description: + * Set Led serial mode active congiuration + * Input: + * active - LED group. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can set LED serial mode active congiuration. + */ +rtk_api_ret_t dal_rtl8367c_led_serialMode_set(rtk_led_active_t active) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if ( active >= LED_ACTIVE_END) + return RT_ERR_INPUT; + + if ((retVal = rtl8367c_setAsicLedSerialModeConfig(active,1))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_led_serialMode_get + * Description: + * Get Led group congiuration mode + * Input: + * group - LED group. + * Output: + * pConfig - LED configuration. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get LED serial mode active configuration. + */ +rtk_api_ret_t dal_rtl8367c_led_serialMode_get(rtk_led_active_t *pActive) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pActive) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicLedSerialModeConfig(pActive,®Data))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_led_OutputEnable_set + * Description: + * This API set LED I/O state. + * Input: + * enabled - LED I/O state + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error parameter + * Note: + * This API set LED I/O state. + */ +rtk_api_ret_t dal_rtl8367c_led_OutputEnable_set(rtk_enable_t state) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (state >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if ((retVal = rtl8367c_setAsicLedOutputEnable(state))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_led_OutputEnable_get + * Description: + * This API get LED I/O state. + * Input: + * None. + * Output: + * pEnabled - LED I/O state + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error parameter + * Note: + * This API set current LED I/O state. + */ +rtk_api_ret_t dal_rtl8367c_led_OutputEnable_get(rtk_enable_t *pState) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(pState == NULL) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicLedOutputEnable(pState))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; + +} + +/* Function Name: + * dal_rtl8367c_led_serialModePortmask_set + * Description: + * This API configure Serial LED output Group and portmask + * Input: + * output - output group + * pPortmask - output portmask + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error parameter + * Note: + * None. + */ +rtk_api_ret_t dal_rtl8367c_led_serialModePortmask_set(rtk_led_serialOutput_t output, rtk_portmask_t *pPortmask) +{ + rtk_api_ret_t retVal; + rtk_uint32 pmask; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(output >= SERIAL_LED_END) + return RT_ERR_INPUT; + + if(pPortmask == NULL) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtk_switch_portmask_L2P_get(pPortmask, &pmask)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicLedSerialOutput((rtk_uint32)output, pmask))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_led_serialModePortmask_get + * Description: + * This API get Serial LED output Group and portmask + * Input: + * None. + * Output: + * pOutput - output group + * pPortmask - output portmask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error parameter + * Note: + * None. + */ +rtk_api_ret_t dal_rtl8367c_led_serialModePortmask_get(rtk_led_serialOutput_t *pOutput, rtk_portmask_t *pPortmask) +{ + rtk_api_ret_t retVal; + rtk_uint32 pmask; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(pOutput == NULL) + return RT_ERR_NULL_POINTER; + + if(pPortmask == NULL) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicLedSerialOutput((rtk_uint32 *)pOutput, &pmask))!=RT_ERR_OK) + return retVal; + + if((retVal = rtk_switch_portmask_P2L_get(pmask, pPortmask)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_led.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_led.h new file mode 100644 index 00000000..aeaaadd9 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_led.h @@ -0,0 +1,412 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8367/RTL8367C switch high-level API + * + * Feature : The file includes LED module high-layer API defination + * + */ + +#ifndef __DAL_RTL8367C_LED_H__ +#define __DAL_RTL8367C_LED_H__ +#include <../../led.h> + +/* Function Name: + * dal_rtl8367c_led_enable_set + * Description: + * Set Led enable congiuration + * Input: + * group - LED group id. + * pPortmask - LED enable port mask. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can be used to enable LED per port per group. + */ +extern rtk_api_ret_t dal_rtl8367c_led_enable_set(rtk_led_group_t group, rtk_portmask_t *pPortmask); + +/* Function Name: + * dal_rtl8367c_led_enable_get + * Description: + * Get Led enable congiuration + * Input: + * group - LED group id. + * Output: + * pPortmask - LED enable port mask. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can be used to get LED enable status. + */ +extern rtk_api_ret_t dal_rtl8367c_led_enable_get(rtk_led_group_t group, rtk_portmask_t *pPortmask); + +/* Function Name: + * dal_rtl8367c_led_operation_set + * Description: + * Set Led operation mode + * Input: + * mode - LED operation mode. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can set Led operation mode. + * The modes that can be set are as following: + * - LED_OP_SCAN, + * - LED_OP_PARALLEL, + * - LED_OP_SERIAL, + */ +extern rtk_api_ret_t dal_rtl8367c_led_operation_set(rtk_led_operation_t mode); + +/* Function Name: + * dal_rtl8367c_led_operation_get + * Description: + * Get Led operation mode + * Input: + * None + * Output: + * pMode - Support LED operation mode. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get Led operation mode. + * The modes that can be set are as following: + * - LED_OP_SCAN, + * - LED_OP_PARALLEL, + * - LED_OP_SERIAL, + */ +extern rtk_api_ret_t dal_rtl8367c_led_operation_get(rtk_led_operation_t *pMode); + +/* Function Name: + * dal_rtl8367c_led_modeForce_set + * Description: + * Set Led group to congiuration force mode + * Input: + * port - port ID + * group - Support LED group id. + * mode - Support LED force mode. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Error Port ID + * Note: + * The API can force to one force mode. + * The force modes that can be set are as following: + * - LED_FORCE_NORMAL, + * - LED_FORCE_BLINK, + * - LED_FORCE_OFF, + * - LED_FORCE_ON. + */ +extern rtk_api_ret_t dal_rtl8367c_led_modeForce_set(rtk_port_t port, rtk_led_group_t group, rtk_led_force_mode_t mode); + +/* Function Name: + * dal_rtl8367c_led_modeForce_get + * Description: + * Get Led group to congiuration force mode + * Input: + * port - port ID + * group - Support LED group id. + * pMode - Support LED force mode. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Error Port ID + * Note: + * The API can get forced Led group mode. + * The force modes that can be set are as following: + * - LED_FORCE_NORMAL, + * - LED_FORCE_BLINK, + * - LED_FORCE_OFF, + * - LED_FORCE_ON. + */ +extern rtk_api_ret_t dal_rtl8367c_led_modeForce_get(rtk_port_t port, rtk_led_group_t group, rtk_led_force_mode_t *pMode); + +/* Function Name: + * dal_rtl8367c_led_blinkRate_set + * Description: + * Set LED blinking rate + * Input: + * blinkRate - blinking rate. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API configure LED blinking rate: + * - LED_BLINKRATE_32MS + * - LED_BLINKRATE_64MS, + * - LED_BLINKRATE_128MS, + * - LED_BLINKRATE_256MS, + * - LED_BLINKRATE_512MS, + * - LED_BLINKRATE_1024MS, + * - LED_BLINKRATE_48MS, + * - LED_BLINKRATE_96MS, + */ +extern rtk_api_ret_t dal_rtl8367c_led_blinkRate_set(rtk_led_blink_rate_t blinkRate); + +/* Function Name: + * dal_rtl8367c_led_blinkRate_get + * Description: + * Get LED blinking rate at mode 0 to mode 3 + * Input: + * None + * Output: + * pBlinkRate - blinking rate. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API get LED blinking rate: + * - LED_BLINKRATE_32MS + * - LED_BLINKRATE_64MS, + * - LED_BLINKRATE_128MS, + * - LED_BLINKRATE_256MS, + * - LED_BLINKRATE_512MS, + * - LED_BLINKRATE_1024MS, + * - LED_BLINKRATE_48MS, + * - LED_BLINKRATE_96MS, + */ +extern rtk_api_ret_t dal_rtl8367c_led_blinkRate_get(rtk_led_blink_rate_t *pBlinkRate); + +/* Function Name: + * dal_rtl8367c_led_groupConfig_set + * Description: + * Set per group Led to congiuration mode + * Input: + * group - LED group. + * config - LED configuration + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can set LED indicated information configuration for each LED group with 1 to 1 led mapping to each port. + * - Definition LED Statuses Description + * - 0000 LED_Off LED pin Tri-State. + * - 0001 Dup/Col Collision, Full duplex Indicator. + * - 0010 Link/Act Link, Activity Indicator. + * - 0011 Spd1000 1000Mb/s Speed Indicator. + * - 0100 Spd100 100Mb/s Speed Indicator. + * - 0101 Spd10 10Mb/s Speed Indicator. + * - 0110 Spd1000/Act 1000Mb/s Speed/Activity Indicator. + * - 0111 Spd100/Act 100Mb/s Speed/Activity Indicator. + * - 1000 Spd10/Act 10Mb/s Speed/Activity Indicator. + * - 1001 Spd100 (10)/Act 10/100Mb/s Speed/Activity Indicator. + * - 1010 LoopDetect LoopDetect Indicator. + * - 1011 EEE EEE Indicator. + * - 1100 Link/Rx Link, Activity Indicator. + * - 1101 Link/Tx Link, Activity Indicator. + * - 1110 Master Link on Master Indicator. + * - 1111 Act Activity Indicator. Low for link established. + */ +extern rtk_api_ret_t dal_rtl8367c_led_groupConfig_set(rtk_led_group_t group, rtk_led_congig_t config); + +/* Function Name: + * dal_rtl8367c_led_groupConfig_get + * Description: + * Get Led group congiuration mode + * Input: + * group - LED group. + * Output: + * pConfig - LED configuration. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get LED indicated information configuration for each LED group. + */ +extern rtk_api_ret_t dal_rtl8367c_led_groupConfig_get(rtk_led_group_t group, rtk_led_congig_t *pConfig); + +/* Function Name: + * dal_rtl8367c_led_groupAbility_set + * Description: + * Configure per group Led ability + * Input: + * group - LED group. + * pAbility - LED ability + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * None. + */ + +extern rtk_api_ret_t dal_rtl8367c_led_groupAbility_set(rtk_led_group_t group, rtk_led_ability_t *pAbility); + +/* Function Name: + * dal_rtl8367c_led_groupAbility_get + * Description: + * Get per group Led ability + * Input: + * group - LED group. + * pAbility - LED ability + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * None. + */ + +extern rtk_api_ret_t dal_rtl8367c_led_groupAbility_get(rtk_led_group_t group, rtk_led_ability_t *pAbility); + +/* Function Name: + * dal_rtl8367c_led_serialMode_set + * Description: + * Set Led serial mode active congiuration + * Input: + * active - LED group. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can set LED serial mode active congiuration. + */ +extern rtk_api_ret_t dal_rtl8367c_led_serialMode_set(rtk_led_active_t active); + +/* Function Name: + * dal_rtl8367c_led_serialMode_get + * Description: + * Get Led group congiuration mode + * Input: + * group - LED group. + * Output: + * pConfig - LED configuration. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get LED serial mode active configuration. + */ +extern rtk_api_ret_t dal_rtl8367c_led_serialMode_get(rtk_led_active_t *pActive); + +/* Function Name: + * dal_rtl8367c_led_OutputEnable_set + * Description: + * This API set LED I/O state. + * Input: + * enabled - LED I/O state + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error parameter + * Note: + * This API set LED I/O state. + */ +extern rtk_api_ret_t dal_rtl8367c_led_OutputEnable_set(rtk_enable_t state); + + +/* Function Name: + * dal_rtl8367c_led_OutputEnable_get + * Description: + * This API get LED I/O state. + * Input: + * None. + * Output: + * pEnabled - LED I/O state + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error parameter + * Note: + * This API set current LED I/O state. + */ +extern rtk_api_ret_t dal_rtl8367c_led_OutputEnable_get(rtk_enable_t *pState); + +/* Function Name: + * dal_rtl8367c_led_serialModePortmask_set + * Description: + * This API configure Serial LED output Group and portmask + * Input: + * output - output group + * pPortmask - output portmask + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error parameter + * Note: + * None. + */ +extern rtk_api_ret_t dal_rtl8367c_led_serialModePortmask_set(rtk_led_serialOutput_t output, rtk_portmask_t *pPortmask); + +/* Function Name: + * dal_rtl8367c_led_serialModePortmask_get + * Description: + * This API get Serial LED output Group and portmask + * Input: + * None. + * Output: + * pOutput - output group + * pPortmask - output portmask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error parameter + * Note: + * None. + */ +extern rtk_api_ret_t dal_rtl8367c_led_serialModePortmask_get(rtk_led_serialOutput_t *pOutput, rtk_portmask_t *pPortmask); + +#endif /* __DAL_RTL8367C_LED_H__ */ diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_mapper.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_mapper.c new file mode 100644 index 00000000..8f909e7e --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_mapper.c @@ -0,0 +1,615 @@ + +/* + * Copyright (C) 2012 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + */ + +/* + * Include Files + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * Symbol Definition + */ + +/* + * Data Declaration + */ +static dal_mapper_t dal_rtl8367c_mapper = +{ + /* Switch */ + .switch_init = dal_rtl8367c_switch_init, + .switch_portMaxPktLen_set = dal_rtl8367c_switch_portMaxPktLen_set, + .switch_portMaxPktLen_get = dal_rtl8367c_switch_portMaxPktLen_get, + .switch_maxPktLenCfg_set = dal_rtl8367c_switch_maxPktLenCfg_set, + .switch_maxPktLenCfg_get = dal_rtl8367c_switch_maxPktLenCfg_get, + .switch_greenEthernet_set = dal_rtl8367c_switch_greenEthernet_set, + .switch_greenEthernet_get = dal_rtl8367c_switch_greenEthernet_get, + + /* eee */ + .eee_init = dal_rtl8367c_eee_init, + .eee_portEnable_set = dal_rtl8367c_eee_portEnable_set, + .eee_portEnable_get = dal_rtl8367c_eee_portEnable_get, + + /* led */ + .led_enable_set = dal_rtl8367c_led_enable_set, + .led_enable_get = dal_rtl8367c_led_enable_get, + .led_operation_set = dal_rtl8367c_led_operation_set, + .led_operation_get = dal_rtl8367c_led_operation_get, + .led_modeForce_set = dal_rtl8367c_led_modeForce_set, + .led_modeForce_get = dal_rtl8367c_led_modeForce_get, + .led_blinkRate_set = dal_rtl8367c_led_blinkRate_set, + .led_blinkRate_get = dal_rtl8367c_led_blinkRate_get, + .led_groupConfig_set = dal_rtl8367c_led_groupConfig_set, + .led_groupConfig_get = dal_rtl8367c_led_groupConfig_get, + .led_groupAbility_set = dal_rtl8367c_led_groupAbility_set, + .led_groupAbility_get = dal_rtl8367c_led_groupAbility_get, + .led_serialMode_set = dal_rtl8367c_led_serialMode_set, + .led_serialMode_get = dal_rtl8367c_led_serialMode_get, + .led_OutputEnable_set = dal_rtl8367c_led_OutputEnable_set, + .led_OutputEnable_get = dal_rtl8367c_led_OutputEnable_get, + .led_serialModePortmask_set = dal_rtl8367c_led_serialModePortmask_set, + .led_serialModePortmask_get = dal_rtl8367c_led_serialModePortmask_get, + + /* oam */ + .oam_init = dal_rtl8367c_oam_init, + .oam_state_set = dal_rtl8367c_oam_state_set, + .oam_state_get = dal_rtl8367c_oam_state_get, + .oam_parserAction_set = dal_rtl8367c_oam_parserAction_set, + .oam_parserAction_get = dal_rtl8367c_oam_parserAction_get, + .oam_multiplexerAction_set = dal_rtl8367c_oam_multiplexerAction_set, + .oam_multiplexerAction_get = dal_rtl8367c_oam_multiplexerAction_get, + + /* cpu */ + .cpu_enable_set = dal_rtl8367c_cpu_enable_set, + .cpu_enable_get = dal_rtl8367c_cpu_enable_get, + .cpu_tagPort_set = dal_rtl8367c_cpu_tagPort_set, + .cpu_tagPort_get = dal_rtl8367c_cpu_tagPort_get, + .cpu_awarePort_set = dal_rtl8367c_cpu_awarePort_set, + .cpu_awarePort_get = dal_rtl8367c_cpu_awarePort_get, + .cpu_tagPosition_set = dal_rtl8367c_cpu_tagPosition_set, + .cpu_tagPosition_get = dal_rtl8367c_cpu_tagPosition_get, + .cpu_tagLength_set = dal_rtl8367c_cpu_tagLength_set, + .cpu_tagLength_get = dal_rtl8367c_cpu_tagLength_get, + .cpu_acceptLength_set = dal_rtl8367c_cpu_acceptLength_set, + .cpu_acceptLength_get = dal_rtl8367c_cpu_acceptLength_get, + .cpu_priRemap_set = dal_rtl8367c_cpu_priRemap_set, + .cpu_priRemap_get = dal_rtl8367c_cpu_priRemap_get, + + /* stat */ + .stat_global_reset = dal_rtl8367c_stat_global_reset, + .stat_port_reset = dal_rtl8367c_stat_port_reset, + .stat_queueManage_reset = dal_rtl8367c_stat_queueManage_reset, + .stat_global_get = dal_rtl8367c_stat_global_get, + .stat_global_getAll = dal_rtl8367c_stat_global_getAll, + .stat_port_get = dal_rtl8367c_stat_port_get, + .stat_port_getAll = dal_rtl8367c_stat_port_getAll, + .stat_logging_counterCfg_set = dal_rtl8367c_stat_logging_counterCfg_set, + .stat_logging_counterCfg_get = dal_rtl8367c_stat_logging_counterCfg_get, + .stat_logging_counter_reset = dal_rtl8367c_stat_logging_counter_reset, + .stat_logging_counter_get = dal_rtl8367c_stat_logging_counter_get, + .stat_lengthMode_set = dal_rtl8367c_stat_lengthMode_set, + .stat_lengthMode_get = dal_rtl8367c_stat_lengthMode_get, + + /* l2 */ + .l2_init = dal_rtl8367c_l2_init, + .l2_addr_add = dal_rtl8367c_l2_addr_add, + .l2_addr_get = dal_rtl8367c_l2_addr_get, + .l2_addr_next_get = dal_rtl8367c_l2_addr_next_get, + .l2_addr_del = dal_rtl8367c_l2_addr_del, + .l2_mcastAddr_add = dal_rtl8367c_l2_mcastAddr_add, + .l2_mcastAddr_get = dal_rtl8367c_l2_mcastAddr_get, + .l2_mcastAddr_next_get = dal_rtl8367c_l2_mcastAddr_next_get, + .l2_mcastAddr_del = dal_rtl8367c_l2_mcastAddr_del, + .l2_ipMcastAddr_add = dal_rtl8367c_l2_ipMcastAddr_add, + .l2_ipMcastAddr_get = dal_rtl8367c_l2_ipMcastAddr_get, + .l2_ipMcastAddr_next_get = dal_rtl8367c_l2_ipMcastAddr_next_get, + .l2_ipMcastAddr_del = dal_rtl8367c_l2_ipMcastAddr_del, + .l2_ipVidMcastAddr_add = dal_rtl8367c_l2_ipVidMcastAddr_add, + .l2_ipVidMcastAddr_get = dal_rtl8367c_l2_ipVidMcastAddr_get, + .l2_ipVidMcastAddr_next_get = dal_rtl8367c_l2_ipVidMcastAddr_next_get, + .l2_ipVidMcastAddr_del = dal_rtl8367c_l2_ipVidMcastAddr_del, + .l2_ucastAddr_flush = dal_rtl8367c_l2_ucastAddr_flush, + .l2_table_clear = dal_rtl8367c_l2_table_clear, + .l2_table_clearStatus_get = dal_rtl8367c_l2_table_clearStatus_get, + .l2_flushLinkDownPortAddrEnable_set = dal_rtl8367c_l2_flushLinkDownPortAddrEnable_set, + .l2_flushLinkDownPortAddrEnable_get = dal_rtl8367c_l2_flushLinkDownPortAddrEnable_get, + .l2_agingEnable_set = dal_rtl8367c_l2_agingEnable_set, + .l2_agingEnable_get = dal_rtl8367c_l2_agingEnable_get, + .l2_limitLearningCnt_set = dal_rtl8367c_l2_limitLearningCnt_set, + .l2_limitLearningCnt_get = dal_rtl8367c_l2_limitLearningCnt_get, + .l2_limitSystemLearningCnt_set = dal_rtl8367c_l2_limitSystemLearningCnt_set, + .l2_limitSystemLearningCnt_get = dal_rtl8367c_l2_limitSystemLearningCnt_get, + .l2_limitLearningCntAction_set = dal_rtl8367c_l2_limitLearningCntAction_set, + .l2_limitLearningCntAction_get = dal_rtl8367c_l2_limitLearningCntAction_get, + .l2_limitSystemLearningCntAction_set = dal_rtl8367c_l2_limitSystemLearningCntAction_set, + .l2_limitSystemLearningCntAction_get = dal_rtl8367c_l2_limitSystemLearningCntAction_get, + .l2_limitSystemLearningCntPortMask_set = dal_rtl8367c_l2_limitSystemLearningCntPortMask_set, + .l2_limitSystemLearningCntPortMask_get = dal_rtl8367c_l2_limitSystemLearningCntPortMask_get, + .l2_learningCnt_get = dal_rtl8367c_l2_learningCnt_get, + .l2_floodPortMask_set = dal_rtl8367c_l2_floodPortMask_set, + .l2_floodPortMask_get = dal_rtl8367c_l2_floodPortMask_get, + .l2_localPktPermit_set = dal_rtl8367c_l2_localPktPermit_set, + .l2_localPktPermit_get = dal_rtl8367c_l2_localPktPermit_get, + .l2_aging_set = dal_rtl8367c_l2_aging_set, + .l2_aging_get = dal_rtl8367c_l2_aging_get, + .l2_ipMcastAddrLookup_set = dal_rtl8367c_l2_ipMcastAddrLookup_set, + .l2_ipMcastAddrLookup_get = dal_rtl8367c_l2_ipMcastAddrLookup_get, + .l2_ipMcastForwardRouterPort_set = dal_rtl8367c_l2_ipMcastForwardRouterPort_set, + .l2_ipMcastForwardRouterPort_get = dal_rtl8367c_l2_ipMcastForwardRouterPort_get, + .l2_ipMcastGroupEntry_add = dal_rtl8367c_l2_ipMcastGroupEntry_add, + .l2_ipMcastGroupEntry_del = dal_rtl8367c_l2_ipMcastGroupEntry_del, + .l2_ipMcastGroupEntry_get = dal_rtl8367c_l2_ipMcastGroupEntry_get, + .l2_entry_get = dal_rtl8367c_l2_entry_get, + .l2_lookupHitIsolationAction_set = NULL, + .l2_lookupHitIsolationAction_get = NULL, + + /* interrupt */ + .int_polarity_set = dal_rtl8367c_int_polarity_set, + .int_polarity_get = dal_rtl8367c_int_polarity_get, + .int_control_set = dal_rtl8367c_int_control_set, + .int_control_get = dal_rtl8367c_int_control_get, + .int_status_set = dal_rtl8367c_int_status_set, + .int_status_get = dal_rtl8367c_int_status_get, + .int_advanceInfo_get = dal_rtl8367c_int_advanceInfo_get, + + /* acl */ + .filter_igrAcl_init = dal_rtl8367c_filter_igrAcl_init, + .filter_igrAcl_field_add = dal_rtl8367c_filter_igrAcl_field_add, + .filter_igrAcl_cfg_add = dal_rtl8367c_filter_igrAcl_cfg_add, + .filter_igrAcl_cfg_del = dal_rtl8367c_filter_igrAcl_cfg_del, + .filter_igrAcl_cfg_delAll = dal_rtl8367c_filter_igrAcl_cfg_delAll, + .filter_igrAcl_cfg_get = dal_rtl8367c_filter_igrAcl_cfg_get, + .filter_igrAcl_unmatchAction_set = dal_rtl8367c_filter_igrAcl_unmatchAction_set, + .filter_igrAcl_unmatchAction_get = dal_rtl8367c_filter_igrAcl_unmatchAction_get, + .filter_igrAcl_state_set = dal_rtl8367c_filter_igrAcl_state_set, + .filter_igrAcl_state_get = dal_rtl8367c_filter_igrAcl_state_get, + .filter_igrAcl_template_set = dal_rtl8367c_filter_igrAcl_template_set, + .filter_igrAcl_template_get = dal_rtl8367c_filter_igrAcl_template_get, + .filter_igrAcl_field_sel_set = dal_rtl8367c_filter_igrAcl_field_sel_set, + .filter_igrAcl_field_sel_get = dal_rtl8367c_filter_igrAcl_field_sel_get, + .filter_iprange_set = dal_rtl8367c_filter_iprange_set, + .filter_iprange_get = dal_rtl8367c_filter_iprange_get, + .filter_vidrange_set = dal_rtl8367c_filter_vidrange_set, + .filter_vidrange_get = dal_rtl8367c_filter_vidrange_get, + .filter_portrange_set = dal_rtl8367c_filter_portrange_set, + .filter_portrange_get = dal_rtl8367c_filter_portrange_get, + .filter_igrAclPolarity_set = dal_rtl8367c_filter_igrAclPolarity_set, + .filter_igrAclPolarity_get = dal_rtl8367c_filter_igrAclPolarity_get, + + /* mirror */ + .mirror_portBased_set = dal_rtl8367c_mirror_portBased_set, + .mirror_portBased_get = dal_rtl8367c_mirror_portBased_get, + .mirror_portIso_set = dal_rtl8367c_mirror_portIso_set, + .mirror_portIso_get = dal_rtl8367c_mirror_portIso_get, + .mirror_vlanLeaky_set = dal_rtl8367c_mirror_vlanLeaky_set, + .mirror_vlanLeaky_get = dal_rtl8367c_mirror_vlanLeaky_get, + .mirror_isolationLeaky_set = dal_rtl8367c_mirror_isolationLeaky_set, + .mirror_isolationLeaky_get = dal_rtl8367c_mirror_isolationLeaky_get, + .mirror_keep_set = dal_rtl8367c_mirror_keep_set, + .mirror_keep_get = dal_rtl8367c_mirror_keep_get, + .mirror_override_set = dal_rtl8367c_mirror_override_set, + .mirror_override_get = dal_rtl8367c_mirror_override_get, + + /* port */ + .port_phyAutoNegoAbility_set = dal_rtl8367c_port_phyAutoNegoAbility_set, + .port_phyAutoNegoAbility_get = dal_rtl8367c_port_phyAutoNegoAbility_get, + .port_phyForceModeAbility_set = dal_rtl8367c_port_phyForceModeAbility_set, + .port_phyForceModeAbility_get = dal_rtl8367c_port_phyForceModeAbility_get, + .port_phyStatus_get = dal_rtl8367c_port_phyStatus_get, + .port_macForceLink_set = dal_rtl8367c_port_macForceLink_set, + .port_macForceLink_get = dal_rtl8367c_port_macForceLink_get, + .port_macForceLinkExt_set = dal_rtl8367c_port_macForceLinkExt_set, + .port_macForceLinkExt_get = dal_rtl8367c_port_macForceLinkExt_get, + .port_macStatus_get = dal_rtl8367c_port_macStatus_get, + .port_macLocalLoopbackEnable_set = dal_rtl8367c_port_macLocalLoopbackEnable_set, + .port_macLocalLoopbackEnable_get = dal_rtl8367c_port_macLocalLoopbackEnable_get, + .port_phyReg_set = dal_rtl8367c_port_phyReg_set, + .port_phyReg_get = dal_rtl8367c_port_phyReg_get, + .port_phyOCPReg_set = dal_rtl8367c_port_phyOCPReg_set, + .port_phyOCPReg_get = dal_rtl8367c_port_phyOCPReg_get, + .port_backpressureEnable_set = dal_rtl8367c_port_backpressureEnable_set, + .port_backpressureEnable_get = dal_rtl8367c_port_backpressureEnable_get, + .port_adminEnable_set = dal_rtl8367c_port_adminEnable_set, + .port_adminEnable_get = dal_rtl8367c_port_adminEnable_get, + .port_isolation_set = dal_rtl8367c_port_isolation_set, + .port_isolation_get = dal_rtl8367c_port_isolation_get, + .port_rgmiiDelayExt_set = dal_rtl8367c_port_rgmiiDelayExt_set, + .port_rgmiiDelayExt_get = dal_rtl8367c_port_rgmiiDelayExt_get, + .port_phyEnableAll_set = dal_rtl8367c_port_phyEnableAll_set, + .port_phyEnableAll_get = dal_rtl8367c_port_phyEnableAll_get, + .port_efid_set = dal_rtl8367c_port_efid_set, + .port_efid_get = dal_rtl8367c_port_efid_get, + .port_phyComboPortMedia_set = dal_rtl8367c_port_phyComboPortMedia_set, + .port_phyComboPortMedia_get = dal_rtl8367c_port_phyComboPortMedia_get, + .port_rtctEnable_set = dal_rtl8367c_port_rtctEnable_set, + .port_rtctDisable_set = dal_rtl8367c_port_rtctDisable_set, + .port_rtctResult_get = dal_rtl8367c_port_rtctResult_get, + .port_sds_reset = dal_rtl8367c_port_sds_reset, + .port_sgmiiLinkStatus_get = dal_rtl8367c_port_sgmiiLinkStatus_get, + .port_sgmiiNway_set = dal_rtl8367c_port_sgmiiNway_set, + .port_sgmiiNway_get = dal_rtl8367c_port_sgmiiNway_get, + .port_fiberAbilityExt_set = dal_rtl8367c_port_fiberAbilityExt_set, + .port_fiberAbilityExt_get = dal_rtl8367c_port_fiberAbilityExt_get, + .port_autoDos_set = dal_rtl8367c_port_autoDos_set, + .port_autoDos_get = dal_rtl8367c_port_autoDos_get, + .port_fiberAbility_set = NULL, + .port_fiberAbility_get = NULL, + .port_phyMdx_set = dal_rtl8367c_port_phyMdx_set, + .port_phyMdx_get = dal_rtl8367c_port_phyMdx_get, + .port_phyMdxStatus_get = dal_rtl8367c_port_phyMdxStatus_get, + .port_phyTestMode_set = dal_rtl8367c_port_phyTestMode_set, + .port_phyTestMode_get = dal_rtl8367c_port_phyTestMode_get, + + /* Trap */ + .trap_unknownUnicastPktAction_set = dal_rtl8367c_trap_unknownUnicastPktAction_set, + .trap_unknownUnicastPktAction_get = dal_rtl8367c_trap_unknownUnicastPktAction_get, + .trap_unknownMacPktAction_set = dal_rtl8367c_trap_unknownMacPktAction_set, + .trap_unknownMacPktAction_get = dal_rtl8367c_trap_unknownMacPktAction_get, + .trap_unmatchMacPktAction_set = dal_rtl8367c_trap_unmatchMacPktAction_set, + .trap_unmatchMacPktAction_get = dal_rtl8367c_trap_unmatchMacPktAction_get, + .trap_unmatchMacMoving_set = dal_rtl8367c_trap_unmatchMacMoving_set, + .trap_unmatchMacMoving_get = dal_rtl8367c_trap_unmatchMacMoving_get, + .trap_unknownMcastPktAction_set = dal_rtl8367c_trap_unknownMcastPktAction_set, + .trap_unknownMcastPktAction_get = dal_rtl8367c_trap_unknownMcastPktAction_get, + .trap_lldpEnable_set = dal_rtl8367c_trap_lldpEnable_set, + .trap_lldpEnable_get = dal_rtl8367c_trap_lldpEnable_get, + .trap_reasonTrapToCpuPriority_set = dal_rtl8367c_trap_reasonTrapToCpuPriority_set, + .trap_reasonTrapToCpuPriority_get = dal_rtl8367c_trap_reasonTrapToCpuPriority_get, + .trap_rmaAction_set = dal_rtl8367c_trap_rmaAction_set, + .trap_rmaAction_get = dal_rtl8367c_trap_rmaAction_get, + .trap_rmaKeepFormat_set = dal_rtl8367c_trap_rmaKeepFormat_set, + .trap_rmaKeepFormat_get = dal_rtl8367c_trap_rmaKeepFormat_get, + .trap_portUnknownMacPktAction_set = NULL, + .trap_portUnknownMacPktAction_get = NULL, + .trap_portUnmatchMacPktAction_set = NULL, + .trap_portUnmatchMacPktAction_get = NULL, + + /* IGMP */ + .igmp_init = dal_rtl8367c_igmp_init, + .igmp_state_set = dal_rtl8367c_igmp_state_set, + .igmp_state_get = dal_rtl8367c_igmp_state_get, + .igmp_static_router_port_set = dal_rtl8367c_igmp_static_router_port_set, + .igmp_static_router_port_get = dal_rtl8367c_igmp_static_router_port_get, + .igmp_protocol_set = dal_rtl8367c_igmp_protocol_set, + .igmp_protocol_get = dal_rtl8367c_igmp_protocol_get, + .igmp_fastLeave_set = dal_rtl8367c_igmp_fastLeave_set, + .igmp_fastLeave_get = dal_rtl8367c_igmp_fastLeave_get, + .igmp_maxGroup_set = dal_rtl8367c_igmp_maxGroup_set, + .igmp_maxGroup_get = dal_rtl8367c_igmp_maxGroup_get, + .igmp_currentGroup_get = dal_rtl8367c_igmp_currentGroup_get, + .igmp_tableFullAction_set = dal_rtl8367c_igmp_tableFullAction_set, + .igmp_tableFullAction_get = dal_rtl8367c_igmp_tableFullAction_get, + .igmp_checksumErrorAction_set = dal_rtl8367c_igmp_checksumErrorAction_set, + .igmp_checksumErrorAction_get = dal_rtl8367c_igmp_checksumErrorAction_get, + .igmp_leaveTimer_set = dal_rtl8367c_igmp_leaveTimer_set, + .igmp_leaveTimer_get = dal_rtl8367c_igmp_leaveTimer_get, + .igmp_queryInterval_set = dal_rtl8367c_igmp_queryInterval_set, + .igmp_queryInterval_get = dal_rtl8367c_igmp_queryInterval_get, + .igmp_robustness_set = dal_rtl8367c_igmp_robustness_set, + .igmp_robustness_get = dal_rtl8367c_igmp_robustness_get, + .igmp_dynamicRouterPortAllow_set = dal_rtl8367c_igmp_dynamicRouterPortAllow_set, + .igmp_dynamicRouterPortAllow_get = dal_rtl8367c_igmp_dynamicRouterPortAllow_get, + .igmp_dynamicRouterPort_get = dal_rtl8367c_igmp_dynamicRouterPort_get, + .igmp_suppressionEnable_set = dal_rtl8367c_igmp_suppressionEnable_set, + .igmp_suppressionEnable_get = dal_rtl8367c_igmp_suppressionEnable_get, + .igmp_portRxPktEnable_set = dal_rtl8367c_igmp_portRxPktEnable_set, + .igmp_portRxPktEnable_get = dal_rtl8367c_igmp_portRxPktEnable_get, + .igmp_groupInfo_get = dal_rtl8367c_igmp_groupInfo_get, + .igmp_ReportLeaveFwdAction_set = dal_rtl8367c_igmp_ReportLeaveFwdAction_set, + .igmp_ReportLeaveFwdAction_get = dal_rtl8367c_igmp_ReportLeaveFwdAction_get, + .igmp_dropLeaveZeroEnable_set = dal_rtl8367c_igmp_dropLeaveZeroEnable_set, + .igmp_dropLeaveZeroEnable_get = dal_rtl8367c_igmp_dropLeaveZeroEnable_get, + .igmp_bypassGroupRange_set = dal_rtl8367c_igmp_bypassGroupRange_set, + .igmp_bypassGroupRange_get = dal_rtl8367c_igmp_bypassGroupRange_get, + + /* Storm */ + .rate_stormControlMeterIdx_set = dal_rtl8367c_rate_stormControlMeterIdx_set, + .rate_stormControlMeterIdx_get = dal_rtl8367c_rate_stormControlMeterIdx_get, + .rate_stormControlPortEnable_set = dal_rtl8367c_rate_stormControlPortEnable_set, + .rate_stormControlPortEnable_get = dal_rtl8367c_rate_stormControlPortEnable_get, + .storm_bypass_set = dal_rtl8367c_storm_bypass_set, + .storm_bypass_get = dal_rtl8367c_storm_bypass_get, + .rate_stormControlExtPortmask_set = dal_rtl8367c_rate_stormControlExtPortmask_set, + .rate_stormControlExtPortmask_get = dal_rtl8367c_rate_stormControlExtPortmask_get, + .rate_stormControlExtEnable_set = dal_rtl8367c_rate_stormControlExtEnable_set, + .rate_stormControlExtEnable_get = dal_rtl8367c_rate_stormControlExtEnable_get, + .rate_stormControlExtMeterIdx_set = dal_rtl8367c_rate_stormControlExtMeterIdx_set, + .rate_stormControlExtMeterIdx_get = dal_rtl8367c_rate_stormControlExtMeterIdx_get, + + /* Rate */ + .rate_shareMeter_set = dal_rtl8367c_rate_shareMeter_set, + .rate_shareMeter_get = dal_rtl8367c_rate_shareMeter_get, + .rate_shareMeterBucket_set = dal_rtl8367c_rate_shareMeterBucket_set, + .rate_shareMeterBucket_get = dal_rtl8367c_rate_shareMeterBucket_get, + .rate_igrBandwidthCtrlRate_set = dal_rtl8367c_rate_igrBandwidthCtrlRate_set, + .rate_igrBandwidthCtrlRate_get = dal_rtl8367c_rate_igrBandwidthCtrlRate_get, + .rate_egrBandwidthCtrlRate_set = dal_rtl8367c_rate_egrBandwidthCtrlRate_set, + .rate_egrBandwidthCtrlRate_get = dal_rtl8367c_rate_egrBandwidthCtrlRate_get, + .rate_egrQueueBwCtrlEnable_set = dal_rtl8367c_rate_egrQueueBwCtrlEnable_set, + .rate_egrQueueBwCtrlEnable_get = dal_rtl8367c_rate_egrQueueBwCtrlEnable_get, + .rate_egrQueueBwCtrlRate_set = dal_rtl8367c_rate_egrQueueBwCtrlRate_set, + .rate_egrQueueBwCtrlRate_get = dal_rtl8367c_rate_egrQueueBwCtrlRate_get, + + /* I2C */ + .i2c_init = dal_rtl8367c_i2c_init, + .i2c_data_read = dal_rtl8367c_i2c_data_read, + .i2c_data_write = dal_rtl8367c_i2c_data_write, + .i2c_mode_set = dal_rtl8367c_i2c_mode_set, + .i2c_mode_get = dal_rtl8367c_i2c_mode_get, + .i2c_gpioPinGroup_set = dal_rtl8367c_i2c_gpioPinGroup_set, + .i2c_gpioPinGroup_get = dal_rtl8367c_i2c_gpioPinGroup_get, + + /*PTP*/ + .ptp_init = dal_rtl8367c_ptp_init, + .ptp_mac_set = dal_rtl8367c_ptp_mac_set, + .ptp_mac_get = dal_rtl8367c_ptp_mac_get, + .ptp_tpid_set = dal_rtl8367c_ptp_tpid_set, + .ptp_tpid_get = dal_rtl8367c_ptp_tpid_get, + .ptp_refTime_set = dal_rtl8367c_ptp_refTime_set, + .ptp_refTime_get = dal_rtl8367c_ptp_refTime_get, + .ptp_refTimeAdjust_set = dal_rtl8367c_ptp_refTimeAdjust_set, + .ptp_refTimeEnable_set = dal_rtl8367c_ptp_refTimeEnable_set, + .ptp_refTimeEnable_get = dal_rtl8367c_ptp_refTimeEnable_get, + .ptp_portEnable_set = dal_rtl8367c_ptp_portEnable_set, + .ptp_portEnable_get = dal_rtl8367c_ptp_portEnable_get, + .ptp_portTimestamp_get = dal_rtl8367c_ptp_portTimestamp_get, + .ptp_intControl_set = dal_rtl8367c_ptp_intControl_set, + .ptp_intControl_get = dal_rtl8367c_ptp_intControl_get, + .ptp_intStatus_get = dal_rtl8367c_ptp_intStatus_get, + .ptp_portIntStatus_set = dal_rtl8367c_ptp_portIntStatus_set, + .ptp_portIntStatus_get = dal_rtl8367c_ptp_portIntStatus_get, + .ptp_portTrap_set = dal_rtl8367c_ptp_portTrap_set, + .ptp_portTrap_get = dal_rtl8367c_ptp_portTrap_get, + + /*QoS*/ + .qos_init = dal_rtl8367c_qos_init, + .qos_priSel_set = dal_rtl8367c_qos_priSel_set, + .qos_priSel_get = dal_rtl8367c_qos_priSel_get, + .qos_1pPriRemap_set = dal_rtl8367c_qos_1pPriRemap_set, + .qos_1pPriRemap_get = dal_rtl8367c_qos_1pPriRemap_get, + .qos_1pRemarkSrcSel_set = dal_rtl8367c_qos_1pRemarkSrcSel_set, + .qos_1pRemarkSrcSel_get = dal_rtl8367c_qos_1pRemarkSrcSel_get, + .qos_dscpPriRemap_set = dal_rtl8367c_qos_dscpPriRemap_set, + .qos_dscpPriRemap_get = dal_rtl8367c_qos_dscpPriRemap_get, + .qos_portPri_set = dal_rtl8367c_qos_portPri_set, + .qos_portPri_get = dal_rtl8367c_qos_portPri_get, + .qos_queueNum_set = dal_rtl8367c_qos_queueNum_set, + .qos_queueNum_get = dal_rtl8367c_qos_queueNum_get, + .qos_priMap_set = dal_rtl8367c_qos_priMap_set, + .qos_priMap_get = dal_rtl8367c_qos_priMap_get, + .qos_schedulingQueue_set = dal_rtl8367c_qos_schedulingQueue_set, + .qos_schedulingQueue_get = dal_rtl8367c_qos_schedulingQueue_get, + .qos_1pRemarkEnable_set = dal_rtl8367c_qos_1pRemarkEnable_set, + .qos_1pRemarkEnable_get = dal_rtl8367c_qos_1pRemarkEnable_get, + .qos_1pRemark_set = dal_rtl8367c_qos_1pRemark_set, + .qos_1pRemark_get = dal_rtl8367c_qos_1pRemark_get, + .qos_dscpRemarkEnable_set = dal_rtl8367c_qos_dscpRemarkEnable_set, + .qos_dscpRemarkEnable_get = dal_rtl8367c_qos_dscpRemarkEnable_get, + .qos_dscpRemark_set = dal_rtl8367c_qos_dscpRemark_set, + .qos_dscpRemark_get = dal_rtl8367c_qos_dscpRemark_get, + .qos_dscpRemarkSrcSel_set = dal_rtl8367c_qos_dscpRemarkSrcSel_set, + .qos_dscpRemarkSrcSel_get = dal_rtl8367c_qos_dscpRemarkSrcSel_get, + .qos_dscpRemark2Dscp_set = dal_rtl8367c_qos_dscpRemark2Dscp_set, + .qos_dscpRemark2Dscp_get = dal_rtl8367c_qos_dscpRemark2Dscp_get, + .qos_portPriSelIndex_set = dal_rtl8367c_qos_portPriSelIndex_set, + .qos_portPriSelIndex_get = dal_rtl8367c_qos_portPriSelIndex_get, + .qos_schedulingType_set = NULL, + .qos_schedulingType_get = NULL, + + /*VLAN*/ + .vlan_init = dal_rtl8367c_vlan_init, + .vlan_set = dal_rtl8367c_vlan_set, + .vlan_get = dal_rtl8367c_vlan_get, + .vlan_egrFilterEnable_set = dal_rtl8367c_vlan_egrFilterEnable_set, + .vlan_egrFilterEnable_get = dal_rtl8367c_vlan_egrFilterEnable_get, + .vlan_mbrCfg_set = dal_rtl8367c_vlan_mbrCfg_set, + .vlan_mbrCfg_get = dal_rtl8367c_vlan_mbrCfg_get, + .vlan_portPvid_set = dal_rtl8367c_vlan_portPvid_set, + .vlan_portPvid_get = dal_rtl8367c_vlan_portPvid_get, + .vlan_portIgrFilterEnable_set = dal_rtl8367c_vlan_portIgrFilterEnable_set, + .vlan_portIgrFilterEnable_get = dal_rtl8367c_vlan_portIgrFilterEnable_get, + .vlan_portAcceptFrameType_set = dal_rtl8367c_vlan_portAcceptFrameType_set, + .vlan_portAcceptFrameType_get = dal_rtl8367c_vlan_portAcceptFrameType_get, + .vlan_tagMode_set = dal_rtl8367c_vlan_tagMode_set, + .vlan_tagMode_get = dal_rtl8367c_vlan_tagMode_get, + .vlan_transparent_set = dal_rtl8367c_vlan_transparent_set, + .vlan_transparent_get = dal_rtl8367c_vlan_transparent_get, + .vlan_keep_set = dal_rtl8367c_vlan_keep_set, + .vlan_keep_get = dal_rtl8367c_vlan_keep_get, + .vlan_stg_set = dal_rtl8367c_vlan_stg_set, + .vlan_stg_get = dal_rtl8367c_vlan_stg_get, + .vlan_protoAndPortBasedVlan_add = dal_rtl8367c_vlan_protoAndPortBasedVlan_add, + .vlan_protoAndPortBasedVlan_get = dal_rtl8367c_vlan_protoAndPortBasedVlan_get, + .vlan_protoAndPortBasedVlan_del = dal_rtl8367c_vlan_protoAndPortBasedVlan_del, + .vlan_protoAndPortBasedVlan_delAll = dal_rtl8367c_vlan_protoAndPortBasedVlan_delAll, + .vlan_portFid_set = dal_rtl8367c_vlan_portFid_set, + .vlan_portFid_get = dal_rtl8367c_vlan_portFid_get, + .vlan_UntagDscpPriorityEnable_set = dal_rtl8367c_vlan_UntagDscpPriorityEnable_set, + .vlan_UntagDscpPriorityEnable_get = dal_rtl8367c_vlan_UntagDscpPriorityEnable_get, + .stp_mstpState_set = dal_rtl8367c_stp_mstpState_set, + .stp_mstpState_get = dal_rtl8367c_stp_mstpState_get, + .vlan_reservedVidAction_set = dal_rtl8367c_vlan_reservedVidAction_set, + .vlan_reservedVidAction_get = dal_rtl8367c_vlan_reservedVidAction_get, + .vlan_realKeepRemarkEnable_set = dal_rtl8367c_vlan_realKeepRemarkEnable_set, + .vlan_realKeepRemarkEnable_get = dal_rtl8367c_vlan_realKeepRemarkEnable_get, + .vlan_reset = dal_rtl8367c_vlan_reset, + + /*dot1x*/ + .dot1x_unauthPacketOper_set = dal_rtl8367c_dot1x_unauthPacketOper_set, + .dot1x_unauthPacketOper_get = dal_rtl8367c_dot1x_unauthPacketOper_get, + .dot1x_eapolFrame2CpuEnable_set = dal_rtl8367c_dot1x_eapolFrame2CpuEnable_set, + .dot1x_eapolFrame2CpuEnable_get = dal_rtl8367c_dot1x_eapolFrame2CpuEnable_get, + .dot1x_portBasedEnable_set = dal_rtl8367c_dot1x_portBasedEnable_set, + .dot1x_portBasedEnable_get = dal_rtl8367c_dot1x_portBasedEnable_get, + .dot1x_portBasedAuthStatus_set = dal_rtl8367c_dot1x_portBasedAuthStatus_set, + .dot1x_portBasedAuthStatus_get = dal_rtl8367c_dot1x_portBasedAuthStatus_get, + .dot1x_portBasedDirection_set = dal_rtl8367c_dot1x_portBasedDirection_set, + .dot1x_portBasedDirection_get = dal_rtl8367c_dot1x_portBasedDirection_get, + .dot1x_macBasedEnable_set = dal_rtl8367c_dot1x_macBasedEnable_set, + .dot1x_macBasedEnable_get = dal_rtl8367c_dot1x_macBasedEnable_get, + .dot1x_macBasedAuthMac_add = dal_rtl8367c_dot1x_macBasedAuthMac_add, + .dot1x_macBasedAuthMac_del = dal_rtl8367c_dot1x_macBasedAuthMac_del, + .dot1x_macBasedDirection_set = dal_rtl8367c_dot1x_macBasedDirection_set, + .dot1x_macBasedDirection_get = dal_rtl8367c_dot1x_macBasedDirection_get, + .dot1x_guestVlan_set = dal_rtl8367c_dot1x_guestVlan_set, + .dot1x_guestVlan_get = dal_rtl8367c_dot1x_guestVlan_get, + .dot1x_guestVlan2Auth_set = dal_rtl8367c_dot1x_guestVlan2Auth_set, + .dot1x_guestVlan2Auth_get = dal_rtl8367c_dot1x_guestVlan2Auth_get, + + /*SVLAN*/ + .svlan_init = dal_rtl8367c_svlan_init, + .svlan_servicePort_add = dal_rtl8367c_svlan_servicePort_add, + .svlan_servicePort_get = dal_rtl8367c_svlan_servicePort_get, + .svlan_servicePort_del = dal_rtl8367c_svlan_servicePort_del, + .svlan_tpidEntry_set = dal_rtl8367c_svlan_tpidEntry_set, + .svlan_tpidEntry_get = dal_rtl8367c_svlan_tpidEntry_get, + .svlan_priorityRef_set = dal_rtl8367c_svlan_priorityRef_set, + .svlan_priorityRef_get = dal_rtl8367c_svlan_priorityRef_get, + .svlan_memberPortEntry_set = dal_rtl8367c_svlan_memberPortEntry_set, + .svlan_memberPortEntry_get = dal_rtl8367c_svlan_memberPortEntry_get, + .svlan_memberPortEntry_adv_set = dal_rtl8367c_svlan_memberPortEntry_adv_set, + .svlan_memberPortEntry_adv_get = dal_rtl8367c_svlan_memberPortEntry_adv_get, + .svlan_defaultSvlan_set = dal_rtl8367c_svlan_defaultSvlan_set, + .svlan_defaultSvlan_get = dal_rtl8367c_svlan_defaultSvlan_get, + .svlan_c2s_add = dal_rtl8367c_svlan_c2s_add, + .svlan_c2s_del = dal_rtl8367c_svlan_c2s_del, + .svlan_c2s_get = dal_rtl8367c_svlan_c2s_get, + .svlan_untag_action_set = dal_rtl8367c_svlan_untag_action_set, + .svlan_untag_action_get = dal_rtl8367c_svlan_untag_action_get, + .svlan_unmatch_action_set = dal_rtl8367c_svlan_unmatch_action_set, + .svlan_unmatch_action_get = dal_rtl8367c_svlan_unmatch_action_get, + .svlan_dmac_vidsel_set = dal_rtl8367c_svlan_dmac_vidsel_set, + .svlan_dmac_vidsel_get = dal_rtl8367c_svlan_dmac_vidsel_get, + .svlan_ipmc2s_add = dal_rtl8367c_svlan_ipmc2s_add, + .svlan_ipmc2s_del = dal_rtl8367c_svlan_ipmc2s_del, + .svlan_ipmc2s_get = dal_rtl8367c_svlan_ipmc2s_get, + .svlan_l2mc2s_add = dal_rtl8367c_svlan_l2mc2s_add, + .svlan_l2mc2s_del = dal_rtl8367c_svlan_l2mc2s_del, + .svlan_l2mc2s_get = dal_rtl8367c_svlan_l2mc2s_get, + .svlan_sp2c_add = dal_rtl8367c_svlan_sp2c_add, + .svlan_sp2c_get = dal_rtl8367c_svlan_sp2c_get, + .svlan_sp2c_del = dal_rtl8367c_svlan_sp2c_del, + .svlan_lookupType_set = dal_rtl8367c_svlan_lookupType_set, + .svlan_lookupType_get = dal_rtl8367c_svlan_lookupType_get, + .svlan_trapPri_set = dal_rtl8367c_svlan_trapPri_set, + .svlan_trapPri_get = dal_rtl8367c_svlan_trapPri_get, + .svlan_unassign_action_set = dal_rtl8367c_svlan_unassign_action_set, + .svlan_unassign_action_get = dal_rtl8367c_svlan_unassign_action_get, + + /*RLDP*/ + .rldp_config_set = dal_rtl8367c_rldp_config_set, + .rldp_config_get = dal_rtl8367c_rldp_config_get, + .rldp_portConfig_set = dal_rtl8367c_rldp_portConfig_set, + .rldp_portConfig_get = dal_rtl8367c_rldp_portConfig_get, + .rldp_status_get = dal_rtl8367c_rldp_status_get, + .rldp_portStatus_get = dal_rtl8367c_rldp_portStatus_get, + .rldp_portStatus_set = dal_rtl8367c_rldp_portStatus_set, + .rldp_portLoopPair_get = dal_rtl8367c_rldp_portLoopPair_get, + + /*trunk*/ + .trunk_port_set = dal_rtl8367c_trunk_port_set, + .trunk_port_get = dal_rtl8367c_trunk_port_get, + .trunk_distributionAlgorithm_set = dal_rtl8367c_trunk_distributionAlgorithm_set, + .trunk_distributionAlgorithm_get = dal_rtl8367c_trunk_distributionAlgorithm_get, + .trunk_trafficSeparate_set = dal_rtl8367c_trunk_trafficSeparate_set, + .trunk_trafficSeparate_get = dal_rtl8367c_trunk_trafficSeparate_get, + .trunk_mode_set = dal_rtl8367c_trunk_mode_set, + .trunk_mode_get = dal_rtl8367c_trunk_mode_get, + .trunk_trafficPause_set = dal_rtl8367c_trunk_trafficPause_set, + .trunk_trafficPause_get = dal_rtl8367c_trunk_trafficPause_get, + .trunk_hashMappingTable_set = dal_rtl8367c_trunk_hashMappingTable_set, + .trunk_hashMappingTable_get = dal_rtl8367c_trunk_hashMappingTable_get, + .trunk_portQueueEmpty_get = dal_rtl8367c_trunk_portQueueEmpty_get, + + /*leaky*/ + .leaky_vlan_set = dal_rtl8367c_leaky_vlan_set, + .leaky_vlan_get = dal_rtl8367c_leaky_vlan_get, + .leaky_portIsolation_set = dal_rtl8367c_leaky_portIsolation_set, + .leaky_portIsolation_get = dal_rtl8367c_leaky_portIsolation_get, + + /*GPIO*/ + .gpio_input_get = dal_rtl8367c_gpio_input_get, + .gpio_output_set = dal_rtl8367c_gpio_output_set, + .gpio_output_get = dal_rtl8367c_gpio_output_get, + .gpio_state_set = dal_rtl8367c_gpio_state_set, + .gpio_state_get = dal_rtl8367c_gpio_state_get, + .gpio_mode_set = dal_rtl8367c_gpio_mode_set, + .gpio_mode_get = dal_rtl8367c_gpio_mode_get, + .gpio_aclEnClear_set = dal_rtl8367c_gpio_aclEnClear_set, + .gpio_aclEnClear_get = dal_rtl8367c_gpio_aclEnClear_get, + + /*ASIC*/ + .asic_setAsicReg = rtl8367c_setAsicReg, + .asic_getAsicReg = rtl8367c_getAsicReg, + .asic_setAsicPHYOCPReg = rtl8367c_setAsicPHYOCPReg, + .asic_getAsicPHYOCPReg = rtl8367c_getAsicPHYOCPReg, + .asic_setAsicPHYReg = rtl8367c_setAsicPHYReg, + .asic_getAsicPHYReg = rtl8367c_getAsicPHYReg, +}; + +/* + * Macro Declaration + */ + +/* + * Function Declaration + */ + + +/* Module Name : */ + +/* Function Name: + * dal_rtl8367c_mapper_get + * Description: + * Get DAL mapper function + * Input: + * None + * Output: + * None + * Return: + * dal_mapper_t * - mapper pointer + * Note: + */ +dal_mapper_t *dal_rtl8367c_mapper_get(void) +{ + + return &dal_rtl8367c_mapper; +} /* end of dal_rtl8367c_mapper_get */ + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_mapper.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_mapper.h new file mode 100644 index 00000000..4f9fe4c3 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_mapper.h @@ -0,0 +1,54 @@ + +/* + * Copyright(c) Realtek Semiconductor Corporation, 2011 + * All rights reserved. + * + * Purpose : Enterprise Switch RTK API mapper table + * + * Feature : + * + */ + +#ifndef __DAL_RTL8367C_MAPPER_H__ +#define __DAL_RTL8367C_MAPPER_H__ + +/* + * Include Files + */ +#include +#include +#include + + +/* + * Symbol Definition + */ + +/* + * Data Declaration + */ + +/* + * Macro Declaration + */ + +/* + * Function Declaration + */ + + +/* Function Name: + * dal_rtl8367c_mapper_get + * Description: + * Get DAL mapper function + * Input: + * None + * Output: + * None + * Return: + * dal_mapper_t * - mapper pointer + * Note: + */ +extern dal_mapper_t *dal_rtl8367c_mapper_get(void); + +#endif /* __DAL_RTL8367C_MAPPER_H__ */ diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_mirror.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_mirror.c new file mode 100644 index 00000000..7e3165df --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_mirror.c @@ -0,0 +1,552 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8367C + * Feature : Here is a list of all functions and variables in Mirror module. + * + */ + +#include +#include +#include +#include +#include +#include + +/* Function Name: + * dal_rtl8367c_mirror_portBased_set + * Description: + * Set port mirror function. + * Input: + * mirroring_port - Monitor port. + * pMirrored_rx_portmask - Rx mirror port mask. + * pMirrored_tx_portmask - Tx mirror port mask. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * RT_ERR_PORT_MASK - Invalid portmask. + * Note: + * The API is to set mirror function of source port and mirror port. + * The mirror port can only be set to one port and the TX and RX mirror ports + * should be identical. + */ +rtk_api_ret_t dal_rtl8367c_mirror_portBased_set(rtk_port_t mirroring_port, rtk_portmask_t *pMirrored_rx_portmask, rtk_portmask_t *pMirrored_tx_portmask) +{ + rtk_api_ret_t retVal; + rtk_enable_t mirRx, mirTx; + rtk_uint32 i, pmask; + rtk_port_t source_port; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check port valid */ + RTK_CHK_PORT_VALID(mirroring_port); + + if(NULL == pMirrored_rx_portmask) + return RT_ERR_NULL_POINTER; + + if(NULL == pMirrored_tx_portmask) + return RT_ERR_NULL_POINTER; + + RTK_CHK_PORTMASK_VALID(pMirrored_rx_portmask); + + RTK_CHK_PORTMASK_VALID(pMirrored_tx_portmask); + + /*Mirror Sorce Port Mask Check*/ + if (pMirrored_tx_portmask->bits[0]!=pMirrored_rx_portmask->bits[0]&&pMirrored_tx_portmask->bits[0]!=0&&pMirrored_rx_portmask->bits[0]!=0) + return RT_ERR_PORT_MASK; + + /*mirror port != source port*/ + if(RTK_PORTMASK_IS_PORT_SET((*pMirrored_tx_portmask), mirroring_port) || RTK_PORTMASK_IS_PORT_SET((*pMirrored_rx_portmask), mirroring_port)) + return RT_ERR_PORT_MASK; + + source_port = rtk_switch_maxLogicalPort_get(); + + RTK_SCAN_ALL_LOG_PORT(i) + { + if (pMirrored_tx_portmask->bits[0]&(1<bits[0]&(1<bits[0] != 0) + { + if ((retVal = rtk_switch_portmask_L2P_get(pMirrored_rx_portmask, &pmask)) != RT_ERR_OK) + return retVal; + if ((retVal = rtl8367c_setAsicPortMirrorMask(pmask)) != RT_ERR_OK) + return retVal; + } + else + { + if ((retVal = rtk_switch_portmask_L2P_get(pMirrored_tx_portmask, &pmask)) != RT_ERR_OK) + return retVal; + if ((retVal = rtl8367c_setAsicPortMirrorMask(pmask)) != RT_ERR_OK) + return retVal; + } + + + if (pMirrored_rx_portmask->bits[0]) + mirRx = ENABLED; + else + mirRx = DISABLED; + + if ((retVal = rtl8367c_setAsicPortMirrorRxFunction(mirRx)) != RT_ERR_OK) + return retVal; + + if (pMirrored_tx_portmask->bits[0]) + mirTx = ENABLED; + else + mirTx = DISABLED; + + if ((retVal = rtl8367c_setAsicPortMirrorTxFunction(mirTx)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; + +} + +/* Function Name: + * dal_rtl8367c_mirror_portBased_get + * Description: + * Get port mirror function. + * Input: + * None + * Output: + * pMirroring_port - Monitor port. + * pMirrored_rx_portmask - Rx mirror port mask. + * pMirrored_tx_portmask - Tx mirror port mask. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API is to get mirror function of source port and mirror port. + */ +rtk_api_ret_t dal_rtl8367c_mirror_portBased_get(rtk_port_t *pMirroring_port, rtk_portmask_t *pMirrored_rx_portmask, rtk_portmask_t *pMirrored_tx_portmask) +{ + rtk_api_ret_t retVal; + rtk_port_t source_port; + rtk_enable_t mirRx, mirTx; + rtk_uint32 sport, mport, pmask; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pMirrored_rx_portmask) + return RT_ERR_NULL_POINTER; + + if(NULL == pMirrored_tx_portmask) + return RT_ERR_NULL_POINTER; + + if(NULL == pMirroring_port) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicPortMirror(&sport, &mport)) != RT_ERR_OK) + return retVal; + source_port = rtk_switch_port_P2L_get(sport); + *pMirroring_port = rtk_switch_port_P2L_get(mport); + + if ((retVal = rtl8367c_getAsicPortMirrorRxFunction((rtk_uint32*)&mirRx)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_getAsicPortMirrorTxFunction((rtk_uint32*)&mirTx)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_getAsicPortMirrorMask(&pmask)) != RT_ERR_OK) + return retVal; + + if (DISABLED == mirRx) + pMirrored_rx_portmask->bits[0]=0; + else + { + if ((retVal = rtk_switch_portmask_P2L_get(pmask, pMirrored_rx_portmask)) != RT_ERR_OK) + return retVal; + pMirrored_rx_portmask->bits[0] |= 1<bits[0]=0; + else + { + if ((retVal = rtk_switch_portmask_P2L_get(pmask, pMirrored_tx_portmask)) != RT_ERR_OK) + return retVal; + pMirrored_tx_portmask->bits[0] |= 1<= RTK_ENABLE_END) + return RT_ERR_ENABLE; + + if ((retVal = rtl8367c_setAsicPortMirrorIsolation(enable)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_mirror_portIso_get + * Description: + * Get mirror port isolation. + * Input: + * None + * Output: + * pEnable |Mirror isolation status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API is to get mirror isolation status. + */ +rtk_api_ret_t dal_rtl8367c_mirror_portIso_get(rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pEnable) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicPortMirrorIsolation(pEnable)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_mirror_vlanLeaky_set + * Description: + * Set mirror VLAN leaky. + * Input: + * txenable -TX leaky enable. + * rxenable - RX leaky enable. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid enable input + * Note: + * The API is to set mirror VLAN leaky function forwarding packets to miror port. + */ +rtk_api_ret_t dal_rtl8367c_mirror_vlanLeaky_set(rtk_enable_t txenable, rtk_enable_t rxenable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if ((txenable >= RTK_ENABLE_END) ||(rxenable >= RTK_ENABLE_END)) + return RT_ERR_ENABLE; + + if ((retVal = rtl8367c_setAsicPortMirrorVlanTxLeaky(txenable)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicPortMirrorVlanRxLeaky(rxenable)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_mirror_vlanLeaky_get + * Description: + * Get mirror VLAN leaky. + * Input: + * None + * Output: + * pTxenable - TX leaky enable. + * pRxenable - RX leaky enable. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API is to get mirror VLAN leaky status. + */ +rtk_api_ret_t dal_rtl8367c_mirror_vlanLeaky_get(rtk_enable_t *pTxenable, rtk_enable_t *pRxenable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if( (NULL == pTxenable) || (NULL == pRxenable) ) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicPortMirrorVlanTxLeaky(pTxenable)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_getAsicPortMirrorVlanRxLeaky(pRxenable)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_mirror_isolationLeaky_set + * Description: + * Set mirror Isolation leaky. + * Input: + * txenable -TX leaky enable. + * rxenable - RX leaky enable. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid enable input + * Note: + * The API is to set mirror VLAN leaky function forwarding packets to miror port. + */ +rtk_api_ret_t dal_rtl8367c_mirror_isolationLeaky_set(rtk_enable_t txenable, rtk_enable_t rxenable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if ((txenable >= RTK_ENABLE_END) ||(rxenable >= RTK_ENABLE_END)) + return RT_ERR_ENABLE; + + if ((retVal = rtl8367c_setAsicPortMirrorIsolationTxLeaky(txenable)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicPortMirrorIsolationRxLeaky(rxenable)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_mirror_isolationLeaky_get + * Description: + * Get mirror isolation leaky. + * Input: + * None + * Output: + * pTxenable - TX leaky enable. + * pRxenable - RX leaky enable. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API is to get mirror isolation leaky status. + */ +rtk_api_ret_t dal_rtl8367c_mirror_isolationLeaky_get(rtk_enable_t *pTxenable, rtk_enable_t *pRxenable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if( (NULL == pTxenable) || (NULL == pRxenable) ) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicPortMirrorIsolationTxLeaky(pTxenable)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_getAsicPortMirrorIsolationRxLeaky(pRxenable)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_mirror_keep_set + * Description: + * Set mirror packet format keep. + * Input: + * mode - -mirror keep mode. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid enable input + * Note: + * The API is to set -mirror keep mode. + * The mirror keep mode is as following: + * - MIRROR_FOLLOW_VLAN + * - MIRROR_KEEP_ORIGINAL + * - MIRROR_KEEP_END + */ +rtk_api_ret_t dal_rtl8367c_mirror_keep_set(rtk_mirror_keep_t mode) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (mode >= MIRROR_KEEP_END) + return RT_ERR_ENABLE; + + if ((retVal = rtl8367c_setAsicPortMirrorRealKeep(mode)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_mirror_keep_get + * Description: + * Get mirror packet format keep. + * Input: + * None + * Output: + * pMode -mirror keep mode. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API is to get mirror keep mode. + * The mirror keep mode is as following: + * - MIRROR_FOLLOW_VLAN + * - MIRROR_KEEP_ORIGINAL + * - MIRROR_KEEP_END + */ +rtk_api_ret_t dal_rtl8367c_mirror_keep_get(rtk_mirror_keep_t *pMode) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pMode) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicPortMirrorRealKeep(pMode)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_mirror_override_set + * Description: + * Set port mirror override function. + * Input: + * rxMirror - 1: output mirrored packet, 0: output normal forward packet + * txMirror - 1: output mirrored packet, 0: output normal forward packet + * aclMirror - 1: output mirrored packet, 0: output normal forward packet + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API is to set mirror override function. + * This function control the output format when a port output + * normal forward & mirrored packet at the same time. + */ +rtk_api_ret_t dal_rtl8367c_mirror_override_set(rtk_enable_t rxMirror, rtk_enable_t txMirror, rtk_enable_t aclMirror) +{ + rtk_api_ret_t retVal; + + if( (rxMirror >= RTK_ENABLE_END) || (txMirror >= RTK_ENABLE_END) || (aclMirror >= RTK_ENABLE_END)) + return RT_ERR_ENABLE; + + if ((retVal = rtl8367c_setAsicPortMirrorOverride((rtk_uint32)rxMirror, (rtk_uint32)txMirror, (rtk_uint32)aclMirror)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_mirror_override_get + * Description: + * Get port mirror override function. + * Input: + * None + * Output: + * pRxMirror - 1: output mirrored packet, 0: output normal forward packet + * pTxMirror - 1: output mirrored packet, 0: output normal forward packet + * pAclMirror - 1: output mirrored packet, 0: output normal forward packet + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Null Pointer + * Note: + * The API is to Get mirror override function. + * This function control the output format when a port output + * normal forward & mirrored packet at the same time. + */ +rtk_api_ret_t dal_rtl8367c_mirror_override_get(rtk_enable_t *pRxMirror, rtk_enable_t *pTxMirror, rtk_enable_t *pAclMirror) +{ + rtk_api_ret_t retVal; + + if( (pRxMirror == NULL) || (pTxMirror == NULL) || (pAclMirror == NULL)) + return RT_ERR_ENABLE; + + if ((retVal = rtl8367c_getAsicPortMirrorOverride((rtk_uint32 *)pRxMirror, (rtk_uint32 *)pTxMirror, (rtk_uint32 *)pAclMirror)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_mirror.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_mirror.h new file mode 100644 index 00000000..48e84c5f --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_mirror.h @@ -0,0 +1,268 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8367/RTL8367C switch high-level API + * + * Feature : The file includes Mirror module high-layer API defination + * + */ + +#ifndef __DAL_RTL8367C_MIRROR_H__ +#define __DAL_RTL8367C_MIRROR_H__ + +#include + +/* Function Name: + * dal_rtl8367c_mirror_portBased_set + * Description: + * Set port mirror function. + * Input: + * mirroring_port - Monitor port. + * pMirrored_rx_portmask - Rx mirror port mask. + * pMirrored_tx_portmask - Tx mirror port mask. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * RT_ERR_PORT_MASK - Invalid portmask. + * Note: + * The API is to set mirror function of source port and mirror port. + * The mirror port can only be set to one port and the TX and RX mirror ports + * should be identical. + */ +extern rtk_api_ret_t dal_rtl8367c_mirror_portBased_set(rtk_port_t mirroring_port, rtk_portmask_t *pMirrored_rx_portmask, rtk_portmask_t *pMirrored_tx_portmask); + +/* Function Name: + * dal_rtl8367c_mirror_portBased_get + * Description: + * Get port mirror function. + * Input: + * None + * Output: + * pMirroring_port - Monitor port. + * pMirrored_rx_portmask - Rx mirror port mask. + * pMirrored_tx_portmask - Tx mirror port mask. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API is to get mirror function of source port and mirror port. + */ +extern rtk_api_ret_t dal_rtl8367c_mirror_portBased_get(rtk_port_t* pMirroring_port, rtk_portmask_t *pMirrored_rx_portmask, rtk_portmask_t *pMirrored_tx_portmask); + +/* Function Name: + * dal_rtl8367c_mirror_portIso_set + * Description: + * Set mirror port isolation. + * Input: + * enable |Mirror isolation status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid enable input + * Note: + * The API is to set mirror isolation function that prevent normal forwarding packets to miror port. + */ +extern rtk_api_ret_t dal_rtl8367c_mirror_portIso_set(rtk_enable_t enable); + +/* Function Name: + * dal_rtl8367c_mirror_portIso_get + * Description: + * Get mirror port isolation. + * Input: + * None + * Output: + * pEnable |Mirror isolation status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API is to get mirror isolation status. + */ +extern rtk_api_ret_t dal_rtl8367c_mirror_portIso_get(rtk_enable_t *pEnable); + +/* Function Name: + * dal_rtl8367c_mirror_vlanLeaky_set + * Description: + * Set mirror VLAN leaky. + * Input: + * txenable -TX leaky enable. + * rxenable - RX leaky enable. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid enable input + * Note: + * The API is to set mirror VLAN leaky function forwarding packets to miror port. + */ +extern rtk_api_ret_t dal_rtl8367c_mirror_vlanLeaky_set(rtk_enable_t txenable, rtk_enable_t rxenable); + + +/* Function Name: + * dal_rtl8367c_mirror_vlanLeaky_get + * Description: + * Get mirror VLAN leaky. + * Input: + * None + * Output: + * pTxenable - TX leaky enable. + * pRxenable - RX leaky enable. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API is to get mirror VLAN leaky status. + */ +extern rtk_api_ret_t dal_rtl8367c_mirror_vlanLeaky_get(rtk_enable_t *pTxenable, rtk_enable_t *pRxenable); + +/* Function Name: + * dal_rtl8367c_mirror_isolationLeaky_set + * Description: + * Set mirror Isolation leaky. + * Input: + * txenable -TX leaky enable. + * rxenable - RX leaky enable. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid enable input + * Note: + * The API is to set mirror VLAN leaky function forwarding packets to miror port. + */ +extern rtk_api_ret_t dal_rtl8367c_mirror_isolationLeaky_set(rtk_enable_t txenable, rtk_enable_t rxenable); + +/* Function Name: + * dal_rtl8367c_mirror_isolationLeaky_get + * Description: + * Get mirror isolation leaky. + * Input: + * None + * Output: + * pTxenable - TX leaky enable. + * pRxenable - RX leaky enable. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API is to get mirror isolation leaky status. + */ +extern rtk_api_ret_t dal_rtl8367c_mirror_isolationLeaky_get(rtk_enable_t *pTxenable, rtk_enable_t *pRxenable); + +/* Function Name: + * dal_rtl8367c_mirror_keep_set + * Description: + * Set mirror packet format keep. + * Input: + * mode - -mirror keep mode. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid enable input + * Note: + * The API is to set -mirror keep mode. + * The mirror keep mode is as following: + * - MIRROR_FOLLOW_VLAN + * - MIRROR_KEEP_ORIGINAL + * - MIRROR_KEEP_END + */ +extern rtk_api_ret_t dal_rtl8367c_mirror_keep_set(rtk_mirror_keep_t mode); + + +/* Function Name: + * dal_rtl8367c_mirror_keep_get + * Description: + * Get mirror packet format keep. + * Input: + * None + * Output: + * pMode -mirror keep mode. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API is to get mirror keep mode. + * The mirror keep mode is as following: + * - MIRROR_FOLLOW_VLAN + * - MIRROR_KEEP_ORIGINAL + * - MIRROR_KEEP_END + */ +extern rtk_api_ret_t dal_rtl8367c_mirror_keep_get(rtk_mirror_keep_t *pMode); + +/* Function Name: + * dal_rtl8367c_mirror_override_set + * Description: + * Set port mirror override function. + * Input: + * rxMirror - 1: output mirrored packet, 0: output normal forward packet + * txMirror - 1: output mirrored packet, 0: output normal forward packet + * aclMirror - 1: output mirrored packet, 0: output normal forward packet + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API is to set mirror override function. + * This function control the output format when a port output + * normal forward & mirrored packet at the same time. + */ +extern rtk_api_ret_t dal_rtl8367c_mirror_override_set(rtk_enable_t rxMirror, rtk_enable_t txMirror, rtk_enable_t aclMirror); + +/* Function Name: + * dal_rtl8367c_mirror_override_get + * Description: + * Get port mirror override function. + * Input: + * None + * Output: + * pRxMirror - 1: output mirrored packet, 0: output normal forward packet + * pTxMirror - 1: output mirrored packet, 0: output normal forward packet + * pAclMirror - 1: output mirrored packet, 0: output normal forward packet + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Null Pointer + * Note: + * The API is to Get mirror override function. + * This function control the output format when a port output + * normal forward & mirrored packet at the same time. + */ +extern rtk_api_ret_t dal_rtl8367c_mirror_override_get(rtk_enable_t *pRxMirror, rtk_enable_t *pTxMirror, rtk_enable_t *pAclMirror); + +#endif /* __DAL_RTL8367C_MIRROR_H__ */ + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_oam.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_oam.c new file mode 100644 index 00000000..8e03692a --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_oam.c @@ -0,0 +1,243 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8367C + * Feature : Here is a list of all functions and variables in OAM(802.3ah) module. + * + */ + +#include +#include +#include + +#include + +#include +#include + + +/* Module Name : OAM */ + +/* Function Name: + * dal_rtl8367c_oam_init + * Description: + * Initialize oam module. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * Note: + * Must initialize oam module before calling any oam APIs. + */ +rtk_api_ret_t dal_rtl8367c_oam_init(void) +{ + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_oam_state_set + * Description: + * This API set OAM state. + * Input: + * enabled -OAMstate + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error parameter + * Note: + * This API set OAM state. + */ +rtk_api_ret_t dal_rtl8367c_oam_state_set(rtk_enable_t enabled) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (enabled >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if ((retVal = rtl8367c_setAsicOamEnable(enabled))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_oam_state_get + * Description: + * This API get OAM state. + * Input: + * None. + * Output: + * pEnabled - H/W IGMP state + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error parameter + * Note: + * This API set current OAM state. + */ +rtk_api_ret_t dal_rtl8367c_oam_state_get(rtk_enable_t *pEnabled) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if ((retVal = rtl8367c_getAsicOamEnable(pEnabled))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_oam_parserAction_set + * Description: + * Set OAM parser action + * Input: + * port - port id + * action - parser action + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - invalid port id + * Note: + * None + */ +rtk_api_ret_t dal_rtl8367c_oam_parserAction_set(rtk_port_t port, rtk_oam_parser_act_t action) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if (action >= OAM_PARSER_ACTION_END) + return RT_ERR_INPUT; + + if ((retVal = rtl8367c_setAsicOamParser(rtk_switch_port_L2P_get(port), action))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_oam_parserAction_set + * Description: + * Get OAM parser action + * Input: + * port - port id + * Output: + * pAction - parser action + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - invalid port id + * Note: + * None + */ +rtk_api_ret_t dal_rtl8367c_oam_parserAction_get(rtk_port_t port, rtk_oam_parser_act_t *pAction) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if ((retVal = rtl8367c_getAsicOamParser(rtk_switch_port_L2P_get(port), pAction))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_oam_multiplexerAction_set + * Description: + * Set OAM multiplexer action + * Input: + * port - port id + * action - parser action + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - invalid port id + * Note: + * None + */ +rtk_api_ret_t dal_rtl8367c_oam_multiplexerAction_set(rtk_port_t port, rtk_oam_multiplexer_act_t action) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if (action >= OAM_MULTIPLEXER_ACTION_END) + return RT_ERR_INPUT; + + if ((retVal = rtl8367c_setAsicOamMultiplexer(rtk_switch_port_L2P_get(port), action))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_oam_parserAction_set + * Description: + * Get OAM multiplexer action + * Input: + * port - port id + * Output: + * pAction - parser action + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - invalid port id + * Note: + * None + */ +rtk_api_ret_t dal_rtl8367c_oam_multiplexerAction_get(rtk_port_t port, rtk_oam_multiplexer_act_t *pAction) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if ((retVal = rtl8367c_getAsicOamMultiplexer(rtk_switch_port_L2P_get(port), pAction))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_oam.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_oam.h new file mode 100644 index 00000000..2fdae715 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_oam.h @@ -0,0 +1,173 @@ +/* + * Copyright (C) 2012 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTL8367/RTL8367C switch high-level API + * + * Feature : The file includes the following modules and sub-modules + * (1) OAM (802.3ah) configuration + * + */ + +#ifndef __DAL_RTL8367C_OAM_H__ +#define __DAL_RTL8367C_OAM_H__ + +#include +/* + * Symbol Definition + */ + + +/* + * Data Declaration + */ + + +/* + * Macro Declaration + */ + + +/* + * Function Declaration + */ + +/* Function Name: + * dal_rtl8367c_oam_init + * Description: + * Initialize oam module. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * Note: + * Must initialize oam module before calling any oam APIs. + */ +extern rtk_api_ret_t dal_rtl8367c_oam_init(void); + +/* Function Name: + * dal_rtl8367c_oam_state_set + * Description: + * This API set OAM state. + * Input: + * enabled -OAMstate + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error parameter + * Note: + * This API set OAM state. + */ +extern rtk_api_ret_t dal_rtl8367c_oam_state_set(rtk_enable_t enabled); + +/* Function Name: + * dal_rtl8367c_oam_state_get + * Description: + * This API get OAM state. + * Input: + * None. + * Output: + * pEnabled - H/W IGMP state + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error parameter + * Note: + * This API set current OAM state. + */ +extern rtk_api_ret_t dal_rtl8367c_oam_state_get(rtk_enable_t *pEnabled); + + +/* Module Name : OAM */ + +/* Function Name: + * dal_rtl8367c_oam_parserAction_set + * Description: + * Set OAM parser action + * Input: + * port - port id + * action - parser action + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - invalid port id + * Note: + * None + */ +extern rtk_api_ret_t dal_rtl8367c_oam_parserAction_set(rtk_port_t port, rtk_oam_parser_act_t action); + +/* Function Name: + * dal_rtl8367c_oam_parserAction_set + * Description: + * Get OAM parser action + * Input: + * port - port id + * Output: + * pAction - parser action + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - invalid port id + * Note: + * None + */ +extern rtk_api_ret_t dal_rtl8367c_oam_parserAction_get(rtk_port_t port, rtk_oam_parser_act_t *pAction); + + +/* Function Name: + * dal_rtl8367c_oam_multiplexerAction_set + * Description: + * Set OAM multiplexer action + * Input: + * port - port id + * action - parser action + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - invalid port id + * Note: + * None + */ +extern rtk_api_ret_t dal_rtl8367c_oam_multiplexerAction_set(rtk_port_t port, rtk_oam_multiplexer_act_t action); + +/* Function Name: + * dal_rtl8367c_oam_multiplexerAction_set + * Description: + * Get OAM multiplexer action + * Input: + * port - port id + * Output: + * pAction - parser action + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - invalid port id + * Note: + * None + */ +extern rtk_api_ret_t dal_rtl8367c_oam_multiplexerAction_get(rtk_port_t port, rtk_oam_multiplexer_act_t *pAction); + + +#endif /* __DAL_RTL8367C_OAM_H__ */ + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_port.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_port.c new file mode 100644 index 00000000..823a11d8 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_port.c @@ -0,0 +1,3342 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8367C + * Feature : Here is a list of all functions and variables in Port module. + * + */ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + + +#define FIBER_INIT_SIZE 1817 +CONST_T rtk_uint8 Fiber[FIBER_INIT_SIZE] = { +0x02,0x05,0x5C,0xE4,0xF5,0xA8, +0xD2,0xAF,0x22,0x00,0x00,0x02,0x06,0x87, +0xE4,0x90,0x06,0x2A,0xF0,0x90,0x06,0x2D, +0xF0,0xFD,0x7C,0x01,0x7F,0x3F,0x7E,0x1D, +0x12,0x06,0xE5,0x7D,0x40,0x12,0x03,0x55, +0x80,0x08,0x12,0x06,0x5B,0x50,0x08,0x12, +0x06,0x48,0x12,0x06,0x6C,0x80,0xF3,0xE4, +0xF5,0xA8,0xD2,0xAF,0x7D,0x1F,0xFC,0x7F, +0x49,0x7E,0x13,0x12,0x06,0xE5,0x12,0x07, +0x0C,0x7D,0xFE,0x7C,0x00,0x7F,0xAA,0x7E, +0x12,0x12,0x06,0xE5,0x7D,0xD7,0x12,0x03, +0x20,0x7D,0x80,0x12,0x02,0xBC,0x7D,0x94, +0x7C,0xF9,0x12,0x03,0x4D,0x7D,0x81,0x12, +0x02,0xBC,0x7D,0xA2,0x7C,0x31,0x12,0x03, +0x4D,0x7D,0x82,0x12,0x02,0xD1,0x7D,0x60, +0x7C,0x69,0x12,0x03,0x63,0x7D,0x83,0x12, +0x02,0xD1,0x7D,0x28,0x7C,0x97,0x12,0x03, +0x63,0x7D,0x84,0x12,0x02,0xE6,0x7D,0x85, +0x7C,0x9D,0x12,0x03,0x7C,0x7D,0x23,0x12, +0x02,0xE6,0x7D,0x10,0x7C,0xD8,0x12,0x03, +0x7C,0x7D,0x24,0x7C,0x04,0x12,0x03,0x3A, +0x7D,0x00,0x12,0x03,0x20,0x7D,0x2F,0x12, +0x02,0xFB,0x7D,0x20,0x7C,0x0F,0x7F,0x02, +0x7E,0x66,0x12,0x06,0xE5,0x7D,0x01,0x12, +0x02,0xFB,0x7D,0x04,0x7C,0x00,0x7F,0x01, +0x7E,0x66,0x12,0x06,0xE5,0x7D,0x80,0x7C, +0x00,0x7F,0x00,0x7E,0x66,0x12,0x06,0xE5, +0x7F,0x02,0x7E,0x66,0x12,0x06,0xC1,0x12, +0x06,0x73,0x44,0x02,0xFF,0x12,0x06,0x73, +0x44,0x04,0x12,0x06,0x7C,0xFD,0x7F,0x02, +0x7E,0x66,0x12,0x06,0xE5,0x7D,0x04,0x7C, +0x00,0x12,0x03,0x3A,0x7D,0xB9,0x7C,0x15, +0x7F,0xEB,0x7E,0x13,0x12,0x06,0xE5,0x7D, +0x07,0x7C,0x00,0x7F,0xE7,0x7E,0x13,0x12, +0x06,0xE5,0x7D,0x40,0x7C,0x11,0x7F,0x00, +0x7E,0x62,0x12,0x06,0xE5,0x12,0x04,0x9D, +0x7D,0x41,0x12,0x03,0x55,0x80,0x08,0x12, +0x06,0x5B,0x50,0x08,0x12,0x06,0x48,0x12, +0x06,0x6C,0x80,0xF3,0xC2,0x00,0xC2,0x01, +0xD2,0xA9,0xD2,0x8C,0x12,0x03,0x2A,0xEE, +0x44,0x18,0x12,0x03,0x6B,0xE4,0xFF,0xFE, +0xFD,0x80,0x0C,0x7F,0xD0,0x7E,0x07,0x12, +0x06,0x5F,0x50,0x08,0x12,0x06,0x48,0x12, +0x06,0x6C,0x80,0xEF,0x7F,0x04,0x7E,0x62, +0x12,0x06,0xC1,0x12,0x06,0x73,0xEE,0x44, +0x01,0xFE,0xEF,0x44,0x80,0x12,0x06,0x7C, +0xFD,0x7F,0x04,0x7E,0x62,0x12,0x06,0xE5, +0xE4,0xFF,0xFE,0xFD,0x80,0x08,0x12,0x06, +0x5B,0x50,0x08,0x12,0x06,0x48,0x12,0x06, +0x6C,0x80,0xF3,0x12,0x03,0x2A,0xEE,0x54, +0xE7,0x12,0x03,0x6B,0x12,0x03,0x10,0x12, +0x03,0x10,0x30,0xE2,0x71,0x90,0x06,0x2D, +0xE0,0x64,0x01,0x70,0x62,0x7F,0xEA,0x7E, +0x13,0x12,0x06,0xC1,0x90,0x06,0x2B,0xEE, +0xF0,0xA3,0xEF,0xF0,0x54,0xEF,0xFF,0x90, +0x06,0x2B,0xEE,0xF0,0xA3,0xEF,0xF0,0xEE, +0x44,0x10,0x90,0x06,0x2B,0xF0,0xFC,0xA3, +0xEF,0xF0,0xFD,0x7F,0x16,0x7E,0x13,0x12, +0x06,0xE5,0xE4,0xFF,0xFE,0xFD,0x80,0x0D, +0xE4,0x7F,0xFF,0x7E,0x6F,0x12,0x06,0x60, +0x50,0x08,0x12,0x06,0x48,0x12,0x06,0x6C, +0x80,0xEE,0x90,0x06,0x2B,0xE0,0x54,0xEF, +0xFE,0xA3,0xE0,0x90,0x06,0x2B,0x12,0x06, +0x7F,0xAD,0x07,0x7F,0x16,0x7E,0x13,0x12, +0x06,0xE5,0xE4,0x90,0x06,0x2D,0xF0,0xE4, +0x90,0x06,0x2A,0xF0,0x80,0x86,0x90,0x06, +0x2A,0xE0,0x70,0x13,0x12,0x02,0x47,0x90, +0x06,0x2A,0x74,0x01,0xF0,0xE4,0x90,0x06, +0x30,0xF0,0xA3,0xF0,0x02,0x01,0x92,0xC3, +0x90,0x06,0x31,0xE0,0x94,0x64,0x90,0x06, +0x30,0xE0,0x94,0x00,0x50,0x03,0x02,0x01, +0x92,0xE4,0xF0,0xA3,0xF0,0x12,0x02,0x47, +0x90,0x06,0x2A,0x74,0x01,0xF0,0x02,0x01, +0x92,0x7F,0x56,0x7E,0x13,0x12,0x06,0xC1, +0x90,0x06,0x2B,0xEE,0xF0,0xA3,0xEF,0xF0, +0x54,0xEF,0xFF,0x90,0x06,0x2B,0xEE,0xF0, +0xA3,0xEF,0xF0,0xEE,0x44,0x10,0x90,0x06, +0x2B,0xF0,0xFC,0xA3,0xEF,0xF0,0xFD,0x7F, +0x16,0x7E,0x13,0x12,0x06,0xE5,0x90,0x06, +0x2D,0x74,0x01,0xF0,0x7D,0x04,0x7C,0x00, +0x7F,0x02,0x7E,0x66,0x12,0x06,0xE5,0x7D, +0x00,0x7C,0x04,0x7F,0x01,0x7E,0x66,0x12, +0x06,0xE5,0x7D,0xC0,0x7C,0x00,0x7F,0x00, +0x7E,0x66,0x12,0x06,0xE5,0xE4,0xFD,0xFC, +0x7F,0x02,0x7E,0x66,0x12,0x06,0xE5,0x7D, +0x00,0x7C,0x04,0x7F,0x01,0x7E,0x66,0x12, +0x06,0xE5,0x7D,0xC0,0x7C,0x00,0x7F,0x00, +0x7E,0x66,0x12,0x06,0xE5,0x22,0x7C,0x04, +0x7F,0x01,0x7E,0x66,0x12,0x06,0xE5,0x7D, +0xC0,0x7C,0x00,0x7F,0x00,0x7E,0x66,0x12, +0x06,0xE5,0x22,0x7C,0x04,0x7F,0x01,0x7E, +0x66,0x12,0x06,0xE5,0x7D,0xC0,0x7C,0x00, +0x7F,0x00,0x7E,0x66,0x12,0x06,0xE5,0x22, +0x7C,0x04,0x7F,0x01,0x7E,0x66,0x12,0x06, +0xE5,0x7D,0xC0,0x7C,0x00,0x7F,0x00,0x7E, +0x66,0x12,0x06,0xE5,0x22,0x7C,0x00,0x7F, +0x01,0x7E,0x66,0x12,0x06,0xE5,0x7D,0xC0, +0x7C,0x00,0x7F,0x00,0x7E,0x66,0x12,0x06, +0xE5,0x22,0x7F,0x01,0x7E,0x62,0x12,0x06, +0xC1,0x90,0x06,0x28,0xEE,0xF0,0xA3,0xEF, +0xF0,0x22,0x7C,0x04,0x7F,0x02,0x7E,0x66, +0x12,0x06,0xE5,0x22,0x7F,0xE7,0x7E,0x13, +0x12,0x06,0xC1,0x90,0x06,0x28,0xEE,0xF0, +0xA3,0xEF,0xF0,0x22,0x7F,0x01,0x7E,0x66, +0x12,0x06,0xE5,0x7D,0xC0,0x7C,0x00,0x7F, +0x00,0x7E,0x66,0x12,0x06,0xE5,0x22,0x7F, +0x02,0x7E,0x66,0x12,0x06,0xE5,0x22,0x7C, +0x00,0x7F,0x36,0x7E,0x13,0x12,0x06,0xE5, +0xE4,0xFF,0xFE,0xFD,0x22,0x7F,0x02,0x7E, +0x66,0x12,0x06,0xE5,0x22,0x90,0x06,0x28, +0xF0,0xFC,0xA3,0xEF,0xF0,0xFD,0x7F,0xE7, +0x7E,0x13,0x12,0x06,0xE5,0x22,0x7F,0x02, +0x7E,0x66,0x12,0x06,0xE5,0x22,0xC5,0xF0, +0xF8,0xA3,0xE0,0x28,0xF0,0xC5,0xF0,0xF8, +0xE5,0x82,0x15,0x82,0x70,0x02,0x15,0x83, +0xE0,0x38,0xF0,0x22,0x75,0xF0,0x08,0x75, +0x82,0x00,0xEF,0x2F,0xFF,0xEE,0x33,0xFE, +0xCD,0x33,0xCD,0xCC,0x33,0xCC,0xC5,0x82, +0x33,0xC5,0x82,0x9B,0xED,0x9A,0xEC,0x99, +0xE5,0x82,0x98,0x40,0x0C,0xF5,0x82,0xEE, +0x9B,0xFE,0xED,0x9A,0xFD,0xEC,0x99,0xFC, +0x0F,0xD5,0xF0,0xD6,0xE4,0xCE,0xFB,0xE4, +0xCD,0xFA,0xE4,0xCC,0xF9,0xA8,0x82,0x22, +0xB8,0x00,0xC1,0xB9,0x00,0x59,0xBA,0x00, +0x2D,0xEC,0x8B,0xF0,0x84,0xCF,0xCE,0xCD, +0xFC,0xE5,0xF0,0xCB,0xF9,0x78,0x18,0xEF, +0x2F,0xFF,0xEE,0x33,0xFE,0xED,0x33,0xFD, +0xEC,0x33,0xFC,0xEB,0x33,0xFB,0x10,0xD7, +0x03,0x99,0x40,0x04,0xEB,0x99,0xFB,0x0F, +0xD8,0xE5,0xE4,0xF9,0xFA,0x22,0x78,0x18, +0xEF,0x2F,0xFF,0xEE,0x33,0xFE,0xED,0x33, +0xFD,0xEC,0x33,0xFC,0xC9,0x33,0xC9,0x10, +0xD7,0x05,0x9B,0xE9,0x9A,0x40,0x07,0xEC, +0x9B,0xFC,0xE9,0x9A,0xF9,0x0F,0xD8,0xE0, +0xE4,0xC9,0xFA,0xE4,0xCC,0xFB,0x22,0x75, +0xF0,0x10,0xEF,0x2F,0xFF,0xEE,0x33,0xFE, +0xED,0x33,0xFD,0xCC,0x33,0xCC,0xC8,0x33, +0xC8,0x10,0xD7,0x07,0x9B,0xEC,0x9A,0xE8, +0x99,0x40,0x0A,0xED,0x9B,0xFD,0xEC,0x9A, +0xFC,0xE8,0x99,0xF8,0x0F,0xD5,0xF0,0xDA, +0xE4,0xCD,0xFB,0xE4,0xCC,0xFA,0xE4,0xC8, +0xF9,0x22,0xEB,0x9F,0xF5,0xF0,0xEA,0x9E, +0x42,0xF0,0xE9,0x9D,0x42,0xF0,0xE8,0x9C, +0x45,0xF0,0x22,0xE0,0xFC,0xA3,0xE0,0xFD, +0xA3,0xE0,0xFE,0xA3,0xE0,0xFF,0x22,0xE0, +0xF8,0xA3,0xE0,0xF9,0xA3,0xE0,0xFA,0xA3, +0xE0,0xFB,0x22,0xEC,0xF0,0xA3,0xED,0xF0, +0xA3,0xEE,0xF0,0xA3,0xEF,0xF0,0x22,0x12, +0x05,0x13,0x12,0x05,0x35,0x44,0x40,0x12, +0x05,0x2A,0x7D,0x03,0x7C,0x00,0x12,0x05, +0x3E,0x12,0x06,0xE5,0x12,0x05,0x13,0x12, +0x05,0x35,0x54,0xBF,0x12,0x05,0x2A,0x7D, +0x03,0x7C,0x00,0x12,0x04,0xEB,0x7F,0x02, +0x7E,0x66,0x12,0x06,0xC1,0xEF,0x54,0xFD, +0x54,0xFE,0x12,0x05,0x4E,0x12,0x04,0xEB, +0x7F,0x02,0x7E,0x66,0x12,0x06,0xC1,0xEF, +0x44,0x02,0x44,0x01,0x12,0x05,0x4E,0x12, +0x05,0x3E,0x02,0x06,0xE5,0x7F,0x01,0x7E, +0x66,0x12,0x06,0xE5,0x7D,0xC0,0x7C,0x00, +0x7F,0x00,0x7E,0x66,0x12,0x06,0xE5,0xE4, +0xFD,0xFC,0x7F,0x01,0x7E,0x66,0x12,0x06, +0xE5,0x7D,0x80,0x7C,0x00,0x7F,0x00,0x7E, +0x66,0x12,0x06,0xE5,0x22,0x7D,0x03,0x7C, +0x00,0x7F,0x01,0x7E,0x66,0x12,0x06,0xE5, +0x7D,0x80,0x7C,0x00,0x7F,0x00,0x7E,0x66, +0x12,0x06,0xE5,0x22,0xFD,0xAC,0x06,0x7F, +0x02,0x7E,0x66,0x12,0x06,0xE5,0x22,0x7F, +0x02,0x7E,0x66,0x12,0x06,0xC1,0xEF,0x22, +0x7F,0x01,0x7E,0x66,0x12,0x06,0xE5,0x7D, +0xC0,0x7C,0x00,0x7F,0x00,0x7E,0x66,0x22, +0xFD,0xAC,0x06,0x7F,0x02,0x7E,0x66,0x12, +0x06,0xE5,0xE4,0xFD,0xFC,0x22,0x78,0x7F, +0xE4,0xF6,0xD8,0xFD,0x75,0x81,0x3C,0x02, +0x05,0xA3,0x02,0x00,0x0E,0xE4,0x93,0xA3, +0xF8,0xE4,0x93,0xA3,0x40,0x03,0xF6,0x80, +0x01,0xF2,0x08,0xDF,0xF4,0x80,0x29,0xE4, +0x93,0xA3,0xF8,0x54,0x07,0x24,0x0C,0xC8, +0xC3,0x33,0xC4,0x54,0x0F,0x44,0x20,0xC8, +0x83,0x40,0x04,0xF4,0x56,0x80,0x01,0x46, +0xF6,0xDF,0xE4,0x80,0x0B,0x01,0x02,0x04, +0x08,0x10,0x20,0x40,0x80,0x90,0x07,0x01, +0xE4,0x7E,0x01,0x93,0x60,0xBC,0xA3,0xFF, +0x54,0x3F,0x30,0xE5,0x09,0x54,0x1F,0xFE, +0xE4,0x93,0xA3,0x60,0x01,0x0E,0xCF,0x54, +0xC0,0x25,0xE0,0x60,0xA8,0x40,0xB8,0xE4, +0x93,0xA3,0xFA,0xE4,0x93,0xA3,0xF8,0xE4, +0x93,0xA3,0xC8,0xC5,0x82,0xC8,0xCA,0xC5, +0x83,0xCA,0xF0,0xA3,0xC8,0xC5,0x82,0xC8, +0xCA,0xC5,0x83,0xCA,0xDF,0xE9,0xDE,0xE7, +0x80,0xBE,0x75,0x0F,0x80,0x75,0x0E,0x7E, +0x75,0x0D,0xAA,0x75,0x0C,0x83,0xE4,0xF5, +0x10,0x75,0x0B,0xA0,0x75,0x0A,0xAC,0x75, +0x09,0xB9,0x75,0x08,0x03,0x75,0x89,0x11, +0x7B,0x60,0x7A,0x09,0xF9,0xF8,0xAF,0x0B, +0xAE,0x0A,0xAD,0x09,0xAC,0x08,0x12,0x03, +0xD6,0xAD,0x07,0xAC,0x06,0xC3,0xE4,0x9D, +0xFD,0xE4,0x9C,0xFC,0x78,0x17,0xF6,0xAF, +0x05,0xEF,0x08,0xF6,0x18,0xE6,0xF5,0x8C, +0x08,0xE6,0xF5,0x8A,0x74,0x0D,0x2D,0xFD, +0xE4,0x3C,0x18,0xF6,0xAF,0x05,0xEF,0x08, +0xF6,0x75,0x88,0x10,0x53,0x8E,0xC7,0xD2, +0xA9,0x22,0x90,0x06,0x24,0x12,0x04,0x79, +0xEF,0x24,0x01,0xFF,0xE4,0x3E,0xFE,0xE4, +0x3D,0xFD,0xE4,0x3C,0x22,0x7F,0x20,0x7E, +0x4E,0xE4,0xFD,0xFC,0x90,0x06,0x24,0x12, +0x04,0x85,0xC3,0x02,0x04,0x68,0xFC,0x90, +0x06,0x24,0x02,0x04,0x91,0x90,0x06,0x28, +0xEE,0xF0,0xA3,0xEF,0xF0,0x22,0x90,0x06, +0x28,0xFF,0xEE,0xF0,0xFC,0xA3,0xEF,0xF0, +0x22,0xC0,0xE0,0xC0,0xF0,0xC0,0x83,0xC0, +0x82,0xC0,0xD0,0x75,0xD0,0x00,0xC0,0x00, +0x78,0x17,0xE6,0xF5,0x8C,0x78,0x18,0xE6, +0xF5,0x8A,0x90,0x06,0x2E,0xE4,0x75,0xF0, +0x01,0x12,0x03,0x84,0x90,0x06,0x30,0xE4, +0x75,0xF0,0x01,0x12,0x03,0x84,0xD0,0x00, +0xD0,0xD0,0xD0,0x82,0xD0,0x83,0xD0,0xF0, +0xD0,0xE0,0x32,0xC2,0xAF,0xAD,0x07,0xAC, +0x06,0x8C,0xA2,0x8D,0xA3,0x75,0xA0,0x01, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0xAE,0xA1,0xBE,0x00,0xF0, +0xAE,0xA6,0xAF,0xA7,0xD2,0xAF,0x22,0xC2, +0xAF,0xAB,0x07,0xAA,0x06,0x8A,0xA2,0x8B, +0xA3,0x8C,0xA4,0x8D,0xA5,0x75,0xA0,0x03, +0x00,0x00,0x00,0xAA,0xA1,0xBA,0x00,0xF8, +0xD2,0xAF,0x22,0x42,0x06,0x30,0x00,0x00, +0x42,0x06,0x2E,0x00,0x00,0x00,0x12,0x07, +0x15,0x12,0x05,0xE8,0x02,0x00,0x03,0xE4, +0xF5,0x8E,0x22}; + +#define FIBER_AUTO_INIT_SIZE 1937 +CONST_T rtk_uint8 Fiber_auto[FIBER_AUTO_INIT_SIZE] = { +0x02,0x05,0x7E,0xE4,0xF5,0xA8, +0xD2,0xAF,0x22,0x00,0x00,0x02,0x06,0xFF, +0xE4,0x90,0x06,0x2A,0xF0,0x90,0x06,0x2D, +0xF0,0xA3,0xF0,0xA3,0xF0,0xFD,0x7C,0x01, +0x7F,0x3F,0x7E,0x1D,0x12,0x07,0x5D,0x7D, +0x40,0x12,0x03,0x77,0x80,0x08,0x12,0x06, +0xD3,0x50,0x08,0x12,0x06,0xC0,0x12,0x06, +0xE4,0x80,0xF3,0xE4,0xF5,0xA8,0xD2,0xAF, +0x7D,0x1F,0xFC,0x7F,0x49,0x7E,0x13,0x12, +0x07,0x5D,0x12,0x07,0x84,0x7D,0xFE,0x7C, +0x00,0x7F,0xAA,0x7E,0x12,0x12,0x07,0x5D, +0x7D,0xD7,0x12,0x03,0x42,0x7D,0x80,0x12, +0x02,0xDE,0x7D,0x94,0x7C,0xF9,0x12,0x03, +0x6F,0x7D,0x81,0x12,0x02,0xDE,0x7D,0xA2, +0x7C,0x31,0x12,0x03,0x6F,0x7D,0x82,0x12, +0x02,0xF3,0x7D,0x60,0x7C,0x69,0x12,0x03, +0x85,0x7D,0x83,0x12,0x02,0xF3,0x7D,0x28, +0x7C,0x97,0x12,0x03,0x85,0x7D,0x84,0x12, +0x03,0x08,0x7D,0x85,0x7C,0x9D,0x12,0x03, +0x9E,0x7D,0x23,0x12,0x03,0x08,0x7D,0x10, +0x7C,0xD8,0x12,0x03,0x9E,0x7D,0x24,0x7C, +0x04,0x12,0x03,0x5C,0x7D,0x00,0x12,0x03, +0x42,0x7D,0x2F,0x12,0x03,0x1D,0x7D,0x20, +0x7C,0x0F,0x7F,0x02,0x7E,0x66,0x12,0x07, +0x5D,0x7D,0x01,0x12,0x03,0x1D,0x7D,0x04, +0x7C,0x00,0x7F,0x01,0x7E,0x66,0x12,0x07, +0x5D,0x7D,0x80,0x7C,0x00,0x7F,0x00,0x7E, +0x66,0x12,0x07,0x5D,0x7F,0x02,0x7E,0x66, +0x12,0x07,0x39,0x12,0x06,0xEB,0x44,0x02, +0xFF,0x12,0x06,0xEB,0x44,0x04,0x12,0x06, +0xF4,0xFD,0x7F,0x02,0x7E,0x66,0x12,0x07, +0x5D,0x7D,0x04,0x7C,0x00,0x12,0x03,0x5C, +0x7D,0xB8,0x7C,0x15,0x7F,0xEB,0x7E,0x13, +0x12,0x07,0x5D,0x7D,0x07,0x7C,0x00,0x7F, +0xE7,0x7E,0x13,0x12,0x07,0x5D,0x7D,0x40, +0x7C,0x11,0x7F,0x00,0x7E,0x62,0x12,0x07, +0x5D,0x12,0x04,0xBF,0x7D,0x41,0x12,0x03, +0x77,0x80,0x08,0x12,0x06,0xD3,0x50,0x08, +0x12,0x06,0xC0,0x12,0x06,0xE4,0x80,0xF3, +0xC2,0x00,0xC2,0x01,0xD2,0xA9,0xD2,0x8C, +0x12,0x03,0x4C,0xEE,0x44,0x18,0x12,0x03, +0x8D,0xE4,0xFF,0xFE,0xFD,0x80,0x0C,0x7F, +0xD0,0x7E,0x07,0x12,0x06,0xD7,0x50,0x08, +0x12,0x06,0xC0,0x12,0x06,0xE4,0x80,0xEF, +0x7F,0x04,0x7E,0x62,0x12,0x07,0x39,0x12, +0x06,0xEB,0xEE,0x44,0x01,0xFE,0xEF,0x44, +0x80,0x12,0x06,0xF4,0xFD,0x7F,0x04,0x7E, +0x62,0x12,0x07,0x5D,0xE4,0xFF,0xFE,0xFD, +0x80,0x08,0x12,0x06,0xD3,0x50,0x08,0x12, +0x06,0xC0,0x12,0x06,0xE4,0x80,0xF3,0x12, +0x03,0x4C,0xEE,0x54,0xE7,0x12,0x03,0x8D, +0x7D,0x80,0x7C,0x67,0x7F,0x40,0x7E,0x13, +0x12,0x07,0x5D,0x7F,0x43,0x7E,0x13,0x12, +0x07,0x39,0x90,0x06,0x2E,0xEE,0xF0,0xA3, +0xEF,0xF0,0x30,0xE3,0xE3,0x12,0x03,0x32, +0x12,0x03,0x32,0x30,0xE2,0x72,0x90,0x06, +0x2D,0xE0,0x64,0x01,0x70,0x62,0x7F,0xEA, +0x7E,0x13,0x12,0x07,0x39,0x90,0x06,0x2B, +0xEE,0xF0,0xA3,0xEF,0xF0,0x54,0xEF,0xFF, +0x90,0x06,0x2B,0xEE,0xF0,0xA3,0xEF,0xF0, +0xEE,0x44,0x10,0x90,0x06,0x2B,0xF0,0xFC, +0xA3,0xEF,0xF0,0xFD,0x7F,0x16,0x7E,0x13, +0x12,0x07,0x5D,0xE4,0xFF,0xFE,0xFD,0x80, +0x0D,0xE4,0x7F,0xFF,0x7E,0x6F,0x12,0x06, +0xD8,0x50,0x08,0x12,0x06,0xC0,0x12,0x06, +0xE4,0x80,0xEE,0x90,0x06,0x2B,0xE0,0x54, +0xEF,0xFE,0xA3,0xE0,0x90,0x06,0x2B,0x12, +0x06,0xF7,0xAD,0x07,0x7F,0x16,0x7E,0x13, +0x12,0x07,0x5D,0xE4,0x90,0x06,0x2D,0xF0, +0xE4,0x90,0x06,0x2A,0xF0,0x02,0x01,0x96, +0x90,0x06,0x2A,0xE0,0x70,0x13,0x12,0x02, +0x69,0x90,0x06,0x2A,0x74,0x01,0xF0,0xE4, +0x90,0x06,0x32,0xF0,0xA3,0xF0,0x02,0x01, +0x96,0xC3,0x90,0x06,0x33,0xE0,0x94,0x64, +0x90,0x06,0x32,0xE0,0x94,0x00,0x50,0x03, +0x02,0x01,0x96,0xE4,0xF0,0xA3,0xF0,0x12, +0x02,0x69,0x90,0x06,0x2A,0x74,0x01,0xF0, +0x02,0x01,0x96,0x7F,0x56,0x7E,0x13,0x12, +0x07,0x39,0x90,0x06,0x2B,0xEE,0xF0,0xA3, +0xEF,0xF0,0x54,0xEF,0xFF,0x90,0x06,0x2B, +0xEE,0xF0,0xA3,0xEF,0xF0,0xEE,0x44,0x10, +0x90,0x06,0x2B,0xF0,0xFC,0xA3,0xEF,0xF0, +0xFD,0x7F,0x16,0x7E,0x13,0x12,0x07,0x5D, +0x90,0x06,0x2D,0x74,0x01,0xF0,0x7D,0x04, +0x7C,0x00,0x7F,0x02,0x7E,0x66,0x12,0x07, +0x5D,0x7D,0x00,0x7C,0x04,0x7F,0x01,0x7E, +0x66,0x12,0x07,0x5D,0x7D,0xC0,0x7C,0x00, +0x7F,0x00,0x7E,0x66,0x12,0x07,0x5D,0xE4, +0xFD,0xFC,0x7F,0x02,0x7E,0x66,0x12,0x07, +0x5D,0x7D,0x00,0x7C,0x04,0x7F,0x01,0x7E, +0x66,0x12,0x07,0x5D,0x7D,0xC0,0x7C,0x00, +0x7F,0x00,0x7E,0x66,0x12,0x07,0x5D,0x22, +0x7C,0x04,0x7F,0x01,0x7E,0x66,0x12,0x07, +0x5D,0x7D,0xC0,0x7C,0x00,0x7F,0x00,0x7E, +0x66,0x12,0x07,0x5D,0x22,0x7C,0x04,0x7F, +0x01,0x7E,0x66,0x12,0x07,0x5D,0x7D,0xC0, +0x7C,0x00,0x7F,0x00,0x7E,0x66,0x12,0x07, +0x5D,0x22,0x7C,0x04,0x7F,0x01,0x7E,0x66, +0x12,0x07,0x5D,0x7D,0xC0,0x7C,0x00,0x7F, +0x00,0x7E,0x66,0x12,0x07,0x5D,0x22,0x7C, +0x00,0x7F,0x01,0x7E,0x66,0x12,0x07,0x5D, +0x7D,0xC0,0x7C,0x00,0x7F,0x00,0x7E,0x66, +0x12,0x07,0x5D,0x22,0x7F,0x01,0x7E,0x62, +0x12,0x07,0x39,0x90,0x06,0x28,0xEE,0xF0, +0xA3,0xEF,0xF0,0x22,0x7C,0x04,0x7F,0x02, +0x7E,0x66,0x12,0x07,0x5D,0x22,0x7F,0xE7, +0x7E,0x13,0x12,0x07,0x39,0x90,0x06,0x28, +0xEE,0xF0,0xA3,0xEF,0xF0,0x22,0x7F,0x01, +0x7E,0x66,0x12,0x07,0x5D,0x7D,0xC0,0x7C, +0x00,0x7F,0x00,0x7E,0x66,0x12,0x07,0x5D, +0x22,0x7F,0x02,0x7E,0x66,0x12,0x07,0x5D, +0x22,0x7C,0x00,0x7F,0x36,0x7E,0x13,0x12, +0x07,0x5D,0xE4,0xFF,0xFE,0xFD,0x22,0x7F, +0x02,0x7E,0x66,0x12,0x07,0x5D,0x22,0x90, +0x06,0x28,0xF0,0xFC,0xA3,0xEF,0xF0,0xFD, +0x7F,0xE7,0x7E,0x13,0x12,0x07,0x5D,0x22, +0x7F,0x02,0x7E,0x66,0x12,0x07,0x5D,0x22, +0xC5,0xF0,0xF8,0xA3,0xE0,0x28,0xF0,0xC5, +0xF0,0xF8,0xE5,0x82,0x15,0x82,0x70,0x02, +0x15,0x83,0xE0,0x38,0xF0,0x22,0x75,0xF0, +0x08,0x75,0x82,0x00,0xEF,0x2F,0xFF,0xEE, +0x33,0xFE,0xCD,0x33,0xCD,0xCC,0x33,0xCC, +0xC5,0x82,0x33,0xC5,0x82,0x9B,0xED,0x9A, +0xEC,0x99,0xE5,0x82,0x98,0x40,0x0C,0xF5, +0x82,0xEE,0x9B,0xFE,0xED,0x9A,0xFD,0xEC, +0x99,0xFC,0x0F,0xD5,0xF0,0xD6,0xE4,0xCE, +0xFB,0xE4,0xCD,0xFA,0xE4,0xCC,0xF9,0xA8, +0x82,0x22,0xB8,0x00,0xC1,0xB9,0x00,0x59, +0xBA,0x00,0x2D,0xEC,0x8B,0xF0,0x84,0xCF, +0xCE,0xCD,0xFC,0xE5,0xF0,0xCB,0xF9,0x78, +0x18,0xEF,0x2F,0xFF,0xEE,0x33,0xFE,0xED, +0x33,0xFD,0xEC,0x33,0xFC,0xEB,0x33,0xFB, +0x10,0xD7,0x03,0x99,0x40,0x04,0xEB,0x99, +0xFB,0x0F,0xD8,0xE5,0xE4,0xF9,0xFA,0x22, +0x78,0x18,0xEF,0x2F,0xFF,0xEE,0x33,0xFE, +0xED,0x33,0xFD,0xEC,0x33,0xFC,0xC9,0x33, +0xC9,0x10,0xD7,0x05,0x9B,0xE9,0x9A,0x40, +0x07,0xEC,0x9B,0xFC,0xE9,0x9A,0xF9,0x0F, +0xD8,0xE0,0xE4,0xC9,0xFA,0xE4,0xCC,0xFB, +0x22,0x75,0xF0,0x10,0xEF,0x2F,0xFF,0xEE, +0x33,0xFE,0xED,0x33,0xFD,0xCC,0x33,0xCC, +0xC8,0x33,0xC8,0x10,0xD7,0x07,0x9B,0xEC, +0x9A,0xE8,0x99,0x40,0x0A,0xED,0x9B,0xFD, +0xEC,0x9A,0xFC,0xE8,0x99,0xF8,0x0F,0xD5, +0xF0,0xDA,0xE4,0xCD,0xFB,0xE4,0xCC,0xFA, +0xE4,0xC8,0xF9,0x22,0xEB,0x9F,0xF5,0xF0, +0xEA,0x9E,0x42,0xF0,0xE9,0x9D,0x42,0xF0, +0xE8,0x9C,0x45,0xF0,0x22,0xE0,0xFC,0xA3, +0xE0,0xFD,0xA3,0xE0,0xFE,0xA3,0xE0,0xFF, +0x22,0xE0,0xF8,0xA3,0xE0,0xF9,0xA3,0xE0, +0xFA,0xA3,0xE0,0xFB,0x22,0xEC,0xF0,0xA3, +0xED,0xF0,0xA3,0xEE,0xF0,0xA3,0xEF,0xF0, +0x22,0x12,0x05,0x35,0x12,0x05,0x57,0x44, +0x40,0x12,0x05,0x4C,0x7D,0x03,0x7C,0x00, +0x12,0x05,0x60,0x12,0x07,0x5D,0x12,0x05, +0x35,0x12,0x05,0x57,0x54,0xBF,0x12,0x05, +0x4C,0x7D,0x03,0x7C,0x00,0x12,0x05,0x0D, +0x7F,0x02,0x7E,0x66,0x12,0x07,0x39,0xEF, +0x54,0xFD,0x54,0xFE,0x12,0x05,0x70,0x12, +0x05,0x0D,0x7F,0x02,0x7E,0x66,0x12,0x07, +0x39,0xEF,0x44,0x02,0x44,0x01,0x12,0x05, +0x70,0x12,0x05,0x60,0x02,0x07,0x5D,0x7F, +0x01,0x7E,0x66,0x12,0x07,0x5D,0x7D,0xC0, +0x7C,0x00,0x7F,0x00,0x7E,0x66,0x12,0x07, +0x5D,0xE4,0xFD,0xFC,0x7F,0x01,0x7E,0x66, +0x12,0x07,0x5D,0x7D,0x80,0x7C,0x00,0x7F, +0x00,0x7E,0x66,0x12,0x07,0x5D,0x22,0x7D, +0x03,0x7C,0x00,0x7F,0x01,0x7E,0x66,0x12, +0x07,0x5D,0x7D,0x80,0x7C,0x00,0x7F,0x00, +0x7E,0x66,0x12,0x07,0x5D,0x22,0xFD,0xAC, +0x06,0x7F,0x02,0x7E,0x66,0x12,0x07,0x5D, +0x22,0x7F,0x02,0x7E,0x66,0x12,0x07,0x39, +0xEF,0x22,0x7F,0x01,0x7E,0x66,0x12,0x07, +0x5D,0x7D,0xC0,0x7C,0x00,0x7F,0x00,0x7E, +0x66,0x22,0xFD,0xAC,0x06,0x7F,0x02,0x7E, +0x66,0x12,0x07,0x5D,0xE4,0xFD,0xFC,0x22, +0x78,0x7F,0xE4,0xF6,0xD8,0xFD,0x75,0x81, +0x3C,0x02,0x05,0xC5,0x02,0x00,0x0E,0xE4, +0x93,0xA3,0xF8,0xE4,0x93,0xA3,0x40,0x03, +0xF6,0x80,0x01,0xF2,0x08,0xDF,0xF4,0x80, +0x29,0xE4,0x93,0xA3,0xF8,0x54,0x07,0x24, +0x0C,0xC8,0xC3,0x33,0xC4,0x54,0x0F,0x44, +0x20,0xC8,0x83,0x40,0x04,0xF4,0x56,0x80, +0x01,0x46,0xF6,0xDF,0xE4,0x80,0x0B,0x01, +0x02,0x04,0x08,0x10,0x20,0x40,0x80,0x90, +0x07,0x79,0xE4,0x7E,0x01,0x93,0x60,0xBC, +0xA3,0xFF,0x54,0x3F,0x30,0xE5,0x09,0x54, +0x1F,0xFE,0xE4,0x93,0xA3,0x60,0x01,0x0E, +0xCF,0x54,0xC0,0x25,0xE0,0x60,0xA8,0x40, +0xB8,0xE4,0x93,0xA3,0xFA,0xE4,0x93,0xA3, +0xF8,0xE4,0x93,0xA3,0xC8,0xC5,0x82,0xC8, +0xCA,0xC5,0x83,0xCA,0xF0,0xA3,0xC8,0xC5, +0x82,0xC8,0xCA,0xC5,0x83,0xCA,0xDF,0xE9, +0xDE,0xE7,0x80,0xBE,0x75,0x0F,0x80,0x75, +0x0E,0x7E,0x75,0x0D,0xAA,0x75,0x0C,0x83, +0xE4,0xF5,0x10,0x75,0x0B,0xA0,0x75,0x0A, +0xAC,0x75,0x09,0xB9,0x75,0x08,0x03,0x75, +0x89,0x11,0x7B,0x60,0x7A,0x09,0xF9,0xF8, +0xAF,0x0B,0xAE,0x0A,0xAD,0x09,0xAC,0x08, +0x12,0x03,0xF8,0xAD,0x07,0xAC,0x06,0xC3, +0xE4,0x9D,0xFD,0xE4,0x9C,0xFC,0x78,0x17, +0xF6,0xAF,0x05,0xEF,0x08,0xF6,0x18,0xE6, +0xF5,0x8C,0x08,0xE6,0xF5,0x8A,0x74,0x0D, +0x2D,0xFD,0xE4,0x3C,0x18,0xF6,0xAF,0x05, +0xEF,0x08,0xF6,0x75,0x88,0x10,0x53,0x8E, +0xC7,0xD2,0xA9,0x22,0x7D,0x69,0x7C,0x0A, +0x7F,0x15,0x7E,0x1D,0x12,0x07,0x5D,0x7F, +0x00,0x12,0x06,0x98,0x74,0x20,0xFF,0xFE, +0x12,0x06,0xB1,0x7F,0x40,0x12,0x06,0x98, +0x7F,0x60,0x7E,0x20,0x12,0x06,0xB1,0x7D, +0x40,0x7C,0x13,0x7F,0x80,0x7E,0x20,0x02, +0x07,0x5D,0x7D,0x40,0x7C,0x13,0x7E,0x20, +0x12,0x07,0x5D,0x7D,0x69,0x7C,0x0A,0x7F, +0x15,0x7E,0x1D,0x12,0x07,0x5D,0x7D,0x40, +0x7C,0x13,0x22,0x12,0x07,0x5D,0x7D,0x69, +0x7C,0x0A,0x7F,0x15,0x7E,0x1D,0x12,0x07, +0x5D,0x22,0x90,0x06,0x24,0x12,0x04,0x9B, +0xEF,0x24,0x01,0xFF,0xE4,0x3E,0xFE,0xE4, +0x3D,0xFD,0xE4,0x3C,0x22,0x7F,0x20,0x7E, +0x4E,0xE4,0xFD,0xFC,0x90,0x06,0x24,0x12, +0x04,0xA7,0xC3,0x02,0x04,0x8A,0xFC,0x90, +0x06,0x24,0x02,0x04,0xB3,0x90,0x06,0x28, +0xEE,0xF0,0xA3,0xEF,0xF0,0x22,0x90,0x06, +0x28,0xFF,0xEE,0xF0,0xFC,0xA3,0xEF,0xF0, +0x22,0xC0,0xE0,0xC0,0xF0,0xC0,0x83,0xC0, +0x82,0xC0,0xD0,0x75,0xD0,0x00,0xC0,0x00, +0x78,0x17,0xE6,0xF5,0x8C,0x78,0x18,0xE6, +0xF5,0x8A,0x90,0x06,0x30,0xE4,0x75,0xF0, +0x01,0x12,0x03,0xA6,0x90,0x06,0x32,0xE4, +0x75,0xF0,0x01,0x12,0x03,0xA6,0xD0,0x00, +0xD0,0xD0,0xD0,0x82,0xD0,0x83,0xD0,0xF0, +0xD0,0xE0,0x32,0xC2,0xAF,0xAD,0x07,0xAC, +0x06,0x8C,0xA2,0x8D,0xA3,0x75,0xA0,0x01, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0xAE,0xA1,0xBE,0x00,0xF0, +0xAE,0xA6,0xAF,0xA7,0xD2,0xAF,0x22,0xC2, +0xAF,0xAB,0x07,0xAA,0x06,0x8A,0xA2,0x8B, +0xA3,0x8C,0xA4,0x8D,0xA5,0x75,0xA0,0x03, +0x00,0x00,0x00,0xAA,0xA1,0xBA,0x00,0xF8, +0xD2,0xAF,0x22,0x42,0x06,0x32,0x00,0x00, +0x42,0x06,0x30,0x00,0x00,0x00,0x12,0x07, +0x8D,0x12,0x06,0x0A,0x02,0x00,0x03,0xE4, +0xF5,0x8E,0x22}; + + +static rtk_api_ret_t _dal_rtl8367c_port_FiberModeAbility_set(rtk_port_t port, rtk_port_phy_ability_t *pAbility) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + + /* Check Combo port or not */ + RTK_CHK_PORT_IS_COMBO(port); + + /* Flow Control */ + if ((retVal = rtl8367c_getAsicReg(RTL8367C_REG_FIB0_CFG04, ®Data)) != RT_ERR_OK) + return retVal; + + if (pAbility->AsyFC == 1) + regData |= (0x0001 << 8); + else + regData &= ~(0x0001 << 8); + + if (pAbility->FC == 1) + regData |= (0x0001 << 7); + else + regData &= ~(0x0001 << 7); + + if ((retVal = rtl8367c_setAsicReg(RTL8367C_REG_FIB0_CFG04, regData)) != RT_ERR_OK) + return retVal; + + /* Speed ability */ + if( (pAbility->Full_1000 == 1) && (pAbility->Full_100 == 1) && (pAbility->AutoNegotiation == 1) ) + { + if ((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_FIBER_CFG_1, RTL8367C_SDS_FRC_MODE_OFFSET, 0)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_FIBER_CFG_1, RTL8367C_SDS_MODE_MASK, 7)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicReg(RTL8367C_REG_FIB0_CFG00, 0x1140)) != RT_ERR_OK) + return retVal; + } + else if(pAbility->Full_1000 == 1) + { + if ((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_FIBER_CFG_1, RTL8367C_SDS_FRC_MODE_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_FIBER_CFG_1, RTL8367C_SDS_MODE_MASK, 4)) != RT_ERR_OK) + return retVal; + + if(pAbility->AutoNegotiation == 1) + { + if ((retVal = rtl8367c_setAsicReg(RTL8367C_REG_FIB0_CFG00, 0x1140)) != RT_ERR_OK) + return retVal; + } + else + { + if ((retVal = rtl8367c_setAsicReg(RTL8367C_REG_FIB0_CFG00, 0x0140)) != RT_ERR_OK) + return retVal; + } + } + else if(pAbility->Full_100 == 1) + { + if ((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_FIBER_CFG_1, RTL8367C_SDS_FRC_MODE_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_FIBER_CFG_1, RTL8367C_SDS_MODE_MASK, 5)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicReg(RTL8367C_REG_FIB0_CFG00, 0x2100)) != RT_ERR_OK) + return retVal; + } + + /* Digital software reset */ + if ((retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_ADR, 0x0003)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_CMD, 0x0080)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_getAsicReg(RTL8367C_REG_SDS_INDACS_DATA, ®Data)) != RT_ERR_OK) + return retVal; + + regData |= (0x0001 << 6); + + if ((retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_DATA, regData)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_ADR, 0x0003)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_CMD, 0x00C0)) != RT_ERR_OK) + return retVal; + + regData &= ~(0x0001 << 6); + + if ((retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_DATA, regData)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_ADR, 0x0003)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_CMD, 0x00C0)) != RT_ERR_OK) + return retVal; + + /* CDR reset */ + if ((retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_DATA, 0x1401))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_ADR, 0x0000))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_CMD, 0x00C0))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_DATA, 0x1403))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_ADR, 0x0000))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_CMD, 0x00C0))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +static rtk_api_ret_t _dal_rtl8367c_port_FiberModeAbility_get(rtk_port_t port, rtk_port_phy_ability_t *pAbility) +{ + rtk_api_ret_t retVal; + rtk_uint32 data, regData; + + /* Check Combo port or not */ + RTK_CHK_PORT_IS_COMBO(port); + + memset(pAbility, 0x00, sizeof(rtk_port_phy_ability_t)); + + /* Flow Control */ + if ((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_FIBER_CFG_1, RTL8367C_SDS_FRC_REG4_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_FIBER_CFG_1, RTL8367C_SDS_FRC_REG4_FIB100_OFFSET, 0)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_ADR, 0x0044)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_CMD, 0x0080)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_getAsicReg(RTL8367C_REG_SDS_INDACS_DATA, ®Data)) != RT_ERR_OK) + return retVal; + + if(regData & (0x0001 << 8)) + pAbility->AsyFC = 1; + + if(regData & (0x0001 << 7)) + pAbility->FC = 1; + + /* Speed ability */ + if ((retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_FIBER_CFG_1, RTL8367C_SDS_FRC_MODE_OFFSET, &data)) != RT_ERR_OK) + return retVal; + + if(data == 0) + { + pAbility->AutoNegotiation = 1; + pAbility->Full_1000 = 1; + pAbility->Full_100 = 1; + } + else + { + if ((retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_FIBER_CFG_1, RTL8367C_SDS_MODE_MASK, &data)) != RT_ERR_OK) + return retVal; + + if(data == 4) + { + pAbility->Full_1000 = 1; + + if ((retVal = rtl8367c_getAsicReg(RTL8367C_REG_FIB0_CFG00, &data)) != RT_ERR_OK) + return retVal; + + if(data & 0x1000) + pAbility->AutoNegotiation = 1; + else + pAbility->AutoNegotiation = 0; + } + else if(data == 5) + pAbility->Full_100 = 1; + else + return RT_ERR_FAILED; + } + + return RT_ERR_OK; +} + +static rtk_api_ret_t _dal_rtl8367c_port_phyComboPortMedia_get(rtk_port_t port, rtk_port_media_t *pMedia) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + rtk_uint32 data; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_IS_UTP(port); + + /* Check Combo Port ID */ + RTK_CHK_PORT_IS_COMBO(port); + + if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0249)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_getAsicReg(0x1300, ®Data)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0000)) != RT_ERR_OK) + return retVal; + + if(regData != 0x6367) + { + *pMedia = PORT_MEDIA_COPPER; + } + else + { + if ((retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_UTP_FIB_DET, RTL8367C_UTP_FIB_DISAUTODET_OFFSET, &data))!=RT_ERR_OK) + return retVal; + if(data == 0) + { + *pMedia = PORT_MEDIA_AUTO; + } + else + { + if ((retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_UTP_FIB_DET, RTL8367C_UTP_FIRST_OFFSET, &data))!=RT_ERR_OK) + return retVal; + + if(data == 1) + *pMedia = PORT_MEDIA_COPPER; + else + *pMedia = PORT_MEDIA_FIBER; + } + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_port_phyAutoNegoAbility_set + * Description: + * Set ethernet PHY auto-negotiation desired ability. + * Input: + * port - port id. + * pAbility - Ability structure + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_PHY_REG_ID - Invalid PHY address + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy + * Note: + * If Full_1000 bit is set to 1, the AutoNegotiation will be automatic set to 1. While both AutoNegotiation and Full_1000 are set to 0, the PHY speed and duplex selection will + * be set as following 100F > 100H > 10F > 10H priority sequence. + */ +rtk_api_ret_t dal_rtl8367c_port_phyAutoNegoAbility_set(rtk_port_t port, rtk_port_phy_ability_t *pAbility) +{ + rtk_api_ret_t retVal; + rtk_uint32 phyData; + rtk_uint32 phyEnMsk0; + rtk_uint32 phyEnMsk4; + rtk_uint32 phyEnMsk9; + rtk_port_media_t media_type; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_IS_UTP(port); + + if(NULL == pAbility) + return RT_ERR_NULL_POINTER; + + if (pAbility->Half_10 >= RTK_ENABLE_END || pAbility->Full_10 >= RTK_ENABLE_END || + pAbility->Half_100 >= RTK_ENABLE_END || pAbility->Full_100 >= RTK_ENABLE_END || + pAbility->Full_1000 >= RTK_ENABLE_END || pAbility->AutoNegotiation >= RTK_ENABLE_END || + pAbility->AsyFC >= RTK_ENABLE_END || pAbility->FC >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if (rtk_switch_isComboPort(port) == RT_ERR_OK) + { + if ((retVal = _dal_rtl8367c_port_phyComboPortMedia_get(port, &media_type)) != RT_ERR_OK) + return retVal; + + if(media_type == PORT_MEDIA_FIBER) + { + return _dal_rtl8367c_port_FiberModeAbility_set(port, pAbility); + } + } + + /*for PHY auto mode setup*/ + pAbility->AutoNegotiation = 1; + + phyEnMsk0 = 0; + phyEnMsk4 = 0; + phyEnMsk9 = 0; + + if (1 == pAbility->Half_10) + { + /*10BASE-TX half duplex capable in reg 4.5*/ + phyEnMsk4 = phyEnMsk4 | (1 << 5); + + /*Speed selection [1:0] */ + /* 11=Reserved*/ + /* 10= 1000Mpbs*/ + /* 01= 100Mpbs*/ + /* 00= 10Mpbs*/ + phyEnMsk0 = phyEnMsk0 & (~(1 << 6)); + phyEnMsk0 = phyEnMsk0 & (~(1 << 13)); + } + + if (1 == pAbility->Full_10) + { + /*10BASE-TX full duplex capable in reg 4.6*/ + phyEnMsk4 = phyEnMsk4 | (1 << 6); + /*Speed selection [1:0] */ + /* 11=Reserved*/ + /* 10= 1000Mpbs*/ + /* 01= 100Mpbs*/ + /* 00= 10Mpbs*/ + phyEnMsk0 = phyEnMsk0 & (~(1 << 6)); + phyEnMsk0 = phyEnMsk0 & (~(1 << 13)); + + /*Full duplex mode in reg 0.8*/ + phyEnMsk0 = phyEnMsk0 | (1 << 8); + + } + + if (1 == pAbility->Half_100) + { + /*100BASE-TX half duplex capable in reg 4.7*/ + phyEnMsk4 = phyEnMsk4 | (1 << 7); + /*Speed selection [1:0] */ + /* 11=Reserved*/ + /* 10= 1000Mpbs*/ + /* 01= 100Mpbs*/ + /* 00= 10Mpbs*/ + phyEnMsk0 = phyEnMsk0 & (~(1 << 6)); + phyEnMsk0 = phyEnMsk0 | (1 << 13); + } + + + if (1 == pAbility->Full_100) + { + /*100BASE-TX full duplex capable in reg 4.8*/ + phyEnMsk4 = phyEnMsk4 | (1 << 8); + /*Speed selection [1:0] */ + /* 11=Reserved*/ + /* 10= 1000Mpbs*/ + /* 01= 100Mpbs*/ + /* 00= 10Mpbs*/ + phyEnMsk0 = phyEnMsk0 & (~(1 << 6)); + phyEnMsk0 = phyEnMsk0 | (1 << 13); + /*Full duplex mode in reg 0.8*/ + phyEnMsk0 = phyEnMsk0 | (1 << 8); + } + + + if (1 == pAbility->Full_1000) + { + /*1000 BASE-T FULL duplex capable setting in reg 9.9*/ + phyEnMsk9 = phyEnMsk9 | (1 << 9); + + /*Speed selection [1:0] */ + /* 11=Reserved*/ + /* 10= 1000Mpbs*/ + /* 01= 100Mpbs*/ + /* 00= 10Mpbs*/ + phyEnMsk0 = phyEnMsk0 | (1 << 6); + phyEnMsk0 = phyEnMsk0 & (~(1 << 13)); + + + /*Auto-Negotiation setting in reg 0.12*/ + phyEnMsk0 = phyEnMsk0 | (1 << 12); + + } + + if (1 == pAbility->AutoNegotiation) + { + /*Auto-Negotiation setting in reg 0.12*/ + phyEnMsk0 = phyEnMsk0 | (1 << 12); + } + + if (1 == pAbility->AsyFC) + { + /*Asymetric flow control in reg 4.11*/ + phyEnMsk4 = phyEnMsk4 | (1 << 11); + } + if (1 == pAbility->FC) + { + /*Flow control in reg 4.10*/ + phyEnMsk4 = phyEnMsk4 | (1 << 10); + } + + /*1000 BASE-T control register setting*/ + if ((retVal = rtl8367c_getAsicPHYReg(rtk_switch_port_L2P_get(port), PHY_1000_BASET_CONTROL_REG, &phyData)) != RT_ERR_OK) + return retVal; + + phyData = (phyData & (~0x0200)) | phyEnMsk9 ; + + if ((retVal = rtl8367c_setAsicPHYReg(rtk_switch_port_L2P_get(port), PHY_1000_BASET_CONTROL_REG, phyData)) != RT_ERR_OK) + return retVal; + + /*Auto-Negotiation control register setting*/ + if ((retVal = rtl8367c_getAsicPHYReg(rtk_switch_port_L2P_get(port), PHY_AN_ADVERTISEMENT_REG, &phyData)) != RT_ERR_OK) + return retVal; + + phyData = (phyData & (~0x0DE0)) | phyEnMsk4; + if ((retVal = rtl8367c_setAsicPHYReg(rtk_switch_port_L2P_get(port), PHY_AN_ADVERTISEMENT_REG, phyData)) != RT_ERR_OK) + return retVal; + + /*Control register setting and restart auto*/ + if ((retVal = rtl8367c_getAsicPHYReg(rtk_switch_port_L2P_get(port), PHY_CONTROL_REG, &phyData)) != RT_ERR_OK) + return retVal; + + phyData = (phyData & (~0x3140)) | phyEnMsk0; + /*If have auto-negotiation capable, then restart auto negotiation*/ + if (1 == pAbility->AutoNegotiation) + { + phyData = phyData | (1 << 9); + } + + if ((retVal = rtl8367c_setAsicPHYReg(rtk_switch_port_L2P_get(port), PHY_CONTROL_REG, phyData)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_port_phyAutoNegoAbility_get + * Description: + * Get PHY ability through PHY registers. + * Input: + * port - Port id. + * Output: + * pAbility - Ability structure + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_PHY_REG_ID - Invalid PHY address + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy + * Note: + * Get the capablity of specified PHY. + */ +rtk_api_ret_t dal_rtl8367c_port_phyAutoNegoAbility_get(rtk_port_t port, rtk_port_phy_ability_t *pAbility) +{ + rtk_api_ret_t retVal; + rtk_uint32 phyData0; + rtk_uint32 phyData4; + rtk_uint32 phyData9; + rtk_port_media_t media_type; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_IS_UTP(port); + + if(NULL == pAbility) + return RT_ERR_NULL_POINTER; + + if (rtk_switch_isComboPort(port) == RT_ERR_OK) + { + if ((retVal = _dal_rtl8367c_port_phyComboPortMedia_get(port, &media_type)) != RT_ERR_OK) + return retVal; + + if(media_type == PORT_MEDIA_FIBER) + { + return _dal_rtl8367c_port_FiberModeAbility_get(port, pAbility); + } + } + + /*Control register setting and restart auto*/ + if ((retVal = rtl8367c_getAsicPHYReg(rtk_switch_port_L2P_get(port), PHY_CONTROL_REG, &phyData0)) != RT_ERR_OK) + return retVal; + + /*Auto-Negotiation control register setting*/ + if ((retVal = rtl8367c_getAsicPHYReg(rtk_switch_port_L2P_get(port), PHY_AN_ADVERTISEMENT_REG, &phyData4)) != RT_ERR_OK) + return retVal; + + /*1000 BASE-T control register setting*/ + if ((retVal = rtl8367c_getAsicPHYReg(rtk_switch_port_L2P_get(port), PHY_1000_BASET_CONTROL_REG, &phyData9)) != RT_ERR_OK) + return retVal; + + if (phyData9 & (1 << 9)) + pAbility->Full_1000 = 1; + else + pAbility->Full_1000 = 0; + + if (phyData4 & (1 << 11)) + pAbility->AsyFC = 1; + else + pAbility->AsyFC = 0; + + if (phyData4 & (1 << 10)) + pAbility->FC = 1; + else + pAbility->FC = 0; + + + if (phyData4 & (1 << 8)) + pAbility->Full_100 = 1; + else + pAbility->Full_100 = 0; + + if (phyData4 & (1 << 7)) + pAbility->Half_100 = 1; + else + pAbility->Half_100 = 0; + + if (phyData4 & (1 << 6)) + pAbility->Full_10 = 1; + else + pAbility->Full_10 = 0; + + if (phyData4 & (1 << 5)) + pAbility->Half_10 = 1; + else + pAbility->Half_10 = 0; + + + if (phyData0 & (1 << 12)) + pAbility->AutoNegotiation = 1; + else + pAbility->AutoNegotiation = 0; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_port_phyForceModeAbility_set + * Description: + * Set the port speed/duplex mode/pause/asy_pause in the PHY force mode. + * Input: + * port - port id. + * pAbility - Ability structure + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_PHY_REG_ID - Invalid PHY address + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy + * Note: + * While both AutoNegotiation and Full_1000 are set to 0, the PHY speed and duplex selection will + * be set as following 100F > 100H > 10F > 10H priority sequence. + * This API can be used to configure combo port in fiber mode. + * The possible parameters in fiber mode are Full_1000 and Full 100. + * All the other fields in rtk_port_phy_ability_t will be ignored in fiber port. + */ +rtk_api_ret_t dal_rtl8367c_port_phyForceModeAbility_set(rtk_port_t port, rtk_port_phy_ability_t *pAbility) +{ + rtk_api_ret_t retVal; + rtk_uint32 phyData; + rtk_uint32 phyEnMsk0; + rtk_uint32 phyEnMsk4; + rtk_uint32 phyEnMsk9; + rtk_port_media_t media_type; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_IS_UTP(port); + + if(NULL == pAbility) + return RT_ERR_NULL_POINTER; + + if (pAbility->Half_10 >= RTK_ENABLE_END || pAbility->Full_10 >= RTK_ENABLE_END || + pAbility->Half_100 >= RTK_ENABLE_END || pAbility->Full_100 >= RTK_ENABLE_END || + pAbility->Full_1000 >= RTK_ENABLE_END || pAbility->AutoNegotiation >= RTK_ENABLE_END || + pAbility->AsyFC >= RTK_ENABLE_END || pAbility->FC >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if (rtk_switch_isComboPort(port) == RT_ERR_OK) + { + if ((retVal = _dal_rtl8367c_port_phyComboPortMedia_get(port, &media_type)) != RT_ERR_OK) + return retVal; + + if(media_type == PORT_MEDIA_FIBER) + { + return _dal_rtl8367c_port_FiberModeAbility_set(port, pAbility); + } + } + + if (1 == pAbility->Full_1000) + return RT_ERR_INPUT; + + /*for PHY force mode setup*/ + pAbility->AutoNegotiation = 0; + + phyEnMsk0 = 0; + phyEnMsk4 = 0; + phyEnMsk9 = 0; + + if (1 == pAbility->Half_10) + { + /*10BASE-TX half duplex capable in reg 4.5*/ + phyEnMsk4 = phyEnMsk4 | (1 << 5); + + /*Speed selection [1:0] */ + /* 11=Reserved*/ + /* 10= 1000Mpbs*/ + /* 01= 100Mpbs*/ + /* 00= 10Mpbs*/ + phyEnMsk0 = phyEnMsk0 & (~(1 << 6)); + phyEnMsk0 = phyEnMsk0 & (~(1 << 13)); + } + + if (1 == pAbility->Full_10) + { + /*10BASE-TX full duplex capable in reg 4.6*/ + phyEnMsk4 = phyEnMsk4 | (1 << 6); + /*Speed selection [1:0] */ + /* 11=Reserved*/ + /* 10= 1000Mpbs*/ + /* 01= 100Mpbs*/ + /* 00= 10Mpbs*/ + phyEnMsk0 = phyEnMsk0 & (~(1 << 6)); + phyEnMsk0 = phyEnMsk0 & (~(1 << 13)); + + /*Full duplex mode in reg 0.8*/ + phyEnMsk0 = phyEnMsk0 | (1 << 8); + + } + + if (1 == pAbility->Half_100) + { + /*100BASE-TX half duplex capable in reg 4.7*/ + phyEnMsk4 = phyEnMsk4 | (1 << 7); + /*Speed selection [1:0] */ + /* 11=Reserved*/ + /* 10= 1000Mpbs*/ + /* 01= 100Mpbs*/ + /* 00= 10Mpbs*/ + phyEnMsk0 = phyEnMsk0 & (~(1 << 6)); + phyEnMsk0 = phyEnMsk0 | (1 << 13); + } + + + if (1 == pAbility->Full_100) + { + /*100BASE-TX full duplex capable in reg 4.8*/ + phyEnMsk4 = phyEnMsk4 | (1 << 8); + /*Speed selection [1:0] */ + /* 11=Reserved*/ + /* 10= 1000Mpbs*/ + /* 01= 100Mpbs*/ + /* 00= 10Mpbs*/ + phyEnMsk0 = phyEnMsk0 & (~(1 << 6)); + phyEnMsk0 = phyEnMsk0 | (1 << 13); + /*Full duplex mode in reg 0.8*/ + phyEnMsk0 = phyEnMsk0 | (1 << 8); + } + + if (1 == pAbility->AsyFC) + { + /*Asymetric flow control in reg 4.11*/ + phyEnMsk4 = phyEnMsk4 | (1 << 11); + } + if (1 == pAbility->FC) + { + /*Flow control in reg 4.10*/ + phyEnMsk4 = phyEnMsk4 | ((1 << 10)); + } + + /*1000 BASE-T control register setting*/ + if ((retVal = rtl8367c_getAsicPHYReg(rtk_switch_port_L2P_get(port), PHY_1000_BASET_CONTROL_REG, &phyData)) != RT_ERR_OK) + return retVal; + + phyData = (phyData & (~0x0200)) | phyEnMsk9 ; + + if ((retVal = rtl8367c_setAsicPHYReg(rtk_switch_port_L2P_get(port), PHY_1000_BASET_CONTROL_REG, phyData)) != RT_ERR_OK) + return retVal; + + /*Auto-Negotiation control register setting*/ + if ((retVal = rtl8367c_getAsicPHYReg(rtk_switch_port_L2P_get(port), PHY_AN_ADVERTISEMENT_REG, &phyData)) != RT_ERR_OK) + return retVal; + + phyData = (phyData & (~0x0DE0)) | phyEnMsk4; + if ((retVal = rtl8367c_setAsicPHYReg(rtk_switch_port_L2P_get(port), PHY_AN_ADVERTISEMENT_REG, phyData)) != RT_ERR_OK) + return retVal; + + /*Control register setting and power off/on*/ + phyData = phyEnMsk0 & (~(1 << 12)); + phyData |= (1 << 11); /* power down PHY, bit 11 should be set to 1 */ + if ((retVal = rtl8367c_setAsicPHYReg(rtk_switch_port_L2P_get(port), PHY_CONTROL_REG, phyData)) != RT_ERR_OK) + return retVal; + + phyData = phyData & (~(1 << 11)); /* power on PHY, bit 11 should be set to 0*/ + if ((retVal = rtl8367c_setAsicPHYReg(rtk_switch_port_L2P_get(port), PHY_CONTROL_REG, phyData)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_port_phyForceModeAbility_get + * Description: + * Get PHY ability through PHY registers. + * Input: + * port - Port id. + * Output: + * pAbility - Ability structure + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_PHY_REG_ID - Invalid PHY address + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy + * Note: + * Get the capablity of specified PHY. + */ +rtk_api_ret_t dal_rtl8367c_port_phyForceModeAbility_get(rtk_port_t port, rtk_port_phy_ability_t *pAbility) +{ + rtk_api_ret_t retVal; + rtk_uint32 phyData0; + rtk_uint32 phyData4; + rtk_uint32 phyData9; + rtk_port_media_t media_type; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_IS_UTP(port); + + if(NULL == pAbility) + return RT_ERR_NULL_POINTER; + + if (rtk_switch_isComboPort(port) == RT_ERR_OK) + { + if ((retVal = _dal_rtl8367c_port_phyComboPortMedia_get(port, &media_type)) != RT_ERR_OK) + return retVal; + + if(media_type == PORT_MEDIA_FIBER) + { + return _dal_rtl8367c_port_FiberModeAbility_get(port, pAbility); + } + } + + /*Control register setting and restart auto*/ + if ((retVal = rtl8367c_getAsicPHYReg(rtk_switch_port_L2P_get(port), PHY_CONTROL_REG, &phyData0)) != RT_ERR_OK) + return retVal; + + /*Auto-Negotiation control register setting*/ + if ((retVal = rtl8367c_getAsicPHYReg(rtk_switch_port_L2P_get(port), PHY_AN_ADVERTISEMENT_REG, &phyData4)) != RT_ERR_OK) + return retVal; + + /*1000 BASE-T control register setting*/ + if ((retVal = rtl8367c_getAsicPHYReg(rtk_switch_port_L2P_get(port), PHY_1000_BASET_CONTROL_REG, &phyData9)) != RT_ERR_OK) + return retVal; + + if (phyData9 & (1 << 9)) + pAbility->Full_1000 = 1; + else + pAbility->Full_1000 = 0; + + if (phyData4 & (1 << 11)) + pAbility->AsyFC = 1; + else + pAbility->AsyFC = 0; + + if (phyData4 & ((1 << 10))) + pAbility->FC = 1; + else + pAbility->FC = 0; + + + if (phyData4 & (1 << 8)) + pAbility->Full_100 = 1; + else + pAbility->Full_100 = 0; + + if (phyData4 & (1 << 7)) + pAbility->Half_100 = 1; + else + pAbility->Half_100 = 0; + + if (phyData4 & (1 << 6)) + pAbility->Full_10 = 1; + else + pAbility->Full_10 = 0; + + if (phyData4 & (1 << 5)) + pAbility->Half_10 = 1; + else + pAbility->Half_10 = 0; + + + if (phyData0 & (1 << 12)) + pAbility->AutoNegotiation = 1; + else + pAbility->AutoNegotiation = 0; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_port_phyStatus_get + * Description: + * Get ethernet PHY linking status + * Input: + * port - Port id. + * Output: + * linkStatus - PHY link status + * speed - PHY link speed + * duplex - PHY duplex mode + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_PHY_REG_ID - Invalid PHY address + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy + * Note: + * API will return auto negotiation status of phy. + */ +rtk_api_ret_t dal_rtl8367c_port_phyStatus_get(rtk_port_t port, rtk_port_linkStatus_t *pLinkStatus, rtk_port_speed_t *pSpeed, rtk_port_duplex_t *pDuplex) +{ + rtk_api_ret_t retVal; + rtk_uint32 phyData; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_IS_UTP(port); + + if( (NULL == pLinkStatus) || (NULL == pSpeed) || (NULL == pDuplex) ) + return RT_ERR_NULL_POINTER; + + /*Get PHY resolved register*/ + if ((retVal = rtl8367c_getAsicPHYReg(rtk_switch_port_L2P_get(port), PHY_RESOLVED_REG, &phyData)) != RT_ERR_OK) + return retVal; + + /*check link status*/ + if (phyData & (1<<2)) + { + *pLinkStatus = 1; + + /*check link speed*/ + *pSpeed = (phyData&0x0030) >> 4; + + /*check link duplex*/ + *pDuplex = (phyData&0x0008) >> 3; + } + else + { + *pLinkStatus = 0; + *pSpeed = 0; + *pDuplex = 0; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_port_macForceLink_set + * Description: + * Set port force linking configuration. + * Input: + * port - port id. + * pPortability - port ability configuration + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can set Port/MAC force mode properties. + */ +rtk_api_ret_t dal_rtl8367c_port_macForceLink_set(rtk_port_t port, rtk_port_mac_ability_t *pPortability) +{ + rtk_api_ret_t retVal; + rtl8367c_port_ability_t ability; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_IS_UTP(port); + + if(NULL == pPortability) + return RT_ERR_NULL_POINTER; + + if (pPortability->forcemode >1|| pPortability->speed > 2 || pPortability->duplex > 1 || + pPortability->link > 1 || pPortability->nway > 1 || pPortability->txpause > 1 || pPortability->rxpause > 1) + return RT_ERR_INPUT; + + if ((retVal = rtl8367c_getAsicPortForceLink(rtk_switch_port_L2P_get(port), &ability)) != RT_ERR_OK) + return retVal; + + ability.forcemode = pPortability->forcemode; + ability.speed = pPortability->speed; + ability.duplex = pPortability->duplex; + ability.link = pPortability->link; + ability.nway = pPortability->nway; + ability.txpause = pPortability->txpause; + ability.rxpause = pPortability->rxpause; + + if ((retVal = rtl8367c_setAsicPortForceLink(rtk_switch_port_L2P_get(port), &ability)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_port_macForceLink_get + * Description: + * Get port force linking configuration. + * Input: + * port - Port id. + * Output: + * pPortability - port ability configuration + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can get Port/MAC force mode properties. + */ +rtk_api_ret_t dal_rtl8367c_port_macForceLink_get(rtk_port_t port, rtk_port_mac_ability_t *pPortability) +{ + rtk_api_ret_t retVal; + rtl8367c_port_ability_t ability; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_IS_UTP(port); + + if(NULL == pPortability) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicPortForceLink(rtk_switch_port_L2P_get(port), &ability)) != RT_ERR_OK) + return retVal; + + pPortability->forcemode = ability.forcemode; + pPortability->speed = ability.speed; + pPortability->duplex = ability.duplex; + pPortability->link = ability.link; + pPortability->nway = ability.nway; + pPortability->txpause = ability.txpause; + pPortability->rxpause = ability.rxpause; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_port_macForceLinkExt_set + * Description: + * Set external interface force linking configuration. + * Input: + * port - external port ID + * mode - external interface mode + * pPortability - port ability configuration + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can set external interface force mode properties. + * The external interface can be set to: + * - MODE_EXT_DISABLE, + * - MODE_EXT_RGMII, + * - MODE_EXT_MII_MAC, + * - MODE_EXT_MII_PHY, + * - MODE_EXT_TMII_MAC, + * - MODE_EXT_TMII_PHY, + * - MODE_EXT_GMII, + * - MODE_EXT_RMII_MAC, + * - MODE_EXT_RMII_PHY, + * - MODE_EXT_SGMII, + * - MODE_EXT_HSGMII, + * - MODE_EXT_1000X_100FX, + * - MODE_EXT_1000X, + * - MODE_EXT_100FX, + */ +rtk_api_ret_t dal_rtl8367c_port_macForceLinkExt_set(rtk_port_t port, rtk_mode_ext_t mode, rtk_port_mac_ability_t *pPortability) +{ + rtk_api_ret_t retVal; + rtl8367c_port_ability_t ability; + rtk_uint32 ext_id; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_IS_EXT(port); + + if(NULL == pPortability) + return RT_ERR_NULL_POINTER; + + if (mode >= MODE_EXT_END) + return RT_ERR_INPUT; + + if (mode == MODE_EXT_FIBER_2P5G) + return RT_ERR_CHIP_NOT_SUPPORTED; + + if(mode == MODE_EXT_HSGMII) + { + if (pPortability->forcemode > 1 || pPortability->speed != PORT_SPEED_2500M || pPortability->duplex != PORT_FULL_DUPLEX || + pPortability->link >= PORT_LINKSTATUS_END || pPortability->nway > 1 || pPortability->txpause > 1 || pPortability->rxpause > 1) + return RT_ERR_INPUT; + + if(rtk_switch_isHsgPort(port) != RT_ERR_OK) + return RT_ERR_PORT_ID; + } + else if (mode != MODE_EXT_DISABLE) + { + if (pPortability->forcemode > 1 || pPortability->speed > PORT_SPEED_1000M || pPortability->duplex >= PORT_DUPLEX_END || + pPortability->link >= PORT_LINKSTATUS_END || pPortability->nway > 1 || pPortability->txpause > 1 || pPortability->rxpause > 1) + return RT_ERR_INPUT; + } + + ext_id = port - 15; + + if(mode == MODE_EXT_DISABLE) + { + memset(&ability, 0x00, sizeof(rtl8367c_port_ability_t)); + if ((retVal = rtl8367c_setAsicPortForceLinkExt(ext_id, &ability)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicPortExtMode(ext_id, mode)) != RT_ERR_OK) + return retVal; + } + else + { + if ((retVal = rtl8367c_setAsicPortExtMode(ext_id, mode)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_getAsicPortForceLinkExt(ext_id, &ability)) != RT_ERR_OK) + return retVal; + + ability.forcemode = pPortability->forcemode; + ability.speed = (mode == MODE_EXT_HSGMII) ? PORT_SPEED_1000M : pPortability->speed; + ability.duplex = pPortability->duplex; + ability.link = pPortability->link; + ability.nway = pPortability->nway; + ability.txpause = pPortability->txpause; + ability.rxpause = pPortability->rxpause; + + if ((retVal = rtl8367c_setAsicPortForceLinkExt(ext_id, &ability)) != RT_ERR_OK) + return retVal; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_port_macForceLinkExt_get + * Description: + * Set external interface force linking configuration. + * Input: + * port - external port ID + * Output: + * pMode - external interface mode + * pPortability - port ability configuration + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can get external interface force mode properties. + */ +rtk_api_ret_t dal_rtl8367c_port_macForceLinkExt_get(rtk_port_t port, rtk_mode_ext_t *pMode, rtk_port_mac_ability_t *pPortability) +{ + rtk_api_ret_t retVal; + rtl8367c_port_ability_t ability; + rtk_uint32 ext_id; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_IS_EXT(port); + + if(NULL == pMode) + return RT_ERR_NULL_POINTER; + + if(NULL == pPortability) + return RT_ERR_NULL_POINTER; + + ext_id = port - 15; + + if ((retVal = rtl8367c_getAsicPortExtMode(ext_id, (rtk_uint32 *)pMode)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_getAsicPortForceLinkExt(ext_id, &ability)) != RT_ERR_OK) + return retVal; + + pPortability->forcemode = ability.forcemode; + pPortability->speed = (*pMode == MODE_EXT_HSGMII) ? PORT_SPEED_2500M : ability.speed; + pPortability->duplex = ability.duplex; + pPortability->link = ability.link; + pPortability->nway = ability.nway; + pPortability->txpause = ability.txpause; + pPortability->rxpause = ability.rxpause; + + return RT_ERR_OK; + +} + +/* Function Name: + * dal_rtl8367c_port_macStatus_get + * Description: + * Get port link status. + * Input: + * port - Port id. + * Output: + * pPortstatus - port ability configuration + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can get Port/PHY properties. + */ +rtk_api_ret_t dal_rtl8367c_port_macStatus_get(rtk_port_t port, rtk_port_mac_ability_t *pPortstatus) +{ + rtk_api_ret_t retVal; + rtl8367c_port_status_t status; + rtk_uint32 hsgsel; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if(NULL == pPortstatus) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicPortStatus(rtk_switch_port_L2P_get(port), &status)) != RT_ERR_OK) + return retVal; + + + pPortstatus->duplex = status.duplex; + pPortstatus->link = status.link; + pPortstatus->nway = status.nway; + pPortstatus->txpause = status.txpause; + pPortstatus->rxpause = status.rxpause; + + if( (retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_MAC8_SEL_HSGMII_OFFSET, &hsgsel)) != RT_ERR_OK) + return retVal; + + if( (rtk_switch_isHsgPort(port) == RT_ERR_OK) && (hsgsel == 1) ) + pPortstatus->speed = PORT_SPEED_2500M; + else + pPortstatus->speed = status.speed; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_port_macLocalLoopbackEnable_set + * Description: + * Set Port Local Loopback. (Redirect TX to RX.) + * Input: + * port - Port id. + * enable - Loopback state, 0:disable, 1:enable + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can enable/disable Local loopback in MAC. + * For UTP port, This API will also enable the digital + * loopback bit in PHY register for sync of speed between + * PHY and MAC. For EXT port, users need to force the + * link state by themself. + */ +rtk_api_ret_t dal_rtl8367c_port_macLocalLoopbackEnable_set(rtk_port_t port, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + rtk_uint32 data; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if(enable >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if ((retVal = rtl8367c_setAsicPortLoopback(rtk_switch_port_L2P_get(port), enable)) != RT_ERR_OK) + return retVal; + + if(rtk_switch_isUtpPort(port) == RT_ERR_OK) + { + if ((retVal = rtl8367c_getAsicPHYReg(rtk_switch_port_L2P_get(port), PHY_CONTROL_REG, &data)) != RT_ERR_OK) + return retVal; + + if(enable == ENABLED) + data |= (0x0001 << 14); + else + data &= ~(0x0001 << 14); + + if ((retVal = rtl8367c_setAsicPHYReg(rtk_switch_port_L2P_get(port), PHY_CONTROL_REG, data)) != RT_ERR_OK) + return retVal; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_port_macLocalLoopbackEnable_get + * Description: + * Get Port Local Loopback. (Redirect TX to RX.) + * Input: + * port - Port id. + * Output: + * pEnable - Loopback state, 0:disable, 1:enable + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * None. + */ +rtk_api_ret_t dal_rtl8367c_port_macLocalLoopbackEnable_get(rtk_port_t port, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if(NULL == pEnable) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicPortLoopback(rtk_switch_port_L2P_get(port), pEnable)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_port_phyReg_set + * Description: + * Set PHY register data of the specific port. + * Input: + * port - port id. + * reg - Register id + * regData - Register data + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_PHY_REG_ID - Invalid PHY address + * RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy + * Note: + * This API can set PHY register data of the specific port. + */ +rtk_api_ret_t dal_rtl8367c_port_phyReg_set(rtk_port_t port, rtk_port_phy_reg_t reg, rtk_port_phy_data_t regData) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_IS_UTP(port); + + if ((retVal = rtl8367c_setAsicPHYReg(rtk_switch_port_L2P_get(port), reg, regData)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_port_phyReg_get + * Description: + * Get PHY register data of the specific port. + * Input: + * port - Port id. + * reg - Register id + * Output: + * pData - Register data + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_PHY_REG_ID - Invalid PHY address + * RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy + * Note: + * This API can get PHY register data of the specific port. + */ +rtk_api_ret_t dal_rtl8367c_port_phyReg_get(rtk_port_t port, rtk_port_phy_reg_t reg, rtk_port_phy_data_t *pData) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_IS_UTP(port); + + if ((retVal = rtl8367c_getAsicPHYReg(rtk_switch_port_L2P_get(port), reg, pData)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_port_phyOCPReg_set + * Description: + * Set PHY OCP register + * Input: + * port - PHY ID + * ocpAddr - OCP register address + * ocpData - OCP Data. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_BUSYWAIT_TIMEOUT - Timeout + * Note: + * None. + */ +rtk_api_ret_t dal_rtl8367c_port_phyOCPReg_set(rtk_port_t port, rtk_uint32 ocpAddr, rtk_uint32 ocpData ) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_IS_UTP(port); + + if ((retVal = rtl8367c_setAsicPHYOCPReg(rtk_switch_port_L2P_get(port), ocpAddr, ocpData)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_port_phyOCPReg_get + * Description: + * Set PHY OCP register + * Input: + * phyNo - PHY ID + * ocpAddr - OCP register address + * Output: + * pRegData - OCP data. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * None. + */ +rtk_api_ret_t dal_rtl8367c_port_phyOCPReg_get(rtk_port_t port, rtk_uint32 ocpAddr, rtk_uint32 *pRegData ) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_IS_UTP(port); + + if (pRegData == NULL) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicPHYOCPReg(rtk_switch_port_L2P_get(port), ocpAddr, pRegData)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_port_backpressureEnable_set + * Description: + * Set the half duplex backpressure enable status of the specific port. + * Input: + * port - port id. + * enable - Back pressure status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * This API can set the half duplex backpressure enable status of the specific port. + * The half duplex backpressure enable status of the port is as following: + * - DISABLE(Defer) + * - ENABLE (Backpressure) + */ +rtk_api_ret_t dal_rtl8367c_port_backpressureEnable_set(rtk_port_t port, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (port != RTK_WHOLE_SYSTEM) + return RT_ERR_PORT_ID; + + if (enable >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if ((retVal = rtl8367c_setAsicPortJamMode(!enable)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_port_backpressureEnable_get + * Description: + * Get the half duplex backpressure enable status of the specific port. + * Input: + * port - Port id. + * Output: + * pEnable - Back pressure status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can get the half duplex backpressure enable status of the specific port. + * The half duplex backpressure enable status of the port is as following: + * - DISABLE(Defer) + * - ENABLE (Backpressure) + */ +rtk_api_ret_t dal_rtl8367c_port_backpressureEnable_get(rtk_port_t port, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (port != RTK_WHOLE_SYSTEM) + return RT_ERR_PORT_ID; + + if(NULL == pEnable) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicPortJamMode(®Data)) != RT_ERR_OK) + return retVal; + + *pEnable = !regData; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_port_adminEnable_set + * Description: + * Set port admin configuration of the specific port. + * Input: + * port - port id. + * enable - Back pressure status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * This API can set port admin configuration of the specific port. + * The port admin configuration of the port is as following: + * - DISABLE + * - ENABLE + */ +rtk_api_ret_t dal_rtl8367c_port_adminEnable_set(rtk_port_t port, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + rtk_uint32 data; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_IS_UTP(port); + + if (enable >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if ((retVal = rtl8367c_getAsicPHYReg(rtk_switch_port_L2P_get(port), PHY_CONTROL_REG, &data)) != RT_ERR_OK) + return retVal; + + if (ENABLED == enable) + { + data &= 0xF7FF; + data |= 0x0200; + } + else if (DISABLED == enable) + { + data |= 0x0800; + } + + if ((retVal = rtl8367c_setAsicPHYReg(rtk_switch_port_L2P_get(port), PHY_CONTROL_REG, data)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_port_adminEnable_get + * Description: + * Get port admin configurationof the specific port. + * Input: + * port - Port id. + * Output: + * pEnable - Back pressure status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can get port admin configuration of the specific port. + * The port admin configuration of the port is as following: + * - DISABLE + * - ENABLE + */ +rtk_api_ret_t dal_rtl8367c_port_adminEnable_get(rtk_port_t port, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + rtk_uint32 data; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_IS_UTP(port); + + if(NULL == pEnable) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicPHYReg(port, PHY_CONTROL_REG, &data)) != RT_ERR_OK) + return retVal; + + if ( (data & 0x0800) == 0x0800) + { + *pEnable = DISABLED; + } + else + { + *pEnable = ENABLED; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_port_isolation_set + * Description: + * Set permitted port isolation portmask + * Input: + * port - port id. + * pPortmask - Permit port mask + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_PORT_MASK - Invalid portmask. + * Note: + * This API set the port mask that a port can trasmit packet to of each port + * A port can only transmit packet to ports included in permitted portmask + */ +rtk_api_ret_t dal_rtl8367c_port_isolation_set(rtk_port_t port, rtk_portmask_t *pPortmask) +{ + rtk_api_ret_t retVal; + rtk_uint32 pmask; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if(NULL == pPortmask) + return RT_ERR_NULL_POINTER; + + /* check port mask */ + RTK_CHK_PORTMASK_VALID(pPortmask); + + if ((retVal = rtk_switch_portmask_L2P_get(pPortmask, &pmask)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicPortIsolationPermittedPortmask(rtk_switch_port_L2P_get(port), pmask)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_port_isolation_get + * Description: + * Get permitted port isolation portmask + * Input: + * port - Port id. + * Output: + * pPortmask - Permit port mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API get the port mask that a port can trasmit packet to of each port + * A port can only transmit packet to ports included in permitted portmask + */ +rtk_api_ret_t dal_rtl8367c_port_isolation_get(rtk_port_t port, rtk_portmask_t *pPortmask) +{ + rtk_api_ret_t retVal; + rtk_uint32 pmask; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if(NULL == pPortmask) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicPortIsolationPermittedPortmask(rtk_switch_port_L2P_get(port), &pmask)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtk_switch_portmask_P2L_get(pmask, pPortmask)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_port_rgmiiDelayExt_set + * Description: + * Set RGMII interface delay value for TX and RX. + * Input: + * txDelay - TX delay value, 1 for delay 2ns and 0 for no-delay + * rxDelay - RX delay value, 0~7 for delay setup. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can set external interface 2 RGMII delay. + * In TX delay, there are 2 selection: no-delay and 2ns delay. + * In RX dekay, there are 8 steps for delay tunning. 0 for no-delay, and 7 for maximum delay. + * Note. This API should be called before rtk_port_macForceLinkExt_set(). + */ +rtk_api_ret_t dal_rtl8367c_port_rgmiiDelayExt_set(rtk_port_t port, rtk_data_t txDelay, rtk_data_t rxDelay) +{ + rtk_api_ret_t retVal; + rtk_uint32 regAddr, regData; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_IS_EXT(port); + + if ((txDelay > 1) || (rxDelay > 7)) + return RT_ERR_INPUT; + + if(port == EXT_PORT0) + regAddr = RTL8367C_REG_EXT1_RGMXF; + else if(port == EXT_PORT1) + regAddr = RTL8367C_REG_EXT2_RGMXF; + else + return RT_ERR_INPUT; + + if ((retVal = rtl8367c_getAsicReg(regAddr, ®Data)) != RT_ERR_OK) + return retVal; + + regData = (regData & 0xFFF0) | ((txDelay << 3) & 0x0008) | (rxDelay & 0x0007); + + if ((retVal = rtl8367c_setAsicReg(regAddr, regData)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_port_rgmiiDelayExt_get + * Description: + * Get RGMII interface delay value for TX and RX. + * Input: + * None + * Output: + * pTxDelay - TX delay value + * pRxDelay - RX delay value + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can set external interface 2 RGMII delay. + * In TX delay, there are 2 selection: no-delay and 2ns delay. + * In RX dekay, there are 8 steps for delay tunning. 0 for n0-delay, and 7 for maximum delay. + */ +rtk_api_ret_t dal_rtl8367c_port_rgmiiDelayExt_get(rtk_port_t port, rtk_data_t *pTxDelay, rtk_data_t *pRxDelay) +{ + rtk_api_ret_t retVal; + rtk_uint32 regAddr, regData; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_IS_EXT(port); + + if( (NULL == pTxDelay) || (NULL == pRxDelay) ) + return RT_ERR_NULL_POINTER; + + if(port == EXT_PORT0) + regAddr = RTL8367C_REG_EXT1_RGMXF; + else if(port == EXT_PORT1) + regAddr = RTL8367C_REG_EXT2_RGMXF; + else + return RT_ERR_INPUT; + + if ((retVal = rtl8367c_getAsicReg(regAddr, ®Data)) != RT_ERR_OK) + return retVal; + + *pTxDelay = (regData & 0x0008) >> 3; + *pRxDelay = regData & 0x0007; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_port_phyEnableAll_set + * Description: + * Set all PHY enable status. + * Input: + * enable - PHY Enable State. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * This API can set all PHY status. + * The configuration of all PHY is as following: + * - DISABLE + * - ENABLE + */ +rtk_api_ret_t dal_rtl8367c_port_phyEnableAll_set(rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + rtk_uint32 data; + rtk_uint32 port; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (enable >= RTK_ENABLE_END) + return RT_ERR_ENABLE; + + if ((retVal = rtl8367c_setAsicPortEnableAll(enable)) != RT_ERR_OK) + return retVal; + + RTK_SCAN_ALL_LOG_PORT(port) + { + if(rtk_switch_isUtpPort(port) == RT_ERR_OK) + { + if ((retVal = dal_rtl8367c_port_phyReg_get(port, PHY_CONTROL_REG, &data)) != RT_ERR_OK) + return retVal; + + if (ENABLED == enable) + { + data &= 0xF7FF; + data |= 0x0200; + } + else + { + data |= 0x0800; + } + + if ((retVal = dal_rtl8367c_port_phyReg_set(port, PHY_CONTROL_REG, data)) != RT_ERR_OK) + return retVal; + } + } + + return RT_ERR_OK; + +} + +/* Function Name: + * dal_rtl8367c_port_phyEnableAll_get + * Description: + * Get all PHY enable status. + * Input: + * None + * Output: + * pEnable - PHY Enable State. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API can set all PHY status. + * The configuration of all PHY is as following: + * - DISABLE + * - ENABLE + */ +rtk_api_ret_t dal_rtl8367c_port_phyEnableAll_get(rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pEnable) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicPortEnableAll(pEnable)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_port_efid_set + * Description: + * Set port-based enhanced filtering database + * Input: + * port - Port id. + * efid - Specified enhanced filtering database. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_FID - Invalid fid. + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API can set port-based enhanced filtering database. + */ +rtk_api_ret_t dal_rtl8367c_port_efid_set(rtk_port_t port, rtk_data_t efid) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + /* efid must be 0~7 */ + if (efid > RTK_EFID_MAX) + return RT_ERR_INPUT; + + if ((retVal = rtl8367c_setAsicPortIsolationEfid(rtk_switch_port_L2P_get(port), efid))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_port_efid_get + * Description: + * Get port-based enhanced filtering database + * Input: + * port - Port id. + * Output: + * pEfid - Specified enhanced filtering database. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API can get port-based enhanced filtering database status. + */ +rtk_api_ret_t dal_rtl8367c_port_efid_get(rtk_port_t port, rtk_data_t *pEfid) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if(NULL == pEfid) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicPortIsolationEfid(rtk_switch_port_L2P_get(port), pEfid))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_port_phyComboPortMedia_set + * Description: + * Set Combo port media type + * Input: + * port - Port id. + * media - Media (COPPER or FIBER or AUTO) + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API can Set Combo port media type. + */ +rtk_api_ret_t dal_rtl8367c_port_phyComboPortMedia_set(rtk_port_t port, rtk_port_media_t media) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + rtk_uint32 idx; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_IS_UTP(port); + + /* Check Combo Port ID */ + RTK_CHK_PORT_IS_COMBO(port); + + if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0249)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_getAsicReg(0x1300, ®Data)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0000)) != RT_ERR_OK) + return retVal; + + if(regData != 0x6367) + return RT_ERR_CHIP_NOT_SUPPORTED; + + if(media == PORT_MEDIA_FIBER) + { + /* software init */ + if ((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_CHIP_RESET, RTL8367C_DW8051_RST_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_MISCELLANEOUS_CONFIGURE0, RTL8367C_DW8051_EN_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_DW8051_RDY, RTL8367C_ACS_IROM_ENABLE_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_DW8051_RDY, RTL8367C_IROM_MSB_OFFSET, 0)) != RT_ERR_OK) + return retVal; + + for(idx = 0; idx < FIBER_INIT_SIZE; idx++) + { + if ((retVal = rtl8367c_setAsicReg(0xE000 + idx, (rtk_uint32)Fiber[idx])) != RT_ERR_OK) + return retVal; + } + + if ((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_DW8051_RDY, RTL8367C_IROM_MSB_OFFSET, 0)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_DW8051_RDY, RTL8367C_ACS_IROM_ENABLE_OFFSET, 0)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_CHIP_RESET, RTL8367C_DW8051_RST_OFFSET, 0)) != RT_ERR_OK) + return retVal; + } + else if(media == PORT_MEDIA_AUTO) + { + /* software init */ + if ((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_CHIP_RESET, RTL8367C_DW8051_RST_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_MISCELLANEOUS_CONFIGURE0, RTL8367C_DW8051_EN_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_DW8051_RDY, RTL8367C_ACS_IROM_ENABLE_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_DW8051_RDY, RTL8367C_IROM_MSB_OFFSET, 0)) != RT_ERR_OK) + return retVal; + + for(idx = 0; idx < FIBER_AUTO_INIT_SIZE; idx++) + { + if ((retVal = rtl8367c_setAsicReg(0xE000 + idx, (rtk_uint32)Fiber_auto[idx])) != RT_ERR_OK) + return retVal; + } + + if ((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_DW8051_RDY, RTL8367C_IROM_MSB_OFFSET, 0)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_DW8051_RDY, RTL8367C_ACS_IROM_ENABLE_OFFSET, 0)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_CHIP_RESET, RTL8367C_DW8051_RST_OFFSET, 0)) != RT_ERR_OK) + return retVal; + } + else if(media == PORT_MEDIA_COPPER) + { + if ((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_UTP_FIB_DET, RTL8367C_UTP_FIRST_OFFSET, 1))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_DW8051_RDY, RTL8367C_DW8051_READY_OFFSET, 0)) != RT_ERR_OK) + return retVal; + } + else + return RT_ERR_INPUT; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_port_phyComboPortMedia_get + * Description: + * Get Combo port media type + * Input: + * port - Port id. + * Output: + * pMedia - Media (COPPER or FIBER or AUTO) + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API can Set Combo port media type. + */ +rtk_api_ret_t dal_rtl8367c_port_phyComboPortMedia_get(rtk_port_t port, rtk_port_media_t *pMedia) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + rtk_uint32 data; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_IS_UTP(port); + + /* Check Combo Port ID */ + RTK_CHK_PORT_IS_COMBO(port); + + if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0249)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_getAsicReg(0x1300, ®Data)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0000)) != RT_ERR_OK) + return retVal; + + if(regData != 0x6367) + { + *pMedia = PORT_MEDIA_COPPER; + } + else + { + if ((retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_UTP_FIB_DET, RTL8367C_UTP_FIB_DISAUTODET_OFFSET, &data))!=RT_ERR_OK) + return retVal; + if(data == 0) + { + *pMedia = PORT_MEDIA_AUTO; + } + else + { + if ((retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_UTP_FIB_DET, RTL8367C_UTP_FIRST_OFFSET, &data))!=RT_ERR_OK) + return retVal; + + if(data == 1) + *pMedia = PORT_MEDIA_COPPER; + else + *pMedia = PORT_MEDIA_FIBER; + } + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_port_rtctEnable_set + * Description: + * Enable RTCT test + * Input: + * pPortmask - Port mask of RTCT enabled port + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Invalid port mask. + * Note: + * The API can enable RTCT Test + */ +rtk_api_ret_t dal_rtl8367c_port_rtctEnable_set(rtk_portmask_t *pPortmask) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Mask Valid */ + RTK_CHK_PORTMASK_VALID_ONLY_UTP(pPortmask); + + if ((retVal = rtl8367c_setAsicPortRTCTEnable(pPortmask->bits[0]))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_port_rtctDisable_set + * Description: + * Disable RTCT test + * Input: + * pPortmask - Port mask of RTCT disabled port + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Invalid port mask. + * Note: + * The API can disable RTCT Test + */ +rtk_api_ret_t dal_rtl8367c_port_rtctDisable_set(rtk_portmask_t *pPortmask) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Mask Valid */ + RTK_CHK_PORTMASK_VALID_ONLY_UTP(pPortmask); + + if ((retVal = rtl8367c_setAsicPortRTCTDisable(pPortmask->bits[0]))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_port_rtctResult_get + * Description: + * Get the result of RTCT test + * Input: + * port - Port ID + * Output: + * pRtctResult - The result of RTCT result + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port ID. + * RT_ERR_PHY_RTCT_NOT_FINISH - Testing does not finish. + * Note: + * The API can get RTCT test result. + * RTCT test may takes 4.8 seconds to finish its test at most. + * Thus, if this API return RT_ERR_PHY_RTCT_NOT_FINISH or + * other error code, the result can not be referenced and + * user should call this API again until this API returns + * a RT_ERR_OK. + * The result is stored at pRtctResult->ge_result + * pRtctResult->linkType is unused. + * The unit of channel length is 2.5cm. Ex. 300 means 300 * 2.5 = 750cm = 7.5M + */ +rtk_api_ret_t dal_rtl8367c_port_rtctResult_get(rtk_port_t port, rtk_rtctResult_t *pRtctResult) +{ + rtk_api_ret_t retVal; + rtl8367c_port_rtct_result_t result; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_IS_UTP(port); + + memset(pRtctResult, 0x00, sizeof(rtk_rtctResult_t)); + if ((retVal = rtl8367c_getAsicPortRTCTResult(port, &result))!=RT_ERR_OK) + return retVal; + + pRtctResult->result.ge_result.channelALen = result.channelALen; + pRtctResult->result.ge_result.channelBLen = result.channelBLen; + pRtctResult->result.ge_result.channelCLen = result.channelCLen; + pRtctResult->result.ge_result.channelDLen = result.channelDLen; + + pRtctResult->result.ge_result.channelALinedriver = result.channelALinedriver; + pRtctResult->result.ge_result.channelBLinedriver = result.channelBLinedriver; + pRtctResult->result.ge_result.channelCLinedriver = result.channelCLinedriver; + pRtctResult->result.ge_result.channelDLinedriver = result.channelDLinedriver; + + pRtctResult->result.ge_result.channelAMismatch = result.channelAMismatch; + pRtctResult->result.ge_result.channelBMismatch = result.channelBMismatch; + pRtctResult->result.ge_result.channelCMismatch = result.channelCMismatch; + pRtctResult->result.ge_result.channelDMismatch = result.channelDMismatch; + + pRtctResult->result.ge_result.channelAOpen = result.channelAOpen; + pRtctResult->result.ge_result.channelBOpen = result.channelBOpen; + pRtctResult->result.ge_result.channelCOpen = result.channelCOpen; + pRtctResult->result.ge_result.channelDOpen = result.channelDOpen; + + pRtctResult->result.ge_result.channelAShort = result.channelAShort; + pRtctResult->result.ge_result.channelBShort = result.channelBShort; + pRtctResult->result.ge_result.channelCShort = result.channelCShort; + pRtctResult->result.ge_result.channelDShort = result.channelDShort; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_port_sds_reset + * Description: + * Reset Serdes + * Input: + * port - Port ID + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API can reset Serdes + */ +rtk_api_ret_t dal_rtl8367c_port_sds_reset(rtk_port_t port) +{ + rtk_uint32 ext_id; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + if(rtk_switch_isSgmiiPort(port) != RT_ERR_OK) + return RT_ERR_PORT_ID; + + ext_id = port - 15; + return rtl8367c_sdsReset(ext_id); +} + +/* Function Name: + * dal_rtl8367c_port_sgmiiLinkStatus_get + * Description: + * Get SGMII status + * Input: + * port - Port ID + * Output: + * pSignalDetect - Signal detect + * pSync - Sync + * pLink - Link + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API can reset Serdes + */ +rtk_api_ret_t dal_rtl8367c_port_sgmiiLinkStatus_get(rtk_port_t port, rtk_data_t *pSignalDetect, rtk_data_t *pSync, rtk_port_linkStatus_t *pLink) +{ + rtk_uint32 ext_id; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + if(rtk_switch_isSgmiiPort(port) != RT_ERR_OK) + return RT_ERR_PORT_ID; + + if(NULL == pSignalDetect) + return RT_ERR_NULL_POINTER; + + if(NULL == pSync) + return RT_ERR_NULL_POINTER; + + if(NULL == pLink) + return RT_ERR_NULL_POINTER; + + ext_id = port - 15; + return rtl8367c_getSdsLinkStatus(ext_id, (rtk_uint32 *)pSignalDetect, (rtk_uint32 *)pSync, (rtk_uint32 *)pLink); +} + +/* Function Name: + * dal_rtl8367c_port_sgmiiNway_set + * Description: + * Configure SGMII/HSGMII port Nway state + * Input: + * port - Port ID + * state - Nway state + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API configure SGMII/HSGMII port Nway state + */ +rtk_api_ret_t dal_rtl8367c_port_sgmiiNway_set(rtk_port_t port, rtk_enable_t state) +{ + rtk_uint32 ext_id; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + if(rtk_switch_isSgmiiPort(port) != RT_ERR_OK) + return RT_ERR_PORT_ID; + + if(state >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + ext_id = port - 15; + return rtl8367c_setSgmiiNway(ext_id, (rtk_uint32)state); +} + +/* Function Name: + * dal_rtl8367c_port_sgmiiNway_get + * Description: + * Get SGMII/HSGMII port Nway state + * Input: + * port - Port ID + * Output: + * pState - Nway state + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API can get SGMII/HSGMII port Nway state + */ +rtk_api_ret_t dal_rtl8367c_port_sgmiiNway_get(rtk_port_t port, rtk_enable_t *pState) +{ + rtk_uint32 ext_id; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + if(rtk_switch_isSgmiiPort(port) != RT_ERR_OK) + return RT_ERR_PORT_ID; + + if(NULL == pState) + return RT_ERR_NULL_POINTER; + + ext_id = port - 15; + return rtl8367c_getSgmiiNway(ext_id, (rtk_uint32 *)pState); +} + + +/* Function Name: + * dal_rtl8367c_port_fiberAbilityExt_set + * Description: + * Get SGMII/HSGMII port Nway state + * Input: + * port - Port ID + * pause -pause state + * asypause -asypause state + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API can get SGMII/HSGMII port Nway state + */ +rtk_api_ret_t dal_rtl8367c_port_fiberAbilityExt_set(rtk_port_t port, rtk_uint32 pause, rtk_uint32 asypause) +{ + rtk_uint32 ext_id; + + ext_id = port - 15; + + return rtl8367c_setFiberAbilityExt(ext_id, pause, asypause); + +} + +/* Function Name: + * dal_rtl8367c_port_fiberAbilityExt_get + * Description: + * Get SGMII/HSGMII port Nway state + * Input: + * port - Port ID + * Output: + * pPause -pause state + * pAsypause -asypause state + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API can get SGMII/HSGMII port Nway state + */ +rtk_api_ret_t dal_rtl8367c_port_fiberAbilityExt_get(rtk_port_t port, rtk_uint32* pPause, rtk_uint32* pAsypause) +{ + rtk_uint32 ext_id; + + ext_id = port - 15; + + return rtl8367c_getFiberAbilityExt(ext_id, pPause, pAsypause); + +} + +/* Function Name: + * dal_rtl8367c_port_autoDos_set + * Description: + * Set Auto Dos state + * Input: + * type - Auto DoS type + * state - 1: Eanble(Drop), 0: Disable(Forward) + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set Auto Dos state + */ +rtk_api_ret_t dal_rtl8367c_port_autoDos_set(rtk_port_autoDosType_t type, rtk_enable_t state) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (type >= AUTODOS_END) + return RT_ERR_INPUT; + + if (state >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if ((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_DOS_CFG, RTL8367C_DROP_DAEQSA_OFFSET + type, (state == ENABLED) ? 1 : 0)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_port_autoDos_get + * Description: + * Get Auto Dos state + * Input: + * type - Auto DoS type + * Output: + * pState - 1: Eanble(Drop), 0: Disable(Forward) + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Null Pointer + * Note: + * The API can get Auto Dos state + */ +rtk_api_ret_t dal_rtl8367c_port_autoDos_get(rtk_port_autoDosType_t type, rtk_enable_t *pState) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (type >= AUTODOS_END) + return RT_ERR_INPUT; + + if (pState == NULL) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_DOS_CFG, RTL8367C_DROP_DAEQSA_OFFSET + type, ®Data)) != RT_ERR_OK) + return retVal; + + *pState = (regData == 1) ? ENABLED : DISABLED; + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_port_phyMdx_set + * Description: + * Set PHY MDI/MDIX state + * Input: + * port - port ID + * mode - PHY MDI/MDIX mode + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set PHY MDI/MDIX state + */ +rtk_api_ret_t dal_rtl8367c_port_phyMdx_set(rtk_port_t port, rtk_port_phy_mdix_mode_t mode) +{ + rtk_uint32 regData; + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_IS_UTP(port); + + switch (mode) + { + case PHY_AUTO_CROSSOVER_MODE: + if ((retVal = rtl8367c_getAsicPHYReg(rtk_switch_port_L2P_get(port), 24, ®Data))!=RT_ERR_OK) + return retVal; + + regData &= ~(0x0001 << 9); + + if ((retVal = rtl8367c_setAsicPHYReg(rtk_switch_port_L2P_get(port), 24, regData))!=RT_ERR_OK) + return retVal; + break; + case PHY_FORCE_MDI_MODE: + if ((retVal = rtl8367c_getAsicPHYReg(rtk_switch_port_L2P_get(port), 24, ®Data))!=RT_ERR_OK) + return retVal; + + regData |= (0x0001 << 9); + regData |= (0x0001 << 8); + + if ((retVal = rtl8367c_setAsicPHYReg(rtk_switch_port_L2P_get(port), 24, regData))!=RT_ERR_OK) + return retVal; + break; + case PHY_FORCE_MDIX_MODE: + if ((retVal = rtl8367c_getAsicPHYReg(rtk_switch_port_L2P_get(port), 24, ®Data))!=RT_ERR_OK) + return retVal; + + regData |= (0x0001 << 9); + regData &= ~(0x0001 << 8); + + if ((retVal = rtl8367c_setAsicPHYReg(rtk_switch_port_L2P_get(port), 24, regData))!=RT_ERR_OK) + return retVal; + break; + default: + return RT_ERR_INPUT; + break; + } + + /* Restart N-way */ + if ((retVal = rtl8367c_getAsicPHYReg(rtk_switch_port_L2P_get(port), 0, ®Data))!=RT_ERR_OK) + return retVal; + + regData |= (0x0001 << 9); + + if ((retVal = rtl8367c_setAsicPHYReg(rtk_switch_port_L2P_get(port), 0, regData))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_port_phyMdx_get + * Description: + * Get PHY MDI/MDIX state + * Input: + * port - port ID + * Output: + * pMode - PHY MDI/MDIX mode + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can get PHY MDI/MDIX state + */ +rtk_api_ret_t dal_rtl8367c_port_phyMdx_get(rtk_port_t port, rtk_port_phy_mdix_mode_t *pMode) +{ + rtk_uint32 regData; + rtk_api_ret_t retVal; + + if ((retVal = rtl8367c_getAsicPHYReg(rtk_switch_port_L2P_get(port), 24, ®Data))!=RT_ERR_OK) + return retVal; + + if(regData & (0x0001 << 9)) + { + if(regData & (0x0001 << 8)) + *pMode = PHY_FORCE_MDI_MODE; + else + *pMode = PHY_FORCE_MDIX_MODE; + } + else + *pMode = PHY_AUTO_CROSSOVER_MODE; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_port_phyMdxStatus_get + * Description: + * Get PHY MDI/MDIX status + * Input: + * port - port ID + * Output: + * pStatus - PHY MDI/MDIX status + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can get PHY MDI/MDIX status + */ +rtk_api_ret_t dal_rtl8367c_port_phyMdxStatus_get(rtk_port_t port, rtk_port_phy_mdix_status_t *pStatus) +{ + rtk_uint32 regData; + rtk_api_ret_t retVal; + + if ((retVal = rtl8367c_getAsicPHYReg(rtk_switch_port_L2P_get(port), 24, ®Data))!=RT_ERR_OK) + return retVal; + + if (regData & (0x0001 << 9)) + { + if (regData & (0x0001 << 8)) + *pStatus = PHY_STATUS_FORCE_MDI_MODE; + else + *pStatus = PHY_STATUS_FORCE_MDIX_MODE; + } + else + { + if ((retVal = rtl8367c_getAsicPHYReg(rtk_switch_port_L2P_get(port), 26, ®Data))!=RT_ERR_OK) + return retVal; + + if (regData & (0x0001 << 1)) + *pStatus = PHY_STATUS_AUTO_MDI_MODE; + else + *pStatus = PHY_STATUS_AUTO_MDIX_MODE; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_port_phyTestMode_set + * Description: + * Set PHY in test mode. + * Input: + * port - port id. + * mode - PHY test mode 0:normal 1:test mode 1 2:test mode 2 3: test mode 3 4:test mode 4 5~7:reserved + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy + * RT_ERR_NOT_ALLOWED - The Setting is not allowed, caused by set more than 1 port in Test mode. + * Note: + * Set PHY in test mode and only one PHY can be in test mode at the same time. + * It means API will return FAILED if other PHY is in test mode. + * This API only provide test mode 1 & 4 setup. + */ +rtk_api_ret_t dal_rtl8367c_port_phyTestMode_set(rtk_port_t port, rtk_port_phy_test_mode_t mode) +{ + rtk_uint32 data, regData, i; + rtk_api_ret_t retVal; + + RTK_CHK_PORT_IS_UTP(port); + + if(mode >= PHY_TEST_MODE_END) + return RT_ERR_INPUT; + + if( (mode == PHY_TEST_MODE_2) || (mode == PHY_TEST_MODE_3) ) + return RT_ERR_INPUT; + + if (PHY_TEST_MODE_NORMAL != mode) + { + /* Other port should be Normal mode */ + RTK_SCAN_ALL_LOG_PORT(i) + { + if(rtk_switch_isUtpPort(i) == RT_ERR_OK) + { + if(i != port) + { + if ((retVal = rtl8367c_getAsicPHYReg(rtk_switch_port_L2P_get(i), 9, &data)) != RT_ERR_OK) + return retVal; + + if((data & 0xE000) != 0) + return RT_ERR_NOT_ALLOWED; + } + } + } + } + + if (PHY_TEST_MODE_4 == mode) + { + if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0249)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_getAsicReg(0x1300, ®Data)) != RT_ERR_OK) + return retVal; + + if(regData == 0x6511) + { + if ((retVal = rtl8367c_setAsicPHYOCPReg(rtk_switch_port_L2P_get(port), 0xa436, 0x8081)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicPHYOCPReg(rtk_switch_port_L2P_get(port), 0xa438, 0x7e00)) != RT_ERR_OK) + return retVal; + } + } + + if ((retVal = rtl8367c_getAsicPHYReg(rtk_switch_port_L2P_get(port), 9, &data)) != RT_ERR_OK) + return retVal; + + data &= ~0xE000; + data |= (mode << 13); + if ((retVal = rtl8367c_setAsicPHYReg(rtk_switch_port_L2P_get(port), 9, data)) != RT_ERR_OK) + return retVal; + + if (PHY_TEST_MODE_4 == mode) + { + if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0249)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_getAsicReg(0x1300, ®Data)) != RT_ERR_OK) + return retVal; + + if( (regData == 0x0276) || (regData == 0x0597) ) + { + if ((retVal = rtl8367c_setAsicPHYOCPReg(rtk_switch_port_L2P_get(port), 0xbcc2, 0xF4F4)) != RT_ERR_OK) + return retVal; + } + + if( (regData == 0x6367) ) + { + if ((retVal = rtl8367c_setAsicPHYOCPReg(rtk_switch_port_L2P_get(port), 0xa436, 0x80c1)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicPHYOCPReg(rtk_switch_port_L2P_get(port), 0xa438, 0xfe00)) != RT_ERR_OK) + return retVal; + } + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_port_phyTestMode_get + * Description: + * Get PHY in which test mode. + * Input: + * port - Port id. + * Output: + * mode - PHY test mode 0:normal 1:test mode 1 2:test mode 2 3: test mode 3 4:test mode 4 5~7:reserved + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy + * Note: + * Get test mode of PHY from register setting 9.15 to 9.13. + */ +rtk_api_ret_t dal_rtl8367c_port_phyTestMode_get(rtk_port_t port, rtk_port_phy_test_mode_t *pMode) +{ + rtk_uint32 data; + rtk_api_ret_t retVal; + + RTK_CHK_PORT_IS_UTP(port); + + if (pMode == NULL) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicPHYReg(rtk_switch_port_L2P_get(port), 9, &data)) != RT_ERR_OK) + return retVal; + + *pMode = (data & 0xE000) >> 13; + + return RT_ERR_OK; +} diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_port.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_port.h new file mode 100644 index 00000000..2f8b2741 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_port.h @@ -0,0 +1,976 @@ + /* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8367/RTL8367C switch high-level API + * + * Feature : The file includes port module high-layer API defination + * + */ + +#ifndef __DAL_RTL8367C_PORT_H__ +#define __DAL_RTL8367C_PORT_H__ + +#include + +/* + * Data Type Declaration + */ + +/* Function Name: + * dal_rtl8367c_port_phyAutoNegoAbility_set + * Description: + * Set ethernet PHY auto-negotiation desired ability. + * Input: + * port - port id. + * pAbility - Ability structure + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_PHY_REG_ID - Invalid PHY address + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy + * Note: + * If Full_1000 bit is set to 1, the AutoNegotiation will be automatic set to 1. While both AutoNegotiation and Full_1000 are set to 0, the PHY speed and duplex selection will + * be set as following 100F > 100H > 10F > 10H priority sequence. + */ +extern rtk_api_ret_t dal_rtl8367c_port_phyAutoNegoAbility_set(rtk_port_t port, rtk_port_phy_ability_t *pAbility); + +/* Function Name: + * dal_rtl8367c_port_phyAutoNegoAbility_get + * Description: + * Get PHY ability through PHY registers. + * Input: + * port - Port id. + * Output: + * pAbility - Ability structure + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_PHY_REG_ID - Invalid PHY address + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy + * Note: + * Get the capablity of specified PHY. + */ +extern rtk_api_ret_t dal_rtl8367c_port_phyAutoNegoAbility_get(rtk_port_t port, rtk_port_phy_ability_t *pAbility); + +/* Function Name: + * dal_rtl8367c_port_phyForceModeAbility_set + * Description: + * Set the port speed/duplex mode/pause/asy_pause in the PHY force mode. + * Input: + * port - port id. + * pAbility - Ability structure + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_PHY_REG_ID - Invalid PHY address + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy + * Note: + * While both AutoNegotiation and Full_1000 are set to 0, the PHY speed and duplex selection will + * be set as following 100F > 100H > 10F > 10H priority sequence. + */ +extern rtk_api_ret_t dal_rtl8367c_port_phyForceModeAbility_set(rtk_port_t port, rtk_port_phy_ability_t *pAbility); + +/* Function Name: + * dal_rtl8367c_port_phyForceModeAbility_get + * Description: + * Get PHY ability through PHY registers. + * Input: + * port - Port id. + * Output: + * pAbility - Ability structure + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_PHY_REG_ID - Invalid PHY address + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy + * Note: + * Get the capablity of specified PHY. + */ +extern rtk_api_ret_t dal_rtl8367c_port_phyForceModeAbility_get(rtk_port_t port, rtk_port_phy_ability_t *pAbility); + +/* Function Name: + * dal_rtl8367c_port_phyStatus_get + * Description: + * Get ethernet PHY linking status + * Input: + * port - Port id. + * Output: + * linkStatus - PHY link status + * speed - PHY link speed + * duplex - PHY duplex mode + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_PHY_REG_ID - Invalid PHY address + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy + * Note: + * API will return auto negotiation status of phy. + */ +extern rtk_api_ret_t dal_rtl8367c_port_phyStatus_get(rtk_port_t port, rtk_port_linkStatus_t *pLinkStatus, rtk_port_speed_t *pSpeed, rtk_port_duplex_t *pDuplex); + +/* Function Name: + * dal_rtl8367c_port_macForceLink_set + * Description: + * Set port force linking configuration. + * Input: + * port - port id. + * pPortability - port ability configuration + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can set Port/MAC force mode properties. + */ +extern rtk_api_ret_t dal_rtl8367c_port_macForceLink_set(rtk_port_t port, rtk_port_mac_ability_t *pPortability); + +/* Function Name: + * dal_rtl8367c_port_macForceLink_get + * Description: + * Get port force linking configuration. + * Input: + * port - Port id. + * Output: + * pPortability - port ability configuration + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can get Port/MAC force mode properties. + */ +extern rtk_api_ret_t dal_rtl8367c_port_macForceLink_get(rtk_port_t port, rtk_port_mac_ability_t *pPortability); + +/* Function Name: + * dal_rtl8367c_port_macForceLinkExt_set + * Description: + * Set external interface force linking configuration. + * Input: + * port - external port ID + * mode - external interface mode + * pPortability - port ability configuration + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can set external interface force mode properties. + * The external interface can be set to: + * - MODE_EXT_DISABLE, + * - MODE_EXT_RGMII, + * - MODE_EXT_MII_MAC, + * - MODE_EXT_MII_PHY, + * - MODE_EXT_TMII_MAC, + * - MODE_EXT_TMII_PHY, + * - MODE_EXT_GMII, + * - MODE_EXT_RMII_MAC, + * - MODE_EXT_RMII_PHY, + * - MODE_EXT_SGMII, + * - MODE_EXT_HSGMII, + * - MODE_EXT_1000X_100FX, + * - MODE_EXT_1000X, + * - MODE_EXT_100FX, + */ +extern rtk_api_ret_t dal_rtl8367c_port_macForceLinkExt_set(rtk_port_t port, rtk_mode_ext_t mode, rtk_port_mac_ability_t *pPortability); + +/* Function Name: + * dal_rtl8367c_port_macForceLinkExt_get + * Description: + * Set external interface force linking configuration. + * Input: + * port - external port ID + * Output: + * pMode - external interface mode + * pPortability - port ability configuration + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can get external interface force mode properties. + */ +extern rtk_api_ret_t dal_rtl8367c_port_macForceLinkExt_get(rtk_port_t port, rtk_mode_ext_t *pMode, rtk_port_mac_ability_t *pPortability); + +/* Function Name: + * dal_rtl8367c_port_macStatus_get + * Description: + * Get port link status. + * Input: + * port - Port id. + * Output: + * pPortstatus - port ability configuration + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can get Port/PHY properties. + */ +extern rtk_api_ret_t dal_rtl8367c_port_macStatus_get(rtk_port_t port, rtk_port_mac_ability_t *pPortstatus); + +/* Function Name: + * dal_rtl8367c_port_macLocalLoopbackEnable_set + * Description: + * Set Port Local Loopback. (Redirect TX to RX.) + * Input: + * port - Port id. + * enable - Loopback state, 0:disable, 1:enable + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can enable/disable Local loopback in MAC. + * For UTP port, This API will also enable the digital + * loopback bit in PHY register for sync of speed between + * PHY and MAC. For EXT port, users need to force the + * link state by themself. + */ +extern rtk_api_ret_t dal_rtl8367c_port_macLocalLoopbackEnable_set(rtk_port_t port, rtk_enable_t enable); + +/* Function Name: + * dal_rtl8367c_port_macLocalLoopbackEnable_get + * Description: + * Get Port Local Loopback. (Redirect TX to RX.) + * Input: + * port - Port id. + * Output: + * pEnable - Loopback state, 0:disable, 1:enable + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * None. + */ +extern rtk_api_ret_t dal_rtl8367c_port_macLocalLoopbackEnable_get(rtk_port_t port, rtk_enable_t *pEnable); + +/* Function Name: + * dal_rtl8367c_port_phyReg_set + * Description: + * Set PHY register data of the specific port. + * Input: + * port - port id. + * reg - Register id + * regData - Register data + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_PHY_REG_ID - Invalid PHY address + * RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy + * Note: + * This API can set PHY register data of the specific port. + */ +extern rtk_api_ret_t dal_rtl8367c_port_phyReg_set(rtk_port_t port, rtk_port_phy_reg_t reg, rtk_port_phy_data_t value); + +/* Function Name: + * dal_rtl8367c_port_phyReg_get + * Description: + * Get PHY register data of the specific port. + * Input: + * port - Port id. + * reg - Register id + * Output: + * pData - Register data + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_PHY_REG_ID - Invalid PHY address + * RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy + * Note: + * This API can get PHY register data of the specific port. + */ +extern rtk_api_ret_t dal_rtl8367c_port_phyReg_get(rtk_port_t port, rtk_port_phy_reg_t reg, rtk_port_phy_data_t *pData); + +/* Function Name: + * dal_rtl8367c_port_phyOCPReg_set + * Description: + * Set PHY OCP register + * Input: + * port - PHY ID + * ocpAddr - OCP register address + * ocpData - OCP Data. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_BUSYWAIT_TIMEOUT - Timeout + * Note: + * None. + */ +extern rtk_api_ret_t dal_rtl8367c_port_phyOCPReg_set(rtk_port_t port, rtk_uint32 ocpAddr, rtk_uint32 ocpData); + + +/* Function Name: + * dal_rtl8367c_port_phyOCPReg_get + * Description: + * Set PHY OCP register + * Input: + * phyNo - PHY ID + * ocpAddr - OCP register address + * Output: + * pRegData - OCP data. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * None. + */ +extern rtk_api_ret_t dal_rtl8367c_port_phyOCPReg_get(rtk_port_t port, rtk_uint32 ocpAddr, rtk_uint32 *pRegData); + +/* Function Name: + * dal_rtl8367c_port_backpressureEnable_set + * Description: + * Set the half duplex backpressure enable status of the specific port. + * Input: + * port - port id. + * enable - Back pressure status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * This API can set the half duplex backpressure enable status of the specific port. + * The half duplex backpressure enable status of the port is as following: + * - DISABLE + * - ENABLE + */ +extern rtk_api_ret_t dal_rtl8367c_port_backpressureEnable_set(rtk_port_t port, rtk_enable_t enable); + +/* Function Name: + * dal_rtl8367c_port_backpressureEnable_get + * Description: + * Get the half duplex backpressure enable status of the specific port. + * Input: + * port - Port id. + * Output: + * pEnable - Back pressure status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can get the half duplex backpressure enable status of the specific port. + * The half duplex backpressure enable status of the port is as following: + * - DISABLE + * - ENABLE + */ +extern rtk_api_ret_t dal_rtl8367c_port_backpressureEnable_get(rtk_port_t port, rtk_enable_t *pEnable); + +/* Function Name: + * dal_rtl8367c_port_adminEnable_set + * Description: + * Set port admin configuration of the specific port. + * Input: + * port - port id. + * enable - Back pressure status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * This API can set port admin configuration of the specific port. + * The port admin configuration of the port is as following: + * - DISABLE + * - ENABLE + */ +extern rtk_api_ret_t dal_rtl8367c_port_adminEnable_set(rtk_port_t port, rtk_enable_t enable); + +/* Function Name: + * dal_rtl8367c_port_adminEnable_get + * Description: + * Get port admin configurationof the specific port. + * Input: + * port - Port id. + * Output: + * pEnable - Back pressure status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can get port admin configuration of the specific port. + * The port admin configuration of the port is as following: + * - DISABLE + * - ENABLE + */ +extern rtk_api_ret_t dal_rtl8367c_port_adminEnable_get(rtk_port_t port, rtk_enable_t *pEnable); + +/* Function Name: + * dal_rtl8367c_port_isolation_set + * Description: + * Set permitted port isolation portmask + * Input: + * port - port id. + * pPortmask - Permit port mask + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_PORT_MASK - Invalid portmask. + * Note: + * This API set the port mask that a port can trasmit packet to of each port + * A port can only transmit packet to ports included in permitted portmask + */ +extern rtk_api_ret_t dal_rtl8367c_port_isolation_set(rtk_port_t port, rtk_portmask_t *pPortmask); + +/* Function Name: + * dal_rtl8367c_port_isolation_get + * Description: + * Get permitted port isolation portmask + * Input: + * port - Port id. + * Output: + * pPortmask - Permit port mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API get the port mask that a port can trasmit packet to of each port + * A port can only transmit packet to ports included in permitted portmask + */ +extern rtk_api_ret_t dal_rtl8367c_port_isolation_get(rtk_port_t port, rtk_portmask_t *pPortmask); + +/* Function Name: + * dal_rtl8367c_port_rgmiiDelayExt_set + * Description: + * Set RGMII interface delay value for TX and RX. + * Input: + * txDelay - TX delay value, 1 for delay 2ns and 0 for no-delay + * rxDelay - RX delay value, 0~7 for delay setup. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can set external interface 2 RGMII delay. + * In TX delay, there are 2 selection: no-delay and 2ns delay. + * In RX dekay, there are 8 steps for delay tunning. 0 for no-delay, and 7 for maximum delay. + * Note. This API should be called before rtk_port_macForceLinkExt_set(). + */ +extern rtk_api_ret_t dal_rtl8367c_port_rgmiiDelayExt_set(rtk_port_t port, rtk_data_t txDelay, rtk_data_t rxDelay); + +/* Function Name: + * dal_rtl8367c_port_rgmiiDelayExt_get + * Description: + * Get RGMII interface delay value for TX and RX. + * Input: + * None + * Output: + * pTxDelay - TX delay value + * pRxDelay - RX delay value + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can set external interface 2 RGMII delay. + * In TX delay, there are 2 selection: no-delay and 2ns delay. + * In RX dekay, there are 8 steps for delay tunning. 0 for n0-delay, and 7 for maximum delay. + */ +extern rtk_api_ret_t dal_rtl8367c_port_rgmiiDelayExt_get(rtk_port_t port, rtk_data_t *pTxDelay, rtk_data_t *pRxDelay); + +/* Function Name: + * dal_rtl8367c_port_phyEnableAll_set + * Description: + * Set all PHY enable status. + * Input: + * enable - PHY Enable State. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * This API can set all PHY status. + * The configuration of all PHY is as following: + * - DISABLE + * - ENABLE + */ +extern rtk_api_ret_t dal_rtl8367c_port_phyEnableAll_set(rtk_enable_t enable); + +/* Function Name: + * dal_rtl8367c_port_phyEnableAll_get + * Description: + * Get all PHY enable status. + * Input: + * None + * Output: + * pEnable - PHY Enable State. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API can set all PHY status. + * The configuration of all PHY is as following: + * - DISABLE + * - ENABLE + */ +extern rtk_api_ret_t dal_rtl8367c_port_phyEnableAll_get(rtk_enable_t *pEnable); + +/* Function Name: + * dal_rtl8367c_port_efid_set + * Description: + * Set port-based enhanced filtering database + * Input: + * port - Port id. + * efid - Specified enhanced filtering database. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_FID - Invalid fid. + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API can set port-based enhanced filtering database. + */ +extern rtk_api_ret_t dal_rtl8367c_port_efid_set(rtk_port_t port, rtk_data_t efid); + +/* Function Name: + * dal_rtl8367c_port_efid_get + * Description: + * Get port-based enhanced filtering database + * Input: + * port - Port id. + * Output: + * pEfid - Specified enhanced filtering database. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API can get port-based enhanced filtering database status. + */ +extern rtk_api_ret_t dal_rtl8367c_port_efid_get(rtk_port_t port, rtk_data_t *pEfid); + +/* Function Name: + * dal_rtl8367c_port_phyComboPortMedia_set + * Description: + * Set Combo port media type + * Input: + * port - Port id. (Should be Port 4) + * media - Media (COPPER or FIBER or AUTO) + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API can Set Combo port media type. + */ +extern rtk_api_ret_t dal_rtl8367c_port_phyComboPortMedia_set(rtk_port_t port, rtk_port_media_t media); + +/* Function Name: + * dal_rtl8367c_port_phyComboPortMedia_get + * Description: + * Get Combo port media type + * Input: + * port - Port id. (Should be Port 4) + * Output: + * pMedia - Media (COPPER or FIBER or AUTO) + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API can Set Combo port media type. + */ +extern rtk_api_ret_t dal_rtl8367c_port_phyComboPortMedia_get(rtk_port_t port, rtk_port_media_t *pMedia); + +/* Function Name: + * dal_rtl8367c_port_rtctEnable_set + * Description: + * Enable RTCT test + * Input: + * pPortmask - Port mask of RTCT enabled port + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Invalid port mask. + * Note: + * The API can enable RTCT Test + */ +extern rtk_api_ret_t dal_rtl8367c_port_rtctEnable_set(rtk_portmask_t *pPortmask); + +/* Function Name: + * dal_rtl8367c_port_rtctDisable_set + * Description: + * Disable RTCT test + * Input: + * pPortmask - Port mask of RTCT disabled port + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Invalid port mask. + * Note: + * The API can disable RTCT Test + */ +extern rtk_api_ret_t dal_rtl8367c_port_rtctDisable_set(rtk_portmask_t *pPortmask); + + +/* Function Name: + * dal_rtl8367c_port_rtctResult_get + * Description: + * Get the result of RTCT test + * Input: + * port - Port ID + * Output: + * pRtctResult - The result of RTCT result + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port ID. + * RT_ERR_PHY_RTCT_NOT_FINISH - Testing does not finish. + * Note: + * The API can get RTCT test result. + * RTCT test may takes 4.8 seconds to finish its test at most. + * Thus, if this API return RT_ERR_PHY_RTCT_NOT_FINISH or + * other error code, the result can not be referenced and + * user should call this API again until this API returns + * a RT_ERR_OK. + * The result is stored at pRtctResult->ge_result + * pRtctResult->linkType is unused. + * The unit of channel length is 2.5cm. Ex. 300 means 300 * 2.5 = 750cm = 7.5M + */ +extern rtk_api_ret_t dal_rtl8367c_port_rtctResult_get(rtk_port_t port, rtk_rtctResult_t *pRtctResult); + +/* Function Name: + * dal_rtl8367c_port_sds_reset + * Description: + * Reset Serdes + * Input: + * port - Port ID + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API can reset Serdes + */ +extern rtk_api_ret_t dal_rtl8367c_port_sds_reset(rtk_port_t port); + +/* Function Name: + * dal_rtl8367c_port_sgmiiLinkStatus_get + * Description: + * Get SGMII status + * Input: + * port - Port ID + * Output: + * pSignalDetect - Signal detect + * pSync - Sync + * pLink - Link + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API can reset Serdes + */ +extern rtk_api_ret_t dal_rtl8367c_port_sgmiiLinkStatus_get(rtk_port_t port, rtk_data_t *pSignalDetect, rtk_data_t *pSync, rtk_port_linkStatus_t *pLink); + +/* Function Name: + * dal_rtl8367c_port_sgmiiNway_set + * Description: + * Configure SGMII/HSGMII port Nway state + * Input: + * port - Port ID + * state - Nway state + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API configure SGMII/HSGMII port Nway state + */ +extern rtk_api_ret_t dal_rtl8367c_port_sgmiiNway_set(rtk_port_t port, rtk_enable_t state); + +/* Function Name: + * dal_rtl8367c_port_sgmiiNway_get + * Description: + * Get SGMII/HSGMII port Nway state + * Input: + * port - Port ID + * Output: + * pState - Nway state + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API can get SGMII/HSGMII port Nway state + */ +extern rtk_api_ret_t dal_rtl8367c_port_sgmiiNway_get(rtk_port_t port, rtk_enable_t *pState); + +/* Function Name: + * dal_rtl8367c_port_fiberAbilityExt_set + * Description: + * Get SGMII/HSGMII port Nway state + * Input: + * port - Port ID + * pause -pause state + * asypause -asypause state + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API can get SGMII/HSGMII port Nway state + */ +extern rtk_api_ret_t dal_rtl8367c_port_fiberAbilityExt_set(rtk_port_t port, rtk_uint32 pause, rtk_uint32 asypause); + + + +/* Function Name: + * dal_rtl8367c_port_fiberAbilityExt_get + * Description: + * Get SGMII/HSGMII port Nway state + * Input: + * port - Port ID + * Output: + * pPause -pause state + * pAsypause -asypause state + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API can get SGMII/HSGMII port Nway state + */ +extern rtk_api_ret_t dal_rtl8367c_port_fiberAbilityExt_get(rtk_port_t port, rtk_uint32* pPause, rtk_uint32* pAsypause); + + +/* Function Name: + * dal_rtl8367c_port_autoDos_set + * Description: + * Set Auto Dos state + * Input: + * type - Auto DoS type + * state - 1: Eanble(Drop), 0: Disable(Forward) + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set Auto Dos state + */ +extern rtk_api_ret_t dal_rtl8367c_port_autoDos_set(rtk_port_autoDosType_t type, rtk_enable_t state); + +/* Function Name: + * dal_rtl8367c_port_autoDos_get + * Description: + * Get Auto Dos state + * Input: + * type - Auto DoS type + * Output: + * pState - 1: Eanble(Drop), 0: Disable(Forward) + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Null Pointer + * Note: + * The API can get Auto Dos state + */ +extern rtk_api_ret_t dal_rtl8367c_port_autoDos_get(rtk_port_autoDosType_t type, rtk_enable_t *pState); + +/* Function Name: + * dal_rtl8367c_port_phyMdx_set + * Description: + * Set PHY MDI/MDIX state + * Input: + * port - port ID + * mode - PHY MDI/MDIX mode + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set PHY MDI/MDIX state + */ +extern rtk_api_ret_t dal_rtl8367c_port_phyMdx_set(rtk_port_t port, rtk_port_phy_mdix_mode_t mode); + +/* Function Name: + * dal_rtl8367c_port_phyMdx_get + * Description: + * Get PHY MDI/MDIX state + * Input: + * port - port ID + * Output: + * pMode - PHY MDI/MDIX mode + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can get PHY MDI/MDIX state + */ +extern rtk_api_ret_t dal_rtl8367c_port_phyMdx_get(rtk_port_t port, rtk_port_phy_mdix_mode_t *pMode); + +/* Function Name: + * dal_rtl8367c_port_phyMdxStatus_get + * Description: + * Get PHY MDI/MDIX status + * Input: + * port - port ID + * Output: + * pStatus - PHY MDI/MDIX status + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can get PHY MDI/MDIX status + */ +extern rtk_api_ret_t dal_rtl8367c_port_phyMdxStatus_get(rtk_port_t port, rtk_port_phy_mdix_status_t *pStatus); + +/* Function Name: + * dal_rtl8367c_port_phyTestMode_set + * Description: + * Set PHY in test mode. + * Input: + * port - port id. + * mode - PHY test mode 0:normal 1:test mode 1 2:test mode 2 3: test mode 3 4:test mode 4 5~7:reserved + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy + * RT_ERR_NOT_ALLOWED - The Setting is not allowed, caused by set more than 1 port in Test mode. + * Note: + * Set PHY in test mode and only one PHY can be in test mode at the same time. + * It means API will return FAILED if other PHY is in test mode. + * This API only provide test mode 1 & 4 setup. + */ +extern rtk_api_ret_t dal_rtl8367c_port_phyTestMode_set(rtk_port_t port, rtk_port_phy_test_mode_t mode); + +/* Function Name: + * dal_rtl8367c_port_phyTestMode_get + * Description: + * Get PHY in which test mode. + * Input: + * port - Port id. + * Output: + * mode - PHY test mode 0:normal 1:test mode 1 2:test mode 2 3: test mode 3 4:test mode 4 5~7:reserved + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy + * Note: + * Get test mode of PHY from register setting 9.15 to 9.13. + */ +extern rtk_api_ret_t dal_rtl8367c_port_phyTestMode_get(rtk_port_t port, rtk_port_phy_test_mode_t *pMode); + +#endif /* __DAL_RTL8367C_PORT_H__ */ + + + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_ptp.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_ptp.c new file mode 100644 index 00000000..0f37a02d --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_ptp.c @@ -0,0 +1,755 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision: 39583 $ + * $Date: 2013-05-20 16:59:23 +0800 (星期一, 20 五月 2013) $ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8367C + * Feature : Here is a list of all functions and variables in time module. + * + */ + +#include +#include +#include +#include + +#include +#include + +/* Function Name: + * dal_rtl8367c_ptp_init + * Description: + * PTP function initialization. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API is used to initialize PTP status. + */ +rtk_api_ret_t dal_rtl8367c_ptp_init(void) +{ + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_ptp_mac_set + * Description: + * Configure PTP mac address. + * Input: + * mac - mac address to parser PTP packets. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * Note: + * None + */ +rtk_api_ret_t dal_rtl8367c_ptp_mac_set(rtk_mac_t mac) +{ + rtk_api_ret_t retVal; + ether_addr_t sw_mac; + + memcpy(sw_mac.octet, mac.octet, ETHER_ADDR_LEN); + + if((retVal=rtl8367c_setAsicEavMacAddress(sw_mac))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_ptp_mac_get + * Description: + * Get PTP mac address. + * Input: + * None + * Output: + * pMac - mac address to parser PTP packets. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * Note: + * None + */ + rtk_api_ret_t dal_rtl8367c_ptp_mac_get(rtk_mac_t *pMac) +{ + rtk_api_ret_t retVal; + ether_addr_t sw_mac; + + if((retVal=rtl8367c_getAsicEavMacAddress(&sw_mac))!=RT_ERR_OK) + return retVal; + + memcpy(pMac->octet, sw_mac.octet, ETHER_ADDR_LEN); + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_ptp_tpid_set + * Description: + * Configure PTP accepted outer & inner tag TPID. + * Input: + * outerId - Ether type of S-tag frame parsing in PTP ports. + * innerId - Ether type of C-tag frame parsing in PTP ports. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * Note: + * None + */ +rtk_api_ret_t dal_rtl8367c_ptp_tpid_set(rtk_ptp_tpid_t outerId, rtk_ptp_tpid_t innerId) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if ((outerId>DAL_RTL8367C_MAX_NUM_OF_TPID) ||(innerId>DAL_RTL8367C_MAX_NUM_OF_TPID)) + return RT_ERR_INPUT; + + if ((retVal = rtl8367c_setAsicEavTpid(outerId, innerId)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_ptp_tpid_get + * Description: + * Get PTP accepted outer & inner tag TPID. + * Input: + * None + * Output: + * pOuterId - Ether type of S-tag frame parsing in PTP ports. + * pInnerId - Ether type of C-tag frame parsing in PTP ports. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +rtk_api_ret_t dal_rtl8367c_ptp_tpid_get(rtk_ptp_tpid_t *pOuterId, rtk_ptp_tpid_t *pInnerId) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if ((retVal = rtl8367c_getAsicEavTpid(pOuterId, pInnerId)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_ptp_refTime_set + * Description: + * Set the reference time of the specified device. + * Input: + * timeStamp - reference timestamp value + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT - invalid input parameter + * Applicable: + * 8390, 8380 + * Note: + * None + */ +rtk_api_ret_t dal_rtl8367c_ptp_refTime_set(rtk_ptp_timeStamp_t timeStamp) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (timeStamp.nsec > RTK_MAX_NUM_OF_NANO_SECOND) + return RT_ERR_INPUT; + + if ((retVal = rtl8367c_setAsicEavSysTime(timeStamp.sec, timeStamp.nsec))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_ptp_refTime_get + * Description: + * Get the reference time of the specified device. + * Input: + * Output: + * pTimeStamp - pointer buffer of the reference time + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Applicable: + * 8390, 8380 + * Note: + * None + */ +rtk_api_ret_t dal_rtl8367c_ptp_refTime_get(rtk_ptp_timeStamp_t *pTimeStamp) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if ((retVal = rtl8367c_getAsicEavSysTime(&pTimeStamp->sec, &pTimeStamp->nsec))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_ptp_refTimeAdjust_set + * Description: + * Adjust the reference time. + * Input: + * unit - unit id + * sign - significant + * timeStamp - reference timestamp value + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Note: + * sign=0 for positive adjustment, sign=1 for negative adjustment. + */ + rtk_api_ret_t dal_rtl8367c_ptp_refTimeAdjust_set(rtk_ptp_sys_adjust_t sign, rtk_ptp_timeStamp_t timeStamp) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (timeStamp.nsec > DAL_RTL8367C_MAX_NUM_OF_NANO_SECOND) + return RT_ERR_INPUT; + + if ((retVal = rtl8367c_setAsicEavSysTimeAdjust(sign, timeStamp.sec, timeStamp.nsec))!=RT_ERR_OK) + return retVal; + + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_ptp_refTimeEnable_set + * Description: + * Set the enable state of reference time of the specified device. + * Input: + * enable - status + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT - invalid input parameter + * Note: + * None + */ + rtk_api_ret_t dal_rtl8367c_ptp_refTimeEnable_set(rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (enable >= RTK_ENABLE_END) + return RT_ERR_ENABLE; + + if ((retVal = rtl8367c_setAsicEavSysTimeCtrl(enable))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_ptp_refTimeEnable_get + * Description: + * Get the enable state of reference time of the specified device. + * Input: + * Output: + * pEnable - status + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Applicable: + * 8390, 8380 + * Note: + * None + */ + rtk_api_ret_t dal_rtl8367c_ptp_refTimeEnable_get(rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if ((retVal = rtl8367c_getAsicEavSysTimeCtrl(pEnable))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_ptp_portEnable_set + * Description: + * Set PTP status of the specified port. + * Input: + * port - port id + * enable - status + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT - invalid port id + * RT_ERR_INPUT - invalid input parameter + * Note: + * None + */ +rtk_api_ret_t dal_rtl8367c_ptp_portEnable_set(rtk_port_t port, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check port is PTP port */ + RTK_CHK_PORT_IS_PTP(port); + + if (enable>=RTK_ENABLE_END) + return RT_ERR_INPUT; + + if ((retVal = rtl8367c_setAsicEavPortEnable(rtk_switch_port_L2P_get(port), enable)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_ptp_portEnable_get + * Description: + * Get PTP status of the specified port. + * Input: + * port - port id + * Output: + * pEnable - status + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT - invalid port id + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None + */ +rtk_api_ret_t dal_rtl8367c_ptp_portEnable_get(rtk_port_t port, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check port is PTP port */ + RTK_CHK_PORT_IS_PTP(port); + + if ((retVal = rtl8367c_getAsicEavPortEnable(rtk_switch_port_L2P_get(port), pEnable)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_ptp_portTimestamp_get + * Description: + * Get PTP timstamp according to the PTP identifier on the dedicated port from the specified device. + * Input: + * unit - unit id + * port - port id + * type - PTP message type + * Output: + * pInfo - pointer buffer of sequence ID and timestamp + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Applicable: + * 8390, 8380 + * Note: + * None + */ +rtk_api_ret_t dal_rtl8367c_ptp_portTimestamp_get( rtk_port_t port, rtk_ptp_msgType_t type, rtk_ptp_info_t *pInfo) +{ + rtk_api_ret_t retVal; + rtl8367c_ptp_time_stamp_t time; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check port is PTP port */ + RTK_CHK_PORT_IS_PTP(port); + + if ((retVal = rtl8367c_getAsicEavPortTimeStamp(rtk_switch_port_L2P_get(port), type, &time)) != RT_ERR_OK) + return retVal; + + pInfo->sequenceId = time.sequence_id; + pInfo->timeStamp.sec = time.second; + pInfo->timeStamp.nsec = time.nano_second; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_ptp_intControl_set + * Description: + * Set PTP interrupt trigger status configuration. + * Input: + * type - Interrupt type. + * enable - Interrupt status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * The API can set PTP interrupt status configuration. + * The interrupt trigger status is shown in the following: + * PTP_INT_TYPE_TX_SYNC = 0, + * PTP_INT_TYPE_TX_DELAY_REQ, + * PTP_INT_TYPE_TX_PDELAY_REQ, + * PTP_INT_TYPE_TX_PDELAY_RESP, + * PTP_INT_TYPE_RX_SYNC, + * PTP_INT_TYPE_RX_DELAY_REQ, + * PTP_INT_TYPE_RX_PDELAY_REQ, + * PTP_INT_TYPE_RX_PDELAY_RESP, + * PTP_INT_TYPE_ALL, + */ +rtk_api_ret_t dal_rtl8367c_ptp_intControl_set(rtk_ptp_intType_t type, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + rtk_uint32 mask; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (type>=PTP_INT_TYPE_END) + return RT_ERR_INPUT; + + if (PTP_INT_TYPE_ALL!=type) + { + if ((retVal = rtl8367c_getAsicEavInterruptMask(&mask)) != RT_ERR_OK) + return retVal; + + if (ENABLED == enable) + mask = mask | (1<=PTP_INT_TYPE_ALL) + return RT_ERR_INPUT; + + if ((retVal = rtl8367c_getAsicEavInterruptMask(&mask)) != RT_ERR_OK) + return retVal; + + if (0 == (mask&(1<=RTK_ENABLE_END) + return RT_ERR_INPUT; + + if ((retVal = rtl8367c_setAsicEavTrap(rtk_switch_port_L2P_get(port), enable)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_ptp_portTrap_get + * Description: + * Get PTP packet trap of the specified port. + * Input: + * port - port id + * Output: + * pEnable - status + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT - invalid port id + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None + */ + rtk_api_ret_t dal_rtl8367c_ptp_portTrap_get(rtk_port_t port, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if ((retVal = rtl8367c_getAsicEavTrap(rtk_switch_port_L2P_get(port), pEnable)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_ptp.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_ptp.h new file mode 100644 index 00000000..f247be03 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_ptp.h @@ -0,0 +1,462 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8367/RTL8367C switch high-level API + * + * Feature : The file includes time module high-layer API defination + * + */ + +#ifndef __DAL_RTL8367C_PTP_H__ +#define __DAL_RTL8367C_PTP_H__ + +#include "ptp.h" + +/* + * Symbol Definition + */ +#define DAL_RTL8367C_MAX_NUM_OF_NANO_SECOND 0x3B9AC9FF +#define DAL_RTL8367C_PTP_INTR_MASK 0xFF +#define DAL_RTL8367C_MAX_NUM_OF_TPID 0xFFFF + +/* + * Data Declaration + */ + +/* + * Function Declaration + */ +/* Function Name: + * dal_rtl8367c_ptp_init + * Description: + * PTP function initialization. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API is used to initialize EEE status. + */ +extern rtk_api_ret_t dal_rtl8367c_ptp_init(void); + +/* Function Name: + * dal_rtl8367c_ptp_mac_set + * Description: + * Configure PTP mac address. + * Input: + * mac - mac address to parser PTP packets. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * Note: + * None + */ +extern rtk_api_ret_t dal_rtl8367c_ptp_mac_set(rtk_mac_t mac); + +/* Function Name: + * dal_rtl8367c_ptp_mac_get + * Description: + * Get PTP mac address. + * Input: + * None + * Output: + * pMac - mac address to parser PTP packets. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * Note: + * None + */ +extern rtk_api_ret_t dal_rtl8367c_ptp_mac_get(rtk_mac_t *pMac); + +/* Function Name: + * dal_rtl8367c_ptp_tpid_set + * Description: + * Configure PTP accepted outer & inner tag TPID. + * Input: + * outerId - Ether type of S-tag frame parsing in PTP ports. + * innerId - Ether type of C-tag frame parsing in PTP ports. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * Note: + * None + */ +extern rtk_api_ret_t dal_rtl8367c_ptp_tpid_set(rtk_ptp_tpid_t outerId, rtk_ptp_tpid_t innerId); + +/* Function Name: + * dal_rtl8367c_ptp_tpid_get + * Description: + * Get PTP accepted outer & inner tag TPID. + * Input: + * None + * Output: + * pOuterId - Ether type of S-tag frame parsing in PTP ports. + * pInnerId - Ether type of C-tag frame parsing in PTP ports. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +extern rtk_api_ret_t dal_rtl8367c_ptp_tpid_get(rtk_ptp_tpid_t *pOuterId, rtk_ptp_tpid_t *pInnerId); + +/* Function Name: + * dal_rtl8367c_ptp_refTime_set + * Description: + * Set the reference time of the specified device. + * Input: + * timeStamp - reference timestamp value + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT - invalid input parameter + * Applicable: + * 8390, 8380 + * Note: + * None + */ +extern rtk_api_ret_t dal_rtl8367c_ptp_refTime_set(rtk_ptp_timeStamp_t timeStamp); + +/* Function Name: + * dal_rtl8367c_ptp_refTime_get + * Description: + * Get the reference time of the specified device. + * Input: + * Output: + * pTimeStamp - pointer buffer of the reference time + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Applicable: + * 8390, 8380 + * Note: + * None + */ +extern rtk_api_ret_t dal_rtl8367c_ptp_refTime_get(rtk_ptp_timeStamp_t *pTimeStamp); + +/* Function Name: + * dal_rtl8367c_ptp_refTimeAdjust_set + * Description: + * Adjust the reference time. + * Input: + * unit - unit id + * sign - significant + * timeStamp - reference timestamp value + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Note: + * sign=0 for positive adjustment, sign=1 for negative adjustment. + */ +extern rtk_api_ret_t dal_rtl8367c_ptp_refTimeAdjust_set(rtk_ptp_sys_adjust_t sign, rtk_ptp_timeStamp_t timeStamp); + +/* Function Name: + * dal_rtl8367c_ptp_refTimeEnable_set + * Description: + * Set the enable state of reference time of the specified device. + * Input: + * enable - status + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT - invalid input parameter + * Note: + * None + */ +extern rtk_api_ret_t dal_rtl8367c_ptp_refTimeEnable_set(rtk_enable_t enable); + +/* Function Name: + * dal_rtl8367c_ptp_refTimeEnable_get + * Description: + * Get the enable state of reference time of the specified device. + * Input: + * Output: + * pEnable - status + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Applicable: + * 8390, 8380 + * Note: + * None + */ +extern rtk_api_ret_t dal_rtl8367c_ptp_refTimeEnable_get(rtk_enable_t *pEnable); + +/* Function Name: + * dal_rtl8367c_ptp_portEnable_set + * Description: + * Set PTP status of the specified port. + * Input: + * port - port id + * enable - status + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT - invalid port id + * RT_ERR_INPUT - invalid input parameter + * Note: + * None + */ +extern rtk_api_ret_t dal_rtl8367c_ptp_portEnable_set(rtk_port_t port, rtk_enable_t enable); + +/* Function Name: + * dal_rtl8367c_ptp_portEnable_get + * Description: + * Get PTP status of the specified port. + * Input: + * port - port id + * Output: + * pEnable - status + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT - invalid port id + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None + */ +extern rtk_api_ret_t dal_rtl8367c_ptp_portEnable_get(rtk_port_t port, rtk_enable_t *pEnable); + +/* Function Name: + * dal_rtl8367c_ptp_portTimestamp_get + * Description: + * Get PTP timstamp according to the PTP identifier on the dedicated port from the specified device. + * Input: + * unit - unit id + * port - port id + * type - PTP message type + * Output: + * pInfo - pointer buffer of sequence ID and timestamp + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Applicable: + * 8390, 8380 + * Note: + * None + */ +extern rtk_api_ret_t dal_rtl8367c_ptp_portTimestamp_get( rtk_port_t port, rtk_ptp_msgType_t type, rtk_ptp_info_t *pInfo); + +/* Function Name: + * dal_rtl8367c_ptp_intControl_set + * Description: + * Set PTP interrupt trigger status configuration. + * Input: + * type - Interrupt type. + * enable - Interrupt status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * The API can set PTP interrupt status configuration. + * The interrupt trigger status is shown in the following: + * PTP_INT_TYPE_TX_SYNC = 0, + * PTP_INT_TYPE_TX_DELAY_REQ, + * PTP_INT_TYPE_TX_PDELAY_REQ, + * PTP_INT_TYPE_TX_PDELAY_RESP, + * PTP_INT_TYPE_RX_SYNC, + * PTP_INT_TYPE_RX_DELAY_REQ, + * PTP_INT_TYPE_RX_PDELAY_REQ, + * PTP_INT_TYPE_RX_PDELAY_RESP, + * PTP_INT_TYPE_ALL, + */ +extern rtk_api_ret_t dal_rtl8367c_ptp_intControl_set(rtk_ptp_intType_t type, rtk_enable_t enable); + +/* Function Name: + * dal_rtl8367c_ptp_intControl_get + * Description: + * Get PTP interrupt trigger status configuration. + * Input: + * type - Interrupt type. + * Output: + * pEnable - Interrupt status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get interrupt status configuration. + * The interrupt trigger status is shown in the following: + * PTP_INT_TYPE_TX_SYNC = 0, + * PTP_INT_TYPE_TX_DELAY_REQ, + * PTP_INT_TYPE_TX_PDELAY_REQ, + * PTP_INT_TYPE_TX_PDELAY_RESP, + * PTP_INT_TYPE_RX_SYNC, + * PTP_INT_TYPE_RX_DELAY_REQ, + * PTP_INT_TYPE_RX_PDELAY_REQ, + * PTP_INT_TYPE_RX_PDELAY_RESP, + */ +extern rtk_api_ret_t dal_rtl8367c_ptp_intControl_get(rtk_ptp_intType_t type, rtk_enable_t *pEnable); + + +/* Function Name: + * dal_rtl8367c_ptp_intStatus_get + * Description: + * Get PTP port interrupt trigger status. + * Input: + * port - physical port + * Output: + * pStatusMask - Interrupt status bit mask. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get interrupt trigger status when interrupt happened. + * The interrupt trigger status is shown in the following: + * - PORT 0 INT (value[0] (Bit0)) + * - PORT 1 INT (value[0] (Bit1)) + * - PORT 2 INT (value[0] (Bit2)) + * - PORT 3 INT (value[0] (Bit3)) + * - PORT 4 INT (value[0] (Bit4)) + + * + */ +extern rtk_api_ret_t dal_rtl8367c_ptp_intStatus_get(rtk_ptp_intStatus_t *pStatusMask); + +/* Function Name: + * rtk_ptp_portIntStatus_set + * Description: + * Set PTP port interrupt trigger status to clean. + * Input: + * port - physical port + * statusMask - Interrupt status bit mask. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can clean interrupt trigger status when interrupt happened. + * The interrupt trigger status is shown in the following: + * - PTP_INT_TYPE_TX_SYNC (value[0] (Bit0)) + * - PTP_INT_TYPE_TX_DELAY_REQ (value[0] (Bit1)) + * - PTP_INT_TYPE_TX_PDELAY_REQ (value[0] (Bit2)) + * - PTP_INT_TYPE_TX_PDELAY_RESP (value[0] (Bit3)) + * - PTP_INT_TYPE_RX_SYNC (value[0] (Bit4)) + * - PTP_INT_TYPE_RX_DELAY_REQ (value[0] (Bit5)) + * - PTP_INT_TYPE_RX_PDELAY_REQ (value[0] (Bit6)) + * - PTP_INT_TYPE_RX_PDELAY_RESP (value[0] (Bit7)) + * The status will be cleared after execute this API. + */ +extern rtk_api_ret_t dal_rtl8367c_ptp_portIntStatus_set(rtk_port_t port, rtk_ptp_intStatus_t statusMask); + +/* Function Name: + * dal_rtl8367c_ptp_portIntStatus_get + * Description: + * Get PTP port interrupt trigger status. + * Input: + * port - physical port + * Output: + * pStatusMask - Interrupt status bit mask. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get interrupt trigger status when interrupt happened. + * The interrupt trigger status is shown in the following: + * - PTP_INT_TYPE_TX_SYNC (value[0] (Bit0)) + * - PTP_INT_TYPE_TX_DELAY_REQ (value[0] (Bit1)) + * - PTP_INT_TYPE_TX_PDELAY_REQ (value[0] (Bit2)) + * - PTP_INT_TYPE_TX_PDELAY_RESP (value[0] (Bit3)) + * - PTP_INT_TYPE_RX_SYNC (value[0] (Bit4)) + * - PTP_INT_TYPE_RX_DELAY_REQ (value[0] (Bit5)) + * - PTP_INT_TYPE_RX_PDELAY_REQ (value[0] (Bit6)) + * - PTP_INT_TYPE_RX_PDELAY_RESP (value[0] (Bit7)) + * + */ +extern rtk_api_ret_t dal_rtl8367c_ptp_portIntStatus_get(rtk_port_t port, rtk_ptp_intStatus_t *pStatusMask); + +/* Function Name: + * dal_rtl8367c_ptp_portTrap_set + * Description: + * Set PTP packet trap of the specified port. + * Input: + * port - port id + * enable - status + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT - invalid port id + * RT_ERR_INPUT - invalid input parameter + * Note: + * None + */ +extern rtk_api_ret_t dal_rtl8367c_ptp_portTrap_set(rtk_port_t port, rtk_enable_t enable); + +/* Function Name: + * dal_rtl8367c_ptp_portTrap_get + * Description: + * Get PTP packet trap of the specified port. + * Input: + * port - port id + * Output: + * pEnable - status + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT - invalid port id + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None + */ +extern rtk_api_ret_t dal_rtl8367c_ptp_portTrap_get(rtk_port_t port, rtk_enable_t *pEnable); + +#endif /* __DAL_RTL8367C_PTP_H__ */ diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_qos.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_qos.c new file mode 100644 index 00000000..2c9ef25b --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_qos.c @@ -0,0 +1,1448 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8367C + * Feature : Here is a list of all functions and variables in QoS module. + * + */ + +#include +#include +#include +#include + +#include +#include +#include +#include + +/* Function Name: + * dal_rtl8367c_qos_init + * Description: + * Configure Qos default settings with queue number assigment to each port. + * Input: + * queueNum - Queue number of each port. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will initialize related Qos setting with queue number assigment. + * The queue number is from 1 to 8. + */ +rtk_api_ret_t dal_rtl8367c_qos_init(rtk_queue_num_t queueNum) +{ + CONST_T rtk_uint16 g_prioritytToQid[8][8]= { + {0, 0,0,0,0,0,0,0}, + {0, 0,0,0,7,7,7,7}, + {0, 0,0,0,1,1,7,7}, + {0, 0,1,1,2,2,7,7}, + {0, 0,1,1,2,3,7,7}, + {0, 0,1,2,3,4,7,7}, + {0, 0,1,2,3,4,5,7}, + {0,1,2,3,4,5,6,7} + }; + + CONST_T rtk_uint32 g_priorityDecision[8] = {0x01, 0x80,0x04,0x02,0x20,0x40,0x10,0x08}; + CONST_T rtk_uint32 g_prioritytRemap[8] = {0,1,2,3,4,5,6,7}; + + rtk_api_ret_t retVal; + rtk_uint32 qmapidx; + rtk_uint32 priority; + rtk_uint32 priDec; + rtk_uint32 port; + rtk_uint32 dscp; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (queueNum <= 0 || queueNum > RTK_MAX_NUM_OF_QUEUE) + return RT_ERR_QUEUE_NUM; + + /*Set Output Queue Number*/ + if (RTK_MAX_NUM_OF_QUEUE == queueNum) + qmapidx = 0; + else + qmapidx = queueNum; + + RTK_SCAN_ALL_PHY_PORTMASK(port) + { + if ((retVal = rtl8367c_setAsicOutputQueueMappingIndex(port, qmapidx)) != RT_ERR_OK) + return retVal; + } + + /*Set Priority to Qid*/ + for (priority = 0; priority <= RTK_PRIMAX; priority++) + { + if ((retVal = rtl8367c_setAsicPriorityToQIDMappingTable(queueNum - 1, priority, g_prioritytToQid[queueNum - 1][priority])) != RT_ERR_OK) + return retVal; + } + + /*Set Flow Control Type to Ingress Flow Control*/ + if ((retVal = rtl8367c_setAsicFlowControlSelect(FC_INGRESS)) != RT_ERR_OK) + return retVal; + + + /*Priority Decision Order*/ + for (priDec = 0;priDec < PRIDEC_END;priDec++) + { + if ((retVal = rtl8367c_setAsicPriorityDecision(PRIDECTBL_IDX0, priDec, g_priorityDecision[priDec])) != RT_ERR_OK) + return retVal; + if ((retVal = rtl8367c_setAsicPriorityDecision(PRIDECTBL_IDX1, priDec, g_priorityDecision[priDec])) != RT_ERR_OK) + return retVal; + } + + /*Set Port-based Priority to 0*/ + RTK_SCAN_ALL_PHY_PORTMASK(port) + { + if ((retVal = rtl8367c_setAsicPriorityPortBased(port, 0)) != RT_ERR_OK) + return retVal; + } + + /*Disable 1p Remarking*/ + RTK_SCAN_ALL_PHY_PORTMASK(port) + { + if ((retVal = rtl8367c_setAsicRemarkingDot1pAbility(port, DISABLED)) != RT_ERR_OK) + return retVal; + } + + /*Disable DSCP Remarking*/ + if ((retVal = rtl8367c_setAsicRemarkingDscpAbility(DISABLED)) != RT_ERR_OK) + return retVal; + + /*Set 1p & DSCP Priority Remapping & Remarking*/ + for (priority = 0; priority <= RTL8367C_PRIMAX; priority++) + { + if ((retVal = rtl8367c_setAsicPriorityDot1qRemapping(priority, g_prioritytRemap[priority])) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicRemarkingDot1pParameter(priority, 0)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicRemarkingDscpParameter(priority, 0)) != RT_ERR_OK) + return retVal; + } + + /*Set DSCP Priority*/ + for (dscp = 0; dscp <= 63; dscp++) + { + if ((retVal = rtl8367c_setAsicPriorityDscpBased(dscp, 0)) != RT_ERR_OK) + return retVal; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_qos_priSel_set + * Description: + * Configure the priority order among different priority mechanism. + * Input: + * index - Priority decision table index (0~1) + * pPriDec - Priority assign for port, dscp, 802.1p, cvlan, svlan, acl based priority decision. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_SEL_PRI_SOURCE - Invalid priority decision source parameter. + * Note: + * ASIC will follow user priority setting of mechanisms to select mapped queue priority for receiving frame. + * If two priority mechanisms are the same, the ASIC will chose the highest priority from mechanisms to + * assign queue priority to receiving frame. + * The priority sources are: + * - PRIDEC_PORT + * - PRIDEC_ACL + * - PRIDEC_DSCP + * - PRIDEC_1Q + * - PRIDEC_1AD + * - PRIDEC_CVLAN + * - PRIDEC_DA + * - PRIDEC_SA + */ +rtk_api_ret_t dal_rtl8367c_qos_priSel_set(rtk_qos_priDecTbl_t index, rtk_priority_select_t *pPriDec) +{ + rtk_api_ret_t retVal; + rtk_uint32 port_pow; + rtk_uint32 dot1q_pow; + rtk_uint32 dscp_pow; + rtk_uint32 acl_pow; + rtk_uint32 svlan_pow; + rtk_uint32 cvlan_pow; + rtk_uint32 smac_pow; + rtk_uint32 dmac_pow; + rtk_uint32 i; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (index < 0 || index >= PRIDECTBL_END) + return RT_ERR_ENTRY_INDEX; + + if (pPriDec->port_pri >= 8 || pPriDec->dot1q_pri >= 8 || pPriDec->acl_pri >= 8 || pPriDec->dscp_pri >= 8 || + pPriDec->cvlan_pri >= 8 || pPriDec->svlan_pri >= 8 || pPriDec->dmac_pri >= 8 || pPriDec->smac_pri >= 8) + return RT_ERR_QOS_SEL_PRI_SOURCE; + + port_pow = 1; + for (i = pPriDec->port_pri; i > 0; i--) + port_pow = (port_pow)*2; + + dot1q_pow = 1; + for (i = pPriDec->dot1q_pri; i > 0; i--) + dot1q_pow = (dot1q_pow)*2; + + acl_pow = 1; + for (i = pPriDec->acl_pri; i > 0; i--) + acl_pow = (acl_pow)*2; + + dscp_pow = 1; + for (i = pPriDec->dscp_pri; i > 0; i--) + dscp_pow = (dscp_pow)*2; + + svlan_pow = 1; + for (i = pPriDec->svlan_pri; i > 0; i--) + svlan_pow = (svlan_pow)*2; + + cvlan_pow = 1; + for (i = pPriDec->cvlan_pri; i > 0; i--) + cvlan_pow = (cvlan_pow)*2; + + dmac_pow = 1; + for (i = pPriDec->dmac_pri; i > 0; i--) + dmac_pow = (dmac_pow)*2; + + smac_pow = 1; + for (i = pPriDec->smac_pri; i > 0; i--) + smac_pow = (smac_pow)*2; + + if ((retVal = rtl8367c_setAsicPriorityDecision(index, PRIDEC_PORT, port_pow)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicPriorityDecision(index, PRIDEC_ACL, acl_pow)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicPriorityDecision(index, PRIDEC_DSCP, dscp_pow)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicPriorityDecision(index, PRIDEC_1Q, dot1q_pow)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicPriorityDecision(index, PRIDEC_1AD, svlan_pow)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicPriorityDecision(index, PRIDEC_CVLAN, cvlan_pow)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicPriorityDecision(index, PRIDEC_DA, dmac_pow)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicPriorityDecision(index, PRIDEC_SA, smac_pow)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_qos_priSel_get + * Description: + * Get the priority order configuration among different priority mechanism. + * Input: + * index - Priority decision table index (0~1) + * Output: + * pPriDec - Priority assign for port, dscp, 802.1p, cvlan, svlan, acl based priority decision . + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * ASIC will follow user priority setting of mechanisms to select mapped queue priority for receiving frame. + * If two priority mechanisms are the same, the ASIC will chose the highest priority from mechanisms to + * assign queue priority to receiving frame. + * The priority sources are: + * - PRIDEC_PORT, + * - PRIDEC_ACL, + * - PRIDEC_DSCP, + * - PRIDEC_1Q, + * - PRIDEC_1AD, + * - PRIDEC_CVLAN, + * - PRIDEC_DA, + * - PRIDEC_SA, + */ +rtk_api_ret_t dal_rtl8367c_qos_priSel_get(rtk_qos_priDecTbl_t index, rtk_priority_select_t *pPriDec) +{ + + rtk_api_ret_t retVal; + rtk_int32 i; + rtk_uint32 port_pow; + rtk_uint32 dot1q_pow; + rtk_uint32 dscp_pow; + rtk_uint32 acl_pow; + rtk_uint32 svlan_pow; + rtk_uint32 cvlan_pow; + rtk_uint32 smac_pow; + rtk_uint32 dmac_pow; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (index < 0 || index >= PRIDECTBL_END) + return RT_ERR_ENTRY_INDEX; + + if ((retVal = rtl8367c_getAsicPriorityDecision(index, PRIDEC_PORT, &port_pow)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_getAsicPriorityDecision(index, PRIDEC_ACL, &acl_pow)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_getAsicPriorityDecision(index, PRIDEC_DSCP, &dscp_pow)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_getAsicPriorityDecision(index, PRIDEC_1Q, &dot1q_pow)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_getAsicPriorityDecision(index, PRIDEC_1AD, &svlan_pow)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_getAsicPriorityDecision(index, PRIDEC_CVLAN, &cvlan_pow)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_getAsicPriorityDecision(index, PRIDEC_DA, &dmac_pow)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_getAsicPriorityDecision(index, PRIDEC_SA, &smac_pow)) != RT_ERR_OK) + return retVal; + + for (i = 31; i >= 0; i--) + { + if (port_pow & (1 << i)) + { + pPriDec->port_pri = i; + break; + } + } + + for (i = 31; i >= 0; i--) + { + if (dot1q_pow & (1 << i)) + { + pPriDec->dot1q_pri = i; + break; + } + } + + for (i = 31; i >= 0; i--) + { + if (acl_pow & (1 << i)) + { + pPriDec->acl_pri = i; + break; + } + } + + for (i = 31; i >= 0; i--) + { + if (dscp_pow & (1 << i)) + { + pPriDec->dscp_pri = i; + break; + } + } + + for (i = 31; i >= 0; i--) + { + if (svlan_pow & (1 << i)) + { + pPriDec->svlan_pri = i; + break; + } + } + + for (i = 31;i >= 0; i--) + { + if (cvlan_pow & (1 << i)) + { + pPriDec->cvlan_pri = i; + break; + } + } + + for (i = 31; i >= 0; i--) + { + if (dmac_pow&(1<dmac_pri = i; + break; + } + } + + for (i = 31; i >= 0; i--) + { + if (smac_pow & (1 << i)) + { + pPriDec->smac_pri = i; + break; + } + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_qos_1pPriRemap_set + * Description: + * Configure 1Q priorities mapping to internal absolute priority. + * Input: + * dot1p_pri - 802.1p priority value. + * int_pri - internal priority value. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_VLAN_PRIORITY - Invalid 1p priority. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * Priority of 802.1Q assignment for internal asic priority, and it is used for queue usage and packet scheduling. + */ +rtk_api_ret_t dal_rtl8367c_qos_1pPriRemap_set(rtk_pri_t dot1p_pri, rtk_pri_t int_pri) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (dot1p_pri > RTL8367C_PRIMAX || int_pri > RTL8367C_PRIMAX) + return RT_ERR_VLAN_PRIORITY; + + if ((retVal = rtl8367c_setAsicPriorityDot1qRemapping(dot1p_pri, int_pri)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_qos_1pPriRemap_get + * Description: + * Get 1Q priorities mapping to internal absolute priority. + * Input: + * dot1p_pri - 802.1p priority value . + * Output: + * pInt_pri - internal priority value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_VLAN_PRIORITY - Invalid priority. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * Priority of 802.1Q assigment for internal asic priority, and it is uesed for queue usage and packet scheduling. + */ +rtk_api_ret_t dal_rtl8367c_qos_1pPriRemap_get(rtk_pri_t dot1p_pri, rtk_pri_t *pInt_pri) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (dot1p_pri > RTL8367C_PRIMAX) + return RT_ERR_QOS_INT_PRIORITY; + + if ((retVal = rtl8367c_getAsicPriorityDot1qRemapping(dot1p_pri, pInt_pri)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_qos_dscpPriRemap_set + * Description: + * Map dscp value to internal priority. + * Input: + * dscp - Dscp value of receiving frame + * int_pri - internal priority value . + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_QOS_DSCP_VALUE - Invalid DSCP value. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * The Differentiated Service Code Point is a selector for router's per-hop behaviors. As a selector, there is no implication that a numerically + * greater DSCP implies a better network service. As can be seen, the DSCP totally overlaps the old precedence field of TOS. So if values of + * DSCP are carefully chosen then backward compatibility can be achieved. + */ +rtk_api_ret_t dal_rtl8367c_qos_dscpPriRemap_set(rtk_dscp_t dscp, rtk_pri_t int_pri) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (int_pri > RTL8367C_PRIMAX ) + return RT_ERR_QOS_INT_PRIORITY; + + if (dscp > RTL8367C_DSCPMAX) + return RT_ERR_QOS_DSCP_VALUE; + + if ((retVal = rtl8367c_setAsicPriorityDscpBased(dscp, int_pri)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_qos_dscpPriRemap_get + * Description: + * Get dscp value to internal priority. + * Input: + * dscp - Dscp value of receiving frame + * Output: + * pInt_pri - internal priority value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_DSCP_VALUE - Invalid DSCP value. + * Note: + * The Differentiated Service Code Point is a selector for router's per-hop behaviors. As a selector, there is no implication that a numerically + * greater DSCP implies a better network service. As can be seen, the DSCP totally overlaps the old precedence field of TOS. So if values of + * DSCP are carefully chosen then backward compatibility can be achieved. + */ +rtk_api_ret_t dal_rtl8367c_qos_dscpPriRemap_get(rtk_dscp_t dscp, rtk_pri_t *pInt_pri) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (dscp > RTL8367C_DSCPMAX) + return RT_ERR_QOS_DSCP_VALUE; + + if ((retVal = rtl8367c_getAsicPriorityDscpBased(dscp, pInt_pri)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_qos_portPri_set + * Description: + * Configure priority usage to each port. + * Input: + * port - Port id. + * int_pri - internal priority value. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_QOS_SEL_PORT_PRI - Invalid port priority. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * The API can set priority of port assignments for queue usage and packet scheduling. + */ +rtk_api_ret_t dal_rtl8367c_qos_portPri_set(rtk_port_t port, rtk_pri_t int_pri) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if (int_pri > RTL8367C_PRIMAX ) + return RT_ERR_QOS_INT_PRIORITY; + + if ((retVal = rtl8367c_setAsicPriorityPortBased(rtk_switch_port_L2P_get(port), int_pri)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_qos_portPri_get + * Description: + * Get priority usage to each port. + * Input: + * port - Port id. + * Output: + * pInt_pri - internal priority value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get priority of port assignments for queue usage and packet scheduling. + */ +rtk_api_ret_t dal_rtl8367c_qos_portPri_get(rtk_port_t port, rtk_pri_t *pInt_pri) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if ((retVal = rtl8367c_getAsicPriorityPortBased(rtk_switch_port_L2P_get(port), pInt_pri)) != RT_ERR_OK) + return retVal; + + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_qos_queueNum_set + * Description: + * Set output queue number for each port. + * Input: + * port - Port id. + * index - Mapping queue number (1~8) + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_QUEUE_NUM - Invalid queue number. + * Note: + * The API can set the output queue number of the specified port. The queue number is from 1 to 8. + */ +rtk_api_ret_t dal_rtl8367c_qos_queueNum_set(rtk_port_t port, rtk_queue_num_t queue_num) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if ((0 == queue_num) || (queue_num > RTK_MAX_NUM_OF_QUEUE)) + return RT_ERR_FAILED; + + if (RTK_MAX_NUM_OF_QUEUE == queue_num) + queue_num = 0; + + if ((retVal = rtl8367c_setAsicOutputQueueMappingIndex(rtk_switch_port_L2P_get(port), queue_num)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_qos_queueNum_get + * Description: + * Get output queue number. + * Input: + * port - Port id. + * Output: + * pQueue_num - Mapping queue number + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API will return the output queue number of the specified port. The queue number is from 1 to 8. + */ +rtk_api_ret_t dal_rtl8367c_qos_queueNum_get(rtk_port_t port, rtk_queue_num_t *pQueue_num) +{ + rtk_api_ret_t retVal; + rtk_uint32 qidx; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if ((retVal = rtl8367c_getAsicOutputQueueMappingIndex(rtk_switch_port_L2P_get(port), &qidx)) != RT_ERR_OK) + return retVal; + + if (0 == qidx) + *pQueue_num = 8; + else + *pQueue_num = qidx; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_qos_priMap_set + * Description: + * Set output queue number for each port. + * Input: + * queue_num - Queue number usage. + * pPri2qid - Priority mapping to queue ID. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_QUEUE_ID - Invalid queue id. + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * ASIC supports priority mapping to queue with different queue number from 1 to 8. + * For different queue numbers usage, ASIC supports different internal available queue IDs. + */ +rtk_api_ret_t dal_rtl8367c_qos_priMap_set(rtk_queue_num_t queue_num, rtk_qos_pri2queue_t *pPri2qid) +{ + rtk_api_ret_t retVal; + rtk_uint32 pri; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if ((0 == queue_num) || (queue_num > RTK_MAX_NUM_OF_QUEUE)) + return RT_ERR_QUEUE_NUM; + + for (pri = 0; pri <= RTK_PRIMAX; pri++) + { + if (pPri2qid->pri2queue[pri] > RTK_QIDMAX) + return RT_ERR_QUEUE_ID; + + if ((retVal = rtl8367c_setAsicPriorityToQIDMappingTable(queue_num - 1, pri, pPri2qid->pri2queue[pri])) != RT_ERR_OK) + return retVal; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_qos_priMap_get + * Description: + * Get priority to queue ID mapping table parameters. + * Input: + * queue_num - Queue number usage. + * Output: + * pPri2qid - Priority mapping to queue ID. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_QUEUE_NUM - Invalid queue number. + * Note: + * The API can return the mapping queue id of the specified priority and queue number. + * The queue number is from 1 to 8. + */ +rtk_api_ret_t dal_rtl8367c_qos_priMap_get(rtk_queue_num_t queue_num, rtk_qos_pri2queue_t *pPri2qid) +{ + rtk_api_ret_t retVal; + rtk_uint32 pri; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if ((0 == queue_num) || (queue_num > RTK_MAX_NUM_OF_QUEUE)) + return RT_ERR_QUEUE_NUM; + + for (pri = 0; pri <= RTK_PRIMAX; pri++) + { + if ((retVal = rtl8367c_getAsicPriorityToQIDMappingTable(queue_num-1, pri, &pPri2qid->pri2queue[pri])) != RT_ERR_OK) + return retVal; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_qos_schedulingQueue_set + * Description: + * Set weight and type of queues in dedicated port. + * Input: + * port - Port id. + * pQweights - The array of weights for WRR/WFQ queue (0 for STRICT_PRIORITY queue). + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_QOS_QUEUE_WEIGHT - Invalid queue weight. + * Note: + * The API can set weight and type, strict priority or weight fair queue (WFQ) for + * dedicated port for using queues. If queue id is not included in queue usage, + * then its type and weight setting in dummy for setting. There are priorities + * as queue id in strict queues. It means strict queue id 5 carrying higher priority + * than strict queue id 4. The WFQ queue weight is from 1 to 127, and weight 0 is + * for strict priority queue type. + */ +rtk_api_ret_t dal_rtl8367c_qos_schedulingQueue_set(rtk_port_t port, rtk_qos_queue_weights_t *pQweights) +{ + rtk_api_ret_t retVal; + rtk_uint32 qid; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + for (qid = 0; qid < RTL8367C_QUEUENO; qid ++) + { + + if (pQweights->weights[qid] > QOS_WEIGHT_MAX) + return RT_ERR_QOS_QUEUE_WEIGHT; + + if (0 == pQweights->weights[qid]) + { + if ((retVal = rtl8367c_setAsicQueueType(rtk_switch_port_L2P_get(port), qid, QTYPE_STRICT)) != RT_ERR_OK) + return retVal; + } + else + { + if ((retVal = rtl8367c_setAsicQueueType(rtk_switch_port_L2P_get(port), qid, QTYPE_WFQ)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicWFQWeight(rtk_switch_port_L2P_get(port),qid, pQweights->weights[qid])) != RT_ERR_OK) + return retVal; + } + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_qos_schedulingQueue_get + * Description: + * Get weight and type of queues in dedicated port. + * Input: + * port - Port id. + * Output: + * pQweights - The array of weights for WRR/WFQ queue (0 for STRICT_PRIORITY queue). + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get weight and type, strict priority or weight fair queue (WFQ) for dedicated port for using queues. + * The WFQ queue weight is from 1 to 127, and weight 0 is for strict priority queue type. + */ +rtk_api_ret_t dal_rtl8367c_qos_schedulingQueue_get(rtk_port_t port, rtk_qos_queue_weights_t *pQweights) +{ + rtk_api_ret_t retVal; + rtk_uint32 qid,qtype,qweight; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + for (qid = 0; qid < RTL8367C_QUEUENO; qid++) + { + if ((retVal = rtl8367c_getAsicQueueType(rtk_switch_port_L2P_get(port), qid, &qtype)) != RT_ERR_OK) + return retVal; + + if (QTYPE_STRICT == qtype) + { + pQweights->weights[qid] = 0; + } + else if (QTYPE_WFQ == qtype) + { + if ((retVal = rtl8367c_getAsicWFQWeight(rtk_switch_port_L2P_get(port), qid, &qweight)) != RT_ERR_OK) + return retVal; + pQweights->weights[qid] = qweight; + } + } + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_qos_1pRemarkEnable_set + * Description: + * Set 1p Remarking state + * Input: + * port - Port id. + * enable - State of per-port 1p Remarking + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable parameter. + * Note: + * The API can enable or disable 802.1p remarking ability for whole system. + * The status of 802.1p remark: + * - DISABLED + * - ENABLED + */ +rtk_api_ret_t dal_rtl8367c_qos_1pRemarkEnable_set(rtk_port_t port, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if (enable >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if ((retVal = rtl8367c_setAsicRemarkingDot1pAbility(rtk_switch_port_L2P_get(port), enable)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_qos_1pRemarkEnable_get + * Description: + * Get 802.1p remarking ability. + * Input: + * port - Port id. + * Output: + * pEnable - Status of 802.1p remark. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get 802.1p remarking ability. + * The status of 802.1p remark: + * - DISABLED + * - ENABLED + */ +rtk_api_ret_t dal_rtl8367c_qos_1pRemarkEnable_get(rtk_port_t port, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if ((retVal = rtl8367c_getAsicRemarkingDot1pAbility(rtk_switch_port_L2P_get(port), pEnable)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_qos_1pRemark_set + * Description: + * Set 802.1p remarking parameter. + * Input: + * int_pri - Internal priority value. + * dot1p_pri - 802.1p priority value. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_VLAN_PRIORITY - Invalid 1p priority. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * The API can set 802.1p parameters source priority and new priority. + */ +rtk_api_ret_t dal_rtl8367c_qos_1pRemark_set(rtk_pri_t int_pri, rtk_pri_t dot1p_pri) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (int_pri > RTL8367C_PRIMAX ) + return RT_ERR_QOS_INT_PRIORITY; + + if (dot1p_pri > RTL8367C_PRIMAX) + return RT_ERR_VLAN_PRIORITY; + + if ((retVal = rtl8367c_setAsicRemarkingDot1pParameter(int_pri, dot1p_pri)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_qos_1pRemark_get + * Description: + * Get 802.1p remarking parameter. + * Input: + * int_pri - Internal priority value. + * Output: + * pDot1p_pri - 802.1p priority value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * The API can get 802.1p remarking parameters. It would return new priority of ingress priority. + */ +rtk_api_ret_t dal_rtl8367c_qos_1pRemark_get(rtk_pri_t int_pri, rtk_pri_t *pDot1p_pri) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (int_pri > RTL8367C_PRIMAX ) + return RT_ERR_QOS_INT_PRIORITY; + + if ((retVal = rtl8367c_getAsicRemarkingDot1pParameter(int_pri, pDot1p_pri)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_qos_1pRemarkSrcSel_set + * Description: + * Set remarking source of 802.1p remarking. + * Input: + * type - remarking source + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + + * Note: + * The API can configure 802.1p remark functionality to map original 802.1p value or internal + * priority to TX DSCP value. + */ +rtk_api_ret_t dal_rtl8367c_qos_1pRemarkSrcSel_set(rtk_qos_1pRmkSrc_t type) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (type >= DOT1P_RMK_SRC_END ) + return RT_ERR_QOS_INT_PRIORITY; + + if ((retVal = rtl8367c_setAsicRemarkingDot1pSrc(type)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_qos_1pRemarkSrcSel_get + * Description: + * Get remarking source of 802.1p remarking. + * Input: + * none + * Output: + * pType - remarking source + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * RT_ERR_NULL_POINTER - input parameter may be null pointer + + * Note: + * None + */ +rtk_api_ret_t dal_rtl8367c_qos_1pRemarkSrcSel_get(rtk_qos_1pRmkSrc_t *pType) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if ((retVal = rtl8367c_getAsicRemarkingDot1pSrc(pType)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_qos_dscpRemarkEnable_set + * Description: + * Set DSCP remarking ability. + * Input: + * port - Port id. + * enable - status of DSCP remark. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * RT_ERR_ENABLE - Invalid enable parameter. + * Note: + * The API can enable or disable DSCP remarking ability for whole system. + * The status of DSCP remark: + * - DISABLED + * - ENABLED + */ +rtk_api_ret_t dal_rtl8367c_qos_dscpRemarkEnable_set(rtk_port_t port, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /*for whole system function, the port value should be 0xFF*/ + if (port != RTK_WHOLE_SYSTEM) + return RT_ERR_PORT_ID; + + if (enable >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if ((retVal = rtl8367c_setAsicRemarkingDscpAbility(enable)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_qos_dscpRemarkEnable_get + * Description: + * Get DSCP remarking ability. + * Input: + * port - Port id. + * Output: + * pEnable - status of DSCP remarking. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get DSCP remarking ability. + * The status of DSCP remark: + * - DISABLED + * - ENABLED + */ +rtk_api_ret_t dal_rtl8367c_qos_dscpRemarkEnable_get(rtk_port_t port, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /*for whole system function, the port value should be 0xFF*/ + if (port != RTK_WHOLE_SYSTEM) + return RT_ERR_PORT_ID; + + if ((retVal = rtl8367c_getAsicRemarkingDscpAbility(pEnable)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_qos_dscpRemark_set + * Description: + * Set DSCP remarking parameter. + * Input: + * int_pri - Internal priority value. + * dscp - DSCP value. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * RT_ERR_QOS_DSCP_VALUE - Invalid DSCP value. + * Note: + * The API can set DSCP value and mapping priority. + */ +rtk_api_ret_t dal_rtl8367c_qos_dscpRemark_set(rtk_pri_t int_pri, rtk_dscp_t dscp) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (int_pri > RTK_PRIMAX ) + return RT_ERR_QOS_INT_PRIORITY; + + if (dscp > RTK_DSCPMAX) + return RT_ERR_QOS_DSCP_VALUE; + + if ((retVal = rtl8367c_setAsicRemarkingDscpParameter(int_pri, dscp)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_qos_dscpRemark_get + * Description: + * Get DSCP remarking parameter. + * Input: + * int_pri - Internal priority value. + * Output: + * Dscp - DSCP value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * The API can get DSCP parameters. It would return DSCP value for mapping priority. + */ + +rtk_api_ret_t dal_rtl8367c_qos_dscpRemark_get(rtk_pri_t int_pri, rtk_dscp_t *pDscp) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (int_pri > RTK_PRIMAX ) + return RT_ERR_QOS_INT_PRIORITY; + + if ((retVal = rtl8367c_getAsicRemarkingDscpParameter(int_pri, pDscp)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_qos_dscpRemarkSrcSel_set + * Description: + * Set remarking source of DSCP remarking. + * Input: + * type - remarking source + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + + * Note: + * The API can configure DSCP remark functionality to map original DSCP value or internal + * priority to TX DSCP value. + */ +rtk_api_ret_t dal_rtl8367c_qos_dscpRemarkSrcSel_set(rtk_qos_dscpRmkSrc_t type) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (type >= DSCP_RMK_SRC_END ) + return RT_ERR_QOS_INT_PRIORITY; + + if ((retVal = rtl8367c_setAsicRemarkingDscpSrc(type)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_qos_dscpRemarkSrcSel_get + * Description: + * Get remarking source of DSCP remarking. + * Input: + * none + * Output: + * pType - remarking source + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * RT_ERR_NULL_POINTER - input parameter may be null pointer + + * Note: + * None + */ +rtk_api_ret_t dal_rtl8367c_qos_dscpRemarkSrcSel_get(rtk_qos_dscpRmkSrc_t *pType) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if ((retVal = rtl8367c_getAsicRemarkingDscpSrc(pType)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_qos_dscpRemark2Dscp_set + * Description: + * Set DSCP to remarked DSCP mapping. + * Input: + * dscp - DSCP value + * rmkDscp - remarked DSCP value + * Output: + * None. + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_QOS_DSCP_VALUE - Invalid dscp value + * Note: + * dscp parameter can be DSCP value or internal priority according to configuration of API + * dal_apollomp_qos_dscpRemarkSrcSel_set(), because DSCP remark functionality can map original DSCP + * value or internal priority to TX DSCP value. + */ +rtk_api_ret_t dal_rtl8367c_qos_dscpRemark2Dscp_set(rtk_dscp_t dscp, rtk_dscp_t rmkDscp) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if ((dscp > RTK_DSCPMAX) || (rmkDscp > RTK_DSCPMAX)) + return RT_ERR_QOS_DSCP_VALUE; + + if ((retVal = rtl8367c_setAsicRemarkingDscp2Dscp(dscp, rmkDscp)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_qos_dscpRemark2Dscp_get + * Description: + * Get DSCP to remarked DSCP mapping. + * Input: + * dscp - DSCP value + * Output: + * pDscp - remarked DSCP value + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_QOS_DSCP_VALUE - Invalid dscp value + * RT_ERR_NULL_POINTER - NULL pointer + * Note: + * None. + */ +rtk_api_ret_t dal_rtl8367c_qos_dscpRemark2Dscp_get(rtk_dscp_t dscp, rtk_dscp_t *pDscp) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (dscp > RTK_DSCPMAX) + return RT_ERR_QOS_DSCP_VALUE; + + if ((retVal = rtl8367c_getAsicRemarkingDscp2Dscp(dscp, pDscp)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_qos_portPriSelIndex_set + * Description: + * Configure priority decision index to each port. + * Input: + * port - Port id. + * index - priority decision index. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENTRY_INDEX - Invalid entry index. + * Note: + * The API can set priority of port assignments for queue usage and packet scheduling. + */ +rtk_api_ret_t dal_rtl8367c_qos_portPriSelIndex_set(rtk_port_t port, rtk_qos_priDecTbl_t index) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if (index >= PRIDECTBL_END ) + return RT_ERR_ENTRY_INDEX; + + if ((retVal = rtl8367c_setAsicPortPriorityDecisionIndex(rtk_switch_port_L2P_get(port), index)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_qos_portPriSelIndex_get + * Description: + * Get priority decision index from each port. + * Input: + * port - Port id. + * Output: + * pIndex - priority decision index. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get priority of port assignments for queue usage and packet scheduling. + */ +rtk_api_ret_t dal_rtl8367c_qos_portPriSelIndex_get(rtk_port_t port, rtk_qos_priDecTbl_t *pIndex) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if ((retVal = rtl8367c_getAsicPortPriorityDecisionIndex(rtk_switch_port_L2P_get(port), pIndex)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_qos.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_qos.h new file mode 100644 index 00000000..7c458767 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_qos.h @@ -0,0 +1,681 @@ + /* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8367/RTL8367C switch high-level API + * + * Feature : The file includes QoS module high-layer API defination + * + */ + +#ifndef __DAL_RTL8367C_QOS_H__ +#define __DAL_RTL8367C_QOS_H__ + +#include + +/* Function Name: + * dal_rtl8367c_qos_init + * Description: + * Configure Qos default settings with queue number assigment to each port. + * Input: + * queueNum - Queue number of each port. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will initialize related Qos setting with queue number assigment. + * The queue number is from 1 to 8. + */ +extern rtk_api_ret_t dal_rtl8367c_qos_init(rtk_queue_num_t queueNum); + +/* Function Name: + * dal_rtl8367c_qos_priSel_set + * Description: + * Configure the priority order among different priority mechanism. + * Input: + * index - Priority decision table index (0~1) + * pPriDec - Priority assign for port, dscp, 802.1p, cvlan, svlan, acl based priority decision. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_SEL_PRI_SOURCE - Invalid priority decision source parameter. + * Note: + * ASIC will follow user priority setting of mechanisms to select mapped queue priority for receiving frame. + * If two priority mechanisms are the same, the ASIC will chose the highest priority from mechanisms to + * assign queue priority to receiving frame. + * The priority sources are: + * - PRIDEC_PORT + * - PRIDEC_ACL + * - PRIDEC_DSCP + * - PRIDEC_1Q + * - PRIDEC_1AD + * - PRIDEC_CVLAN + * - PRIDEC_DA + * - PRIDEC_SA + */ +extern rtk_api_ret_t dal_rtl8367c_qos_priSel_set(rtk_qos_priDecTbl_t index, rtk_priority_select_t *pPriDec); + + +/* Function Name: + * dal_rtl8367c_qos_priSel_get + * Description: + * Get the priority order configuration among different priority mechanism. + * Input: + * index - Priority decision table index (0~1) + * Output: + * pPriDec - Priority assign for port, dscp, 802.1p, cvlan, svlan, acl based priority decision . + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * ASIC will follow user priority setting of mechanisms to select mapped queue priority for receiving frame. + * If two priority mechanisms are the same, the ASIC will chose the highest priority from mechanisms to + * assign queue priority to receiving frame. + * The priority sources are: + * - PRIDEC_PORT, + * - PRIDEC_ACL, + * - PRIDEC_DSCP, + * - PRIDEC_1Q, + * - PRIDEC_1AD, + * - PRIDEC_CVLAN, + * - PRIDEC_DA, + * - PRIDEC_SA, + */ +extern rtk_api_ret_t dal_rtl8367c_qos_priSel_get(rtk_qos_priDecTbl_t index, rtk_priority_select_t *pPriDec); + +/* Function Name: + * dal_rtl8367c_qos_1pPriRemap_set + * Description: + * Configure 1Q priorities mapping to internal absolute priority. + * Input: + * dot1p_pri - 802.1p priority value. + * int_pri - internal priority value. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_VLAN_PRIORITY - Invalid 1p priority. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * Priority of 802.1Q assignment for internal asic priority, and it is used for queue usage and packet scheduling. + */ +extern rtk_api_ret_t dal_rtl8367c_qos_1pPriRemap_set(rtk_pri_t dot1p_pri, rtk_pri_t int_pri); + +/* Function Name: + * dal_rtl8367c_qos_1pPriRemap_get + * Description: + * Get 1Q priorities mapping to internal absolute priority. + * Input: + * dot1p_pri - 802.1p priority value . + * Output: + * pInt_pri - internal priority value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_VLAN_PRIORITY - Invalid priority. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * Priority of 802.1Q assigment for internal asic priority, and it is uesed for queue usage and packet scheduling. + */ +extern rtk_api_ret_t dal_rtl8367c_qos_1pPriRemap_get(rtk_pri_t dot1p_pri, rtk_pri_t *pInt_pri); + + +/* Function Name: + * dal_rtl8367c_qos_1pRemarkSrcSel_set + * Description: + * Set remarking source of 802.1p remarking. + * Input: + * type - remarking source + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + + * Note: + * The API can configure 802.1p remark functionality to map original 802.1p value or internal + * priority to TX DSCP value. + */ +extern rtk_api_ret_t dal_rtl8367c_qos_1pRemarkSrcSel_set(rtk_qos_1pRmkSrc_t type); + +/* Function Name: + * dal_rtl8367c_qos_1pRemarkSrcSel_get + * Description: + * Get remarking source of 802.1p remarking. + * Input: + * none + * Output: + * pType - remarking source + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * RT_ERR_NULL_POINTER - input parameter may be null pointer + + * Note: + * None + */ +extern rtk_api_ret_t dal_rtl8367c_qos_1pRemarkSrcSel_get(rtk_qos_1pRmkSrc_t *pType); + +/* Function Name: + * dal_rtl8367c_qos_dscpPriRemap_set + * Description: + * Map dscp value to internal priority. + * Input: + * dscp - Dscp value of receiving frame + * int_pri - internal priority value . + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_QOS_DSCP_VALUE - Invalid DSCP value. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * The Differentiated Service Code Point is a selector for router's per-hop behaviors. As a selector, there is no implication that a numerically + * greater DSCP implies a better network service. As can be seen, the DSCP totally overlaps the old precedence field of TOS. So if values of + * DSCP are carefully chosen then backward compatibility can be achieved. + */ +extern rtk_api_ret_t dal_rtl8367c_qos_dscpPriRemap_set(rtk_dscp_t dscp, rtk_pri_t int_pri); + +/* Function Name: + * dal_rtl8367c_qos_dscpPriRemap_get + * Description: + * Get dscp value to internal priority. + * Input: + * dscp - Dscp value of receiving frame + * Output: + * pInt_pri - internal priority value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_DSCP_VALUE - Invalid DSCP value. + * Note: + * The Differentiated Service Code Point is a selector for router's per-hop behaviors. As a selector, there is no implication that a numerically + * greater DSCP implies a better network service. As can be seen, the DSCP totally overlaps the old precedence field of TOS. So if values of + * DSCP are carefully chosen then backward compatibility can be achieved. + */ +extern rtk_api_ret_t dal_rtl8367c_qos_dscpPriRemap_get(rtk_dscp_t dscp, rtk_pri_t *pInt_pri); + +/* Function Name: + * dal_rtl8367c_qos_portPri_set + * Description: + * Configure priority usage to each port. + * Input: + * port - Port id. + * int_pri - internal priority value. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_QOS_SEL_PORT_PRI - Invalid port priority. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * The API can set priority of port assignments for queue usage and packet scheduling. + */ +extern rtk_api_ret_t dal_rtl8367c_qos_portPri_set(rtk_port_t port, rtk_pri_t int_pri) ; + +/* Function Name: + * dal_rtl8367c_qos_portPri_get + * Description: + * Get priority usage to each port. + * Input: + * port - Port id. + * Output: + * pInt_pri - internal priority value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get priority of port assignments for queue usage and packet scheduling. + */ +extern rtk_api_ret_t dal_rtl8367c_qos_portPri_get(rtk_port_t port, rtk_pri_t *pInt_pri) ; + +/* Function Name: + * dal_rtl8367c_qos_queueNum_set + * Description: + * Set output queue number for each port. + * Input: + * port - Port id. + * index - Mapping queue number (1~8) + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_QUEUE_NUM - Invalid queue number. + * Note: + * The API can set the output queue number of the specified port. The queue number is from 1 to 8. + */ +extern rtk_api_ret_t dal_rtl8367c_qos_queueNum_set(rtk_port_t port, rtk_queue_num_t queue_num); + +/* Function Name: + * dal_rtl8367c_qos_queueNum_get + * Description: + * Get output queue number. + * Input: + * port - Port id. + * Output: + * pQueue_num - Mapping queue number + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API will return the output queue number of the specified port. The queue number is from 1 to 8. + */ +extern rtk_api_ret_t dal_rtl8367c_qos_queueNum_get(rtk_port_t port, rtk_queue_num_t *pQueue_num); + +/* Function Name: + * dal_rtl8367c_qos_priMap_set + * Description: + * Set output queue number for each port. + * Input: + * queue_num - Queue number usage. + * pPri2qid - Priority mapping to queue ID. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_QUEUE_ID - Invalid queue id. + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * ASIC supports priority mapping to queue with different queue number from 1 to 8. + * For different queue numbers usage, ASIC supports different internal available queue IDs. + */ +extern rtk_api_ret_t dal_rtl8367c_qos_priMap_set(rtk_queue_num_t queue_num, rtk_qos_pri2queue_t *pPri2qid); + + +/* Function Name: + * dal_rtl8367c_qos_priMap_get + * Description: + * Get priority to queue ID mapping table parameters. + * Input: + * queue_num - Queue number usage. + * Output: + * pPri2qid - Priority mapping to queue ID. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_QUEUE_NUM - Invalid queue number. + * Note: + * The API can return the mapping queue id of the specified priority and queue number. + * The queue number is from 1 to 8. + */ +extern rtk_api_ret_t dal_rtl8367c_qos_priMap_get(rtk_queue_num_t queue_num, rtk_qos_pri2queue_t *pPri2qid); + +/* Function Name: + * dal_rtl8367c_qos_schedulingQueue_set + * Description: + * Set weight and type of queues in dedicated port. + * Input: + * port - Port id. + * pQweights - The array of weights for WRR/WFQ queue (0 for STRICT_PRIORITY queue). + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_QOS_QUEUE_WEIGHT - Invalid queue weight. + * Note: + * The API can set weight and type, strict priority or weight fair queue (WFQ) for + * dedicated port for using queues. If queue id is not included in queue usage, + * then its type and weight setting in dummy for setting. There are priorities + * as queue id in strict queues. It means strict queue id 5 carrying higher priority + * than strict queue id 4. The WFQ queue weight is from 1 to 128, and weight 0 is + * for strict priority queue type. + */ +extern rtk_api_ret_t dal_rtl8367c_qos_schedulingQueue_set(rtk_port_t port, rtk_qos_queue_weights_t *pQweights); + +/* Function Name: + * dal_rtl8367c_qos_schedulingQueue_get + * Description: + * Get weight and type of queues in dedicated port. + * Input: + * port - Port id. + * Output: + * pQweights - The array of weights for WRR/WFQ queue (0 for STRICT_PRIORITY queue). + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get weight and type, strict priority or weight fair queue (WFQ) for dedicated port for using queues. + * The WFQ queue weight is from 1 to 128, and weight 0 is for strict priority queue type. + */ +extern rtk_api_ret_t dal_rtl8367c_qos_schedulingQueue_get(rtk_port_t port, rtk_qos_queue_weights_t *pQweights); + +/* Function Name: + * dal_rtl8367c_qos_1pRemarkEnable_set + * Description: + * Set 1p Remarking state + * Input: + * port - Port id. + * enable - State of per-port 1p Remarking + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable parameter. + * Note: + * The API can enable or disable 802.1p remarking ability for whole system. + * The status of 802.1p remark: + * - DISABLED + * - ENABLED + */ +extern rtk_api_ret_t dal_rtl8367c_qos_1pRemarkEnable_set(rtk_port_t port, rtk_enable_t enable); + +/* Function Name: + * dal_rtl8367c_qos_1pRemarkEnable_get + * Description: + * Get 802.1p remarking ability. + * Input: + * port - Port id. + * Output: + * pEnable - Status of 802.1p remark. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get 802.1p remarking ability. + * The status of 802.1p remark: + * - DISABLED + * - ENABLED + */ +extern rtk_api_ret_t dal_rtl8367c_qos_1pRemarkEnable_get(rtk_port_t port, rtk_enable_t *pEnable); + +/* Function Name: + * dal_rtl8367c_qos_1pRemark_set + * Description: + * Set 802.1p remarking parameter. + * Input: + * int_pri - Internal priority value. + * dot1p_pri - 802.1p priority value. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_VLAN_PRIORITY - Invalid 1p priority. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * The API can set 802.1p parameters source priority and new priority. + */ +extern rtk_api_ret_t dal_rtl8367c_qos_1pRemark_set(rtk_pri_t int_pri, rtk_pri_t dot1p_pri); + +/* Function Name: + * dal_rtl8367c_qos_1pRemark_get + * Description: + * Get 802.1p remarking parameter. + * Input: + * int_pri - Internal priority value. + * Output: + * pDot1p_pri - 802.1p priority value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * The API can get 802.1p remarking parameters. It would return new priority of ingress priority. + */ +extern rtk_api_ret_t dal_rtl8367c_qos_1pRemark_get(rtk_pri_t int_pri, rtk_pri_t *pDot1p_pri); + +/* Function Name: + * dal_rtl8367c_qos_dscpRemarkEnable_set + * Description: + * Set DSCP remarking ability. + * Input: + * port - Port id. + * enable - status of DSCP remark. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * RT_ERR_ENABLE - Invalid enable parameter. + * Note: + * The API can enable or disable DSCP remarking ability for whole system. + * The status of DSCP remark: + * - DISABLED + * - ENABLED + */ +extern rtk_api_ret_t dal_rtl8367c_qos_dscpRemarkEnable_set(rtk_port_t port, rtk_enable_t enable); + +/* Function Name: + * dal_rtl8367c_qos_dscpRemarkEnable_get + * Description: + * Get DSCP remarking ability. + * Input: + * port - Port id. + * Output: + * pEnable - status of DSCP remarking. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get DSCP remarking ability. + * The status of DSCP remark: + * - DISABLED + * - ENABLED + */ +extern rtk_api_ret_t dal_rtl8367c_qos_dscpRemarkEnable_get(rtk_port_t port, rtk_enable_t *pEnable); + +/* Function Name: + * dal_rtl8367c_qos_dscpRemark_set + * Description: + * Set DSCP remarking parameter. + * Input: + * int_pri - Internal priority value. + * dscp - DSCP value. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * RT_ERR_QOS_DSCP_VALUE - Invalid DSCP value. + * Note: + * The API can set DSCP value and mapping priority. + */ +extern rtk_api_ret_t dal_rtl8367c_qos_dscpRemark_set(rtk_pri_t int_pri, rtk_dscp_t dscp); + +/* Function Name: + * dal_rtl8367c_qos_dscpRemark_get + * Description: + * Get DSCP remarking parameter. + * Input: + * int_pri - Internal priority value. + * Output: + * Dscp - DSCP value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * The API can get DSCP parameters. It would return DSCP value for mapping priority. + */ +extern rtk_api_ret_t dal_rtl8367c_qos_dscpRemark_get(rtk_pri_t int_pri, rtk_dscp_t *pDscp); + +/* Function Name: + * dal_rtl8367c_qos_dscpRemarkSrcSel_set + * Description: + * Set remarking source of DSCP remarking. + * Input: + * type - remarking source + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + + * Note: + * The API can configure DSCP remark functionality to map original DSCP value or internal + * priority to TX DSCP value. + */ +extern rtk_api_ret_t dal_rtl8367c_qos_dscpRemarkSrcSel_set(rtk_qos_dscpRmkSrc_t type); + + +/* Function Name: + * dal_rtl8367c_qos_dcpRemarkSrcSel_get + * Description: + * Get remarking source of DSCP remarking. + * Input: + * none + * Output: + * pType - remarking source + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * RT_ERR_NULL_POINTER - input parameter may be null pointer + + * Note: + * None + */ +extern rtk_api_ret_t dal_rtl8367c_qos_dscpRemarkSrcSel_get(rtk_qos_dscpRmkSrc_t *pType); + + +/* Function Name: + * dal_rtl8367c_qos_dscpRemark2Dscp_set + * Description: + * Set DSCP to remarked DSCP mapping. + * Input: + * dscp - DSCP value + * rmkDscp - remarked DSCP value + * Output: + * None. + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_QOS_DSCP_VALUE - Invalid dscp value + * Note: + * dscp parameter can be DSCP value or internal priority according to configuration of API + * dal_apollomp_qos_dscpRemarkSrcSel_set(), because DSCP remark functionality can map original DSCP + * value or internal priority to TX DSCP value. + */ +extern rtk_api_ret_t dal_rtl8367c_qos_dscpRemark2Dscp_set(rtk_dscp_t dscp, rtk_dscp_t rmkDscp); + +/* Function Name: + * dal_rtl8367c_qos_dscpRemark2Dscp_get + * Description: + * Get DSCP to remarked DSCP mapping. + * Input: + * dscp - DSCP value + * Output: + * pDscp - remarked DSCP value + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_QOS_DSCP_VALUE - Invalid dscp value + * RT_ERR_NULL_POINTER - NULL pointer + * Note: + * None. + */ +extern rtk_api_ret_t dal_rtl8367c_qos_dscpRemark2Dscp_get(rtk_dscp_t dscp, rtk_dscp_t *pDscp); + +/* Function Name: + * dal_rtl8367c_qos_portPriSelIndex_set + * Description: + * Configure priority decision index to each port. + * Input: + * port - Port id. + * index - priority decision index. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENTRY_INDEX - Invalid entry index. + * Note: + * The API can set priority of port assignments for queue usage and packet scheduling. + */ +extern rtk_api_ret_t dal_rtl8367c_qos_portPriSelIndex_set(rtk_port_t port, rtk_qos_priDecTbl_t index); + +/* Function Name: + * dal_rtl8367c_qos_portPriSelIndex_get + * Description: + * Get priority decision index from each port. + * Input: + * port - Port id. + * Output: + * pIndex - priority decision index. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get priority of port assignments for queue usage and packet scheduling. + */ +extern rtk_api_ret_t dal_rtl8367c_qos_portPriSelIndex_get(rtk_port_t port, rtk_qos_priDecTbl_t *pIndex); + +#endif /* __DAL_RTL8367C_QOS_H__*/ diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_rate.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_rate.c new file mode 100644 index 00000000..9b3620e9 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_rate.c @@ -0,0 +1,608 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8367C + * Feature : Here is a list of all functions and variables in rate module. + * + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +/* Function Name: + * dal_rtl8367c_rate_shareMeter_set + * Description: + * Set meter configuration + * Input: + * index - shared meter index + * type - shared meter type + * rate - rate of share meter + * ifg_include - include IFG or not, ENABLE:include DISABLE:exclude + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_METER_ID - Invalid meter + * RT_ERR_RATE - Invalid rate + * RT_ERR_INPUT - Invalid input parameters + * Note: + * The API can set shared meter rate and ifg include for each meter. + * The rate unit is 1 kbps and the range is from 8k to 1048568k if type is METER_TYPE_KBPS and + * the granularity of rate is 8 kbps. + * The rate unit is packets per second and the range is 1 ~ 0x1FFF if type is METER_TYPE_PPS. + * The ifg_include parameter is used + * for rate calculation with/without inter-frame-gap and preamble. + */ +rtk_api_ret_t dal_rtl8367c_rate_shareMeter_set(rtk_meter_id_t index, rtk_meter_type_t type, rtk_rate_t rate, rtk_enable_t ifg_include) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (index > RTK_MAX_METER_ID) + return RT_ERR_FILTER_METER_ID; + + if (type >= METER_TYPE_END) + return RT_ERR_INPUT; + + if (ifg_include >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + switch (type) + { + case METER_TYPE_KBPS: + if (rate > RTL8367C_QOS_RATE_INPUT_MAX_HSG || rate < RTL8367C_QOS_RATE_INPUT_MIN) + return RT_ERR_RATE ; + + if ((retVal = rtl8367c_setAsicShareMeter(index, rate >> 3, ifg_include)) != RT_ERR_OK) + return retVal; + + break; + case METER_TYPE_PPS: + if (rate > RTL8367C_QOS_PPS_INPUT_MAX || rate < RTL8367C_QOS_PPS_INPUT_MIN) + return RT_ERR_RATE ; + + if ((retVal = rtl8367c_setAsicShareMeter(index, rate, ifg_include)) != RT_ERR_OK) + return retVal; + + break; + default: + return RT_ERR_INPUT; + } + + /* Set Type */ + if ((retVal = rtl8367c_setAsicShareMeterType(index, (rtk_uint32)type)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_rate_shareMeter_get + * Description: + * Get meter configuration + * Input: + * index - shared meter index + * Output: + * pType - Meter Type + * pRate - pointer of rate of share meter + * pIfg_include - include IFG or not, ENABLE:include DISABLE:exclude + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_METER_ID - Invalid meter + * Note: + * + */ +rtk_api_ret_t dal_rtl8367c_rate_shareMeter_get(rtk_meter_id_t index, rtk_meter_type_t *pType, rtk_rate_t *pRate, rtk_enable_t *pIfg_include) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (index > RTK_MAX_METER_ID) + return RT_ERR_FILTER_METER_ID; + + if(NULL == pType) + return RT_ERR_NULL_POINTER; + + if(NULL == pRate) + return RT_ERR_NULL_POINTER; + + if(NULL == pIfg_include) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicShareMeter(index, ®Data, pIfg_include)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_getAsicShareMeterType(index, (rtk_uint32 *)pType)) != RT_ERR_OK) + return retVal; + + if(*pType == METER_TYPE_KBPS) + *pRate = regData<<3; + else + *pRate = regData; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_rate_shareMeterBucket_set + * Description: + * Set meter Bucket Size + * Input: + * index - shared meter index + * bucket_size - Bucket Size + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_INPUT - Error Input + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_METER_ID - Invalid meter + * Note: + * The API can set shared meter bucket size. + */ +rtk_api_ret_t dal_rtl8367c_rate_shareMeterBucket_set(rtk_meter_id_t index, rtk_uint32 bucket_size) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (index > RTK_MAX_METER_ID) + return RT_ERR_FILTER_METER_ID; + + if(bucket_size > RTL8367C_METERBUCKETSIZEMAX) + return RT_ERR_INPUT; + + if ((retVal = rtl8367c_setAsicShareMeterBucketSize(index, bucket_size)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_rate_shareMeterBucket_get + * Description: + * Get meter Bucket Size + * Input: + * index - shared meter index + * Output: + * pBucket_size - Bucket Size + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_METER_ID - Invalid meter + * Note: + * The API can get shared meter bucket size. + */ +rtk_api_ret_t dal_rtl8367c_rate_shareMeterBucket_get(rtk_meter_id_t index, rtk_uint32 *pBucket_size) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (index > RTK_MAX_METER_ID) + return RT_ERR_FILTER_METER_ID; + + if(NULL == pBucket_size) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicShareMeterBucketSize(index, pBucket_size)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_rate_igrBandwidthCtrlRate_set + * Description: + * Set port ingress bandwidth control + * Input: + * port - Port id + * rate - Rate of share meter + * ifg_include - include IFG or not, ENABLE:include DISABLE:exclude + * fc_enable - enable flow control or not, ENABLE:use flow control DISABLE:drop + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid IFG parameter. + * RT_ERR_INBW_RATE - Invalid ingress rate parameter. + * Note: + * The rate unit is 1 kbps and the range is from 8k to 1048568k. The granularity of rate is 8 kbps. + * The ifg_include parameter is used for rate calculation with/without inter-frame-gap and preamble. + */ +rtk_api_ret_t dal_rtl8367c_rate_igrBandwidthCtrlRate_set(rtk_port_t port, rtk_rate_t rate, rtk_enable_t ifg_include, rtk_enable_t fc_enable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if(ifg_include >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if(fc_enable >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if(rtk_switch_isHsgPort(port) == RT_ERR_OK) + { + if ((rate > RTL8367C_QOS_RATE_INPUT_MAX_HSG) || (rate < RTL8367C_QOS_RATE_INPUT_MIN)) + return RT_ERR_QOS_EBW_RATE ; + } + else + { + if ((rate > RTL8367C_QOS_RATE_INPUT_MAX) || (rate < RTL8367C_QOS_RATE_INPUT_MIN)) + return RT_ERR_QOS_EBW_RATE ; + } + + if ((retVal = rtl8367c_setAsicPortIngressBandwidth(rtk_switch_port_L2P_get(port), rate>>3, ifg_include,fc_enable)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_rate_igrBandwidthCtrlRate_get + * Description: + * Get port ingress bandwidth control + * Input: + * port - Port id + * Output: + * pRate - Rate of share meter + * pIfg_include - Rate's calculation including IFG, ENABLE:include DISABLE:exclude + * pFc_enable - enable flow control or not, ENABLE:use flow control DISABLE:drop + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The rate unit is 1 kbps and the range is from 8k to 1048568k. The granularity of rate is 8 kbps. + * The ifg_include parameter is used for rate calculation with/without inter-frame-gap and preamble. + */ +rtk_api_ret_t dal_rtl8367c_rate_igrBandwidthCtrlRate_get(rtk_port_t port, rtk_rate_t *pRate, rtk_enable_t *pIfg_include, rtk_enable_t *pFc_enable) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if(NULL == pIfg_include) + return RT_ERR_NULL_POINTER; + + if(NULL == pFc_enable) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicPortIngressBandwidth(rtk_switch_port_L2P_get(port), ®Data, pIfg_include, pFc_enable)) != RT_ERR_OK) + return retVal; + + *pRate = regData<<3; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_rate_egrBandwidthCtrlRate_set + * Description: + * Set port egress bandwidth control + * Input: + * port - Port id + * rate - Rate of egress bandwidth + * ifg_include - include IFG or not, ENABLE:include DISABLE:exclude + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_QOS_EBW_RATE - Invalid egress bandwidth/rate + * Note: + * The rate unit is 1 kbps and the range is from 8k to 1048568k. The granularity of rate is 8 kbps. + * The ifg_include parameter is used for rate calculation with/without inter-frame-gap and preamble. + */ +rtk_api_ret_t dal_rtl8367c_rate_egrBandwidthCtrlRate_set( rtk_port_t port, rtk_rate_t rate, rtk_enable_t ifg_include) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if(rtk_switch_isHsgPort(port) == RT_ERR_OK) + { + if ((rate > RTL8367C_QOS_RATE_INPUT_MAX_HSG) || (rate < RTL8367C_QOS_RATE_INPUT_MIN)) + return RT_ERR_QOS_EBW_RATE ; + } + else + { + if ((rate > RTL8367C_QOS_RATE_INPUT_MAX) || (rate < RTL8367C_QOS_RATE_INPUT_MIN)) + return RT_ERR_QOS_EBW_RATE ; + } + + if (ifg_include >= RTK_ENABLE_END) + return RT_ERR_ENABLE; + + if ((retVal = rtl8367c_setAsicPortEgressRate(rtk_switch_port_L2P_get(port), rate>>3)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicPortEgressRateIfg(ifg_include)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_rate_egrBandwidthCtrlRate_get + * Description: + * Get port egress bandwidth control + * Input: + * port - Port id + * Output: + * pRate - Rate of egress bandwidth + * pIfg_include - Rate's calculation including IFG, ENABLE:include DISABLE:exclude + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The rate unit is 1 kbps and the range is from 8k to 1048568k. The granularity of rate is 8 kbps. + * The ifg_include parameter is used for rate calculation with/without inter-frame-gap and preamble. + */ +rtk_api_ret_t dal_rtl8367c_rate_egrBandwidthCtrlRate_get(rtk_port_t port, rtk_rate_t *pRate, rtk_enable_t *pIfg_include) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if(NULL == pRate) + return RT_ERR_NULL_POINTER; + + if(NULL == pIfg_include) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicPortEgressRate(rtk_switch_port_L2P_get(port), ®Data)) != RT_ERR_OK) + return retVal; + + *pRate = regData << 3; + + if ((retVal = rtl8367c_getAsicPortEgressRateIfg((rtk_uint32*)pIfg_include)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_rate_egrQueueBwCtrlEnable_get + * Description: + * Get enable status of egress bandwidth control on specified queue. + * Input: + * unit - unit id + * port - port id + * queue - queue id + * Output: + * pEnable - Pointer to enable status of egress queue bandwidth control + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_QUEUE_ID - invalid queue id + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None + */ +rtk_api_ret_t dal_rtl8367c_rate_egrQueueBwCtrlEnable_get(rtk_port_t port, rtk_qid_t queue, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + /*for whole port function, the queue value should be 0xFF*/ + if (queue != RTK_WHOLE_SYSTEM) + return RT_ERR_QUEUE_ID; + + if(NULL == pEnable) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicAprEnable(rtk_switch_port_L2P_get(port),pEnable))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_rate_egrQueueBwCtrlEnable_set + * Description: + * Set enable status of egress bandwidth control on specified queue. + * Input: + * port - port id + * queue - queue id + * enable - enable status of egress queue bandwidth control + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_QUEUE_ID - invalid queue id + * RT_ERR_INPUT - invalid input parameter + * Note: + * None + */ +rtk_api_ret_t dal_rtl8367c_rate_egrQueueBwCtrlEnable_set(rtk_port_t port, rtk_qid_t queue, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + /*for whole port function, the queue value should be 0xFF*/ + if (queue != RTK_WHOLE_SYSTEM) + return RT_ERR_QUEUE_ID; + + if (enable>=RTK_ENABLE_END) + return RT_ERR_INPUT; + + if ((retVal = rtl8367c_setAsicAprEnable(rtk_switch_port_L2P_get(port), enable))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_rate_egrQueueBwCtrlRate_get + * Description: + * Get rate of egress bandwidth control on specified queue. + * Input: + * port - port id + * queue - queue id + * pIndex - shared meter index + * Output: + * pRate - pointer to rate of egress queue bandwidth control + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_QUEUE_ID - invalid queue id + * RT_ERR_FILTER_METER_ID - Invalid meter id + * Note: + * The actual rate control is set in shared meters. + * The unit of granularity is 8Kbps. + */ +rtk_api_ret_t dal_rtl8367c_rate_egrQueueBwCtrlRate_get(rtk_port_t port, rtk_qid_t queue, rtk_meter_id_t *pIndex) +{ + rtk_api_ret_t retVal; + rtk_uint32 offset_idx; + rtk_uint32 phy_port; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if (queue >= RTK_MAX_NUM_OF_QUEUE) + return RT_ERR_QUEUE_ID; + + if(NULL == pIndex) + return RT_ERR_NULL_POINTER; + + phy_port = rtk_switch_port_L2P_get(port); + if ((retVal=rtl8367c_getAsicAprMeter(phy_port, queue,&offset_idx))!=RT_ERR_OK) + return retVal; + + *pIndex = offset_idx + ((phy_port%4)*8); + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_rate_egrQueueBwCtrlRate_set + * Description: + * Set rate of egress bandwidth control on specified queue. + * Input: + * port - port id + * queue - queue id + * index - shared meter index + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_QUEUE_ID - invalid queue id + * RT_ERR_FILTER_METER_ID - Invalid meter id + * Note: + * The actual rate control is set in shared meters. + * The unit of granularity is 8Kbps. + */ +rtk_api_ret_t dal_rtl8367c_rate_egrQueueBwCtrlRate_set(rtk_port_t port, rtk_qid_t queue, rtk_meter_id_t index) +{ + rtk_api_ret_t retVal; + rtk_uint32 offset_idx; + rtk_uint32 phy_port; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if (queue >= RTK_MAX_NUM_OF_QUEUE) + return RT_ERR_QUEUE_ID; + + if (index > RTK_MAX_METER_ID) + return RT_ERR_FILTER_METER_ID; + + phy_port = rtk_switch_port_L2P_get(port); + if (index < ((phy_port%4)*8) || index > (7 + (phy_port%4)*8)) + return RT_ERR_FILTER_METER_ID; + + offset_idx = index - ((phy_port%4)*8); + + if ((retVal=rtl8367c_setAsicAprMeter(phy_port,queue,offset_idx))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_rate.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_rate.h new file mode 100644 index 00000000..4ba3f87d --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_rate.h @@ -0,0 +1,298 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8367/RTL8367C switch high-level API + * + * Feature : The file includes rate module high-layer API defination + * + */ + +#ifndef __DAL_RTL8367C_RATE_H__ +#define __DAL_RTL8367C_RATE_H__ + +/* + * Include Files + */ +#include + +/* + * Data Type Declaration + */ + +/* + * Function Declaration + */ + + /* Rate */ +/* Function Name: + * dal_rtl8367c_rate_shareMeter_set + * Description: + * Set meter configuration + * Input: + * index - shared meter index + * type - shared meter type + * rate - rate of share meter + * ifg_include - include IFG or not, ENABLE:include DISABLE:exclude + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_METER_ID - Invalid meter + * RT_ERR_RATE - Invalid rate + * RT_ERR_INPUT - Invalid input parameters + * Note: + * The API can set shared meter rate and ifg include for each meter. + * The rate unit is 1 kbps and the range is from 8k to 1048568k if type is METER_TYPE_KBPS and + * the granularity of rate is 8 kbps. + * The rate unit is packets per second and the range is 1 ~ 0x1FFF if type is METER_TYPE_PPS. + * The ifg_include parameter is used + * for rate calculation with/without inter-frame-gap and preamble. + */ +extern rtk_api_ret_t dal_rtl8367c_rate_shareMeter_set(rtk_meter_id_t index, rtk_meter_type_t type, rtk_rate_t rate, rtk_enable_t ifg_include); + +/* Function Name: + * dal_rtl8367c_rate_shareMeter_get + * Description: + * Get meter configuration + * Input: + * index - shared meter index + * Output: + * pType - Meter Type + * pRate - pointer of rate of share meter + * pIfg_include - include IFG or not, ENABLE:include DISABLE:exclude + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_METER_ID - Invalid meter + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367c_rate_shareMeter_get(rtk_meter_id_t index, rtk_meter_type_t *pType, rtk_rate_t *pRate, rtk_enable_t *pIfg_include); + +/* Function Name: + * dal_rtl8367c_rate_shareMeterBucket_set + * Description: + * Set meter Bucket Size + * Input: + * index - shared meter index + * bucket_size - Bucket Size + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_INPUT - Error Input + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_METER_ID - Invalid meter + * Note: + * The API can set shared meter bucket size. + */ +extern rtk_api_ret_t dal_rtl8367c_rate_shareMeterBucket_set(rtk_meter_id_t index, rtk_uint32 bucket_size); + +/* Function Name: + * dal_rtl8367c_rate_shareMeterBucket_get + * Description: + * Get meter Bucket Size + * Input: + * index - shared meter index + * Output: + * pBucket_size - Bucket Size + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_METER_ID - Invalid meter + * Note: + * The API can get shared meter bucket size. + */ +extern rtk_api_ret_t dal_rtl8367c_rate_shareMeterBucket_get(rtk_meter_id_t index, rtk_uint32 *pBucket_size); + +/* Function Name: + * dal_rtl8367c_rate_igrBandwidthCtrlRate_set + * Description: + * Set port ingress bandwidth control + * Input: + * port - Port id + * rate - Rate of share meter + * ifg_include - include IFG or not, ENABLE:include DISABLE:exclude + * fc_enable - enable flow control or not, ENABLE:use flow control DISABLE:drop + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid IFG parameter. + * RT_ERR_INBW_RATE - Invalid ingress rate parameter. + * Note: + * The rate unit is 1 kbps and the range is from 8k to 1048568k. The granularity of rate is 8 kbps. + * The ifg_include parameter is used for rate calculation with/without inter-frame-gap and preamble. + */ +extern rtk_api_ret_t dal_rtl8367c_rate_igrBandwidthCtrlRate_set( rtk_port_t port, rtk_rate_t rate, rtk_enable_t ifg_include, rtk_enable_t fc_enable); + +/* Function Name: + * dal_rtl8367c_rate_igrBandwidthCtrlRate_get + * Description: + * Get port ingress bandwidth control + * Input: + * port - Port id + * Output: + * pRate - Rate of share meter + * pIfg_include - Rate's calculation including IFG, ENABLE:include DISABLE:exclude + * pFc_enable - enable flow control or not, ENABLE:use flow control DISABLE:drop + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The rate unit is 1 kbps and the range is from 8k to 1048568k. The granularity of rate is 8 kbps. + * The ifg_include parameter is used for rate calculation with/without inter-frame-gap and preamble. + */ +extern rtk_api_ret_t dal_rtl8367c_rate_igrBandwidthCtrlRate_get(rtk_port_t port, rtk_rate_t *pRate, rtk_enable_t *pIfg_include, rtk_enable_t *pFc_enable); + +/* Function Name: + * dal_rtl8367c_rate_egrBandwidthCtrlRate_set + * Description: + * Set port egress bandwidth control + * Input: + * port - Port id + * rate - Rate of egress bandwidth + * ifg_include - include IFG or not, ENABLE:include DISABLE:exclude + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_QOS_EBW_RATE - Invalid egress bandwidth/rate + * Note: + * The rate unit is 1 kbps and the range is from 8k to 1048568k. The granularity of rate is 8 kbps. + * The ifg_include parameter is used for rate calculation with/without inter-frame-gap and preamble. + */ +extern rtk_api_ret_t dal_rtl8367c_rate_egrBandwidthCtrlRate_set(rtk_port_t port, rtk_rate_t rate, rtk_enable_t ifg_includ); + +/* Function Name: + * dal_rtl8367c_rate_egrBandwidthCtrlRate_get + * Description: + * Get port egress bandwidth control + * Input: + * port - Port id + * Output: + * pRate - Rate of egress bandwidth + * pIfg_include - Rate's calculation including IFG, ENABLE:include DISABLE:exclude + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The rate unit is 1 kbps and the range is from 8k to 1048568k. The granularity of rate is 8 kbps. + * The ifg_include parameter is used for rate calculation with/without inter-frame-gap and preamble. + */ +extern rtk_api_ret_t dal_rtl8367c_rate_egrBandwidthCtrlRate_get(rtk_port_t port, rtk_rate_t *pRate, rtk_enable_t *pIfg_include); + +/* Function Name: + * dal_rtl8367c_rate_egrQueueBwCtrlEnable_set + * Description: + * Set enable status of egress bandwidth control on specified queue. + * Input: + * port - port id + * queue - queue id + * enable - enable status of egress queue bandwidth control + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_QUEUE_ID - invalid queue id + * RT_ERR_INPUT - invalid input parameter + * Note: + * None + */ +extern rtk_api_ret_t dal_rtl8367c_rate_egrQueueBwCtrlEnable_set(rtk_port_t port, rtk_qid_t queue, rtk_enable_t enable); + +/* Function Name: + * dal_rtl8367c_rate_egrQueueBwCtrlRate_get + * Description: + * Get rate of egress bandwidth control on specified queue. + * Input: + * port - port id + * queue - queue id + * pIndex - shared meter index + * Output: + * pRate - pointer to rate of egress queue bandwidth control + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_QUEUE_ID - invalid queue id + * RT_ERR_FILTER_METER_ID - Invalid meter id + * Note: + * None. + */ +extern rtk_api_ret_t dal_rtl8367c_rate_egrQueueBwCtrlEnable_get(rtk_port_t port, rtk_qid_t queue, rtk_enable_t *pEnable); + +/* Function Name: + * dal_rtl8367c_rate_egrQueueBwCtrlRate_set + * Description: + * Set rate of egress bandwidth control on specified queue. + * Input: + * port - port id + * queue - queue id + * index - shared meter index + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_QUEUE_ID - invalid queue id + * RT_ERR_FILTER_METER_ID - Invalid meter id + * Note: + * The actual rate control is set in shared meters. + * The unit of granularity is 8Kbps. + */ +extern rtk_api_ret_t dal_rtl8367c_rate_egrQueueBwCtrlRate_set(rtk_port_t port, rtk_qid_t queue, rtk_meter_id_t index); + +/* Function Name: + * dal_rtl8367c_rate_egrQueueBwCtrlRate_get + * Description: + * Get rate of egress bandwidth control on specified queue. + * Input: + * port - port id + * queue - queue id + * pIndex - shared meter index + * Output: + * pRate - pointer to rate of egress queue bandwidth control + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_QUEUE_ID - invalid queue id + * RT_ERR_FILTER_METER_ID - Invalid meter id + * Note: + * The actual rate control is set in shared meters. + * The unit of granularity is 8Kbps. + */ +extern rtk_api_ret_t dal_rtl8367c_rate_egrQueueBwCtrlRate_get(rtk_port_t port, rtk_qid_t queue, rtk_meter_id_t *pIndex); + +#endif /* __DAL_RTL8367C_RATE_H__ */ + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_rldp.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_rldp.c new file mode 100644 index 00000000..3329335d --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_rldp.c @@ -0,0 +1,454 @@ +/* + * Copyright (C) 2012 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision: $ + * $Date: $ + * + * Purpose : Declaration of RLDP and RLPP API + * + * Feature : The file have include the following module and sub-modules + * 1) RLDP and RLPP configuration and status + * + */ + + +/* + * Include Files + */ +#include +#include +#include + + +#include +#include + + +/* Function Name: + * dal_rtl8367c_rldp_config_set + * Description: + * Set RLDP module configuration + * Input: + * pConfig - configuration structure of RLDP + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT + * RT_ERR_NULL_POINTER + * Note: + * None + */ +rtk_api_ret_t dal_rtl8367c_rldp_config_set(rtk_rldp_config_t *pConfig) +{ + rtk_api_ret_t retVal; + ether_addr_t magic; + rtk_uint32 pmsk; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (pConfig->rldp_enable >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if (pConfig->trigger_mode >= RTK_RLDP_TRIGGER_END) + return RT_ERR_INPUT; + + if (pConfig->compare_type >= RTK_RLDP_CMPTYPE_END) + return RT_ERR_INPUT; + + if (pConfig->num_check >= RTK_RLDP_NUM_MAX) + return RT_ERR_INPUT; + + if (pConfig->interval_check >= RTK_RLDP_INTERVAL_MAX) + return RT_ERR_INPUT; + + if (pConfig->num_loop >= RTK_RLDP_NUM_MAX) + return RT_ERR_INPUT; + + if (pConfig->interval_loop >= RTK_RLDP_INTERVAL_MAX) + return RT_ERR_INPUT; + + if ((retVal = rtl8367c_getAsicRldpTxPortmask(&pmsk))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicRldpTxPortmask(0x00))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicRldpTxPortmask(pmsk))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicRldp(pConfig->rldp_enable))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicRldpTriggerMode(pConfig->trigger_mode))!=RT_ERR_OK) + return retVal; + + memcpy(&magic, &pConfig->magic, sizeof(ether_addr_t)); + if ((retVal = rtl8367c_setAsicRldpMagicNum(magic))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicRldpCompareRandomNumber(pConfig->compare_type))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicRldpCompareRandomNumber(pConfig->compare_type))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicRldpCheckingStatePara(pConfig->num_check, pConfig->interval_check))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicRldpLoopStatePara(pConfig->num_loop, pConfig->interval_loop))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_rldp_config_get + * Description: + * Get RLDP module configuration + * Input: + * None + * Output: + * pConfig - configuration structure of RLDP + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT + * RT_ERR_NULL_POINTER + * Note: + * None + */ +rtk_api_ret_t dal_rtl8367c_rldp_config_get(rtk_rldp_config_t *pConfig) +{ + rtk_api_ret_t retVal; + ether_addr_t magic; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if ((retVal = rtl8367c_getAsicRldp(&pConfig->rldp_enable))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_getAsicRldpTriggerMode(&pConfig->trigger_mode))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_getAsicRldpMagicNum(&magic))!=RT_ERR_OK) + return retVal; + memcpy(&pConfig->magic, &magic, sizeof(ether_addr_t)); + + if ((retVal = rtl8367c_getAsicRldpCompareRandomNumber(&pConfig->compare_type))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_getAsicRldpCompareRandomNumber(&pConfig->compare_type))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_getAsicRldpCheckingStatePara(&pConfig->num_check, &pConfig->interval_check))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_getAsicRldpLoopStatePara(&pConfig->num_loop, &pConfig->interval_loop))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8367c_rldp_portConfig_set + * Description: + * Set per port RLDP module configuration + * Input: + * port - port number to be configured + * pPortConfig - per port configuration structure of RLDP + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT + * RT_ERR_NULL_POINTER + * Note: + * None + */ +rtk_api_ret_t dal_rtl8367c_rldp_portConfig_set(rtk_port_t port, rtk_rldp_portConfig_t *pPortConfig) +{ + rtk_api_ret_t retVal; + rtk_uint32 pmsk; + rtk_uint32 phyPort; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if (pPortConfig->tx_enable>= RTK_ENABLE_END) + return RT_ERR_INPUT; + + phyPort = rtk_switch_port_L2P_get(port); + if (phyPort == UNDEFINE_PHY_PORT) + return RT_ERR_PORT_ID; + + if ((retVal = rtl8367c_getAsicRldpTxPortmask(&pmsk))!=RT_ERR_OK) + return retVal; + + if (pPortConfig->tx_enable) + { + pmsk |=(1<tx_enable = ENABLED; + } + else + { + pPortConfig->tx_enable = DISABLED; + } + + return RT_ERR_OK; +} + + + +/* Function Name: + * dal_rtl8367c_rldp_status_get + * Description: + * Get RLDP module status + * Input: + * None + * Output: + * pStatus - status structure of RLDP + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NULL_POINTER + * Note: + * None + */ +rtk_api_ret_t dal_rtl8367c_rldp_status_get(rtk_rldp_status_t *pStatus) +{ + rtk_api_ret_t retVal; + ether_addr_t seed; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if ((retVal = rtl8367c_getAsicRldpRandomNumber(&seed))!=RT_ERR_OK) + return retVal; + memcpy(&pStatus->id, &seed, sizeof(ether_addr_t)); + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_rldp_portStatus_get + * Description: + * Get RLDP module status + * Input: + * port - port number to be get + * Output: + * pPortStatus - per port status structure of RLDP + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT + * RT_ERR_NULL_POINTER + * Note: + * None + */ +rtk_api_ret_t dal_rtl8367c_rldp_portStatus_get(rtk_port_t port, rtk_rldp_portStatus_t *pPortStatus) +{ + rtk_api_ret_t retVal; + rtk_uint32 pmsk; + rtk_portmask_t logicalPmask; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if ((retVal = rtl8367c_getAsicRldpLoopedPortmask(&pmsk))!=RT_ERR_OK) + return retVal; + if ((retVal = rtk_switch_portmask_P2L_get(pmsk, &logicalPmask)) != RT_ERR_OK) + return retVal; + + if (logicalPmask.bits[0] & (1<loop_status = RTK_RLDP_LOOPSTS_LOOPING; + } + else + { + pPortStatus->loop_status = RTK_RLDP_LOOPSTS_NONE; + } + + if ((retVal = rtl8367c_getAsicRldpEnterLoopedPortmask(&pmsk))!=RT_ERR_OK) + return retVal; + if ((retVal = rtk_switch_portmask_P2L_get(pmsk, &logicalPmask)) != RT_ERR_OK) + return retVal; + + if (logicalPmask.bits[0] & (1<loop_enter = RTK_RLDP_LOOPSTS_LOOPING; + } + else + { + pPortStatus->loop_enter = RTK_RLDP_LOOPSTS_NONE; + } + + if ((retVal = rtl8367c_getAsicRldpLeaveLoopedPortmask(&pmsk))!=RT_ERR_OK) + return retVal; + if ((retVal = rtk_switch_portmask_P2L_get(pmsk, &logicalPmask)) != RT_ERR_OK) + return retVal; + + if (logicalPmask.bits[0] & (1<loop_leave = RTK_RLDP_LOOPSTS_LOOPING; + } + else + { + pPortStatus->loop_leave = RTK_RLDP_LOOPSTS_NONE; + } + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8367c_rldp_portStatus_clear + * Description: + * Clear RLDP module status + * Input: + * port - port number to be clear + * pPortStatus - per port status structure of RLDP + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT + * RT_ERR_NULL_POINTER + * Note: + * Clear operation effect loop_enter and loop_leave only, other field in + * the structure are don't care + */ +rtk_api_ret_t dal_rtl8367c_rldp_portStatus_set(rtk_port_t port, rtk_rldp_portStatus_t *pPortStatus) +{ + rtk_api_ret_t retVal; + rtk_uint32 pmsk; + rtk_uint32 phyPort; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + phyPort = rtk_switch_port_L2P_get(port); + if (phyPort == UNDEFINE_PHY_PORT) + return RT_ERR_PORT_ID; + + pmsk = (pPortStatus->loop_enter) << phyPort; + if ((retVal = rtl8367c_setAsicRldpEnterLoopedPortmask(pmsk))!=RT_ERR_OK) + return retVal; + + pmsk = (pPortStatus->loop_leave) << phyPort; + if ((retVal = rtl8367c_setAsicRldpLeaveLoopedPortmask(pmsk))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8367c_rldp_portLoopPair_get + * Description: + * Get RLDP port loop pairs + * Input: + * port - port number to be get + * Output: + * pPortmask - per port related loop ports + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT + * RT_ERR_NULL_POINTER + * Note: + * None + */ +rtk_api_ret_t dal_rtl8367c_rldp_portLoopPair_get(rtk_port_t port, rtk_portmask_t *pPortmask) +{ + rtk_api_ret_t retVal; + rtk_uint32 pmsk; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if ((retVal = rtl8367c_getAsicRldpLoopedPortPair(rtk_switch_port_L2P_get(port), &pmsk))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtk_switch_portmask_P2L_get(pmsk, pPortmask)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_rldp.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_rldp.h new file mode 100644 index 00000000..3dd59672 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_rldp.h @@ -0,0 +1,194 @@ +/* + * Copyright (C) 2012 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision: $ + * $Date: $ + * + * Purpose : Declaration of RLDP and RLPP API + * + * Feature : The file have include the following module and sub-modules + * 1) RLDP and RLPP configuration and status + * + */ + + +#ifndef __DAL_RTL8367C_RLDP_H__ +#define __DAL_RTL8367C_RLDP_H__ + + +/* + * Include Files + */ + +#include + +/* + * Function Declaration + */ + +/* Module Name : RLDP */ + + +/* Function Name: + * dal_rtl8367c_rldp_config_set + * Description: + * Set RLDP module configuration + * Input: + * pConfig - configuration structure of RLDP + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT + * RT_ERR_NULL_POINTER + * Note: + * None + */ +extern rtk_api_ret_t dal_rtl8367c_rldp_config_set(rtk_rldp_config_t *pConfig); + + +/* Function Name: + * dal_rtl8367c_rldp_config_get + * Description: + * Get RLDP module configuration + * Input: + * None + * Output: + * pConfig - configuration structure of RLDP + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT + * RT_ERR_NULL_POINTER + * Note: + * None + */ +extern rtk_api_ret_t dal_rtl8367c_rldp_config_get(rtk_rldp_config_t *pConfig); + + +/* Function Name: + * dal_rtl8367c_rldp_portConfig_set + * Description: + * Set per port RLDP module configuration + * Input: + * port - port number to be configured + * pPortConfig - per port configuration structure of RLDP + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT + * RT_ERR_NULL_POINTER + * Note: + * None + */ +extern rtk_api_ret_t dal_rtl8367c_rldp_portConfig_set(rtk_port_t port, rtk_rldp_portConfig_t *pPortConfig); + + +/* Function Name: + * dal_rtl8367c_rldp_portConfig_get + * Description: + * Get per port RLDP module configuration + * Input: + * port - port number to be get + * Output: + * pPortConfig - per port configuration structure of RLDP + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT + * RT_ERR_NULL_POINTER + * Note: + * None + */ +extern rtk_api_ret_t dal_rtl8367c_rldp_portConfig_get(rtk_port_t port, rtk_rldp_portConfig_t *pPortConfig); + + +/* Function Name: + * dal_rtl8367c_rldp_status_get + * Description: + * Get RLDP module status + * Input: + * None + * Output: + * pStatus - status structure of RLDP + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NULL_POINTER + * Note: + * None + */ +extern rtk_api_ret_t dal_rtl8367c_rldp_status_get(rtk_rldp_status_t *pStatus); + + +/* Function Name: + * dal_rtl8367c_rldp_portStatus_get + * Description: + * Get RLDP module status + * Input: + * port - port number to be get + * Output: + * pPortStatus - per port status structure of RLDP + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT + * RT_ERR_NULL_POINTER + * Note: + * None + */ +extern rtk_api_ret_t dal_rtl8367c_rldp_portStatus_get(rtk_port_t port, rtk_rldp_portStatus_t *pPortStatus); + + +/* Function Name: + * dal_rtl8367c_rldp_portStatus_clear + * Description: + * Clear RLDP module status + * Input: + * port - port number to be clear + * pPortStatus - per port status structure of RLDP + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT + * RT_ERR_NULL_POINTER + * Note: + * Clear operation effect loop_enter and loop_leave only, other field in + * the structure are don't care + */ +extern rtk_api_ret_t dal_rtl8367c_rldp_portStatus_set(rtk_port_t port, rtk_rldp_portStatus_t *pPortStatus); + + +/* Function Name: + * dal_rtl8367c_rldp_portLoopPair_get + * Description: + * Get RLDP port loop pairs + * Input: + * port - port number to be get + * Output: + * pPortmask - per port related loop ports + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT + * RT_ERR_NULL_POINTER + * Note: + * None + */ +extern rtk_api_ret_t dal_rtl8367c_rldp_portLoopPair_get(rtk_port_t port, rtk_portmask_t *pPortmask); + +#endif /* __DAL_RTL8367C_RLDP_H__ */ + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_stat.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_stat.c new file mode 100644 index 00000000..c4ddf86f --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_stat.c @@ -0,0 +1,633 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8367C + * Feature : Here is a list of all functions and variables in MIB module. + * + */ + +#include +#include +#include + +#include + +#include +#include + +#define MIB_NOT_SUPPORT (0xFFFF) +static rtk_api_ret_t _get_asic_mib_idx(rtk_stat_port_type_t cnt_idx, RTL8367C_MIBCOUNTER *pMib_idx) +{ + RTL8367C_MIBCOUNTER mib_asic_idx[STAT_PORT_CNTR_END]= + { + ifInOctets, /* STAT_IfInOctets */ + dot3StatsFCSErrors, /* STAT_Dot3StatsFCSErrors */ + dot3StatsSymbolErrors, /* STAT_Dot3StatsSymbolErrors */ + dot3InPauseFrames, /* STAT_Dot3InPauseFrames */ + dot3ControlInUnknownOpcodes, /* STAT_Dot3ControlInUnknownOpcodes */ + etherStatsFragments, /* STAT_EtherStatsFragments */ + etherStatsJabbers, /* STAT_EtherStatsJabbers */ + ifInUcastPkts, /* STAT_IfInUcastPkts */ + etherStatsDropEvents, /* STAT_EtherStatsDropEvents */ + etherStatsOctets, /* STAT_EtherStatsOctets */ + etherStatsUnderSizePkts, /* STAT_EtherStatsUnderSizePkts */ + etherOversizeStats, /* STAT_EtherOversizeStats */ + etherStatsPkts64Octets, /* STAT_EtherStatsPkts64Octets */ + etherStatsPkts65to127Octets, /* STAT_EtherStatsPkts65to127Octets */ + etherStatsPkts128to255Octets, /* STAT_EtherStatsPkts128to255Octets */ + etherStatsPkts256to511Octets, /* STAT_EtherStatsPkts256to511Octets */ + etherStatsPkts512to1023Octets, /* STAT_EtherStatsPkts512to1023Octets */ + etherStatsPkts1024to1518Octets, /* STAT_EtherStatsPkts1024to1518Octets */ + ifInMulticastPkts, /* STAT_EtherStatsMulticastPkts */ + ifInBroadcastPkts, /* STAT_EtherStatsBroadcastPkts */ + ifOutOctets, /* STAT_IfOutOctets */ + dot3StatsSingleCollisionFrames, /* STAT_Dot3StatsSingleCollisionFrames */ + dot3StatMultipleCollisionFrames,/* STAT_Dot3StatsMultipleCollisionFrames */ + dot3sDeferredTransmissions, /* STAT_Dot3StatsDeferredTransmissions */ + dot3StatsLateCollisions, /* STAT_Dot3StatsLateCollisions */ + etherStatsCollisions, /* STAT_EtherStatsCollisions */ + dot3StatsExcessiveCollisions, /* STAT_Dot3StatsExcessiveCollisions */ + dot3OutPauseFrames, /* STAT_Dot3OutPauseFrames */ + MIB_NOT_SUPPORT, /* STAT_Dot1dBasePortDelayExceededDiscards */ + dot1dTpPortInDiscards, /* STAT_Dot1dTpPortInDiscards */ + ifOutUcastPkts, /* STAT_IfOutUcastPkts */ + ifOutMulticastPkts, /* STAT_IfOutMulticastPkts */ + ifOutBroadcastPkts, /* STAT_IfOutBroadcastPkts */ + outOampduPkts, /* STAT_OutOampduPkts */ + inOampduPkts, /* STAT_InOampduPkts */ + MIB_NOT_SUPPORT, /* STAT_PktgenPkts */ + inMldChecksumError, /* STAT_InMldChecksumError */ + inIgmpChecksumError, /* STAT_InIgmpChecksumError */ + inMldSpecificQuery, /* STAT_InMldSpecificQuery */ + inMldGeneralQuery, /* STAT_InMldGeneralQuery */ + inIgmpSpecificQuery, /* STAT_InIgmpSpecificQuery */ + inIgmpGeneralQuery, /* STAT_InIgmpGeneralQuery */ + inMldLeaves, /* STAT_InMldLeaves */ + inIgmpLeaves, /* STAT_InIgmpInterfaceLeaves */ + inIgmpJoinsSuccess, /* STAT_InIgmpJoinsSuccess */ + inIgmpJoinsFail, /* STAT_InIgmpJoinsFail */ + inMldJoinsSuccess, /* STAT_InMldJoinsSuccess */ + inMldJoinsFail, /* STAT_InMldJoinsFail */ + inReportSuppressionDrop, /* STAT_InReportSuppressionDrop */ + inLeaveSuppressionDrop, /* STAT_InLeaveSuppressionDrop */ + outIgmpReports, /* STAT_OutIgmpReports */ + outIgmpLeaves, /* STAT_OutIgmpLeaves */ + outIgmpGeneralQuery, /* STAT_OutIgmpGeneralQuery */ + outIgmpSpecificQuery, /* STAT_OutIgmpSpecificQuery */ + outMldReports, /* STAT_OutMldReports */ + outMldLeaves, /* STAT_OutMldLeaves */ + outMldGeneralQuery, /* STAT_OutMldGeneralQuery */ + outMldSpecificQuery, /* STAT_OutMldSpecificQuery */ + inKnownMulticastPkts, /* STAT_InKnownMulticastPkts */ + ifInMulticastPkts, /* STAT_IfInMulticastPkts */ + ifInBroadcastPkts, /* STAT_IfInBroadcastPkts */ + ifOutDiscards /* STAT_IfOutDiscards */ + }; + + if(cnt_idx >= STAT_PORT_CNTR_END) + return RT_ERR_STAT_INVALID_PORT_CNTR; + + if(mib_asic_idx[cnt_idx] == MIB_NOT_SUPPORT) + return RT_ERR_CHIP_NOT_SUPPORTED; + + *pMib_idx = mib_asic_idx[cnt_idx]; + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_stat_global_reset + * Description: + * Reset global MIB counter. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * Reset MIB counter of ports. API will use global reset while port mask is all-ports. + */ +rtk_api_ret_t dal_rtl8367c_stat_global_reset(void) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if ((retVal = rtl8367c_setAsicMIBsCounterReset(TRUE,FALSE, 0)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_stat_port_reset + * Description: + * Reset per port MIB counter by port. + * Input: + * port - port id. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * + */ +rtk_api_ret_t dal_rtl8367c_stat_port_reset(rtk_port_t port) +{ + rtk_api_ret_t retVal; + rtk_uint32 phyPort; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check port valid */ + RTK_CHK_PORT_VALID(port); + + phyPort = rtk_switch_port_L2P_get(port); + if (phyPort == UNDEFINE_PHY_PORT) + return RT_ERR_PORT_ID; + + if ((retVal = rtl8367c_setAsicMIBsCounterReset(FALSE,FALSE,1 << phyPort)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_stat_queueManage_reset + * Description: + * Reset queue manage MIB counter. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * + */ +rtk_api_ret_t dal_rtl8367c_stat_queueManage_reset(void) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if ((retVal = rtl8367c_setAsicMIBsCounterReset(FALSE,TRUE,0)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_stat_global_get + * Description: + * Get global MIB counter + * Input: + * cntr_idx - global counter index. + * Output: + * pCntr - global counter value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * Get global MIB counter by index definition. + */ +rtk_api_ret_t dal_rtl8367c_stat_global_get(rtk_stat_global_type_t cntr_idx, rtk_stat_counter_t *pCntr) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pCntr) + return RT_ERR_NULL_POINTER; + + if (cntr_idx!=DOT1D_TP_LEARNED_ENTRY_DISCARDS_INDEX) + return RT_ERR_STAT_INVALID_GLOBAL_CNTR; + + if ((retVal = rtl8367c_getAsicMIBsCounter(0, dot1dTpLearnedEntryDiscards, pCntr)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_stat_global_getAll + * Description: + * Get all global MIB counter + * Input: + * None + * Output: + * pGlobal_cntrs - global counter structure. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * Get all global MIB counter by index definition. + */ +rtk_api_ret_t dal_rtl8367c_stat_global_getAll(rtk_stat_global_cntr_t *pGlobal_cntrs) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pGlobal_cntrs) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicMIBsCounter(0, (RTL8367C_MIBCOUNTER)DOT1D_TP_LEARNED_ENTRY_DISCARDS_INDEX, &pGlobal_cntrs->dot1dTpLearnedEntryDiscards)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_stat_port_get + * Description: + * Get per port MIB counter by index + * Input: + * port - port id. + * cntr_idx - port counter index. + * Output: + * pCntr - MIB retrived counter. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * Get per port MIB counter by index definition. + */ +rtk_api_ret_t dal_rtl8367c_stat_port_get(rtk_port_t port, rtk_stat_port_type_t cntr_idx, rtk_stat_counter_t *pCntr) +{ + rtk_api_ret_t retVal; + RTL8367C_MIBCOUNTER mib_idx; + rtk_stat_counter_t second_cnt; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pCntr) + return RT_ERR_NULL_POINTER; + + /* Check port valid */ + RTK_CHK_PORT_VALID(port); + + if (cntr_idx>=STAT_PORT_CNTR_END) + return RT_ERR_STAT_INVALID_PORT_CNTR; + + if((retVal = _get_asic_mib_idx(cntr_idx, &mib_idx)) != RT_ERR_OK) + return retVal; + + if(mib_idx == MIB_NOT_SUPPORT) + return RT_ERR_CHIP_NOT_SUPPORTED; + + if ((retVal = rtl8367c_getAsicMIBsCounter(rtk_switch_port_L2P_get(port), mib_idx, pCntr)) != RT_ERR_OK) + return retVal; + + if(cntr_idx == STAT_EtherStatsMulticastPkts) + { + if((retVal = _get_asic_mib_idx(STAT_IfOutMulticastPkts, &mib_idx)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_getAsicMIBsCounter(rtk_switch_port_L2P_get(port), mib_idx, &second_cnt)) != RT_ERR_OK) + return retVal; + + *pCntr += second_cnt; + } + + if(cntr_idx == STAT_EtherStatsBroadcastPkts) + { + if((retVal = _get_asic_mib_idx(STAT_IfOutBroadcastPkts, &mib_idx)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_getAsicMIBsCounter(rtk_switch_port_L2P_get(port), mib_idx, &second_cnt)) != RT_ERR_OK) + return retVal; + + *pCntr += second_cnt; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_stat_port_getAll + * Description: + * Get all counters of one specified port in the specified device. + * Input: + * port - port id. + * Output: + * pPort_cntrs - buffer pointer of counter value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * Get all MIB counters of one port. + */ +rtk_api_ret_t dal_rtl8367c_stat_port_getAll(rtk_port_t port, rtk_stat_port_cntr_t *pPort_cntrs) +{ + rtk_api_ret_t retVal; + rtk_uint32 mibIndex; + rtk_uint64 mibCounter; + rtk_uint32 *accessPtr; + /* address offset to MIBs counter */ + CONST_T rtk_uint16 mibLength[STAT_PORT_CNTR_END]= { + 2,1,1,1,1,1,1,1,1, + 2,1,1,1,1,1,1,1,1,1,1, + 2,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, + 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1}; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pPort_cntrs) + return RT_ERR_NULL_POINTER; + + /* Check port valid */ + RTK_CHK_PORT_VALID(port); + + accessPtr = (rtk_uint32*)pPort_cntrs; + for (mibIndex=0;mibIndex RTL8367C_MIB_MAX_LOG_CNT_IDX) + return RT_ERR_OUT_OF_RANGE; + + if((idx % 2) == 1) + return RT_ERR_INPUT; + + if(mode >= LOGGING_MODE_END) + return RT_ERR_OUT_OF_RANGE; + + if(type >= LOGGING_TYPE_END) + return RT_ERR_OUT_OF_RANGE; + + if((retVal = rtl8367c_setAsicMIBsLoggingType((idx / 2), (rtk_uint32)type)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicMIBsLoggingMode((idx / 2), (rtk_uint32)mode)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_stat_logging_counterCfg_get + * Description: + * Get the type and mode of Logging Counter + * Input: + * idx - The index of Logging Counter. Should be even number only.(0,2,4,6,8.....30) + * Output: + * pMode - 32 bits or 64 bits mode + * pType - Packet counter or byte counter + * Return: + * RT_ERR_OK - OK + * RT_ERR_OUT_OF_RANGE - Out of range. + * RT_ERR_FAILED - Failed + * RT_ERR_NULL_POINTER - NULL Pointer + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * Get the type and mode of Logging Counter. + */ +rtk_api_ret_t dal_rtl8367c_stat_logging_counterCfg_get(rtk_uint32 idx, rtk_logging_counter_mode_t *pMode, rtk_logging_counter_type_t *pType) +{ + rtk_api_ret_t retVal; + rtk_uint32 type, mode; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(idx > RTL8367C_MIB_MAX_LOG_CNT_IDX) + return RT_ERR_OUT_OF_RANGE; + + if((idx % 2) == 1) + return RT_ERR_INPUT; + + if(pMode == NULL) + return RT_ERR_NULL_POINTER; + + if(pType == NULL) + return RT_ERR_NULL_POINTER; + + if((retVal = rtl8367c_getAsicMIBsLoggingType((idx / 2), &type)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_getAsicMIBsLoggingMode((idx / 2), &mode)) != RT_ERR_OK) + return retVal; + + *pMode = (rtk_logging_counter_mode_t)mode; + *pType = (rtk_logging_counter_type_t)type; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_stat_logging_counter_reset + * Description: + * Reset Logging Counter + * Input: + * idx - The index of Logging Counter. (0~31) + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_OUT_OF_RANGE - Out of range. + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * Reset Logging Counter. + */ +rtk_api_ret_t dal_rtl8367c_stat_logging_counter_reset(rtk_uint32 idx) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(idx > RTL8367C_MIB_MAX_LOG_CNT_IDX) + return RT_ERR_OUT_OF_RANGE; + + if((retVal = rtl8367c_setAsicMIBsResetLoggingCounter(idx)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_stat_logging_counter_get + * Description: + * Get Logging Counter + * Input: + * idx - The index of Logging Counter. (0~31) + * Output: + * pCnt - Logging counter value + * Return: + * RT_ERR_OK - OK + * RT_ERR_OUT_OF_RANGE - Out of range. + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * Get Logging Counter. + */ +rtk_api_ret_t dal_rtl8367c_stat_logging_counter_get(rtk_uint32 idx, rtk_uint32 *pCnt) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pCnt) + return RT_ERR_NULL_POINTER; + + if(idx > RTL8367C_MIB_MAX_LOG_CNT_IDX) + return RT_ERR_OUT_OF_RANGE; + + if((retVal = rtl8367c_getAsicMIBsLogCounter(idx, pCnt)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_stat_lengthMode_set + * Description: + * Set Legnth mode. + * Input: + * txMode - The length counting mode + * rxMode - The length counting mode + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_INPUT - Out of range. + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * + */ +rtk_api_ret_t dal_rtl8367c_stat_lengthMode_set(rtk_stat_lengthMode_t txMode, rtk_stat_lengthMode_t rxMode) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(txMode >= LENGTH_MODE_END) + return RT_ERR_INPUT; + + if(rxMode >= LENGTH_MODE_END) + return RT_ERR_INPUT; + + if((retVal = rtl8367c_setAsicMIBsLength((rtk_uint32)txMode, (rtk_uint32)rxMode)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_stat_lengthMode_get + * Description: + * Get Legnth mode. + * Input: + * None. + * Output: + * pTxMode - The length counting mode + * pRxMode - The length counting mode + * Return: + * RT_ERR_OK - OK + * RT_ERR_INPUT - Out of range. + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +rtk_api_ret_t dal_rtl8367c_stat_lengthMode_get(rtk_stat_lengthMode_t *pTxMode, rtk_stat_lengthMode_t *pRxMode) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pTxMode) + return RT_ERR_NULL_POINTER; + + if(NULL == pRxMode) + return RT_ERR_NULL_POINTER; + + if((retVal = rtl8367c_getAsicMIBsLength((rtk_uint32 *)pTxMode, (rtk_uint32 *)pRxMode)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_stat.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_stat.h new file mode 100644 index 00000000..0295f184 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_stat.h @@ -0,0 +1,262 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8367/RTL8367C switch high-level API + * + * Feature : The file includes MIB module high-layer API defination + * + */ + +#ifndef __DAL_RTL8367C_STAT_H__ +#define __DAL_RTL8367C_STAT_H__ + +#include + +/* Function Name: + * dal_rtl8367c_stat_global_reset + * Description: + * Reset global MIB counter. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * Reset MIB counter of ports. API will use global reset while port mask is all-ports. + */ +extern rtk_api_ret_t dal_rtl8367c_stat_global_reset(void); + +/* Function Name: + * dal_rtl8367c_stat_port_reset + * Description: + * Reset per port MIB counter by port. + * Input: + * port - port id. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367c_stat_port_reset(rtk_port_t port); + +/* Function Name: + * dal_rtl8367c_stat_queueManage_reset + * Description: + * Reset queue manage MIB counter. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367c_stat_queueManage_reset(void); + +/* Function Name: + * dal_rtl8367c_stat_global_get + * Description: + * Get global MIB counter + * Input: + * cntr_idx - global counter index. + * Output: + * pCntr - global counter value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * Get global MIB counter by index definition. + */ +extern rtk_api_ret_t dal_rtl8367c_stat_global_get(rtk_stat_global_type_t cntr_idx, rtk_stat_counter_t *pCntr); + +/* Function Name: + * dal_rtl8367c_stat_global_getAll + * Description: + * Get all global MIB counter + * Input: + * None + * Output: + * pGlobal_cntrs - global counter structure. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * Get all global MIB counter by index definition. + */ +extern rtk_api_ret_t dal_rtl8367c_stat_global_getAll(rtk_stat_global_cntr_t *pGlobal_cntrs); + +/* Function Name: + * dal_rtl8367c_stat_port_get + * Description: + * Get per port MIB counter by index + * Input: + * port - port id. + * cntr_idx - port counter index. + * Output: + * pCntr - MIB retrived counter. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * Get per port MIB counter by index definition. + */ +extern rtk_api_ret_t dal_rtl8367c_stat_port_get(rtk_port_t port, rtk_stat_port_type_t cntr_idx, rtk_stat_counter_t *pCntr); + +/* Function Name: + * dal_rtl8367c_stat_port_getAll + * Description: + * Get all counters of one specified port in the specified device. + * Input: + * port - port id. + * Output: + * pPort_cntrs - buffer pointer of counter value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * Get all MIB counters of one port. + */ +extern rtk_api_ret_t dal_rtl8367c_stat_port_getAll(rtk_port_t port, rtk_stat_port_cntr_t *pPort_cntrs); + +/* Function Name: + * dal_rtl8367c_stat_logging_counterCfg_set + * Description: + * Set the type and mode of Logging Counter + * Input: + * idx - The index of Logging Counter. Should be even number only.(0,2,4,6,8.....30) + * mode - 32 bits or 64 bits mode + * type - Packet counter or byte counter + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_OUT_OF_RANGE - Out of range. + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * Set the type and mode of Logging Counter. + */ +extern rtk_api_ret_t dal_rtl8367c_stat_logging_counterCfg_set(rtk_uint32 idx, rtk_logging_counter_mode_t mode, rtk_logging_counter_type_t type); + +/* Function Name: + * dal_rtl8367c_stat_logging_counterCfg_get + * Description: + * Get the type and mode of Logging Counter + * Input: + * idx - The index of Logging Counter. Should be even number only.(0,2,4,6,8.....30) + * Output: + * pMode - 32 bits or 64 bits mode + * pType - Packet counter or byte counter + * Return: + * RT_ERR_OK - OK + * RT_ERR_OUT_OF_RANGE - Out of range. + * RT_ERR_FAILED - Failed + * RT_ERR_NULL_POINTER - NULL Pointer + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * Get the type and mode of Logging Counter. + */ +extern rtk_api_ret_t dal_rtl8367c_stat_logging_counterCfg_get(rtk_uint32 idx, rtk_logging_counter_mode_t *pMode, rtk_logging_counter_type_t *pType); + +/* Function Name: + * dal_rtl8367c_stat_logging_counter_reset + * Description: + * Reset Logging Counter + * Input: + * idx - The index of Logging Counter. (0~31) + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_OUT_OF_RANGE - Out of range. + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * Reset Logging Counter. + */ +extern rtk_api_ret_t dal_rtl8367c_stat_logging_counter_reset(rtk_uint32 idx); + +/* Function Name: + * dal_rtl8367c_stat_logging_counter_get + * Description: + * Get Logging Counter + * Input: + * idx - The index of Logging Counter. (0~31) + * Output: + * pCnt - Logging counter value + * Return: + * RT_ERR_OK - OK + * RT_ERR_OUT_OF_RANGE - Out of range. + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * Get Logging Counter. + */ +extern rtk_api_ret_t dal_rtl8367c_stat_logging_counter_get(rtk_uint32 idx, rtk_uint32 *pCnt); + +/* Function Name: + * dal_rtl8367c_stat_lengthMode_set + * Description: + * Set Legnth mode. + * Input: + * txMode - The length counting mode + * rxMode - The length counting mode + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_INPUT - Out of range. + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367c_stat_lengthMode_set(rtk_stat_lengthMode_t txMode, rtk_stat_lengthMode_t rxMode); + +/* Function Name: + * dal_rtl8367c_stat_lengthMode_get + * Description: + * Get Legnth mode. + * Input: + * None. + * Output: + * pTxMode - The length counting mode + * pRxMode - The length counting mode + * Return: + * RT_ERR_OK - OK + * RT_ERR_INPUT - Out of range. + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +extern rtk_api_ret_t dal_rtl8367c_stat_lengthMode_get(rtk_stat_lengthMode_t *pTxMode, rtk_stat_lengthMode_t *pRxMode); + +#endif /* __DAL_RTL8367C_STAT_H__ */ + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_storm.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_storm.c new file mode 100644 index 00000000..6bce1b07 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_storm.c @@ -0,0 +1,817 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8367C + * Feature : Here is a list of all functions and variables in Storm module. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Function Name: + * dal_rtl8367c_rate_stormControlMeterIdx_set + * Description: + * Set the storm control meter index. + * Input: + * port - port id + * storm_type - storm group type + * index - storm control meter index. + * Output: + * None. + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - Invalid port id + * RT_ERR_FILTER_METER_ID - Invalid meter + * Note: + * + */ +rtk_api_ret_t dal_rtl8367c_rate_stormControlMeterIdx_set(rtk_port_t port, rtk_rate_storm_group_t stormType, rtk_uint32 index) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if (stormType >= STORM_GROUP_END) + return RT_ERR_SFC_UNKNOWN_GROUP; + + if (index > RTK_MAX_METER_ID) + return RT_ERR_FILTER_METER_ID; + + switch (stormType) + { + case STORM_GROUP_UNKNOWN_UNICAST: + if ((retVal = rtl8367c_setAsicStormFilterUnknownUnicastMeter(rtk_switch_port_L2P_get(port), index))!=RT_ERR_OK) + return retVal; + break; + case STORM_GROUP_UNKNOWN_MULTICAST: + if ((retVal = rtl8367c_setAsicStormFilterUnknownMulticastMeter(rtk_switch_port_L2P_get(port), index))!=RT_ERR_OK) + return retVal; + break; + case STORM_GROUP_MULTICAST: + if ((retVal = rtl8367c_setAsicStormFilterMulticastMeter(rtk_switch_port_L2P_get(port), index))!=RT_ERR_OK) + return retVal; + break; + case STORM_GROUP_BROADCAST: + if ((retVal = rtl8367c_setAsicStormFilterBroadcastMeter(rtk_switch_port_L2P_get(port), index))!=RT_ERR_OK) + return retVal; + break; + default: + break; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_rate_stormControlMeterIdx_get + * Description: + * Get the storm control meter index. + * Input: + * port - port id + * storm_type - storm group type + * Output: + * pIndex - storm control meter index. + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - Invalid port id + * RT_ERR_FILTER_METER_ID - Invalid meter + * Note: + * + */ +rtk_api_ret_t dal_rtl8367c_rate_stormControlMeterIdx_get(rtk_port_t port, rtk_rate_storm_group_t stormType, rtk_uint32 *pIndex) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if (stormType >= STORM_GROUP_END) + return RT_ERR_SFC_UNKNOWN_GROUP; + + if (NULL == pIndex ) + return RT_ERR_NULL_POINTER; + + switch (stormType) + { + case STORM_GROUP_UNKNOWN_UNICAST: + if ((retVal = rtl8367c_getAsicStormFilterUnknownUnicastMeter(rtk_switch_port_L2P_get(port), pIndex))!=RT_ERR_OK) + return retVal; + break; + case STORM_GROUP_UNKNOWN_MULTICAST: + if ((retVal = rtl8367c_getAsicStormFilterUnknownMulticastMeter(rtk_switch_port_L2P_get(port), pIndex))!=RT_ERR_OK) + return retVal; + break; + case STORM_GROUP_MULTICAST: + if ((retVal = rtl8367c_getAsicStormFilterMulticastMeter(rtk_switch_port_L2P_get(port), pIndex))!=RT_ERR_OK) + return retVal; + break; + case STORM_GROUP_BROADCAST: + if ((retVal = rtl8367c_getAsicStormFilterBroadcastMeter(rtk_switch_port_L2P_get(port), pIndex))!=RT_ERR_OK) + return retVal; + break; + default: + break; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_rate_stormControlPortEnable_set + * Description: + * Set enable status of storm control on specified port. + * Input: + * port - port id + * stormType - storm group type + * enable - enable status of storm control + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +rtk_api_ret_t dal_rtl8367c_rate_stormControlPortEnable_set(rtk_port_t port, rtk_rate_storm_group_t stormType, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if (stormType >= STORM_GROUP_END) + return RT_ERR_SFC_UNKNOWN_GROUP; + + if (enable >= RTK_ENABLE_END) + return RT_ERR_ENABLE; + + switch (stormType) + { + case STORM_GROUP_UNKNOWN_UNICAST: + if ((retVal = rtl8367c_setAsicStormFilterUnknownUnicastEnable(rtk_switch_port_L2P_get(port), enable)) != RT_ERR_OK) + return retVal; + break; + case STORM_GROUP_UNKNOWN_MULTICAST: + if ((retVal = rtl8367c_setAsicStormFilterUnknownMulticastEnable(rtk_switch_port_L2P_get(port), enable)) != RT_ERR_OK) + return retVal; + break; + case STORM_GROUP_MULTICAST: + if ((retVal = rtl8367c_setAsicStormFilterMulticastEnable(rtk_switch_port_L2P_get(port), enable)) != RT_ERR_OK) + return retVal; + break; + case STORM_GROUP_BROADCAST: + if ((retVal = rtl8367c_setAsicStormFilterBroadcastEnable(rtk_switch_port_L2P_get(port), enable)) != RT_ERR_OK) + return retVal; + break; + default: + break; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_rate_stormControlPortEnable_set + * Description: + * Set enable status of storm control on specified port. + * Input: + * port - port id + * stormType - storm group type + * Output: + * pEnable - enable status of storm control + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +rtk_api_ret_t dal_rtl8367c_rate_stormControlPortEnable_get(rtk_port_t port, rtk_rate_storm_group_t stormType, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if (stormType >= STORM_GROUP_END) + return RT_ERR_SFC_UNKNOWN_GROUP; + + if (NULL == pEnable) + return RT_ERR_ENABLE; + + switch (stormType) + { + case STORM_GROUP_UNKNOWN_UNICAST: + if ((retVal = rtl8367c_getAsicStormFilterUnknownUnicastEnable(rtk_switch_port_L2P_get(port), pEnable)) != RT_ERR_OK) + return retVal; + break; + case STORM_GROUP_UNKNOWN_MULTICAST: + if ((retVal = rtl8367c_getAsicStormFilterUnknownMulticastEnable(rtk_switch_port_L2P_get(port), pEnable)) != RT_ERR_OK) + return retVal; + break; + case STORM_GROUP_MULTICAST: + if ((retVal = rtl8367c_getAsicStormFilterMulticastEnable(rtk_switch_port_L2P_get(port), pEnable)) != RT_ERR_OK) + return retVal; + break; + case STORM_GROUP_BROADCAST: + if ((retVal = rtl8367c_getAsicStormFilterBroadcastEnable(rtk_switch_port_L2P_get(port), pEnable)) != RT_ERR_OK) + return retVal; + break; + default: + break; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_storm_bypass_set + * Description: + * Set bypass storm filter control configuration. + * Input: + * type - Bypass storm filter control type. + * enable - Bypass status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_ENABLE - Invalid IFG parameter + * Note: + * + * This API can set per-port bypass stomr filter control frame type including RMA and igmp. + * The bypass frame type is as following: + * - BYPASS_BRG_GROUP, + * - BYPASS_FD_PAUSE, + * - BYPASS_SP_MCAST, + * - BYPASS_1X_PAE, + * - BYPASS_UNDEF_BRG_04, + * - BYPASS_UNDEF_BRG_05, + * - BYPASS_UNDEF_BRG_06, + * - BYPASS_UNDEF_BRG_07, + * - BYPASS_PROVIDER_BRIDGE_GROUP_ADDRESS, + * - BYPASS_UNDEF_BRG_09, + * - BYPASS_UNDEF_BRG_0A, + * - BYPASS_UNDEF_BRG_0B, + * - BYPASS_UNDEF_BRG_0C, + * - BYPASS_PROVIDER_BRIDGE_GVRP_ADDRESS, + * - BYPASS_8021AB, + * - BYPASS_UNDEF_BRG_0F, + * - BYPASS_BRG_MNGEMENT, + * - BYPASS_UNDEFINED_11, + * - BYPASS_UNDEFINED_12, + * - BYPASS_UNDEFINED_13, + * - BYPASS_UNDEFINED_14, + * - BYPASS_UNDEFINED_15, + * - BYPASS_UNDEFINED_16, + * - BYPASS_UNDEFINED_17, + * - BYPASS_UNDEFINED_18, + * - BYPASS_UNDEFINED_19, + * - BYPASS_UNDEFINED_1A, + * - BYPASS_UNDEFINED_1B, + * - BYPASS_UNDEFINED_1C, + * - BYPASS_UNDEFINED_1D, + * - BYPASS_UNDEFINED_1E, + * - BYPASS_UNDEFINED_1F, + * - BYPASS_GMRP, + * - BYPASS_GVRP, + * - BYPASS_UNDEF_GARP_22, + * - BYPASS_UNDEF_GARP_23, + * - BYPASS_UNDEF_GARP_24, + * - BYPASS_UNDEF_GARP_25, + * - BYPASS_UNDEF_GARP_26, + * - BYPASS_UNDEF_GARP_27, + * - BYPASS_UNDEF_GARP_28, + * - BYPASS_UNDEF_GARP_29, + * - BYPASS_UNDEF_GARP_2A, + * - BYPASS_UNDEF_GARP_2B, + * - BYPASS_UNDEF_GARP_2C, + * - BYPASS_UNDEF_GARP_2D, + * - BYPASS_UNDEF_GARP_2E, + * - BYPASS_UNDEF_GARP_2F, + * - BYPASS_IGMP. + * - BYPASS_CDP. + * - BYPASS_CSSTP. + * - BYPASS_LLDP. + */ +rtk_api_ret_t dal_rtl8367c_storm_bypass_set(rtk_storm_bypass_t type, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + rtl8367c_rma_t rmacfg; + rtk_uint32 tmp; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (type >= BYPASS_END) + return RT_ERR_INPUT; + + if (enable >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if (type >= 0 && type <= BYPASS_UNDEF_GARP_2F) + { + if ((retVal = rtl8367c_getAsicRma(type, &rmacfg)) != RT_ERR_OK) + return retVal; + + rmacfg.discard_storm_filter = enable; + + if ((retVal = rtl8367c_setAsicRma(type, &rmacfg)) != RT_ERR_OK) + return retVal; + } + else if(type == BYPASS_IGMP) + { + if ((retVal = rtl8367c_setAsicIGMPBypassStormCTRL(enable)) != RT_ERR_OK) + return retVal; + } + else if (type == BYPASS_CDP) + { + if ((retVal = rtl8367c_getAsicRmaCdp(&rmacfg)) != RT_ERR_OK) + return retVal; + + rmacfg.discard_storm_filter = enable; + + if ((retVal = rtl8367c_setAsicRmaCdp(&rmacfg)) != RT_ERR_OK) + return retVal; + } + else if (type == BYPASS_CSSTP) + { + if ((retVal = rtl8367c_getAsicRmaCsstp(&rmacfg)) != RT_ERR_OK) + return retVal; + + rmacfg.discard_storm_filter = enable; + + if ((retVal = rtl8367c_setAsicRmaCsstp(&rmacfg)) != RT_ERR_OK) + return retVal; + } + else if (type == BYPASS_LLDP) + { + if ((retVal = rtl8367c_getAsicRmaLldp(&tmp, &rmacfg)) != RT_ERR_OK) + return retVal; + + rmacfg.discard_storm_filter = enable; + + if ((retVal = rtl8367c_setAsicRmaLldp(tmp, &rmacfg)) != RT_ERR_OK) + return retVal; + } + else + return RT_ERR_INPUT; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_storm_bypass_get + * Description: + * Get bypass storm filter control configuration. + * Input: + * type - Bypass storm filter control type. + * Output: + * pEnable - Bypass status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can get per-port bypass stomr filter control frame type including RMA and igmp. + * The bypass frame type is as following: + * - BYPASS_BRG_GROUP, + * - BYPASS_FD_PAUSE, + * - BYPASS_SP_MCAST, + * - BYPASS_1X_PAE, + * - BYPASS_UNDEF_BRG_04, + * - BYPASS_UNDEF_BRG_05, + * - BYPASS_UNDEF_BRG_06, + * - BYPASS_UNDEF_BRG_07, + * - BYPASS_PROVIDER_BRIDGE_GROUP_ADDRESS, + * - BYPASS_UNDEF_BRG_09, + * - BYPASS_UNDEF_BRG_0A, + * - BYPASS_UNDEF_BRG_0B, + * - BYPASS_UNDEF_BRG_0C, + * - BYPASS_PROVIDER_BRIDGE_GVRP_ADDRESS, + * - BYPASS_8021AB, + * - BYPASS_UNDEF_BRG_0F, + * - BYPASS_BRG_MNGEMENT, + * - BYPASS_UNDEFINED_11, + * - BYPASS_UNDEFINED_12, + * - BYPASS_UNDEFINED_13, + * - BYPASS_UNDEFINED_14, + * - BYPASS_UNDEFINED_15, + * - BYPASS_UNDEFINED_16, + * - BYPASS_UNDEFINED_17, + * - BYPASS_UNDEFINED_18, + * - BYPASS_UNDEFINED_19, + * - BYPASS_UNDEFINED_1A, + * - BYPASS_UNDEFINED_1B, + * - BYPASS_UNDEFINED_1C, + * - BYPASS_UNDEFINED_1D, + * - BYPASS_UNDEFINED_1E, + * - BYPASS_UNDEFINED_1F, + * - BYPASS_GMRP, + * - BYPASS_GVRP, + * - BYPASS_UNDEF_GARP_22, + * - BYPASS_UNDEF_GARP_23, + * - BYPASS_UNDEF_GARP_24, + * - BYPASS_UNDEF_GARP_25, + * - BYPASS_UNDEF_GARP_26, + * - BYPASS_UNDEF_GARP_27, + * - BYPASS_UNDEF_GARP_28, + * - BYPASS_UNDEF_GARP_29, + * - BYPASS_UNDEF_GARP_2A, + * - BYPASS_UNDEF_GARP_2B, + * - BYPASS_UNDEF_GARP_2C, + * - BYPASS_UNDEF_GARP_2D, + * - BYPASS_UNDEF_GARP_2E, + * - BYPASS_UNDEF_GARP_2F, + * - BYPASS_IGMP. + * - BYPASS_CDP. + * - BYPASS_CSSTP. + * - BYPASS_LLDP. + */ +rtk_api_ret_t dal_rtl8367c_storm_bypass_get(rtk_storm_bypass_t type, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + rtl8367c_rma_t rmacfg; + rtk_uint32 tmp; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (type >= BYPASS_END) + return RT_ERR_INPUT; + + if(NULL == pEnable) + return RT_ERR_NULL_POINTER; + + if (type >= 0 && type <= BYPASS_UNDEF_GARP_2F) + { + if ((retVal = rtl8367c_getAsicRma(type, &rmacfg)) != RT_ERR_OK) + return retVal; + + *pEnable = rmacfg.discard_storm_filter; + } + else if(type == BYPASS_IGMP) + { + if ((retVal = rtl8367c_getAsicIGMPBypassStormCTRL(pEnable)) != RT_ERR_OK) + return retVal; + } + else if (type == BYPASS_CDP) + { + if ((retVal = rtl8367c_getAsicRmaCdp(&rmacfg)) != RT_ERR_OK) + return retVal; + + *pEnable = rmacfg.discard_storm_filter; + } + else if (type == BYPASS_CSSTP) + { + if ((retVal = rtl8367c_getAsicRmaCsstp(&rmacfg)) != RT_ERR_OK) + return retVal; + + *pEnable = rmacfg.discard_storm_filter; + } + else if (type == BYPASS_LLDP) + { + if ((retVal = rtl8367c_getAsicRmaLldp(&tmp,&rmacfg)) != RT_ERR_OK) + return retVal; + + *pEnable = rmacfg.discard_storm_filter; + } + else + return RT_ERR_INPUT; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_rate_stormControlExtPortmask_set + * Description: + * Set externsion storm control port mask + * Input: + * pPortmask - port mask + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +rtk_api_ret_t dal_rtl8367c_rate_stormControlExtPortmask_set(rtk_portmask_t *pPortmask) +{ + rtk_api_ret_t retVal; + rtk_uint32 pmask; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pPortmask) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtk_switch_portmask_L2P_get(pPortmask, &pmask)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicStormFilterExtEnablePortMask(pmask)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_rate_stormControlExtPortmask_get + * Description: + * Set externsion storm control port mask + * Input: + * None + * Output: + * pPortmask - port mask + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +rtk_api_ret_t dal_rtl8367c_rate_stormControlExtPortmask_get(rtk_portmask_t *pPortmask) +{ + rtk_api_ret_t retVal; + rtk_uint32 pmask; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pPortmask) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicStormFilterExtEnablePortMask(&pmask)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtk_switch_portmask_P2L_get(pmask, pPortmask)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_rate_stormControlExtEnable_set + * Description: + * Set externsion storm control state + * Input: + * stormType - storm group type + * enable - externsion storm control state + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +rtk_api_ret_t dal_rtl8367c_rate_stormControlExtEnable_set(rtk_rate_storm_group_t stormType, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (stormType >= STORM_GROUP_END) + return RT_ERR_SFC_UNKNOWN_GROUP; + + if (enable >= RTK_ENABLE_END) + return RT_ERR_ENABLE; + + switch (stormType) + { + case STORM_GROUP_UNKNOWN_UNICAST: + if ((retVal = rtl8367c_setAsicStormFilterExtUnknownUnicastEnable(enable)) != RT_ERR_OK) + return retVal; + break; + case STORM_GROUP_UNKNOWN_MULTICAST: + if ((retVal = rtl8367c_setAsicStormFilterExtUnknownMulticastEnable(enable)) != RT_ERR_OK) + return retVal; + break; + case STORM_GROUP_MULTICAST: + if ((retVal = rtl8367c_setAsicStormFilterExtMulticastEnable(enable)) != RT_ERR_OK) + return retVal; + break; + case STORM_GROUP_BROADCAST: + if ((retVal = rtl8367c_setAsicStormFilterExtBroadcastEnable(enable)) != RT_ERR_OK) + return retVal; + break; + default: + break; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_rate_stormControlExtEnable_get + * Description: + * Get externsion storm control state + * Input: + * stormType - storm group type + * Output: + * pEnable - externsion storm control state + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +rtk_api_ret_t dal_rtl8367c_rate_stormControlExtEnable_get(rtk_rate_storm_group_t stormType, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (stormType >= STORM_GROUP_END) + return RT_ERR_SFC_UNKNOWN_GROUP; + + if (NULL == pEnable) + return RT_ERR_NULL_POINTER; + + switch (stormType) + { + case STORM_GROUP_UNKNOWN_UNICAST: + if ((retVal = rtl8367c_getAsicStormFilterExtUnknownUnicastEnable((rtk_uint32 *)pEnable)) != RT_ERR_OK) + return retVal; + break; + case STORM_GROUP_UNKNOWN_MULTICAST: + if ((retVal = rtl8367c_getAsicStormFilterExtUnknownMulticastEnable((rtk_uint32 *)pEnable)) != RT_ERR_OK) + return retVal; + break; + case STORM_GROUP_MULTICAST: + if ((retVal = rtl8367c_getAsicStormFilterExtMulticastEnable((rtk_uint32 *)pEnable)) != RT_ERR_OK) + return retVal; + break; + case STORM_GROUP_BROADCAST: + if ((retVal = rtl8367c_getAsicStormFilterExtBroadcastEnable((rtk_uint32 *)pEnable)) != RT_ERR_OK) + return retVal; + break; + default: + break; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_rate_stormControlExtMeterIdx_set + * Description: + * Set externsion storm control meter index + * Input: + * stormType - storm group type + * index - externsion storm control state + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +rtk_api_ret_t dal_rtl8367c_rate_stormControlExtMeterIdx_set(rtk_rate_storm_group_t stormType, rtk_uint32 index) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (stormType >= STORM_GROUP_END) + return RT_ERR_SFC_UNKNOWN_GROUP; + + if (index > RTK_MAX_METER_ID) + return RT_ERR_FILTER_METER_ID; + + switch (stormType) + { + case STORM_GROUP_UNKNOWN_UNICAST: + if ((retVal = rtl8367c_setAsicStormFilterExtUnknownUnicastMeter(index))!=RT_ERR_OK) + return retVal; + break; + case STORM_GROUP_UNKNOWN_MULTICAST: + if ((retVal = rtl8367c_setAsicStormFilterExtUnknownMulticastMeter(index))!=RT_ERR_OK) + return retVal; + break; + case STORM_GROUP_MULTICAST: + if ((retVal = rtl8367c_setAsicStormFilterExtMulticastMeter(index))!=RT_ERR_OK) + return retVal; + break; + case STORM_GROUP_BROADCAST: + if ((retVal = rtl8367c_setAsicStormFilterExtBroadcastMeter(index))!=RT_ERR_OK) + return retVal; + break; + default: + break; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_rate_stormControlExtMeterIdx_get + * Description: + * Get externsion storm control meter index + * Input: + * stormType - storm group type + * pIndex - externsion storm control state + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +rtk_api_ret_t dal_rtl8367c_rate_stormControlExtMeterIdx_get(rtk_rate_storm_group_t stormType, rtk_uint32 *pIndex) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (stormType >= STORM_GROUP_END) + return RT_ERR_SFC_UNKNOWN_GROUP; + + if(NULL == pIndex) + return RT_ERR_NULL_POINTER; + + switch (stormType) + { + case STORM_GROUP_UNKNOWN_UNICAST: + if ((retVal = rtl8367c_getAsicStormFilterExtUnknownUnicastMeter(pIndex))!=RT_ERR_OK) + return retVal; + break; + case STORM_GROUP_UNKNOWN_MULTICAST: + if ((retVal = rtl8367c_getAsicStormFilterExtUnknownMulticastMeter(pIndex))!=RT_ERR_OK) + return retVal; + break; + case STORM_GROUP_MULTICAST: + if ((retVal = rtl8367c_getAsicStormFilterExtMulticastMeter(pIndex))!=RT_ERR_OK) + return retVal; + break; + case STORM_GROUP_BROADCAST: + if ((retVal = rtl8367c_getAsicStormFilterExtBroadcastMeter(pIndex))!=RT_ERR_OK) + return retVal; + break; + default: + break; + } + + return RT_ERR_OK; +} + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_storm.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_storm.h new file mode 100644 index 00000000..9595b218 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_storm.h @@ -0,0 +1,355 @@ + /* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8367/RTL8367C switch high-level API + * + * Feature : The file includes Storm module high-layer API defination + * + */ + +#ifndef __DAL_RTL8367C_STORM_H__ +#define __DAL_RTL8367C_STORM_H__ + +#include + +/* Function Name: + * dal_rtl8367c_rate_stormControlMeterIdx_set + * Description: + * Set the storm control meter index. + * Input: + * port - port id + * storm_type - storm group type + * index - storm control meter index. + * Output: + * None. + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - Invalid port id + * RT_ERR_FILTER_METER_ID - Invalid meter + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367c_rate_stormControlMeterIdx_set(rtk_port_t port, rtk_rate_storm_group_t stormType, rtk_uint32 index); + +/* Function Name: + * dal_rtl8367c_rate_stormControlMeterIdx_get + * Description: + * Get the storm control meter index. + * Input: + * port - port id + * storm_type - storm group type + * Output: + * pIndex - storm control meter index. + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - Invalid port id + * RT_ERR_FILTER_METER_ID - Invalid meter + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367c_rate_stormControlMeterIdx_get(rtk_port_t port, rtk_rate_storm_group_t stormType, rtk_uint32 *pIndex); + +/* Function Name: + * dal_rtl8367c_rate_stormControlPortEnable_set + * Description: + * Set enable status of storm control on specified port. + * Input: + * port - port id + * stormType - storm group type + * enable - enable status of storm control + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367c_rate_stormControlPortEnable_set(rtk_port_t port, rtk_rate_storm_group_t stormType, rtk_enable_t enable); + +/* Function Name: + * dal_rtl8367c_rate_stormControlPortEnable_set + * Description: + * Set enable status of storm control on specified port. + * Input: + * port - port id + * stormType - storm group type + * Output: + * pEnable - enable status of storm control + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367c_rate_stormControlPortEnable_get(rtk_port_t port, rtk_rate_storm_group_t stormType, rtk_enable_t *pEnable); + +/* Function Name: + * dal_rtl8367c_storm_bypass_set + * Description: + * Set bypass storm filter control configuration. + * Input: + * type - Bypass storm filter control type. + * enable - Bypass status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_ENABLE - Invalid IFG parameter + * Note: + * + * This API can set per-port bypass stomr filter control frame type including RMA and igmp. + * The bypass frame type is as following: + * - BYPASS_BRG_GROUP, + * - BYPASS_FD_PAUSE, + * - BYPASS_SP_MCAST, + * - BYPASS_1X_PAE, + * - BYPASS_UNDEF_BRG_04, + * - BYPASS_UNDEF_BRG_05, + * - BYPASS_UNDEF_BRG_06, + * - BYPASS_UNDEF_BRG_07, + * - BYPASS_PROVIDER_BRIDGE_GROUP_ADDRESS, + * - BYPASS_UNDEF_BRG_09, + * - BYPASS_UNDEF_BRG_0A, + * - BYPASS_UNDEF_BRG_0B, + * - BYPASS_UNDEF_BRG_0C, + * - BYPASS_PROVIDER_BRIDGE_GVRP_ADDRESS, + * - BYPASS_8021AB, + * - BYPASS_UNDEF_BRG_0F, + * - BYPASS_BRG_MNGEMENT, + * - BYPASS_UNDEFINED_11, + * - BYPASS_UNDEFINED_12, + * - BYPASS_UNDEFINED_13, + * - BYPASS_UNDEFINED_14, + * - BYPASS_UNDEFINED_15, + * - BYPASS_UNDEFINED_16, + * - BYPASS_UNDEFINED_17, + * - BYPASS_UNDEFINED_18, + * - BYPASS_UNDEFINED_19, + * - BYPASS_UNDEFINED_1A, + * - BYPASS_UNDEFINED_1B, + * - BYPASS_UNDEFINED_1C, + * - BYPASS_UNDEFINED_1D, + * - BYPASS_UNDEFINED_1E, + * - BYPASS_UNDEFINED_1F, + * - BYPASS_GMRP, + * - BYPASS_GVRP, + * - BYPASS_UNDEF_GARP_22, + * - BYPASS_UNDEF_GARP_23, + * - BYPASS_UNDEF_GARP_24, + * - BYPASS_UNDEF_GARP_25, + * - BYPASS_UNDEF_GARP_26, + * - BYPASS_UNDEF_GARP_27, + * - BYPASS_UNDEF_GARP_28, + * - BYPASS_UNDEF_GARP_29, + * - BYPASS_UNDEF_GARP_2A, + * - BYPASS_UNDEF_GARP_2B, + * - BYPASS_UNDEF_GARP_2C, + * - BYPASS_UNDEF_GARP_2D, + * - BYPASS_UNDEF_GARP_2E, + * - BYPASS_UNDEF_GARP_2F, + * - BYPASS_IGMP. + */ +extern rtk_api_ret_t dal_rtl8367c_storm_bypass_set(rtk_storm_bypass_t type, rtk_enable_t enable); + +/* Function Name: + * dal_rtl8367c_storm_bypass_get + * Description: + * Get bypass storm filter control configuration. + * Input: + * type - Bypass storm filter control type. + * Output: + * pEnable - Bypass status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can get per-port bypass stomr filter control frame type including RMA and igmp. + * The bypass frame type is as following: + * - BYPASS_BRG_GROUP, + * - BYPASS_FD_PAUSE, + * - BYPASS_SP_MCAST, + * - BYPASS_1X_PAE, + * - BYPASS_UNDEF_BRG_04, + * - BYPASS_UNDEF_BRG_05, + * - BYPASS_UNDEF_BRG_06, + * - BYPASS_UNDEF_BRG_07, + * - BYPASS_PROVIDER_BRIDGE_GROUP_ADDRESS, + * - BYPASS_UNDEF_BRG_09, + * - BYPASS_UNDEF_BRG_0A, + * - BYPASS_UNDEF_BRG_0B, + * - BYPASS_UNDEF_BRG_0C, + * - BYPASS_PROVIDER_BRIDGE_GVRP_ADDRESS, + * - BYPASS_8021AB, + * - BYPASS_UNDEF_BRG_0F, + * - BYPASS_BRG_MNGEMENT, + * - BYPASS_UNDEFINED_11, + * - BYPASS_UNDEFINED_12, + * - BYPASS_UNDEFINED_13, + * - BYPASS_UNDEFINED_14, + * - BYPASS_UNDEFINED_15, + * - BYPASS_UNDEFINED_16, + * - BYPASS_UNDEFINED_17, + * - BYPASS_UNDEFINED_18, + * - BYPASS_UNDEFINED_19, + * - BYPASS_UNDEFINED_1A, + * - BYPASS_UNDEFINED_1B, + * - BYPASS_UNDEFINED_1C, + * - BYPASS_UNDEFINED_1D, + * - BYPASS_UNDEFINED_1E, + * - BYPASS_UNDEFINED_1F, + * - BYPASS_GMRP, + * - BYPASS_GVRP, + * - BYPASS_UNDEF_GARP_22, + * - BYPASS_UNDEF_GARP_23, + * - BYPASS_UNDEF_GARP_24, + * - BYPASS_UNDEF_GARP_25, + * - BYPASS_UNDEF_GARP_26, + * - BYPASS_UNDEF_GARP_27, + * - BYPASS_UNDEF_GARP_28, + * - BYPASS_UNDEF_GARP_29, + * - BYPASS_UNDEF_GARP_2A, + * - BYPASS_UNDEF_GARP_2B, + * - BYPASS_UNDEF_GARP_2C, + * - BYPASS_UNDEF_GARP_2D, + * - BYPASS_UNDEF_GARP_2E, + * - BYPASS_UNDEF_GARP_2F, + * - BYPASS_IGMP. + */ +extern rtk_api_ret_t dal_rtl8367c_storm_bypass_get(rtk_storm_bypass_t type, rtk_enable_t *pEnable); + +/* Function Name: + * dal_rtl8367c_rate_stormControlExtPortmask_set + * Description: + * Set externsion storm control port mask + * Input: + * pPortmask - port mask + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367c_rate_stormControlExtPortmask_set(rtk_portmask_t *pPortmask); + +/* Function Name: + * dal_rtl8367c_rate_stormControlExtPortmask_get + * Description: + * Set externsion storm control port mask + * Input: + * None + * Output: + * pPortmask - port mask + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367c_rate_stormControlExtPortmask_get(rtk_portmask_t *pPortmask); + +/* Function Name: + * dal_rtl8367c_rate_stormControlExtEnable_set + * Description: + * Set externsion storm control state + * Input: + * stormType - storm group type + * enable - externsion storm control state + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367c_rate_stormControlExtEnable_set(rtk_rate_storm_group_t stormType, rtk_enable_t enable); + +/* Function Name: + * dal_rtl8367c_rate_stormControlExtEnable_get + * Description: + * Get externsion storm control state + * Input: + * stormType - storm group type + * Output: + * pEnable - externsion storm control state + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367c_rate_stormControlExtEnable_get(rtk_rate_storm_group_t stormType, rtk_enable_t *pEnable); + +/* Function Name: + * dal_rtl8367c_rate_stormControlExtMeterIdx_set + * Description: + * Set externsion storm control meter index + * Input: + * stormType - storm group type + * index - externsion storm control state + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367c_rate_stormControlExtMeterIdx_set(rtk_rate_storm_group_t stormType, rtk_uint32 index); + +/* Function Name: + * dal_rtl8367c_rate_stormControlExtMeterIdx_get + * Description: + * Get externsion storm control meter index + * Input: + * stormType - storm group type + * pIndex - externsion storm control state + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367c_rate_stormControlExtMeterIdx_get(rtk_rate_storm_group_t stormType, rtk_uint32 *pIndex); + + + +#endif /* __DAL_RTL8367C_STORM_H__ */ diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_svlan.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_svlan.c new file mode 100644 index 00000000..8630a95f --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_svlan.c @@ -0,0 +1,2441 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8367C + * Feature : Here is a list of all functions and variables in SVLAN module. + * + */ + +#include +#include +#include +#include + +#include + +#include +#include + +rtk_uint8 svlan_mbrCfgUsage[RTL8367C_SVIDXNO]; +rtk_uint16 svlan_mbrCfgVid[RTL8367C_SVIDXNO]; +rtk_svlan_lookupType_t svlan_lookupType; + +rtk_api_ret_t dal_rtl8367c_svlan_lookupType_set(rtk_svlan_lookupType_t type); + + +/* Function Name: + * dal_rtl8367c_svlan_init + * Description: + * Initialize SVLAN Configuration + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * Ether type of S-tag in 802.1ad is 0x88a8 and there are existed ether type 0x9100 and 0x9200 for Q-in-Q SLAN design. + * User can set mathced ether type as service provider supported protocol. + */ +rtk_api_ret_t dal_rtl8367c_svlan_init(void) +{ + rtk_uint32 i; + rtk_api_ret_t retVal; + rtl8367c_svlan_memconf_t svlanMemConf; + rtl8367c_svlan_s2c_t svlanSP2CConf; + rtl8367c_svlan_mc2s_t svlanMC2SConf; + rtk_uint32 svidx; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /*default use C-priority*/ + if ((retVal = rtl8367c_setAsicSvlanPrioritySel(SPRISEL_CTAGPRI)) != RT_ERR_OK) + return retVal; + + /*Drop SVLAN untag frame*/ + if ((retVal = rtl8367c_setAsicSvlanIngressUntag(UNTAG_DROP)) != RT_ERR_OK) + return retVal; + + /*Drop SVLAN unmatch frame*/ + if ((retVal = rtl8367c_setAsicSvlanIngressUnmatch(UNMATCH_DROP)) != RT_ERR_OK) + return retVal; + + /*Set TPID to 0x88a8*/ + if ((retVal = rtl8367c_setAsicSvlanTpid(0x88a8)) != RT_ERR_OK) + return retVal; + + /*Clean Uplink Port Mask to none*/ + if ((retVal = rtl8367c_setAsicSvlanUplinkPortMask(0)) != RT_ERR_OK) + return retVal; + + /*Clean SVLAN Member Configuration*/ + for (i=0; i<= RTL8367C_SVIDXMAX; i++) + { + memset(&svlanMemConf, 0, sizeof(rtl8367c_svlan_memconf_t)); + if ((retVal = rtl8367c_setAsicSvlanMemberConfiguration(i, &svlanMemConf)) != RT_ERR_OK) + return retVal; + } + + /*Clean C2S Configuration*/ + for (i=0; i<= RTL8367C_C2SIDXMAX; i++) + { + if ((retVal = rtl8367c_setAsicSvlanC2SConf(i, 0,0,0)) != RT_ERR_OK) + return retVal; + } + + /*Clean SP2C Configuration*/ + for (i=0; i <= RTL8367C_SP2CMAX ; i++) + { + memset(&svlanSP2CConf, 0, sizeof(rtl8367c_svlan_s2c_t)); + if ((retVal = rtl8367c_setAsicSvlanSP2CConf(i, &svlanSP2CConf)) != RT_ERR_OK) + return retVal; + } + + /*Clean MC2S Configuration*/ + for (i=0 ; i<= RTL8367C_MC2SIDXMAX; i++) + { + memset(&svlanMC2SConf, 0, sizeof(rtl8367c_svlan_mc2s_t)); + if ((retVal = rtl8367c_setAsicSvlanMC2SConf(i, &svlanMC2SConf)) != RT_ERR_OK) + return retVal; + } + + + if ((retVal = dal_rtl8367c_svlan_lookupType_set(SVLAN_LOOKUP_S64MBRCGF)) != RT_ERR_OK) + return retVal; + + + for (svidx = 0; svidx <= RTL8367C_SVIDXMAX; svidx++) + { + svlan_mbrCfgUsage[svidx] = FALSE; + } + + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_svlan_servicePort_add + * Description: + * Add one service port in the specified device + * Input: + * port - Port id. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API is setting which port is connected to provider switch. All frames receiving from this port must + * contain accept SVID in S-tag field. + */ +rtk_api_ret_t dal_rtl8367c_svlan_servicePort_add(rtk_port_t port) +{ + rtk_api_ret_t retVal; + rtk_uint32 pmsk; + rtk_uint32 phyPort; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* check port valid */ + RTK_CHK_PORT_VALID(port); + + phyPort = rtk_switch_port_L2P_get(port); + if (phyPort == UNDEFINE_PHY_PORT) + return RT_ERR_PORT_ID; + + if ((retVal = rtl8367c_getAsicSvlanUplinkPortMask(&pmsk)) != RT_ERR_OK) + return retVal; + + pmsk = pmsk | (1 << phyPort); + + if ((retVal = rtl8367c_setAsicSvlanUplinkPortMask(pmsk)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_svlan_servicePort_get + * Description: + * Get service ports in the specified device. + * Input: + * None + * Output: + * pSvlan_portmask - pointer buffer of svlan ports. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API is setting which port is connected to provider switch. All frames receiving from this port must + * contain accept SVID in S-tag field. + */ +rtk_api_ret_t dal_rtl8367c_svlan_servicePort_get(rtk_portmask_t *pSvlan_portmask) +{ + rtk_api_ret_t retVal; + rtk_uint32 phyMbrPmask; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pSvlan_portmask) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicSvlanUplinkPortMask(&phyMbrPmask)) != RT_ERR_OK) + return retVal; + + if(rtk_switch_portmask_P2L_get(phyMbrPmask, pSvlan_portmask) != RT_ERR_OK) + return RT_ERR_FAILED; + + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_svlan_servicePort_del + * Description: + * Delete one service port in the specified device + * Input: + * port - Port id. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API is removing SVLAN service port in the specified device. + */ +rtk_api_ret_t dal_rtl8367c_svlan_servicePort_del(rtk_port_t port) +{ + rtk_api_ret_t retVal; + rtk_uint32 pmsk; + rtk_uint32 phyPort; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* check port valid */ + RTK_CHK_PORT_VALID(port); + + phyPort = rtk_switch_port_L2P_get(port); + if (phyPort == UNDEFINE_PHY_PORT) + return RT_ERR_PORT_ID; + + if ((retVal = rtl8367c_getAsicSvlanUplinkPortMask(&pmsk)) != RT_ERR_OK) + return retVal; + + pmsk = pmsk & ~(1<RTK_MAX_NUM_OF_PROTO_TYPE) + return RT_ERR_INPUT; + + if ((retVal = rtl8367c_setAsicSvlanTpid(svlan_tag_id)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_svlan_tpidEntry_get + * Description: + * Get accepted S-VLAN ether type setting. + * Input: + * None + * Output: + * pSvlan_tag_id - Ether type of S-tag frame parsing in uplink ports. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API is setting which port is connected to provider switch. All frames receiving from this port must + * contain accept SVID in S-tag field. + */ +rtk_api_ret_t dal_rtl8367c_svlan_tpidEntry_get(rtk_uint32 *pSvlan_tag_id) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pSvlan_tag_id) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicSvlanTpid(pSvlan_tag_id)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_svlan_priorityRef_set + * Description: + * Set S-VLAN upstream priority reference setting. + * Input: + * ref - reference selection parameter. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * Note: + * The API can set the upstream SVLAN tag priority reference source. The related priority + * sources are as following: + * - REF_INTERNAL_PRI, + * - REF_CTAG_PRI, + * - REF_SVLAN_PRI, + * - REF_PB_PRI. + */ +rtk_api_ret_t dal_rtl8367c_svlan_priorityRef_set(rtk_svlan_pri_ref_t ref) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (ref >= REF_PRI_END) + return RT_ERR_INPUT; + + if ((retVal = rtl8367c_setAsicSvlanPrioritySel(ref)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_svlan_priorityRef_get + * Description: + * Get S-VLAN upstream priority reference setting. + * Input: + * None + * Output: + * pRef - reference selection parameter. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can get the upstream SVLAN tag priority reference source. The related priority + * sources are as following: + * - REF_INTERNAL_PRI, + * - REF_CTAG_PRI, + * - REF_SVLAN_PRI, + * - REF_PB_PRI + */ +rtk_api_ret_t dal_rtl8367c_svlan_priorityRef_get(rtk_svlan_pri_ref_t *pRef) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pRef) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicSvlanPrioritySel(pRef)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_svlan_memberPortEntry_set + * Description: + * Configure system SVLAN member content + * Input: + * svid - SVLAN id + * psvlan_cfg - SVLAN member configuration + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_PORT_MASK - Invalid portmask. + * RT_ERR_SVLAN_TABLE_FULL - SVLAN configuration is full. + * Note: + * The API can set system 64 accepted s-tag frame format. Only 64 SVID S-tag frame will be accpeted + * to receiving from uplink ports. Other SVID S-tag frame or S-untagged frame will be droped by default setup. + * - rtk_svlan_memberCfg_t->svid is SVID of SVLAN member configuration. + * - rtk_svlan_memberCfg_t->memberport is member port mask of SVLAN member configuration. + * - rtk_svlan_memberCfg_t->fid is filtering database of SVLAN member configuration. + * - rtk_svlan_memberCfg_t->priority is priority of SVLAN member configuration. + */ +rtk_api_ret_t dal_rtl8367c_svlan_memberPortEntry_set(rtk_vlan_t svid, rtk_svlan_memberCfg_t *pSvlan_cfg) +{ + rtk_api_ret_t retVal; + rtk_int32 i; + rtk_uint32 empty_idx; + rtl8367c_svlan_memconf_t svlanMemConf; + rtk_uint32 phyMbrPmask; + rtk_vlan_cfg_t vlanCfg; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pSvlan_cfg) + return RT_ERR_NULL_POINTER; + + if(svid > RTL8367C_VIDMAX) + return RT_ERR_SVLAN_VID; + + RTK_CHK_PORTMASK_VALID(&(pSvlan_cfg->memberport)); + + RTK_CHK_PORTMASK_VALID(&(pSvlan_cfg->untagport)); + + if (pSvlan_cfg->fiden > ENABLED) + return RT_ERR_ENABLE; + + if (pSvlan_cfg->fid > RTL8367C_FIDMAX) + return RT_ERR_L2_FID; + + if (pSvlan_cfg->priority > RTL8367C_PRIMAX) + return RT_ERR_VLAN_PRIORITY; + + if (pSvlan_cfg->efiden > ENABLED) + return RT_ERR_ENABLE; + + if (pSvlan_cfg->efid > RTL8367C_EFIDMAX) + return RT_ERR_L2_FID; + + if(SVLAN_LOOKUP_C4KVLAN == svlan_lookupType) + { + if ((retVal = rtk_vlan_get(svid, &vlanCfg)) != RT_ERR_OK) + return retVal; + + vlanCfg.mbr = pSvlan_cfg->memberport; + vlanCfg.untag = pSvlan_cfg->untagport; + + if ((retVal = rtk_vlan_set(svid, &vlanCfg)) != RT_ERR_OK) + return retVal; + + empty_idx = 0xFF; + + for (i = 0; i<= RTL8367C_SVIDXMAX; i++) + { + if (svid == svlan_mbrCfgVid[i] && TRUE == svlan_mbrCfgUsage[i]) + { + memset(&svlanMemConf, 0, sizeof(rtl8367c_svlan_memconf_t)); + svlanMemConf.vs_svid = svid; + svlanMemConf.vs_efiden = pSvlan_cfg->efiden; + svlanMemConf.vs_efid = pSvlan_cfg->efid; + svlanMemConf.vs_priority = pSvlan_cfg->priority; + + /*for create check*/ + if(0 == svlanMemConf.vs_efiden && 0 == svlanMemConf.vs_efid) + svlanMemConf.vs_efid = 1; + + if ((retVal = rtl8367c_setAsicSvlanMemberConfiguration(i, &svlanMemConf)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; + } + else if (FALSE == svlan_mbrCfgUsage[i] && 0xFF == empty_idx) + { + empty_idx = i; + } + } + + if (empty_idx != 0xFF) + { + svlan_mbrCfgUsage[empty_idx] = TRUE; + svlan_mbrCfgVid[empty_idx] = svid; + + memset(&svlanMemConf, 0, sizeof(rtl8367c_svlan_memconf_t)); + svlanMemConf.vs_svid = svid; + svlanMemConf.vs_efiden = pSvlan_cfg->efiden; + svlanMemConf.vs_efid = pSvlan_cfg->efid; + svlanMemConf.vs_priority = pSvlan_cfg->priority; + + /*for create check*/ + if(0 == svlanMemConf.vs_efiden && 0 == svlanMemConf.vs_efid) + svlanMemConf.vs_efid = 1; + + if ((retVal = rtl8367c_setAsicSvlanMemberConfiguration(empty_idx, &svlanMemConf)) != RT_ERR_OK) + return retVal; + + } + + return RT_ERR_OK; + } + + + empty_idx = 0xFF; + + for (i = 0; i<= RTL8367C_SVIDXMAX; i++) + { + /* + if ((retVal = rtl8367c_getAsicSvlanMemberConfiguration(i, &svlanMemConf)) != RT_ERR_OK) + return retVal; + */ + if (svid == svlan_mbrCfgVid[i] && TRUE == svlan_mbrCfgUsage[i]) + { + svlanMemConf.vs_svid = svid; + + if(rtk_switch_portmask_L2P_get(&(pSvlan_cfg->memberport), &phyMbrPmask) != RT_ERR_OK) + return RT_ERR_FAILED; + + svlanMemConf.vs_member = phyMbrPmask; + + if(rtk_switch_portmask_L2P_get(&(pSvlan_cfg->untagport), &phyMbrPmask) != RT_ERR_OK) + return RT_ERR_FAILED; + + svlanMemConf.vs_untag = phyMbrPmask; + + svlanMemConf.vs_force_fid = pSvlan_cfg->fiden; + svlanMemConf.vs_fid_msti = pSvlan_cfg->fid; + svlanMemConf.vs_priority = pSvlan_cfg->priority; + svlanMemConf.vs_efiden = pSvlan_cfg->efiden; + svlanMemConf.vs_efid = pSvlan_cfg->efid; + + /*all items are reset means deleting*/ + if( 0 == svlanMemConf.vs_member && + 0 == svlanMemConf.vs_untag && + 0 == svlanMemConf.vs_force_fid && + 0 == svlanMemConf.vs_fid_msti && + 0 == svlanMemConf.vs_priority && + 0 == svlanMemConf.vs_efiden && + 0 == svlanMemConf.vs_efid) + { + svlan_mbrCfgUsage[i] = FALSE; + svlan_mbrCfgVid[i] = 0; + + /* Clear SVID also */ + svlanMemConf.vs_svid = 0; + } + else + { + svlan_mbrCfgUsage[i] = TRUE; + svlan_mbrCfgVid[i] = svlanMemConf.vs_svid; + + if(0 == svlanMemConf.vs_svid) + { + /*for create check*/ + if(0 == svlanMemConf.vs_efiden && 0 == svlanMemConf.vs_efid) + { + svlanMemConf.vs_efid = 1; + } + } + } + + if ((retVal = rtl8367c_setAsicSvlanMemberConfiguration(i, &svlanMemConf)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; + } + else if (FALSE == svlan_mbrCfgUsage[i] && 0xFF == empty_idx) + { + empty_idx = i; + } + } + + if (empty_idx != 0xFF) + { + memset(&svlanMemConf, 0, sizeof(rtl8367c_svlan_memconf_t)); + svlanMemConf.vs_svid = svid; + + if(rtk_switch_portmask_L2P_get(&(pSvlan_cfg->memberport), &phyMbrPmask) != RT_ERR_OK) + return RT_ERR_FAILED; + + svlanMemConf.vs_member = phyMbrPmask; + + if(rtk_switch_portmask_L2P_get(&(pSvlan_cfg->untagport), &phyMbrPmask) != RT_ERR_OK) + return RT_ERR_FAILED; + + svlanMemConf.vs_untag = phyMbrPmask; + + svlanMemConf.vs_force_fid = pSvlan_cfg->fiden; + svlanMemConf.vs_fid_msti = pSvlan_cfg->fid; + svlanMemConf.vs_priority = pSvlan_cfg->priority; + + svlanMemConf.vs_efiden = pSvlan_cfg->efiden; + svlanMemConf.vs_efid = pSvlan_cfg->efid; + + /*change efid for empty svid 0*/ + if(0 == svlanMemConf.vs_svid) + { /*for create check*/ + if(0 == svlanMemConf.vs_efiden && 0 == svlanMemConf.vs_efid) + { + svlanMemConf.vs_efid = 1; + } + } + + svlan_mbrCfgUsage[empty_idx] = TRUE; + svlan_mbrCfgVid[empty_idx] = svlanMemConf.vs_svid; + + if ((retVal = rtl8367c_setAsicSvlanMemberConfiguration(empty_idx, &svlanMemConf)) != RT_ERR_OK) + { + return retVal; + } + + return RT_ERR_OK; + } + + return RT_ERR_SVLAN_TABLE_FULL; +} + +/* Function Name: + * dal_rtl8367c_svlan_memberPortEntry_get + * Description: + * Get SVLAN member Configure. + * Input: + * svid - SVLAN id + * Output: + * pSvlan_cfg - SVLAN member configuration + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get system 64 accepted s-tag frame format. Only 64 SVID S-tag frame will be accpeted + * to receiving from uplink ports. Other SVID S-tag frame or S-untagged frame will be droped. + */ +rtk_api_ret_t dal_rtl8367c_svlan_memberPortEntry_get(rtk_vlan_t svid, rtk_svlan_memberCfg_t *pSvlan_cfg) +{ + rtk_api_ret_t retVal; + rtk_uint32 i; + rtl8367c_svlan_memconf_t svlanMemConf; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pSvlan_cfg) + return RT_ERR_NULL_POINTER; + + if (svid > RTL8367C_VIDMAX) + return RT_ERR_SVLAN_VID; + + + for (i = 0; i<= RTL8367C_SVIDXMAX; i++) + { + if ((retVal = rtl8367c_getAsicSvlanMemberConfiguration(i, &svlanMemConf)) != RT_ERR_OK) + return retVal; + + if (svid == svlanMemConf.vs_svid) + { + pSvlan_cfg->svid = svlanMemConf.vs_svid; + + if(rtk_switch_portmask_P2L_get(svlanMemConf.vs_member,&(pSvlan_cfg->memberport)) != RT_ERR_OK) + return RT_ERR_FAILED; + + if(rtk_switch_portmask_P2L_get(svlanMemConf.vs_untag,&(pSvlan_cfg->untagport)) != RT_ERR_OK) + return RT_ERR_FAILED; + + pSvlan_cfg->fiden = svlanMemConf.vs_force_fid; + pSvlan_cfg->fid = svlanMemConf.vs_fid_msti; + pSvlan_cfg->priority = svlanMemConf.vs_priority; + pSvlan_cfg->efiden = svlanMemConf.vs_efiden; + pSvlan_cfg->efid = svlanMemConf.vs_efid; + + return RT_ERR_OK; + } + } + + return RT_ERR_SVLAN_ENTRY_NOT_FOUND; + +} + +/* Function Name: + * dal_rtl8367c_svlan_memberPortEntry_adv_set + * Description: + * Configure system SVLAN member by index + * Input: + * idx - Index (0 ~ 63) + * psvlan_cfg - SVLAN member configuration + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_PORT_MASK - Invalid portmask. + * RT_ERR_SVLAN_TABLE_FULL - SVLAN configuration is full. + * Note: + * The API can set system 64 accepted s-tag frame format by index. + * - rtk_svlan_memberCfg_t->svid is SVID of SVLAN member configuration. + * - rtk_svlan_memberCfg_t->memberport is member port mask of SVLAN member configuration. + * - rtk_svlan_memberCfg_t->fid is filtering database of SVLAN member configuration. + * - rtk_svlan_memberCfg_t->priority is priority of SVLAN member configuration. + */ +rtk_api_ret_t dal_rtl8367c_svlan_memberPortEntry_adv_set(rtk_uint32 idx, rtk_svlan_memberCfg_t *pSvlan_cfg) +{ + rtk_api_ret_t retVal; + rtl8367c_svlan_memconf_t svlanMemConf; + rtk_uint32 phyMbrPmask; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pSvlan_cfg) + return RT_ERR_NULL_POINTER; + + if (idx > RTL8367C_SVIDXMAX) + return RT_ERR_SVLAN_ENTRY_INDEX; + + if (pSvlan_cfg->svid>RTL8367C_VIDMAX) + return RT_ERR_SVLAN_VID; + + RTK_CHK_PORTMASK_VALID(&(pSvlan_cfg->memberport)); + + RTK_CHK_PORTMASK_VALID(&(pSvlan_cfg->untagport)); + + if (pSvlan_cfg->fiden > ENABLED) + return RT_ERR_ENABLE; + + if (pSvlan_cfg->fid > RTL8367C_FIDMAX) + return RT_ERR_L2_FID; + + if (pSvlan_cfg->priority > RTL8367C_PRIMAX) + return RT_ERR_VLAN_PRIORITY; + + if (pSvlan_cfg->efiden > ENABLED) + return RT_ERR_ENABLE; + + if (pSvlan_cfg->efid > RTL8367C_EFIDMAX) + return RT_ERR_L2_FID; + + memset(&svlanMemConf, 0, sizeof(rtl8367c_svlan_memconf_t)); + svlanMemConf.vs_svid = pSvlan_cfg->svid; + if(rtk_switch_portmask_L2P_get(&(pSvlan_cfg->memberport), &phyMbrPmask) != RT_ERR_OK) + return RT_ERR_FAILED; + + svlanMemConf.vs_member = phyMbrPmask; + + if(rtk_switch_portmask_L2P_get(&(pSvlan_cfg->untagport), &phyMbrPmask) != RT_ERR_OK) + return RT_ERR_FAILED; + + svlanMemConf.vs_untag = phyMbrPmask; + + + svlanMemConf.vs_force_fid = pSvlan_cfg->fiden; + svlanMemConf.vs_fid_msti = pSvlan_cfg->fid; + svlanMemConf.vs_priority = pSvlan_cfg->priority; + svlanMemConf.vs_efiden = pSvlan_cfg->efiden; + svlanMemConf.vs_efid = pSvlan_cfg->efid; + + if(0 == svlanMemConf.vs_svid && + 0 == svlanMemConf.vs_member && + 0 == svlanMemConf.vs_untag && + 0 == svlanMemConf.vs_force_fid && + 0 == svlanMemConf.vs_fid_msti && + 0 == svlanMemConf.vs_priority && + 0 == svlanMemConf.vs_efiden && + 0 == svlanMemConf.vs_efid) + { + svlan_mbrCfgUsage[idx] = FALSE; + svlan_mbrCfgVid[idx] = 0; + } + else + { + svlan_mbrCfgUsage[idx] = TRUE; + svlan_mbrCfgVid[idx] = svlanMemConf.vs_svid; + } + + if ((retVal = rtl8367c_setAsicSvlanMemberConfiguration(idx, &svlanMemConf)) != RT_ERR_OK) + return retVal; + + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_svlan_memberPortEntry_adv_get + * Description: + * Get SVLAN member Configure by index. + * Input: + * idx - Index (0 ~ 63) + * Output: + * pSvlan_cfg - SVLAN member configuration + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get system 64 accepted s-tag frame format. Only 64 SVID S-tag frame will be accpeted + * to receiving from uplink ports. Other SVID S-tag frame or S-untagged frame will be droped. + */ +rtk_api_ret_t dal_rtl8367c_svlan_memberPortEntry_adv_get(rtk_uint32 idx, rtk_svlan_memberCfg_t *pSvlan_cfg) +{ + rtk_api_ret_t retVal; + rtl8367c_svlan_memconf_t svlanMemConf; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pSvlan_cfg) + return RT_ERR_NULL_POINTER; + + if (idx > RTL8367C_SVIDXMAX) + return RT_ERR_SVLAN_ENTRY_INDEX; + + if ((retVal = rtl8367c_getAsicSvlanMemberConfiguration(idx, &svlanMemConf)) != RT_ERR_OK) + return retVal; + + pSvlan_cfg->svid = svlanMemConf.vs_svid; + if(rtk_switch_portmask_P2L_get(svlanMemConf.vs_member,&(pSvlan_cfg->memberport)) != RT_ERR_OK) + return RT_ERR_FAILED; + + if(rtk_switch_portmask_P2L_get(svlanMemConf.vs_untag,&(pSvlan_cfg->untagport)) != RT_ERR_OK) + return RT_ERR_FAILED; + + pSvlan_cfg->fiden = svlanMemConf.vs_force_fid; + pSvlan_cfg->fid = svlanMemConf.vs_fid_msti; + pSvlan_cfg->priority = svlanMemConf.vs_priority; + pSvlan_cfg->efiden = svlanMemConf.vs_efiden; + pSvlan_cfg->efid = svlanMemConf.vs_efid; + + return RT_ERR_OK; + +} + +/* Function Name: + * dal_rtl8367c_svlan_defaultSvlan_set + * Description: + * Configure default egress SVLAN. + * Input: + * port - Source port + * svid - SVLAN id + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found. + * Note: + * The API can set port n S-tag format index while receiving frame from port n + * is transmit through uplink port with s-tag field + */ +rtk_api_ret_t dal_rtl8367c_svlan_defaultSvlan_set(rtk_port_t port, rtk_vlan_t svid) +{ + rtk_api_ret_t retVal; + rtk_uint32 i; + rtl8367c_svlan_memconf_t svlanMemConf; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check port Valid */ + RTK_CHK_PORT_VALID(port); + + /* svid must be 0~4095 */ + if (svid > RTL8367C_VIDMAX) + return RT_ERR_SVLAN_VID; + + for (i = 0; i < RTL8367C_SVIDXNO; i++) + { + if ((retVal = rtl8367c_getAsicSvlanMemberConfiguration(i, &svlanMemConf)) != RT_ERR_OK) + return retVal; + + if (svid == svlanMemConf.vs_svid) + { + if ((retVal = rtl8367c_setAsicSvlanDefaultVlan(rtk_switch_port_L2P_get(port), i)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; + } + } + + return RT_ERR_SVLAN_ENTRY_NOT_FOUND; +} + +/* Function Name: + * dal_rtl8367c_svlan_defaultSvlan_get + * Description: + * Get the configure default egress SVLAN. + * Input: + * port - Source port + * Output: + * pSvid - SVLAN VID + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get port n S-tag format index while receiving frame from port n + * is transmit through uplink port with s-tag field + */ +rtk_api_ret_t dal_rtl8367c_svlan_defaultSvlan_get(rtk_port_t port, rtk_vlan_t *pSvid) +{ + rtk_api_ret_t retVal; + rtk_uint32 idx; + rtl8367c_svlan_memconf_t svlanMemConf; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pSvid) + return RT_ERR_NULL_POINTER; + + /* Check port Valid */ + RTK_CHK_PORT_VALID(port); + + if ((retVal = rtl8367c_getAsicSvlanDefaultVlan(rtk_switch_port_L2P_get(port), &idx)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_getAsicSvlanMemberConfiguration(idx, &svlanMemConf)) != RT_ERR_OK) + return retVal; + + *pSvid = svlanMemConf.vs_svid; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_svlan_c2s_add + * Description: + * Configure SVLAN C2S table + * Input: + * vid - VLAN ID + * src_port - Ingress Port + * svid - SVLAN VID + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port ID. + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can set system C2S configuration. ASIC will check upstream's VID and assign related + * SVID to mathed packet. There are 128 SVLAN C2S configurations. + */ +rtk_api_ret_t dal_rtl8367c_svlan_c2s_add(rtk_vlan_t vid, rtk_port_t src_port, rtk_vlan_t svid) +{ + rtk_api_ret_t retVal, i; + rtk_uint32 empty_idx; + rtk_uint32 evid, pmsk, svidx, c2s_svidx; + rtl8367c_svlan_memconf_t svlanMemConf; + rtk_port_t phyPort; + rtk_uint16 doneFlag; + + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + + if (vid > RTL8367C_VIDMAX) + return RT_ERR_VLAN_VID; + + if (svid > RTL8367C_VIDMAX) + return RT_ERR_SVLAN_VID; + + /* Check port Valid */ + RTK_CHK_PORT_VALID(src_port); + + phyPort = rtk_switch_port_L2P_get(src_port); + + empty_idx = 0xFFFF; + svidx = 0xFFFF; + doneFlag = FALSE; + + for (i = 0; i<= RTL8367C_SVIDXMAX; i++) + { + if ((retVal = rtl8367c_getAsicSvlanMemberConfiguration(i, &svlanMemConf)) != RT_ERR_OK) + return retVal; + + if (svid == svlanMemConf.vs_svid) + { + svidx = i; + break; + } + } + + if (0xFFFF == svidx) + return RT_ERR_SVLAN_VID; + + for (i=RTL8367C_C2SIDXMAX; i>=0; i--) + { + if ((retVal = rtl8367c_getAsicSvlanC2SConf(i, &evid, &pmsk, &c2s_svidx)) != RT_ERR_OK) + return retVal; + + if (evid == vid) + { + /* Check Src_port */ + if(pmsk & (1 << phyPort)) + { + /* Check SVIDX */ + if(c2s_svidx == svidx) + { + /* All the same, do nothing */ + } + else + { + /* New svidx, remove src_port and find a new slot to add a new enrty */ + pmsk = pmsk & ~(1 << phyPort); + if(pmsk == 0) + c2s_svidx = 0; + + if ((retVal = rtl8367c_setAsicSvlanC2SConf(i, vid, pmsk, c2s_svidx)) != RT_ERR_OK) + return retVal; + } + } + else + { + if(c2s_svidx == svidx && doneFlag == FALSE) + { + pmsk = pmsk | (1 << phyPort); + if ((retVal = rtl8367c_setAsicSvlanC2SConf(i, vid, pmsk, svidx)) != RT_ERR_OK) + return retVal; + + doneFlag = TRUE; + } + } + } + else if (evid==0&&pmsk==0) + { + empty_idx = i; + } + } + + if (0xFFFF != empty_idx && doneFlag ==FALSE) + { + if ((retVal = rtl8367c_setAsicSvlanC2SConf(empty_idx, vid, (1< RTL8367C_EVIDMAX) + return RT_ERR_VLAN_VID; + + /* Check port Valid */ + RTK_CHK_PORT_VALID(src_port); + phyPort = rtk_switch_port_L2P_get(src_port); + if (phyPort == UNDEFINE_PHY_PORT) + return RT_ERR_PORT_ID; + + for (i = 0; i <= RTL8367C_C2SIDXMAX; i++) + { + if ((retVal = rtl8367c_getAsicSvlanC2SConf(i, &evid, &pmsk, &svidx)) != RT_ERR_OK) + return retVal; + + if (evid == vid) + { + if(pmsk & (1 << phyPort)) + { + pmsk = pmsk & ~(1 << phyPort); + if(pmsk == 0) + { + vid = 0; + svidx = 0; + } + + if ((retVal = rtl8367c_setAsicSvlanC2SConf(i, vid, pmsk, svidx)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; + } + } + } + + return RT_ERR_OUT_OF_RANGE; +} + +/* Function Name: + * dal_rtl8367c_svlan_c2s_get + * Description: + * Get configure SVLAN C2S table + * Input: + * vid - VLAN ID + * src_port - Ingress Port + * Output: + * pSvid - SVLAN ID + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port ID. + * RT_ERR_OUT_OF_RANGE - input out of range. + * Note: + * The API can get system C2S configuration. There are 128 SVLAN C2S configurations. + */ +rtk_api_ret_t dal_rtl8367c_svlan_c2s_get(rtk_vlan_t vid, rtk_port_t src_port, rtk_vlan_t *pSvid) +{ + rtk_api_ret_t retVal; + rtk_uint32 i; + rtk_uint32 evid, pmsk, svidx; + rtl8367c_svlan_memconf_t svlanMemConf; + rtk_port_t phyPort; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pSvid) + return RT_ERR_NULL_POINTER; + + if (vid > RTL8367C_VIDMAX) + return RT_ERR_VLAN_VID; + + /* Check port Valid */ + RTK_CHK_PORT_VALID(src_port); + phyPort = rtk_switch_port_L2P_get(src_port); + if (phyPort == UNDEFINE_PHY_PORT) + return RT_ERR_PORT_ID; + + for (i = 0; i <= RTL8367C_C2SIDXMAX; i++) + { + if ((retVal = rtl8367c_getAsicSvlanC2SConf(i, &evid, &pmsk, &svidx)) != RT_ERR_OK) + return retVal; + + if (evid == vid) + { + if(pmsk & (1 << phyPort)) + { + if ((retVal = rtl8367c_getAsicSvlanMemberConfiguration(svidx, &svlanMemConf)) != RT_ERR_OK) + return retVal; + + *pSvid = svlanMemConf.vs_svid; + return RT_ERR_OK; + } + } + } + + return RT_ERR_OUT_OF_RANGE; +} + +/* Function Name: + * dal_rtl8367c_svlan_untag_action_set + * Description: + * Configure Action of downstream Un-Stag packet + * Input: + * action - Action for UnStag + * svid - The SVID assigned to UnStag packet + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found. + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can configure action of downstream Un-Stag packet. A SVID assigned + * to the un-stag is also supported by this API. The parameter of svid is + * only referenced when the action is set to UNTAG_ASSIGN + */ +rtk_api_ret_t dal_rtl8367c_svlan_untag_action_set(rtk_svlan_untag_action_t action, rtk_vlan_t svid) +{ + rtk_api_ret_t retVal; + rtk_uint32 i; + rtl8367c_svlan_memconf_t svlanMemConf; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (action >= UNTAG_END) + return RT_ERR_OUT_OF_RANGE; + + if(action == UNTAG_ASSIGN) + { + if (svid > RTL8367C_VIDMAX) + return RT_ERR_SVLAN_VID; + } + + if ((retVal = rtl8367c_setAsicSvlanIngressUntag((rtk_uint32)action)) != RT_ERR_OK) + return retVal; + + if(action == UNTAG_ASSIGN) + { + for (i = 0; i < RTL8367C_SVIDXNO; i++) + { + if ((retVal = rtl8367c_getAsicSvlanMemberConfiguration(i, &svlanMemConf)) != RT_ERR_OK) + return retVal; + + if (svid == svlanMemConf.vs_svid) + { + if ((retVal = rtl8367c_setAsicSvlanUntagVlan(i)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; + } + } + + return RT_ERR_SVLAN_ENTRY_NOT_FOUND; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_svlan_untag_action_get + * Description: + * Get Action of downstream Un-Stag packet + * Input: + * None + * Output: + * pAction - Action for UnStag + * pSvid - The SVID assigned to UnStag packet + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found. + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can Get action of downstream Un-Stag packet. A SVID assigned + * to the un-stag is also retrieved by this API. The parameter pSvid is + * only refernced when the action is UNTAG_ASSIGN + */ +rtk_api_ret_t dal_rtl8367c_svlan_untag_action_get(rtk_svlan_untag_action_t *pAction, rtk_vlan_t *pSvid) +{ + rtk_api_ret_t retVal; + rtk_uint32 svidx; + rtl8367c_svlan_memconf_t svlanMemConf; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pAction || NULL == pSvid) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicSvlanIngressUntag(pAction)) != RT_ERR_OK) + return retVal; + + if(*pAction == UNTAG_ASSIGN) + { + if ((retVal = rtl8367c_getAsicSvlanUntagVlan(&svidx)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_getAsicSvlanMemberConfiguration(svidx, &svlanMemConf)) != RT_ERR_OK) + return retVal; + + *pSvid = svlanMemConf.vs_svid; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_svlan_unmatch_action_set + * Description: + * Configure Action of downstream Unmatch packet + * Input: + * action - Action for Unmatch + * svid - The SVID assigned to Unmatch packet + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found. + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can configure action of downstream Un-match packet. A SVID assigned + * to the un-match is also supported by this API. The parameter od svid is + * only refernced when the action is set to UNMATCH_ASSIGN + */ +rtk_api_ret_t dal_rtl8367c_svlan_unmatch_action_set(rtk_svlan_unmatch_action_t action, rtk_vlan_t svid) +{ + rtk_api_ret_t retVal; + rtk_uint32 i; + rtl8367c_svlan_memconf_t svlanMemConf; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (action >= UNMATCH_END) + return RT_ERR_OUT_OF_RANGE; + + if (action == UNMATCH_ASSIGN) + { + if (svid > RTL8367C_VIDMAX) + return RT_ERR_SVLAN_VID; + } + + if ((retVal = rtl8367c_setAsicSvlanIngressUnmatch((rtk_uint32)action)) != RT_ERR_OK) + return retVal; + + if(action == UNMATCH_ASSIGN) + { + for (i = 0; i < RTL8367C_SVIDXNO; i++) + { + if ((retVal = rtl8367c_getAsicSvlanMemberConfiguration(i, &svlanMemConf)) != RT_ERR_OK) + return retVal; + + if (svid == svlanMemConf.vs_svid) + { + if ((retVal = rtl8367c_setAsicSvlanUnmatchVlan(i)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; + } + } + + return RT_ERR_SVLAN_ENTRY_NOT_FOUND; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_svlan_unmatch_action_get + * Description: + * Get Action of downstream Unmatch packet + * Input: + * None + * Output: + * pAction - Action for Unmatch + * pSvid - The SVID assigned to Unmatch packet + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found. + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can Get action of downstream Un-match packet. A SVID assigned + * to the un-match is also retrieved by this API. The parameter pSvid is + * only refernced when the action is UNMATCH_ASSIGN + */ +rtk_api_ret_t dal_rtl8367c_svlan_unmatch_action_get(rtk_svlan_unmatch_action_t *pAction, rtk_vlan_t *pSvid) +{ + rtk_api_ret_t retVal; + rtk_uint32 svidx; + rtl8367c_svlan_memconf_t svlanMemConf; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pAction || NULL == pSvid) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicSvlanIngressUnmatch(pAction)) != RT_ERR_OK) + return retVal; + + if(*pAction == UNMATCH_ASSIGN) + { + if ((retVal = rtl8367c_getAsicSvlanUnmatchVlan(&svidx)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_getAsicSvlanMemberConfiguration(svidx, &svlanMemConf)) != RT_ERR_OK) + return retVal; + + *pSvid = svlanMemConf.vs_svid; + } + + return RT_ERR_OK; +} + + + +/* Function Name: + * dal_rtl8367c_svlan_unassign_action_set + * Description: + * Configure Action of upstream without svid assign action + * Input: + * action - Action for Un-assign + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can configure action of upstream Un-assign svid packet. If action is not + * trap to CPU, the port-based SVID sure be assign as system need + */ +rtk_api_ret_t dal_rtl8367c_svlan_unassign_action_set(rtk_svlan_unassign_action_t action) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (action >= UNASSIGN_END) + return RT_ERR_OUT_OF_RANGE; + + retVal = rtl8367c_setAsicSvlanEgressUnassign((rtk_uint32)action); + + return retVal; +} + +/* Function Name: + * dal_rtl8367c_svlan_unassign_action_get + * Description: + * Get action of upstream without svid assignment + * Input: + * None + * Output: + * pAction - Action for Un-assign + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * Note: + * None + */ +rtk_api_ret_t dal_rtl8367c_svlan_unassign_action_get(rtk_svlan_unassign_action_t *pAction) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pAction) + return RT_ERR_NULL_POINTER; + + retVal = rtl8367c_getAsicSvlanEgressUnassign(pAction); + + return retVal; +} + +/* Function Name: + * dal_rtl8367c_svlan_dmac_vidsel_set + * Description: + * Set DMAC CVID selection + * Input: + * port - Port + * enable - state of DMAC CVID Selection + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found. + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can set DMAC CVID Selection state + */ +rtk_api_ret_t dal_rtl8367c_svlan_dmac_vidsel_set(rtk_port_t port, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check port Valid */ + RTK_CHK_PORT_VALID(port); + + if (enable >= RTK_ENABLE_END) + return RT_ERR_ENABLE; + + if ((retVal = rtl8367c_setAsicSvlanDmacCvidSel(rtk_switch_port_L2P_get(port), enable)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_svlan_dmac_vidsel_get + * Description: + * Get DMAC CVID selection + * Input: + * port - Port + * Output: + * pEnable - state of DMAC CVID Selection + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found. + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can get DMAC CVID Selection state + */ +rtk_api_ret_t dal_rtl8367c_svlan_dmac_vidsel_get(rtk_port_t port, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pEnable) + return RT_ERR_NULL_POINTER; + + /* Check port Valid */ + RTK_CHK_PORT_VALID(port); + + if ((retVal = rtl8367c_getAsicSvlanDmacCvidSel(rtk_switch_port_L2P_get(port), pEnable)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} +/* Function Name: + * dal_rtl8367c_svlan_ipmc2s_add + * Description: + * add ip multicast address to SVLAN + * Input: + * svid - SVLAN VID + * ipmc - ip multicast address + * ipmcMsk - ip multicast mask + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found. + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can set IP mutlicast to SVID configuration. If upstream packet is IPv4 multicast + * packet and DIP is matched MC2S configuration, ASIC will assign egress SVID to the packet. + * There are 32 SVLAN multicast configurations for IP and L2 multicast. + */ +rtk_api_ret_t dal_rtl8367c_svlan_ipmc2s_add(ipaddr_t ipmc, ipaddr_t ipmcMsk, rtk_vlan_t svid) +{ + rtk_api_ret_t retVal, i; + rtk_uint32 empty_idx; + rtk_uint32 svidx; + rtl8367c_svlan_memconf_t svlanMemConf; + rtl8367c_svlan_mc2s_t svlanMC2SConf; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (svid > RTL8367C_VIDMAX) + return RT_ERR_SVLAN_VID; + + if ((ipmc&0xF0000000)!=0xE0000000) + return RT_ERR_INPUT; + + svidx = 0xFFFF; + + for (i = 0; i < RTL8367C_SVIDXNO; i++) + { + if ((retVal = rtl8367c_getAsicSvlanMemberConfiguration(i, &svlanMemConf)) != RT_ERR_OK) + return retVal; + + if (svid == svlanMemConf.vs_svid) + { + svidx = i; + break; + } + } + + if (0xFFFF == svidx) + return RT_ERR_SVLAN_ENTRY_NOT_FOUND; + + + empty_idx = 0xFFFF; + + for (i = RTL8367C_MC2SIDXMAX; i >= 0; i--) + { + if ((retVal = rtl8367c_getAsicSvlanMC2SConf(i, &svlanMC2SConf)) != RT_ERR_OK) + return retVal; + + if (TRUE == svlanMC2SConf.valid) + { + if (svlanMC2SConf.format == SVLAN_MC2S_MODE_IP && + svlanMC2SConf.sdata==ipmc&& + svlanMC2SConf.smask==ipmcMsk) + { + svlanMC2SConf.svidx = svidx; + if ((retVal = rtl8367c_setAsicSvlanMC2SConf(i, &svlanMC2SConf)) != RT_ERR_OK) + return retVal; + } + } + else + { + empty_idx = i; + } + } + + if (empty_idx!=0xFFFF) + { + svlanMC2SConf.valid = TRUE; + svlanMC2SConf.svidx = svidx; + svlanMC2SConf.format = SVLAN_MC2S_MODE_IP; + svlanMC2SConf.sdata = ipmc; + svlanMC2SConf.smask = ipmcMsk; + if ((retVal = rtl8367c_setAsicSvlanMC2SConf(empty_idx, &svlanMC2SConf)) != RT_ERR_OK) + return retVal; + return RT_ERR_OK; + } + + return RT_ERR_OUT_OF_RANGE; + +} + +/* Function Name: + * dal_rtl8367c_svlan_ipmc2s_del + * Description: + * delete ip multicast address to SVLAN + * Input: + * ipmc - ip multicast address + * ipmcMsk - ip multicast mask + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_OUT_OF_RANGE - input out of range. + * Note: + * The API can delete IP mutlicast to SVID configuration. There are 32 SVLAN multicast configurations for IP and L2 multicast. + */ +rtk_api_ret_t dal_rtl8367c_svlan_ipmc2s_del(ipaddr_t ipmc, ipaddr_t ipmcMsk) +{ + rtk_api_ret_t retVal; + rtk_uint32 i; + rtl8367c_svlan_mc2s_t svlanMC2SConf; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if ((ipmc&0xF0000000)!=0xE0000000) + return RT_ERR_INPUT; + + for (i = 0; i <= RTL8367C_MC2SIDXMAX; i++) + { + if ((retVal = rtl8367c_getAsicSvlanMC2SConf(i, &svlanMC2SConf)) != RT_ERR_OK) + return retVal; + + if (TRUE == svlanMC2SConf.valid) + { + if (svlanMC2SConf.format == SVLAN_MC2S_MODE_IP && + svlanMC2SConf.sdata==ipmc&& + svlanMC2SConf.smask==ipmcMsk) + { + memset(&svlanMC2SConf, 0, sizeof(rtl8367c_svlan_mc2s_t)); + if ((retVal = rtl8367c_setAsicSvlanMC2SConf(i, &svlanMC2SConf)) != RT_ERR_OK) + return retVal; + return RT_ERR_OK; + } + } + } + + return RT_ERR_OUT_OF_RANGE; +} + +/* Function Name: + * dal_rtl8367c_svlan_ipmc2s_get + * Description: + * Get ip multicast address to SVLAN + * Input: + * ipmc - ip multicast address + * ipmcMsk - ip multicast mask + * Output: + * pSvid - SVLAN VID + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_OUT_OF_RANGE - input out of range. + * Note: + * The API can get IP mutlicast to SVID configuration. There are 32 SVLAN multicast configurations for IP and L2 multicast. + */ +rtk_api_ret_t dal_rtl8367c_svlan_ipmc2s_get(ipaddr_t ipmc, ipaddr_t ipmcMsk, rtk_vlan_t *pSvid) +{ + rtk_api_ret_t retVal; + rtk_uint32 i; + rtl8367c_svlan_memconf_t svlanMemConf; + rtl8367c_svlan_mc2s_t svlanMC2SConf; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pSvid) + return RT_ERR_NULL_POINTER; + + if ((ipmc&0xF0000000)!=0xE0000000) + return RT_ERR_INPUT; + + for (i = 0; i <= RTL8367C_MC2SIDXMAX; i++) + { + if ((retVal = rtl8367c_getAsicSvlanMC2SConf(i, &svlanMC2SConf)) != RT_ERR_OK) + return retVal; + + if (TRUE == svlanMC2SConf.valid && + svlanMC2SConf.format == SVLAN_MC2S_MODE_IP && + svlanMC2SConf.sdata == ipmc && + svlanMC2SConf.smask == ipmcMsk) + { + if ((retVal = rtl8367c_getAsicSvlanMemberConfiguration(svlanMC2SConf.svidx, &svlanMemConf)) != RT_ERR_OK) + return retVal; + *pSvid = svlanMemConf.vs_svid; + return RT_ERR_OK; + } + } + + return RT_ERR_OUT_OF_RANGE; +} + +/* Function Name: + * dal_rtl8367c_svlan_l2mc2s_add + * Description: + * Add L2 multicast address to SVLAN + * Input: + * mac - L2 multicast address + * macMsk - L2 multicast address mask + * svid - SVLAN VID + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found. + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can set L2 Mutlicast to SVID configuration. If upstream packet is L2 multicast + * packet and DMAC is matched, ASIC will assign egress SVID to the packet. There are 32 + * SVLAN multicast configurations for IP and L2 multicast. + */ +rtk_api_ret_t dal_rtl8367c_svlan_l2mc2s_add(rtk_mac_t mac, rtk_mac_t macMsk, rtk_vlan_t svid) +{ + rtk_api_ret_t retVal, i; + rtk_uint32 empty_idx; + rtk_uint32 svidx, l2add, l2Mask; + rtl8367c_svlan_memconf_t svlanMemConf; + rtl8367c_svlan_mc2s_t svlanMC2SConf; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (svid > RTL8367C_VIDMAX) + return RT_ERR_SVLAN_VID; + + if (mac.octet[0]!= 1&&mac.octet[1]!=0) + return RT_ERR_INPUT; + + l2add = (mac.octet[2] << 24) | (mac.octet[3] << 16) | (mac.octet[4] << 8) | mac.octet[5]; + l2Mask = (macMsk.octet[2] << 24) | (macMsk.octet[3] << 16) | (macMsk.octet[4] << 8) | macMsk.octet[5]; + + svidx = 0xFFFF; + + for (i = 0; i < RTL8367C_SVIDXNO; i++) + { + if ((retVal = rtl8367c_getAsicSvlanMemberConfiguration(i, &svlanMemConf)) != RT_ERR_OK) + return retVal; + + if (svid == svlanMemConf.vs_svid) + { + svidx = i; + break; + } + } + + if (0xFFFF == svidx) + return RT_ERR_SVLAN_ENTRY_NOT_FOUND; + + empty_idx = 0xFFFF; + + for (i = RTL8367C_MC2SIDXMAX; i >=0; i--) + { + if ((retVal = rtl8367c_getAsicSvlanMC2SConf(i, &svlanMC2SConf)) != RT_ERR_OK) + return retVal; + + if (TRUE == svlanMC2SConf.valid) + { + if (svlanMC2SConf.format == SVLAN_MC2S_MODE_MAC && + svlanMC2SConf.sdata==l2add&& + svlanMC2SConf.smask==l2Mask) + { + svlanMC2SConf.svidx = svidx; + if ((retVal = rtl8367c_setAsicSvlanMC2SConf(i, &svlanMC2SConf)) != RT_ERR_OK) + return retVal; + } + } + else + { + empty_idx = i; + } + } + + if (empty_idx!=0xFFFF) + { + svlanMC2SConf.valid = TRUE; + svlanMC2SConf.svidx = svidx; + svlanMC2SConf.format = SVLAN_MC2S_MODE_MAC; + svlanMC2SConf.sdata = l2add; + svlanMC2SConf.smask = l2Mask; + + if ((retVal = rtl8367c_setAsicSvlanMC2SConf(empty_idx, &svlanMC2SConf)) != RT_ERR_OK) + return retVal; + return RT_ERR_OK; + } + + return RT_ERR_OUT_OF_RANGE; +} + +/* Function Name: + * dal_rtl8367c_svlan_l2mc2s_del + * Description: + * delete L2 multicast address to SVLAN + * Input: + * mac - L2 multicast address + * macMsk - L2 multicast address mask + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_OUT_OF_RANGE - input out of range. + * Note: + * The API can delete Mutlicast to SVID configuration. There are 32 SVLAN multicast configurations for IP and L2 multicast. + */ +rtk_api_ret_t dal_rtl8367c_svlan_l2mc2s_del(rtk_mac_t mac, rtk_mac_t macMsk) +{ + rtk_api_ret_t retVal; + rtk_uint32 i; + rtk_uint32 l2add, l2Mask; + rtl8367c_svlan_mc2s_t svlanMC2SConf; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (mac.octet[0]!= 1&&mac.octet[1]!=0) + return RT_ERR_INPUT; + + l2add = (mac.octet[2] << 24) | (mac.octet[3] << 16) | (mac.octet[4] << 8) | mac.octet[5]; + l2Mask = (macMsk.octet[2] << 24) | (macMsk.octet[3] << 16) | (macMsk.octet[4] << 8) | macMsk.octet[5]; + + for (i = 0; i <= RTL8367C_MC2SIDXMAX; i++) + { + if ((retVal = rtl8367c_getAsicSvlanMC2SConf(i, &svlanMC2SConf)) != RT_ERR_OK) + return retVal; + + if (TRUE == svlanMC2SConf.valid) + { + if (svlanMC2SConf.format == SVLAN_MC2S_MODE_MAC && + svlanMC2SConf.sdata==l2add&& + svlanMC2SConf.smask==l2Mask) + { + memset(&svlanMC2SConf, 0, sizeof(rtl8367c_svlan_mc2s_t)); + if ((retVal = rtl8367c_setAsicSvlanMC2SConf(i, &svlanMC2SConf)) != RT_ERR_OK) + return retVal; + return RT_ERR_OK; + } + } + } + + return RT_ERR_OUT_OF_RANGE; +} + +/* Function Name: + * dal_rtl8367c_svlan_l2mc2s_get + * Description: + * Get L2 multicast address to SVLAN + * Input: + * mac - L2 multicast address + * macMsk - L2 multicast address mask + * Output: + * pSvid - SVLAN VID + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_OUT_OF_RANGE - input out of range. + * Note: + * The API can get L2 mutlicast to SVID configuration. There are 32 SVLAN multicast configurations for IP and L2 multicast. + */ +rtk_api_ret_t dal_rtl8367c_svlan_l2mc2s_get(rtk_mac_t mac, rtk_mac_t macMsk, rtk_vlan_t *pSvid) +{ + rtk_api_ret_t retVal; + rtk_uint32 i; + rtk_uint32 l2add,l2Mask; + rtl8367c_svlan_memconf_t svlanMemConf; + rtl8367c_svlan_mc2s_t svlanMC2SConf; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pSvid) + return RT_ERR_NULL_POINTER; + + if (mac.octet[0]!= 1&&mac.octet[1]!=0) + return RT_ERR_INPUT; + + l2add = (mac.octet[2] << 24) | (mac.octet[3] << 16) | (mac.octet[4] << 8) | mac.octet[5]; + l2Mask = (macMsk.octet[2] << 24) | (macMsk.octet[3] << 16) | (macMsk.octet[4] << 8) | macMsk.octet[5]; + + for (i = 0; i <= RTL8367C_MC2SIDXMAX; i++) + { + if ((retVal = rtl8367c_getAsicSvlanMC2SConf(i, &svlanMC2SConf)) != RT_ERR_OK) + return retVal; + + if (TRUE == svlanMC2SConf.valid) + { + if (svlanMC2SConf.format == SVLAN_MC2S_MODE_MAC && + svlanMC2SConf.sdata==l2add&& + svlanMC2SConf.smask==l2Mask) + { + if ((retVal = rtl8367c_getAsicSvlanMemberConfiguration(svlanMC2SConf.svidx, &svlanMemConf)) != RT_ERR_OK) + return retVal; + *pSvid = svlanMemConf.vs_svid; + + return RT_ERR_OK; + } + } + } + + return RT_ERR_OUT_OF_RANGE; +} + +/* Function Name: + * dal_rtl8367c_svlan_sp2c_add + * Description: + * Add system SP2C configuration + * Input: + * cvid - VLAN ID + * dst_port - Destination port of SVLAN to CVLAN configuration + * svid - SVLAN VID + * + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can add SVID & Destination Port to CVLAN configuration. The downstream frames with assigned + * SVID will be add C-tag with assigned CVID if the output port is the assigned destination port. + * There are 128 SP2C configurations. + */ +rtk_api_ret_t dal_rtl8367c_svlan_sp2c_add(rtk_vlan_t svid, rtk_port_t dst_port, rtk_vlan_t cvid) +{ + rtk_api_ret_t retVal, i; + rtk_uint32 empty_idx, svidx; + rtl8367c_svlan_memconf_t svlanMemConf; + rtl8367c_svlan_s2c_t svlanSP2CConf; + rtk_port_t port; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (svid > RTL8367C_VIDMAX) + return RT_ERR_SVLAN_VID; + + if (cvid > RTL8367C_VIDMAX) + return RT_ERR_VLAN_VID; + + /* Check port Valid */ + RTK_CHK_PORT_VALID(dst_port); + port = rtk_switch_port_L2P_get(dst_port); + + svidx = 0xFFFF; + + for (i = 0; i < RTL8367C_SVIDXNO; i++) + { + if ((retVal = rtl8367c_getAsicSvlanMemberConfiguration(i, &svlanMemConf)) != RT_ERR_OK) + return retVal; + + if (svid == svlanMemConf.vs_svid) + { + svidx = i; + break; + } + } + + if (0xFFFF == svidx) + return RT_ERR_SVLAN_ENTRY_NOT_FOUND; + + empty_idx = 0xFFFF; + + for (i=RTL8367C_SP2CMAX; i >=0 ; i--) + { + if ((retVal = rtl8367c_getAsicSvlanSP2CConf(i, &svlanSP2CConf)) != RT_ERR_OK) + return retVal; + + if ( (svlanSP2CConf.svidx == svidx) && (svlanSP2CConf.dstport == port) && (svlanSP2CConf.valid == 1)) + { + empty_idx = i; + break; + } + else if (svlanSP2CConf.valid == 0) + { + empty_idx = i; + } + } + + if (empty_idx!=0xFFFF) + { + svlanSP2CConf.valid = 1; + svlanSP2CConf.vid = cvid; + svlanSP2CConf.svidx = svidx; + svlanSP2CConf.dstport = port; + + if ((retVal = rtl8367c_setAsicSvlanSP2CConf(empty_idx, &svlanSP2CConf)) != RT_ERR_OK) + return retVal; + return RT_ERR_OK; + } + + return RT_ERR_OUT_OF_RANGE; + +} + +/* Function Name: + * dal_rtl8367c_svlan_sp2c_get + * Description: + * Get configure system SP2C content + * Input: + * svid - SVLAN VID + * dst_port - Destination port of SVLAN to CVLAN configuration + * Output: + * pCvid - VLAN ID + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * Note: + * The API can get SVID & Destination Port to CVLAN configuration. There are 128 SP2C configurations. + */ +rtk_api_ret_t dal_rtl8367c_svlan_sp2c_get(rtk_vlan_t svid, rtk_port_t dst_port, rtk_vlan_t *pCvid) +{ + rtk_api_ret_t retVal; + rtk_uint32 i, svidx; + rtl8367c_svlan_memconf_t svlanMemConf; + rtl8367c_svlan_s2c_t svlanSP2CConf; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pCvid) + return RT_ERR_NULL_POINTER; + + if (svid > RTL8367C_VIDMAX) + return RT_ERR_SVLAN_VID; + + /* Check port Valid */ + RTK_CHK_PORT_VALID(dst_port); + dst_port = rtk_switch_port_L2P_get(dst_port); + + svidx = 0xFFFF; + + for (i = 0; i < RTL8367C_SVIDXNO; i++) + { + if ((retVal = rtl8367c_getAsicSvlanMemberConfiguration(i, &svlanMemConf)) != RT_ERR_OK) + return retVal; + + if (svid == svlanMemConf.vs_svid) + { + svidx = i; + break; + } + } + + if (0xFFFF == svidx) + return RT_ERR_SVLAN_ENTRY_NOT_FOUND; + + for (i = 0; i <= RTL8367C_SP2CMAX; i++) + { + if ((retVal = rtl8367c_getAsicSvlanSP2CConf(i, &svlanSP2CConf)) != RT_ERR_OK) + return retVal; + + if ( (svlanSP2CConf.svidx == svidx) && (svlanSP2CConf.dstport == dst_port) && (svlanSP2CConf.valid == 1) ) + { + *pCvid = svlanSP2CConf.vid; + return RT_ERR_OK; + } + } + + return RT_ERR_OUT_OF_RANGE; +} + +/* Function Name: + * dal_rtl8367c_svlan_sp2c_del + * Description: + * Delete system SP2C configuration + * Input: + * svid - SVLAN VID + * dst_port - Destination port of SVLAN to CVLAN configuration + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_OUT_OF_RANGE - input out of range. + * Note: + * The API can delete SVID & Destination Port to CVLAN configuration. There are 128 SP2C configurations. + */ +rtk_api_ret_t dal_rtl8367c_svlan_sp2c_del(rtk_vlan_t svid, rtk_port_t dst_port) +{ + rtk_api_ret_t retVal; + rtk_uint32 i, svidx; + rtl8367c_svlan_memconf_t svlanMemConf; + rtl8367c_svlan_s2c_t svlanSP2CConf; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (svid > RTL8367C_VIDMAX) + return RT_ERR_SVLAN_VID; + + /* Check port Valid */ + RTK_CHK_PORT_VALID(dst_port); + dst_port = rtk_switch_port_L2P_get(dst_port); + + svidx = 0xFFFF; + + for (i = 0; i < RTL8367C_SVIDXNO; i++) + { + if ((retVal = rtl8367c_getAsicSvlanMemberConfiguration(i, &svlanMemConf)) != RT_ERR_OK) + return retVal; + + if (svid == svlanMemConf.vs_svid) + { + svidx = i; + break; + } + } + + if (0xFFFF == svidx) + return RT_ERR_SVLAN_ENTRY_NOT_FOUND; + + for (i = 0; i <= RTL8367C_SP2CMAX; i++) + { + if ((retVal = rtl8367c_getAsicSvlanSP2CConf(i, &svlanSP2CConf)) != RT_ERR_OK) + return retVal; + + if ( (svlanSP2CConf.svidx == svidx) && (svlanSP2CConf.dstport == dst_port) && (svlanSP2CConf.valid == 1) ) + { + svlanSP2CConf.valid = 0; + svlanSP2CConf.vid = 0; + svlanSP2CConf.svidx = 0; + svlanSP2CConf.dstport = 0; + + if ((retVal = rtl8367c_setAsicSvlanSP2CConf(i, &svlanSP2CConf)) != RT_ERR_OK) + return retVal; + return RT_ERR_OK; + } + + } + + return RT_ERR_OUT_OF_RANGE; +} + +/* Function Name: + * dal_rtl8367c_svlan_lookupType_set + * Description: + * Set lookup type of SVLAN + * Input: + * type - lookup type + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * Note: + * none + */ +rtk_api_ret_t dal_rtl8367c_svlan_lookupType_set(rtk_svlan_lookupType_t type) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (type >= SVLAN_LOOKUP_END) + return RT_ERR_CHIP_NOT_SUPPORTED; + + + svlan_lookupType = type; + + retVal = rtl8367c_setAsicSvlanLookupType((rtk_uint32)type); + + return retVal; +} + +/* Function Name: + * dal_rtl8367c_svlan_lookupType_get + * Description: + * Get lookup type of SVLAN + * Input: + * pType - lookup type + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * Note: + * none + */ +rtk_api_ret_t dal_rtl8367c_svlan_lookupType_get(rtk_svlan_lookupType_t *pType) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pType) + return RT_ERR_NULL_POINTER; + + retVal = rtl8367c_getAsicSvlanLookupType(pType); + + svlan_lookupType = *pType; + + return retVal; +} + +/* Function Name: + * dal_rtl8367c_svlan_trapPri_set + * Description: + * Set svlan trap priority + * Input: + * priority - priority for trap packets + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_QOS_INT_PRIORITY + * Note: + * None + */ +rtk_api_ret_t dal_rtl8367c_svlan_trapPri_set(rtk_pri_t priority) +{ + rtk_api_ret_t retVal; + + RTK_CHK_INIT_STATE(); + + if(priority > RTL8367C_PRIMAX) + return RT_ERR_OUT_OF_RANGE; + + retVal = rtl8367c_setAsicSvlanTrapPriority(priority); + + return retVal; +} + +/* Function Name: + * dal_rtl8367c_svlan_trapPri_get + * Description: + * Get svlan trap priority + * Input: + * None + * Output: + * pPriority - priority for trap packets + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None + */ +rtk_api_ret_t dal_rtl8367c_svlan_trapPri_get(rtk_pri_t *pPriority) +{ + rtk_api_ret_t retVal; + + RTK_CHK_INIT_STATE(); + + if(NULL == pPriority) + return RT_ERR_NULL_POINTER; + + retVal = rtl8367c_getAsicSvlanTrapPriority(pPriority); + + return retVal; +} /* end of rtk_svlan_trapPri_get */ + + +/*Don't lock mutex in following API*/ + + +/* Function Name: + * dal_rtl8367c_svlan_checkAndCreateMbr + * Description: + * Check and create Member configuration and return index + * Input: + * vid - VLAN id. + * Output: + * pIndex - Member configuration index + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_VLAN_VID - Invalid VLAN ID. + * RT_ERR_TBL_FULL - Member Configuration table full + * Note: + * + */ +rtk_api_ret_t dal_rtl8367c_svlan_checkAndCreateMbr(rtk_vlan_t vid, rtk_uint32 *pIndex) +{ + rtk_api_ret_t retVal; + rtk_uint32 svidx; + rtk_uint32 empty_idx = 0xFFFF; + rtl8367c_svlan_memconf_t svlan_cfg; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* vid must be 0~4095 */ + if (vid > RTL8367C_VIDMAX) + return RT_ERR_VLAN_VID; + + /* Null pointer check */ + if(NULL == pIndex) + return RT_ERR_NULL_POINTER; + + /* Search exist entry */ + for (svidx = 0; svidx <= RTL8367C_SVIDXMAX; svidx++) + { + if(svlan_mbrCfgUsage[svidx] == TRUE) + { + if(svlan_mbrCfgVid[svidx] == vid) + { + /* Found! return index */ + *pIndex = svidx; + return RT_ERR_OK; + } + } + else if(empty_idx == 0xFFFF) + { + empty_idx = svidx; + } + + } + + if(empty_idx == 0xFFFF) + { + /* No empty index */ + return RT_ERR_TBL_FULL; + } + + svlan_mbrCfgUsage[empty_idx] = TRUE; + svlan_mbrCfgVid[empty_idx] = vid; + + memset(&svlan_cfg, 0, sizeof(rtl8367c_svlan_memconf_t)); + + svlan_cfg.vs_svid = vid; + /*for create check*/ + if(vid == 0) + { + svlan_cfg.vs_efid = 1; + } + + if((retVal = rtl8367c_setAsicSvlanMemberConfiguration(empty_idx, &svlan_cfg)) != RT_ERR_OK) + return retVal; + + *pIndex = empty_idx; + return RT_ERR_OK; +} + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_svlan.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_svlan.h new file mode 100644 index 00000000..092ebe30 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_svlan.h @@ -0,0 +1,843 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8367/RTL8367C switch high-level API + * + * Feature : The file includes SVLAN module high-layer API defination + * + */ + +#ifndef __DAL_RTL8367C_SVLAN_H__ +#define __DAL_RTL8367C_SVLAN_H__ + +#include + +/* Function Name: + * dal_rtl8367c_svlan_init + * Description: + * Initialize SVLAN Configuration + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * Ether type of S-tag in 802.1ad is 0x88a8 and there are existed ether type 0x9100 and 0x9200 for Q-in-Q SLAN design. + * User can set mathced ether type as service provider supported protocol. + */ +extern rtk_api_ret_t dal_rtl8367c_svlan_init(void); + +/* Function Name: + * dal_rtl8367c_svlan_servicePort_add + * Description: + * Add one service port in the specified device + * Input: + * port - Port id. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API is setting which port is connected to provider switch. All frames receiving from this port must + * contain accept SVID in S-tag field. + */ +extern rtk_api_ret_t dal_rtl8367c_svlan_servicePort_add(rtk_port_t port); + +/* Function Name: + * dal_rtl8367c_svlan_servicePort_get + * Description: + * Get service ports in the specified device. + * Input: + * None + * Output: + * pSvlan_portmask - pointer buffer of svlan ports. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API is setting which port is connected to provider switch. All frames receiving from this port must + * contain accept SVID in S-tag field. + */ +extern rtk_api_ret_t dal_rtl8367c_svlan_servicePort_get(rtk_portmask_t *pSvlan_portmask); + +/* Function Name: + * dal_rtl8367c_svlan_servicePort_del + * Description: + * Delete one service port in the specified device + * Input: + * port - Port id. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API is removing SVLAN service port in the specified device. + */ +extern rtk_api_ret_t dal_rtl8367c_svlan_servicePort_del(rtk_port_t port); + +/* Function Name: + * dal_rtl8367c_svlan_tpidEntry_set + * Description: + * Configure accepted S-VLAN ether type. + * Input: + * svlan_tag_id - Ether type of S-tag frame parsing in uplink ports. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * Note: + * Ether type of S-tag in 802.1ad is 0x88a8 and there are existed ether type 0x9100 and 0x9200 for Q-in-Q SLAN design. + * User can set mathced ether type as service provider supported protocol. + */ +extern rtk_api_ret_t dal_rtl8367c_svlan_tpidEntry_set(rtk_uint32 svlan_tag_id); + +/* Function Name: + * dal_rtl8367c_svlan_tpidEntry_get + * Description: + * Get accepted S-VLAN ether type setting. + * Input: + * None + * Output: + * pSvlan_tag_id - Ether type of S-tag frame parsing in uplink ports. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API is setting which port is connected to provider switch. All frames receiving from this port must + * contain accept SVID in S-tag field. + */ +extern rtk_api_ret_t dal_rtl8367c_svlan_tpidEntry_get(rtk_uint32 *pSvlan_tag_id); + +/* Function Name: + * dal_rtl8367c_svlan_priorityRef_set + * Description: + * Set S-VLAN upstream priority reference setting. + * Input: + * ref - reference selection parameter. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * Note: + * The API can set the upstream SVLAN tag priority reference source. The related priority + * sources are as following: + * - REF_INTERNAL_PRI, + * - REF_CTAG_PRI, + * - REF_SVLAN_PRI, + * - REF_PB_PRI. + */ +extern rtk_api_ret_t dal_rtl8367c_svlan_priorityRef_set(rtk_svlan_pri_ref_t ref); + +/* Function Name: + * dal_rtl8367c_svlan_priorityRef_get + * Description: + * Get S-VLAN upstream priority reference setting. + * Input: + * None + * Output: + * pRef - reference selection parameter. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can get the upstream SVLAN tag priority reference source. The related priority + * sources are as following: + * - REF_INTERNAL_PRI, + * - REF_CTAG_PRI, + * - REF_SVLAN_PRI, + * - REF_PB_PRI + */ +extern rtk_api_ret_t dal_rtl8367c_svlan_priorityRef_get(rtk_svlan_pri_ref_t *pRef); + +/* Function Name: + * dal_rtl8367c_svlan_memberPortEntry_set + * Description: + * Configure system SVLAN member content + * Input: + * svid - SVLAN id + * psvlan_cfg - SVLAN member configuration + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_PORT_MASK - Invalid portmask. + * RT_ERR_SVLAN_TABLE_FULL - SVLAN configuration is full. + * Note: + * The API can set system 64 accepted s-tag frame format. Only 64 SVID S-tag frame will be accpeted + * to receiving from uplink ports. Other SVID S-tag frame or S-untagged frame will be droped by default setup. + * - rtk_svlan_memberCfg_t->svid is SVID of SVLAN member configuration. + * - rtk_svlan_memberCfg_t->memberport is member port mask of SVLAN member configuration. + * - rtk_svlan_memberCfg_t->fid is filtering database of SVLAN member configuration. + * - rtk_svlan_memberCfg_t->priority is priority of SVLAN member configuration. + */ +extern rtk_api_ret_t dal_rtl8367c_svlan_memberPortEntry_set(rtk_uint32 svid_idx, rtk_svlan_memberCfg_t *psvlan_cfg); + +/* Function Name: + * dal_rtl8367c_svlan_memberPortEntry_get + * Description: + * Get SVLAN member Configure. + * Input: + * svid - SVLAN id + * Output: + * pSvlan_cfg - SVLAN member configuration + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get system 64 accepted s-tag frame format. Only 64 SVID S-tag frame will be accpeted + * to receiving from uplink ports. Other SVID S-tag frame or S-untagged frame will be droped. + */ +extern rtk_api_ret_t dal_rtl8367c_svlan_memberPortEntry_get(rtk_uint32 svid_idx, rtk_svlan_memberCfg_t *pSvlan_cfg); + +/* Function Name: + * dal_rtl8367c_svlan_memberPortEntry_adv_set + * Description: + * Configure system SVLAN member by index + * Input: + * idx - Index (0 ~ 63) + * psvlan_cfg - SVLAN member configuration + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_PORT_MASK - Invalid portmask. + * RT_ERR_SVLAN_TABLE_FULL - SVLAN configuration is full. + * Note: + * The API can set system 64 accepted s-tag frame format by index. + * - rtk_svlan_memberCfg_t->svid is SVID of SVLAN member configuration. + * - rtk_svlan_memberCfg_t->memberport is member port mask of SVLAN member configuration. + * - rtk_svlan_memberCfg_t->fid is filtering database of SVLAN member configuration. + * - rtk_svlan_memberCfg_t->priority is priority of SVLAN member configuration. + */ +extern rtk_api_ret_t dal_rtl8367c_svlan_memberPortEntry_adv_set(rtk_uint32 idx, rtk_svlan_memberCfg_t *pSvlan_cfg); + +/* Function Name: + * dal_rtl8367c_svlan_memberPortEntry_adv_get + * Description: + * Get SVLAN member Configure by index. + * Input: + * idx - Index (0 ~ 63) + * Output: + * pSvlan_cfg - SVLAN member configuration + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get system 64 accepted s-tag frame format. Only 64 SVID S-tag frame will be accpeted + * to receiving from uplink ports. Other SVID S-tag frame or S-untagged frame will be droped. + */ +extern rtk_api_ret_t dal_rtl8367c_svlan_memberPortEntry_adv_get(rtk_uint32 idx, rtk_svlan_memberCfg_t *pSvlan_cfg); + +/* Function Name: + * dal_rtl8367c_svlan_defaultSvlan_set + * Description: + * Configure default egress SVLAN. + * Input: + * port - Source port + * svid - SVLAN id + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found. + * Note: + * The API can set port n S-tag format index while receiving frame from port n + * is transmit through uplink port with s-tag field + */ +extern rtk_api_ret_t dal_rtl8367c_svlan_defaultSvlan_set(rtk_port_t port, rtk_vlan_t svid); + +/* Function Name: + * dal_rtl8367c_svlan_defaultSvlan_get + * Description: + * Get the configure default egress SVLAN. + * Input: + * port - Source port + * Output: + * pSvid - SVLAN VID + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get port n S-tag format index while receiving frame from port n + * is transmit through uplink port with s-tag field + */ +extern rtk_api_ret_t dal_rtl8367c_svlan_defaultSvlan_get(rtk_port_t port, rtk_vlan_t *pSvid); + +/* Function Name: + * dal_rtl8367c_svlan_c2s_add + * Description: + * Configure SVLAN C2S table + * Input: + * vid - VLAN ID + * src_port - Ingress Port + * svid - SVLAN VID + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port ID. + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can set system C2S configuration. ASIC will check upstream's VID and assign related + * SVID to mathed packet. There are 128 SVLAN C2S configurations. + */ +extern rtk_api_ret_t dal_rtl8367c_svlan_c2s_add(rtk_vlan_t vid, rtk_port_t src_port, rtk_vlan_t svid); + +/* Function Name: + * dal_rtl8367c_svlan_c2s_del + * Description: + * Delete one C2S entry + * Input: + * vid - VLAN ID + * src_port - Ingress Port + * svid - SVLAN VID + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_VLAN_VID - Invalid VID parameter. + * RT_ERR_PORT_ID - Invalid port ID. + * RT_ERR_OUT_OF_RANGE - input out of range. + * Note: + * The API can delete system C2S configuration. There are 128 SVLAN C2S configurations. + */ +extern rtk_api_ret_t dal_rtl8367c_svlan_c2s_del(rtk_vlan_t vid, rtk_port_t src_port); + +/* Function Name: + * dal_rtl8367c_svlan_c2s_get + * Description: + * Get configure SVLAN C2S table + * Input: + * vid - VLAN ID + * src_port - Ingress Port + * Output: + * pSvid - SVLAN ID + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port ID. + * RT_ERR_OUT_OF_RANGE - input out of range. + * Note: + * The API can get system C2S configuration. There are 128 SVLAN C2S configurations. + */ +extern rtk_api_ret_t dal_rtl8367c_svlan_c2s_get(rtk_vlan_t vid, rtk_port_t src_port, rtk_vlan_t *pSvid); + +/* Function Name: + * dal_rtl8367c_svlan_untag_action_set + * Description: + * Configure Action of downstream Un-Stag packet + * Input: + * action - Action for UnStag + * svid - The SVID assigned to UnStag packet + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found. + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can configure action of downstream Un-Stag packet. A SVID assigned + * to the un-stag is also supported by this API. The parameter of svid is + * only referenced when the action is set to UNTAG_ASSIGN + */ +extern rtk_api_ret_t dal_rtl8367c_svlan_untag_action_set(rtk_svlan_untag_action_t action, rtk_vlan_t svid); + +/* Function Name: + * dal_rtl8367c_svlan_untag_action_get + * Description: + * Get Action of downstream Un-Stag packet + * Input: + * None + * Output: + * pAction - Action for UnStag + * pSvid - The SVID assigned to UnStag packet + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found. + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can Get action of downstream Un-Stag packet. A SVID assigned + * to the un-stag is also retrieved by this API. The parameter pSvid is + * only refernced when the action is UNTAG_ASSIGN + */ +extern rtk_api_ret_t dal_rtl8367c_svlan_untag_action_get(rtk_svlan_untag_action_t *pAction, rtk_vlan_t *pSvid); + +/* Function Name: + * dal_rtl8367c_svlan_unmatch_action_set + * Description: + * Configure Action of downstream Unmatch packet + * Input: + * action - Action for Unmatch + * svid - The SVID assigned to Unmatch packet + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found. + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can configure action of downstream Un-match packet. A SVID assigned + * to the un-match is also supported by this API. The parameter od svid is + * only refernced when the action is set to UNMATCH_ASSIGN + */ +extern rtk_api_ret_t dal_rtl8367c_svlan_unmatch_action_set(rtk_svlan_unmatch_action_t action, rtk_vlan_t svid); + +/* Function Name: + * dal_rtl8367c_svlan_unmatch_action_get + * Description: + * Get Action of downstream Unmatch packet + * Input: + * None + * Output: + * pAction - Action for Unmatch + * pSvid - The SVID assigned to Unmatch packet + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found. + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can Get action of downstream Un-match packet. A SVID assigned + * to the un-match is also retrieved by this API. The parameter pSvid is + * only refernced when the action is UNMATCH_ASSIGN + */ +extern rtk_api_ret_t dal_rtl8367c_svlan_unmatch_action_get(rtk_svlan_unmatch_action_t *pAction, rtk_vlan_t *pSvid); + +/* Function Name: + * dal_rtl8367c_svlan_dmac_vidsel_set + * Description: + * Set DMAC CVID selection + * Input: + * port - Port + * enable - state of DMAC CVID Selection + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found. + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can set DMAC CVID Selection state + */ +extern rtk_api_ret_t dal_rtl8367c_svlan_dmac_vidsel_set(rtk_port_t port, rtk_enable_t enable); + +/* Function Name: + * dal_rtl8367c_svlan_dmac_vidsel_get + * Description: + * Get DMAC CVID selection + * Input: + * port - Port + * Output: + * pEnable - state of DMAC CVID Selection + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found. + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can get DMAC CVID Selection state + */ +extern rtk_api_ret_t dal_rtl8367c_svlan_dmac_vidsel_get(rtk_port_t port, rtk_enable_t *pEnable); + +/* Function Name: + * dal_rtl8367c_svlan_ipmc2s_add + * Description: + * add ip multicast address to SVLAN + * Input: + * svid - SVLAN VID + * ipmc - ip multicast address + * ipmcMsk - ip multicast mask + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found. + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can set IP mutlicast to SVID configuration. If upstream packet is IPv4 multicast + * packet and DIP is matched MC2S configuration, ASIC will assign egress SVID to the packet. + * There are 32 SVLAN multicast configurations for IP and L2 multicast. + */ +extern rtk_api_ret_t dal_rtl8367c_svlan_ipmc2s_add(ipaddr_t ipmc, ipaddr_t ipmcMsk, rtk_vlan_t svid); + +/* Function Name: + * dal_rtl8367c_svlan_ipmc2s_del + * Description: + * delete ip multicast address to SVLAN + * Input: + * ipmc - ip multicast address + * ipmcMsk - ip multicast mask + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_OUT_OF_RANGE - input out of range. + * Note: + * The API can delete IP mutlicast to SVID configuration. There are 32 SVLAN multicast configurations for IP and L2 multicast. + */ +extern rtk_api_ret_t dal_rtl8367c_svlan_ipmc2s_del(ipaddr_t ipmc, ipaddr_t ipmcMsk); + +/* Function Name: + * dal_rtl8367c_svlan_ipmc2s_get + * Description: + * Get ip multicast address to SVLAN + * Input: + * ipmc - ip multicast address + * ipmcMsk - ip multicast mask + * Output: + * pSvid - SVLAN VID + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_OUT_OF_RANGE - input out of range. + * Note: + * The API can get IP mutlicast to SVID configuration. There are 32 SVLAN multicast configurations for IP and L2 multicast. + */ +extern rtk_api_ret_t dal_rtl8367c_svlan_ipmc2s_get(ipaddr_t ipmc, ipaddr_t ipmcMsk, rtk_vlan_t *pSvid); + +/* Function Name: + * dal_rtl8367c_svlan_l2mc2s_add + * Description: + * Add L2 multicast address to SVLAN + * Input: + * mac - L2 multicast address + * macMsk - L2 multicast address mask + * svid - SVLAN VID + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found. + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can set L2 Mutlicast to SVID configuration. If upstream packet is L2 multicast + * packet and DMAC is matched, ASIC will assign egress SVID to the packet. There are 32 + * SVLAN multicast configurations for IP and L2 multicast. + */ +extern rtk_api_ret_t dal_rtl8367c_svlan_l2mc2s_add(rtk_mac_t mac, rtk_mac_t macMsk, rtk_vlan_t svid); + +/* Function Name: + * dal_rtl8367c_svlan_l2mc2s_del + * Description: + * delete L2 multicast address to SVLAN + * Input: + * mac - L2 multicast address + * macMsk - L2 multicast address mask + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_OUT_OF_RANGE - input out of range. + * Note: + * The API can delete Mutlicast to SVID configuration. There are 32 SVLAN multicast configurations for IP and L2 multicast. + */ +extern rtk_api_ret_t dal_rtl8367c_svlan_l2mc2s_del(rtk_mac_t mac, rtk_mac_t macMsk); + +/* Function Name: + * dal_rtl8367c_svlan_l2mc2s_get + * Description: + * Get L2 multicast address to SVLAN + * Input: + * mac - L2 multicast address + * macMsk - L2 multicast address mask + * Output: + * pSvid - SVLAN VID + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_OUT_OF_RANGE - input out of range. + * Note: + * The API can get L2 mutlicast to SVID configuration. There are 32 SVLAN multicast configurations for IP and L2 multicast. + */ +extern rtk_api_ret_t dal_rtl8367c_svlan_l2mc2s_get(rtk_mac_t mac, rtk_mac_t macMsk, rtk_vlan_t *pSvid); + +/* Function Name: + * dal_rtl8367c_svlan_sp2c_add + * Description: + * Add system SP2C configuration + * Input: + * cvid - VLAN ID + * dst_port - Destination port of SVLAN to CVLAN configuration + * svid - SVLAN VID + * + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can add SVID & Destination Port to CVLAN configuration. The downstream frames with assigned + * SVID will be add C-tag with assigned CVID if the output port is the assigned destination port. + * There are 128 SP2C configurations. + */ +extern rtk_api_ret_t dal_rtl8367c_svlan_sp2c_add(rtk_vlan_t svid, rtk_port_t dst_port, rtk_vlan_t cvid); + +/* Function Name: + * dal_rtl8367c_svlan_sp2c_get + * Description: + * Get configure system SP2C content + * Input: + * svid - SVLAN VID + * dst_port - Destination port of SVLAN to CVLAN configuration + * Output: + * pCvid - VLAN ID + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * Note: + * The API can get SVID & Destination Port to CVLAN configuration. There are 128 SP2C configurations. + */ +extern rtk_api_ret_t dal_rtl8367c_svlan_sp2c_get(rtk_vlan_t svid, rtk_port_t dst_port, rtk_vlan_t *pCvid); + +/* Function Name: + * dal_rtl8367c_svlan_sp2c_del + * Description: + * Delete system SP2C configuration + * Input: + * svid - SVLAN VID + * dst_port - Destination port of SVLAN to CVLAN configuration + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_OUT_OF_RANGE - input out of range. + * Note: + * The API can delete SVID & Destination Port to CVLAN configuration. There are 128 SP2C configurations. + */ +extern rtk_api_ret_t dal_rtl8367c_svlan_sp2c_del(rtk_vlan_t svid, rtk_port_t dst_port); + + +/* Function Name: + * dal_rtl8367c_svlan_lookupType_set + * Description: + * Set lookup type of SVLAN + * Input: + * type - lookup type + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * Note: + * none + */ +extern rtk_api_ret_t dal_rtl8367c_svlan_lookupType_set(rtk_svlan_lookupType_t type); + +/* Function Name: + * dal_rtl8367c_svlan_lookupType_get + * Description: + * Get lookup type of SVLAN + * Input: + * pType - lookup type + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * Note: + * none + */ +extern rtk_api_ret_t dal_rtl8367c_svlan_lookupType_get(rtk_svlan_lookupType_t *pType); + +/* Function Name: + * dal_rtl8367c_svlan_trapPri_set + * Description: + * Set svlan trap priority + * Input: + * priority - priority for trap packets + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_QOS_INT_PRIORITY + * Note: + * None + */ +extern rtk_api_ret_t dal_rtl8367c_svlan_trapPri_set(rtk_pri_t priority); + +/* Function Name: + * dal_rtl8367c_svlan_trapPri_get + * Description: + * Get svlan trap priority + * Input: + * None + * Output: + * pPriority - priority for trap packets + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None + */ +extern rtk_api_ret_t dal_rtl8367c_svlan_trapPri_get(rtk_pri_t *pPriority); + +/* Function Name: + * dal_rtl8367c_svlan_unassign_action_set + * Description: + * Configure Action of upstream without svid assign action + * Input: + * action - Action for Un-assign + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can configure action of upstream Un-assign svid packet. If action is not + * trap to CPU, the port-based SVID sure be assign as system need + */ +extern rtk_api_ret_t dal_rtl8367c_svlan_unassign_action_set(rtk_svlan_unassign_action_t action); + +/* Function Name: + * dal_rtl8367c_svlan_unassign_action_get + * Description: + * Get action of upstream without svid assignment + * Input: + * None + * Output: + * pAction - Action for Un-assign + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * Note: + * None + */ +extern rtk_api_ret_t dal_rtl8367c_svlan_unassign_action_get(rtk_svlan_unassign_action_t *pAction); + + +/* Function Name: + * dal_rtl8367c_svlan_checkAndCreateMbr + * Description: + * Check and create Member configuration and return index + * Input: + * vid - VLAN id. + * Output: + * pIndex - Member configuration index + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_VLAN_VID - Invalid VLAN ID. + * RT_ERR_TBL_FULL - Member Configuration table full + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367c_svlan_checkAndCreateMbr(rtk_vlan_t vid, rtk_uint32 *pIndex); + + +#endif /* __DAL_RTL8367C_SVLAN_H__ */ diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_switch.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_switch.c new file mode 100644 index 00000000..249a9520 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_switch.c @@ -0,0 +1,784 @@ +/* + * Copyright (C) 2012 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : Definition of Switch Global API + * + * Feature : The file have include the following module and sub-modules + * (1) Switch parameter settings + * + */ + + +/* + * Include Files + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * Symbol Definition + */ + +/* + * Data Declaration + */ +static rtk_uint32 PatchChipData[210][2] = +{ + {0xa436, 0x8028}, {0xa438, 0x6800}, {0xb82e, 0x0001}, {0xa436, 0xb820}, {0xa438, 0x0090}, {0xa436, 0xa012}, {0xa438, 0x0000}, {0xa436, 0xa014}, {0xa438, 0x2c04}, {0xa438, 0x2c6c}, + {0xa438, 0x2c75}, {0xa438, 0x2c77}, {0xa438, 0x1414}, {0xa438, 0x1579}, {0xa438, 0x1536}, {0xa438, 0xc432}, {0xa438, 0x32c0}, {0xa438, 0x42d6}, {0xa438, 0x32b5}, {0xa438, 0x003e}, + {0xa438, 0x614c}, {0xa438, 0x1569}, {0xa438, 0xd705}, {0xa438, 0x318c}, {0xa438, 0x42d6}, {0xa438, 0xd702}, {0xa438, 0x31ef}, {0xa438, 0x42d6}, {0xa438, 0x629c}, {0xa438, 0x2c04}, + {0xa438, 0x653c}, {0xa438, 0x422a}, {0xa438, 0x5d83}, {0xa438, 0xd06a}, {0xa438, 0xd1b0}, {0xa438, 0x1536}, {0xa438, 0xc43a}, {0xa438, 0x32c0}, {0xa438, 0x42d6}, {0xa438, 0x32b5}, + {0xa438, 0x003e}, {0xa438, 0x314a}, {0xa438, 0x42fe}, {0xa438, 0x337b}, {0xa438, 0x02d6}, {0xa438, 0x3063}, {0xa438, 0x0c1b}, {0xa438, 0x22fe}, {0xa438, 0xc435}, {0xa438, 0xd0be}, + {0xa438, 0xd1f7}, {0xa438, 0xe0f0}, {0xa438, 0x1a40}, {0xa438, 0xa320}, {0xa438, 0xd702}, {0xa438, 0x154a}, {0xa438, 0xc434}, {0xa438, 0x32c0}, {0xa438, 0x42d6}, {0xa438, 0x32b5}, + {0xa438, 0x003e}, {0xa438, 0x60ec}, {0xa438, 0x1569}, {0xa438, 0xd705}, {0xa438, 0x619f}, {0xa438, 0xd702}, {0xa438, 0x414f}, {0xa438, 0x2c2e}, {0xa438, 0x610a}, {0xa438, 0xd705}, + {0xa438, 0x5e1f}, {0xa438, 0xc43f}, {0xa438, 0xc88b}, {0xa438, 0xd702}, {0xa438, 0x7fe0}, {0xa438, 0x22f3}, {0xa438, 0xd0a0}, {0xa438, 0xd1b2}, {0xa438, 0xd0c3}, {0xa438, 0xd1c3}, + {0xa438, 0x8d01}, {0xa438, 0x1536}, {0xa438, 0xc438}, {0xa438, 0xe0f0}, {0xa438, 0x1a80}, {0xa438, 0xd706}, {0xa438, 0x60c0}, {0xa438, 0xd710}, {0xa438, 0x409e}, {0xa438, 0xa804}, + {0xa438, 0xad01}, {0xa438, 0x8804}, {0xa438, 0xd702}, {0xa438, 0x32c0}, {0xa438, 0x42d6}, {0xa438, 0x32b5}, {0xa438, 0x003e}, {0xa438, 0x405b}, {0xa438, 0x1576}, {0xa438, 0x7c9c}, + {0xa438, 0x60ec}, {0xa438, 0x1569}, {0xa438, 0xd702}, {0xa438, 0x5d43}, {0xa438, 0x31ef}, {0xa438, 0x02fe}, {0xa438, 0x22d6}, {0xa438, 0x590a}, {0xa438, 0xd706}, {0xa438, 0x5c80}, + {0xa438, 0xd702}, {0xa438, 0x5c44}, {0xa438, 0x3063}, {0xa438, 0x02d6}, {0xa438, 0x5be2}, {0xa438, 0x22fb}, {0xa438, 0xa240}, {0xa438, 0xa104}, {0xa438, 0x8c03}, {0xa438, 0x8178}, + {0xa438, 0xd701}, {0xa438, 0x31ad}, {0xa438, 0x4917}, {0xa438, 0x8102}, {0xa438, 0x2917}, {0xa438, 0xc302}, {0xa438, 0x268a}, {0xa436, 0xA01A}, {0xa438, 0x0000}, {0xa436, 0xA006}, + {0xa438, 0x0fff}, {0xa436, 0xA004}, {0xa438, 0x0689}, {0xa436, 0xA002}, {0xa438, 0x0911}, {0xa436, 0xA000}, {0xa438, 0x7302}, {0xa436, 0xB820}, {0xa438, 0x0010}, {0xa436, 0x8412}, + {0xa438, 0xaf84}, {0xa438, 0x1eaf}, {0xa438, 0x8427}, {0xa438, 0xaf84}, {0xa438, 0x27af}, {0xa438, 0x8427}, {0xa438, 0x0251}, {0xa438, 0x6802}, {0xa438, 0x8427}, {0xa438, 0xaf04}, + {0xa438, 0x0af8}, {0xa438, 0xf9bf}, {0xa438, 0x5581}, {0xa438, 0x0255}, {0xa438, 0x27ef}, {0xa438, 0x310d}, {0xa438, 0x345b}, {0xa438, 0x0fa3}, {0xa438, 0x032a}, {0xa438, 0xe087}, + {0xa438, 0xffac}, {0xa438, 0x2040}, {0xa438, 0xbf56}, {0xa438, 0x7402}, {0xa438, 0x5527}, {0xa438, 0xef31}, {0xa438, 0xef20}, {0xa438, 0xe787}, {0xa438, 0xfee6}, {0xa438, 0x87fd}, + {0xa438, 0xd488}, {0xa438, 0x88bf}, {0xa438, 0x5674}, {0xa438, 0x0254}, {0xa438, 0xe3e0}, {0xa438, 0x87ff}, {0xa438, 0xf720}, {0xa438, 0xe487}, {0xa438, 0xffaf}, {0xa438, 0x847e}, + {0xa438, 0xe087}, {0xa438, 0xffad}, {0xa438, 0x2016}, {0xa438, 0xe387}, {0xa438, 0xfee2}, {0xa438, 0x87fd}, {0xa438, 0xef45}, {0xa438, 0xbf56}, {0xa438, 0x7402}, {0xa438, 0x54e3}, + {0xa438, 0xe087}, {0xa438, 0xfff6}, {0xa438, 0x20e4}, {0xa438, 0x87ff}, {0xa438, 0xfdfc}, {0xa438, 0x0400}, {0xa436, 0xb818}, {0xa438, 0x0407}, {0xa436, 0xb81a}, {0xa438, 0xfffd}, + {0xa436, 0xb81c}, {0xa438, 0xfffd}, {0xa436, 0xb81e}, {0xa438, 0xfffd}, {0xa436, 0xb832}, {0xa438, 0x0001}, {0xb820, 0x0000}, {0xb82e, 0x0000}, {0xa436, 0x8028}, {0xa438, 0x0000} +}; + + +static rtk_api_ret_t _dal_switch_init_8367c(void) +{ + rtk_port_t port; + rtk_uint32 retVal; + rtk_uint32 regData; + rtk_uint32 regValue; + + if( (retVal = rtl8367c_setAsicReg(0x13c2, 0x0249)) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367c_getAsicReg(0x1301, ®Value)) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367c_setAsicReg(0x13c2, 0x0000)) != RT_ERR_OK) + return retVal; + + RTK_SCAN_ALL_LOG_PORT(port) + { + if(rtk_switch_isUtpPort(port) == RT_ERR_OK) + { + if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_PORT0_EEECFG + (0x20 * port), RTL8367C_PORT0_EEECFG_EEE_100M_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_PORT0_EEECFG + (0x20 * port), RTL8367C_PORT0_EEECFG_EEE_GIGA_500M_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_PORT0_EEECFG + (0x20 * port), RTL8367C_PORT0_EEECFG_EEE_TX_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_PORT0_EEECFG + (0x20 * port), RTL8367C_PORT0_EEECFG_EEE_RX_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xA428, ®Data)) != RT_ERR_OK) + return retVal; + + regData &= ~(0x0200); + if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xA428, regData)) != RT_ERR_OK) + return retVal; + + if((regValue & 0x00F0) == 0x00A0) + { + if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xA5D0, ®Data)) != RT_ERR_OK) + return retVal; + + regData |= 0x0006; + if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xA5D0, regData)) != RT_ERR_OK) + return retVal; + } + } + } + + if((retVal = rtl8367c_setAsicReg(RTL8367C_REG_UTP_FIB_DET, 0x15BB)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicReg(0x1303, 0x06D6)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicReg(0x1304, 0x0700)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicReg(0x13E2, 0x003F)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicReg(0x13F9, 0x0090)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicReg(0x121e, 0x03CA)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicReg(0x1233, 0x0352)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicReg(0x1237, 0x00a0)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicReg(0x123a, 0x0030)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicReg(0x1239, 0x0084)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicReg(0x0301, 0x1000)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicReg(0x1349, 0x001F)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicRegBit(0x18e0, 0, 0)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicRegBit(0x122b, 14, 1)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicRegBits(0x1305, 0xC000, 3)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicRegBit(0x13f0, 0, 0)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicReg(0x1722, 0x1158)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +static rtk_api_ret_t _dal_switch_init_8370b(void) +{ + ret_t retVal; + rtk_uint32 regData, tmp = 0; + rtk_uint32 i, prf, counter; + rtk_uint32 long_link[8] = {0x0210, 0x03e8, 0x0218, 0x03f0, 0x0220, 0x03f8, 0x0208, 0x03e0 }; + + prf = 0; + + if((retVal = rtl8367c_setAsicRegBits(0x1205, 0x0300, 3)) != RT_ERR_OK) + return retVal; + + + for(i=0; i<8; i++) + { + if ((retVal = rtl8367c_getAsicPHYOCPReg(i, 0xa420, ®Data)) != RT_ERR_OK) + return retVal; + tmp = regData & 0x7 ; + if(tmp == 0x3) + { + prf = 1; + if((retVal = rtl8367c_setAsicPHYOCPReg(i, 0xb83e, 0x6fa9)) != RT_ERR_OK) + return retVal; + if((retVal = rtl8367c_setAsicPHYOCPReg(i, 0xb840, 0xa9)) != RT_ERR_OK) + return retVal; + for(counter = 0; counter < 10000; counter++); //delay + + if ((retVal = rtl8367c_getAsicPHYOCPReg(i, 0xb820, ®Data)) != RT_ERR_OK) + return retVal; + tmp = regData | 0x10; + if ((retVal = rtl8367c_setAsicPHYOCPReg(i, 0xb820, tmp)) != RT_ERR_OK) + return retVal; + for(counter = 0; counter < 10000; counter++); //delay + counter = 0; + do{ + counter = counter + 1; + if ((retVal = rtl8367c_getAsicPHYOCPReg(i, 0xb800, ®Data)) != RT_ERR_OK) + return retVal; + tmp = regData & 0x40; + if(tmp != 0) + break; + } while (counter < 20); //Wait for patch ready = 1... + } + } + if ((retVal = rtl8367c_getAsicReg(0x1d01, ®Data)) != RT_ERR_OK) + return retVal; + tmp = regData; + tmp = tmp | 0x3BE0; /*Broadcast port enable*/ + tmp = tmp & 0xFFE0; /*Phy_id = 0 */ + if((retVal = rtl8367c_setAsicReg(0x1d01, tmp)) != RT_ERR_OK) + return retVal; + + for(i=0;i < 210; i++) + { + if((retVal = rtl8367c_setAsicPHYOCPReg(0, PatchChipData[i][0], PatchChipData[i][1])) != RT_ERR_OK) + return retVal; + } + + if((retVal = rtl8367c_setAsicReg(0x1d01, regData)) != RT_ERR_OK) + return retVal; + + for(i=0; i < 8; i++) + { + if((retVal = rtl8367c_setAsicPHYOCPReg(i, 0xa4b4, long_link[i])) != RT_ERR_OK) + return retVal; + } + + if(prf == 0x1) + { + for(i=0; i<8; i++) + { + if ((retVal = rtl8367c_getAsicPHYOCPReg(i, 0xb820, ®Data)) != RT_ERR_OK) + return retVal; + tmp = regData & 0xFFEF; + if ((retVal = rtl8367c_setAsicPHYOCPReg(i, 0xb820, tmp)) != RT_ERR_OK) + return retVal; + + for(counter = 0; counter < 10000; counter++); //delay + + counter = 0; + do{ + counter = counter + 1; + if ((retVal = rtl8367c_getAsicPHYOCPReg(i, 0xb800, ®Data)) != RT_ERR_OK) + return retVal; + tmp = regData & 0x40; + if( tmp == 0 ) + break; + } while (counter < 20); //Wait for patch ready = 1... + if ((retVal = rtl8367c_setAsicPHYOCPReg(i, 0xb83e, 0x6f48)) != RT_ERR_OK) + return retVal; + if ((retVal = rtl8367c_setAsicPHYOCPReg(i, 0xb840, 0xfa)) != RT_ERR_OK) + return retVal; + } + } + + /*Check phy link status*/ + for(i=0; i<8; i++) + { + if ((retVal = rtl8367c_getAsicPHYOCPReg(i, 0xa400, ®Data)) != RT_ERR_OK) + return retVal; + tmp = regData & 0x800; + if(tmp == 0x0) + { + tmp = regData | 0x200; + if ((retVal = rtl8367c_setAsicPHYOCPReg(i, 0xa400, tmp)) != RT_ERR_OK) + return retVal; + } + } + + for(counter = 0; counter < 10000; counter++); //delay + + return RT_ERR_OK; +} + +static rtk_api_ret_t _dal_switch_init_8364b(void) +{ + ret_t retVal; + rtk_uint32 regData; + + if ((retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_RMA_CTRL02, RTL8367C_RMA_CTRL02_OPERATION_MASK, 0)) != RT_ERR_OK) + return retVal; + + /*enable EEE, include mac & phy*/ + + if ((retVal = rtl8367c_setAsicRegBits(0x38, 0x300, 3)) != RT_ERR_OK) + return retVal; + if ((retVal = rtl8367c_setAsicRegBits(0x78, 0x300, 3)) != RT_ERR_OK) + return retVal; + if ((retVal = rtl8367c_setAsicRegBits(0xd8, 0x300, 0)) != RT_ERR_OK) + return retVal; + if ((retVal = rtl8367c_setAsicRegBits(0xf8, 0x300, 0)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicPHYOCPReg(1, 0xa5d0, 6)) != RT_ERR_OK) + return retVal; + if ((retVal = rtl8367c_setAsicPHYOCPReg(3, 0xa5d0, 6)) != RT_ERR_OK) + return retVal; + + /*PAD para*/ + + /*EXT1 PAD Para*/ + if ((retVal = rtl8367c_getAsicReg(0x1303, ®Data)) != RT_ERR_OK) + return retVal; + regData &= 0xFFFFFFFE; + regData |= 0x250; + if((retVal = rtl8367c_setAsicReg(0x1303, regData)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicRegBits(0x1304, 0x7000, 0)) != RT_ERR_OK) + return retVal; + if ((retVal = rtl8367c_setAsicRegBits(0x1304, 0x700, 7)) != RT_ERR_OK) + return retVal; + if ((retVal = rtl8367c_setAsicRegBits(0x13f9, 0x38, 0)) != RT_ERR_OK) + return retVal; + + /*EXT2 PAD Para*/ + if ((retVal = rtl8367c_setAsicRegBit(0x1303, 10, 1)) != RT_ERR_OK) + return retVal; + if ((retVal = rtl8367c_setAsicRegBits(0x13E2, 0x1ff, 0x26)) != RT_ERR_OK) + return retVal; + if ((retVal = rtl8367c_setAsicRegBits(0x13f9, 0x1c0, 0)) != RT_ERR_OK) + return retVal; + + + /*SDS PATCH*/ + /*SP_CFG_EN_LINK_FIB1G*/ + if((retVal = rtl8367c_getAsicSdsReg(0, 4, 0, ®Data)) != RT_ERR_OK) + return retVal; + regData |= 0x4; + if((retVal = rtl8367c_setAsicSdsReg(0,4,0, regData)) != RT_ERR_OK) + return retVal; + + /*FIB100 Down-speed*/ + if((retVal = rtl8367c_getAsicSdsReg(0, 1, 0, ®Data)) != RT_ERR_OK) + return retVal; + regData |= 0x20; + if((retVal = rtl8367c_setAsicSdsReg(0,1,0, regData)) != RT_ERR_OK) + return retVal; + + /*gphy endurance crc patch*/ + if((retVal = rtl8367c_setAsicPHYSram(1, 0x8016, 0xb00)) != RT_ERR_OK) + return retVal; + if((retVal = rtl8367c_setAsicPHYSram(3, 0x8016, 0xb00)) != RT_ERR_OK) + return retVal; + if((retVal = rtl8367c_setAsicPHYSram(1, 0x83a7, 0x160c)) != RT_ERR_OK) + return retVal; + if((retVal = rtl8367c_setAsicPHYSram(3, 0x83a7, 0x160c)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +static rtk_api_ret_t _dal_switch_init_8363sc_vb(void) +{ + + ret_t retVal; + rtk_uint32 regData; + + if ((retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_RMA_CTRL02, RTL8367C_RMA_CTRL02_OPERATION_MASK, 0)) != RT_ERR_OK) + return retVal; + + /*enable EEE, include mac & phy*/ + + if ((retVal = rtl8367c_setAsicRegBits(0x38, 0x300, 3)) != RT_ERR_OK) + return retVal; + if ((retVal = rtl8367c_setAsicRegBits(0x78, 0x300, 3)) != RT_ERR_OK) + return retVal; + if ((retVal = rtl8367c_setAsicRegBits(0xd8, 0x300, 0)) != RT_ERR_OK) + return retVal; + if ((retVal = rtl8367c_setAsicRegBits(0xf8, 0x300, 0)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicPHYOCPReg(1, 0xa5d0, 6)) != RT_ERR_OK) + return retVal; + if ((retVal = rtl8367c_setAsicPHYOCPReg(3, 0xa5d0, 6)) != RT_ERR_OK) + return retVal; + + /*PAD para*/ + + /*EXT1 PAD Para*/ + if ((retVal = rtl8367c_getAsicReg(0x1303, ®Data)) != RT_ERR_OK) + return retVal; + regData &= 0xFFFFFFFE; + regData |= 0x250; + if((retVal = rtl8367c_setAsicReg(0x1303, regData)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicRegBits(0x1304, 0x7000, 0)) != RT_ERR_OK) + return retVal; + if ((retVal = rtl8367c_setAsicRegBits(0x1304, 0x700, 7)) != RT_ERR_OK) + return retVal; + if ((retVal = rtl8367c_setAsicRegBits(0x13f9, 0x38, 0)) != RT_ERR_OK) + return retVal; + + /*EXT2 PAD Para*/ + if ((retVal = rtl8367c_setAsicRegBit(0x1303, 10, 1)) != RT_ERR_OK) + return retVal; + if ((retVal = rtl8367c_setAsicRegBits(0x13E2, 0x1ff, 0x26)) != RT_ERR_OK) + return retVal; + if ((retVal = rtl8367c_setAsicRegBits(0x13f9, 0x1c0, 0)) != RT_ERR_OK) + return retVal; + + + /*SDS PATCH*/ + /*SP_CFG_EN_LINK_FIB1G*/ + if((retVal = rtl8367c_getAsicSdsReg(0, 4, 0, ®Data)) != RT_ERR_OK) + return retVal; + regData |= 0x4; + if((retVal = rtl8367c_setAsicSdsReg(0,4,0, regData)) != RT_ERR_OK) + return retVal; + + /*FIB100 Down-speed*/ + if((retVal = rtl8367c_getAsicSdsReg(0, 1, 0, ®Data)) != RT_ERR_OK) + return retVal; + regData |= 0x20; + if((retVal = rtl8367c_setAsicSdsReg(0,1,0, regData)) != RT_ERR_OK) + return retVal; + + /*gphy endurance crc patch*/ + if((retVal = rtl8367c_setAsicPHYSram(1, 0x8016, 0xb00)) != RT_ERR_OK) + return retVal; + if((retVal = rtl8367c_setAsicPHYSram(3, 0x8016, 0xb00)) != RT_ERR_OK) + return retVal; + if((retVal = rtl8367c_setAsicPHYSram(1, 0x83a7, 0x160c)) != RT_ERR_OK) + return retVal; + if((retVal = rtl8367c_setAsicPHYSram(3, 0x83a7, 0x160c)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* + * Function Declaration + */ +/* Function Name: + * dal_rtl8367c_switch_init + * Description: + * Set chip to default configuration enviroment + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set chip registers to default configuration for different release chip model. + */ +rtk_api_ret_t dal_rtl8367c_switch_init(void) +{ + rtk_int32 retVal; + rtl8367c_rma_t rmaCfg; + + /* Initial */ + switch(rtk_switch_chipType_get()) + { + case CHIP_RTL8367C: + if((retVal = _dal_switch_init_8367c()) != RT_ERR_OK) + return retVal; + break; + case CHIP_RTL8370B: + if((retVal = _dal_switch_init_8370b()) != RT_ERR_OK) + return retVal; + break; + case CHIP_RTL8364B: + if((retVal = _dal_switch_init_8364b()) != RT_ERR_OK) + return retVal; + break; + case CHIP_RTL8363SC_VB: + if((retVal = _dal_switch_init_8363sc_vb()) != RT_ERR_OK) + return retVal; + break; + default: + return RT_ERR_CHIP_NOT_FOUND; + } + + /* Set Old max packet length to 16K */ + if((retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_MAX_LENGTH_LIMINT_IPG, RTL8367C_MAX_LENTH_CTRL_MASK, 3)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_MAX_LEN_RX_TX, RTL8367C_MAX_LEN_RX_TX_MASK, 3)) != RT_ERR_OK) + return retVal; + + /* ACL Mode */ + if((retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_ACL_ACCESS_MODE, RTL8367C_ACL_ACCESS_MODE_MASK, 1)) != RT_ERR_OK) + return retVal; + + /* Max rate */ + if((retVal = rtl8367c_setAsicPortIngressBandwidth(rtk_switch_port_L2P_get(EXT_PORT0), RTL8367C_QOS_RATE_INPUT_MAX_HSG>>3, DISABLED, ENABLED)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicPortEgressRate(rtk_switch_port_L2P_get(EXT_PORT0), RTL8367C_QOS_RATE_INPUT_MAX_HSG>>3)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicPortEgressRateIfg(ENABLED)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicReg(0x03fa, 0x0007)) != RT_ERR_OK) + return retVal; + + /* Change unknown DA to per port setting */ + if((retVal = rtl8367c_setAsicRegBits(RTL8367C_PORT_SECURIT_CTRL_REG, RTL8367C_UNKNOWN_UNICAST_DA_BEHAVE_MASK, 3)) != RT_ERR_OK) + return retVal; + + /* LUT lookup OP = 1 */ + if ((retVal = rtl8367c_setAsicLutIpLookupMethod(1))!=RT_ERR_OK) + return retVal; + + /* Set RMA */ + rmaCfg.portiso_leaky = 0; + rmaCfg.vlan_leaky = 0; + rmaCfg.keep_format = 0; + rmaCfg.trap_priority = 0; + rmaCfg.discard_storm_filter = 0; + rmaCfg.operation = 0; + if ((retVal = rtl8367c_setAsicRma(2, &rmaCfg))!=RT_ERR_OK) + return retVal; + + /* Enable TX Mirror isolation leaky */ + if ((retVal = rtl8367c_setAsicPortMirrorIsolationTxLeaky(ENABLED)) != RT_ERR_OK) + return retVal; + + /* INT EN */ + if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_IO_MISC_FUNC, RTL8367C_INT_EN_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_switch_portMaxPktLen_set + * Description: + * Set Max packet length + * Input: + * port - Port ID + * speed - Speed + * cfgId - Configuration ID + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + */ +rtk_api_ret_t dal_rtl8367c_switch_portMaxPktLen_set(rtk_port_t port, rtk_switch_maxPktLen_linkSpeed_t speed, rtk_uint32 cfgId) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if(speed >= MAXPKTLEN_LINK_SPEED_END) + return RT_ERR_INPUT; + + if(cfgId > MAXPKTLEN_CFG_ID_MAX) + return RT_ERR_INPUT; + + if((retVal = rtl8367c_setAsicMaxLength(rtk_switch_port_L2P_get(port), (rtk_uint32)speed, cfgId)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_switch_portMaxPktLen_get + * Description: + * Get Max packet length + * Input: + * port - Port ID + * speed - Speed + * Output: + * pCfgId - Configuration ID + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + */ +rtk_api_ret_t dal_rtl8367c_switch_portMaxPktLen_get(rtk_port_t port, rtk_switch_maxPktLen_linkSpeed_t speed, rtk_uint32 *pCfgId) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if(speed >= MAXPKTLEN_LINK_SPEED_END) + return RT_ERR_INPUT; + + if(NULL == pCfgId) + return RT_ERR_NULL_POINTER; + + if((retVal = rtl8367c_getAsicMaxLength(rtk_switch_port_L2P_get(port), (rtk_uint32)speed, pCfgId)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8367c_switch_maxPktLenCfg_set + * Description: + * Set Max packet length configuration + * Input: + * cfgId - Configuration ID + * pktLen - Max packet length + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + */ +rtk_api_ret_t dal_rtl8367c_switch_maxPktLenCfg_set(rtk_uint32 cfgId, rtk_uint32 pktLen) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(cfgId > MAXPKTLEN_CFG_ID_MAX) + return RT_ERR_INPUT; + + if(pktLen > RTK_SWITCH_MAX_PKTLEN) + return RT_ERR_INPUT; + + if((retVal = rtl8367c_setAsicMaxLengthCfg(cfgId, pktLen)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_switch_maxPktLenCfg_get + * Description: + * Get Max packet length configuration + * Input: + * cfgId - Configuration ID + * pPktLen - Max packet length + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + */ +rtk_api_ret_t dal_rtl8367c_switch_maxPktLenCfg_get(rtk_uint32 cfgId, rtk_uint32 *pPktLen) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(cfgId > MAXPKTLEN_CFG_ID_MAX) + return RT_ERR_INPUT; + + if(NULL == pPktLen) + return RT_ERR_NULL_POINTER; + + if((retVal = rtl8367c_getAsicMaxLengthCfg(cfgId, pPktLen)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_switch_greenEthernet_set + * Description: + * Set all Ports Green Ethernet state. + * Input: + * enable - Green Ethernet state. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * This API can set all Ports Green Ethernet state. + * The configuration is as following: + * - DISABLE + * - ENABLE + */ +rtk_api_ret_t dal_rtl8367c_switch_greenEthernet_set(rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + rtk_uint32 port; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + RTK_SCAN_ALL_LOG_PORT(port) + { + if(rtk_switch_isUtpPort(port) == RT_ERR_OK) + { + if ((retVal = rtl8367c_setAsicPowerSaving(rtk_switch_port_L2P_get(port),enable))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicGreenEthernet(rtk_switch_port_L2P_get(port), enable))!=RT_ERR_OK) + return retVal; + } + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_switch_greenEthernet_get + * Description: + * Get all Ports Green Ethernet state. + * Input: + * None + * Output: + * pEnable - Green Ethernet state. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API can get Green Ethernet state. + */ +rtk_api_ret_t dal_rtl8367c_switch_greenEthernet_get(rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + rtk_uint32 port; + rtk_uint32 state; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + RTK_SCAN_ALL_LOG_PORT(port) + { + if(rtk_switch_isUtpPort(port) == RT_ERR_OK) + { + if ((retVal = rtl8367c_getAsicPowerSaving(rtk_switch_port_L2P_get(port), &state))!=RT_ERR_OK) + return retVal; + + if(state == DISABLED) + { + *pEnable = DISABLED; + return RT_ERR_OK; + } + + if ((retVal = rtl8367c_getAsicGreenEthernet(rtk_switch_port_L2P_get(port), &state))!=RT_ERR_OK) + return retVal; + + if(state == DISABLED) + { + *pEnable = DISABLED; + return RT_ERR_OK; + } + } + } + + *pEnable = ENABLED; + return RT_ERR_OK; +} + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_switch.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_switch.h new file mode 100644 index 00000000..42669b4a --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_switch.h @@ -0,0 +1,182 @@ + +/* + * Copyright (C) 2012 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : Definition of Switch Global API + * + * Feature : The file have include the following module and sub-modules + * (1) Switch parameter settings + * + */ + +#ifndef __DAL_RTL8367C_SWITCH_H__ +#define __DAL_RTL8367C_SWITCH_H__ + +/* + * Include Files + */ +#include +#include + +/* + * Symbol Definition + */ + +/* + * Data Declaration + */ + +/* + * Function Declaration + */ + +/* Module Name : Switch */ +/* Sub-module Name: Switch parameter settings */ + +/* Function Name: + * dal_rtl8367c_switch_init + * Description: + * Initialize switch module of the specified device. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * Note: + * Module must be initialized before using all of APIs in this module + */ +extern rtk_api_ret_t +dal_rtl8367c_switch_init(void); + +/* Module Name : Switch */ +/* Sub-module Name: Switch parameter settings */ +/* Function Name: + * dal_rtl8367c_switch_portMaxPktLen_set + * Description: + * Set Max packet length + * Input: + * port - Port ID + * speed - Speed + * cfgId - Configuration ID + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + */ +extern rtk_api_ret_t +dal_rtl8367c_switch_portMaxPktLen_set(rtk_port_t port, rtk_switch_maxPktLen_linkSpeed_t speed, rtk_uint32 cfgId); + +/* Function Name: + * dal_rtl8367c_switch_portMaxPktLen_get + * Description: + * Get Max packet length + * Input: + * port - Port ID + * speed - Speed + * Output: + * pCfgId - Configuration ID + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + */ +extern rtk_api_ret_t +dal_rtl8367c_switch_portMaxPktLen_get(rtk_port_t port, rtk_switch_maxPktLen_linkSpeed_t speed, rtk_uint32 *pCfgId); + +/* Function Name: + * dal_rtl8367c_switch_maxPktLenCfg_set + * Description: + * Set Max packet length configuration + * Input: + * cfgId - Configuration ID + * pktLen - Max packet length + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + */ +extern rtk_api_ret_t +dal_rtl8367c_switch_maxPktLenCfg_set(rtk_uint32 cfgId, rtk_uint32 pktLen); + +/* Function Name: + * dal_rtl8367c_switch_maxPktLenCfg_get + * Description: + * Get Max packet length configuration + * Input: + * cfgId - Configuration ID + * pPktLen - Max packet length + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + */ +extern rtk_api_ret_t +dal_rtl8367c_switch_maxPktLenCfg_get(rtk_uint32 cfgId, rtk_uint32 *pPktLen); + +/* Function Name: + * dal_rtl8367c_switch_greenEthernet_set + * Description: + * Set all Ports Green Ethernet state. + * Input: + * enable - Green Ethernet state. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * This API can set all Ports Green Ethernet state. + * The configuration is as following: + * - DISABLE + * - ENABLE + */ +extern rtk_api_ret_t +dal_rtl8367c_switch_greenEthernet_set(rtk_enable_t enable); + +/* Function Name: + * dal_rtl8367c_switch_greenEthernet_get + * Description: + * Get all Ports Green Ethernet state. + * Input: + * None + * Output: + * pEnable - Green Ethernet state. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API can get Green Ethernet state. + */ +extern rtk_api_ret_t +dal_rtl8367c_switch_greenEthernet_get(rtk_enable_t *pEnable); + + +#endif /* __DAL_RTL8367C_SWITCH_H__ */ + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_trap.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_trap.c new file mode 100644 index 00000000..c5f842f4 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_trap.c @@ -0,0 +1,1304 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8367C + * Feature : Here is a list of all functions and variables in Trap module. + * + */ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Function Name: + * rtk_trap_unknownUnicastPktAction_set + * Description: + * Set unknown unicast packet action configuration. + * Input: + * port - ingress port ID for unknown unicast packet + * ucast_action - Unknown unicast action. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid action. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can set unknown unicast packet action configuration. + * The unknown unicast action is as following: + * - UCAST_ACTION_FORWARD_PMASK + * - UCAST_ACTION_DROP + * - UCAST_ACTION_TRAP2CPU + * - UCAST_ACTION_FLOODING + */ +rtk_api_ret_t dal_rtl8367c_trap_unknownUnicastPktAction_set(rtk_port_t port, rtk_trap_ucast_action_t ucast_action) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* check port valid */ + RTK_CHK_PORT_VALID(port); + + if (ucast_action >= UCAST_ACTION_COPY28051) + return RT_ERR_INPUT; + + if ((retVal = rtl8367c_setAsicPortUnknownDaBehavior(rtk_switch_port_L2P_get(port), ucast_action)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_trap_unknownUnicastPktAction_get + * Description: + * Get unknown unicast packet action configuration. + * Input: + * port - ingress port ID for unknown unicast packet + * Output: + * pUcast_action - Unknown unicast action. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid action. + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * This API can get unknown unicast packet action configuration. + * The unknown unicast action is as following: + * - UCAST_ACTION_FORWARD_PMASK + * - UCAST_ACTION_DROP + * - UCAST_ACTION_TRAP2CPU + * - UCAST_ACTION_FLOODING + */ +rtk_api_ret_t dal_rtl8367c_trap_unknownUnicastPktAction_get(rtk_port_t port, rtk_trap_ucast_action_t *pUcast_action) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* check port valid */ + RTK_CHK_PORT_VALID(port); + + if (NULL == pUcast_action) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicPortUnknownDaBehavior(rtk_switch_port_L2P_get(port), pUcast_action)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_trap_unknownMacPktAction_set + * Description: + * Set unknown source MAC packet action configuration. + * Input: + * ucast_action - Unknown source MAC action. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid action. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can set unknown unicast packet action configuration. + * The unknown unicast action is as following: + * - UCAST_ACTION_FORWARD_PMASK + * - UCAST_ACTION_DROP + * - UCAST_ACTION_TRAP2CPU + * - UCAST_ACTION_COPY28051 + */ +rtk_api_ret_t dal_rtl8367c_trap_unknownMacPktAction_set(rtk_trap_ucast_action_t ucast_action) +{ + rtk_api_ret_t retVal; + rtk_uint32 behavior; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + switch (ucast_action) + { + case UCAST_ACTION_FORWARD_PMASK: + behavior = L2_BEHAVE_SA_FLOODING; + break; + case UCAST_ACTION_DROP: + behavior = L2_BEHAVE_SA_DROP; + break; + case UCAST_ACTION_TRAP2CPU: + behavior = L2_BEHAVE_SA_TRAP; + break; + case UCAST_ACTION_COPY28051: + behavior = L2_BEHAVE_SA_COPY28051; + break; + default: + return RT_ERR_INPUT; + break; + } + + if ((retVal = rtl8367c_setAsicPortUnknownSaBehavior(behavior)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_trap_unknownMacPktAction_get + * Description: + * Get unknown source MAC packet action configuration. + * Input: + * None. + * Output: + * pUcast_action - Unknown source MAC action. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Null Pointer. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * + */ +rtk_api_ret_t dal_rtl8367c_trap_unknownMacPktAction_get(rtk_trap_ucast_action_t *pUcast_action) +{ + rtk_api_ret_t retVal; + rtk_uint32 behavior; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pUcast_action) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicPortUnknownSaBehavior(&behavior)) != RT_ERR_OK) + return retVal; + + switch (behavior) + { + case L2_BEHAVE_SA_FLOODING: + *pUcast_action = UCAST_ACTION_FORWARD_PMASK; + break; + case L2_BEHAVE_SA_DROP: + *pUcast_action = UCAST_ACTION_DROP; + break; + case L2_BEHAVE_SA_TRAP: + *pUcast_action = UCAST_ACTION_TRAP2CPU; + break; + case L2_BEHAVE_SA_COPY28051: + *pUcast_action = UCAST_ACTION_COPY28051; + break; + default: + return RT_ERR_FAILED; + break; + } + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_trap_unmatchMacPktAction_set + * Description: + * Set unmatch source MAC packet action configuration. + * Input: + * ucast_action - Unknown source MAC action. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid action. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can set unknown unicast packet action configuration. + * The unknown unicast action is as following: + * - UCAST_ACTION_FORWARD_PMASK + * - UCAST_ACTION_DROP + * - UCAST_ACTION_TRAP2CPU + * - UCAST_ACTION_COPY28051 + */ +rtk_api_ret_t dal_rtl8367c_trap_unmatchMacPktAction_set(rtk_trap_ucast_action_t ucast_action) +{ + rtk_api_ret_t retVal; + rtk_uint32 behavior; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + switch (ucast_action) + { + case UCAST_ACTION_FORWARD_PMASK: + behavior = L2_BEHAVE_SA_FLOODING; + break; + case UCAST_ACTION_DROP: + behavior = L2_BEHAVE_SA_DROP; + break; + case UCAST_ACTION_TRAP2CPU: + behavior = L2_BEHAVE_SA_TRAP; + break; + case UCAST_ACTION_COPY28051: + behavior = L2_BEHAVE_SA_COPY28051; + break; + default: + return RT_ERR_INPUT; + break; + } + + if ((retVal = rtl8367c_setAsicPortUnmatchedSaBehavior(behavior)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_trap_unmatchMacPktAction_get + * Description: + * Get unmatch source MAC packet action configuration. + * Input: + * None. + * Output: + * pUcast_action - Unknown source MAC action. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid action. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can set unknown unicast packet action configuration. + * The unknown unicast action is as following: + * - UCAST_ACTION_FORWARD_PMASK + * - UCAST_ACTION_DROP + * - UCAST_ACTION_TRAP2CPU + */ +rtk_api_ret_t dal_rtl8367c_trap_unmatchMacPktAction_get(rtk_trap_ucast_action_t *pUcast_action) +{ + rtk_api_ret_t retVal; + rtk_uint32 behavior; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pUcast_action) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicPortUnmatchedSaBehavior(&behavior)) != RT_ERR_OK) + return retVal; + + switch (behavior) + { + case L2_BEHAVE_SA_FLOODING: + *pUcast_action = UCAST_ACTION_FORWARD_PMASK; + break; + case L2_BEHAVE_SA_DROP: + *pUcast_action = UCAST_ACTION_DROP; + break; + case L2_BEHAVE_SA_TRAP: + *pUcast_action = UCAST_ACTION_TRAP2CPU; + break; + case L2_BEHAVE_SA_COPY28051: + *pUcast_action = UCAST_ACTION_COPY28051; + break; + default: + return RT_ERR_FAILED; + break; + } + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_trap_unmatchMacMoving_set + * Description: + * Set unmatch source MAC packet moving state. + * Input: + * port - Port ID. + * enable - ENABLED: allow SA moving, DISABLE: don't allow SA moving. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid action. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + */ +rtk_api_ret_t dal_rtl8367c_trap_unmatchMacMoving_set(rtk_port_t port, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* check port valid */ + RTK_CHK_PORT_VALID(port); + + if(enable >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if ((retVal = rtl8367c_setAsicPortUnmatchedSaMoving(rtk_switch_port_L2P_get(port), enable)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_trap_unmatchMacMoving_get + * Description: + * Set unmatch source MAC packet moving state. + * Input: + * port - Port ID. + * Output: + * pEnable - ENABLED: allow SA moving, DISABLE: don't allow SA moving. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid action. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + */ +rtk_api_ret_t dal_rtl8367c_trap_unmatchMacMoving_get(rtk_port_t port, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* check port valid */ + RTK_CHK_PORT_VALID(port); + + if(NULL == pEnable) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicPortUnmatchedSaMoving(rtk_switch_port_L2P_get(port), pEnable)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_trap_unknownMcastPktAction_set + * Description: + * Set behavior of unknown multicast + * Input: + * port - Port id. + * type - unknown multicast packet type. + * mcast_action - unknown multicast action. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_NOT_ALLOWED - Invalid action. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * When receives an unknown multicast packet, switch may trap, drop or flood this packet + * (1) The unknown multicast packet type is as following: + * - MCAST_L2 + * - MCAST_IPV4 + * - MCAST_IPV6 + * (2) The unknown multicast action is as following: + * - MCAST_ACTION_FORWARD + * - MCAST_ACTION_DROP + * - MCAST_ACTION_TRAP2CPU + */ +rtk_api_ret_t dal_rtl8367c_trap_unknownMcastPktAction_set(rtk_port_t port, rtk_mcast_type_t type, rtk_trap_mcast_action_t mcast_action) +{ + rtk_api_ret_t retVal; + rtk_uint32 rawAction; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if (type >= MCAST_END) + return RT_ERR_INPUT; + + if (mcast_action >= MCAST_ACTION_END) + return RT_ERR_INPUT; + + + switch (type) + { + case MCAST_L2: + if (MCAST_ACTION_ROUTER_PORT == mcast_action) + return RT_ERR_INPUT; + else if(MCAST_ACTION_DROP_EX_RMA == mcast_action) + rawAction = L2_UNKOWN_MULTICAST_DROP_EXCLUDE_RMA; + else + rawAction = (rtk_uint32)mcast_action; + + if ((retVal = rtl8367c_setAsicUnknownL2MulticastBehavior(rtk_switch_port_L2P_get(port), rawAction)) != RT_ERR_OK) + return retVal; + + break; + case MCAST_IPV4: + if (MCAST_ACTION_DROP_EX_RMA == mcast_action) + return RT_ERR_INPUT; + else + rawAction = (rtk_uint32)mcast_action; + + if ((retVal = rtl8367c_setAsicUnknownIPv4MulticastBehavior(rtk_switch_port_L2P_get(port), rawAction)) != RT_ERR_OK) + return retVal; + + break; + case MCAST_IPV6: + if (MCAST_ACTION_DROP_EX_RMA == mcast_action) + return RT_ERR_INPUT; + else + rawAction = (rtk_uint32)mcast_action; + + if ((retVal = rtl8367c_setAsicUnknownIPv6MulticastBehavior(rtk_switch_port_L2P_get(port), rawAction)) != RT_ERR_OK) + return retVal; + + break; + default: + break; + } + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_trap_unknownMcastPktAction_get + * Description: + * Get behavior of unknown multicast + * Input: + * type - unknown multicast packet type. + * Output: + * pMcast_action - unknown multicast action. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_NOT_ALLOWED - Invalid operation. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * When receives an unknown multicast packet, switch may trap, drop or flood this packet + * (1) The unknown multicast packet type is as following: + * - MCAST_L2 + * - MCAST_IPV4 + * - MCAST_IPV6 + * (2) The unknown multicast action is as following: + * - MCAST_ACTION_FORWARD + * - MCAST_ACTION_DROP + * - MCAST_ACTION_TRAP2CPU + */ +rtk_api_ret_t dal_rtl8367c_trap_unknownMcastPktAction_get(rtk_port_t port, rtk_mcast_type_t type, rtk_trap_mcast_action_t *pMcast_action) +{ + rtk_api_ret_t retVal; + rtk_uint32 rawAction; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if (type >= MCAST_END) + return RT_ERR_INPUT; + + if(NULL == pMcast_action) + return RT_ERR_NULL_POINTER; + + switch (type) + { + case MCAST_L2: + if ((retVal = rtl8367c_getAsicUnknownL2MulticastBehavior(rtk_switch_port_L2P_get(port), &rawAction)) != RT_ERR_OK) + return retVal; + + if(L2_UNKOWN_MULTICAST_DROP_EXCLUDE_RMA == rawAction) + *pMcast_action = MCAST_ACTION_DROP_EX_RMA; + else + *pMcast_action = (rtk_trap_mcast_action_t)rawAction; + + break; + case MCAST_IPV4: + if ((retVal = rtl8367c_getAsicUnknownIPv4MulticastBehavior(rtk_switch_port_L2P_get(port), &rawAction)) != RT_ERR_OK) + return retVal; + + *pMcast_action = (rtk_trap_mcast_action_t)rawAction; + break; + case MCAST_IPV6: + if ((retVal = rtl8367c_getAsicUnknownIPv6MulticastBehavior(rtk_switch_port_L2P_get(port), &rawAction)) != RT_ERR_OK) + return retVal; + + *pMcast_action = (rtk_trap_mcast_action_t)rawAction; + break; + default: + break; + } + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_trap_lldpEnable_set + * Description: + * Set LLDP enable. + * Input: + * enabled - LLDP enable, 0: follow RMA, 1: use LLDP action. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid action. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * - DMAC Assignment + * - 01:80:c2:00:00:0e ethertype = 0x88CC LLDP + * - 01:80:c2:00:00:03 ethertype = 0x88CC + * - 01:80:c2:00:00:00 ethertype = 0x88CC + + */ +rtk_api_ret_t dal_rtl8367c_trap_lldpEnable_set(rtk_enable_t enabled) +{ + rtk_api_ret_t retVal; + rtl8367c_rma_t rmacfg; + rtk_enable_t tmp; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (enabled >= RTK_ENABLE_END) + return RT_ERR_ENABLE; + + if ((retVal = rtl8367c_getAsicRmaLldp(&tmp, &rmacfg)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicRmaLldp(enabled, &rmacfg)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_trap_lldpEnable_get + * Description: + * Get LLDP status. + * Input: + * None + * Output: + * pEnabled - LLDP enable, 0: follow RMA, 1: use LLDP action. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * LLDP is as following definition. + * - DMAC Assignment + * - 01:80:c2:00:00:0e ethertype = 0x88CC LLDP + * - 01:80:c2:00:00:03 ethertype = 0x88CC + * - 01:80:c2:00:00:00 ethertype = 0x88CC + */ +rtk_api_ret_t dal_rtl8367c_trap_lldpEnable_get(rtk_enable_t *pEnabled) +{ + rtk_api_ret_t retVal; + rtl8367c_rma_t rmacfg; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pEnabled) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicRmaLldp(pEnabled, &rmacfg)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_trap_reasonTrapToCpuPriority_set + * Description: + * Set priority value of a packet that trapped to CPU port according to specific reason. + * Input: + * type - reason that trap to CPU port. + * priority - internal priority that is going to be set for specific trap reason. + * Output: + * None. + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - Invalid input parameter + * Note: + * Currently the trap reason that supported are listed as follows: + * - TRAP_REASON_RMA + * - TRAP_REASON_OAM + * - TRAP_REASON_1XUNAUTH + * - TRAP_REASON_VLANSTACK + * - TRAP_REASON_UNKNOWNMC + */ +rtk_api_ret_t dal_rtl8367c_trap_reasonTrapToCpuPriority_set(rtk_trap_reason_type_t type, rtk_pri_t priority) +{ + rtk_api_ret_t retVal; + rtl8367c_rma_t rmacfg; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (type >= TRAP_REASON_END) + return RT_ERR_INPUT; + + if (priority > RTL8367C_PRIMAX) + return RT_ERR_QOS_INT_PRIORITY; + + switch (type) + { + case TRAP_REASON_RMA: + if ((retVal = rtl8367c_getAsicRma(0, &rmacfg)) != RT_ERR_OK) + return retVal; + rmacfg.trap_priority= priority; + if ((retVal = rtl8367c_setAsicRma(0, &rmacfg)) != RT_ERR_OK) + return retVal; + + break; + case TRAP_REASON_OAM: + if ((retVal = rtl8367c_setAsicOamCpuPri(priority)) != RT_ERR_OK) + return retVal; + + break; + case TRAP_REASON_1XUNAUTH: + if ((retVal = rtl8367c_setAsic1xTrapPriority(priority)) != RT_ERR_OK) + return retVal; + + break; + case TRAP_REASON_VLANSTACK: + if ((retVal = rtl8367c_setAsicSvlanTrapPriority(priority)) != RT_ERR_OK) + return retVal; + + break; + case TRAP_REASON_UNKNOWNMC: + if ((retVal = rtl8367c_setAsicUnknownMulticastTrapPriority(priority)) != RT_ERR_OK) + return retVal; + + break; + default: + return RT_ERR_CHIP_NOT_SUPPORTED; + } + + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_trap_reasonTrapToCpuPriority_get + * Description: + * Get priority value of a packet that trapped to CPU port according to specific reason. + * Input: + * type - reason that trap to CPU port. + * Output: + * pPriority - configured internal priority for such reason. + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - Invalid input parameter + * RT_ERR_NULL_POINTER - NULL pointer + * Note: + * Currently the trap reason that supported are listed as follows: + * - TRAP_REASON_RMA + * - TRAP_REASON_OAM + * - TRAP_REASON_1XUNAUTH + * - TRAP_REASON_VLANSTACK + * - TRAP_REASON_UNKNOWNMC + */ +rtk_api_ret_t dal_rtl8367c_trap_reasonTrapToCpuPriority_get(rtk_trap_reason_type_t type, rtk_pri_t *pPriority) +{ + rtk_api_ret_t retVal; + rtl8367c_rma_t rmacfg; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (type >= TRAP_REASON_END) + return RT_ERR_INPUT; + + if(NULL == pPriority) + return RT_ERR_NULL_POINTER; + + switch (type) + { + case TRAP_REASON_RMA: + if ((retVal = rtl8367c_getAsicRma(0, &rmacfg)) != RT_ERR_OK) + return retVal; + *pPriority = rmacfg.trap_priority; + + break; + case TRAP_REASON_OAM: + if ((retVal = rtl8367c_getAsicOamCpuPri(pPriority)) != RT_ERR_OK) + return retVal; + + break; + case TRAP_REASON_1XUNAUTH: + if ((retVal = rtl8367c_getAsic1xTrapPriority(pPriority)) != RT_ERR_OK) + return retVal; + + break; + case TRAP_REASON_VLANSTACK: + if ((retVal = rtl8367c_getAsicSvlanTrapPriority(pPriority)) != RT_ERR_OK) + return retVal; + + break; + case TRAP_REASON_UNKNOWNMC: + if ((retVal = rtl8367c_getAsicUnknownMulticastTrapPriority(pPriority)) != RT_ERR_OK) + return retVal; + + break; + default: + return RT_ERR_CHIP_NOT_SUPPORTED; + + } + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_trap_rmaAction_set + * Description: + * Set Reserved multicast address action configuration. + * Input: + * type - rma type. + * rma_action - RMA action. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * + * There are 48 types of Reserved Multicast Address frame for application usage. + * (1)They are as following definition. + * - TRAP_BRG_GROUP, + * - TRAP_FD_PAUSE, + * - TRAP_SP_MCAST, + * - TRAP_1X_PAE, + * - TRAP_UNDEF_BRG_04, + * - TRAP_UNDEF_BRG_05, + * - TRAP_UNDEF_BRG_06, + * - TRAP_UNDEF_BRG_07, + * - TRAP_PROVIDER_BRIDGE_GROUP_ADDRESS, + * - TRAP_UNDEF_BRG_09, + * - TRAP_UNDEF_BRG_0A, + * - TRAP_UNDEF_BRG_0B, + * - TRAP_UNDEF_BRG_0C, + * - TRAP_PROVIDER_BRIDGE_GVRP_ADDRESS, + * - TRAP_8021AB, + * - TRAP_UNDEF_BRG_0F, + * - TRAP_BRG_MNGEMENT, + * - TRAP_UNDEFINED_11, + * - TRAP_UNDEFINED_12, + * - TRAP_UNDEFINED_13, + * - TRAP_UNDEFINED_14, + * - TRAP_UNDEFINED_15, + * - TRAP_UNDEFINED_16, + * - TRAP_UNDEFINED_17, + * - TRAP_UNDEFINED_18, + * - TRAP_UNDEFINED_19, + * - TRAP_UNDEFINED_1A, + * - TRAP_UNDEFINED_1B, + * - TRAP_UNDEFINED_1C, + * - TRAP_UNDEFINED_1D, + * - TRAP_UNDEFINED_1E, + * - TRAP_UNDEFINED_1F, + * - TRAP_GMRP, + * - TRAP_GVRP, + * - TRAP_UNDEF_GARP_22, + * - TRAP_UNDEF_GARP_23, + * - TRAP_UNDEF_GARP_24, + * - TRAP_UNDEF_GARP_25, + * - TRAP_UNDEF_GARP_26, + * - TRAP_UNDEF_GARP_27, + * - TRAP_UNDEF_GARP_28, + * - TRAP_UNDEF_GARP_29, + * - TRAP_UNDEF_GARP_2A, + * - TRAP_UNDEF_GARP_2B, + * - TRAP_UNDEF_GARP_2C, + * - TRAP_UNDEF_GARP_2D, + * - TRAP_UNDEF_GARP_2E, + * - TRAP_UNDEF_GARP_2F, + * - TRAP_CDP. + * - TRAP_CSSTP. + * - TRAP_LLDP. + * (2) The RMA action is as following: + * - RMA_ACTION_FORWARD + * - RMA_ACTION_TRAP2CPU + * - RMA_ACTION_DROP + * - RMA_ACTION_FORWARD_EXCLUDE_CPU + */ +rtk_api_ret_t dal_rtl8367c_trap_rmaAction_set(rtk_trap_type_t type, rtk_trap_rma_action_t rma_action) +{ + rtk_api_ret_t retVal; + rtl8367c_rma_t rmacfg; + rtk_uint32 tmp; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (type >= TRAP_END) + return RT_ERR_INPUT; + + if (rma_action >= RMA_ACTION_END) + return RT_ERR_RMA_ACTION; + + if (type >= 0 && type <= TRAP_UNDEF_GARP_2F) + { + if ((retVal = rtl8367c_getAsicRma(type, &rmacfg)) != RT_ERR_OK) + return retVal; + + rmacfg.operation = rma_action; + + if ((retVal = rtl8367c_setAsicRma(type, &rmacfg)) != RT_ERR_OK) + return retVal; + } + else if (type == TRAP_CDP) + { + if ((retVal = rtl8367c_getAsicRmaCdp(&rmacfg)) != RT_ERR_OK) + return retVal; + + rmacfg.operation = rma_action; + + if ((retVal = rtl8367c_setAsicRmaCdp(&rmacfg)) != RT_ERR_OK) + return retVal; + } + else if (type == TRAP_CSSTP) + { + if ((retVal = rtl8367c_getAsicRmaCsstp(&rmacfg)) != RT_ERR_OK) + return retVal; + + rmacfg.operation = rma_action; + + if ((retVal = rtl8367c_setAsicRmaCsstp(&rmacfg)) != RT_ERR_OK) + return retVal; + } + else if (type == TRAP_LLDP) + { + if ((retVal = rtl8367c_getAsicRmaLldp(&tmp, &rmacfg)) != RT_ERR_OK) + return retVal; + + rmacfg.operation = rma_action; + + if ((retVal = rtl8367c_setAsicRmaLldp(tmp, &rmacfg)) != RT_ERR_OK) + return retVal; + } + else + return RT_ERR_INPUT; + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_trap_rmaAction_get + * Description: + * Get Reserved multicast address action configuration. + * Input: + * type - rma type. + * Output: + * pRma_action - RMA action. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * There are 48 types of Reserved Multicast Address frame for application usage. + * (1)They are as following definition. + * - TRAP_BRG_GROUP, + * - TRAP_FD_PAUSE, + * - TRAP_SP_MCAST, + * - TRAP_1X_PAE, + * - TRAP_UNDEF_BRG_04, + * - TRAP_UNDEF_BRG_05, + * - TRAP_UNDEF_BRG_06, + * - TRAP_UNDEF_BRG_07, + * - TRAP_PROVIDER_BRIDGE_GROUP_ADDRESS, + * - TRAP_UNDEF_BRG_09, + * - TRAP_UNDEF_BRG_0A, + * - TRAP_UNDEF_BRG_0B, + * - TRAP_UNDEF_BRG_0C, + * - TRAP_PROVIDER_BRIDGE_GVRP_ADDRESS, + * - TRAP_8021AB, + * - TRAP_UNDEF_BRG_0F, + * - TRAP_BRG_MNGEMENT, + * - TRAP_UNDEFINED_11, + * - TRAP_UNDEFINED_12, + * - TRAP_UNDEFINED_13, + * - TRAP_UNDEFINED_14, + * - TRAP_UNDEFINED_15, + * - TRAP_UNDEFINED_16, + * - TRAP_UNDEFINED_17, + * - TRAP_UNDEFINED_18, + * - TRAP_UNDEFINED_19, + * - TRAP_UNDEFINED_1A, + * - TRAP_UNDEFINED_1B, + * - TRAP_UNDEFINED_1C, + * - TRAP_UNDEFINED_1D, + * - TRAP_UNDEFINED_1E, + * - TRAP_UNDEFINED_1F, + * - TRAP_GMRP, + * - TRAP_GVRP, + * - TRAP_UNDEF_GARP_22, + * - TRAP_UNDEF_GARP_23, + * - TRAP_UNDEF_GARP_24, + * - TRAP_UNDEF_GARP_25, + * - TRAP_UNDEF_GARP_26, + * - TRAP_UNDEF_GARP_27, + * - TRAP_UNDEF_GARP_28, + * - TRAP_UNDEF_GARP_29, + * - TRAP_UNDEF_GARP_2A, + * - TRAP_UNDEF_GARP_2B, + * - TRAP_UNDEF_GARP_2C, + * - TRAP_UNDEF_GARP_2D, + * - TRAP_UNDEF_GARP_2E, + * - TRAP_UNDEF_GARP_2F, + * - TRAP_CDP. + * - TRAP_CSSTP. + * - TRAP_LLDP. + * (2) The RMA action is as following: + * - RMA_ACTION_FORWARD + * - RMA_ACTION_TRAP2CPU + * - RMA_ACTION_DROP + * - RMA_ACTION_FORWARD_EXCLUDE_CPU + */ +rtk_api_ret_t dal_rtl8367c_trap_rmaAction_get(rtk_trap_type_t type, rtk_trap_rma_action_t *pRma_action) +{ + rtk_api_ret_t retVal; + rtl8367c_rma_t rmacfg; + rtk_uint32 tmp; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (type >= TRAP_END) + return RT_ERR_INPUT; + + if(NULL == pRma_action) + return RT_ERR_NULL_POINTER; + + if (type >= 0 && type <= TRAP_UNDEF_GARP_2F) + { + if ((retVal = rtl8367c_getAsicRma(type, &rmacfg)) != RT_ERR_OK) + return retVal; + + *pRma_action = rmacfg.operation; + } + else if (type == TRAP_CDP) + { + if ((retVal = rtl8367c_getAsicRmaCdp(&rmacfg)) != RT_ERR_OK) + return retVal; + + *pRma_action = rmacfg.operation; + } + else if (type == TRAP_CSSTP) + { + if ((retVal = rtl8367c_getAsicRmaCsstp(&rmacfg)) != RT_ERR_OK) + return retVal; + + *pRma_action = rmacfg.operation; + } + else if (type == TRAP_LLDP) + { + if ((retVal = rtl8367c_getAsicRmaLldp(&tmp,&rmacfg)) != RT_ERR_OK) + return retVal; + + *pRma_action = rmacfg.operation; + } + else + return RT_ERR_INPUT; + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_trap_rmaKeepFormat_set + * Description: + * Set Reserved multicast address keep format configuration. + * Input: + * type - rma type. + * enable - enable keep format. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_ENABLE - Invalid IFG parameter + * Note: + * + * There are 48 types of Reserved Multicast Address frame for application usage. + * They are as following definition. + * - TRAP_BRG_GROUP, + * - TRAP_FD_PAUSE, + * - TRAP_SP_MCAST, + * - TRAP_1X_PAE, + * - TRAP_UNDEF_BRG_04, + * - TRAP_UNDEF_BRG_05, + * - TRAP_UNDEF_BRG_06, + * - TRAP_UNDEF_BRG_07, + * - TRAP_PROVIDER_BRIDGE_GROUP_ADDRESS, + * - TRAP_UNDEF_BRG_09, + * - TRAP_UNDEF_BRG_0A, + * - TRAP_UNDEF_BRG_0B, + * - TRAP_UNDEF_BRG_0C, + * - TRAP_PROVIDER_BRIDGE_GVRP_ADDRESS, + * - TRAP_8021AB, + * - TRAP_UNDEF_BRG_0F, + * - TRAP_BRG_MNGEMENT, + * - TRAP_UNDEFINED_11, + * - TRAP_UNDEFINED_12, + * - TRAP_UNDEFINED_13, + * - TRAP_UNDEFINED_14, + * - TRAP_UNDEFINED_15, + * - TRAP_UNDEFINED_16, + * - TRAP_UNDEFINED_17, + * - TRAP_UNDEFINED_18, + * - TRAP_UNDEFINED_19, + * - TRAP_UNDEFINED_1A, + * - TRAP_UNDEFINED_1B, + * - TRAP_UNDEFINED_1C, + * - TRAP_UNDEFINED_1D, + * - TRAP_UNDEFINED_1E, + * - TRAP_UNDEFINED_1F, + * - TRAP_GMRP, + * - TRAP_GVRP, + * - TRAP_UNDEF_GARP_22, + * - TRAP_UNDEF_GARP_23, + * - TRAP_UNDEF_GARP_24, + * - TRAP_UNDEF_GARP_25, + * - TRAP_UNDEF_GARP_26, + * - TRAP_UNDEF_GARP_27, + * - TRAP_UNDEF_GARP_28, + * - TRAP_UNDEF_GARP_29, + * - TRAP_UNDEF_GARP_2A, + * - TRAP_UNDEF_GARP_2B, + * - TRAP_UNDEF_GARP_2C, + * - TRAP_UNDEF_GARP_2D, + * - TRAP_UNDEF_GARP_2E, + * - TRAP_UNDEF_GARP_2F, + * - TRAP_CDP. + * - TRAP_CSSTP. + * - TRAP_LLDP. + */ +rtk_api_ret_t dal_rtl8367c_trap_rmaKeepFormat_set(rtk_trap_type_t type, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + rtl8367c_rma_t rmacfg; + rtk_uint32 tmp; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (type >= TRAP_END) + return RT_ERR_INPUT; + + if (enable >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if (type >= 0 && type <= TRAP_UNDEF_GARP_2F) + { + if ((retVal = rtl8367c_getAsicRma(type, &rmacfg)) != RT_ERR_OK) + return retVal; + + rmacfg.keep_format = enable; + + if ((retVal = rtl8367c_setAsicRma(type, &rmacfg)) != RT_ERR_OK) + return retVal; + } + else if (type == TRAP_CDP) + { + if ((retVal = rtl8367c_getAsicRmaCdp(&rmacfg)) != RT_ERR_OK) + return retVal; + + rmacfg.keep_format = enable; + + if ((retVal = rtl8367c_setAsicRmaCdp(&rmacfg)) != RT_ERR_OK) + return retVal; + } + else if (type == TRAP_CSSTP) + { + if ((retVal = rtl8367c_getAsicRmaCsstp(&rmacfg)) != RT_ERR_OK) + return retVal; + + rmacfg.keep_format = enable; + + if ((retVal = rtl8367c_setAsicRmaCsstp(&rmacfg)) != RT_ERR_OK) + return retVal; + } + else if (type == TRAP_LLDP) + { + if ((retVal = rtl8367c_getAsicRmaLldp(&tmp, &rmacfg)) != RT_ERR_OK) + return retVal; + + rmacfg.keep_format = enable; + + if ((retVal = rtl8367c_setAsicRmaLldp(tmp, &rmacfg)) != RT_ERR_OK) + return retVal; + } + else + return RT_ERR_INPUT; + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_trap_rmaKeepFormat_get + * Description: + * Get Reserved multicast address action configuration. + * Input: + * type - rma type. + * Output: + * pEnable - keep format status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * There are 48 types of Reserved Multicast Address frame for application usage. + * They are as following definition. + * - TRAP_BRG_GROUP, + * - TRAP_FD_PAUSE, + * - TRAP_SP_MCAST, + * - TRAP_1X_PAE, + * - TRAP_UNDEF_BRG_04, + * - TRAP_UNDEF_BRG_05, + * - TRAP_UNDEF_BRG_06, + * - TRAP_UNDEF_BRG_07, + * - TRAP_PROVIDER_BRIDGE_GROUP_ADDRESS, + * - TRAP_UNDEF_BRG_09, + * - TRAP_UNDEF_BRG_0A, + * - TRAP_UNDEF_BRG_0B, + * - TRAP_UNDEF_BRG_0C, + * - TRAP_PROVIDER_BRIDGE_GVRP_ADDRESS, + * - TRAP_8021AB, + * - TRAP_UNDEF_BRG_0F, + * - TRAP_BRG_MNGEMENT, + * - TRAP_UNDEFINED_11, + * - TRAP_UNDEFINED_12, + * - TRAP_UNDEFINED_13, + * - TRAP_UNDEFINED_14, + * - TRAP_UNDEFINED_15, + * - TRAP_UNDEFINED_16, + * - TRAP_UNDEFINED_17, + * - TRAP_UNDEFINED_18, + * - TRAP_UNDEFINED_19, + * - TRAP_UNDEFINED_1A, + * - TRAP_UNDEFINED_1B, + * - TRAP_UNDEFINED_1C, + * - TRAP_UNDEFINED_1D, + * - TRAP_UNDEFINED_1E, + * - TRAP_UNDEFINED_1F, + * - TRAP_GMRP, + * - TRAP_GVRP, + * - TRAP_UNDEF_GARP_22, + * - TRAP_UNDEF_GARP_23, + * - TRAP_UNDEF_GARP_24, + * - TRAP_UNDEF_GARP_25, + * - TRAP_UNDEF_GARP_26, + * - TRAP_UNDEF_GARP_27, + * - TRAP_UNDEF_GARP_28, + * - TRAP_UNDEF_GARP_29, + * - TRAP_UNDEF_GARP_2A, + * - TRAP_UNDEF_GARP_2B, + * - TRAP_UNDEF_GARP_2C, + * - TRAP_UNDEF_GARP_2D, + * - TRAP_UNDEF_GARP_2E, + * - TRAP_UNDEF_GARP_2F, + * - TRAP_CDP. + * - TRAP_CSSTP. + * - TRAP_LLDP. + */ +rtk_api_ret_t dal_rtl8367c_trap_rmaKeepFormat_get(rtk_trap_type_t type, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + rtl8367c_rma_t rmacfg; + rtk_uint32 tmp; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (type >= TRAP_END) + return RT_ERR_INPUT; + + if(NULL == pEnable) + return RT_ERR_NULL_POINTER; + + if (type >= 0 && type <= TRAP_UNDEF_GARP_2F) + { + if ((retVal = rtl8367c_getAsicRma(type, &rmacfg)) != RT_ERR_OK) + return retVal; + + *pEnable = rmacfg.keep_format; + } + else if (type == TRAP_CDP) + { + if ((retVal = rtl8367c_getAsicRmaCdp(&rmacfg)) != RT_ERR_OK) + return retVal; + + *pEnable = rmacfg.keep_format; + } + else if (type == TRAP_CSSTP) + { + if ((retVal = rtl8367c_getAsicRmaCsstp(&rmacfg)) != RT_ERR_OK) + return retVal; + + *pEnable = rmacfg.keep_format; + } + else if (type == TRAP_LLDP) + { + if ((retVal = rtl8367c_getAsicRmaLldp(&tmp,&rmacfg)) != RT_ERR_OK) + return retVal; + + *pEnable = rmacfg.keep_format; + } + else + return RT_ERR_INPUT; + + return RT_ERR_OK; +} + + + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_trap.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_trap.h new file mode 100644 index 00000000..cd4bae6e --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_trap.h @@ -0,0 +1,650 @@ + /* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8367/RTL8367C switch high-level API + * + * Feature : The file includes Trap module high-layer API defination + * + */ + +#ifndef __DAL_RTL8367C_TRAP_H__ +#define __DAL_RTL8367C_TRAP_H__ + +#include + +/* Function Name: + * dal_rtl8367c_trap_unknownUnicastPktAction_set + * Description: + * Set unknown unicast packet action configuration. + * Input: + * port - ingress port ID for unknown unicast packet + * ucast_action - Unknown unicast action. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid action. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can set unknown unicast packet action configuration. + * The unknown unicast action is as following: + * - UCAST_ACTION_FORWARD_PMASK + * - UCAST_ACTION_DROP + * - UCAST_ACTION_TRAP2CPU + * - UCAST_ACTION_FLOODING + */ +extern rtk_api_ret_t dal_rtl8367c_trap_unknownUnicastPktAction_set(rtk_port_t port, rtk_trap_ucast_action_t ucast_action); + +/* Function Name: + * dal_rtl8367c_trap_unknownUnicastPktAction_get + * Description: + * Get unknown unicast packet action configuration. + * Input: + * port - ingress port ID for unknown unicast packet + * Output: + * pUcast_action - Unknown unicast action. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid action. + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * This API can get unknown unicast packet action configuration. + * The unknown unicast action is as following: + * - UCAST_ACTION_FORWARD_PMASK + * - UCAST_ACTION_DROP + * - UCAST_ACTION_TRAP2CPU + * - UCAST_ACTION_FLOODING + */ +extern rtk_api_ret_t dal_rtl8367c_trap_unknownUnicastPktAction_get(rtk_port_t port, rtk_trap_ucast_action_t *pUcast_action); + +/* Function Name: + * dal_rtl8367c_trap_unknownMacPktAction_set + * Description: + * Set unknown source MAC packet action configuration. + * Input: + * ucast_action - Unknown source MAC action. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid action. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can set unknown unicast packet action configuration. + * The unknown unicast action is as following: + * - UCAST_ACTION_FORWARD_PMASK + * - UCAST_ACTION_DROP + * - UCAST_ACTION_TRAP2CPU + * - UCAST_ACTION_COPY28051 + */ +extern rtk_api_ret_t dal_rtl8367c_trap_unknownMacPktAction_set(rtk_trap_ucast_action_t ucast_action); + +/* Function Name: + * dal_rtl8367c_trap_unknownMacPktAction_get + * Description: + * Get unknown source MAC packet action configuration. + * Input: + * None. + * Output: + * pUcast_action - Unknown source MAC action. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Null Pointer. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367c_trap_unknownMacPktAction_get(rtk_trap_ucast_action_t *pUcast_action); + +/* Function Name: + * dal_rtl8367c_trap_unmatchMacPktAction_set + * Description: + * Set unmatch source MAC packet action configuration. + * Input: + * ucast_action - Unknown source MAC action. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid action. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can set unknown unicast packet action configuration. + * The unknown unicast action is as following: + * - UCAST_ACTION_FORWARD_PMASK + * - UCAST_ACTION_DROP + * - UCAST_ACTION_TRAP2CPU + * - UCAST_ACTION_COPY28051 + */ +extern rtk_api_ret_t dal_rtl8367c_trap_unmatchMacPktAction_set(rtk_trap_ucast_action_t ucast_action); + +/* Function Name: + * dal_rtl8367c_trap_unmatchMacPktAction_get + * Description: + * Get unmatch source MAC packet action configuration. + * Input: + * None. + * Output: + * pUcast_action - Unknown source MAC action. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid action. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can set unknown unicast packet action configuration. + * The unknown unicast action is as following: + * - UCAST_ACTION_FORWARD_PMASK + * - UCAST_ACTION_DROP + * - UCAST_ACTION_TRAP2CPU + */ +extern rtk_api_ret_t dal_rtl8367c_trap_unmatchMacPktAction_get(rtk_trap_ucast_action_t *pUcast_action); + +/* Function Name: + * dal_rtl8367c_trap_unmatchMacMoving_set + * Description: + * Set unmatch source MAC packet moving state. + * Input: + * port - Port ID. + * enable - ENABLED: allow SA moving, DISABLE: don't allow SA moving. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid action. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + */ +extern rtk_api_ret_t dal_rtl8367c_trap_unmatchMacMoving_set(rtk_port_t port, rtk_enable_t enable); + +/* Function Name: + * dal_rtl8367c_trap_unmatchMacMoving_get + * Description: + * Set unmatch source MAC packet moving state. + * Input: + * port - Port ID. + * Output: + * pEnable - ENABLED: allow SA moving, DISABLE: don't allow SA moving. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid action. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + */ +extern rtk_api_ret_t dal_rtl8367c_trap_unmatchMacMoving_get(rtk_port_t port, rtk_enable_t *pEnable); + +/* Function Name: + * dal_rtl8367c_trap_unknownMcastPktAction_set + * Description: + * Set behavior of unknown multicast + * Input: + * port - Port id. + * type - unknown multicast packet type. + * mcast_action - unknown multicast action. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_NOT_ALLOWED - Invalid action. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * When receives an unknown multicast packet, switch may trap, drop or flood this packet + * (1) The unknown multicast packet type is as following: + * - MCAST_L2 + * - MCAST_IPV4 + * - MCAST_IPV6 + * (2) The unknown multicast action is as following: + * - MCAST_ACTION_FORWARD + * - MCAST_ACTION_DROP + * - MCAST_ACTION_TRAP2CPU + */ +extern rtk_api_ret_t dal_rtl8367c_trap_unknownMcastPktAction_set(rtk_port_t port, rtk_mcast_type_t type, rtk_trap_mcast_action_t mcast_action); + +/* Function Name: + * dal_rtl8367c_trap_unknownMcastPktAction_get + * Description: + * Get behavior of unknown multicast + * Input: + * type - unknown multicast packet type. + * Output: + * pMcast_action - unknown multicast action. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_NOT_ALLOWED - Invalid operation. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * When receives an unknown multicast packet, switch may trap, drop or flood this packet + * (1) The unknown multicast packet type is as following: + * - MCAST_L2 + * - MCAST_IPV4 + * - MCAST_IPV6 + * (2) The unknown multicast action is as following: + * - MCAST_ACTION_FORWARD + * - MCAST_ACTION_DROP + * - MCAST_ACTION_TRAP2CPU + */ +extern rtk_api_ret_t dal_rtl8367c_trap_unknownMcastPktAction_get(rtk_port_t port, rtk_mcast_type_t type, rtk_trap_mcast_action_t *pMcast_action); + +/* Function Name: + * dal_rtl8367c_trap_lldpEnable_set + * Description: + * Set LLDP enable. + * Input: + * enabled - LLDP enable, 0: follow RMA, 1: use LLDP action. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid action. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * - DMAC Assignment + * - 01:80:c2:00:00:0e ethertype = 0x88CC LLDP + * - 01:80:c2:00:00:03 ethertype = 0x88CC + * - 01:80:c2:00:00:00 ethertype = 0x88CC + + */ +extern rtk_api_ret_t dal_rtl8367c_trap_lldpEnable_set(rtk_enable_t enabled); + +/* Function Name: + * dal_rtl8367c_trap_lldpEnable_get + * Description: + * Get LLDP status. + * Input: + * None + * Output: + * pEnabled - LLDP enable, 0: follow RMA, 1: use LLDP action. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * LLDP is as following definition. + * - DMAC Assignment + * - 01:80:c2:00:00:0e ethertype = 0x88CC LLDP + * - 01:80:c2:00:00:03 ethertype = 0x88CC + * - 01:80:c2:00:00:00 ethertype = 0x88CC + */ +extern rtk_api_ret_t dal_rtl8367c_trap_lldpEnable_get(rtk_enable_t *pEnabled); + +/* Function Name: + * dal_rtl8367c_trap_reasonTrapToCpuPriority_set + * Description: + * Set priority value of a packet that trapped to CPU port according to specific reason. + * Input: + * type - reason that trap to CPU port. + * priority - internal priority that is going to be set for specific trap reason. + * Output: + * None. + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - Invalid input parameter + * Note: + * Currently the trap reason that supported are listed as follows: + * - TRAP_REASON_RMA + * - TRAP_REASON_OAM + * - TRAP_REASON_1XUNAUTH + * - TRAP_REASON_VLANSTACK + * - TRAP_REASON_UNKNOWNMC + */ +extern rtk_api_ret_t dal_rtl8367c_trap_reasonTrapToCpuPriority_set(rtk_trap_reason_type_t type, rtk_pri_t priority); + +/* Function Name: + * dal_rtl8367c_trap_reasonTrapToCpuPriority_get + * Description: + * Get priority value of a packet that trapped to CPU port according to specific reason. + * Input: + * type - reason that trap to CPU port. + * Output: + * pPriority - configured internal priority for such reason. + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - Invalid input parameter + * RT_ERR_NULL_POINTER - NULL pointer + * Note: + * Currently the trap reason that supported are listed as follows: + * - TRAP_REASON_RMA + * - TRAP_REASON_OAM + * - TRAP_REASON_1XUNAUTH + * - TRAP_REASON_VLANSTACK + * - TRAP_REASON_UNKNOWNMC + */ +extern rtk_api_ret_t dal_rtl8367c_trap_reasonTrapToCpuPriority_get(rtk_trap_reason_type_t type, rtk_pri_t *pPriority); + +/* Function Name: + * dal_rtl8367c_trap_rmaAction_set + * Description: + * Set Reserved multicast address action configuration. + * Input: + * type - rma type. + * rma_action - RMA action. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_ENABLE - Invalid IFG parameter + * Note: + * + * There are 48 types of Reserved Multicast Address frame for application usage. + * (1)They are as following definition. + * - TRAP_BRG_GROUP, + * - TRAP_FD_PAUSE, + * - TRAP_SP_MCAST, + * - TRAP_1X_PAE, + * - TRAP_UNDEF_BRG_04, + * - TRAP_UNDEF_BRG_05, + * - TRAP_UNDEF_BRG_06, + * - TRAP_UNDEF_BRG_07, + * - TRAP_PROVIDER_BRIDGE_GROUP_ADDRESS, + * - TRAP_UNDEF_BRG_09, + * - TRAP_UNDEF_BRG_0A, + * - TRAP_UNDEF_BRG_0B, + * - TRAP_UNDEF_BRG_0C, + * - TRAP_PROVIDER_BRIDGE_GVRP_ADDRESS, + * - TRAP_8021AB, + * - TRAP_UNDEF_BRG_0F, + * - TRAP_BRG_MNGEMENT, + * - TRAP_UNDEFINED_11, + * - TRAP_UNDEFINED_12, + * - TRAP_UNDEFINED_13, + * - TRAP_UNDEFINED_14, + * - TRAP_UNDEFINED_15, + * - TRAP_UNDEFINED_16, + * - TRAP_UNDEFINED_17, + * - TRAP_UNDEFINED_18, + * - TRAP_UNDEFINED_19, + * - TRAP_UNDEFINED_1A, + * - TRAP_UNDEFINED_1B, + * - TRAP_UNDEFINED_1C, + * - TRAP_UNDEFINED_1D, + * - TRAP_UNDEFINED_1E, + * - TRAP_UNDEFINED_1F, + * - TRAP_GMRP, + * - TRAP_GVRP, + * - TRAP_UNDEF_GARP_22, + * - TRAP_UNDEF_GARP_23, + * - TRAP_UNDEF_GARP_24, + * - TRAP_UNDEF_GARP_25, + * - TRAP_UNDEF_GARP_26, + * - TRAP_UNDEF_GARP_27, + * - TRAP_UNDEF_GARP_28, + * - TRAP_UNDEF_GARP_29, + * - TRAP_UNDEF_GARP_2A, + * - TRAP_UNDEF_GARP_2B, + * - TRAP_UNDEF_GARP_2C, + * - TRAP_UNDEF_GARP_2D, + * - TRAP_UNDEF_GARP_2E, + * - TRAP_UNDEF_GARP_2F, + * - TRAP_CDP. + * - TRAP_CSSTP. + * - TRAP_LLDP. + * (2) The RMA action is as following: + * - RMA_ACTION_FORWARD + * - RMA_ACTION_TRAP2CPU + * - RMA_ACTION_DROP + * - RMA_ACTION_FORWARD_EXCLUDE_CPU + */ +extern rtk_api_ret_t dal_rtl8367c_trap_rmaAction_set(rtk_trap_type_t type, rtk_trap_rma_action_t rma_action); + +/* Function Name: + * dal_rtl8367c_trap_rmaAction_get + * Description: + * Get Reserved multicast address action configuration. + * Input: + * type - rma type. + * Output: + * pRma_action - RMA action. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * There are 48 types of Reserved Multicast Address frame for application usage. + * (1)They are as following definition. + * - TRAP_BRG_GROUP, + * - TRAP_FD_PAUSE, + * - TRAP_SP_MCAST, + * - TRAP_1X_PAE, + * - TRAP_UNDEF_BRG_04, + * - TRAP_UNDEF_BRG_05, + * - TRAP_UNDEF_BRG_06, + * - TRAP_UNDEF_BRG_07, + * - TRAP_PROVIDER_BRIDGE_GROUP_ADDRESS, + * - TRAP_UNDEF_BRG_09, + * - TRAP_UNDEF_BRG_0A, + * - TRAP_UNDEF_BRG_0B, + * - TRAP_UNDEF_BRG_0C, + * - TRAP_PROVIDER_BRIDGE_GVRP_ADDRESS, + * - TRAP_8021AB, + * - TRAP_UNDEF_BRG_0F, + * - TRAP_BRG_MNGEMENT, + * - TRAP_UNDEFINED_11, + * - TRAP_UNDEFINED_12, + * - TRAP_UNDEFINED_13, + * - TRAP_UNDEFINED_14, + * - TRAP_UNDEFINED_15, + * - TRAP_UNDEFINED_16, + * - TRAP_UNDEFINED_17, + * - TRAP_UNDEFINED_18, + * - TRAP_UNDEFINED_19, + * - TRAP_UNDEFINED_1A, + * - TRAP_UNDEFINED_1B, + * - TRAP_UNDEFINED_1C, + * - TRAP_UNDEFINED_1D, + * - TRAP_UNDEFINED_1E, + * - TRAP_UNDEFINED_1F, + * - TRAP_GMRP, + * - TRAP_GVRP, + * - TRAP_UNDEF_GARP_22, + * - TRAP_UNDEF_GARP_23, + * - TRAP_UNDEF_GARP_24, + * - TRAP_UNDEF_GARP_25, + * - TRAP_UNDEF_GARP_26, + * - TRAP_UNDEF_GARP_27, + * - TRAP_UNDEF_GARP_28, + * - TRAP_UNDEF_GARP_29, + * - TRAP_UNDEF_GARP_2A, + * - TRAP_UNDEF_GARP_2B, + * - TRAP_UNDEF_GARP_2C, + * - TRAP_UNDEF_GARP_2D, + * - TRAP_UNDEF_GARP_2E, + * - TRAP_UNDEF_GARP_2F, + * - TRAP_CDP. + * - TRAP_CSSTP. + * - TRAP_LLDP. + * (2) The RMA action is as following: + * - RMA_ACTION_FORWARD + * - RMA_ACTION_TRAP2CPU + * - RMA_ACTION_DROP + * - RMA_ACTION_FORWARD_EXCLUDE_CPU + */ +extern rtk_api_ret_t dal_rtl8367c_trap_rmaAction_get(rtk_trap_type_t type, rtk_trap_rma_action_t *pRma_action); + +/* Function Name: + * dal_rtl8367c_trap_rmaKeepFormat_set + * Description: + * Set Reserved multicast address keep format configuration. + * Input: + * type - rma type. + * enable - enable keep format. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_ENABLE - Invalid IFG parameter + * Note: + * + * There are 48 types of Reserved Multicast Address frame for application usage. + * They are as following definition. + * - TRAP_BRG_GROUP, + * - TRAP_FD_PAUSE, + * - TRAP_SP_MCAST, + * - TRAP_1X_PAE, + * - TRAP_UNDEF_BRG_04, + * - TRAP_UNDEF_BRG_05, + * - TRAP_UNDEF_BRG_06, + * - TRAP_UNDEF_BRG_07, + * - TRAP_PROVIDER_BRIDGE_GROUP_ADDRESS, + * - TRAP_UNDEF_BRG_09, + * - TRAP_UNDEF_BRG_0A, + * - TRAP_UNDEF_BRG_0B, + * - TRAP_UNDEF_BRG_0C, + * - TRAP_PROVIDER_BRIDGE_GVRP_ADDRESS, + * - TRAP_8021AB, + * - TRAP_UNDEF_BRG_0F, + * - TRAP_BRG_MNGEMENT, + * - TRAP_UNDEFINED_11, + * - TRAP_UNDEFINED_12, + * - TRAP_UNDEFINED_13, + * - TRAP_UNDEFINED_14, + * - TRAP_UNDEFINED_15, + * - TRAP_UNDEFINED_16, + * - TRAP_UNDEFINED_17, + * - TRAP_UNDEFINED_18, + * - TRAP_UNDEFINED_19, + * - TRAP_UNDEFINED_1A, + * - TRAP_UNDEFINED_1B, + * - TRAP_UNDEFINED_1C, + * - TRAP_UNDEFINED_1D, + * - TRAP_UNDEFINED_1E, + * - TRAP_UNDEFINED_1F, + * - TRAP_GMRP, + * - TRAP_GVRP, + * - TRAP_UNDEF_GARP_22, + * - TRAP_UNDEF_GARP_23, + * - TRAP_UNDEF_GARP_24, + * - TRAP_UNDEF_GARP_25, + * - TRAP_UNDEF_GARP_26, + * - TRAP_UNDEF_GARP_27, + * - TRAP_UNDEF_GARP_28, + * - TRAP_UNDEF_GARP_29, + * - TRAP_UNDEF_GARP_2A, + * - TRAP_UNDEF_GARP_2B, + * - TRAP_UNDEF_GARP_2C, + * - TRAP_UNDEF_GARP_2D, + * - TRAP_UNDEF_GARP_2E, + * - TRAP_UNDEF_GARP_2F, + * - TRAP_CDP. + * - TRAP_CSSTP. + * - TRAP_LLDP. + */ +extern rtk_api_ret_t dal_rtl8367c_trap_rmaKeepFormat_set(rtk_trap_type_t type, rtk_enable_t enable); + +/* Function Name: + * dal_rtl8367c_trap_rmaKeepFormat_get + * Description: + * Get Reserved multicast address action configuration. + * Input: + * type - rma type. + * Output: + * pEnable - keep format status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * There are 48 types of Reserved Multicast Address frame for application usage. + * They are as following definition. + * - TRAP_BRG_GROUP, + * - TRAP_FD_PAUSE, + * - TRAP_SP_MCAST, + * - TRAP_1X_PAE, + * - TRAP_UNDEF_BRG_04, + * - TRAP_UNDEF_BRG_05, + * - TRAP_UNDEF_BRG_06, + * - TRAP_UNDEF_BRG_07, + * - TRAP_PROVIDER_BRIDGE_GROUP_ADDRESS, + * - TRAP_UNDEF_BRG_09, + * - TRAP_UNDEF_BRG_0A, + * - TRAP_UNDEF_BRG_0B, + * - TRAP_UNDEF_BRG_0C, + * - TRAP_PROVIDER_BRIDGE_GVRP_ADDRESS, + * - TRAP_8021AB, + * - TRAP_UNDEF_BRG_0F, + * - TRAP_BRG_MNGEMENT, + * - TRAP_UNDEFINED_11, + * - TRAP_UNDEFINED_12, + * - TRAP_UNDEFINED_13, + * - TRAP_UNDEFINED_14, + * - TRAP_UNDEFINED_15, + * - TRAP_UNDEFINED_16, + * - TRAP_UNDEFINED_17, + * - TRAP_UNDEFINED_18, + * - TRAP_UNDEFINED_19, + * - TRAP_UNDEFINED_1A, + * - TRAP_UNDEFINED_1B, + * - TRAP_UNDEFINED_1C, + * - TRAP_UNDEFINED_1D, + * - TRAP_UNDEFINED_1E, + * - TRAP_UNDEFINED_1F, + * - TRAP_GMRP, + * - TRAP_GVRP, + * - TRAP_UNDEF_GARP_22, + * - TRAP_UNDEF_GARP_23, + * - TRAP_UNDEF_GARP_24, + * - TRAP_UNDEF_GARP_25, + * - TRAP_UNDEF_GARP_26, + * - TRAP_UNDEF_GARP_27, + * - TRAP_UNDEF_GARP_28, + * - TRAP_UNDEF_GARP_29, + * - TRAP_UNDEF_GARP_2A, + * - TRAP_UNDEF_GARP_2B, + * - TRAP_UNDEF_GARP_2C, + * - TRAP_UNDEF_GARP_2D, + * - TRAP_UNDEF_GARP_2E, + * - TRAP_UNDEF_GARP_2F, + * - TRAP_CDP. + * - TRAP_CSSTP. + * - TRAP_LLDP. + */ +extern rtk_api_ret_t dal_rtl8367c_trap_rmaKeepFormat_get(rtk_trap_type_t type, rtk_enable_t *pEnable); + + +#endif /* __DAL_RTL8367C_TRAP_H__ */ + + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_trunk.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_trunk.c new file mode 100644 index 00000000..afc27b0d --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_trunk.c @@ -0,0 +1,607 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8367C + * Feature : Here is a list of all functions and variables in Trunk module. + * + */ + +#include +#include +#include +#include + +#include +#include + +/* Function Name: + * dal_rtl8367c_trunk_port_set + * Description: + * Set trunking group available port mask + * Input: + * trk_gid - trunk group id + * pTrunk_member_portmask - Logic trunking member port mask + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_LA_TRUNK_ID - Invalid trunking group + * RT_ERR_PORT_MASK - Invalid portmask. + * Note: + * The API can set port trunking group port mask. Each port trunking group has max 4 ports. + * If enabled port mask has less than 2 ports available setting, then this trunking group function is disabled. + */ +rtk_api_ret_t dal_rtl8367c_trunk_port_set(rtk_trunk_group_t trk_gid, rtk_portmask_t *pTrunk_member_portmask) +{ + rtk_api_ret_t retVal; + rtk_uint32 pmsk; + rtk_uint32 regValue, type, tmp; + + + if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0249)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_getAsicReg(0x1300, ®Value)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0000)) != RT_ERR_OK) + return retVal; + + switch (regValue) + { + case 0x0276: + case 0x0597: + case 0x6367: + type = 0; + break; + case 0x0652: + case 0x6368: + type = 1; + break; + case 0x0801: + case 0x6511: + type = 2; + break; + default: + return RT_ERR_FAILED; + } + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Trunk Group Valid */ + RTK_CHK_TRUNK_GROUP_VALID(trk_gid); + + if(NULL == pTrunk_member_portmask) + return RT_ERR_NULL_POINTER; + + RTK_CHK_PORTMASK_VALID(pTrunk_member_portmask); + + if((retVal = rtk_switch_portmask_L2P_get(pTrunk_member_portmask, &pmsk)) != RT_ERR_OK) + return retVal; + + if((type == 0) || (type == 1)) + { + if ((pmsk | RTL8367C_PORT_TRUNK_GROUP_MASK_MASK(trk_gid)) != (rtk_uint32)RTL8367C_PORT_TRUNK_GROUP_MASK_MASK(trk_gid)) + return RT_ERR_PORT_MASK; + + pmsk = (pmsk & RTL8367C_PORT_TRUNK_GROUP_MASK_MASK(trk_gid)) >> RTL8367C_PORT_TRUNK_GROUP_MASK_OFFSET(trk_gid); + } + else if(type == 2) + { + tmp = 0; + + if(pmsk & 0x2) + tmp |= 1; + if(pmsk & 0x8) + tmp |=2; + if(pmsk & 0x80) + tmp |=8; + + pmsk = tmp; + } + + if ((retVal = rtl8367c_setAsicTrunkingGroup(trk_gid, pmsk)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_trunk_port_get + * Description: + * Get trunking group available port mask + * Input: + * trk_gid - trunk group id + * Output: + * pTrunk_member_portmask - Logic trunking member port mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_LA_TRUNK_ID - Invalid trunking group + * Note: + * The API can get 2 port trunking group. + */ +rtk_api_ret_t dal_rtl8367c_trunk_port_get(rtk_trunk_group_t trk_gid, rtk_portmask_t *pTrunk_member_portmask) +{ + rtk_api_ret_t retVal; + rtk_uint32 pmsk; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Trunk Group Valid */ + RTK_CHK_TRUNK_GROUP_VALID(trk_gid); + + if ((retVal = rtl8367c_getAsicTrunkingGroup(trk_gid, &pmsk)) != RT_ERR_OK) + return retVal; + + pmsk = pmsk << RTL8367C_PORT_TRUNK_GROUP_MASK_OFFSET(trk_gid); + + if((retVal = rtk_switch_portmask_P2L_get(pmsk, pTrunk_member_portmask)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_trunk_distributionAlgorithm_set + * Description: + * Set port trunking hash select sources + * Input: + * trk_gid - trunk group id + * algo_bitmask - Bitmask of the distribution algorithm + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_LA_TRUNK_ID - Invalid trunking group + * RT_ERR_LA_HASHMASK - Hash algorithm selection error. + * RT_ERR_PORT_MASK - Invalid portmask. + * Note: + * The API can set port trunking hash algorithm sources. + * 7 bits mask for link aggregation group0 hash parameter selection {DIP, SIP, DMAC, SMAC, SPA} + * - 0b0000001: SPA + * - 0b0000010: SMAC + * - 0b0000100: DMAC + * - 0b0001000: SIP + * - 0b0010000: DIP + * - 0b0100000: TCP/UDP Source Port + * - 0b1000000: TCP/UDP Destination Port + * Example: + * - 0b0000011: SMAC & SPA + * - Note that it could be an arbitrary combination or independent set + */ +rtk_api_ret_t dal_rtl8367c_trunk_distributionAlgorithm_set(rtk_trunk_group_t trk_gid, rtk_uint32 algo_bitmask) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (trk_gid != RTK_WHOLE_SYSTEM) + return RT_ERR_LA_TRUNK_ID; + + if (algo_bitmask >= 128) + return RT_ERR_LA_HASHMASK; + + if ((retVal = rtl8367c_setAsicTrunkingHashSelect(algo_bitmask)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_trunk_distributionAlgorithm_get + * Description: + * Get port trunking hash select sources + * Input: + * trk_gid - trunk group id + * Output: + * pAlgo_bitmask - Bitmask of the distribution algorithm + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_LA_TRUNK_ID - Invalid trunking group + * Note: + * The API can get port trunking hash algorithm sources. + */ +rtk_api_ret_t dal_rtl8367c_trunk_distributionAlgorithm_get(rtk_trunk_group_t trk_gid, rtk_uint32 *pAlgo_bitmask) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (trk_gid != RTK_WHOLE_SYSTEM) + return RT_ERR_LA_TRUNK_ID; + + if(NULL == pAlgo_bitmask) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicTrunkingHashSelect((rtk_uint32 *)pAlgo_bitmask)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_trunk_trafficSeparate_set + * Description: + * Set the traffic separation setting of a trunk group from the specified device. + * Input: + * trk_gid - trunk group id + * separateType - traffic separation setting + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_LA_TRUNK_ID - invalid trunk ID + * RT_ERR_LA_HASHMASK - invalid hash mask + * Note: + * SEPARATE_NONE: disable traffic separation + * SEPARATE_FLOOD: trunk MSB link up port is dedicated to TX flooding (L2 lookup miss) traffic + */ +rtk_api_ret_t dal_rtl8367c_trunk_trafficSeparate_set(rtk_trunk_group_t trk_gid, rtk_trunk_separateType_t separateType) +{ + rtk_api_ret_t retVal; + rtk_uint32 enabled; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (trk_gid != RTK_WHOLE_SYSTEM) + return RT_ERR_LA_TRUNK_ID; + + if(separateType >= SEPARATE_END) + return RT_ERR_INPUT; + + enabled = (separateType == SEPARATE_FLOOD) ? ENABLED : DISABLED; + if ((retVal = rtl8367c_setAsicTrunkingFlood(enabled)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_trunk_trafficSeparate_get + * Description: + * Get the traffic separation setting of a trunk group from the specified device. + * Input: + * trk_gid - trunk group id + * Output: + * pSeparateType - pointer separated traffic type + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_LA_TRUNK_ID - invalid trunk ID + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * SEPARATE_NONE: disable traffic separation + * SEPARATE_FLOOD: trunk MSB link up port is dedicated to TX flooding (L2 lookup miss) traffic + */ +rtk_api_ret_t dal_rtl8367c_trunk_trafficSeparate_get(rtk_trunk_group_t trk_gid, rtk_trunk_separateType_t *pSeparateType) +{ + rtk_api_ret_t retVal; + rtk_uint32 enabled; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (trk_gid != RTK_WHOLE_SYSTEM) + return RT_ERR_LA_TRUNK_ID; + + if(NULL == pSeparateType) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicTrunkingFlood(&enabled)) != RT_ERR_OK) + return retVal; + + *pSeparateType = (enabled == ENABLED) ? SEPARATE_FLOOD : SEPARATE_NONE; + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_trunk_mode_set + * Description: + * Set the trunk mode to the specified device. + * Input: + * mode - trunk mode + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT - invalid input parameter + * Note: + * The enum of the trunk mode as following + * - TRUNK_MODE_NORMAL + * - TRUNK_MODE_DUMB + */ +rtk_api_ret_t dal_rtl8367c_trunk_mode_set(rtk_trunk_mode_t mode) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(mode >= TRUNK_MODE_END) + return RT_ERR_INPUT; + + if ((retVal = rtl8367c_setAsicTrunkingMode((rtk_uint32)mode)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_trunk_mode_get + * Description: + * Get the trunk mode from the specified device. + * Input: + * None + * Output: + * pMode - pointer buffer of trunk mode + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * The enum of the trunk mode as following + * - TRUNK_MODE_NORMAL + * - TRUNK_MODE_DUMB + */ +rtk_api_ret_t dal_rtl8367c_trunk_mode_get(rtk_trunk_mode_t *pMode) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pMode) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicTrunkingMode((rtk_uint32 *)pMode)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_trunk_trafficPause_set + * Description: + * Set the traffic pause setting of a trunk group. + * Input: + * trk_gid - trunk group id + * enable - traffic pause state + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_LA_TRUNK_ID - invalid trunk ID + * Note: + * None. + */ +rtk_api_ret_t dal_rtl8367c_trunk_trafficPause_set(rtk_trunk_group_t trk_gid, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Trunk Group Valid */ + RTK_CHK_TRUNK_GROUP_VALID(trk_gid); + + if(enable >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if ((retVal = rtl8367c_setAsicTrunkingFc((rtk_uint32)trk_gid, (rtk_uint32)enable)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_trunk_trafficPause_get + * Description: + * Get the traffic pause setting of a trunk group. + * Input: + * trk_gid - trunk group id + * Output: + * pEnable - pointer of traffic pause state. + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_LA_TRUNK_ID - invalid trunk ID + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None. + */ +rtk_api_ret_t dal_rtl8367c_trunk_trafficPause_get(rtk_trunk_group_t trk_gid, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Trunk Group Valid */ + RTK_CHK_TRUNK_GROUP_VALID(trk_gid); + + if(NULL == pEnable) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicTrunkingFc((rtk_uint32)trk_gid, (rtk_uint32 *)pEnable)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_trunk_hashMappingTable_set + * Description: + * Set hash value to port array in the trunk group id from the specified device. + * Input: + * trk_gid - trunk group id + * pHash2Port_array - ports associate with the hash value + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_LA_TRUNK_ID - invalid trunk ID + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * RT_ERR_LA_TRUNK_NOT_EXIST - the trunk doesn't exist + * RT_ERR_LA_NOT_MEMBER_PORT - the port is not a member port of the trunk + * RT_ERR_LA_CPUPORT - CPU port can not be aggregated port + * Note: + * Trunk group 0 & 1 shares the same hash mapping table. + * Trunk group 2 uses a independent table. + */ +rtk_api_ret_t dal_rtl8367c_trunk_hashMappingTable_set(rtk_trunk_group_t trk_gid, rtk_trunk_hashVal2Port_t *pHash2Port_array) +{ + rtk_api_ret_t retVal; + rtk_uint32 hashValue; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Trunk Group Valid */ + RTK_CHK_TRUNK_GROUP_VALID(trk_gid); + + if(NULL == pHash2Port_array) + return RT_ERR_NULL_POINTER; + + if(trk_gid <= TRUNK_GROUP1) + { + for(hashValue = 0; hashValue < RTK_MAX_NUM_OF_TRUNK_HASH_VAL; hashValue++) + { + if ((retVal = rtl8367c_setAsicTrunkingHashTable(hashValue, pHash2Port_array->value[hashValue])) != RT_ERR_OK) + return retVal; + } + } + else + { + for(hashValue = 0; hashValue < RTK_MAX_NUM_OF_TRUNK_HASH_VAL; hashValue++) + { + if ((retVal = rtl8367c_setAsicTrunkingHashTable1(hashValue, pHash2Port_array->value[hashValue])) != RT_ERR_OK) + return retVal; + } + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_trunk_hashMappingTable_get + * Description: + * Get hash value to port array in the trunk group id from the specified device. + * Input: + * trk_gid - trunk group id + * Output: + * pHash2Port_array - pointer buffer of ports associate with the hash value + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_LA_TRUNK_ID - invalid trunk ID + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * Trunk group 0 & 1 shares the same hash mapping table. + * Trunk group 2 uses a independent table. + */ +rtk_api_ret_t dal_rtl8367c_trunk_hashMappingTable_get(rtk_trunk_group_t trk_gid, rtk_trunk_hashVal2Port_t *pHash2Port_array) +{ + rtk_api_ret_t retVal; + rtk_uint32 hashValue; + rtk_uint32 hashPort; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Trunk Group Valid */ + RTK_CHK_TRUNK_GROUP_VALID(trk_gid); + + if(NULL == pHash2Port_array) + return RT_ERR_NULL_POINTER; + + if(trk_gid <= TRUNK_GROUP1) + { + for(hashValue = 0; hashValue < RTK_MAX_NUM_OF_TRUNK_HASH_VAL; hashValue++) + { + if ((retVal = rtl8367c_getAsicTrunkingHashTable(hashValue, &hashPort)) != RT_ERR_OK) + return retVal; + + pHash2Port_array->value[hashValue] = hashPort; + } + } + else + { + for(hashValue = 0; hashValue < RTK_MAX_NUM_OF_TRUNK_HASH_VAL; hashValue++) + { + if ((retVal = rtl8367c_getAsicTrunkingHashTable1(hashValue, &hashPort)) != RT_ERR_OK) + return retVal; + + pHash2Port_array->value[hashValue] = hashPort; + } + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_trunk_portQueueEmpty_get + * Description: + * Get the port mask which all queues are empty. + * Input: + * None. + * Output: + * pEmpty_portmask - pointer empty port mask + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None. + */ +rtk_api_ret_t dal_rtl8367c_trunk_portQueueEmpty_get(rtk_portmask_t *pEmpty_portmask) +{ + rtk_api_ret_t retVal; + rtk_uint32 pmask; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pEmpty_portmask) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicQeueuEmptyStatus(&pmask)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtk_switch_portmask_P2L_get(pmask, pEmpty_portmask)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_trunk.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_trunk.h new file mode 100644 index 00000000..0b774f7c --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_trunk.h @@ -0,0 +1,289 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8367/RTL8367C switch high-level API + * + * Feature : The file includes Trunk module high-layer TRUNK defination + * + */ + +#ifndef __DAL_RTL8367C_TRUNK_H__ +#define __DAL_RTL8367C_TRUNK_H__ + +#include + +/* Function Name: + * dal_rtl8367c_trunk_port_set + * Description: + * Set trunking group available port mask + * Input: + * trk_gid - trunk group id + * pTrunk_member_portmask - Logic trunking member port mask + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_LA_TRUNK_ID - Invalid trunking group + * RT_ERR_PORT_MASK - Invalid portmask. + * Note: + * The API can set port trunking group port mask. Each port trunking group has max 4 ports. + * If enabled port mask has less than 2 ports available setting, then this trunking group function is disabled. + */ +extern rtk_api_ret_t dal_rtl8367c_trunk_port_set(rtk_trunk_group_t trk_gid, rtk_portmask_t *pTrunk_member_portmask); + +/* Function Name: + * dal_rtl8367c_trunk_port_get + * Description: + * Get trunking group available port mask + * Input: + * trk_gid - trunk group id + * Output: + * pTrunk_member_portmask - Logic trunking member port mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_LA_TRUNK_ID - Invalid trunking group + * Note: + * The API can get 2 port trunking group. + */ +extern rtk_api_ret_t dal_rtl8367c_trunk_port_get(rtk_trunk_group_t trk_gid, rtk_portmask_t *pTrunk_member_portmask); + +/* Function Name: + * dal_rtl8367c_trunk_distributionAlgorithm_set + * Description: + * Set port trunking hash select sources + * Input: + * trk_gid - trunk group id + * algo_bitmask - Bitmask of the distribution algorithm + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_LA_TRUNK_ID - Invalid trunking group + * RT_ERR_LA_HASHMASK - Hash algorithm selection error. + * RT_ERR_PORT_MASK - Invalid portmask. + * Note: + * The API can set port trunking hash algorithm sources. + * 7 bits mask for link aggregation group0 hash parameter selection {DIP, SIP, DMAC, SMAC, SPA} + * - 0b0000001: SPA + * - 0b0000010: SMAC + * - 0b0000100: DMAC + * - 0b0001000: SIP + * - 0b0010000: DIP + * - 0b0100000: TCP/UDP Source Port + * - 0b1000000: TCP/UDP Destination Port + * Example: + * - 0b0000011: SMAC & SPA + * - Note that it could be an arbitrary combination or independent set + */ +extern rtk_api_ret_t dal_rtl8367c_trunk_distributionAlgorithm_set(rtk_trunk_group_t trk_gid, rtk_uint32 algo_bitmask); + +/* Function Name: + * dal_rtl8367c_trunk_distributionAlgorithm_get + * Description: + * Get port trunking hash select sources + * Input: + * trk_gid - trunk group id + * Output: + * pAlgo_bitmask - Bitmask of the distribution algorithm + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_LA_TRUNK_ID - Invalid trunking group + * Note: + * The API can get port trunking hash algorithm sources. + */ +extern rtk_api_ret_t dal_rtl8367c_trunk_distributionAlgorithm_get(rtk_trunk_group_t trk_gid, rtk_uint32 *pAlgo_bitmask); + +/* Function Name: + * dal_rtl8367c_trunk_trafficSeparate_set + * Description: + * Set the traffic separation setting of a trunk group from the specified device. + * Input: + * trk_gid - trunk group id + * separateType - traffic separation setting + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_LA_TRUNK_ID - invalid trunk ID + * RT_ERR_LA_HASHMASK - invalid hash mask + * Note: + * SEPARATE_NONE: disable traffic separation + * SEPARATE_FLOOD: trunk MSB link up port is dedicated to TX flooding (L2 lookup miss) traffic + */ +extern rtk_api_ret_t dal_rtl8367c_trunk_trafficSeparate_set(rtk_trunk_group_t trk_gid, rtk_trunk_separateType_t separateType); + +/* Function Name: + * dal_rtl8367c_trunk_trafficSeparate_get + * Description: + * Get the traffic separation setting of a trunk group from the specified device. + * Input: + * trk_gid - trunk group id + * Output: + * pSeparateType - pointer separated traffic type + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_LA_TRUNK_ID - invalid trunk ID + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * SEPARATE_NONE: disable traffic separation + * SEPARATE_FLOOD: trunk MSB link up port is dedicated to TX flooding (L2 lookup miss) traffic + */ +extern rtk_api_ret_t dal_rtl8367c_trunk_trafficSeparate_get(rtk_trunk_group_t trk_gid, rtk_trunk_separateType_t *pSeparateType); + + +/* Function Name: + * dal_rtl8367c_trunk_mode_set + * Description: + * Set the trunk mode to the specified device. + * Input: + * mode - trunk mode + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT - invalid input parameter + * Note: + * The enum of the trunk mode as following + * - TRUNK_MODE_NORMAL + * - TRUNK_MODE_DUMB + */ +extern rtk_api_ret_t dal_rtl8367c_trunk_mode_set(rtk_trunk_mode_t mode); + +/* Function Name: + * dal_rtl8367c_trunk_mode_get + * Description: + * Get the trunk mode from the specified device. + * Input: + * None + * Output: + * pMode - pointer buffer of trunk mode + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * The enum of the trunk mode as following + * - TRUNK_MODE_NORMAL + * - TRUNK_MODE_DUMB + */ +extern rtk_api_ret_t dal_rtl8367c_trunk_mode_get(rtk_trunk_mode_t *pMode); + +/* Function Name: + * dal_rtl8367c_trunk_trafficPause_set + * Description: + * Set the traffic pause setting of a trunk group. + * Input: + * trk_gid - trunk group id + * enable - traffic pause state + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_LA_TRUNK_ID - invalid trunk ID + * Note: + * None. + */ +extern rtk_api_ret_t dal_rtl8367c_trunk_trafficPause_set(rtk_trunk_group_t trk_gid, rtk_enable_t enable); + +/* Function Name: + * dal_rtl8367c_trunk_trafficPause_get + * Description: + * Get the traffic pause setting of a trunk group. + * Input: + * trk_gid - trunk group id + * Output: + * pEnable - pointer of traffic pause state. + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_LA_TRUNK_ID - invalid trunk ID + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None. + */ +extern rtk_api_ret_t dal_rtl8367c_trunk_trafficPause_get(rtk_trunk_group_t trk_gid, rtk_enable_t *pEnable); + +/* Function Name: + * dal_rtl8367c_trunk_hashMappingTable_set + * Description: + * Set hash value to port array in the trunk group id from the specified device. + * Input: + * trk_gid - trunk group id + * pHash2Port_array - ports associate with the hash value + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_LA_TRUNK_ID - invalid trunk ID + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * RT_ERR_LA_TRUNK_NOT_EXIST - the trunk doesn't exist + * RT_ERR_LA_NOT_MEMBER_PORT - the port is not a member port of the trunk + * RT_ERR_LA_CPUPORT - CPU port can not be aggregated port + * Note: + * Trunk group 0 & 1 shares the same hash mapping table. + * Trunk group 2 uses a independent table. + */ +extern rtk_api_ret_t dal_rtl8367c_trunk_hashMappingTable_set(rtk_trunk_group_t trk_gid, rtk_trunk_hashVal2Port_t *pHash2Port_array); + +/* Function Name: + * dal_rtl8367c_trunk_hashMappingTable_get + * Description: + * Get hash value to port array in the trunk group id from the specified device. + * Input: + * trk_gid - trunk group id + * Output: + * pHash2Port_array - pointer buffer of ports associate with the hash value + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_LA_TRUNK_ID - invalid trunk ID + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * Trunk group 0 & 1 shares the same hash mapping table. + * Trunk group 2 uses a independent table. + */ +extern rtk_api_ret_t dal_rtl8367c_trunk_hashMappingTable_get(rtk_trunk_group_t trk_gid, rtk_trunk_hashVal2Port_t *pHash2Port_array); + +/* Function Name: + * dal_rtl8367c_trunk_portQueueEmpty_get + * Description: + * Get the port mask which all queues are empty. + * Input: + * None. + * Output: + * pEmpty_portmask - pointer empty port mask + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None. + */ +extern rtk_api_ret_t dal_rtl8367c_trunk_portQueueEmpty_get(rtk_portmask_t *pEmpty_portmask); + +#endif /* __DAL_RTL8367C_TRUNK_H__ */ diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_vlan.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_vlan.c new file mode 100644 index 00000000..67b4f82e --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_vlan.c @@ -0,0 +1,2136 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8367C + * Feature : Here is a list of all functions and variables in VLAN module. + * + */ + +#include +#include +#include +#include + +#include +#include +#include + +typedef enum vlan_mbrCfgType_e +{ + MBRCFG_UNUSED = 0, + MBRCFG_USED_BY_VLAN, + MBRCFG_END +}vlan_mbrCfgType_t; + +static rtk_vlan_t vlan_mbrCfgVid[RTL8367C_CVIDXNO]; +static vlan_mbrCfgType_t vlan_mbrCfgUsage[RTL8367C_CVIDXNO]; + + +/* Function Name: + * dal_rtl8367c_vlan_init + * Description: + * Initialize VLAN. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * VLAN is disabled by default. User has to call this API to enable VLAN before + * using it. And It will set a default VLAN(vid 1) including all ports and set + * all ports PVID to the default VLAN. + */ +rtk_api_ret_t dal_rtl8367c_vlan_init(void) +{ + rtk_api_ret_t retVal; + rtk_uint32 i; + rtl8367c_user_vlan4kentry vlan4K; + rtl8367c_vlanconfiguser vlanMC; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Clean Database */ + memset(vlan_mbrCfgVid, 0x00, sizeof(rtk_vlan_t) * RTL8367C_CVIDXNO); + memset(vlan_mbrCfgUsage, 0x00, sizeof(vlan_mbrCfgType_t) * RTL8367C_CVIDXNO); + + /* clean 32 VLAN member configuration */ + for (i = 0; i <= RTL8367C_CVIDXMAX; i++) + { + vlanMC.evid = 0; + vlanMC.mbr = 0; + vlanMC.fid_msti = 0; + vlanMC.envlanpol = 0; + vlanMC.meteridx = 0; + vlanMC.vbpen = 0; + vlanMC.vbpri = 0; + if ((retVal = rtl8367c_setAsicVlanMemberConfig(i, &vlanMC)) != RT_ERR_OK) + return retVal; + } + + /* Set a default VLAN with vid 1 to 4K table for all ports */ + memset(&vlan4K, 0, sizeof(rtl8367c_user_vlan4kentry)); + vlan4K.vid = 1; + vlan4K.mbr = RTK_PHY_PORTMASK_ALL; + vlan4K.untag = RTK_PHY_PORTMASK_ALL; + vlan4K.fid_msti = 0; + if ((retVal = rtl8367c_setAsicVlan4kEntry(&vlan4K)) != RT_ERR_OK) + return retVal; + + /* Also set the default VLAN to 32 member configuration index 0 */ + memset(&vlanMC, 0, sizeof(rtl8367c_vlanconfiguser)); + vlanMC.evid = 1; + vlanMC.mbr = RTK_PHY_PORTMASK_ALL; + vlanMC.fid_msti = 0; + if ((retVal = rtl8367c_setAsicVlanMemberConfig(0, &vlanMC)) != RT_ERR_OK) + return retVal; + + /* Set all ports PVID to default VLAN and tag-mode to original */ + RTK_SCAN_ALL_PHY_PORTMASK(i) + { + if ((retVal = rtl8367c_setAsicVlanPortBasedVID(i, 0, 0)) != RT_ERR_OK) + return retVal; + if ((retVal = rtl8367c_setAsicVlanEgressTagMode(i, EG_TAG_MODE_ORI)) != RT_ERR_OK) + return retVal; + } + + /* Updata Databse */ + vlan_mbrCfgUsage[0] = MBRCFG_USED_BY_VLAN; + vlan_mbrCfgVid[0] = 1; + + /* Enable Ingress filter */ + RTK_SCAN_ALL_PHY_PORTMASK(i) + { + if ((retVal = rtl8367c_setAsicVlanIngressFilter(i, ENABLED)) != RT_ERR_OK) + return retVal; + } + + /* enable VLAN */ + if ((retVal = rtl8367c_setAsicVlanFilter(ENABLED)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_vlan_set + * Description: + * Set a VLAN entry. + * Input: + * vid - VLAN ID to configure. + * pVlanCfg - VLAN Configuration + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_L2_FID - Invalid FID. + * RT_ERR_VLAN_PORT_MBR_EXIST - Invalid member port mask. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * Note: + * + */ +rtk_api_ret_t dal_rtl8367c_vlan_set(rtk_vlan_t vid, rtk_vlan_cfg_t *pVlanCfg) +{ + rtk_api_ret_t retVal; + rtk_uint32 phyMbrPmask; + rtk_uint32 phyUntagPmask; + rtl8367c_user_vlan4kentry vlan4K; + rtl8367c_vlanconfiguser vlanMC; + rtk_uint32 idx; + rtk_uint32 empty_index = 0xffff; + rtk_uint32 update_evid = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* vid must be 0~8191 */ + if (vid > RTL8367C_EVIDMAX) + return RT_ERR_VLAN_VID; + + /* Null pointer check */ + if(NULL == pVlanCfg) + return RT_ERR_NULL_POINTER; + + /* Check port mask valid */ + RTK_CHK_PORTMASK_VALID(&(pVlanCfg->mbr)); + + if (vid <= RTL8367C_VIDMAX) + { + /* Check untag port mask valid */ + RTK_CHK_PORTMASK_VALID(&(pVlanCfg->untag)); + } + + /* IVL_EN */ + if(pVlanCfg->ivl_en >= RTK_ENABLE_END) + return RT_ERR_ENABLE; + + /* fid must be 0~15 */ + if(pVlanCfg->fid_msti > RTL8367C_FIDMAX) + return RT_ERR_L2_FID; + + /* Policing */ + if(pVlanCfg->envlanpol >= RTK_ENABLE_END) + return RT_ERR_ENABLE; + + /* Meter ID */ + if(pVlanCfg->meteridx > RTK_MAX_METER_ID) + return RT_ERR_INPUT; + + /* VLAN based priority */ + if(pVlanCfg->vbpen >= RTK_ENABLE_END) + return RT_ERR_ENABLE; + + /* Priority */ + if(pVlanCfg->vbpri > RTL8367C_PRIMAX) + return RT_ERR_INPUT; + + /* Get physical port mask */ + if(rtk_switch_portmask_L2P_get(&(pVlanCfg->mbr), &phyMbrPmask) != RT_ERR_OK) + return RT_ERR_FAILED; + + if(rtk_switch_portmask_L2P_get(&(pVlanCfg->untag), &phyUntagPmask) != RT_ERR_OK) + return RT_ERR_FAILED; + + if (vid <= RTL8367C_VIDMAX) + { + /* update 4K table */ + memset(&vlan4K, 0, sizeof(rtl8367c_user_vlan4kentry)); + vlan4K.vid = vid; + + vlan4K.mbr = (phyMbrPmask & 0xFFFF); + vlan4K.untag = (phyUntagPmask & 0xFFFF); + + vlan4K.ivl_svl = pVlanCfg->ivl_en; + vlan4K.fid_msti = pVlanCfg->fid_msti; + vlan4K.envlanpol = pVlanCfg->envlanpol; + vlan4K.meteridx = pVlanCfg->meteridx; + vlan4K.vbpen = pVlanCfg->vbpen; + vlan4K.vbpri = pVlanCfg->vbpri; + + if ((retVal = rtl8367c_setAsicVlan4kEntry(&vlan4K)) != RT_ERR_OK) + return retVal; + + /* Update Member configuration if exist */ + for (idx = 0; idx <= RTL8367C_CVIDXMAX; idx++) + { + if(vlan_mbrCfgUsage[idx] == MBRCFG_USED_BY_VLAN) + { + if(vlan_mbrCfgVid[idx] == vid) + { + /* Found! Update */ + if(phyMbrPmask == 0x00) + { + /* Member port = 0x00, delete this VLAN from Member Configuration */ + memset(&vlanMC, 0x00, sizeof(rtl8367c_vlanconfiguser)); + if ((retVal = rtl8367c_setAsicVlanMemberConfig(idx, &vlanMC)) != RT_ERR_OK) + return retVal; + + /* Clear Database */ + vlan_mbrCfgUsage[idx] = MBRCFG_UNUSED; + vlan_mbrCfgVid[idx] = 0; + } + else + { + /* Normal VLAN config, update to member configuration */ + vlanMC.evid = vid; + vlanMC.mbr = vlan4K.mbr; + vlanMC.fid_msti = vlan4K.fid_msti; + vlanMC.meteridx = vlan4K.meteridx; + vlanMC.envlanpol= vlan4K.envlanpol; + vlanMC.vbpen = vlan4K.vbpen; + vlanMC.vbpri = vlan4K.vbpri; + if ((retVal = rtl8367c_setAsicVlanMemberConfig(idx, &vlanMC)) != RT_ERR_OK) + return retVal; + } + + break; + } + } + } + } + else + { + /* vid > 4095 */ + for (idx = 0; idx <= RTL8367C_CVIDXMAX; idx++) + { + if(vlan_mbrCfgUsage[idx] == MBRCFG_USED_BY_VLAN) + { + if(vlan_mbrCfgVid[idx] == vid) + { + /* Found! Update */ + if(phyMbrPmask == 0x00) + { + /* Member port = 0x00, delete this VLAN from Member Configuration */ + memset(&vlanMC, 0x00, sizeof(rtl8367c_vlanconfiguser)); + if ((retVal = rtl8367c_setAsicVlanMemberConfig(idx, &vlanMC)) != RT_ERR_OK) + return retVal; + + /* Clear Database */ + vlan_mbrCfgUsage[idx] = MBRCFG_UNUSED; + vlan_mbrCfgVid[idx] = 0; + } + else + { + /* Normal VLAN config, update to member configuration */ + vlanMC.evid = vid; + vlanMC.mbr = phyMbrPmask; + vlanMC.fid_msti = pVlanCfg->fid_msti; + vlanMC.meteridx = pVlanCfg->meteridx; + vlanMC.envlanpol= pVlanCfg->envlanpol; + vlanMC.vbpen = pVlanCfg->vbpen; + vlanMC.vbpri = pVlanCfg->vbpri; + if ((retVal = rtl8367c_setAsicVlanMemberConfig(idx, &vlanMC)) != RT_ERR_OK) + return retVal; + + break; + } + + update_evid = 1; + } + } + + if(vlan_mbrCfgUsage[idx] == MBRCFG_UNUSED) + { + if(0xffff == empty_index) + empty_index = idx; + } + } + + /* doesn't find out same EVID entry and there is empty index in member configuration */ + if( (phyMbrPmask != 0x00) && (update_evid == 0) && (empty_index != 0xFFFF) ) + { + vlanMC.evid = vid; + vlanMC.mbr = phyMbrPmask; + vlanMC.fid_msti = pVlanCfg->fid_msti; + vlanMC.meteridx = pVlanCfg->meteridx; + vlanMC.envlanpol= pVlanCfg->envlanpol; + vlanMC.vbpen = pVlanCfg->vbpen; + vlanMC.vbpri = pVlanCfg->vbpri; + if ((retVal = rtl8367c_setAsicVlanMemberConfig(empty_index, &vlanMC)) != RT_ERR_OK) + return retVal; + + vlan_mbrCfgUsage[empty_index] = MBRCFG_USED_BY_VLAN; + vlan_mbrCfgVid[empty_index] = vid; + + } + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_vlan_get + * Description: + * Get a VLAN entry. + * Input: + * vid - VLAN ID to configure. + * Output: + * pVlanCfg - VLAN Configuration + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * Note: + * + */ +rtk_api_ret_t dal_rtl8367c_vlan_get(rtk_vlan_t vid, rtk_vlan_cfg_t *pVlanCfg) +{ + rtk_api_ret_t retVal; + rtk_uint32 phyMbrPmask; + rtk_uint32 phyUntagPmask; + rtl8367c_user_vlan4kentry vlan4K; + rtl8367c_vlanconfiguser vlanMC; + rtk_uint32 idx; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* vid must be 0~8191 */ + if (vid > RTL8367C_EVIDMAX) + return RT_ERR_VLAN_VID; + + /* Null pointer check */ + if(NULL == pVlanCfg) + return RT_ERR_NULL_POINTER; + + if (vid <= RTL8367C_VIDMAX) + { + vlan4K.vid = vid; + + if ((retVal = rtl8367c_getAsicVlan4kEntry(&vlan4K)) != RT_ERR_OK) + return retVal; + + phyMbrPmask = vlan4K.mbr; + phyUntagPmask = vlan4K.untag; + if(rtk_switch_portmask_P2L_get(phyMbrPmask, &(pVlanCfg->mbr)) != RT_ERR_OK) + return RT_ERR_FAILED; + + if(rtk_switch_portmask_P2L_get(phyUntagPmask, &(pVlanCfg->untag)) != RT_ERR_OK) + return RT_ERR_FAILED; + + pVlanCfg->ivl_en = vlan4K.ivl_svl; + pVlanCfg->fid_msti = vlan4K.fid_msti; + pVlanCfg->envlanpol = vlan4K.envlanpol; + pVlanCfg->meteridx = vlan4K.meteridx; + pVlanCfg->vbpen = vlan4K.vbpen; + pVlanCfg->vbpri = vlan4K.vbpri; + } + else + { + for (idx = 0; idx <= RTL8367C_CVIDXMAX; idx++) + { + if(vlan_mbrCfgUsage[idx] == MBRCFG_USED_BY_VLAN) + { + if(vlan_mbrCfgVid[idx] == vid) + { + if ((retVal = rtl8367c_getAsicVlanMemberConfig(idx, &vlanMC)) != RT_ERR_OK) + return retVal; + + phyMbrPmask = vlanMC.mbr; + if(rtk_switch_portmask_P2L_get(phyMbrPmask, &(pVlanCfg->mbr)) != RT_ERR_OK) + return RT_ERR_FAILED; + + pVlanCfg->untag.bits[0] = 0; + pVlanCfg->ivl_en = 0; + pVlanCfg->fid_msti = vlanMC.fid_msti; + pVlanCfg->envlanpol = vlanMC.envlanpol; + pVlanCfg->meteridx = vlanMC.meteridx; + pVlanCfg->vbpen = vlanMC.vbpen; + pVlanCfg->vbpri = vlanMC.vbpri; + } + } + } + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_vlan_egrFilterEnable_set + * Description: + * Set VLAN egress filter. + * Input: + * egrFilter - Egress filtering + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid input parameters. + * Note: + * + */ +rtk_api_ret_t dal_rtl8367c_vlan_egrFilterEnable_set(rtk_enable_t egrFilter) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(egrFilter >= RTK_ENABLE_END) + return RT_ERR_ENABLE; + + /* enable VLAN */ + if ((retVal = rtl8367c_setAsicVlanFilter((rtk_uint32)egrFilter)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_vlan_egrFilterEnable_get + * Description: + * Get VLAN egress filter. + * Input: + * pEgrFilter - Egress filtering + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - NULL Pointer. + * Note: + * + */ +rtk_api_ret_t dal_rtl8367c_vlan_egrFilterEnable_get(rtk_enable_t *pEgrFilter) +{ + rtk_api_ret_t retVal; + rtk_uint32 state; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pEgrFilter) + return RT_ERR_NULL_POINTER; + + /* enable VLAN */ + if ((retVal = rtl8367c_getAsicVlanFilter(&state)) != RT_ERR_OK) + return retVal; + + *pEgrFilter = (rtk_enable_t)state; + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_vlan_mbrCfg_set + * Description: + * Set a VLAN Member Configuration entry by index. + * Input: + * idx - Index of VLAN Member Configuration. + * pMbrcfg - VLAN member Configuration. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * Note: + * Set a VLAN Member Configuration entry by index. + */ +rtk_api_ret_t dal_rtl8367c_vlan_mbrCfg_set(rtk_uint32 idx, rtk_vlan_mbrcfg_t *pMbrcfg) +{ + rtk_api_ret_t retVal; + rtk_uint32 phyMbrPmask; + rtl8367c_vlanconfiguser mbrCfg; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Error check */ + if(pMbrcfg == NULL) + return RT_ERR_NULL_POINTER; + + if(idx > RTL8367C_CVIDXMAX) + return RT_ERR_INPUT; + + if(pMbrcfg->evid > RTL8367C_EVIDMAX) + return RT_ERR_INPUT; + + if(pMbrcfg->fid_msti > RTL8367C_FIDMAX) + return RT_ERR_L2_FID; + + if(pMbrcfg->envlanpol >= RTK_ENABLE_END) + return RT_ERR_ENABLE; + + if(pMbrcfg->meteridx > RTK_MAX_METER_ID) + return RT_ERR_FILTER_METER_ID; + + if(pMbrcfg->vbpen >= RTK_ENABLE_END) + return RT_ERR_ENABLE; + + if(pMbrcfg->vbpri > RTL8367C_PRIMAX) + return RT_ERR_QOS_INT_PRIORITY; + + /* Check port mask valid */ + RTK_CHK_PORTMASK_VALID(&(pMbrcfg->mbr)); + + mbrCfg.evid = pMbrcfg->evid; + mbrCfg.fid_msti = pMbrcfg->fid_msti; + mbrCfg.envlanpol = pMbrcfg->envlanpol; + mbrCfg.meteridx = pMbrcfg->meteridx; + mbrCfg.vbpen = pMbrcfg->vbpen; + mbrCfg.vbpri = pMbrcfg->vbpri; + + if(rtk_switch_portmask_L2P_get(&(pMbrcfg->mbr), &phyMbrPmask) != RT_ERR_OK) + return RT_ERR_FAILED; + + mbrCfg.mbr = phyMbrPmask; + + if ((retVal = rtl8367c_setAsicVlanMemberConfig(idx, &mbrCfg)) != RT_ERR_OK) + return retVal; + + /* Update Database */ + if( (mbrCfg.evid == 0) && (mbrCfg.mbr == 0) ) + { + vlan_mbrCfgUsage[idx] = MBRCFG_UNUSED; + vlan_mbrCfgVid[idx] = 0; + } + else + { + vlan_mbrCfgUsage[idx] = MBRCFG_USED_BY_VLAN; + vlan_mbrCfgVid[idx] = mbrCfg.evid; + } + + return RT_ERR_OK; + +} + +/* Function Name: + * dal_rtl8367c_vlan_mbrCfg_get + * Description: + * Get a VLAN Member Configuration entry by index. + * Input: + * idx - Index of VLAN Member Configuration. + * Output: + * pMbrcfg - VLAN member Configuration. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * Note: + * Get a VLAN Member Configuration entry by index. + */ +rtk_api_ret_t dal_rtl8367c_vlan_mbrCfg_get(rtk_uint32 idx, rtk_vlan_mbrcfg_t *pMbrcfg) +{ + rtk_api_ret_t retVal; + rtk_uint32 phyMbrPmask; + rtl8367c_vlanconfiguser mbrCfg; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Error check */ + if(pMbrcfg == NULL) + return RT_ERR_NULL_POINTER; + + if(idx > RTL8367C_CVIDXMAX) + return RT_ERR_INPUT; + + memset(&mbrCfg, 0x00, sizeof(rtl8367c_vlanconfiguser)); + if ((retVal = rtl8367c_getAsicVlanMemberConfig(idx, &mbrCfg)) != RT_ERR_OK) + return retVal; + + pMbrcfg->evid = mbrCfg.evid; + pMbrcfg->fid_msti = mbrCfg.fid_msti; + pMbrcfg->envlanpol = mbrCfg.envlanpol; + pMbrcfg->meteridx = mbrCfg.meteridx; + pMbrcfg->vbpen = mbrCfg.vbpen; + pMbrcfg->vbpri = mbrCfg.vbpri; + + phyMbrPmask = mbrCfg.mbr; + if(rtk_switch_portmask_P2L_get(phyMbrPmask, &(pMbrcfg->mbr)) != RT_ERR_OK) + return RT_ERR_FAILED; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_vlan_portPvid_set + * Description: + * Set port to specified VLAN ID(PVID). + * Input: + * port - Port id. + * pvid - Specified VLAN ID. + * priority - 802.1p priority for the PVID. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_VLAN_PRIORITY - Invalid priority. + * RT_ERR_VLAN_ENTRY_NOT_FOUND - VLAN entry not found. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * Note: + * The API is used for Port-based VLAN. The untagged frame received from the + * port will be classified to the specified VLAN and assigned to the specified priority. + */ +rtk_api_ret_t dal_rtl8367c_vlan_portPvid_set(rtk_port_t port, rtk_vlan_t pvid, rtk_pri_t priority) +{ + rtk_api_ret_t retVal; + rtk_uint32 index; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + /* vid must be 0~8191 */ + if (pvid > RTL8367C_EVIDMAX) + return RT_ERR_VLAN_VID; + + /* priority must be 0~7 */ + if (priority > RTL8367C_PRIMAX) + return RT_ERR_VLAN_PRIORITY; + + if((retVal = dal_rtl8367c_vlan_checkAndCreateMbr(pvid, &index)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicVlanPortBasedVID(rtk_switch_port_L2P_get(port), index, priority)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_vlan_portPvid_get + * Description: + * Get VLAN ID(PVID) on specified port. + * Input: + * port - Port id. + * Output: + * pPvid - Specified VLAN ID. + * pPriority - 802.1p priority for the PVID. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get the PVID and 802.1p priority for the PVID of Port-based VLAN. + */ +rtk_api_ret_t dal_rtl8367c_vlan_portPvid_get(rtk_port_t port, rtk_vlan_t *pPvid, rtk_pri_t *pPriority) +{ + rtk_api_ret_t retVal; + rtk_uint32 index, pri; + rtl8367c_vlanconfiguser mbrCfg; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if(NULL == pPvid) + return RT_ERR_NULL_POINTER; + + if(NULL == pPriority) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicVlanPortBasedVID(rtk_switch_port_L2P_get(port), &index, &pri)) != RT_ERR_OK) + return retVal; + + memset(&mbrCfg, 0x00, sizeof(rtl8367c_vlanconfiguser)); + if ((retVal = rtl8367c_getAsicVlanMemberConfig(index, &mbrCfg)) != RT_ERR_OK) + return retVal; + + *pPvid = mbrCfg.evid; + *pPriority = pri; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_vlan_portIgrFilterEnable_set + * Description: + * Set VLAN ingress for each port. + * Input: + * port - Port id. + * igr_filter - VLAN ingress function enable status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * RT_ERR_ENABLE - Invalid enable input + * Note: + * The status of vlan ingress filter is as following: + * - DISABLED + * - ENABLED + * While VLAN function is enabled, ASIC will decide VLAN ID for each received frame and get belonged member + * ports from VLAN table. If received port is not belonged to VLAN member ports, ASIC will drop received frame if VLAN ingress function is enabled. + */ +rtk_api_ret_t dal_rtl8367c_vlan_portIgrFilterEnable_set(rtk_port_t port, rtk_enable_t igr_filter) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if (igr_filter >= RTK_ENABLE_END) + return RT_ERR_ENABLE; + + if ((retVal = rtl8367c_setAsicVlanIngressFilter(rtk_switch_port_L2P_get(port), igr_filter)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_vlan_portIgrFilterEnable_get + * Description: + * Get VLAN Ingress Filter + * Input: + * port - Port id. + * Output: + * pIgr_filter - VLAN ingress function enable status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can Get the VLAN ingress filter status. + * The status of vlan ingress filter is as following: + * - DISABLED + * - ENABLED + */ +rtk_api_ret_t dal_rtl8367c_vlan_portIgrFilterEnable_get(rtk_port_t port, rtk_enable_t *pIgr_filter) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if(NULL == pIgr_filter) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicVlanIngressFilter(rtk_switch_port_L2P_get(port), pIgr_filter)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_vlan_portAcceptFrameType_set + * Description: + * Set VLAN accept_frame_type + * Input: + * port - Port id. + * accept_frame_type - accept frame type + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_VLAN_ACCEPT_FRAME_TYPE - Invalid frame type. + * Note: + * The API is used for checking 802.1Q tagged frames. + * The accept frame type as following: + * - ACCEPT_FRAME_TYPE_ALL + * - ACCEPT_FRAME_TYPE_TAG_ONLY + * - ACCEPT_FRAME_TYPE_UNTAG_ONLY + */ +rtk_api_ret_t dal_rtl8367c_vlan_portAcceptFrameType_set(rtk_port_t port, rtk_vlan_acceptFrameType_t accept_frame_type) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if (accept_frame_type >= ACCEPT_FRAME_TYPE_END) + return RT_ERR_VLAN_ACCEPT_FRAME_TYPE; + + if ((retVal = rtl8367c_setAsicVlanAccpetFrameType(rtk_switch_port_L2P_get(port), (rtl8367c_accframetype)accept_frame_type)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_vlan_portAcceptFrameType_get + * Description: + * Get VLAN accept_frame_type + * Input: + * port - Port id. + * Output: + * pAccept_frame_type - accept frame type + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can Get the VLAN ingress filter. + * The accept frame type as following: + * - ACCEPT_FRAME_TYPE_ALL + * - ACCEPT_FRAME_TYPE_TAG_ONLY + * - ACCEPT_FRAME_TYPE_UNTAG_ONLY + */ +rtk_api_ret_t dal_rtl8367c_vlan_portAcceptFrameType_get(rtk_port_t port, rtk_vlan_acceptFrameType_t *pAccept_frame_type) +{ + rtk_api_ret_t retVal; + rtl8367c_accframetype acc_frm_type; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if(NULL == pAccept_frame_type) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicVlanAccpetFrameType(rtk_switch_port_L2P_get(port), &acc_frm_type)) != RT_ERR_OK) + return retVal; + + *pAccept_frame_type = (rtk_vlan_acceptFrameType_t)acc_frm_type; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_vlan_protoAndPortBasedVlan_add + * Description: + * Add the protocol-and-port-based vlan to the specified port of device. + * Input: + * port - Port id. + * pInfo - Protocol and port based VLAN configuration information. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * RT_ERR_VLAN_PRIORITY - Invalid priority. + * RT_ERR_TBL_FULL - Table is full. + * RT_ERR_OUT_OF_RANGE - input out of range. + * Note: + * The incoming packet which match the protocol-and-port-based vlan will use the configure vid for ingress pipeline + * The frame type is shown in the following: + * - FRAME_TYPE_ETHERNET + * - FRAME_TYPE_RFC1042 + * - FRAME_TYPE_LLCOTHER + */ +rtk_api_ret_t dal_rtl8367c_vlan_protoAndPortBasedVlan_add(rtk_port_t port, rtk_vlan_protoAndPortInfo_t *pInfo) +{ + rtk_api_ret_t retVal, i; + rtk_uint32 exist, empty, used, index; + rtl8367c_protocolgdatacfg ppb_data_cfg; + rtl8367c_protocolvlancfg ppb_vlan_cfg; + rtl8367c_provlan_frametype tmp; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if(NULL == pInfo) + return RT_ERR_NULL_POINTER; + + if (pInfo->proto_type > RTK_MAX_NUM_OF_PROTO_TYPE) + return RT_ERR_OUT_OF_RANGE; + + if (pInfo->frame_type >= FRAME_TYPE_END) + return RT_ERR_OUT_OF_RANGE; + + if (pInfo->cvid > RTL8367C_VIDMAX) + return RT_ERR_VLAN_VID; + + if (pInfo->cpri > RTL8367C_PRIMAX) + return RT_ERR_VLAN_PRIORITY; + + exist = 0xFF; + empty = 0xFF; + for (i = RTL8367C_PROTOVLAN_GIDX_MAX; i >= 0; i--) + { + if ((retVal = rtl8367c_getAsicVlanProtocolBasedGroupData(i, &ppb_data_cfg)) != RT_ERR_OK) + return retVal; + tmp = (rtl8367c_provlan_frametype)pInfo->frame_type; + if (ppb_data_cfg.etherType == pInfo->proto_type && ppb_data_cfg.frameType == tmp) + { + /*Already exist*/ + exist = i; + break; + } + else if (ppb_data_cfg.etherType == 0 && ppb_data_cfg.frameType == 0) + { + /*find empty index*/ + empty = i; + } + } + + used = 0xFF; + /*No empty and exist index*/ + if (0xFF == exist && 0xFF == empty) + return RT_ERR_TBL_FULL; + else if (existframe_type; + ppb_data_cfg.etherType = pInfo->proto_type; + if ((retVal = rtl8367c_setAsicVlanProtocolBasedGroupData(empty, &ppb_data_cfg)) != RT_ERR_OK) + return retVal; + used = empty; + } + else + return RT_ERR_FAILED; + + if((retVal = dal_rtl8367c_vlan_checkAndCreateMbr(pInfo->cvid, &index)) != RT_ERR_OK) + return retVal; + + ppb_vlan_cfg.vlan_idx = index; + ppb_vlan_cfg.valid = TRUE; + ppb_vlan_cfg.priority = pInfo->cpri; + if ((retVal = rtl8367c_setAsicVlanPortAndProtocolBased(rtk_switch_port_L2P_get(port), used, &ppb_vlan_cfg)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_vlan_protoAndPortBasedVlan_get + * Description: + * Get the protocol-and-port-based vlan to the specified port of device. + * Input: + * port - Port id. + * proto_type - protocol-and-port-based vlan protocol type. + * frame_type - protocol-and-port-based vlan frame type. + * Output: + * pInfo - Protocol and port based VLAN configuration information. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_TBL_FULL - Table is full. + * Note: + * The incoming packet which match the protocol-and-port-based vlan will use the configure vid for ingress pipeline + * The frame type is shown in the following: + * - FRAME_TYPE_ETHERNET + * - FRAME_TYPE_RFC1042 + * - FRAME_TYPE_LLCOTHER + */ +rtk_api_ret_t dal_rtl8367c_vlan_protoAndPortBasedVlan_get(rtk_port_t port, rtk_vlan_proto_type_t proto_type, rtk_vlan_protoVlan_frameType_t frame_type, rtk_vlan_protoAndPortInfo_t *pInfo) +{ + rtk_api_ret_t retVal; + rtk_uint32 i; + rtk_uint32 ppb_idx; + rtl8367c_protocolgdatacfg ppb_data_cfg; + rtl8367c_protocolvlancfg ppb_vlan_cfg; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if (proto_type > RTK_MAX_NUM_OF_PROTO_TYPE) + return RT_ERR_OUT_OF_RANGE; + + if (frame_type >= FRAME_TYPE_END) + return RT_ERR_OUT_OF_RANGE; + + ppb_idx = 0; + + for (i = 0; i<= RTL8367C_PROTOVLAN_GIDX_MAX; i++) + { + if ((retVal = rtl8367c_getAsicVlanProtocolBasedGroupData(i, &ppb_data_cfg)) != RT_ERR_OK) + return retVal; + + if ( (ppb_data_cfg.frameType == (rtl8367c_provlan_frametype)frame_type) && (ppb_data_cfg.etherType == proto_type) ) + { + ppb_idx = i; + break; + } + else if (RTL8367C_PROTOVLAN_GIDX_MAX == i) + return RT_ERR_TBL_FULL; + } + + if ((retVal = rtl8367c_getAsicVlanPortAndProtocolBased(rtk_switch_port_L2P_get(port), ppb_idx, &ppb_vlan_cfg)) != RT_ERR_OK) + return retVal; + + if (FALSE == ppb_vlan_cfg.valid) + return RT_ERR_FAILED; + + pInfo->frame_type = frame_type; + pInfo->proto_type = proto_type; + pInfo->cvid = vlan_mbrCfgVid[ppb_vlan_cfg.vlan_idx]; + pInfo->cpri = ppb_vlan_cfg.priority; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_vlan_protoAndPortBasedVlan_del + * Description: + * Delete the protocol-and-port-based vlan from the specified port of device. + * Input: + * port - Port id. + * proto_type - protocol-and-port-based vlan protocol type. + * frame_type - protocol-and-port-based vlan frame type. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_TBL_FULL - Table is full. + * Note: + * The incoming packet which match the protocol-and-port-based vlan will use the configure vid for ingress pipeline + * The frame type is shown in the following: + * - FRAME_TYPE_ETHERNET + * - FRAME_TYPE_RFC1042 + * - FRAME_TYPE_LLCOTHER + */ +rtk_api_ret_t dal_rtl8367c_vlan_protoAndPortBasedVlan_del(rtk_port_t port, rtk_vlan_proto_type_t proto_type, rtk_vlan_protoVlan_frameType_t frame_type) +{ + rtk_api_ret_t retVal; + rtk_uint32 i, bUsed; + rtk_uint32 ppb_idx; + rtl8367c_protocolgdatacfg ppb_data_cfg; + rtl8367c_protocolvlancfg ppb_vlan_cfg; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if (proto_type > RTK_MAX_NUM_OF_PROTO_TYPE) + return RT_ERR_OUT_OF_RANGE; + + if (frame_type >= FRAME_TYPE_END) + return RT_ERR_OUT_OF_RANGE; + + ppb_idx = 0; + + for (i = 0; i<= RTL8367C_PROTOVLAN_GIDX_MAX; i++) + { + if ((retVal = rtl8367c_getAsicVlanProtocolBasedGroupData(i, &ppb_data_cfg)) != RT_ERR_OK) + return retVal; + + if ( (ppb_data_cfg.frameType == (rtl8367c_provlan_frametype)frame_type) && (ppb_data_cfg.etherType == proto_type) ) + { + ppb_idx = i; + ppb_vlan_cfg.valid = FALSE; + ppb_vlan_cfg.vlan_idx = 0; + ppb_vlan_cfg.priority = 0; + if ((retVal = rtl8367c_setAsicVlanPortAndProtocolBased(rtk_switch_port_L2P_get(port), ppb_idx, &ppb_vlan_cfg)) != RT_ERR_OK) + return retVal; + } + } + + bUsed = FALSE; + RTK_SCAN_ALL_PHY_PORTMASK(i) + { + if ((retVal = rtl8367c_getAsicVlanPortAndProtocolBased(i, ppb_idx, &ppb_vlan_cfg)) != RT_ERR_OK) + return retVal; + + if (TRUE == ppb_vlan_cfg.valid) + { + bUsed = TRUE; + break; + } + } + + if (FALSE == bUsed) /*No Port use this PPB Index, Delete it*/ + { + ppb_data_cfg.etherType=0; + ppb_data_cfg.frameType=0; + if ((retVal = rtl8367c_setAsicVlanProtocolBasedGroupData(ppb_idx, &ppb_data_cfg)) != RT_ERR_OK) + return retVal; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_vlan_protoAndPortBasedVlan_delAll + * Description: + * Delete all protocol-and-port-based vlans from the specified port of device. + * Input: + * port - Port id. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_OUT_OF_RANGE - input out of range. + * Note: + * The incoming packet which match the protocol-and-port-based vlan will use the configure vid for ingress pipeline + * Delete all flow table protocol-and-port-based vlan entries. + */ +rtk_api_ret_t dal_rtl8367c_vlan_protoAndPortBasedVlan_delAll(rtk_port_t port) +{ + rtk_api_ret_t retVal; + rtk_uint32 i, j, bUsed[4]; + rtl8367c_protocolgdatacfg ppb_data_cfg; + rtl8367c_protocolvlancfg ppb_vlan_cfg; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + for (i = 0; i<= RTL8367C_PROTOVLAN_GIDX_MAX; i++) + { + ppb_vlan_cfg.valid = FALSE; + ppb_vlan_cfg.vlan_idx = 0; + ppb_vlan_cfg.priority = 0; + if ((retVal = rtl8367c_setAsicVlanPortAndProtocolBased(rtk_switch_port_L2P_get(port), i, &ppb_vlan_cfg)) != RT_ERR_OK) + return retVal; + } + + bUsed[0] = FALSE; + bUsed[1] = FALSE; + bUsed[2] = FALSE; + bUsed[3] = FALSE; + RTK_SCAN_ALL_PHY_PORTMASK(i) + { + for (j = 0; j <= RTL8367C_PROTOVLAN_GIDX_MAX; j++) + { + if ((retVal = rtl8367c_getAsicVlanPortAndProtocolBased(i,j, &ppb_vlan_cfg)) != RT_ERR_OK) + return retVal; + + if (TRUE == ppb_vlan_cfg.valid) + { + bUsed[j] = TRUE; + } + } + } + + for (i = 0; i<= RTL8367C_PROTOVLAN_GIDX_MAX; i++) + { + if (FALSE == bUsed[i]) /*No Port use this PPB Index, Delete it*/ + { + ppb_data_cfg.etherType=0; + ppb_data_cfg.frameType=0; + if ((retVal = rtl8367c_setAsicVlanProtocolBasedGroupData(i, &ppb_data_cfg)) != RT_ERR_OK) + return retVal; + } + } + + + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_vlan_tagMode_set + * Description: + * Set CVLAN egress tag mode + * Input: + * port - Port id. + * tag_mode - The egress tag mode. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * The API can set Egress tag mode. There are 4 mode for egress tag: + * - VLAN_TAG_MODE_ORIGINAL, + * - VLAN_TAG_MODE_KEEP_FORMAT, + * - VLAN_TAG_MODE_PRI. + * - VLAN_TAG_MODE_REAL_KEEP_FORMAT, + */ +rtk_api_ret_t dal_rtl8367c_vlan_tagMode_set(rtk_port_t port, rtk_vlan_tagMode_t tag_mode) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if (tag_mode >= VLAN_TAG_MODE_END) + return RT_ERR_PORT_ID; + + if ((retVal = rtl8367c_setAsicVlanEgressTagMode(rtk_switch_port_L2P_get(port), (rtl8367c_egtagmode)tag_mode)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_vlan_tagMode_get + * Description: + * Get CVLAN egress tag mode + * Input: + * port - Port id. + * Output: + * pTag_mode - The egress tag mode. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get Egress tag mode. There are 4 mode for egress tag: + * - VLAN_TAG_MODE_ORIGINAL, + * - VLAN_TAG_MODE_KEEP_FORMAT, + * - VLAN_TAG_MODE_PRI. + * - VLAN_TAG_MODE_REAL_KEEP_FORMAT, + */ +rtk_api_ret_t dal_rtl8367c_vlan_tagMode_get(rtk_port_t port, rtk_vlan_tagMode_t *pTag_mode) +{ + rtk_api_ret_t retVal; + rtl8367c_egtagmode mode; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if(NULL == pTag_mode) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicVlanEgressTagMode(rtk_switch_port_L2P_get(port), &mode)) != RT_ERR_OK) + return retVal; + + *pTag_mode = (rtk_vlan_tagMode_t)mode; + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_vlan_transparent_set + * Description: + * Set VLAN transparent mode + * Input: + * egr_port - Egress Port id. + * pIgr_pmask - Ingress Port Mask. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * None. + */ +rtk_api_ret_t dal_rtl8367c_vlan_transparent_set(rtk_port_t egr_port, rtk_portmask_t *pIgr_pmask) +{ + rtk_api_ret_t retVal; + rtk_uint32 pmask; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(egr_port); + + if(NULL == pIgr_pmask) + return RT_ERR_NULL_POINTER; + + RTK_CHK_PORTMASK_VALID(pIgr_pmask); + + if(rtk_switch_portmask_L2P_get(pIgr_pmask, &pmask) != RT_ERR_OK) + return RT_ERR_FAILED; + + if ((retVal = rtl8367c_setAsicVlanTransparent(rtk_switch_port_L2P_get(egr_port), pmask)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_vlan_transparent_get + * Description: + * Get VLAN transparent mode + * Input: + * egr_port - Egress Port id. + * Output: + * pIgr_pmask - Ingress Port Mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * None. + */ +rtk_api_ret_t dal_rtl8367c_vlan_transparent_get(rtk_port_t egr_port, rtk_portmask_t *pIgr_pmask) +{ + rtk_api_ret_t retVal; + rtk_uint32 pmask; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(egr_port); + + if(NULL == pIgr_pmask) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicVlanTransparent(rtk_switch_port_L2P_get(egr_port), &pmask)) != RT_ERR_OK) + return retVal; + + if(rtk_switch_portmask_P2L_get(pmask, pIgr_pmask) != RT_ERR_OK) + return RT_ERR_FAILED; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_vlan_keep_set + * Description: + * Set VLAN egress keep mode + * Input: + * egr_port - Egress Port id. + * pIgr_pmask - Ingress Port Mask. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * None. + */ +rtk_api_ret_t dal_rtl8367c_vlan_keep_set(rtk_port_t egr_port, rtk_portmask_t *pIgr_pmask) +{ + rtk_api_ret_t retVal; + rtk_uint32 pmask; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(egr_port); + + if(NULL == pIgr_pmask) + return RT_ERR_NULL_POINTER; + + RTK_CHK_PORTMASK_VALID(pIgr_pmask); + + if(rtk_switch_portmask_L2P_get(pIgr_pmask, &pmask) != RT_ERR_OK) + return RT_ERR_FAILED; + + if ((retVal = rtl8367c_setAsicVlanEgressKeep(rtk_switch_port_L2P_get(egr_port), pmask)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_vlan_keep_get + * Description: + * Get VLAN egress keep mode + * Input: + * egr_port - Egress Port id. + * Output: + * pIgr_pmask - Ingress Port Mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * None. + */ +rtk_api_ret_t dal_rtl8367c_vlan_keep_get(rtk_port_t egr_port, rtk_portmask_t *pIgr_pmask) +{ + rtk_api_ret_t retVal; + rtk_uint32 pmask; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(egr_port); + + if(NULL == pIgr_pmask) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicVlanEgressKeep(rtk_switch_port_L2P_get(egr_port), &pmask)) != RT_ERR_OK) + return retVal; + + if(rtk_switch_portmask_P2L_get(pmask, pIgr_pmask) != RT_ERR_OK) + return RT_ERR_FAILED; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_vlan_stg_set + * Description: + * Set spanning tree group instance of the vlan to the specified device + * Input: + * vid - Specified VLAN ID. + * stg - spanning tree group instance. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_MSTI - Invalid msti parameter + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * Note: + * The API can set spanning tree group instance of the vlan to the specified device. + */ +rtk_api_ret_t dal_rtl8367c_vlan_stg_set(rtk_vlan_t vid, rtk_stp_msti_id_t stg) +{ + rtk_api_ret_t retVal; + rtl8367c_user_vlan4kentry vlan4K; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* vid must be 0~4095 */ + if (vid > RTL8367C_VIDMAX) + return RT_ERR_VLAN_VID; + + /* priority must be 0~15 */ + if (stg > RTL8367C_MSTIMAX) + return RT_ERR_MSTI; + + /* update 4K table */ + vlan4K.vid = vid; + if ((retVal = rtl8367c_getAsicVlan4kEntry(&vlan4K)) != RT_ERR_OK) + return retVal; + + vlan4K.fid_msti= stg; + if ((retVal = rtl8367c_setAsicVlan4kEntry(&vlan4K)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_vlan_stg_get + * Description: + * Get spanning tree group instance of the vlan to the specified device + * Input: + * vid - Specified VLAN ID. + * Output: + * pStg - spanning tree group instance. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * Note: + * The API can get spanning tree group instance of the vlan to the specified device. + */ +rtk_api_ret_t dal_rtl8367c_vlan_stg_get(rtk_vlan_t vid, rtk_stp_msti_id_t *pStg) +{ + rtk_api_ret_t retVal; + rtl8367c_user_vlan4kentry vlan4K; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* vid must be 0~4095 */ + if (vid > RTL8367C_VIDMAX) + return RT_ERR_VLAN_VID; + + if(NULL == pStg) + return RT_ERR_NULL_POINTER; + + /* update 4K table */ + vlan4K.vid = vid; + if ((retVal = rtl8367c_getAsicVlan4kEntry(&vlan4K)) != RT_ERR_OK) + return retVal; + + *pStg = vlan4K.fid_msti; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_vlan_portFid_set + * Description: + * Set port-based filtering database + * Input: + * port - Port id. + * enable - ebable port-based FID + * fid - Specified filtering database. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_FID - Invalid fid. + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API can set port-based filtering database. If the function is enabled, all input + * packets will be assigned to the port-based fid regardless vlan tag. + */ +rtk_api_ret_t dal_rtl8367c_vlan_portFid_set(rtk_port_t port, rtk_enable_t enable, rtk_fid_t fid) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if (enable>=RTK_ENABLE_END) + return RT_ERR_ENABLE; + + /* fid must be 0~4095 */ + if (fid > RTK_FID_MAX) + return RT_ERR_L2_FID; + + if ((retVal = rtl8367c_setAsicPortBasedFidEn(rtk_switch_port_L2P_get(port), enable))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicPortBasedFid(rtk_switch_port_L2P_get(port), fid))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_vlan_portFid_get + * Description: + * Get port-based filtering database + * Input: + * port - Port id. + * Output: + * pEnable - ebable port-based FID + * pFid - Specified filtering database. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API can get port-based filtering database status. If the function is enabled, all input + * packets will be assigned to the port-based fid regardless vlan tag. + */ +rtk_api_ret_t dal_rtl8367c_vlan_portFid_get(rtk_port_t port, rtk_enable_t *pEnable, rtk_fid_t *pFid) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if(NULL == pEnable) + return RT_ERR_NULL_POINTER; + + if(NULL == pFid) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicPortBasedFidEn(rtk_switch_port_L2P_get(port), pEnable))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_getAsicPortBasedFid(rtk_switch_port_L2P_get(port), pFid))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_vlan_UntagDscpPriorityEnable_set + * Description: + * Set Untag DSCP priority assign + * Input: + * enable - state of Untag DSCP priority assign + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid input parameters. + * Note: + * + */ +rtk_api_ret_t dal_rtl8367c_vlan_UntagDscpPriorityEnable_set(rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(enable >= RTK_ENABLE_END) + return RT_ERR_ENABLE; + + if ((retVal = rtl8367c_setAsicVlanUntagDscpPriorityEn((rtk_uint32)enable)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_vlan_UntagDscpPriorityEnable_get + * Description: + * Get Untag DSCP priority assign + * Input: + * None + * Output: + * pEnable - state of Untag DSCP priority assign + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * + */ +rtk_api_ret_t dal_rtl8367c_vlan_UntagDscpPriorityEnable_get(rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + rtk_uint32 value; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pEnable) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicVlanUntagDscpPriorityEn(&value)) != RT_ERR_OK) + return retVal; + + *pEnable = (rtk_enable_t)value; + return RT_ERR_OK; +} + + + +/*Spanning Tree*/ +/* Function Name: + * dal_rtl8367c_stp_mstpState_set + * Description: + * Configure spanning tree state per each port. + * Input: + * port - Port id + * msti - Multiple spanning tree instance. + * stp_state - Spanning tree state for msti + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_MSTI - Invalid msti parameter. + * RT_ERR_MSTP_STATE - Invalid STP state. + * Note: + * System supports per-port multiple spanning tree state for each msti. + * There are four states supported by ASIC. + * - STP_STATE_DISABLED + * - STP_STATE_BLOCKING + * - STP_STATE_LEARNING + * - STP_STATE_FORWARDING + */ +rtk_api_ret_t dal_rtl8367c_stp_mstpState_set(rtk_stp_msti_id_t msti, rtk_port_t port, rtk_stp_state_t stp_state) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if (msti > RTK_MAX_NUM_OF_MSTI) + return RT_ERR_MSTI; + + if (stp_state >= STP_STATE_END) + return RT_ERR_MSTP_STATE; + + if ((retVal = rtl8367c_setAsicSpanningTreeStatus(rtk_switch_port_L2P_get(port), msti, stp_state)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_stp_mstpState_get + * Description: + * Get spanning tree state per each port. + * Input: + * port - Port id. + * msti - Multiple spanning tree instance. + * Output: + * pStp_state - Spanning tree state for msti + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_MSTI - Invalid msti parameter. + * Note: + * System supports per-port multiple spanning tree state for each msti. + * There are four states supported by ASIC. + * - STP_STATE_DISABLED + * - STP_STATE_BLOCKING + * - STP_STATE_LEARNING + * - STP_STATE_FORWARDING + */ +rtk_api_ret_t dal_rtl8367c_stp_mstpState_get(rtk_stp_msti_id_t msti, rtk_port_t port, rtk_stp_state_t *pStp_state) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if (msti > RTK_MAX_NUM_OF_MSTI) + return RT_ERR_MSTI; + + if(NULL == pStp_state) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicSpanningTreeStatus(rtk_switch_port_L2P_get(port), msti, pStp_state)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8367c_vlan_reservedVidAction_set + * Description: + * Set Action of VLAN ID = 0 & 4095 tagged packet + * Input: + * action_vid0 - Action for VID 0. + * action_vid4095 - Action for VID 4095. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + * + */ +rtk_api_ret_t dal_rtl8367c_vlan_reservedVidAction_set(rtk_vlan_resVidAction_t action_vid0, rtk_vlan_resVidAction_t action_vid4095) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(action_vid0 >= RESVID_ACTION_END) + return RT_ERR_INPUT; + + if(action_vid4095 >= RESVID_ACTION_END) + return RT_ERR_INPUT; + + if ((retVal = rtl8367c_setReservedVidAction((rtk_uint32)action_vid0, (rtk_uint32)action_vid4095)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_vlan_reservedVidAction_get + * Description: + * Get Action of VLAN ID = 0 & 4095 tagged packet + * Input: + * pAction_vid0 - Action for VID 0. + * pAction_vid4095 - Action for VID 4095. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - NULL Pointer + * Note: + * + */ +rtk_api_ret_t dal_rtl8367c_vlan_reservedVidAction_get(rtk_vlan_resVidAction_t *pAction_vid0, rtk_vlan_resVidAction_t *pAction_vid4095) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(pAction_vid0 == NULL) + return RT_ERR_NULL_POINTER; + + if(pAction_vid4095 == NULL) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getReservedVidAction((rtk_uint32 *)pAction_vid0, (rtk_uint32 *)pAction_vid4095)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_vlan_realKeepRemarkEnable_set + * Description: + * Set Real keep 1p remarking feature + * Input: + * enabled - State of 1p remarking at real keep packet + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + * + */ +rtk_api_ret_t dal_rtl8367c_vlan_realKeepRemarkEnable_set(rtk_enable_t enabled) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(enabled >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if ((retVal = rtl8367c_setRealKeepRemarkEn((rtk_uint32)enabled)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_vlan_realKeepRemarkEnable_get + * Description: + * Get Real keep 1p remarking feature + * Input: + * None. + * Output: + * pEnabled - State of 1p remarking at real keep packet + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + * + */ +rtk_api_ret_t dal_rtl8367c_vlan_realKeepRemarkEnable_get(rtk_enable_t *pEnabled) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pEnabled) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getRealKeepRemarkEn((rtk_uint32 *)pEnabled)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8367c_vlan_reset + * Description: + * Reset VLAN + * Input: + * None. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + * + */ +rtk_api_ret_t dal_rtl8367c_vlan_reset(void) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if ((retVal = rtl8367c_resetVlan()) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/*Don't lock mutex in following API*/ + +/* Function Name: + * dal_rtl8367c_vlan_checkAndCreateMbr + * Description: + * Check and create Member configuration and return index + * Input: + * vid - VLAN id. + * Output: + * pIndex - Member configuration index + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_VLAN_VID - Invalid VLAN ID. + * RT_ERR_VLAN_ENTRY_NOT_FOUND - VLAN not found + * RT_ERR_TBL_FULL - Member Configuration table full + * Note: + * + */ +rtk_api_ret_t dal_rtl8367c_vlan_checkAndCreateMbr(rtk_vlan_t vid, rtk_uint32 *pIndex) +{ + rtk_api_ret_t retVal; + rtl8367c_user_vlan4kentry vlan4K; + rtl8367c_vlanconfiguser vlanMC; + rtk_uint32 idx; + rtk_uint32 empty_idx = 0xFFFF; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* vid must be 0~8191 */ + if (vid > RTL8367C_EVIDMAX) + return RT_ERR_VLAN_VID; + + /* Null pointer check */ + if(NULL == pIndex) + return RT_ERR_NULL_POINTER; + + /* Get 4K VLAN */ + if (vid <= RTL8367C_VIDMAX) + { + memset(&vlan4K, 0x00, sizeof(rtl8367c_user_vlan4kentry)); + vlan4K.vid = vid; + if ((retVal = rtl8367c_getAsicVlan4kEntry(&vlan4K)) != RT_ERR_OK) + return retVal; + } + + /* Search exist entry */ + for (idx = 0; idx <= RTL8367C_CVIDXMAX; idx++) + { + if(vlan_mbrCfgUsage[idx] == MBRCFG_USED_BY_VLAN) + { + if(vlan_mbrCfgVid[idx] == vid) + { + /* Found! return index */ + *pIndex = idx; + return RT_ERR_OK; + } + } + } + + /* Not found, Read H/W Member Configuration table to update database */ + for (idx = 0; idx <= RTL8367C_CVIDXMAX; idx++) + { + if ((retVal = rtl8367c_getAsicVlanMemberConfig(idx, &vlanMC)) != RT_ERR_OK) + return retVal; + + if( (vlanMC.evid == 0) && (vlanMC.mbr == 0x00)) + { + vlan_mbrCfgUsage[idx] = MBRCFG_UNUSED; + vlan_mbrCfgVid[idx] = 0; + } + else + { + vlan_mbrCfgUsage[idx] = MBRCFG_USED_BY_VLAN; + vlan_mbrCfgVid[idx] = vlanMC.evid; + } + } + + /* Search exist entry again */ + for (idx = 0; idx <= RTL8367C_CVIDXMAX; idx++) + { + if(vlan_mbrCfgUsage[idx] == MBRCFG_USED_BY_VLAN) + { + if(vlan_mbrCfgVid[idx] == vid) + { + /* Found! return index */ + *pIndex = idx; + return RT_ERR_OK; + } + } + } + + /* try to look up an empty index */ + for (idx = 0; idx <= RTL8367C_CVIDXMAX; idx++) + { + if(vlan_mbrCfgUsage[idx] == MBRCFG_UNUSED) + { + empty_idx = idx; + break; + } + } + + if(empty_idx == 0xFFFF) + { + /* No empty index */ + return RT_ERR_TBL_FULL; + } + + if (vid > RTL8367C_VIDMAX) + { + /* > 4K, there is no 4K entry, create on member configuration directly */ + memset(&vlanMC, 0x00, sizeof(rtl8367c_vlanconfiguser)); + vlanMC.evid = vid; + if ((retVal = rtl8367c_setAsicVlanMemberConfig(empty_idx, &vlanMC)) != RT_ERR_OK) + return retVal; + } + else + { + /* Copy from 4K table */ + vlanMC.evid = vid; + vlanMC.mbr = vlan4K.mbr; + vlanMC.fid_msti = vlan4K.fid_msti; + vlanMC.meteridx= vlan4K.meteridx; + vlanMC.envlanpol= vlan4K.envlanpol; + vlanMC.vbpen = vlan4K.vbpen; + vlanMC.vbpri = vlan4K.vbpri; + if ((retVal = rtl8367c_setAsicVlanMemberConfig(empty_idx, &vlanMC)) != RT_ERR_OK) + return retVal; + } + + /* Update Database */ + vlan_mbrCfgUsage[empty_idx] = MBRCFG_USED_BY_VLAN; + vlan_mbrCfgVid[empty_idx] = vid; + + *pIndex = empty_idx; + return RT_ERR_OK; +} + + + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_vlan.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_vlan.h new file mode 100644 index 00000000..9364d0d5 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/dal_rtl8367c_vlan.h @@ -0,0 +1,806 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8367/RTL8367C switch high-level API + * + * Feature : The file includes Trap module high-layer VLAN defination + * + */ + +#ifndef __DAL_RTL8367C_VLAN_H__ +#define __DAL_RTL8367C_VLAN_H__ + +#include + +/* Function Name: + * dal_rtl8367c_vlan_init + * Description: + * Initialize VLAN. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * VLAN is disabled by default. User has to call this API to enable VLAN before + * using it. And It will set a default VLAN(vid 1) including all ports and set + * all ports PVID to the default VLAN. + */ +extern rtk_api_ret_t dal_rtl8367c_vlan_init(void); + +/* Function Name: + * dal_rtl8367c_vlan_set + * Description: + * Set a VLAN entry. + * Input: + * vid - VLAN ID to configure. + * pVlanCfg - VLAN Configuration + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_L2_FID - Invalid FID. + * RT_ERR_VLAN_PORT_MBR_EXIST - Invalid member port mask. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367c_vlan_set(rtk_vlan_t vid, rtk_vlan_cfg_t *pVlanCfg); + +/* Function Name: + * dal_rtl8367c_vlan_get + * Description: + * Get a VLAN entry. + * Input: + * vid - VLAN ID to configure. + * Output: + * pVlanCfg - VLAN Configuration + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367c_vlan_get(rtk_vlan_t vid, rtk_vlan_cfg_t *pVlanCfg); + +/* Function Name: + * dal_rtl8367c_vlan_egrFilterEnable_set + * Description: + * Set VLAN egress filter. + * Input: + * egrFilter - Egress filtering + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid input parameters. + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367c_vlan_egrFilterEnable_set(rtk_enable_t egrFilter); + +/* Function Name: + * dal_rtl8367c_vlan_egrFilterEnable_get + * Description: + * Get VLAN egress filter. + * Input: + * pEgrFilter - Egress filtering + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - NULL Pointer. + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367c_vlan_egrFilterEnable_get(rtk_enable_t *pEgrFilter); + +/* Function Name: + * dal_rtl8367c_vlan_mbrCfg_set + * Description: + * Set a VLAN Member Configuration entry by index. + * Input: + * idx - Index of VLAN Member Configuration. + * pMbrcfg - VLAN member Configuration. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * Note: + * Set a VLAN Member Configuration entry by index. + */ +extern rtk_api_ret_t dal_rtl8367c_vlan_mbrCfg_set(rtk_uint32 idx, rtk_vlan_mbrcfg_t *pMbrcfg); + +/* Function Name: + * dal_rtl8367c_vlan_mbrCfg_get + * Description: + * Get a VLAN Member Configuration entry by index. + * Input: + * idx - Index of VLAN Member Configuration. + * Output: + * pMbrcfg - VLAN member Configuration. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * Note: + * Get a VLAN Member Configuration entry by index. + */ +extern rtk_api_ret_t dal_rtl8367c_vlan_mbrCfg_get(rtk_uint32 idx, rtk_vlan_mbrcfg_t *pMbrcfg); + +/* Function Name: + * dal_rtl8367c_vlan_portPvid_set + * Description: + * Set port to specified VLAN ID(PVID). + * Input: + * port - Port id. + * pvid - Specified VLAN ID. + * priority - 802.1p priority for the PVID. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_VLAN_PRIORITY - Invalid priority. + * RT_ERR_VLAN_ENTRY_NOT_FOUND - VLAN entry not found. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * Note: + * The API is used for Port-based VLAN. The untagged frame received from the + * port will be classified to the specified VLAN and assigned to the specified priority. + */ +extern rtk_api_ret_t dal_rtl8367c_vlan_portPvid_set(rtk_port_t port, rtk_vlan_t pvid, rtk_pri_t priority); + +/* Function Name: + * dal_rtl8367c_vlan_portPvid_get + * Description: + * Get VLAN ID(PVID) on specified port. + * Input: + * port - Port id. + * Output: + * pPvid - Specified VLAN ID. + * pPriority - 802.1p priority for the PVID. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get the PVID and 802.1p priority for the PVID of Port-based VLAN. + */ +extern rtk_api_ret_t dal_rtl8367c_vlan_portPvid_get(rtk_port_t port, rtk_vlan_t *pPvid, rtk_pri_t *pPriority); + +/* Function Name: + * dal_rtl8367c_vlan_portIgrFilterEnable_set + * Description: + * Set VLAN ingress for each port. + * Input: + * port - Port id. + * igr_filter - VLAN ingress function enable status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * RT_ERR_ENABLE - Invalid enable input + * Note: + * The status of vlan ingress filter is as following: + * - DISABLED + * - ENABLED + * While VLAN function is enabled, ASIC will decide VLAN ID for each received frame and get belonged member + * ports from VLAN table. If received port is not belonged to VLAN member ports, ASIC will drop received frame if VLAN ingress function is enabled. + */ +extern rtk_api_ret_t dal_rtl8367c_vlan_portIgrFilterEnable_set(rtk_port_t port, rtk_enable_t igr_filter); + +/* Function Name: + * dal_rtl8367c_vlan_portIgrFilterEnable_get + * Description: + * Get VLAN Ingress Filter + * Input: + * port - Port id. + * Output: + * pIgr_filter - VLAN ingress function enable status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can Get the VLAN ingress filter status. + * The status of vlan ingress filter is as following: + * - DISABLED + * - ENABLED + */ +extern rtk_api_ret_t dal_rtl8367c_vlan_portIgrFilterEnable_get(rtk_port_t port, rtk_enable_t *pIgr_filter); + +/* Function Name: + * dal_rtl8367c_vlan_portAcceptFrameType_set + * Description: + * Set VLAN accept_frame_type + * Input: + * port - Port id. + * accept_frame_type - accept frame type + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_VLAN_ACCEPT_FRAME_TYPE - Invalid frame type. + * Note: + * The API is used for checking 802.1Q tagged frames. + * The accept frame type as following: + * - ACCEPT_FRAME_TYPE_ALL + * - ACCEPT_FRAME_TYPE_TAG_ONLY + * - ACCEPT_FRAME_TYPE_UNTAG_ONLY + */ +extern rtk_api_ret_t dal_rtl8367c_vlan_portAcceptFrameType_set(rtk_port_t port, rtk_vlan_acceptFrameType_t accept_frame_type); + +/* Function Name: + * dal_rtl8367c_vlan_portAcceptFrameType_get + * Description: + * Get VLAN accept_frame_type + * Input: + * port - Port id. + * Output: + * pAccept_frame_type - accept frame type + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can Get the VLAN ingress filter. + * The accept frame type as following: + * - ACCEPT_FRAME_TYPE_ALL + * - ACCEPT_FRAME_TYPE_TAG_ONLY + * - ACCEPT_FRAME_TYPE_UNTAG_ONLY + */ +extern rtk_api_ret_t dal_rtl8367c_vlan_portAcceptFrameType_get(rtk_port_t port, rtk_vlan_acceptFrameType_t *pAccept_frame_type); + +/* Function Name: + * dal_rtl8367c_vlan_tagMode_set + * Description: + * Set CVLAN egress tag mode + * Input: + * port - Port id. + * tag_mode - The egress tag mode. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * The API can set Egress tag mode. There are 4 mode for egress tag: + * - VLAN_TAG_MODE_ORIGINAL, + * - VLAN_TAG_MODE_KEEP_FORMAT, + * - VLAN_TAG_MODE_PRI. + * - VLAN_TAG_MODE_REAL_KEEP_FORMAT, + */ +extern rtk_api_ret_t dal_rtl8367c_vlan_tagMode_set(rtk_port_t port, rtk_vlan_tagMode_t tag_mode); + +/* Function Name: + * dal_rtl8367c_vlan_tagMode_get + * Description: + * Get CVLAN egress tag mode + * Input: + * port - Port id. + * Output: + * pTag_mode - The egress tag mode. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get Egress tag mode. There are 4 mode for egress tag: + * - VLAN_TAG_MODE_ORIGINAL, + * - VLAN_TAG_MODE_KEEP_FORMAT, + * - VLAN_TAG_MODE_PRI. + * - VLAN_TAG_MODE_REAL_KEEP_FORMAT, + */ +extern rtk_api_ret_t dal_rtl8367c_vlan_tagMode_get(rtk_port_t port, rtk_vlan_tagMode_t *pTag_mode); + +/* Function Name: + * dal_rtl8367c_vlan_transparent_set + * Description: + * Set VLAN transparent mode + * Input: + * egr_port - Egress Port id. + * pIgr_pmask - Ingress Port Mask. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * None. + */ +extern rtk_api_ret_t dal_rtl8367c_vlan_transparent_set(rtk_port_t egr_port, rtk_portmask_t *pIgr_pmask); + +/* Function Name: + * dal_rtl8367c_vlan_transparent_get + * Description: + * Get VLAN transparent mode + * Input: + * egr_port - Egress Port id. + * Output: + * pIgr_pmask - Ingress Port Mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * None. + */ +extern rtk_api_ret_t dal_rtl8367c_vlan_transparent_get(rtk_port_t egr_port, rtk_portmask_t *pIgr_pmask); + +/* Function Name: + * dal_rtl8367c_vlan_keep_set + * Description: + * Set VLAN egress keep mode + * Input: + * egr_port - Egress Port id. + * pIgr_pmask - Ingress Port Mask. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * None. + */ +extern rtk_api_ret_t dal_rtl8367c_vlan_keep_set(rtk_port_t egr_port, rtk_portmask_t *pIgr_pmask); + +/* Function Name: + * dal_rtl8367c_vlan_keep_get + * Description: + * Get VLAN egress keep mode + * Input: + * egr_port - Egress Port id. + * Output: + * pIgr_pmask - Ingress Port Mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * None. + */ +extern rtk_api_ret_t dal_rtl8367c_vlan_keep_get(rtk_port_t egr_port, rtk_portmask_t *pIgr_pmask); + +/* Function Name: + * dal_rtl8367c_vlan_stg_set + * Description: + * Set spanning tree group instance of the vlan to the specified device + * Input: + * vid - Specified VLAN ID. + * stg - spanning tree group instance. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_MSTI - Invalid msti parameter + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * Note: + * The API can set spanning tree group instance of the vlan to the specified device. + */ +extern rtk_api_ret_t dal_rtl8367c_vlan_stg_set(rtk_vlan_t vid, rtk_stp_msti_id_t stg); + +/* Function Name: + * dal_rtl8367c_vlan_stg_get + * Description: + * Get spanning tree group instance of the vlan to the specified device + * Input: + * vid - Specified VLAN ID. + * Output: + * pStg - spanning tree group instance. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * Note: + * The API can get spanning tree group instance of the vlan to the specified device. + */ +extern rtk_api_ret_t dal_rtl8367c_vlan_stg_get(rtk_vlan_t vid, rtk_stp_msti_id_t *pStg); + +/* Function Name: + * dal_rtl8367c_vlan_protoAndPortBasedVlan_add + * Description: + * Add the protocol-and-port-based vlan to the specified port of device. + * Input: + * port - Port id. + * pInfo - Protocol and port based VLAN configuration information. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * RT_ERR_VLAN_PRIORITY - Invalid priority. + * RT_ERR_TBL_FULL - Table is full. + * RT_ERR_OUT_OF_RANGE - input out of range. + * Note: + * The incoming packet which match the protocol-and-port-based vlan will use the configure vid for ingress pipeline + * The frame type is shown in the following: + * - FRAME_TYPE_ETHERNET + * - FRAME_TYPE_RFC1042 + * - FRAME_TYPE_LLCOTHER + */ +extern rtk_api_ret_t dal_rtl8367c_vlan_protoAndPortBasedVlan_add(rtk_port_t port, rtk_vlan_protoAndPortInfo_t *pInfo); + +/* Function Name: + * dal_rtl8367c_vlan_protoAndPortBasedVlan_get + * Description: + * Get the protocol-and-port-based vlan to the specified port of device. + * Input: + * port - Port id. + * proto_type - protocol-and-port-based vlan protocol type. + * frame_type - protocol-and-port-based vlan frame type. + * Output: + * pInfo - Protocol and port based VLAN configuration information. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_TBL_FULL - Table is full. + * Note: + * The incoming packet which match the protocol-and-port-based vlan will use the configure vid for ingress pipeline + * The frame type is shown in the following: + * - FRAME_TYPE_ETHERNET + * - FRAME_TYPE_RFC1042 + * - FRAME_TYPE_LLCOTHER + */ +extern rtk_api_ret_t dal_rtl8367c_vlan_protoAndPortBasedVlan_get(rtk_port_t port, rtk_vlan_proto_type_t proto_type, rtk_vlan_protoVlan_frameType_t frame_type, rtk_vlan_protoAndPortInfo_t *pInfo); + +/* Function Name: + * dal_rtl8367c_vlan_protoAndPortBasedVlan_del + * Description: + * Delete the protocol-and-port-based vlan from the specified port of device. + * Input: + * port - Port id. + * proto_type - protocol-and-port-based vlan protocol type. + * frame_type - protocol-and-port-based vlan frame type. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_TBL_FULL - Table is full. + * Note: + * The incoming packet which match the protocol-and-port-based vlan will use the configure vid for ingress pipeline + * The frame type is shown in the following: + * - FRAME_TYPE_ETHERNET + * - FRAME_TYPE_RFC1042 + * - FRAME_TYPE_LLCOTHER + */ +extern rtk_api_ret_t dal_rtl8367c_vlan_protoAndPortBasedVlan_del(rtk_port_t port, rtk_vlan_proto_type_t proto_type, rtk_vlan_protoVlan_frameType_t frame_type); + +/* Function Name: + * dal_rtl8367c_vlan_protoAndPortBasedVlan_delAll + * Description: + * Delete all protocol-and-port-based vlans from the specified port of device. + * Input: + * port - Port id. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_OUT_OF_RANGE - input out of range. + * Note: + * The incoming packet which match the protocol-and-port-based vlan will use the configure vid for ingress pipeline + * Delete all flow table protocol-and-port-based vlan entries. + */ +extern rtk_api_ret_t dal_rtl8367c_vlan_protoAndPortBasedVlan_delAll(rtk_port_t port); + +/* Function Name: + * dal_rtl8367c_vlan_portFid_set + * Description: + * Set port-based filtering database + * Input: + * port - Port id. + * enable - ebable port-based FID + * fid - Specified filtering database. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_FID - Invalid fid. + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API can set port-based filtering database. If the function is enabled, all input + * packets will be assigned to the port-based fid regardless vlan tag. + */ +extern rtk_api_ret_t dal_rtl8367c_vlan_portFid_set(rtk_port_t port, rtk_enable_t enable, rtk_fid_t fid); + +/* Function Name: + * dal_rtl8367c_vlan_portFid_get + * Description: + * Get port-based filtering database + * Input: + * port - Port id. + * Output: + * pEnable - ebable port-based FID + * pFid - Specified filtering database. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API can get port-based filtering database status. If the function is enabled, all input + * packets will be assigned to the port-based fid regardless vlan tag. + */ +extern rtk_api_ret_t dal_rtl8367c_vlan_portFid_get(rtk_port_t port, rtk_enable_t *pEnable, rtk_fid_t *pFid); + +/* Function Name: + * dal_rtl8367c_vlan_UntagDscpPriorityEnable_set + * Description: + * Set Untag DSCP priority assign + * Input: + * enable - state of Untag DSCP priority assign + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid input parameters. + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367c_vlan_UntagDscpPriorityEnable_set(rtk_enable_t enable); + +/* Function Name: + * dal_rtl8367c_vlan_UntagDscpPriorityEnable_get + * Description: + * Get Untag DSCP priority assign + * Input: + * None + * Output: + * pEnable - state of Untag DSCP priority assign + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367c_vlan_UntagDscpPriorityEnable_get(rtk_enable_t *pEnable); + + +/*Spanning Tree*/ +/* Function Name: + * dal_rtl8367c_stp_mstpState_set + * Description: + * Configure spanning tree state per each port. + * Input: + * port - Port id + * msti - Multiple spanning tree instance. + * stp_state - Spanning tree state for msti + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_MSTI - Invalid msti parameter. + * RT_ERR_MSTP_STATE - Invalid STP state. + * Note: + * System supports per-port multiple spanning tree state for each msti. + * There are four states supported by ASIC. + * - STP_STATE_DISABLED + * - STP_STATE_BLOCKING + * - STP_STATE_LEARNING + * - STP_STATE_FORWARDING + */ +extern rtk_api_ret_t dal_rtl8367c_stp_mstpState_set(rtk_stp_msti_id_t msti, rtk_port_t port, rtk_stp_state_t stp_state); + +/* Function Name: + * dal_rtl8367c_stp_mstpState_get + * Description: + * Get spanning tree state per each port. + * Input: + * port - Port id. + * msti - Multiple spanning tree instance. + * Output: + * pStp_state - Spanning tree state for msti + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_MSTI - Invalid msti parameter. + * Note: + * System supports per-port multiple spanning tree state for each msti. + * There are four states supported by ASIC. + * - STP_STATE_DISABLED + * - STP_STATE_BLOCKING + * - STP_STATE_LEARNING + * - STP_STATE_FORWARDING + */ +extern rtk_api_ret_t dal_rtl8367c_stp_mstpState_get(rtk_stp_msti_id_t msti, rtk_port_t port, rtk_stp_state_t *pStp_state); + +/* Function Name: + * dal_rtl8367c_vlan_checkAndCreateMbr + * Description: + * Check and create Member configuration and return index + * Input: + * vid - VLAN id. + * Output: + * pIndex - Member configuration index + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_VLAN_VID - Invalid VLAN ID. + * RT_ERR_VLAN_ENTRY_NOT_FOUND - VLAN not found + * RT_ERR_TBL_FULL - Member Configuration table full + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367c_vlan_checkAndCreateMbr(rtk_vlan_t vid, rtk_uint32 *pIndex); + +/* Function Name: + * dal_rtl8367c_vlan_reservedVidAction_set + * Description: + * Set Action of VLAN ID = 0 & 4095 tagged packet + * Input: + * action_vid0 - Action for VID 0. + * action_vid4095 - Action for VID 4095. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367c_vlan_reservedVidAction_set(rtk_vlan_resVidAction_t action_vid0, rtk_vlan_resVidAction_t action_vid4095); + +/* Function Name: + * dal_rtl8367c_vlan_reservedVidAction_get + * Description: + * Get Action of VLAN ID = 0 & 4095 tagged packet + * Input: + * pAction_vid0 - Action for VID 0. + * pAction_vid4095 - Action for VID 4095. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - NULL Pointer + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367c_vlan_reservedVidAction_get(rtk_vlan_resVidAction_t *pAction_vid0, rtk_vlan_resVidAction_t *pAction_vid4095); + +/* Function Name: + * dal_rtl8367c_vlan_realKeepRemarkEnable_set + * Description: + * Set Real keep 1p remarking feature + * Input: + * enabled - State of 1p remarking at real keep packet + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367c_vlan_realKeepRemarkEnable_set(rtk_enable_t enabled); + +/* Function Name: + * dal_rtl8367c_vlan_realKeepRemarkEnable_get + * Description: + * Get Real keep 1p remarking feature + * Input: + * None. + * Output: + * pEnabled - State of 1p remarking at real keep packet + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367c_vlan_realKeepRemarkEnable_get(rtk_enable_t *pEnabled); + +/* Function Name: + * dal_rtl8367c_vlan_reset + * Description: + * Reset VLAN + * Input: + * None. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + * + */ +rtk_api_ret_t dal_rtl8367c_vlan_reset(void); + +#endif /* __DAL_RTL8367C_VLAN_H__ */ diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv.c new file mode 100644 index 00000000..192aca24 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv.c @@ -0,0 +1,642 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTL8367C switch high-level API for RTL8367C + * Feature : + * + */ + +#include + +#if defined(RTK_X86_ASICDRV) +#include +#else +#include +#endif +#include + +/*for driver verify testing only*/ +#ifdef CONFIG_RTL8367C_ASICDRV_TEST +#define CLE_VIRTUAL_REG_SIZE 0x10000 +rtk_uint16 CleVirtualReg[CLE_VIRTUAL_REG_SIZE]; +#endif + +#if defined(CONFIG_RTL865X_CLE) || defined (RTK_X86_CLE) +extern rtk_uint32 cleDebuggingDisplay; +#endif + +#ifdef EMBEDDED_SUPPORT +extern void setReg(rtk_uint16, rtk_uint16); +extern rtk_uint16 getReg(rtk_uint16); +#endif + +/* Function Name: + * rtl8367c_setAsicRegBit + * Description: + * Set a bit value of a specified register + * Input: + * reg - register's address + * bit - bit location + * value - value to set. It can be value 0 or 1. + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter + * Note: + * Set a bit of a specified register to 1 or 0. + */ +ret_t rtl8367c_setAsicRegBit(rtk_uint32 reg, rtk_uint32 bit, rtk_uint32 value) +{ + +#if defined(RTK_X86_ASICDRV) + rtk_uint32 regData; + ret_t retVal; + + if(bit >= RTL8367C_REGBITLENGTH) + return RT_ERR_INPUT; + + retVal = Access_Read(reg, 2, ®Data); + if(TRUE != retVal) + return RT_ERR_SMI; + + if(0x8367B == cleDebuggingDisplay) + PRINT("R[0x%4.4x]=0x%4.4x\n", reg, regData); + + if(value) + regData = regData | (1 << bit); + else + regData = regData & (~(1 << bit)); + + retVal = Access_Write(reg,2, regData); + if(TRUE != retVal) + return RT_ERR_SMI; + + if(0x8367B == cleDebuggingDisplay) + PRINT("W[0x%4.4x]=0x%4.4x\n", reg, regData); + + +#elif defined(CONFIG_RTL8367C_ASICDRV_TEST) + + if(bit >= RTL8367C_REGBITLENGTH) + return RT_ERR_INPUT; + + else if(reg >= CLE_VIRTUAL_REG_SIZE) + return RT_ERR_OUT_OF_RANGE; + + if(value) + { + CleVirtualReg[reg] = CleVirtualReg[reg] | (1 << bit); + } + else + { + CleVirtualReg[reg] = CleVirtualReg[reg] & (~(1 << bit)); + } + + if(0x8367B == cleDebuggingDisplay) + PRINT("W[0x%4.4x]=0x%4.4x\n", reg, CleVirtualReg[reg]); + +#elif defined(EMBEDDED_SUPPORT) + rtk_uint16 tmp; + + if(reg > RTL8367C_REGDATAMAX || value > 1) + return RT_ERR_INPUT; + + tmp = getReg(reg); + tmp &= (1 << bitIdx); + tmp |= (value << bitIdx); + setReg(reg, tmp); + +#else + rtk_uint32 regData; + ret_t retVal; + + if(bit >= RTL8367C_REGBITLENGTH) + return RT_ERR_INPUT; + + retVal = rtl8367c_smi_read(reg, ®Data); + if(retVal != RT_ERR_OK) + return RT_ERR_SMI; + + #ifdef CONFIG_RTL865X_CLE + if(0x8367B == cleDebuggingDisplay) + PRINT("R[0x%4.4x]=0x%4.4x\n", reg, regData); + #endif + if(value) + regData = regData | (1 << bit); + else + regData = regData & (~(1 << bit)); + + retVal = rtl8367c_smi_write(reg, regData); + if(retVal != RT_ERR_OK) + return RT_ERR_SMI; + + #ifdef CONFIG_RTL865X_CLE + if(0x8367B == cleDebuggingDisplay) + PRINT("W[0x%4.4x]=0x%4.4x\n", reg, regData); + #endif + +#endif + return RT_ERR_OK; +} +/* Function Name: + * rtl8367c_getAsicRegBit + * Description: + * Get a bit value of a specified register + * Input: + * reg - register's address + * bit - bit location + * value - value to get. + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter + * Note: + * None + */ +ret_t rtl8367c_getAsicRegBit(rtk_uint32 reg, rtk_uint32 bit, rtk_uint32 *pValue) +{ + +#if defined(RTK_X86_ASICDRV) + + rtk_uint32 regData; + ret_t retVal; + + if(bit >= RTL8367C_REGBITLENGTH) + return RT_ERR_INPUT; + + retVal = Access_Read(reg, 2, ®Data); + if(TRUE != retVal) + return RT_ERR_SMI; + + *pValue = (regData & (0x1 << bit)) >> bit; + + if(0x8367B == cleDebuggingDisplay) + PRINT("R[0x%4.4x]=0x%4.4x\n", reg, regData); + +#elif defined(CONFIG_RTL8367C_ASICDRV_TEST) + + if(bit >= RTL8367C_REGBITLENGTH) + return RT_ERR_INPUT; + + if(reg >= CLE_VIRTUAL_REG_SIZE) + return RT_ERR_OUT_OF_RANGE; + + *pValue = (CleVirtualReg[reg] & (0x1 << bit)) >> bit; + + if(0x8367B == cleDebuggingDisplay) + PRINT("R[0x%4.4x]=0x%4.4x\n", reg, CleVirtualReg[reg]); + +#elif defined(EMBEDDED_SUPPORT) + rtk_uint16 tmp; + + if(reg > RTL8367C_REGDATAMAX ) + return RT_ERR_INPUT; + + tmp = getReg(reg); + tmp = tmp >> bitIdx; + tmp &= 1; + *value = tmp; +#else + rtk_uint32 regData; + ret_t retVal; + + retVal = rtl8367c_smi_read(reg, ®Data); + if(retVal != RT_ERR_OK) + return RT_ERR_SMI; + + #ifdef CONFIG_RTL865X_CLE + if(0x8367B == cleDebuggingDisplay) + PRINT("R[0x%4.4x]=0x%4.4x\n", reg, regData); + #endif + + *pValue = (regData & (0x1 << bit)) >> bit; + +#endif + return RT_ERR_OK; +} +/* Function Name: + * rtl8367c_setAsicRegBits + * Description: + * Set bits value of a specified register + * Input: + * reg - register's address + * bits - bits mask for setting + * value - bits value for setting + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter + * Note: + * Set bits of a specified register to value. Both bits and value are be treated as bit-mask + */ +ret_t rtl8367c_setAsicRegBits(rtk_uint32 reg, rtk_uint32 bits, rtk_uint32 value) +{ + +#if defined(RTK_X86_ASICDRV) + + rtk_uint32 regData; + ret_t retVal; + rtk_uint32 bitsShift; + rtk_uint32 valueShifted; + + if(bits >= (1 << RTL8367C_REGBITLENGTH) ) + return RT_ERR_INPUT; + + bitsShift = 0; + while(!(bits & (1 << bitsShift))) + { + bitsShift++; + if(bitsShift >= RTL8367C_REGBITLENGTH) + return RT_ERR_INPUT; + } + + valueShifted = value << bitsShift; + if(valueShifted > RTL8367C_REGDATAMAX) + return RT_ERR_INPUT; + + retVal = Access_Read(reg, 2, ®Data); + if(TRUE != retVal) + return RT_ERR_SMI; + + if(0x8367B == cleDebuggingDisplay) + PRINT("R[0x%4.4x]=0x%4.4x\n", reg, regData); + + regData = regData & (~bits); + regData = regData | (valueShifted & bits); + + retVal = Access_Write(reg,2, regData); + if(TRUE != retVal) + return RT_ERR_SMI; + + if(0x8367B == cleDebuggingDisplay) + PRINT("W[0x%4.4x]=0x%4.4x\n", reg, regData); + +#elif defined(CONFIG_RTL8367C_ASICDRV_TEST) + rtk_uint32 regData; + rtk_uint32 bitsShift; + rtk_uint32 valueShifted; + + if(bits >= (1 << RTL8367C_REGBITLENGTH) ) + return RT_ERR_INPUT; + + bitsShift = 0; + while(!(bits & (1 << bitsShift))) + { + bitsShift++; + if(bitsShift >= RTL8367C_REGBITLENGTH) + return RT_ERR_INPUT; + } + valueShifted = value << bitsShift; + + if(valueShifted > RTL8367C_REGDATAMAX) + return RT_ERR_INPUT; + + if(reg >= CLE_VIRTUAL_REG_SIZE) + return RT_ERR_OUT_OF_RANGE; + + regData = CleVirtualReg[reg] & (~bits); + regData = regData | (valueShifted & bits); + + CleVirtualReg[reg] = regData; + + if(0x8367B == cleDebuggingDisplay) + PRINT("W[0x%4.4x]=0x%4.4x\n", reg, regData); + +#elif defined(EMBEDDED_SUPPORT) + rtk_uint32 regData; + rtk_uint32 bitsShift; + rtk_uint32 valueShifted; + + if(reg > RTL8367C_REGDATAMAX ) + return RT_ERR_INPUT; + + if(bits >= (1 << RTL8367C_REGBITLENGTH) ) + return RT_ERR_INPUT; + + bitsShift = 0; + while(!(bits & (1 << bitsShift))) + { + bitsShift++; + if(bitsShift >= RTL8367C_REGBITLENGTH) + return RT_ERR_INPUT; + } + + valueShifted = value << bitsShift; + if(valueShifted > RTL8367C_REGDATAMAX) + return RT_ERR_INPUT; + + regData = getReg(reg); + regData = regData & (~bits); + regData = regData | (valueShifted & bits); + + setReg(reg, regData); + +#else + rtk_uint32 regData; + ret_t retVal; + rtk_uint32 bitsShift; + rtk_uint32 valueShifted; + + if(bits >= (1 << RTL8367C_REGBITLENGTH) ) + return RT_ERR_INPUT; + + bitsShift = 0; + while(!(bits & (1 << bitsShift))) + { + bitsShift++; + if(bitsShift >= RTL8367C_REGBITLENGTH) + return RT_ERR_INPUT; + } + valueShifted = value << bitsShift; + + if(valueShifted > RTL8367C_REGDATAMAX) + return RT_ERR_INPUT; + + retVal = rtl8367c_smi_read(reg, ®Data); + if(retVal != RT_ERR_OK) + return RT_ERR_SMI; + #ifdef CONFIG_RTL865X_CLE + if(0x8367B == cleDebuggingDisplay) + PRINT("R[0x%4.4x]=0x%4.4x\n", reg, regData); + #endif + + regData = regData & (~bits); + regData = regData | (valueShifted & bits); + + retVal = rtl8367c_smi_write(reg, regData); + if(retVal != RT_ERR_OK) + return RT_ERR_SMI; + #ifdef CONFIG_RTL865X_CLE + if(0x8367B == cleDebuggingDisplay) + PRINT("W[0x%4.4x]=0x%4.4x\n", reg, regData); + #endif +#endif + return RT_ERR_OK; +} +/* Function Name: + * rtl8367c_getAsicRegBits + * Description: + * Get bits value of a specified register + * Input: + * reg - register's address + * bits - bits mask for setting + * value - bits value for setting + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter + * Note: + * None + */ +ret_t rtl8367c_getAsicRegBits(rtk_uint32 reg, rtk_uint32 bits, rtk_uint32 *pValue) +{ + +#if defined(RTK_X86_ASICDRV) + + rtk_uint32 regData; + ret_t retVal; + rtk_uint32 bitsShift; + + if(bits >= (1 << RTL8367C_REGBITLENGTH) ) + return RT_ERR_INPUT; + + bitsShift = 0; + while(!(bits & (1 << bitsShift))) + { + bitsShift++; + if(bitsShift >= RTL8367C_REGBITLENGTH) + return RT_ERR_INPUT; + } + + retVal = Access_Read(reg, 2, ®Data); + if(TRUE != retVal) + return RT_ERR_SMI; + + *pValue = (regData & bits) >> bitsShift; + + if(0x8367B == cleDebuggingDisplay) + PRINT("R[0x%4.4x]=0x%4.4x\n", reg, regData); + +#elif defined(CONFIG_RTL8367C_ASICDRV_TEST) + rtk_uint32 bitsShift; + + if(bits >= (1 << RTL8367C_REGBITLENGTH) ) + return RT_ERR_INPUT; + + bitsShift = 0; + while(!(bits & (1 << bitsShift))) + { + bitsShift++; + if(bitsShift >= RTL8367C_REGBITLENGTH) + return RT_ERR_INPUT; + } + + if(reg >= CLE_VIRTUAL_REG_SIZE) + return RT_ERR_OUT_OF_RANGE; + + *pValue = (CleVirtualReg[reg] & bits) >> bitsShift; + + if(0x8367B == cleDebuggingDisplay) + PRINT("R[0x%4.4x]=0x%4.4x\n", reg, CleVirtualReg[reg]); + +#elif defined(EMBEDDED_SUPPORT) + rtk_uint32 regData; + rtk_uint32 bitsShift; + + if(reg > RTL8367C_REGDATAMAX ) + return RT_ERR_INPUT; + + if(bits >= (1UL << RTL8367C_REGBITLENGTH) ) + return RT_ERR_INPUT; + + bitsShift = 0; + while(!(bits & (1UL << bitsShift))) + { + bitsShift++; + if(bitsShift >= RTL8367C_REGBITLENGTH) + return RT_ERR_INPUT; + } + + regData = getReg(reg); + *value = (regData & bits) >> bitsShift; + +#else + rtk_uint32 regData; + ret_t retVal; + rtk_uint32 bitsShift; + + if(bits>= (1<= RTL8367C_REGBITLENGTH) + return RT_ERR_INPUT; + } + + retVal = rtl8367c_smi_read(reg, ®Data); + if(retVal != RT_ERR_OK) return RT_ERR_SMI; + + *pValue = (regData & bits) >> bitsShift; + #ifdef CONFIG_RTL865X_CLE + if(0x8367B == cleDebuggingDisplay) + PRINT("R[0x%4.4x]=0x%4.4x\n",reg, regData); + #endif + +#endif + return RT_ERR_OK; +} +/* Function Name: + * rtl8367c_setAsicReg + * Description: + * Set content of asic register + * Input: + * reg - register's address + * value - Value setting to register + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * The value will be set to ASIC mapping address only and it is always return RT_ERR_OK while setting un-mapping address registers + */ +ret_t rtl8367c_setAsicReg(rtk_uint32 reg, rtk_uint32 value) +{ +#if defined(RTK_X86_ASICDRV)/*RTK-CNSD2-NickWu-20061222: for x86 compile*/ + + ret_t retVal; + + retVal = Access_Write(reg,2,value); + if(TRUE != retVal) return RT_ERR_SMI; + + if(0x8367B == cleDebuggingDisplay) + PRINT("W[0x%4.4x]=0x%4.4x\n",reg,value); + +#elif defined(CONFIG_RTL8367C_ASICDRV_TEST) + + /*MIBs emulating*/ + if(reg == RTL8367C_REG_MIB_ADDRESS) + { + CleVirtualReg[RTL8367C_MIB_COUNTER_BASE_REG] = 0x1; + CleVirtualReg[RTL8367C_MIB_COUNTER_BASE_REG+1] = 0x2; + CleVirtualReg[RTL8367C_MIB_COUNTER_BASE_REG+2] = 0x3; + CleVirtualReg[RTL8367C_MIB_COUNTER_BASE_REG+3] = 0x4; + } + + if(reg >= CLE_VIRTUAL_REG_SIZE) + return RT_ERR_OUT_OF_RANGE; + + CleVirtualReg[reg] = value; + + if(0x8367B == cleDebuggingDisplay) + PRINT("W[0x%4.4x]=0x%4.4x\n",reg,CleVirtualReg[reg]); + +#elif defined(EMBEDDED_SUPPORT) + if(reg > RTL8367C_REGDATAMAX || value > RTL8367C_REGDATAMAX ) + return RT_ERR_INPUT; + + setReg(reg, value); + +#else + ret_t retVal; + + retVal = rtl8367c_smi_write(reg, value); + if(retVal != RT_ERR_OK) + return RT_ERR_SMI; + #ifdef CONFIG_RTL865X_CLE + if(0x8367B == cleDebuggingDisplay) + PRINT("W[0x%4.4x]=0x%4.4x\n",reg,value); + #endif + +#endif + + return RT_ERR_OK; +} +/* Function Name: + * rtl8367c_getAsicReg + * Description: + * Get content of asic register + * Input: + * reg - register's address + * value - Value setting to register + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * Value 0x0000 will be returned for ASIC un-mapping address + */ +ret_t rtl8367c_getAsicReg(rtk_uint32 reg, rtk_uint32 *pValue) +{ + +#if defined(RTK_X86_ASICDRV) + + rtk_uint32 regData; + ret_t retVal; + + retVal = Access_Read(reg, 2, ®Data); + if(TRUE != retVal) + return RT_ERR_SMI; + + *pValue = regData; + + if(0x8367B == cleDebuggingDisplay) + PRINT("R[0x%4.4x]=0x%4.4x\n", reg, regData); + +#elif defined(CONFIG_RTL8367C_ASICDRV_TEST) + if(reg >= CLE_VIRTUAL_REG_SIZE) + return RT_ERR_OUT_OF_RANGE; + + *pValue = CleVirtualReg[reg]; + + if(0x8367B == cleDebuggingDisplay) + PRINT("R[0x%4.4x]=0x%4.4x\n", reg, CleVirtualReg[reg]); + +#elif defined(EMBEDDED_SUPPORT) + if(reg > RTL8367C_REGDATAMAX ) + return RT_ERR_INPUT; + + *value = getReg(reg); + +#else + rtk_uint32 regData; + ret_t retVal; + + retVal = rtl8367c_smi_read(reg, ®Data); + if(retVal != RT_ERR_OK) + return RT_ERR_SMI; + + *pValue = regData; + #ifdef CONFIG_RTL865X_CLE + if(0x8367B == cleDebuggingDisplay) + PRINT("R[0x%4.4x]=0x%4.4x\n", reg, regData); + #endif + +#endif + + return RT_ERR_OK; +} + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv.h new file mode 100644 index 00000000..c4e8d1a8 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv.h @@ -0,0 +1,111 @@ +#ifndef _RTL8367C_ASICDRV_H_ +#define _RTL8367C_ASICDRV_H_ + +#include +#include +#include +#include + +#define RTL8367C_REGBITLENGTH 16 +#define RTL8367C_REGDATAMAX 0xFFFF + +#define RTL8367C_VIDMAX 0xFFF +#define RTL8367C_EVIDMAX 0x1FFF +#define RTL8367C_CVIDXNO 32 +#define RTL8367C_CVIDXMAX (RTL8367C_CVIDXNO-1) + +#define RTL8367C_PRIMAX 7 +#define RTL8367C_DSCPMAX 63 + +#define RTL8367C_PORTNO 11 +#define RTL8367C_PORTIDMAX (RTL8367C_PORTNO-1) +#define RTL8367C_PMSKMAX ((1<<(RTL8367C_PORTNO))-1) +#define RTL8367C_PORTMASK 0x7FF + +#define RTL8367C_PHYNO 5 +#define RTL8367C_PHYIDMAX (RTL8367C_PHYNO-1) + +#define RTL8367C_SVIDXNO 64 +#define RTL8367C_SVIDXMAX (RTL8367C_SVIDXNO-1) +#define RTL8367C_MSTIMAX 15 + +#define RTL8367C_METERNO 64 +#define RTL8367C_METERMAX (RTL8367C_METERNO-1) +#define RTL8367C_METERBUCKETSIZEMAX 0xFFFF + +#define RTL8367C_QUEUENO 8 +#define RTL8367C_QIDMAX (RTL8367C_QUEUENO-1) + +#define RTL8367C_PHY_BUSY_CHECK_COUNTER 1000 + +#define RTL8367C_QOS_GRANULARTY_MAX 0x7FFFF +#define RTL8367C_QOS_GRANULARTY_LSB_MASK 0xFFFF +#define RTL8367C_QOS_GRANULARTY_LSB_OFFSET 0 +#define RTL8367C_QOS_GRANULARTY_MSB_MASK 0x70000 +#define RTL8367C_QOS_GRANULARTY_MSB_OFFSET 16 + +#define RTL8367C_QOS_GRANULARTY_UNIT_KBPS 8 + +#define RTL8367C_QOS_RATE_INPUT_MAX (0x1FFFF * 8) +#define RTL8367C_QOS_RATE_INPUT_MAX_HSG (0x7FFFF * 8) +#define RTL8367C_QOS_RATE_INPUT_MIN 8 +#define RTL8367C_QOS_PPS_INPUT_MAX (0x7FFFF) +#define RTL8367C_QOS_PPS_INPUT_MIN 1 + +#define RTL8367C_QUEUE_MASK 0xFF + +#define RTL8367C_EFIDMAX 0x7 +#define RTL8367C_FIDMAX 0xF + +#define RTL8367C_EAV_SECONDMAX 0xFFFFFFFF +#define RTL8367C_EAV_NANOSECONDMAX 0x3B9AC9FF + + +/* the above macro is generated by genDotH */ +#define RTL8367C_VALID_REG_NO 3869 + +/*======================================================================= + * Enum + *========================================================================*/ +enum RTL8367C_TABLE_ACCESS_OP +{ + TB_OP_READ = 0, + TB_OP_WRITE +}; + +enum RTL8367C_TABLE_ACCESS_TARGET +{ + TB_TARGET_ACLRULE = 1, + TB_TARGET_ACLACT, + TB_TARGET_CVLAN, + TB_TARGET_L2, + TB_TARGET_IGMP_GROUP +}; + +#define RTL8367C_TABLE_ACCESS_REG_DATA(op, target) ((op << 3) | target) + +/*======================================================================= + * Structures + *========================================================================*/ + + +#ifdef __cplusplus +extern "C" { +#endif +extern ret_t rtl8367c_setAsicRegBit(rtk_uint32 reg, rtk_uint32 bit, rtk_uint32 value); +extern ret_t rtl8367c_getAsicRegBit(rtk_uint32 reg, rtk_uint32 bit, rtk_uint32 *pValue); + +extern ret_t rtl8367c_setAsicRegBits(rtk_uint32 reg, rtk_uint32 bits, rtk_uint32 value); +extern ret_t rtl8367c_getAsicRegBits(rtk_uint32 reg, rtk_uint32 bits, rtk_uint32 *pValue); + +extern ret_t rtl8367c_setAsicReg(rtk_uint32 reg, rtk_uint32 value); +extern ret_t rtl8367c_getAsicReg(rtk_uint32 reg, rtk_uint32 *pValue); + +#ifdef __cplusplus +} +#endif + + + +#endif /*#ifndef _RTL8367C_ASICDRV_H_*/ + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_acl.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_acl.c new file mode 100644 index 00000000..ca7c3ef6 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_acl.c @@ -0,0 +1,1175 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTL8367C switch high-level API for RTL8367C + * Feature : ACL related function drivers + * + */ +#include + +#include + +#if defined(CONFIG_RTL8367C_ASICDRV_TEST) +rtl8367c_aclrulesmi Rtl8370sVirtualAclRuleTable[RTL8367C_ACLRULENO]; +rtk_uint16 Rtl8370sVirtualAclActTable[RTL8367C_ACLRULENO][RTL8367C_ACL_ACT_TABLE_LEN]; +#endif + +/* + Exchange structure type define with MMI and SMI +*/ +static void _rtl8367c_aclRuleStSmi2User( rtl8367c_aclrule *pAclUser, rtl8367c_aclrulesmi *pAclSmi) +{ + rtk_uint8 *care_ptr, *data_ptr; + rtk_uint8 care_tmp, data_tmp; + rtk_uint32 i; + + pAclUser->data_bits.active_portmsk = (((pAclSmi->data_bits_ext.rule_info >> 1) & 0x0007) << 8) | ((pAclSmi->data_bits.rule_info >> 8) & 0x00FF); + pAclUser->data_bits.type = (pAclSmi->data_bits.rule_info & 0x0007); + pAclUser->data_bits.tag_exist = (pAclSmi->data_bits.rule_info & 0x00F8) >> 3; + + care_ptr = (rtk_uint8*)&pAclSmi->care_bits; + data_ptr = (rtk_uint8*)&pAclSmi->data_bits; + + for ( i = 0; i < sizeof(struct acl_rule_smi_st); i++) + { + care_tmp = *(care_ptr + i) ^ (*(data_ptr + i)); + data_tmp = *(data_ptr + i); + + *(care_ptr + i) = care_tmp; + *(data_ptr + i) = data_tmp; + } + + care_ptr = (rtk_uint8*)&pAclSmi->care_bits_ext; + data_ptr = (rtk_uint8*)&pAclSmi->data_bits_ext; + care_tmp = (*care_ptr) ^ (*data_ptr); + data_tmp = (*data_ptr); + *care_ptr = care_tmp; + *data_ptr = data_tmp; + + for(i = 0; i < RTL8367C_ACLRULEFIELDNO; i++) + pAclUser->data_bits.field[i] = pAclSmi->data_bits.field[i]; + + pAclUser->valid = pAclSmi->valid; + + pAclUser->care_bits.active_portmsk = (((pAclSmi->care_bits_ext.rule_info >> 1) & 0x0007) << 8) | ((pAclSmi->care_bits.rule_info >> 8) & 0x00FF); + pAclUser->care_bits.type = (pAclSmi->care_bits.rule_info & 0x0007); + pAclUser->care_bits.tag_exist = (pAclSmi->care_bits.rule_info & 0x00F8) >> 3; + + for(i = 0; i < RTL8367C_ACLRULEFIELDNO; i++) + pAclUser->care_bits.field[i] = pAclSmi->care_bits.field[i]; +} + +/* + Exchange structure type define with MMI and SMI +*/ +static void _rtl8367c_aclRuleStUser2Smi(rtl8367c_aclrule *pAclUser, rtl8367c_aclrulesmi *pAclSmi) +{ + rtk_uint8 *care_ptr, *data_ptr; + rtk_uint8 care_tmp, data_tmp; + rtk_uint32 i; + + pAclSmi->data_bits_ext.rule_info = ((pAclUser->data_bits.active_portmsk >> 8) & 0x7) << 1; + pAclSmi->data_bits.rule_info = ((pAclUser->data_bits.active_portmsk & 0xff) << 8) | ((pAclUser->data_bits.tag_exist & 0x1F) << 3) | (pAclUser->data_bits.type & 0x07); + + for(i = 0;i < RTL8367C_ACLRULEFIELDNO; i++) + pAclSmi->data_bits.field[i] = pAclUser->data_bits.field[i]; + + pAclSmi->valid = pAclUser->valid; + + pAclSmi->care_bits_ext.rule_info = ((pAclUser->care_bits.active_portmsk >> 8) & 0x7) << 1; + pAclSmi->care_bits.rule_info = ((pAclUser->care_bits.active_portmsk & 0xff) << 8) | ((pAclUser->care_bits.tag_exist & 0x1F) << 3) | (pAclUser->care_bits.type & 0x07); + + for(i = 0; i < RTL8367C_ACLRULEFIELDNO; i++) + pAclSmi->care_bits.field[i] = pAclUser->care_bits.field[i]; + + care_ptr = (rtk_uint8*)&pAclSmi->care_bits; + data_ptr = (rtk_uint8*)&pAclSmi->data_bits; + + for ( i = 0; i < sizeof(struct acl_rule_smi_st); i++) + { + care_tmp = *(care_ptr + i) & ~(*(data_ptr + i)); + data_tmp = *(care_ptr + i) & *(data_ptr + i); + + *(care_ptr + i) = care_tmp; + *(data_ptr + i) = data_tmp; + } + + care_ptr = (rtk_uint8*)&pAclSmi->care_bits_ext; + data_ptr = (rtk_uint8*)&pAclSmi->data_bits_ext; + care_tmp = *care_ptr & ~(*data_ptr); + data_tmp = *care_ptr & *data_ptr; + + *care_ptr = care_tmp; + *data_ptr = data_tmp; +} + +/* + Exchange structure type define with MMI and SMI +*/ +static void _rtl8367c_aclActStSmi2User(rtl8367c_acl_act_t *pAclUser, rtk_uint16 *pAclSmi) +{ + pAclUser->cact = (pAclSmi[0] & 0x00C0) >> 6; + pAclUser->cvidx_cact = (pAclSmi[0] & 0x003F) | (((pAclSmi[3] & 0x0008) >> 3) << 6); + + pAclUser->sact = (pAclSmi[0] & 0xC000) >> 14; + pAclUser->svidx_sact = ((pAclSmi[0] & 0x3F00) >> 8) | (((pAclSmi[3] & 0x0010) >> 4) << 6); + + pAclUser->aclmeteridx = (pAclSmi[1] & 0x003F) | (((pAclSmi[3] & 0x0020) >> 5) << 6); + + pAclUser->fwdact = (pAclSmi[1] & 0xC000) >> 14; + pAclUser->fwdpmask = ((pAclSmi[1] & 0x3FC0) >> 6) | (((pAclSmi[3] & 0x01C0) >> 6) << 8); + + pAclUser->priact = (pAclSmi[2] & 0x00C0) >> 6; + pAclUser->pridx = (pAclSmi[2] & 0x003F) | (((pAclSmi[3] & 0x0200) >> 9) << 6); + + pAclUser->aclint = (pAclSmi[2] & 0x2000) >> 13; + pAclUser->gpio_en = (pAclSmi[2] & 0x1000) >> 12; + pAclUser->gpio_pin = (pAclSmi[2] & 0x0F00) >> 8; + + pAclUser->cact_ext = (pAclSmi[2] & 0xC000) >> 14; + pAclUser->tag_fmt = (pAclSmi[3] & 0x0003); + pAclUser->fwdact_ext = (pAclSmi[3] & 0x0004) >> 2; +} + +/* + Exchange structure type define with MMI and SMI +*/ +static void _rtl8367c_aclActStUser2Smi(rtl8367c_acl_act_t *pAclUser, rtk_uint16 *pAclSmi) +{ + pAclSmi[0] |= (pAclUser->cvidx_cact & 0x003F); + pAclSmi[0] |= (pAclUser->cact & 0x0003) << 6; + pAclSmi[0] |= (pAclUser->svidx_sact & 0x003F) << 8; + pAclSmi[0] |= (pAclUser->sact & 0x0003) << 14; + + pAclSmi[1] |= (pAclUser->aclmeteridx & 0x003F); + pAclSmi[1] |= (pAclUser->fwdpmask & 0x00FF) << 6; + pAclSmi[1] |= (pAclUser->fwdact & 0x0003) << 14; + + pAclSmi[2] |= (pAclUser->pridx & 0x003F); + pAclSmi[2] |= (pAclUser->priact & 0x0003) << 6; + pAclSmi[2] |= (pAclUser->gpio_pin & 0x000F) << 8; + pAclSmi[2] |= (pAclUser->gpio_en & 0x0001) << 12; + pAclSmi[2] |= (pAclUser->aclint & 0x0001) << 13; + pAclSmi[2] |= (pAclUser->cact_ext & 0x0003) << 14; + + pAclSmi[3] |= (pAclUser->tag_fmt & 0x0003); + pAclSmi[3] |= (pAclUser->fwdact_ext & 0x0001) << 2; + pAclSmi[3] |= ((pAclUser->cvidx_cact & 0x0040) >> 6) << 3; + pAclSmi[3] |= ((pAclUser->svidx_sact & 0x0040) >> 6) << 4; + pAclSmi[3] |= ((pAclUser->aclmeteridx & 0x0040) >> 6) << 5; + pAclSmi[3] |= ((pAclUser->fwdpmask & 0x0700) >> 8) << 6; + pAclSmi[3] |= ((pAclUser->pridx & 0x0040) >> 6) << 9; +} + +/* Function Name: + * rtl8367c_setAsicAcl + * Description: + * Set port acl function enable/disable + * Input: + * port - Physical port number (0~10) + * enabled - 1: enabled, 0: disabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_setAsicAcl(rtk_uint32 port, rtk_uint32 enabled) +{ + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + return rtl8367c_setAsicRegBit(RTL8367C_ACL_ENABLE_REG, port, enabled); +} +/* Function Name: + * rtl8367c_getAsicAcl + * Description: + * Get port acl function enable/disable + * Input: + * port - Physical port number (0~10) + * enabled - 1: enabled, 0: disabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_getAsicAcl(rtk_uint32 port, rtk_uint32* pEnabled) +{ + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + return rtl8367c_getAsicRegBit(RTL8367C_ACL_ENABLE_REG, port, pEnabled); +} +/* Function Name: + * rtl8367c_setAsicAclUnmatchedPermit + * Description: + * Set port acl function unmatched permit action + * Input: + * port - Physical port number (0~10) + * enabled - 1: enabled, 0: disabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_setAsicAclUnmatchedPermit(rtk_uint32 port, rtk_uint32 enabled) +{ + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + return rtl8367c_setAsicRegBit(RTL8367C_ACL_UNMATCH_PERMIT_REG, port, enabled); +} +/* Function Name: + * rtl8367c_getAsicAclUnmatchedPermit + * Description: + * Get port acl function unmatched permit action + * Input: + * port - Physical port number (0~10) + * enabled - 1: enabled, 0: disabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_getAsicAclUnmatchedPermit(rtk_uint32 port, rtk_uint32* pEnabled) +{ + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + return rtl8367c_getAsicRegBit(RTL8367C_ACL_UNMATCH_PERMIT_REG, port, pEnabled); +} + +/* Function Name: + * rtl8367c_setAsicAclRule + * Description: + * Set acl rule content + * Input: + * index - ACL rule index (0-95) of 96 ACL rules + * pAclRule - ACL rule stucture for setting + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - Invalid ACL rule index (0-95) + * Note: + * System supported 95 shared 289-bit ACL ingress rule. Index was available at range 0-95 only. + * If software want to modify ACL rule, the ACL function should be disable at first or unspecify + * acl action will be executed. + * One ACL rule structure has three parts setting: + * Bit 0-147 Data Bits of this Rule + * Bit 148 Valid Bit + * Bit 149-296 Care Bits of this Rule + * There are four kinds of field in Data Bits and Care Bits: Active Portmask, Type, Tag Exist, and 8 fields + */ +ret_t rtl8367c_setAsicAclRule(rtk_uint32 index, rtl8367c_aclrule* pAclRule) +{ + rtl8367c_aclrulesmi aclRuleSmi; + rtk_uint16* tableAddr; + rtk_uint32 regAddr; + rtk_uint32 regData; + rtk_uint32 i; + ret_t retVal; + + if(index > RTL8367C_ACLRULEMAX) + return RT_ERR_OUT_OF_RANGE; + + memset(&aclRuleSmi, 0x00, sizeof(rtl8367c_aclrulesmi)); + + _rtl8367c_aclRuleStUser2Smi(pAclRule, &aclRuleSmi); + + /* Write valid bit = 0 */ + regAddr = RTL8367C_TABLE_ACCESS_ADDR_REG; + if(index >= 64) + regData = RTL8367C_ACLRULETBADDR2(DATABITS, index); + else + regData = RTL8367C_ACLRULETBADDR(DATABITS, index); + retVal = rtl8367c_setAsicReg(regAddr,regData); + if(retVal !=RT_ERR_OK) + return retVal; + + retVal = rtl8367c_setAsicRegBits(RTL8367C_TABLE_ACCESS_WRDATA_REG(RTL8367C_ACLRULETBLEN), 0x1, 0); + if(retVal !=RT_ERR_OK) + return retVal; + + regAddr = RTL8367C_TABLE_ACCESS_CTRL_REG; + regData = RTL8367C_TABLE_ACCESS_REG_DATA(TB_OP_WRITE, TB_TARGET_ACLRULE); + retVal = rtl8367c_setAsicReg(regAddr, regData); + if(retVal !=RT_ERR_OK) + return retVal; + + + + /* Write ACS_ADR register */ + regAddr = RTL8367C_TABLE_ACCESS_ADDR_REG; + if(index >= 64) + regData = RTL8367C_ACLRULETBADDR2(CAREBITS, index); + else + regData = RTL8367C_ACLRULETBADDR(CAREBITS, index); + retVal = rtl8367c_setAsicReg(regAddr, regData); + if(retVal != RT_ERR_OK) + return retVal; + + /* Write Care Bits to ACS_DATA registers */ + tableAddr = (rtk_uint16*)&aclRuleSmi.care_bits; + regAddr = RTL8367C_TABLE_ACCESS_WRDATA_BASE; + + for(i = 0; i < RTL8367C_ACLRULETBLEN; i++) + { + regData = *tableAddr; + retVal = rtl8367c_setAsicReg(regAddr, regData); + if(retVal != RT_ERR_OK) + return retVal; + + regAddr++; + tableAddr++; + } + retVal = rtl8367c_setAsicRegBits(RTL8367C_TABLE_ACCESS_WRDATA_REG(RTL8367C_ACLRULETBLEN), (0x0007 << 1), (aclRuleSmi.care_bits_ext.rule_info >> 1) & 0x0007); + if(retVal != RT_ERR_OK) + return retVal; + + /* Write ACS_CMD register */ + regAddr = RTL8367C_TABLE_ACCESS_CTRL_REG; + regData = RTL8367C_TABLE_ACCESS_REG_DATA(TB_OP_WRITE, TB_TARGET_ACLRULE); + retVal = rtl8367c_setAsicRegBits(regAddr, RTL8367C_TABLE_TYPE_MASK | RTL8367C_COMMAND_TYPE_MASK,regData); + if(retVal != RT_ERR_OK) + return retVal; + + + + /* Write ACS_ADR register for data bits */ + regAddr = RTL8367C_TABLE_ACCESS_ADDR_REG; + if(index >= 64) + regData = RTL8367C_ACLRULETBADDR2(DATABITS, index); + else + regData = RTL8367C_ACLRULETBADDR(DATABITS, index); + + retVal = rtl8367c_setAsicReg(regAddr, regData); + if(retVal != RT_ERR_OK) + return retVal; + + /* Write Data Bits to ACS_DATA registers */ + tableAddr = (rtk_uint16*)&aclRuleSmi.data_bits; + regAddr = RTL8367C_TABLE_ACCESS_WRDATA_BASE; + + for(i = 0; i < RTL8367C_ACLRULETBLEN; i++) + { + regData = *tableAddr; + retVal = rtl8367c_setAsicReg(regAddr, regData); + if(retVal != RT_ERR_OK) + return retVal; + + regAddr++; + tableAddr++; + } + + retVal = rtl8367c_setAsicRegBit(RTL8367C_TABLE_ACCESS_WRDATA_REG(RTL8367C_ACLRULETBLEN), 0, aclRuleSmi.valid); + if(retVal != RT_ERR_OK) + return retVal; + retVal = rtl8367c_setAsicRegBits(RTL8367C_TABLE_ACCESS_WRDATA_REG(RTL8367C_ACLRULETBLEN), (0x0007 << 1), (aclRuleSmi.data_bits_ext.rule_info >> 1) & 0x0007); + if(retVal != RT_ERR_OK) + return retVal; + + /* Write ACS_CMD register for care bits*/ + regAddr = RTL8367C_TABLE_ACCESS_CTRL_REG; + regData = RTL8367C_TABLE_ACCESS_REG_DATA(TB_OP_WRITE, TB_TARGET_ACLRULE); + retVal = rtl8367c_setAsicRegBits(regAddr, RTL8367C_TABLE_TYPE_MASK | RTL8367C_COMMAND_TYPE_MASK, regData); + if(retVal != RT_ERR_OK) + return retVal; + +#ifdef CONFIG_RTL8367C_ASICDRV_TEST + memcpy(&Rtl8370sVirtualAclRuleTable[index], &aclRuleSmi, sizeof(rtl8367c_aclrulesmi)); +#endif + + return RT_ERR_OK; +} +/* Function Name: + * rtl8367c_getAsicAclRule + * Description: + * Get acl rule content + * Input: + * index - ACL rule index (0-63) of 64 ACL rules + * pAclRule - ACL rule stucture for setting + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - Invalid ACL rule index (0-63) + * Note: + * None + */ +ret_t rtl8367c_getAsicAclRule(rtk_uint32 index, rtl8367c_aclrule *pAclRule) +{ + rtl8367c_aclrulesmi aclRuleSmi; + rtk_uint32 regAddr, regData; + ret_t retVal; + rtk_uint16* tableAddr; + rtk_uint32 i; + + if(index > RTL8367C_ACLRULEMAX) + return RT_ERR_OUT_OF_RANGE; + + memset(&aclRuleSmi, 0x00, sizeof(rtl8367c_aclrulesmi)); + + /* Write ACS_ADR register for data bits */ + regAddr = RTL8367C_TABLE_ACCESS_ADDR_REG; + if(index >= 64) + regData = RTL8367C_ACLRULETBADDR2(DATABITS, index); + else + regData = RTL8367C_ACLRULETBADDR(DATABITS, index); + + retVal = rtl8367c_setAsicReg(regAddr, regData); + if(retVal != RT_ERR_OK) + return retVal; + + + /* Write ACS_CMD register */ + regAddr = RTL8367C_TABLE_ACCESS_CTRL_REG; + regData = RTL8367C_TABLE_ACCESS_REG_DATA(TB_OP_READ, TB_TARGET_ACLRULE); + retVal = rtl8367c_setAsicRegBits(regAddr, RTL8367C_TABLE_TYPE_MASK | RTL8367C_COMMAND_TYPE_MASK, regData); + if(retVal != RT_ERR_OK) + return retVal; + + /* Read Data Bits */ + regAddr = RTL8367C_TABLE_ACCESS_RDDATA_BASE; + tableAddr = (rtk_uint16*)&aclRuleSmi.data_bits; + for(i = 0; i < RTL8367C_ACLRULETBLEN; i++) + { + retVal = rtl8367c_getAsicReg(regAddr, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + *tableAddr = regData; + + regAddr ++; + tableAddr ++; + } + + /* Read Valid Bit */ + retVal = rtl8367c_getAsicRegBit(RTL8367C_TABLE_ACCESS_RDDATA_REG(RTL8367C_ACLRULETBLEN), 0, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + aclRuleSmi.valid = regData & 0x1; + /* Read active_portmsk_ext Bits */ + retVal = rtl8367c_getAsicRegBits(RTL8367C_TABLE_ACCESS_RDDATA_REG(RTL8367C_ACLRULETBLEN), 0x7<<1, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + aclRuleSmi.data_bits_ext.rule_info = (regData % 0x0007) << 1; + + + /* Write ACS_ADR register for carebits*/ + regAddr = RTL8367C_TABLE_ACCESS_ADDR_REG; + if(index >= 64) + regData = RTL8367C_ACLRULETBADDR2(CAREBITS, index); + else + regData = RTL8367C_ACLRULETBADDR(CAREBITS, index); + + retVal = rtl8367c_setAsicReg(regAddr, regData); + if(retVal != RT_ERR_OK) + return retVal; + + /* Write ACS_CMD register */ + regAddr = RTL8367C_TABLE_ACCESS_CTRL_REG; + regData = RTL8367C_TABLE_ACCESS_REG_DATA(TB_OP_READ, TB_TARGET_ACLRULE); + retVal = rtl8367c_setAsicRegBits(regAddr, RTL8367C_TABLE_TYPE_MASK | RTL8367C_COMMAND_TYPE_MASK, regData); + if(retVal != RT_ERR_OK) + return retVal; + + /* Read Care Bits */ + regAddr = RTL8367C_TABLE_ACCESS_RDDATA_BASE; + tableAddr = (rtk_uint16*)&aclRuleSmi.care_bits; + for(i = 0; i < RTL8367C_ACLRULETBLEN; i++) + { + retVal = rtl8367c_getAsicReg(regAddr, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + *tableAddr = regData; + + regAddr ++; + tableAddr ++; + } + /* Read active_portmsk_ext care Bits */ + retVal = rtl8367c_getAsicRegBits(RTL8367C_TABLE_ACCESS_RDDATA_REG(RTL8367C_ACLRULETBLEN), 0x7<<1, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + aclRuleSmi.care_bits_ext.rule_info = (regData & 0x0007) << 1; + +#ifdef CONFIG_RTL8367C_ASICDRV_TEST + memcpy(&aclRuleSmi,&Rtl8370sVirtualAclRuleTable[index], sizeof(rtl8367c_aclrulesmi)); +#endif + + _rtl8367c_aclRuleStSmi2User(pAclRule, &aclRuleSmi); + + return RT_ERR_OK; +} +/* Function Name: + * rtl8367c_setAsicAclNot + * Description: + * Set rule comparison result inversion / no inversion + * Input: + * index - ACL rule index (0-95) of 96 ACL rules + * not - 1: inverse, 0: don't inverse + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - Invalid ACL rule index (0-95) + * Note: + * None + */ +ret_t rtl8367c_setAsicAclNot(rtk_uint32 index, rtk_uint32 not) +{ + if(index > RTL8367C_ACLRULEMAX) + return RT_ERR_OUT_OF_RANGE; + + if(index < 64) + return rtl8367c_setAsicRegBit(RTL8367C_ACL_ACTION_CTRL_REG(index), RTL8367C_ACL_OP_NOT_OFFSET(index), not); + else + return rtl8367c_setAsicRegBit(RTL8367C_ACL_ACTION_CTRL2_REG(index), RTL8367C_ACL_OP_NOT_OFFSET(index), not); + +} +/* Function Name: + * rtl8367c_getAsicAcl + * Description: + * Get rule comparison result inversion / no inversion + * Input: + * index - ACL rule index (0-95) of 95 ACL rules + * pNot - 1: inverse, 0: don't inverse + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - Invalid ACL rule index (0-95) + * Note: + * None + */ +ret_t rtl8367c_getAsicAclNot(rtk_uint32 index, rtk_uint32* pNot) +{ + if(index > RTL8367C_ACLRULEMAX) + return RT_ERR_OUT_OF_RANGE; + + if(index < 64) + return rtl8367c_getAsicRegBit(RTL8367C_ACL_ACTION_CTRL_REG(index), RTL8367C_ACL_OP_NOT_OFFSET(index), pNot); + else + return rtl8367c_getAsicRegBit(RTL8367C_ACL_ACTION_CTRL2_REG(index), RTL8367C_ACL_OP_NOT_OFFSET(index), pNot); + +} +/* Function Name: + * rtl8367c_setAsicAclTemplate + * Description: + * Set fields of a ACL Template + * Input: + * index - ACL template index(0~4) + * pAclType - ACL type stucture for setting + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - Invalid ACL template index(0~4) + * Note: + * The API can set type field of the 5 ACL rule templates. + * Each type has 8 fields. One field means what data in one field of a ACL rule means + * 8 fields of ACL rule 0~95 is descripted by one type in ACL group + */ +ret_t rtl8367c_setAsicAclTemplate(rtk_uint32 index, rtl8367c_acltemplate_t* pAclType) +{ + ret_t retVal; + rtk_uint32 i; + rtk_uint32 regAddr, regData; + + if(index >= RTL8367C_ACLTEMPLATENO) + return RT_ERR_OUT_OF_RANGE; + + regAddr = RTL8367C_ACL_RULE_TEMPLATE_CTRL_REG(index); + + for(i = 0; i < (RTL8367C_ACLRULEFIELDNO/2); i++) + { + regData = pAclType->field[i*2+1]; + regData = regData << 8 | pAclType->field[i*2]; + + retVal = rtl8367c_setAsicReg(regAddr + i, regData); + + if(retVal != RT_ERR_OK) + return retVal; + } + + return retVal; +} +/* Function Name: + * rtl8367c_getAsicAclTemplate + * Description: + * Get fields of a ACL Template + * Input: + * index - ACL template index(0~4) + * pAclType - ACL type stucture for setting + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - Invalid ACL template index(0~4) + * Note: + * None + */ +ret_t rtl8367c_getAsicAclTemplate(rtk_uint32 index, rtl8367c_acltemplate_t *pAclType) +{ + ret_t retVal; + rtk_uint32 i; + rtk_uint32 regData, regAddr; + + if(index >= RTL8367C_ACLTEMPLATENO) + return RT_ERR_OUT_OF_RANGE; + + regAddr = RTL8367C_ACL_RULE_TEMPLATE_CTRL_REG(index); + + for(i = 0; i < (RTL8367C_ACLRULEFIELDNO/2); i++) + { + retVal = rtl8367c_getAsicReg(regAddr + i,®Data); + if(retVal != RT_ERR_OK) + return retVal; + + pAclType->field[i*2] = regData & 0xFF; + pAclType->field[i*2 + 1] = (regData >> 8) & 0xFF; + } + + return RT_ERR_OK; +} +/* Function Name: + * rtl8367c_setAsicAclAct + * Description: + * Set ACL rule matched Action + * Input: + * index - ACL rule index (0-95) of 96 ACL rules + * pAclAct - ACL action stucture for setting + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - Invalid ACL rule index (0-95) + * Note: + * None + */ +ret_t rtl8367c_setAsicAclAct(rtk_uint32 index, rtl8367c_acl_act_t* pAclAct) +{ + rtk_uint16 aclActSmi[RTL8367C_ACL_ACT_TABLE_LEN]; + ret_t retVal; + rtk_uint32 regAddr, regData; + rtk_uint16* tableAddr; + rtk_uint32 i; + + if(index > RTL8367C_ACLRULEMAX) + return RT_ERR_OUT_OF_RANGE; + + memset(aclActSmi, 0x00, sizeof(rtk_uint16) * RTL8367C_ACL_ACT_TABLE_LEN); + _rtl8367c_aclActStUser2Smi(pAclAct, aclActSmi); + + /* Write ACS_ADR register for data bits */ + regAddr = RTL8367C_TABLE_ACCESS_ADDR_REG; + regData = index; + retVal = rtl8367c_setAsicReg(regAddr, regData); + if(retVal != RT_ERR_OK) + return retVal; + + /* Write Data Bits to ACS_DATA registers */ + tableAddr = aclActSmi; + regAddr = RTL8367C_TABLE_ACCESS_WRDATA_BASE; + + for(i = 0; i < RTL8367C_ACLACTTBLEN; i++) + { + regData = *tableAddr; + retVal = rtl8367c_setAsicReg(regAddr, regData); + if(retVal != RT_ERR_OK) + return retVal; + + regAddr++; + tableAddr++; + } + + /* Write ACS_CMD register for care bits*/ + regAddr = RTL8367C_TABLE_ACCESS_CTRL_REG; + regData = RTL8367C_TABLE_ACCESS_REG_DATA(TB_OP_WRITE, TB_TARGET_ACLACT); + retVal = rtl8367c_setAsicRegBits(regAddr, RTL8367C_TABLE_TYPE_MASK | RTL8367C_COMMAND_TYPE_MASK, regData); + if(retVal != RT_ERR_OK) + return retVal; + +#ifdef CONFIG_RTL8367C_ASICDRV_TEST + memcpy(&Rtl8370sVirtualAclActTable[index][0], aclActSmi, sizeof(rtk_uint16) * RTL8367C_ACL_ACT_TABLE_LEN); +#endif + + return RT_ERR_OK; +} +/* Function Name: + * rtl8367c_getAsicAclAct + * Description: + * Get ACL rule matched Action + * Input: + * index - ACL rule index (0-95) of 96 ACL rules + * pAclAct - ACL action stucture for setting + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - Invalid ACL rule index (0-95) + * Note: + * None + */ +ret_t rtl8367c_getAsicAclAct(rtk_uint32 index, rtl8367c_acl_act_t *pAclAct) +{ + rtk_uint16 aclActSmi[RTL8367C_ACL_ACT_TABLE_LEN]; + ret_t retVal; + rtk_uint32 regAddr, regData; + rtk_uint16 *tableAddr; + rtk_uint32 i; + + if(index > RTL8367C_ACLRULEMAX) + return RT_ERR_OUT_OF_RANGE; + + memset(aclActSmi, 0x00, sizeof(rtk_uint16) * RTL8367C_ACL_ACT_TABLE_LEN); + + /* Write ACS_ADR register for data bits */ + regAddr = RTL8367C_TABLE_ACCESS_ADDR_REG; + regData = index; + retVal = rtl8367c_setAsicReg(regAddr, regData); + if(retVal != RT_ERR_OK) + return retVal; + + /* Write ACS_CMD register */ + regAddr = RTL8367C_TABLE_ACCESS_CTRL_REG; + regData = RTL8367C_TABLE_ACCESS_REG_DATA(TB_OP_READ, TB_TARGET_ACLACT); + retVal = rtl8367c_setAsicRegBits(regAddr, RTL8367C_TABLE_TYPE_MASK | RTL8367C_COMMAND_TYPE_MASK, regData); + if(retVal != RT_ERR_OK) + return retVal; + + /* Read Data Bits */ + regAddr = RTL8367C_TABLE_ACCESS_RDDATA_BASE; + tableAddr = aclActSmi; + for(i = 0; i < RTL8367C_ACLACTTBLEN; i++) + { + retVal = rtl8367c_getAsicReg(regAddr, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + *tableAddr = regData; + + regAddr ++; + tableAddr ++; + } + +#ifdef CONFIG_RTL8367C_ASICDRV_TEST + memcpy(aclActSmi, &Rtl8370sVirtualAclActTable[index][0], sizeof(rtk_uint16) * RTL8367C_ACL_ACT_TABLE_LEN); +#endif + + _rtl8367c_aclActStSmi2User(pAclAct, aclActSmi); + + return RT_ERR_OK; +} +/* Function Name: + * rtl8367c_setAsicAclActCtrl + * Description: + * Set ACL rule matched Action Control Bits + * Input: + * index - ACL rule index (0-95) of 96 ACL rules + * aclActCtrl - 6 ACL Control Bits + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - Invalid ACL rule index (0-95) + * Note: + * ACL Action Control Bits Indicate which actions will be take when a rule matches + */ +ret_t rtl8367c_setAsicAclActCtrl(rtk_uint32 index, rtk_uint32 aclActCtrl) +{ + ret_t retVal; + + if(index > RTL8367C_ACLRULEMAX) + return RT_ERR_OUT_OF_RANGE; + + if(index >= 64) + retVal = rtl8367c_setAsicRegBits(RTL8367C_ACL_ACTION_CTRL2_REG(index), RTL8367C_ACL_OP_ACTION_MASK(index), aclActCtrl); + else + retVal = rtl8367c_setAsicRegBits(RTL8367C_ACL_ACTION_CTRL_REG(index), RTL8367C_ACL_OP_ACTION_MASK(index), aclActCtrl); + + return retVal; +} +/* Function Name: + * rtl8367c_getAsicAclActCtrl + * Description: + * Get ACL rule matched Action Control Bits + * Input: + * index - ACL rule index (0-95) of 96 ACL rules + * pAclActCtrl - 6 ACL Control Bits + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - Invalid ACL rule index (0-95) + * Note: + * None + */ +ret_t rtl8367c_getAsicAclActCtrl(rtk_uint32 index, rtk_uint32 *pAclActCtrl) +{ + ret_t retVal; + rtk_uint32 regData; + + if(index > RTL8367C_ACLRULEMAX) + return RT_ERR_OUT_OF_RANGE; + + if(index >= 64) + retVal = rtl8367c_getAsicRegBits(RTL8367C_ACL_ACTION_CTRL2_REG(index), RTL8367C_ACL_OP_ACTION_MASK(index), ®Data); + else + retVal = rtl8367c_getAsicRegBits(RTL8367C_ACL_ACTION_CTRL_REG(index), RTL8367C_ACL_OP_ACTION_MASK(index), ®Data); + + if(retVal != RT_ERR_OK) + return retVal; + + *pAclActCtrl = regData; + + return RT_ERR_OK; +} +/* Function Name: + * rtl8367c_setAsicAclPortRange + * Description: + * Set ACL TCP/UDP range check + * Input: + * index - TCP/UDP port range check table index + * type - Range check type + * upperPort - TCP/UDP port range upper bound + * lowerPort - TCP/UDP port range lower bound + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - Invalid TCP/UDP port range check table index + * Note: + * None + */ +ret_t rtl8367c_setAsicAclPortRange(rtk_uint32 index, rtk_uint32 type, rtk_uint32 upperPort, rtk_uint32 lowerPort) +{ + ret_t retVal; + + if(index > RTL8367C_ACLRANGEMAX) + return RT_ERR_OUT_OF_RANGE; + + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY0_CTRL2 + index*3, RTL8367C_ACL_SDPORT_RANGE_ENTRY0_CTRL2_MASK, type); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8367c_setAsicReg(RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY0_CTRL1 + index*3, upperPort); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8367c_setAsicReg(RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY0_CTRL0 + index*3, lowerPort); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} +/* Function Name: + * rtl8367c_getAsicAclPortRange + * Description: + * Get ACL TCP/UDP range check + * Input: + * index - TCP/UDP port range check table index + * pType - Range check type + * pUpperPort - TCP/UDP port range upper bound + * pLowerPort - TCP/UDP port range lower bound + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - Invalid TCP/UDP port range check table index + * Note: + * None + */ +ret_t rtl8367c_getAsicAclPortRange(rtk_uint32 index, rtk_uint32* pType, rtk_uint32* pUpperPort, rtk_uint32* pLowerPort) +{ + ret_t retVal; + + if(index > RTL8367C_ACLRANGEMAX) + return RT_ERR_OUT_OF_RANGE; + + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY0_CTRL2 + index*3, RTL8367C_ACL_SDPORT_RANGE_ENTRY0_CTRL2_MASK, pType); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8367c_getAsicReg(RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY0_CTRL1 + index*3, pUpperPort); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8367c_getAsicReg(RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY0_CTRL0 + index*3, pLowerPort); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} +/* Function Name: + * rtl8367c_setAsicAclVidRange + * Description: + * Set ACL VID range check + * Input: + * index - ACL VID range check index(0~15) + * type - Range check type + * upperVid - VID range upper bound + * lowerVid - VID range lower bound + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - Invalid ACL VID range check index(0~15) + * Note: + * None + */ +ret_t rtl8367c_setAsicAclVidRange(rtk_uint32 index, rtk_uint32 type, rtk_uint32 upperVid, rtk_uint32 lowerVid) +{ + ret_t retVal; + rtk_uint32 regData; + + if(index > RTL8367C_ACLRANGEMAX) + return RT_ERR_OUT_OF_RANGE; + + regData = ((type << RTL8367C_ACL_VID_RANGE_ENTRY0_CTRL1_CHECK0_TYPE_OFFSET) & RTL8367C_ACL_VID_RANGE_ENTRY0_CTRL1_CHECK0_TYPE_MASK) | + (upperVid & RTL8367C_ACL_VID_RANGE_ENTRY0_CTRL1_CHECK0_HIGH_MASK); + + retVal = rtl8367c_setAsicReg(RTL8367C_REG_ACL_VID_RANGE_ENTRY0_CTRL1 + index*2, regData); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8367c_setAsicReg(RTL8367C_REG_ACL_VID_RANGE_ENTRY0_CTRL0 + index*2, lowerVid); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} +/* Function Name: + * rtl8367c_getAsicAclVidRange + * Description: + * Get ACL VID range check + * Input: + * index - ACL VID range check index(0~15) + * pType - Range check type + * pUpperVid - VID range upper bound + * pLowerVid - VID range lower bound + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - Invalid ACL VID range check index(0~15) + * Note: + * None + */ +ret_t rtl8367c_getAsicAclVidRange(rtk_uint32 index, rtk_uint32* pType, rtk_uint32* pUpperVid, rtk_uint32* pLowerVid) +{ + ret_t retVal; + rtk_uint32 regData; + + if(index > RTL8367C_ACLRANGEMAX) + return RT_ERR_OUT_OF_RANGE; + + retVal = rtl8367c_getAsicReg(RTL8367C_REG_ACL_VID_RANGE_ENTRY0_CTRL1 + index*2, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + *pType = (regData & RTL8367C_ACL_VID_RANGE_ENTRY0_CTRL1_CHECK0_TYPE_MASK) >> RTL8367C_ACL_VID_RANGE_ENTRY0_CTRL1_CHECK0_TYPE_OFFSET; + *pUpperVid = regData & RTL8367C_ACL_VID_RANGE_ENTRY0_CTRL1_CHECK0_HIGH_MASK; + + retVal = rtl8367c_getAsicReg(RTL8367C_REG_ACL_VID_RANGE_ENTRY0_CTRL0 + index*2, pLowerVid); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} +/* Function Name: + * rtl8367c_setAsicAclIpRange + * Description: + * Set ACL IP range check + * Input: + * index - ACL IP range check index(0~15) + * type - Range check type + * upperIp - IP range upper bound + * lowerIp - IP range lower bound + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - Invalid ACL IP range check index(0~15) + * Note: + * None + */ +ret_t rtl8367c_setAsicAclIpRange(rtk_uint32 index, rtk_uint32 type, ipaddr_t upperIp, ipaddr_t lowerIp) +{ + ret_t retVal; + rtk_uint32 regData; + ipaddr_t ipData; + + if(index > RTL8367C_ACLRANGEMAX) + return RT_ERR_OUT_OF_RANGE; + + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_ACL_IP_RANGE_ENTRY0_CTRL4 + index*5, RTL8367C_ACL_IP_RANGE_ENTRY0_CTRL4_MASK, type); + if(retVal != RT_ERR_OK) + return retVal; + + ipData = upperIp; + + regData = ipData & 0xFFFF; + retVal = rtl8367c_setAsicReg(RTL8367C_REG_ACL_IP_RANGE_ENTRY0_CTRL2 + index*5, regData); + if(retVal != RT_ERR_OK) + return retVal; + + regData = (ipData>>16) & 0xFFFF; + retVal = rtl8367c_setAsicReg(RTL8367C_REG_ACL_IP_RANGE_ENTRY0_CTRL3 + index*5, regData); + if(retVal != RT_ERR_OK) + return retVal; + + ipData = lowerIp; + + regData = ipData & 0xFFFF; + retVal = rtl8367c_setAsicReg(RTL8367C_REG_ACL_IP_RANGE_ENTRY0_CTRL0 + index*5, regData); + if(retVal != RT_ERR_OK) + return retVal; + + regData = (ipData>>16) & 0xFFFF; + retVal = rtl8367c_setAsicReg(RTL8367C_REG_ACL_IP_RANGE_ENTRY0_CTRL1 + index*5, regData); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} +/* Function Name: + * rtl8367c_getAsicAclIpRange + * Description: + * Get ACL IP range check + * Input: + * index - ACL IP range check index(0~15) + * pType - Range check type + * pUpperIp - IP range upper bound + * pLowerIp - IP range lower bound + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - Invalid ACL IP range check index(0~15) + * Note: + * None + */ +ret_t rtl8367c_getAsicAclIpRange(rtk_uint32 index, rtk_uint32* pType, ipaddr_t* pUpperIp, ipaddr_t* pLowerIp) +{ + ret_t retVal; + rtk_uint32 regData; + ipaddr_t ipData; + + if(index > RTL8367C_ACLRANGEMAX) + return RT_ERR_OUT_OF_RANGE; + + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_ACL_IP_RANGE_ENTRY0_CTRL4 + index*5, RTL8367C_ACL_IP_RANGE_ENTRY0_CTRL4_MASK, pType); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8367c_getAsicReg(RTL8367C_REG_ACL_IP_RANGE_ENTRY0_CTRL2 + index*5, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + ipData = regData; + + + retVal = rtl8367c_getAsicReg(RTL8367C_REG_ACL_IP_RANGE_ENTRY0_CTRL3 + index*5, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + ipData = (regData <<16) | ipData; + *pUpperIp = ipData; + + + retVal = rtl8367c_getAsicReg(RTL8367C_REG_ACL_IP_RANGE_ENTRY0_CTRL0 + index*5, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + ipData = regData; + + + retVal = rtl8367c_getAsicReg(RTL8367C_REG_ACL_IP_RANGE_ENTRY0_CTRL1 + index*5, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + ipData = (regData << 16) | ipData; + *pLowerIp = ipData; + + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_setAsicAclGpioPolarity + * Description: + * Set ACL Goip control palarity + * Input: + * polarity - 1: High, 0: Low + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * none + */ +ret_t rtl8367c_setAsicAclGpioPolarity(rtk_uint32 polarity) +{ + return rtl8367c_setAsicRegBit(RTL8367C_REG_ACL_GPIO_POLARITY, RTL8367C_ACL_GPIO_POLARITY_OFFSET, polarity); +} +/* Function Name: + * rtl8367c_getAsicAclGpioPolarity + * Description: + * Get ACL Goip control palarity + * Input: + * pPolarity - 1: High, 0: Low + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * none + */ +ret_t rtl8367c_getAsicAclGpioPolarity(rtk_uint32* pPolarity) +{ + return rtl8367c_getAsicRegBit(RTL8367C_REG_ACL_GPIO_POLARITY, RTL8367C_ACL_GPIO_POLARITY_OFFSET, pPolarity); +} + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_acl.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_acl.h new file mode 100644 index 00000000..6a1c4145 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_acl.h @@ -0,0 +1,214 @@ +#ifndef _RTL8367C_ASICDRV_ACL_H_ +#define _RTL8367C_ASICDRV_ACL_H_ + +#include + +#define RTL8367C_ACLRULENO 96 + +#define RTL8367C_ACLRULEMAX (RTL8367C_ACLRULENO-1) +#define RTL8367C_ACLRULEFIELDNO 8 +#define RTL8367C_ACLTEMPLATENO 5 +#define RTL8367C_ACLTYPEMAX (RTL8367C_ACLTEMPLATENO-1) + +#define RTL8367C_ACLRULETBLEN 9 +#define RTL8367C_ACLACTTBLEN 4 +#define RTL8367C_ACLRULETBADDR(type, rule) ((type << 6) | rule) +#define RTL8367C_ACLRULETBADDR2(type, rule) ((type << 5) | (rule + 64)) + +#define ACL_ACT_CVLAN_ENABLE_MASK 0x1 +#define ACL_ACT_SVLAN_ENABLE_MASK 0x2 +#define ACL_ACT_PRIORITY_ENABLE_MASK 0x4 +#define ACL_ACT_POLICING_ENABLE_MASK 0x8 +#define ACL_ACT_FWD_ENABLE_MASK 0x10 +#define ACL_ACT_INTGPIO_ENABLE_MASK 0x20 + +#define RTL8367C_ACLRULETAGBITS 5 + +#define RTL8367C_ACLRANGENO 16 + +#define RTL8367C_ACLRANGEMAX (RTL8367C_ACLRANGENO-1) + +#define RTL8367C_ACL_PORTRANGEMAX (0xFFFF) +#define RTL8367C_ACL_ACT_TABLE_LEN (4) + +enum ACLTCAMTYPES +{ + CAREBITS= 0, + DATABITS +}; + +typedef enum aclFwdAct +{ + RTL8367C_ACL_FWD_MIRROR = 0, + RTL8367C_ACL_FWD_REDIRECT, + RTL8367C_ACL_FWD_MIRRORFUNTION, + RTL8367C_ACL_FWD_TRAP, +} rtl8367c_aclFwd_t; + +enum ACLFIELDTYPES +{ + ACL_UNUSED, + ACL_DMAC0, + ACL_DMAC1, + ACL_DMAC2, + ACL_SMAC0, + ACL_SMAC1, + ACL_SMAC2, + ACL_ETHERTYPE, + ACL_STAG, + ACL_CTAG, + ACL_IP4SIP0 = 0x10, + ACL_IP4SIP1, + ACL_IP4DIP0, + ACL_IP4DIP1, + ACL_IP6SIP0WITHIPV4 = 0x20, + ACL_IP6SIP1WITHIPV4, + ACL_IP6DIP0WITHIPV4 = 0x28, + ACL_IP6DIP1WITHIPV4, + ACL_VIDRANGE = 0x30, + ACL_IPRANGE, + ACL_PORTRANGE, + ACL_FIELD_VALID, + ACL_FIELD_SELECT00 = 0x40, + ACL_FIELD_SELECT01, + ACL_FIELD_SELECT02, + ACL_FIELD_SELECT03, + ACL_FIELD_SELECT04, + ACL_FIELD_SELECT05, + ACL_FIELD_SELECT06, + ACL_FIELD_SELECT07, + ACL_FIELD_SELECT08, + ACL_FIELD_SELECT09, + ACL_FIELD_SELECT10, + ACL_FIELD_SELECT11, + ACL_FIELD_SELECT12, + ACL_FIELD_SELECT13, + ACL_FIELD_SELECT14, + ACL_FIELD_SELECT15, + ACL_TCPSPORT = 0x80, + ACL_TCPDPORT, + ACL_TCPFLAG, + ACL_UDPSPORT, + ACL_UDPDPORT, + ACL_ICMPCODETYPE, + ACL_IGMPTYPE, + ACL_SPORT, + ACL_DPORT, + ACL_IP4TOSPROTO, + ACL_IP4FLAGOFF, + ACL_TCNH, + ACL_CPUTAG, + ACL_L2PAYLOAD, + ACL_IP6SIP0, + ACL_IP6SIP1, + ACL_IP6SIP2, + ACL_IP6SIP3, + ACL_IP6SIP4, + ACL_IP6SIP5, + ACL_IP6SIP6, + ACL_IP6SIP7, + ACL_IP6DIP0, + ACL_IP6DIP1, + ACL_IP6DIP2, + ACL_IP6DIP3, + ACL_IP6DIP4, + ACL_IP6DIP5, + ACL_IP6DIP6, + ACL_IP6DIP7, + ACL_TYPE_END +}; + +struct acl_rule_smi_st{ + rtk_uint16 rule_info; + rtk_uint16 field[RTL8367C_ACLRULEFIELDNO]; +}; + +struct acl_rule_smi_ext_st{ + rtk_uint16 rule_info; +}; + +typedef struct ACLRULESMI{ + struct acl_rule_smi_st care_bits; + rtk_uint16 valid:1; + struct acl_rule_smi_st data_bits; + + struct acl_rule_smi_ext_st care_bits_ext; + struct acl_rule_smi_ext_st data_bits_ext; +}rtl8367c_aclrulesmi; + +struct acl_rule_st{ + rtk_uint16 active_portmsk:11; + rtk_uint16 type:3; + rtk_uint16 tag_exist:5; + rtk_uint16 field[RTL8367C_ACLRULEFIELDNO]; +}; + +typedef struct ACLRULE{ + struct acl_rule_st data_bits; + rtk_uint16 valid:1; + struct acl_rule_st care_bits; +}rtl8367c_aclrule; + + +typedef struct rtl8367c_acltemplate_s{ + rtk_uint8 field[8]; +}rtl8367c_acltemplate_t; + + +typedef struct acl_act_s{ + rtk_uint16 cvidx_cact:7; + rtk_uint16 cact:2; + rtk_uint16 svidx_sact:7; + rtk_uint16 sact:2; + + + rtk_uint16 aclmeteridx:7; + rtk_uint16 fwdpmask:11; + rtk_uint16 fwdact:2; + + rtk_uint16 pridx:7; + rtk_uint16 priact:2; + rtk_uint16 gpio_pin:4; + rtk_uint16 gpio_en:1; + rtk_uint16 aclint:1; + + rtk_uint16 cact_ext:2; + rtk_uint16 fwdact_ext:1; + rtk_uint16 tag_fmt:2; +}rtl8367c_acl_act_t; + +typedef struct acl_rule_union_s +{ + rtl8367c_aclrule aclRule; + rtl8367c_acl_act_t aclAct; + rtk_uint32 aclActCtrl; + rtk_uint32 aclNot; +}rtl8367c_acl_rule_union_t; + + +extern ret_t rtl8367c_setAsicAcl(rtk_uint32 port, rtk_uint32 enabled); +extern ret_t rtl8367c_getAsicAcl(rtk_uint32 port, rtk_uint32* pEnabled); +extern ret_t rtl8367c_setAsicAclUnmatchedPermit(rtk_uint32 port, rtk_uint32 enabled); +extern ret_t rtl8367c_getAsicAclUnmatchedPermit(rtk_uint32 port, rtk_uint32* pEnabled); +extern ret_t rtl8367c_setAsicAclRule(rtk_uint32 index, rtl8367c_aclrule *pAclRule); +extern ret_t rtl8367c_getAsicAclRule(rtk_uint32 index, rtl8367c_aclrule *pAclRule); +extern ret_t rtl8367c_setAsicAclNot(rtk_uint32 index, rtk_uint32 not); +extern ret_t rtl8367c_getAsicAclNot(rtk_uint32 index, rtk_uint32* pNot); +extern ret_t rtl8367c_setAsicAclTemplate(rtk_uint32 index, rtl8367c_acltemplate_t* pAclType); +extern ret_t rtl8367c_getAsicAclTemplate(rtk_uint32 index, rtl8367c_acltemplate_t *pAclType); +extern ret_t rtl8367c_setAsicAclAct(rtk_uint32 index, rtl8367c_acl_act_t* pAclAct); +extern ret_t rtl8367c_getAsicAclAct(rtk_uint32 index, rtl8367c_acl_act_t *pAclAct); +extern ret_t rtl8367c_setAsicAclActCtrl(rtk_uint32 index, rtk_uint32 aclActCtrl); +extern ret_t rtl8367c_getAsicAclActCtrl(rtk_uint32 index, rtk_uint32 *aclActCtrl); +extern ret_t rtl8367c_setAsicAclPortRange(rtk_uint32 index, rtk_uint32 type, rtk_uint32 upperPort, rtk_uint32 lowerPort); +extern ret_t rtl8367c_getAsicAclPortRange(rtk_uint32 index, rtk_uint32* pType, rtk_uint32* pUpperPort, rtk_uint32* pLowerPort); +extern ret_t rtl8367c_setAsicAclVidRange(rtk_uint32 index, rtk_uint32 type, rtk_uint32 upperVid, rtk_uint32 lowerVid); +extern ret_t rtl8367c_getAsicAclVidRange(rtk_uint32 index, rtk_uint32* pType, rtk_uint32* pUpperVid, rtk_uint32* pLowerVid); +extern ret_t rtl8367c_setAsicAclIpRange(rtk_uint32 index, rtk_uint32 type, ipaddr_t upperIp, ipaddr_t lowerIp); +extern ret_t rtl8367c_getAsicAclIpRange(rtk_uint32 index, rtk_uint32* pType, ipaddr_t* pUpperIp, ipaddr_t* pLowerIp); +extern ret_t rtl8367c_setAsicAclGpioPolarity(rtk_uint32 polarity); +extern ret_t rtl8367c_getAsicAclGpioPolarity(rtk_uint32* pPolarity); + +#endif /*_RTL8367C_ASICDRV_ACL_H_*/ + + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_cputag.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_cputag.c new file mode 100644 index 00000000..f16e197c --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_cputag.c @@ -0,0 +1,371 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTL8367C switch high-level API for RTL8367C + * Feature : Proprietary CPU-tag related function drivers + * + */ +#include +/* Function Name: + * rtl8367c_setAsicCputagEnable + * Description: + * Set cpu tag function enable/disable + * Input: + * enabled - 1: enabled, 0: disabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid enable/disable input + * Note: + * If CPU tag function is disabled, CPU tag will not be added to frame + * forwarded to CPU port, and all ports cannot parse CPU tag. + */ +ret_t rtl8367c_setAsicCputagEnable(rtk_uint32 enabled) +{ + if(enabled > 1) + return RT_ERR_ENABLE; + + return rtl8367c_setAsicRegBit(RTL8367C_REG_CPU_CTRL, RTL8367C_CPU_EN_OFFSET, enabled); +} +/* Function Name: + * rtl8367c_getAsicCputagEnable + * Description: + * Get cpu tag function enable/disable + * Input: + * pEnabled - 1: enabled, 0: disabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicCputagEnable(rtk_uint32 *pEnabled) +{ + return rtl8367c_getAsicRegBit(RTL8367C_REG_CPU_CTRL, RTL8367C_CPU_EN_OFFSET, pEnabled); +} +/* Function Name: + * rtl8367c_setAsicCputagTrapPort + * Description: + * Set cpu tag trap port + * Input: + * port - port number + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * API can set destination port of trapping frame + */ +ret_t rtl8367c_setAsicCputagTrapPort(rtk_uint32 port) +{ + ret_t retVal; + + if(port >= RTL8367C_PORTNO) + return RT_ERR_PORT_ID; + + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_CPU_CTRL, RTL8367C_CPU_TRAP_PORT_MASK, port & 7); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_CPU_CTRL, RTL8367C_CPU_TRAP_PORT_EXT_MASK, (port>>3) & 1); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} +/* Function Name: + * rtl8367c_getAsicCputagTrapPort + * Description: + * Get cpu tag trap port + * Input: + * pPort - port number + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicCputagTrapPort(rtk_uint32 *pPort) +{ + ret_t retVal; + rtk_uint32 tmpPort; + + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_CPU_CTRL, RTL8367C_CPU_TRAP_PORT_MASK, &tmpPort); + if(retVal != RT_ERR_OK) + return retVal; + *pPort = tmpPort; + + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_CPU_CTRL, RTL8367C_CPU_TRAP_PORT_EXT_MASK, &tmpPort); + if(retVal != RT_ERR_OK) + return retVal; + *pPort |= (tmpPort & 1) << 3; + + return RT_ERR_OK; +} +/* Function Name: + * rtl8367c_setAsicCputagPortmask + * Description: + * Set ports that can parse CPU tag + * Input: + * portmask - port mask + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Invalid portmask + * Note: + * None + */ +ret_t rtl8367c_setAsicCputagPortmask(rtk_uint32 portmask) +{ + if(portmask > RTL8367C_PORTMASK) + return RT_ERR_PORT_MASK; + + return rtl8367c_setAsicReg(RTL8367C_CPU_PORT_MASK_REG, portmask); +} +/* Function Name: + * rtl8367c_getAsicCputagPortmask + * Description: + * Get ports that can parse CPU tag + * Input: + * pPortmask - port mask + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicCputagPortmask(rtk_uint32 *pPortmask) +{ + return rtl8367c_getAsicReg(RTL8367C_CPU_PORT_MASK_REG, pPortmask); +} +/* Function Name: + * rtl8367c_setAsicCputagInsertMode + * Description: + * Set CPU-tag insert mode + * Input: + * mode - 0: insert to all packets; 1: insert to trapped packets; 2: don't insert + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Actions not allowed by the function + * Note: + * None + */ +ret_t rtl8367c_setAsicCputagInsertMode(rtk_uint32 mode) +{ + if(mode >= CPUTAG_INSERT_END) + return RT_ERR_NOT_ALLOWED; + + return rtl8367c_setAsicRegBits(RTL8367C_REG_CPU_CTRL, RTL8367C_CPU_INSERTMODE_MASK, mode); +} +/* Function Name: + * rtl8367c_getAsicCputagInsertMode + * Description: + * Get CPU-tag insert mode + * Input: + * pMode - 0: insert to all packets; 1: insert to trapped packets; 2: don't insert + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicCputagInsertMode(rtk_uint32 *pMode) +{ + return rtl8367c_getAsicRegBits(RTL8367C_REG_CPU_CTRL, RTL8367C_CPU_INSERTMODE_MASK, pMode); +} +/* Function Name: + * rtl8367c_setAsicCputagPriorityRemapping + * Description: + * Set queue assignment of CPU port + * Input: + * srcPri - internal priority (0~7) + * newPri - internal priority after remapping (0~7) + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_INT_PRIORITY - Invalid priority + * Note: + * None + */ +ret_t rtl8367c_setAsicCputagPriorityRemapping(rtk_uint32 srcPri, rtk_uint32 newPri) +{ + if((srcPri > RTL8367C_PRIMAX) || (newPri > RTL8367C_PRIMAX)) + return RT_ERR_QOS_INT_PRIORITY; + + return rtl8367c_setAsicRegBits(RTL8367C_QOS_PRIPORITY_REMAPPING_IN_CPU_REG(srcPri), RTL8367C_QOS_PRIPORITY_REMAPPING_IN_CPU_MASK(srcPri), newPri); +} +/* Function Name: + * rtl8367c_getAsicCputagPriorityRemapping + * Description: + * Get queue assignment of CPU port + * Input: + * srcPri - internal priority (0~7) + * pNewPri - internal priority after remapping (0~7) + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_INT_PRIORITY - Invalid priority + * Note: + * None + */ +ret_t rtl8367c_getAsicCputagPriorityRemapping(rtk_uint32 srcPri, rtk_uint32 *pNewPri) +{ + if(srcPri > RTL8367C_PRIMAX) + return RT_ERR_QOS_INT_PRIORITY; + + return rtl8367c_getAsicRegBits(RTL8367C_QOS_PRIPORITY_REMAPPING_IN_CPU_REG(srcPri), RTL8367C_QOS_PRIPORITY_REMAPPING_IN_CPU_MASK(srcPri), pNewPri); +} +/* Function Name: + * rtl8367c_setAsicCputagPosition + * Description: + * Set cpu tag insert position + * Input: + * postion - 1: After entire packet(before CRC field), 0: After MAC_SA (Default) + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicCputagPosition(rtk_uint32 postion) +{ + return rtl8367c_setAsicRegBit(RTL8367C_REG_CPU_CTRL, RTL8367C_CPU_TAG_POSITION_OFFSET, postion); +} +/* Function Name: + * rtl8367c_getAsicCputagPosition + * Description: + * Get cpu tag insert position + * Input: + * pPostion - 1: After entire packet(before CRC field), 0: After MAC_SA (Default) + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicCputagPosition(rtk_uint32* pPostion) +{ + return rtl8367c_getAsicRegBit(RTL8367C_REG_CPU_CTRL, RTL8367C_CPU_TAG_POSITION_OFFSET, pPostion); +} + +/* Function Name: + * rtl8367c_setAsicCputagMode + * Description: + * Set cpu tag mode + * Input: + * mode - 1: 4bytes mode, 0: 8bytes mode + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters + * Note: + * If CPU tag function is disabled, CPU tag will not be added to frame + * forwarded to CPU port, and all ports cannot parse CPU tag. + */ +ret_t rtl8367c_setAsicCputagMode(rtk_uint32 mode) +{ + if(mode > 1) + return RT_ERR_INPUT; + + return rtl8367c_setAsicRegBit(RTL8367C_REG_CPU_CTRL, RTL8367C_CPU_TAG_FORMAT_OFFSET, mode); +} +/* Function Name: + * rtl8367c_getAsicCputagMode + * Description: + * Get cpu tag mode + * Input: + * pMode - 1: 4bytes mode, 0: 8bytes mode + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicCputagMode(rtk_uint32 *pMode) +{ + return rtl8367c_getAsicRegBit(RTL8367C_REG_CPU_CTRL, RTL8367C_CPU_TAG_FORMAT_OFFSET, pMode); +} +/* Function Name: + * rtl8367c_setAsicCputagRxMinLength + * Description: + * Set cpu tag mode + * Input: + * mode - 1: 64bytes, 0: 72bytes + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters + * Note: + * If CPU tag function is disabled, CPU tag will not be added to frame + * forwarded to CPU port, and all ports cannot parse CPU tag. + */ +ret_t rtl8367c_setAsicCputagRxMinLength(rtk_uint32 mode) +{ + if(mode > 1) + return RT_ERR_INPUT; + + return rtl8367c_setAsicRegBit(RTL8367C_REG_CPU_CTRL, RTL8367C_CPU_TAG_RXBYTECOUNT_OFFSET, mode); +} +/* Function Name: + * rtl8367c_getAsicCputagRxMinLength + * Description: + * Get cpu tag mode + * Input: + * pMode - 1: 64bytes, 0: 72bytes + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicCputagRxMinLength(rtk_uint32 *pMode) +{ + return rtl8367c_getAsicRegBit(RTL8367C_REG_CPU_CTRL, RTL8367C_CPU_TAG_RXBYTECOUNT_OFFSET, pMode); +} + + + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_cputag.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_cputag.h new file mode 100644 index 00000000..7e526a61 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_cputag.h @@ -0,0 +1,32 @@ +#ifndef _RTL8367C_ASICDRV_CPUTAG_H_ +#define _RTL8367C_ASICDRV_CPUTAG_H_ + +#include + +enum CPUTAG_INSERT_MODE +{ + CPUTAG_INSERT_TO_ALL = 0, + CPUTAG_INSERT_TO_TRAPPING, + CPUTAG_INSERT_TO_NO, + CPUTAG_INSERT_END +}; + +extern ret_t rtl8367c_setAsicCputagEnable(rtk_uint32 enabled); +extern ret_t rtl8367c_getAsicCputagEnable(rtk_uint32 *pEnabled); +extern ret_t rtl8367c_setAsicCputagTrapPort(rtk_uint32 port); +extern ret_t rtl8367c_getAsicCputagTrapPort(rtk_uint32 *pPort); +extern ret_t rtl8367c_setAsicCputagPortmask(rtk_uint32 portmask); +extern ret_t rtl8367c_getAsicCputagPortmask(rtk_uint32 *pPmsk); +extern ret_t rtl8367c_setAsicCputagInsertMode(rtk_uint32 mode); +extern ret_t rtl8367c_getAsicCputagInsertMode(rtk_uint32 *pMode); +extern ret_t rtl8367c_setAsicCputagPriorityRemapping(rtk_uint32 srcPri, rtk_uint32 newPri); +extern ret_t rtl8367c_getAsicCputagPriorityRemapping(rtk_uint32 srcPri, rtk_uint32 *pNewPri); +extern ret_t rtl8367c_setAsicCputagPosition(rtk_uint32 postion); +extern ret_t rtl8367c_getAsicCputagPosition(rtk_uint32* pPostion); +extern ret_t rtl8367c_setAsicCputagMode(rtk_uint32 mode); +extern ret_t rtl8367c_getAsicCputagMode(rtk_uint32 *pMode); +extern ret_t rtl8367c_setAsicCputagRxMinLength(rtk_uint32 mode); +extern ret_t rtl8367c_getAsicCputagRxMinLength(rtk_uint32 *pMode); + +#endif /*#ifndef _RTL8367C_ASICDRV_CPUTAG_H_*/ + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_dot1x.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_dot1x.c new file mode 100644 index 00000000..ad684fe7 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_dot1x.c @@ -0,0 +1,417 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTL8367C switch high-level API for RTL8367C + * Feature : 802.1X related functions + * + */ +#include +/* Function Name: + * rtl8367c_setAsic1xPBEnConfig + * Description: + * Set 802.1x port-based port enable configuration + * Input: + * port - Physical port number (0~7) + * enabled - 1: enabled, 0: disabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_setAsic1xPBEnConfig(rtk_uint32 port, rtk_uint32 enabled) +{ + if(port >= RTL8367C_PORTNO) + return RT_ERR_PORT_ID; + + return rtl8367c_setAsicRegBit(RTL8367C_DOT1X_PORT_ENABLE_REG, port, enabled); +} +/* Function Name: + * rtl8367c_getAsic1xPBEnConfig + * Description: + * Get 802.1x port-based port enable configuration + * Input: + * port - Physical port number (0~7) + * pEnabled - 1: enabled, 0: disabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_getAsic1xPBEnConfig(rtk_uint32 port, rtk_uint32 *pEnabled) +{ + if(port >= RTL8367C_PORTNO) + return RT_ERR_PORT_ID; + + return rtl8367c_getAsicRegBit(RTL8367C_DOT1X_PORT_ENABLE_REG, port, pEnabled); +} +/* Function Name: + * rtl8367c_setAsic1xPBAuthConfig + * Description: + * Set 802.1x port-based authorised port configuration + * Input: + * port - Physical port number (0~7) + * auth - 1: authorised, 0: non-authorised + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_setAsic1xPBAuthConfig(rtk_uint32 port, rtk_uint32 auth) +{ + if(port >= RTL8367C_PORTNO) + return RT_ERR_PORT_ID; + + return rtl8367c_setAsicRegBit(RTL8367C_DOT1X_PORT_AUTH_REG, port, auth); +} +/* Function Name: + * rtl8367c_getAsic1xPBAuthConfig + * Description: + * Get 802.1x port-based authorised port configuration + * Input: + * port - Physical port number (0~7) + * pAuth - 1: authorised, 0: non-authorised + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_getAsic1xPBAuthConfig(rtk_uint32 port, rtk_uint32 *pAuth) +{ + if(port >= RTL8367C_PORTNO) + return RT_ERR_PORT_ID; + + return rtl8367c_getAsicRegBit(RTL8367C_DOT1X_PORT_AUTH_REG, port, pAuth); +} +/* Function Name: + * rtl8367c_setAsic1xPBOpdirConfig + * Description: + * Set 802.1x port-based operational direction + * Input: + * port - Physical port number (0~7) + * opdir - Operation direction 1: IN, 0:BOTH + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_setAsic1xPBOpdirConfig(rtk_uint32 port, rtk_uint32 opdir) +{ + if(port >= RTL8367C_PORTNO) + return RT_ERR_PORT_ID; + + return rtl8367c_setAsicRegBit(RTL8367C_DOT1X_PORT_OPDIR_REG, port, opdir); +} +/* Function Name: + * rtl8367c_getAsic1xPBOpdirConfig + * Description: + * Get 802.1x port-based operational direction + * Input: + * port - Physical port number (0~7) + * pOpdir - Operation direction 1: IN, 0:BOTH + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_getAsic1xPBOpdirConfig(rtk_uint32 port, rtk_uint32* pOpdir) +{ + if(port >= RTL8367C_PORTNO) + return RT_ERR_PORT_ID; + + return rtl8367c_getAsicRegBit(RTL8367C_DOT1X_PORT_OPDIR_REG, port, pOpdir); +} +/* Function Name: + * rtl8367c_setAsic1xMBEnConfig + * Description: + * Set 802.1x mac-based port enable configuration + * Input: + * port - Physical port number (0~7) + * enabled - 1: enabled, 0: disabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_setAsic1xMBEnConfig(rtk_uint32 port, rtk_uint32 enabled) +{ + if(port >= RTL8367C_PORTNO) + return RT_ERR_PORT_ID; + + return rtl8367c_setAsicRegBit(RTL8367C_DOT1X_MAC_ENABLE_REG, port, enabled); +} +/* Function Name: + * rtl8367c_getAsic1xMBEnConfig + * Description: + * Get 802.1x mac-based port enable configuration + * Input: + * port - Physical port number (0~7) + * pEnabled - 1: enabled, 0: disabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_getAsic1xMBEnConfig(rtk_uint32 port, rtk_uint32 *pEnabled) +{ + if(port >= RTL8367C_PORTNO) + return RT_ERR_PORT_ID; + + return rtl8367c_getAsicRegBit(RTL8367C_DOT1X_MAC_ENABLE_REG, port, pEnabled); +} +/* Function Name: + * rtl8367c_setAsic1xMBOpdirConfig + * Description: + * Set 802.1x mac-based operational direction + * Input: + * opdir - Operation direction 1: IN, 0:BOTH + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsic1xMBOpdirConfig(rtk_uint32 opdir) +{ + return rtl8367c_setAsicRegBit(RTL8367C_DOT1X_CFG_REG, RTL8367C_DOT1X_MAC_OPDIR_OFFSET, opdir); +} +/* Function Name: + * rtl8367c_getAsic1xMBOpdirConfig + * Description: + * Get 802.1x mac-based operational direction + * Input: + * pOpdir - Operation direction 1: IN, 0:BOTH + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsic1xMBOpdirConfig(rtk_uint32 *pOpdir) +{ + return rtl8367c_getAsicRegBit(RTL8367C_DOT1X_CFG_REG, RTL8367C_DOT1X_MAC_OPDIR_OFFSET, pOpdir); +} +/* Function Name: + * rtl8367c_setAsic1xProcConfig + * Description: + * Set 802.1x unauth. behavior configuration + * Input: + * port - Physical port number (0~7) + * proc - 802.1x unauth. behavior configuration 0:drop 1:trap to CPU 2:Guest VLAN + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * RT_ERR_DOT1X_PROC - Unauthorized behavior error + * Note: + * None + */ +ret_t rtl8367c_setAsic1xProcConfig(rtk_uint32 port, rtk_uint32 proc) +{ + + if(port >= RTL8367C_PORTNO) + return RT_ERR_PORT_ID; + + if(proc >= DOT1X_UNAUTH_END) + return RT_ERR_DOT1X_PROC; + + if(port < 8) + { + return rtl8367c_setAsicRegBits(RTL8367C_DOT1X_UNAUTH_ACT_BASE, RTL8367C_DOT1X_UNAUTH_ACT_MASK(port),proc); + } + else + { + return rtl8367c_setAsicRegBits(RTL8367C_REG_DOT1X_UNAUTH_ACT_W1, RTL8367C_DOT1X_UNAUTH_ACT_MASK(port),proc); + } +} +/* Function Name: + * rtl8367c_getAsic1xProcConfig + * Description: + * Get 802.1x unauth. behavior configuration + * Input: + * port - Physical port number (0~7) + * pProc - 802.1x unauth. behavior configuration 0:drop 1:trap to CPU 2:Guest VLAN + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_getAsic1xProcConfig(rtk_uint32 port, rtk_uint32* pProc) +{ + if(port >= RTL8367C_PORTNO) + return RT_ERR_PORT_ID; + + if(port < 8) + return rtl8367c_getAsicRegBits(RTL8367C_DOT1X_UNAUTH_ACT_BASE, RTL8367C_DOT1X_UNAUTH_ACT_MASK(port),pProc); + else + return rtl8367c_getAsicRegBits(RTL8367C_REG_DOT1X_UNAUTH_ACT_W1, RTL8367C_DOT1X_UNAUTH_ACT_MASK(port),pProc); +} +/* Function Name: + * rtl8367c_setAsic1xGuestVidx + * Description: + * Set 802.1x guest vlan index + * Input: + * index - 802.1x guest vlan index (0~31) + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_DOT1X_GVLANIDX - Invalid cvid index + * Note: + * None + */ +ret_t rtl8367c_setAsic1xGuestVidx(rtk_uint32 index) +{ + if(index >= RTL8367C_CVIDXNO) + return RT_ERR_DOT1X_GVLANIDX; + + return rtl8367c_setAsicRegBits(RTL8367C_DOT1X_CFG_REG, RTL8367C_DOT1X_GVIDX_MASK, index); +} +/* Function Name: + * rtl8367c_getAsic1xGuestVidx + * Description: + * Get 802.1x guest vlan index + * Input: + * pIndex - 802.1x guest vlan index (0~31) + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsic1xGuestVidx(rtk_uint32 *pIndex) +{ + return rtl8367c_getAsicRegBits(RTL8367C_DOT1X_CFG_REG, RTL8367C_DOT1X_GVIDX_MASK, pIndex); +} +/* Function Name: + * rtl8367c_setAsic1xGVOpdir + * Description: + * Set 802.1x guest vlan talk to auth. DA + * Input: + * enabled - 0:disable 1:enable + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsic1xGVOpdir(rtk_uint32 enabled) +{ + return rtl8367c_setAsicRegBit(RTL8367C_DOT1X_CFG_REG, RTL8367C_DOT1X_GVOPDIR_OFFSET, enabled); +} +/* Function Name: + * rtl8367c_getAsic1xGVOpdir + * Description: + * Get 802.1x guest vlan talk to auth. DA + * Input: + * pEnabled - 0:disable 1:enable + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsic1xGVOpdir(rtk_uint32 *pEnabled) +{ + return rtl8367c_getAsicRegBit(RTL8367C_DOT1X_CFG_REG, RTL8367C_DOT1X_GVOPDIR_OFFSET, pEnabled); +} +/* Function Name: + * rtl8367c_setAsic1xTrapPriority + * Description: + * Set 802.1x Trap priority + * Input: + * priority - priority (0~7) + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_INT_PRIORITY - Invalid priority + * Note: + * None + */ +ret_t rtl8367c_setAsic1xTrapPriority(rtk_uint32 priority) +{ + if(priority > RTL8367C_PRIMAX) + return RT_ERR_QOS_INT_PRIORITY; + + return rtl8367c_setAsicRegBits(RTL8367C_REG_QOS_TRAP_PRIORITY0, RTL8367C_DOT1X_PRIORTY_MASK,priority); +} +/* Function Name: + * rtl8367c_getAsic1xTrapPriority + * Description: + * Get 802.1x Trap priority + * Input: + * pPriority - priority (0~7) + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsic1xTrapPriority(rtk_uint32 *pPriority) +{ + return rtl8367c_getAsicRegBits(RTL8367C_REG_QOS_TRAP_PRIORITY0, RTL8367C_DOT1X_PRIORTY_MASK, pPriority); +} + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_dot1x.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_dot1x.h new file mode 100644 index 00000000..6e0ee12a --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_dot1x.h @@ -0,0 +1,35 @@ +#ifndef _RTL8367C_ASICDRV_DOT1X_H_ +#define _RTL8367C_ASICDRV_DOT1X_H_ + +#include + +enum DOT1X_UNAUTH_BEHAV +{ + DOT1X_UNAUTH_DROP = 0, + DOT1X_UNAUTH_TRAP, + DOT1X_UNAUTH_GVLAN, + DOT1X_UNAUTH_END +}; + +extern ret_t rtl8367c_setAsic1xPBEnConfig(rtk_uint32 port, rtk_uint32 enabled); +extern ret_t rtl8367c_getAsic1xPBEnConfig(rtk_uint32 port, rtk_uint32 *pEnabled); +extern ret_t rtl8367c_setAsic1xPBAuthConfig(rtk_uint32 port, rtk_uint32 auth); +extern ret_t rtl8367c_getAsic1xPBAuthConfig(rtk_uint32 port, rtk_uint32 *pAuth); +extern ret_t rtl8367c_setAsic1xPBOpdirConfig(rtk_uint32 port, rtk_uint32 opdir); +extern ret_t rtl8367c_getAsic1xPBOpdirConfig(rtk_uint32 port, rtk_uint32 *pOpdir); +extern ret_t rtl8367c_setAsic1xMBEnConfig(rtk_uint32 port, rtk_uint32 enabled); +extern ret_t rtl8367c_getAsic1xMBEnConfig(rtk_uint32 port, rtk_uint32 *pEnabled); +extern ret_t rtl8367c_setAsic1xMBOpdirConfig(rtk_uint32 opdir); +extern ret_t rtl8367c_getAsic1xMBOpdirConfig(rtk_uint32 *pOpdir); +extern ret_t rtl8367c_setAsic1xProcConfig(rtk_uint32 port, rtk_uint32 proc); +extern ret_t rtl8367c_getAsic1xProcConfig(rtk_uint32 port, rtk_uint32 *pProc); +extern ret_t rtl8367c_setAsic1xGuestVidx(rtk_uint32 index); +extern ret_t rtl8367c_getAsic1xGuestVidx(rtk_uint32 *pIndex); +extern ret_t rtl8367c_setAsic1xGVOpdir(rtk_uint32 enabled); +extern ret_t rtl8367c_getAsic1xGVOpdir(rtk_uint32 *pEnabled); +extern ret_t rtl8367c_setAsic1xTrapPriority(rtk_uint32 priority); +extern ret_t rtl8367c_getAsic1xTrapPriority(rtk_uint32 *pPriority); + + +#endif /*_RTL8367C_ASICDRV_DOT1X_H_*/ + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_eav.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_eav.c new file mode 100644 index 00000000..aebb7a64 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_eav.c @@ -0,0 +1,871 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTL8367C switch high-level API for RTL8367C + * Feature : Ethernet AV related functions + * + */ + +#include +/* Function Name: + * rtl8367c_setAsicEavMacAddress + * Description: + * Set PTP MAC address + * Input: + * mac - PTP mac + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicEavMacAddress(ether_addr_t mac) +{ + ret_t retVal; + rtk_uint32 regData; + rtk_uint8 *accessPtr; + rtk_uint32 i; + + accessPtr = (rtk_uint8*)&mac; + + for(i = 0; i <=2; i++) + { + regData = (*(accessPtr + (i*2)) << 8) | *(accessPtr + (i*2) + 1); + retVal = rtl8367c_setAsicReg(RTL8367C_REG_MAC_ADDR_H - i, regData); + if(retVal != RT_ERR_OK) + return retVal; + } + + return retVal; +} +/* Function Name: + * rtl8367c_getAsicEavMacAddress + * Description: + * Get PTP MAC address + * Input: + * None + * Output: + * pMac - PTP mac + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicEavMacAddress(ether_addr_t *pMac) +{ + ret_t retVal; + rtk_uint32 regData; + rtk_uint8 *accessPtr; + rtk_uint32 i; + + accessPtr = (rtk_uint8*)pMac; + + for(i = 0; i <= 2; i++) + { + retVal = rtl8367c_getAsicReg(RTL8367C_REG_MAC_ADDR_H - i, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + *accessPtr = (regData & 0xFF00) >> 8; + accessPtr ++; + *accessPtr = regData & 0xFF; + accessPtr ++; + } + + return retVal; +} + +/* Function Name: + * rtl8367c_setAsicEavTpid + * Description: + * Set PTP parser tag TPID. + * Input: + * outerTag - outter tag TPID + * innerTag - inner tag TPID + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicEavTpid(rtk_uint32 outerTag, rtk_uint32 innerTag) +{ + ret_t retVal; + + if((retVal = rtl8367c_setAsicReg(RTL8367C_REG_OTAG_TPID, outerTag)) != RT_ERR_OK) + return retVal; + if((retVal = rtl8367c_setAsicReg(RTL8367C_REG_ITAG_TPID, innerTag)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} +/* Function Name: + * rtl8367c_getAsicEavTpid + * Description: + * Get PTP parser tag TPID. + * Input: + * None + * Output: + * pOuterTag - outter tag TPID + * pInnerTag - inner tag TPID + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicEavTpid(rtk_uint32* pOuterTag, rtk_uint32* pInnerTag) +{ + ret_t retVal; + + if((retVal = rtl8367c_getAsicReg(RTL8367C_REG_OTAG_TPID, pOuterTag)) != RT_ERR_OK) + return retVal; + if((retVal = rtl8367c_getAsicReg(RTL8367C_REG_ITAG_TPID, pInnerTag)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_setAsicEavSysTime + * Description: + * Set PTP system time + * Input: + * second - seconds + * nanoSecond - nano seconds + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * The time granuality is 8 nano seconds. + */ +ret_t rtl8367c_setAsicEavSysTime(rtk_uint32 second, rtk_uint32 nanoSecond) +{ + ret_t retVal; + rtk_uint32 sec_h, sec_l, nsec8_h, nsec8_l; + rtk_uint32 nano_second_8; + rtk_uint32 regData, busyFlag, count; + + if(nanoSecond > RTL8367C_EAV_NANOSECONDMAX) + return RT_ERR_INPUT; + + regData = 0; + sec_h = second >>16; + sec_l = second & 0xFFFF; + nano_second_8 = nanoSecond >> 3; + nsec8_h = (nano_second_8 >>16) & RTL8367C_PTP_TIME_NSEC_H_NSEC_MASK; + nsec8_l = nano_second_8 &0xFFFF; + + if((retVal = rtl8367c_setAsicReg(RTL8367C_REG_PTP_TIME_SEC_H_SEC, sec_h)) != RT_ERR_OK) + return retVal; + if((retVal = rtl8367c_setAsicReg(RTL8367C_REG_PTP_TIME_SEC_L_SEC, sec_l)) != RT_ERR_OK) + return retVal; + if((retVal = rtl8367c_setAsicReg(RTL8367C_REG_PTP_TIME_NSEC_L_NSEC, nsec8_l)) != RT_ERR_OK) + return retVal; + + regData = nsec8_h | (PTP_TIME_WRITE<= PTP_TIME_ADJ_END) + return RT_ERR_INPUT; + if(nanoSecond > RTL8367C_EAV_NANOSECONDMAX) + return RT_ERR_INPUT; + + regData = 0; + sec_h = second >>16; + sec_l = second & 0xFFFF; + nano_second_8 = nanoSecond >> 3; + nsec8_h = (nano_second_8 >>16) & RTL8367C_PTP_TIME_NSEC_H_NSEC_MASK; + nsec8_l = nano_second_8 &0xFFFF; + + if((retVal = rtl8367c_setAsicReg(RTL8367C_REG_PTP_TIME_SEC_H_SEC, sec_h)) != RT_ERR_OK) + return retVal; + if((retVal = rtl8367c_setAsicReg(RTL8367C_REG_PTP_TIME_SEC_L_SEC, sec_l)) != RT_ERR_OK) + return retVal; + if((retVal = rtl8367c_setAsicReg(RTL8367C_REG_PTP_TIME_NSEC_L_NSEC, nsec8_l)) != RT_ERR_OK) + return retVal; + + if (PTP_TIME_ADJ_INC == type) + regData = nsec8_h | (PTP_TIME_INC<=PTP_TIME_CTRL_END) + return RT_ERR_INPUT; + + regData = 0; + if (PTP_TIME_CTRL_START == control) + regData = RTL8367C_CFG_TIMER_EN_FRC_MASK | RTL8367C_CFG_TIMER_1588_EN_MASK; + else + regData = 0; + + if((retVal = rtl8367c_setAsicReg(RTL8367C_REG_PTP_TIME_CFG, regData)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_getAsicEavSysTimeCtrl + * Description: + * Get PTP system time control + * Input: + * None + * Output: + * pControl - start or stop + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicEavSysTimeCtrl(rtk_uint32* pControl) +{ + ret_t retVal; + rtk_uint32 regData; + rtk_uint32 mask; + + mask = RTL8367C_CFG_TIMER_EN_FRC_MASK | RTL8367C_CFG_TIMER_1588_EN_MASK; + + if((retVal = rtl8367c_getAsicReg(RTL8367C_REG_PTP_TIME_CFG, ®Data)) != RT_ERR_OK) + return retVal; + + if( (regData & mask) == mask) + *pControl = PTP_TIME_CTRL_START; + else if( (regData & mask) == 0) + *pControl = PTP_TIME_CTRL_STOP; + else + return RT_ERR_NOT_ALLOWED; + + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_setAsicEavInterruptMask + * Description: + * Set PTP interrupt enable mask + * Input: + * imr - Interrupt mask + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * [0]:TX_SYNC, + * [1]:TX_DELAY, + * [2]:TX_PDELAY_REQ, + * [3]:TX_PDELAY_RESP, + * [4]:RX_SYNC, + * [5]:RX_DELAY, + * [6]:RX_PDELAY_REQ, + * [7]:RX_PDELAY_RESP, + */ +ret_t rtl8367c_setAsicEavInterruptMask(rtk_uint32 imr) +{ + if ((imr&(RTL8367C_PTP_INTR_MASK<<8))>0) + return RT_ERR_INPUT; + + return rtl8367c_setAsicRegBits(RTL8367C_REG_PTP_TIME_CFG2, RTL8367C_PTP_INTR_MASK, imr); +} +/* Function Name: + * rtl8367c_getAsicEavInterruptMask + * Description: + * Get PTP interrupt enable mask + * Input: + * pImr - Interrupt mask + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * [0]:TX_SYNC, + * [1]:TX_DELAY, + * [2]:TX_PDELAY_REQ, + * [3]:TX_PDELAY_RESP, + * [4]:RX_SYNC, + * [5]:RX_DELAY, + * [6]:RX_PDELAY_REQ, + * [7]:RX_PDELAY_RESP, + */ +ret_t rtl8367c_getAsicEavInterruptMask(rtk_uint32* pImr) +{ + return rtl8367c_getAsicRegBits(RTL8367C_REG_PTP_TIME_CFG2, RTL8367C_PTP_INTR_MASK, pImr); +} + +/* Function Name: + * rtl8367c_getAsicEavInterruptStatus + * Description: + * Get PTP interrupt port status mask + * Input: + * pIms - Interrupt mask + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * [0]:p0 interrupt, + * [1]:p1 interrupt, + * [2]:p2 interrupt, + * [3]:p3 interrupt, + * [4]:p4 interrupt, + */ +ret_t rtl8367c_getAsicEavInterruptStatus(rtk_uint32* pIms) +{ + return rtl8367c_getAsicRegBits(RTL8367C_REG_PTP_INTERRUPT_CFG, RTL8367C_PTP_PORT_MASK, pIms); +} + +/* Function Name: + * rtl8367c_setAsicInterruptMask + * Description: + * Clear interrupt enable mask + * Input: + * ims - Interrupt status mask + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * This API can be used to clear ASIC interrupt status and register will be cleared by writting 1. + * [0]:TX_SYNC, + * [1]:TX_DELAY, + * [2]:TX_PDELAY_REQ, + * [3]:TX_PDELAY_RESP, + * [4]:RX_SYNC, + * [5]:RX_DELAY, + * [6]:RX_PDELAY_REQ, + * [7]:RX_PDELAY_RESP, + */ +ret_t rtl8367c_setAsicEavPortInterruptStatus(rtk_uint32 port, rtk_uint32 ims) +{ + + if(port > RTL8367C_PORTNO) + return RT_ERR_PORT_ID; + + if(port < 5) + return rtl8367c_setAsicRegBits(RTL8367C_EAV_PORT_CFG_REG(port), RTL8367C_PTP_INTR_MASK,ims); + else if(port == 5) + return rtl8367c_setAsicRegBits(RTL8367C_REG_P5_EAV_CFG, RTL8367C_PTP_INTR_MASK,ims); + else if(port == 6) + return rtl8367c_setAsicRegBits(RTL8367C_REG_P6_EAV_CFG, RTL8367C_PTP_INTR_MASK,ims); + else if(port == 7) + return rtl8367c_setAsicRegBits(RTL8367C_REG_P7_EAV_CFG, RTL8367C_PTP_INTR_MASK,ims); + else if(port == 8) + return rtl8367c_setAsicRegBits(RTL8367C_REG_P8_EAV_CFG, RTL8367C_PTP_INTR_MASK,ims); + else if(port == 9) + return rtl8367c_setAsicRegBits(RTL8367C_REG_P9_EAV_CFG, RTL8367C_PTP_INTR_MASK,ims); + + return RT_ERR_OK; +} +/* Function Name: + * rtl8367c_getAsicInterruptStatus + * Description: + * Get interrupt enable mask + * Input: + * pIms - Interrupt status mask + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * [0]:TX_SYNC, + * [1]:TX_DELAY, + * [2]:TX_PDELAY_REQ, + * [3]:TX_PDELAY_RESP, + * [4]:RX_SYNC, + * [5]:RX_DELAY, + * [6]:RX_PDELAY_REQ, + * [7]:RX_PDELAY_RESP, + */ +ret_t rtl8367c_getAsicEavPortInterruptStatus(rtk_uint32 port, rtk_uint32* pIms) +{ + + if(port > RTL8367C_PORTNO) + return RT_ERR_PORT_ID; + if(port < 5) + return rtl8367c_getAsicRegBits(RTL8367C_EAV_PORT_CFG_REG(port), RTL8367C_PTP_INTR_MASK, pIms); + else if(port == 5) + return rtl8367c_getAsicRegBits(RTL8367C_REG_P5_EAV_CFG, RTL8367C_PTP_INTR_MASK, pIms); + else if(port == 6) + return rtl8367c_getAsicRegBits(RTL8367C_REG_P6_EAV_CFG, RTL8367C_PTP_INTR_MASK,pIms); + else if(port == 7) + return rtl8367c_getAsicRegBits(RTL8367C_REG_P7_EAV_CFG, RTL8367C_PTP_INTR_MASK,pIms); + else if(port == 8) + return rtl8367c_getAsicRegBits(RTL8367C_REG_P8_EAV_CFG, RTL8367C_PTP_INTR_MASK,pIms); + else if(port == 9) + return rtl8367c_getAsicRegBits(RTL8367C_REG_P9_EAV_CFG, RTL8367C_PTP_INTR_MASK,pIms); + + return RT_ERR_OK; + +} + + +/* Function Name: + * rtl8367c_setAsicEavPortEnable + * Description: + * Set per-port EAV function enable/disable + * Input: + * port - Physical port number (0~9) + * enabled - 1: enabled, 0: disabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * If EAV function is enabled, PTP event messgae packet will be attached PTP timestamp for trapping + */ +ret_t rtl8367c_setAsicEavPortEnable(rtk_uint32 port, rtk_uint32 enabled) +{ + if(port > RTL8367C_PORTNO) + return RT_ERR_PORT_ID; + + if(port < 5) + return rtl8367c_setAsicRegBit(RTL8367C_EAV_PORT_CFG_REG(port), RTL8367C_EAV_CFG_PTP_PHY_EN_EN_OFFSET, enabled); + else if(port == 5) + return rtl8367c_setAsicRegBit(RTL8367C_REG_P5_EAV_CFG, RTL8367C_EAV_CFG_PTP_PHY_EN_EN_OFFSET, enabled); + else if(port == 6) + return rtl8367c_setAsicRegBit(RTL8367C_REG_P6_EAV_CFG, RTL8367C_EAV_CFG_PTP_PHY_EN_EN_OFFSET, enabled); + else if(port == 7) + return rtl8367c_setAsicRegBit(RTL8367C_REG_P7_EAV_CFG, RTL8367C_EAV_CFG_PTP_PHY_EN_EN_OFFSET, enabled); + else if(port == 8) + return rtl8367c_setAsicRegBit(RTL8367C_REG_P8_EAV_CFG, RTL8367C_EAV_CFG_PTP_PHY_EN_EN_OFFSET, enabled); + else if(port == 9) + return rtl8367c_setAsicRegBit(RTL8367C_REG_P9_EAV_CFG, RTL8367C_EAV_CFG_PTP_PHY_EN_EN_OFFSET, enabled); + + + return RT_ERR_OK; +} +/* Function Name: + * rtl8367c_getAsicEavPortEnable + * Description: + * Get per-port EAV function enable/disable + * Input: + * port - Physical port number (0~9) + * pEnabled - 1: enabled, 0: disabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_getAsicEavPortEnable(rtk_uint32 port, rtk_uint32 *pEnabled) +{ + if(port > RTL8367C_PORTNO) + return RT_ERR_PORT_ID; + + + + if(port < 5) + return rtl8367c_getAsicRegBit(RTL8367C_EAV_PORT_CFG_REG(port), RTL8367C_EAV_CFG_PTP_PHY_EN_EN_OFFSET, pEnabled); + else if(port == 5) + return rtl8367c_getAsicRegBit(RTL8367C_REG_P5_EAV_CFG, RTL8367C_EAV_CFG_PTP_PHY_EN_EN_OFFSET, pEnabled); + else if(port == 6) + return rtl8367c_getAsicRegBit(RTL8367C_REG_P6_EAV_CFG, RTL8367C_EAV_CFG_PTP_PHY_EN_EN_OFFSET, pEnabled); + else if(port == 7) + return rtl8367c_getAsicRegBit(RTL8367C_REG_P7_EAV_CFG, RTL8367C_EAV_CFG_PTP_PHY_EN_EN_OFFSET, pEnabled); + else if(port == 8) + return rtl8367c_getAsicRegBit(RTL8367C_REG_P8_EAV_CFG, RTL8367C_EAV_CFG_PTP_PHY_EN_EN_OFFSET, pEnabled); + else if(port == 9) + return rtl8367c_getAsicRegBit(RTL8367C_REG_P9_EAV_CFG, RTL8367C_EAV_CFG_PTP_PHY_EN_EN_OFFSET, pEnabled); + + + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_getAsicEavPortTimeStamp + * Description: + * Get PTP port time stamp + * Input: + * port - Physical port number (0~9) + * type - PTP packet type + * Output: + * timeStamp - seconds + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * The time granuality is 8 nano seconds. + */ +ret_t rtl8367c_getAsicEavPortTimeStamp(rtk_uint32 port, rtk_uint32 type, rtl8367c_ptp_time_stamp_t* timeStamp) +{ + ret_t retVal; + rtk_uint32 sec_h = 0, sec_l = 0, nsec8_h = 0, nsec8_l = 0; + rtk_uint32 nano_second_8; + + if(port > 9) + return RT_ERR_PORT_ID; + if(type >= PTP_PKT_TYPE_END) + return RT_ERR_INPUT; + + if(port < 5){ + if((retVal = rtl8367c_getAsicReg(RTL8367C_REG_SEQ_ID(port, type), &timeStamp->sequence_id))!= RT_ERR_OK) + return retVal; + if((retVal = rtl8367c_getAsicReg(RTL8367C_REG_PORT_SEC_H(port) , &sec_h)) != RT_ERR_OK) + return retVal; + if((retVal = rtl8367c_getAsicReg(RTL8367C_REG_PORT_SEC_L(port), &sec_l)) != RT_ERR_OK) + return retVal; + if((retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_PORT_NSEC_H(port) , RTL8367C_PORT_NSEC_H_MASK,&nsec8_h)) != RT_ERR_OK) + return retVal; + if((retVal = rtl8367c_getAsicReg(RTL8367C_REG_PORT_NSEC_L(port) , &nsec8_l)) != RT_ERR_OK) + return retVal; + }else if(port == 5){ + if((retVal = rtl8367c_getAsicReg(RTL8367C_REG_P5_TX_SYNC_SEQ_ID+type, &timeStamp->sequence_id))!= RT_ERR_OK) + return retVal; + if((retVal = rtl8367c_getAsicReg(RTL8367C_REG_P5_PORT_SEC_31_16, &sec_h)) != RT_ERR_OK) + return retVal; + if((retVal = rtl8367c_getAsicReg(RTL8367C_REG_P5_PORT_SEC_15_0, &sec_l)) != RT_ERR_OK) + return retVal; + if((retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_P5_PORT_NSEC_26_16 , RTL8367C_PORT_NSEC_H_MASK,&nsec8_h)) != RT_ERR_OK) + return retVal; + if((retVal = rtl8367c_getAsicReg(RTL8367C_REG_P5_PORT_NSEC_15_0, &nsec8_l)) != RT_ERR_OK) + return retVal; + }else if(port == 6){ + if((retVal = rtl8367c_getAsicReg(RTL8367C_REG_P6_TX_SYNC_SEQ_ID+type, &timeStamp->sequence_id))!= RT_ERR_OK) + return retVal; + if((retVal = rtl8367c_getAsicReg(RTL8367C_REG_P6_PORT_SEC_31_16, &sec_h)) != RT_ERR_OK) + return retVal; + if((retVal = rtl8367c_getAsicReg(RTL8367C_REG_P6_PORT_SEC_15_0, &sec_l)) != RT_ERR_OK) + return retVal; + if((retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_P6_PORT_NSEC_26_16 , RTL8367C_PORT_NSEC_H_MASK,&nsec8_h)) != RT_ERR_OK) + return retVal; + if((retVal = rtl8367c_getAsicReg(RTL8367C_REG_P6_PORT_NSEC_15_0, &nsec8_l)) != RT_ERR_OK) + return retVal; + }else if(port == 7){ + if((retVal = rtl8367c_getAsicReg(RTL8367C_REG_P7_TX_SYNC_SEQ_ID+type, &timeStamp->sequence_id))!= RT_ERR_OK) + return retVal; + if((retVal = rtl8367c_getAsicReg(RTL8367C_REG_P7_PORT_SEC_31_16, &sec_h)) != RT_ERR_OK) + return retVal; + if((retVal = rtl8367c_getAsicReg(RTL8367C_REG_P7_PORT_SEC_15_0, &sec_l)) != RT_ERR_OK) + return retVal; + if((retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_P7_PORT_NSEC_26_16 , RTL8367C_PORT_NSEC_H_MASK,&nsec8_h)) != RT_ERR_OK) + return retVal; + if((retVal = rtl8367c_getAsicReg(RTL8367C_REG_P7_PORT_NSEC_15_0, &nsec8_l)) != RT_ERR_OK) + return retVal; + }else if(port == 8){ + if((retVal = rtl8367c_getAsicReg(RTL8367C_REG_P8_TX_SYNC_SEQ_ID+type, &timeStamp->sequence_id))!= RT_ERR_OK) + return retVal; + if((retVal = rtl8367c_getAsicReg(RTL8367C_REG_P8_PORT_SEC_31_16, &sec_h)) != RT_ERR_OK) + return retVal; + if((retVal = rtl8367c_getAsicReg(RTL8367C_REG_P8_PORT_SEC_15_0, &sec_l)) != RT_ERR_OK) + return retVal; + if((retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_P8_PORT_NSEC_26_16 , RTL8367C_PORT_NSEC_H_MASK,&nsec8_h)) != RT_ERR_OK) + return retVal; + if((retVal = rtl8367c_getAsicReg(RTL8367C_REG_P8_PORT_NSEC_15_0, &nsec8_l)) != RT_ERR_OK) + return retVal; + }else if(port == 9){ + if((retVal = rtl8367c_getAsicReg(RTL8367C_REG_P9_TX_SYNC_SEQ_ID+type, &timeStamp->sequence_id))!= RT_ERR_OK) + return retVal; + if((retVal = rtl8367c_getAsicReg(RTL8367C_REG_P9_PORT_SEC_31_16, &sec_h)) != RT_ERR_OK) + return retVal; + if((retVal = rtl8367c_getAsicReg(RTL8367C_REG_P9_PORT_SEC_15_0, &sec_l)) != RT_ERR_OK) + return retVal; + if((retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_P9_PORT_NSEC_26_16 , RTL8367C_PORT_NSEC_H_MASK,&nsec8_h)) != RT_ERR_OK) + return retVal; + if((retVal = rtl8367c_getAsicReg(RTL8367C_REG_P9_PORT_NSEC_15_0, &nsec8_l)) != RT_ERR_OK) + return retVal; + } + + timeStamp->second = (sec_h<<16) | sec_l; + nano_second_8 = (nsec8_h<<16) | nsec8_l; + timeStamp->nano_second = nano_second_8<<3; + + return RT_ERR_OK; +} + + +/* Function Name: + * rtl8367c_setAsicEavTrap + * Description: + * Set per-port PTP packet trap to CPU + * Input: + * port - Physical port number (0~5) + * enabled - 1: enabled, 0: disabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * If EAV trap enabled, switch will trap PTP packet to CPU + */ +ret_t rtl8367c_setAsicEavTrap(rtk_uint32 port, rtk_uint32 enabled) +{ + if(port > RTL8367C_PORTNO) + return RT_ERR_PORT_ID; + + return rtl8367c_setAsicRegBit(RTL8367C_REG_PTP_PORT0_CFG1 + (port * 0x20), RTL8367C_PTP_PORT0_CFG1_OFFSET, enabled); +} +/* Function Name: + * rtl8367c_getAsicEavTimeSyncEn + * Description: + * Get per-port EPTP packet trap to CPU + * Input: + * port - Physical port number (0~5) + * pEnabled - 1: enabled, 0: disabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_getAsicEavTrap(rtk_uint32 port, rtk_uint32 *pEnabled) +{ + if(port > RTL8367C_PORTNO) + return RT_ERR_PORT_ID; + + return rtl8367c_getAsicRegBit(RTL8367C_REG_PTP_PORT0_CFG1 + (port * 0x20), RTL8367C_PTP_PORT0_CFG1_OFFSET, pEnabled); +} + +/* Function Name: + * rtl8367c_setAsicEavEnable + * Description: + * Set per-port EAV function enable/disable + * Input: + * port - Physical port number (0~5) + * enabled - 1: enabled, 0: disabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * If EAV function is enabled, PTP event messgae packet will be attached PTP timestamp for trapping + */ +ret_t rtl8367c_setAsicEavEnable(rtk_uint32 port, rtk_uint32 enabled) +{ + if(port > RTL8367C_PORTNO) + return RT_ERR_PORT_ID; + + return rtl8367c_setAsicRegBit(RTL8367C_REG_EAV_CTRL0, port, enabled); +} +/* Function Name: + * rtl8367c_getAsicEavEnable + * Description: + * Get per-port EAV function enable/disable + * Input: + * port - Physical port number (0~5) + * pEnabled - 1: enabled, 0: disabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_getAsicEavEnable(rtk_uint32 port, rtk_uint32 *pEnabled) +{ + if(port > RTL8367C_PORTNO) + return RT_ERR_PORT_ID; + + return rtl8367c_getAsicRegBit(RTL8367C_REG_EAV_CTRL0, port, pEnabled); +} +/* Function Name: + * rtl8367c_setAsicEavPriRemapping + * Description: + * Set non-EAV streaming priority remapping + * Input: + * srcpriority - Priority value + * priority - Absolute priority value + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_INT_PRIORITY - Invalid priority + * Note: + * None + */ +ret_t rtl8367c_setAsicEavPriRemapping(rtk_uint32 srcpriority, rtk_uint32 priority) +{ + if(srcpriority > RTL8367C_PRIMAX || priority > RTL8367C_PRIMAX) + return RT_ERR_QOS_INT_PRIORITY; + + return rtl8367c_setAsicRegBits(RTL8367C_EAV_PRIORITY_REMAPPING_REG(srcpriority), RTL8367C_EAV_PRIORITY_REMAPPING_MASK(srcpriority),priority); +} +/* Function Name: + * rtl8367c_getAsicEavPriRemapping + * Description: + * Get non-EAV streaming priority remapping + * Input: + * srcpriority - Priority value + * pPriority - Absolute priority value + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_INT_PRIORITY - Invalid priority + * Note: + * None + */ +ret_t rtl8367c_getAsicEavPriRemapping(rtk_uint32 srcpriority, rtk_uint32 *pPriority) +{ + if(srcpriority > RTL8367C_PRIMAX ) + return RT_ERR_QOS_INT_PRIORITY; + + return rtl8367c_getAsicRegBits(RTL8367C_EAV_PRIORITY_REMAPPING_REG(srcpriority), RTL8367C_EAV_PRIORITY_REMAPPING_MASK(srcpriority),pPriority); +} + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_eav.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_eav.h new file mode 100644 index 00000000..4205c5a6 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_eav.h @@ -0,0 +1,92 @@ +#ifndef _RTL8367C_ASICDRV_EAV_H_ +#define _RTL8367C_ASICDRV_EAV_H_ + +#include + +typedef enum RTL8367C_PTP_TIME_CMD_E +{ + PTP_TIME_READ = 0, + PTP_TIME_WRITE, + PTP_TIME_INC, + PTP_TIME_DEC, + PTP_TIME_CMD_END +}RTL8367C_PTP_TIME_CMD; + +typedef enum RTL8367C_PTP_TIME_ADJ_E +{ + PTP_TIME_ADJ_INC = 0, + PTP_TIME_ADJ_DEC, + PTP_TIME_ADJ_END +}RTL8367C_PTP_TIME_ADJ; + +typedef enum RTL8367C_PTP_TIME_CTRL_E +{ + PTP_TIME_CTRL_STOP = 0, + PTP_TIME_CTRL_START, + PTP_TIME_CTRL_END +}RTL8367C_PTP_TIME_CTRL; + +typedef enum RTL8367C_PTP_INTR_IMRS_E +{ + PTP_IMRS_TX_SYNC, + PTP_IMRS_TX_DELAY_REQ, + PTP_IMRS_TX_PDELAY_REQ, + PTP_IMRS_TX_PDELAY_RESP, + PTP_IMRS_RX_SYNC, + PTP_IMRS_RX_DELAY_REQ, + PTP_IMRS_RX_PDELAY_REQ, + PTP_IMRS_RX_PDELAY_RESP, + PTP_IMRS_END, +}RTL8367C_PTP_INTR_IMRS; + + +typedef enum RTL8367C_PTP_PKT_TYPE_E +{ + PTP_PKT_TYPE_TX_SYNC, + PTP_PKT_TYPE_TX_DELAY_REQ, + PTP_PKT_TYPE_TX_PDELAY_REQ, + PTP_PKT_TYPE_TX_PDELAY_RESP, + PTP_PKT_TYPE_RX_SYNC, + PTP_PKT_TYPE_RX_DELAY_REQ, + PTP_PKT_TYPE_RX_PDELAY_REQ, + PTP_PKT_TYPE_RX_PDELAY_RESP, + PTP_PKT_TYPE_END, +}RTL8367C_PTP_PKT_TYPE; + +typedef struct rtl8367c_ptp_time_stamp_s{ + rtk_uint32 sequence_id; + rtk_uint32 second; + rtk_uint32 nano_second; +}rtl8367c_ptp_time_stamp_t; + +#define RTL8367C_PTP_INTR_MASK 0xFF + +#define RTL8367C_PTP_PORT_MASK 0x3FF + +extern ret_t rtl8367c_setAsicEavMacAddress(ether_addr_t mac); +extern ret_t rtl8367c_getAsicEavMacAddress(ether_addr_t *pMac); +extern ret_t rtl8367c_setAsicEavTpid(rtk_uint32 outerTag, rtk_uint32 innerTag); +extern ret_t rtl8367c_getAsicEavTpid(rtk_uint32* pOuterTag, rtk_uint32* pInnerTag); +extern ret_t rtl8367c_setAsicEavSysTime(rtk_uint32 second, rtk_uint32 nanoSecond); +extern ret_t rtl8367c_getAsicEavSysTime(rtk_uint32* pSecond, rtk_uint32* pNanoSecond); +extern ret_t rtl8367c_setAsicEavSysTimeAdjust(rtk_uint32 type, rtk_uint32 second, rtk_uint32 nanoSecond); +extern ret_t rtl8367c_setAsicEavSysTimeCtrl(rtk_uint32 control); +extern ret_t rtl8367c_getAsicEavSysTimeCtrl(rtk_uint32* pControl); +extern ret_t rtl8367c_setAsicEavInterruptMask(rtk_uint32 imr); +extern ret_t rtl8367c_getAsicEavInterruptMask(rtk_uint32* pImr); +extern ret_t rtl8367c_getAsicEavInterruptStatus(rtk_uint32* pIms); +extern ret_t rtl8367c_setAsicEavPortInterruptStatus(rtk_uint32 port, rtk_uint32 ims); +extern ret_t rtl8367c_getAsicEavPortInterruptStatus(rtk_uint32 port, rtk_uint32* pIms); +extern ret_t rtl8367c_setAsicEavPortEnable(rtk_uint32 port, rtk_uint32 enabled); +extern ret_t rtl8367c_getAsicEavPortEnable(rtk_uint32 port, rtk_uint32 *pEnabled); +extern ret_t rtl8367c_getAsicEavPortTimeStamp(rtk_uint32 port, rtk_uint32 type, rtl8367c_ptp_time_stamp_t* timeStamp); + +extern ret_t rtl8367c_setAsicEavTrap(rtk_uint32 port, rtk_uint32 enabled); +extern ret_t rtl8367c_getAsicEavTrap(rtk_uint32 port, rtk_uint32 *pEnabled); +extern ret_t rtl8367c_setAsicEavEnable(rtk_uint32 port, rtk_uint32 enabled); +extern ret_t rtl8367c_getAsicEavEnable(rtk_uint32 port, rtk_uint32 *pEnabled); +extern ret_t rtl8367c_setAsicEavPriRemapping(rtk_uint32 srcpriority, rtk_uint32 priority); +extern ret_t rtl8367c_getAsicEavPriRemapping(rtk_uint32 srcpriority, rtk_uint32 *pPriority); + +#endif /*#ifndef _RTL8367C_ASICDRV_EAV_H_*/ + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_eee.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_eee.c new file mode 100644 index 00000000..341dbc67 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_eee.c @@ -0,0 +1,165 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTL8370 switch high-level API for RTL8367C + * Feature : + * + */ + +#include +#include + +/* +@func ret_t | rtl8367c_setAsicEee100M | Set eee force mode function enable/disable. +@parm rtk_uint32 | port | The port number. +@parm rtk_uint32 | enabled | 1: enabled, 0: disabled. +@rvalue RT_ERR_OK | Success. +@rvalue RT_ERR_SMI | SMI access error. +@rvalue RT_ERR_INPUT | Invalid input parameter. +@comm + This API set the 100M EEE enable function. + +*/ +ret_t rtl8367c_setAsicEee100M(rtk_uint32 port, rtk_uint32 enable) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + + if(port >= RTL8367C_PORTNO) + return RT_ERR_PORT_ID; + + if (enable > 1) + return RT_ERR_INPUT; + + if((retVal = rtl8367c_getAsicPHYOCPReg(port, EEE_OCP_PHY_ADDR, ®Data)) != RT_ERR_OK) + return retVal; + + if(enable) + regData |= (0x0001 << 1); + else + regData &= ~(0x0001 << 1); + + if((retVal = rtl8367c_setAsicPHYOCPReg(port, EEE_OCP_PHY_ADDR, regData)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_getAsicReg(RTL8367C_PORT_EEE_CFG_REG(port), ®Data)) != RT_ERR_OK) + return retVal; + + if(enable) + regData |= (0x0001 << 11); + else + regData &= ~(0x0001 << 11); + + if((retVal = rtl8367c_setAsicReg(RTL8367C_PORT_EEE_CFG_REG(port),regData)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* +@func ret_t | rtl8367c_getAsicEee100M | Get 100M eee enable/disable. +@parm rtk_uint32 | port | The port number. +@parm rtk_uint32* | enabled | 1: enabled, 0: disabled. +@rvalue RT_ERR_OK | Success. +@rvalue RT_ERR_SMI | SMI access error. +@rvalue RT_ERR_INPUT | Invalid input parameter. +@comm + This API get the 100M EEE function. +*/ +ret_t rtl8367c_getAsicEee100M(rtk_uint32 port, rtk_uint32 *enable) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + + if(port >= RTL8367C_PORTNO) + return RT_ERR_PORT_ID; + + if((retVal = rtl8367c_getAsicPHYOCPReg(port, EEE_OCP_PHY_ADDR, ®Data)) != RT_ERR_OK) + return retVal; + + *enable = (regData & (0x0001 << 1)) ? ENABLED : DISABLED; + return RT_ERR_OK; +} + +/* +@func ret_t | rtl8367c_setAsicEeeGiga | Set eee force mode function enable/disable. +@parm rtk_uint32 | port | The port number. +@parm rtk_uint32 | enabled | 1: enabled, 0: disabled. +@rvalue RT_ERR_OK | Success. +@rvalue RT_ERR_SMI | SMI access error. +@rvalue RT_ERR_INPUT | Invalid input parameter. +@comm + This API set the 100M EEE enable function. + +*/ +ret_t rtl8367c_setAsicEeeGiga(rtk_uint32 port, rtk_uint32 enable) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + + if(port >= RTL8367C_PORTNO) + return RT_ERR_PORT_ID; + + if (enable > 1) + return RT_ERR_INPUT; + + if((retVal = rtl8367c_getAsicPHYOCPReg(port, EEE_OCP_PHY_ADDR, ®Data)) != RT_ERR_OK) + return retVal; + + if(enable) + regData |= (0x0001 << 2); + else + regData &= ~(0x0001 << 2); + + if((retVal = rtl8367c_setAsicPHYOCPReg(port, EEE_OCP_PHY_ADDR, regData)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_getAsicReg(RTL8367C_PORT_EEE_CFG_REG(port), ®Data)) != RT_ERR_OK) + return retVal; + + if(enable) + regData |= (0x0001 << 10); + else + regData &= ~(0x0001 << 10); + + if((retVal = rtl8367c_setAsicReg(RTL8367C_PORT_EEE_CFG_REG(port),regData)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* +@func ret_t | rtl8367c_getAsicEeeGiga | Get 100M eee enable/disable. +@parm rtk_uint32 | port | The port number. +@parm rtk_uint32* | enabled | 1: enabled, 0: disabled. +@rvalue RT_ERR_OK | Success. +@rvalue RT_ERR_SMI | SMI access error. +@rvalue RT_ERR_INPUT | Invalid input parameter. +@comm + This API get the 100M EEE function. +*/ +ret_t rtl8367c_getAsicEeeGiga(rtk_uint32 port, rtk_uint32 *enable) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + + if(port >= RTL8367C_PORTNO) + return RT_ERR_PORT_ID; + + if((retVal = rtl8367c_getAsicPHYOCPReg(port, EEE_OCP_PHY_ADDR, ®Data)) != RT_ERR_OK) + return retVal; + + *enable = (regData & (0x0001 << 2)) ? ENABLED : DISABLED; + return RT_ERR_OK; +} diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_eee.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_eee.h new file mode 100644 index 00000000..f02fa929 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_eee.h @@ -0,0 +1,14 @@ +#ifndef _RTL8367C_ASICDRV_EEE_H_ +#define _RTL8367C_ASICDRV_EEE_H_ + +#include + +#define EEE_OCP_PHY_ADDR (0xA5D0) + +extern ret_t rtl8367c_setAsicEee100M(rtk_uint32 port, rtk_uint32 enable); +extern ret_t rtl8367c_getAsicEee100M(rtk_uint32 port, rtk_uint32 *enable); +extern ret_t rtl8367c_setAsicEeeGiga(rtk_uint32 port, rtk_uint32 enable); +extern ret_t rtl8367c_getAsicEeeGiga(rtk_uint32 port, rtk_uint32 *enable); + + +#endif /*_RTL8367C_ASICDRV_EEE_H_*/ diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_fc.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_fc.c new file mode 100644 index 00000000..ae0de1d9 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_fc.c @@ -0,0 +1,1356 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTL8367C switch high-level API for RTL8367C + * Feature : Flow control related functions + * + */ + +#include +/* Function Name: + * rtl8367c_setAsicFlowControlSelect + * Description: + * Set system flow control type + * Input: + * select - System flow control type 1: Ingress flow control 0:Egress flow control + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicFlowControlSelect(rtk_uint32 select) +{ + return rtl8367c_setAsicRegBit(RTL8367C_REG_FLOWCTRL_CTRL0, RTL8367C_FLOWCTRL_TYPE_OFFSET, select); +} +/* Function Name: + * rtl8367c_getAsicFlowControlSelect + * Description: + * Get system flow control type + * Input: + * pSelect - System flow control type 1: Ingress flow control 0:Egress flow control + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicFlowControlSelect(rtk_uint32 *pSelect) +{ + return rtl8367c_getAsicRegBit(RTL8367C_REG_FLOWCTRL_CTRL0, RTL8367C_FLOWCTRL_TYPE_OFFSET, pSelect); +} +/* Function Name: + * rtl8367c_setAsicFlowControlJumboMode + * Description: + * Set Jumbo threhsold for flow control + * Input: + * enabled - Jumbo mode flow control 1: Enable 0:Disable + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicFlowControlJumboMode(rtk_uint32 enabled) +{ + return rtl8367c_setAsicRegBit(RTL8367C_REG_FLOWCTRL_JUMBO_SIZE, RTL8367C_JUMBO_MODE_OFFSET, enabled); +} +/* Function Name: + * rtl8367c_getAsicFlowControlJumboMode + * Description: + * Get Jumbo threhsold for flow control + * Input: + * pEnabled - Jumbo mode flow control 1: Enable 0:Disable + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicFlowControlJumboMode(rtk_uint32* pEnabled) +{ + return rtl8367c_getAsicRegBit(RTL8367C_REG_FLOWCTRL_JUMBO_SIZE, RTL8367C_JUMBO_MODE_OFFSET, pEnabled); +} +/* Function Name: + * rtl8367c_setAsicFlowControlJumboModeSize + * Description: + * Set Jumbo size for Jumbo mode flow control + * Input: + * size - Jumbo size 0:3Kbytes 1:4Kbytes 2:6Kbytes 3:9Kbytes + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - input parameter out of range + * Note: + * None + */ +ret_t rtl8367c_setAsicFlowControlJumboModeSize(rtk_uint32 size) +{ + if(size >= FC_JUMBO_SIZE_END) + return RT_ERR_OUT_OF_RANGE; + + return rtl8367c_setAsicRegBits(RTL8367C_REG_FLOWCTRL_JUMBO_SIZE, RTL8367C_JUMBO_SIZE_MASK, size); +} +/* Function Name: + * rtl8367c_getAsicFlowControlJumboModeSize + * Description: + * Get Jumbo size for Jumbo mode flow control + * Input: + * pSize - Jumbo size 0:3Kbytes 1:4Kbytes 2:6Kbytes 3:9Kbytes + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicFlowControlJumboModeSize(rtk_uint32* pSize) +{ + return rtl8367c_getAsicRegBits(RTL8367C_REG_FLOWCTRL_JUMBO_SIZE, RTL8367C_JUMBO_SIZE_MASK, pSize); +} + +/* Function Name: + * rtl8367c_setAsicFlowControlQueueEgressEnable + * Description: + * Set flow control ability for each queue + * Input: + * port - Physical port number (0~7) + * qid - Queue id + * enabled - 1: enabled, 0: disabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * RT_ERR_QUEUE_ID - Invalid queue id + * Note: + * None + */ +ret_t rtl8367c_setAsicFlowControlQueueEgressEnable(rtk_uint32 port, rtk_uint32 qid, rtk_uint32 enabled) +{ + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + if(qid > RTL8367C_QIDMAX) + return RT_ERR_QUEUE_ID; + + return rtl8367c_setAsicRegBit(RTL8367C_FLOWCRTL_EGRESS_QUEUE_ENABLE_REG(port), RTL8367C_FLOWCRTL_EGRESS_QUEUE_ENABLE_REG_OFFSET(port)+ qid, enabled); +} +/* Function Name: + * rtl8367c_getAsicFlowControlQueueEgressEnable + * Description: + * Get flow control ability for each queue + * Input: + * port - Physical port number (0~7) + * qid - Queue id + * pEnabled - 1: enabled, 0: disabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * RT_ERR_QUEUE_ID - Invalid queue id + * Note: + * None + */ +ret_t rtl8367c_getAsicFlowControlQueueEgressEnable(rtk_uint32 port, rtk_uint32 qid, rtk_uint32* pEnabled) +{ + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + if(qid > RTL8367C_QIDMAX) + return RT_ERR_QUEUE_ID; + + return rtl8367c_getAsicRegBit(RTL8367C_FLOWCRTL_EGRESS_QUEUE_ENABLE_REG(port), RTL8367C_FLOWCRTL_EGRESS_QUEUE_ENABLE_REG_OFFSET(port)+ qid, pEnabled); +} +/* Function Name: + * rtl8367c_setAsicFlowControlDropAll + * Description: + * Set system-based drop parameters + * Input: + * dropall - Whole system drop threshold + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - input parameter out of range + * Note: + * None + */ +ret_t rtl8367c_setAsicFlowControlDropAll(rtk_uint32 dropall) +{ + if(dropall >= RTK_MAX_BUF_PAGE_NUM) + return RT_ERR_OUT_OF_RANGE; + + return rtl8367c_setAsicRegBits(RTL8367C_REG_FLOWCTRL_CTRL0, RTL8367C_DROP_ALL_THRESHOLD_MASK, dropall); +} +/* Function Name: + * rtl8367c_getAsicFlowControlDropAll + * Description: + * Get system-based drop parameters + * Input: + * pDropall - Whole system drop threshold + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicFlowControlDropAll(rtk_uint32* pDropall) +{ + return rtl8367c_getAsicRegBits(RTL8367C_REG_FLOWCTRL_CTRL0, RTL8367C_DROP_ALL_THRESHOLD_MASK, pDropall); +} +/* Function Name: + * rtl8367c_setAsicFlowControlPauseAll + * Description: + * Set system-based all ports enable flow control parameters + * Input: + * threshold - Whole system pause all threshold + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - input parameter out of range + * Note: + * None + */ +ret_t rtl8367c_setAsicFlowControlPauseAllThreshold(rtk_uint32 threshold) +{ + if(threshold >= RTK_MAX_BUF_PAGE_NUM) + return RT_ERR_OUT_OF_RANGE; + + return rtl8367c_setAsicRegBits(RTL8367C_REG_FLOWCTRL_ALL_ON, RTL8367C_FLOWCTRL_ALL_ON_THRESHOLD_MASK, threshold); +} +/* Function Name: + * rtl8367c_getAsicFlowControlPauseAllThreshold + * Description: + * Get system-based all ports enable flow control parameters + * Input: + * pThreshold - Whole system pause all threshold + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicFlowControlPauseAllThreshold(rtk_uint32 *pThreshold) +{ + return rtl8367c_getAsicRegBits(RTL8367C_REG_FLOWCTRL_ALL_ON, RTL8367C_FLOWCTRL_ALL_ON_THRESHOLD_MASK, pThreshold); +} +/* Function Name: + * rtl8367c_setAsicFlowControlSystemThreshold + * Description: + * Set system-based flow control parameters + * Input: + * onThreshold - Flow control turn ON threshold + * offThreshold - Flow control turn OFF threshold + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - input parameter out of range + * Note: + * None + */ +ret_t rtl8367c_setAsicFlowControlSystemThreshold(rtk_uint32 onThreshold, rtk_uint32 offThreshold) +{ + ret_t retVal; + + if((onThreshold >= RTK_MAX_BUF_PAGE_NUM) || (offThreshold >= RTK_MAX_BUF_PAGE_NUM)) + return RT_ERR_OUT_OF_RANGE; + + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_FLOWCTRL_SYS_OFF, RTL8367C_FLOWCTRL_SYS_OFF_MASK, offThreshold); + + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_FLOWCTRL_SYS_ON, RTL8367C_FLOWCTRL_SYS_ON_MASK, onThreshold); + + return retVal; +} +/* Function Name: + * rtl8367c_getAsicFlowControlSystemThreshold + * Description: + * Get system-based flow control parameters + * Input: + * pOnThreshold - Flow control turn ON threshold + * pOffThreshold - Flow control turn OFF threshold + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicFlowControlSystemThreshold(rtk_uint32 *pOnThreshold, rtk_uint32 *pOffThreshold) +{ + ret_t retVal; + + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_FLOWCTRL_SYS_OFF, RTL8367C_FLOWCTRL_SYS_OFF_MASK, pOffThreshold); + + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_FLOWCTRL_SYS_ON, RTL8367C_FLOWCTRL_SYS_ON_MASK, pOnThreshold); + + return retVal; +} +/* Function Name: + * rtl8367c_setAsicFlowControlSharedThreshold + * Description: + * Set share-based flow control parameters + * Input: + * onThreshold - Flow control turn ON threshold + * offThreshold - Flow control turn OFF threshold + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - input parameter out of range + * Note: + * None + */ +ret_t rtl8367c_setAsicFlowControlSharedThreshold(rtk_uint32 onThreshold, rtk_uint32 offThreshold) +{ + ret_t retVal; + + if((onThreshold >= RTK_MAX_BUF_PAGE_NUM) || (offThreshold >= RTK_MAX_BUF_PAGE_NUM)) + return RT_ERR_OUT_OF_RANGE; + + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_FLOWCTRL_SHARE_OFF, RTL8367C_FLOWCTRL_SHARE_OFF_MASK, offThreshold); + + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_FLOWCTRL_SHARE_ON, RTL8367C_FLOWCTRL_SHARE_ON_MASK, onThreshold); + + return retVal; +} +/* Function Name: + * rtl8367c_getAsicFlowControlSharedThreshold + * Description: + * Get share-based flow control parameters + * Input: + * pOnThreshold - Flow control turn ON threshold + * pOffThreshold - Flow control turn OFF threshold + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicFlowControlSharedThreshold(rtk_uint32 *pOnThreshold, rtk_uint32 *pOffThreshold) +{ + ret_t retVal; + + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_FLOWCTRL_SHARE_OFF, RTL8367C_FLOWCTRL_SHARE_OFF_MASK, pOffThreshold); + + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_FLOWCTRL_SHARE_ON, RTL8367C_FLOWCTRL_SHARE_ON_MASK, pOnThreshold); + + return retVal; +} +/* Function Name: + * rtl8367c_setAsicFlowControlPortThreshold + * Description: + * Set Port-based flow control parameters + * Input: + * onThreshold - Flow control turn ON threshold + * offThreshold - Flow control turn OFF threshold + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - input parameter out of range + * Note: + * None + */ +ret_t rtl8367c_setAsicFlowControlPortThreshold(rtk_uint32 onThreshold, rtk_uint32 offThreshold) +{ + ret_t retVal; + + if((onThreshold >= RTK_MAX_BUF_PAGE_NUM) || (offThreshold >= RTK_MAX_BUF_PAGE_NUM)) + return RT_ERR_OUT_OF_RANGE; + + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_FLOWCTRL_PORT_OFF, RTL8367C_FLOWCTRL_PORT_OFF_MASK, offThreshold); + + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_FLOWCTRL_PORT_ON, RTL8367C_FLOWCTRL_PORT_ON_MASK, onThreshold); + + return retVal; +} +/* Function Name: + * rtl8367c_getAsicFlowControlPortThreshold + * Description: + * Get Port-based flow control parameters + * Input: + * pOnThreshold - Flow control turn ON threshold + * pOffThreshold - Flow control turn OFF threshold + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicFlowControlPortThreshold(rtk_uint32 *pOnThreshold, rtk_uint32 *pOffThreshold) +{ + ret_t retVal; + + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_FLOWCTRL_PORT_OFF, RTL8367C_FLOWCTRL_PORT_OFF_MASK, pOffThreshold); + + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_FLOWCTRL_PORT_ON, RTL8367C_FLOWCTRL_PORT_ON_MASK, pOnThreshold); + + return retVal; +} +/* Function Name: + * rtl8367c_setAsicFlowControlPortPrivateThreshold + * Description: + * Set Port-private-based flow control parameters + * Input: + * onThreshold - Flow control turn ON threshold + * offThreshold - Flow control turn OFF threshold + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - input parameter out of range + * Note: + * None + */ +ret_t rtl8367c_setAsicFlowControlPortPrivateThreshold(rtk_uint32 onThreshold, rtk_uint32 offThreshold) +{ + ret_t retVal; + + if((onThreshold >= RTK_MAX_BUF_PAGE_NUM) || (offThreshold >= RTK_MAX_BUF_PAGE_NUM)) + return RT_ERR_OUT_OF_RANGE; + + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_FLOWCTRL_PORT_PRIVATE_OFF, RTL8367C_FLOWCTRL_PORT_PRIVATE_OFF_MASK, offThreshold); + + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_FLOWCTRL_PORT_PRIVATE_ON, RTL8367C_FLOWCTRL_PORT_PRIVATE_ON_MASK, onThreshold); + + return retVal; +} +/* Function Name: + * rtl8367c_getAsicFlowControlPortPrivateThreshold + * Description: + * Get Port-private-based flow control parameters + * Input: + * pOnThreshold - Flow control turn ON threshold + * pOffThreshold - Flow control turn OFF threshold + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicFlowControlPortPrivateThreshold(rtk_uint32 *pOnThreshold, rtk_uint32 *pOffThreshold) +{ + ret_t retVal; + + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_FLOWCTRL_PORT_PRIVATE_OFF, RTL8367C_FLOWCTRL_PORT_PRIVATE_OFF_MASK, pOffThreshold); + + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_FLOWCTRL_PORT_PRIVATE_ON, RTL8367C_FLOWCTRL_PORT_PRIVATE_ON_MASK, pOnThreshold); + + return retVal; +} +/* Function Name: + * rtl8367c_setAsicFlowControlSystemDropThreshold + * Description: + * Set system-based drop parameters + * Input: + * onThreshold - Drop turn ON threshold + * offThreshold - Drop turn OFF threshold + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - input parameter out of range + * Note: + * None + */ +ret_t rtl8367c_setAsicFlowControlSystemDropThreshold(rtk_uint32 onThreshold, rtk_uint32 offThreshold) +{ + ret_t retVal; + + if((onThreshold >= RTK_MAX_BUF_PAGE_NUM) || (offThreshold >= RTK_MAX_BUF_PAGE_NUM)) + return RT_ERR_OUT_OF_RANGE; + + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_FLOWCTRL_FCOFF_SYS_OFF, RTL8367C_FLOWCTRL_FCOFF_SYS_OFF_MASK, offThreshold); + + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_FLOWCTRL_FCOFF_SYS_ON, RTL8367C_FLOWCTRL_FCOFF_SYS_ON_MASK, onThreshold); + + return retVal; +} +/* Function Name: + * rtl8367c_getAsicFlowControlSystemDropThreshold + * Description: + * Get system-based drop parameters + * Input: + * pOnThreshold - Drop turn ON threshold + * pOffThreshold - Drop turn OFF threshold + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicFlowControlSystemDropThreshold(rtk_uint32 *pOnThreshold, rtk_uint32 *pOffThreshold) +{ + ret_t retVal; + + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_FLOWCTRL_FCOFF_SYS_OFF, RTL8367C_FLOWCTRL_FCOFF_SYS_OFF_MASK, pOffThreshold); + + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_FLOWCTRL_FCOFF_SYS_ON, RTL8367C_FLOWCTRL_FCOFF_SYS_ON_MASK, pOnThreshold); + + return retVal; +} +/* Function Name: + * rtl8367c_setAsicFlowControlSharedDropThreshold + * Description: + * Set share-based fdrop parameters + * Input: + * onThreshold - Drop turn ON threshold + * offThreshold - Drop turn OFF threshold + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - input parameter out of range + * Note: + * None + */ +ret_t rtl8367c_setAsicFlowControlSharedDropThreshold(rtk_uint32 onThreshold, rtk_uint32 offThreshold) +{ + ret_t retVal; + + if((onThreshold >= RTK_MAX_BUF_PAGE_NUM) || (offThreshold >= RTK_MAX_BUF_PAGE_NUM)) + return RT_ERR_OUT_OF_RANGE; + + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_FLOWCTRL_FCOFF_SHARE_OFF, RTL8367C_FLOWCTRL_FCOFF_SHARE_OFF_MASK, offThreshold); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_FLOWCTRL_FCOFF_SHARE_ON, RTL8367C_FLOWCTRL_FCOFF_SHARE_ON_MASK, onThreshold); + + return retVal; +} +/* Function Name: + * rtl8367c_getAsicFlowControlSharedDropThreshold + * Description: + * Get share-based fdrop parameters + * Input: + * pOnThreshold - Drop turn ON threshold + * pOffThreshold - Drop turn OFF threshold + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicFlowControlSharedDropThreshold(rtk_uint32 *pOnThreshold, rtk_uint32 *pOffThreshold) +{ + ret_t retVal; + + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_FLOWCTRL_FCOFF_SHARE_OFF, RTL8367C_FLOWCTRL_FCOFF_SHARE_OFF_MASK, pOffThreshold); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_FLOWCTRL_FCOFF_SHARE_ON, RTL8367C_FLOWCTRL_FCOFF_SHARE_ON_MASK, pOnThreshold); + + return retVal; +} +/* Function Name: + * rtl8367c_setAsicFlowControlPortDropThreshold + * Description: + * Set Port-based drop parameters + * Input: + * onThreshold - Drop turn ON threshold + * offThreshold - Drop turn OFF threshold + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - input parameter out of range + * Note: + * None + */ +ret_t rtl8367c_setAsicFlowControlPortDropThreshold(rtk_uint32 onThreshold, rtk_uint32 offThreshold) +{ + ret_t retVal; + + if((onThreshold >= RTK_MAX_BUF_PAGE_NUM) || (offThreshold >= RTK_MAX_BUF_PAGE_NUM)) + return RT_ERR_OUT_OF_RANGE; + + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_FLOWCTRL_FCOFF_PORT_OFF, RTL8367C_FLOWCTRL_FCOFF_PORT_OFF_MASK, offThreshold); + + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_FLOWCTRL_FCOFF_PORT_ON, RTL8367C_FLOWCTRL_FCOFF_PORT_ON_MASK, onThreshold); + + return retVal; +} +/* Function Name: + * rtl8367c_getAsicFlowControlPortDropThreshold + * Description: + * Get Port-based drop parameters + * Input: + * pOnThreshold - Drop turn ON threshold + * pOffThreshold - Drop turn OFF threshold + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicFlowControlPortDropThreshold(rtk_uint32 *pOnThreshold, rtk_uint32 *pOffThreshold) +{ + ret_t retVal; + + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_FLOWCTRL_FCOFF_PORT_OFF, RTL8367C_FLOWCTRL_FCOFF_PORT_OFF_MASK, pOffThreshold); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_FLOWCTRL_FCOFF_PORT_ON, RTL8367C_FLOWCTRL_FCOFF_PORT_ON_MASK, pOnThreshold); + + return retVal; +} +/* Function Name: + * rtl8367c_setAsicFlowControlPortPrivateDropThreshold + * Description: + * Set Port-private-based drop parameters + * Input: + * onThreshold - Drop turn ON threshold + * offThreshold - Drop turn OFF threshold + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - input parameter out of range + * Note: + * None + */ +ret_t rtl8367c_setAsicFlowControlPortPrivateDropThreshold(rtk_uint32 onThreshold, rtk_uint32 offThreshold) +{ + ret_t retVal; + + if((onThreshold >= RTK_MAX_BUF_PAGE_NUM) || (offThreshold >= RTK_MAX_BUF_PAGE_NUM)) + return RT_ERR_OUT_OF_RANGE; + + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_FLOWCTRL_FCOFF_PORT_PRIVATE_OFF, RTL8367C_FLOWCTRL_FCOFF_PORT_PRIVATE_OFF_MASK, offThreshold); + + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_FLOWCTRL_FCOFF_PORT_PRIVATE_ON, RTL8367C_FLOWCTRL_FCOFF_PORT_PRIVATE_ON_MASK, onThreshold); + + return retVal; +} +/* Function Name: + * rtl8367c_getAsicFlowControlPortPrivateDropThreshold + * Description: + * Get Port-private-based drop parameters + * Input: + * pOnThreshold - Drop turn ON threshold + * pOffThreshold - Drop turn OFF threshold + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicFlowControlPortPrivateDropThreshold(rtk_uint32 *pOnThreshold, rtk_uint32 *pOffThreshold) +{ + ret_t retVal; + + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_FLOWCTRL_FCOFF_PORT_PRIVATE_OFF, RTL8367C_FLOWCTRL_FCOFF_PORT_PRIVATE_OFF_MASK, pOffThreshold); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_FLOWCTRL_FCOFF_PORT_PRIVATE_ON, RTL8367C_FLOWCTRL_FCOFF_PORT_PRIVATE_ON_MASK, pOnThreshold); + + return retVal; +} +/* Function Name: + * rtl8367c_setAsicFlowControlSystemJumboThreshold + * Description: + * Set Jumbo system-based flow control parameters + * Input: + * onThreshold - Flow control turn ON threshold + * offThreshold - Flow control turn OFF threshold + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - input parameter out of range + * Note: + * None + */ +ret_t rtl8367c_setAsicFlowControlSystemJumboThreshold(rtk_uint32 onThreshold, rtk_uint32 offThreshold) +{ + ret_t retVal; + + if((onThreshold >= RTK_MAX_BUF_PAGE_NUM) || (offThreshold >= RTK_MAX_BUF_PAGE_NUM)) + return RT_ERR_OUT_OF_RANGE; + + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_FLOWCTRL_JUMBO_SYS_OFF, RTL8367C_FLOWCTRL_JUMBO_SYS_OFF_MASK, offThreshold); + + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_FLOWCTRL_JUMBO_SYS_ON, RTL8367C_FLOWCTRL_JUMBO_SYS_ON_MASK, onThreshold); + + return retVal; +} +/* Function Name: + * rtl8367c_getAsicFlowControlSystemJumboThreshold + * Description: + * Get Jumbo system-based flow control parameters + * Input: + * pOnThreshold - Flow control turn ON threshold + * pOffThreshold - Flow control turn OFF threshold + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicFlowControlSystemJumboThreshold(rtk_uint32 *pOnThreshold, rtk_uint32 *pOffThreshold) +{ + ret_t retVal; + + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_FLOWCTRL_JUMBO_SYS_OFF, RTL8367C_FLOWCTRL_JUMBO_SYS_OFF_MASK, pOffThreshold); + + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_FLOWCTRL_JUMBO_SYS_ON, RTL8367C_FLOWCTRL_JUMBO_SYS_ON_MASK, pOnThreshold); + + return retVal; +} +/* Function Name: + * rtl8367c_setAsicFlowControlSharedJumboThreshold + * Description: + * Set Jumbo share-based flow control parameters + * Input: + * onThreshold - Flow control turn ON threshold + * offThreshold - Flow control turn OFF threshold + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - input parameter out of range + * Note: + * None + */ +ret_t rtl8367c_setAsicFlowControlSharedJumboThreshold(rtk_uint32 onThreshold, rtk_uint32 offThreshold) +{ + ret_t retVal; + + if((onThreshold >= RTK_MAX_BUF_PAGE_NUM) || (offThreshold >= RTK_MAX_BUF_PAGE_NUM)) + return RT_ERR_OUT_OF_RANGE; + + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_FLOWCTRL_JUMBO_SHARE_OFF, RTL8367C_FLOWCTRL_JUMBO_SHARE_OFF_MASK, offThreshold); + + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_FLOWCTRL_JUMBO_SHARE_ON, RTL8367C_FLOWCTRL_JUMBO_SHARE_ON_MASK, onThreshold); + + return retVal; +} +/* Function Name: + * rtl8367c_getAsicFlowControlSharedJumboThreshold + * Description: + * Get Jumbo share-based flow control parameters + * Input: + * pOnThreshold - Flow control turn ON threshold + * pOffThreshold - Flow control turn OFF threshold + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicFlowControlSharedJumboThreshold(rtk_uint32 *pOnThreshold, rtk_uint32 *pOffThreshold) +{ + ret_t retVal; + + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_FLOWCTRL_JUMBO_SHARE_OFF, RTL8367C_FLOWCTRL_JUMBO_SHARE_OFF_MASK, pOffThreshold); + + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_FLOWCTRL_JUMBO_SHARE_ON, RTL8367C_FLOWCTRL_JUMBO_SHARE_ON_MASK, pOnThreshold); + + return retVal; +} +/* Function Name: + * rtl8367c_setAsicFlowControlPortJumboThreshold + * Description: + * Set Jumbo Port-based flow control parameters + * Input: + * onThreshold - Flow control turn ON threshold + * offThreshold - Flow control turn OFF threshold + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - input parameter out of range + * Note: + * None + */ +ret_t rtl8367c_setAsicFlowControlPortJumboThreshold(rtk_uint32 onThreshold, rtk_uint32 offThreshold) +{ + ret_t retVal; + + if((onThreshold >= RTK_MAX_BUF_PAGE_NUM) || (offThreshold >= RTK_MAX_BUF_PAGE_NUM)) + return RT_ERR_OUT_OF_RANGE; + + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_FLOWCTRL_JUMBO_PORT_OFF, RTL8367C_FLOWCTRL_JUMBO_PORT_OFF_MASK, offThreshold); + + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_FLOWCTRL_JUMBO_PORT_ON, RTL8367C_FLOWCTRL_JUMBO_PORT_ON_MASK, onThreshold); + + return retVal; +} +/* Function Name: + * rtl8367c_getAsicFlowControlPortJumboThreshold + * Description: + * Get Jumbo Port-based flow control parameters + * Input: + * pOnThreshold - Flow control turn ON threshold + * pOffThreshold - Flow control turn OFF threshold + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicFlowControlPortJumboThreshold(rtk_uint32 *pOnThreshold, rtk_uint32 *pOffThreshold) +{ + ret_t retVal; + + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_FLOWCTRL_JUMBO_PORT_OFF, RTL8367C_FLOWCTRL_JUMBO_PORT_OFF_MASK, pOffThreshold); + + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_FLOWCTRL_JUMBO_PORT_ON, RTL8367C_FLOWCTRL_JUMBO_PORT_ON_MASK, pOnThreshold); + + return retVal; +} +/* Function Name: + * rtl8367c_setAsicFlowControlPortPrivateJumboThreshold + * Description: + * Set Jumbo Port-private-based flow control parameters + * Input: + * onThreshold - Flow control turn ON threshold + * offThreshold - Flow control turn OFF threshold + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - input parameter out of range + * Note: + * None + */ +ret_t rtl8367c_setAsicFlowControlPortPrivateJumboThreshold(rtk_uint32 onThreshold, rtk_uint32 offThreshold) +{ + ret_t retVal; + + if((onThreshold >= RTK_MAX_BUF_PAGE_NUM) || (offThreshold >= RTK_MAX_BUF_PAGE_NUM)) + return RT_ERR_OUT_OF_RANGE; + + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_FLOWCTRL_JUMBO_PORT_PRIVATE_OFF, RTL8367C_FLOWCTRL_JUMBO_PORT_PRIVATE_OFF_MASK, offThreshold); + + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_FLOWCTRL_JUMBO_PORT_PRIVATE_ON, RTL8367C_FLOWCTRL_JUMBO_PORT_PRIVATE_ON_MASK, onThreshold); + + return retVal; +} +/* Function Name: + * rtl8367c_getAsicFlowControlPortPrivateJumboThreshold + * Description: + * Get Jumbo Port-private-based flow control parameters + * Input: + * pOnThreshold - Flow control turn ON threshold + * pOffThreshold - Flow control turn OFF threshold + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicFlowControlPortPrivateJumboThreshold(rtk_uint32 *pOnThreshold, rtk_uint32 *pOffThreshold) +{ + ret_t retVal; + + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_FLOWCTRL_JUMBO_PORT_PRIVATE_OFF, RTL8367C_FLOWCTRL_JUMBO_PORT_PRIVATE_OFF_MASK, pOffThreshold); + + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_FLOWCTRL_JUMBO_PORT_PRIVATE_ON, RTL8367C_FLOWCTRL_JUMBO_PORT_PRIVATE_ON_MASK, pOnThreshold); + + return retVal; +} + + + +/* Function Name: + * rtl8367c_setAsicEgressFlowControlQueueDropThreshold + * Description: + * Set Queue-based egress flow control turn on or ingress flow control drop on threshold + * Input: + * qid - The queue id + * threshold - Queue-based flown control/drop turn ON threshold + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - input parameter out of range + * RT_ERR_QUEUE_ID - Invalid queue id + * Note: + * None + */ +ret_t rtl8367c_setAsicEgressFlowControlQueueDropThreshold(rtk_uint32 qid, rtk_uint32 threshold) +{ + if( threshold >= RTK_MAX_BUF_PAGE_NUM) + return RT_ERR_OUT_OF_RANGE; + + if(qid > RTL8367C_QIDMAX) + return RT_ERR_QUEUE_ID; + + return rtl8367c_setAsicRegBits(RTL8367C_FLOWCTRL_QUEUE_DROP_ON_REG(qid), RTL8367C_FLOWCTRL_QUEUE_DROP_ON_MASK, threshold); +} +/* Function Name: + * rtl8367c_getAsicEgressFlowControlQueueDropThreshold + * Description: + * Get Queue-based egress flow control turn on or ingress flow control drop on threshold + * Input: + * qid - The queue id + * pThreshold - Queue-based flown control/drop turn ON threshold + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_ID - Invalid queue id + * Note: + * None + */ +ret_t rtl8367c_getAsicEgressFlowControlQueueDropThreshold(rtk_uint32 qid, rtk_uint32 *pThreshold) +{ + if(qid > RTL8367C_QIDMAX) + return RT_ERR_QUEUE_ID; + + return rtl8367c_getAsicRegBits(RTL8367C_FLOWCTRL_QUEUE_DROP_ON_REG(qid), RTL8367C_FLOWCTRL_QUEUE_DROP_ON_MASK, pThreshold); +} +/* Function Name: + * rtl8367c_setAsicEgressFlowControlPortDropThreshold + * Description: + * Set port-based egress flow control turn on or ingress flow control drop on threshold + * Input: + * port - Physical port number (0~7) + * threshold - Queue-based flown control/drop turn ON threshold + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * RT_ERR_OUT_OF_RANGE - input parameter out of range + * Note: + * None + */ +ret_t rtl8367c_setAsicEgressFlowControlPortDropThreshold(rtk_uint32 port, rtk_uint32 threshold) +{ + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + if(threshold >= RTK_MAX_BUF_PAGE_NUM) + return RT_ERR_OUT_OF_RANGE; + + return rtl8367c_setAsicRegBits(RTL8367C_FLOWCTRL_PORT_DROP_ON_REG(port), RTL8367C_FLOWCTRL_PORT_DROP_ON_MASK, threshold); +} +/* Function Name: + * rtl8367c_setAsicEgressFlowControlPortDropThreshold + * Description: + * Set port-based egress flow control turn on or ingress flow control drop on threshold + * Input: + * port - Physical port number (0~7) + * pThreshold - Queue-based flown control/drop turn ON threshold + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_getAsicEgressFlowControlPortDropThreshold(rtk_uint32 port, rtk_uint32 *pThreshold) +{ + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + return rtl8367c_getAsicRegBits(RTL8367C_FLOWCTRL_PORT_DROP_ON_REG(port), RTL8367C_FLOWCTRL_PORT_DROP_ON_MASK, pThreshold); +} +/* Function Name: + * rtl8367c_setAsicEgressFlowControlPortDropGap + * Description: + * Set port-based egress flow control turn off or ingress flow control drop off gap + * Input: + * gap - Flow control/drop turn OFF threshold = turn ON threshold - gap + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - input parameter out of range + * Note: + * None + */ +ret_t rtl8367c_setAsicEgressFlowControlPortDropGap(rtk_uint32 gap) +{ + if(gap >= RTK_MAX_BUF_PAGE_NUM) + return RT_ERR_OUT_OF_RANGE; + + return rtl8367c_setAsicRegBits(RTL8367C_REG_FLOWCTRL_PORT_GAP, RTL8367C_FLOWCTRL_PORT_GAP_MASK, gap); +} +/* Function Name: + * rtl8367c_getAsicEgressFlowControlPortDropGap + * Description: + * Get port-based egress flow control turn off or ingress flow control drop off gap + * Input: + * pGap - Flow control/drop turn OFF threshold = turn ON threshold - gap + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicEgressFlowControlPortDropGap(rtk_uint32 *pGap) +{ + return rtl8367c_getAsicRegBits(RTL8367C_REG_FLOWCTRL_PORT_GAP, RTL8367C_FLOWCTRL_PORT_GAP_MASK, pGap); +} +/* Function Name: + * rtl8367c_setAsicEgressFlowControlQueueDropGap + * Description: + * Set Queue-based egress flow control turn off or ingress flow control drop off gap + * Input: + * gap - Flow control/drop turn OFF threshold = turn ON threshold - gap + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - input parameter out of range + * Note: + * None + */ +ret_t rtl8367c_setAsicEgressFlowControlQueueDropGap(rtk_uint32 gap) +{ + if(gap >= RTK_MAX_BUF_PAGE_NUM) + return RT_ERR_OUT_OF_RANGE; + + return rtl8367c_setAsicRegBits(RTL8367C_REG_FLOWCTRL_QUEUE_GAP, RTL8367C_FLOWCTRL_QUEUE_GAP_MASK, gap); +} +/* Function Name: + * rtl8367c_getAsicEgressFlowControlQueueDropGap + * Description: + * Get Queue-based egress flow control turn off or ingress flow control drop off gap + * Input: + * pGap - Flow control/drop turn OFF threshold = turn ON threshold - gap + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicEgressFlowControlQueueDropGap(rtk_uint32 *pGap) +{ + return rtl8367c_getAsicRegBits(RTL8367C_REG_FLOWCTRL_QUEUE_GAP, RTL8367C_FLOWCTRL_QUEUE_GAP_MASK, pGap); +} +/* Function Name: + * rtl8367c_getAsicEgressQueueEmptyPortMask + * Description: + * Get queue empty port mask + * Input: + * pPortmask - Queue empty port mask + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicEgressQueueEmptyPortMask(rtk_uint32 *pPortmask) +{ + return rtl8367c_getAsicReg(RTL8367C_REG_PORT_QEMPTY, pPortmask); +} +/* Function Name: + * rtl8367c_getAsicTotalPage + * Description: + * Get system total page usage number + * Input: + * pPageCount - page usage number + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicTotalPage(rtk_uint32 *pPageCount) +{ + return rtl8367c_getAsicRegBits(RTL8367C_REG_FLOWCTRL_TOTAL_PAGE_COUNTER, RTL8367C_FLOWCTRL_TOTAL_PAGE_COUNTER_MASK, pPageCount); +} +/* Function Name: + * rtl8367c_getAsicPulbicPage + * Description: + * Get system public page usage number + * Input: + * pPageCount - page usage number + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicPulbicPage(rtk_uint32 *pPageCount) +{ + return rtl8367c_getAsicRegBits(RTL8367C_REG_FLOWCTRL_PUBLIC_PAGE_COUNTER, RTL8367C_FLOWCTRL_PUBLIC_PAGE_COUNTER_MASK, pPageCount); +} +/* Function Name: + * rtl8367c_getAsicMaxTotalPage + * Description: + * Get system total page max usage number + * Input: + * pPageCount - page usage number + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicMaxTotalPage(rtk_uint32 *pPageCount) +{ + return rtl8367c_getAsicRegBits(RTL8367C_REG_FLOWCTRL_TOTAL_PAGE_MAX, RTL8367C_FLOWCTRL_TOTAL_PAGE_MAX_MASK, pPageCount); +} +/* Function Name: + * rtl8367c_getAsicPulbicPage + * Description: + * Get system public page max usage number + * Input: + * pPageCount - page usage number + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicMaxPulbicPage(rtk_uint32 *pPageCount) +{ + return rtl8367c_getAsicRegBits(RTL8367C_REG_FLOWCTRL_PUBLIC_PAGE_MAX, RTL8367C_FLOWCTRL_PUBLIC_PAGE_MAX_MASK, pPageCount); +} +/* Function Name: + * rtl8367c_getAsicPortPage + * Description: + * Get per-port page usage number + * Input: + * port - Physical port number (0~7) + * pPageCount - page usage number + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_getAsicPortPage(rtk_uint32 port, rtk_uint32 *pPageCount) +{ + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + if(port < 8) + return rtl8367c_getAsicRegBits(RTL8367C_FLOWCTRL_PORT_PAGE_COUNTER_REG(port), RTL8367C_FLOWCTRL_PORT_PAGE_COUNTER_MASK, pPageCount); + else + return rtl8367c_getAsicRegBits(RTL8367C_REG_FLOWCTRL_PORT8_PAGE_COUNTER+port - 8, RTL8367C_FLOWCTRL_PORT_PAGE_COUNTER_MASK, pPageCount); +} +/* Function Name: + * rtl8367c_getAsicPortPage + * Description: + * Get per-port page max usage number + * Input: + * port - Physical port number (0~7) + * pPageCount - page usage number + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_getAsicPortPageMax(rtk_uint32 port, rtk_uint32 *pPageCount) +{ + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + if(port < 8) + return rtl8367c_getAsicRegBits(RTL8367C_FLOWCTRL_PORT_PAGE_MAX_REG(port), RTL8367C_FLOWCTRL_PORT_PAGE_MAX_MASK, pPageCount); + else + return rtl8367c_getAsicRegBits(RTL8367C_REG_FLOWCTRL_PORT0_PAGE_MAX+port-8, RTL8367C_FLOWCTRL_PORT_PAGE_MAX_MASK, pPageCount); + + +} + +/* Function Name: + * rtl8367c_setAsicFlowControlEgressPortIndep + * Description: + * Set per-port egress flow control independent + * Input: + * port - Physical port number (0~7) + * enabled - Egress port flow control usage 1:enable 0:disable. + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_setAsicFlowControlEgressPortIndep(rtk_uint32 port, rtk_uint32 enable) +{ + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + return rtl8367c_setAsicRegBit(RTL8367C_REG_PORT0_MISC_CFG + (port *0x20), RTL8367C_PORT0_MISC_CFG_FLOWCTRL_INDEP_OFFSET,enable); +} + +/* Function Name: + * rtl8367c_getAsicFlowControlEgressPortIndep + * Description: + * Get per-port egress flow control independent + * Input: + * port - Physical port number (0~7) + * enabled - Egress port flow control usage 1:enable 0:disable. + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_getAsicFlowControlEgressPortIndep(rtk_uint32 port, rtk_uint32 *pEnable) +{ + return rtl8367c_getAsicRegBit(RTL8367C_REG_PORT0_MISC_CFG + (port *0x20),RTL8367C_PORT0_MISC_CFG_FLOWCTRL_INDEP_OFFSET,pEnable); +} diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_fc.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_fc.h new file mode 100644 index 00000000..d3a7be1d --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_fc.h @@ -0,0 +1,81 @@ +#ifndef _RTL8367C_ASICDRV_FC_H_ +#define _RTL8367C_ASICDRV_FC_H_ + +#include +#include + + +enum FLOW_CONTROL_TYPE +{ + FC_EGRESS = 0, + FC_INGRESS, +}; + +enum FC_JUMBO_SIZE +{ + FC_JUMBO_SIZE_3K = 0, + FC_JUMBO_SIZE_4K, + FC_JUMBO_SIZE_6K, + FC_JUMBO_SIZE_9K, + FC_JUMBO_SIZE_END, + +}; + + +extern ret_t rtl8367c_setAsicFlowControlSelect(rtk_uint32 select); +extern ret_t rtl8367c_getAsicFlowControlSelect(rtk_uint32 *pSelect); +extern ret_t rtl8367c_setAsicFlowControlJumboMode(rtk_uint32 enabled); +extern ret_t rtl8367c_getAsicFlowControlJumboMode(rtk_uint32* pEnabled); +extern ret_t rtl8367c_setAsicFlowControlJumboModeSize(rtk_uint32 size); +extern ret_t rtl8367c_getAsicFlowControlJumboModeSize(rtk_uint32* pSize); +extern ret_t rtl8367c_setAsicFlowControlQueueEgressEnable(rtk_uint32 port, rtk_uint32 qid, rtk_uint32 enabled); +extern ret_t rtl8367c_getAsicFlowControlQueueEgressEnable(rtk_uint32 port, rtk_uint32 qid, rtk_uint32* pEnabled); +extern ret_t rtl8367c_setAsicFlowControlDropAll(rtk_uint32 dropall); +extern ret_t rtl8367c_getAsicFlowControlDropAll(rtk_uint32* pDropall); +extern ret_t rtl8367c_setAsicFlowControlPauseAllThreshold(rtk_uint32 threshold); +extern ret_t rtl8367c_getAsicFlowControlPauseAllThreshold(rtk_uint32 *pThreshold); +extern ret_t rtl8367c_setAsicFlowControlSystemThreshold(rtk_uint32 onThreshold, rtk_uint32 offThreshold); +extern ret_t rtl8367c_getAsicFlowControlSystemThreshold(rtk_uint32 *pOnThreshold, rtk_uint32 *pOffThreshold); +extern ret_t rtl8367c_setAsicFlowControlSharedThreshold(rtk_uint32 onThreshold, rtk_uint32 offThreshold); +extern ret_t rtl8367c_getAsicFlowControlSharedThreshold(rtk_uint32 *pOnThreshold, rtk_uint32 *pOffThreshold); +extern ret_t rtl8367c_setAsicFlowControlPortThreshold(rtk_uint32 onThreshold, rtk_uint32 offThreshold); +extern ret_t rtl8367c_getAsicFlowControlPortThreshold(rtk_uint32 *pOnThreshold, rtk_uint32 *pOffThreshold); +extern ret_t rtl8367c_setAsicFlowControlPortPrivateThreshold(rtk_uint32 onThreshold, rtk_uint32 offThreshold); +extern ret_t rtl8367c_getAsicFlowControlPortPrivateThreshold(rtk_uint32 *pOnThreshold, rtk_uint32 *pOffThreshold); +extern ret_t rtl8367c_setAsicFlowControlSystemDropThreshold(rtk_uint32 onThreshold, rtk_uint32 offThreshold); +extern ret_t rtl8367c_getAsicFlowControlSystemDropThreshold(rtk_uint32 *pOnThreshold, rtk_uint32 *pOffThreshold); +extern ret_t rtl8367c_setAsicFlowControlSharedDropThreshold(rtk_uint32 onThreshold, rtk_uint32 offThreshold); +extern ret_t rtl8367c_getAsicFlowControlSharedDropThreshold(rtk_uint32 *pOnThreshold, rtk_uint32 *pOffThreshold); +extern ret_t rtl8367c_setAsicFlowControlPortDropThreshold(rtk_uint32 onThreshold, rtk_uint32 offThreshold); +extern ret_t rtl8367c_getAsicFlowControlPortDropThreshold(rtk_uint32 *pOnThreshold, rtk_uint32 *pOffThreshold); +extern ret_t rtl8367c_setAsicFlowControlPortPrivateDropThreshold(rtk_uint32 onThreshold, rtk_uint32 offThreshold); +extern ret_t rtl8367c_getAsicFlowControlPortPrivateDropThreshold(rtk_uint32 *pOnThreshold, rtk_uint32 *pOffThreshold); +extern ret_t rtl8367c_setAsicFlowControlSystemJumboThreshold(rtk_uint32 onThreshold, rtk_uint32 offThreshold); +extern ret_t rtl8367c_getAsicFlowControlSystemJumboThreshold(rtk_uint32 *pOnThreshold, rtk_uint32 *pOffThreshold); +extern ret_t rtl8367c_setAsicFlowControlSharedJumboThreshold(rtk_uint32 onThreshold, rtk_uint32 offThreshold); +extern ret_t rtl8367c_getAsicFlowControlSharedJumboThreshold(rtk_uint32 *pOnThreshold, rtk_uint32 *pOffThreshold); +extern ret_t rtl8367c_setAsicFlowControlPortJumboThreshold(rtk_uint32 onThreshold, rtk_uint32 offThreshold); +extern ret_t rtl8367c_getAsicFlowControlPortJumboThreshold(rtk_uint32 *pOnThreshold, rtk_uint32 *pOffThreshold); +extern ret_t rtl8367c_setAsicFlowControlPortPrivateJumboThreshold(rtk_uint32 onThreshold, rtk_uint32 offThreshold); +extern ret_t rtl8367c_getAsicFlowControlPortPrivateJumboThreshold(rtk_uint32 *pOnThreshold, rtk_uint32 *pOffThreshold); + +extern ret_t rtl8367c_setAsicEgressFlowControlPortDropGap(rtk_uint32 gap); +extern ret_t rtl8367c_getAsicEgressFlowControlPortDropGap(rtk_uint32 *pGap); +extern ret_t rtl8367c_setAsicEgressFlowControlQueueDropGap(rtk_uint32 gap); +extern ret_t rtl8367c_getAsicEgressFlowControlQueueDropGap(rtk_uint32 *pGap); +extern ret_t rtl8367c_setAsicEgressFlowControlPortDropThreshold(rtk_uint32 port, rtk_uint32 threshold); +extern ret_t rtl8367c_getAsicEgressFlowControlPortDropThreshold(rtk_uint32 port, rtk_uint32 *pThreshold); +extern ret_t rtl8367c_setAsicEgressFlowControlQueueDropThreshold(rtk_uint32 qid, rtk_uint32 threshold); +extern ret_t rtl8367c_getAsicEgressFlowControlQueueDropThreshold(rtk_uint32 qid, rtk_uint32 *pThreshold); +extern ret_t rtl8367c_getAsicEgressQueueEmptyPortMask(rtk_uint32 *pPortmask); +extern ret_t rtl8367c_getAsicTotalPage(rtk_uint32 *pPageCount); +extern ret_t rtl8367c_getAsicPulbicPage(rtk_uint32 *pPageCount); +extern ret_t rtl8367c_getAsicMaxTotalPage(rtk_uint32 *pPageCount); +extern ret_t rtl8367c_getAsicMaxPulbicPage(rtk_uint32 *pPageCount); +extern ret_t rtl8367c_getAsicPortPage(rtk_uint32 port, rtk_uint32 *pPageCount); +extern ret_t rtl8367c_getAsicPortPageMax(rtk_uint32 port, rtk_uint32 *pPageCount); +extern ret_t rtl8367c_setAsicFlowControlEgressPortIndep(rtk_uint32 port, rtk_uint32 enable); +extern ret_t rtl8367c_getAsicFlowControlEgressPortIndep(rtk_uint32 port, rtk_uint32 *pEnable); + +#endif /*_RTL8367C_ASICDRV_FC_H_*/ + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_green.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_green.c new file mode 100644 index 00000000..a6f17a23 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_green.c @@ -0,0 +1,625 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTL8367C switch high-level API for RTL8367C + * Feature : Green ethernet related functions + * + */ +#include + +/* Function Name: + * rtl8367c_getAsicGreenPortPage + * Description: + * Get per-Port ingress page usage per second + * Input: + * port - Physical port number (0~7) + * pPage - page number of ingress packet occuping per second + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * Ingress traffic occuping page number per second for high layer green feature usage + */ +ret_t rtl8367c_getAsicGreenPortPage(rtk_uint32 port, rtk_uint32* pPage) +{ + ret_t retVal; + rtk_uint32 regData; + rtk_uint32 pageMeter; + + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + retVal = rtl8367c_getAsicReg(RTL8367C_PAGEMETER_PORT_REG(port), ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + pageMeter = regData; + + retVal = rtl8367c_getAsicReg(RTL8367C_PAGEMETER_PORT_REG(port) + 1, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + pageMeter = pageMeter + (regData << 16); + + *pPage = pageMeter; + return RT_ERR_OK; +} +/* Function Name: + * rtl8367c_setAsicGreenTrafficType + * Description: + * Set traffic type for each priority + * Input: + * priority - internal priority (0~7) + * traffictype - high/low traffic type, 1:high priority traffic type, 0:low priority traffic type + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_INT_PRIORITY - Invalid priority + * Note: + * None + */ +ret_t rtl8367c_setAsicGreenTrafficType(rtk_uint32 priority, rtk_uint32 traffictype) +{ + + if(priority > RTL8367C_PRIMAX) + return RT_ERR_QOS_INT_PRIORITY; + + return rtl8367c_setAsicRegBit(RTL8367C_REG_HIGHPRI_CFG, priority, (traffictype?1:0)); +} +/* Function Name: + * rtl8367c_getAsicGreenTrafficType + * Description: + * Get traffic type for each priority + * Input: + * priority - internal priority (0~7) + * pTraffictype - high/low traffic type, 1:high priority traffic type, 0:low priority traffic type + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_INT_PRIORITY - Invalid priority + * Note: + * None + */ +ret_t rtl8367c_getAsicGreenTrafficType(rtk_uint32 priority, rtk_uint32* pTraffictype) +{ + if(priority > RTL8367C_PRIMAX) + return RT_ERR_QOS_INT_PRIORITY; + + return rtl8367c_getAsicRegBit(RTL8367C_REG_HIGHPRI_CFG, priority, pTraffictype); +} + +/* Function Name: + * rtl8367c_setAsicGreenHighPriorityTraffic + * Description: + * Set indicator which ASIC had received high priority traffic + * Input: + * port - Physical port number (0~7) + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_setAsicGreenHighPriorityTraffic(rtk_uint32 port) +{ + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + return rtl8367c_setAsicRegBit(RTL8367C_REG_HIGHPRI_INDICATOR, port, 1); +} + + +/* Function Name: + * rtl8367c_getAsicGreenHighPriorityTraffic + * Description: + * Get indicator which ASIC had received high priority traffic or not + * Input: + * port - Physical port number (0~7) + * pIndicator - Have received high priority traffic indicator. If 1 means ASCI had received high priority in 1second checking priod + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_getAsicGreenHighPriorityTraffic(rtk_uint32 port, rtk_uint32* pIndicator) +{ + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + return rtl8367c_getAsicRegBit(RTL8367C_REG_HIGHPRI_INDICATOR, port, pIndicator); +} + +/* +@func rtk_int32 | rtl8367c_setAsicGreenEthernet | Set green ethernet function. +@parm rtk_uint32 | green | Green feature function usage 1:enable 0:disable. +@rvalue RT_ERR_OK | Success. +@rvalue RT_ERR_SMI | SMI access error. +@comm + The API can set Green Ethernet function to reduce power consumption. While green feature is enabled, ASIC will automatic + detect the cable length and then select different power mode for best performance with minimums power consumption. Link down + ports will enter power savining mode in 10 seconds after the cable disconnected if power saving function is enabled. +*/ +ret_t rtl8367c_setAsicGreenEthernet(rtk_uint32 port, rtk_uint32 green) +{ + ret_t retVal; + rtk_uint32 checkCounter; + rtk_uint32 regData; + rtk_uint32 phy_status; + rtk_uint32 patchData[6][2] = { {0x809A, 0x8911}, {0x80A3, 0x9233}, {0x80AC, 0xA444}, {0x809F, 0x6B20}, {0x80A8, 0x6B22}, {0x80B1, 0x6B23} }; + rtk_uint32 idx; + rtk_uint32 data; + + if (green > 1) + return RT_ERR_INPUT; + + if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0249)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_getAsicReg(0x1300, &data)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0000)) != RT_ERR_OK) + return retVal; + + /* Stop Watchdog */ + switch (data) + { + case 0x0652: + case 0x6368: + case 0x0801: + case 0x6511: + if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xB83E, ®Data)) != RT_ERR_OK) + return retVal; + + regData &= 0xFF00; + regData |= 0x00A9; + if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xB83E, regData)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xB840, ®Data)) != RT_ERR_OK) + return retVal; + + regData &= 0xFF00; + regData |= 0x00A9; + if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xB840, regData)) != RT_ERR_OK) + return retVal; + break; + default: + break;; + } + + /* 0xa420[2:0] */ + if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xA420, ®Data)) != RT_ERR_OK) + return retVal; + phy_status = (regData & 0x0007); + + if(phy_status == 3) + { + /* 0xb820[4] = 1 */ + if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xB820, ®Data)) != RT_ERR_OK) + return retVal; + + regData |= (0x0001 << 4); + + if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xB820, regData)) != RT_ERR_OK) + return retVal; + + /* wait 0xb800[6] = 1 */ + checkCounter = 100; + while(checkCounter) + { + retVal = rtl8367c_getAsicPHYOCPReg(port, 0xB800, ®Data); + if( (retVal != RT_ERR_OK) || ((regData & 0x0040) != 0x0040) ) + { + checkCounter --; + if(0 == checkCounter) + return RT_ERR_BUSYWAIT_TIMEOUT; + } + else + checkCounter = 0; + } + } + + switch (data) + { + case 0x0276: + case 0x0597: + case 0x6367: + if(green) + { + for(idx = 0; idx < 6; idx++ ) + { + if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xA436, patchData[idx][0])) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xA438, patchData[idx][1])) != RT_ERR_OK) + return retVal; + } + } + break; + default: + break;; + } + + + + /* 0xa436 = 0x8011 */ + if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xA436, 0x8011)) != RT_ERR_OK) + return retVal; + + /* wr 0xa438[15] = 0: disable, 1: enable */ + if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xA438, ®Data)) != RT_ERR_OK) + return retVal; + + if(green) + regData |= 0x8000; + else + regData &= 0x7FFF; + + if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xA438, regData)) != RT_ERR_OK) + return retVal; + + if(green == 0) + { + /* Disable Green, write analog parameter as long cable parameter */ + /* 0xBCC2 [14:12] 0x4 + 0xBCC2 [10:8] 0x4 + 0xBCC2 [7:4] 0x4 + 0xBCC2 [3:0] 0x4 */ + if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xBCC2, ®Data)) != RT_ERR_OK) + return retVal; + + regData &= 0x8800; + regData |= 0x4444; + if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xBCC2, regData)) != RT_ERR_OK) + return retVal; + + /* 0xBCCA [9:8] 0x3 + 0xBCCA [7] 0x0 */ + if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xBCCA, ®Data)) != RT_ERR_OK) + return retVal; + + regData &= 0xFF7F; + regData |= 0x0300; + if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xBCCA, regData)) != RT_ERR_OK) + return retVal; + + /* 0xBCC0 [2:0] 0x0 */ + if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xBCC0, ®Data)) != RT_ERR_OK) + return retVal; + + regData &= 0xFFF8; + if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xBCC0, regData)) != RT_ERR_OK) + return retVal; + + /* 0xA80E [11:10] 0x2 */ + if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xA80E, ®Data)) != RT_ERR_OK) + return retVal; + + regData &= 0xF3FF; + regData |= 0x0800; + if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xA80E, regData)) != RT_ERR_OK) + return retVal; + + /* 0xBCD6 [2:0] 0x3 */ + if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xBCD6, ®Data)) != RT_ERR_OK) + return retVal; + + regData &= 0xFFF8; + regData |= 0x0003; + if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xBCD6, regData)) != RT_ERR_OK) + return retVal; + } + + /* Re-nway */ + if((retVal = rtl8367c_getAsicPHYReg(port, 0, ®Data)) != RT_ERR_OK) + return retVal; + + regData |= 0x0200; + if((retVal = rtl8367c_setAsicPHYReg(port, 0, regData)) != RT_ERR_OK) + return retVal; + + if(phy_status == 3) + { + /* 0xb820[4] = 0 */ + if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xB820, ®Data)) != RT_ERR_OK) + return retVal; + + regData &= ~(0x0001 << 4); + + if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xB820, regData)) != RT_ERR_OK) + return retVal; + + /* wait 0xb800[6] = 0 */ + checkCounter = 100; + while(checkCounter) + { + retVal = rtl8367c_getAsicPHYOCPReg(port, 0xB800, ®Data); + if( (retVal != RT_ERR_OK) || ((regData & 0x0040) != 0x0000) ) + { + checkCounter --; + if(0 == checkCounter) + return RT_ERR_BUSYWAIT_TIMEOUT; + } + else + checkCounter = 0; + } + } + + /* Start Watchdog */ + switch (data) + { + case 0x0652: + case 0x6368: + case 0x0801: + case 0x6511: + if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xB83E, ®Data)) != RT_ERR_OK) + return retVal; + + regData &= 0xFF00; + regData |= 0x0048; + if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xB83E, regData)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xB840, ®Data)) != RT_ERR_OK) + return retVal; + + regData &= 0xFF00; + regData |= 0x00FA; + if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xB840, regData)) != RT_ERR_OK) + return retVal; + break; + default: + break;; + } + + return RT_ERR_OK; +} + +/* +@func rtk_int32 | rtl8367c_getAsicGreenEthernet | Get green ethernet function. +@parm rtk_uint32 | *green | Green feature function usage 1:enable 0:disable. +@rvalue RT_ERR_OK | Success. +@rvalue RT_ERR_SMI | SMI access error. +@comm + The API can set Green Ethernet function to reduce power consumption. While green feature is enabled, ASIC will automatic + detect the cable length and then select different power mode for best performance with minimums power consumption. Link down + ports will enter power savining mode in 10 seconds after the cable disconnected if power saving function is enabled. +*/ +ret_t rtl8367c_getAsicGreenEthernet(rtk_uint32 port, rtk_uint32* green) +{ + ret_t retVal; + rtk_uint32 regData; + + /* 0xa436 = 0x8011 */ + if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xA436, 0x8011)) != RT_ERR_OK) + return retVal; + + /* wr 0xa438[15] = 0: disable, 1: enable */ + if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xA438, ®Data)) != RT_ERR_OK) + return retVal; + + if(regData & 0x8000) + *green = ENABLED; + else + *green = DISABLED; + + return RT_ERR_OK; +} + + +/* +@func ret_t | rtl8367c_setAsicPowerSaving | Set power saving mode +@parm rtk_uint32 | phy | phy number +@parm rtk_uint32 | enable | enable power saving mode. +@rvalue RT_ERR_OK | Success. +@rvalue RT_ERR_SMI | SMI access error. +@rvalue RT_ERR_PORT_ID | Invalid port number. +@comm + The API can set power saving mode per phy. +*/ +ret_t rtl8367c_setAsicPowerSaving(rtk_uint32 phy, rtk_uint32 enable) +{ + rtk_api_ret_t retVal; + rtk_uint32 phyData; + rtk_uint32 regData; + rtk_uint32 phy_status; + rtk_uint32 checkCounter; + rtk_uint32 data; + + if (enable > 1) + return RT_ERR_INPUT; + + if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0249)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_getAsicReg(0x1300, &data)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0000)) != RT_ERR_OK) + return retVal; + + /* Stop Watchdog */ + switch (data) + { + case 0x0652: + case 0x6368: + case 0x0801: + case 0x6511: + if((retVal = rtl8367c_getAsicPHYOCPReg(phy, 0xB83E, ®Data)) != RT_ERR_OK) + return retVal; + + regData &= 0xFF00; + regData |= 0x00A9; + if((retVal = rtl8367c_setAsicPHYOCPReg(phy, 0xB83E, regData)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_getAsicPHYOCPReg(phy, 0xB840, ®Data)) != RT_ERR_OK) + return retVal; + + regData &= 0xFF00; + regData |= 0x00A9; + if((retVal = rtl8367c_setAsicPHYOCPReg(phy, 0xB840, regData)) != RT_ERR_OK) + return retVal; + break; + default: + break;; + } + + /* 0xa420[2:0] */ + if((retVal = rtl8367c_getAsicPHYOCPReg(phy, 0xA420, ®Data)) != RT_ERR_OK) + return retVal; + + phy_status = (regData & 0x0007); + + if(phy_status == 3) + { + /* 0xb820[4] = 1 */ + if((retVal = rtl8367c_getAsicPHYOCPReg(phy, 0xB820, ®Data)) != RT_ERR_OK) + return retVal; + + regData |= (0x0001 << 4); + + if((retVal = rtl8367c_setAsicPHYOCPReg(phy, 0xB820, regData)) != RT_ERR_OK) + return retVal; + + /* wait 0xb800[6] = 1 */ + checkCounter = 100; + while(checkCounter) + { + retVal = rtl8367c_getAsicPHYOCPReg(phy, 0xB800, ®Data); + if( (retVal != RT_ERR_OK) || ((regData & 0x0040) != 0x0040) ) + { + checkCounter --; + if(0 == checkCounter) + { + return RT_ERR_BUSYWAIT_TIMEOUT; + } + } + else + checkCounter = 0; + } + } + + if ((retVal = rtl8367c_getAsicPHYReg(phy,PHY_POWERSAVING_REG,&phyData))!=RT_ERR_OK) + return retVal; + + phyData = phyData & ~(0x0001 << 2); + phyData = phyData | (enable << 2); + + if ((retVal = rtl8367c_setAsicPHYReg(phy,PHY_POWERSAVING_REG,phyData))!=RT_ERR_OK) + return retVal; + + if(phy_status == 3) + { + /* 0xb820[4] = 0 */ + if((retVal = rtl8367c_getAsicPHYOCPReg(phy, 0xB820, ®Data)) != RT_ERR_OK) + return retVal; + + regData &= ~(0x0001 << 4); + + if((retVal = rtl8367c_setAsicPHYOCPReg(phy, 0xB820, regData)) != RT_ERR_OK) + return retVal; + + /* wait 0xb800[6] = 0 */ + checkCounter = 100; + while(checkCounter) + { + retVal = rtl8367c_getAsicPHYOCPReg(phy, 0xB800, ®Data); + if( (retVal != RT_ERR_OK) || ((regData & 0x0040) != 0x0000) ) + { + checkCounter --; + if(0 == checkCounter) + { + return RT_ERR_BUSYWAIT_TIMEOUT; + } + } + else + checkCounter = 0; + } + } + + /* Start Watchdog */ + switch (data) + { + case 0x0652: + case 0x6368: + case 0x0801: + case 0x6511: + if((retVal = rtl8367c_getAsicPHYOCPReg(phy, 0xB83E, ®Data)) != RT_ERR_OK) + return retVal; + + regData &= 0xFF00; + regData |= 0x0048; + if((retVal = rtl8367c_setAsicPHYOCPReg(phy, 0xB83E, regData)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_getAsicPHYOCPReg(phy, 0xB840, ®Data)) != RT_ERR_OK) + return retVal; + + regData &= 0xFF00; + regData |= 0x00FA; + if((retVal = rtl8367c_setAsicPHYOCPReg(phy, 0xB840, regData)) != RT_ERR_OK) + return retVal; + break; + default: + break;; + } + + return RT_ERR_OK; +} + +/* +@func ret_t | rtl8367c_getAsicPowerSaving | Get power saving mode +@parm rtk_uint32 | port | The port number +@parm rtk_uint32* | enable | enable power saving mode. +@rvalue RT_ERR_OK | Success. +@rvalue RT_ERR_SMI | SMI access error. +@rvalue RT_ERR_PORT_ID | Invalid port number. +@comm + The API can get power saving mode per phy. +*/ +ret_t rtl8367c_getAsicPowerSaving(rtk_uint32 phy, rtk_uint32* enable) +{ + rtk_api_ret_t retVal; + rtk_uint32 phyData; + + if(NULL == enable) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367c_getAsicPHYReg(phy,PHY_POWERSAVING_REG,&phyData))!=RT_ERR_OK) + return retVal; + + if ((phyData & 0x0004) > 0) + *enable = 1; + else + *enable = 0; + + return RT_ERR_OK; +} + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_green.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_green.h new file mode 100644 index 00000000..c2218b5c --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_green.h @@ -0,0 +1,19 @@ +#ifndef _RTL8367C_ASICDRV_GREEN_H_ +#define _RTL8367C_ASICDRV_GREEN_H_ + +#include +#include + +#define PHY_POWERSAVING_REG 24 + +extern ret_t rtl8367c_setAsicGreenTrafficType(rtk_uint32 priority, rtk_uint32 traffictype); +extern ret_t rtl8367c_getAsicGreenTrafficType(rtk_uint32 priority, rtk_uint32* pTraffictype); +extern ret_t rtl8367c_getAsicGreenPortPage(rtk_uint32 port, rtk_uint32* pPage); +extern ret_t rtl8367c_getAsicGreenHighPriorityTraffic(rtk_uint32 port, rtk_uint32* pIndicator); +extern ret_t rtl8367c_setAsicGreenHighPriorityTraffic(rtk_uint32 port); +extern ret_t rtl8367c_setAsicGreenEthernet(rtk_uint32 port, rtk_uint32 green); +extern ret_t rtl8367c_getAsicGreenEthernet(rtk_uint32 port, rtk_uint32* green); +extern ret_t rtl8367c_setAsicPowerSaving(rtk_uint32 phy, rtk_uint32 enable); +extern ret_t rtl8367c_getAsicPowerSaving(rtk_uint32 phy, rtk_uint32* enable); +#endif /*#ifndef _RTL8367C_ASICDRV_GREEN_H_*/ + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_hsb.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_hsb.c new file mode 100644 index 00000000..258f5268 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_hsb.c @@ -0,0 +1,83 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTL8367C switch high-level API for RTL8367C + * Feature : Field selector related functions + * + */ +#include +/* Function Name: + * rtl8367c_setAsicFieldSelector + * Description: + * Set user defined field selectors in HSB + * Input: + * index - index of field selector 0-15 + * format - Format of field selector + * offset - Retrieving data offset + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - input parameter out of range + * Note: + * System support 16 user defined field selctors. + * Each selector can be enabled or disable. User can defined retrieving 16-bits in many predefiend + * standard l2/l3/l4 payload. + */ +ret_t rtl8367c_setAsicFieldSelector(rtk_uint32 index, rtk_uint32 format, rtk_uint32 offset) +{ + rtk_uint32 regData; + + if(index > RTL8367C_FIELDSEL_FORMAT_NUMBER) + return RT_ERR_OUT_OF_RANGE; + + if(format >= FIELDSEL_FORMAT_END) + return RT_ERR_OUT_OF_RANGE; + + regData = (((format << RTL8367C_FIELD_SELECTOR_FORMAT_OFFSET) & RTL8367C_FIELD_SELECTOR_FORMAT_MASK ) | + ((offset << RTL8367C_FIELD_SELECTOR_OFFSET_OFFSET) & RTL8367C_FIELD_SELECTOR_OFFSET_MASK )); + + return rtl8367c_setAsicReg(RTL8367C_FIELD_SELECTOR_REG(index), regData); +} +/* Function Name: + * rtl8367c_getAsicFieldSelector + * Description: + * Get user defined field selectors in HSB + * Input: + * index - index of field selector 0-15 + * pFormat - Format of field selector + * pOffset - Retrieving data offset + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicFieldSelector(rtk_uint32 index, rtk_uint32* pFormat, rtk_uint32* pOffset) +{ + ret_t retVal; + rtk_uint32 regData; + + retVal = rtl8367c_getAsicReg(RTL8367C_FIELD_SELECTOR_REG(index), ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + *pFormat = ((regData & RTL8367C_FIELD_SELECTOR_FORMAT_MASK) >> RTL8367C_FIELD_SELECTOR_FORMAT_OFFSET); + *pOffset = ((regData & RTL8367C_FIELD_SELECTOR_OFFSET_MASK) >> RTL8367C_FIELD_SELECTOR_OFFSET_OFFSET); + + return RT_ERR_OK; +} diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_hsb.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_hsb.h new file mode 100644 index 00000000..d848d4d5 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_hsb.h @@ -0,0 +1,26 @@ +#ifndef _RTL8367C_ASICDRV__HSB_H_ +#define _RTL8367C_ASICDRV__HSB_H_ + +#include + +#define RTL8367C_FIELDSEL_FORMAT_NUMBER (16) +#define RTL8367C_FIELDSEL_MAX_OFFSET (255) + +enum FIELDSEL_FORMAT_FORMAT +{ + FIELDSEL_FORMAT_DEFAULT = 0, + FIELDSEL_FORMAT_RAW, + FIELDSEL_FORMAT_LLC, + FIELDSEL_FORMAT_IPV4, + FIELDSEL_FORMAT_ARP, + FIELDSEL_FORMAT_IPV6, + FIELDSEL_FORMAT_IPPAYLOAD, + FIELDSEL_FORMAT_L4PAYLOAD, + FIELDSEL_FORMAT_END +}; + +extern ret_t rtl8367c_setAsicFieldSelector(rtk_uint32 index, rtk_uint32 format, rtk_uint32 offset); +extern ret_t rtl8367c_getAsicFieldSelector(rtk_uint32 index, rtk_uint32* pFormat, rtk_uint32* pOffset); + +#endif /*_RTL8367C_ASICDRV__HSB_H_*/ + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_i2c.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_i2c.c new file mode 100644 index 00000000..b29df629 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_i2c.c @@ -0,0 +1,476 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision: 38651 $ + * $Date: 2016-02-27 14:32:56 +0800 (周三, 17 四月 2016) $ + * + * Purpose : RTL8367C switch high-level API for RTL8367C + * Feature : I2C related functions + * + */ + + +#include +#include +#include + + + +/* Function Name: + * rtl8367c_setAsicI2C_checkBusIdle + * Description: + * Check i2c bus status idle or not + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_BUSYWAIT_TIMEOUT - i2c bus is busy + * Note: + * This API can check i2c bus status. + */ +ret_t rtl8367c_setAsicI2C_checkBusIdle(void) +{ + rtk_uint32 regData; + ret_t retVal; + + if ((retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_M_I2C_CTL_STA_REG, RTL8367C_M_I2C_BUS_IDLE_OFFSET, ®Data)) != RT_ERR_OK) + return retVal; + + if(regData == 0x0001) + return RT_ERR_OK; /*i2c is idle*/ + else + return RT_ERR_BUSYWAIT_TIMEOUT; /*i2c is busy*/ +} + + +/* Function Name: + * rtl8367c_setAsicI2CStartCmd + * Description: + * Set I2C start command + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - Success + * Note: + * This API can set i2c start command ,start a i2c traffic . + */ +ret_t rtl8367c_setAsicI2CStartCmd(void) +{ + rtk_uint32 regData; + ret_t retVal; + + /* Bits [4-1] = 0b0000, Start Command; Bit [0] = 1, Trigger the Command */ + if ((retVal = rtl8367c_getAsicReg(RTL8367C_REG_M_I2C_CTL_STA_REG, ®Data)) != RT_ERR_OK) + return retVal; + regData &= 0xFFE0; + regData |= 0x0001; + + if ((retVal = rtl8367c_setAsicReg(RTL8367C_REG_M_I2C_CTL_STA_REG, regData)) != RT_ERR_OK) + return retVal; + + /* wait for command finished */ + do{ + if ((retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_M_I2C_CTL_STA_REG, RTL8367C_I2C_CMD_EXEC_OFFSET, ®Data)) != RT_ERR_OK) + return retVal; + }while( regData != 0x0); + + return RT_ERR_OK ; +} + +/* Function Name: + * rtl8367c_setAsicI2CStopCmd + * Description: + * Set I2C stop command + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - Success + * Note: + * This API can set i2c stop command ,stop a i2c traffic. + */ +ret_t rtl8367c_setAsicI2CStopCmd(void) +{ + + rtk_uint32 regData; + ret_t retVal; + + /* Bits [4-1] = 0b0001, Stop Command; Bit [0] = 1, Trigger the Command */ + if ((retVal = rtl8367c_getAsicReg(RTL8367C_REG_M_I2C_CTL_STA_REG, ®Data)) != RT_ERR_OK) + return retVal; + regData &= 0xFFE0; + regData |= 0x0003; + + if ((retVal = rtl8367c_setAsicReg(RTL8367C_REG_M_I2C_CTL_STA_REG, regData)) != RT_ERR_OK) + return retVal; + + + /* wait for command finished */ + do{ + if ((retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_M_I2C_CTL_STA_REG, RTL8367C_I2C_CMD_EXEC_OFFSET, ®Data)) != RT_ERR_OK) + return retVal; + }while( regData != 0x0); + + return RT_ERR_OK ; +} + +/* Function Name: + * rtl8367c_setAsicI2CTxOneCharCmd + * Description: + * Set I2C Tx a char command, with a 8-bit data + * Input: + * oneChar - 8-bit data + * Output: + * None + * Return: + * RT_ERR_OK - Success + * Note: + * This API can set i2c Tx command and with a 8-bit data. + */ +ret_t rtl8367c_setAsicI2CTxOneCharCmd(rtk_uint8 oneChar) +{ + rtk_uint32 regData; + ret_t retVal; + + /* Bits [4-1] = 0b0010, tx one char; Bit [0] = 1, Trigger the Command */ + if ((retVal = rtl8367c_getAsicReg(RTL8367C_REG_M_I2C_CTL_STA_REG, ®Data)) != RT_ERR_OK) + return retVal; + + regData &= 0xFFE0; + regData |= 0x0005; + regData &= 0x00FF; + regData |= (rtk_uint16) (oneChar << 8); + + if ((retVal = rtl8367c_setAsicReg(RTL8367C_REG_M_I2C_CTL_STA_REG, regData)) != RT_ERR_OK) + return retVal; + + + /* wait for command finished */ + do{ + if ((retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_M_I2C_CTL_STA_REG, RTL8367C_I2C_CMD_EXEC_OFFSET, ®Data)) != RT_ERR_OK) + return retVal; + }while( regData != 0x0); + + return RT_ERR_OK ; +} + + +/* Function Name: + * rtl8367c_setAsicI2CcheckRxAck + * Description: + * Check if rx an Ack + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - Success + * Note: + * This API can check if rx an ack from i2c slave. + */ +ret_t rtl8367c_setAsicI2CcheckRxAck(void) +{ + rtk_uint32 regData; + ret_t retVal; + rtk_uint32 count = 0; + + do{ + count++; + if ((retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_M_I2C_CTL_STA_REG, RTL8367C_SLV_ACK_FLAG_OFFSET, ®Data)) != RT_ERR_OK) + return retVal; + }while( (regData != 0x1) && (count < TIMEROUT_FOR_MICROSEMI) ); + + if(regData != 0x1) + return RT_ERR_FAILED; + else + return RT_ERR_OK; +} + + +/* Function Name: + * rtl8367c_setAsicI2CRxOneCharCmd + * Description: + * Set I2C Rx command and get 8-bit data + * Input: + * None + * Output: + * pValue - 8bit-data + * Return: + * RT_ERR_OK - Success + * Note: + * This API can set I2C Rx command and get 8-bit data. + */ +ret_t rtl8367c_setAsicI2CRxOneCharCmd(rtk_uint8 *pValue) +{ + rtk_uint32 regData; + ret_t retVal; + + /* Bits [4-1] = 0b0011, Rx one char; Bit [0] = 1, Trigger the Command */ + if ((retVal = rtl8367c_getAsicReg(RTL8367C_REG_M_I2C_CTL_STA_REG, ®Data)) != RT_ERR_OK) + return retVal; + regData &= 0xFFE0; + regData |= 0x0007; + if ((retVal = rtl8367c_setAsicReg(RTL8367C_REG_M_I2C_CTL_STA_REG, regData)) != RT_ERR_OK) + return retVal; + + /* wait for command finished */ + do{ + if ((retVal = rtl8367c_getAsicReg(RTL8367C_REG_M_I2C_CTL_STA_REG, ®Data)) != RT_ERR_OK) + return retVal; + }while( (regData & 0x1) != 0x0); + + *pValue = (rtk_uint8)(regData >> 8); + return RT_ERR_OK ; + +} + +/* Function Name: + * rtl8367c_setAsicI2CTxAckCmd + * Description: + * Set I2C Tx ACK command + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - Success + * Note: + * This API can set I2C Tx ack command. + */ +ret_t rtl8367c_setAsicI2CTxAckCmd(void) +{ + rtk_uint32 regData; + ret_t retVal; + + /* Bits [4-1] = 0b0100, tx ACK Command; Bit [0] = 1, Trigger the Command */ + if ((retVal = rtl8367c_getAsicReg(RTL8367C_REG_M_I2C_CTL_STA_REG, ®Data)) != RT_ERR_OK) + return retVal; + regData &= 0xFFE0; + regData |= 0x0009; + if ((retVal = rtl8367c_setAsicReg(RTL8367C_REG_M_I2C_CTL_STA_REG, regData)) != RT_ERR_OK) + return retVal; + + /* wait for command finished */ + do{ + if ((retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_M_I2C_CTL_STA_REG, RTL8367C_I2C_CMD_EXEC_OFFSET, ®Data)) != RT_ERR_OK) + return retVal; + }while( regData != 0x0); + + return RT_ERR_OK ; + +} + + +/* Function Name: + * rtl8367c_setAsicI2CTxNoAckCmd + * Description: + * Set I2C master Tx noACK command + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - Success + * Note: + * This API can set I2C master Tx noACK command. + */ +ret_t rtl8367c_setAsicI2CTxNoAckCmd(void) +{ + rtk_uint32 regData; + ret_t retVal; + + /* Bits [4-1] = 0b0101, tx noACK Command; Bit [0] = 1, Trigger the Command */ + if ((retVal = rtl8367c_getAsicReg(RTL8367C_REG_M_I2C_CTL_STA_REG, ®Data)) != RT_ERR_OK) + return retVal; + regData &= 0xFFE0; + regData |= 0x000b; + if ((retVal = rtl8367c_setAsicReg(RTL8367C_REG_M_I2C_CTL_STA_REG, regData)) != RT_ERR_OK) + return retVal; + + /* wait for command finished */ + do{ + if ((retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_M_I2C_CTL_STA_REG, RTL8367C_I2C_CMD_EXEC_OFFSET, ®Data)) != RT_ERR_OK) + return retVal; + }while( regData != 0x0); + + return RT_ERR_OK ; + +} + +/* Function Name: + * rtl8367c_setAsicI2CSoftRSTseqCmd + * Description: + * set I2C master tx soft reset command + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - Success + * Note: + * This API can set I2C master tx soft reset command. + */ +ret_t rtl8367c_setAsicI2CSoftRSTseqCmd(void) +{ + + rtk_uint32 regData; + ret_t retVal; + + /*Bits [4-1] = 0b0110, tx soft reset Command; Bit [0] = 1, Trigger the Command */ + if ((retVal = rtl8367c_getAsicReg(RTL8367C_REG_M_I2C_CTL_STA_REG, ®Data)) != RT_ERR_OK) + return retVal; + regData &= 0xFFE0; + regData |= 0x000d; + + if ((retVal = rtl8367c_setAsicReg(RTL8367C_REG_M_I2C_CTL_STA_REG, regData)) != RT_ERR_OK) + return retVal; + + + /* wait for command finished */ + do{ + if ((retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_M_I2C_CTL_STA_REG, RTL8367C_I2C_CMD_EXEC_OFFSET, ®Data)) != RT_ERR_OK) + return retVal; + }while( regData != 0x0); + + return RT_ERR_OK ; +} + + +/* Function Name: + * rtl8367c_setAsicI2CGpioPinGroup + * Description: + * set I2C function used gpio pins + * Input: + * pinGroup_ID - gpio pins group + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_INPUT _ Invalid input parameter + * Note: + * This API can set I2C function used gpio pins. + * There are three group gpio pins + */ +ret_t rtl8367c_setAsicI2CGpioPinGroup(rtk_uint32 pinGroup_ID) +{ + rtk_uint32 regData; + ret_t retVal; + + if ((retVal = rtl8367c_getAsicReg(RTL8367C_REG_M_I2C_SYS_CTL, ®Data)) != RT_ERR_OK) + return retVal; + if( pinGroup_ID==0 ) + { + regData &= 0x0FFF; + regData |= 0x5000; + + if ((retVal = rtl8367c_setAsicReg(RTL8367C_REG_M_I2C_SYS_CTL, regData)) != RT_ERR_OK) + return retVal; + } + + else if( pinGroup_ID==1 ) + { + regData &= 0x0FFF; + regData |= 0xA000; + + if ((retVal = rtl8367c_setAsicReg(RTL8367C_REG_M_I2C_SYS_CTL, regData)) != RT_ERR_OK) + return retVal; + } + + else if( pinGroup_ID==2 ) + { + regData &= 0x0FFF; + regData |= 0xF000; + + if ((retVal = rtl8367c_setAsicReg(RTL8367C_REG_M_I2C_SYS_CTL, regData)) != RT_ERR_OK) + return retVal; + } + else + return RT_ERR_INPUT; + + return RT_ERR_OK ; + +} + +/* Function Name: + * rtl8367c_setAsicI2CGpioPinGroup + * Description: + * set I2C function used gpio pins + * Input: + * pinGroup_ID - gpio pins group + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_INPUT _ Invalid input parameter + * Note: + * This API can set I2C function used gpio pins. + * There are three group gpio pins + */ +ret_t rtl8367c_getAsicI2CGpioPinGroup(rtk_uint32 * pPinGroup_ID) +{ + + rtk_uint32 regData; + ret_t retVal; + if( (retVal = rtl8367c_getAsicReg(RTL8367C_REG_M_I2C_SYS_CTL, ®Data)) != RT_ERR_OK) + return retVal; + regData &= 0xF000 ; + regData = (regData >> 12); + + if( regData == 0x5 ) + *pPinGroup_ID = 0; + else if(regData == 0xA) + *pPinGroup_ID = 1; + else if(regData == 0xF) + *pPinGroup_ID = 2; + else + return RT_ERR_FAILED; + return RT_ERR_OK ; +} + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_i2c.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_i2c.h new file mode 100644 index 00000000..7a73a711 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_i2c.h @@ -0,0 +1,29 @@ +#ifndef _RTL8367C_ASICDRV_I2C_H_ +#define _RTL8367C_ASICDRV_I2C_H_ +#include +#include + + +#define TIMEROUT_FOR_MICROSEMI (0x400) + +#define GPIO_INPUT 1 +#define GPIO_OUTPUT 2 + +extern ret_t rtl8367c_setAsicI2C_checkBusIdle(void); +extern ret_t rtl8367c_setAsicI2CStartCmd(void); +extern ret_t rtl8367c_setAsicI2CStopCmd(void); +extern ret_t rtl8367c_setAsicI2CTxOneCharCmd(rtk_uint8 oneChar); +extern ret_t rtl8367c_setAsicI2CcheckRxAck(void); +extern ret_t rtl8367c_setAsicI2CRxOneCharCmd(rtk_uint8 *pValue); +extern ret_t rtl8367c_setAsicI2CTxAckCmd(void); +extern ret_t rtl8367c_setAsicI2CTxNoAckCmd(void); +extern ret_t rtl8367c_setAsicI2CSoftRSTseqCmd(void); +extern ret_t rtl8367c_setAsicI2CGpioPinGroup(rtk_uint32 pinGroup_ID); +extern ret_t rtl8367c_getAsicI2CGpioPinGroup(rtk_uint32 * pPinGroup_ID); + + + + + +#endif /*#ifndef _RTL8367C_ASICDRV_I2C_H_*/ + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_igmp.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_igmp.c new file mode 100644 index 00000000..101faa3d --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_igmp.c @@ -0,0 +1,2111 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTL8367C switch high-level API for RTL8367C + * Feature : IGMP related functions + * + */ +#include +/* Function Name: + * rtl8367c_setAsicIgmp + * Description: + * Set IGMP/MLD state + * Input: + * enabled - 1: enabled, 0: disabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicIgmp(rtk_uint32 enabled) +{ + ret_t retVal; + + /* Enable/Disable H/W IGMP/MLD */ + retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_IGMP_MLD_CFG0, RTL8367C_IGMP_MLD_EN_OFFSET, enabled); + + return retVal; +} +/* Function Name: + * rtl8367c_getAsicIgmp + * Description: + * Get IGMP/MLD state + * Input: + * enabled - 1: enabled, 0: disabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicIgmp(rtk_uint32 *ptr_enabled) +{ + ret_t retVal; + + retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_IGMP_MLD_CFG0, RTL8367C_IGMP_MLD_EN_OFFSET, ptr_enabled); + return retVal; +} +/* Function Name: + * rtl8367c_setAsicIpMulticastVlanLeaky + * Description: + * Set IP multicast VLAN Leaky function + * Input: + * port - Physical port number (0~7) + * enabled - 1: enabled, 0: disabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * When enabling this function, + * if the lookup result(forwarding portmap) of IP Multicast packet is over VLAN boundary, + * the packet can be forwarded across VLAN + */ +ret_t rtl8367c_setAsicIpMulticastVlanLeaky(rtk_uint32 port, rtk_uint32 enabled) +{ + ret_t retVal; + + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_IPMCAST_VLAN_LEAKY, port, enabled); + + return retVal; +} +/* Function Name: + * rtl8367c_getAsicIpMulticastVlanLeaky + * Description: + * Get IP multicast VLAN Leaky function + * Input: + * port - Physical port number (0~7) + * enabled - 1: enabled, 0: disabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_getAsicIpMulticastVlanLeaky(rtk_uint32 port, rtk_uint32 *ptr_enabled) +{ + ret_t retVal; + + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_IPMCAST_VLAN_LEAKY, port, ptr_enabled); + + return retVal; +} + +/* Function Name: + * rtl8367c_setAsicIGMPTableFullOP + * Description: + * Set Table Full operation + * Input: + * operation - The operation should be taken when the IGMP table is full. + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - input parameter is out of range + * Note: + * None + */ +ret_t rtl8367c_setAsicIGMPTableFullOP(rtk_uint32 operation) +{ + ret_t retVal; + + if(operation >= TABLE_FULL_OP_END) + return RT_ERR_OUT_OF_RANGE; + + /* Table full Operation */ + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_IGMP_MLD_CFG1, RTL8367C_TABLE_FULL_OP_MASK, operation); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_getAsicIGMPTableFullOP + * Description: + * Get Table Full operation + * Input: + * None + * Output: + * poperation - The operation should be taken when the IGMP table is full. + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicIGMPTableFullOP(rtk_uint32 *poperation) +{ + ret_t retVal; + rtk_uint32 value; + + /* Table full Operation */ + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_MLD_CFG1, RTL8367C_TABLE_FULL_OP_MASK, &value); + if(retVal != RT_ERR_OK) + return retVal; + + *poperation = value; + + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_setAsicIGMPCRCErrOP + * Description: + * Set the operation when ASIC receive a Checksum error packet + * Input: + * operation -The operation when ASIC receive a Checksum error packet + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - input parameter is out of range + * Note: + * None + */ +ret_t rtl8367c_setAsicIGMPCRCErrOP(rtk_uint32 operation) +{ + ret_t retVal; + + if(operation >= CRC_ERR_OP_END) + return RT_ERR_OUT_OF_RANGE; + + /* CRC Error Operation */ + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_IGMP_MLD_CFG0, RTL8367C_CKS_ERR_OP_MASK, operation); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_getAsicIGMPCRCErrOP + * Description: + * Get the operation when ASIC receive a Checksum error packet + * Input: + * None + * Output: + * poperation - The operation of Checksum error packet + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicIGMPCRCErrOP(rtk_uint32 *poperation) +{ + ret_t retVal; + rtk_uint32 value; + + /* CRC Error Operation */ + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_MLD_CFG0, RTL8367C_CKS_ERR_OP_MASK, &value); + if(retVal != RT_ERR_OK) + return retVal; + + *poperation = value; + + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_setAsicIGMPFastLeaveEn + * Description: + * Enable/Disable Fast Leave + * Input: + * enabled - 1:enable Fast Leave; 0:disable Fast Leave + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicIGMPFastLeaveEn(rtk_uint32 enabled) +{ + ret_t retVal; + + /* Fast Leave */ + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_IGMP_MLD_CFG0, RTL8367C_FAST_LEAVE_EN_MASK, (enabled >= 1) ? 1 : 0); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_getAsicIGMPFastLeaveEn + * Description: + * Get Fast Leave state + * Input: + * None + * Output: + * penabled - 1:enable Fast Leave; 0:disable Fast Leave + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicIGMPFastLeaveEn(rtk_uint32 *penabled) +{ + ret_t retVal; + rtk_uint32 value; + + /* Fast Leave */ + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_MLD_CFG0, RTL8367C_FAST_LEAVE_EN_MASK, &value); + if(retVal != RT_ERR_OK) + return retVal; + + *penabled = value; + + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_setAsicIGMPLeaveTimer + * Description: + * Set the Leave timer of IGMP/MLD + * Input: + * leave_timer - Leave timer + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - input parameter is out of range + * Note: + * None + */ +ret_t rtl8367c_setAsicIGMPLeaveTimer(rtk_uint32 leave_timer) +{ + ret_t retVal; + + if(leave_timer > RTL8367C_MAX_LEAVE_TIMER) + return RT_ERR_OUT_OF_RANGE; + + /* Leave timer */ + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_IGMP_MLD_CFG0, RTL8367C_LEAVE_TIMER_MASK, leave_timer); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_getAsicIGMPLeaveTimer + * Description: + * Get the Leave timer of IGMP/MLD + * Input: + * None + * Output: + * pleave_timer - Leave timer + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicIGMPLeaveTimer(rtk_uint32 *pleave_timer) +{ + ret_t retVal; + rtk_uint32 value; + + /* Leave timer */ + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_MLD_CFG0, RTL8367C_LEAVE_TIMER_MASK, &value); + if(retVal != RT_ERR_OK) + return retVal; + + *pleave_timer = value; + + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_setAsicIGMPQueryInterval + * Description: + * Set Query Interval of IGMP/MLD + * Input: + * interval - Query Interval + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - input parameter is out of range + * Note: + * None + */ +ret_t rtl8367c_setAsicIGMPQueryInterval(rtk_uint32 interval) +{ + ret_t retVal; + + if(interval > RTL8367C_MAX_QUERY_INT) + return RT_ERR_OUT_OF_RANGE; + + /* Query Interval */ + retVal = rtl8367c_setAsicReg(RTL8367C_REG_IGMP_MLD_CFG2, interval); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_getAsicIGMPQueryInterval + * Description: + * Get Query Interval of IGMP/MLD + * Input: + * None + * Output: + * pinterval - Query Interval + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicIGMPQueryInterval(rtk_uint32 *pinterval) +{ + ret_t retVal; + rtk_uint32 value; + + /* Query Interval */ + retVal = rtl8367c_getAsicReg(RTL8367C_REG_IGMP_MLD_CFG2, &value); + if(retVal != RT_ERR_OK) + return retVal; + + *pinterval = value; + + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_setAsicIGMPRobVar + * Description: + * Set Robustness Variable of IGMP/MLD + * Input: + * rob_var - Robustness Variable + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - input parameter is out of range + * Note: + * None + */ +ret_t rtl8367c_setAsicIGMPRobVar(rtk_uint32 rob_var) +{ + ret_t retVal; + + if(rob_var > RTL8367C_MAX_ROB_VAR) + return RT_ERR_OUT_OF_RANGE; + + /* Bourstness variable */ + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_IGMP_MLD_CFG0, RTL8367C_ROBURSTNESS_VAR_MASK, rob_var); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_getAsicIGMPRobVar + * Description: + * Get Robustness Variable of IGMP/MLD + * Input: + * none + * Output: + * prob_var - Robustness Variable + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicIGMPRobVar(rtk_uint32 *prob_var) +{ + ret_t retVal; + rtk_uint32 value; + + /* Bourstness variable */ + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_MLD_CFG0, RTL8367C_ROBURSTNESS_VAR_MASK, &value); + if(retVal != RT_ERR_OK) + return retVal; + + *prob_var = value; + + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_setAsicIGMPStaticRouterPort + * Description: + * Set IGMP static router port mask + * Input: + * pmsk - Static portmask + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Invalid port mask + * Note: + * None + */ +ret_t rtl8367c_setAsicIGMPStaticRouterPort(rtk_uint32 pmsk) +{ + if(pmsk > RTL8367C_PORTMASK) + return RT_ERR_PORT_MASK; + + return rtl8367c_setAsicRegBits(RTL8367C_REG_IGMP_STATIC_ROUTER_PORT, RTL8367C_IGMP_STATIC_ROUTER_PORT_MASK, pmsk); +} + +/* Function Name: + * rtl8367c_getAsicIGMPStaticRouterPort + * Description: + * Get IGMP static router port mask + * Input: + * pmsk - Static portmask + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicIGMPStaticRouterPort(rtk_uint32 *pmsk) +{ + return rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_STATIC_ROUTER_PORT, RTL8367C_IGMP_STATIC_ROUTER_PORT_MASK, pmsk); +} + +/* Function Name: + * rtl8367c_setAsicIGMPAllowDynamicRouterPort + * Description: + * Set IGMP dynamic router port allow mask + * Input: + * pmsk - Allow dynamic router port mask + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Invalid port mask + * Note: + * None + */ +ret_t rtl8367c_setAsicIGMPAllowDynamicRouterPort(rtk_uint32 pmsk) +{ + return rtl8367c_setAsicReg(RTL8367C_REG_IGMP_MLD_CFG4, pmsk); +} + +/* Function Name: + * rtl8367c_getAsicIGMPAllowDynamicRouterPort + * Description: + * Get IGMP dynamic router port allow mask + * Input: + * None. + * Output: + * pPmsk - Allow dynamic router port mask + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Invalid port mask + * Note: + * None + */ +ret_t rtl8367c_getAsicIGMPAllowDynamicRouterPort(rtk_uint32 *pPmsk) +{ + return rtl8367c_getAsicReg(RTL8367C_REG_IGMP_MLD_CFG4, pPmsk); +} + +/* Function Name: + * rtl8367c_getAsicIGMPdynamicRouterPort1 + * Description: + * Get 1st dynamic router port and timer + * Input: + * port - Physical port number (0~7) + * timer - router port timer + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicIGMPdynamicRouterPort1(rtk_uint32 *port, rtk_uint32 *timer) +{ + ret_t retVal; + + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_DYNAMIC_ROUTER_PORT, RTL8367C_D_ROUTER_PORT_1_MASK, port); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_DYNAMIC_ROUTER_PORT, RTL8367C_D_ROUTER_PORT_TMR_1_MASK, timer); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_getAsicIGMPdynamicRouterPort2 + * Description: + * Get 2nd dynamic router port and timer + * Input: + * port - Physical port number (0~7) + * timer - router port timer + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicIGMPdynamicRouterPort2(rtk_uint32 *port, rtk_uint32 *timer) +{ + ret_t retVal; + + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_DYNAMIC_ROUTER_PORT, RTL8367C_D_ROUTER_PORT_2_MASK, port); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_DYNAMIC_ROUTER_PORT, RTL8367C_D_ROUTER_PORT_TMR_2_MASK, timer); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_setAsicIGMPSuppression + * Description: + * Set the suppression function + * Input: + * report_supp_enabled - Report suppression, 1:Enable, 0:disable + * leave_supp_enabled - Leave suppression, 1:Enable, 0:disable + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicIGMPSuppression(rtk_uint32 report_supp_enabled, rtk_uint32 leave_supp_enabled) +{ + ret_t retVal; + + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_IGMP_MLD_CFG0, RTL8367C_REPORT_SUPPRESSION_MASK, report_supp_enabled); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_IGMP_MLD_CFG0, RTL8367C_LEAVE_SUPPRESSION_MASK, leave_supp_enabled); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_getAsicIGMPSuppression + * Description: + * Get the suppression function + * Input: + * report_supp_enabled - Report suppression, 1:Enable, 0:disable + * leave_supp_enabled - Leave suppression, 1:Enable, 0:disable + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicIGMPSuppression(rtk_uint32 *report_supp_enabled, rtk_uint32 *leave_supp_enabled) +{ + ret_t retVal; + + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_MLD_CFG0, RTL8367C_REPORT_SUPPRESSION_MASK, report_supp_enabled); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_MLD_CFG0, RTL8367C_LEAVE_SUPPRESSION_MASK, leave_supp_enabled); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_setAsicIGMPQueryRX + * Description: + * Set port-based Query packet RX allowance + * Input: + * port - port number + * allow_query - allowance of Query packet RX, 1:Allow, 0:Drop + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_PORT_ID - Error PORT ID + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicIGMPQueryRX(rtk_uint32 port, rtk_uint32 allow_query) +{ + ret_t retVal; + + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + /* Allow Query */ + if (port < 8) + { + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_IGMP_PORT0_CONTROL + port, RTL8367C_IGMP_PORT0_CONTROL_ALLOW_QUERY_MASK, allow_query); + if(retVal != RT_ERR_OK) + return retVal; + } + else + { + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_IGMP_PORT8_CONTROL + port - 8, RTL8367C_IGMP_PORT0_CONTROL_ALLOW_QUERY_MASK, allow_query); + if(retVal != RT_ERR_OK) + return retVal; + } + + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_getAsicIGMPQueryRX + * Description: + * Get port-based Query packet RX allowance + * Input: + * port - port number + * Output: + * allow_query - allowance of Query packet RX, 1:Allow, 0:Drop + * Return: + * RT_ERR_OK - Success + * RT_ERR_PORT_ID - Error PORT ID + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicIGMPQueryRX(rtk_uint32 port, rtk_uint32 *allow_query) +{ + ret_t retVal; + rtk_uint32 value; + + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + /* Allow Query */ + if (port < 8) + { + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_PORT0_CONTROL + port, RTL8367C_IGMP_PORT0_CONTROL_ALLOW_QUERY_MASK, &value); + if(retVal != RT_ERR_OK) + return retVal; + } + else + { + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_PORT8_CONTROL + port - 8, RTL8367C_IGMP_PORT0_CONTROL_ALLOW_QUERY_MASK, &value); + if(retVal != RT_ERR_OK) + return retVal; + } + *allow_query = value; + + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_setAsicIGMPReportRX + * Description: + * Set port-based Report packet RX allowance + * Input: + * port - port number + * allow_report - allowance of Report packet RX, 1:Allow, 0:Drop + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_PORT_ID - Error PORT ID + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicIGMPReportRX(rtk_uint32 port, rtk_uint32 allow_report) +{ + ret_t retVal; + + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + if(port < 8) + { + /* Allow Report */ + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_IGMP_PORT0_CONTROL + port, RTL8367C_IGMP_PORT0_CONTROL_ALLOW_REPORT_MASK, allow_report); + if(retVal != RT_ERR_OK) + return retVal; + } + else + { + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_IGMP_PORT8_CONTROL + port - 8, RTL8367C_IGMP_PORT0_CONTROL_ALLOW_REPORT_MASK, allow_report); + if(retVal != RT_ERR_OK) + return retVal; + } + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_getAsicIGMPReportRX + * Description: + * Get port-based Report packet RX allowance + * Input: + * port - port number + * Output: + * allow_report - allowance of Report packet RX, 1:Allow, 0:Drop + * Return: + * RT_ERR_OK - Success + * RT_ERR_PORT_ID - Error PORT ID + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicIGMPReportRX(rtk_uint32 port, rtk_uint32 *allow_report) +{ + ret_t retVal; + rtk_uint32 value; + + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + if(port < 8) + { + /* Allow Report */ + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_PORT0_CONTROL + port, RTL8367C_IGMP_PORT0_CONTROL_ALLOW_REPORT_MASK, &value); + if(retVal != RT_ERR_OK) + return retVal; + } + else + { + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_PORT8_CONTROL + port - 8, RTL8367C_IGMP_PORT0_CONTROL_ALLOW_REPORT_MASK, &value); + if(retVal != RT_ERR_OK) + return retVal; + } + *allow_report = value; + + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_setAsicIGMPLeaveRX + * Description: + * Set port-based Leave packet RX allowance + * Input: + * port - port number + * allow_leave - allowance of Leave packet RX, 1:Allow, 0:Drop + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_PORT_ID - Error PORT ID + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicIGMPLeaveRX(rtk_uint32 port, rtk_uint32 allow_leave) +{ + ret_t retVal; + + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + if(port < 8) + { + /* Allow Leave */ + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_IGMP_PORT0_CONTROL + port, RTL8367C_IGMP_PORT0_CONTROL_ALLOW_LEAVE_MASK, allow_leave); + if(retVal != RT_ERR_OK) + return retVal; + } + else + { + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_IGMP_PORT8_CONTROL + port - 8, RTL8367C_IGMP_PORT0_CONTROL_ALLOW_LEAVE_MASK, allow_leave); + if(retVal != RT_ERR_OK) + return retVal; + } + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_getAsicIGMPLeaveRX + * Description: + * Get port-based Leave packet RX allowance + * Input: + * port - port number + * Output: + * allow_leave - allowance of Leave packet RX, 1:Allow, 0:Drop + * Return: + * RT_ERR_OK - Success + * RT_ERR_PORT_ID - Error PORT ID + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicIGMPLeaveRX(rtk_uint32 port, rtk_uint32 *allow_leave) +{ + ret_t retVal; + rtk_uint32 value; + + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + if(port < 8) + { + /* Allow Leave */ + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_PORT0_CONTROL + port, RTL8367C_IGMP_PORT0_CONTROL_ALLOW_LEAVE_MASK, &value); + if(retVal != RT_ERR_OK) + return retVal; + } + else + { + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_PORT8_CONTROL + port - 8, RTL8367C_IGMP_PORT0_CONTROL_ALLOW_LEAVE_MASK, &value); + if(retVal != RT_ERR_OK) + return retVal; + } + + *allow_leave = value; + + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_setAsicIGMPMRPRX + * Description: + * Set port-based Multicast Routing Protocol packet RX allowance + * Input: + * port - port number + * allow_mrp - allowance of Multicast Routing Protocol packet RX, 1:Allow, 0:Drop + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_PORT_ID - Error PORT ID + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicIGMPMRPRX(rtk_uint32 port, rtk_uint32 allow_mrp) +{ + ret_t retVal; + + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + if(port < 8) + { + /* Allow Multicast Routing Protocol */ + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_IGMP_PORT0_CONTROL + port, RTL8367C_IGMP_PORT0_CONTROL_ALLOW_MRP_MASK, allow_mrp); + if(retVal != RT_ERR_OK) + return retVal; + } + else + { + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_IGMP_PORT8_CONTROL + port - 8, RTL8367C_IGMP_PORT0_CONTROL_ALLOW_MRP_MASK, allow_mrp); + if(retVal != RT_ERR_OK) + return retVal; + } + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_getAsicIGMPMRPRX + * Description: + * Get port-based Multicast Routing Protocol packet RX allowance + * Input: + * port - port number + * Output: + * allow_mrp - allowance of Multicast Routing Protocol packet RX, 1:Allow, 0:Drop + * Return: + * RT_ERR_OK - Success + * RT_ERR_PORT_ID - Error PORT ID + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicIGMPMRPRX(rtk_uint32 port, rtk_uint32 *allow_mrp) +{ + ret_t retVal; + rtk_uint32 value; + + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + /* Allow Multicast Routing Protocol */ + if(port < 8) + { + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_PORT0_CONTROL + port, RTL8367C_IGMP_PORT0_CONTROL_ALLOW_MRP_MASK, &value); + if(retVal != RT_ERR_OK) + return retVal; + } + else + { + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_PORT8_CONTROL + port - 8, RTL8367C_IGMP_PORT0_CONTROL_ALLOW_MRP_MASK, &value); + if(retVal != RT_ERR_OK) + return retVal; + } + *allow_mrp = value; + + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_setAsicIGMPMcDataRX + * Description: + * Set port-based Multicast data packet RX allowance + * Input: + * port - port number + * allow_mcdata - allowance of Multicast data packet RX, 1:Allow, 0:Drop + * Output: + * none + * Return: + * RT_ERR_OK - Success + * RT_ERR_PORT_ID - Error PORT ID + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicIGMPMcDataRX(rtk_uint32 port, rtk_uint32 allow_mcdata) +{ + ret_t retVal; + + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + /* Allow Multicast Data */ + if(port < 8) + { + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_IGMP_PORT0_CONTROL + port, RTL8367C_IGMP_PORT0_CONTROL_ALLOW_MC_DATA_MASK, allow_mcdata); + if(retVal != RT_ERR_OK) + return retVal; + } + else + { + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_IGMP_PORT8_CONTROL + port - 8, RTL8367C_IGMP_PORT0_CONTROL_ALLOW_MC_DATA_MASK, allow_mcdata); + if(retVal != RT_ERR_OK) + return retVal; + } + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_getAsicIGMPMcDataRX + * Description: + * Get port-based Multicast data packet RX allowance + * Input: + * port - port number + * Output: + * allow_mcdata - allowance of Multicast data packet RX, 1:Allow, 0:Drop + * Return: + * RT_ERR_OK - Success + * RT_ERR_PORT_ID - Error PORT ID + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicIGMPMcDataRX(rtk_uint32 port, rtk_uint32 *allow_mcdata) +{ + ret_t retVal; + rtk_uint32 value; + + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + /* Allow Multicast data */ + if(port < 8) + { + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_PORT0_CONTROL + port, RTL8367C_IGMP_PORT0_CONTROL_ALLOW_MC_DATA_MASK, &value); + if(retVal != RT_ERR_OK) + return retVal; + } + else + { + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_PORT8_CONTROL + port - 8, RTL8367C_IGMP_PORT0_CONTROL_ALLOW_MC_DATA_MASK, &value); + if(retVal != RT_ERR_OK) + return retVal; + } + + *allow_mcdata = value; + + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_setAsicIGMPv1Opeartion + * Description: + * Set port-based IGMPv1 Control packet action + * Input: + * port - port number + * igmpv1_op - IGMPv1 control packet action + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_PORT_ID - Error PORT ID + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicIGMPv1Opeartion(rtk_uint32 port, rtk_uint32 igmpv1_op) +{ + ret_t retVal; + + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + if(igmpv1_op >= PROTOCOL_OP_END) + return RT_ERR_INPUT; + + /* IGMPv1 operation */ + if(port < 8) + { + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_IGMP_PORT0_CONTROL + port, RTL8367C_IGMP_PORT0_CONTROL_IGMPV1_OP_MASK, igmpv1_op); + if(retVal != RT_ERR_OK) + return retVal; + } + else + { + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_IGMP_PORT8_CONTROL + port - 8, RTL8367C_IGMP_PORT0_CONTROL_IGMPV1_OP_MASK, igmpv1_op); + if(retVal != RT_ERR_OK) + return retVal; + } + + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_getAsicIGMPv1Opeartion + * Description: + * Get port-based IGMPv1 Control packet action + * Input: + * port - port number + * Output: + * igmpv1_op - IGMPv1 control packet action + * Return: + * RT_ERR_OK - Success + * RT_ERR_PORT_ID - Error PORT ID + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicIGMPv1Opeartion(rtk_uint32 port, rtk_uint32 *igmpv1_op) +{ + ret_t retVal; + rtk_uint32 value; + + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + /* IGMPv1 operation */ + if(port < 8) + { + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_PORT0_CONTROL + port, RTL8367C_IGMP_PORT0_CONTROL_IGMPV1_OP_MASK, &value); + if(retVal != RT_ERR_OK) + return retVal; + } + else + { + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_PORT8_CONTROL + port - 8, RTL8367C_IGMP_PORT0_CONTROL_IGMPV1_OP_MASK, &value); + if(retVal != RT_ERR_OK) + return retVal; + } + + *igmpv1_op = value; + + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_setAsicIGMPv2Opeartion + * Description: + * Set port-based IGMPv2 Control packet action + * Input: + * port - port number + * igmpv2_op - IGMPv2 control packet action + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_PORT_ID - Error PORT ID + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicIGMPv2Opeartion(rtk_uint32 port, rtk_uint32 igmpv2_op) +{ + ret_t retVal; + + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + if(igmpv2_op >= PROTOCOL_OP_END) + return RT_ERR_INPUT; + + /* IGMPv2 operation */ + if(port < 8) + { + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_IGMP_PORT0_CONTROL + port, RTL8367C_IGMP_PORT0_CONTROL_IGMPV2_OP_MASK, igmpv2_op); + if(retVal != RT_ERR_OK) + return retVal; + } + else + { + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_IGMP_PORT8_CONTROL + port - 8, RTL8367C_IGMP_PORT0_CONTROL_IGMPV2_OP_MASK, igmpv2_op); + if(retVal != RT_ERR_OK) + return retVal; + } + + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_getAsicIGMPv2Opeartion + * Description: + * Get port-based IGMPv2 Control packet action + * Input: + * port - port number + * Output: + * igmpv2_op - IGMPv2 control packet action + * Return: + * RT_ERR_OK - Success + * RT_ERR_PORT_ID - Error PORT ID + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicIGMPv2Opeartion(rtk_uint32 port, rtk_uint32 *igmpv2_op) +{ + ret_t retVal; + rtk_uint32 value; + + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + /* IGMPv2 operation */ + if(port < 8) + { + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_PORT0_CONTROL + port, RTL8367C_IGMP_PORT0_CONTROL_IGMPV2_OP_MASK, &value); + if(retVal != RT_ERR_OK) + return retVal; + } + else + { + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_PORT8_CONTROL + port - 8, RTL8367C_IGMP_PORT0_CONTROL_IGMPV2_OP_MASK, &value); + if(retVal != RT_ERR_OK) + return retVal; + } + + *igmpv2_op = value; + + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_setAsicIGMPv3Opeartion + * Description: + * Set port-based IGMPv3 Control packet action + * Input: + * port - port number + * igmpv3_op - IGMPv3 control packet action + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_PORT_ID - Error PORT ID + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicIGMPv3Opeartion(rtk_uint32 port, rtk_uint32 igmpv3_op) +{ + ret_t retVal; + + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + if(igmpv3_op >= PROTOCOL_OP_END) + return RT_ERR_INPUT; + + /* IGMPv3 operation */ + if(port < 8) + { + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_IGMP_PORT0_CONTROL + port, RTL8367C_IGMP_PORT0_CONTROL_IGMPV3_OP_MASK, igmpv3_op); + if(retVal != RT_ERR_OK) + return retVal; + } + else + { + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_IGMP_PORT8_CONTROL + port - 8, RTL8367C_IGMP_PORT0_CONTROL_IGMPV3_OP_MASK, igmpv3_op); + if(retVal != RT_ERR_OK) + return retVal; + } + + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_getAsicIGMPv3Opeartion + * Description: + * Get port-based IGMPv3 Control packet action + * Input: + * port - port number + * Output: + * igmpv3_op - IGMPv3 control packet action + * Return: + * RT_ERR_OK - Success + * RT_ERR_PORT_ID - Error PORT ID + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicIGMPv3Opeartion(rtk_uint32 port, rtk_uint32 *igmpv3_op) +{ + ret_t retVal; + rtk_uint32 value; + + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + /* IGMPv3 operation */ + if(port < 8) + { + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_PORT0_CONTROL + port, RTL8367C_IGMP_PORT0_CONTROL_IGMPV3_OP_MASK, &value); + if(retVal != RT_ERR_OK) + return retVal; + } + else + { + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_PORT8_CONTROL + port - 8, RTL8367C_IGMP_PORT0_CONTROL_IGMPV3_OP_MASK, &value); + if(retVal != RT_ERR_OK) + return retVal; + } + + *igmpv3_op = value; + + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_setAsicMLDv1Opeartion + * Description: + * Set port-based MLDv1 Control packet action + * Input: + * port - port number + * mldv1_op - MLDv1 control packet action + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_PORT_ID - Error PORT ID + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicMLDv1Opeartion(rtk_uint32 port, rtk_uint32 mldv1_op) +{ + ret_t retVal; + + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + if(mldv1_op >= PROTOCOL_OP_END) + return RT_ERR_INPUT; + + /* MLDv1 operation */ + if(port < 8) + { + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_IGMP_PORT0_CONTROL + port, RTL8367C_IGMP_PORT0_CONTROL_MLDv1_OP_MASK, mldv1_op); + if(retVal != RT_ERR_OK) + return retVal; + } + else + { + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_IGMP_PORT8_CONTROL + port - 8, RTL8367C_IGMP_PORT0_CONTROL_MLDv1_OP_MASK, mldv1_op); + if(retVal != RT_ERR_OK) + return retVal; + } + + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_getAsicMLDv1Opeartion + * Description: + * Get port-based MLDv1 Control packet action + * Input: + * port - port number + * Output: + * mldv1_op - MLDv1 control packet action + * Return: + * RT_ERR_OK - Success + * RT_ERR_PORT_ID - Error PORT ID + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicMLDv1Opeartion(rtk_uint32 port, rtk_uint32 *mldv1_op) +{ + ret_t retVal; + rtk_uint32 value; + + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + /* MLDv1 operation */ + if(port < 8) + { + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_PORT0_CONTROL + port, RTL8367C_IGMP_PORT0_CONTROL_MLDv1_OP_MASK, &value); + if(retVal != RT_ERR_OK) + return retVal; + } + else + { + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_PORT8_CONTROL + port - 8, RTL8367C_IGMP_PORT0_CONTROL_MLDv1_OP_MASK, &value); + if(retVal != RT_ERR_OK) + return retVal; + } + + *mldv1_op = value; + + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_setAsicMLDv2Opeartion + * Description: + * Set port-based MLDv2 Control packet action + * Input: + * port - port number + * mldv2_op - MLDv2 control packet action + * Output: + * none + * Return: + * RT_ERR_OK - Success + * RT_ERR_PORT_ID - Error PORT ID + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicMLDv2Opeartion(rtk_uint32 port, rtk_uint32 mldv2_op) +{ + ret_t retVal; + + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + if(mldv2_op >= PROTOCOL_OP_END) + return RT_ERR_INPUT; + + /* MLDv2 operation */ + if(port < 8) + { + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_IGMP_PORT0_CONTROL + port, RTL8367C_IGMP_PORT0_CONTROL_MLDv2_OP_MASK, mldv2_op); + if(retVal != RT_ERR_OK) + return retVal; + } + else + { + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_IGMP_PORT8_CONTROL + port - 8, RTL8367C_IGMP_PORT0_CONTROL_MLDv2_OP_MASK, mldv2_op); + if(retVal != RT_ERR_OK) + return retVal; + } + + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_getAsicMLDv2Opeartion + * Description: + * Get port-based MLDv2 Control packet action + * Input: + * port - port number + * Output: + * mldv2_op - MLDv2 control packet action + * Return: + * RT_ERR_OK - Success + * RT_ERR_PORT_ID - Error PORT ID + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicMLDv2Opeartion(rtk_uint32 port, rtk_uint32 *mldv2_op) +{ + ret_t retVal; + rtk_uint32 value; + + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + /* MLDv2 operation */ + if(port < 8) + { + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_PORT0_CONTROL + port, RTL8367C_IGMP_PORT0_CONTROL_MLDv2_OP_MASK, &value); + if(retVal != RT_ERR_OK) + return retVal; + } + else + { + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_PORT8_CONTROL + port - 8, RTL8367C_IGMP_PORT0_CONTROL_MLDv2_OP_MASK, &value); + if(retVal != RT_ERR_OK) + return retVal; + } + + *mldv2_op = value; + + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_setAsicIGMPPortMAXGroup + * Description: + * Set per-port Max group number + * Input: + * port - Physical port number (0~7) + * max_group - max IGMP group + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * RT_ERR_OUT_OF_RANGE - input parameter out of range + * Note: + * None + */ +ret_t rtl8367c_setAsicIGMPPortMAXGroup(rtk_uint32 port, rtk_uint32 max_group) +{ + ret_t retVal; + + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + if(max_group > RTL8367C_IGMP_MAX_GOUP) + return RT_ERR_OUT_OF_RANGE; + + if(port < 8) + { + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_IGMP_PORT01_MAX_GROUP + (port/2), RTL8367C_PORT0_MAX_GROUP_MASK << (RTL8367C_PORT1_MAX_GROUP_OFFSET * (port%2)), max_group); + if(retVal != RT_ERR_OK) + return retVal; + } + else + { + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_IGMP_PORT89_MAX_GROUP + (port/2), RTL8367C_PORT0_MAX_GROUP_MASK << (RTL8367C_PORT1_MAX_GROUP_OFFSET * (port%2)), max_group); + if(retVal != RT_ERR_OK) + return retVal; + } + + return RT_ERR_OK; +} +/* Function Name: + * rtl8367c_getAsicIGMPPortMAXGroup + * Description: + * Get per-port Max group number + * Input: + * port - Physical port number (0~7) + * max_group - max IGMP group + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_getAsicIGMPPortMAXGroup(rtk_uint32 port, rtk_uint32 *max_group) +{ + ret_t retVal; + rtk_uint32 value; + + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + if(port < 8) + { + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_PORT01_MAX_GROUP + (port/2), RTL8367C_PORT0_MAX_GROUP_MASK << (RTL8367C_PORT1_MAX_GROUP_OFFSET * (port%2)), &value); + if(retVal != RT_ERR_OK) + return retVal; + } + else + { + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_PORT89_MAX_GROUP + (port/2), RTL8367C_PORT0_MAX_GROUP_MASK << (RTL8367C_PORT1_MAX_GROUP_OFFSET * (port%2)), &value); + if(retVal != RT_ERR_OK) + return retVal; + } + + *max_group = value; + return RT_ERR_OK; +} +/* Function Name: + * rtl8367c_getAsicIGMPPortCurrentGroup + * Description: + * Get per-port current group number + * Input: + * port - Physical port number (0~7) + * current_group - current IGMP group + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_getAsicIGMPPortCurrentGroup(rtk_uint32 port, rtk_uint32 *current_group) +{ + ret_t retVal; + rtk_uint32 value; + + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + if(port < 8) + { + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_PORT01_CURRENT_GROUP + (port/2), RTL8367C_PORT0_CURRENT_GROUP_MASK << (RTL8367C_PORT1_CURRENT_GROUP_OFFSET * (port%2)), &value); + if(retVal != RT_ERR_OK) + return retVal; + } + else + { + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_PORT89_CURRENT_GROUP + ((port - 8)/2), RTL8367C_PORT0_CURRENT_GROUP_MASK << (RTL8367C_PORT1_CURRENT_GROUP_OFFSET * (port%2)), &value); + if(retVal != RT_ERR_OK) + return retVal; + } + + *current_group = value; + return RT_ERR_OK; +} +/* Function Name: + * rtl8367c_getAsicIGMPGroup + * Description: + * Get IGMP group + * Input: + * idx - Group index (0~255) + * valid - valid bit + * grp - IGMP group + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - Group index is out of range + * Note: + * None + */ +ret_t rtl8367c_getAsicIGMPGroup(rtk_uint32 idx, rtk_uint32 *valid, rtl8367c_igmpgroup *grp) +{ + ret_t retVal; + rtk_uint32 regAddr, regData; + rtk_uint32 i; + rtk_uint32 groupInfo = 0; + + if(idx > RTL8367C_IGMP_MAX_GOUP) + return RT_ERR_OUT_OF_RANGE; + + /* Write ACS_ADR register for data bits */ + regAddr = RTL8367C_TABLE_ACCESS_ADDR_REG; + regData = idx; + retVal = rtl8367c_setAsicReg(regAddr, regData); + if(retVal != RT_ERR_OK) + return retVal; + + /* Write ACS_CMD register */ + regAddr = RTL8367C_TABLE_ACCESS_CTRL_REG; + regData = RTL8367C_TABLE_ACCESS_REG_DATA(TB_OP_READ, TB_TARGET_IGMP_GROUP); + retVal = rtl8367c_setAsicRegBits(regAddr, RTL8367C_TABLE_TYPE_MASK | RTL8367C_COMMAND_TYPE_MASK, regData); + if(retVal != RT_ERR_OK) + return retVal; + + /* Read Data Bits */ + regAddr = RTL8367C_TABLE_ACCESS_RDDATA_BASE; + for(i = 0 ;i <= 1; i++) + { + retVal = rtl8367c_getAsicReg(regAddr, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + groupInfo |= ((regData & 0xFFFF) << (i * 16)); + regAddr ++; + } + + grp->p0_timer = groupInfo & 0x00000007; + grp->p1_timer = (groupInfo >> 3) & 0x00000007; + grp->p2_timer = (groupInfo >> 6) & 0x00000007; + grp->p3_timer = (groupInfo >> 9) & 0x00000007; + grp->p4_timer = (groupInfo >> 12) & 0x00000007; + grp->p5_timer = (groupInfo >> 15) & 0x00000007; + grp->p6_timer = (groupInfo >> 18) & 0x00000007; + grp->p7_timer = (groupInfo >> 21) & 0x00000007; + grp->report_supp_flag = (groupInfo >> 24) & 0x00000001; + grp->p8_timer = (groupInfo >> 25) & 0x00000007; + grp->p9_timer = (groupInfo >> 28) & 0x00000007; + grp->p10_timer = (groupInfo >> 31) & 0x00000001; + + regAddr = RTL8367C_TABLE_ACCESS_RDDATA_BASE + 2; + retVal = rtl8367c_getAsicReg(regAddr, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + grp->p10_timer |= (regData & 0x00000003) << 1; + + /* Valid bit */ + retVal = rtl8367c_getAsicReg(RTL8367C_IGMP_GROUP_USAGE_REG(idx), ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + *valid = ((regData & (0x0001 << (idx %16))) != 0) ? 1 : 0; + + return RT_ERR_OK; +} +/* Function Name: + * rtl8367c_setAsicIpMulticastPortIsoLeaky + * Description: + * Set IP multicast Port Isolation leaky + * Input: + * port - Physical port number (0~7) + * enabled - 1: enabled, 0: disabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_setAsicIpMulticastPortIsoLeaky(rtk_uint32 port, rtk_uint32 enabled) +{ + ret_t retVal; + + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + retVal = rtl8367c_setAsicRegBits(RTL8367C_IPMCAST_PORTISO_LEAKY_REG, (0x0001 << port), enabled); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_getAsicIpMulticastPortIsoLeaky + * Description: + * Get IP multicast Port Isolation leaky + * Input: + * port - Physical port number (0~7) + * enabled - 1: enabled, 0: disabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicIpMulticastPortIsoLeaky(rtk_uint32 port, rtk_uint32 *enabled) +{ + ret_t retVal; + rtk_uint32 regData; + + retVal = rtl8367c_getAsicRegBits(RTL8367C_IPMCAST_PORTISO_LEAKY_REG, (0x0001 << port), ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + *enabled = regData; + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_setAsicIGMPReportLeaveFlood + * Description: + * Set IGMP/MLD Report/Leave flood + * Input: + * flood - 0: Reserved, 1: flooding to router ports, 2: flooding to all ports, 3: flooding to router port or to all ports if there is no router port + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicIGMPReportLeaveFlood(rtk_uint32 flood) +{ + ret_t retVal; + + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_IGMP_MLD_CFG3, RTL8367C_REPORT_LEAVE_FORWARD_MASK, flood); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_getAsicIGMPReportLeaveFlood + * Description: + * Get IGMP/MLD Report/Leave flood + * Input: + * None + * Output: + * pflood - 0: Reserved, 1: flooding to router ports, 2: flooding to all ports, 3: flooding to router port or to all ports if there is no router port + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicIGMPReportLeaveFlood(rtk_uint32 *pFlood) +{ + ret_t retVal; + rtk_uint32 regData; + + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_MLD_CFG3, RTL8367C_REPORT_LEAVE_FORWARD_MASK, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + *pFlood = regData; + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_setAsicIGMPDropLeaveZero + * Description: + * Set the function of droppping Leave packet with group IP = 0.0.0.0 + * Input: + * drop - 1: Drop, 0:Bypass + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicIGMPDropLeaveZero(rtk_uint32 drop) +{ + ret_t retVal; + + retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_IGMP_MLD_CFG1, RTL8367C_DROP_LEAVE_ZERO_OFFSET, drop); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_getAsicIGMPDropLeaveZero + * Description: + * Get the function of droppping Leave packet with group IP = 0.0.0.0 + * Input: + * None + * Output: + * pDrop - 1: Drop, 0:Bypass + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicIGMPDropLeaveZero(rtk_uint32 *pDrop) +{ + ret_t retVal; + rtk_uint32 regData; + + retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_IGMP_MLD_CFG1, RTL8367C_DROP_LEAVE_ZERO_OFFSET, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + *pDrop = regData; + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_setAsicIGMPBypassStormCTRL + * Description: + * Set the function of bypass strom control for IGMP/MLD packet + * Input: + * bypass - 1: Bypass, 0:not bypass + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicIGMPBypassStormCTRL(rtk_uint32 bypass) +{ + ret_t retVal; + + retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_IGMP_MLD_CFG0, RTL8367C_IGMP_MLD_DISCARD_STORM_FILTER_OFFSET, bypass); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_getAsicIGMPBypassStormCTRL + * Description: + * Set the function of bypass strom control for IGMP/MLD packet + * Input: + * None + * Output: + * pBypass - 1: Bypass, 0:not bypass + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicIGMPBypassStormCTRL(rtk_uint32 *pBypass) +{ + ret_t retVal; + rtk_uint32 regData; + + retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_IGMP_MLD_CFG0, RTL8367C_IGMP_MLD_DISCARD_STORM_FILTER_OFFSET, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + *pBypass = regData; + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_setAsicIGMPIsoLeaky + * Description: + * Set Port Isolation leaky for IGMP/MLD packet + * Input: + * leaky - 1: Leaky, 0:not leaky + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicIGMPIsoLeaky(rtk_uint32 leaky) +{ + ret_t retVal; + + retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_IGMP_MLD_CFG0, RTL8367C_IGMP_MLD_PORTISO_LEAKY_OFFSET, leaky); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_getAsicIGMPIsoLeaky + * Description: + * Get Port Isolation leaky for IGMP/MLD packet + * Input: + * Noen + * Output: + * pLeaky - 1: Leaky, 0:not leaky + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicIGMPIsoLeaky(rtk_uint32 *pLeaky) +{ + ret_t retVal; + rtk_uint32 regData; + + retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_IGMP_MLD_CFG0, RTL8367C_IGMP_MLD_PORTISO_LEAKY_OFFSET, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + *pLeaky = regData; + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_setAsicIGMPVLANLeaky + * Description: + * Set VLAN leaky for IGMP/MLD packet + * Input: + * leaky - 1: Leaky, 0:not leaky + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicIGMPVLANLeaky(rtk_uint32 leaky) +{ + ret_t retVal; + + retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_IGMP_MLD_CFG0, RTL8367C_IGMP_MLD_VLAN_LEAKY_OFFSET, leaky); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_getAsicIGMPVLANLeaky + * Description: + * Get VLAN leaky for IGMP/MLD packet + * Input: + * Noen + * Output: + * pLeaky - 1: Leaky, 0:not leaky + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicIGMPVLANLeaky(rtk_uint32 *pLeaky) +{ + ret_t retVal; + rtk_uint32 regData; + + retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_IGMP_MLD_CFG0, RTL8367C_IGMP_MLD_VLAN_LEAKY_OFFSET, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + *pLeaky = regData; + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_setAsicIGMPBypassGroup + * Description: + * Set IGMP/MLD Bypass group + * Input: + * bypassType - Bypass type + * enabled - enabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicIGMPBypassGroup(rtk_uint32 bypassType, rtk_uint32 enabled) +{ + ret_t retVal; + rtk_uint32 offset; + + switch(bypassType) + { + case BYPASS_224_0_0_X: + offset = RTL8367C_IGMP_MLD_IP4_BYPASS_224_0_0_OFFSET; + break; + case BYPASS_224_0_1_X: + offset = RTL8367C_IGMP_MLD_IP4_BYPASS_224_0_1_OFFSET; + break; + case BYPASS_239_255_255_X: + offset = RTL8367C_IGMP_MLD_IP4_BYPASS_239_255_255_OFFSET; + break; + case BYPASS_IPV6_00XX: + offset = RTL8367C_IGMP_MLD_IP6_BYPASS_OFFSET; + break; + default: + return RT_ERR_INPUT; + } + + retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_IGMP_MLD_CFG3, offset, enabled); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_getAsicIGMPBypassGroup + * Description: + * Get IGMP/MLD Bypass group + * Input: + * bypassType - Bypass type + * Output: + * pEnabled - enabled + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicIGMPBypassGroup(rtk_uint32 bypassType, rtk_uint32 *pEnabled) +{ + ret_t retVal; + rtk_uint32 offset; + + switch(bypassType) + { + case BYPASS_224_0_0_X: + offset = RTL8367C_IGMP_MLD_IP4_BYPASS_224_0_0_OFFSET; + break; + case BYPASS_224_0_1_X: + offset = RTL8367C_IGMP_MLD_IP4_BYPASS_224_0_1_OFFSET; + break; + case BYPASS_239_255_255_X: + offset = RTL8367C_IGMP_MLD_IP4_BYPASS_239_255_255_OFFSET; + break; + case BYPASS_IPV6_00XX: + offset = RTL8367C_IGMP_MLD_IP6_BYPASS_OFFSET; + break; + default: + return RT_ERR_INPUT; + } + + retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_IGMP_MLD_CFG3, offset, pEnabled); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_igmp.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_igmp.h new file mode 100644 index 00000000..ab4f1419 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_igmp.h @@ -0,0 +1,134 @@ +#ifndef _RTL8367C_ASICDRV_IGMP_H_ +#define _RTL8367C_ASICDRV_IGMP_H_ + +/****************************************************************/ +/* Header File inclusion */ +/****************************************************************/ +#include + +#define RTL8367C_MAX_LEAVE_TIMER (7) +#define RTL8367C_MAX_QUERY_INT (0xFFFF) +#define RTL8367C_MAX_ROB_VAR (7) + +#define RTL8367C_IGMP_GOUP_NO (256) +#define RTL8367C_IGMP_MAX_GOUP (0xFF) +#define RTL8367C_IGMP_GRP_BLEN (3) +#define RTL8367C_ROUTER_PORT_INVALID (0xF) + +enum RTL8367C_IGMPTABLE_FULL_OP +{ + TABLE_FULL_FORWARD = 0, + TABLE_FULL_DROP, + TABLE_FULL_TRAP, + TABLE_FULL_OP_END +}; + +enum RTL8367C_CRC_ERR_OP +{ + CRC_ERR_DROP = 0, + CRC_ERR_TRAP, + CRC_ERR_FORWARD, + CRC_ERR_OP_END +}; + +enum RTL8367C_IGMP_MLD_PROTOCOL_OP +{ + PROTOCOL_OP_ASIC = 0, + PROTOCOL_OP_FLOOD, + PROTOCOL_OP_TRAP, + PROTOCOL_OP_DROP, + PROTOCOL_OP_END +}; + +enum RTL8367C_IGMP_MLD_BYPASS_GROUP +{ + BYPASS_224_0_0_X = 0, + BYPASS_224_0_1_X, + BYPASS_239_255_255_X, + BYPASS_IPV6_00XX, + BYPASS_GROUP_END +}; + +typedef struct +{ + rtk_uint32 p0_timer; + rtk_uint32 p1_timer; + rtk_uint32 p2_timer; + rtk_uint32 p3_timer; + rtk_uint32 p4_timer; + rtk_uint32 p5_timer; + rtk_uint32 p6_timer; + rtk_uint32 p7_timer; + rtk_uint32 p8_timer; + rtk_uint32 p9_timer; + rtk_uint32 p10_timer; + rtk_uint32 report_supp_flag; + +}rtl8367c_igmpgroup; + + +ret_t rtl8367c_setAsicIgmp(rtk_uint32 enabled); +ret_t rtl8367c_getAsicIgmp(rtk_uint32 *pEnabled); +ret_t rtl8367c_setAsicIpMulticastVlanLeaky(rtk_uint32 port, rtk_uint32 enabled ); +ret_t rtl8367c_getAsicIpMulticastVlanLeaky(rtk_uint32 port, rtk_uint32 *pEnabled ); +ret_t rtl8367c_setAsicIGMPTableFullOP(rtk_uint32 operation); +ret_t rtl8367c_getAsicIGMPTableFullOP(rtk_uint32 *pOperation); +ret_t rtl8367c_setAsicIGMPCRCErrOP(rtk_uint32 operation); +ret_t rtl8367c_getAsicIGMPCRCErrOP(rtk_uint32 *pOperation); +ret_t rtl8367c_setAsicIGMPFastLeaveEn(rtk_uint32 enabled); +ret_t rtl8367c_getAsicIGMPFastLeaveEn(rtk_uint32 *pEnabled); +ret_t rtl8367c_setAsicIGMPLeaveTimer(rtk_uint32 leave_timer); +ret_t rtl8367c_getAsicIGMPLeaveTimer(rtk_uint32 *pLeave_timer); +ret_t rtl8367c_setAsicIGMPQueryInterval(rtk_uint32 interval); +ret_t rtl8367c_getAsicIGMPQueryInterval(rtk_uint32 *pInterval); +ret_t rtl8367c_setAsicIGMPRobVar(rtk_uint32 rob_var); +ret_t rtl8367c_getAsicIGMPRobVar(rtk_uint32 *pRob_var); +ret_t rtl8367c_setAsicIGMPStaticRouterPort(rtk_uint32 pmsk); +ret_t rtl8367c_getAsicIGMPStaticRouterPort(rtk_uint32 *pMsk); +ret_t rtl8367c_setAsicIGMPAllowDynamicRouterPort(rtk_uint32 pmsk); +ret_t rtl8367c_getAsicIGMPAllowDynamicRouterPort(rtk_uint32 *pPmsk); +ret_t rtl8367c_getAsicIGMPdynamicRouterPort1(rtk_uint32 *pPort, rtk_uint32 *pTimer); +ret_t rtl8367c_getAsicIGMPdynamicRouterPort2(rtk_uint32 *pPort, rtk_uint32 *pTimer); +ret_t rtl8367c_setAsicIGMPSuppression(rtk_uint32 report_supp_enabled, rtk_uint32 leave_supp_enabled); +ret_t rtl8367c_getAsicIGMPSuppression(rtk_uint32 *pReport_supp_enabled, rtk_uint32 *pLeave_supp_enabled); +ret_t rtl8367c_setAsicIGMPQueryRX(rtk_uint32 port, rtk_uint32 allow_query); +ret_t rtl8367c_getAsicIGMPQueryRX(rtk_uint32 port, rtk_uint32 *pAllow_query); +ret_t rtl8367c_setAsicIGMPReportRX(rtk_uint32 port, rtk_uint32 allow_report); +ret_t rtl8367c_getAsicIGMPReportRX(rtk_uint32 port, rtk_uint32 *pAllow_report); +ret_t rtl8367c_setAsicIGMPLeaveRX(rtk_uint32 port, rtk_uint32 allow_leave); +ret_t rtl8367c_getAsicIGMPLeaveRX(rtk_uint32 port, rtk_uint32 *pAllow_leave); +ret_t rtl8367c_setAsicIGMPMRPRX(rtk_uint32 port, rtk_uint32 allow_mrp); +ret_t rtl8367c_getAsicIGMPMRPRX(rtk_uint32 port, rtk_uint32 *pAllow_mrp); +ret_t rtl8367c_setAsicIGMPMcDataRX(rtk_uint32 port, rtk_uint32 allow_mcdata); +ret_t rtl8367c_getAsicIGMPMcDataRX(rtk_uint32 port, rtk_uint32 *pAllow_mcdata); +ret_t rtl8367c_setAsicIGMPv1Opeartion(rtk_uint32 port, rtk_uint32 igmpv1_op); +ret_t rtl8367c_getAsicIGMPv1Opeartion(rtk_uint32 port, rtk_uint32 *pIgmpv1_op); +ret_t rtl8367c_setAsicIGMPv2Opeartion(rtk_uint32 port, rtk_uint32 igmpv2_op); +ret_t rtl8367c_getAsicIGMPv2Opeartion(rtk_uint32 port, rtk_uint32 *pIgmpv2_op); +ret_t rtl8367c_setAsicIGMPv3Opeartion(rtk_uint32 port, rtk_uint32 igmpv3_op); +ret_t rtl8367c_getAsicIGMPv3Opeartion(rtk_uint32 port, rtk_uint32 *pIgmpv3_op); +ret_t rtl8367c_setAsicMLDv1Opeartion(rtk_uint32 port, rtk_uint32 mldv1_op); +ret_t rtl8367c_getAsicMLDv1Opeartion(rtk_uint32 port, rtk_uint32 *pMldv1_op); +ret_t rtl8367c_setAsicMLDv2Opeartion(rtk_uint32 port, rtk_uint32 mldv2_op); +ret_t rtl8367c_getAsicMLDv2Opeartion(rtk_uint32 port, rtk_uint32 *pMldv2_op); +ret_t rtl8367c_setAsicIGMPPortMAXGroup(rtk_uint32 port, rtk_uint32 max_group); +ret_t rtl8367c_getAsicIGMPPortMAXGroup(rtk_uint32 port, rtk_uint32 *pMax_group); +ret_t rtl8367c_getAsicIGMPPortCurrentGroup(rtk_uint32 port, rtk_uint32 *pCurrent_group); +ret_t rtl8367c_getAsicIGMPGroup(rtk_uint32 idx, rtk_uint32 *pValid, rtl8367c_igmpgroup *pGrp); +ret_t rtl8367c_setAsicIpMulticastPortIsoLeaky(rtk_uint32 port, rtk_uint32 enabled); +ret_t rtl8367c_getAsicIpMulticastPortIsoLeaky(rtk_uint32 port, rtk_uint32 *pEnabled); +ret_t rtl8367c_setAsicIGMPReportLeaveFlood(rtk_uint32 flood); +ret_t rtl8367c_getAsicIGMPReportLeaveFlood(rtk_uint32 *pFlood); +ret_t rtl8367c_setAsicIGMPDropLeaveZero(rtk_uint32 drop); +ret_t rtl8367c_getAsicIGMPDropLeaveZero(rtk_uint32 *pDrop); +ret_t rtl8367c_setAsicIGMPBypassStormCTRL(rtk_uint32 bypass); +ret_t rtl8367c_getAsicIGMPBypassStormCTRL(rtk_uint32 *pBypass); +ret_t rtl8367c_setAsicIGMPIsoLeaky(rtk_uint32 leaky); +ret_t rtl8367c_getAsicIGMPIsoLeaky(rtk_uint32 *pLeaky); +ret_t rtl8367c_setAsicIGMPVLANLeaky(rtk_uint32 leaky); +ret_t rtl8367c_getAsicIGMPVLANLeaky(rtk_uint32 *pLeaky); +ret_t rtl8367c_setAsicIGMPBypassGroup(rtk_uint32 bypassType, rtk_uint32 enabled); +ret_t rtl8367c_getAsicIGMPBypassGroup(rtk_uint32 bypassType, rtk_uint32 *pEnabled); + +#endif /*#ifndef _RTL8367C_ASICDRV_IGMP_H_*/ + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_inbwctrl.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_inbwctrl.c new file mode 100644 index 00000000..2d4407e9 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_inbwctrl.c @@ -0,0 +1,166 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTL8367C switch high-level API for RTL8367C + * Feature : Ingress bandwidth control related functions + * + */ +#include +/* Function Name: + * rtl8367c_setAsicPortIngressBandwidth + * Description: + * Set per-port total ingress bandwidth + * Input: + * port - Physical port number (0~7) + * bandwidth - The total ingress bandwidth (unit: 8Kbps), 0x1FFFF:disable + * preifg - Include preamble and IFG, 0:Exclude, 1:Include + * enableFC - Action when input rate exceeds. 0: Drop 1: Flow Control + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * RT_ERR_OUT_OF_RANGE - input parameter out of range + * Note: + * None + */ +ret_t rtl8367c_setAsicPortIngressBandwidth(rtk_uint32 port, rtk_uint32 bandwidth, rtk_uint32 preifg, rtk_uint32 enableFC) +{ + ret_t retVal; + rtk_uint32 regData; + rtk_uint32 regAddr; + + /* Invalid input parameter */ + if(port >= RTL8367C_PORTNO) + return RT_ERR_PORT_ID; + + if(bandwidth > RTL8367C_QOS_GRANULARTY_MAX) + return RT_ERR_OUT_OF_RANGE; + + regAddr = RTL8367C_INGRESSBW_PORT_RATE_LSB_REG(port); + regData = bandwidth & RTL8367C_QOS_GRANULARTY_LSB_MASK; + retVal = rtl8367c_setAsicReg(regAddr, regData); + if(retVal != RT_ERR_OK) + return retVal; + + regAddr += 1; + regData = (bandwidth & RTL8367C_QOS_GRANULARTY_MSB_MASK) >> RTL8367C_QOS_GRANULARTY_MSB_OFFSET; + retVal = rtl8367c_setAsicRegBits(regAddr, RTL8367C_INGRESSBW_PORT0_RATE_CTRL1_INGRESSBW_RATE16_MASK, regData); + if(retVal != RT_ERR_OK) + return retVal; + + regAddr = RTL8367C_PORT_MISC_CFG_REG(port); + retVal = rtl8367c_setAsicRegBit(regAddr, RTL8367C_PORT0_MISC_CFG_INGRESSBW_IFG_OFFSET, preifg); + if(retVal != RT_ERR_OK) + return retVal; + + regAddr = RTL8367C_PORT_MISC_CFG_REG(port); + retVal = rtl8367c_setAsicRegBit(regAddr, RTL8367C_PORT0_MISC_CFG_INGRESSBW_FLOWCTRL_OFFSET, enableFC); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} +/* Function Name: + * rtl8367c_getAsicPortIngressBandwidth + * Description: + * Get per-port total ingress bandwidth + * Input: + * port - Physical port number (0~7) + * pBandwidth - The total ingress bandwidth (unit: 8Kbps), 0x1FFFF:disable + * pPreifg - Include preamble and IFG, 0:Exclude, 1:Include + * pEnableFC - Action when input rate exceeds. 0: Drop 1: Flow Control + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_getAsicPortIngressBandwidth(rtk_uint32 port, rtk_uint32* pBandwidth, rtk_uint32* pPreifg, rtk_uint32* pEnableFC) +{ + ret_t retVal; + rtk_uint32 regData; + rtk_uint32 regAddr; + + /* Invalid input parameter */ + if(port >= RTL8367C_PORTNO) + return RT_ERR_PORT_ID; + + regAddr = RTL8367C_INGRESSBW_PORT_RATE_LSB_REG(port); + retVal = rtl8367c_getAsicReg(regAddr, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + *pBandwidth = regData; + + regAddr += 1; + retVal = rtl8367c_getAsicRegBits(regAddr, RTL8367C_INGRESSBW_PORT0_RATE_CTRL1_INGRESSBW_RATE16_MASK, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + *pBandwidth |= (regData << RTL8367C_QOS_GRANULARTY_MSB_OFFSET); + + regAddr = RTL8367C_PORT_MISC_CFG_REG(port); + retVal = rtl8367c_getAsicRegBit(regAddr, RTL8367C_PORT0_MISC_CFG_INGRESSBW_IFG_OFFSET, pPreifg); + if(retVal != RT_ERR_OK) + return retVal; + + regAddr = RTL8367C_PORT_MISC_CFG_REG(port); + retVal = rtl8367c_getAsicRegBit(regAddr, RTL8367C_PORT0_MISC_CFG_INGRESSBW_FLOWCTRL_OFFSET, pEnableFC); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} +/* Function Name: + * rtl8367c_setAsicPortIngressBandwidthBypass + * Description: + * Set ingress bandwidth control bypasss 8899, RMA 01-80-C2-00-00-xx and IGMP + * Input: + * enabled - 1: enabled, 0: disabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicPortIngressBandwidthBypass(rtk_uint32 enabled) +{ + return rtl8367c_setAsicRegBit(RTL8367C_REG_SW_DUMMY0, RTL8367C_INGRESSBW_BYPASS_EN_OFFSET, enabled); +} +/* Function Name: + * rtl8367c_getAsicPortIngressBandwidthBypass + * Description: + * Set ingress bandwidth control bypasss 8899, RMA 01-80-C2-00-00-xx and IGMP + * Input: + * pEnabled - 1: enabled, 0: disabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicPortIngressBandwidthBypass(rtk_uint32* pEnabled) +{ + return rtl8367c_getAsicRegBit(RTL8367C_REG_SW_DUMMY0, RTL8367C_INGRESSBW_BYPASS_EN_OFFSET, pEnabled); +} + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_inbwctrl.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_inbwctrl.h new file mode 100644 index 00000000..4abaf3c8 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_inbwctrl.h @@ -0,0 +1,13 @@ +#ifndef _RTL8367C_ASICDRV_INBWCTRL_H_ +#define _RTL8367C_ASICDRV_INBWCTRL_H_ + +#include + +extern ret_t rtl8367c_setAsicPortIngressBandwidth(rtk_uint32 port, rtk_uint32 bandwidth, rtk_uint32 preifg, rtk_uint32 enableFC); +extern ret_t rtl8367c_getAsicPortIngressBandwidth(rtk_uint32 port, rtk_uint32* pBandwidth, rtk_uint32* pPreifg, rtk_uint32* pEnableFC ); +extern ret_t rtl8367c_setAsicPortIngressBandwidthBypass(rtk_uint32 enabled); +extern ret_t rtl8367c_getAsicPortIngressBandwidthBypass(rtk_uint32* pEnabled); + + +#endif /*_RTL8367C_ASICDRV_INBWCTRL_H_*/ + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_interrupt.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_interrupt.c new file mode 100644 index 00000000..9999afde --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_interrupt.c @@ -0,0 +1,207 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTL8367C switch high-level API for RTL8367C + * Feature : Interrupt related functions + * + */ +#include +/* Function Name: + * rtl8367c_setAsicInterruptPolarity + * Description: + * Set interrupt trigger polarity + * Input: + * polarity - 0:pull high 1: pull low + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicInterruptPolarity(rtk_uint32 polarity) +{ + return rtl8367c_setAsicRegBit(RTL8367C_REG_INTR_CTRL, RTL8367C_INTR_CTRL_OFFSET, polarity); +} +/* Function Name: + * rtl8367c_getAsicInterruptPolarity + * Description: + * Get interrupt trigger polarity + * Input: + * pPolarity - 0:pull high 1: pull low + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicInterruptPolarity(rtk_uint32* pPolarity) +{ + return rtl8367c_getAsicRegBit(RTL8367C_REG_INTR_CTRL, RTL8367C_INTR_CTRL_OFFSET, pPolarity); +} +/* Function Name: + * rtl8367c_setAsicInterruptMask + * Description: + * Set interrupt enable mask + * Input: + * imr - Interrupt mask + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicInterruptMask(rtk_uint32 imr) +{ + return rtl8367c_setAsicReg(RTL8367C_REG_INTR_IMR, imr); +} +/* Function Name: + * rtl8367c_getAsicInterruptMask + * Description: + * Get interrupt enable mask + * Input: + * pImr - Interrupt mask + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicInterruptMask(rtk_uint32* pImr) +{ + return rtl8367c_getAsicReg(RTL8367C_REG_INTR_IMR, pImr); +} +/* Function Name: + * rtl8367c_setAsicInterruptMask + * Description: + * Clear interrupt enable mask + * Input: + * ims - Interrupt status mask + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * This API can be used to clear ASIC interrupt status and register will be cleared by writting 1. + * [0]:Link change, + * [1]:Share meter exceed, + * [2]:Learn number overed, + * [3]:Speed Change, + * [4]:Tx special congestion + * [5]:1 second green feature + * [6]:loop detection + * [7]:interrupt from 8051 + * [8]:Cable diagnostic finish + * [9]:ACL action interrupt trigger + * [11]: Silent Start + */ +ret_t rtl8367c_setAsicInterruptStatus(rtk_uint32 ims) +{ + return rtl8367c_setAsicReg(RTL8367C_REG_INTR_IMS, ims); +} +/* Function Name: + * rtl8367c_getAsicInterruptStatus + * Description: + * Get interrupt enable mask + * Input: + * pIms - Interrupt status mask + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicInterruptStatus(rtk_uint32* pIms) +{ + return rtl8367c_getAsicReg(RTL8367C_REG_INTR_IMS, pIms); +} +/* Function Name: + * rtl8367c_setAsicInterruptRelatedStatus + * Description: + * Clear interrupt status + * Input: + * type - per port Learn over, per-port speed change, per-port special congest, share meter exceed status + * status - exceed status, write 1 to clear + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - input parameter out of range + * Note: + * None + */ +ret_t rtl8367c_setAsicInterruptRelatedStatus(rtk_uint32 type, rtk_uint32 status) +{ + CONST rtk_uint32 indicatorAddress[INTRST_END] = {RTL8367C_REG_LEARN_OVER_INDICATOR, + RTL8367C_REG_SPEED_CHANGE_INDICATOR, + RTL8367C_REG_SPECIAL_CONGEST_INDICATOR, + RTL8367C_REG_PORT_LINKDOWN_INDICATOR, + RTL8367C_REG_PORT_LINKUP_INDICATOR, + RTL8367C_REG_METER_OVERRATE_INDICATOR0, + RTL8367C_REG_METER_OVERRATE_INDICATOR1, + RTL8367C_REG_RLDP_LOOPED_INDICATOR, + RTL8367C_REG_RLDP_RELEASED_INDICATOR, + RTL8367C_REG_SYSTEM_LEARN_OVER_INDICATOR}; + + if(type >= INTRST_END ) + return RT_ERR_OUT_OF_RANGE; + + return rtl8367c_setAsicReg(indicatorAddress[type], status); +} +/* Function Name: + * rtl8367c_getAsicInterruptRelatedStatus + * Description: + * Get interrupt status + * Input: + * type - per port Learn over, per-port speed change, per-port special congest, share meter exceed status + * pStatus - exceed status, write 1 to clear + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - input parameter out of range + * Note: + * None + */ +ret_t rtl8367c_getAsicInterruptRelatedStatus(rtk_uint32 type, rtk_uint32* pStatus) +{ + CONST rtk_uint32 indicatorAddress[INTRST_END] = {RTL8367C_REG_LEARN_OVER_INDICATOR, + RTL8367C_REG_SPEED_CHANGE_INDICATOR, + RTL8367C_REG_SPECIAL_CONGEST_INDICATOR, + RTL8367C_REG_PORT_LINKDOWN_INDICATOR, + RTL8367C_REG_PORT_LINKUP_INDICATOR, + RTL8367C_REG_METER_OVERRATE_INDICATOR0, + RTL8367C_REG_METER_OVERRATE_INDICATOR1, + RTL8367C_REG_RLDP_LOOPED_INDICATOR, + RTL8367C_REG_RLDP_RELEASED_INDICATOR, + RTL8367C_REG_SYSTEM_LEARN_OVER_INDICATOR}; + + if(type >= INTRST_END ) + return RT_ERR_OUT_OF_RANGE; + + return rtl8367c_getAsicReg(indicatorAddress[type], pStatus); +} + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_interrupt.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_interrupt.h new file mode 100644 index 00000000..e4bd52c7 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_interrupt.h @@ -0,0 +1,49 @@ +#ifndef _RTL8367C_ASICDRV_INTERRUPT_H_ +#define _RTL8367C_ASICDRV_INTERRUPT_H_ + +#include + +typedef enum RTL8367C_INTR_IMRS_E +{ + IMRS_LINK_CHANGE, + IMRS_METER_EXCEED, + IMRS_L2_LEARN, + IMRS_SPEED_CHANGE, + IMRS_SPECIAL_CONGESTION, + IMRS_GREEN_FEATURE, + IMRS_LOOP_DETECTION, + IMRS_8051, + IMRS_CABLE_DIAG, + IMRS_ACL, + IMRS_RESERVED, /* Unused */ + IMRS_SLIENT, + IMRS_END, +}RTL8367C_INTR_IMRS; + +typedef enum RTL8367C_INTR_INDICATOR_E +{ + INTRST_L2_LEARN = 0, + INTRST_SPEED_CHANGE, + INTRST_SPECIAL_CONGESTION, + INTRST_PORT_LINKDOWN, + INTRST_PORT_LINKUP, + INTRST_METER0_15, + INTRST_METER16_31, + INTRST_RLDP_LOOPED, + INTRST_RLDP_RELEASED, + INTRST_SYS_LEARN, + INTRST_END, +}RTL8367C_INTR_INDICATOR; + +extern ret_t rtl8367c_setAsicInterruptPolarity(rtk_uint32 polarity); +extern ret_t rtl8367c_getAsicInterruptPolarity(rtk_uint32* pPolarity); +extern ret_t rtl8367c_setAsicInterruptMask(rtk_uint32 imr); +extern ret_t rtl8367c_getAsicInterruptMask(rtk_uint32* pImr); +extern ret_t rtl8367c_setAsicInterruptStatus(rtk_uint32 ims); +extern ret_t rtl8367c_getAsicInterruptStatus(rtk_uint32* pIms); +extern ret_t rtl8367c_setAsicInterruptRelatedStatus(rtk_uint32 type, rtk_uint32 status); +extern ret_t rtl8367c_getAsicInterruptRelatedStatus(rtk_uint32 type, rtk_uint32* pStatus); + + +#endif /*#ifndef _RTL8367C_ASICDRV_INTERRUPT_H_*/ + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_led.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_led.c new file mode 100644 index 00000000..70b76a8f --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_led.c @@ -0,0 +1,819 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTL8367C switch high-level API for RTL8367C + * Feature : LED related functions + * + */ +#include +/* Function Name: + * rtl8367c_setAsicLedIndicateInfoConfig + * Description: + * Set Leds indicated information mode + * Input: + * ledno - LED group number. There are 1 to 1 led mapping to each port in each led group + * config - Support 16 types configuration + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - input parameter out of range + * Note: + * The API can set LED indicated information configuration for each LED group with 1 to 1 led mapping to each port. + * Definition LED Statuses Description + * 0000 LED_Off LED pin Tri-State. + * 0001 Dup/Col Collision, Full duplex Indicator. Blinking every 43ms when collision happens. Low for full duplex, and high for half duplex mode. + * 0010 Link/Act Link, Activity Indicator. Low for link established. Link/Act Blinks every 43ms when the corresponding port is transmitting or receiving. + * 0011 Spd1000 1000Mb/s Speed Indicator. Low for 1000Mb/s. + * 0100 Spd100 100Mb/s Speed Indicator. Low for 100Mb/s. + * 0101 Spd10 10Mb/s Speed Indicator. Low for 10Mb/s. + * 0110 Spd1000/Act 1000Mb/s Speed/Activity Indicator. Low for 1000Mb/s. Blinks every 43ms when the corresponding port is transmitting or receiving. + * 0111 Spd100/Act 100Mb/s Speed/Activity Indicator. Low for 100Mb/s. Blinks every 43ms when the corresponding port is transmitting or receiving. + * 1000 Spd10/Act 10Mb/s Speed/Activity Indicator. Low for 10Mb/s. Blinks every 43ms when the corresponding port is transmitting or receiving. + * 1001 Spd100 (10)/Act 10/100Mb/s Speed/Activity Indicator. Low for 10/100Mb/s. Blinks every 43ms when the corresponding port is transmitting or receiving. + * 1010 Fiber Fiber link Indicator. Low for Fiber. + * 1011 Fault Auto-negotiation Fault Indicator. Low for Fault. + * 1100 Link/Rx Link, Activity Indicator. Low for link established. Link/Rx Blinks every 43ms when the corresponding port is transmitting. + * 1101 Link/Tx Link, Activity Indicator. Low for link established. Link/Tx Blinks every 43ms when the corresponding port is receiving. + * 1110 Master Link on Master Indicator. Low for link Master established. + * 1111 LED_Force Force LED output, LED output value reference + */ +ret_t rtl8367c_setAsicLedIndicateInfoConfig(rtk_uint32 ledno, rtk_uint32 config) +{ + ret_t retVal; + CONST rtk_uint16 bits[RTL8367C_LEDGROUPNO] = {RTL8367C_LED0_CFG_MASK, RTL8367C_LED1_CFG_MASK, RTL8367C_LED2_CFG_MASK}; + + if(ledno >= RTL8367C_LEDGROUPNO) + return RT_ERR_OUT_OF_RANGE; + + if(config >= LEDCONF_END) + return RT_ERR_OUT_OF_RANGE; + + retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_LED_CONFIGURATION, RTL8367C_LED_CONFIG_SEL_OFFSET, 0); + if(retVal != RT_ERR_OK) + return retVal; + + return rtl8367c_setAsicRegBits(RTL8367C_REG_LED_CONFIGURATION, bits[ledno], config); +} +/* Function Name: + * rtl8367c_getAsicLedIndicateInfoConfig + * Description: + * Get Leds indicated information mode + * Input: + * ledno - LED group number. There are 1 to 1 led mapping to each port in each led group + * pConfig - Support 16 types configuration + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - input parameter out of range + * Note: + * None + */ +ret_t rtl8367c_getAsicLedIndicateInfoConfig(rtk_uint32 ledno, rtk_uint32* pConfig) +{ + CONST rtk_uint16 bits[RTL8367C_LEDGROUPNO]= {RTL8367C_LED0_CFG_MASK, RTL8367C_LED1_CFG_MASK, RTL8367C_LED2_CFG_MASK}; + + if(ledno >= RTL8367C_LEDGROUPNO) + return RT_ERR_OUT_OF_RANGE; + + /* Get register value */ + return rtl8367c_getAsicRegBits(RTL8367C_REG_LED_CONFIGURATION, bits[ledno], pConfig); +} +/* Function Name: + * rtl8367c_setAsicLedGroupMode + * Description: + * Set Led Group mode + * Input: + * mode - LED mode + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - input parameter out of range + * Note: + * None + */ +ret_t rtl8367c_setAsicLedGroupMode(rtk_uint32 mode) +{ + ret_t retVal; + + /* Invalid input parameter */ + if(mode >= RTL8367C_LED_MODE_END) + return RT_ERR_OUT_OF_RANGE; + + retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_LED_CONFIGURATION, RTL8367C_LED_CONFIG_SEL_OFFSET, 1); + if(retVal != RT_ERR_OK) + return retVal; + + return rtl8367c_setAsicRegBits(RTL8367C_REG_LED_CONFIGURATION, RTL8367C_DATA_LED_MASK, mode); +} +/* Function Name: + * rtl8367c_getAsicLedGroupMode + * Description: + * Get Led Group mode + * Input: + * pMode - LED mode + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicLedGroupMode(rtk_uint32* pMode) +{ + ret_t retVal; + rtk_uint32 regData; + + retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_LED_CONFIGURATION, RTL8367C_LED_CONFIG_SEL_OFFSET, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + if(regData!=1) + return RT_ERR_FAILED; + + return rtl8367c_getAsicRegBits(RTL8367C_REG_LED_CONFIGURATION, RTL8367C_DATA_LED_MASK, pMode); +} +/* Function Name: + * rtl8367c_setAsicForceLeds + * Description: + * Set group LED mode + * Input: + * port - Physical port number (0~7) + * group - LED group number + * mode - LED mode + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * RT_ERR_OUT_OF_RANGE - input parameter out of range + * Note: + * None + */ +ret_t rtl8367c_setAsicForceLed(rtk_uint32 port, rtk_uint32 group, rtk_uint32 mode) +{ + rtk_uint16 regAddr; + ret_t retVal; + + /* Invalid input parameter */ + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + if(group >= RTL8367C_LEDGROUPNO) + return RT_ERR_OUT_OF_RANGE; + + if(mode >= LEDFORCEMODE_END) + return RT_ERR_OUT_OF_RANGE; + /* Set Related Registers */ + if(port < 8){ + regAddr = RTL8367C_LED_FORCE_MODE_BASE + (group << 1); + if((retVal = rtl8367c_setAsicRegBits(regAddr, 0x3 << (port * 2), mode)) != RT_ERR_OK) + return retVal; + }else if(port >= 8){ + regAddr = RTL8367C_REG_CPU_FORCE_LED0_CFG1 + (group << 1); + if((retVal = rtl8367c_setAsicRegBits(regAddr, 0x3 << ((port-8) * 2), mode)) != RT_ERR_OK) + return retVal; + } + + return RT_ERR_OK; +} +/* Function Name: + * rtl8367c_getAsicForceLed + * Description: + * Get group LED mode + * Input: + * port - Physical port number (0~7) + * group - LED group number + * pMode - LED mode + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * RT_ERR_OUT_OF_RANGE - input parameter out of range + * Note: + * None + */ +ret_t rtl8367c_getAsicForceLed(rtk_uint32 port, rtk_uint32 group, rtk_uint32* pMode) +{ + rtk_uint16 regAddr; + ret_t retVal; + + /* Invalid input parameter */ + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + if(group >= RTL8367C_LEDGROUPNO) + return RT_ERR_INPUT; + + /* Get Related Registers */ + if(port < 8){ + regAddr = RTL8367C_LED_FORCE_MODE_BASE + (group << 1); + if((retVal = rtl8367c_getAsicRegBits(regAddr, 0x3 << (port * 2), pMode)) != RT_ERR_OK) + return retVal; + }else if(port >= 8){ + regAddr = RTL8367C_REG_CPU_FORCE_LED0_CFG1 + (group << 1); + if((retVal = rtl8367c_getAsicRegBits(regAddr, 0x3 << ((port-8) * 2), pMode)) != RT_ERR_OK) + return retVal; + } + + return RT_ERR_OK; +} +/* Function Name: + * rtl8367c_setAsicForceGroupLed + * Description: + * Turn on/off Led of all ports + * Input: + * group - LED group number + * mode - 0b00:normal mode, 0b01:force blink, 0b10:force off, 0b11:force on + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - input parameter out of range + * Note: + * None + */ +ret_t rtl8367c_setAsicForceGroupLed(rtk_uint32 groupmask, rtk_uint32 mode) +{ + ret_t retVal; + rtk_uint32 i,bitmask; + CONST rtk_uint16 bits[3]= {0x0004,0x0010,0x0040}; + + /* Invalid input parameter */ + if(groupmask > RTL8367C_LEDGROUPMASK) + return RT_ERR_OUT_OF_RANGE; + + if(mode >= LEDFORCEMODE_END) + return RT_ERR_OUT_OF_RANGE; + + bitmask = 0; + for(i = 0; i < RTL8367C_LEDGROUPNO; i++) + { + if(groupmask & (1 << i)) + { + bitmask = bitmask | bits[i]; + } + + } + + retVal = rtl8367c_setAsicRegBits(RTL8367C_LED_FORCE_CTRL, RTL8367C_LED_FORCE_MODE_MASK, bitmask); + + retVal = rtl8367c_setAsicRegBits(RTL8367C_LED_FORCE_CTRL, RTL8367C_FORCE_MODE_MASK, mode); + + if(LEDFORCEMODE_NORMAL == mode) + retVal = rtl8367c_setAsicRegBits(RTL8367C_LED_FORCE_CTRL, RTL8367C_LED_FORCE_MODE_MASK, 0); + + return retVal; +} +/* Function Name: + * rtl8367c_getAsicForceGroupLed + * Description: + * Turn on/off Led of all ports + * Input: + * group - LED group number + * pMode - 0b00:normal mode, 0b01:force blink, 0b10:force off, 0b11:force on + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicForceGroupLed(rtk_uint32* groupmask, rtk_uint32* pMode) +{ + ret_t retVal; + rtk_uint32 i,regData; + CONST rtk_uint16 bits[3] = {0x0004,0x0010,0x0040}; + + /* Get Related Registers */ + if((retVal = rtl8367c_getAsicRegBits(RTL8367C_LED_FORCE_CTRL, RTL8367C_LED_FORCE_MODE_MASK, ®Data)) != RT_ERR_OK) + return retVal; + + for(i = 0; i< RTL8367C_LEDGROUPNO; i++) + { + if((regData & bits[i]) == bits[i]) + { + *groupmask = *groupmask | (1 << i); + } + } + + return rtl8367c_getAsicRegBits(RTL8367C_LED_FORCE_CTRL, RTL8367C_FORCE_MODE_MASK, pMode); +} +/* Function Name: + * rtl8367c_setAsicLedBlinkRate + * Description: + * Set led blinking rate at mode 0 to mode 3 + * Input: + * blinkRate - Support 6 blink rates + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - input parameter out of range + * Note: + * The API configure LED blinking rate: + * - LED_BLINKRATE_32MS + * - LED_BLINKRATE_64MS, + * - LED_BLINKRATE_128MS, + * - LED_BLINKRATE_256MS, + * - LED_BLINKRATE_512MS, + * - LED_BLINKRATE_1024MS, + * - LED_BLINKRATE_48MS, + * - LED_BLINKRATE_96MS, + */ +ret_t rtl8367c_setAsicLedBlinkRate(rtk_uint32 blinkRate) +{ + if(blinkRate >= LEDBLINKRATE_END) + return RT_ERR_OUT_OF_RANGE; + + return rtl8367c_setAsicRegBits(RTL8367C_REG_LED_MODE, RTL8367C_SEL_LEDRATE_MASK, blinkRate); +} +/* Function Name: + * rtl8367c_getAsicLedBlinkRate + * Description: + * Get led blinking rate at mode 0 to mode 3 + * Input: + * pBlinkRate - Support 6 blink rates + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * The API get LED blinking rate: + * - LED_BLINKRATE_32MS + * - LED_BLINKRATE_64MS, + * - LED_BLINKRATE_128MS, + * - LED_BLINKRATE_256MS, + * - LED_BLINKRATE_512MS, + * - LED_BLINKRATE_1024MS, + * - LED_BLINKRATE_48MS, + * - LED_BLINKRATE_96MS, + */ +ret_t rtl8367c_getAsicLedBlinkRate(rtk_uint32* pBlinkRate) +{ + return rtl8367c_getAsicRegBits(RTL8367C_REG_LED_MODE, RTL8367C_SEL_LEDRATE_MASK, pBlinkRate); +} +/* Function Name: + * rtl8367c_setAsicLedForceBlinkRate + * Description: + * Set LEd blinking rate for force mode led + * Input: + * blinkRate - Support 6 blink rates + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - input parameter out of range + * Note: + * None + */ +ret_t rtl8367c_setAsicLedForceBlinkRate(rtk_uint32 blinkRate) +{ + if(blinkRate >= LEDFORCERATE_END) + return RT_ERR_OUT_OF_RANGE; + + return rtl8367c_setAsicRegBits(RTL8367C_REG_LED_MODE, RTL8367C_FORCE_RATE_MASK, blinkRate); +} +/* Function Name: + * rtl8367c_getAsicLedForceBlinkRate + * Description: + * Get LED blinking rate for force mode led + * Input: + * pBlinkRate - Support 6 blink rates + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicLedForceBlinkRate(rtk_uint32* pBlinkRate) +{ + return rtl8367c_getAsicRegBits(RTL8367C_REG_LED_MODE, RTL8367C_FORCE_RATE_MASK, pBlinkRate); +} + +/* +@func ret_t | rtl8367c_setAsicLedGroupEnable | Turn on/off Led of all system ports +@parm rtk_uint32 | group | LED group id. +@parm rtk_uint32 | portmask | LED port mask. +@rvalue RT_ERR_OK | Success. +@rvalue RT_ERR_SMI | SMI access error. +@rvalue RT_ERR_PORT_ID | Invalid port number. +@rvalue RT_ERR_INPUT | Invalid input value. +@comm + The API can turn on/off leds of dedicated port while indicated information configuration of LED group is set to force mode. + */ +ret_t rtl8367c_setAsicLedGroupEnable(rtk_uint32 group, rtk_uint32 portmask) +{ + ret_t retVal; + rtk_uint32 regAddr; + rtk_uint32 regDataMask; + rtk_uint32 data, regValue,tmp; + + if ( group >= RTL8367C_LEDGROUPNO ) + return RT_ERR_INPUT; + + if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0249)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_getAsicReg(0x1300, &data)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_getAsicReg(0x1301, ®Value)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0000)) != RT_ERR_OK) + return retVal; + + if((data == 0x6511) || (data == 0x0801)) + { + regAddr = RTL8367C_REG_PARA_LED_IO_EN1 + group/2; + regDataMask = 0xFF << ((group%2)*8); + + if((regValue & 0xff) == 0x80) + { + retVal = rtl8367c_setAsicRegBits(regAddr, regDataMask, (portmask >>1) & 0xff); + if(retVal != RT_ERR_OK) + return retVal; + } + else if((regValue & 0xff) == 0x60) + { + tmp = portmask >> 3; + portmask = (tmp << 2) | (portmask & 0xf7); + retVal = rtl8367c_setAsicRegBits(regAddr, regDataMask, portmask&0xff); + if(retVal != RT_ERR_OK) + return retVal; + } + else + { + retVal = rtl8367c_setAsicRegBits(regAddr, regDataMask, portmask&0xff); + if(retVal != RT_ERR_OK) + return retVal; + } + } + else + { + regAddr = RTL8367C_REG_PARA_LED_IO_EN1 + group/2; + regDataMask = 0xFF << ((group%2)*8); + retVal = rtl8367c_setAsicRegBits(regAddr, regDataMask, portmask&0xff); + if(retVal != RT_ERR_OK) + return retVal; + + regAddr = RTL8367C_REG_PARA_LED_IO_EN3; + regDataMask = 0x3 << (group*2); + retVal = rtl8367c_setAsicRegBits(regAddr, regDataMask, (portmask>>8)&0x7); + if(retVal != RT_ERR_OK) + return retVal; + } + + return RT_ERR_OK; +} + +/* +@func ret_t | rtl8367c_getAsicLedGroupEnable | Get on/off status of Led of all system ports +@parm rtk_uint32 | group | LED group id. +@parm rtk_uint32 | *portmask | LED port mask. +@rvalue RT_ERR_OK | Success. +@rvalue RT_ERR_SMI | SMI access error. +@rvalue RT_ERR_PORT_ID | Invalid port number. +@rvalue RT_ERR_INPUT | Invalid input value. +@comm + The API can turn on/off leds of dedicated port while indicated information configuration of LED group is set to force mode. + */ +ret_t rtl8367c_getAsicLedGroupEnable(rtk_uint32 group, rtk_uint32 *portmask) +{ + ret_t retVal; + rtk_uint32 regAddr; + rtk_uint32 regDataMask,regData; + rtk_uint32 data, regValue,tmp; + + if ( group >= RTL8367C_LEDGROUPNO ) + return RT_ERR_INPUT; + + if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0249)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_getAsicReg(0x1300, &data)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_getAsicReg(0x1301, ®Value)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0000)) != RT_ERR_OK) + return retVal; + + if((data == 0x6511) || (data == 0x0801)) + { + regAddr = RTL8367C_REG_PARA_LED_IO_EN1 + group/2; + regDataMask = 0xFF << ((group%2)*8); + retVal = rtl8367c_getAsicRegBits(regAddr, regDataMask, portmask); + if(retVal != RT_ERR_OK) + return retVal; + + if((regValue & 0xff) == 0x80) + { + *portmask = *portmask << 1; + } + else if((regValue & 0xff) == 0x60) + { + tmp = (*portmask >> 2) & 0x1; + *portmask = (tmp << 3 ) | (*portmask & 0xfb); + } + } + else + { + regAddr = RTL8367C_REG_PARA_LED_IO_EN1 + group/2; + regDataMask = 0xFF << ((group%2)*8); + retVal = rtl8367c_getAsicRegBits(regAddr, regDataMask, portmask); + if(retVal != RT_ERR_OK) + return retVal; + + regAddr = RTL8367C_REG_PARA_LED_IO_EN3; + regDataMask = 0x3 << (group*2); + retVal = rtl8367c_getAsicRegBits(regAddr, regDataMask, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + *portmask = (regData << 8) | *portmask; + } + + return RT_ERR_OK; +} + +/* +@func ret_t | rtl8367c_setAsicLedOperationMode | Set LED operation mode +@parm rtk_uint32 | mode | LED mode. 1:scan mode 1, 2:parallel mode, 3:mdx mode (serial mode) +@rvalue RT_ERR_OK | Success. +@rvalue RT_ERR_SMI | SMI access error. +@rvalue RT_ERR_INPUT | Invalid input value. +@comm + The API can turn on/off led serial mode and set signal to active high/low. + */ +ret_t rtl8367c_setAsicLedOperationMode(rtk_uint32 mode) +{ + ret_t retVal; + + /* Invalid input parameter */ + if( mode >= LEDOP_END) + return RT_ERR_INPUT; + + switch(mode) + { + case LEDOP_PARALLEL: + if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_LED_SYS_CONFIG, RTL8367C_LED_SELECT_OFFSET, 0))!= RT_ERR_OK) + return retVal; + /*Disable serial CLK mode*/ + if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_SCAN0_LED_IO_EN1,RTL8367C_LED_SERI_CLK_EN_OFFSET, 0))!= RT_ERR_OK) + return retVal; + /*Disable serial DATA mode*/ + if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_SCAN0_LED_IO_EN1,RTL8367C_LED_SERI_DATA_EN_OFFSET, 0))!= RT_ERR_OK) + return retVal; + break; + case LEDOP_SERIAL: + if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_LED_SYS_CONFIG, RTL8367C_LED_SELECT_OFFSET, 1))!= RT_ERR_OK) + return retVal; + /*Enable serial CLK mode*/ + if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_SCAN0_LED_IO_EN1,RTL8367C_LED_SERI_CLK_EN_OFFSET, 1))!= RT_ERR_OK) + return retVal; + /*Enable serial DATA mode*/ + if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_SCAN0_LED_IO_EN1,RTL8367C_LED_SERI_DATA_EN_OFFSET, 1))!= RT_ERR_OK) + return retVal; + break; + default: + return RT_ERR_INPUT; + break; + } + + return RT_ERR_OK; +} + + +/* +@func ret_t | rtl8367c_getAsicLedOperationMode | Get LED OP mode setup +@parm rtk_uint32*| mode | LED mode. 1:scan mode 1, 2:parallel mode, 3:mdx mode (serial mode) +@rvalue RT_ERR_OK | Success. +@rvalue RT_ERR_SMI | SMI access error. +@rvalue RT_ERR_INPUT | Invalid input value. +@comm + The API can get LED serial mode setup and get signal active high/low. + */ +ret_t rtl8367c_getAsicLedOperationMode(rtk_uint32 *mode) +{ + ret_t retVal; + rtk_uint32 regData; + + if((retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_LED_SYS_CONFIG, RTL8367C_LED_SELECT_OFFSET, ®Data))!= RT_ERR_OK) + return retVal; + + if (regData == 1) + *mode = LEDOP_SERIAL; + else if (regData == 0) + *mode = LEDOP_PARALLEL; + else + return RT_ERR_FAILED; + + return RT_ERR_OK; +} + +/* +@func ret_t | rtl8367c_setAsicLedSerialModeConfig | Set LED serial mode +@parm rtk_uint32 | active | Active High or Low. +@rvalue RT_ERR_OK | Success. +@rvalue RT_ERR_SMI | SMI access error. +@rvalue RT_ERR_INPUT | Invalid input value. +@comm + The API can turn on/off led serial mode and set signal to active high/low. + */ +ret_t rtl8367c_setAsicLedSerialModeConfig(rtk_uint32 active, rtk_uint32 serimode) +{ + ret_t retVal; + + /* Invalid input parameter */ + if( active >= LEDSERACT_MAX) + return RT_ERR_INPUT; + if( serimode >= LEDSER_MAX) + return RT_ERR_INPUT; + + /* Set Active High or Low */ + if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_LED_SYS_CONFIG, RTL8367C_SERI_LED_ACT_LOW_OFFSET, active)) != RT_ERR_OK) + return retVal; + + /*set to 8G mode (not 16G mode)*/ + if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_LED_MODE, RTL8367C_DLINK_TIME_OFFSET, serimode))!= RT_ERR_OK) + return retVal; + + + return RT_ERR_OK; +} + + +/* +@func ret_t | rtl8367c_getAsicLedSerialModeConfig | Get LED serial mode setup +@parm rtk_uint32*| active | Active High or Low. +@rvalue RT_ERR_OK | Success. +@rvalue RT_ERR_SMI | SMI access error. +@rvalue RT_ERR_INPUT | Invalid input value. +@comm + The API can get LED serial mode setup and get signal active high/low. + */ +ret_t rtl8367c_getAsicLedSerialModeConfig(rtk_uint32 *active, rtk_uint32 *serimode) +{ + ret_t retVal; + + if((retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_LED_SYS_CONFIG, RTL8367C_SERI_LED_ACT_LOW_OFFSET, active))!= RT_ERR_OK) + return retVal; + + /*get to 8G mode (not 16G mode)*/ + if((retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_LED_MODE, RTL8367C_DLINK_TIME_OFFSET, serimode))!= RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* +@func ret_t | rtl8367c_setAsicLedOutputEnable | Set LED output enable +@parm rtk_uint32 | enabled | enable or disalbe. +@rvalue RT_ERR_OK | Success. +@rvalue RT_ERR_SMI | SMI access error. +@rvalue RT_ERR_INPUT | Invalid input value. +@comm + The API can turn on/off LED output Enable + */ +ret_t rtl8367c_setAsicLedOutputEnable(rtk_uint32 enabled) +{ + ret_t retVal; + rtk_uint32 regdata; + + if (enabled == 1) + regdata = 0; + else + regdata = 1; + + /* Enable/Disable H/W IGMP/MLD */ + retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_LED_SYS_CONFIG, RTL8367C_LED_IO_DISABLE_OFFSET, regdata); + + return retVal; +} + + +/* +@func ret_t | rtl8367c_getAsicLedOutputEnable | Get LED serial mode setup +@parm rtk_uint32*| active | Active High or Low. +@rvalue RT_ERR_OK | Success. +@rvalue RT_ERR_SMI | SMI access error. +@rvalue RT_ERR_INPUT | Invalid input value. +@comm + The API can get LED serial mode setup and get signal active high/low. + */ +ret_t rtl8367c_getAsicLedOutputEnable(rtk_uint32 *ptr_enabled) +{ + ret_t retVal; + rtk_uint32 regdata; + + retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_LED_SYS_CONFIG, RTL8367C_LED_IO_DISABLE_OFFSET, ®data); + if (retVal != RT_ERR_OK) + return retVal; + + if (regdata == 1) + *ptr_enabled = 0; + else + *ptr_enabled = 1; + + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_setAsicLedSerialOutput + * Description: + * Set serial LED output group and portmask. + * Input: + * output - Serial LED output group + * pmask - Serial LED output portmask + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - input parameter out of range + * Note: + * None + */ +ret_t rtl8367c_setAsicLedSerialOutput(rtk_uint32 output, rtk_uint32 pmask) +{ + ret_t retVal; + + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_SERIAL_LED_CTRL, RTL8367C_SERIAL_LED_GROUP_NUM_MASK, output); + if (retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_SERIAL_LED_CTRL, RTL8367C_SERIAL_LED_PORT_EN_MASK, pmask); + if (retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_getAsicLedSerialOutput + * Description: + * Get serial LED output group and portmask. + * Input: + * None + * Output: + * pOutput - Serial LED output group + * pPmask - Serial LED output portmask + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - input parameter out of range + * Note: + * None + */ +ret_t rtl8367c_getAsicLedSerialOutput(rtk_uint32 *pOutput, rtk_uint32 *pPmask) +{ + ret_t retVal; + + if(pOutput == NULL) + return RT_ERR_NULL_POINTER; + + if(pPmask == NULL) + return RT_ERR_NULL_POINTER; + + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_SERIAL_LED_CTRL, RTL8367C_SERIAL_LED_GROUP_NUM_MASK, pOutput); + if (retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_SERIAL_LED_CTRL, RTL8367C_SERIAL_LED_PORT_EN_MASK, pPmask); + if (retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_led.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_led.h new file mode 100644 index 00000000..3bf34c29 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_led.h @@ -0,0 +1,121 @@ +#ifndef _RTL8367C_ASICDRV_LED_H_ +#define _RTL8367C_ASICDRV_LED_H_ + +#include + +#define RTL8367C_LEDGROUPNO 3 +#define RTL8367C_LEDGROUPMASK 0x7 +#define RTL8367C_LED_FORCE_MODE_BASE RTL8367C_REG_CPU_FORCE_LED0_CFG0 +#define RTL8367C_LED_FORCE_CTRL RTL8367C_REG_CPU_FORCE_LED_CFG + +enum RTL8367C_LEDOP{ + + LEDOP_SCAN0=0, + LEDOP_SCAN1, + LEDOP_PARALLEL, + LEDOP_SERIAL, + LEDOP_END, +}; + +enum RTL8367C_LEDSERACT{ + + LEDSERACT_HIGH=0, + LEDSERACT_LOW, + LEDSERACT_MAX, +}; + +enum RTL8367C_LEDSER{ + + LEDSER_16G=0, + LEDSER_8G, + LEDSER_MAX, +}; + +enum RTL8367C_LEDCONF{ + + LEDCONF_LEDOFF=0, + LEDCONF_DUPCOL, + LEDCONF_LINK_ACT, + LEDCONF_SPD1000, + LEDCONF_SPD100, + LEDCONF_SPD10, + LEDCONF_SPD1000ACT, + LEDCONF_SPD100ACT, + LEDCONF_SPD10ACT, + LEDCONF_SPD10010ACT, + LEDCONF_LOOPDETECT, + LEDCONF_EEE, + LEDCONF_LINKRX, + LEDCONF_LINKTX, + LEDCONF_MASTER, + LEDCONF_ACT, + LEDCONF_END +}; + +enum RTL8367C_LEDBLINKRATE{ + + LEDBLINKRATE_32MS=0, + LEDBLINKRATE_64MS, + LEDBLINKRATE_128MS, + LEDBLINKRATE_256MS, + LEDBLINKRATE_512MS, + LEDBLINKRATE_1024MS, + LEDBLINKRATE_48MS, + LEDBLINKRATE_96MS, + LEDBLINKRATE_END, +}; + +enum RTL8367C_LEDFORCEMODE{ + + LEDFORCEMODE_NORMAL=0, + LEDFORCEMODE_BLINK, + LEDFORCEMODE_OFF, + LEDFORCEMODE_ON, + LEDFORCEMODE_END, +}; + +enum RTL8367C_LEDFORCERATE{ + + LEDFORCERATE_512MS=0, + LEDFORCERATE_1024MS, + LEDFORCERATE_2048MS, + LEDFORCERATE_NORMAL, + LEDFORCERATE_END, + +}; + +enum RTL8367C_LEDMODE +{ + RTL8367C_LED_MODE_0 = 0, + RTL8367C_LED_MODE_1, + RTL8367C_LED_MODE_2, + RTL8367C_LED_MODE_3, + RTL8367C_LED_MODE_END +}; + +extern ret_t rtl8367c_setAsicLedIndicateInfoConfig(rtk_uint32 ledno, rtk_uint32 config); +extern ret_t rtl8367c_getAsicLedIndicateInfoConfig(rtk_uint32 ledno, rtk_uint32* pConfig); +extern ret_t rtl8367c_setAsicForceLed(rtk_uint32 port, rtk_uint32 group, rtk_uint32 mode); +extern ret_t rtl8367c_getAsicForceLed(rtk_uint32 port, rtk_uint32 group, rtk_uint32* pMode); +extern ret_t rtl8367c_setAsicForceGroupLed(rtk_uint32 groupmask, rtk_uint32 mode); +extern ret_t rtl8367c_getAsicForceGroupLed(rtk_uint32* groupmask, rtk_uint32* pMode); +extern ret_t rtl8367c_setAsicLedBlinkRate(rtk_uint32 blinkRate); +extern ret_t rtl8367c_getAsicLedBlinkRate(rtk_uint32* pBlinkRate); +extern ret_t rtl8367c_setAsicLedForceBlinkRate(rtk_uint32 blinkRate); +extern ret_t rtl8367c_getAsicLedForceBlinkRate(rtk_uint32* pBlinkRate); +extern ret_t rtl8367c_setAsicLedGroupMode(rtk_uint32 mode); +extern ret_t rtl8367c_getAsicLedGroupMode(rtk_uint32* pMode); +extern ret_t rtl8367c_setAsicLedGroupEnable(rtk_uint32 group, rtk_uint32 portmask); +extern ret_t rtl8367c_getAsicLedGroupEnable(rtk_uint32 group, rtk_uint32 *portmask); +extern ret_t rtl8367c_setAsicLedOperationMode(rtk_uint32 mode); +extern ret_t rtl8367c_getAsicLedOperationMode(rtk_uint32 *mode); +extern ret_t rtl8367c_setAsicLedSerialModeConfig(rtk_uint32 active, rtk_uint32 serimode); +extern ret_t rtl8367c_getAsicLedSerialModeConfig(rtk_uint32 *active, rtk_uint32 *serimode); +extern ret_t rtl8367c_setAsicLedOutputEnable(rtk_uint32 enabled); +extern ret_t rtl8367c_getAsicLedOutputEnable(rtk_uint32 *ptr_enabled); +extern ret_t rtl8367c_setAsicLedSerialOutput(rtk_uint32 output, rtk_uint32 pmask); +extern ret_t rtl8367c_getAsicLedSerialOutput(rtk_uint32 *pOutput, rtk_uint32 *pPmask); + + +#endif /*#ifndef _RTL8367C_ASICDRV_LED_H_*/ + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_lut.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_lut.c new file mode 100644 index 00000000..f5b3d539 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_lut.c @@ -0,0 +1,1548 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTL8367C switch high-level API for RTL8367C + * Feature : LUT related functions + * + */ + +#include + +#include + +static void _rtl8367c_fdbStUser2Smi( rtl8367c_luttb *pLutSt, rtk_uint16 *pFdbSmi) +{ + /* L3 lookup */ + if(pLutSt->l3lookup) + { + if(pLutSt->l3vidlookup) + { + pFdbSmi[0] = (pLutSt->sip & 0x0000FFFF); + pFdbSmi[1] = (pLutSt->sip & 0xFFFF0000) >> 16; + + pFdbSmi[2] = (pLutSt->dip & 0x0000FFFF); + pFdbSmi[3] = (pLutSt->dip & 0x0FFF0000) >> 16; + + pFdbSmi[3] |= (pLutSt->l3lookup & 0x0001) << 12; + pFdbSmi[3] |= (pLutSt->l3vidlookup & 0x0001) << 13; + pFdbSmi[3] |= ((pLutSt->mbr & 0x0300) >> 8) << 14; + + pFdbSmi[4] |= (pLutSt->mbr & 0x00FF); + pFdbSmi[4] |= (pLutSt->l3_vid & 0x00FF) << 8; + + pFdbSmi[5] |= ((pLutSt->l3_vid & 0x0F00) >> 8); + pFdbSmi[5] |= (pLutSt->nosalearn & 0x0001) << 5; + pFdbSmi[5] |= ((pLutSt->mbr & 0x0400) >> 10) << 7; + } + else + { + pFdbSmi[0] = (pLutSt->sip & 0x0000FFFF); + pFdbSmi[1] = (pLutSt->sip & 0xFFFF0000) >> 16; + + pFdbSmi[2] = (pLutSt->dip & 0x0000FFFF); + pFdbSmi[3] = (pLutSt->dip & 0x0FFF0000) >> 16; + + pFdbSmi[3] |= (pLutSt->l3lookup & 0x0001) << 12; + pFdbSmi[3] |= (pLutSt->l3vidlookup & 0x0001) << 13; + pFdbSmi[3] |= ((pLutSt->mbr & 0x0300) >> 8) << 14; + + pFdbSmi[4] |= (pLutSt->mbr & 0x00FF); + pFdbSmi[4] |= (pLutSt->igmpidx & 0x00FF) << 8; + + pFdbSmi[5] |= (pLutSt->igmp_asic & 0x0001); + pFdbSmi[5] |= (pLutSt->lut_pri & 0x0007) << 1; + pFdbSmi[5] |= (pLutSt->fwd_en & 0x0001) << 4; + pFdbSmi[5] |= (pLutSt->nosalearn & 0x0001) << 5; + pFdbSmi[5] |= ((pLutSt->mbr & 0x0400) >> 10) << 7; + } + } + else if(pLutSt->mac.octet[0] & 0x01) /*Multicast L2 Lookup*/ + { + pFdbSmi[0] |= pLutSt->mac.octet[5]; + pFdbSmi[0] |= pLutSt->mac.octet[4] << 8; + + pFdbSmi[1] |= pLutSt->mac.octet[3]; + pFdbSmi[1] |= pLutSt->mac.octet[2] << 8; + + pFdbSmi[2] |= pLutSt->mac.octet[1]; + pFdbSmi[2] |= pLutSt->mac.octet[0] << 8; + + pFdbSmi[3] |= pLutSt->cvid_fid; + pFdbSmi[3] |= (pLutSt->l3lookup & 0x0001) << 12; + pFdbSmi[3] |= (pLutSt->ivl_svl & 0x0001) << 13; + pFdbSmi[3] |= ((pLutSt->mbr & 0x0300) >> 8) << 14; + + pFdbSmi[4] |= (pLutSt->mbr & 0x00FF); + pFdbSmi[4] |= (pLutSt->igmpidx & 0x00FF) << 8; + + pFdbSmi[5] |= pLutSt->igmp_asic; + pFdbSmi[5] |= (pLutSt->lut_pri & 0x0007) << 1; + pFdbSmi[5] |= (pLutSt->fwd_en & 0x0001) << 4; + pFdbSmi[5] |= (pLutSt->nosalearn & 0x0001) << 5; + pFdbSmi[5] |= ((pLutSt->mbr & 0x0400) >> 10) << 7; + } + else /*Asic auto-learning*/ + { + pFdbSmi[0] |= pLutSt->mac.octet[5]; + pFdbSmi[0] |= pLutSt->mac.octet[4] << 8; + + pFdbSmi[1] |= pLutSt->mac.octet[3]; + pFdbSmi[1] |= pLutSt->mac.octet[2] << 8; + + pFdbSmi[2] |= pLutSt->mac.octet[1]; + pFdbSmi[2] |= pLutSt->mac.octet[0] << 8; + + pFdbSmi[3] |= pLutSt->cvid_fid; + pFdbSmi[3] |= (pLutSt->l3lookup & 0x0001) << 12; + pFdbSmi[3] |= (pLutSt->ivl_svl & 0x0001) << 13; + pFdbSmi[3] |= ((pLutSt->spa & 0x0008) >> 3) << 15; + + pFdbSmi[4] |= pLutSt->efid; + pFdbSmi[4] |= (pLutSt->fid & 0x000F) << 3; + pFdbSmi[4] |= (pLutSt->sa_en & 0x0001) << 7; + pFdbSmi[4] |= (pLutSt->spa & 0x0007) << 8; + pFdbSmi[4] |= (pLutSt->age & 0x0007) << 11; + pFdbSmi[4] |= (pLutSt->auth & 0x0001) << 14; + pFdbSmi[4] |= (pLutSt->sa_block & 0x0001) << 15; + + pFdbSmi[5] |= pLutSt->da_block; + pFdbSmi[5] |= (pLutSt->lut_pri & 0x0007) << 1; + pFdbSmi[5] |= (pLutSt->fwd_en & 0x0001) << 4; + pFdbSmi[5] |= (pLutSt->nosalearn & 0x0001) << 5; + } +} + + +static void _rtl8367c_fdbStSmi2User( rtl8367c_luttb *pLutSt, rtk_uint16 *pFdbSmi) +{ + /*L3 lookup*/ + if(pFdbSmi[3] & 0x1000) + { + if(pFdbSmi[3] & 0x2000) + { + pLutSt->sip = pFdbSmi[0] | (pFdbSmi[1] << 16); + pLutSt->dip = 0xE0000000 | pFdbSmi[2] | ((pFdbSmi[3] & 0x0FFF) << 16); + + pLutSt->mbr = (pFdbSmi[4] & 0x00FF) | (((pFdbSmi[3] & 0xC000) >> 14) << 8) | (((pFdbSmi[5] & 0x0080) >> 7) << 10); + pLutSt->l3_vid = ((pFdbSmi[4] & 0xFF00) >> 8) | (pFdbSmi[5] & 0x000F); + + pLutSt->l3lookup = (pFdbSmi[3] & 0x1000) >> 12; + pLutSt->l3vidlookup = (pFdbSmi[3] & 0x2000) >> 13; + pLutSt->nosalearn = (pFdbSmi[5] & 0x0020) >> 5; + } + else + { + pLutSt->sip = pFdbSmi[0] | (pFdbSmi[1] << 16); + pLutSt->dip = 0xE0000000 | pFdbSmi[2] | ((pFdbSmi[3] & 0x0FFF) << 16); + + pLutSt->lut_pri = (pFdbSmi[5] & 0x000E) >> 1; + pLutSt->fwd_en = (pFdbSmi[5] & 0x0010) >> 4; + + pLutSt->mbr = (pFdbSmi[4] & 0x00FF) | (((pFdbSmi[3] & 0xC000) >> 14) << 8) | (((pFdbSmi[5] & 0x0080) >> 7) << 10); + pLutSt->igmpidx = (pFdbSmi[4] & 0xFF00) >> 8; + + pLutSt->igmp_asic = (pFdbSmi[5] & 0x0001); + pLutSt->l3lookup = (pFdbSmi[3] & 0x1000) >> 12; + pLutSt->nosalearn = (pFdbSmi[5] & 0x0020) >> 5; + } + } + else if(pFdbSmi[2] & 0x0100) /*Multicast L2 Lookup*/ + { + pLutSt->mac.octet[0] = (pFdbSmi[2] & 0xFF00) >> 8; + pLutSt->mac.octet[1] = (pFdbSmi[2] & 0x00FF); + pLutSt->mac.octet[2] = (pFdbSmi[1] & 0xFF00) >> 8; + pLutSt->mac.octet[3] = (pFdbSmi[1] & 0x00FF); + pLutSt->mac.octet[4] = (pFdbSmi[0] & 0xFF00) >> 8; + pLutSt->mac.octet[5] = (pFdbSmi[0] & 0x00FF); + + pLutSt->cvid_fid = pFdbSmi[3] & 0x0FFF; + pLutSt->lut_pri = (pFdbSmi[5] & 0x000E) >> 1; + pLutSt->fwd_en = (pFdbSmi[5] & 0x0010) >> 4; + + pLutSt->mbr = (pFdbSmi[4] & 0x00FF) | (((pFdbSmi[3] & 0xC000) >> 14) << 8) | (((pFdbSmi[5] & 0x0080) >> 7) << 10); + pLutSt->igmpidx = (pFdbSmi[4] & 0xFF00) >> 8; + + pLutSt->igmp_asic = (pFdbSmi[5] & 0x0001); + pLutSt->l3lookup = (pFdbSmi[3] & 0x1000) >> 12; + pLutSt->ivl_svl = (pFdbSmi[3] & 0x2000) >> 13; + pLutSt->nosalearn = (pFdbSmi[5] & 0x0020) >> 5; + } + else /*Asic auto-learning*/ + { + pLutSt->mac.octet[0] = (pFdbSmi[2] & 0xFF00) >> 8; + pLutSt->mac.octet[1] = (pFdbSmi[2] & 0x00FF); + pLutSt->mac.octet[2] = (pFdbSmi[1] & 0xFF00) >> 8; + pLutSt->mac.octet[3] = (pFdbSmi[1] & 0x00FF); + pLutSt->mac.octet[4] = (pFdbSmi[0] & 0xFF00) >> 8; + pLutSt->mac.octet[5] = (pFdbSmi[0] & 0x00FF); + + pLutSt->cvid_fid = pFdbSmi[3] & 0x0FFF; + pLutSt->lut_pri = (pFdbSmi[5] & 0x000E) >> 1; + pLutSt->fwd_en = (pFdbSmi[5] & 0x0010) >> 4; + + pLutSt->sa_en = (pFdbSmi[4] & 0x0080) >> 7; + pLutSt->auth = (pFdbSmi[4] & 0x4000) >> 14; + pLutSt->spa = ((pFdbSmi[4] & 0x0700) >> 8) | (((pFdbSmi[3] & 0x8000) >> 15) << 3); + pLutSt->age = (pFdbSmi[4] & 0x3800) >> 11; + pLutSt->fid = (pFdbSmi[4] & 0x0078) >> 3; + pLutSt->efid = (pFdbSmi[4] & 0x0007); + pLutSt->sa_block = (pFdbSmi[4] & 0x8000) >> 15; + + pLutSt->da_block = (pFdbSmi[5] & 0x0001); + pLutSt->l3lookup = (pFdbSmi[3] & 0x1000) >> 12; + pLutSt->ivl_svl = (pFdbSmi[3] & 0x2000) >> 13; + pLutSt->nosalearn = (pFdbSmi[5] & 0x0020) >> 5; + } +} + +/* Function Name: + * rtl8367c_setAsicLutIpMulticastLookup + * Description: + * Set Lut IP multicast lookup function + * Input: + * enabled - 1: enabled, 0: disabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicLutIpMulticastLookup(rtk_uint32 enabled) +{ + return rtl8367c_setAsicRegBit(RTL8367C_REG_LUT_CFG, RTL8367C_LUT_IPMC_HASH_OFFSET, enabled); +} +/* Function Name: + * rtl8367c_getAsicLutIpMulticastLookup + * Description: + * Get Lut IP multicast lookup function + * Input: + * pEnabled - 1: enabled, 0: disabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicLutIpMulticastLookup(rtk_uint32* pEnabled) +{ + return rtl8367c_getAsicRegBit(RTL8367C_REG_LUT_CFG, RTL8367C_LUT_IPMC_HASH_OFFSET, pEnabled); +} + +/* Function Name: + * rtl8367c_setAsicLutIpMulticastLookup + * Description: + * Set Lut IP multicast + VID lookup function + * Input: + * enabled - 1: enabled, 0: disabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicLutIpMulticastVidLookup(rtk_uint32 enabled) +{ + return rtl8367c_setAsicRegBit(RTL8367C_REG_LUT_CFG2, RTL8367C_LUT_IPMC_VID_HASH_OFFSET, enabled); +} + +/* Function Name: + * rtl8367c_getAsicLutIpMulticastVidLookup + * Description: + * Get Lut IP multicast lookup function + * Input: + * pEnabled - 1: enabled, 0: disabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicLutIpMulticastVidLookup(rtk_uint32* pEnabled) +{ + return rtl8367c_getAsicRegBit(RTL8367C_REG_LUT_CFG2, RTL8367C_LUT_IPMC_VID_HASH_OFFSET, pEnabled); +} + +/* Function Name: + * rtl8367c_setAsicLutIpLookupMethod + * Description: + * Set Lut IP lookup hash with DIP or {DIP,SIP} pair + * Input: + * type - 1: When DIP can be found in IPMC_GROUP_TABLE, use DIP+SIP Hash, otherwise, use DIP+(SIP=0.0.0.0) Hash. + * 0: When DIP can be found in IPMC_GROUP_TABLE, use DIP+(SIP=0.0.0.0) Hash, otherwise use DIP+SIP Hash. + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicLutIpLookupMethod(rtk_uint32 type) +{ + return rtl8367c_setAsicRegBit(RTL8367C_REG_LUT_CFG, RTL8367C_LUT_IPMC_LOOKUP_OP_OFFSET, type); +} +/* Function Name: + * rtl8367c_getAsicLutIpLookupMethod + * Description: + * Get Lut IP lookup hash with DIP or {DIP,SIP} pair + * Input: + * pType - 1: When DIP can be found in IPMC_GROUP_TABLE, use DIP+SIP Hash, otherwise, use DIP+(SIP=0.0.0.0) Hash. + * 0: When DIP can be found in IPMC_GROUP_TABLE, use DIP+(SIP=0.0.0.0) Hash, otherwise use DIP+SIP Hash. + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicLutIpLookupMethod(rtk_uint32* pType) +{ + return rtl8367c_getAsicRegBit(RTL8367C_REG_LUT_CFG, RTL8367C_LUT_IPMC_LOOKUP_OP_OFFSET, pType); +} +/* Function Name: + * rtl8367c_setAsicLutAgeTimerSpeed + * Description: + * Set LUT agging out speed + * Input: + * timer - Agging out timer 0:Has been aged out + * speed - Agging out speed 0-fastest 3-slowest + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - input parameter out of range + * Note: + * None + */ +ret_t rtl8367c_setAsicLutAgeTimerSpeed(rtk_uint32 timer, rtk_uint32 speed) +{ + if(timer>RTL8367C_LUT_AGETIMERMAX) + return RT_ERR_OUT_OF_RANGE; + + if(speed >RTL8367C_LUT_AGESPEEDMAX) + return RT_ERR_OUT_OF_RANGE; + + return rtl8367c_setAsicRegBits(RTL8367C_REG_LUT_CFG, RTL8367C_AGE_TIMER_MASK | RTL8367C_AGE_SPEED_MASK, (timer << RTL8367C_AGE_TIMER_OFFSET) | (speed << RTL8367C_AGE_SPEED_OFFSET)); +} +/* Function Name: + * rtl8367c_getAsicLutAgeTimerSpeed + * Description: + * Get LUT agging out speed + * Input: + * pTimer - Agging out timer 0:Has been aged out + * pSpeed - Agging out speed 0-fastest 3-slowest + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - input parameter out of range + * Note: + * None + */ +ret_t rtl8367c_getAsicLutAgeTimerSpeed(rtk_uint32* pTimer, rtk_uint32* pSpeed) +{ + rtk_uint32 regData; + ret_t retVal; + + retVal = rtl8367c_getAsicReg(RTL8367C_REG_LUT_CFG, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + *pTimer = (regData & RTL8367C_AGE_TIMER_MASK) >> RTL8367C_AGE_TIMER_OFFSET; + + *pSpeed = (regData & RTL8367C_AGE_SPEED_MASK) >> RTL8367C_AGE_SPEED_OFFSET; + + return RT_ERR_OK; + +} +/* Function Name: + * rtl8367c_setAsicLutCamTbUsage + * Description: + * Configure Lut CAM table usage + * Input: + * enabled - L2 CAM table usage 1: enabled, 0: disabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicLutCamTbUsage(rtk_uint32 enabled) +{ + ret_t retVal; + + retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_LUT_CFG, RTL8367C_BCAM_DISABLE_OFFSET, enabled ? 0 : 1); + + return retVal; +} +/* Function Name: + * rtl8367c_getAsicLutCamTbUsage + * Description: + * Get Lut CAM table usage + * Input: + * pEnabled - L2 CAM table usage 1: enabled, 0: disabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicLutCamTbUsage(rtk_uint32* pEnabled) +{ + ret_t retVal; + rtk_uint32 regData; + + if ((retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_LUT_CFG, RTL8367C_BCAM_DISABLE_OFFSET, ®Data)) != RT_ERR_OK) + return retVal; + + *pEnabled = regData ? 0 : 1; + return RT_ERR_OK; +} +/* Function Name: + * rtl8367c_setAsicLutLearnLimitNo + * Description: + * Set per-Port auto learning limit number + * Input: + * port - Physical port number (0~7) + * number - ASIC auto learning entries limit number + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * RT_ERR_LIMITED_L2ENTRY_NUM - Invalid auto learning limit number + * Note: + * None + */ + /*ÐÞ¸Ä: RTL8367C_PORTIDMAX, RTL8367C_LUT_LEARNLIMITMAX, RTL8367C_LUT_PORT_LEARN_LIMITNO_REG*/ +ret_t rtl8367c_setAsicLutLearnLimitNo(rtk_uint32 port, rtk_uint32 number) +{ + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + if(number > RTL8367C_LUT_LEARNLIMITMAX) + return RT_ERR_LIMITED_L2ENTRY_NUM; + + if(port < 8) + return rtl8367c_setAsicReg(RTL8367C_LUT_PORT_LEARN_LIMITNO_REG(port), number); + else + return rtl8367c_setAsicReg(RTL8367C_REG_LUT_PORT8_LEARN_LIMITNO+port-8, number); + +} +/* Function Name: + * rtl8367c_getAsicLutLearnLimitNo + * Description: + * Get per-Port auto learning limit number + * Input: + * port - Physical port number (0~7) + * pNumber - ASIC auto learning entries limit number + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ + /*ÐÞ¸Ä: RTL8367C_PORTIDMAX, RTL8367C_LUT_PORT_LEARN_LIMITNO_REG*/ +ret_t rtl8367c_getAsicLutLearnLimitNo(rtk_uint32 port, rtk_uint32* pNumber) +{ + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + if(port < 8) + return rtl8367c_getAsicReg(RTL8367C_LUT_PORT_LEARN_LIMITNO_REG(port), pNumber); + else + return rtl8367c_getAsicReg(RTL8367C_REG_LUT_PORT8_LEARN_LIMITNO+port-8, pNumber); +} + +/* Function Name: + * rtl8367c_setAsicSystemLutLearnLimitNo + * Description: + * Set system auto learning limit number + * Input: + * number - ASIC auto learning entries limit number + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * RT_ERR_LIMITED_L2ENTRY_NUM - Invalid auto learning limit number + * Note: + * None + */ + /*ÐÞ¸Ä: RTL8367C_LUT_LEARNLIMITMAX*/ +ret_t rtl8367c_setAsicSystemLutLearnLimitNo(rtk_uint32 number) +{ + if(number > RTL8367C_LUT_LEARNLIMITMAX) + return RT_ERR_LIMITED_L2ENTRY_NUM; + + return rtl8367c_setAsicReg(RTL8367C_REG_LUT_SYS_LEARN_LIMITNO, number); +} + +/* Function Name: + * rtl8367c_getAsicSystemLutLearnLimitNo + * Description: + * Get system auto learning limit number + * Input: + * port - Physical port number (0~7) + * pNumber - ASIC auto learning entries limit number + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_getAsicSystemLutLearnLimitNo(rtk_uint32 *pNumber) +{ + if(NULL == pNumber) + return RT_ERR_NULL_POINTER; + + return rtl8367c_getAsicReg(RTL8367C_REG_LUT_SYS_LEARN_LIMITNO, pNumber); +} + +/* Function Name: + * rtl8367c_setAsicLutLearnOverAct + * Description: + * Set auto learn over limit number action + * Input: + * action - Learn over action 0:normal, 1:drop 2:trap + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid learn over action + * Note: + * None + */ +ret_t rtl8367c_setAsicLutLearnOverAct(rtk_uint32 action) +{ + if(action >= LRNOVERACT_END) + return RT_ERR_NOT_ALLOWED; + + return rtl8367c_setAsicRegBits(RTL8367C_REG_PORT_SECURITY_CTRL, RTL8367C_LUT_LEARN_OVER_ACT_MASK, action); +} +/* Function Name: + * rtl8367c_getAsicLutLearnOverAct + * Description: + * Get auto learn over limit number action + * Input: + * pAction - Learn over action 0:normal, 1:drop 2:trap + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicLutLearnOverAct(rtk_uint32* pAction) +{ + return rtl8367c_getAsicRegBits(RTL8367C_REG_PORT_SECURITY_CTRL, RTL8367C_LUT_LEARN_OVER_ACT_MASK, pAction); +} + +/* Function Name: + * rtl8367c_setAsicSystemLutLearnOverAct + * Description: + * Set system auto learn over limit number action + * Input: + * action - Learn over action 0:normal, 1:drop, 2:trap + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid learn over action + * Note: + * None + */ +ret_t rtl8367c_setAsicSystemLutLearnOverAct(rtk_uint32 action) +{ + if(action >= LRNOVERACT_END) + return RT_ERR_NOT_ALLOWED; + + return rtl8367c_setAsicRegBits(RTL8367C_REG_LUT_LRN_SYS_LMT_CTRL, RTL8367C_LUT_SYSTEM_LEARN_OVER_ACT_MASK, action); +} + +/* Function Name: + * rtl8367c_getAsicSystemLutLearnOverAct + * Description: + * Get system auto learn over limit number action + * Input: + * pAction - Learn over action 0:normal, 1:drop 2:trap + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicSystemLutLearnOverAct(rtk_uint32 *pAction) +{ + if(NULL == pAction) + return RT_ERR_NULL_POINTER; + + return rtl8367c_getAsicRegBits(RTL8367C_REG_LUT_LRN_SYS_LMT_CTRL, RTL8367C_LUT_SYSTEM_LEARN_OVER_ACT_MASK, pAction); +} + +/* Function Name: + * rtl8367c_setAsicSystemLutLearnPortMask + * Description: + * Set system auto learn limit port mask + * Input: + * portmask - port mask of system learning limit + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Error port mask + * Note: + * None + */ + /*ÐÞ¸Ä: RTL8367C_LUT_SYSTEM_LEARN_PMASK_MASK*/ +ret_t rtl8367c_setAsicSystemLutLearnPortMask(rtk_uint32 portmask) +{ + ret_t retVal; + + if(portmask > RTL8367C_PORTMASK) + return RT_ERR_PORT_MASK; + + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_LUT_LRN_SYS_LMT_CTRL, RTL8367C_LUT_SYSTEM_LEARN_PMASK_MASK, portmask & 0xff); + if(retVal != RT_ERR_OK) + return retVal; + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_LUT_LRN_SYS_LMT_CTRL, RTL8367C_LUT_SYSTEM_LEARN_PMASK1_MASK, (portmask>>8) & 0x7); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; + +} + +/* Function Name: + * rtl8367c_getAsicSystemLutLearnPortMask + * Description: + * Get system auto learn limit port mask + * Input: + * None + * Output: + * pPortmask - port mask of system learning limit + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - NULL pointer + * Note: + * None + */ + /*ÐÞ¸Ä: RTL8367C_LUT_SYSTEM_LEARN_PMASK_MASK*/ +ret_t rtl8367c_getAsicSystemLutLearnPortMask(rtk_uint32 *pPortmask) +{ + rtk_uint32 tmpmask; + ret_t retVal; + + if(NULL == pPortmask) + return RT_ERR_NULL_POINTER; + + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_LUT_LRN_SYS_LMT_CTRL, RTL8367C_LUT_SYSTEM_LEARN_PMASK_MASK, &tmpmask); + if(retVal != RT_ERR_OK) + return retVal; + *pPortmask = tmpmask & 0xff; + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_LUT_LRN_SYS_LMT_CTRL, RTL8367C_LUT_SYSTEM_LEARN_PMASK1_MASK, &tmpmask); + if(retVal != RT_ERR_OK) + return retVal; + *pPortmask |= (tmpmask & 0x7) << 8; + + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_setAsicL2LookupTb + * Description: + * Set filtering database entry + * Input: + * pL2Table - L2 table entry writing to 8K+64 filtering database + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicL2LookupTb(rtl8367c_luttb *pL2Table) +{ + ret_t retVal; + rtk_uint32 regData; + rtk_uint16 *accessPtr; + rtk_uint32 i; + rtk_uint16 smil2Table[RTL8367C_LUT_TABLE_SIZE]; + rtk_uint32 tblCmd; + rtk_uint32 busyCounter; + + memset(smil2Table, 0x00, sizeof(rtk_uint16) * RTL8367C_LUT_TABLE_SIZE); + _rtl8367c_fdbStUser2Smi(pL2Table, smil2Table); + + if(pL2Table->wait_time == 0) + busyCounter = RTL8367C_LUT_BUSY_CHECK_NO; + else + busyCounter = pL2Table->wait_time; + + while(busyCounter) + { + retVal = rtl8367c_getAsicRegBit(RTL8367C_TABLE_ACCESS_STATUS_REG, RTL8367C_TABLE_LUT_ADDR_BUSY_FLAG_OFFSET,®Data); + if(retVal != RT_ERR_OK) + return retVal; + + pL2Table->lookup_busy = regData; + if(!regData) + break; + + busyCounter --; + if(busyCounter == 0) + return RT_ERR_BUSYWAIT_TIMEOUT; + } + + accessPtr = smil2Table; + + for(i = 0; i < RTL8367C_LUT_ENTRY_SIZE; i++) + { + regData = *(accessPtr + i); + retVal = rtl8367c_setAsicReg(RTL8367C_TABLE_ACCESS_WRDATA_BASE + i, regData); + if(retVal != RT_ERR_OK) + return retVal; + } + + tblCmd = (RTL8367C_TABLE_ACCESS_REG_DATA(TB_OP_WRITE,TB_TARGET_L2)) & (RTL8367C_TABLE_TYPE_MASK | RTL8367C_COMMAND_TYPE_MASK); + /* Write Command */ + retVal = rtl8367c_setAsicReg(RTL8367C_TABLE_ACCESS_CTRL_REG, tblCmd); + if(retVal != RT_ERR_OK) + return retVal; + + if(pL2Table->wait_time == 0) + busyCounter = RTL8367C_LUT_BUSY_CHECK_NO; + else + busyCounter = pL2Table->wait_time; + + while(busyCounter) + { + retVal = rtl8367c_getAsicRegBit(RTL8367C_TABLE_ACCESS_STATUS_REG, RTL8367C_TABLE_LUT_ADDR_BUSY_FLAG_OFFSET,®Data); + if(retVal != RT_ERR_OK) + return retVal; + + pL2Table->lookup_busy = regData; + if(!regData) + break; + + busyCounter --; + if(busyCounter == 0) + return RT_ERR_BUSYWAIT_TIMEOUT; + } + + /*Read access status*/ + retVal = rtl8367c_getAsicRegBit(RTL8367C_TABLE_ACCESS_STATUS_REG, RTL8367C_HIT_STATUS_OFFSET, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + pL2Table->lookup_hit = regData; + if(!pL2Table->lookup_hit) + return RT_ERR_FAILED; + + /*Read access address*/ + /* + retVal = rtl8367c_getAsicRegBits(RTL8367C_TABLE_ACCESS_STATUS_REG, RTL8367C_TABLE_LUT_ADDR_TYPE_MASK | RTL8367C_TABLE_LUT_ADDR_ADDRESS_MASK,®Data); + if(retVal != RT_ERR_OK) + return retVal; + + pL2Table->address = regData;*/ + + retVal = rtl8367c_getAsicReg(RTL8367C_TABLE_ACCESS_STATUS_REG, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + pL2Table->address = (regData & 0x7ff) | ((regData & 0x4000) >> 3) | ((regData & 0x800) << 1); + pL2Table->lookup_busy = 0; + + return RT_ERR_OK; +} +/* Function Name: + * rtl8367c_getAsicL2LookupTb + * Description: + * Get filtering database entry + * Input: + * pL2Table - L2 table entry writing to 2K+64 filtering database + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter + * RT_ERR_BUSYWAIT_TIMEOUT - LUT is busy at retrieving + * Note: + * None + */ +ret_t rtl8367c_getAsicL2LookupTb(rtk_uint32 method, rtl8367c_luttb *pL2Table) +{ + ret_t retVal; + rtk_uint32 regData; + rtk_uint16* accessPtr; + rtk_uint32 i; + rtk_uint16 smil2Table[RTL8367C_LUT_TABLE_SIZE]; + rtk_uint32 busyCounter; + rtk_uint32 tblCmd; + + if(pL2Table->wait_time == 0) + busyCounter = RTL8367C_LUT_BUSY_CHECK_NO; + else + busyCounter = pL2Table->wait_time; + + while(busyCounter) + { + retVal = rtl8367c_getAsicRegBit(RTL8367C_TABLE_ACCESS_STATUS_REG, RTL8367C_TABLE_LUT_ADDR_BUSY_FLAG_OFFSET,®Data); + if(retVal != RT_ERR_OK) + return retVal; + + pL2Table->lookup_busy = regData; + if(!pL2Table->lookup_busy) + break; + + busyCounter --; + if(busyCounter == 0) + return RT_ERR_BUSYWAIT_TIMEOUT; + } + + + tblCmd = (method << RTL8367C_ACCESS_METHOD_OFFSET) & RTL8367C_ACCESS_METHOD_MASK; + + switch(method) + { + case LUTREADMETHOD_ADDRESS: + case LUTREADMETHOD_NEXT_ADDRESS: + case LUTREADMETHOD_NEXT_L2UC: + case LUTREADMETHOD_NEXT_L2MC: + case LUTREADMETHOD_NEXT_L3MC: + case LUTREADMETHOD_NEXT_L2L3MC: + retVal = rtl8367c_setAsicReg(RTL8367C_TABLE_ACCESS_ADDR_REG, pL2Table->address); + if(retVal != RT_ERR_OK) + return retVal; + break; + case LUTREADMETHOD_MAC: + memset(smil2Table, 0x00, sizeof(rtk_uint16) * RTL8367C_LUT_TABLE_SIZE); + _rtl8367c_fdbStUser2Smi(pL2Table, smil2Table); + + accessPtr = smil2Table; + regData = *accessPtr; + for(i=0; iaddress); + if(retVal != RT_ERR_OK) + return retVal; + + tblCmd = tblCmd | ((pL2Table->spa << RTL8367C_TABLE_ACCESS_CTRL_SPA_OFFSET) & RTL8367C_TABLE_ACCESS_CTRL_SPA_MASK); + + break; + default: + return RT_ERR_INPUT; + } + + tblCmd = tblCmd | ((RTL8367C_TABLE_ACCESS_REG_DATA(TB_OP_READ,TB_TARGET_L2)) & (RTL8367C_TABLE_TYPE_MASK | RTL8367C_COMMAND_TYPE_MASK)); + /* Read Command */ + retVal = rtl8367c_setAsicReg(RTL8367C_TABLE_ACCESS_CTRL_REG, tblCmd); + if(retVal != RT_ERR_OK) + return retVal; + + if(pL2Table->wait_time == 0) + busyCounter = RTL8367C_LUT_BUSY_CHECK_NO; + else + busyCounter = pL2Table->wait_time; + + while(busyCounter) + { + retVal = rtl8367c_getAsicRegBit(RTL8367C_TABLE_ACCESS_STATUS_REG, RTL8367C_TABLE_LUT_ADDR_BUSY_FLAG_OFFSET,®Data); + if(retVal != RT_ERR_OK) + return retVal; + + pL2Table->lookup_busy = regData; + if(!pL2Table->lookup_busy) + break; + + busyCounter --; + if(busyCounter == 0) + return RT_ERR_BUSYWAIT_TIMEOUT; + } + + retVal = rtl8367c_getAsicRegBit(RTL8367C_TABLE_ACCESS_STATUS_REG, RTL8367C_HIT_STATUS_OFFSET,®Data); + if(retVal != RT_ERR_OK) + return retVal; + pL2Table->lookup_hit = regData; + if(!pL2Table->lookup_hit) + return RT_ERR_L2_ENTRY_NOTFOUND; + + /*Read access address*/ + //retVal = rtl8367c_getAsicRegBits(RTL8367C_TABLE_ACCESS_STATUS_REG, RTL8367C_TABLE_LUT_ADDR_TYPE_MASK | RTL8367C_TABLE_LUT_ADDR_ADDRESS_MASK,®Data); + retVal = rtl8367c_getAsicReg(RTL8367C_TABLE_ACCESS_STATUS_REG, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + pL2Table->address = (regData & 0x7ff) | ((regData & 0x4000) >> 3) | ((regData & 0x800) << 1); + + /*read L2 entry */ + memset(smil2Table, 0x00, sizeof(rtk_uint16) * RTL8367C_LUT_TABLE_SIZE); + + accessPtr = smil2Table; + + for(i = 0; i < RTL8367C_LUT_ENTRY_SIZE; i++) + { + retVal = rtl8367c_getAsicReg(RTL8367C_TABLE_ACCESS_RDDATA_BASE + i, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + *accessPtr = regData; + + accessPtr ++; + } + + _rtl8367c_fdbStSmi2User(pL2Table, smil2Table); + + return RT_ERR_OK; +} +/* Function Name: + * rtl8367c_getAsicLutLearnNo + * Description: + * Get per-Port auto learning number + * Input: + * port - Physical port number (0~7) + * pNumber - ASIC auto learning entries number + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ + /*ÐÞ¸ÄRTL8367C_PORTIDMAX, RTL8367C_REG_L2_LRN_CNT_REG, port10 reg is not contnious, wait for updating of base.h*/ +ret_t rtl8367c_getAsicLutLearnNo(rtk_uint32 port, rtk_uint32* pNumber) +{ + ret_t retVal; + + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + if(port < 10) + { + retVal = rtl8367c_getAsicReg(RTL8367C_REG_L2_LRN_CNT_REG(port), pNumber); + if (retVal != RT_ERR_OK) + return retVal; + } + else + { + retVal = rtl8367c_getAsicReg(RTL8367C_REG_L2_LRN_CNT_CTRL10, pNumber); + if (retVal != RT_ERR_OK) + return retVal; + } + + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_setAsicLutFlushAll + * Description: + * Flush all entries in LUT. Includes static & dynamic entries + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicLutFlushAll(void) +{ + return rtl8367c_setAsicRegBit(RTL8367C_REG_L2_FLUSH_CTRL3, RTL8367C_L2_FLUSH_CTRL3_OFFSET, 1); +} + +/* Function Name: + * rtl8367c_getAsicLutFlushAllStatus + * Description: + * Get Flush all status, 1:Busy, 0 normal + * Input: + * None + * Output: + * pBusyStatus - Busy state + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * None + */ +ret_t rtl8367c_getAsicLutFlushAllStatus(rtk_uint32 *pBusyStatus) +{ + if(NULL == pBusyStatus) + return RT_ERR_NULL_POINTER; + + return rtl8367c_getAsicRegBit(RTL8367C_REG_L2_FLUSH_CTRL3, RTL8367C_L2_FLUSH_CTRL3_OFFSET, pBusyStatus); +} + +/* Function Name: + * rtl8367c_setAsicLutForceFlush + * Description: + * Set per port force flush setting + * Input: + * portmask - portmask(0~0xFF) + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Invalid portmask + * Note: + * None + */ + /*port8~port10µÄÉèÖÃÔÚÁíÍâÒ»¸öregister, wait for updating of base.h, reg.h*/ +ret_t rtl8367c_setAsicLutForceFlush(rtk_uint32 portmask) +{ + ret_t retVal; + + if(portmask > RTL8367C_PORTMASK) + return RT_ERR_PORT_MASK; + + retVal = rtl8367c_setAsicRegBits(RTL8367C_FORCE_FLUSH_REG, RTL8367C_FORCE_FLUSH_PORTMASK_MASK, portmask & 0xff); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_FORCE_FLUSH1, RTL8367C_PORTMASK1_MASK, (portmask >> 8) & 0x7); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} +/* Function Name: + * rtl8367c_getAsicLutForceFlushStatus + * Description: + * Get per port force flush status + * Input: + * pPortmask - portmask(0~0xFF) + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ + /*port8~port10µÄÉèÖÃÔÚÁíÍâÒ»¸öregister, wait for updating of base.h, reg.h*/ +ret_t rtl8367c_getAsicLutForceFlushStatus(rtk_uint32 *pPortmask) +{ + rtk_uint32 tmpMask; + ret_t retVal; + + retVal = rtl8367c_getAsicRegBits(RTL8367C_FORCE_FLUSH_REG, RTL8367C_BUSY_STATUS_MASK,&tmpMask); + if(retVal != RT_ERR_OK) + return retVal; + *pPortmask = tmpMask & 0xff; + + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_FORCE_FLUSH1, RTL8367C_BUSY_STATUS1_MASK,&tmpMask); + if(retVal != RT_ERR_OK) + return retVal; + *pPortmask |= (tmpMask & 7) << 8; + + return RT_ERR_OK; +} +/* Function Name: + * rtl8367c_setAsicLutFlushMode + * Description: + * Set user force L2 pLutSt table flush mode + * Input: + * mode - 0:Port based 1: Port + VLAN based 2:Port + FID/MSTI based + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Actions not allowed by the function + * Note: + * None + */ +ret_t rtl8367c_setAsicLutFlushMode(rtk_uint32 mode) +{ + if( mode >= FLUSHMDOE_END ) + return RT_ERR_NOT_ALLOWED; + + return rtl8367c_setAsicRegBits(RTL8367C_REG_L2_FLUSH_CTRL2, RTL8367C_LUT_FLUSH_MODE_MASK, mode); +} +/* Function Name: + * rtl8367c_getAsicLutFlushMode + * Description: + * Get user force L2 pLutSt table flush mode + * Input: + * pMode - 0:Port based 1: Port + VLAN based 2:Port + FID/MSTI based + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicLutFlushMode(rtk_uint32* pMode) +{ + return rtl8367c_getAsicRegBits(RTL8367C_REG_L2_FLUSH_CTRL2, RTL8367C_LUT_FLUSH_MODE_MASK, pMode); +} +/* Function Name: + * rtl8367c_setAsicLutFlushType + * Description: + * Get L2 LUT flush type + * Input: + * type - 0: dynamice unicast; 1: both dynamic and static unicast entry + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicLutFlushType(rtk_uint32 type) +{ + return rtl8367c_setAsicRegBit(RTL8367C_REG_L2_FLUSH_CTRL2, RTL8367C_LUT_FLUSH_TYPE_OFFSET,type); +} +/* Function Name: + * rtl8367c_getAsicLutFlushType + * Description: + * Set L2 LUT flush type + * Input: + * pType - 0: dynamice unicast; 1: both dynamic and static unicast entry + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicLutFlushType(rtk_uint32* pType) +{ + return rtl8367c_getAsicRegBit(RTL8367C_REG_L2_FLUSH_CTRL2, RTL8367C_LUT_FLUSH_TYPE_OFFSET,pType); +} + + +/* Function Name: + * rtl8367c_setAsicLutFlushVid + * Description: + * Set VID of Port + VID pLutSt flush mode + * Input: + * vid - Vid (0~4095) + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_VLAN_VID - Invalid VID parameter (0~4095) + * Note: + * None + */ +ret_t rtl8367c_setAsicLutFlushVid(rtk_uint32 vid) +{ + if( vid > RTL8367C_VIDMAX ) + return RT_ERR_VLAN_VID; + + return rtl8367c_setAsicRegBits(RTL8367C_REG_L2_FLUSH_CTRL1, RTL8367C_LUT_FLUSH_VID_MASK, vid); +} +/* Function Name: + * rtl8367c_getAsicLutFlushVid + * Description: + * Get VID of Port + VID pLutSt flush mode + * Input: + * pVid - Vid (0~4095) + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicLutFlushVid(rtk_uint32* pVid) +{ + return rtl8367c_getAsicRegBits(RTL8367C_REG_L2_FLUSH_CTRL1, RTL8367C_LUT_FLUSH_VID_MASK, pVid); +} +/* Function Name: + * rtl8367c_setAsicPortFlusdFid + * Description: + * Set FID of Port + FID pLutSt flush mode + * Input: + * fid - FID/MSTI for force flush + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_FID - Invalid FID (0~15) + * Note: + * None + */ +ret_t rtl8367c_setAsicLutFlushFid(rtk_uint32 fid) +{ + if( fid > RTL8367C_FIDMAX ) + return RT_ERR_L2_FID; + + return rtl8367c_setAsicRegBits(RTL8367C_REG_L2_FLUSH_CTRL1, RTL8367C_LUT_FLUSH_FID_MASK, fid); +} +/* Function Name: + * rtl8367c_getAsicLutFlushFid + * Description: + * Get FID of Port + FID pLutSt flush mode + * Input: + * pFid - FID/MSTI for force flush + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicLutFlushFid(rtk_uint32* pFid) +{ + return rtl8367c_getAsicRegBits(RTL8367C_REG_L2_FLUSH_CTRL1, RTL8367C_LUT_FLUSH_FID_MASK, pFid); +} +/* Function Name: + * rtl8367c_setAsicLutDisableAging + * Description: + * Set L2 LUT aging per port setting + * Input: + * port - Physical port number (0~7) + * disabled - 0: enable aging; 1: disabling aging + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ + /*ÐÞ¸ÄRTL8367C_PORTIDMAX*/ +ret_t rtl8367c_setAsicLutDisableAging(rtk_uint32 port, rtk_uint32 disabled) +{ + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + return rtl8367c_setAsicRegBit(RTL8367C_LUT_AGEOUT_CTRL_REG, port, disabled); +} +/* Function Name: + * rtl8367c_getAsicLutDisableAging + * Description: + * Get L2 LUT aging per port setting + * Input: + * port - Physical port number (0~7) + * pDisabled - 0: enable aging; 1: disabling aging + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ + /*ÐÞ¸ÄRTL8367C_PORTIDMAX*/ +ret_t rtl8367c_getAsicLutDisableAging(rtk_uint32 port, rtk_uint32 *pDisabled) +{ + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + return rtl8367c_getAsicRegBit(RTL8367C_LUT_AGEOUT_CTRL_REG, port, pDisabled); +} + +/* Function Name: + * rtl8367c_setAsicLutIPMCGroup + * Description: + * Set IPMC Group Table + * Input: + * index - the entry index in table (0 ~ 63) + * group_addr - the multicast group address (224.0.0.0 ~ 239.255.255.255) + * vid - VLAN ID + * pmask - portmask + * valid - valid bit + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid parameter + * Note: + * None + */ +ret_t rtl8367c_setAsicLutIPMCGroup(rtk_uint32 index, ipaddr_t group_addr, rtk_uint32 vid, rtk_uint32 pmask, rtk_uint32 valid) +{ + rtk_uint32 regAddr, regData, bitoffset; + ipaddr_t ipData; + ret_t retVal; + + if(index > RTL8367C_LUT_IPMCGRP_TABLE_MAX) + return RT_ERR_INPUT; + + if (vid > RTL8367C_VIDMAX) + return RT_ERR_VLAN_VID; + + ipData = group_addr; + + if( (ipData & 0xF0000000) != 0xE0000000) /* not in 224.0.0.0 ~ 239.255.255.255 */ + return RT_ERR_INPUT; + + /* Group Address */ + regAddr = RTL8367C_REG_IPMC_GROUP_ENTRY0_H + (index * 2); + regData = ((ipData & 0x0FFFFFFF) >> 16); + + if( (retVal = rtl8367c_setAsicReg(regAddr, regData)) != RT_ERR_OK) + return retVal; + + regAddr++; + regData = (ipData & 0x0000FFFF); + + if( (retVal = rtl8367c_setAsicReg(regAddr, regData)) != RT_ERR_OK) + return retVal; + + /* VID */ + regAddr = RTL8367C_REG_IPMC_GROUP_VID_00 + index; + regData = vid; + + if( (retVal = rtl8367c_setAsicReg(regAddr, regData)) != RT_ERR_OK) + return retVal; + + /* portmask */ + regAddr = RTL8367C_REG_IPMC_GROUP_PMSK_00 + index; + regData = pmask; + + if( (retVal = rtl8367c_setAsicReg(regAddr, regData)) != RT_ERR_OK) + return retVal; + + /* valid */ + regAddr = RTL8367C_REG_IPMC_GROUP_VALID_15_0 + (index / 16); + bitoffset = index % 16; + if( (retVal = rtl8367c_setAsicRegBit(regAddr, bitoffset, valid)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_getAsicLutIPMCGroup + * Description: + * Set IPMC Group Table + * Input: + * index - the entry index in table (0 ~ 63) + * Output: + * pGroup_addr - the multicast group address (224.0.0.0 ~ 239.255.255.255) + * pVid - VLAN ID + * pPmask - portmask + * pValid - Valid bit + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid parameter + * Note: + * None + */ +ret_t rtl8367c_getAsicLutIPMCGroup(rtk_uint32 index, ipaddr_t *pGroup_addr, rtk_uint32 *pVid, rtk_uint32 *pPmask, rtk_uint32 *pValid) +{ + rtk_uint32 regAddr, regData, bitoffset; + ipaddr_t ipData; + ret_t retVal; + + if(index > RTL8367C_LUT_IPMCGRP_TABLE_MAX) + return RT_ERR_INPUT; + + if (NULL == pGroup_addr) + return RT_ERR_NULL_POINTER; + + if (NULL == pVid) + return RT_ERR_NULL_POINTER; + + if (NULL == pPmask) + return RT_ERR_NULL_POINTER; + + /* Group address */ + regAddr = RTL8367C_REG_IPMC_GROUP_ENTRY0_H + (index * 2); + if( (retVal = rtl8367c_getAsicReg(regAddr, ®Data)) != RT_ERR_OK) + return retVal; + + *pGroup_addr = (((regData & 0x00000FFF) << 16) | 0xE0000000); + + regAddr++; + if( (retVal = rtl8367c_getAsicReg(regAddr, ®Data)) != RT_ERR_OK) + return retVal; + + ipData = (*pGroup_addr | (regData & 0x0000FFFF)); + *pGroup_addr = ipData; + + /* VID */ + regAddr = RTL8367C_REG_IPMC_GROUP_VID_00 + index; + if( (retVal = rtl8367c_getAsicReg(regAddr, ®Data)) != RT_ERR_OK) + return retVal; + + *pVid = regData; + + /* portmask */ + regAddr = RTL8367C_REG_IPMC_GROUP_PMSK_00 + index; + if( (retVal = rtl8367c_getAsicReg(regAddr, ®Data)) != RT_ERR_OK) + return retVal; + + *pPmask = regData; + + /* valid */ + regAddr = RTL8367C_REG_IPMC_GROUP_VALID_15_0 + (index / 16); + bitoffset = index % 16; + if( (retVal = rtl8367c_getAsicRegBit(regAddr, bitoffset, ®Data)) != RT_ERR_OK) + return retVal; + + *pValid = regData; + + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_setAsicLutLinkDownForceAging + * Description: + * Set LUT link down aging setting. + * Input: + * enable - link down aging setting + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid parameter + * Note: + * None + */ +ret_t rtl8367c_setAsicLutLinkDownForceAging(rtk_uint32 enable) +{ + if(enable > 1) + return RT_ERR_ENABLE; + + return rtl8367c_setAsicRegBit(RTL8367C_REG_LUT_CFG, RTL8367C_LINKDOWN_AGEOUT_OFFSET, enable ? 0 : 1); +} + +/* Function Name: + * rtl8367c_getAsicLutLinkDownForceAging + * Description: + * Get LUT link down aging setting. + * Input: + * pEnable - link down aging setting + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid parameter + * Note: + * None + */ +ret_t rtl8367c_getAsicLutLinkDownForceAging(rtk_uint32 *pEnable) +{ + rtk_uint32 value; + ret_t retVal; + + if ((retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_LUT_CFG, RTL8367C_LINKDOWN_AGEOUT_OFFSET, &value)) != RT_ERR_OK) + return retVal; + + *pEnable = value ? 0 : 1; + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_setAsicLutIpmcFwdRouterPort + * Description: + * Set IPMC packet forward to rounter port also or not + * Input: + * enable - 1: Inlcude router port, 0, exclude router port + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE Invalid parameter + * Note: + * None + */ +ret_t rtl8367c_setAsicLutIpmcFwdRouterPort(rtk_uint32 enable) +{ + if(enable > 1) + return RT_ERR_ENABLE; + + return rtl8367c_setAsicRegBit(RTL8367C_REG_LUT_CFG2, RTL8367C_LUT_IPMC_FWD_RPORT_OFFSET, enable); +} + +/* Function Name: + * rtl8367c_getAsicLutIpmcFwdRouterPort + * Description: + * Get IPMC packet forward to rounter port also or not + * Input: + * None + * Output: + * pEnable - 1: Inlcude router port, 0, exclude router port + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * None + */ +ret_t rtl8367c_getAsicLutIpmcFwdRouterPort(rtk_uint32 *pEnable) +{ + if(NULL == pEnable) + return RT_ERR_NULL_POINTER; + + return rtl8367c_getAsicRegBit(RTL8367C_REG_LUT_CFG2, RTL8367C_LUT_IPMC_FWD_RPORT_OFFSET, pEnable); +} + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_lut.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_lut.h new file mode 100644 index 00000000..1340e9a1 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_lut.h @@ -0,0 +1,141 @@ +#ifndef _RTL8367C_ASICDRV_LUT_H_ +#define _RTL8367C_ASICDRV_LUT_H_ + +#include + +#define RTL8367C_LUT_AGETIMERMAX (7) +#define RTL8367C_LUT_AGESPEEDMAX (3) +#define RTL8367C_LUT_LEARNLIMITMAX (0x1040) +#define RTL8367C_LUT_ADDRMAX (0x103F) +#define RTL8367C_LUT_IPMCGRP_TABLE_MAX (0x3F) +#define RTL8367C_LUT_ENTRY_SIZE (6) +#define RTL8367C_LUT_BUSY_CHECK_NO (10) + +#define RTL8367C_LUT_TABLE_SIZE (6) + +enum RTL8367C_LUTHASHMETHOD{ + + LUTHASHMETHOD_SVL=0, + LUTHASHMETHOD_IVL, + LUTHASHMETHOD_END, +}; + + +enum RTL8367C_LRNOVERACT{ + + LRNOVERACT_FORWARD=0, + LRNOVERACT_DROP, + LRNOVERACT_TRAP, + LRNOVERACT_END, +}; + +enum RTL8367C_LUTREADMETHOD{ + + LUTREADMETHOD_MAC =0, + LUTREADMETHOD_ADDRESS, + LUTREADMETHOD_NEXT_ADDRESS, + LUTREADMETHOD_NEXT_L2UC, + LUTREADMETHOD_NEXT_L2MC, + LUTREADMETHOD_NEXT_L3MC, + LUTREADMETHOD_NEXT_L2L3MC, + LUTREADMETHOD_NEXT_L2UCSPA, +}; + +enum RTL8367C_FLUSHMODE +{ + FLUSHMDOE_PORT = 0, + FLUSHMDOE_VID, + FLUSHMDOE_FID, + FLUSHMDOE_END, +}; + +enum RTL8367C_FLUSHTYPE +{ + FLUSHTYPE_DYNAMIC = 0, + FLUSHTYPE_BOTH, + FLUSHTYPE_END, +}; + + +typedef struct LUTTABLE{ + + ipaddr_t sip; + ipaddr_t dip; + ether_addr_t mac; + rtk_uint16 ivl_svl:1; + rtk_uint16 cvid_fid:12; + rtk_uint16 fid:4; + rtk_uint16 efid:3; + + rtk_uint16 nosalearn:1; + rtk_uint16 da_block:1; + rtk_uint16 sa_block:1; + rtk_uint16 auth:1; + rtk_uint16 lut_pri:3; + rtk_uint16 sa_en:1; + rtk_uint16 fwd_en:1; + rtk_uint16 mbr:11; + rtk_uint16 spa:4; + rtk_uint16 age:3; + rtk_uint16 l3lookup:1; + rtk_uint16 igmp_asic:1; + rtk_uint16 igmpidx:8; + + rtk_uint16 lookup_hit:1; + rtk_uint16 lookup_busy:1; + rtk_uint16 address:13; + + rtk_uint16 l3vidlookup:1; + rtk_uint16 l3_vid:12; + + rtk_uint16 wait_time; + +}rtl8367c_luttb; + +extern ret_t rtl8367c_setAsicLutIpMulticastLookup(rtk_uint32 enabled); +extern ret_t rtl8367c_getAsicLutIpMulticastLookup(rtk_uint32* pEnabled); +extern ret_t rtl8367c_setAsicLutIpMulticastVidLookup(rtk_uint32 enabled); +extern ret_t rtl8367c_getAsicLutIpMulticastVidLookup(rtk_uint32* pEnabled); +extern ret_t rtl8367c_setAsicLutAgeTimerSpeed(rtk_uint32 timer, rtk_uint32 speed); +extern ret_t rtl8367c_getAsicLutAgeTimerSpeed(rtk_uint32* pTimer, rtk_uint32* pSpeed); +extern ret_t rtl8367c_setAsicLutCamTbUsage(rtk_uint32 enabled); +extern ret_t rtl8367c_getAsicLutCamTbUsage(rtk_uint32* pEnabled); +extern ret_t rtl8367c_getAsicLutCamType(rtk_uint32* pType); +extern ret_t rtl8367c_setAsicLutLearnLimitNo(rtk_uint32 port, rtk_uint32 number); +extern ret_t rtl8367c_getAsicLutLearnLimitNo(rtk_uint32 port, rtk_uint32* pNumber); +extern ret_t rtl8367c_setAsicSystemLutLearnLimitNo(rtk_uint32 number); +extern ret_t rtl8367c_getAsicSystemLutLearnLimitNo(rtk_uint32 *pNumber); +extern ret_t rtl8367c_setAsicLutLearnOverAct(rtk_uint32 action); +extern ret_t rtl8367c_getAsicLutLearnOverAct(rtk_uint32* pAction); +extern ret_t rtl8367c_setAsicSystemLutLearnOverAct(rtk_uint32 action); +extern ret_t rtl8367c_getAsicSystemLutLearnOverAct(rtk_uint32 *pAction); +extern ret_t rtl8367c_setAsicSystemLutLearnPortMask(rtk_uint32 portmask); +extern ret_t rtl8367c_getAsicSystemLutLearnPortMask(rtk_uint32 *pPortmask); +extern ret_t rtl8367c_setAsicL2LookupTb(rtl8367c_luttb *pL2Table); +extern ret_t rtl8367c_getAsicL2LookupTb(rtk_uint32 method, rtl8367c_luttb *pL2Table); +extern ret_t rtl8367c_getAsicLutLearnNo(rtk_uint32 port, rtk_uint32* pNumber); +extern ret_t rtl8367c_setAsicLutIpLookupMethod(rtk_uint32 type); +extern ret_t rtl8367c_getAsicLutIpLookupMethod(rtk_uint32* pType); +extern ret_t rtl8367c_setAsicLutForceFlush(rtk_uint32 portmask); +extern ret_t rtl8367c_getAsicLutForceFlushStatus(rtk_uint32 *pPortmask); +extern ret_t rtl8367c_setAsicLutFlushMode(rtk_uint32 mode); +extern ret_t rtl8367c_getAsicLutFlushMode(rtk_uint32* pMode); +extern ret_t rtl8367c_setAsicLutFlushType(rtk_uint32 type); +extern ret_t rtl8367c_getAsicLutFlushType(rtk_uint32* pType); +extern ret_t rtl8367c_setAsicLutFlushVid(rtk_uint32 vid); +extern ret_t rtl8367c_getAsicLutFlushVid(rtk_uint32* pVid); +extern ret_t rtl8367c_setAsicLutFlushFid(rtk_uint32 fid); +extern ret_t rtl8367c_getAsicLutFlushFid(rtk_uint32* pFid); +extern ret_t rtl8367c_setAsicLutDisableAging(rtk_uint32 port, rtk_uint32 disabled); +extern ret_t rtl8367c_getAsicLutDisableAging(rtk_uint32 port, rtk_uint32 *pDisabled); +extern ret_t rtl8367c_setAsicLutIPMCGroup(rtk_uint32 index, ipaddr_t group_addr, rtk_uint32 vid, rtk_uint32 pmask, rtk_uint32 valid); +extern ret_t rtl8367c_getAsicLutIPMCGroup(rtk_uint32 index, ipaddr_t *pGroup_addr, rtk_uint32 *pVid, rtk_uint32 *pPmask, rtk_uint32 *pValid); +extern ret_t rtl8367c_setAsicLutLinkDownForceAging(rtk_uint32 enable); +extern ret_t rtl8367c_getAsicLutLinkDownForceAging(rtk_uint32 *pEnable); +extern ret_t rtl8367c_setAsicLutFlushAll(void); +extern ret_t rtl8367c_getAsicLutFlushAllStatus(rtk_uint32 *pBusyStatus); +extern ret_t rtl8367c_setAsicLutIpmcFwdRouterPort(rtk_uint32 enable); +extern ret_t rtl8367c_getAsicLutIpmcFwdRouterPort(rtk_uint32 *pEnable); + +#endif /*_RTL8367C_ASICDRV_LUT_H_*/ + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_meter.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_meter.c new file mode 100644 index 00000000..858a631d --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_meter.c @@ -0,0 +1,307 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTL8367C switch high-level API for RTL8367C + * Feature : Shared meter related functions + * + */ +#include +/* Function Name: + * rtl8367c_setAsicShareMeter + * Description: + * Set meter configuration + * Input: + * index - hared meter index (0-31) + * rate - 17-bits rate of share meter, unit is 8Kpbs + * ifg - Including IFG in rate calculation, 1:include 0:exclude + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_METER_ID - Invalid meter + * Note: + * None + */ +ret_t rtl8367c_setAsicShareMeter(rtk_uint32 index, rtk_uint32 rate, rtk_uint32 ifg) +{ + ret_t retVal; + + if(index > RTL8367C_METERMAX) + return RT_ERR_FILTER_METER_ID; + + if(index < 32) + { + /*19-bits Rate*/ + retVal = rtl8367c_setAsicReg(RTL8367C_METER_RATE_REG(index), rate&0xFFFF); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8367c_setAsicReg(RTL8367C_METER_RATE_REG(index) + 1, (rate &0x70000) >> 16); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8367c_setAsicRegBit(RTL8367C_METER_IFG_CTRL_REG(index), RTL8367C_METER_IFG_OFFSET(index), ifg); + if(retVal != RT_ERR_OK) + return retVal; + } + else + { + /*19-bits Rate*/ + retVal = rtl8367c_setAsicReg(RTL8367C_REG_METER32_RATE_CTRL0 + ((index-32) << 1), rate&0xFFFF); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8367c_setAsicReg(RTL8367C_REG_METER32_RATE_CTRL0 + ((index-32) << 1) + 1, (rate &0x70000) >> 16); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_METER_IFG_CTRL2 + ((index-32) >> 4), RTL8367C_METER_IFG_OFFSET(index), ifg); + if(retVal != RT_ERR_OK) + return retVal; + } + + return RT_ERR_OK; +} +/* Function Name: + * rtl8367c_getAsicShareMeter + * Description: + * Get meter configuration + * Input: + * index - hared meter index (0-31) + * pRate - 17-bits rate of share meter, unit is 8Kpbs + * pIfg - Including IFG in rate calculation, 1:include 0:exclude + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_METER_ID - Invalid meter + * Note: + * None + */ +ret_t rtl8367c_getAsicShareMeter(rtk_uint32 index, rtk_uint32 *pRate, rtk_uint32 *pIfg) +{ + rtk_uint32 regData; + rtk_uint32 regData2; + ret_t retVal; + + if(index > RTL8367C_METERMAX) + return RT_ERR_FILTER_METER_ID; + + if(index < 32) + { + /*17-bits Rate*/ + retVal = rtl8367c_getAsicReg(RTL8367C_METER_RATE_REG(index), ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8367c_getAsicReg(RTL8367C_METER_RATE_REG(index) + 1, ®Data2); + if(retVal != RT_ERR_OK) + return retVal; + + *pRate = ((regData2 << 16) & 0x70000) | regData; + /*IFG*/ + retVal = rtl8367c_getAsicRegBit(RTL8367C_METER_IFG_CTRL_REG(index), RTL8367C_METER_IFG_OFFSET(index), pIfg); + + return retVal; + } + else + { + /*17-bits Rate*/ + retVal = rtl8367c_getAsicReg(RTL8367C_REG_METER32_RATE_CTRL0 + ((index-32) << 1), ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8367c_getAsicReg(RTL8367C_REG_METER32_RATE_CTRL0 + ((index-32) << 1) + 1, ®Data2); + if(retVal != RT_ERR_OK) + return retVal; + + *pRate = ((regData2 << 16) & 0x70000) | regData; + /*IFG*/ + retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_METER_IFG_CTRL2 + ((index-32) >> 4), RTL8367C_METER_IFG_OFFSET(index), pIfg); + + return retVal; + } +} +/* Function Name: + * rtl8367c_setAsicShareMeterBucketSize + * Description: + * Set meter related leaky bucket threshold + * Input: + * index - hared meter index (0-31) + * lbthreshold - Leaky bucket threshold of meter + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_METER_ID - Invalid meter + * Note: + * None + */ +ret_t rtl8367c_setAsicShareMeterBucketSize(rtk_uint32 index, rtk_uint32 lbthreshold) +{ + + if(index > RTL8367C_METERMAX) + return RT_ERR_FILTER_METER_ID; + + if(index < 32) + return rtl8367c_setAsicReg(RTL8367C_METER_BUCKET_SIZE_REG(index), lbthreshold); + else + return rtl8367c_setAsicReg(RTL8367C_REG_METER32_BUCKET_SIZE + index - 32, lbthreshold); +} +/* Function Name: + * rtl8367c_getAsicShareMeterBucketSize + * Description: + * Get meter related leaky bucket threshold + * Input: + * index - hared meter index (0-31) + * pLbthreshold - Leaky bucket threshold of meter + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_METER_ID - Invalid meter + * Note: + * None + */ +ret_t rtl8367c_getAsicShareMeterBucketSize(rtk_uint32 index, rtk_uint32 *pLbthreshold) +{ + if(index > RTL8367C_METERMAX) + return RT_ERR_FILTER_METER_ID; + + if(index < 32) + return rtl8367c_getAsicReg(RTL8367C_METER_BUCKET_SIZE_REG(index), pLbthreshold); + else + return rtl8367c_getAsicReg(RTL8367C_REG_METER32_BUCKET_SIZE + index - 32, pLbthreshold); +} + +/* Function Name: + * rtl8367c_setAsicShareMeterType + * Description: + * Set meter Type + * Input: + * index - shared meter index (0-31) + * Type - 0: kbps, 1: pps + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_METER_ID - Invalid meter + * Note: + * None + */ +ret_t rtl8367c_setAsicShareMeterType(rtk_uint32 index, rtk_uint32 type) +{ + rtk_uint32 reg; + + if(index > RTL8367C_METERMAX) + return RT_ERR_FILTER_METER_ID; + + if(index < 32) + reg = RTL8367C_REG_METER_MODE_SETTING0 + (index / 16); + else + reg = RTL8367C_REG_METER_MODE_SETTING2 + ((index - 32) / 16); + return rtl8367c_setAsicRegBit(reg, index % 16, type); +} + +/* Function Name: + * rtl8367c_getAsicShareMeterType + * Description: + * Get meter Type + * Input: + * index - shared meter index (0-31) + * Output: + * pType - 0: kbps, 1: pps + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_METER_ID - Invalid meter + * Note: + * None + */ +ret_t rtl8367c_getAsicShareMeterType(rtk_uint32 index, rtk_uint32 *pType) +{ + rtk_uint32 reg; + + if(index > RTL8367C_METERMAX) + return RT_ERR_FILTER_METER_ID; + + if(NULL == pType) + return RT_ERR_NULL_POINTER; + + if(index < 32) + reg = RTL8367C_REG_METER_MODE_SETTING0 + (index / 16); + else + reg = RTL8367C_REG_METER_MODE_SETTING2 + ((index - 32) / 16); + return rtl8367c_getAsicRegBit(reg, index % 16, pType); +} + + +/* Function Name: + * rtl8367c_setAsicMeterExceedStatus + * Description: + * Clear shared meter status + * Input: + * index - hared meter index (0-31) + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_METER_ID - Invalid meter + * Note: + * None + */ +ret_t rtl8367c_setAsicMeterExceedStatus(rtk_uint32 index) +{ + if(index > RTL8367C_METERMAX) + return RT_ERR_FILTER_METER_ID; + + if(index < 32) + return rtl8367c_setAsicRegBit(RTL8367C_METER_OVERRATE_INDICATOR_REG(index), RTL8367C_METER_EXCEED_OFFSET(index), 1); + else + return rtl8367c_setAsicRegBit(RTL8367C_REG_METER_OVERRATE_INDICATOR2 + ((index - 32) >> 4), RTL8367C_METER_EXCEED_OFFSET(index), 1); + +} +/* Function Name: + * rtl8367c_getAsicMeterExceedStatus + * Description: + * Get shared meter status + * Input: + * index - hared meter index (0-31) + * pStatus - 0: rate doesn't exceed 1: rate exceeds + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_METER_ID - Invalid meter + * Note: + * If rate is over rate*8Kbps of a meter, the state bit of this meter is set to 1. + */ +ret_t rtl8367c_getAsicMeterExceedStatus(rtk_uint32 index, rtk_uint32* pStatus) +{ + if(index > RTL8367C_METERMAX) + return RT_ERR_FILTER_METER_ID; + + if(index < 32) + return rtl8367c_getAsicRegBit(RTL8367C_METER_OVERRATE_INDICATOR_REG(index), RTL8367C_METER_EXCEED_OFFSET(index), pStatus); + else + return rtl8367c_getAsicRegBit(RTL8367C_REG_METER_OVERRATE_INDICATOR2 + ((index - 32) >> 4), RTL8367C_METER_EXCEED_OFFSET(index), pStatus); +} + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_meter.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_meter.h new file mode 100644 index 00000000..a3da8a52 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_meter.h @@ -0,0 +1,17 @@ +#ifndef _RTL8367C_ASICDRV_METER_H_ +#define _RTL8367C_ASICDRV_METER_H_ + +#include + + +extern ret_t rtl8367c_setAsicShareMeter(rtk_uint32 index, rtk_uint32 rate, rtk_uint32 ifg); +extern ret_t rtl8367c_getAsicShareMeter(rtk_uint32 index, rtk_uint32 *pRate, rtk_uint32 *pIfg); +extern ret_t rtl8367c_setAsicShareMeterBucketSize(rtk_uint32 index, rtk_uint32 lbThreshold); +extern ret_t rtl8367c_getAsicShareMeterBucketSize(rtk_uint32 index, rtk_uint32 *pLbThreshold); +extern ret_t rtl8367c_setAsicShareMeterType(rtk_uint32 index, rtk_uint32 type); +extern ret_t rtl8367c_getAsicShareMeterType(rtk_uint32 index, rtk_uint32 *pType); +extern ret_t rtl8367c_setAsicMeterExceedStatus(rtk_uint32 index); +extern ret_t rtl8367c_getAsicMeterExceedStatus(rtk_uint32 index, rtk_uint32* pStatus); + +#endif /*_RTL8367C_ASICDRV_FC_H_*/ + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_mib.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_mib.c new file mode 100644 index 00000000..1badef44 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_mib.c @@ -0,0 +1,637 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTL8367C switch high-level API for RTL8367C + * Feature : MIB related functions + * + */ +#include +/* Function Name: + * rtl8367c_setAsicMIBsCounterReset + * Description: + * Reset global/queue manage or per-port MIB counter + * Input: + * greset - Global reset + * qmreset - Queue maganement reset + * portmask - Port reset mask + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicMIBsCounterReset(rtk_uint32 greset, rtk_uint32 qmreset, rtk_uint32 portmask) +{ + ret_t retVal; + rtk_uint32 regData; + rtk_uint32 regBits; + + regBits = RTL8367C_GLOBAL_RESET_MASK | + RTL8367C_QM_RESET_MASK | + RTL8367C_MIB_PORT07_MASK | + ((rtk_uint32)0x7 << 13); + regData = ((greset << RTL8367C_GLOBAL_RESET_OFFSET) & RTL8367C_GLOBAL_RESET_MASK) | + ((qmreset << RTL8367C_QM_RESET_OFFSET) & RTL8367C_QM_RESET_MASK) | + (((portmask & 0xFF) << RTL8367C_PORT0_RESET_OFFSET) & RTL8367C_MIB_PORT07_MASK) | + (((portmask >> 8)&0x7) << 13); + + + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_MIB_CTRL0, regBits, (regData >> RTL8367C_PORT0_RESET_OFFSET)); + + return retVal; +} +/* Function Name: + * rtl8367c_getAsicMIBsCounter + * Description: + * Get MIBs counter + * Input: + * port - Physical port number (0~7) + * mibIdx - MIB counter index + * pCounter - MIB retrived counter + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * RT_ERR_BUSYWAIT_TIMEOUT - MIB is busy at retrieving + * RT_ERR_STAT_CNTR_FAIL - MIB is resetting + * Note: + * Before MIBs counter retrieving, writting accessing address to ASIC at first and check the MIB + * control register status. If busy bit of MIB control is set, that means MIB counter have been + * waiting for preparing, then software must wait atfer this busy flag reset by ASIC. This driver + * did not recycle reading user desired counter. Software must use driver again to get MIB counter + * if return value is not RT_ERR_OK. + */ +ret_t rtl8367c_getAsicMIBsCounter(rtk_uint32 port, RTL8367C_MIBCOUNTER mibIdx, rtk_uint64* pCounter) +{ + ret_t retVal; + rtk_uint32 regAddr; + rtk_uint32 regData; + rtk_uint32 mibAddr; + rtk_uint32 mibOff=0; + + /* address offset to MIBs counter */ + CONST rtk_uint16 mibLength[RTL8367C_MIBS_NUMBER]= { + 4,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2, + 4,2,2,2,2,2,2,2,2, + 4,2,2,2,2,2,2,2,2,2,2,2,2,2,2, + 2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2}; + + rtk_uint16 i; + rtk_uint64 mibCounter; + + + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + if(mibIdx >= RTL8367C_MIBS_NUMBER) + return RT_ERR_STAT_INVALID_CNTR; + + if(dot1dTpLearnedEntryDiscards == mibIdx) + { + mibAddr = RTL8367C_MIB_LEARNENTRYDISCARD_OFFSET; + } + else + { + i = 0; + mibOff = RTL8367C_MIB_PORT_OFFSET * port; + + if(port > 7) + mibOff = mibOff + 68; + + while(i < mibIdx) + { + mibOff += mibLength[i]; + i++; + } + + mibAddr = mibOff; + } + + /* Read MIB addr before writing */ + retVal = rtl8367c_getAsicReg(RTL8367C_REG_MIB_ADDRESS, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + if (regData == (mibAddr >> 2)) + { + /* Write MIB addr to an alternate value */ + retVal = rtl8367c_setAsicReg(RTL8367C_REG_MIB_ADDRESS, (mibAddr >> 2) + 1); + if(retVal != RT_ERR_OK) + return retVal; + + while(1) + { + retVal = rtl8367c_getAsicReg(RTL8367C_REG_MIB_ADDRESS, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + if(regData == ((mibAddr >> 2) + 1)) + { + break; + } + + retVal = rtl8367c_setAsicReg(RTL8367C_REG_MIB_ADDRESS, (mibAddr >> 2) + 1); + if(retVal != RT_ERR_OK) + return retVal; + } + + /* polling busy flag */ + i = 100; + while(i > 0) + { + /*read MIB control register*/ + retVal = rtl8367c_getAsicReg(RTL8367C_MIB_CTRL_REG,®Data); + if(retVal != RT_ERR_OK) + return retVal; + + if((regData & RTL8367C_MIB_CTRL0_BUSY_FLAG_MASK) == 0) + { + break; + } + + i--; + } + + if(regData & RTL8367C_MIB_CTRL0_BUSY_FLAG_MASK) + return RT_ERR_BUSYWAIT_TIMEOUT; + + if(regData & RTL8367C_RESET_FLAG_MASK) + return RT_ERR_STAT_CNTR_FAIL; + } + + /*writing access counter address first*/ + /*This address is SRAM address, and SRAM address = MIB register address >> 2*/ + /*then ASIC will prepare 64bits counter wait for being retrived*/ + /*Write Mib related address to access control register*/ + retVal = rtl8367c_setAsicReg(RTL8367C_REG_MIB_ADDRESS, (mibAddr >> 2)); + if(retVal != RT_ERR_OK) + return retVal; + + /* polling MIB Addr register */ + while(1) + { + retVal = rtl8367c_getAsicReg(RTL8367C_REG_MIB_ADDRESS, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + if(regData == (mibAddr >> 2)) + { + break; + } + + retVal = rtl8367c_setAsicReg(RTL8367C_REG_MIB_ADDRESS, (mibAddr >> 2)); + if(retVal != RT_ERR_OK) + return retVal; + } + + /* polling busy flag */ + i = 100; + while(i > 0) + { + /*read MIB control register*/ + retVal = rtl8367c_getAsicReg(RTL8367C_MIB_CTRL_REG,®Data); + if(retVal != RT_ERR_OK) + return retVal; + + if((regData & RTL8367C_MIB_CTRL0_BUSY_FLAG_MASK) == 0) + { + break; + } + + i--; + } + + if(regData & RTL8367C_MIB_CTRL0_BUSY_FLAG_MASK) + return RT_ERR_BUSYWAIT_TIMEOUT; + + if(regData & RTL8367C_RESET_FLAG_MASK) + return RT_ERR_STAT_CNTR_FAIL; + + mibCounter = 0; + i = mibLength[mibIdx]; + if(4 == i) + regAddr = RTL8367C_MIB_COUNTER_BASE_REG + 3; + else + regAddr = RTL8367C_MIB_COUNTER_BASE_REG + ((mibOff + 1) % 4); + + while(i) + { + retVal = rtl8367c_getAsicReg(regAddr, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + mibCounter = (mibCounter << 16) | (regData & 0xFFFF); + + regAddr --; + i --; + + } + + *pCounter = mibCounter; + + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_getAsicMIBsLogCounter + * Description: + * Get MIBs Loggin counter + * Input: + * index - The index of 32 logging counter (0 ~ 31) + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_ENTRY_INDEX - Wrong index + * RT_ERR_BUSYWAIT_TIMEOUT - MIB is busy at retrieving + * RT_ERR_STAT_CNTR_FAIL - MIB is resetting + * Note: + * This API get 32 logging counter + */ +ret_t rtl8367c_getAsicMIBsLogCounter(rtk_uint32 index, rtk_uint32 *pCounter) +{ + ret_t retVal; + rtk_uint32 regAddr; + rtk_uint32 regData; + rtk_uint32 mibAddr; + rtk_uint16 i; + rtk_uint64 mibCounter; + + if(index > RTL8367C_MIB_MAX_LOG_CNT_IDX) + return RT_ERR_ENTRY_INDEX; + + mibAddr = RTL8367C_MIB_LOG_CNT_OFFSET + ((index / 2) * 4); + + retVal = rtl8367c_setAsicReg(RTL8367C_REG_MIB_ADDRESS, (mibAddr >> 2)); + if(retVal != RT_ERR_OK) + return retVal; + + /*read MIB control register*/ + retVal = rtl8367c_getAsicReg(RTL8367C_MIB_CTRL_REG, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + if(regData & RTL8367C_MIB_CTRL0_BUSY_FLAG_MASK) + return RT_ERR_BUSYWAIT_TIMEOUT; + + if(regData & RTL8367C_RESET_FLAG_MASK) + return RT_ERR_STAT_CNTR_FAIL; + + mibCounter = 0; + if((index % 2) == 1) + regAddr = RTL8367C_MIB_COUNTER_BASE_REG + 3; + else + regAddr = RTL8367C_MIB_COUNTER_BASE_REG + 1; + + for(i = 0; i <= 1; i++) + { + retVal = rtl8367c_getAsicReg(regAddr, ®Data); + + if(retVal != RT_ERR_OK) + return retVal; + + mibCounter = (mibCounter << 16) | (regData & 0xFFFF); + + regAddr --; + } + + *pCounter = mibCounter; + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_getAsicMIBsControl + * Description: + * Get MIB control register + * Input: + * pMask - MIB control status mask bit[0]-busy bit[1] + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * Software need to check this control register atfer doing port resetting or global resetting + */ +ret_t rtl8367c_getAsicMIBsControl(rtk_uint32* pMask) +{ + ret_t retVal; + rtk_uint32 regData; + + retVal = rtl8367c_getAsicReg(RTL8367C_MIB_CTRL_REG, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + *pMask = regData & (RTL8367C_MIB_CTRL0_BUSY_FLAG_MASK | RTL8367C_RESET_FLAG_MASK); + + return RT_ERR_OK; +} +/* Function Name: + * rtl8367c_setAsicMIBsResetValue + * Description: + * Reset all counter to 0 or 1 + * Input: + * value - Reset to value 0 or 1 + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicMIBsResetValue(rtk_uint32 value) +{ + return rtl8367c_setAsicRegBit(RTL8367C_REG_MIB_CTRL0, RTL8367C_RESET_VALUE_OFFSET, value); +} +/* Function Name: + * rtl8367c_getAsicMIBsResetValue + * Description: + * Reset all counter to 0 or 1 + * Input: + * value - Reset to value 0 or 1 + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicMIBsResetValue(rtk_uint32* value) +{ + return rtl8367c_getAsicRegBit(RTL8367C_REG_MIB_CTRL0, RTL8367C_RESET_VALUE_OFFSET, value); +} + +/* Function Name: + * rtl8367c_setAsicMIBsUsageMode + * Description: + * MIB update mode + * Input: + * mode - 1: latch all MIBs by timer 0:normal free run counting + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicMIBsUsageMode(rtk_uint32 mode) +{ + return rtl8367c_setAsicRegBit(RTL8367C_REG_MIB_CTRL4, RTL8367C_MIB_USAGE_MODE_OFFSET, mode); +} +/* Function Name: + * rtl8367c_getAsicMIBsUsageMode + * Description: + * MIB update mode + * Input: + * pMode - 1: latch all MIBs by timer 0:normal free run counting + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicMIBsUsageMode(rtk_uint32* pMode) +{ + return rtl8367c_getAsicRegBit(RTL8367C_REG_MIB_CTRL4, RTL8367C_MIB_USAGE_MODE_OFFSET, pMode); +} + +/* Function Name: + * rtl8367c_setAsicMIBsTimer + * Description: + * MIB latching timer + * Input: + * timer - latch timer, unit 1 second + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicMIBsTimer(rtk_uint32 timer) +{ + return rtl8367c_setAsicRegBits(RTL8367C_REG_MIB_CTRL4, RTL8367C_MIB_TIMER_MASK, timer); +} +/* Function Name: + * rtl8367c_getAsicMIBsTimer + * Description: + * MIB latching timer + * Input: + * pTimer - latch timer, unit 1 second + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicMIBsTimer(rtk_uint32* pTimer) +{ + return rtl8367c_getAsicRegBits(RTL8367C_REG_MIB_CTRL4, RTL8367C_MIB_TIMER_MASK, pTimer); +} +/* Function Name: + * rtl8367c_setAsicMIBsLoggingMode + * Description: + * MIB logging counter mode + * Input: + * index - logging counter mode index (0~15) + * mode - 0:32-bits mode 1:64-bits mode + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - input parameter out of range + * Note: + * None + */ +ret_t rtl8367c_setAsicMIBsLoggingMode(rtk_uint32 index, rtk_uint32 mode) +{ + if(index > RTL8367C_MIB_MAX_LOG_MODE_IDX) + return RT_ERR_OUT_OF_RANGE; + + return rtl8367c_setAsicRegBit(RTL8367C_REG_MIB_CTRL3, index,mode); +} +/* Function Name: + * rtl8367c_getAsicMIBsLoggingMode + * Description: + * MIB logging counter mode + * Input: + * index - logging counter mode index (0~15) + * pMode - 0:32-bits mode 1:64-bits mode + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - input parameter out of range + * Note: + * None + */ +ret_t rtl8367c_getAsicMIBsLoggingMode(rtk_uint32 index, rtk_uint32* pMode) +{ + if(index > RTL8367C_MIB_MAX_LOG_MODE_IDX) + return RT_ERR_OUT_OF_RANGE; + + return rtl8367c_getAsicRegBit(RTL8367C_REG_MIB_CTRL3, index,pMode); +} + +/* Function Name: + * rtl8367c_setAsicMIBsLoggingType + * Description: + * MIB logging counter type + * Input: + * index - logging counter mode index (0~15) + * type - 0:Packet count 1:Byte count + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - input parameter out of range + * Note: + * None + */ +ret_t rtl8367c_setAsicMIBsLoggingType(rtk_uint32 index, rtk_uint32 type) +{ + if(index > RTL8367C_MIB_MAX_LOG_MODE_IDX) + return RT_ERR_OUT_OF_RANGE; + + return rtl8367c_setAsicRegBit(RTL8367C_REG_MIB_CTRL5, index,type); +} + +/* Function Name: + * rtl8367c_getAsicMIBsLoggingType + * Description: + * MIB logging counter type + * Input: + * index - logging counter mode index (0~15) + * pType - 0:Packet count 1:Byte count + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - input parameter out of range + * Note: + * None + */ +ret_t rtl8367c_getAsicMIBsLoggingType(rtk_uint32 index, rtk_uint32* pType) +{ + if(index > RTL8367C_MIB_MAX_LOG_MODE_IDX) + return RT_ERR_OUT_OF_RANGE; + + return rtl8367c_getAsicRegBit(RTL8367C_REG_MIB_CTRL5, index,pType); +} + +/* Function Name: + * rtl8367c_setAsicMIBsResetLoggingCounter + * Description: + * MIB logging counter type + * Input: + * index - logging counter index (0~31) + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - input parameter out of range + * Note: + * None + */ +ret_t rtl8367c_setAsicMIBsResetLoggingCounter(rtk_uint32 index) +{ + ret_t retVal; + + if(index > RTL8367C_MIB_MAX_LOG_CNT_IDX) + return RT_ERR_OUT_OF_RANGE; + + if(index < 16) + retVal = rtl8367c_setAsicReg(RTL8367C_REG_MIB_CTRL1, 1< + +#define RTL8367C_MIB_PORT_OFFSET (0x7C) +#define RTL8367C_MIB_LEARNENTRYDISCARD_OFFSET (0x420) + +#define RTL8367C_MAX_LOG_CNT_NUM (32) +#define RTL8367C_MIB_MAX_LOG_CNT_IDX (RTL8367C_MAX_LOG_CNT_NUM - 1) +#define RTL8367C_MIB_LOG_CNT_OFFSET (0x3E0) +#define RTL8367C_MIB_MAX_LOG_MODE_IDX (16-1) + +typedef enum RTL8367C_MIBCOUNTER_E{ + + /* RX */ + ifInOctets = 0, + + dot3StatsFCSErrors, + dot3StatsSymbolErrors, + dot3InPauseFrames, + dot3ControlInUnknownOpcodes, + + etherStatsFragments, + etherStatsJabbers, + ifInUcastPkts, + etherStatsDropEvents, + + ifInMulticastPkts, + ifInBroadcastPkts, + inMldChecksumError, + inIgmpChecksumError, + inMldSpecificQuery, + inMldGeneralQuery, + inIgmpSpecificQuery, + inIgmpGeneralQuery, + inMldLeaves, + inIgmpLeaves, + + /* TX/RX */ + etherStatsOctets, + + etherStatsUnderSizePkts, + etherOversizeStats, + etherStatsPkts64Octets, + etherStatsPkts65to127Octets, + etherStatsPkts128to255Octets, + etherStatsPkts256to511Octets, + etherStatsPkts512to1023Octets, + etherStatsPkts1024to1518Octets, + + /* TX */ + ifOutOctets, + + dot3StatsSingleCollisionFrames, + dot3StatMultipleCollisionFrames, + dot3sDeferredTransmissions, + dot3StatsLateCollisions, + etherStatsCollisions, + dot3StatsExcessiveCollisions, + dot3OutPauseFrames, + ifOutDiscards, + + /* ALE */ + dot1dTpPortInDiscards, + ifOutUcastPkts, + ifOutMulticastPkts, + ifOutBroadcastPkts, + outOampduPkts, + inOampduPkts, + + inIgmpJoinsSuccess, + inIgmpJoinsFail, + inMldJoinsSuccess, + inMldJoinsFail, + inReportSuppressionDrop, + inLeaveSuppressionDrop, + outIgmpReports, + outIgmpLeaves, + outIgmpGeneralQuery, + outIgmpSpecificQuery, + outMldReports, + outMldLeaves, + outMldGeneralQuery, + outMldSpecificQuery, + inKnownMulticastPkts, + + /*Device only */ + dot1dTpLearnedEntryDiscards, + RTL8367C_MIBS_NUMBER, + +}RTL8367C_MIBCOUNTER; + + +extern ret_t rtl8367c_setAsicMIBsCounterReset(rtk_uint32 greset, rtk_uint32 qmreset, rtk_uint32 pmask); +extern ret_t rtl8367c_getAsicMIBsCounter(rtk_uint32 port,RTL8367C_MIBCOUNTER mibIdx, rtk_uint64* pCounter); +extern ret_t rtl8367c_getAsicMIBsLogCounter(rtk_uint32 index, rtk_uint32 *pCounter); +extern ret_t rtl8367c_getAsicMIBsControl(rtk_uint32* pMask); + +extern ret_t rtl8367c_setAsicMIBsResetValue(rtk_uint32 value); +extern ret_t rtl8367c_getAsicMIBsResetValue(rtk_uint32* value); + +extern ret_t rtl8367c_setAsicMIBsUsageMode(rtk_uint32 mode); +extern ret_t rtl8367c_getAsicMIBsUsageMode(rtk_uint32* pMode); +extern ret_t rtl8367c_setAsicMIBsTimer(rtk_uint32 timer); +extern ret_t rtl8367c_getAsicMIBsTimer(rtk_uint32* pTimer); +extern ret_t rtl8367c_setAsicMIBsLoggingMode(rtk_uint32 index, rtk_uint32 mode); +extern ret_t rtl8367c_getAsicMIBsLoggingMode(rtk_uint32 index, rtk_uint32* pMode); +extern ret_t rtl8367c_setAsicMIBsLoggingType(rtk_uint32 index, rtk_uint32 type); +extern ret_t rtl8367c_getAsicMIBsLoggingType(rtk_uint32 index, rtk_uint32* pType); +extern ret_t rtl8367c_setAsicMIBsResetLoggingCounter(rtk_uint32 index); +extern ret_t rtl8367c_setAsicMIBsLength(rtk_uint32 txLengthMode, rtk_uint32 rxLengthMode); +extern ret_t rtl8367c_getAsicMIBsLength(rtk_uint32 *pTxLengthMode, rtk_uint32 *pRxLengthMode); + +#endif /*#ifndef _RTL8367C_ASICDRV_MIB_H_*/ + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_mirror.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_mirror.c new file mode 100644 index 00000000..17fcb975 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_mirror.c @@ -0,0 +1,474 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTL8367C switch high-level API for RTL8367C + * Feature : Port mirror related functions + * + */ +#include +/* Function Name: + * rtl8367c_setAsicPortMirror + * Description: + * Set port mirror function + * Input: + * source - Source port + * monitor - Monitor (destination) port + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_setAsicPortMirror(rtk_uint32 source, rtk_uint32 monitor) +{ + ret_t retVal; + + if((source > RTL8367C_PORTIDMAX) || (monitor > RTL8367C_PORTIDMAX)) + return RT_ERR_PORT_ID; + + retVal = rtl8367c_setAsicRegBits(RTL8367C_MIRROR_CTRL_REG, RTL8367C_MIRROR_SOURCE_PORT_MASK, source); + if(retVal != RT_ERR_OK) + return retVal; + + + return rtl8367c_setAsicRegBits(RTL8367C_MIRROR_CTRL_REG, RTL8367C_MIRROR_MONITOR_PORT_MASK, monitor); +} +/* Function Name: + * rtl8367c_getAsicPortMirror + * Description: + * Get port mirror function + * Input: + * pSource - Source port + * pMonitor - Monitor (destination) port + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicPortMirror(rtk_uint32 *pSource, rtk_uint32 *pMonitor) +{ + ret_t retVal; + + retVal = rtl8367c_getAsicRegBits(RTL8367C_MIRROR_CTRL_REG, RTL8367C_MIRROR_SOURCE_PORT_MASK, pSource); + if(retVal != RT_ERR_OK) + return retVal; + + return rtl8367c_getAsicRegBits(RTL8367C_MIRROR_CTRL_REG, RTL8367C_MIRROR_MONITOR_PORT_MASK, pMonitor); +} +/* Function Name: + * rtl8367c_setAsicPortMirrorRxFunction + * Description: + * Set the mirror function on RX of the mirrored + * Input: + * enabled - 1: enabled, 0: disabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicPortMirrorRxFunction(rtk_uint32 enabled) +{ + return rtl8367c_setAsicRegBit(RTL8367C_MIRROR_CTRL_REG, RTL8367C_MIRROR_RX_OFFSET, enabled); +} +/* Function Name: + * rtl8367c_getAsicPortMirrorRxFunction + * Description: + * Get the mirror function on RX of the mirrored + * Input: + * pEnabled - 1: enabled, 0: disabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicPortMirrorRxFunction(rtk_uint32* pEnabled) +{ + return rtl8367c_getAsicRegBit(RTL8367C_MIRROR_CTRL_REG, RTL8367C_MIRROR_RX_OFFSET, pEnabled); +} +/* Function Name: + * rtl8367c_setAsicPortMirrorTxFunction + * Description: + * Set the mirror function on TX of the mirrored + * Input: + * enabled - 1: enabled, 0: disabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicPortMirrorTxFunction(rtk_uint32 enabled) +{ + return rtl8367c_setAsicRegBit(RTL8367C_MIRROR_CTRL_REG, RTL8367C_MIRROR_TX_OFFSET, enabled); +} +/* Function Name: + * rtl8367c_getAsicPortMirrorTxFunction + * Description: + * Get the mirror function on TX of the mirrored + * Input: + * pEnabled - 1: enabled, 0: disabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicPortMirrorTxFunction(rtk_uint32* pEnabled) +{ + return rtl8367c_getAsicRegBit(RTL8367C_MIRROR_CTRL_REG, RTL8367C_MIRROR_TX_OFFSET, pEnabled); +} +/* Function Name: + * rtl8367c_setAsicPortMirrorIsolation + * Description: + * Set the traffic isolation on monitor port + * Input: + * enabled - 1: enabled, 0: disabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicPortMirrorIsolation(rtk_uint32 enabled) +{ + return rtl8367c_setAsicRegBit(RTL8367C_MIRROR_CTRL_REG, RTL8367C_MIRROR_ISO_OFFSET, enabled); +} +/* Function Name: + * rtl8367c_getAsicPortMirrorIsolation + * Description: + * Get the traffic isolation on monitor port + * Input: + * pEnabled - 1: enabled, 0: disabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicPortMirrorIsolation(rtk_uint32* pEnabled) +{ + return rtl8367c_getAsicRegBit(RTL8367C_MIRROR_CTRL_REG, RTL8367C_MIRROR_ISO_OFFSET, pEnabled); +} + +/* Function Name: + * rtl8367c_setAsicPortMirrorMask + * Description: + * Set mirror source port mask + * Input: + * SourcePortmask - Source Portmask + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK- Port Mask Error + * Note: + * None + */ +ret_t rtl8367c_setAsicPortMirrorMask(rtk_uint32 SourcePortmask) +{ + if( SourcePortmask > RTL8367C_PORTMASK) + return RT_ERR_PORT_MASK; + + return rtl8367c_setAsicRegBits(RTL8367C_REG_MIRROR_SRC_PMSK, RTL8367C_MIRROR_SRC_PMSK_MASK, SourcePortmask); +} + +/* Function Name: + * rtl8367c_getAsicPortMirrorMask + * Description: + * Get mirror source port mask + * Input: + * None + * Output: + * pSourcePortmask - Source Portmask + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK- Port Mask Error + * Note: + * None + */ +ret_t rtl8367c_getAsicPortMirrorMask(rtk_uint32 *pSourcePortmask) +{ + return rtl8367c_getAsicRegBits(RTL8367C_REG_MIRROR_SRC_PMSK, RTL8367C_MIRROR_SRC_PMSK_MASK, pSourcePortmask); +} + +/* Function Name: + * rtl8367c_setAsicPortMirrorVlanRxLeaky + * Description: + * Set the mirror function of VLAN RX leaky + * Input: + * enabled - 1: enabled, 0: disabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicPortMirrorVlanRxLeaky(rtk_uint32 enabled) +{ + return rtl8367c_setAsicRegBit(RTL8367C_REG_MIRROR_CTRL2, RTL8367C_MIRROR_RX_VLAN_LEAKY_OFFSET, enabled); +} +/* Function Name: + * rtl8367c_getAsicPortMirrorVlanRxLeaky + * Description: + * Get the mirror function of VLAN RX leaky + * Input: + * pEnabled - 1: enabled, 0: disabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicPortMirrorVlanRxLeaky(rtk_uint32* pEnabled) +{ + return rtl8367c_getAsicRegBit(RTL8367C_REG_MIRROR_CTRL2, RTL8367C_MIRROR_RX_VLAN_LEAKY_OFFSET, pEnabled); +} + +/* Function Name: + * rtl8367c_setAsicPortMirrorVlanTxLeaky + * Description: + * Set the mirror function of VLAN TX leaky + * Input: + * enabled - 1: enabled, 0: disabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicPortMirrorVlanTxLeaky(rtk_uint32 enabled) +{ + return rtl8367c_setAsicRegBit(RTL8367C_REG_MIRROR_CTRL2, RTL8367C_MIRROR_TX_VLAN_LEAKY_OFFSET, enabled); +} +/* Function Name: + * rtl8367c_getAsicPortMirrorVlanTxLeaky + * Description: + * Get the mirror function of VLAN TX leaky + * Input: + * pEnabled - 1: enabled, 0: disabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicPortMirrorVlanTxLeaky(rtk_uint32* pEnabled) +{ + return rtl8367c_getAsicRegBit(RTL8367C_REG_MIRROR_CTRL2, RTL8367C_MIRROR_TX_VLAN_LEAKY_OFFSET, pEnabled); +} + +/* Function Name: + * rtl8367c_setAsicPortMirrorIsolationRxLeaky + * Description: + * Set the mirror function of Isolation RX leaky + * Input: + * enabled - 1: enabled, 0: disabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicPortMirrorIsolationRxLeaky(rtk_uint32 enabled) +{ + return rtl8367c_setAsicRegBit(RTL8367C_REG_MIRROR_CTRL2, RTL8367C_MIRROR_RX_ISOLATION_LEAKY_OFFSET, enabled); +} +/* Function Name: + * rtl8367c_getAsicPortMirrorIsolationRxLeaky + * Description: + * Get the mirror function of VLAN RX leaky + * Input: + * pEnabled - 1: enabled, 0: disabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicPortMirrorIsolationRxLeaky(rtk_uint32* pEnabled) +{ + return rtl8367c_getAsicRegBit(RTL8367C_REG_MIRROR_CTRL2, RTL8367C_MIRROR_RX_ISOLATION_LEAKY_OFFSET, pEnabled); +} + +/* Function Name: + * rtl8367c_setAsicPortMirrorIsolationTxLeaky + * Description: + * Set the mirror function of Isolation TX leaky + * Input: + * enabled - 1: enabled, 0: disabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicPortMirrorIsolationTxLeaky(rtk_uint32 enabled) +{ + return rtl8367c_setAsicRegBit(RTL8367C_REG_MIRROR_CTRL2, RTL8367C_MIRROR_TX_ISOLATION_LEAKY_OFFSET, enabled); +} +/* Function Name: + * rtl8367c_getAsicPortMirrorIsolationTxLeaky + * Description: + * Get the mirror function of VLAN TX leaky + * Input: + * pEnabled - 1: enabled, 0: disabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicPortMirrorIsolationTxLeaky(rtk_uint32* pEnabled) +{ + return rtl8367c_getAsicRegBit(RTL8367C_REG_MIRROR_CTRL2, RTL8367C_MIRROR_TX_ISOLATION_LEAKY_OFFSET, pEnabled); +} + +/* Function Name: + * rtl8367c_setAsicPortMirrorRealKeep + * Description: + * Set the mirror function of keep format + * Input: + * mode - 1: keep original format, 0: follow VLAN config + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicPortMirrorRealKeep(rtk_uint32 mode) +{ + return rtl8367c_setAsicRegBit(RTL8367C_REG_MIRROR_CTRL2, RTL8367C_MIRROR_REALKEEP_EN_OFFSET, mode); +} +/* Function Name: + * rtl8367c_getAsicPortMirrorRealKeep + * Description: + * Get the mirror function of keep format + * Input: + * pMode - 1: keep original format, 0: follow VLAN config + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicPortMirrorRealKeep(rtk_uint32* pMode) +{ + return rtl8367c_getAsicRegBit(RTL8367C_REG_MIRROR_CTRL2, RTL8367C_MIRROR_REALKEEP_EN_OFFSET, pMode); +} + +/* Function Name: + * rtl8367c_setAsicPortMirrorOverride + * Description: + * Set the mirror function of override + * Input: + * rxMirror - 1: output rx Mirror format, 0: output forward format + * txMirror - 1: output tx Mirror format, 0: output forward format + * aclMirror - 1: output ACL Mirror format, 0: output forward format + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicPortMirrorOverride(rtk_uint32 rxMirror, rtk_uint32 txMirror, rtk_uint32 aclMirror) +{ + ret_t retVal; + + if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_MIRROR_CTRL3, RTL8367C_MIRROR_RX_OVERRIDE_EN_OFFSET, rxMirror)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_MIRROR_CTRL3, RTL8367C_MIRROR_TX_OVERRIDE_EN_OFFSET, txMirror)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_MIRROR_CTRL3, RTL8367C_MIRROR_ACL_OVERRIDE_EN_OFFSET, aclMirror)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_getAsicPortMirrorOverride + * Description: + * Get the mirror function of override + * Input: + * None + * Output: + * pRxMirror - 1: output rx Mirror format, 0: output forward format + * pTxMirror - 1: output tx Mirror format, 0: output forward format + * pAclMirror - 1: output ACL Mirror format, 0: output forward format + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicPortMirrorOverride(rtk_uint32 *pRxMirror, rtk_uint32 *pTxMirror, rtk_uint32 *pAclMirror) +{ + ret_t retVal; + + if((retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_MIRROR_CTRL3, RTL8367C_MIRROR_RX_OVERRIDE_EN_OFFSET, pRxMirror)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_MIRROR_CTRL3, RTL8367C_MIRROR_TX_OVERRIDE_EN_OFFSET, pTxMirror)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_MIRROR_CTRL3, RTL8367C_MIRROR_ACL_OVERRIDE_EN_OFFSET, pAclMirror)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_mirror.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_mirror.h new file mode 100644 index 00000000..8365407c --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_mirror.h @@ -0,0 +1,32 @@ +#ifndef _RTL8367C_ASICDRV_MIRROR_H_ +#define _RTL8367C_ASICDRV_MIRROR_H_ + +#include + +extern ret_t rtl8367c_setAsicPortMirror(rtk_uint32 source, rtk_uint32 monitor); +extern ret_t rtl8367c_getAsicPortMirror(rtk_uint32 *pSource, rtk_uint32 *pMonitor); +extern ret_t rtl8367c_setAsicPortMirrorRxFunction(rtk_uint32 enabled); +extern ret_t rtl8367c_getAsicPortMirrorRxFunction(rtk_uint32* pEnabled); +extern ret_t rtl8367c_setAsicPortMirrorTxFunction(rtk_uint32 enabled); +extern ret_t rtl8367c_getAsicPortMirrorTxFunction(rtk_uint32* pEnabled); +extern ret_t rtl8367c_setAsicPortMirrorIsolation(rtk_uint32 enabled); +extern ret_t rtl8367c_getAsicPortMirrorIsolation(rtk_uint32* pEnabled); +extern ret_t rtl8367c_setAsicPortMirrorPriority(rtk_uint32 priority); +extern ret_t rtl8367c_getAsicPortMirrorPriority(rtk_uint32* pPriority); +extern ret_t rtl8367c_setAsicPortMirrorMask(rtk_uint32 SourcePortmask); +extern ret_t rtl8367c_getAsicPortMirrorMask(rtk_uint32 *pSourcePortmask); +extern ret_t rtl8367c_setAsicPortMirrorVlanRxLeaky(rtk_uint32 enabled); +extern ret_t rtl8367c_getAsicPortMirrorVlanRxLeaky(rtk_uint32* pEnabled); +extern ret_t rtl8367c_setAsicPortMirrorVlanTxLeaky(rtk_uint32 enabled); +extern ret_t rtl8367c_getAsicPortMirrorVlanTxLeaky(rtk_uint32* pEnabled); +extern ret_t rtl8367c_setAsicPortMirrorIsolationRxLeaky(rtk_uint32 enabled); +extern ret_t rtl8367c_getAsicPortMirrorIsolationRxLeaky(rtk_uint32* pEnabled); +extern ret_t rtl8367c_setAsicPortMirrorIsolationTxLeaky(rtk_uint32 enabled); +extern ret_t rtl8367c_getAsicPortMirrorIsolationTxLeaky(rtk_uint32* pEnabled); +extern ret_t rtl8367c_setAsicPortMirrorRealKeep(rtk_uint32 mode); +extern ret_t rtl8367c_getAsicPortMirrorRealKeep(rtk_uint32* pMode); +extern ret_t rtl8367c_setAsicPortMirrorOverride(rtk_uint32 rxMirror, rtk_uint32 txMirror, rtk_uint32 aclMirror); +extern ret_t rtl8367c_getAsicPortMirrorOverride(rtk_uint32 *pRxMirror, rtk_uint32 *pTxMirror, rtk_uint32 *pAclMirror); + +#endif /*#ifndef _RTL8367C_ASICDRV_MIRROR_H_*/ + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_misc.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_misc.c new file mode 100644 index 00000000..26136ade --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_misc.c @@ -0,0 +1,262 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTL8367C switch high-level API for RTL8367C + * Feature : Miscellaneous functions + * + */ + +#include +/* Function Name: + * rtl8367c_setAsicMacAddress + * Description: + * Set switch MAC address + * Input: + * mac - switch mac + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicMacAddress(ether_addr_t mac) +{ + ret_t retVal; + rtk_uint32 regData; + rtk_uint8 *accessPtr; + rtk_uint32 i; + + accessPtr = (rtk_uint8*)&mac; + + for(i = 0; i <=2; i++) + { + regData = (*(accessPtr + (i*2)) << 8) | *(accessPtr + (i*2) + 1); + retVal = rtl8367c_setAsicReg(RTL8367C_REG_SWITCH_MAC2 - i, regData); + if(retVal != RT_ERR_OK) + return retVal; + } + + return retVal; +} +/* Function Name: + * rtl8367c_getAsicMacAddress + * Description: + * Get switch MAC address + * Input: + * pMac - switch mac + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicMacAddress(ether_addr_t *pMac) +{ + ret_t retVal; + rtk_uint32 regData; + rtk_uint8 *accessPtr; + rtk_uint32 i; + + + accessPtr = (rtk_uint8*)pMac; + + for(i = 0; i <= 2; i++) + { + retVal = rtl8367c_getAsicReg(RTL8367C_REG_SWITCH_MAC2 - i, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + *accessPtr = (regData & 0xFF00) >> 8; + accessPtr ++; + *accessPtr = regData & 0xFF; + accessPtr ++; + } + + return retVal; +} +/* Function Name: + * rtl8367c_getAsicDebugInfo + * Description: + * Get per-port packet forward debugging information + * Input: + * port - Physical port number (0~7) + * pDebugifo - per-port packet trap/drop/forward reason + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_getAsicDebugInfo(rtk_uint32 port, rtk_uint32 *pDebugifo) +{ + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + return rtl8367c_getAsicRegBits(RTL8367C_DEBUG_INFO_REG(port), RTL8367C_DEBUG_INFO_MASK(port), pDebugifo); +} +/* Function Name: + * rtl8367c_setAsicPortJamMode + * Description: + * Set half duplex flow control setting + * Input: + * mode - 0: Back-Pressure 1: DEFER + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicPortJamMode(rtk_uint32 mode) +{ + return rtl8367c_setAsicRegBit(RTL8367C_REG_CFG_BACKPRESSURE, RTL8367C_LONGTXE_OFFSET,mode); +} +/* Function Name: + * rtl8367c_getAsicPortJamMode + * Description: + * Get half duplex flow control setting + * Input: + * pMode - 0: Back-Pressure 1: DEFER + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicPortJamMode(rtk_uint32* pMode) +{ + return rtl8367c_getAsicRegBit(RTL8367C_REG_CFG_BACKPRESSURE, RTL8367C_LONGTXE_OFFSET, pMode); +} + +/* Function Name: + * rtl8367c_setAsicMaxLengthCfg + * Description: + * Set Max packet length configuration + * Input: + * cfgId - Configuration ID + * maxLength - Max Length + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicMaxLengthCfg(rtk_uint32 cfgId, rtk_uint32 maxLength) +{ + return rtl8367c_setAsicRegBits(RTL8367C_REG_MAX_LEN_RX_TX_CFG0 + cfgId, RTL8367C_MAX_LEN_RX_TX_CFG0_MASK, maxLength); +} + +/* Function Name: + * rtl8367c_getAsicMaxLengthCfg + * Description: + * Get Max packet length configuration + * Input: + * cfgId - Configuration ID + * maxLength - Max Length + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicMaxLengthCfg(rtk_uint32 cfgId, rtk_uint32 *pMaxLength) +{ + return rtl8367c_getAsicRegBits(RTL8367C_REG_MAX_LEN_RX_TX_CFG0 + cfgId, RTL8367C_MAX_LEN_RX_TX_CFG0_MASK, pMaxLength); +} + +/* Function Name: + * rtl8367c_setAsicMaxLength + * Description: + * Set Max packet length + * Input: + * port - port ID + * type - 0: 10M/100M speed, 1: giga speed + * cfgId - Configuration ID + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicMaxLength(rtk_uint32 port, rtk_uint32 type, rtk_uint32 cfgId) +{ + ret_t retVal; + + if(port < 8) + { + retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_MAX_LENGTH_CFG, (type * 8) + port, cfgId); + if(retVal != RT_ERR_OK) + return retVal; + } + else + { + retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_MAX_LENGTH_CFG_EXT, (type * 3) + port - 8, cfgId); + if(retVal != RT_ERR_OK) + return retVal; + } + + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_getAsicMaxLength + * Description: + * Get Max packet length + * Input: + * port - port ID + * type - 0: 10M/100M speed, 1: giga speed + * cfgId - Configuration ID + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicMaxLength(rtk_uint32 port, rtk_uint32 type, rtk_uint32 *pCfgId) +{ + ret_t retVal; + + if(port < 8) + { + retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_MAX_LENGTH_CFG, (type * 8) + port, pCfgId); + if(retVal != RT_ERR_OK) + return retVal; + } + else + { + retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_MAX_LENGTH_CFG_EXT, (type * 3) + port - 8, pCfgId); + if(retVal != RT_ERR_OK) + return retVal; + } + return RT_ERR_OK; +} + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_misc.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_misc.h new file mode 100644 index 00000000..bba37483 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_misc.h @@ -0,0 +1,17 @@ +#ifndef _RTL8367C_ASICDRV_MISC_H_ +#define _RTL8367C_ASICDRV_MISC_H_ + +#include + +extern ret_t rtl8367c_setAsicMacAddress(ether_addr_t mac); +extern ret_t rtl8367c_getAsicMacAddress(ether_addr_t *pMac); +extern ret_t rtl8367c_getAsicDebugInfo(rtk_uint32 port, rtk_uint32 *pDebugifo); +extern ret_t rtl8367c_setAsicPortJamMode(rtk_uint32 mode); +extern ret_t rtl8367c_getAsicPortJamMode(rtk_uint32* pMode); +extern ret_t rtl8367c_setAsicMaxLengthCfg(rtk_uint32 cfgId, rtk_uint32 maxLength); +extern ret_t rtl8367c_getAsicMaxLengthCfg(rtk_uint32 cfgId, rtk_uint32 *pMaxLength); +extern ret_t rtl8367c_setAsicMaxLength(rtk_uint32 port, rtk_uint32 type, rtk_uint32 cfgId); +extern ret_t rtl8367c_getAsicMaxLength(rtk_uint32 port, rtk_uint32 type, rtk_uint32 *pCfgId); + +#endif /*_RTL8367C_ASICDRV_MISC_H_*/ + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_oam.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_oam.c new file mode 100644 index 00000000..f6a6c1cc --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_oam.c @@ -0,0 +1,196 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision: 42321 $ + * $Date: 2013-08-26 13:51:29 +0800 (週一, 26 八月 2013) $ + * + * Purpose : RTL8367C switch high-level API for RTL8367C + * Feature : OAM related functions + * + */ + +#include +/* Function Name: + * rtl8367c_setAsicOamParser + * Description: + * Set OAM parser state + * Input: + * port - Physical port number (0~7) + * parser - Per-Port OAM parser state + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * RT_ERR_NOT_ALLOWED - Invalid paser state + * Note: + * None + */ +ret_t rtl8367c_setAsicOamParser(rtk_uint32 port, rtk_uint32 parser) +{ + if(port >= RTL8367C_PORTNO) + return RT_ERR_PORT_ID; + + if(parser > OAM_PARFWDCPU) + return RT_ERR_NOT_ALLOWED; + + return rtl8367c_setAsicRegBits(RTL8367C_REG_OAM_PARSER_CTRL0 + port/8, RTL8367C_OAM_PARSER_MASK(port % 8), parser); +} +/* Function Name: + * rtl8367c_getAsicOamParser + * Description: + * Get OAM parser state + * Input: + * port - Physical port number (0~7) + * pParser - Per-Port OAM parser state + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_getAsicOamParser(rtk_uint32 port, rtk_uint32* pParser) +{ + if(port >= RTL8367C_PORTNO) + return RT_ERR_PORT_ID; + + return rtl8367c_getAsicRegBits(RTL8367C_REG_OAM_PARSER_CTRL0 + port/8, RTL8367C_OAM_PARSER_MASK(port%8), pParser); +} +/* Function Name: + * rtl8367c_setAsicOamMultiplexer + * Description: + * Set OAM multiplexer state + * Input: + * port - Physical port number (0~7) + * multiplexer - Per-Port OAM multiplexer state + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * RT_ERR_NOT_ALLOWED - Invalid multiplexer state + * Note: + * None + */ +ret_t rtl8367c_setAsicOamMultiplexer(rtk_uint32 port, rtk_uint32 multiplexer) +{ + if(port >= RTL8367C_PORTNO) + return RT_ERR_PORT_ID; + + if(multiplexer > OAM_MULCPU) + return RT_ERR_NOT_ALLOWED; + + return rtl8367c_setAsicRegBits(RTL8367C_REG_OAM_MULTIPLEXER_CTRL0 + port/8, RTL8367C_OAM_MULTIPLEXER_MASK(port%8), multiplexer); +} +/* Function Name: + * rtl8367c_getAsicOamMultiplexer + * Description: + * Get OAM multiplexer state + * Input: + * port - Physical port number (0~7) + * pMultiplexer - Per-Port OAM multiplexer state + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_getAsicOamMultiplexer(rtk_uint32 port, rtk_uint32* pMultiplexer) +{ + if(port >= RTL8367C_PORTNO) + return RT_ERR_PORT_ID; + + return rtl8367c_getAsicRegBits(RTL8367C_REG_OAM_MULTIPLEXER_CTRL0 + port/8, RTL8367C_OAM_MULTIPLEXER_MASK(port%8), pMultiplexer); +} +/* Function Name: + * rtl8367c_setAsicOamCpuPri + * Description: + * Set trap priority for OAM packet + * Input: + * priority - priority (0~7) + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_INT_PRIORITY - Invalid priority + * Note: + * None + */ +ret_t rtl8367c_setAsicOamCpuPri(rtk_uint32 priority) +{ + if(priority > RTL8367C_PRIMAX) + return RT_ERR_QOS_INT_PRIORITY; + + return rtl8367c_setAsicRegBits(RTL8367C_REG_QOS_TRAP_PRIORITY0, RTL8367C_OAM_PRIOIRTY_MASK, priority); +} +/* Function Name: + * rtl8367c_getAsicOamCpuPri + * Description: + * Get trap priority for OAM packet + * Input: + * pPriority - priority (0~7) + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicOamCpuPri(rtk_uint32 *pPriority) +{ + return rtl8367c_getAsicRegBits(RTL8367C_REG_QOS_TRAP_PRIORITY0, RTL8367C_OAM_PRIOIRTY_MASK, pPriority); +} +/* Function Name: + * rtl8367c_setAsicOamEnable + * Description: + * Set OAM function state + * Input: + * enabled - OAM function usage 1:enable, 0:disabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicOamEnable(rtk_uint32 enabled) +{ + return rtl8367c_setAsicRegBit(RTL8367C_REG_OAM_CTRL, RTL8367C_OAM_CTRL_OFFSET, enabled); +} +/* Function Name: + * rtl8367c_getAsicOamEnable + * Description: + * Get OAM function state + * Input: + * pEnabled - OAM function usage 1:enable, 0:disabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicOamEnable(rtk_uint32 *pEnabled) +{ + return rtl8367c_getAsicRegBit(RTL8367C_REG_OAM_CTRL, RTL8367C_OAM_CTRL_OFFSET, pEnabled); +} diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_oam.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_oam.h new file mode 100644 index 00000000..248ebadc --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_oam.h @@ -0,0 +1,30 @@ +#ifndef _RTL8367C_ASICDRV_OAM_H_ +#define _RTL8367C_ASICDRV_OAM_H_ + +#include + +enum OAMPARACT +{ + OAM_PARFWD = 0, + OAM_PARLB, + OAM_PARDISCARD, + OAM_PARFWDCPU +}; + +enum OAMMULACT +{ + OAM_MULFWD = 0, + OAM_MULDISCARD, + OAM_MULCPU +}; + +extern ret_t rtl8367c_setAsicOamParser(rtk_uint32 port, rtk_uint32 parser); +extern ret_t rtl8367c_getAsicOamParser(rtk_uint32 port, rtk_uint32* pParser); +extern ret_t rtl8367c_setAsicOamMultiplexer(rtk_uint32 port, rtk_uint32 multiplexer); +extern ret_t rtl8367c_getAsicOamMultiplexer(rtk_uint32 port, rtk_uint32* pMultiplexer); +extern ret_t rtl8367c_setAsicOamCpuPri(rtk_uint32 priority); +extern ret_t rtl8367c_getAsicOamCpuPri(rtk_uint32 *pPriority); +extern ret_t rtl8367c_setAsicOamEnable(rtk_uint32 enabled); +extern ret_t rtl8367c_getAsicOamEnable(rtk_uint32 *pEnabled); +#endif /*_RTL8367C_ASICDRV_OAM_H_*/ + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_phy.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_phy.c new file mode 100644 index 00000000..7fbd945f --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_phy.c @@ -0,0 +1,429 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTL8367C switch high-level API for RTL8367C + * Feature : PHY related functions + * + */ +#include + +#if 1 +/* Function Name: + * rtl8367c_setAsicPHYOCPReg + * Description: + * Set PHY OCP registers + * Input: + * phyNo - Physical port number (0~7) + * ocpAddr - OCP address + * ocpData - Writing data + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PHY_REG_ID - invalid PHY address + * RT_ERR_PHY_ID - invalid PHY no + * RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy + * Note: + * None + */ +ret_t rtl8367c_setAsicPHYOCPReg(rtk_uint32 phyNo, rtk_uint32 ocpAddr, rtk_uint32 ocpData ) +{ + ret_t retVal; + rtk_uint32 regAddr; + rtk_uint32 ocpAddrPrefix, ocpAddr9_6, ocpAddr5_1; + + /* OCP prefix */ + ocpAddrPrefix = ((ocpAddr & 0xFC00) >> 10); + if((retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_GPHY_OCP_MSB_0, RTL8367C_CFG_CPU_OCPADR_MSB_MASK, ocpAddrPrefix)) != RT_ERR_OK) + return retVal; + + /*prepare access address*/ + ocpAddr9_6 = ((ocpAddr >> 6) & 0x000F); + ocpAddr5_1 = ((ocpAddr >> 1) & 0x001F); + regAddr = RTL8367C_PHY_BASE | (ocpAddr9_6 << 8) | (phyNo << RTL8367C_PHY_OFFSET) | ocpAddr5_1; + if((retVal = rtl8367c_setAsicReg(regAddr, ocpData)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_getAsicPHYOCPReg + * Description: + * Get PHY OCP registers + * Input: + * phyNo - Physical port number (0~7) + * ocpAddr - PHY address + * pRegData - read data + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PHY_REG_ID - invalid PHY address + * RT_ERR_PHY_ID - invalid PHY no + * RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy + * Note: + * None + */ +ret_t rtl8367c_getAsicPHYOCPReg(rtk_uint32 phyNo, rtk_uint32 ocpAddr, rtk_uint32 *pRegData ) +{ + ret_t retVal; + rtk_uint32 regAddr; + rtk_uint32 ocpAddrPrefix, ocpAddr9_6, ocpAddr5_1; + /* OCP prefix */ + ocpAddrPrefix = ((ocpAddr & 0xFC00) >> 10); + if((retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_GPHY_OCP_MSB_0, RTL8367C_CFG_CPU_OCPADR_MSB_MASK, ocpAddrPrefix)) != RT_ERR_OK) + return retVal; + + /*prepare access address*/ + ocpAddr9_6 = ((ocpAddr >> 6) & 0x000F); + ocpAddr5_1 = ((ocpAddr >> 1) & 0x001F); + regAddr = RTL8367C_PHY_BASE | (ocpAddr9_6 << 8) | (phyNo << RTL8367C_PHY_OFFSET) | ocpAddr5_1; + if((retVal = rtl8367c_getAsicReg(regAddr, pRegData)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +#else + +/* Function Name: + * rtl8367c_setAsicPHYOCPReg + * Description: + * Set PHY OCP registers + * Input: + * phyNo - Physical port number (0~7) + * ocpAddr - OCP address + * ocpData - Writing data + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PHY_REG_ID - invalid PHY address + * RT_ERR_PHY_ID - invalid PHY no + * RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy + * Note: + * None + */ +ret_t rtl8367c_setAsicPHYOCPReg(rtk_uint32 phyNo, rtk_uint32 ocpAddr, rtk_uint32 ocpData ) +{ + ret_t retVal; + rtk_uint32 regData; + rtk_uint32 busyFlag, checkCounter; + rtk_uint32 ocpAddrPrefix, ocpAddr9_6, ocpAddr5_1; + + /*Check internal phy access busy or not*/ + /*retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_INDRECT_ACCESS_STATUS, RTL8367C_INDRECT_ACCESS_STATUS_OFFSET,&busyFlag);*/ + retVal = rtl8367c_getAsicReg(RTL8367C_REG_INDRECT_ACCESS_STATUS,&busyFlag); + if(retVal != RT_ERR_OK) + return retVal; + + if(busyFlag) + return RT_ERR_BUSYWAIT_TIMEOUT; + + /* OCP prefix */ + ocpAddrPrefix = ((ocpAddr & 0xFC00) >> 10); + if((retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_GPHY_OCP_MSB_0, RTL8367C_CFG_CPU_OCPADR_MSB_MASK, ocpAddrPrefix)) != RT_ERR_OK) + return retVal; + + /*prepare access data*/ + retVal = rtl8367c_setAsicReg(RTL8367C_REG_INDRECT_ACCESS_WRITE_DATA, ocpData); + if(retVal != RT_ERR_OK) + return retVal; + + /*prepare access address*/ + ocpAddr9_6 = ((ocpAddr >> 6) & 0x000F); + ocpAddr5_1 = ((ocpAddr >> 1) & 0x001F); + regData = RTL8367C_PHY_BASE | (ocpAddr9_6 << 8) | (phyNo << RTL8367C_PHY_OFFSET) | ocpAddr5_1; + retVal = rtl8367c_setAsicReg(RTL8367C_REG_INDRECT_ACCESS_ADDRESS, regData); + if(retVal != RT_ERR_OK) + return retVal; + + /*Set WRITE Command*/ + retVal = rtl8367c_setAsicReg(RTL8367C_REG_INDRECT_ACCESS_CTRL, RTL8367C_CMD_MASK | RTL8367C_RW_MASK); + + checkCounter = 100; + while(checkCounter) + { + retVal = rtl8367c_getAsicReg(RTL8367C_REG_INDRECT_ACCESS_STATUS,&busyFlag); + if((retVal != RT_ERR_OK) || busyFlag) + { + checkCounter --; + if(0 == checkCounter) + return RT_ERR_BUSYWAIT_TIMEOUT; + } + else + { + checkCounter = 0; + } + } + + return retVal; +} +/* Function Name: + * rtl8367c_getAsicPHYOCPReg + * Description: + * Get PHY OCP registers + * Input: + * phyNo - Physical port number (0~7) + * ocpAddr - PHY address + * pRegData - read data + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PHY_REG_ID - invalid PHY address + * RT_ERR_PHY_ID - invalid PHY no + * RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy + * Note: + * None + */ +ret_t rtl8367c_getAsicPHYOCPReg(rtk_uint32 phyNo, rtk_uint32 ocpAddr, rtk_uint32 *pRegData ) +{ + ret_t retVal; + rtk_uint32 regData; + rtk_uint32 busyFlag,checkCounter; + rtk_uint32 ocpAddrPrefix, ocpAddr9_6, ocpAddr5_1; + /*Check internal phy access busy or not*/ + /*retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_INDRECT_ACCESS_STATUS, RTL8367C_INDRECT_ACCESS_STATUS_OFFSET,&busyFlag);*/ + retVal = rtl8367c_getAsicReg(RTL8367C_REG_INDRECT_ACCESS_STATUS,&busyFlag); + if(retVal != RT_ERR_OK) + return retVal; + + if(busyFlag) + return RT_ERR_BUSYWAIT_TIMEOUT; + + /* OCP prefix */ + ocpAddrPrefix = ((ocpAddr & 0xFC00) >> 10); + if((retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_GPHY_OCP_MSB_0, RTL8367C_CFG_CPU_OCPADR_MSB_MASK, ocpAddrPrefix)) != RT_ERR_OK) + return retVal; + + /*prepare access address*/ + ocpAddr9_6 = ((ocpAddr >> 6) & 0x000F); + ocpAddr5_1 = ((ocpAddr >> 1) & 0x001F); + regData = RTL8367C_PHY_BASE | (ocpAddr9_6 << 8) | (phyNo << RTL8367C_PHY_OFFSET) | ocpAddr5_1; + retVal = rtl8367c_setAsicReg(RTL8367C_REG_INDRECT_ACCESS_ADDRESS, regData); + if(retVal != RT_ERR_OK) + return retVal; + + /*Set READ Command*/ + retVal = rtl8367c_setAsicReg(RTL8367C_REG_INDRECT_ACCESS_CTRL, RTL8367C_CMD_MASK ); + if(retVal != RT_ERR_OK) + return retVal; + + checkCounter = 100; + while(checkCounter) + { + retVal = rtl8367c_getAsicReg(RTL8367C_REG_INDRECT_ACCESS_STATUS,&busyFlag); + if((retVal != RT_ERR_OK) || busyFlag) + { + checkCounter --; + if(0 == checkCounter) + return RT_ERR_FAILED; + } + else + { + checkCounter = 0; + } + } + + /*get PHY register*/ + retVal = rtl8367c_getAsicReg(RTL8367C_REG_INDRECT_ACCESS_READ_DATA, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + *pRegData = regData; + + return RT_ERR_OK; +} + +#endif + +/* Function Name: + * rtl8367c_setAsicPHYReg + * Description: + * Set PHY registers + * Input: + * phyNo - Physical port number (0~7) + * phyAddr - PHY address (0~31) + * phyData - Writing data + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PHY_REG_ID - invalid PHY address + * RT_ERR_PHY_ID - invalid PHY no + * RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy + * Note: + * None + */ +ret_t rtl8367c_setAsicPHYReg(rtk_uint32 phyNo, rtk_uint32 phyAddr, rtk_uint32 phyData ) +{ + rtk_uint32 ocp_addr; + + if(phyAddr > RTL8367C_PHY_REGNOMAX) + return RT_ERR_PHY_REG_ID; + + ocp_addr = 0xa400 + phyAddr*2; + + return rtl8367c_setAsicPHYOCPReg(phyNo, ocp_addr, phyData); +} +/* Function Name: + * rtl8367c_getAsicPHYReg + * Description: + * Get PHY registers + * Input: + * phyNo - Physical port number (0~7) + * phyAddr - PHY address (0~31) + * pRegData - Writing data + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PHY_REG_ID - invalid PHY address + * RT_ERR_PHY_ID - invalid PHY no + * RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy + * Note: + * None + */ +ret_t rtl8367c_getAsicPHYReg(rtk_uint32 phyNo, rtk_uint32 phyAddr, rtk_uint32 *pRegData ) +{ + rtk_uint32 ocp_addr; + + if(phyAddr > RTL8367C_PHY_REGNOMAX) + return RT_ERR_PHY_REG_ID; + + ocp_addr = 0xa400 + phyAddr*2; + + return rtl8367c_getAsicPHYOCPReg(phyNo, ocp_addr, pRegData); +} + + +/* Function Name: + * rtl8367c_setAsicSdsReg + * Description: + * Set Serdes registers + * Input: + * sdsId - sdsid (0~1) + * sdsReg - reg address (0~31) + * sdsPage - Writing data + * Output: + * None + * Return: + * RT_ERR_OK - Success + + * Note: + * None + */ + +ret_t rtl8367c_setAsicSdsReg(rtk_uint32 sdsId, rtk_uint32 sdsReg, rtk_uint32 sdsPage, rtk_uint32 value) +{ + rtk_uint32 retVal; + + if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_DATA, value)) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_ADR, (sdsPage<<5) | sdsReg)) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_CMD, 0x00C0|sdsId)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; + +} + +/* Function Name: + * rtl8367c_getAiscSdsReg + * Description: + * Get Serdes registers + * Input: + * sdsId - sdsid (0~1) + * sdsReg - reg address (0~31) + * sdsPage - Writing data + * Output: + * None + * Return: + * RT_ERR_OK - Success + + * Note: + * None + */ +ret_t rtl8367c_getAsicSdsReg(rtk_uint32 sdsId, rtk_uint32 sdsReg, rtk_uint32 sdsPage, rtk_uint32 *value) +{ + rtk_uint32 retVal, busy; + + if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_ADR, (sdsPage<<5) | sdsReg)) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_CMD, 0x0080|sdsId)) != RT_ERR_OK) + return retVal; + + while(1) + { + if ((retVal = rtl8367c_getAsicReg(RTL8367C_REG_SDS_INDACS_CMD, &busy))!=RT_ERR_OK) + return retVal; + + if ((busy & 0x100) == 0) + break; + } + + if ((retVal = rtl8367c_getAsicReg(RTL8367C_REG_SDS_INDACS_DATA, value))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * rtl8367c_setAsicPHYSram + * Description: + * Set PHY registers + * Input: + * phyNo - Physical port number (0~7) + * sramAddr - SRAM address + * sramData - Writing data + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PHY_REG_ID - invalid PHY address + * RT_ERR_PHY_ID - invalid PHY no + * RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy + * Note: + * None + */ + +ret_t rtl8367c_setAsicPHYSram(rtk_uint32 phyNo, rtk_uint32 sramAddr, rtk_uint32 sramData ) +{ + rtk_uint32 retVal; + + if ((retVal = rtl8367c_setAsicPHYOCPReg(phyNo, 0xa436, sramAddr)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicPHYOCPReg(phyNo, 0xa438, sramData)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_phy.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_phy.h new file mode 100644 index 00000000..7031edf5 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_phy.h @@ -0,0 +1,28 @@ +#ifndef _RTL8367C_ASICDRV_PHY_H_ +#define _RTL8367C_ASICDRV_PHY_H_ + +#include + +#define RTL8367C_PHY_REGNOMAX 0x1F +#define RTL8367C_PHY_EXTERNALMAX 0x7 + +#define RTL8367C_PHY_BASE 0x2000 +#define RTL8367C_PHY_EXT_BASE 0xA000 + +#define RTL8367C_PHY_OFFSET 5 +#define RTL8367C_PHY_EXT_OFFSET 9 + +#define RTL8367C_PHY_PAGE_ADDRESS 31 + + +extern ret_t rtl8367c_setAsicPHYReg(rtk_uint32 phyNo, rtk_uint32 phyAddr, rtk_uint32 regData ); +extern ret_t rtl8367c_getAsicPHYReg(rtk_uint32 phyNo, rtk_uint32 phyAddr, rtk_uint32* pRegData ); +extern ret_t rtl8367c_setAsicPHYOCPReg(rtk_uint32 phyNo, rtk_uint32 ocpAddr, rtk_uint32 ocpData ); +extern ret_t rtl8367c_getAsicPHYOCPReg(rtk_uint32 phyNo, rtk_uint32 ocpAddr, rtk_uint32 *pRegData ); +extern ret_t rtl8367c_setAsicSdsReg(rtk_uint32 sdsId, rtk_uint32 sdsReg, rtk_uint32 sdsPage, rtk_uint32 value); +extern ret_t rtl8367c_getAsicSdsReg(rtk_uint32 sdsId, rtk_uint32 sdsReg, rtk_uint32 sdsPage, rtk_uint32 *value); +extern ret_t rtl8367c_setAsicPHYSram(rtk_uint32 phyNo, rtk_uint32 sramAddr, rtk_uint32 sramData ); + + +#endif /*#ifndef _RTL8367C_ASICDRV_PHY_H_*/ + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_port.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_port.c new file mode 100644 index 00000000..426dbbfb --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_port.c @@ -0,0 +1,6052 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTL8367C switch high-level API for RTL8367C + * Feature : Port security related functions + * + */ + +#include + +#include +#include + + +#define FIBER2_AUTO_INIT_SIZE 1947 +rtk_uint8 Fiber2_Auto[FIBER2_AUTO_INIT_SIZE] = { +0x02,0x05,0x9D,0xE4,0xF5,0xA8, +0xD2,0xAF,0x22,0x00,0x00,0x02,0x06,0xD1, +0xC5,0xF0,0xF8,0xA3,0xE0,0x28,0xF0,0xC5, +0xF0,0xF8,0xE5,0x82,0x15,0x82,0x70,0x02, +0x15,0x83,0xE0,0x38,0xF0,0x22,0x75,0xF0, +0x08,0x75,0x82,0x00,0xEF,0x2F,0xFF,0xEE, +0x33,0xFE,0xCD,0x33,0xCD,0xCC,0x33,0xCC, +0xC5,0x82,0x33,0xC5,0x82,0x9B,0xED,0x9A, +0xEC,0x99,0xE5,0x82,0x98,0x40,0x0C,0xF5, +0x82,0xEE,0x9B,0xFE,0xED,0x9A,0xFD,0xEC, +0x99,0xFC,0x0F,0xD5,0xF0,0xD6,0xE4,0xCE, +0xFB,0xE4,0xCD,0xFA,0xE4,0xCC,0xF9,0xA8, +0x82,0x22,0xB8,0x00,0xC1,0xB9,0x00,0x59, +0xBA,0x00,0x2D,0xEC,0x8B,0xF0,0x84,0xCF, +0xCE,0xCD,0xFC,0xE5,0xF0,0xCB,0xF9,0x78, +0x18,0xEF,0x2F,0xFF,0xEE,0x33,0xFE,0xED, +0x33,0xFD,0xEC,0x33,0xFC,0xEB,0x33,0xFB, +0x10,0xD7,0x03,0x99,0x40,0x04,0xEB,0x99, +0xFB,0x0F,0xD8,0xE5,0xE4,0xF9,0xFA,0x22, +0x78,0x18,0xEF,0x2F,0xFF,0xEE,0x33,0xFE, +0xED,0x33,0xFD,0xEC,0x33,0xFC,0xC9,0x33, +0xC9,0x10,0xD7,0x05,0x9B,0xE9,0x9A,0x40, +0x07,0xEC,0x9B,0xFC,0xE9,0x9A,0xF9,0x0F, +0xD8,0xE0,0xE4,0xC9,0xFA,0xE4,0xCC,0xFB, +0x22,0x75,0xF0,0x10,0xEF,0x2F,0xFF,0xEE, +0x33,0xFE,0xED,0x33,0xFD,0xCC,0x33,0xCC, +0xC8,0x33,0xC8,0x10,0xD7,0x07,0x9B,0xEC, +0x9A,0xE8,0x99,0x40,0x0A,0xED,0x9B,0xFD, +0xEC,0x9A,0xFC,0xE8,0x99,0xF8,0x0F,0xD5, +0xF0,0xDA,0xE4,0xCD,0xFB,0xE4,0xCC,0xFA, +0xE4,0xC8,0xF9,0x22,0xEB,0x9F,0xF5,0xF0, +0xEA,0x9E,0x42,0xF0,0xE9,0x9D,0x42,0xF0, +0xE8,0x9C,0x45,0xF0,0x22,0xE0,0xFC,0xA3, +0xE0,0xFD,0xA3,0xE0,0xFE,0xA3,0xE0,0xFF, +0x22,0xE0,0xF8,0xA3,0xE0,0xF9,0xA3,0xE0, +0xFA,0xA3,0xE0,0xFB,0x22,0xEC,0xF0,0xA3, +0xED,0xF0,0xA3,0xEE,0xF0,0xA3,0xEF,0xF0, +0x22,0x7D,0xD7,0x7C,0x04,0x7F,0x02,0x7E, +0x66,0x12,0x07,0x50,0x7D,0x80,0x7C,0x04, +0x7F,0x01,0x7E,0x66,0x12,0x07,0x50,0x7D, +0xC0,0x7C,0x00,0x7F,0x00,0x7E,0x66,0x12, +0x07,0x50,0x7D,0x94,0x7C,0xF9,0x7F,0x02, +0x7E,0x66,0x12,0x07,0x50,0x7D,0x81,0x7C, +0x04,0x7F,0x01,0x7E,0x66,0x12,0x07,0x50, +0x7D,0xC0,0x7C,0x00,0x7F,0x00,0x7E,0x66, +0x12,0x07,0x50,0x7D,0xA2,0x7C,0x31,0x7F, +0x02,0x7E,0x66,0x12,0x07,0x50,0x7D,0x82, +0x7C,0x04,0x7F,0x01,0x7E,0x66,0x12,0x07, +0x50,0x7D,0xC0,0x7C,0x00,0x7F,0x00,0x7E, +0x66,0x12,0x07,0x50,0x7D,0x60,0x7C,0x69, +0x7F,0x02,0x7E,0x66,0x12,0x07,0x50,0x7D, +0x83,0x7C,0x04,0x7F,0x01,0x7E,0x66,0x12, +0x07,0x50,0x7D,0xC0,0x7C,0x00,0x7F,0x00, +0x7E,0x66,0x12,0x07,0x50,0x7D,0x28,0x7C, +0x97,0x7F,0x02,0x7E,0x66,0x12,0x07,0x50, +0x7D,0x84,0x7C,0x04,0x7F,0x01,0x7E,0x66, +0x12,0x07,0x50,0x7D,0xC0,0x7C,0x00,0x7F, +0x00,0x7E,0x66,0x12,0x07,0x50,0x7D,0x85, +0x7C,0x9D,0x7F,0x02,0x7E,0x66,0x12,0x07, +0x50,0x7D,0x23,0x7C,0x04,0x7F,0x01,0x7E, +0x66,0x12,0x07,0x50,0x7D,0xC0,0x7C,0x00, +0x7F,0x00,0x7E,0x66,0x12,0x07,0x50,0x7D, +0x10,0x7C,0xD8,0x7F,0x02,0x7E,0x66,0x12, +0x07,0x50,0x7D,0x24,0x7C,0x04,0x7F,0x01, +0x7E,0x66,0x12,0x07,0x50,0x7D,0xC0,0x7C, +0x00,0x7F,0x00,0x7E,0x66,0x12,0x07,0x50, +0x7D,0x00,0x7C,0x04,0x7F,0x02,0x7E,0x66, +0x12,0x07,0x50,0x7D,0x2F,0x7C,0x00,0x7F, +0x01,0x7E,0x66,0x12,0x07,0x50,0x7D,0xC0, +0x7C,0x00,0x7F,0x00,0x7E,0x66,0x02,0x07, +0x50,0xE4,0x90,0x06,0x2C,0xF0,0xFD,0x7C, +0x01,0x7F,0x3F,0x7E,0x1D,0x12,0x07,0x50, +0x7D,0x40,0x7C,0x00,0x7F,0x36,0x7E,0x13, +0x12,0x07,0x50,0xE4,0xFF,0xFE,0xFD,0x80, +0x25,0xE4,0x7F,0x20,0x7E,0x4E,0xFD,0xFC, +0x90,0x06,0x24,0x12,0x01,0x0F,0xC3,0x12, +0x00,0xF2,0x50,0x1B,0x90,0x06,0x24,0x12, +0x01,0x03,0xEF,0x24,0x01,0xFF,0xE4,0x3E, +0xFE,0xE4,0x3D,0xFD,0xE4,0x3C,0xFC,0x90, +0x06,0x24,0x12,0x01,0x1B,0x80,0xD2,0xE4, +0xF5,0xA8,0xD2,0xAF,0x12,0x07,0x80,0x7D, +0xFE,0x7C,0x00,0x7F,0xAA,0x7E,0x12,0x12, +0x07,0x50,0x12,0x01,0x27,0x12,0x06,0x29, +0x12,0x07,0x2F,0x12,0x06,0x8F,0x7D,0x41, +0x7C,0x00,0x7F,0x36,0x7E,0x13,0x12,0x07, +0x50,0xE4,0xFF,0xFE,0xFD,0x80,0x25,0xE4, +0x7F,0x20,0x7E,0x4E,0xFD,0xFC,0x90,0x06, +0x24,0x12,0x01,0x0F,0xC3,0x12,0x00,0xF2, +0x50,0x1B,0x90,0x06,0x24,0x12,0x01,0x03, +0xEF,0x24,0x01,0xFF,0xE4,0x3E,0xFE,0xE4, +0x3D,0xFD,0xE4,0x3C,0xFC,0x90,0x06,0x24, +0x12,0x01,0x1B,0x80,0xD2,0xC2,0x00,0xC2, +0x01,0xD2,0xA9,0xD2,0x8C,0x7F,0x01,0x7E, +0x62,0x12,0x07,0x0B,0x7F,0x01,0x7E,0x62, +0x12,0x07,0x0B,0xEF,0x30,0xE2,0x07,0xE4, +0x90,0x06,0x2C,0xF0,0x80,0xE7,0x90,0x06, +0x2C,0xE0,0x70,0x12,0x12,0x04,0xF7,0x90, +0x06,0x2C,0x74,0x01,0xF0,0xE4,0x90,0x06, +0x33,0xF0,0xA3,0xF0,0x80,0xCF,0xC3,0x90, +0x06,0x34,0xE0,0x94,0x62,0x90,0x06,0x33, +0xE0,0x94,0x00,0x40,0xC0,0xE4,0xF0,0xA3, +0xF0,0x12,0x04,0xF7,0x90,0x06,0x2C,0x74, +0x01,0xF0,0x80,0xB1,0x7D,0x03,0x7C,0x00, +0x7F,0x01,0x7E,0x66,0x12,0x07,0x50,0x7D, +0x80,0x7C,0x00,0x7F,0x00,0x7E,0x66,0x12, +0x07,0x50,0x7F,0x02,0x7E,0x66,0x12,0x07, +0x0B,0xEF,0x44,0x40,0xFD,0xAC,0x06,0x7F, +0x02,0x7E,0x66,0x12,0x07,0x50,0x7D,0x03, +0x7C,0x00,0x7F,0x01,0x7E,0x66,0x12,0x07, +0x50,0x7D,0xC0,0x7C,0x00,0x7F,0x00,0x7E, +0x66,0x12,0x07,0x50,0x7D,0x03,0x7C,0x00, +0x7F,0x01,0x7E,0x66,0x12,0x07,0x50,0x7D, +0x80,0x7C,0x00,0x7F,0x00,0x7E,0x66,0x12, +0x07,0x50,0x7F,0x02,0x7E,0x66,0x12,0x07, +0x0B,0xEF,0x54,0xBF,0xFD,0xAC,0x06,0x7F, +0x02,0x7E,0x66,0x12,0x07,0x50,0x7D,0x03, +0x7C,0x00,0x7F,0x01,0x7E,0x66,0x12,0x07, +0x50,0x7D,0xC0,0x7C,0x00,0x7F,0x00,0x7E, +0x66,0x12,0x07,0x50,0xE4,0xFD,0xFC,0x7F, +0x01,0x7E,0x66,0x12,0x07,0x50,0x7D,0x80, +0x7C,0x00,0x7F,0x00,0x7E,0x66,0x12,0x07, +0x50,0x7F,0x02,0x7E,0x66,0x12,0x07,0x0B, +0xEF,0x54,0xFD,0x54,0xFE,0xFD,0xAC,0x06, +0x7F,0x02,0x7E,0x66,0x12,0x07,0x50,0xE4, +0xFD,0xFC,0x7F,0x01,0x7E,0x66,0x12,0x07, +0x50,0x7D,0xC0,0x7C,0x00,0x7F,0x00,0x7E, +0x66,0x12,0x07,0x50,0xE4,0xFD,0xFC,0x7F, +0x01,0x7E,0x66,0x12,0x07,0x50,0x7D,0x80, +0x7C,0x00,0x7F,0x00,0x7E,0x66,0x12,0x07, +0x50,0x7F,0x02,0x7E,0x66,0x12,0x07,0x0B, +0xEF,0x44,0x02,0x44,0x01,0xFD,0xAC,0x06, +0x7F,0x02,0x7E,0x66,0x12,0x07,0x50,0xE4, +0xFD,0xFC,0x7F,0x01,0x7E,0x66,0x12,0x07, +0x50,0x7D,0xC0,0x7C,0x00,0x7F,0x00,0x7E, +0x66,0x02,0x07,0x50,0x75,0x0F,0x80,0x75, +0x0E,0x7E,0x75,0x0D,0xAA,0x75,0x0C,0x83, +0xE4,0xF5,0x10,0x7F,0x36,0x7E,0x13,0x12, +0x07,0x0B,0xEE,0xC4,0xF8,0x54,0xF0,0xC8, +0xEF,0xC4,0x54,0x0F,0x48,0x54,0x07,0xFB, +0x7A,0x00,0xEA,0x70,0x4A,0xEB,0x14,0x60, +0x1C,0x14,0x60,0x27,0x24,0xFE,0x60,0x31, +0x14,0x60,0x3C,0x24,0x05,0x70,0x38,0x75, +0x0B,0x00,0x75,0x0A,0xC2,0x75,0x09,0xEB, +0x75,0x08,0x0B,0x80,0x36,0x75,0x0B,0x40, +0x75,0x0A,0x59,0x75,0x09,0x73,0x75,0x08, +0x07,0x80,0x28,0x75,0x0B,0x00,0x75,0x0A, +0xE1,0x75,0x09,0xF5,0x75,0x08,0x05,0x80, +0x1A,0x75,0x0B,0xA0,0x75,0x0A,0xAC,0x75, +0x09,0xB9,0x75,0x08,0x03,0x80,0x0C,0x75, +0x0B,0x00,0x75,0x0A,0x62,0x75,0x09,0x3D, +0x75,0x08,0x01,0x75,0x89,0x11,0xE4,0x7B, +0x60,0x7A,0x09,0xF9,0xF8,0xAF,0x0B,0xAE, +0x0A,0xAD,0x09,0xAC,0x08,0x12,0x00,0x60, +0xAA,0x06,0xAB,0x07,0xC3,0xE4,0x9B,0xFB, +0xE4,0x9A,0xFA,0x78,0x17,0xF6,0xAF,0x03, +0xEF,0x08,0xF6,0x18,0xE6,0xF5,0x8C,0x08, +0xE6,0xF5,0x8A,0x74,0x0D,0x2B,0xFB,0xE4, +0x3A,0x18,0xF6,0xAF,0x03,0xEF,0x08,0xF6, +0x75,0x88,0x10,0x53,0x8E,0xC7,0xD2,0xA9, +0x22,0x7D,0x02,0x7C,0x00,0x7F,0x4A,0x7E, +0x13,0x12,0x07,0x50,0x7D,0x46,0x7C,0x71, +0x7F,0x02,0x7E,0x66,0x12,0x07,0x50,0x7D, +0x03,0x7C,0x00,0x7F,0x01,0x7E,0x66,0x12, +0x07,0x50,0x7D,0xC0,0x7C,0x00,0x7F,0x00, +0x7E,0x66,0x12,0x07,0x50,0xE4,0xFF,0xFE, +0x0F,0xBF,0x00,0x01,0x0E,0xEF,0x64,0x64, +0x4E,0x70,0xF5,0x7D,0x04,0x7C,0x00,0x7F, +0x02,0x7E,0x66,0x12,0x07,0x50,0x7D,0x00, +0x7C,0x04,0x7F,0x01,0x7E,0x66,0x12,0x07, +0x50,0x7D,0xC0,0x7C,0x00,0x7F,0x00,0x7E, +0x66,0x12,0x07,0x50,0xE4,0xFD,0xFC,0x7F, +0x02,0x7E,0x66,0x12,0x07,0x50,0x7D,0x00, +0x7C,0x04,0x7F,0x01,0x7E,0x66,0x12,0x07, +0x50,0x7D,0xC0,0x7C,0x00,0x7F,0x00,0x7E, +0x66,0x12,0x07,0x50,0xE4,0xFD,0xFC,0x7F, +0x4A,0x7E,0x13,0x12,0x07,0x50,0x7D,0x06, +0x7C,0x71,0x7F,0x02,0x7E,0x66,0x12,0x07, +0x50,0x7D,0x03,0x7C,0x00,0x7F,0x01,0x7E, +0x66,0x12,0x07,0x50,0x7D,0xC0,0x7C,0x00, +0x7F,0x00,0x7E,0x66,0x02,0x07,0x50,0x78, +0x7F,0xE4,0xF6,0xD8,0xFD,0x75,0x81,0x3C, +0x02,0x05,0xE4,0x02,0x02,0x2F,0xE4,0x93, +0xA3,0xF8,0xE4,0x93,0xA3,0x40,0x03,0xF6, +0x80,0x01,0xF2,0x08,0xDF,0xF4,0x80,0x29, +0xE4,0x93,0xA3,0xF8,0x54,0x07,0x24,0x0C, +0xC8,0xC3,0x33,0xC4,0x54,0x0F,0x44,0x20, +0xC8,0x83,0x40,0x04,0xF4,0x56,0x80,0x01, +0x46,0xF6,0xDF,0xE4,0x80,0x0B,0x01,0x02, +0x04,0x08,0x10,0x20,0x40,0x80,0x90,0x07, +0x8C,0xE4,0x7E,0x01,0x93,0x60,0xBC,0xA3, +0xFF,0x54,0x3F,0x30,0xE5,0x09,0x54,0x1F, +0xFE,0xE4,0x93,0xA3,0x60,0x01,0x0E,0xCF, +0x54,0xC0,0x25,0xE0,0x60,0xA8,0x40,0xB8, +0xE4,0x93,0xA3,0xFA,0xE4,0x93,0xA3,0xF8, +0xE4,0x93,0xA3,0xC8,0xC5,0x82,0xC8,0xCA, +0xC5,0x83,0xCA,0xF0,0xA3,0xC8,0xC5,0x82, +0xC8,0xCA,0xC5,0x83,0xCA,0xDF,0xE9,0xDE, +0xE7,0x80,0xBE,0x7D,0xD7,0x7C,0x04,0x7F, +0x02,0x7E,0x66,0x12,0x07,0x50,0x7D,0x80, +0x7C,0x04,0x7F,0x01,0x7E,0x66,0x12,0x07, +0x50,0x7D,0xC0,0x7C,0x00,0x7F,0x00,0x7E, +0x66,0x12,0x07,0x50,0x7D,0x40,0x7C,0x17, +0x7F,0x11,0x7E,0x1D,0x12,0x07,0x50,0x7F, +0x41,0x7E,0x1D,0x12,0x07,0x0B,0xEF,0x44, +0x20,0x44,0x80,0xFD,0xAC,0x06,0x7F,0x41, +0x7E,0x1D,0x12,0x07,0x50,0x7D,0xBB,0x7C, +0x15,0x7F,0xEB,0x7E,0x13,0x12,0x07,0x50, +0x7D,0x07,0x7C,0x00,0x7F,0xE7,0x7E,0x13, +0x12,0x07,0x50,0x7D,0x40,0x7C,0x11,0x7F, +0x00,0x7E,0x62,0x12,0x07,0x50,0x02,0x03, +0x32,0x7D,0x04,0x7C,0x00,0x7F,0x01,0x7E, +0x66,0x12,0x07,0x50,0x7D,0x80,0x7C,0x00, +0x7F,0x00,0x7E,0x66,0x12,0x07,0x50,0x7F, +0x02,0x7E,0x66,0x12,0x07,0x0B,0xEF,0x44, +0x02,0x44,0x04,0xFD,0xAC,0x06,0x7F,0x02, +0x7E,0x66,0x12,0x07,0x50,0x7D,0x04,0x7C, +0x00,0x7F,0x01,0x7E,0x66,0x12,0x07,0x50, +0x7D,0xC0,0x7C,0x00,0x7F,0x00,0x7E,0x66, +0x02,0x07,0x50,0xC0,0xE0,0xC0,0xF0,0xC0, +0x83,0xC0,0x82,0xC0,0xD0,0x75,0xD0,0x00, +0xC0,0x00,0x78,0x17,0xE6,0xF5,0x8C,0x78, +0x18,0xE6,0xF5,0x8A,0x90,0x06,0x31,0xE4, +0x75,0xF0,0x01,0x12,0x00,0x0E,0x90,0x06, +0x33,0xE4,0x75,0xF0,0x01,0x12,0x00,0x0E, +0xD0,0x00,0xD0,0xD0,0xD0,0x82,0xD0,0x83, +0xD0,0xF0,0xD0,0xE0,0x32,0xC2,0xAF,0xAD, +0x07,0xAC,0x06,0x8C,0xA2,0x8D,0xA3,0x75, +0xA0,0x01,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0xAE,0xA1,0xBE, +0x00,0xF0,0xAE,0xA6,0xAF,0xA7,0xD2,0xAF, +0x22,0x7D,0x20,0x7C,0x0F,0x7F,0x02,0x7E, +0x66,0x12,0x07,0x50,0x7D,0x01,0x7C,0x00, +0x7F,0x01,0x7E,0x66,0x12,0x07,0x50,0x7D, +0xC0,0x7C,0x00,0x7F,0x00,0x7E,0x66,0x02, +0x07,0x50,0xC2,0xAF,0xAB,0x07,0xAA,0x06, +0x8A,0xA2,0x8B,0xA3,0x8C,0xA4,0x8D,0xA5, +0x75,0xA0,0x03,0x00,0x00,0x00,0xAA,0xA1, +0xBA,0x00,0xF8,0xD2,0xAF,0x22,0x7F,0x0C, +0x7E,0x13,0x12,0x07,0x0B,0xEF,0x44,0x50, +0xFD,0xAC,0x06,0x7F,0x0C,0x7E,0x13,0x02, +0x07,0x50,0x12,0x07,0x6C,0x12,0x07,0x97, +0x12,0x04,0x32,0x02,0x00,0x03,0x42,0x06, +0x33,0x00,0x00,0x42,0x06,0x31,0x00,0x00, +0x00,0xE4,0xF5,0x8E,0x22}; + +#define FIBER2_1G_INIT_SIZE 1842 +rtk_uint8 Fiber2_1G[FIBER2_1G_INIT_SIZE] = { +0x02,0x05,0x97,0xE4,0xF5,0xA8, +0xD2,0xAF,0x22,0x00,0x00,0x02,0x06,0x89, +0xC5,0xF0,0xF8,0xA3,0xE0,0x28,0xF0,0xC5, +0xF0,0xF8,0xE5,0x82,0x15,0x82,0x70,0x02, +0x15,0x83,0xE0,0x38,0xF0,0x22,0x75,0xF0, +0x08,0x75,0x82,0x00,0xEF,0x2F,0xFF,0xEE, +0x33,0xFE,0xCD,0x33,0xCD,0xCC,0x33,0xCC, +0xC5,0x82,0x33,0xC5,0x82,0x9B,0xED,0x9A, +0xEC,0x99,0xE5,0x82,0x98,0x40,0x0C,0xF5, +0x82,0xEE,0x9B,0xFE,0xED,0x9A,0xFD,0xEC, +0x99,0xFC,0x0F,0xD5,0xF0,0xD6,0xE4,0xCE, +0xFB,0xE4,0xCD,0xFA,0xE4,0xCC,0xF9,0xA8, +0x82,0x22,0xB8,0x00,0xC1,0xB9,0x00,0x59, +0xBA,0x00,0x2D,0xEC,0x8B,0xF0,0x84,0xCF, +0xCE,0xCD,0xFC,0xE5,0xF0,0xCB,0xF9,0x78, +0x18,0xEF,0x2F,0xFF,0xEE,0x33,0xFE,0xED, +0x33,0xFD,0xEC,0x33,0xFC,0xEB,0x33,0xFB, +0x10,0xD7,0x03,0x99,0x40,0x04,0xEB,0x99, +0xFB,0x0F,0xD8,0xE5,0xE4,0xF9,0xFA,0x22, +0x78,0x18,0xEF,0x2F,0xFF,0xEE,0x33,0xFE, +0xED,0x33,0xFD,0xEC,0x33,0xFC,0xC9,0x33, +0xC9,0x10,0xD7,0x05,0x9B,0xE9,0x9A,0x40, +0x07,0xEC,0x9B,0xFC,0xE9,0x9A,0xF9,0x0F, +0xD8,0xE0,0xE4,0xC9,0xFA,0xE4,0xCC,0xFB, +0x22,0x75,0xF0,0x10,0xEF,0x2F,0xFF,0xEE, +0x33,0xFE,0xED,0x33,0xFD,0xCC,0x33,0xCC, +0xC8,0x33,0xC8,0x10,0xD7,0x07,0x9B,0xEC, +0x9A,0xE8,0x99,0x40,0x0A,0xED,0x9B,0xFD, +0xEC,0x9A,0xFC,0xE8,0x99,0xF8,0x0F,0xD5, +0xF0,0xDA,0xE4,0xCD,0xFB,0xE4,0xCC,0xFA, +0xE4,0xC8,0xF9,0x22,0xEB,0x9F,0xF5,0xF0, +0xEA,0x9E,0x42,0xF0,0xE9,0x9D,0x42,0xF0, +0xE8,0x9C,0x45,0xF0,0x22,0xE0,0xFC,0xA3, +0xE0,0xFD,0xA3,0xE0,0xFE,0xA3,0xE0,0xFF, +0x22,0xE0,0xF8,0xA3,0xE0,0xF9,0xA3,0xE0, +0xFA,0xA3,0xE0,0xFB,0x22,0xEC,0xF0,0xA3, +0xED,0xF0,0xA3,0xEE,0xF0,0xA3,0xEF,0xF0, +0x22,0x7D,0xD7,0x7C,0x04,0x7F,0x02,0x7E, +0x66,0x12,0x06,0xE7,0x7D,0x80,0x7C,0x04, +0x7F,0x01,0x7E,0x66,0x12,0x06,0xE7,0x7D, +0xC0,0x7C,0x00,0x7F,0x00,0x7E,0x66,0x12, +0x06,0xE7,0x7D,0x94,0x7C,0xF9,0x7F,0x02, +0x7E,0x66,0x12,0x06,0xE7,0x7D,0x81,0x7C, +0x04,0x7F,0x01,0x7E,0x66,0x12,0x06,0xE7, +0x7D,0xC0,0x7C,0x00,0x7F,0x00,0x7E,0x66, +0x12,0x06,0xE7,0x7D,0xA2,0x7C,0x31,0x7F, +0x02,0x7E,0x66,0x12,0x06,0xE7,0x7D,0x82, +0x7C,0x04,0x7F,0x01,0x7E,0x66,0x12,0x06, +0xE7,0x7D,0xC0,0x7C,0x00,0x7F,0x00,0x7E, +0x66,0x12,0x06,0xE7,0x7D,0x60,0x7C,0x69, +0x7F,0x02,0x7E,0x66,0x12,0x06,0xE7,0x7D, +0x83,0x7C,0x04,0x7F,0x01,0x7E,0x66,0x12, +0x06,0xE7,0x7D,0xC0,0x7C,0x00,0x7F,0x00, +0x7E,0x66,0x12,0x06,0xE7,0x7D,0x28,0x7C, +0x97,0x7F,0x02,0x7E,0x66,0x12,0x06,0xE7, +0x7D,0x84,0x7C,0x04,0x7F,0x01,0x7E,0x66, +0x12,0x06,0xE7,0x7D,0xC0,0x7C,0x00,0x7F, +0x00,0x7E,0x66,0x12,0x06,0xE7,0x7D,0x85, +0x7C,0x9D,0x7F,0x02,0x7E,0x66,0x12,0x06, +0xE7,0x7D,0x23,0x7C,0x04,0x7F,0x01,0x7E, +0x66,0x12,0x06,0xE7,0x7D,0xC0,0x7C,0x00, +0x7F,0x00,0x7E,0x66,0x12,0x06,0xE7,0x7D, +0x10,0x7C,0xD8,0x7F,0x02,0x7E,0x66,0x12, +0x06,0xE7,0x7D,0x24,0x7C,0x04,0x7F,0x01, +0x7E,0x66,0x12,0x06,0xE7,0x7D,0xC0,0x7C, +0x00,0x7F,0x00,0x7E,0x66,0x12,0x06,0xE7, +0x7D,0x00,0x7C,0x04,0x7F,0x02,0x7E,0x66, +0x12,0x06,0xE7,0x7D,0x2F,0x7C,0x00,0x7F, +0x01,0x7E,0x66,0x12,0x06,0xE7,0x7D,0xC0, +0x7C,0x00,0x7F,0x00,0x7E,0x66,0x02,0x06, +0xE7,0x7D,0x03,0x7C,0x00,0x7F,0x01,0x7E, +0x66,0x12,0x06,0xE7,0x7D,0x80,0x7C,0x00, +0x7F,0x00,0x7E,0x66,0x12,0x06,0xE7,0x7F, +0x02,0x7E,0x66,0x12,0x06,0xC3,0xEF,0x44, +0x40,0xFD,0xAC,0x06,0x7F,0x02,0x7E,0x66, +0x12,0x06,0xE7,0x7D,0x03,0x7C,0x00,0x7F, +0x01,0x7E,0x66,0x12,0x06,0xE7,0x7D,0xC0, +0x7C,0x00,0x7F,0x00,0x7E,0x66,0x12,0x06, +0xE7,0x7D,0x03,0x7C,0x00,0x7F,0x01,0x7E, +0x66,0x12,0x06,0xE7,0x7D,0x80,0x7C,0x00, +0x7F,0x00,0x7E,0x66,0x12,0x06,0xE7,0x7F, +0x02,0x7E,0x66,0x12,0x06,0xC3,0xEF,0x54, +0xBF,0xFD,0xAC,0x06,0x7F,0x02,0x7E,0x66, +0x12,0x06,0xE7,0x7D,0x03,0x7C,0x00,0x7F, +0x01,0x7E,0x66,0x12,0x06,0xE7,0x7D,0xC0, +0x7C,0x00,0x7F,0x00,0x7E,0x66,0x12,0x06, +0xE7,0xE4,0xFD,0xFC,0x7F,0x01,0x7E,0x66, +0x12,0x06,0xE7,0x7D,0x80,0x7C,0x00,0x7F, +0x00,0x7E,0x66,0x12,0x06,0xE7,0x7F,0x02, +0x7E,0x66,0x12,0x06,0xC3,0xEF,0x54,0xFD, +0x54,0xFE,0xFD,0xAC,0x06,0x7F,0x02,0x7E, +0x66,0x12,0x06,0xE7,0xE4,0xFD,0xFC,0x7F, +0x01,0x7E,0x66,0x12,0x06,0xE7,0x7D,0xC0, +0x7C,0x00,0x7F,0x00,0x7E,0x66,0x12,0x06, +0xE7,0xE4,0xFD,0xFC,0x7F,0x01,0x7E,0x66, +0x12,0x06,0xE7,0x7D,0x80,0x7C,0x00,0x7F, +0x00,0x7E,0x66,0x12,0x06,0xE7,0x7F,0x02, +0x7E,0x66,0x12,0x06,0xC3,0xEF,0x44,0x02, +0x44,0x01,0xFD,0xAC,0x06,0x7F,0x02,0x7E, +0x66,0x12,0x06,0xE7,0xE4,0xFD,0xFC,0x7F, +0x01,0x7E,0x66,0x12,0x06,0xE7,0x7D,0xC0, +0x7C,0x00,0x7F,0x00,0x7E,0x66,0x02,0x06, +0xE7,0xE4,0x90,0x06,0x2C,0xF0,0xFD,0x7C, +0x01,0x7F,0x3F,0x7E,0x1D,0x12,0x06,0xE7, +0x7D,0x40,0x7C,0x00,0x7F,0x36,0x7E,0x13, +0x12,0x06,0xE7,0xE4,0xFF,0xFE,0xFD,0x80, +0x25,0xE4,0x7F,0x20,0x7E,0x4E,0xFD,0xFC, +0x90,0x06,0x24,0x12,0x01,0x0F,0xC3,0x12, +0x00,0xF2,0x50,0x1B,0x90,0x06,0x24,0x12, +0x01,0x03,0xEF,0x24,0x01,0xFF,0xE4,0x3E, +0xFE,0xE4,0x3D,0xFD,0xE4,0x3C,0xFC,0x90, +0x06,0x24,0x12,0x01,0x1B,0x80,0xD2,0xE4, +0xF5,0xA8,0xD2,0xAF,0x12,0x07,0x17,0x7D, +0xFE,0x7C,0x00,0x7F,0xAA,0x7E,0x12,0x12, +0x06,0xE7,0x12,0x01,0x27,0x12,0x06,0x23, +0x7D,0x41,0x7C,0x00,0x7F,0x36,0x7E,0x13, +0x12,0x06,0xE7,0xE4,0xFF,0xFE,0xFD,0x80, +0x25,0xE4,0x7F,0x20,0x7E,0x4E,0xFD,0xFC, +0x90,0x06,0x24,0x12,0x01,0x0F,0xC3,0x12, +0x00,0xF2,0x50,0x1B,0x90,0x06,0x24,0x12, +0x01,0x03,0xEF,0x24,0x01,0xFF,0xE4,0x3E, +0xFE,0xE4,0x3D,0xFD,0xE4,0x3C,0xFC,0x90, +0x06,0x24,0x12,0x01,0x1B,0x80,0xD2,0xC2, +0x00,0xC2,0x01,0xD2,0xA9,0xD2,0x8C,0x7F, +0x01,0x7E,0x62,0x12,0x06,0xC3,0x7F,0x01, +0x7E,0x62,0x12,0x06,0xC3,0xEF,0x30,0xE2, +0x07,0xE4,0x90,0x06,0x2C,0xF0,0x80,0xE7, +0x90,0x06,0x2C,0xE0,0x70,0x12,0x12,0x04, +0xF1,0x90,0x06,0x2C,0x74,0x01,0xF0,0xE4, +0x90,0x06,0x33,0xF0,0xA3,0xF0,0x80,0xCF, +0xC3,0x90,0x06,0x34,0xE0,0x94,0x62,0x90, +0x06,0x33,0xE0,0x94,0x00,0x40,0xC0,0xE4, +0xF0,0xA3,0xF0,0x12,0x04,0xF1,0x90,0x06, +0x2C,0x74,0x01,0xF0,0x80,0xB1,0x75,0x0F, +0x80,0x75,0x0E,0x7E,0x75,0x0D,0xAA,0x75, +0x0C,0x83,0xE4,0xF5,0x10,0x7F,0x36,0x7E, +0x13,0x12,0x06,0xC3,0xEE,0xC4,0xF8,0x54, +0xF0,0xC8,0xEF,0xC4,0x54,0x0F,0x48,0x54, +0x07,0xFB,0x7A,0x00,0xEA,0x70,0x4A,0xEB, +0x14,0x60,0x1C,0x14,0x60,0x27,0x24,0xFE, +0x60,0x31,0x14,0x60,0x3C,0x24,0x05,0x70, +0x38,0x75,0x0B,0x00,0x75,0x0A,0xC2,0x75, +0x09,0xEB,0x75,0x08,0x0B,0x80,0x36,0x75, +0x0B,0x40,0x75,0x0A,0x59,0x75,0x09,0x73, +0x75,0x08,0x07,0x80,0x28,0x75,0x0B,0x00, +0x75,0x0A,0xE1,0x75,0x09,0xF5,0x75,0x08, +0x05,0x80,0x1A,0x75,0x0B,0xA0,0x75,0x0A, +0xAC,0x75,0x09,0xB9,0x75,0x08,0x03,0x80, +0x0C,0x75,0x0B,0x00,0x75,0x0A,0x62,0x75, +0x09,0x3D,0x75,0x08,0x01,0x75,0x89,0x11, +0xE4,0x7B,0x60,0x7A,0x09,0xF9,0xF8,0xAF, +0x0B,0xAE,0x0A,0xAD,0x09,0xAC,0x08,0x12, +0x00,0x60,0xAA,0x06,0xAB,0x07,0xC3,0xE4, +0x9B,0xFB,0xE4,0x9A,0xFA,0x78,0x17,0xF6, +0xAF,0x03,0xEF,0x08,0xF6,0x18,0xE6,0xF5, +0x8C,0x08,0xE6,0xF5,0x8A,0x74,0x0D,0x2B, +0xFB,0xE4,0x3A,0x18,0xF6,0xAF,0x03,0xEF, +0x08,0xF6,0x75,0x88,0x10,0x53,0x8E,0xC7, +0xD2,0xA9,0x22,0x7D,0x02,0x7C,0x00,0x7F, +0x4A,0x7E,0x13,0x12,0x06,0xE7,0x7D,0x46, +0x7C,0x71,0x7F,0x02,0x7E,0x66,0x12,0x06, +0xE7,0x7D,0x03,0x7C,0x00,0x7F,0x01,0x7E, +0x66,0x12,0x06,0xE7,0x7D,0xC0,0x7C,0x00, +0x7F,0x00,0x7E,0x66,0x12,0x06,0xE7,0xE4, +0xFF,0xFE,0x0F,0xBF,0x00,0x01,0x0E,0xEF, +0x64,0x64,0x4E,0x70,0xF5,0x7D,0x04,0x7C, +0x00,0x7F,0x02,0x7E,0x66,0x12,0x06,0xE7, +0x7D,0x00,0x7C,0x04,0x7F,0x01,0x7E,0x66, +0x12,0x06,0xE7,0x7D,0xC0,0x7C,0x00,0x7F, +0x00,0x7E,0x66,0x12,0x06,0xE7,0xE4,0xFD, +0xFC,0x7F,0x02,0x7E,0x66,0x12,0x06,0xE7, +0x7D,0x00,0x7C,0x04,0x7F,0x01,0x7E,0x66, +0x12,0x06,0xE7,0x7D,0xC0,0x7C,0x00,0x7F, +0x00,0x7E,0x66,0x12,0x06,0xE7,0xE4,0xFD, +0xFC,0x7F,0x4A,0x7E,0x13,0x12,0x06,0xE7, +0x7D,0x06,0x7C,0x71,0x7F,0x02,0x7E,0x66, +0x12,0x06,0xE7,0x7D,0x03,0x7C,0x00,0x7F, +0x01,0x7E,0x66,0x12,0x06,0xE7,0x7D,0xC0, +0x7C,0x00,0x7F,0x00,0x7E,0x66,0x02,0x06, +0xE7,0x78,0x7F,0xE4,0xF6,0xD8,0xFD,0x75, +0x81,0x3C,0x02,0x05,0xDE,0x02,0x03,0x2F, +0xE4,0x93,0xA3,0xF8,0xE4,0x93,0xA3,0x40, +0x03,0xF6,0x80,0x01,0xF2,0x08,0xDF,0xF4, +0x80,0x29,0xE4,0x93,0xA3,0xF8,0x54,0x07, +0x24,0x0C,0xC8,0xC3,0x33,0xC4,0x54,0x0F, +0x44,0x20,0xC8,0x83,0x40,0x04,0xF4,0x56, +0x80,0x01,0x46,0xF6,0xDF,0xE4,0x80,0x0B, +0x01,0x02,0x04,0x08,0x10,0x20,0x40,0x80, +0x90,0x07,0x23,0xE4,0x7E,0x01,0x93,0x60, +0xBC,0xA3,0xFF,0x54,0x3F,0x30,0xE5,0x09, +0x54,0x1F,0xFE,0xE4,0x93,0xA3,0x60,0x01, +0x0E,0xCF,0x54,0xC0,0x25,0xE0,0x60,0xA8, +0x40,0xB8,0xE4,0x93,0xA3,0xFA,0xE4,0x93, +0xA3,0xF8,0xE4,0x93,0xA3,0xC8,0xC5,0x82, +0xC8,0xCA,0xC5,0x83,0xCA,0xF0,0xA3,0xC8, +0xC5,0x82,0xC8,0xCA,0xC5,0x83,0xCA,0xDF, +0xE9,0xDE,0xE7,0x80,0xBE,0x7D,0xD7,0x7C, +0x04,0x7F,0x02,0x7E,0x66,0x12,0x06,0xE7, +0x7D,0x80,0x7C,0x04,0x7F,0x01,0x7E,0x66, +0x12,0x06,0xE7,0x7D,0xC0,0x7C,0x00,0x7F, +0x00,0x7E,0x66,0x12,0x06,0xE7,0x7D,0x40, +0x7C,0x17,0x7F,0x11,0x7E,0x1D,0x12,0x06, +0xE7,0x7D,0xBB,0x7C,0x15,0x7F,0xEB,0x7E, +0x13,0x12,0x06,0xE7,0x7D,0x0C,0x7C,0x00, +0x7F,0xE7,0x7E,0x13,0x12,0x06,0xE7,0x7F, +0x41,0x7E,0x1D,0x12,0x06,0xC3,0xEF,0x44, +0x20,0x44,0x80,0xFD,0xAC,0x06,0x7F,0x41, +0x7E,0x1D,0x12,0x06,0xE7,0x7D,0x40,0x7C, +0x01,0x7F,0x00,0x7E,0x62,0x12,0x06,0xE7, +0x02,0x02,0x2F,0xC0,0xE0,0xC0,0xF0,0xC0, +0x83,0xC0,0x82,0xC0,0xD0,0x75,0xD0,0x00, +0xC0,0x00,0x78,0x17,0xE6,0xF5,0x8C,0x78, +0x18,0xE6,0xF5,0x8A,0x90,0x06,0x31,0xE4, +0x75,0xF0,0x01,0x12,0x00,0x0E,0x90,0x06, +0x33,0xE4,0x75,0xF0,0x01,0x12,0x00,0x0E, +0xD0,0x00,0xD0,0xD0,0xD0,0x82,0xD0,0x83, +0xD0,0xF0,0xD0,0xE0,0x32,0xC2,0xAF,0xAD, +0x07,0xAC,0x06,0x8C,0xA2,0x8D,0xA3,0x75, +0xA0,0x01,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0xAE,0xA1,0xBE, +0x00,0xF0,0xAE,0xA6,0xAF,0xA7,0xD2,0xAF, +0x22,0xC2,0xAF,0xAB,0x07,0xAA,0x06,0x8A, +0xA2,0x8B,0xA3,0x8C,0xA4,0x8D,0xA5,0x75, +0xA0,0x03,0x00,0x00,0x00,0xAA,0xA1,0xBA, +0x00,0xF8,0xD2,0xAF,0x22,0x7F,0x0C,0x7E, +0x13,0x12,0x06,0xC3,0xEF,0x44,0x50,0xFD, +0xAC,0x06,0x7F,0x0C,0x7E,0x13,0x02,0x06, +0xE7,0x12,0x07,0x03,0x12,0x07,0x2E,0x12, +0x04,0x2C,0x02,0x00,0x03,0x42,0x06,0x33, +0x00,0x00,0x42,0x06,0x31,0x00,0x00,0x00, +0xE4,0xF5,0x8E,0x22}; + +#define FIBER2_100M_INIT_SIZE 1842 +rtk_uint8 Fiber2_100M[FIBER2_100M_INIT_SIZE] = { +0x02,0x05,0x97,0xE4,0xF5,0xA8, +0xD2,0xAF,0x22,0x00,0x00,0x02,0x06,0x89, +0xC5,0xF0,0xF8,0xA3,0xE0,0x28,0xF0,0xC5, +0xF0,0xF8,0xE5,0x82,0x15,0x82,0x70,0x02, +0x15,0x83,0xE0,0x38,0xF0,0x22,0x75,0xF0, +0x08,0x75,0x82,0x00,0xEF,0x2F,0xFF,0xEE, +0x33,0xFE,0xCD,0x33,0xCD,0xCC,0x33,0xCC, +0xC5,0x82,0x33,0xC5,0x82,0x9B,0xED,0x9A, +0xEC,0x99,0xE5,0x82,0x98,0x40,0x0C,0xF5, +0x82,0xEE,0x9B,0xFE,0xED,0x9A,0xFD,0xEC, +0x99,0xFC,0x0F,0xD5,0xF0,0xD6,0xE4,0xCE, +0xFB,0xE4,0xCD,0xFA,0xE4,0xCC,0xF9,0xA8, +0x82,0x22,0xB8,0x00,0xC1,0xB9,0x00,0x59, +0xBA,0x00,0x2D,0xEC,0x8B,0xF0,0x84,0xCF, +0xCE,0xCD,0xFC,0xE5,0xF0,0xCB,0xF9,0x78, +0x18,0xEF,0x2F,0xFF,0xEE,0x33,0xFE,0xED, +0x33,0xFD,0xEC,0x33,0xFC,0xEB,0x33,0xFB, +0x10,0xD7,0x03,0x99,0x40,0x04,0xEB,0x99, +0xFB,0x0F,0xD8,0xE5,0xE4,0xF9,0xFA,0x22, +0x78,0x18,0xEF,0x2F,0xFF,0xEE,0x33,0xFE, +0xED,0x33,0xFD,0xEC,0x33,0xFC,0xC9,0x33, +0xC9,0x10,0xD7,0x05,0x9B,0xE9,0x9A,0x40, +0x07,0xEC,0x9B,0xFC,0xE9,0x9A,0xF9,0x0F, +0xD8,0xE0,0xE4,0xC9,0xFA,0xE4,0xCC,0xFB, +0x22,0x75,0xF0,0x10,0xEF,0x2F,0xFF,0xEE, +0x33,0xFE,0xED,0x33,0xFD,0xCC,0x33,0xCC, +0xC8,0x33,0xC8,0x10,0xD7,0x07,0x9B,0xEC, +0x9A,0xE8,0x99,0x40,0x0A,0xED,0x9B,0xFD, +0xEC,0x9A,0xFC,0xE8,0x99,0xF8,0x0F,0xD5, +0xF0,0xDA,0xE4,0xCD,0xFB,0xE4,0xCC,0xFA, +0xE4,0xC8,0xF9,0x22,0xEB,0x9F,0xF5,0xF0, +0xEA,0x9E,0x42,0xF0,0xE9,0x9D,0x42,0xF0, +0xE8,0x9C,0x45,0xF0,0x22,0xE0,0xFC,0xA3, +0xE0,0xFD,0xA3,0xE0,0xFE,0xA3,0xE0,0xFF, +0x22,0xE0,0xF8,0xA3,0xE0,0xF9,0xA3,0xE0, +0xFA,0xA3,0xE0,0xFB,0x22,0xEC,0xF0,0xA3, +0xED,0xF0,0xA3,0xEE,0xF0,0xA3,0xEF,0xF0, +0x22,0x7D,0xD7,0x7C,0x04,0x7F,0x02,0x7E, +0x66,0x12,0x06,0xE7,0x7D,0x80,0x7C,0x04, +0x7F,0x01,0x7E,0x66,0x12,0x06,0xE7,0x7D, +0xC0,0x7C,0x00,0x7F,0x00,0x7E,0x66,0x12, +0x06,0xE7,0x7D,0x94,0x7C,0xF9,0x7F,0x02, +0x7E,0x66,0x12,0x06,0xE7,0x7D,0x81,0x7C, +0x04,0x7F,0x01,0x7E,0x66,0x12,0x06,0xE7, +0x7D,0xC0,0x7C,0x00,0x7F,0x00,0x7E,0x66, +0x12,0x06,0xE7,0x7D,0xA2,0x7C,0x31,0x7F, +0x02,0x7E,0x66,0x12,0x06,0xE7,0x7D,0x82, +0x7C,0x04,0x7F,0x01,0x7E,0x66,0x12,0x06, +0xE7,0x7D,0xC0,0x7C,0x00,0x7F,0x00,0x7E, +0x66,0x12,0x06,0xE7,0x7D,0x60,0x7C,0x69, +0x7F,0x02,0x7E,0x66,0x12,0x06,0xE7,0x7D, +0x83,0x7C,0x04,0x7F,0x01,0x7E,0x66,0x12, +0x06,0xE7,0x7D,0xC0,0x7C,0x00,0x7F,0x00, +0x7E,0x66,0x12,0x06,0xE7,0x7D,0x28,0x7C, +0x97,0x7F,0x02,0x7E,0x66,0x12,0x06,0xE7, +0x7D,0x84,0x7C,0x04,0x7F,0x01,0x7E,0x66, +0x12,0x06,0xE7,0x7D,0xC0,0x7C,0x00,0x7F, +0x00,0x7E,0x66,0x12,0x06,0xE7,0x7D,0x85, +0x7C,0x9D,0x7F,0x02,0x7E,0x66,0x12,0x06, +0xE7,0x7D,0x23,0x7C,0x04,0x7F,0x01,0x7E, +0x66,0x12,0x06,0xE7,0x7D,0xC0,0x7C,0x00, +0x7F,0x00,0x7E,0x66,0x12,0x06,0xE7,0x7D, +0x10,0x7C,0xD8,0x7F,0x02,0x7E,0x66,0x12, +0x06,0xE7,0x7D,0x24,0x7C,0x04,0x7F,0x01, +0x7E,0x66,0x12,0x06,0xE7,0x7D,0xC0,0x7C, +0x00,0x7F,0x00,0x7E,0x66,0x12,0x06,0xE7, +0x7D,0x00,0x7C,0x04,0x7F,0x02,0x7E,0x66, +0x12,0x06,0xE7,0x7D,0x2F,0x7C,0x00,0x7F, +0x01,0x7E,0x66,0x12,0x06,0xE7,0x7D,0xC0, +0x7C,0x00,0x7F,0x00,0x7E,0x66,0x02,0x06, +0xE7,0x7D,0x03,0x7C,0x00,0x7F,0x01,0x7E, +0x66,0x12,0x06,0xE7,0x7D,0x80,0x7C,0x00, +0x7F,0x00,0x7E,0x66,0x12,0x06,0xE7,0x7F, +0x02,0x7E,0x66,0x12,0x06,0xC3,0xEF,0x44, +0x40,0xFD,0xAC,0x06,0x7F,0x02,0x7E,0x66, +0x12,0x06,0xE7,0x7D,0x03,0x7C,0x00,0x7F, +0x01,0x7E,0x66,0x12,0x06,0xE7,0x7D,0xC0, +0x7C,0x00,0x7F,0x00,0x7E,0x66,0x12,0x06, +0xE7,0x7D,0x03,0x7C,0x00,0x7F,0x01,0x7E, +0x66,0x12,0x06,0xE7,0x7D,0x80,0x7C,0x00, +0x7F,0x00,0x7E,0x66,0x12,0x06,0xE7,0x7F, +0x02,0x7E,0x66,0x12,0x06,0xC3,0xEF,0x54, +0xBF,0xFD,0xAC,0x06,0x7F,0x02,0x7E,0x66, +0x12,0x06,0xE7,0x7D,0x03,0x7C,0x00,0x7F, +0x01,0x7E,0x66,0x12,0x06,0xE7,0x7D,0xC0, +0x7C,0x00,0x7F,0x00,0x7E,0x66,0x12,0x06, +0xE7,0xE4,0xFD,0xFC,0x7F,0x01,0x7E,0x66, +0x12,0x06,0xE7,0x7D,0x80,0x7C,0x00,0x7F, +0x00,0x7E,0x66,0x12,0x06,0xE7,0x7F,0x02, +0x7E,0x66,0x12,0x06,0xC3,0xEF,0x54,0xFD, +0x54,0xFE,0xFD,0xAC,0x06,0x7F,0x02,0x7E, +0x66,0x12,0x06,0xE7,0xE4,0xFD,0xFC,0x7F, +0x01,0x7E,0x66,0x12,0x06,0xE7,0x7D,0xC0, +0x7C,0x00,0x7F,0x00,0x7E,0x66,0x12,0x06, +0xE7,0xE4,0xFD,0xFC,0x7F,0x01,0x7E,0x66, +0x12,0x06,0xE7,0x7D,0x80,0x7C,0x00,0x7F, +0x00,0x7E,0x66,0x12,0x06,0xE7,0x7F,0x02, +0x7E,0x66,0x12,0x06,0xC3,0xEF,0x44,0x02, +0x44,0x01,0xFD,0xAC,0x06,0x7F,0x02,0x7E, +0x66,0x12,0x06,0xE7,0xE4,0xFD,0xFC,0x7F, +0x01,0x7E,0x66,0x12,0x06,0xE7,0x7D,0xC0, +0x7C,0x00,0x7F,0x00,0x7E,0x66,0x02,0x06, +0xE7,0xE4,0x90,0x06,0x2C,0xF0,0xFD,0x7C, +0x01,0x7F,0x3F,0x7E,0x1D,0x12,0x06,0xE7, +0x7D,0x40,0x7C,0x00,0x7F,0x36,0x7E,0x13, +0x12,0x06,0xE7,0xE4,0xFF,0xFE,0xFD,0x80, +0x25,0xE4,0x7F,0x20,0x7E,0x4E,0xFD,0xFC, +0x90,0x06,0x24,0x12,0x01,0x0F,0xC3,0x12, +0x00,0xF2,0x50,0x1B,0x90,0x06,0x24,0x12, +0x01,0x03,0xEF,0x24,0x01,0xFF,0xE4,0x3E, +0xFE,0xE4,0x3D,0xFD,0xE4,0x3C,0xFC,0x90, +0x06,0x24,0x12,0x01,0x1B,0x80,0xD2,0xE4, +0xF5,0xA8,0xD2,0xAF,0x12,0x07,0x17,0x7D, +0xFE,0x7C,0x00,0x7F,0xAA,0x7E,0x12,0x12, +0x06,0xE7,0x12,0x01,0x27,0x12,0x06,0x23, +0x7D,0x41,0x7C,0x00,0x7F,0x36,0x7E,0x13, +0x12,0x06,0xE7,0xE4,0xFF,0xFE,0xFD,0x80, +0x25,0xE4,0x7F,0x20,0x7E,0x4E,0xFD,0xFC, +0x90,0x06,0x24,0x12,0x01,0x0F,0xC3,0x12, +0x00,0xF2,0x50,0x1B,0x90,0x06,0x24,0x12, +0x01,0x03,0xEF,0x24,0x01,0xFF,0xE4,0x3E, +0xFE,0xE4,0x3D,0xFD,0xE4,0x3C,0xFC,0x90, +0x06,0x24,0x12,0x01,0x1B,0x80,0xD2,0xC2, +0x00,0xC2,0x01,0xD2,0xA9,0xD2,0x8C,0x7F, +0x01,0x7E,0x62,0x12,0x06,0xC3,0x7F,0x01, +0x7E,0x62,0x12,0x06,0xC3,0xEF,0x30,0xE2, +0x07,0xE4,0x90,0x06,0x2C,0xF0,0x80,0xE7, +0x90,0x06,0x2C,0xE0,0x70,0x12,0x12,0x04, +0xF1,0x90,0x06,0x2C,0x74,0x01,0xF0,0xE4, +0x90,0x06,0x33,0xF0,0xA3,0xF0,0x80,0xCF, +0xC3,0x90,0x06,0x34,0xE0,0x94,0x62,0x90, +0x06,0x33,0xE0,0x94,0x00,0x40,0xC0,0xE4, +0xF0,0xA3,0xF0,0x12,0x04,0xF1,0x90,0x06, +0x2C,0x74,0x01,0xF0,0x80,0xB1,0x75,0x0F, +0x80,0x75,0x0E,0x7E,0x75,0x0D,0xAA,0x75, +0x0C,0x83,0xE4,0xF5,0x10,0x7F,0x36,0x7E, +0x13,0x12,0x06,0xC3,0xEE,0xC4,0xF8,0x54, +0xF0,0xC8,0xEF,0xC4,0x54,0x0F,0x48,0x54, +0x07,0xFB,0x7A,0x00,0xEA,0x70,0x4A,0xEB, +0x14,0x60,0x1C,0x14,0x60,0x27,0x24,0xFE, +0x60,0x31,0x14,0x60,0x3C,0x24,0x05,0x70, +0x38,0x75,0x0B,0x00,0x75,0x0A,0xC2,0x75, +0x09,0xEB,0x75,0x08,0x0B,0x80,0x36,0x75, +0x0B,0x40,0x75,0x0A,0x59,0x75,0x09,0x73, +0x75,0x08,0x07,0x80,0x28,0x75,0x0B,0x00, +0x75,0x0A,0xE1,0x75,0x09,0xF5,0x75,0x08, +0x05,0x80,0x1A,0x75,0x0B,0xA0,0x75,0x0A, +0xAC,0x75,0x09,0xB9,0x75,0x08,0x03,0x80, +0x0C,0x75,0x0B,0x00,0x75,0x0A,0x62,0x75, +0x09,0x3D,0x75,0x08,0x01,0x75,0x89,0x11, +0xE4,0x7B,0x60,0x7A,0x09,0xF9,0xF8,0xAF, +0x0B,0xAE,0x0A,0xAD,0x09,0xAC,0x08,0x12, +0x00,0x60,0xAA,0x06,0xAB,0x07,0xC3,0xE4, +0x9B,0xFB,0xE4,0x9A,0xFA,0x78,0x17,0xF6, +0xAF,0x03,0xEF,0x08,0xF6,0x18,0xE6,0xF5, +0x8C,0x08,0xE6,0xF5,0x8A,0x74,0x0D,0x2B, +0xFB,0xE4,0x3A,0x18,0xF6,0xAF,0x03,0xEF, +0x08,0xF6,0x75,0x88,0x10,0x53,0x8E,0xC7, +0xD2,0xA9,0x22,0x7D,0x02,0x7C,0x00,0x7F, +0x4A,0x7E,0x13,0x12,0x06,0xE7,0x7D,0x46, +0x7C,0x71,0x7F,0x02,0x7E,0x66,0x12,0x06, +0xE7,0x7D,0x03,0x7C,0x00,0x7F,0x01,0x7E, +0x66,0x12,0x06,0xE7,0x7D,0xC0,0x7C,0x00, +0x7F,0x00,0x7E,0x66,0x12,0x06,0xE7,0xE4, +0xFF,0xFE,0x0F,0xBF,0x00,0x01,0x0E,0xEF, +0x64,0x64,0x4E,0x70,0xF5,0x7D,0x04,0x7C, +0x00,0x7F,0x02,0x7E,0x66,0x12,0x06,0xE7, +0x7D,0x00,0x7C,0x04,0x7F,0x01,0x7E,0x66, +0x12,0x06,0xE7,0x7D,0xC0,0x7C,0x00,0x7F, +0x00,0x7E,0x66,0x12,0x06,0xE7,0xE4,0xFD, +0xFC,0x7F,0x02,0x7E,0x66,0x12,0x06,0xE7, +0x7D,0x00,0x7C,0x04,0x7F,0x01,0x7E,0x66, +0x12,0x06,0xE7,0x7D,0xC0,0x7C,0x00,0x7F, +0x00,0x7E,0x66,0x12,0x06,0xE7,0xE4,0xFD, +0xFC,0x7F,0x4A,0x7E,0x13,0x12,0x06,0xE7, +0x7D,0x06,0x7C,0x71,0x7F,0x02,0x7E,0x66, +0x12,0x06,0xE7,0x7D,0x03,0x7C,0x00,0x7F, +0x01,0x7E,0x66,0x12,0x06,0xE7,0x7D,0xC0, +0x7C,0x00,0x7F,0x00,0x7E,0x66,0x02,0x06, +0xE7,0x78,0x7F,0xE4,0xF6,0xD8,0xFD,0x75, +0x81,0x3C,0x02,0x05,0xDE,0x02,0x03,0x2F, +0xE4,0x93,0xA3,0xF8,0xE4,0x93,0xA3,0x40, +0x03,0xF6,0x80,0x01,0xF2,0x08,0xDF,0xF4, +0x80,0x29,0xE4,0x93,0xA3,0xF8,0x54,0x07, +0x24,0x0C,0xC8,0xC3,0x33,0xC4,0x54,0x0F, +0x44,0x20,0xC8,0x83,0x40,0x04,0xF4,0x56, +0x80,0x01,0x46,0xF6,0xDF,0xE4,0x80,0x0B, +0x01,0x02,0x04,0x08,0x10,0x20,0x40,0x80, +0x90,0x07,0x23,0xE4,0x7E,0x01,0x93,0x60, +0xBC,0xA3,0xFF,0x54,0x3F,0x30,0xE5,0x09, +0x54,0x1F,0xFE,0xE4,0x93,0xA3,0x60,0x01, +0x0E,0xCF,0x54,0xC0,0x25,0xE0,0x60,0xA8, +0x40,0xB8,0xE4,0x93,0xA3,0xFA,0xE4,0x93, +0xA3,0xF8,0xE4,0x93,0xA3,0xC8,0xC5,0x82, +0xC8,0xCA,0xC5,0x83,0xCA,0xF0,0xA3,0xC8, +0xC5,0x82,0xC8,0xCA,0xC5,0x83,0xCA,0xDF, +0xE9,0xDE,0xE7,0x80,0xBE,0x7D,0xD7,0x7C, +0x24,0x7F,0x02,0x7E,0x66,0x12,0x06,0xE7, +0x7D,0x80,0x7C,0x04,0x7F,0x01,0x7E,0x66, +0x12,0x06,0xE7,0x7D,0xC0,0x7C,0x00,0x7F, +0x00,0x7E,0x66,0x12,0x06,0xE7,0x7D,0xC0, +0x7C,0x16,0x7F,0x11,0x7E,0x1D,0x12,0x06, +0xE7,0x7D,0xBB,0x7C,0x15,0x7F,0xEB,0x7E, +0x13,0x12,0x06,0xE7,0x7D,0x0D,0x7C,0x00, +0x7F,0xE7,0x7E,0x13,0x12,0x06,0xE7,0x7F, +0x41,0x7E,0x1D,0x12,0x06,0xC3,0xEF,0x44, +0x20,0x44,0x80,0xFD,0xAC,0x06,0x7F,0x41, +0x7E,0x1D,0x12,0x06,0xE7,0x7D,0x00,0x7C, +0x21,0x7F,0x00,0x7E,0x62,0x12,0x06,0xE7, +0x02,0x02,0x2F,0xC0,0xE0,0xC0,0xF0,0xC0, +0x83,0xC0,0x82,0xC0,0xD0,0x75,0xD0,0x00, +0xC0,0x00,0x78,0x17,0xE6,0xF5,0x8C,0x78, +0x18,0xE6,0xF5,0x8A,0x90,0x06,0x31,0xE4, +0x75,0xF0,0x01,0x12,0x00,0x0E,0x90,0x06, +0x33,0xE4,0x75,0xF0,0x01,0x12,0x00,0x0E, +0xD0,0x00,0xD0,0xD0,0xD0,0x82,0xD0,0x83, +0xD0,0xF0,0xD0,0xE0,0x32,0xC2,0xAF,0xAD, +0x07,0xAC,0x06,0x8C,0xA2,0x8D,0xA3,0x75, +0xA0,0x01,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0xAE,0xA1,0xBE, +0x00,0xF0,0xAE,0xA6,0xAF,0xA7,0xD2,0xAF, +0x22,0xC2,0xAF,0xAB,0x07,0xAA,0x06,0x8A, +0xA2,0x8B,0xA3,0x8C,0xA4,0x8D,0xA5,0x75, +0xA0,0x03,0x00,0x00,0x00,0xAA,0xA1,0xBA, +0x00,0xF8,0xD2,0xAF,0x22,0x7F,0x0C,0x7E, +0x13,0x12,0x06,0xC3,0xEF,0x44,0x50,0xFD, +0xAC,0x06,0x7F,0x0C,0x7E,0x13,0x02,0x06, +0xE7,0x12,0x07,0x03,0x12,0x07,0x2E,0x12, +0x04,0x2C,0x02,0x00,0x03,0x42,0x06,0x33, +0x00,0x00,0x42,0x06,0x31,0x00,0x00,0x00, +0xE4,0xF5,0x8E,0x22}; + + +#define SGMII_INIT_SIZE 1233 +rtk_uint8 Sgmii_Init[SGMII_INIT_SIZE] = { +0x02,0x03,0xB3,0xE4,0xF5,0xA8, +0xD2,0xAF,0x22,0x00,0x00,0x02,0x04,0x3F, +0xC5,0xF0,0xF8,0xA3,0xE0,0x28,0xF0,0xC5, +0xF0,0xF8,0xE5,0x82,0x15,0x82,0x70,0x02, +0x15,0x83,0xE0,0x38,0xF0,0x22,0x75,0xF0, +0x08,0x75,0x82,0x00,0xEF,0x2F,0xFF,0xEE, +0x33,0xFE,0xCD,0x33,0xCD,0xCC,0x33,0xCC, +0xC5,0x82,0x33,0xC5,0x82,0x9B,0xED,0x9A, +0xEC,0x99,0xE5,0x82,0x98,0x40,0x0C,0xF5, +0x82,0xEE,0x9B,0xFE,0xED,0x9A,0xFD,0xEC, +0x99,0xFC,0x0F,0xD5,0xF0,0xD6,0xE4,0xCE, +0xFB,0xE4,0xCD,0xFA,0xE4,0xCC,0xF9,0xA8, +0x82,0x22,0xB8,0x00,0xC1,0xB9,0x00,0x59, +0xBA,0x00,0x2D,0xEC,0x8B,0xF0,0x84,0xCF, +0xCE,0xCD,0xFC,0xE5,0xF0,0xCB,0xF9,0x78, +0x18,0xEF,0x2F,0xFF,0xEE,0x33,0xFE,0xED, +0x33,0xFD,0xEC,0x33,0xFC,0xEB,0x33,0xFB, +0x10,0xD7,0x03,0x99,0x40,0x04,0xEB,0x99, +0xFB,0x0F,0xD8,0xE5,0xE4,0xF9,0xFA,0x22, +0x78,0x18,0xEF,0x2F,0xFF,0xEE,0x33,0xFE, +0xED,0x33,0xFD,0xEC,0x33,0xFC,0xC9,0x33, +0xC9,0x10,0xD7,0x05,0x9B,0xE9,0x9A,0x40, +0x07,0xEC,0x9B,0xFC,0xE9,0x9A,0xF9,0x0F, +0xD8,0xE0,0xE4,0xC9,0xFA,0xE4,0xCC,0xFB, +0x22,0x75,0xF0,0x10,0xEF,0x2F,0xFF,0xEE, +0x33,0xFE,0xED,0x33,0xFD,0xCC,0x33,0xCC, +0xC8,0x33,0xC8,0x10,0xD7,0x07,0x9B,0xEC, +0x9A,0xE8,0x99,0x40,0x0A,0xED,0x9B,0xFD, +0xEC,0x9A,0xFC,0xE8,0x99,0xF8,0x0F,0xD5, +0xF0,0xDA,0xE4,0xCD,0xFB,0xE4,0xCC,0xFA, +0xE4,0xC8,0xF9,0x22,0xEB,0x9F,0xF5,0xF0, +0xEA,0x9E,0x42,0xF0,0xE9,0x9D,0x42,0xF0, +0xE8,0x9C,0x45,0xF0,0x22,0xE0,0xFC,0xA3, +0xE0,0xFD,0xA3,0xE0,0xFE,0xA3,0xE0,0xFF, +0x22,0xE0,0xF8,0xA3,0xE0,0xF9,0xA3,0xE0, +0xFA,0xA3,0xE0,0xFB,0x22,0xEC,0xF0,0xA3, +0xED,0xF0,0xA3,0xEE,0xF0,0xA3,0xEF,0xF0, +0x22,0xE4,0x90,0x06,0x28,0xF0,0xFD,0x7C, +0x01,0x7F,0x3F,0x7E,0x1D,0x12,0x04,0x9D, +0x7D,0x40,0x7C,0x00,0x7F,0x36,0x7E,0x13, +0x12,0x04,0x9D,0xE4,0xFF,0xFE,0xFD,0x80, +0x25,0xE4,0x7F,0xFF,0x7E,0xFF,0xFD,0xFC, +0x90,0x06,0x24,0x12,0x01,0x0F,0xC3,0x12, +0x00,0xF2,0x50,0x1B,0x90,0x06,0x24,0x12, +0x01,0x03,0xEF,0x24,0x01,0xFF,0xE4,0x3E, +0xFE,0xE4,0x3D,0xFD,0xE4,0x3C,0xFC,0x90, +0x06,0x24,0x12,0x01,0x1B,0x80,0xD2,0xE4, +0xF5,0xA8,0xD2,0xAF,0x7D,0x1F,0xFC,0x7F, +0x49,0x7E,0x13,0x12,0x04,0x9D,0x12,0x04, +0xC4,0x7D,0xFE,0x7C,0x00,0x7F,0xAA,0x7E, +0x12,0x12,0x04,0x9D,0x7D,0x41,0x7C,0x00, +0x7F,0x36,0x7E,0x13,0x12,0x04,0x9D,0xE4, +0xFF,0xFE,0xFD,0x80,0x25,0xE4,0x7F,0x20, +0x7E,0x4E,0xFD,0xFC,0x90,0x06,0x24,0x12, +0x01,0x0F,0xC3,0x12,0x00,0xF2,0x50,0x1B, +0x90,0x06,0x24,0x12,0x01,0x03,0xEF,0x24, +0x01,0xFF,0xE4,0x3E,0xFE,0xE4,0x3D,0xFD, +0xE4,0x3C,0xFC,0x90,0x06,0x24,0x12,0x01, +0x1B,0x80,0xD2,0xC2,0x00,0xC2,0x01,0xD2, +0xA9,0xD2,0x8C,0x7D,0x3D,0x7C,0x00,0x7F, +0x01,0x7E,0x66,0x12,0x04,0x9D,0x7D,0x80, +0x7C,0x00,0x7F,0x00,0x7E,0x66,0x12,0x04, +0x9D,0x7F,0x02,0x7E,0x66,0x12,0x04,0x79, +0x7F,0x02,0x7E,0x66,0x12,0x04,0x79,0xEF, +0x30,0xE4,0x07,0xE4,0x90,0x06,0x28,0xF0, +0x80,0xD1,0x90,0x06,0x28,0xE0,0x70,0x12, +0x12,0x03,0x03,0x90,0x06,0x28,0x74,0x01, +0xF0,0xE4,0x90,0x06,0x2B,0xF0,0xA3,0xF0, +0x80,0xB9,0xC3,0x90,0x06,0x2C,0xE0,0x94, +0x62,0x90,0x06,0x2B,0xE0,0x94,0x00,0x40, +0xAA,0xE4,0xF0,0xA3,0xF0,0x12,0x03,0x03, +0x90,0x06,0x28,0x74,0x01,0xF0,0x80,0x9B, +0x75,0x0F,0x80,0x75,0x0E,0x7E,0x75,0x0D, +0xAA,0x75,0x0C,0x83,0xE4,0xF5,0x10,0x7F, +0x36,0x7E,0x13,0x12,0x04,0x79,0xEE,0xC4, +0xF8,0x54,0xF0,0xC8,0xEF,0xC4,0x54,0x0F, +0x48,0x54,0x07,0xFB,0x7A,0x00,0xEA,0x70, +0x4A,0xEB,0x14,0x60,0x1C,0x14,0x60,0x27, +0x24,0xFE,0x60,0x31,0x14,0x60,0x3C,0x24, +0x05,0x70,0x38,0x75,0x0B,0x00,0x75,0x0A, +0xC2,0x75,0x09,0xEB,0x75,0x08,0x0B,0x80, +0x36,0x75,0x0B,0x40,0x75,0x0A,0x59,0x75, +0x09,0x73,0x75,0x08,0x07,0x80,0x28,0x75, +0x0B,0x00,0x75,0x0A,0xE1,0x75,0x09,0xF5, +0x75,0x08,0x05,0x80,0x1A,0x75,0x0B,0xA0, +0x75,0x0A,0xAC,0x75,0x09,0xB9,0x75,0x08, +0x03,0x80,0x0C,0x75,0x0B,0x00,0x75,0x0A, +0x62,0x75,0x09,0x3D,0x75,0x08,0x01,0x75, +0x89,0x11,0xE4,0x7B,0x60,0x7A,0x09,0xF9, +0xF8,0xAF,0x0B,0xAE,0x0A,0xAD,0x09,0xAC, +0x08,0x12,0x00,0x60,0xAA,0x06,0xAB,0x07, +0xC3,0xE4,0x9B,0xFB,0xE4,0x9A,0xFA,0x78, +0x17,0xF6,0xAF,0x03,0xEF,0x08,0xF6,0x18, +0xE6,0xF5,0x8C,0x08,0xE6,0xF5,0x8A,0x74, +0x0D,0x2B,0xFB,0xE4,0x3A,0x18,0xF6,0xAF, +0x03,0xEF,0x08,0xF6,0x75,0x88,0x10,0x53, +0x8E,0xC7,0xD2,0xA9,0x22,0x7D,0x26,0x7C, +0x02,0x7F,0xA1,0x7E,0x13,0x12,0x04,0x9D, +0x7D,0x02,0x7C,0x00,0x7F,0x4A,0x7E,0x13, +0x12,0x04,0x9D,0x7D,0x06,0x7C,0x71,0x7F, +0x02,0x7E,0x66,0x12,0x04,0x9D,0x7D,0x03, +0x7C,0x00,0x7F,0x01,0x7E,0x66,0x12,0x04, +0x9D,0x7D,0xC0,0x7C,0x00,0x7F,0x00,0x7E, +0x66,0x12,0x04,0x9D,0xE4,0xFF,0xFE,0x0F, +0xBF,0x00,0x01,0x0E,0xEF,0x64,0x64,0x4E, +0x70,0xF5,0x7D,0x01,0x7C,0x14,0x7F,0x02, +0x7E,0x66,0x12,0x04,0x9D,0xE4,0xFD,0xFC, +0x7F,0x01,0x7E,0x66,0x12,0x04,0x9D,0x7D, +0xC0,0x7C,0x00,0x7F,0x00,0x7E,0x66,0x12, +0x04,0x9D,0x7D,0x03,0x7C,0x14,0x7F,0x02, +0x7E,0x66,0x12,0x04,0x9D,0xE4,0xFD,0xFC, +0x7F,0x01,0x7E,0x66,0x12,0x04,0x9D,0x7D, +0xC0,0x7C,0x00,0x7F,0x00,0x7E,0x66,0x12, +0x04,0x9D,0xE4,0xFD,0xFC,0x7F,0x4A,0x7E, +0x13,0x12,0x04,0x9D,0x7D,0x06,0x7C,0x71, +0x7F,0x02,0x7E,0x66,0x12,0x04,0x9D,0x7D, +0x03,0x7C,0x00,0x7F,0x01,0x7E,0x66,0x12, +0x04,0x9D,0x7D,0xC0,0x7C,0x00,0x7F,0x00, +0x7E,0x66,0x02,0x04,0x9D,0x78,0x7F,0xE4, +0xF6,0xD8,0xFD,0x75,0x81,0x3C,0x02,0x03, +0xFA,0x02,0x01,0x27,0xE4,0x93,0xA3,0xF8, +0xE4,0x93,0xA3,0x40,0x03,0xF6,0x80,0x01, +0xF2,0x08,0xDF,0xF4,0x80,0x29,0xE4,0x93, +0xA3,0xF8,0x54,0x07,0x24,0x0C,0xC8,0xC3, +0x33,0xC4,0x54,0x0F,0x44,0x20,0xC8,0x83, +0x40,0x04,0xF4,0x56,0x80,0x01,0x46,0xF6, +0xDF,0xE4,0x80,0x0B,0x01,0x02,0x04,0x08, +0x10,0x20,0x40,0x80,0x90,0x04,0xB9,0xE4, +0x7E,0x01,0x93,0x60,0xBC,0xA3,0xFF,0x54, +0x3F,0x30,0xE5,0x09,0x54,0x1F,0xFE,0xE4, +0x93,0xA3,0x60,0x01,0x0E,0xCF,0x54,0xC0, +0x25,0xE0,0x60,0xA8,0x40,0xB8,0xE4,0x93, +0xA3,0xFA,0xE4,0x93,0xA3,0xF8,0xE4,0x93, +0xA3,0xC8,0xC5,0x82,0xC8,0xCA,0xC5,0x83, +0xCA,0xF0,0xA3,0xC8,0xC5,0x82,0xC8,0xCA, +0xC5,0x83,0xCA,0xDF,0xE9,0xDE,0xE7,0x80, +0xBE,0xC0,0xE0,0xC0,0xF0,0xC0,0x83,0xC0, +0x82,0xC0,0xD0,0x75,0xD0,0x00,0xC0,0x00, +0x78,0x17,0xE6,0xF5,0x8C,0x78,0x18,0xE6, +0xF5,0x8A,0x90,0x06,0x29,0xE4,0x75,0xF0, +0x01,0x12,0x00,0x0E,0x90,0x06,0x2B,0xE4, +0x75,0xF0,0x01,0x12,0x00,0x0E,0xD0,0x00, +0xD0,0xD0,0xD0,0x82,0xD0,0x83,0xD0,0xF0, +0xD0,0xE0,0x32,0xC2,0xAF,0xAD,0x07,0xAC, +0x06,0x8C,0xA2,0x8D,0xA3,0x75,0xA0,0x01, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0xAE,0xA1,0xBE,0x00,0xF0, +0xAE,0xA6,0xAF,0xA7,0xD2,0xAF,0x22,0xC2, +0xAF,0xAB,0x07,0xAA,0x06,0x8A,0xA2,0x8B, +0xA3,0x8C,0xA4,0x8D,0xA5,0x75,0xA0,0x03, +0x00,0x00,0x00,0xAA,0xA1,0xBA,0x00,0xF8, +0xD2,0xAF,0x22,0x42,0x06,0x2B,0x00,0x00, +0x42,0x06,0x29,0x00,0x00,0x00,0x12,0x04, +0xCD,0x12,0x02,0x3E,0x02,0x00,0x03,0xE4, +0xF5,0x8E,0x22}; + +#define FIBER1_2_INIT_SIZE 1332 +rtk_uint8 Fiber1_2_Init[FIBER1_2_INIT_SIZE] = { +0x02,0x05,0x28,0x90,0x00,0x0A,0xEE,0xF0, +0xA3,0xEF,0xF0,0xE4,0x7F,0x11,0x7E,0x62, +0x12,0x04,0xF7,0x7F,0x11,0x7E,0x62,0x12, +0x04,0xF7,0xEF,0x30,0xE2,0x03,0x02,0x01, +0xA8,0x90,0x00,0x0B,0xE0,0x04,0xF0,0x70, +0x06,0x90,0x00,0x0A,0xE0,0x04,0xF0,0x90, +0x00,0x0A,0xE0,0xFC,0xA3,0xE0,0xFD,0x7F, +0xA4,0x7E,0x0B,0x12,0x04,0xDB,0x7D,0x66, +0x7C,0x00,0x7F,0x11,0x7E,0x13,0x12,0x04, +0xDB,0x7D,0x66,0x7C,0x10,0x7F,0x11,0x7E, +0x13,0x12,0x04,0xDB,0x7F,0x9D,0x7E,0x1D, +0x12,0x04,0xF7,0xEE,0x30,0xE0,0xF5,0xE4, +0x90,0x00,0x0C,0xF0,0xA3,0xF0,0x90,0x00, +0x0D,0xE0,0x04,0xF0,0x70,0x06,0x90,0x00, +0x0C,0xE0,0x04,0xF0,0x90,0x00,0x0C,0xE0, +0xB4,0x0B,0xEB,0xA3,0xE0,0xB4,0xB8,0xE6, +0x7D,0x02,0x7C,0x00,0x7F,0x3D,0x7E,0x13, +0x12,0x04,0xDB,0xE4,0x90,0x00,0x0C,0xF0, +0xA3,0xF0,0x90,0x00,0x0D,0xE0,0x04,0xF0, +0x70,0x06,0x90,0x00,0x0C,0xE0,0x04,0xF0, +0x90,0x00,0x0C,0xE0,0xB4,0x0B,0xEB,0xA3, +0xE0,0xB4,0xB8,0xE6,0x90,0x00,0x14,0x74, +0x14,0xF0,0xA3,0xE4,0xF0,0xFB,0xFA,0xFD, +0xFC,0x7F,0x01,0xFE,0x12,0x04,0x2D,0xE4, +0x90,0x00,0x0C,0xF0,0xA3,0xF0,0x90,0x00, +0x0C,0xE0,0xFE,0xA3,0xE0,0xFF,0xE4,0xFC, +0xFD,0x7B,0x60,0x7A,0xEA,0xF9,0xF8,0xD3, +0x12,0x05,0x12,0x40,0x10,0x90,0x00,0x0D, +0xE0,0x04,0xF0,0x70,0x06,0x90,0x00,0x0C, +0xE0,0x04,0xF0,0x80,0xD9,0xE4,0x90,0x00, +0x0C,0xF0,0xA3,0xF0,0x90,0x00,0x0C,0xE0, +0xFE,0xA3,0xE0,0xFF,0xE4,0xFC,0xFD,0x7B, +0x60,0x7A,0xEA,0xF9,0xF8,0xD3,0x12,0x05, +0x12,0x40,0x10,0x90,0x00,0x0D,0xE0,0x04, +0xF0,0x70,0x06,0x90,0x00,0x0C,0xE0,0x04, +0xF0,0x80,0xD9,0x90,0x00,0x14,0x74,0x14, +0xF0,0xA3,0x74,0x03,0xF0,0xE4,0xFB,0xFA, +0xFD,0xFC,0x7F,0x01,0xFE,0x12,0x04,0x2D, +0xE4,0x90,0x00,0x0C,0xF0,0xA3,0xF0,0x90, +0x00,0x0D,0xE0,0x04,0xF0,0x70,0x06,0x90, +0x00,0x0C,0xE0,0x04,0xF0,0x90,0x00,0x0C, +0xE0,0xB4,0x75,0xEB,0xA3,0xE0,0xB4,0x30, +0xE6,0xE4,0x90,0x00,0x0C,0xF0,0xA3,0xF0, +0x90,0x00,0x0D,0xE0,0x04,0xF0,0x70,0x06, +0x90,0x00,0x0C,0xE0,0x04,0xF0,0x90,0x00, +0x0C,0xE0,0xB4,0x75,0xEB,0xA3,0xE0,0xB4, +0x30,0xE6,0xE4,0xFD,0xFC,0x7F,0x3D,0x7E, +0x13,0x12,0x04,0xDB,0xE4,0x90,0x00,0x0C, +0xF0,0xA3,0xF0,0x90,0x00,0x0D,0xE0,0x04, +0xF0,0x70,0x06,0x90,0x00,0x0C,0xE0,0x04, +0xF0,0x90,0x00,0x0C,0xE0,0xB4,0x0B,0xEB, +0xA3,0xE0,0xB4,0xB8,0xE6,0x7D,0x66,0x7C, +0x00,0x7F,0x11,0x7E,0x13,0x12,0x04,0xDB, +0x22,0x90,0x00,0x0A,0xEE,0xF0,0xA3,0xEF, +0xF0,0xE4,0xFF,0x0F,0x7E,0x62,0x12,0x04, +0xF7,0x7F,0x01,0x7E,0x62,0x12,0x04,0xF7, +0xEF,0x30,0xE2,0x03,0x02,0x03,0x4C,0x90, +0x00,0x0B,0xE0,0x04,0xF0,0x70,0x06,0x90, +0x00,0x0A,0xE0,0x04,0xF0,0x90,0x00,0x0A, +0xE0,0xFC,0xA3,0xE0,0xFD,0x7F,0xA3,0x7E, +0x0B,0x12,0x04,0xDB,0x7D,0x66,0x7C,0x00, +0x7F,0xC4,0x7E,0x13,0x12,0x04,0xDB,0x7D, +0x66,0x7C,0x10,0x7F,0xC4,0x7E,0x13,0x12, +0x04,0xDB,0x7F,0x9D,0x7E,0x1D,0x12,0x04, +0xF7,0xEE,0x30,0xE1,0xF5,0xE4,0x90,0x00, +0x0C,0xF0,0xA3,0xF0,0x90,0x00,0x0D,0xE0, +0x04,0xF0,0x70,0x06,0x90,0x00,0x0C,0xE0, +0x04,0xF0,0x90,0x00,0x0C,0xE0,0xB4,0x0B, +0xEB,0xA3,0xE0,0xB4,0xB8,0xE6,0x7D,0x02, +0x7C,0x00,0x7F,0x3D,0x7E,0x13,0x12,0x04, +0xDB,0xE4,0x90,0x00,0x0C,0xF0,0xA3,0xF0, +0x90,0x00,0x0D,0xE0,0x04,0xF0,0x70,0x06, +0x90,0x00,0x0C,0xE0,0x04,0xF0,0x90,0x00, +0x0C,0xE0,0xB4,0x0B,0xEB,0xA3,0xE0,0xB4, +0xB8,0xE6,0x90,0x00,0x14,0x74,0x14,0xF0, +0xA3,0xE4,0xF0,0xFB,0xFA,0xFD,0xFC,0xFF, +0xFE,0x12,0x04,0x2D,0xE4,0x90,0x00,0x0C, +0xF0,0xA3,0xF0,0x90,0x00,0x0C,0xE0,0xFE, +0xA3,0xE0,0xFF,0xE4,0xFC,0xFD,0x7B,0x60, +0x7A,0xEA,0xF9,0xF8,0xD3,0x12,0x05,0x12, +0x40,0x10,0x90,0x00,0x0D,0xE0,0x04,0xF0, +0x70,0x06,0x90,0x00,0x0C,0xE0,0x04,0xF0, +0x80,0xD9,0xE4,0x90,0x00,0x0C,0xF0,0xA3, +0xF0,0x90,0x00,0x0C,0xE0,0xFE,0xA3,0xE0, +0xFF,0xE4,0xFC,0xFD,0x7B,0x60,0x7A,0xEA, +0xF9,0xF8,0xD3,0x12,0x05,0x12,0x40,0x10, +0x90,0x00,0x0D,0xE0,0x04,0xF0,0x70,0x06, +0x90,0x00,0x0C,0xE0,0x04,0xF0,0x80,0xD9, +0x90,0x00,0x14,0x74,0x14,0xF0,0xA3,0x74, +0x03,0xF0,0xE4,0xFB,0xFA,0xFD,0xFC,0xFF, +0xFE,0x12,0x04,0x2D,0xE4,0x90,0x00,0x0C, +0xF0,0xA3,0xF0,0x90,0x00,0x0D,0xE0,0x04, +0xF0,0x70,0x06,0x90,0x00,0x0C,0xE0,0x04, +0xF0,0x90,0x00,0x0C,0xE0,0xB4,0x75,0xEB, +0xA3,0xE0,0xB4,0x30,0xE6,0xE4,0x90,0x00, +0x0C,0xF0,0xA3,0xF0,0x90,0x00,0x0D,0xE0, +0x04,0xF0,0x70,0x06,0x90,0x00,0x0C,0xE0, +0x04,0xF0,0x90,0x00,0x0C,0xE0,0xB4,0x75, +0xEB,0xA3,0xE0,0xB4,0x30,0xE6,0xE4,0xFD, +0xFC,0x7F,0x3D,0x7E,0x13,0x12,0x04,0xDB, +0xE4,0x90,0x00,0x0C,0xF0,0xA3,0xF0,0x90, +0x00,0x0D,0xE0,0x04,0xF0,0x70,0x06,0x90, +0x00,0x0C,0xE0,0x04,0xF0,0x90,0x00,0x0C, +0xE0,0xB4,0x0B,0xEB,0xA3,0xE0,0xB4,0xB8, +0xE6,0x7D,0x66,0x7C,0x00,0x7F,0xC4,0x7E, +0x13,0x12,0x04,0xDB,0x22,0xE4,0x90,0x00, +0x00,0xF0,0xA3,0xF0,0xA3,0xF0,0xA3,0xF0, +0xA3,0xF0,0xA3,0xF0,0xA3,0xF0,0xA3,0xF0, +0x7D,0x51,0xFC,0x7F,0x36,0x7E,0x13,0x12, +0x04,0xDB,0xE4,0x90,0x00,0x08,0xF0,0xA3, +0xF0,0x90,0x00,0x09,0xE0,0x04,0xF0,0x70, +0x06,0x90,0x00,0x08,0xE0,0x04,0xF0,0x90, +0x00,0x08,0xE0,0x70,0x04,0xA3,0xE0,0x64, +0x64,0x70,0xE6,0xE4,0x90,0x00,0x08,0xF0, +0xA3,0xF0,0xE4,0xFF,0xFE,0x0F,0xBF,0x00, +0x01,0x0E,0xEF,0x64,0x32,0x4E,0x70,0xF5, +0x90,0x00,0x09,0xE0,0x04,0xF0,0x70,0x06, +0x90,0x00,0x08,0xE0,0x04,0xF0,0x90,0x00, +0x08,0xE0,0xB4,0x75,0xDD,0xA3,0xE0,0xB4, +0x30,0xD8,0x7F,0x59,0x7E,0x1B,0x12,0x04, +0xF7,0xEF,0x4E,0x70,0xC6,0x7F,0x92,0x7E, +0x1D,0x12,0x04,0xF7,0x90,0x00,0x06,0xEE, +0xF0,0xA3,0xEF,0xF0,0x64,0x07,0x60,0x0A, +0xEF,0x64,0x05,0x60,0x05,0xEF,0x64,0x04, +0x70,0x19,0x90,0x00,0x01,0xE0,0x04,0xF0, +0x70,0x06,0x90,0x00,0x00,0xE0,0x04,0xF0, +0x90,0x00,0x00,0xE0,0xFE,0xA3,0xE0,0xFF, +0x12,0x01,0xA9,0x90,0x00,0x06,0xE0,0xFF, +0x64,0x07,0x60,0x0D,0xEF,0x64,0x05,0x60, +0x08,0xEF,0x64,0x04,0x60,0x03,0x02,0x03, +0x8B,0x90,0x00,0x03,0xE0,0x04,0xF0,0x70, +0x06,0x90,0x00,0x02,0xE0,0x04,0xF0,0x90, +0x00,0x02,0xE0,0xFE,0xA3,0xE0,0xFF,0x12, +0x00,0x03,0x02,0x03,0x8B,0x90,0x00,0x0E, +0xEE,0xF0,0xA3,0xEF,0xF0,0xE4,0x90,0x00, +0x16,0xF0,0xA3,0xF0,0xA3,0xF0,0xA3,0xF0, +0xAE,0x02,0xEB,0x78,0x05,0xC3,0x33,0xCE, +0x33,0xCE,0xD8,0xF9,0xFF,0xEE,0x4C,0xFE, +0xEF,0x4D,0xFF,0x90,0x00,0x16,0xEE,0xF0, +0xA3,0xEF,0xF0,0x90,0x00,0x0E,0xE0,0xFF, +0xA3,0xE0,0x44,0xC0,0x90,0x00,0x18,0xCF, +0xF0,0xA3,0xEF,0xF0,0x90,0x00,0x14,0xE0, +0xFC,0xA3,0xE0,0xFD,0x7F,0x02,0x7E,0x66, +0x12,0x04,0xDB,0x90,0x00,0x16,0xE0,0xFC, +0xA3,0xE0,0xFD,0x7F,0x01,0x7E,0x66,0x12, +0x04,0xDB,0x90,0x00,0x18,0xE0,0xFC,0xA3, +0xE0,0xFD,0x7F,0x00,0x7E,0x66,0x12,0x04, +0xDB,0x90,0x00,0x1A,0xE4,0xF0,0xA3,0x74, +0x64,0xF0,0x90,0x00,0x1A,0xE0,0x70,0x02, +0xA3,0xE0,0x60,0x2C,0x7F,0x00,0x7E,0x66, +0x12,0x04,0xF7,0xEE,0x30,0xE0,0x18,0x90, +0x00,0x1B,0xE0,0x24,0xFF,0xF0,0x90,0x00, +0x1A,0xE0,0x34,0xFF,0xF0,0xE0,0x70,0x02, +0xA3,0xE0,0x70,0xD6,0x7F,0xFF,0x22,0xE4, +0x90,0x00,0x1A,0xF0,0xA3,0xF0,0x80,0xCA, +0x7F,0x00,0x22,0xAB,0x07,0xAA,0x06,0x8A, +0xA2,0x00,0x8B,0xA3,0x00,0x8C,0xA4,0x00, +0x8D,0xA5,0x00,0x75,0xA0,0x03,0x00,0x00, +0xAA,0xA1,0x00,0xBA,0x00,0xF9,0x22,0xAD, +0x07,0xAC,0x06,0x8C,0xA2,0x00,0x8D,0xA3, +0x00,0x75,0xA0,0x01,0x00,0xAE,0xA1,0x00, +0xBE,0x00,0xF9,0x00,0xAE,0xA6,0x00,0xAF, +0xA7,0x22,0xEB,0x9F,0xF5,0xF0,0xEA,0x9E, +0x42,0xF0,0xE9,0x9D,0x42,0xF0,0xEC,0x64, +0x80,0xC8,0x64,0x80,0x98,0x45,0xF0,0x22, +0x78,0x7F,0xE4,0xF6,0xD8,0xFD,0x75,0x81, +0x09,0x02,0x03,0x4D,}; + + +/* Function Name: + * rtl8367c_setAsicPortUnknownDaBehavior + * Description: + * Set UNDA behavior + * Input: + * port - port ID + * behavior - 0: flooding to unknwon DA portmask; 1: drop; 2:trap; 3: flooding + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid behavior + * Note: + * None + */ +ret_t rtl8367c_setAsicPortUnknownDaBehavior(rtk_uint32 port, rtk_uint32 behavior) +{ + if(port >= RTL8367C_PORTNO) + return RT_ERR_PORT_ID; + + if(behavior >= L2_UNDA_BEHAVE_END) + return RT_ERR_NOT_ALLOWED; + + if(port < 8) + return rtl8367c_setAsicRegBits(RTL8367C_REG_UNKNOWN_UNICAST_DA_PORT_BEHAVE, RTL8367C_Port0_ACTION_MASK << (port * 2), behavior); + else + return rtl8367c_setAsicRegBits(RTL8367C_REG_UNKNOWN_UNICAST_DA_PORT_BEHAVE_EXT, RTL8367C_PORT8_ACTION_MASK << ((port-8) * 2), behavior); +} +/* Function Name: + * rtl8367c_getAsicPortUnknownDaBehavior + * Description: + * Get UNDA behavior + * Input: + * port - port ID + * Output: + * pBehavior - 0: flooding to unknwon DA portmask; 1: drop; 2:trap; 3: flooding + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicPortUnknownDaBehavior(rtk_uint32 port, rtk_uint32 *pBehavior) +{ + if(port >= RTL8367C_PORTNO) + return RT_ERR_PORT_ID; + + if(port < 8) + return rtl8367c_getAsicRegBits(RTL8367C_REG_UNKNOWN_UNICAST_DA_PORT_BEHAVE, RTL8367C_Port0_ACTION_MASK << (port * 2), pBehavior); + else + return rtl8367c_getAsicRegBits(RTL8367C_REG_UNKNOWN_UNICAST_DA_PORT_BEHAVE_EXT, RTL8367C_PORT8_ACTION_MASK << ((port-8) * 2), pBehavior); +} +/* Function Name: + * rtl8367c_setAsicPortUnknownSaBehavior + * Description: + * Set UNSA behavior + * Input: + * behavior - 0: flooding; 1: drop; 2:trap + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid behavior + * Note: + * None + */ +ret_t rtl8367c_setAsicPortUnknownSaBehavior(rtk_uint32 behavior) +{ + if(behavior >= L2_BEHAVE_SA_END) + return RT_ERR_NOT_ALLOWED; + + return rtl8367c_setAsicRegBits(RTL8367C_PORT_SECURIT_CTRL_REG, RTL8367C_UNKNOWN_SA_BEHAVE_MASK, behavior); +} +/* Function Name: + * rtl8367c_getAsicPortUnknownSaBehavior + * Description: + * Get UNSA behavior + * Input: + * pBehavior - 0: flooding; 1: drop; 2:trap + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicPortUnknownSaBehavior(rtk_uint32 *pBehavior) +{ + return rtl8367c_getAsicRegBits(RTL8367C_PORT_SECURIT_CTRL_REG, RTL8367C_UNKNOWN_SA_BEHAVE_MASK, pBehavior); +} +/* Function Name: + * rtl8367c_setAsicPortUnmatchedSaBehavior + * Description: + * Set Unmatched SA behavior + * Input: + * behavior - 0: flooding; 1: drop; 2:trap + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid behavior + * Note: + * None + */ +ret_t rtl8367c_setAsicPortUnmatchedSaBehavior(rtk_uint32 behavior) +{ + if(behavior >= L2_BEHAVE_SA_END) + return RT_ERR_NOT_ALLOWED; + + return rtl8367c_setAsicRegBits(RTL8367C_PORT_SECURIT_CTRL_REG, RTL8367C_UNMATCHED_SA_BEHAVE_MASK, behavior); +} +/* Function Name: + * rtl8367c_getAsicPortUnmatchedSaBehavior + * Description: + * Get Unmatched SA behavior + * Input: + * pBehavior - 0: flooding; 1: drop; 2:trap + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicPortUnmatchedSaBehavior(rtk_uint32 *pBehavior) +{ + return rtl8367c_getAsicRegBits(RTL8367C_PORT_SECURIT_CTRL_REG, RTL8367C_UNMATCHED_SA_BEHAVE_MASK, pBehavior); +} + +/* Function Name: + * rtl8367c_setAsicPortUnmatchedSaMoving + * Description: + * Set Unmatched SA moving state + * Input: + * port - Port ID + * enabled - 0: can't move to new port; 1: can move to new port + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Error Port ID + * Note: + * None + */ +ret_t rtl8367c_setAsicPortUnmatchedSaMoving(rtk_uint32 port, rtk_uint32 enabled) +{ + if(port >= RTL8367C_PORTNO) + return RT_ERR_PORT_ID; + + return rtl8367c_setAsicRegBit(RTL8367C_REG_L2_SA_MOVING_FORBID, port, (enabled == 1) ? 0 : 1); +} + +/* Function Name: + * rtl8367c_getAsicPortUnmatchedSaMoving + * Description: + * Get Unmatched SA moving state + * Input: + * port - Port ID + * Output: + * pEnabled - 0: can't move to new port; 1: can move to new port + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Error Port ID + * Note: + * None + */ +ret_t rtl8367c_getAsicPortUnmatchedSaMoving(rtk_uint32 port, rtk_uint32 *pEnabled) +{ + rtk_uint32 data; + ret_t retVal; + + if(port >= RTL8367C_PORTNO) + return RT_ERR_PORT_ID; + + if((retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_L2_SA_MOVING_FORBID, port, &data)) != RT_ERR_OK) + return retVal; + + *pEnabled = (data == 1) ? 0 : 1; + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_setAsicPortUnknownDaFloodingPortmask + * Description: + * Set UNDA flooding portmask + * Input: + * portmask - portmask(0~0xFF) + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Invalid portmask + * Note: + * None + */ +ret_t rtl8367c_setAsicPortUnknownDaFloodingPortmask(rtk_uint32 portmask) +{ + if(portmask > RTL8367C_PORTMASK) + return RT_ERR_PORT_MASK; + + return rtl8367c_setAsicReg(RTL8367C_UNUCAST_FLOADING_PMSK_REG, portmask); +} +/* Function Name: + * rtl8367c_getAsicPortUnknownDaFloodingPortmask + * Description: + * Get UNDA flooding portmask + * Input: + * pPortmask - portmask(0~0xFF) + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicPortUnknownDaFloodingPortmask(rtk_uint32 *pPortmask) +{ + return rtl8367c_getAsicReg(RTL8367C_UNUCAST_FLOADING_PMSK_REG, pPortmask); +} +/* Function Name: + * rtl8367c_setAsicPortUnknownMulticastFloodingPortmask + * Description: + * Set UNMC flooding portmask + * Input: + * portmask - portmask(0~0xFF) + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Invalid portmask + * Note: + * None + */ +ret_t rtl8367c_setAsicPortUnknownMulticastFloodingPortmask(rtk_uint32 portmask) +{ + if(portmask > RTL8367C_PORTMASK) + return RT_ERR_PORT_MASK; + + return rtl8367c_setAsicReg(RTL8367C_UNMCAST_FLOADING_PMSK_REG, portmask); +} +/* Function Name: + * rtl8367c_getAsicPortUnknownMulticastFloodingPortmask + * Description: + * Get UNMC flooding portmask + * Input: + * pPortmask - portmask(0~0xFF) + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicPortUnknownMulticastFloodingPortmask(rtk_uint32 *pPortmask) +{ + return rtl8367c_getAsicReg(RTL8367C_UNMCAST_FLOADING_PMSK_REG, pPortmask); +} +/* Function Name: + * rtl8367c_setAsicPortBcastFloodingPortmask + * Description: + * Set Bcast flooding portmask + * Input: + * portmask - portmask(0~0xFF) + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Invalid portmask + * Note: + * None + */ +ret_t rtl8367c_setAsicPortBcastFloodingPortmask(rtk_uint32 portmask) +{ + if(portmask > RTL8367C_PORTMASK) + return RT_ERR_PORT_MASK; + + return rtl8367c_setAsicReg(RTL8367C_BCAST_FLOADING_PMSK_REG, portmask); +} +/* Function Name: + * rtl8367c_getAsicPortBcastFloodingPortmask + * Description: + * Get Bcast flooding portmask + * Input: + * pPortmask - portmask(0~0xFF) + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicPortBcastFloodingPortmask(rtk_uint32 *pPortmask) +{ + return rtl8367c_getAsicReg(RTL8367C_BCAST_FLOADING_PMSK_REG, pPortmask); +} +/* Function Name: + * rtl8367c_setAsicPortBlockSpa + * Description: + * Set disabling blocking frame if source port and destination port are the same + * Input: + * port - Physical port number (0~7) + * permit - 0: block; 1: permit + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_setAsicPortBlockSpa(rtk_uint32 port, rtk_uint32 permit) +{ + if(port >= RTL8367C_PORTNO) + return RT_ERR_PORT_ID; + + return rtl8367c_setAsicRegBit(RTL8367C_SOURCE_PORT_BLOCK_REG, port, permit); +} +/* Function Name: + * rtl8367c_getAsicPortBlockSpa + * Description: + * Get disabling blocking frame if source port and destination port are the same + * Input: + * port - Physical port number (0~7) + * pPermit - 0: block; 1: permit + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_getAsicPortBlockSpa(rtk_uint32 port, rtk_uint32* pPermit) +{ + if(port >= RTL8367C_PORTNO) + return RT_ERR_PORT_ID; + + return rtl8367c_getAsicRegBit(RTL8367C_SOURCE_PORT_BLOCK_REG, port, pPermit); +} + +/* Function Name: + * rtl8367c_setAsicPortForceLink + * Description: + * Set port force linking configuration + * Input: + * port - Physical port number (0~7) + * pPortAbility - port ability configuration + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_setAsicPortForceLink(rtk_uint32 port, rtl8367c_port_ability_t *pPortAbility) +{ + rtk_uint32 regData = 0; + + /* Invalid input parameter */ + if(port >= RTL8367C_PORTNO) + return RT_ERR_PORT_ID; + + regData |= pPortAbility->forcemode << 12; + regData |= pPortAbility->mstfault << 9; + regData |= pPortAbility->mstmode << 8; + regData |= pPortAbility->nway << 7; + regData |= pPortAbility->txpause << 6; + regData |= pPortAbility->rxpause << 5; + regData |= pPortAbility->link << 4; + regData |= pPortAbility->duplex << 2; + regData |= pPortAbility->speed; + + return rtl8367c_setAsicReg(RTL8367C_REG_MAC0_FORCE_SELECT+port, regData); +} +/* Function Name: + * rtl8367c_getAsicPortForceLink + * Description: + * Get port force linking configuration + * Input: + * port - Physical port number (0~7) + * pPortAbility - port ability configuration + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_getAsicPortForceLink(rtk_uint32 port, rtl8367c_port_ability_t *pPortAbility) +{ + ret_t retVal; + rtk_uint32 regData; + + /* Invalid input parameter */ + if(port >= RTL8367C_PORTNO) + return RT_ERR_PORT_ID; + + retVal = rtl8367c_getAsicReg(RTL8367C_REG_MAC0_FORCE_SELECT + port, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + pPortAbility->forcemode = (regData >> 12) & 0x0001; + pPortAbility->mstfault = (regData >> 9) & 0x0001; + pPortAbility->mstmode = (regData >> 8) & 0x0001; + pPortAbility->nway = (regData >> 7) & 0x0001; + pPortAbility->txpause = (regData >> 6) & 0x0001; + pPortAbility->rxpause = (regData >> 5) & 0x0001; + pPortAbility->link = (regData >> 4) & 0x0001; + pPortAbility->duplex = (regData >> 2) & 0x0001; + pPortAbility->speed = regData & 0x0003; + + return RT_ERR_OK; +} +/* Function Name: + * rtl8367c_getAsicPortStatus + * Description: + * Get port link status + * Input: + * port - Physical port number (0~7) + * pPortAbility - port ability configuration + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_getAsicPortStatus(rtk_uint32 port, rtl8367c_port_status_t *pPortStatus) +{ + ret_t retVal; + rtk_uint32 regData; + + /* Invalid input parameter */ + if(port >= RTL8367C_PORTNO) + return RT_ERR_PORT_ID; + + retVal = rtl8367c_getAsicReg(RTL8367C_REG_PORT0_STATUS+port,®Data); + if(retVal != RT_ERR_OK) + return retVal; + + pPortStatus->lpi1000 = (regData >> 11) & 0x0001; + pPortStatus->lpi100 = (regData >> 10) & 0x0001; + pPortStatus->mstfault = (regData >> 9) & 0x0001; + pPortStatus->mstmode = (regData >> 8) & 0x0001; + pPortStatus->nway = (regData >> 7) & 0x0001; + pPortStatus->txpause = (regData >> 6) & 0x0001; + pPortStatus->rxpause = (regData >> 5) & 0x0001; + pPortStatus->link = (regData >> 4) & 0x0001; + pPortStatus->duplex = (regData >> 2) & 0x0001; + pPortStatus->speed = regData & 0x0003; + + return RT_ERR_OK; +} +/* Function Name: + * rtl8367c_setAsicPortForceLinkExt + * Description: + * Set external interface force linking configuration + * Input: + * id - external interface id (0~2) + * portAbility - port ability configuration + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - input parameter out of range + * Note: + * None + */ +ret_t rtl8367c_setAsicPortForceLinkExt(rtk_uint32 id, rtl8367c_port_ability_t *pPortAbility) +{ + rtk_uint32 retVal, regValue, regValue2, type, sgmiibit, hisgmiibit; + rtk_uint32 reg_data = 0; + rtk_uint32 i = 0; + + /* Invalid input parameter */ + if(id >= RTL8367C_EXTNO) + return RT_ERR_OUT_OF_RANGE; + + reg_data |= pPortAbility->forcemode << 12; + reg_data |= pPortAbility->mstfault << 9; + reg_data |= pPortAbility->mstmode << 8; + reg_data |= pPortAbility->nway << 7; + reg_data |= pPortAbility->txpause << 6; + reg_data |= pPortAbility->rxpause << 5; + reg_data |= pPortAbility->link << 4; + reg_data |= pPortAbility->duplex << 2; + reg_data |= pPortAbility->speed; + + if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0249)) != RT_ERR_OK) + return retVal; + /*get chip ID */ + if((retVal = rtl8367c_getAsicReg(0x1300, ®Value)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0000)) != RT_ERR_OK) + return retVal; + + type = 0; + + switch (regValue) + { + case 0x0276: + case 0x0597: + case 0x6367: + type = 1; + break; + case 0x0652: + case 0x6368: + type = 2; + break; + case 0x0801: + case 0x6511: + type = 3; + break; + default: + return RT_ERR_FAILED; + } + + if (1 == type) + { + if(1 == id) + { + if ((retVal = rtl8367c_getAsicReg(RTL8367C_REG_REG_TO_ECO4, ®Value)) != RT_ERR_OK) + return retVal; + + if((regValue & (0x0001 << 5)) && (regValue & (0x0001 << 7))) + { + return RT_ERR_OK; + } + + if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_SGMII_FDUP_OFFSET, pPortAbility->duplex)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_SGMII_SPD_MASK, pPortAbility->speed)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_SGMII_LINK_OFFSET, pPortAbility->link)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_SGMII_TXFC_OFFSET, pPortAbility->txpause)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_SGMII_RXFC_OFFSET, pPortAbility->rxpause)) != RT_ERR_OK) + return retVal; + } + + if(0 == id || 1 == id) + return rtl8367c_setAsicReg(RTL8367C_REG_DIGITAL_INTERFACE0_FORCE + id, reg_data); + else + return rtl8367c_setAsicReg(RTL8367C_REG_DIGITAL_INTERFACE2_FORCE, reg_data); + } + else if (2 == type) + { + if (1 == id) + { + if((retVal = rtl8367c_setAsicRegBit(0x1311, 2, pPortAbility->duplex)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicRegBits(0x1311, 0x3, pPortAbility->speed)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicRegBit(0x1311, 4, pPortAbility->link)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicRegBit(0x1311, 6, pPortAbility->txpause)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicRegBit(0x1311, 5, pPortAbility->rxpause)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicRegBit(0x1311, 12, pPortAbility->forcemode)) != RT_ERR_OK) + return retVal; + + if (pPortAbility->link == 1) + { + if((retVal = rtl8367c_setAsicRegBit(0x1311, 4, 0)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicRegBit(0x1311, 4, 1)) != RT_ERR_OK) + return retVal; + } + else + { + if((retVal = rtl8367c_setAsicRegBits(0x1311, 0x3, 2)) != RT_ERR_OK) + return retVal; + } + + + if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_SGMII_FDUP_OFFSET, pPortAbility->duplex)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_SGMII_SPD_MASK, pPortAbility->speed)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_SGMII_LINK_OFFSET, pPortAbility->link)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_SGMII_TXFC_OFFSET, pPortAbility->txpause)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_SGMII_RXFC_OFFSET, pPortAbility->rxpause)) != RT_ERR_OK) + return retVal; + } + else if (2 == id) + { + if((retVal = rtl8367c_setAsicRegBit(0x13c4, 2, pPortAbility->duplex)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicRegBits(0x13c4, 0x3, pPortAbility->speed)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicRegBit(0x13c4, 4, pPortAbility->link)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicRegBit(0x13c4, 6, pPortAbility->txpause)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicRegBit(0x13c4, 5, pPortAbility->rxpause)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicRegBit(0x13c4, 12, pPortAbility->forcemode)) != RT_ERR_OK) + return retVal; + + if (pPortAbility->link == 1) + { + if((retVal = rtl8367c_setAsicRegBit(0x13c4, 4, 0)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicRegBit(0x13c4, 4, 1)) != RT_ERR_OK) + return retVal; + } + else + { + if((retVal = rtl8367c_setAsicRegBits(0x13c4, 0x3, 2)) != RT_ERR_OK) + return retVal; + } + + if((retVal = rtl8367c_setAsicRegBit(0x1dc1, RTL8367C_CFG_SGMII_FDUP_OFFSET, pPortAbility->duplex)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicRegBits(0x1dc1, RTL8367C_CFG_SGMII_SPD_MASK, pPortAbility->speed)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicRegBit(0x1dc1, RTL8367C_CFG_SGMII_LINK_OFFSET, pPortAbility->link)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicRegBit(0x1dc1, RTL8367C_CFG_SGMII_TXFC_OFFSET, pPortAbility->txpause)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicRegBit(0x1dc1, RTL8367C_CFG_SGMII_RXFC_OFFSET, pPortAbility->rxpause)) != RT_ERR_OK) + return retVal; + } + + } + else if(3 == type) + { + if(1 == id) + { + if((retVal = rtl8367c_getAsicRegBit(0x1d11, 6, &sgmiibit)) != RT_ERR_OK) + return retVal; + if((retVal = rtl8367c_getAsicRegBit(0x1d11, 11, &hisgmiibit)) != RT_ERR_OK) + return retVal; + + if ((sgmiibit == 1) || (hisgmiibit == 1)) + { + /*for 1000x/100fx/1000x_100fx, param has to be set to serdes registers*/ + if((retVal = rtl8367c_getAsicReg(0x1d41, ®Value)) != RT_ERR_OK) + return retVal; + + + if((regValue & 0xa0) == 0xa0) + { + + if((retVal = rtl8367c_getAsicRegBits(0x1d95, 0x1f00, ®Value2)) != RT_ERR_OK) + return retVal; + + /*1000X*/ + if(regValue2 == 0x4) + { +#if 0 + /* new_cfg_sds_mode:reset mode */ + if((retVal = rtl8367c_setAsicRegBits(0x1d95, 0x1f00, 0x1f)) != RT_ERR_OK) + return retVal; +#endif + /* Enable new sds mode config */ + if((retVal = rtl8367c_setAsicRegBit(0x1d95, 13, 1)) != RT_ERR_OK) + return retVal; + + /* 0 4 0 bit 12 set 1, bit15~13 = 4*/ + if((retVal = rtl8367c_getAsicSdsReg(0, 4, 0, ®_data)) != RT_ERR_OK) + return retVal; + reg_data &= 0xFFFF0FFF; + reg_data |= 0x9000; + if((retVal = rtl8367c_setAsicSdsReg(0,4,0, reg_data)) != RT_ERR_OK) + return retVal; + + /* 0 0 2 bit 6 set 1, bit13 set to 0, bit12 nway_en*/ + if((retVal = rtl8367c_getAsicSdsReg(0, 0, 2, ®_data)) != RT_ERR_OK) + return retVal; + reg_data &= 0xFFFFDFFF; + reg_data |= 0x40; + if(pPortAbility->forcemode) + reg_data &= 0xffffefff; + else + reg_data |= 0x1000; + + if((retVal = rtl8367c_setAsicSdsReg(0,0,2, reg_data)) != RT_ERR_OK) + return retVal; + + /* 0 4 2 bit 8 rx pause, bit7 tx pause*/ + if((retVal = rtl8367c_getAsicSdsReg(0, 4, 2, ®_data)) != RT_ERR_OK) + return retVal; + + if (pPortAbility->txpause) + reg_data |= 0x80; + else + reg_data &= (~0x80); + + if (pPortAbility->rxpause) + reg_data |= 0x100; + else + reg_data &= (~0x100); + + if((retVal = rtl8367c_setAsicSdsReg(0,4,2, reg_data)) != RT_ERR_OK) + return retVal; + + /* 0 4 0 bit 12 set 0*/ + if((retVal = rtl8367c_getAsicSdsReg(0, 4, 0, ®_data)) != RT_ERR_OK) + return retVal; + reg_data &= 0xFFFFEFFF; + if((retVal = rtl8367c_setAsicSdsReg(0,4,0, reg_data)) != RT_ERR_OK) + return retVal; + + /*new_cfg_sds_mode=1000x*/ + if((retVal = rtl8367c_setAsicRegBits(0x1d95, 0x1f00, 0x4)) != RT_ERR_OK) + return retVal; + + } + else if(regValue2 == 0x5) + { +#if 0 + /*100FX*/ + if((retVal = rtl8367c_setAsicRegBits(0x1d95, 0x1f00, 0x1f)) != RT_ERR_OK) + return retVal; +#endif + + if((retVal = rtl8367c_setAsicRegBit(0x1d95, 13, 1)) != RT_ERR_OK) + return retVal; + + /* 0 4 0 bit 12 set 1, bit15~13 = 5*/ + if((retVal = rtl8367c_getAsicSdsReg(0, 4, 0, ®_data)) != RT_ERR_OK) + return retVal; + reg_data &= 0xFFFF0FFF; + reg_data |= 0xB000; + if((retVal = rtl8367c_setAsicSdsReg(0,4,0, reg_data)) != RT_ERR_OK) + return retVal; + + /* 0 0 2 bit 6 set 0, bit13 set to 1, bit12 0*/ + if((retVal = rtl8367c_getAsicSdsReg(0, 0, 2, ®_data)) != RT_ERR_OK) + return retVal; + reg_data &= 0xFFFFFFBF; + reg_data |= 0x2000; + reg_data &= 0xffffefff; + + if((retVal = rtl8367c_setAsicSdsReg(0,0,2, reg_data)) != RT_ERR_OK) + return retVal; + + /* 0 4 2 bit 8 rx pause, bit7 tx pause*/ + if((retVal = rtl8367c_getAsicSdsReg(0, 4, 2, ®_data)) != RT_ERR_OK) + return retVal; + if (pPortAbility->txpause) + reg_data |= 0x80; + else + reg_data &= (~0x80); + if (pPortAbility->rxpause) + reg_data |= 0x100; + else + reg_data &= (~0x100); + if((retVal = rtl8367c_setAsicSdsReg(0,4,2, reg_data)) != RT_ERR_OK) + return retVal; + + /* 0 4 0 bit 12 set 0*/ + if((retVal = rtl8367c_getAsicSdsReg(0, 4, 0, ®_data)) != RT_ERR_OK) + return retVal; + reg_data &= 0xFFFFEFFF; + if((retVal = rtl8367c_setAsicSdsReg(0,4,0, reg_data)) != RT_ERR_OK) + return retVal; + /* new_cfg_sds_mode=1000x */ + if((retVal = rtl8367c_setAsicRegBits(0x1d95, 0x1f00, 0x5)) != RT_ERR_OK) + return retVal; + + } + else if(regValue2 == 0x7) + { +#if 0 + /*100FX*/ + if((retVal = rtl8367c_setAsicRegBits(0x1d95, 0x1f00, 0x1f)) != RT_ERR_OK) + return retVal; +#endif + if((retVal = rtl8367c_setAsicRegBit(0x1d95, 13, 1)) != RT_ERR_OK) + return retVal; + + /* 0 4 0 bit 12 set 1, bit15~13 = 5*/ + if((retVal = rtl8367c_getAsicSdsReg(0, 4, 0, ®_data)) != RT_ERR_OK) + return retVal; + reg_data &= 0xFFFF0FFF; + reg_data |= 0xB000; + if((retVal = rtl8367c_setAsicSdsReg(0,4,0, reg_data)) != RT_ERR_OK) + return retVal; + + /* 0 0 2 bit 6 set 0, bit13 set to 1, bit12 0*/ + if((retVal = rtl8367c_getAsicSdsReg(0, 0, 2, ®_data)) != RT_ERR_OK) + return retVal; + reg_data &= 0xFFFFFFBF; + reg_data |= 0x2000; + reg_data &= 0xffffefff; + + if((retVal = rtl8367c_setAsicSdsReg(0,0,2, reg_data)) != RT_ERR_OK) + return retVal; + + /* 0 4 2 bit 8 rx pause, bit7 tx pause*/ + if((retVal = rtl8367c_getAsicSdsReg(0, 4, 2, ®_data)) != RT_ERR_OK) + return retVal; + if (pPortAbility->txpause) + reg_data |= 0x80; + else + reg_data &= 0xffffff7f; + if (pPortAbility->rxpause) + reg_data |= 0x100; + else + reg_data &= 0xfffffeff; + if((retVal = rtl8367c_setAsicSdsReg(0,4,2, reg_data)) != RT_ERR_OK) + return retVal; + + /* 0 4 0 bit 12 set 0*/ + if((retVal = rtl8367c_getAsicSdsReg(0, 4, 0, ®_data)) != RT_ERR_OK) + return retVal; + reg_data &= 0xFFFFEFFF; + if((retVal = rtl8367c_setAsicSdsReg(0,4,0, reg_data)) != RT_ERR_OK) + return retVal; + + /* 0 4 0 bit 12 set 1, bit15~13 = 4*/ + if((retVal = rtl8367c_getAsicSdsReg(0, 4, 0, ®_data)) != RT_ERR_OK) + return retVal; + reg_data &= 0xFFFF0FFF; + reg_data |= 0x9000; + if((retVal = rtl8367c_setAsicSdsReg(0,4,0, reg_data)) != RT_ERR_OK) + return retVal; + + /* 0 0 2 bit 6 set 1, bit13 set to 0, bit12 nway_en*/ + if((retVal = rtl8367c_getAsicSdsReg(0, 0, 2, ®_data)) != RT_ERR_OK) + return retVal; + reg_data &= 0xFFFFDFFF; + reg_data |= 0x40; + if(pPortAbility->forcemode) + reg_data &= 0xffffefff; + else + reg_data |= 0x1000; + + if((retVal = rtl8367c_setAsicSdsReg(0,0,2, reg_data)) != RT_ERR_OK) + return retVal; + + /* 0 4 2 bit 8 rx pause, bit7 tx pause*/ + if((retVal = rtl8367c_getAsicSdsReg(0, 4, 2, ®_data)) != RT_ERR_OK) + return retVal; + if (pPortAbility->txpause) + reg_data |= 0x80; + else + reg_data &= (~0x80); + if (pPortAbility->rxpause) + reg_data |= 0x100; + else + reg_data &=(~0x100); + if((retVal = rtl8367c_setAsicSdsReg(0,4,2, reg_data)) != RT_ERR_OK) + return retVal; + + /* 0 4 0 bit 12 set 0*/ + if((retVal = rtl8367c_getAsicSdsReg(0, 4, 0, ®_data)) != RT_ERR_OK) + return retVal; + reg_data &= 0xFFFFEFFF; + if((retVal = rtl8367c_setAsicSdsReg(0,4,0, reg_data)) != RT_ERR_OK) + return retVal; + + /*sds_mode:*/ + if((retVal = rtl8367c_setAsicRegBits(0x1d95, 0x1f00, 0x7)) != RT_ERR_OK) + return retVal; + + } + + /*disable force ability --- */ + if((retVal = rtl8367c_setAsicRegBit(0x137c, 12, 0)) != RT_ERR_OK) + return retVal; + return RT_ERR_OK; + + } + + /* new_cfg_sds_mode */ + if((retVal = rtl8367c_getAsicRegBits(0x1d95, 0x1f00, ®Value2)) != RT_ERR_OK) + return retVal; + if(regValue2 == 0x2) + { +#if 0 + /*SGMII*/ + if((retVal = rtl8367c_setAsicRegBits(0x1d95, 0x1f00, 0x1f)) != RT_ERR_OK) + return retVal; +#endif + if((retVal = rtl8367c_setAsicRegBit(0x1d95, 13, 1)) != RT_ERR_OK) + return retVal; + + for(i=0;i<0xfff; i++); + + if((retVal = rtl8367c_setAsicRegBits(0x1d95, 0x1f00, 0x2)) != RT_ERR_OK) + return retVal; + + for(i=0;i<0xfff; i++); + + if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_SGMII_FDUP_OFFSET, pPortAbility->duplex)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_SGMII_SPD_MASK, pPortAbility->speed)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_SGMII_TXFC_OFFSET, pPortAbility->txpause)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_SGMII_RXFC_OFFSET, pPortAbility->rxpause)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_SGMII_LINK_OFFSET, pPortAbility->link)) != RT_ERR_OK) + return retVal; + + /*disable force ability --- */ + if((retVal = rtl8367c_setAsicRegBit(0x137c, 12, 0)) != RT_ERR_OK) + return retVal; + return RT_ERR_OK; + } + else if(regValue2 == 0x12) + { +#if 0 + /*HiSGMII*/ + if((retVal = rtl8367c_setAsicRegBits(0x1d95, 0x1f00, 0x1f)) != RT_ERR_OK) + return retVal; +#endif + if((retVal = rtl8367c_setAsicRegBit(0x1d95, 13, 1)) != RT_ERR_OK) + return retVal; + + for(i=0;i<0xfff; i++); + + if((retVal = rtl8367c_setAsicRegBits(0x1d95, 0x1f00, 0x12)) != RT_ERR_OK) + return retVal; + + for(i=0;i<0xfff; i++); + + if((retVal = rtl8367c_setAsicRegBit(0x1d11, 11, 0x1)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_SGMII_FDUP_OFFSET, pPortAbility->duplex)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_SGMII_SPD_MASK, pPortAbility->speed)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_SGMII_TXFC_OFFSET, pPortAbility->txpause)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_SGMII_RXFC_OFFSET, pPortAbility->rxpause)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_SGMII_LINK_OFFSET, pPortAbility->link)) != RT_ERR_OK) + return retVal; + + /*disable force ability --- */ + if((retVal = rtl8367c_setAsicRegBit(0x137c, 12, 0)) != RT_ERR_OK) + return retVal; + return RT_ERR_OK; + + } + } + else + { + if((retVal = rtl8367c_getAsicRegBits(0x1d3d, 10, ®Value2)) != RT_ERR_OK) + return retVal; + if (regValue2 == 0) + { + /*ext1_force_ablty*/ + if((retVal = rtl8367c_setAsicRegBit(0x1311, 2, pPortAbility->duplex)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicRegBits(0x1311, 0x3, pPortAbility->speed)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicRegBit(0x1311, 4, pPortAbility->link)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicRegBit(0x1311, 6, pPortAbility->txpause)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicRegBit(0x1311, 5, pPortAbility->rxpause)) != RT_ERR_OK) + return retVal; + + /*force mode for ext1*/ + if((retVal = rtl8367c_setAsicRegBit(0x1311, 12, pPortAbility->forcemode)) != RT_ERR_OK) + return retVal; + + if (pPortAbility->link == 1) + { + if((retVal = rtl8367c_setAsicRegBit(0x1311, 4, 0)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicRegBit(0x1311, 4, 1)) != RT_ERR_OK) + return retVal; + } + else + { + if((retVal = rtl8367c_setAsicRegBits(0x1311, 0x3, 2)) != RT_ERR_OK) + return retVal; + } + + /*disable force ability --- */ + if((retVal = rtl8367c_setAsicRegBit(0x137c, 12, 0)) != RT_ERR_OK) + return retVal; + return RT_ERR_OK; + } + } + + + } + else if (2 == id) + { + + if((retVal = rtl8367c_getAsicRegBit(0x1d95, 0, &sgmiibit)) != RT_ERR_OK) + return retVal; + if (sgmiibit == 1) + { + /*for 1000x/100fx/1000x_100fx, param has to bet set to serdes registers*/ + if((retVal = rtl8367c_getAsicReg(0x1d95, ®Value)) != RT_ERR_OK) + return retVal; + /*cfg_mac7_sel_sgmii=1 & cfg_mac7_fib =1*/ + if((regValue & 0x3) == 0x3) + { + if((retVal = rtl8367c_getAsicRegBits(0x1d95, 0x1f00, ®Value2)) != RT_ERR_OK) + return retVal; + + if(regValue2 == 0x4) + { + /*1000X*/ +#if 0 + if((retVal = rtl8367c_setAsicRegBits(0x1d95, 0x1f00, 0x1f)) != RT_ERR_OK) + return retVal; +#endif + if((retVal = rtl8367c_setAsicRegBit(0x1d95, 13, 1)) != RT_ERR_OK) + return retVal; + + /* 0 4 0 bit 12 set 1, bit15~13 = 4*/ + if((retVal = rtl8367c_getAsicSdsReg(0, 4, 0, ®_data)) != RT_ERR_OK) + return retVal; + reg_data &= 0xFFFF0FFF; + reg_data |= 0x9000; + if((retVal = rtl8367c_setAsicSdsReg(0,4,0, reg_data)) != RT_ERR_OK) + return retVal; + + /* 0 0 2 bit 6 set 1, bit13 set to 0, bit12 nway_en*/ + if((retVal = rtl8367c_getAsicSdsReg(0, 0, 2, ®_data)) != RT_ERR_OK) + return retVal; + reg_data &= 0xFFFFDFFF; + reg_data |= 0x40; + if(pPortAbility->forcemode) + reg_data &= 0xffffefff; + else + reg_data |= 0x1000; + + if((retVal = rtl8367c_setAsicSdsReg(0,0,2, reg_data)) != RT_ERR_OK) + return retVal; + + /* 0 4 2 bit 8 rx pause, bit7 tx pause*/ + if((retVal = rtl8367c_getAsicSdsReg(0, 4, 2, ®_data)) != RT_ERR_OK) + return retVal; + if (pPortAbility->txpause) + reg_data |= 0x80; + else + reg_data &= 0xffffff7f; + if (pPortAbility->rxpause) + reg_data |= 0x100; + else + reg_data &= 0xfffffeff; + if((retVal = rtl8367c_setAsicSdsReg(0,4,2, reg_data)) != RT_ERR_OK) + return retVal; + + /* 0 4 0 bit 12 set 0*/ + if((retVal = rtl8367c_getAsicSdsReg(0, 4, 0, ®_data)) != RT_ERR_OK) + return retVal; + reg_data &= 0xFFFFEFFF; + if((retVal = rtl8367c_setAsicSdsReg(0,4,0, reg_data)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicRegBits(0x1d95, 0x1f00, 0x4)) != RT_ERR_OK) + return retVal; + + } + else if(regValue2 == 0x5) + { + /*100FX*/ +#if 0 + if((retVal = rtl8367c_setAsicRegBits(0x1d95, 0x1f00, 0x1f)) != RT_ERR_OK) + return retVal; +#endif + if((retVal = rtl8367c_setAsicRegBit(0x1d95, 13, 1)) != RT_ERR_OK) + return retVal; + + /* 0 4 0 bit 12 set 1, bit15~13 = 5*/ + if((retVal = rtl8367c_getAsicSdsReg(0, 4, 0, ®_data)) != RT_ERR_OK) + return retVal; + reg_data &= 0xFFFF0FFF; + reg_data |= 0xB000; + if((retVal = rtl8367c_setAsicSdsReg(0,4,0, reg_data)) != RT_ERR_OK) + return retVal; + + /* 0 0 2 bit 6 set 0, bit13 set to 1, bit12 0*/ + if((retVal = rtl8367c_getAsicSdsReg(0, 0, 2, ®_data)) != RT_ERR_OK) + return retVal; + reg_data &= 0xFFFFFFBF; + reg_data |= 0x2000; + reg_data &= 0xffffefff; + + if((retVal = rtl8367c_setAsicSdsReg(0,0,2, reg_data)) != RT_ERR_OK) + return retVal; + + /* 0 4 2 bit 8 rx pause, bit7 tx pause*/ + if((retVal = rtl8367c_getAsicSdsReg(0, 4, 2, ®_data)) != RT_ERR_OK) + return retVal; + if (pPortAbility->txpause) + reg_data |= 0x80; + else + reg_data &= 0xffffff7f; + if (pPortAbility->rxpause) + reg_data |= 0x100; + else + reg_data &= 0xfffffeff; + if((retVal = rtl8367c_setAsicSdsReg(0,4,2, reg_data)) != RT_ERR_OK) + return retVal; + + /* 0 4 0 bit 12 set 0*/ + if((retVal = rtl8367c_getAsicSdsReg(0, 4, 0, ®_data)) != RT_ERR_OK) + return retVal; + reg_data &= 0xFFFFEFFF; + if((retVal = rtl8367c_setAsicSdsReg(0,4,0, reg_data)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicRegBits(0x1d95, 0x1f00, 0x5)) != RT_ERR_OK) + return retVal; + + } + else if(regValue2 == 0x7) + { + /*100FX*/ +#if 0 + if((retVal = rtl8367c_setAsicRegBits(0x1d95, 0x1f00, 0x1f)) != RT_ERR_OK) + return retVal; +#endif + if((retVal = rtl8367c_setAsicRegBit(0x1d95, 13, 1)) != RT_ERR_OK) + return retVal; + + /* 0 4 0 bit 12 set 1, bit15~13 = 5*/ + if((retVal = rtl8367c_getAsicSdsReg(0, 4, 0, ®_data)) != RT_ERR_OK) + return retVal; + reg_data &= 0xFFFF0FFF; + reg_data |= 0xB000; + if((retVal = rtl8367c_setAsicSdsReg(0,4,0, reg_data)) != RT_ERR_OK) + return retVal; + + /* 0 0 2 bit 6 set 0, bit13 set to 1, bit12 0*/ + if((retVal = rtl8367c_getAsicSdsReg(0, 0, 2, ®_data)) != RT_ERR_OK) + return retVal; + reg_data &= 0xFFFFFFBF; + reg_data |= 0x2000; + reg_data &= 0xffffefff; + + if((retVal = rtl8367c_setAsicSdsReg(0,0,2, reg_data)) != RT_ERR_OK) + return retVal; + + /* 0 4 2 bit 8 rx pause, bit7 tx pause*/ + if((retVal = rtl8367c_getAsicSdsReg(0, 4, 2, ®_data)) != RT_ERR_OK) + return retVal; + if (pPortAbility->txpause) + reg_data |= 0x80; + else + reg_data &= 0xffffff7f; + if (pPortAbility->rxpause) + reg_data |= 0x100; + else + reg_data &= 0xfffffeff; + if((retVal = rtl8367c_setAsicSdsReg(0,4,2, reg_data)) != RT_ERR_OK) + return retVal; + + /* 0 4 0 bit 12 set 0*/ + if((retVal = rtl8367c_getAsicSdsReg(0, 4, 0, ®_data)) != RT_ERR_OK) + return retVal; + reg_data &= 0xFFFFEFFF; + if((retVal = rtl8367c_setAsicSdsReg(0,4,0, reg_data)) != RT_ERR_OK) + return retVal; + + /* 0 4 0 bit 12 set 1, bit15~13 = 4*/ + if((retVal = rtl8367c_getAsicSdsReg(0, 4, 0, ®_data)) != RT_ERR_OK) + return retVal; + reg_data &= 0xFFFF0FFF; + reg_data |= 0x9000; + if((retVal = rtl8367c_setAsicSdsReg(0,4,0, reg_data)) != RT_ERR_OK) + return retVal; + + /* 0 0 2 bit 6 set 1, bit13 set to 0, bit12 nway_en*/ + if((retVal = rtl8367c_getAsicSdsReg(0, 0, 2, ®_data)) != RT_ERR_OK) + return retVal; + reg_data &= 0xFFFFDFFF; + reg_data |= 0x40; + if(pPortAbility->forcemode) + reg_data &= 0xffffefff; + else + reg_data |= 0x1000; + + if((retVal = rtl8367c_setAsicSdsReg(0,0,2, reg_data)) != RT_ERR_OK) + return retVal; + + /* 0 4 2 bit 8 rx pause, bit7 tx pause*/ + if((retVal = rtl8367c_getAsicSdsReg(0, 4, 2, ®_data)) != RT_ERR_OK) + return retVal; + if (pPortAbility->txpause) + reg_data |= 0x80; + else + reg_data &= 0xffffff7f; + if (pPortAbility->rxpause) + reg_data |= 0x100; + else + reg_data &= 0xfffffeff; + if((retVal = rtl8367c_setAsicSdsReg(0,4,2, reg_data)) != RT_ERR_OK) + return retVal; + + /* 0 4 0 bit 12 set 0*/ + if((retVal = rtl8367c_getAsicSdsReg(0, 4, 0, ®_data)) != RT_ERR_OK) + return retVal; + reg_data &= 0xFFFFEFFF; + if((retVal = rtl8367c_setAsicSdsReg(0,4,0, reg_data)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicRegBits(0x1d95, 0x1f00, 0x7)) != RT_ERR_OK) + return retVal; + + } + + if((retVal = rtl8367c_setAsicRegBit(0x137d, 12, 0)) != RT_ERR_OK) + return retVal; + return RT_ERR_OK; + + } + + if((retVal = rtl8367c_getAsicRegBits(0x1d95, 0x1f00, ®Value2)) != RT_ERR_OK) + return retVal; + if(regValue2 == 0x2) + { + /*SGMII*/ +#if 0 + if((retVal = rtl8367c_setAsicRegBits(0x1d95, 0x1f00, 0x1f)) != RT_ERR_OK) + return retVal; +#endif + if((retVal = rtl8367c_setAsicRegBit(0x1d95, 13, 1)) != RT_ERR_OK) + return retVal; + + for(i=0;i<0xfff; i++); + + /* 0 2 0 bit 8-9 nway*/ + if((retVal = rtl8367c_getAsicSdsReg(0, 2, 0, ®_data)) != RT_ERR_OK) + return retVal; + reg_data &= 0xfffffcff; + if (pPortAbility->nway) + reg_data &= 0xfffffcff; + else + reg_data |= 0x100; + if((retVal = rtl8367c_setAsicSdsReg(0,2,0, reg_data)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicRegBits(0x1d95, 0x1f00, 0x2)) != RT_ERR_OK) + return retVal; + + for(i=0;i<0xfff; i++); + + if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_SGMII_FDUP_OFFSET, pPortAbility->duplex)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_SGMII_SPD_MASK, pPortAbility->speed)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_SGMII_TXFC_OFFSET, pPortAbility->txpause)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_SGMII_RXFC_OFFSET, pPortAbility->rxpause)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_SGMII_LINK_OFFSET, pPortAbility->link)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicRegBit(0x137d, 12, 0)) != RT_ERR_OK) + return retVal; + return RT_ERR_OK; + } + } + else + { + + /*ext2_force_ablty*/ + if((retVal = rtl8367c_setAsicRegBit(0x13c4, 2, pPortAbility->duplex)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicRegBits(0x13c4, 0x3, pPortAbility->speed)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicRegBit(0x13c4, 4, pPortAbility->link)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicRegBit(0x13c4, 6, pPortAbility->txpause)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicRegBit(0x13c4, 5, pPortAbility->rxpause)) != RT_ERR_OK) + return retVal; + + /*force mode for ext2*/ + if((retVal = rtl8367c_setAsicRegBit(0x13c4, 12, pPortAbility->forcemode)) != RT_ERR_OK) + return retVal; + + if (pPortAbility->link == 1) + { + if((retVal = rtl8367c_setAsicRegBit(0x13c4, 4, 0)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicRegBit(0x13c4, 4, 1)) != RT_ERR_OK) + return retVal; + } + else + { + if((retVal = rtl8367c_setAsicRegBits(0x13c4, 0x3, 2)) != RT_ERR_OK) + return retVal; + } + + + if((retVal = rtl8367c_getAsicRegBit(0x1d3d, 10, ®_data)) != RT_ERR_OK) + return retVal; + if(reg_data == 1) + { + if((retVal = rtl8367c_setAsicRegBit(0x1311, 2, pPortAbility->duplex)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicRegBits(0x1311, 0x3, pPortAbility->speed)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicRegBit(0x1311, 4, pPortAbility->link)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicRegBit(0x1311, 6, pPortAbility->txpause)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicRegBit(0x1311, 5, pPortAbility->rxpause)) != RT_ERR_OK) + return retVal; + + /*force mode for ext1*/ + if((retVal = rtl8367c_setAsicRegBit(0x1311, 12, pPortAbility->forcemode)) != RT_ERR_OK) + return retVal; + + if (pPortAbility->link == 1) + { + if((retVal = rtl8367c_setAsicRegBit(0x1311, 4, 0)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicRegBit(0x1311, 4, 1)) != RT_ERR_OK) + return retVal; + } + else + { + if((retVal = rtl8367c_setAsicRegBits(0x1311, 0x3, 2)) != RT_ERR_OK) + return retVal; + } + } + + + } + + /*disable force ability --- */ + if((retVal = rtl8367c_setAsicRegBit(0x137d, 12, 0)) != RT_ERR_OK) + return retVal; + } +#if 0 + if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_SGMII_FDUP_OFFSET, pPortAbility->duplex)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_SGMII_SPD_MASK, pPortAbility->speed)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_SGMII_TXFC_OFFSET, pPortAbility->txpause)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_SGMII_RXFC_OFFSET, pPortAbility->rxpause)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_SGMII_LINK_OFFSET, pPortAbility->link)) != RT_ERR_OK) + return retVal; +#endif + } + + return RT_ERR_OK; +} +/* Function Name: + * rtl8367c_getAsicPortForceLinkExt + * Description: + * Get external interface force linking configuration + * Input: + * id - external interface id (0~1) + * pPortAbility - port ability configuration + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - input parameter out of range + * Note: + * None + */ +ret_t rtl8367c_getAsicPortForceLinkExt(rtk_uint32 id, rtl8367c_port_ability_t *pPortAbility) +{ + rtk_uint32 reg_data, regValue, type; + rtk_uint32 sgmiiSel; + rtk_uint32 hsgmiiSel; + rtk_uint32 Mode; + ret_t retVal; + + + if(id >= RTL8367C_EXTNO) + return RT_ERR_OUT_OF_RANGE; + + if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0249)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_getAsicReg(0x1300, ®Value)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0000)) != RT_ERR_OK) + return retVal; + + type = 0; + + switch (regValue) + { + case 0x0276: + case 0x0597: + case 0x6367: + type = 1; + break; + case 0x0652: + case 0x6368: + type = 2; + break; + case 0x0801: + case 0x6511: + type = 3; + break; + default: + return RT_ERR_FAILED; + } + + if (1 == type) + { + if(1 == id) + { + if((retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_MAC8_SEL_SGMII_OFFSET, &sgmiiSel)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_MAC8_SEL_HSGMII_OFFSET, &hsgmiiSel)) != RT_ERR_OK) + return retVal; + + if( (sgmiiSel == 1) || (hsgmiiSel == 1) ) + { + memset(pPortAbility, 0x00, sizeof(rtl8367c_port_ability_t)); + pPortAbility->forcemode = 1; + + if((retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_SGMII_FDUP_OFFSET, ®_data)) != RT_ERR_OK) + return retVal; + + pPortAbility->duplex = reg_data; + + if((retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_SGMII_SPD_MASK, ®_data)) != RT_ERR_OK) + return retVal; + + pPortAbility->speed = reg_data; + + if((retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_SGMII_LINK_OFFSET, ®_data)) != RT_ERR_OK) + return retVal; + + pPortAbility->link = reg_data; + + if((retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_SGMII_TXFC_OFFSET, ®_data)) != RT_ERR_OK) + return retVal; + + pPortAbility->txpause = reg_data; + + if((retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_SGMII_RXFC_OFFSET, ®_data)) != RT_ERR_OK) + return retVal; + + pPortAbility->rxpause = reg_data; + + return RT_ERR_OK; + } + } + + if(0 == id || 1 == id) + retVal = rtl8367c_getAsicReg(RTL8367C_REG_DIGITAL_INTERFACE0_FORCE+id, ®_data); + else + retVal = rtl8367c_getAsicReg(RTL8367C_REG_DIGITAL_INTERFACE2_FORCE, ®_data); + + if(retVal != RT_ERR_OK) + return retVal; + + pPortAbility->forcemode = (reg_data >> 12) & 0x0001; + pPortAbility->mstfault = (reg_data >> 9) & 0x0001; + pPortAbility->mstmode = (reg_data >> 8) & 0x0001; + pPortAbility->nway = (reg_data >> 7) & 0x0001; + pPortAbility->txpause = (reg_data >> 6) & 0x0001; + pPortAbility->rxpause = (reg_data >> 5) & 0x0001; + pPortAbility->link = (reg_data >> 4) & 0x0001; + pPortAbility->duplex = (reg_data >> 2) & 0x0001; + pPortAbility->speed = reg_data & 0x0003; + } + else if (2 == type) + { + if (id == 1) + { + if ((retVal = rtl8367c_getAsicReg(0x1311, ®_data))!=RT_ERR_OK) + return retVal; + + pPortAbility->forcemode = (reg_data >> 12) & 1; + pPortAbility->duplex = (reg_data >> 2) & 1; + pPortAbility->link = (reg_data >> 4) & 1; + pPortAbility->speed = reg_data & 3; + pPortAbility->rxpause = (reg_data >> 5) & 1; + pPortAbility->txpause = (reg_data >> 6) & 1; + } + else if (2 == id) + { + if ((retVal = rtl8367c_getAsicReg(0x13c4, ®_data))!=RT_ERR_OK) + return retVal; + + pPortAbility->forcemode = (reg_data >> 12) & 1; + pPortAbility->duplex = (reg_data >> 2) & 1; + pPortAbility->link = (reg_data >> 4) & 1; + pPortAbility->speed = reg_data & 3; + pPortAbility->rxpause = (reg_data >> 5) & 1; + pPortAbility->txpause = (reg_data >> 6) & 1; + } + } + else if (3 == type) + { + if (id == 1) + { + + if((retVal = rtl8367c_getAsicPortExtMode(id, &Mode))!=RT_ERR_OK) + return retVal; + if(Mode < EXT_SGMII) + { + + if ((retVal = rtl8367c_getAsicReg(0x1311, ®_data))!=RT_ERR_OK) + return retVal; + + pPortAbility->forcemode = (reg_data >> 12) & 1; + pPortAbility->duplex = (reg_data >> 2) & 1; + pPortAbility->link = (reg_data >> 4) & 1; + pPortAbility->speed = reg_data & 3; + pPortAbility->rxpause = (reg_data >> 5) & 1; + pPortAbility->txpause = (reg_data >> 6) & 1; + } + else if(Mode < EXT_1000X_100FX) + { + if ((retVal = rtl8367c_getAsicReg(0x1d11, ®_data))!=RT_ERR_OK) + return retVal; + + //pPortAbility->forcemode = (reg_data >> 12) & 1; + pPortAbility->duplex = (reg_data >> 10) & 1; + pPortAbility->link = (reg_data >> 9) & 1; + pPortAbility->speed = (reg_data >> 7) & 3; + pPortAbility->rxpause = (reg_data >> 14) & 1; + pPortAbility->txpause = (reg_data >> 13) & 1; + } + else if(Mode < EXT_RGMII_2) + { + if ((retVal = rtl8367c_getAsicReg(0x1358, ®_data))!=RT_ERR_OK) + return retVal; + + //pPortAbility->forcemode = (reg_data >> 12) & 1; + pPortAbility->duplex = (reg_data >> 2) & 1; + pPortAbility->link = (reg_data >> 4) & 1; + pPortAbility->speed = reg_data & 3; + pPortAbility->rxpause = (reg_data >> 5) & 1; + pPortAbility->txpause = (reg_data >> 6) & 1; + } + + } + else if (2 == id) + { + if((retVal = rtl8367c_getAsicPortExtMode(id, &Mode))!=RT_ERR_OK) + return retVal; + if(Mode < EXT_SGMII) + { + + if ((retVal = rtl8367c_getAsicReg(0x13c4, ®_data))!=RT_ERR_OK) + return retVal; + + pPortAbility->forcemode = (reg_data >> 12) & 1; + pPortAbility->duplex = (reg_data >> 2) & 1; + pPortAbility->link = (reg_data >> 4) & 1; + pPortAbility->speed = reg_data & 3; + pPortAbility->rxpause = (reg_data >> 5) & 1; + pPortAbility->txpause = (reg_data >> 6) & 1; + } + else if(Mode < EXT_1000X_100FX) + { + if ((retVal = rtl8367c_getAsicReg(0x1d11, ®_data))!=RT_ERR_OK) + return retVal; + + //pPortAbility->forcemode = (reg_data >> 12) & 1; + pPortAbility->duplex = (reg_data >> 10) & 1; + pPortAbility->link = (reg_data >> 9) & 1; + pPortAbility->speed = (reg_data >> 7) & 3; + pPortAbility->rxpause = (reg_data >> 14) & 1; + pPortAbility->txpause = (reg_data >> 13) & 1; + } + else if(Mode < EXT_RGMII_2) + { + if ((retVal = rtl8367c_getAsicReg(0x1359, ®_data))!=RT_ERR_OK) + return retVal; + + //pPortAbility->forcemode = (reg_data >> 12) & 1; + pPortAbility->duplex = (reg_data >> 2) & 1; + pPortAbility->link = (reg_data >> 4) & 1; + pPortAbility->speed = reg_data & 3; + pPortAbility->rxpause = (reg_data >> 5) & 1; + pPortAbility->txpause = (reg_data >> 6) & 1; + } + else if(Mode < EXT_END) + { + + if ((retVal = rtl8367c_getAsicReg(0x1311, ®_data))!=RT_ERR_OK) + return retVal; + + pPortAbility->forcemode = (reg_data >> 12) & 1; + pPortAbility->duplex = (reg_data >> 2) & 1; + pPortAbility->link = (reg_data >> 4) & 1; + pPortAbility->speed = reg_data & 3; + pPortAbility->rxpause = (reg_data >> 5) & 1; + pPortAbility->txpause = (reg_data >> 6) & 1; + } + } + } + return RT_ERR_OK; +} +/* Function Name: + * rtl8367c_setAsicPortExtMode + * Description: + * Set external interface mode configuration + * Input: + * id - external interface id (0~2) + * mode - external interface mode + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - input parameter out of range + * Note: + * None + */ +ret_t rtl8367c_setAsicPortExtMode(rtk_uint32 id, rtk_uint32 mode) +{ + ret_t retVal; + rtk_uint32 i, regValue, type, option,reg_data,reg_value; + rtk_uint32 idx; + rtk_uint32 redData[][2] = { {0x04D7, 0x0480}, {0xF994, 0x0481}, {0x21A2, 0x0482}, {0x6960, 0x0483}, {0x9728, 0x0484}, {0x9D85, 0x0423}, {0xD810, 0x0424}, {0x83F2, 0x002E} }; + rtk_uint32 redDataSB[][2] = { {0x04D7, 0x0480}, {0xF994, 0x0481}, {0x2420, 0x0482}, {0x6960, 0x0483}, {0x9728, 0x0484}, {0x9D85, 0x0423}, {0xD810, 0x0424}, {0x83F2, 0x002E} }; + rtk_uint32 redData1[][2] = { {0x82F1, 0x0500}, {0xF195, 0x0501}, {0x31A2, 0x0502}, {0x796C, 0x0503}, {0x9728, 0x0504}, {0x9D85, 0x0423}, {0xD810, 0x0424}, {0x0F80, 0x0001}, {0x83F2, 0x002E} }; + rtk_uint32 redData5[][2] = { {0x82F1, 0x0500}, {0xF195, 0x0501}, {0x31A2, 0x0502}, {0x796C, 0x0503}, {0x9728, 0x0504}, {0x9D85, 0x0423}, {0xD810, 0x0424}, {0x0F80, 0x0001}, {0x83F2, 0x002E} }; + rtk_uint32 redData6[][2] = { {0x82F1, 0x0500}, {0xF195, 0x0501}, {0x31A2, 0x0502}, {0x796C, 0x0503}, {0x9728, 0x0504}, {0x9D85, 0x0423}, {0xD810, 0x0424}, {0x0F80, 0x0001}, {0x83F2, 0x002E} }; + rtk_uint32 redData8[][2] = { {0x82F1, 0x0500}, {0xF995, 0x0501}, {0x31A2, 0x0502}, {0x796C, 0x0503}, {0x9728, 0x0504}, {0x9D85, 0x0423}, {0xD810, 0x0424}, {0x0F80, 0x0001}, {0x83F2, 0x002E} }; + rtk_uint32 redData9[][2] = { {0x82F1, 0x0500}, {0xF995, 0x0501}, {0x31A2, 0x0502}, {0x796C, 0x0503}, {0x9728, 0x0504}, {0x9D85, 0x0423}, {0xD810, 0x0424}, {0x0F80, 0x0001}, {0x83F2, 0x002E} }; + rtk_uint32 redDataHB[][2] = { {0x82F0, 0x0500}, {0xF195, 0x0501}, {0x31A2, 0x0502}, {0x7960, 0x0503}, {0x9728, 0x0504}, {0x9D85, 0x0423}, {0xD810, 0x0424}, {0x0F80, 0x0001}, {0x83F2, 0x002E} }; + + if(id >= RTL8367C_EXTNO) + return RT_ERR_OUT_OF_RANGE; + + if(mode >= EXT_END) + return RT_ERR_OUT_OF_RANGE; + + if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0249)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_getAsicReg(0x1300, ®Value)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0000)) != RT_ERR_OK) + return retVal; + + type = 0; + + switch (regValue) + { + case 0x0276: + case 0x0597: + case 0x6367: + type = 1; + break; + case 0x0652: + case 0x6368: + type = 2; + break; + case 0x0801: + case 0x6511: + type = 3; + break; + default: + return RT_ERR_FAILED; + } + + + if (1==type) + { + if((mode == EXT_1000X_100FX) || (mode == EXT_1000X) || (mode == EXT_100FX)) + { + if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_REG_TO_ECO4, 5, 1)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_REG_TO_ECO4, 7, 1)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_CHIP_RESET, RTL8367C_DW8051_RST_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_MISCELLANEOUS_CONFIGURE0, RTL8367C_DW8051_EN_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_DW8051_RDY, RTL8367C_ACS_IROM_ENABLE_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_DW8051_RDY, RTL8367C_IROM_MSB_OFFSET, 0)) != RT_ERR_OK) + return retVal; + + if(mode == EXT_1000X_100FX) + { + for(idx = 0; idx < FIBER2_AUTO_INIT_SIZE; idx++) + { + if ((retVal = rtl8367c_setAsicReg(0xE000 + idx, (rtk_uint32)Fiber2_Auto[idx])) != RT_ERR_OK) + return retVal; + } + } + + if(mode == EXT_1000X) + { + for(idx = 0; idx < FIBER2_1G_INIT_SIZE; idx++) + { + if ((retVal = rtl8367c_setAsicReg(0xE000 + idx, (rtk_uint32)Fiber2_1G[idx])) != RT_ERR_OK) + return retVal; + } + } + + if(mode == EXT_100FX) + { + for(idx = 0; idx < FIBER2_100M_INIT_SIZE; idx++) + { + if ((retVal = rtl8367c_setAsicReg(0xE000 + idx, (rtk_uint32)Fiber2_100M[idx])) != RT_ERR_OK) + return retVal; + } + } + + if ((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_DW8051_RDY, RTL8367C_IROM_MSB_OFFSET, 0)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_DW8051_RDY, RTL8367C_ACS_IROM_ENABLE_OFFSET, 0)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_CHIP_RESET, RTL8367C_DW8051_RST_OFFSET, 0)) != RT_ERR_OK) + return retVal; + } + + if(mode == EXT_GMII) + { + if( (retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_EXT0_RGMXF, RTL8367C_EXT0_RGTX_INV_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_EXT1_RGMXF, RTL8367C_EXT1_RGTX_INV_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_EXT_TXC_DLY, RTL8367C_EXT1_GMII_TX_DELAY_MASK, 5)) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_EXT_TXC_DLY, RTL8367C_EXT0_GMII_TX_DELAY_MASK, 6)) != RT_ERR_OK) + return retVal; + } + + /* Serdes reset */ + if( (mode == EXT_TMII_MAC) || (mode == EXT_TMII_PHY) ) + { + if( (retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_BYPASS_LINE_RATE, id, 1)) != RT_ERR_OK) + return retVal; + } + else + { + if( (retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_BYPASS_LINE_RATE, id, 0)) != RT_ERR_OK) + return retVal; + } + + if( (mode == EXT_SGMII) || (mode == EXT_HSGMII) ) + { + if(id != 1) + return RT_ERR_PORT_ID; + + if((retVal = rtl8367c_setAsicReg(0x13C0, 0x0249)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_getAsicReg(0x13C1, &option)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicReg(0x13C0, 0x0000)) != RT_ERR_OK) + return retVal; + } + + if(mode == EXT_SGMII) + { + if(option == 0) + { + for(i = 0; i <= 7; i++) + { + if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_DATA, redData[i][0])) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_ADR, redData[i][1])) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_CMD, 0x00C0)) != RT_ERR_OK) + return retVal; + } + } + else + { + for(i = 0; i <= 7; i++) + { + if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_DATA, redDataSB[i][0])) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_ADR, redDataSB[i][1])) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_CMD, 0x00C0)) != RT_ERR_OK) + return retVal; + } + } + } + + if(mode == EXT_HSGMII) + { + if(option == 0) + { + if( (retVal = rtl8367c_setAsicReg(0x13c2, 0x0249)) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367c_getAsicReg(0x1301, ®Value)) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367c_setAsicReg(0x13c2, 0x0000)) != RT_ERR_OK) + return retVal; + + if ( ((regValue & 0x00F0) >> 4) == 0x0001) + { + for(i = 0; i <= 8; i++) + { + if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_DATA, redData1[i][0])) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_ADR, redData1[i][1])) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_CMD, 0x00C0)) != RT_ERR_OK) + return retVal; + } + } + else if ( ((regValue & 0x00F0) >> 4) == 0x0005) + { + for(i = 0; i <= 8; i++) + { + if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_DATA, redData5[i][0])) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_ADR, redData5[i][1])) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_CMD, 0x00C0)) != RT_ERR_OK) + return retVal; + } + } + else if ( ((regValue & 0x00F0) >> 4) == 0x0006) + { + for(i = 0; i <= 8; i++) + { + if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_DATA, redData6[i][0])) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_ADR, redData6[i][1])) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_CMD, 0x00C0)) != RT_ERR_OK) + return retVal; + } + } + else if ( ((regValue & 0x00F0) >> 4) == 0x0008) + { + for(i = 0; i <= 8; i++) + { + if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_DATA, redData8[i][0])) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_ADR, redData8[i][1])) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_CMD, 0x00C0)) != RT_ERR_OK) + return retVal; + } + } + else if ( ((regValue & 0x00F0) >> 4) == 0x0009) + { + for(i = 0; i <= 8; i++) + { + if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_DATA, redData9[i][0])) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_ADR, redData9[i][1])) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_CMD, 0x00C0)) != RT_ERR_OK) + return retVal; + } + } + } + else + { + for(i = 0; i <= 8; i++) + { + if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_DATA, redDataHB[i][0])) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_ADR, redDataHB[i][1])) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_CMD, 0x00C0)) != RT_ERR_OK) + return retVal; + } + } + } + + /* Only one ext port should care SGMII setting */ + if(id == 1) + { + + if(mode == EXT_SGMII) + { + if( (retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_MAC8_SEL_SGMII_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_MAC8_SEL_HSGMII_OFFSET, 0)) != RT_ERR_OK) + return retVal; + } + else if(mode == EXT_HSGMII) + { + if( (retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_MAC8_SEL_SGMII_OFFSET, 0)) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_MAC8_SEL_HSGMII_OFFSET, 1)) != RT_ERR_OK) + return retVal; + } + else + { + + if((mode != EXT_1000X_100FX) && (mode != EXT_1000X) && (mode != EXT_100FX)) + { + if( (retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_MAC8_SEL_SGMII_OFFSET, 0)) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_MAC8_SEL_HSGMII_OFFSET, 0)) != RT_ERR_OK) + return retVal; + } + } + } + + if(0 == id || 1 == id) + { + if((retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_DIGITAL_INTERFACE_SELECT, RTL8367C_SELECT_GMII_0_MASK << (id * RTL8367C_SELECT_GMII_1_OFFSET), mode)) != RT_ERR_OK) + return retVal; + } + else + { + if((retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_DIGITAL_INTERFACE_SELECT_1, RTL8367C_SELECT_GMII_2_MASK, mode)) != RT_ERR_OK) + return retVal; + } + + /* Serdes not reset */ + if( (mode == EXT_SGMII) || (mode == EXT_HSGMII) ) + { + if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_DATA, 0x7106)) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_ADR, 0x0003)) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_CMD, 0x00C0)) != RT_ERR_OK) + return retVal; + } + + if( (mode == EXT_SGMII) || (mode == EXT_HSGMII) ) + { + if ((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_CHIP_RESET, RTL8367C_DW8051_RST_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_MISCELLANEOUS_CONFIGURE0, RTL8367C_DW8051_EN_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_DW8051_RDY, RTL8367C_ACS_IROM_ENABLE_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_DW8051_RDY, RTL8367C_IROM_MSB_OFFSET, 0)) != RT_ERR_OK) + return retVal; + + for(idx = 0; idx < SGMII_INIT_SIZE; idx++) + { + if ((retVal = rtl8367c_setAsicReg(0xE000 + idx, (rtk_uint32)Sgmii_Init[idx])) != RT_ERR_OK) + return retVal; + } + + if ((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_DW8051_RDY, RTL8367C_IROM_MSB_OFFSET, 0)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_DW8051_RDY, RTL8367C_ACS_IROM_ENABLE_OFFSET, 0)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_CHIP_RESET, RTL8367C_DW8051_RST_OFFSET, 0)) != RT_ERR_OK) + return retVal; + } + } + else if (2 == type) + { + + if ((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_CHIP_RESET, RTL8367C_DW8051_RST_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_MISCELLANEOUS_CONFIGURE0, RTL8367C_DW8051_EN_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_DW8051_RDY, RTL8367C_ACS_IROM_ENABLE_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_DW8051_RDY, RTL8367C_IROM_MSB_OFFSET, 0)) != RT_ERR_OK) + return retVal; + + for(idx = 0; idx < FIBER1_2_INIT_SIZE; idx++) + { + if ((retVal = rtl8367c_setAsicReg(0xE000 + idx, (rtk_uint32)Fiber1_2_Init[idx])) != RT_ERR_OK) + return retVal; + } + + + if ((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_DW8051_RDY, RTL8367C_IROM_MSB_OFFSET, 0)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_DW8051_RDY, RTL8367C_ACS_IROM_ENABLE_OFFSET, 0)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_CHIP_RESET, RTL8367C_DW8051_RST_OFFSET, 0)) != RT_ERR_OK) + return retVal; + + + if( (mode == EXT_TMII_MAC) || (mode == EXT_TMII_PHY) ) + { + if( (retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_BYPASS_LINE_RATE, id+2, 1)) != RT_ERR_OK) + return retVal; + } + else + { + if( (retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_BYPASS_LINE_RATE, id+2, 0)) != RT_ERR_OK) + return retVal; + } + + + if (id == 1) + { + if(mode == EXT_HSGMII) + return RT_ERR_PORT_ID; + + if (mode == EXT_SGMII) + { + + if ((retVal = rtl8367c_setAsicRegBits(0x1305, 0xf0, 0)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBit(0x1d92, 14, 1)) != RT_ERR_OK) + return retVal; + } + else if (mode == EXT_1000X || mode == EXT_100FX || mode == EXT_1000X_100FX) + { + + if ((retVal = rtl8367c_setAsicRegBits(0x1305, 0xf0, 0)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBit(0x1d92, 14, 0)) != RT_ERR_OK) + return retVal; + + + if((retVal = rtl8367c_setAsicRegBit(0x6210, 11, 0)) != RT_ERR_OK) + return retVal; + } + else + { + + if ((retVal = rtl8367c_setAsicRegBits(0x1305, 0xf0, mode)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBit(0x1d92, 14, 0)) != RT_ERR_OK) + return retVal; + } + + if ((retVal = rtl8367c_setAsicRegBits(0x1d92, 0x1f00, 0x1f)) != RT_ERR_OK) + return retVal; + } + else if(id == 2) + { + if (mode == EXT_HSGMII) + { + if ((retVal = rtl8367c_setAsicReg(0x130, 7)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicReg(0x39f, 7)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicReg(0x3fa, 7)) != RT_ERR_OK) + return retVal; + } + else + { + if ((retVal = rtl8367c_setAsicReg(0x130, 1)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicReg(0x39f, 1)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicReg(0x3fa, 4)) != RT_ERR_OK) + return retVal; + + } + + + if (mode == EXT_SGMII) + { + + if ((retVal = rtl8367c_setAsicRegBits(0x13c3, 0xf, 0)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBit(0x1d92, 6, 1)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBit(0x1d92, 7, 0)) != RT_ERR_OK) + return retVal; + } + else if (mode == EXT_HSGMII) + { + + if ((retVal = rtl8367c_setAsicRegBits(0x13c3, 0xf, 0)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBit(0x1d92, 6, 0)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBit(0x1d92, 7, 1)) != RT_ERR_OK) + return retVal; + } + else if (mode == EXT_1000X || mode == EXT_100FX || mode == EXT_1000X_100FX) + { + + if ((retVal = rtl8367c_setAsicRegBits(0x13c3, 0xf, 0)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBit(0x1d92, 6, 0)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBit(0x1d92, 7, 0)) != RT_ERR_OK) + return retVal; + + + if((retVal = rtl8367c_setAsicRegBit(0x6200, 11, 0)) != RT_ERR_OK) + return retVal; + } + else + { + + if ((retVal = rtl8367c_setAsicRegBits(0x13c3, 0xf, mode)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBit(0x1d92, 6, 0)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBit(0x1d92, 7, 0)) != RT_ERR_OK) + return retVal; + } + + if ((retVal = rtl8367c_setAsicRegBits(0x1d92, 0x1f, 0x1f)) != RT_ERR_OK) + return retVal; + } + + + if (mode == EXT_RGMII) + { + + if ((retVal = rtl8367c_setAsicReg(RTL8367C_REG_PARA_LED_IO_EN3, 0)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicReg(RTL8367C_REG_PARA_LED_IO_EN1, 0)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicReg(RTL8367C_REG_PARA_LED_IO_EN2, 0)) != RT_ERR_OK) + return retVal; + + + if (id == 1) + { + + if ((retVal = rtl8367c_setAsicRegBit(0x1303, 9, 1)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBit(0x1303, 6, 1)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBit(0x1303, 4, 1)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBit(0x1303, 1, 0)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_getAsicRegBit(0x1307, 3, ®_value)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicRegBit(0x1307, 3, reg_value)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBits(0x13f9, 0x38, 0)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_getAsicRegBits(0x1307, 0x7, ®_value)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicRegBits(0x1307, 0x7, reg_value)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBits(0x1304, 0x7000, 4)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBits(0x13f9, 0x700, 4)) != RT_ERR_OK) + return retVal; + } + else if (id == 2) + { + + if ((retVal = rtl8367c_setAsicRegBit(0x1303, 10, 1)) != RT_ERR_OK) + return retVal; + + /*drving 1*/ + if ((retVal = rtl8367c_setAsicRegBit(0x13e2, 2, 1)) != RT_ERR_OK) + return retVal; + + /*drving 1*/ + if ((retVal = rtl8367c_setAsicRegBit(0x13e2, 1, 1)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBit(0x13e2, 0, 0)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_getAsicRegBit(0x13c5, 3, ®_value)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicRegBit(0x13c5, 3, reg_value)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBits(0x13f9, 0x1c0, 0)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_getAsicRegBits(0x13c5, 0x7, ®_value)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicRegBits(0x13c5, 0x7, reg_value)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBits(0x13e2, 0x1c0, 4)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBits(0x13e2, 0x38, 4)) != RT_ERR_OK) + return retVal; + } + } + else if (mode == EXT_SGMII) + { + if (id == 1) + { + /*sds 1 reg 1 page 0x21 write value 0xec91*/ + if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_DATA, 0xec91)) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_ADR, (0x21<<5) | 1)) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_CMD, 0x00C1)) != RT_ERR_OK) + return retVal; + + /*sds 1 reg 5 page 0x24 write value 0x5825*/ + if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_DATA, 0x5825)) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_ADR, (0x24<<5) | 5)) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_CMD, 0x00C1)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicRegBits(0x1d92, 0x1f00, 2)) != RT_ERR_OK) + return retVal; + + /*?????????????????*/ + + } + else if (id == 2) + { + /*sds 0 reg 0 page 0x28 write value 0x942c*/ + if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_DATA, 0x942c)) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_ADR, (0x28<<5) | 0)) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_CMD, 0x00C0)) != RT_ERR_OK) + return retVal; + + /*sds 0 reg 0 page 0x24 write value 0x942c*/ + if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_DATA, 0x942c)) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_ADR, (0x24<<5) | 0)) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_CMD, 0x00C0)) != RT_ERR_OK) + return retVal; + + /*sds 0 reg 5 page 0x21 write value 0x8dc3*/ + if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_DATA, 0x8dc3)) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_ADR, (0x21<<5) | 5)) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_CMD, 0x00C0)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicRegBits(0x1d92, 0x1f, 2)) != RT_ERR_OK) + return retVal; + + /*?????????????????*/ + } + } + else if (mode == EXT_HSGMII) + { + if (id == 2) + { + /*sds 0 reg 0 page 0x28 write value 0x942c*/ + if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_DATA, 0x942c)) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_ADR, (0x28<<5) | 0)) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_CMD, 0x00C0)) != RT_ERR_OK) + return retVal; + + /*sds 0 reg 0 page 0x24 write value 0x942c*/ + if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_DATA, 0x942c)) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_ADR, (0x24<<5) | 0)) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_CMD, 0x00C0)) != RT_ERR_OK) + return retVal; + + /*sds 0 reg 5 page 0x21 write value 0x8dc3*/ + if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_DATA, 0x8dc3)) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_ADR, (0x21<<5) | 5)) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_CMD, 0x00C0)) != RT_ERR_OK) + return retVal; + + + /* optimizing HISGMII performance while RGMII used & */ + /*sds 0 reg 9 page 0x21 write value 0x3931*/ + if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_DATA, 0x3931)) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_ADR, (0x21<<5)|9) ) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_CMD, 0x00C0)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBits(0x1d92, 0x1f, 0x12)) != RT_ERR_OK) + return retVal; + + /*?????????????????*/ + } + } + else if (mode == EXT_1000X) + { + if (id == 1) + { + + if( (retVal = rtl8367c_setAsicSdsReg(1, 1, 0x21, 0xec91)) != RT_ERR_OK) + return retVal; + if( (retVal = rtl8367c_setAsicSdsReg(1, 5, 0x24, 0x5825)) != RT_ERR_OK) + return retVal; + if ((retVal = rtl8367c_setAsicRegBits(0x1d92, 0x1f00, 4)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicRegBits(0x1d92, 0x1f00, 0x1f)) != RT_ERR_OK) + return retVal; + + /*patch speed change sds1 1000M*/ + if( (retVal = rtl8367c_getAsicSdsReg(1, 4, 0, ®Value)) != RT_ERR_OK) + return retVal; + regValue &= 0xFFFF0FFF; + regValue |= 0x9000; + if( (retVal = rtl8367c_setAsicSdsReg(1, 4, 0, regValue)) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367c_getAsicSdsReg(1, 0, 2, ®Value)) != RT_ERR_OK) + return retVal; + regValue &= 0xFFFFdFFF; + regValue |= 0x40; + if( (retVal = rtl8367c_setAsicSdsReg(1, 0, 2, regValue)) != RT_ERR_OK) + return retVal; + + + if( (retVal = rtl8367c_getAsicSdsReg(1, 4, 0, ®Value)) != RT_ERR_OK) + return retVal; + regValue &= 0xFFFFEFFF; + if( (retVal = rtl8367c_setAsicSdsReg(1, 4, 0, regValue)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicRegBits(0x1d92, 0x1f00, 4)) != RT_ERR_OK) + return retVal; + if ((retVal = rtl8367c_setAsicRegBits(0x1d92, 0x6000, 0)) != RT_ERR_OK) + return retVal; + + } + else if (id == 2) + { + if( (retVal = rtl8367c_setAsicSdsReg(0, 0, 0x28, 0x942c)) != RT_ERR_OK) + return retVal; + if( (retVal = rtl8367c_setAsicSdsReg(0, 0, 0x24, 0x942c)) != RT_ERR_OK) + return retVal; + if( (retVal = rtl8367c_setAsicSdsReg(0, 5, 0x21, 0x8dc3)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicRegBits(0x1d92, 0x1f, 4)) != RT_ERR_OK) + return retVal; + + /*patch speed change sds0 1000M*/ + if ((retVal = rtl8367c_setAsicRegBits(0x1d92, 0x1f, 0x1f)) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367c_getAsicSdsReg(0, 4, 0, ®Value)) != RT_ERR_OK) + return retVal; + regValue &= 0xFFFF0FFF; + regValue |= 0x9000; + if( (retVal = rtl8367c_setAsicSdsReg(0, 4, 0, regValue)) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367c_getAsicSdsReg(0, 0, 2, ®Value)) != RT_ERR_OK) + return retVal; + regValue &= 0xFFFFDFFF; + regValue |= 0x40; + if( (retVal = rtl8367c_setAsicSdsReg(0, 0, 2, regValue)) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367c_getAsicSdsReg(0, 4, 0, ®Value)) != RT_ERR_OK) + return retVal; + regValue &= 0xFFFFEFFF; + if( (retVal = rtl8367c_setAsicSdsReg(0, 4, 0, regValue)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicRegBits(0x1d92, 0x1f, 4)) != RT_ERR_OK) + return retVal; + if ((retVal = rtl8367c_setAsicRegBits(0x1d92, 0xe0, 0)) != RT_ERR_OK) + return retVal; + + } + } + else if (mode == EXT_100FX) + { + if (id == 1) + { + if( (retVal = rtl8367c_setAsicSdsReg(1, 1, 0x21, 0xec91)) != RT_ERR_OK) + return retVal; + if( (retVal = rtl8367c_setAsicSdsReg(1, 5, 0x24, 0x5825)) != RT_ERR_OK) + return retVal; + if ((retVal = rtl8367c_setAsicRegBits(0x1d92, 0x1f00, 5)) != RT_ERR_OK) + return retVal; + + /*patch speed change sds1 100M*/ + if ((retVal = rtl8367c_setAsicRegBits(0x1d92, 0x1f00, 0x1f)) != RT_ERR_OK) + return retVal; + if( (retVal = rtl8367c_getAsicSdsReg(1, 4, 0, ®Value)) != RT_ERR_OK) + return retVal; + regValue &= 0xFFFF0FFF; + regValue |= 0xb000; + if( (retVal = rtl8367c_setAsicSdsReg(1, 4, 0, regValue)) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367c_getAsicSdsReg(1, 0, 2, ®Value)) != RT_ERR_OK) + return retVal; + regValue &= 0xFFFFFFBF; + regValue |= 0x2000; + if( (retVal = rtl8367c_setAsicSdsReg(1, 0, 2, regValue)) != RT_ERR_OK) + return retVal; +#if 0 + if( (retVal = rtl8367c_setAsicReg(0x6214, 0x1a0)) != RT_ERR_OK) + return retVal; +#endif + if( (retVal = rtl8367c_getAsicSdsReg(1, 4, 0, ®Value)) != RT_ERR_OK) + return retVal; + regValue &= 0xFFFFEFFF; + if( (retVal = rtl8367c_setAsicSdsReg(1, 4, 0, regValue)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicRegBits(0x1d92, 0x1f00, 5)) != RT_ERR_OK) + return retVal; + if ((retVal = rtl8367c_setAsicRegBits(0x1d92, 0x6000, 0)) != RT_ERR_OK) + return retVal; + } + else if (id == 2) + { + if( (retVal = rtl8367c_setAsicSdsReg(0, 0, 0x28, 0x942c)) != RT_ERR_OK) + return retVal; + if( (retVal = rtl8367c_setAsicSdsReg(0, 0, 0x24, 0x942c)) != RT_ERR_OK) + return retVal; + if( (retVal = rtl8367c_setAsicSdsReg(0, 5, 0x21, 0x8dc3)) != RT_ERR_OK) + return retVal; + if ((retVal = rtl8367c_setAsicRegBits(0x1d92, 0x1f, 5)) != RT_ERR_OK) + return retVal; + + /*patch speed change sds0 100M*/ + if ((retVal = rtl8367c_setAsicRegBits(0x1d92, 0x1f, 0x1f)) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367c_getAsicSdsReg(0, 4, 0, ®Value)) != RT_ERR_OK) + return retVal; + regValue &= 0xFFFF0FFF; + regValue |= 0xb000; + if( (retVal = rtl8367c_setAsicSdsReg(0, 4, 0, regValue)) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367c_getAsicSdsReg(0, 0, 2, ®Value)) != RT_ERR_OK) + return retVal; + regValue &= 0xFFFFFFBF; + regValue |= 0x2000; + if( (retVal = rtl8367c_setAsicSdsReg(0, 0, 2, regValue)) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367c_getAsicSdsReg(0, 4, 0, ®Value)) != RT_ERR_OK) + return retVal; + regValue &= 0xFFFFEFFF; + if( (retVal = rtl8367c_setAsicSdsReg(0, 4, 0, regValue)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicRegBits(0x1d92, 0x1f, 5)) != RT_ERR_OK) + return retVal; + if ((retVal = rtl8367c_setAsicRegBits(0x1d92, 0xe0, 0)) != RT_ERR_OK) + return retVal; + } + } + else if (mode == EXT_1000X_100FX) + { + if (id == 1) + { + if( (retVal = rtl8367c_setAsicSdsReg(1, 1, 0x21, 0xec91)) != RT_ERR_OK) + return retVal; + if( (retVal = rtl8367c_setAsicSdsReg(1, 5, 0x24, 0x5825)) != RT_ERR_OK) + return retVal; + if( (retVal = rtl8367c_setAsicSdsReg(1, 13, 0, 0x4616)) != RT_ERR_OK) + return retVal; + if( (retVal = rtl8367c_setAsicSdsReg(1, 1, 0, 0xf20)) != RT_ERR_OK) + return retVal; + if ((retVal = rtl8367c_setAsicRegBits(0x1d92, 0x1f00, 7)) != RT_ERR_OK) + return retVal; + } + else if (id == 2) + { + if( (retVal = rtl8367c_setAsicSdsReg(0, 0, 0x28, 0x942c)) != RT_ERR_OK) + return retVal; + if( (retVal = rtl8367c_setAsicSdsReg(0, 0, 0x24, 0x942c)) != RT_ERR_OK) + return retVal; + if( (retVal = rtl8367c_setAsicSdsReg(0, 5, 0x21, 0x8dc3)) != RT_ERR_OK) + return retVal; + if( (retVal = rtl8367c_setAsicSdsReg(0, 13, 0, 0x4616)) != RT_ERR_OK) + return retVal; + if( (retVal = rtl8367c_setAsicSdsReg(0, 1, 0, 0xf20)) != RT_ERR_OK) + return retVal; + if ((retVal = rtl8367c_setAsicRegBits(0x1d92, 0x1f, 7)) != RT_ERR_OK) + return retVal; + } + } + + } + else if (3 == type) + { + + /*restore patch, by designer. patch Tx FIFO issue, when not HSGMII 2.5G mode + #sds0, page 1, reg 1, bit4=0*/ + if( (retVal = rtl8367c_getAsicSdsReg(0, 1, 1, ®Value)) != RT_ERR_OK) + return retVal; + regValue &= 0xFFFFFFEF; + if( (retVal = rtl8367c_setAsicSdsReg(0, 1, 1, regValue)) != RT_ERR_OK) + return retVal; + + /*set for mac 6*/ + if (1 == id) + { + + if ((retVal = rtl8367c_setAsicReg(0x137c, 0x1000)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_getAsicRegBit(0x1d9d, 6, ®_data)) != RT_ERR_OK) + return retVal; + while(reg_data == 0) + { + if ((retVal = rtl8367c_getAsicRegBit(0x1d9d, 6, ®_data)) != RT_ERR_OK) + return retVal; + } + + if (mode == EXT_SGMII) + { + + if ((retVal = rtl8367c_getAsicRegBit(0x1d3d, 10, ®_data)) != RT_ERR_OK) + return retVal; + if(reg_data == 0) + { + if ((retVal = rtl8367c_setAsicRegBits(0x1305, 0xf0, 0)) != RT_ERR_OK) + return retVal; + } + + if ((retVal = rtl8367c_setAsicRegBit(0x3f7, 1, 0)) != RT_ERR_OK) + return retVal; + + + + + if ((retVal = rtl8367c_setAsicRegBit(0x1d41, 5, 0)) != RT_ERR_OK) + return retVal; + if ((retVal = rtl8367c_setAsicRegBit(0x1d41, 7, 0)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBit(0x1d95, 1, 0)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBit(0x1d95, 0, 0)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBit(0x1d11, 9, 0)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBit(0x1d11, 11, 0)) != RT_ERR_OK) + return retVal; + + + + if ((retVal = rtl8367c_setAsicRegBit(0x1d95, 13, 1)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBits(0x1d95, 0x1f00, 0x1f)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBit(0x1d11, 6, 1)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBits(0x1d95, 0x1f00, 0x2)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicRegBit(0x1d95, 2, 0)) != RT_ERR_OK) + return retVal; + + + } + else if (mode == EXT_HSGMII) + { + + /*restore patch, by designer. patch Tx FIFO issue, when HSGMII 2.5G mode + #sds0, page 1, reg 1, bit4=1*/ + if( (retVal = rtl8367c_getAsicSdsReg(0, 1, 1, ®Value)) != RT_ERR_OK) + return retVal; + regValue |= 0x10; + if( (retVal = rtl8367c_setAsicSdsReg(0, 1, 1, regValue)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_getAsicRegBit(0x1d3d, 10, ®_data)) != RT_ERR_OK) + return retVal; + if(reg_data == 0) + { + if ((retVal = rtl8367c_setAsicRegBits(0x1305, 0xf0, 0)) != RT_ERR_OK) + return retVal; + } + + if ((retVal = rtl8367c_setAsicRegBit(0x3f7, 1, 0)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBit(0x1d41, 5, 0)) != RT_ERR_OK) + return retVal; + if ((retVal = rtl8367c_setAsicRegBit(0x1d41, 7, 0)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBit(0x1d95, 1, 0)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBit(0x1d95, 0, 0)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBit(0x1d11, 9, 0)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBit(0x1d11, 11, 1)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicRegBit(0x1d11, 6, 0)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicReg(0xd0,7)) != RT_ERR_OK) + return retVal; + if ((retVal = rtl8367c_setAsicReg(0x399, 7)) != RT_ERR_OK) + return retVal; + if ((retVal = rtl8367c_setAsicReg(0x3fa, 7)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBit(0x1d95, 13, 1)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicRegBits(0x1d95, 0x1f00, 0x12)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicRegBit(0x1d95, 2, 0)) != RT_ERR_OK) + return retVal; + + } + else if(mode == EXT_1000X) + { + + if((retVal = rtl8367c_getAsicSdsReg(0, 2, 0, ®_data)) != RT_ERR_OK) + return retVal; + reg_data &= 0xFFFFFCFF; + if((retVal = rtl8367c_setAsicSdsReg(0,2,0, reg_data)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_getAsicRegBit(0x1d3d, 10, ®_data)) != RT_ERR_OK) + return retVal; + if(reg_data == 0) + { + if ((retVal = rtl8367c_setAsicRegBits(0x1305, 0xf0, 0)) != RT_ERR_OK) + return retVal; + } + + if ((retVal = rtl8367c_setAsicRegBit(0x3f7, 1, 0)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicReg(0x1d11, 0x1500)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBits(0x1d95, 0x1f00, 0x1f)) != RT_ERR_OK) + return retVal; + if ((retVal = rtl8367c_setAsicRegBit(0x1d95, 13, 1)) != RT_ERR_OK) + return retVal; + if ((retVal = rtl8367c_setAsicRegBits(0x1d95, 3, 0)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicReg(0x13eb, 0x15bb)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicReg(0x13e7, 0xc)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBit(0x1d41, 5, 1)) != RT_ERR_OK) + return retVal; + if ((retVal = rtl8367c_setAsicRegBit(0x1d41, 7, 1)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBit(0x1d11, 11, 0)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBit(0x1d11, 6, 1)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicRegBits(0x1d95, 0x1f00, 0x4)) != RT_ERR_OK) + return retVal; + } + else if(mode == EXT_100FX) + { + + if((retVal = rtl8367c_getAsicSdsReg(0, 2, 0, ®_data)) != RT_ERR_OK) + return retVal; + reg_data &= 0xFFFFFCFF; + if((retVal = rtl8367c_setAsicSdsReg(0,2,0, reg_data)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_getAsicRegBit(0x1d3d, 10, ®_data)) != RT_ERR_OK) + return retVal; + if(reg_data == 0) + { + if ((retVal = rtl8367c_setAsicRegBits(0x1305, 0xf0, 0)) != RT_ERR_OK) + return retVal; + } + + if ((retVal = rtl8367c_setAsicRegBit(0x3f7, 1, 0)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicReg(0x1d11, 0x1500)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBits(0x1d95, 0x1f00, 0x1f)) != RT_ERR_OK) + return retVal; + if ((retVal = rtl8367c_setAsicRegBit(0x1d95, 13, 1)) != RT_ERR_OK) + return retVal; + if ((retVal = rtl8367c_setAsicRegBits(0x1d95, 3, 0)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicReg(0x13eb, 0x15bb)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicReg(0x13e7, 0xc)) != RT_ERR_OK) + return retVal; + + + + if ((retVal = rtl8367c_setAsicRegBit(0x1d41, 5, 1)) != RT_ERR_OK) + return retVal; + if ((retVal = rtl8367c_setAsicRegBit(0x1d41, 7, 1)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBit(0x1d11, 11, 0)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBit(0x1d11, 6, 1)) != RT_ERR_OK) + return retVal; + + + + if ((retVal = rtl8367c_setAsicRegBits(0x1d95, 0x1f00, 0x5)) != RT_ERR_OK) + return retVal; + } + else if(mode == EXT_1000X_100FX) + { + /* 0 2 0 bit 8~9 set 0, force n-way*/ + if((retVal = rtl8367c_getAsicSdsReg(0, 2, 0, ®_data)) != RT_ERR_OK) + return retVal; + reg_data &= 0xFFFFFCFF; + if((retVal = rtl8367c_setAsicSdsReg(0,2,0, reg_data)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_getAsicRegBit(0x1d3d, 10, ®_data)) != RT_ERR_OK) + return retVal; + if(reg_data == 0) + { + if ((retVal = rtl8367c_setAsicRegBits(0x1305, 0xf0, 0)) != RT_ERR_OK) + return retVal; + } + + if ((retVal = rtl8367c_setAsicRegBit(0x3f7, 1, 0)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicReg(0x1d11, 0x1500)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBits(0x1d95, 0x1f00, 0x1f)) != RT_ERR_OK) + return retVal; + if ((retVal = rtl8367c_setAsicRegBit(0x1d95, 13, 0)) != RT_ERR_OK) + return retVal; + if ((retVal = rtl8367c_setAsicRegBits(0x1d95, 3, 0)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicReg(0x13eb, 0x15bb)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicReg(0x13e7, 0xc)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBit(0x1d41, 5, 1)) != RT_ERR_OK) + return retVal; + if ((retVal = rtl8367c_setAsicRegBit(0x1d41, 7, 1)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBit(0x1d11, 11, 0)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBit(0x1d11, 6, 1)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBits(0x1d95, 0x1f00, 0x7)) != RT_ERR_OK) + return retVal; + } + else if(mode < EXT_SGMII) + { + if ((retVal = rtl8367c_setAsicRegBit(0x1d3d, 10, 0)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicRegBit(0x3f7, 1, 0)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBit(0x1d11, 11, 0)) != RT_ERR_OK) + return retVal; + if ((retVal = rtl8367c_setAsicRegBit(0x1d11, 6, 0)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBit(0x1d41, 5, 0)) != RT_ERR_OK) + return retVal; + if ((retVal = rtl8367c_setAsicRegBit(0x1d41, 7, 0)) != RT_ERR_OK) + return retVal; + + if (mode < EXT_GMII) + { + /* set mac6 mode*/ + if ((retVal = rtl8367c_setAsicRegBits(0x1305, 0xf0, mode)) != RT_ERR_OK) + return retVal; + } + else if(mode == EXT_RMII_MAC) + { + + if ((retVal = rtl8367c_setAsicRegBits(0x1305, 0xf0, 7)) != RT_ERR_OK) + return retVal; + } + else if(mode == EXT_RMII_PHY) + { + if ((retVal = rtl8367c_setAsicRegBits(0x1305, 0xf0, 8)) != RT_ERR_OK) + return retVal; + } + + if ((mode == EXT_TMII_MAC) || (mode == EXT_TMII_PHY)) + { + if ((retVal = rtl8367c_setAsicRegBit(0x3f7, 1, 1)) != RT_ERR_OK) + return retVal; + } + } + + } + else if (2 == id) + { + + /*force port7 linkdown*/ + if ((retVal = rtl8367c_setAsicReg(0x137d, 0x1000)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_getAsicRegBit(0x1d9d, 7, ®_data)) != RT_ERR_OK) + return retVal; + while(reg_data == 0) + { + if ((retVal = rtl8367c_getAsicRegBit(0x1d9d, 7, ®_data)) != RT_ERR_OK) + return retVal; + } + + if (mode == EXT_SGMII) + { + + if ((retVal = rtl8367c_setAsicRegBits(0x13c3, 0xf,0)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicReg(0x13c4, 0)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicRegBit(0x3f7, 2, 0)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBit(0x1d41, 5, 0)) != RT_ERR_OK) + return retVal; + if ((retVal = rtl8367c_setAsicRegBit(0x1d41, 7, 0)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBits(0x1d95, 3, 0)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBit(0x1d11, 11, 0)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBit(0x1d11, 6, 0)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBit(0x1d95, 13, 1)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBits(0x1d95, 0x1f00, 0x1f)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBit(0x1d95, 0, 1)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBits(0x1d95, 0x1f00, 0x2)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBit(0x1d95, 2, 0)) != RT_ERR_OK) + return retVal; + } + else if (mode == EXT_1000X) + { + + if ((retVal = rtl8367c_setAsicRegBits(0x13c3, 0xf, 0)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicReg(0x13c4, 0)) != RT_ERR_OK) + return retVal; + + + if((retVal = rtl8367c_getAsicSdsReg(0, 2, 0, ®_data)) != RT_ERR_OK) + return retVal; + reg_data &= 0xFFFFFCFF; + if((retVal = rtl8367c_setAsicSdsReg(0,2,0, reg_data)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBit(0x3f7, 2, 0)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicReg(0x1d11, 0x1500)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicRegBit(0x1d95, 13, 1)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBits(0x1d95, 0x1f00, 0x1f)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBit(0x1d41, 5, 0)) != RT_ERR_OK) + return retVal; + if ((retVal = rtl8367c_setAsicRegBit(0x1d41, 7, 0)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBits(0x1d95, 3, 3)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBits(0x1d95, 0x1f00, 0x4)) != RT_ERR_OK) + return retVal; + + } + else if (mode == EXT_100FX) + { + + if ((retVal = rtl8367c_setAsicRegBits(0x13c3, 0xf, 0)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicReg(0x13c4, 0)) != RT_ERR_OK) + return retVal; + + + if((retVal = rtl8367c_getAsicSdsReg(0, 2, 0, ®_data)) != RT_ERR_OK) + return retVal; + reg_data &= 0xFFFFFCFF; + if((retVal = rtl8367c_setAsicSdsReg(0,2,0, reg_data)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBit(0x3f7, 2, 0)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicReg(0x1d11, 0x1500)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBit(0x1d95, 13, 1)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBits(0x1d95, 0x1f00, 0x1f)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBit(0x1d41, 5, 0)) != RT_ERR_OK) + return retVal; + if ((retVal = rtl8367c_setAsicRegBit(0x1d41, 7, 0)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBits(0x1d95, 3, 3)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBits(0x1d95, 0x1f00, 0x5)) != RT_ERR_OK) + return retVal; + } + else if (mode == EXT_1000X_100FX) + { + /* disable mac7 MII/TMM/RMII/GMII/RGMII mode, mode_ext2 = disable */ + if ((retVal = rtl8367c_setAsicRegBits(0x13c3, 0xf, 0)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicReg(0x13c4, 0)) != RT_ERR_OK) + return retVal; + + + if((retVal = rtl8367c_getAsicSdsReg(0, 2, 0, ®_data)) != RT_ERR_OK) + return retVal; + reg_data &= 0xFFFFFCFF; + if((retVal = rtl8367c_setAsicSdsReg(0,2,0, reg_data)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBit(0x3f7, 2, 0)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicReg(0x1d11, 0x1500)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBit(0x1d95, 13, 1)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBits(0x1d95, 0x1f00, 0x1f)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBit(0x1d41, 5, 0)) != RT_ERR_OK) + return retVal; + if ((retVal = rtl8367c_setAsicRegBit(0x1d41, 7, 0)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBits(0x1d95, 3, 3)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBits(0x1d95, 0x1f00, 0x7)) != RT_ERR_OK) + return retVal; + } + else if (mode < EXT_SGMII) + { + if ((retVal = rtl8367c_setAsicRegBit(0x1d3d, 10, 0)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicRegBit(0x3f7, 2, 0)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicReg(0x1d95, 0x1f00)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBits(0x1d95, 3, 0)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBits(0x13c3, 0xf, mode)) != RT_ERR_OK) + return retVal; + + if ((mode == EXT_TMII_MAC) || (mode == EXT_TMII_PHY)) + { + if ((retVal = rtl8367c_setAsicRegBit(0x3f7, 2, 1)) != RT_ERR_OK) + return retVal; + } + + } + else if ((mode < EXT_END) && (mode > EXT_100FX)) + { + if ((retVal = rtl8367c_setAsicRegBits(0x13C3, 0xf, 0)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicRegBit(0x3f7, 2, 0)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8367c_setAsicRegBits(0x1d95, 3, 0)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicRegBit(0x1d3d, 10, 1)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_getAsicRegBit(0x1d11, 11, ®_data)) != RT_ERR_OK) + return retVal; + if(reg_data == 0) + { + if ((retVal = rtl8367c_setAsicRegBit(0x1d11, 6, 1)) != RT_ERR_OK) + return retVal; + } + + + if (mode < EXT_RMII_MAC_2) + { + if ((retVal = rtl8367c_setAsicRegBits(0x1305, 0xf0, (mode-13))) != RT_ERR_OK) + return retVal; + } + else + { + if ((retVal = rtl8367c_setAsicRegBits(0x1305, 0xf0, (mode-12))) != RT_ERR_OK) + return retVal; + } + + if ((mode == EXT_TMII_MAC_2) || (mode == EXT_TMII_PHY_2)) + { + if ((retVal = rtl8367c_setAsicRegBit(0x3f7, 2, 1)) != RT_ERR_OK) + return retVal; + } + } + + } + + } + return RT_ERR_OK; +} +/* Function Name: + * rtl8367c_getAsicPortExtMode + * Description: + * Get external interface mode configuration + * Input: + * id - external interface id (0~1) + * pMode - external interface mode + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - input parameter out of range + * Note: + * None + */ +ret_t rtl8367c_getAsicPortExtMode(rtk_uint32 id, rtk_uint32 *pMode) +{ + ret_t retVal; + rtk_uint32 regData, regValue, type; + + if(id >= RTL8367C_EXTNO) + return RT_ERR_OUT_OF_RANGE; + + if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0249)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_getAsicReg(0x1300, ®Value)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0000)) != RT_ERR_OK) + return retVal; + + type = 0; + + switch (regValue) + { + case 0x0276: + case 0x0597: + case 0x6367: + type = 1; + break; + case 0x0652: + case 0x6368: + type = 2; + break; + case 0x0801: + case 0x6511: + type = 3; + break; + default: + return RT_ERR_FAILED; + } + + + if (1 == type) + { + if(0 == id || 1 == id) + return rtl8367c_getAsicRegBits(RTL8367C_REG_DIGITAL_INTERFACE_SELECT, RTL8367C_SELECT_GMII_0_MASK << (id * RTL8367C_SELECT_GMII_1_OFFSET), pMode); + else + return rtl8367c_getAsicRegBits(RTL8367C_REG_DIGITAL_INTERFACE_SELECT_1, RTL8367C_SELECT_GMII_2_MASK, pMode); + } + else if (2 == type) + { + if (1 == id) + { + if ((retVal = rtl8367c_getAsicReg(0x1d92, ®Data))!=RT_ERR_OK) + return retVal; + + if (regData & 0x4000) + { + *pMode = EXT_SGMII; + return RT_ERR_OK; + } + + else if (((regData >> 8) & 0x1f) == 4) + { + *pMode = EXT_1000X; + return RT_ERR_OK; + } + else if (((regData >> 8) & 0x1f) == 5) + { + *pMode = EXT_100FX; + return RT_ERR_OK; + } + else if (((regData >> 8) & 0x1f) == 7) + { + *pMode = EXT_1000X_100FX; + return RT_ERR_OK; + } + + return rtl8367c_getAsicRegBits(0x1305, 0xf0, pMode); + } + else if (2 == id) + { +#if 0 + if ((retVal = rtl8367c_getAsicRegBit(0x1d92, 6, ®Data))!=RT_ERR_OK) + return retVal; + + if (regData == 1) + { + *pMode = EXT_SGMII; + return RT_ERR_OK; + } + + if ((retVal = rtl8367c_getAsicRegBit(0x1d92, 7, ®Data))!=RT_ERR_OK) + return retVal; + + if (regData == 1) + { + *pMode = EXT_HSGMII; + return RT_ERR_OK; + } +#endif + if ((retVal = rtl8367c_getAsicReg(0x1d92, ®Data))!=RT_ERR_OK) + return retVal; + + if (regData & 0x40) + { + *pMode = EXT_SGMII; + return RT_ERR_OK; + } + else if (regData & 0x80) + { + *pMode = EXT_HSGMII; + return RT_ERR_OK; + } + else if ((regData & 0x1f) == 4) + { + *pMode = EXT_1000X; + return RT_ERR_OK; + } + else if ((regData & 0x1f) == 5) + { + *pMode = EXT_100FX; + return RT_ERR_OK; + } + else if ((regData & 0x1f) == 7) + { + *pMode = EXT_1000X_100FX; + return RT_ERR_OK; + } + + return rtl8367c_getAsicRegBits(0x13c3, 0xf, pMode); + } + } + else if(3 == type) + { + if (1 == id) + { + /* SDS_CFG_NEW */ + if ((retVal = rtl8367c_getAsicReg(0x1d95, ®Data))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_getAsicReg(0x1d41, ®Value))!=RT_ERR_OK) + return retVal; + + + if((regValue & 0xa0) == 0xa0 ) + { + + regData = regData >> 8; + if((regData & 0x1f) == 4) + { + *pMode = EXT_1000X; + return RT_ERR_OK; + } + else if((regData & 0x1f) == 5) + { + *pMode = EXT_100FX; + return RT_ERR_OK; + } + else if((regData & 0x1f) == 7) + { + *pMode = EXT_1000X_100FX; + return RT_ERR_OK; + } + + } + + + if ((retVal = rtl8367c_getAsicReg(0x1d11, ®Data))!=RT_ERR_OK) + return retVal; + + /* check cfg_mac6_sel_sgmii */ + if((regData >> 6) & 1) + { + *pMode = EXT_SGMII; + return RT_ERR_OK; + } + else if((regData >> 11) & 1) + { + *pMode = EXT_HSGMII; + return RT_ERR_OK; + } + else + { + /* check port6 MAC mode */ + if ((retVal = rtl8367c_getAsicRegBits(0x1305, 0xf0, ®Data))!=RT_ERR_OK) + return retVal; + + *pMode = regData; + return RT_ERR_OK; + } + } + else if (2 == id) + { + if ((retVal = rtl8367c_getAsicReg(0x1d95, ®Data))!=RT_ERR_OK) + return retVal; + + + if(((regData & 0x3) == 3) && (((regData >> 8) & 0x1f) == 0x4)) + { + *pMode = EXT_1000X; + return RT_ERR_OK; + } + else if (((regData & 0x3) == 3) && (((regData >> 8) & 0x1f) == 0x5)) + { + *pMode = EXT_100FX; + return RT_ERR_OK; + } + else if (((regData & 0x3) == 3) && (((regData >> 8) & 0x1f) == 0x7)) + { + *pMode = EXT_1000X_100FX; + return RT_ERR_OK; + } + else if(regData & 1) + { + *pMode = EXT_SGMII; + return RT_ERR_OK; + } + else + { + + if ((retVal = rtl8367c_getAsicRegBits(0x13c3, 0xf, ®Data))!=RT_ERR_OK) + return retVal; + + *pMode = regData; + + return RT_ERR_OK; + } + } + } + + return RT_ERR_OK; +} + +/* Function Name: + * rtl8370_setAsicPortEnableAll + * Description: + * Set ALL ports enable. + * Input: + * enable - enable all ports. + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicPortEnableAll(rtk_uint32 enable) +{ + if(enable >= 2) + return RT_ERR_INPUT; + + return rtl8367c_setAsicRegBit(RTL8367C_REG_PHY_AD, RTL8367C_PDNPHY_OFFSET, !enable); +} + +/* Function Name: + * rtl8367c_getAsicPortEnableAll + * Description: + * Set ALL ports enable. + * Input: + * enable - enable all ports. + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicPortEnableAll(rtk_uint32 *pEnable) +{ + ret_t retVal; + rtk_uint32 regData; + + retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_PHY_AD, RTL8367C_PDNPHY_OFFSET, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + if (regData==0) + *pEnable = 1; + else + *pEnable = 0; + + return RT_ERR_OK; +} +/* Function Name: + * rtl8367c_setAsicPortSmallIpg + * Description: + * Set small ipg egress mode + * Input: + * port - Physical port number (0~7) + * enable - 0: normal, 1: small + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_setAsicPortSmallIpg(rtk_uint32 port, rtk_uint32 enable) +{ + if(port >= RTL8367C_PORTNO) + return RT_ERR_PORT_ID; + + return rtl8367c_setAsicRegBit(RTL8367C_PORT_SMALL_IPG_REG(port), RTL8367C_PORT0_MISC_CFG_SMALL_TAG_IPG_OFFSET, enable); +} + +/* Function Name: + * rtl8367c_getAsicPortSmallIpg + * Description: + * Get small ipg egress mode + * Input: + * port - Physical port number (0~7) + * pEnable - 0: normal, 1: small + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_getAsicPortSmallIpg(rtk_uint32 port, rtk_uint32* pEnable) +{ + if(port >= RTL8367C_PORTNO) + return RT_ERR_PORT_ID; + + return rtl8367c_getAsicRegBit(RTL8367C_PORT_SMALL_IPG_REG(port), RTL8367C_PORT0_MISC_CFG_SMALL_TAG_IPG_OFFSET, pEnable); +} + +/* Function Name: + * rtl8367c_setAsicPortLoopback + * Description: + * Set MAC loopback + * Input: + * port - Physical port number (0~7) + * enable - 0: Disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_setAsicPortLoopback(rtk_uint32 port, rtk_uint32 enable) +{ + if(port >= RTL8367C_PORTNO) + return RT_ERR_PORT_ID; + + return rtl8367c_setAsicRegBit(RTL8367C_PORT_MISC_CFG_REG(port), RTL8367C_PORT0_MISC_CFG_MAC_LOOPBACK_OFFSET, enable); +} + +/* Function Name: + * rtl8367c_getAsicPortLoopback + * Description: + * Set MAC loopback + * Input: + * port - Physical port number (0~7) + * Output: + * pEnable - 0: Disable, 1: enable + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_getAsicPortLoopback(rtk_uint32 port, rtk_uint32 *pEnable) +{ + if(port >= RTL8367C_PORTNO) + return RT_ERR_PORT_ID; + + return rtl8367c_getAsicRegBit(RTL8367C_PORT_MISC_CFG_REG(port), RTL8367C_PORT0_MISC_CFG_MAC_LOOPBACK_OFFSET, pEnable); +} + +/* Function Name: + * rtl8367c_setAsicPortRTCTEnable + * Description: + * Set RTCT Enable echo response mode + * Input: + * portmask - Port mask of RTCT enabled (0-4) + * Output: + * None. + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Invalid port mask + * Note: + * RTCT test takes 4.8 seconds at most. + */ +ret_t rtl8367c_setAsicPortRTCTEnable(rtk_uint32 portmask) +{ + ret_t retVal; + rtk_uint32 regData; + rtk_uint32 port; + + if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0249)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_getAsicReg(0x1300, ®Data)) != RT_ERR_OK) + return retVal; + + if( (regData == 0x0276) || (regData == 0x0597) ) + return RT_ERR_CHIP_NOT_SUPPORTED; + + for(port = 0; port <= 10 ; port++) + { + if(portmask & (0x0001 << port)) + { + if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xa422, ®Data)) != RT_ERR_OK) + return retVal; + + regData &= 0x7FFF; + if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xa422, regData)) != RT_ERR_OK) + return retVal; + + regData |= 0x00F2;/*RTCT set to echo response mode*/ + if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xa422, regData)) != RT_ERR_OK) + return retVal; + + regData |= 0x0001; + if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xa422, regData)) != RT_ERR_OK) + return retVal; + } + } + + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_setAsicPortRTCTDisable + * Description: + * Set RTCT Disable + * Input: + * portmask - Port mask of RTCT enabled (0-4) + * Output: + * None. + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Invalid port mask + * Note: + * RTCT test takes 4.8 seconds at most. + */ +ret_t rtl8367c_setAsicPortRTCTDisable(rtk_uint32 portmask) +{ + ret_t retVal; + rtk_uint32 regData; + rtk_uint32 port; + + if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0249)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_getAsicReg(0x1300, ®Data)) != RT_ERR_OK) + return retVal; + + if( (regData == 0x0276) || (regData == 0x0597) ) + return RT_ERR_CHIP_NOT_SUPPORTED; + + for(port = 0; port <= 10 ; port++) + { + if(portmask & (0x0001 << port)) + { + if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xa422, ®Data)) != RT_ERR_OK) + return retVal; + + regData &= 0x7FFF; + if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xa422, regData)) != RT_ERR_OK) + return retVal; + + regData |= 0x00F0; + if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xa422, regData)) != RT_ERR_OK) + return retVal; + + regData &= ~0x0001; + if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xa422, regData)) != RT_ERR_OK) + return retVal; + } + } + + return RT_ERR_OK; +} + + +/* Function Name: + * rtl8367c_getAsicPortRTCTResult + * Description: + * Get RTCT result + * Input: + * port - Port ID of RTCT result + * Output: + * pResult - The result of port ID + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Invalid port mask + * RT_ERR_PHY_RTCT_NOT_FINISH - RTCT test doesn't finish. + * Note: + * RTCT test takes 4.8 seconds at most. + * If this API returns RT_ERR_PHY_RTCT_NOT_FINISH, + * users should wait a whole then read it again. + */ +ret_t rtl8367c_getAsicPortRTCTResult(rtk_uint32 port, rtl8367c_port_rtct_result_t *pResult) +{ + ret_t retVal; + rtk_uint32 regData, finish = 1; + + if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0249)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_getAsicReg(0x1300, ®Data)) != RT_ERR_OK) + return retVal; + + if( (regData == 0x6367) ) + { + if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xa422, ®Data)) != RT_ERR_OK) + return retVal; + + if((regData & 0x8000) == 0x8000) + { + /* Channel A */ + if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xa436, 0x802a)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xa438, ®Data)) != RT_ERR_OK) + return retVal; + + pResult->channelAOpen = (regData == 0x0048) ? 1 : 0; + pResult->channelAShort = (regData == 0x0050) ? 1 : 0; + pResult->channelAMismatch = ((regData == 0x0042) || (regData == 0x0044)) ? 1 : 0; + pResult->channelALinedriver = (regData == 0x0041) ? 1 : 0; + + /* Channel B */ + if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xa436, 0x802e)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xa438, ®Data)) != RT_ERR_OK) + return retVal; + + pResult->channelBOpen = (regData == 0x0048) ? 1 : 0; + pResult->channelBShort = (regData == 0x0050) ? 1 : 0; + pResult->channelBMismatch = ((regData == 0x0042) || (regData == 0x0044)) ? 1 : 0; + pResult->channelBLinedriver = (regData == 0x0041) ? 1 : 0; + + /* Channel C */ + if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xa436, 0x8032)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xa438, ®Data)) != RT_ERR_OK) + return retVal; + + pResult->channelCOpen = (regData == 0x0048) ? 1 : 0; + pResult->channelCShort = (regData == 0x0050) ? 1 : 0; + pResult->channelCMismatch = ((regData == 0x0042) || (regData == 0x0044)) ? 1 : 0; + pResult->channelCLinedriver = (regData == 0x0041) ? 1 : 0; + + /* Channel D */ + if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xa436, 0x8036)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xa438, ®Data)) != RT_ERR_OK) + return retVal; + + pResult->channelDOpen = (regData == 0x0048) ? 1 : 0; + pResult->channelDShort = (regData == 0x0050) ? 1 : 0; + pResult->channelDMismatch = ((regData == 0x0042) || (regData == 0x0044)) ? 1 : 0; + pResult->channelDLinedriver = (regData == 0x0041) ? 1 : 0; + + /* Channel A Length */ + if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xa436, 0x802c)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xa438, ®Data)) != RT_ERR_OK) + return retVal; + + pResult->channelALen = (regData / 2); + + /* Channel B Length */ + if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xa436, 0x8030)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xa438, ®Data)) != RT_ERR_OK) + return retVal; + + pResult->channelBLen = (regData / 2); + + /* Channel C Length */ + if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xa436, 0x8034)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xa438, ®Data)) != RT_ERR_OK) + return retVal; + + pResult->channelCLen = (regData / 2); + + /* Channel D Length */ + if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xa436, 0x8038)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xa438, ®Data)) != RT_ERR_OK) + return retVal; + + pResult->channelDLen = (regData / 2); + } + else + finish = 0; + } + else if(regData == 0x6368) + { + if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xa422, ®Data)) != RT_ERR_OK) + return retVal; + + if((regData & 0x8000) == 0x8000) + { + /* Channel A */ + if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xa436, 0x802b)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xa438, ®Data)) != RT_ERR_OK) + return retVal; + + pResult->channelAOpen = (regData == 0x0048) ? 1 : 0; + pResult->channelAShort = (regData == 0x0050) ? 1 : 0; + pResult->channelAMismatch = ((regData == 0x0042) || (regData == 0x0044)) ? 1 : 0; + pResult->channelALinedriver = (regData == 0x0041) ? 1 : 0; + + /* Channel B */ + if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xa436, 0x802f)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xa438, ®Data)) != RT_ERR_OK) + return retVal; + + pResult->channelBOpen = (regData == 0x0048) ? 1 : 0; + pResult->channelBShort = (regData == 0x0050) ? 1 : 0; + pResult->channelBMismatch = ((regData == 0x0042) || (regData == 0x0044)) ? 1 : 0; + pResult->channelBLinedriver = (regData == 0x0041) ? 1 : 0; + + /* Channel C */ + if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xa436, 0x8033)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xa438, ®Data)) != RT_ERR_OK) + return retVal; + + pResult->channelCOpen = (regData == 0x0048) ? 1 : 0; + pResult->channelCShort = (regData == 0x0050) ? 1 : 0; + pResult->channelCMismatch = ((regData == 0x0042) || (regData == 0x0044)) ? 1 : 0; + pResult->channelCLinedriver = (regData == 0x0041) ? 1 : 0; + + /* Channel D */ + if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xa436, 0x8037)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xa438, ®Data)) != RT_ERR_OK) + return retVal; + + pResult->channelDOpen = (regData == 0x0048) ? 1 : 0; + pResult->channelDShort = (regData == 0x0050) ? 1 : 0; + pResult->channelDMismatch = ((regData == 0x0042) || (regData == 0x0044)) ? 1 : 0; + pResult->channelDLinedriver = (regData == 0x0041) ? 1 : 0; + + /* Channel A Length */ + if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xa436, 0x802d)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xa438, ®Data)) != RT_ERR_OK) + return retVal; + + pResult->channelALen = (regData / 2); + + /* Channel B Length */ + if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xa436, 0x8031)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xa438, ®Data)) != RT_ERR_OK) + return retVal; + + pResult->channelBLen = (regData / 2); + + /* Channel C Length */ + if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xa436, 0x8035)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xa438, ®Data)) != RT_ERR_OK) + return retVal; + + pResult->channelCLen = (regData / 2); + + /* Channel D Length */ + if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xa436, 0x8039)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xa438, ®Data)) != RT_ERR_OK) + return retVal; + + pResult->channelDLen = (regData / 2); + } + else + finish = 0; + + } + else if((regData == 0x6511) || (regData == 0x0801)) + { + if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xa422, ®Data)) != RT_ERR_OK) + return retVal; + + if((regData & 0x8000) == 0x8000) + { + /* Channel A */ + if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xa436, 0x802a)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xa438, ®Data)) != RT_ERR_OK) + return retVal; + + pResult->channelAOpen = (regData == 0x0048) ? 1 : 0; + pResult->channelAShort = (regData == 0x0050) ? 1 : 0; + pResult->channelAMismatch = ((regData == 0x0042) || (regData == 0x0044)) ? 1 : 0; + pResult->channelALinedriver = (regData == 0x0041) ? 1 : 0; + + /* Channel B */ + if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xa436, 0x802e)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xa438, ®Data)) != RT_ERR_OK) + return retVal; + + pResult->channelBOpen = (regData == 0x0048) ? 1 : 0; + pResult->channelBShort = (regData == 0x0050) ? 1 : 0; + pResult->channelBMismatch = ((regData == 0x0042) || (regData == 0x0044)) ? 1 : 0; + pResult->channelBLinedriver = (regData == 0x0041) ? 1 : 0; + + /* Channel C */ + if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xa436, 0x8032)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xa438, ®Data)) != RT_ERR_OK) + return retVal; + + pResult->channelCOpen = (regData == 0x0048) ? 1 : 0; + pResult->channelCShort = (regData == 0x0050) ? 1 : 0; + pResult->channelCMismatch = ((regData == 0x0042) || (regData == 0x0044)) ? 1 : 0; + pResult->channelCLinedriver = (regData == 0x0041) ? 1 : 0; + + /* Channel D */ + if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xa436, 0x8036)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xa438, ®Data)) != RT_ERR_OK) + return retVal; + + pResult->channelDOpen = (regData == 0x0048) ? 1 : 0; + pResult->channelDShort = (regData == 0x0050) ? 1 : 0; + pResult->channelDMismatch = ((regData == 0x0042) || (regData == 0x0044)) ? 1 : 0; + pResult->channelDLinedriver = (regData == 0x0041) ? 1 : 0; + + /* Channel A Length */ + if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xa436, 0x802c)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xa438, ®Data)) != RT_ERR_OK) + return retVal; + + pResult->channelALen = (regData / 2); + + /* Channel B Length */ + if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xa436, 0x8030)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xa438, ®Data)) != RT_ERR_OK) + return retVal; + + pResult->channelBLen = (regData / 2); + + /* Channel C Length */ + if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xa436, 0x8034)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xa438, ®Data)) != RT_ERR_OK) + return retVal; + + pResult->channelCLen = (regData / 2); + + /* Channel D Length */ + if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xa436, 0x8038)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xa438, ®Data)) != RT_ERR_OK) + return retVal; + + pResult->channelDLen = (regData / 2); + } + else + finish = 0; + + } + else + return RT_ERR_CHIP_NOT_SUPPORTED; + + if(finish == 0) + return RT_ERR_PHY_RTCT_NOT_FINISH; + else + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_sdsReset + * Description: + * Reset Serdes + * Input: + * id - EXT ID + * Output: + * None. + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None. + */ +ret_t rtl8367c_sdsReset(rtk_uint32 id) +{ + rtk_uint32 retVal, regValue, state, i, option, running = 0, retVal2; + + if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0249)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_getAsicReg(0x1300, ®Value)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0000)) != RT_ERR_OK) + return retVal; + + switch (regValue) + { + case 0x0276: + case 0x0597: + case 0x6367: + option = 0; + break; + case 0x0652: + case 0x6368: + option = 1; + break; + case 0x0801: + case 0x6511: + option = 2; + break; + default: + return RT_ERR_FAILED; + } + + if(option == 0) + { + if (1 == id) + { + if ((retVal = rtl8367c_getAsicRegBit(0x130c, 5, &running))!=RT_ERR_OK) + return retVal; + + if(running == 1) + { + if ((retVal = rtl8367c_setAsicRegBit(0x130c, 5, 0))!=RT_ERR_OK) + return retVal; + } + + retVal = rtl8367c_setAsicReg(0x6601, 0x0000); + + if(retVal == RT_ERR_OK) + retVal = rtl8367c_setAsicReg(0x6602, 0x1401); + + if(retVal == RT_ERR_OK) + retVal = rtl8367c_setAsicReg(0x6600, 0x00C0); + + if(retVal == RT_ERR_OK) + retVal = rtl8367c_setAsicReg(0x6601, 0x0000); + + if(retVal == RT_ERR_OK) + retVal = rtl8367c_setAsicReg(0x6602, 0x1403); + + if(retVal == RT_ERR_OK) + retVal = rtl8367c_setAsicReg(0x6600, 0x00C0); + + if(running == 1) + { + if ((retVal2 = rtl8367c_setAsicRegBit(0x130c, 5, 1))!=RT_ERR_OK) + return retVal2; + } + + if(retVal != RT_ERR_OK) + return retVal; + } + else + return RT_ERR_PORT_ID; + } + else if(option == 1) + { + if (1 == id) + { + if((retVal = rtl8367c_getAsicReg(0x1311, &state)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicReg(0x1311, 0x66)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicReg(0x1311, 0x1066)) != RT_ERR_OK) + return retVal; + + while(1) + { + if((retVal = rtl8367c_getAsicReg(0x1d9d, ®Value)) != RT_ERR_OK) + return retVal; + if((regValue >> 8) & 1) + break; + } + + for (i=0; i<0xffff; i++); + + if((retVal = rtl8367c_setAsicReg(0x133d, 0x2)) != RT_ERR_OK) + return retVal; + + for (i=0; i<0xffff; i++); + + if((retVal = rtl8367c_setAsicReg(0x6601, 0x0)) != RT_ERR_OK) + return retVal; + if((retVal = rtl8367c_setAsicReg(0x6602, 0x1401)) != RT_ERR_OK) + return retVal; + if((retVal = rtl8367c_setAsicReg(0x6600, 0xc1)) != RT_ERR_OK) + return retVal; + if((retVal = rtl8367c_setAsicReg(0x6601, 0x0)) != RT_ERR_OK) + return retVal; + if((retVal = rtl8367c_setAsicReg(0x6602, 0x1403)) != RT_ERR_OK) + return retVal; + if((retVal = rtl8367c_setAsicReg(0x6600, 0xc1)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicReg(0x133d, 0x0)) != RT_ERR_OK) + return retVal; + + for (i=0; i<0xffff; i++); + + if((retVal = rtl8367c_setAsicReg(0x1311, state)) != RT_ERR_OK) + return retVal; + + + } + else if (2== id) + { + if((retVal = rtl8367c_getAsicReg(0x13c4, &state)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicReg(0x13c4, 0x66)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicReg(0x13c4, 0x1066)) != RT_ERR_OK) + return retVal; + + while(1) + { + if((retVal = rtl8367c_getAsicReg(0x1d9d, ®Value)) != RT_ERR_OK) + return retVal; + if((regValue >> 9) & 1) + break; + } + + for (i=0; i<0xffff; i++); + + if((retVal = rtl8367c_setAsicReg(0x133d, 0x2)) != RT_ERR_OK) + return retVal; + + for (i=0; i<0xffff; i++); + + if((retVal = rtl8367c_setAsicReg(0x6601, 0x0)) != RT_ERR_OK) + return retVal; + if((retVal = rtl8367c_setAsicReg(0x6602, 0x1401)) != RT_ERR_OK) + return retVal; + if((retVal = rtl8367c_setAsicReg(0x6600, 0xc0)) != RT_ERR_OK) + return retVal; + if((retVal = rtl8367c_setAsicReg(0x6601, 0x0)) != RT_ERR_OK) + return retVal; + if((retVal = rtl8367c_setAsicReg(0x6602, 0x1403)) != RT_ERR_OK) + return retVal; + if((retVal = rtl8367c_setAsicReg(0x6600, 0xc0)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicReg(0x133d, 0x0)) != RT_ERR_OK) + return retVal; + + for (i=0; i<0xffff; i++); + + if((retVal = rtl8367c_setAsicReg(0x13c4, state)) != RT_ERR_OK) + return retVal; + } + else + return RT_ERR_PORT_ID; + } + else if(option == 2) + { + if ((retVal = rtl8367c_getAsicSdsReg(0, 3, 0, ®Value))!=RT_ERR_OK) + return retVal; + regValue |= 0x40; + if ((retVal = rtl8367c_setAsicSdsReg(0, 3, 0, regValue))!=RT_ERR_OK) + return retVal; + + for (i=0; i<0xffff; i++); + + regValue &= ~(0x40); + if ((retVal = rtl8367c_setAsicSdsReg(0, 3, 0, regValue))!=RT_ERR_OK) + return retVal; + + } + + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_getSdsLinkStatus + * Description: + * Get SGMII status + * Input: + * id - EXT ID + * Output: + * None. + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None. + */ +ret_t rtl8367c_getSdsLinkStatus(rtk_uint32 ext_id, rtk_uint32 *pSignalDetect, rtk_uint32 *pSync, rtk_uint32 *pLink) +{ + rtk_uint32 retVal, regValue, type, running = 0, retVal2; + + + if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0249)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_getAsicReg(0x1300, ®Value)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0000)) != RT_ERR_OK) + return retVal; + + switch (regValue) + { + case 0x0276: + case 0x0597: + case 0x6367: + type = 0; + break; + case 0x0652: + case 0x6368: + type = 1; + break; + case 0x0801: + case 0x6511: + type = 2; + break; + default: + return RT_ERR_FAILED; + } + + if(type == 0) + { + if (1 == ext_id) + { + if ((retVal = rtl8367c_getAsicRegBit(0x130c, 5, &running))!=RT_ERR_OK) + return retVal; + + if(running == 1) + { + if ((retVal = rtl8367c_setAsicRegBit(0x130c, 5, 0))!=RT_ERR_OK) + return retVal; + } + + retVal = rtl8367c_setAsicReg(0x6601, 0x003D); + + if(retVal == RT_ERR_OK) + retVal = rtl8367c_setAsicReg(0x6600, 0x0080); + + if(retVal == RT_ERR_OK) + retVal = rtl8367c_getAsicReg(0x6602, ®Value); + + if(running == 1) + { + if ((retVal2 = rtl8367c_setAsicRegBit(0x130c, 5, 1))!=RT_ERR_OK) + return retVal2; + } + + if(retVal != RT_ERR_OK) + return retVal; + + *pSignalDetect = (regValue & 0x0100) ? 1 : 0; + *pSync = (regValue & 0x0001) ? 1 : 0; + *pLink = (regValue & 0x0010) ? 1 : 0; + } + else + return RT_ERR_PORT_ID; + } + else if(type == 1) + { + if (1 == ext_id) + { + if ((retVal = rtl8367c_setAsicReg(0x6601, 0x003D))!=RT_ERR_OK) + return retVal; + if ((retVal = rtl8367c_setAsicReg(0x6600, 0x0081))!=RT_ERR_OK) + return retVal; + if ((retVal = rtl8367c_getAsicReg(0x6602, ®Value))!=RT_ERR_OK) + return retVal; + + *pSignalDetect = (regValue & 0x0100) ? 1 : 0; + *pSync = (regValue & 0x0001) ? 1 : 0; + *pLink = (regValue & 0x0010) ? 1 : 0; + } + else if (2 == ext_id) + { + if ((retVal = rtl8367c_setAsicReg(0x6601, 0x003D))!=RT_ERR_OK) + return retVal; + if ((retVal = rtl8367c_setAsicReg(0x6600, 0x0080))!=RT_ERR_OK) + return retVal; + if ((retVal = rtl8367c_getAsicReg(0x6602, ®Value))!=RT_ERR_OK) + return retVal; + + *pSignalDetect = (regValue & 0x0100) ? 1 : 0; + *pSync = (regValue & 0x0001) ? 1 : 0; + *pLink = (regValue & 0x0010) ? 1 : 0; + } + else + return RT_ERR_PORT_ID; + } + else if(type == 2) + { + if((retVal = rtl8367c_getAsicSdsReg(0, 30, 1, ®Value)) != RT_ERR_OK) + return retVal; + if((retVal = rtl8367c_getAsicSdsReg(0, 30, 1, ®Value)) != RT_ERR_OK) + return retVal; + + *pSignalDetect = (regValue & 0x0100) ? 1 : 0; + *pSync = (regValue & 0x0001) ? 1 : 0; + *pLink = (regValue & 0x0010) ? 1 : 0; + + } + + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_setSgmiiNway + * Description: + * Set SGMII Nway + * Input: + * ext_id - EXT ID + * state - SGMII Nway state + * Output: + * None. + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None. + */ +ret_t rtl8367c_setSgmiiNway(rtk_uint32 ext_id, rtk_uint32 state) +{ + rtk_uint32 retVal, regValue, type, running = 0, retVal2; + + if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0249)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_getAsicReg(0x1300, ®Value)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0000)) != RT_ERR_OK) + return retVal; + + switch (regValue) + { + case 0x0276: + case 0x0597: + case 0x6367: + type = 0; + break; + case 0x0652: + case 0x6368: + type = 1; + break; + case 0x0801: + case 0x6511: + type = 2; + break; + default: + return RT_ERR_FAILED; + } + + if(type == 0) + { + if (1 == ext_id) + { + if ((retVal = rtl8367c_getAsicRegBit(0x130c, 5, &running))!=RT_ERR_OK) + return retVal; + + if(running == 1) + { + if ((retVal = rtl8367c_setAsicRegBit(0x130c, 5, 0))!=RT_ERR_OK) + return retVal; + } + + retVal = rtl8367c_setAsicReg(0x6601, 0x0002); + + if(retVal == RT_ERR_OK) + retVal = rtl8367c_setAsicReg(0x6600, 0x0080); + + if(retVal == RT_ERR_OK) + retVal = rtl8367c_getAsicReg(0x6602, ®Value); + + if(retVal == RT_ERR_OK) + { + if(state) + regValue |= 0x0200; + else + regValue &= ~0x0200; + + regValue |= 0x0100; + } + + if(retVal == RT_ERR_OK) + retVal = rtl8367c_setAsicReg(0x6602, regValue); + + if(retVal == RT_ERR_OK) + retVal = rtl8367c_setAsicReg(0x6601, 0x0002); + + if(retVal == RT_ERR_OK) + retVal = rtl8367c_setAsicReg(0x6600, 0x00C0); + + if(running == 1) + { + if ((retVal2 = rtl8367c_setAsicRegBit(0x130c, 5, 1))!=RT_ERR_OK) + return retVal2; + } + + if(retVal != RT_ERR_OK) + return retVal; + } + else + return RT_ERR_PORT_ID; + } + else if(type == 1) + { + if (1 == ext_id) + { + if ((retVal = rtl8367c_setAsicReg(0x6601, 0x0002))!=RT_ERR_OK) + return retVal; + if ((retVal = rtl8367c_setAsicReg(0x6600, 0x0081))!=RT_ERR_OK) + return retVal; + if ((retVal = rtl8367c_getAsicReg(0x6602, ®Value))!=RT_ERR_OK) + return retVal; + + if(state) + regValue |= 0x0200; + else + regValue &= ~0x0200; + + regValue |= 0x0100; + + if ((retVal = rtl8367c_setAsicReg(0x6602, regValue))!=RT_ERR_OK) + return retVal; + if ((retVal = rtl8367c_setAsicReg(0x6601, 0x0002))!=RT_ERR_OK) + return retVal; + if ((retVal = rtl8367c_setAsicReg(0x6600, 0x00C1))!=RT_ERR_OK) + return retVal; + } + else if (2 == ext_id) + { + if ((retVal = rtl8367c_setAsicReg(0x6601, 0x0002))!=RT_ERR_OK) + return retVal; + if ((retVal = rtl8367c_setAsicReg(0x6600, 0x0080))!=RT_ERR_OK) + return retVal; + if ((retVal = rtl8367c_getAsicReg(0x6602, ®Value))!=RT_ERR_OK) + return retVal; + + if(state) + regValue |= 0x0200; + else + regValue &= ~0x0200; + + regValue |= 0x0100; + + if ((retVal = rtl8367c_setAsicReg(0x6602, regValue))!=RT_ERR_OK) + return retVal; + if ((retVal = rtl8367c_setAsicReg(0x6601, 0x0002))!=RT_ERR_OK) + return retVal; + if ((retVal = rtl8367c_setAsicReg(0x6600, 0x00C0))!=RT_ERR_OK) + return retVal; + } + else + return RT_ERR_PORT_ID; + } + else if(type == 2) + { + if ((retVal = rtl8367c_getAsicSdsReg(0, 2, 0, ®Value))!=RT_ERR_OK) + return retVal; + + if(state & 1) + regValue &= ~0x100; + else + regValue |= 0x100; + + if ((retVal = rtl8367c_setAsicSdsReg(0, 2, 0, regValue))!=RT_ERR_OK) + return retVal; + } + + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_getSgmiiNway + * Description: + * Get SGMII Nway + * Input: + * ext_id - EXT ID + * state - SGMII Nway state + * Output: + * None. + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None. + */ +ret_t rtl8367c_getSgmiiNway(rtk_uint32 ext_id, rtk_uint32 *pState) +{ + rtk_uint32 retVal, regValue, type, running = 0, retVal2; + + if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0249)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_getAsicReg(0x1300, ®Value)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0000)) != RT_ERR_OK) + return retVal; + + switch (regValue) + { + case 0x0276: + case 0x0597: + case 0x6367: + type = 0; + break; + case 0x0652: + case 0x6368: + type = 1; + break; + case 0x0801: + case 0x6511: + type = 2; + break; + default: + return RT_ERR_FAILED; + } + + if(type == 0) + { + if (1 == ext_id) + { + if ((retVal = rtl8367c_getAsicRegBit(0x130c, 5, &running))!=RT_ERR_OK) + return retVal; + + if(running == 1) + { + if ((retVal = rtl8367c_setAsicRegBit(0x130c, 5, 0))!=RT_ERR_OK) + return retVal; + } + + retVal = rtl8367c_setAsicReg(0x6601, 0x0002); + + if(retVal == RT_ERR_OK) + retVal = rtl8367c_setAsicReg(0x6600, 0x0080); + + if(retVal == RT_ERR_OK) + retVal = rtl8367c_getAsicReg(0x6602, ®Value); + + if(running == 1) + { + if ((retVal2 = rtl8367c_setAsicRegBit(0x130c, 5, 1))!=RT_ERR_OK) + return retVal2; + } + + if(retVal != RT_ERR_OK) + return retVal; + + if(regValue & 0x0200) + *pState = 1; + else + *pState = 0; + } + else + return RT_ERR_PORT_ID; + } + else if(type == 1) + { + if (1 == ext_id) + { + if ((retVal = rtl8367c_setAsicReg(0x6601, 0x0002))!=RT_ERR_OK) + return retVal; + if ((retVal = rtl8367c_setAsicReg(0x6600, 0x0081))!=RT_ERR_OK) + return retVal; + if ((retVal = rtl8367c_getAsicReg(0x6602, ®Value))!=RT_ERR_OK) + return retVal; + + if(regValue & 0x0200) + *pState = 1; + else + *pState = 0; + } + else if (2 == ext_id) + { + if ((retVal = rtl8367c_setAsicReg(0x6601, 0x0002))!=RT_ERR_OK) + return retVal; + if ((retVal = rtl8367c_setAsicReg(0x6600, 0x0080))!=RT_ERR_OK) + return retVal; + if ((retVal = rtl8367c_getAsicReg(0x6602, ®Value))!=RT_ERR_OK) + return retVal; + + if(regValue & 0x0200) + *pState = 1; + else + *pState = 0; + } + else + return RT_ERR_PORT_ID; + } + else if(type == 2) + { + if ((retVal = rtl8367c_getAsicSdsReg(0, 2, 0, ®Value))!=RT_ERR_OK) + return retVal; + + if(regValue & 0x100) + *pState = 0; + else + *pState = 1; + } + + return RT_ERR_OK; +} + + + +/* Function Name: + * rtl8367c_setFiberAbilityExt + * Description: + * Set external interface serdes pause/asypause ability + * Input: + * id - external interface id (0~2) + * pause - pause + * asypause - asypause + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - input parameter out of range + * Note: + * None + */ +ret_t rtl8367c_setFiberAbilityExt(rtk_uint32 ext_id, rtk_uint32 pause, rtk_uint32 asypause) +{ + rtk_uint32 retVal, regValue, type; + + if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0249)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_getAsicReg(0x1300, ®Value)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0000)) != RT_ERR_OK) + return retVal; + + switch (regValue) + { + case 0x0276: + case 0x0597: + case 0x6367: + type = 0; + break; + case 0x0652: + case 0x6368: + type = 1; + break; + case 0x0801: + case 0x6511: + type = 2; + break; + default: + return RT_ERR_FAILED; + } + + + if(type == 0) + { + return RT_ERR_OK; + } + else if(type == 1) + { + if (1 == ext_id) + { + if ((retVal = rtl8367c_setAsicRegBit(0x6210, 11, 1))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicRegBit(0x6214, 8, asypause))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicRegBit(0x6214, 7, pause))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicRegBit(0x6210, 11, 0))!=RT_ERR_OK) + return retVal; + } + else if (2 == ext_id) + { + if ((retVal = rtl8367c_setAsicRegBit(0x6200, 11, 1))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicRegBit(0x6204, 8, asypause))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicRegBit(0x6204, 7, pause))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicRegBit(0x6200, 11, 0))!=RT_ERR_OK) + return retVal; + } + else + return RT_ERR_PORT_ID; + } + else if(type == 2) + { + return RT_ERR_OK; + } + + return RT_ERR_OK; +} + + +/* Function Name: + * rtl8367c_getFiberAbilityExt + * Description: + * Set external interface serdes pause/asypause ability + * Input: + * id - external interface id (0~2) + * pPause - pause + * pAsypause - asypause + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - input parameter out of range + * Note: + * None + */ +ret_t rtl8367c_getFiberAbilityExt(rtk_uint32 ext_id, rtk_uint32* pPause, rtk_uint32* pAsypause) +{ + rtk_uint32 retVal, regValue, type; + + if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0249)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_getAsicReg(0x1300, ®Value)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0000)) != RT_ERR_OK) + return retVal; + + switch (regValue) + { + case 0x0276: + case 0x0597: + case 0x6367: + type = 0; + break; + case 0x0652: + case 0x6368: + type = 1; + break; + case 0x0801: + case 0x6511: + type = 2; + break; + default: + return RT_ERR_FAILED; + } + + + if(type == 0) + { + return RT_ERR_OK; + } + else if(type == 1) + { + if (1 == ext_id) + { + if ((retVal = rtl8367c_setAsicRegBit(0x6210, 11, 1))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_getAsicRegBit(0x6214, 8, pAsypause))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_getAsicRegBit(0x6214, 7, pPause))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicRegBit(0x6210, 11, 0))!=RT_ERR_OK) + return retVal; + } + else if (2 == ext_id) + { + if ((retVal = rtl8367c_setAsicRegBit(0x6200, 11, 1))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_getAsicRegBit(0x6204, 8, pAsypause))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_getAsicRegBit(0x6204, 7, pPause))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367c_setAsicRegBit(0x6200, 11, 0))!=RT_ERR_OK) + return retVal; + } + else + return RT_ERR_PORT_ID; + } + else if(type == 2) + { + return RT_ERR_OK; + } + + return RT_ERR_OK; +} + + + + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_port.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_port.h new file mode 100644 index 00000000..f150439a --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_port.h @@ -0,0 +1,205 @@ +#ifndef _RTL8367C_ASICDRV_PORTSECURITY_H_ +#define _RTL8367C_ASICDRV_PORTSECURITY_H_ + +#include +#include +#include + +/****************************************************************/ +/* Type Definition */ +/****************************************************************/ + +#define RTL8367C_MAC7 7 +#define RTL8367C_EXTNO 3 + +#define RTL8367C_RTCT_PAGE (11) +#define RTL8367C_RTCT_RESULT_A_REG (27) +#define RTL8367C_RTCT_RESULT_B_REG (28) +#define RTL8367C_RTCT_RESULT_C_REG (29) +#define RTL8367C_RTCT_RESULT_D_REG (30) +#define RTL8367C_RTCT_STATUS_REG (26) + +enum L2_SECURITY_BEHAVE +{ + L2_BEHAVE_FLOODING = 0, + L2_BEHAVE_DROP, + L2_BEHAVE_TRAP, + L2_BEHAVE_END +}; + +enum L2_UNDA_BEHAVE +{ + L2_UNDA_BEHAVE_FLOODING_PMASK = 0, + L2_UNDA_BEHAVE_DROP, + L2_UNDA_BEHAVE_TRAP, + L2_UNDA_BEHAVE_FLOODING, + L2_UNDA_BEHAVE_END +}; + +enum L2_SECURITY_SA_BEHAVE +{ + L2_BEHAVE_SA_FLOODING = 0, + L2_BEHAVE_SA_DROP, + L2_BEHAVE_SA_TRAP, + L2_BEHAVE_SA_COPY28051, + L2_BEHAVE_SA_END +}; + +/* enum for port current link speed */ +enum SPEEDMODE +{ + SPD_10M = 0, + SPD_100M, + SPD_1000M, + SPD_2500M +}; + +/* enum for mac link mode */ +enum LINKMODE +{ + MAC_NORMAL = 0, + MAC_FORCE, +}; + +/* enum for port current link duplex mode */ +enum DUPLEXMODE +{ + HALF_DUPLEX = 0, + FULL_DUPLEX +}; + +/* enum for port current MST mode */ +enum MSTMODE +{ + SLAVE_MODE= 0, + MASTER_MODE +}; + + +enum EXTMODE +{ + EXT_DISABLE = 0, + EXT_RGMII, + EXT_MII_MAC, + EXT_MII_PHY, + EXT_TMII_MAC, + EXT_TMII_PHY, + EXT_GMII, + EXT_RMII_MAC, + EXT_RMII_PHY, + EXT_SGMII, + EXT_HSGMII, + EXT_1000X_100FX, + EXT_1000X, + EXT_100FX, + EXT_RGMII_2, + EXT_MII_MAC_2, + EXT_MII_PHY_2, + EXT_TMII_MAC_2, + EXT_TMII_PHY_2, + EXT_RMII_MAC_2, + EXT_RMII_PHY_2, + EXT_END +}; + +typedef struct rtl8367c_port_ability_s{ + rtk_uint16 forcemode; + rtk_uint16 mstfault; + rtk_uint16 mstmode; + rtk_uint16 nway; + rtk_uint16 txpause; + rtk_uint16 rxpause; + rtk_uint16 link; + rtk_uint16 duplex; + rtk_uint16 speed; +}rtl8367c_port_ability_t; + +typedef struct rtl8367c_port_status_s{ + + rtk_uint16 lpi1000; + rtk_uint16 lpi100; + rtk_uint16 mstfault; + rtk_uint16 mstmode; + rtk_uint16 nway; + rtk_uint16 txpause; + rtk_uint16 rxpause; + rtk_uint16 link; + rtk_uint16 duplex; + rtk_uint16 speed; + +}rtl8367c_port_status_t; + +typedef struct rtct_result_s +{ + rtk_uint32 channelAShort; + rtk_uint32 channelBShort; + rtk_uint32 channelCShort; + rtk_uint32 channelDShort; + + rtk_uint32 channelAOpen; + rtk_uint32 channelBOpen; + rtk_uint32 channelCOpen; + rtk_uint32 channelDOpen; + + rtk_uint32 channelAMismatch; + rtk_uint32 channelBMismatch; + rtk_uint32 channelCMismatch; + rtk_uint32 channelDMismatch; + + rtk_uint32 channelALinedriver; + rtk_uint32 channelBLinedriver; + rtk_uint32 channelCLinedriver; + rtk_uint32 channelDLinedriver; + + rtk_uint32 channelALen; + rtk_uint32 channelBLen; + rtk_uint32 channelCLen; + rtk_uint32 channelDLen; +} rtl8367c_port_rtct_result_t; + + +/****************************************************************/ +/* Driver Proto Type Definition */ +/****************************************************************/ +extern ret_t rtl8367c_setAsicPortUnknownDaBehavior(rtk_uint32 port, rtk_uint32 behavior); +extern ret_t rtl8367c_getAsicPortUnknownDaBehavior(rtk_uint32 port, rtk_uint32 *pBehavior); +extern ret_t rtl8367c_setAsicPortUnknownSaBehavior(rtk_uint32 behavior); +extern ret_t rtl8367c_getAsicPortUnknownSaBehavior(rtk_uint32 *pBehavior); +extern ret_t rtl8367c_setAsicPortUnmatchedSaBehavior(rtk_uint32 behavior); +extern ret_t rtl8367c_getAsicPortUnmatchedSaBehavior(rtk_uint32 *pBehavior); +extern ret_t rtl8367c_setAsicPortUnmatchedSaMoving(rtk_uint32 port, rtk_uint32 enabled); +extern ret_t rtl8367c_getAsicPortUnmatchedSaMoving(rtk_uint32 port, rtk_uint32 *pEnabled); +extern ret_t rtl8367c_setAsicPortUnknownDaFloodingPortmask(rtk_uint32 portmask); +extern ret_t rtl8367c_getAsicPortUnknownDaFloodingPortmask(rtk_uint32 *pPortmask); +extern ret_t rtl8367c_setAsicPortUnknownMulticastFloodingPortmask(rtk_uint32 portmask); +extern ret_t rtl8367c_getAsicPortUnknownMulticastFloodingPortmask(rtk_uint32 *pPortmask); +extern ret_t rtl8367c_setAsicPortBcastFloodingPortmask(rtk_uint32 portmask); +extern ret_t rtl8367c_getAsicPortBcastFloodingPortmask(rtk_uint32 *pPortmask); +extern ret_t rtl8367c_setAsicPortBlockSpa(rtk_uint32 port, rtk_uint32 block); +extern ret_t rtl8367c_getAsicPortBlockSpa(rtk_uint32 port, rtk_uint32 *pBlock); +extern ret_t rtl8367c_setAsicPortForceLink(rtk_uint32 port, rtl8367c_port_ability_t *pPortAbility); +extern ret_t rtl8367c_getAsicPortForceLink(rtk_uint32 port, rtl8367c_port_ability_t *pPortAbility); +extern ret_t rtl8367c_getAsicPortStatus(rtk_uint32 port, rtl8367c_port_status_t *pPortStatus); +extern ret_t rtl8367c_setAsicPortForceLinkExt(rtk_uint32 id, rtl8367c_port_ability_t *pPortAbility); +extern ret_t rtl8367c_getAsicPortForceLinkExt(rtk_uint32 id, rtl8367c_port_ability_t *pPortAbility); +extern ret_t rtl8367c_setAsicPortExtMode(rtk_uint32 id, rtk_uint32 mode); +extern ret_t rtl8367c_getAsicPortExtMode(rtk_uint32 id, rtk_uint32 *pMode); +extern ret_t rtl8367c_setAsicPortEnableAll(rtk_uint32 enable); +extern ret_t rtl8367c_getAsicPortEnableAll(rtk_uint32 *pEnable); +extern ret_t rtl8367c_setAsicPortSmallIpg(rtk_uint32 port, rtk_uint32 enable); +extern ret_t rtl8367c_getAsicPortSmallIpg(rtk_uint32 port, rtk_uint32* pEnable); +extern ret_t rtl8367c_setAsicPortLoopback(rtk_uint32 port, rtk_uint32 enable); +extern ret_t rtl8367c_getAsicPortLoopback(rtk_uint32 port, rtk_uint32 *pEnable); +extern ret_t rtl8367c_setAsicPortRTCTEnable(rtk_uint32 portmask); +extern ret_t rtl8367c_setAsicPortRTCTDisable(rtk_uint32 portmask); +extern ret_t rtl8367c_getAsicPortRTCTResult(rtk_uint32 port, rtl8367c_port_rtct_result_t *pResult); +extern ret_t rtl8367c_sdsReset(rtk_uint32 id); +extern ret_t rtl8367c_getSdsLinkStatus(rtk_uint32 ext_id, rtk_uint32 *pSignalDetect, rtk_uint32 *pSync, rtk_uint32 *pLink); +extern ret_t rtl8367c_setSgmiiNway(rtk_uint32 ext_id, rtk_uint32 state); +extern ret_t rtl8367c_getSgmiiNway(rtk_uint32 ext_id, rtk_uint32 *pState); +extern ret_t rtl8367c_setFiberAbilityExt(rtk_uint32 ext_id, rtk_uint32 pause, rtk_uint32 asypause); +extern ret_t rtl8367c_getFiberAbilityExt(rtk_uint32 ext_id, rtk_uint32* pPause, rtk_uint32* pAsypause); + + +#endif /*_RTL8367C_ASICDRV_PORTSECURITY_H_*/ + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_portIsolation.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_portIsolation.c new file mode 100644 index 00000000..676c82eb --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_portIsolation.c @@ -0,0 +1,121 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTL8367C switch high-level API for RTL8367C + * Feature : Port isolation related functions + * + */ + +#include +/* Function Name: + * rtl8367c_setAsicPortIsolationPermittedPortmask + * Description: + * Set permitted port isolation portmask + * Input: + * port - Physical port number (0~10) + * permitPortmask - port mask + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * RT_ERR_PORT_MASK - Invalid portmask + * Note: + * None + */ +ret_t rtl8367c_setAsicPortIsolationPermittedPortmask(rtk_uint32 port, rtk_uint32 permitPortmask) +{ + if(port >= RTL8367C_PORTNO) + return RT_ERR_PORT_ID; + + if( permitPortmask > RTL8367C_PORTMASK) + return RT_ERR_PORT_MASK; + + return rtl8367c_setAsicReg(RTL8367C_PORT_ISOLATION_PORT_MASK_REG(port), permitPortmask); +} +/* Function Name: + * rtl8367c_getAsicPortIsolationPermittedPortmask + * Description: + * Get permitted port isolation portmask + * Input: + * port - Physical port number (0~10) + * pPermitPortmask - port mask + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_getAsicPortIsolationPermittedPortmask(rtk_uint32 port, rtk_uint32 *pPermitPortmask) +{ + if(port >= RTL8367C_PORTNO) + return RT_ERR_PORT_ID; + + return rtl8367c_getAsicReg(RTL8367C_PORT_ISOLATION_PORT_MASK_REG(port), pPermitPortmask); +} +/* Function Name: + * rtl8367c_setAsicPortIsolationEfid + * Description: + * Set port isolation EFID + * Input: + * port - Physical port number (0~10) + * efid - EFID (0~7) + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * RT_ERR_OUT_OF_RANGE - Input parameter out of range + * Note: + * EFID is used in individual learning in filtering database + */ +ret_t rtl8367c_setAsicPortIsolationEfid(rtk_uint32 port, rtk_uint32 efid) +{ + if(port >= RTL8367C_PORTNO) + return RT_ERR_PORT_ID; + + if( efid > RTL8367C_EFIDMAX) + return RT_ERR_OUT_OF_RANGE; + + return rtl8367c_setAsicRegBits(RTL8367C_PORT_EFID_REG(port), RTL8367C_PORT_EFID_MASK(port), efid); +} +/* Function Name: + * rtl8367c_getAsicPortIsolationEfid + * Description: + * Get port isolation EFID + * Input: + * port - Physical port number (0~10) + * pEfid - EFID (0~7) + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_getAsicPortIsolationEfid(rtk_uint32 port, rtk_uint32 *pEfid) +{ + if(port >= RTL8367C_PORTNO) + return RT_ERR_PORT_ID; + + return rtl8367c_getAsicRegBits(RTL8367C_PORT_EFID_REG(port), RTL8367C_PORT_EFID_MASK(port), pEfid); +} + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_portIsolation.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_portIsolation.h new file mode 100644 index 00000000..0e4e1f6d --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_portIsolation.h @@ -0,0 +1,11 @@ +#ifndef _RTL8367C_ASICDRV_PORTISOLATION_H_ +#define _RTL8367C_ASICDRV_PORTISOLATION_H_ + +#include + +extern ret_t rtl8367c_setAsicPortIsolationPermittedPortmask(rtk_uint32 port, rtk_uint32 permitPortmask); +extern ret_t rtl8367c_getAsicPortIsolationPermittedPortmask(rtk_uint32 port, rtk_uint32 *pPermitPortmask); +extern ret_t rtl8367c_setAsicPortIsolationEfid(rtk_uint32 port, rtk_uint32 efid); +extern ret_t rtl8367c_getAsicPortIsolationEfid(rtk_uint32 port, rtk_uint32 *pEfid); + +#endif /*_RTL8367C_ASICDRV_PORTISOLATION_H_*/ diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_qos.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_qos.c new file mode 100644 index 00000000..5ba395be --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_qos.c @@ -0,0 +1,780 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTL8367C switch high-level API for RTL8367C + * Feature : Qos related functions + * + */ + +#include +/* Function Name: + * rtl8367c_setAsicPriorityDot1qRemapping + * Description: + * Set 802.1Q absolutely priority + * Input: + * srcpriority - Priority value + * priority - Absolute priority value + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_INT_PRIORITY - Invalid priority + * Note: + * None + */ +ret_t rtl8367c_setAsicPriorityDot1qRemapping(rtk_uint32 srcpriority, rtk_uint32 priority ) +{ + if((srcpriority > RTL8367C_PRIMAX) || (priority > RTL8367C_PRIMAX)) + return RT_ERR_QOS_INT_PRIORITY; + + return rtl8367c_setAsicRegBits(RTL8367C_QOS_1Q_PRIORITY_REMAPPING_REG(srcpriority), RTL8367C_QOS_1Q_PRIORITY_REMAPPING_MASK(srcpriority),priority); +} +/* Function Name: + * rtl8367c_getAsicPriorityDot1qRemapping + * Description: + * Get 802.1Q absolutely priority + * Input: + * srcpriority - Priority value + * pPriority - Absolute priority value + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicPriorityDot1qRemapping(rtk_uint32 srcpriority, rtk_uint32 *pPriority ) +{ + if(srcpriority > RTL8367C_PRIMAX ) + return RT_ERR_QOS_INT_PRIORITY; + + return rtl8367c_getAsicRegBits(RTL8367C_QOS_1Q_PRIORITY_REMAPPING_REG(srcpriority), RTL8367C_QOS_1Q_PRIORITY_REMAPPING_MASK(srcpriority), pPriority); +} +/* Function Name: + * rtl8367c_setAsicPriorityPortBased + * Description: + * Set port based priority + * Input: + * port - Physical port number (0~7) + * priority - Priority value + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * RT_ERR_QOS_INT_PRIORITY - Invalid priority + * Note: + * None + */ +ret_t rtl8367c_setAsicPriorityPortBased(rtk_uint32 port, rtk_uint32 priority ) +{ + ret_t retVal; + + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + if(priority > RTL8367C_PRIMAX ) + return RT_ERR_QOS_INT_PRIORITY; + + if(port < 8) + { + retVal = rtl8367c_setAsicRegBits(RTL8367C_QOS_PORTBASED_PRIORITY_REG(port), RTL8367C_QOS_PORTBASED_PRIORITY_MASK(port), priority); + if(retVal != RT_ERR_OK) + return retVal; + } + else + { + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_QOS_PORTBASED_PRIORITY_CTRL2, 0x7 << ((port - 8) << 2), priority); + if(retVal != RT_ERR_OK) + return retVal; + } + + return RT_ERR_OK; +} +/* Function Name: + * rtl8367c_getAsicPriorityPortBased + * Description: + * Get port based priority + * Input: + * port - Physical port number (0~7) + * pPriority - Priority value + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_getAsicPriorityPortBased(rtk_uint32 port, rtk_uint32 *pPriority ) +{ + ret_t retVal; + + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + if(port < 8) + { + retVal = rtl8367c_getAsicRegBits(RTL8367C_QOS_PORTBASED_PRIORITY_REG(port), RTL8367C_QOS_PORTBASED_PRIORITY_MASK(port), pPriority); + if(retVal != RT_ERR_OK) + return retVal; + } + else + { + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_QOS_PORTBASED_PRIORITY_CTRL2, 0x7 << ((port - 8) << 2), pPriority); + if(retVal != RT_ERR_OK) + return retVal; + } + + return RT_ERR_OK; +} +/* Function Name: + * rtl8367c_setAsicPriorityDscpBased + * Description: + * Set DSCP-based priority + * Input: + * dscp - DSCP value + * priority - Priority value + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_DSCP_VALUE - Invalid DSCP value + * RT_ERR_QOS_INT_PRIORITY - Invalid priority + * Note: + * None + */ +ret_t rtl8367c_setAsicPriorityDscpBased(rtk_uint32 dscp, rtk_uint32 priority ) +{ + if(priority > RTL8367C_PRIMAX ) + return RT_ERR_QOS_INT_PRIORITY; + + if(dscp > RTL8367C_DSCPMAX) + return RT_ERR_QOS_DSCP_VALUE; + + return rtl8367c_setAsicRegBits(RTL8367C_QOS_DSCP_TO_PRIORITY_REG(dscp), RTL8367C_QOS_DSCP_TO_PRIORITY_MASK(dscp), priority); +} +/* Function Name: + * rtl8367c_getAsicPriorityDscpBased + * Description: + * Get DSCP-based priority + * Input: + * dscp - DSCP value + * pPriority - Priority value + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_INT_PRIORITY - Invalid priority + * Note: + * None + */ +ret_t rtl8367c_getAsicPriorityDscpBased(rtk_uint32 dscp, rtk_uint32 *pPriority ) +{ + if(dscp > RTL8367C_DSCPMAX) + return RT_ERR_QOS_DSCP_VALUE; + + return rtl8367c_getAsicRegBits(RTL8367C_QOS_DSCP_TO_PRIORITY_REG(dscp), RTL8367C_QOS_DSCP_TO_PRIORITY_MASK(dscp), pPriority); +} +/* Function Name: + * rtl8367c_setAsicPriorityDecision + * Description: + * Set priority decision table + * Input: + * prisrc - Priority decision source + * decisionPri - Decision priority assignment + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_INT_PRIORITY - Invalid priority + * RT_ERR_QOS_SEL_PRI_SOURCE - Invalid priority decision source parameter + * Note: + * None + */ +ret_t rtl8367c_setAsicPriorityDecision(rtk_uint32 index, rtk_uint32 prisrc, rtk_uint32 decisionPri) +{ + ret_t retVal; + + if(index >= PRIDEC_IDX_END ) + return RT_ERR_ENTRY_INDEX; + + if(prisrc >= PRIDEC_END ) + return RT_ERR_QOS_SEL_PRI_SOURCE; + + if(decisionPri > RTL8367C_DECISIONPRIMAX ) + return RT_ERR_QOS_INT_PRIORITY; + + switch(index) + { + case PRIDEC_IDX0: + if((retVal = rtl8367c_setAsicRegBits(RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_REG(prisrc), RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_MASK(prisrc), decisionPri))!= RT_ERR_OK) + return retVal; + break; + case PRIDEC_IDX1: + if((retVal = rtl8367c_setAsicRegBits(RTL8367C_QOS_INTERNAL_PRIORITY_DECISION2_REG(prisrc), RTL8367C_QOS_INTERNAL_PRIORITY_DECISION2_MASK(prisrc), decisionPri))!= RT_ERR_OK) + return retVal; + break; + default: + break; + }; + + return RT_ERR_OK; + + +} + +/* Function Name: + * rtl8367c_getAsicPriorityDecision + * Description: + * Get priority decision table + * Input: + * prisrc - Priority decision source + * pDecisionPri - Decision priority assignment + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_SEL_PRI_SOURCE - Invalid priority decision source parameter + * Note: + * None + */ +ret_t rtl8367c_getAsicPriorityDecision(rtk_uint32 index, rtk_uint32 prisrc, rtk_uint32* pDecisionPri) +{ + ret_t retVal; + + if(index >= PRIDEC_IDX_END ) + return RT_ERR_ENTRY_INDEX; + + if(prisrc >= PRIDEC_END ) + return RT_ERR_QOS_SEL_PRI_SOURCE; + + switch(index) + { + case PRIDEC_IDX0: + if((retVal = rtl8367c_getAsicRegBits(RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_REG(prisrc), RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_MASK(prisrc), pDecisionPri))!= RT_ERR_OK) + return retVal; + break; + case PRIDEC_IDX1: + if((retVal = rtl8367c_getAsicRegBits(RTL8367C_QOS_INTERNAL_PRIORITY_DECISION2_REG(prisrc), RTL8367C_QOS_INTERNAL_PRIORITY_DECISION2_MASK(prisrc), pDecisionPri))!= RT_ERR_OK) + return retVal; + break; + default: + break; + }; + + return RT_ERR_OK; + +} + +/* Function Name: + * rtl8367c_setAsicPortPriorityDecisionIndex + * Description: + * Set priority decision index for each port + * Input: + * port - Physical port number (0~7) + * index - Table index + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * RT_ERR_QUEUE_NUM - Invalid queue number + * Note: + * None + */ +ret_t rtl8367c_setAsicPortPriorityDecisionIndex(rtk_uint32 port, rtk_uint32 index ) +{ + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + if(index >= PRIDEC_IDX_END) + return RT_ERR_ENTRY_INDEX; + + return rtl8367c_setAsicRegBit(RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_IDX_CTRL, port, index); +} +/* Function Name: + * rtl8367c_getAsicPortPriorityDecisionIndex + * Description: + * Get priority decision index for each port + * Input: + * port - Physical port number (0~7) + * pIndex - Table index + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_getAsicPortPriorityDecisionIndex(rtk_uint32 port, rtk_uint32 *pIndex ) +{ + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + return rtl8367c_getAsicRegBit(RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_IDX_CTRL, port, pIndex); +} + +/* Function Name: + * rtl8367c_setAsicOutputQueueMappingIndex + * Description: + * Set output queue number for each port + * Input: + * port - Physical port number (0~7) + * index - Mapping table index + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * RT_ERR_QUEUE_NUM - Invalid queue number + * Note: + * None + */ +ret_t rtl8367c_setAsicOutputQueueMappingIndex(rtk_uint32 port, rtk_uint32 index ) +{ + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + if(index >= RTL8367C_QUEUENO) + return RT_ERR_QUEUE_NUM; + + return rtl8367c_setAsicRegBits(RTL8367C_QOS_PORT_QUEUE_NUMBER_REG(port), RTL8367C_QOS_PORT_QUEUE_NUMBER_MASK(port), index); +} +/* Function Name: + * rtl8367c_getAsicOutputQueueMappingIndex + * Description: + * Get output queue number for each port + * Input: + * port - Physical port number (0~7) + * pIndex - Mapping table index + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_getAsicOutputQueueMappingIndex(rtk_uint32 port, rtk_uint32 *pIndex ) +{ + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + return rtl8367c_getAsicRegBits(RTL8367C_QOS_PORT_QUEUE_NUMBER_REG(port), RTL8367C_QOS_PORT_QUEUE_NUMBER_MASK(port), pIndex); +} +/* Function Name: + * rtl8367c_setAsicPriorityToQIDMappingTable + * Description: + * Set priority to QID mapping table parameters + * Input: + * index - Mapping table index + * priority - The priority value + * qid - Queue id + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_ID - Invalid queue id + * RT_ERR_QUEUE_NUM - Invalid queue number + * RT_ERR_QOS_INT_PRIORITY - Invalid priority + * Note: + * None + */ +ret_t rtl8367c_setAsicPriorityToQIDMappingTable(rtk_uint32 index, rtk_uint32 priority, rtk_uint32 qid ) +{ + if(index >= RTL8367C_QUEUENO) + return RT_ERR_QUEUE_NUM; + + if(priority > RTL8367C_PRIMAX) + return RT_ERR_QOS_INT_PRIORITY; + + if(qid > RTL8367C_QIDMAX) + return RT_ERR_QUEUE_ID; + + return rtl8367c_setAsicRegBits(RTL8367C_QOS_1Q_PRIORITY_TO_QID_REG(index, priority), RTL8367C_QOS_1Q_PRIORITY_TO_QID_MASK(priority), qid); +} +/* Function Name: + * rtl8367c_getAsicPriorityToQIDMappingTable + * Description: + * Get priority to QID mapping table parameters + * Input: + * index - Mapping table index + * priority - The priority value + * pQid - Queue id + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number + * RT_ERR_QOS_INT_PRIORITY - Invalid priority + * Note: + * None + */ +ret_t rtl8367c_getAsicPriorityToQIDMappingTable(rtk_uint32 index, rtk_uint32 priority, rtk_uint32* pQid) +{ + if(index >= RTL8367C_QUEUENO) + return RT_ERR_QUEUE_NUM; + + if(priority > RTL8367C_PRIMAX) + return RT_ERR_QOS_INT_PRIORITY; + + return rtl8367c_getAsicRegBits(RTL8367C_QOS_1Q_PRIORITY_TO_QID_REG(index, priority), RTL8367C_QOS_1Q_PRIORITY_TO_QID_MASK(priority), pQid); +} +/* Function Name: + * rtl8367c_setAsicRemarkingDot1pAbility + * Description: + * Set 802.1p remarking ability + * Input: + * port - Physical port number (0~7) + * enabled - 1: enabled, 0: disabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_setAsicRemarkingDot1pAbility(rtk_uint32 port, rtk_uint32 enabled) +{ + return rtl8367c_setAsicRegBit(RTL8367C_PORT_MISC_CFG_REG(port), RTL8367C_1QREMARK_ENABLE_OFFSET, enabled); +} +/* Function Name: + * rtl8367c_getAsicRemarkingDot1pAbility + * Description: + * Get 802.1p remarking ability + * Input: + * port - Physical port number (0~7) + * pEnabled - 1: enabled, 0: disabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicRemarkingDot1pAbility(rtk_uint32 port, rtk_uint32* pEnabled) +{ + return rtl8367c_getAsicRegBit(RTL8367C_PORT_MISC_CFG_REG(port), RTL8367C_1QREMARK_ENABLE_OFFSET, pEnabled); +} +/* Function Name: + * rtl8367c_setAsicRemarkingDot1pParameter + * Description: + * Set 802.1p remarking parameter + * Input: + * priority - Priority value + * newPriority - New priority value + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_INT_PRIORITY - Invalid priority + * Note: + * None + */ +ret_t rtl8367c_setAsicRemarkingDot1pParameter(rtk_uint32 priority, rtk_uint32 newPriority ) +{ + if(priority > RTL8367C_PRIMAX || newPriority > RTL8367C_PRIMAX) + return RT_ERR_QOS_INT_PRIORITY; + + return rtl8367c_setAsicRegBits(RTL8367C_QOS_1Q_REMARK_REG(priority), RTL8367C_QOS_1Q_REMARK_MASK(priority), newPriority); +} +/* Function Name: + * rtl8367c_getAsicRemarkingDot1pParameter + * Description: + * Get 802.1p remarking parameter + * Input: + * priority - Priority value + * pNewPriority - New priority value + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_INT_PRIORITY - Invalid priority + * Note: + * None + */ +ret_t rtl8367c_getAsicRemarkingDot1pParameter(rtk_uint32 priority, rtk_uint32 *pNewPriority ) +{ + if(priority > RTL8367C_PRIMAX ) + return RT_ERR_QOS_INT_PRIORITY; + + return rtl8367c_getAsicRegBits(RTL8367C_QOS_1Q_REMARK_REG(priority), RTL8367C_QOS_1Q_REMARK_MASK(priority), pNewPriority); +} + +/* Function Name: + * rtl8367c_setAsicRemarkingDot1pSrc + * Description: + * Set remarking source of 802.1p remarking. + * Input: + * type - remarking source + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + + * Note: + * The API can configure 802.1p remark functionality to map original DSCP value or internal + * priority to TX DSCP value. + */ +ret_t rtl8367c_setAsicRemarkingDot1pSrc(rtk_uint32 type) +{ + + if(type >= DOT1P_PRISEL_END ) + return RT_ERR_QOS_SEL_PRI_SOURCE; + + return rtl8367c_setAsicRegBit(RTL8367C_REG_RMK_CFG_SEL_CTRL, RTL8367C_RMK_1Q_CFG_SEL_OFFSET, type); +} + + +/* Function Name: + * rtl8367c_getAsicRemarkingDot1pSrc + * Description: + * Get remarking source of 802.1p remarking. + * Output: + * pType - remarking source + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * RT_ERR_NULL_POINTER - input parameter may be null pointer + + * Note: + * None + */ +ret_t rtl8367c_getAsicRemarkingDot1pSrc(rtk_uint32 *pType) +{ + return rtl8367c_getAsicRegBit(RTL8367C_REG_RMK_CFG_SEL_CTRL, RTL8367C_RMK_1Q_CFG_SEL_OFFSET, pType); +} + + + + + +/* Function Name: + * rtl8367c_setAsicRemarkingDscpAbility + * Description: + * Set DSCP remarking ability + * Input: + * enabled - 1: enabled, 0: disabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicRemarkingDscpAbility(rtk_uint32 enabled) +{ + return rtl8367c_setAsicRegBit(RTL8367C_REMARKING_CTRL_REG, RTL8367C_REMARKING_DSCP_ENABLE_OFFSET, enabled); +} +/* Function Name: + * rtl8367c_getAsicRemarkingDscpAbility + * Description: + * Get DSCP remarking ability + * Input: + * enabled - 1: enabled, 0: disabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicRemarkingDscpAbility(rtk_uint32* pEnabled) +{ + return rtl8367c_getAsicRegBit(RTL8367C_REMARKING_CTRL_REG, RTL8367C_REMARKING_DSCP_ENABLE_OFFSET, pEnabled); +} +/* Function Name: + * rtl8367c_setAsicRemarkingDscpParameter + * Description: + * Set DSCP remarking parameter + * Input: + * priority - Priority value + * newDscp - New DSCP value + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_DSCP_VALUE - Invalid DSCP value + * RT_ERR_QOS_INT_PRIORITY - Invalid priority + * Note: + * None + */ +ret_t rtl8367c_setAsicRemarkingDscpParameter(rtk_uint32 priority, rtk_uint32 newDscp ) +{ + if(priority > RTL8367C_PRIMAX ) + return RT_ERR_QOS_INT_PRIORITY; + + if(newDscp > RTL8367C_DSCPMAX) + return RT_ERR_QOS_DSCP_VALUE; + + return rtl8367c_setAsicRegBits(RTL8367C_QOS_DSCP_REMARK_REG(priority), RTL8367C_QOS_DSCP_REMARK_MASK(priority), newDscp); +} +/* Function Name: + * rtl8367c_getAsicRemarkingDscpParameter + * Description: + * Get DSCP remarking parameter + * Input: + * priority - Priority value + * pNewDscp - New DSCP value + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_INT_PRIORITY - Invalid priority + * Note: + * None + */ +ret_t rtl8367c_getAsicRemarkingDscpParameter(rtk_uint32 priority, rtk_uint32* pNewDscp ) +{ + if(priority > RTL8367C_PRIMAX ) + return RT_ERR_QOS_INT_PRIORITY; + + return rtl8367c_getAsicRegBits(RTL8367C_QOS_DSCP_REMARK_REG(priority), RTL8367C_QOS_DSCP_REMARK_MASK(priority), pNewDscp); +} + +/* Function Name: + * rtl8367c_setAsicRemarkingDscpSrc + * Description: + * Set remarking source of DSCP remarking. + * Input: + * type - remarking source + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + + * Note: + * The API can configure DSCP remark functionality to map original DSCP value or internal + * priority to TX DSCP value. + */ +ret_t rtl8367c_setAsicRemarkingDscpSrc(rtk_uint32 type) +{ + + if(type >= DSCP_PRISEL_END ) + return RT_ERR_QOS_SEL_PRI_SOURCE; + + return rtl8367c_setAsicRegBits(RTL8367C_REG_RMK_CFG_SEL_CTRL, RTL8367C_RMK_DSCP_CFG_SEL_MASK, type); +} + + +/* Function Name: + * rtl8367c_getAsicRemarkingDscpSrc + * Description: + * Get remarking source of DSCP remarking. + * Output: + * pType - remarking source + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * RT_ERR_NULL_POINTER - input parameter may be null pointer + + * Note: + * None + */ +ret_t rtl8367c_getAsicRemarkingDscpSrc(rtk_uint32 *pType) +{ + return rtl8367c_getAsicRegBits(RTL8367C_REG_RMK_CFG_SEL_CTRL, RTL8367C_RMK_DSCP_CFG_SEL_MASK, pType); +} + +/* Function Name: + * rtl8367c_setAsicRemarkingDscp2Dscp + * Description: + * Set DSCP to remarked DSCP mapping. + * Input: + * dscp - DSCP value + * rmkDscp - remarked DSCP value + * Output: + * None. + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_UNIT_ID - Invalid unit id + * RT_ERR_QOS_DSCP_VALUE - Invalid dscp value + * Note: + * dscp parameter can be DSCP value or internal priority according to configuration of API + * dal_apollomp_qos_dscpRemarkSrcSel_set(), because DSCP remark functionality can map original DSCP + * value or internal priority to TX DSCP value. + */ +ret_t rtl8367c_setAsicRemarkingDscp2Dscp(rtk_uint32 dscp, rtk_uint32 rmkDscp) +{ + if((dscp > RTL8367C_DSCPMAX ) || (rmkDscp > RTL8367C_DSCPMAX)) + return RT_ERR_QOS_INT_PRIORITY; + + return rtl8367c_setAsicRegBits(RTL8367C_QOS_DSCP_TO_DSCP_REG(dscp), RTL8367C_QOS_DSCP_TO_DSCP_MASK(dscp), rmkDscp); +} + +/* Function Name: + * rtl8367c_getAsicRemarkingDscp2Dscp + * Description: + * Get DSCP to remarked DSCP mapping. + * Input: + * dscp - DSCP value + * Output: + * pRmkDscp - remarked DSCP value + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_QOS_DSCP_VALUE - Invalid dscp value + * RT_ERR_NULL_POINTER - NULL pointer + * Note: + * None. + */ +ret_t rtl8367c_getAsicRemarkingDscp2Dscp(rtk_uint32 dscp, rtk_uint32 *pRmkDscp) +{ + if(dscp > RTL8367C_DSCPMAX) + return RT_ERR_QOS_DSCP_VALUE; + + return rtl8367c_getAsicRegBits(RTL8367C_QOS_DSCP_TO_DSCP_REG(dscp), RTL8367C_QOS_DSCP_TO_DSCP_MASK(dscp), pRmkDscp); + +} + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_qos.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_qos.h new file mode 100644 index 00000000..e3f2f870 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_qos.h @@ -0,0 +1,79 @@ +#ifndef _RTL8367C_ASICDRV_QOS_H_ +#define _RTL8367C_ASICDRV_QOS_H_ + +#include + +#define RTL8367C_DECISIONPRIMAX 0xFF + +/* enum Priority Selection Types */ +enum PRIDECISION +{ + PRIDEC_PORT = 0, + PRIDEC_ACL, + PRIDEC_DSCP, + PRIDEC_1Q, + PRIDEC_1AD, + PRIDEC_CVLAN, + PRIDEC_DA, + PRIDEC_SA, + PRIDEC_END, +}; + +/* enum Priority Selection Index */ +enum RTL8367C_PRIDEC_TABLE +{ + PRIDEC_IDX0 = 0, + PRIDEC_IDX1, + PRIDEC_IDX_END, +}; + +enum RTL8367C_DOT1P_PRISEL +{ + DOT1P_PRISEL_USER = 0, + DOT1P_PRISEL_TAG, + DOT1P_PRISEL_END +}; + +enum RTL8367C_DSCP_PRISEL +{ + DSCP_PRISEL_INTERNAL = 0, + DSCP_PRISEL_DSCP, + DSCP_PRISEL_USER , + DSCP_PRISEL_END +}; + + +extern ret_t rtl8367c_setAsicRemarkingDot1pAbility(rtk_uint32 port, rtk_uint32 enabled); +extern ret_t rtl8367c_getAsicRemarkingDot1pAbility(rtk_uint32 port, rtk_uint32* pEnabled); +extern ret_t rtl8367c_setAsicRemarkingDot1pParameter(rtk_uint32 priority, rtk_uint32 newPriority ); +extern ret_t rtl8367c_getAsicRemarkingDot1pParameter(rtk_uint32 priority, rtk_uint32 *pNewPriority ); +extern ret_t rtl8367c_setAsicRemarkingDot1pSrc(rtk_uint32 type); +extern ret_t rtl8367c_getAsicRemarkingDot1pSrc(rtk_uint32 *pType); +extern ret_t rtl8367c_setAsicRemarkingDscpAbility(rtk_uint32 enabled); +extern ret_t rtl8367c_getAsicRemarkingDscpAbility(rtk_uint32* pEnabled); +extern ret_t rtl8367c_setAsicRemarkingDscpParameter(rtk_uint32 priority, rtk_uint32 newDscp ); +extern ret_t rtl8367c_getAsicRemarkingDscpParameter(rtk_uint32 priority, rtk_uint32* pNewDscp ); + +extern ret_t rtl8367c_setAsicPriorityDot1qRemapping(rtk_uint32 srcpriority, rtk_uint32 priority ); +extern ret_t rtl8367c_getAsicPriorityDot1qRemapping(rtk_uint32 srcpriority, rtk_uint32 *pPriority ); +extern ret_t rtl8367c_setAsicPriorityDscpBased(rtk_uint32 dscp, rtk_uint32 priority ); +extern ret_t rtl8367c_getAsicPriorityDscpBased(rtk_uint32 dscp, rtk_uint32 *pPriority ); +extern ret_t rtl8367c_setAsicPriorityPortBased(rtk_uint32 port, rtk_uint32 priority ); +extern ret_t rtl8367c_getAsicPriorityPortBased(rtk_uint32 port, rtk_uint32 *pPriority ); +extern ret_t rtl8367c_setAsicPriorityDecision(rtk_uint32 index, rtk_uint32 prisrc, rtk_uint32 decisionPri); +extern ret_t rtl8367c_getAsicPriorityDecision(rtk_uint32 index, rtk_uint32 prisrc, rtk_uint32* pDecisionPri); +extern ret_t rtl8367c_setAsicPriorityToQIDMappingTable(rtk_uint32 qnum, rtk_uint32 priority, rtk_uint32 qid ); +extern ret_t rtl8367c_getAsicPriorityToQIDMappingTable(rtk_uint32 qnum, rtk_uint32 priority, rtk_uint32* pQid); +extern ret_t rtl8367c_setAsicOutputQueueMappingIndex(rtk_uint32 port, rtk_uint32 qnum ); +extern ret_t rtl8367c_getAsicOutputQueueMappingIndex(rtk_uint32 port, rtk_uint32 *pQnum ); + +extern ret_t rtl8367c_setAsicRemarkingDscpSrc(rtk_uint32 type); +extern ret_t rtl8367c_getAsicRemarkingDscpSrc(rtk_uint32 *pType); +extern ret_t rtl8367c_setAsicRemarkingDscp2Dscp(rtk_uint32 dscp, rtk_uint32 rmkDscp); +extern ret_t rtl8367c_getAsicRemarkingDscp2Dscp(rtk_uint32 dscp, rtk_uint32 *pRmkDscp); + +extern ret_t rtl8367c_setAsicPortPriorityDecisionIndex(rtk_uint32 port, rtk_uint32 index ); +extern ret_t rtl8367c_getAsicPortPriorityDecisionIndex(rtk_uint32 port, rtk_uint32 *pIndex ); + +#endif /*#ifndef _RTL8367C_ASICDRV_QOS_H_*/ + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_rldp.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_rldp.c new file mode 100644 index 00000000..a734221c --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_rldp.c @@ -0,0 +1,676 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision: 42321 $ + * $Date: 2013-08-26 13:51:29 +0800 (週一, 26 八月 2013) $ + * + * Purpose : RTL8367C switch high-level API for RTL8367C + * Feature : RLDP related functions + * + */ + +#include +/* Function Name: + * rtl8367c_setAsicRldp + * Description: + * Set RLDP function enable/disable + * Input: + * enabled - 1: enabled, 0: disabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicRldp(rtk_uint32 enabled) +{ + return rtl8367c_setAsicRegBit(RTL8367C_REG_RLDP_CTRL0, RTL8367C_RLDP_ENABLE_OFFSET, enabled); +} +/* Function Name: + * rtl8367c_getAsicRldp + * Description: + * Get RLDP function enable/disable + * Input: + * pEnabled - 1: enabled, 0: disabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicRldp(rtk_uint32 *pEnabled) +{ + return rtl8367c_getAsicRegBit(RTL8367C_REG_RLDP_CTRL0, RTL8367C_RLDP_ENABLE_OFFSET, pEnabled); +} +/* Function Name: + * rtl8367c_setAsicRldpEnable8051 + * Description: + * Set RLDP function handled by ASIC or 8051 + * Input: + * enabled - 1: enabled 8051, 0: disabled 8051 (RLDP is handled by ASIC) + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicRldpEnable8051(rtk_uint32 enabled) +{ + return rtl8367c_setAsicRegBit(RTL8367C_REG_RLDP_CTRL0, RTL8367C_RLDP_8051_ENABLE_OFFSET, enabled); +} +/* Function Name: + * rtl8367c_setAsicRldrtl8367c_getAsicRldpEnable8051pEnable8051 + * Description: + * Get RLDP function handled by ASIC or 8051 + * Input: + * pEnabled - 1: enabled 8051, 0: disabled 8051 (RLDP is handled by ASIC) + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicRldpEnable8051(rtk_uint32 *pEnabled) +{ + return rtl8367c_getAsicRegBit(RTL8367C_REG_RLDP_CTRL0, RTL8367C_RLDP_8051_ENABLE_OFFSET, pEnabled); +} +/* Function Name: + * rtl8367c_setAsicRldpCompareRandomNumber + * Description: + * Set enable compare the random number field and seed field of RLDP frame + * Input: + * enabled - 1: enabled comparing random number, 0: disabled comparing random number + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicRldpCompareRandomNumber(rtk_uint32 enabled) +{ + return rtl8367c_setAsicRegBit(RTL8367C_REG_RLDP_CTRL0, RTL8367C_RLDP_COMP_ID_OFFSET, enabled); +} +/* Function Name: + * rtl8367c_getAsicRldpCompareRandomNumber + * Description: + * Get enable compare the random number field and seed field of RLDP frame + * Input: + * pEnabled - 1: enabled comparing random number, 0: disabled comparing random number + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicRldpCompareRandomNumber(rtk_uint32 *pEnabled) +{ + return rtl8367c_getAsicRegBit(RTL8367C_REG_RLDP_CTRL0, RTL8367C_RLDP_COMP_ID_OFFSET, pEnabled); +} +/* Function Name: + * rtl8367c_setAsicRldpIndicatorSource + * Description: + * Set buzzer and LED source when detecting a loop + * Input: + * src - 0: ASIC, 1: 8051 + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicRldpIndicatorSource(rtk_uint32 src) +{ + return rtl8367c_setAsicRegBit(RTL8367C_REG_RLDP_CTRL0, RTL8367C_RLDP_INDICATOR_SOURCE_OFFSET, src); +} +/* Function Name: + * rtl8367c_getAsicRldpIndicatorSource + * Description: + * Get buzzer and LED source when detecting a loop + * Input: + * pSrc - 0: ASIC, 1: 8051 + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicRldpIndicatorSource(rtk_uint32 *pSrc) +{ + return rtl8367c_getAsicRegBit(RTL8367C_REG_RLDP_CTRL0, RTL8367C_RLDP_INDICATOR_SOURCE_OFFSET, pSrc); +} +/* Function Name: + * rtl8367c_setAsicRldpCheckingStatePara + * Description: + * Set retry count and retry period of checking state + * Input: + * retryCount - 0~0xFF (times) + * retryPeriod - 0~0xFFFF (ms) + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - input parameter out of range + * Note: + * None + */ +ret_t rtl8367c_setAsicRldpCheckingStatePara(rtk_uint32 retryCount, rtk_uint32 retryPeriod) +{ + ret_t retVal; + + if(retryCount > 0xFF) + return RT_ERR_OUT_OF_RANGE; + if(retryPeriod > RTL8367C_REGDATAMAX) + return RT_ERR_OUT_OF_RANGE; + + retVal = rtl8367c_setAsicRegBits(RTL8367C_RLDP_RETRY_COUNT_REG, RTL8367C_RLDP_RETRY_COUNT_CHKSTATE_MASK, retryCount); + if(retVal != RT_ERR_OK) + return retVal; + + return rtl8367c_setAsicReg(RTL8367C_RLDP_RETRY_PERIOD_CHKSTATE_REG, retryPeriod); +} +/* Function Name: + * rtl8367c_getAsicRldpCheckingStatePara + * Description: + * Get retry count and retry period of checking state + * Input: + * pRetryCount - 0~0xFF (times) + * pRetryPeriod - 0~0xFFFF (ms) + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - input parameter out of range + * Note: + * None + */ +ret_t rtl8367c_getAsicRldpCheckingStatePara(rtk_uint32 *pRetryCount, rtk_uint32 *pRetryPeriod) +{ + ret_t retVal; + + retVal = rtl8367c_getAsicRegBits(RTL8367C_RLDP_RETRY_COUNT_REG, RTL8367C_RLDP_RETRY_COUNT_CHKSTATE_MASK, pRetryCount); + if(retVal != RT_ERR_OK) + return retVal; + + return rtl8367c_getAsicReg(RTL8367C_RLDP_RETRY_PERIOD_CHKSTATE_REG, pRetryPeriod); +} +/* Function Name: + * rtl8367c_setAsicRldpLoopStatePara + * Description: + * Set retry count and retry period of loop state + * Input: + * retryCount - 0~0xFF (times) + * retryPeriod - 0~0xFFFF (ms) + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - input parameter out of range + * Note: + * None + */ +ret_t rtl8367c_setAsicRldpLoopStatePara(rtk_uint32 retryCount, rtk_uint32 retryPeriod) +{ + ret_t retVal; + + if(retryCount > 0xFF) + return RT_ERR_OUT_OF_RANGE; + + if(retryPeriod > RTL8367C_REGDATAMAX) + return RT_ERR_OUT_OF_RANGE; + + retVal = rtl8367c_setAsicRegBits(RTL8367C_RLDP_RETRY_COUNT_REG, RTL8367C_RLDP_RETRY_COUNT_LOOPSTATE_MASK, retryCount); + if(retVal != RT_ERR_OK) + return retVal; + + return rtl8367c_setAsicReg(RTL8367C_RLDP_RETRY_PERIOD_LOOPSTATE_REG, retryPeriod); +} +/* Function Name: + * rtl8367c_getAsicRldpLoopStatePara + * Description: + * Get retry count and retry period of loop state + * Input: + * pRetryCount - 0~0xFF (times) + * pRetryPeriod - 0~0xFFFF (ms) + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - input parameter out of range + * Note: + * None + */ +ret_t rtl8367c_getAsicRldpLoopStatePara(rtk_uint32 *pRetryCount, rtk_uint32 *pRetryPeriod) +{ + ret_t retVal; + + retVal = rtl8367c_getAsicRegBits(RTL8367C_RLDP_RETRY_COUNT_REG, RTL8367C_RLDP_RETRY_COUNT_LOOPSTATE_MASK, pRetryCount); + if(retVal != RT_ERR_OK) + return retVal; + + return rtl8367c_getAsicReg(RTL8367C_RLDP_RETRY_PERIOD_LOOPSTATE_REG, pRetryPeriod); +} +/* Function Name: + * rtl8367c_setAsicRldpTxPortmask + * Description: + * Set portmask that send/forward RLDP frame + * Input: + * portmask - 0~0xFF + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Invalid portmask + * Note: + * None + */ +ret_t rtl8367c_setAsicRldpTxPortmask(rtk_uint32 portmask) +{ + if(portmask > RTL8367C_PORTMASK) + return RT_ERR_PORT_MASK; + + return rtl8367c_setAsicReg(RTL8367C_RLDP_TX_PMSK_REG, portmask); +} +/* Function Name: + * rtl8367c_getAsicRldpTxPortmask + * Description: + * Get portmask that send/forward RLDP frame + * Input: + * pPortmask - 0~0xFF + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicRldpTxPortmask(rtk_uint32 *pPortmask) +{ + return rtl8367c_getAsicReg(RTL8367C_RLDP_TX_PMSK_REG, pPortmask); +} +/* Function Name: + * rtl8367c_setAsicRldpMagicNum + * Description: + * Set Random seed of RLDP + * Input: + * seed - MAC + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicRldpMagicNum(ether_addr_t seed) +{ + ret_t retVal; + rtk_uint32 regData; + rtk_uint16 *accessPtr; + rtk_uint32 i; + + accessPtr = (rtk_uint16*)&seed; + + for (i = 0; i < 3; i++) + { + regData = *accessPtr; + retVal = rtl8367c_setAsicReg(RTL8367C_RLDP_MAGIC_NUM_REG_BASE + i, regData); + if(retVal != RT_ERR_OK) + return retVal; + + accessPtr++; + } + + return retVal; +} +/* Function Name: + * rtl8367c_getAsicRldpMagicNum + * Description: + * Get Random seed of RLDP + * Input: + * pSeed - MAC + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicRldpMagicNum(ether_addr_t *pSeed) +{ + ret_t retVal; + rtk_uint32 regData; + rtk_uint16 *accessPtr; + rtk_uint32 i; + + accessPtr = (rtk_uint16*)pSeed; + + for(i = 0; i < 3; i++) + { + retVal = rtl8367c_getAsicReg(RTL8367C_RLDP_MAGIC_NUM_REG_BASE + i, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + *accessPtr = regData; + accessPtr++; + } + + return retVal; +} + +/* Function Name: + * rtl8367c_getAsicRldpLoopedPortmask + * Description: + * Get looped portmask + * Input: + * pPortmask - 0~0xFF + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicRldpLoopedPortmask(rtk_uint32 *pPortmask) +{ + return rtl8367c_getAsicReg(RTL8367C_RLDP_LOOP_PMSK_REG, pPortmask); +} +/* Function Name: + * rtl8367c_getAsicRldpRandomNumber + * Description: + * Get Random number of RLDP + * Input: + * pRandNumber - MAC + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicRldpRandomNumber(ether_addr_t *pRandNumber) +{ + ret_t retVal; + rtk_uint32 regData; + rtk_int16 accessPtr[3]; + rtk_uint32 i; + + for(i = 0; i < 3; i++) + { + retVal = rtl8367c_getAsicReg(RTL8367C_RLDP_RAND_NUM_REG_BASE+ i, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + accessPtr[i] = regData; + } + + memcpy(pRandNumber, accessPtr, 6); + return retVal; +} +/* Function Name: + * rtl8367c_getAsicRldpLoopedPortmask + * Description: + * Get port number of looped pair + * Input: + * port - Physical port number (0~7) + * pLoopedPair - port (0~7) + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_getAsicRldpLoopedPortPair(rtk_uint32 port, rtk_uint32 *pLoopedPair) +{ + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + if(port < 8) + return rtl8367c_getAsicRegBits(RTL8367C_RLDP_LOOP_PORT_REG(port), RTL8367C_RLDP_LOOP_PORT_MASK(port), pLoopedPair); + else + return rtl8367c_getAsicRegBits(RTL8367C_REG_RLDP_LOOP_PORT_REG4 + ((port - 8) >> 1), RTL8367C_RLDP_LOOP_PORT_MASK(port), pLoopedPair); +} +/* Function Name: + * rtl8367c_setAsicRlppTrap8051 + * Description: + * Set trap RLPP packet to 8051 + * Input: + * enabled - 1: enabled, 0: disabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicRlppTrap8051(rtk_uint32 enabled) +{ + return rtl8367c_setAsicRegBit(RTL8367C_REG_RLDP_CTRL0, RTL8367C_RLPP_8051_TRAP_OFFSET, enabled); +} +/* Function Name: + * rtl8367c_getAsicRlppTrap8051 + * Description: + * Get trap RLPP packet to 8051 + * Input: + * pEnabled - 1: enabled, 0: disabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicRlppTrap8051(rtk_uint32 *pEnabled) +{ + return rtl8367c_getAsicRegBit(RTL8367C_REG_RLDP_CTRL0, RTL8367C_RLPP_8051_TRAP_OFFSET, pEnabled); +} +/* Function Name: + * rtl8367c_setAsicRldpLeaveLoopedPortmask + * Description: + * Clear leaved looped portmask + * Input: + * portmask - 0~0xFF + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicRldpLeaveLoopedPortmask(rtk_uint32 portmask) +{ + return rtl8367c_setAsicReg(RTL8367C_REG_RLDP_RELEASED_INDICATOR, portmask); +} +/* Function Name: + * rtl8367c_getAsicRldpLeaveLoopedPortmask + * Description: + * Get leaved looped portmask + * Input: + * pPortmask - 0~0xFF + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicRldpLeaveLoopedPortmask(rtk_uint32 *pPortmask) +{ + return rtl8367c_getAsicReg(RTL8367C_REG_RLDP_RELEASED_INDICATOR, pPortmask); +} +/* Function Name: + * rtl8367c_setAsicRldpEnterLoopedPortmask + * Description: + * Clear enter loop portmask + * Input: + * portmask - 0~0xFF + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicRldpEnterLoopedPortmask(rtk_uint32 portmask) +{ + return rtl8367c_setAsicReg(RTL8367C_REG_RLDP_LOOPED_INDICATOR, portmask); +} +/* Function Name: + * rtl8367c_getAsicRldpEnterLoopedPortmask + * Description: + * Get enter loop portmask + * Input: + * pPortmask - 0~0xFF + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicRldpEnterLoopedPortmask(rtk_uint32 *pPortmask) +{ + return rtl8367c_getAsicReg(RTL8367C_REG_RLDP_LOOPED_INDICATOR, pPortmask); +} + +/* Function Name: + * rtl8367c_setAsicRldpTriggerMode + * Description: + * Set trigger RLDP mode + * Input: + * mode - 1: Periodically, 0: SA moving + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicRldpTriggerMode(rtk_uint32 enabled) +{ + return rtl8367c_setAsicRegBit(RTL8367C_REG_RLDP_CTRL0, RTL8367C_RLDP_TRIGGER_MODE_OFFSET, enabled); +} +/* Function Name: + * rtl8367c_getAsicRldpTriggerMode + * Description: + * Get trigger RLDP mode + * Input: + * pMode - - 1: Periodically, 0: SA moving + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicRldpTriggerMode(rtk_uint32 *pEnabled) +{ + return rtl8367c_getAsicRegBit(RTL8367C_REG_RLDP_CTRL0, RTL8367C_RLDP_TRIGGER_MODE_OFFSET, pEnabled); +} + +/* Function Name: + * rtl8367c_setAsicRldp8051Portmask + * Description: + * Set 8051/CPU configured looped portmask + * Input: + * portmask - 0~0xFF + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Invalid portmask + * Note: + * None + */ +ret_t rtl8367c_setAsicRldp8051Portmask(rtk_uint32 portmask) +{ + ret_t retVal; + if(portmask > RTL8367C_PORTMASK) + return RT_ERR_PORT_MASK; + + retVal = rtl8367c_setAsicRegBits(RTL8367C_RLDP_CTRL0_REG,RTL8367C_RLDP_8051_LOOP_PORTMSK_MASK,portmask & 0xff); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_RLDP_CTRL5,RTL8367C_RLDP_CTRL5_MASK,(portmask >> 8) & 7); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} +/* Function Name: + * rtl8367c_getAsicRldp8051Portmask + * Description: + * Get 8051/CPU configured looped portmask + * Input: + * pPortmask - 0~0xFF + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicRldp8051Portmask(rtk_uint32 *pPortmask) +{ + rtk_uint32 tmpPmsk; + ret_t retVal; + + retVal = rtl8367c_getAsicRegBits(RTL8367C_RLDP_CTRL0_REG,RTL8367C_RLDP_8051_LOOP_PORTMSK_MASK,&tmpPmsk); + if(retVal != RT_ERR_OK) + return retVal; + *pPortmask = tmpPmsk & 0xff; + + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_RLDP_CTRL5,RTL8367C_RLDP_CTRL5_MASK,&tmpPmsk); + if(retVal != RT_ERR_OK) + return retVal; + *pPortmask |= (tmpPmsk & 7) <<8; + + return RT_ERR_OK; +} + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_rldp.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_rldp.h new file mode 100644 index 00000000..27504f80 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_rldp.h @@ -0,0 +1,43 @@ +#ifndef _RTL8367C_ASICDRV_RLDP_H_ +#define _RTL8367C_ASICDRV_RLDP_H_ + +#include +#include + +extern ret_t rtl8367c_setAsicRldp(rtk_uint32 enabled); +extern ret_t rtl8367c_getAsicRldp(rtk_uint32 *pEnabled); +extern ret_t rtl8367c_setAsicRldpEnable8051(rtk_uint32 enabled); +extern ret_t rtl8367c_getAsicRldpEnable8051(rtk_uint32 *pEnabled); +extern ret_t rtl8367c_setAsicRldpCompareRandomNumber(rtk_uint32 enabled); +extern ret_t rtl8367c_getAsicRldpCompareRandomNumber(rtk_uint32 *pEnabled); +extern ret_t rtl8367c_setAsicRldpIndicatorSource(rtk_uint32 src); +extern ret_t rtl8367c_getAsicRldpIndicatorSource(rtk_uint32 *pSrc); +extern ret_t rtl8367c_setAsicRldpCheckingStatePara(rtk_uint32 retryCount, rtk_uint32 retryPeriod); +extern ret_t rtl8367c_getAsicRldpCheckingStatePara(rtk_uint32 *pRetryCount, rtk_uint32 *pRetryPeriod); +extern ret_t rtl8367c_setAsicRldpLoopStatePara(rtk_uint32 retryCount, rtk_uint32 retryPeriod); +extern ret_t rtl8367c_getAsicRldpLoopStatePara(rtk_uint32 *pRetryCount, rtk_uint32 *pRetryPeriod); +extern ret_t rtl8367c_setAsicRldpTxPortmask(rtk_uint32 portmask); +extern ret_t rtl8367c_getAsicRldpTxPortmask(rtk_uint32 *pPortmask); +extern ret_t rtl8367c_setAsicRldpMagicNum(ether_addr_t seed); +extern ret_t rtl8367c_getAsicRldpMagicNum(ether_addr_t *pSeed); +extern ret_t rtl8367c_getAsicRldpLoopedPortmask(rtk_uint32 *pPortmask); +extern ret_t rtl8367c_setAsicRldp8051Portmask(rtk_uint32 portmask); +extern ret_t rtl8367c_getAsicRldp8051Portmask(rtk_uint32 *pPortmask); + + +extern ret_t rtl8367c_getAsicRldpRandomNumber(ether_addr_t *pRandNumber); +extern ret_t rtl8367c_getAsicRldpLoopedPortPair(rtk_uint32 port, rtk_uint32 *pLoopedPair); +extern ret_t rtl8367c_setAsicRlppTrap8051(rtk_uint32 enabled); +extern ret_t rtl8367c_getAsicRlppTrap8051(rtk_uint32 *pEnabled); + +extern ret_t rtl8367c_setAsicRldpLeaveLoopedPortmask(rtk_uint32 portmask); +extern ret_t rtl8367c_getAsicRldpLeaveLoopedPortmask(rtk_uint32 *pPortmask); + +extern ret_t rtl8367c_setAsicRldpEnterLoopedPortmask(rtk_uint32 portmask); +extern ret_t rtl8367c_getAsicRldpEnterLoopedPortmask(rtk_uint32 *pPortmask); + +extern ret_t rtl8367c_setAsicRldpTriggerMode(rtk_uint32 enabled); +extern ret_t rtl8367c_getAsicRldpTriggerMode(rtk_uint32 *pEnabled); + +#endif /*_RTL8367C_ASICDRV_RLDP_H_*/ + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_rma.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_rma.c new file mode 100644 index 00000000..de857dcf --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_rma.c @@ -0,0 +1,363 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTL8367C switch high-level API for RTL8367C + * Feature : RMA related functions + * + */ +#include +/* Function Name: + * rtl8367c_setAsicRma + * Description: + * Set reserved multicast address for CPU trapping + * Input: + * index - reserved multicast LSB byte, 0x00~0x2F is available value + * pRmacfg - type of RMA for trapping frame type setting + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RMA_ADDR - Invalid RMA address index + * Note: + * None + */ +ret_t rtl8367c_setAsicRma(rtk_uint32 index, rtl8367c_rma_t* pRmacfg) +{ + rtk_uint32 regData = 0; + ret_t retVal; + + if(index > RTL8367C_RMAMAX) + return RT_ERR_RMA_ADDR; + + regData |= (pRmacfg->portiso_leaky & 0x0001); + regData |= ((pRmacfg->vlan_leaky & 0x0001) << 1); + regData |= ((pRmacfg->keep_format & 0x0001) << 2); + regData |= ((pRmacfg->trap_priority & 0x0007) << 3); + regData |= ((pRmacfg->discard_storm_filter & 0x0001) << 6); + regData |= ((pRmacfg->operation & 0x0003) << 7); + + if( (index >= 0x4 && index <= 0x7) || (index >= 0x9 && index <= 0x0C) || (0x0F == index)) + index = 0x04; + else if((index >= 0x13 && index <= 0x17) || (0x19 == index) || (index >= 0x1B && index <= 0x1f)) + index = 0x13; + else if(index >= 0x22 && index <= 0x2F) + index = 0x22; + + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_RMA_CTRL00, RTL8367C_TRAP_PRIORITY_MASK, pRmacfg->trap_priority); + if(retVal != RT_ERR_OK) + return retVal; + + return rtl8367c_setAsicReg(RTL8367C_REG_RMA_CTRL00+index, regData); +} +/* Function Name: + * rtl8367c_getAsicRma + * Description: + * Get reserved multicast address for CPU trapping + * Input: + * index - reserved multicast LSB byte, 0x00~0x2F is available value + * rmacfg - type of RMA for trapping frame type setting + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RMA_ADDR - Invalid RMA address index + * Note: + * None + */ +ret_t rtl8367c_getAsicRma(rtk_uint32 index, rtl8367c_rma_t* pRmacfg) +{ + ret_t retVal; + rtk_uint32 regData; + + if(index > RTL8367C_RMAMAX) + return RT_ERR_RMA_ADDR; + + if( (index >= 0x4 && index <= 0x7) || (index >= 0x9 && index <= 0x0C) || (0x0F == index)) + index = 0x04; + else if((index >= 0x13 && index <= 0x17) || (0x19 == index) || (index >= 0x1B && index <= 0x1f)) + index = 0x13; + else if(index >= 0x22 && index <= 0x2F) + index = 0x22; + + retVal = rtl8367c_getAsicReg(RTL8367C_REG_RMA_CTRL00+index, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + pRmacfg->operation = ((regData >> 7) & 0x0003); + pRmacfg->discard_storm_filter = ((regData >> 6) & 0x0001); + pRmacfg->trap_priority = ((regData >> 3) & 0x0007); + pRmacfg->keep_format = ((regData >> 2) & 0x0001); + pRmacfg->vlan_leaky = ((regData >> 1) & 0x0001); + pRmacfg->portiso_leaky = (regData & 0x0001); + + + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_RMA_CTRL00, RTL8367C_TRAP_PRIORITY_MASK, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + pRmacfg->trap_priority = regData; + + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_setAsicRmaCdp + * Description: + * Set CDP(Cisco Discovery Protocol) for CPU trapping + * Input: + * pRmacfg - type of RMA for trapping frame type setting + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RMA_ADDR - Invalid RMA address index + * Note: + * None + */ +ret_t rtl8367c_setAsicRmaCdp(rtl8367c_rma_t* pRmacfg) +{ + rtk_uint32 regData = 0; + ret_t retVal; + + if(pRmacfg->operation >= RMAOP_END) + return RT_ERR_RMA_ACTION; + + if(pRmacfg->trap_priority > RTL8367C_PRIMAX) + return RT_ERR_QOS_INT_PRIORITY; + + regData |= (pRmacfg->portiso_leaky & 0x0001); + regData |= ((pRmacfg->vlan_leaky & 0x0001) << 1); + regData |= ((pRmacfg->keep_format & 0x0001) << 2); + regData |= ((pRmacfg->trap_priority & 0x0007) << 3); + regData |= ((pRmacfg->discard_storm_filter & 0x0001) << 6); + regData |= ((pRmacfg->operation & 0x0003) << 7); + + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_RMA_CTRL00, RTL8367C_TRAP_PRIORITY_MASK, pRmacfg->trap_priority); + if(retVal != RT_ERR_OK) + return retVal; + + return rtl8367c_setAsicReg(RTL8367C_REG_RMA_CTRL_CDP, regData); +} +/* Function Name: + * rtl8367c_getAsicRmaCdp + * Description: + * Get CDP(Cisco Discovery Protocol) for CPU trapping + * Input: + * None + * Output: + * pRmacfg - type of RMA for trapping frame type setting + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RMA_ADDR - Invalid RMA address index + * Note: + * None + */ +ret_t rtl8367c_getAsicRmaCdp(rtl8367c_rma_t* pRmacfg) +{ + ret_t retVal; + rtk_uint32 regData; + + retVal = rtl8367c_getAsicReg(RTL8367C_REG_RMA_CTRL_CDP, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + pRmacfg->operation = ((regData >> 7) & 0x0003); + pRmacfg->discard_storm_filter = ((regData >> 6) & 0x0001); + pRmacfg->trap_priority = ((regData >> 3) & 0x0007); + pRmacfg->keep_format = ((regData >> 2) & 0x0001); + pRmacfg->vlan_leaky = ((regData >> 1) & 0x0001); + pRmacfg->portiso_leaky = (regData & 0x0001); + + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_RMA_CTRL00, RTL8367C_TRAP_PRIORITY_MASK, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + pRmacfg->trap_priority = regData; + + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_setAsicRmaCsstp + * Description: + * Set CSSTP(Cisco Shared Spanning Tree Protocol) for CPU trapping + * Input: + * pRmacfg - type of RMA for trapping frame type setting + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RMA_ADDR - Invalid RMA address index + * Note: + * None + */ +ret_t rtl8367c_setAsicRmaCsstp(rtl8367c_rma_t* pRmacfg) +{ + rtk_uint32 regData = 0; + ret_t retVal; + + if(pRmacfg->operation >= RMAOP_END) + return RT_ERR_RMA_ACTION; + + if(pRmacfg->trap_priority > RTL8367C_PRIMAX) + return RT_ERR_QOS_INT_PRIORITY; + + regData |= (pRmacfg->portiso_leaky & 0x0001); + regData |= ((pRmacfg->vlan_leaky & 0x0001) << 1); + regData |= ((pRmacfg->keep_format & 0x0001) << 2); + regData |= ((pRmacfg->trap_priority & 0x0007) << 3); + regData |= ((pRmacfg->discard_storm_filter & 0x0001) << 6); + regData |= ((pRmacfg->operation & 0x0003) << 7); + + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_RMA_CTRL00, RTL8367C_TRAP_PRIORITY_MASK, pRmacfg->trap_priority); + if(retVal != RT_ERR_OK) + return retVal; + + return rtl8367c_setAsicReg(RTL8367C_REG_RMA_CTRL_CSSTP, regData); +} +/* Function Name: + * rtl8367c_getAsicRmaCsstp + * Description: + * Get CSSTP(Cisco Shared Spanning Tree Protocol) for CPU trapping + * Input: + * None + * Output: + * pRmacfg - type of RMA for trapping frame type setting + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RMA_ADDR - Invalid RMA address index + * Note: + * None + */ +ret_t rtl8367c_getAsicRmaCsstp(rtl8367c_rma_t* pRmacfg) +{ + ret_t retVal; + rtk_uint32 regData; + + retVal = rtl8367c_getAsicReg(RTL8367C_REG_RMA_CTRL_CSSTP, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + pRmacfg->operation = ((regData >> 7) & 0x0003); + pRmacfg->discard_storm_filter = ((regData >> 6) & 0x0001); + pRmacfg->trap_priority = ((regData >> 3) & 0x0007); + pRmacfg->keep_format = ((regData >> 2) & 0x0001); + pRmacfg->vlan_leaky = ((regData >> 1) & 0x0001); + pRmacfg->portiso_leaky = (regData & 0x0001); + + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_RMA_CTRL00, RTL8367C_TRAP_PRIORITY_MASK, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + pRmacfg->trap_priority = regData; + + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_setAsicRmaLldp + * Description: + * Set LLDP for CPU trapping + * Input: + * pRmacfg - type of RMA for trapping frame type setting + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RMA_ADDR - Invalid RMA address index + * Note: + * None + */ +ret_t rtl8367c_setAsicRmaLldp(rtk_uint32 enabled, rtl8367c_rma_t* pRmacfg) +{ + rtk_uint32 regData = 0; + ret_t retVal; + + if(enabled > 1) + return RT_ERR_ENABLE; + + if(pRmacfg->operation >= RMAOP_END) + return RT_ERR_RMA_ACTION; + + if(pRmacfg->trap_priority > RTL8367C_PRIMAX) + return RT_ERR_QOS_INT_PRIORITY; + + retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_RMA_LLDP_EN, RTL8367C_RMA_LLDP_EN_OFFSET,enabled); + if(retVal != RT_ERR_OK) + return retVal; + + regData |= (pRmacfg->portiso_leaky & 0x0001); + regData |= ((pRmacfg->vlan_leaky & 0x0001) << 1); + regData |= ((pRmacfg->keep_format & 0x0001) << 2); + regData |= ((pRmacfg->trap_priority & 0x0007) << 3); + regData |= ((pRmacfg->discard_storm_filter & 0x0001) << 6); + regData |= ((pRmacfg->operation & 0x0003) << 7); + + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_RMA_CTRL00, RTL8367C_TRAP_PRIORITY_MASK, pRmacfg->trap_priority); + if(retVal != RT_ERR_OK) + return retVal; + + return rtl8367c_setAsicReg(RTL8367C_REG_RMA_CTRL_LLDP, regData); +} +/* Function Name: + * rtl8367c_getAsicRmaLldp + * Description: + * Get LLDP for CPU trapping + * Input: + * None + * Output: + * pRmacfg - type of RMA for trapping frame type setting + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RMA_ADDR - Invalid RMA address index + * Note: + * None + */ +ret_t rtl8367c_getAsicRmaLldp(rtk_uint32 *pEnabled, rtl8367c_rma_t* pRmacfg) +{ + ret_t retVal; + rtk_uint32 regData; + + retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_RMA_LLDP_EN, RTL8367C_RMA_LLDP_EN_OFFSET,pEnabled); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8367c_getAsicReg(RTL8367C_REG_RMA_CTRL_LLDP, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + pRmacfg->operation = ((regData >> 7) & 0x0003); + pRmacfg->discard_storm_filter = ((regData >> 6) & 0x0001); + pRmacfg->trap_priority = ((regData >> 3) & 0x0007); + pRmacfg->keep_format = ((regData >> 2) & 0x0001); + pRmacfg->vlan_leaky = ((regData >> 1) & 0x0001); + pRmacfg->portiso_leaky = (regData & 0x0001); + + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_RMA_CTRL00, RTL8367C_TRAP_PRIORITY_MASK, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + pRmacfg->trap_priority = regData; + + return RT_ERR_OK; +} + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_rma.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_rma.h new file mode 100644 index 00000000..d97e9eb0 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_rma.h @@ -0,0 +1,40 @@ +#ifndef _RTL8367C_ASICDRV_RMA_H_ +#define _RTL8367C_ASICDRV_RMA_H_ + +#include + +#define RTL8367C_RMAMAX 0x2F + +enum RTL8367C_RMAOP +{ + RMAOP_FORWARD = 0, + RMAOP_TRAP_TO_CPU, + RMAOP_DROP, + RMAOP_FORWARD_EXCLUDE_CPU, + RMAOP_END +}; + + +typedef struct rtl8367c_rma_s{ + + rtk_uint16 operation; + rtk_uint16 discard_storm_filter; + rtk_uint16 trap_priority; + rtk_uint16 keep_format; + rtk_uint16 vlan_leaky; + rtk_uint16 portiso_leaky; + +}rtl8367c_rma_t; + + +extern ret_t rtl8367c_setAsicRma(rtk_uint32 index, rtl8367c_rma_t* pRmacfg); +extern ret_t rtl8367c_getAsicRma(rtk_uint32 index, rtl8367c_rma_t* pRmacfg); +extern ret_t rtl8367c_setAsicRmaCdp(rtl8367c_rma_t* pRmacfg); +extern ret_t rtl8367c_getAsicRmaCdp(rtl8367c_rma_t* pRmacfg); +extern ret_t rtl8367c_setAsicRmaCsstp(rtl8367c_rma_t* pRmacfg); +extern ret_t rtl8367c_getAsicRmaCsstp(rtl8367c_rma_t* pRmacfg); +extern ret_t rtl8367c_setAsicRmaLldp(rtk_uint32 enabled, rtl8367c_rma_t* pRmacfg); +extern ret_t rtl8367c_getAsicRmaLldp(rtk_uint32 *pEnabled, rtl8367c_rma_t* pRmacfg); + +#endif /*#ifndef _RTL8367C_ASICDRV_RMA_H_*/ + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_scheduling.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_scheduling.c new file mode 100644 index 00000000..baf578dc --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_scheduling.c @@ -0,0 +1,527 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTL8367C switch high-level API for RTL8367C + * Feature : Packet Scheduling related functions + * + */ + +#include +/* Function Name: + * rtl8367c_setAsicLeakyBucketParameter + * Description: + * Set Leaky Bucket Paramters + * Input: + * tick - Tick is used for time slot size unit + * token - Token is used for adding budget in each time slot + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_TICK - Invalid TICK + * RT_ERR_TOKEN - Invalid TOKEN + * Note: + * None + */ +ret_t rtl8367c_setAsicLeakyBucketParameter(rtk_uint32 tick, rtk_uint32 token) +{ + ret_t retVal; + + if(tick > 0xFF) + return RT_ERR_TICK; + + if(token > 0xFF) + return RT_ERR_TOKEN; + + retVal = rtl8367c_setAsicRegBits(RTL8367C_LEAKY_BUCKET_TICK_REG, RTL8367C_LEAKY_BUCKET_TICK_MASK, tick); + + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8367c_setAsicRegBits(RTL8367C_LEAKY_BUCKET_TOKEN_REG, RTL8367C_LEAKY_BUCKET_TOKEN_MASK, token); + + return retVal; +} +/* Function Name: + * rtl8367c_getAsicLeakyBucketParameter + * Description: + * Get Leaky Bucket Paramters + * Input: + * tick - Tick is used for time slot size unit + * token - Token is used for adding budget in each time slot + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicLeakyBucketParameter(rtk_uint32 *tick, rtk_uint32 *token) +{ + ret_t retVal; + + retVal = rtl8367c_getAsicRegBits(RTL8367C_LEAKY_BUCKET_TICK_REG, RTL8367C_LEAKY_BUCKET_TICK_MASK, tick); + + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8367c_getAsicRegBits(RTL8367C_LEAKY_BUCKET_TOKEN_REG, RTL8367C_LEAKY_BUCKET_TOKEN_MASK, token); + + return retVal; +} +/* Function Name: + * rtl8367c_setAsicAprMeter + * Description: + * Set per-port per-queue APR shared meter index + * Input: + * port - Physical port number (0~10) + * qid - Queue id + * apridx - dedicated shared meter index for APR (0~7) + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * RT_ERR_QUEUE_ID - Invalid queue id + * RT_ERR_FILTER_METER_ID - Invalid meter + * Note: + * None + */ +ret_t rtl8367c_setAsicAprMeter(rtk_uint32 port, rtk_uint32 qid, rtk_uint32 apridx) +{ + ret_t retVal; + rtk_uint32 regAddr; + + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + if(qid > RTL8367C_QIDMAX) + return RT_ERR_QUEUE_ID; + + if(apridx > RTL8367C_PORT_QUEUE_METER_INDEX_MAX) + return RT_ERR_FILTER_METER_ID; + + if(port < 8) + retVal = rtl8367c_setAsicRegBits(RTL8367C_SCHEDULE_PORT_APR_METER_REG(port, qid), RTL8367C_SCHEDULE_PORT_APR_METER_MASK(qid), apridx); + else { + regAddr = RTL8367C_REG_SCHEDULE_PORT8_APR_METER_CTRL0 + ((port-8) << 1) + (qid / 5); + retVal = rtl8367c_setAsicRegBits(regAddr, RTL8367C_SCHEDULE_PORT_APR_METER_MASK(qid), apridx); + } + + return retVal; +} +/* Function Name: + * rtl8367c_getAsicAprMeter + * Description: + * Get per-port per-queue APR shared meter index + * Input: + * port - Physical port number (0~10) + * qid - Queue id + * apridx - dedicated shared meter index for APR (0~7) + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * RT_ERR_QUEUE_ID - Invalid queue id + * Note: + * None + */ +ret_t rtl8367c_getAsicAprMeter(rtk_uint32 port, rtk_uint32 qid, rtk_uint32 *apridx) +{ + ret_t retVal; + rtk_uint32 regAddr; + + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + if(qid > RTL8367C_QIDMAX) + return RT_ERR_QUEUE_ID; + + if(port < 8) + retVal = rtl8367c_getAsicRegBits(RTL8367C_SCHEDULE_PORT_APR_METER_REG(port, qid), RTL8367C_SCHEDULE_PORT_APR_METER_MASK(qid), apridx); + else { + regAddr = RTL8367C_REG_SCHEDULE_PORT8_APR_METER_CTRL0 + ((port-8) << 1) + (qid / 5); + retVal = rtl8367c_getAsicRegBits(regAddr, RTL8367C_SCHEDULE_PORT_APR_METER_MASK(qid), apridx); + } + + return retVal; +} +/* Function Name: + * rtl8367c_setAsicAprEnable + * Description: + * Set per-port APR enable + * Input: + * port - Physical port number (0~7) + * aprEnable - APR enable seting 1:enable 0:disable + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_setAsicAprEnable(rtk_uint32 port, rtk_uint32 aprEnable) +{ + ret_t retVal; + + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + retVal = rtl8367c_setAsicRegBit(RTL8367C_SCHEDULE_APR_CTRL_REG, RTL8367C_SCHEDULE_APR_CTRL_OFFSET(port), aprEnable); + + return retVal; +} +/* Function Name: + * rtl8367c_getAsicAprEnable + * Description: + * Get per-port APR enable + * Input: + * port - Physical port number (0~7) + * aprEnable - APR enable seting 1:enable 0:disable + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_getAsicAprEnable(rtk_uint32 port, rtk_uint32 *aprEnable) +{ + ret_t retVal; + + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + retVal = rtl8367c_getAsicRegBit(RTL8367C_SCHEDULE_APR_CTRL_REG, RTL8367C_SCHEDULE_APR_CTRL_OFFSET(port), aprEnable); + + return retVal; +} +/* Function Name: + * rtl8367c_setAsicWFQWeight + * Description: + * Set weight of a queue + * Input: + * port - Physical port number (0~10) + * qid - The queue ID wanted to set + * qWeight - The weight value wanted to set (valid:0~127) + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * RT_ERR_QUEUE_ID - Invalid queue id + * RT_ERR_QOS_QUEUE_WEIGHT - Invalid queue weight + * Note: + * None + */ +ret_t rtl8367c_setAsicWFQWeight(rtk_uint32 port, rtk_uint32 qid, rtk_uint32 qWeight) +{ + ret_t retVal; + + /* Invalid input parameter */ + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + if(qid > RTL8367C_QIDMAX) + return RT_ERR_QUEUE_ID; + + if(qWeight > RTL8367C_QWEIGHTMAX && qid > 0) + return RT_ERR_QOS_QUEUE_WEIGHT; + + retVal = rtl8367c_setAsicReg(RTL8367C_SCHEDULE_PORT_QUEUE_WFQ_WEIGHT_REG(port, qid), qWeight); + + return retVal; +} +/* Function Name: + * rtl8367c_getAsicWFQWeight + * Description: + * Get weight of a queue + * Input: + * port - Physical port number (0~10) + * qid - The queue ID wanted to set + * qWeight - The weight value wanted to set (valid:0~127) + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * RT_ERR_QUEUE_ID - Invalid queue id + * Note: + * None + */ +ret_t rtl8367c_getAsicWFQWeight(rtk_uint32 port, rtk_uint32 qid, rtk_uint32 *qWeight) +{ + ret_t retVal; + + + /* Invalid input parameter */ + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + if(qid > RTL8367C_QIDMAX) + return RT_ERR_QUEUE_ID; + + + retVal = rtl8367c_getAsicReg(RTL8367C_SCHEDULE_PORT_QUEUE_WFQ_WEIGHT_REG(port, qid), qWeight); + + return retVal; +} +/* Function Name: + * rtl8367c_setAsicWFQBurstSize + * Description: + * Set WFQ leaky bucket burst size + * Input: + * burstsize - Leaky bucket burst size, unit byte + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicWFQBurstSize(rtk_uint32 burstsize) +{ + ret_t retVal; + + retVal = rtl8367c_setAsicReg(RTL8367C_SCHEDULE_WFQ_BURST_SIZE_REG, burstsize); + + return retVal; +} +/* Function Name: + * rtl8367c_getAsicWFQBurstSize + * Description: + * Get WFQ leaky bucket burst size + * Input: + * burstsize - Leaky bucket burst size, unit byte + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicWFQBurstSize(rtk_uint32 *burstsize) +{ + ret_t retVal; + + retVal = rtl8367c_getAsicReg(RTL8367C_SCHEDULE_WFQ_BURST_SIZE_REG, burstsize); + + return retVal; +} +/* Function Name: + * rtl8367c_setAsicQueueType + * Description: + * Set type of a queue + * Input: + * port - Physical port number (0~10) + * qid - The queue ID wanted to set + * queueType - The specified queue type. 0b0: Strict priority, 0b1: WFQ + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * RT_ERR_QUEUE_ID - Invalid queue id + * Note: + * None + */ +ret_t rtl8367c_setAsicQueueType(rtk_uint32 port, rtk_uint32 qid, rtk_uint32 queueType) +{ + ret_t retVal; + + /* Invalid input parameter */ + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + if(qid > RTL8367C_QIDMAX) + return RT_ERR_QUEUE_ID; + + /* Set Related Registers */ + retVal = rtl8367c_setAsicRegBit(RTL8367C_SCHEDULE_QUEUE_TYPE_REG(port), RTL8367C_SCHEDULE_QUEUE_TYPE_OFFSET(port, qid),queueType); + + return retVal; +} +/* Function Name: + * rtl8367c_getAsicQueueType + * Description: + * Get type of a queue + * Input: + * port - Physical port number (0~7) + * qid - The queue ID wanted to set + * queueType - The specified queue type. 0b0: Strict priority, 0b1: WFQ + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * RT_ERR_QUEUE_ID - Invalid queue id + * Note: + * None + */ +ret_t rtl8367c_getAsicQueueType(rtk_uint32 port, rtk_uint32 qid, rtk_uint32 *queueType) +{ + ret_t retVal; + + /* Invalid input parameter */ + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + if(qid > RTL8367C_QIDMAX) + return RT_ERR_QUEUE_ID; + + retVal = rtl8367c_getAsicRegBit(RTL8367C_SCHEDULE_QUEUE_TYPE_REG(port), RTL8367C_SCHEDULE_QUEUE_TYPE_OFFSET(port, qid),queueType); + + return retVal; +} +/* Function Name: + * rtl8367c_setAsicPortEgressRate + * Description: + * Set per-port egress rate + * Input: + * port - Physical port number (0~10) + * rate - Egress rate + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * RT_ERR_QOS_EBW_RATE - Invalid bandwidth/rate + * Note: + * None + */ +ret_t rtl8367c_setAsicPortEgressRate(rtk_uint32 port, rtk_uint32 rate) +{ + ret_t retVal; + rtk_uint32 regAddr, regData; + + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + if(rate > RTL8367C_QOS_GRANULARTY_MAX) + return RT_ERR_QOS_EBW_RATE; + + regAddr = RTL8367C_PORT_EGRESSBW_LSB_REG(port); + regData = RTL8367C_QOS_GRANULARTY_LSB_MASK & rate; + + retVal = rtl8367c_setAsicReg(regAddr, regData); + + if(retVal != RT_ERR_OK) + return retVal; + + regAddr = RTL8367C_PORT_EGRESSBW_MSB_REG(port); + regData = (RTL8367C_QOS_GRANULARTY_MSB_MASK & rate) >> RTL8367C_QOS_GRANULARTY_MSB_OFFSET; + + retVal = rtl8367c_setAsicRegBits(regAddr, RTL8367C_PORT6_EGRESSBW_CTRL1_MASK, regData); + + return retVal; +} +/* Function Name: + * rtl8367c_getAsicPortEgressRate + * Description: + * Get per-port egress rate + * Input: + * port - Physical port number (0~10) + * rate - Egress rate + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_getAsicPortEgressRate(rtk_uint32 port, rtk_uint32 *rate) +{ + ret_t retVal; + rtk_uint32 regAddr, regData,regData2; + + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + regAddr = RTL8367C_PORT_EGRESSBW_LSB_REG(port); + + retVal = rtl8367c_getAsicReg(regAddr, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + regAddr = RTL8367C_PORT_EGRESSBW_MSB_REG(port); + retVal = rtl8367c_getAsicRegBits(regAddr, RTL8367C_PORT6_EGRESSBW_CTRL1_MASK, ®Data2); + if(retVal != RT_ERR_OK) + return retVal; + + *rate = regData | (regData2 << RTL8367C_QOS_GRANULARTY_MSB_OFFSET); + + return RT_ERR_OK; +} +/* Function Name: + * rtl8367c_setAsicPortEgressRateIfg + * Description: + * Set per-port egress rate calculate include/exclude IFG + * Input: + * ifg - 1:include IFG 0:exclude IFG + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicPortEgressRateIfg(rtk_uint32 ifg) +{ + ret_t retVal; + + retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_SCHEDULE_WFQ_CTRL, RTL8367C_SCHEDULE_WFQ_CTRL_OFFSET, ifg); + + return retVal; +} +/* Function Name: + * rtl8367c_getAsicPortEgressRateIfg + * Description: + * Get per-port egress rate calculate include/exclude IFG + * Input: + * ifg - 1:include IFG 0:exclude IFG + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicPortEgressRateIfg(rtk_uint32 *ifg) +{ + ret_t retVal; + + retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_SCHEDULE_WFQ_CTRL, RTL8367C_SCHEDULE_WFQ_CTRL_OFFSET, ifg); + + return retVal; +} diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_scheduling.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_scheduling.h new file mode 100644 index 00000000..b7f64f1d --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_scheduling.h @@ -0,0 +1,41 @@ +#ifndef _RTL8367C_ASICDRV_SCHEDULING_H_ +#define _RTL8367C_ASICDRV_SCHEDULING_H_ + +#include + +#define RTL8367C_QWEIGHTMAX 0x7F +#define RTL8367C_PORT_QUEUE_METER_INDEX_MAX 7 + +/* enum for queue type */ +enum QUEUETYPE +{ + QTYPE_STRICT = 0, + QTYPE_WFQ, +}; +extern ret_t rtl8367c_setAsicLeakyBucketParameter(rtk_uint32 tick, rtk_uint32 token); +extern ret_t rtl8367c_getAsicLeakyBucketParameter(rtk_uint32 *tick, rtk_uint32 *token); +extern ret_t rtl8367c_setAsicAprMeter(rtk_uint32 port, rtk_uint32 qid, rtk_uint32 apridx); +extern ret_t rtl8367c_getAsicAprMeter(rtk_uint32 port, rtk_uint32 qid, rtk_uint32 *apridx); +extern ret_t rtl8367c_setAsicPprMeter(rtk_uint32 port, rtk_uint32 qid, rtk_uint32 ppridx); +extern ret_t rtl8367c_getAsicPprMeter(rtk_uint32 port, rtk_uint32 qid, rtk_uint32 *ppridx); +extern ret_t rtl8367c_setAsicAprEnable(rtk_uint32 port, rtk_uint32 aprEnable); +extern ret_t rtl8367c_getAsicAprEnable(rtk_uint32 port, rtk_uint32 *aprEnable); +extern ret_t rtl8367c_setAsicPprEnable(rtk_uint32 port, rtk_uint32 pprEnable); +extern ret_t rtl8367c_getAsicPprEnable(rtk_uint32 port, rtk_uint32 *pprEnable); + +extern ret_t rtl8367c_setAsicWFQWeight(rtk_uint32, rtk_uint32 queueid, rtk_uint32 weight ); +extern ret_t rtl8367c_getAsicWFQWeight(rtk_uint32, rtk_uint32 queueid, rtk_uint32 *weight ); +extern ret_t rtl8367c_setAsicWFQBurstSize(rtk_uint32 burstsize); +extern ret_t rtl8367c_getAsicWFQBurstSize(rtk_uint32 *burstsize); + +extern ret_t rtl8367c_setAsicQueueType(rtk_uint32 port, rtk_uint32 qid, rtk_uint32 queueType); +extern ret_t rtl8367c_getAsicQueueType(rtk_uint32 port, rtk_uint32 qid, rtk_uint32 *queueType); +extern ret_t rtl8367c_setAsicQueueRate(rtk_uint32 port, rtk_uint32 qid, rtk_uint32 ppridx, rtk_uint32 apridx ); +extern ret_t rtl8367c_getAsicQueueRate(rtk_uint32 port, rtk_uint32 qid, rtk_uint32* ppridx, rtk_uint32* apridx ); +extern ret_t rtl8367c_setAsicPortEgressRate(rtk_uint32 port, rtk_uint32 rate); +extern ret_t rtl8367c_getAsicPortEgressRate(rtk_uint32 port, rtk_uint32 *rate); +extern ret_t rtl8367c_setAsicPortEgressRateIfg(rtk_uint32 ifg); +extern ret_t rtl8367c_getAsicPortEgressRateIfg(rtk_uint32 *ifg); + +#endif /*_RTL8367C_ASICDRV_SCHEDULING_H_*/ + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_storm.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_storm.c new file mode 100644 index 00000000..9964a074 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_storm.c @@ -0,0 +1,853 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTL8367C switch high-level API for RTL8367C + * Feature : Storm control filtering related functions + * + */ + +#include +/* Function Name: + * rtl8367c_setAsicStormFilterBroadcastEnable + * Description: + * Set per-port broadcast storm filter enable/disable + * Input: + * port - Physical port number (0~7) + * enabled - 1: enabled, 0: disabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_setAsicStormFilterBroadcastEnable(rtk_uint32 port, rtk_uint32 enabled) +{ + if(port >= RTL8367C_PORTNO) + return RT_ERR_PORT_ID; + + return rtl8367c_setAsicRegBit(RTL8367C_STORM_BCAST_REG, port, enabled); +} +/* Function Name: + * rtl8367c_getAsicStormFilterBroadcastEnable + * Description: + * Get per-port broadcast storm filter enable/disable + * Input: + * port - Physical port number (0~7) + * pEnabled - 1: enabled, 0: disabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_getAsicStormFilterBroadcastEnable(rtk_uint32 port, rtk_uint32 *pEnabled) +{ + if(port >= RTL8367C_PORTNO) + return RT_ERR_PORT_ID; + + return rtl8367c_getAsicRegBit(RTL8367C_STORM_BCAST_REG, port, pEnabled); +} +/* Function Name: + * rtl8367c_setAsicStormFilterBroadcastMeter + * Description: + * Set per-port broadcast storm filter meter + * Input: + * port - Physical port number (0~7) + * meter - meter index (0~31) + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * RT_ERR_FILTER_METER_ID - Invalid meter index + * Note: + * None + */ +ret_t rtl8367c_setAsicStormFilterBroadcastMeter(rtk_uint32 port, rtk_uint32 meter) +{ + if(port >= RTL8367C_PORTNO) + return RT_ERR_PORT_ID; + + if(meter > RTL8367C_METERMAX) + return RT_ERR_FILTER_METER_ID; + + return rtl8367c_setAsicRegBits(RTL8367C_STORM_BCAST_METER_CTRL_REG(port), RTL8367C_STORM_BCAST_METER_CTRL_MASK(port), meter); +} +/* Function Name: + * rtl8367c_getAsicStormFilterBroadcastMeter + * Description: + * Get per-port broadcast storm filter meter + * Input: + * port - Physical port number (0~7) + * pMeter - meter index (0~31) + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_getAsicStormFilterBroadcastMeter(rtk_uint32 port, rtk_uint32 *pMeter) +{ + if(port >= RTL8367C_PORTNO) + return RT_ERR_PORT_ID; + + return rtl8367c_getAsicRegBits(RTL8367C_STORM_BCAST_METER_CTRL_REG(port), RTL8367C_STORM_BCAST_METER_CTRL_MASK(port), pMeter); +} +/* Function Name: + * rtl8367c_setAsicStormFilterMulticastEnable + * Description: + * Set per-port multicast storm filter enable/disable + * Input: + * port - Physical port number (0~7) + * enabled - 1: enabled, 0: disabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_setAsicStormFilterMulticastEnable(rtk_uint32 port, rtk_uint32 enabled) +{ + if(port >= RTL8367C_PORTNO) + return RT_ERR_PORT_ID; + + return rtl8367c_setAsicRegBit(RTL8367C_STORM_MCAST_REG, port, enabled); +} +/* Function Name: + * rtl8367c_getAsicStormFilterMulticastEnable + * Description: + * Get per-port multicast storm filter enable/disable + * Input: + * port - Physical port number (0~7) + * pEnabled - 1: enabled, 0: disabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_getAsicStormFilterMulticastEnable(rtk_uint32 port, rtk_uint32 *pEnabled) +{ + if(port >= RTL8367C_PORTNO) + return RT_ERR_PORT_ID; + + return rtl8367c_getAsicRegBit(RTL8367C_STORM_MCAST_REG, port, pEnabled); +} +/* Function Name: + * rtl8367c_setAsicStormFilterMulticastMeter + * Description: + * Set per-port multicast storm filter meter + * Input: + * port - Physical port number (0~7) + * meter - meter index (0~31) + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * RT_ERR_FILTER_METER_ID - Invalid meter index + * Note: + * None + */ +ret_t rtl8367c_setAsicStormFilterMulticastMeter(rtk_uint32 port, rtk_uint32 meter) +{ + if(port >= RTL8367C_PORTNO) + return RT_ERR_PORT_ID; + + if(meter > RTL8367C_METERMAX) + return RT_ERR_FILTER_METER_ID; + + return rtl8367c_setAsicRegBits(RTL8367C_STORM_MCAST_METER_CTRL_REG(port), RTL8367C_STORM_MCAST_METER_CTRL_MASK(port), meter); +} +/* Function Name: + * rtl8367c_getAsicStormFilterMulticastMeter + * Description: + * Get per-port multicast storm filter meter + * Input: + * port - Physical port number (0~7) + * pMeter - meter index (0~31) + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_getAsicStormFilterMulticastMeter(rtk_uint32 port, rtk_uint32 *pMeter) +{ + if(port >= RTL8367C_PORTNO) + return RT_ERR_PORT_ID; + + return rtl8367c_getAsicRegBits(RTL8367C_STORM_MCAST_METER_CTRL_REG(port), RTL8367C_STORM_MCAST_METER_CTRL_MASK(port), pMeter); +} +/* Function Name: + * rtl8367c_setAsicStormFilterUnknownMulticastEnable + * Description: + * Set per-port unknown multicast storm filter enable/disable + * Input: + * port - Physical port number (0~7) + * enabled - 1: enabled, 0: disabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_setAsicStormFilterUnknownMulticastEnable(rtk_uint32 port, rtk_uint32 enabled) +{ + if(port >= RTL8367C_PORTNO) + return RT_ERR_PORT_ID; + + return rtl8367c_setAsicRegBit(RTL8367C_STORM_UNKNOWN_MCAST_REG, port, enabled); +} +/* Function Name: + * rtl8367c_getAsicStormFilterUnknownMulticastEnable + * Description: + * Get per-port unknown multicast storm filter enable/disable + * Input: + * port - Physical port number (0~7) + * pEnabled - 1: enabled, 0: disabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_getAsicStormFilterUnknownMulticastEnable(rtk_uint32 port, rtk_uint32 *pEnabled) +{ + if(port >= RTL8367C_PORTNO) + return RT_ERR_PORT_ID; + + return rtl8367c_getAsicRegBit(RTL8367C_STORM_UNKNOWN_MCAST_REG, port, pEnabled); +} +/* Function Name: + * rtl8367c_setAsicStormFilterUnknownMulticastMeter + * Description: + * Set per-port unknown multicast storm filter meter + * Input: + * port - Physical port number (0~7) + * meter - meter index (0~31) + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * RT_ERR_FILTER_METER_ID - Invalid meter index + * Note: + * None + */ +ret_t rtl8367c_setAsicStormFilterUnknownMulticastMeter(rtk_uint32 port, rtk_uint32 meter) +{ + ret_t retVal; + + if(port >= RTL8367C_PORTNO) + return RT_ERR_PORT_ID; + + if(meter > RTL8367C_METERMAX) + return RT_ERR_FILTER_METER_ID; + + if(port < 8) + { + retVal = rtl8367c_setAsicRegBits(RTL8367C_STORM_UNMC_METER_CTRL_REG(port), RTL8367C_STORM_UNMC_METER_CTRL_MASK(port), meter); + if(retVal != RT_ERR_OK) + return retVal; + } + else + { + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_STORM_UNMC_METER_CTRL4 + ((port - 8) >> 1), RTL8367C_STORM_UNMC_METER_CTRL_MASK(port), meter); + if(retVal != RT_ERR_OK) + return retVal; + } + + return RT_ERR_OK; +} +/* Function Name: + * rtl8367c_getAsicStormFilterUnknownMulticastMeter + * Description: + * Get per-port unknown multicast storm filter meter + * Input: + * port - Physical port number (0~7) + * pMeter - meter index (0~31) + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_getAsicStormFilterUnknownMulticastMeter(rtk_uint32 port, rtk_uint32 *pMeter) +{ + ret_t retVal; + + if(port >= RTL8367C_PORTNO) + return RT_ERR_PORT_ID; + + if(port < 8) + { + retVal = rtl8367c_getAsicRegBits(RTL8367C_STORM_UNMC_METER_CTRL_REG(port), RTL8367C_STORM_UNMC_METER_CTRL_MASK(port), pMeter); + if(retVal != RT_ERR_OK) + return retVal; + } + else + { + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_STORM_UNMC_METER_CTRL4 + ((port - 8) >> 1), RTL8367C_STORM_UNMC_METER_CTRL_MASK(port), pMeter); + if(retVal != RT_ERR_OK) + return retVal; + } + + return RT_ERR_OK; +} +/* Function Name: + * rtl8367c_setAsicStormFilterUnknownUnicastEnable + * Description: + * Set per-port unknown unicast storm filter enable/disable + * Input: + * port - Physical port number (0~7) + * enabled - 1: enabled, 0: disabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_setAsicStormFilterUnknownUnicastEnable(rtk_uint32 port, rtk_uint32 enabled) +{ + if(port >= RTL8367C_PORTNO) + return RT_ERR_PORT_ID; + + return rtl8367c_setAsicRegBit(RTL8367C_STORM_UNKNOWN_UCAST_REG, port, enabled); +} +/* Function Name: + * rtl8367c_getAsicStormFilterUnknownUnicastEnable + * Description: + * get per-port unknown unicast storm filter enable/disable + * Input: + * port - Physical port number (0~7) + * pEnabled - 1: enabled, 0: disabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_getAsicStormFilterUnknownUnicastEnable(rtk_uint32 port, rtk_uint32 *pEnabled) +{ + if(port >= RTL8367C_PORTNO) + return RT_ERR_PORT_ID; + + return rtl8367c_getAsicRegBit(RTL8367C_STORM_UNKNOWN_UCAST_REG, port, pEnabled); +} +/* Function Name: + * rtl8367c_setAsicStormFilterUnknownUnicastMeter + * Description: + * Set per-port unknown unicast storm filter meter + * Input: + * port - Physical port number (0~7) + * meter - meter index (0~31) + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * RT_ERR_FILTER_METER_ID - Invalid meter index + * Note: + * None + */ +ret_t rtl8367c_setAsicStormFilterUnknownUnicastMeter(rtk_uint32 port, rtk_uint32 meter) +{ + if(port >= RTL8367C_PORTNO) + return RT_ERR_PORT_ID; + + if(meter > RTL8367C_METERMAX) + return RT_ERR_FILTER_METER_ID; + + return rtl8367c_setAsicRegBits(RTL8367C_STORM_UNDA_METER_CTRL_REG(port), RTL8367C_STORM_UNDA_METER_CTRL_MASK(port), meter); +} +/* Function Name: + * rtl8367c_getAsicStormFilterUnknownUnicastMeter + * Description: + * Get per-port unknown unicast storm filter meter + * Input: + * port - Physical port number (0~7) + * pMeter - meter index (0~31) + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_getAsicStormFilterUnknownUnicastMeter(rtk_uint32 port, rtk_uint32 *pMeter) +{ + if(port >= RTL8367C_PORTNO) + return RT_ERR_PORT_ID; + + return rtl8367c_getAsicRegBits(RTL8367C_STORM_UNDA_METER_CTRL_REG(port), RTL8367C_STORM_UNDA_METER_CTRL_MASK(port), pMeter); +} + +/* Function Name: + * rtl8367c_setAsicStormFilterExtBroadcastMeter + * Description: + * Set extension broadcast storm filter meter + * Input: + * meter - meter index (0~31) + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_METER_ID - Invalid meter index + * Note: + * None + */ +ret_t rtl8367c_setAsicStormFilterExtBroadcastMeter(rtk_uint32 meter) +{ + if(meter > RTL8367C_METERMAX) + return RT_ERR_FILTER_METER_ID; + + return rtl8367c_setAsicRegBits(RTL8367C_REG_STORM_EXT_MTRIDX_CFG0, RTL8367C_BC_STORM_EXT_METERIDX_MASK, meter); +} + +/* Function Name: + * rtl8367c_getAsicStormFilterExtBroadcastMeter + * Description: + * get extension broadcast storm filter meter + * Input: + * None + * Output: + * pMeter - meter index (0~31) + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Invalid meter index + * Note: + * None + */ +ret_t rtl8367c_getAsicStormFilterExtBroadcastMeter(rtk_uint32 *pMeter) +{ + if(NULL == pMeter) + return RT_ERR_NULL_POINTER; + + return rtl8367c_getAsicRegBits(RTL8367C_REG_STORM_EXT_MTRIDX_CFG0, RTL8367C_BC_STORM_EXT_METERIDX_MASK, pMeter); +} + +/* Function Name: + * rtl8367c_setAsicStormFilterExtMulticastMeter + * Description: + * Set extension multicast storm filter meter + * Input: + * meter - meter index (0~31) + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_METER_ID - Invalid meter index + * Note: + * None + */ +ret_t rtl8367c_setAsicStormFilterExtMulticastMeter(rtk_uint32 meter) +{ + if(meter > RTL8367C_METERMAX) + return RT_ERR_FILTER_METER_ID; + + return rtl8367c_setAsicRegBits(RTL8367C_REG_STORM_EXT_MTRIDX_CFG0, RTL8367C_MC_STORM_EXT_METERIDX_MASK, meter); +} + +/* Function Name: + * rtl8367c_getAsicStormFilterExtMulticastMeter + * Description: + * get extension multicast storm filter meter + * Input: + * None + * Output: + * pMeter - meter index (0~31) + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Invalid meter index + * Note: + * None + */ +ret_t rtl8367c_getAsicStormFilterExtMulticastMeter(rtk_uint32 *pMeter) +{ + if(NULL == pMeter) + return RT_ERR_NULL_POINTER; + + return rtl8367c_getAsicRegBits(RTL8367C_REG_STORM_EXT_MTRIDX_CFG0, RTL8367C_MC_STORM_EXT_METERIDX_MASK, pMeter); +} + +/* Function Name: + * rtl8367c_setAsicStormFilterExtUnknownMulticastMeter + * Description: + * Set extension unknown multicast storm filter meter + * Input: + * meter - meter index (0~31) + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_METER_ID - Invalid meter index + * Note: + * None + */ +ret_t rtl8367c_setAsicStormFilterExtUnknownMulticastMeter(rtk_uint32 meter) +{ + if(meter > RTL8367C_METERMAX) + return RT_ERR_FILTER_METER_ID; + + return rtl8367c_setAsicRegBits(RTL8367C_REG_STORM_EXT_MTRIDX_CFG1, RTL8367C_UNMC_STORM_EXT_METERIDX_MASK, meter); +} + +/* Function Name: + * rtl8367c_getAsicStormFilterExtUnknownMulticastMeter + * Description: + * get extension unknown multicast storm filter meter + * Input: + * None + * Output: + * pMeter - meter index (0~31) + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Invalid meter index + * Note: + * None + */ +ret_t rtl8367c_getAsicStormFilterExtUnknownMulticastMeter(rtk_uint32 *pMeter) +{ + if(NULL == pMeter) + return RT_ERR_NULL_POINTER; + + return rtl8367c_getAsicRegBits(RTL8367C_REG_STORM_EXT_MTRIDX_CFG1, RTL8367C_UNMC_STORM_EXT_METERIDX_MASK, pMeter); +} + +/* Function Name: + * rtl8367c_setAsicStormFilterExtUnknownUnicastMeter + * Description: + * Set extension unknown unicast storm filter meter + * Input: + * meter - meter index (0~31) + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_METER_ID - Invalid meter index + * Note: + * None + */ +ret_t rtl8367c_setAsicStormFilterExtUnknownUnicastMeter(rtk_uint32 meter) +{ + if(meter > RTL8367C_METERMAX) + return RT_ERR_FILTER_METER_ID; + + return rtl8367c_setAsicRegBits(RTL8367C_REG_STORM_EXT_MTRIDX_CFG1, RTL8367C_UNUC_STORM_EXT_METERIDX_MASK, meter); +} + +/* Function Name: + * rtl8367c_getAsicStormFilterExtUnknownUnicastMeter + * Description: + * get extension unknown unicast storm filter meter + * Input: + * None + * Output: + * pMeter - meter index (0~31) + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Invalid meter index + * Note: + * None + */ +ret_t rtl8367c_getAsicStormFilterExtUnknownUnicastMeter(rtk_uint32 *pMeter) +{ + if(NULL == pMeter) + return RT_ERR_NULL_POINTER; + + return rtl8367c_getAsicRegBits(RTL8367C_REG_STORM_EXT_MTRIDX_CFG1, RTL8367C_UNUC_STORM_EXT_METERIDX_MASK, pMeter); +} + +/* Function Name: + * rtl8367c_setAsicStormFilterExtBroadcastEnable + * Description: + * Set extension broadcast storm filter state + * Input: + * enabled - state + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicStormFilterExtBroadcastEnable(rtk_uint32 enabled) +{ + return rtl8367c_setAsicRegBit(RTL8367C_REG_STORM_EXT_CFG, RTL8367C_STORM_BCAST_EXT_EN_OFFSET, enabled); +} + +/* Function Name: + * rtl8367c_getAsicStormFilterExtBroadcastEnable + * Description: + * Get extension broadcast storm filter state + * Input: + * None + * Output: + * pEnabled - state + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * None + */ +ret_t rtl8367c_getAsicStormFilterExtBroadcastEnable(rtk_uint32 *pEnabled) +{ + if(NULL == pEnabled) + return RT_ERR_NULL_POINTER; + + return rtl8367c_getAsicRegBit(RTL8367C_REG_STORM_EXT_CFG, RTL8367C_STORM_BCAST_EXT_EN_OFFSET, pEnabled); +} + +/* Function Name: + * rtl8367c_setAsicStormFilterExtMulticastEnable + * Description: + * Set extension multicast storm filter state + * Input: + * enabled - state + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicStormFilterExtMulticastEnable(rtk_uint32 enabled) +{ + return rtl8367c_setAsicRegBit(RTL8367C_REG_STORM_EXT_CFG, RTL8367C_STORM_MCAST_EXT_EN_OFFSET, enabled); +} + +/* Function Name: + * rtl8367c_getAsicStormFilterExtMulticastEnable + * Description: + * Get extension multicast storm filter state + * Input: + * None + * Output: + * pEnabled - state + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * None + */ +ret_t rtl8367c_getAsicStormFilterExtMulticastEnable(rtk_uint32 *pEnabled) +{ + if(NULL == pEnabled) + return RT_ERR_NULL_POINTER; + + return rtl8367c_getAsicRegBit(RTL8367C_REG_STORM_EXT_CFG, RTL8367C_STORM_MCAST_EXT_EN_OFFSET, pEnabled); +} + +/* Function Name: + * rtl8367c_setAsicStormFilterExtUnknownMulticastEnable + * Description: + * Set extension unknown multicast storm filter state + * Input: + * enabled - state + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicStormFilterExtUnknownMulticastEnable(rtk_uint32 enabled) +{ + return rtl8367c_setAsicRegBit(RTL8367C_REG_STORM_EXT_CFG, RTL8367C_STORM_UNKNOWN_MCAST_EXT_EN_OFFSET, enabled); +} + +/* Function Name: + * rtl8367c_getAsicStormFilterExtUnknownMulticastEnable + * Description: + * Get extension unknown multicast storm filter state + * Input: + * None + * Output: + * pEnabled - state + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * None + */ +ret_t rtl8367c_getAsicStormFilterExtUnknownMulticastEnable(rtk_uint32 *pEnabled) +{ + if(NULL == pEnabled) + return RT_ERR_NULL_POINTER; + + return rtl8367c_getAsicRegBit(RTL8367C_REG_STORM_EXT_CFG, RTL8367C_STORM_UNKNOWN_MCAST_EXT_EN_OFFSET, pEnabled); +} + +/* Function Name: + * rtl8367c_setAsicStormFilterExtUnknownUnicastEnable + * Description: + * Set extension unknown unicast storm filter state + * Input: + * enabled - state + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicStormFilterExtUnknownUnicastEnable(rtk_uint32 enabled) +{ + return rtl8367c_setAsicRegBit(RTL8367C_REG_STORM_EXT_CFG, RTL8367C_STORM_UNKNOWN_UCAST_EXT_EN_OFFSET, enabled); +} + +/* Function Name: + * rtl8367c_getAsicStormFilterExtUnknownUnicastEnable + * Description: + * Get extension unknown unicast storm filter state + * Input: + * None + * Output: + * pEnabled - state + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * None + */ +ret_t rtl8367c_getAsicStormFilterExtUnknownUnicastEnable(rtk_uint32 *pEnabled) +{ + if(NULL == pEnabled) + return RT_ERR_NULL_POINTER; + + return rtl8367c_getAsicRegBit(RTL8367C_REG_STORM_EXT_CFG, RTL8367C_STORM_UNKNOWN_UCAST_EXT_EN_OFFSET, pEnabled); +} + +/* Function Name: + * rtl8367c_setAsicStormFilterExtEnablePortMask + * Description: + * Set extension storm filter port mask + * Input: + * portmask - port mask + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicStormFilterExtEnablePortMask(rtk_uint32 portmask) +{ + ret_t retVal; + + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_STORM_EXT_CFG, RTL8367C_STORM_EXT_EN_PORTMASK_MASK, portmask & 0x3FF); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_STORM_EXT_CFG, RTL8367C_STORM_EXT_EN_PORTMASK_EXT_MASK, (portmask >> 10)&1); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_getAsicStormFilterExtEnablePortMask + * Description: + * Get extension storm filter port mask + * Input: + * portmask - port mask + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * None + */ +ret_t rtl8367c_getAsicStormFilterExtEnablePortMask(rtk_uint32 *pPortmask) +{ + rtk_uint32 tmpPmsk; + ret_t retVal; + + if(NULL == pPortmask) + return RT_ERR_NULL_POINTER; + + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_STORM_EXT_CFG, RTL8367C_STORM_EXT_EN_PORTMASK_MASK, &tmpPmsk); + if(retVal != RT_ERR_OK) + return retVal; + *pPortmask = tmpPmsk & 0x3ff; + + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_STORM_EXT_CFG, RTL8367C_STORM_EXT_EN_PORTMASK_EXT_MASK, &tmpPmsk); + if(retVal != RT_ERR_OK) + return retVal; + *pPortmask |= (tmpPmsk & 1) << 10; + + return RT_ERR_OK; +} + + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_storm.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_storm.h new file mode 100644 index 00000000..6d263ccf --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_storm.h @@ -0,0 +1,44 @@ +#ifndef _RTL8367C_ASICDRV_STORM_H_ +#define _RTL8367C_ASICDRV_STORM_H_ + +#include + +extern ret_t rtl8367c_setAsicStormFilterBroadcastEnable(rtk_uint32 port, rtk_uint32 enabled); +extern ret_t rtl8367c_getAsicStormFilterBroadcastEnable(rtk_uint32 port, rtk_uint32 *pEnabled); +extern ret_t rtl8367c_setAsicStormFilterBroadcastMeter(rtk_uint32 port, rtk_uint32 meter); +extern ret_t rtl8367c_getAsicStormFilterBroadcastMeter(rtk_uint32 port, rtk_uint32 *pMeter); +extern ret_t rtl8367c_setAsicStormFilterMulticastEnable(rtk_uint32 port, rtk_uint32 enabled); +extern ret_t rtl8367c_getAsicStormFilterMulticastEnable(rtk_uint32 port, rtk_uint32 *pEnabled); +extern ret_t rtl8367c_setAsicStormFilterMulticastMeter(rtk_uint32 port, rtk_uint32 meter); +extern ret_t rtl8367c_getAsicStormFilterMulticastMeter(rtk_uint32 port, rtk_uint32 *pMeter); +extern ret_t rtl8367c_setAsicStormFilterUnknownMulticastEnable(rtk_uint32 port, rtk_uint32 enabled); +extern ret_t rtl8367c_getAsicStormFilterUnknownMulticastEnable(rtk_uint32 port, rtk_uint32 *pEnabled); +extern ret_t rtl8367c_setAsicStormFilterUnknownMulticastMeter(rtk_uint32 port, rtk_uint32 meter); +extern ret_t rtl8367c_getAsicStormFilterUnknownMulticastMeter(rtk_uint32 port, rtk_uint32 *pMeter); +extern ret_t rtl8367c_setAsicStormFilterUnknownUnicastEnable(rtk_uint32 port, rtk_uint32 enabled); +extern ret_t rtl8367c_getAsicStormFilterUnknownUnicastEnable(rtk_uint32 port, rtk_uint32 *pEnabled); +extern ret_t rtl8367c_setAsicStormFilterUnknownUnicastMeter(rtk_uint32 port, rtk_uint32 meter); +extern ret_t rtl8367c_getAsicStormFilterUnknownUnicastMeter(rtk_uint32 port, rtk_uint32 *pMeter); +extern ret_t rtl8367c_setAsicStormFilterExtBroadcastMeter(rtk_uint32 meter); +extern ret_t rtl8367c_getAsicStormFilterExtBroadcastMeter(rtk_uint32 *pMeter); +extern ret_t rtl8367c_setAsicStormFilterExtMulticastMeter(rtk_uint32 meter); +extern ret_t rtl8367c_getAsicStormFilterExtMulticastMeter(rtk_uint32 *pMeter); +extern ret_t rtl8367c_setAsicStormFilterExtUnknownMulticastMeter(rtk_uint32 meter); +extern ret_t rtl8367c_getAsicStormFilterExtUnknownMulticastMeter(rtk_uint32 *pMeter); +extern ret_t rtl8367c_setAsicStormFilterExtUnknownUnicastMeter(rtk_uint32 meter); +extern ret_t rtl8367c_getAsicStormFilterExtUnknownUnicastMeter(rtk_uint32 *pMeter); +extern ret_t rtl8367c_setAsicStormFilterExtBroadcastEnable(rtk_uint32 enabled); +extern ret_t rtl8367c_getAsicStormFilterExtBroadcastEnable(rtk_uint32 *pEnabled); +extern ret_t rtl8367c_setAsicStormFilterExtMulticastEnable(rtk_uint32 enabled); +extern ret_t rtl8367c_getAsicStormFilterExtMulticastEnable(rtk_uint32 *pEnabled); +extern ret_t rtl8367c_setAsicStormFilterExtUnknownMulticastEnable(rtk_uint32 enabled); +extern ret_t rtl8367c_getAsicStormFilterExtUnknownMulticastEnable(rtk_uint32 *pEnabled); +extern ret_t rtl8367c_setAsicStormFilterExtUnknownUnicastEnable(rtk_uint32 enabled); +extern ret_t rtl8367c_getAsicStormFilterExtUnknownUnicastEnable(rtk_uint32 *pEnabled); +extern ret_t rtl8367c_setAsicStormFilterExtEnablePortMask(rtk_uint32 portmask); +extern ret_t rtl8367c_getAsicStormFilterExtEnablePortMask(rtk_uint32 *pPortmask); + + +#endif /*_RTL8367C_ASICDRV_STORM_H_*/ + + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_svlan.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_svlan.c new file mode 100644 index 00000000..8c1e1df8 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_svlan.c @@ -0,0 +1,1007 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTL8367C switch high-level API for RTL8367C + * Feature : SVLAN related functions + * + */ +#include + +#include + +static void _rtl8367c_svlanConfStUser2Smi( rtl8367c_svlan_memconf_t *pUserSt, rtk_uint16 *pSmiSt) +{ + pSmiSt[0] |= (pUserSt->vs_member & 0x00FF); + pSmiSt[0] |= (pUserSt->vs_untag & 0x00FF) << 8; + + pSmiSt[1] |= (pUserSt->vs_fid_msti & 0x000F); + pSmiSt[1] |= (pUserSt->vs_priority & 0x0007) << 4; + pSmiSt[1] |= (pUserSt->vs_force_fid & 0x0001) << 7; + + pSmiSt[2] |= (pUserSt->vs_svid & 0x0FFF); + pSmiSt[2] |= (pUserSt->vs_efiden & 0x0001) << 12; + pSmiSt[2] |= (pUserSt->vs_efid & 0x0007) << 13; + + pSmiSt[3] |= ((pUserSt->vs_member & 0x0700) >> 8); + pSmiSt[3] |= ((pUserSt->vs_untag & 0x0700) >> 8) << 8; +} + +static void _rtl8367c_svlanConfStSmi2User( rtl8367c_svlan_memconf_t *pUserSt, rtk_uint16 *pSmiSt) +{ + + pUserSt->vs_member = (pSmiSt[0] & 0x00FF) | ((pSmiSt[3] & 0x0007) << 8); + pUserSt->vs_untag = ((pSmiSt[0] & 0xFF00) >> 8) | (((pSmiSt[3] & 0x0700) >> 8) << 8); + + pUserSt->vs_fid_msti = (pSmiSt[1] & 0x000F); + pUserSt->vs_priority = (pSmiSt[1] & 0x0070) >> 4; + pUserSt->vs_force_fid = (pSmiSt[1] & 0x0080) >> 7; + + pUserSt->vs_svid = (pSmiSt[2] & 0x0FFF); + pUserSt->vs_efiden = (pSmiSt[2] & 0x1000) >> 12; + pUserSt->vs_efid = (pSmiSt[2] & 0xE000) >> 13; +} + +static void _rtl8367c_svlanMc2sStUser2Smi(rtl8367c_svlan_mc2s_t *pUserSt, rtk_uint16 *pSmiSt) +{ + pSmiSt[0] |= (pUserSt->svidx & 0x003F); + pSmiSt[0] |= (pUserSt->format & 0x0001) << 6; + pSmiSt[0] |= (pUserSt->valid & 0x0001) << 7; + + pSmiSt[1] = (rtk_uint16)(pUserSt->smask & 0x0000FFFF); + pSmiSt[2] = (rtk_uint16)((pUserSt->smask & 0xFFFF0000) >> 16); + + pSmiSt[3] = (rtk_uint16)(pUserSt->sdata & 0x0000FFFF); + pSmiSt[4] = (rtk_uint16)((pUserSt->sdata & 0xFFFF0000) >> 16); +} + +static void _rtl8367c_svlanMc2sStSmi2User(rtl8367c_svlan_mc2s_t *pUserSt, rtk_uint16 *pSmiSt) +{ + pUserSt->svidx = (pSmiSt[0] & 0x003F); + pUserSt->format = (pSmiSt[0] & 0x0040) >> 6; + pUserSt->valid = (pSmiSt[0] & 0x0080) >> 7; + + pUserSt->smask = pSmiSt[1] | (pSmiSt[2] << 16); + pUserSt->sdata = pSmiSt[3] | (pSmiSt[4] << 16); +} + +static void _rtl8367c_svlanSp2cStUser2Smi(rtl8367c_svlan_s2c_t *pUserSt, rtk_uint16 *pSmiSt) +{ + pSmiSt[0] |= (pUserSt->dstport & 0x0007); + pSmiSt[0] |= (pUserSt->svidx & 0x003F) << 3; + pSmiSt[0] |= ((pUserSt->dstport & 0x0008) >> 3) << 9; + + pSmiSt[1] |= (pUserSt->vid & 0x0FFF); + pSmiSt[1] |= (pUserSt->valid & 0x0001) << 12; +} + +static void _rtl8367c_svlanSp2cStSmi2User(rtl8367c_svlan_s2c_t *pUserSt, rtk_uint16 *pSmiSt) +{ + pUserSt->dstport = (((pSmiSt[0] & 0x0200) >> 9) << 3) | (pSmiSt[0] & 0x0007); + pUserSt->svidx = (pSmiSt[0] & 0x01F8) >> 3; + pUserSt->vid = (pSmiSt[1] & 0x0FFF); + pUserSt->valid = (pSmiSt[1] & 0x1000) >> 12; +} + +/* Function Name: + * rtl8367c_setAsicSvlanUplinkPortMask + * Description: + * Set uplink ports mask + * Input: + * portMask - Uplink port mask setting + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicSvlanUplinkPortMask(rtk_uint32 portMask) +{ + return rtl8367c_setAsicReg(RTL8367C_REG_SVLAN_UPLINK_PORTMASK, portMask); +} +/* Function Name: + * rtl8367c_getAsicSvlanUplinkPortMask + * Description: + * Get uplink ports mask + * Input: + * pPortmask - Uplink port mask setting + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicSvlanUplinkPortMask(rtk_uint32* pPortmask) +{ + return rtl8367c_getAsicReg(RTL8367C_REG_SVLAN_UPLINK_PORTMASK, pPortmask); +} +/* Function Name: + * rtl8367c_setAsicSvlanTpid + * Description: + * Set accepted S-VLAN ether type. The default ether type of S-VLAN is 0x88a8 + * Input: + * protocolType - Ether type of S-tag frame parsing in uplink ports + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * Ether type of S-tag in 802.1ad is 0x88a8 and there are existed ether type 0x9100 and 0x9200 + * for Q-in-Q SLAN design. User can set mathced ether type as service provider supported protocol + */ +ret_t rtl8367c_setAsicSvlanTpid(rtk_uint32 protocolType) +{ + return rtl8367c_setAsicReg(RTL8367C_REG_VS_TPID, protocolType); +} +/* Function Name: + * rtl8367c_getAsicReg + * Description: + * Get accepted S-VLAN ether type. The default ether type of S-VLAN is 0x88a8 + * Input: + * pProtocolType - Ether type of S-tag frame parsing in uplink ports + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicSvlanTpid(rtk_uint32* pProtocolType) +{ + return rtl8367c_getAsicReg(RTL8367C_REG_VS_TPID, pProtocolType); +} +/* Function Name: + * rtl8367c_setAsicSvlanPrioritySel + * Description: + * Set SVLAN priority field setting + * Input: + * priSel - S-priority assignment method, 0:internal priority 1:C-tag priority 2:using Svlan member configuration + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter + * Note: + * None + */ +ret_t rtl8367c_setAsicSvlanPrioritySel(rtk_uint32 priSel) +{ + if(priSel >= SPRISEL_END) + return RT_ERR_QOS_INT_PRIORITY; + + return rtl8367c_setAsicRegBits(RTL8367C_REG_SVLAN_CFG, RTL8367C_VS_SPRISEL_MASK, priSel); +} +/* Function Name: + * rtl8367c_getAsicSvlanPrioritySel + * Description: + * Get SVLAN priority field setting + * Input: + * pPriSel - S-priority assignment method, 0:internal priority 1:C-tag priority 2:using Svlan member configuration + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicSvlanPrioritySel(rtk_uint32* pPriSel) +{ + return rtl8367c_getAsicRegBits(RTL8367C_REG_SVLAN_CFG, RTL8367C_VS_SPRISEL_MASK, pPriSel); +} +/* Function Name: + * rtl8367c_setAsicSvlanTrapPriority + * Description: + * Set trap to CPU priority assignment + * Input: + * priority - Priority assignment + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_INT_PRIORITY - Invalid priority + * Note: + * None + */ +ret_t rtl8367c_setAsicSvlanTrapPriority(rtk_uint32 priority) +{ + if(priority > RTL8367C_PRIMAX) + return RT_ERR_QOS_INT_PRIORITY; + + return rtl8367c_setAsicRegBits(RTL8367C_REG_QOS_TRAP_PRIORITY0, RTL8367C_SVLAN_PRIOIRTY_MASK, priority); +} +/* Function Name: + * rtl8367c_getAsicSvlanTrapPriority + * Description: + * Get trap to CPU priority assignment + * Input: + * pPriority - Priority assignment + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicSvlanTrapPriority(rtk_uint32* pPriority) +{ + return rtl8367c_getAsicRegBits(RTL8367C_REG_QOS_TRAP_PRIORITY0, RTL8367C_SVLAN_PRIOIRTY_MASK, pPriority); +} +/* Function Name: + * rtl8367c_setAsicSvlanDefaultVlan + * Description: + * Set default egress SVLAN + * Input: + * port - Physical port number (0~10) + * index - index SVLAN member configuration + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * RT_ERR_SVLAN_ENTRY_INDEX - Invalid SVLAN index parameter + * Note: + * None + */ +ret_t rtl8367c_setAsicSvlanDefaultVlan(rtk_uint32 port, rtk_uint32 index) +{ + ret_t retVal = RT_ERR_FAILED; + + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + if(index > RTL8367C_SVIDXMAX) + return RT_ERR_SVLAN_ENTRY_INDEX; + + if(port < 8) + { + if(port & 1) + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_SVLAN_PORTBASED_SVIDX_CTRL0 + (port >> 1), RTL8367C_VS_PORT1_SVIDX_MASK,index); + else + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_SVLAN_PORTBASED_SVIDX_CTRL0 + (port >> 1), RTL8367C_VS_PORT0_SVIDX_MASK,index); + } + else + { + switch(port) + { + case 8: + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_SVLAN_PORTBASED_SVIDX_CTRL4, RTL8367C_VS_PORT8_SVIDX_MASK,index); + break; + case 9: + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_SVLAN_PORTBASED_SVIDX_CTRL4, RTL8367C_VS_PORT9_SVIDX_MASK,index); + break; + case 10: + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_SVLAN_PORTBASED_SVIDX_CTRL5, RTL8367C_SVLAN_PORTBASED_SVIDX_CTRL5_MASK,index); + break; + default: + return RT_ERR_PORT_ID; + } + } + + return retVal; +} +/* Function Name: + * rtl8367c_getAsicSvlanDefaultVlan + * Description: + * Get default egress SVLAN + * Input: + * port - Physical port number (0~7) + * pIndex - index SVLAN member configuration + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_getAsicSvlanDefaultVlan(rtk_uint32 port, rtk_uint32* pIndex) +{ + ret_t retVal = RT_ERR_FAILED; + + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + if(port < 8) + { + if(port & 1) + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_SVLAN_PORTBASED_SVIDX_CTRL0 + (port >> 1), RTL8367C_VS_PORT1_SVIDX_MASK,pIndex); + else + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_SVLAN_PORTBASED_SVIDX_CTRL0 + (port >> 1), RTL8367C_VS_PORT0_SVIDX_MASK,pIndex); + } + else + { + switch(port) + { + case 8: + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_SVLAN_PORTBASED_SVIDX_CTRL4, RTL8367C_VS_PORT8_SVIDX_MASK,pIndex); + break; + case 9: + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_SVLAN_PORTBASED_SVIDX_CTRL4, RTL8367C_VS_PORT9_SVIDX_MASK,pIndex); + break; + case 10: + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_SVLAN_PORTBASED_SVIDX_CTRL5, RTL8367C_SVLAN_PORTBASED_SVIDX_CTRL5_MASK,pIndex); + break; + default: + return RT_ERR_PORT_ID; + } + } + + return retVal; + +} +/* Function Name: + * rtl8367c_setAsicSvlanIngressUntag + * Description: + * Set action received un-Stag frame from unplink port + * Input: + * mode - 0:Drop 1:Trap 2:Assign SVLAN + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicSvlanIngressUntag(rtk_uint32 mode) +{ + return rtl8367c_setAsicRegBits(RTL8367C_REG_SVLAN_CFG, RTL8367C_VS_UNTAG_MASK, mode); +} +/* Function Name: + * rtl8367c_getAsicSvlanIngressUntag + * Description: + * Get action received un-Stag frame from unplink port + * Input: + * pMode - 0:Drop 1:Trap 2:Assign SVLAN + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicSvlanIngressUntag(rtk_uint32* pMode) +{ + return rtl8367c_getAsicRegBits(RTL8367C_REG_SVLAN_CFG, RTL8367C_VS_UNTAG_MASK, pMode); +} +/* Function Name: + * rtl8367c_setAsicSvlanIngressUnmatch + * Description: + * Set action received unmatched Stag frame from unplink port + * Input: + * mode - 0:Drop 1:Trap 2:Assign SVLAN + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicSvlanIngressUnmatch(rtk_uint32 mode) +{ + return rtl8367c_setAsicRegBits(RTL8367C_REG_SVLAN_CFG, RTL8367C_VS_UNMAT_MASK, mode); +} +/* Function Name: + * rtl8367c_getAsicSvlanIngressUnmatch + * Description: + * Get action received unmatched Stag frame from unplink port + * Input: + * pMode - 0:Drop 1:Trap 2:Assign SVLAN + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicSvlanIngressUnmatch(rtk_uint32* pMode) +{ + return rtl8367c_getAsicRegBits(RTL8367C_REG_SVLAN_CFG, RTL8367C_VS_UNMAT_MASK, pMode); + +} +/* Function Name: + * rtl8367c_setAsicSvlanEgressUnassign + * Description: + * Set unplink stream without egress SVID action + * Input: + * enabled - 1:Trap egress unassigned frames to CPU, 0: Use SVLAN setup in VS_CPSVIDX as egress SVID + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicSvlanEgressUnassign(rtk_uint32 enabled) +{ + return rtl8367c_setAsicRegBit(RTL8367C_REG_SVLAN_CFG, RTL8367C_VS_UIFSEG_OFFSET, enabled); +} +/* Function Name: + * rtl8367c_getAsicSvlanEgressUnassign + * Description: + * Get unplink stream without egress SVID action + * Input: + * pEnabled - 1:Trap egress unassigned frames to CPU, 0: Use SVLAN setup in VS_CPSVIDX as egress SVID + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicSvlanEgressUnassign(rtk_uint32* pEnabled) +{ + return rtl8367c_getAsicRegBit(RTL8367C_REG_SVLAN_CFG, RTL8367C_VS_UIFSEG_OFFSET, pEnabled); +} + + +/* Function Name: + * rtl8367c_setAsicSvlanMemberConfiguration + * Description: + * Set system 64 S-tag content + * Input: + * index - index of 64 s-tag configuration + * pSvlanMemCfg - SVLAN member configuration + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_SVLAN_ENTRY_INDEX - Invalid SVLAN index parameter + * Note: + * None + */ +ret_t rtl8367c_setAsicSvlanMemberConfiguration(rtk_uint32 index, rtl8367c_svlan_memconf_t* pSvlanMemCfg) +{ + ret_t retVal; + rtk_uint32 regAddr = 0, regData; + rtk_uint16 *accessPtr; + rtk_uint32 i; + rtk_uint16 smiSvlanMemConf[RTL8367C_SVLAN_MEMCONF_LEN]; + + if(index > RTL8367C_SVIDXMAX) + return RT_ERR_SVLAN_ENTRY_INDEX; + + memset(smiSvlanMemConf, 0x00, sizeof(rtk_uint16) * RTL8367C_SVLAN_MEMCONF_LEN); + _rtl8367c_svlanConfStUser2Smi(pSvlanMemCfg, smiSvlanMemConf); + + accessPtr = smiSvlanMemConf; + + regData = *accessPtr; + for(i = 0; i < 3; i++) + { + retVal = rtl8367c_setAsicReg(RTL8367C_SVLAN_MEMBERCFG_BASE_REG(index) + i, regData); + if(retVal != RT_ERR_OK) + return retVal; + + accessPtr ++; + regData = *accessPtr; + } + + if(index < 63) + regAddr = RTL8367C_REG_SVLAN_MEMBERCFG0_CTRL4+index; + else if(index == 63) + regAddr = RTL8367C_REG_SVLAN_MEMBERCFG63_CTRL4; + + retVal = rtl8367c_setAsicReg(regAddr, regData); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; + +} +/* Function Name: + * rtl8367c_getAsicSvlanMemberConfiguration + * Description: + * Get system 64 S-tag content + * Input: + * index - index of 64 s-tag configuration + * pSvlanMemCfg - SVLAN member configuration + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_SVLAN_ENTRY_INDEX - Invalid SVLAN index parameter + * Note: + * None + */ +ret_t rtl8367c_getAsicSvlanMemberConfiguration(rtk_uint32 index,rtl8367c_svlan_memconf_t* pSvlanMemCfg) +{ + ret_t retVal; + rtk_uint32 regAddr = 0,regData; + rtk_uint16 *accessPtr; + rtk_uint32 i; + rtk_uint16 smiSvlanMemConf[RTL8367C_SVLAN_MEMCONF_LEN]; + + if(index > RTL8367C_SVIDXMAX) + return RT_ERR_SVLAN_ENTRY_INDEX; + + memset(smiSvlanMemConf, 0x00, sizeof(rtk_uint16) * RTL8367C_SVLAN_MEMCONF_LEN); + + accessPtr = smiSvlanMemConf; + + for(i = 0; i < 3; i++) + { + retVal = rtl8367c_getAsicReg(RTL8367C_SVLAN_MEMBERCFG_BASE_REG(index) + i, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + *accessPtr = regData; + + accessPtr ++; + } + + if(index < 63) + regAddr = RTL8367C_REG_SVLAN_MEMBERCFG0_CTRL4+index; + else if(index == 63) + regAddr = RTL8367C_REG_SVLAN_MEMBERCFG63_CTRL4; + + retVal = rtl8367c_getAsicReg(regAddr, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + *accessPtr = regData; + + _rtl8367c_svlanConfStSmi2User(pSvlanMemCfg, smiSvlanMemConf); + + return RT_ERR_OK; +} +/* Function Name: + * rtl8367c_setAsicSvlanC2SConf + * Description: + * Set SVLAN C2S table + * Input: + * index - index of 128 Svlan C2S configuration + * evid - Enhanced VID + * portmask - available c2s port mask + * svidx - index of 64 Svlan member configuration + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_ENTRY_INDEX - Invalid entry index + * Note: + * ASIC will check upstream's VID and assign related SVID to mathed packet + */ +ret_t rtl8367c_setAsicSvlanC2SConf(rtk_uint32 index, rtk_uint32 evid, rtk_uint32 portmask, rtk_uint32 svidx) +{ + ret_t retVal; + + if(index > RTL8367C_C2SIDXMAX) + return RT_ERR_ENTRY_INDEX; + + retVal = rtl8367c_setAsicReg(RTL8367C_SVLAN_C2SCFG_BASE_REG(index), svidx); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8367c_setAsicReg(RTL8367C_SVLAN_C2SCFG_BASE_REG(index) + 1, portmask); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8367c_setAsicReg(RTL8367C_SVLAN_C2SCFG_BASE_REG(index) + 2, evid); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} +/* Function Name: + * rtl8367c_getAsicSvlanC2SConf + * Description: + * Get SVLAN C2S table + * Input: + * index - index of 128 Svlan C2S configuration + * pEvid - Enhanced VID + * pPortmask - available c2s port mask + * pSvidx - index of 64 Svlan member configuration + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_ENTRY_INDEX - Invalid entry index + * Note: + * None + */ +ret_t rtl8367c_getAsicSvlanC2SConf(rtk_uint32 index, rtk_uint32* pEvid, rtk_uint32* pPortmask, rtk_uint32* pSvidx) +{ + ret_t retVal; + + if(index > RTL8367C_C2SIDXMAX) + return RT_ERR_ENTRY_INDEX; + + retVal = rtl8367c_getAsicReg(RTL8367C_SVLAN_C2SCFG_BASE_REG(index), pSvidx); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8367c_getAsicReg(RTL8367C_SVLAN_C2SCFG_BASE_REG(index) + 1, pPortmask); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8367c_getAsicReg(RTL8367C_SVLAN_C2SCFG_BASE_REG(index) + 2, pEvid); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_setAsicSvlanMC2SConf + * Description: + * Set system MC2S content + * Input: + * index - index of 32 SVLAN 32 MC2S configuration + * pSvlanMc2sCfg - SVLAN Multicast to SVLAN member configuration + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_ENTRY_INDEX - Invalid entry index + * Note: + * If upstream packet is L2 multicast or IPv4 multicast packet and DMAC/DIP is matched MC2S + * configuration, ASIC will assign egress SVID to the packet + */ +ret_t rtl8367c_setAsicSvlanMC2SConf(rtk_uint32 index,rtl8367c_svlan_mc2s_t* pSvlanMc2sCfg) +{ + ret_t retVal; + rtk_uint32 regData; + rtk_uint16 *accessPtr; + rtk_uint32 i; + rtk_uint16 smiSvlanMC2S[RTL8367C_SVLAN_MC2S_LEN]; + + if(index > RTL8367C_MC2SIDXMAX) + return RT_ERR_ENTRY_INDEX; + + memset(smiSvlanMC2S, 0x00, sizeof(rtk_uint16) * RTL8367C_SVLAN_MC2S_LEN); + _rtl8367c_svlanMc2sStUser2Smi(pSvlanMc2sCfg, smiSvlanMC2S); + + accessPtr = smiSvlanMC2S; + + for(i = 0; i < 5; i++) + { + regData = *(accessPtr + i); + retVal = rtl8367c_setAsicReg(RTL8367C_SVLAN_MCAST2S_ENTRY_BASE_REG(index) + i, regData); + if(retVal != RT_ERR_OK) + return retVal; + } + + return retVal; +} +/* Function Name: + * rtl8367c_getAsicSvlanMC2SConf + * Description: + * Get system MC2S content + * Input: + * index - index of 32 SVLAN 32 MC2S configuration + * pSvlanMc2sCfg - SVLAN Multicast to SVLAN member configuration + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_ENTRY_INDEX - Invalid entry index + * Note: + * None + */ +ret_t rtl8367c_getAsicSvlanMC2SConf(rtk_uint32 index, rtl8367c_svlan_mc2s_t* pSvlanMc2sCfg) +{ + ret_t retVal; + rtk_uint32 regData; + rtk_uint16 *accessPtr; + rtk_uint32 i; + rtk_uint16 smiSvlanMC2S[RTL8367C_SVLAN_MC2S_LEN]; + + if(index > RTL8367C_MC2SIDXMAX) + return RT_ERR_ENTRY_INDEX; + + memset(smiSvlanMC2S, 0x00, sizeof(rtk_uint16) * RTL8367C_SVLAN_MC2S_LEN); + + accessPtr = smiSvlanMC2S; + + for(i = 0; i < 5; i++) + { + retVal = rtl8367c_getAsicReg(RTL8367C_SVLAN_MCAST2S_ENTRY_BASE_REG(index) + i, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + *accessPtr = regData; + accessPtr ++; + } + + + _rtl8367c_svlanMc2sStSmi2User(pSvlanMc2sCfg, smiSvlanMC2S); + + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_setAsicSvlanSP2CConf + * Description: + * Set system 128 SP2C content + * Input: + * index - index of 128 SVLAN & Port to CVLAN configuration + * pSvlanSp2cCfg - SVLAN & Port to CVLAN configuration + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_ENTRY_INDEX - Invalid entry index + * Note: + * None + */ +ret_t rtl8367c_setAsicSvlanSP2CConf(rtk_uint32 index, rtl8367c_svlan_s2c_t* pSvlanSp2cCfg) +{ + ret_t retVal; + rtk_uint32 regData; + rtk_uint16 *accessPtr; + rtk_uint32 i; + rtk_uint16 smiSvlanSP2C[RTL8367C_SVLAN_SP2C_LEN]; + + if(index > RTL8367C_SP2CMAX) + return RT_ERR_ENTRY_INDEX; + + memset(smiSvlanSP2C, 0x00, sizeof(rtk_uint16) * RTL8367C_SVLAN_SP2C_LEN); + _rtl8367c_svlanSp2cStUser2Smi(pSvlanSp2cCfg,smiSvlanSP2C); + + accessPtr = smiSvlanSP2C; + + for(i = 0; i < 2; i++) + { + regData = *(accessPtr + i); + retVal = rtl8367c_setAsicReg(RTL8367C_SVLAN_S2C_ENTRY_BASE_REG(index) + i, regData); + if(retVal != RT_ERR_OK) + return retVal; + } + + return retVal; +} +/* Function Name: + * rtl8367c_getAsicSvlanSP2CConf + * Description: + * Get system 128 SP2C content + * Input: + * index - index of 128 SVLAN & Port to CVLAN configuration + * pSvlanSp2cCfg - SVLAN & Port to CVLAN configuration + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_ENTRY_INDEX - Invalid entry index + * Note: + * None + */ +ret_t rtl8367c_getAsicSvlanSP2CConf(rtk_uint32 index,rtl8367c_svlan_s2c_t* pSvlanSp2cCfg) +{ + ret_t retVal; + rtk_uint32 regData; + rtk_uint16 *accessPtr; + rtk_uint32 i; + rtk_uint16 smiSvlanSP2C[RTL8367C_SVLAN_SP2C_LEN]; + + if(index > RTL8367C_SP2CMAX) + return RT_ERR_ENTRY_INDEX; + + memset(smiSvlanSP2C, 0x00, sizeof(rtk_uint16) * RTL8367C_SVLAN_SP2C_LEN); + + accessPtr = smiSvlanSP2C; + + for(i = 0; i < 2; i++) + { + retVal = rtl8367c_getAsicReg(RTL8367C_SVLAN_S2C_ENTRY_BASE_REG(index) + i, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + *accessPtr = regData; + + accessPtr ++; + } + + _rtl8367c_svlanSp2cStSmi2User(pSvlanSp2cCfg, smiSvlanSP2C); + + return RT_ERR_OK; +} +/* Function Name: + * rtl8367c_setAsicSvlanDmacCvidSel + * Description: + * Set downstream CVID decision by DMAC + * Input: + * port - Physical port number (0~7) + * enabled - 0:disabled, 1:enabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_setAsicSvlanDmacCvidSel(rtk_uint32 port, rtk_uint32 enabled) +{ + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + if(port < 8) + return rtl8367c_setAsicRegBit(RTL8367C_REG_SVLAN_CFG, RTL8367C_VS_PORT0_DMACVIDSEL_OFFSET + port, enabled); + else + return rtl8367c_setAsicRegBit(RTL8367C_REG_SVLAN_CFG_EXT, RTL8367C_VS_PORT8_DMACVIDSEL_OFFSET + (port-8), enabled); +} +/* Function Name: + * rtl8367c_getAsicSvlanDmacCvidSel + * Description: + * Get downstream CVID decision by DMAC + * Input: + * port - Physical port number (0~7) + * pEnabled - 0:disabled, 1:enabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_getAsicSvlanDmacCvidSel(rtk_uint32 port, rtk_uint32* pEnabled) +{ + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + if(port < 8) + return rtl8367c_getAsicRegBit(RTL8367C_REG_SVLAN_CFG, RTL8367C_VS_PORT0_DMACVIDSEL_OFFSET + port, pEnabled); + else + return rtl8367c_getAsicRegBit(RTL8367C_REG_SVLAN_CFG_EXT, RTL8367C_VS_PORT8_DMACVIDSEL_OFFSET + (port-8), pEnabled); +} +/* Function Name: + * rtl8367c_setAsicSvlanUntagVlan + * Description: + * Set default ingress untag SVLAN + * Input: + * index - index SVLAN member configuration + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_SVLAN_ENTRY_INDEX - Invalid SVLAN index parameter + * Note: + * None + */ +ret_t rtl8367c_setAsicSvlanUntagVlan(rtk_uint32 index) +{ + if(index > RTL8367C_SVIDXMAX) + return RT_ERR_SVLAN_ENTRY_INDEX; + + return rtl8367c_setAsicRegBits(RTL8367C_REG_SVLAN_UNTAG_UNMAT_CFG, RTL8367C_VS_UNTAG_SVIDX_MASK, index); +} +/* Function Name: + * rtl8367c_getAsicSvlanUntagVlan + * Description: + * Get default ingress untag SVLAN + * Input: + * pIndex - index SVLAN member configuration + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicSvlanUntagVlan(rtk_uint32* pIndex) +{ + return rtl8367c_getAsicRegBits(RTL8367C_REG_SVLAN_UNTAG_UNMAT_CFG, RTL8367C_VS_UNTAG_SVIDX_MASK, pIndex); +} + +/* Function Name: + * rtl8367c_setAsicSvlanUnmatchVlan + * Description: + * Set default ingress unmatch SVLAN + * Input: + * index - index SVLAN member configuration + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_SVLAN_ENTRY_INDEX - Invalid SVLAN index parameter + * Note: + * None + */ +ret_t rtl8367c_setAsicSvlanUnmatchVlan(rtk_uint32 index) +{ + if(index > RTL8367C_SVIDXMAX) + return RT_ERR_SVLAN_ENTRY_INDEX; + + return rtl8367c_setAsicRegBits(RTL8367C_REG_SVLAN_UNTAG_UNMAT_CFG, RTL8367C_VS_UNMAT_SVIDX_MASK, index); +} +/* Function Name: + * rtl8367c_getAsicSvlanUnmatchVlan + * Description: + * Get default ingress unmatch SVLAN + * Input: + * pIndex - index SVLAN member configuration + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicSvlanUnmatchVlan(rtk_uint32* pIndex) +{ + return rtl8367c_getAsicRegBits(RTL8367C_REG_SVLAN_UNTAG_UNMAT_CFG, RTL8367C_VS_UNMAT_SVIDX_MASK, pIndex); +} + + +/* Function Name: + * rtl8367c_setAsicSvlanLookupType + * Description: + * Set svlan lookup table selection + * Input: + * type - lookup type + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicSvlanLookupType(rtk_uint32 type) +{ + return rtl8367c_setAsicRegBit(RTL8367C_REG_SVLAN_LOOKUP_TYPE, RTL8367C_SVLAN_LOOKUP_TYPE_OFFSET, type); +} + +/* Function Name: + * rtl8367c_getAsicSvlanLookupType + * Description: + * Get svlan lookup table selection + * Input: + * pType - lookup type + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicSvlanLookupType(rtk_uint32* pType) +{ + return rtl8367c_getAsicRegBit(RTL8367C_REG_SVLAN_LOOKUP_TYPE, RTL8367C_SVLAN_LOOKUP_TYPE_OFFSET, pType); +} + + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_svlan.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_svlan.h new file mode 100644 index 00000000..be0ce170 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_svlan.h @@ -0,0 +1,115 @@ +#ifndef _RTL8367C_ASICDRV_SVLAN_H_ +#define _RTL8367C_ASICDRV_SVLAN_H_ + +#include + +#define RTL8367C_C2SIDXNO 128 +#define RTL8367C_C2SIDXMAX (RTL8367C_C2SIDXNO-1) +#define RTL8367C_MC2SIDXNO 32 +#define RTL8367C_MC2SIDXMAX (RTL8367C_MC2SIDXNO-1) +#define RTL8367C_SP2CIDXNO 128 +#define RTL8367C_SP2CMAX (RTL8367C_SP2CIDXNO-1) + +#define RTL8367C_SVLAN_MEMCONF_LEN 4 +#define RTL8367C_SVLAN_MC2S_LEN 5 +#define RTL8367C_SVLAN_SP2C_LEN 2 + +enum RTL8367C_SPRISEL +{ + SPRISEL_INTERNALPRI = 0, + SPRISEL_CTAGPRI, + SPRISEL_VSPRI, + SPRISEL_PBPRI, + SPRISEL_END +}; + +enum RTL8367C_SUNACCEPT +{ + SUNACCEPT_DROP = 0, + SUNACCEPT_TRAP, + SUNACCEPT_SVLAN, + SUNACCEPT_END +}; + +enum RTL8367C_SVLAN_MC2S_MODE +{ + SVLAN_MC2S_MODE_MAC = 0, + SVLAN_MC2S_MODE_IP, + SVLAN_MC2S_MODE_END +}; + + +typedef struct rtl8367c_svlan_memconf_s{ + + rtk_uint16 vs_member:11; + rtk_uint16 vs_untag:11; + + rtk_uint16 vs_fid_msti:4; + rtk_uint16 vs_priority:3; + rtk_uint16 vs_force_fid:1; + rtk_uint16 reserved:8; + + rtk_uint16 vs_svid:12; + rtk_uint16 vs_efiden:1; + rtk_uint16 vs_efid:3; + + +}rtl8367c_svlan_memconf_t; + + +typedef struct rtl8367c_svlan_mc2s_s{ + + rtk_uint16 valid:1; + rtk_uint16 format:1; + rtk_uint16 svidx:6; + rtk_uint32 sdata; + rtk_uint32 smask; +}rtl8367c_svlan_mc2s_t; + + +typedef struct rtl8367c_svlan_s2c_s{ + + rtk_uint16 valid:1; + rtk_uint16 svidx:6; + rtk_uint16 dstport:4; + rtk_uint32 vid:12; +}rtl8367c_svlan_s2c_t; + +extern ret_t rtl8367c_setAsicSvlanIngressUntag(rtk_uint32 mode); +extern ret_t rtl8367c_getAsicSvlanIngressUntag(rtk_uint32* pMode); +extern ret_t rtl8367c_setAsicSvlanIngressUnmatch(rtk_uint32 mode); +extern ret_t rtl8367c_getAsicSvlanIngressUnmatch(rtk_uint32* pMode); +extern ret_t rtl8367c_setAsicSvlanTrapPriority(rtk_uint32 priority); +extern ret_t rtl8367c_getAsicSvlanTrapPriority(rtk_uint32* pPriority); +extern ret_t rtl8367c_setAsicSvlanDefaultVlan(rtk_uint32 port, rtk_uint32 index); +extern ret_t rtl8367c_getAsicSvlanDefaultVlan(rtk_uint32 port, rtk_uint32* pIndex); + +extern ret_t rtl8367c_setAsicSvlanMemberConfiguration(rtk_uint32 index,rtl8367c_svlan_memconf_t* pSvlanMemCfg); +extern ret_t rtl8367c_getAsicSvlanMemberConfiguration(rtk_uint32 index,rtl8367c_svlan_memconf_t* pSvlanMemCfg); + +extern ret_t rtl8367c_setAsicSvlanPrioritySel(rtk_uint32 priSel); +extern ret_t rtl8367c_getAsicSvlanPrioritySel(rtk_uint32* pPriSel); +extern ret_t rtl8367c_setAsicSvlanTpid(rtk_uint32 protocolType); +extern ret_t rtl8367c_getAsicSvlanTpid(rtk_uint32* pProtocolType); +extern ret_t rtl8367c_setAsicSvlanUplinkPortMask(rtk_uint32 portMask); +extern ret_t rtl8367c_getAsicSvlanUplinkPortMask(rtk_uint32* pPortmask); +extern ret_t rtl8367c_setAsicSvlanEgressUnassign(rtk_uint32 enabled); +extern ret_t rtl8367c_getAsicSvlanEgressUnassign(rtk_uint32* pEnabled); +extern ret_t rtl8367c_setAsicSvlanC2SConf(rtk_uint32 index, rtk_uint32 evid, rtk_uint32 portmask, rtk_uint32 svidx); +extern ret_t rtl8367c_getAsicSvlanC2SConf(rtk_uint32 index, rtk_uint32* pEvid, rtk_uint32* pPortmask, rtk_uint32* pSvidx); +extern ret_t rtl8367c_setAsicSvlanMC2SConf(rtk_uint32 index,rtl8367c_svlan_mc2s_t* pSvlanMc2sCfg); +extern ret_t rtl8367c_getAsicSvlanMC2SConf(rtk_uint32 index,rtl8367c_svlan_mc2s_t* pSvlanMc2sCfg); +extern ret_t rtl8367c_setAsicSvlanSP2CConf(rtk_uint32 index,rtl8367c_svlan_s2c_t* pSvlanSp2cCfg); +extern ret_t rtl8367c_getAsicSvlanSP2CConf(rtk_uint32 index,rtl8367c_svlan_s2c_t* pSvlanSp2cCfg); +extern ret_t rtl8367c_setAsicSvlanDmacCvidSel(rtk_uint32 port, rtk_uint32 enabled); +extern ret_t rtl8367c_getAsicSvlanDmacCvidSel(rtk_uint32 port, rtk_uint32* pEnabled); +extern ret_t rtl8367c_setAsicSvlanUntagVlan(rtk_uint32 index); +extern ret_t rtl8367c_getAsicSvlanUntagVlan(rtk_uint32* pIndex); +extern ret_t rtl8367c_setAsicSvlanUnmatchVlan(rtk_uint32 index); +extern ret_t rtl8367c_getAsicSvlanUnmatchVlan(rtk_uint32* pIndex); +extern ret_t rtl8367c_setAsicSvlanLookupType(rtk_uint32 type); +extern ret_t rtl8367c_getAsicSvlanLookupType(rtk_uint32* pType); + + +#endif /*#ifndef _RTL8367C_ASICDRV_SVLAN_H_*/ + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_trunking.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_trunking.c new file mode 100644 index 00000000..5fc9cf75 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_trunking.c @@ -0,0 +1,358 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTL8367C switch high-level API for RTL8367C + * Feature : Port trunking related functions + * + */ + +#include +/* Function Name: + * rtl8367c_setAsicTrunkingMode + * Description: + * Set port trunking mode + * Input: + * mode - 1:dumb 0:user defined + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicTrunkingMode(rtk_uint32 mode) +{ + return rtl8367c_setAsicRegBit(RTL8367C_REG_PORT_TRUNK_CTRL, RTL8367C_PORT_TRUNK_DUMB_OFFSET, mode); +} +/* Function Name: + * rtl8367c_getAsicTrunkingMode + * Description: + * Get port trunking mode + * Input: + * pMode - 1:dumb 0:user defined + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicTrunkingMode(rtk_uint32* pMode) +{ + return rtl8367c_getAsicRegBit(RTL8367C_REG_PORT_TRUNK_CTRL, RTL8367C_PORT_TRUNK_DUMB_OFFSET, pMode); +} +/* Function Name: + * rtl8367c_setAsicTrunkingFc + * Description: + * Set port trunking flow control + * Input: + * group - Trunk Group ID + * enabled - 0:disable, 1:enable + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicTrunkingFc(rtk_uint32 group, rtk_uint32 enabled) +{ + ret_t retVal; + + if(group > RTL8367C_MAX_TRUNK_GID) + return RT_ERR_LA_TRUNK_ID; + + if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_PORT_TRUNK_DROP_CTRL, RTL8367C_PORT_TRUNK_DROP_CTRL_OFFSET, ENABLED)) != RT_ERR_OK) + return retVal; + + return rtl8367c_setAsicRegBit(RTL8367C_REG_PORT_TRUNK_FLOWCTRL, (RTL8367C_EN_FLOWCTRL_TG0_OFFSET + group), enabled); +} +/* Function Name: + * rtl8367c_getAsicTrunkingFc + * Description: + * Get port trunking flow control + * Input: + * group - Trunk Group ID + * pEnabled - 0:disable, 1:enable + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicTrunkingFc(rtk_uint32 group, rtk_uint32* pEnabled) +{ + if(group > RTL8367C_MAX_TRUNK_GID) + return RT_ERR_LA_TRUNK_ID; + + return rtl8367c_getAsicRegBit(RTL8367C_REG_PORT_TRUNK_FLOWCTRL, (RTL8367C_EN_FLOWCTRL_TG0_OFFSET + group), pEnabled); +} +/* Function Name: + * rtl8367c_setAsicTrunkingGroup + * Description: + * Set trunking group available port mask + * Input: + * group - Trunk Group ID + * portmask - Logic trunking enable port mask, max 4 ports + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicTrunkingGroup(rtk_uint32 group, rtk_uint32 portmask) +{ + if(group > RTL8367C_MAX_TRUNK_GID) + return RT_ERR_LA_TRUNK_ID; + return rtl8367c_setAsicRegBits(RTL8367C_REG_PORT_TRUNK_GROUP_MASK, RTL8367C_PORT_TRUNK_GROUP0_MASK_MASK << (group * 4), portmask); +} +/* Function Name: + * rtl8367c_getAsicTrunkingGroup + * Description: + * Get trunking group available port mask + * Input: + * group - Trunk Group ID + * Output: + * pPortmask - Logic trunking enable port mask, max 4 ports + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicTrunkingGroup(rtk_uint32 group, rtk_uint32* pPortmask) +{ + if(group > RTL8367C_MAX_TRUNK_GID) + return RT_ERR_LA_TRUNK_ID; + + return rtl8367c_getAsicRegBits(RTL8367C_REG_PORT_TRUNK_GROUP_MASK, RTL8367C_PORT_TRUNK_GROUP0_MASK_MASK << (group * 4), pPortmask); +} +/* Function Name: + * rtl8367c_setAsicTrunkingFlood + * Description: + * Set port trunking flood function + * Input: + * enabled - Port trunking flooding function 0:disable 1:enable + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicTrunkingFlood(rtk_uint32 enabled) +{ + return rtl8367c_setAsicRegBit(RTL8367C_REG_PORT_TRUNK_CTRL, RTL8367C_PORT_TRUNK_FLOOD_OFFSET, enabled); +} +/* Function Name: + * rtl8367c_getAsicTrunkingFlood + * Description: + * Get port trunking flood function + * Input: + * pEnabled - Port trunking flooding function 0:disable 1:enable + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicTrunkingFlood(rtk_uint32* pEnabled) +{ + return rtl8367c_getAsicRegBit(RTL8367C_REG_PORT_TRUNK_CTRL, RTL8367C_PORT_TRUNK_FLOOD_OFFSET, pEnabled); +} +/* Function Name: + * rtl8367c_setAsicTrunkingHashSelect + * Description: + * Set port trunking hash select sources + * Input: + * hashsel - hash sources mask + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * 7 bits mask for link aggregation group0 hash parameter selection {DIP, SIP, DMAC, SMAC, SPA} + * 0b0000001: SPA + * 0b0000010: SMAC + * 0b0000100: DMAC + * 0b0001000: SIP + * 0b0010000: DIP + * 0b0100000: TCP/UDP Source Port + * 0b1000000: TCP/UDP Destination Port + */ +ret_t rtl8367c_setAsicTrunkingHashSelect(rtk_uint32 hashsel) +{ + return rtl8367c_setAsicRegBits(RTL8367C_REG_PORT_TRUNK_CTRL, RTL8367C_PORT_TRUNK_HASH_MASK, hashsel); +} +/* Function Name: + * rtl8367c_getAsicTrunkingHashSelect + * Description: + * Get port trunking hash select sources + * Input: + * pHashsel - hash sources mask + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicTrunkingHashSelect(rtk_uint32* pHashsel) +{ + return rtl8367c_getAsicRegBits(RTL8367C_REG_PORT_TRUNK_CTRL, RTL8367C_PORT_TRUNK_HASH_MASK, pHashsel); +} +/* Function Name: + * rtl8367c_getAsicQeueuEmptyStatus + * Description: + * Get current output queue if empty status + * Input: + * portmask - queue empty port mask + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicQeueuEmptyStatus(rtk_uint32* portmask) +{ + return rtl8367c_getAsicReg(RTL8367C_REG_PORT_QEMPTY, portmask); +} +/* Function Name: + * rtl8367c_setAsicTrunkingHashTable + * Description: + * Set port trunking hash value mapping table + * Input: + * hashval - hashing value 0-15 + * portId - trunking port id 0-3 + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * RT_ERR_OUT_OF_RANGE - Invalid hashing value (0-15) + * Note: + * None + */ +ret_t rtl8367c_setAsicTrunkingHashTable(rtk_uint32 hashval, rtk_uint32 portId) +{ + if(hashval > RTL8367C_TRUNKING_HASHVALUE_MAX) + return RT_ERR_OUT_OF_RANGE; + + if(portId >= RTL8367C_TRUNKING_PORTNO) + return RT_ERR_PORT_ID; + + if(hashval >= 8) + return rtl8367c_setAsicRegBits(RTL8367C_REG_PORT_TRUNK_HASH_MAPPING_CTRL1, RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL1_HASH8_MASK<<((hashval-8)*2), portId); + else + return rtl8367c_setAsicRegBits(RTL8367C_REG_PORT_TRUNK_HASH_MAPPING_CTRL0, RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL0_HASH0_MASK<<(hashval*2), portId); +} +/* Function Name: + * rtl8367c_getAsicTrunkingHashTable + * Description: + * Get port trunking hash value mapping table + * Input: + * hashval - hashing value 0-15 + * pPortId - trunking port id 0-3 + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - Invalid hashing value (0-15) + * Note: + * None + */ +ret_t rtl8367c_getAsicTrunkingHashTable(rtk_uint32 hashval, rtk_uint32* pPortId) +{ + if(hashval > RTL8367C_TRUNKING_HASHVALUE_MAX) + return RT_ERR_OUT_OF_RANGE; + + if(hashval >= 8) + return rtl8367c_getAsicRegBits(RTL8367C_REG_PORT_TRUNK_HASH_MAPPING_CTRL1, RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL1_HASH8_MASK<<((hashval-8)*2), pPortId); + else + return rtl8367c_getAsicRegBits(RTL8367C_REG_PORT_TRUNK_HASH_MAPPING_CTRL0, RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL0_HASH0_MASK<<(hashval*2), pPortId); +} + +/* Function Name: + * rtl8367c_setAsicTrunkingHashTable1 + * Description: + * Set port trunking hash value mapping table + * Input: + * hashval - hashing value 0-15 + * portId - trunking port id 0-3 + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * RT_ERR_OUT_OF_RANGE - Invalid hashing value (0-15) + * Note: + * None + */ +ret_t rtl8367c_setAsicTrunkingHashTable1(rtk_uint32 hashval, rtk_uint32 portId) +{ + if(hashval > RTL8367C_TRUNKING_HASHVALUE_MAX) + return RT_ERR_OUT_OF_RANGE; + + if(portId >= RTL8367C_TRUNKING1_PORTN0) + return RT_ERR_PORT_ID; + + if(hashval >= 8) + return rtl8367c_setAsicRegBits(RTL8367C_REG_PORT_TRUNK_HASH_MAPPING_CTRL3, RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL3_HASH8_MASK<<((hashval-8)*2), portId); + else + return rtl8367c_setAsicRegBits(RTL8367C_REG_PORT_TRUNK_HASH_MAPPING_CTRL2, RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL2_HASH0_MASK<<(hashval*2), portId); +} +/* Function Name: + * rtl8367c_getAsicTrunkingHashTable1 + * Description: + * Get port trunking hash value mapping table + * Input: + * hashval - hashing value 0-15 + * pPortId - trunking port id 0-3 + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - Invalid hashing value (0-15) + * Note: + * None + */ +ret_t rtl8367c_getAsicTrunkingHashTable1(rtk_uint32 hashval, rtk_uint32* pPortId) +{ + if(hashval > RTL8367C_TRUNKING_HASHVALUE_MAX) + return RT_ERR_OUT_OF_RANGE; + + if(hashval >= 8) + return rtl8367c_getAsicRegBits(RTL8367C_REG_PORT_TRUNK_HASH_MAPPING_CTRL3, RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL3_HASH8_MASK<<((hashval-8)*2), pPortId); + else + return rtl8367c_getAsicRegBits(RTL8367C_REG_PORT_TRUNK_HASH_MAPPING_CTRL2, RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL2_HASH0_MASK<<(hashval*2), pPortId); +} + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_trunking.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_trunking.h new file mode 100644 index 00000000..b8c35098 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_trunking.h @@ -0,0 +1,30 @@ +#ifndef _RTL8367C_ASICDRV_TRUNKING_H_ +#define _RTL8367C_ASICDRV_TRUNKING_H_ + +#include + +#define RTL8367C_MAX_TRUNK_GID (2) +#define RTL8367C_TRUNKING_PORTNO (4) +#define RTL8367C_TRUNKING1_PORTN0 (2) +#define RTL8367C_TRUNKING_HASHVALUE_MAX (15) + +extern ret_t rtl8367c_setAsicTrunkingGroup(rtk_uint32 group, rtk_uint32 portmask); +extern ret_t rtl8367c_getAsicTrunkingGroup(rtk_uint32 group, rtk_uint32* pPortmask); +extern ret_t rtl8367c_setAsicTrunkingFlood(rtk_uint32 enabled); +extern ret_t rtl8367c_getAsicTrunkingFlood(rtk_uint32* pEnabled); +extern ret_t rtl8367c_setAsicTrunkingHashSelect(rtk_uint32 hashsel); +extern ret_t rtl8367c_getAsicTrunkingHashSelect(rtk_uint32* pHashsel); + +extern ret_t rtl8367c_getAsicQeueuEmptyStatus(rtk_uint32* pPortmask); + +extern ret_t rtl8367c_setAsicTrunkingMode(rtk_uint32 mode); +extern ret_t rtl8367c_getAsicTrunkingMode(rtk_uint32* pMode); +extern ret_t rtl8367c_setAsicTrunkingFc(rtk_uint32 group, rtk_uint32 enabled); +extern ret_t rtl8367c_getAsicTrunkingFc(rtk_uint32 group, rtk_uint32* pEnabled); +extern ret_t rtl8367c_setAsicTrunkingHashTable(rtk_uint32 hashval, rtk_uint32 portId); +extern ret_t rtl8367c_getAsicTrunkingHashTable(rtk_uint32 hashval, rtk_uint32* pPortId); +extern ret_t rtl8367c_setAsicTrunkingHashTable1(rtk_uint32 hashval, rtk_uint32 portId); +extern ret_t rtl8367c_getAsicTrunkingHashTable1(rtk_uint32 hashval, rtk_uint32* pPortId); + +#endif /*_RTL8367C_ASICDRV_TRUNKING_H_*/ + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_unknownMulticast.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_unknownMulticast.c new file mode 100644 index 00000000..3cf9a5e6 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_unknownMulticast.c @@ -0,0 +1,238 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTL8367C switch high-level API for RTL8367C + * Feature : Unkown multicast related functions + * + */ +#include +/* Function Name: + * rtl8367c_setAsicUnknownL2MulticastBehavior + * Description: + * Set behavior of L2 multicast + * Input: + * port - Physical port number (0~7) + * behave - 0: flooding, 1: drop, 2: trap + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * RT_ERR_NOT_ALLOWED - Invalid operation + * Note: + * None + */ +ret_t rtl8367c_setAsicUnknownL2MulticastBehavior(rtk_uint32 port, rtk_uint32 behave) +{ + ret_t retVal; + + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + if(behave >= L2_UNKOWN_MULTICAST_END) + return RT_ERR_NOT_ALLOWED; + if(port < 8) + { + retVal = rtl8367c_setAsicRegBits(RTL8367C_UNKNOWN_L2_MULTICAST_REG(port), RTL8367C_UNKNOWN_L2_MULTICAST_MASK(port), behave); + if(retVal != RT_ERR_OK) + return retVal; + } + else + { + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_UNKNOWN_L2_MULTICAST_CTRL1, 3 << ((port - 8) << 1), behave); + if(retVal != RT_ERR_OK) + return retVal; + } + + return RT_ERR_OK; +} +/* Function Name: + * rtl8367c_getAsicUnknownL2MulticastBehavior + * Description: + * Get behavior of L2 multicast + * Input: + * port - Physical port number (0~7) + * pBehave - 0: flooding, 1: drop, 2: trap + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_getAsicUnknownL2MulticastBehavior(rtk_uint32 port, rtk_uint32 *pBehave) +{ + ret_t retVal; + + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + if(port < 8) + { + retVal = rtl8367c_getAsicRegBits(RTL8367C_UNKNOWN_L2_MULTICAST_REG(port), RTL8367C_UNKNOWN_L2_MULTICAST_MASK(port), pBehave); + if (retVal != RT_ERR_OK) + return retVal; + } + else + { + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_UNKNOWN_L2_MULTICAST_CTRL1, 3 << ((port - 8) << 1), pBehave); + if (retVal != RT_ERR_OK) + return retVal; + } + + return RT_ERR_OK; +} +/* Function Name: + * rtl8367c_setAsicUnknownIPv4MulticastBehavior + * Description: + * Set behavior of IPv4 multicast + * Input: + * port - Physical port number (0~7) + * behave - 0: flooding, 1: drop, 2: trap + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * RT_ERR_NOT_ALLOWED - Invalid operation + * Note: + * None + */ +ret_t rtl8367c_setAsicUnknownIPv4MulticastBehavior(rtk_uint32 port, rtk_uint32 behave) +{ + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + if(behave >= L3_UNKOWN_MULTICAST_END) + return RT_ERR_NOT_ALLOWED; + + return rtl8367c_setAsicRegBits(RTL8367C_UNKNOWN_IPV4_MULTICAST_REG(port), RTL8367C_UNKNOWN_IPV4_MULTICAST_MASK(port), behave); +} +/* Function Name: + * rtl8367c_getAsicUnknownIPv4MulticastBehavior + * Description: + * Get behavior of IPv4 multicast + * Input: + * port - Physical port number (0~7) + * pBehave - 0: flooding, 1: drop, 2: trap + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_getAsicUnknownIPv4MulticastBehavior(rtk_uint32 port, rtk_uint32 *pBehave) +{ + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + return rtl8367c_getAsicRegBits(RTL8367C_UNKNOWN_IPV4_MULTICAST_REG(port), RTL8367C_UNKNOWN_IPV4_MULTICAST_MASK(port), pBehave); +} +/* Function Name: + * rtl8367c_setAsicUnknownIPv6MulticastBehavior + * Description: + * Set behavior of IPv6 multicast + * Input: + * port - Physical port number (0~7) + * behave - 0: flooding, 1: drop, 2: trap + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * RT_ERR_NOT_ALLOWED - Invalid operation + * Note: + * None + */ +ret_t rtl8367c_setAsicUnknownIPv6MulticastBehavior(rtk_uint32 port, rtk_uint32 behave) +{ + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + if(behave >= L3_UNKOWN_MULTICAST_END) + return RT_ERR_NOT_ALLOWED; + + return rtl8367c_setAsicRegBits(RTL8367C_UNKNOWN_IPV6_MULTICAST_REG(port), RTL8367C_UNKNOWN_IPV6_MULTICAST_MASK(port), behave); +} +/* Function Name: + * rtl8367c_getAsicUnknownIPv6MulticastBehavior + * Description: + * Get behavior of IPv6 multicast + * Input: + * port - Physical port number (0~7) + * pBehave - 0: flooding, 1: drop, 2: trap + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_getAsicUnknownIPv6MulticastBehavior(rtk_uint32 port, rtk_uint32 *pBehave) +{ + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + return rtl8367c_getAsicRegBits(RTL8367C_UNKNOWN_IPV6_MULTICAST_REG(port), RTL8367C_UNKNOWN_IPV6_MULTICAST_MASK(port), pBehave); +} +/* Function Name: + * rtl8367c_setAsicUnknownMulticastTrapPriority + * Description: + * Set trap priority of unknown multicast frame + * Input: + * priority - priority (0~7) + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_INT_PRIORITY - Invalid priority + * Note: + * None + */ +ret_t rtl8367c_setAsicUnknownMulticastTrapPriority(rtk_uint32 priority) +{ + if(priority > RTL8367C_PRIMAX) + return RT_ERR_QOS_INT_PRIORITY; + + return rtl8367c_setAsicRegBits(RTL8367C_QOS_TRAP_PRIORITY_CTRL0_REG, RTL8367C_UNKNOWN_MC_PRIORTY_MASK, priority); +} +/* Function Name: + * rtl8367c_getAsicUnknownMulticastTrapPriority + * Description: + * Get trap priority of unknown multicast frame + * Input: + * pPriority - priority (0~7) + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicUnknownMulticastTrapPriority(rtk_uint32 *pPriority) +{ + return rtl8367c_getAsicRegBits(RTL8367C_QOS_TRAP_PRIORITY_CTRL0_REG, RTL8367C_UNKNOWN_MC_PRIORTY_MASK, pPriority); +} diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_unknownMulticast.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_unknownMulticast.h new file mode 100644 index 00000000..e975d1f7 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_unknownMulticast.h @@ -0,0 +1,42 @@ +#ifndef _RTL8367C_ASICDRV_UNKNOWNMULTICAST_H_ +#define _RTL8367C_ASICDRV_UNKNOWNMULTICAST_H_ + +#include + +enum L2_UNKOWN_MULTICAST_BEHAVE +{ + L2_UNKOWN_MULTICAST_FLOODING = 0, + L2_UNKOWN_MULTICAST_DROP, + L2_UNKOWN_MULTICAST_TRAP, + L2_UNKOWN_MULTICAST_DROP_EXCLUDE_RMA, + L2_UNKOWN_MULTICAST_END +}; + +enum L3_UNKOWN_MULTICAST_BEHAVE +{ + L3_UNKOWN_MULTICAST_FLOODING = 0, + L3_UNKOWN_MULTICAST_DROP, + L3_UNKOWN_MULTICAST_TRAP, + L3_UNKOWN_MULTICAST_ROUTER, + L3_UNKOWN_MULTICAST_END +}; + +enum MULTICASTTYPE{ + MULTICAST_TYPE_IPV4 = 0, + MULTICAST_TYPE_IPV6, + MULTICAST_TYPE_L2, + MULTICAST_TYPE_END +}; + +extern ret_t rtl8367c_setAsicUnknownL2MulticastBehavior(rtk_uint32 port, rtk_uint32 behave); +extern ret_t rtl8367c_getAsicUnknownL2MulticastBehavior(rtk_uint32 port, rtk_uint32 *pBehave); +extern ret_t rtl8367c_setAsicUnknownIPv4MulticastBehavior(rtk_uint32 port, rtk_uint32 behave); +extern ret_t rtl8367c_getAsicUnknownIPv4MulticastBehavior(rtk_uint32 port, rtk_uint32 *pBehave); +extern ret_t rtl8367c_setAsicUnknownIPv6MulticastBehavior(rtk_uint32 port, rtk_uint32 behave); +extern ret_t rtl8367c_getAsicUnknownIPv6MulticastBehavior(rtk_uint32 port, rtk_uint32 *pBehave); +extern ret_t rtl8367c_setAsicUnknownMulticastTrapPriority(rtk_uint32 priority); +extern ret_t rtl8367c_getAsicUnknownMulticastTrapPriority(rtk_uint32 *pPriority); + +#endif /*_RTL8367C_ASICDRV_UNKNOWNMULTICAST_H_*/ + + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_vlan.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_vlan.c new file mode 100644 index 00000000..40fbd9fa --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_vlan.c @@ -0,0 +1,1529 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTL8367C switch high-level API for RTL8367C + * Feature : VLAN related functions + * + */ +#include + +#include + +#if defined(CONFIG_RTL8367C_ASICDRV_TEST) +rtl8367c_user_vlan4kentry Rtl8370sVirtualVlanTable[RTL8367C_VIDMAX + 1]; +#endif + +static void _rtl8367c_VlanMCStUser2Smi(rtl8367c_vlanconfiguser *pVlanCg, rtk_uint16 *pSmiVlanCfg) +{ + pSmiVlanCfg[0] |= pVlanCg->mbr & 0x07FF; + + pSmiVlanCfg[1] |= pVlanCg->fid_msti & 0x000F; + + pSmiVlanCfg[2] |= pVlanCg->vbpen & 0x0001; + pSmiVlanCfg[2] |= (pVlanCg->vbpri & 0x0007) << 1; + pSmiVlanCfg[2] |= (pVlanCg->envlanpol & 0x0001) << 4; + pSmiVlanCfg[2] |= (pVlanCg->meteridx & 0x003F) << 5; + + pSmiVlanCfg[3] |= pVlanCg->evid & 0x1FFF; +} + +static void _rtl8367c_VlanMCStSmi2User(rtk_uint16 *pSmiVlanCfg, rtl8367c_vlanconfiguser *pVlanCg) +{ + pVlanCg->mbr = pSmiVlanCfg[0] & 0x07FF; + pVlanCg->fid_msti = pSmiVlanCfg[1] & 0x000F; + pVlanCg->meteridx = (pSmiVlanCfg[2] >> 5) & 0x003F; + pVlanCg->envlanpol = (pSmiVlanCfg[2] >> 4) & 0x0001; + pVlanCg->vbpri = (pSmiVlanCfg[2] >> 1) & 0x0007; + pVlanCg->vbpen = pSmiVlanCfg[2] & 0x0001; + pVlanCg->evid = pSmiVlanCfg[3] & 0x1FFF; +} + +static void _rtl8367c_Vlan4kStUser2Smi(rtl8367c_user_vlan4kentry *pUserVlan4kEntry, rtk_uint16 *pSmiVlan4kEntry) +{ + pSmiVlan4kEntry[0] |= (pUserVlan4kEntry->mbr & 0x00FF); + pSmiVlan4kEntry[0] |= (pUserVlan4kEntry->untag & 0x00FF) << 8; + + pSmiVlan4kEntry[1] |= (pUserVlan4kEntry->fid_msti & 0x000F); + pSmiVlan4kEntry[1] |= (pUserVlan4kEntry->vbpen & 0x0001) << 4; + pSmiVlan4kEntry[1] |= (pUserVlan4kEntry->vbpri & 0x0007) << 5; + pSmiVlan4kEntry[1] |= (pUserVlan4kEntry->envlanpol & 0x0001) << 8; + pSmiVlan4kEntry[1] |= (pUserVlan4kEntry->meteridx & 0x001F) << 9; + pSmiVlan4kEntry[1] |= (pUserVlan4kEntry->ivl_svl & 0x0001) << 14; + + pSmiVlan4kEntry[2] |= ((pUserVlan4kEntry->mbr & 0x0700) >> 8); + pSmiVlan4kEntry[2] |= ((pUserVlan4kEntry->untag & 0x0700) >> 8) << 3; + pSmiVlan4kEntry[2] |= ((pUserVlan4kEntry->meteridx & 0x0020) >> 5) << 6; +} + + +static void _rtl8367c_Vlan4kStSmi2User(rtk_uint16 *pSmiVlan4kEntry, rtl8367c_user_vlan4kentry *pUserVlan4kEntry) +{ + pUserVlan4kEntry->mbr = (pSmiVlan4kEntry[0] & 0x00FF) | ((pSmiVlan4kEntry[2] & 0x0007) << 8); + pUserVlan4kEntry->untag = ((pSmiVlan4kEntry[0] & 0xFF00) >> 8) | (((pSmiVlan4kEntry[2] & 0x0038) >> 3) << 8); + pUserVlan4kEntry->fid_msti = pSmiVlan4kEntry[1] & 0x000F; + pUserVlan4kEntry->vbpen = (pSmiVlan4kEntry[1] & 0x0010) >> 4; + pUserVlan4kEntry->vbpri = (pSmiVlan4kEntry[1] & 0x00E0) >> 5; + pUserVlan4kEntry->envlanpol = (pSmiVlan4kEntry[1] & 0x0100) >> 8; + pUserVlan4kEntry->meteridx = ((pSmiVlan4kEntry[1] & 0x3E00) >> 9) | (((pSmiVlan4kEntry[2] & 0x0040) >> 6) << 5); + pUserVlan4kEntry->ivl_svl = (pSmiVlan4kEntry[1] & 0x4000) >> 14; +} + +/* Function Name: + * rtl8367c_setAsicVlanMemberConfig + * Description: + * Set 32 VLAN member configurations + * Input: + * index - VLAN member configuration index (0~31) + * pVlanCg - VLAN member configuration + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter + * RT_ERR_L2_FID - Invalid FID + * RT_ERR_PORT_MASK - Invalid portmask + * RT_ERR_FILTER_METER_ID - Invalid meter + * RT_ERR_QOS_INT_PRIORITY - Invalid priority + * RT_ERR_VLAN_ENTRY_NOT_FOUND - Invalid VLAN member configuration index + * Note: + * None + */ +ret_t rtl8367c_setAsicVlanMemberConfig(rtk_uint32 index, rtl8367c_vlanconfiguser *pVlanCg) +{ + ret_t retVal; + rtk_uint32 regAddr; + rtk_uint32 regData; + rtk_uint16 *tableAddr; + rtk_uint32 page_idx; + rtk_uint16 smi_vlancfg[RTL8367C_VLAN_MBRCFG_LEN]; + + /* Error Checking */ + if(index > RTL8367C_CVIDXMAX) + return RT_ERR_VLAN_ENTRY_NOT_FOUND; + + if(pVlanCg->evid > RTL8367C_EVIDMAX) + return RT_ERR_INPUT; + + + if(pVlanCg->mbr > RTL8367C_PORTMASK) + return RT_ERR_PORT_MASK; + + if(pVlanCg->fid_msti > RTL8367C_FIDMAX) + return RT_ERR_L2_FID; + + if(pVlanCg->meteridx > RTL8367C_METERMAX) + return RT_ERR_FILTER_METER_ID; + + if(pVlanCg->vbpri > RTL8367C_PRIMAX) + return RT_ERR_QOS_INT_PRIORITY; + + memset(smi_vlancfg, 0x00, sizeof(rtk_uint16) * RTL8367C_VLAN_MBRCFG_LEN); + _rtl8367c_VlanMCStUser2Smi(pVlanCg, smi_vlancfg); + tableAddr = smi_vlancfg; + + for(page_idx = 0; page_idx < 4; page_idx++) /* 4 pages per VLAN Member Config */ + { + regAddr = RTL8367C_VLAN_MEMBER_CONFIGURATION_BASE + (index * 4) + page_idx; + regData = *tableAddr; + + retVal = rtl8367c_setAsicReg(regAddr, regData); + if(retVal != RT_ERR_OK) + return retVal; + + tableAddr++; + } + + return RT_ERR_OK; +} +/* Function Name: + * rtl8367c_getAsicVlanMemberConfig + * Description: + * Get 32 VLAN member configurations + * Input: + * index - VLAN member configuration index (0~31) + * pVlanCg - VLAN member configuration + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter + * RT_ERR_VLAN_ENTRY_NOT_FOUND - Invalid VLAN member configuration index + * Note: + * None + */ +ret_t rtl8367c_getAsicVlanMemberConfig(rtk_uint32 index, rtl8367c_vlanconfiguser *pVlanCg) +{ + ret_t retVal; + rtk_uint32 page_idx; + rtk_uint32 regAddr; + rtk_uint32 regData; + rtk_uint16 *tableAddr; + rtk_uint16 smi_vlancfg[RTL8367C_VLAN_MBRCFG_LEN]; + + if(index > RTL8367C_CVIDXMAX) + return RT_ERR_VLAN_ENTRY_NOT_FOUND; + + memset(smi_vlancfg, 0x00, sizeof(rtk_uint16) * RTL8367C_VLAN_MBRCFG_LEN); + tableAddr = smi_vlancfg; + + for(page_idx = 0; page_idx < 4; page_idx++) /* 4 pages per VLAN Member Config */ + { + regAddr = RTL8367C_VLAN_MEMBER_CONFIGURATION_BASE + (index * 4) + page_idx; + + retVal = rtl8367c_getAsicReg(regAddr, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + *tableAddr = (rtk_uint16)regData; + tableAddr++; + } + + _rtl8367c_VlanMCStSmi2User(smi_vlancfg, pVlanCg); + return RT_ERR_OK; +} +/* Function Name: + * rtl8367c_setAsicVlan4kEntry + * Description: + * Set VID mapped entry to 4K VLAN table + * Input: + * pVlan4kEntry - 4K VLAN configuration + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter + * RT_ERR_L2_FID - Invalid FID + * RT_ERR_VLAN_VID - Invalid VID parameter (0~4095) + * RT_ERR_PORT_MASK - Invalid portmask + * RT_ERR_FILTER_METER_ID - Invalid meter + * RT_ERR_QOS_INT_PRIORITY - Invalid priority + * Note: + * None + */ +ret_t rtl8367c_setAsicVlan4kEntry(rtl8367c_user_vlan4kentry *pVlan4kEntry ) +{ + rtk_uint16 vlan_4k_entry[RTL8367C_VLAN_4KTABLE_LEN]; + rtk_uint32 page_idx; + rtk_uint16 *tableAddr; + ret_t retVal; + rtk_uint32 regData; + + if(pVlan4kEntry->vid > RTL8367C_VIDMAX) + return RT_ERR_VLAN_VID; + + if(pVlan4kEntry->mbr > RTL8367C_PORTMASK) + return RT_ERR_PORT_MASK; + + if(pVlan4kEntry->untag > RTL8367C_PORTMASK) + return RT_ERR_PORT_MASK; + + if(pVlan4kEntry->fid_msti > RTL8367C_FIDMAX) + return RT_ERR_L2_FID; + + if(pVlan4kEntry->meteridx > RTL8367C_METERMAX) + return RT_ERR_FILTER_METER_ID; + + if(pVlan4kEntry->vbpri > RTL8367C_PRIMAX) + return RT_ERR_QOS_INT_PRIORITY; + + memset(vlan_4k_entry, 0x00, sizeof(rtk_uint16) * RTL8367C_VLAN_4KTABLE_LEN); + _rtl8367c_Vlan4kStUser2Smi(pVlan4kEntry, vlan_4k_entry); + + /* Prepare Data */ + tableAddr = vlan_4k_entry; + for(page_idx = 0; page_idx < RTL8367C_VLAN_4KTABLE_LEN; page_idx++) + { + regData = *tableAddr; + retVal = rtl8367c_setAsicReg(RTL8367C_TABLE_ACCESS_WRDATA_BASE + page_idx, regData); + if(retVal != RT_ERR_OK) + return retVal; + + tableAddr++; + } + + /* Write Address (VLAN_ID) */ + regData = pVlan4kEntry->vid; + retVal = rtl8367c_setAsicReg(RTL8367C_TABLE_ACCESS_ADDR_REG, regData); + if(retVal != RT_ERR_OK) + return retVal; + + /* Write Command */ + retVal = rtl8367c_setAsicRegBits(RTL8367C_TABLE_ACCESS_CTRL_REG, RTL8367C_TABLE_TYPE_MASK | RTL8367C_COMMAND_TYPE_MASK,RTL8367C_TABLE_ACCESS_REG_DATA(TB_OP_WRITE,TB_TARGET_CVLAN)); + if(retVal != RT_ERR_OK) + return retVal; + +#if defined(CONFIG_RTL8367C_ASICDRV_TEST) + memcpy(&Rtl8370sVirtualVlanTable[pVlan4kEntry->vid], pVlan4kEntry, sizeof(rtl8367c_user_vlan4kentry)); +#endif + + return RT_ERR_OK; +} +/* Function Name: + * rtl8367c_getAsicVlan4kEntry + * Description: + * Get VID mapped entry to 4K VLAN table + * Input: + * pVlan4kEntry - 4K VLAN configuration + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_VLAN_VID - Invalid VID parameter (0~4095) + * RT_ERR_BUSYWAIT_TIMEOUT - LUT is busy at retrieving + * Note: + * None + */ +ret_t rtl8367c_getAsicVlan4kEntry(rtl8367c_user_vlan4kentry *pVlan4kEntry ) +{ + rtk_uint16 vlan_4k_entry[RTL8367C_VLAN_4KTABLE_LEN]; + rtk_uint32 page_idx; + rtk_uint16 *tableAddr; + ret_t retVal; + rtk_uint32 regData; + rtk_uint32 busyCounter; + + if(pVlan4kEntry->vid > RTL8367C_VIDMAX) + return RT_ERR_VLAN_VID; + + /* Polling status */ + busyCounter = RTL8367C_VLAN_BUSY_CHECK_NO; + while(busyCounter) + { + retVal = rtl8367c_getAsicRegBit(RTL8367C_TABLE_ACCESS_STATUS_REG, RTL8367C_TABLE_LUT_ADDR_BUSY_FLAG_OFFSET,®Data); + if(retVal != RT_ERR_OK) + return retVal; + + if(regData == 0) + break; + + busyCounter --; + if(busyCounter == 0) + return RT_ERR_BUSYWAIT_TIMEOUT; + } + + /* Write Address (VLAN_ID) */ + regData = pVlan4kEntry->vid; + retVal = rtl8367c_setAsicReg(RTL8367C_TABLE_ACCESS_ADDR_REG, regData); + if(retVal != RT_ERR_OK) + return retVal; + + /* Read Command */ + retVal = rtl8367c_setAsicRegBits(RTL8367C_TABLE_ACCESS_CTRL_REG, RTL8367C_TABLE_TYPE_MASK | RTL8367C_COMMAND_TYPE_MASK, RTL8367C_TABLE_ACCESS_REG_DATA(TB_OP_READ,TB_TARGET_CVLAN)); + if(retVal != RT_ERR_OK) + return retVal; + + /* Polling status */ + busyCounter = RTL8367C_VLAN_BUSY_CHECK_NO; + while(busyCounter) + { + retVal = rtl8367c_getAsicRegBit(RTL8367C_TABLE_ACCESS_STATUS_REG, RTL8367C_TABLE_LUT_ADDR_BUSY_FLAG_OFFSET,®Data); + if(retVal != RT_ERR_OK) + return retVal; + + if(regData == 0) + break; + + busyCounter --; + if(busyCounter == 0) + return RT_ERR_BUSYWAIT_TIMEOUT; + } + + /* Read VLAN data from register */ + tableAddr = vlan_4k_entry; + for(page_idx = 0; page_idx < RTL8367C_VLAN_4KTABLE_LEN; page_idx++) + { + retVal = rtl8367c_getAsicReg(RTL8367C_TABLE_ACCESS_RDDATA_BASE + page_idx, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + *tableAddr = regData; + tableAddr++; + } + + _rtl8367c_Vlan4kStSmi2User(vlan_4k_entry, pVlan4kEntry); + +#if defined(CONFIG_RTL8367C_ASICDRV_TEST) + memcpy(pVlan4kEntry, &Rtl8370sVirtualVlanTable[pVlan4kEntry->vid], sizeof(rtl8367c_user_vlan4kentry)); +#endif + + return RT_ERR_OK; +} +/* Function Name: + * rtl8367c_setAsicVlanAccpetFrameType + * Description: + * Set per-port acceptable frame type + * Input: + * port - Physical port number (0~10) + * frameType - The acceptable frame type + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * RT_ERR_VLAN_ACCEPT_FRAME_TYPE - Invalid frame type + * Note: + * None + */ +ret_t rtl8367c_setAsicVlanAccpetFrameType(rtk_uint32 port, rtl8367c_accframetype frameType) +{ + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + if(frameType >= FRAME_TYPE_MAX_BOUND) + return RT_ERR_VLAN_ACCEPT_FRAME_TYPE; + + return rtl8367c_setAsicRegBits(RTL8367C_VLAN_ACCEPT_FRAME_TYPE_REG(port), RTL8367C_VLAN_ACCEPT_FRAME_TYPE_MASK(port), frameType); +} +/* Function Name: + * rtl8367c_getAsicVlanAccpetFrameType + * Description: + * Get per-port acceptable frame type + * Input: + * port - Physical port number (0~10) + * pFrameType - The acceptable frame type + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * RT_ERR_VLAN_ACCEPT_FRAME_TYPE - Invalid frame type + * Note: + * None + */ +ret_t rtl8367c_getAsicVlanAccpetFrameType(rtk_uint32 port, rtl8367c_accframetype *pFrameType) +{ + rtk_uint32 regData; + ret_t retVal; + + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + if((retVal = rtl8367c_getAsicRegBits(RTL8367C_VLAN_ACCEPT_FRAME_TYPE_REG(port), RTL8367C_VLAN_ACCEPT_FRAME_TYPE_MASK(port), ®Data)) != RT_ERR_OK) + return retVal; + + *pFrameType = (rtl8367c_accframetype)regData; + return RT_ERR_OK; +} +/* Function Name: + * rtl8367c_setAsicVlanIngressFilter + * Description: + * Set VLAN Ingress Filter + * Input: + * port - Physical port number (0~10) + * enabled - Enable or disable Ingress filter + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_setAsicVlanIngressFilter(rtk_uint32 port, rtk_uint32 enabled) +{ + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + return rtl8367c_setAsicRegBit(RTL8367C_VLAN_INGRESS_REG, port, enabled); +} +/* Function Name: + * rtl8367c_getAsicVlanIngressFilter + * Description: + * Get VLAN Ingress Filter + * Input: + * port - Physical port number (0~10) + * pEnable - Enable or disable Ingress filter + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_getAsicVlanIngressFilter(rtk_uint32 port, rtk_uint32 *pEnable) +{ + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + return rtl8367c_getAsicRegBit(RTL8367C_VLAN_INGRESS_REG, port, pEnable); +} +/* Function Name: + * rtl8367c_setAsicVlanEgressTagMode + * Description: + * Set CVLAN egress tag mode + * Input: + * port - Physical port number (0~10) + * tagMode - The egress tag mode. Including Original mode, Keep tag mode and Priority tag mode + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_setAsicVlanEgressTagMode(rtk_uint32 port, rtl8367c_egtagmode tagMode) +{ + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + if(tagMode >= EG_TAG_MODE_END) + return RT_ERR_INPUT; + + return rtl8367c_setAsicRegBits(RTL8367C_PORT_MISC_CFG_REG(port), RTL8367C_VLAN_EGRESS_MDOE_MASK, tagMode); +} +/* Function Name: + * rtl8367c_getAsicVlanEgressTagMode + * Description: + * Get CVLAN egress tag mode + * Input: + * port - Physical port number (0~10) + * pTagMode - The egress tag mode. Including Original mode, Keep tag mode and Priority tag mode + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_getAsicVlanEgressTagMode(rtk_uint32 port, rtl8367c_egtagmode *pTagMode) +{ + rtk_uint32 regData; + ret_t retVal; + + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + if((retVal = rtl8367c_getAsicRegBits(RTL8367C_PORT_MISC_CFG_REG(port), RTL8367C_VLAN_EGRESS_MDOE_MASK, ®Data)) != RT_ERR_OK) + return retVal; + + *pTagMode = (rtl8367c_egtagmode)regData; + return RT_ERR_OK; +} +/* Function Name: + * rtl8367c_setAsicVlanPortBasedVID + * Description: + * Set port based VID which is indexed to 32 VLAN member configurations + * Input: + * port - Physical port number (0~10) + * index - Index to VLAN member configuration + * pri - 1Q Port based VLAN priority + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * RT_ERR_QOS_INT_PRIORITY - Invalid priority + * RT_ERR_VLAN_ENTRY_NOT_FOUND - Invalid VLAN member configuration index + * Note: + * None + */ +ret_t rtl8367c_setAsicVlanPortBasedVID(rtk_uint32 port, rtk_uint32 index, rtk_uint32 pri) +{ + rtk_uint32 regAddr, bit_mask; + ret_t retVal; + + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + if(index > RTL8367C_CVIDXMAX) + return RT_ERR_VLAN_ENTRY_NOT_FOUND; + + if(pri > RTL8367C_PRIMAX) + return RT_ERR_QOS_INT_PRIORITY; + + regAddr = RTL8367C_VLAN_PVID_CTRL_REG(port); + bit_mask = RTL8367C_PORT_VIDX_MASK(port); + retVal = rtl8367c_setAsicRegBits(regAddr, bit_mask, index); + if(retVal != RT_ERR_OK) + return retVal; + + regAddr = RTL8367C_VLAN_PORTBASED_PRIORITY_REG(port); + bit_mask = RTL8367C_VLAN_PORTBASED_PRIORITY_MASK(port); + retVal = rtl8367c_setAsicRegBits(regAddr, bit_mask, pri); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} +/* Function Name: + * rtl8367c_getAsicVlanPortBasedVID + * Description: + * Get port based VID which is indexed to 32 VLAN member configurations + * Input: + * port - Physical port number (0~10) + * pIndex - Index to VLAN member configuration + * pPri - 1Q Port based VLAN priority + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_getAsicVlanPortBasedVID(rtk_uint32 port, rtk_uint32 *pIndex, rtk_uint32 *pPri) +{ + rtk_uint32 regAddr,bit_mask; + ret_t retVal; + + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + regAddr = RTL8367C_VLAN_PVID_CTRL_REG(port); + bit_mask = RTL8367C_PORT_VIDX_MASK(port); + retVal = rtl8367c_getAsicRegBits(regAddr, bit_mask, pIndex); + if(retVal != RT_ERR_OK) + return retVal; + + regAddr = RTL8367C_VLAN_PORTBASED_PRIORITY_REG(port); + bit_mask = RTL8367C_VLAN_PORTBASED_PRIORITY_MASK(port); + retVal = rtl8367c_getAsicRegBits(regAddr, bit_mask, pPri); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} +/* Function Name: + * rtl8367c_setAsicVlanProtocolBasedGroupData + * Description: + * Set protocol and port based group database + * Input: + * index - Index to VLAN member configuration + * pPbCfg - Protocol and port based group database entry + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter + * RT_ERR_VLAN_PROTO_AND_PORT - Invalid protocol base group database index + * Note: + * None + */ +ret_t rtl8367c_setAsicVlanProtocolBasedGroupData(rtk_uint32 index, rtl8367c_protocolgdatacfg *pPbCfg) +{ + rtk_uint32 frameType; + rtk_uint32 etherType; + ret_t retVal; + + /* Error Checking */ + if(index > RTL8367C_PROTOVLAN_GIDX_MAX) + return RT_ERR_VLAN_PROTO_AND_PORT; + + if(pPbCfg->frameType >= PPVLAN_FRAME_TYPE_END ) + return RT_ERR_INPUT; + + frameType = pPbCfg->frameType; + etherType = pPbCfg->etherType; + + /* Frame type */ + retVal = rtl8367c_setAsicRegBits(RTL8367C_VLAN_PPB_FRAMETYPE_REG(index), RTL8367C_VLAN_PPB_FRAMETYPE_MASK, frameType); + if(retVal != RT_ERR_OK) + return retVal; + + /* Ether type */ + retVal = rtl8367c_setAsicReg(RTL8367C_VLAN_PPB_ETHERTYPR_REG(index), etherType); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} +/* Function Name: + * rtl8367c_getAsicVlanProtocolBasedGroupData + * Description: + * Get protocol and port based group database + * Input: + * index - Index to VLAN member configuration + * pPbCfg - Protocol and port based group database entry + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter + * RT_ERR_VLAN_PROTO_AND_PORT - Invalid protocol base group database index + * Note: + * None + */ +ret_t rtl8367c_getAsicVlanProtocolBasedGroupData(rtk_uint32 index, rtl8367c_protocolgdatacfg *pPbCfg) +{ + rtk_uint32 frameType; + rtk_uint32 etherType; + ret_t retVal; + + /* Error Checking */ + if(index > RTL8367C_PROTOVLAN_GIDX_MAX) + return RT_ERR_VLAN_PROTO_AND_PORT; + + /* Read Frame type */ + retVal = rtl8367c_getAsicRegBits(RTL8367C_VLAN_PPB_FRAMETYPE_REG(index), RTL8367C_VLAN_PPB_FRAMETYPE_MASK, &frameType); + if(retVal != RT_ERR_OK) + return retVal; + + /* Read Ether type */ + retVal = rtl8367c_getAsicReg(RTL8367C_VLAN_PPB_ETHERTYPR_REG(index), ðerType); + if(retVal != RT_ERR_OK) + return retVal; + + + pPbCfg->frameType = frameType; + pPbCfg->etherType = etherType; + return RT_ERR_OK; +} +/* Function Name: + * rtl8367c_setAsicVlanPortAndProtocolBased + * Description: + * Set protocol and port based VLAN configuration + * Input: + * port - Physical port number (0~10) + * index - Index of protocol and port based database index + * pPpbCfg - Protocol and port based VLAN configuration + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter + * RT_ERR_PORT_ID - Invalid port number + * RT_ERR_QOS_INT_PRIORITY - Invalid priority + * RT_ERR_VLAN_PROTO_AND_PORT - Invalid protocol base group database index + * RT_ERR_VLAN_ENTRY_NOT_FOUND - Invalid VLAN member configuration index + * Note: + * None + */ +ret_t rtl8367c_setAsicVlanPortAndProtocolBased(rtk_uint32 port, rtk_uint32 index, rtl8367c_protocolvlancfg *pPpbCfg) +{ + rtk_uint32 reg_addr, bit_mask, bit_value; + ret_t retVal; + + /* Error Checking */ + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + if(index > RTL8367C_PROTOVLAN_GIDX_MAX) + return RT_ERR_VLAN_PROTO_AND_PORT; + + if( (pPpbCfg->valid != FALSE) && (pPpbCfg->valid != TRUE) ) + return RT_ERR_INPUT; + + if(pPpbCfg->vlan_idx > RTL8367C_CVIDXMAX) + return RT_ERR_VLAN_ENTRY_NOT_FOUND; + + if(pPpbCfg->priority > RTL8367C_PRIMAX) + return RT_ERR_QOS_INT_PRIORITY; + + /* Valid bit */ + reg_addr = RTL8367C_VLAN_PPB_VALID_REG(index); + bit_mask = 0x0001 << port; + bit_value = ((TRUE == pPpbCfg->valid) ? 0x1 : 0x0); + retVal = rtl8367c_setAsicRegBits(reg_addr, bit_mask, bit_value); + if(retVal != RT_ERR_OK) + return retVal; + + /* Calculate the actual register address for CVLAN index*/ + if(port < 8) + { + reg_addr = RTL8367C_VLAN_PPB_CTRL_REG(index, port); + bit_mask = RTL8367C_VLAN_PPB_CTRL_MASK(port); + } + else if(port == 8) + { + reg_addr = RTL8367C_REG_VLAN_PPB0_CTRL4; + bit_mask = RTL8367C_VLAN_PPB0_CTRL4_PORT8_INDEX_MASK; + } + else if(port == 9) + { + reg_addr = RTL8367C_REG_VLAN_PPB0_CTRL4; + bit_mask = RTL8367C_VLAN_PPB0_CTRL4_PORT9_INDEX_MASK; + } + else if(port == 10) + { + reg_addr = RTL8367C_REG_VLAN_PPB0_CTRL4; + bit_mask = RTL8367C_VLAN_PPB0_CTRL4_PORT10_INDEX_MASK; + } + + bit_value = pPpbCfg->vlan_idx; + retVal = rtl8367c_setAsicRegBits(reg_addr, bit_mask, bit_value); + if(retVal != RT_ERR_OK) + return retVal; + + /* write priority */ + reg_addr = RTL8367C_VLAN_PPB_PRIORITY_ITEM_REG(port, index); + bit_mask = RTL8367C_VLAN_PPB_PRIORITY_ITEM_MASK(port); + bit_value = pPpbCfg->priority; + retVal = rtl8367c_setAsicRegBits(reg_addr, bit_mask, bit_value); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} +/* Function Name: + * rtl8367c_getAsicVlanPortAndProtocolBased + * Description: + * Get protocol and port based VLAN configuration + * Input: + * port - Physical port number (0~7) + * index - Index of protocol and port based database index + * pPpbCfg - Protocol and port based VLAN configuration + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter + * RT_ERR_PORT_ID - Invalid port number + * RT_ERR_VLAN_PROTO_AND_PORT - Invalid protocol base group database index + * Note: + * None + */ +ret_t rtl8367c_getAsicVlanPortAndProtocolBased(rtk_uint32 port, rtk_uint32 index, rtl8367c_protocolvlancfg *pPpbCfg) +{ + rtk_uint32 reg_addr, bit_mask, bit_value; + ret_t retVal; + + /* Error Checking */ + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + if(index > RTL8367C_PROTOVLAN_GIDX_MAX) + return RT_ERR_VLAN_PROTO_AND_PORT; + + if(pPpbCfg == NULL) + return RT_ERR_INPUT; + + /* Valid bit */ + reg_addr = RTL8367C_VLAN_PPB_VALID_REG(index); + bit_mask = 0x0001 << port; + retVal = rtl8367c_getAsicRegBits(reg_addr, bit_mask, &bit_value); + if(retVal != RT_ERR_OK) + return retVal; + + pPpbCfg->valid = bit_value; + + /* CVLAN index */ + if(port < 8) + { + reg_addr = RTL8367C_VLAN_PPB_CTRL_REG(index, port); + bit_mask = RTL8367C_VLAN_PPB_CTRL_MASK(port); + } + else if(port == 8) + { + reg_addr = RTL8367C_REG_VLAN_PPB0_CTRL4; + bit_mask = RTL8367C_VLAN_PPB0_CTRL4_PORT8_INDEX_MASK; + } + else if(port == 9) + { + reg_addr = RTL8367C_REG_VLAN_PPB0_CTRL4; + bit_mask = RTL8367C_VLAN_PPB0_CTRL4_PORT9_INDEX_MASK; + } + else if(port == 10) + { + reg_addr = RTL8367C_REG_VLAN_PPB0_CTRL4; + bit_mask = RTL8367C_VLAN_PPB0_CTRL4_PORT10_INDEX_MASK; + } + + retVal = rtl8367c_getAsicRegBits(reg_addr, bit_mask, &bit_value); + if(retVal != RT_ERR_OK) + return retVal; + + pPpbCfg->vlan_idx = bit_value; + + + /* priority */ + reg_addr = RTL8367C_VLAN_PPB_PRIORITY_ITEM_REG(port,index); + bit_mask = RTL8367C_VLAN_PPB_PRIORITY_ITEM_MASK(port); + retVal = rtl8367c_getAsicRegBits(reg_addr, bit_mask, &bit_value); + if(retVal != RT_ERR_OK) + return retVal; + + pPpbCfg->priority = bit_value; + return RT_ERR_OK; +} +/* Function Name: + * rtl8367c_setAsicVlanFilter + * Description: + * Set enable CVLAN filtering function + * Input: + * enabled - 1: enabled, 0: disabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicVlanFilter(rtk_uint32 enabled) +{ + return rtl8367c_setAsicRegBit(RTL8367C_REG_VLAN_CTRL, RTL8367C_VLAN_CTRL_OFFSET, enabled); +} +/* Function Name: + * rtl8367c_getAsicVlanFilter + * Description: + * Get enable CVLAN filtering function + * Input: + * pEnabled - 1: enabled, 0: disabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicVlanFilter(rtk_uint32* pEnabled) +{ + return rtl8367c_getAsicRegBit(RTL8367C_REG_VLAN_CTRL, RTL8367C_VLAN_CTRL_OFFSET, pEnabled); +} +/* Function Name: + * rtl8367c_setAsicVlanUntagDscpPriorityEn + * Description: + * Set enable Dscp to untag 1Q priority + * Input: + * enabled - 1: enabled, 0: disabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_setAsicVlanUntagDscpPriorityEn(rtk_uint32 enabled) +{ + return rtl8367c_setAsicRegBit(RTL8367C_REG_UNTAG_DSCP_PRI_CFG, RTL8367C_UNTAG_DSCP_PRI_CFG_OFFSET, enabled); +} +/* Function Name: + * rtl8367c_getAsicVlanUntagDscpPriorityEn + * Description: + * Get enable Dscp to untag 1Q priority + * Input: + * enabled - 1: enabled, 0: disabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_getAsicVlanUntagDscpPriorityEn(rtk_uint32* enabled) +{ + return rtl8367c_getAsicRegBit(RTL8367C_REG_UNTAG_DSCP_PRI_CFG, RTL8367C_UNTAG_DSCP_PRI_CFG_OFFSET, enabled); +} +/* Function Name: + * rtl8367c_setAsicPortBasedFid + * Description: + * Set port based FID + * Input: + * port - Physical port number (0~10) + * fid - Port based fid + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_FID - Invalid FID + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_setAsicPortBasedFid(rtk_uint32 port, rtk_uint32 fid) +{ + rtk_uint32 reg_addr; + + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + if(fid > RTL8367C_FIDMAX) + return RT_ERR_L2_FID; + + if(port < 8) + return rtl8367c_setAsicReg(RTL8367C_PORT_PBFID_REG(port),fid); + else { + reg_addr = RTL8367C_REG_PORT8_PBFID + port-8; + return rtl8367c_setAsicReg(reg_addr, fid); + } + +} +/* Function Name: + * rtl8367c_getAsicPortBasedFid + * Description: + * Get port based FID + * Input: + * port - Physical port number (0~7) + * pFid - Port based fid + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_getAsicPortBasedFid(rtk_uint32 port, rtk_uint32* pFid) +{ + rtk_uint32 reg_addr; + + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + if(port < 8) + return rtl8367c_getAsicReg(RTL8367C_PORT_PBFID_REG(port), pFid); + else{ + reg_addr = RTL8367C_REG_PORT8_PBFID + port-8; + return rtl8367c_getAsicReg(reg_addr, pFid); + } +} +/* Function Name: + * rtl8367c_setAsicPortBasedFidEn + * Description: + * Set port based FID selection enable + * Input: + * port - Physical port number (0~10) + * enabled - 1: enabled, 0: disabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_setAsicPortBasedFidEn(rtk_uint32 port, rtk_uint32 enabled) +{ + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + return rtl8367c_setAsicRegBit(RTL8367C_REG_PORT_PBFIDEN,port, enabled); +} +/* Function Name: + * rtl8367c_getAsicPortBasedFidEn + * Description: + * Get port based FID selection enable + * Input: + * port - Physical port number (0~10) + * pEnabled - 1: enabled, 0: disabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_getAsicPortBasedFidEn(rtk_uint32 port, rtk_uint32* pEnabled) +{ + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + return rtl8367c_getAsicRegBit(RTL8367C_REG_PORT_PBFIDEN,port, pEnabled); +} +/* Function Name: + * rtl8367c_setAsicSpanningTreeStatus + * Description: + * Set spanning tree state per each port + * Input: + * port - Physical port number (0~10) + * msti - Multiple spanning tree instance + * state - Spanning tree state for msti + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_MSTI - Invalid msti parameter + * RT_ERR_PORT_ID - Invalid port number + * RT_ERR_MSTP_STATE - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_setAsicSpanningTreeStatus(rtk_uint32 port, rtk_uint32 msti, rtk_uint32 state) +{ + rtk_uint32 reg_addr,bits_msk; + + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + if(msti > RTL8367C_MSTIMAX) + return RT_ERR_MSTI; + + if(state > STPST_FORWARDING) + return RT_ERR_MSTP_STATE; + + if(port < 8) + return rtl8367c_setAsicRegBits(RTL8367C_VLAN_MSTI_REG(msti,port), RTL8367C_VLAN_MSTI_MASK(port),state); + else + { + reg_addr = RTL8367C_VLAN_MSTI_REG(msti,port); + switch(port) + { + case 8: + bits_msk = RTL8367C_VLAN_MSTI0_CTRL1_PORT8_STATE_MASK; + break; + case 9: + bits_msk = RTL8367C_VLAN_MSTI0_CTRL1_PORT9_STATE_MASK; + break; + case 10: + bits_msk = RTL8367C_VLAN_MSTI0_CTRL1_PORT10_STATE_MASK; + break; + default: + return RT_ERR_PORT_ID; + } + + return rtl8367c_setAsicRegBits(reg_addr, bits_msk,state); + } +} +/* Function Name: + * rtl8367c_getAsicSpanningTreeStatus + * Description: + * Set spanning tree state per each port + * Input: + * port - Physical port number (0~10) + * msti - Multiple spanning tree instance + * pState - Spanning tree state for msti + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_MSTI - Invalid msti parameter + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_getAsicSpanningTreeStatus(rtk_uint32 port, rtk_uint32 msti, rtk_uint32* pState) +{ + rtk_uint32 reg_addr,bits_msk; + + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + if(msti > RTL8367C_MSTIMAX) + return RT_ERR_MSTI; + + if(port < 8) + return rtl8367c_getAsicRegBits(RTL8367C_VLAN_MSTI_REG(msti,port), RTL8367C_VLAN_MSTI_MASK(port), pState); + else + { + reg_addr = RTL8367C_VLAN_MSTI_REG(msti,port); + switch(port) + { + case 8: + bits_msk = RTL8367C_VLAN_MSTI0_CTRL1_PORT8_STATE_MASK; + break; + case 9: + bits_msk = RTL8367C_VLAN_MSTI0_CTRL1_PORT9_STATE_MASK; + break; + case 10: + bits_msk = RTL8367C_VLAN_MSTI0_CTRL1_PORT10_STATE_MASK; + break; + default: + return RT_ERR_PORT_ID; + } + + return rtl8367c_getAsicRegBits(reg_addr, bits_msk, pState); + } + +} + +/* Function Name: + * rtl8367c_setAsicVlanTransparent + * Description: + * Set VLAN transparent + * Input: + * port - Physical port number (0~10) + * portmask - portmask(0~0xFF) + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Invalid portmask + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_setAsicVlanTransparent(rtk_uint32 port, rtk_uint32 portmask) +{ + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + if(portmask > RTL8367C_PORTMASK) + return RT_ERR_PORT_MASK; + + return rtl8367c_setAsicRegBits(RTL8367C_REG_VLAN_EGRESS_TRANS_CTRL0 + port, RTL8367C_VLAN_EGRESS_TRANS_CTRL0_MASK, portmask); +} + +/* Function Name: + * rtl8367c_getAsicVlanTransparent + * Description: + * Get VLAN transparent + * Input: + * port - Physical port number (0~10) + * Output: + * pPortmask - Ingress port mask + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Invalid portmask + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_getAsicVlanTransparent(rtk_uint32 port, rtk_uint32 *pPortmask) +{ + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + return rtl8367c_getAsicRegBits(RTL8367C_REG_VLAN_EGRESS_TRANS_CTRL0 + port, RTL8367C_VLAN_EGRESS_TRANS_CTRL0_MASK, pPortmask); +} + +/* Function Name: + * rtl8367c_setAsicVlanEgressKeep + * Description: + * Set per egress port VLAN keep mode + * Input: + * port - Physical port number (0~10) + * portmask - portmask(0~0xFF) + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Invalid portmask + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_setAsicVlanEgressKeep(rtk_uint32 port, rtk_uint32 portmask) +{ + rtk_uint32 regAddr, bit_mask; + ret_t retVal; + + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + if(portmask > RTL8367C_PORTMASK) + return RT_ERR_PORT_MASK; + + if(port < 8){ + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_VLAN_EGRESS_KEEP_CTRL0 + (port>>1),RTL8367C_PORT0_VLAN_KEEP_MASK_MASK<<((port&1)*8),portmask & 0xff); + if(retVal != RT_ERR_OK) + return retVal; + regAddr = RTL8367C_REG_VLAN_EGRESS_KEEP_CTRL0_EXT + (port>>1); + bit_mask = RTL8367C_PORT0_VLAN_KEEP_MASK_EXT_MASK; + bit_mask <<= (port&1)*3; + retVal = rtl8367c_setAsicRegBits(regAddr, bit_mask, (portmask>>8)&0x7); + if(retVal != RT_ERR_OK) + return retVal; + } + else{ + switch(port){ + case 8: + regAddr = RTL8367C_REG_VLAN_EGRESS_KEEP_CTRL4; + bit_mask = RTL8367C_PORT8_VLAN_KEEP_MASK_MASK; + retVal = rtl8367c_setAsicRegBits(regAddr, bit_mask, portmask & 0xff); + if(retVal != RT_ERR_OK) + return retVal; + regAddr = RTL8367C_REG_VLAN_EGRESS_KEEP_CTRL4_EXT; + bit_mask = RTL8367C_PORT8_VLAN_KEEP_MASK_EXT_MASK; + retVal = rtl8367c_setAsicRegBits(regAddr, bit_mask, (portmask>>8)&0x7); + if(retVal != RT_ERR_OK) + return retVal; + break; + + case 9: + regAddr = RTL8367C_REG_VLAN_EGRESS_KEEP_CTRL4; + bit_mask = RTL8367C_PORT9_VLAN_KEEP_MASK_MASK; + retVal = rtl8367c_setAsicRegBits(regAddr, bit_mask, portmask & 0xff); + if(retVal != RT_ERR_OK) + return retVal; + regAddr = RTL8367C_REG_VLAN_EGRESS_KEEP_CTRL4_EXT; + bit_mask = RTL8367C_PORT9_VLAN_KEEP_MASK_EXT_MASK; + retVal = rtl8367c_setAsicRegBits(regAddr, bit_mask, (portmask>>8)&0x7); + if(retVal != RT_ERR_OK) + return retVal; + break; + + case 10: + regAddr = RTL8367C_REG_VLAN_EGRESS_KEEP_CTRL5; + bit_mask = RTL8367C_VLAN_EGRESS_KEEP_CTRL5_MASK; + retVal = rtl8367c_setAsicRegBits(regAddr, bit_mask, portmask & 0xff); + if(retVal != RT_ERR_OK) + return retVal; + regAddr = RTL8367C_REG_VLAN_EGRESS_KEEP_CTRL5_EXT; + bit_mask = RTL8367C_VLAN_EGRESS_KEEP_CTRL5_EXT_MASK; + retVal = rtl8367c_setAsicRegBits(regAddr, bit_mask, (portmask>>8)&0x7); + if(retVal != RT_ERR_OK) + return retVal; + break; + } + } + + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_getAsicVlanEgressKeep + * Description: + * Get per egress port VLAN keep mode + * Input: + * port - Physical port number (0~7) + * pPortmask - portmask(0~0xFF) + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtl8367c_getAsicVlanEgressKeep(rtk_uint32 port, rtk_uint32* pPortmask) +{ + rtk_uint32 regAddr, bit_mask, regval_l, regval_h; + ret_t retVal; + + if(port > RTL8367C_PORTIDMAX) + return RT_ERR_PORT_ID; + + if(port < 8){ + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_VLAN_EGRESS_KEEP_CTRL0 + (port>>1),RTL8367C_PORT0_VLAN_KEEP_MASK_MASK<<((port&1)*8),®val_l); + if(retVal != RT_ERR_OK) + return retVal; + regAddr = RTL8367C_REG_VLAN_EGRESS_KEEP_CTRL0_EXT + (port>>1); + bit_mask = RTL8367C_PORT0_VLAN_KEEP_MASK_EXT_MASK; + bit_mask <<= (port&1)*3; + retVal = rtl8367c_getAsicRegBits(regAddr, bit_mask, ®val_h); + if(retVal != RT_ERR_OK) + return retVal; + *pPortmask = (regval_h << 8) | regval_l; + } + else{ + switch(port){ + case 8: + regAddr = RTL8367C_REG_VLAN_EGRESS_KEEP_CTRL4; + bit_mask = RTL8367C_PORT8_VLAN_KEEP_MASK_MASK; + retVal = rtl8367c_getAsicRegBits(regAddr, bit_mask, ®val_l); + if(retVal != RT_ERR_OK) + return retVal; + regAddr = RTL8367C_REG_VLAN_EGRESS_KEEP_CTRL4_EXT; + bit_mask = RTL8367C_PORT8_VLAN_KEEP_MASK_EXT_MASK; + retVal = rtl8367c_getAsicRegBits(regAddr, bit_mask, ®val_h); + if(retVal != RT_ERR_OK) + return retVal; + + *pPortmask = (regval_h << 8) | regval_l; + break; + + case 9: + regAddr = RTL8367C_REG_VLAN_EGRESS_KEEP_CTRL4; + bit_mask = RTL8367C_PORT9_VLAN_KEEP_MASK_MASK; + retVal = rtl8367c_getAsicRegBits(regAddr, bit_mask, ®val_l); + if(retVal != RT_ERR_OK) + return retVal; + regAddr = RTL8367C_REG_VLAN_EGRESS_KEEP_CTRL4_EXT; + bit_mask = RTL8367C_PORT9_VLAN_KEEP_MASK_EXT_MASK; + retVal = rtl8367c_getAsicRegBits(regAddr, bit_mask, ®val_h); + if(retVal != RT_ERR_OK) + return retVal; + + *pPortmask = (regval_h << 8) | regval_l; + break; + + case 10: + regAddr = RTL8367C_REG_VLAN_EGRESS_KEEP_CTRL5; + bit_mask = RTL8367C_VLAN_EGRESS_KEEP_CTRL5_MASK; + retVal = rtl8367c_getAsicRegBits(regAddr, bit_mask, ®val_l); + if(retVal != RT_ERR_OK) + return retVal; + regAddr = RTL8367C_REG_VLAN_EGRESS_KEEP_CTRL5_EXT; + bit_mask = RTL8367C_VLAN_EGRESS_KEEP_CTRL5_EXT_MASK; + retVal = rtl8367c_getAsicRegBits(regAddr, bit_mask, ®val_h); + if(retVal != RT_ERR_OK) + return retVal; + + *pPortmask = (regval_h << 8) | regval_l; + break; + } + } + + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_setReservedVidAction + * Description: + * Set reserved VID action + * Input: + * vid0Action - VID 0 action + * vid4095Action - VID 4095 action + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error input + * Note: + * None + */ +ret_t rtl8367c_setReservedVidAction(rtk_uint32 vid0Action, rtk_uint32 vid4095Action) +{ + ret_t retVal; + + if(vid0Action >= RES_VID_ACT_END) + return RT_ERR_INPUT; + + if(vid4095Action >= RES_VID_ACT_END) + return RT_ERR_INPUT; + + if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_VLAN_EXT_CTRL, RTL8367C_VLAN_VID0_TYPE_OFFSET, vid0Action)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_VLAN_EXT_CTRL, RTL8367C_VLAN_VID4095_TYPE_OFFSET, vid4095Action)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_getReservedVidAction + * Description: + * Get reserved VID action + * Input: + * pVid0Action - VID 0 action + * pVid4095Action - VID 4095 action + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * None + */ +ret_t rtl8367c_getReservedVidAction(rtk_uint32 *pVid0Action, rtk_uint32 *pVid4095Action) +{ + ret_t retVal; + + if(pVid0Action == NULL) + return RT_ERR_NULL_POINTER; + + if(pVid4095Action == NULL) + return RT_ERR_NULL_POINTER; + + if((retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_VLAN_EXT_CTRL, RTL8367C_VLAN_VID0_TYPE_OFFSET, pVid0Action)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_VLAN_EXT_CTRL, RTL8367C_VLAN_VID4095_TYPE_OFFSET, pVid4095Action)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; + +} + +/* Function Name: + * rtl8367c_setRealKeepRemarkEn + * Description: + * Set Real Keep Remark + * Input: + * enabled - 0: 1P remarking is forbidden at real keep packet, 1: 1P remarking is enabled at real keep packet + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error input + * Note: + * None + */ +ret_t rtl8367c_setRealKeepRemarkEn(rtk_uint32 enabled) +{ + ret_t retVal; + + if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_VLAN_EXT_CTRL, RTL8367C_VLAN_1P_REMARK_BYPASS_REALKEEP_OFFSET, enabled)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_getRealKeepRemarkEn + * Description: + * Get Real Keep Remark + * Input: + * None + * Output: + * pEnabled - 0: 1P remarking is forbidden at real keep packet, 1: 1P remarking is enabled at real keep packet + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error input + * Note: + * None + */ +ret_t rtl8367c_getRealKeepRemarkEn(rtk_uint32 *pEnabled) +{ + ret_t retVal; + + if((retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_VLAN_EXT_CTRL, RTL8367C_VLAN_1P_REMARK_BYPASS_REALKEEP_OFFSET, pEnabled)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtl8367c_resetVlan + * Description: + * Reset VLAN table + * Input: + * None. + * Output: + * None. + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t rtl8367c_resetVlan(void) +{ + ret_t retVal; + + if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_VLAN_EXT_CTRL2, RTL8367C_VLAN_EXT_CTRL2_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_vlan.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_vlan.h new file mode 100644 index 00000000..cfcbd037 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_asicdrv_vlan.h @@ -0,0 +1,139 @@ +#ifndef _RTL8367C_ASICDRV_VLAN_H_ +#define _RTL8367C_ASICDRV_VLAN_H_ + +/****************************************************************/ +/* Header File inclusion */ +/****************************************************************/ +#include + +/****************************************************************/ +/* Constant Definition */ +/****************************************************************/ +#define RTL8367C_PROTOVLAN_GIDX_MAX 3 +#define RTL8367C_PROTOVLAN_GROUPNO 4 + +#define RTL8367C_VLAN_BUSY_CHECK_NO (10) + +#define RTL8367C_VLAN_MBRCFG_LEN (4) +#define RTL8367C_VLAN_4KTABLE_LEN (3) + +/****************************************************************/ +/* Type Definition */ +/****************************************************************/ +typedef struct VLANCONFIGUSER +{ + rtk_uint16 evid; + rtk_uint16 mbr; + rtk_uint16 fid_msti; + rtk_uint16 envlanpol; + rtk_uint16 meteridx; + rtk_uint16 vbpen; + rtk_uint16 vbpri; +}rtl8367c_vlanconfiguser; + +typedef struct USER_VLANTABLE{ + + rtk_uint16 vid; + rtk_uint16 mbr; + rtk_uint16 untag; + rtk_uint16 fid_msti; + rtk_uint16 envlanpol; + rtk_uint16 meteridx; + rtk_uint16 vbpen; + rtk_uint16 vbpri; + rtk_uint16 ivl_svl; + +}rtl8367c_user_vlan4kentry; + +typedef enum +{ + FRAME_TYPE_BOTH = 0, + FRAME_TYPE_TAGGED_ONLY, + FRAME_TYPE_UNTAGGED_ONLY, + FRAME_TYPE_MAX_BOUND +} rtl8367c_accframetype; + +typedef enum +{ + EG_TAG_MODE_ORI = 0, + EG_TAG_MODE_KEEP, + EG_TAG_MODE_PRI_TAG, + EG_TAG_MODE_REAL_KEEP, + EG_TAG_MODE_END +} rtl8367c_egtagmode; + +typedef enum +{ + PPVLAN_FRAME_TYPE_ETHERNET = 0, + PPVLAN_FRAME_TYPE_LLC, + PPVLAN_FRAME_TYPE_RFC1042, + PPVLAN_FRAME_TYPE_END +} rtl8367c_provlan_frametype; + +enum RTL8367C_STPST +{ + STPST_DISABLED = 0, + STPST_BLOCKING, + STPST_LEARNING, + STPST_FORWARDING +}; + +enum RTL8367C_RESVIDACT +{ + RES_VID_ACT_UNTAG = 0, + RES_VID_ACT_TAG, + RES_VID_ACT_END +}; + +typedef struct +{ + rtl8367c_provlan_frametype frameType; + rtk_uint32 etherType; +} rtl8367c_protocolgdatacfg; + +typedef struct +{ + rtk_uint32 valid; + rtk_uint32 vlan_idx; + rtk_uint32 priority; +} rtl8367c_protocolvlancfg; + +extern ret_t rtl8367c_setAsicVlanMemberConfig(rtk_uint32 index, rtl8367c_vlanconfiguser *pVlanCg); +extern ret_t rtl8367c_getAsicVlanMemberConfig(rtk_uint32 index, rtl8367c_vlanconfiguser *pVlanCg); +extern ret_t rtl8367c_setAsicVlan4kEntry(rtl8367c_user_vlan4kentry *pVlan4kEntry ); +extern ret_t rtl8367c_getAsicVlan4kEntry(rtl8367c_user_vlan4kentry *pVlan4kEntry ); +extern ret_t rtl8367c_setAsicVlanAccpetFrameType(rtk_uint32 port, rtl8367c_accframetype frameType); +extern ret_t rtl8367c_getAsicVlanAccpetFrameType(rtk_uint32 port, rtl8367c_accframetype *pFrameType); +extern ret_t rtl8367c_setAsicVlanIngressFilter(rtk_uint32 port, rtk_uint32 enabled); +extern ret_t rtl8367c_getAsicVlanIngressFilter(rtk_uint32 port, rtk_uint32 *pEnable); +extern ret_t rtl8367c_setAsicVlanEgressTagMode(rtk_uint32 port, rtl8367c_egtagmode tagMode); +extern ret_t rtl8367c_getAsicVlanEgressTagMode(rtk_uint32 port, rtl8367c_egtagmode *pTagMode); +extern ret_t rtl8367c_setAsicVlanPortBasedVID(rtk_uint32 port, rtk_uint32 index, rtk_uint32 pri); +extern ret_t rtl8367c_getAsicVlanPortBasedVID(rtk_uint32 port, rtk_uint32 *pIndex, rtk_uint32 *pPri); +extern ret_t rtl8367c_setAsicVlanProtocolBasedGroupData(rtk_uint32 index, rtl8367c_protocolgdatacfg *pPbCfg); +extern ret_t rtl8367c_getAsicVlanProtocolBasedGroupData(rtk_uint32 index, rtl8367c_protocolgdatacfg *pPbCfg); +extern ret_t rtl8367c_setAsicVlanPortAndProtocolBased(rtk_uint32 port, rtk_uint32 index, rtl8367c_protocolvlancfg *pPpbCfg); +extern ret_t rtl8367c_getAsicVlanPortAndProtocolBased(rtk_uint32 port, rtk_uint32 index, rtl8367c_protocolvlancfg *pPpbCfg); +extern ret_t rtl8367c_setAsicVlanFilter(rtk_uint32 enabled); +extern ret_t rtl8367c_getAsicVlanFilter(rtk_uint32* pEnabled); + +extern ret_t rtl8367c_setAsicPortBasedFid(rtk_uint32 port, rtk_uint32 fid); +extern ret_t rtl8367c_getAsicPortBasedFid(rtk_uint32 port, rtk_uint32* pFid); +extern ret_t rtl8367c_setAsicPortBasedFidEn(rtk_uint32 port, rtk_uint32 enabled); +extern ret_t rtl8367c_getAsicPortBasedFidEn(rtk_uint32 port, rtk_uint32* pEnabled); +extern ret_t rtl8367c_setAsicSpanningTreeStatus(rtk_uint32 port, rtk_uint32 msti, rtk_uint32 state); +extern ret_t rtl8367c_getAsicSpanningTreeStatus(rtk_uint32 port, rtk_uint32 msti, rtk_uint32* pState); +extern ret_t rtl8367c_setAsicVlanUntagDscpPriorityEn(rtk_uint32 enabled); +extern ret_t rtl8367c_getAsicVlanUntagDscpPriorityEn(rtk_uint32* enabled); +extern ret_t rtl8367c_setAsicVlanTransparent(rtk_uint32 port, rtk_uint32 portmask); +extern ret_t rtl8367c_getAsicVlanTransparent(rtk_uint32 port, rtk_uint32 *pPortmask); +extern ret_t rtl8367c_setAsicVlanEgressKeep(rtk_uint32 port, rtk_uint32 portmask); +extern ret_t rtl8367c_getAsicVlanEgressKeep(rtk_uint32 port, rtk_uint32* pPortmask); +extern ret_t rtl8367c_setReservedVidAction(rtk_uint32 vid0Action, rtk_uint32 vid4095Action); +extern ret_t rtl8367c_getReservedVidAction(rtk_uint32 *pVid0Action, rtk_uint32 *pVid4095Action); +extern ret_t rtl8367c_setRealKeepRemarkEn(rtk_uint32 enabled); +extern ret_t rtl8367c_getRealKeepRemarkEn(rtk_uint32 *pEnabled); +extern ret_t rtl8367c_resetVlan(void); + +#endif /*#ifndef _RTL8367C_ASICDRV_VLAN_H_*/ + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_base.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_base.h new file mode 100644 index 00000000..2496230e --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_base.h @@ -0,0 +1,579 @@ +#ifndef _RTL8367C_BASE_H_ +#define _RTL8367C_BASE_H_ + +#include + +/* (16'h0000) port_reg */ + +#define RTL8367C_PORT_SPECIAL_CONGEST_MODE_TIMER_BASE RTL8367C_REG_PKTGEN_PORT0_TIMER +#define RTL8367C_PORT_SPECIAL_CONGEST_MODE_TIMER_REG(port) (RTL8367C_PORT_SPECIAL_CONGEST_MODE_TIMER_BASE + (port << 5)) + +#define RTL8367C_PORT_MISC_CFG_BASE RTL8367C_REG_PORT0_MISC_CFG +#define RTL8367C_PORT_MISC_CFG_REG(port) (RTL8367C_PORT_MISC_CFG_BASE + (port << 5)) +#define RTL8367C_1QREMARK_ENABLE_OFFSET RTL8367C_PORT0_MISC_CFG_DOT1Q_REMARK_ENABLE_OFFSET +#define RTL8367C_1QREMARK_ENABLE_MASK RTL8367C_PORT0_MISC_CFG_DOT1Q_REMARK_ENABLE_MASK + +#define RTL8367C_INGRESSBW_PORT_IFG_MASK RTL8367C_PORT0_MISC_CFG_INGRESSBW_IFG_MASK +#define RTL8367C_VLAN_EGRESS_MDOE_MASK RTL8367C_PORT0_MISC_CFG_VLAN_EGRESS_MODE_MASK +#define RTL8367C_SPECIALCONGEST_SUSTAIN_TIMER_MASK RTL8367C_PORT0_MISC_CFG_CONGESTION_SUSTAIN_TIME_MASK + +#define RTL8367C_INGRESSBW_PORT_RATE_LSB_BASE RTL8367C_REG_INGRESSBW_PORT0_RATE_CTRL0 +#define RTL8367C_INGRESSBW_PORT_RATE_LSB_REG(port) (RTL8367C_INGRESSBW_PORT_RATE_LSB_BASE + (port << 5)) + +#define RTL8367C_PORT_SMALL_IPG_REG(port) (RTL8367C_REG_PORT0_MISC_CFG + (port*0x20)) + +#define RTL8367C_PORT_EEE_CFG_BASE RTL8367C_REG_PORT0_EEECFG +#define RTL8367C_PORT_EEE_CFG_REG(port) (RTL8367C_REG_PORT0_EEECFG + (port << 5)) +#define RTL8367C_PORT_EEE_100M_OFFSET RTL8367C_PORT0_EEECFG_EEE_100M_OFFSET +#define RTL8367C_PORT_EEE_100M_MASK RTL8367C_PORT0_EEECFG_EEE_100M_MASK +#define RTL8367C_PORT_EEE_GIGA_OFFSET RTL8367C_PORT0_EEECFG_EEE_GIGA_500M_OFFSET +#define RTL8367C_PORT_EEE_GIGA_MASK RTL8367C_PORT0_EEECFG_EEE_GIGA_500M_MASK + + +/* (16'h0200) outq_reg */ + +#define RTL8367C_FLOWCTRL_QUEUE_DROP_ON_BASE RTL8367C_REG_FLOWCTRL_QUEUE0_DROP_ON +#define RTL8367C_FLOWCTRL_QUEUE_DROP_ON_REG(queue) (RTL8367C_FLOWCTRL_QUEUE_DROP_ON_BASE + queue) +#define RTL8367C_FLOWCTRL_QUEUE_DROP_ON_MASK RTL8367C_FLOWCTRL_QUEUE0_DROP_ON_MASK + +#define RTL8367C_FLOWCTRL_PORT_DROP_ON_BASE RTL8367C_REG_FLOWCTRL_PORT0_DROP_ON +#define RTL8367C_FLOWCTRL_PORT_DROP_ON_REG(PORT) (RTL8367C_FLOWCTRL_PORT_DROP_ON_BASE + PORT) +#define RTL8367C_FLOWCTRL_PORT_DROP_ON_MASK RTL8367C_FLOWCTRL_PORT0_DROP_ON_MASK + +#define RTL8367C_FLOWCTRL_PORT_GAP_REG RTL8367C_REG_FLOWCTRL_PORT_GAP +#define RTL8367C_FLOWCTRL_QUEUE_GAP_REG RTL8367C_REG_FLOWCTRL_QUEUE_GAP +#define RTL8367C_FLOWCTRL_PORT_QEMPTY_REG RTL8367C_REG_PORT_QEMPTY + +/* (16'h0300) sch_reg */ + +#define RTL8367C_SCHEDULE_WFQ_BURST_SIZE_REG RTL8367C_REG_SCHEDULE_WFQ_BURST_SIZE + +#define RTL8367C_SCHEDULE_QUEUE_TYPE_BASE RTL8367C_REG_SCHEDULE_QUEUE_TYPE_CTRL0 +#define RTL8367C_SCHEDULE_QUEUE_TYPE_REG(port) (RTL8367C_SCHEDULE_QUEUE_TYPE_BASE + (port >> 1)) +#define RTL8367C_SCHEDULE_QUEUE_TYPE_OFFSET(port, queue) (((port & 0x1) << 3) + queue) +#define RTL8367C_SCHEDULE_QUEUE_TYPE_MASK(port, queue) RTL8367C_SCHEDULE_QUEUE_TYPE_OFFSET(port, queue) + +#define RTL8367C_SCHEDULE_PORT_QUEUE_WFQ_WEIGHT_BASE RTL8367C_REG_SCHEDULE_PORT0_QUEUE0_WFQ_WEIGHT +#define RTL8367C_SCHEDULE_PORT_QUEUE_WFQ_WEIGHT_REG(port, queue) (RTL8367C_SCHEDULE_PORT_QUEUE_WFQ_WEIGHT_BASE + (port << 3) + queue) + +#define RTL8367C_SCHEDULE_APR_CTRL_REG RTL8367C_REG_SCHEDULE_APR_CTRL0 +#define RTL8367C_SCHEDULE_APR_CTRL_OFFSET(port) (port) +#define RTL8367C_SCHEDULE_APR_CTRL_MASK(port) (1 << RTL8367C_SCHEDULE_APR_CTRL_OFFSET(port)) + +#define RTL8367C_SCHEDULE_PORT_APR_METER_BASE RTL8367C_REG_SCHEDULE_PORT0_APR_METER_CTRL0 +#define RTL8367C_SCHEDULE_PORT_APR_METER_REG(port, queue) (RTL8367C_SCHEDULE_PORT_APR_METER_BASE + (port << 2) + (queue / 5)) +#define RTL8367C_SCHEDULE_PORT_APR_METER_OFFSET(queue) (3 * (queue % 5)) +#define RTL8367C_SCHEDULE_PORT_APR_METER_MASK(queue) (RTL8367C_SCHEDULE_PORT0_APR_METER_CTRL0_QUEUE0_APR_METER_MASK << RTL8367C_SCHEDULE_PORT_APR_METER_OFFSET(queue)) + +#define RTL8367C_PORT_EGRESSBW_LSB_BASE RTL8367C_REG_PORT0_EGRESSBW_CTRL0 +#define RTL8367C_PORT_EGRESSBW_LSB_REG(port) (RTL8367C_PORT_EGRESSBW_LSB_BASE + (port << 1)) + +#define RTL8367C_PORT_EGRESSBW_MSB_BASE RTL8367C_REG_PORT0_EGRESSBW_CTRL1 +#define RTL8367C_PORT_EGRESSBW_MSB_REG(port) (RTL8367C_PORT_EGRESSBW_MSB_BASE + (port << 1)) + +/* (16'h0500) table_reg */ + +#define RTL8367C_TABLE_ACCESS_CTRL_REG RTL8367C_REG_TABLE_ACCESS_CTRL + +#define RTL8367C_TABLE_ACCESS_ADDR_REG RTL8367C_REG_TABLE_ACCESS_ADDR + +#define RTL8367C_TABLE_ACCESS_STATUS_REG RTL8367C_REG_TABLE_LUT_ADDR + +#define RTL8367C_TABLE_ACCESS_WRDATA_BASE RTL8367C_REG_TABLE_WRITE_DATA0 +#define RTL8367C_TABLE_ACCESS_WRDATA_REG(index) (RTL8367C_TABLE_ACCESS_WRDATA_BASE + index) + +#define RTL8367C_TABLE_ACCESS_RDDATA_BASE RTL8367C_REG_TABLE_READ_DATA0 +#define RTL8367C_TABLE_ACCESS_RDDATA_REG(index) (RTL8367C_TABLE_ACCESS_RDDATA_BASE + index) + + + +/* (16'h0600) acl_reg */ + +#define RTL8367C_ACL_RULE_TEMPLATE_CTRL_BASE RTL8367C_REG_ACL_RULE_TEMPLATE0_CTRL0 +#define RTL8367C_ACL_RULE_TEMPLATE_CTRL_REG(template) (RTL8367C_ACL_RULE_TEMPLATE_CTRL_BASE + template * 0x4) +#define RTL8367C_ACL_TEMPLATE_FIELD_OFFSET(field) ((field & 0x01) <<3) +#define RTL8367C_ACL_TEMPLATE_FIELD_MASK(field) (0x3F << RTL8367C_ACL_TEMPLATE_FIELD_OFFSET(field)) + +#define RTL8367C_ACL_ACTION_CTRL_BASE RTL8367C_REG_ACL_ACTION_CTRL0 +#define RTL8367C_ACL_ACTION_CTRL_REG(rule) (RTL8367C_ACL_ACTION_CTRL_BASE + (rule >> 1)) +#define RTL8367C_ACL_ACTION_CTRL2_BASE RTL8367C_REG_ACL_ACTION_CTRL32 +#define RTL8367C_ACL_ACTION_CTRL2_REG(rule) (RTL8367C_ACL_ACTION_CTRL2_BASE + ((rule-64) >> 1)) + +#define RTL8367C_ACL_OP_NOT_OFFSET(rule) (6 + ((rule & 0x1) << 3)) +#define RTL8367C_ACL_OP_NOT_MASK(rule) (1 << RTL8367C_ACL_OP_NOT_OFFSET(rule)) +#define RTL8367C_ACL_OP_ACTION_OFFSET(rule) ((rule & 0x1) << 3) +#define RTL8367C_ACL_OP_ACTION_MASK(rule) (0x3F << RTL8367C_ACL_OP_ACTION_OFFSET(rule)) + +#define RTL8367C_ACL_ENABLE_REG RTL8367C_REG_ACL_ENABLE +#define RTL8367C_ACL_UNMATCH_PERMIT_REG RTL8367C_REG_ACL_UNMATCH_PERMIT + +/* (16'h0700) cvlan_reg */ + +#define RTL8367C_VLAN_PVID_CTRL_BASE RTL8367C_REG_VLAN_PVID_CTRL0 +#define RTL8367C_VLAN_PVID_CTRL_REG(port) (RTL8367C_VLAN_PVID_CTRL_BASE + (port >> 1)) +#define RTL8367C_PORT_VIDX_OFFSET(port) ((port &1)<<3) +#define RTL8367C_PORT_VIDX_MASK(port) (RTL8367C_PORT0_VIDX_MASK << RTL8367C_PORT_VIDX_OFFSET(port)) + +#define RTL8367C_VLAN_PPB_VALID_BASE RTL8367C_REG_VLAN_PPB0_VALID +#define RTL8367C_VLAN_PPB_VALID_REG(item) (RTL8367C_VLAN_PPB_VALID_BASE + (item << 3)) + +#define RTL8367C_VLAN_PPB_CTRL_BASE RTL8367C_REG_VLAN_PPB0_CTRL0 +#define RTL8367C_VLAN_PPB_CTRL_REG(item, port) (RTL8367C_VLAN_PPB_CTRL_BASE + (item << 3) + (port / 3) ) +#define RTL8367C_VLAN_PPB_CTRL_OFFSET(port) ((port % 3) * 5) +#define RTL8367C_VLAN_PPB_CTRL_MASK(port) (RTL8367C_VLAN_PPB0_CTRL0_PORT0_INDEX_MASK << RTL8367C_VLAN_PPB_CTRL_OFFSET(port)) + +#define RTL8367C_VLAN_PPB_FRAMETYPE_BASE RTL8367C_REG_VLAN_PPB0_CTRL2 +#define RTL8367C_VLAN_PPB_FRAMETYPE_REG(item) (RTL8367C_VLAN_PPB_FRAMETYPE_BASE + (item << 3)) +#define RTL8367C_VLAN_PPB_FRAMETYPE_MASK RTL8367C_VLAN_PPB0_CTRL2_FRAME_TYPE_MASK + +#define RTL8367C_VLAN_PPB_ETHERTYPR_BASE RTL8367C_REG_VLAN_PPB0_CTRL3 +#define RTL8367C_VLAN_PPB_ETHERTYPR_REG(item) (RTL8367C_VLAN_PPB_ETHERTYPR_BASE + (item << 3)) + +#define RTL8367C_VLAN_MEMBER_CONFIGURATION_BASE RTL8367C_REG_VLAN_MEMBER_CONFIGURATION0_CTRL0 + + +#define RTL8367C_VLAN_CTRL_REG RTL8367C_REG_VLAN_CTRL + +#define RTL8367C_VLAN_INGRESS_REG RTL8367C_REG_VLAN_INGRESS + +#define RTL8367C_VLAN_ACCEPT_FRAME_TYPE_BASE RTL8367C_REG_VLAN_ACCEPT_FRAME_TYPE_CTRL0 +#define RTL8367C_VLAN_ACCEPT_FRAME_TYPE_REG(port) (RTL8367C_VLAN_ACCEPT_FRAME_TYPE_BASE + (port >> 3)) +#define RTL8367C_VLAN_ACCEPT_FRAME_TYPE_MASK(port) (RTL8367C_PORT0_FRAME_TYPE_MASK << ((port & 0x7) << 1)) + +#define RTL8367C_PORT_EFID_BASE RTL8367C_REG_PORT_EFID_CTRL0 +#define RTL8367C_PORT_EFID_REG(port) (RTL8367C_PORT_EFID_BASE + (port >> 2)) +#define RTL8367C_PORT_EFID_OFFSET(port) ((port & 0x3) << 2) +#define RTL8367C_PORT_EFID_MASK(port) (RTL8367C_PORT0_EFID_MASK << RTL8367C_PORT_EFID_OFFSET(port)) + +#define RTL8367C_PORT_PBFIDEN_REG RTL8367C_REG_PORT_PBFIDEN + +#define RTL8367C_PORT_PBFID_BASE RTL8367C_REG_PORT0_PBFID +#define RTL8367C_PORT_PBFID_REG(port) (RTL8367C_PORT_PBFID_BASE + port) + +/* (16'h0800) dpm_reg */ + +#define RTL8367C_RMA_CTRL_BASE RTL8367C_REG_RMA_CTRL00 + + +#define RTL8367C_VLAN_PORTBASED_PRIORITY_BASE RTL8367C_REG_VLAN_PORTBASED_PRIORITY_CTRL0 +#define RTL8367C_VLAN_PORTBASED_PRIORITY_REG(port) (RTL8367C_VLAN_PORTBASED_PRIORITY_BASE + (port >> 2)) +#define RTL8367C_VLAN_PORTBASED_PRIORITY_OFFSET(port) ((port & 0x3) << 2) +#define RTL8367C_VLAN_PORTBASED_PRIORITY_MASK(port) (0x7 << RTL8367C_VLAN_PORTBASED_PRIORITY_OFFSET(port)) + +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM_BASE RTL8367C_REG_VLAN_PPB_PRIORITY_ITEM0_CTRL0 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM_REG(port, item) (RTL8367C_VLAN_PPB_PRIORITY_ITEM_BASE + (item << 2)+ (port>>2)) +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM_OFFSET(port) ((port & 0x3) <<2) +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM_MASK(port) (RTL8367C_VLAN_PPB_PRIORITY_ITEM0_CTRL0_PORT0_PRIORITY_MASK << RTL8367C_VLAN_PPB_PRIORITY_ITEM_OFFSET(port)) + +#define RTL8367C_QOS_1Q_PRIORITY_REMAPPING_BASE RTL8367C_REG_QOS_1Q_PRIORITY_REMAPPING_CTRL0 +#define RTL8367C_QOS_1Q_PRIORITY_REMAPPING_REG(pri) (RTL8367C_QOS_1Q_PRIORITY_REMAPPING_BASE + (pri >> 2)) +#define RTL8367C_QOS_1Q_PRIORITY_REMAPPING_OFFSET(pri) ((pri & 0x3) << 2) +#define RTL8367C_QOS_1Q_PRIORITY_REMAPPING_MASK(pri) (0x7 << RTL8367C_QOS_1Q_PRIORITY_REMAPPING_OFFSET(pri)) + +#define RTL8367C_QOS_DSCP_TO_PRIORITY_BASE RTL8367C_REG_QOS_DSCP_TO_PRIORITY_CTRL0 +#define RTL8367C_QOS_DSCP_TO_PRIORITY_REG(dscp) (RTL8367C_QOS_DSCP_TO_PRIORITY_BASE + (dscp >> 2)) +#define RTL8367C_QOS_DSCP_TO_PRIORITY_OFFSET(dscp) ((dscp & 0x3) << 2) +#define RTL8367C_QOS_DSCP_TO_PRIORITY_MASK(dscp) (0x7 << RTL8367C_QOS_DSCP_TO_PRIORITY_OFFSET(dscp)) + +#define RTL8367C_QOS_PORTBASED_PRIORITY_BASE RTL8367C_REG_QOS_PORTBASED_PRIORITY_CTRL0 +#define RTL8367C_QOS_PORTBASED_PRIORITY_REG(port) (RTL8367C_QOS_PORTBASED_PRIORITY_BASE + (port >> 2)) +#define RTL8367C_QOS_PORTBASED_PRIORITY_OFFSET(port) ((port & 0x3) << 2) +#define RTL8367C_QOS_PORTBASED_PRIORITY_MASK(port) (0x7 << RTL8367C_QOS_PORTBASED_PRIORITY_OFFSET(port)) + +#define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_BASE RTL8367C_REG_QOS_INTERNAL_PRIORITY_DECISION_CTRL0 +#define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_REG(src) (RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_BASE + (src >> 1)) +#define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_OFFSET(src) ((src & 1) << 3) +#define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_MASK(src) (RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_CTRL0_QOS_PORT_WEIGHT_MASK << RTL8367C_QOS_INTERNAL_PRIORITY_DECISION2_OFFSET(src)) + +#define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION2_BASE RTL8367C_REG_QOS_INTERNAL_PRIORITY_DECISION2_CTRL0 +#define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION2_REG(src) (RTL8367C_QOS_INTERNAL_PRIORITY_DECISION2_BASE + (src >> 1)) +#define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION2_OFFSET(src) ((src & 1) << 3) +#define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION2_MASK(src) (RTL8367C_QOS_INTERNAL_PRIORITY_DECISION2_CTRL0_QOS_PORT_WEIGHT_MASK << RTL8367C_QOS_INTERNAL_PRIORITY_DECISION2_OFFSET(src)) + +#define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_IDX_CTRL RTL8367C_REG_QOS_INTERNAL_PRIORITY_DECISION_IDX +#define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_IDX(port) (1 << port) + +#define RTL8367C_QOS_PRIPORITY_REMAPPING_IN_CPU_BASE RTL8367C_REG_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL0 +#define RTL8367C_QOS_PRIPORITY_REMAPPING_IN_CPU_REG(pri) (RTL8367C_QOS_PRIPORITY_REMAPPING_IN_CPU_BASE + (pri >> 2)) +#define RTL8367C_QOS_PRIPORITY_REMAPPING_IN_CPU_OFFSET(pri) ((pri & 0x3) << 2) +#define RTL8367C_QOS_PRIPORITY_REMAPPING_IN_CPU_MASK(pri) (RTL8367C_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL0_PRIORITY0_MASK << RTL8367C_QOS_PRIPORITY_REMAPPING_IN_CPU_OFFSET(pri)) + +#define RTL8367C_QOS_TRAP_PRIORITY_CTRL0_REG RTL8367C_REG_QOS_TRAP_PRIORITY0 + +#define RTL8367C_QOS_TRAP_PRIORITY_CTRL1_REG RTL8367C_REG_QOS_TRAP_PRIORITY1 + +#define RTL8367C_QOS_DSCP_TO_DSCP_BASE RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL0 +#define RTL8367C_QOS_DSCP_TO_DSCP_REG(dscp) (RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL0 + (dscp >> 1)) +#define RTL8367C_QOS_DSCP_TO_DSCP_OFFSET(dscp) ((dscp & 0x1) << 8) +#define RTL8367C_QOS_DSCP_TO_DSCP_MASK(dscp) (0x3F << RTL8367C_QOS_DSCP_TO_DSCP_OFFSET(dscp)) + +#define RTL8367C_UNUCAST_FLOADING_PMSK_REG RTL8367C_REG_UNDA_FLOODING_PMSK + +#define RTL8367C_UNMCAST_FLOADING_PMSK_REG RTL8367C_REG_UNMCAST_FLOADING_PMSK + +#define RTL8367C_BCAST_FLOADING_PMSK_REG RTL8367C_REG_BCAST_FLOADING_PMSK + +#define RTL8367C_PORT_ISOLATION_PORT_MASK_BASE RTL8367C_REG_PORT_ISOLATION_PORT0_MASK +#define RTL8367C_PORT_ISOLATION_PORT_MASK_REG(port) (RTL8367C_PORT_ISOLATION_PORT_MASK_BASE + port) + +#define RTL8367C_FORCE_CTRL_REG RTL8367C_REG_FORCE_CTRL + +#define RTL8367C_SOURCE_PORT_BLOCK_REG RTL8367C_REG_SOURCE_PORT_PERMIT + +#define RTL8367C_IPMCAST_VLAN_LEAKY_REG RTL8367C_REG_IPMCAST_VLAN_LEAKY + +#define RTL8367C_IPMCAST_PORTISO_LEAKY_REG RTL8367C_REG_IPMCAST_PORTISO_LEAKY + +#define RTL8367C_PORT_SECURIT_CTRL_REG RTL8367C_REG_PORT_SECURITY_CTRL + +#define RTL8367C_UNKNOWN_IPV4_MULTICAST_BASE RTL8367C_REG_UNKNOWN_IPV4_MULTICAST_CTRL0 +#define RTL8367C_UNKNOWN_IPV4_MULTICAST_REG(port) (RTL8367C_UNKNOWN_IPV4_MULTICAST_BASE + (port >> 3)) +#define RTL8367C_UNKNOWN_IPV4_MULTICAST_OFFSET(port) ((port & 0x7) << 1) +#define RTL8367C_UNKNOWN_IPV4_MULTICAST_MASK(port) (RTL8367C_PORT0_UNKNOWN_IP4_MCAST_MASK << RTL8367C_UNKNOWN_IPV4_MULTICAST_OFFSET(port)) + +#define RTL8367C_UNKNOWN_IPV6_MULTICAST_BASE RTL8367C_REG_UNKNOWN_IPV6_MULTICAST_CTRL0 +#define RTL8367C_UNKNOWN_IPV6_MULTICAST_REG(port) (RTL8367C_UNKNOWN_IPV6_MULTICAST_BASE + (port >> 3)) +#define RTL8367C_UNKNOWN_IPV6_MULTICAST_OFFSET(port) ((port & 0x7) << 1) +#define RTL8367C_UNKNOWN_IPV6_MULTICAST_MASK(port) (RTL8367C_PORT0_UNKNOWN_IP4_MCAST_MASK << RTL8367C_UNKNOWN_IPV6_MULTICAST_OFFSET(port)) + +#define RTL8367C_UNKNOWN_L2_MULTICAST_BASE RTL8367C_REG_UNKNOWN_L2_MULTICAST_CTRL0 +#define RTL8367C_UNKNOWN_L2_MULTICAST_REG(port) (RTL8367C_UNKNOWN_L2_MULTICAST_BASE + (port >> 3)) +#define RTL8367C_UNKNOWN_L2_MULTICAST_OFFSET(port) ((port & 0x7) << 1) +#define RTL8367C_UNKNOWN_L2_MULTICAST_MASK(port) (RTL8367C_PORT0_UNKNOWN_L2_MCAST_MASK << RTL8367C_UNKNOWN_L2_MULTICAST_OFFSET(port)) + +#define RTL8367C_PORT_TRUNK_CTRL_REG RTL8367C_REG_PORT_TRUNK_CTRL +#define RTL8367C_PORT_TRUNK_HASH_MASK 0x007F + +#define RTL8367C_PORT_TRUNK_GROUP_MASK_REG RTL8367C_REG_PORT_TRUNK_GROUP_MASK +#define RTL8367C_PORT_TRUNK_GROUP_MASK_OFFSET(group) (group << 2) +#define RTL8367C_PORT_TRUNK_GROUP_MASK_MASK(group) (RTL8367C_PORT_TRUNK_GROUP0_MASK_MASK << RTL8367C_PORT_TRUNK_GROUP_MASK_OFFSET(group)) + +#define RTL8367C_PORT_TRUNK_FLOWCTRL_REG RTL8367C_REG_PORT_TRUNK_FLOWCTRL + +#define RTL8367C_QOS_PORT_QUEUE_NUMBER_BASE RTL8367C_REG_QOS_PORT_QUEUE_NUMBER_CTRL0 +#define RTL8367C_QOS_PORT_QUEUE_NUMBER_REG(port) (RTL8367C_QOS_PORT_QUEUE_NUMBER_BASE + (port >> 2)) +#define RTL8367C_QOS_PORT_QUEUE_NUMBER_OFFSET(port) ((port & 0x3) << 2) +#define RTL8367C_QOS_PORT_QUEUE_NUMBER_MASK(port) (0x7 << RTL8367C_QOS_PORT_QUEUE_NUMBER_OFFSET(port)) + +#define RTL8367C_QOS_1Q_PRIORITY_TO_QID_BASE RTL8367C_REG_QOS_1Q_PRIORITY_TO_QID_CTRL0 +#define RTL8367C_QOS_1Q_PRIORITY_TO_QID_REG(index, pri) (RTL8367C_QOS_1Q_PRIORITY_TO_QID_BASE + (index << 1) + (pri >> 2)) +#define RTL8367C_QOS_1Q_PRIORITY_TO_QID_OFFSET(pri) ((pri & 0x3) << 2) +#define RTL8367C_QOS_1Q_PRIORITY_TO_QID_MASK(pri) (RTL8367C_QOS_1Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_MASK << RTL8367C_QOS_1Q_PRIORITY_TO_QID_OFFSET(pri)) + +#define RTL8367C_DEBUG_INFO_BASE RTL8367C_REG_PORT_DEBUG_INFO_CTRL0 +#define RTL8367C_DEBUG_INFO_REG(port) (RTL8367C_DEBUG_INFO_BASE + (port >>1)) +#define RTL8367C_DEBUG_INFO_OFFSET(port) ((port&1)<<3) +#define RTL8367C_DEBUG_INFO_MASK(port) (RTL8367C_PORT0_DEBUG_INFO_MASK << RTL8367C_DEBUG_INFO_OFFSET(port)) + +/* (16'h0a00) l2_reg */ + +#define RTL8367C_VLAN_MSTI_BASE RTL8367C_REG_VLAN_MSTI0_CTRL0 +#define RTL8367C_VLAN_MSTI_REG(tree, port) (RTL8367C_VLAN_MSTI_BASE + (tree << 1) + (port >> 3)) +#define RTL8367C_VLAN_MSTI_OFFSET(port) ((port & 0x7) << 1) +#define RTL8367C_VLAN_MSTI_MASK(port) (RTL8367C_VLAN_MSTI0_CTRL0_PORT0_STATE_MASK << RTL8367C_VLAN_MSTI_OFFSET(port)) + +#define RTL8367C_LUT_PORT_LEARN_LIMITNO_BASE RTL8367C_REG_LUT_PORT0_LEARN_LIMITNO +#define RTL8367C_LUT_PORT_LEARN_LIMITNO_REG(port) (RTL8367C_LUT_PORT_LEARN_LIMITNO_BASE + port) + +#define RTL8367C_LUT_CFG_REG RTL8367C_REG_LUT_CFG + +#define RTL8367C_LUT_AGEOUT_CTRL_REG RTL8367C_REG_LUT_AGEOUT_CTRL + +#define RTL8367C_FORCE_FLUSH_REG RTL8367C_REG_FORCE_FLUSH + +#define RTL8367C_STORM_BCAST_REG RTL8367C_REG_STORM_BCAST + +#define RTL8367C_STORM_MCAST_REG RTL8367C_REG_STORM_MCAST + +#define RTL8367C_STORM_UNKNOWN_UCAST_REG RTL8367C_REG_STORM_UNKOWN_UCAST + +#define RTL8367C_STORM_UNKNOWN_MCAST_REG RTL8367C_REG_STORM_UNKOWN_MCAST + +#define RTL8367C_STORM_BCAST_METER_CTRL_BASE RTL8367C_REG_STORM_BCAST_METER_CTRL0 +#define RTL8367C_STORM_BCAST_METER_CTRL_REG(port) (RTL8367C_STORM_BCAST_METER_CTRL_BASE + (port >> 1)) +#define RTL8367C_STORM_BCAST_METER_CTRL_OFFSET(port) ((port & 0x1) << 3) +#define RTL8367C_STORM_BCAST_METER_CTRL_MASK(port) (0xFF << RTL8367C_STORM_BCAST_METER_CTRL_OFFSET(port)) + +#define RTL8367C_STORM_MCAST_METER_CTRL_BASE RTL8367C_REG_STORM_MCAST_METER_CTRL0 +#define RTL8367C_STORM_MCAST_METER_CTRL_REG(port) (RTL8367C_STORM_MCAST_METER_CTRL_BASE + (port >> 1)) +#define RTL8367C_STORM_MCAST_METER_CTRL_OFFSET(port) ((port & 0x1) << 3) +#define RTL8367C_STORM_MCAST_METER_CTRL_MASK(port) (0xFF << RTL8367C_STORM_MCAST_METER_CTRL_OFFSET(port)) + +#define RTL8367C_STORM_UNDA_METER_CTRL_BASE RTL8367C_REG_STORM_UNDA_METER_CTRL0 +#define RTL8367C_STORM_UNDA_METER_CTRL_REG(port) (RTL8367C_STORM_UNDA_METER_CTRL_BASE + (port >> 1)) +#define RTL8367C_STORM_UNDA_METER_CTRL_OFFSET(port) ((port & 0x1) << 3) +#define RTL8367C_STORM_UNDA_METER_CTRL_MASK(port) (0xFF << RTL8367C_STORM_UNDA_METER_CTRL_OFFSET(port)) + +#define RTL8367C_STORM_UNMC_METER_CTRL_BASE RTL8367C_REG_STORM_UNMC_METER_CTRL0 +#define RTL8367C_STORM_UNMC_METER_CTRL_REG(port) (RTL8367C_STORM_UNMC_METER_CTRL_BASE + (port >> 1)) +#define RTL8367C_STORM_UNMC_METER_CTRL_OFFSET(port) ((port & 0x1) << 3) +#define RTL8367C_STORM_UNMC_METER_CTRL_MASK(port) (0xFF << RTL8367C_STORM_UNMC_METER_CTRL_OFFSET(port)) + +#define RTL8367C_OAM_PARSER_OFFSET(port) (port*2) +#define RTL8367C_OAM_PARSER_MASK(port) (RTL8367C_PORT0_PARACT_MASK << RTL8367C_OAM_PARSER_OFFSET(port)) + +#define RTL8367C_OAM_MULTIPLEXER_OFFSET(port) (port*2) +#define RTL8367C_OAM_MULTIPLEXER_MASK(port) (RTL8367C_PORT0_PARACT_MASK << RTL8367C_OAM_MULTIPLEXER_OFFSET(port)) + +#define RTL8367C_OAM_CTRL_REG RTL8367C_REG_OAM_CTRL + +#define RTL8367C_DOT1X_PORT_ENABLE_REG RTL8367C_REG_DOT1X_PORT_ENABLE + +#define RTL8367C_DOT1X_MAC_ENABLE_REG RTL8367C_REG_DOT1X_MAC_ENABLE + +#define RTL8367C_DOT1X_PORT_AUTH_REG RTL8367C_REG_DOT1X_PORT_AUTH + +#define RTL8367C_DOT1X_PORT_OPDIR_REG RTL8367C_REG_DOT1X_PORT_OPDIR + +#define RTL8367C_DOT1X_UNAUTH_ACT_BASE RTL8367C_REG_DOT1X_UNAUTH_ACT_W0 +#define RTL8367C_DOT1X_UNAUTH_ACT_OFFSET(port) ((port & 0x7) << 1) +#define RTL8367C_DOT1X_UNAUTH_ACT_MASK(port) (RTL8367C_DOT1X_PORT0_UNAUTHBH_MASK << RTL8367C_DOT1X_UNAUTH_ACT_OFFSET(port)) + +#define RTL8367C_DOT1X_CFG_REG RTL8367C_REG_DOT1X_CFG + +#define RTL8367C_REG_L2_LRN_CNT_BASE RTL8367C_REG_L2_LRN_CNT_CTRL0 +#define RTL8367C_REG_L2_LRN_CNT_REG(port) (RTL8367C_REG_L2_LRN_CNT_BASE + port) + +/* (16'h0b00) mltvlan_reg */ + +#define RTL8367C_SVLAN_MCAST2S_ENTRY_BASE_REG(index) (RTL8367C_REG_SVLAN_MCAST2S_ENTRY0_CTRL0 + index*5) + +/* (16'h0c00) svlan_reg */ + +#define RTL8367C_SVLAN_MEMBERCFG_BASE_REG(index) (RTL8367C_REG_SVLAN_MEMBERCFG0_CTRL1 + index*3) +#define RTL8367C_SVLAN_C2SCFG_BASE_REG(index) (RTL8367C_REG_SVLAN_C2SCFG0_CTRL0+ index*3) +#define RTL8367C_SVLAN_CFG_REG RTL8367C_REG_SVLAN_CFG + +/* (16'h0f00) hsactrl_reg */ + +#define RTL8367C_SVLAN_S2C_ENTRY_BASE_REG(index) (RTL8367C_REG_SVLAN_SP2C_ENTRY0_CTRL0 + index*2) + +/* (16'h1000) mib_reg */ + +#define RTL8367C_MIB_COUNTER_BASE_REG RTL8367C_REG_MIB_COUNTER0 + +#define RTL8367C_MIB_ADDRESS_REG RTL8367C_REG_MIB_ADDRESS + +#define RTL8367C_MIB_CTRL_REG RTL8367C_REG_MIB_CTRL0 +#define RTL8367C_MIB_PORT07_MASK (0xFF<> 4)) +#define RTL8367C_REG_METER_EXCEED_INDICATOR_OFFSET(meter) (meter & 0xF) + +/* (16'h1200) swcore_reg */ + +#define RTL8367C_VS_TPID_REG RTL8367C_REG_VS_TPID + +#define RTL8367C_SWITCH_MAC_BASE RTL8367C_REG_SWITCH_MAC0 + +#define RTL8367C_REMARKING_CTRL_REG RTL8367C_REG_SWITCH_CTRL0 + +#define RTL8367C_QOS_DSCP_REMARK_BASE RTL8367C_REG_QOS_DSCP_REMARK_CTRL0 +#define RTL8367C_QOS_DSCP_REMARK_REG(pri) (RTL8367C_QOS_DSCP_REMARK_BASE + (pri >> 1)) +#define RTL8367C_QOS_DSCP_REMARK_OFFSET(pri) (((pri) & 0x1) << 3) +#define RTL8367C_QOS_DSCP_REMARK_MASK(pri) (0x3F << RTL8367C_QOS_DSCP_REMARK_OFFSET(pri)) + +#define RTL8367C_QOS_1Q_REMARK_BASE RTL8367C_REG_QOS_1Q_REMARK_CTRL0 +#define RTL8367C_QOS_1Q_REMARK_REG(pri) (RTL8367C_QOS_1Q_REMARK_BASE + (pri >> 2)) +#define RTL8367C_QOS_1Q_REMARK_OFFSET(pri) ((pri & 0x3) << 2) +#define RTL8367C_QOS_1Q_REMARK_MASK(pri) (0x7 << RTL8367C_QOS_1Q_REMARK_OFFSET(pri)) + +#define RTL8367C_PTKGEN_PAYLOAD_CTRL0_REG RTL8367C_REG_PTKGEN_PAYLOAD_CTRL0 + +#define RTL8367C_PTKGEN_PAYLOAD_CTRL1_REG RTL8367C_REG_PTKGEN_PAYLOAD_CTRL1 + +#define RTL8367C_SVLAN_UPLINK_PORTMASK_REG RTL8367C_REG_SVLAN_UPLINK_PORTMASK + +#define RTL8367C_CPU_PORT_MASK_REG RTL8367C_REG_CPU_PORT_MASK + +#define RTL8367C_CPU_CTRL_REG RTL8367C_REG_CPU_CTRL + +#define RTL8367C_MIRROR_CTRL_REG RTL8367C_REG_MIRROR_CTRL + + +#define RTL8367C_FLOWCRTL_EGRESS_QUEUE_ENABLE_BASE RTL8367C_REG_FLOWCRTL_EGRESS_QUEUE_ENABLE_CTRL0 +#define RTL8367C_FLOWCRTL_EGRESS_QUEUE_ENABLE_REG(port) (RTL8367C_FLOWCRTL_EGRESS_QUEUE_ENABLE_BASE + (port >> 1)) +#define RTL8367C_FLOWCRTL_EGRESS_QUEUE_ENABLE_REG_OFFSET(port) ((port & 0x1) << 3) +#define RTL8367C_FLOWCRTL_EGRESS_QUEUE_ENABLE_REG_MASK(port) (RTL8367C_PORT0_QUEUE_MASK_MASK << RTL8367C_FLOWCRTL_EGRESS_QUEUE_ENABLE_REG_OFFSET(port)) + + +#define RTL8367C_FLOWCTRL_PORT_PAGE_COUNTER_BASE RTL8367C_REG_FLOWCTRL_PORT0_PAGE_COUNTER +#define RTL8367C_FLOWCTRL_PORT_PAGE_COUNTER_REG(port) (RTL8367C_FLOWCTRL_PORT_PAGE_COUNTER_BASE + port) +#define RTL8367C_FLOWCTRL_PORT_PAGE_COUNTER_MASK RTL8367C_FLOWCTRL_PORT0_PAGE_COUNTER_MASK + +#define RTL8367C_FLOWCTRL_PORT_PAGE_MAX_BASE RTL8367C_REG_FLOWCTRL_PORT0_PAGE_MAX +#define RTL8367C_FLOWCTRL_PORT_PAGE_MAX_REG(port) (RTL8367C_FLOWCTRL_PORT_PAGE_MAX_BASE + port) +#define RTL8367C_FLOWCTRL_PORT_PAGE_MAX_MASK RTL8367C_FLOWCTRL_PORT0_PAGE_MAX_MASK + +#define RTL8367C_FIELD_SELECTOR_REG(index) (RTL8367C_REG_FIELD_SELECTOR0 + index) +#define RTL8367C_FIELD_SELECTOR_ENABLE_OFFSET RTL8367C_FIELD_SELECTOR0_ENABLE_OFFSET +#define RTL8367C_FIELD_SELECTOR_ENABLE_MASK RTL8367C_FIELD_SELECTOR0_ENABLE_MASK +#define RTL8367C_FIELD_SELECTOR_FORMAT_OFFSET RTL8367C_FIELD_SELECTOR0_FORMAT_OFFSET +#define RTL8367C_FIELD_SELECTOR_FORMAT_MASK RTL8367C_FIELD_SELECTOR0_FORMAT_MASK +#define RTL8367C_FIELD_SELECTOR_OFFSET_OFFSET RTL8367C_FIELD_SELECTOR0_OFFSET_OFFSET +#define RTL8367C_FIELD_SELECTOR_OFFSET_MASK RTL8367C_FIELD_SELECTOR0_OFFSET_MASK + +/* (16'h1300) chip_reg*/ + +/* (16'h1400) mtrpool_reg */ +#define RTL8367C_METER_RATE_BASE RTL8367C_REG_METER0_RATE_CTRL0 +#define RTL8367C_METER_RATE_REG(meter) ((meter << 1) + RTL8367C_METER_RATE_BASE) + +#define RTL8367C_METER_BUCKET_SIZE_BASE RTL8367C_REG_METER0_BUCKET_SIZE +#define RTL8367C_METER_BUCKET_SIZE_REG(meter) (RTL8367C_METER_BUCKET_SIZE_BASE + meter) + +#define RTL8367C_LEAKY_BUCKET_TICK_REG RTL8367C_REG_METER_CTRL0 +#define RTL8367C_LEAKY_BUCKET_TICK_OFFSET RTL8367C_METER_TICK_OFFSET +#define RTL8367C_LEAKY_BUCKET_TICK_MASK RTL8367C_METER_TICK_MASK + +#define RTL8367C_LEAKY_BUCKET_TOKEN_REG RTL8367C_REG_METER_CTRL1 +#define RTL8367C_LEAKY_BUCKET_TOKEN_OFFSET RTL8367C_METER_CTRL1_OFFSET +#define RTL8367C_LEAKY_BUCKET_TOKEN_MASK RTL8367C_METER_CTRL1_MASK + +#define RTL8367C_METER_OVERRATE_INDICATOR_BASE RTL8367C_REG_METER_OVERRATE_INDICATOR0 +#define RTL8367C_METER_OVERRATE_INDICATOR_REG(meter) (RTL8367C_METER_OVERRATE_INDICATOR_BASE + (meter >> 4)) +#define RTL8367C_METER_EXCEED_OFFSET(meter) (meter & 0xF) +#define RTL8367C_METER_EXCEED_MASK(meter) (1 << RTL8367C_METER_EXCEED_OFFSET(meter)) + +#define RTL8367C_METER_IFG_CTRL_BASE RTL8367C_REG_METER_IFG_CTRL0 +#define RTL8367C_METER_IFG_CTRL_REG(meter) (RTL8367C_METER_IFG_CTRL_BASE + (meter >> 4)) +#define RTL8367C_METER_IFG_OFFSET(meter) (meter & 0xF) +#define RTL8367C_METER_IFG_MASK(meter) (1 << RTL8367C_METER_IFG_OFFSET(meter)) + +#define RTL8367C_FLOWCTRL_CTRL_REG RTL8367C_REG_FLOWCTRL_CTRL0 + +/* (16'h1800)8051_RLDP_EEE_reg */ +#define RTL8367C_EEELLDP_CTRL0_REG RTL8367C_REG_EEELLDP_CTRL0 + +#define RTL8367C_EEELLDP_CTRL1_REG RTL8367C_REG_EEELLDP_CTRL1 + +#define RTL8367C_EEELLDP_PMSK_REG RTL8367C_REG_EEELLDP_PMSK + +#define RTL8367C_EEELLDP_TX_FRAMEU_REG_BASE RTL8367C_REG_EEELLDP_FRAMEU00 + +#define RTL8367C_EEELLDP_TX_CAP_FRAMEL_REG_BASE RTL8367C_REG_EEELLDP_CAP_FRAMEL00 + +#define RTL8367C_EEELLDP_RX_VALUE_PORT_BASE RTL8367C_REG_EEELLDP_RX_VALUE_P00_00 +#define RTL8367C_EEELLDP_RX_VALUE_PORT_REG(port) (RTL8367C_EEELLDP_RX_VALUE_PORT_BASE + (port * 9)) + +#define RTL8367C_RLDP_CTRL0_REG RTL8367C_REG_RLDP_CTRL0 +#define RTL8367C_RLDP_MODE_OFFSET 14 + +#define RTL8367C_RLDP_RETRY_COUNT_REG RTL8367C_REG_RLDP_CTRL1 + +#define RTL8367C_RLDP_RETRY_PERIOD_LOOPSTATE_REG RTL8367C_REG_RLDP_CTRL2 + +#define RTL8367C_RLDP_RETRY_PERIOD_CHKSTATE_REG RTL8367C_REG_RLDP_CTRL3 + +#define RTL8367C_RLDP_TX_PMSK_REG RTL8367C_REG_RLDP_CTRL4 + +#define RTL8367C_RLDP_RAND_NUM_REG_BASE RTL8367C_REG_RLDP_RAND_NUM0 + +#define RTL8367C_RLDP_MAGIC_NUM_REG_BASE RTL8367C_REG_RLDP_MAGIC_NUM0 + +#define RTL8367C_RLDP_LOOP_PMSK_REG RTL8367C_REG_RLDP_LOOPSTATUS_INDICATOR + +#define RTL8367C_RLDP_LOOP_PORT_BASE RTL8367C_REG_RLDP_LOOP_PORT_REG0 +#define RTL8367C_RLDP_LOOP_PORT_REG(port) (RTL8367C_RLDP_LOOP_PORT_BASE + (port >> 1)) +#define RTL8367C_RLDP_LOOP_PORT_OFFSET(port) ((port & 0x1) << 3) +#define RTL8367C_RLDP_LOOP_PORT_MASK(port) (RTL8367C_RLDP_LOOP_PORT_00_MASK << RTL8367C_RLDP_LOOP_PORT_OFFSET(port)) + +#define RTL8367C_PAGEMETER_PORT_BASE RTL8367C_REG_PAGEMETER_PORT0_CTRL0 +#define RTL8367C_PAGEMETER_PORT_REG(port) (RTL8367C_PAGEMETER_PORT_BASE + 0x20*port) + +#define RTL8367C_HIGHPRI_INDICATOR_REG RTL8367C_REG_HIGHPRI_INDICATOR +#define RTL8367C_PORT_INDICATOR_OFFSET(port) (port) +#define RTL8367C_PORT_INDICATOR_MASK(port) (RTL8367C_PORT0_INDICATOR_MASK << RTL8367C_PORT_INDICATOR_OFFSET(port)) + +#define RTL8367C_HIGHPRI_CFG_REG RTL8367C_REG_HIGHPRI_CFG + +#define RTL8367C_EAV_PRIORITY_REMAPPING_BASE RTL8367C_REG_EAV_CTRL1 +#define RTL8367C_EAV_PRIORITY_REMAPPING_REG(pri) (RTL8367C_EAV_PRIORITY_REMAPPING_BASE + (pri >> 2)) +#define RTL8367C_EAV_PRIORITY_REMAPPING_OFFSET(pri) ((pri & 0x3) * RTL8367C_REMAP_EAV_PRI1_REGEN_OFFSET) +#define RTL8367C_EAV_PRIORITY_REMAPPING_MASK(pri) (RTL8367C_REMAP_EAV_PRI0_REGEN_MASK << RTL8367C_EAV_PRIORITY_REMAPPING_OFFSET(pri)) + +#define RTL8367C_EEEP_CFG_BASE RTL8367C_REG_PORT0_EEECFG +#define RTL8367C_EEEP_CFG_REG(port) (RTL8367C_EEEP_CFG_BASE + (port*0x20)) + +#define RTL8367C_PKG_CFG_BASE RTL8367C_REG_PKTGEN_PORT0_CTRL +#define RTL8367C_PKG_CFG_REG(port) (RTL8367C_PKG_CFG_BASE + (port*0x20)) + +#define RTL8367C_PKG_DA_BASE RTL8367C_REG_PKTGEN_PORT0_DA0 +#define RTL8367C_PKG_DA_REG(port) (RTL8367C_PKG_DA_BASE + (port*0x20)) + +#define RTL8367C_PKG_SA_BASE RTL8367C_REG_PKTGEN_PORT0_SA0 +#define RTL8367C_PKG_SA_REG(port) (RTL8367C_PKG_SA_BASE + (port*0x20)) + +#define RTL8367C_PKG_NUM_BASE RTL8367C_REG_PKTGEN_PORT0_COUNTER0 +#define RTL8367C_PKG_NUM_REG(port) (RTL8367C_PKG_NUM_BASE + (port*0x20)) + +#define RTL8367C_PKG_LENGTH_BASE RTL8367C_REG_PKTGEN_PORT0_TX_LENGTH +#define RTL8367C_PKG_LENGTH_REG(port) (RTL8367C_PKG_LENGTH_BASE + (port*0x20)) + +/* (16'h1c00)IGMP_MLD_reg */ +#define RTL8367C_IGMP_GROUP_USAGE_BASE RTL8367C_REG_IGMP_GROUP_USAGE_LIST0 +#define RTL8367C_IGMP_GROUP_USAGE_REG(idx) (RTL8367C_IGMP_GROUP_USAGE_BASE + (idx / 16)) + +#define RTL8367C_FALLBACK_BASE RTL8367C_REG_FALLBACK_PORT0_CFG0 +#define RTL8367C_FALLBACK_PORT_CFG_REG(port) (RTL8367C_FALLBACK_BASE + (port * 4)) +#define RTL8367C_FALLBACK_PORT_MON_CNT_REG(port) (RTL8367C_FALLBACK_BASE + 1 + (port * 4)) +#define RTL8367C_FALLBACK_PORT_ERR_CNT_REG(port) (RTL8367C_FALLBACK_BASE + 3 + (port * 4)) + + +/* (16'h6400)timer_1588 */ +#define RTL8367C_EAV_CFG_BASE RTL8367C_REG_P0_EAV_CFG +#define RTL8367C_EAV_PORT_CFG_REG(port) (RTL8367C_EAV_CFG_BASE + (port *0x10)) +#define RTL8367C_EAV_CFG_PTP_PHY_EN_EN_OFFSET RTL8367C_P0_EAV_CFG_PTP_PHY_EN_EN_OFFSET +#define RTL8367C_EAV_CFG_RX_PDELAY_RESP_OFFSET RTL8367C_P0_EAV_CFG_RX_PDELAY_RESP_OFFSET +#define RTL8367C_EAV_CFG_RX_PDELAY_REQ_OFFSET RTL8367C_P0_EAV_CFG_RX_PDELAY_REQ_OFFSET +#define RTL8367C_EAV_CFG_RX_DELAY_REQ_OFFSET RTL8367C_P0_EAV_CFG_RX_DELAY_REQ_OFFSET +#define RTL8367C_EAV_CFG_RX_SYNC_OFFSET RTL8367C_P0_EAV_CFG_RX_SYNC_OFFSET +#define RTL8367C_EAV_CFG_TX_PDELAY_RESP_OFFSET RTL8367C_P0_EAV_CFG_TX_PDELAY_RESP_OFFSET +#define RTL8367C_EAV_CFG_TX_PDELAY_REQ_OFFSET RTL8367C_P0_EAV_CFG_TX_PDELAY_REQ_OFFSET +#define RTL8367C_EAV_CFG_TX_DELAY_REQ_OFFSET RTL8367C_P0_EAV_CFG_TX_DELAY_REQ_OFFSET +#define RTL8367C_EAV_CFG_TX_SYNC_OFFSET RTL8367C_P0_EAV_CFG_TX_SYNC_OFFSET + +#define RTL8367C_REG_TX_SYNC_SEQ_ID_BASE RTL8367C_REG_P0_TX_SYNC_SEQ_ID +#define RTL8367C_REG_TX_SYNC_SEQ_ID(port) (RTL8367C_REG_TX_SYNC_SEQ_ID_BASE + (port *0x10)) +#define RTL8367C_REG_SEQ_ID(port, type) (RTL8367C_REG_TX_SYNC_SEQ_ID_BASE + type + (port *0x10)) + +#define RTL8367C_REG_TX_DELAY_REQ_SEQ_ID_BASE RTL8367C_REG_P0_TX_DELAY_REQ_SEQ_ID +#define RTL8367C_REG_TX_PDELAY_REQ_SEQ_ID_BASE RTL8367C_REG_P0_TX_PDELAY_REQ_SEQ_ID +#define RTL8367C_REG_TX_PDELAY_RESP_SEQ_ID_BASE RTL8367C_REG_P0_TX_PDELAY_RESP_SEQ_ID +#define RTL8367C_REG_RX_SYNC_SEQ_ID_BASE RTL8367C_REG_P0_RX_SYNC_SEQ_ID +#define RTL8367C_REG_RX_DELAY_REQ_SEQ_ID_BASE RTL8367C_REG_P0_RX_DELAY_REQ_SEQ_ID +#define RTL8367C_REG_RX_PDELAY_REQ_SEQ_ID_BASE RTL8367C_REG_P0_RX_PDELAY_REQ_SEQ_ID +#define RTL8367C_REG_RX_PDELAY_RESP_SEQ_ID_BASE RTL8367C_REG_P0_RX_PDELAY_RESP_SEQ_ID + +#define RTL8367C_REG_PORT_NSEC_L_BASE RTL8367C_REG_P0_PORT_NSEC_15_0 +#define RTL8367C_REG_PORT_NSEC_L(port) (RTL8367C_REG_PORT_NSEC_L_BASE + (port *0x10)) +#define RTL8367C_REG_PORT_NSEC_H_BASE RTL8367C_REG_P0_PORT_NSEC_26_16 +#define RTL8367C_REG_PORT_NSEC_H(port) (RTL8367C_REG_PORT_NSEC_H_BASE + (port *0x10)) +#define RTL8367C_PORT_NSEC_H_OFFSET RTL8367C_P0_PORT_NSEC_26_16_OFFSET +#define RTL8367C_PORT_NSEC_H_MASK RTL8367C_P0_PORT_NSEC_26_16_MASK + +#define RTL8367C_REG_PORT_SEC_L_BASE RTL8367C_REG_P0_PORT_SEC_15_0 +#define RTL8367C_REG_PORT_SEC_L(port) (RTL8367C_REG_PORT_SEC_L_BASE + (port *0x10)) +#define RTL8367C_REG_PORT_SEC_H_BASE RTL8367C_REG_P0_PORT_SEC_31_16 +#define RTL8367C_REG_PORT_SEC_H(port) (RTL8367C_REG_PORT_SEC_H_BASE + (port *0x10)) + +#endif /*#ifndef _RTL8367C_BASE_H_*/ + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_reg.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_reg.h new file mode 100644 index 00000000..eb4f48b8 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_reg.h @@ -0,0 +1,22819 @@ +#ifndef _RTL8367C_REG_H_ +#define _RTL8367C_REG_H_ + +/************************************************************ +auto-generated register address and field data +*************************************************************/ + +/* (16'h0000)port_reg */ + +#define RTL8367C_REG_PORT0_CGST_HALF_CFG 0x0000 +#define RTL8367C_PORT0_CGST_HALF_CFG_CONGESTION_TIME_OFFSET 4 +#define RTL8367C_PORT0_CGST_HALF_CFG_CONGESTION_TIME_MASK 0xF0 +#define RTL8367C_PORT0_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_OFFSET 0 +#define RTL8367C_PORT0_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_MASK 0xF + +#define RTL8367C_REG_PKTGEN_PORT0_CTRL 0x0001 +#define RTL8367C_PKTGEN_PORT0_CTRL_STATUS_OFFSET 15 +#define RTL8367C_PKTGEN_PORT0_CTRL_STATUS_MASK 0x8000 +#define RTL8367C_PKTGEN_PORT0_CTRL_PKTGEN_STS_OFFSET 13 +#define RTL8367C_PKTGEN_PORT0_CTRL_PKTGEN_STS_MASK 0x2000 +#define RTL8367C_PKTGEN_PORT0_CTRL_CRC_NO_ERROR_OFFSET 4 +#define RTL8367C_PKTGEN_PORT0_CTRL_CRC_NO_ERROR_MASK 0x10 +#define RTL8367C_PKTGEN_PORT0_CTRL_CMD_START_OFFSET 0 +#define RTL8367C_PKTGEN_PORT0_CTRL_CMD_START_MASK 0x1 + +#define RTL8367C_REG_TX_ERR_CNT_PORT0 0x0002 +#define RTL8367C_TX_ERR_CNT_PORT0_OFFSET 0 +#define RTL8367C_TX_ERR_CNT_PORT0_MASK 0x7 + +#define RTL8367C_REG_PKTGEN_PORT0_DA0 0x0003 + +#define RTL8367C_REG_PKTGEN_PORT0_DA1 0x0004 + +#define RTL8367C_REG_PKTGEN_PORT0_DA2 0x0005 + +#define RTL8367C_REG_PKTGEN_PORT0_SA0 0x0006 + +#define RTL8367C_REG_PKTGEN_PORT0_SA1 0x0007 + +#define RTL8367C_REG_PKTGEN_PORT0_SA2 0x0008 + +#define RTL8367C_REG_PKTGEN_PORT0_COUNTER0 0x0009 + +#define RTL8367C_REG_PKTGEN_PORT0_COUNTER1 0x000a +#define RTL8367C_PKTGEN_PORT0_COUNTER1_OFFSET 0 +#define RTL8367C_PKTGEN_PORT0_COUNTER1_MASK 0xFF + +#define RTL8367C_REG_PKTGEN_PORT0_TX_LENGTH 0x000b +#define RTL8367C_PKTGEN_PORT0_TX_LENGTH_OFFSET 0 +#define RTL8367C_PKTGEN_PORT0_TX_LENGTH_MASK 0x3FFF + +#define RTL8367C_REG_PKTGEN_PORT0_TIMER 0x000d +#define RTL8367C_PKTGEN_PORT0_TIMER_TIMER_OFFSET 4 +#define RTL8367C_PKTGEN_PORT0_TIMER_TIMER_MASK 0xF0 +#define RTL8367C_PKTGEN_PORT0_TIMER_RX_DMA_ERR_FLAG_OFFSET 3 +#define RTL8367C_PKTGEN_PORT0_TIMER_RX_DMA_ERR_FLAG_MASK 0x8 + +#define RTL8367C_REG_PORT0_MISC_CFG 0x000e +#define RTL8367C_PORT0_MISC_CFG_SMALL_TAG_IPG_OFFSET 15 +#define RTL8367C_PORT0_MISC_CFG_SMALL_TAG_IPG_MASK 0x8000 +#define RTL8367C_PORT0_MISC_CFG_TX_ITFSP_MODE_OFFSET 14 +#define RTL8367C_PORT0_MISC_CFG_TX_ITFSP_MODE_MASK 0x4000 +#define RTL8367C_PORT0_MISC_CFG_FLOWCTRL_INDEP_OFFSET 13 +#define RTL8367C_PORT0_MISC_CFG_FLOWCTRL_INDEP_MASK 0x2000 +#define RTL8367C_PORT0_MISC_CFG_DOT1Q_REMARK_ENABLE_OFFSET 12 +#define RTL8367C_PORT0_MISC_CFG_DOT1Q_REMARK_ENABLE_MASK 0x1000 +#define RTL8367C_PORT0_MISC_CFG_INGRESSBW_FLOWCTRL_OFFSET 11 +#define RTL8367C_PORT0_MISC_CFG_INGRESSBW_FLOWCTRL_MASK 0x800 +#define RTL8367C_PORT0_MISC_CFG_INGRESSBW_IFG_OFFSET 10 +#define RTL8367C_PORT0_MISC_CFG_INGRESSBW_IFG_MASK 0x400 +#define RTL8367C_PORT0_MISC_CFG_RX_SPC_OFFSET 9 +#define RTL8367C_PORT0_MISC_CFG_RX_SPC_MASK 0x200 +#define RTL8367C_PORT0_MISC_CFG_CRC_SKIP_OFFSET 8 +#define RTL8367C_PORT0_MISC_CFG_CRC_SKIP_MASK 0x100 +#define RTL8367C_PORT0_MISC_CFG_PKTGEN_TX_FIRST_OFFSET 7 +#define RTL8367C_PORT0_MISC_CFG_PKTGEN_TX_FIRST_MASK 0x80 +#define RTL8367C_PORT0_MISC_CFG_MAC_LOOPBACK_OFFSET 6 +#define RTL8367C_PORT0_MISC_CFG_MAC_LOOPBACK_MASK 0x40 +#define RTL8367C_PORT0_MISC_CFG_VLAN_EGRESS_MODE_OFFSET 4 +#define RTL8367C_PORT0_MISC_CFG_VLAN_EGRESS_MODE_MASK 0x30 +#define RTL8367C_PORT0_MISC_CFG_CONGESTION_SUSTAIN_TIME_OFFSET 0 +#define RTL8367C_PORT0_MISC_CFG_CONGESTION_SUSTAIN_TIME_MASK 0xF + +#define RTL8367C_REG_INGRESSBW_PORT0_RATE_CTRL0 0x000f + +#define RTL8367C_REG_INGRESSBW_PORT0_RATE_CTRL1 0x0010 +#define RTL8367C_INGRESSBW_PORT0_RATE_CTRL1_DUMMY_OFFSET 3 +#define RTL8367C_INGRESSBW_PORT0_RATE_CTRL1_DUMMY_MASK 0xFFF8 +#define RTL8367C_INGRESSBW_PORT0_RATE_CTRL1_INGRESSBW_RATE16_OFFSET 0 +#define RTL8367C_INGRESSBW_PORT0_RATE_CTRL1_INGRESSBW_RATE16_MASK 0x7 + +#define RTL8367C_REG_PORT0_FORCE_RATE0 0x0011 + +#define RTL8367C_REG_PORT0_FORCE_RATE1 0x0012 + +#define RTL8367C_REG_PORT0_CURENT_RATE0 0x0013 + +#define RTL8367C_REG_PORT0_CURENT_RATE1 0x0014 + +#define RTL8367C_REG_PORT0_PAGE_COUNTER 0x0015 +#define RTL8367C_PORT0_PAGE_COUNTER_OFFSET 0 +#define RTL8367C_PORT0_PAGE_COUNTER_MASK 0x7F + +#define RTL8367C_REG_PAGEMETER_PORT0_CTRL0 0x0016 + +#define RTL8367C_REG_PAGEMETER_PORT0_CTRL1 0x0017 + +#define RTL8367C_REG_PORT0_EEECFG 0x0018 +#define RTL8367C_PORT0_EEECFG_EEEP_ENABLE_TX_OFFSET 14 +#define RTL8367C_PORT0_EEECFG_EEEP_ENABLE_TX_MASK 0x4000 +#define RTL8367C_PORT0_EEECFG_EEEP_ENABLE_RX_OFFSET 13 +#define RTL8367C_PORT0_EEECFG_EEEP_ENABLE_RX_MASK 0x2000 +#define RTL8367C_PORT0_EEECFG_EEE_FORCE_OFFSET 12 +#define RTL8367C_PORT0_EEECFG_EEE_FORCE_MASK 0x1000 +#define RTL8367C_PORT0_EEECFG_EEE_100M_OFFSET 11 +#define RTL8367C_PORT0_EEECFG_EEE_100M_MASK 0x800 +#define RTL8367C_PORT0_EEECFG_EEE_GIGA_500M_OFFSET 10 +#define RTL8367C_PORT0_EEECFG_EEE_GIGA_500M_MASK 0x400 +#define RTL8367C_PORT0_EEECFG_EEE_TX_OFFSET 9 +#define RTL8367C_PORT0_EEECFG_EEE_TX_MASK 0x200 +#define RTL8367C_PORT0_EEECFG_EEE_RX_OFFSET 8 +#define RTL8367C_PORT0_EEECFG_EEE_RX_MASK 0x100 +#define RTL8367C_PORT0_EEECFG_EEE_DSP_RX_OFFSET 6 +#define RTL8367C_PORT0_EEECFG_EEE_DSP_RX_MASK 0x40 +#define RTL8367C_PORT0_EEECFG_EEE_LPI_OFFSET 5 +#define RTL8367C_PORT0_EEECFG_EEE_LPI_MASK 0x20 +#define RTL8367C_PORT0_EEECFG_EEE_TX_LPI_OFFSET 4 +#define RTL8367C_PORT0_EEECFG_EEE_TX_LPI_MASK 0x10 +#define RTL8367C_PORT0_EEECFG_EEE_RX_LPI_OFFSET 3 +#define RTL8367C_PORT0_EEECFG_EEE_RX_LPI_MASK 0x8 +#define RTL8367C_PORT0_EEECFG_EEE_PAUSE_INDICATOR_OFFSET 2 +#define RTL8367C_PORT0_EEECFG_EEE_PAUSE_INDICATOR_MASK 0x4 +#define RTL8367C_PORT0_EEECFG_EEE_WAKE_REQ_OFFSET 1 +#define RTL8367C_PORT0_EEECFG_EEE_WAKE_REQ_MASK 0x2 +#define RTL8367C_PORT0_EEECFG_EEE_SLEEP_REQ_OFFSET 0 +#define RTL8367C_PORT0_EEECFG_EEE_SLEEP_REQ_MASK 0x1 + +#define RTL8367C_REG_PORT0_EEETXMTR 0x0019 + +#define RTL8367C_REG_PORT0_EEERXMTR 0x001a + +#define RTL8367C_REG_PORT0_EEEPTXMTR 0x001b + +#define RTL8367C_REG_PORT0_EEEPRXMTR 0x001c + +#define RTL8367C_REG_PTP_PORT0_CFG1 0x001e +#define RTL8367C_PTP_PORT0_CFG1_OFFSET 7 +#define RTL8367C_PTP_PORT0_CFG1_MASK 0xFF + +#define RTL8367C_REG_P0_MSIC1 0x001f +#define RTL8367C_P0_MSIC1_OFFSET 0 +#define RTL8367C_P0_MSIC1_MASK 0x1 + +#define RTL8367C_REG_PORT1_CGST_HALF_CFG 0x0020 +#define RTL8367C_PORT1_CGST_HALF_CFG_CONGESTION_TIME_OFFSET 4 +#define RTL8367C_PORT1_CGST_HALF_CFG_CONGESTION_TIME_MASK 0xF0 +#define RTL8367C_PORT1_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_OFFSET 0 +#define RTL8367C_PORT1_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_MASK 0xF + +#define RTL8367C_REG_PKTGEN_PORT1_CTRL 0x0021 +#define RTL8367C_PKTGEN_PORT1_CTRL_STATUS_OFFSET 15 +#define RTL8367C_PKTGEN_PORT1_CTRL_STATUS_MASK 0x8000 +#define RTL8367C_PKTGEN_PORT1_CTRL_PKTGEN_STS_OFFSET 13 +#define RTL8367C_PKTGEN_PORT1_CTRL_PKTGEN_STS_MASK 0x2000 +#define RTL8367C_PKTGEN_PORT1_CTRL_CRC_NO_ERROR_OFFSET 4 +#define RTL8367C_PKTGEN_PORT1_CTRL_CRC_NO_ERROR_MASK 0x10 +#define RTL8367C_PKTGEN_PORT1_CTRL_CMD_START_OFFSET 0 +#define RTL8367C_PKTGEN_PORT1_CTRL_CMD_START_MASK 0x1 + +#define RTL8367C_REG_TX_ERR_CNT_PORT1 0x0022 +#define RTL8367C_TX_ERR_CNT_PORT1_OFFSET 0 +#define RTL8367C_TX_ERR_CNT_PORT1_MASK 0x7 + +#define RTL8367C_REG_PKTGEN_PORT1_DA0 0x0023 + +#define RTL8367C_REG_PKTGEN_PORT1_DA1 0x0024 + +#define RTL8367C_REG_PKTGEN_PORT1_DA2 0x0025 + +#define RTL8367C_REG_PKTGEN_PORT1_SA0 0x0026 + +#define RTL8367C_REG_PKTGEN_PORT1_SA1 0x0027 + +#define RTL8367C_REG_PKTGEN_PORT1_SA2 0x0028 + +#define RTL8367C_REG_PKTGEN_PORT1_COUNTER0 0x0029 + +#define RTL8367C_REG_PKTGEN_PORT1_COUNTER1 0x002a +#define RTL8367C_PKTGEN_PORT1_COUNTER1_OFFSET 0 +#define RTL8367C_PKTGEN_PORT1_COUNTER1_MASK 0xFF + +#define RTL8367C_REG_PKTGEN_PORT1_TX_LENGTH 0x002b +#define RTL8367C_PKTGEN_PORT1_TX_LENGTH_OFFSET 0 +#define RTL8367C_PKTGEN_PORT1_TX_LENGTH_MASK 0x3FFF + +#define RTL8367C_REG_PKTGEN_PORT1_TIMER 0x002d +#define RTL8367C_PKTGEN_PORT1_TIMER_TIMER_OFFSET 4 +#define RTL8367C_PKTGEN_PORT1_TIMER_TIMER_MASK 0xF0 +#define RTL8367C_PKTGEN_PORT1_TIMER_RX_DMA_ERR_FLAG_OFFSET 3 +#define RTL8367C_PKTGEN_PORT1_TIMER_RX_DMA_ERR_FLAG_MASK 0x8 + +#define RTL8367C_REG_PORT1_MISC_CFG 0x002e +#define RTL8367C_PORT1_MISC_CFG_SMALL_TAG_IPG_OFFSET 15 +#define RTL8367C_PORT1_MISC_CFG_SMALL_TAG_IPG_MASK 0x8000 +#define RTL8367C_PORT1_MISC_CFG_TX_ITFSP_MODE_OFFSET 14 +#define RTL8367C_PORT1_MISC_CFG_TX_ITFSP_MODE_MASK 0x4000 +#define RTL8367C_PORT1_MISC_CFG_FLOWCTRL_INDEP_OFFSET 13 +#define RTL8367C_PORT1_MISC_CFG_FLOWCTRL_INDEP_MASK 0x2000 +#define RTL8367C_PORT1_MISC_CFG_DOT1Q_REMARK_ENABLE_OFFSET 12 +#define RTL8367C_PORT1_MISC_CFG_DOT1Q_REMARK_ENABLE_MASK 0x1000 +#define RTL8367C_PORT1_MISC_CFG_INGRESSBW_FLOWCTRL_OFFSET 11 +#define RTL8367C_PORT1_MISC_CFG_INGRESSBW_FLOWCTRL_MASK 0x800 +#define RTL8367C_PORT1_MISC_CFG_INGRESSBW_IFG_OFFSET 10 +#define RTL8367C_PORT1_MISC_CFG_INGRESSBW_IFG_MASK 0x400 +#define RTL8367C_PORT1_MISC_CFG_RX_SPC_OFFSET 9 +#define RTL8367C_PORT1_MISC_CFG_RX_SPC_MASK 0x200 +#define RTL8367C_PORT1_MISC_CFG_CRC_SKIP_OFFSET 8 +#define RTL8367C_PORT1_MISC_CFG_CRC_SKIP_MASK 0x100 +#define RTL8367C_PORT1_MISC_CFG_PKTGEN_TX_FIRST_OFFSET 7 +#define RTL8367C_PORT1_MISC_CFG_PKTGEN_TX_FIRST_MASK 0x80 +#define RTL8367C_PORT1_MISC_CFG_MAC_LOOPBACK_OFFSET 6 +#define RTL8367C_PORT1_MISC_CFG_MAC_LOOPBACK_MASK 0x40 +#define RTL8367C_PORT1_MISC_CFG_VLAN_EGRESS_MODE_OFFSET 4 +#define RTL8367C_PORT1_MISC_CFG_VLAN_EGRESS_MODE_MASK 0x30 +#define RTL8367C_PORT1_MISC_CFG_CONGESTION_SUSTAIN_TIME_OFFSET 0 +#define RTL8367C_PORT1_MISC_CFG_CONGESTION_SUSTAIN_TIME_MASK 0xF + +#define RTL8367C_REG_INGRESSBW_PORT1_RATE_CTRL0 0x002f + +#define RTL8367C_REG_INGRESSBW_PORT1_RATE_CTRL1 0x0030 +#define RTL8367C_INGRESSBW_PORT1_RATE_CTRL1_DUMMY_OFFSET 3 +#define RTL8367C_INGRESSBW_PORT1_RATE_CTRL1_DUMMY_MASK 0xFFF8 +#define RTL8367C_INGRESSBW_PORT1_RATE_CTRL1_INGRESSBW_RATE16_OFFSET 0 +#define RTL8367C_INGRESSBW_PORT1_RATE_CTRL1_INGRESSBW_RATE16_MASK 0x7 + +#define RTL8367C_REG_PORT1_FORCE_RATE0 0x0031 + +#define RTL8367C_REG_PORT1_FORCE_RATE1 0x0032 + +#define RTL8367C_REG_PORT1_CURENT_RATE0 0x0033 + +#define RTL8367C_REG_PORT1_CURENT_RATE1 0x0034 + +#define RTL8367C_REG_PORT1_PAGE_COUNTER 0x0035 +#define RTL8367C_PORT1_PAGE_COUNTER_OFFSET 0 +#define RTL8367C_PORT1_PAGE_COUNTER_MASK 0x7F + +#define RTL8367C_REG_PAGEMETER_PORT1_CTRL0 0x0036 + +#define RTL8367C_REG_PAGEMETER_PORT1_CTRL1 0x0037 + +#define RTL8367C_REG_PORT1_EEECFG 0x0038 +#define RTL8367C_PORT1_EEECFG_EEEP_ENABLE_TX_OFFSET 14 +#define RTL8367C_PORT1_EEECFG_EEEP_ENABLE_TX_MASK 0x4000 +#define RTL8367C_PORT1_EEECFG_EEEP_ENABLE_RX_OFFSET 13 +#define RTL8367C_PORT1_EEECFG_EEEP_ENABLE_RX_MASK 0x2000 +#define RTL8367C_PORT1_EEECFG_EEE_FORCE_OFFSET 12 +#define RTL8367C_PORT1_EEECFG_EEE_FORCE_MASK 0x1000 +#define RTL8367C_PORT1_EEECFG_EEE_100M_OFFSET 11 +#define RTL8367C_PORT1_EEECFG_EEE_100M_MASK 0x800 +#define RTL8367C_PORT1_EEECFG_EEE_GIGA_500M_OFFSET 10 +#define RTL8367C_PORT1_EEECFG_EEE_GIGA_500M_MASK 0x400 +#define RTL8367C_PORT1_EEECFG_EEE_TX_OFFSET 9 +#define RTL8367C_PORT1_EEECFG_EEE_TX_MASK 0x200 +#define RTL8367C_PORT1_EEECFG_EEE_RX_OFFSET 8 +#define RTL8367C_PORT1_EEECFG_EEE_RX_MASK 0x100 +#define RTL8367C_PORT1_EEECFG_EEE_DSP_RX_OFFSET 6 +#define RTL8367C_PORT1_EEECFG_EEE_DSP_RX_MASK 0x40 +#define RTL8367C_PORT1_EEECFG_EEE_LPI_OFFSET 5 +#define RTL8367C_PORT1_EEECFG_EEE_LPI_MASK 0x20 +#define RTL8367C_PORT1_EEECFG_EEE_TX_LPI_OFFSET 4 +#define RTL8367C_PORT1_EEECFG_EEE_TX_LPI_MASK 0x10 +#define RTL8367C_PORT1_EEECFG_EEE_RX_LPI_OFFSET 3 +#define RTL8367C_PORT1_EEECFG_EEE_RX_LPI_MASK 0x8 +#define RTL8367C_PORT1_EEECFG_EEE_PAUSE_INDICATOR_OFFSET 2 +#define RTL8367C_PORT1_EEECFG_EEE_PAUSE_INDICATOR_MASK 0x4 +#define RTL8367C_PORT1_EEECFG_EEE_WAKE_REQ_OFFSET 1 +#define RTL8367C_PORT1_EEECFG_EEE_WAKE_REQ_MASK 0x2 +#define RTL8367C_PORT1_EEECFG_EEE_SLEEP_REQ_OFFSET 0 +#define RTL8367C_PORT1_EEECFG_EEE_SLEEP_REQ_MASK 0x1 + +#define RTL8367C_REG_PORT1_EEETXMTR 0x0039 + +#define RTL8367C_REG_PORT1_EEERXMTR 0x003a + +#define RTL8367C_REG_PORT1_EEEPTXMTR 0x003b + +#define RTL8367C_REG_PORT1_EEEPRXMTR 0x003c + +#define RTL8367C_REG_PTP_PORT1_CFG1 0x003e +#define RTL8367C_PTP_PORT1_CFG1_OFFSET 7 +#define RTL8367C_PTP_PORT1_CFG1_MASK 0xFF + +#define RTL8367C_REG_P1_MSIC1 0x003f +#define RTL8367C_P1_MSIC1_OFFSET 0 +#define RTL8367C_P1_MSIC1_MASK 0x1 + +#define RTL8367C_REG_PORT2_CGST_HALF_CFG 0x0040 +#define RTL8367C_PORT2_CGST_HALF_CFG_CONGESTION_TIME_OFFSET 4 +#define RTL8367C_PORT2_CGST_HALF_CFG_CONGESTION_TIME_MASK 0xF0 +#define RTL8367C_PORT2_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_OFFSET 0 +#define RTL8367C_PORT2_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_MASK 0xF + +#define RTL8367C_REG_PKTGEN_PORT2_CTRL 0x0041 +#define RTL8367C_PKTGEN_PORT2_CTRL_STATUS_OFFSET 15 +#define RTL8367C_PKTGEN_PORT2_CTRL_STATUS_MASK 0x8000 +#define RTL8367C_PKTGEN_PORT2_CTRL_PKTGEN_STS_OFFSET 13 +#define RTL8367C_PKTGEN_PORT2_CTRL_PKTGEN_STS_MASK 0x2000 +#define RTL8367C_PKTGEN_PORT2_CTRL_CRC_NO_ERROR_OFFSET 4 +#define RTL8367C_PKTGEN_PORT2_CTRL_CRC_NO_ERROR_MASK 0x10 +#define RTL8367C_PKTGEN_PORT2_CTRL_CMD_START_OFFSET 0 +#define RTL8367C_PKTGEN_PORT2_CTRL_CMD_START_MASK 0x1 + +#define RTL8367C_REG_TX_ERR_CNT_PORT2 0x0042 +#define RTL8367C_TX_ERR_CNT_PORT2_OFFSET 0 +#define RTL8367C_TX_ERR_CNT_PORT2_MASK 0x7 + +#define RTL8367C_REG_PKTGEN_PORT2_DA0 0x0043 + +#define RTL8367C_REG_PKTGEN_PORT2_DA1 0x0044 + +#define RTL8367C_REG_PKTGEN_PORT2_DA2 0x0045 + +#define RTL8367C_REG_PKTGEN_PORT2_SA0 0x0046 + +#define RTL8367C_REG_PKTGEN_PORT2_SA1 0x0047 + +#define RTL8367C_REG_PKTGEN_PORT2_SA2 0x0048 + +#define RTL8367C_REG_PKTGEN_PORT2_COUNTER0 0x0049 + +#define RTL8367C_REG_PKTGEN_PORT2_COUNTER1 0x004a +#define RTL8367C_PKTGEN_PORT2_COUNTER1_OFFSET 0 +#define RTL8367C_PKTGEN_PORT2_COUNTER1_MASK 0xFF + +#define RTL8367C_REG_PKTGEN_PORT2_TX_LENGTH 0x004b +#define RTL8367C_PKTGEN_PORT2_TX_LENGTH_OFFSET 0 +#define RTL8367C_PKTGEN_PORT2_TX_LENGTH_MASK 0x3FFF + +#define RTL8367C_REG_PKTGEN_PORT2_TIMER 0x004d +#define RTL8367C_PKTGEN_PORT2_TIMER_TIMER_OFFSET 4 +#define RTL8367C_PKTGEN_PORT2_TIMER_TIMER_MASK 0xF0 +#define RTL8367C_PKTGEN_PORT2_TIMER_RX_DMA_ERR_FLAG_OFFSET 3 +#define RTL8367C_PKTGEN_PORT2_TIMER_RX_DMA_ERR_FLAG_MASK 0x8 + +#define RTL8367C_REG_PORT2_MISC_CFG 0x004e +#define RTL8367C_PORT2_MISC_CFG_SMALL_TAG_IPG_OFFSET 15 +#define RTL8367C_PORT2_MISC_CFG_SMALL_TAG_IPG_MASK 0x8000 +#define RTL8367C_PORT2_MISC_CFG_TX_ITFSP_MODE_OFFSET 14 +#define RTL8367C_PORT2_MISC_CFG_TX_ITFSP_MODE_MASK 0x4000 +#define RTL8367C_PORT2_MISC_CFG_FLOWCTRL_INDEP_OFFSET 13 +#define RTL8367C_PORT2_MISC_CFG_FLOWCTRL_INDEP_MASK 0x2000 +#define RTL8367C_PORT2_MISC_CFG_DOT1Q_REMARK_ENABLE_OFFSET 12 +#define RTL8367C_PORT2_MISC_CFG_DOT1Q_REMARK_ENABLE_MASK 0x1000 +#define RTL8367C_PORT2_MISC_CFG_INGRESSBW_FLOWCTRL_OFFSET 11 +#define RTL8367C_PORT2_MISC_CFG_INGRESSBW_FLOWCTRL_MASK 0x800 +#define RTL8367C_PORT2_MISC_CFG_INGRESSBW_IFG_OFFSET 10 +#define RTL8367C_PORT2_MISC_CFG_INGRESSBW_IFG_MASK 0x400 +#define RTL8367C_PORT2_MISC_CFG_RX_SPC_OFFSET 9 +#define RTL8367C_PORT2_MISC_CFG_RX_SPC_MASK 0x200 +#define RTL8367C_PORT2_MISC_CFG_CRC_SKIP_OFFSET 8 +#define RTL8367C_PORT2_MISC_CFG_CRC_SKIP_MASK 0x100 +#define RTL8367C_PORT2_MISC_CFG_PKTGEN_TX_FIRST_OFFSET 7 +#define RTL8367C_PORT2_MISC_CFG_PKTGEN_TX_FIRST_MASK 0x80 +#define RTL8367C_PORT2_MISC_CFG_MAC_LOOPBACK_OFFSET 6 +#define RTL8367C_PORT2_MISC_CFG_MAC_LOOPBACK_MASK 0x40 +#define RTL8367C_PORT2_MISC_CFG_VLAN_EGRESS_MODE_OFFSET 4 +#define RTL8367C_PORT2_MISC_CFG_VLAN_EGRESS_MODE_MASK 0x30 +#define RTL8367C_PORT2_MISC_CFG_CONGESTION_SUSTAIN_TIME_OFFSET 0 +#define RTL8367C_PORT2_MISC_CFG_CONGESTION_SUSTAIN_TIME_MASK 0xF + +#define RTL8367C_REG_INGRESSBW_PORT2_RATE_CTRL0 0x004f + +#define RTL8367C_REG_INGRESSBW_PORT2_RATE_CTRL1 0x0050 +#define RTL8367C_INGRESSBW_PORT2_RATE_CTRL1_DUMMY_OFFSET 3 +#define RTL8367C_INGRESSBW_PORT2_RATE_CTRL1_DUMMY_MASK 0xFFF8 +#define RTL8367C_INGRESSBW_PORT2_RATE_CTRL1_INGRESSBW_RATE16_OFFSET 0 +#define RTL8367C_INGRESSBW_PORT2_RATE_CTRL1_INGRESSBW_RATE16_MASK 0x7 + +#define RTL8367C_REG_PORT2_FORCE_RATE0 0x0051 + +#define RTL8367C_REG_PORT2_FORCE_RATE1 0x0052 + +#define RTL8367C_REG_PORT2_CURENT_RATE0 0x0053 + +#define RTL8367C_REG_PORT2_CURENT_RATE1 0x0054 + +#define RTL8367C_REG_PORT2_PAGE_COUNTER 0x0055 +#define RTL8367C_PORT2_PAGE_COUNTER_OFFSET 0 +#define RTL8367C_PORT2_PAGE_COUNTER_MASK 0x7F + +#define RTL8367C_REG_PAGEMETER_PORT2_CTRL0 0x0056 + +#define RTL8367C_REG_PAGEMETER_PORT2_CTRL1 0x0057 + +#define RTL8367C_REG_PORT2_EEECFG 0x0058 +#define RTL8367C_PORT2_EEECFG_EEEP_ENABLE_TX_OFFSET 14 +#define RTL8367C_PORT2_EEECFG_EEEP_ENABLE_TX_MASK 0x4000 +#define RTL8367C_PORT2_EEECFG_EEEP_ENABLE_RX_OFFSET 13 +#define RTL8367C_PORT2_EEECFG_EEEP_ENABLE_RX_MASK 0x2000 +#define RTL8367C_PORT2_EEECFG_EEE_FORCE_OFFSET 12 +#define RTL8367C_PORT2_EEECFG_EEE_FORCE_MASK 0x1000 +#define RTL8367C_PORT2_EEECFG_EEE_100M_OFFSET 11 +#define RTL8367C_PORT2_EEECFG_EEE_100M_MASK 0x800 +#define RTL8367C_PORT2_EEECFG_EEE_GIGA_500M_OFFSET 10 +#define RTL8367C_PORT2_EEECFG_EEE_GIGA_500M_MASK 0x400 +#define RTL8367C_PORT2_EEECFG_EEE_TX_OFFSET 9 +#define RTL8367C_PORT2_EEECFG_EEE_TX_MASK 0x200 +#define RTL8367C_PORT2_EEECFG_EEE_RX_OFFSET 8 +#define RTL8367C_PORT2_EEECFG_EEE_RX_MASK 0x100 +#define RTL8367C_PORT2_EEECFG_EEE_DSP_RX_OFFSET 6 +#define RTL8367C_PORT2_EEECFG_EEE_DSP_RX_MASK 0x40 +#define RTL8367C_PORT2_EEECFG_EEE_LPI_OFFSET 5 +#define RTL8367C_PORT2_EEECFG_EEE_LPI_MASK 0x20 +#define RTL8367C_PORT2_EEECFG_EEE_TX_LPI_OFFSET 4 +#define RTL8367C_PORT2_EEECFG_EEE_TX_LPI_MASK 0x10 +#define RTL8367C_PORT2_EEECFG_EEE_RX_LPI_OFFSET 3 +#define RTL8367C_PORT2_EEECFG_EEE_RX_LPI_MASK 0x8 +#define RTL8367C_PORT2_EEECFG_EEE_PAUSE_INDICATOR_OFFSET 2 +#define RTL8367C_PORT2_EEECFG_EEE_PAUSE_INDICATOR_MASK 0x4 +#define RTL8367C_PORT2_EEECFG_EEE_WAKE_REQ_OFFSET 1 +#define RTL8367C_PORT2_EEECFG_EEE_WAKE_REQ_MASK 0x2 +#define RTL8367C_PORT2_EEECFG_EEE_SLEEP_REQ_OFFSET 0 +#define RTL8367C_PORT2_EEECFG_EEE_SLEEP_REQ_MASK 0x1 + +#define RTL8367C_REG_PORT2_EEETXMTR 0x0059 + +#define RTL8367C_REG_PORT2_EEERXMTR 0x005a + +#define RTL8367C_REG_PORT2_EEEPTXMTR 0x005b + +#define RTL8367C_REG_PORT2_EEEPRXMTR 0x005c + +#define RTL8367C_REG_PTP_PORT2_CFG1 0x005e +#define RTL8367C_PTP_PORT2_CFG1_OFFSET 7 +#define RTL8367C_PTP_PORT2_CFG1_MASK 0xFF + +#define RTL8367C_REG_P2_MSIC1 0x005f +#define RTL8367C_P2_MSIC1_OFFSET 0 +#define RTL8367C_P2_MSIC1_MASK 0x1 + +#define RTL8367C_REG_PORT3_CGST_HALF_CFG 0x0060 +#define RTL8367C_PORT3_CGST_HALF_CFG_CONGESTION_TIME_OFFSET 4 +#define RTL8367C_PORT3_CGST_HALF_CFG_CONGESTION_TIME_MASK 0xF0 +#define RTL8367C_PORT3_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_OFFSET 0 +#define RTL8367C_PORT3_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_MASK 0xF + +#define RTL8367C_REG_PKTGEN_PORT3_CTRL 0x0061 +#define RTL8367C_PKTGEN_PORT3_CTRL_STATUS_OFFSET 15 +#define RTL8367C_PKTGEN_PORT3_CTRL_STATUS_MASK 0x8000 +#define RTL8367C_PKTGEN_PORT3_CTRL_PKTGEN_STS_OFFSET 13 +#define RTL8367C_PKTGEN_PORT3_CTRL_PKTGEN_STS_MASK 0x2000 +#define RTL8367C_PKTGEN_PORT3_CTRL_CRC_NO_ERROR_OFFSET 4 +#define RTL8367C_PKTGEN_PORT3_CTRL_CRC_NO_ERROR_MASK 0x10 +#define RTL8367C_PKTGEN_PORT3_CTRL_CMD_START_OFFSET 0 +#define RTL8367C_PKTGEN_PORT3_CTRL_CMD_START_MASK 0x1 + +#define RTL8367C_REG_TX_ERR_CNT_PORT3 0x0062 +#define RTL8367C_TX_ERR_CNT_PORT3_OFFSET 0 +#define RTL8367C_TX_ERR_CNT_PORT3_MASK 0x7 + +#define RTL8367C_REG_PKTGEN_PORT3_DA0 0x0063 + +#define RTL8367C_REG_PKTGEN_PORT3_DA1 0x0064 + +#define RTL8367C_REG_PKTGEN_PORT3_DA2 0x0065 + +#define RTL8367C_REG_PKTGEN_PORT3_SA0 0x0066 + +#define RTL8367C_REG_PKTGEN_PORT3_SA1 0x0067 + +#define RTL8367C_REG_PKTGEN_PORT3_SA2 0x0068 + +#define RTL8367C_REG_PKTGEN_PORT3_COUNTER0 0x0069 + +#define RTL8367C_REG_PKTGEN_PORT3_COUNTER1 0x006a +#define RTL8367C_PKTGEN_PORT3_COUNTER1_OFFSET 0 +#define RTL8367C_PKTGEN_PORT3_COUNTER1_MASK 0xFF + +#define RTL8367C_REG_PKTGEN_PORT3_TX_LENGTH 0x006b +#define RTL8367C_PKTGEN_PORT3_TX_LENGTH_OFFSET 0 +#define RTL8367C_PKTGEN_PORT3_TX_LENGTH_MASK 0x3FFF + +#define RTL8367C_REG_PKTGEN_PORT3_TIMER 0x006d +#define RTL8367C_PKTGEN_PORT3_TIMER_TIMER_OFFSET 4 +#define RTL8367C_PKTGEN_PORT3_TIMER_TIMER_MASK 0xF0 +#define RTL8367C_PKTGEN_PORT3_TIMER_RX_DMA_ERR_FLAG_OFFSET 3 +#define RTL8367C_PKTGEN_PORT3_TIMER_RX_DMA_ERR_FLAG_MASK 0x8 + +#define RTL8367C_REG_PORT3_MISC_CFG 0x006e +#define RTL8367C_PORT3_MISC_CFG_SMALL_TAG_IPG_OFFSET 15 +#define RTL8367C_PORT3_MISC_CFG_SMALL_TAG_IPG_MASK 0x8000 +#define RTL8367C_PORT3_MISC_CFG_TX_ITFSP_MODE_OFFSET 14 +#define RTL8367C_PORT3_MISC_CFG_TX_ITFSP_MODE_MASK 0x4000 +#define RTL8367C_PORT3_MISC_CFG_FLOWCTRL_INDEP_OFFSET 13 +#define RTL8367C_PORT3_MISC_CFG_FLOWCTRL_INDEP_MASK 0x2000 +#define RTL8367C_PORT3_MISC_CFG_DOT1Q_REMARK_ENABLE_OFFSET 12 +#define RTL8367C_PORT3_MISC_CFG_DOT1Q_REMARK_ENABLE_MASK 0x1000 +#define RTL8367C_PORT3_MISC_CFG_INGRESSBW_FLOWCTRL_OFFSET 11 +#define RTL8367C_PORT3_MISC_CFG_INGRESSBW_FLOWCTRL_MASK 0x800 +#define RTL8367C_PORT3_MISC_CFG_INGRESSBW_IFG_OFFSET 10 +#define RTL8367C_PORT3_MISC_CFG_INGRESSBW_IFG_MASK 0x400 +#define RTL8367C_PORT3_MISC_CFG_RX_SPC_OFFSET 9 +#define RTL8367C_PORT3_MISC_CFG_RX_SPC_MASK 0x200 +#define RTL8367C_PORT3_MISC_CFG_CRC_SKIP_OFFSET 8 +#define RTL8367C_PORT3_MISC_CFG_CRC_SKIP_MASK 0x100 +#define RTL8367C_PORT3_MISC_CFG_PKTGEN_TX_FIRST_OFFSET 7 +#define RTL8367C_PORT3_MISC_CFG_PKTGEN_TX_FIRST_MASK 0x80 +#define RTL8367C_PORT3_MISC_CFG_MAC_LOOPBACK_OFFSET 6 +#define RTL8367C_PORT3_MISC_CFG_MAC_LOOPBACK_MASK 0x40 +#define RTL8367C_PORT3_MISC_CFG_VLAN_EGRESS_MODE_OFFSET 4 +#define RTL8367C_PORT3_MISC_CFG_VLAN_EGRESS_MODE_MASK 0x30 +#define RTL8367C_PORT3_MISC_CFG_CONGESTION_SUSTAIN_TIME_OFFSET 0 +#define RTL8367C_PORT3_MISC_CFG_CONGESTION_SUSTAIN_TIME_MASK 0xF + +#define RTL8367C_REG_INGRESSBW_PORT3_RATE_CTRL0 0x006f + +#define RTL8367C_REG_INGRESSBW_PORT3_RATE_CTRL1 0x0070 +#define RTL8367C_INGRESSBW_PORT3_RATE_CTRL1_DUMMY_OFFSET 3 +#define RTL8367C_INGRESSBW_PORT3_RATE_CTRL1_DUMMY_MASK 0xFFF8 +#define RTL8367C_INGRESSBW_PORT3_RATE_CTRL1_INGRESSBW_RATE16_OFFSET 0 +#define RTL8367C_INGRESSBW_PORT3_RATE_CTRL1_INGRESSBW_RATE16_MASK 0x7 + +#define RTL8367C_REG_PORT3_FORCE_RATE0 0x0071 + +#define RTL8367C_REG_PORT3_FORCE_RATE1 0x0072 + +#define RTL8367C_REG_PORT3_CURENT_RATE0 0x0073 + +#define RTL8367C_REG_PORT3_CURENT_RATE1 0x0074 + +#define RTL8367C_REG_PORT3_PAGE_COUNTER 0x0075 +#define RTL8367C_PORT3_PAGE_COUNTER_OFFSET 0 +#define RTL8367C_PORT3_PAGE_COUNTER_MASK 0x7F + +#define RTL8367C_REG_PAGEMETER_PORT3_CTRL0 0x0076 + +#define RTL8367C_REG_PAGEMETER_PORT3_CTRL1 0x0077 + +#define RTL8367C_REG_PORT3_EEECFG 0x0078 +#define RTL8367C_PORT3_EEECFG_EEEP_ENABLE_TX_OFFSET 14 +#define RTL8367C_PORT3_EEECFG_EEEP_ENABLE_TX_MASK 0x4000 +#define RTL8367C_PORT3_EEECFG_EEEP_ENABLE_RX_OFFSET 13 +#define RTL8367C_PORT3_EEECFG_EEEP_ENABLE_RX_MASK 0x2000 +#define RTL8367C_PORT3_EEECFG_EEE_FORCE_OFFSET 12 +#define RTL8367C_PORT3_EEECFG_EEE_FORCE_MASK 0x1000 +#define RTL8367C_PORT3_EEECFG_EEE_100M_OFFSET 11 +#define RTL8367C_PORT3_EEECFG_EEE_100M_MASK 0x800 +#define RTL8367C_PORT3_EEECFG_EEE_GIGA_500M_OFFSET 10 +#define RTL8367C_PORT3_EEECFG_EEE_GIGA_500M_MASK 0x400 +#define RTL8367C_PORT3_EEECFG_EEE_TX_OFFSET 9 +#define RTL8367C_PORT3_EEECFG_EEE_TX_MASK 0x200 +#define RTL8367C_PORT3_EEECFG_EEE_RX_OFFSET 8 +#define RTL8367C_PORT3_EEECFG_EEE_RX_MASK 0x100 +#define RTL8367C_PORT3_EEECFG_EEE_DSP_RX_OFFSET 6 +#define RTL8367C_PORT3_EEECFG_EEE_DSP_RX_MASK 0x40 +#define RTL8367C_PORT3_EEECFG_EEE_LPI_OFFSET 5 +#define RTL8367C_PORT3_EEECFG_EEE_LPI_MASK 0x20 +#define RTL8367C_PORT3_EEECFG_EEE_TX_LPI_OFFSET 4 +#define RTL8367C_PORT3_EEECFG_EEE_TX_LPI_MASK 0x10 +#define RTL8367C_PORT3_EEECFG_EEE_RX_LPI_OFFSET 3 +#define RTL8367C_PORT3_EEECFG_EEE_RX_LPI_MASK 0x8 +#define RTL8367C_PORT3_EEECFG_EEE_PAUSE_INDICATOR_OFFSET 2 +#define RTL8367C_PORT3_EEECFG_EEE_PAUSE_INDICATOR_MASK 0x4 +#define RTL8367C_PORT3_EEECFG_EEE_WAKE_REQ_OFFSET 1 +#define RTL8367C_PORT3_EEECFG_EEE_WAKE_REQ_MASK 0x2 +#define RTL8367C_PORT3_EEECFG_EEE_SLEEP_REQ_OFFSET 0 +#define RTL8367C_PORT3_EEECFG_EEE_SLEEP_REQ_MASK 0x1 + +#define RTL8367C_REG_PORT3_EEETXMTR 0x0079 + +#define RTL8367C_REG_PORT3_EEERXMTR 0x007a + +#define RTL8367C_REG_PORT3_EEEPTXMTR 0x007b + +#define RTL8367C_REG_PORT3_EEEPRXMTR 0x007c + +#define RTL8367C_REG_PTP_PORT3_CFG1 0x007e +#define RTL8367C_PTP_PORT3_CFG1_OFFSET 7 +#define RTL8367C_PTP_PORT3_CFG1_MASK 0xFF + +#define RTL8367C_REG_P3_MSIC1 0x007f +#define RTL8367C_P3_MSIC1_OFFSET 0 +#define RTL8367C_P3_MSIC1_MASK 0x1 + +#define RTL8367C_REG_PORT4_CGST_HALF_CFG 0x0080 +#define RTL8367C_PORT4_CGST_HALF_CFG_CONGESTION_TIME_OFFSET 4 +#define RTL8367C_PORT4_CGST_HALF_CFG_CONGESTION_TIME_MASK 0xF0 +#define RTL8367C_PORT4_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_OFFSET 0 +#define RTL8367C_PORT4_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_MASK 0xF + +#define RTL8367C_REG_PKTGEN_PORT4_CTRL 0x0081 +#define RTL8367C_PKTGEN_PORT4_CTRL_STATUS_OFFSET 15 +#define RTL8367C_PKTGEN_PORT4_CTRL_STATUS_MASK 0x8000 +#define RTL8367C_PKTGEN_PORT4_CTRL_PKTGEN_STS_OFFSET 13 +#define RTL8367C_PKTGEN_PORT4_CTRL_PKTGEN_STS_MASK 0x2000 +#define RTL8367C_PKTGEN_PORT4_CTRL_CRC_NO_ERROR_OFFSET 4 +#define RTL8367C_PKTGEN_PORT4_CTRL_CRC_NO_ERROR_MASK 0x10 +#define RTL8367C_PKTGEN_PORT4_CTRL_CMD_START_OFFSET 0 +#define RTL8367C_PKTGEN_PORT4_CTRL_CMD_START_MASK 0x1 + +#define RTL8367C_REG_TX_ERR_CNT_PORT4 0x0082 +#define RTL8367C_TX_ERR_CNT_PORT4_OFFSET 0 +#define RTL8367C_TX_ERR_CNT_PORT4_MASK 0x7 + +#define RTL8367C_REG_PKTGEN_PORT4_DA0 0x0083 + +#define RTL8367C_REG_PKTGEN_PORT4_DA1 0x0084 + +#define RTL8367C_REG_PKTGEN_PORT4_DA2 0x0085 + +#define RTL8367C_REG_PKTGEN_PORT4_SA0 0x0086 + +#define RTL8367C_REG_PKTGEN_PORT4_SA1 0x0087 + +#define RTL8367C_REG_PKTGEN_PORT4_SA2 0x0088 + +#define RTL8367C_REG_PKTGEN_PORT4_COUNTER0 0x0089 + +#define RTL8367C_REG_PKTGEN_PORT4_COUNTER1 0x008a +#define RTL8367C_PKTGEN_PORT4_COUNTER1_OFFSET 0 +#define RTL8367C_PKTGEN_PORT4_COUNTER1_MASK 0xFF + +#define RTL8367C_REG_PKTGEN_PORT4_TX_LENGTH 0x008b +#define RTL8367C_PKTGEN_PORT4_TX_LENGTH_OFFSET 0 +#define RTL8367C_PKTGEN_PORT4_TX_LENGTH_MASK 0x3FFF + +#define RTL8367C_REG_PKTGEN_PORT4_TIMER 0x008d +#define RTL8367C_PKTGEN_PORT4_TIMER_TIMER_OFFSET 4 +#define RTL8367C_PKTGEN_PORT4_TIMER_TIMER_MASK 0xF0 +#define RTL8367C_PKTGEN_PORT4_TIMER_RX_DMA_ERR_FLAG_OFFSET 3 +#define RTL8367C_PKTGEN_PORT4_TIMER_RX_DMA_ERR_FLAG_MASK 0x8 + +#define RTL8367C_REG_PORT4_MISC_CFG 0x008e +#define RTL8367C_PORT4_MISC_CFG_SMALL_TAG_IPG_OFFSET 15 +#define RTL8367C_PORT4_MISC_CFG_SMALL_TAG_IPG_MASK 0x8000 +#define RTL8367C_PORT4_MISC_CFG_TX_ITFSP_MODE_OFFSET 14 +#define RTL8367C_PORT4_MISC_CFG_TX_ITFSP_MODE_MASK 0x4000 +#define RTL8367C_PORT4_MISC_CFG_FLOWCTRL_INDEP_OFFSET 13 +#define RTL8367C_PORT4_MISC_CFG_FLOWCTRL_INDEP_MASK 0x2000 +#define RTL8367C_PORT4_MISC_CFG_DOT1Q_REMARK_ENABLE_OFFSET 12 +#define RTL8367C_PORT4_MISC_CFG_DOT1Q_REMARK_ENABLE_MASK 0x1000 +#define RTL8367C_PORT4_MISC_CFG_INGRESSBW_FLOWCTRL_OFFSET 11 +#define RTL8367C_PORT4_MISC_CFG_INGRESSBW_FLOWCTRL_MASK 0x800 +#define RTL8367C_PORT4_MISC_CFG_INGRESSBW_IFG_OFFSET 10 +#define RTL8367C_PORT4_MISC_CFG_INGRESSBW_IFG_MASK 0x400 +#define RTL8367C_PORT4_MISC_CFG_RX_SPC_OFFSET 9 +#define RTL8367C_PORT4_MISC_CFG_RX_SPC_MASK 0x200 +#define RTL8367C_PORT4_MISC_CFG_CRC_SKIP_OFFSET 8 +#define RTL8367C_PORT4_MISC_CFG_CRC_SKIP_MASK 0x100 +#define RTL8367C_PORT4_MISC_CFG_PKTGEN_TX_FIRST_OFFSET 7 +#define RTL8367C_PORT4_MISC_CFG_PKTGEN_TX_FIRST_MASK 0x80 +#define RTL8367C_PORT4_MISC_CFG_MAC_LOOPBACK_OFFSET 6 +#define RTL8367C_PORT4_MISC_CFG_MAC_LOOPBACK_MASK 0x40 +#define RTL8367C_PORT4_MISC_CFG_VLAN_EGRESS_MODE_OFFSET 4 +#define RTL8367C_PORT4_MISC_CFG_VLAN_EGRESS_MODE_MASK 0x30 +#define RTL8367C_PORT4_MISC_CFG_CONGESTION_SUSTAIN_TIME_OFFSET 0 +#define RTL8367C_PORT4_MISC_CFG_CONGESTION_SUSTAIN_TIME_MASK 0xF + +#define RTL8367C_REG_INGRESSBW_PORT4_RATE_CTRL0 0x008f + +#define RTL8367C_REG_INGRESSBW_PORT4_RATE_CTRL1 0x0090 +#define RTL8367C_INGRESSBW_PORT4_RATE_CTRL1_DUMMY_OFFSET 3 +#define RTL8367C_INGRESSBW_PORT4_RATE_CTRL1_DUMMY_MASK 0xFFF8 +#define RTL8367C_INGRESSBW_PORT4_RATE_CTRL1_INGRESSBW_RATE16_OFFSET 0 +#define RTL8367C_INGRESSBW_PORT4_RATE_CTRL1_INGRESSBW_RATE16_MASK 0x7 + +#define RTL8367C_REG_PORT4_FORCE_RATE0 0x0091 + +#define RTL8367C_REG_PORT4_FORCE_RATE1 0x0092 + +#define RTL8367C_REG_PORT4_CURENT_RATE0 0x0093 + +#define RTL8367C_REG_PORT4_CURENT_RATE1 0x0094 + +#define RTL8367C_REG_PORT4_PAGE_COUNTER 0x0095 +#define RTL8367C_PORT4_PAGE_COUNTER_OFFSET 0 +#define RTL8367C_PORT4_PAGE_COUNTER_MASK 0x7F + +#define RTL8367C_REG_PAGEMETER_PORT4_CTRL0 0x0096 + +#define RTL8367C_REG_PAGEMETER_PORT4_CTRL1 0x0097 + +#define RTL8367C_REG_PORT4_EEECFG 0x0098 +#define RTL8367C_PORT4_EEECFG_EEEP_ENABLE_TX_OFFSET 14 +#define RTL8367C_PORT4_EEECFG_EEEP_ENABLE_TX_MASK 0x4000 +#define RTL8367C_PORT4_EEECFG_EEEP_ENABLE_RX_OFFSET 13 +#define RTL8367C_PORT4_EEECFG_EEEP_ENABLE_RX_MASK 0x2000 +#define RTL8367C_PORT4_EEECFG_EEE_FORCE_OFFSET 12 +#define RTL8367C_PORT4_EEECFG_EEE_FORCE_MASK 0x1000 +#define RTL8367C_PORT4_EEECFG_EEE_100M_OFFSET 11 +#define RTL8367C_PORT4_EEECFG_EEE_100M_MASK 0x800 +#define RTL8367C_PORT4_EEECFG_EEE_GIGA_500M_OFFSET 10 +#define RTL8367C_PORT4_EEECFG_EEE_GIGA_500M_MASK 0x400 +#define RTL8367C_PORT4_EEECFG_EEE_TX_OFFSET 9 +#define RTL8367C_PORT4_EEECFG_EEE_TX_MASK 0x200 +#define RTL8367C_PORT4_EEECFG_EEE_RX_OFFSET 8 +#define RTL8367C_PORT4_EEECFG_EEE_RX_MASK 0x100 +#define RTL8367C_PORT4_EEECFG_EEE_DSP_RX_OFFSET 6 +#define RTL8367C_PORT4_EEECFG_EEE_DSP_RX_MASK 0x40 +#define RTL8367C_PORT4_EEECFG_EEE_LPI_OFFSET 5 +#define RTL8367C_PORT4_EEECFG_EEE_LPI_MASK 0x20 +#define RTL8367C_PORT4_EEECFG_EEE_TX_LPI_OFFSET 4 +#define RTL8367C_PORT4_EEECFG_EEE_TX_LPI_MASK 0x10 +#define RTL8367C_PORT4_EEECFG_EEE_RX_LPI_OFFSET 3 +#define RTL8367C_PORT4_EEECFG_EEE_RX_LPI_MASK 0x8 +#define RTL8367C_PORT4_EEECFG_EEE_PAUSE_INDICATOR_OFFSET 2 +#define RTL8367C_PORT4_EEECFG_EEE_PAUSE_INDICATOR_MASK 0x4 +#define RTL8367C_PORT4_EEECFG_EEE_WAKE_REQ_OFFSET 1 +#define RTL8367C_PORT4_EEECFG_EEE_WAKE_REQ_MASK 0x2 +#define RTL8367C_PORT4_EEECFG_EEE_SLEEP_REQ_OFFSET 0 +#define RTL8367C_PORT4_EEECFG_EEE_SLEEP_REQ_MASK 0x1 + +#define RTL8367C_REG_PORT4_EEETXMTR 0x0099 + +#define RTL8367C_REG_PORT4_EEERXMTR 0x009a + +#define RTL8367C_REG_PORT4_EEEPTXMTR 0x009b + +#define RTL8367C_REG_PORT4_EEEPRXMTR 0x009c + +#define RTL8367C_REG_PTP_PORT4_CFG1 0x009e +#define RTL8367C_PTP_PORT4_CFG1_OFFSET 7 +#define RTL8367C_PTP_PORT4_CFG1_MASK 0xFF + +#define RTL8367C_REG_P4_MSIC1 0x009f +#define RTL8367C_P4_MSIC1_OFFSET 0 +#define RTL8367C_P4_MSIC1_MASK 0x1 + +#define RTL8367C_REG_PORT5_CGST_HALF_CFG 0x00a0 +#define RTL8367C_PORT5_CGST_HALF_CFG_CONGESTION_TIME_OFFSET 4 +#define RTL8367C_PORT5_CGST_HALF_CFG_CONGESTION_TIME_MASK 0xF0 +#define RTL8367C_PORT5_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_OFFSET 0 +#define RTL8367C_PORT5_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_MASK 0xF + +#define RTL8367C_REG_PKTGEN_PORT5_CTRL 0x00a1 +#define RTL8367C_PKTGEN_PORT5_CTRL_STATUS_OFFSET 15 +#define RTL8367C_PKTGEN_PORT5_CTRL_STATUS_MASK 0x8000 +#define RTL8367C_PKTGEN_PORT5_CTRL_PKTGEN_STS_OFFSET 13 +#define RTL8367C_PKTGEN_PORT5_CTRL_PKTGEN_STS_MASK 0x2000 +#define RTL8367C_PKTGEN_PORT5_CTRL_CRC_NO_ERROR_OFFSET 4 +#define RTL8367C_PKTGEN_PORT5_CTRL_CRC_NO_ERROR_MASK 0x10 +#define RTL8367C_PKTGEN_PORT5_CTRL_CMD_START_OFFSET 0 +#define RTL8367C_PKTGEN_PORT5_CTRL_CMD_START_MASK 0x1 + +#define RTL8367C_REG_TX_ERR_CNT_PORT5 0x00a2 +#define RTL8367C_TX_ERR_CNT_PORT5_OFFSET 0 +#define RTL8367C_TX_ERR_CNT_PORT5_MASK 0x7 + +#define RTL8367C_REG_PKTGEN_PORT5_DA0 0x00a3 + +#define RTL8367C_REG_PKTGEN_PORT5_DA1 0x00a4 + +#define RTL8367C_REG_PKTGEN_PORT5_DA2 0x00a5 + +#define RTL8367C_REG_PKTGEN_PORT5_SA0 0x00a6 + +#define RTL8367C_REG_PKTGEN_PORT5_SA1 0x00a7 + +#define RTL8367C_REG_PKTGEN_PORT5_SA2 0x00a8 + +#define RTL8367C_REG_PKTGEN_PORT5_COUNTER0 0x00a9 + +#define RTL8367C_REG_PKTGEN_PORT5_COUNTER1 0x00aa +#define RTL8367C_PKTGEN_PORT5_COUNTER1_OFFSET 0 +#define RTL8367C_PKTGEN_PORT5_COUNTER1_MASK 0xFF + +#define RTL8367C_REG_PKTGEN_PORT5_TX_LENGTH 0x00ab +#define RTL8367C_PKTGEN_PORT5_TX_LENGTH_OFFSET 0 +#define RTL8367C_PKTGEN_PORT5_TX_LENGTH_MASK 0x3FFF + +#define RTL8367C_REG_PKTGEN_PORT5_TIMER 0x00ad +#define RTL8367C_PKTGEN_PORT5_TIMER_TIMER_OFFSET 4 +#define RTL8367C_PKTGEN_PORT5_TIMER_TIMER_MASK 0xF0 +#define RTL8367C_PKTGEN_PORT5_TIMER_RX_DMA_ERR_FLAG_OFFSET 3 +#define RTL8367C_PKTGEN_PORT5_TIMER_RX_DMA_ERR_FLAG_MASK 0x8 + +#define RTL8367C_REG_PORT5_MISC_CFG 0x00ae +#define RTL8367C_PORT5_MISC_CFG_SMALL_TAG_IPG_OFFSET 15 +#define RTL8367C_PORT5_MISC_CFG_SMALL_TAG_IPG_MASK 0x8000 +#define RTL8367C_PORT5_MISC_CFG_TX_ITFSP_MODE_OFFSET 14 +#define RTL8367C_PORT5_MISC_CFG_TX_ITFSP_MODE_MASK 0x4000 +#define RTL8367C_PORT5_MISC_CFG_FLOWCTRL_INDEP_OFFSET 13 +#define RTL8367C_PORT5_MISC_CFG_FLOWCTRL_INDEP_MASK 0x2000 +#define RTL8367C_PORT5_MISC_CFG_DOT1Q_REMARK_ENABLE_OFFSET 12 +#define RTL8367C_PORT5_MISC_CFG_DOT1Q_REMARK_ENABLE_MASK 0x1000 +#define RTL8367C_PORT5_MISC_CFG_INGRESSBW_FLOWCTRL_OFFSET 11 +#define RTL8367C_PORT5_MISC_CFG_INGRESSBW_FLOWCTRL_MASK 0x800 +#define RTL8367C_PORT5_MISC_CFG_INGRESSBW_IFG_OFFSET 10 +#define RTL8367C_PORT5_MISC_CFG_INGRESSBW_IFG_MASK 0x400 +#define RTL8367C_PORT5_MISC_CFG_RX_SPC_OFFSET 9 +#define RTL8367C_PORT5_MISC_CFG_RX_SPC_MASK 0x200 +#define RTL8367C_PORT5_MISC_CFG_CRC_SKIP_OFFSET 8 +#define RTL8367C_PORT5_MISC_CFG_CRC_SKIP_MASK 0x100 +#define RTL8367C_PORT5_MISC_CFG_PKTGEN_TX_FIRST_OFFSET 7 +#define RTL8367C_PORT5_MISC_CFG_PKTGEN_TX_FIRST_MASK 0x80 +#define RTL8367C_PORT5_MISC_CFG_MAC_LOOPBACK_OFFSET 6 +#define RTL8367C_PORT5_MISC_CFG_MAC_LOOPBACK_MASK 0x40 +#define RTL8367C_PORT5_MISC_CFG_VLAN_EGRESS_MODE_OFFSET 4 +#define RTL8367C_PORT5_MISC_CFG_VLAN_EGRESS_MODE_MASK 0x30 +#define RTL8367C_PORT5_MISC_CFG_CONGESTION_SUSTAIN_TIME_OFFSET 0 +#define RTL8367C_PORT5_MISC_CFG_CONGESTION_SUSTAIN_TIME_MASK 0xF + +#define RTL8367C_REG_INGRESSBW_PORT5_RATE_CTRL0 0x00af + +#define RTL8367C_REG_INGRESSBW_PORT5_RATE_CTRL1 0x00b0 +#define RTL8367C_INGRESSBW_PORT5_RATE_CTRL1_DUMMY_OFFSET 3 +#define RTL8367C_INGRESSBW_PORT5_RATE_CTRL1_DUMMY_MASK 0xFFF8 +#define RTL8367C_INGRESSBW_PORT5_RATE_CTRL1_INGRESSBW_RATE16_OFFSET 0 +#define RTL8367C_INGRESSBW_PORT5_RATE_CTRL1_INGRESSBW_RATE16_MASK 0x7 + +#define RTL8367C_REG_PORT5_FORCE_RATE0 0x00b1 + +#define RTL8367C_REG_PORT5_FORCE_RATE1 0x00b2 + +#define RTL8367C_REG_PORT5_CURENT_RATE0 0x00b3 + +#define RTL8367C_REG_PORT5_CURENT_RATE1 0x00b4 + +#define RTL8367C_REG_PORT5_PAGE_COUNTER 0x00b5 +#define RTL8367C_PORT5_PAGE_COUNTER_OFFSET 0 +#define RTL8367C_PORT5_PAGE_COUNTER_MASK 0x7F + +#define RTL8367C_REG_PAGEMETER_PORT5_CTRL0 0x00b6 + +#define RTL8367C_REG_PAGEMETER_PORT5_CTRL1 0x00b7 + +#define RTL8367C_REG_PORT5_EEECFG 0x00b8 +#define RTL8367C_PORT5_EEECFG_EEEP_ENABLE_TX_OFFSET 14 +#define RTL8367C_PORT5_EEECFG_EEEP_ENABLE_TX_MASK 0x4000 +#define RTL8367C_PORT5_EEECFG_EEEP_ENABLE_RX_OFFSET 13 +#define RTL8367C_PORT5_EEECFG_EEEP_ENABLE_RX_MASK 0x2000 +#define RTL8367C_PORT5_EEECFG_EEE_FORCE_OFFSET 12 +#define RTL8367C_PORT5_EEECFG_EEE_FORCE_MASK 0x1000 +#define RTL8367C_PORT5_EEECFG_EEE_100M_OFFSET 11 +#define RTL8367C_PORT5_EEECFG_EEE_100M_MASK 0x800 +#define RTL8367C_PORT5_EEECFG_EEE_GIGA_500M_OFFSET 10 +#define RTL8367C_PORT5_EEECFG_EEE_GIGA_500M_MASK 0x400 +#define RTL8367C_PORT5_EEECFG_EEE_TX_OFFSET 9 +#define RTL8367C_PORT5_EEECFG_EEE_TX_MASK 0x200 +#define RTL8367C_PORT5_EEECFG_EEE_RX_OFFSET 8 +#define RTL8367C_PORT5_EEECFG_EEE_RX_MASK 0x100 +#define RTL8367C_PORT5_EEECFG_EEE_DSP_RX_OFFSET 6 +#define RTL8367C_PORT5_EEECFG_EEE_DSP_RX_MASK 0x40 +#define RTL8367C_PORT5_EEECFG_EEE_LPI_OFFSET 5 +#define RTL8367C_PORT5_EEECFG_EEE_LPI_MASK 0x20 +#define RTL8367C_PORT5_EEECFG_EEE_TX_LPI_OFFSET 4 +#define RTL8367C_PORT5_EEECFG_EEE_TX_LPI_MASK 0x10 +#define RTL8367C_PORT5_EEECFG_EEE_RX_LPI_OFFSET 3 +#define RTL8367C_PORT5_EEECFG_EEE_RX_LPI_MASK 0x8 +#define RTL8367C_PORT5_EEECFG_EEE_PAUSE_INDICATOR_OFFSET 2 +#define RTL8367C_PORT5_EEECFG_EEE_PAUSE_INDICATOR_MASK 0x4 +#define RTL8367C_PORT5_EEECFG_EEE_WAKE_REQ_OFFSET 1 +#define RTL8367C_PORT5_EEECFG_EEE_WAKE_REQ_MASK 0x2 +#define RTL8367C_PORT5_EEECFG_EEE_SLEEP_REQ_OFFSET 0 +#define RTL8367C_PORT5_EEECFG_EEE_SLEEP_REQ_MASK 0x1 + +#define RTL8367C_REG_PORT5_EEETXMTR 0x00b9 + +#define RTL8367C_REG_PORT5_EEERXMTR 0x00ba + +#define RTL8367C_REG_PORT5_EEEPTXMTR 0x00bb + +#define RTL8367C_REG_PORT5_EEEPRXMTR 0x00bc + +#define RTL8367C_REG_PTP_PORT5_CFG1 0x00be +#define RTL8367C_PTP_PORT5_CFG1_OFFSET 7 +#define RTL8367C_PTP_PORT5_CFG1_MASK 0xFF + +#define RTL8367C_REG_P5_MSIC1 0x00bf +#define RTL8367C_P5_MSIC1_OFFSET 0 +#define RTL8367C_P5_MSIC1_MASK 0x1 + +#define RTL8367C_REG_PORT6_CGST_HALF_CFG 0x00c0 +#define RTL8367C_PORT6_CGST_HALF_CFG_CONGESTION_TIME_OFFSET 4 +#define RTL8367C_PORT6_CGST_HALF_CFG_CONGESTION_TIME_MASK 0xF0 +#define RTL8367C_PORT6_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_OFFSET 0 +#define RTL8367C_PORT6_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_MASK 0xF + +#define RTL8367C_REG_PKTGEN_PORT6_CTRL 0x00c1 +#define RTL8367C_PKTGEN_PORT6_CTRL_STATUS_OFFSET 15 +#define RTL8367C_PKTGEN_PORT6_CTRL_STATUS_MASK 0x8000 +#define RTL8367C_PKTGEN_PORT6_CTRL_PKTGEN_STS_OFFSET 13 +#define RTL8367C_PKTGEN_PORT6_CTRL_PKTGEN_STS_MASK 0x2000 +#define RTL8367C_PKTGEN_PORT6_CTRL_CRC_NO_ERROR_OFFSET 4 +#define RTL8367C_PKTGEN_PORT6_CTRL_CRC_NO_ERROR_MASK 0x10 +#define RTL8367C_PKTGEN_PORT6_CTRL_CMD_START_OFFSET 0 +#define RTL8367C_PKTGEN_PORT6_CTRL_CMD_START_MASK 0x1 + +#define RTL8367C_REG_TX_ERR_CNT_PORT6 0x00c2 +#define RTL8367C_TX_ERR_CNT_PORT6_OFFSET 0 +#define RTL8367C_TX_ERR_CNT_PORT6_MASK 0x7 + +#define RTL8367C_REG_PKTGEN_PORT6_DA0 0x00c3 + +#define RTL8367C_REG_PKTGEN_PORT6_DA1 0x00c4 + +#define RTL8367C_REG_PKTGEN_PORT6_DA2 0x00c5 + +#define RTL8367C_REG_PKTGEN_PORT6_SA0 0x00c6 + +#define RTL8367C_REG_PKTGEN_PORT6_SA1 0x00c7 + +#define RTL8367C_REG_PKTGEN_PORT6_SA2 0x00c8 + +#define RTL8367C_REG_PKTGEN_PORT6_COUNTER0 0x00c9 + +#define RTL8367C_REG_PKTGEN_PORT6_COUNTER1 0x00ca +#define RTL8367C_PKTGEN_PORT6_COUNTER1_OFFSET 0 +#define RTL8367C_PKTGEN_PORT6_COUNTER1_MASK 0xFF + +#define RTL8367C_REG_PKTGEN_PORT6_TX_LENGTH 0x00cb +#define RTL8367C_PKTGEN_PORT6_TX_LENGTH_OFFSET 0 +#define RTL8367C_PKTGEN_PORT6_TX_LENGTH_MASK 0x3FFF + +#define RTL8367C_REG_PKTGEN_PORT6_TIMER 0x00cd +#define RTL8367C_PKTGEN_PORT6_TIMER_TIMER_OFFSET 4 +#define RTL8367C_PKTGEN_PORT6_TIMER_TIMER_MASK 0xF0 +#define RTL8367C_PKTGEN_PORT6_TIMER_RX_DMA_ERR_FLAG_OFFSET 3 +#define RTL8367C_PKTGEN_PORT6_TIMER_RX_DMA_ERR_FLAG_MASK 0x8 + +#define RTL8367C_REG_PORT6_MISC_CFG 0x00ce +#define RTL8367C_PORT6_MISC_CFG_SMALL_TAG_IPG_OFFSET 15 +#define RTL8367C_PORT6_MISC_CFG_SMALL_TAG_IPG_MASK 0x8000 +#define RTL8367C_PORT6_MISC_CFG_TX_ITFSP_MODE_OFFSET 14 +#define RTL8367C_PORT6_MISC_CFG_TX_ITFSP_MODE_MASK 0x4000 +#define RTL8367C_PORT6_MISC_CFG_FLOWCTRL_INDEP_OFFSET 13 +#define RTL8367C_PORT6_MISC_CFG_FLOWCTRL_INDEP_MASK 0x2000 +#define RTL8367C_PORT6_MISC_CFG_DOT1Q_REMARK_ENABLE_OFFSET 12 +#define RTL8367C_PORT6_MISC_CFG_DOT1Q_REMARK_ENABLE_MASK 0x1000 +#define RTL8367C_PORT6_MISC_CFG_INGRESSBW_FLOWCTRL_OFFSET 11 +#define RTL8367C_PORT6_MISC_CFG_INGRESSBW_FLOWCTRL_MASK 0x800 +#define RTL8367C_PORT6_MISC_CFG_INGRESSBW_IFG_OFFSET 10 +#define RTL8367C_PORT6_MISC_CFG_INGRESSBW_IFG_MASK 0x400 +#define RTL8367C_PORT6_MISC_CFG_RX_SPC_OFFSET 9 +#define RTL8367C_PORT6_MISC_CFG_RX_SPC_MASK 0x200 +#define RTL8367C_PORT6_MISC_CFG_CRC_SKIP_OFFSET 8 +#define RTL8367C_PORT6_MISC_CFG_CRC_SKIP_MASK 0x100 +#define RTL8367C_PORT6_MISC_CFG_PKTGEN_TX_FIRST_OFFSET 7 +#define RTL8367C_PORT6_MISC_CFG_PKTGEN_TX_FIRST_MASK 0x80 +#define RTL8367C_PORT6_MISC_CFG_MAC_LOOPBACK_OFFSET 6 +#define RTL8367C_PORT6_MISC_CFG_MAC_LOOPBACK_MASK 0x40 +#define RTL8367C_PORT6_MISC_CFG_VLAN_EGRESS_MODE_OFFSET 4 +#define RTL8367C_PORT6_MISC_CFG_VLAN_EGRESS_MODE_MASK 0x30 +#define RTL8367C_PORT6_MISC_CFG_CONGESTION_SUSTAIN_TIME_OFFSET 0 +#define RTL8367C_PORT6_MISC_CFG_CONGESTION_SUSTAIN_TIME_MASK 0xF + +#define RTL8367C_REG_INGRESSBW_PORT6_RATE_CTRL0 0x00cf + +#define RTL8367C_REG_INGRESSBW_PORT6_RATE_CTRL1 0x00d0 +#define RTL8367C_INGRESSBW_PORT6_RATE_CTRL1_DUMMY_OFFSET 3 +#define RTL8367C_INGRESSBW_PORT6_RATE_CTRL1_DUMMY_MASK 0xFFF8 +#define RTL8367C_INGRESSBW_PORT6_RATE_CTRL1_INGRESSBW_RATE16_OFFSET 0 +#define RTL8367C_INGRESSBW_PORT6_RATE_CTRL1_INGRESSBW_RATE16_MASK 0x7 + +#define RTL8367C_REG_PORT6_FORCE_RATE0 0x00d1 + +#define RTL8367C_REG_PORT6_FORCE_RATE1 0x00d2 + +#define RTL8367C_REG_PORT6_CURENT_RATE0 0x00d3 + +#define RTL8367C_REG_PORT6_CURENT_RATE1 0x00d4 + +#define RTL8367C_REG_PORT6_PAGE_COUNTER 0x00d5 +#define RTL8367C_PORT6_PAGE_COUNTER_OFFSET 0 +#define RTL8367C_PORT6_PAGE_COUNTER_MASK 0x7F + +#define RTL8367C_REG_PAGEMETER_PORT6_CTRL0 0x00d6 + +#define RTL8367C_REG_PAGEMETER_PORT6_CTRL1 0x00d7 + +#define RTL8367C_REG_PORT6_EEECFG 0x00d8 +#define RTL8367C_PORT6_EEECFG_EEEP_ENABLE_TX_OFFSET 14 +#define RTL8367C_PORT6_EEECFG_EEEP_ENABLE_TX_MASK 0x4000 +#define RTL8367C_PORT6_EEECFG_EEEP_ENABLE_RX_OFFSET 13 +#define RTL8367C_PORT6_EEECFG_EEEP_ENABLE_RX_MASK 0x2000 +#define RTL8367C_PORT6_EEECFG_EEE_FORCE_OFFSET 12 +#define RTL8367C_PORT6_EEECFG_EEE_FORCE_MASK 0x1000 +#define RTL8367C_PORT6_EEECFG_EEE_100M_OFFSET 11 +#define RTL8367C_PORT6_EEECFG_EEE_100M_MASK 0x800 +#define RTL8367C_PORT6_EEECFG_EEE_GIGA_500M_OFFSET 10 +#define RTL8367C_PORT6_EEECFG_EEE_GIGA_500M_MASK 0x400 +#define RTL8367C_PORT6_EEECFG_EEE_TX_OFFSET 9 +#define RTL8367C_PORT6_EEECFG_EEE_TX_MASK 0x200 +#define RTL8367C_PORT6_EEECFG_EEE_RX_OFFSET 8 +#define RTL8367C_PORT6_EEECFG_EEE_RX_MASK 0x100 +#define RTL8367C_PORT6_EEECFG_EEE_DSP_RX_OFFSET 6 +#define RTL8367C_PORT6_EEECFG_EEE_DSP_RX_MASK 0x40 +#define RTL8367C_PORT6_EEECFG_EEE_LPI_OFFSET 5 +#define RTL8367C_PORT6_EEECFG_EEE_LPI_MASK 0x20 +#define RTL8367C_PORT6_EEECFG_EEE_TX_LPI_OFFSET 4 +#define RTL8367C_PORT6_EEECFG_EEE_TX_LPI_MASK 0x10 +#define RTL8367C_PORT6_EEECFG_EEE_RX_LPI_OFFSET 3 +#define RTL8367C_PORT6_EEECFG_EEE_RX_LPI_MASK 0x8 +#define RTL8367C_PORT6_EEECFG_EEE_PAUSE_INDICATOR_OFFSET 2 +#define RTL8367C_PORT6_EEECFG_EEE_PAUSE_INDICATOR_MASK 0x4 +#define RTL8367C_PORT6_EEECFG_EEE_WAKE_REQ_OFFSET 1 +#define RTL8367C_PORT6_EEECFG_EEE_WAKE_REQ_MASK 0x2 +#define RTL8367C_PORT6_EEECFG_EEE_SLEEP_REQ_OFFSET 0 +#define RTL8367C_PORT6_EEECFG_EEE_SLEEP_REQ_MASK 0x1 + +#define RTL8367C_REG_PORT6_EEETXMTR 0x00d9 + +#define RTL8367C_REG_PORT6_EEERXMTR 0x00da + +#define RTL8367C_REG_PORT6_EEEPTXMTR 0x00db + +#define RTL8367C_REG_PORT6_EEEPRXMTR 0x00dc + +#define RTL8367C_REG_PTP_PORT6_CFG1 0x00de +#define RTL8367C_PTP_PORT6_CFG1_OFFSET 7 +#define RTL8367C_PTP_PORT6_CFG1_MASK 0xFF + +#define RTL8367C_REG_P6_MSIC1 0x00df +#define RTL8367C_P6_MSIC1_OFFSET 0 +#define RTL8367C_P6_MSIC1_MASK 0x1 + +#define RTL8367C_REG_PORT7_CGST_HALF_CFG 0x00e0 +#define RTL8367C_PORT7_CGST_HALF_CFG_CONGESTION_TIME_OFFSET 4 +#define RTL8367C_PORT7_CGST_HALF_CFG_CONGESTION_TIME_MASK 0xF0 +#define RTL8367C_PORT7_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_OFFSET 0 +#define RTL8367C_PORT7_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_MASK 0xF + +#define RTL8367C_REG_PKTGEN_PORT7_CTRL 0x00e1 +#define RTL8367C_PKTGEN_PORT7_CTRL_STATUS_OFFSET 15 +#define RTL8367C_PKTGEN_PORT7_CTRL_STATUS_MASK 0x8000 +#define RTL8367C_PKTGEN_PORT7_CTRL_PKTGEN_STS_OFFSET 13 +#define RTL8367C_PKTGEN_PORT7_CTRL_PKTGEN_STS_MASK 0x2000 +#define RTL8367C_PKTGEN_PORT7_CTRL_CRC_NO_ERROR_OFFSET 4 +#define RTL8367C_PKTGEN_PORT7_CTRL_CRC_NO_ERROR_MASK 0x10 +#define RTL8367C_PKTGEN_PORT7_CTRL_CMD_START_OFFSET 0 +#define RTL8367C_PKTGEN_PORT7_CTRL_CMD_START_MASK 0x1 + +#define RTL8367C_REG_TX_ERR_CNT_PORT7 0x00e2 +#define RTL8367C_TX_ERR_CNT_PORT7_OFFSET 0 +#define RTL8367C_TX_ERR_CNT_PORT7_MASK 0x7 + +#define RTL8367C_REG_PKTGEN_PORT7_DA0 0x00e3 + +#define RTL8367C_REG_PKTGEN_PORT7_DA1 0x00e4 + +#define RTL8367C_REG_PKTGEN_PORT7_DA2 0x00e5 + +#define RTL8367C_REG_PKTGEN_PORT7_SA0 0x00e6 + +#define RTL8367C_REG_PKTGEN_PORT7_SA1 0x00e7 + +#define RTL8367C_REG_PKTGEN_PORT7_SA2 0x00e8 + +#define RTL8367C_REG_PKTGEN_PORT7_COUNTER0 0x00e9 + +#define RTL8367C_REG_PKTGEN_PORT7_COUNTER1 0x00ea +#define RTL8367C_PKTGEN_PORT7_COUNTER1_OFFSET 0 +#define RTL8367C_PKTGEN_PORT7_COUNTER1_MASK 0xFF + +#define RTL8367C_REG_PKTGEN_PORT7_TX_LENGTH 0x00eb +#define RTL8367C_PKTGEN_PORT7_TX_LENGTH_OFFSET 0 +#define RTL8367C_PKTGEN_PORT7_TX_LENGTH_MASK 0x3FFF + +#define RTL8367C_REG_PKTGEN_PORT7_TIMER 0x00ed +#define RTL8367C_PKTGEN_PORT7_TIMER_TIMER_OFFSET 4 +#define RTL8367C_PKTGEN_PORT7_TIMER_TIMER_MASK 0xF0 +#define RTL8367C_PKTGEN_PORT7_TIMER_RX_DMA_ERR_FLAG_OFFSET 3 +#define RTL8367C_PKTGEN_PORT7_TIMER_RX_DMA_ERR_FLAG_MASK 0x8 + +#define RTL8367C_REG_PORT7_MISC_CFG 0x00ee +#define RTL8367C_PORT7_MISC_CFG_SMALL_TAG_IPG_OFFSET 15 +#define RTL8367C_PORT7_MISC_CFG_SMALL_TAG_IPG_MASK 0x8000 +#define RTL8367C_PORT7_MISC_CFG_TX_ITFSP_MODE_OFFSET 14 +#define RTL8367C_PORT7_MISC_CFG_TX_ITFSP_MODE_MASK 0x4000 +#define RTL8367C_PORT7_MISC_CFG_FLOWCTRL_INDEP_OFFSET 13 +#define RTL8367C_PORT7_MISC_CFG_FLOWCTRL_INDEP_MASK 0x2000 +#define RTL8367C_PORT7_MISC_CFG_DOT1Q_REMARK_ENABLE_OFFSET 12 +#define RTL8367C_PORT7_MISC_CFG_DOT1Q_REMARK_ENABLE_MASK 0x1000 +#define RTL8367C_PORT7_MISC_CFG_INGRESSBW_FLOWCTRL_OFFSET 11 +#define RTL8367C_PORT7_MISC_CFG_INGRESSBW_FLOWCTRL_MASK 0x800 +#define RTL8367C_PORT7_MISC_CFG_INGRESSBW_IFG_OFFSET 10 +#define RTL8367C_PORT7_MISC_CFG_INGRESSBW_IFG_MASK 0x400 +#define RTL8367C_PORT7_MISC_CFG_RX_SPC_OFFSET 9 +#define RTL8367C_PORT7_MISC_CFG_RX_SPC_MASK 0x200 +#define RTL8367C_PORT7_MISC_CFG_CRC_SKIP_OFFSET 8 +#define RTL8367C_PORT7_MISC_CFG_CRC_SKIP_MASK 0x100 +#define RTL8367C_PORT7_MISC_CFG_PKTGEN_TX_FIRST_OFFSET 7 +#define RTL8367C_PORT7_MISC_CFG_PKTGEN_TX_FIRST_MASK 0x80 +#define RTL8367C_PORT7_MISC_CFG_MAC_LOOPBACK_OFFSET 6 +#define RTL8367C_PORT7_MISC_CFG_MAC_LOOPBACK_MASK 0x40 +#define RTL8367C_PORT7_MISC_CFG_VLAN_EGRESS_MODE_OFFSET 4 +#define RTL8367C_PORT7_MISC_CFG_VLAN_EGRESS_MODE_MASK 0x30 +#define RTL8367C_PORT7_MISC_CFG_CONGESTION_SUSTAIN_TIME_OFFSET 0 +#define RTL8367C_PORT7_MISC_CFG_CONGESTION_SUSTAIN_TIME_MASK 0xF + +#define RTL8367C_REG_INGRESSBW_PORT7_RATE_CTRL0 0x00ef + +#define RTL8367C_REG_INGRESSBW_PORT7_RATE_CTRL1 0x00f0 +#define RTL8367C_INGRESSBW_PORT7_RATE_CTRL1_DUMMY_OFFSET 3 +#define RTL8367C_INGRESSBW_PORT7_RATE_CTRL1_DUMMY_MASK 0xFFF8 +#define RTL8367C_INGRESSBW_PORT7_RATE_CTRL1_INGRESSBW_RATE16_OFFSET 0 +#define RTL8367C_INGRESSBW_PORT7_RATE_CTRL1_INGRESSBW_RATE16_MASK 0x7 + +#define RTL8367C_REG_PORT7_FORCE_RATE0 0x00f1 + +#define RTL8367C_REG_PORT7_FORCE_RATE1 0x00f2 + +#define RTL8367C_REG_PORT7_CURENT_RATE0 0x00f3 + +#define RTL8367C_REG_PORT7_CURENT_RATE1 0x00f4 + +#define RTL8367C_REG_PORT7_PAGE_COUNTER 0x00f5 +#define RTL8367C_PORT7_PAGE_COUNTER_OFFSET 0 +#define RTL8367C_PORT7_PAGE_COUNTER_MASK 0x7F + +#define RTL8367C_REG_PAGEMETER_PORT7_CTRL0 0x00f6 + +#define RTL8367C_REG_PAGEMETER_PORT7_CTRL1 0x00f7 + +#define RTL8367C_REG_PORT7_EEECFG 0x00f8 +#define RTL8367C_PORT7_EEECFG_EEEP_ENABLE_TX_OFFSET 14 +#define RTL8367C_PORT7_EEECFG_EEEP_ENABLE_TX_MASK 0x4000 +#define RTL8367C_PORT7_EEECFG_EEEP_ENABLE_RX_OFFSET 13 +#define RTL8367C_PORT7_EEECFG_EEEP_ENABLE_RX_MASK 0x2000 +#define RTL8367C_PORT7_EEECFG_EEE_FORCE_OFFSET 12 +#define RTL8367C_PORT7_EEECFG_EEE_FORCE_MASK 0x1000 +#define RTL8367C_PORT7_EEECFG_EEE_100M_OFFSET 11 +#define RTL8367C_PORT7_EEECFG_EEE_100M_MASK 0x800 +#define RTL8367C_PORT7_EEECFG_EEE_GIGA_500M_OFFSET 10 +#define RTL8367C_PORT7_EEECFG_EEE_GIGA_500M_MASK 0x400 +#define RTL8367C_PORT7_EEECFG_EEE_TX_OFFSET 9 +#define RTL8367C_PORT7_EEECFG_EEE_TX_MASK 0x200 +#define RTL8367C_PORT7_EEECFG_EEE_RX_OFFSET 8 +#define RTL8367C_PORT7_EEECFG_EEE_RX_MASK 0x100 +#define RTL8367C_PORT7_EEECFG_EEE_DSP_RX_OFFSET 6 +#define RTL8367C_PORT7_EEECFG_EEE_DSP_RX_MASK 0x40 +#define RTL8367C_PORT7_EEECFG_EEE_LPI_OFFSET 5 +#define RTL8367C_PORT7_EEECFG_EEE_LPI_MASK 0x20 +#define RTL8367C_PORT7_EEECFG_EEE_TX_LPI_OFFSET 4 +#define RTL8367C_PORT7_EEECFG_EEE_TX_LPI_MASK 0x10 +#define RTL8367C_PORT7_EEECFG_EEE_RX_LPI_OFFSET 3 +#define RTL8367C_PORT7_EEECFG_EEE_RX_LPI_MASK 0x8 +#define RTL8367C_PORT7_EEECFG_EEE_PAUSE_INDICATOR_OFFSET 2 +#define RTL8367C_PORT7_EEECFG_EEE_PAUSE_INDICATOR_MASK 0x4 +#define RTL8367C_PORT7_EEECFG_EEE_WAKE_REQ_OFFSET 1 +#define RTL8367C_PORT7_EEECFG_EEE_WAKE_REQ_MASK 0x2 +#define RTL8367C_PORT7_EEECFG_EEE_SLEEP_REQ_OFFSET 0 +#define RTL8367C_PORT7_EEECFG_EEE_SLEEP_REQ_MASK 0x1 + +#define RTL8367C_REG_PORT7_EEETXMTR 0x00f9 + +#define RTL8367C_REG_PORT7_EEERXMTR 0x00fa + +#define RTL8367C_REG_PORT7_EEEPTXMTR 0x00fb + +#define RTL8367C_REG_PORT7_EEEPRXMTR 0x00fc + +#define RTL8367C_REG_PTP_PORT7_CFG1 0x00fe +#define RTL8367C_PTP_PORT7_CFG1_OFFSET 7 +#define RTL8367C_PTP_PORT7_CFG1_MASK 0xFF + +#define RTL8367C_REG_P7_MSIC1 0x00ff +#define RTL8367C_P7_MSIC1_OFFSET 0 +#define RTL8367C_P7_MSIC1_MASK 0x1 + +#define RTL8367C_REG_PORT8_CGST_HALF_CFG 0x0100 +#define RTL8367C_PORT8_CGST_HALF_CFG_CONGESTION_TIME_OFFSET 4 +#define RTL8367C_PORT8_CGST_HALF_CFG_CONGESTION_TIME_MASK 0xF0 +#define RTL8367C_PORT8_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_OFFSET 0 +#define RTL8367C_PORT8_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_MASK 0xF + +#define RTL8367C_REG_PKTGEN_PORT8_CTRL 0x0101 +#define RTL8367C_PKTGEN_PORT8_CTRL_STATUS_OFFSET 15 +#define RTL8367C_PKTGEN_PORT8_CTRL_STATUS_MASK 0x8000 +#define RTL8367C_PKTGEN_PORT8_CTRL_PKTGEN_STS_OFFSET 13 +#define RTL8367C_PKTGEN_PORT8_CTRL_PKTGEN_STS_MASK 0x2000 +#define RTL8367C_PKTGEN_PORT8_CTRL_CRC_NO_ERROR_OFFSET 4 +#define RTL8367C_PKTGEN_PORT8_CTRL_CRC_NO_ERROR_MASK 0x10 +#define RTL8367C_PKTGEN_PORT8_CTRL_CMD_START_OFFSET 0 +#define RTL8367C_PKTGEN_PORT8_CTRL_CMD_START_MASK 0x1 + +#define RTL8367C_REG_TX_ERR_CNT_PORT8 0x0102 +#define RTL8367C_TX_ERR_CNT_PORT8_OFFSET 0 +#define RTL8367C_TX_ERR_CNT_PORT8_MASK 0x7 + +#define RTL8367C_REG_PKTGEN_PORT8_DA0 0x0103 + +#define RTL8367C_REG_PKTGEN_PORT8_DA1 0x0104 + +#define RTL8367C_REG_PKTGEN_PORT8_DA2 0x0105 + +#define RTL8367C_REG_PKTGEN_PORT8_SA0 0x0106 + +#define RTL8367C_REG_PKTGEN_PORT8_SA1 0x0107 + +#define RTL8367C_REG_PKTGEN_PORT8_SA2 0x0108 + +#define RTL8367C_REG_PKTGEN_PORT8_COUNTER0 0x0109 + +#define RTL8367C_REG_PKTGEN_PORT8_COUNTER1 0x010a +#define RTL8367C_PKTGEN_PORT8_COUNTER1_OFFSET 0 +#define RTL8367C_PKTGEN_PORT8_COUNTER1_MASK 0xFF + +#define RTL8367C_REG_PKTGEN_PORT8_TX_LENGTH 0x010b +#define RTL8367C_PKTGEN_PORT8_TX_LENGTH_OFFSET 0 +#define RTL8367C_PKTGEN_PORT8_TX_LENGTH_MASK 0x3FFF + +#define RTL8367C_REG_PKTGEN_PORT8_TIMER 0x010d +#define RTL8367C_PKTGEN_PORT8_TIMER_TIMER_OFFSET 4 +#define RTL8367C_PKTGEN_PORT8_TIMER_TIMER_MASK 0xF0 +#define RTL8367C_PKTGEN_PORT8_TIMER_RX_DMA_ERR_FLAG_OFFSET 3 +#define RTL8367C_PKTGEN_PORT8_TIMER_RX_DMA_ERR_FLAG_MASK 0x8 + +#define RTL8367C_REG_PORT8_MISC_CFG 0x010e +#define RTL8367C_PORT8_MISC_CFG_SMALL_TAG_IPG_OFFSET 15 +#define RTL8367C_PORT8_MISC_CFG_SMALL_TAG_IPG_MASK 0x8000 +#define RTL8367C_PORT8_MISC_CFG_TX_ITFSP_MODE_OFFSET 14 +#define RTL8367C_PORT8_MISC_CFG_TX_ITFSP_MODE_MASK 0x4000 +#define RTL8367C_PORT8_MISC_CFG_FLOWCTRL_INDEP_OFFSET 13 +#define RTL8367C_PORT8_MISC_CFG_FLOWCTRL_INDEP_MASK 0x2000 +#define RTL8367C_PORT8_MISC_CFG_DOT1Q_REMARK_ENABLE_OFFSET 12 +#define RTL8367C_PORT8_MISC_CFG_DOT1Q_REMARK_ENABLE_MASK 0x1000 +#define RTL8367C_PORT8_MISC_CFG_INGRESSBW_FLOWCTRL_OFFSET 11 +#define RTL8367C_PORT8_MISC_CFG_INGRESSBW_FLOWCTRL_MASK 0x800 +#define RTL8367C_PORT8_MISC_CFG_INGRESSBW_IFG_OFFSET 10 +#define RTL8367C_PORT8_MISC_CFG_INGRESSBW_IFG_MASK 0x400 +#define RTL8367C_PORT8_MISC_CFG_RX_SPC_OFFSET 9 +#define RTL8367C_PORT8_MISC_CFG_RX_SPC_MASK 0x200 +#define RTL8367C_PORT8_MISC_CFG_CRC_SKIP_OFFSET 8 +#define RTL8367C_PORT8_MISC_CFG_CRC_SKIP_MASK 0x100 +#define RTL8367C_PORT8_MISC_CFG_PKTGEN_TX_FIRST_OFFSET 7 +#define RTL8367C_PORT8_MISC_CFG_PKTGEN_TX_FIRST_MASK 0x80 +#define RTL8367C_PORT8_MISC_CFG_MAC_LOOPBACK_OFFSET 6 +#define RTL8367C_PORT8_MISC_CFG_MAC_LOOPBACK_MASK 0x40 +#define RTL8367C_PORT8_MISC_CFG_VLAN_EGRESS_MODE_OFFSET 4 +#define RTL8367C_PORT8_MISC_CFG_VLAN_EGRESS_MODE_MASK 0x30 +#define RTL8367C_PORT8_MISC_CFG_CONGESTION_SUSTAIN_TIME_OFFSET 0 +#define RTL8367C_PORT8_MISC_CFG_CONGESTION_SUSTAIN_TIME_MASK 0xF + +#define RTL8367C_REG_INGRESSBW_PORT8_RATE_CTRL0 0x010f + +#define RTL8367C_REG_INGRESSBW_PORT8_RATE_CTRL1 0x0110 +#define RTL8367C_INGRESSBW_PORT8_RATE_CTRL1_DUMMY_OFFSET 3 +#define RTL8367C_INGRESSBW_PORT8_RATE_CTRL1_DUMMY_MASK 0xFFF8 +#define RTL8367C_INGRESSBW_PORT8_RATE_CTRL1_INGRESSBW_RATE16_OFFSET 0 +#define RTL8367C_INGRESSBW_PORT8_RATE_CTRL1_INGRESSBW_RATE16_MASK 0x7 + +#define RTL8367C_REG_PORT8_FORCE_RATE0 0x0111 + +#define RTL8367C_REG_PORT8_FORCE_RATE1 0x0112 + +#define RTL8367C_REG_PORT8_CURENT_RATE0 0x0113 + +#define RTL8367C_REG_PORT8_CURENT_RATE1 0x0114 + +#define RTL8367C_REG_PORT8_PAGE_COUNTER 0x0115 +#define RTL8367C_PORT8_PAGE_COUNTER_OFFSET 0 +#define RTL8367C_PORT8_PAGE_COUNTER_MASK 0x7F + +#define RTL8367C_REG_PAGEMETER_PORT8_CTRL0 0x0116 + +#define RTL8367C_REG_PAGEMETER_PORT8_CTRL1 0x0117 + +#define RTL8367C_REG_PORT8_EEECFG 0x0118 +#define RTL8367C_PORT8_EEECFG_EEEP_ENABLE_TX_OFFSET 14 +#define RTL8367C_PORT8_EEECFG_EEEP_ENABLE_TX_MASK 0x4000 +#define RTL8367C_PORT8_EEECFG_EEEP_ENABLE_RX_OFFSET 13 +#define RTL8367C_PORT8_EEECFG_EEEP_ENABLE_RX_MASK 0x2000 +#define RTL8367C_PORT8_EEECFG_EEE_FORCE_OFFSET 12 +#define RTL8367C_PORT8_EEECFG_EEE_FORCE_MASK 0x1000 +#define RTL8367C_PORT8_EEECFG_EEE_100M_OFFSET 11 +#define RTL8367C_PORT8_EEECFG_EEE_100M_MASK 0x800 +#define RTL8367C_PORT8_EEECFG_EEE_GIGA_500M_OFFSET 10 +#define RTL8367C_PORT8_EEECFG_EEE_GIGA_500M_MASK 0x400 +#define RTL8367C_PORT8_EEECFG_EEE_TX_OFFSET 9 +#define RTL8367C_PORT8_EEECFG_EEE_TX_MASK 0x200 +#define RTL8367C_PORT8_EEECFG_EEE_RX_OFFSET 8 +#define RTL8367C_PORT8_EEECFG_EEE_RX_MASK 0x100 +#define RTL8367C_PORT8_EEECFG_EEE_DSP_RX_OFFSET 6 +#define RTL8367C_PORT8_EEECFG_EEE_DSP_RX_MASK 0x40 +#define RTL8367C_PORT8_EEECFG_EEE_LPI_OFFSET 5 +#define RTL8367C_PORT8_EEECFG_EEE_LPI_MASK 0x20 +#define RTL8367C_PORT8_EEECFG_EEE_TX_LPI_OFFSET 4 +#define RTL8367C_PORT8_EEECFG_EEE_TX_LPI_MASK 0x10 +#define RTL8367C_PORT8_EEECFG_EEE_RX_LPI_OFFSET 3 +#define RTL8367C_PORT8_EEECFG_EEE_RX_LPI_MASK 0x8 +#define RTL8367C_PORT8_EEECFG_EEE_PAUSE_INDICATOR_OFFSET 2 +#define RTL8367C_PORT8_EEECFG_EEE_PAUSE_INDICATOR_MASK 0x4 +#define RTL8367C_PORT8_EEECFG_EEE_WAKE_REQ_OFFSET 1 +#define RTL8367C_PORT8_EEECFG_EEE_WAKE_REQ_MASK 0x2 +#define RTL8367C_PORT8_EEECFG_EEE_SLEEP_REQ_OFFSET 0 +#define RTL8367C_PORT8_EEECFG_EEE_SLEEP_REQ_MASK 0x1 + +#define RTL8367C_REG_PORT8_EEETXMTR 0x0119 + +#define RTL8367C_REG_PORT8_EEERXMTR 0x011a + +#define RTL8367C_REG_PORT8_EEEPTXMTR 0x011b + +#define RTL8367C_REG_PORT8_EEEPRXMTR 0x011c + +#define RTL8367C_REG_PTP_PORT8_CFG1 0x011e +#define RTL8367C_PTP_PORT8_CFG1_OFFSET 7 +#define RTL8367C_PTP_PORT8_CFG1_MASK 0xFF + +#define RTL8367C_REG_P8_MSIC1 0x011f +#define RTL8367C_P8_MSIC1_OFFSET 0 +#define RTL8367C_P8_MSIC1_MASK 0x1 + +#define RTL8367C_REG_PORT9_CGST_HALF_CFG 0x0120 +#define RTL8367C_PORT9_CGST_HALF_CFG_CONGESTION_TIME_OFFSET 4 +#define RTL8367C_PORT9_CGST_HALF_CFG_CONGESTION_TIME_MASK 0xF0 +#define RTL8367C_PORT9_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_OFFSET 0 +#define RTL8367C_PORT9_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_MASK 0xF + +#define RTL8367C_REG_PKTGEN_PORT9_CTRL 0x0121 +#define RTL8367C_PKTGEN_PORT9_CTRL_STATUS_OFFSET 15 +#define RTL8367C_PKTGEN_PORT9_CTRL_STATUS_MASK 0x8000 +#define RTL8367C_PKTGEN_PORT9_CTRL_PKTGEN_STS_OFFSET 13 +#define RTL8367C_PKTGEN_PORT9_CTRL_PKTGEN_STS_MASK 0x2000 +#define RTL8367C_PKTGEN_PORT9_CTRL_CRC_NO_ERROR_OFFSET 4 +#define RTL8367C_PKTGEN_PORT9_CTRL_CRC_NO_ERROR_MASK 0x10 +#define RTL8367C_PKTGEN_PORT9_CTRL_CMD_START_OFFSET 0 +#define RTL8367C_PKTGEN_PORT9_CTRL_CMD_START_MASK 0x1 + +#define RTL8367C_REG_TX_ERR_CNT_PORT9 0x0122 +#define RTL8367C_TX_ERR_CNT_PORT9_OFFSET 0 +#define RTL8367C_TX_ERR_CNT_PORT9_MASK 0x7 + +#define RTL8367C_REG_PKTGEN_PORT9_DA0 0x0123 + +#define RTL8367C_REG_PKTGEN_PORT9_DA1 0x0124 + +#define RTL8367C_REG_PKTGEN_PORT9_DA2 0x0125 + +#define RTL8367C_REG_PKTGEN_PORT9_SA0 0x0126 + +#define RTL8367C_REG_PKTGEN_PORT9_SA1 0x0127 + +#define RTL8367C_REG_PKTGEN_PORT9_SA2 0x0128 + +#define RTL8367C_REG_PKTGEN_PORT9_COUNTER0 0x0129 + +#define RTL8367C_REG_PKTGEN_PORT9_COUNTER1 0x012a +#define RTL8367C_PKTGEN_PORT9_COUNTER1_OFFSET 0 +#define RTL8367C_PKTGEN_PORT9_COUNTER1_MASK 0xFF + +#define RTL8367C_REG_PKTGEN_PORT9_TX_LENGTH 0x012b +#define RTL8367C_PKTGEN_PORT9_TX_LENGTH_OFFSET 0 +#define RTL8367C_PKTGEN_PORT9_TX_LENGTH_MASK 0x3FFF + +#define RTL8367C_REG_PKTGEN_PORT9_TIMER 0x012d +#define RTL8367C_PKTGEN_PORT9_TIMER_TIMER_OFFSET 4 +#define RTL8367C_PKTGEN_PORT9_TIMER_TIMER_MASK 0xF0 +#define RTL8367C_PKTGEN_PORT9_TIMER_RX_DMA_ERR_FLAG_OFFSET 3 +#define RTL8367C_PKTGEN_PORT9_TIMER_RX_DMA_ERR_FLAG_MASK 0x8 + +#define RTL8367C_REG_PORT9_MISC_CFG 0x012e +#define RTL8367C_PORT9_MISC_CFG_SMALL_TAG_IPG_OFFSET 15 +#define RTL8367C_PORT9_MISC_CFG_SMALL_TAG_IPG_MASK 0x8000 +#define RTL8367C_PORT9_MISC_CFG_TX_ITFSP_MODE_OFFSET 14 +#define RTL8367C_PORT9_MISC_CFG_TX_ITFSP_MODE_MASK 0x4000 +#define RTL8367C_PORT9_MISC_CFG_FLOWCTRL_INDEP_OFFSET 13 +#define RTL8367C_PORT9_MISC_CFG_FLOWCTRL_INDEP_MASK 0x2000 +#define RTL8367C_PORT9_MISC_CFG_DOT1Q_REMARK_ENABLE_OFFSET 12 +#define RTL8367C_PORT9_MISC_CFG_DOT1Q_REMARK_ENABLE_MASK 0x1000 +#define RTL8367C_PORT9_MISC_CFG_INGRESSBW_FLOWCTRL_OFFSET 11 +#define RTL8367C_PORT9_MISC_CFG_INGRESSBW_FLOWCTRL_MASK 0x800 +#define RTL8367C_PORT9_MISC_CFG_INGRESSBW_IFG_OFFSET 10 +#define RTL8367C_PORT9_MISC_CFG_INGRESSBW_IFG_MASK 0x400 +#define RTL8367C_PORT9_MISC_CFG_RX_SPC_OFFSET 9 +#define RTL8367C_PORT9_MISC_CFG_RX_SPC_MASK 0x200 +#define RTL8367C_PORT9_MISC_CFG_CRC_SKIP_OFFSET 8 +#define RTL8367C_PORT9_MISC_CFG_CRC_SKIP_MASK 0x100 +#define RTL8367C_PORT9_MISC_CFG_PKTGEN_TX_FIRST_OFFSET 7 +#define RTL8367C_PORT9_MISC_CFG_PKTGEN_TX_FIRST_MASK 0x80 +#define RTL8367C_PORT9_MISC_CFG_MAC_LOOPBACK_OFFSET 6 +#define RTL8367C_PORT9_MISC_CFG_MAC_LOOPBACK_MASK 0x40 +#define RTL8367C_PORT9_MISC_CFG_VLAN_EGRESS_MODE_OFFSET 4 +#define RTL8367C_PORT9_MISC_CFG_VLAN_EGRESS_MODE_MASK 0x30 +#define RTL8367C_PORT9_MISC_CFG_CONGESTION_SUSTAIN_TIME_OFFSET 0 +#define RTL8367C_PORT9_MISC_CFG_CONGESTION_SUSTAIN_TIME_MASK 0xF + +#define RTL8367C_REG_INGRESSBW_PORT9_RATE_CTRL0 0x012f + +#define RTL8367C_REG_INGRESSBW_PORT9_RATE_CTRL1 0x0130 +#define RTL8367C_INGRESSBW_PORT9_RATE_CTRL1_DUMMY_OFFSET 3 +#define RTL8367C_INGRESSBW_PORT9_RATE_CTRL1_DUMMY_MASK 0xFFF8 +#define RTL8367C_INGRESSBW_PORT9_RATE_CTRL1_INGRESSBW_RATE16_OFFSET 0 +#define RTL8367C_INGRESSBW_PORT9_RATE_CTRL1_INGRESSBW_RATE16_MASK 0x7 + +#define RTL8367C_REG_PORT9_FORCE_RATE0 0x0131 + +#define RTL8367C_REG_PORT9_FORCE_RATE1 0x0132 + +#define RTL8367C_REG_PORT9_CURENT_RATE0 0x0133 + +#define RTL8367C_REG_PORT9_CURENT_RATE1 0x0134 + +#define RTL8367C_REG_PORT9_PAGE_COUNTER 0x0135 +#define RTL8367C_PORT9_PAGE_COUNTER_OFFSET 0 +#define RTL8367C_PORT9_PAGE_COUNTER_MASK 0x7F + +#define RTL8367C_REG_PAGEMETER_PORT9_CTRL0 0x0136 + +#define RTL8367C_REG_PAGEMETER_PORT9_CTRL1 0x0137 + +#define RTL8367C_REG_PORT9_EEECFG 0x0138 +#define RTL8367C_PORT9_EEECFG_EEEP_ENABLE_TX_OFFSET 14 +#define RTL8367C_PORT9_EEECFG_EEEP_ENABLE_TX_MASK 0x4000 +#define RTL8367C_PORT9_EEECFG_EEEP_ENABLE_RX_OFFSET 13 +#define RTL8367C_PORT9_EEECFG_EEEP_ENABLE_RX_MASK 0x2000 +#define RTL8367C_PORT9_EEECFG_EEE_FORCE_OFFSET 12 +#define RTL8367C_PORT9_EEECFG_EEE_FORCE_MASK 0x1000 +#define RTL8367C_PORT9_EEECFG_EEE_100M_OFFSET 11 +#define RTL8367C_PORT9_EEECFG_EEE_100M_MASK 0x800 +#define RTL8367C_PORT9_EEECFG_EEE_GIGA_500M_OFFSET 10 +#define RTL8367C_PORT9_EEECFG_EEE_GIGA_500M_MASK 0x400 +#define RTL8367C_PORT9_EEECFG_EEE_TX_OFFSET 9 +#define RTL8367C_PORT9_EEECFG_EEE_TX_MASK 0x200 +#define RTL8367C_PORT9_EEECFG_EEE_RX_OFFSET 8 +#define RTL8367C_PORT9_EEECFG_EEE_RX_MASK 0x100 +#define RTL8367C_PORT9_EEECFG_EEE_DSP_RX_OFFSET 6 +#define RTL8367C_PORT9_EEECFG_EEE_DSP_RX_MASK 0x40 +#define RTL8367C_PORT9_EEECFG_EEE_LPI_OFFSET 5 +#define RTL8367C_PORT9_EEECFG_EEE_LPI_MASK 0x20 +#define RTL8367C_PORT9_EEECFG_EEE_TX_LPI_OFFSET 4 +#define RTL8367C_PORT9_EEECFG_EEE_TX_LPI_MASK 0x10 +#define RTL8367C_PORT9_EEECFG_EEE_RX_LPI_OFFSET 3 +#define RTL8367C_PORT9_EEECFG_EEE_RX_LPI_MASK 0x8 +#define RTL8367C_PORT9_EEECFG_EEE_PAUSE_INDICATOR_OFFSET 2 +#define RTL8367C_PORT9_EEECFG_EEE_PAUSE_INDICATOR_MASK 0x4 +#define RTL8367C_PORT9_EEECFG_EEE_WAKE_REQ_OFFSET 1 +#define RTL8367C_PORT9_EEECFG_EEE_WAKE_REQ_MASK 0x2 +#define RTL8367C_PORT9_EEECFG_EEE_SLEEP_REQ_OFFSET 0 +#define RTL8367C_PORT9_EEECFG_EEE_SLEEP_REQ_MASK 0x1 + +#define RTL8367C_REG_PORT9_EEETXMTR 0x0139 + +#define RTL8367C_REG_PORT9_EEERXMTR 0x013a + +#define RTL8367C_REG_PORT9_EEEPTXMTR 0x013b + +#define RTL8367C_REG_PORT9_EEEPRXMTR 0x013c + +#define RTL8367C_REG_PTP_PORT9_CFG1 0x013e +#define RTL8367C_PTP_PORT9_CFG1_OFFSET 7 +#define RTL8367C_PTP_PORT9_CFG1_MASK 0xFF + +#define RTL8367C_REG_P9_MSIC1 0x013f +#define RTL8367C_P9_MSIC1_OFFSET 0 +#define RTL8367C_P9_MSIC1_MASK 0x1 + +#define RTL8367C_REG_PORT10_CGST_HALF_CFG 0x0140 +#define RTL8367C_PORT10_CGST_HALF_CFG_CONGESTION_TIME_OFFSET 4 +#define RTL8367C_PORT10_CGST_HALF_CFG_CONGESTION_TIME_MASK 0xF0 +#define RTL8367C_PORT10_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_OFFSET 0 +#define RTL8367C_PORT10_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_MASK 0xF + +#define RTL8367C_REG_PKTGEN_PORT10_CTRL 0x0141 +#define RTL8367C_PKTGEN_PORT10_CTRL_STATUS_OFFSET 15 +#define RTL8367C_PKTGEN_PORT10_CTRL_STATUS_MASK 0x8000 +#define RTL8367C_PKTGEN_PORT10_CTRL_PKTGEN_STS_OFFSET 13 +#define RTL8367C_PKTGEN_PORT10_CTRL_PKTGEN_STS_MASK 0x2000 +#define RTL8367C_PKTGEN_PORT10_CTRL_CRC_NO_ERROR_OFFSET 4 +#define RTL8367C_PKTGEN_PORT10_CTRL_CRC_NO_ERROR_MASK 0x10 +#define RTL8367C_PKTGEN_PORT10_CTRL_CMD_START_OFFSET 0 +#define RTL8367C_PKTGEN_PORT10_CTRL_CMD_START_MASK 0x1 + +#define RTL8367C_REG_TX_ERR_CNT_PORT10 0x0142 +#define RTL8367C_TX_ERR_CNT_PORT10_OFFSET 0 +#define RTL8367C_TX_ERR_CNT_PORT10_MASK 0x7 + +#define RTL8367C_REG_PKTGEN_PORT10_DA0 0x0143 + +#define RTL8367C_REG_PKTGEN_PORT10_DA1 0x0144 + +#define RTL8367C_REG_PKTGEN_PORT10_DA2 0x0145 + +#define RTL8367C_REG_PKTGEN_PORT10_SA0 0x0146 + +#define RTL8367C_REG_PKTGEN_PORT10_SA1 0x0147 + +#define RTL8367C_REG_PKTGEN_PORT10_SA2 0x0148 + +#define RTL8367C_REG_PKTGEN_PORT10_COUNTER0 0x0149 + +#define RTL8367C_REG_PKTGEN_PORT10_COUNTER1 0x014a +#define RTL8367C_PKTGEN_PORT10_COUNTER1_OFFSET 0 +#define RTL8367C_PKTGEN_PORT10_COUNTER1_MASK 0xFF + +#define RTL8367C_REG_PKTGEN_PORT10_TX_LENGTH 0x014b +#define RTL8367C_PKTGEN_PORT10_TX_LENGTH_OFFSET 0 +#define RTL8367C_PKTGEN_PORT10_TX_LENGTH_MASK 0x3FFF + +#define RTL8367C_REG_PKTGEN_PORT10_TIMER 0x014d +#define RTL8367C_PKTGEN_PORT10_TIMER_TIMER_OFFSET 4 +#define RTL8367C_PKTGEN_PORT10_TIMER_TIMER_MASK 0xF0 +#define RTL8367C_PKTGEN_PORT10_TIMER_RX_DMA_ERR_FLAG_OFFSET 3 +#define RTL8367C_PKTGEN_PORT10_TIMER_RX_DMA_ERR_FLAG_MASK 0x8 + +#define RTL8367C_REG_PORT10_MISC_CFG 0x014e +#define RTL8367C_PORT10_MISC_CFG_SMALL_TAG_IPG_OFFSET 15 +#define RTL8367C_PORT10_MISC_CFG_SMALL_TAG_IPG_MASK 0x8000 +#define RTL8367C_PORT10_MISC_CFG_TX_ITFSP_MODE_OFFSET 14 +#define RTL8367C_PORT10_MISC_CFG_TX_ITFSP_MODE_MASK 0x4000 +#define RTL8367C_PORT10_MISC_CFG_FLOWCTRL_INDEP_OFFSET 13 +#define RTL8367C_PORT10_MISC_CFG_FLOWCTRL_INDEP_MASK 0x2000 +#define RTL8367C_PORT10_MISC_CFG_DOT1Q_REMARK_ENABLE_OFFSET 12 +#define RTL8367C_PORT10_MISC_CFG_DOT1Q_REMARK_ENABLE_MASK 0x1000 +#define RTL8367C_PORT10_MISC_CFG_INGRESSBW_FLOWCTRL_OFFSET 11 +#define RTL8367C_PORT10_MISC_CFG_INGRESSBW_FLOWCTRL_MASK 0x800 +#define RTL8367C_PORT10_MISC_CFG_INGRESSBW_IFG_OFFSET 10 +#define RTL8367C_PORT10_MISC_CFG_INGRESSBW_IFG_MASK 0x400 +#define RTL8367C_PORT10_MISC_CFG_RX_SPC_OFFSET 9 +#define RTL8367C_PORT10_MISC_CFG_RX_SPC_MASK 0x200 +#define RTL8367C_PORT10_MISC_CFG_CRC_SKIP_OFFSET 8 +#define RTL8367C_PORT10_MISC_CFG_CRC_SKIP_MASK 0x100 +#define RTL8367C_PORT10_MISC_CFG_PKTGEN_TX_FIRST_OFFSET 7 +#define RTL8367C_PORT10_MISC_CFG_PKTGEN_TX_FIRST_MASK 0x80 +#define RTL8367C_PORT10_MISC_CFG_MAC_LOOPBACK_OFFSET 6 +#define RTL8367C_PORT10_MISC_CFG_MAC_LOOPBACK_MASK 0x40 +#define RTL8367C_PORT10_MISC_CFG_VLAN_EGRESS_MODE_OFFSET 4 +#define RTL8367C_PORT10_MISC_CFG_VLAN_EGRESS_MODE_MASK 0x30 +#define RTL8367C_PORT10_MISC_CFG_CONGESTION_SUSTAIN_TIME_OFFSET 0 +#define RTL8367C_PORT10_MISC_CFG_CONGESTION_SUSTAIN_TIME_MASK 0xF + +#define RTL8367C_REG_INGRESSBW_PORT10_RATE_CTRL0 0x014f + +#define RTL8367C_REG_INGRESSBW_PORT10_RATE_CTRL1 0x0150 +#define RTL8367C_INGRESSBW_PORT10_RATE_CTRL1_DUMMY_OFFSET 3 +#define RTL8367C_INGRESSBW_PORT10_RATE_CTRL1_DUMMY_MASK 0xFFF8 +#define RTL8367C_INGRESSBW_PORT10_RATE_CTRL1_INGRESSBW_RATE16_OFFSET 0 +#define RTL8367C_INGRESSBW_PORT10_RATE_CTRL1_INGRESSBW_RATE16_MASK 0x7 + +#define RTL8367C_REG_PORT10_FORCE_RATE0 0x0151 + +#define RTL8367C_REG_PORT10_FORCE_RATE1 0x0152 + +#define RTL8367C_REG_PORT10_CURENT_RATE0 0x0153 + +#define RTL8367C_REG_PORT10_CURENT_RATE1 0x0154 + +#define RTL8367C_REG_PORT10_PAGE_COUNTER 0x0155 +#define RTL8367C_PORT10_PAGE_COUNTER_OFFSET 0 +#define RTL8367C_PORT10_PAGE_COUNTER_MASK 0x7F + +#define RTL8367C_REG_PAGEMETER_PORT10_CTRL0 0x0156 + +#define RTL8367C_REG_PAGEMETER_PORT10_CTRL1 0x0157 + +#define RTL8367C_REG_PORT10_EEECFG 0x0158 +#define RTL8367C_PORT10_EEECFG_EEEP_ENABLE_TX_OFFSET 14 +#define RTL8367C_PORT10_EEECFG_EEEP_ENABLE_TX_MASK 0x4000 +#define RTL8367C_PORT10_EEECFG_EEEP_ENABLE_RX_OFFSET 13 +#define RTL8367C_PORT10_EEECFG_EEEP_ENABLE_RX_MASK 0x2000 +#define RTL8367C_PORT10_EEECFG_EEE_FORCE_OFFSET 12 +#define RTL8367C_PORT10_EEECFG_EEE_FORCE_MASK 0x1000 +#define RTL8367C_PORT10_EEECFG_EEE_100M_OFFSET 11 +#define RTL8367C_PORT10_EEECFG_EEE_100M_MASK 0x800 +#define RTL8367C_PORT10_EEECFG_EEE_GIGA_500M_OFFSET 10 +#define RTL8367C_PORT10_EEECFG_EEE_GIGA_500M_MASK 0x400 +#define RTL8367C_PORT10_EEECFG_EEE_TX_OFFSET 9 +#define RTL8367C_PORT10_EEECFG_EEE_TX_MASK 0x200 +#define RTL8367C_PORT10_EEECFG_EEE_RX_OFFSET 8 +#define RTL8367C_PORT10_EEECFG_EEE_RX_MASK 0x100 +#define RTL8367C_PORT10_EEECFG_EEE_DSP_RX_OFFSET 6 +#define RTL8367C_PORT10_EEECFG_EEE_DSP_RX_MASK 0x40 +#define RTL8367C_PORT10_EEECFG_EEE_LPI_OFFSET 5 +#define RTL8367C_PORT10_EEECFG_EEE_LPI_MASK 0x20 +#define RTL8367C_PORT10_EEECFG_EEE_TX_LPI_OFFSET 4 +#define RTL8367C_PORT10_EEECFG_EEE_TX_LPI_MASK 0x10 +#define RTL8367C_PORT10_EEECFG_EEE_RX_LPI_OFFSET 3 +#define RTL8367C_PORT10_EEECFG_EEE_RX_LPI_MASK 0x8 +#define RTL8367C_PORT10_EEECFG_EEE_PAUSE_INDICATOR_OFFSET 2 +#define RTL8367C_PORT10_EEECFG_EEE_PAUSE_INDICATOR_MASK 0x4 +#define RTL8367C_PORT10_EEECFG_EEE_WAKE_REQ_OFFSET 1 +#define RTL8367C_PORT10_EEECFG_EEE_WAKE_REQ_MASK 0x2 +#define RTL8367C_PORT10_EEECFG_EEE_SLEEP_REQ_OFFSET 0 +#define RTL8367C_PORT10_EEECFG_EEE_SLEEP_REQ_MASK 0x1 + +#define RTL8367C_REG_PORT10_EEETXMTR 0x0159 + +#define RTL8367C_REG_PORT10_EEERXMTR 0x015a + +#define RTL8367C_REG_PORT10_EEEPTXMTR 0x015b + +#define RTL8367C_REG_PORT10_EEEPRXMTR 0x015c + +#define RTL8367C_REG_PTP_PORT10_CFG1 0x015e +#define RTL8367C_PTP_PORT10_CFG1_OFFSET 7 +#define RTL8367C_PTP_PORT10_CFG1_MASK 0xFF + +#define RTL8367C_REG_P10_MSIC1 0x015f +#define RTL8367C_P10_MSIC1_OFFSET 0 +#define RTL8367C_P10_MSIC1_MASK 0x1 + +/* (16'h0200)outq_reg */ + +#define RTL8367C_REG_FLOWCTRL_QUEUE0_DROP_ON 0x0200 +#define RTL8367C_FLOWCTRL_QUEUE0_DROP_ON_OFFSET 0 +#define RTL8367C_FLOWCTRL_QUEUE0_DROP_ON_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_QUEUE1_DROP_ON 0x0201 +#define RTL8367C_FLOWCTRL_QUEUE1_DROP_ON_OFFSET 0 +#define RTL8367C_FLOWCTRL_QUEUE1_DROP_ON_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_QUEUE2_DROP_ON 0x0202 +#define RTL8367C_FLOWCTRL_QUEUE2_DROP_ON_OFFSET 0 +#define RTL8367C_FLOWCTRL_QUEUE2_DROP_ON_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_QUEUE3_DROP_ON 0x0203 +#define RTL8367C_FLOWCTRL_QUEUE3_DROP_ON_OFFSET 0 +#define RTL8367C_FLOWCTRL_QUEUE3_DROP_ON_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_QUEUE4_DROP_ON 0x0204 +#define RTL8367C_FLOWCTRL_QUEUE4_DROP_ON_OFFSET 0 +#define RTL8367C_FLOWCTRL_QUEUE4_DROP_ON_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_QUEUE5_DROP_ON 0x0205 +#define RTL8367C_FLOWCTRL_QUEUE5_DROP_ON_OFFSET 0 +#define RTL8367C_FLOWCTRL_QUEUE5_DROP_ON_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_QUEUE6_DROP_ON 0x0206 +#define RTL8367C_FLOWCTRL_QUEUE6_DROP_ON_OFFSET 0 +#define RTL8367C_FLOWCTRL_QUEUE6_DROP_ON_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_QUEUE7_DROP_ON 0x0207 +#define RTL8367C_FLOWCTRL_QUEUE7_DROP_ON_OFFSET 0 +#define RTL8367C_FLOWCTRL_QUEUE7_DROP_ON_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_PORT0_DROP_ON 0x0208 +#define RTL8367C_FLOWCTRL_PORT0_DROP_ON_OFFSET 0 +#define RTL8367C_FLOWCTRL_PORT0_DROP_ON_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_PORT1_DROP_ON 0x0209 +#define RTL8367C_FLOWCTRL_PORT1_DROP_ON_OFFSET 0 +#define RTL8367C_FLOWCTRL_PORT1_DROP_ON_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_PORT2_DROP_ON 0x020a +#define RTL8367C_FLOWCTRL_PORT2_DROP_ON_OFFSET 0 +#define RTL8367C_FLOWCTRL_PORT2_DROP_ON_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_PORT3_DROP_ON 0x020b +#define RTL8367C_FLOWCTRL_PORT3_DROP_ON_OFFSET 0 +#define RTL8367C_FLOWCTRL_PORT3_DROP_ON_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_PORT4_DROP_ON 0x020c +#define RTL8367C_FLOWCTRL_PORT4_DROP_ON_OFFSET 0 +#define RTL8367C_FLOWCTRL_PORT4_DROP_ON_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_PORT5_DROP_ON 0x020d +#define RTL8367C_FLOWCTRL_PORT5_DROP_ON_OFFSET 0 +#define RTL8367C_FLOWCTRL_PORT5_DROP_ON_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_PORT6_DROP_ON 0x020e +#define RTL8367C_FLOWCTRL_PORT6_DROP_ON_OFFSET 0 +#define RTL8367C_FLOWCTRL_PORT6_DROP_ON_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_PORT7_DROP_ON 0x020f +#define RTL8367C_FLOWCTRL_PORT7_DROP_ON_OFFSET 0 +#define RTL8367C_FLOWCTRL_PORT7_DROP_ON_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_PORT8_DROP_ON 0x0210 +#define RTL8367C_FLOWCTRL_PORT8_DROP_ON_OFFSET 0 +#define RTL8367C_FLOWCTRL_PORT8_DROP_ON_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_PORT9_DROP_ON 0x0211 +#define RTL8367C_FLOWCTRL_PORT9_DROP_ON_OFFSET 0 +#define RTL8367C_FLOWCTRL_PORT9_DROP_ON_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_PORT10_DROP_ON 0x0212 +#define RTL8367C_FLOWCTRL_PORT10_DROP_ON_OFFSET 0 +#define RTL8367C_FLOWCTRL_PORT10_DROP_ON_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_PORT_GAP 0x0218 +#define RTL8367C_FLOWCTRL_PORT_GAP_OFFSET 0 +#define RTL8367C_FLOWCTRL_PORT_GAP_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_QUEUE_GAP 0x0219 +#define RTL8367C_FLOWCTRL_QUEUE_GAP_OFFSET 0 +#define RTL8367C_FLOWCTRL_QUEUE_GAP_MASK 0x7FF + +#define RTL8367C_REG_PORT_QEMPTY 0x022d +#define RTL8367C_PORT_QEMPTY_OFFSET 0 +#define RTL8367C_PORT_QEMPTY_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_DEBUG_CTRL0 0x022e +#define RTL8367C_FLOWCTRL_DEBUG_CTRL0_OFFSET 0 +#define RTL8367C_FLOWCTRL_DEBUG_CTRL0_MASK 0xF + +#define RTL8367C_REG_FLOWCTRL_DEBUG_CTRL1 0x022f +#define RTL8367C_TOTAL_OFFSET 9 +#define RTL8367C_TOTAL_MASK 0x200 +#define RTL8367C_PORT_MAX_OFFSET 8 +#define RTL8367C_PORT_MAX_MASK 0x100 +#define RTL8367C_QMAX_MASK_OFFSET 0 +#define RTL8367C_QMAX_MASK_MASK 0xFF + +#define RTL8367C_REG_FLOWCTRL_QUEUE0_PAGE_COUNT 0x0230 +#define RTL8367C_FLOWCTRL_QUEUE0_PAGE_COUNT_OFFSET 0 +#define RTL8367C_FLOWCTRL_QUEUE0_PAGE_COUNT_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_QUEUE1_PAGE_COUNT 0x0231 +#define RTL8367C_FLOWCTRL_QUEUE1_PAGE_COUNT_OFFSET 0 +#define RTL8367C_FLOWCTRL_QUEUE1_PAGE_COUNT_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_QUEUE2_PAGE_COUNT 0x0232 +#define RTL8367C_FLOWCTRL_QUEUE2_PAGE_COUNT_OFFSET 0 +#define RTL8367C_FLOWCTRL_QUEUE2_PAGE_COUNT_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_QUEUE3_PAGE_COUNT 0x0233 +#define RTL8367C_FLOWCTRL_QUEUE3_PAGE_COUNT_OFFSET 0 +#define RTL8367C_FLOWCTRL_QUEUE3_PAGE_COUNT_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_QUEUE4_PAGE_COUNT 0x0234 +#define RTL8367C_FLOWCTRL_QUEUE4_PAGE_COUNT_OFFSET 0 +#define RTL8367C_FLOWCTRL_QUEUE4_PAGE_COUNT_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_QUEUE5_PAGE_COUNT 0x0235 +#define RTL8367C_FLOWCTRL_QUEUE5_PAGE_COUNT_OFFSET 0 +#define RTL8367C_FLOWCTRL_QUEUE5_PAGE_COUNT_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_QUEUE6_PAGE_COUNT 0x0236 +#define RTL8367C_FLOWCTRL_QUEUE6_PAGE_COUNT_OFFSET 0 +#define RTL8367C_FLOWCTRL_QUEUE6_PAGE_COUNT_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_QUEUE7_PAGE_COUNT 0x0237 +#define RTL8367C_FLOWCTRL_QUEUE7_PAGE_COUNT_OFFSET 0 +#define RTL8367C_FLOWCTRL_QUEUE7_PAGE_COUNT_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_PORT_PAGE_COUNT 0x0238 +#define RTL8367C_FLOWCTRL_PORT_PAGE_COUNT_OFFSET 0 +#define RTL8367C_FLOWCTRL_PORT_PAGE_COUNT_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_QUEUE0_MAX_PAGE_COUNT 0x0239 +#define RTL8367C_FLOWCTRL_QUEUE0_MAX_PAGE_COUNT_OFFSET 0 +#define RTL8367C_FLOWCTRL_QUEUE0_MAX_PAGE_COUNT_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_QUEUE1_MAX_PAGE_COUNT 0x023a +#define RTL8367C_FLOWCTRL_QUEUE1_MAX_PAGE_COUNT_OFFSET 0 +#define RTL8367C_FLOWCTRL_QUEUE1_MAX_PAGE_COUNT_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_QUEUE2_MAX_PAGE_COUNT 0x023b +#define RTL8367C_FLOWCTRL_QUEUE2_MAX_PAGE_COUNT_OFFSET 0 +#define RTL8367C_FLOWCTRL_QUEUE2_MAX_PAGE_COUNT_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_QUEUE3_MAX_PAGE_COUNT 0x023c +#define RTL8367C_FLOWCTRL_QUEUE3_MAX_PAGE_COUNT_OFFSET 0 +#define RTL8367C_FLOWCTRL_QUEUE3_MAX_PAGE_COUNT_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_QUEUE4_MAX_PAGE_COUNT 0x023d +#define RTL8367C_FLOWCTRL_QUEUE4_MAX_PAGE_COUNT_OFFSET 0 +#define RTL8367C_FLOWCTRL_QUEUE4_MAX_PAGE_COUNT_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_QUEUE5_MAX_PAGE_COUNT 0x023e +#define RTL8367C_FLOWCTRL_QUEUE5_MAX_PAGE_COUNT_OFFSET 0 +#define RTL8367C_FLOWCTRL_QUEUE5_MAX_PAGE_COUNT_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_QUEUE6_MAX_PAGE_COUNT 0x023f +#define RTL8367C_FLOWCTRL_QUEUE6_MAX_PAGE_COUNT_OFFSET 0 +#define RTL8367C_FLOWCTRL_QUEUE6_MAX_PAGE_COUNT_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_QUEUE7_MAX_PAGE_COUNT 0x0240 +#define RTL8367C_FLOWCTRL_QUEUE7_MAX_PAGE_COUNT_OFFSET 0 +#define RTL8367C_FLOWCTRL_QUEUE7_MAX_PAGE_COUNT_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_PORT_MAX_PAGE_COUNT 0x0241 +#define RTL8367C_FLOWCTRL_PORT_MAX_PAGE_COUNT_OFFSET 0 +#define RTL8367C_FLOWCTRL_PORT_MAX_PAGE_COUNT_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_TOTAL_PACKET_COUNT 0x0243 + +#define RTL8367C_REG_HIGH_QUEUE_MASK0 0x0244 +#define RTL8367C_PORT1_HIGH_QUEUE_MASK_OFFSET 8 +#define RTL8367C_PORT1_HIGH_QUEUE_MASK_MASK 0xFF00 +#define RTL8367C_PORT0_HIGH_QUEUE_MASK_OFFSET 0 +#define RTL8367C_PORT0_HIGH_QUEUE_MASK_MASK 0xFF + +#define RTL8367C_REG_HIGH_QUEUE_MASK1 0x0245 +#define RTL8367C_PORT3_HIGH_QUEUE_MASK_OFFSET 8 +#define RTL8367C_PORT3_HIGH_QUEUE_MASK_MASK 0xFF00 +#define RTL8367C_PORT2_HIGH_QUEUE_MASK_OFFSET 0 +#define RTL8367C_PORT2_HIGH_QUEUE_MASK_MASK 0xFF + +#define RTL8367C_REG_HIGH_QUEUE_MASK2 0x0246 +#define RTL8367C_PORT5_HIGH_QUEUE_MASK_OFFSET 8 +#define RTL8367C_PORT5_HIGH_QUEUE_MASK_MASK 0xFF00 +#define RTL8367C_PORT4_HIGH_QUEUE_MASK_OFFSET 0 +#define RTL8367C_PORT4_HIGH_QUEUE_MASK_MASK 0xFF + +#define RTL8367C_REG_HIGH_QUEUE_MASK3 0x0247 +#define RTL8367C_PORT7_HIGH_QUEUE_MASK_OFFSET 8 +#define RTL8367C_PORT7_HIGH_QUEUE_MASK_MASK 0xFF00 +#define RTL8367C_PORT6_HIGH_QUEUE_MASK_OFFSET 0 +#define RTL8367C_PORT6_HIGH_QUEUE_MASK_MASK 0xFF + +#define RTL8367C_REG_HIGH_QUEUE_MASK4 0x0248 +#define RTL8367C_PORT9_HIGH_QUEUE_MASK_OFFSET 8 +#define RTL8367C_PORT9_HIGH_QUEUE_MASK_MASK 0xFF00 +#define RTL8367C_PORT8_HIGH_QUEUE_MASK_OFFSET 0 +#define RTL8367C_PORT8_HIGH_QUEUE_MASK_MASK 0xFF + +#define RTL8367C_REG_HIGH_QUEUE_MASK5 0x0249 +#define RTL8367C_HIGH_QUEUE_MASK5_OFFSET 0 +#define RTL8367C_HIGH_QUEUE_MASK5_MASK 0xFF + +#define RTL8367C_REG_LOW_QUEUE_TH 0x024c +#define RTL8367C_LOW_QUEUE_TH_OFFSET 0 +#define RTL8367C_LOW_QUEUE_TH_MASK 0x7FF + +#define RTL8367C_REG_TH_TX_PREFET 0x0250 +#define RTL8367C_TH_TX_PREFET_OFFSET 0 +#define RTL8367C_TH_TX_PREFET_MASK 0xFF + +#define RTL8367C_REG_DUMMY_0251 0x0251 + +#define RTL8367C_REG_DUMMY_0252 0x0252 + +#define RTL8367C_REG_DUMMY_0253 0x0253 + +#define RTL8367C_REG_DUMMY_0254 0x0254 + +#define RTL8367C_REG_DUMMY_0255 0x0255 + +#define RTL8367C_REG_DUMMY_0256 0x0256 + +#define RTL8367C_REG_DUMMY_0257 0x0257 + +#define RTL8367C_REG_DUMMY_0258 0x0258 + +#define RTL8367C_REG_DUMMY_0259 0x0259 + +#define RTL8367C_REG_DUMMY_025A 0x025A + +#define RTL8367C_REG_DUMMY_025B 0x025B + +#define RTL8367C_REG_DUMMY_025C 0x025C + +#define RTL8367C_REG_Q_TXPKT_CNT_CTL 0x025d +#define RTL8367C_QUEUE_PKT_CNT_CLR_OFFSET 4 +#define RTL8367C_QUEUE_PKT_CNT_CLR_MASK 0x10 +#define RTL8367C_PORT_ID_QUEUE_PKT_CNT_OFFSET 0 +#define RTL8367C_PORT_ID_QUEUE_PKT_CNT_MASK 0xF + +#define RTL8367C_REG_Q0_TXPKT_CNT_L 0x025e + +#define RTL8367C_REG_Q0_TXPKT_CNT_H 0x025f + +#define RTL8367C_REG_Q1_TXPKT_CNT_L 0x0260 + +#define RTL8367C_REG_Q1_TXPKT_CNT_H 0x0261 + +#define RTL8367C_REG_Q2_TXPKT_CNT_L 0x0262 + +#define RTL8367C_REG_Q2_TXPKT_CNT_H 0x0263 + +#define RTL8367C_REG_Q3_TXPKT_CNT_L 0x0264 + +#define RTL8367C_REG_Q3_TXPKT_CNT_H 0x0265 + +#define RTL8367C_REG_Q4_TXPKT_CNT_L 0x0266 + +#define RTL8367C_REG_Q4_TXPKT_CNT_H 0x0267 + +#define RTL8367C_REG_Q5_TXPKT_CNT_L 0x0268 + +#define RTL8367C_REG_Q5_TXPKT_CNT_H 0x0269 + +#define RTL8367C_REG_Q6_TXPKT_CNT_L 0x026a + +#define RTL8367C_REG_Q6_TXPKT_CNT_H 0x026b + +#define RTL8367C_REG_Q7_TXPKT_CNT_L 0x026c + +#define RTL8367C_REG_Q7_TXPKT_CNT_H 0x026d + +/* (16'h0300)sch_reg */ + +#define RTL8367C_REG_SCHEDULE_WFQ_CTRL 0x0300 +#define RTL8367C_SCHEDULE_WFQ_CTRL_OFFSET 0 +#define RTL8367C_SCHEDULE_WFQ_CTRL_MASK 0x1 + +#define RTL8367C_REG_SCHEDULE_WFQ_BURST_SIZE 0x0301 + +#define RTL8367C_REG_SCHEDULE_QUEUE_TYPE_CTRL0 0x0302 +#define RTL8367C_PORT1_QUEUE7_TYPE_OFFSET 15 +#define RTL8367C_PORT1_QUEUE7_TYPE_MASK 0x8000 +#define RTL8367C_PORT1_QUEUE6_TYPE_OFFSET 14 +#define RTL8367C_PORT1_QUEUE6_TYPE_MASK 0x4000 +#define RTL8367C_PORT1_QUEUE5_TYPE_OFFSET 13 +#define RTL8367C_PORT1_QUEUE5_TYPE_MASK 0x2000 +#define RTL8367C_PORT1_QUEUE4_TYPE_OFFSET 12 +#define RTL8367C_PORT1_QUEUE4_TYPE_MASK 0x1000 +#define RTL8367C_PORT1_QUEUE3_TYPE_OFFSET 11 +#define RTL8367C_PORT1_QUEUE3_TYPE_MASK 0x800 +#define RTL8367C_PORT1_QUEUE2_TYPE_OFFSET 10 +#define RTL8367C_PORT1_QUEUE2_TYPE_MASK 0x400 +#define RTL8367C_PORT1_QUEUE1_TYPE_OFFSET 9 +#define RTL8367C_PORT1_QUEUE1_TYPE_MASK 0x200 +#define RTL8367C_PORT1_QUEUE0_TYPE_OFFSET 8 +#define RTL8367C_PORT1_QUEUE0_TYPE_MASK 0x100 +#define RTL8367C_PORT0_QUEUE7_TYPE_OFFSET 7 +#define RTL8367C_PORT0_QUEUE7_TYPE_MASK 0x80 +#define RTL8367C_PORT0_QUEUE6_TYPE_OFFSET 6 +#define RTL8367C_PORT0_QUEUE6_TYPE_MASK 0x40 +#define RTL8367C_PORT0_QUEUE5_TYPE_OFFSET 5 +#define RTL8367C_PORT0_QUEUE5_TYPE_MASK 0x20 +#define RTL8367C_PORT0_QUEUE4_TYPE_OFFSET 4 +#define RTL8367C_PORT0_QUEUE4_TYPE_MASK 0x10 +#define RTL8367C_PORT0_QUEUE3_TYPE_OFFSET 3 +#define RTL8367C_PORT0_QUEUE3_TYPE_MASK 0x8 +#define RTL8367C_PORT0_QUEUE2_TYPE_OFFSET 2 +#define RTL8367C_PORT0_QUEUE2_TYPE_MASK 0x4 +#define RTL8367C_PORT0_QUEUE1_TYPE_OFFSET 1 +#define RTL8367C_PORT0_QUEUE1_TYPE_MASK 0x2 +#define RTL8367C_PORT0_QUEUE0_TYPE_OFFSET 0 +#define RTL8367C_PORT0_QUEUE0_TYPE_MASK 0x1 + +#define RTL8367C_REG_SCHEDULE_QUEUE_TYPE_CTRL1 0x0303 +#define RTL8367C_PORT3_QUEUE7_TYPE_OFFSET 15 +#define RTL8367C_PORT3_QUEUE7_TYPE_MASK 0x8000 +#define RTL8367C_PORT3_QUEUE6_TYPE_OFFSET 14 +#define RTL8367C_PORT3_QUEUE6_TYPE_MASK 0x4000 +#define RTL8367C_PORT3_QUEUE5_TYPE_OFFSET 13 +#define RTL8367C_PORT3_QUEUE5_TYPE_MASK 0x2000 +#define RTL8367C_PORT3_QUEUE4_TYPE_OFFSET 12 +#define RTL8367C_PORT3_QUEUE4_TYPE_MASK 0x1000 +#define RTL8367C_PORT3_QUEUE3_TYPE_OFFSET 11 +#define RTL8367C_PORT3_QUEUE3_TYPE_MASK 0x800 +#define RTL8367C_PORT3_QUEUE2_TYPE_OFFSET 10 +#define RTL8367C_PORT3_QUEUE2_TYPE_MASK 0x400 +#define RTL8367C_PORT3_QUEUE1_TYPE_OFFSET 9 +#define RTL8367C_PORT3_QUEUE1_TYPE_MASK 0x200 +#define RTL8367C_PORT3_QUEUE0_TYPE_OFFSET 8 +#define RTL8367C_PORT3_QUEUE0_TYPE_MASK 0x100 +#define RTL8367C_PORT2_QUEUE7_TYPE_OFFSET 7 +#define RTL8367C_PORT2_QUEUE7_TYPE_MASK 0x80 +#define RTL8367C_PORT2_QUEUE6_TYPE_OFFSET 6 +#define RTL8367C_PORT2_QUEUE6_TYPE_MASK 0x40 +#define RTL8367C_PORT2_QUEUE5_TYPE_OFFSET 5 +#define RTL8367C_PORT2_QUEUE5_TYPE_MASK 0x20 +#define RTL8367C_PORT2_QUEUE4_TYPE_OFFSET 4 +#define RTL8367C_PORT2_QUEUE4_TYPE_MASK 0x10 +#define RTL8367C_PORT2_QUEUE3_TYPE_OFFSET 3 +#define RTL8367C_PORT2_QUEUE3_TYPE_MASK 0x8 +#define RTL8367C_PORT2_QUEUE2_TYPE_OFFSET 2 +#define RTL8367C_PORT2_QUEUE2_TYPE_MASK 0x4 +#define RTL8367C_PORT2_QUEUE1_TYPE_OFFSET 1 +#define RTL8367C_PORT2_QUEUE1_TYPE_MASK 0x2 +#define RTL8367C_PORT2_QUEUE0_TYPE_OFFSET 0 +#define RTL8367C_PORT2_QUEUE0_TYPE_MASK 0x1 + +#define RTL8367C_REG_SCHEDULE_QUEUE_TYPE_CTRL2 0x0304 +#define RTL8367C_PORT5_QUEUE7_TYPE_OFFSET 15 +#define RTL8367C_PORT5_QUEUE7_TYPE_MASK 0x8000 +#define RTL8367C_PORT5_QUEUE6_TYPE_OFFSET 14 +#define RTL8367C_PORT5_QUEUE6_TYPE_MASK 0x4000 +#define RTL8367C_PORT5_QUEUE5_TYPE_OFFSET 13 +#define RTL8367C_PORT5_QUEUE5_TYPE_MASK 0x2000 +#define RTL8367C_PORT5_QUEUE4_TYPE_OFFSET 12 +#define RTL8367C_PORT5_QUEUE4_TYPE_MASK 0x1000 +#define RTL8367C_PORT5_QUEUE3_TYPE_OFFSET 11 +#define RTL8367C_PORT5_QUEUE3_TYPE_MASK 0x800 +#define RTL8367C_PORT5_QUEUE2_TYPE_OFFSET 10 +#define RTL8367C_PORT5_QUEUE2_TYPE_MASK 0x400 +#define RTL8367C_PORT5_QUEUE1_TYPE_OFFSET 9 +#define RTL8367C_PORT5_QUEUE1_TYPE_MASK 0x200 +#define RTL8367C_PORT5_QUEUE0_TYPE_OFFSET 8 +#define RTL8367C_PORT5_QUEUE0_TYPE_MASK 0x100 +#define RTL8367C_PORT4_QUEUE7_TYPE_OFFSET 7 +#define RTL8367C_PORT4_QUEUE7_TYPE_MASK 0x80 +#define RTL8367C_PORT4_QUEUE6_TYPE_OFFSET 6 +#define RTL8367C_PORT4_QUEUE6_TYPE_MASK 0x40 +#define RTL8367C_PORT4_QUEUE5_TYPE_OFFSET 5 +#define RTL8367C_PORT4_QUEUE5_TYPE_MASK 0x20 +#define RTL8367C_PORT4_QUEUE4_TYPE_OFFSET 4 +#define RTL8367C_PORT4_QUEUE4_TYPE_MASK 0x10 +#define RTL8367C_PORT4_QUEUE3_TYPE_OFFSET 3 +#define RTL8367C_PORT4_QUEUE3_TYPE_MASK 0x8 +#define RTL8367C_PORT4_QUEUE2_TYPE_OFFSET 2 +#define RTL8367C_PORT4_QUEUE2_TYPE_MASK 0x4 +#define RTL8367C_PORT4_QUEUE1_TYPE_OFFSET 1 +#define RTL8367C_PORT4_QUEUE1_TYPE_MASK 0x2 +#define RTL8367C_PORT4_QUEUE0_TYPE_OFFSET 0 +#define RTL8367C_PORT4_QUEUE0_TYPE_MASK 0x1 + +#define RTL8367C_REG_SCHEDULE_QUEUE_TYPE_CTRL3 0x0305 +#define RTL8367C_PORT7_QUEUE7_TYPE_OFFSET 15 +#define RTL8367C_PORT7_QUEUE7_TYPE_MASK 0x8000 +#define RTL8367C_PORT7_QUEUE6_TYPE_OFFSET 14 +#define RTL8367C_PORT7_QUEUE6_TYPE_MASK 0x4000 +#define RTL8367C_PORT7_QUEUE5_TYPE_OFFSET 13 +#define RTL8367C_PORT7_QUEUE5_TYPE_MASK 0x2000 +#define RTL8367C_PORT7_QUEUE4_TYPE_OFFSET 12 +#define RTL8367C_PORT7_QUEUE4_TYPE_MASK 0x1000 +#define RTL8367C_PORT7_QUEUE3_TYPE_OFFSET 11 +#define RTL8367C_PORT7_QUEUE3_TYPE_MASK 0x800 +#define RTL8367C_PORT7_QUEUE2_TYPE_OFFSET 10 +#define RTL8367C_PORT7_QUEUE2_TYPE_MASK 0x400 +#define RTL8367C_PORT7_QUEUE1_TYPE_OFFSET 9 +#define RTL8367C_PORT7_QUEUE1_TYPE_MASK 0x200 +#define RTL8367C_PORT7_QUEUE0_TYPE_OFFSET 8 +#define RTL8367C_PORT7_QUEUE0_TYPE_MASK 0x100 +#define RTL8367C_PORT6_QUEUE7_TYPE_OFFSET 7 +#define RTL8367C_PORT6_QUEUE7_TYPE_MASK 0x80 +#define RTL8367C_PORT6_QUEUE6_TYPE_OFFSET 6 +#define RTL8367C_PORT6_QUEUE6_TYPE_MASK 0x40 +#define RTL8367C_PORT6_QUEUE5_TYPE_OFFSET 5 +#define RTL8367C_PORT6_QUEUE5_TYPE_MASK 0x20 +#define RTL8367C_PORT6_QUEUE4_TYPE_OFFSET 4 +#define RTL8367C_PORT6_QUEUE4_TYPE_MASK 0x10 +#define RTL8367C_PORT6_QUEUE3_TYPE_OFFSET 3 +#define RTL8367C_PORT6_QUEUE3_TYPE_MASK 0x8 +#define RTL8367C_PORT6_QUEUE2_TYPE_OFFSET 2 +#define RTL8367C_PORT6_QUEUE2_TYPE_MASK 0x4 +#define RTL8367C_PORT6_QUEUE1_TYPE_OFFSET 1 +#define RTL8367C_PORT6_QUEUE1_TYPE_MASK 0x2 +#define RTL8367C_SCHEDULE_QUEUE_TYPE_CTRL3_PORT6_QUEUE0_TYPE_OFFSET 0 +#define RTL8367C_SCHEDULE_QUEUE_TYPE_CTRL3_PORT6_QUEUE0_TYPE_MASK 0x1 + +#define RTL8367C_REG_SCHEDULE_QUEUE_TYPE_CTRL4 0x0306 +#define RTL8367C_PORT9_QUEUE7_TYPE_OFFSET 15 +#define RTL8367C_PORT9_QUEUE7_TYPE_MASK 0x8000 +#define RTL8367C_PORT9_QUEUE6_TYPE_OFFSET 14 +#define RTL8367C_PORT9_QUEUE6_TYPE_MASK 0x4000 +#define RTL8367C_PORT9_QUEUE5_TYPE_OFFSET 13 +#define RTL8367C_PORT9_QUEUE5_TYPE_MASK 0x2000 +#define RTL8367C_PORT9_QUEUE4_TYPE_OFFSET 12 +#define RTL8367C_PORT9_QUEUE4_TYPE_MASK 0x1000 +#define RTL8367C_PORT9_QUEUE3_TYPE_OFFSET 11 +#define RTL8367C_PORT9_QUEUE3_TYPE_MASK 0x800 +#define RTL8367C_PORT9_QUEUE2_TYPE_OFFSET 10 +#define RTL8367C_PORT9_QUEUE2_TYPE_MASK 0x400 +#define RTL8367C_PORT9_QUEUE1_TYPE_OFFSET 9 +#define RTL8367C_PORT9_QUEUE1_TYPE_MASK 0x200 +#define RTL8367C_PORT9_QUEUE0_TYPE_OFFSET 8 +#define RTL8367C_PORT9_QUEUE0_TYPE_MASK 0x100 +#define RTL8367C_PORT8_QUEUE7_TYPE_OFFSET 7 +#define RTL8367C_PORT8_QUEUE7_TYPE_MASK 0x80 +#define RTL8367C_PORT8_QUEUE6_TYPE_OFFSET 6 +#define RTL8367C_PORT8_QUEUE6_TYPE_MASK 0x40 +#define RTL8367C_PORT8_QUEUE5_TYPE_OFFSET 5 +#define RTL8367C_PORT8_QUEUE5_TYPE_MASK 0x20 +#define RTL8367C_PORT8_QUEUE4_TYPE_OFFSET 4 +#define RTL8367C_PORT8_QUEUE4_TYPE_MASK 0x10 +#define RTL8367C_PORT8_QUEUE3_TYPE_OFFSET 3 +#define RTL8367C_PORT8_QUEUE3_TYPE_MASK 0x8 +#define RTL8367C_PORT8_QUEUE2_TYPE_OFFSET 2 +#define RTL8367C_PORT8_QUEUE2_TYPE_MASK 0x4 +#define RTL8367C_PORT8_QUEUE1_TYPE_OFFSET 1 +#define RTL8367C_PORT8_QUEUE1_TYPE_MASK 0x2 +#define RTL8367C_SCHEDULE_QUEUE_TYPE_CTRL4_PORT6_QUEUE0_TYPE_OFFSET 0 +#define RTL8367C_SCHEDULE_QUEUE_TYPE_CTRL4_PORT6_QUEUE0_TYPE_MASK 0x1 + +#define RTL8367C_REG_SCHEDULE_QUEUE_TYPE_CTRL5 0x0307 +#define RTL8367C_PORT10_QUEUE7_TYPE_OFFSET 7 +#define RTL8367C_PORT10_QUEUE7_TYPE_MASK 0x80 +#define RTL8367C_PORT10_QUEUE6_TYPE_OFFSET 6 +#define RTL8367C_PORT10_QUEUE6_TYPE_MASK 0x40 +#define RTL8367C_PORT10_QUEUE5_TYPE_OFFSET 5 +#define RTL8367C_PORT10_QUEUE5_TYPE_MASK 0x20 +#define RTL8367C_PORT10_QUEUE4_TYPE_OFFSET 4 +#define RTL8367C_PORT10_QUEUE4_TYPE_MASK 0x10 +#define RTL8367C_PORT10_QUEUE3_TYPE_OFFSET 3 +#define RTL8367C_PORT10_QUEUE3_TYPE_MASK 0x8 +#define RTL8367C_PORT10_QUEUE2_TYPE_OFFSET 2 +#define RTL8367C_PORT10_QUEUE2_TYPE_MASK 0x4 +#define RTL8367C_PORT10_QUEUE1_TYPE_OFFSET 1 +#define RTL8367C_PORT10_QUEUE1_TYPE_MASK 0x2 +#define RTL8367C_PORT10_QUEUE0_TYPE_OFFSET 0 +#define RTL8367C_PORT10_QUEUE0_TYPE_MASK 0x1 + +#define RTL8367C_REG_SCHEDULE_APR_CTRL0 0x030a +#define RTL8367C_PORT10_APR_ENABLE_OFFSET 10 +#define RTL8367C_PORT10_APR_ENABLE_MASK 0x400 +#define RTL8367C_PORT9_APR_ENABLE_OFFSET 9 +#define RTL8367C_PORT9_APR_ENABLE_MASK 0x200 +#define RTL8367C_PORT8_APR_ENABLE_OFFSET 8 +#define RTL8367C_PORT8_APR_ENABLE_MASK 0x100 +#define RTL8367C_PORT7_APR_ENABLE_OFFSET 7 +#define RTL8367C_PORT7_APR_ENABLE_MASK 0x80 +#define RTL8367C_PORT6_APR_ENABLE_OFFSET 6 +#define RTL8367C_PORT6_APR_ENABLE_MASK 0x40 +#define RTL8367C_PORT5_APR_ENABLE_OFFSET 5 +#define RTL8367C_PORT5_APR_ENABLE_MASK 0x20 +#define RTL8367C_PORT4_APR_ENABLE_OFFSET 4 +#define RTL8367C_PORT4_APR_ENABLE_MASK 0x10 +#define RTL8367C_PORT3_APR_ENABLE_OFFSET 3 +#define RTL8367C_PORT3_APR_ENABLE_MASK 0x8 +#define RTL8367C_PORT2_APR_ENABLE_OFFSET 2 +#define RTL8367C_PORT2_APR_ENABLE_MASK 0x4 +#define RTL8367C_PORT1_APR_ENABLE_OFFSET 1 +#define RTL8367C_PORT1_APR_ENABLE_MASK 0x2 +#define RTL8367C_PORT0_APR_ENABLE_OFFSET 0 +#define RTL8367C_PORT0_APR_ENABLE_MASK 0x1 + +#define RTL8367C_REG_SCHEDULE_PORT0_QUEUE0_WFQ_WEIGHT 0x030c + +#define RTL8367C_REG_SCHEDULE_PORT0_QUEUE1_WFQ_WEIGHT 0x030d +#define RTL8367C_SCHEDULE_PORT0_QUEUE1_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT0_QUEUE1_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT0_QUEUE2_WFQ_WEIGHT 0x030e +#define RTL8367C_SCHEDULE_PORT0_QUEUE2_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT0_QUEUE2_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT0_QUEUE3_WFQ_WEIGHT 0x030f +#define RTL8367C_SCHEDULE_PORT0_QUEUE3_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT0_QUEUE3_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT0_QUEUE4_WFQ_WEIGHT 0x0310 +#define RTL8367C_SCHEDULE_PORT0_QUEUE4_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT0_QUEUE4_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT0_QUEUE5_WFQ_WEIGHT 0x0311 +#define RTL8367C_SCHEDULE_PORT0_QUEUE5_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT0_QUEUE5_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT0_QUEUE6_WFQ_WEIGHT 0x0312 +#define RTL8367C_SCHEDULE_PORT0_QUEUE6_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT0_QUEUE6_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT0_QUEUE7_WFQ_WEIGHT 0x0313 +#define RTL8367C_SCHEDULE_PORT0_QUEUE7_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT0_QUEUE7_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT1_QUEUE0_WFQ_WEIGHT 0x0314 + +#define RTL8367C_REG_SCHEDULE_PORT1_QUEUE1_WFQ_WEIGHT 0x0315 +#define RTL8367C_SCHEDULE_PORT1_QUEUE1_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT1_QUEUE1_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT1_QUEUE2_WFQ_WEIGHT 0x0316 +#define RTL8367C_SCHEDULE_PORT1_QUEUE2_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT1_QUEUE2_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT1_QUEUE3_WFQ_WEIGHT 0x0317 +#define RTL8367C_SCHEDULE_PORT1_QUEUE3_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT1_QUEUE3_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT1_QUEUE4_WFQ_WEIGHT 0x0318 +#define RTL8367C_SCHEDULE_PORT1_QUEUE4_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT1_QUEUE4_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT1_QUEUE5_WFQ_WEIGHT 0x0319 +#define RTL8367C_SCHEDULE_PORT1_QUEUE5_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT1_QUEUE5_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT1_QUEUE6_WFQ_WEIGHT 0x031a +#define RTL8367C_SCHEDULE_PORT1_QUEUE6_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT1_QUEUE6_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT1_QUEUE7_WFQ_WEIGHT 0x031b +#define RTL8367C_SCHEDULE_PORT1_QUEUE7_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT1_QUEUE7_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT2_QUEUE0_WFQ_WEIGHT 0x031c + +#define RTL8367C_REG_SCHEDULE_PORT2_QUEUE1_WFQ_WEIGHT 0x031d +#define RTL8367C_SCHEDULE_PORT2_QUEUE1_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT2_QUEUE1_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT2_QUEUE2_WFQ_WEIGHT 0x031e +#define RTL8367C_SCHEDULE_PORT2_QUEUE2_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT2_QUEUE2_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT2_QUEUE3_WFQ_WEIGHT 0x031f +#define RTL8367C_SCHEDULE_PORT2_QUEUE3_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT2_QUEUE3_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT2_QUEUE4_WFQ_WEIGHT 0x0320 +#define RTL8367C_SCHEDULE_PORT2_QUEUE4_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT2_QUEUE4_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT2_QUEUE5_WFQ_WEIGHT 0x0321 +#define RTL8367C_SCHEDULE_PORT2_QUEUE5_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT2_QUEUE5_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT2_QUEUE6_WFQ_WEIGHT 0x0322 +#define RTL8367C_SCHEDULE_PORT2_QUEUE6_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT2_QUEUE6_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT2_QUEUE7_WFQ_WEIGHT 0x0323 +#define RTL8367C_SCHEDULE_PORT2_QUEUE7_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT2_QUEUE7_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT3_QUEUE0_WFQ_WEIGHT 0x0324 + +#define RTL8367C_REG_SCHEDULE_PORT3_QUEUE1_WFQ_WEIGHT 0x0325 +#define RTL8367C_SCHEDULE_PORT3_QUEUE1_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT3_QUEUE1_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT3_QUEUE2_WFQ_WEIGHT 0x0326 +#define RTL8367C_SCHEDULE_PORT3_QUEUE2_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT3_QUEUE2_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT3_QUEUE3_WFQ_WEIGHT 0x0327 +#define RTL8367C_SCHEDULE_PORT3_QUEUE3_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT3_QUEUE3_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT3_QUEUE4_WFQ_WEIGHT 0x0328 +#define RTL8367C_SCHEDULE_PORT3_QUEUE4_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT3_QUEUE4_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT3_QUEUE5_WFQ_WEIGHT 0x0329 +#define RTL8367C_SCHEDULE_PORT3_QUEUE5_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT3_QUEUE5_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT3_QUEUE6_WFQ_WEIGHT 0x032a +#define RTL8367C_SCHEDULE_PORT3_QUEUE6_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT3_QUEUE6_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT3_QUEUE7_WFQ_WEIGHT 0x032b +#define RTL8367C_SCHEDULE_PORT3_QUEUE7_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT3_QUEUE7_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT4_QUEUE0_WFQ_WEIGHT 0x032c + +#define RTL8367C_REG_SCHEDULE_PORT4_QUEUE1_WFQ_WEIGHT 0x032d +#define RTL8367C_SCHEDULE_PORT4_QUEUE1_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT4_QUEUE1_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT4_QUEUE2_WFQ_WEIGHT 0x032e +#define RTL8367C_SCHEDULE_PORT4_QUEUE2_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT4_QUEUE2_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT4_QUEUE3_WFQ_WEIGHT 0x032f +#define RTL8367C_SCHEDULE_PORT4_QUEUE3_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT4_QUEUE3_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT4_QUEUE4_WFQ_WEIGHT 0x0330 +#define RTL8367C_SCHEDULE_PORT4_QUEUE4_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT4_QUEUE4_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT4_QUEUE5_WFQ_WEIGHT 0x0331 +#define RTL8367C_SCHEDULE_PORT4_QUEUE5_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT4_QUEUE5_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT4_QUEUE6_WFQ_WEIGHT 0x0332 +#define RTL8367C_SCHEDULE_PORT4_QUEUE6_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT4_QUEUE6_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT4_QUEUE7_WFQ_WEIGHT 0x0333 +#define RTL8367C_SCHEDULE_PORT4_QUEUE7_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT4_QUEUE7_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT5_QUEUE0_WFQ_WEIGHT 0x0334 + +#define RTL8367C_REG_SCHEDULE_PORT5_QUEUE1_WFQ_WEIGHT 0x0335 +#define RTL8367C_SCHEDULE_PORT5_QUEUE1_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT5_QUEUE1_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT5_QUEUE2_WFQ_WEIGHT 0x0336 +#define RTL8367C_SCHEDULE_PORT5_QUEUE2_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT5_QUEUE2_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT5_QUEUE3_WFQ_WEIGHT 0x0337 +#define RTL8367C_SCHEDULE_PORT5_QUEUE3_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT5_QUEUE3_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT5_QUEUE4_WFQ_WEIGHT 0x0338 +#define RTL8367C_SCHEDULE_PORT5_QUEUE4_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT5_QUEUE4_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT5_QUEUE5_WFQ_WEIGHT 0x0339 +#define RTL8367C_SCHEDULE_PORT5_QUEUE5_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT5_QUEUE5_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT5_QUEUE6_WFQ_WEIGHT 0x033a +#define RTL8367C_SCHEDULE_PORT5_QUEUE6_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT5_QUEUE6_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT5_QUEUE7_WFQ_WEIGHT 0x033b +#define RTL8367C_SCHEDULE_PORT5_QUEUE7_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT5_QUEUE7_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT6_QUEUE0_WFQ_WEIGHT 0x033c + +#define RTL8367C_REG_SCHEDULE_PORT6_QUEUE1_WFQ_WEIGHT 0x033d +#define RTL8367C_SCHEDULE_PORT6_QUEUE1_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT6_QUEUE1_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT6_QUEUE2_WFQ_WEIGHT 0x033e +#define RTL8367C_SCHEDULE_PORT6_QUEUE2_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT6_QUEUE2_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT6_QUEUE3_WFQ_WEIGHT 0x033f +#define RTL8367C_SCHEDULE_PORT6_QUEUE3_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT6_QUEUE3_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT6_QUEUE4_WFQ_WEIGHT 0x0340 +#define RTL8367C_SCHEDULE_PORT6_QUEUE4_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT6_QUEUE4_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT6_QUEUE5_WFQ_WEIGHT 0x0341 +#define RTL8367C_SCHEDULE_PORT6_QUEUE5_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT6_QUEUE5_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT6_QUEUE6_WFQ_WEIGHT 0x0342 +#define RTL8367C_SCHEDULE_PORT6_QUEUE6_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT6_QUEUE6_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT6_QUEUE7_WFQ_WEIGHT 0x0343 +#define RTL8367C_SCHEDULE_PORT6_QUEUE7_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT6_QUEUE7_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT7_QUEUE0_WFQ_WEIGHT 0x0344 + +#define RTL8367C_REG_SCHEDULE_PORT7_QUEUE1_WFQ_WEIGHT 0x0345 +#define RTL8367C_SCHEDULE_PORT7_QUEUE1_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT7_QUEUE1_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT7_QUEUE2_WFQ_WEIGHT 0x0346 +#define RTL8367C_SCHEDULE_PORT7_QUEUE2_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT7_QUEUE2_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT7_QUEUE3_WFQ_WEIGHT 0x0347 +#define RTL8367C_SCHEDULE_PORT7_QUEUE3_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT7_QUEUE3_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT7_QUEUE4_WFQ_WEIGHT 0x0348 +#define RTL8367C_SCHEDULE_PORT7_QUEUE4_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT7_QUEUE4_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT7_QUEUE5_WFQ_WEIGHT 0x0349 +#define RTL8367C_SCHEDULE_PORT7_QUEUE5_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT7_QUEUE5_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT7_QUEUE6_WFQ_WEIGHT 0x034a +#define RTL8367C_SCHEDULE_PORT7_QUEUE6_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT7_QUEUE6_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT7_QUEUE7_WFQ_WEIGHT 0x034b +#define RTL8367C_SCHEDULE_PORT7_QUEUE7_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT7_QUEUE7_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT8_QUEUE0_WFQ_WEIGHT 0x034c + +#define RTL8367C_REG_SCHEDULE_PORT8_QUEUE1_WFQ_WEIGHT 0x034d +#define RTL8367C_SCHEDULE_PORT8_QUEUE1_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT8_QUEUE1_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT8_QUEUE2_WFQ_WEIGHT 0x034e +#define RTL8367C_SCHEDULE_PORT8_QUEUE2_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT8_QUEUE2_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT8_QUEUE3_WFQ_WEIGHT 0x034f +#define RTL8367C_SCHEDULE_PORT8_QUEUE3_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT8_QUEUE3_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT8_QUEUE4_WFQ_WEIGHT 0x0350 +#define RTL8367C_SCHEDULE_PORT8_QUEUE4_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT8_QUEUE4_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT8_QUEUE5_WFQ_WEIGHT 0x0351 +#define RTL8367C_SCHEDULE_PORT8_QUEUE5_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT8_QUEUE5_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT8_QUEUE6_WFQ_WEIGHT 0x0352 +#define RTL8367C_SCHEDULE_PORT8_QUEUE6_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT8_QUEUE6_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT8_QUEUE7_WFQ_WEIGHT 0x0353 +#define RTL8367C_SCHEDULE_PORT8_QUEUE7_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT8_QUEUE7_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT9_QUEUE0_WFQ_WEIGHT 0x0354 + +#define RTL8367C_REG_SCHEDULE_PORT9_QUEUE1_WFQ_WEIGHT 0x0355 +#define RTL8367C_SCHEDULE_PORT9_QUEUE1_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT9_QUEUE1_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT9_QUEUE2_WFQ_WEIGHT 0x0356 +#define RTL8367C_SCHEDULE_PORT9_QUEUE2_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT9_QUEUE2_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT9_QUEUE3_WFQ_WEIGHT 0x0357 +#define RTL8367C_SCHEDULE_PORT9_QUEUE3_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT9_QUEUE3_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT9_QUEUE4_WFQ_WEIGHT 0x0358 +#define RTL8367C_SCHEDULE_PORT9_QUEUE4_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT9_QUEUE4_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT9_QUEUE5_WFQ_WEIGHT 0x0359 +#define RTL8367C_SCHEDULE_PORT9_QUEUE5_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT9_QUEUE5_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT9_QUEUE6_WFQ_WEIGHT 0x035a +#define RTL8367C_SCHEDULE_PORT9_QUEUE6_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT9_QUEUE6_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT9_QUEUE7_WFQ_WEIGHT 0x035b +#define RTL8367C_SCHEDULE_PORT9_QUEUE7_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT9_QUEUE7_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT10_QUEUE0_WFQ_WEIGHT 0x035c + +#define RTL8367C_REG_SCHEDULE_PORT10_QUEUE1_WFQ_WEIGHT 0x035d +#define RTL8367C_SCHEDULE_PORT10_QUEUE1_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT10_QUEUE1_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT10_QUEUE2_WFQ_WEIGHT 0x035e +#define RTL8367C_SCHEDULE_PORT10_QUEUE2_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT10_QUEUE2_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT10_QUEUE3_WFQ_WEIGHT 0x035f +#define RTL8367C_SCHEDULE_PORT10_QUEUE3_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT10_QUEUE3_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT10_QUEUE4_WFQ_WEIGHT 0x0360 +#define RTL8367C_SCHEDULE_PORT10_QUEUE4_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT10_QUEUE4_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT10_QUEUE5_WFQ_WEIGHT 0x0361 +#define RTL8367C_SCHEDULE_PORT10_QUEUE5_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT10_QUEUE5_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT10_QUEUE6_WFQ_WEIGHT 0x0362 +#define RTL8367C_SCHEDULE_PORT10_QUEUE6_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT10_QUEUE6_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_SCHEDULE_PORT10_QUEUE7_WFQ_WEIGHT 0x0363 +#define RTL8367C_SCHEDULE_PORT10_QUEUE7_WFQ_WEIGHT_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT10_QUEUE7_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367C_REG_PORT0_EGRESSBW_CTRL0 0x038c + +#define RTL8367C_REG_PORT0_EGRESSBW_CTRL1 0x038d +#define RTL8367C_PORT0_EGRESSBW_CTRL1_OFFSET 0 +#define RTL8367C_PORT0_EGRESSBW_CTRL1_MASK 0x1 + +#define RTL8367C_REG_PORT1_EGRESSBW_CTRL0 0x038e + +#define RTL8367C_REG_PORT1_EGRESSBW_CTRL1 0x038f +#define RTL8367C_PORT1_EGRESSBW_CTRL1_OFFSET 0 +#define RTL8367C_PORT1_EGRESSBW_CTRL1_MASK 0x1 + +#define RTL8367C_REG_PORT2_EGRESSBW_CTRL0 0x0390 + +#define RTL8367C_REG_PORT2_EGRESSBW_CTRL1 0x0391 +#define RTL8367C_PORT2_EGRESSBW_CTRL1_OFFSET 0 +#define RTL8367C_PORT2_EGRESSBW_CTRL1_MASK 0x1 + +#define RTL8367C_REG_PORT3_EGRESSBW_CTRL0 0x0392 + +#define RTL8367C_REG_PORT3_EGRESSBW_CTRL1 0x0393 +#define RTL8367C_PORT3_EGRESSBW_CTRL1_OFFSET 0 +#define RTL8367C_PORT3_EGRESSBW_CTRL1_MASK 0x1 + +#define RTL8367C_REG_PORT4_EGRESSBW_CTRL0 0x0394 + +#define RTL8367C_REG_PORT4_EGRESSBW_CTRL1 0x0395 +#define RTL8367C_PORT4_EGRESSBW_CTRL1_OFFSET 0 +#define RTL8367C_PORT4_EGRESSBW_CTRL1_MASK 0x1 + +#define RTL8367C_REG_PORT5_EGRESSBW_CTRL0 0x0396 + +#define RTL8367C_REG_PORT5_EGRESSBW_CTRL1 0x0397 +#define RTL8367C_PORT5_EGRESSBW_CTRL1_OFFSET 0 +#define RTL8367C_PORT5_EGRESSBW_CTRL1_MASK 0x1 + +#define RTL8367C_REG_PORT6_EGRESSBW_CTRL0 0x0398 + +#define RTL8367C_REG_PORT6_EGRESSBW_CTRL1 0x0399 +#define RTL8367C_PORT6_EGRESSBW_CTRL1_OFFSET 0 +#define RTL8367C_PORT6_EGRESSBW_CTRL1_MASK 0x7 + +#define RTL8367C_REG_PORT7_EGRESSBW_CTRL0 0x039a + +#define RTL8367C_REG_PORT7_EGRESSBW_CTRL1 0x039b +#define RTL8367C_PORT7_EGRESSBW_CTRL1_OFFSET 0 +#define RTL8367C_PORT7_EGRESSBW_CTRL1_MASK 0x1 + +#define RTL8367C_REG_PORT8_EGRESSBW_CTRL0 0x039c + +#define RTL8367C_REG_PORT8_EGRESSBW_CTRL1 0x039d +#define RTL8367C_PORT8_EGRESSBW_CTRL1_OFFSET 0 +#define RTL8367C_PORT8_EGRESSBW_CTRL1_MASK 0x1 + +#define RTL8367C_REG_PORT9_EGRESSBW_CTRL0 0x039e + +#define RTL8367C_REG_PORT9_EGRESSBW_CTRL1 0x039f +#define RTL8367C_PORT9_EGRESSBW_CTRL1_OFFSET 0 +#define RTL8367C_PORT9_EGRESSBW_CTRL1_MASK 0x7 + +#define RTL8367C_REG_PORT10_EGRESSBW_CTRL0 0x03a0 + +#define RTL8367C_REG_PORT10_EGRESSBW_CTRL1 0x03a1 +#define RTL8367C_PORT10_EGRESSBW_CTRL1_OFFSET 0 +#define RTL8367C_PORT10_EGRESSBW_CTRL1_MASK 0x1 + +#define RTL8367C_REG_SCHEDULE_PORT0_APR_METER_CTRL0 0x03ac +#define RTL8367C_SCHEDULE_PORT0_APR_METER_CTRL0_QUEUE4_APR_METER_OFFSET 12 +#define RTL8367C_SCHEDULE_PORT0_APR_METER_CTRL0_QUEUE4_APR_METER_MASK 0x7000 +#define RTL8367C_SCHEDULE_PORT0_APR_METER_CTRL0_QUEUE3_APR_METER_OFFSET 9 +#define RTL8367C_SCHEDULE_PORT0_APR_METER_CTRL0_QUEUE3_APR_METER_MASK 0xE00 +#define RTL8367C_SCHEDULE_PORT0_APR_METER_CTRL0_QUEUE2_APR_METER_OFFSET 6 +#define RTL8367C_SCHEDULE_PORT0_APR_METER_CTRL0_QUEUE2_APR_METER_MASK 0x1C0 +#define RTL8367C_SCHEDULE_PORT0_APR_METER_CTRL0_QUEUE1_APR_METER_OFFSET 3 +#define RTL8367C_SCHEDULE_PORT0_APR_METER_CTRL0_QUEUE1_APR_METER_MASK 0x38 +#define RTL8367C_SCHEDULE_PORT0_APR_METER_CTRL0_QUEUE0_APR_METER_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT0_APR_METER_CTRL0_QUEUE0_APR_METER_MASK 0x7 + +#define RTL8367C_REG_SCHEDULE_PORT0_APR_METER_CTRL1 0x03ad +#define RTL8367C_SCHEDULE_PORT0_APR_METER_CTRL1_QUEUE7_APR_METER_OFFSET 6 +#define RTL8367C_SCHEDULE_PORT0_APR_METER_CTRL1_QUEUE7_APR_METER_MASK 0x1C0 +#define RTL8367C_SCHEDULE_PORT0_APR_METER_CTRL1_QUEUE6_APR_METER_OFFSET 3 +#define RTL8367C_SCHEDULE_PORT0_APR_METER_CTRL1_QUEUE6_APR_METER_MASK 0x38 +#define RTL8367C_SCHEDULE_PORT0_APR_METER_CTRL1_QUEUE5_APR_METER_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT0_APR_METER_CTRL1_QUEUE5_APR_METER_MASK 0x7 + +#define RTL8367C_REG_SCHEDULE_PORT1_APR_METER_CTRL0 0x03b0 +#define RTL8367C_SCHEDULE_PORT1_APR_METER_CTRL0_QUEUE4_APR_METER_OFFSET 12 +#define RTL8367C_SCHEDULE_PORT1_APR_METER_CTRL0_QUEUE4_APR_METER_MASK 0x7000 +#define RTL8367C_SCHEDULE_PORT1_APR_METER_CTRL0_QUEUE3_APR_METER_OFFSET 9 +#define RTL8367C_SCHEDULE_PORT1_APR_METER_CTRL0_QUEUE3_APR_METER_MASK 0xE00 +#define RTL8367C_SCHEDULE_PORT1_APR_METER_CTRL0_QUEUE2_APR_METER_OFFSET 6 +#define RTL8367C_SCHEDULE_PORT1_APR_METER_CTRL0_QUEUE2_APR_METER_MASK 0x1C0 +#define RTL8367C_SCHEDULE_PORT1_APR_METER_CTRL0_QUEUE1_APR_METER_OFFSET 3 +#define RTL8367C_SCHEDULE_PORT1_APR_METER_CTRL0_QUEUE1_APR_METER_MASK 0x38 +#define RTL8367C_SCHEDULE_PORT1_APR_METER_CTRL0_QUEUE0_APR_METER_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT1_APR_METER_CTRL0_QUEUE0_APR_METER_MASK 0x7 + +#define RTL8367C_REG_SCHEDULE_PORT1_APR_METER_CTRL1 0x03b1 +#define RTL8367C_SCHEDULE_PORT1_APR_METER_CTRL1_QUEUE7_APR_METER_OFFSET 6 +#define RTL8367C_SCHEDULE_PORT1_APR_METER_CTRL1_QUEUE7_APR_METER_MASK 0x1C0 +#define RTL8367C_SCHEDULE_PORT1_APR_METER_CTRL1_QUEUE6_APR_METER_OFFSET 3 +#define RTL8367C_SCHEDULE_PORT1_APR_METER_CTRL1_QUEUE6_APR_METER_MASK 0x38 +#define RTL8367C_SCHEDULE_PORT1_APR_METER_CTRL1_QUEUE5_APR_METER_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT1_APR_METER_CTRL1_QUEUE5_APR_METER_MASK 0x7 + +#define RTL8367C_REG_SCHEDULE_PORT2_APR_METER_CTRL0 0x03b4 +#define RTL8367C_SCHEDULE_PORT2_APR_METER_CTRL0_QUEUE4_APR_METER_OFFSET 12 +#define RTL8367C_SCHEDULE_PORT2_APR_METER_CTRL0_QUEUE4_APR_METER_MASK 0x7000 +#define RTL8367C_SCHEDULE_PORT2_APR_METER_CTRL0_QUEUE3_APR_METER_OFFSET 9 +#define RTL8367C_SCHEDULE_PORT2_APR_METER_CTRL0_QUEUE3_APR_METER_MASK 0xE00 +#define RTL8367C_SCHEDULE_PORT2_APR_METER_CTRL0_QUEUE2_APR_METER_OFFSET 6 +#define RTL8367C_SCHEDULE_PORT2_APR_METER_CTRL0_QUEUE2_APR_METER_MASK 0x1C0 +#define RTL8367C_SCHEDULE_PORT2_APR_METER_CTRL0_QUEUE1_APR_METER_OFFSET 3 +#define RTL8367C_SCHEDULE_PORT2_APR_METER_CTRL0_QUEUE1_APR_METER_MASK 0x38 +#define RTL8367C_SCHEDULE_PORT2_APR_METER_CTRL0_QUEUE0_APR_METER_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT2_APR_METER_CTRL0_QUEUE0_APR_METER_MASK 0x7 + +#define RTL8367C_REG_SCHEDULE_PORT2_APR_METER_CTRL1 0x03b5 +#define RTL8367C_SCHEDULE_PORT2_APR_METER_CTRL1_QUEUE7_APR_METER_OFFSET 6 +#define RTL8367C_SCHEDULE_PORT2_APR_METER_CTRL1_QUEUE7_APR_METER_MASK 0x1C0 +#define RTL8367C_SCHEDULE_PORT2_APR_METER_CTRL1_QUEUE6_APR_METER_OFFSET 3 +#define RTL8367C_SCHEDULE_PORT2_APR_METER_CTRL1_QUEUE6_APR_METER_MASK 0x38 +#define RTL8367C_SCHEDULE_PORT2_APR_METER_CTRL1_QUEUE5_APR_METER_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT2_APR_METER_CTRL1_QUEUE5_APR_METER_MASK 0x7 + +#define RTL8367C_REG_SCHEDULE_PORT3_APR_METER_CTRL0 0x03b8 +#define RTL8367C_SCHEDULE_PORT3_APR_METER_CTRL0_QUEUE4_APR_METER_OFFSET 12 +#define RTL8367C_SCHEDULE_PORT3_APR_METER_CTRL0_QUEUE4_APR_METER_MASK 0x7000 +#define RTL8367C_SCHEDULE_PORT3_APR_METER_CTRL0_QUEUE3_APR_METER_OFFSET 9 +#define RTL8367C_SCHEDULE_PORT3_APR_METER_CTRL0_QUEUE3_APR_METER_MASK 0xE00 +#define RTL8367C_SCHEDULE_PORT3_APR_METER_CTRL0_QUEUE2_APR_METER_OFFSET 6 +#define RTL8367C_SCHEDULE_PORT3_APR_METER_CTRL0_QUEUE2_APR_METER_MASK 0x1C0 +#define RTL8367C_SCHEDULE_PORT3_APR_METER_CTRL0_QUEUE1_APR_METER_OFFSET 3 +#define RTL8367C_SCHEDULE_PORT3_APR_METER_CTRL0_QUEUE1_APR_METER_MASK 0x38 +#define RTL8367C_SCHEDULE_PORT3_APR_METER_CTRL0_QUEUE0_APR_METER_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT3_APR_METER_CTRL0_QUEUE0_APR_METER_MASK 0x7 + +#define RTL8367C_REG_SCHEDULE_PORT3_APR_METER_CTRL1 0x03b9 +#define RTL8367C_SCHEDULE_PORT3_APR_METER_CTRL1_QUEUE7_APR_METER_OFFSET 6 +#define RTL8367C_SCHEDULE_PORT3_APR_METER_CTRL1_QUEUE7_APR_METER_MASK 0x1C0 +#define RTL8367C_SCHEDULE_PORT3_APR_METER_CTRL1_QUEUE6_APR_METER_OFFSET 3 +#define RTL8367C_SCHEDULE_PORT3_APR_METER_CTRL1_QUEUE6_APR_METER_MASK 0x38 +#define RTL8367C_SCHEDULE_PORT3_APR_METER_CTRL1_QUEUE5_APR_METER_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT3_APR_METER_CTRL1_QUEUE5_APR_METER_MASK 0x7 + +#define RTL8367C_REG_SCHEDULE_PORT4_APR_METER_CTRL0 0x03bc +#define RTL8367C_SCHEDULE_PORT4_APR_METER_CTRL0_QUEUE4_APR_METER_OFFSET 12 +#define RTL8367C_SCHEDULE_PORT4_APR_METER_CTRL0_QUEUE4_APR_METER_MASK 0x7000 +#define RTL8367C_SCHEDULE_PORT4_APR_METER_CTRL0_QUEUE3_APR_METER_OFFSET 9 +#define RTL8367C_SCHEDULE_PORT4_APR_METER_CTRL0_QUEUE3_APR_METER_MASK 0xE00 +#define RTL8367C_SCHEDULE_PORT4_APR_METER_CTRL0_QUEUE2_APR_METER_OFFSET 6 +#define RTL8367C_SCHEDULE_PORT4_APR_METER_CTRL0_QUEUE2_APR_METER_MASK 0x1C0 +#define RTL8367C_SCHEDULE_PORT4_APR_METER_CTRL0_QUEUE1_APR_METER_OFFSET 3 +#define RTL8367C_SCHEDULE_PORT4_APR_METER_CTRL0_QUEUE1_APR_METER_MASK 0x38 +#define RTL8367C_SCHEDULE_PORT4_APR_METER_CTRL0_QUEUE0_APR_METER_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT4_APR_METER_CTRL0_QUEUE0_APR_METER_MASK 0x7 + +#define RTL8367C_REG_SCHEDULE_PORT4_APR_METER_CTRL1 0x03bd +#define RTL8367C_SCHEDULE_PORT4_APR_METER_CTRL1_QUEUE7_APR_METER_OFFSET 6 +#define RTL8367C_SCHEDULE_PORT4_APR_METER_CTRL1_QUEUE7_APR_METER_MASK 0x1C0 +#define RTL8367C_SCHEDULE_PORT4_APR_METER_CTRL1_QUEUE6_APR_METER_OFFSET 3 +#define RTL8367C_SCHEDULE_PORT4_APR_METER_CTRL1_QUEUE6_APR_METER_MASK 0x38 +#define RTL8367C_SCHEDULE_PORT4_APR_METER_CTRL1_QUEUE5_APR_METER_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT4_APR_METER_CTRL1_QUEUE5_APR_METER_MASK 0x7 + +#define RTL8367C_REG_SCHEDULE_PORT5_APR_METER_CTRL0 0x03c0 +#define RTL8367C_SCHEDULE_PORT5_APR_METER_CTRL0_QUEUE4_APR_METER_OFFSET 12 +#define RTL8367C_SCHEDULE_PORT5_APR_METER_CTRL0_QUEUE4_APR_METER_MASK 0x7000 +#define RTL8367C_SCHEDULE_PORT5_APR_METER_CTRL0_QUEUE3_APR_METER_OFFSET 9 +#define RTL8367C_SCHEDULE_PORT5_APR_METER_CTRL0_QUEUE3_APR_METER_MASK 0xE00 +#define RTL8367C_SCHEDULE_PORT5_APR_METER_CTRL0_QUEUE2_APR_METER_OFFSET 6 +#define RTL8367C_SCHEDULE_PORT5_APR_METER_CTRL0_QUEUE2_APR_METER_MASK 0x1C0 +#define RTL8367C_SCHEDULE_PORT5_APR_METER_CTRL0_QUEUE1_APR_METER_OFFSET 3 +#define RTL8367C_SCHEDULE_PORT5_APR_METER_CTRL0_QUEUE1_APR_METER_MASK 0x38 +#define RTL8367C_SCHEDULE_PORT5_APR_METER_CTRL0_QUEUE0_APR_METER_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT5_APR_METER_CTRL0_QUEUE0_APR_METER_MASK 0x7 + +#define RTL8367C_REG_SCHEDULE_PORT5_APR_METER_CTRL1 0x03c1 +#define RTL8367C_SCHEDULE_PORT5_APR_METER_CTRL1_QUEUE7_APR_METER_OFFSET 6 +#define RTL8367C_SCHEDULE_PORT5_APR_METER_CTRL1_QUEUE7_APR_METER_MASK 0x1C0 +#define RTL8367C_SCHEDULE_PORT5_APR_METER_CTRL1_QUEUE6_APR_METER_OFFSET 3 +#define RTL8367C_SCHEDULE_PORT5_APR_METER_CTRL1_QUEUE6_APR_METER_MASK 0x38 +#define RTL8367C_SCHEDULE_PORT5_APR_METER_CTRL1_QUEUE5_APR_METER_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT5_APR_METER_CTRL1_QUEUE5_APR_METER_MASK 0x7 + +#define RTL8367C_REG_SCHEDULE_PORT6_APR_METER_CTRL0 0x03c4 +#define RTL8367C_SCHEDULE_PORT6_APR_METER_CTRL0_QUEUE4_APR_METER_OFFSET 12 +#define RTL8367C_SCHEDULE_PORT6_APR_METER_CTRL0_QUEUE4_APR_METER_MASK 0x7000 +#define RTL8367C_SCHEDULE_PORT6_APR_METER_CTRL0_QUEUE3_APR_METER_OFFSET 9 +#define RTL8367C_SCHEDULE_PORT6_APR_METER_CTRL0_QUEUE3_APR_METER_MASK 0xE00 +#define RTL8367C_SCHEDULE_PORT6_APR_METER_CTRL0_QUEUE2_APR_METER_OFFSET 6 +#define RTL8367C_SCHEDULE_PORT6_APR_METER_CTRL0_QUEUE2_APR_METER_MASK 0x1C0 +#define RTL8367C_SCHEDULE_PORT6_APR_METER_CTRL0_QUEUE1_APR_METER_OFFSET 3 +#define RTL8367C_SCHEDULE_PORT6_APR_METER_CTRL0_QUEUE1_APR_METER_MASK 0x38 +#define RTL8367C_SCHEDULE_PORT6_APR_METER_CTRL0_QUEUE0_APR_METER_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT6_APR_METER_CTRL0_QUEUE0_APR_METER_MASK 0x7 + +#define RTL8367C_REG_SCHEDULE_PORT6_APR_METER_CTRL1 0x03c5 +#define RTL8367C_SCHEDULE_PORT6_APR_METER_CTRL1_QUEUE7_APR_METER_OFFSET 6 +#define RTL8367C_SCHEDULE_PORT6_APR_METER_CTRL1_QUEUE7_APR_METER_MASK 0x1C0 +#define RTL8367C_SCHEDULE_PORT6_APR_METER_CTRL1_QUEUE6_APR_METER_OFFSET 3 +#define RTL8367C_SCHEDULE_PORT6_APR_METER_CTRL1_QUEUE6_APR_METER_MASK 0x38 +#define RTL8367C_SCHEDULE_PORT6_APR_METER_CTRL1_QUEUE5_APR_METER_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT6_APR_METER_CTRL1_QUEUE5_APR_METER_MASK 0x7 + +#define RTL8367C_REG_SCHEDULE_PORT7_APR_METER_CTRL0 0x03c8 +#define RTL8367C_SCHEDULE_PORT7_APR_METER_CTRL0_QUEUE4_APR_METER_OFFSET 12 +#define RTL8367C_SCHEDULE_PORT7_APR_METER_CTRL0_QUEUE4_APR_METER_MASK 0x7000 +#define RTL8367C_SCHEDULE_PORT7_APR_METER_CTRL0_QUEUE3_APR_METER_OFFSET 9 +#define RTL8367C_SCHEDULE_PORT7_APR_METER_CTRL0_QUEUE3_APR_METER_MASK 0xE00 +#define RTL8367C_SCHEDULE_PORT7_APR_METER_CTRL0_QUEUE2_APR_METER_OFFSET 6 +#define RTL8367C_SCHEDULE_PORT7_APR_METER_CTRL0_QUEUE2_APR_METER_MASK 0x1C0 +#define RTL8367C_SCHEDULE_PORT7_APR_METER_CTRL0_QUEUE1_APR_METER_OFFSET 3 +#define RTL8367C_SCHEDULE_PORT7_APR_METER_CTRL0_QUEUE1_APR_METER_MASK 0x38 +#define RTL8367C_SCHEDULE_PORT7_APR_METER_CTRL0_QUEUE0_APR_METER_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT7_APR_METER_CTRL0_QUEUE0_APR_METER_MASK 0x7 + +#define RTL8367C_REG_SCHEDULE_PORT7_APR_METER_CTRL1 0x03c9 +#define RTL8367C_SCHEDULE_PORT7_APR_METER_CTRL1_QUEUE7_APR_METER_OFFSET 6 +#define RTL8367C_SCHEDULE_PORT7_APR_METER_CTRL1_QUEUE7_APR_METER_MASK 0x1C0 +#define RTL8367C_SCHEDULE_PORT7_APR_METER_CTRL1_QUEUE6_APR_METER_OFFSET 3 +#define RTL8367C_SCHEDULE_PORT7_APR_METER_CTRL1_QUEUE6_APR_METER_MASK 0x38 +#define RTL8367C_SCHEDULE_PORT7_APR_METER_CTRL1_QUEUE5_APR_METER_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT7_APR_METER_CTRL1_QUEUE5_APR_METER_MASK 0x7 + +#define RTL8367C_REG_SCHEDULE_PORT8_APR_METER_CTRL0 0x03ca +#define RTL8367C_SCHEDULE_PORT8_APR_METER_CTRL0_QUEUE4_APR_METER_OFFSET 12 +#define RTL8367C_SCHEDULE_PORT8_APR_METER_CTRL0_QUEUE4_APR_METER_MASK 0x7000 +#define RTL8367C_SCHEDULE_PORT8_APR_METER_CTRL0_QUEUE3_APR_METER_OFFSET 9 +#define RTL8367C_SCHEDULE_PORT8_APR_METER_CTRL0_QUEUE3_APR_METER_MASK 0xE00 +#define RTL8367C_SCHEDULE_PORT8_APR_METER_CTRL0_QUEUE2_APR_METER_OFFSET 6 +#define RTL8367C_SCHEDULE_PORT8_APR_METER_CTRL0_QUEUE2_APR_METER_MASK 0x1C0 +#define RTL8367C_SCHEDULE_PORT8_APR_METER_CTRL0_QUEUE1_APR_METER_OFFSET 3 +#define RTL8367C_SCHEDULE_PORT8_APR_METER_CTRL0_QUEUE1_APR_METER_MASK 0x38 +#define RTL8367C_SCHEDULE_PORT8_APR_METER_CTRL0_QUEUE0_APR_METER_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT8_APR_METER_CTRL0_QUEUE0_APR_METER_MASK 0x7 + +#define RTL8367C_REG_SCHEDULE_PORT8_APR_METER_CTRL1 0x03cb +#define RTL8367C_SCHEDULE_PORT8_APR_METER_CTRL1_QUEUE7_APR_METER_OFFSET 6 +#define RTL8367C_SCHEDULE_PORT8_APR_METER_CTRL1_QUEUE7_APR_METER_MASK 0x1C0 +#define RTL8367C_SCHEDULE_PORT8_APR_METER_CTRL1_QUEUE6_APR_METER_OFFSET 3 +#define RTL8367C_SCHEDULE_PORT8_APR_METER_CTRL1_QUEUE6_APR_METER_MASK 0x38 +#define RTL8367C_SCHEDULE_PORT8_APR_METER_CTRL1_QUEUE5_APR_METER_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT8_APR_METER_CTRL1_QUEUE5_APR_METER_MASK 0x7 + +#define RTL8367C_REG_SCHEDULE_PORT9_APR_METER_CTRL0 0x03cc +#define RTL8367C_SCHEDULE_PORT9_APR_METER_CTRL0_QUEUE4_APR_METER_OFFSET 12 +#define RTL8367C_SCHEDULE_PORT9_APR_METER_CTRL0_QUEUE4_APR_METER_MASK 0x7000 +#define RTL8367C_SCHEDULE_PORT9_APR_METER_CTRL0_QUEUE3_APR_METER_OFFSET 9 +#define RTL8367C_SCHEDULE_PORT9_APR_METER_CTRL0_QUEUE3_APR_METER_MASK 0xE00 +#define RTL8367C_SCHEDULE_PORT9_APR_METER_CTRL0_QUEUE2_APR_METER_OFFSET 6 +#define RTL8367C_SCHEDULE_PORT9_APR_METER_CTRL0_QUEUE2_APR_METER_MASK 0x1C0 +#define RTL8367C_SCHEDULE_PORT9_APR_METER_CTRL0_QUEUE1_APR_METER_OFFSET 3 +#define RTL8367C_SCHEDULE_PORT9_APR_METER_CTRL0_QUEUE1_APR_METER_MASK 0x38 +#define RTL8367C_SCHEDULE_PORT9_APR_METER_CTRL0_QUEUE0_APR_METER_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT9_APR_METER_CTRL0_QUEUE0_APR_METER_MASK 0x7 + +#define RTL8367C_REG_SCHEDULE_PORT9_APR_METER_CTRL1 0x03cd +#define RTL8367C_SCHEDULE_PORT9_APR_METER_CTRL1_QUEUE7_APR_METER_OFFSET 6 +#define RTL8367C_SCHEDULE_PORT9_APR_METER_CTRL1_QUEUE7_APR_METER_MASK 0x1C0 +#define RTL8367C_SCHEDULE_PORT9_APR_METER_CTRL1_QUEUE6_APR_METER_OFFSET 3 +#define RTL8367C_SCHEDULE_PORT9_APR_METER_CTRL1_QUEUE6_APR_METER_MASK 0x38 +#define RTL8367C_SCHEDULE_PORT9_APR_METER_CTRL1_QUEUE5_APR_METER_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT9_APR_METER_CTRL1_QUEUE5_APR_METER_MASK 0x7 + +#define RTL8367C_REG_SCHEDULE_PORT10_APR_METER_CTRL0 0x03ce +#define RTL8367C_SCHEDULE_PORT10_APR_METER_CTRL0_QUEUE4_APR_METER_OFFSET 12 +#define RTL8367C_SCHEDULE_PORT10_APR_METER_CTRL0_QUEUE4_APR_METER_MASK 0x7000 +#define RTL8367C_SCHEDULE_PORT10_APR_METER_CTRL0_QUEUE3_APR_METER_OFFSET 9 +#define RTL8367C_SCHEDULE_PORT10_APR_METER_CTRL0_QUEUE3_APR_METER_MASK 0xE00 +#define RTL8367C_SCHEDULE_PORT10_APR_METER_CTRL0_QUEUE2_APR_METER_OFFSET 6 +#define RTL8367C_SCHEDULE_PORT10_APR_METER_CTRL0_QUEUE2_APR_METER_MASK 0x1C0 +#define RTL8367C_SCHEDULE_PORT10_APR_METER_CTRL0_QUEUE1_APR_METER_OFFSET 3 +#define RTL8367C_SCHEDULE_PORT10_APR_METER_CTRL0_QUEUE1_APR_METER_MASK 0x38 +#define RTL8367C_SCHEDULE_PORT10_APR_METER_CTRL0_QUEUE0_APR_METER_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT10_APR_METER_CTRL0_QUEUE0_APR_METER_MASK 0x7 + +#define RTL8367C_REG_SCHEDULE_PORT10_APR_METER_CTRL1 0x03cf +#define RTL8367C_SCHEDULE_PORT10_APR_METER_CTRL1_QUEUE7_APR_METER_OFFSET 6 +#define RTL8367C_SCHEDULE_PORT10_APR_METER_CTRL1_QUEUE7_APR_METER_MASK 0x1C0 +#define RTL8367C_SCHEDULE_PORT10_APR_METER_CTRL1_QUEUE6_APR_METER_OFFSET 3 +#define RTL8367C_SCHEDULE_PORT10_APR_METER_CTRL1_QUEUE6_APR_METER_MASK 0x38 +#define RTL8367C_SCHEDULE_PORT10_APR_METER_CTRL1_QUEUE5_APR_METER_OFFSET 0 +#define RTL8367C_SCHEDULE_PORT10_APR_METER_CTRL1_QUEUE5_APR_METER_MASK 0x7 + +#define RTL8367C_REG_LINE_RATE_1G_L 0x03ec + +#define RTL8367C_REG_LINE_RATE_1G_H 0x03ed +#define RTL8367C_LINE_RATE_1G_H_OFFSET 0 +#define RTL8367C_LINE_RATE_1G_H_MASK 0x1 + +#define RTL8367C_REG_LINE_RATE_100_L 0x03ee + +#define RTL8367C_REG_LINE_RATE_100_H 0x03ef +#define RTL8367C_LINE_RATE_100_H_OFFSET 0 +#define RTL8367C_LINE_RATE_100_H_MASK 0x1 + +#define RTL8367C_REG_LINE_RATE_10_L 0x03f0 + +#define RTL8367C_REG_LINE_RATE_10_H 0x03f1 +#define RTL8367C_LINE_RATE_10_H_OFFSET 0 +#define RTL8367C_LINE_RATE_10_H_MASK 0x1 + +#define RTL8367C_REG_DUMMY_03f2 0x03f2 + +#define RTL8367C_REG_DUMMY_03f3 0x03f3 + +#define RTL8367C_REG_DUMMY_03f4 0x03f4 + +#define RTL8367C_REG_DUMMY_03f5 0x03f5 + +#define RTL8367C_REG_DUMMY_03f6 0x03f6 + +#define RTL8367C_REG_BYPASS_LINE_RATE 0x03f7 +#define RTL8367C_BYPASS_PORT10_CONSTRAINT_OFFSET 5 +#define RTL8367C_BYPASS_PORT10_CONSTRAINT_MASK 0x20 +#define RTL8367C_BYPASS_PORT9_CONSTRAINT_OFFSET 4 +#define RTL8367C_BYPASS_PORT9_CONSTRAINT_MASK 0x10 +#define RTL8367C_BYPASS_PORT8_CONSTRAINT_OFFSET 3 +#define RTL8367C_BYPASS_PORT8_CONSTRAINT_MASK 0x8 +#define RTL8367C_BYPASS_PORT7_CONSTRAINT_OFFSET 2 +#define RTL8367C_BYPASS_PORT7_CONSTRAINT_MASK 0x4 +#define RTL8367C_BYPASS_PORT6_CONSTRAINT_OFFSET 1 +#define RTL8367C_BYPASS_PORT6_CONSTRAINT_MASK 0x2 +#define RTL8367C_BYPASS_PORT5_CONSTRAINT_OFFSET 0 +#define RTL8367C_BYPASS_PORT5_CONSTRAINT_MASK 0x1 + +#define RTL8367C_REG_LINE_RATE_500_H 0x03f8 +#define RTL8367C_LINE_RATE_500_H_OFFSET 0 +#define RTL8367C_LINE_RATE_500_H_MASK 0x7 + +#define RTL8367C_REG_LINE_RATE_500_L 0x03f9 + +#define RTL8367C_REG_LINE_RATE_HSG_H 0x03fa +#define RTL8367C_LINE_RATE_HSG_H_OFFSET 0 +#define RTL8367C_LINE_RATE_HSG_H_MASK 0x7 + +#define RTL8367C_REG_LINE_RATE_HSG_L 0x03fb + +/* (16'h0500)table_reg */ + +#define RTL8367C_REG_TABLE_ACCESS_CTRL 0x0500 +#define RTL8367C_TABLE_ACCESS_CTRL_SPA_OFFSET 8 +#define RTL8367C_TABLE_ACCESS_CTRL_SPA_MASK 0xF00 +#define RTL8367C_ACCESS_METHOD_OFFSET 4 +#define RTL8367C_ACCESS_METHOD_MASK 0x70 +#define RTL8367C_COMMAND_TYPE_OFFSET 3 +#define RTL8367C_COMMAND_TYPE_MASK 0x8 +#define RTL8367C_TABLE_TYPE_OFFSET 0 +#define RTL8367C_TABLE_TYPE_MASK 0x7 + +#define RTL8367C_REG_TABLE_ACCESS_ADDR 0x0501 +#define RTL8367C_TABLE_ACCESS_ADDR_OFFSET 0 +#define RTL8367C_TABLE_ACCESS_ADDR_MASK 0x1FFF + +#define RTL8367C_REG_TABLE_LUT_ADDR 0x0502 +#define RTL8367C_ADDRESS2_OFFSET 14 +#define RTL8367C_ADDRESS2_MASK 0x4000 +#define RTL8367C_TABLE_LUT_ADDR_BUSY_FLAG_OFFSET 13 +#define RTL8367C_TABLE_LUT_ADDR_BUSY_FLAG_MASK 0x2000 +#define RTL8367C_HIT_STATUS_OFFSET 12 +#define RTL8367C_HIT_STATUS_MASK 0x1000 +#define RTL8367C_TABLE_LUT_ADDR_TYPE_OFFSET 11 +#define RTL8367C_TABLE_LUT_ADDR_TYPE_MASK 0x800 +#define RTL8367C_TABLE_LUT_ADDR_ADDRESS_OFFSET 0 +#define RTL8367C_TABLE_LUT_ADDR_ADDRESS_MASK 0x7FF + +#define RTL8367C_REG_HSA_HSB_LATCH 0x0503 +#define RTL8367C_LATCH_ALWAYS_OFFSET 15 +#define RTL8367C_LATCH_ALWAYS_MASK 0x8000 +#define RTL8367C_LATCH_FIRST_OFFSET 14 +#define RTL8367C_LATCH_FIRST_MASK 0x4000 +#define RTL8367C_SPA_EN_OFFSET 13 +#define RTL8367C_SPA_EN_MASK 0x2000 +#define RTL8367C_FORWARD_EN_OFFSET 12 +#define RTL8367C_FORWARD_EN_MASK 0x1000 +#define RTL8367C_REASON_EN_OFFSET 11 +#define RTL8367C_REASON_EN_MASK 0x800 +#define RTL8367C_HSA_HSB_LATCH_SPA_OFFSET 8 +#define RTL8367C_HSA_HSB_LATCH_SPA_MASK 0x700 +#define RTL8367C_FORWARD_OFFSET 6 +#define RTL8367C_FORWARD_MASK 0xC0 +#define RTL8367C_REASON_OFFSET 0 +#define RTL8367C_REASON_MASK 0x3F + +#define RTL8367C_REG_HSA_HSB_LATCH2 0x0504 +#define RTL8367C_HSA_HSB_LATCH2_Reserved_OFFSET 1 +#define RTL8367C_HSA_HSB_LATCH2_Reserved_MASK 0xFFFE +#define RTL8367C_SPA2_OFFSET 0 +#define RTL8367C_SPA2_MASK 0x1 + +#define RTL8367C_REG_TABLE_WRITE_DATA0 0x0510 + +#define RTL8367C_REG_TABLE_WRITE_DATA1 0x0511 + +#define RTL8367C_REG_TABLE_WRITE_DATA2 0x0512 + +#define RTL8367C_REG_TABLE_WRITE_DATA3 0x0513 + +#define RTL8367C_REG_TABLE_WRITE_DATA4 0x0514 + +#define RTL8367C_REG_TABLE_WRITE_DATA5 0x0515 + +#define RTL8367C_REG_TABLE_WRITE_DATA6 0x0516 + +#define RTL8367C_REG_TABLE_WRITE_DATA7 0x0517 + +#define RTL8367C_REG_TABLE_WRITE_DATA8 0x0518 + +#define RTL8367C_REG_TABLE_WRITE_DATA9 0x0519 +#define RTL8367C_TABLE_WRITE_DATA9_OFFSET 0 +#define RTL8367C_TABLE_WRITE_DATA9_MASK 0xF + +#define RTL8367C_REG_TABLE_READ_DATA0 0x0520 + +#define RTL8367C_REG_TABLE_READ_DATA1 0x0521 + +#define RTL8367C_REG_TABLE_READ_DATA2 0x0522 + +#define RTL8367C_REG_TABLE_READ_DATA3 0x0523 + +#define RTL8367C_REG_TABLE_READ_DATA4 0x0524 + +#define RTL8367C_REG_TABLE_READ_DATA5 0x0525 + +#define RTL8367C_REG_TABLE_READ_DATA6 0x0526 + +#define RTL8367C_REG_TABLE_READ_DATA7 0x0527 + +#define RTL8367C_REG_TABLE_READ_DATA8 0x0528 + +#define RTL8367C_REG_TABLE_READ_DATA9 0x0529 +#define RTL8367C_TABLE_READ_DATA9_OFFSET 0 +#define RTL8367C_TABLE_READ_DATA9_MASK 0xF + +#define RTL8367C_REG_TBL_DUMMY00 0x0550 + +#define RTL8367C_REG_TBL_DUMMY01 0x0551 + +/* (16'h0600)acl_reg */ + +#define RTL8367C_REG_ACL_RULE_TEMPLATE0_CTRL0 0x0600 +#define RTL8367C_ACL_RULE_TEMPLATE0_CTRL0_FIELD1_OFFSET 8 +#define RTL8367C_ACL_RULE_TEMPLATE0_CTRL0_FIELD1_MASK 0x7F00 +#define RTL8367C_ACL_RULE_TEMPLATE0_CTRL0_FIELD0_OFFSET 0 +#define RTL8367C_ACL_RULE_TEMPLATE0_CTRL0_FIELD0_MASK 0x7F + +#define RTL8367C_REG_ACL_RULE_TEMPLATE0_CTRL1 0x0601 +#define RTL8367C_ACL_RULE_TEMPLATE0_CTRL1_FIELD3_OFFSET 8 +#define RTL8367C_ACL_RULE_TEMPLATE0_CTRL1_FIELD3_MASK 0x7F00 +#define RTL8367C_ACL_RULE_TEMPLATE0_CTRL1_FIELD2_OFFSET 0 +#define RTL8367C_ACL_RULE_TEMPLATE0_CTRL1_FIELD2_MASK 0x7F + +#define RTL8367C_REG_ACL_RULE_TEMPLATE0_CTRL2 0x0602 +#define RTL8367C_ACL_RULE_TEMPLATE0_CTRL2_FIELD5_OFFSET 8 +#define RTL8367C_ACL_RULE_TEMPLATE0_CTRL2_FIELD5_MASK 0x7F00 +#define RTL8367C_ACL_RULE_TEMPLATE0_CTRL2_FIELD4_OFFSET 0 +#define RTL8367C_ACL_RULE_TEMPLATE0_CTRL2_FIELD4_MASK 0x7F + +#define RTL8367C_REG_ACL_RULE_TEMPLATE0_CTRL3 0x0603 +#define RTL8367C_ACL_RULE_TEMPLATE0_CTRL3_FIELD7_OFFSET 8 +#define RTL8367C_ACL_RULE_TEMPLATE0_CTRL3_FIELD7_MASK 0x7F00 +#define RTL8367C_ACL_RULE_TEMPLATE0_CTRL3_FIELD6_OFFSET 0 +#define RTL8367C_ACL_RULE_TEMPLATE0_CTRL3_FIELD6_MASK 0x7F + +#define RTL8367C_REG_ACL_RULE_TEMPLATE1_CTRL0 0x0604 +#define RTL8367C_ACL_RULE_TEMPLATE1_CTRL0_FIELD1_OFFSET 8 +#define RTL8367C_ACL_RULE_TEMPLATE1_CTRL0_FIELD1_MASK 0x7F00 +#define RTL8367C_ACL_RULE_TEMPLATE1_CTRL0_FIELD0_OFFSET 0 +#define RTL8367C_ACL_RULE_TEMPLATE1_CTRL0_FIELD0_MASK 0x7F + +#define RTL8367C_REG_ACL_RULE_TEMPLATE1_CTRL1 0x0605 +#define RTL8367C_ACL_RULE_TEMPLATE1_CTRL1_FIELD3_OFFSET 8 +#define RTL8367C_ACL_RULE_TEMPLATE1_CTRL1_FIELD3_MASK 0x7F00 +#define RTL8367C_ACL_RULE_TEMPLATE1_CTRL1_FIELD2_OFFSET 0 +#define RTL8367C_ACL_RULE_TEMPLATE1_CTRL1_FIELD2_MASK 0x7F + +#define RTL8367C_REG_ACL_RULE_TEMPLATE1_CTRL2 0x0606 +#define RTL8367C_ACL_RULE_TEMPLATE1_CTRL2_FIELD5_OFFSET 8 +#define RTL8367C_ACL_RULE_TEMPLATE1_CTRL2_FIELD5_MASK 0x7F00 +#define RTL8367C_ACL_RULE_TEMPLATE1_CTRL2_FIELD4_OFFSET 0 +#define RTL8367C_ACL_RULE_TEMPLATE1_CTRL2_FIELD4_MASK 0x7F + +#define RTL8367C_REG_ACL_RULE_TEMPLATE1_CTRL3 0x0607 +#define RTL8367C_ACL_RULE_TEMPLATE1_CTRL3_FIELD7_OFFSET 8 +#define RTL8367C_ACL_RULE_TEMPLATE1_CTRL3_FIELD7_MASK 0x7F00 +#define RTL8367C_ACL_RULE_TEMPLATE1_CTRL3_FIELD6_OFFSET 0 +#define RTL8367C_ACL_RULE_TEMPLATE1_CTRL3_FIELD6_MASK 0x7F + +#define RTL8367C_REG_ACL_RULE_TEMPLATE2_CTRL0 0x0608 +#define RTL8367C_ACL_RULE_TEMPLATE2_CTRL0_FIELD1_OFFSET 8 +#define RTL8367C_ACL_RULE_TEMPLATE2_CTRL0_FIELD1_MASK 0x7F00 +#define RTL8367C_ACL_RULE_TEMPLATE2_CTRL0_FIELD0_OFFSET 0 +#define RTL8367C_ACL_RULE_TEMPLATE2_CTRL0_FIELD0_MASK 0x7F + +#define RTL8367C_REG_ACL_RULE_TEMPLATE2_CTRL1 0x0609 +#define RTL8367C_ACL_RULE_TEMPLATE2_CTRL1_FIELD3_OFFSET 8 +#define RTL8367C_ACL_RULE_TEMPLATE2_CTRL1_FIELD3_MASK 0x7F00 +#define RTL8367C_ACL_RULE_TEMPLATE2_CTRL1_FIELD2_OFFSET 0 +#define RTL8367C_ACL_RULE_TEMPLATE2_CTRL1_FIELD2_MASK 0x7F + +#define RTL8367C_REG_ACL_RULE_TEMPLATE2_CTRL2 0x060a +#define RTL8367C_ACL_RULE_TEMPLATE2_CTRL2_FIELD5_OFFSET 8 +#define RTL8367C_ACL_RULE_TEMPLATE2_CTRL2_FIELD5_MASK 0x7F00 +#define RTL8367C_ACL_RULE_TEMPLATE2_CTRL2_FIELD4_OFFSET 0 +#define RTL8367C_ACL_RULE_TEMPLATE2_CTRL2_FIELD4_MASK 0x7F + +#define RTL8367C_REG_ACL_RULE_TEMPLATE2_CTRL3 0x060b +#define RTL8367C_ACL_RULE_TEMPLATE2_CTRL3_FIELD7_OFFSET 8 +#define RTL8367C_ACL_RULE_TEMPLATE2_CTRL3_FIELD7_MASK 0x7F00 +#define RTL8367C_ACL_RULE_TEMPLATE2_CTRL3_FIELD6_OFFSET 0 +#define RTL8367C_ACL_RULE_TEMPLATE2_CTRL3_FIELD6_MASK 0x7F + +#define RTL8367C_REG_ACL_RULE_TEMPLATE3_CTRL0 0x060c +#define RTL8367C_ACL_RULE_TEMPLATE3_CTRL0_FIELD1_OFFSET 8 +#define RTL8367C_ACL_RULE_TEMPLATE3_CTRL0_FIELD1_MASK 0x7F00 +#define RTL8367C_ACL_RULE_TEMPLATE3_CTRL0_FIELD0_OFFSET 0 +#define RTL8367C_ACL_RULE_TEMPLATE3_CTRL0_FIELD0_MASK 0x7F + +#define RTL8367C_REG_ACL_RULE_TEMPLATE3_CTRL1 0x060d +#define RTL8367C_ACL_RULE_TEMPLATE3_CTRL1_FIELD3_OFFSET 8 +#define RTL8367C_ACL_RULE_TEMPLATE3_CTRL1_FIELD3_MASK 0x7F00 +#define RTL8367C_ACL_RULE_TEMPLATE3_CTRL1_FIELD2_OFFSET 0 +#define RTL8367C_ACL_RULE_TEMPLATE3_CTRL1_FIELD2_MASK 0x7F + +#define RTL8367C_REG_ACL_RULE_TEMPLATE3_CTRL2 0x060e +#define RTL8367C_ACL_RULE_TEMPLATE3_CTRL2_FIELD5_OFFSET 8 +#define RTL8367C_ACL_RULE_TEMPLATE3_CTRL2_FIELD5_MASK 0x7F00 +#define RTL8367C_ACL_RULE_TEMPLATE3_CTRL2_FIELD4_OFFSET 0 +#define RTL8367C_ACL_RULE_TEMPLATE3_CTRL2_FIELD4_MASK 0x7F + +#define RTL8367C_REG_ACL_RULE_TEMPLATE3_CTRL3 0x060f +#define RTL8367C_ACL_RULE_TEMPLATE3_CTRL3_FIELD7_OFFSET 8 +#define RTL8367C_ACL_RULE_TEMPLATE3_CTRL3_FIELD7_MASK 0x7F00 +#define RTL8367C_ACL_RULE_TEMPLATE3_CTRL3_FIELD6_OFFSET 0 +#define RTL8367C_ACL_RULE_TEMPLATE3_CTRL3_FIELD6_MASK 0x7F + +#define RTL8367C_REG_ACL_RULE_TEMPLATE4_CTRL0 0x0610 +#define RTL8367C_ACL_RULE_TEMPLATE4_CTRL0_FIELD1_OFFSET 8 +#define RTL8367C_ACL_RULE_TEMPLATE4_CTRL0_FIELD1_MASK 0x7F00 +#define RTL8367C_ACL_RULE_TEMPLATE4_CTRL0_FIELD0_OFFSET 0 +#define RTL8367C_ACL_RULE_TEMPLATE4_CTRL0_FIELD0_MASK 0x7F + +#define RTL8367C_REG_ACL_RULE_TEMPLATE4_CTRL1 0x0611 +#define RTL8367C_ACL_RULE_TEMPLATE4_CTRL1_FIELD3_OFFSET 8 +#define RTL8367C_ACL_RULE_TEMPLATE4_CTRL1_FIELD3_MASK 0x7F00 +#define RTL8367C_ACL_RULE_TEMPLATE4_CTRL1_FIELD2_OFFSET 0 +#define RTL8367C_ACL_RULE_TEMPLATE4_CTRL1_FIELD2_MASK 0x7F + +#define RTL8367C_REG_ACL_RULE_TEMPLATE4_CTRL2 0x0612 +#define RTL8367C_ACL_RULE_TEMPLATE4_CTRL2_FIELD5_OFFSET 8 +#define RTL8367C_ACL_RULE_TEMPLATE4_CTRL2_FIELD5_MASK 0x7F00 +#define RTL8367C_ACL_RULE_TEMPLATE4_CTRL2_FIELD4_OFFSET 0 +#define RTL8367C_ACL_RULE_TEMPLATE4_CTRL2_FIELD4_MASK 0x7F + +#define RTL8367C_REG_ACL_RULE_TEMPLATE4_CTRL3 0x0613 +#define RTL8367C_ACL_RULE_TEMPLATE4_CTRL3_FIELD7_OFFSET 8 +#define RTL8367C_ACL_RULE_TEMPLATE4_CTRL3_FIELD7_MASK 0x7F00 +#define RTL8367C_ACL_RULE_TEMPLATE4_CTRL3_FIELD6_OFFSET 0 +#define RTL8367C_ACL_RULE_TEMPLATE4_CTRL3_FIELD6_MASK 0x7F + +#define RTL8367C_REG_ACL_ACTION_CTRL0 0x0614 +#define RTL8367C_OP1_NOT_OFFSET 14 +#define RTL8367C_OP1_NOT_MASK 0x4000 +#define RTL8367C_ACT1_GPIO_OFFSET 13 +#define RTL8367C_ACT1_GPIO_MASK 0x2000 +#define RTL8367C_ACT1_FORWARD_OFFSET 12 +#define RTL8367C_ACT1_FORWARD_MASK 0x1000 +#define RTL8367C_ACT1_POLICING_OFFSET 11 +#define RTL8367C_ACT1_POLICING_MASK 0x800 +#define RTL8367C_ACT1_PRIORITY_OFFSET 10 +#define RTL8367C_ACT1_PRIORITY_MASK 0x400 +#define RTL8367C_ACT1_SVID_OFFSET 9 +#define RTL8367C_ACT1_SVID_MASK 0x200 +#define RTL8367C_ACT1_CVID_OFFSET 8 +#define RTL8367C_ACT1_CVID_MASK 0x100 +#define RTL8367C_OP0_NOT_OFFSET 6 +#define RTL8367C_OP0_NOT_MASK 0x40 +#define RTL8367C_ACT0_GPIO_OFFSET 5 +#define RTL8367C_ACT0_GPIO_MASK 0x20 +#define RTL8367C_ACT0_FORWARD_OFFSET 4 +#define RTL8367C_ACT0_FORWARD_MASK 0x10 +#define RTL8367C_ACT0_POLICING_OFFSET 3 +#define RTL8367C_ACT0_POLICING_MASK 0x8 +#define RTL8367C_ACT0_PRIORITY_OFFSET 2 +#define RTL8367C_ACT0_PRIORITY_MASK 0x4 +#define RTL8367C_ACT0_SVID_OFFSET 1 +#define RTL8367C_ACT0_SVID_MASK 0x2 +#define RTL8367C_ACT0_CVID_OFFSET 0 +#define RTL8367C_ACT0_CVID_MASK 0x1 + +#define RTL8367C_REG_ACL_ACTION_CTRL1 0x0615 +#define RTL8367C_OP3_NOT_OFFSET 14 +#define RTL8367C_OP3_NOT_MASK 0x4000 +#define RTL8367C_ACT3_GPIO_OFFSET 13 +#define RTL8367C_ACT3_GPIO_MASK 0x2000 +#define RTL8367C_ACT3_FORWARD_OFFSET 12 +#define RTL8367C_ACT3_FORWARD_MASK 0x1000 +#define RTL8367C_ACT3_POLICING_OFFSET 11 +#define RTL8367C_ACT3_POLICING_MASK 0x800 +#define RTL8367C_ACT3_PRIORITY_OFFSET 10 +#define RTL8367C_ACT3_PRIORITY_MASK 0x400 +#define RTL8367C_ACT3_SVID_OFFSET 9 +#define RTL8367C_ACT3_SVID_MASK 0x200 +#define RTL8367C_ACT3_CVID_OFFSET 8 +#define RTL8367C_ACT3_CVID_MASK 0x100 +#define RTL8367C_OP2_NOT_OFFSET 6 +#define RTL8367C_OP2_NOT_MASK 0x40 +#define RTL8367C_ACT2_GPIO_OFFSET 5 +#define RTL8367C_ACT2_GPIO_MASK 0x20 +#define RTL8367C_ACT2_FORWARD_OFFSET 4 +#define RTL8367C_ACT2_FORWARD_MASK 0x10 +#define RTL8367C_ACT2_POLICING_OFFSET 3 +#define RTL8367C_ACT2_POLICING_MASK 0x8 +#define RTL8367C_ACT2_PRIORITY_OFFSET 2 +#define RTL8367C_ACT2_PRIORITY_MASK 0x4 +#define RTL8367C_ACT2_SVID_OFFSET 1 +#define RTL8367C_ACT2_SVID_MASK 0x2 +#define RTL8367C_ACT2_CVID_OFFSET 0 +#define RTL8367C_ACT2_CVID_MASK 0x1 + +#define RTL8367C_REG_ACL_ACTION_CTRL2 0x0616 +#define RTL8367C_OP5_NOT_OFFSET 14 +#define RTL8367C_OP5_NOT_MASK 0x4000 +#define RTL8367C_ACT5_GPIO_OFFSET 13 +#define RTL8367C_ACT5_GPIO_MASK 0x2000 +#define RTL8367C_ACT5_FORWARD_OFFSET 12 +#define RTL8367C_ACT5_FORWARD_MASK 0x1000 +#define RTL8367C_ACT5_POLICING_OFFSET 11 +#define RTL8367C_ACT5_POLICING_MASK 0x800 +#define RTL8367C_ACT5_PRIORITY_OFFSET 10 +#define RTL8367C_ACT5_PRIORITY_MASK 0x400 +#define RTL8367C_ACT5_SVID_OFFSET 9 +#define RTL8367C_ACT5_SVID_MASK 0x200 +#define RTL8367C_ACT5_CVID_OFFSET 8 +#define RTL8367C_ACT5_CVID_MASK 0x100 +#define RTL8367C_OP4_NOT_OFFSET 6 +#define RTL8367C_OP4_NOT_MASK 0x40 +#define RTL8367C_ACT4_GPIO_OFFSET 5 +#define RTL8367C_ACT4_GPIO_MASK 0x20 +#define RTL8367C_ACT4_FORWARD_OFFSET 4 +#define RTL8367C_ACT4_FORWARD_MASK 0x10 +#define RTL8367C_ACT4_POLICING_OFFSET 3 +#define RTL8367C_ACT4_POLICING_MASK 0x8 +#define RTL8367C_ACT4_PRIORITY_OFFSET 2 +#define RTL8367C_ACT4_PRIORITY_MASK 0x4 +#define RTL8367C_ACT4_SVID_OFFSET 1 +#define RTL8367C_ACT4_SVID_MASK 0x2 +#define RTL8367C_ACT4_CVID_OFFSET 0 +#define RTL8367C_ACT4_CVID_MASK 0x1 + +#define RTL8367C_REG_ACL_ACTION_CTRL3 0x0617 +#define RTL8367C_OP7_NOT_OFFSET 14 +#define RTL8367C_OP7_NOT_MASK 0x4000 +#define RTL8367C_ACT7_GPIO_OFFSET 13 +#define RTL8367C_ACT7_GPIO_MASK 0x2000 +#define RTL8367C_ACT7_FORWARD_OFFSET 12 +#define RTL8367C_ACT7_FORWARD_MASK 0x1000 +#define RTL8367C_ACT7_POLICING_OFFSET 11 +#define RTL8367C_ACT7_POLICING_MASK 0x800 +#define RTL8367C_ACT7_PRIORITY_OFFSET 10 +#define RTL8367C_ACT7_PRIORITY_MASK 0x400 +#define RTL8367C_ACT7_SVID_OFFSET 9 +#define RTL8367C_ACT7_SVID_MASK 0x200 +#define RTL8367C_ACT7_CVID_OFFSET 8 +#define RTL8367C_ACT7_CVID_MASK 0x100 +#define RTL8367C_OP6_NOT_OFFSET 6 +#define RTL8367C_OP6_NOT_MASK 0x40 +#define RTL8367C_ACT6_GPIO_OFFSET 5 +#define RTL8367C_ACT6_GPIO_MASK 0x20 +#define RTL8367C_ACT6_FORWARD_OFFSET 4 +#define RTL8367C_ACT6_FORWARD_MASK 0x10 +#define RTL8367C_ACT6_POLICING_OFFSET 3 +#define RTL8367C_ACT6_POLICING_MASK 0x8 +#define RTL8367C_ACT6_PRIORITY_OFFSET 2 +#define RTL8367C_ACT6_PRIORITY_MASK 0x4 +#define RTL8367C_ACT6_SVID_OFFSET 1 +#define RTL8367C_ACT6_SVID_MASK 0x2 +#define RTL8367C_ACT6_CVID_OFFSET 0 +#define RTL8367C_ACT6_CVID_MASK 0x1 + +#define RTL8367C_REG_ACL_ACTION_CTRL4 0x0618 +#define RTL8367C_OP9_NOT_OFFSET 14 +#define RTL8367C_OP9_NOT_MASK 0x4000 +#define RTL8367C_ACT9_GPIO_OFFSET 13 +#define RTL8367C_ACT9_GPIO_MASK 0x2000 +#define RTL8367C_ACT9_FORWARD_OFFSET 12 +#define RTL8367C_ACT9_FORWARD_MASK 0x1000 +#define RTL8367C_ACT9_POLICING_OFFSET 11 +#define RTL8367C_ACT9_POLICING_MASK 0x800 +#define RTL8367C_ACT9_PRIORITY_OFFSET 10 +#define RTL8367C_ACT9_PRIORITY_MASK 0x400 +#define RTL8367C_ACT9_SVID_OFFSET 9 +#define RTL8367C_ACT9_SVID_MASK 0x200 +#define RTL8367C_ACT9_CVID_OFFSET 8 +#define RTL8367C_ACT9_CVID_MASK 0x100 +#define RTL8367C_OP8_NOT_OFFSET 6 +#define RTL8367C_OP8_NOT_MASK 0x40 +#define RTL8367C_ACT8_GPIO_OFFSET 5 +#define RTL8367C_ACT8_GPIO_MASK 0x20 +#define RTL8367C_ACT8_FORWARD_OFFSET 4 +#define RTL8367C_ACT8_FORWARD_MASK 0x10 +#define RTL8367C_ACT8_POLICING_OFFSET 3 +#define RTL8367C_ACT8_POLICING_MASK 0x8 +#define RTL8367C_ACT8_PRIORITY_OFFSET 2 +#define RTL8367C_ACT8_PRIORITY_MASK 0x4 +#define RTL8367C_ACT8_SVID_OFFSET 1 +#define RTL8367C_ACT8_SVID_MASK 0x2 +#define RTL8367C_ACT8_CVID_OFFSET 0 +#define RTL8367C_ACT8_CVID_MASK 0x1 + +#define RTL8367C_REG_ACL_ACTION_CTRL5 0x0619 +#define RTL8367C_OP11_NOT_OFFSET 14 +#define RTL8367C_OP11_NOT_MASK 0x4000 +#define RTL8367C_ACT11_GPIO_OFFSET 13 +#define RTL8367C_ACT11_GPIO_MASK 0x2000 +#define RTL8367C_ACT11_FORWARD_OFFSET 12 +#define RTL8367C_ACT11_FORWARD_MASK 0x1000 +#define RTL8367C_ACT11_POLICING_OFFSET 11 +#define RTL8367C_ACT11_POLICING_MASK 0x800 +#define RTL8367C_ACT11_PRIORITY_OFFSET 10 +#define RTL8367C_ACT11_PRIORITY_MASK 0x400 +#define RTL8367C_ACT11_SVID_OFFSET 9 +#define RTL8367C_ACT11_SVID_MASK 0x200 +#define RTL8367C_ACT11_CVID_OFFSET 8 +#define RTL8367C_ACT11_CVID_MASK 0x100 +#define RTL8367C_OP10_NOT_OFFSET 6 +#define RTL8367C_OP10_NOT_MASK 0x40 +#define RTL8367C_ACT10_GPIO_OFFSET 5 +#define RTL8367C_ACT10_GPIO_MASK 0x20 +#define RTL8367C_ACT10_FORWARD_OFFSET 4 +#define RTL8367C_ACT10_FORWARD_MASK 0x10 +#define RTL8367C_ACT10_POLICING_OFFSET 3 +#define RTL8367C_ACT10_POLICING_MASK 0x8 +#define RTL8367C_ACT10_PRIORITY_OFFSET 2 +#define RTL8367C_ACT10_PRIORITY_MASK 0x4 +#define RTL8367C_ACT10_SVID_OFFSET 1 +#define RTL8367C_ACT10_SVID_MASK 0x2 +#define RTL8367C_ACT10_CVID_OFFSET 0 +#define RTL8367C_ACT10_CVID_MASK 0x1 + +#define RTL8367C_REG_ACL_ACTION_CTRL6 0x061a +#define RTL8367C_OP13_NOT_OFFSET 14 +#define RTL8367C_OP13_NOT_MASK 0x4000 +#define RTL8367C_ACT13_GPIO_OFFSET 13 +#define RTL8367C_ACT13_GPIO_MASK 0x2000 +#define RTL8367C_ACT13_FORWARD_OFFSET 12 +#define RTL8367C_ACT13_FORWARD_MASK 0x1000 +#define RTL8367C_ACT13_POLICING_OFFSET 11 +#define RTL8367C_ACT13_POLICING_MASK 0x800 +#define RTL8367C_ACT13_PRIORITY_OFFSET 10 +#define RTL8367C_ACT13_PRIORITY_MASK 0x400 +#define RTL8367C_ACT13_SVID_OFFSET 9 +#define RTL8367C_ACT13_SVID_MASK 0x200 +#define RTL8367C_ACT13_CVID_OFFSET 8 +#define RTL8367C_ACT13_CVID_MASK 0x100 +#define RTL8367C_OP12_NOT_OFFSET 6 +#define RTL8367C_OP12_NOT_MASK 0x40 +#define RTL8367C_ACT12_GPIO_OFFSET 5 +#define RTL8367C_ACT12_GPIO_MASK 0x20 +#define RTL8367C_ACT12_FORWARD_OFFSET 4 +#define RTL8367C_ACT12_FORWARD_MASK 0x10 +#define RTL8367C_ACT12_POLICING_OFFSET 3 +#define RTL8367C_ACT12_POLICING_MASK 0x8 +#define RTL8367C_ACT12_PRIORITY_OFFSET 2 +#define RTL8367C_ACT12_PRIORITY_MASK 0x4 +#define RTL8367C_ACT12_SVID_OFFSET 1 +#define RTL8367C_ACT12_SVID_MASK 0x2 +#define RTL8367C_ACT12_CVID_OFFSET 0 +#define RTL8367C_ACT12_CVID_MASK 0x1 + +#define RTL8367C_REG_ACL_ACTION_CTRL7 0x061b +#define RTL8367C_OP15_NOT_OFFSET 14 +#define RTL8367C_OP15_NOT_MASK 0x4000 +#define RTL8367C_ACT15_GPIO_OFFSET 13 +#define RTL8367C_ACT15_GPIO_MASK 0x2000 +#define RTL8367C_ACT15_FORWARD_OFFSET 12 +#define RTL8367C_ACT15_FORWARD_MASK 0x1000 +#define RTL8367C_ACT15_POLICING_OFFSET 11 +#define RTL8367C_ACT15_POLICING_MASK 0x800 +#define RTL8367C_ACT15_PRIORITY_OFFSET 10 +#define RTL8367C_ACT15_PRIORITY_MASK 0x400 +#define RTL8367C_ACT15_SVID_OFFSET 9 +#define RTL8367C_ACT15_SVID_MASK 0x200 +#define RTL8367C_ACT15_CVID_OFFSET 8 +#define RTL8367C_ACT15_CVID_MASK 0x100 +#define RTL8367C_OP14_NOT_OFFSET 6 +#define RTL8367C_OP14_NOT_MASK 0x40 +#define RTL8367C_ACT14_GPIO_OFFSET 5 +#define RTL8367C_ACT14_GPIO_MASK 0x20 +#define RTL8367C_ACT14_FORWARD_OFFSET 4 +#define RTL8367C_ACT14_FORWARD_MASK 0x10 +#define RTL8367C_ACT14_POLICING_OFFSET 3 +#define RTL8367C_ACT14_POLICING_MASK 0x8 +#define RTL8367C_ACT14_PRIORITY_OFFSET 2 +#define RTL8367C_ACT14_PRIORITY_MASK 0x4 +#define RTL8367C_ACT14_SVID_OFFSET 1 +#define RTL8367C_ACT14_SVID_MASK 0x2 +#define RTL8367C_ACT14_CVID_OFFSET 0 +#define RTL8367C_ACT14_CVID_MASK 0x1 + +#define RTL8367C_REG_ACL_ACTION_CTRL8 0x061c +#define RTL8367C_OP17_NOT_OFFSET 14 +#define RTL8367C_OP17_NOT_MASK 0x4000 +#define RTL8367C_ACT17_GPIO_OFFSET 13 +#define RTL8367C_ACT17_GPIO_MASK 0x2000 +#define RTL8367C_ACT17_FORWARD_OFFSET 12 +#define RTL8367C_ACT17_FORWARD_MASK 0x1000 +#define RTL8367C_ACT17_POLICING_OFFSET 11 +#define RTL8367C_ACT17_POLICING_MASK 0x800 +#define RTL8367C_ACT17_PRIORITY_OFFSET 10 +#define RTL8367C_ACT17_PRIORITY_MASK 0x400 +#define RTL8367C_ACT17_SVID_OFFSET 9 +#define RTL8367C_ACT17_SVID_MASK 0x200 +#define RTL8367C_ACT17_CVID_OFFSET 8 +#define RTL8367C_ACT17_CVID_MASK 0x100 +#define RTL8367C_OP16_NOT_OFFSET 6 +#define RTL8367C_OP16_NOT_MASK 0x40 +#define RTL8367C_ACT16_GPIO_OFFSET 5 +#define RTL8367C_ACT16_GPIO_MASK 0x20 +#define RTL8367C_ACT16_FORWARD_OFFSET 4 +#define RTL8367C_ACT16_FORWARD_MASK 0x10 +#define RTL8367C_ACT16_POLICING_OFFSET 3 +#define RTL8367C_ACT16_POLICING_MASK 0x8 +#define RTL8367C_ACT16_PRIORITY_OFFSET 2 +#define RTL8367C_ACT16_PRIORITY_MASK 0x4 +#define RTL8367C_ACT16_SVID_OFFSET 1 +#define RTL8367C_ACT16_SVID_MASK 0x2 +#define RTL8367C_ACT16_CVID_OFFSET 0 +#define RTL8367C_ACT16_CVID_MASK 0x1 + +#define RTL8367C_REG_ACL_ACTION_CTRL9 0x061d +#define RTL8367C_OP19_NOT_OFFSET 14 +#define RTL8367C_OP19_NOT_MASK 0x4000 +#define RTL8367C_ACT19_GPIO_OFFSET 13 +#define RTL8367C_ACT19_GPIO_MASK 0x2000 +#define RTL8367C_ACT19_FORWARD_OFFSET 12 +#define RTL8367C_ACT19_FORWARD_MASK 0x1000 +#define RTL8367C_ACT19_POLICING_OFFSET 11 +#define RTL8367C_ACT19_POLICING_MASK 0x800 +#define RTL8367C_ACT19_PRIORITY_OFFSET 10 +#define RTL8367C_ACT19_PRIORITY_MASK 0x400 +#define RTL8367C_ACT19_SVID_OFFSET 9 +#define RTL8367C_ACT19_SVID_MASK 0x200 +#define RTL8367C_ACT19_CVID_OFFSET 8 +#define RTL8367C_ACT19_CVID_MASK 0x100 +#define RTL8367C_OP18_NOT_OFFSET 6 +#define RTL8367C_OP18_NOT_MASK 0x40 +#define RTL8367C_ACT18_GPIO_OFFSET 5 +#define RTL8367C_ACT18_GPIO_MASK 0x20 +#define RTL8367C_ACT18_FORWARD_OFFSET 4 +#define RTL8367C_ACT18_FORWARD_MASK 0x10 +#define RTL8367C_ACT18_POLICING_OFFSET 3 +#define RTL8367C_ACT18_POLICING_MASK 0x8 +#define RTL8367C_ACT18_PRIORITY_OFFSET 2 +#define RTL8367C_ACT18_PRIORITY_MASK 0x4 +#define RTL8367C_ACT18_SVID_OFFSET 1 +#define RTL8367C_ACT18_SVID_MASK 0x2 +#define RTL8367C_ACT18_CVID_OFFSET 0 +#define RTL8367C_ACT18_CVID_MASK 0x1 + +#define RTL8367C_REG_ACL_ACTION_CTRL10 0x061e +#define RTL8367C_OP21_NOT_OFFSET 14 +#define RTL8367C_OP21_NOT_MASK 0x4000 +#define RTL8367C_ACT21_GPIO_OFFSET 13 +#define RTL8367C_ACT21_GPIO_MASK 0x2000 +#define RTL8367C_ACT21_FORWARD_OFFSET 12 +#define RTL8367C_ACT21_FORWARD_MASK 0x1000 +#define RTL8367C_ACT21_POLICING_OFFSET 11 +#define RTL8367C_ACT21_POLICING_MASK 0x800 +#define RTL8367C_ACT21_PRIORITY_OFFSET 10 +#define RTL8367C_ACT21_PRIORITY_MASK 0x400 +#define RTL8367C_ACT21_SVID_OFFSET 9 +#define RTL8367C_ACT21_SVID_MASK 0x200 +#define RTL8367C_ACT21_CVID_OFFSET 8 +#define RTL8367C_ACT21_CVID_MASK 0x100 +#define RTL8367C_OP20_NOT_OFFSET 6 +#define RTL8367C_OP20_NOT_MASK 0x40 +#define RTL8367C_ACT20_GPIO_OFFSET 5 +#define RTL8367C_ACT20_GPIO_MASK 0x20 +#define RTL8367C_ACT20_FORWARD_OFFSET 4 +#define RTL8367C_ACT20_FORWARD_MASK 0x10 +#define RTL8367C_ACT20_POLICING_OFFSET 3 +#define RTL8367C_ACT20_POLICING_MASK 0x8 +#define RTL8367C_ACT20_PRIORITY_OFFSET 2 +#define RTL8367C_ACT20_PRIORITY_MASK 0x4 +#define RTL8367C_ACT20_SVID_OFFSET 1 +#define RTL8367C_ACT20_SVID_MASK 0x2 +#define RTL8367C_ACT20_CVID_OFFSET 0 +#define RTL8367C_ACT20_CVID_MASK 0x1 + +#define RTL8367C_REG_ACL_ACTION_CTRL11 0x061f +#define RTL8367C_OP23_NOT_OFFSET 14 +#define RTL8367C_OP23_NOT_MASK 0x4000 +#define RTL8367C_ACT23_GPIO_OFFSET 13 +#define RTL8367C_ACT23_GPIO_MASK 0x2000 +#define RTL8367C_ACT23_FORWARD_OFFSET 12 +#define RTL8367C_ACT23_FORWARD_MASK 0x1000 +#define RTL8367C_ACT23_POLICING_OFFSET 11 +#define RTL8367C_ACT23_POLICING_MASK 0x800 +#define RTL8367C_ACT23_PRIORITY_OFFSET 10 +#define RTL8367C_ACT23_PRIORITY_MASK 0x400 +#define RTL8367C_ACT23_SVID_OFFSET 9 +#define RTL8367C_ACT23_SVID_MASK 0x200 +#define RTL8367C_ACT23_CVID_OFFSET 8 +#define RTL8367C_ACT23_CVID_MASK 0x100 +#define RTL8367C_OP22_NOT_OFFSET 6 +#define RTL8367C_OP22_NOT_MASK 0x40 +#define RTL8367C_ACT22_GPIO_OFFSET 5 +#define RTL8367C_ACT22_GPIO_MASK 0x20 +#define RTL8367C_ACT22_FORWARD_OFFSET 4 +#define RTL8367C_ACT22_FORWARD_MASK 0x10 +#define RTL8367C_ACT22_POLICING_OFFSET 3 +#define RTL8367C_ACT22_POLICING_MASK 0x8 +#define RTL8367C_ACT22_PRIORITY_OFFSET 2 +#define RTL8367C_ACT22_PRIORITY_MASK 0x4 +#define RTL8367C_ACT22_SVID_OFFSET 1 +#define RTL8367C_ACT22_SVID_MASK 0x2 +#define RTL8367C_ACT22_CVID_OFFSET 0 +#define RTL8367C_ACT22_CVID_MASK 0x1 + +#define RTL8367C_REG_ACL_ACTION_CTRL12 0x0620 +#define RTL8367C_OP25_NOT_OFFSET 14 +#define RTL8367C_OP25_NOT_MASK 0x4000 +#define RTL8367C_ACT25_GPIO_OFFSET 13 +#define RTL8367C_ACT25_GPIO_MASK 0x2000 +#define RTL8367C_ACT25_FORWARD_OFFSET 12 +#define RTL8367C_ACT25_FORWARD_MASK 0x1000 +#define RTL8367C_ACT25_POLICING_OFFSET 11 +#define RTL8367C_ACT25_POLICING_MASK 0x800 +#define RTL8367C_ACT25_PRIORITY_OFFSET 10 +#define RTL8367C_ACT25_PRIORITY_MASK 0x400 +#define RTL8367C_ACT25_SVID_OFFSET 9 +#define RTL8367C_ACT25_SVID_MASK 0x200 +#define RTL8367C_ACT25_CVID_OFFSET 8 +#define RTL8367C_ACT25_CVID_MASK 0x100 +#define RTL8367C_OP24_NOT_OFFSET 6 +#define RTL8367C_OP24_NOT_MASK 0x40 +#define RTL8367C_ACT24_GPIO_OFFSET 5 +#define RTL8367C_ACT24_GPIO_MASK 0x20 +#define RTL8367C_ACT24_FORWARD_OFFSET 4 +#define RTL8367C_ACT24_FORWARD_MASK 0x10 +#define RTL8367C_ACT24_POLICING_OFFSET 3 +#define RTL8367C_ACT24_POLICING_MASK 0x8 +#define RTL8367C_ACT24_PRIORITY_OFFSET 2 +#define RTL8367C_ACT24_PRIORITY_MASK 0x4 +#define RTL8367C_ACT24_SVID_OFFSET 1 +#define RTL8367C_ACT24_SVID_MASK 0x2 +#define RTL8367C_ACT24_CVID_OFFSET 0 +#define RTL8367C_ACT24_CVID_MASK 0x1 + +#define RTL8367C_REG_ACL_ACTION_CTRL13 0x0621 +#define RTL8367C_OP27_NOT_OFFSET 14 +#define RTL8367C_OP27_NOT_MASK 0x4000 +#define RTL8367C_ACT27_GPIO_OFFSET 13 +#define RTL8367C_ACT27_GPIO_MASK 0x2000 +#define RTL8367C_ACT27_FORWARD_OFFSET 12 +#define RTL8367C_ACT27_FORWARD_MASK 0x1000 +#define RTL8367C_ACT27_POLICING_OFFSET 11 +#define RTL8367C_ACT27_POLICING_MASK 0x800 +#define RTL8367C_ACT27_PRIORITY_OFFSET 10 +#define RTL8367C_ACT27_PRIORITY_MASK 0x400 +#define RTL8367C_ACT27_SVID_OFFSET 9 +#define RTL8367C_ACT27_SVID_MASK 0x200 +#define RTL8367C_ACT27_CVID_OFFSET 8 +#define RTL8367C_ACT27_CVID_MASK 0x100 +#define RTL8367C_OP26_NOT_OFFSET 6 +#define RTL8367C_OP26_NOT_MASK 0x40 +#define RTL8367C_ACT26_GPIO_OFFSET 5 +#define RTL8367C_ACT26_GPIO_MASK 0x20 +#define RTL8367C_ACT26_FORWARD_OFFSET 4 +#define RTL8367C_ACT26_FORWARD_MASK 0x10 +#define RTL8367C_ACT26_POLICING_OFFSET 3 +#define RTL8367C_ACT26_POLICING_MASK 0x8 +#define RTL8367C_ACT26_PRIORITY_OFFSET 2 +#define RTL8367C_ACT26_PRIORITY_MASK 0x4 +#define RTL8367C_ACT26_SVID_OFFSET 1 +#define RTL8367C_ACT26_SVID_MASK 0x2 +#define RTL8367C_ACT26_CVID_OFFSET 0 +#define RTL8367C_ACT26_CVID_MASK 0x1 + +#define RTL8367C_REG_ACL_ACTION_CTRL14 0x0622 +#define RTL8367C_OP29_NOT_OFFSET 14 +#define RTL8367C_OP29_NOT_MASK 0x4000 +#define RTL8367C_ACT29_GPIO_OFFSET 13 +#define RTL8367C_ACT29_GPIO_MASK 0x2000 +#define RTL8367C_ACT29_FORWARD_OFFSET 12 +#define RTL8367C_ACT29_FORWARD_MASK 0x1000 +#define RTL8367C_ACT29_POLICING_OFFSET 11 +#define RTL8367C_ACT29_POLICING_MASK 0x800 +#define RTL8367C_ACT29_PRIORITY_OFFSET 10 +#define RTL8367C_ACT29_PRIORITY_MASK 0x400 +#define RTL8367C_ACT29_SVID_OFFSET 9 +#define RTL8367C_ACT29_SVID_MASK 0x200 +#define RTL8367C_ACT29_CVID_OFFSET 8 +#define RTL8367C_ACT29_CVID_MASK 0x100 +#define RTL8367C_OP28_NOT_OFFSET 6 +#define RTL8367C_OP28_NOT_MASK 0x40 +#define RTL8367C_ACT28_GPIO_OFFSET 5 +#define RTL8367C_ACT28_GPIO_MASK 0x20 +#define RTL8367C_ACT28_FORWARD_OFFSET 4 +#define RTL8367C_ACT28_FORWARD_MASK 0x10 +#define RTL8367C_ACT28_POLICING_OFFSET 3 +#define RTL8367C_ACT28_POLICING_MASK 0x8 +#define RTL8367C_ACT28_PRIORITY_OFFSET 2 +#define RTL8367C_ACT28_PRIORITY_MASK 0x4 +#define RTL8367C_ACT28_SVID_OFFSET 1 +#define RTL8367C_ACT28_SVID_MASK 0x2 +#define RTL8367C_ACT28_CVID_OFFSET 0 +#define RTL8367C_ACT28_CVID_MASK 0x1 + +#define RTL8367C_REG_ACL_ACTION_CTRL15 0x0623 +#define RTL8367C_OP31_NOT_OFFSET 14 +#define RTL8367C_OP31_NOT_MASK 0x4000 +#define RTL8367C_ACT31_GPIO_OFFSET 13 +#define RTL8367C_ACT31_GPIO_MASK 0x2000 +#define RTL8367C_ACT31_FORWARD_OFFSET 12 +#define RTL8367C_ACT31_FORWARD_MASK 0x1000 +#define RTL8367C_ACT31_POLICING_OFFSET 11 +#define RTL8367C_ACT31_POLICING_MASK 0x800 +#define RTL8367C_ACT31_PRIORITY_OFFSET 10 +#define RTL8367C_ACT31_PRIORITY_MASK 0x400 +#define RTL8367C_ACT31_SVID_OFFSET 9 +#define RTL8367C_ACT31_SVID_MASK 0x200 +#define RTL8367C_ACT31_CVID_OFFSET 8 +#define RTL8367C_ACT31_CVID_MASK 0x100 +#define RTL8367C_OP30_NOT_OFFSET 6 +#define RTL8367C_OP30_NOT_MASK 0x40 +#define RTL8367C_ACT30_GPIO_OFFSET 5 +#define RTL8367C_ACT30_GPIO_MASK 0x20 +#define RTL8367C_ACT30_FORWARD_OFFSET 4 +#define RTL8367C_ACT30_FORWARD_MASK 0x10 +#define RTL8367C_ACT30_POLICING_OFFSET 3 +#define RTL8367C_ACT30_POLICING_MASK 0x8 +#define RTL8367C_ACT30_PRIORITY_OFFSET 2 +#define RTL8367C_ACT30_PRIORITY_MASK 0x4 +#define RTL8367C_ACT30_SVID_OFFSET 1 +#define RTL8367C_ACT30_SVID_MASK 0x2 +#define RTL8367C_ACT30_CVID_OFFSET 0 +#define RTL8367C_ACT30_CVID_MASK 0x1 + +#define RTL8367C_REG_ACL_ACTION_CTRL16 0x0624 +#define RTL8367C_OP33_NOT_OFFSET 14 +#define RTL8367C_OP33_NOT_MASK 0x4000 +#define RTL8367C_ACT33_GPIO_OFFSET 13 +#define RTL8367C_ACT33_GPIO_MASK 0x2000 +#define RTL8367C_ACT33_FORWARD_OFFSET 12 +#define RTL8367C_ACT33_FORWARD_MASK 0x1000 +#define RTL8367C_ACT33_POLICING_OFFSET 11 +#define RTL8367C_ACT33_POLICING_MASK 0x800 +#define RTL8367C_ACT33_PRIORITY_OFFSET 10 +#define RTL8367C_ACT33_PRIORITY_MASK 0x400 +#define RTL8367C_ACT33_SVID_OFFSET 9 +#define RTL8367C_ACT33_SVID_MASK 0x200 +#define RTL8367C_ACT33_CVID_OFFSET 8 +#define RTL8367C_ACT33_CVID_MASK 0x100 +#define RTL8367C_OP32_NOT_OFFSET 6 +#define RTL8367C_OP32_NOT_MASK 0x40 +#define RTL8367C_ACT32_GPIO_OFFSET 5 +#define RTL8367C_ACT32_GPIO_MASK 0x20 +#define RTL8367C_ACT32_FORWARD_OFFSET 4 +#define RTL8367C_ACT32_FORWARD_MASK 0x10 +#define RTL8367C_ACT32_POLICING_OFFSET 3 +#define RTL8367C_ACT32_POLICING_MASK 0x8 +#define RTL8367C_ACT32_PRIORITY_OFFSET 2 +#define RTL8367C_ACT32_PRIORITY_MASK 0x4 +#define RTL8367C_ACT32_SVID_OFFSET 1 +#define RTL8367C_ACT32_SVID_MASK 0x2 +#define RTL8367C_ACT32_CVID_OFFSET 0 +#define RTL8367C_ACT32_CVID_MASK 0x1 + +#define RTL8367C_REG_ACL_ACTION_CTRL17 0x0625 +#define RTL8367C_OP35_NOT_OFFSET 14 +#define RTL8367C_OP35_NOT_MASK 0x4000 +#define RTL8367C_ACT35_GPIO_OFFSET 13 +#define RTL8367C_ACT35_GPIO_MASK 0x2000 +#define RTL8367C_ACT35_FORWARD_OFFSET 12 +#define RTL8367C_ACT35_FORWARD_MASK 0x1000 +#define RTL8367C_ACT35_POLICING_OFFSET 11 +#define RTL8367C_ACT35_POLICING_MASK 0x800 +#define RTL8367C_ACT35_PRIORITY_OFFSET 10 +#define RTL8367C_ACT35_PRIORITY_MASK 0x400 +#define RTL8367C_ACT35_SVID_OFFSET 9 +#define RTL8367C_ACT35_SVID_MASK 0x200 +#define RTL8367C_ACT35_CVID_OFFSET 8 +#define RTL8367C_ACT35_CVID_MASK 0x100 +#define RTL8367C_OP34_NOT_OFFSET 6 +#define RTL8367C_OP34_NOT_MASK 0x40 +#define RTL8367C_ACT34_GPIO_OFFSET 5 +#define RTL8367C_ACT34_GPIO_MASK 0x20 +#define RTL8367C_ACT34_FORWARD_OFFSET 4 +#define RTL8367C_ACT34_FORWARD_MASK 0x10 +#define RTL8367C_ACT34_POLICING_OFFSET 3 +#define RTL8367C_ACT34_POLICING_MASK 0x8 +#define RTL8367C_ACT34_PRIORITY_OFFSET 2 +#define RTL8367C_ACT34_PRIORITY_MASK 0x4 +#define RTL8367C_ACT34_SVID_OFFSET 1 +#define RTL8367C_ACT34_SVID_MASK 0x2 +#define RTL8367C_ACT34_CVID_OFFSET 0 +#define RTL8367C_ACT34_CVID_MASK 0x1 + +#define RTL8367C_REG_ACL_ACTION_CTRL18 0x0626 +#define RTL8367C_OP37_NOT_OFFSET 14 +#define RTL8367C_OP37_NOT_MASK 0x4000 +#define RTL8367C_ACT37_GPIO_OFFSET 13 +#define RTL8367C_ACT37_GPIO_MASK 0x2000 +#define RTL8367C_ACT37_FORWARD_OFFSET 12 +#define RTL8367C_ACT37_FORWARD_MASK 0x1000 +#define RTL8367C_ACT37_POLICING_OFFSET 11 +#define RTL8367C_ACT37_POLICING_MASK 0x800 +#define RTL8367C_ACT37_PRIORITY_OFFSET 10 +#define RTL8367C_ACT37_PRIORITY_MASK 0x400 +#define RTL8367C_ACT37_SVID_OFFSET 9 +#define RTL8367C_ACT37_SVID_MASK 0x200 +#define RTL8367C_ACT37_CVID_OFFSET 8 +#define RTL8367C_ACT37_CVID_MASK 0x100 +#define RTL8367C_OP36_NOT_OFFSET 6 +#define RTL8367C_OP36_NOT_MASK 0x40 +#define RTL8367C_ACT36_GPIO_OFFSET 5 +#define RTL8367C_ACT36_GPIO_MASK 0x20 +#define RTL8367C_ACT36_FORWARD_OFFSET 4 +#define RTL8367C_ACT36_FORWARD_MASK 0x10 +#define RTL8367C_ACT36_POLICING_OFFSET 3 +#define RTL8367C_ACT36_POLICING_MASK 0x8 +#define RTL8367C_ACT36_PRIORITY_OFFSET 2 +#define RTL8367C_ACT36_PRIORITY_MASK 0x4 +#define RTL8367C_ACT36_SVID_OFFSET 1 +#define RTL8367C_ACT36_SVID_MASK 0x2 +#define RTL8367C_ACT36_CVID_OFFSET 0 +#define RTL8367C_ACT36_CVID_MASK 0x1 + +#define RTL8367C_REG_ACL_ACTION_CTRL19 0x0627 +#define RTL8367C_OP39_NOT_OFFSET 14 +#define RTL8367C_OP39_NOT_MASK 0x4000 +#define RTL8367C_ACT39_GPIO_OFFSET 13 +#define RTL8367C_ACT39_GPIO_MASK 0x2000 +#define RTL8367C_ACT39_FORWARD_OFFSET 12 +#define RTL8367C_ACT39_FORWARD_MASK 0x1000 +#define RTL8367C_ACT39_POLICING_OFFSET 11 +#define RTL8367C_ACT39_POLICING_MASK 0x800 +#define RTL8367C_ACT39_PRIORITY_OFFSET 10 +#define RTL8367C_ACT39_PRIORITY_MASK 0x400 +#define RTL8367C_ACT39_SVID_OFFSET 9 +#define RTL8367C_ACT39_SVID_MASK 0x200 +#define RTL8367C_ACT39_CVID_OFFSET 8 +#define RTL8367C_ACT39_CVID_MASK 0x100 +#define RTL8367C_OP38_NOT_OFFSET 6 +#define RTL8367C_OP38_NOT_MASK 0x40 +#define RTL8367C_ACT38_GPIO_OFFSET 5 +#define RTL8367C_ACT38_GPIO_MASK 0x20 +#define RTL8367C_ACT38_FORWARD_OFFSET 4 +#define RTL8367C_ACT38_FORWARD_MASK 0x10 +#define RTL8367C_ACT38_POLICING_OFFSET 3 +#define RTL8367C_ACT38_POLICING_MASK 0x8 +#define RTL8367C_ACT38_PRIORITY_OFFSET 2 +#define RTL8367C_ACT38_PRIORITY_MASK 0x4 +#define RTL8367C_ACT38_SVID_OFFSET 1 +#define RTL8367C_ACT38_SVID_MASK 0x2 +#define RTL8367C_ACT38_CVID_OFFSET 0 +#define RTL8367C_ACT38_CVID_MASK 0x1 + +#define RTL8367C_REG_ACL_ACTION_CTRL20 0x0628 +#define RTL8367C_OP41_NOT_OFFSET 14 +#define RTL8367C_OP41_NOT_MASK 0x4000 +#define RTL8367C_ACT41_GPIO_OFFSET 13 +#define RTL8367C_ACT41_GPIO_MASK 0x2000 +#define RTL8367C_ACT41_FORWARD_OFFSET 12 +#define RTL8367C_ACT41_FORWARD_MASK 0x1000 +#define RTL8367C_ACT41_POLICING_OFFSET 11 +#define RTL8367C_ACT41_POLICING_MASK 0x800 +#define RTL8367C_ACT41_PRIORITY_OFFSET 10 +#define RTL8367C_ACT41_PRIORITY_MASK 0x400 +#define RTL8367C_ACT41_SVID_OFFSET 9 +#define RTL8367C_ACT41_SVID_MASK 0x200 +#define RTL8367C_ACT41_CVID_OFFSET 8 +#define RTL8367C_ACT41_CVID_MASK 0x100 +#define RTL8367C_OP40_NOT_OFFSET 6 +#define RTL8367C_OP40_NOT_MASK 0x40 +#define RTL8367C_ACT40_GPIO_OFFSET 5 +#define RTL8367C_ACT40_GPIO_MASK 0x20 +#define RTL8367C_ACT40_FORWARD_OFFSET 4 +#define RTL8367C_ACT40_FORWARD_MASK 0x10 +#define RTL8367C_ACT40_POLICING_OFFSET 3 +#define RTL8367C_ACT40_POLICING_MASK 0x8 +#define RTL8367C_ACT40_PRIORITY_OFFSET 2 +#define RTL8367C_ACT40_PRIORITY_MASK 0x4 +#define RTL8367C_ACT40_SVID_OFFSET 1 +#define RTL8367C_ACT40_SVID_MASK 0x2 +#define RTL8367C_ACT40_CVID_OFFSET 0 +#define RTL8367C_ACT40_CVID_MASK 0x1 + +#define RTL8367C_REG_ACL_ACTION_CTRL21 0x0629 +#define RTL8367C_OP43_NOT_OFFSET 14 +#define RTL8367C_OP43_NOT_MASK 0x4000 +#define RTL8367C_ACT43_GPIO_OFFSET 13 +#define RTL8367C_ACT43_GPIO_MASK 0x2000 +#define RTL8367C_ACT43_FORWARD_OFFSET 12 +#define RTL8367C_ACT43_FORWARD_MASK 0x1000 +#define RTL8367C_ACT43_POLICING_OFFSET 11 +#define RTL8367C_ACT43_POLICING_MASK 0x800 +#define RTL8367C_ACT43_PRIORITY_OFFSET 10 +#define RTL8367C_ACT43_PRIORITY_MASK 0x400 +#define RTL8367C_ACT43_SVID_OFFSET 9 +#define RTL8367C_ACT43_SVID_MASK 0x200 +#define RTL8367C_ACT43_CVID_OFFSET 8 +#define RTL8367C_ACT43_CVID_MASK 0x100 +#define RTL8367C_OP42_NOT_OFFSET 6 +#define RTL8367C_OP42_NOT_MASK 0x40 +#define RTL8367C_ACT42_GPIO_OFFSET 5 +#define RTL8367C_ACT42_GPIO_MASK 0x20 +#define RTL8367C_ACT42_FORWARD_OFFSET 4 +#define RTL8367C_ACT42_FORWARD_MASK 0x10 +#define RTL8367C_ACT42_POLICING_OFFSET 3 +#define RTL8367C_ACT42_POLICING_MASK 0x8 +#define RTL8367C_ACT42_PRIORITY_OFFSET 2 +#define RTL8367C_ACT42_PRIORITY_MASK 0x4 +#define RTL8367C_ACT42_SVID_OFFSET 1 +#define RTL8367C_ACT42_SVID_MASK 0x2 +#define RTL8367C_ACT42_CVID_OFFSET 0 +#define RTL8367C_ACT42_CVID_MASK 0x1 + +#define RTL8367C_REG_ACL_ACTION_CTRL22 0x062a +#define RTL8367C_OP45_NOT_OFFSET 14 +#define RTL8367C_OP45_NOT_MASK 0x4000 +#define RTL8367C_ACT45_GPIO_OFFSET 13 +#define RTL8367C_ACT45_GPIO_MASK 0x2000 +#define RTL8367C_ACT45_FORWARD_OFFSET 12 +#define RTL8367C_ACT45_FORWARD_MASK 0x1000 +#define RTL8367C_ACT45_POLICING_OFFSET 11 +#define RTL8367C_ACT45_POLICING_MASK 0x800 +#define RTL8367C_ACT45_PRIORITY_OFFSET 10 +#define RTL8367C_ACT45_PRIORITY_MASK 0x400 +#define RTL8367C_ACT45_SVID_OFFSET 9 +#define RTL8367C_ACT45_SVID_MASK 0x200 +#define RTL8367C_ACT45_CVID_OFFSET 8 +#define RTL8367C_ACT45_CVID_MASK 0x100 +#define RTL8367C_OP44_NOT_OFFSET 6 +#define RTL8367C_OP44_NOT_MASK 0x40 +#define RTL8367C_ACT44_GPIO_OFFSET 5 +#define RTL8367C_ACT44_GPIO_MASK 0x20 +#define RTL8367C_ACT44_FORWARD_OFFSET 4 +#define RTL8367C_ACT44_FORWARD_MASK 0x10 +#define RTL8367C_ACT44_POLICING_OFFSET 3 +#define RTL8367C_ACT44_POLICING_MASK 0x8 +#define RTL8367C_ACT44_PRIORITY_OFFSET 2 +#define RTL8367C_ACT44_PRIORITY_MASK 0x4 +#define RTL8367C_ACT44_SVID_OFFSET 1 +#define RTL8367C_ACT44_SVID_MASK 0x2 +#define RTL8367C_ACT44_CVID_OFFSET 0 +#define RTL8367C_ACT44_CVID_MASK 0x1 + +#define RTL8367C_REG_ACL_ACTION_CTRL23 0x062b +#define RTL8367C_OP47_NOT_OFFSET 14 +#define RTL8367C_OP47_NOT_MASK 0x4000 +#define RTL8367C_ACT47_GPIO_OFFSET 13 +#define RTL8367C_ACT47_GPIO_MASK 0x2000 +#define RTL8367C_ACT47_FORWARD_OFFSET 12 +#define RTL8367C_ACT47_FORWARD_MASK 0x1000 +#define RTL8367C_ACT47_POLICING_OFFSET 11 +#define RTL8367C_ACT47_POLICING_MASK 0x800 +#define RTL8367C_ACT47_PRIORITY_OFFSET 10 +#define RTL8367C_ACT47_PRIORITY_MASK 0x400 +#define RTL8367C_ACT47_SVID_OFFSET 9 +#define RTL8367C_ACT47_SVID_MASK 0x200 +#define RTL8367C_ACT47_CVID_OFFSET 8 +#define RTL8367C_ACT47_CVID_MASK 0x100 +#define RTL8367C_OP46_NOT_OFFSET 6 +#define RTL8367C_OP46_NOT_MASK 0x40 +#define RTL8367C_ACT46_GPIO_OFFSET 5 +#define RTL8367C_ACT46_GPIO_MASK 0x20 +#define RTL8367C_ACT46_FORWARD_OFFSET 4 +#define RTL8367C_ACT46_FORWARD_MASK 0x10 +#define RTL8367C_ACT46_POLICING_OFFSET 3 +#define RTL8367C_ACT46_POLICING_MASK 0x8 +#define RTL8367C_ACT46_PRIORITY_OFFSET 2 +#define RTL8367C_ACT46_PRIORITY_MASK 0x4 +#define RTL8367C_ACT46_SVID_OFFSET 1 +#define RTL8367C_ACT46_SVID_MASK 0x2 +#define RTL8367C_ACT46_CVID_OFFSET 0 +#define RTL8367C_ACT46_CVID_MASK 0x1 + +#define RTL8367C_REG_ACL_ACTION_CTRL24 0x062c +#define RTL8367C_OP49_NOT_OFFSET 14 +#define RTL8367C_OP49_NOT_MASK 0x4000 +#define RTL8367C_ACT49_GPIO_OFFSET 13 +#define RTL8367C_ACT49_GPIO_MASK 0x2000 +#define RTL8367C_ACT49_FORWARD_OFFSET 12 +#define RTL8367C_ACT49_FORWARD_MASK 0x1000 +#define RTL8367C_ACT49_POLICING_OFFSET 11 +#define RTL8367C_ACT49_POLICING_MASK 0x800 +#define RTL8367C_ACT49_PRIORITY_OFFSET 10 +#define RTL8367C_ACT49_PRIORITY_MASK 0x400 +#define RTL8367C_ACT49_SVID_OFFSET 9 +#define RTL8367C_ACT49_SVID_MASK 0x200 +#define RTL8367C_ACT49_CVID_OFFSET 8 +#define RTL8367C_ACT49_CVID_MASK 0x100 +#define RTL8367C_OP48_NOT_OFFSET 6 +#define RTL8367C_OP48_NOT_MASK 0x40 +#define RTL8367C_ACT48_GPIO_OFFSET 5 +#define RTL8367C_ACT48_GPIO_MASK 0x20 +#define RTL8367C_ACT48_FORWARD_OFFSET 4 +#define RTL8367C_ACT48_FORWARD_MASK 0x10 +#define RTL8367C_ACT48_POLICING_OFFSET 3 +#define RTL8367C_ACT48_POLICING_MASK 0x8 +#define RTL8367C_ACT48_PRIORITY_OFFSET 2 +#define RTL8367C_ACT48_PRIORITY_MASK 0x4 +#define RTL8367C_ACT48_SVID_OFFSET 1 +#define RTL8367C_ACT48_SVID_MASK 0x2 +#define RTL8367C_ACT48_CVID_OFFSET 0 +#define RTL8367C_ACT48_CVID_MASK 0x1 + +#define RTL8367C_REG_ACL_ACTION_CTRL25 0x062d +#define RTL8367C_OP51_NOT_OFFSET 14 +#define RTL8367C_OP51_NOT_MASK 0x4000 +#define RTL8367C_ACT51_GPIO_OFFSET 13 +#define RTL8367C_ACT51_GPIO_MASK 0x2000 +#define RTL8367C_ACT51_FORWARD_OFFSET 12 +#define RTL8367C_ACT51_FORWARD_MASK 0x1000 +#define RTL8367C_ACT51_POLICING_OFFSET 11 +#define RTL8367C_ACT51_POLICING_MASK 0x800 +#define RTL8367C_ACT51_PRIORITY_OFFSET 10 +#define RTL8367C_ACT51_PRIORITY_MASK 0x400 +#define RTL8367C_ACT51_SVID_OFFSET 9 +#define RTL8367C_ACT51_SVID_MASK 0x200 +#define RTL8367C_ACT51_CVID_OFFSET 8 +#define RTL8367C_ACT51_CVID_MASK 0x100 +#define RTL8367C_OP50_NOT_OFFSET 6 +#define RTL8367C_OP50_NOT_MASK 0x40 +#define RTL8367C_ACT50_GPIO_OFFSET 5 +#define RTL8367C_ACT50_GPIO_MASK 0x20 +#define RTL8367C_ACT50_FORWARD_OFFSET 4 +#define RTL8367C_ACT50_FORWARD_MASK 0x10 +#define RTL8367C_ACT50_POLICING_OFFSET 3 +#define RTL8367C_ACT50_POLICING_MASK 0x8 +#define RTL8367C_ACT50_PRIORITY_OFFSET 2 +#define RTL8367C_ACT50_PRIORITY_MASK 0x4 +#define RTL8367C_ACT50_SVID_OFFSET 1 +#define RTL8367C_ACT50_SVID_MASK 0x2 +#define RTL8367C_ACT50_CVID_OFFSET 0 +#define RTL8367C_ACT50_CVID_MASK 0x1 + +#define RTL8367C_REG_ACL_ACTION_CTRL26 0x062e +#define RTL8367C_OP53_NOT_OFFSET 14 +#define RTL8367C_OP53_NOT_MASK 0x4000 +#define RTL8367C_ACT53_GPIO_OFFSET 13 +#define RTL8367C_ACT53_GPIO_MASK 0x2000 +#define RTL8367C_ACT53_FORWARD_OFFSET 12 +#define RTL8367C_ACT53_FORWARD_MASK 0x1000 +#define RTL8367C_ACT53_POLICING_OFFSET 11 +#define RTL8367C_ACT53_POLICING_MASK 0x800 +#define RTL8367C_ACT53_PRIORITY_OFFSET 10 +#define RTL8367C_ACT53_PRIORITY_MASK 0x400 +#define RTL8367C_ACT53_SVID_OFFSET 9 +#define RTL8367C_ACT53_SVID_MASK 0x200 +#define RTL8367C_ACT53_CVID_OFFSET 8 +#define RTL8367C_ACT53_CVID_MASK 0x100 +#define RTL8367C_OP52_NOT_OFFSET 6 +#define RTL8367C_OP52_NOT_MASK 0x40 +#define RTL8367C_ACT52_GPIO_OFFSET 5 +#define RTL8367C_ACT52_GPIO_MASK 0x20 +#define RTL8367C_ACT52_FORWARD_OFFSET 4 +#define RTL8367C_ACT52_FORWARD_MASK 0x10 +#define RTL8367C_ACT52_POLICING_OFFSET 3 +#define RTL8367C_ACT52_POLICING_MASK 0x8 +#define RTL8367C_ACT52_PRIORITY_OFFSET 2 +#define RTL8367C_ACT52_PRIORITY_MASK 0x4 +#define RTL8367C_ACT52_SVID_OFFSET 1 +#define RTL8367C_ACT52_SVID_MASK 0x2 +#define RTL8367C_ACT52_CVID_OFFSET 0 +#define RTL8367C_ACT52_CVID_MASK 0x1 + +#define RTL8367C_REG_ACL_ACTION_CTRL27 0x062f +#define RTL8367C_OP55_NOT_OFFSET 14 +#define RTL8367C_OP55_NOT_MASK 0x4000 +#define RTL8367C_ACT55_GPIO_OFFSET 13 +#define RTL8367C_ACT55_GPIO_MASK 0x2000 +#define RTL8367C_ACT55_FORWARD_OFFSET 12 +#define RTL8367C_ACT55_FORWARD_MASK 0x1000 +#define RTL8367C_ACT55_POLICING_OFFSET 11 +#define RTL8367C_ACT55_POLICING_MASK 0x800 +#define RTL8367C_ACT55_PRIORITY_OFFSET 10 +#define RTL8367C_ACT55_PRIORITY_MASK 0x400 +#define RTL8367C_ACT55_SVID_OFFSET 9 +#define RTL8367C_ACT55_SVID_MASK 0x200 +#define RTL8367C_ACT55_CVID_OFFSET 8 +#define RTL8367C_ACT55_CVID_MASK 0x100 +#define RTL8367C_OP54_NOT_OFFSET 6 +#define RTL8367C_OP54_NOT_MASK 0x40 +#define RTL8367C_ACT54_GPIO_OFFSET 5 +#define RTL8367C_ACT54_GPIO_MASK 0x20 +#define RTL8367C_ACT54_FORWARD_OFFSET 4 +#define RTL8367C_ACT54_FORWARD_MASK 0x10 +#define RTL8367C_ACT54_POLICING_OFFSET 3 +#define RTL8367C_ACT54_POLICING_MASK 0x8 +#define RTL8367C_ACT54_PRIORITY_OFFSET 2 +#define RTL8367C_ACT54_PRIORITY_MASK 0x4 +#define RTL8367C_ACT54_SVID_OFFSET 1 +#define RTL8367C_ACT54_SVID_MASK 0x2 +#define RTL8367C_ACT54_CVID_OFFSET 0 +#define RTL8367C_ACT54_CVID_MASK 0x1 + +#define RTL8367C_REG_ACL_ACTION_CTRL28 0x0630 +#define RTL8367C_OP57_NOT_OFFSET 14 +#define RTL8367C_OP57_NOT_MASK 0x4000 +#define RTL8367C_ACT57_GPIO_OFFSET 13 +#define RTL8367C_ACT57_GPIO_MASK 0x2000 +#define RTL8367C_ACT57_FORWARD_OFFSET 12 +#define RTL8367C_ACT57_FORWARD_MASK 0x1000 +#define RTL8367C_ACT57_POLICING_OFFSET 11 +#define RTL8367C_ACT57_POLICING_MASK 0x800 +#define RTL8367C_ACT57_PRIORITY_OFFSET 10 +#define RTL8367C_ACT57_PRIORITY_MASK 0x400 +#define RTL8367C_ACT57_SVID_OFFSET 9 +#define RTL8367C_ACT57_SVID_MASK 0x200 +#define RTL8367C_ACT57_CVID_OFFSET 8 +#define RTL8367C_ACT57_CVID_MASK 0x100 +#define RTL8367C_OP56_NOT_OFFSET 6 +#define RTL8367C_OP56_NOT_MASK 0x40 +#define RTL8367C_ACT56_GPIO_OFFSET 5 +#define RTL8367C_ACT56_GPIO_MASK 0x20 +#define RTL8367C_ACT56_FORWARD_OFFSET 4 +#define RTL8367C_ACT56_FORWARD_MASK 0x10 +#define RTL8367C_ACT56_POLICING_OFFSET 3 +#define RTL8367C_ACT56_POLICING_MASK 0x8 +#define RTL8367C_ACT56_PRIORITY_OFFSET 2 +#define RTL8367C_ACT56_PRIORITY_MASK 0x4 +#define RTL8367C_ACT56_SVID_OFFSET 1 +#define RTL8367C_ACT56_SVID_MASK 0x2 +#define RTL8367C_ACT56_CVID_OFFSET 0 +#define RTL8367C_ACT56_CVID_MASK 0x1 + +#define RTL8367C_REG_ACL_ACTION_CTRL29 0x0631 +#define RTL8367C_OP59_NOT_OFFSET 14 +#define RTL8367C_OP59_NOT_MASK 0x4000 +#define RTL8367C_ACT59_GPIO_OFFSET 13 +#define RTL8367C_ACT59_GPIO_MASK 0x2000 +#define RTL8367C_ACT59_FORWARD_OFFSET 12 +#define RTL8367C_ACT59_FORWARD_MASK 0x1000 +#define RTL8367C_ACT59_POLICING_OFFSET 11 +#define RTL8367C_ACT59_POLICING_MASK 0x800 +#define RTL8367C_ACT59_PRIORITY_OFFSET 10 +#define RTL8367C_ACT59_PRIORITY_MASK 0x400 +#define RTL8367C_ACT59_SVID_OFFSET 9 +#define RTL8367C_ACT59_SVID_MASK 0x200 +#define RTL8367C_ACT59_CVID_OFFSET 8 +#define RTL8367C_ACT59_CVID_MASK 0x100 +#define RTL8367C_OP58_NOT_OFFSET 6 +#define RTL8367C_OP58_NOT_MASK 0x40 +#define RTL8367C_ACT58_GPIO_OFFSET 5 +#define RTL8367C_ACT58_GPIO_MASK 0x20 +#define RTL8367C_ACT58_FORWARD_OFFSET 4 +#define RTL8367C_ACT58_FORWARD_MASK 0x10 +#define RTL8367C_ACT58_POLICING_OFFSET 3 +#define RTL8367C_ACT58_POLICING_MASK 0x8 +#define RTL8367C_ACT58_PRIORITY_OFFSET 2 +#define RTL8367C_ACT58_PRIORITY_MASK 0x4 +#define RTL8367C_ACT58_SVID_OFFSET 1 +#define RTL8367C_ACT58_SVID_MASK 0x2 +#define RTL8367C_ACT58_CVID_OFFSET 0 +#define RTL8367C_ACT58_CVID_MASK 0x1 + +#define RTL8367C_REG_ACL_ACTION_CTRL30 0x0632 +#define RTL8367C_OP61_NOT_OFFSET 14 +#define RTL8367C_OP61_NOT_MASK 0x4000 +#define RTL8367C_ACT61_GPIO_OFFSET 13 +#define RTL8367C_ACT61_GPIO_MASK 0x2000 +#define RTL8367C_ACT61_FORWARD_OFFSET 12 +#define RTL8367C_ACT61_FORWARD_MASK 0x1000 +#define RTL8367C_ACT61_POLICING_OFFSET 11 +#define RTL8367C_ACT61_POLICING_MASK 0x800 +#define RTL8367C_ACT61_PRIORITY_OFFSET 10 +#define RTL8367C_ACT61_PRIORITY_MASK 0x400 +#define RTL8367C_ACT61_SVID_OFFSET 9 +#define RTL8367C_ACT61_SVID_MASK 0x200 +#define RTL8367C_ACT61_CVID_OFFSET 8 +#define RTL8367C_ACT61_CVID_MASK 0x100 +#define RTL8367C_OP60_NOT_OFFSET 6 +#define RTL8367C_OP60_NOT_MASK 0x40 +#define RTL8367C_ACT60_GPIO_OFFSET 5 +#define RTL8367C_ACT60_GPIO_MASK 0x20 +#define RTL8367C_ACT60_FORWARD_OFFSET 4 +#define RTL8367C_ACT60_FORWARD_MASK 0x10 +#define RTL8367C_ACT60_POLICING_OFFSET 3 +#define RTL8367C_ACT60_POLICING_MASK 0x8 +#define RTL8367C_ACT60_PRIORITY_OFFSET 2 +#define RTL8367C_ACT60_PRIORITY_MASK 0x4 +#define RTL8367C_ACT60_SVID_OFFSET 1 +#define RTL8367C_ACT60_SVID_MASK 0x2 +#define RTL8367C_ACT60_CVID_OFFSET 0 +#define RTL8367C_ACT60_CVID_MASK 0x1 + +#define RTL8367C_REG_ACL_ACTION_CTRL31 0x0633 +#define RTL8367C_OP63_NOT_OFFSET 14 +#define RTL8367C_OP63_NOT_MASK 0x4000 +#define RTL8367C_ACT63_GPIO_OFFSET 13 +#define RTL8367C_ACT63_GPIO_MASK 0x2000 +#define RTL8367C_ACT63_FORWARD_OFFSET 12 +#define RTL8367C_ACT63_FORWARD_MASK 0x1000 +#define RTL8367C_ACT63_POLICING_OFFSET 11 +#define RTL8367C_ACT63_POLICING_MASK 0x800 +#define RTL8367C_ACT63_PRIORITY_OFFSET 10 +#define RTL8367C_ACT63_PRIORITY_MASK 0x400 +#define RTL8367C_ACT63_SVID_OFFSET 9 +#define RTL8367C_ACT63_SVID_MASK 0x200 +#define RTL8367C_ACT63_CVID_OFFSET 8 +#define RTL8367C_ACT63_CVID_MASK 0x100 +#define RTL8367C_OP62_NOT_OFFSET 6 +#define RTL8367C_OP62_NOT_MASK 0x40 +#define RTL8367C_ACT62_GPIO_OFFSET 5 +#define RTL8367C_ACT62_GPIO_MASK 0x20 +#define RTL8367C_ACT62_FORWARD_OFFSET 4 +#define RTL8367C_ACT62_FORWARD_MASK 0x10 +#define RTL8367C_ACT62_POLICING_OFFSET 3 +#define RTL8367C_ACT62_POLICING_MASK 0x8 +#define RTL8367C_ACT62_PRIORITY_OFFSET 2 +#define RTL8367C_ACT62_PRIORITY_MASK 0x4 +#define RTL8367C_ACT62_SVID_OFFSET 1 +#define RTL8367C_ACT62_SVID_MASK 0x2 +#define RTL8367C_ACT62_CVID_OFFSET 0 +#define RTL8367C_ACT62_CVID_MASK 0x1 + +#define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY0_CTRL0 0x0635 + +#define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY0_CTRL1 0x0636 + +#define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY0_CTRL2 0x0637 +#define RTL8367C_ACL_SDPORT_RANGE_ENTRY0_CTRL2_OFFSET 0 +#define RTL8367C_ACL_SDPORT_RANGE_ENTRY0_CTRL2_MASK 0x3 + +#define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY1_CTRL0 0x0638 + +#define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY1_CTRL1 0x0639 + +#define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY1_CTRL2 0x063a +#define RTL8367C_ACL_SDPORT_RANGE_ENTRY1_CTRL2_OFFSET 0 +#define RTL8367C_ACL_SDPORT_RANGE_ENTRY1_CTRL2_MASK 0x3 + +#define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY2_CTRL0 0x063b + +#define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY2_CTRL1 0x063c + +#define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY2_CTRL2 0x063d +#define RTL8367C_ACL_SDPORT_RANGE_ENTRY2_CTRL2_OFFSET 0 +#define RTL8367C_ACL_SDPORT_RANGE_ENTRY2_CTRL2_MASK 0x3 + +#define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY3_CTRL0 0x063e + +#define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY3_CTRL1 0x063f + +#define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY3_CTRL2 0x0640 +#define RTL8367C_ACL_SDPORT_RANGE_ENTRY3_CTRL2_OFFSET 0 +#define RTL8367C_ACL_SDPORT_RANGE_ENTRY3_CTRL2_MASK 0x3 + +#define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY4_CTRL0 0x0641 + +#define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY4_CTRL1 0x0642 + +#define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY4_CTRL2 0x0643 +#define RTL8367C_ACL_SDPORT_RANGE_ENTRY4_CTRL2_OFFSET 0 +#define RTL8367C_ACL_SDPORT_RANGE_ENTRY4_CTRL2_MASK 0x3 + +#define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY5_CTRL0 0x0644 + +#define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY5_CTRL1 0x0645 + +#define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY5_CTRL2 0x0646 +#define RTL8367C_ACL_SDPORT_RANGE_ENTRY5_CTRL2_OFFSET 0 +#define RTL8367C_ACL_SDPORT_RANGE_ENTRY5_CTRL2_MASK 0x3 + +#define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY6_CTRL0 0x0647 + +#define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY6_CTRL1 0x0648 + +#define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY6_CTRL2 0x0649 +#define RTL8367C_ACL_SDPORT_RANGE_ENTRY6_CTRL2_OFFSET 0 +#define RTL8367C_ACL_SDPORT_RANGE_ENTRY6_CTRL2_MASK 0x3 + +#define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY7_CTRL0 0x064a + +#define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY7_CTRL1 0x064b + +#define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY7_CTRL2 0x064c +#define RTL8367C_ACL_SDPORT_RANGE_ENTRY7_CTRL2_OFFSET 0 +#define RTL8367C_ACL_SDPORT_RANGE_ENTRY7_CTRL2_MASK 0x3 + +#define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY8_CTRL0 0x064d + +#define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY8_CTRL1 0x064e + +#define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY8_CTRL2 0x064f +#define RTL8367C_ACL_SDPORT_RANGE_ENTRY8_CTRL2_OFFSET 0 +#define RTL8367C_ACL_SDPORT_RANGE_ENTRY8_CTRL2_MASK 0x3 + +#define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY9_CTRL0 0x0650 + +#define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY9_CTRL1 0x0651 + +#define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY9_CTRL2 0x0652 +#define RTL8367C_ACL_SDPORT_RANGE_ENTRY9_CTRL2_OFFSET 0 +#define RTL8367C_ACL_SDPORT_RANGE_ENTRY9_CTRL2_MASK 0x3 + +#define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY10_CTRL0 0x0653 + +#define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY10_CTRL1 0x0654 + +#define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY10_CTRL2 0x0655 +#define RTL8367C_ACL_SDPORT_RANGE_ENTRY10_CTRL2_OFFSET 0 +#define RTL8367C_ACL_SDPORT_RANGE_ENTRY10_CTRL2_MASK 0x3 + +#define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY11_CTRL0 0x0656 + +#define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY11_CTRL1 0x0657 + +#define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY11_CTRL2 0x0658 +#define RTL8367C_ACL_SDPORT_RANGE_ENTRY11_CTRL2_OFFSET 0 +#define RTL8367C_ACL_SDPORT_RANGE_ENTRY11_CTRL2_MASK 0x3 + +#define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY12_CTRL0 0x0659 + +#define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY12_CTRL1 0x065a + +#define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY12_CTRL2 0x065b +#define RTL8367C_ACL_SDPORT_RANGE_ENTRY12_CTRL2_OFFSET 0 +#define RTL8367C_ACL_SDPORT_RANGE_ENTRY12_CTRL2_MASK 0x3 + +#define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY13_CTRL0 0x065c + +#define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY13_CTRL1 0x065d + +#define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY13_CTRL2 0x065e +#define RTL8367C_ACL_SDPORT_RANGE_ENTRY13_CTRL2_OFFSET 0 +#define RTL8367C_ACL_SDPORT_RANGE_ENTRY13_CTRL2_MASK 0x3 + +#define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY14_CTRL0 0x065f + +#define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY14_CTRL1 0x0660 + +#define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY14_CTRL2 0x0661 +#define RTL8367C_ACL_SDPORT_RANGE_ENTRY14_CTRL2_OFFSET 0 +#define RTL8367C_ACL_SDPORT_RANGE_ENTRY14_CTRL2_MASK 0x3 + +#define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY15_CTRL0 0x0662 + +#define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY15_CTRL1 0x0663 + +#define RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY15_CTRL2 0x0664 +#define RTL8367C_ACL_SDPORT_RANGE_ENTRY15_CTRL2_OFFSET 0 +#define RTL8367C_ACL_SDPORT_RANGE_ENTRY15_CTRL2_MASK 0x3 + +#define RTL8367C_REG_ACL_VID_RANGE_ENTRY0_CTRL0 0x0665 +#define RTL8367C_ACL_VID_RANGE_ENTRY0_CTRL0_OFFSET 0 +#define RTL8367C_ACL_VID_RANGE_ENTRY0_CTRL0_MASK 0xFFF + +#define RTL8367C_REG_ACL_VID_RANGE_ENTRY0_CTRL1 0x0666 +#define RTL8367C_ACL_VID_RANGE_ENTRY0_CTRL1_CHECK0_TYPE_OFFSET 12 +#define RTL8367C_ACL_VID_RANGE_ENTRY0_CTRL1_CHECK0_TYPE_MASK 0x3000 +#define RTL8367C_ACL_VID_RANGE_ENTRY0_CTRL1_CHECK0_HIGH_OFFSET 0 +#define RTL8367C_ACL_VID_RANGE_ENTRY0_CTRL1_CHECK0_HIGH_MASK 0xFFF + +#define RTL8367C_REG_ACL_VID_RANGE_ENTRY1_CTRL0 0x0667 +#define RTL8367C_ACL_VID_RANGE_ENTRY1_CTRL0_OFFSET 0 +#define RTL8367C_ACL_VID_RANGE_ENTRY1_CTRL0_MASK 0xFFF + +#define RTL8367C_REG_ACL_VID_RANGE_ENTRY1_CTRL1 0x0668 +#define RTL8367C_ACL_VID_RANGE_ENTRY1_CTRL1_CHECK1_TYPE_OFFSET 12 +#define RTL8367C_ACL_VID_RANGE_ENTRY1_CTRL1_CHECK1_TYPE_MASK 0x3000 +#define RTL8367C_ACL_VID_RANGE_ENTRY1_CTRL1_CHECK1_HIGH_OFFSET 0 +#define RTL8367C_ACL_VID_RANGE_ENTRY1_CTRL1_CHECK1_HIGH_MASK 0xFFF + +#define RTL8367C_REG_ACL_VID_RANGE_ENTRY2_CTRL0 0x0669 +#define RTL8367C_ACL_VID_RANGE_ENTRY2_CTRL0_OFFSET 0 +#define RTL8367C_ACL_VID_RANGE_ENTRY2_CTRL0_MASK 0xFFF + +#define RTL8367C_REG_ACL_VID_RANGE_ENTRY2_CTRL1 0x066a +#define RTL8367C_ACL_VID_RANGE_ENTRY2_CTRL1_CHECK2_TYPE_OFFSET 12 +#define RTL8367C_ACL_VID_RANGE_ENTRY2_CTRL1_CHECK2_TYPE_MASK 0x3000 +#define RTL8367C_ACL_VID_RANGE_ENTRY2_CTRL1_CHECK2_HIGH_OFFSET 0 +#define RTL8367C_ACL_VID_RANGE_ENTRY2_CTRL1_CHECK2_HIGH_MASK 0xFFF + +#define RTL8367C_REG_ACL_VID_RANGE_ENTRY3_CTRL0 0x066b +#define RTL8367C_ACL_VID_RANGE_ENTRY3_CTRL0_OFFSET 0 +#define RTL8367C_ACL_VID_RANGE_ENTRY3_CTRL0_MASK 0xFFF + +#define RTL8367C_REG_ACL_VID_RANGE_ENTRY3_CTRL1 0x066c +#define RTL8367C_ACL_VID_RANGE_ENTRY3_CTRL1_CHECK3_TYPE_OFFSET 12 +#define RTL8367C_ACL_VID_RANGE_ENTRY3_CTRL1_CHECK3_TYPE_MASK 0x3000 +#define RTL8367C_ACL_VID_RANGE_ENTRY3_CTRL1_CHECK3_HIGH_OFFSET 0 +#define RTL8367C_ACL_VID_RANGE_ENTRY3_CTRL1_CHECK3_HIGH_MASK 0xFFF + +#define RTL8367C_REG_ACL_VID_RANGE_ENTRY4_CTRL0 0x066d +#define RTL8367C_ACL_VID_RANGE_ENTRY4_CTRL0_OFFSET 0 +#define RTL8367C_ACL_VID_RANGE_ENTRY4_CTRL0_MASK 0xFFF + +#define RTL8367C_REG_ACL_VID_RANGE_ENTRY4_CTRL1 0x066e +#define RTL8367C_ACL_VID_RANGE_ENTRY4_CTRL1_CHECK4_TYPE_OFFSET 12 +#define RTL8367C_ACL_VID_RANGE_ENTRY4_CTRL1_CHECK4_TYPE_MASK 0x3000 +#define RTL8367C_ACL_VID_RANGE_ENTRY4_CTRL1_CHECK4_HIGH_OFFSET 0 +#define RTL8367C_ACL_VID_RANGE_ENTRY4_CTRL1_CHECK4_HIGH_MASK 0xFFF + +#define RTL8367C_REG_ACL_VID_RANGE_ENTRY5_CTRL0 0x066f +#define RTL8367C_ACL_VID_RANGE_ENTRY5_CTRL0_OFFSET 0 +#define RTL8367C_ACL_VID_RANGE_ENTRY5_CTRL0_MASK 0xFFF + +#define RTL8367C_REG_ACL_VID_RANGE_ENTRY5_CTRL1 0x0670 +#define RTL8367C_ACL_VID_RANGE_ENTRY5_CTRL1_CHECK5_TYPE_OFFSET 12 +#define RTL8367C_ACL_VID_RANGE_ENTRY5_CTRL1_CHECK5_TYPE_MASK 0x3000 +#define RTL8367C_ACL_VID_RANGE_ENTRY5_CTRL1_CHECK5_HIGH_OFFSET 0 +#define RTL8367C_ACL_VID_RANGE_ENTRY5_CTRL1_CHECK5_HIGH_MASK 0xFFF + +#define RTL8367C_REG_ACL_VID_RANGE_ENTRY6_CTRL0 0x0671 +#define RTL8367C_ACL_VID_RANGE_ENTRY6_CTRL0_OFFSET 0 +#define RTL8367C_ACL_VID_RANGE_ENTRY6_CTRL0_MASK 0xFFF + +#define RTL8367C_REG_ACL_VID_RANGE_ENTRY6_CTRL1 0x0672 +#define RTL8367C_ACL_VID_RANGE_ENTRY6_CTRL1_CHECK6_TYPE_OFFSET 12 +#define RTL8367C_ACL_VID_RANGE_ENTRY6_CTRL1_CHECK6_TYPE_MASK 0x3000 +#define RTL8367C_ACL_VID_RANGE_ENTRY6_CTRL1_CHECK6_HIGH_OFFSET 0 +#define RTL8367C_ACL_VID_RANGE_ENTRY6_CTRL1_CHECK6_HIGH_MASK 0xFFF + +#define RTL8367C_REG_ACL_VID_RANGE_ENTRY7_CTRL0 0x0673 +#define RTL8367C_ACL_VID_RANGE_ENTRY7_CTRL0_OFFSET 0 +#define RTL8367C_ACL_VID_RANGE_ENTRY7_CTRL0_MASK 0xFFF + +#define RTL8367C_REG_ACL_VID_RANGE_ENTRY7_CTRL1 0x0674 +#define RTL8367C_ACL_VID_RANGE_ENTRY7_CTRL1_CHECK7_TYPE_OFFSET 12 +#define RTL8367C_ACL_VID_RANGE_ENTRY7_CTRL1_CHECK7_TYPE_MASK 0x3000 +#define RTL8367C_ACL_VID_RANGE_ENTRY7_CTRL1_CHECK7_HIGH_OFFSET 0 +#define RTL8367C_ACL_VID_RANGE_ENTRY7_CTRL1_CHECK7_HIGH_MASK 0xFFF + +#define RTL8367C_REG_ACL_VID_RANGE_ENTRY8_CTRL0 0x0675 +#define RTL8367C_ACL_VID_RANGE_ENTRY8_CTRL0_OFFSET 0 +#define RTL8367C_ACL_VID_RANGE_ENTRY8_CTRL0_MASK 0xFFF + +#define RTL8367C_REG_ACL_VID_RANGE_ENTRY8_CTRL1 0x0676 +#define RTL8367C_ACL_VID_RANGE_ENTRY8_CTRL1_CHECK8_TYPE_OFFSET 12 +#define RTL8367C_ACL_VID_RANGE_ENTRY8_CTRL1_CHECK8_TYPE_MASK 0x3000 +#define RTL8367C_ACL_VID_RANGE_ENTRY8_CTRL1_CHECK8_HIGH_OFFSET 0 +#define RTL8367C_ACL_VID_RANGE_ENTRY8_CTRL1_CHECK8_HIGH_MASK 0xFFF + +#define RTL8367C_REG_ACL_VID_RANGE_ENTRY9_CTRL0 0x0677 +#define RTL8367C_ACL_VID_RANGE_ENTRY9_CTRL0_OFFSET 0 +#define RTL8367C_ACL_VID_RANGE_ENTRY9_CTRL0_MASK 0xFFF + +#define RTL8367C_REG_ACL_VID_RANGE_ENTRY9_CTRL1 0x0678 +#define RTL8367C_ACL_VID_RANGE_ENTRY9_CTRL1_CHECK9_TYPE_OFFSET 12 +#define RTL8367C_ACL_VID_RANGE_ENTRY9_CTRL1_CHECK9_TYPE_MASK 0x3000 +#define RTL8367C_ACL_VID_RANGE_ENTRY9_CTRL1_CHECK9_HIGH_OFFSET 0 +#define RTL8367C_ACL_VID_RANGE_ENTRY9_CTRL1_CHECK9_HIGH_MASK 0xFFF + +#define RTL8367C_REG_ACL_VID_RANGE_ENTRY10_CTRL0 0x0679 +#define RTL8367C_ACL_VID_RANGE_ENTRY10_CTRL0_OFFSET 0 +#define RTL8367C_ACL_VID_RANGE_ENTRY10_CTRL0_MASK 0xFFF + +#define RTL8367C_REG_ACL_VID_RANGE_ENTRY10_CTRL1 0x067a +#define RTL8367C_ACL_VID_RANGE_ENTRY10_CTRL1_CHECK10_TYPE_OFFSET 12 +#define RTL8367C_ACL_VID_RANGE_ENTRY10_CTRL1_CHECK10_TYPE_MASK 0x3000 +#define RTL8367C_ACL_VID_RANGE_ENTRY10_CTRL1_CHECK10_HIGH_OFFSET 0 +#define RTL8367C_ACL_VID_RANGE_ENTRY10_CTRL1_CHECK10_HIGH_MASK 0xFFF + +#define RTL8367C_REG_ACL_VID_RANGE_ENTRY11_CTRL0 0x067b +#define RTL8367C_ACL_VID_RANGE_ENTRY11_CTRL0_OFFSET 0 +#define RTL8367C_ACL_VID_RANGE_ENTRY11_CTRL0_MASK 0xFFF + +#define RTL8367C_REG_ACL_VID_RANGE_ENTRY11_CTRL1 0x067c +#define RTL8367C_ACL_VID_RANGE_ENTRY11_CTRL1_CHECK11_TYPE_OFFSET 12 +#define RTL8367C_ACL_VID_RANGE_ENTRY11_CTRL1_CHECK11_TYPE_MASK 0x3000 +#define RTL8367C_ACL_VID_RANGE_ENTRY11_CTRL1_CHECK11_HIGH_OFFSET 0 +#define RTL8367C_ACL_VID_RANGE_ENTRY11_CTRL1_CHECK11_HIGH_MASK 0xFFF + +#define RTL8367C_REG_ACL_VID_RANGE_ENTRY12_CTRL0 0x067d +#define RTL8367C_ACL_VID_RANGE_ENTRY12_CTRL0_OFFSET 0 +#define RTL8367C_ACL_VID_RANGE_ENTRY12_CTRL0_MASK 0xFFF + +#define RTL8367C_REG_ACL_VID_RANGE_ENTRY12_CTRL1 0x067e +#define RTL8367C_ACL_VID_RANGE_ENTRY12_CTRL1_CHECK12_TYPE_OFFSET 12 +#define RTL8367C_ACL_VID_RANGE_ENTRY12_CTRL1_CHECK12_TYPE_MASK 0x3000 +#define RTL8367C_ACL_VID_RANGE_ENTRY12_CTRL1_CHECK12_HIGH_OFFSET 0 +#define RTL8367C_ACL_VID_RANGE_ENTRY12_CTRL1_CHECK12_HIGH_MASK 0xFFF + +#define RTL8367C_REG_ACL_VID_RANGE_ENTRY13_CTRL0 0x067f +#define RTL8367C_ACL_VID_RANGE_ENTRY13_CTRL0_OFFSET 0 +#define RTL8367C_ACL_VID_RANGE_ENTRY13_CTRL0_MASK 0xFFF + +#define RTL8367C_REG_ACL_VID_RANGE_ENTRY13_CTRL1 0x0680 +#define RTL8367C_ACL_VID_RANGE_ENTRY13_CTRL1_CHECK13_TYPE_OFFSET 12 +#define RTL8367C_ACL_VID_RANGE_ENTRY13_CTRL1_CHECK13_TYPE_MASK 0x3000 +#define RTL8367C_ACL_VID_RANGE_ENTRY13_CTRL1_CHECK13_HIGH_OFFSET 0 +#define RTL8367C_ACL_VID_RANGE_ENTRY13_CTRL1_CHECK13_HIGH_MASK 0xFFF + +#define RTL8367C_REG_ACL_VID_RANGE_ENTRY14_CTRL0 0x0681 +#define RTL8367C_ACL_VID_RANGE_ENTRY14_CTRL0_OFFSET 0 +#define RTL8367C_ACL_VID_RANGE_ENTRY14_CTRL0_MASK 0xFFF + +#define RTL8367C_REG_ACL_VID_RANGE_ENTRY14_CTRL1 0x0682 +#define RTL8367C_ACL_VID_RANGE_ENTRY14_CTRL1_CHECK14_TYPE_OFFSET 12 +#define RTL8367C_ACL_VID_RANGE_ENTRY14_CTRL1_CHECK14_TYPE_MASK 0x3000 +#define RTL8367C_ACL_VID_RANGE_ENTRY14_CTRL1_CHECK14_HIGH_OFFSET 0 +#define RTL8367C_ACL_VID_RANGE_ENTRY14_CTRL1_CHECK14_HIGH_MASK 0xFFF + +#define RTL8367C_REG_ACL_VID_RANGE_ENTRY15_CTRL0 0x0683 +#define RTL8367C_ACL_VID_RANGE_ENTRY15_CTRL0_OFFSET 0 +#define RTL8367C_ACL_VID_RANGE_ENTRY15_CTRL0_MASK 0xFFF + +#define RTL8367C_REG_ACL_VID_RANGE_ENTRY15_CTRL1 0x0684 +#define RTL8367C_ACL_VID_RANGE_ENTRY15_CTRL1_CHECK15_TYPE_OFFSET 12 +#define RTL8367C_ACL_VID_RANGE_ENTRY15_CTRL1_CHECK15_TYPE_MASK 0x3000 +#define RTL8367C_ACL_VID_RANGE_ENTRY15_CTRL1_CHECK15_HIGH_OFFSET 0 +#define RTL8367C_ACL_VID_RANGE_ENTRY15_CTRL1_CHECK15_HIGH_MASK 0xFFF + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY0_CTRL0 0x0685 + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY0_CTRL1 0x0686 + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY0_CTRL2 0x0687 + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY0_CTRL3 0x0688 + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY0_CTRL4 0x0689 +#define RTL8367C_ACL_IP_RANGE_ENTRY0_CTRL4_OFFSET 0 +#define RTL8367C_ACL_IP_RANGE_ENTRY0_CTRL4_MASK 0x7 + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY1_CTRL0 0x068a + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY1_CTRL1 0x068b + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY1_CTRL2 0x068c + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY1_CTRL3 0x068d + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY1_CTRL4 0x068e +#define RTL8367C_ACL_IP_RANGE_ENTRY1_CTRL4_OFFSET 0 +#define RTL8367C_ACL_IP_RANGE_ENTRY1_CTRL4_MASK 0x7 + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY2_CTRL0 0x068f + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY2_CTRL1 0x0690 + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY2_CTRL2 0x0691 + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY2_CTRL3 0x0692 + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY2_CTRL4 0x0693 +#define RTL8367C_ACL_IP_RANGE_ENTRY2_CTRL4_OFFSET 0 +#define RTL8367C_ACL_IP_RANGE_ENTRY2_CTRL4_MASK 0x7 + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY3_CTRL0 0x0694 + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY3_CTRL1 0x0695 + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY3_CTRL2 0x0696 + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY3_CTRL3 0x0697 + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY3_CTRL4 0x0698 +#define RTL8367C_ACL_IP_RANGE_ENTRY3_CTRL4_OFFSET 0 +#define RTL8367C_ACL_IP_RANGE_ENTRY3_CTRL4_MASK 0x7 + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY4_CTRL0 0x0699 + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY4_CTRL1 0x069a + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY4_CTRL2 0x069b + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY4_CTRL3 0x069c + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY4_CTRL4 0x069d +#define RTL8367C_ACL_IP_RANGE_ENTRY4_CTRL4_OFFSET 0 +#define RTL8367C_ACL_IP_RANGE_ENTRY4_CTRL4_MASK 0x7 + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY5_CTRL0 0x069e + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY5_CTRL1 0x069f + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY5_CTRL2 0x06a0 + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY5_CTRL3 0x06a1 + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY5_CTRL4 0x06a2 +#define RTL8367C_ACL_IP_RANGE_ENTRY5_CTRL4_OFFSET 0 +#define RTL8367C_ACL_IP_RANGE_ENTRY5_CTRL4_MASK 0x7 + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY6_CTRL0 0x06a3 + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY6_CTRL1 0x06a4 + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY6_CTRL2 0x06a5 + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY6_CTRL3 0x06a6 + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY6_CTRL4 0x06a7 +#define RTL8367C_ACL_IP_RANGE_ENTRY6_CTRL4_OFFSET 0 +#define RTL8367C_ACL_IP_RANGE_ENTRY6_CTRL4_MASK 0x7 + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY7_CTRL0 0x06a8 + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY7_CTRL1 0x06a9 + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY7_CTRL2 0x06aa + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY7_CTRL3 0x06ab + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY7_CTRL4 0x06ac +#define RTL8367C_ACL_IP_RANGE_ENTRY7_CTRL4_OFFSET 0 +#define RTL8367C_ACL_IP_RANGE_ENTRY7_CTRL4_MASK 0x7 + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY8_CTRL0 0x06ad + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY8_CTRL1 0x06ae + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY8_CTRL2 0x06af + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY8_CTRL3 0x06b0 + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY8_CTRL4 0x06b1 +#define RTL8367C_ACL_IP_RANGE_ENTRY8_CTRL4_OFFSET 0 +#define RTL8367C_ACL_IP_RANGE_ENTRY8_CTRL4_MASK 0x7 + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY9_CTRL0 0x06b2 + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY9_CTRL1 0x06b3 + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY9_CTRL2 0x06b4 + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY9_CTRL3 0x06b5 + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY9_CTRL4 0x06b6 +#define RTL8367C_ACL_IP_RANGE_ENTRY9_CTRL4_OFFSET 0 +#define RTL8367C_ACL_IP_RANGE_ENTRY9_CTRL4_MASK 0x7 + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY10_CTRL0 0x06b7 + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY10_CTRL1 0x06b8 + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY10_CTRL2 0x06b9 + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY10_CTRL3 0x06ba + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY10_CTRL4 0x06bb +#define RTL8367C_ACL_IP_RANGE_ENTRY10_CTRL4_OFFSET 0 +#define RTL8367C_ACL_IP_RANGE_ENTRY10_CTRL4_MASK 0x7 + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY11_CTRL0 0x06bc + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY11_CTRL1 0x06bd + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY11_CTRL2 0x06be + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY11_CTRL3 0x06bf + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY11_CTRL4 0x06c0 +#define RTL8367C_ACL_IP_RANGE_ENTRY11_CTRL4_OFFSET 0 +#define RTL8367C_ACL_IP_RANGE_ENTRY11_CTRL4_MASK 0x7 + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY12_CTRL0 0x06c1 + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY12_CTRL1 0x06c2 + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY12_CTRL2 0x06c3 + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY12_CTRL3 0x06c4 + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY12_CTRL4 0x06c5 +#define RTL8367C_ACL_IP_RANGE_ENTRY12_CTRL4_OFFSET 0 +#define RTL8367C_ACL_IP_RANGE_ENTRY12_CTRL4_MASK 0x7 + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY13_CTRL0 0x06c6 + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY13_CTRL1 0x06c7 + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY13_CTRL2 0x06c8 + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY13_CTRL3 0x06c9 + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY13_CTRL4 0x06ca +#define RTL8367C_ACL_IP_RANGE_ENTRY13_CTRL4_OFFSET 0 +#define RTL8367C_ACL_IP_RANGE_ENTRY13_CTRL4_MASK 0x7 + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY14_CTRL0 0x06cb + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY14_CTRL1 0x06cc + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY14_CTRL2 0x06cd + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY14_CTRL3 0x06ce + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY14_CTRL4 0x06cf +#define RTL8367C_ACL_IP_RANGE_ENTRY14_CTRL4_OFFSET 0 +#define RTL8367C_ACL_IP_RANGE_ENTRY14_CTRL4_MASK 0x7 + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY15_CTRL0 0x06d0 + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY15_CTRL1 0x06d1 + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY15_CTRL2 0x06d2 + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY15_CTRL3 0x06d3 + +#define RTL8367C_REG_ACL_IP_RANGE_ENTRY15_CTRL4 0x06d4 +#define RTL8367C_ACL_IP_RANGE_ENTRY15_CTRL4_OFFSET 0 +#define RTL8367C_ACL_IP_RANGE_ENTRY15_CTRL4_MASK 0x7 + +#define RTL8367C_REG_ACL_ENABLE 0x06d5 +#define RTL8367C_PORT10_ENABLE_OFFSET 10 +#define RTL8367C_PORT10_ENABLE_MASK 0x400 +#define RTL8367C_PORT9_ENABLE_OFFSET 9 +#define RTL8367C_PORT9_ENABLE_MASK 0x200 +#define RTL8367C_PORT8_ENABLE_OFFSET 8 +#define RTL8367C_PORT8_ENABLE_MASK 0x100 +#define RTL8367C_PORT7_ENABLE_OFFSET 7 +#define RTL8367C_PORT7_ENABLE_MASK 0x80 +#define RTL8367C_PORT6_ENABLE_OFFSET 6 +#define RTL8367C_PORT6_ENABLE_MASK 0x40 +#define RTL8367C_PORT5_ENABLE_OFFSET 5 +#define RTL8367C_PORT5_ENABLE_MASK 0x20 +#define RTL8367C_PORT4_ENABLE_OFFSET 4 +#define RTL8367C_PORT4_ENABLE_MASK 0x10 +#define RTL8367C_PORT3_ENABLE_OFFSET 3 +#define RTL8367C_PORT3_ENABLE_MASK 0x8 +#define RTL8367C_PORT2_ENABLE_OFFSET 2 +#define RTL8367C_PORT2_ENABLE_MASK 0x4 +#define RTL8367C_PORT1_ENABLE_OFFSET 1 +#define RTL8367C_PORT1_ENABLE_MASK 0x2 +#define RTL8367C_PORT0_ENABLE_OFFSET 0 +#define RTL8367C_PORT0_ENABLE_MASK 0x1 + +#define RTL8367C_REG_ACL_UNMATCH_PERMIT 0x06d6 +#define RTL8367C_PORT10_PERMIT_OFFSET 10 +#define RTL8367C_PORT10_PERMIT_MASK 0x400 +#define RTL8367C_PORT9_PERMIT_OFFSET 9 +#define RTL8367C_PORT9_PERMIT_MASK 0x200 +#define RTL8367C_PORT8_PERMIT_OFFSET 8 +#define RTL8367C_PORT8_PERMIT_MASK 0x100 +#define RTL8367C_PORT7_PERMIT_OFFSET 7 +#define RTL8367C_PORT7_PERMIT_MASK 0x80 +#define RTL8367C_PORT6_PERMIT_OFFSET 6 +#define RTL8367C_PORT6_PERMIT_MASK 0x40 +#define RTL8367C_PORT5_PERMIT_OFFSET 5 +#define RTL8367C_PORT5_PERMIT_MASK 0x20 +#define RTL8367C_PORT4_PERMIT_OFFSET 4 +#define RTL8367C_PORT4_PERMIT_MASK 0x10 +#define RTL8367C_PORT3_PERMIT_OFFSET 3 +#define RTL8367C_PORT3_PERMIT_MASK 0x8 +#define RTL8367C_PORT2_PERMIT_OFFSET 2 +#define RTL8367C_PORT2_PERMIT_MASK 0x4 +#define RTL8367C_PORT1_PERMIT_OFFSET 1 +#define RTL8367C_PORT1_PERMIT_MASK 0x2 +#define RTL8367C_PORT0_PERMIT_OFFSET 0 +#define RTL8367C_PORT0_PERMIT_MASK 0x1 + +#define RTL8367C_REG_ACL_GPIO_POLARITY 0x06d7 +#define RTL8367C_ACL_GPIO_POLARITY_OFFSET 0 +#define RTL8367C_ACL_GPIO_POLARITY_MASK 0x1 + +#define RTL8367C_REG_ACL_LOG_CNT_TYPE 0x06d8 +#define RTL8367C_ACL_LOG_CNT_TYPE_COUNTER15_TYPE_OFFSET 15 +#define RTL8367C_ACL_LOG_CNT_TYPE_COUNTER15_TYPE_MASK 0x8000 +#define RTL8367C_ACL_LOG_CNT_TYPE_COUNTER14_TYPE_OFFSET 14 +#define RTL8367C_ACL_LOG_CNT_TYPE_COUNTER14_TYPE_MASK 0x4000 +#define RTL8367C_ACL_LOG_CNT_TYPE_COUNTER13_TYPE_OFFSET 13 +#define RTL8367C_ACL_LOG_CNT_TYPE_COUNTER13_TYPE_MASK 0x2000 +#define RTL8367C_ACL_LOG_CNT_TYPE_COUNTER12_TYPE_OFFSET 12 +#define RTL8367C_ACL_LOG_CNT_TYPE_COUNTER12_TYPE_MASK 0x1000 +#define RTL8367C_ACL_LOG_CNT_TYPE_COUNTER11_TYPE_OFFSET 11 +#define RTL8367C_ACL_LOG_CNT_TYPE_COUNTER11_TYPE_MASK 0x800 +#define RTL8367C_ACL_LOG_CNT_TYPE_COUNTER10_TYPE_OFFSET 10 +#define RTL8367C_ACL_LOG_CNT_TYPE_COUNTER10_TYPE_MASK 0x400 +#define RTL8367C_ACL_LOG_CNT_TYPE_COUNTER9_TYPE_OFFSET 9 +#define RTL8367C_ACL_LOG_CNT_TYPE_COUNTER9_TYPE_MASK 0x200 +#define RTL8367C_ACL_LOG_CNT_TYPE_COUNTER8_TYPE_OFFSET 8 +#define RTL8367C_ACL_LOG_CNT_TYPE_COUNTER8_TYPE_MASK 0x100 +#define RTL8367C_ACL_LOG_CNT_TYPE_COUNTER7_TYPE_OFFSET 7 +#define RTL8367C_ACL_LOG_CNT_TYPE_COUNTER7_TYPE_MASK 0x80 +#define RTL8367C_ACL_LOG_CNT_TYPE_COUNTER6_TYPE_OFFSET 6 +#define RTL8367C_ACL_LOG_CNT_TYPE_COUNTER6_TYPE_MASK 0x40 +#define RTL8367C_ACL_LOG_CNT_TYPE_COUNTER5_TYPE_OFFSET 5 +#define RTL8367C_ACL_LOG_CNT_TYPE_COUNTER5_TYPE_MASK 0x20 +#define RTL8367C_ACL_LOG_CNT_TYPE_COUNTER4_TYPE_OFFSET 4 +#define RTL8367C_ACL_LOG_CNT_TYPE_COUNTER4_TYPE_MASK 0x10 +#define RTL8367C_ACL_LOG_CNT_TYPE_COUNTER3_TYPE_OFFSET 3 +#define RTL8367C_ACL_LOG_CNT_TYPE_COUNTER3_TYPE_MASK 0x8 +#define RTL8367C_ACL_LOG_CNT_TYPE_COUNTER2_TYPE_OFFSET 2 +#define RTL8367C_ACL_LOG_CNT_TYPE_COUNTER2_TYPE_MASK 0x4 +#define RTL8367C_ACL_LOG_CNT_TYPE_COUNTER1_TYPE_OFFSET 1 +#define RTL8367C_ACL_LOG_CNT_TYPE_COUNTER1_TYPE_MASK 0x2 +#define RTL8367C_ACL_LOG_CNT_TYPE_COUNTER0_TYPE_OFFSET 0 +#define RTL8367C_ACL_LOG_CNT_TYPE_COUNTER0_TYPE_MASK 0x1 + +#define RTL8367C_REG_ACL_RESET_CFG 0x06d9 +#define RTL8367C_ACL_RESET_CFG_OFFSET 0 +#define RTL8367C_ACL_RESET_CFG_MASK 0x1 + +#define RTL8367C_REG_ACL_DUMMY00 0x06E0 + +#define RTL8367C_REG_ACL_DUMMY01 0x06E1 + +#define RTL8367C_REG_ACL_DUMMY02 0x06E2 + +#define RTL8367C_REG_ACL_DUMMY03 0x06E3 + +#define RTL8367C_REG_ACL_DUMMY04 0x06E4 + +#define RTL8367C_REG_ACL_DUMMY05 0x06E5 + +#define RTL8367C_REG_ACL_DUMMY06 0x06E6 + +#define RTL8367C_REG_ACL_DUMMY07 0x06E7 + +#define RTL8367C_REG_ACL_REASON_01 0x06E8 +#define RTL8367C_ACL_ACT_1_OFFSET 8 +#define RTL8367C_ACL_ACT_1_MASK 0xFF00 +#define RTL8367C_ACL_ACT_0_OFFSET 0 +#define RTL8367C_ACL_ACT_0_MASK 0xFF + +#define RTL8367C_REG_ACL_REASON_23 0x06E9 +#define RTL8367C_ACL_ACT_3_OFFSET 8 +#define RTL8367C_ACL_ACT_3_MASK 0xFF00 +#define RTL8367C_ACL_ACT_2_OFFSET 0 +#define RTL8367C_ACL_ACT_2_MASK 0xFF + +#define RTL8367C_REG_ACL_REASON_45 0x06EA +#define RTL8367C_ACL_ACT_5_OFFSET 8 +#define RTL8367C_ACL_ACT_5_MASK 0xFF00 +#define RTL8367C_ACL_ACT_4_OFFSET 0 +#define RTL8367C_ACL_ACT_4_MASK 0xFF + +#define RTL8367C_REG_ACL_ACCESS_MODE 0x06EB +#define RTL8367C_ACL_ACCESS_MODE_OFFSET 0 +#define RTL8367C_ACL_ACCESS_MODE_MASK 0x1 + +#define RTL8367C_REG_ACL_ACTION_CTRL32 0x06F0 +#define RTL8367C_OP65_NOT_OFFSET 14 +#define RTL8367C_OP65_NOT_MASK 0x4000 +#define RTL8367C_ACT65_GPIO_OFFSET 13 +#define RTL8367C_ACT65_GPIO_MASK 0x2000 +#define RTL8367C_ACT65_FORWARD_OFFSET 12 +#define RTL8367C_ACT65_FORWARD_MASK 0x1000 +#define RTL8367C_ACT65_POLICING_OFFSET 11 +#define RTL8367C_ACT65_POLICING_MASK 0x800 +#define RTL8367C_ACT65_PRIORITY_OFFSET 10 +#define RTL8367C_ACT65_PRIORITY_MASK 0x400 +#define RTL8367C_ACT65_SVID_OFFSET 9 +#define RTL8367C_ACT65_SVID_MASK 0x200 +#define RTL8367C_ACT65_CVID_OFFSET 8 +#define RTL8367C_ACT65_CVID_MASK 0x100 +#define RTL8367C_OP64_NOT_OFFSET 6 +#define RTL8367C_OP64_NOT_MASK 0x40 +#define RTL8367C_ACT64_GPIO_OFFSET 5 +#define RTL8367C_ACT64_GPIO_MASK 0x20 +#define RTL8367C_ACT64_FORWARD_OFFSET 4 +#define RTL8367C_ACT64_FORWARD_MASK 0x10 +#define RTL8367C_ACT64_POLICING_OFFSET 3 +#define RTL8367C_ACT64_POLICING_MASK 0x8 +#define RTL8367C_ACT64_PRIORITY_OFFSET 2 +#define RTL8367C_ACT64_PRIORITY_MASK 0x4 +#define RTL8367C_ACT64_SVID_OFFSET 1 +#define RTL8367C_ACT64_SVID_MASK 0x2 +#define RTL8367C_ACT64_CVID_OFFSET 0 +#define RTL8367C_ACT64_CVID_MASK 0x1 + +#define RTL8367C_REG_ACL_ACTION_CTRL33 0x06F1 +#define RTL8367C_OP67_NOT_OFFSET 14 +#define RTL8367C_OP67_NOT_MASK 0x4000 +#define RTL8367C_ACT67_GPIO_OFFSET 13 +#define RTL8367C_ACT67_GPIO_MASK 0x2000 +#define RTL8367C_ACT67_FORWARD_OFFSET 12 +#define RTL8367C_ACT67_FORWARD_MASK 0x1000 +#define RTL8367C_ACT67_POLICING_OFFSET 11 +#define RTL8367C_ACT67_POLICING_MASK 0x800 +#define RTL8367C_ACT67_PRIORITY_OFFSET 10 +#define RTL8367C_ACT67_PRIORITY_MASK 0x400 +#define RTL8367C_ACT67_SVID_OFFSET 9 +#define RTL8367C_ACT67_SVID_MASK 0x200 +#define RTL8367C_ACT67_CVID_OFFSET 8 +#define RTL8367C_ACT67_CVID_MASK 0x100 +#define RTL8367C_OP66_NOT_OFFSET 6 +#define RTL8367C_OP66_NOT_MASK 0x40 +#define RTL8367C_ACT66_GPIO_OFFSET 5 +#define RTL8367C_ACT66_GPIO_MASK 0x20 +#define RTL8367C_ACT66_FORWARD_OFFSET 4 +#define RTL8367C_ACT66_FORWARD_MASK 0x10 +#define RTL8367C_ACT66_POLICING_OFFSET 3 +#define RTL8367C_ACT66_POLICING_MASK 0x8 +#define RTL8367C_ACT66_PRIORITY_OFFSET 2 +#define RTL8367C_ACT66_PRIORITY_MASK 0x4 +#define RTL8367C_ACT66_SVID_OFFSET 1 +#define RTL8367C_ACT66_SVID_MASK 0x2 +#define RTL8367C_ACT66_CVID_OFFSET 0 +#define RTL8367C_ACT66_CVID_MASK 0x1 + +#define RTL8367C_REG_ACL_ACTION_CTRL34 0x06F2 +#define RTL8367C_OP69_NOT_OFFSET 14 +#define RTL8367C_OP69_NOT_MASK 0x4000 +#define RTL8367C_ACT69_GPIO_OFFSET 13 +#define RTL8367C_ACT69_GPIO_MASK 0x2000 +#define RTL8367C_ACT69_FORWARD_OFFSET 12 +#define RTL8367C_ACT69_FORWARD_MASK 0x1000 +#define RTL8367C_ACT69_POLICING_OFFSET 11 +#define RTL8367C_ACT69_POLICING_MASK 0x800 +#define RTL8367C_ACT69_PRIORITY_OFFSET 10 +#define RTL8367C_ACT69_PRIORITY_MASK 0x400 +#define RTL8367C_ACT69_SVID_OFFSET 9 +#define RTL8367C_ACT69_SVID_MASK 0x200 +#define RTL8367C_ACT69_CVID_OFFSET 8 +#define RTL8367C_ACT69_CVID_MASK 0x100 +#define RTL8367C_OP68_NOT_OFFSET 6 +#define RTL8367C_OP68_NOT_MASK 0x40 +#define RTL8367C_ACT68_GPIO_OFFSET 5 +#define RTL8367C_ACT68_GPIO_MASK 0x20 +#define RTL8367C_ACT68_FORWARD_OFFSET 4 +#define RTL8367C_ACT68_FORWARD_MASK 0x10 +#define RTL8367C_ACT68_POLICING_OFFSET 3 +#define RTL8367C_ACT68_POLICING_MASK 0x8 +#define RTL8367C_ACT68_PRIORITY_OFFSET 2 +#define RTL8367C_ACT68_PRIORITY_MASK 0x4 +#define RTL8367C_ACT68_SVID_OFFSET 1 +#define RTL8367C_ACT68_SVID_MASK 0x2 +#define RTL8367C_ACT68_CVID_OFFSET 0 +#define RTL8367C_ACT68_CVID_MASK 0x1 + +#define RTL8367C_REG_ACL_ACTION_CTRL35 0x06F3 +#define RTL8367C_OP71_NOT_OFFSET 14 +#define RTL8367C_OP71_NOT_MASK 0x4000 +#define RTL8367C_ACT71_GPIO_OFFSET 13 +#define RTL8367C_ACT71_GPIO_MASK 0x2000 +#define RTL8367C_ACT71_FORWARD_OFFSET 12 +#define RTL8367C_ACT71_FORWARD_MASK 0x1000 +#define RTL8367C_ACT71_POLICING_OFFSET 11 +#define RTL8367C_ACT71_POLICING_MASK 0x800 +#define RTL8367C_ACT71_PRIORITY_OFFSET 10 +#define RTL8367C_ACT71_PRIORITY_MASK 0x400 +#define RTL8367C_ACT71_SVID_OFFSET 9 +#define RTL8367C_ACT71_SVID_MASK 0x200 +#define RTL8367C_ACT71_CVID_OFFSET 8 +#define RTL8367C_ACT71_CVID_MASK 0x100 +#define RTL8367C_OP70_NOT_OFFSET 6 +#define RTL8367C_OP70_NOT_MASK 0x40 +#define RTL8367C_ACT70_GPIO_OFFSET 5 +#define RTL8367C_ACT70_GPIO_MASK 0x20 +#define RTL8367C_ACT70_FORWARD_OFFSET 4 +#define RTL8367C_ACT70_FORWARD_MASK 0x10 +#define RTL8367C_ACT70_POLICING_OFFSET 3 +#define RTL8367C_ACT70_POLICING_MASK 0x8 +#define RTL8367C_ACT70_PRIORITY_OFFSET 2 +#define RTL8367C_ACT70_PRIORITY_MASK 0x4 +#define RTL8367C_ACT70_SVID_OFFSET 1 +#define RTL8367C_ACT70_SVID_MASK 0x2 +#define RTL8367C_ACT70_CVID_OFFSET 0 +#define RTL8367C_ACT70_CVID_MASK 0x1 + +#define RTL8367C_REG_ACL_ACTION_CTRL36 0x06F4 +#define RTL8367C_OP73_NOT_OFFSET 14 +#define RTL8367C_OP73_NOT_MASK 0x4000 +#define RTL8367C_ACT73_GPIO_OFFSET 13 +#define RTL8367C_ACT73_GPIO_MASK 0x2000 +#define RTL8367C_ACT73_FORWARD_OFFSET 12 +#define RTL8367C_ACT73_FORWARD_MASK 0x1000 +#define RTL8367C_ACT73_POLICING_OFFSET 11 +#define RTL8367C_ACT73_POLICING_MASK 0x800 +#define RTL8367C_ACT73_PRIORITY_OFFSET 10 +#define RTL8367C_ACT73_PRIORITY_MASK 0x400 +#define RTL8367C_ACT73_SVID_OFFSET 9 +#define RTL8367C_ACT73_SVID_MASK 0x200 +#define RTL8367C_ACT73_CVID_OFFSET 8 +#define RTL8367C_ACT73_CVID_MASK 0x100 +#define RTL8367C_OP72_NOT_OFFSET 6 +#define RTL8367C_OP72_NOT_MASK 0x40 +#define RTL8367C_ACT72_GPIO_OFFSET 5 +#define RTL8367C_ACT72_GPIO_MASK 0x20 +#define RTL8367C_ACT72_FORWARD_OFFSET 4 +#define RTL8367C_ACT72_FORWARD_MASK 0x10 +#define RTL8367C_ACT72_POLICING_OFFSET 3 +#define RTL8367C_ACT72_POLICING_MASK 0x8 +#define RTL8367C_ACT72_PRIORITY_OFFSET 2 +#define RTL8367C_ACT72_PRIORITY_MASK 0x4 +#define RTL8367C_ACT72_SVID_OFFSET 1 +#define RTL8367C_ACT72_SVID_MASK 0x2 +#define RTL8367C_ACT72_CVID_OFFSET 0 +#define RTL8367C_ACT72_CVID_MASK 0x1 + +#define RTL8367C_REG_ACL_ACTION_CTRL37 0x06F5 +#define RTL8367C_OP75_NOT_OFFSET 14 +#define RTL8367C_OP75_NOT_MASK 0x4000 +#define RTL8367C_ACT75_GPIO_OFFSET 13 +#define RTL8367C_ACT75_GPIO_MASK 0x2000 +#define RTL8367C_ACT75_FORWARD_OFFSET 12 +#define RTL8367C_ACT75_FORWARD_MASK 0x1000 +#define RTL8367C_ACT75_POLICING_OFFSET 11 +#define RTL8367C_ACT75_POLICING_MASK 0x800 +#define RTL8367C_ACT75_PRIORITY_OFFSET 10 +#define RTL8367C_ACT75_PRIORITY_MASK 0x400 +#define RTL8367C_ACT75_SVID_OFFSET 9 +#define RTL8367C_ACT75_SVID_MASK 0x200 +#define RTL8367C_ACT75_CVID_OFFSET 8 +#define RTL8367C_ACT75_CVID_MASK 0x100 +#define RTL8367C_OP74_NOT_OFFSET 6 +#define RTL8367C_OP74_NOT_MASK 0x40 +#define RTL8367C_ACT74_GPIO_OFFSET 5 +#define RTL8367C_ACT74_GPIO_MASK 0x20 +#define RTL8367C_ACT74_FORWARD_OFFSET 4 +#define RTL8367C_ACT74_FORWARD_MASK 0x10 +#define RTL8367C_ACT74_POLICING_OFFSET 3 +#define RTL8367C_ACT74_POLICING_MASK 0x8 +#define RTL8367C_ACT74_PRIORITY_OFFSET 2 +#define RTL8367C_ACT74_PRIORITY_MASK 0x4 +#define RTL8367C_ACT74_SVID_OFFSET 1 +#define RTL8367C_ACT74_SVID_MASK 0x2 +#define RTL8367C_ACT74_CVID_OFFSET 0 +#define RTL8367C_ACT74_CVID_MASK 0x1 + +#define RTL8367C_REG_ACL_ACTION_CTRL38 0x06F6 +#define RTL8367C_OP77_NOT_OFFSET 14 +#define RTL8367C_OP77_NOT_MASK 0x4000 +#define RTL8367C_ACT77_GPIO_OFFSET 13 +#define RTL8367C_ACT77_GPIO_MASK 0x2000 +#define RTL8367C_ACT77_FORWARD_OFFSET 12 +#define RTL8367C_ACT77_FORWARD_MASK 0x1000 +#define RTL8367C_ACT77_POLICING_OFFSET 11 +#define RTL8367C_ACT77_POLICING_MASK 0x800 +#define RTL8367C_ACT77_PRIORITY_OFFSET 10 +#define RTL8367C_ACT77_PRIORITY_MASK 0x400 +#define RTL8367C_ACT77_SVID_OFFSET 9 +#define RTL8367C_ACT77_SVID_MASK 0x200 +#define RTL8367C_ACT77_CVID_OFFSET 8 +#define RTL8367C_ACT77_CVID_MASK 0x100 +#define RTL8367C_OP76_NOT_OFFSET 6 +#define RTL8367C_OP76_NOT_MASK 0x40 +#define RTL8367C_ACT76_GPIO_OFFSET 5 +#define RTL8367C_ACT76_GPIO_MASK 0x20 +#define RTL8367C_ACT76_FORWARD_OFFSET 4 +#define RTL8367C_ACT76_FORWARD_MASK 0x10 +#define RTL8367C_ACT76_POLICING_OFFSET 3 +#define RTL8367C_ACT76_POLICING_MASK 0x8 +#define RTL8367C_ACT76_PRIORITY_OFFSET 2 +#define RTL8367C_ACT76_PRIORITY_MASK 0x4 +#define RTL8367C_ACT76_SVID_OFFSET 1 +#define RTL8367C_ACT76_SVID_MASK 0x2 +#define RTL8367C_ACT76_CVID_OFFSET 0 +#define RTL8367C_ACT76_CVID_MASK 0x1 + +#define RTL8367C_REG_ACL_ACTION_CTRL39 0x06F7 +#define RTL8367C_OP79_NOT_OFFSET 14 +#define RTL8367C_OP79_NOT_MASK 0x4000 +#define RTL8367C_ACT79_GPIO_OFFSET 13 +#define RTL8367C_ACT79_GPIO_MASK 0x2000 +#define RTL8367C_ACT79_FORWARD_OFFSET 12 +#define RTL8367C_ACT79_FORWARD_MASK 0x1000 +#define RTL8367C_ACT79_POLICING_OFFSET 11 +#define RTL8367C_ACT79_POLICING_MASK 0x800 +#define RTL8367C_ACT79_PRIORITY_OFFSET 10 +#define RTL8367C_ACT79_PRIORITY_MASK 0x400 +#define RTL8367C_ACT79_SVID_OFFSET 9 +#define RTL8367C_ACT79_SVID_MASK 0x200 +#define RTL8367C_ACT79_CVID_OFFSET 8 +#define RTL8367C_ACT79_CVID_MASK 0x100 +#define RTL8367C_OP78_NOT_OFFSET 6 +#define RTL8367C_OP78_NOT_MASK 0x40 +#define RTL8367C_ACT78_GPIO_OFFSET 5 +#define RTL8367C_ACT78_GPIO_MASK 0x20 +#define RTL8367C_ACT78_FORWARD_OFFSET 4 +#define RTL8367C_ACT78_FORWARD_MASK 0x10 +#define RTL8367C_ACT78_POLICING_OFFSET 3 +#define RTL8367C_ACT78_POLICING_MASK 0x8 +#define RTL8367C_ACT78_PRIORITY_OFFSET 2 +#define RTL8367C_ACT78_PRIORITY_MASK 0x4 +#define RTL8367C_ACT78_SVID_OFFSET 1 +#define RTL8367C_ACT78_SVID_MASK 0x2 +#define RTL8367C_ACT78_CVID_OFFSET 0 +#define RTL8367C_ACT78_CVID_MASK 0x1 + +#define RTL8367C_REG_ACL_ACTION_CTRL40 0x06F8 +#define RTL8367C_OP81_NOT_OFFSET 14 +#define RTL8367C_OP81_NOT_MASK 0x4000 +#define RTL8367C_ACT81_GPIO_OFFSET 13 +#define RTL8367C_ACT81_GPIO_MASK 0x2000 +#define RTL8367C_ACT81_FORWARD_OFFSET 12 +#define RTL8367C_ACT81_FORWARD_MASK 0x1000 +#define RTL8367C_ACT81_POLICING_OFFSET 11 +#define RTL8367C_ACT81_POLICING_MASK 0x800 +#define RTL8367C_ACT81_PRIORITY_OFFSET 10 +#define RTL8367C_ACT81_PRIORITY_MASK 0x400 +#define RTL8367C_ACT81_SVID_OFFSET 9 +#define RTL8367C_ACT81_SVID_MASK 0x200 +#define RTL8367C_ACT81_CVID_OFFSET 8 +#define RTL8367C_ACT81_CVID_MASK 0x100 +#define RTL8367C_OP80_NOT_OFFSET 6 +#define RTL8367C_OP80_NOT_MASK 0x40 +#define RTL8367C_ACT80_GPIO_OFFSET 5 +#define RTL8367C_ACT80_GPIO_MASK 0x20 +#define RTL8367C_ACT80_FORWARD_OFFSET 4 +#define RTL8367C_ACT80_FORWARD_MASK 0x10 +#define RTL8367C_ACT80_POLICING_OFFSET 3 +#define RTL8367C_ACT80_POLICING_MASK 0x8 +#define RTL8367C_ACT80_PRIORITY_OFFSET 2 +#define RTL8367C_ACT80_PRIORITY_MASK 0x4 +#define RTL8367C_ACT80_SVID_OFFSET 1 +#define RTL8367C_ACT80_SVID_MASK 0x2 +#define RTL8367C_ACT80_CVID_OFFSET 0 +#define RTL8367C_ACT80_CVID_MASK 0x1 + +#define RTL8367C_REG_ACL_ACTION_CTRL41 0x06F9 +#define RTL8367C_OP83_NOT_OFFSET 14 +#define RTL8367C_OP83_NOT_MASK 0x4000 +#define RTL8367C_ACT83_GPIO_OFFSET 13 +#define RTL8367C_ACT83_GPIO_MASK 0x2000 +#define RTL8367C_ACT83_FORWARD_OFFSET 12 +#define RTL8367C_ACT83_FORWARD_MASK 0x1000 +#define RTL8367C_ACT83_POLICING_OFFSET 11 +#define RTL8367C_ACT83_POLICING_MASK 0x800 +#define RTL8367C_ACT83_PRIORITY_OFFSET 10 +#define RTL8367C_ACT83_PRIORITY_MASK 0x400 +#define RTL8367C_ACT83_SVID_OFFSET 9 +#define RTL8367C_ACT83_SVID_MASK 0x200 +#define RTL8367C_ACT83_CVID_OFFSET 8 +#define RTL8367C_ACT83_CVID_MASK 0x100 +#define RTL8367C_OP82_NOT_OFFSET 6 +#define RTL8367C_OP82_NOT_MASK 0x40 +#define RTL8367C_ACT82_GPIO_OFFSET 5 +#define RTL8367C_ACT82_GPIO_MASK 0x20 +#define RTL8367C_ACT82_FORWARD_OFFSET 4 +#define RTL8367C_ACT82_FORWARD_MASK 0x10 +#define RTL8367C_ACT82_POLICING_OFFSET 3 +#define RTL8367C_ACT82_POLICING_MASK 0x8 +#define RTL8367C_ACT82_PRIORITY_OFFSET 2 +#define RTL8367C_ACT82_PRIORITY_MASK 0x4 +#define RTL8367C_ACT82_SVID_OFFSET 1 +#define RTL8367C_ACT82_SVID_MASK 0x2 +#define RTL8367C_ACT82_CVID_OFFSET 0 +#define RTL8367C_ACT82_CVID_MASK 0x1 + +#define RTL8367C_REG_ACL_ACTION_CTRL42 0x06FA +#define RTL8367C_OP85_NOT_OFFSET 14 +#define RTL8367C_OP85_NOT_MASK 0x4000 +#define RTL8367C_ACT85_GPIO_OFFSET 13 +#define RTL8367C_ACT85_GPIO_MASK 0x2000 +#define RTL8367C_ACT85_FORWARD_OFFSET 12 +#define RTL8367C_ACT85_FORWARD_MASK 0x1000 +#define RTL8367C_ACT85_POLICING_OFFSET 11 +#define RTL8367C_ACT85_POLICING_MASK 0x800 +#define RTL8367C_ACT85_PRIORITY_OFFSET 10 +#define RTL8367C_ACT85_PRIORITY_MASK 0x400 +#define RTL8367C_ACT85_SVID_OFFSET 9 +#define RTL8367C_ACT85_SVID_MASK 0x200 +#define RTL8367C_ACT85_CVID_OFFSET 8 +#define RTL8367C_ACT85_CVID_MASK 0x100 +#define RTL8367C_OP84_NOT_OFFSET 6 +#define RTL8367C_OP84_NOT_MASK 0x40 +#define RTL8367C_ACT84_GPIO_OFFSET 5 +#define RTL8367C_ACT84_GPIO_MASK 0x20 +#define RTL8367C_ACT84_FORWARD_OFFSET 4 +#define RTL8367C_ACT84_FORWARD_MASK 0x10 +#define RTL8367C_ACT84_POLICING_OFFSET 3 +#define RTL8367C_ACT84_POLICING_MASK 0x8 +#define RTL8367C_ACT84_PRIORITY_OFFSET 2 +#define RTL8367C_ACT84_PRIORITY_MASK 0x4 +#define RTL8367C_ACT84_SVID_OFFSET 1 +#define RTL8367C_ACT84_SVID_MASK 0x2 +#define RTL8367C_ACT84_CVID_OFFSET 0 +#define RTL8367C_ACT84_CVID_MASK 0x1 + +#define RTL8367C_REG_ACL_ACTION_CTRL43 0x06FB +#define RTL8367C_OP87_NOT_OFFSET 14 +#define RTL8367C_OP87_NOT_MASK 0x4000 +#define RTL8367C_ACT87_GPIO_OFFSET 13 +#define RTL8367C_ACT87_GPIO_MASK 0x2000 +#define RTL8367C_ACT87_FORWARD_OFFSET 12 +#define RTL8367C_ACT87_FORWARD_MASK 0x1000 +#define RTL8367C_ACT87_POLICING_OFFSET 11 +#define RTL8367C_ACT87_POLICING_MASK 0x800 +#define RTL8367C_ACT87_PRIORITY_OFFSET 10 +#define RTL8367C_ACT87_PRIORITY_MASK 0x400 +#define RTL8367C_ACT87_SVID_OFFSET 9 +#define RTL8367C_ACT87_SVID_MASK 0x200 +#define RTL8367C_ACT87_CVID_OFFSET 8 +#define RTL8367C_ACT87_CVID_MASK 0x100 +#define RTL8367C_OP86_NOT_OFFSET 6 +#define RTL8367C_OP86_NOT_MASK 0x40 +#define RTL8367C_ACT86_GPIO_OFFSET 5 +#define RTL8367C_ACT86_GPIO_MASK 0x20 +#define RTL8367C_ACT86_FORWARD_OFFSET 4 +#define RTL8367C_ACT86_FORWARD_MASK 0x10 +#define RTL8367C_ACT86_POLICING_OFFSET 3 +#define RTL8367C_ACT86_POLICING_MASK 0x8 +#define RTL8367C_ACT86_PRIORITY_OFFSET 2 +#define RTL8367C_ACT86_PRIORITY_MASK 0x4 +#define RTL8367C_ACT86_SVID_OFFSET 1 +#define RTL8367C_ACT86_SVID_MASK 0x2 +#define RTL8367C_ACT86_CVID_OFFSET 0 +#define RTL8367C_ACT86_CVID_MASK 0x1 + +#define RTL8367C_REG_ACL_ACTION_CTRL44 0x06FC +#define RTL8367C_OP89_NOT_OFFSET 14 +#define RTL8367C_OP89_NOT_MASK 0x4000 +#define RTL8367C_ACT89_GPIO_OFFSET 13 +#define RTL8367C_ACT89_GPIO_MASK 0x2000 +#define RTL8367C_ACT89_FORWARD_OFFSET 12 +#define RTL8367C_ACT89_FORWARD_MASK 0x1000 +#define RTL8367C_ACT89_POLICING_OFFSET 11 +#define RTL8367C_ACT89_POLICING_MASK 0x800 +#define RTL8367C_ACT89_PRIORITY_OFFSET 10 +#define RTL8367C_ACT89_PRIORITY_MASK 0x400 +#define RTL8367C_ACT89_SVID_OFFSET 9 +#define RTL8367C_ACT89_SVID_MASK 0x200 +#define RTL8367C_ACT89_CVID_OFFSET 8 +#define RTL8367C_ACT89_CVID_MASK 0x100 +#define RTL8367C_OP88_NOT_OFFSET 6 +#define RTL8367C_OP88_NOT_MASK 0x40 +#define RTL8367C_ACT88_GPIO_OFFSET 5 +#define RTL8367C_ACT88_GPIO_MASK 0x20 +#define RTL8367C_ACT88_FORWARD_OFFSET 4 +#define RTL8367C_ACT88_FORWARD_MASK 0x10 +#define RTL8367C_ACT88_POLICING_OFFSET 3 +#define RTL8367C_ACT88_POLICING_MASK 0x8 +#define RTL8367C_ACT88_PRIORITY_OFFSET 2 +#define RTL8367C_ACT88_PRIORITY_MASK 0x4 +#define RTL8367C_ACT88_SVID_OFFSET 1 +#define RTL8367C_ACT88_SVID_MASK 0x2 +#define RTL8367C_ACT88_CVID_OFFSET 0 +#define RTL8367C_ACT88_CVID_MASK 0x1 + +#define RTL8367C_REG_ACL_ACTION_CTRL45 0x06FD +#define RTL8367C_OP91_NOT_OFFSET 14 +#define RTL8367C_OP91_NOT_MASK 0x4000 +#define RTL8367C_ACT91_GPIO_OFFSET 13 +#define RTL8367C_ACT91_GPIO_MASK 0x2000 +#define RTL8367C_ACT91_FORWARD_OFFSET 12 +#define RTL8367C_ACT91_FORWARD_MASK 0x1000 +#define RTL8367C_ACT91_POLICING_OFFSET 11 +#define RTL8367C_ACT91_POLICING_MASK 0x800 +#define RTL8367C_ACT91_PRIORITY_OFFSET 10 +#define RTL8367C_ACT91_PRIORITY_MASK 0x400 +#define RTL8367C_ACT91_SVID_OFFSET 9 +#define RTL8367C_ACT91_SVID_MASK 0x200 +#define RTL8367C_ACT91_CVID_OFFSET 8 +#define RTL8367C_ACT91_CVID_MASK 0x100 +#define RTL8367C_OP90_NOT_OFFSET 6 +#define RTL8367C_OP90_NOT_MASK 0x40 +#define RTL8367C_ACT90_GPIO_OFFSET 5 +#define RTL8367C_ACT90_GPIO_MASK 0x20 +#define RTL8367C_ACT90_FORWARD_OFFSET 4 +#define RTL8367C_ACT90_FORWARD_MASK 0x10 +#define RTL8367C_ACT90_POLICING_OFFSET 3 +#define RTL8367C_ACT90_POLICING_MASK 0x8 +#define RTL8367C_ACT90_PRIORITY_OFFSET 2 +#define RTL8367C_ACT90_PRIORITY_MASK 0x4 +#define RTL8367C_ACT90_SVID_OFFSET 1 +#define RTL8367C_ACT90_SVID_MASK 0x2 +#define RTL8367C_ACT90_CVID_OFFSET 0 +#define RTL8367C_ACT90_CVID_MASK 0x1 + +#define RTL8367C_REG_ACL_ACTION_CTRL46 0x06FE +#define RTL8367C_OP93_NOT_OFFSET 14 +#define RTL8367C_OP93_NOT_MASK 0x4000 +#define RTL8367C_ACT93_GPIO_OFFSET 13 +#define RTL8367C_ACT93_GPIO_MASK 0x2000 +#define RTL8367C_ACT93_FORWARD_OFFSET 12 +#define RTL8367C_ACT93_FORWARD_MASK 0x1000 +#define RTL8367C_ACT93_POLICING_OFFSET 11 +#define RTL8367C_ACT93_POLICING_MASK 0x800 +#define RTL8367C_ACT93_PRIORITY_OFFSET 10 +#define RTL8367C_ACT93_PRIORITY_MASK 0x400 +#define RTL8367C_ACT93_SVID_OFFSET 9 +#define RTL8367C_ACT93_SVID_MASK 0x200 +#define RTL8367C_ACT93_CVID_OFFSET 8 +#define RTL8367C_ACT93_CVID_MASK 0x100 +#define RTL8367C_OP92_NOT_OFFSET 6 +#define RTL8367C_OP92_NOT_MASK 0x40 +#define RTL8367C_ACT92_GPIO_OFFSET 5 +#define RTL8367C_ACT92_GPIO_MASK 0x20 +#define RTL8367C_ACT92_FORWARD_OFFSET 4 +#define RTL8367C_ACT92_FORWARD_MASK 0x10 +#define RTL8367C_ACT92_POLICING_OFFSET 3 +#define RTL8367C_ACT92_POLICING_MASK 0x8 +#define RTL8367C_ACT92_PRIORITY_OFFSET 2 +#define RTL8367C_ACT92_PRIORITY_MASK 0x4 +#define RTL8367C_ACT92_SVID_OFFSET 1 +#define RTL8367C_ACT92_SVID_MASK 0x2 +#define RTL8367C_ACT92_CVID_OFFSET 0 +#define RTL8367C_ACT92_CVID_MASK 0x1 + +#define RTL8367C_REG_ACL_ACTION_CTRL47 0x06FF +#define RTL8367C_OP95_NOT_OFFSET 14 +#define RTL8367C_OP95_NOT_MASK 0x4000 +#define RTL8367C_ACT95_GPIO_OFFSET 13 +#define RTL8367C_ACT95_GPIO_MASK 0x2000 +#define RTL8367C_ACT95_FORWARD_OFFSET 12 +#define RTL8367C_ACT95_FORWARD_MASK 0x1000 +#define RTL8367C_ACT95_POLICING_OFFSET 11 +#define RTL8367C_ACT95_POLICING_MASK 0x800 +#define RTL8367C_ACT95_PRIORITY_OFFSET 10 +#define RTL8367C_ACT95_PRIORITY_MASK 0x400 +#define RTL8367C_ACT95_SVID_OFFSET 9 +#define RTL8367C_ACT95_SVID_MASK 0x200 +#define RTL8367C_ACT95_CVID_OFFSET 8 +#define RTL8367C_ACT95_CVID_MASK 0x100 +#define RTL8367C_OP94_NOT_OFFSET 6 +#define RTL8367C_OP94_NOT_MASK 0x40 +#define RTL8367C_ACT94_GPIO_OFFSET 5 +#define RTL8367C_ACT94_GPIO_MASK 0x20 +#define RTL8367C_ACT94_FORWARD_OFFSET 4 +#define RTL8367C_ACT94_FORWARD_MASK 0x10 +#define RTL8367C_ACT94_POLICING_OFFSET 3 +#define RTL8367C_ACT94_POLICING_MASK 0x8 +#define RTL8367C_ACT94_PRIORITY_OFFSET 2 +#define RTL8367C_ACT94_PRIORITY_MASK 0x4 +#define RTL8367C_ACT94_SVID_OFFSET 1 +#define RTL8367C_ACT94_SVID_MASK 0x2 +#define RTL8367C_ACT94_CVID_OFFSET 0 +#define RTL8367C_ACT94_CVID_MASK 0x1 + +/* (16'h0700)cvlan_reg */ + +#define RTL8367C_REG_VLAN_PVID_CTRL0 0x0700 +#define RTL8367C_PORT1_VIDX_OFFSET 8 +#define RTL8367C_PORT1_VIDX_MASK 0x1F00 +#define RTL8367C_PORT0_VIDX_OFFSET 0 +#define RTL8367C_PORT0_VIDX_MASK 0x1F + +#define RTL8367C_REG_VLAN_PVID_CTRL1 0x0701 +#define RTL8367C_PORT3_VIDX_OFFSET 8 +#define RTL8367C_PORT3_VIDX_MASK 0x1F00 +#define RTL8367C_PORT2_VIDX_OFFSET 0 +#define RTL8367C_PORT2_VIDX_MASK 0x1F + +#define RTL8367C_REG_VLAN_PVID_CTRL2 0x0702 +#define RTL8367C_PORT5_VIDX_OFFSET 8 +#define RTL8367C_PORT5_VIDX_MASK 0x1F00 +#define RTL8367C_PORT4_VIDX_OFFSET 0 +#define RTL8367C_PORT4_VIDX_MASK 0x1F + +#define RTL8367C_REG_VLAN_PVID_CTRL3 0x0703 +#define RTL8367C_PORT7_VIDX_OFFSET 8 +#define RTL8367C_PORT7_VIDX_MASK 0x1F00 +#define RTL8367C_PORT6_VIDX_OFFSET 0 +#define RTL8367C_PORT6_VIDX_MASK 0x1F + +#define RTL8367C_REG_VLAN_PVID_CTRL4 0x0704 +#define RTL8367C_PORT9_VIDX_OFFSET 8 +#define RTL8367C_PORT9_VIDX_MASK 0x1F00 +#define RTL8367C_PORT8_VIDX_OFFSET 0 +#define RTL8367C_PORT8_VIDX_MASK 0x1F + +#define RTL8367C_REG_VLAN_PVID_CTRL5 0x0705 +#define RTL8367C_VLAN_PVID_CTRL5_OFFSET 0 +#define RTL8367C_VLAN_PVID_CTRL5_MASK 0x1F + +#define RTL8367C_REG_VLAN_PPB0_VALID 0x0708 +#define RTL8367C_VLAN_PPB0_VALID_VALID_EXT_OFFSET 8 +#define RTL8367C_VLAN_PPB0_VALID_VALID_EXT_MASK 0x700 +#define RTL8367C_VLAN_PPB0_VALID_VALID_OFFSET 0 +#define RTL8367C_VLAN_PPB0_VALID_VALID_MASK 0xFF + +#define RTL8367C_REG_VLAN_PPB0_CTRL0 0x0709 +#define RTL8367C_VLAN_PPB0_CTRL0_PORT2_INDEX_OFFSET 10 +#define RTL8367C_VLAN_PPB0_CTRL0_PORT2_INDEX_MASK 0x7C00 +#define RTL8367C_VLAN_PPB0_CTRL0_PORT1_INDEX_OFFSET 5 +#define RTL8367C_VLAN_PPB0_CTRL0_PORT1_INDEX_MASK 0x3E0 +#define RTL8367C_VLAN_PPB0_CTRL0_PORT0_INDEX_OFFSET 0 +#define RTL8367C_VLAN_PPB0_CTRL0_PORT0_INDEX_MASK 0x1F + +#define RTL8367C_REG_VLAN_PPB0_CTRL1 0x070a +#define RTL8367C_VLAN_PPB0_CTRL1_PORT5_INDEX_OFFSET 10 +#define RTL8367C_VLAN_PPB0_CTRL1_PORT5_INDEX_MASK 0x7C00 +#define RTL8367C_VLAN_PPB0_CTRL1_PORT4_INDEX_OFFSET 5 +#define RTL8367C_VLAN_PPB0_CTRL1_PORT4_INDEX_MASK 0x3E0 +#define RTL8367C_VLAN_PPB0_CTRL1_PORT3_INDEX_OFFSET 0 +#define RTL8367C_VLAN_PPB0_CTRL1_PORT3_INDEX_MASK 0x1F + +#define RTL8367C_REG_VLAN_PPB0_CTRL2 0x070b +#define RTL8367C_VLAN_PPB0_CTRL2_FRAME_TYPE_OFFSET 10 +#define RTL8367C_VLAN_PPB0_CTRL2_FRAME_TYPE_MASK 0xC00 +#define RTL8367C_VLAN_PPB0_CTRL2_PORT7_INDEX_OFFSET 5 +#define RTL8367C_VLAN_PPB0_CTRL2_PORT7_INDEX_MASK 0x3E0 +#define RTL8367C_VLAN_PPB0_CTRL2_PORT6_INDEX_OFFSET 0 +#define RTL8367C_VLAN_PPB0_CTRL2_PORT6_INDEX_MASK 0x1F + +#define RTL8367C_REG_VLAN_PPB0_CTRL4 0x070c +#define RTL8367C_VLAN_PPB0_CTRL4_PORT10_INDEX_OFFSET 10 +#define RTL8367C_VLAN_PPB0_CTRL4_PORT10_INDEX_MASK 0x7C00 +#define RTL8367C_VLAN_PPB0_CTRL4_PORT9_INDEX_OFFSET 5 +#define RTL8367C_VLAN_PPB0_CTRL4_PORT9_INDEX_MASK 0x3E0 +#define RTL8367C_VLAN_PPB0_CTRL4_PORT8_INDEX_OFFSET 0 +#define RTL8367C_VLAN_PPB0_CTRL4_PORT8_INDEX_MASK 0x1F + +#define RTL8367C_REG_VLAN_PPB0_CTRL3 0x070f + +#define RTL8367C_REG_VLAN_PPB1_VALID 0x0710 +#define RTL8367C_VLAN_PPB1_VALID_VALID_EXT_OFFSET 8 +#define RTL8367C_VLAN_PPB1_VALID_VALID_EXT_MASK 0x700 +#define RTL8367C_VLAN_PPB1_VALID_VALID_OFFSET 0 +#define RTL8367C_VLAN_PPB1_VALID_VALID_MASK 0xFF + +#define RTL8367C_REG_VLAN_PPB1_CTRL0 0x0711 +#define RTL8367C_VLAN_PPB1_CTRL0_PORT2_INDEX_OFFSET 10 +#define RTL8367C_VLAN_PPB1_CTRL0_PORT2_INDEX_MASK 0x7C00 +#define RTL8367C_VLAN_PPB1_CTRL0_PORT1_INDEX_OFFSET 5 +#define RTL8367C_VLAN_PPB1_CTRL0_PORT1_INDEX_MASK 0x3E0 +#define RTL8367C_VLAN_PPB1_CTRL0_PORT0_INDEX_OFFSET 0 +#define RTL8367C_VLAN_PPB1_CTRL0_PORT0_INDEX_MASK 0x1F + +#define RTL8367C_REG_VLAN_PPB1_CTRL1 0x0712 +#define RTL8367C_VLAN_PPB1_CTRL1_PORT5_INDEX_OFFSET 10 +#define RTL8367C_VLAN_PPB1_CTRL1_PORT5_INDEX_MASK 0x7C00 +#define RTL8367C_VLAN_PPB1_CTRL1_PORT4_INDEX_OFFSET 5 +#define RTL8367C_VLAN_PPB1_CTRL1_PORT4_INDEX_MASK 0x3E0 +#define RTL8367C_VLAN_PPB1_CTRL1_PORT3_INDEX_OFFSET 0 +#define RTL8367C_VLAN_PPB1_CTRL1_PORT3_INDEX_MASK 0x1F + +#define RTL8367C_REG_VLAN_PPB1_CTRL2 0x0713 +#define RTL8367C_VLAN_PPB1_CTRL2_FRAME_TYPE_OFFSET 10 +#define RTL8367C_VLAN_PPB1_CTRL2_FRAME_TYPE_MASK 0xC00 +#define RTL8367C_VLAN_PPB1_CTRL2_PORT7_INDEX_OFFSET 5 +#define RTL8367C_VLAN_PPB1_CTRL2_PORT7_INDEX_MASK 0x3E0 +#define RTL8367C_VLAN_PPB1_CTRL2_PORT6_INDEX_OFFSET 0 +#define RTL8367C_VLAN_PPB1_CTRL2_PORT6_INDEX_MASK 0x1F + +#define RTL8367C_REG_VLAN_PPB1_CTRL4 0x0714 +#define RTL8367C_VLAN_PPB1_CTRL4_PORT10_INDEX_OFFSET 10 +#define RTL8367C_VLAN_PPB1_CTRL4_PORT10_INDEX_MASK 0x7C00 +#define RTL8367C_VLAN_PPB1_CTRL4_PORT9_INDEX_OFFSET 5 +#define RTL8367C_VLAN_PPB1_CTRL4_PORT9_INDEX_MASK 0x3E0 +#define RTL8367C_VLAN_PPB1_CTRL4_PORT8_INDEX_OFFSET 0 +#define RTL8367C_VLAN_PPB1_CTRL4_PORT8_INDEX_MASK 0x1F + +#define RTL8367C_REG_VLAN_PPB1_CTRL3 0x0717 + +#define RTL8367C_REG_VLAN_PPB2_VALID 0x0718 +#define RTL8367C_VLAN_PPB2_VALID_VALID_EXT_OFFSET 8 +#define RTL8367C_VLAN_PPB2_VALID_VALID_EXT_MASK 0x700 +#define RTL8367C_VLAN_PPB2_VALID_VALID_OFFSET 0 +#define RTL8367C_VLAN_PPB2_VALID_VALID_MASK 0xFF + +#define RTL8367C_REG_VLAN_PPB2_CTRL0 0x0719 +#define RTL8367C_VLAN_PPB2_CTRL0_PORT2_INDEX_OFFSET 10 +#define RTL8367C_VLAN_PPB2_CTRL0_PORT2_INDEX_MASK 0x7C00 +#define RTL8367C_VLAN_PPB2_CTRL0_PORT1_INDEX_OFFSET 5 +#define RTL8367C_VLAN_PPB2_CTRL0_PORT1_INDEX_MASK 0x3E0 +#define RTL8367C_VLAN_PPB2_CTRL0_PORT0_INDEX_OFFSET 0 +#define RTL8367C_VLAN_PPB2_CTRL0_PORT0_INDEX_MASK 0x1F + +#define RTL8367C_REG_VLAN_PPB2_CTRL1 0x071a +#define RTL8367C_VLAN_PPB2_CTRL1_PORT5_INDEX_OFFSET 10 +#define RTL8367C_VLAN_PPB2_CTRL1_PORT5_INDEX_MASK 0x7C00 +#define RTL8367C_VLAN_PPB2_CTRL1_PORT4_INDEX_OFFSET 5 +#define RTL8367C_VLAN_PPB2_CTRL1_PORT4_INDEX_MASK 0x3E0 +#define RTL8367C_VLAN_PPB2_CTRL1_PORT3_INDEX_OFFSET 0 +#define RTL8367C_VLAN_PPB2_CTRL1_PORT3_INDEX_MASK 0x1F + +#define RTL8367C_REG_VLAN_PPB2_CTRL2 0x071b +#define RTL8367C_VLAN_PPB2_CTRL2_FRAME_TYPE_OFFSET 10 +#define RTL8367C_VLAN_PPB2_CTRL2_FRAME_TYPE_MASK 0xC00 +#define RTL8367C_VLAN_PPB2_CTRL2_PORT7_INDEX_OFFSET 5 +#define RTL8367C_VLAN_PPB2_CTRL2_PORT7_INDEX_MASK 0x3E0 +#define RTL8367C_VLAN_PPB2_CTRL2_PORT6_INDEX_OFFSET 0 +#define RTL8367C_VLAN_PPB2_CTRL2_PORT6_INDEX_MASK 0x1F + +#define RTL8367C_REG_VLAN_PPB2_CTRL4 0x071c +#define RTL8367C_VLAN_PPB2_CTRL4_PORT10_INDEX_OFFSET 10 +#define RTL8367C_VLAN_PPB2_CTRL4_PORT10_INDEX_MASK 0x7C00 +#define RTL8367C_VLAN_PPB2_CTRL4_PORT9_INDEX_OFFSET 5 +#define RTL8367C_VLAN_PPB2_CTRL4_PORT9_INDEX_MASK 0x3E0 +#define RTL8367C_VLAN_PPB2_CTRL4_PORT8_INDEX_OFFSET 0 +#define RTL8367C_VLAN_PPB2_CTRL4_PORT8_INDEX_MASK 0x1F + +#define RTL8367C_REG_VLAN_PPB2_CTRL3 0x071f + +#define RTL8367C_REG_VLAN_PPB3_VALID 0x0720 +#define RTL8367C_VLAN_PPB3_VALID_VALID_EXT_OFFSET 8 +#define RTL8367C_VLAN_PPB3_VALID_VALID_EXT_MASK 0x700 +#define RTL8367C_VLAN_PPB3_VALID_VALID_OFFSET 0 +#define RTL8367C_VLAN_PPB3_VALID_VALID_MASK 0xFF + +#define RTL8367C_REG_VLAN_PPB3_CTRL0 0x0721 +#define RTL8367C_VLAN_PPB3_CTRL0_PORT2_INDEX_OFFSET 10 +#define RTL8367C_VLAN_PPB3_CTRL0_PORT2_INDEX_MASK 0x7C00 +#define RTL8367C_VLAN_PPB3_CTRL0_PORT1_INDEX_OFFSET 5 +#define RTL8367C_VLAN_PPB3_CTRL0_PORT1_INDEX_MASK 0x3E0 +#define RTL8367C_VLAN_PPB3_CTRL0_PORT0_INDEX_OFFSET 0 +#define RTL8367C_VLAN_PPB3_CTRL0_PORT0_INDEX_MASK 0x1F + +#define RTL8367C_REG_VLAN_PPB3_CTRL1 0x0722 +#define RTL8367C_VLAN_PPB3_CTRL1_PORT5_INDEX_OFFSET 10 +#define RTL8367C_VLAN_PPB3_CTRL1_PORT5_INDEX_MASK 0x7C00 +#define RTL8367C_VLAN_PPB3_CTRL1_PORT4_INDEX_OFFSET 5 +#define RTL8367C_VLAN_PPB3_CTRL1_PORT4_INDEX_MASK 0x3E0 +#define RTL8367C_VLAN_PPB3_CTRL1_PORT3_INDEX_OFFSET 0 +#define RTL8367C_VLAN_PPB3_CTRL1_PORT3_INDEX_MASK 0x1F + +#define RTL8367C_REG_VLAN_PPB3_CTRL2 0x0723 +#define RTL8367C_VLAN_PPB3_CTRL2_FRAME_TYPE_OFFSET 10 +#define RTL8367C_VLAN_PPB3_CTRL2_FRAME_TYPE_MASK 0xC00 +#define RTL8367C_VLAN_PPB3_CTRL2_PORT7_INDEX_OFFSET 5 +#define RTL8367C_VLAN_PPB3_CTRL2_PORT7_INDEX_MASK 0x3E0 +#define RTL8367C_VLAN_PPB3_CTRL2_PORT6_INDEX_OFFSET 0 +#define RTL8367C_VLAN_PPB3_CTRL2_PORT6_INDEX_MASK 0x1F + +#define RTL8367C_REG_VLAN_PPB3_CTRL4 0x0724 +#define RTL8367C_VLAN_PPB3_CTRL4_PORT10_INDEX_OFFSET 10 +#define RTL8367C_VLAN_PPB3_CTRL4_PORT10_INDEX_MASK 0x7C00 +#define RTL8367C_VLAN_PPB3_CTRL4_PORT9_INDEX_OFFSET 5 +#define RTL8367C_VLAN_PPB3_CTRL4_PORT9_INDEX_MASK 0x3E0 +#define RTL8367C_VLAN_PPB3_CTRL4_PORT8_INDEX_OFFSET 0 +#define RTL8367C_VLAN_PPB3_CTRL4_PORT8_INDEX_MASK 0x1F + +#define RTL8367C_REG_VLAN_PPB3_CTRL3 0x0727 + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION0_CTRL0 0x0728 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION0_CTRL0_MBR_EXT_OFFSET 8 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION0_CTRL0_MBR_EXT_MASK 0x700 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION0_CTRL0_MBR_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION0_CTRL0_MBR_MASK 0xFF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION0_CTRL1 0x0729 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION0_CTRL1_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION0_CTRL1_MASK 0xF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION0_CTRL2 0x072a +#define RTL8367C_VLAN_MEMBER_CONFIGURATION0_CTRL2_METERIDX_EXT_OFFSET 10 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION0_CTRL2_METERIDX_EXT_MASK 0x400 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION0_CTRL2_METERIDX_OFFSET 5 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION0_CTRL2_METERIDX_MASK 0x3E0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION0_CTRL2_ENVLANPOL_OFFSET 4 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION0_CTRL2_ENVLANPOL_MASK 0x10 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION0_CTRL2_VBPRI_OFFSET 1 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION0_CTRL2_VBPRI_MASK 0xE +#define RTL8367C_VLAN_MEMBER_CONFIGURATION0_CTRL2_VBPEN_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION0_CTRL2_VBPEN_MASK 0x1 + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION0_CTRL3 0x072b +#define RTL8367C_VLAN_MEMBER_CONFIGURATION0_CTRL3_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION0_CTRL3_MASK 0x1FFF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION1_CTRL0 0x072c +#define RTL8367C_VLAN_MEMBER_CONFIGURATION1_CTRL0_MBR_EXT_OFFSET 8 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION1_CTRL0_MBR_EXT_MASK 0x700 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION1_CTRL0_MBR_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION1_CTRL0_MBR_MASK 0xFF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION1_CTRL1 0x072d +#define RTL8367C_VLAN_MEMBER_CONFIGURATION1_CTRL1_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION1_CTRL1_MASK 0xF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION1_CTRL2 0x072e +#define RTL8367C_VLAN_MEMBER_CONFIGURATION1_CTRL2_METERIDX_EXT_OFFSET 10 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION1_CTRL2_METERIDX_EXT_MASK 0x400 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION1_CTRL2_METERIDX_OFFSET 5 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION1_CTRL2_METERIDX_MASK 0x3E0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION1_CTRL2_ENVLANPOL_OFFSET 4 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION1_CTRL2_ENVLANPOL_MASK 0x10 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION1_CTRL2_VBPRI_OFFSET 1 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION1_CTRL2_VBPRI_MASK 0xE +#define RTL8367C_VLAN_MEMBER_CONFIGURATION1_CTRL2_VBPEN_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION1_CTRL2_VBPEN_MASK 0x1 + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION1_CTRL3 0x072f +#define RTL8367C_VLAN_MEMBER_CONFIGURATION1_CTRL3_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION1_CTRL3_MASK 0x1FFF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION2_CTRL0 0x0730 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION2_CTRL0_MBR_EXT_OFFSET 8 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION2_CTRL0_MBR_EXT_MASK 0x700 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION2_CTRL0_MBR_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION2_CTRL0_MBR_MASK 0xFF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION2_CTRL1 0x0731 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION2_CTRL1_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION2_CTRL1_MASK 0xF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION2_CTRL2 0x0732 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION2_CTRL2_METERIDX_EXT_OFFSET 10 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION2_CTRL2_METERIDX_EXT_MASK 0x400 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION2_CTRL2_METERIDX_OFFSET 5 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION2_CTRL2_METERIDX_MASK 0x3E0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION2_CTRL2_ENVLANPOL_OFFSET 4 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION2_CTRL2_ENVLANPOL_MASK 0x10 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION2_CTRL2_VBPRI_OFFSET 1 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION2_CTRL2_VBPRI_MASK 0xE +#define RTL8367C_VLAN_MEMBER_CONFIGURATION2_CTRL2_VBPEN_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION2_CTRL2_VBPEN_MASK 0x1 + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION2_CTRL3 0x0733 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION2_CTRL3_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION2_CTRL3_MASK 0x1FFF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION3_CTRL0 0x0734 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION3_CTRL0_MBR_EXT_OFFSET 8 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION3_CTRL0_MBR_EXT_MASK 0x700 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION3_CTRL0_MBR_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION3_CTRL0_MBR_MASK 0xFF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION3_CTRL1 0x0735 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION3_CTRL1_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION3_CTRL1_MASK 0xF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION3_CTRL2 0x0736 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION3_CTRL2_METERIDX_EXT_OFFSET 10 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION3_CTRL2_METERIDX_EXT_MASK 0x400 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION3_CTRL2_METERIDX_OFFSET 5 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION3_CTRL2_METERIDX_MASK 0x3E0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION3_CTRL2_ENVLANPOL_OFFSET 4 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION3_CTRL2_ENVLANPOL_MASK 0x10 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION3_CTRL2_VBPRI_OFFSET 1 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION3_CTRL2_VBPRI_MASK 0xE +#define RTL8367C_VLAN_MEMBER_CONFIGURATION3_CTRL2_VBPEN_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION3_CTRL2_VBPEN_MASK 0x1 + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION3_CTRL3 0x0737 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION3_CTRL3_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION3_CTRL3_MASK 0x1FFF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION4_CTRL0 0x0738 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION4_CTRL0_MBR_EXT_OFFSET 8 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION4_CTRL0_MBR_EXT_MASK 0x700 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION4_CTRL0_MBR_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION4_CTRL0_MBR_MASK 0xFF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION4_CTRL1 0x0739 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION4_CTRL1_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION4_CTRL1_MASK 0xF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION4_CTRL2 0x073a +#define RTL8367C_VLAN_MEMBER_CONFIGURATION4_CTRL2_METERIDX_EXT_OFFSET 10 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION4_CTRL2_METERIDX_EXT_MASK 0x400 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION4_CTRL2_METERIDX_OFFSET 5 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION4_CTRL2_METERIDX_MASK 0x3E0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION4_CTRL2_ENVLANPOL_OFFSET 4 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION4_CTRL2_ENVLANPOL_MASK 0x10 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION4_CTRL2_VBPRI_OFFSET 1 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION4_CTRL2_VBPRI_MASK 0xE +#define RTL8367C_VLAN_MEMBER_CONFIGURATION4_CTRL2_VBPEN_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION4_CTRL2_VBPEN_MASK 0x1 + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION4_CTRL3 0x073b +#define RTL8367C_VLAN_MEMBER_CONFIGURATION4_CTRL3_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION4_CTRL3_MASK 0x1FFF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION5_CTRL0 0x073c +#define RTL8367C_VLAN_MEMBER_CONFIGURATION5_CTRL0_MBR_EXT_OFFSET 8 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION5_CTRL0_MBR_EXT_MASK 0x700 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION5_CTRL0_MBR_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION5_CTRL0_MBR_MASK 0xFF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION5_CTRL1 0x073d +#define RTL8367C_VLAN_MEMBER_CONFIGURATION5_CTRL1_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION5_CTRL1_MASK 0xF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION5_CTRL2 0x073e +#define RTL8367C_VLAN_MEMBER_CONFIGURATION5_CTRL2_METERIDX_EXT_OFFSET 10 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION5_CTRL2_METERIDX_EXT_MASK 0x400 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION5_CTRL2_METERIDX_OFFSET 5 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION5_CTRL2_METERIDX_MASK 0x3E0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION5_CTRL2_ENVLANPOL_OFFSET 4 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION5_CTRL2_ENVLANPOL_MASK 0x10 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION5_CTRL2_VBPRI_OFFSET 1 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION5_CTRL2_VBPRI_MASK 0xE +#define RTL8367C_VLAN_MEMBER_CONFIGURATION5_CTRL2_VBPEN_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION5_CTRL2_VBPEN_MASK 0x1 + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION5_CTRL3 0x073f +#define RTL8367C_VLAN_MEMBER_CONFIGURATION5_CTRL3_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION5_CTRL3_MASK 0x1FFF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION6_CTRL0 0x0740 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION6_CTRL0_MBR_EXT_OFFSET 8 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION6_CTRL0_MBR_EXT_MASK 0x700 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION6_CTRL0_MBR_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION6_CTRL0_MBR_MASK 0xFF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION6_CTRL1 0x0741 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION6_CTRL1_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION6_CTRL1_MASK 0xF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION6_CTRL2 0x0742 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION6_CTRL2_METERIDX_EXT_OFFSET 10 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION6_CTRL2_METERIDX_EXT_MASK 0x400 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION6_CTRL2_METERIDX_OFFSET 5 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION6_CTRL2_METERIDX_MASK 0x3E0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION6_CTRL2_ENVLANPOL_OFFSET 4 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION6_CTRL2_ENVLANPOL_MASK 0x10 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION6_CTRL2_VBPRI_OFFSET 1 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION6_CTRL2_VBPRI_MASK 0xE +#define RTL8367C_VLAN_MEMBER_CONFIGURATION6_CTRL2_VBPEN_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION6_CTRL2_VBPEN_MASK 0x1 + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION6_CTRL3 0x0743 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION6_CTRL3_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION6_CTRL3_MASK 0x1FFF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION7_CTRL0 0x0744 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION7_CTRL0_MBR_EXT_OFFSET 8 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION7_CTRL0_MBR_EXT_MASK 0x700 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION7_CTRL0_MBR_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION7_CTRL0_MBR_MASK 0xFF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION7_CTRL1 0x0745 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION7_CTRL1_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION7_CTRL1_MASK 0xF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION7_CTRL2 0x0746 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION7_CTRL2_METERIDX_EXT_OFFSET 10 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION7_CTRL2_METERIDX_EXT_MASK 0x400 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION7_CTRL2_METERIDX_OFFSET 5 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION7_CTRL2_METERIDX_MASK 0x3E0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION7_CTRL2_ENVLANPOL_OFFSET 4 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION7_CTRL2_ENVLANPOL_MASK 0x10 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION7_CTRL2_VBPRI_OFFSET 1 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION7_CTRL2_VBPRI_MASK 0xE +#define RTL8367C_VLAN_MEMBER_CONFIGURATION7_CTRL2_VBPEN_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION7_CTRL2_VBPEN_MASK 0x1 + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION7_CTRL3 0x0747 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION7_CTRL3_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION7_CTRL3_MASK 0x1FFF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION8_CTRL0 0x0748 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION8_CTRL0_MBR_EXT_OFFSET 8 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION8_CTRL0_MBR_EXT_MASK 0x700 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION8_CTRL0_MBR_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION8_CTRL0_MBR_MASK 0xFF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION8_CTRL1 0x0749 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION8_CTRL1_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION8_CTRL1_MASK 0xF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION8_CTRL2 0x074a +#define RTL8367C_VLAN_MEMBER_CONFIGURATION8_CTRL2_METERIDX_EXT_OFFSET 10 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION8_CTRL2_METERIDX_EXT_MASK 0x400 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION8_CTRL2_METERIDX_OFFSET 5 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION8_CTRL2_METERIDX_MASK 0x3E0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION8_CTRL2_ENVLANPOL_OFFSET 4 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION8_CTRL2_ENVLANPOL_MASK 0x10 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION8_CTRL2_VBPRI_OFFSET 1 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION8_CTRL2_VBPRI_MASK 0xE +#define RTL8367C_VLAN_MEMBER_CONFIGURATION8_CTRL2_VBPEN_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION8_CTRL2_VBPEN_MASK 0x1 + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION8_CTRL3 0x074b +#define RTL8367C_VLAN_MEMBER_CONFIGURATION8_CTRL3_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION8_CTRL3_MASK 0x1FFF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION9_CTRL0 0x074c +#define RTL8367C_VLAN_MEMBER_CONFIGURATION9_CTRL0_MBR_EXT_OFFSET 8 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION9_CTRL0_MBR_EXT_MASK 0x700 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION9_CTRL0_MBR_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION9_CTRL0_MBR_MASK 0xFF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION9_CTRL1 0x074d +#define RTL8367C_VLAN_MEMBER_CONFIGURATION9_CTRL1_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION9_CTRL1_MASK 0xF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION9_CTRL2 0x074e +#define RTL8367C_VLAN_MEMBER_CONFIGURATION9_CTRL2_METERIDX_EXT_OFFSET 10 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION9_CTRL2_METERIDX_EXT_MASK 0x400 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION9_CTRL2_METERIDX_OFFSET 5 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION9_CTRL2_METERIDX_MASK 0x3E0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION9_CTRL2_ENVLANPOL_OFFSET 4 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION9_CTRL2_ENVLANPOL_MASK 0x10 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION9_CTRL2_VBPRI_OFFSET 1 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION9_CTRL2_VBPRI_MASK 0xE +#define RTL8367C_VLAN_MEMBER_CONFIGURATION9_CTRL2_VBPEN_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION9_CTRL2_VBPEN_MASK 0x1 + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION9_CTRL3 0x074f +#define RTL8367C_VLAN_MEMBER_CONFIGURATION9_CTRL3_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION9_CTRL3_MASK 0x1FFF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION10_CTRL0 0x0750 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION10_CTRL0_MBR_EXT_OFFSET 8 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION10_CTRL0_MBR_EXT_MASK 0x700 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION10_CTRL0_MBR_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION10_CTRL0_MBR_MASK 0xFF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION10_CTRL1 0x0751 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION10_CTRL1_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION10_CTRL1_MASK 0xF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION10_CTRL2 0x0752 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION10_CTRL2_METERIDX_EXT_OFFSET 10 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION10_CTRL2_METERIDX_EXT_MASK 0x400 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION10_CTRL2_METERIDX_OFFSET 5 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION10_CTRL2_METERIDX_MASK 0x3E0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION10_CTRL2_ENVLANPOL_OFFSET 4 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION10_CTRL2_ENVLANPOL_MASK 0x10 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION10_CTRL2_VBPRI_OFFSET 1 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION10_CTRL2_VBPRI_MASK 0xE +#define RTL8367C_VLAN_MEMBER_CONFIGURATION10_CTRL2_VBPEN_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION10_CTRL2_VBPEN_MASK 0x1 + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION10_CTRL3 0x0753 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION10_CTRL3_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION10_CTRL3_MASK 0x1FFF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION11_CTRL0 0x0754 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION11_CTRL0_MBR_EXT_OFFSET 8 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION11_CTRL0_MBR_EXT_MASK 0x700 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION11_CTRL0_MBR_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION11_CTRL0_MBR_MASK 0xFF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION11_CTRL1 0x0755 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION11_CTRL1_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION11_CTRL1_MASK 0xF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION11_CTRL2 0x0756 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION11_CTRL2_METERIDX_EXT_OFFSET 10 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION11_CTRL2_METERIDX_EXT_MASK 0x400 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION11_CTRL2_METERIDX_OFFSET 5 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION11_CTRL2_METERIDX_MASK 0x3E0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION11_CTRL2_ENVLANPOL_OFFSET 4 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION11_CTRL2_ENVLANPOL_MASK 0x10 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION11_CTRL2_VBPRI_OFFSET 1 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION11_CTRL2_VBPRI_MASK 0xE +#define RTL8367C_VLAN_MEMBER_CONFIGURATION11_CTRL2_VBPEN_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION11_CTRL2_VBPEN_MASK 0x1 + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION11_CTRL3 0x0757 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION11_CTRL3_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION11_CTRL3_MASK 0x1FFF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION12_CTRL0 0x0758 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION12_CTRL0_MBR_EXT_OFFSET 8 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION12_CTRL0_MBR_EXT_MASK 0x700 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION12_CTRL0_MBR_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION12_CTRL0_MBR_MASK 0xFF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION12_CTRL1 0x0759 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION12_CTRL1_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION12_CTRL1_MASK 0xF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION12_CTRL2 0x075a +#define RTL8367C_VLAN_MEMBER_CONFIGURATION12_CTRL2_METERIDX_EXT_OFFSET 10 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION12_CTRL2_METERIDX_EXT_MASK 0x400 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION12_CTRL2_METERIDX_OFFSET 5 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION12_CTRL2_METERIDX_MASK 0x3E0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION12_CTRL2_ENVLANPOL_OFFSET 4 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION12_CTRL2_ENVLANPOL_MASK 0x10 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION12_CTRL2_VBPRI_OFFSET 1 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION12_CTRL2_VBPRI_MASK 0xE +#define RTL8367C_VLAN_MEMBER_CONFIGURATION12_CTRL2_VBPEN_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION12_CTRL2_VBPEN_MASK 0x1 + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION12_CTRL3 0x075b +#define RTL8367C_VLAN_MEMBER_CONFIGURATION12_CTRL3_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION12_CTRL3_MASK 0x1FFF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION13_CTRL0 0x075c +#define RTL8367C_VLAN_MEMBER_CONFIGURATION13_CTRL0_MBR_EXT_OFFSET 8 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION13_CTRL0_MBR_EXT_MASK 0x700 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION13_CTRL0_MBR_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION13_CTRL0_MBR_MASK 0xFF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION13_CTRL1 0x075d +#define RTL8367C_VLAN_MEMBER_CONFIGURATION13_CTRL1_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION13_CTRL1_MASK 0xF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION13_CTRL2 0x075e +#define RTL8367C_VLAN_MEMBER_CONFIGURATION13_CTRL2_METERIDX_EXT_OFFSET 10 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION13_CTRL2_METERIDX_EXT_MASK 0x400 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION13_CTRL2_METERIDX_OFFSET 5 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION13_CTRL2_METERIDX_MASK 0x3E0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION13_CTRL2_ENVLANPOL_OFFSET 4 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION13_CTRL2_ENVLANPOL_MASK 0x10 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION13_CTRL2_VBPRI_OFFSET 1 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION13_CTRL2_VBPRI_MASK 0xE +#define RTL8367C_VLAN_MEMBER_CONFIGURATION13_CTRL2_VBPEN_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION13_CTRL2_VBPEN_MASK 0x1 + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION13_CTRL3 0x075f +#define RTL8367C_VLAN_MEMBER_CONFIGURATION13_CTRL3_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION13_CTRL3_MASK 0x1FFF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION14_CTRL0 0x0760 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION14_CTRL0_MBR_EXT_OFFSET 8 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION14_CTRL0_MBR_EXT_MASK 0x700 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION14_CTRL0_MBR_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION14_CTRL0_MBR_MASK 0xFF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION14_CTRL1 0x0761 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION14_CTRL1_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION14_CTRL1_MASK 0xF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION14_CTRL2 0x0762 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION14_CTRL2_METERIDX_EXT_OFFSET 10 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION14_CTRL2_METERIDX_EXT_MASK 0x400 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION14_CTRL2_METERIDX_OFFSET 5 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION14_CTRL2_METERIDX_MASK 0x3E0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION14_CTRL2_ENVLANPOL_OFFSET 4 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION14_CTRL2_ENVLANPOL_MASK 0x10 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION14_CTRL2_VBPRI_OFFSET 1 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION14_CTRL2_VBPRI_MASK 0xE +#define RTL8367C_VLAN_MEMBER_CONFIGURATION14_CTRL2_VBPEN_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION14_CTRL2_VBPEN_MASK 0x1 + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION14_CTRL3 0x0763 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION14_CTRL3_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION14_CTRL3_MASK 0x1FFF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION15_CTRL0 0x0764 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION15_CTRL0_MBR_EXT_OFFSET 8 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION15_CTRL0_MBR_EXT_MASK 0x700 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION15_CTRL0_MBR_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION15_CTRL0_MBR_MASK 0xFF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION15_CTRL1 0x0765 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION15_CTRL1_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION15_CTRL1_MASK 0xF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION15_CTRL2 0x0766 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION15_CTRL2_METERIDX_EXT_OFFSET 10 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION15_CTRL2_METERIDX_EXT_MASK 0x400 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION15_CTRL2_METERIDX_OFFSET 5 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION15_CTRL2_METERIDX_MASK 0x3E0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION15_CTRL2_ENVLANPOL_OFFSET 4 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION15_CTRL2_ENVLANPOL_MASK 0x10 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION15_CTRL2_VBPRI_OFFSET 1 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION15_CTRL2_VBPRI_MASK 0xE +#define RTL8367C_VLAN_MEMBER_CONFIGURATION15_CTRL2_VBPEN_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION15_CTRL2_VBPEN_MASK 0x1 + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION15_CTRL3 0x0767 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION15_CTRL3_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION15_CTRL3_MASK 0x1FFF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION16_CTRL0 0x0768 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION16_CTRL0_MBR_EXT_OFFSET 8 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION16_CTRL0_MBR_EXT_MASK 0x700 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION16_CTRL0_MBR_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION16_CTRL0_MBR_MASK 0xFF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION16_CTRL1 0x0769 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION16_CTRL1_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION16_CTRL1_MASK 0xF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION16_CTRL2 0x076a +#define RTL8367C_VLAN_MEMBER_CONFIGURATION16_CTRL2_METERIDX_EXT_OFFSET 10 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION16_CTRL2_METERIDX_EXT_MASK 0x400 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION16_CTRL2_METERIDX_OFFSET 5 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION16_CTRL2_METERIDX_MASK 0x3E0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION16_CTRL2_ENVLANPOL_OFFSET 4 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION16_CTRL2_ENVLANPOL_MASK 0x10 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION16_CTRL2_VBPRI_OFFSET 1 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION16_CTRL2_VBPRI_MASK 0xE +#define RTL8367C_VLAN_MEMBER_CONFIGURATION16_CTRL2_VBPEN_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION16_CTRL2_VBPEN_MASK 0x1 + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION16_CTRL3 0x076b +#define RTL8367C_VLAN_MEMBER_CONFIGURATION16_CTRL3_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION16_CTRL3_MASK 0x1FFF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION17_CTRL0 0x076c +#define RTL8367C_VLAN_MEMBER_CONFIGURATION17_CTRL0_MBR_EXT_OFFSET 8 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION17_CTRL0_MBR_EXT_MASK 0x700 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION17_CTRL0_MBR_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION17_CTRL0_MBR_MASK 0xFF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION17_CTRL1 0x076d +#define RTL8367C_VLAN_MEMBER_CONFIGURATION17_CTRL1_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION17_CTRL1_MASK 0xF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION17_CTRL2 0x076e +#define RTL8367C_VLAN_MEMBER_CONFIGURATION17_CTRL2_METERIDX_EXT_OFFSET 10 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION17_CTRL2_METERIDX_EXT_MASK 0x400 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION17_CTRL2_METERIDX_OFFSET 5 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION17_CTRL2_METERIDX_MASK 0x3E0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION17_CTRL2_ENVLANPOL_OFFSET 4 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION17_CTRL2_ENVLANPOL_MASK 0x10 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION17_CTRL2_VBPRI_OFFSET 1 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION17_CTRL2_VBPRI_MASK 0xE +#define RTL8367C_VLAN_MEMBER_CONFIGURATION17_CTRL2_VBPEN_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION17_CTRL2_VBPEN_MASK 0x1 + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION17_CTRL3 0x076f +#define RTL8367C_VLAN_MEMBER_CONFIGURATION17_CTRL3_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION17_CTRL3_MASK 0x1FFF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION18_CTRL0 0x0770 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION18_CTRL0_MBR_EXT_OFFSET 8 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION18_CTRL0_MBR_EXT_MASK 0x700 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION18_CTRL0_MBR_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION18_CTRL0_MBR_MASK 0xFF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION18_CTRL1 0x0771 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION18_CTRL1_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION18_CTRL1_MASK 0xF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION18_CTRL2 0x0772 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION18_CTRL2_METERIDX_EXT_OFFSET 10 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION18_CTRL2_METERIDX_EXT_MASK 0x400 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION18_CTRL2_METERIDX_OFFSET 5 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION18_CTRL2_METERIDX_MASK 0x3E0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION18_CTRL2_ENVLANPOL_OFFSET 4 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION18_CTRL2_ENVLANPOL_MASK 0x10 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION18_CTRL2_VBPRI_OFFSET 1 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION18_CTRL2_VBPRI_MASK 0xE +#define RTL8367C_VLAN_MEMBER_CONFIGURATION18_CTRL2_VBPEN_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION18_CTRL2_VBPEN_MASK 0x1 + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION18_CTRL3 0x0773 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION18_CTRL3_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION18_CTRL3_MASK 0x1FFF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION19_CTRL0 0x0774 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION19_CTRL0_MBR_EXT_OFFSET 8 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION19_CTRL0_MBR_EXT_MASK 0x700 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION19_CTRL0_MBR_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION19_CTRL0_MBR_MASK 0xFF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION19_CTRL1 0x0775 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION19_CTRL1_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION19_CTRL1_MASK 0xF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION19_CTRL2 0x0776 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION19_CTRL2_METERIDX_EXT_OFFSET 10 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION19_CTRL2_METERIDX_EXT_MASK 0x400 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION19_CTRL2_METERIDX_OFFSET 5 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION19_CTRL2_METERIDX_MASK 0x3E0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION19_CTRL2_ENVLANPOL_OFFSET 4 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION19_CTRL2_ENVLANPOL_MASK 0x10 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION19_CTRL2_VBPRI_OFFSET 1 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION19_CTRL2_VBPRI_MASK 0xE +#define RTL8367C_VLAN_MEMBER_CONFIGURATION19_CTRL2_VBPEN_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION19_CTRL2_VBPEN_MASK 0x1 + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION19_CTRL3 0x0777 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION19_CTRL3_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION19_CTRL3_MASK 0x1FFF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION20_CTRL0 0x0778 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION20_CTRL0_MBR_EXT_OFFSET 8 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION20_CTRL0_MBR_EXT_MASK 0x700 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION20_CTRL0_MBR_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION20_CTRL0_MBR_MASK 0xFF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION20_CTRL1 0x0779 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION20_CTRL1_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION20_CTRL1_MASK 0xF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION20_CTRL2 0x077a +#define RTL8367C_VLAN_MEMBER_CONFIGURATION20_CTRL2_METERIDX_EXT_OFFSET 10 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION20_CTRL2_METERIDX_EXT_MASK 0x400 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION20_CTRL2_METERIDX_OFFSET 5 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION20_CTRL2_METERIDX_MASK 0x3E0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION20_CTRL2_ENVLANPOL_OFFSET 4 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION20_CTRL2_ENVLANPOL_MASK 0x10 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION20_CTRL2_VBPRI_OFFSET 1 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION20_CTRL2_VBPRI_MASK 0xE +#define RTL8367C_VLAN_MEMBER_CONFIGURATION20_CTRL2_VBPEN_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION20_CTRL2_VBPEN_MASK 0x1 + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION20_CTRL3 0x077b +#define RTL8367C_VLAN_MEMBER_CONFIGURATION20_CTRL3_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION20_CTRL3_MASK 0x1FFF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION21_CTRL0 0x077c +#define RTL8367C_VLAN_MEMBER_CONFIGURATION21_CTRL0_MBR_EXT_OFFSET 8 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION21_CTRL0_MBR_EXT_MASK 0x700 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION21_CTRL0_MBR_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION21_CTRL0_MBR_MASK 0xFF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION21_CTRL1 0x077d +#define RTL8367C_VLAN_MEMBER_CONFIGURATION21_CTRL1_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION21_CTRL1_MASK 0xF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION21_CTRL2 0x077e +#define RTL8367C_VLAN_MEMBER_CONFIGURATION21_CTRL2_METERIDX_EXT_OFFSET 10 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION21_CTRL2_METERIDX_EXT_MASK 0x400 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION21_CTRL2_METERIDX_OFFSET 5 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION21_CTRL2_METERIDX_MASK 0x3E0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION21_CTRL2_ENVLANPOL_OFFSET 4 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION21_CTRL2_ENVLANPOL_MASK 0x10 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION21_CTRL2_VBPRI_OFFSET 1 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION21_CTRL2_VBPRI_MASK 0xE +#define RTL8367C_VLAN_MEMBER_CONFIGURATION21_CTRL2_VBPEN_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION21_CTRL2_VBPEN_MASK 0x1 + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION21_CTRL3 0x077f +#define RTL8367C_VLAN_MEMBER_CONFIGURATION21_CTRL3_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION21_CTRL3_MASK 0x1FFF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION22_CTRL0 0x0780 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION22_CTRL0_MBR_EXT_OFFSET 8 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION22_CTRL0_MBR_EXT_MASK 0x700 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION22_CTRL0_MBR_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION22_CTRL0_MBR_MASK 0xFF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION22_CTRL1 0x0781 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION22_CTRL1_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION22_CTRL1_MASK 0xF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION22_CTRL2 0x0782 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION22_CTRL2_METERIDX_EXT_OFFSET 10 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION22_CTRL2_METERIDX_EXT_MASK 0x400 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION22_CTRL2_METERIDX_OFFSET 5 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION22_CTRL2_METERIDX_MASK 0x3E0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION22_CTRL2_ENVLANPOL_OFFSET 4 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION22_CTRL2_ENVLANPOL_MASK 0x10 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION22_CTRL2_VBPRI_OFFSET 1 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION22_CTRL2_VBPRI_MASK 0xE +#define RTL8367C_VLAN_MEMBER_CONFIGURATION22_CTRL2_VBPEN_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION22_CTRL2_VBPEN_MASK 0x1 + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION22_CTRL3 0x0783 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION22_CTRL3_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION22_CTRL3_MASK 0x1FFF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION23_CTRL0 0x0784 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION23_CTRL0_MBR_EXT_OFFSET 8 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION23_CTRL0_MBR_EXT_MASK 0x700 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION23_CTRL0_MBR_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION23_CTRL0_MBR_MASK 0xFF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION23_CTRL1 0x0785 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION23_CTRL1_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION23_CTRL1_MASK 0xF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION23_CTRL2 0x0786 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION23_CTRL2_METERIDX_EXT_OFFSET 10 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION23_CTRL2_METERIDX_EXT_MASK 0x400 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION23_CTRL2_METERIDX_OFFSET 5 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION23_CTRL2_METERIDX_MASK 0x3E0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION23_CTRL2_ENVLANPOL_OFFSET 4 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION23_CTRL2_ENVLANPOL_MASK 0x10 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION23_CTRL2_VBPRI_OFFSET 1 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION23_CTRL2_VBPRI_MASK 0xE +#define RTL8367C_VLAN_MEMBER_CONFIGURATION23_CTRL2_VBPEN_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION23_CTRL2_VBPEN_MASK 0x1 + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION23_CTRL3 0x0787 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION23_CTRL3_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION23_CTRL3_MASK 0x1FFF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION24_CTRL0 0x0788 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION24_CTRL0_MBR_EXT_OFFSET 8 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION24_CTRL0_MBR_EXT_MASK 0x700 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION24_CTRL0_MBR_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION24_CTRL0_MBR_MASK 0xFF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION24_CTRL1 0x0789 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION24_CTRL1_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION24_CTRL1_MASK 0xF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION24_CTRL2 0x078a +#define RTL8367C_VLAN_MEMBER_CONFIGURATION24_CTRL2_METERIDX_EXT_OFFSET 10 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION24_CTRL2_METERIDX_EXT_MASK 0x400 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION24_CTRL2_METERIDX_OFFSET 5 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION24_CTRL2_METERIDX_MASK 0x3E0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION24_CTRL2_ENVLANPOL_OFFSET 4 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION24_CTRL2_ENVLANPOL_MASK 0x10 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION24_CTRL2_VBPRI_OFFSET 1 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION24_CTRL2_VBPRI_MASK 0xE +#define RTL8367C_VLAN_MEMBER_CONFIGURATION24_CTRL2_VBPEN_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION24_CTRL2_VBPEN_MASK 0x1 + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION24_CTRL3 0x078b +#define RTL8367C_VLAN_MEMBER_CONFIGURATION24_CTRL3_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION24_CTRL3_MASK 0x1FFF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION25_CTRL0 0x078c +#define RTL8367C_VLAN_MEMBER_CONFIGURATION25_CTRL0_MBR_EXT_OFFSET 8 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION25_CTRL0_MBR_EXT_MASK 0x700 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION25_CTRL0_MBR_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION25_CTRL0_MBR_MASK 0xFF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION25_CTRL1 0x078d +#define RTL8367C_VLAN_MEMBER_CONFIGURATION25_CTRL1_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION25_CTRL1_MASK 0xF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION25_CTRL2 0x078e +#define RTL8367C_VLAN_MEMBER_CONFIGURATION25_CTRL2_METERIDX_EXT_OFFSET 10 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION25_CTRL2_METERIDX_EXT_MASK 0x400 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION25_CTRL2_METERIDX_OFFSET 5 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION25_CTRL2_METERIDX_MASK 0x3E0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION25_CTRL2_ENVLANPOL_OFFSET 4 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION25_CTRL2_ENVLANPOL_MASK 0x10 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION25_CTRL2_VBPRI_OFFSET 1 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION25_CTRL2_VBPRI_MASK 0xE +#define RTL8367C_VLAN_MEMBER_CONFIGURATION25_CTRL2_VBPEN_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION25_CTRL2_VBPEN_MASK 0x1 + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION25_CTRL3 0x078f +#define RTL8367C_VLAN_MEMBER_CONFIGURATION25_CTRL3_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION25_CTRL3_MASK 0x1FFF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION26_CTRL0 0x0790 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION26_CTRL0_MBR_EXT_OFFSET 8 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION26_CTRL0_MBR_EXT_MASK 0x700 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION26_CTRL0_MBR_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION26_CTRL0_MBR_MASK 0xFF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION26_CTRL1 0x0791 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION26_CTRL1_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION26_CTRL1_MASK 0xF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION26_CTRL2 0x0792 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION26_CTRL2_METERIDX_EXT_OFFSET 10 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION26_CTRL2_METERIDX_EXT_MASK 0x400 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION26_CTRL2_METERIDX_OFFSET 5 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION26_CTRL2_METERIDX_MASK 0x3E0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION26_CTRL2_ENVLANPOL_OFFSET 4 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION26_CTRL2_ENVLANPOL_MASK 0x10 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION26_CTRL2_VBPRI_OFFSET 1 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION26_CTRL2_VBPRI_MASK 0xE +#define RTL8367C_VLAN_MEMBER_CONFIGURATION26_CTRL2_VBPEN_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION26_CTRL2_VBPEN_MASK 0x1 + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION26_CTRL3 0x0793 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION26_CTRL3_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION26_CTRL3_MASK 0x1FFF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION27_CTRL0 0x0794 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION27_CTRL0_MBR_EXT_OFFSET 8 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION27_CTRL0_MBR_EXT_MASK 0x700 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION27_CTRL0_MBR_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION27_CTRL0_MBR_MASK 0xFF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION27_CTRL1 0x0795 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION27_CTRL1_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION27_CTRL1_MASK 0xF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION27_CTRL2 0x0796 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION27_CTRL2_METERIDX_EXT_OFFSET 10 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION27_CTRL2_METERIDX_EXT_MASK 0x400 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION27_CTRL2_METERIDX_OFFSET 5 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION27_CTRL2_METERIDX_MASK 0x3E0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION27_CTRL2_ENVLANPOL_OFFSET 4 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION27_CTRL2_ENVLANPOL_MASK 0x10 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION27_CTRL2_VBPRI_OFFSET 1 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION27_CTRL2_VBPRI_MASK 0xE +#define RTL8367C_VLAN_MEMBER_CONFIGURATION27_CTRL2_VBPEN_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION27_CTRL2_VBPEN_MASK 0x1 + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION27_CTRL3 0x0797 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION27_CTRL3_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION27_CTRL3_MASK 0x1FFF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION28_CTRL0 0x0798 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION28_CTRL0_MBR_EXT_OFFSET 8 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION28_CTRL0_MBR_EXT_MASK 0x700 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION28_CTRL0_MBR_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION28_CTRL0_MBR_MASK 0xFF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION28_CTRL1 0x0799 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION28_CTRL1_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION28_CTRL1_MASK 0xF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION28_CTRL2 0x079a +#define RTL8367C_VLAN_MEMBER_CONFIGURATION28_CTRL2_METERIDX_EXT_OFFSET 10 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION28_CTRL2_METERIDX_EXT_MASK 0x400 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION28_CTRL2_METERIDX_OFFSET 5 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION28_CTRL2_METERIDX_MASK 0x3E0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION28_CTRL2_ENVLANPOL_OFFSET 4 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION28_CTRL2_ENVLANPOL_MASK 0x10 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION28_CTRL2_VBPRI_OFFSET 1 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION28_CTRL2_VBPRI_MASK 0xE +#define RTL8367C_VLAN_MEMBER_CONFIGURATION28_CTRL2_VBPEN_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION28_CTRL2_VBPEN_MASK 0x1 + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION28_CTRL3 0x079b +#define RTL8367C_VLAN_MEMBER_CONFIGURATION28_CTRL3_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION28_CTRL3_MASK 0x1FFF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION29_CTRL0 0x079c +#define RTL8367C_VLAN_MEMBER_CONFIGURATION29_CTRL0_MBR_EXT_OFFSET 8 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION29_CTRL0_MBR_EXT_MASK 0x700 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION29_CTRL0_MBR_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION29_CTRL0_MBR_MASK 0xFF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION29_CTRL1 0x079d +#define RTL8367C_VLAN_MEMBER_CONFIGURATION29_CTRL1_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION29_CTRL1_MASK 0xF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION29_CTRL2 0x079e +#define RTL8367C_VLAN_MEMBER_CONFIGURATION29_CTRL2_METERIDX_EXT_OFFSET 10 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION29_CTRL2_METERIDX_EXT_MASK 0x400 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION29_CTRL2_METERIDX_OFFSET 5 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION29_CTRL2_METERIDX_MASK 0x3E0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION29_CTRL2_ENVLANPOL_OFFSET 4 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION29_CTRL2_ENVLANPOL_MASK 0x10 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION29_CTRL2_VBPRI_OFFSET 1 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION29_CTRL2_VBPRI_MASK 0xE +#define RTL8367C_VLAN_MEMBER_CONFIGURATION29_CTRL2_VBPEN_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION29_CTRL2_VBPEN_MASK 0x1 + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION29_CTRL3 0x079f +#define RTL8367C_VLAN_MEMBER_CONFIGURATION29_CTRL3_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION29_CTRL3_MASK 0x1FFF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION30_CTRL0 0x07a0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION30_CTRL0_MBR_EXT_OFFSET 8 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION30_CTRL0_MBR_EXT_MASK 0x700 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION30_CTRL0_MBR_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION30_CTRL0_MBR_MASK 0xFF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION30_CTRL1 0x07a1 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION30_CTRL1_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION30_CTRL1_MASK 0xF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION30_CTRL2 0x07a2 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION30_CTRL2_METERIDX_EXT_OFFSET 10 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION30_CTRL2_METERIDX_EXT_MASK 0x400 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION30_CTRL2_METERIDX_OFFSET 5 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION30_CTRL2_METERIDX_MASK 0x3E0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION30_CTRL2_ENVLANPOL_OFFSET 4 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION30_CTRL2_ENVLANPOL_MASK 0x10 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION30_CTRL2_VBPRI_OFFSET 1 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION30_CTRL2_VBPRI_MASK 0xE +#define RTL8367C_VLAN_MEMBER_CONFIGURATION30_CTRL2_VBPEN_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION30_CTRL2_VBPEN_MASK 0x1 + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION30_CTRL3 0x07a3 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION30_CTRL3_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION30_CTRL3_MASK 0x1FFF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION31_CTRL0 0x07a4 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION31_CTRL0_MBR_EXT_OFFSET 8 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION31_CTRL0_MBR_EXT_MASK 0x700 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION31_CTRL0_MBR_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION31_CTRL0_MBR_MASK 0xFF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION31_CTRL1 0x07a5 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION31_CTRL1_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION31_CTRL1_MASK 0xF + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION31_CTRL2 0x07a6 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION31_CTRL2_METERIDX_EXT_OFFSET 10 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION31_CTRL2_METERIDX_EXT_MASK 0x400 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION31_CTRL2_METERIDX_OFFSET 5 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION31_CTRL2_METERIDX_MASK 0x3E0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION31_CTRL2_ENVLANPOL_OFFSET 4 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION31_CTRL2_ENVLANPOL_MASK 0x10 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION31_CTRL2_VBPRI_OFFSET 1 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION31_CTRL2_VBPRI_MASK 0xE +#define RTL8367C_VLAN_MEMBER_CONFIGURATION31_CTRL2_VBPEN_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION31_CTRL2_VBPEN_MASK 0x1 + +#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION31_CTRL3 0x07a7 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION31_CTRL3_OFFSET 0 +#define RTL8367C_VLAN_MEMBER_CONFIGURATION31_CTRL3_MASK 0x1FFF + +#define RTL8367C_REG_VLAN_CTRL 0x07a8 +#define RTL8367C_VLAN_CTRL_OFFSET 0 +#define RTL8367C_VLAN_CTRL_MASK 0x1 + +#define RTL8367C_REG_VLAN_INGRESS 0x07a9 +#define RTL8367C_VLAN_INGRESS_OFFSET 0 +#define RTL8367C_VLAN_INGRESS_MASK 0x7FF + +#define RTL8367C_REG_VLAN_ACCEPT_FRAME_TYPE_CTRL0 0x07aa +#define RTL8367C_PORT7_FRAME_TYPE_OFFSET 14 +#define RTL8367C_PORT7_FRAME_TYPE_MASK 0xC000 +#define RTL8367C_PORT6_FRAME_TYPE_OFFSET 12 +#define RTL8367C_PORT6_FRAME_TYPE_MASK 0x3000 +#define RTL8367C_PORT5_FRAME_TYPE_OFFSET 10 +#define RTL8367C_PORT5_FRAME_TYPE_MASK 0xC00 +#define RTL8367C_PORT4_FRAME_TYPE_OFFSET 8 +#define RTL8367C_PORT4_FRAME_TYPE_MASK 0x300 +#define RTL8367C_PORT3_FRAME_TYPE_OFFSET 6 +#define RTL8367C_PORT3_FRAME_TYPE_MASK 0xC0 +#define RTL8367C_PORT2_FRAME_TYPE_OFFSET 4 +#define RTL8367C_PORT2_FRAME_TYPE_MASK 0x30 +#define RTL8367C_PORT1_FRAME_TYPE_OFFSET 2 +#define RTL8367C_PORT1_FRAME_TYPE_MASK 0xC +#define RTL8367C_PORT0_FRAME_TYPE_OFFSET 0 +#define RTL8367C_PORT0_FRAME_TYPE_MASK 0x3 + +#define RTL8367C_REG_VLAN_ACCEPT_FRAME_TYPE_CTRL1 0x07ab +#define RTL8367C_PORT10_FRAME_TYPE_OFFSET 4 +#define RTL8367C_PORT10_FRAME_TYPE_MASK 0x30 +#define RTL8367C_PORT9_FRAME_TYPE_OFFSET 2 +#define RTL8367C_PORT9_FRAME_TYPE_MASK 0xC +#define RTL8367C_PORT8_FRAME_TYPE_OFFSET 0 +#define RTL8367C_PORT8_FRAME_TYPE_MASK 0x3 + +#define RTL8367C_REG_PORT_PBFIDEN 0x07ac +#define RTL8367C_PORT_PBFIDEN_OFFSET 0 +#define RTL8367C_PORT_PBFIDEN_MASK 0x7FF + +#define RTL8367C_REG_PORT0_PBFID 0x07ad +#define RTL8367C_PORT0_PBFID_OFFSET 0 +#define RTL8367C_PORT0_PBFID_MASK 0xF + +#define RTL8367C_REG_PORT1_PBFID 0x07ae +#define RTL8367C_PORT1_PBFID_OFFSET 0 +#define RTL8367C_PORT1_PBFID_MASK 0xF + +#define RTL8367C_REG_PORT2_PBFID 0x07af +#define RTL8367C_PORT2_PBFID_OFFSET 0 +#define RTL8367C_PORT2_PBFID_MASK 0xF + +#define RTL8367C_REG_PORT3_PBFID 0x07b0 +#define RTL8367C_PORT3_PBFID_OFFSET 0 +#define RTL8367C_PORT3_PBFID_MASK 0xF + +#define RTL8367C_REG_PORT4_PBFID 0x07b1 +#define RTL8367C_PORT4_PBFID_OFFSET 0 +#define RTL8367C_PORT4_PBFID_MASK 0xF + +#define RTL8367C_REG_PORT5_PBFID 0x07b2 +#define RTL8367C_PORT5_PBFID_OFFSET 0 +#define RTL8367C_PORT5_PBFID_MASK 0xF + +#define RTL8367C_REG_PORT6_PBFID 0x07b3 +#define RTL8367C_PORT6_PBFID_OFFSET 0 +#define RTL8367C_PORT6_PBFID_MASK 0xF + +#define RTL8367C_REG_PORT7_PBFID 0x07b4 +#define RTL8367C_PORT7_PBFID_OFFSET 0 +#define RTL8367C_PORT7_PBFID_MASK 0xF + +#define RTL8367C_REG_VLAN_EXT_CTRL 0x07b5 +#define RTL8367C_VLAN_1P_REMARK_BYPASS_REALKEEP_OFFSET 2 +#define RTL8367C_VLAN_1P_REMARK_BYPASS_REALKEEP_MASK 0x4 +#define RTL8367C_VLAN_VID4095_TYPE_OFFSET 1 +#define RTL8367C_VLAN_VID4095_TYPE_MASK 0x2 +#define RTL8367C_VLAN_VID0_TYPE_OFFSET 0 +#define RTL8367C_VLAN_VID0_TYPE_MASK 0x1 + +#define RTL8367C_REG_VLAN_EXT_CTRL2 0x07b6 +#define RTL8367C_VLAN_EXT_CTRL2_OFFSET 0 +#define RTL8367C_VLAN_EXT_CTRL2_MASK 0x1 + +#define RTL8367C_REG_PORT8_PBFID 0x07b7 +#define RTL8367C_PORT8_PBFID_OFFSET 0 +#define RTL8367C_PORT8_PBFID_MASK 0xF + +#define RTL8367C_REG_PORT9_PBFID 0x07b8 +#define RTL8367C_PORT9_PBFID_OFFSET 0 +#define RTL8367C_PORT9_PBFID_MASK 0xF + +#define RTL8367C_REG_PORT10_PBFID 0x07b9 +#define RTL8367C_PORT10_PBFID_OFFSET 0 +#define RTL8367C_PORT10_PBFID_MASK 0xF + +#define RTL8367C_REG_CVLAN_DUMMY00 0x07E0 + +#define RTL8367C_REG_CVLAN_DUMMY01 0x07E1 + +#define RTL8367C_REG_CVLAN_DUMMY02 0x07E2 + +#define RTL8367C_REG_CVLAN_DUMMY03 0x07E3 + +#define RTL8367C_REG_CVLAN_DUMMY04 0x07E4 + +#define RTL8367C_REG_CVLAN_DUMMY05 0x07E5 + +#define RTL8367C_REG_CVLAN_DUMMY06 0x07E6 + +#define RTL8367C_REG_CVLAN_DUMMY07 0x07E7 + +#define RTL8367C_REG_CVLAN_DUMMY08 0x07E8 + +#define RTL8367C_REG_CVLAN_DUMMY09 0x07E9 + +#define RTL8367C_REG_CVLAN_DUMMY10 0x07EA + +#define RTL8367C_REG_CVLAN_DUMMY11 0x07EB + +#define RTL8367C_REG_CVLAN_DUMMY12 0x07EC + +#define RTL8367C_REG_CVLAN_DUMMY13 0x07ED + +#define RTL8367C_REG_CVLAN_DUMMY14 0x07EE + +#define RTL8367C_REG_CVLAN_DUMMY15 0x07EF + +/* (16'h0800)dpm_reg */ + +#define RTL8367C_REG_RMA_CTRL00 0x0800 +#define RTL8367C_RMA_CTRL00_OPERATION_OFFSET 7 +#define RTL8367C_RMA_CTRL00_OPERATION_MASK 0x180 +#define RTL8367C_RMA_CTRL00_DISCARD_STORM_FILTER_OFFSET 6 +#define RTL8367C_RMA_CTRL00_DISCARD_STORM_FILTER_MASK 0x40 +#define RTL8367C_TRAP_PRIORITY_OFFSET 3 +#define RTL8367C_TRAP_PRIORITY_MASK 0x38 +#define RTL8367C_RMA_CTRL00_KEEP_FORMAT_OFFSET 2 +#define RTL8367C_RMA_CTRL00_KEEP_FORMAT_MASK 0x4 +#define RTL8367C_RMA_CTRL00_VLAN_LEAKY_OFFSET 1 +#define RTL8367C_RMA_CTRL00_VLAN_LEAKY_MASK 0x2 +#define RTL8367C_RMA_CTRL00_PORTISO_LEAKY_OFFSET 0 +#define RTL8367C_RMA_CTRL00_PORTISO_LEAKY_MASK 0x1 + +#define RTL8367C_REG_RMA_CTRL01 0x0801 +#define RTL8367C_RMA_CTRL01_OPERATION_OFFSET 7 +#define RTL8367C_RMA_CTRL01_OPERATION_MASK 0x180 +#define RTL8367C_RMA_CTRL01_DISCARD_STORM_FILTER_OFFSET 6 +#define RTL8367C_RMA_CTRL01_DISCARD_STORM_FILTER_MASK 0x40 +#define RTL8367C_RMA_CTRL01_KEEP_FORMAT_OFFSET 2 +#define RTL8367C_RMA_CTRL01_KEEP_FORMAT_MASK 0x4 +#define RTL8367C_RMA_CTRL01_VLAN_LEAKY_OFFSET 1 +#define RTL8367C_RMA_CTRL01_VLAN_LEAKY_MASK 0x2 +#define RTL8367C_RMA_CTRL01_PORTISO_LEAKY_OFFSET 0 +#define RTL8367C_RMA_CTRL01_PORTISO_LEAKY_MASK 0x1 + +#define RTL8367C_REG_RMA_CTRL02 0x0802 +#define RTL8367C_RMA_CTRL02_OPERATION_OFFSET 7 +#define RTL8367C_RMA_CTRL02_OPERATION_MASK 0x180 +#define RTL8367C_RMA_CTRL02_DISCARD_STORM_FILTER_OFFSET 6 +#define RTL8367C_RMA_CTRL02_DISCARD_STORM_FILTER_MASK 0x40 +#define RTL8367C_RMA_CTRL02_KEEP_FORMAT_OFFSET 2 +#define RTL8367C_RMA_CTRL02_KEEP_FORMAT_MASK 0x4 +#define RTL8367C_RMA_CTRL02_VLAN_LEAKY_OFFSET 1 +#define RTL8367C_RMA_CTRL02_VLAN_LEAKY_MASK 0x2 +#define RTL8367C_RMA_CTRL02_PORTISO_LEAKY_OFFSET 0 +#define RTL8367C_RMA_CTRL02_PORTISO_LEAKY_MASK 0x1 + +#define RTL8367C_REG_RMA_CTRL03 0x0803 +#define RTL8367C_RMA_CTRL03_OPERATION_OFFSET 7 +#define RTL8367C_RMA_CTRL03_OPERATION_MASK 0x180 +#define RTL8367C_RMA_CTRL03_DISCARD_STORM_FILTER_OFFSET 6 +#define RTL8367C_RMA_CTRL03_DISCARD_STORM_FILTER_MASK 0x40 +#define RTL8367C_RMA_CTRL03_KEEP_FORMAT_OFFSET 2 +#define RTL8367C_RMA_CTRL03_KEEP_FORMAT_MASK 0x4 +#define RTL8367C_RMA_CTRL03_VLAN_LEAKY_OFFSET 1 +#define RTL8367C_RMA_CTRL03_VLAN_LEAKY_MASK 0x2 +#define RTL8367C_RMA_CTRL03_PORTISO_LEAKY_OFFSET 0 +#define RTL8367C_RMA_CTRL03_PORTISO_LEAKY_MASK 0x1 + +#define RTL8367C_REG_RMA_CTRL04 0x0804 +#define RTL8367C_RMA_CTRL04_OPERATION_OFFSET 7 +#define RTL8367C_RMA_CTRL04_OPERATION_MASK 0x180 +#define RTL8367C_RMA_CTRL04_DISCARD_STORM_FILTER_OFFSET 6 +#define RTL8367C_RMA_CTRL04_DISCARD_STORM_FILTER_MASK 0x40 +#define RTL8367C_RMA_CTRL04_KEEP_FORMAT_OFFSET 2 +#define RTL8367C_RMA_CTRL04_KEEP_FORMAT_MASK 0x4 +#define RTL8367C_RMA_CTRL04_VLAN_LEAKY_OFFSET 1 +#define RTL8367C_RMA_CTRL04_VLAN_LEAKY_MASK 0x2 +#define RTL8367C_RMA_CTRL04_PORTISO_LEAKY_OFFSET 0 +#define RTL8367C_RMA_CTRL04_PORTISO_LEAKY_MASK 0x1 + +#define RTL8367C_REG_RMA_CTRL08 0x0808 +#define RTL8367C_RMA_CTRL08_OPERATION_OFFSET 7 +#define RTL8367C_RMA_CTRL08_OPERATION_MASK 0x180 +#define RTL8367C_RMA_CTRL08_DISCARD_STORM_FILTER_OFFSET 6 +#define RTL8367C_RMA_CTRL08_DISCARD_STORM_FILTER_MASK 0x40 +#define RTL8367C_RMA_CTRL08_KEEP_FORMAT_OFFSET 2 +#define RTL8367C_RMA_CTRL08_KEEP_FORMAT_MASK 0x4 +#define RTL8367C_RMA_CTRL08_VLAN_LEAKY_OFFSET 1 +#define RTL8367C_RMA_CTRL08_VLAN_LEAKY_MASK 0x2 +#define RTL8367C_RMA_CTRL08_PORTISO_LEAKY_OFFSET 0 +#define RTL8367C_RMA_CTRL08_PORTISO_LEAKY_MASK 0x1 + +#define RTL8367C_REG_RMA_CTRL0D 0x080d +#define RTL8367C_RMA_CTRL0D_OPERATION_OFFSET 7 +#define RTL8367C_RMA_CTRL0D_OPERATION_MASK 0x180 +#define RTL8367C_RMA_CTRL0D_DISCARD_STORM_FILTER_OFFSET 6 +#define RTL8367C_RMA_CTRL0D_DISCARD_STORM_FILTER_MASK 0x40 +#define RTL8367C_RMA_CTRL0D_KEEP_FORMAT_OFFSET 2 +#define RTL8367C_RMA_CTRL0D_KEEP_FORMAT_MASK 0x4 +#define RTL8367C_RMA_CTRL0D_VLAN_LEAKY_OFFSET 1 +#define RTL8367C_RMA_CTRL0D_VLAN_LEAKY_MASK 0x2 +#define RTL8367C_RMA_CTRL0D_PORTISO_LEAKY_OFFSET 0 +#define RTL8367C_RMA_CTRL0D_PORTISO_LEAKY_MASK 0x1 + +#define RTL8367C_REG_RMA_CTRL0E 0x080e +#define RTL8367C_RMA_CTRL0E_OPERATION_OFFSET 7 +#define RTL8367C_RMA_CTRL0E_OPERATION_MASK 0x180 +#define RTL8367C_RMA_CTRL0E_DISCARD_STORM_FILTER_OFFSET 6 +#define RTL8367C_RMA_CTRL0E_DISCARD_STORM_FILTER_MASK 0x40 +#define RTL8367C_RMA_CTRL0E_KEEP_FORMAT_OFFSET 2 +#define RTL8367C_RMA_CTRL0E_KEEP_FORMAT_MASK 0x4 +#define RTL8367C_RMA_CTRL0E_VLAN_LEAKY_OFFSET 1 +#define RTL8367C_RMA_CTRL0E_VLAN_LEAKY_MASK 0x2 +#define RTL8367C_RMA_CTRL0E_PORTISO_LEAKY_OFFSET 0 +#define RTL8367C_RMA_CTRL0E_PORTISO_LEAKY_MASK 0x1 + +#define RTL8367C_REG_RMA_CTRL10 0x0810 +#define RTL8367C_RMA_CTRL10_OPERATION_OFFSET 7 +#define RTL8367C_RMA_CTRL10_OPERATION_MASK 0x180 +#define RTL8367C_RMA_CTRL10_DISCARD_STORM_FILTER_OFFSET 6 +#define RTL8367C_RMA_CTRL10_DISCARD_STORM_FILTER_MASK 0x40 +#define RTL8367C_RMA_CTRL10_KEEP_FORMAT_OFFSET 2 +#define RTL8367C_RMA_CTRL10_KEEP_FORMAT_MASK 0x4 +#define RTL8367C_RMA_CTRL10_VLAN_LEAKY_OFFSET 1 +#define RTL8367C_RMA_CTRL10_VLAN_LEAKY_MASK 0x2 +#define RTL8367C_RMA_CTRL10_PORTISO_LEAKY_OFFSET 0 +#define RTL8367C_RMA_CTRL10_PORTISO_LEAKY_MASK 0x1 + +#define RTL8367C_REG_RMA_CTRL11 0x0811 +#define RTL8367C_RMA_CTRL11_OPERATION_OFFSET 7 +#define RTL8367C_RMA_CTRL11_OPERATION_MASK 0x180 +#define RTL8367C_RMA_CTRL11_DISCARD_STORM_FILTER_OFFSET 6 +#define RTL8367C_RMA_CTRL11_DISCARD_STORM_FILTER_MASK 0x40 +#define RTL8367C_RMA_CTRL11_KEEP_FORMAT_OFFSET 2 +#define RTL8367C_RMA_CTRL11_KEEP_FORMAT_MASK 0x4 +#define RTL8367C_RMA_CTRL11_VLAN_LEAKY_OFFSET 1 +#define RTL8367C_RMA_CTRL11_VLAN_LEAKY_MASK 0x2 +#define RTL8367C_RMA_CTRL11_PORTISO_LEAKY_OFFSET 0 +#define RTL8367C_RMA_CTRL11_PORTISO_LEAKY_MASK 0x1 + +#define RTL8367C_REG_RMA_CTRL12 0x0812 +#define RTL8367C_RMA_CTRL12_OPERATION_OFFSET 7 +#define RTL8367C_RMA_CTRL12_OPERATION_MASK 0x180 +#define RTL8367C_RMA_CTRL12_DISCARD_STORM_FILTER_OFFSET 6 +#define RTL8367C_RMA_CTRL12_DISCARD_STORM_FILTER_MASK 0x40 +#define RTL8367C_RMA_CTRL12_KEEP_FORMAT_OFFSET 2 +#define RTL8367C_RMA_CTRL12_KEEP_FORMAT_MASK 0x4 +#define RTL8367C_RMA_CTRL12_VLAN_LEAKY_OFFSET 1 +#define RTL8367C_RMA_CTRL12_VLAN_LEAKY_MASK 0x2 +#define RTL8367C_RMA_CTRL12_PORTISO_LEAKY_OFFSET 0 +#define RTL8367C_RMA_CTRL12_PORTISO_LEAKY_MASK 0x1 + +#define RTL8367C_REG_RMA_CTRL13 0x0813 +#define RTL8367C_RMA_CTRL13_OPERATION_OFFSET 7 +#define RTL8367C_RMA_CTRL13_OPERATION_MASK 0x180 +#define RTL8367C_RMA_CTRL13_DISCARD_STORM_FILTER_OFFSET 6 +#define RTL8367C_RMA_CTRL13_DISCARD_STORM_FILTER_MASK 0x40 +#define RTL8367C_RMA_CTRL13_KEEP_FORMAT_OFFSET 2 +#define RTL8367C_RMA_CTRL13_KEEP_FORMAT_MASK 0x4 +#define RTL8367C_RMA_CTRL13_VLAN_LEAKY_OFFSET 1 +#define RTL8367C_RMA_CTRL13_VLAN_LEAKY_MASK 0x2 +#define RTL8367C_RMA_CTRL13_PORTISO_LEAKY_OFFSET 0 +#define RTL8367C_RMA_CTRL13_PORTISO_LEAKY_MASK 0x1 + +#define RTL8367C_REG_RMA_CTRL18 0x0818 +#define RTL8367C_RMA_CTRL18_OPERATION_OFFSET 7 +#define RTL8367C_RMA_CTRL18_OPERATION_MASK 0x180 +#define RTL8367C_RMA_CTRL18_DISCARD_STORM_FILTER_OFFSET 6 +#define RTL8367C_RMA_CTRL18_DISCARD_STORM_FILTER_MASK 0x40 +#define RTL8367C_RMA_CTRL18_KEEP_FORMAT_OFFSET 2 +#define RTL8367C_RMA_CTRL18_KEEP_FORMAT_MASK 0x4 +#define RTL8367C_RMA_CTRL18_VLAN_LEAKY_OFFSET 1 +#define RTL8367C_RMA_CTRL18_VLAN_LEAKY_MASK 0x2 +#define RTL8367C_RMA_CTRL18_PORTISO_LEAKY_OFFSET 0 +#define RTL8367C_RMA_CTRL18_PORTISO_LEAKY_MASK 0x1 + +#define RTL8367C_REG_RMA_CTRL1A 0x081a +#define RTL8367C_RMA_CTRL1A_OPERATION_OFFSET 7 +#define RTL8367C_RMA_CTRL1A_OPERATION_MASK 0x180 +#define RTL8367C_RMA_CTRL1A_DISCARD_STORM_FILTER_OFFSET 6 +#define RTL8367C_RMA_CTRL1A_DISCARD_STORM_FILTER_MASK 0x40 +#define RTL8367C_RMA_CTRL1A_KEEP_FORMAT_OFFSET 2 +#define RTL8367C_RMA_CTRL1A_KEEP_FORMAT_MASK 0x4 +#define RTL8367C_RMA_CTRL1A_VLAN_LEAKY_OFFSET 1 +#define RTL8367C_RMA_CTRL1A_VLAN_LEAKY_MASK 0x2 +#define RTL8367C_RMA_CTRL1A_PORTISO_LEAKY_OFFSET 0 +#define RTL8367C_RMA_CTRL1A_PORTISO_LEAKY_MASK 0x1 + +#define RTL8367C_REG_RMA_CTRL20 0x0820 +#define RTL8367C_RMA_CTRL20_OPERATION_OFFSET 7 +#define RTL8367C_RMA_CTRL20_OPERATION_MASK 0x180 +#define RTL8367C_RMA_CTRL20_DISCARD_STORM_FILTER_OFFSET 6 +#define RTL8367C_RMA_CTRL20_DISCARD_STORM_FILTER_MASK 0x40 +#define RTL8367C_RMA_CTRL20_KEEP_FORMAT_OFFSET 2 +#define RTL8367C_RMA_CTRL20_KEEP_FORMAT_MASK 0x4 +#define RTL8367C_RMA_CTRL20_VLAN_LEAKY_OFFSET 1 +#define RTL8367C_RMA_CTRL20_VLAN_LEAKY_MASK 0x2 +#define RTL8367C_RMA_CTRL20_PORTISO_LEAKY_OFFSET 0 +#define RTL8367C_RMA_CTRL20_PORTISO_LEAKY_MASK 0x1 + +#define RTL8367C_REG_RMA_CTRL21 0x0821 +#define RTL8367C_RMA_CTRL21_OPERATION_OFFSET 7 +#define RTL8367C_RMA_CTRL21_OPERATION_MASK 0x180 +#define RTL8367C_RMA_CTRL21_DISCARD_STORM_FILTER_OFFSET 6 +#define RTL8367C_RMA_CTRL21_DISCARD_STORM_FILTER_MASK 0x40 +#define RTL8367C_RMA_CTRL21_KEEP_FORMAT_OFFSET 2 +#define RTL8367C_RMA_CTRL21_KEEP_FORMAT_MASK 0x4 +#define RTL8367C_RMA_CTRL21_VLAN_LEAKY_OFFSET 1 +#define RTL8367C_RMA_CTRL21_VLAN_LEAKY_MASK 0x2 +#define RTL8367C_RMA_CTRL21_PORTISO_LEAKY_OFFSET 0 +#define RTL8367C_RMA_CTRL21_PORTISO_LEAKY_MASK 0x1 + +#define RTL8367C_REG_RMA_CTRL22 0x0822 +#define RTL8367C_RMA_CTRL22_OPERATION_OFFSET 7 +#define RTL8367C_RMA_CTRL22_OPERATION_MASK 0x180 +#define RTL8367C_RMA_CTRL22_DISCARD_STORM_FILTER_OFFSET 6 +#define RTL8367C_RMA_CTRL22_DISCARD_STORM_FILTER_MASK 0x40 +#define RTL8367C_RMA_CTRL22_KEEP_FORMAT_OFFSET 2 +#define RTL8367C_RMA_CTRL22_KEEP_FORMAT_MASK 0x4 +#define RTL8367C_RMA_CTRL22_VLAN_LEAKY_OFFSET 1 +#define RTL8367C_RMA_CTRL22_VLAN_LEAKY_MASK 0x2 +#define RTL8367C_RMA_CTRL22_PORTISO_LEAKY_OFFSET 0 +#define RTL8367C_RMA_CTRL22_PORTISO_LEAKY_MASK 0x1 + +#define RTL8367C_REG_RMA_CTRL_CDP 0x0830 +#define RTL8367C_RMA_CTRL_CDP_OPERATION_OFFSET 7 +#define RTL8367C_RMA_CTRL_CDP_OPERATION_MASK 0x180 +#define RTL8367C_RMA_CTRL_CDP_DISCARD_STORM_FILTER_OFFSET 6 +#define RTL8367C_RMA_CTRL_CDP_DISCARD_STORM_FILTER_MASK 0x40 +#define RTL8367C_RMA_CTRL_CDP_KEEP_FORMAT_OFFSET 2 +#define RTL8367C_RMA_CTRL_CDP_KEEP_FORMAT_MASK 0x4 +#define RTL8367C_RMA_CTRL_CDP_VLAN_LEAKY_OFFSET 1 +#define RTL8367C_RMA_CTRL_CDP_VLAN_LEAKY_MASK 0x2 +#define RTL8367C_RMA_CTRL_CDP_PORTISO_LEAKY_OFFSET 0 +#define RTL8367C_RMA_CTRL_CDP_PORTISO_LEAKY_MASK 0x1 + +#define RTL8367C_REG_RMA_CTRL_CSSTP 0x0831 +#define RTL8367C_RMA_CTRL_CSSTP_OPERATION_OFFSET 7 +#define RTL8367C_RMA_CTRL_CSSTP_OPERATION_MASK 0x180 +#define RTL8367C_RMA_CTRL_CSSTP_DISCARD_STORM_FILTER_OFFSET 6 +#define RTL8367C_RMA_CTRL_CSSTP_DISCARD_STORM_FILTER_MASK 0x40 +#define RTL8367C_RMA_CTRL_CSSTP_KEEP_FORMAT_OFFSET 2 +#define RTL8367C_RMA_CTRL_CSSTP_KEEP_FORMAT_MASK 0x4 +#define RTL8367C_RMA_CTRL_CSSTP_VLAN_LEAKY_OFFSET 1 +#define RTL8367C_RMA_CTRL_CSSTP_VLAN_LEAKY_MASK 0x2 +#define RTL8367C_RMA_CTRL_CSSTP_PORTISO_LEAKY_OFFSET 0 +#define RTL8367C_RMA_CTRL_CSSTP_PORTISO_LEAKY_MASK 0x1 + +#define RTL8367C_REG_RMA_CTRL_LLDP 0x0832 +#define RTL8367C_RMA_CTRL_LLDP_OPERATION_OFFSET 7 +#define RTL8367C_RMA_CTRL_LLDP_OPERATION_MASK 0x180 +#define RTL8367C_RMA_CTRL_LLDP_DISCARD_STORM_FILTER_OFFSET 6 +#define RTL8367C_RMA_CTRL_LLDP_DISCARD_STORM_FILTER_MASK 0x40 +#define RTL8367C_RMA_CTRL_LLDP_KEEP_FORMAT_OFFSET 2 +#define RTL8367C_RMA_CTRL_LLDP_KEEP_FORMAT_MASK 0x4 +#define RTL8367C_RMA_CTRL_LLDP_VLAN_LEAKY_OFFSET 1 +#define RTL8367C_RMA_CTRL_LLDP_VLAN_LEAKY_MASK 0x2 +#define RTL8367C_RMA_CTRL_LLDP_PORTISO_LEAKY_OFFSET 0 +#define RTL8367C_RMA_CTRL_LLDP_PORTISO_LEAKY_MASK 0x1 + +#define RTL8367C_REG_RMA_LLDP_EN 0x0833 +#define RTL8367C_RMA_LLDP_EN_OFFSET 0 +#define RTL8367C_RMA_LLDP_EN_MASK 0x1 + +#define RTL8367C_REG_VLAN_PORTBASED_PRIORITY_CTRL0 0x0851 +#define RTL8367C_VLAN_PORTBASED_PRIORITY_CTRL0_PORT3_PRIORITY_OFFSET 12 +#define RTL8367C_VLAN_PORTBASED_PRIORITY_CTRL0_PORT3_PRIORITY_MASK 0x7000 +#define RTL8367C_VLAN_PORTBASED_PRIORITY_CTRL0_PORT2_PRIORITY_OFFSET 8 +#define RTL8367C_VLAN_PORTBASED_PRIORITY_CTRL0_PORT2_PRIORITY_MASK 0x700 +#define RTL8367C_VLAN_PORTBASED_PRIORITY_CTRL0_PORT1_PRIORITY_OFFSET 4 +#define RTL8367C_VLAN_PORTBASED_PRIORITY_CTRL0_PORT1_PRIORITY_MASK 0x70 +#define RTL8367C_VLAN_PORTBASED_PRIORITY_CTRL0_PORT0_PRIORITY_OFFSET 0 +#define RTL8367C_VLAN_PORTBASED_PRIORITY_CTRL0_PORT0_PRIORITY_MASK 0x7 + +#define RTL8367C_REG_VLAN_PORTBASED_PRIORITY_CTRL1 0x0852 +#define RTL8367C_VLAN_PORTBASED_PRIORITY_CTRL1_PORT7_PRIORITY_OFFSET 12 +#define RTL8367C_VLAN_PORTBASED_PRIORITY_CTRL1_PORT7_PRIORITY_MASK 0x7000 +#define RTL8367C_VLAN_PORTBASED_PRIORITY_CTRL1_PORT6_PRIORITY_OFFSET 8 +#define RTL8367C_VLAN_PORTBASED_PRIORITY_CTRL1_PORT6_PRIORITY_MASK 0x700 +#define RTL8367C_VLAN_PORTBASED_PRIORITY_CTRL1_PORT5_PRIORITY_OFFSET 4 +#define RTL8367C_VLAN_PORTBASED_PRIORITY_CTRL1_PORT5_PRIORITY_MASK 0x70 +#define RTL8367C_VLAN_PORTBASED_PRIORITY_CTRL1_PORT4_PRIORITY_OFFSET 0 +#define RTL8367C_VLAN_PORTBASED_PRIORITY_CTRL1_PORT4_PRIORITY_MASK 0x7 + +#define RTL8367C_REG_VLAN_PORTBASED_PRIORITY_CTRL2 0x0853 +#define RTL8367C_VLAN_PORTBASED_PRIORITY_CTRL2_PORT10_PRIORITY_OFFSET 8 +#define RTL8367C_VLAN_PORTBASED_PRIORITY_CTRL2_PORT10_PRIORITY_MASK 0x700 +#define RTL8367C_VLAN_PORTBASED_PRIORITY_CTRL2_PORT9_PRIORITY_OFFSET 4 +#define RTL8367C_VLAN_PORTBASED_PRIORITY_CTRL2_PORT9_PRIORITY_MASK 0x70 +#define RTL8367C_VLAN_PORTBASED_PRIORITY_CTRL2_PORT8_PRIORITY_OFFSET 0 +#define RTL8367C_VLAN_PORTBASED_PRIORITY_CTRL2_PORT8_PRIORITY_MASK 0x7 + +#define RTL8367C_REG_VLAN_PPB_PRIORITY_ITEM0_CTRL0 0x0855 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM0_CTRL0_PORT3_PRIORITY_OFFSET 12 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM0_CTRL0_PORT3_PRIORITY_MASK 0x7000 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM0_CTRL0_PORT2_PRIORITY_OFFSET 8 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM0_CTRL0_PORT2_PRIORITY_MASK 0x700 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM0_CTRL0_PORT1_PRIORITY_OFFSET 4 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM0_CTRL0_PORT1_PRIORITY_MASK 0x70 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM0_CTRL0_PORT0_PRIORITY_OFFSET 0 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM0_CTRL0_PORT0_PRIORITY_MASK 0x7 + +#define RTL8367C_REG_VLAN_PPB_PRIORITY_ITEM0_CTRL1 0x0856 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM0_CTRL1_PORT7_PRIORITY_OFFSET 12 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM0_CTRL1_PORT7_PRIORITY_MASK 0x7000 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM0_CTRL1_PORT6_PRIORITY_OFFSET 8 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM0_CTRL1_PORT6_PRIORITY_MASK 0x700 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM0_CTRL1_PORT5_PRIORITY_OFFSET 4 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM0_CTRL1_PORT5_PRIORITY_MASK 0x70 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM0_CTRL1_PORT4_PRIORITY_OFFSET 0 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM0_CTRL1_PORT4_PRIORITY_MASK 0x7 + +#define RTL8367C_REG_VLAN_PPB_PRIORITY_ITEM0_CTRL2 0x0857 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM0_CTRL2_PORT10_PRIORITY_OFFSET 8 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM0_CTRL2_PORT10_PRIORITY_MASK 0x700 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM0_CTRL2_PORT9_PRIORITY_OFFSET 4 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM0_CTRL2_PORT9_PRIORITY_MASK 0x70 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM0_CTRL2_PORT8_PRIORITY_OFFSET 0 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM0_CTRL2_PORT8_PRIORITY_MASK 0x7 + +#define RTL8367C_REG_VLAN_PPB_PRIORITY_ITEM1_CTRL0 0x0859 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM1_CTRL0_PORT3_PRIORITY_OFFSET 12 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM1_CTRL0_PORT3_PRIORITY_MASK 0x7000 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM1_CTRL0_PORT2_PRIORITY_OFFSET 8 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM1_CTRL0_PORT2_PRIORITY_MASK 0x700 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM1_CTRL0_PORT1_PRIORITY_OFFSET 4 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM1_CTRL0_PORT1_PRIORITY_MASK 0x70 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM1_CTRL0_PORT0_PRIORITY_OFFSET 0 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM1_CTRL0_PORT0_PRIORITY_MASK 0x7 + +#define RTL8367C_REG_VLAN_PPB_PRIORITY_ITEM1_CTRL1 0x085a +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM1_CTRL1_PORT7_PRIORITY_OFFSET 12 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM1_CTRL1_PORT7_PRIORITY_MASK 0x7000 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM1_CTRL1_PORT6_PRIORITY_OFFSET 8 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM1_CTRL1_PORT6_PRIORITY_MASK 0x700 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM1_CTRL1_PORT5_PRIORITY_OFFSET 4 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM1_CTRL1_PORT5_PRIORITY_MASK 0x70 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM1_CTRL1_PORT4_PRIORITY_OFFSET 0 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM1_CTRL1_PORT4_PRIORITY_MASK 0x7 + +#define RTL8367C_REG_VLAN_PPB_PRIORITY_ITEM1_CTRL2 0x085b +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM1_CTRL2_PORT10_PRIORITY_OFFSET 8 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM1_CTRL2_PORT10_PRIORITY_MASK 0x700 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM1_CTRL2_PORT9_PRIORITY_OFFSET 4 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM1_CTRL2_PORT9_PRIORITY_MASK 0x70 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM1_CTRL2_PORT8_PRIORITY_OFFSET 0 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM1_CTRL2_PORT8_PRIORITY_MASK 0x7 + +#define RTL8367C_REG_VLAN_PPB_PRIORITY_ITEM2_CTRL0 0x085d +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM2_CTRL0_PORT3_PRIORITY_OFFSET 12 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM2_CTRL0_PORT3_PRIORITY_MASK 0x7000 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM2_CTRL0_PORT2_PRIORITY_OFFSET 8 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM2_CTRL0_PORT2_PRIORITY_MASK 0x700 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM2_CTRL0_PORT1_PRIORITY_OFFSET 4 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM2_CTRL0_PORT1_PRIORITY_MASK 0x70 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM2_CTRL0_PORT0_PRIORITY_OFFSET 0 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM2_CTRL0_PORT0_PRIORITY_MASK 0x7 + +#define RTL8367C_REG_VLAN_PPB_PRIORITY_ITEM2_CTRL1 0x085e +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM2_CTRL1_PORT7_PRIORITY_OFFSET 12 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM2_CTRL1_PORT7_PRIORITY_MASK 0x7000 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM2_CTRL1_PORT6_PRIORITY_OFFSET 8 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM2_CTRL1_PORT6_PRIORITY_MASK 0x700 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM2_CTRL1_PORT5_PRIORITY_OFFSET 4 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM2_CTRL1_PORT5_PRIORITY_MASK 0x70 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM2_CTRL1_PORT4_PRIORITY_OFFSET 0 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM2_CTRL1_PORT4_PRIORITY_MASK 0x7 + +#define RTL8367C_REG_VLAN_PPB_PRIORITY_ITEM2_CTRL2 0x085f +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM2_CTRL2_PORT10_PRIORITY_OFFSET 8 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM2_CTRL2_PORT10_PRIORITY_MASK 0x700 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM2_CTRL2_PORT9_PRIORITY_OFFSET 4 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM2_CTRL2_PORT9_PRIORITY_MASK 0x70 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM2_CTRL2_PORT8_PRIORITY_OFFSET 0 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM2_CTRL2_PORT8_PRIORITY_MASK 0x7 + +#define RTL8367C_REG_VLAN_PPB_PRIORITY_ITEM3_CTRL0 0x0861 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM3_CTRL0_PORT3_PRIORITY_OFFSET 12 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM3_CTRL0_PORT3_PRIORITY_MASK 0x7000 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM3_CTRL0_PORT2_PRIORITY_OFFSET 8 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM3_CTRL0_PORT2_PRIORITY_MASK 0x700 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM3_CTRL0_PORT1_PRIORITY_OFFSET 4 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM3_CTRL0_PORT1_PRIORITY_MASK 0x70 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM3_CTRL0_PORT0_PRIORITY_OFFSET 0 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM3_CTRL0_PORT0_PRIORITY_MASK 0x7 + +#define RTL8367C_REG_VLAN_PPB_PRIORITY_ITEM3_CTRL1 0x0862 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM3_CTRL1_PORT7_PRIORITY_OFFSET 12 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM3_CTRL1_PORT7_PRIORITY_MASK 0x7000 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM3_CTRL1_PORT6_PRIORITY_OFFSET 8 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM3_CTRL1_PORT6_PRIORITY_MASK 0x700 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM3_CTRL1_PORT5_PRIORITY_OFFSET 4 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM3_CTRL1_PORT5_PRIORITY_MASK 0x70 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM3_CTRL1_PORT4_PRIORITY_OFFSET 0 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM3_CTRL1_PORT4_PRIORITY_MASK 0x7 + +#define RTL8367C_REG_VLAN_PPB_PRIORITY_ITEM3_CTRL2 0x0863 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM3_CTRL2_PORT10_PRIORITY_OFFSET 8 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM3_CTRL2_PORT10_PRIORITY_MASK 0x700 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM3_CTRL2_PORT9_PRIORITY_OFFSET 4 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM3_CTRL2_PORT9_PRIORITY_MASK 0x70 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM3_CTRL2_PORT8_PRIORITY_OFFSET 0 +#define RTL8367C_VLAN_PPB_PRIORITY_ITEM3_CTRL2_PORT8_PRIORITY_MASK 0x7 + +#define RTL8367C_REG_QOS_1Q_PRIORITY_REMAPPING_CTRL0 0x0865 +#define RTL8367C_QOS_1Q_PRIORITY_REMAPPING_CTRL0_PRIORITY3_OFFSET 12 +#define RTL8367C_QOS_1Q_PRIORITY_REMAPPING_CTRL0_PRIORITY3_MASK 0x7000 +#define RTL8367C_QOS_1Q_PRIORITY_REMAPPING_CTRL0_PRIORITY2_OFFSET 8 +#define RTL8367C_QOS_1Q_PRIORITY_REMAPPING_CTRL0_PRIORITY2_MASK 0x700 +#define RTL8367C_QOS_1Q_PRIORITY_REMAPPING_CTRL0_PRIORITY1_OFFSET 4 +#define RTL8367C_QOS_1Q_PRIORITY_REMAPPING_CTRL0_PRIORITY1_MASK 0x70 +#define RTL8367C_QOS_1Q_PRIORITY_REMAPPING_CTRL0_PRIORITY0_OFFSET 0 +#define RTL8367C_QOS_1Q_PRIORITY_REMAPPING_CTRL0_PRIORITY0_MASK 0x7 + +#define RTL8367C_REG_QOS_1Q_PRIORITY_REMAPPING_CTRL1 0x0866 +#define RTL8367C_QOS_1Q_PRIORITY_REMAPPING_CTRL1_PRIORITY7_OFFSET 12 +#define RTL8367C_QOS_1Q_PRIORITY_REMAPPING_CTRL1_PRIORITY7_MASK 0x7000 +#define RTL8367C_QOS_1Q_PRIORITY_REMAPPING_CTRL1_PRIORITY6_OFFSET 8 +#define RTL8367C_QOS_1Q_PRIORITY_REMAPPING_CTRL1_PRIORITY6_MASK 0x700 +#define RTL8367C_QOS_1Q_PRIORITY_REMAPPING_CTRL1_PRIORITY5_OFFSET 4 +#define RTL8367C_QOS_1Q_PRIORITY_REMAPPING_CTRL1_PRIORITY5_MASK 0x70 +#define RTL8367C_QOS_1Q_PRIORITY_REMAPPING_CTRL1_PRIORITY4_OFFSET 0 +#define RTL8367C_QOS_1Q_PRIORITY_REMAPPING_CTRL1_PRIORITY4_MASK 0x7 + +#define RTL8367C_REG_QOS_DSCP_TO_PRIORITY_CTRL0 0x0867 +#define RTL8367C_DSCP3_PRIORITY_OFFSET 12 +#define RTL8367C_DSCP3_PRIORITY_MASK 0x7000 +#define RTL8367C_DSCP2_PRIORITY_OFFSET 8 +#define RTL8367C_DSCP2_PRIORITY_MASK 0x700 +#define RTL8367C_DSCP1_PRIORITY_OFFSET 4 +#define RTL8367C_DSCP1_PRIORITY_MASK 0x70 +#define RTL8367C_DSCP0_PRIORITY_OFFSET 0 +#define RTL8367C_DSCP0_PRIORITY_MASK 0x7 + +#define RTL8367C_REG_QOS_DSCP_TO_PRIORITY_CTRL1 0x0868 +#define RTL8367C_DSCP7_PRIORITY_OFFSET 12 +#define RTL8367C_DSCP7_PRIORITY_MASK 0x7000 +#define RTL8367C_DSCP6_PRIORITY_OFFSET 8 +#define RTL8367C_DSCP6_PRIORITY_MASK 0x700 +#define RTL8367C_DSCP5_PRIORITY_OFFSET 4 +#define RTL8367C_DSCP5_PRIORITY_MASK 0x70 +#define RTL8367C_DSCP4_PRIORITY_OFFSET 0 +#define RTL8367C_DSCP4_PRIORITY_MASK 0x7 + +#define RTL8367C_REG_QOS_DSCP_TO_PRIORITY_CTRL2 0x0869 +#define RTL8367C_DSCP11_PRIORITY_OFFSET 12 +#define RTL8367C_DSCP11_PRIORITY_MASK 0x7000 +#define RTL8367C_DSCP10_PRIORITY_OFFSET 8 +#define RTL8367C_DSCP10_PRIORITY_MASK 0x700 +#define RTL8367C_DSCP9_PRIORITY_OFFSET 4 +#define RTL8367C_DSCP9_PRIORITY_MASK 0x70 +#define RTL8367C_DSCP8_PRIORITY_OFFSET 0 +#define RTL8367C_DSCP8_PRIORITY_MASK 0x7 + +#define RTL8367C_REG_QOS_DSCP_TO_PRIORITY_CTRL3 0x086a +#define RTL8367C_DSCP15_PRIORITY_OFFSET 12 +#define RTL8367C_DSCP15_PRIORITY_MASK 0x7000 +#define RTL8367C_DSCP14_PRIORITY_OFFSET 8 +#define RTL8367C_DSCP14_PRIORITY_MASK 0x700 +#define RTL8367C_DSCP13_PRIORITY_OFFSET 4 +#define RTL8367C_DSCP13_PRIORITY_MASK 0x70 +#define RTL8367C_DSCP12_PRIORITY_OFFSET 0 +#define RTL8367C_DSCP12_PRIORITY_MASK 0x7 + +#define RTL8367C_REG_QOS_DSCP_TO_PRIORITY_CTRL4 0x086b +#define RTL8367C_DSCP19_PRIORITY_OFFSET 12 +#define RTL8367C_DSCP19_PRIORITY_MASK 0x7000 +#define RTL8367C_DSCP18_PRIORITY_OFFSET 8 +#define RTL8367C_DSCP18_PRIORITY_MASK 0x700 +#define RTL8367C_DSCP17_PRIORITY_OFFSET 4 +#define RTL8367C_DSCP17_PRIORITY_MASK 0x70 +#define RTL8367C_DSCP16_PRIORITY_OFFSET 0 +#define RTL8367C_DSCP16_PRIORITY_MASK 0x7 + +#define RTL8367C_REG_QOS_DSCP_TO_PRIORITY_CTRL5 0x086c +#define RTL8367C_DSCP23_PRIORITY_OFFSET 12 +#define RTL8367C_DSCP23_PRIORITY_MASK 0x7000 +#define RTL8367C_DSCP22_PRIORITY_OFFSET 8 +#define RTL8367C_DSCP22_PRIORITY_MASK 0x700 +#define RTL8367C_DSCP21_PRIORITY_OFFSET 4 +#define RTL8367C_DSCP21_PRIORITY_MASK 0x70 +#define RTL8367C_DSCP20_PRIORITY_OFFSET 0 +#define RTL8367C_DSCP20_PRIORITY_MASK 0x7 + +#define RTL8367C_REG_QOS_DSCP_TO_PRIORITY_CTRL6 0x086d +#define RTL8367C_DSCP27_PRIORITY_OFFSET 12 +#define RTL8367C_DSCP27_PRIORITY_MASK 0x7000 +#define RTL8367C_DSCP26_PRIORITY_OFFSET 8 +#define RTL8367C_DSCP26_PRIORITY_MASK 0x700 +#define RTL8367C_DSCP25_PRIORITY_OFFSET 4 +#define RTL8367C_DSCP25_PRIORITY_MASK 0x70 +#define RTL8367C_DSCP24_PRIORITY_OFFSET 0 +#define RTL8367C_DSCP24_PRIORITY_MASK 0x7 + +#define RTL8367C_REG_QOS_DSCP_TO_PRIORITY_CTRL7 0x086e +#define RTL8367C_DSCP31_PRIORITY_OFFSET 12 +#define RTL8367C_DSCP31_PRIORITY_MASK 0x7000 +#define RTL8367C_DSCP30_PRIORITY_OFFSET 8 +#define RTL8367C_DSCP30_PRIORITY_MASK 0x700 +#define RTL8367C_DSCP29_PRIORITY_OFFSET 4 +#define RTL8367C_DSCP29_PRIORITY_MASK 0x70 +#define RTL8367C_DSCP28_PRIORITY_OFFSET 0 +#define RTL8367C_DSCP28_PRIORITY_MASK 0x7 + +#define RTL8367C_REG_QOS_DSCP_TO_PRIORITY_CTRL8 0x086f +#define RTL8367C_DSCP35_PRIORITY_OFFSET 12 +#define RTL8367C_DSCP35_PRIORITY_MASK 0x7000 +#define RTL8367C_DSCP34_PRIORITY_OFFSET 8 +#define RTL8367C_DSCP34_PRIORITY_MASK 0x700 +#define RTL8367C_DSCP33_PRIORITY_OFFSET 4 +#define RTL8367C_DSCP33_PRIORITY_MASK 0x70 +#define RTL8367C_DSCP32_PRIORITY_OFFSET 0 +#define RTL8367C_DSCP32_PRIORITY_MASK 0x7 + +#define RTL8367C_REG_QOS_DSCP_TO_PRIORITY_CTRL9 0x0870 +#define RTL8367C_DSCP39_PRIORITY_OFFSET 12 +#define RTL8367C_DSCP39_PRIORITY_MASK 0x7000 +#define RTL8367C_DSCP38_PRIORITY_OFFSET 8 +#define RTL8367C_DSCP38_PRIORITY_MASK 0x700 +#define RTL8367C_DSCP37_PRIORITY_OFFSET 4 +#define RTL8367C_DSCP37_PRIORITY_MASK 0x70 +#define RTL8367C_DSCP36_PRIORITY_OFFSET 0 +#define RTL8367C_DSCP36_PRIORITY_MASK 0x7 + +#define RTL8367C_REG_QOS_DSCP_TO_PRIORITY_CTRL10 0x0871 +#define RTL8367C_DSCP43_PRIORITY_OFFSET 12 +#define RTL8367C_DSCP43_PRIORITY_MASK 0x7000 +#define RTL8367C_DSCP42_PRIORITY_OFFSET 8 +#define RTL8367C_DSCP42_PRIORITY_MASK 0x700 +#define RTL8367C_DSCP41_PRIORITY_OFFSET 4 +#define RTL8367C_DSCP41_PRIORITY_MASK 0x70 +#define RTL8367C_DSCP40_PRIORITY_OFFSET 0 +#define RTL8367C_DSCP40_PRIORITY_MASK 0x7 + +#define RTL8367C_REG_QOS_DSCP_TO_PRIORITY_CTRL11 0x0872 +#define RTL8367C_DSCP47_PRIORITY_OFFSET 12 +#define RTL8367C_DSCP47_PRIORITY_MASK 0x7000 +#define RTL8367C_DSCP46_PRIORITY_OFFSET 8 +#define RTL8367C_DSCP46_PRIORITY_MASK 0x700 +#define RTL8367C_DSCP45_PRIORITY_OFFSET 4 +#define RTL8367C_DSCP45_PRIORITY_MASK 0x70 +#define RTL8367C_DSCP44_PRIORITY_OFFSET 0 +#define RTL8367C_DSCP44_PRIORITY_MASK 0x7 + +#define RTL8367C_REG_QOS_DSCP_TO_PRIORITY_CTRL12 0x0873 +#define RTL8367C_DSCP51_PRIORITY_OFFSET 12 +#define RTL8367C_DSCP51_PRIORITY_MASK 0x7000 +#define RTL8367C_DSCP50_PRIORITY_OFFSET 8 +#define RTL8367C_DSCP50_PRIORITY_MASK 0x700 +#define RTL8367C_DSCP49_PRIORITY_OFFSET 4 +#define RTL8367C_DSCP49_PRIORITY_MASK 0x70 +#define RTL8367C_DSCP48_PRIORITY_OFFSET 0 +#define RTL8367C_DSCP48_PRIORITY_MASK 0x7 + +#define RTL8367C_REG_QOS_DSCP_TO_PRIORITY_CTRL13 0x0874 +#define RTL8367C_DSCP55_PRIORITY_OFFSET 12 +#define RTL8367C_DSCP55_PRIORITY_MASK 0x7000 +#define RTL8367C_DSCP54_PRIORITY_OFFSET 8 +#define RTL8367C_DSCP54_PRIORITY_MASK 0x700 +#define RTL8367C_DSCP53_PRIORITY_OFFSET 4 +#define RTL8367C_DSCP53_PRIORITY_MASK 0x70 +#define RTL8367C_DSCP52_PRIORITY_OFFSET 0 +#define RTL8367C_DSCP52_PRIORITY_MASK 0x7 + +#define RTL8367C_REG_QOS_DSCP_TO_PRIORITY_CTRL14 0x0875 +#define RTL8367C_DSCP59_PRIORITY_OFFSET 12 +#define RTL8367C_DSCP59_PRIORITY_MASK 0x7000 +#define RTL8367C_DSCP58_PRIORITY_OFFSET 8 +#define RTL8367C_DSCP58_PRIORITY_MASK 0x700 +#define RTL8367C_DSCP57_PRIORITY_OFFSET 4 +#define RTL8367C_DSCP57_PRIORITY_MASK 0x70 +#define RTL8367C_DSCP56_PRIORITY_OFFSET 0 +#define RTL8367C_DSCP56_PRIORITY_MASK 0x7 + +#define RTL8367C_REG_QOS_DSCP_TO_PRIORITY_CTRL15 0x0876 +#define RTL8367C_DSCP63_PRIORITY_OFFSET 12 +#define RTL8367C_DSCP63_PRIORITY_MASK 0x7000 +#define RTL8367C_DSCP62_PRIORITY_OFFSET 8 +#define RTL8367C_DSCP62_PRIORITY_MASK 0x700 +#define RTL8367C_DSCP61_PRIORITY_OFFSET 4 +#define RTL8367C_DSCP61_PRIORITY_MASK 0x70 +#define RTL8367C_DSCP60_PRIORITY_OFFSET 0 +#define RTL8367C_DSCP60_PRIORITY_MASK 0x7 + +#define RTL8367C_REG_QOS_PORTBASED_PRIORITY_CTRL0 0x0877 +#define RTL8367C_QOS_PORTBASED_PRIORITY_CTRL0_PORT3_PRIORITY_OFFSET 12 +#define RTL8367C_QOS_PORTBASED_PRIORITY_CTRL0_PORT3_PRIORITY_MASK 0x7000 +#define RTL8367C_QOS_PORTBASED_PRIORITY_CTRL0_PORT2_PRIORITY_OFFSET 8 +#define RTL8367C_QOS_PORTBASED_PRIORITY_CTRL0_PORT2_PRIORITY_MASK 0x700 +#define RTL8367C_QOS_PORTBASED_PRIORITY_CTRL0_PORT1_PRIORITY_OFFSET 4 +#define RTL8367C_QOS_PORTBASED_PRIORITY_CTRL0_PORT1_PRIORITY_MASK 0x70 +#define RTL8367C_QOS_PORTBASED_PRIORITY_CTRL0_PORT0_PRIORITY_OFFSET 0 +#define RTL8367C_QOS_PORTBASED_PRIORITY_CTRL0_PORT0_PRIORITY_MASK 0x7 + +#define RTL8367C_REG_QOS_PORTBASED_PRIORITY_CTRL1 0x0878 +#define RTL8367C_QOS_PORTBASED_PRIORITY_CTRL1_PORT7_PRIORITY_OFFSET 12 +#define RTL8367C_QOS_PORTBASED_PRIORITY_CTRL1_PORT7_PRIORITY_MASK 0x7000 +#define RTL8367C_QOS_PORTBASED_PRIORITY_CTRL1_PORT6_PRIORITY_OFFSET 8 +#define RTL8367C_QOS_PORTBASED_PRIORITY_CTRL1_PORT6_PRIORITY_MASK 0x700 +#define RTL8367C_QOS_PORTBASED_PRIORITY_CTRL1_PORT5_PRIORITY_OFFSET 4 +#define RTL8367C_QOS_PORTBASED_PRIORITY_CTRL1_PORT5_PRIORITY_MASK 0x70 +#define RTL8367C_QOS_PORTBASED_PRIORITY_CTRL1_PORT4_PRIORITY_OFFSET 0 +#define RTL8367C_QOS_PORTBASED_PRIORITY_CTRL1_PORT4_PRIORITY_MASK 0x7 + +#define RTL8367C_REG_DUMMY0879 0x0879 +#define RTL8367C_DUMMY0879_OFFSET 0 +#define RTL8367C_DUMMY0879_MASK 0x1 + +#define RTL8367C_REG_QOS_PORTBASED_PRIORITY_CTRL2 0x087a +#define RTL8367C_QOS_PORTBASED_PRIORITY_CTRL2_PORT10_PRIORITY_OFFSET 8 +#define RTL8367C_QOS_PORTBASED_PRIORITY_CTRL2_PORT10_PRIORITY_MASK 0x700 +#define RTL8367C_QOS_PORTBASED_PRIORITY_CTRL2_PORT9_PRIORITY_OFFSET 4 +#define RTL8367C_QOS_PORTBASED_PRIORITY_CTRL2_PORT9_PRIORITY_MASK 0x70 +#define RTL8367C_QOS_PORTBASED_PRIORITY_CTRL2_PORT8_PRIORITY_OFFSET 0 +#define RTL8367C_QOS_PORTBASED_PRIORITY_CTRL2_PORT8_PRIORITY_MASK 0x7 + +#define RTL8367C_REG_QOS_INTERNAL_PRIORITY_DECISION_CTRL0 0x087b +#define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_CTRL0_QOS_ACL_WEIGHT_OFFSET 8 +#define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_CTRL0_QOS_ACL_WEIGHT_MASK 0xFF00 +#define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_CTRL0_QOS_PORT_WEIGHT_OFFSET 0 +#define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_CTRL0_QOS_PORT_WEIGHT_MASK 0xFF + +#define RTL8367C_REG_QOS_INTERNAL_PRIORITY_DECISION_CTRL1 0x087c +#define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_CTRL1_QOS_DOT1Q_WEIGHT_OFFSET 8 +#define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_CTRL1_QOS_DOT1Q_WEIGHT_MASK 0xFF00 +#define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_CTRL1_QOS_DSCP_WEIGHT_OFFSET 0 +#define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_CTRL1_QOS_DSCP_WEIGHT_MASK 0xFF + +#define RTL8367C_REG_QOS_INTERNAL_PRIORITY_DECISION_CTRL2 0x087d +#define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_CTRL2_QOS_CVLAN_WEIGHT_OFFSET 8 +#define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_CTRL2_QOS_CVLAN_WEIGHT_MASK 0xFF00 +#define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_CTRL2_QOS_SVLAN_WEIGHT_OFFSET 0 +#define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_CTRL2_QOS_SVLAN_WEIGHT_MASK 0xFF + +#define RTL8367C_REG_QOS_INTERNAL_PRIORITY_DECISION_CTRL3 0x087e +#define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_CTRL3_QOS_SA_WEIGHT_OFFSET 8 +#define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_CTRL3_QOS_SA_WEIGHT_MASK 0xFF00 +#define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_CTRL3_QOS_LUTFWD_WEIGHT_OFFSET 0 +#define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_CTRL3_QOS_LUTFWD_WEIGHT_MASK 0xFF + +#define RTL8367C_REG_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL0 0x087f +#define RTL8367C_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL0_PRIORITY3_OFFSET 12 +#define RTL8367C_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL0_PRIORITY3_MASK 0x7000 +#define RTL8367C_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL0_PRIORITY2_OFFSET 8 +#define RTL8367C_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL0_PRIORITY2_MASK 0x700 +#define RTL8367C_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL0_PRIORITY1_OFFSET 4 +#define RTL8367C_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL0_PRIORITY1_MASK 0x70 +#define RTL8367C_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL0_PRIORITY0_OFFSET 0 +#define RTL8367C_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL0_PRIORITY0_MASK 0x7 + +#define RTL8367C_REG_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL1 0x0880 +#define RTL8367C_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL1_PRIORITY7_OFFSET 12 +#define RTL8367C_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL1_PRIORITY7_MASK 0x7000 +#define RTL8367C_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL1_PRIORITY6_OFFSET 8 +#define RTL8367C_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL1_PRIORITY6_MASK 0x700 +#define RTL8367C_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL1_PRIORITY5_OFFSET 4 +#define RTL8367C_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL1_PRIORITY5_MASK 0x70 +#define RTL8367C_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL1_PRIORITY4_OFFSET 0 +#define RTL8367C_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL1_PRIORITY4_MASK 0x7 + +#define RTL8367C_REG_QOS_TRAP_PRIORITY0 0x0881 +#define RTL8367C_UNKNOWN_MC_PRIORTY_OFFSET 12 +#define RTL8367C_UNKNOWN_MC_PRIORTY_MASK 0x7000 +#define RTL8367C_SVLAN_PRIOIRTY_OFFSET 8 +#define RTL8367C_SVLAN_PRIOIRTY_MASK 0x700 +#define RTL8367C_OAM_PRIOIRTY_OFFSET 4 +#define RTL8367C_OAM_PRIOIRTY_MASK 0x70 +#define RTL8367C_DOT1X_PRIORTY_OFFSET 0 +#define RTL8367C_DOT1X_PRIORTY_MASK 0x7 + +#define RTL8367C_REG_QOS_TRAP_PRIORITY1 0x0882 +#define RTL8367C_DW8051_TRAP_PRI_OFFSET 4 +#define RTL8367C_DW8051_TRAP_PRI_MASK 0x70 +#define RTL8367C_EEELLDP_TRAP_PRI_OFFSET 0 +#define RTL8367C_EEELLDP_TRAP_PRI_MASK 0x7 + +#define RTL8367C_REG_MAX_LENGTH_CFG 0x0883 +#define RTL8367C_MAX_LENGTH_GIGA_OFFSET 8 +#define RTL8367C_MAX_LENGTH_GIGA_MASK 0xFF00 +#define RTL8367C_MAX_LENGTH_10_100M_OFFSET 0 +#define RTL8367C_MAX_LENGTH_10_100M_MASK 0xFF + +#define RTL8367C_REG_MAX_LEN_RX_TX 0x0884 +#define RTL8367C_MAX_LEN_RX_TX_OFFSET 0 +#define RTL8367C_MAX_LEN_RX_TX_MASK 0x3 + +#define RTL8367C_REG_QOS_INTERNAL_PRIORITY_DECISION2_CTRL0 0x0885 +#define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION2_CTRL0_QOS_ACL_WEIGHT_OFFSET 8 +#define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION2_CTRL0_QOS_ACL_WEIGHT_MASK 0xFF00 +#define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION2_CTRL0_QOS_PORT_WEIGHT_OFFSET 0 +#define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION2_CTRL0_QOS_PORT_WEIGHT_MASK 0xFF + +#define RTL8367C_REG_QOS_INTERNAL_PRIORITY_DECISION2_CTRL1 0x0886 +#define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION2_CTRL1_QOS_DOT1Q_WEIGHT_OFFSET 8 +#define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION2_CTRL1_QOS_DOT1Q_WEIGHT_MASK 0xFF00 +#define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION2_CTRL1_QOS_DSCP_WEIGHT_OFFSET 0 +#define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION2_CTRL1_QOS_DSCP_WEIGHT_MASK 0xFF + +#define RTL8367C_REG_QOS_INTERNAL_PRIORITY_DECISION2_CTRL2 0x0887 +#define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION2_CTRL2_QOS_CVLAN_WEIGHT_OFFSET 8 +#define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION2_CTRL2_QOS_CVLAN_WEIGHT_MASK 0xFF00 +#define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION2_CTRL2_QOS_SVLAN_WEIGHT_OFFSET 0 +#define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION2_CTRL2_QOS_SVLAN_WEIGHT_MASK 0xFF + +#define RTL8367C_REG_QOS_INTERNAL_PRIORITY_DECISION2_CTRL3 0x0888 +#define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION2_CTRL3_QOS_SA_WEIGHT_OFFSET 8 +#define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION2_CTRL3_QOS_SA_WEIGHT_MASK 0xFF00 +#define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION2_CTRL3_QOS_LUTFWD_WEIGHT_OFFSET 0 +#define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION2_CTRL3_QOS_LUTFWD_WEIGHT_MASK 0xFF + +#define RTL8367C_REG_QOS_INTERNAL_PRIORITY_DECISION_IDX 0x0889 +#define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_IDX_OFFSET 0 +#define RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_IDX_MASK 0x7FF + +#define RTL8367C_REG_MAX_LENGTH_CFG_EXT 0x088a +#define RTL8367C_MAX_LENGTH_GIGA_EXT_OFFSET 3 +#define RTL8367C_MAX_LENGTH_GIGA_EXT_MASK 0x38 +#define RTL8367C_MAX_LENGTH_10_100M_EXT_OFFSET 0 +#define RTL8367C_MAX_LENGTH_10_100M_EXT_MASK 0x7 + +#define RTL8367C_REG_MAX_LEN_RX_TX_CFG0 0x088c +#define RTL8367C_MAX_LEN_RX_TX_CFG0_OFFSET 0 +#define RTL8367C_MAX_LEN_RX_TX_CFG0_MASK 0x3FFF + +#define RTL8367C_REG_MAX_LEN_RX_TX_CFG1 0x088d +#define RTL8367C_MAX_LEN_RX_TX_CFG1_OFFSET 0 +#define RTL8367C_MAX_LEN_RX_TX_CFG1_MASK 0x3FFF + +#define RTL8367C_REG_UNDA_FLOODING_PMSK 0x0890 +#define RTL8367C_UNDA_FLOODING_PMSK_OFFSET 0 +#define RTL8367C_UNDA_FLOODING_PMSK_MASK 0x7FF + +#define RTL8367C_REG_UNMCAST_FLOADING_PMSK 0x0891 +#define RTL8367C_UNMCAST_FLOADING_PMSK_OFFSET 0 +#define RTL8367C_UNMCAST_FLOADING_PMSK_MASK 0x7FF + +#define RTL8367C_REG_BCAST_FLOADING_PMSK 0x0892 +#define RTL8367C_BCAST_FLOADING_PMSK_OFFSET 0 +#define RTL8367C_BCAST_FLOADING_PMSK_MASK 0x7FF + +#define RTL8367C_REG_PORT_TRUNK_HASH_MAPPING_CTRL2 0x08a0 +#define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL2_HASH7_OFFSET 14 +#define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL2_HASH7_MASK 0xC000 +#define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL2_HASH6_OFFSET 12 +#define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL2_HASH6_MASK 0x3000 +#define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL2_HASH5_OFFSET 10 +#define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL2_HASH5_MASK 0xC00 +#define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL2_HASH4_OFFSET 8 +#define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL2_HASH4_MASK 0x300 +#define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL2_HASH3_OFFSET 6 +#define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL2_HASH3_MASK 0xC0 +#define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL2_HASH2_OFFSET 4 +#define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL2_HASH2_MASK 0x30 +#define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL2_HASH1_OFFSET 2 +#define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL2_HASH1_MASK 0xC +#define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL2_HASH0_OFFSET 0 +#define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL2_HASH0_MASK 0x3 + +#define RTL8367C_REG_PORT_TRUNK_HASH_MAPPING_CTRL3 0x08a1 +#define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL3_HASH15_OFFSET 14 +#define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL3_HASH15_MASK 0xC000 +#define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL3_HASH14_OFFSET 12 +#define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL3_HASH14_MASK 0x3000 +#define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL3_HASH13_OFFSET 10 +#define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL3_HASH13_MASK 0xC00 +#define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL3_HASH12_OFFSET 8 +#define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL3_HASH12_MASK 0x300 +#define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL3_HASH11_OFFSET 6 +#define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL3_HASH11_MASK 0xC0 +#define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL3_HASH10_OFFSET 4 +#define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL3_HASH10_MASK 0x30 +#define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL3_HASH9_OFFSET 2 +#define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL3_HASH9_MASK 0xC +#define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL3_HASH8_OFFSET 0 +#define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL3_HASH8_MASK 0x3 + +#define RTL8367C_REG_PORT_ISOLATION_PORT0_MASK 0x08a2 +#define RTL8367C_PORT_ISOLATION_PORT0_MASK_OFFSET 0 +#define RTL8367C_PORT_ISOLATION_PORT0_MASK_MASK 0x7FF + +#define RTL8367C_REG_PORT_ISOLATION_PORT1_MASK 0x08a3 +#define RTL8367C_PORT_ISOLATION_PORT1_MASK_OFFSET 0 +#define RTL8367C_PORT_ISOLATION_PORT1_MASK_MASK 0x7FF + +#define RTL8367C_REG_PORT_ISOLATION_PORT2_MASK 0x08a4 +#define RTL8367C_PORT_ISOLATION_PORT2_MASK_OFFSET 0 +#define RTL8367C_PORT_ISOLATION_PORT2_MASK_MASK 0x7FF + +#define RTL8367C_REG_PORT_ISOLATION_PORT3_MASK 0x08a5 +#define RTL8367C_PORT_ISOLATION_PORT3_MASK_OFFSET 0 +#define RTL8367C_PORT_ISOLATION_PORT3_MASK_MASK 0x7FF + +#define RTL8367C_REG_PORT_ISOLATION_PORT4_MASK 0x08a6 +#define RTL8367C_PORT_ISOLATION_PORT4_MASK_OFFSET 0 +#define RTL8367C_PORT_ISOLATION_PORT4_MASK_MASK 0x7FF + +#define RTL8367C_REG_PORT_ISOLATION_PORT5_MASK 0x08a7 +#define RTL8367C_PORT_ISOLATION_PORT5_MASK_OFFSET 0 +#define RTL8367C_PORT_ISOLATION_PORT5_MASK_MASK 0x7FF + +#define RTL8367C_REG_PORT_ISOLATION_PORT6_MASK 0x08a8 +#define RTL8367C_PORT_ISOLATION_PORT6_MASK_OFFSET 0 +#define RTL8367C_PORT_ISOLATION_PORT6_MASK_MASK 0x7FF + +#define RTL8367C_REG_PORT_ISOLATION_PORT7_MASK 0x08a9 +#define RTL8367C_PORT_ISOLATION_PORT7_MASK_OFFSET 0 +#define RTL8367C_PORT_ISOLATION_PORT7_MASK_MASK 0x7FF + +#define RTL8367C_REG_PORT_ISOLATION_PORT8_MASK 0x08aa +#define RTL8367C_PORT_ISOLATION_PORT8_MASK_OFFSET 0 +#define RTL8367C_PORT_ISOLATION_PORT8_MASK_MASK 0x7FF + +#define RTL8367C_REG_PORT_ISOLATION_PORT9_MASK 0x08ab +#define RTL8367C_PORT_ISOLATION_PORT9_MASK_OFFSET 0 +#define RTL8367C_PORT_ISOLATION_PORT9_MASK_MASK 0x7FF + +#define RTL8367C_REG_PORT_ISOLATION_PORT10_MASK 0x08ac +#define RTL8367C_PORT_ISOLATION_PORT10_MASK_OFFSET 0 +#define RTL8367C_PORT_ISOLATION_PORT10_MASK_MASK 0x7FF + +#define RTL8367C_REG_FORCE_CTRL 0x08b4 +#define RTL8367C_FORCE_CTRL_OFFSET 0 +#define RTL8367C_FORCE_CTRL_MASK 0x7FF + +#define RTL8367C_REG_FORCE_PORT0_MASK 0x08b5 +#define RTL8367C_FORCE_PORT0_MASK_OFFSET 0 +#define RTL8367C_FORCE_PORT0_MASK_MASK 0x7FF + +#define RTL8367C_REG_FORCE_PORT1_MASK 0x08b6 +#define RTL8367C_FORCE_PORT1_MASK_OFFSET 0 +#define RTL8367C_FORCE_PORT1_MASK_MASK 0x7FF + +#define RTL8367C_REG_FORCE_PORT2_MASK 0x08b7 +#define RTL8367C_FORCE_PORT2_MASK_OFFSET 0 +#define RTL8367C_FORCE_PORT2_MASK_MASK 0x7FF + +#define RTL8367C_REG_FORCE_PORT3_MASK 0x08b8 +#define RTL8367C_FORCE_PORT3_MASK_OFFSET 0 +#define RTL8367C_FORCE_PORT3_MASK_MASK 0x7FF + +#define RTL8367C_REG_FORCE_PORT4_MASK 0x08b9 +#define RTL8367C_FORCE_PORT4_MASK_OFFSET 0 +#define RTL8367C_FORCE_PORT4_MASK_MASK 0x7FF + +#define RTL8367C_REG_FORCE_PORT5_MASK 0x08ba +#define RTL8367C_FORCE_PORT5_MASK_OFFSET 0 +#define RTL8367C_FORCE_PORT5_MASK_MASK 0x7FF + +#define RTL8367C_REG_FORCE_PORT6_MASK 0x08bb +#define RTL8367C_FORCE_PORT6_MASK_OFFSET 0 +#define RTL8367C_FORCE_PORT6_MASK_MASK 0x7FF + +#define RTL8367C_REG_FORCE_PORT7_MASK 0x08bc +#define RTL8367C_FORCE_PORT7_MASK_OFFSET 0 +#define RTL8367C_FORCE_PORT7_MASK_MASK 0x7FF + +#define RTL8367C_REG_FORCE_PORT8_MASK 0x08bd +#define RTL8367C_FORCE_PORT8_MASK_OFFSET 0 +#define RTL8367C_FORCE_PORT8_MASK_MASK 0x7FF + +#define RTL8367C_REG_FORCE_PORT9_MASK 0x08be +#define RTL8367C_FORCE_PORT9_MASK_OFFSET 0 +#define RTL8367C_FORCE_PORT9_MASK_MASK 0x7FF + +#define RTL8367C_REG_FORCE_PORT10_MASK 0x08bf +#define RTL8367C_FORCE_PORT10_MASK_OFFSET 0 +#define RTL8367C_FORCE_PORT10_MASK_MASK 0x7FF + +#define RTL8367C_REG_SOURCE_PORT_PERMIT 0x08c5 +#define RTL8367C_SOURCE_PORT_PERMIT_OFFSET 0 +#define RTL8367C_SOURCE_PORT_PERMIT_MASK 0x7FF + +#define RTL8367C_REG_IPMCAST_VLAN_LEAKY 0x08c6 +#define RTL8367C_IPMCAST_VLAN_LEAKY_OFFSET 0 +#define RTL8367C_IPMCAST_VLAN_LEAKY_MASK 0x7FF + +#define RTL8367C_REG_IPMCAST_PORTISO_LEAKY 0x08c7 +#define RTL8367C_IPMCAST_PORTISO_LEAKY_OFFSET 0 +#define RTL8367C_IPMCAST_PORTISO_LEAKY_MASK 0x7FF + +#define RTL8367C_REG_PORT_SECURITY_CTRL 0x08c8 +#define RTL8367C_UNKNOWN_UNICAST_DA_BEHAVE_OFFSET 6 +#define RTL8367C_UNKNOWN_UNICAST_DA_BEHAVE_MASK 0xC0 +#define RTL8367C_LUT_LEARN_OVER_ACT_OFFSET 4 +#define RTL8367C_LUT_LEARN_OVER_ACT_MASK 0x30 +#define RTL8367C_UNMATCHED_SA_BEHAVE_OFFSET 2 +#define RTL8367C_UNMATCHED_SA_BEHAVE_MASK 0xC +#define RTL8367C_UNKNOWN_SA_BEHAVE_OFFSET 0 +#define RTL8367C_UNKNOWN_SA_BEHAVE_MASK 0x3 + +#define RTL8367C_REG_UNKNOWN_IPV4_MULTICAST_CTRL0 0x08c9 +#define RTL8367C_PORT7_UNKNOWN_IP4_MCAST_OFFSET 14 +#define RTL8367C_PORT7_UNKNOWN_IP4_MCAST_MASK 0xC000 +#define RTL8367C_PORT6_UNKNOWN_IP4_MCAST_OFFSET 12 +#define RTL8367C_PORT6_UNKNOWN_IP4_MCAST_MASK 0x3000 +#define RTL8367C_PORT5_UNKNOWN_IP4_MCAST_OFFSET 10 +#define RTL8367C_PORT5_UNKNOWN_IP4_MCAST_MASK 0xC00 +#define RTL8367C_PORT4_UNKNOWN_IP4_MCAST_OFFSET 8 +#define RTL8367C_PORT4_UNKNOWN_IP4_MCAST_MASK 0x300 +#define RTL8367C_PORT3_UNKNOWN_IP4_MCAST_OFFSET 6 +#define RTL8367C_PORT3_UNKNOWN_IP4_MCAST_MASK 0xC0 +#define RTL8367C_PORT2_UNKNOWN_IP4_MCAST_OFFSET 4 +#define RTL8367C_PORT2_UNKNOWN_IP4_MCAST_MASK 0x30 +#define RTL8367C_PORT1_UNKNOWN_IP4_MCAST_OFFSET 2 +#define RTL8367C_PORT1_UNKNOWN_IP4_MCAST_MASK 0xC +#define RTL8367C_PORT0_UNKNOWN_IP4_MCAST_OFFSET 0 +#define RTL8367C_PORT0_UNKNOWN_IP4_MCAST_MASK 0x3 + +#define RTL8367C_REG_UNKNOWN_IPV4_MULTICAST_CTRL1 0x08ca +#define RTL8367C_PORT10_UNKNOWN_IP4_MCAST_OFFSET 4 +#define RTL8367C_PORT10_UNKNOWN_IP4_MCAST_MASK 0x30 +#define RTL8367C_PORT9_UNKNOWN_IP4_MCAST_OFFSET 2 +#define RTL8367C_PORT9_UNKNOWN_IP4_MCAST_MASK 0xC +#define RTL8367C_PORT8_UNKNOWN_IP4_MCAST_OFFSET 0 +#define RTL8367C_PORT8_UNKNOWN_IP4_MCAST_MASK 0x3 + +#define RTL8367C_REG_UNKNOWN_IPV6_MULTICAST_CTRL0 0x08cb +#define RTL8367C_PORT7_UNKNOWN_IP6_MCAST_OFFSET 14 +#define RTL8367C_PORT7_UNKNOWN_IP6_MCAST_MASK 0xC000 +#define RTL8367C_PORT6_UNKNOWN_IP6_MCAST_OFFSET 12 +#define RTL8367C_PORT6_UNKNOWN_IP6_MCAST_MASK 0x3000 +#define RTL8367C_PORT5_UNKNOWN_IP6_MCAST_OFFSET 10 +#define RTL8367C_PORT5_UNKNOWN_IP6_MCAST_MASK 0xC00 +#define RTL8367C_PORT4_UNKNOWN_IP6_MCAST_OFFSET 8 +#define RTL8367C_PORT4_UNKNOWN_IP6_MCAST_MASK 0x300 +#define RTL8367C_PORT3_UNKNOWN_IP6_MCAST_OFFSET 6 +#define RTL8367C_PORT3_UNKNOWN_IP6_MCAST_MASK 0xC0 +#define RTL8367C_PORT2_UNKNOWN_IP6_MCAST_OFFSET 4 +#define RTL8367C_PORT2_UNKNOWN_IP6_MCAST_MASK 0x30 +#define RTL8367C_PORT1_UNKNOWN_IP6_MCAST_OFFSET 2 +#define RTL8367C_PORT1_UNKNOWN_IP6_MCAST_MASK 0xC +#define RTL8367C_PORT0_UNKNOWN_IP6_MCAST_OFFSET 0 +#define RTL8367C_PORT0_UNKNOWN_IP6_MCAST_MASK 0x3 + +#define RTL8367C_REG_UNKNOWN_IPV6_MULTICAST_CTRL1 0x08cc +#define RTL8367C_PORT10_UNKNOWN_IP6_MCAST_OFFSET 4 +#define RTL8367C_PORT10_UNKNOWN_IP6_MCAST_MASK 0x30 +#define RTL8367C_PORT9_UNKNOWN_IP6_MCAST_OFFSET 2 +#define RTL8367C_PORT9_UNKNOWN_IP6_MCAST_MASK 0xC +#define RTL8367C_PORT8_UNKNOWN_IP6_MCAST_OFFSET 0 +#define RTL8367C_PORT8_UNKNOWN_IP6_MCAST_MASK 0x3 + +#define RTL8367C_REG_UNKNOWN_L2_MULTICAST_CTRL0 0x08cd +#define RTL8367C_PORT7_UNKNOWN_L2_MCAST_OFFSET 14 +#define RTL8367C_PORT7_UNKNOWN_L2_MCAST_MASK 0xC000 +#define RTL8367C_PORT6_UNKNOWN_L2_MCAST_OFFSET 12 +#define RTL8367C_PORT6_UNKNOWN_L2_MCAST_MASK 0x3000 +#define RTL8367C_PORT5_UNKNOWN_L2_MCAST_OFFSET 10 +#define RTL8367C_PORT5_UNKNOWN_L2_MCAST_MASK 0xC00 +#define RTL8367C_PORT4_UNKNOWN_L2_MCAST_OFFSET 8 +#define RTL8367C_PORT4_UNKNOWN_L2_MCAST_MASK 0x300 +#define RTL8367C_PORT3_UNKNOWN_L2_MCAST_OFFSET 6 +#define RTL8367C_PORT3_UNKNOWN_L2_MCAST_MASK 0xC0 +#define RTL8367C_PORT2_UNKNOWN_L2_MCAST_OFFSET 4 +#define RTL8367C_PORT2_UNKNOWN_L2_MCAST_MASK 0x30 +#define RTL8367C_PORT1_UNKNOWN_L2_MCAST_OFFSET 2 +#define RTL8367C_PORT1_UNKNOWN_L2_MCAST_MASK 0xC +#define RTL8367C_PORT0_UNKNOWN_L2_MCAST_OFFSET 0 +#define RTL8367C_PORT0_UNKNOWN_L2_MCAST_MASK 0x3 + +#define RTL8367C_REG_PORT_TRUNK_DROP_CTRL 0x08ce +#define RTL8367C_PORT_TRUNK_DROP_CTRL_OFFSET 0 +#define RTL8367C_PORT_TRUNK_DROP_CTRL_MASK 0x1 + +#define RTL8367C_REG_PORT_TRUNK_CTRL 0x08cf +#define RTL8367C_PORT_TRUNK_DUMB_OFFSET 8 +#define RTL8367C_PORT_TRUNK_DUMB_MASK 0x100 +#define RTL8367C_PORT_TRUNK_FLOOD_OFFSET 7 +#define RTL8367C_PORT_TRUNK_FLOOD_MASK 0x80 +#define RTL8367C_DPORT_HASH_OFFSET 6 +#define RTL8367C_DPORT_HASH_MASK 0x40 +#define RTL8367C_SPORT_HASH_OFFSET 5 +#define RTL8367C_SPORT_HASH_MASK 0x20 +#define RTL8367C_DIP_HASH_OFFSET 4 +#define RTL8367C_DIP_HASH_MASK 0x10 +#define RTL8367C_SIP_HASH_OFFSET 3 +#define RTL8367C_SIP_HASH_MASK 0x8 +#define RTL8367C_DMAC_HASH_OFFSET 2 +#define RTL8367C_DMAC_HASH_MASK 0x4 +#define RTL8367C_SMAC_HASH_OFFSET 1 +#define RTL8367C_SMAC_HASH_MASK 0x2 +#define RTL8367C_SPA_HASH_OFFSET 0 +#define RTL8367C_SPA_HASH_MASK 0x1 + +#define RTL8367C_REG_PORT_TRUNK_GROUP_MASK 0x08d0 +#define RTL8367C_PORT_TRUNK_GROUP2_MASK_OFFSET 8 +#define RTL8367C_PORT_TRUNK_GROUP2_MASK_MASK 0x300 +#define RTL8367C_PORT_TRUNK_GROUP1_MASK_OFFSET 4 +#define RTL8367C_PORT_TRUNK_GROUP1_MASK_MASK 0xF0 +#define RTL8367C_PORT_TRUNK_GROUP0_MASK_OFFSET 0 +#define RTL8367C_PORT_TRUNK_GROUP0_MASK_MASK 0xF + +#define RTL8367C_REG_PORT_TRUNK_FLOWCTRL 0x08d1 +#define RTL8367C_EN_FLOWCTRL_TG2_OFFSET 2 +#define RTL8367C_EN_FLOWCTRL_TG2_MASK 0x4 +#define RTL8367C_EN_FLOWCTRL_TG1_OFFSET 1 +#define RTL8367C_EN_FLOWCTRL_TG1_MASK 0x2 +#define RTL8367C_EN_FLOWCTRL_TG0_OFFSET 0 +#define RTL8367C_EN_FLOWCTRL_TG0_MASK 0x1 + +#define RTL8367C_REG_PORT_TRUNK_HASH_MAPPING_CTRL0 0x08d2 +#define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL0_HASH7_OFFSET 14 +#define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL0_HASH7_MASK 0xC000 +#define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL0_HASH6_OFFSET 12 +#define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL0_HASH6_MASK 0x3000 +#define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL0_HASH5_OFFSET 10 +#define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL0_HASH5_MASK 0xC00 +#define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL0_HASH4_OFFSET 8 +#define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL0_HASH4_MASK 0x300 +#define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL0_HASH3_OFFSET 6 +#define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL0_HASH3_MASK 0xC0 +#define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL0_HASH2_OFFSET 4 +#define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL0_HASH2_MASK 0x30 +#define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL0_HASH1_OFFSET 2 +#define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL0_HASH1_MASK 0xC +#define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL0_HASH0_OFFSET 0 +#define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL0_HASH0_MASK 0x3 + +#define RTL8367C_REG_PORT_TRUNK_HASH_MAPPING_CTRL1 0x08d3 +#define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL1_HASH15_OFFSET 14 +#define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL1_HASH15_MASK 0xC000 +#define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL1_HASH14_OFFSET 12 +#define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL1_HASH14_MASK 0x3000 +#define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL1_HASH13_OFFSET 10 +#define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL1_HASH13_MASK 0xC00 +#define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL1_HASH12_OFFSET 8 +#define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL1_HASH12_MASK 0x300 +#define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL1_HASH11_OFFSET 6 +#define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL1_HASH11_MASK 0xC0 +#define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL1_HASH10_OFFSET 4 +#define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL1_HASH10_MASK 0x30 +#define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL1_HASH9_OFFSET 2 +#define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL1_HASH9_MASK 0xC +#define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL1_HASH8_OFFSET 0 +#define RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL1_HASH8_MASK 0x3 + +#define RTL8367C_REG_DOS_CFG 0x08d4 +#define RTL8367C_DROP_ICMPFRAGMENT_OFFSET 9 +#define RTL8367C_DROP_ICMPFRAGMENT_MASK 0x200 +#define RTL8367C_DROP_TCPFRAGERROR_OFFSET 8 +#define RTL8367C_DROP_TCPFRAGERROR_MASK 0x100 +#define RTL8367C_DROP_TCPSHORTHDR_OFFSET 7 +#define RTL8367C_DROP_TCPSHORTHDR_MASK 0x80 +#define RTL8367C_DROP_SYN1024_OFFSET 6 +#define RTL8367C_DROP_SYN1024_MASK 0x40 +#define RTL8367C_DROP_NULLSCAN_OFFSET 5 +#define RTL8367C_DROP_NULLSCAN_MASK 0x20 +#define RTL8367C_DROP_XMASCAN_OFFSET 4 +#define RTL8367C_DROP_XMASCAN_MASK 0x10 +#define RTL8367C_DROP_SYNFINSCAN_OFFSET 3 +#define RTL8367C_DROP_SYNFINSCAN_MASK 0x8 +#define RTL8367C_DROP_BLATATTACKS_OFFSET 2 +#define RTL8367C_DROP_BLATATTACKS_MASK 0x4 +#define RTL8367C_DROP_LANDATTACKS_OFFSET 1 +#define RTL8367C_DROP_LANDATTACKS_MASK 0x2 +#define RTL8367C_DROP_DAEQSA_OFFSET 0 +#define RTL8367C_DROP_DAEQSA_MASK 0x1 + +#define RTL8367C_REG_UNKNOWN_L2_MULTICAST_CTRL1 0x08d5 +#define RTL8367C_PORT10_UNKNOWN_L2_MCAST_OFFSET 4 +#define RTL8367C_PORT10_UNKNOWN_L2_MCAST_MASK 0x30 +#define RTL8367C_PORT9_UNKNOWN_L2_MCAST_OFFSET 2 +#define RTL8367C_PORT9_UNKNOWN_L2_MCAST_MASK 0xC +#define RTL8367C_PORT8_UNKNOWN_L2_MCAST_OFFSET 0 +#define RTL8367C_PORT8_UNKNOWN_L2_MCAST_MASK 0x3 + +#define RTL8367C_REG_VLAN_EGRESS_KEEP_CTRL4 0x08d6 +#define RTL8367C_PORT9_VLAN_KEEP_MASK_OFFSET 8 +#define RTL8367C_PORT9_VLAN_KEEP_MASK_MASK 0xFF00 +#define RTL8367C_PORT8_VLAN_KEEP_MASK_OFFSET 0 +#define RTL8367C_PORT8_VLAN_KEEP_MASK_MASK 0xFF + +#define RTL8367C_REG_VLAN_EGRESS_KEEP_CTRL5 0x08d7 +#define RTL8367C_VLAN_EGRESS_KEEP_CTRL5_OFFSET 0 +#define RTL8367C_VLAN_EGRESS_KEEP_CTRL5_MASK 0xFF + +#define RTL8367C_REG_VLAN_EGRESS_KEEP_CTRL0_EXT 0x08d8 +#define RTL8367C_PORT1_VLAN_KEEP_MASK_EXT_OFFSET 3 +#define RTL8367C_PORT1_VLAN_KEEP_MASK_EXT_MASK 0x38 +#define RTL8367C_PORT0_VLAN_KEEP_MASK_EXT_OFFSET 0 +#define RTL8367C_PORT0_VLAN_KEEP_MASK_EXT_MASK 0x7 + +#define RTL8367C_REG_VLAN_EGRESS_KEEP_CTRL1_EXT 0x08d9 +#define RTL8367C_PORT3_VLAN_KEEP_MASK_EXT_OFFSET 3 +#define RTL8367C_PORT3_VLAN_KEEP_MASK_EXT_MASK 0x38 +#define RTL8367C_PORT2_VLAN_KEEP_MASK_EXT_OFFSET 0 +#define RTL8367C_PORT2_VLAN_KEEP_MASK_EXT_MASK 0x7 + +#define RTL8367C_REG_VLAN_EGRESS_KEEP_CTRL2_EXT 0x08da +#define RTL8367C_PORT5_VLAN_KEEP_MASK_EXT_OFFSET 3 +#define RTL8367C_PORT5_VLAN_KEEP_MASK_EXT_MASK 0x38 +#define RTL8367C_PORT4_VLAN_KEEP_MASK_EXT_OFFSET 0 +#define RTL8367C_PORT4_VLAN_KEEP_MASK_EXT_MASK 0x7 + +#define RTL8367C_REG_VLAN_EGRESS_KEEP_CTRL3_EXT 0x08db +#define RTL8367C_PORT7_VLAN_KEEP_MASK_EXT_OFFSET 3 +#define RTL8367C_PORT7_VLAN_KEEP_MASK_EXT_MASK 0x38 +#define RTL8367C_PORT6_VLAN_KEEP_MASK_EXT_OFFSET 0 +#define RTL8367C_PORT6_VLAN_KEEP_MASK_EXT_MASK 0x7 + +#define RTL8367C_REG_VLAN_EGRESS_KEEP_CTRL4_EXT 0x08dc +#define RTL8367C_PORT9_VLAN_KEEP_MASK_EXT_OFFSET 3 +#define RTL8367C_PORT9_VLAN_KEEP_MASK_EXT_MASK 0x38 +#define RTL8367C_PORT8_VLAN_KEEP_MASK_EXT_OFFSET 0 +#define RTL8367C_PORT8_VLAN_KEEP_MASK_EXT_MASK 0x7 + +#define RTL8367C_REG_VLAN_EGRESS_KEEP_CTRL5_EXT 0x08dd +#define RTL8367C_VLAN_EGRESS_KEEP_CTRL5_EXT_OFFSET 0 +#define RTL8367C_VLAN_EGRESS_KEEP_CTRL5_EXT_MASK 0x7 + +#define RTL8367C_REG_VLAN_EGRESS_TRANS_CTRL10 0x08de +#define RTL8367C_VLAN_EGRESS_TRANS_CTRL10_OFFSET 0 +#define RTL8367C_VLAN_EGRESS_TRANS_CTRL10_MASK 0x7FF + +#define RTL8367C_REG_FPGA_VER_CEN 0x08e0 + +#define RTL8367C_REG_FPGA_TIME_CEN 0x08e1 + +#define RTL8367C_REG_FPGA_DATE_CEN 0x08e2 + +#define RTL8367C_REG_QOS_PORT_QUEUE_NUMBER_CTRL0 0x0900 +#define RTL8367C_PORT3_NUMBER_OFFSET 12 +#define RTL8367C_PORT3_NUMBER_MASK 0x7000 +#define RTL8367C_PORT2_NUMBER_OFFSET 8 +#define RTL8367C_PORT2_NUMBER_MASK 0x700 +#define RTL8367C_PORT1_NUMBER_OFFSET 4 +#define RTL8367C_PORT1_NUMBER_MASK 0x70 +#define RTL8367C_PORT0_NUMBER_OFFSET 0 +#define RTL8367C_PORT0_NUMBER_MASK 0x7 + +#define RTL8367C_REG_QOS_PORT_QUEUE_NUMBER_CTRL1 0x0901 +#define RTL8367C_PORT7_NUMBER_OFFSET 12 +#define RTL8367C_PORT7_NUMBER_MASK 0x7000 +#define RTL8367C_PORT6_NUMBER_OFFSET 8 +#define RTL8367C_PORT6_NUMBER_MASK 0x700 +#define RTL8367C_PORT5_NUMBER_OFFSET 4 +#define RTL8367C_PORT5_NUMBER_MASK 0x70 +#define RTL8367C_PORT4_NUMBER_OFFSET 0 +#define RTL8367C_PORT4_NUMBER_MASK 0x7 + +#define RTL8367C_REG_QOS_PORT_QUEUE_NUMBER_CTRL2 0x0902 +#define RTL8367C_PORT10_NUMBER_OFFSET 8 +#define RTL8367C_PORT10_NUMBER_MASK 0x700 +#define RTL8367C_PORT9_NUMBER_OFFSET 4 +#define RTL8367C_PORT9_NUMBER_MASK 0x70 +#define RTL8367C_PORT8_NUMBER_OFFSET 0 +#define RTL8367C_PORT8_NUMBER_MASK 0x7 + +#define RTL8367C_REG_QOS_1Q_PRIORITY_TO_QID_CTRL0 0x0904 +#define RTL8367C_QOS_1Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_OFFSET 12 +#define RTL8367C_QOS_1Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_MASK 0x7000 +#define RTL8367C_QOS_1Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_OFFSET 8 +#define RTL8367C_QOS_1Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_MASK 0x700 +#define RTL8367C_QOS_1Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_OFFSET 4 +#define RTL8367C_QOS_1Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_MASK 0x70 +#define RTL8367C_QOS_1Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_OFFSET 0 +#define RTL8367C_QOS_1Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_MASK 0x7 + +#define RTL8367C_REG_QOS_1Q_PRIORITY_TO_QID_CTRL1 0x0905 +#define RTL8367C_QOS_1Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_OFFSET 12 +#define RTL8367C_QOS_1Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_MASK 0x7000 +#define RTL8367C_QOS_1Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_OFFSET 8 +#define RTL8367C_QOS_1Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_MASK 0x700 +#define RTL8367C_QOS_1Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_OFFSET 4 +#define RTL8367C_QOS_1Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_MASK 0x70 +#define RTL8367C_QOS_1Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_OFFSET 0 +#define RTL8367C_QOS_1Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_MASK 0x7 + +#define RTL8367C_REG_QOS_2Q_PRIORITY_TO_QID_CTRL0 0x0906 +#define RTL8367C_QOS_2Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_OFFSET 12 +#define RTL8367C_QOS_2Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_MASK 0x7000 +#define RTL8367C_QOS_2Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_OFFSET 8 +#define RTL8367C_QOS_2Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_MASK 0x700 +#define RTL8367C_QOS_2Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_OFFSET 4 +#define RTL8367C_QOS_2Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_MASK 0x70 +#define RTL8367C_QOS_2Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_OFFSET 0 +#define RTL8367C_QOS_2Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_MASK 0x7 + +#define RTL8367C_REG_QOS_2Q_PRIORITY_TO_QID_CTRL1 0x0907 +#define RTL8367C_QOS_2Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_OFFSET 12 +#define RTL8367C_QOS_2Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_MASK 0x7000 +#define RTL8367C_QOS_2Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_OFFSET 8 +#define RTL8367C_QOS_2Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_MASK 0x700 +#define RTL8367C_QOS_2Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_OFFSET 4 +#define RTL8367C_QOS_2Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_MASK 0x70 +#define RTL8367C_QOS_2Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_OFFSET 0 +#define RTL8367C_QOS_2Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_MASK 0x7 + +#define RTL8367C_REG_QOS_3Q_PRIORITY_TO_QID_CTRL0 0x0908 +#define RTL8367C_QOS_3Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_OFFSET 12 +#define RTL8367C_QOS_3Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_MASK 0x7000 +#define RTL8367C_QOS_3Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_OFFSET 8 +#define RTL8367C_QOS_3Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_MASK 0x700 +#define RTL8367C_QOS_3Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_OFFSET 4 +#define RTL8367C_QOS_3Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_MASK 0x70 +#define RTL8367C_QOS_3Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_OFFSET 0 +#define RTL8367C_QOS_3Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_MASK 0x7 + +#define RTL8367C_REG_QOS_3Q_PRIORITY_TO_QID_CTRL1 0x0909 +#define RTL8367C_QOS_3Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_OFFSET 12 +#define RTL8367C_QOS_3Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_MASK 0x7000 +#define RTL8367C_QOS_3Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_OFFSET 8 +#define RTL8367C_QOS_3Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_MASK 0x700 +#define RTL8367C_QOS_3Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_OFFSET 4 +#define RTL8367C_QOS_3Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_MASK 0x70 +#define RTL8367C_QOS_3Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_OFFSET 0 +#define RTL8367C_QOS_3Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_MASK 0x7 + +#define RTL8367C_REG_QOS_4Q_PRIORITY_TO_QID_CTRL0 0x090a +#define RTL8367C_QOS_4Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_OFFSET 12 +#define RTL8367C_QOS_4Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_MASK 0x7000 +#define RTL8367C_QOS_4Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_OFFSET 8 +#define RTL8367C_QOS_4Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_MASK 0x700 +#define RTL8367C_QOS_4Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_OFFSET 4 +#define RTL8367C_QOS_4Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_MASK 0x70 +#define RTL8367C_QOS_4Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_OFFSET 0 +#define RTL8367C_QOS_4Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_MASK 0x7 + +#define RTL8367C_REG_QOS_4Q_PRIORITY_TO_QID_CTRL1 0x090b +#define RTL8367C_QOS_4Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_OFFSET 12 +#define RTL8367C_QOS_4Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_MASK 0x7000 +#define RTL8367C_QOS_4Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_OFFSET 8 +#define RTL8367C_QOS_4Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_MASK 0x700 +#define RTL8367C_QOS_4Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_OFFSET 4 +#define RTL8367C_QOS_4Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_MASK 0x70 +#define RTL8367C_QOS_4Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_OFFSET 0 +#define RTL8367C_QOS_4Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_MASK 0x7 + +#define RTL8367C_REG_QOS_5Q_PRIORITY_TO_QID_CTRL0 0x090c +#define RTL8367C_QOS_5Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_OFFSET 12 +#define RTL8367C_QOS_5Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_MASK 0x7000 +#define RTL8367C_QOS_5Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_OFFSET 8 +#define RTL8367C_QOS_5Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_MASK 0x700 +#define RTL8367C_QOS_5Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_OFFSET 4 +#define RTL8367C_QOS_5Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_MASK 0x70 +#define RTL8367C_QOS_5Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_OFFSET 0 +#define RTL8367C_QOS_5Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_MASK 0x7 + +#define RTL8367C_REG_QOS_5Q_PRIORITY_TO_QID_CTRL1 0x090d +#define RTL8367C_QOS_5Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_OFFSET 12 +#define RTL8367C_QOS_5Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_MASK 0x7000 +#define RTL8367C_QOS_5Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_OFFSET 8 +#define RTL8367C_QOS_5Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_MASK 0x700 +#define RTL8367C_QOS_5Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_OFFSET 4 +#define RTL8367C_QOS_5Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_MASK 0x70 +#define RTL8367C_QOS_5Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_OFFSET 0 +#define RTL8367C_QOS_5Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_MASK 0x7 + +#define RTL8367C_REG_QOS_6Q_PRIORITY_TO_QID_CTRL0 0x090e +#define RTL8367C_QOS_6Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_OFFSET 12 +#define RTL8367C_QOS_6Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_MASK 0x7000 +#define RTL8367C_QOS_6Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_OFFSET 8 +#define RTL8367C_QOS_6Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_MASK 0x700 +#define RTL8367C_QOS_6Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_OFFSET 4 +#define RTL8367C_QOS_6Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_MASK 0x70 +#define RTL8367C_QOS_6Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_OFFSET 0 +#define RTL8367C_QOS_6Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_MASK 0x7 + +#define RTL8367C_REG_QOS_6Q_PRIORITY_TO_QID_CTRL1 0x090f +#define RTL8367C_QOS_6Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_OFFSET 12 +#define RTL8367C_QOS_6Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_MASK 0x7000 +#define RTL8367C_QOS_6Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_OFFSET 8 +#define RTL8367C_QOS_6Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_MASK 0x700 +#define RTL8367C_QOS_6Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_OFFSET 4 +#define RTL8367C_QOS_6Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_MASK 0x70 +#define RTL8367C_QOS_6Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_OFFSET 0 +#define RTL8367C_QOS_6Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_MASK 0x7 + +#define RTL8367C_REG_QOS_7Q_PRIORITY_TO_QID_CTRL0 0x0910 +#define RTL8367C_QOS_7Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_OFFSET 12 +#define RTL8367C_QOS_7Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_MASK 0x7000 +#define RTL8367C_QOS_7Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_OFFSET 8 +#define RTL8367C_QOS_7Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_MASK 0x700 +#define RTL8367C_QOS_7Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_OFFSET 4 +#define RTL8367C_QOS_7Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_MASK 0x70 +#define RTL8367C_QOS_7Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_OFFSET 0 +#define RTL8367C_QOS_7Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_MASK 0x7 + +#define RTL8367C_REG_QOS_7Q_PRIORITY_TO_QID_CTRL1 0x0911 +#define RTL8367C_QOS_7Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_OFFSET 12 +#define RTL8367C_QOS_7Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_MASK 0x7000 +#define RTL8367C_QOS_7Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_OFFSET 8 +#define RTL8367C_QOS_7Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_MASK 0x700 +#define RTL8367C_QOS_7Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_OFFSET 4 +#define RTL8367C_QOS_7Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_MASK 0x70 +#define RTL8367C_QOS_7Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_OFFSET 0 +#define RTL8367C_QOS_7Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_MASK 0x7 + +#define RTL8367C_REG_QOS_8Q_PRIORITY_TO_QID_CTRL0 0x0912 +#define RTL8367C_QOS_8Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_OFFSET 12 +#define RTL8367C_QOS_8Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_MASK 0x7000 +#define RTL8367C_QOS_8Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_OFFSET 8 +#define RTL8367C_QOS_8Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_MASK 0x700 +#define RTL8367C_QOS_8Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_OFFSET 4 +#define RTL8367C_QOS_8Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_MASK 0x70 +#define RTL8367C_QOS_8Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_OFFSET 0 +#define RTL8367C_QOS_8Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_MASK 0x7 + +#define RTL8367C_REG_QOS_8Q_PRIORITY_TO_QID_CTRL1 0x0913 +#define RTL8367C_QOS_8Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_OFFSET 12 +#define RTL8367C_QOS_8Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_MASK 0x7000 +#define RTL8367C_QOS_8Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_OFFSET 8 +#define RTL8367C_QOS_8Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_MASK 0x700 +#define RTL8367C_QOS_8Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_OFFSET 4 +#define RTL8367C_QOS_8Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_MASK 0x70 +#define RTL8367C_QOS_8Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_OFFSET 0 +#define RTL8367C_QOS_8Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_MASK 0x7 + +#define RTL8367C_REG_HIGHPRI_INDICATOR 0x0915 +#define RTL8367C_PORT10_INDICATOR_OFFSET 10 +#define RTL8367C_PORT10_INDICATOR_MASK 0x400 +#define RTL8367C_PORT9_INDICATOR_OFFSET 9 +#define RTL8367C_PORT9_INDICATOR_MASK 0x200 +#define RTL8367C_PORT8_INDICATOR_OFFSET 8 +#define RTL8367C_PORT8_INDICATOR_MASK 0x100 +#define RTL8367C_PORT7_INDICATOR_OFFSET 7 +#define RTL8367C_PORT7_INDICATOR_MASK 0x80 +#define RTL8367C_PORT6_INDICATOR_OFFSET 6 +#define RTL8367C_PORT6_INDICATOR_MASK 0x40 +#define RTL8367C_PORT5_INDICATOR_OFFSET 5 +#define RTL8367C_PORT5_INDICATOR_MASK 0x20 +#define RTL8367C_PORT4_INDICATOR_OFFSET 4 +#define RTL8367C_PORT4_INDICATOR_MASK 0x10 +#define RTL8367C_PORT3_INDICATOR_OFFSET 3 +#define RTL8367C_PORT3_INDICATOR_MASK 0x8 +#define RTL8367C_PORT2_INDICATOR_OFFSET 2 +#define RTL8367C_PORT2_INDICATOR_MASK 0x4 +#define RTL8367C_PORT1_INDICATOR_OFFSET 1 +#define RTL8367C_PORT1_INDICATOR_MASK 0x2 +#define RTL8367C_PORT0_INDICATOR_OFFSET 0 +#define RTL8367C_PORT0_INDICATOR_MASK 0x1 + +#define RTL8367C_REG_HIGHPRI_CFG 0x0916 +#define RTL8367C_HIGHPRI_CFG_OFFSET 0 +#define RTL8367C_HIGHPRI_CFG_MASK 0xFF + +#define RTL8367C_REG_PORT_DEBUG_INFO_CTRL0 0x0917 +#define RTL8367C_PORT1_DEBUG_INFO_OFFSET 8 +#define RTL8367C_PORT1_DEBUG_INFO_MASK 0xFF00 +#define RTL8367C_PORT0_DEBUG_INFO_OFFSET 0 +#define RTL8367C_PORT0_DEBUG_INFO_MASK 0xFF + +#define RTL8367C_REG_PORT_DEBUG_INFO_CTRL1 0x0918 +#define RTL8367C_PORT3_DEBUG_INFO_OFFSET 8 +#define RTL8367C_PORT3_DEBUG_INFO_MASK 0xFF00 +#define RTL8367C_PORT2_DEBUG_INFO_OFFSET 0 +#define RTL8367C_PORT2_DEBUG_INFO_MASK 0xFF + +#define RTL8367C_REG_PORT_DEBUG_INFO_CTRL2 0x0919 +#define RTL8367C_PORT5_DEBUG_INFO_OFFSET 8 +#define RTL8367C_PORT5_DEBUG_INFO_MASK 0xFF00 +#define RTL8367C_PORT4_DEBUG_INFO_OFFSET 0 +#define RTL8367C_PORT4_DEBUG_INFO_MASK 0xFF + +#define RTL8367C_REG_PORT_DEBUG_INFO_CTRL3 0x091a +#define RTL8367C_PORT7_DEBUG_INFO_OFFSET 8 +#define RTL8367C_PORT7_DEBUG_INFO_MASK 0xFF00 +#define RTL8367C_PORT6_DEBUG_INFO_OFFSET 0 +#define RTL8367C_PORT6_DEBUG_INFO_MASK 0xFF + +#define RTL8367C_REG_PORT_DEBUG_INFO_CTRL4 0x091b +#define RTL8367C_PORT9_DEBUG_INFO_OFFSET 8 +#define RTL8367C_PORT9_DEBUG_INFO_MASK 0xFF00 +#define RTL8367C_PORT8_DEBUG_INFO_OFFSET 0 +#define RTL8367C_PORT8_DEBUG_INFO_MASK 0xFF + +#define RTL8367C_REG_PORT_DEBUG_INFO_CTRL5 0x091c +#define RTL8367C_PORT10_DEBUG_INFO_OFFSET 0 +#define RTL8367C_PORT10_DEBUG_INFO_MASK 0xFF + +#define RTL8367C_REG_PORT_DEBUG_INFO_CTRL6 0x091d +#define RTL8367C_PORT7_DEBUG_INDICATOR_OFFSET 14 +#define RTL8367C_PORT7_DEBUG_INDICATOR_MASK 0xC000 +#define RTL8367C_PORT6_DEBUG_INDICATOR_OFFSET 12 +#define RTL8367C_PORT6_DEBUG_INDICATOR_MASK 0x3000 +#define RTL8367C_PORT5_DEBUG_INDICATOR_OFFSET 10 +#define RTL8367C_PORT5_DEBUG_INDICATOR_MASK 0xC00 +#define RTL8367C_PORT4_DEBUG_INDICATOR_OFFSET 8 +#define RTL8367C_PORT4_DEBUG_INDICATOR_MASK 0x300 +#define RTL8367C_PORT3_DEBUG_INDICATOR_OFFSET 6 +#define RTL8367C_PORT3_DEBUG_INDICATOR_MASK 0xC0 +#define RTL8367C_PORT2_DEBUG_INDICATOR_OFFSET 4 +#define RTL8367C_PORT2_DEBUG_INDICATOR_MASK 0x30 +#define RTL8367C_PORT1_DEBUG_INDICATOR_OFFSET 2 +#define RTL8367C_PORT1_DEBUG_INDICATOR_MASK 0xC +#define RTL8367C_PORT0_DEBUG_INDICATOR_OFFSET 0 +#define RTL8367C_PORT0_DEBUG_INDICATOR_MASK 0x3 + +#define RTL8367C_REG_PORT_DEBUG_INFO_CTRL7 0x091e +#define RTL8367C_PORT10_DEBUG_INDICATOR_OFFSET 4 +#define RTL8367C_PORT10_DEBUG_INDICATOR_MASK 0x30 +#define RTL8367C_PORT9_DEBUG_INDICATOR_OFFSET 2 +#define RTL8367C_PORT9_DEBUG_INDICATOR_MASK 0xC +#define RTL8367C_PORT8_DEBUG_INDICATOR_OFFSET 0 +#define RTL8367C_PORT8_DEBUG_INDICATOR_MASK 0x3 + +#define RTL8367C_REG_FLOWCRTL_EGRESS_QUEUE_ENABLE_CTRL0 0x0930 +#define RTL8367C_PORT1_QUEUE_MASK_OFFSET 8 +#define RTL8367C_PORT1_QUEUE_MASK_MASK 0xFF00 +#define RTL8367C_PORT0_QUEUE_MASK_OFFSET 0 +#define RTL8367C_PORT0_QUEUE_MASK_MASK 0xFF + +#define RTL8367C_REG_FLOWCRTL_EGRESS_QUEUE_ENABLE_CTRL1 0x0931 +#define RTL8367C_PORT3_QUEUE_MASK_OFFSET 8 +#define RTL8367C_PORT3_QUEUE_MASK_MASK 0xFF00 +#define RTL8367C_PORT2_QUEUE_MASK_OFFSET 0 +#define RTL8367C_PORT2_QUEUE_MASK_MASK 0xFF + +#define RTL8367C_REG_FLOWCRTL_EGRESS_QUEUE_ENABLE_CTRL2 0x0932 +#define RTL8367C_PORT5_QUEUE_MASK_OFFSET 8 +#define RTL8367C_PORT5_QUEUE_MASK_MASK 0xFF00 +#define RTL8367C_PORT4_QUEUE_MASK_OFFSET 0 +#define RTL8367C_PORT4_QUEUE_MASK_MASK 0xFF + +#define RTL8367C_REG_FLOWCRTL_EGRESS_QUEUE_ENABLE_CTRL3 0x0933 +#define RTL8367C_PORT7_QUEUE_MASK_OFFSET 8 +#define RTL8367C_PORT7_QUEUE_MASK_MASK 0xFF00 +#define RTL8367C_PORT6_QUEUE_MASK_OFFSET 0 +#define RTL8367C_PORT6_QUEUE_MASK_MASK 0xFF + +#define RTL8367C_REG_FLOWCRTL_EGRESS_QUEUE_ENABLE_CTRL4 0x0934 +#define RTL8367C_PORT9_QUEUE_MASK_OFFSET 8 +#define RTL8367C_PORT9_QUEUE_MASK_MASK 0xFF00 +#define RTL8367C_PORT8_QUEUE_MASK_OFFSET 0 +#define RTL8367C_PORT8_QUEUE_MASK_MASK 0xFF + +#define RTL8367C_REG_FLOWCRTL_EGRESS_QUEUE_ENABLE_CTRL5 0x0935 +#define RTL8367C_FLOWCRTL_EGRESS_QUEUE_ENABLE_CTRL5_OFFSET 0 +#define RTL8367C_FLOWCRTL_EGRESS_QUEUE_ENABLE_CTRL5_MASK 0xFF + +#define RTL8367C_REG_FLOWCRTL_EGRESS_PORT_ENABLE 0x0938 +#define RTL8367C_FLOWCRTL_EGRESS_PORT_ENABLE_OFFSET 0 +#define RTL8367C_FLOWCRTL_EGRESS_PORT_ENABLE_MASK 0xFF + +#define RTL8367C_REG_EAV_CTRL 0x0939 +#define RTL8367C_EAV_TRAP_CPU_OFFSET 1 +#define RTL8367C_EAV_TRAP_CPU_MASK 0x2 +#define RTL8367C_EAV_TRAP_8051_OFFSET 0 +#define RTL8367C_EAV_TRAP_8051_MASK 0x1 + +#define RTL8367C_REG_UNTAG_DSCP_PRI_CFG 0x093a +#define RTL8367C_UNTAG_DSCP_PRI_CFG_OFFSET 0 +#define RTL8367C_UNTAG_DSCP_PRI_CFG_MASK 0x1 + +#define RTL8367C_REG_VLAN_EGRESS_KEEP_CTRL0 0x093b +#define RTL8367C_PORT1_VLAN_KEEP_MASK_OFFSET 8 +#define RTL8367C_PORT1_VLAN_KEEP_MASK_MASK 0xFF00 +#define RTL8367C_PORT0_VLAN_KEEP_MASK_OFFSET 0 +#define RTL8367C_PORT0_VLAN_KEEP_MASK_MASK 0xFF + +#define RTL8367C_REG_VLAN_EGRESS_KEEP_CTRL1 0x093c +#define RTL8367C_PORT3_VLAN_KEEP_MASK_OFFSET 8 +#define RTL8367C_PORT3_VLAN_KEEP_MASK_MASK 0xFF00 +#define RTL8367C_PORT2_VLAN_KEEP_MASK_OFFSET 0 +#define RTL8367C_PORT2_VLAN_KEEP_MASK_MASK 0xFF + +#define RTL8367C_REG_VLAN_EGRESS_KEEP_CTRL2 0x093d +#define RTL8367C_PORT5_VLAN_KEEP_MASK_OFFSET 8 +#define RTL8367C_PORT5_VLAN_KEEP_MASK_MASK 0xFF00 +#define RTL8367C_PORT4_VLAN_KEEP_MASK_OFFSET 0 +#define RTL8367C_PORT4_VLAN_KEEP_MASK_MASK 0xFF + +#define RTL8367C_REG_VLAN_EGRESS_KEEP_CTRL3 0x093e +#define RTL8367C_PORT7_VLAN_KEEP_MASK_OFFSET 8 +#define RTL8367C_PORT7_VLAN_KEEP_MASK_MASK 0xFF00 +#define RTL8367C_PORT6_VLAN_KEEP_MASK_OFFSET 0 +#define RTL8367C_PORT6_VLAN_KEEP_MASK_MASK 0xFF + +#define RTL8367C_REG_VLAN_TRANSPARENT_EN_CFG 0x093f +#define RTL8367C_VLAN_TRANSPARENT_EN_CFG_OFFSET 0 +#define RTL8367C_VLAN_TRANSPARENT_EN_CFG_MASK 0x1 + +#define RTL8367C_REG_IPMC_GROUP_ENTRY0_H 0x0940 +#define RTL8367C_IPMC_GROUP_ENTRY0_H_OFFSET 0 +#define RTL8367C_IPMC_GROUP_ENTRY0_H_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_ENTRY0_L 0x0941 + +#define RTL8367C_REG_IPMC_GROUP_ENTRY1_H 0x0942 +#define RTL8367C_IPMC_GROUP_ENTRY1_H_OFFSET 0 +#define RTL8367C_IPMC_GROUP_ENTRY1_H_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_ENTRY1_L 0x0943 + +#define RTL8367C_REG_IPMC_GROUP_ENTRY2_H 0x0944 +#define RTL8367C_IPMC_GROUP_ENTRY2_H_OFFSET 0 +#define RTL8367C_IPMC_GROUP_ENTRY2_H_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_ENTRY2_L 0x0945 + +#define RTL8367C_REG_IPMC_GROUP_ENTRY3_H 0x0946 +#define RTL8367C_IPMC_GROUP_ENTRY3_H_OFFSET 0 +#define RTL8367C_IPMC_GROUP_ENTRY3_H_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_ENTRY3_L 0x0947 + +#define RTL8367C_REG_IPMC_GROUP_ENTRY4_H 0x0948 +#define RTL8367C_IPMC_GROUP_ENTRY4_H_OFFSET 0 +#define RTL8367C_IPMC_GROUP_ENTRY4_H_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_ENTRY4_L 0x0949 + +#define RTL8367C_REG_IPMC_GROUP_ENTRY5_H 0x094a +#define RTL8367C_IPMC_GROUP_ENTRY5_H_OFFSET 0 +#define RTL8367C_IPMC_GROUP_ENTRY5_H_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_ENTRY5_L 0x094b + +#define RTL8367C_REG_IPMC_GROUP_ENTRY6_H 0x094c +#define RTL8367C_IPMC_GROUP_ENTRY6_H_OFFSET 0 +#define RTL8367C_IPMC_GROUP_ENTRY6_H_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_ENTRY6_L 0x094d + +#define RTL8367C_REG_IPMC_GROUP_ENTRY7_H 0x094e +#define RTL8367C_IPMC_GROUP_ENTRY7_H_OFFSET 0 +#define RTL8367C_IPMC_GROUP_ENTRY7_H_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_ENTRY7_L 0x094f + +#define RTL8367C_REG_IPMC_GROUP_ENTRY8_H 0x0950 +#define RTL8367C_IPMC_GROUP_ENTRY8_H_OFFSET 0 +#define RTL8367C_IPMC_GROUP_ENTRY8_H_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_ENTRY8_L 0x0951 + +#define RTL8367C_REG_IPMC_GROUP_ENTRY9_H 0x0952 +#define RTL8367C_IPMC_GROUP_ENTRY9_H_OFFSET 0 +#define RTL8367C_IPMC_GROUP_ENTRY9_H_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_ENTRY9_L 0x0953 + +#define RTL8367C_REG_IPMC_GROUP_ENTRY10_H 0x0954 +#define RTL8367C_IPMC_GROUP_ENTRY10_H_OFFSET 0 +#define RTL8367C_IPMC_GROUP_ENTRY10_H_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_ENTRY10_L 0x0955 + +#define RTL8367C_REG_IPMC_GROUP_ENTRY11_H 0x0956 +#define RTL8367C_IPMC_GROUP_ENTRY11_H_OFFSET 0 +#define RTL8367C_IPMC_GROUP_ENTRY11_H_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_ENTRY11_L 0x0957 + +#define RTL8367C_REG_IPMC_GROUP_ENTRY12_H 0x0958 +#define RTL8367C_IPMC_GROUP_ENTRY12_H_OFFSET 0 +#define RTL8367C_IPMC_GROUP_ENTRY12_H_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_ENTRY12_L 0x0959 + +#define RTL8367C_REG_IPMC_GROUP_ENTRY13_H 0x095a +#define RTL8367C_IPMC_GROUP_ENTRY13_H_OFFSET 0 +#define RTL8367C_IPMC_GROUP_ENTRY13_H_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_ENTRY13_L 0x095b + +#define RTL8367C_REG_IPMC_GROUP_ENTRY14_H 0x095c +#define RTL8367C_IPMC_GROUP_ENTRY14_H_OFFSET 0 +#define RTL8367C_IPMC_GROUP_ENTRY14_H_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_ENTRY14_L 0x095d + +#define RTL8367C_REG_IPMC_GROUP_ENTRY15_H 0x095e +#define RTL8367C_IPMC_GROUP_ENTRY15_H_OFFSET 0 +#define RTL8367C_IPMC_GROUP_ENTRY15_H_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_ENTRY15_L 0x095f + +#define RTL8367C_REG_IPMC_GROUP_ENTRY16_H 0x0960 +#define RTL8367C_IPMC_GROUP_ENTRY16_H_OFFSET 0 +#define RTL8367C_IPMC_GROUP_ENTRY16_H_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_ENTRY16_L 0x0961 + +#define RTL8367C_REG_IPMC_GROUP_ENTRY17_H 0x0962 +#define RTL8367C_IPMC_GROUP_ENTRY17_H_OFFSET 0 +#define RTL8367C_IPMC_GROUP_ENTRY17_H_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_ENTRY17_L 0x0963 + +#define RTL8367C_REG_IPMC_GROUP_ENTRY18_H 0x0964 +#define RTL8367C_IPMC_GROUP_ENTRY18_H_OFFSET 0 +#define RTL8367C_IPMC_GROUP_ENTRY18_H_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_ENTRY18_L 0x0965 + +#define RTL8367C_REG_IPMC_GROUP_ENTRY19_H 0x0966 +#define RTL8367C_IPMC_GROUP_ENTRY19_H_OFFSET 0 +#define RTL8367C_IPMC_GROUP_ENTRY19_H_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_ENTRY19_L 0x0967 + +#define RTL8367C_REG_IPMC_GROUP_ENTRY20_H 0x0968 +#define RTL8367C_IPMC_GROUP_ENTRY20_H_OFFSET 0 +#define RTL8367C_IPMC_GROUP_ENTRY20_H_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_ENTRY20_L 0x0969 + +#define RTL8367C_REG_IPMC_GROUP_ENTRY21_H 0x096a +#define RTL8367C_IPMC_GROUP_ENTRY21_H_OFFSET 0 +#define RTL8367C_IPMC_GROUP_ENTRY21_H_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_ENTRY21_L 0x096b + +#define RTL8367C_REG_IPMC_GROUP_ENTRY22_H 0x096c +#define RTL8367C_IPMC_GROUP_ENTRY22_H_OFFSET 0 +#define RTL8367C_IPMC_GROUP_ENTRY22_H_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_ENTRY22_L 0x096d + +#define RTL8367C_REG_IPMC_GROUP_ENTRY23_H 0x096e +#define RTL8367C_IPMC_GROUP_ENTRY23_H_OFFSET 0 +#define RTL8367C_IPMC_GROUP_ENTRY23_H_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_ENTRY23_L 0x096f + +#define RTL8367C_REG_IPMC_GROUP_ENTRY24_H 0x0970 +#define RTL8367C_IPMC_GROUP_ENTRY24_H_OFFSET 0 +#define RTL8367C_IPMC_GROUP_ENTRY24_H_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_ENTRY24_L 0x0971 + +#define RTL8367C_REG_IPMC_GROUP_ENTRY25_H 0x0972 +#define RTL8367C_IPMC_GROUP_ENTRY25_H_OFFSET 0 +#define RTL8367C_IPMC_GROUP_ENTRY25_H_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_ENTRY25_L 0x0973 + +#define RTL8367C_REG_IPMC_GROUP_ENTRY26_H 0x0974 +#define RTL8367C_IPMC_GROUP_ENTRY26_H_OFFSET 0 +#define RTL8367C_IPMC_GROUP_ENTRY26_H_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_ENTRY26_L 0x0975 + +#define RTL8367C_REG_IPMC_GROUP_ENTRY27_H 0x0976 +#define RTL8367C_IPMC_GROUP_ENTRY27_H_OFFSET 0 +#define RTL8367C_IPMC_GROUP_ENTRY27_H_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_ENTRY27_L 0x0977 + +#define RTL8367C_REG_IPMC_GROUP_ENTRY28_H 0x0978 +#define RTL8367C_IPMC_GROUP_ENTRY28_H_OFFSET 0 +#define RTL8367C_IPMC_GROUP_ENTRY28_H_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_ENTRY28_L 0x0979 + +#define RTL8367C_REG_IPMC_GROUP_ENTRY29_H 0x097a +#define RTL8367C_IPMC_GROUP_ENTRY29_H_OFFSET 0 +#define RTL8367C_IPMC_GROUP_ENTRY29_H_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_ENTRY29_L 0x097b + +#define RTL8367C_REG_IPMC_GROUP_ENTRY30_H 0x097c +#define RTL8367C_IPMC_GROUP_ENTRY30_H_OFFSET 0 +#define RTL8367C_IPMC_GROUP_ENTRY30_H_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_ENTRY30_L 0x097d + +#define RTL8367C_REG_IPMC_GROUP_ENTRY31_H 0x097e +#define RTL8367C_IPMC_GROUP_ENTRY31_H_OFFSET 0 +#define RTL8367C_IPMC_GROUP_ENTRY31_H_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_ENTRY31_L 0x097f + +#define RTL8367C_REG_IPMC_GROUP_ENTRY32_H 0x0980 +#define RTL8367C_IPMC_GROUP_ENTRY32_H_OFFSET 0 +#define RTL8367C_IPMC_GROUP_ENTRY32_H_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_ENTRY32_L 0x0981 + +#define RTL8367C_REG_IPMC_GROUP_ENTRY33_H 0x0982 +#define RTL8367C_IPMC_GROUP_ENTRY33_H_OFFSET 0 +#define RTL8367C_IPMC_GROUP_ENTRY33_H_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_ENTRY33_L 0x0983 + +#define RTL8367C_REG_IPMC_GROUP_ENTRY34_H 0x0984 +#define RTL8367C_IPMC_GROUP_ENTRY34_H_OFFSET 0 +#define RTL8367C_IPMC_GROUP_ENTRY34_H_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_ENTRY34_L 0x0985 + +#define RTL8367C_REG_IPMC_GROUP_ENTRY35_H 0x0986 +#define RTL8367C_IPMC_GROUP_ENTRY35_H_OFFSET 0 +#define RTL8367C_IPMC_GROUP_ENTRY35_H_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_ENTRY35_L 0x0987 + +#define RTL8367C_REG_IPMC_GROUP_ENTRY36_H 0x0988 +#define RTL8367C_IPMC_GROUP_ENTRY36_H_OFFSET 0 +#define RTL8367C_IPMC_GROUP_ENTRY36_H_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_ENTRY36_L 0x0989 + +#define RTL8367C_REG_IPMC_GROUP_ENTRY37_H 0x098a +#define RTL8367C_IPMC_GROUP_ENTRY37_H_OFFSET 0 +#define RTL8367C_IPMC_GROUP_ENTRY37_H_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_ENTRY37_L 0x098b + +#define RTL8367C_REG_IPMC_GROUP_ENTRY38_H 0x098c +#define RTL8367C_IPMC_GROUP_ENTRY38_H_OFFSET 0 +#define RTL8367C_IPMC_GROUP_ENTRY38_H_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_ENTRY38_L 0x098d + +#define RTL8367C_REG_IPMC_GROUP_ENTRY39_H 0x098e +#define RTL8367C_IPMC_GROUP_ENTRY39_H_OFFSET 0 +#define RTL8367C_IPMC_GROUP_ENTRY39_H_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_ENTRY39_L 0x098f + +#define RTL8367C_REG_IPMC_GROUP_ENTRY40_H 0x0990 +#define RTL8367C_IPMC_GROUP_ENTRY40_H_OFFSET 0 +#define RTL8367C_IPMC_GROUP_ENTRY40_H_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_ENTRY40_L 0x0991 + +#define RTL8367C_REG_IPMC_GROUP_ENTRY41_H 0x0992 +#define RTL8367C_IPMC_GROUP_ENTRY41_H_OFFSET 0 +#define RTL8367C_IPMC_GROUP_ENTRY41_H_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_ENTRY41_L 0x0993 + +#define RTL8367C_REG_IPMC_GROUP_ENTRY42_H 0x0994 +#define RTL8367C_IPMC_GROUP_ENTRY42_H_OFFSET 0 +#define RTL8367C_IPMC_GROUP_ENTRY42_H_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_ENTRY42_L 0x0995 + +#define RTL8367C_REG_IPMC_GROUP_ENTRY43_H 0x0996 +#define RTL8367C_IPMC_GROUP_ENTRY43_H_OFFSET 0 +#define RTL8367C_IPMC_GROUP_ENTRY43_H_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_ENTRY43_L 0x0997 + +#define RTL8367C_REG_IPMC_GROUP_ENTRY44_H 0x0998 +#define RTL8367C_IPMC_GROUP_ENTRY44_H_OFFSET 0 +#define RTL8367C_IPMC_GROUP_ENTRY44_H_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_ENTRY44_L 0x0999 + +#define RTL8367C_REG_IPMC_GROUP_ENTRY45_H 0x099a +#define RTL8367C_IPMC_GROUP_ENTRY45_H_OFFSET 0 +#define RTL8367C_IPMC_GROUP_ENTRY45_H_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_ENTRY45_L 0x099b + +#define RTL8367C_REG_IPMC_GROUP_ENTRY46_H 0x099c +#define RTL8367C_IPMC_GROUP_ENTRY46_H_OFFSET 0 +#define RTL8367C_IPMC_GROUP_ENTRY46_H_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_ENTRY46_L 0x099d + +#define RTL8367C_REG_IPMC_GROUP_ENTRY47_H 0x099e +#define RTL8367C_IPMC_GROUP_ENTRY47_H_OFFSET 0 +#define RTL8367C_IPMC_GROUP_ENTRY47_H_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_ENTRY47_L 0x099f + +#define RTL8367C_REG_IPMC_GROUP_ENTRY48_H 0x09a0 +#define RTL8367C_IPMC_GROUP_ENTRY48_H_OFFSET 0 +#define RTL8367C_IPMC_GROUP_ENTRY48_H_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_ENTRY48_L 0x09a1 + +#define RTL8367C_REG_IPMC_GROUP_ENTRY49_H 0x09a2 +#define RTL8367C_IPMC_GROUP_ENTRY49_H_OFFSET 0 +#define RTL8367C_IPMC_GROUP_ENTRY49_H_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_ENTRY49_L 0x09a3 + +#define RTL8367C_REG_IPMC_GROUP_ENTRY50_H 0x09a4 +#define RTL8367C_IPMC_GROUP_ENTRY50_H_OFFSET 0 +#define RTL8367C_IPMC_GROUP_ENTRY50_H_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_ENTRY50_L 0x09a5 + +#define RTL8367C_REG_IPMC_GROUP_ENTRY51_H 0x09a6 +#define RTL8367C_IPMC_GROUP_ENTRY51_H_OFFSET 0 +#define RTL8367C_IPMC_GROUP_ENTRY51_H_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_ENTRY51_L 0x09a7 + +#define RTL8367C_REG_IPMC_GROUP_ENTRY52_H 0x09a8 +#define RTL8367C_IPMC_GROUP_ENTRY52_H_OFFSET 0 +#define RTL8367C_IPMC_GROUP_ENTRY52_H_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_ENTRY52_L 0x09a9 + +#define RTL8367C_REG_IPMC_GROUP_ENTRY53_H 0x09aa +#define RTL8367C_IPMC_GROUP_ENTRY53_H_OFFSET 0 +#define RTL8367C_IPMC_GROUP_ENTRY53_H_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_ENTRY53_L 0x09ab + +#define RTL8367C_REG_IPMC_GROUP_ENTRY54_H 0x09ac +#define RTL8367C_IPMC_GROUP_ENTRY54_H_OFFSET 0 +#define RTL8367C_IPMC_GROUP_ENTRY54_H_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_ENTRY54_L 0x09ad + +#define RTL8367C_REG_IPMC_GROUP_ENTRY55_H 0x09ae +#define RTL8367C_IPMC_GROUP_ENTRY55_H_OFFSET 0 +#define RTL8367C_IPMC_GROUP_ENTRY55_H_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_ENTRY55_L 0x09af + +#define RTL8367C_REG_IPMC_GROUP_ENTRY56_H 0x09b0 +#define RTL8367C_IPMC_GROUP_ENTRY56_H_OFFSET 0 +#define RTL8367C_IPMC_GROUP_ENTRY56_H_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_ENTRY56_L 0x09b1 + +#define RTL8367C_REG_IPMC_GROUP_ENTRY57_H 0x09b2 +#define RTL8367C_IPMC_GROUP_ENTRY57_H_OFFSET 0 +#define RTL8367C_IPMC_GROUP_ENTRY57_H_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_ENTRY57_L 0x09b3 + +#define RTL8367C_REG_IPMC_GROUP_ENTRY58_H 0x09b4 +#define RTL8367C_IPMC_GROUP_ENTRY58_H_OFFSET 0 +#define RTL8367C_IPMC_GROUP_ENTRY58_H_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_ENTRY58_L 0x09b5 + +#define RTL8367C_REG_IPMC_GROUP_ENTRY59_H 0x09b6 +#define RTL8367C_IPMC_GROUP_ENTRY59_H_OFFSET 0 +#define RTL8367C_IPMC_GROUP_ENTRY59_H_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_ENTRY59_L 0x09b7 + +#define RTL8367C_REG_IPMC_GROUP_ENTRY60_H 0x09b8 +#define RTL8367C_IPMC_GROUP_ENTRY60_H_OFFSET 0 +#define RTL8367C_IPMC_GROUP_ENTRY60_H_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_ENTRY60_L 0x09b9 + +#define RTL8367C_REG_IPMC_GROUP_ENTRY61_H 0x09ba +#define RTL8367C_IPMC_GROUP_ENTRY61_H_OFFSET 0 +#define RTL8367C_IPMC_GROUP_ENTRY61_H_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_ENTRY61_L 0x09bb + +#define RTL8367C_REG_IPMC_GROUP_ENTRY62_H 0x09bc +#define RTL8367C_IPMC_GROUP_ENTRY62_H_OFFSET 0 +#define RTL8367C_IPMC_GROUP_ENTRY62_H_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_ENTRY62_L 0x09bd + +#define RTL8367C_REG_IPMC_GROUP_ENTRY63_H 0x09be +#define RTL8367C_IPMC_GROUP_ENTRY63_H_OFFSET 0 +#define RTL8367C_IPMC_GROUP_ENTRY63_H_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_ENTRY63_L 0x09bf + +#define RTL8367C_REG_UNKNOWN_UNICAST_DA_PORT_BEHAVE 0x09C0 +#define RTL8367C_Port7_ACTION_OFFSET 14 +#define RTL8367C_Port7_ACTION_MASK 0xC000 +#define RTL8367C_Port6_ACTION_OFFSET 12 +#define RTL8367C_Port6_ACTION_MASK 0x3000 +#define RTL8367C_Port5_ACTION_OFFSET 10 +#define RTL8367C_Port5_ACTION_MASK 0xC00 +#define RTL8367C_Port4_ACTION_OFFSET 8 +#define RTL8367C_Port4_ACTION_MASK 0x300 +#define RTL8367C_Port3_ACTION_OFFSET 6 +#define RTL8367C_Port3_ACTION_MASK 0xC0 +#define RTL8367C_Port2_ACTION_OFFSET 4 +#define RTL8367C_Port2_ACTION_MASK 0x30 +#define RTL8367C_Port1_ACTION_OFFSET 2 +#define RTL8367C_Port1_ACTION_MASK 0xC +#define RTL8367C_Port0_ACTION_OFFSET 0 +#define RTL8367C_Port0_ACTION_MASK 0x3 + +#define RTL8367C_REG_MIRROR_CTRL3 0x09C1 +#define RTL8367C_MIRROR_ACL_OVERRIDE_EN_OFFSET 2 +#define RTL8367C_MIRROR_ACL_OVERRIDE_EN_MASK 0x4 +#define RTL8367C_MIRROR_TX_OVERRIDE_EN_OFFSET 1 +#define RTL8367C_MIRROR_TX_OVERRIDE_EN_MASK 0x2 +#define RTL8367C_MIRROR_RX_OVERRIDE_EN_OFFSET 0 +#define RTL8367C_MIRROR_RX_OVERRIDE_EN_MASK 0x1 + +#define RTL8367C_REG_DPM_DUMMY02 0x09C2 + +#define RTL8367C_REG_DPM_DUMMY03 0x09C3 + +#define RTL8367C_REG_DPM_DUMMY04 0x09C4 + +#define RTL8367C_REG_DPM_DUMMY05 0x09C5 + +#define RTL8367C_REG_DPM_DUMMY06 0x09C6 + +#define RTL8367C_REG_DPM_DUMMY07 0x09C7 + +#define RTL8367C_REG_DPM_DUMMY08 0x09C8 + +#define RTL8367C_REG_DPM_DUMMY09 0x09C9 + +#define RTL8367C_REG_DPM_DUMMY10 0x09CA + +#define RTL8367C_REG_DPM_DUMMY11 0x09CB + +#define RTL8367C_REG_DPM_DUMMY12 0x09CC + +#define RTL8367C_REG_DPM_DUMMY13 0x09CD + +#define RTL8367C_REG_DPM_DUMMY14 0x09CE + +#define RTL8367C_REG_DPM_DUMMY15 0x09CF + +#define RTL8367C_REG_VLAN_EGRESS_TRANS_CTRL0 0x09D0 +#define RTL8367C_VLAN_EGRESS_TRANS_CTRL0_OFFSET 0 +#define RTL8367C_VLAN_EGRESS_TRANS_CTRL0_MASK 0x7FF + +#define RTL8367C_REG_VLAN_EGRESS_TRANS_CTRL1 0x09D1 +#define RTL8367C_VLAN_EGRESS_TRANS_CTRL1_OFFSET 0 +#define RTL8367C_VLAN_EGRESS_TRANS_CTRL1_MASK 0x7FF + +#define RTL8367C_REG_VLAN_EGRESS_TRANS_CTRL2 0x09D2 +#define RTL8367C_VLAN_EGRESS_TRANS_CTRL2_OFFSET 0 +#define RTL8367C_VLAN_EGRESS_TRANS_CTRL2_MASK 0x7FF + +#define RTL8367C_REG_VLAN_EGRESS_TRANS_CTRL3 0x09D3 +#define RTL8367C_VLAN_EGRESS_TRANS_CTRL3_OFFSET 0 +#define RTL8367C_VLAN_EGRESS_TRANS_CTRL3_MASK 0x7FF + +#define RTL8367C_REG_VLAN_EGRESS_TRANS_CTRL4 0x09D4 +#define RTL8367C_VLAN_EGRESS_TRANS_CTRL4_OFFSET 0 +#define RTL8367C_VLAN_EGRESS_TRANS_CTRL4_MASK 0x7FF + +#define RTL8367C_REG_VLAN_EGRESS_TRANS_CTRL5 0x09D5 +#define RTL8367C_VLAN_EGRESS_TRANS_CTRL5_OFFSET 0 +#define RTL8367C_VLAN_EGRESS_TRANS_CTRL5_MASK 0x7FF + +#define RTL8367C_REG_VLAN_EGRESS_TRANS_CTRL6 0x09D6 +#define RTL8367C_VLAN_EGRESS_TRANS_CTRL6_OFFSET 0 +#define RTL8367C_VLAN_EGRESS_TRANS_CTRL6_MASK 0x7FF + +#define RTL8367C_REG_VLAN_EGRESS_TRANS_CTRL7 0x09D7 +#define RTL8367C_VLAN_EGRESS_TRANS_CTRL7_OFFSET 0 +#define RTL8367C_VLAN_EGRESS_TRANS_CTRL7_MASK 0x7FF + +#define RTL8367C_REG_VLAN_EGRESS_TRANS_CTRL8 0x09D8 +#define RTL8367C_VLAN_EGRESS_TRANS_CTRL8_OFFSET 0 +#define RTL8367C_VLAN_EGRESS_TRANS_CTRL8_MASK 0x7FF + +#define RTL8367C_REG_VLAN_EGRESS_TRANS_CTRL9 0x09D9 +#define RTL8367C_VLAN_EGRESS_TRANS_CTRL9_OFFSET 0 +#define RTL8367C_VLAN_EGRESS_TRANS_CTRL9_MASK 0x7FF + +#define RTL8367C_REG_MIRROR_CTRL2 0x09DA +#define RTL8367C_MIRROR_REALKEEP_EN_OFFSET 4 +#define RTL8367C_MIRROR_REALKEEP_EN_MASK 0x10 +#define RTL8367C_MIRROR_RX_ISOLATION_LEAKY_OFFSET 3 +#define RTL8367C_MIRROR_RX_ISOLATION_LEAKY_MASK 0x8 +#define RTL8367C_MIRROR_TX_ISOLATION_LEAKY_OFFSET 2 +#define RTL8367C_MIRROR_TX_ISOLATION_LEAKY_MASK 0x4 +#define RTL8367C_MIRROR_RX_VLAN_LEAKY_OFFSET 1 +#define RTL8367C_MIRROR_RX_VLAN_LEAKY_MASK 0x2 +#define RTL8367C_MIRROR_TX_VLAN_LEAKY_OFFSET 0 +#define RTL8367C_MIRROR_TX_VLAN_LEAKY_MASK 0x1 + +#define RTL8367C_REG_OUTPUT_DROP_CFG 0x09DB +#define RTL8367C_ENABLE_PMASK_EXT_OFFSET 13 +#define RTL8367C_ENABLE_PMASK_EXT_MASK 0xE000 +#define RTL8367C_ENABLE_BC_OFFSET 12 +#define RTL8367C_ENABLE_BC_MASK 0x1000 +#define RTL8367C_ENABLE_MC_OFFSET 11 +#define RTL8367C_ENABLE_MC_MASK 0x800 +#define RTL8367C_ENABLE_UC_OFFSET 10 +#define RTL8367C_ENABLE_UC_MASK 0x400 +#define RTL8367C_ENABLE_PMASK_OFFSET 0 +#define RTL8367C_ENABLE_PMASK_MASK 0xFF + +#define RTL8367C_REG_UNKNOWN_UNICAST_DA_PORT_BEHAVE_EXT 0x09DC +#define RTL8367C_PORT10_ACTION_OFFSET 4 +#define RTL8367C_PORT10_ACTION_MASK 0x30 +#define RTL8367C_PORT9_ACTION_OFFSET 2 +#define RTL8367C_PORT9_ACTION_MASK 0xC +#define RTL8367C_PORT8_ACTION_OFFSET 0 +#define RTL8367C_PORT8_ACTION_MASK 0x3 + +#define RTL8367C_REG_RMK_CFG_SEL_CTRL 0x09DF +#define RTL8367C_RMK_1Q_CFG_SEL_OFFSET 2 +#define RTL8367C_RMK_1Q_CFG_SEL_MASK 0x4 +#define RTL8367C_RMK_DSCP_CFG_SEL_OFFSET 0 +#define RTL8367C_RMK_DSCP_CFG_SEL_MASK 0x3 + +#define RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL0 0x09E0 +#define RTL8367C_DSCP1_DSCP_OFFSET 8 +#define RTL8367C_DSCP1_DSCP_MASK 0x3F00 +#define RTL8367C_DSCP0_DSCP_OFFSET 0 +#define RTL8367C_DSCP0_DSCP_MASK 0x3F + +#define RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL1 0x09E1 +#define RTL8367C_DSCP3_DSCP_OFFSET 8 +#define RTL8367C_DSCP3_DSCP_MASK 0x3F00 +#define RTL8367C_DSCP2_DSCP_OFFSET 0 +#define RTL8367C_DSCP2_DSCP_MASK 0x3F + +#define RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL2 0x09E2 +#define RTL8367C_DSCP5_DSCP_OFFSET 8 +#define RTL8367C_DSCP5_DSCP_MASK 0x3F00 +#define RTL8367C_DSCP4_DSCP_OFFSET 0 +#define RTL8367C_DSCP4_DSCP_MASK 0x3F + +#define RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL3 0x09E3 +#define RTL8367C_DSCP7_DSCP_OFFSET 8 +#define RTL8367C_DSCP7_DSCP_MASK 0x3F00 +#define RTL8367C_DSCP6_DSCP_OFFSET 0 +#define RTL8367C_DSCP6_DSCP_MASK 0x3F + +#define RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL4 0x09E4 +#define RTL8367C_DSCP9_DSCP_OFFSET 8 +#define RTL8367C_DSCP9_DSCP_MASK 0x3F00 +#define RTL8367C_DSCP8_DSCP_OFFSET 0 +#define RTL8367C_DSCP8_DSCP_MASK 0x3F + +#define RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL5 0x09E5 +#define RTL8367C_DSCP11_DSCP_OFFSET 8 +#define RTL8367C_DSCP11_DSCP_MASK 0x3F00 +#define RTL8367C_DSCP10_DSCP_OFFSET 0 +#define RTL8367C_DSCP10_DSCP_MASK 0x3F + +#define RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL6 0x09E6 +#define RTL8367C_DSCP13_DSCP_OFFSET 8 +#define RTL8367C_DSCP13_DSCP_MASK 0x3F00 +#define RTL8367C_DSCP12_DSCP_OFFSET 0 +#define RTL8367C_DSCP12_DSCP_MASK 0x3F + +#define RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL7 0x09E7 +#define RTL8367C_DSCP15_DSCP_OFFSET 8 +#define RTL8367C_DSCP15_DSCP_MASK 0x3F00 +#define RTL8367C_DSCP14_DSCP_OFFSET 0 +#define RTL8367C_DSCP14_DSCP_MASK 0x3F + +#define RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL8 0x09E8 +#define RTL8367C_DSCP17_DSCP_OFFSET 8 +#define RTL8367C_DSCP17_DSCP_MASK 0x3F00 +#define RTL8367C_DSCP16_DSCP_OFFSET 0 +#define RTL8367C_DSCP16_DSCP_MASK 0x3F + +#define RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL9 0x09E9 +#define RTL8367C_DSCP19_DSCP_OFFSET 8 +#define RTL8367C_DSCP19_DSCP_MASK 0x3F00 +#define RTL8367C_DSCP18_DSCP_OFFSET 0 +#define RTL8367C_DSCP18_DSCP_MASK 0x3F + +#define RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL10 0x09EA +#define RTL8367C_DSCP21_DSCP_OFFSET 8 +#define RTL8367C_DSCP21_DSCP_MASK 0x3F00 +#define RTL8367C_DSCP20_DSCP_OFFSET 0 +#define RTL8367C_DSCP20_DSCP_MASK 0x3F + +#define RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL11 0x09EB +#define RTL8367C_DSCP23_DSCP_OFFSET 8 +#define RTL8367C_DSCP23_DSCP_MASK 0x3F00 +#define RTL8367C_DSCP22_DSCP_OFFSET 0 +#define RTL8367C_DSCP22_DSCP_MASK 0x3F + +#define RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL12 0x09EC +#define RTL8367C_DSCP25_DSCP_OFFSET 8 +#define RTL8367C_DSCP25_DSCP_MASK 0x3F00 +#define RTL8367C_DSCP24_DSCP_OFFSET 0 +#define RTL8367C_DSCP24_DSCP_MASK 0x3F + +#define RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL13 0x09ED +#define RTL8367C_DSCP27_DSCP_OFFSET 8 +#define RTL8367C_DSCP27_DSCP_MASK 0x3F00 +#define RTL8367C_DSCP26_DSCP_OFFSET 0 +#define RTL8367C_DSCP26_DSCP_MASK 0x3F + +#define RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL14 0x09EE +#define RTL8367C_DSCP29_DSCP_OFFSET 8 +#define RTL8367C_DSCP29_DSCP_MASK 0x3F00 +#define RTL8367C_DSCP28_DSCP_OFFSET 0 +#define RTL8367C_DSCP28_DSCP_MASK 0x3F + +#define RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL15 0x09EF +#define RTL8367C_DSCP31_DSCP_OFFSET 8 +#define RTL8367C_DSCP31_DSCP_MASK 0x3F00 +#define RTL8367C_DSCP30_DSCP_OFFSET 0 +#define RTL8367C_DSCP30_DSCP_MASK 0x3F + +#define RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL16 0x09F0 +#define RTL8367C_DSCP33_DSCP_OFFSET 8 +#define RTL8367C_DSCP33_DSCP_MASK 0x3F00 +#define RTL8367C_DSCP32_DSCP_OFFSET 0 +#define RTL8367C_DSCP32_DSCP_MASK 0x3F + +#define RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL17 0x09F1 +#define RTL8367C_DSCP35_DSCP_OFFSET 8 +#define RTL8367C_DSCP35_DSCP_MASK 0x3F00 +#define RTL8367C_DSCP34_DSCP_OFFSET 0 +#define RTL8367C_DSCP34_DSCP_MASK 0x3F + +#define RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL18 0x09F2 +#define RTL8367C_DSCP37_DSCP_OFFSET 8 +#define RTL8367C_DSCP37_DSCP_MASK 0x3F00 +#define RTL8367C_DSCP36_DSCP_OFFSET 0 +#define RTL8367C_DSCP36_DSCP_MASK 0x3F + +#define RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL19 0x09F3 +#define RTL8367C_DSCP39_DSCP_OFFSET 8 +#define RTL8367C_DSCP39_DSCP_MASK 0x3F00 +#define RTL8367C_DSCP38_DSCP_OFFSET 0 +#define RTL8367C_DSCP38_DSCP_MASK 0x3F + +#define RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL20 0x09F4 +#define RTL8367C_DSCP41_DSCP_OFFSET 8 +#define RTL8367C_DSCP41_DSCP_MASK 0x3F00 +#define RTL8367C_DSCP40_DSCP_OFFSET 0 +#define RTL8367C_DSCP40_DSCP_MASK 0x3F + +#define RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL21 0x09F5 +#define RTL8367C_DSCP43_DSCP_OFFSET 8 +#define RTL8367C_DSCP43_DSCP_MASK 0x3F00 +#define RTL8367C_DSCP42_DSCP_OFFSET 0 +#define RTL8367C_DSCP42_DSCP_MASK 0x3F + +#define RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL22 0x09F6 +#define RTL8367C_DSCP45_DSCP_OFFSET 8 +#define RTL8367C_DSCP45_DSCP_MASK 0x3F00 +#define RTL8367C_DSCP44_DSCP_OFFSET 0 +#define RTL8367C_DSCP44_DSCP_MASK 0x3F + +#define RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL23 0x09F7 +#define RTL8367C_DSCP47_DSCP_OFFSET 8 +#define RTL8367C_DSCP47_DSCP_MASK 0x3F00 +#define RTL8367C_DSCP46_DSCP_OFFSET 0 +#define RTL8367C_DSCP46_DSCP_MASK 0x3F + +#define RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL24 0x09F8 +#define RTL8367C_DSCP49_DSCP_OFFSET 8 +#define RTL8367C_DSCP49_DSCP_MASK 0x3F00 +#define RTL8367C_DSCP48_DSCP_OFFSET 0 +#define RTL8367C_DSCP48_DSCP_MASK 0x3F + +#define RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL25 0x09F9 +#define RTL8367C_DSCP51_DSCP_OFFSET 8 +#define RTL8367C_DSCP51_DSCP_MASK 0x3F00 +#define RTL8367C_DSCP50_DSCP_OFFSET 0 +#define RTL8367C_DSCP50_DSCP_MASK 0x3F + +#define RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL26 0x09FA +#define RTL8367C_DSCP53_DSCP_OFFSET 8 +#define RTL8367C_DSCP53_DSCP_MASK 0x3F00 +#define RTL8367C_DSCP52_DSCP_OFFSET 0 +#define RTL8367C_DSCP52_DSCP_MASK 0x3F + +#define RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL27 0x09FB +#define RTL8367C_DSCP55_DSCP_OFFSET 8 +#define RTL8367C_DSCP55_DSCP_MASK 0x3F00 +#define RTL8367C_DSCP54_DSCP_OFFSET 0 +#define RTL8367C_DSCP54_DSCP_MASK 0x3F + +#define RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL28 0x09FC +#define RTL8367C_DSCP57_DSCP_OFFSET 8 +#define RTL8367C_DSCP57_DSCP_MASK 0x3F00 +#define RTL8367C_DSCP56_DSCP_OFFSET 0 +#define RTL8367C_DSCP56_DSCP_MASK 0x3F + +#define RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL29 0x09FD +#define RTL8367C_DSCP59_DSCP_OFFSET 8 +#define RTL8367C_DSCP59_DSCP_MASK 0x3F00 +#define RTL8367C_DSCP58_DSCP_OFFSET 0 +#define RTL8367C_DSCP58_DSCP_MASK 0x3F + +#define RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL30 0x09FE +#define RTL8367C_DSCP61_DSCP_OFFSET 8 +#define RTL8367C_DSCP61_DSCP_MASK 0x3F00 +#define RTL8367C_DSCP60_DSCP_OFFSET 0 +#define RTL8367C_DSCP60_DSCP_MASK 0x3F + +#define RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL31 0x09FF +#define RTL8367C_DSCP63_DSCP_OFFSET 8 +#define RTL8367C_DSCP63_DSCP_MASK 0x3F00 +#define RTL8367C_DSCP62_DSCP_OFFSET 0 +#define RTL8367C_DSCP62_DSCP_MASK 0x3F + +/* (16'h0a00)l2_reg */ + +#define RTL8367C_REG_VLAN_MSTI0_CTRL0 0x0a00 +#define RTL8367C_VLAN_MSTI0_CTRL0_PORT7_STATE_OFFSET 14 +#define RTL8367C_VLAN_MSTI0_CTRL0_PORT7_STATE_MASK 0xC000 +#define RTL8367C_VLAN_MSTI0_CTRL0_PORT6_STATE_OFFSET 12 +#define RTL8367C_VLAN_MSTI0_CTRL0_PORT6_STATE_MASK 0x3000 +#define RTL8367C_VLAN_MSTI0_CTRL0_PORT5_STATE_OFFSET 10 +#define RTL8367C_VLAN_MSTI0_CTRL0_PORT5_STATE_MASK 0xC00 +#define RTL8367C_VLAN_MSTI0_CTRL0_PORT4_STATE_OFFSET 8 +#define RTL8367C_VLAN_MSTI0_CTRL0_PORT4_STATE_MASK 0x300 +#define RTL8367C_VLAN_MSTI0_CTRL0_PORT3_STATE_OFFSET 6 +#define RTL8367C_VLAN_MSTI0_CTRL0_PORT3_STATE_MASK 0xC0 +#define RTL8367C_VLAN_MSTI0_CTRL0_PORT2_STATE_OFFSET 4 +#define RTL8367C_VLAN_MSTI0_CTRL0_PORT2_STATE_MASK 0x30 +#define RTL8367C_VLAN_MSTI0_CTRL0_PORT1_STATE_OFFSET 2 +#define RTL8367C_VLAN_MSTI0_CTRL0_PORT1_STATE_MASK 0xC +#define RTL8367C_VLAN_MSTI0_CTRL0_PORT0_STATE_OFFSET 0 +#define RTL8367C_VLAN_MSTI0_CTRL0_PORT0_STATE_MASK 0x3 + +#define RTL8367C_REG_VLAN_MSTI0_CTRL1 0x0a01 +#define RTL8367C_VLAN_MSTI0_CTRL1_PORT10_STATE_OFFSET 4 +#define RTL8367C_VLAN_MSTI0_CTRL1_PORT10_STATE_MASK 0x30 +#define RTL8367C_VLAN_MSTI0_CTRL1_PORT9_STATE_OFFSET 2 +#define RTL8367C_VLAN_MSTI0_CTRL1_PORT9_STATE_MASK 0xC +#define RTL8367C_VLAN_MSTI0_CTRL1_PORT8_STATE_OFFSET 0 +#define RTL8367C_VLAN_MSTI0_CTRL1_PORT8_STATE_MASK 0x3 + +#define RTL8367C_REG_VLAN_MSTI1_CTRL0 0x0a02 +#define RTL8367C_VLAN_MSTI1_CTRL0_PORT7_STATE_OFFSET 14 +#define RTL8367C_VLAN_MSTI1_CTRL0_PORT7_STATE_MASK 0xC000 +#define RTL8367C_VLAN_MSTI1_CTRL0_PORT6_STATE_OFFSET 12 +#define RTL8367C_VLAN_MSTI1_CTRL0_PORT6_STATE_MASK 0x3000 +#define RTL8367C_VLAN_MSTI1_CTRL0_PORT5_STATE_OFFSET 10 +#define RTL8367C_VLAN_MSTI1_CTRL0_PORT5_STATE_MASK 0xC00 +#define RTL8367C_VLAN_MSTI1_CTRL0_PORT4_STATE_OFFSET 8 +#define RTL8367C_VLAN_MSTI1_CTRL0_PORT4_STATE_MASK 0x300 +#define RTL8367C_VLAN_MSTI1_CTRL0_PORT3_STATE_OFFSET 6 +#define RTL8367C_VLAN_MSTI1_CTRL0_PORT3_STATE_MASK 0xC0 +#define RTL8367C_VLAN_MSTI1_CTRL0_PORT2_STATE_OFFSET 4 +#define RTL8367C_VLAN_MSTI1_CTRL0_PORT2_STATE_MASK 0x30 +#define RTL8367C_VLAN_MSTI1_CTRL0_PORT1_STATE_OFFSET 2 +#define RTL8367C_VLAN_MSTI1_CTRL0_PORT1_STATE_MASK 0xC +#define RTL8367C_VLAN_MSTI1_CTRL0_PORT0_STATE_OFFSET 0 +#define RTL8367C_VLAN_MSTI1_CTRL0_PORT0_STATE_MASK 0x3 + +#define RTL8367C_REG_VLAN_MSTI1_CTRL1 0x0a03 +#define RTL8367C_VLAN_MSTI1_CTRL1_PORT10_STATE_OFFSET 4 +#define RTL8367C_VLAN_MSTI1_CTRL1_PORT10_STATE_MASK 0x30 +#define RTL8367C_VLAN_MSTI1_CTRL1_PORT9_STATE_OFFSET 2 +#define RTL8367C_VLAN_MSTI1_CTRL1_PORT9_STATE_MASK 0xC +#define RTL8367C_VLAN_MSTI1_CTRL1_PORT8_STATE_OFFSET 0 +#define RTL8367C_VLAN_MSTI1_CTRL1_PORT8_STATE_MASK 0x3 + +#define RTL8367C_REG_VLAN_MSTI2_CTRL0 0x0a04 +#define RTL8367C_VLAN_MSTI2_CTRL0_PORT7_STATE_OFFSET 14 +#define RTL8367C_VLAN_MSTI2_CTRL0_PORT7_STATE_MASK 0xC000 +#define RTL8367C_VLAN_MSTI2_CTRL0_PORT6_STATE_OFFSET 12 +#define RTL8367C_VLAN_MSTI2_CTRL0_PORT6_STATE_MASK 0x3000 +#define RTL8367C_VLAN_MSTI2_CTRL0_PORT5_STATE_OFFSET 10 +#define RTL8367C_VLAN_MSTI2_CTRL0_PORT5_STATE_MASK 0xC00 +#define RTL8367C_VLAN_MSTI2_CTRL0_PORT4_STATE_OFFSET 8 +#define RTL8367C_VLAN_MSTI2_CTRL0_PORT4_STATE_MASK 0x300 +#define RTL8367C_VLAN_MSTI2_CTRL0_PORT3_STATE_OFFSET 6 +#define RTL8367C_VLAN_MSTI2_CTRL0_PORT3_STATE_MASK 0xC0 +#define RTL8367C_VLAN_MSTI2_CTRL0_PORT2_STATE_OFFSET 4 +#define RTL8367C_VLAN_MSTI2_CTRL0_PORT2_STATE_MASK 0x30 +#define RTL8367C_VLAN_MSTI2_CTRL0_PORT1_STATE_OFFSET 2 +#define RTL8367C_VLAN_MSTI2_CTRL0_PORT1_STATE_MASK 0xC +#define RTL8367C_VLAN_MSTI2_CTRL0_PORT0_STATE_OFFSET 0 +#define RTL8367C_VLAN_MSTI2_CTRL0_PORT0_STATE_MASK 0x3 + +#define RTL8367C_REG_VLAN_MSTI2_CTRL1 0x0a05 +#define RTL8367C_VLAN_MSTI2_CTRL1_PORT10_STATE_OFFSET 4 +#define RTL8367C_VLAN_MSTI2_CTRL1_PORT10_STATE_MASK 0x30 +#define RTL8367C_VLAN_MSTI2_CTRL1_PORT9_STATE_OFFSET 2 +#define RTL8367C_VLAN_MSTI2_CTRL1_PORT9_STATE_MASK 0xC +#define RTL8367C_VLAN_MSTI2_CTRL1_PORT8_STATE_OFFSET 0 +#define RTL8367C_VLAN_MSTI2_CTRL1_PORT8_STATE_MASK 0x3 + +#define RTL8367C_REG_VLAN_MSTI3_CTRL0 0x0a06 +#define RTL8367C_VLAN_MSTI3_CTRL0_PORT7_STATE_OFFSET 14 +#define RTL8367C_VLAN_MSTI3_CTRL0_PORT7_STATE_MASK 0xC000 +#define RTL8367C_VLAN_MSTI3_CTRL0_PORT6_STATE_OFFSET 12 +#define RTL8367C_VLAN_MSTI3_CTRL0_PORT6_STATE_MASK 0x3000 +#define RTL8367C_VLAN_MSTI3_CTRL0_PORT5_STATE_OFFSET 10 +#define RTL8367C_VLAN_MSTI3_CTRL0_PORT5_STATE_MASK 0xC00 +#define RTL8367C_VLAN_MSTI3_CTRL0_PORT4_STATE_OFFSET 8 +#define RTL8367C_VLAN_MSTI3_CTRL0_PORT4_STATE_MASK 0x300 +#define RTL8367C_VLAN_MSTI3_CTRL0_PORT3_STATE_OFFSET 6 +#define RTL8367C_VLAN_MSTI3_CTRL0_PORT3_STATE_MASK 0xC0 +#define RTL8367C_VLAN_MSTI3_CTRL0_PORT2_STATE_OFFSET 4 +#define RTL8367C_VLAN_MSTI3_CTRL0_PORT2_STATE_MASK 0x30 +#define RTL8367C_VLAN_MSTI3_CTRL0_PORT1_STATE_OFFSET 2 +#define RTL8367C_VLAN_MSTI3_CTRL0_PORT1_STATE_MASK 0xC +#define RTL8367C_VLAN_MSTI3_CTRL0_PORT0_STATE_OFFSET 0 +#define RTL8367C_VLAN_MSTI3_CTRL0_PORT0_STATE_MASK 0x3 + +#define RTL8367C_REG_VLAN_MSTI3_CTRL1 0x0a07 +#define RTL8367C_VLAN_MSTI3_CTRL1_PORT10_STATE_OFFSET 4 +#define RTL8367C_VLAN_MSTI3_CTRL1_PORT10_STATE_MASK 0x30 +#define RTL8367C_VLAN_MSTI3_CTRL1_PORT9_STATE_OFFSET 2 +#define RTL8367C_VLAN_MSTI3_CTRL1_PORT9_STATE_MASK 0xC +#define RTL8367C_VLAN_MSTI3_CTRL1_PORT8_STATE_OFFSET 0 +#define RTL8367C_VLAN_MSTI3_CTRL1_PORT8_STATE_MASK 0x3 + +#define RTL8367C_REG_VLAN_MSTI4_CTRL0 0x0a08 +#define RTL8367C_VLAN_MSTI4_CTRL0_PORT7_STATE_OFFSET 14 +#define RTL8367C_VLAN_MSTI4_CTRL0_PORT7_STATE_MASK 0xC000 +#define RTL8367C_VLAN_MSTI4_CTRL0_PORT6_STATE_OFFSET 12 +#define RTL8367C_VLAN_MSTI4_CTRL0_PORT6_STATE_MASK 0x3000 +#define RTL8367C_VLAN_MSTI4_CTRL0_PORT5_STATE_OFFSET 10 +#define RTL8367C_VLAN_MSTI4_CTRL0_PORT5_STATE_MASK 0xC00 +#define RTL8367C_VLAN_MSTI4_CTRL0_PORT4_STATE_OFFSET 8 +#define RTL8367C_VLAN_MSTI4_CTRL0_PORT4_STATE_MASK 0x300 +#define RTL8367C_VLAN_MSTI4_CTRL0_PORT3_STATE_OFFSET 6 +#define RTL8367C_VLAN_MSTI4_CTRL0_PORT3_STATE_MASK 0xC0 +#define RTL8367C_VLAN_MSTI4_CTRL0_PORT2_STATE_OFFSET 4 +#define RTL8367C_VLAN_MSTI4_CTRL0_PORT2_STATE_MASK 0x30 +#define RTL8367C_VLAN_MSTI4_CTRL0_PORT1_STATE_OFFSET 2 +#define RTL8367C_VLAN_MSTI4_CTRL0_PORT1_STATE_MASK 0xC +#define RTL8367C_VLAN_MSTI4_CTRL0_PORT0_STATE_OFFSET 0 +#define RTL8367C_VLAN_MSTI4_CTRL0_PORT0_STATE_MASK 0x3 + +#define RTL8367C_REG_VLAN_MSTI4_CTRL1 0x0a09 +#define RTL8367C_VLAN_MSTI4_CTRL1_PORT10_STATE_OFFSET 4 +#define RTL8367C_VLAN_MSTI4_CTRL1_PORT10_STATE_MASK 0x30 +#define RTL8367C_VLAN_MSTI4_CTRL1_PORT9_STATE_OFFSET 2 +#define RTL8367C_VLAN_MSTI4_CTRL1_PORT9_STATE_MASK 0xC +#define RTL8367C_VLAN_MSTI4_CTRL1_PORT8_STATE_OFFSET 0 +#define RTL8367C_VLAN_MSTI4_CTRL1_PORT8_STATE_MASK 0x3 + +#define RTL8367C_REG_VLAN_MSTI5_CTRL0 0x0a0a +#define RTL8367C_VLAN_MSTI5_CTRL0_PORT7_STATE_OFFSET 14 +#define RTL8367C_VLAN_MSTI5_CTRL0_PORT7_STATE_MASK 0xC000 +#define RTL8367C_VLAN_MSTI5_CTRL0_PORT6_STATE_OFFSET 12 +#define RTL8367C_VLAN_MSTI5_CTRL0_PORT6_STATE_MASK 0x3000 +#define RTL8367C_VLAN_MSTI5_CTRL0_PORT5_STATE_OFFSET 10 +#define RTL8367C_VLAN_MSTI5_CTRL0_PORT5_STATE_MASK 0xC00 +#define RTL8367C_VLAN_MSTI5_CTRL0_PORT4_STATE_OFFSET 8 +#define RTL8367C_VLAN_MSTI5_CTRL0_PORT4_STATE_MASK 0x300 +#define RTL8367C_VLAN_MSTI5_CTRL0_PORT3_STATE_OFFSET 6 +#define RTL8367C_VLAN_MSTI5_CTRL0_PORT3_STATE_MASK 0xC0 +#define RTL8367C_VLAN_MSTI5_CTRL0_PORT2_STATE_OFFSET 4 +#define RTL8367C_VLAN_MSTI5_CTRL0_PORT2_STATE_MASK 0x30 +#define RTL8367C_VLAN_MSTI5_CTRL0_PORT1_STATE_OFFSET 2 +#define RTL8367C_VLAN_MSTI5_CTRL0_PORT1_STATE_MASK 0xC +#define RTL8367C_VLAN_MSTI5_CTRL0_PORT0_STATE_OFFSET 0 +#define RTL8367C_VLAN_MSTI5_CTRL0_PORT0_STATE_MASK 0x3 + +#define RTL8367C_REG_VLAN_MSTI5_CTRL1 0x0a0b +#define RTL8367C_VLAN_MSTI5_CTRL1_PORT10_STATE_OFFSET 4 +#define RTL8367C_VLAN_MSTI5_CTRL1_PORT10_STATE_MASK 0x30 +#define RTL8367C_VLAN_MSTI5_CTRL1_PORT9_STATE_OFFSET 2 +#define RTL8367C_VLAN_MSTI5_CTRL1_PORT9_STATE_MASK 0xC +#define RTL8367C_VLAN_MSTI5_CTRL1_PORT8_STATE_OFFSET 0 +#define RTL8367C_VLAN_MSTI5_CTRL1_PORT8_STATE_MASK 0x3 + +#define RTL8367C_REG_VLAN_MSTI6_CTRL0 0x0a0c +#define RTL8367C_VLAN_MSTI6_CTRL0_PORT7_STATE_OFFSET 14 +#define RTL8367C_VLAN_MSTI6_CTRL0_PORT7_STATE_MASK 0xC000 +#define RTL8367C_VLAN_MSTI6_CTRL0_PORT6_STATE_OFFSET 12 +#define RTL8367C_VLAN_MSTI6_CTRL0_PORT6_STATE_MASK 0x3000 +#define RTL8367C_VLAN_MSTI6_CTRL0_PORT5_STATE_OFFSET 10 +#define RTL8367C_VLAN_MSTI6_CTRL0_PORT5_STATE_MASK 0xC00 +#define RTL8367C_VLAN_MSTI6_CTRL0_PORT4_STATE_OFFSET 8 +#define RTL8367C_VLAN_MSTI6_CTRL0_PORT4_STATE_MASK 0x300 +#define RTL8367C_VLAN_MSTI6_CTRL0_PORT3_STATE_OFFSET 6 +#define RTL8367C_VLAN_MSTI6_CTRL0_PORT3_STATE_MASK 0xC0 +#define RTL8367C_VLAN_MSTI6_CTRL0_PORT2_STATE_OFFSET 4 +#define RTL8367C_VLAN_MSTI6_CTRL0_PORT2_STATE_MASK 0x30 +#define RTL8367C_VLAN_MSTI6_CTRL0_PORT1_STATE_OFFSET 2 +#define RTL8367C_VLAN_MSTI6_CTRL0_PORT1_STATE_MASK 0xC +#define RTL8367C_VLAN_MSTI6_CTRL0_PORT0_STATE_OFFSET 0 +#define RTL8367C_VLAN_MSTI6_CTRL0_PORT0_STATE_MASK 0x3 + +#define RTL8367C_REG_VLAN_MSTI6_CTRL1 0x0a0d +#define RTL8367C_VLAN_MSTI6_CTRL1_PORT10_STATE_OFFSET 4 +#define RTL8367C_VLAN_MSTI6_CTRL1_PORT10_STATE_MASK 0x30 +#define RTL8367C_VLAN_MSTI6_CTRL1_PORT9_STATE_OFFSET 2 +#define RTL8367C_VLAN_MSTI6_CTRL1_PORT9_STATE_MASK 0xC +#define RTL8367C_VLAN_MSTI6_CTRL1_PORT8_STATE_OFFSET 0 +#define RTL8367C_VLAN_MSTI6_CTRL1_PORT8_STATE_MASK 0x3 + +#define RTL8367C_REG_VLAN_MSTI7_CTRL0 0x0a0e +#define RTL8367C_VLAN_MSTI7_CTRL0_PORT7_STATE_OFFSET 14 +#define RTL8367C_VLAN_MSTI7_CTRL0_PORT7_STATE_MASK 0xC000 +#define RTL8367C_VLAN_MSTI7_CTRL0_PORT6_STATE_OFFSET 12 +#define RTL8367C_VLAN_MSTI7_CTRL0_PORT6_STATE_MASK 0x3000 +#define RTL8367C_VLAN_MSTI7_CTRL0_PORT5_STATE_OFFSET 10 +#define RTL8367C_VLAN_MSTI7_CTRL0_PORT5_STATE_MASK 0xC00 +#define RTL8367C_VLAN_MSTI7_CTRL0_PORT4_STATE_OFFSET 8 +#define RTL8367C_VLAN_MSTI7_CTRL0_PORT4_STATE_MASK 0x300 +#define RTL8367C_VLAN_MSTI7_CTRL0_PORT3_STATE_OFFSET 6 +#define RTL8367C_VLAN_MSTI7_CTRL0_PORT3_STATE_MASK 0xC0 +#define RTL8367C_VLAN_MSTI7_CTRL0_PORT2_STATE_OFFSET 4 +#define RTL8367C_VLAN_MSTI7_CTRL0_PORT2_STATE_MASK 0x30 +#define RTL8367C_VLAN_MSTI7_CTRL0_PORT1_STATE_OFFSET 2 +#define RTL8367C_VLAN_MSTI7_CTRL0_PORT1_STATE_MASK 0xC +#define RTL8367C_VLAN_MSTI7_CTRL0_PORT0_STATE_OFFSET 0 +#define RTL8367C_VLAN_MSTI7_CTRL0_PORT0_STATE_MASK 0x3 + +#define RTL8367C_REG_VLAN_MSTI7_CTRL1 0x0a0f +#define RTL8367C_VLAN_MSTI7_CTRL1_PORT10_STATE_OFFSET 4 +#define RTL8367C_VLAN_MSTI7_CTRL1_PORT10_STATE_MASK 0x30 +#define RTL8367C_VLAN_MSTI7_CTRL1_PORT9_STATE_OFFSET 2 +#define RTL8367C_VLAN_MSTI7_CTRL1_PORT9_STATE_MASK 0xC +#define RTL8367C_VLAN_MSTI7_CTRL1_PORT8_STATE_OFFSET 0 +#define RTL8367C_VLAN_MSTI7_CTRL1_PORT8_STATE_MASK 0x3 + +#define RTL8367C_REG_VLAN_MSTI8_CTRL0 0x0a10 +#define RTL8367C_VLAN_MSTI8_CTRL0_PORT7_STATE_OFFSET 14 +#define RTL8367C_VLAN_MSTI8_CTRL0_PORT7_STATE_MASK 0xC000 +#define RTL8367C_VLAN_MSTI8_CTRL0_PORT6_STATE_OFFSET 12 +#define RTL8367C_VLAN_MSTI8_CTRL0_PORT6_STATE_MASK 0x3000 +#define RTL8367C_VLAN_MSTI8_CTRL0_PORT5_STATE_OFFSET 10 +#define RTL8367C_VLAN_MSTI8_CTRL0_PORT5_STATE_MASK 0xC00 +#define RTL8367C_VLAN_MSTI8_CTRL0_PORT4_STATE_OFFSET 8 +#define RTL8367C_VLAN_MSTI8_CTRL0_PORT4_STATE_MASK 0x300 +#define RTL8367C_VLAN_MSTI8_CTRL0_PORT3_STATE_OFFSET 6 +#define RTL8367C_VLAN_MSTI8_CTRL0_PORT3_STATE_MASK 0xC0 +#define RTL8367C_VLAN_MSTI8_CTRL0_PORT2_STATE_OFFSET 4 +#define RTL8367C_VLAN_MSTI8_CTRL0_PORT2_STATE_MASK 0x30 +#define RTL8367C_VLAN_MSTI8_CTRL0_PORT1_STATE_OFFSET 2 +#define RTL8367C_VLAN_MSTI8_CTRL0_PORT1_STATE_MASK 0xC +#define RTL8367C_VLAN_MSTI8_CTRL0_PORT0_STATE_OFFSET 0 +#define RTL8367C_VLAN_MSTI8_CTRL0_PORT0_STATE_MASK 0x3 + +#define RTL8367C_REG_VLAN_MSTI8_CTRL1 0x0a11 +#define RTL8367C_VLAN_MSTI8_CTRL1_PORT10_STATE_OFFSET 4 +#define RTL8367C_VLAN_MSTI8_CTRL1_PORT10_STATE_MASK 0x30 +#define RTL8367C_VLAN_MSTI8_CTRL1_PORT9_STATE_OFFSET 2 +#define RTL8367C_VLAN_MSTI8_CTRL1_PORT9_STATE_MASK 0xC +#define RTL8367C_VLAN_MSTI8_CTRL1_PORT8_STATE_OFFSET 0 +#define RTL8367C_VLAN_MSTI8_CTRL1_PORT8_STATE_MASK 0x3 + +#define RTL8367C_REG_VLAN_MSTI9_CTRL0 0x0a12 +#define RTL8367C_VLAN_MSTI9_CTRL0_PORT7_STATE_OFFSET 14 +#define RTL8367C_VLAN_MSTI9_CTRL0_PORT7_STATE_MASK 0xC000 +#define RTL8367C_VLAN_MSTI9_CTRL0_PORT6_STATE_OFFSET 12 +#define RTL8367C_VLAN_MSTI9_CTRL0_PORT6_STATE_MASK 0x3000 +#define RTL8367C_VLAN_MSTI9_CTRL0_PORT5_STATE_OFFSET 10 +#define RTL8367C_VLAN_MSTI9_CTRL0_PORT5_STATE_MASK 0xC00 +#define RTL8367C_VLAN_MSTI9_CTRL0_PORT4_STATE_OFFSET 8 +#define RTL8367C_VLAN_MSTI9_CTRL0_PORT4_STATE_MASK 0x300 +#define RTL8367C_VLAN_MSTI9_CTRL0_PORT3_STATE_OFFSET 6 +#define RTL8367C_VLAN_MSTI9_CTRL0_PORT3_STATE_MASK 0xC0 +#define RTL8367C_VLAN_MSTI9_CTRL0_PORT2_STATE_OFFSET 4 +#define RTL8367C_VLAN_MSTI9_CTRL0_PORT2_STATE_MASK 0x30 +#define RTL8367C_VLAN_MSTI9_CTRL0_PORT1_STATE_OFFSET 2 +#define RTL8367C_VLAN_MSTI9_CTRL0_PORT1_STATE_MASK 0xC +#define RTL8367C_VLAN_MSTI9_CTRL0_PORT0_STATE_OFFSET 0 +#define RTL8367C_VLAN_MSTI9_CTRL0_PORT0_STATE_MASK 0x3 + +#define RTL8367C_REG_VLAN_MSTI9_CTRL1 0x0a13 +#define RTL8367C_VLAN_MSTI9_CTRL1_PORT10_STATE_OFFSET 4 +#define RTL8367C_VLAN_MSTI9_CTRL1_PORT10_STATE_MASK 0x30 +#define RTL8367C_VLAN_MSTI9_CTRL1_PORT9_STATE_OFFSET 2 +#define RTL8367C_VLAN_MSTI9_CTRL1_PORT9_STATE_MASK 0xC +#define RTL8367C_VLAN_MSTI9_CTRL1_PORT8_STATE_OFFSET 0 +#define RTL8367C_VLAN_MSTI9_CTRL1_PORT8_STATE_MASK 0x3 + +#define RTL8367C_REG_VLAN_MSTI10_CTRL0 0x0a14 +#define RTL8367C_VLAN_MSTI10_CTRL0_PORT7_STATE_OFFSET 14 +#define RTL8367C_VLAN_MSTI10_CTRL0_PORT7_STATE_MASK 0xC000 +#define RTL8367C_VLAN_MSTI10_CTRL0_PORT6_STATE_OFFSET 12 +#define RTL8367C_VLAN_MSTI10_CTRL0_PORT6_STATE_MASK 0x3000 +#define RTL8367C_VLAN_MSTI10_CTRL0_PORT5_STATE_OFFSET 10 +#define RTL8367C_VLAN_MSTI10_CTRL0_PORT5_STATE_MASK 0xC00 +#define RTL8367C_VLAN_MSTI10_CTRL0_PORT4_STATE_OFFSET 8 +#define RTL8367C_VLAN_MSTI10_CTRL0_PORT4_STATE_MASK 0x300 +#define RTL8367C_VLAN_MSTI10_CTRL0_PORT3_STATE_OFFSET 6 +#define RTL8367C_VLAN_MSTI10_CTRL0_PORT3_STATE_MASK 0xC0 +#define RTL8367C_VLAN_MSTI10_CTRL0_PORT2_STATE_OFFSET 4 +#define RTL8367C_VLAN_MSTI10_CTRL0_PORT2_STATE_MASK 0x30 +#define RTL8367C_VLAN_MSTI10_CTRL0_PORT1_STATE_OFFSET 2 +#define RTL8367C_VLAN_MSTI10_CTRL0_PORT1_STATE_MASK 0xC +#define RTL8367C_VLAN_MSTI10_CTRL0_PORT0_STATE_OFFSET 0 +#define RTL8367C_VLAN_MSTI10_CTRL0_PORT0_STATE_MASK 0x3 + +#define RTL8367C_REG_VLAN_MSTI10_CTRL1 0x0a15 +#define RTL8367C_VLAN_MSTI10_CTRL1_PORT10_STATE_OFFSET 4 +#define RTL8367C_VLAN_MSTI10_CTRL1_PORT10_STATE_MASK 0x30 +#define RTL8367C_VLAN_MSTI10_CTRL1_PORT9_STATE_OFFSET 2 +#define RTL8367C_VLAN_MSTI10_CTRL1_PORT9_STATE_MASK 0xC +#define RTL8367C_VLAN_MSTI10_CTRL1_PORT8_STATE_OFFSET 0 +#define RTL8367C_VLAN_MSTI10_CTRL1_PORT8_STATE_MASK 0x3 + +#define RTL8367C_REG_VLAN_MSTI11_CTRL0 0x0a16 +#define RTL8367C_VLAN_MSTI11_CTRL0_PORT7_STATE_OFFSET 14 +#define RTL8367C_VLAN_MSTI11_CTRL0_PORT7_STATE_MASK 0xC000 +#define RTL8367C_VLAN_MSTI11_CTRL0_PORT6_STATE_OFFSET 12 +#define RTL8367C_VLAN_MSTI11_CTRL0_PORT6_STATE_MASK 0x3000 +#define RTL8367C_VLAN_MSTI11_CTRL0_PORT5_STATE_OFFSET 10 +#define RTL8367C_VLAN_MSTI11_CTRL0_PORT5_STATE_MASK 0xC00 +#define RTL8367C_VLAN_MSTI11_CTRL0_PORT4_STATE_OFFSET 8 +#define RTL8367C_VLAN_MSTI11_CTRL0_PORT4_STATE_MASK 0x300 +#define RTL8367C_VLAN_MSTI11_CTRL0_PORT3_STATE_OFFSET 6 +#define RTL8367C_VLAN_MSTI11_CTRL0_PORT3_STATE_MASK 0xC0 +#define RTL8367C_VLAN_MSTI11_CTRL0_PORT2_STATE_OFFSET 4 +#define RTL8367C_VLAN_MSTI11_CTRL0_PORT2_STATE_MASK 0x30 +#define RTL8367C_VLAN_MSTI11_CTRL0_PORT1_STATE_OFFSET 2 +#define RTL8367C_VLAN_MSTI11_CTRL0_PORT1_STATE_MASK 0xC +#define RTL8367C_VLAN_MSTI11_CTRL0_PORT0_STATE_OFFSET 0 +#define RTL8367C_VLAN_MSTI11_CTRL0_PORT0_STATE_MASK 0x3 + +#define RTL8367C_REG_VLAN_MSTI11_CTRL1 0x0a17 +#define RTL8367C_VLAN_MSTI11_CTRL1_PORT10_STATE_OFFSET 4 +#define RTL8367C_VLAN_MSTI11_CTRL1_PORT10_STATE_MASK 0x30 +#define RTL8367C_VLAN_MSTI11_CTRL1_PORT9_STATE_OFFSET 2 +#define RTL8367C_VLAN_MSTI11_CTRL1_PORT9_STATE_MASK 0xC +#define RTL8367C_VLAN_MSTI11_CTRL1_PORT8_STATE_OFFSET 0 +#define RTL8367C_VLAN_MSTI11_CTRL1_PORT8_STATE_MASK 0x3 + +#define RTL8367C_REG_VLAN_MSTI12_CTRL0 0x0a18 +#define RTL8367C_VLAN_MSTI12_CTRL0_PORT7_STATE_OFFSET 14 +#define RTL8367C_VLAN_MSTI12_CTRL0_PORT7_STATE_MASK 0xC000 +#define RTL8367C_VLAN_MSTI12_CTRL0_PORT6_STATE_OFFSET 12 +#define RTL8367C_VLAN_MSTI12_CTRL0_PORT6_STATE_MASK 0x3000 +#define RTL8367C_VLAN_MSTI12_CTRL0_PORT5_STATE_OFFSET 10 +#define RTL8367C_VLAN_MSTI12_CTRL0_PORT5_STATE_MASK 0xC00 +#define RTL8367C_VLAN_MSTI12_CTRL0_PORT4_STATE_OFFSET 8 +#define RTL8367C_VLAN_MSTI12_CTRL0_PORT4_STATE_MASK 0x300 +#define RTL8367C_VLAN_MSTI12_CTRL0_PORT3_STATE_OFFSET 6 +#define RTL8367C_VLAN_MSTI12_CTRL0_PORT3_STATE_MASK 0xC0 +#define RTL8367C_VLAN_MSTI12_CTRL0_PORT2_STATE_OFFSET 4 +#define RTL8367C_VLAN_MSTI12_CTRL0_PORT2_STATE_MASK 0x30 +#define RTL8367C_VLAN_MSTI12_CTRL0_PORT1_STATE_OFFSET 2 +#define RTL8367C_VLAN_MSTI12_CTRL0_PORT1_STATE_MASK 0xC +#define RTL8367C_VLAN_MSTI12_CTRL0_PORT0_STATE_OFFSET 0 +#define RTL8367C_VLAN_MSTI12_CTRL0_PORT0_STATE_MASK 0x3 + +#define RTL8367C_REG_VLAN_MSTI12_CTRL1 0x0a19 +#define RTL8367C_VLAN_MSTI12_CTRL1_PORT10_STATE_OFFSET 4 +#define RTL8367C_VLAN_MSTI12_CTRL1_PORT10_STATE_MASK 0x30 +#define RTL8367C_VLAN_MSTI12_CTRL1_PORT9_STATE_OFFSET 2 +#define RTL8367C_VLAN_MSTI12_CTRL1_PORT9_STATE_MASK 0xC +#define RTL8367C_VLAN_MSTI12_CTRL1_PORT8_STATE_OFFSET 0 +#define RTL8367C_VLAN_MSTI12_CTRL1_PORT8_STATE_MASK 0x3 + +#define RTL8367C_REG_VLAN_MSTI13_CTRL0 0x0a1a +#define RTL8367C_VLAN_MSTI13_CTRL0_PORT7_STATE_OFFSET 14 +#define RTL8367C_VLAN_MSTI13_CTRL0_PORT7_STATE_MASK 0xC000 +#define RTL8367C_VLAN_MSTI13_CTRL0_PORT6_STATE_OFFSET 12 +#define RTL8367C_VLAN_MSTI13_CTRL0_PORT6_STATE_MASK 0x3000 +#define RTL8367C_VLAN_MSTI13_CTRL0_PORT5_STATE_OFFSET 10 +#define RTL8367C_VLAN_MSTI13_CTRL0_PORT5_STATE_MASK 0xC00 +#define RTL8367C_VLAN_MSTI13_CTRL0_PORT4_STATE_OFFSET 8 +#define RTL8367C_VLAN_MSTI13_CTRL0_PORT4_STATE_MASK 0x300 +#define RTL8367C_VLAN_MSTI13_CTRL0_PORT3_STATE_OFFSET 6 +#define RTL8367C_VLAN_MSTI13_CTRL0_PORT3_STATE_MASK 0xC0 +#define RTL8367C_VLAN_MSTI13_CTRL0_PORT2_STATE_OFFSET 4 +#define RTL8367C_VLAN_MSTI13_CTRL0_PORT2_STATE_MASK 0x30 +#define RTL8367C_VLAN_MSTI13_CTRL0_PORT1_STATE_OFFSET 2 +#define RTL8367C_VLAN_MSTI13_CTRL0_PORT1_STATE_MASK 0xC +#define RTL8367C_VLAN_MSTI13_CTRL0_PORT0_STATE_OFFSET 0 +#define RTL8367C_VLAN_MSTI13_CTRL0_PORT0_STATE_MASK 0x3 + +#define RTL8367C_REG_VLAN_MSTI13_CTRL1 0x0a1b +#define RTL8367C_VLAN_MSTI13_CTRL1_PORT10_STATE_OFFSET 4 +#define RTL8367C_VLAN_MSTI13_CTRL1_PORT10_STATE_MASK 0x30 +#define RTL8367C_VLAN_MSTI13_CTRL1_PORT9_STATE_OFFSET 2 +#define RTL8367C_VLAN_MSTI13_CTRL1_PORT9_STATE_MASK 0xC +#define RTL8367C_VLAN_MSTI13_CTRL1_PORT8_STATE_OFFSET 0 +#define RTL8367C_VLAN_MSTI13_CTRL1_PORT8_STATE_MASK 0x3 + +#define RTL8367C_REG_VLAN_MSTI14_CTRL0 0x0a1c +#define RTL8367C_VLAN_MSTI14_CTRL0_PORT7_STATE_OFFSET 14 +#define RTL8367C_VLAN_MSTI14_CTRL0_PORT7_STATE_MASK 0xC000 +#define RTL8367C_VLAN_MSTI14_CTRL0_PORT6_STATE_OFFSET 12 +#define RTL8367C_VLAN_MSTI14_CTRL0_PORT6_STATE_MASK 0x3000 +#define RTL8367C_VLAN_MSTI14_CTRL0_PORT5_STATE_OFFSET 10 +#define RTL8367C_VLAN_MSTI14_CTRL0_PORT5_STATE_MASK 0xC00 +#define RTL8367C_VLAN_MSTI14_CTRL0_PORT4_STATE_OFFSET 8 +#define RTL8367C_VLAN_MSTI14_CTRL0_PORT4_STATE_MASK 0x300 +#define RTL8367C_VLAN_MSTI14_CTRL0_PORT3_STATE_OFFSET 6 +#define RTL8367C_VLAN_MSTI14_CTRL0_PORT3_STATE_MASK 0xC0 +#define RTL8367C_VLAN_MSTI14_CTRL0_PORT2_STATE_OFFSET 4 +#define RTL8367C_VLAN_MSTI14_CTRL0_PORT2_STATE_MASK 0x30 +#define RTL8367C_VLAN_MSTI14_CTRL0_PORT1_STATE_OFFSET 2 +#define RTL8367C_VLAN_MSTI14_CTRL0_PORT1_STATE_MASK 0xC +#define RTL8367C_VLAN_MSTI14_CTRL0_PORT0_STATE_OFFSET 0 +#define RTL8367C_VLAN_MSTI14_CTRL0_PORT0_STATE_MASK 0x3 + +#define RTL8367C_REG_VLAN_MSTI14_CTRL1 0x0a1d +#define RTL8367C_VLAN_MSTI14_CTRL1_PORT10_STATE_OFFSET 4 +#define RTL8367C_VLAN_MSTI14_CTRL1_PORT10_STATE_MASK 0x30 +#define RTL8367C_VLAN_MSTI14_CTRL1_PORT9_STATE_OFFSET 2 +#define RTL8367C_VLAN_MSTI14_CTRL1_PORT9_STATE_MASK 0xC +#define RTL8367C_VLAN_MSTI14_CTRL1_PORT8_STATE_OFFSET 0 +#define RTL8367C_VLAN_MSTI14_CTRL1_PORT8_STATE_MASK 0x3 + +#define RTL8367C_REG_VLAN_MSTI15_CTRL0 0x0a1e +#define RTL8367C_VLAN_MSTI15_CTRL0_PORT7_STATE_OFFSET 14 +#define RTL8367C_VLAN_MSTI15_CTRL0_PORT7_STATE_MASK 0xC000 +#define RTL8367C_VLAN_MSTI15_CTRL0_PORT6_STATE_OFFSET 12 +#define RTL8367C_VLAN_MSTI15_CTRL0_PORT6_STATE_MASK 0x3000 +#define RTL8367C_VLAN_MSTI15_CTRL0_PORT5_STATE_OFFSET 10 +#define RTL8367C_VLAN_MSTI15_CTRL0_PORT5_STATE_MASK 0xC00 +#define RTL8367C_VLAN_MSTI15_CTRL0_PORT4_STATE_OFFSET 8 +#define RTL8367C_VLAN_MSTI15_CTRL0_PORT4_STATE_MASK 0x300 +#define RTL8367C_VLAN_MSTI15_CTRL0_PORT3_STATE_OFFSET 6 +#define RTL8367C_VLAN_MSTI15_CTRL0_PORT3_STATE_MASK 0xC0 +#define RTL8367C_VLAN_MSTI15_CTRL0_PORT2_STATE_OFFSET 4 +#define RTL8367C_VLAN_MSTI15_CTRL0_PORT2_STATE_MASK 0x30 +#define RTL8367C_VLAN_MSTI15_CTRL0_PORT1_STATE_OFFSET 2 +#define RTL8367C_VLAN_MSTI15_CTRL0_PORT1_STATE_MASK 0xC +#define RTL8367C_VLAN_MSTI15_CTRL0_PORT0_STATE_OFFSET 0 +#define RTL8367C_VLAN_MSTI15_CTRL0_PORT0_STATE_MASK 0x3 + +#define RTL8367C_REG_VLAN_MSTI15_CTRL1 0x0a1f +#define RTL8367C_VLAN_MSTI15_CTRL1_PORT10_STATE_OFFSET 4 +#define RTL8367C_VLAN_MSTI15_CTRL1_PORT10_STATE_MASK 0x30 +#define RTL8367C_VLAN_MSTI15_CTRL1_PORT9_STATE_OFFSET 2 +#define RTL8367C_VLAN_MSTI15_CTRL1_PORT9_STATE_MASK 0xC +#define RTL8367C_VLAN_MSTI15_CTRL1_PORT8_STATE_OFFSET 0 +#define RTL8367C_VLAN_MSTI15_CTRL1_PORT8_STATE_MASK 0x3 + +#define RTL8367C_REG_LUT_PORT0_LEARN_LIMITNO 0x0a20 +#define RTL8367C_LUT_PORT0_LEARN_LIMITNO_OFFSET 0 +#define RTL8367C_LUT_PORT0_LEARN_LIMITNO_MASK 0x1FFF + +#define RTL8367C_REG_LUT_PORT1_LEARN_LIMITNO 0x0a21 +#define RTL8367C_LUT_PORT1_LEARN_LIMITNO_OFFSET 0 +#define RTL8367C_LUT_PORT1_LEARN_LIMITNO_MASK 0x1FFF + +#define RTL8367C_REG_LUT_PORT2_LEARN_LIMITNO 0x0a22 +#define RTL8367C_LUT_PORT2_LEARN_LIMITNO_OFFSET 0 +#define RTL8367C_LUT_PORT2_LEARN_LIMITNO_MASK 0x1FFF + +#define RTL8367C_REG_LUT_PORT3_LEARN_LIMITNO 0x0a23 +#define RTL8367C_LUT_PORT3_LEARN_LIMITNO_OFFSET 0 +#define RTL8367C_LUT_PORT3_LEARN_LIMITNO_MASK 0x1FFF + +#define RTL8367C_REG_LUT_PORT4_LEARN_LIMITNO 0x0a24 +#define RTL8367C_LUT_PORT4_LEARN_LIMITNO_OFFSET 0 +#define RTL8367C_LUT_PORT4_LEARN_LIMITNO_MASK 0x1FFF + +#define RTL8367C_REG_LUT_PORT5_LEARN_LIMITNO 0x0a25 +#define RTL8367C_LUT_PORT5_LEARN_LIMITNO_OFFSET 0 +#define RTL8367C_LUT_PORT5_LEARN_LIMITNO_MASK 0x1FFF + +#define RTL8367C_REG_LUT_PORT6_LEARN_LIMITNO 0x0a26 +#define RTL8367C_LUT_PORT6_LEARN_LIMITNO_OFFSET 0 +#define RTL8367C_LUT_PORT6_LEARN_LIMITNO_MASK 0x1FFF + +#define RTL8367C_REG_LUT_PORT7_LEARN_LIMITNO 0x0a27 +#define RTL8367C_LUT_PORT7_LEARN_LIMITNO_OFFSET 0 +#define RTL8367C_LUT_PORT7_LEARN_LIMITNO_MASK 0x1FFF + +#define RTL8367C_REG_LUT_SYS_LEARN_LIMITNO 0x0a28 +#define RTL8367C_LUT_SYS_LEARN_LIMITNO_OFFSET 0 +#define RTL8367C_LUT_SYS_LEARN_LIMITNO_MASK 0x1FFF + +#define RTL8367C_REG_LUT_LRN_SYS_LMT_CTRL 0x0a29 +#define RTL8367C_LUT_SYSTEM_LEARN_PMASK1_OFFSET 12 +#define RTL8367C_LUT_SYSTEM_LEARN_PMASK1_MASK 0x7000 +#define RTL8367C_LUT_SYSTEM_LEARN_OVER_ACT_OFFSET 10 +#define RTL8367C_LUT_SYSTEM_LEARN_OVER_ACT_MASK 0xC00 +#define RTL8367C_LUT_SYSTEM_LEARN_PMASK_OFFSET 0 +#define RTL8367C_LUT_SYSTEM_LEARN_PMASK_MASK 0xFF + +#define RTL8367C_REG_LUT_PORT8_LEARN_LIMITNO 0x0a2a +#define RTL8367C_LUT_PORT8_LEARN_LIMITNO_OFFSET 0 +#define RTL8367C_LUT_PORT8_LEARN_LIMITNO_MASK 0x1FFF + +#define RTL8367C_REG_LUT_PORT9_LEARN_LIMITNO 0x0a2b +#define RTL8367C_LUT_PORT9_LEARN_LIMITNO_OFFSET 0 +#define RTL8367C_LUT_PORT9_LEARN_LIMITNO_MASK 0x1FFF + +#define RTL8367C_REG_LUT_PORT10_LEARN_LIMITNO 0x0a2c +#define RTL8367C_LUT_PORT10_LEARN_LIMITNO_OFFSET 0 +#define RTL8367C_LUT_PORT10_LEARN_LIMITNO_MASK 0x1FFF + +#define RTL8367C_REG_LUT_CFG 0x0a30 +#define RTL8367C_AGE_SPEED_OFFSET 8 +#define RTL8367C_AGE_SPEED_MASK 0x300 +#define RTL8367C_BCAM_DISABLE_OFFSET 6 +#define RTL8367C_BCAM_DISABLE_MASK 0x40 +#define RTL8367C_LINKDOWN_AGEOUT_OFFSET 5 +#define RTL8367C_LINKDOWN_AGEOUT_MASK 0x20 +#define RTL8367C_LUT_IPMC_HASH_OFFSET 4 +#define RTL8367C_LUT_IPMC_HASH_MASK 0x10 +#define RTL8367C_LUT_IPMC_LOOKUP_OP_OFFSET 3 +#define RTL8367C_LUT_IPMC_LOOKUP_OP_MASK 0x8 +#define RTL8367C_AGE_TIMER_OFFSET 0 +#define RTL8367C_AGE_TIMER_MASK 0x7 + +#define RTL8367C_REG_LUT_AGEOUT_CTRL 0x0a31 +#define RTL8367C_LUT_AGEOUT_CTRL_OFFSET 0 +#define RTL8367C_LUT_AGEOUT_CTRL_MASK 0x7FF + +#define RTL8367C_REG_PORT_EFID_CTRL0 0x0a32 +#define RTL8367C_PORT3_EFID_OFFSET 12 +#define RTL8367C_PORT3_EFID_MASK 0x7000 +#define RTL8367C_PORT2_EFID_OFFSET 8 +#define RTL8367C_PORT2_EFID_MASK 0x700 +#define RTL8367C_PORT1_EFID_OFFSET 4 +#define RTL8367C_PORT1_EFID_MASK 0x70 +#define RTL8367C_PORT0_EFID_OFFSET 0 +#define RTL8367C_PORT0_EFID_MASK 0x7 + +#define RTL8367C_REG_PORT_EFID_CTRL1 0x0a33 +#define RTL8367C_PORT7_EFID_OFFSET 12 +#define RTL8367C_PORT7_EFID_MASK 0x7000 +#define RTL8367C_PORT6_EFID_OFFSET 8 +#define RTL8367C_PORT6_EFID_MASK 0x700 +#define RTL8367C_PORT5_EFID_OFFSET 4 +#define RTL8367C_PORT5_EFID_MASK 0x70 +#define RTL8367C_PORT4_EFID_OFFSET 0 +#define RTL8367C_PORT4_EFID_MASK 0x7 + +#define RTL8367C_REG_PORT_EFID_CTRL2 0x0a34 +#define RTL8367C_PORT10_EFID_OFFSET 8 +#define RTL8367C_PORT10_EFID_MASK 0x700 +#define RTL8367C_PORT9_EFID_OFFSET 4 +#define RTL8367C_PORT9_EFID_MASK 0x70 +#define RTL8367C_PORT8_EFID_OFFSET 0 +#define RTL8367C_PORT8_EFID_MASK 0x7 + +#define RTL8367C_REG_FORCE_FLUSH1 0x0a35 +#define RTL8367C_BUSY_STATUS1_OFFSET 3 +#define RTL8367C_BUSY_STATUS1_MASK 0x38 +#define RTL8367C_PORTMASK1_OFFSET 0 +#define RTL8367C_PORTMASK1_MASK 0x7 + +#define RTL8367C_REG_FORCE_FLUSH 0x0a36 +#define RTL8367C_BUSY_STATUS_OFFSET 8 +#define RTL8367C_BUSY_STATUS_MASK 0xFF00 +#define RTL8367C_FORCE_FLUSH_PORTMASK_OFFSET 0 +#define RTL8367C_FORCE_FLUSH_PORTMASK_MASK 0xFF + +#define RTL8367C_REG_L2_FLUSH_CTRL1 0x0a37 +#define RTL8367C_LUT_FLUSH_FID_OFFSET 12 +#define RTL8367C_LUT_FLUSH_FID_MASK 0xF000 +#define RTL8367C_LUT_FLUSH_VID_OFFSET 0 +#define RTL8367C_LUT_FLUSH_VID_MASK 0xFFF + +#define RTL8367C_REG_L2_FLUSH_CTRL2 0x0a38 +#define RTL8367C_LUT_FLUSH_TYPE_OFFSET 2 +#define RTL8367C_LUT_FLUSH_TYPE_MASK 0x4 +#define RTL8367C_LUT_FLUSH_MODE_OFFSET 0 +#define RTL8367C_LUT_FLUSH_MODE_MASK 0x3 + +#define RTL8367C_REG_L2_FLUSH_CTRL3 0x0a39 +#define RTL8367C_L2_FLUSH_CTRL3_OFFSET 0 +#define RTL8367C_L2_FLUSH_CTRL3_MASK 0x1 + +#define RTL8367C_REG_LUT_CFG2 0x0a3a +#define RTL8367C_LUT_IPMC_FWD_RPORT_OFFSET 1 +#define RTL8367C_LUT_IPMC_FWD_RPORT_MASK 0x2 +#define RTL8367C_LUT_IPMC_VID_HASH_OFFSET 0 +#define RTL8367C_LUT_IPMC_VID_HASH_MASK 0x1 + +#define RTL8367C_REG_FLUSH_STATUS 0x0a3f +#define RTL8367C_FLUSH_STATUS_OFFSET 0 +#define RTL8367C_FLUSH_STATUS_MASK 0x1 + +#define RTL8367C_REG_STORM_BCAST 0x0a40 +#define RTL8367C_STORM_BCAST_OFFSET 0 +#define RTL8367C_STORM_BCAST_MASK 0x7FF + +#define RTL8367C_REG_STORM_MCAST 0x0a41 +#define RTL8367C_STORM_MCAST_OFFSET 0 +#define RTL8367C_STORM_MCAST_MASK 0x7FF + +#define RTL8367C_REG_STORM_UNKOWN_UCAST 0x0a42 +#define RTL8367C_STORM_UNKOWN_UCAST_OFFSET 0 +#define RTL8367C_STORM_UNKOWN_UCAST_MASK 0x7FF + +#define RTL8367C_REG_STORM_UNKOWN_MCAST 0x0a43 +#define RTL8367C_STORM_UNKOWN_MCAST_OFFSET 0 +#define RTL8367C_STORM_UNKOWN_MCAST_MASK 0x7FF + +#define RTL8367C_REG_STORM_BCAST_METER_CTRL0 0x0a44 +#define RTL8367C_STORM_BCAST_METER_CTRL0_PORT1_METERIDX_OFFSET 8 +#define RTL8367C_STORM_BCAST_METER_CTRL0_PORT1_METERIDX_MASK 0x3F00 +#define RTL8367C_STORM_BCAST_METER_CTRL0_PORT0_METERIDX_OFFSET 0 +#define RTL8367C_STORM_BCAST_METER_CTRL0_PORT0_METERIDX_MASK 0x3F + +#define RTL8367C_REG_STORM_BCAST_METER_CTRL1 0x0a45 +#define RTL8367C_STORM_BCAST_METER_CTRL1_PORT3_METERIDX_OFFSET 8 +#define RTL8367C_STORM_BCAST_METER_CTRL1_PORT3_METERIDX_MASK 0x3F00 +#define RTL8367C_STORM_BCAST_METER_CTRL1_PORT2_METERIDX_OFFSET 0 +#define RTL8367C_STORM_BCAST_METER_CTRL1_PORT2_METERIDX_MASK 0x3F + +#define RTL8367C_REG_STORM_BCAST_METER_CTRL2 0x0a46 +#define RTL8367C_STORM_BCAST_METER_CTRL2_PORT5_METERIDX_OFFSET 8 +#define RTL8367C_STORM_BCAST_METER_CTRL2_PORT5_METERIDX_MASK 0x3F00 +#define RTL8367C_STORM_BCAST_METER_CTRL2_PORT4_METERIDX_OFFSET 0 +#define RTL8367C_STORM_BCAST_METER_CTRL2_PORT4_METERIDX_MASK 0x3F + +#define RTL8367C_REG_STORM_BCAST_METER_CTRL3 0x0a47 +#define RTL8367C_STORM_BCAST_METER_CTRL3_PORT7_METERIDX_OFFSET 8 +#define RTL8367C_STORM_BCAST_METER_CTRL3_PORT7_METERIDX_MASK 0x3F00 +#define RTL8367C_STORM_BCAST_METER_CTRL3_PORT6_METERIDX_OFFSET 0 +#define RTL8367C_STORM_BCAST_METER_CTRL3_PORT6_METERIDX_MASK 0x3F + +#define RTL8367C_REG_STORM_BCAST_METER_CTRL4 0x0a48 +#define RTL8367C_STORM_BCAST_METER_CTRL4_PORT9_METERIDX_OFFSET 8 +#define RTL8367C_STORM_BCAST_METER_CTRL4_PORT9_METERIDX_MASK 0x3F00 +#define RTL8367C_STORM_BCAST_METER_CTRL4_PORT8_METERIDX_OFFSET 0 +#define RTL8367C_STORM_BCAST_METER_CTRL4_PORT8_METERIDX_MASK 0x3F + +#define RTL8367C_REG_STORM_BCAST_METER_CTRL5 0x0a49 +#define RTL8367C_STORM_BCAST_METER_CTRL5_OFFSET 0 +#define RTL8367C_STORM_BCAST_METER_CTRL5_MASK 0x3F + +#define RTL8367C_REG_STORM_MCAST_METER_CTRL0 0x0a4c +#define RTL8367C_STORM_MCAST_METER_CTRL0_PORT1_METERIDX_OFFSET 8 +#define RTL8367C_STORM_MCAST_METER_CTRL0_PORT1_METERIDX_MASK 0x3F00 +#define RTL8367C_STORM_MCAST_METER_CTRL0_PORT0_METERIDX_OFFSET 0 +#define RTL8367C_STORM_MCAST_METER_CTRL0_PORT0_METERIDX_MASK 0x3F + +#define RTL8367C_REG_STORM_MCAST_METER_CTRL1 0x0a4d +#define RTL8367C_STORM_MCAST_METER_CTRL1_PORT3_METERIDX_OFFSET 8 +#define RTL8367C_STORM_MCAST_METER_CTRL1_PORT3_METERIDX_MASK 0x3F00 +#define RTL8367C_STORM_MCAST_METER_CTRL1_PORT2_METERIDX_OFFSET 0 +#define RTL8367C_STORM_MCAST_METER_CTRL1_PORT2_METERIDX_MASK 0x3F + +#define RTL8367C_REG_STORM_MCAST_METER_CTRL2 0x0a4e +#define RTL8367C_STORM_MCAST_METER_CTRL2_PORT5_METERIDX_OFFSET 8 +#define RTL8367C_STORM_MCAST_METER_CTRL2_PORT5_METERIDX_MASK 0x3F00 +#define RTL8367C_STORM_MCAST_METER_CTRL2_PORT4_METERIDX_OFFSET 0 +#define RTL8367C_STORM_MCAST_METER_CTRL2_PORT4_METERIDX_MASK 0x3F + +#define RTL8367C_REG_STORM_MCAST_METER_CTRL3 0x0a4f +#define RTL8367C_STORM_MCAST_METER_CTRL3_PORT7_METERIDX_OFFSET 8 +#define RTL8367C_STORM_MCAST_METER_CTRL3_PORT7_METERIDX_MASK 0x3F00 +#define RTL8367C_STORM_MCAST_METER_CTRL3_PORT6_METERIDX_OFFSET 0 +#define RTL8367C_STORM_MCAST_METER_CTRL3_PORT6_METERIDX_MASK 0x3F + +#define RTL8367C_REG_STORM_MCAST_METER_CTRL4 0x0a50 +#define RTL8367C_STORM_MCAST_METER_CTRL4_PORT9_METERIDX_OFFSET 8 +#define RTL8367C_STORM_MCAST_METER_CTRL4_PORT9_METERIDX_MASK 0x3F00 +#define RTL8367C_STORM_MCAST_METER_CTRL4_PORT8_METERIDX_OFFSET 0 +#define RTL8367C_STORM_MCAST_METER_CTRL4_PORT8_METERIDX_MASK 0x3F + +#define RTL8367C_REG_STORM_MCAST_METER_CTRL5 0x0a51 +#define RTL8367C_STORM_MCAST_METER_CTRL5_OFFSET 0 +#define RTL8367C_STORM_MCAST_METER_CTRL5_MASK 0x3F + +#define RTL8367C_REG_STORM_UNDA_METER_CTRL0 0x0a54 +#define RTL8367C_STORM_UNDA_METER_CTRL0_PORT1_METERIDX_OFFSET 8 +#define RTL8367C_STORM_UNDA_METER_CTRL0_PORT1_METERIDX_MASK 0x3F00 +#define RTL8367C_STORM_UNDA_METER_CTRL0_PORT0_METERIDX_OFFSET 0 +#define RTL8367C_STORM_UNDA_METER_CTRL0_PORT0_METERIDX_MASK 0x3F + +#define RTL8367C_REG_STORM_UNDA_METER_CTRL1 0x0a55 +#define RTL8367C_STORM_UNDA_METER_CTRL1_PORT3_METERIDX_OFFSET 8 +#define RTL8367C_STORM_UNDA_METER_CTRL1_PORT3_METERIDX_MASK 0x3F00 +#define RTL8367C_STORM_UNDA_METER_CTRL1_PORT2_METERIDX_OFFSET 0 +#define RTL8367C_STORM_UNDA_METER_CTRL1_PORT2_METERIDX_MASK 0x3F + +#define RTL8367C_REG_STORM_UNDA_METER_CTRL2 0x0a56 +#define RTL8367C_STORM_UNDA_METER_CTRL2_PORT5_METERIDX_OFFSET 8 +#define RTL8367C_STORM_UNDA_METER_CTRL2_PORT5_METERIDX_MASK 0x3F00 +#define RTL8367C_STORM_UNDA_METER_CTRL2_PORT4_METERIDX_OFFSET 0 +#define RTL8367C_STORM_UNDA_METER_CTRL2_PORT4_METERIDX_MASK 0x3F + +#define RTL8367C_REG_STORM_UNDA_METER_CTRL3 0x0a57 +#define RTL8367C_STORM_UNDA_METER_CTRL3_PORT7_METERIDX_OFFSET 8 +#define RTL8367C_STORM_UNDA_METER_CTRL3_PORT7_METERIDX_MASK 0x3F00 +#define RTL8367C_STORM_UNDA_METER_CTRL3_PORT6_METERIDX_OFFSET 0 +#define RTL8367C_STORM_UNDA_METER_CTRL3_PORT6_METERIDX_MASK 0x3F + +#define RTL8367C_REG_STORM_UNDA_METER_CTRL4 0x0a58 +#define RTL8367C_STORM_UNDA_METER_CTRL4_PORT9_METERIDX_OFFSET 8 +#define RTL8367C_STORM_UNDA_METER_CTRL4_PORT9_METERIDX_MASK 0x3F00 +#define RTL8367C_STORM_UNDA_METER_CTRL4_PORT8_METERIDX_OFFSET 0 +#define RTL8367C_STORM_UNDA_METER_CTRL4_PORT8_METERIDX_MASK 0x3F + +#define RTL8367C_REG_STORM_UNDA_METER_CTRL5 0x0a59 +#define RTL8367C_STORM_UNDA_METER_CTRL5_OFFSET 0 +#define RTL8367C_STORM_UNDA_METER_CTRL5_MASK 0x3F + +#define RTL8367C_REG_STORM_UNMC_METER_CTRL0 0x0a5c +#define RTL8367C_STORM_UNMC_METER_CTRL0_PORT1_METERIDX_OFFSET 8 +#define RTL8367C_STORM_UNMC_METER_CTRL0_PORT1_METERIDX_MASK 0x3F00 +#define RTL8367C_STORM_UNMC_METER_CTRL0_PORT0_METERIDX_OFFSET 0 +#define RTL8367C_STORM_UNMC_METER_CTRL0_PORT0_METERIDX_MASK 0x3F + +#define RTL8367C_REG_STORM_UNMC_METER_CTRL1 0x0a5d +#define RTL8367C_STORM_UNMC_METER_CTRL1_PORT3_METERIDX_OFFSET 8 +#define RTL8367C_STORM_UNMC_METER_CTRL1_PORT3_METERIDX_MASK 0x3F00 +#define RTL8367C_STORM_UNMC_METER_CTRL1_PORT2_METERIDX_OFFSET 0 +#define RTL8367C_STORM_UNMC_METER_CTRL1_PORT2_METERIDX_MASK 0x3F + +#define RTL8367C_REG_STORM_UNMC_METER_CTRL2 0x0a5e +#define RTL8367C_STORM_UNMC_METER_CTRL2_PORT5_METERIDX_OFFSET 8 +#define RTL8367C_STORM_UNMC_METER_CTRL2_PORT5_METERIDX_MASK 0x3F00 +#define RTL8367C_STORM_UNMC_METER_CTRL2_PORT4_METERIDX_OFFSET 0 +#define RTL8367C_STORM_UNMC_METER_CTRL2_PORT4_METERIDX_MASK 0x3F + +#define RTL8367C_REG_STORM_UNMC_METER_CTRL3 0x0a5f +#define RTL8367C_STORM_UNMC_METER_CTRL3_PORT7_METERIDX_OFFSET 8 +#define RTL8367C_STORM_UNMC_METER_CTRL3_PORT7_METERIDX_MASK 0x3F00 +#define RTL8367C_STORM_UNMC_METER_CTRL3_PORT6_METERIDX_OFFSET 0 +#define RTL8367C_STORM_UNMC_METER_CTRL3_PORT6_METERIDX_MASK 0x3F + +#define RTL8367C_REG_STORM_EXT_CFG 0x0a60 +#define RTL8367C_STORM_EXT_EN_PORTMASK_EXT_OFFSET 14 +#define RTL8367C_STORM_EXT_EN_PORTMASK_EXT_MASK 0x4000 +#define RTL8367C_STORM_UNKNOWN_MCAST_EXT_EN_OFFSET 13 +#define RTL8367C_STORM_UNKNOWN_MCAST_EXT_EN_MASK 0x2000 +#define RTL8367C_STORM_UNKNOWN_UCAST_EXT_EN_OFFSET 12 +#define RTL8367C_STORM_UNKNOWN_UCAST_EXT_EN_MASK 0x1000 +#define RTL8367C_STORM_MCAST_EXT_EN_OFFSET 11 +#define RTL8367C_STORM_MCAST_EXT_EN_MASK 0x800 +#define RTL8367C_STORM_BCAST_EXT_EN_OFFSET 10 +#define RTL8367C_STORM_BCAST_EXT_EN_MASK 0x400 +#define RTL8367C_STORM_EXT_EN_PORTMASK_OFFSET 0 +#define RTL8367C_STORM_EXT_EN_PORTMASK_MASK 0x3FF + +#define RTL8367C_REG_STORM_EXT_MTRIDX_CFG0 0x0a61 +#define RTL8367C_MC_STORM_EXT_METERIDX_OFFSET 8 +#define RTL8367C_MC_STORM_EXT_METERIDX_MASK 0x3F00 +#define RTL8367C_BC_STORM_EXT_METERIDX_OFFSET 0 +#define RTL8367C_BC_STORM_EXT_METERIDX_MASK 0x3F + +#define RTL8367C_REG_STORM_EXT_MTRIDX_CFG1 0x0a62 +#define RTL8367C_UNMC_STORM_EXT_METERIDX_OFFSET 8 +#define RTL8367C_UNMC_STORM_EXT_METERIDX_MASK 0x3F00 +#define RTL8367C_UNUC_STORM_EXT_METERIDX_OFFSET 0 +#define RTL8367C_UNUC_STORM_EXT_METERIDX_MASK 0x3F + +#define RTL8367C_REG_STORM_UNMC_METER_CTRL4 0x0a63 +#define RTL8367C_STORM_UNMC_METER_CTRL4_PORT9_METERIDX_OFFSET 8 +#define RTL8367C_STORM_UNMC_METER_CTRL4_PORT9_METERIDX_MASK 0x3F00 +#define RTL8367C_STORM_UNMC_METER_CTRL4_PORT8_METERIDX_OFFSET 0 +#define RTL8367C_STORM_UNMC_METER_CTRL4_PORT8_METERIDX_MASK 0x3F + +#define RTL8367C_REG_STORM_UNMC_METER_CTRL5 0x0a64 +#define RTL8367C_STORM_UNMC_METER_CTRL5_OFFSET 0 +#define RTL8367C_STORM_UNMC_METER_CTRL5_MASK 0x3F + +#define RTL8367C_REG_OAM_PARSER_CTRL0 0x0a70 +#define RTL8367C_PORT7_PARACT_OFFSET 14 +#define RTL8367C_PORT7_PARACT_MASK 0xC000 +#define RTL8367C_PORT6_PARACT_OFFSET 12 +#define RTL8367C_PORT6_PARACT_MASK 0x3000 +#define RTL8367C_PORT5_PARACT_OFFSET 10 +#define RTL8367C_PORT5_PARACT_MASK 0xC00 +#define RTL8367C_PORT4_PARACT_OFFSET 8 +#define RTL8367C_PORT4_PARACT_MASK 0x300 +#define RTL8367C_PORT3_PARACT_OFFSET 6 +#define RTL8367C_PORT3_PARACT_MASK 0xC0 +#define RTL8367C_PORT2_PARACT_OFFSET 4 +#define RTL8367C_PORT2_PARACT_MASK 0x30 +#define RTL8367C_PORT1_PARACT_OFFSET 2 +#define RTL8367C_PORT1_PARACT_MASK 0xC +#define RTL8367C_PORT0_PARACT_OFFSET 0 +#define RTL8367C_PORT0_PARACT_MASK 0x3 + +#define RTL8367C_REG_OAM_PARSER_CTRL1 0x0a71 +#define RTL8367C_PORT10_PARACT_OFFSET 4 +#define RTL8367C_PORT10_PARACT_MASK 0x30 +#define RTL8367C_PORT9_PARACT_OFFSET 2 +#define RTL8367C_PORT9_PARACT_MASK 0xC +#define RTL8367C_PORT8_PARACT_OFFSET 0 +#define RTL8367C_PORT8_PARACT_MASK 0x3 + +#define RTL8367C_REG_OAM_MULTIPLEXER_CTRL0 0x0a72 +#define RTL8367C_PORT7_MULACT_OFFSET 14 +#define RTL8367C_PORT7_MULACT_MASK 0xC000 +#define RTL8367C_PORT6_MULACT_OFFSET 12 +#define RTL8367C_PORT6_MULACT_MASK 0x3000 +#define RTL8367C_PORT5_MULACT_OFFSET 10 +#define RTL8367C_PORT5_MULACT_MASK 0xC00 +#define RTL8367C_PORT4_MULACT_OFFSET 8 +#define RTL8367C_PORT4_MULACT_MASK 0x300 +#define RTL8367C_PORT3_MULACT_OFFSET 6 +#define RTL8367C_PORT3_MULACT_MASK 0xC0 +#define RTL8367C_PORT2_MULACT_OFFSET 4 +#define RTL8367C_PORT2_MULACT_MASK 0x30 +#define RTL8367C_PORT1_MULACT_OFFSET 2 +#define RTL8367C_PORT1_MULACT_MASK 0xC +#define RTL8367C_PORT0_MULACT_OFFSET 0 +#define RTL8367C_PORT0_MULACT_MASK 0x3 + +#define RTL8367C_REG_OAM_MULTIPLEXER_CTRL1 0x0a73 +#define RTL8367C_PORT10_MULACT_OFFSET 4 +#define RTL8367C_PORT10_MULACT_MASK 0x30 +#define RTL8367C_PORT9_MULACT_OFFSET 2 +#define RTL8367C_PORT9_MULACT_MASK 0xC +#define RTL8367C_PORT8_MULACT_OFFSET 0 +#define RTL8367C_PORT8_MULACT_MASK 0x3 + +#define RTL8367C_REG_OAM_CTRL 0x0a74 +#define RTL8367C_OAM_CTRL_OFFSET 0 +#define RTL8367C_OAM_CTRL_MASK 0x1 + +#define RTL8367C_REG_DOT1X_PORT_ENABLE 0x0a80 +#define RTL8367C_DOT1X_PORT_ENABLE_OFFSET 0 +#define RTL8367C_DOT1X_PORT_ENABLE_MASK 0x7FF + +#define RTL8367C_REG_DOT1X_MAC_ENABLE 0x0a81 +#define RTL8367C_DOT1X_MAC_ENABLE_OFFSET 0 +#define RTL8367C_DOT1X_MAC_ENABLE_MASK 0x7FF + +#define RTL8367C_REG_DOT1X_PORT_AUTH 0x0a82 +#define RTL8367C_DOT1X_PORT_AUTH_OFFSET 0 +#define RTL8367C_DOT1X_PORT_AUTH_MASK 0x7FF + +#define RTL8367C_REG_DOT1X_PORT_OPDIR 0x0a83 +#define RTL8367C_DOT1X_PORT_OPDIR_OFFSET 0 +#define RTL8367C_DOT1X_PORT_OPDIR_MASK 0x7FF + +#define RTL8367C_REG_DOT1X_UNAUTH_ACT_W0 0x0a84 +#define RTL8367C_DOT1X_PORT7_UNAUTHBH_OFFSET 14 +#define RTL8367C_DOT1X_PORT7_UNAUTHBH_MASK 0xC000 +#define RTL8367C_DOT1X_PORT6_UNAUTHBH_OFFSET 12 +#define RTL8367C_DOT1X_PORT6_UNAUTHBH_MASK 0x3000 +#define RTL8367C_DOT1X_PORT5_UNAUTHBH_OFFSET 10 +#define RTL8367C_DOT1X_PORT5_UNAUTHBH_MASK 0xC00 +#define RTL8367C_DOT1X_PORT4_UNAUTHBH_OFFSET 8 +#define RTL8367C_DOT1X_PORT4_UNAUTHBH_MASK 0x300 +#define RTL8367C_DOT1X_PORT3_UNAUTHBH_OFFSET 6 +#define RTL8367C_DOT1X_PORT3_UNAUTHBH_MASK 0xC0 +#define RTL8367C_DOT1X_PORT2_UNAUTHBH_OFFSET 4 +#define RTL8367C_DOT1X_PORT2_UNAUTHBH_MASK 0x30 +#define RTL8367C_DOT1X_PORT1_UNAUTHBH_OFFSET 2 +#define RTL8367C_DOT1X_PORT1_UNAUTHBH_MASK 0xC +#define RTL8367C_DOT1X_PORT0_UNAUTHBH_OFFSET 0 +#define RTL8367C_DOT1X_PORT0_UNAUTHBH_MASK 0x3 + +#define RTL8367C_REG_DOT1X_UNAUTH_ACT_W1 0x0a85 +#define RTL8367C_DOT1X_PORT10_UNAUTHBH_OFFSET 4 +#define RTL8367C_DOT1X_PORT10_UNAUTHBH_MASK 0x30 +#define RTL8367C_DOT1X_PORT9_UNAUTHBH_OFFSET 2 +#define RTL8367C_DOT1X_PORT9_UNAUTHBH_MASK 0xC +#define RTL8367C_DOT1X_PORT8_UNAUTHBH_OFFSET 0 +#define RTL8367C_DOT1X_PORT8_UNAUTHBH_MASK 0x3 + +#define RTL8367C_REG_DOT1X_CFG 0x0a86 +#define RTL8367C_DOT1X_GVOPDIR_OFFSET 6 +#define RTL8367C_DOT1X_GVOPDIR_MASK 0x40 +#define RTL8367C_DOT1X_MAC_OPDIR_OFFSET 5 +#define RTL8367C_DOT1X_MAC_OPDIR_MASK 0x20 +#define RTL8367C_DOT1X_GVIDX_OFFSET 0 +#define RTL8367C_DOT1X_GVIDX_MASK 0x1F + +#define RTL8367C_REG_L2_LRN_CNT_CTRL0 0x0a87 +#define RTL8367C_L2_LRN_CNT_CTRL0_OFFSET 0 +#define RTL8367C_L2_LRN_CNT_CTRL0_MASK 0x1FFF + +#define RTL8367C_REG_L2_LRN_CNT_CTRL1 0x0a88 +#define RTL8367C_L2_LRN_CNT_CTRL1_OFFSET 0 +#define RTL8367C_L2_LRN_CNT_CTRL1_MASK 0x1FFF + +#define RTL8367C_REG_L2_LRN_CNT_CTRL2 0x0a89 +#define RTL8367C_L2_LRN_CNT_CTRL2_OFFSET 0 +#define RTL8367C_L2_LRN_CNT_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_L2_LRN_CNT_CTRL3 0x0a8a +#define RTL8367C_L2_LRN_CNT_CTRL3_OFFSET 0 +#define RTL8367C_L2_LRN_CNT_CTRL3_MASK 0x1FFF + +#define RTL8367C_REG_L2_LRN_CNT_CTRL4 0x0a8b +#define RTL8367C_L2_LRN_CNT_CTRL4_OFFSET 0 +#define RTL8367C_L2_LRN_CNT_CTRL4_MASK 0x1FFF + +#define RTL8367C_REG_L2_LRN_CNT_CTRL5 0x0a8c +#define RTL8367C_L2_LRN_CNT_CTRL5_OFFSET 0 +#define RTL8367C_L2_LRN_CNT_CTRL5_MASK 0x1FFF + +#define RTL8367C_REG_L2_LRN_CNT_CTRL6 0x0a8d +#define RTL8367C_L2_LRN_CNT_CTRL6_OFFSET 0 +#define RTL8367C_L2_LRN_CNT_CTRL6_MASK 0x1FFF + +#define RTL8367C_REG_L2_LRN_CNT_CTRL7 0x0a8e +#define RTL8367C_L2_LRN_CNT_CTRL7_OFFSET 0 +#define RTL8367C_L2_LRN_CNT_CTRL7_MASK 0x1FFF + +#define RTL8367C_REG_L2_LRN_CNT_CTRL8 0x0a8f +#define RTL8367C_L2_LRN_CNT_CTRL8_OFFSET 0 +#define RTL8367C_L2_LRN_CNT_CTRL8_MASK 0x1FFF + +#define RTL8367C_REG_L2_LRN_CNT_CTRL9 0x0a90 +#define RTL8367C_L2_LRN_CNT_CTRL9_OFFSET 0 +#define RTL8367C_L2_LRN_CNT_CTRL9_MASK 0x1FFF + +#define RTL8367C_REG_L2_LRN_CNT_CTRL10 0x0a92 +#define RTL8367C_L2_LRN_CNT_CTRL10_OFFSET 0 +#define RTL8367C_L2_LRN_CNT_CTRL10_MASK 0x1FFF + +#define RTL8367C_REG_LUT_LRN_UNDER_STATUS 0x0a91 +#define RTL8367C_LUT_LRN_UNDER_STATUS_OFFSET 0 +#define RTL8367C_LUT_LRN_UNDER_STATUS_MASK 0x7FF + +#define RTL8367C_REG_L2_SA_MOVING_FORBID 0x0aa0 +#define RTL8367C_L2_SA_MOVING_FORBID_OFFSET 0 +#define RTL8367C_L2_SA_MOVING_FORBID_MASK 0x7FF + +#define RTL8367C_REG_DRPORT_LEARN_CTRL 0x0aa1 +#define RTL8367C_FORBID1_OFFSET 1 +#define RTL8367C_FORBID1_MASK 0x2 +#define RTL8367C_FORBID0_OFFSET 0 +#define RTL8367C_FORBID0_MASK 0x1 + +#define RTL8367C_REG_L2_DUMMY02 0x0aa2 + +#define RTL8367C_REG_L2_DUMMY03 0x0aa3 + +#define RTL8367C_REG_L2_DUMMY04 0x0aa4 + +#define RTL8367C_REG_L2_DUMMY05 0x0aa5 + +#define RTL8367C_REG_L2_DUMMY06 0x0aa6 + +#define RTL8367C_REG_L2_DUMMY07 0x0aa7 + +#define RTL8367C_REG_IPMC_GROUP_PMSK_00 0x0AC0 +#define RTL8367C_IPMC_GROUP_PMSK_00_OFFSET 0 +#define RTL8367C_IPMC_GROUP_PMSK_00_MASK 0x7FF + +#define RTL8367C_REG_IPMC_GROUP_PMSK_01 0x0AC1 +#define RTL8367C_IPMC_GROUP_PMSK_01_OFFSET 0 +#define RTL8367C_IPMC_GROUP_PMSK_01_MASK 0x7FF + +#define RTL8367C_REG_IPMC_GROUP_PMSK_02 0x0AC2 +#define RTL8367C_IPMC_GROUP_PMSK_02_OFFSET 0 +#define RTL8367C_IPMC_GROUP_PMSK_02_MASK 0x7FF + +#define RTL8367C_REG_IPMC_GROUP_PMSK_03 0x0AC3 +#define RTL8367C_IPMC_GROUP_PMSK_03_OFFSET 0 +#define RTL8367C_IPMC_GROUP_PMSK_03_MASK 0x7FF + +#define RTL8367C_REG_IPMC_GROUP_PMSK_04 0x0AC4 +#define RTL8367C_IPMC_GROUP_PMSK_04_OFFSET 0 +#define RTL8367C_IPMC_GROUP_PMSK_04_MASK 0x7FF + +#define RTL8367C_REG_IPMC_GROUP_PMSK_05 0x0AC5 +#define RTL8367C_IPMC_GROUP_PMSK_05_OFFSET 0 +#define RTL8367C_IPMC_GROUP_PMSK_05_MASK 0x7FF + +#define RTL8367C_REG_IPMC_GROUP_PMSK_06 0x0AC6 +#define RTL8367C_IPMC_GROUP_PMSK_06_OFFSET 0 +#define RTL8367C_IPMC_GROUP_PMSK_06_MASK 0x7FF + +#define RTL8367C_REG_IPMC_GROUP_PMSK_07 0x0AC7 +#define RTL8367C_IPMC_GROUP_PMSK_07_OFFSET 0 +#define RTL8367C_IPMC_GROUP_PMSK_07_MASK 0x7FF + +#define RTL8367C_REG_IPMC_GROUP_PMSK_08 0x0AC8 +#define RTL8367C_IPMC_GROUP_PMSK_08_OFFSET 0 +#define RTL8367C_IPMC_GROUP_PMSK_08_MASK 0x7FF + +#define RTL8367C_REG_IPMC_GROUP_PMSK_09 0x0AC9 +#define RTL8367C_IPMC_GROUP_PMSK_09_OFFSET 0 +#define RTL8367C_IPMC_GROUP_PMSK_09_MASK 0x7FF + +#define RTL8367C_REG_IPMC_GROUP_PMSK_10 0x0ACA +#define RTL8367C_IPMC_GROUP_PMSK_10_OFFSET 0 +#define RTL8367C_IPMC_GROUP_PMSK_10_MASK 0x7FF + +#define RTL8367C_REG_IPMC_GROUP_PMSK_11 0x0ACB +#define RTL8367C_IPMC_GROUP_PMSK_11_OFFSET 0 +#define RTL8367C_IPMC_GROUP_PMSK_11_MASK 0x7FF + +#define RTL8367C_REG_IPMC_GROUP_PMSK_12 0x0ACC +#define RTL8367C_IPMC_GROUP_PMSK_12_OFFSET 0 +#define RTL8367C_IPMC_GROUP_PMSK_12_MASK 0x7FF + +#define RTL8367C_REG_IPMC_GROUP_PMSK_13 0x0ACD +#define RTL8367C_IPMC_GROUP_PMSK_13_OFFSET 0 +#define RTL8367C_IPMC_GROUP_PMSK_13_MASK 0x7FF + +#define RTL8367C_REG_IPMC_GROUP_PMSK_14 0x0ACE +#define RTL8367C_IPMC_GROUP_PMSK_14_OFFSET 0 +#define RTL8367C_IPMC_GROUP_PMSK_14_MASK 0x7FF + +#define RTL8367C_REG_IPMC_GROUP_PMSK_15 0x0ACF +#define RTL8367C_IPMC_GROUP_PMSK_15_OFFSET 0 +#define RTL8367C_IPMC_GROUP_PMSK_15_MASK 0x7FF + +#define RTL8367C_REG_IPMC_GROUP_PMSK_16 0x0AD0 +#define RTL8367C_IPMC_GROUP_PMSK_16_OFFSET 0 +#define RTL8367C_IPMC_GROUP_PMSK_16_MASK 0x7FF + +#define RTL8367C_REG_IPMC_GROUP_PMSK_17 0x0AD1 +#define RTL8367C_IPMC_GROUP_PMSK_17_OFFSET 0 +#define RTL8367C_IPMC_GROUP_PMSK_17_MASK 0x7FF + +#define RTL8367C_REG_IPMC_GROUP_PMSK_18 0x0AD2 +#define RTL8367C_IPMC_GROUP_PMSK_18_OFFSET 0 +#define RTL8367C_IPMC_GROUP_PMSK_18_MASK 0x7FF + +#define RTL8367C_REG_IPMC_GROUP_PMSK_19 0x0AD3 +#define RTL8367C_IPMC_GROUP_PMSK_19_OFFSET 0 +#define RTL8367C_IPMC_GROUP_PMSK_19_MASK 0x7FF + +#define RTL8367C_REG_IPMC_GROUP_PMSK_20 0x0AD4 +#define RTL8367C_IPMC_GROUP_PMSK_20_OFFSET 0 +#define RTL8367C_IPMC_GROUP_PMSK_20_MASK 0x7FF + +#define RTL8367C_REG_IPMC_GROUP_PMSK_21 0x0AD5 +#define RTL8367C_IPMC_GROUP_PMSK_21_OFFSET 0 +#define RTL8367C_IPMC_GROUP_PMSK_21_MASK 0x7FF + +#define RTL8367C_REG_IPMC_GROUP_PMSK_22 0x0AD6 +#define RTL8367C_IPMC_GROUP_PMSK_22_OFFSET 0 +#define RTL8367C_IPMC_GROUP_PMSK_22_MASK 0x7FF + +#define RTL8367C_REG_IPMC_GROUP_PMSK_23 0x0AD7 +#define RTL8367C_IPMC_GROUP_PMSK_23_OFFSET 0 +#define RTL8367C_IPMC_GROUP_PMSK_23_MASK 0x7FF + +#define RTL8367C_REG_IPMC_GROUP_PMSK_24 0x0AD8 +#define RTL8367C_IPMC_GROUP_PMSK_24_OFFSET 0 +#define RTL8367C_IPMC_GROUP_PMSK_24_MASK 0x7FF + +#define RTL8367C_REG_IPMC_GROUP_PMSK_25 0x0AD9 +#define RTL8367C_IPMC_GROUP_PMSK_25_OFFSET 0 +#define RTL8367C_IPMC_GROUP_PMSK_25_MASK 0x7FF + +#define RTL8367C_REG_IPMC_GROUP_PMSK_26 0x0ADA +#define RTL8367C_IPMC_GROUP_PMSK_26_OFFSET 0 +#define RTL8367C_IPMC_GROUP_PMSK_26_MASK 0x7FF + +#define RTL8367C_REG_IPMC_GROUP_PMSK_27 0x0ADB +#define RTL8367C_IPMC_GROUP_PMSK_27_OFFSET 0 +#define RTL8367C_IPMC_GROUP_PMSK_27_MASK 0x7FF + +#define RTL8367C_REG_IPMC_GROUP_PMSK_28 0x0ADC +#define RTL8367C_IPMC_GROUP_PMSK_28_OFFSET 0 +#define RTL8367C_IPMC_GROUP_PMSK_28_MASK 0x7FF + +#define RTL8367C_REG_IPMC_GROUP_PMSK_29 0x0ADD +#define RTL8367C_IPMC_GROUP_PMSK_29_OFFSET 0 +#define RTL8367C_IPMC_GROUP_PMSK_29_MASK 0x7FF + +#define RTL8367C_REG_IPMC_GROUP_PMSK_30 0x0ADE +#define RTL8367C_IPMC_GROUP_PMSK_30_OFFSET 0 +#define RTL8367C_IPMC_GROUP_PMSK_30_MASK 0x7FF + +#define RTL8367C_REG_IPMC_GROUP_PMSK_31 0x0ADF +#define RTL8367C_IPMC_GROUP_PMSK_31_OFFSET 0 +#define RTL8367C_IPMC_GROUP_PMSK_31_MASK 0x7FF + +#define RTL8367C_REG_IPMC_GROUP_PMSK_32 0x0AE0 +#define RTL8367C_IPMC_GROUP_PMSK_32_OFFSET 0 +#define RTL8367C_IPMC_GROUP_PMSK_32_MASK 0x7FF + +#define RTL8367C_REG_IPMC_GROUP_PMSK_33 0x0AE1 +#define RTL8367C_IPMC_GROUP_PMSK_33_OFFSET 0 +#define RTL8367C_IPMC_GROUP_PMSK_33_MASK 0x7FF + +#define RTL8367C_REG_IPMC_GROUP_PMSK_34 0x0AE2 +#define RTL8367C_IPMC_GROUP_PMSK_34_OFFSET 0 +#define RTL8367C_IPMC_GROUP_PMSK_34_MASK 0x7FF + +#define RTL8367C_REG_IPMC_GROUP_PMSK_35 0x0AE3 +#define RTL8367C_IPMC_GROUP_PMSK_35_OFFSET 0 +#define RTL8367C_IPMC_GROUP_PMSK_35_MASK 0x7FF + +#define RTL8367C_REG_IPMC_GROUP_PMSK_36 0x0AE4 +#define RTL8367C_IPMC_GROUP_PMSK_36_OFFSET 0 +#define RTL8367C_IPMC_GROUP_PMSK_36_MASK 0x7FF + +#define RTL8367C_REG_IPMC_GROUP_PMSK_37 0x0AE5 +#define RTL8367C_IPMC_GROUP_PMSK_37_OFFSET 0 +#define RTL8367C_IPMC_GROUP_PMSK_37_MASK 0x7FF + +#define RTL8367C_REG_IPMC_GROUP_PMSK_38 0x0AE6 +#define RTL8367C_IPMC_GROUP_PMSK_38_OFFSET 0 +#define RTL8367C_IPMC_GROUP_PMSK_38_MASK 0x7FF + +#define RTL8367C_REG_IPMC_GROUP_PMSK_39 0x0AE7 +#define RTL8367C_IPMC_GROUP_PMSK_39_OFFSET 0 +#define RTL8367C_IPMC_GROUP_PMSK_39_MASK 0x7FF + +#define RTL8367C_REG_IPMC_GROUP_PMSK_40 0x0AE8 +#define RTL8367C_IPMC_GROUP_PMSK_40_OFFSET 0 +#define RTL8367C_IPMC_GROUP_PMSK_40_MASK 0x7FF + +#define RTL8367C_REG_IPMC_GROUP_PMSK_41 0x0AE9 +#define RTL8367C_IPMC_GROUP_PMSK_41_OFFSET 0 +#define RTL8367C_IPMC_GROUP_PMSK_41_MASK 0x7FF + +#define RTL8367C_REG_IPMC_GROUP_PMSK_42 0x0AEA +#define RTL8367C_IPMC_GROUP_PMSK_42_OFFSET 0 +#define RTL8367C_IPMC_GROUP_PMSK_42_MASK 0x7FF + +#define RTL8367C_REG_IPMC_GROUP_PMSK_43 0x0AEB +#define RTL8367C_IPMC_GROUP_PMSK_43_OFFSET 0 +#define RTL8367C_IPMC_GROUP_PMSK_43_MASK 0x7FF + +#define RTL8367C_REG_IPMC_GROUP_PMSK_44 0x0AEC +#define RTL8367C_IPMC_GROUP_PMSK_44_OFFSET 0 +#define RTL8367C_IPMC_GROUP_PMSK_44_MASK 0x7FF + +#define RTL8367C_REG_IPMC_GROUP_PMSK_45 0x0AED +#define RTL8367C_IPMC_GROUP_PMSK_45_OFFSET 0 +#define RTL8367C_IPMC_GROUP_PMSK_45_MASK 0x7FF + +#define RTL8367C_REG_IPMC_GROUP_PMSK_46 0x0AEE +#define RTL8367C_IPMC_GROUP_PMSK_46_OFFSET 0 +#define RTL8367C_IPMC_GROUP_PMSK_46_MASK 0x7FF + +#define RTL8367C_REG_IPMC_GROUP_PMSK_47 0x0AEF +#define RTL8367C_IPMC_GROUP_PMSK_47_OFFSET 0 +#define RTL8367C_IPMC_GROUP_PMSK_47_MASK 0x7FF + +#define RTL8367C_REG_IPMC_GROUP_PMSK_48 0x0AF0 +#define RTL8367C_IPMC_GROUP_PMSK_48_OFFSET 0 +#define RTL8367C_IPMC_GROUP_PMSK_48_MASK 0x7FF + +#define RTL8367C_REG_IPMC_GROUP_PMSK_49 0x0AF1 +#define RTL8367C_IPMC_GROUP_PMSK_49_OFFSET 0 +#define RTL8367C_IPMC_GROUP_PMSK_49_MASK 0x7FF + +#define RTL8367C_REG_IPMC_GROUP_PMSK_50 0x0AF2 +#define RTL8367C_IPMC_GROUP_PMSK_50_OFFSET 0 +#define RTL8367C_IPMC_GROUP_PMSK_50_MASK 0x7FF + +#define RTL8367C_REG_IPMC_GROUP_PMSK_51 0x0AF3 +#define RTL8367C_IPMC_GROUP_PMSK_51_OFFSET 0 +#define RTL8367C_IPMC_GROUP_PMSK_51_MASK 0x7FF + +#define RTL8367C_REG_IPMC_GROUP_PMSK_52 0x0AF4 +#define RTL8367C_IPMC_GROUP_PMSK_52_OFFSET 0 +#define RTL8367C_IPMC_GROUP_PMSK_52_MASK 0x7FF + +#define RTL8367C_REG_IPMC_GROUP_PMSK_53 0x0AF5 +#define RTL8367C_IPMC_GROUP_PMSK_53_OFFSET 0 +#define RTL8367C_IPMC_GROUP_PMSK_53_MASK 0x7FF + +#define RTL8367C_REG_IPMC_GROUP_PMSK_54 0x0AF6 +#define RTL8367C_IPMC_GROUP_PMSK_54_OFFSET 0 +#define RTL8367C_IPMC_GROUP_PMSK_54_MASK 0x7FF + +#define RTL8367C_REG_IPMC_GROUP_PMSK_55 0x0AF7 +#define RTL8367C_IPMC_GROUP_PMSK_55_OFFSET 0 +#define RTL8367C_IPMC_GROUP_PMSK_55_MASK 0x7FF + +#define RTL8367C_REG_IPMC_GROUP_PMSK_56 0x0AF8 +#define RTL8367C_IPMC_GROUP_PMSK_56_OFFSET 0 +#define RTL8367C_IPMC_GROUP_PMSK_56_MASK 0x7FF + +#define RTL8367C_REG_IPMC_GROUP_PMSK_57 0x0AF9 +#define RTL8367C_IPMC_GROUP_PMSK_57_OFFSET 0 +#define RTL8367C_IPMC_GROUP_PMSK_57_MASK 0x7FF + +#define RTL8367C_REG_IPMC_GROUP_PMSK_58 0x0AFA +#define RTL8367C_IPMC_GROUP_PMSK_58_OFFSET 0 +#define RTL8367C_IPMC_GROUP_PMSK_58_MASK 0x7FF + +#define RTL8367C_REG_IPMC_GROUP_PMSK_59 0x0AFB +#define RTL8367C_IPMC_GROUP_PMSK_59_OFFSET 0 +#define RTL8367C_IPMC_GROUP_PMSK_59_MASK 0x7FF + +#define RTL8367C_REG_IPMC_GROUP_PMSK_60 0x0AFC +#define RTL8367C_IPMC_GROUP_PMSK_60_OFFSET 0 +#define RTL8367C_IPMC_GROUP_PMSK_60_MASK 0x7FF + +#define RTL8367C_REG_IPMC_GROUP_PMSK_61 0x0AFD +#define RTL8367C_IPMC_GROUP_PMSK_61_OFFSET 0 +#define RTL8367C_IPMC_GROUP_PMSK_61_MASK 0x7FF + +#define RTL8367C_REG_IPMC_GROUP_PMSK_62 0x0AFE +#define RTL8367C_IPMC_GROUP_PMSK_62_OFFSET 0 +#define RTL8367C_IPMC_GROUP_PMSK_62_MASK 0x7FF + +#define RTL8367C_REG_IPMC_GROUP_PMSK_63 0x0AFF +#define RTL8367C_IPMC_GROUP_PMSK_63_OFFSET 0 +#define RTL8367C_IPMC_GROUP_PMSK_63_MASK 0x7FF + +/* (16'h0b00)mltvlan_reg */ + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY0_CTRL0 0x0b00 +#define RTL8367C_SVLAN_MCAST2S_ENTRY0_CTRL0_VALID_OFFSET 7 +#define RTL8367C_SVLAN_MCAST2S_ENTRY0_CTRL0_VALID_MASK 0x80 +#define RTL8367C_SVLAN_MCAST2S_ENTRY0_CTRL0_FORMAT_OFFSET 6 +#define RTL8367C_SVLAN_MCAST2S_ENTRY0_CTRL0_FORMAT_MASK 0x40 +#define RTL8367C_SVLAN_MCAST2S_ENTRY0_CTRL0_SVIDX_OFFSET 0 +#define RTL8367C_SVLAN_MCAST2S_ENTRY0_CTRL0_SVIDX_MASK 0x3F + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY0_CTRL1 0x0b01 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY0_CTRL2 0x0b02 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY0_CTRL3 0x0b03 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY0_CTRL4 0x0b04 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY1_CTRL0 0x0b05 +#define RTL8367C_SVLAN_MCAST2S_ENTRY1_CTRL0_VALID_OFFSET 7 +#define RTL8367C_SVLAN_MCAST2S_ENTRY1_CTRL0_VALID_MASK 0x80 +#define RTL8367C_SVLAN_MCAST2S_ENTRY1_CTRL0_FORMAT_OFFSET 6 +#define RTL8367C_SVLAN_MCAST2S_ENTRY1_CTRL0_FORMAT_MASK 0x40 +#define RTL8367C_SVLAN_MCAST2S_ENTRY1_CTRL0_SVIDX_OFFSET 0 +#define RTL8367C_SVLAN_MCAST2S_ENTRY1_CTRL0_SVIDX_MASK 0x3F + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY1_CTRL1 0x0b06 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY1_CTRL2 0x0b07 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY1_CTRL3 0x0b08 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY1_CTRL4 0x0b09 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY2_CTRL0 0x0b0a +#define RTL8367C_SVLAN_MCAST2S_ENTRY2_CTRL0_VALID_OFFSET 7 +#define RTL8367C_SVLAN_MCAST2S_ENTRY2_CTRL0_VALID_MASK 0x80 +#define RTL8367C_SVLAN_MCAST2S_ENTRY2_CTRL0_FORMAT_OFFSET 6 +#define RTL8367C_SVLAN_MCAST2S_ENTRY2_CTRL0_FORMAT_MASK 0x40 +#define RTL8367C_SVLAN_MCAST2S_ENTRY2_CTRL0_SVIDX_OFFSET 0 +#define RTL8367C_SVLAN_MCAST2S_ENTRY2_CTRL0_SVIDX_MASK 0x3F + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY2_CTRL1 0x0b0b + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY2_CTRL2 0x0b0c + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY2_CTRL3 0x0b0d + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY2_CTRL4 0x0b0e + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY3_CTRL0 0x0b0f +#define RTL8367C_SVLAN_MCAST2S_ENTRY3_CTRL0_VALID_OFFSET 7 +#define RTL8367C_SVLAN_MCAST2S_ENTRY3_CTRL0_VALID_MASK 0x80 +#define RTL8367C_SVLAN_MCAST2S_ENTRY3_CTRL0_FORMAT_OFFSET 6 +#define RTL8367C_SVLAN_MCAST2S_ENTRY3_CTRL0_FORMAT_MASK 0x40 +#define RTL8367C_SVLAN_MCAST2S_ENTRY3_CTRL0_SVIDX_OFFSET 0 +#define RTL8367C_SVLAN_MCAST2S_ENTRY3_CTRL0_SVIDX_MASK 0x3F + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY3_CTRL1 0x0b10 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY3_CTRL2 0x0b11 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY3_CTRL3 0x0b12 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY3_CTRL4 0x0b13 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY4_CTRL0 0x0b14 +#define RTL8367C_SVLAN_MCAST2S_ENTRY4_CTRL0_VALID_OFFSET 7 +#define RTL8367C_SVLAN_MCAST2S_ENTRY4_CTRL0_VALID_MASK 0x80 +#define RTL8367C_SVLAN_MCAST2S_ENTRY4_CTRL0_FORMAT_OFFSET 6 +#define RTL8367C_SVLAN_MCAST2S_ENTRY4_CTRL0_FORMAT_MASK 0x40 +#define RTL8367C_SVLAN_MCAST2S_ENTRY4_CTRL0_SVIDX_OFFSET 0 +#define RTL8367C_SVLAN_MCAST2S_ENTRY4_CTRL0_SVIDX_MASK 0x3F + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY4_CTRL1 0x0b15 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY4_CTRL2 0x0b16 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY4_CTRL3 0x0b17 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY4_CTRL4 0x0b18 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY5_CTRL0 0x0b19 +#define RTL8367C_SVLAN_MCAST2S_ENTRY5_CTRL0_VALID_OFFSET 7 +#define RTL8367C_SVLAN_MCAST2S_ENTRY5_CTRL0_VALID_MASK 0x80 +#define RTL8367C_SVLAN_MCAST2S_ENTRY5_CTRL0_FORMAT_OFFSET 6 +#define RTL8367C_SVLAN_MCAST2S_ENTRY5_CTRL0_FORMAT_MASK 0x40 +#define RTL8367C_SVLAN_MCAST2S_ENTRY5_CTRL0_SVIDX_OFFSET 0 +#define RTL8367C_SVLAN_MCAST2S_ENTRY5_CTRL0_SVIDX_MASK 0x3F + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY5_CTRL1 0x0b1a + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY5_CTRL2 0x0b1b + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY5_CTRL3 0x0b1c + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY5_CTRL4 0x0b1d + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY6_CTRL0 0x0b1e +#define RTL8367C_SVLAN_MCAST2S_ENTRY6_CTRL0_VALID_OFFSET 7 +#define RTL8367C_SVLAN_MCAST2S_ENTRY6_CTRL0_VALID_MASK 0x80 +#define RTL8367C_SVLAN_MCAST2S_ENTRY6_CTRL0_FORMAT_OFFSET 6 +#define RTL8367C_SVLAN_MCAST2S_ENTRY6_CTRL0_FORMAT_MASK 0x40 +#define RTL8367C_SVLAN_MCAST2S_ENTRY6_CTRL0_SVIDX_OFFSET 0 +#define RTL8367C_SVLAN_MCAST2S_ENTRY6_CTRL0_SVIDX_MASK 0x3F + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY6_CTRL1 0x0b1f + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY6_CTRL2 0x0b20 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY6_CTRL3 0x0b21 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY6_CTRL4 0x0b22 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY7_CTRL0 0x0b23 +#define RTL8367C_SVLAN_MCAST2S_ENTRY7_CTRL0_VALID_OFFSET 7 +#define RTL8367C_SVLAN_MCAST2S_ENTRY7_CTRL0_VALID_MASK 0x80 +#define RTL8367C_SVLAN_MCAST2S_ENTRY7_CTRL0_FORMAT_OFFSET 6 +#define RTL8367C_SVLAN_MCAST2S_ENTRY7_CTRL0_FORMAT_MASK 0x40 +#define RTL8367C_SVLAN_MCAST2S_ENTRY7_CTRL0_SVIDX_OFFSET 0 +#define RTL8367C_SVLAN_MCAST2S_ENTRY7_CTRL0_SVIDX_MASK 0x3F + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY7_CTRL1 0x0b24 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY7_CTRL2 0x0b25 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY7_CTRL3 0x0b26 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY7_CTRL4 0x0b27 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY8_CTRL0 0x0b28 +#define RTL8367C_SVLAN_MCAST2S_ENTRY8_CTRL0_VALID_OFFSET 7 +#define RTL8367C_SVLAN_MCAST2S_ENTRY8_CTRL0_VALID_MASK 0x80 +#define RTL8367C_SVLAN_MCAST2S_ENTRY8_CTRL0_FORMAT_OFFSET 6 +#define RTL8367C_SVLAN_MCAST2S_ENTRY8_CTRL0_FORMAT_MASK 0x40 +#define RTL8367C_SVLAN_MCAST2S_ENTRY8_CTRL0_SVIDX_OFFSET 0 +#define RTL8367C_SVLAN_MCAST2S_ENTRY8_CTRL0_SVIDX_MASK 0x3F + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY8_CTRL1 0x0b29 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY8_CTRL2 0x0b2a + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY8_CTRL3 0x0b2b + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY8_CTRL4 0x0b2c + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY9_CTRL0 0x0b2d +#define RTL8367C_SVLAN_MCAST2S_ENTRY9_CTRL0_VALID_OFFSET 7 +#define RTL8367C_SVLAN_MCAST2S_ENTRY9_CTRL0_VALID_MASK 0x80 +#define RTL8367C_SVLAN_MCAST2S_ENTRY9_CTRL0_FORMAT_OFFSET 6 +#define RTL8367C_SVLAN_MCAST2S_ENTRY9_CTRL0_FORMAT_MASK 0x40 +#define RTL8367C_SVLAN_MCAST2S_ENTRY9_CTRL0_SVIDX_OFFSET 0 +#define RTL8367C_SVLAN_MCAST2S_ENTRY9_CTRL0_SVIDX_MASK 0x3F + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY9_CTRL1 0x0b2e + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY9_CTRL2 0x0b2f + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY9_CTRL3 0x0b30 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY9_CTRL4 0x0b31 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY10_CTRL0 0x0b32 +#define RTL8367C_SVLAN_MCAST2S_ENTRY10_CTRL0_VALID_OFFSET 7 +#define RTL8367C_SVLAN_MCAST2S_ENTRY10_CTRL0_VALID_MASK 0x80 +#define RTL8367C_SVLAN_MCAST2S_ENTRY10_CTRL0_FORMAT_OFFSET 6 +#define RTL8367C_SVLAN_MCAST2S_ENTRY10_CTRL0_FORMAT_MASK 0x40 +#define RTL8367C_SVLAN_MCAST2S_ENTRY10_CTRL0_SVIDX_OFFSET 0 +#define RTL8367C_SVLAN_MCAST2S_ENTRY10_CTRL0_SVIDX_MASK 0x3F + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY10_CTRL1 0x0b33 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY10_CTRL2 0x0b34 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY10_CTRL3 0x0b35 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY10_CTRL4 0x0b36 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY11_CTRL0 0x0b37 +#define RTL8367C_SVLAN_MCAST2S_ENTRY11_CTRL0_VALID_OFFSET 7 +#define RTL8367C_SVLAN_MCAST2S_ENTRY11_CTRL0_VALID_MASK 0x80 +#define RTL8367C_SVLAN_MCAST2S_ENTRY11_CTRL0_FORMAT_OFFSET 6 +#define RTL8367C_SVLAN_MCAST2S_ENTRY11_CTRL0_FORMAT_MASK 0x40 +#define RTL8367C_SVLAN_MCAST2S_ENTRY11_CTRL0_SVIDX_OFFSET 0 +#define RTL8367C_SVLAN_MCAST2S_ENTRY11_CTRL0_SVIDX_MASK 0x3F + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY11_CTRL1 0x0b38 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY11_CTRL2 0x0b39 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY11_CTRL3 0x0b3a + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY11_CTRL4 0x0b3b + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY12_CTRL0 0x0b3c +#define RTL8367C_SVLAN_MCAST2S_ENTRY12_CTRL0_VALID_OFFSET 7 +#define RTL8367C_SVLAN_MCAST2S_ENTRY12_CTRL0_VALID_MASK 0x80 +#define RTL8367C_SVLAN_MCAST2S_ENTRY12_CTRL0_FORMAT_OFFSET 6 +#define RTL8367C_SVLAN_MCAST2S_ENTRY12_CTRL0_FORMAT_MASK 0x40 +#define RTL8367C_SVLAN_MCAST2S_ENTRY12_CTRL0_SVIDX_OFFSET 0 +#define RTL8367C_SVLAN_MCAST2S_ENTRY12_CTRL0_SVIDX_MASK 0x3F + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY12_CTRL1 0x0b3d + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY12_CTRL2 0x0b3e + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY12_CTRL3 0x0b3f + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY12_CTRL4 0x0b40 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY13_CTRL0 0x0b41 +#define RTL8367C_SVLAN_MCAST2S_ENTRY13_CTRL0_VALID_OFFSET 7 +#define RTL8367C_SVLAN_MCAST2S_ENTRY13_CTRL0_VALID_MASK 0x80 +#define RTL8367C_SVLAN_MCAST2S_ENTRY13_CTRL0_FORMAT_OFFSET 6 +#define RTL8367C_SVLAN_MCAST2S_ENTRY13_CTRL0_FORMAT_MASK 0x40 +#define RTL8367C_SVLAN_MCAST2S_ENTRY13_CTRL0_SVIDX_OFFSET 0 +#define RTL8367C_SVLAN_MCAST2S_ENTRY13_CTRL0_SVIDX_MASK 0x3F + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY13_CTRL1 0x0b42 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY13_CTRL2 0x0b43 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY13_CTRL3 0x0b44 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY13_CTRL4 0x0b45 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY14_CTRL0 0x0b46 +#define RTL8367C_SVLAN_MCAST2S_ENTRY14_CTRL0_VALID_OFFSET 7 +#define RTL8367C_SVLAN_MCAST2S_ENTRY14_CTRL0_VALID_MASK 0x80 +#define RTL8367C_SVLAN_MCAST2S_ENTRY14_CTRL0_FORMAT_OFFSET 6 +#define RTL8367C_SVLAN_MCAST2S_ENTRY14_CTRL0_FORMAT_MASK 0x40 +#define RTL8367C_SVLAN_MCAST2S_ENTRY14_CTRL0_SVIDX_OFFSET 0 +#define RTL8367C_SVLAN_MCAST2S_ENTRY14_CTRL0_SVIDX_MASK 0x3F + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY14_CTRL1 0x0b47 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY14_CTRL2 0x0b48 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY14_CTRL3 0x0b49 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY14_CTRL4 0x0b4a + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY15_CTRL0 0x0b4b +#define RTL8367C_SVLAN_MCAST2S_ENTRY15_CTRL0_VALID_OFFSET 7 +#define RTL8367C_SVLAN_MCAST2S_ENTRY15_CTRL0_VALID_MASK 0x80 +#define RTL8367C_SVLAN_MCAST2S_ENTRY15_CTRL0_FORMAT_OFFSET 6 +#define RTL8367C_SVLAN_MCAST2S_ENTRY15_CTRL0_FORMAT_MASK 0x40 +#define RTL8367C_SVLAN_MCAST2S_ENTRY15_CTRL0_SVIDX_OFFSET 0 +#define RTL8367C_SVLAN_MCAST2S_ENTRY15_CTRL0_SVIDX_MASK 0x3F + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY15_CTRL1 0x0b4c + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY15_CTRL2 0x0b4d + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY15_CTRL3 0x0b4e + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY15_CTRL4 0x0b4f + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY16_CTRL0 0x0b50 +#define RTL8367C_SVLAN_MCAST2S_ENTRY16_CTRL0_VALID_OFFSET 7 +#define RTL8367C_SVLAN_MCAST2S_ENTRY16_CTRL0_VALID_MASK 0x80 +#define RTL8367C_SVLAN_MCAST2S_ENTRY16_CTRL0_FORMAT_OFFSET 6 +#define RTL8367C_SVLAN_MCAST2S_ENTRY16_CTRL0_FORMAT_MASK 0x40 +#define RTL8367C_SVLAN_MCAST2S_ENTRY16_CTRL0_SVIDX_OFFSET 0 +#define RTL8367C_SVLAN_MCAST2S_ENTRY16_CTRL0_SVIDX_MASK 0x3F + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY16_CTRL1 0x0b51 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY16_CTRL2 0x0b52 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY16_CTRL3 0x0b53 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY16_CTRL4 0x0b54 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY17_CTRL0 0x0b55 +#define RTL8367C_SVLAN_MCAST2S_ENTRY17_CTRL0_VALID_OFFSET 7 +#define RTL8367C_SVLAN_MCAST2S_ENTRY17_CTRL0_VALID_MASK 0x80 +#define RTL8367C_SVLAN_MCAST2S_ENTRY17_CTRL0_FORMAT_OFFSET 6 +#define RTL8367C_SVLAN_MCAST2S_ENTRY17_CTRL0_FORMAT_MASK 0x40 +#define RTL8367C_SVLAN_MCAST2S_ENTRY17_CTRL0_SVIDX_OFFSET 0 +#define RTL8367C_SVLAN_MCAST2S_ENTRY17_CTRL0_SVIDX_MASK 0x3F + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY17_CTRL1 0x0b56 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY17_CTRL2 0x0b57 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY17_CTRL3 0x0b58 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY17_CTRL4 0x0b59 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY18_CTRL0 0x0b5a +#define RTL8367C_SVLAN_MCAST2S_ENTRY18_CTRL0_VALID_OFFSET 7 +#define RTL8367C_SVLAN_MCAST2S_ENTRY18_CTRL0_VALID_MASK 0x80 +#define RTL8367C_SVLAN_MCAST2S_ENTRY18_CTRL0_FORMAT_OFFSET 6 +#define RTL8367C_SVLAN_MCAST2S_ENTRY18_CTRL0_FORMAT_MASK 0x40 +#define RTL8367C_SVLAN_MCAST2S_ENTRY18_CTRL0_SVIDX_OFFSET 0 +#define RTL8367C_SVLAN_MCAST2S_ENTRY18_CTRL0_SVIDX_MASK 0x3F + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY18_CTRL1 0x0b5b + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY18_CTRL2 0x0b5c + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY18_CTRL3 0x0b5d + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY18_CTRL4 0x0b5e + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY19_CTRL0 0x0b5f +#define RTL8367C_SVLAN_MCAST2S_ENTRY19_CTRL0_VALID_OFFSET 7 +#define RTL8367C_SVLAN_MCAST2S_ENTRY19_CTRL0_VALID_MASK 0x80 +#define RTL8367C_SVLAN_MCAST2S_ENTRY19_CTRL0_FORMAT_OFFSET 6 +#define RTL8367C_SVLAN_MCAST2S_ENTRY19_CTRL0_FORMAT_MASK 0x40 +#define RTL8367C_SVLAN_MCAST2S_ENTRY19_CTRL0_SVIDX_OFFSET 0 +#define RTL8367C_SVLAN_MCAST2S_ENTRY19_CTRL0_SVIDX_MASK 0x3F + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY19_CTRL1 0x0b60 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY19_CTRL2 0x0b61 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY19_CTRL3 0x0b62 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY19_CTRL4 0x0b63 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY20_CTRL0 0x0b64 +#define RTL8367C_SVLAN_MCAST2S_ENTRY20_CTRL0_VALID_OFFSET 7 +#define RTL8367C_SVLAN_MCAST2S_ENTRY20_CTRL0_VALID_MASK 0x80 +#define RTL8367C_SVLAN_MCAST2S_ENTRY20_CTRL0_FORMAT_OFFSET 6 +#define RTL8367C_SVLAN_MCAST2S_ENTRY20_CTRL0_FORMAT_MASK 0x40 +#define RTL8367C_SVLAN_MCAST2S_ENTRY20_CTRL0_SVIDX_OFFSET 0 +#define RTL8367C_SVLAN_MCAST2S_ENTRY20_CTRL0_SVIDX_MASK 0x3F + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY20_CTRL1 0x0b65 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY20_CTRL2 0x0b66 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY20_CTRL3 0x0b67 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY20_CTRL4 0x0b68 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY21_CTRL0 0x0b69 +#define RTL8367C_SVLAN_MCAST2S_ENTRY21_CTRL0_VALID_OFFSET 7 +#define RTL8367C_SVLAN_MCAST2S_ENTRY21_CTRL0_VALID_MASK 0x80 +#define RTL8367C_SVLAN_MCAST2S_ENTRY21_CTRL0_FORMAT_OFFSET 6 +#define RTL8367C_SVLAN_MCAST2S_ENTRY21_CTRL0_FORMAT_MASK 0x40 +#define RTL8367C_SVLAN_MCAST2S_ENTRY21_CTRL0_SVIDX_OFFSET 0 +#define RTL8367C_SVLAN_MCAST2S_ENTRY21_CTRL0_SVIDX_MASK 0x3F + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY21_CTRL1 0x0b6a + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY21_CTRL2 0x0b6b + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY21_CTRL3 0x0b6c + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY21_CTRL4 0x0b6d + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY22_CTRL0 0x0b6e +#define RTL8367C_SVLAN_MCAST2S_ENTRY22_CTRL0_VALID_OFFSET 7 +#define RTL8367C_SVLAN_MCAST2S_ENTRY22_CTRL0_VALID_MASK 0x80 +#define RTL8367C_SVLAN_MCAST2S_ENTRY22_CTRL0_FORMAT_OFFSET 6 +#define RTL8367C_SVLAN_MCAST2S_ENTRY22_CTRL0_FORMAT_MASK 0x40 +#define RTL8367C_SVLAN_MCAST2S_ENTRY22_CTRL0_SVIDX_OFFSET 0 +#define RTL8367C_SVLAN_MCAST2S_ENTRY22_CTRL0_SVIDX_MASK 0x3F + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY22_CTRL1 0x0b6f + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY22_CTRL2 0x0b70 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY22_CTRL3 0x0b71 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY22_CTRL4 0x0b72 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY23_CTRL0 0x0b73 +#define RTL8367C_SVLAN_MCAST2S_ENTRY23_CTRL0_VALID_OFFSET 7 +#define RTL8367C_SVLAN_MCAST2S_ENTRY23_CTRL0_VALID_MASK 0x80 +#define RTL8367C_SVLAN_MCAST2S_ENTRY23_CTRL0_FORMAT_OFFSET 6 +#define RTL8367C_SVLAN_MCAST2S_ENTRY23_CTRL0_FORMAT_MASK 0x40 +#define RTL8367C_SVLAN_MCAST2S_ENTRY23_CTRL0_SVIDX_OFFSET 0 +#define RTL8367C_SVLAN_MCAST2S_ENTRY23_CTRL0_SVIDX_MASK 0x3F + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY23_CTRL1 0x0b74 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY23_CTRL2 0x0b75 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY23_CTRL3 0x0b76 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY23_CTRL4 0x0b77 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY24_CTRL0 0x0b78 +#define RTL8367C_SVLAN_MCAST2S_ENTRY24_CTRL0_VALID_OFFSET 7 +#define RTL8367C_SVLAN_MCAST2S_ENTRY24_CTRL0_VALID_MASK 0x80 +#define RTL8367C_SVLAN_MCAST2S_ENTRY24_CTRL0_FORMAT_OFFSET 6 +#define RTL8367C_SVLAN_MCAST2S_ENTRY24_CTRL0_FORMAT_MASK 0x40 +#define RTL8367C_SVLAN_MCAST2S_ENTRY24_CTRL0_SVIDX_OFFSET 0 +#define RTL8367C_SVLAN_MCAST2S_ENTRY24_CTRL0_SVIDX_MASK 0x3F + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY24_CTRL1 0x0b79 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY24_CTRL2 0x0b7a + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY24_CTRL3 0x0b7b + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY24_CTRL4 0x0b7c + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY25_CTRL0 0x0b7d +#define RTL8367C_SVLAN_MCAST2S_ENTRY25_CTRL0_VALID_OFFSET 7 +#define RTL8367C_SVLAN_MCAST2S_ENTRY25_CTRL0_VALID_MASK 0x80 +#define RTL8367C_SVLAN_MCAST2S_ENTRY25_CTRL0_FORMAT_OFFSET 6 +#define RTL8367C_SVLAN_MCAST2S_ENTRY25_CTRL0_FORMAT_MASK 0x40 +#define RTL8367C_SVLAN_MCAST2S_ENTRY25_CTRL0_SVIDX_OFFSET 0 +#define RTL8367C_SVLAN_MCAST2S_ENTRY25_CTRL0_SVIDX_MASK 0x3F + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY25_CTRL1 0x0b7e + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY25_CTRL2 0x0b7f + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY25_CTRL3 0x0b80 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY25_CTRL4 0x0b81 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY26_CTRL0 0x0b82 +#define RTL8367C_SVLAN_MCAST2S_ENTRY26_CTRL0_VALID_OFFSET 7 +#define RTL8367C_SVLAN_MCAST2S_ENTRY26_CTRL0_VALID_MASK 0x80 +#define RTL8367C_SVLAN_MCAST2S_ENTRY26_CTRL0_FORMAT_OFFSET 6 +#define RTL8367C_SVLAN_MCAST2S_ENTRY26_CTRL0_FORMAT_MASK 0x40 +#define RTL8367C_SVLAN_MCAST2S_ENTRY26_CTRL0_SVIDX_OFFSET 0 +#define RTL8367C_SVLAN_MCAST2S_ENTRY26_CTRL0_SVIDX_MASK 0x3F + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY26_CTRL1 0x0b83 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY26_CTRL2 0x0b84 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY26_CTRL3 0x0b85 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY26_CTRL4 0x0b86 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY27_CTRL0 0x0b87 +#define RTL8367C_SVLAN_MCAST2S_ENTRY27_CTRL0_VALID_OFFSET 7 +#define RTL8367C_SVLAN_MCAST2S_ENTRY27_CTRL0_VALID_MASK 0x80 +#define RTL8367C_SVLAN_MCAST2S_ENTRY27_CTRL0_FORMAT_OFFSET 6 +#define RTL8367C_SVLAN_MCAST2S_ENTRY27_CTRL0_FORMAT_MASK 0x40 +#define RTL8367C_SVLAN_MCAST2S_ENTRY27_CTRL0_SVIDX_OFFSET 0 +#define RTL8367C_SVLAN_MCAST2S_ENTRY27_CTRL0_SVIDX_MASK 0x3F + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY27_CTRL1 0x0b88 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY27_CTRL2 0x0b89 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY27_CTRL3 0x0b8a + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY27_CTRL4 0x0b8b + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY28_CTRL0 0x0b8c +#define RTL8367C_SVLAN_MCAST2S_ENTRY28_CTRL0_VALID_OFFSET 7 +#define RTL8367C_SVLAN_MCAST2S_ENTRY28_CTRL0_VALID_MASK 0x80 +#define RTL8367C_SVLAN_MCAST2S_ENTRY28_CTRL0_FORMAT_OFFSET 6 +#define RTL8367C_SVLAN_MCAST2S_ENTRY28_CTRL0_FORMAT_MASK 0x40 +#define RTL8367C_SVLAN_MCAST2S_ENTRY28_CTRL0_SVIDX_OFFSET 0 +#define RTL8367C_SVLAN_MCAST2S_ENTRY28_CTRL0_SVIDX_MASK 0x3F + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY28_CTRL1 0x0b8d + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY28_CTRL2 0x0b8e + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY28_CTRL3 0x0b8f + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY28_CTRL4 0x0b90 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY29_CTRL0 0x0b91 +#define RTL8367C_SVLAN_MCAST2S_ENTRY29_CTRL0_VALID_OFFSET 7 +#define RTL8367C_SVLAN_MCAST2S_ENTRY29_CTRL0_VALID_MASK 0x80 +#define RTL8367C_SVLAN_MCAST2S_ENTRY29_CTRL0_FORMAT_OFFSET 6 +#define RTL8367C_SVLAN_MCAST2S_ENTRY29_CTRL0_FORMAT_MASK 0x40 +#define RTL8367C_SVLAN_MCAST2S_ENTRY29_CTRL0_SVIDX_OFFSET 0 +#define RTL8367C_SVLAN_MCAST2S_ENTRY29_CTRL0_SVIDX_MASK 0x3F + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY29_CTRL1 0x0b92 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY29_CTRL2 0x0b93 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY29_CTRL3 0x0b94 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY29_CTRL4 0x0b95 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY30_CTRL0 0x0b96 +#define RTL8367C_SVLAN_MCAST2S_ENTRY30_CTRL0_VALID_OFFSET 7 +#define RTL8367C_SVLAN_MCAST2S_ENTRY30_CTRL0_VALID_MASK 0x80 +#define RTL8367C_SVLAN_MCAST2S_ENTRY30_CTRL0_FORMAT_OFFSET 6 +#define RTL8367C_SVLAN_MCAST2S_ENTRY30_CTRL0_FORMAT_MASK 0x40 +#define RTL8367C_SVLAN_MCAST2S_ENTRY30_CTRL0_SVIDX_OFFSET 0 +#define RTL8367C_SVLAN_MCAST2S_ENTRY30_CTRL0_SVIDX_MASK 0x3F + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY30_CTRL1 0x0b97 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY30_CTRL2 0x0b98 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY30_CTRL3 0x0b99 + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY30_CTRL4 0x0b9a + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY31_CTRL0 0x0b9b +#define RTL8367C_SVLAN_MCAST2S_ENTRY31_CTRL0_VALID_OFFSET 7 +#define RTL8367C_SVLAN_MCAST2S_ENTRY31_CTRL0_VALID_MASK 0x80 +#define RTL8367C_SVLAN_MCAST2S_ENTRY31_CTRL0_FORMAT_OFFSET 6 +#define RTL8367C_SVLAN_MCAST2S_ENTRY31_CTRL0_FORMAT_MASK 0x40 +#define RTL8367C_SVLAN_MCAST2S_ENTRY31_CTRL0_SVIDX_OFFSET 0 +#define RTL8367C_SVLAN_MCAST2S_ENTRY31_CTRL0_SVIDX_MASK 0x3F + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY31_CTRL1 0x0b9c + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY31_CTRL2 0x0b9d + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY31_CTRL3 0x0b9e + +#define RTL8367C_REG_SVLAN_MCAST2S_ENTRY31_CTRL4 0x0b9f + +#define RTL8367C_REG_MLTVLAN_DUMMY_0 0x0ba0 + +#define RTL8367C_REG_MLTVLAN_DUMMY_1 0x0ba1 + +#define RTL8367C_REG_MLTVLAN_DUMMY_2 0x0ba2 + +#define RTL8367C_REG_MLTVLAN_DUMMY_3 0x0ba3 + +#define RTL8367C_REG_MLTVLAN_DUMMY_4 0x0ba4 + +#define RTL8367C_REG_MLTVLAN_DUMMY_5 0x0ba5 + +#define RTL8367C_REG_MLTVLAN_DUMMY_6 0x0ba6 + +#define RTL8367C_REG_MLTVLAN_DUMMY_7 0x0ba7 + +/* (16'h0c00)svlan_reg */ + +#define RTL8367C_REG_SVLAN_MEMBERCFG0_CTRL1 0x0c01 +#define RTL8367C_SVLAN_MEMBERCFG0_CTRL1_VS_UNTAGSET_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG0_CTRL1_VS_UNTAGSET_MASK 0xFF00 +#define RTL8367C_SVLAN_MEMBERCFG0_CTRL1_VS_SMBR_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG0_CTRL1_VS_SMBR_MASK 0xFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG0_CTRL2 0x0c02 +#define RTL8367C_SVLAN_MEMBERCFG0_CTRL2_VS_FIDEN_OFFSET 7 +#define RTL8367C_SVLAN_MEMBERCFG0_CTRL2_VS_FIDEN_MASK 0x80 +#define RTL8367C_SVLAN_MEMBERCFG0_CTRL2_VS_SPRI_OFFSET 4 +#define RTL8367C_SVLAN_MEMBERCFG0_CTRL2_VS_SPRI_MASK 0x70 +#define RTL8367C_SVLAN_MEMBERCFG0_CTRL2_VS_FID_MSTI_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG0_CTRL2_VS_FID_MSTI_MASK 0xF + +#define RTL8367C_REG_SVLAN_MEMBERCFG0_CTRL3 0x0c03 +#define RTL8367C_SVLAN_MEMBERCFG0_CTRL3_VS_EFID_OFFSET 13 +#define RTL8367C_SVLAN_MEMBERCFG0_CTRL3_VS_EFID_MASK 0xE000 +#define RTL8367C_SVLAN_MEMBERCFG0_CTRL3_VS_EFIDEN_OFFSET 12 +#define RTL8367C_SVLAN_MEMBERCFG0_CTRL3_VS_EFIDEN_MASK 0x1000 +#define RTL8367C_SVLAN_MEMBERCFG0_CTRL3_VS_SVID_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG0_CTRL3_VS_SVID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG1_CTRL1 0x0c04 +#define RTL8367C_SVLAN_MEMBERCFG1_CTRL1_VS_UNTAGSET_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG1_CTRL1_VS_UNTAGSET_MASK 0xFF00 +#define RTL8367C_SVLAN_MEMBERCFG1_CTRL1_VS_SMBR_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG1_CTRL1_VS_SMBR_MASK 0xFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG1_CTRL2 0x0c05 +#define RTL8367C_SVLAN_MEMBERCFG1_CTRL2_VS_FIDEN_OFFSET 7 +#define RTL8367C_SVLAN_MEMBERCFG1_CTRL2_VS_FIDEN_MASK 0x80 +#define RTL8367C_SVLAN_MEMBERCFG1_CTRL2_VS_SPRI_OFFSET 4 +#define RTL8367C_SVLAN_MEMBERCFG1_CTRL2_VS_SPRI_MASK 0x70 +#define RTL8367C_SVLAN_MEMBERCFG1_CTRL2_VS_FID_MSTI_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG1_CTRL2_VS_FID_MSTI_MASK 0xF + +#define RTL8367C_REG_SVLAN_MEMBERCFG1_CTRL3 0x0c06 +#define RTL8367C_SVLAN_MEMBERCFG1_CTRL3_VS_EFID_OFFSET 13 +#define RTL8367C_SVLAN_MEMBERCFG1_CTRL3_VS_EFID_MASK 0xE000 +#define RTL8367C_SVLAN_MEMBERCFG1_CTRL3_VS_EFIDEN_OFFSET 12 +#define RTL8367C_SVLAN_MEMBERCFG1_CTRL3_VS_EFIDEN_MASK 0x1000 +#define RTL8367C_SVLAN_MEMBERCFG1_CTRL3_VS_SVID_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG1_CTRL3_VS_SVID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG2_CTRL1 0x0c07 +#define RTL8367C_SVLAN_MEMBERCFG2_CTRL1_VS_UNTAGSET_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG2_CTRL1_VS_UNTAGSET_MASK 0xFF00 +#define RTL8367C_SVLAN_MEMBERCFG2_CTRL1_VS_SMBR_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG2_CTRL1_VS_SMBR_MASK 0xFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG2_CTRL2 0x0c08 +#define RTL8367C_SVLAN_MEMBERCFG2_CTRL2_VS_FIDEN_OFFSET 7 +#define RTL8367C_SVLAN_MEMBERCFG2_CTRL2_VS_FIDEN_MASK 0x80 +#define RTL8367C_SVLAN_MEMBERCFG2_CTRL2_VS_SPRI_OFFSET 4 +#define RTL8367C_SVLAN_MEMBERCFG2_CTRL2_VS_SPRI_MASK 0x70 +#define RTL8367C_SVLAN_MEMBERCFG2_CTRL2_VS_FID_MSTI_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG2_CTRL2_VS_FID_MSTI_MASK 0xF + +#define RTL8367C_REG_SVLAN_MEMBERCFG2_CTRL3 0x0c09 +#define RTL8367C_SVLAN_MEMBERCFG2_CTRL3_VS_EFID_OFFSET 13 +#define RTL8367C_SVLAN_MEMBERCFG2_CTRL3_VS_EFID_MASK 0xE000 +#define RTL8367C_SVLAN_MEMBERCFG2_CTRL3_VS_EFIDEN_OFFSET 12 +#define RTL8367C_SVLAN_MEMBERCFG2_CTRL3_VS_EFIDEN_MASK 0x1000 +#define RTL8367C_SVLAN_MEMBERCFG2_CTRL3_VS_SVID_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG2_CTRL3_VS_SVID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG3_CTRL1 0x0c0a +#define RTL8367C_SVLAN_MEMBERCFG3_CTRL1_VS_UNTAGSET_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG3_CTRL1_VS_UNTAGSET_MASK 0xFF00 +#define RTL8367C_SVLAN_MEMBERCFG3_CTRL1_VS_SMBR_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG3_CTRL1_VS_SMBR_MASK 0xFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG3_CTRL2 0x0c0b +#define RTL8367C_SVLAN_MEMBERCFG3_CTRL2_VS_FIDEN_OFFSET 7 +#define RTL8367C_SVLAN_MEMBERCFG3_CTRL2_VS_FIDEN_MASK 0x80 +#define RTL8367C_SVLAN_MEMBERCFG3_CTRL2_VS_SPRI_OFFSET 4 +#define RTL8367C_SVLAN_MEMBERCFG3_CTRL2_VS_SPRI_MASK 0x70 +#define RTL8367C_SVLAN_MEMBERCFG3_CTRL2_VS_FID_MSTI_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG3_CTRL2_VS_FID_MSTI_MASK 0xF + +#define RTL8367C_REG_SVLAN_MEMBERCFG3_CTRL3 0x0c0c +#define RTL8367C_SVLAN_MEMBERCFG3_CTRL3_VS_EFID_OFFSET 13 +#define RTL8367C_SVLAN_MEMBERCFG3_CTRL3_VS_EFID_MASK 0xE000 +#define RTL8367C_SVLAN_MEMBERCFG3_CTRL3_VS_EFIDEN_OFFSET 12 +#define RTL8367C_SVLAN_MEMBERCFG3_CTRL3_VS_EFIDEN_MASK 0x1000 +#define RTL8367C_SVLAN_MEMBERCFG3_CTRL3_VS_SVID_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG3_CTRL3_VS_SVID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG4_CTRL1 0x0c0d +#define RTL8367C_SVLAN_MEMBERCFG4_CTRL1_VS_UNTAGSET_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG4_CTRL1_VS_UNTAGSET_MASK 0xFF00 +#define RTL8367C_SVLAN_MEMBERCFG4_CTRL1_VS_SMBR_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG4_CTRL1_VS_SMBR_MASK 0xFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG4_CTRL2 0x0c0e +#define RTL8367C_SVLAN_MEMBERCFG4_CTRL2_VS_FIDEN_OFFSET 7 +#define RTL8367C_SVLAN_MEMBERCFG4_CTRL2_VS_FIDEN_MASK 0x80 +#define RTL8367C_SVLAN_MEMBERCFG4_CTRL2_VS_SPRI_OFFSET 4 +#define RTL8367C_SVLAN_MEMBERCFG4_CTRL2_VS_SPRI_MASK 0x70 +#define RTL8367C_SVLAN_MEMBERCFG4_CTRL2_VS_FID_MSTI_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG4_CTRL2_VS_FID_MSTI_MASK 0xF + +#define RTL8367C_REG_SVLAN_MEMBERCFG4_CTRL3 0x0c0f +#define RTL8367C_SVLAN_MEMBERCFG4_CTRL3_VS_EFID_OFFSET 13 +#define RTL8367C_SVLAN_MEMBERCFG4_CTRL3_VS_EFID_MASK 0xE000 +#define RTL8367C_SVLAN_MEMBERCFG4_CTRL3_VS_EFIDEN_OFFSET 12 +#define RTL8367C_SVLAN_MEMBERCFG4_CTRL3_VS_EFIDEN_MASK 0x1000 +#define RTL8367C_SVLAN_MEMBERCFG4_CTRL3_VS_SVID_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG4_CTRL3_VS_SVID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG5_CTRL1 0x0c10 +#define RTL8367C_SVLAN_MEMBERCFG5_CTRL1_VS_UNTAGSET_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG5_CTRL1_VS_UNTAGSET_MASK 0xFF00 +#define RTL8367C_SVLAN_MEMBERCFG5_CTRL1_VS_SMBR_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG5_CTRL1_VS_SMBR_MASK 0xFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG5_CTRL2 0x0c11 +#define RTL8367C_SVLAN_MEMBERCFG5_CTRL2_VS_FIDEN_OFFSET 7 +#define RTL8367C_SVLAN_MEMBERCFG5_CTRL2_VS_FIDEN_MASK 0x80 +#define RTL8367C_SVLAN_MEMBERCFG5_CTRL2_VS_SPRI_OFFSET 4 +#define RTL8367C_SVLAN_MEMBERCFG5_CTRL2_VS_SPRI_MASK 0x70 +#define RTL8367C_SVLAN_MEMBERCFG5_CTRL2_VS_FID_MSTI_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG5_CTRL2_VS_FID_MSTI_MASK 0xF + +#define RTL8367C_REG_SVLAN_MEMBERCFG5_CTRL3 0x0c12 +#define RTL8367C_SVLAN_MEMBERCFG5_CTRL3_VS_EFID_OFFSET 13 +#define RTL8367C_SVLAN_MEMBERCFG5_CTRL3_VS_EFID_MASK 0xE000 +#define RTL8367C_SVLAN_MEMBERCFG5_CTRL3_VS_EFIDEN_OFFSET 12 +#define RTL8367C_SVLAN_MEMBERCFG5_CTRL3_VS_EFIDEN_MASK 0x1000 +#define RTL8367C_SVLAN_MEMBERCFG5_CTRL3_VS_SVID_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG5_CTRL3_VS_SVID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG6_CTRL1 0x0c13 +#define RTL8367C_SVLAN_MEMBERCFG6_CTRL1_VS_UNTAGSET_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG6_CTRL1_VS_UNTAGSET_MASK 0xFF00 +#define RTL8367C_SVLAN_MEMBERCFG6_CTRL1_VS_SMBR_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG6_CTRL1_VS_SMBR_MASK 0xFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG6_CTRL2 0x0c14 +#define RTL8367C_SVLAN_MEMBERCFG6_CTRL2_VS_FIDEN_OFFSET 7 +#define RTL8367C_SVLAN_MEMBERCFG6_CTRL2_VS_FIDEN_MASK 0x80 +#define RTL8367C_SVLAN_MEMBERCFG6_CTRL2_VS_SPRI_OFFSET 4 +#define RTL8367C_SVLAN_MEMBERCFG6_CTRL2_VS_SPRI_MASK 0x70 +#define RTL8367C_SVLAN_MEMBERCFG6_CTRL2_VS_FID_MSTI_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG6_CTRL2_VS_FID_MSTI_MASK 0xF + +#define RTL8367C_REG_SVLAN_MEMBERCFG6_CTRL3 0x0c15 +#define RTL8367C_SVLAN_MEMBERCFG6_CTRL3_VS_EFID_OFFSET 13 +#define RTL8367C_SVLAN_MEMBERCFG6_CTRL3_VS_EFID_MASK 0xE000 +#define RTL8367C_SVLAN_MEMBERCFG6_CTRL3_VS_EFIDEN_OFFSET 12 +#define RTL8367C_SVLAN_MEMBERCFG6_CTRL3_VS_EFIDEN_MASK 0x1000 +#define RTL8367C_SVLAN_MEMBERCFG6_CTRL3_VS_SVID_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG6_CTRL3_VS_SVID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG7_CTRL1 0x0c16 +#define RTL8367C_SVLAN_MEMBERCFG7_CTRL1_VS_UNTAGSET_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG7_CTRL1_VS_UNTAGSET_MASK 0xFF00 +#define RTL8367C_SVLAN_MEMBERCFG7_CTRL1_VS_SMBR_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG7_CTRL1_VS_SMBR_MASK 0xFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG7_CTRL2 0x0c17 +#define RTL8367C_SVLAN_MEMBERCFG7_CTRL2_VS_FIDEN_OFFSET 7 +#define RTL8367C_SVLAN_MEMBERCFG7_CTRL2_VS_FIDEN_MASK 0x80 +#define RTL8367C_SVLAN_MEMBERCFG7_CTRL2_VS_SPRI_OFFSET 4 +#define RTL8367C_SVLAN_MEMBERCFG7_CTRL2_VS_SPRI_MASK 0x70 +#define RTL8367C_SVLAN_MEMBERCFG7_CTRL2_VS_FID_MSTI_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG7_CTRL2_VS_FID_MSTI_MASK 0xF + +#define RTL8367C_REG_SVLAN_MEMBERCFG7_CTRL3 0x0c18 +#define RTL8367C_SVLAN_MEMBERCFG7_CTRL3_VS_EFID_OFFSET 13 +#define RTL8367C_SVLAN_MEMBERCFG7_CTRL3_VS_EFID_MASK 0xE000 +#define RTL8367C_SVLAN_MEMBERCFG7_CTRL3_VS_EFIDEN_OFFSET 12 +#define RTL8367C_SVLAN_MEMBERCFG7_CTRL3_VS_EFIDEN_MASK 0x1000 +#define RTL8367C_SVLAN_MEMBERCFG7_CTRL3_VS_SVID_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG7_CTRL3_VS_SVID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG8_CTRL1 0x0c19 +#define RTL8367C_SVLAN_MEMBERCFG8_CTRL1_VS_UNTAGSET_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG8_CTRL1_VS_UNTAGSET_MASK 0xFF00 +#define RTL8367C_SVLAN_MEMBERCFG8_CTRL1_VS_SMBR_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG8_CTRL1_VS_SMBR_MASK 0xFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG8_CTRL2 0x0c1a +#define RTL8367C_SVLAN_MEMBERCFG8_CTRL2_VS_FIDEN_OFFSET 7 +#define RTL8367C_SVLAN_MEMBERCFG8_CTRL2_VS_FIDEN_MASK 0x80 +#define RTL8367C_SVLAN_MEMBERCFG8_CTRL2_VS_SPRI_OFFSET 4 +#define RTL8367C_SVLAN_MEMBERCFG8_CTRL2_VS_SPRI_MASK 0x70 +#define RTL8367C_SVLAN_MEMBERCFG8_CTRL2_VS_FID_MSTI_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG8_CTRL2_VS_FID_MSTI_MASK 0xF + +#define RTL8367C_REG_SVLAN_MEMBERCFG8_CTRL3 0x0c1b +#define RTL8367C_SVLAN_MEMBERCFG8_CTRL3_VS_EFID_OFFSET 13 +#define RTL8367C_SVLAN_MEMBERCFG8_CTRL3_VS_EFID_MASK 0xE000 +#define RTL8367C_SVLAN_MEMBERCFG8_CTRL3_VS_EFIDEN_OFFSET 12 +#define RTL8367C_SVLAN_MEMBERCFG8_CTRL3_VS_EFIDEN_MASK 0x1000 +#define RTL8367C_SVLAN_MEMBERCFG8_CTRL3_VS_SVID_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG8_CTRL3_VS_SVID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG9_CTRL1 0x0c1c +#define RTL8367C_SVLAN_MEMBERCFG9_CTRL1_VS_UNTAGSET_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG9_CTRL1_VS_UNTAGSET_MASK 0xFF00 +#define RTL8367C_SVLAN_MEMBERCFG9_CTRL1_VS_SMBR_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG9_CTRL1_VS_SMBR_MASK 0xFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG9_CTRL2 0x0c1d +#define RTL8367C_SVLAN_MEMBERCFG9_CTRL2_VS_FIDEN_OFFSET 7 +#define RTL8367C_SVLAN_MEMBERCFG9_CTRL2_VS_FIDEN_MASK 0x80 +#define RTL8367C_SVLAN_MEMBERCFG9_CTRL2_VS_SPRI_OFFSET 4 +#define RTL8367C_SVLAN_MEMBERCFG9_CTRL2_VS_SPRI_MASK 0x70 +#define RTL8367C_SVLAN_MEMBERCFG9_CTRL2_VS_FID_MSTI_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG9_CTRL2_VS_FID_MSTI_MASK 0xF + +#define RTL8367C_REG_SVLAN_MEMBERCFG9_CTRL3 0x0c1e +#define RTL8367C_SVLAN_MEMBERCFG9_CTRL3_VS_EFID_OFFSET 13 +#define RTL8367C_SVLAN_MEMBERCFG9_CTRL3_VS_EFID_MASK 0xE000 +#define RTL8367C_SVLAN_MEMBERCFG9_CTRL3_VS_EFIDEN_OFFSET 12 +#define RTL8367C_SVLAN_MEMBERCFG9_CTRL3_VS_EFIDEN_MASK 0x1000 +#define RTL8367C_SVLAN_MEMBERCFG9_CTRL3_VS_SVID_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG9_CTRL3_VS_SVID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG10_CTRL1 0x0c1f +#define RTL8367C_SVLAN_MEMBERCFG10_CTRL1_VS_UNTAGSET_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG10_CTRL1_VS_UNTAGSET_MASK 0xFF00 +#define RTL8367C_SVLAN_MEMBERCFG10_CTRL1_VS_SMBR_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG10_CTRL1_VS_SMBR_MASK 0xFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG10_CTRL2 0x0c20 +#define RTL8367C_SVLAN_MEMBERCFG10_CTRL2_VS_FIDEN_OFFSET 7 +#define RTL8367C_SVLAN_MEMBERCFG10_CTRL2_VS_FIDEN_MASK 0x80 +#define RTL8367C_SVLAN_MEMBERCFG10_CTRL2_VS_SPRI_OFFSET 4 +#define RTL8367C_SVLAN_MEMBERCFG10_CTRL2_VS_SPRI_MASK 0x70 +#define RTL8367C_SVLAN_MEMBERCFG10_CTRL2_VS_FID_MSTI_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG10_CTRL2_VS_FID_MSTI_MASK 0xF + +#define RTL8367C_REG_SVLAN_MEMBERCFG10_CTRL3 0x0c21 +#define RTL8367C_SVLAN_MEMBERCFG10_CTRL3_VS_EFID_OFFSET 13 +#define RTL8367C_SVLAN_MEMBERCFG10_CTRL3_VS_EFID_MASK 0xE000 +#define RTL8367C_SVLAN_MEMBERCFG10_CTRL3_VS_EFIDEN_OFFSET 12 +#define RTL8367C_SVLAN_MEMBERCFG10_CTRL3_VS_EFIDEN_MASK 0x1000 +#define RTL8367C_SVLAN_MEMBERCFG10_CTRL3_VS_SVID_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG10_CTRL3_VS_SVID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG11_CTRL1 0x0c22 +#define RTL8367C_SVLAN_MEMBERCFG11_CTRL1_VS_UNTAGSET_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG11_CTRL1_VS_UNTAGSET_MASK 0xFF00 +#define RTL8367C_SVLAN_MEMBERCFG11_CTRL1_VS_SMBR_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG11_CTRL1_VS_SMBR_MASK 0xFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG11_CTRL2 0x0c23 +#define RTL8367C_SVLAN_MEMBERCFG11_CTRL2_VS_FIDEN_OFFSET 7 +#define RTL8367C_SVLAN_MEMBERCFG11_CTRL2_VS_FIDEN_MASK 0x80 +#define RTL8367C_SVLAN_MEMBERCFG11_CTRL2_VS_SPRI_OFFSET 4 +#define RTL8367C_SVLAN_MEMBERCFG11_CTRL2_VS_SPRI_MASK 0x70 +#define RTL8367C_SVLAN_MEMBERCFG11_CTRL2_VS_FID_MSTI_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG11_CTRL2_VS_FID_MSTI_MASK 0xF + +#define RTL8367C_REG_SVLAN_MEMBERCFG11_CTRL3 0x0c24 +#define RTL8367C_SVLAN_MEMBERCFG11_CTRL3_VS_EFID_OFFSET 13 +#define RTL8367C_SVLAN_MEMBERCFG11_CTRL3_VS_EFID_MASK 0xE000 +#define RTL8367C_SVLAN_MEMBERCFG11_CTRL3_VS_EFIDEN_OFFSET 12 +#define RTL8367C_SVLAN_MEMBERCFG11_CTRL3_VS_EFIDEN_MASK 0x1000 +#define RTL8367C_SVLAN_MEMBERCFG11_CTRL3_VS_SVID_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG11_CTRL3_VS_SVID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG12_CTRL1 0x0c25 +#define RTL8367C_SVLAN_MEMBERCFG12_CTRL1_VS_UNTAGSET_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG12_CTRL1_VS_UNTAGSET_MASK 0xFF00 +#define RTL8367C_SVLAN_MEMBERCFG12_CTRL1_VS_SMBR_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG12_CTRL1_VS_SMBR_MASK 0xFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG12_CTRL2 0x0c26 +#define RTL8367C_SVLAN_MEMBERCFG12_CTRL2_VS_FIDEN_OFFSET 7 +#define RTL8367C_SVLAN_MEMBERCFG12_CTRL2_VS_FIDEN_MASK 0x80 +#define RTL8367C_SVLAN_MEMBERCFG12_CTRL2_VS_SPRI_OFFSET 4 +#define RTL8367C_SVLAN_MEMBERCFG12_CTRL2_VS_SPRI_MASK 0x70 +#define RTL8367C_SVLAN_MEMBERCFG12_CTRL2_VS_FID_MSTI_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG12_CTRL2_VS_FID_MSTI_MASK 0xF + +#define RTL8367C_REG_SVLAN_MEMBERCFG12_CTRL3 0x0c27 +#define RTL8367C_SVLAN_MEMBERCFG12_CTRL3_VS_EFID_OFFSET 13 +#define RTL8367C_SVLAN_MEMBERCFG12_CTRL3_VS_EFID_MASK 0xE000 +#define RTL8367C_SVLAN_MEMBERCFG12_CTRL3_VS_EFIDEN_OFFSET 12 +#define RTL8367C_SVLAN_MEMBERCFG12_CTRL3_VS_EFIDEN_MASK 0x1000 +#define RTL8367C_SVLAN_MEMBERCFG12_CTRL3_VS_SVID_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG12_CTRL3_VS_SVID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG13_CTRL1 0x0c28 +#define RTL8367C_SVLAN_MEMBERCFG13_CTRL1_VS_UNTAGSET_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG13_CTRL1_VS_UNTAGSET_MASK 0xFF00 +#define RTL8367C_SVLAN_MEMBERCFG13_CTRL1_VS_SMBR_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG13_CTRL1_VS_SMBR_MASK 0xFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG13_CTRL2 0x0c29 +#define RTL8367C_SVLAN_MEMBERCFG13_CTRL2_VS_FIDEN_OFFSET 7 +#define RTL8367C_SVLAN_MEMBERCFG13_CTRL2_VS_FIDEN_MASK 0x80 +#define RTL8367C_SVLAN_MEMBERCFG13_CTRL2_VS_SPRI_OFFSET 4 +#define RTL8367C_SVLAN_MEMBERCFG13_CTRL2_VS_SPRI_MASK 0x70 +#define RTL8367C_SVLAN_MEMBERCFG13_CTRL2_VS_FID_MSTI_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG13_CTRL2_VS_FID_MSTI_MASK 0xF + +#define RTL8367C_REG_SVLAN_MEMBERCFG13_CTRL3 0x0c2a +#define RTL8367C_SVLAN_MEMBERCFG13_CTRL3_VS_EFID_OFFSET 13 +#define RTL8367C_SVLAN_MEMBERCFG13_CTRL3_VS_EFID_MASK 0xE000 +#define RTL8367C_SVLAN_MEMBERCFG13_CTRL3_VS_EFIDEN_OFFSET 12 +#define RTL8367C_SVLAN_MEMBERCFG13_CTRL3_VS_EFIDEN_MASK 0x1000 +#define RTL8367C_SVLAN_MEMBERCFG13_CTRL3_VS_SVID_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG13_CTRL3_VS_SVID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG14_CTRL1 0x0c2b +#define RTL8367C_SVLAN_MEMBERCFG14_CTRL1_VS_UNTAGSET_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG14_CTRL1_VS_UNTAGSET_MASK 0xFF00 +#define RTL8367C_SVLAN_MEMBERCFG14_CTRL1_VS_SMBR_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG14_CTRL1_VS_SMBR_MASK 0xFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG14_CTRL2 0x0c2c +#define RTL8367C_SVLAN_MEMBERCFG14_CTRL2_VS_FIDEN_OFFSET 7 +#define RTL8367C_SVLAN_MEMBERCFG14_CTRL2_VS_FIDEN_MASK 0x80 +#define RTL8367C_SVLAN_MEMBERCFG14_CTRL2_VS_SPRI_OFFSET 4 +#define RTL8367C_SVLAN_MEMBERCFG14_CTRL2_VS_SPRI_MASK 0x70 +#define RTL8367C_SVLAN_MEMBERCFG14_CTRL2_VS_FID_MSTI_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG14_CTRL2_VS_FID_MSTI_MASK 0xF + +#define RTL8367C_REG_SVLAN_MEMBERCFG14_CTRL3 0x0c2d +#define RTL8367C_SVLAN_MEMBERCFG14_CTRL3_VS_EFID_OFFSET 13 +#define RTL8367C_SVLAN_MEMBERCFG14_CTRL3_VS_EFID_MASK 0xE000 +#define RTL8367C_SVLAN_MEMBERCFG14_CTRL3_VS_EFIDEN_OFFSET 12 +#define RTL8367C_SVLAN_MEMBERCFG14_CTRL3_VS_EFIDEN_MASK 0x1000 +#define RTL8367C_SVLAN_MEMBERCFG14_CTRL3_VS_SVID_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG14_CTRL3_VS_SVID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG15_CTRL1 0x0c2e +#define RTL8367C_SVLAN_MEMBERCFG15_CTRL1_VS_UNTAGSET_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG15_CTRL1_VS_UNTAGSET_MASK 0xFF00 +#define RTL8367C_SVLAN_MEMBERCFG15_CTRL1_VS_SMBR_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG15_CTRL1_VS_SMBR_MASK 0xFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG15_CTRL2 0x0c2f +#define RTL8367C_SVLAN_MEMBERCFG15_CTRL2_VS_FIDEN_OFFSET 7 +#define RTL8367C_SVLAN_MEMBERCFG15_CTRL2_VS_FIDEN_MASK 0x80 +#define RTL8367C_SVLAN_MEMBERCFG15_CTRL2_VS_SPRI_OFFSET 4 +#define RTL8367C_SVLAN_MEMBERCFG15_CTRL2_VS_SPRI_MASK 0x70 +#define RTL8367C_SVLAN_MEMBERCFG15_CTRL2_VS_FID_MSTI_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG15_CTRL2_VS_FID_MSTI_MASK 0xF + +#define RTL8367C_REG_SVLAN_MEMBERCFG15_CTRL3 0x0c30 +#define RTL8367C_SVLAN_MEMBERCFG15_CTRL3_VS_EFID_OFFSET 13 +#define RTL8367C_SVLAN_MEMBERCFG15_CTRL3_VS_EFID_MASK 0xE000 +#define RTL8367C_SVLAN_MEMBERCFG15_CTRL3_VS_EFIDEN_OFFSET 12 +#define RTL8367C_SVLAN_MEMBERCFG15_CTRL3_VS_EFIDEN_MASK 0x1000 +#define RTL8367C_SVLAN_MEMBERCFG15_CTRL3_VS_SVID_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG15_CTRL3_VS_SVID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG16_CTRL1 0x0c31 +#define RTL8367C_SVLAN_MEMBERCFG16_CTRL1_VS_UNTAGSET_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG16_CTRL1_VS_UNTAGSET_MASK 0xFF00 +#define RTL8367C_SVLAN_MEMBERCFG16_CTRL1_VS_SMBR_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG16_CTRL1_VS_SMBR_MASK 0xFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG16_CTRL2 0x0c32 +#define RTL8367C_SVLAN_MEMBERCFG16_CTRL2_VS_FIDEN_OFFSET 7 +#define RTL8367C_SVLAN_MEMBERCFG16_CTRL2_VS_FIDEN_MASK 0x80 +#define RTL8367C_SVLAN_MEMBERCFG16_CTRL2_VS_SPRI_OFFSET 4 +#define RTL8367C_SVLAN_MEMBERCFG16_CTRL2_VS_SPRI_MASK 0x70 +#define RTL8367C_SVLAN_MEMBERCFG16_CTRL2_VS_FID_MSTI_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG16_CTRL2_VS_FID_MSTI_MASK 0xF + +#define RTL8367C_REG_SVLAN_MEMBERCFG16_CTRL3 0x0c33 +#define RTL8367C_SVLAN_MEMBERCFG16_CTRL3_VS_EFID_OFFSET 13 +#define RTL8367C_SVLAN_MEMBERCFG16_CTRL3_VS_EFID_MASK 0xE000 +#define RTL8367C_SVLAN_MEMBERCFG16_CTRL3_VS_EFIDEN_OFFSET 12 +#define RTL8367C_SVLAN_MEMBERCFG16_CTRL3_VS_EFIDEN_MASK 0x1000 +#define RTL8367C_SVLAN_MEMBERCFG16_CTRL3_VS_SVID_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG16_CTRL3_VS_SVID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG17_CTRL1 0x0c34 +#define RTL8367C_SVLAN_MEMBERCFG17_CTRL1_VS_UNTAGSET_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG17_CTRL1_VS_UNTAGSET_MASK 0xFF00 +#define RTL8367C_SVLAN_MEMBERCFG17_CTRL1_VS_SMBR_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG17_CTRL1_VS_SMBR_MASK 0xFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG17_CTRL2 0x0c35 +#define RTL8367C_SVLAN_MEMBERCFG17_CTRL2_VS_FIDEN_OFFSET 7 +#define RTL8367C_SVLAN_MEMBERCFG17_CTRL2_VS_FIDEN_MASK 0x80 +#define RTL8367C_SVLAN_MEMBERCFG17_CTRL2_VS_SPRI_OFFSET 4 +#define RTL8367C_SVLAN_MEMBERCFG17_CTRL2_VS_SPRI_MASK 0x70 +#define RTL8367C_SVLAN_MEMBERCFG17_CTRL2_VS_FID_MSTI_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG17_CTRL2_VS_FID_MSTI_MASK 0xF + +#define RTL8367C_REG_SVLAN_MEMBERCFG17_CTRL3 0x0c36 +#define RTL8367C_SVLAN_MEMBERCFG17_CTRL3_VS_EFID_OFFSET 13 +#define RTL8367C_SVLAN_MEMBERCFG17_CTRL3_VS_EFID_MASK 0xE000 +#define RTL8367C_SVLAN_MEMBERCFG17_CTRL3_VS_EFIDEN_OFFSET 12 +#define RTL8367C_SVLAN_MEMBERCFG17_CTRL3_VS_EFIDEN_MASK 0x1000 +#define RTL8367C_SVLAN_MEMBERCFG17_CTRL3_VS_SVID_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG17_CTRL3_VS_SVID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG18_CTRL1 0x0c37 +#define RTL8367C_SVLAN_MEMBERCFG18_CTRL1_VS_UNTAGSET_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG18_CTRL1_VS_UNTAGSET_MASK 0xFF00 +#define RTL8367C_SVLAN_MEMBERCFG18_CTRL1_VS_SMBR_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG18_CTRL1_VS_SMBR_MASK 0xFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG18_CTRL2 0x0c38 +#define RTL8367C_SVLAN_MEMBERCFG18_CTRL2_VS_FIDEN_OFFSET 7 +#define RTL8367C_SVLAN_MEMBERCFG18_CTRL2_VS_FIDEN_MASK 0x80 +#define RTL8367C_SVLAN_MEMBERCFG18_CTRL2_VS_SPRI_OFFSET 4 +#define RTL8367C_SVLAN_MEMBERCFG18_CTRL2_VS_SPRI_MASK 0x70 +#define RTL8367C_SVLAN_MEMBERCFG18_CTRL2_VS_FID_MSTI_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG18_CTRL2_VS_FID_MSTI_MASK 0xF + +#define RTL8367C_REG_SVLAN_MEMBERCFG18_CTRL3 0x0c39 +#define RTL8367C_SVLAN_MEMBERCFG18_CTRL3_VS_EFID_OFFSET 13 +#define RTL8367C_SVLAN_MEMBERCFG18_CTRL3_VS_EFID_MASK 0xE000 +#define RTL8367C_SVLAN_MEMBERCFG18_CTRL3_VS_EFIDEN_OFFSET 12 +#define RTL8367C_SVLAN_MEMBERCFG18_CTRL3_VS_EFIDEN_MASK 0x1000 +#define RTL8367C_SVLAN_MEMBERCFG18_CTRL3_VS_SVID_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG18_CTRL3_VS_SVID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG19_CTRL1 0x0c3a +#define RTL8367C_SVLAN_MEMBERCFG19_CTRL1_VS_UNTAGSET_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG19_CTRL1_VS_UNTAGSET_MASK 0xFF00 +#define RTL8367C_SVLAN_MEMBERCFG19_CTRL1_VS_SMBR_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG19_CTRL1_VS_SMBR_MASK 0xFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG19_CTRL2 0x0c3b +#define RTL8367C_SVLAN_MEMBERCFG19_CTRL2_VS_FIDEN_OFFSET 7 +#define RTL8367C_SVLAN_MEMBERCFG19_CTRL2_VS_FIDEN_MASK 0x80 +#define RTL8367C_SVLAN_MEMBERCFG19_CTRL2_VS_SPRI_OFFSET 4 +#define RTL8367C_SVLAN_MEMBERCFG19_CTRL2_VS_SPRI_MASK 0x70 +#define RTL8367C_SVLAN_MEMBERCFG19_CTRL2_VS_FID_MSTI_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG19_CTRL2_VS_FID_MSTI_MASK 0xF + +#define RTL8367C_REG_SVLAN_MEMBERCFG19_CTRL3 0x0c3c +#define RTL8367C_SVLAN_MEMBERCFG19_CTRL3_VS_EFID_OFFSET 13 +#define RTL8367C_SVLAN_MEMBERCFG19_CTRL3_VS_EFID_MASK 0xE000 +#define RTL8367C_SVLAN_MEMBERCFG19_CTRL3_VS_EFIDEN_OFFSET 12 +#define RTL8367C_SVLAN_MEMBERCFG19_CTRL3_VS_EFIDEN_MASK 0x1000 +#define RTL8367C_SVLAN_MEMBERCFG19_CTRL3_VS_SVID_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG19_CTRL3_VS_SVID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG20_CTRL1 0x0c3d +#define RTL8367C_SVLAN_MEMBERCFG20_CTRL1_VS_UNTAGSET_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG20_CTRL1_VS_UNTAGSET_MASK 0xFF00 +#define RTL8367C_SVLAN_MEMBERCFG20_CTRL1_VS_SMBR_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG20_CTRL1_VS_SMBR_MASK 0xFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG20_CTRL2 0x0c3e +#define RTL8367C_SVLAN_MEMBERCFG20_CTRL2_VS_FIDEN_OFFSET 7 +#define RTL8367C_SVLAN_MEMBERCFG20_CTRL2_VS_FIDEN_MASK 0x80 +#define RTL8367C_SVLAN_MEMBERCFG20_CTRL2_VS_SPRI_OFFSET 4 +#define RTL8367C_SVLAN_MEMBERCFG20_CTRL2_VS_SPRI_MASK 0x70 +#define RTL8367C_SVLAN_MEMBERCFG20_CTRL2_VS_FID_MSTI_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG20_CTRL2_VS_FID_MSTI_MASK 0xF + +#define RTL8367C_REG_SVLAN_MEMBERCFG20_CTRL3 0x0c3f +#define RTL8367C_SVLAN_MEMBERCFG20_CTRL3_VS_EFID_OFFSET 13 +#define RTL8367C_SVLAN_MEMBERCFG20_CTRL3_VS_EFID_MASK 0xE000 +#define RTL8367C_SVLAN_MEMBERCFG20_CTRL3_VS_EFIDEN_OFFSET 12 +#define RTL8367C_SVLAN_MEMBERCFG20_CTRL3_VS_EFIDEN_MASK 0x1000 +#define RTL8367C_SVLAN_MEMBERCFG20_CTRL3_VS_SVID_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG20_CTRL3_VS_SVID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG21_CTRL1 0x0c40 +#define RTL8367C_SVLAN_MEMBERCFG21_CTRL1_VS_UNTAGSET_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG21_CTRL1_VS_UNTAGSET_MASK 0xFF00 +#define RTL8367C_SVLAN_MEMBERCFG21_CTRL1_VS_SMBR_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG21_CTRL1_VS_SMBR_MASK 0xFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG21_CTRL2 0x0c41 +#define RTL8367C_SVLAN_MEMBERCFG21_CTRL2_VS_FIDEN_OFFSET 7 +#define RTL8367C_SVLAN_MEMBERCFG21_CTRL2_VS_FIDEN_MASK 0x80 +#define RTL8367C_SVLAN_MEMBERCFG21_CTRL2_VS_SPRI_OFFSET 4 +#define RTL8367C_SVLAN_MEMBERCFG21_CTRL2_VS_SPRI_MASK 0x70 +#define RTL8367C_SVLAN_MEMBERCFG21_CTRL2_VS_FID_MSTI_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG21_CTRL2_VS_FID_MSTI_MASK 0xF + +#define RTL8367C_REG_SVLAN_MEMBERCFG21_CTRL3 0x0c42 +#define RTL8367C_SVLAN_MEMBERCFG21_CTRL3_VS_EFID_OFFSET 13 +#define RTL8367C_SVLAN_MEMBERCFG21_CTRL3_VS_EFID_MASK 0xE000 +#define RTL8367C_SVLAN_MEMBERCFG21_CTRL3_VS_EFIDEN_OFFSET 12 +#define RTL8367C_SVLAN_MEMBERCFG21_CTRL3_VS_EFIDEN_MASK 0x1000 +#define RTL8367C_SVLAN_MEMBERCFG21_CTRL3_VS_SVID_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG21_CTRL3_VS_SVID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG22_CTRL1 0x0c43 +#define RTL8367C_SVLAN_MEMBERCFG22_CTRL1_VS_UNTAGSET_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG22_CTRL1_VS_UNTAGSET_MASK 0xFF00 +#define RTL8367C_SVLAN_MEMBERCFG22_CTRL1_VS_SMBR_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG22_CTRL1_VS_SMBR_MASK 0xFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG22_CTRL2 0x0c44 +#define RTL8367C_SVLAN_MEMBERCFG22_CTRL2_VS_FIDEN_OFFSET 7 +#define RTL8367C_SVLAN_MEMBERCFG22_CTRL2_VS_FIDEN_MASK 0x80 +#define RTL8367C_SVLAN_MEMBERCFG22_CTRL2_VS_SPRI_OFFSET 4 +#define RTL8367C_SVLAN_MEMBERCFG22_CTRL2_VS_SPRI_MASK 0x70 +#define RTL8367C_SVLAN_MEMBERCFG22_CTRL2_VS_FID_MSTI_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG22_CTRL2_VS_FID_MSTI_MASK 0xF + +#define RTL8367C_REG_SVLAN_MEMBERCFG22_CTRL3 0x0c45 +#define RTL8367C_SVLAN_MEMBERCFG22_CTRL3_VS_EFID_OFFSET 13 +#define RTL8367C_SVLAN_MEMBERCFG22_CTRL3_VS_EFID_MASK 0xE000 +#define RTL8367C_SVLAN_MEMBERCFG22_CTRL3_VS_EFIDEN_OFFSET 12 +#define RTL8367C_SVLAN_MEMBERCFG22_CTRL3_VS_EFIDEN_MASK 0x1000 +#define RTL8367C_SVLAN_MEMBERCFG22_CTRL3_VS_SVID_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG22_CTRL3_VS_SVID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG23_CTRL1 0x0c46 +#define RTL8367C_SVLAN_MEMBERCFG23_CTRL1_VS_UNTAGSET_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG23_CTRL1_VS_UNTAGSET_MASK 0xFF00 +#define RTL8367C_SVLAN_MEMBERCFG23_CTRL1_VS_SMBR_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG23_CTRL1_VS_SMBR_MASK 0xFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG23_CTRL2 0x0c47 +#define RTL8367C_SVLAN_MEMBERCFG23_CTRL2_VS_FIDEN_OFFSET 7 +#define RTL8367C_SVLAN_MEMBERCFG23_CTRL2_VS_FIDEN_MASK 0x80 +#define RTL8367C_SVLAN_MEMBERCFG23_CTRL2_VS_SPRI_OFFSET 4 +#define RTL8367C_SVLAN_MEMBERCFG23_CTRL2_VS_SPRI_MASK 0x70 +#define RTL8367C_SVLAN_MEMBERCFG23_CTRL2_VS_FID_MSTI_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG23_CTRL2_VS_FID_MSTI_MASK 0xF + +#define RTL8367C_REG_SVLAN_MEMBERCFG23_CTRL3 0x0c48 +#define RTL8367C_SVLAN_MEMBERCFG23_CTRL3_VS_EFID_OFFSET 13 +#define RTL8367C_SVLAN_MEMBERCFG23_CTRL3_VS_EFID_MASK 0xE000 +#define RTL8367C_SVLAN_MEMBERCFG23_CTRL3_VS_EFIDEN_OFFSET 12 +#define RTL8367C_SVLAN_MEMBERCFG23_CTRL3_VS_EFIDEN_MASK 0x1000 +#define RTL8367C_SVLAN_MEMBERCFG23_CTRL3_VS_SVID_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG23_CTRL3_VS_SVID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG24_CTRL1 0x0c49 +#define RTL8367C_SVLAN_MEMBERCFG24_CTRL1_VS_UNTAGSET_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG24_CTRL1_VS_UNTAGSET_MASK 0xFF00 +#define RTL8367C_SVLAN_MEMBERCFG24_CTRL1_VS_SMBR_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG24_CTRL1_VS_SMBR_MASK 0xFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG24_CTRL2 0x0c4a +#define RTL8367C_SVLAN_MEMBERCFG24_CTRL2_VS_FIDEN_OFFSET 7 +#define RTL8367C_SVLAN_MEMBERCFG24_CTRL2_VS_FIDEN_MASK 0x80 +#define RTL8367C_SVLAN_MEMBERCFG24_CTRL2_VS_SPRI_OFFSET 4 +#define RTL8367C_SVLAN_MEMBERCFG24_CTRL2_VS_SPRI_MASK 0x70 +#define RTL8367C_SVLAN_MEMBERCFG24_CTRL2_VS_FID_MSTI_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG24_CTRL2_VS_FID_MSTI_MASK 0xF + +#define RTL8367C_REG_SVLAN_MEMBERCFG24_CTRL3 0x0c4b +#define RTL8367C_SVLAN_MEMBERCFG24_CTRL3_VS_EFID_OFFSET 13 +#define RTL8367C_SVLAN_MEMBERCFG24_CTRL3_VS_EFID_MASK 0xE000 +#define RTL8367C_SVLAN_MEMBERCFG24_CTRL3_VS_EFIDEN_OFFSET 12 +#define RTL8367C_SVLAN_MEMBERCFG24_CTRL3_VS_EFIDEN_MASK 0x1000 +#define RTL8367C_SVLAN_MEMBERCFG24_CTRL3_VS_SVID_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG24_CTRL3_VS_SVID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG25_CTRL1 0x0c4c +#define RTL8367C_SVLAN_MEMBERCFG25_CTRL1_VS_UNTAGSET_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG25_CTRL1_VS_UNTAGSET_MASK 0xFF00 +#define RTL8367C_SVLAN_MEMBERCFG25_CTRL1_VS_SMBR_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG25_CTRL1_VS_SMBR_MASK 0xFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG25_CTRL2 0x0c4d +#define RTL8367C_SVLAN_MEMBERCFG25_CTRL2_VS_FIDEN_OFFSET 7 +#define RTL8367C_SVLAN_MEMBERCFG25_CTRL2_VS_FIDEN_MASK 0x80 +#define RTL8367C_SVLAN_MEMBERCFG25_CTRL2_VS_SPRI_OFFSET 4 +#define RTL8367C_SVLAN_MEMBERCFG25_CTRL2_VS_SPRI_MASK 0x70 +#define RTL8367C_SVLAN_MEMBERCFG25_CTRL2_VS_FID_MSTI_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG25_CTRL2_VS_FID_MSTI_MASK 0xF + +#define RTL8367C_REG_SVLAN_MEMBERCFG25_CTRL3 0x0c4e +#define RTL8367C_SVLAN_MEMBERCFG25_CTRL3_VS_EFID_OFFSET 13 +#define RTL8367C_SVLAN_MEMBERCFG25_CTRL3_VS_EFID_MASK 0xE000 +#define RTL8367C_SVLAN_MEMBERCFG25_CTRL3_VS_EFIDEN_OFFSET 12 +#define RTL8367C_SVLAN_MEMBERCFG25_CTRL3_VS_EFIDEN_MASK 0x1000 +#define RTL8367C_SVLAN_MEMBERCFG25_CTRL3_VS_SVID_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG25_CTRL3_VS_SVID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG26_CTRL1 0x0c4f +#define RTL8367C_SVLAN_MEMBERCFG26_CTRL1_VS_UNTAGSET_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG26_CTRL1_VS_UNTAGSET_MASK 0xFF00 +#define RTL8367C_SVLAN_MEMBERCFG26_CTRL1_VS_SMBR_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG26_CTRL1_VS_SMBR_MASK 0xFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG26_CTRL2 0x0c50 +#define RTL8367C_SVLAN_MEMBERCFG26_CTRL2_VS_FIDEN_OFFSET 7 +#define RTL8367C_SVLAN_MEMBERCFG26_CTRL2_VS_FIDEN_MASK 0x80 +#define RTL8367C_SVLAN_MEMBERCFG26_CTRL2_VS_SPRI_OFFSET 4 +#define RTL8367C_SVLAN_MEMBERCFG26_CTRL2_VS_SPRI_MASK 0x70 +#define RTL8367C_SVLAN_MEMBERCFG26_CTRL2_VS_FID_MSTI_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG26_CTRL2_VS_FID_MSTI_MASK 0xF + +#define RTL8367C_REG_SVLAN_MEMBERCFG26_CTRL3 0x0c51 +#define RTL8367C_SVLAN_MEMBERCFG26_CTRL3_VS_EFID_OFFSET 13 +#define RTL8367C_SVLAN_MEMBERCFG26_CTRL3_VS_EFID_MASK 0xE000 +#define RTL8367C_SVLAN_MEMBERCFG26_CTRL3_VS_EFIDEN_OFFSET 12 +#define RTL8367C_SVLAN_MEMBERCFG26_CTRL3_VS_EFIDEN_MASK 0x1000 +#define RTL8367C_SVLAN_MEMBERCFG26_CTRL3_VS_SVID_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG26_CTRL3_VS_SVID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG27_CTRL1 0x0c52 +#define RTL8367C_SVLAN_MEMBERCFG27_CTRL1_VS_UNTAGSET_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG27_CTRL1_VS_UNTAGSET_MASK 0xFF00 +#define RTL8367C_SVLAN_MEMBERCFG27_CTRL1_VS_SMBR_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG27_CTRL1_VS_SMBR_MASK 0xFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG27_CTRL2 0x0c53 +#define RTL8367C_SVLAN_MEMBERCFG27_CTRL2_VS_FIDEN_OFFSET 7 +#define RTL8367C_SVLAN_MEMBERCFG27_CTRL2_VS_FIDEN_MASK 0x80 +#define RTL8367C_SVLAN_MEMBERCFG27_CTRL2_VS_SPRI_OFFSET 4 +#define RTL8367C_SVLAN_MEMBERCFG27_CTRL2_VS_SPRI_MASK 0x70 +#define RTL8367C_SVLAN_MEMBERCFG27_CTRL2_VS_FID_MSTI_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG27_CTRL2_VS_FID_MSTI_MASK 0xF + +#define RTL8367C_REG_SVLAN_MEMBERCFG27_CTRL3 0x0c54 +#define RTL8367C_SVLAN_MEMBERCFG27_CTRL3_VS_EFID_OFFSET 13 +#define RTL8367C_SVLAN_MEMBERCFG27_CTRL3_VS_EFID_MASK 0xE000 +#define RTL8367C_SVLAN_MEMBERCFG27_CTRL3_VS_EFIDEN_OFFSET 12 +#define RTL8367C_SVLAN_MEMBERCFG27_CTRL3_VS_EFIDEN_MASK 0x1000 +#define RTL8367C_SVLAN_MEMBERCFG27_CTRL3_VS_SVID_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG27_CTRL3_VS_SVID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG28_CTRL1 0x0c55 +#define RTL8367C_SVLAN_MEMBERCFG28_CTRL1_VS_UNTAGSET_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG28_CTRL1_VS_UNTAGSET_MASK 0xFF00 +#define RTL8367C_SVLAN_MEMBERCFG28_CTRL1_VS_SMBR_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG28_CTRL1_VS_SMBR_MASK 0xFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG28_CTRL2 0x0c56 +#define RTL8367C_SVLAN_MEMBERCFG28_CTRL2_VS_FIDEN_OFFSET 7 +#define RTL8367C_SVLAN_MEMBERCFG28_CTRL2_VS_FIDEN_MASK 0x80 +#define RTL8367C_SVLAN_MEMBERCFG28_CTRL2_VS_SPRI_OFFSET 4 +#define RTL8367C_SVLAN_MEMBERCFG28_CTRL2_VS_SPRI_MASK 0x70 +#define RTL8367C_SVLAN_MEMBERCFG28_CTRL2_VS_FID_MSTI_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG28_CTRL2_VS_FID_MSTI_MASK 0xF + +#define RTL8367C_REG_SVLAN_MEMBERCFG28_CTRL3 0x0c57 +#define RTL8367C_SVLAN_MEMBERCFG28_CTRL3_VS_EFID_OFFSET 13 +#define RTL8367C_SVLAN_MEMBERCFG28_CTRL3_VS_EFID_MASK 0xE000 +#define RTL8367C_SVLAN_MEMBERCFG28_CTRL3_VS_EFIDEN_OFFSET 12 +#define RTL8367C_SVLAN_MEMBERCFG28_CTRL3_VS_EFIDEN_MASK 0x1000 +#define RTL8367C_SVLAN_MEMBERCFG28_CTRL3_VS_SVID_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG28_CTRL3_VS_SVID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG29_CTRL1 0x0c58 +#define RTL8367C_SVLAN_MEMBERCFG29_CTRL1_VS_UNTAGSET_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG29_CTRL1_VS_UNTAGSET_MASK 0xFF00 +#define RTL8367C_SVLAN_MEMBERCFG29_CTRL1_VS_SMBR_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG29_CTRL1_VS_SMBR_MASK 0xFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG29_CTRL2 0x0c59 +#define RTL8367C_SVLAN_MEMBERCFG29_CTRL2_VS_FIDEN_OFFSET 7 +#define RTL8367C_SVLAN_MEMBERCFG29_CTRL2_VS_FIDEN_MASK 0x80 +#define RTL8367C_SVLAN_MEMBERCFG29_CTRL2_VS_SPRI_OFFSET 4 +#define RTL8367C_SVLAN_MEMBERCFG29_CTRL2_VS_SPRI_MASK 0x70 +#define RTL8367C_SVLAN_MEMBERCFG29_CTRL2_VS_FID_MSTI_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG29_CTRL2_VS_FID_MSTI_MASK 0xF + +#define RTL8367C_REG_SVLAN_MEMBERCFG29_CTRL3 0x0c5a +#define RTL8367C_SVLAN_MEMBERCFG29_CTRL3_VS_EFID_OFFSET 13 +#define RTL8367C_SVLAN_MEMBERCFG29_CTRL3_VS_EFID_MASK 0xE000 +#define RTL8367C_SVLAN_MEMBERCFG29_CTRL3_VS_EFIDEN_OFFSET 12 +#define RTL8367C_SVLAN_MEMBERCFG29_CTRL3_VS_EFIDEN_MASK 0x1000 +#define RTL8367C_SVLAN_MEMBERCFG29_CTRL3_VS_SVID_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG29_CTRL3_VS_SVID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG30_CTRL1 0x0c5b +#define RTL8367C_SVLAN_MEMBERCFG30_CTRL1_VS_UNTAGSET_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG30_CTRL1_VS_UNTAGSET_MASK 0xFF00 +#define RTL8367C_SVLAN_MEMBERCFG30_CTRL1_VS_SMBR_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG30_CTRL1_VS_SMBR_MASK 0xFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG30_CTRL2 0x0c5c +#define RTL8367C_SVLAN_MEMBERCFG30_CTRL2_VS_FIDEN_OFFSET 7 +#define RTL8367C_SVLAN_MEMBERCFG30_CTRL2_VS_FIDEN_MASK 0x80 +#define RTL8367C_SVLAN_MEMBERCFG30_CTRL2_VS_SPRI_OFFSET 4 +#define RTL8367C_SVLAN_MEMBERCFG30_CTRL2_VS_SPRI_MASK 0x70 +#define RTL8367C_SVLAN_MEMBERCFG30_CTRL2_VS_FID_MSTI_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG30_CTRL2_VS_FID_MSTI_MASK 0xF + +#define RTL8367C_REG_SVLAN_MEMBERCFG30_CTRL3 0x0c5d +#define RTL8367C_SVLAN_MEMBERCFG30_CTRL3_VS_EFID_OFFSET 13 +#define RTL8367C_SVLAN_MEMBERCFG30_CTRL3_VS_EFID_MASK 0xE000 +#define RTL8367C_SVLAN_MEMBERCFG30_CTRL3_VS_EFIDEN_OFFSET 12 +#define RTL8367C_SVLAN_MEMBERCFG30_CTRL3_VS_EFIDEN_MASK 0x1000 +#define RTL8367C_SVLAN_MEMBERCFG30_CTRL3_VS_SVID_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG30_CTRL3_VS_SVID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG31_CTRL1 0x0c5e +#define RTL8367C_SVLAN_MEMBERCFG31_CTRL1_VS_UNTAGSET_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG31_CTRL1_VS_UNTAGSET_MASK 0xFF00 +#define RTL8367C_SVLAN_MEMBERCFG31_CTRL1_VS_SMBR_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG31_CTRL1_VS_SMBR_MASK 0xFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG31_CTRL2 0x0c5f +#define RTL8367C_SVLAN_MEMBERCFG31_CTRL2_VS_FIDEN_OFFSET 7 +#define RTL8367C_SVLAN_MEMBERCFG31_CTRL2_VS_FIDEN_MASK 0x80 +#define RTL8367C_SVLAN_MEMBERCFG31_CTRL2_VS_SPRI_OFFSET 4 +#define RTL8367C_SVLAN_MEMBERCFG31_CTRL2_VS_SPRI_MASK 0x70 +#define RTL8367C_SVLAN_MEMBERCFG31_CTRL2_VS_FID_MSTI_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG31_CTRL2_VS_FID_MSTI_MASK 0xF + +#define RTL8367C_REG_SVLAN_MEMBERCFG31_CTRL3 0x0c60 +#define RTL8367C_SVLAN_MEMBERCFG31_CTRL3_VS_EFID_OFFSET 13 +#define RTL8367C_SVLAN_MEMBERCFG31_CTRL3_VS_EFID_MASK 0xE000 +#define RTL8367C_SVLAN_MEMBERCFG31_CTRL3_VS_EFIDEN_OFFSET 12 +#define RTL8367C_SVLAN_MEMBERCFG31_CTRL3_VS_EFIDEN_MASK 0x1000 +#define RTL8367C_SVLAN_MEMBERCFG31_CTRL3_VS_SVID_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG31_CTRL3_VS_SVID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG32_CTRL1 0x0c61 +#define RTL8367C_SVLAN_MEMBERCFG32_CTRL1_VS_UNTAGSET_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG32_CTRL1_VS_UNTAGSET_MASK 0xFF00 +#define RTL8367C_SVLAN_MEMBERCFG32_CTRL1_VS_SMBR_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG32_CTRL1_VS_SMBR_MASK 0xFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG32_CTRL2 0x0c62 +#define RTL8367C_SVLAN_MEMBERCFG32_CTRL2_VS_FIDEN_OFFSET 7 +#define RTL8367C_SVLAN_MEMBERCFG32_CTRL2_VS_FIDEN_MASK 0x80 +#define RTL8367C_SVLAN_MEMBERCFG32_CTRL2_VS_SPRI_OFFSET 4 +#define RTL8367C_SVLAN_MEMBERCFG32_CTRL2_VS_SPRI_MASK 0x70 +#define RTL8367C_SVLAN_MEMBERCFG32_CTRL2_VS_FID_MSTI_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG32_CTRL2_VS_FID_MSTI_MASK 0xF + +#define RTL8367C_REG_SVLAN_MEMBERCFG32_CTRL3 0x0c63 +#define RTL8367C_SVLAN_MEMBERCFG32_CTRL3_VS_EFID_OFFSET 13 +#define RTL8367C_SVLAN_MEMBERCFG32_CTRL3_VS_EFID_MASK 0xE000 +#define RTL8367C_SVLAN_MEMBERCFG32_CTRL3_VS_EFIDEN_OFFSET 12 +#define RTL8367C_SVLAN_MEMBERCFG32_CTRL3_VS_EFIDEN_MASK 0x1000 +#define RTL8367C_SVLAN_MEMBERCFG32_CTRL3_VS_SVID_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG32_CTRL3_VS_SVID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG33_CTRL1 0x0c64 +#define RTL8367C_SVLAN_MEMBERCFG33_CTRL1_VS_UNTAGSET_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG33_CTRL1_VS_UNTAGSET_MASK 0xFF00 +#define RTL8367C_SVLAN_MEMBERCFG33_CTRL1_VS_SMBR_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG33_CTRL1_VS_SMBR_MASK 0xFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG33_CTRL2 0x0c65 +#define RTL8367C_SVLAN_MEMBERCFG33_CTRL2_VS_FIDEN_OFFSET 7 +#define RTL8367C_SVLAN_MEMBERCFG33_CTRL2_VS_FIDEN_MASK 0x80 +#define RTL8367C_SVLAN_MEMBERCFG33_CTRL2_VS_SPRI_OFFSET 4 +#define RTL8367C_SVLAN_MEMBERCFG33_CTRL2_VS_SPRI_MASK 0x70 +#define RTL8367C_SVLAN_MEMBERCFG33_CTRL2_VS_FID_MSTI_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG33_CTRL2_VS_FID_MSTI_MASK 0xF + +#define RTL8367C_REG_SVLAN_MEMBERCFG33_CTRL3 0x0c66 +#define RTL8367C_SVLAN_MEMBERCFG33_CTRL3_VS_EFID_OFFSET 13 +#define RTL8367C_SVLAN_MEMBERCFG33_CTRL3_VS_EFID_MASK 0xE000 +#define RTL8367C_SVLAN_MEMBERCFG33_CTRL3_VS_EFIDEN_OFFSET 12 +#define RTL8367C_SVLAN_MEMBERCFG33_CTRL3_VS_EFIDEN_MASK 0x1000 +#define RTL8367C_SVLAN_MEMBERCFG33_CTRL3_VS_SVID_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG33_CTRL3_VS_SVID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG34_CTRL1 0x0c67 +#define RTL8367C_SVLAN_MEMBERCFG34_CTRL1_VS_UNTAGSET_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG34_CTRL1_VS_UNTAGSET_MASK 0xFF00 +#define RTL8367C_SVLAN_MEMBERCFG34_CTRL1_VS_SMBR_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG34_CTRL1_VS_SMBR_MASK 0xFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG34_CTRL2 0x0c68 +#define RTL8367C_SVLAN_MEMBERCFG34_CTRL2_VS_FIDEN_OFFSET 7 +#define RTL8367C_SVLAN_MEMBERCFG34_CTRL2_VS_FIDEN_MASK 0x80 +#define RTL8367C_SVLAN_MEMBERCFG34_CTRL2_VS_SPRI_OFFSET 4 +#define RTL8367C_SVLAN_MEMBERCFG34_CTRL2_VS_SPRI_MASK 0x70 +#define RTL8367C_SVLAN_MEMBERCFG34_CTRL2_VS_FID_MSTI_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG34_CTRL2_VS_FID_MSTI_MASK 0xF + +#define RTL8367C_REG_SVLAN_MEMBERCFG34_CTRL3 0x0c69 +#define RTL8367C_SVLAN_MEMBERCFG34_CTRL3_VS_EFID_OFFSET 13 +#define RTL8367C_SVLAN_MEMBERCFG34_CTRL3_VS_EFID_MASK 0xE000 +#define RTL8367C_SVLAN_MEMBERCFG34_CTRL3_VS_EFIDEN_OFFSET 12 +#define RTL8367C_SVLAN_MEMBERCFG34_CTRL3_VS_EFIDEN_MASK 0x1000 +#define RTL8367C_SVLAN_MEMBERCFG34_CTRL3_VS_SVID_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG34_CTRL3_VS_SVID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG35_CTRL1 0x0c6a +#define RTL8367C_SVLAN_MEMBERCFG35_CTRL1_VS_UNTAGSET_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG35_CTRL1_VS_UNTAGSET_MASK 0xFF00 +#define RTL8367C_SVLAN_MEMBERCFG35_CTRL1_VS_SMBR_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG35_CTRL1_VS_SMBR_MASK 0xFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG35_CTRL2 0x0c6b +#define RTL8367C_SVLAN_MEMBERCFG35_CTRL2_VS_FIDEN_OFFSET 7 +#define RTL8367C_SVLAN_MEMBERCFG35_CTRL2_VS_FIDEN_MASK 0x80 +#define RTL8367C_SVLAN_MEMBERCFG35_CTRL2_VS_SPRI_OFFSET 4 +#define RTL8367C_SVLAN_MEMBERCFG35_CTRL2_VS_SPRI_MASK 0x70 +#define RTL8367C_SVLAN_MEMBERCFG35_CTRL2_VS_FID_MSTI_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG35_CTRL2_VS_FID_MSTI_MASK 0xF + +#define RTL8367C_REG_SVLAN_MEMBERCFG35_CTRL3 0x0c6c +#define RTL8367C_SVLAN_MEMBERCFG35_CTRL3_VS_EFID_OFFSET 13 +#define RTL8367C_SVLAN_MEMBERCFG35_CTRL3_VS_EFID_MASK 0xE000 +#define RTL8367C_SVLAN_MEMBERCFG35_CTRL3_VS_EFIDEN_OFFSET 12 +#define RTL8367C_SVLAN_MEMBERCFG35_CTRL3_VS_EFIDEN_MASK 0x1000 +#define RTL8367C_SVLAN_MEMBERCFG35_CTRL3_VS_SVID_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG35_CTRL3_VS_SVID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG36_CTRL1 0x0c6d +#define RTL8367C_SVLAN_MEMBERCFG36_CTRL1_VS_UNTAGSET_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG36_CTRL1_VS_UNTAGSET_MASK 0xFF00 +#define RTL8367C_SVLAN_MEMBERCFG36_CTRL1_VS_SMBR_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG36_CTRL1_VS_SMBR_MASK 0xFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG36_CTRL2 0x0c6e +#define RTL8367C_SVLAN_MEMBERCFG36_CTRL2_VS_FIDEN_OFFSET 7 +#define RTL8367C_SVLAN_MEMBERCFG36_CTRL2_VS_FIDEN_MASK 0x80 +#define RTL8367C_SVLAN_MEMBERCFG36_CTRL2_VS_SPRI_OFFSET 4 +#define RTL8367C_SVLAN_MEMBERCFG36_CTRL2_VS_SPRI_MASK 0x70 +#define RTL8367C_SVLAN_MEMBERCFG36_CTRL2_VS_FID_MSTI_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG36_CTRL2_VS_FID_MSTI_MASK 0xF + +#define RTL8367C_REG_SVLAN_MEMBERCFG36_CTRL3 0x0c6f +#define RTL8367C_SVLAN_MEMBERCFG36_CTRL3_VS_EFID_OFFSET 13 +#define RTL8367C_SVLAN_MEMBERCFG36_CTRL3_VS_EFID_MASK 0xE000 +#define RTL8367C_SVLAN_MEMBERCFG36_CTRL3_VS_EFIDEN_OFFSET 12 +#define RTL8367C_SVLAN_MEMBERCFG36_CTRL3_VS_EFIDEN_MASK 0x1000 +#define RTL8367C_SVLAN_MEMBERCFG36_CTRL3_VS_SVID_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG36_CTRL3_VS_SVID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG37_CTRL1 0x0c70 +#define RTL8367C_SVLAN_MEMBERCFG37_CTRL1_VS_UNTAGSET_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG37_CTRL1_VS_UNTAGSET_MASK 0xFF00 +#define RTL8367C_SVLAN_MEMBERCFG37_CTRL1_VS_SMBR_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG37_CTRL1_VS_SMBR_MASK 0xFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG37_CTRL2 0x0c71 +#define RTL8367C_SVLAN_MEMBERCFG37_CTRL2_VS_FIDEN_OFFSET 7 +#define RTL8367C_SVLAN_MEMBERCFG37_CTRL2_VS_FIDEN_MASK 0x80 +#define RTL8367C_SVLAN_MEMBERCFG37_CTRL2_VS_SPRI_OFFSET 4 +#define RTL8367C_SVLAN_MEMBERCFG37_CTRL2_VS_SPRI_MASK 0x70 +#define RTL8367C_SVLAN_MEMBERCFG37_CTRL2_VS_FID_MSTI_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG37_CTRL2_VS_FID_MSTI_MASK 0xF + +#define RTL8367C_REG_SVLAN_MEMBERCFG37_CTRL3 0x0c72 +#define RTL8367C_SVLAN_MEMBERCFG37_CTRL3_VS_EFID_OFFSET 13 +#define RTL8367C_SVLAN_MEMBERCFG37_CTRL3_VS_EFID_MASK 0xE000 +#define RTL8367C_SVLAN_MEMBERCFG37_CTRL3_VS_EFIDEN_OFFSET 12 +#define RTL8367C_SVLAN_MEMBERCFG37_CTRL3_VS_EFIDEN_MASK 0x1000 +#define RTL8367C_SVLAN_MEMBERCFG37_CTRL3_VS_SVID_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG37_CTRL3_VS_SVID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG38_CTRL1 0x0c73 +#define RTL8367C_SVLAN_MEMBERCFG38_CTRL1_VS_UNTAGSET_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG38_CTRL1_VS_UNTAGSET_MASK 0xFF00 +#define RTL8367C_SVLAN_MEMBERCFG38_CTRL1_VS_SMBR_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG38_CTRL1_VS_SMBR_MASK 0xFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG38_CTRL2 0x0c74 +#define RTL8367C_SVLAN_MEMBERCFG38_CTRL2_VS_FIDEN_OFFSET 7 +#define RTL8367C_SVLAN_MEMBERCFG38_CTRL2_VS_FIDEN_MASK 0x80 +#define RTL8367C_SVLAN_MEMBERCFG38_CTRL2_VS_SPRI_OFFSET 4 +#define RTL8367C_SVLAN_MEMBERCFG38_CTRL2_VS_SPRI_MASK 0x70 +#define RTL8367C_SVLAN_MEMBERCFG38_CTRL2_VS_FID_MSTI_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG38_CTRL2_VS_FID_MSTI_MASK 0xF + +#define RTL8367C_REG_SVLAN_MEMBERCFG38_CTRL3 0x0c75 +#define RTL8367C_SVLAN_MEMBERCFG38_CTRL3_VS_EFID_OFFSET 13 +#define RTL8367C_SVLAN_MEMBERCFG38_CTRL3_VS_EFID_MASK 0xE000 +#define RTL8367C_SVLAN_MEMBERCFG38_CTRL3_VS_EFIDEN_OFFSET 12 +#define RTL8367C_SVLAN_MEMBERCFG38_CTRL3_VS_EFIDEN_MASK 0x1000 +#define RTL8367C_SVLAN_MEMBERCFG38_CTRL3_VS_SVID_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG38_CTRL3_VS_SVID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG39_CTRL1 0x0c76 +#define RTL8367C_SVLAN_MEMBERCFG39_CTRL1_VS_UNTAGSET_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG39_CTRL1_VS_UNTAGSET_MASK 0xFF00 +#define RTL8367C_SVLAN_MEMBERCFG39_CTRL1_VS_SMBR_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG39_CTRL1_VS_SMBR_MASK 0xFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG39_CTRL2 0x0c77 +#define RTL8367C_SVLAN_MEMBERCFG39_CTRL2_VS_FIDEN_OFFSET 7 +#define RTL8367C_SVLAN_MEMBERCFG39_CTRL2_VS_FIDEN_MASK 0x80 +#define RTL8367C_SVLAN_MEMBERCFG39_CTRL2_VS_SPRI_OFFSET 4 +#define RTL8367C_SVLAN_MEMBERCFG39_CTRL2_VS_SPRI_MASK 0x70 +#define RTL8367C_SVLAN_MEMBERCFG39_CTRL2_VS_FID_MSTI_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG39_CTRL2_VS_FID_MSTI_MASK 0xF + +#define RTL8367C_REG_SVLAN_MEMBERCFG39_CTRL3 0x0c78 +#define RTL8367C_SVLAN_MEMBERCFG39_CTRL3_VS_EFID_OFFSET 13 +#define RTL8367C_SVLAN_MEMBERCFG39_CTRL3_VS_EFID_MASK 0xE000 +#define RTL8367C_SVLAN_MEMBERCFG39_CTRL3_VS_EFIDEN_OFFSET 12 +#define RTL8367C_SVLAN_MEMBERCFG39_CTRL3_VS_EFIDEN_MASK 0x1000 +#define RTL8367C_SVLAN_MEMBERCFG39_CTRL3_VS_SVID_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG39_CTRL3_VS_SVID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG40_CTRL1 0x0c79 +#define RTL8367C_SVLAN_MEMBERCFG40_CTRL1_VS_UNTAGSET_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG40_CTRL1_VS_UNTAGSET_MASK 0xFF00 +#define RTL8367C_SVLAN_MEMBERCFG40_CTRL1_VS_SMBR_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG40_CTRL1_VS_SMBR_MASK 0xFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG40_CTRL2 0x0c7a +#define RTL8367C_SVLAN_MEMBERCFG40_CTRL2_VS_FIDEN_OFFSET 7 +#define RTL8367C_SVLAN_MEMBERCFG40_CTRL2_VS_FIDEN_MASK 0x80 +#define RTL8367C_SVLAN_MEMBERCFG40_CTRL2_VS_SPRI_OFFSET 4 +#define RTL8367C_SVLAN_MEMBERCFG40_CTRL2_VS_SPRI_MASK 0x70 +#define RTL8367C_SVLAN_MEMBERCFG40_CTRL2_VS_FID_MSTI_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG40_CTRL2_VS_FID_MSTI_MASK 0xF + +#define RTL8367C_REG_SVLAN_MEMBERCFG40_CTRL3 0x0c7b +#define RTL8367C_SVLAN_MEMBERCFG40_CTRL3_VS_EFID_OFFSET 13 +#define RTL8367C_SVLAN_MEMBERCFG40_CTRL3_VS_EFID_MASK 0xE000 +#define RTL8367C_SVLAN_MEMBERCFG40_CTRL3_VS_EFIDEN_OFFSET 12 +#define RTL8367C_SVLAN_MEMBERCFG40_CTRL3_VS_EFIDEN_MASK 0x1000 +#define RTL8367C_SVLAN_MEMBERCFG40_CTRL3_VS_SVID_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG40_CTRL3_VS_SVID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG41_CTRL1 0x0c7c +#define RTL8367C_SVLAN_MEMBERCFG41_CTRL1_VS_UNTAGSET_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG41_CTRL1_VS_UNTAGSET_MASK 0xFF00 +#define RTL8367C_SVLAN_MEMBERCFG41_CTRL1_VS_SMBR_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG41_CTRL1_VS_SMBR_MASK 0xFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG41_CTRL2 0x0c7d +#define RTL8367C_SVLAN_MEMBERCFG41_CTRL2_VS_FIDEN_OFFSET 7 +#define RTL8367C_SVLAN_MEMBERCFG41_CTRL2_VS_FIDEN_MASK 0x80 +#define RTL8367C_SVLAN_MEMBERCFG41_CTRL2_VS_SPRI_OFFSET 4 +#define RTL8367C_SVLAN_MEMBERCFG41_CTRL2_VS_SPRI_MASK 0x70 +#define RTL8367C_SVLAN_MEMBERCFG41_CTRL2_VS_FID_MSTI_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG41_CTRL2_VS_FID_MSTI_MASK 0xF + +#define RTL8367C_REG_SVLAN_MEMBERCFG41_CTRL3 0x0c7e +#define RTL8367C_SVLAN_MEMBERCFG41_CTRL3_VS_EFID_OFFSET 13 +#define RTL8367C_SVLAN_MEMBERCFG41_CTRL3_VS_EFID_MASK 0xE000 +#define RTL8367C_SVLAN_MEMBERCFG41_CTRL3_VS_EFIDEN_OFFSET 12 +#define RTL8367C_SVLAN_MEMBERCFG41_CTRL3_VS_EFIDEN_MASK 0x1000 +#define RTL8367C_SVLAN_MEMBERCFG41_CTRL3_VS_SVID_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG41_CTRL3_VS_SVID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG42_CTRL1 0x0c7f +#define RTL8367C_SVLAN_MEMBERCFG42_CTRL1_VS_UNTAGSET_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG42_CTRL1_VS_UNTAGSET_MASK 0xFF00 +#define RTL8367C_SVLAN_MEMBERCFG42_CTRL1_VS_SMBR_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG42_CTRL1_VS_SMBR_MASK 0xFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG42_CTRL2 0x0c80 +#define RTL8367C_SVLAN_MEMBERCFG42_CTRL2_VS_FIDEN_OFFSET 7 +#define RTL8367C_SVLAN_MEMBERCFG42_CTRL2_VS_FIDEN_MASK 0x80 +#define RTL8367C_SVLAN_MEMBERCFG42_CTRL2_VS_SPRI_OFFSET 4 +#define RTL8367C_SVLAN_MEMBERCFG42_CTRL2_VS_SPRI_MASK 0x70 +#define RTL8367C_SVLAN_MEMBERCFG42_CTRL2_VS_FID_MSTI_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG42_CTRL2_VS_FID_MSTI_MASK 0xF + +#define RTL8367C_REG_SVLAN_MEMBERCFG42_CTRL3 0x0c81 +#define RTL8367C_SVLAN_MEMBERCFG42_CTRL3_VS_EFID_OFFSET 13 +#define RTL8367C_SVLAN_MEMBERCFG42_CTRL3_VS_EFID_MASK 0xE000 +#define RTL8367C_SVLAN_MEMBERCFG42_CTRL3_VS_EFIDEN_OFFSET 12 +#define RTL8367C_SVLAN_MEMBERCFG42_CTRL3_VS_EFIDEN_MASK 0x1000 +#define RTL8367C_SVLAN_MEMBERCFG42_CTRL3_VS_SVID_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG42_CTRL3_VS_SVID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG43_CTRL1 0x0c82 +#define RTL8367C_SVLAN_MEMBERCFG43_CTRL1_VS_UNTAGSET_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG43_CTRL1_VS_UNTAGSET_MASK 0xFF00 +#define RTL8367C_SVLAN_MEMBERCFG43_CTRL1_VS_SMBR_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG43_CTRL1_VS_SMBR_MASK 0xFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG43_CTRL2 0x0c83 +#define RTL8367C_SVLAN_MEMBERCFG43_CTRL2_VS_FIDEN_OFFSET 7 +#define RTL8367C_SVLAN_MEMBERCFG43_CTRL2_VS_FIDEN_MASK 0x80 +#define RTL8367C_SVLAN_MEMBERCFG43_CTRL2_VS_SPRI_OFFSET 4 +#define RTL8367C_SVLAN_MEMBERCFG43_CTRL2_VS_SPRI_MASK 0x70 +#define RTL8367C_SVLAN_MEMBERCFG43_CTRL2_VS_FID_MSTI_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG43_CTRL2_VS_FID_MSTI_MASK 0xF + +#define RTL8367C_REG_SVLAN_MEMBERCFG43_CTRL3 0x0c84 +#define RTL8367C_SVLAN_MEMBERCFG43_CTRL3_VS_EFID_OFFSET 13 +#define RTL8367C_SVLAN_MEMBERCFG43_CTRL3_VS_EFID_MASK 0xE000 +#define RTL8367C_SVLAN_MEMBERCFG43_CTRL3_VS_EFIDEN_OFFSET 12 +#define RTL8367C_SVLAN_MEMBERCFG43_CTRL3_VS_EFIDEN_MASK 0x1000 +#define RTL8367C_SVLAN_MEMBERCFG43_CTRL3_VS_SVID_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG43_CTRL3_VS_SVID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG44_CTRL1 0x0c85 +#define RTL8367C_SVLAN_MEMBERCFG44_CTRL1_VS_UNTAGSET_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG44_CTRL1_VS_UNTAGSET_MASK 0xFF00 +#define RTL8367C_SVLAN_MEMBERCFG44_CTRL1_VS_SMBR_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG44_CTRL1_VS_SMBR_MASK 0xFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG44_CTRL2 0x0c86 +#define RTL8367C_SVLAN_MEMBERCFG44_CTRL2_VS_FIDEN_OFFSET 7 +#define RTL8367C_SVLAN_MEMBERCFG44_CTRL2_VS_FIDEN_MASK 0x80 +#define RTL8367C_SVLAN_MEMBERCFG44_CTRL2_VS_SPRI_OFFSET 4 +#define RTL8367C_SVLAN_MEMBERCFG44_CTRL2_VS_SPRI_MASK 0x70 +#define RTL8367C_SVLAN_MEMBERCFG44_CTRL2_VS_FID_MSTI_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG44_CTRL2_VS_FID_MSTI_MASK 0xF + +#define RTL8367C_REG_SVLAN_MEMBERCFG44_CTRL3 0x0c87 +#define RTL8367C_SVLAN_MEMBERCFG44_CTRL3_VS_EFID_OFFSET 13 +#define RTL8367C_SVLAN_MEMBERCFG44_CTRL3_VS_EFID_MASK 0xE000 +#define RTL8367C_SVLAN_MEMBERCFG44_CTRL3_VS_EFIDEN_OFFSET 12 +#define RTL8367C_SVLAN_MEMBERCFG44_CTRL3_VS_EFIDEN_MASK 0x1000 +#define RTL8367C_SVLAN_MEMBERCFG44_CTRL3_VS_SVID_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG44_CTRL3_VS_SVID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG45_CTRL1 0x0c88 +#define RTL8367C_SVLAN_MEMBERCFG45_CTRL1_VS_UNTAGSET_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG45_CTRL1_VS_UNTAGSET_MASK 0xFF00 +#define RTL8367C_SVLAN_MEMBERCFG45_CTRL1_VS_SMBR_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG45_CTRL1_VS_SMBR_MASK 0xFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG45_CTRL2 0x0c89 +#define RTL8367C_SVLAN_MEMBERCFG45_CTRL2_VS_FIDEN_OFFSET 7 +#define RTL8367C_SVLAN_MEMBERCFG45_CTRL2_VS_FIDEN_MASK 0x80 +#define RTL8367C_SVLAN_MEMBERCFG45_CTRL2_VS_SPRI_OFFSET 4 +#define RTL8367C_SVLAN_MEMBERCFG45_CTRL2_VS_SPRI_MASK 0x70 +#define RTL8367C_SVLAN_MEMBERCFG45_CTRL2_VS_FID_MSTI_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG45_CTRL2_VS_FID_MSTI_MASK 0xF + +#define RTL8367C_REG_SVLAN_MEMBERCFG45_CTRL3 0x0c8a +#define RTL8367C_SVLAN_MEMBERCFG45_CTRL3_VS_EFID_OFFSET 13 +#define RTL8367C_SVLAN_MEMBERCFG45_CTRL3_VS_EFID_MASK 0xE000 +#define RTL8367C_SVLAN_MEMBERCFG45_CTRL3_VS_EFIDEN_OFFSET 12 +#define RTL8367C_SVLAN_MEMBERCFG45_CTRL3_VS_EFIDEN_MASK 0x1000 +#define RTL8367C_SVLAN_MEMBERCFG45_CTRL3_VS_SVID_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG45_CTRL3_VS_SVID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG46_CTRL1 0x0c8b +#define RTL8367C_SVLAN_MEMBERCFG46_CTRL1_VS_UNTAGSET_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG46_CTRL1_VS_UNTAGSET_MASK 0xFF00 +#define RTL8367C_SVLAN_MEMBERCFG46_CTRL1_VS_SMBR_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG46_CTRL1_VS_SMBR_MASK 0xFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG46_CTRL2 0x0c8c +#define RTL8367C_SVLAN_MEMBERCFG46_CTRL2_VS_FIDEN_OFFSET 7 +#define RTL8367C_SVLAN_MEMBERCFG46_CTRL2_VS_FIDEN_MASK 0x80 +#define RTL8367C_SVLAN_MEMBERCFG46_CTRL2_VS_SPRI_OFFSET 4 +#define RTL8367C_SVLAN_MEMBERCFG46_CTRL2_VS_SPRI_MASK 0x70 +#define RTL8367C_SVLAN_MEMBERCFG46_CTRL2_VS_FID_MSTI_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG46_CTRL2_VS_FID_MSTI_MASK 0xF + +#define RTL8367C_REG_SVLAN_MEMBERCFG46_CTRL3 0x0c8d +#define RTL8367C_SVLAN_MEMBERCFG46_CTRL3_VS_EFID_OFFSET 13 +#define RTL8367C_SVLAN_MEMBERCFG46_CTRL3_VS_EFID_MASK 0xE000 +#define RTL8367C_SVLAN_MEMBERCFG46_CTRL3_VS_EFIDEN_OFFSET 12 +#define RTL8367C_SVLAN_MEMBERCFG46_CTRL3_VS_EFIDEN_MASK 0x1000 +#define RTL8367C_SVLAN_MEMBERCFG46_CTRL3_VS_SVID_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG46_CTRL3_VS_SVID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG47_CTRL1 0x0c8e +#define RTL8367C_SVLAN_MEMBERCFG47_CTRL1_VS_UNTAGSET_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG47_CTRL1_VS_UNTAGSET_MASK 0xFF00 +#define RTL8367C_SVLAN_MEMBERCFG47_CTRL1_VS_SMBR_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG47_CTRL1_VS_SMBR_MASK 0xFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG47_CTRL2 0x0c8f +#define RTL8367C_SVLAN_MEMBERCFG47_CTRL2_VS_FIDEN_OFFSET 7 +#define RTL8367C_SVLAN_MEMBERCFG47_CTRL2_VS_FIDEN_MASK 0x80 +#define RTL8367C_SVLAN_MEMBERCFG47_CTRL2_VS_SPRI_OFFSET 4 +#define RTL8367C_SVLAN_MEMBERCFG47_CTRL2_VS_SPRI_MASK 0x70 +#define RTL8367C_SVLAN_MEMBERCFG47_CTRL2_VS_FID_MSTI_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG47_CTRL2_VS_FID_MSTI_MASK 0xF + +#define RTL8367C_REG_SVLAN_MEMBERCFG47_CTRL3 0x0c90 +#define RTL8367C_SVLAN_MEMBERCFG47_CTRL3_VS_EFID_OFFSET 13 +#define RTL8367C_SVLAN_MEMBERCFG47_CTRL3_VS_EFID_MASK 0xE000 +#define RTL8367C_SVLAN_MEMBERCFG47_CTRL3_VS_EFIDEN_OFFSET 12 +#define RTL8367C_SVLAN_MEMBERCFG47_CTRL3_VS_EFIDEN_MASK 0x1000 +#define RTL8367C_SVLAN_MEMBERCFG47_CTRL3_VS_SVID_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG47_CTRL3_VS_SVID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG48_CTRL1 0x0c91 +#define RTL8367C_SVLAN_MEMBERCFG48_CTRL1_VS_UNTAGSET_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG48_CTRL1_VS_UNTAGSET_MASK 0xFF00 +#define RTL8367C_SVLAN_MEMBERCFG48_CTRL1_VS_SMBR_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG48_CTRL1_VS_SMBR_MASK 0xFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG48_CTRL2 0x0c92 +#define RTL8367C_SVLAN_MEMBERCFG48_CTRL2_VS_FIDEN_OFFSET 7 +#define RTL8367C_SVLAN_MEMBERCFG48_CTRL2_VS_FIDEN_MASK 0x80 +#define RTL8367C_SVLAN_MEMBERCFG48_CTRL2_VS_SPRI_OFFSET 4 +#define RTL8367C_SVLAN_MEMBERCFG48_CTRL2_VS_SPRI_MASK 0x70 +#define RTL8367C_SVLAN_MEMBERCFG48_CTRL2_VS_FID_MSTI_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG48_CTRL2_VS_FID_MSTI_MASK 0xF + +#define RTL8367C_REG_SVLAN_MEMBERCFG48_CTRL3 0x0c93 +#define RTL8367C_SVLAN_MEMBERCFG48_CTRL3_VS_EFID_OFFSET 13 +#define RTL8367C_SVLAN_MEMBERCFG48_CTRL3_VS_EFID_MASK 0xE000 +#define RTL8367C_SVLAN_MEMBERCFG48_CTRL3_VS_EFIDEN_OFFSET 12 +#define RTL8367C_SVLAN_MEMBERCFG48_CTRL3_VS_EFIDEN_MASK 0x1000 +#define RTL8367C_SVLAN_MEMBERCFG48_CTRL3_VS_SVID_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG48_CTRL3_VS_SVID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG49_CTRL1 0x0c94 +#define RTL8367C_SVLAN_MEMBERCFG49_CTRL1_VS_UNTAGSET_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG49_CTRL1_VS_UNTAGSET_MASK 0xFF00 +#define RTL8367C_SVLAN_MEMBERCFG49_CTRL1_VS_SMBR_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG49_CTRL1_VS_SMBR_MASK 0xFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG49_CTRL2 0x0c95 +#define RTL8367C_SVLAN_MEMBERCFG49_CTRL2_VS_FIDEN_OFFSET 7 +#define RTL8367C_SVLAN_MEMBERCFG49_CTRL2_VS_FIDEN_MASK 0x80 +#define RTL8367C_SVLAN_MEMBERCFG49_CTRL2_VS_SPRI_OFFSET 4 +#define RTL8367C_SVLAN_MEMBERCFG49_CTRL2_VS_SPRI_MASK 0x70 +#define RTL8367C_SVLAN_MEMBERCFG49_CTRL2_VS_FID_MSTI_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG49_CTRL2_VS_FID_MSTI_MASK 0xF + +#define RTL8367C_REG_SVLAN_MEMBERCFG49_CTRL3 0x0c96 +#define RTL8367C_SVLAN_MEMBERCFG49_CTRL3_VS_EFID_OFFSET 13 +#define RTL8367C_SVLAN_MEMBERCFG49_CTRL3_VS_EFID_MASK 0xE000 +#define RTL8367C_SVLAN_MEMBERCFG49_CTRL3_VS_EFIDEN_OFFSET 12 +#define RTL8367C_SVLAN_MEMBERCFG49_CTRL3_VS_EFIDEN_MASK 0x1000 +#define RTL8367C_SVLAN_MEMBERCFG49_CTRL3_VS_SVID_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG49_CTRL3_VS_SVID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG50_CTRL1 0x0c97 +#define RTL8367C_SVLAN_MEMBERCFG50_CTRL1_VS_UNTAGSET_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG50_CTRL1_VS_UNTAGSET_MASK 0xFF00 +#define RTL8367C_SVLAN_MEMBERCFG50_CTRL1_VS_SMBR_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG50_CTRL1_VS_SMBR_MASK 0xFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG50_CTRL2 0x0c98 +#define RTL8367C_SVLAN_MEMBERCFG50_CTRL2_VS_FIDEN_OFFSET 7 +#define RTL8367C_SVLAN_MEMBERCFG50_CTRL2_VS_FIDEN_MASK 0x80 +#define RTL8367C_SVLAN_MEMBERCFG50_CTRL2_VS_SPRI_OFFSET 4 +#define RTL8367C_SVLAN_MEMBERCFG50_CTRL2_VS_SPRI_MASK 0x70 +#define RTL8367C_SVLAN_MEMBERCFG50_CTRL2_VS_FID_MSTI_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG50_CTRL2_VS_FID_MSTI_MASK 0xF + +#define RTL8367C_REG_SVLAN_MEMBERCFG50_CTRL3 0x0c99 +#define RTL8367C_SVLAN_MEMBERCFG50_CTRL3_VS_EFID_OFFSET 13 +#define RTL8367C_SVLAN_MEMBERCFG50_CTRL3_VS_EFID_MASK 0xE000 +#define RTL8367C_SVLAN_MEMBERCFG50_CTRL3_VS_EFIDEN_OFFSET 12 +#define RTL8367C_SVLAN_MEMBERCFG50_CTRL3_VS_EFIDEN_MASK 0x1000 +#define RTL8367C_SVLAN_MEMBERCFG50_CTRL3_VS_SVID_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG50_CTRL3_VS_SVID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG51_CTRL1 0x0c9a +#define RTL8367C_SVLAN_MEMBERCFG51_CTRL1_VS_UNTAGSET_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG51_CTRL1_VS_UNTAGSET_MASK 0xFF00 +#define RTL8367C_SVLAN_MEMBERCFG51_CTRL1_VS_SMBR_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG51_CTRL1_VS_SMBR_MASK 0xFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG51_CTRL2 0x0c9b +#define RTL8367C_SVLAN_MEMBERCFG51_CTRL2_VS_FIDEN_OFFSET 7 +#define RTL8367C_SVLAN_MEMBERCFG51_CTRL2_VS_FIDEN_MASK 0x80 +#define RTL8367C_SVLAN_MEMBERCFG51_CTRL2_VS_SPRI_OFFSET 4 +#define RTL8367C_SVLAN_MEMBERCFG51_CTRL2_VS_SPRI_MASK 0x70 +#define RTL8367C_SVLAN_MEMBERCFG51_CTRL2_VS_FID_MSTI_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG51_CTRL2_VS_FID_MSTI_MASK 0xF + +#define RTL8367C_REG_SVLAN_MEMBERCFG51_CTRL3 0x0c9c +#define RTL8367C_SVLAN_MEMBERCFG51_CTRL3_VS_EFID_OFFSET 13 +#define RTL8367C_SVLAN_MEMBERCFG51_CTRL3_VS_EFID_MASK 0xE000 +#define RTL8367C_SVLAN_MEMBERCFG51_CTRL3_VS_EFIDEN_OFFSET 12 +#define RTL8367C_SVLAN_MEMBERCFG51_CTRL3_VS_EFIDEN_MASK 0x1000 +#define RTL8367C_SVLAN_MEMBERCFG51_CTRL3_VS_SVID_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG51_CTRL3_VS_SVID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG52_CTRL1 0x0c9d +#define RTL8367C_SVLAN_MEMBERCFG52_CTRL1_VS_UNTAGSET_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG52_CTRL1_VS_UNTAGSET_MASK 0xFF00 +#define RTL8367C_SVLAN_MEMBERCFG52_CTRL1_VS_SMBR_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG52_CTRL1_VS_SMBR_MASK 0xFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG52_CTRL2 0x0c9e +#define RTL8367C_SVLAN_MEMBERCFG52_CTRL2_VS_FIDEN_OFFSET 7 +#define RTL8367C_SVLAN_MEMBERCFG52_CTRL2_VS_FIDEN_MASK 0x80 +#define RTL8367C_SVLAN_MEMBERCFG52_CTRL2_VS_SPRI_OFFSET 4 +#define RTL8367C_SVLAN_MEMBERCFG52_CTRL2_VS_SPRI_MASK 0x70 +#define RTL8367C_SVLAN_MEMBERCFG52_CTRL2_VS_FID_MSTI_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG52_CTRL2_VS_FID_MSTI_MASK 0xF + +#define RTL8367C_REG_SVLAN_MEMBERCFG52_CTRL3 0x0c9f +#define RTL8367C_SVLAN_MEMBERCFG52_CTRL3_VS_EFID_OFFSET 13 +#define RTL8367C_SVLAN_MEMBERCFG52_CTRL3_VS_EFID_MASK 0xE000 +#define RTL8367C_SVLAN_MEMBERCFG52_CTRL3_VS_EFIDEN_OFFSET 12 +#define RTL8367C_SVLAN_MEMBERCFG52_CTRL3_VS_EFIDEN_MASK 0x1000 +#define RTL8367C_SVLAN_MEMBERCFG52_CTRL3_VS_SVID_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG52_CTRL3_VS_SVID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG53_CTRL1 0x0ca0 +#define RTL8367C_SVLAN_MEMBERCFG53_CTRL1_VS_UNTAGSET_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG53_CTRL1_VS_UNTAGSET_MASK 0xFF00 +#define RTL8367C_SVLAN_MEMBERCFG53_CTRL1_VS_SMBR_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG53_CTRL1_VS_SMBR_MASK 0xFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG53_CTRL2 0x0ca1 +#define RTL8367C_SVLAN_MEMBERCFG53_CTRL2_VS_FIDEN_OFFSET 7 +#define RTL8367C_SVLAN_MEMBERCFG53_CTRL2_VS_FIDEN_MASK 0x80 +#define RTL8367C_SVLAN_MEMBERCFG53_CTRL2_VS_SPRI_OFFSET 4 +#define RTL8367C_SVLAN_MEMBERCFG53_CTRL2_VS_SPRI_MASK 0x70 +#define RTL8367C_SVLAN_MEMBERCFG53_CTRL2_VS_FID_MSTI_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG53_CTRL2_VS_FID_MSTI_MASK 0xF + +#define RTL8367C_REG_SVLAN_MEMBERCFG53_CTRL3 0x0ca2 +#define RTL8367C_SVLAN_MEMBERCFG53_CTRL3_VS_EFID_OFFSET 13 +#define RTL8367C_SVLAN_MEMBERCFG53_CTRL3_VS_EFID_MASK 0xE000 +#define RTL8367C_SVLAN_MEMBERCFG53_CTRL3_VS_EFIDEN_OFFSET 12 +#define RTL8367C_SVLAN_MEMBERCFG53_CTRL3_VS_EFIDEN_MASK 0x1000 +#define RTL8367C_SVLAN_MEMBERCFG53_CTRL3_VS_SVID_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG53_CTRL3_VS_SVID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG54_CTRL1 0x0ca3 +#define RTL8367C_SVLAN_MEMBERCFG54_CTRL1_VS_UNTAGSET_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG54_CTRL1_VS_UNTAGSET_MASK 0xFF00 +#define RTL8367C_SVLAN_MEMBERCFG54_CTRL1_VS_SMBR_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG54_CTRL1_VS_SMBR_MASK 0xFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG54_CTRL2 0x0ca4 +#define RTL8367C_SVLAN_MEMBERCFG54_CTRL2_VS_FIDEN_OFFSET 7 +#define RTL8367C_SVLAN_MEMBERCFG54_CTRL2_VS_FIDEN_MASK 0x80 +#define RTL8367C_SVLAN_MEMBERCFG54_CTRL2_VS_SPRI_OFFSET 4 +#define RTL8367C_SVLAN_MEMBERCFG54_CTRL2_VS_SPRI_MASK 0x70 +#define RTL8367C_SVLAN_MEMBERCFG54_CTRL2_VS_FID_MSTI_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG54_CTRL2_VS_FID_MSTI_MASK 0xF + +#define RTL8367C_REG_SVLAN_MEMBERCFG54_CTRL3 0x0ca5 +#define RTL8367C_SVLAN_MEMBERCFG54_CTRL3_VS_EFID_OFFSET 13 +#define RTL8367C_SVLAN_MEMBERCFG54_CTRL3_VS_EFID_MASK 0xE000 +#define RTL8367C_SVLAN_MEMBERCFG54_CTRL3_VS_EFIDEN_OFFSET 12 +#define RTL8367C_SVLAN_MEMBERCFG54_CTRL3_VS_EFIDEN_MASK 0x1000 +#define RTL8367C_SVLAN_MEMBERCFG54_CTRL3_VS_SVID_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG54_CTRL3_VS_SVID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG55_CTRL1 0x0ca6 +#define RTL8367C_SVLAN_MEMBERCFG55_CTRL1_VS_UNTAGSET_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG55_CTRL1_VS_UNTAGSET_MASK 0xFF00 +#define RTL8367C_SVLAN_MEMBERCFG55_CTRL1_VS_SMBR_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG55_CTRL1_VS_SMBR_MASK 0xFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG55_CTRL2 0x0ca7 +#define RTL8367C_SVLAN_MEMBERCFG55_CTRL2_VS_FIDEN_OFFSET 7 +#define RTL8367C_SVLAN_MEMBERCFG55_CTRL2_VS_FIDEN_MASK 0x80 +#define RTL8367C_SVLAN_MEMBERCFG55_CTRL2_VS_SPRI_OFFSET 4 +#define RTL8367C_SVLAN_MEMBERCFG55_CTRL2_VS_SPRI_MASK 0x70 +#define RTL8367C_SVLAN_MEMBERCFG55_CTRL2_VS_FID_MSTI_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG55_CTRL2_VS_FID_MSTI_MASK 0xF + +#define RTL8367C_REG_SVLAN_MEMBERCFG55_CTRL3 0x0ca8 +#define RTL8367C_SVLAN_MEMBERCFG55_CTRL3_VS_EFID_OFFSET 13 +#define RTL8367C_SVLAN_MEMBERCFG55_CTRL3_VS_EFID_MASK 0xE000 +#define RTL8367C_SVLAN_MEMBERCFG55_CTRL3_VS_EFIDEN_OFFSET 12 +#define RTL8367C_SVLAN_MEMBERCFG55_CTRL3_VS_EFIDEN_MASK 0x1000 +#define RTL8367C_SVLAN_MEMBERCFG55_CTRL3_VS_SVID_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG55_CTRL3_VS_SVID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG56_CTRL1 0x0ca9 +#define RTL8367C_SVLAN_MEMBERCFG56_CTRL1_VS_UNTAGSET_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG56_CTRL1_VS_UNTAGSET_MASK 0xFF00 +#define RTL8367C_SVLAN_MEMBERCFG56_CTRL1_VS_SMBR_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG56_CTRL1_VS_SMBR_MASK 0xFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG56_CTRL2 0x0caa +#define RTL8367C_SVLAN_MEMBERCFG56_CTRL2_VS_FIDEN_OFFSET 7 +#define RTL8367C_SVLAN_MEMBERCFG56_CTRL2_VS_FIDEN_MASK 0x80 +#define RTL8367C_SVLAN_MEMBERCFG56_CTRL2_VS_SPRI_OFFSET 4 +#define RTL8367C_SVLAN_MEMBERCFG56_CTRL2_VS_SPRI_MASK 0x70 +#define RTL8367C_SVLAN_MEMBERCFG56_CTRL2_VS_FID_MSTI_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG56_CTRL2_VS_FID_MSTI_MASK 0xF + +#define RTL8367C_REG_SVLAN_MEMBERCFG56_CTRL3 0x0cab +#define RTL8367C_SVLAN_MEMBERCFG56_CTRL3_VS_EFID_OFFSET 13 +#define RTL8367C_SVLAN_MEMBERCFG56_CTRL3_VS_EFID_MASK 0xE000 +#define RTL8367C_SVLAN_MEMBERCFG56_CTRL3_VS_EFIDEN_OFFSET 12 +#define RTL8367C_SVLAN_MEMBERCFG56_CTRL3_VS_EFIDEN_MASK 0x1000 +#define RTL8367C_SVLAN_MEMBERCFG56_CTRL3_VS_SVID_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG56_CTRL3_VS_SVID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG57_CTRL1 0x0cac +#define RTL8367C_SVLAN_MEMBERCFG57_CTRL1_VS_UNTAGSET_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG57_CTRL1_VS_UNTAGSET_MASK 0xFF00 +#define RTL8367C_SVLAN_MEMBERCFG57_CTRL1_VS_SMBR_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG57_CTRL1_VS_SMBR_MASK 0xFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG57_CTRL2 0x0cad +#define RTL8367C_SVLAN_MEMBERCFG57_CTRL2_VS_FIDEN_OFFSET 7 +#define RTL8367C_SVLAN_MEMBERCFG57_CTRL2_VS_FIDEN_MASK 0x80 +#define RTL8367C_SVLAN_MEMBERCFG57_CTRL2_VS_SPRI_OFFSET 4 +#define RTL8367C_SVLAN_MEMBERCFG57_CTRL2_VS_SPRI_MASK 0x70 +#define RTL8367C_SVLAN_MEMBERCFG57_CTRL2_VS_FID_MSTI_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG57_CTRL2_VS_FID_MSTI_MASK 0xF + +#define RTL8367C_REG_SVLAN_MEMBERCFG57_CTRL3 0x0cae +#define RTL8367C_SVLAN_MEMBERCFG57_CTRL3_VS_EFID_OFFSET 13 +#define RTL8367C_SVLAN_MEMBERCFG57_CTRL3_VS_EFID_MASK 0xE000 +#define RTL8367C_SVLAN_MEMBERCFG57_CTRL3_VS_EFIDEN_OFFSET 12 +#define RTL8367C_SVLAN_MEMBERCFG57_CTRL3_VS_EFIDEN_MASK 0x1000 +#define RTL8367C_SVLAN_MEMBERCFG57_CTRL3_VS_SVID_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG57_CTRL3_VS_SVID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG58_CTRL1 0x0caf +#define RTL8367C_SVLAN_MEMBERCFG58_CTRL1_VS_UNTAGSET_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG58_CTRL1_VS_UNTAGSET_MASK 0xFF00 +#define RTL8367C_SVLAN_MEMBERCFG58_CTRL1_VS_SMBR_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG58_CTRL1_VS_SMBR_MASK 0xFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG58_CTRL2 0x0cb0 +#define RTL8367C_SVLAN_MEMBERCFG58_CTRL2_VS_FIDEN_OFFSET 7 +#define RTL8367C_SVLAN_MEMBERCFG58_CTRL2_VS_FIDEN_MASK 0x80 +#define RTL8367C_SVLAN_MEMBERCFG58_CTRL2_VS_SPRI_OFFSET 4 +#define RTL8367C_SVLAN_MEMBERCFG58_CTRL2_VS_SPRI_MASK 0x70 +#define RTL8367C_SVLAN_MEMBERCFG58_CTRL2_VS_FID_MSTI_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG58_CTRL2_VS_FID_MSTI_MASK 0xF + +#define RTL8367C_REG_SVLAN_MEMBERCFG58_CTRL3 0x0cb1 +#define RTL8367C_SVLAN_MEMBERCFG58_CTRL3_VS_EFID_OFFSET 13 +#define RTL8367C_SVLAN_MEMBERCFG58_CTRL3_VS_EFID_MASK 0xE000 +#define RTL8367C_SVLAN_MEMBERCFG58_CTRL3_VS_EFIDEN_OFFSET 12 +#define RTL8367C_SVLAN_MEMBERCFG58_CTRL3_VS_EFIDEN_MASK 0x1000 +#define RTL8367C_SVLAN_MEMBERCFG58_CTRL3_VS_SVID_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG58_CTRL3_VS_SVID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG59_CTRL1 0x0cb2 +#define RTL8367C_SVLAN_MEMBERCFG59_CTRL1_VS_UNTAGSET_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG59_CTRL1_VS_UNTAGSET_MASK 0xFF00 +#define RTL8367C_SVLAN_MEMBERCFG59_CTRL1_VS_SMBR_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG59_CTRL1_VS_SMBR_MASK 0xFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG59_CTRL2 0x0cb3 +#define RTL8367C_SVLAN_MEMBERCFG59_CTRL2_VS_FIDEN_OFFSET 7 +#define RTL8367C_SVLAN_MEMBERCFG59_CTRL2_VS_FIDEN_MASK 0x80 +#define RTL8367C_SVLAN_MEMBERCFG59_CTRL2_VS_SPRI_OFFSET 4 +#define RTL8367C_SVLAN_MEMBERCFG59_CTRL2_VS_SPRI_MASK 0x70 +#define RTL8367C_SVLAN_MEMBERCFG59_CTRL2_VS_FID_MSTI_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG59_CTRL2_VS_FID_MSTI_MASK 0xF + +#define RTL8367C_REG_SVLAN_MEMBERCFG59_CTRL3 0x0cb4 +#define RTL8367C_SVLAN_MEMBERCFG59_CTRL3_VS_EFID_OFFSET 13 +#define RTL8367C_SVLAN_MEMBERCFG59_CTRL3_VS_EFID_MASK 0xE000 +#define RTL8367C_SVLAN_MEMBERCFG59_CTRL3_VS_EFIDEN_OFFSET 12 +#define RTL8367C_SVLAN_MEMBERCFG59_CTRL3_VS_EFIDEN_MASK 0x1000 +#define RTL8367C_SVLAN_MEMBERCFG59_CTRL3_VS_SVID_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG59_CTRL3_VS_SVID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG60_CTRL1 0x0cb5 +#define RTL8367C_SVLAN_MEMBERCFG60_CTRL1_VS_UNTAGSET_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG60_CTRL1_VS_UNTAGSET_MASK 0xFF00 +#define RTL8367C_SVLAN_MEMBERCFG60_CTRL1_VS_SMBR_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG60_CTRL1_VS_SMBR_MASK 0xFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG60_CTRL2 0x0cb6 +#define RTL8367C_SVLAN_MEMBERCFG60_CTRL2_VS_FIDEN_OFFSET 7 +#define RTL8367C_SVLAN_MEMBERCFG60_CTRL2_VS_FIDEN_MASK 0x80 +#define RTL8367C_SVLAN_MEMBERCFG60_CTRL2_VS_SPRI_OFFSET 4 +#define RTL8367C_SVLAN_MEMBERCFG60_CTRL2_VS_SPRI_MASK 0x70 +#define RTL8367C_SVLAN_MEMBERCFG60_CTRL2_VS_FID_MSTI_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG60_CTRL2_VS_FID_MSTI_MASK 0xF + +#define RTL8367C_REG_SVLAN_MEMBERCFG60_CTRL3 0x0cb7 +#define RTL8367C_SVLAN_MEMBERCFG60_CTRL3_VS_EFID_OFFSET 13 +#define RTL8367C_SVLAN_MEMBERCFG60_CTRL3_VS_EFID_MASK 0xE000 +#define RTL8367C_SVLAN_MEMBERCFG60_CTRL3_VS_EFIDEN_OFFSET 12 +#define RTL8367C_SVLAN_MEMBERCFG60_CTRL3_VS_EFIDEN_MASK 0x1000 +#define RTL8367C_SVLAN_MEMBERCFG60_CTRL3_VS_SVID_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG60_CTRL3_VS_SVID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG61_CTRL1 0x0cb8 +#define RTL8367C_SVLAN_MEMBERCFG61_CTRL1_VS_UNTAGSET_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG61_CTRL1_VS_UNTAGSET_MASK 0xFF00 +#define RTL8367C_SVLAN_MEMBERCFG61_CTRL1_VS_SMBR_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG61_CTRL1_VS_SMBR_MASK 0xFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG61_CTRL2 0x0cb9 +#define RTL8367C_SVLAN_MEMBERCFG61_CTRL2_VS_FIDEN_OFFSET 7 +#define RTL8367C_SVLAN_MEMBERCFG61_CTRL2_VS_FIDEN_MASK 0x80 +#define RTL8367C_SVLAN_MEMBERCFG61_CTRL2_VS_SPRI_OFFSET 4 +#define RTL8367C_SVLAN_MEMBERCFG61_CTRL2_VS_SPRI_MASK 0x70 +#define RTL8367C_SVLAN_MEMBERCFG61_CTRL2_VS_FID_MSTI_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG61_CTRL2_VS_FID_MSTI_MASK 0xF + +#define RTL8367C_REG_SVLAN_MEMBERCFG61_CTRL3 0x0cba +#define RTL8367C_SVLAN_MEMBERCFG61_CTRL3_VS_EFID_OFFSET 13 +#define RTL8367C_SVLAN_MEMBERCFG61_CTRL3_VS_EFID_MASK 0xE000 +#define RTL8367C_SVLAN_MEMBERCFG61_CTRL3_VS_EFIDEN_OFFSET 12 +#define RTL8367C_SVLAN_MEMBERCFG61_CTRL3_VS_EFIDEN_MASK 0x1000 +#define RTL8367C_SVLAN_MEMBERCFG61_CTRL3_VS_SVID_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG61_CTRL3_VS_SVID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG62_CTRL1 0x0cbb +#define RTL8367C_SVLAN_MEMBERCFG62_CTRL1_VS_UNTAGSET_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG62_CTRL1_VS_UNTAGSET_MASK 0xFF00 +#define RTL8367C_SVLAN_MEMBERCFG62_CTRL1_VS_SMBR_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG62_CTRL1_VS_SMBR_MASK 0xFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG62_CTRL2 0x0cbc +#define RTL8367C_SVLAN_MEMBERCFG62_CTRL2_VS_FIDEN_OFFSET 7 +#define RTL8367C_SVLAN_MEMBERCFG62_CTRL2_VS_FIDEN_MASK 0x80 +#define RTL8367C_SVLAN_MEMBERCFG62_CTRL2_VS_SPRI_OFFSET 4 +#define RTL8367C_SVLAN_MEMBERCFG62_CTRL2_VS_SPRI_MASK 0x70 +#define RTL8367C_SVLAN_MEMBERCFG62_CTRL2_VS_FID_MSTI_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG62_CTRL2_VS_FID_MSTI_MASK 0xF + +#define RTL8367C_REG_SVLAN_MEMBERCFG62_CTRL3 0x0cbd +#define RTL8367C_SVLAN_MEMBERCFG62_CTRL3_VS_EFID_OFFSET 13 +#define RTL8367C_SVLAN_MEMBERCFG62_CTRL3_VS_EFID_MASK 0xE000 +#define RTL8367C_SVLAN_MEMBERCFG62_CTRL3_VS_EFIDEN_OFFSET 12 +#define RTL8367C_SVLAN_MEMBERCFG62_CTRL3_VS_EFIDEN_MASK 0x1000 +#define RTL8367C_SVLAN_MEMBERCFG62_CTRL3_VS_SVID_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG62_CTRL3_VS_SVID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG63_CTRL1 0x0cbe +#define RTL8367C_SVLAN_MEMBERCFG63_CTRL1_VS_UNTAGSET_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG63_CTRL1_VS_UNTAGSET_MASK 0xFF00 +#define RTL8367C_SVLAN_MEMBERCFG63_CTRL1_VS_SMBR_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG63_CTRL1_VS_SMBR_MASK 0xFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG63_CTRL2 0x0cbf +#define RTL8367C_SVLAN_MEMBERCFG63_CTRL2_VS_FIDEN_OFFSET 7 +#define RTL8367C_SVLAN_MEMBERCFG63_CTRL2_VS_FIDEN_MASK 0x80 +#define RTL8367C_SVLAN_MEMBERCFG63_CTRL2_VS_SPRI_OFFSET 4 +#define RTL8367C_SVLAN_MEMBERCFG63_CTRL2_VS_SPRI_MASK 0x70 +#define RTL8367C_SVLAN_MEMBERCFG63_CTRL2_VS_FID_MSTI_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG63_CTRL2_VS_FID_MSTI_MASK 0xF + +#define RTL8367C_REG_SVLAN_MEMBERCFG63_CTRL3 0x0cc0 +#define RTL8367C_SVLAN_MEMBERCFG63_CTRL3_VS_EFID_OFFSET 13 +#define RTL8367C_SVLAN_MEMBERCFG63_CTRL3_VS_EFID_MASK 0xE000 +#define RTL8367C_SVLAN_MEMBERCFG63_CTRL3_VS_EFIDEN_OFFSET 12 +#define RTL8367C_SVLAN_MEMBERCFG63_CTRL3_VS_EFIDEN_MASK 0x1000 +#define RTL8367C_SVLAN_MEMBERCFG63_CTRL3_VS_SVID_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG63_CTRL3_VS_SVID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_MEMBERCFG0_CTRL4 0x0cc1 +#define RTL8367C_SVLAN_MEMBERCFG0_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG0_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 +#define RTL8367C_SVLAN_MEMBERCFG0_CTRL4_VS_SMBR_EXT_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG0_CTRL4_VS_SMBR_EXT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_MEMBERCFG1_CTRL4 0x0cc2 +#define RTL8367C_SVLAN_MEMBERCFG1_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG1_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 +#define RTL8367C_SVLAN_MEMBERCFG1_CTRL4_VS_SMBR_EXT_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG1_CTRL4_VS_SMBR_EXT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_MEMBERCFG2_CTRL4 0x0cc3 +#define RTL8367C_SVLAN_MEMBERCFG2_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG2_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 +#define RTL8367C_SVLAN_MEMBERCFG2_CTRL4_VS_SMBR_EXT_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG2_CTRL4_VS_SMBR_EXT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_MEMBERCFG3_CTRL4 0x0cc4 +#define RTL8367C_SVLAN_MEMBERCFG3_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG3_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 +#define RTL8367C_SVLAN_MEMBERCFG3_CTRL4_VS_SMBR_EXT_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG3_CTRL4_VS_SMBR_EXT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_MEMBERCFG4_CTRL4 0x0cc5 +#define RTL8367C_SVLAN_MEMBERCFG4_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG4_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 +#define RTL8367C_SVLAN_MEMBERCFG4_CTRL4_VS_SMBR_EXT_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG4_CTRL4_VS_SMBR_EXT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_MEMBERCFG5_CTRL4 0x0cc6 +#define RTL8367C_SVLAN_MEMBERCFG5_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG5_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 +#define RTL8367C_SVLAN_MEMBERCFG5_CTRL4_VS_SMBR_EXT_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG5_CTRL4_VS_SMBR_EXT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_MEMBERCFG6_CTRL4 0x0cc7 +#define RTL8367C_SVLAN_MEMBERCFG6_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG6_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 +#define RTL8367C_SVLAN_MEMBERCFG6_CTRL4_VS_SMBR_EXT_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG6_CTRL4_VS_SMBR_EXT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_MEMBERCFG7_CTRL4 0x0cc8 +#define RTL8367C_SVLAN_MEMBERCFG7_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG7_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 +#define RTL8367C_SVLAN_MEMBERCFG7_CTRL4_VS_SMBR_EXT_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG7_CTRL4_VS_SMBR_EXT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_MEMBERCFG8_CTRL4 0x0cc9 +#define RTL8367C_SVLAN_MEMBERCFG8_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG8_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 +#define RTL8367C_SVLAN_MEMBERCFG8_CTRL4_VS_SMBR_EXT_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG8_CTRL4_VS_SMBR_EXT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_MEMBERCFG9_CTRL4 0x0cca +#define RTL8367C_SVLAN_MEMBERCFG9_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG9_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 +#define RTL8367C_SVLAN_MEMBERCFG9_CTRL4_VS_SMBR_EXT_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG9_CTRL4_VS_SMBR_EXT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_MEMBERCFG10_CTRL4 0x0ccb +#define RTL8367C_SVLAN_MEMBERCFG10_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG10_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 +#define RTL8367C_SVLAN_MEMBERCFG10_CTRL4_VS_SMBR_EXT_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG10_CTRL4_VS_SMBR_EXT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_MEMBERCFG11_CTRL4 0x0ccc +#define RTL8367C_SVLAN_MEMBERCFG11_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG11_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 +#define RTL8367C_SVLAN_MEMBERCFG11_CTRL4_VS_SMBR_EXT_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG11_CTRL4_VS_SMBR_EXT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_MEMBERCFG12_CTRL4 0x0ccd +#define RTL8367C_SVLAN_MEMBERCFG12_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG12_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 +#define RTL8367C_SVLAN_MEMBERCFG12_CTRL4_VS_SMBR_EXT_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG12_CTRL4_VS_SMBR_EXT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_MEMBERCFG13_CTRL4 0x0cce +#define RTL8367C_SVLAN_MEMBERCFG13_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG13_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 +#define RTL8367C_SVLAN_MEMBERCFG13_CTRL4_VS_SMBR_EXT_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG13_CTRL4_VS_SMBR_EXT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_MEMBERCFG14_CTRL4 0x0ccf +#define RTL8367C_SVLAN_MEMBERCFG14_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG14_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 +#define RTL8367C_SVLAN_MEMBERCFG14_CTRL4_VS_SMBR_EXT_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG14_CTRL4_VS_SMBR_EXT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_MEMBERCFG15_CTRL4 0x0cd0 +#define RTL8367C_SVLAN_MEMBERCFG15_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG15_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 +#define RTL8367C_SVLAN_MEMBERCFG15_CTRL4_VS_SMBR_EXT_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG15_CTRL4_VS_SMBR_EXT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_MEMBERCFG16_CTRL4 0x0cd1 +#define RTL8367C_SVLAN_MEMBERCFG16_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG16_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 +#define RTL8367C_SVLAN_MEMBERCFG16_CTRL4_VS_SMBR_EXT_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG16_CTRL4_VS_SMBR_EXT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_MEMBERCFG17_CTRL4 0x0cd2 +#define RTL8367C_SVLAN_MEMBERCFG17_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG17_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 +#define RTL8367C_SVLAN_MEMBERCFG17_CTRL4_VS_SMBR_EXT_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG17_CTRL4_VS_SMBR_EXT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_MEMBERCFG18_CTRL4 0x0cd3 +#define RTL8367C_SVLAN_MEMBERCFG18_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG18_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 +#define RTL8367C_SVLAN_MEMBERCFG18_CTRL4_VS_SMBR_EXT_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG18_CTRL4_VS_SMBR_EXT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_MEMBERCFG19_CTRL4 0x0cd4 +#define RTL8367C_SVLAN_MEMBERCFG19_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG19_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 +#define RTL8367C_SVLAN_MEMBERCFG19_CTRL4_VS_SMBR_EXT_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG19_CTRL4_VS_SMBR_EXT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_MEMBERCFG20_CTRL4 0x0cd5 +#define RTL8367C_SVLAN_MEMBERCFG20_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG20_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 +#define RTL8367C_SVLAN_MEMBERCFG20_CTRL4_VS_SMBR_EXT_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG20_CTRL4_VS_SMBR_EXT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_MEMBERCFG21_CTRL4 0x0cd6 +#define RTL8367C_SVLAN_MEMBERCFG21_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG21_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 +#define RTL8367C_SVLAN_MEMBERCFG21_CTRL4_VS_SMBR_EXT_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG21_CTRL4_VS_SMBR_EXT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_MEMBERCFG22_CTRL4 0x0cd7 +#define RTL8367C_SVLAN_MEMBERCFG22_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG22_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 +#define RTL8367C_SVLAN_MEMBERCFG22_CTRL4_VS_SMBR_EXT_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG22_CTRL4_VS_SMBR_EXT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_MEMBERCFG23_CTRL4 0x0cd8 +#define RTL8367C_SVLAN_MEMBERCFG23_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG23_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 +#define RTL8367C_SVLAN_MEMBERCFG23_CTRL4_VS_SMBR_EXT_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG23_CTRL4_VS_SMBR_EXT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_MEMBERCFG24_CTRL4 0x0cd9 +#define RTL8367C_SVLAN_MEMBERCFG24_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG24_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 +#define RTL8367C_SVLAN_MEMBERCFG24_CTRL4_VS_SMBR_EXT_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG24_CTRL4_VS_SMBR_EXT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_MEMBERCFG25_CTRL4 0x0cda +#define RTL8367C_SVLAN_MEMBERCFG25_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG25_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 +#define RTL8367C_SVLAN_MEMBERCFG25_CTRL4_VS_SMBR_EXT_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG25_CTRL4_VS_SMBR_EXT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_MEMBERCFG26_CTRL4 0x0cdb +#define RTL8367C_SVLAN_MEMBERCFG26_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG26_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 +#define RTL8367C_SVLAN_MEMBERCFG26_CTRL4_VS_SMBR_EXT_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG26_CTRL4_VS_SMBR_EXT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_MEMBERCFG27_CTRL4 0x0cdc +#define RTL8367C_SVLAN_MEMBERCFG27_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG27_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 +#define RTL8367C_SVLAN_MEMBERCFG27_CTRL4_VS_SMBR_EXT_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG27_CTRL4_VS_SMBR_EXT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_MEMBERCFG28_CTRL4 0x0cdd +#define RTL8367C_SVLAN_MEMBERCFG28_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG28_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 +#define RTL8367C_SVLAN_MEMBERCFG28_CTRL4_VS_SMBR_EXT_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG28_CTRL4_VS_SMBR_EXT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_MEMBERCFG29_CTRL4 0x0cde +#define RTL8367C_SVLAN_MEMBERCFG29_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG29_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 +#define RTL8367C_SVLAN_MEMBERCFG29_CTRL4_VS_SMBR_EXT_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG29_CTRL4_VS_SMBR_EXT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_MEMBERCFG30_CTRL4 0x0cdf +#define RTL8367C_SVLAN_MEMBERCFG30_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG30_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 +#define RTL8367C_SVLAN_MEMBERCFG30_CTRL4_VS_SMBR_EXT_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG30_CTRL4_VS_SMBR_EXT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_MEMBERCFG31_CTRL4 0x0ce0 +#define RTL8367C_SVLAN_MEMBERCFG31_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG31_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 +#define RTL8367C_SVLAN_MEMBERCFG31_CTRL4_VS_SMBR_EXT_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG31_CTRL4_VS_SMBR_EXT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_MEMBERCFG32_CTRL4 0x0ce1 +#define RTL8367C_SVLAN_MEMBERCFG32_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG32_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 +#define RTL8367C_SVLAN_MEMBERCFG32_CTRL4_VS_SMBR_EXT_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG32_CTRL4_VS_SMBR_EXT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_MEMBERCFG33_CTRL4 0x0ce2 +#define RTL8367C_SVLAN_MEMBERCFG33_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG33_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 +#define RTL8367C_SVLAN_MEMBERCFG33_CTRL4_VS_SMBR_EXT_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG33_CTRL4_VS_SMBR_EXT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_MEMBERCFG34_CTRL4 0x0ce3 +#define RTL8367C_SVLAN_MEMBERCFG34_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG34_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 +#define RTL8367C_SVLAN_MEMBERCFG34_CTRL4_VS_SMBR_EXT_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG34_CTRL4_VS_SMBR_EXT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_MEMBERCFG35_CTRL4 0x0ce4 +#define RTL8367C_SVLAN_MEMBERCFG35_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG35_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 +#define RTL8367C_SVLAN_MEMBERCFG35_CTRL4_VS_SMBR_EXT_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG35_CTRL4_VS_SMBR_EXT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_MEMBERCFG36_CTRL4 0x0ce5 +#define RTL8367C_SVLAN_MEMBERCFG36_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG36_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 +#define RTL8367C_SVLAN_MEMBERCFG36_CTRL4_VS_SMBR_EXT_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG36_CTRL4_VS_SMBR_EXT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_MEMBERCFG37_CTRL4 0x0ce6 +#define RTL8367C_SVLAN_MEMBERCFG37_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG37_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 +#define RTL8367C_SVLAN_MEMBERCFG37_CTRL4_VS_SMBR_EXT_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG37_CTRL4_VS_SMBR_EXT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_MEMBERCFG38_CTRL4 0x0ce7 +#define RTL8367C_SVLAN_MEMBERCFG38_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG38_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 +#define RTL8367C_SVLAN_MEMBERCFG38_CTRL4_VS_SMBR_EXT_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG38_CTRL4_VS_SMBR_EXT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_MEMBERCFG39_CTRL4 0x0ce8 +#define RTL8367C_SVLAN_MEMBERCFG39_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG39_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 +#define RTL8367C_SVLAN_MEMBERCFG39_CTRL4_VS_SMBR_EXT_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG39_CTRL4_VS_SMBR_EXT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_MEMBERCFG40_CTRL4 0x0ce9 +#define RTL8367C_SVLAN_MEMBERCFG40_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG40_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 +#define RTL8367C_SVLAN_MEMBERCFG40_CTRL4_VS_SMBR_EXT_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG40_CTRL4_VS_SMBR_EXT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_MEMBERCFG41_CTRL4 0x0cea +#define RTL8367C_SVLAN_MEMBERCFG41_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG41_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 +#define RTL8367C_SVLAN_MEMBERCFG41_CTRL4_VS_SMBR_EXT_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG41_CTRL4_VS_SMBR_EXT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_MEMBERCFG42_CTRL4 0x0ceb +#define RTL8367C_SVLAN_MEMBERCFG42_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG42_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 +#define RTL8367C_SVLAN_MEMBERCFG42_CTRL4_VS_SMBR_EXT_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG42_CTRL4_VS_SMBR_EXT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_MEMBERCFG43_CTRL4 0x0cec +#define RTL8367C_SVLAN_MEMBERCFG43_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG43_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 +#define RTL8367C_SVLAN_MEMBERCFG43_CTRL4_VS_SMBR_EXT_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG43_CTRL4_VS_SMBR_EXT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_MEMBERCFG44_CTRL4 0x0ced +#define RTL8367C_SVLAN_MEMBERCFG44_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG44_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 +#define RTL8367C_SVLAN_MEMBERCFG44_CTRL4_VS_SMBR_EXT_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG44_CTRL4_VS_SMBR_EXT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_MEMBERCFG45_CTRL4 0x0cee +#define RTL8367C_SVLAN_MEMBERCFG45_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG45_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 +#define RTL8367C_SVLAN_MEMBERCFG45_CTRL4_VS_SMBR_EXT_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG45_CTRL4_VS_SMBR_EXT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_MEMBERCFG46_CTRL4 0x0cef +#define RTL8367C_SVLAN_MEMBERCFG46_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG46_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 +#define RTL8367C_SVLAN_MEMBERCFG46_CTRL4_VS_SMBR_EXT_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG46_CTRL4_VS_SMBR_EXT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_MEMBERCFG47_CTRL4 0x0cf0 +#define RTL8367C_SVLAN_MEMBERCFG47_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG47_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 +#define RTL8367C_SVLAN_MEMBERCFG47_CTRL4_VS_SMBR_EXT_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG47_CTRL4_VS_SMBR_EXT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_MEMBERCFG48_CTRL4 0x0cf1 +#define RTL8367C_SVLAN_MEMBERCFG48_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG48_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 +#define RTL8367C_SVLAN_MEMBERCFG48_CTRL4_VS_SMBR_EXT_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG48_CTRL4_VS_SMBR_EXT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_MEMBERCFG49_CTRL4 0x0cf2 +#define RTL8367C_SVLAN_MEMBERCFG49_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG49_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 +#define RTL8367C_SVLAN_MEMBERCFG49_CTRL4_VS_SMBR_EXT_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG49_CTRL4_VS_SMBR_EXT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_MEMBERCFG50_CTRL4 0x0cf3 +#define RTL8367C_SVLAN_MEMBERCFG50_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG50_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 +#define RTL8367C_SVLAN_MEMBERCFG50_CTRL4_VS_SMBR_EXT_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG50_CTRL4_VS_SMBR_EXT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_MEMBERCFG51_CTRL4 0x0cf4 +#define RTL8367C_SVLAN_MEMBERCFG51_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG51_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 +#define RTL8367C_SVLAN_MEMBERCFG51_CTRL4_VS_SMBR_EXT_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG51_CTRL4_VS_SMBR_EXT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_MEMBERCFG52_CTRL4 0x0cf5 +#define RTL8367C_SVLAN_MEMBERCFG52_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG52_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 +#define RTL8367C_SVLAN_MEMBERCFG52_CTRL4_VS_SMBR_EXT_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG52_CTRL4_VS_SMBR_EXT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_MEMBERCFG53_CTRL4 0x0cf6 +#define RTL8367C_SVLAN_MEMBERCFG53_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG53_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 +#define RTL8367C_SVLAN_MEMBERCFG53_CTRL4_VS_SMBR_EXT_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG53_CTRL4_VS_SMBR_EXT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_MEMBERCFG54_CTRL4 0x0cf7 +#define RTL8367C_SVLAN_MEMBERCFG54_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG54_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 +#define RTL8367C_SVLAN_MEMBERCFG54_CTRL4_VS_SMBR_EXT_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG54_CTRL4_VS_SMBR_EXT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_MEMBERCFG55_CTRL4 0x0cf8 +#define RTL8367C_SVLAN_MEMBERCFG55_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG55_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 +#define RTL8367C_SVLAN_MEMBERCFG55_CTRL4_VS_SMBR_EXT_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG55_CTRL4_VS_SMBR_EXT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_MEMBERCFG56_CTRL4 0x0cf9 +#define RTL8367C_SVLAN_MEMBERCFG56_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG56_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 +#define RTL8367C_SVLAN_MEMBERCFG56_CTRL4_VS_SMBR_EXT_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG56_CTRL4_VS_SMBR_EXT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_MEMBERCFG57_CTRL4 0x0cfa +#define RTL8367C_SVLAN_MEMBERCFG57_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG57_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 +#define RTL8367C_SVLAN_MEMBERCFG57_CTRL4_VS_SMBR_EXT_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG57_CTRL4_VS_SMBR_EXT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_MEMBERCFG58_CTRL4 0x0cfb +#define RTL8367C_SVLAN_MEMBERCFG58_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG58_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 +#define RTL8367C_SVLAN_MEMBERCFG58_CTRL4_VS_SMBR_EXT_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG58_CTRL4_VS_SMBR_EXT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_MEMBERCFG59_CTRL4 0x0cfc +#define RTL8367C_SVLAN_MEMBERCFG59_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG59_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 +#define RTL8367C_SVLAN_MEMBERCFG59_CTRL4_VS_SMBR_EXT_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG59_CTRL4_VS_SMBR_EXT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_MEMBERCFG60_CTRL4 0x0cfd +#define RTL8367C_SVLAN_MEMBERCFG60_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG60_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 +#define RTL8367C_SVLAN_MEMBERCFG60_CTRL4_VS_SMBR_EXT_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG60_CTRL4_VS_SMBR_EXT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_MEMBERCFG61_CTRL4 0x0cfe +#define RTL8367C_SVLAN_MEMBERCFG61_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG61_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 +#define RTL8367C_SVLAN_MEMBERCFG61_CTRL4_VS_SMBR_EXT_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG61_CTRL4_VS_SMBR_EXT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_MEMBERCFG62_CTRL4 0x0cff +#define RTL8367C_SVLAN_MEMBERCFG62_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG62_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 +#define RTL8367C_SVLAN_MEMBERCFG62_CTRL4_VS_SMBR_EXT_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG62_CTRL4_VS_SMBR_EXT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_C2SCFG0_CTRL0 0x0d00 +#define RTL8367C_SVLAN_C2SCFG0_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG0_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG0_CTRL1 0x0d01 +#define RTL8367C_SVLAN_C2SCFG0_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG0_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG0_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG0_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG0_CTRL2 0x0d02 +#define RTL8367C_SVLAN_C2SCFG0_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG0_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG1_CTRL0 0x0d03 +#define RTL8367C_SVLAN_C2SCFG1_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG1_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG1_CTRL1 0x0d04 +#define RTL8367C_SVLAN_C2SCFG1_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG1_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG1_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG1_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG1_CTRL2 0x0d05 +#define RTL8367C_SVLAN_C2SCFG1_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG1_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG2_CTRL0 0x0d06 +#define RTL8367C_SVLAN_C2SCFG2_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG2_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG2_CTRL1 0x0d07 +#define RTL8367C_SVLAN_C2SCFG2_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG2_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG2_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG2_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG2_CTRL2 0x0d08 +#define RTL8367C_SVLAN_C2SCFG2_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG2_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG3_CTRL0 0x0d09 +#define RTL8367C_SVLAN_C2SCFG3_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG3_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG3_CTRL1 0x0d0a +#define RTL8367C_SVLAN_C2SCFG3_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG3_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG3_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG3_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG3_CTRL2 0x0d0b +#define RTL8367C_SVLAN_C2SCFG3_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG3_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG4_CTRL0 0x0d0c +#define RTL8367C_SVLAN_C2SCFG4_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG4_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG4_CTRL1 0x0d0d +#define RTL8367C_SVLAN_C2SCFG4_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG4_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG4_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG4_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG4_CTRL2 0x0d0e +#define RTL8367C_SVLAN_C2SCFG4_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG4_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG5_CTRL0 0x0d0f +#define RTL8367C_SVLAN_C2SCFG5_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG5_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG5_CTRL1 0x0d10 +#define RTL8367C_SVLAN_C2SCFG5_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG5_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG5_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG5_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG5_CTRL2 0x0d11 +#define RTL8367C_SVLAN_C2SCFG5_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG5_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG6_CTRL0 0x0d12 +#define RTL8367C_SVLAN_C2SCFG6_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG6_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG6_CTRL1 0x0d13 +#define RTL8367C_SVLAN_C2SCFG6_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG6_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG6_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG6_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG6_CTRL2 0x0d14 +#define RTL8367C_SVLAN_C2SCFG6_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG6_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG7_CTRL0 0x0d15 +#define RTL8367C_SVLAN_C2SCFG7_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG7_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG7_CTRL1 0x0d16 +#define RTL8367C_SVLAN_C2SCFG7_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG7_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG7_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG7_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG7_CTRL2 0x0d17 +#define RTL8367C_SVLAN_C2SCFG7_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG7_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG8_CTRL0 0x0d18 +#define RTL8367C_SVLAN_C2SCFG8_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG8_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG8_CTRL1 0x0d19 +#define RTL8367C_SVLAN_C2SCFG8_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG8_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG8_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG8_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG8_CTRL2 0x0d1a +#define RTL8367C_SVLAN_C2SCFG8_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG8_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG9_CTRL0 0x0d1b +#define RTL8367C_SVLAN_C2SCFG9_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG9_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG9_CTRL1 0x0d1c +#define RTL8367C_SVLAN_C2SCFG9_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG9_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG9_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG9_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG9_CTRL2 0x0d1d +#define RTL8367C_SVLAN_C2SCFG9_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG9_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG10_CTRL0 0x0d1e +#define RTL8367C_SVLAN_C2SCFG10_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG10_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG10_CTRL1 0x0d1f +#define RTL8367C_SVLAN_C2SCFG10_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG10_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG10_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG10_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG10_CTRL2 0x0d20 +#define RTL8367C_SVLAN_C2SCFG10_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG10_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG11_CTRL0 0x0d21 +#define RTL8367C_SVLAN_C2SCFG11_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG11_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG11_CTRL1 0x0d22 +#define RTL8367C_SVLAN_C2SCFG11_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG11_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG11_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG11_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG11_CTRL2 0x0d23 +#define RTL8367C_SVLAN_C2SCFG11_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG11_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG12_CTRL0 0x0d24 +#define RTL8367C_SVLAN_C2SCFG12_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG12_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG12_CTRL1 0x0d25 +#define RTL8367C_SVLAN_C2SCFG12_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG12_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG12_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG12_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG12_CTRL2 0x0d26 +#define RTL8367C_SVLAN_C2SCFG12_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG12_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG13_CTRL0 0x0d27 +#define RTL8367C_SVLAN_C2SCFG13_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG13_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG13_CTRL1 0x0d28 +#define RTL8367C_SVLAN_C2SCFG13_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG13_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG13_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG13_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG13_CTRL2 0x0d29 +#define RTL8367C_SVLAN_C2SCFG13_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG13_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG14_CTRL0 0x0d2a +#define RTL8367C_SVLAN_C2SCFG14_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG14_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG14_CTRL1 0x0d2b +#define RTL8367C_SVLAN_C2SCFG14_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG14_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG14_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG14_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG14_CTRL2 0x0d2c +#define RTL8367C_SVLAN_C2SCFG14_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG14_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG15_CTRL0 0x0d2d +#define RTL8367C_SVLAN_C2SCFG15_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG15_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG15_CTRL1 0x0d2e +#define RTL8367C_SVLAN_C2SCFG15_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG15_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG15_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG15_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG15_CTRL2 0x0d2f +#define RTL8367C_SVLAN_C2SCFG15_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG15_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG16_CTRL0 0x0d30 +#define RTL8367C_SVLAN_C2SCFG16_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG16_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG16_CTRL1 0x0d31 +#define RTL8367C_SVLAN_C2SCFG16_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG16_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG16_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG16_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG16_CTRL2 0x0d32 +#define RTL8367C_SVLAN_C2SCFG16_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG16_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG17_CTRL0 0x0d33 +#define RTL8367C_SVLAN_C2SCFG17_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG17_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG17_CTRL1 0x0d34 +#define RTL8367C_SVLAN_C2SCFG17_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG17_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG17_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG17_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG17_CTRL2 0x0d35 +#define RTL8367C_SVLAN_C2SCFG17_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG17_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG18_CTRL0 0x0d36 +#define RTL8367C_SVLAN_C2SCFG18_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG18_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG18_CTRL1 0x0d37 +#define RTL8367C_SVLAN_C2SCFG18_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG18_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG18_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG18_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG18_CTRL2 0x0d38 +#define RTL8367C_SVLAN_C2SCFG18_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG18_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG19_CTRL0 0x0d39 +#define RTL8367C_SVLAN_C2SCFG19_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG19_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG19_CTRL1 0x0d3a +#define RTL8367C_SVLAN_C2SCFG19_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG19_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG19_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG19_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG19_CTRL2 0x0d3b +#define RTL8367C_SVLAN_C2SCFG19_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG19_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG20_CTRL0 0x0d3c +#define RTL8367C_SVLAN_C2SCFG20_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG20_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG20_CTRL1 0x0d3d +#define RTL8367C_SVLAN_C2SCFG20_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG20_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG20_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG20_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG20_CTRL2 0x0d3e +#define RTL8367C_SVLAN_C2SCFG20_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG20_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG21_CTRL0 0x0d3f +#define RTL8367C_SVLAN_C2SCFG21_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG21_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG21_CTRL1 0x0d40 +#define RTL8367C_SVLAN_C2SCFG21_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG21_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG21_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG21_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG21_CTRL2 0x0d41 +#define RTL8367C_SVLAN_C2SCFG21_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG21_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG22_CTRL0 0x0d42 +#define RTL8367C_SVLAN_C2SCFG22_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG22_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG22_CTRL1 0x0d43 +#define RTL8367C_SVLAN_C2SCFG22_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG22_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG22_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG22_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG22_CTRL2 0x0d44 +#define RTL8367C_SVLAN_C2SCFG22_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG22_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG23_CTRL0 0x0d45 +#define RTL8367C_SVLAN_C2SCFG23_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG23_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG23_CTRL1 0x0d46 +#define RTL8367C_SVLAN_C2SCFG23_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG23_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG23_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG23_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG23_CTRL2 0x0d47 +#define RTL8367C_SVLAN_C2SCFG23_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG23_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG24_CTRL0 0x0d48 +#define RTL8367C_SVLAN_C2SCFG24_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG24_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG24_CTRL1 0x0d49 +#define RTL8367C_SVLAN_C2SCFG24_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG24_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG24_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG24_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG24_CTRL2 0x0d4a +#define RTL8367C_SVLAN_C2SCFG24_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG24_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG25_CTRL0 0x0d4b +#define RTL8367C_SVLAN_C2SCFG25_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG25_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG25_CTRL1 0x0d4c +#define RTL8367C_SVLAN_C2SCFG25_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG25_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG25_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG25_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG25_CTRL2 0x0d4d +#define RTL8367C_SVLAN_C2SCFG25_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG25_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG26_CTRL0 0x0d4e +#define RTL8367C_SVLAN_C2SCFG26_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG26_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG26_CTRL1 0x0d4f +#define RTL8367C_SVLAN_C2SCFG26_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG26_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG26_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG26_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG26_CTRL2 0x0d50 +#define RTL8367C_SVLAN_C2SCFG26_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG26_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG27_CTRL0 0x0d51 +#define RTL8367C_SVLAN_C2SCFG27_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG27_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG27_CTRL1 0x0d52 +#define RTL8367C_SVLAN_C2SCFG27_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG27_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG27_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG27_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG27_CTRL2 0x0d53 +#define RTL8367C_SVLAN_C2SCFG27_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG27_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG28_CTRL0 0x0d54 +#define RTL8367C_SVLAN_C2SCFG28_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG28_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG28_CTRL1 0x0d55 +#define RTL8367C_SVLAN_C2SCFG28_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG28_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG28_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG28_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG28_CTRL2 0x0d56 +#define RTL8367C_SVLAN_C2SCFG28_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG28_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG29_CTRL0 0x0d57 +#define RTL8367C_SVLAN_C2SCFG29_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG29_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG29_CTRL1 0x0d58 +#define RTL8367C_SVLAN_C2SCFG29_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG29_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG29_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG29_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG29_CTRL2 0x0d59 +#define RTL8367C_SVLAN_C2SCFG29_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG29_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG30_CTRL0 0x0d5a +#define RTL8367C_SVLAN_C2SCFG30_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG30_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG30_CTRL1 0x0d5b +#define RTL8367C_SVLAN_C2SCFG30_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG30_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG30_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG30_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG30_CTRL2 0x0d5c +#define RTL8367C_SVLAN_C2SCFG30_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG30_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG31_CTRL0 0x0d5d +#define RTL8367C_SVLAN_C2SCFG31_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG31_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG31_CTRL1 0x0d5e +#define RTL8367C_SVLAN_C2SCFG31_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG31_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG31_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG31_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG31_CTRL2 0x0d5f +#define RTL8367C_SVLAN_C2SCFG31_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG31_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG32_CTRL0 0x0d60 +#define RTL8367C_SVLAN_C2SCFG32_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG32_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG32_CTRL1 0x0d61 +#define RTL8367C_SVLAN_C2SCFG32_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG32_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG32_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG32_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG32_CTRL2 0x0d62 +#define RTL8367C_SVLAN_C2SCFG32_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG32_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG33_CTRL0 0x0d63 +#define RTL8367C_SVLAN_C2SCFG33_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG33_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG33_CTRL1 0x0d64 +#define RTL8367C_SVLAN_C2SCFG33_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG33_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG33_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG33_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG33_CTRL2 0x0d65 +#define RTL8367C_SVLAN_C2SCFG33_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG33_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG34_CTRL0 0x0d66 +#define RTL8367C_SVLAN_C2SCFG34_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG34_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG34_CTRL1 0x0d67 +#define RTL8367C_SVLAN_C2SCFG34_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG34_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG34_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG34_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG34_CTRL2 0x0d68 +#define RTL8367C_SVLAN_C2SCFG34_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG34_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG35_CTRL0 0x0d69 +#define RTL8367C_SVLAN_C2SCFG35_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG35_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG35_CTRL1 0x0d6a +#define RTL8367C_SVLAN_C2SCFG35_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG35_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG35_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG35_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG35_CTRL2 0x0d6b +#define RTL8367C_SVLAN_C2SCFG35_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG35_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG36_CTRL0 0x0d6c +#define RTL8367C_SVLAN_C2SCFG36_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG36_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG36_CTRL1 0x0d6d +#define RTL8367C_SVLAN_C2SCFG36_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG36_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG36_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG36_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG36_CTRL2 0x0d6e +#define RTL8367C_SVLAN_C2SCFG36_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG36_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG37_CTRL0 0x0d6f +#define RTL8367C_SVLAN_C2SCFG37_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG37_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG37_CTRL1 0x0d70 +#define RTL8367C_SVLAN_C2SCFG37_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG37_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG37_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG37_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG37_CTRL2 0x0d71 +#define RTL8367C_SVLAN_C2SCFG37_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG37_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG38_CTRL0 0x0d72 +#define RTL8367C_SVLAN_C2SCFG38_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG38_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG38_CTRL1 0x0d73 +#define RTL8367C_SVLAN_C2SCFG38_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG38_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG38_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG38_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG38_CTRL2 0x0d74 +#define RTL8367C_SVLAN_C2SCFG38_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG38_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG39_CTRL0 0x0d75 +#define RTL8367C_SVLAN_C2SCFG39_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG39_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG39_CTRL1 0x0d76 +#define RTL8367C_SVLAN_C2SCFG39_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG39_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG39_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG39_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG39_CTRL2 0x0d77 +#define RTL8367C_SVLAN_C2SCFG39_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG39_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG40_CTRL0 0x0d78 +#define RTL8367C_SVLAN_C2SCFG40_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG40_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG40_CTRL1 0x0d79 +#define RTL8367C_SVLAN_C2SCFG40_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG40_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG40_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG40_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG40_CTRL2 0x0d7a +#define RTL8367C_SVLAN_C2SCFG40_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG40_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG41_CTRL0 0x0d7b +#define RTL8367C_SVLAN_C2SCFG41_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG41_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG41_CTRL1 0x0d7c +#define RTL8367C_SVLAN_C2SCFG41_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG41_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG41_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG41_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG41_CTRL2 0x0d7d +#define RTL8367C_SVLAN_C2SCFG41_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG41_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG42_CTRL0 0x0d7e +#define RTL8367C_SVLAN_C2SCFG42_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG42_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG42_CTRL1 0x0d7f +#define RTL8367C_SVLAN_C2SCFG42_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG42_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG42_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG42_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG42_CTRL2 0x0d80 +#define RTL8367C_SVLAN_C2SCFG42_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG42_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG43_CTRL0 0x0d81 +#define RTL8367C_SVLAN_C2SCFG43_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG43_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG43_CTRL1 0x0d82 +#define RTL8367C_SVLAN_C2SCFG43_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG43_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG43_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG43_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG43_CTRL2 0x0d83 +#define RTL8367C_SVLAN_C2SCFG43_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG43_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG44_CTRL0 0x0d84 +#define RTL8367C_SVLAN_C2SCFG44_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG44_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG44_CTRL1 0x0d85 +#define RTL8367C_SVLAN_C2SCFG44_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG44_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG44_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG44_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG44_CTRL2 0x0d86 +#define RTL8367C_SVLAN_C2SCFG44_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG44_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG45_CTRL0 0x0d87 +#define RTL8367C_SVLAN_C2SCFG45_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG45_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG45_CTRL1 0x0d88 +#define RTL8367C_SVLAN_C2SCFG45_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG45_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG45_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG45_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG45_CTRL2 0x0d89 +#define RTL8367C_SVLAN_C2SCFG45_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG45_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG46_CTRL0 0x0d8a +#define RTL8367C_SVLAN_C2SCFG46_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG46_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG46_CTRL1 0x0d8b +#define RTL8367C_SVLAN_C2SCFG46_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG46_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG46_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG46_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG46_CTRL2 0x0d8c +#define RTL8367C_SVLAN_C2SCFG46_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG46_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG47_CTRL0 0x0d8d +#define RTL8367C_SVLAN_C2SCFG47_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG47_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG47_CTRL1 0x0d8e +#define RTL8367C_SVLAN_C2SCFG47_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG47_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG47_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG47_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG47_CTRL2 0x0d8f +#define RTL8367C_SVLAN_C2SCFG47_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG47_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG48_CTRL0 0x0d90 +#define RTL8367C_SVLAN_C2SCFG48_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG48_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG48_CTRL1 0x0d91 +#define RTL8367C_SVLAN_C2SCFG48_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG48_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG48_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG48_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG48_CTRL2 0x0d92 +#define RTL8367C_SVLAN_C2SCFG48_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG48_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG49_CTRL0 0x0d93 +#define RTL8367C_SVLAN_C2SCFG49_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG49_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG49_CTRL1 0x0d94 +#define RTL8367C_SVLAN_C2SCFG49_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG49_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG49_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG49_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG49_CTRL2 0x0d95 +#define RTL8367C_SVLAN_C2SCFG49_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG49_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG50_CTRL0 0x0d96 +#define RTL8367C_SVLAN_C2SCFG50_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG50_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG50_CTRL1 0x0d97 +#define RTL8367C_SVLAN_C2SCFG50_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG50_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG50_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG50_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG50_CTRL2 0x0d98 +#define RTL8367C_SVLAN_C2SCFG50_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG50_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG51_CTRL0 0x0d99 +#define RTL8367C_SVLAN_C2SCFG51_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG51_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG51_CTRL1 0x0d9a +#define RTL8367C_SVLAN_C2SCFG51_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG51_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG51_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG51_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG51_CTRL2 0x0d9b +#define RTL8367C_SVLAN_C2SCFG51_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG51_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG52_CTRL0 0x0d9c +#define RTL8367C_SVLAN_C2SCFG52_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG52_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG52_CTRL1 0x0d9d +#define RTL8367C_SVLAN_C2SCFG52_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG52_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG52_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG52_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG52_CTRL2 0x0d9e +#define RTL8367C_SVLAN_C2SCFG52_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG52_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG53_CTRL0 0x0d9f +#define RTL8367C_SVLAN_C2SCFG53_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG53_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG53_CTRL1 0x0da0 +#define RTL8367C_SVLAN_C2SCFG53_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG53_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG53_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG53_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG53_CTRL2 0x0da1 +#define RTL8367C_SVLAN_C2SCFG53_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG53_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG54_CTRL0 0x0da2 +#define RTL8367C_SVLAN_C2SCFG54_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG54_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG54_CTRL1 0x0da3 +#define RTL8367C_SVLAN_C2SCFG54_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG54_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG54_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG54_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG54_CTRL2 0x0da4 +#define RTL8367C_SVLAN_C2SCFG54_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG54_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG55_CTRL0 0x0da5 +#define RTL8367C_SVLAN_C2SCFG55_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG55_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG55_CTRL1 0x0da6 +#define RTL8367C_SVLAN_C2SCFG55_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG55_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG55_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG55_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG55_CTRL2 0x0da7 +#define RTL8367C_SVLAN_C2SCFG55_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG55_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG56_CTRL0 0x0da8 +#define RTL8367C_SVLAN_C2SCFG56_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG56_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG56_CTRL1 0x0da9 +#define RTL8367C_SVLAN_C2SCFG56_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG56_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG56_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG56_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG56_CTRL2 0x0daa +#define RTL8367C_SVLAN_C2SCFG56_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG56_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG57_CTRL0 0x0dab +#define RTL8367C_SVLAN_C2SCFG57_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG57_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG57_CTRL1 0x0dac +#define RTL8367C_SVLAN_C2SCFG57_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG57_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG57_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG57_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG57_CTRL2 0x0dad +#define RTL8367C_SVLAN_C2SCFG57_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG57_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG58_CTRL0 0x0dae +#define RTL8367C_SVLAN_C2SCFG58_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG58_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG58_CTRL1 0x0daf +#define RTL8367C_SVLAN_C2SCFG58_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG58_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG58_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG58_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG58_CTRL2 0x0db0 +#define RTL8367C_SVLAN_C2SCFG58_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG58_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG59_CTRL0 0x0db1 +#define RTL8367C_SVLAN_C2SCFG59_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG59_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG59_CTRL1 0x0db2 +#define RTL8367C_SVLAN_C2SCFG59_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG59_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG59_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG59_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG59_CTRL2 0x0db3 +#define RTL8367C_SVLAN_C2SCFG59_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG59_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG60_CTRL0 0x0db4 +#define RTL8367C_SVLAN_C2SCFG60_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG60_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG60_CTRL1 0x0db5 +#define RTL8367C_SVLAN_C2SCFG60_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG60_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG60_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG60_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG60_CTRL2 0x0db6 +#define RTL8367C_SVLAN_C2SCFG60_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG60_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG61_CTRL0 0x0db7 +#define RTL8367C_SVLAN_C2SCFG61_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG61_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG61_CTRL1 0x0db8 +#define RTL8367C_SVLAN_C2SCFG61_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG61_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG61_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG61_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG61_CTRL2 0x0db9 +#define RTL8367C_SVLAN_C2SCFG61_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG61_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG62_CTRL0 0x0dba +#define RTL8367C_SVLAN_C2SCFG62_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG62_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG62_CTRL1 0x0dbb +#define RTL8367C_SVLAN_C2SCFG62_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG62_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG62_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG62_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG62_CTRL2 0x0dbc +#define RTL8367C_SVLAN_C2SCFG62_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG62_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG63_CTRL0 0x0dbd +#define RTL8367C_SVLAN_C2SCFG63_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG63_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG63_CTRL1 0x0dbe +#define RTL8367C_SVLAN_C2SCFG63_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG63_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG63_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG63_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG63_CTRL2 0x0dbf +#define RTL8367C_SVLAN_C2SCFG63_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG63_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG64_CTRL0 0x0dc0 +#define RTL8367C_SVLAN_C2SCFG64_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG64_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG64_CTRL1 0x0dc1 +#define RTL8367C_SVLAN_C2SCFG64_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG64_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG64_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG64_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG64_CTRL2 0x0dc2 +#define RTL8367C_SVLAN_C2SCFG64_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG64_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG65_CTRL0 0x0dc3 +#define RTL8367C_SVLAN_C2SCFG65_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG65_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG65_CTRL1 0x0dc4 +#define RTL8367C_SVLAN_C2SCFG65_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG65_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG65_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG65_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG65_CTRL2 0x0dc5 +#define RTL8367C_SVLAN_C2SCFG65_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG65_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG66_CTRL0 0x0dc6 +#define RTL8367C_SVLAN_C2SCFG66_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG66_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG66_CTRL1 0x0dc7 +#define RTL8367C_SVLAN_C2SCFG66_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG66_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG66_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG66_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG66_CTRL2 0x0dc8 +#define RTL8367C_SVLAN_C2SCFG66_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG66_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG67_CTRL0 0x0dc9 +#define RTL8367C_SVLAN_C2SCFG67_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG67_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG67_CTRL1 0x0dca +#define RTL8367C_SVLAN_C2SCFG67_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG67_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG67_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG67_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG67_CTRL2 0x0dcb +#define RTL8367C_SVLAN_C2SCFG67_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG67_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG68_CTRL0 0x0dcc +#define RTL8367C_SVLAN_C2SCFG68_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG68_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG68_CTRL1 0x0dcd +#define RTL8367C_SVLAN_C2SCFG68_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG68_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG68_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG68_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG68_CTRL2 0x0dce +#define RTL8367C_SVLAN_C2SCFG68_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG68_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG69_CTRL0 0x0dcf +#define RTL8367C_SVLAN_C2SCFG69_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG69_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG69_CTRL1 0x0dd0 +#define RTL8367C_SVLAN_C2SCFG69_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG69_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG69_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG69_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG69_CTRL2 0x0dd1 +#define RTL8367C_SVLAN_C2SCFG69_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG69_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG70_CTRL0 0x0dd2 +#define RTL8367C_SVLAN_C2SCFG70_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG70_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG70_CTRL1 0x0dd3 +#define RTL8367C_SVLAN_C2SCFG70_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG70_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG70_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG70_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG70_CTRL2 0x0dd4 +#define RTL8367C_SVLAN_C2SCFG70_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG70_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG71_CTRL0 0x0dd5 +#define RTL8367C_SVLAN_C2SCFG71_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG71_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG71_CTRL1 0x0dd6 +#define RTL8367C_SVLAN_C2SCFG71_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG71_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG71_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG71_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG71_CTRL2 0x0dd7 +#define RTL8367C_SVLAN_C2SCFG71_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG71_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG72_CTRL0 0x0dd8 +#define RTL8367C_SVLAN_C2SCFG72_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG72_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG72_CTRL1 0x0dd9 +#define RTL8367C_SVLAN_C2SCFG72_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG72_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG72_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG72_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG72_CTRL2 0x0dda +#define RTL8367C_SVLAN_C2SCFG72_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG72_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG73_CTRL0 0x0ddb +#define RTL8367C_SVLAN_C2SCFG73_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG73_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG73_CTRL1 0x0ddc +#define RTL8367C_SVLAN_C2SCFG73_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG73_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG73_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG73_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG73_CTRL2 0x0ddd +#define RTL8367C_SVLAN_C2SCFG73_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG73_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG74_CTRL0 0x0dde +#define RTL8367C_SVLAN_C2SCFG74_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG74_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG74_CTRL1 0x0ddf +#define RTL8367C_SVLAN_C2SCFG74_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG74_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG74_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG74_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG74_CTRL2 0x0de0 +#define RTL8367C_SVLAN_C2SCFG74_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG74_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG75_CTRL0 0x0de1 +#define RTL8367C_SVLAN_C2SCFG75_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG75_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG75_CTRL1 0x0de2 +#define RTL8367C_SVLAN_C2SCFG75_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG75_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG75_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG75_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG75_CTRL2 0x0de3 +#define RTL8367C_SVLAN_C2SCFG75_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG75_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG76_CTRL0 0x0de4 +#define RTL8367C_SVLAN_C2SCFG76_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG76_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG76_CTRL1 0x0de5 +#define RTL8367C_SVLAN_C2SCFG76_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG76_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG76_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG76_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG76_CTRL2 0x0de6 +#define RTL8367C_SVLAN_C2SCFG76_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG76_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG77_CTRL0 0x0de7 +#define RTL8367C_SVLAN_C2SCFG77_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG77_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG77_CTRL1 0x0de8 +#define RTL8367C_SVLAN_C2SCFG77_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG77_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG77_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG77_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG77_CTRL2 0x0de9 +#define RTL8367C_SVLAN_C2SCFG77_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG77_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG78_CTRL0 0x0dea +#define RTL8367C_SVLAN_C2SCFG78_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG78_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG78_CTRL1 0x0deb +#define RTL8367C_SVLAN_C2SCFG78_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG78_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG78_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG78_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG78_CTRL2 0x0dec +#define RTL8367C_SVLAN_C2SCFG78_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG78_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG79_CTRL0 0x0ded +#define RTL8367C_SVLAN_C2SCFG79_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG79_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG79_CTRL1 0x0dee +#define RTL8367C_SVLAN_C2SCFG79_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG79_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG79_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG79_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG79_CTRL2 0x0def +#define RTL8367C_SVLAN_C2SCFG79_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG79_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG80_CTRL0 0x0df0 +#define RTL8367C_SVLAN_C2SCFG80_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG80_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG80_CTRL1 0x0df1 +#define RTL8367C_SVLAN_C2SCFG80_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG80_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG80_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG80_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG80_CTRL2 0x0df2 +#define RTL8367C_SVLAN_C2SCFG80_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG80_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG81_CTRL0 0x0df3 +#define RTL8367C_SVLAN_C2SCFG81_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG81_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG81_CTRL1 0x0df4 +#define RTL8367C_SVLAN_C2SCFG81_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG81_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG81_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG81_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG81_CTRL2 0x0df5 +#define RTL8367C_SVLAN_C2SCFG81_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG81_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG82_CTRL0 0x0df6 +#define RTL8367C_SVLAN_C2SCFG82_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG82_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG82_CTRL1 0x0df7 +#define RTL8367C_SVLAN_C2SCFG82_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG82_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG82_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG82_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG82_CTRL2 0x0df8 +#define RTL8367C_SVLAN_C2SCFG82_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG82_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG83_CTRL0 0x0df9 +#define RTL8367C_SVLAN_C2SCFG83_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG83_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG83_CTRL1 0x0dfa +#define RTL8367C_SVLAN_C2SCFG83_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG83_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG83_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG83_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG83_CTRL2 0x0dfb +#define RTL8367C_SVLAN_C2SCFG83_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG83_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG84_CTRL0 0x0dfc +#define RTL8367C_SVLAN_C2SCFG84_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG84_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG84_CTRL1 0x0dfd +#define RTL8367C_SVLAN_C2SCFG84_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG84_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG84_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG84_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG84_CTRL2 0x0dfe +#define RTL8367C_SVLAN_C2SCFG84_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG84_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG85_CTRL0 0x0dff +#define RTL8367C_SVLAN_C2SCFG85_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG85_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG85_CTRL1 0x0e00 +#define RTL8367C_SVLAN_C2SCFG85_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG85_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG85_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG85_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG85_CTRL2 0x0e01 +#define RTL8367C_SVLAN_C2SCFG85_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG85_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG86_CTRL0 0x0e02 +#define RTL8367C_SVLAN_C2SCFG86_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG86_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG86_CTRL1 0x0e03 +#define RTL8367C_SVLAN_C2SCFG86_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG86_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG86_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG86_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG86_CTRL2 0x0e04 +#define RTL8367C_SVLAN_C2SCFG86_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG86_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG87_CTRL0 0x0e05 +#define RTL8367C_SVLAN_C2SCFG87_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG87_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG87_CTRL1 0x0e06 +#define RTL8367C_SVLAN_C2SCFG87_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG87_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG87_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG87_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG87_CTRL2 0x0e07 +#define RTL8367C_SVLAN_C2SCFG87_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG87_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG88_CTRL0 0x0e08 +#define RTL8367C_SVLAN_C2SCFG88_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG88_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG88_CTRL1 0x0e09 +#define RTL8367C_SVLAN_C2SCFG88_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG88_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG88_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG88_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG88_CTRL2 0x0e0a +#define RTL8367C_SVLAN_C2SCFG88_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG88_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG89_CTRL0 0x0e0b +#define RTL8367C_SVLAN_C2SCFG89_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG89_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG89_CTRL1 0x0e0c +#define RTL8367C_SVLAN_C2SCFG89_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG89_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG89_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG89_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG89_CTRL2 0x0e0d +#define RTL8367C_SVLAN_C2SCFG89_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG89_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG90_CTRL0 0x0e0e +#define RTL8367C_SVLAN_C2SCFG90_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG90_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG90_CTRL1 0x0e0f +#define RTL8367C_SVLAN_C2SCFG90_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG90_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG90_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG90_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG90_CTRL2 0x0e10 +#define RTL8367C_SVLAN_C2SCFG90_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG90_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG91_CTRL0 0x0e11 +#define RTL8367C_SVLAN_C2SCFG91_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG91_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG91_CTRL1 0x0e12 +#define RTL8367C_SVLAN_C2SCFG91_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG91_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG91_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG91_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG91_CTRL2 0x0e13 +#define RTL8367C_SVLAN_C2SCFG91_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG91_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG92_CTRL0 0x0e14 +#define RTL8367C_SVLAN_C2SCFG92_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG92_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG92_CTRL1 0x0e15 +#define RTL8367C_SVLAN_C2SCFG92_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG92_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG92_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG92_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG92_CTRL2 0x0e16 +#define RTL8367C_SVLAN_C2SCFG92_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG92_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG93_CTRL0 0x0e17 +#define RTL8367C_SVLAN_C2SCFG93_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG93_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG93_CTRL1 0x0e18 +#define RTL8367C_SVLAN_C2SCFG93_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG93_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG93_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG93_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG93_CTRL2 0x0e19 +#define RTL8367C_SVLAN_C2SCFG93_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG93_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG94_CTRL0 0x0e1a +#define RTL8367C_SVLAN_C2SCFG94_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG94_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG94_CTRL1 0x0e1b +#define RTL8367C_SVLAN_C2SCFG94_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG94_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG94_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG94_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG94_CTRL2 0x0e1c +#define RTL8367C_SVLAN_C2SCFG94_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG94_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG95_CTRL0 0x0e1d +#define RTL8367C_SVLAN_C2SCFG95_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG95_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG95_CTRL1 0x0e1e +#define RTL8367C_SVLAN_C2SCFG95_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG95_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG95_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG95_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG95_CTRL2 0x0e1f +#define RTL8367C_SVLAN_C2SCFG95_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG95_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG96_CTRL0 0x0e20 +#define RTL8367C_SVLAN_C2SCFG96_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG96_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG96_CTRL1 0x0e21 +#define RTL8367C_SVLAN_C2SCFG96_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG96_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG96_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG96_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG96_CTRL2 0x0e22 +#define RTL8367C_SVLAN_C2SCFG96_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG96_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG97_CTRL0 0x0e23 +#define RTL8367C_SVLAN_C2SCFG97_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG97_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG97_CTRL1 0x0e24 +#define RTL8367C_SVLAN_C2SCFG97_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG97_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG97_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG97_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG97_CTRL2 0x0e25 +#define RTL8367C_SVLAN_C2SCFG97_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG97_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG98_CTRL0 0x0e26 +#define RTL8367C_SVLAN_C2SCFG98_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG98_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG98_CTRL1 0x0e27 +#define RTL8367C_SVLAN_C2SCFG98_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG98_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG98_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG98_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG98_CTRL2 0x0e28 +#define RTL8367C_SVLAN_C2SCFG98_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG98_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG99_CTRL0 0x0e29 +#define RTL8367C_SVLAN_C2SCFG99_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG99_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG99_CTRL1 0x0e2a +#define RTL8367C_SVLAN_C2SCFG99_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG99_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG99_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG99_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG99_CTRL2 0x0e2b +#define RTL8367C_SVLAN_C2SCFG99_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG99_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG100_CTRL0 0x0e2c +#define RTL8367C_SVLAN_C2SCFG100_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG100_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG100_CTRL1 0x0e2d +#define RTL8367C_SVLAN_C2SCFG100_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG100_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG100_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG100_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG100_CTRL2 0x0e2e +#define RTL8367C_SVLAN_C2SCFG100_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG100_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG101_CTRL0 0x0e2f +#define RTL8367C_SVLAN_C2SCFG101_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG101_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG101_CTRL1 0x0e30 +#define RTL8367C_SVLAN_C2SCFG101_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG101_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG101_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG101_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG101_CTRL2 0x0e31 +#define RTL8367C_SVLAN_C2SCFG101_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG101_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG102_CTRL0 0x0e32 +#define RTL8367C_SVLAN_C2SCFG102_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG102_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG102_CTRL1 0x0e33 +#define RTL8367C_SVLAN_C2SCFG102_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG102_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG102_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG102_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG102_CTRL2 0x0e34 +#define RTL8367C_SVLAN_C2SCFG102_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG102_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG103_CTRL0 0x0e35 +#define RTL8367C_SVLAN_C2SCFG103_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG103_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG103_CTRL1 0x0e36 +#define RTL8367C_SVLAN_C2SCFG103_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG103_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG103_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG103_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG103_CTRL2 0x0e37 +#define RTL8367C_SVLAN_C2SCFG103_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG103_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG104_CTRL0 0x0e38 +#define RTL8367C_SVLAN_C2SCFG104_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG104_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG104_CTRL1 0x0e39 +#define RTL8367C_SVLAN_C2SCFG104_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG104_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG104_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG104_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG104_CTRL2 0x0e3a +#define RTL8367C_SVLAN_C2SCFG104_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG104_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG105_CTRL0 0x0e3b +#define RTL8367C_SVLAN_C2SCFG105_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG105_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG105_CTRL1 0x0e3c +#define RTL8367C_SVLAN_C2SCFG105_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG105_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG105_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG105_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG105_CTRL2 0x0e3d +#define RTL8367C_SVLAN_C2SCFG105_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG105_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG106_CTRL0 0x0e3e +#define RTL8367C_SVLAN_C2SCFG106_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG106_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG106_CTRL1 0x0e3f +#define RTL8367C_SVLAN_C2SCFG106_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG106_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG106_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG106_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG106_CTRL2 0x0e40 +#define RTL8367C_SVLAN_C2SCFG106_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG106_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG107_CTRL0 0x0e41 +#define RTL8367C_SVLAN_C2SCFG107_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG107_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG107_CTRL1 0x0e42 +#define RTL8367C_SVLAN_C2SCFG107_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG107_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG107_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG107_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG107_CTRL2 0x0e43 +#define RTL8367C_SVLAN_C2SCFG107_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG107_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG108_CTRL0 0x0e44 +#define RTL8367C_SVLAN_C2SCFG108_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG108_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG108_CTRL1 0x0e45 +#define RTL8367C_SVLAN_C2SCFG108_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG108_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG108_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG108_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG108_CTRL2 0x0e46 +#define RTL8367C_SVLAN_C2SCFG108_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG108_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG109_CTRL0 0x0e47 +#define RTL8367C_SVLAN_C2SCFG109_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG109_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG109_CTRL1 0x0e48 +#define RTL8367C_SVLAN_C2SCFG109_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG109_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG109_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG109_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG109_CTRL2 0x0e49 +#define RTL8367C_SVLAN_C2SCFG109_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG109_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG110_CTRL0 0x0e4a +#define RTL8367C_SVLAN_C2SCFG110_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG110_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG110_CTRL1 0x0e4b +#define RTL8367C_SVLAN_C2SCFG110_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG110_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG110_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG110_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG110_CTRL2 0x0e4c +#define RTL8367C_SVLAN_C2SCFG110_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG110_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG111_CTRL0 0x0e4d +#define RTL8367C_SVLAN_C2SCFG111_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG111_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG111_CTRL1 0x0e4e +#define RTL8367C_SVLAN_C2SCFG111_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG111_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG111_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG111_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG111_CTRL2 0x0e4f +#define RTL8367C_SVLAN_C2SCFG111_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG111_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG112_CTRL0 0x0e50 +#define RTL8367C_SVLAN_C2SCFG112_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG112_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG112_CTRL1 0x0e51 +#define RTL8367C_SVLAN_C2SCFG112_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG112_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG112_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG112_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG112_CTRL2 0x0e52 +#define RTL8367C_SVLAN_C2SCFG112_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG112_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG113_CTRL0 0x0e53 +#define RTL8367C_SVLAN_C2SCFG113_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG113_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG113_CTRL1 0x0e54 +#define RTL8367C_SVLAN_C2SCFG113_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG113_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG113_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG113_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG113_CTRL2 0x0e55 +#define RTL8367C_SVLAN_C2SCFG113_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG113_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG114_CTRL0 0x0e56 +#define RTL8367C_SVLAN_C2SCFG114_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG114_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG114_CTRL1 0x0e57 +#define RTL8367C_SVLAN_C2SCFG114_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG114_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG114_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG114_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG114_CTRL2 0x0e58 +#define RTL8367C_SVLAN_C2SCFG114_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG114_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG115_CTRL0 0x0e59 +#define RTL8367C_SVLAN_C2SCFG115_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG115_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG115_CTRL1 0x0e5a +#define RTL8367C_SVLAN_C2SCFG115_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG115_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG115_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG115_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG115_CTRL2 0x0e5b +#define RTL8367C_SVLAN_C2SCFG115_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG115_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG116_CTRL0 0x0e5c +#define RTL8367C_SVLAN_C2SCFG116_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG116_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG116_CTRL1 0x0e5d +#define RTL8367C_SVLAN_C2SCFG116_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG116_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG116_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG116_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG116_CTRL2 0x0e5e +#define RTL8367C_SVLAN_C2SCFG116_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG116_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG117_CTRL0 0x0e5f +#define RTL8367C_SVLAN_C2SCFG117_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG117_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG117_CTRL1 0x0e60 +#define RTL8367C_SVLAN_C2SCFG117_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG117_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG117_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG117_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG117_CTRL2 0x0e61 +#define RTL8367C_SVLAN_C2SCFG117_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG117_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG118_CTRL0 0x0e62 +#define RTL8367C_SVLAN_C2SCFG118_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG118_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG118_CTRL1 0x0e63 +#define RTL8367C_SVLAN_C2SCFG118_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG118_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG118_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG118_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG118_CTRL2 0x0e64 +#define RTL8367C_SVLAN_C2SCFG118_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG118_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG119_CTRL0 0x0e65 +#define RTL8367C_SVLAN_C2SCFG119_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG119_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG119_CTRL1 0x0e66 +#define RTL8367C_SVLAN_C2SCFG119_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG119_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG119_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG119_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG119_CTRL2 0x0e67 +#define RTL8367C_SVLAN_C2SCFG119_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG119_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG120_CTRL0 0x0e68 +#define RTL8367C_SVLAN_C2SCFG120_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG120_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG120_CTRL1 0x0e69 +#define RTL8367C_SVLAN_C2SCFG120_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG120_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG120_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG120_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG120_CTRL2 0x0e6a +#define RTL8367C_SVLAN_C2SCFG120_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG120_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG121_CTRL0 0x0e6b +#define RTL8367C_SVLAN_C2SCFG121_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG121_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG121_CTRL1 0x0e6c +#define RTL8367C_SVLAN_C2SCFG121_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG121_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG121_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG121_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG121_CTRL2 0x0e6d +#define RTL8367C_SVLAN_C2SCFG121_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG121_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG122_CTRL0 0x0e6e +#define RTL8367C_SVLAN_C2SCFG122_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG122_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG122_CTRL1 0x0e6f +#define RTL8367C_SVLAN_C2SCFG122_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG122_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG122_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG122_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG122_CTRL2 0x0e70 +#define RTL8367C_SVLAN_C2SCFG122_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG122_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG123_CTRL0 0x0e71 +#define RTL8367C_SVLAN_C2SCFG123_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG123_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG123_CTRL1 0x0e72 +#define RTL8367C_SVLAN_C2SCFG123_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG123_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG123_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG123_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG123_CTRL2 0x0e73 +#define RTL8367C_SVLAN_C2SCFG123_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG123_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG124_CTRL0 0x0e74 +#define RTL8367C_SVLAN_C2SCFG124_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG124_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG124_CTRL1 0x0e75 +#define RTL8367C_SVLAN_C2SCFG124_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG124_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG124_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG124_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG124_CTRL2 0x0e76 +#define RTL8367C_SVLAN_C2SCFG124_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG124_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG125_CTRL0 0x0e77 +#define RTL8367C_SVLAN_C2SCFG125_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG125_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG125_CTRL1 0x0e78 +#define RTL8367C_SVLAN_C2SCFG125_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG125_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG125_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG125_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG125_CTRL2 0x0e79 +#define RTL8367C_SVLAN_C2SCFG125_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG125_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG126_CTRL0 0x0e7a +#define RTL8367C_SVLAN_C2SCFG126_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG126_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG126_CTRL1 0x0e7b +#define RTL8367C_SVLAN_C2SCFG126_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG126_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG126_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG126_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG126_CTRL2 0x0e7c +#define RTL8367C_SVLAN_C2SCFG126_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG126_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_C2SCFG127_CTRL0 0x0e7d +#define RTL8367C_SVLAN_C2SCFG127_CTRL0_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG127_CTRL0_MASK 0x3F + +#define RTL8367C_REG_SVLAN_C2SCFG127_CTRL1 0x0e7e +#define RTL8367C_SVLAN_C2SCFG127_CTRL1_C2SENPMSK_EXT_OFFSET 8 +#define RTL8367C_SVLAN_C2SCFG127_CTRL1_C2SENPMSK_EXT_MASK 0x700 +#define RTL8367C_SVLAN_C2SCFG127_CTRL1_C2SENPMSK_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG127_CTRL1_C2SENPMSK_MASK 0xFF + +#define RTL8367C_REG_SVLAN_C2SCFG127_CTRL2 0x0e7f +#define RTL8367C_SVLAN_C2SCFG127_CTRL2_OFFSET 0 +#define RTL8367C_SVLAN_C2SCFG127_CTRL2_MASK 0x1FFF + +#define RTL8367C_REG_SVLAN_CFG 0x0e80 +#define RTL8367C_VS_PORT7_DMACVIDSEL_OFFSET 14 +#define RTL8367C_VS_PORT7_DMACVIDSEL_MASK 0x4000 +#define RTL8367C_VS_PORT6_DMACVIDSEL_OFFSET 13 +#define RTL8367C_VS_PORT6_DMACVIDSEL_MASK 0x2000 +#define RTL8367C_VS_PORT5_DMACVIDSEL_OFFSET 12 +#define RTL8367C_VS_PORT5_DMACVIDSEL_MASK 0x1000 +#define RTL8367C_VS_PORT4_DMACVIDSEL_OFFSET 11 +#define RTL8367C_VS_PORT4_DMACVIDSEL_MASK 0x800 +#define RTL8367C_VS_PORT3_DMACVIDSEL_OFFSET 10 +#define RTL8367C_VS_PORT3_DMACVIDSEL_MASK 0x400 +#define RTL8367C_VS_PORT2_DMACVIDSEL_OFFSET 9 +#define RTL8367C_VS_PORT2_DMACVIDSEL_MASK 0x200 +#define RTL8367C_VS_PORT1_DMACVIDSEL_OFFSET 8 +#define RTL8367C_VS_PORT1_DMACVIDSEL_MASK 0x100 +#define RTL8367C_VS_PORT0_DMACVIDSEL_OFFSET 7 +#define RTL8367C_VS_PORT0_DMACVIDSEL_MASK 0x80 +#define RTL8367C_VS_UIFSEG_OFFSET 6 +#define RTL8367C_VS_UIFSEG_MASK 0x40 +#define RTL8367C_VS_UNMAT_OFFSET 4 +#define RTL8367C_VS_UNMAT_MASK 0x30 +#define RTL8367C_VS_UNTAG_OFFSET 2 +#define RTL8367C_VS_UNTAG_MASK 0xC +#define RTL8367C_VS_SPRISEL_OFFSET 0 +#define RTL8367C_VS_SPRISEL_MASK 0x3 + +#define RTL8367C_REG_SVLAN_PORTBASED_SVIDX_CTRL0 0x0e81 +#define RTL8367C_VS_PORT1_SVIDX_OFFSET 8 +#define RTL8367C_VS_PORT1_SVIDX_MASK 0x3F00 +#define RTL8367C_VS_PORT0_SVIDX_OFFSET 0 +#define RTL8367C_VS_PORT0_SVIDX_MASK 0x3F + +#define RTL8367C_REG_SVLAN_PORTBASED_SVIDX_CTRL1 0x0e82 +#define RTL8367C_VS_PORT3_SVIDX_OFFSET 8 +#define RTL8367C_VS_PORT3_SVIDX_MASK 0x3F00 +#define RTL8367C_VS_PORT2_SVIDX_OFFSET 0 +#define RTL8367C_VS_PORT2_SVIDX_MASK 0x3F + +#define RTL8367C_REG_SVLAN_PORTBASED_SVIDX_CTRL2 0x0e83 +#define RTL8367C_VS_PORT5_SVIDX_OFFSET 8 +#define RTL8367C_VS_PORT5_SVIDX_MASK 0x3F00 +#define RTL8367C_VS_PORT4_SVIDX_OFFSET 0 +#define RTL8367C_VS_PORT4_SVIDX_MASK 0x3F + +#define RTL8367C_REG_SVLAN_PORTBASED_SVIDX_CTRL3 0x0e84 +#define RTL8367C_VS_PORT7_SVIDX_OFFSET 8 +#define RTL8367C_VS_PORT7_SVIDX_MASK 0x3F00 +#define RTL8367C_VS_PORT6_SVIDX_OFFSET 0 +#define RTL8367C_VS_PORT6_SVIDX_MASK 0x3F + +#define RTL8367C_REG_SVLAN_UNTAG_UNMAT_CFG 0x0e85 +#define RTL8367C_VS_UNTAG_SVIDX_OFFSET 8 +#define RTL8367C_VS_UNTAG_SVIDX_MASK 0x3F00 +#define RTL8367C_VS_UNMAT_SVIDX_OFFSET 0 +#define RTL8367C_VS_UNMAT_SVIDX_MASK 0x3F + +#define RTL8367C_REG_SVLAN_LOOKUP_TYPE 0x0e86 +#define RTL8367C_SVLAN_LOOKUP_TYPE_OFFSET 0 +#define RTL8367C_SVLAN_LOOKUP_TYPE_MASK 0x1 + +#define RTL8367C_REG_IPMC_GROUP_VALID_15_0 0x0e87 + +#define RTL8367C_REG_IPMC_GROUP_VALID_31_16 0x0e88 + +#define RTL8367C_REG_IPMC_GROUP_VALID_47_32 0x0e89 + +#define RTL8367C_REG_IPMC_GROUP_VALID_63_48 0x0e8a + +#define RTL8367C_REG_SVLAN_PORTBASED_SVIDX_CTRL4 0x0e8b +#define RTL8367C_VS_PORT9_SVIDX_OFFSET 8 +#define RTL8367C_VS_PORT9_SVIDX_MASK 0x3F00 +#define RTL8367C_VS_PORT8_SVIDX_OFFSET 0 +#define RTL8367C_VS_PORT8_SVIDX_MASK 0x3F + +#define RTL8367C_REG_SVLAN_PORTBASED_SVIDX_CTRL5 0x0e8c +#define RTL8367C_SVLAN_PORTBASED_SVIDX_CTRL5_OFFSET 0 +#define RTL8367C_SVLAN_PORTBASED_SVIDX_CTRL5_MASK 0x3F + +#define RTL8367C_REG_SVLAN_CFG_EXT 0x0e8d +#define RTL8367C_VS_PORT10_DMACVIDSEL_OFFSET 2 +#define RTL8367C_VS_PORT10_DMACVIDSEL_MASK 0x4 +#define RTL8367C_VS_PORT9_DMACVIDSEL_OFFSET 1 +#define RTL8367C_VS_PORT9_DMACVIDSEL_MASK 0x2 +#define RTL8367C_VS_PORT8_DMACVIDSEL_OFFSET 0 +#define RTL8367C_VS_PORT8_DMACVIDSEL_MASK 0x1 + +#define RTL8367C_REG_SVLAN_MEMBERCFG63_CTRL4 0x0e8e +#define RTL8367C_SVLAN_MEMBERCFG63_CTRL4_VS_UNTAGSET_EXT_OFFSET 8 +#define RTL8367C_SVLAN_MEMBERCFG63_CTRL4_VS_UNTAGSET_EXT_MASK 0x700 +#define RTL8367C_SVLAN_MEMBERCFG63_CTRL4_VS_SMBR_EXT_OFFSET 0 +#define RTL8367C_SVLAN_MEMBERCFG63_CTRL4_VS_SMBR_EXT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_DUMMY_0 0x0e90 + +#define RTL8367C_REG_SVLAN_DUMMY_1 0x0e91 + +#define RTL8367C_REG_SVLAN_DUMMY_2 0x0e92 + +#define RTL8367C_REG_SVLAN_DUMMY_3 0x0e93 + +#define RTL8367C_REG_SVLAN_DUMMY_4 0x0e94 + +#define RTL8367C_REG_SVLAN_DUMMY_5 0x0e95 + +#define RTL8367C_REG_SVLAN_DUMMY_6 0x0e96 + +#define RTL8367C_REG_SVLAN_DUMMY_7 0x0e97 + +#define RTL8367C_REG_SVLAN_DUMMY_8 0x0e98 + +#define RTL8367C_REG_SVLAN_DUMMY_9 0x0e99 + +#define RTL8367C_REG_SVLAN_DUMMY_10 0x0e9a + +#define RTL8367C_REG_SVLAN_DUMMY_11 0x0e9b + +#define RTL8367C_REG_SVLAN_DUMMY_12 0x0e9c + +#define RTL8367C_REG_SVLAN_DUMMY_13 0x0e9d + +#define RTL8367C_REG_SVLAN_DUMMY_14 0x0e9e + +#define RTL8367C_REG_SVLAN_DUMMY_15 0x0e9f + +#define RTL8367C_REG_SVLAN_DUMMY_16 0x0ea0 + +#define RTL8367C_REG_SVLAN_DUMMY_17 0x0ea1 + +#define RTL8367C_REG_SVLAN_DUMMY_18 0x0ea2 + +#define RTL8367C_REG_SVLAN_DUMMY_19 0x0ea3 + +#define RTL8367C_REG_SVLAN_DUMMY_20 0x0ea4 + +#define RTL8367C_REG_SVLAN_DUMMY_21 0x0ea5 + +#define RTL8367C_REG_SVLAN_DUMMY_22 0x0ea6 + +#define RTL8367C_REG_SVLAN_DUMMY_23 0x0ea7 + +#define RTL8367C_REG_SVLAN_DUMMY_24 0x0ea8 + +#define RTL8367C_REG_SVLAN_DUMMY_25 0x0ea9 + +#define RTL8367C_REG_SVLAN_DUMMY_26 0x0eaa + +#define RTL8367C_REG_SVLAN_DUMMY_27 0x0eab + +#define RTL8367C_REG_SVLAN_DUMMY_28 0x0eac + +#define RTL8367C_REG_SVLAN_DUMMY_29 0x0ead + +#define RTL8367C_REG_SVLAN_DUMMY_30 0x0eae + +#define RTL8367C_REG_SVLAN_DUMMY_31 0x0eaf + +#define RTL8367C_REG_IPMC_GROUP_VID_00 0x0eb0 +#define RTL8367C_IPMC_GROUP_VID_00_OFFSET 0 +#define RTL8367C_IPMC_GROUP_VID_00_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_VID_01 0x0eb1 +#define RTL8367C_IPMC_GROUP_VID_01_OFFSET 0 +#define RTL8367C_IPMC_GROUP_VID_01_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_VID_02 0x0eb2 +#define RTL8367C_IPMC_GROUP_VID_02_OFFSET 0 +#define RTL8367C_IPMC_GROUP_VID_02_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_VID_03 0x0eb3 +#define RTL8367C_IPMC_GROUP_VID_03_OFFSET 0 +#define RTL8367C_IPMC_GROUP_VID_03_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_VID_04 0x0eb4 +#define RTL8367C_IPMC_GROUP_VID_04_OFFSET 0 +#define RTL8367C_IPMC_GROUP_VID_04_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_VID_05 0x0eb5 +#define RTL8367C_IPMC_GROUP_VID_05_OFFSET 0 +#define RTL8367C_IPMC_GROUP_VID_05_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_VID_06 0x0eb6 +#define RTL8367C_IPMC_GROUP_VID_06_OFFSET 0 +#define RTL8367C_IPMC_GROUP_VID_06_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_VID_07 0x0eb7 +#define RTL8367C_IPMC_GROUP_VID_07_OFFSET 0 +#define RTL8367C_IPMC_GROUP_VID_07_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_VID_08 0x0eb8 +#define RTL8367C_IPMC_GROUP_VID_08_OFFSET 0 +#define RTL8367C_IPMC_GROUP_VID_08_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_VID_09 0x0eb9 +#define RTL8367C_IPMC_GROUP_VID_09_OFFSET 0 +#define RTL8367C_IPMC_GROUP_VID_09_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_VID_10 0x0eba +#define RTL8367C_IPMC_GROUP_VID_10_OFFSET 0 +#define RTL8367C_IPMC_GROUP_VID_10_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_VID_11 0x0ebb +#define RTL8367C_IPMC_GROUP_VID_11_OFFSET 0 +#define RTL8367C_IPMC_GROUP_VID_11_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_VID_12 0x0ebc +#define RTL8367C_IPMC_GROUP_VID_12_OFFSET 0 +#define RTL8367C_IPMC_GROUP_VID_12_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_VID_13 0x0ebd +#define RTL8367C_IPMC_GROUP_VID_13_OFFSET 0 +#define RTL8367C_IPMC_GROUP_VID_13_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_VID_14 0x0ebe +#define RTL8367C_IPMC_GROUP_VID_14_OFFSET 0 +#define RTL8367C_IPMC_GROUP_VID_14_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_VID_15 0x0ebf +#define RTL8367C_IPMC_GROUP_VID_15_OFFSET 0 +#define RTL8367C_IPMC_GROUP_VID_15_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_VID_16 0x0ec0 +#define RTL8367C_IPMC_GROUP_VID_16_OFFSET 0 +#define RTL8367C_IPMC_GROUP_VID_16_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_VID_17 0x0ec1 +#define RTL8367C_IPMC_GROUP_VID_17_OFFSET 0 +#define RTL8367C_IPMC_GROUP_VID_17_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_VID_18 0x0ec2 +#define RTL8367C_IPMC_GROUP_VID_18_OFFSET 0 +#define RTL8367C_IPMC_GROUP_VID_18_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_VID_19 0x0ec3 +#define RTL8367C_IPMC_GROUP_VID_19_OFFSET 0 +#define RTL8367C_IPMC_GROUP_VID_19_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_VID_20 0x0ec4 +#define RTL8367C_IPMC_GROUP_VID_20_OFFSET 0 +#define RTL8367C_IPMC_GROUP_VID_20_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_VID_21 0x0ec5 +#define RTL8367C_IPMC_GROUP_VID_21_OFFSET 0 +#define RTL8367C_IPMC_GROUP_VID_21_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_VID_22 0x0ec6 +#define RTL8367C_IPMC_GROUP_VID_22_OFFSET 0 +#define RTL8367C_IPMC_GROUP_VID_22_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_VID_23 0x0ec7 +#define RTL8367C_IPMC_GROUP_VID_23_OFFSET 0 +#define RTL8367C_IPMC_GROUP_VID_23_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_VID_24 0x0ec8 +#define RTL8367C_IPMC_GROUP_VID_24_OFFSET 0 +#define RTL8367C_IPMC_GROUP_VID_24_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_VID_25 0x0ec9 +#define RTL8367C_IPMC_GROUP_VID_25_OFFSET 0 +#define RTL8367C_IPMC_GROUP_VID_25_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_VID_26 0x0eca +#define RTL8367C_IPMC_GROUP_VID_26_OFFSET 0 +#define RTL8367C_IPMC_GROUP_VID_26_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_VID_27 0x0ecb +#define RTL8367C_IPMC_GROUP_VID_27_OFFSET 0 +#define RTL8367C_IPMC_GROUP_VID_27_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_VID_28 0x0ecc +#define RTL8367C_IPMC_GROUP_VID_28_OFFSET 0 +#define RTL8367C_IPMC_GROUP_VID_28_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_VID_29 0x0ecd +#define RTL8367C_IPMC_GROUP_VID_29_OFFSET 0 +#define RTL8367C_IPMC_GROUP_VID_29_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_VID_30 0x0ece +#define RTL8367C_IPMC_GROUP_VID_30_OFFSET 0 +#define RTL8367C_IPMC_GROUP_VID_30_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_VID_31 0x0ecf +#define RTL8367C_IPMC_GROUP_VID_31_OFFSET 0 +#define RTL8367C_IPMC_GROUP_VID_31_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_VID_32 0x0ed0 +#define RTL8367C_IPMC_GROUP_VID_32_OFFSET 0 +#define RTL8367C_IPMC_GROUP_VID_32_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_VID_33 0x0ed1 +#define RTL8367C_IPMC_GROUP_VID_33_OFFSET 0 +#define RTL8367C_IPMC_GROUP_VID_33_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_VID_34 0x0ed2 +#define RTL8367C_IPMC_GROUP_VID_34_OFFSET 0 +#define RTL8367C_IPMC_GROUP_VID_34_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_VID_35 0x0ed3 +#define RTL8367C_IPMC_GROUP_VID_35_OFFSET 0 +#define RTL8367C_IPMC_GROUP_VID_35_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_VID_36 0x0ed4 +#define RTL8367C_IPMC_GROUP_VID_36_OFFSET 0 +#define RTL8367C_IPMC_GROUP_VID_36_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_VID_37 0x0ed5 +#define RTL8367C_IPMC_GROUP_VID_37_OFFSET 0 +#define RTL8367C_IPMC_GROUP_VID_37_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_VID_38 0x0ed6 +#define RTL8367C_IPMC_GROUP_VID_38_OFFSET 0 +#define RTL8367C_IPMC_GROUP_VID_38_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_VID_39 0x0ed7 +#define RTL8367C_IPMC_GROUP_VID_39_OFFSET 0 +#define RTL8367C_IPMC_GROUP_VID_39_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_VID_40 0x0ed8 +#define RTL8367C_IPMC_GROUP_VID_40_OFFSET 0 +#define RTL8367C_IPMC_GROUP_VID_40_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_VID_41 0x0ed9 +#define RTL8367C_IPMC_GROUP_VID_41_OFFSET 0 +#define RTL8367C_IPMC_GROUP_VID_41_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_VID_42 0x0eda +#define RTL8367C_IPMC_GROUP_VID_42_OFFSET 0 +#define RTL8367C_IPMC_GROUP_VID_42_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_VID_43 0x0edb +#define RTL8367C_IPMC_GROUP_VID_43_OFFSET 0 +#define RTL8367C_IPMC_GROUP_VID_43_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_VID_44 0x0edc +#define RTL8367C_IPMC_GROUP_VID_44_OFFSET 0 +#define RTL8367C_IPMC_GROUP_VID_44_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_VID_45 0x0edd +#define RTL8367C_IPMC_GROUP_VID_45_OFFSET 0 +#define RTL8367C_IPMC_GROUP_VID_45_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_VID_46 0x0ede +#define RTL8367C_IPMC_GROUP_VID_46_OFFSET 0 +#define RTL8367C_IPMC_GROUP_VID_46_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_VID_47 0x0edf +#define RTL8367C_IPMC_GROUP_VID_47_OFFSET 0 +#define RTL8367C_IPMC_GROUP_VID_47_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_VID_48 0x0ef0 +#define RTL8367C_IPMC_GROUP_VID_48_OFFSET 0 +#define RTL8367C_IPMC_GROUP_VID_48_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_VID_49 0x0ef1 +#define RTL8367C_IPMC_GROUP_VID_49_OFFSET 0 +#define RTL8367C_IPMC_GROUP_VID_49_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_VID_50 0x0ef2 +#define RTL8367C_IPMC_GROUP_VID_50_OFFSET 0 +#define RTL8367C_IPMC_GROUP_VID_50_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_VID_51 0x0ef3 +#define RTL8367C_IPMC_GROUP_VID_51_OFFSET 0 +#define RTL8367C_IPMC_GROUP_VID_51_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_VID_52 0x0ef4 +#define RTL8367C_IPMC_GROUP_VID_52_OFFSET 0 +#define RTL8367C_IPMC_GROUP_VID_52_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_VID_53 0x0ef5 +#define RTL8367C_IPMC_GROUP_VID_53_OFFSET 0 +#define RTL8367C_IPMC_GROUP_VID_53_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_VID_54 0x0ef6 +#define RTL8367C_IPMC_GROUP_VID_54_OFFSET 0 +#define RTL8367C_IPMC_GROUP_VID_54_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_VID_55 0x0ef7 +#define RTL8367C_IPMC_GROUP_VID_55_OFFSET 0 +#define RTL8367C_IPMC_GROUP_VID_55_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_VID_56 0x0ef8 +#define RTL8367C_IPMC_GROUP_VID_56_OFFSET 0 +#define RTL8367C_IPMC_GROUP_VID_56_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_VID_57 0x0ef9 +#define RTL8367C_IPMC_GROUP_VID_57_OFFSET 0 +#define RTL8367C_IPMC_GROUP_VID_57_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_VID_58 0x0efa +#define RTL8367C_IPMC_GROUP_VID_58_OFFSET 0 +#define RTL8367C_IPMC_GROUP_VID_58_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_VID_59 0x0efb +#define RTL8367C_IPMC_GROUP_VID_59_OFFSET 0 +#define RTL8367C_IPMC_GROUP_VID_59_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_VID_60 0x0efc +#define RTL8367C_IPMC_GROUP_VID_60_OFFSET 0 +#define RTL8367C_IPMC_GROUP_VID_60_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_VID_61 0x0efd +#define RTL8367C_IPMC_GROUP_VID_61_OFFSET 0 +#define RTL8367C_IPMC_GROUP_VID_61_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_VID_62 0x0efe +#define RTL8367C_IPMC_GROUP_VID_62_OFFSET 0 +#define RTL8367C_IPMC_GROUP_VID_62_MASK 0xFFF + +#define RTL8367C_REG_IPMC_GROUP_VID_63 0x0eff +#define RTL8367C_IPMC_GROUP_VID_63_OFFSET 0 +#define RTL8367C_IPMC_GROUP_VID_63_MASK 0xFFF + +/* (16'h0f00)hsactrl_reg */ + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY0_CTRL0 0x0f00 +#define RTL8367C_SVLAN_SP2C_ENTRY0_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY0_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY0_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY0_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY0_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY0_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY0_CTRL1 0x0f01 +#define RTL8367C_SVLAN_SP2C_ENTRY0_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY0_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY0_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY0_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY1_CTRL0 0x0f02 +#define RTL8367C_SVLAN_SP2C_ENTRY1_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY1_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY1_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY1_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY1_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY1_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY1_CTRL1 0x0f03 +#define RTL8367C_SVLAN_SP2C_ENTRY1_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY1_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY1_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY1_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY2_CTRL0 0x0f04 +#define RTL8367C_SVLAN_SP2C_ENTRY2_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY2_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY2_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY2_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY2_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY2_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY2_CTRL1 0x0f05 +#define RTL8367C_SVLAN_SP2C_ENTRY2_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY2_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY2_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY2_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY3_CTRL0 0x0f06 +#define RTL8367C_SVLAN_SP2C_ENTRY3_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY3_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY3_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY3_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY3_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY3_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY3_CTRL1 0x0f07 +#define RTL8367C_SVLAN_SP2C_ENTRY3_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY3_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY3_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY3_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY4_CTRL0 0x0f08 +#define RTL8367C_SVLAN_SP2C_ENTRY4_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY4_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY4_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY4_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY4_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY4_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY4_CTRL1 0x0f09 +#define RTL8367C_SVLAN_SP2C_ENTRY4_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY4_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY4_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY4_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY5_CTRL0 0x0f0a +#define RTL8367C_SVLAN_SP2C_ENTRY5_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY5_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY5_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY5_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY5_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY5_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY5_CTRL1 0x0f0b +#define RTL8367C_SVLAN_SP2C_ENTRY5_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY5_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY5_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY5_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY6_CTRL0 0x0f0c +#define RTL8367C_SVLAN_SP2C_ENTRY6_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY6_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY6_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY6_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY6_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY6_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY6_CTRL1 0x0f0d +#define RTL8367C_SVLAN_SP2C_ENTRY6_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY6_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY6_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY6_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY7_CTRL0 0x0f0e +#define RTL8367C_SVLAN_SP2C_ENTRY7_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY7_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY7_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY7_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY7_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY7_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY7_CTRL1 0x0f0f +#define RTL8367C_SVLAN_SP2C_ENTRY7_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY7_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY7_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY7_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY8_CTRL0 0x0f10 +#define RTL8367C_SVLAN_SP2C_ENTRY8_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY8_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY8_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY8_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY8_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY8_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY8_CTRL1 0x0f11 +#define RTL8367C_SVLAN_SP2C_ENTRY8_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY8_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY8_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY8_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY9_CTRL0 0x0f12 +#define RTL8367C_SVLAN_SP2C_ENTRY9_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY9_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY9_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY9_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY9_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY9_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY9_CTRL1 0x0f13 +#define RTL8367C_SVLAN_SP2C_ENTRY9_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY9_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY9_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY9_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY10_CTRL0 0x0f14 +#define RTL8367C_SVLAN_SP2C_ENTRY10_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY10_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY10_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY10_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY10_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY10_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY10_CTRL1 0x0f15 +#define RTL8367C_SVLAN_SP2C_ENTRY10_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY10_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY10_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY10_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY11_CTRL0 0x0f16 +#define RTL8367C_SVLAN_SP2C_ENTRY11_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY11_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY11_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY11_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY11_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY11_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY11_CTRL1 0x0f17 +#define RTL8367C_SVLAN_SP2C_ENTRY11_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY11_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY11_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY11_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY12_CTRL0 0x0f18 +#define RTL8367C_SVLAN_SP2C_ENTRY12_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY12_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY12_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY12_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY12_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY12_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY12_CTRL1 0x0f19 +#define RTL8367C_SVLAN_SP2C_ENTRY12_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY12_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY12_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY12_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY13_CTRL0 0x0f1a +#define RTL8367C_SVLAN_SP2C_ENTRY13_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY13_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY13_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY13_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY13_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY13_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY13_CTRL1 0x0f1b +#define RTL8367C_SVLAN_SP2C_ENTRY13_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY13_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY13_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY13_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY14_CTRL0 0x0f1c +#define RTL8367C_SVLAN_SP2C_ENTRY14_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY14_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY14_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY14_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY14_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY14_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY14_CTRL1 0x0f1d +#define RTL8367C_SVLAN_SP2C_ENTRY14_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY14_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY14_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY14_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY15_CTRL0 0x0f1e +#define RTL8367C_SVLAN_SP2C_ENTRY15_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY15_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY15_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY15_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY15_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY15_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY15_CTRL1 0x0f1f +#define RTL8367C_SVLAN_SP2C_ENTRY15_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY15_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY15_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY15_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY16_CTRL0 0x0f20 +#define RTL8367C_SVLAN_SP2C_ENTRY16_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY16_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY16_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY16_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY16_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY16_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY16_CTRL1 0x0f21 +#define RTL8367C_SVLAN_SP2C_ENTRY16_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY16_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY16_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY16_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY17_CTRL0 0x0f22 +#define RTL8367C_SVLAN_SP2C_ENTRY17_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY17_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY17_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY17_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY17_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY17_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY17_CTRL1 0x0f23 +#define RTL8367C_SVLAN_SP2C_ENTRY17_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY17_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY17_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY17_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY18_CTRL0 0x0f24 +#define RTL8367C_SVLAN_SP2C_ENTRY18_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY18_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY18_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY18_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY18_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY18_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY18_CTRL1 0x0f25 +#define RTL8367C_SVLAN_SP2C_ENTRY18_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY18_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY18_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY18_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY19_CTRL0 0x0f26 +#define RTL8367C_SVLAN_SP2C_ENTRY19_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY19_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY19_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY19_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY19_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY19_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY19_CTRL1 0x0f27 +#define RTL8367C_SVLAN_SP2C_ENTRY19_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY19_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY19_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY19_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY20_CTRL0 0x0f28 +#define RTL8367C_SVLAN_SP2C_ENTRY20_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY20_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY20_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY20_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY20_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY20_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY20_CTRL1 0x0f29 +#define RTL8367C_SVLAN_SP2C_ENTRY20_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY20_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY20_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY20_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY21_CTRL0 0x0f2a +#define RTL8367C_SVLAN_SP2C_ENTRY21_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY21_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY21_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY21_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY21_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY21_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY21_CTRL1 0x0f2b +#define RTL8367C_SVLAN_SP2C_ENTRY21_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY21_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY21_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY21_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY22_CTRL0 0x0f2c +#define RTL8367C_SVLAN_SP2C_ENTRY22_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY22_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY22_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY22_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY22_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY22_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY22_CTRL1 0x0f2d +#define RTL8367C_SVLAN_SP2C_ENTRY22_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY22_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY22_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY22_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY23_CTRL0 0x0f2e +#define RTL8367C_SVLAN_SP2C_ENTRY23_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY23_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY23_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY23_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY23_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY23_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY23_CTRL1 0x0f2f +#define RTL8367C_SVLAN_SP2C_ENTRY23_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY23_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY23_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY23_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY24_CTRL0 0x0f30 +#define RTL8367C_SVLAN_SP2C_ENTRY24_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY24_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY24_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY24_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY24_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY24_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY24_CTRL1 0x0f31 +#define RTL8367C_SVLAN_SP2C_ENTRY24_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY24_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY24_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY24_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY25_CTRL0 0x0f32 +#define RTL8367C_SVLAN_SP2C_ENTRY25_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY25_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY25_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY25_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY25_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY25_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY25_CTRL1 0x0f33 +#define RTL8367C_SVLAN_SP2C_ENTRY25_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY25_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY25_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY25_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY26_CTRL0 0x0f34 +#define RTL8367C_SVLAN_SP2C_ENTRY26_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY26_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY26_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY26_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY26_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY26_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY26_CTRL1 0x0f35 +#define RTL8367C_SVLAN_SP2C_ENTRY26_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY26_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY26_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY26_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY27_CTRL0 0x0f36 +#define RTL8367C_SVLAN_SP2C_ENTRY27_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY27_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY27_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY27_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY27_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY27_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY27_CTRL1 0x0f37 +#define RTL8367C_SVLAN_SP2C_ENTRY27_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY27_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY27_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY27_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY28_CTRL0 0x0f38 +#define RTL8367C_SVLAN_SP2C_ENTRY28_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY28_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY28_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY28_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY28_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY28_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY28_CTRL1 0x0f39 +#define RTL8367C_SVLAN_SP2C_ENTRY28_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY28_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY28_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY28_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY29_CTRL0 0x0f3a +#define RTL8367C_SVLAN_SP2C_ENTRY29_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY29_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY29_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY29_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY29_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY29_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY29_CTRL1 0x0f3b +#define RTL8367C_SVLAN_SP2C_ENTRY29_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY29_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY29_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY29_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY30_CTRL0 0x0f3c +#define RTL8367C_SVLAN_SP2C_ENTRY30_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY30_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY30_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY30_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY30_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY30_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY30_CTRL1 0x0f3d +#define RTL8367C_SVLAN_SP2C_ENTRY30_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY30_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY30_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY30_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY31_CTRL0 0x0f3e +#define RTL8367C_SVLAN_SP2C_ENTRY31_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY31_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY31_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY31_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY31_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY31_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY31_CTRL1 0x0f3f +#define RTL8367C_SVLAN_SP2C_ENTRY31_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY31_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY31_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY31_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY32_CTRL0 0x0f40 +#define RTL8367C_SVLAN_SP2C_ENTRY32_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY32_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY32_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY32_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY32_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY32_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY32_CTRL1 0x0f41 +#define RTL8367C_SVLAN_SP2C_ENTRY32_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY32_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY32_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY32_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY33_CTRL0 0x0f42 +#define RTL8367C_SVLAN_SP2C_ENTRY33_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY33_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY33_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY33_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY33_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY33_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY33_CTRL1 0x0f43 +#define RTL8367C_SVLAN_SP2C_ENTRY33_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY33_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY33_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY33_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY34_CTRL0 0x0f44 +#define RTL8367C_SVLAN_SP2C_ENTRY34_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY34_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY34_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY34_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY34_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY34_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY34_CTRL1 0x0f45 +#define RTL8367C_SVLAN_SP2C_ENTRY34_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY34_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY34_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY34_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY35_CTRL0 0x0f46 +#define RTL8367C_SVLAN_SP2C_ENTRY35_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY35_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY35_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY35_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY35_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY35_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY35_CTRL1 0x0f47 +#define RTL8367C_SVLAN_SP2C_ENTRY35_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY35_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY35_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY35_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY36_CTRL0 0x0f48 +#define RTL8367C_SVLAN_SP2C_ENTRY36_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY36_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY36_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY36_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY36_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY36_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY36_CTRL1 0x0f49 +#define RTL8367C_SVLAN_SP2C_ENTRY36_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY36_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY36_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY36_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY37_CTRL0 0x0f4a +#define RTL8367C_SVLAN_SP2C_ENTRY37_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY37_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY37_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY37_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY37_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY37_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY37_CTRL1 0x0f4b +#define RTL8367C_SVLAN_SP2C_ENTRY37_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY37_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY37_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY37_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY38_CTRL0 0x0f4c +#define RTL8367C_SVLAN_SP2C_ENTRY38_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY38_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY38_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY38_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY38_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY38_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY38_CTRL1 0x0f4d +#define RTL8367C_SVLAN_SP2C_ENTRY38_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY38_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY38_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY38_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY39_CTRL0 0x0f4e +#define RTL8367C_SVLAN_SP2C_ENTRY39_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY39_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY39_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY39_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY39_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY39_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY39_CTRL1 0x0f4f +#define RTL8367C_SVLAN_SP2C_ENTRY39_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY39_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY39_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY39_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY40_CTRL0 0x0f50 +#define RTL8367C_SVLAN_SP2C_ENTRY40_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY40_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY40_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY40_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY40_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY40_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY40_CTRL1 0x0f51 +#define RTL8367C_SVLAN_SP2C_ENTRY40_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY40_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY40_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY40_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY41_CTRL0 0x0f52 +#define RTL8367C_SVLAN_SP2C_ENTRY41_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY41_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY41_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY41_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY41_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY41_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY41_CTRL1 0x0f53 +#define RTL8367C_SVLAN_SP2C_ENTRY41_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY41_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY41_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY41_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY42_CTRL0 0x0f54 +#define RTL8367C_SVLAN_SP2C_ENTRY42_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY42_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY42_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY42_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY42_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY42_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY42_CTRL1 0x0f55 +#define RTL8367C_SVLAN_SP2C_ENTRY42_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY42_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY42_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY42_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY43_CTRL0 0x0f56 +#define RTL8367C_SVLAN_SP2C_ENTRY43_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY43_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY43_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY43_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY43_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY43_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY43_CTRL1 0x0f57 +#define RTL8367C_SVLAN_SP2C_ENTRY43_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY43_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY43_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY43_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY44_CTRL0 0x0f58 +#define RTL8367C_SVLAN_SP2C_ENTRY44_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY44_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY44_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY44_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY44_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY44_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY44_CTRL1 0x0f59 +#define RTL8367C_SVLAN_SP2C_ENTRY44_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY44_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY44_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY44_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY45_CTRL0 0x0f5a +#define RTL8367C_SVLAN_SP2C_ENTRY45_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY45_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY45_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY45_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY45_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY45_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY45_CTRL1 0x0f5b +#define RTL8367C_SVLAN_SP2C_ENTRY45_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY45_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY45_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY45_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY46_CTRL0 0x0f5c +#define RTL8367C_SVLAN_SP2C_ENTRY46_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY46_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY46_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY46_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY46_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY46_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY46_CTRL1 0x0f5d +#define RTL8367C_SVLAN_SP2C_ENTRY46_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY46_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY46_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY46_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY47_CTRL0 0x0f5e +#define RTL8367C_SVLAN_SP2C_ENTRY47_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY47_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY47_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY47_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY47_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY47_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY47_CTRL1 0x0f5f +#define RTL8367C_SVLAN_SP2C_ENTRY47_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY47_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY47_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY47_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY48_CTRL0 0x0f60 +#define RTL8367C_SVLAN_SP2C_ENTRY48_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY48_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY48_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY48_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY48_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY48_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY48_CTRL1 0x0f61 +#define RTL8367C_SVLAN_SP2C_ENTRY48_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY48_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY48_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY48_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY49_CTRL0 0x0f62 +#define RTL8367C_SVLAN_SP2C_ENTRY49_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY49_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY49_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY49_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY49_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY49_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY49_CTRL1 0x0f63 +#define RTL8367C_SVLAN_SP2C_ENTRY49_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY49_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY49_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY49_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY50_CTRL0 0x0f64 +#define RTL8367C_SVLAN_SP2C_ENTRY50_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY50_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY50_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY50_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY50_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY50_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY50_CTRL1 0x0f65 +#define RTL8367C_SVLAN_SP2C_ENTRY50_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY50_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY50_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY50_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY51_CTRL0 0x0f66 +#define RTL8367C_SVLAN_SP2C_ENTRY51_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY51_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY51_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY51_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY51_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY51_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY51_CTRL1 0x0f67 +#define RTL8367C_SVLAN_SP2C_ENTRY51_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY51_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY51_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY51_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY52_CTRL0 0x0f68 +#define RTL8367C_SVLAN_SP2C_ENTRY52_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY52_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY52_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY52_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY52_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY52_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY52_CTRL1 0x0f69 +#define RTL8367C_SVLAN_SP2C_ENTRY52_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY52_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY52_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY52_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY53_CTRL0 0x0f6a +#define RTL8367C_SVLAN_SP2C_ENTRY53_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY53_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY53_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY53_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY53_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY53_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY53_CTRL1 0x0f6b +#define RTL8367C_SVLAN_SP2C_ENTRY53_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY53_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY53_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY53_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY54_CTRL0 0x0f6c +#define RTL8367C_SVLAN_SP2C_ENTRY54_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY54_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY54_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY54_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY54_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY54_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY54_CTRL1 0x0f6d +#define RTL8367C_SVLAN_SP2C_ENTRY54_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY54_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY54_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY54_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY55_CTRL0 0x0f6e +#define RTL8367C_SVLAN_SP2C_ENTRY55_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY55_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY55_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY55_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY55_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY55_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY55_CTRL1 0x0f6f +#define RTL8367C_SVLAN_SP2C_ENTRY55_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY55_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY55_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY55_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY56_CTRL0 0x0f70 +#define RTL8367C_SVLAN_SP2C_ENTRY56_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY56_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY56_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY56_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY56_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY56_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY56_CTRL1 0x0f71 +#define RTL8367C_SVLAN_SP2C_ENTRY56_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY56_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY56_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY56_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY57_CTRL0 0x0f72 +#define RTL8367C_SVLAN_SP2C_ENTRY57_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY57_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY57_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY57_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY57_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY57_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY57_CTRL1 0x0f73 +#define RTL8367C_SVLAN_SP2C_ENTRY57_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY57_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY57_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY57_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY58_CTRL0 0x0f74 +#define RTL8367C_SVLAN_SP2C_ENTRY58_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY58_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY58_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY58_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY58_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY58_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY58_CTRL1 0x0f75 +#define RTL8367C_SVLAN_SP2C_ENTRY58_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY58_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY58_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY58_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY59_CTRL0 0x0f76 +#define RTL8367C_SVLAN_SP2C_ENTRY59_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY59_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY59_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY59_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY59_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY59_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY59_CTRL1 0x0f77 +#define RTL8367C_SVLAN_SP2C_ENTRY59_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY59_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY59_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY59_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY60_CTRL0 0x0f78 +#define RTL8367C_SVLAN_SP2C_ENTRY60_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY60_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY60_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY60_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY60_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY60_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY60_CTRL1 0x0f79 +#define RTL8367C_SVLAN_SP2C_ENTRY60_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY60_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY60_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY60_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY61_CTRL0 0x0f7a +#define RTL8367C_SVLAN_SP2C_ENTRY61_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY61_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY61_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY61_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY61_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY61_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY61_CTRL1 0x0f7b +#define RTL8367C_SVLAN_SP2C_ENTRY61_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY61_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY61_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY61_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY62_CTRL0 0x0f7c +#define RTL8367C_SVLAN_SP2C_ENTRY62_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY62_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY62_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY62_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY62_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY62_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY62_CTRL1 0x0f7d +#define RTL8367C_SVLAN_SP2C_ENTRY62_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY62_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY62_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY62_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY63_CTRL0 0x0f7e +#define RTL8367C_SVLAN_SP2C_ENTRY63_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY63_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY63_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY63_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY63_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY63_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY63_CTRL1 0x0f7f +#define RTL8367C_SVLAN_SP2C_ENTRY63_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY63_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY63_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY63_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY64_CTRL0 0x0f80 +#define RTL8367C_SVLAN_SP2C_ENTRY64_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY64_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY64_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY64_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY64_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY64_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY64_CTRL1 0x0f81 +#define RTL8367C_SVLAN_SP2C_ENTRY64_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY64_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY64_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY64_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY65_CTRL0 0x0f82 +#define RTL8367C_SVLAN_SP2C_ENTRY65_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY65_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY65_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY65_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY65_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY65_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY65_CTRL1 0x0f83 +#define RTL8367C_SVLAN_SP2C_ENTRY65_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY65_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY65_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY65_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY66_CTRL0 0x0f84 +#define RTL8367C_SVLAN_SP2C_ENTRY66_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY66_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY66_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY66_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY66_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY66_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY66_CTRL1 0x0f85 +#define RTL8367C_SVLAN_SP2C_ENTRY66_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY66_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY66_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY66_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY67_CTRL0 0x0f86 +#define RTL8367C_SVLAN_SP2C_ENTRY67_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY67_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY67_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY67_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY67_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY67_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY67_CTRL1 0x0f87 +#define RTL8367C_SVLAN_SP2C_ENTRY67_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY67_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY67_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY67_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY68_CTRL0 0x0f88 +#define RTL8367C_SVLAN_SP2C_ENTRY68_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY68_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY68_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY68_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY68_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY68_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY68_CTRL1 0x0f89 +#define RTL8367C_SVLAN_SP2C_ENTRY68_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY68_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY68_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY68_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY69_CTRL0 0x0f8a +#define RTL8367C_SVLAN_SP2C_ENTRY69_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY69_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY69_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY69_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY69_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY69_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY69_CTRL1 0x0f8b +#define RTL8367C_SVLAN_SP2C_ENTRY69_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY69_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY69_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY69_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY70_CTRL0 0x0f8c +#define RTL8367C_SVLAN_SP2C_ENTRY70_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY70_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY70_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY70_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY70_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY70_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY70_CTRL1 0x0f8d +#define RTL8367C_SVLAN_SP2C_ENTRY70_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY70_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY70_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY70_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY71_CTRL0 0x0f8e +#define RTL8367C_SVLAN_SP2C_ENTRY71_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY71_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY71_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY71_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY71_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY71_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY71_CTRL1 0x0f8f +#define RTL8367C_SVLAN_SP2C_ENTRY71_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY71_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY71_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY71_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY72_CTRL0 0x0f90 +#define RTL8367C_SVLAN_SP2C_ENTRY72_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY72_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY72_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY72_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY72_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY72_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY72_CTRL1 0x0f91 +#define RTL8367C_SVLAN_SP2C_ENTRY72_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY72_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY72_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY72_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY73_CTRL0 0x0f92 +#define RTL8367C_SVLAN_SP2C_ENTRY73_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY73_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY73_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY73_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY73_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY73_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY73_CTRL1 0x0f93 +#define RTL8367C_SVLAN_SP2C_ENTRY73_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY73_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY73_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY73_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY74_CTRL0 0x0f94 +#define RTL8367C_SVLAN_SP2C_ENTRY74_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY74_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY74_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY74_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY74_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY74_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY74_CTRL1 0x0f95 +#define RTL8367C_SVLAN_SP2C_ENTRY74_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY74_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY74_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY74_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY75_CTRL0 0x0f96 +#define RTL8367C_SVLAN_SP2C_ENTRY75_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY75_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY75_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY75_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY75_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY75_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY75_CTRL1 0x0f97 +#define RTL8367C_SVLAN_SP2C_ENTRY75_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY75_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY75_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY75_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY76_CTRL0 0x0f98 +#define RTL8367C_SVLAN_SP2C_ENTRY76_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY76_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY76_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY76_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY76_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY76_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY76_CTRL1 0x0f99 +#define RTL8367C_SVLAN_SP2C_ENTRY76_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY76_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY76_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY76_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY77_CTRL0 0x0f9a +#define RTL8367C_SVLAN_SP2C_ENTRY77_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY77_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY77_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY77_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY77_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY77_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY77_CTRL1 0x0f9b +#define RTL8367C_SVLAN_SP2C_ENTRY77_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY77_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY77_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY77_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY78_CTRL0 0x0f9c +#define RTL8367C_SVLAN_SP2C_ENTRY78_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY78_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY78_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY78_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY78_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY78_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY78_CTRL1 0x0f9d +#define RTL8367C_SVLAN_SP2C_ENTRY78_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY78_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY78_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY78_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY79_CTRL0 0x0f9e +#define RTL8367C_SVLAN_SP2C_ENTRY79_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY79_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY79_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY79_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY79_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY79_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY79_CTRL1 0x0f9f +#define RTL8367C_SVLAN_SP2C_ENTRY79_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY79_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY79_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY79_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY80_CTRL0 0x0fa0 +#define RTL8367C_SVLAN_SP2C_ENTRY80_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY80_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY80_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY80_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY80_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY80_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY80_CTRL1 0x0fa1 +#define RTL8367C_SVLAN_SP2C_ENTRY80_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY80_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY80_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY80_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY81_CTRL0 0x0fa2 +#define RTL8367C_SVLAN_SP2C_ENTRY81_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY81_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY81_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY81_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY81_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY81_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY81_CTRL1 0x0fa3 +#define RTL8367C_SVLAN_SP2C_ENTRY81_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY81_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY81_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY81_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY82_CTRL0 0x0fa4 +#define RTL8367C_SVLAN_SP2C_ENTRY82_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY82_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY82_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY82_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY82_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY82_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY82_CTRL1 0x0fa5 +#define RTL8367C_SVLAN_SP2C_ENTRY82_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY82_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY82_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY82_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY83_CTRL0 0x0fa6 +#define RTL8367C_SVLAN_SP2C_ENTRY83_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY83_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY83_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY83_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY83_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY83_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY83_CTRL1 0x0fa7 +#define RTL8367C_SVLAN_SP2C_ENTRY83_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY83_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY83_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY83_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY84_CTRL0 0x0fa8 +#define RTL8367C_SVLAN_SP2C_ENTRY84_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY84_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY84_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY84_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY84_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY84_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY84_CTRL1 0x0fa9 +#define RTL8367C_SVLAN_SP2C_ENTRY84_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY84_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY84_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY84_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY85_CTRL0 0x0faa +#define RTL8367C_SVLAN_SP2C_ENTRY85_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY85_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY85_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY85_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY85_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY85_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY85_CTRL1 0x0fab +#define RTL8367C_SVLAN_SP2C_ENTRY85_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY85_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY85_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY85_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY86_CTRL0 0x0fac +#define RTL8367C_SVLAN_SP2C_ENTRY86_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY86_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY86_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY86_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY86_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY86_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY86_CTRL1 0x0fad +#define RTL8367C_SVLAN_SP2C_ENTRY86_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY86_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY86_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY86_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY87_CTRL0 0x0fae +#define RTL8367C_SVLAN_SP2C_ENTRY87_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY87_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY87_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY87_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY87_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY87_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY87_CTRL1 0x0faf +#define RTL8367C_SVLAN_SP2C_ENTRY87_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY87_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY87_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY87_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY88_CTRL0 0x0fb0 +#define RTL8367C_SVLAN_SP2C_ENTRY88_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY88_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY88_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY88_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY88_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY88_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY88_CTRL1 0x0fb1 +#define RTL8367C_SVLAN_SP2C_ENTRY88_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY88_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY88_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY88_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY89_CTRL0 0x0fb2 +#define RTL8367C_SVLAN_SP2C_ENTRY89_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY89_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY89_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY89_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY89_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY89_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY89_CTRL1 0x0fb3 +#define RTL8367C_SVLAN_SP2C_ENTRY89_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY89_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY89_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY89_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY90_CTRL0 0x0fb4 +#define RTL8367C_SVLAN_SP2C_ENTRY90_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY90_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY90_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY90_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY90_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY90_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY90_CTRL1 0x0fb5 +#define RTL8367C_SVLAN_SP2C_ENTRY90_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY90_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY90_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY90_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY91_CTRL0 0x0fb6 +#define RTL8367C_SVLAN_SP2C_ENTRY91_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY91_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY91_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY91_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY91_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY91_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY91_CTRL1 0x0fb7 +#define RTL8367C_SVLAN_SP2C_ENTRY91_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY91_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY91_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY91_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY92_CTRL0 0x0fb8 +#define RTL8367C_SVLAN_SP2C_ENTRY92_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY92_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY92_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY92_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY92_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY92_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY92_CTRL1 0x0fb9 +#define RTL8367C_SVLAN_SP2C_ENTRY92_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY92_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY92_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY92_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY93_CTRL0 0x0fba +#define RTL8367C_SVLAN_SP2C_ENTRY93_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY93_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY93_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY93_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY93_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY93_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY93_CTRL1 0x0fbb +#define RTL8367C_SVLAN_SP2C_ENTRY93_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY93_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY93_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY93_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY94_CTRL0 0x0fbc +#define RTL8367C_SVLAN_SP2C_ENTRY94_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY94_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY94_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY94_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY94_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY94_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY94_CTRL1 0x0fbd +#define RTL8367C_SVLAN_SP2C_ENTRY94_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY94_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY94_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY94_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY95_CTRL0 0x0fbe +#define RTL8367C_SVLAN_SP2C_ENTRY95_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY95_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY95_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY95_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY95_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY95_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY95_CTRL1 0x0fbf +#define RTL8367C_SVLAN_SP2C_ENTRY95_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY95_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY95_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY95_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY96_CTRL0 0x0fc0 +#define RTL8367C_SVLAN_SP2C_ENTRY96_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY96_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY96_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY96_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY96_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY96_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY96_CTRL1 0x0fc1 +#define RTL8367C_SVLAN_SP2C_ENTRY96_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY96_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY96_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY96_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY97_CTRL0 0x0fc2 +#define RTL8367C_SVLAN_SP2C_ENTRY97_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY97_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY97_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY97_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY97_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY97_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY97_CTRL1 0x0fc3 +#define RTL8367C_SVLAN_SP2C_ENTRY97_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY97_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY97_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY97_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY98_CTRL0 0x0fc4 +#define RTL8367C_SVLAN_SP2C_ENTRY98_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY98_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY98_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY98_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY98_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY98_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY98_CTRL1 0x0fc5 +#define RTL8367C_SVLAN_SP2C_ENTRY98_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY98_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY98_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY98_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY99_CTRL0 0x0fc6 +#define RTL8367C_SVLAN_SP2C_ENTRY99_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY99_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY99_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY99_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY99_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY99_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY99_CTRL1 0x0fc7 +#define RTL8367C_SVLAN_SP2C_ENTRY99_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY99_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY99_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY99_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY100_CTRL0 0x0fc8 +#define RTL8367C_SVLAN_SP2C_ENTRY100_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY100_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY100_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY100_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY100_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY100_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY100_CTRL1 0x0fc9 +#define RTL8367C_SVLAN_SP2C_ENTRY100_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY100_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY100_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY100_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY101_CTRL0 0x0fca +#define RTL8367C_SVLAN_SP2C_ENTRY101_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY101_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY101_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY101_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY101_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY101_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY101_CTRL1 0x0fcb +#define RTL8367C_SVLAN_SP2C_ENTRY101_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY101_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY101_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY101_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY102_CTRL0 0x0fcc +#define RTL8367C_SVLAN_SP2C_ENTRY102_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY102_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY102_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY102_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY102_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY102_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY102_CTRL1 0x0fcd +#define RTL8367C_SVLAN_SP2C_ENTRY102_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY102_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY102_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY102_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY103_CTRL0 0x0fce +#define RTL8367C_SVLAN_SP2C_ENTRY103_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY103_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY103_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY103_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY103_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY103_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY103_CTRL1 0x0fcf +#define RTL8367C_SVLAN_SP2C_ENTRY103_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY103_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY103_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY103_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY104_CTRL0 0x0fd0 +#define RTL8367C_SVLAN_SP2C_ENTRY104_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY104_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY104_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY104_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY104_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY104_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY104_CTRL1 0x0fd1 +#define RTL8367C_SVLAN_SP2C_ENTRY104_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY104_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY104_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY104_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY105_CTRL0 0x0fd2 +#define RTL8367C_SVLAN_SP2C_ENTRY105_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY105_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY105_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY105_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY105_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY105_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY105_CTRL1 0x0fd3 +#define RTL8367C_SVLAN_SP2C_ENTRY105_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY105_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY105_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY105_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY106_CTRL0 0x0fd4 +#define RTL8367C_SVLAN_SP2C_ENTRY106_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY106_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY106_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY106_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY106_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY106_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY106_CTRL1 0x0fd5 +#define RTL8367C_SVLAN_SP2C_ENTRY106_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY106_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY106_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY106_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY107_CTRL0 0x0fd6 +#define RTL8367C_SVLAN_SP2C_ENTRY107_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY107_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY107_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY107_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY107_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY107_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY107_CTRL1 0x0fd7 +#define RTL8367C_SVLAN_SP2C_ENTRY107_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY107_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY107_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY107_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY108_CTRL0 0x0fd8 +#define RTL8367C_SVLAN_SP2C_ENTRY108_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY108_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY108_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY108_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY108_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY108_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY108_CTRL1 0x0fd9 +#define RTL8367C_SVLAN_SP2C_ENTRY108_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY108_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY108_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY108_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY109_CTRL0 0x0fda +#define RTL8367C_SVLAN_SP2C_ENTRY109_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY109_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY109_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY109_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY109_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY109_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY109_CTRL1 0x0fdb +#define RTL8367C_SVLAN_SP2C_ENTRY109_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY109_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY109_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY109_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY110_CTRL0 0x0fdc +#define RTL8367C_SVLAN_SP2C_ENTRY110_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY110_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY110_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY110_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY110_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY110_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY110_CTRL1 0x0fdd +#define RTL8367C_SVLAN_SP2C_ENTRY110_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY110_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY110_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY110_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY111_CTRL0 0x0fde +#define RTL8367C_SVLAN_SP2C_ENTRY111_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY111_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY111_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY111_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY111_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY111_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY111_CTRL1 0x0fdf +#define RTL8367C_SVLAN_SP2C_ENTRY111_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY111_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY111_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY111_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY112_CTRL0 0x0fe0 +#define RTL8367C_SVLAN_SP2C_ENTRY112_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY112_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY112_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY112_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY112_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY112_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY112_CTRL1 0x0fe1 +#define RTL8367C_SVLAN_SP2C_ENTRY112_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY112_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY112_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY112_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY113_CTRL0 0x0fe2 +#define RTL8367C_SVLAN_SP2C_ENTRY113_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY113_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY113_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY113_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY113_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY113_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY113_CTRL1 0x0fe3 +#define RTL8367C_SVLAN_SP2C_ENTRY113_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY113_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY113_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY113_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY114_CTRL0 0x0fe4 +#define RTL8367C_SVLAN_SP2C_ENTRY114_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY114_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY114_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY114_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY114_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY114_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY114_CTRL1 0x0fe5 +#define RTL8367C_SVLAN_SP2C_ENTRY114_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY114_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY114_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY114_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY115_CTRL0 0x0fe6 +#define RTL8367C_SVLAN_SP2C_ENTRY115_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY115_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY115_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY115_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY115_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY115_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY115_CTRL1 0x0fe7 +#define RTL8367C_SVLAN_SP2C_ENTRY115_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY115_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY115_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY115_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY116_CTRL0 0x0fe8 +#define RTL8367C_SVLAN_SP2C_ENTRY116_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY116_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY116_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY116_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY116_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY116_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY116_CTRL1 0x0fe9 +#define RTL8367C_SVLAN_SP2C_ENTRY116_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY116_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY116_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY116_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY117_CTRL0 0x0fea +#define RTL8367C_SVLAN_SP2C_ENTRY117_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY117_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY117_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY117_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY117_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY117_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY117_CTRL1 0x0feb +#define RTL8367C_SVLAN_SP2C_ENTRY117_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY117_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY117_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY117_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY118_CTRL0 0x0fec +#define RTL8367C_SVLAN_SP2C_ENTRY118_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY118_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY118_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY118_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY118_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY118_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY118_CTRL1 0x0fed +#define RTL8367C_SVLAN_SP2C_ENTRY118_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY118_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY118_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY118_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY119_CTRL0 0x0fee +#define RTL8367C_SVLAN_SP2C_ENTRY119_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY119_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY119_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY119_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY119_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY119_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY119_CTRL1 0x0fef +#define RTL8367C_SVLAN_SP2C_ENTRY119_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY119_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY119_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY119_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY120_CTRL0 0x0ff0 +#define RTL8367C_SVLAN_SP2C_ENTRY120_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY120_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY120_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY120_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY120_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY120_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY120_CTRL1 0x0ff1 +#define RTL8367C_SVLAN_SP2C_ENTRY120_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY120_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY120_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY120_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY121_CTRL0 0x0ff2 +#define RTL8367C_SVLAN_SP2C_ENTRY121_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY121_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY121_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY121_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY121_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY121_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY121_CTRL1 0x0ff3 +#define RTL8367C_SVLAN_SP2C_ENTRY121_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY121_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY121_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY121_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY122_CTRL0 0x0ff4 +#define RTL8367C_SVLAN_SP2C_ENTRY122_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY122_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY122_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY122_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY122_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY122_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY122_CTRL1 0x0ff5 +#define RTL8367C_SVLAN_SP2C_ENTRY122_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY122_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY122_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY122_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY123_CTRL0 0x0ff6 +#define RTL8367C_SVLAN_SP2C_ENTRY123_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY123_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY123_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY123_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY123_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY123_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY123_CTRL1 0x0ff7 +#define RTL8367C_SVLAN_SP2C_ENTRY123_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY123_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY123_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY123_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY124_CTRL0 0x0ff8 +#define RTL8367C_SVLAN_SP2C_ENTRY124_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY124_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY124_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY124_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY124_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY124_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY124_CTRL1 0x0ff9 +#define RTL8367C_SVLAN_SP2C_ENTRY124_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY124_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY124_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY124_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY125_CTRL0 0x0ffa +#define RTL8367C_SVLAN_SP2C_ENTRY125_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY125_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY125_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY125_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY125_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY125_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY125_CTRL1 0x0ffb +#define RTL8367C_SVLAN_SP2C_ENTRY125_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY125_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY125_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY125_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY126_CTRL0 0x0ffc +#define RTL8367C_SVLAN_SP2C_ENTRY126_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY126_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY126_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY126_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY126_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY126_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY126_CTRL1 0x0ffd +#define RTL8367C_SVLAN_SP2C_ENTRY126_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY126_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY126_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY126_CTRL1_VID_MASK 0xFFF + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY127_CTRL0 0x0ffe +#define RTL8367C_SVLAN_SP2C_ENTRY127_CTRL0_DST_PORT1_OFFSET 9 +#define RTL8367C_SVLAN_SP2C_ENTRY127_CTRL0_DST_PORT1_MASK 0x200 +#define RTL8367C_SVLAN_SP2C_ENTRY127_CTRL0_SVIDX_OFFSET 3 +#define RTL8367C_SVLAN_SP2C_ENTRY127_CTRL0_SVIDX_MASK 0x1F8 +#define RTL8367C_SVLAN_SP2C_ENTRY127_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY127_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367C_REG_SVLAN_SP2C_ENTRY127_CTRL1 0x0fff +#define RTL8367C_SVLAN_SP2C_ENTRY127_CTRL1_VALID_OFFSET 12 +#define RTL8367C_SVLAN_SP2C_ENTRY127_CTRL1_VALID_MASK 0x1000 +#define RTL8367C_SVLAN_SP2C_ENTRY127_CTRL1_VID_OFFSET 0 +#define RTL8367C_SVLAN_SP2C_ENTRY127_CTRL1_VID_MASK 0xFFF + +/* (16'h1000)mib_reg */ + +#define RTL8367C_REG_MIB_COUNTER0 0x1000 + +#define RTL8367C_REG_MIB_COUNTER1 0x1001 + +#define RTL8367C_REG_MIB_COUNTER2 0x1002 + +#define RTL8367C_REG_MIB_COUNTER3 0x1003 + +#define RTL8367C_REG_MIB_ADDRESS 0x1004 +#define RTL8367C_MIB_ADDRESS_OFFSET 0 +#define RTL8367C_MIB_ADDRESS_MASK 0x1FF + +#define RTL8367C_REG_MIB_CTRL0 0x1005 +#define RTL8367C_PORT10_RESET_OFFSET 15 +#define RTL8367C_PORT10_RESET_MASK 0x8000 +#define RTL8367C_PORT9_RESET_OFFSET 14 +#define RTL8367C_PORT9_RESET_MASK 0x4000 +#define RTL8367C_PORT8_RESET_OFFSET 13 +#define RTL8367C_PORT8_RESET_MASK 0x2000 +#define RTL8367C_RESET_VALUE_OFFSET 12 +#define RTL8367C_RESET_VALUE_MASK 0x1000 +#define RTL8367C_GLOBAL_RESET_OFFSET 11 +#define RTL8367C_GLOBAL_RESET_MASK 0x800 +#define RTL8367C_QM_RESET_OFFSET 10 +#define RTL8367C_QM_RESET_MASK 0x400 +#define RTL8367C_PORT7_RESET_OFFSET 9 +#define RTL8367C_PORT7_RESET_MASK 0x200 +#define RTL8367C_PORT6_RESET_OFFSET 8 +#define RTL8367C_PORT6_RESET_MASK 0x100 +#define RTL8367C_PORT5_RESET_OFFSET 7 +#define RTL8367C_PORT5_RESET_MASK 0x80 +#define RTL8367C_PORT4_RESET_OFFSET 6 +#define RTL8367C_PORT4_RESET_MASK 0x40 +#define RTL8367C_PORT3_RESET_OFFSET 5 +#define RTL8367C_PORT3_RESET_MASK 0x20 +#define RTL8367C_PORT2_RESET_OFFSET 4 +#define RTL8367C_PORT2_RESET_MASK 0x10 +#define RTL8367C_PORT1_RESET_OFFSET 3 +#define RTL8367C_PORT1_RESET_MASK 0x8 +#define RTL8367C_PORT0_RESET_OFFSET 2 +#define RTL8367C_PORT0_RESET_MASK 0x4 +#define RTL8367C_RESET_FLAG_OFFSET 1 +#define RTL8367C_RESET_FLAG_MASK 0x2 +#define RTL8367C_MIB_CTRL0_BUSY_FLAG_OFFSET 0 +#define RTL8367C_MIB_CTRL0_BUSY_FLAG_MASK 0x1 + +#define RTL8367C_REG_MIB_CTRL1 0x1007 +#define RTL8367C_COUNTER15_RESET_OFFSET 15 +#define RTL8367C_COUNTER15_RESET_MASK 0x8000 +#define RTL8367C_COUNTER14_RESET_OFFSET 14 +#define RTL8367C_COUNTER14_RESET_MASK 0x4000 +#define RTL8367C_COUNTER13_RESET_OFFSET 13 +#define RTL8367C_COUNTER13_RESET_MASK 0x2000 +#define RTL8367C_COUNTER12_RESET_OFFSET 12 +#define RTL8367C_COUNTER12_RESET_MASK 0x1000 +#define RTL8367C_COUNTER11_RESET_OFFSET 11 +#define RTL8367C_COUNTER11_RESET_MASK 0x800 +#define RTL8367C_COUNTER10_RESET_OFFSET 10 +#define RTL8367C_COUNTER10_RESET_MASK 0x400 +#define RTL8367C_COUNTER9_RESET_OFFSET 9 +#define RTL8367C_COUNTER9_RESET_MASK 0x200 +#define RTL8367C_COUNTER8_RESET_OFFSET 8 +#define RTL8367C_COUNTER8_RESET_MASK 0x100 +#define RTL8367C_COUNTER7_RESET_OFFSET 7 +#define RTL8367C_COUNTER7_RESET_MASK 0x80 +#define RTL8367C_COUNTER6_RESET_OFFSET 6 +#define RTL8367C_COUNTER6_RESET_MASK 0x40 +#define RTL8367C_COUNTER5_RESET_OFFSET 5 +#define RTL8367C_COUNTER5_RESET_MASK 0x20 +#define RTL8367C_COUNTER4_RESET_OFFSET 4 +#define RTL8367C_COUNTER4_RESET_MASK 0x10 +#define RTL8367C_COUNTER3_RESET_OFFSET 3 +#define RTL8367C_COUNTER3_RESET_MASK 0x8 +#define RTL8367C_COUNTER2_RESET_OFFSET 2 +#define RTL8367C_COUNTER2_RESET_MASK 0x4 +#define RTL8367C_COUNTER1_RESET_OFFSET 1 +#define RTL8367C_COUNTER1_RESET_MASK 0x2 +#define RTL8367C_COUNTER0_RESET_OFFSET 0 +#define RTL8367C_COUNTER0_RESET_MASK 0x1 + +#define RTL8367C_REG_MIB_CTRL2 0x1008 +#define RTL8367C_COUNTER31_RESET_OFFSET 15 +#define RTL8367C_COUNTER31_RESET_MASK 0x8000 +#define RTL8367C_COUNTER30_RESET_OFFSET 14 +#define RTL8367C_COUNTER30_RESET_MASK 0x4000 +#define RTL8367C_COUNTER29_RESET_OFFSET 13 +#define RTL8367C_COUNTER29_RESET_MASK 0x2000 +#define RTL8367C_COUNTER28_RESET_OFFSET 12 +#define RTL8367C_COUNTER28_RESET_MASK 0x1000 +#define RTL8367C_COUNTER27_RESET_OFFSET 11 +#define RTL8367C_COUNTER27_RESET_MASK 0x800 +#define RTL8367C_COUNTER26_RESET_OFFSET 10 +#define RTL8367C_COUNTER26_RESET_MASK 0x400 +#define RTL8367C_COUNTER25_RESET_OFFSET 9 +#define RTL8367C_COUNTER25_RESET_MASK 0x200 +#define RTL8367C_COUNTER24_RESET_OFFSET 8 +#define RTL8367C_COUNTER24_RESET_MASK 0x100 +#define RTL8367C_COUNTER23_RESET_OFFSET 7 +#define RTL8367C_COUNTER23_RESET_MASK 0x80 +#define RTL8367C_COUNTER22_RESET_OFFSET 6 +#define RTL8367C_COUNTER22_RESET_MASK 0x40 +#define RTL8367C_COUNTER21_RESET_OFFSET 5 +#define RTL8367C_COUNTER21_RESET_MASK 0x20 +#define RTL8367C_COUNTER20_RESET_OFFSET 4 +#define RTL8367C_COUNTER20_RESET_MASK 0x10 +#define RTL8367C_COUNTER19_RESET_OFFSET 3 +#define RTL8367C_COUNTER19_RESET_MASK 0x8 +#define RTL8367C_COUNTER18_RESET_OFFSET 2 +#define RTL8367C_COUNTER18_RESET_MASK 0x4 +#define RTL8367C_COUNTER17_RESET_OFFSET 1 +#define RTL8367C_COUNTER17_RESET_MASK 0x2 +#define RTL8367C_COUNTER16_RESET_OFFSET 0 +#define RTL8367C_COUNTER16_RESET_MASK 0x1 + +#define RTL8367C_REG_MIB_CTRL3 0x1009 +#define RTL8367C_COUNTER15_MODE_OFFSET 15 +#define RTL8367C_COUNTER15_MODE_MASK 0x8000 +#define RTL8367C_COUNTER14_MODE_OFFSET 14 +#define RTL8367C_COUNTER14_MODE_MASK 0x4000 +#define RTL8367C_COUNTER13_MODE_OFFSET 13 +#define RTL8367C_COUNTER13_MODE_MASK 0x2000 +#define RTL8367C_COUNTER12_MODE_OFFSET 12 +#define RTL8367C_COUNTER12_MODE_MASK 0x1000 +#define RTL8367C_COUNTER11_MODE_OFFSET 11 +#define RTL8367C_COUNTER11_MODE_MASK 0x800 +#define RTL8367C_COUNTER10_MODE_OFFSET 10 +#define RTL8367C_COUNTER10_MODE_MASK 0x400 +#define RTL8367C_COUNTER9_MODE_OFFSET 9 +#define RTL8367C_COUNTER9_MODE_MASK 0x200 +#define RTL8367C_COUNTER8_MODE_OFFSET 8 +#define RTL8367C_COUNTER8_MODE_MASK 0x100 +#define RTL8367C_COUNTER7_MODE_OFFSET 7 +#define RTL8367C_COUNTER7_MODE_MASK 0x80 +#define RTL8367C_COUNTER6_MODE_OFFSET 6 +#define RTL8367C_COUNTER6_MODE_MASK 0x40 +#define RTL8367C_COUNTER5_MODE_OFFSET 5 +#define RTL8367C_COUNTER5_MODE_MASK 0x20 +#define RTL8367C_COUNTER4_MODE_OFFSET 4 +#define RTL8367C_COUNTER4_MODE_MASK 0x10 +#define RTL8367C_COUNTER3_MODE_OFFSET 3 +#define RTL8367C_COUNTER3_MODE_MASK 0x8 +#define RTL8367C_COUNTER2_MODE_OFFSET 2 +#define RTL8367C_COUNTER2_MODE_MASK 0x4 +#define RTL8367C_COUNTER1_MODE_OFFSET 1 +#define RTL8367C_COUNTER1_MODE_MASK 0x2 +#define RTL8367C_COUNTER0_MODE_OFFSET 0 +#define RTL8367C_COUNTER0_MODE_MASK 0x1 + +#define RTL8367C_REG_MIB_CTRL4 0x100a +#define RTL8367C_MIB_USAGE_MODE_OFFSET 8 +#define RTL8367C_MIB_USAGE_MODE_MASK 0x100 +#define RTL8367C_MIB_TIMER_OFFSET 0 +#define RTL8367C_MIB_TIMER_MASK 0xFF + +#define RTL8367C_REG_MIB_CTRL5 0x100b +#define RTL8367C_MIB_CTRL5_COUNTER15_TYPE_OFFSET 15 +#define RTL8367C_MIB_CTRL5_COUNTER15_TYPE_MASK 0x8000 +#define RTL8367C_MIB_CTRL5_COUNTER14_TYPE_OFFSET 14 +#define RTL8367C_MIB_CTRL5_COUNTER14_TYPE_MASK 0x4000 +#define RTL8367C_MIB_CTRL5_COUNTER13_TYPE_OFFSET 13 +#define RTL8367C_MIB_CTRL5_COUNTER13_TYPE_MASK 0x2000 +#define RTL8367C_MIB_CTRL5_COUNTER12_TYPE_OFFSET 12 +#define RTL8367C_MIB_CTRL5_COUNTER12_TYPE_MASK 0x1000 +#define RTL8367C_MIB_CTRL5_COUNTER11_TYPE_OFFSET 11 +#define RTL8367C_MIB_CTRL5_COUNTER11_TYPE_MASK 0x800 +#define RTL8367C_MIB_CTRL5_COUNTER10_TYPE_OFFSET 10 +#define RTL8367C_MIB_CTRL5_COUNTER10_TYPE_MASK 0x400 +#define RTL8367C_MIB_CTRL5_COUNTER9_TYPE_OFFSET 9 +#define RTL8367C_MIB_CTRL5_COUNTER9_TYPE_MASK 0x200 +#define RTL8367C_MIB_CTRL5_COUNTER8_TYPE_OFFSET 8 +#define RTL8367C_MIB_CTRL5_COUNTER8_TYPE_MASK 0x100 +#define RTL8367C_MIB_CTRL5_COUNTER7_TYPE_OFFSET 7 +#define RTL8367C_MIB_CTRL5_COUNTER7_TYPE_MASK 0x80 +#define RTL8367C_MIB_CTRL5_COUNTER6_TYPE_OFFSET 6 +#define RTL8367C_MIB_CTRL5_COUNTER6_TYPE_MASK 0x40 +#define RTL8367C_MIB_CTRL5_COUNTER5_TYPE_OFFSET 5 +#define RTL8367C_MIB_CTRL5_COUNTER5_TYPE_MASK 0x20 +#define RTL8367C_MIB_CTRL5_COUNTER4_TYPE_OFFSET 4 +#define RTL8367C_MIB_CTRL5_COUNTER4_TYPE_MASK 0x10 +#define RTL8367C_MIB_CTRL5_COUNTER3_TYPE_OFFSET 3 +#define RTL8367C_MIB_CTRL5_COUNTER3_TYPE_MASK 0x8 +#define RTL8367C_MIB_CTRL5_COUNTER2_TYPE_OFFSET 2 +#define RTL8367C_MIB_CTRL5_COUNTER2_TYPE_MASK 0x4 +#define RTL8367C_MIB_CTRL5_COUNTER1_TYPE_OFFSET 1 +#define RTL8367C_MIB_CTRL5_COUNTER1_TYPE_MASK 0x2 +#define RTL8367C_MIB_CTRL5_COUNTER0_TYPE_OFFSET 0 +#define RTL8367C_MIB_CTRL5_COUNTER0_TYPE_MASK 0x1 + +/* (16'h1100)intrpt_reg */ + +#define RTL8367C_REG_INTR_CTRL 0x1100 +#define RTL8367C_INTR_CTRL_OFFSET 0 +#define RTL8367C_INTR_CTRL_MASK 0x1 + +#define RTL8367C_REG_INTR_IMR 0x1101 +#define RTL8367C_INTR_IMR_SLIENT_START_2_OFFSET 12 +#define RTL8367C_INTR_IMR_SLIENT_START_2_MASK 0x1000 +#define RTL8367C_INTR_IMR_SLIENT_START_OFFSET 11 +#define RTL8367C_INTR_IMR_SLIENT_START_MASK 0x800 +#define RTL8367C_INTR_IMR_ACL_ACTION_OFFSET 9 +#define RTL8367C_INTR_IMR_ACL_ACTION_MASK 0x200 +#define RTL8367C_INTR_IMR_CABLE_DIAG_FIN_OFFSET 8 +#define RTL8367C_INTR_IMR_CABLE_DIAG_FIN_MASK 0x100 +#define RTL8367C_INTR_IMR_INTERRUPT_8051_OFFSET 7 +#define RTL8367C_INTR_IMR_INTERRUPT_8051_MASK 0x80 +#define RTL8367C_INTR_IMR_LOOP_DETECTION_OFFSET 6 +#define RTL8367C_INTR_IMR_LOOP_DETECTION_MASK 0x40 +#define RTL8367C_INTR_IMR_GREEN_TIMER_OFFSET 5 +#define RTL8367C_INTR_IMR_GREEN_TIMER_MASK 0x20 +#define RTL8367C_INTR_IMR_SPECIAL_CONGEST_OFFSET 4 +#define RTL8367C_INTR_IMR_SPECIAL_CONGEST_MASK 0x10 +#define RTL8367C_INTR_IMR_SPEED_CHANGE_OFFSET 3 +#define RTL8367C_INTR_IMR_SPEED_CHANGE_MASK 0x8 +#define RTL8367C_INTR_IMR_LEARN_OVER_OFFSET 2 +#define RTL8367C_INTR_IMR_LEARN_OVER_MASK 0x4 +#define RTL8367C_INTR_IMR_METER_EXCEEDED_OFFSET 1 +#define RTL8367C_INTR_IMR_METER_EXCEEDED_MASK 0x2 +#define RTL8367C_INTR_IMR_LINK_CHANGE_OFFSET 0 +#define RTL8367C_INTR_IMR_LINK_CHANGE_MASK 0x1 + +#define RTL8367C_REG_INTR_IMS 0x1102 +#define RTL8367C_INTR_IMS_SLIENT_START_2_OFFSET 12 +#define RTL8367C_INTR_IMS_SLIENT_START_2_MASK 0x1000 +#define RTL8367C_INTR_IMS_SLIENT_START_OFFSET 11 +#define RTL8367C_INTR_IMS_SLIENT_START_MASK 0x800 +#define RTL8367C_INTR_IMS_ACL_ACTION_OFFSET 9 +#define RTL8367C_INTR_IMS_ACL_ACTION_MASK 0x200 +#define RTL8367C_INTR_IMS_CABLE_DIAG_FIN_OFFSET 8 +#define RTL8367C_INTR_IMS_CABLE_DIAG_FIN_MASK 0x100 +#define RTL8367C_INTR_IMS_INTERRUPT_8051_OFFSET 7 +#define RTL8367C_INTR_IMS_INTERRUPT_8051_MASK 0x80 +#define RTL8367C_INTR_IMS_LOOP_DETECTION_OFFSET 6 +#define RTL8367C_INTR_IMS_LOOP_DETECTION_MASK 0x40 +#define RTL8367C_INTR_IMS_GREEN_TIMER_OFFSET 5 +#define RTL8367C_INTR_IMS_GREEN_TIMER_MASK 0x20 +#define RTL8367C_INTR_IMS_SPECIAL_CONGEST_OFFSET 4 +#define RTL8367C_INTR_IMS_SPECIAL_CONGEST_MASK 0x10 +#define RTL8367C_INTR_IMS_SPEED_CHANGE_OFFSET 3 +#define RTL8367C_INTR_IMS_SPEED_CHANGE_MASK 0x8 +#define RTL8367C_INTR_IMS_LEARN_OVER_OFFSET 2 +#define RTL8367C_INTR_IMS_LEARN_OVER_MASK 0x4 +#define RTL8367C_INTR_IMS_METER_EXCEEDED_OFFSET 1 +#define RTL8367C_INTR_IMS_METER_EXCEEDED_MASK 0x2 +#define RTL8367C_INTR_IMS_LINK_CHANGE_OFFSET 0 +#define RTL8367C_INTR_IMS_LINK_CHANGE_MASK 0x1 + +#define RTL8367C_REG_LEARN_OVER_INDICATOR 0x1103 +#define RTL8367C_LEARN_OVER_INDICATOR_OFFSET 0 +#define RTL8367C_LEARN_OVER_INDICATOR_MASK 0x7FF + +#define RTL8367C_REG_SPEED_CHANGE_INDICATOR 0x1104 +#define RTL8367C_SPEED_CHANGE_INDICATOR_OFFSET 0 +#define RTL8367C_SPEED_CHANGE_INDICATOR_MASK 0x7FF + +#define RTL8367C_REG_SPECIAL_CONGEST_INDICATOR 0x1105 +#define RTL8367C_SPECIAL_CONGEST_INDICATOR_OFFSET 0 +#define RTL8367C_SPECIAL_CONGEST_INDICATOR_MASK 0x7FF + +#define RTL8367C_REG_PORT_LINKDOWN_INDICATOR 0x1106 +#define RTL8367C_PORT_LINKDOWN_INDICATOR_OFFSET 0 +#define RTL8367C_PORT_LINKDOWN_INDICATOR_MASK 0x7FF + +#define RTL8367C_REG_PORT_LINKUP_INDICATOR 0x1107 +#define RTL8367C_PORT_LINKUP_INDICATOR_OFFSET 0 +#define RTL8367C_PORT_LINKUP_INDICATOR_MASK 0x7FF + +#define RTL8367C_REG_SYSTEM_LEARN_OVER_INDICATOR 0x1108 +#define RTL8367C_SYSTEM_LEARN_OVER_INDICATOR_OFFSET 0 +#define RTL8367C_SYSTEM_LEARN_OVER_INDICATOR_MASK 0x1 + +#define RTL8367C_REG_INTR_IMR_8051 0x1118 +#define RTL8367C_INTR_IMR_8051_SLIENT_START_2_OFFSET 13 +#define RTL8367C_INTR_IMR_8051_SLIENT_START_2_MASK 0x2000 +#define RTL8367C_INTR_IMR_8051_SLIENT_START_OFFSET 12 +#define RTL8367C_INTR_IMR_8051_SLIENT_START_MASK 0x1000 +#define RTL8367C_INTR_IMR_8051_ACL_ACTION_OFFSET 10 +#define RTL8367C_INTR_IMR_8051_ACL_ACTION_MASK 0x400 +#define RTL8367C_INTR_IMR_8051_SAMOVING_8051_OFFSET 9 +#define RTL8367C_INTR_IMR_8051_SAMOVING_8051_MASK 0x200 +#define RTL8367C_INTR_IMR_8051_CABLE_DIAG_FIN_8051_OFFSET 8 +#define RTL8367C_INTR_IMR_8051_CABLE_DIAG_FIN_8051_MASK 0x100 +#define RTL8367C_INTR_IMR_8051_EEELLDP_8051_OFFSET 7 +#define RTL8367C_INTR_IMR_8051_EEELLDP_8051_MASK 0x80 +#define RTL8367C_INTR_IMR_8051_LOOP_DETECTION_8051_OFFSET 6 +#define RTL8367C_INTR_IMR_8051_LOOP_DETECTION_8051_MASK 0x40 +#define RTL8367C_INTR_IMR_8051_GREEN_TIMER_8051_OFFSET 5 +#define RTL8367C_INTR_IMR_8051_GREEN_TIMER_8051_MASK 0x20 +#define RTL8367C_INTR_IMR_8051_SPECIAL_CONGEST_8051_OFFSET 4 +#define RTL8367C_INTR_IMR_8051_SPECIAL_CONGEST_8051_MASK 0x10 +#define RTL8367C_INTR_IMR_8051_SPEED_CHANGE_8051_OFFSET 3 +#define RTL8367C_INTR_IMR_8051_SPEED_CHANGE_8051_MASK 0x8 +#define RTL8367C_INTR_IMR_8051_LEARN_OVER_8051_OFFSET 2 +#define RTL8367C_INTR_IMR_8051_LEARN_OVER_8051_MASK 0x4 +#define RTL8367C_INTR_IMR_8051_METER_EXCEEDED_8051_OFFSET 1 +#define RTL8367C_INTR_IMR_8051_METER_EXCEEDED_8051_MASK 0x2 +#define RTL8367C_INTR_IMR_8051_LINK_CHANGE_8051_OFFSET 0 +#define RTL8367C_INTR_IMR_8051_LINK_CHANGE_8051_MASK 0x1 + +#define RTL8367C_REG_INTR_IMS_8051 0x1119 +#define RTL8367C_INTR_IMS_8051_SLIENT_START_2_OFFSET 13 +#define RTL8367C_INTR_IMS_8051_SLIENT_START_2_MASK 0x2000 +#define RTL8367C_INTR_IMS_8051_SLIENT_START_OFFSET 12 +#define RTL8367C_INTR_IMS_8051_SLIENT_START_MASK 0x1000 +#define RTL8367C_INTR_IMS_8051_ACL_ACTION_OFFSET 10 +#define RTL8367C_INTR_IMS_8051_ACL_ACTION_MASK 0x400 +#define RTL8367C_INTR_IMS_8051_SAMOVING_8051_OFFSET 9 +#define RTL8367C_INTR_IMS_8051_SAMOVING_8051_MASK 0x200 +#define RTL8367C_INTR_IMS_8051_CABLE_DIAG_FIN_8051_OFFSET 8 +#define RTL8367C_INTR_IMS_8051_CABLE_DIAG_FIN_8051_MASK 0x100 +#define RTL8367C_INTR_IMS_8051_EEELLDP_8051_OFFSET 7 +#define RTL8367C_INTR_IMS_8051_EEELLDP_8051_MASK 0x80 +#define RTL8367C_INTR_IMS_8051_LOOP_DETECTION_8051_OFFSET 6 +#define RTL8367C_INTR_IMS_8051_LOOP_DETECTION_8051_MASK 0x40 +#define RTL8367C_INTR_IMS_8051_GREEN_TIMER_8051_OFFSET 5 +#define RTL8367C_INTR_IMS_8051_GREEN_TIMER_8051_MASK 0x20 +#define RTL8367C_INTR_IMS_8051_SPECIAL_CONGEST_8051_OFFSET 4 +#define RTL8367C_INTR_IMS_8051_SPECIAL_CONGEST_8051_MASK 0x10 +#define RTL8367C_INTR_IMS_8051_SPEED_CHANGE_8051_OFFSET 3 +#define RTL8367C_INTR_IMS_8051_SPEED_CHANGE_8051_MASK 0x8 +#define RTL8367C_INTR_IMS_8051_LEARN_OVER_8051_OFFSET 2 +#define RTL8367C_INTR_IMS_8051_LEARN_OVER_8051_MASK 0x4 +#define RTL8367C_INTR_IMS_8051_METER_EXCEEDED_8051_OFFSET 1 +#define RTL8367C_INTR_IMS_8051_METER_EXCEEDED_8051_MASK 0x2 +#define RTL8367C_INTR_IMS_8051_LINK_CHANGE_8051_OFFSET 0 +#define RTL8367C_INTR_IMS_8051_LINK_CHANGE_8051_MASK 0x1 + +#define RTL8367C_REG_DW8051_INT_CPU 0x111a +#define RTL8367C_DW8051_INT_CPU_OFFSET 0 +#define RTL8367C_DW8051_INT_CPU_MASK 0x1 + +#define RTL8367C_REG_LEARN_OVER_INDICATOR_8051 0x1120 +#define RTL8367C_LEARN_OVER_INDICATOR_8051_OFFSET 0 +#define RTL8367C_LEARN_OVER_INDICATOR_8051_MASK 0x7FF + +#define RTL8367C_REG_SPEED_CHANGE_INDICATOR_8051 0x1121 +#define RTL8367C_SPEED_CHANGE_INDICATOR_8051_OFFSET 0 +#define RTL8367C_SPEED_CHANGE_INDICATOR_8051_MASK 0x7FF + +#define RTL8367C_REG_SPECIAL_CONGEST_INDICATOR_8051 0x1122 +#define RTL8367C_SPECIAL_CONGEST_INDICATOR_8051_OFFSET 0 +#define RTL8367C_SPECIAL_CONGEST_INDICATOR_8051_MASK 0x7FF + +#define RTL8367C_REG_PORT_LINKDOWN_INDICATOR_8051 0x1123 +#define RTL8367C_PORT_LINKDOWN_INDICATOR_8051_OFFSET 0 +#define RTL8367C_PORT_LINKDOWN_INDICATOR_8051_MASK 0x7FF + +#define RTL8367C_REG_PORT_LINKUP_INDICATOR_8051 0x1124 +#define RTL8367C_PORT_LINKUP_INDICATOR_8051_OFFSET 0 +#define RTL8367C_PORT_LINKUP_INDICATOR_8051_MASK 0x7FF + +#define RTL8367C_REG_DUMMY_1125 0x1125 + +#define RTL8367C_REG_DUMMY_1126 0x1126 + +#define RTL8367C_REG_DUMMY_1127 0x1127 + +#define RTL8367C_REG_DUMMY_1128 0x1128 + +#define RTL8367C_REG_DUMMY_1129 0x1129 + +#define RTL8367C_REG_INTR_IMS_BUFFER_RESET 0x112a +#define RTL8367C_INTR_IMS_BUFFER_RESET_IMR_BUFF_RESET_OFFSET 1 +#define RTL8367C_INTR_IMS_BUFFER_RESET_IMR_BUFF_RESET_MASK 0x2 +#define RTL8367C_INTR_IMS_BUFFER_RESET_BUFFER_RESET_OFFSET 0 +#define RTL8367C_INTR_IMS_BUFFER_RESET_BUFFER_RESET_MASK 0x1 + +#define RTL8367C_REG_INTR_IMS_8051_BUFFER_RESET 0x112b +#define RTL8367C_INTR_IMS_8051_BUFFER_RESET_IMR_BUFF_RESET_OFFSET 1 +#define RTL8367C_INTR_IMS_8051_BUFFER_RESET_IMR_BUFF_RESET_MASK 0x2 +#define RTL8367C_INTR_IMS_8051_BUFFER_RESET_BUFFER_RESET_OFFSET 0 +#define RTL8367C_INTR_IMS_8051_BUFFER_RESET_BUFFER_RESET_MASK 0x1 + +#define RTL8367C_REG_GPHY_INTRPT_8051 0x112c +#define RTL8367C_IMS_GPHY_8051_H_OFFSET 13 +#define RTL8367C_IMS_GPHY_8051_H_MASK 0xE000 +#define RTL8367C_IMR_GPHY_8051_H_OFFSET 10 +#define RTL8367C_IMR_GPHY_8051_H_MASK 0x1C00 +#define RTL8367C_IMS_GPHY_8051_OFFSET 5 +#define RTL8367C_IMS_GPHY_8051_MASK 0x3E0 +#define RTL8367C_IMR_GPHY_8051_OFFSET 0 +#define RTL8367C_IMR_GPHY_8051_MASK 0x1F + +#define RTL8367C_REG_GPHY_INTRPT 0x112d +#define RTL8367C_IMS_GPHY_H_OFFSET 13 +#define RTL8367C_IMS_GPHY_H_MASK 0xE000 +#define RTL8367C_IMR_GPHY_H_OFFSET 10 +#define RTL8367C_IMR_GPHY_H_MASK 0x1C00 +#define RTL8367C_IMS_GPHY_OFFSET 5 +#define RTL8367C_IMS_GPHY_MASK 0x3E0 +#define RTL8367C_IMR_GPHY_OFFSET 0 +#define RTL8367C_IMR_GPHY_MASK 0x1F + +#define RTL8367C_REG_THERMAL_INTRPT 0x112e +#define RTL8367C_IMS_TM_HIGH_OFFSET 3 +#define RTL8367C_IMS_TM_HIGH_MASK 0x8 +#define RTL8367C_IMR_TM_HIGH_OFFSET 2 +#define RTL8367C_IMR_TM_HIGH_MASK 0x4 +#define RTL8367C_IMS_TM_LOW_OFFSET 1 +#define RTL8367C_IMS_TM_LOW_MASK 0x2 +#define RTL8367C_IMR_TM_LOW_OFFSET 0 +#define RTL8367C_IMR_TM_LOW_MASK 0x1 + +#define RTL8367C_REG_THERMAL_INTRPT_8051 0x112f +#define RTL8367C_IMS_TM_HIGH_8051_OFFSET 3 +#define RTL8367C_IMS_TM_HIGH_8051_MASK 0x8 +#define RTL8367C_IMR_TM_HIGH_8051_OFFSET 2 +#define RTL8367C_IMR_TM_HIGH_8051_MASK 0x4 +#define RTL8367C_IMS_TM_LOW_8051_OFFSET 1 +#define RTL8367C_IMS_TM_LOW_8051_MASK 0x2 +#define RTL8367C_IMR_TM_LOW_8051_OFFSET 0 +#define RTL8367C_IMR_TM_LOW_8051_MASK 0x1 + +#define RTL8367C_REG_SDS_LINK_CHG_INT 0x1130 +#define RTL8367C_IMS_SDS_LINK_STS_C7_OFFSET 15 +#define RTL8367C_IMS_SDS_LINK_STS_C7_MASK 0x8000 +#define RTL8367C_IMS_SDS_LINK_STS_C6_OFFSET 14 +#define RTL8367C_IMS_SDS_LINK_STS_C6_MASK 0x4000 +#define RTL8367C_IMS_SDS_LINK_STS_C5_OFFSET 13 +#define RTL8367C_IMS_SDS_LINK_STS_C5_MASK 0x2000 +#define RTL8367C_IMS_SDS_LINK_STS_C4_OFFSET 12 +#define RTL8367C_IMS_SDS_LINK_STS_C4_MASK 0x1000 +#define RTL8367C_IMS_SDS_LINK_STS_C3_OFFSET 11 +#define RTL8367C_IMS_SDS_LINK_STS_C3_MASK 0x800 +#define RTL8367C_IMS_SDS_LINK_STS_C2_OFFSET 10 +#define RTL8367C_IMS_SDS_LINK_STS_C2_MASK 0x400 +#define RTL8367C_IMS_SDS_LINK_STS_C1_OFFSET 9 +#define RTL8367C_IMS_SDS_LINK_STS_C1_MASK 0x200 +#define RTL8367C_IMS_SDS_LINK_STS_C0_OFFSET 8 +#define RTL8367C_IMS_SDS_LINK_STS_C0_MASK 0x100 +#define RTL8367C_IMR_SDS_LINK_STS_C7_OFFSET 7 +#define RTL8367C_IMR_SDS_LINK_STS_C7_MASK 0x80 +#define RTL8367C_IMR_SDS_LINK_STS_C6_OFFSET 6 +#define RTL8367C_IMR_SDS_LINK_STS_C6_MASK 0x40 +#define RTL8367C_IMR_SDS_LINK_STS_C5_OFFSET 5 +#define RTL8367C_IMR_SDS_LINK_STS_C5_MASK 0x20 +#define RTL8367C_IMR_SDS_LINK_STS_C4_OFFSET 4 +#define RTL8367C_IMR_SDS_LINK_STS_C4_MASK 0x10 +#define RTL8367C_IMR_SDS_LINK_STS_C3_OFFSET 3 +#define RTL8367C_IMR_SDS_LINK_STS_C3_MASK 0x8 +#define RTL8367C_IMR_SDS_LINK_STS_C2_OFFSET 2 +#define RTL8367C_IMR_SDS_LINK_STS_C2_MASK 0x4 +#define RTL8367C_IMR_SDS_LINK_STS_C1_OFFSET 1 +#define RTL8367C_IMR_SDS_LINK_STS_C1_MASK 0x2 +#define RTL8367C_IMR_SDS_LINK_STS_C0_OFFSET 0 +#define RTL8367C_IMR_SDS_LINK_STS_C0_MASK 0x1 + +#define RTL8367C_REG_SDS_LINK_CHG_INT_8051 0x1131 +#define RTL8367C_IMS_SDS_LINK_STS_C7_8051_OFFSET 15 +#define RTL8367C_IMS_SDS_LINK_STS_C7_8051_MASK 0x8000 +#define RTL8367C_IMS_SDS_LINK_STS_C6_8051_OFFSET 14 +#define RTL8367C_IMS_SDS_LINK_STS_C6_8051_MASK 0x4000 +#define RTL8367C_IMS_SDS_LINK_STS_C5_8051_OFFSET 13 +#define RTL8367C_IMS_SDS_LINK_STS_C5_8051_MASK 0x2000 +#define RTL8367C_IMS_SDS_LINK_STS_C4_8051_OFFSET 12 +#define RTL8367C_IMS_SDS_LINK_STS_C4_8051_MASK 0x1000 +#define RTL8367C_IMS_SDS_LINK_STS_C3_8051_OFFSET 11 +#define RTL8367C_IMS_SDS_LINK_STS_C3_8051_MASK 0x800 +#define RTL8367C_IMS_SDS_LINK_STS_C2_8051_OFFSET 10 +#define RTL8367C_IMS_SDS_LINK_STS_C2_8051_MASK 0x400 +#define RTL8367C_IMS_SDS_LINK_STS_C1_8051_OFFSET 9 +#define RTL8367C_IMS_SDS_LINK_STS_C1_8051_MASK 0x200 +#define RTL8367C_IMS_SDS_LINK_STS_C0_8051_OFFSET 8 +#define RTL8367C_IMS_SDS_LINK_STS_C0_8051_MASK 0x100 +#define RTL8367C_IMR_SDS_LINK_STS_C7_8051_OFFSET 7 +#define RTL8367C_IMR_SDS_LINK_STS_C7_8051_MASK 0x80 +#define RTL8367C_IMR_SDS_LINK_STS_C6_8051_OFFSET 6 +#define RTL8367C_IMR_SDS_LINK_STS_C6_8051_MASK 0x40 +#define RTL8367C_IMR_SDS_LINK_STS_C5_8051_OFFSET 5 +#define RTL8367C_IMR_SDS_LINK_STS_C5_8051_MASK 0x20 +#define RTL8367C_IMR_SDS_LINK_STS_C4_8051_OFFSET 4 +#define RTL8367C_IMR_SDS_LINK_STS_C4_8051_MASK 0x10 +#define RTL8367C_IMR_SDS_LINK_STS_C3_8051_OFFSET 3 +#define RTL8367C_IMR_SDS_LINK_STS_C3_8051_MASK 0x8 +#define RTL8367C_IMR_SDS_LINK_STS_C2_8051_OFFSET 2 +#define RTL8367C_IMR_SDS_LINK_STS_C2_8051_MASK 0x4 +#define RTL8367C_IMR_SDS_LINK_STS_C1_8051_OFFSET 1 +#define RTL8367C_IMR_SDS_LINK_STS_C1_8051_MASK 0x2 +#define RTL8367C_IMR_SDS_LINK_STS_C0_8051_OFFSET 0 +#define RTL8367C_IMR_SDS_LINK_STS_C0_8051_MASK 0x1 + +/* (16'h1200)swcore_reg */ + +#define RTL8367C_REG_MAX_LENGTH_LIMINT_IPG 0x1200 +#define RTL8367C_MAX_LENTH_CTRL_OFFSET 13 +#define RTL8367C_MAX_LENTH_CTRL_MASK 0x6000 +#define RTL8367C_PAGES_BEFORE_FCDROP_OFFSET 6 +#define RTL8367C_PAGES_BEFORE_FCDROP_MASK 0x1FC0 +#define RTL8367C_CHECK_MIN_IPG_RXDV_OFFSET 5 +#define RTL8367C_CHECK_MIN_IPG_RXDV_MASK 0x20 +#define RTL8367C_LIMIT_IPG_CFG_OFFSET 0 +#define RTL8367C_LIMIT_IPG_CFG_MASK 0x1F + +#define RTL8367C_REG_IOL_RXDROP_CFG 0x1201 +#define RTL8367C_RX_IOL_MAX_LENGTH_CFG_OFFSET 13 +#define RTL8367C_RX_IOL_MAX_LENGTH_CFG_MASK 0x2000 +#define RTL8367C_RX_IOL_ERROR_LENGTH_CFG_OFFSET 12 +#define RTL8367C_RX_IOL_ERROR_LENGTH_CFG_MASK 0x1000 +#define RTL8367C_RX_NODROP_PAUSE_CFG_OFFSET 8 +#define RTL8367C_RX_NODROP_PAUSE_CFG_MASK 0x100 +#define RTL8367C_RX_DV_CNT_CFG_OFFSET 0 +#define RTL8367C_RX_DV_CNT_CFG_MASK 0x3F + +#define RTL8367C_REG_VS_TPID 0x1202 + +#define RTL8367C_REG_INBW_BOUND 0x1203 +#define RTL8367C_LBOUND_OFFSET 4 +#define RTL8367C_LBOUND_MASK 0xF0 +#define RTL8367C_HBOUND_OFFSET 0 +#define RTL8367C_HBOUND_MASK 0xF + +#define RTL8367C_REG_CFG_TX_ITFSP_OP 0x1204 +#define RTL8367C_MASK_OFFSET 1 +#define RTL8367C_MASK_MASK 0x2 +#define RTL8367C_OP_OFFSET 0 +#define RTL8367C_OP_MASK 0x1 + +#define RTL8367C_REG_INBW_BOUND2 0x1205 +#define RTL8367C_LBOUND2_H_OFFSET 9 +#define RTL8367C_LBOUND2_H_MASK 0x200 +#define RTL8367C_HBOUND2_H_OFFSET 8 +#define RTL8367C_HBOUND2_H_MASK 0x100 +#define RTL8367C_LBOUND2_OFFSET 4 +#define RTL8367C_LBOUND2_MASK 0xF0 +#define RTL8367C_HBOUND2_OFFSET 0 +#define RTL8367C_HBOUND2_MASK 0xF + +#define RTL8367C_REG_CFG_48PASS1_DROP 0x1206 +#define RTL8367C_CFG_48PASS1_DROP_OFFSET 0 +#define RTL8367C_CFG_48PASS1_DROP_MASK 0x1 + +#define RTL8367C_REG_CFG_BACKPRESSURE 0x1207 +#define RTL8367C_LONGTXE_OFFSET 12 +#define RTL8367C_LONGTXE_MASK 0x1000 +#define RTL8367C_EN_BYPASS_ERROR_OFFSET 8 +#define RTL8367C_EN_BYPASS_ERROR_MASK 0x100 +#define RTL8367C_EN_BACKPRESSURE_OFFSET 4 +#define RTL8367C_EN_BACKPRESSURE_MASK 0x10 +#define RTL8367C_EN_48_PASS_1_OFFSET 0 +#define RTL8367C_EN_48_PASS_1_MASK 0x1 + +#define RTL8367C_REG_CFG_UNHIOL 0x1208 +#define RTL8367C_IOL_BACKOFF_OFFSET 12 +#define RTL8367C_IOL_BACKOFF_MASK 0x1000 +#define RTL8367C_BACKOFF_RANDOM_TIME_OFFSET 8 +#define RTL8367C_BACKOFF_RANDOM_TIME_MASK 0x100 +#define RTL8367C_DISABLE_BACK_OFF_OFFSET 4 +#define RTL8367C_DISABLE_BACK_OFF_MASK 0x10 +#define RTL8367C_IPG_COMPENSATION_OFFSET 0 +#define RTL8367C_IPG_COMPENSATION_MASK 0x1 + +#define RTL8367C_REG_SWITCH_MAC0 0x1209 + +#define RTL8367C_REG_SWITCH_MAC1 0x120a + +#define RTL8367C_REG_SWITCH_MAC2 0x120b + +#define RTL8367C_REG_SWITCH_CTRL0 0x120c +#define RTL8367C_REMARKING_DSCP_ENABLE_OFFSET 8 +#define RTL8367C_REMARKING_DSCP_ENABLE_MASK 0x100 +#define RTL8367C_SHORT_IPG_OFFSET 4 +#define RTL8367C_SHORT_IPG_MASK 0x10 +#define RTL8367C_PAUSE_MAX128_OFFSET 0 +#define RTL8367C_PAUSE_MAX128_MASK 0x1 + +#define RTL8367C_REG_QOS_DSCP_REMARK_CTRL0 0x120d +#define RTL8367C_INTPRI1_DSCP_OFFSET 8 +#define RTL8367C_INTPRI1_DSCP_MASK 0x3F00 +#define RTL8367C_INTPRI0_DSCP_OFFSET 0 +#define RTL8367C_INTPRI0_DSCP_MASK 0x3F + +#define RTL8367C_REG_QOS_DSCP_REMARK_CTRL1 0x120e +#define RTL8367C_INTPRI3_DSCP_OFFSET 8 +#define RTL8367C_INTPRI3_DSCP_MASK 0x3F00 +#define RTL8367C_INTPRI2_DSCP_OFFSET 0 +#define RTL8367C_INTPRI2_DSCP_MASK 0x3F + +#define RTL8367C_REG_QOS_DSCP_REMARK_CTRL2 0x120f +#define RTL8367C_INTPRI5_DSCP_OFFSET 8 +#define RTL8367C_INTPRI5_DSCP_MASK 0x3F00 +#define RTL8367C_INTPRI4_DSCP_OFFSET 0 +#define RTL8367C_INTPRI4_DSCP_MASK 0x3F + +#define RTL8367C_REG_QOS_DSCP_REMARK_CTRL3 0x1210 +#define RTL8367C_INTPRI7_DSCP_OFFSET 8 +#define RTL8367C_INTPRI7_DSCP_MASK 0x3F00 +#define RTL8367C_INTPRI6_DSCP_OFFSET 0 +#define RTL8367C_INTPRI6_DSCP_MASK 0x3F + +#define RTL8367C_REG_QOS_1Q_REMARK_CTRL0 0x1211 +#define RTL8367C_INTPRI3_PRI_OFFSET 12 +#define RTL8367C_INTPRI3_PRI_MASK 0x7000 +#define RTL8367C_INTPRI2_PRI_OFFSET 8 +#define RTL8367C_INTPRI2_PRI_MASK 0x700 +#define RTL8367C_INTPRI1_PRI_OFFSET 4 +#define RTL8367C_INTPRI1_PRI_MASK 0x70 +#define RTL8367C_INTPRI0_PRI_OFFSET 0 +#define RTL8367C_INTPRI0_PRI_MASK 0x7 + +#define RTL8367C_REG_QOS_1Q_REMARK_CTRL1 0x1212 +#define RTL8367C_INTPRI7_PRI_OFFSET 12 +#define RTL8367C_INTPRI7_PRI_MASK 0x7000 +#define RTL8367C_INTPRI6_PRI_OFFSET 8 +#define RTL8367C_INTPRI6_PRI_MASK 0x700 +#define RTL8367C_INTPRI5_PRI_OFFSET 4 +#define RTL8367C_INTPRI5_PRI_MASK 0x70 +#define RTL8367C_INTPRI4_PRI_OFFSET 0 +#define RTL8367C_INTPRI4_PRI_MASK 0x7 + +#define RTL8367C_REG_PKTGEN_COMMAND 0x1213 +#define RTL8367C_PKTGEN_STOP_OFFSET 8 +#define RTL8367C_PKTGEN_STOP_MASK 0x100 +#define RTL8367C_PKTGEN_START_OFFSET 4 +#define RTL8367C_PKTGEN_START_MASK 0x10 +#define RTL8367C_PKTGEN_BYPASS_FLOWCONTROL_OFFSET 0 +#define RTL8367C_PKTGEN_BYPASS_FLOWCONTROL_MASK 0x1 + +#define RTL8367C_REG_SW_DUMMY0 0x1214 +#define RTL8367C_SW_DUMMY0_DUMMY_OFFSET 4 +#define RTL8367C_SW_DUMMY0_DUMMY_MASK 0xFFF0 +#define RTL8367C_EEE_DEFER_TXLPI_OFFSET 3 +#define RTL8367C_EEE_DEFER_TXLPI_MASK 0x8 +#define RTL8367C_INGRESSBW_BYPASS_EN_OFFSET 2 +#define RTL8367C_INGRESSBW_BYPASS_EN_MASK 0x4 +#define RTL8367C_CFG_RX_MIN_OFFSET 0 +#define RTL8367C_CFG_RX_MIN_MASK 0x3 + +#define RTL8367C_REG_SW_DUMMY1 0x1215 + +#define RTL8367C_REG_PKTGEN_PAUSE_TIME 0x1216 + +#define RTL8367C_REG_SVLAN_UPLINK_PORTMASK 0x1218 +#define RTL8367C_SVLAN_UPLINK_PORTMASK_OFFSET 0 +#define RTL8367C_SVLAN_UPLINK_PORTMASK_MASK 0x7FF + +#define RTL8367C_REG_CPU_PORT_MASK 0x1219 +#define RTL8367C_CPU_PORT_MASK_OFFSET 0 +#define RTL8367C_CPU_PORT_MASK_MASK 0x7FF + +#define RTL8367C_REG_CPU_CTRL 0x121a +#define RTL8367C_CPU_TRAP_PORT_EXT_OFFSET 10 +#define RTL8367C_CPU_TRAP_PORT_EXT_MASK 0x400 +#define RTL8367C_CPU_TAG_FORMAT_OFFSET 9 +#define RTL8367C_CPU_TAG_FORMAT_MASK 0x200 +#define RTL8367C_IOL_16DROP_OFFSET 8 +#define RTL8367C_IOL_16DROP_MASK 0x100 +#define RTL8367C_CPU_TAG_RXBYTECOUNT_OFFSET 7 +#define RTL8367C_CPU_TAG_RXBYTECOUNT_MASK 0x80 +#define RTL8367C_CPU_TAG_POSITION_OFFSET 6 +#define RTL8367C_CPU_TAG_POSITION_MASK 0x40 +#define RTL8367C_CPU_TRAP_PORT_OFFSET 3 +#define RTL8367C_CPU_TRAP_PORT_MASK 0x38 +#define RTL8367C_CPU_INSERTMODE_OFFSET 1 +#define RTL8367C_CPU_INSERTMODE_MASK 0x6 +#define RTL8367C_CPU_EN_OFFSET 0 +#define RTL8367C_CPU_EN_MASK 0x1 + +#define RTL8367C_REG_MIRROR_CTRL 0x121c +#define RTL8367C_MIRROR_CTRL_DUMMY_OFFSET 12 +#define RTL8367C_MIRROR_CTRL_DUMMY_MASK 0xF000 +#define RTL8367C_MIRROR_ISO_OFFSET 11 +#define RTL8367C_MIRROR_ISO_MASK 0x800 +#define RTL8367C_MIRROR_TX_OFFSET 10 +#define RTL8367C_MIRROR_TX_MASK 0x400 +#define RTL8367C_MIRROR_RX_OFFSET 9 +#define RTL8367C_MIRROR_RX_MASK 0x200 +#define RTL8367C_MIRROR_MONITOR_PORT_OFFSET 4 +#define RTL8367C_MIRROR_MONITOR_PORT_MASK 0xF0 +#define RTL8367C_MIRROR_SOURCE_PORT_OFFSET 0 +#define RTL8367C_MIRROR_SOURCE_PORT_MASK 0xF + +#define RTL8367C_REG_FLOWCTRL_CTRL0 0x121d +#define RTL8367C_FLOWCTRL_TYPE_OFFSET 15 +#define RTL8367C_FLOWCTRL_TYPE_MASK 0x8000 +#define RTL8367C_DROP_ALL_THRESHOLD_OFFSET 5 +#define RTL8367C_DROP_ALL_THRESHOLD_MASK 0x7FE0 +#define RTL8367C_DROP_ALL_THRESHOLD_MSB_OFFSET 4 +#define RTL8367C_DROP_ALL_THRESHOLD_MSB_MASK 0x10 +#define RTL8367C_ITFSP_REG_OFFSET 0 +#define RTL8367C_ITFSP_REG_MASK 0x7 + +#define RTL8367C_REG_FLOWCTRL_ALL_ON 0x121e +#define RTL8367C_CFG_RLDPACT_OFFSET 12 +#define RTL8367C_CFG_RLDPACT_MASK 0x1000 +#define RTL8367C_FLOWCTRL_ALL_ON_THRESHOLD_OFFSET 0 +#define RTL8367C_FLOWCTRL_ALL_ON_THRESHOLD_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_SYS_ON 0x121f +#define RTL8367C_FLOWCTRL_SYS_ON_OFFSET 0 +#define RTL8367C_FLOWCTRL_SYS_ON_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_SYS_OFF 0x1220 +#define RTL8367C_FLOWCTRL_SYS_OFF_OFFSET 0 +#define RTL8367C_FLOWCTRL_SYS_OFF_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_SHARE_ON 0x1221 +#define RTL8367C_FLOWCTRL_SHARE_ON_OFFSET 0 +#define RTL8367C_FLOWCTRL_SHARE_ON_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_SHARE_OFF 0x1222 +#define RTL8367C_FLOWCTRL_SHARE_OFF_OFFSET 0 +#define RTL8367C_FLOWCTRL_SHARE_OFF_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_FCOFF_SYS_ON 0x1223 +#define RTL8367C_FLOWCTRL_FCOFF_SYS_ON_OFFSET 0 +#define RTL8367C_FLOWCTRL_FCOFF_SYS_ON_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_FCOFF_SYS_OFF 0x1224 +#define RTL8367C_FLOWCTRL_FCOFF_SYS_OFF_OFFSET 0 +#define RTL8367C_FLOWCTRL_FCOFF_SYS_OFF_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_FCOFF_SHARE_ON 0x1225 +#define RTL8367C_FLOWCTRL_FCOFF_SHARE_ON_OFFSET 0 +#define RTL8367C_FLOWCTRL_FCOFF_SHARE_ON_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_FCOFF_SHARE_OFF 0x1226 +#define RTL8367C_FLOWCTRL_FCOFF_SHARE_OFF_OFFSET 0 +#define RTL8367C_FLOWCTRL_FCOFF_SHARE_OFF_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_PORT_ON 0x1227 +#define RTL8367C_FLOWCTRL_PORT_ON_OFFSET 0 +#define RTL8367C_FLOWCTRL_PORT_ON_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_PORT_OFF 0x1228 +#define RTL8367C_FLOWCTRL_PORT_OFF_OFFSET 0 +#define RTL8367C_FLOWCTRL_PORT_OFF_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_PORT_PRIVATE_ON 0x1229 +#define RTL8367C_FLOWCTRL_PORT_PRIVATE_ON_OFFSET 0 +#define RTL8367C_FLOWCTRL_PORT_PRIVATE_ON_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_PORT_PRIVATE_OFF 0x122a +#define RTL8367C_FLOWCTRL_PORT_PRIVATE_OFF_OFFSET 0 +#define RTL8367C_FLOWCTRL_PORT_PRIVATE_OFF_MASK 0x7FF + +#define RTL8367C_REG_RRCP_CTRL0 0x122b +#define RTL8367C_COL_SEL_OFFSET 14 +#define RTL8367C_COL_SEL_MASK 0x4000 +#define RTL8367C_CRS_SEL_OFFSET 13 +#define RTL8367C_CRS_SEL_MASK 0x2000 +#define RTL8367C_RRCP_PBVLAN_EN_OFFSET 11 +#define RTL8367C_RRCP_PBVLAN_EN_MASK 0x800 +#define RTL8367C_RRCPV3_SECURITY_CRC_OFFSET 10 +#define RTL8367C_RRCPV3_SECURITY_CRC_MASK 0x400 +#define RTL8367C_RRCPV3_HANDLE_OFFSET 8 +#define RTL8367C_RRCPV3_HANDLE_MASK 0x300 +#define RTL8367C_RRCPV1_MALFORMED_ACT_OFFSET 5 +#define RTL8367C_RRCPV1_MALFORMED_ACT_MASK 0x60 +#define RTL8367C_RRCP_VLANLEAKY_OFFSET 4 +#define RTL8367C_RRCP_VLANLEAKY_MASK 0x10 +#define RTL8367C_RRCPV1_SECURITY_CRC_GET_OFFSET 3 +#define RTL8367C_RRCPV1_SECURITY_CRC_GET_MASK 0x8 +#define RTL8367C_RRCPV1_SECURITY_CRC_SET_OFFSET 2 +#define RTL8367C_RRCPV1_SECURITY_CRC_SET_MASK 0x4 +#define RTL8367C_RRCPV1_HANDLE_OFFSET 1 +#define RTL8367C_RRCPV1_HANDLE_MASK 0x2 +#define RTL8367C_RRCP_ENABLE_OFFSET 0 +#define RTL8367C_RRCP_ENABLE_MASK 0x1 + +#define RTL8367C_REG_RRCP_CTRL1 0x122c +#define RTL8367C_RRCP_ADMIN_PMSK_OFFSET 8 +#define RTL8367C_RRCP_ADMIN_PMSK_MASK 0xFF00 +#define RTL8367C_RRCP_AUTH_PMSK_OFFSET 0 +#define RTL8367C_RRCP_AUTH_PMSK_MASK 0xFF + +#define RTL8367C_REG_RRCP_CTRL2 0x122d +#define RTL8367C_RRCPV1_HELLOFWD_TAG_OFFSET 9 +#define RTL8367C_RRCPV1_HELLOFWD_TAG_MASK 0x600 +#define RTL8367C_RRCP_FWD_TAG_OFFSET 7 +#define RTL8367C_RRCP_FWD_TAG_MASK 0x180 +#define RTL8367C_RRCPV1_REPLY_TAG_OFFSET 6 +#define RTL8367C_RRCPV1_REPLY_TAG_MASK 0x40 +#define RTL8367C_RRCPV1_HELLO_COUNT_OFFSET 3 +#define RTL8367C_RRCPV1_HELLO_COUNT_MASK 0x38 +#define RTL8367C_RRCPV1_HELLO_PEDIOD_OFFSET 0 +#define RTL8367C_RRCPV1_HELLO_PEDIOD_MASK 0x3 + +#define RTL8367C_REG_RRCP_CTRL3 0x122e +#define RTL8367C_RRCP_TAG_PRIORITY_OFFSET 13 +#define RTL8367C_RRCP_TAG_PRIORITY_MASK 0xE000 +#define RTL8367C_RRCP_TAG_VID_OFFSET 0 +#define RTL8367C_RRCP_TAG_VID_MASK 0xFFF + +#define RTL8367C_REG_FLOWCTRL_FCOFF_PORT_ON 0x122f +#define RTL8367C_FLOWCTRL_FCOFF_PORT_ON_OFFSET 0 +#define RTL8367C_FLOWCTRL_FCOFF_PORT_ON_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_FCOFF_PORT_OFF 0x1230 +#define RTL8367C_FLOWCTRL_FCOFF_PORT_OFF_OFFSET 0 +#define RTL8367C_FLOWCTRL_FCOFF_PORT_OFF_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_FCOFF_PORT_PRIVATE_ON 0x1231 +#define RTL8367C_FLOWCTRL_FCOFF_PORT_PRIVATE_ON_OFFSET 0 +#define RTL8367C_FLOWCTRL_FCOFF_PORT_PRIVATE_ON_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_FCOFF_PORT_PRIVATE_OFF 0x1232 +#define RTL8367C_FLOWCTRL_FCOFF_PORT_PRIVATE_OFF_OFFSET 0 +#define RTL8367C_FLOWCTRL_FCOFF_PORT_PRIVATE_OFF_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_JUMBO_SYS_ON 0x1233 +#define RTL8367C_FLOWCTRL_JUMBO_SYS_ON_OFFSET 0 +#define RTL8367C_FLOWCTRL_JUMBO_SYS_ON_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_JUMBO_SYS_OFF 0x1234 +#define RTL8367C_FLOWCTRL_JUMBO_SYS_OFF_OFFSET 0 +#define RTL8367C_FLOWCTRL_JUMBO_SYS_OFF_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_JUMBO_SHARE_ON 0x1235 +#define RTL8367C_FLOWCTRL_JUMBO_SHARE_ON_OFFSET 0 +#define RTL8367C_FLOWCTRL_JUMBO_SHARE_ON_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_JUMBO_SHARE_OFF 0x1236 +#define RTL8367C_FLOWCTRL_JUMBO_SHARE_OFF_OFFSET 0 +#define RTL8367C_FLOWCTRL_JUMBO_SHARE_OFF_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_JUMBO_PORT_ON 0x1237 +#define RTL8367C_FLOWCTRL_JUMBO_PORT_ON_OFFSET 0 +#define RTL8367C_FLOWCTRL_JUMBO_PORT_ON_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_JUMBO_PORT_OFF 0x1238 +#define RTL8367C_FLOWCTRL_JUMBO_PORT_OFF_OFFSET 0 +#define RTL8367C_FLOWCTRL_JUMBO_PORT_OFF_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_JUMBO_PORT_PRIVATE_ON 0x1239 +#define RTL8367C_FLOWCTRL_JUMBO_PORT_PRIVATE_ON_OFFSET 0 +#define RTL8367C_FLOWCTRL_JUMBO_PORT_PRIVATE_ON_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_JUMBO_PORT_PRIVATE_OFF 0x123a +#define RTL8367C_FLOWCTRL_JUMBO_PORT_PRIVATE_OFF_OFFSET 0 +#define RTL8367C_FLOWCTRL_JUMBO_PORT_PRIVATE_OFF_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_JUMBO_SIZE 0x123b +#define RTL8367C_JUMBO_MODE_OFFSET 2 +#define RTL8367C_JUMBO_MODE_MASK 0x4 +#define RTL8367C_JUMBO_SIZE_OFFSET 0 +#define RTL8367C_JUMBO_SIZE_MASK 0x3 + +#define RTL8367C_REG_FLOWCTRL_TOTAL_PAGE_COUNTER 0x124c +#define RTL8367C_FLOWCTRL_TOTAL_PAGE_COUNTER_OFFSET 0 +#define RTL8367C_FLOWCTRL_TOTAL_PAGE_COUNTER_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_PUBLIC_PAGE_COUNTER 0x124d +#define RTL8367C_FLOWCTRL_PUBLIC_PAGE_COUNTER_OFFSET 0 +#define RTL8367C_FLOWCTRL_PUBLIC_PAGE_COUNTER_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_TOTAL_PAGE_MAX 0x124e +#define RTL8367C_FLOWCTRL_TOTAL_PAGE_MAX_OFFSET 0 +#define RTL8367C_FLOWCTRL_TOTAL_PAGE_MAX_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_PUBLIC_PAGE_MAX 0x124f +#define RTL8367C_FLOWCTRL_PUBLIC_PAGE_MAX_OFFSET 0 +#define RTL8367C_FLOWCTRL_PUBLIC_PAGE_MAX_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_PORT0_PAGE_COUNTER 0x1250 +#define RTL8367C_FLOWCTRL_PORT0_PAGE_COUNTER_OFFSET 0 +#define RTL8367C_FLOWCTRL_PORT0_PAGE_COUNTER_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_PORT1_PAGE_COUNTER 0x1251 +#define RTL8367C_FLOWCTRL_PORT1_PAGE_COUNTER_OFFSET 0 +#define RTL8367C_FLOWCTRL_PORT1_PAGE_COUNTER_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_PORT2_PAGE_COUNTER 0x1252 +#define RTL8367C_FLOWCTRL_PORT2_PAGE_COUNTER_OFFSET 0 +#define RTL8367C_FLOWCTRL_PORT2_PAGE_COUNTER_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_PORT3_PAGE_COUNTER 0x1253 +#define RTL8367C_FLOWCTRL_PORT3_PAGE_COUNTER_OFFSET 0 +#define RTL8367C_FLOWCTRL_PORT3_PAGE_COUNTER_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_PORT4_PAGE_COUNTER 0x1254 +#define RTL8367C_FLOWCTRL_PORT4_PAGE_COUNTER_OFFSET 0 +#define RTL8367C_FLOWCTRL_PORT4_PAGE_COUNTER_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_PORT5_PAGE_COUNTER 0x1255 +#define RTL8367C_FLOWCTRL_PORT5_PAGE_COUNTER_OFFSET 0 +#define RTL8367C_FLOWCTRL_PORT5_PAGE_COUNTER_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_PORT6_PAGE_COUNTER 0x1256 +#define RTL8367C_FLOWCTRL_PORT6_PAGE_COUNTER_OFFSET 0 +#define RTL8367C_FLOWCTRL_PORT6_PAGE_COUNTER_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_PORT7_PAGE_COUNTER 0x1257 +#define RTL8367C_FLOWCTRL_PORT7_PAGE_COUNTER_OFFSET 0 +#define RTL8367C_FLOWCTRL_PORT7_PAGE_COUNTER_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_PUBLIC_FCOFF_PAGE_COUNTER 0x1258 +#define RTL8367C_FLOWCTRL_PUBLIC_FCOFF_PAGE_COUNTER_OFFSET 0 +#define RTL8367C_FLOWCTRL_PUBLIC_FCOFF_PAGE_COUNTER_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_PUBLIC_JUMBO_PAGE_COUNTER 0x1259 +#define RTL8367C_FLOWCTRL_PUBLIC_JUMBO_PAGE_COUNTER_OFFSET 0 +#define RTL8367C_FLOWCTRL_PUBLIC_JUMBO_PAGE_COUNTER_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_MAX_PUBLIC_FCOFF_PAGE_COUNTER 0x125a +#define RTL8367C_FLOWCTRL_MAX_PUBLIC_FCOFF_PAGE_COUNTER_OFFSET 0 +#define RTL8367C_FLOWCTRL_MAX_PUBLIC_FCOFF_PAGE_COUNTER_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_MAX_PUBLIC_JUMBO_PAGE_COUNTER 0x125b +#define RTL8367C_FLOWCTRL_MAX_PUBLIC_JUMBO_PAGE_COUNTER_OFFSET 0 +#define RTL8367C_FLOWCTRL_MAX_PUBLIC_JUMBO_PAGE_COUNTER_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_PORT0_PAGE_MAX 0x1260 +#define RTL8367C_FLOWCTRL_PORT0_PAGE_MAX_OFFSET 0 +#define RTL8367C_FLOWCTRL_PORT0_PAGE_MAX_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_PORT1_PAGE_MAX 0x1261 +#define RTL8367C_FLOWCTRL_PORT1_PAGE_MAX_OFFSET 0 +#define RTL8367C_FLOWCTRL_PORT1_PAGE_MAX_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_PORT2_PAGE_MAX 0x1262 +#define RTL8367C_FLOWCTRL_PORT2_PAGE_MAX_OFFSET 0 +#define RTL8367C_FLOWCTRL_PORT2_PAGE_MAX_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_PORT3_PAGE_MAX 0x1263 +#define RTL8367C_FLOWCTRL_PORT3_PAGE_MAX_OFFSET 0 +#define RTL8367C_FLOWCTRL_PORT3_PAGE_MAX_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_PORT4_PAGE_MAX 0x1264 +#define RTL8367C_FLOWCTRL_PORT4_PAGE_MAX_OFFSET 0 +#define RTL8367C_FLOWCTRL_PORT4_PAGE_MAX_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_PORT5_PAGE_MAX 0x1265 +#define RTL8367C_FLOWCTRL_PORT5_PAGE_MAX_OFFSET 0 +#define RTL8367C_FLOWCTRL_PORT5_PAGE_MAX_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_PORT6_PAGE_MAX 0x1266 +#define RTL8367C_FLOWCTRL_PORT6_PAGE_MAX_OFFSET 0 +#define RTL8367C_FLOWCTRL_PORT6_PAGE_MAX_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_PORT7_PAGE_MAX 0x1267 +#define RTL8367C_FLOWCTRL_PORT7_PAGE_MAX_OFFSET 0 +#define RTL8367C_FLOWCTRL_PORT7_PAGE_MAX_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_PAGE_COUNT_CLEAR 0x1268 +#define RTL8367C_DIS_SKIP_FP_OFFSET 1 +#define RTL8367C_DIS_SKIP_FP_MASK 0x2 +#define RTL8367C_PAGE_COUNT_CLEAR_OFFSET 0 +#define RTL8367C_PAGE_COUNT_CLEAR_MASK 0x1 + +#define RTL8367C_REG_FLOWCTRL_PORT8_PAGE_MAX 0x1269 +#define RTL8367C_FLOWCTRL_PORT8_PAGE_MAX_OFFSET 0 +#define RTL8367C_FLOWCTRL_PORT8_PAGE_MAX_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_PORT9_PAGE_MAX 0x126a +#define RTL8367C_FLOWCTRL_PORT9_PAGE_MAX_OFFSET 0 +#define RTL8367C_FLOWCTRL_PORT9_PAGE_MAX_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_PORT10_PAGE_MAX 0x126b +#define RTL8367C_FLOWCTRL_PORT10_PAGE_MAX_OFFSET 0 +#define RTL8367C_FLOWCTRL_PORT10_PAGE_MAX_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_PORT8_PAGE_COUNTER 0x126c +#define RTL8367C_FLOWCTRL_PORT8_PAGE_COUNTER_OFFSET 0 +#define RTL8367C_FLOWCTRL_PORT8_PAGE_COUNTER_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_PORT9_PAGE_COUNTER 0x126d +#define RTL8367C_FLOWCTRL_PORT9_PAGE_COUNTER_OFFSET 0 +#define RTL8367C_FLOWCTRL_PORT9_PAGE_COUNTER_MASK 0x7FF + +#define RTL8367C_REG_FLOWCTRL_PORT10_PAGE_COUNTER 0x126e +#define RTL8367C_FLOWCTRL_PORT10_PAGE_COUNTER_OFFSET 0 +#define RTL8367C_FLOWCTRL_PORT10_PAGE_COUNTER_MASK 0x7FF + +#define RTL8367C_REG_RRCP_CTRL1_H 0x126f +#define RTL8367C_RRCP_ADMIN_PMSK_P10_8_OFFSET 3 +#define RTL8367C_RRCP_ADMIN_PMSK_P10_8_MASK 0x38 +#define RTL8367C_RRCP_AUTH_PMSK_P10_8_OFFSET 0 +#define RTL8367C_RRCP_AUTH_PMSK_P10_8_MASK 0x7 + +#define RTL8367C_REG_EMA_CTRL0 0x1270 +#define RTL8367C_CFG_DVSE_VIAROM_OFFSET 13 +#define RTL8367C_CFG_DVSE_VIAROM_MASK 0x2000 +#define RTL8367C_CFG_DVSE_MIBRAM_OFFSET 12 +#define RTL8367C_CFG_DVSE_MIBRAM_MASK 0x1000 +#define RTL8367C_CFG_DVSE_IROM_OFFSET 11 +#define RTL8367C_CFG_DVSE_IROM_MASK 0x800 +#define RTL8367C_CFG_DVSE_ERAM_OFFSET 10 +#define RTL8367C_CFG_DVSE_ERAM_MASK 0x400 +#define RTL8367C_CFG_DVSE_IRAM_OFFSET 9 +#define RTL8367C_CFG_DVSE_IRAM_MASK 0x200 +#define RTL8367C_CFG_DVSE_NICRAM_OFFSET 8 +#define RTL8367C_CFG_DVSE_NICRAM_MASK 0x100 +#define RTL8367C_CFG_DVSE_CVLANRAM_OFFSET 7 +#define RTL8367C_CFG_DVSE_CVLANRAM_MASK 0x80 +#define RTL8367C_CFG_DVSE_ACTRAM_OFFSET 6 +#define RTL8367C_CFG_DVSE_ACTRAM_MASK 0x40 +#define RTL8367C_CFG_DVSE_INQRAM_OFFSET 5 +#define RTL8367C_CFG_DVSE_INQRAM_MASK 0x20 +#define RTL8367C_CFG_DVSE_HSARAM_OFFSET 4 +#define RTL8367C_CFG_DVSE_HSARAM_MASK 0x10 +#define RTL8367C_CFG_DVSE_OUTQRAM_OFFSET 3 +#define RTL8367C_CFG_DVSE_OUTQRAM_MASK 0x8 +#define RTL8367C_CFG_DVSE_HTRAM_OFFSET 2 +#define RTL8367C_CFG_DVSE_HTRAM_MASK 0x4 +#define RTL8367C_CFG_DVSE_PBRAM_OFFSET 1 +#define RTL8367C_CFG_DVSE_PBRAM_MASK 0x2 +#define RTL8367C_CFG_DVSE_L2RAM_OFFSET 0 +#define RTL8367C_CFG_DVSE_L2RAM_MASK 0x1 + +#define RTL8367C_REG_EMA_CTRL1 0x1271 +#define RTL8367C_CFG_DVS_OUTQRAM_OFFSET 12 +#define RTL8367C_CFG_DVS_OUTQRAM_MASK 0xF000 +#define RTL8367C_CFG_DVS_HTRAM_OFFSET 8 +#define RTL8367C_CFG_DVS_HTRAM_MASK 0x700 +#define RTL8367C_CFG_DVS_PBRAM_OFFSET 4 +#define RTL8367C_CFG_DVS_PBRAM_MASK 0xF0 +#define RTL8367C_CFG_DVS_L2RAM_OFFSET 0 +#define RTL8367C_CFG_DVS_L2RAM_MASK 0xF + +#define RTL8367C_REG_EMA_CTRL2 0x1272 +#define RTL8367C_CFG_DVS_CVLANRAM_OFFSET 12 +#define RTL8367C_CFG_DVS_CVLANRAM_MASK 0xF000 +#define RTL8367C_CFG_DVS_ACTRAM_OFFSET 8 +#define RTL8367C_CFG_DVS_ACTRAM_MASK 0xF00 +#define RTL8367C_CFG_DVS_INQRAM_OFFSET 4 +#define RTL8367C_CFG_DVS_INQRAM_MASK 0xF0 +#define RTL8367C_CFG_DVS_HSARAM_OFFSET 0 +#define RTL8367C_CFG_DVS_HSARAM_MASK 0xF + +#define RTL8367C_REG_EMA_CTRL3 0x1273 +#define RTL8367C_CFG_DVS_IROM_OFFSET 12 +#define RTL8367C_CFG_DVS_IROM_MASK 0xF000 +#define RTL8367C_CFG_DVS_ERAM_OFFSET 8 +#define RTL8367C_CFG_DVS_ERAM_MASK 0xF00 +#define RTL8367C_CFG_DVS_IRAM_OFFSET 4 +#define RTL8367C_CFG_DVS_IRAM_MASK 0xF0 +#define RTL8367C_CFG_DVS_NICRAM_OFFSET 0 +#define RTL8367C_CFG_DVS_NICRAM_MASK 0xF + +#define RTL8367C_REG_EMA_CTRL4 0x1274 +#define RTL8367C_CFG_DVS_VIAROM_OFFSET 4 +#define RTL8367C_CFG_DVS_VIAROM_MASK 0xF0 +#define RTL8367C_CFG_DVS_MIBRAM_OFFSET 0 +#define RTL8367C_CFG_DVS_MIBRAM_MASK 0xF + +#define RTL8367C_REG_DIAG_MODE 0x1275 +#define RTL8367C_DIAG_MODE_OFFSET 0 +#define RTL8367C_DIAG_MODE_MASK 0x1F + +#define RTL8367C_REG_BIST_MODE 0x1276 + +#define RTL8367C_REG_STS_BIST_DONE 0x1277 + +#define RTL8367C_REG_STS_BIST_RLT0 0x1278 +#define RTL8367C_STS_BIST_RLT0_OFFSET 0 +#define RTL8367C_STS_BIST_RLT0_MASK 0x1 + +#define RTL8367C_REG_STS_BIST_RLT1 0x1279 + +#define RTL8367C_REG_STS_BIST_RLT2 0x127a + +#define RTL8367C_REG_STS_BIST_RLT3 0x127b +#define RTL8367C_STS_BIST_RLT3_OFFSET 0 +#define RTL8367C_STS_BIST_RLT3_MASK 0x3FF + +#define RTL8367C_REG_STS_BIST_RLT4 0x127c +#define RTL8367C_STS_BIST_RLT4_OFFSET 0 +#define RTL8367C_STS_BIST_RLT4_MASK 0x7 + +#define RTL8367C_REG_VIAROM_MISR 0x127d + +#define RTL8367C_REG_DRF_BIST_MODE 0x1280 +#define RTL8367C_DRF_TCAMDEL_OFFSET 15 +#define RTL8367C_DRF_TCAMDEL_MASK 0x8000 +#define RTL8367C_CFG_DRF_BIST_MODE_OFFSET 0 +#define RTL8367C_CFG_DRF_BIST_MODE_MASK 0x7FFF + +#define RTL8367C_REG_STS_DRF_BIST 0x1281 +#define RTL8367C_STS_DRF_BIST_OFFSET 0 +#define RTL8367C_STS_DRF_BIST_MASK 0x7FFF + +#define RTL8367C_REG_STS_DRF_BIST_RLT0 0x1282 +#define RTL8367C_STS_DRF_BIST_RLT0_OFFSET 0 +#define RTL8367C_STS_DRF_BIST_RLT0_MASK 0x1 + +#define RTL8367C_REG_STS_DRF_BIST_RLT1 0x1283 + +#define RTL8367C_REG_STS_DRF_BIST_RLT2 0x1284 + +#define RTL8367C_REG_STS_DRF_BIST_RLT3 0x1285 +#define RTL8367C_STS_DRF_BIST_RLT3_OFFSET 0 +#define RTL8367C_STS_DRF_BIST_RLT3_MASK 0x3FF + +#define RTL8367C_REG_STS_DRF_BIST_RLT4 0x1286 +#define RTL8367C_STS_DRF_BIST_RLT4_OFFSET 0 +#define RTL8367C_STS_DRF_BIST_RLT4_MASK 0x7FFF + +#define RTL8367C_REG_RAM_DRF_CTRL 0x1289 +#define RTL8367C_RAM_DRF_CTRL_OFFSET 0 +#define RTL8367C_RAM_DRF_CTRL_MASK 0x1 + +#define RTL8367C_REG_MIB_RMON_LEN_CTRL 0x128a +#define RTL8367C_RX_LENGTH_CTRL_OFFSET 1 +#define RTL8367C_RX_LENGTH_CTRL_MASK 0x2 +#define RTL8367C_TX_LENGTH_CTRL_OFFSET 0 +#define RTL8367C_TX_LENGTH_CTRL_MASK 0x1 + +#define RTL8367C_REG_COND0_BISR_OUT0 0x1290 + +#define RTL8367C_REG_COND0_BISR_OUT1 0x1291 + +#define RTL8367C_REG_COND0_BISR_OUT2 0x1292 + +#define RTL8367C_REG_COND0_BISR_OUT3 0x1293 + +#define RTL8367C_REG_COND0_BISR_OUT4 0x1294 +#define RTL8367C_COND0_BISR_OUT4_OFFSET 0 +#define RTL8367C_COND0_BISR_OUT4_MASK 0x3F + +#define RTL8367C_REG_COND0_BISR_OUT5 0x1295 +#define RTL8367C_COND0_BISR_OUT5_OFFSET 0 +#define RTL8367C_COND0_BISR_OUT5_MASK 0x7 + +#define RTL8367C_REG_CHG_DUPLEX_CFG 0x1296 +#define RTL8367C_CHG_COL_CNT_PORT_OFFSET 13 +#define RTL8367C_CHG_COL_CNT_PORT_MASK 0xE000 +#define RTL8367C_CHG_COL_CNT_OFFSET 8 +#define RTL8367C_CHG_COL_CNT_MASK 0x1F00 +#define RTL8367C_CFG_CHG_DUP_EN_OFFSET 7 +#define RTL8367C_CFG_CHG_DUP_EN_MASK 0x80 +#define RTL8367C_CFG_CHG_DUP_THR_OFFSET 2 +#define RTL8367C_CFG_CHG_DUP_THR_MASK 0x7C +#define RTL8367C_CFG_CHG_DUP_CONGEST_OFFSET 1 +#define RTL8367C_CFG_CHG_DUP_CONGEST_MASK 0x2 +#define RTL8367C_CFG_CHG_DUP_REF_OFFSET 0 +#define RTL8367C_CFG_CHG_DUP_REF_MASK 0x1 + +#define RTL8367C_REG_COND0_BIST_PASS 0x1297 +#define RTL8367C_COND0_DRF_BIST_NOFAIL_OFFSET 1 +#define RTL8367C_COND0_DRF_BIST_NOFAIL_MASK 0x2 +#define RTL8367C_COND0_BIST_NOFAIL_OFFSET 0 +#define RTL8367C_COND0_BIST_NOFAIL_MASK 0x1 + +#define RTL8367C_REG_COND1_BISR_OUT0 0x1298 + +#define RTL8367C_REG_COND1_BISR_OUT1 0x1299 + +#define RTL8367C_REG_COND1_BISR_OUT2 0x129a + +#define RTL8367C_REG_COND1_BISR_OUT3 0x129b + +#define RTL8367C_REG_COND1_BISR_OUT4 0x129c +#define RTL8367C_COND1_BISR_OUT4_OFFSET 0 +#define RTL8367C_COND1_BISR_OUT4_MASK 0x3F + +#define RTL8367C_REG_COND1_BISR_OUT5 0x129d +#define RTL8367C_COND1_BISR_OUT5_OFFSET 0 +#define RTL8367C_COND1_BISR_OUT5_MASK 0x7 + +#define RTL8367C_REG_COND1_BIST_PASS 0x129f +#define RTL8367C_COND1_DRF_BIST_NOFAIL_OFFSET 1 +#define RTL8367C_COND1_DRF_BIST_NOFAIL_MASK 0x2 +#define RTL8367C_COND1_BIST_NOFAIL_OFFSET 0 +#define RTL8367C_COND1_BIST_NOFAIL_MASK 0x1 + +#define RTL8367C_REG_EEE_TX_THR_Giga_500M 0x12a0 + +#define RTL8367C_REG_EEE_TX_THR_FE 0x12a1 + +#define RTL8367C_REG_EEE_MISC 0x12a3 +#define RTL8367C_EEE_REQ_SET1_OFFSET 13 +#define RTL8367C_EEE_REQ_SET1_MASK 0x2000 +#define RTL8367C_EEE_REQ_SET0_OFFSET 12 +#define RTL8367C_EEE_REQ_SET0_MASK 0x1000 +#define RTL8367C_EEE_WAKE_SET1_OFFSET 9 +#define RTL8367C_EEE_WAKE_SET1_MASK 0x200 +#define RTL8367C_EEE_Wake_SET0_OFFSET 8 +#define RTL8367C_EEE_Wake_SET0_MASK 0x100 +#define RTL8367C_EEE_TU_GIGA_500M_OFFSET 4 +#define RTL8367C_EEE_TU_GIGA_500M_MASK 0x30 +#define RTL8367C_EEE_TU_100M_OFFSET 2 +#define RTL8367C_EEE_TU_100M_MASK 0xC + +#define RTL8367C_REG_EEE_GIGA_CTRL0 0x12a4 +#define RTL8367C_EEE_TW_GIGA_OFFSET 8 +#define RTL8367C_EEE_TW_GIGA_MASK 0xFF00 +#define RTL8367C_EEE_TR_GIGA_500M_OFFSET 0 +#define RTL8367C_EEE_TR_GIGA_500M_MASK 0xFF + +#define RTL8367C_REG_EEE_GIGA_CTRL1 0x12a5 +#define RTL8367C_EEE_TD_GIGA_500M_OFFSET 8 +#define RTL8367C_EEE_TD_GIGA_500M_MASK 0xFF00 +#define RTL8367C_EEE_TP_GIGA_OFFSET 0 +#define RTL8367C_EEE_TP_GIGA_MASK 0xFF + +#define RTL8367C_REG_EEE_100M_CTRL0 0x12a6 +#define RTL8367C_EEE_TW_100M_OFFSET 8 +#define RTL8367C_EEE_TW_100M_MASK 0xFF00 +#define RTL8367C_EEE_TR_100M_OFFSET 0 +#define RTL8367C_EEE_TR_100M_MASK 0xFF + +#define RTL8367C_REG_EEE_100M_CTRL1 0x12a7 +#define RTL8367C_EEE_TD_100M_OFFSET 8 +#define RTL8367C_EEE_TD_100M_MASK 0xFF00 +#define RTL8367C_EEE_TP_100M_OFFSET 0 +#define RTL8367C_EEE_TP_100M_MASK 0xFF + +#define RTL8367C_REG_RX_FC_REG 0x12aa +#define RTL8367C_EN_EEE_HALF_DUP_OFFSET 8 +#define RTL8367C_EN_EEE_HALF_DUP_MASK 0x100 +#define RTL8367C_RX_PGCNT_OFFSET 0 +#define RTL8367C_RX_PGCNT_MASK 0xFF + +#define RTL8367C_REG_MAX_FIFO_SIZE 0x12af +#define RTL8367C_MAX_FIFO_SIZE_OFFSET 0 +#define RTL8367C_MAX_FIFO_SIZE_MASK 0xF + +#define RTL8367C_REG_EEEP_RX_RATE_GIGA 0x12b0 + +#define RTL8367C_REG_EEEP_RX_RATE_100M 0x12b1 + +#define RTL8367C_REG_DUMMY_REG_12_2 0x12b2 + +#define RTL8367C_REG_EEEP_TX_RATE_GIGA 0x12b3 + +#define RTL8367C_REG_EEEP_TX_RATE_100M 0x12b4 + +#define RTL8367C_REG_DUMMY_REG_12_3 0x12b5 + +#define RTL8367C_REG_EEEP_GIGA_CTRL0 0x12b6 +#define RTL8367C_EEEP_TR_GIGA_OFFSET 8 +#define RTL8367C_EEEP_TR_GIGA_MASK 0xFF00 +#define RTL8367C_EEEP_RW_GIGA_MST_OFFSET 0 +#define RTL8367C_EEEP_RW_GIGA_MST_MASK 0xFF + +#define RTL8367C_REG_EEEP_GIGA_CTRL1 0x12b7 +#define RTL8367C_EEEP_TW_GIGA_OFFSET 8 +#define RTL8367C_EEEP_TW_GIGA_MASK 0xFF00 +#define RTL8367C_EEEP_TP_GIGA_OFFSET 0 +#define RTL8367C_EEEP_TP_GIGA_MASK 0xFF + +#define RTL8367C_REG_EEEP_GIGA_CTRL2 0x12b8 +#define RTL8367C_EEEP_TXEN_GIGA_OFFSET 12 +#define RTL8367C_EEEP_TXEN_GIGA_MASK 0x1000 +#define RTL8367C_EEEP_TU_GIGA_OFFSET 8 +#define RTL8367C_EEEP_TU_GIGA_MASK 0x300 +#define RTL8367C_EEEP_TS_GIGA_OFFSET 0 +#define RTL8367C_EEEP_TS_GIGA_MASK 0xFF + +#define RTL8367C_REG_EEEP_100M_CTRL0 0x12b9 +#define RTL8367C_EEEP_TR_100M_OFFSET 8 +#define RTL8367C_EEEP_TR_100M_MASK 0xFF00 +#define RTL8367C_EEEP_RW_100M_OFFSET 0 +#define RTL8367C_EEEP_RW_100M_MASK 0xFF + +#define RTL8367C_REG_EEEP_100M_CTRL1 0x12ba +#define RTL8367C_EEEP_TW_100M_OFFSET 8 +#define RTL8367C_EEEP_TW_100M_MASK 0xFF00 +#define RTL8367C_EEEP_TP_100M_OFFSET 0 +#define RTL8367C_EEEP_TP_100M_MASK 0xFF + +#define RTL8367C_REG_EEEP_100M_CTRL2 0x12bb +#define RTL8367C_EEEP_TXEN_100M_OFFSET 12 +#define RTL8367C_EEEP_TXEN_100M_MASK 0x1000 +#define RTL8367C_EEEP_TU_100M_OFFSET 8 +#define RTL8367C_EEEP_TU_100M_MASK 0x300 +#define RTL8367C_EEEP_TS_100M_OFFSET 0 +#define RTL8367C_EEEP_TS_100M_MASK 0xFF + +#define RTL8367C_REG_EEEP_CTRL0 0x12bc +#define RTL8367C_EEEP_CTRL0_DUMMY_OFFSET 8 +#define RTL8367C_EEEP_CTRL0_DUMMY_MASK 0xFF00 +#define RTL8367C_EEEP_SLEEP_STEP_OFFSET 0 +#define RTL8367C_EEEP_SLEEP_STEP_MASK 0xFF + +#define RTL8367C_REG_EEEP_CTRL1 0x12bd +#define RTL8367C_EEEP_TXR_GIGA_OFFSET 8 +#define RTL8367C_EEEP_TXR_GIGA_MASK 0xFF00 +#define RTL8367C_EEEP_TXR_100M_OFFSET 0 +#define RTL8367C_EEEP_TXR_100M_MASK 0xFF + +#define RTL8367C_REG_BACK_PRESSURE_IPG 0x12be +#define RTL8367C_BACK_PRESSURE_IPG_OFFSET 0 +#define RTL8367C_BACK_PRESSURE_IPG_MASK 0x3 + +#define RTL8367C_REG_TX_ESD_LEVEL 0x12bf +#define RTL8367C_TX_ESD_LEVEL_MODE_OFFSET 8 +#define RTL8367C_TX_ESD_LEVEL_MODE_MASK 0x100 +#define RTL8367C_LEVEL_OFFSET 0 +#define RTL8367C_LEVEL_MASK 0xFF + +#define RTL8367C_REG_RRCP_CTRL4 0x12e0 + +#define RTL8367C_REG_RRCP_CTRL5 0x12e1 + +#define RTL8367C_REG_RRCP_CTRL6 0x12e2 + +#define RTL8367C_REG_RRCP_CTRL7 0x12e3 + +#define RTL8367C_REG_RRCP_CTRL8 0x12e4 + +#define RTL8367C_REG_RRCP_CTRL9 0x12e5 + +#define RTL8367C_REG_RRCP_CTRL10 0x12e6 + +#define RTL8367C_REG_FIELD_SELECTOR0 0x12e7 +#define RTL8367C_FIELD_SELECTOR0_FORMAT_OFFSET 8 +#define RTL8367C_FIELD_SELECTOR0_FORMAT_MASK 0x700 +#define RTL8367C_FIELD_SELECTOR0_OFFSET_OFFSET 0 +#define RTL8367C_FIELD_SELECTOR0_OFFSET_MASK 0xFF + +#define RTL8367C_REG_FIELD_SELECTOR1 0x12e8 +#define RTL8367C_FIELD_SELECTOR1_FORMAT_OFFSET 8 +#define RTL8367C_FIELD_SELECTOR1_FORMAT_MASK 0x700 +#define RTL8367C_FIELD_SELECTOR1_OFFSET_OFFSET 0 +#define RTL8367C_FIELD_SELECTOR1_OFFSET_MASK 0xFF + +#define RTL8367C_REG_FIELD_SELECTOR2 0x12e9 +#define RTL8367C_FIELD_SELECTOR2_FORMAT_OFFSET 8 +#define RTL8367C_FIELD_SELECTOR2_FORMAT_MASK 0x700 +#define RTL8367C_FIELD_SELECTOR2_OFFSET_OFFSET 0 +#define RTL8367C_FIELD_SELECTOR2_OFFSET_MASK 0xFF + +#define RTL8367C_REG_FIELD_SELECTOR3 0x12ea +#define RTL8367C_FIELD_SELECTOR3_FORMAT_OFFSET 8 +#define RTL8367C_FIELD_SELECTOR3_FORMAT_MASK 0x700 +#define RTL8367C_FIELD_SELECTOR3_OFFSET_OFFSET 0 +#define RTL8367C_FIELD_SELECTOR3_OFFSET_MASK 0xFF + +#define RTL8367C_REG_FIELD_SELECTOR4 0x12eb +#define RTL8367C_FIELD_SELECTOR4_FORMAT_OFFSET 8 +#define RTL8367C_FIELD_SELECTOR4_FORMAT_MASK 0x700 +#define RTL8367C_FIELD_SELECTOR4_OFFSET_OFFSET 0 +#define RTL8367C_FIELD_SELECTOR4_OFFSET_MASK 0xFF + +#define RTL8367C_REG_FIELD_SELECTOR5 0x12ec +#define RTL8367C_FIELD_SELECTOR5_FORMAT_OFFSET 8 +#define RTL8367C_FIELD_SELECTOR5_FORMAT_MASK 0x700 +#define RTL8367C_FIELD_SELECTOR5_OFFSET_OFFSET 0 +#define RTL8367C_FIELD_SELECTOR5_OFFSET_MASK 0xFF + +#define RTL8367C_REG_FIELD_SELECTOR6 0x12ed +#define RTL8367C_FIELD_SELECTOR6_FORMAT_OFFSET 8 +#define RTL8367C_FIELD_SELECTOR6_FORMAT_MASK 0x700 +#define RTL8367C_FIELD_SELECTOR6_OFFSET_OFFSET 0 +#define RTL8367C_FIELD_SELECTOR6_OFFSET_MASK 0xFF + +#define RTL8367C_REG_FIELD_SELECTOR7 0x12ee +#define RTL8367C_FIELD_SELECTOR7_FORMAT_OFFSET 8 +#define RTL8367C_FIELD_SELECTOR7_FORMAT_MASK 0x700 +#define RTL8367C_FIELD_SELECTOR7_OFFSET_OFFSET 0 +#define RTL8367C_FIELD_SELECTOR7_OFFSET_MASK 0xFF + +#define RTL8367C_REG_FIELD_SELECTOR8 0x12ef +#define RTL8367C_FIELD_SELECTOR8_FORMAT_OFFSET 8 +#define RTL8367C_FIELD_SELECTOR8_FORMAT_MASK 0x700 +#define RTL8367C_FIELD_SELECTOR8_OFFSET_OFFSET 0 +#define RTL8367C_FIELD_SELECTOR8_OFFSET_MASK 0xFF + +#define RTL8367C_REG_FIELD_SELECTOR9 0x12f0 +#define RTL8367C_FIELD_SELECTOR9_FORMAT_OFFSET 8 +#define RTL8367C_FIELD_SELECTOR9_FORMAT_MASK 0x700 +#define RTL8367C_FIELD_SELECTOR9_OFFSET_OFFSET 0 +#define RTL8367C_FIELD_SELECTOR9_OFFSET_MASK 0xFF + +#define RTL8367C_REG_FIELD_SELECTOR10 0x12f1 +#define RTL8367C_FIELD_SELECTOR10_FORMAT_OFFSET 8 +#define RTL8367C_FIELD_SELECTOR10_FORMAT_MASK 0x700 +#define RTL8367C_FIELD_SELECTOR10_OFFSET_OFFSET 0 +#define RTL8367C_FIELD_SELECTOR10_OFFSET_MASK 0xFF + +#define RTL8367C_REG_FIELD_SELECTOR11 0x12f2 +#define RTL8367C_FIELD_SELECTOR11_FORMAT_OFFSET 8 +#define RTL8367C_FIELD_SELECTOR11_FORMAT_MASK 0x700 +#define RTL8367C_FIELD_SELECTOR11_OFFSET_OFFSET 0 +#define RTL8367C_FIELD_SELECTOR11_OFFSET_MASK 0xFF + +#define RTL8367C_REG_FIELD_SELECTOR12 0x12f3 +#define RTL8367C_FIELD_SELECTOR12_FORMAT_OFFSET 8 +#define RTL8367C_FIELD_SELECTOR12_FORMAT_MASK 0x700 +#define RTL8367C_FIELD_SELECTOR12_OFFSET_OFFSET 0 +#define RTL8367C_FIELD_SELECTOR12_OFFSET_MASK 0xFF + +#define RTL8367C_REG_FIELD_SELECTOR13 0x12f4 +#define RTL8367C_FIELD_SELECTOR13_FORMAT_OFFSET 8 +#define RTL8367C_FIELD_SELECTOR13_FORMAT_MASK 0x700 +#define RTL8367C_FIELD_SELECTOR13_OFFSET_OFFSET 0 +#define RTL8367C_FIELD_SELECTOR13_OFFSET_MASK 0xFF + +#define RTL8367C_REG_FIELD_SELECTOR14 0x12f5 +#define RTL8367C_FIELD_SELECTOR14_FORMAT_OFFSET 8 +#define RTL8367C_FIELD_SELECTOR14_FORMAT_MASK 0x700 +#define RTL8367C_FIELD_SELECTOR14_OFFSET_OFFSET 0 +#define RTL8367C_FIELD_SELECTOR14_OFFSET_MASK 0xFF + +#define RTL8367C_REG_FIELD_SELECTOR15 0x12f6 +#define RTL8367C_FIELD_SELECTOR15_FORMAT_OFFSET 8 +#define RTL8367C_FIELD_SELECTOR15_FORMAT_MASK 0x700 +#define RTL8367C_FIELD_SELECTOR15_OFFSET_OFFSET 0 +#define RTL8367C_FIELD_SELECTOR15_OFFSET_MASK 0xFF + +#define RTL8367C_REG_HWPKT_GEN_MISC_H 0x12f7 +#define RTL8367C_PKT_GEN_SUSPEND_P10_8_OFFSET 3 +#define RTL8367C_PKT_GEN_SUSPEND_P10_8_MASK 0x38 +#define RTL8367C_PKT_GEN_STATUS_P10_8_OFFSET 0 +#define RTL8367C_PKT_GEN_STATUS_P10_8_MASK 0x7 + +#define RTL8367C_REG_MIRROR_SRC_PMSK 0x12fb +#define RTL8367C_MIRROR_SRC_PMSK_OFFSET 0 +#define RTL8367C_MIRROR_SRC_PMSK_MASK 0x7FF + +#define RTL8367C_REG_EEE_BURSTSIZE 0x12fc + +#define RTL8367C_REG_EEE_IFG_CFG 0x12fd +#define RTL8367C_EEE_IFG_CFG_OFFSET 0 +#define RTL8367C_EEE_IFG_CFG_MASK 0x1 + +#define RTL8367C_REG_FPGA_VER_MAC 0x12fe + +#define RTL8367C_REG_HWPKT_GEN_MISC 0x12ff +#define RTL8367C_PKT_GEN_SUSPEND_OFFSET 8 +#define RTL8367C_PKT_GEN_SUSPEND_MASK 0xFF00 +#define RTL8367C_PKT_GEN_STATUS_OFFSET 0 +#define RTL8367C_PKT_GEN_STATUS_MASK 0xFF + +/* (16'h1300)chip_reg */ + +#define RTL8367C_REG_CHIP_NUMBER 0x1300 + +#define RTL8367C_REG_CHIP_VER 0x1301 +#define RTL8367C_VERID_OFFSET 12 +#define RTL8367C_VERID_MASK 0xF000 +#define RTL8367C_MCID_OFFSET 8 +#define RTL8367C_MCID_MASK 0xF00 +#define RTL8367C_MODEL_ID_OFFSET 4 +#define RTL8367C_MODEL_ID_MASK 0xF0 +#define RTL8367C_AFE_VERSION_OFFSET 0 +#define RTL8367C_AFE_VERSION_MASK 0x1 + +#define RTL8367C_REG_CHIP_DEBUG0 0x1303 +#define RTL8367C_SEL33_EXT2_OFFSET 10 +#define RTL8367C_SEL33_EXT2_MASK 0x400 +#define RTL8367C_SEL33_EXT1_OFFSET 9 +#define RTL8367C_SEL33_EXT1_MASK 0x200 +#define RTL8367C_SEL33_EXT0_OFFSET 8 +#define RTL8367C_SEL33_EXT0_MASK 0x100 +#define RTL8367C_DRI_OTHER_OFFSET 7 +#define RTL8367C_DRI_OTHER_MASK 0x80 +#define RTL8367C_DRI_EXT1_RG_OFFSET 6 +#define RTL8367C_DRI_EXT1_RG_MASK 0x40 +#define RTL8367C_DRI_EXT0_RG_OFFSET 5 +#define RTL8367C_DRI_EXT0_RG_MASK 0x20 +#define RTL8367C_DRI_EXT1_OFFSET 4 +#define RTL8367C_DRI_EXT1_MASK 0x10 +#define RTL8367C_DRI_EXT0_OFFSET 3 +#define RTL8367C_DRI_EXT0_MASK 0x8 +#define RTL8367C_SLR_OTHER_OFFSET 2 +#define RTL8367C_SLR_OTHER_MASK 0x4 +#define RTL8367C_SLR_EXT1_OFFSET 1 +#define RTL8367C_SLR_EXT1_MASK 0x2 +#define RTL8367C_SLR_EXT0_OFFSET 0 +#define RTL8367C_SLR_EXT0_MASK 0x1 + +#define RTL8367C_REG_CHIP_DEBUG1 0x1304 +#define RTL8367C_RG1_DN_OFFSET 12 +#define RTL8367C_RG1_DN_MASK 0x7000 +#define RTL8367C_RG1_DP_OFFSET 8 +#define RTL8367C_RG1_DP_MASK 0x700 +#define RTL8367C_RG0_DN_OFFSET 4 +#define RTL8367C_RG0_DN_MASK 0x70 +#define RTL8367C_RG0_DP_OFFSET 0 +#define RTL8367C_RG0_DP_MASK 0x7 + +#define RTL8367C_REG_DIGITAL_INTERFACE_SELECT 0x1305 +#define RTL8367C_ORG_COL_OFFSET 15 +#define RTL8367C_ORG_COL_MASK 0x8000 +#define RTL8367C_ORG_CRS_OFFSET 14 +#define RTL8367C_ORG_CRS_MASK 0x4000 +#define RTL8367C_SKIP_MII_1_RXER_OFFSET 13 +#define RTL8367C_SKIP_MII_1_RXER_MASK 0x2000 +#define RTL8367C_SKIP_MII_0_RXER_OFFSET 12 +#define RTL8367C_SKIP_MII_0_RXER_MASK 0x1000 +#define RTL8367C_SELECT_GMII_1_OFFSET 4 +#define RTL8367C_SELECT_GMII_1_MASK 0xF0 +#define RTL8367C_SELECT_GMII_0_OFFSET 0 +#define RTL8367C_SELECT_GMII_0_MASK 0xF + +#define RTL8367C_REG_EXT0_RGMXF 0x1306 +#define RTL8367C_EXT0_RGTX_INV_OFFSET 6 +#define RTL8367C_EXT0_RGTX_INV_MASK 0x40 +#define RTL8367C_EXT0_RGRX_INV_OFFSET 5 +#define RTL8367C_EXT0_RGRX_INV_MASK 0x20 +#define RTL8367C_EXT0_RGMXF_OFFSET 0 +#define RTL8367C_EXT0_RGMXF_MASK 0x1F + +#define RTL8367C_REG_EXT1_RGMXF 0x1307 +#define RTL8367C_EXT1_RGTX_INV_OFFSET 6 +#define RTL8367C_EXT1_RGTX_INV_MASK 0x40 +#define RTL8367C_EXT1_RGRX_INV_OFFSET 5 +#define RTL8367C_EXT1_RGRX_INV_MASK 0x20 +#define RTL8367C_EXT1_RGMXF_OFFSET 0 +#define RTL8367C_EXT1_RGMXF_MASK 0x1F + +#define RTL8367C_REG_BISR_CTRL 0x1308 +#define RTL8367C_BISR_CTRL_OFFSET 0 +#define RTL8367C_BISR_CTRL_MASK 0x7 + +#define RTL8367C_REG_SLF_IF 0x1309 +#define RTL8367C_LINK_DOWN_CLR_FIFO_OFFSET 7 +#define RTL8367C_LINK_DOWN_CLR_FIFO_MASK 0x80 +#define RTL8367C_LOOPBACK_OFFSET 6 +#define RTL8367C_LOOPBACK_MASK 0x40 +#define RTL8367C_WATER_LEVEL_OFFSET 4 +#define RTL8367C_WATER_LEVEL_MASK 0x30 +#define RTL8367C_SLF_IF_OFFSET 0 +#define RTL8367C_SLF_IF_MASK 0x3 + +#define RTL8367C_REG_I2C_CLOCK_DIV 0x130a +#define RTL8367C_I2C_CLOCK_DIV_OFFSET 0 +#define RTL8367C_I2C_CLOCK_DIV_MASK 0x3FF + +#define RTL8367C_REG_MDX_MDC_DIV 0x130b +#define RTL8367C_MDX_MDC_DIV_OFFSET 0 +#define RTL8367C_MDX_MDC_DIV_MASK 0x3FF + +#define RTL8367C_REG_MISCELLANEOUS_CONFIGURE0 0x130c +#define RTL8367C_ADCCKI_FROM_PAD_OFFSET 14 +#define RTL8367C_ADCCKI_FROM_PAD_MASK 0x4000 +#define RTL8367C_ADCCKI_EN_OFFSET 13 +#define RTL8367C_ADCCKI_EN_MASK 0x2000 +#define RTL8367C_FLASH_ENABLE_OFFSET 12 +#define RTL8367C_FLASH_ENABLE_MASK 0x1000 +#define RTL8367C_EEE_ENABLE_OFFSET 11 +#define RTL8367C_EEE_ENABLE_MASK 0x800 +#define RTL8367C_NIC_ENABLE_OFFSET 10 +#define RTL8367C_NIC_ENABLE_MASK 0x400 +#define RTL8367C_FT_ENABLE_OFFSET 9 +#define RTL8367C_FT_ENABLE_MASK 0x200 +#define RTL8367C_OLT_ENABLE_OFFSET 8 +#define RTL8367C_OLT_ENABLE_MASK 0x100 +#define RTL8367C_RTCT_EN_OFFSET 7 +#define RTL8367C_RTCT_EN_MASK 0x80 +#define RTL8367C_PON_LIGHT_EN_OFFSET 6 +#define RTL8367C_PON_LIGHT_EN_MASK 0x40 +#define RTL8367C_DW8051_EN_OFFSET 5 +#define RTL8367C_DW8051_EN_MASK 0x20 +#define RTL8367C_AUTOLOAD_EN_OFFSET 4 +#define RTL8367C_AUTOLOAD_EN_MASK 0x10 +#define RTL8367C_NRESTORE_EN_OFFSET 3 +#define RTL8367C_NRESTORE_EN_MASK 0x8 +#define RTL8367C_DIS_PON_TABLE_INIT_OFFSET 2 +#define RTL8367C_DIS_PON_TABLE_INIT_MASK 0x4 +#define RTL8367C_DIS_PON_BIST_OFFSET 1 +#define RTL8367C_DIS_PON_BIST_MASK 0x2 +#define RTL8367C_EFUSE_EN_OFFSET 0 +#define RTL8367C_EFUSE_EN_MASK 0x1 + +#define RTL8367C_REG_MISCELLANEOUS_CONFIGURE1 0x130d +#define RTL8367C_EEPROM_DEV_ADR_OFFSET 8 +#define RTL8367C_EEPROM_DEV_ADR_MASK 0x7F00 +#define RTL8367C_EEPROM_MSB_OFFSET 7 +#define RTL8367C_EEPROM_MSB_MASK 0x80 +#define RTL8367C_EEPROM_ADDRESS_16B_OFFSET 6 +#define RTL8367C_EEPROM_ADDRESS_16B_MASK 0x40 +#define RTL8367C_EEPROM_DWONLOAD_COMPLETE_OFFSET 3 +#define RTL8367C_EEPROM_DWONLOAD_COMPLETE_MASK 0x8 +#define RTL8367C_SPI_SLAVE_EN_OFFSET 2 +#define RTL8367C_SPI_SLAVE_EN_MASK 0x4 +#define RTL8367C_SMI_SEL_OFFSET 0 +#define RTL8367C_SMI_SEL_MASK 0x3 + +#define RTL8367C_REG_PHY_AD 0x130f +#define RTL8367C_EN_PHY_MAX_POWER_OFFSET 14 +#define RTL8367C_EN_PHY_MAX_POWER_MASK 0x4000 +#define RTL8367C_EN_PHY_SEL_DEG_OFFSET 13 +#define RTL8367C_EN_PHY_SEL_DEG_MASK 0x2000 +#define RTL8367C_EXTPHY_AD_OFFSET 8 +#define RTL8367C_EXTPHY_AD_MASK 0x1F00 +#define RTL8367C_EN_PHY_LOW_POWER_MODE_OFFSET 7 +#define RTL8367C_EN_PHY_LOW_POWER_MODE_MASK 0x80 +#define RTL8367C_EN_PHY_GREEN_OFFSET 6 +#define RTL8367C_EN_PHY_GREEN_MASK 0x40 +#define RTL8367C_PDNPHY_OFFSET 5 +#define RTL8367C_PDNPHY_MASK 0x20 +#define RTL8367C_INTPHY_AD_OFFSET 0 +#define RTL8367C_INTPHY_AD_MASK 0x1F + +#define RTL8367C_REG_DIGITAL_INTERFACE0_FORCE 0x1310 +#define RTL8367C_GMII_0_FORCE_OFFSET 12 +#define RTL8367C_GMII_0_FORCE_MASK 0x1000 +#define RTL8367C_RGMII_0_FORCE_OFFSET 0 +#define RTL8367C_RGMII_0_FORCE_MASK 0xFFF + +#define RTL8367C_REG_DIGITAL_INTERFACE1_FORCE 0x1311 +#define RTL8367C_GMII_1_FORCE_OFFSET 12 +#define RTL8367C_GMII_1_FORCE_MASK 0x1000 +#define RTL8367C_RGMII_1_FORCE_OFFSET 0 +#define RTL8367C_RGMII_1_FORCE_MASK 0xFFF + +#define RTL8367C_REG_MAC0_FORCE_SELECT 0x1312 +#define RTL8367C_EN_MAC0_FORCE_OFFSET 12 +#define RTL8367C_EN_MAC0_FORCE_MASK 0x1000 +#define RTL8367C_MAC0_FORCE_ABLTY_OFFSET 0 +#define RTL8367C_MAC0_FORCE_ABLTY_MASK 0xFFF + +#define RTL8367C_REG_MAC1_FORCE_SELECT 0x1313 +#define RTL8367C_EN_MAC1_FORCE_OFFSET 12 +#define RTL8367C_EN_MAC1_FORCE_MASK 0x1000 +#define RTL8367C_MAC1_FORCE_ABLTY_OFFSET 0 +#define RTL8367C_MAC1_FORCE_ABLTY_MASK 0xFFF + +#define RTL8367C_REG_MAC2_FORCE_SELECT 0x1314 +#define RTL8367C_EN_MAC2_FORCE_OFFSET 12 +#define RTL8367C_EN_MAC2_FORCE_MASK 0x1000 +#define RTL8367C_MAC2_FORCE_ABLTY_OFFSET 0 +#define RTL8367C_MAC2_FORCE_ABLTY_MASK 0xFFF + +#define RTL8367C_REG_MAC3_FORCE_SELECT 0x1315 +#define RTL8367C_EN_MAC3_FORCE_OFFSET 12 +#define RTL8367C_EN_MAC3_FORCE_MASK 0x1000 +#define RTL8367C_MAC3_FORCE_ABLTY_OFFSET 0 +#define RTL8367C_MAC3_FORCE_ABLTY_MASK 0xFFF + +#define RTL8367C_REG_MAC4_FORCE_SELECT 0x1316 +#define RTL8367C_EN_MAC4_FORCE_OFFSET 12 +#define RTL8367C_EN_MAC4_FORCE_MASK 0x1000 +#define RTL8367C_MAC4_FORCE_ABLTY_OFFSET 0 +#define RTL8367C_MAC4_FORCE_ABLTY_MASK 0xFFF + +#define RTL8367C_REG_MAC5_FORCE_SELECT 0x1317 +#define RTL8367C_EN_MAC5_FORCE_OFFSET 12 +#define RTL8367C_EN_MAC5_FORCE_MASK 0x1000 +#define RTL8367C_MAC5_FORCE_ABLTY_OFFSET 0 +#define RTL8367C_MAC5_FORCE_ABLTY_MASK 0xFFF + +#define RTL8367C_REG_MAC6_FORCE_SELECT 0x1318 +#define RTL8367C_EN_MAC6_FORCE_OFFSET 12 +#define RTL8367C_EN_MAC6_FORCE_MASK 0x1000 +#define RTL8367C_MAC6_FORCE_ABLTY_OFFSET 0 +#define RTL8367C_MAC6_FORCE_ABLTY_MASK 0xFFF + +#define RTL8367C_REG_MAC7_FORCE_SELECT 0x1319 +#define RTL8367C_EN_MAC7_FORCE_OFFSET 12 +#define RTL8367C_EN_MAC7_FORCE_MASK 0x1000 +#define RTL8367C_MAC7_FORCE_ABLTY_OFFSET 0 +#define RTL8367C_MAC7_FORCE_ABLTY_MASK 0xFFF + +#define RTL8367C_REG_M10_FORCE_SELECT 0x131c +#define RTL8367C_EN_M10_FORCE_OFFSET 12 +#define RTL8367C_EN_M10_FORCE_MASK 0x1000 +#define RTL8367C_M10_FORCE_ABLTY_OFFSET 0 +#define RTL8367C_M10_FORCE_ABLTY_MASK 0xFFF + +#define RTL8367C_REG_CHIP_RESET 0x1322 +#define RTL8367C_GPHY_RESET_OFFSET 6 +#define RTL8367C_GPHY_RESET_MASK 0x40 +#define RTL8367C_NIC_RST_OFFSET 5 +#define RTL8367C_NIC_RST_MASK 0x20 +#define RTL8367C_DW8051_RST_OFFSET 4 +#define RTL8367C_DW8051_RST_MASK 0x10 +#define RTL8367C_SDS_RST_OFFSET 3 +#define RTL8367C_SDS_RST_MASK 0x8 +#define RTL8367C_CONFIG_RST_OFFSET 2 +#define RTL8367C_CONFIG_RST_MASK 0x4 +#define RTL8367C_SW_RST_OFFSET 1 +#define RTL8367C_SW_RST_MASK 0x2 +#define RTL8367C_CHIP_RST_OFFSET 0 +#define RTL8367C_CHIP_RST_MASK 0x1 + +#define RTL8367C_REG_DIGITAL_DEBUG_0 0x1323 + +#define RTL8367C_REG_DIGITAL_DEBUG_1 0x1324 + +#define RTL8367C_REG_INTERNAL_PHY_MDC_DRIVER 0x1325 +#define RTL8367C_INTERNAL_PHY_MDC_DRIVER_OFFSET 0 +#define RTL8367C_INTERNAL_PHY_MDC_DRIVER_MASK 0x3FF + +#define RTL8367C_REG_LINKDOWN_TIME_CTRL 0x1326 +#define RTL8367C_LINKDOWN_TIME_CFG_OFFSET 9 +#define RTL8367C_LINKDOWN_TIME_CFG_MASK 0x7E00 +#define RTL8367C_LINKDOWN_TIME_ENABLE_OFFSET 8 +#define RTL8367C_LINKDOWN_TIME_ENABLE_MASK 0x100 +#define RTL8367C_LINKDOWN_TIME_OFFSET 0 +#define RTL8367C_LINKDOWN_TIME_MASK 0xFF + +#define RTL8367C_REG_PHYACK_TIMEOUT 0x1331 + +#define RTL8367C_REG_MDXACK_TIMEOUT 0x1333 + +#define RTL8367C_REG_DW8051_RDY 0x1336 +#define RTL8367C_VIAROM_WRITE_EN_OFFSET 9 +#define RTL8367C_VIAROM_WRITE_EN_MASK 0x200 +#define RTL8367C_SPIF_CK2_OFFSET 8 +#define RTL8367C_SPIF_CK2_MASK 0x100 +#define RTL8367C_RRCP_MDOE_OFFSET 7 +#define RTL8367C_RRCP_MDOE_MASK 0x80 +#define RTL8367C_DW8051_RATE_OFFSET 4 +#define RTL8367C_DW8051_RATE_MASK 0x70 +#define RTL8367C_IROM_MSB_OFFSET 2 +#define RTL8367C_IROM_MSB_MASK 0xC +#define RTL8367C_ACS_IROM_ENABLE_OFFSET 1 +#define RTL8367C_ACS_IROM_ENABLE_MASK 0x2 +#define RTL8367C_DW8051_READY_OFFSET 0 +#define RTL8367C_DW8051_READY_MASK 0x1 + +#define RTL8367C_REG_BIST_CTRL 0x133c +#define RTL8367C_DRF_BIST_DONE_ALL_OFFSET 5 +#define RTL8367C_DRF_BIST_DONE_ALL_MASK 0x20 +#define RTL8367C_DRF_BIST_PAUSE_ALL_OFFSET 4 +#define RTL8367C_DRF_BIST_PAUSE_ALL_MASK 0x10 +#define RTL8367C_BIST_DOAN_ALL_OFFSET 3 +#define RTL8367C_BIST_DOAN_ALL_MASK 0x8 +#define RTL8367C_BIST_PASS_OFFSET 0 +#define RTL8367C_BIST_PASS_MASK 0x7 + +#define RTL8367C_REG_DIAG_MODE2 0x133d +#define RTL8367C_DIAG_MODE2_ACTRAM_OFFSET 1 +#define RTL8367C_DIAG_MODE2_ACTRAM_MASK 0x2 +#define RTL8367C_DIAG_MODE2_BCAM_ACTION_OFFSET 0 +#define RTL8367C_DIAG_MODE2_BCAM_ACTION_MASK 0x1 + +#define RTL8367C_REG_MDX_PHY_REG0 0x133e +#define RTL8367C_PHY_BRD_MASK_OFFSET 4 +#define RTL8367C_PHY_BRD_MASK_MASK 0x1F0 +#define RTL8367C_MDX_INDACC_PAGE_OFFSET 0 +#define RTL8367C_MDX_INDACC_PAGE_MASK 0xF + +#define RTL8367C_REG_MDX_PHY_REG1 0x133f +#define RTL8367C_PHY_BRD_MODE_OFFSET 5 +#define RTL8367C_PHY_BRD_MODE_MASK 0x20 +#define RTL8367C_BRD_PHYAD_OFFSET 0 +#define RTL8367C_BRD_PHYAD_MASK 0x1F + +#define RTL8367C_REG_DEBUG_SIGNAL_SELECT_SW 0x1340 + +#define RTL8367C_REG_DEBUG_SIGNAL_SELECT_B 0x1341 +#define RTL8367C_DEBUG_MX_OFFSET 9 +#define RTL8367C_DEBUG_MX_MASK 0xE00 +#define RTL8367C_DEBUG_SHIFT_MISC_OFFSET 6 +#define RTL8367C_DEBUG_SHIFT_MISC_MASK 0x1C0 +#define RTL8367C_DEBUG_SHIFT_SW_OFFSET 3 +#define RTL8367C_DEBUG_SHIFT_SW_MASK 0x38 +#define RTL8367C_DEBUG_SHIFT_GPHY_OFFSET 0 +#define RTL8367C_DEBUG_SHIFT_GPHY_MASK 0x7 + +#define RTL8367C_REG_DEBUG_SIGNAL_I 0x1343 + +#define RTL8367C_REG_DEBUG_SIGNAL_H 0x1344 + +#define RTL8367C_REG_DBGO_SEL_GPHY 0x1345 + +#define RTL8367C_REG_DBGO_SEL_MISC 0x1346 + +#define RTL8367C_REG_BYPASS_ABLTY_LOCK 0x1349 +#define RTL8367C_BYPASS_ABLTY_LOCK_OFFSET 0 +#define RTL8367C_BYPASS_ABLTY_LOCK_MASK 0xFF + +#define RTL8367C_REG_BYPASS_ABLTY_LOCK_EXT 0x134a +#define RTL8367C_BYPASS_P10_ABILIITY_LOCK_OFFSET 3 +#define RTL8367C_BYPASS_P10_ABILIITY_LOCK_MASK 0x8 +#define RTL8367C_BYPASS_EXT_ABILITY_LOCK_OFFSET 0 +#define RTL8367C_BYPASS_EXT_ABILITY_LOCK_MASK 0x7 + +#define RTL8367C_REG_ACL_GPIO 0x134f +#define RTL8367C_ACL_GPIO_13_OFFSET 13 +#define RTL8367C_ACL_GPIO_13_MASK 0x2000 +#define RTL8367C_ACL_GPIO_12_OFFSET 12 +#define RTL8367C_ACL_GPIO_12_MASK 0x1000 +#define RTL8367C_ACL_GPIO_11_OFFSET 11 +#define RTL8367C_ACL_GPIO_11_MASK 0x800 +#define RTL8367C_ACL_GPIO_10_OFFSET 10 +#define RTL8367C_ACL_GPIO_10_MASK 0x400 +#define RTL8367C_ACL_GPIO_9_OFFSET 9 +#define RTL8367C_ACL_GPIO_9_MASK 0x200 +#define RTL8367C_ACL_GPIO_8_OFFSET 8 +#define RTL8367C_ACL_GPIO_8_MASK 0x100 +#define RTL8367C_ACL_GPIO_7_OFFSET 7 +#define RTL8367C_ACL_GPIO_7_MASK 0x80 +#define RTL8367C_ACL_GPIO_6_OFFSET 6 +#define RTL8367C_ACL_GPIO_6_MASK 0x40 +#define RTL8367C_ACL_GPIO_5_OFFSET 5 +#define RTL8367C_ACL_GPIO_5_MASK 0x20 +#define RTL8367C_ACL_GPIO_4_OFFSET 4 +#define RTL8367C_ACL_GPIO_4_MASK 0x10 +#define RTL8367C_ACL_GPIO_3_OFFSET 3 +#define RTL8367C_ACL_GPIO_3_MASK 0x8 +#define RTL8367C_ACL_GPIO_2_OFFSET 2 +#define RTL8367C_ACL_GPIO_2_MASK 0x4 +#define RTL8367C_ACL_GPIO_1_OFFSET 1 +#define RTL8367C_ACL_GPIO_1_MASK 0x2 +#define RTL8367C_ACL_GPIO_0_OFFSET 0 +#define RTL8367C_ACL_GPIO_0_MASK 0x1 + +#define RTL8367C_REG_EN_GPIO 0x1350 +#define RTL8367C_EN_GPIO_13_OFFSET 13 +#define RTL8367C_EN_GPIO_13_MASK 0x2000 +#define RTL8367C_EN_GPIO_12_OFFSET 12 +#define RTL8367C_EN_GPIO_12_MASK 0x1000 +#define RTL8367C_EN_GPIO_11_OFFSET 11 +#define RTL8367C_EN_GPIO_11_MASK 0x800 +#define RTL8367C_EN_GPIO_10_OFFSET 10 +#define RTL8367C_EN_GPIO_10_MASK 0x400 +#define RTL8367C_EN_GPIO_9_OFFSET 9 +#define RTL8367C_EN_GPIO_9_MASK 0x200 +#define RTL8367C_EN_GPIO_8_OFFSET 8 +#define RTL8367C_EN_GPIO_8_MASK 0x100 +#define RTL8367C_EN_GPIO_7_OFFSET 7 +#define RTL8367C_EN_GPIO_7_MASK 0x80 +#define RTL8367C_EN_GPIO_6_OFFSET 6 +#define RTL8367C_EN_GPIO_6_MASK 0x40 +#define RTL8367C_EN_GPIO_5_OFFSET 5 +#define RTL8367C_EN_GPIO_5_MASK 0x20 +#define RTL8367C_EN_GPIO_4_OFFSET 4 +#define RTL8367C_EN_GPIO_4_MASK 0x10 +#define RTL8367C_EN_GPIO_3_OFFSET 3 +#define RTL8367C_EN_GPIO_3_MASK 0x8 +#define RTL8367C_EN_GPIO_2_OFFSET 2 +#define RTL8367C_EN_GPIO_2_MASK 0x4 +#define RTL8367C_EN_GPIO_1_OFFSET 1 +#define RTL8367C_EN_GPIO_1_MASK 0x2 +#define RTL8367C_EN_GPIO_0_OFFSET 0 +#define RTL8367C_EN_GPIO_0_MASK 0x1 + +#define RTL8367C_REG_CFG_MULTI_PIN 0x1351 +#define RTL8367C_CFG_MULTI_PIN_OFFSET 0 +#define RTL8367C_CFG_MULTI_PIN_MASK 0x3 + +#define RTL8367C_REG_PORT0_STATUS 0x1352 +#define RTL8367C_PORT0_STATUS_EN_1000_LPI_OFFSET 11 +#define RTL8367C_PORT0_STATUS_EN_1000_LPI_MASK 0x800 +#define RTL8367C_PORT0_STATUS_EN_100_LPI_OFFSET 10 +#define RTL8367C_PORT0_STATUS_EN_100_LPI_MASK 0x400 +#define RTL8367C_PORT0_STATUS_NWAY_FAULT_OFFSET 9 +#define RTL8367C_PORT0_STATUS_NWAY_FAULT_MASK 0x200 +#define RTL8367C_PORT0_STATUS_LINK_ON_MASTER_OFFSET 8 +#define RTL8367C_PORT0_STATUS_LINK_ON_MASTER_MASK 0x100 +#define RTL8367C_PORT0_STATUS_NWAY_CAP_OFFSET 7 +#define RTL8367C_PORT0_STATUS_NWAY_CAP_MASK 0x80 +#define RTL8367C_PORT0_STATUS_TX_FLOWCTRL_CAP_OFFSET 6 +#define RTL8367C_PORT0_STATUS_TX_FLOWCTRL_CAP_MASK 0x40 +#define RTL8367C_PORT0_STATUS_RX_FLOWCTRL_CAP_OFFSET 5 +#define RTL8367C_PORT0_STATUS_RX_FLOWCTRL_CAP_MASK 0x20 +#define RTL8367C_PORT0_STATUS_LINK_STATE_OFFSET 4 +#define RTL8367C_PORT0_STATUS_LINK_STATE_MASK 0x10 +#define RTL8367C_PORT0_STATUS_FULL_DUPLUX_CAP_OFFSET 2 +#define RTL8367C_PORT0_STATUS_FULL_DUPLUX_CAP_MASK 0x4 +#define RTL8367C_PORT0_STATUS_LINK_SPEED_OFFSET 0 +#define RTL8367C_PORT0_STATUS_LINK_SPEED_MASK 0x3 + +#define RTL8367C_REG_PORT1_STATUS 0x1353 +#define RTL8367C_PORT1_STATUS_EN_1000_LPI_OFFSET 11 +#define RTL8367C_PORT1_STATUS_EN_1000_LPI_MASK 0x800 +#define RTL8367C_PORT1_STATUS_EN_100_LPI_OFFSET 10 +#define RTL8367C_PORT1_STATUS_EN_100_LPI_MASK 0x400 +#define RTL8367C_PORT1_STATUS_NWAY_FAULT_OFFSET 9 +#define RTL8367C_PORT1_STATUS_NWAY_FAULT_MASK 0x200 +#define RTL8367C_PORT1_STATUS_LINK_ON_MASTER_OFFSET 8 +#define RTL8367C_PORT1_STATUS_LINK_ON_MASTER_MASK 0x100 +#define RTL8367C_PORT1_STATUS_NWAY_CAP_OFFSET 7 +#define RTL8367C_PORT1_STATUS_NWAY_CAP_MASK 0x80 +#define RTL8367C_PORT1_STATUS_TX_FLOWCTRL_CAP_OFFSET 6 +#define RTL8367C_PORT1_STATUS_TX_FLOWCTRL_CAP_MASK 0x40 +#define RTL8367C_PORT1_STATUS_RX_FLOWCTRL_CAP_OFFSET 5 +#define RTL8367C_PORT1_STATUS_RX_FLOWCTRL_CAP_MASK 0x20 +#define RTL8367C_PORT1_STATUS_LINK_STATE_OFFSET 4 +#define RTL8367C_PORT1_STATUS_LINK_STATE_MASK 0x10 +#define RTL8367C_PORT1_STATUS_FULL_DUPLUX_CAP_OFFSET 2 +#define RTL8367C_PORT1_STATUS_FULL_DUPLUX_CAP_MASK 0x4 +#define RTL8367C_PORT1_STATUS_LINK_SPEED_OFFSET 0 +#define RTL8367C_PORT1_STATUS_LINK_SPEED_MASK 0x3 + +#define RTL8367C_REG_PORT2_STATUS 0x1354 +#define RTL8367C_PORT2_STATUS_EN_1000_LPI_OFFSET 11 +#define RTL8367C_PORT2_STATUS_EN_1000_LPI_MASK 0x800 +#define RTL8367C_PORT2_STATUS_EN_100_LPI_OFFSET 10 +#define RTL8367C_PORT2_STATUS_EN_100_LPI_MASK 0x400 +#define RTL8367C_PORT2_STATUS_NWAY_FAULT_OFFSET 9 +#define RTL8367C_PORT2_STATUS_NWAY_FAULT_MASK 0x200 +#define RTL8367C_PORT2_STATUS_LINK_ON_MASTER_OFFSET 8 +#define RTL8367C_PORT2_STATUS_LINK_ON_MASTER_MASK 0x100 +#define RTL8367C_PORT2_STATUS_NWAY_CAP_OFFSET 7 +#define RTL8367C_PORT2_STATUS_NWAY_CAP_MASK 0x80 +#define RTL8367C_PORT2_STATUS_TX_FLOWCTRL_CAP_OFFSET 6 +#define RTL8367C_PORT2_STATUS_TX_FLOWCTRL_CAP_MASK 0x40 +#define RTL8367C_PORT2_STATUS_RX_FLOWCTRL_CAP_OFFSET 5 +#define RTL8367C_PORT2_STATUS_RX_FLOWCTRL_CAP_MASK 0x20 +#define RTL8367C_PORT2_STATUS_LINK_STATE_OFFSET 4 +#define RTL8367C_PORT2_STATUS_LINK_STATE_MASK 0x10 +#define RTL8367C_PORT2_STATUS_FULL_DUPLUX_CAP_OFFSET 2 +#define RTL8367C_PORT2_STATUS_FULL_DUPLUX_CAP_MASK 0x4 +#define RTL8367C_PORT2_STATUS_LINK_SPEED_OFFSET 0 +#define RTL8367C_PORT2_STATUS_LINK_SPEED_MASK 0x3 + +#define RTL8367C_REG_PORT3_STATUS 0x1355 +#define RTL8367C_PORT3_STATUS_EN_1000_LPI_OFFSET 11 +#define RTL8367C_PORT3_STATUS_EN_1000_LPI_MASK 0x800 +#define RTL8367C_PORT3_STATUS_EN_100_LPI_OFFSET 10 +#define RTL8367C_PORT3_STATUS_EN_100_LPI_MASK 0x400 +#define RTL8367C_PORT3_STATUS_NWAY_FAULT_OFFSET 9 +#define RTL8367C_PORT3_STATUS_NWAY_FAULT_MASK 0x200 +#define RTL8367C_PORT3_STATUS_LINK_ON_MASTER_OFFSET 8 +#define RTL8367C_PORT3_STATUS_LINK_ON_MASTER_MASK 0x100 +#define RTL8367C_PORT3_STATUS_NWAY_CAP_OFFSET 7 +#define RTL8367C_PORT3_STATUS_NWAY_CAP_MASK 0x80 +#define RTL8367C_PORT3_STATUS_TX_FLOWCTRL_CAP_OFFSET 6 +#define RTL8367C_PORT3_STATUS_TX_FLOWCTRL_CAP_MASK 0x40 +#define RTL8367C_PORT3_STATUS_RX_FLOWCTRL_CAP_OFFSET 5 +#define RTL8367C_PORT3_STATUS_RX_FLOWCTRL_CAP_MASK 0x20 +#define RTL8367C_PORT3_STATUS_LINK_STATE_OFFSET 4 +#define RTL8367C_PORT3_STATUS_LINK_STATE_MASK 0x10 +#define RTL8367C_PORT3_STATUS_FULL_DUPLUX_CAP_OFFSET 2 +#define RTL8367C_PORT3_STATUS_FULL_DUPLUX_CAP_MASK 0x4 +#define RTL8367C_PORT3_STATUS_LINK_SPEED_OFFSET 0 +#define RTL8367C_PORT3_STATUS_LINK_SPEED_MASK 0x3 + +#define RTL8367C_REG_PORT4_STATUS 0x1356 +#define RTL8367C_PORT4_STATUS_EN_1000_LPI_OFFSET 11 +#define RTL8367C_PORT4_STATUS_EN_1000_LPI_MASK 0x800 +#define RTL8367C_PORT4_STATUS_EN_100_LPI_OFFSET 10 +#define RTL8367C_PORT4_STATUS_EN_100_LPI_MASK 0x400 +#define RTL8367C_PORT4_STATUS_NWAY_FAULT_OFFSET 9 +#define RTL8367C_PORT4_STATUS_NWAY_FAULT_MASK 0x200 +#define RTL8367C_PORT4_STATUS_LINK_ON_MASTER_OFFSET 8 +#define RTL8367C_PORT4_STATUS_LINK_ON_MASTER_MASK 0x100 +#define RTL8367C_PORT4_STATUS_NWAY_CAP_OFFSET 7 +#define RTL8367C_PORT4_STATUS_NWAY_CAP_MASK 0x80 +#define RTL8367C_PORT4_STATUS_TX_FLOWCTRL_CAP_OFFSET 6 +#define RTL8367C_PORT4_STATUS_TX_FLOWCTRL_CAP_MASK 0x40 +#define RTL8367C_PORT4_STATUS_RX_FLOWCTRL_CAP_OFFSET 5 +#define RTL8367C_PORT4_STATUS_RX_FLOWCTRL_CAP_MASK 0x20 +#define RTL8367C_PORT4_STATUS_LINK_STATE_OFFSET 4 +#define RTL8367C_PORT4_STATUS_LINK_STATE_MASK 0x10 +#define RTL8367C_PORT4_STATUS_FULL_DUPLUX_CAP_OFFSET 2 +#define RTL8367C_PORT4_STATUS_FULL_DUPLUX_CAP_MASK 0x4 +#define RTL8367C_PORT4_STATUS_LINK_SPEED_OFFSET 0 +#define RTL8367C_PORT4_STATUS_LINK_SPEED_MASK 0x3 + +#define RTL8367C_REG_PORT5_STATUS 0x1357 +#define RTL8367C_PORT5_STATUS_EN_1000_LPI_OFFSET 11 +#define RTL8367C_PORT5_STATUS_EN_1000_LPI_MASK 0x800 +#define RTL8367C_PORT5_STATUS_EN_100_LPI_OFFSET 10 +#define RTL8367C_PORT5_STATUS_EN_100_LPI_MASK 0x400 +#define RTL8367C_PORT5_STATUS_NWAY_FAULT_OFFSET 9 +#define RTL8367C_PORT5_STATUS_NWAY_FAULT_MASK 0x200 +#define RTL8367C_PORT5_STATUS_LINK_ON_MASTER_OFFSET 8 +#define RTL8367C_PORT5_STATUS_LINK_ON_MASTER_MASK 0x100 +#define RTL8367C_PORT5_STATUS_NWAY_CAP_OFFSET 7 +#define RTL8367C_PORT5_STATUS_NWAY_CAP_MASK 0x80 +#define RTL8367C_PORT5_STATUS_TX_FLOWCTRL_CAP_OFFSET 6 +#define RTL8367C_PORT5_STATUS_TX_FLOWCTRL_CAP_MASK 0x40 +#define RTL8367C_PORT5_STATUS_RX_FLOWCTRL_CAP_OFFSET 5 +#define RTL8367C_PORT5_STATUS_RX_FLOWCTRL_CAP_MASK 0x20 +#define RTL8367C_PORT5_STATUS_LINK_STATE_OFFSET 4 +#define RTL8367C_PORT5_STATUS_LINK_STATE_MASK 0x10 +#define RTL8367C_PORT5_STATUS_FULL_DUPLUX_CAP_OFFSET 2 +#define RTL8367C_PORT5_STATUS_FULL_DUPLUX_CAP_MASK 0x4 +#define RTL8367C_PORT5_STATUS_LINK_SPEED_OFFSET 0 +#define RTL8367C_PORT5_STATUS_LINK_SPEED_MASK 0x3 + +#define RTL8367C_REG_PORT6_STATUS 0x1358 +#define RTL8367C_PORT6_STATUS_EN_1000_LPI_OFFSET 11 +#define RTL8367C_PORT6_STATUS_EN_1000_LPI_MASK 0x800 +#define RTL8367C_PORT6_STATUS_EN_100_LPI_OFFSET 10 +#define RTL8367C_PORT6_STATUS_EN_100_LPI_MASK 0x400 +#define RTL8367C_PORT6_STATUS_NWAY_FAULT_OFFSET 9 +#define RTL8367C_PORT6_STATUS_NWAY_FAULT_MASK 0x200 +#define RTL8367C_PORT6_STATUS_LINK_ON_MASTER_OFFSET 8 +#define RTL8367C_PORT6_STATUS_LINK_ON_MASTER_MASK 0x100 +#define RTL8367C_PORT6_STATUS_NWAY_CAP_OFFSET 7 +#define RTL8367C_PORT6_STATUS_NWAY_CAP_MASK 0x80 +#define RTL8367C_PORT6_STATUS_TX_FLOWCTRL_CAP_OFFSET 6 +#define RTL8367C_PORT6_STATUS_TX_FLOWCTRL_CAP_MASK 0x40 +#define RTL8367C_PORT6_STATUS_RX_FLOWCTRL_CAP_OFFSET 5 +#define RTL8367C_PORT6_STATUS_RX_FLOWCTRL_CAP_MASK 0x20 +#define RTL8367C_PORT6_STATUS_LINK_STATE_OFFSET 4 +#define RTL8367C_PORT6_STATUS_LINK_STATE_MASK 0x10 +#define RTL8367C_PORT6_STATUS_FULL_DUPLUX_CAP_OFFSET 2 +#define RTL8367C_PORT6_STATUS_FULL_DUPLUX_CAP_MASK 0x4 +#define RTL8367C_PORT6_STATUS_LINK_SPEED_OFFSET 0 +#define RTL8367C_PORT6_STATUS_LINK_SPEED_MASK 0x3 + +#define RTL8367C_REG_PORT7_STATUS 0x1359 +#define RTL8367C_PORT7_STATUS_EN_1000_LPI_OFFSET 11 +#define RTL8367C_PORT7_STATUS_EN_1000_LPI_MASK 0x800 +#define RTL8367C_PORT7_STATUS_EN_100_LPI_OFFSET 10 +#define RTL8367C_PORT7_STATUS_EN_100_LPI_MASK 0x400 +#define RTL8367C_PORT7_STATUS_NWAY_FAULT_OFFSET 9 +#define RTL8367C_PORT7_STATUS_NWAY_FAULT_MASK 0x200 +#define RTL8367C_PORT7_STATUS_LINK_ON_MASTER_OFFSET 8 +#define RTL8367C_PORT7_STATUS_LINK_ON_MASTER_MASK 0x100 +#define RTL8367C_PORT7_STATUS_NWAY_CAP_OFFSET 7 +#define RTL8367C_PORT7_STATUS_NWAY_CAP_MASK 0x80 +#define RTL8367C_PORT7_STATUS_TX_FLOWCTRL_CAP_OFFSET 6 +#define RTL8367C_PORT7_STATUS_TX_FLOWCTRL_CAP_MASK 0x40 +#define RTL8367C_PORT7_STATUS_RX_FLOWCTRL_CAP_OFFSET 5 +#define RTL8367C_PORT7_STATUS_RX_FLOWCTRL_CAP_MASK 0x20 +#define RTL8367C_PORT7_STATUS_LINK_STATE_OFFSET 4 +#define RTL8367C_PORT7_STATUS_LINK_STATE_MASK 0x10 +#define RTL8367C_PORT7_STATUS_FULL_DUPLUX_CAP_OFFSET 2 +#define RTL8367C_PORT7_STATUS_FULL_DUPLUX_CAP_MASK 0x4 +#define RTL8367C_PORT7_STATUS_LINK_SPEED_OFFSET 0 +#define RTL8367C_PORT7_STATUS_LINK_SPEED_MASK 0x3 + +#define RTL8367C_REG_PORT8_STATUS 0x135a +#define RTL8367C_PORT8_STATUS_EN_1000_LPI_OFFSET 11 +#define RTL8367C_PORT8_STATUS_EN_1000_LPI_MASK 0x800 +#define RTL8367C_PORT8_STATUS_EN_100_LPI_OFFSET 10 +#define RTL8367C_PORT8_STATUS_EN_100_LPI_MASK 0x400 +#define RTL8367C_PORT8_STATUS_NWAY_FAULT_OFFSET 9 +#define RTL8367C_PORT8_STATUS_NWAY_FAULT_MASK 0x200 +#define RTL8367C_PORT8_STATUS_LINK_ON_MASTER_OFFSET 8 +#define RTL8367C_PORT8_STATUS_LINK_ON_MASTER_MASK 0x100 +#define RTL8367C_PORT8_STATUS_NWAY_CAP_OFFSET 7 +#define RTL8367C_PORT8_STATUS_NWAY_CAP_MASK 0x80 +#define RTL8367C_PORT8_STATUS_TX_FLOWCTRL_CAP_OFFSET 6 +#define RTL8367C_PORT8_STATUS_TX_FLOWCTRL_CAP_MASK 0x40 +#define RTL8367C_PORT8_STATUS_RX_FLOWCTRL_CAP_OFFSET 5 +#define RTL8367C_PORT8_STATUS_RX_FLOWCTRL_CAP_MASK 0x20 +#define RTL8367C_PORT8_STATUS_LINK_STATE_OFFSET 4 +#define RTL8367C_PORT8_STATUS_LINK_STATE_MASK 0x10 +#define RTL8367C_PORT8_STATUS_FULL_DUPLUX_CAP_OFFSET 2 +#define RTL8367C_PORT8_STATUS_FULL_DUPLUX_CAP_MASK 0x4 +#define RTL8367C_PORT8_STATUS_LINK_SPEED_OFFSET 0 +#define RTL8367C_PORT8_STATUS_LINK_SPEED_MASK 0x3 + +#define RTL8367C_REG_PORT9_STATUS 0x135b +#define RTL8367C_PORT9_STATUS_EN_1000_LPI_OFFSET 11 +#define RTL8367C_PORT9_STATUS_EN_1000_LPI_MASK 0x800 +#define RTL8367C_PORT9_STATUS_EN_100_LPI_OFFSET 10 +#define RTL8367C_PORT9_STATUS_EN_100_LPI_MASK 0x400 +#define RTL8367C_PORT9_STATUS_NWAY_FAULT_OFFSET 9 +#define RTL8367C_PORT9_STATUS_NWAY_FAULT_MASK 0x200 +#define RTL8367C_PORT9_STATUS_LINK_ON_MASTER_OFFSET 8 +#define RTL8367C_PORT9_STATUS_LINK_ON_MASTER_MASK 0x100 +#define RTL8367C_PORT9_STATUS_NWAY_CAP_OFFSET 7 +#define RTL8367C_PORT9_STATUS_NWAY_CAP_MASK 0x80 +#define RTL8367C_PORT9_STATUS_TX_FLOWCTRL_CAP_OFFSET 6 +#define RTL8367C_PORT9_STATUS_TX_FLOWCTRL_CAP_MASK 0x40 +#define RTL8367C_PORT9_STATUS_RX_FLOWCTRL_CAP_OFFSET 5 +#define RTL8367C_PORT9_STATUS_RX_FLOWCTRL_CAP_MASK 0x20 +#define RTL8367C_PORT9_STATUS_LINK_STATE_OFFSET 4 +#define RTL8367C_PORT9_STATUS_LINK_STATE_MASK 0x10 +#define RTL8367C_PORT9_STATUS_FULL_DUPLUX_CAP_OFFSET 2 +#define RTL8367C_PORT9_STATUS_FULL_DUPLUX_CAP_MASK 0x4 +#define RTL8367C_PORT9_STATUS_LINK_SPEED_OFFSET 0 +#define RTL8367C_PORT9_STATUS_LINK_SPEED_MASK 0x3 + +#define RTL8367C_REG_PORT10_STATUS 0x135c +#define RTL8367C_PORT10_STATUS_EN_1000_LPI_OFFSET 11 +#define RTL8367C_PORT10_STATUS_EN_1000_LPI_MASK 0x800 +#define RTL8367C_PORT10_STATUS_EN_100_LPI_OFFSET 10 +#define RTL8367C_PORT10_STATUS_EN_100_LPI_MASK 0x400 +#define RTL8367C_PORT10_STATUS_NWAY_FAULT_OFFSET 9 +#define RTL8367C_PORT10_STATUS_NWAY_FAULT_MASK 0x200 +#define RTL8367C_PORT10_STATUS_LINK_ON_MASTER_OFFSET 8 +#define RTL8367C_PORT10_STATUS_LINK_ON_MASTER_MASK 0x100 +#define RTL8367C_PORT10_STATUS_NWAY_CAP_OFFSET 7 +#define RTL8367C_PORT10_STATUS_NWAY_CAP_MASK 0x80 +#define RTL8367C_PORT10_STATUS_TX_FLOWCTRL_CAP_OFFSET 6 +#define RTL8367C_PORT10_STATUS_TX_FLOWCTRL_CAP_MASK 0x40 +#define RTL8367C_PORT10_STATUS_RX_FLOWCTRL_CAP_OFFSET 5 +#define RTL8367C_PORT10_STATUS_RX_FLOWCTRL_CAP_MASK 0x20 +#define RTL8367C_PORT10_STATUS_LINK_STATE_OFFSET 4 +#define RTL8367C_PORT10_STATUS_LINK_STATE_MASK 0x10 +#define RTL8367C_PORT10_STATUS_FULL_DUPLUX_CAP_OFFSET 2 +#define RTL8367C_PORT10_STATUS_FULL_DUPLUX_CAP_MASK 0x4 +#define RTL8367C_PORT10_STATUS_LINK_SPEED_OFFSET 0 +#define RTL8367C_PORT10_STATUS_LINK_SPEED_MASK 0x3 + +#define RTL8367C_REG_UPS_CTRL0 0x1362 +#define RTL8367C_P3_REF_SD_BIT0_OFFSET 8 +#define RTL8367C_P3_REF_SD_BIT0_MASK 0xFF00 +#define RTL8367C_P2_REF_SD_OFFSET 0 +#define RTL8367C_P2_REF_SD_MASK 0xFF + +#define RTL8367C_REG_UPS_CTRL1 0x1363 +#define RTL8367C_UPS_OUT_OFFSET 8 +#define RTL8367C_UPS_OUT_MASK 0xFF00 +#define RTL8367C_UPS_WRITE_PULSE_OFFSET 1 +#define RTL8367C_UPS_WRITE_PULSE_MASK 0x2 +#define RTL8367C_UPS_EN_OFFSET 0 +#define RTL8367C_UPS_EN_MASK 0x1 + +#define RTL8367C_REG_UPS_CTRL2 0x1364 +#define RTL8367C_IGNOE_MAC8_LINK_OFFSET 15 +#define RTL8367C_IGNOE_MAC8_LINK_MASK 0x8000 +#define RTL8367C_AGREE_SLEEP_OFFSET 14 +#define RTL8367C_AGREE_SLEEP_MASK 0x4000 +#define RTL8367C_WAIT_FOR_AGREEMENT_OFFSET 13 +#define RTL8367C_WAIT_FOR_AGREEMENT_MASK 0x2000 +#define RTL8367C_WAKE_UP_BY_LINK_OFFSET 12 +#define RTL8367C_WAKE_UP_BY_LINK_MASK 0x1000 +#define RTL8367C_WAKE_UP_BY_PHY_OFFSET 11 +#define RTL8367C_WAKE_UP_BY_PHY_MASK 0x800 +#define RTL8367C_SLOW_CLK_TGL_RATE_OFFSET 7 +#define RTL8367C_SLOW_CLK_TGL_RATE_MASK 0x780 +#define RTL8367C_PLL_G1_CTRL_EN_OFFSET 6 +#define RTL8367C_PLL_G1_CTRL_EN_MASK 0x40 +#define RTL8367C_PLL_G0_CTRL_EN_OFFSET 5 +#define RTL8367C_PLL_G0_CTRL_EN_MASK 0x20 +#define RTL8367C_SLOW_DOWN_PLL_EN_OFFSET 4 +#define RTL8367C_SLOW_DOWN_PLL_EN_MASK 0x10 +#define RTL8367C_SLOW_DOWN_CLK_EN_OFFSET 3 +#define RTL8367C_SLOW_DOWN_CLK_EN_MASK 0x8 +#define RTL8367C_GATING_CLK_SDS_EN_OFFSET 2 +#define RTL8367C_GATING_CLK_SDS_EN_MASK 0x4 +#define RTL8367C_GATING_CLK_CHIP_EN_OFFSET 1 +#define RTL8367C_GATING_CLK_CHIP_EN_MASK 0x2 +#define RTL8367C_GATING_SW_EN_OFFSET 0 +#define RTL8367C_GATING_SW_EN_MASK 0x1 + +#define RTL8367C_REG_GATING_CLK_1 0x1365 +#define RTL8367C_ALDPS_MODE_4_OFFSET 15 +#define RTL8367C_ALDPS_MODE_4_MASK 0x8000 +#define RTL8367C_ALDPS_MODE_3_OFFSET 14 +#define RTL8367C_ALDPS_MODE_3_MASK 0x4000 +#define RTL8367C_ALDPS_MODE_2_OFFSET 13 +#define RTL8367C_ALDPS_MODE_2_MASK 0x2000 +#define RTL8367C_ALDPS_MODE_1_OFFSET 12 +#define RTL8367C_ALDPS_MODE_1_MASK 0x1000 +#define RTL8367C_ALDPS_MODE_0_OFFSET 11 +#define RTL8367C_ALDPS_MODE_0_MASK 0x800 +#define RTL8367C_UPS_DBGO_OFFSET 10 +#define RTL8367C_UPS_DBGO_MASK 0x400 +#define RTL8367C_IFMX_AFF_NOT_FF_OUT_OFFSET 9 +#define RTL8367C_IFMX_AFF_NOT_FF_OUT_MASK 0x200 +#define RTL8367C_WATER_LEVEL_FD_OFFSET 6 +#define RTL8367C_WATER_LEVEL_FD_MASK 0x1C0 +#define RTL8367C_WATER_LEVEL_Y2X_OFFSET 3 +#define RTL8367C_WATER_LEVEL_Y2X_MASK 0x38 +#define RTL8367C_WATER_LEVEL_X2Y_2_OFFSET 2 +#define RTL8367C_WATER_LEVEL_X2Y_2_MASK 0x4 +#define RTL8367C_IGNOE_MAC10_LINK_OFFSET 1 +#define RTL8367C_IGNOE_MAC10_LINK_MASK 0x2 +#define RTL8367C_IGNOE_MAC9_LINK_OFFSET 0 +#define RTL8367C_IGNOE_MAC9_LINK_MASK 0x1 + +#define RTL8367C_REG_UPS_CTRL4 0x1366 +#define RTL8367C_PROB_EN_OFFSET 6 +#define RTL8367C_PROB_EN_MASK 0x40 +#define RTL8367C_PLL_DOWN_OFFSET 1 +#define RTL8367C_PLL_DOWN_MASK 0x2 +#define RTL8367C_XTAL_DOWN_OFFSET 0 +#define RTL8367C_XTAL_DOWN_MASK 0x1 + +#define RTL8367C_REG_UPS_CTRL5 0x1367 +#define RTL8367C_FRC_CPU_ACPT_OFFSET 3 +#define RTL8367C_FRC_CPU_ACPT_MASK 0x8 +#define RTL8367C_UPS_CPU_ACPT_OFFSET 2 +#define RTL8367C_UPS_CPU_ACPT_MASK 0x4 +#define RTL8367C_UPS_DBG_4_OFFSET 0 +#define RTL8367C_UPS_DBG_4_MASK 0x3 + +#define RTL8367C_REG_UPS_CTRL6 0x1368 +#define RTL8367C_UPS_CTRL6_OFFSET 0 +#define RTL8367C_UPS_CTRL6_MASK 0xF + +#define RTL8367C_REG_EFUSE_CMD_70B 0x1369 + +#define RTL8367C_REG_EFUSE_CMD 0x1370 +#define RTL8367C_EFUSE_TIME_OUT_FLAG_OFFSET 3 +#define RTL8367C_EFUSE_TIME_OUT_FLAG_MASK 0x8 +#define RTL8367C_EFUSE_ACCESS_BUSY_OFFSET 2 +#define RTL8367C_EFUSE_ACCESS_BUSY_MASK 0x4 +#define RTL8367C_EFUSE_COMMAND_EN_OFFSET 1 +#define RTL8367C_EFUSE_COMMAND_EN_MASK 0x2 +#define RTL8367C_EFUSE_WR_OFFSET 0 +#define RTL8367C_EFUSE_WR_MASK 0x1 + +#define RTL8367C_REG_EFUSE_ADR 0x1371 +#define RTL8367C_DUMMY_15_10_OFFSET 8 +#define RTL8367C_DUMMY_15_10_MASK 0xFF00 +#define RTL8367C_EFUSE_ADDRESS_OFFSET 0 +#define RTL8367C_EFUSE_ADDRESS_MASK 0xFF + +#define RTL8367C_REG_EFUSE_WDAT 0x1372 + +#define RTL8367C_REG_EFUSE_RDAT 0x1373 + +#define RTL8367C_REG_I2C_CTRL 0x1374 +#define RTL8367C_MDX_MST_FAIL_LAT_OFFSET 1 +#define RTL8367C_MDX_MST_FAIL_LAT_MASK 0x2 +#define RTL8367C_MDX_MST_FAIL_CLRPS_OFFSET 0 +#define RTL8367C_MDX_MST_FAIL_CLRPS_MASK 0x1 + +#define RTL8367C_REG_EEE_CFG 0x1375 +#define RTL8367C_CFG_BYPASS_GATELPTD_OFFSET 11 +#define RTL8367C_CFG_BYPASS_GATELPTD_MASK 0x800 +#define RTL8367C_EEE_ABT_ADDR2_OFFSET 6 +#define RTL8367C_EEE_ABT_ADDR2_MASK 0x7C0 +#define RTL8367C_EEE_ABT_ADDR1_OFFSET 1 +#define RTL8367C_EEE_ABT_ADDR1_MASK 0x3E +#define RTL8367C_EEE_POLL_EN_OFFSET 0 +#define RTL8367C_EEE_POLL_EN_MASK 0x1 + +#define RTL8367C_REG_EEE_PAGE 0x1376 + +#define RTL8367C_REG_EEE_EXT_PAGE 0x1377 + +#define RTL8367C_REG_EEE_EN_SPD1000 0x1378 + +#define RTL8367C_REG_EEE_EN_SPD100 0x1379 + +#define RTL8367C_REG_EEE_LP_SPD1000 0x137a + +#define RTL8367C_REG_EEE_LP_SPD100 0x137b + +#define RTL8367C_REG_DW8051_PRO_REG0 0x13a0 + +#define RTL8367C_REG_DW8051_PRO_REG1 0x13a1 + +#define RTL8367C_REG_DW8051_PRO_REG2 0x13a2 + +#define RTL8367C_REG_DW8051_PRO_REG3 0x13a3 + +#define RTL8367C_REG_DW8051_PRO_REG4 0x13a4 + +#define RTL8367C_REG_DW8051_PRO_REG5 0x13a5 + +#define RTL8367C_REG_DW8051_PRO_REG6 0x13a6 + +#define RTL8367C_REG_DW8051_PRO_REG7 0x13a7 + +#define RTL8367C_REG_PROTECT_ID 0x13c0 + +#define RTL8367C_REG_CHIP_VER_INTL 0x13c1 +#define RTL8367C_CHIP_VER_INTL_OFFSET 0 +#define RTL8367C_CHIP_VER_INTL_MASK 0xF + +#define RTL8367C_REG_MAGIC_ID 0x13c2 + +#define RTL8367C_REG_DIGITAL_INTERFACE_SELECT_1 0x13c3 +#define RTL8367C_SKIP_MII_2_RXER_OFFSET 4 +#define RTL8367C_SKIP_MII_2_RXER_MASK 0x10 +#define RTL8367C_SELECT_GMII_2_OFFSET 0 +#define RTL8367C_SELECT_GMII_2_MASK 0xF + +#define RTL8367C_REG_DIGITAL_INTERFACE2_FORCE 0x13c4 +#define RTL8367C_GMII_2_FORCE_OFFSET 12 +#define RTL8367C_GMII_2_FORCE_MASK 0x1000 +#define RTL8367C_RGMII_2_FORCE_OFFSET 0 +#define RTL8367C_RGMII_2_FORCE_MASK 0xFFF + +#define RTL8367C_REG_EXT2_RGMXF 0x13c5 +#define RTL8367C_EXT2_RGTX_INV_OFFSET 6 +#define RTL8367C_EXT2_RGTX_INV_MASK 0x40 +#define RTL8367C_EXT2_RGRX_INV_OFFSET 5 +#define RTL8367C_EXT2_RGRX_INV_MASK 0x20 +#define RTL8367C_EXT2_RGMXF_OFFSET 0 +#define RTL8367C_EXT2_RGMXF_MASK 0x1F + +#define RTL8367C_REG_ROUTER_UPS_CFG 0x13c6 +#define RTL8367C_UPS_Status_OFFSET 1 +#define RTL8367C_UPS_Status_MASK 0x2 +#define RTL8367C_SoftStart_OFFSET 0 +#define RTL8367C_SoftStart_MASK 0x1 + +#define RTL8367C_REG_CTRL_GPIO 0x13c7 +#define RTL8367C_CTRL_GPIO_13_OFFSET 13 +#define RTL8367C_CTRL_GPIO_13_MASK 0x2000 +#define RTL8367C_CTRL_GPIO_12_OFFSET 12 +#define RTL8367C_CTRL_GPIO_12_MASK 0x1000 +#define RTL8367C_CTRL_GPIO_11_OFFSET 11 +#define RTL8367C_CTRL_GPIO_11_MASK 0x800 +#define RTL8367C_CTRL_GPIO_10_OFFSET 10 +#define RTL8367C_CTRL_GPIO_10_MASK 0x400 +#define RTL8367C_CTRL_GPIO_9_OFFSET 9 +#define RTL8367C_CTRL_GPIO_9_MASK 0x200 +#define RTL8367C_CTRL_GPIO_8_OFFSET 8 +#define RTL8367C_CTRL_GPIO_8_MASK 0x100 +#define RTL8367C_CTRL_GPIO_7_OFFSET 7 +#define RTL8367C_CTRL_GPIO_7_MASK 0x80 +#define RTL8367C_CTRL_GPIO_6_OFFSET 6 +#define RTL8367C_CTRL_GPIO_6_MASK 0x40 +#define RTL8367C_CTRL_GPIO_5_OFFSET 5 +#define RTL8367C_CTRL_GPIO_5_MASK 0x20 +#define RTL8367C_CTRL_GPIO_4_OFFSET 4 +#define RTL8367C_CTRL_GPIO_4_MASK 0x10 +#define RTL8367C_CTRL_GPIO_3_OFFSET 3 +#define RTL8367C_CTRL_GPIO_3_MASK 0x8 +#define RTL8367C_CTRL_GPIO_2_OFFSET 2 +#define RTL8367C_CTRL_GPIO_2_MASK 0x4 +#define RTL8367C_CTRL_GPIO_1_OFFSET 1 +#define RTL8367C_CTRL_GPIO_1_MASK 0x2 +#define RTL8367C_CTRL_GPIO_0_OFFSET 0 +#define RTL8367C_CTRL_GPIO_0_MASK 0x1 + +#define RTL8367C_REG_SEL_GPIO 0x13c8 +#define RTL8367C_SEL_GPIO_13_OFFSET 13 +#define RTL8367C_SEL_GPIO_13_MASK 0x2000 +#define RTL8367C_SEL_GPIO_12_OFFSET 12 +#define RTL8367C_SEL_GPIO_12_MASK 0x1000 +#define RTL8367C_SEL_GPIO_11_OFFSET 11 +#define RTL8367C_SEL_GPIO_11_MASK 0x800 +#define RTL8367C_SEL_GPIO_10_OFFSET 10 +#define RTL8367C_SEL_GPIO_10_MASK 0x400 +#define RTL8367C_SEL_GPIO_9_OFFSET 9 +#define RTL8367C_SEL_GPIO_9_MASK 0x200 +#define RTL8367C_SEL_GPIO_8_OFFSET 8 +#define RTL8367C_SEL_GPIO_8_MASK 0x100 +#define RTL8367C_SEL_GPIO_7_OFFSET 7 +#define RTL8367C_SEL_GPIO_7_MASK 0x80 +#define RTL8367C_SEL_GPIO_6_OFFSET 6 +#define RTL8367C_SEL_GPIO_6_MASK 0x40 +#define RTL8367C_SEL_GPIO_5_OFFSET 5 +#define RTL8367C_SEL_GPIO_5_MASK 0x20 +#define RTL8367C_SEL_GPIO_4_OFFSET 4 +#define RTL8367C_SEL_GPIO_4_MASK 0x10 +#define RTL8367C_SEL_GPIO_3_OFFSET 3 +#define RTL8367C_SEL_GPIO_3_MASK 0x8 +#define RTL8367C_SEL_GPIO_2_OFFSET 2 +#define RTL8367C_SEL_GPIO_2_MASK 0x4 +#define RTL8367C_SEL_GPIO_1_OFFSET 1 +#define RTL8367C_SEL_GPIO_1_MASK 0x2 +#define RTL8367C_SEL_GPIO_0_OFFSET 0 +#define RTL8367C_SEL_GPIO_0_MASK 0x1 + +#define RTL8367C_REG_STATUS_GPIO 0x13c9 +#define RTL8367C_STATUS_GPIO_OFFSET 0 +#define RTL8367C_STATUS_GPIO_MASK 0x3FFF + +#define RTL8367C_REG_SYNC_ETH_CFG 0x13e0 +#define RTL8367C_DUMMY2_OFFSET 9 +#define RTL8367C_DUMMY2_MASK 0xFE00 +#define RTL8367C_RFC2819_TYPE_OFFSET 8 +#define RTL8367C_RFC2819_TYPE_MASK 0x100 +#define RTL8367C_DUMMY1_OFFSET 7 +#define RTL8367C_DUMMY1_MASK 0x80 +#define RTL8367C_FIBER_SYNCE125_L_SEL_OFFSET 6 +#define RTL8367C_FIBER_SYNCE125_L_SEL_MASK 0x40 +#define RTL8367C_SYNC_ETH_EN_RTT2_OFFSET 5 +#define RTL8367C_SYNC_ETH_EN_RTT2_MASK 0x20 +#define RTL8367C_SYNC_ETH_EN_RTT1_OFFSET 4 +#define RTL8367C_SYNC_ETH_EN_RTT1_MASK 0x10 +#define RTL8367C_SYNC_ETH_SEL_DPLL_OFFSET 3 +#define RTL8367C_SYNC_ETH_SEL_DPLL_MASK 0x8 +#define RTL8367C_SYNC_ETH_SEL_PHYREF_OFFSET 2 +#define RTL8367C_SYNC_ETH_SEL_PHYREF_MASK 0x4 +#define RTL8367C_SYNC_ETH_SEL_XTAL_OFFSET 1 +#define RTL8367C_SYNC_ETH_SEL_XTAL_MASK 0x2 +#define RTL8367C_DUMMY0_OFFSET 0 +#define RTL8367C_DUMMY0_MASK 0x1 + +#define RTL8367C_REG_LED_DRI_CFG 0x13e1 +#define RTL8367C_LED_DRI_CFG_DUMMY_OFFSET 1 +#define RTL8367C_LED_DRI_CFG_DUMMY_MASK 0xFFFE +#define RTL8367C_LED_DRIVING_OFFSET 0 +#define RTL8367C_LED_DRIVING_MASK 0x1 + +#define RTL8367C_REG_CHIP_DEBUG2 0x13e2 +#define RTL8367C_RG2_DN_OFFSET 6 +#define RTL8367C_RG2_DN_MASK 0x1C0 +#define RTL8367C_RG2_DP_OFFSET 3 +#define RTL8367C_RG2_DP_MASK 0x38 +#define RTL8367C_DRI_EXT2_RG_OFFSET 2 +#define RTL8367C_DRI_EXT2_RG_MASK 0x4 +#define RTL8367C_DRI_EXT2_OFFSET 1 +#define RTL8367C_DRI_EXT2_MASK 0x2 +#define RTL8367C_SLR_EXT2_OFFSET 0 +#define RTL8367C_SLR_EXT2_MASK 0x1 + +#define RTL8367C_REG_DIGITAL_DEBUG_2 0x13e3 + +#define RTL8367C_REG_FIBER_RTL_OUI_CFG0 0x13e4 +#define RTL8367C_FIBER_RTL_OUI_CFG0_OFFSET 0 +#define RTL8367C_FIBER_RTL_OUI_CFG0_MASK 0xFF + +#define RTL8367C_REG_FIBER_RTL_OUI_CFG1 0x13e5 + +#define RTL8367C_REG_FIBER_CFG_0 0x13e6 +#define RTL8367C_REV_NUM_OFFSET 8 +#define RTL8367C_REV_NUM_MASK 0xF00 +#define RTL8367C_MODEL_NUM_OFFSET 0 +#define RTL8367C_MODEL_NUM_MASK 0x3F + +#define RTL8367C_REG_FIBER_CFG_1 0x13e7 +#define RTL8367C_SDS_FRC_REG4_OFFSET 12 +#define RTL8367C_SDS_FRC_REG4_MASK 0x1000 +#define RTL8367C_SDS_FRC_REG4_FIB100_OFFSET 11 +#define RTL8367C_SDS_FRC_REG4_FIB100_MASK 0x800 +#define RTL8367C_SEL_MASK_ONL_OFFSET 5 +#define RTL8367C_SEL_MASK_ONL_MASK 0x20 +#define RTL8367C_DIS_QUALITY_IN_MASK_OFFSET 4 +#define RTL8367C_DIS_QUALITY_IN_MASK_MASK 0x10 +#define RTL8367C_SDS_FRC_MODE_OFFSET 3 +#define RTL8367C_SDS_FRC_MODE_MASK 0x8 +#define RTL8367C_SDS_MODE_OFFSET 0 +#define RTL8367C_SDS_MODE_MASK 0x7 + +#define RTL8367C_REG_FIBER_CFG_2 0x13e8 +#define RTL8367C_SEL_SDET_PS_OFFSET 12 +#define RTL8367C_SEL_SDET_PS_MASK 0xF000 +#define RTL8367C_UTP_DIS_RX_OFFSET 10 +#define RTL8367C_UTP_DIS_RX_MASK 0xC00 +#define RTL8367C_UTP_FRC_LD_OFFSET 8 +#define RTL8367C_UTP_FRC_LD_MASK 0x300 +#define RTL8367C_SDS_RX_DISABLE_OFFSET 6 +#define RTL8367C_SDS_RX_DISABLE_MASK 0xC0 +#define RTL8367C_SDS_TX_DISABLE_OFFSET 4 +#define RTL8367C_SDS_TX_DISABLE_MASK 0x30 +#define RTL8367C_FIBER_CFG_2_SDS_PWR_ISO_OFFSET 2 +#define RTL8367C_FIBER_CFG_2_SDS_PWR_ISO_MASK 0xC +#define RTL8367C_SDS_FRC_LD_OFFSET 0 +#define RTL8367C_SDS_FRC_LD_MASK 0x3 + +#define RTL8367C_REG_FIBER_CFG_3 0x13e9 +#define RTL8367C_FIBER_CFG_3_OFFSET 0 +#define RTL8367C_FIBER_CFG_3_MASK 0xFFF + +#define RTL8367C_REG_FIBER_CFG_4 0x13ea + +#define RTL8367C_REG_UTP_FIB_DET 0x13eb +#define RTL8367C_FORCE_SEL_FIBER_OFFSET 14 +#define RTL8367C_FORCE_SEL_FIBER_MASK 0xC000 +#define RTL8367C_FIB_FINAL_TIMER_OFFSET 12 +#define RTL8367C_FIB_FINAL_TIMER_MASK 0x3000 +#define RTL8367C_FIB_LINK_TIMER_OFFSET 10 +#define RTL8367C_FIB_LINK_TIMER_MASK 0xC00 +#define RTL8367C_FIB_SDET_TIMER_OFFSET 8 +#define RTL8367C_FIB_SDET_TIMER_MASK 0x300 +#define RTL8367C_UTP_LINK_TIMER_OFFSET 6 +#define RTL8367C_UTP_LINK_TIMER_MASK 0xC0 +#define RTL8367C_UTP_SDET_TIMER_OFFSET 4 +#define RTL8367C_UTP_SDET_TIMER_MASK 0x30 +#define RTL8367C_FORCE_AUTODET_OFFSET 3 +#define RTL8367C_FORCE_AUTODET_MASK 0x8 +#define RTL8367C_AUTODET_FSM_CLR_OFFSET 2 +#define RTL8367C_AUTODET_FSM_CLR_MASK 0x4 +#define RTL8367C_UTP_FIRST_OFFSET 1 +#define RTL8367C_UTP_FIRST_MASK 0x2 +#define RTL8367C_UTP_FIB_DISAUTODET_OFFSET 0 +#define RTL8367C_UTP_FIB_DISAUTODET_MASK 0x1 + +#define RTL8367C_REG_NRESTORE_MAGIC_NUM 0x13ec +#define RTL8367C_NRESTORE_MAGIC_NUM_MASK 0xFFFF +#define RTL8367C_EEPROM_PROGRAM_CYCLE_OFFSET 0 +#define RTL8367C_EEPROM_PROGRAM_CYCLE_MASK 0x3 + +#define RTL8367C_REG_MAC_ACTIVE 0x13ee +#define RTL8367C_MAC_ACTIVE_H_OFFSET 9 +#define RTL8367C_MAC_ACTIVE_H_MASK 0xE00 +#define RTL8367C_FORCE_MAC_ACTIVE_OFFSET 8 +#define RTL8367C_FORCE_MAC_ACTIVE_MASK 0x100 +#define RTL8367C_MAC_ACTIVE_OFFSET 0 +#define RTL8367C_MAC_ACTIVE_MASK 0xFF + +#define RTL8367C_REG_SERDES_RESULT 0x13ef +#define RTL8367C_FIB100_DET_1_OFFSET 12 +#define RTL8367C_FIB100_DET_1_MASK 0x1000 +#define RTL8367C_FIB_ISO_1_OFFSET 11 +#define RTL8367C_FIB_ISO_1_MASK 0x800 +#define RTL8367C_SDS_ANFAULT_1_OFFSET 10 +#define RTL8367C_SDS_ANFAULT_1_MASK 0x400 +#define RTL8367C_SDS_INTB_1_OFFSET 9 +#define RTL8367C_SDS_INTB_1_MASK 0x200 +#define RTL8367C_SDS_LINK_OK_1_OFFSET 8 +#define RTL8367C_SDS_LINK_OK_1_MASK 0x100 +#define RTL8367C_FIB100_DET_OFFSET 4 +#define RTL8367C_FIB100_DET_MASK 0x10 +#define RTL8367C_FIB_ISO_OFFSET 3 +#define RTL8367C_FIB_ISO_MASK 0x8 +#define RTL8367C_SDS_ANFAULT_OFFSET 2 +#define RTL8367C_SDS_ANFAULT_MASK 0x4 +#define RTL8367C_SDS_INTB_OFFSET 1 +#define RTL8367C_SDS_INTB_MASK 0x2 +#define RTL8367C_SDS_LINK_OK_OFFSET 0 +#define RTL8367C_SDS_LINK_OK_MASK 0x1 + +#define RTL8367C_REG_CHIP_ECO 0x13f0 +#define RTL8367C_CFG_CHIP_ECO_OFFSET 1 +#define RTL8367C_CFG_CHIP_ECO_MASK 0xFFFE +#define RTL8367C_CFG_CKOUTEN_OFFSET 0 +#define RTL8367C_CFG_CKOUTEN_MASK 0x1 + +#define RTL8367C_REG_WAKELPI_SLOT_PRD 0x13f1 +#define RTL8367C_WAKELPI_SLOT_PRD_OFFSET 0 +#define RTL8367C_WAKELPI_SLOT_PRD_MASK 0x1F + +#define RTL8367C_REG_WAKELPI_SLOT_PG0 0x13f2 +#define RTL8367C_WAKELPI_SLOT_P1_OFFSET 8 +#define RTL8367C_WAKELPI_SLOT_P1_MASK 0x1F00 +#define RTL8367C_WAKELPI_SLOT_P0_OFFSET 0 +#define RTL8367C_WAKELPI_SLOT_P0_MASK 0x1F + +#define RTL8367C_REG_WAKELPI_SLOT_PG1 0x13f3 +#define RTL8367C_WAKELPI_SLOT_P3_OFFSET 8 +#define RTL8367C_WAKELPI_SLOT_P3_MASK 0x1F00 +#define RTL8367C_WAKELPI_SLOT_P2_OFFSET 0 +#define RTL8367C_WAKELPI_SLOT_P2_MASK 0x1F + +#define RTL8367C_REG_WAKELPI_SLOT_PG2 0x13f4 +#define RTL8367C_WAKELPI_SLOT_P5_OFFSET 8 +#define RTL8367C_WAKELPI_SLOT_P5_MASK 0x1F00 +#define RTL8367C_WAKELPI_SLOT_P4_OFFSET 0 +#define RTL8367C_WAKELPI_SLOT_P4_MASK 0x1F + +#define RTL8367C_REG_WAKELPI_SLOT_PG3 0x13f5 +#define RTL8367C_WAKELPI_SLOT_P7_OFFSET 8 +#define RTL8367C_WAKELPI_SLOT_P7_MASK 0x1F00 +#define RTL8367C_WAKELPI_SLOT_P6_OFFSET 0 +#define RTL8367C_WAKELPI_SLOT_P6_MASK 0x1F + +#define RTL8367C_REG_SYNC_FIFO_0 0x13f6 +#define RTL8367C_SYNC_FIFO_TX_OFFSET 8 +#define RTL8367C_SYNC_FIFO_TX_MASK 0x700 +#define RTL8367C_SYNC_FIFO_RX_OFFSET 0 +#define RTL8367C_SYNC_FIFO_RX_MASK 0xFF + +#define RTL8367C_REG_SYNC_FIFO_1 0x13f7 +#define RTL8367C_SYNC_FIFO_RX_ERR_P10_8_OFFSET 11 +#define RTL8367C_SYNC_FIFO_RX_ERR_P10_8_MASK 0x3800 +#define RTL8367C_SYNC_FIFO_TX_ERR_OFFSET 8 +#define RTL8367C_SYNC_FIFO_TX_ERR_MASK 0x700 +#define RTL8367C_SYNC_FIFO_RX_ERR_OFFSET 0 +#define RTL8367C_SYNC_FIFO_RX_ERR_MASK 0xFF + +#define RTL8367C_REG_RGM_EEE 0x13f8 +#define RTL8367C_EXT2_PAD_STOP_EN_OFFSET 14 +#define RTL8367C_EXT2_PAD_STOP_EN_MASK 0x4000 +#define RTL8367C_EXT1_PAD_STOP_EN_OFFSET 13 +#define RTL8367C_EXT1_PAD_STOP_EN_MASK 0x2000 +#define RTL8367C_EXT0_PAD_STOP_EN_OFFSET 12 +#define RTL8367C_EXT0_PAD_STOP_EN_MASK 0x1000 +#define RTL8367C_EXT2_CYCLE_PAD_OFFSET 8 +#define RTL8367C_EXT2_CYCLE_PAD_MASK 0xF00 +#define RTL8367C_EXT1_CYCLE_PAD_OFFSET 4 +#define RTL8367C_EXT1_CYCLE_PAD_MASK 0xF0 +#define RTL8367C_EXT0_CYCLE_PAD_OFFSET 0 +#define RTL8367C_EXT0_CYCLE_PAD_MASK 0xF + +#define RTL8367C_REG_EXT_TXC_DLY 0x13f9 +#define RTL8367C_EXT1_GMII_TX_DELAY_OFFSET 12 +#define RTL8367C_EXT1_GMII_TX_DELAY_MASK 0x7000 +#define RTL8367C_EXT0_GMII_TX_DELAY_OFFSET 9 +#define RTL8367C_EXT0_GMII_TX_DELAY_MASK 0xE00 +#define RTL8367C_EXT2_RGMII_TX_DELAY_OFFSET 6 +#define RTL8367C_EXT2_RGMII_TX_DELAY_MASK 0x1C0 +#define RTL8367C_EXT1_RGMII_TX_DELAY_OFFSET 3 +#define RTL8367C_EXT1_RGMII_TX_DELAY_MASK 0x38 +#define RTL8367C_EXT0_RGMII_TX_DELAY_OFFSET 0 +#define RTL8367C_EXT0_RGMII_TX_DELAY_MASK 0x7 + +#define RTL8367C_REG_IO_MISC_CTRL 0x13fa +#define RTL8367C_IO_BUZZER_EN_OFFSET 3 +#define RTL8367C_IO_BUZZER_EN_MASK 0x8 +#define RTL8367C_IO_INTRPT_EN_OFFSET 2 +#define RTL8367C_IO_INTRPT_EN_MASK 0x4 +#define RTL8367C_IO_NRESTORE_EN_OFFSET 1 +#define RTL8367C_IO_NRESTORE_EN_MASK 0x2 +#define RTL8367C_IO_UART_EN_OFFSET 0 +#define RTL8367C_IO_UART_EN_MASK 0x1 + +#define RTL8367C_REG_CHIP_DUMMY_NO 0x13fb +#define RTL8367C_CHIP_DUMMY_NO_OFFSET 0 +#define RTL8367C_CHIP_DUMMY_NO_MASK 0xF + +#define RTL8367C_REG_RC_CALIB_CFG 0x13fc +#define RTL8367C_TRIG_BURN_EFUSE_OFFSET 9 +#define RTL8367C_TRIG_BURN_EFUSE_MASK 0x200 +#define RTL8367C_AMP_CALIB_FAIL_OFFSET 8 +#define RTL8367C_AMP_CALIB_FAIL_MASK 0x100 +#define RTL8367C_R_CALIB_FAIL_OFFSET 7 +#define RTL8367C_R_CALIB_FAIL_MASK 0x80 +#define RTL8367C_CFG_CALIB_MODE_OFFSET 6 +#define RTL8367C_CFG_CALIB_MODE_MASK 0x40 +#define RTL8367C_CENTER_PORT_SEL_OFFSET 3 +#define RTL8367C_CENTER_PORT_SEL_MASK 0x38 +#define RTL8367C_CALIB_FINISH_OFFSET 2 +#define RTL8367C_CALIB_FINISH_MASK 0x4 +#define RTL8367C_CFG_CALIB_OPTION_OFFSET 1 +#define RTL8367C_CFG_CALIB_OPTION_MASK 0x2 +#define RTL8367C_CFG_CALIB_EN_OFFSET 0 +#define RTL8367C_CFG_CALIB_EN_MASK 0x1 + +#define RTL8367C_REG_WAKELPI_SLOT_PG4 0x13fd +#define RTL8367C_WAKELPI_SLOT_P9_OFFSET 8 +#define RTL8367C_WAKELPI_SLOT_P9_MASK 0x1F00 +#define RTL8367C_WAKELPI_SLOT_P8_OFFSET 0 +#define RTL8367C_WAKELPI_SLOT_P8_MASK 0x1F + +#define RTL8367C_REG_WAKELPI_SLOT_PG5 0x13fe +#define RTL8367C_WAKELPI_SLOT_PG5_OFFSET 0 +#define RTL8367C_WAKELPI_SLOT_PG5_MASK 0x1F + +/* (16'h1400)mtrpool_reg */ + +#define RTL8367C_REG_METER0_RATE_CTRL0 0x1400 + +#define RTL8367C_REG_METER0_RATE_CTRL1 0x1401 +#define RTL8367C_METER0_RATE_CTRL1_OFFSET 0 +#define RTL8367C_METER0_RATE_CTRL1_MASK 0x7 + +#define RTL8367C_REG_METER1_RATE_CTRL0 0x1402 + +#define RTL8367C_REG_METER1_RATE_CTRL1 0x1403 +#define RTL8367C_METER1_RATE_CTRL1_OFFSET 0 +#define RTL8367C_METER1_RATE_CTRL1_MASK 0x7 + +#define RTL8367C_REG_METER2_RATE_CTRL0 0x1404 + +#define RTL8367C_REG_METER2_RATE_CTRL1 0x1405 +#define RTL8367C_METER2_RATE_CTRL1_OFFSET 0 +#define RTL8367C_METER2_RATE_CTRL1_MASK 0x7 + +#define RTL8367C_REG_METER3_RATE_CTRL0 0x1406 + +#define RTL8367C_REG_METER3_RATE_CTRL1 0x1407 +#define RTL8367C_METER3_RATE_CTRL1_OFFSET 0 +#define RTL8367C_METER3_RATE_CTRL1_MASK 0x7 + +#define RTL8367C_REG_METER4_RATE_CTRL0 0x1408 + +#define RTL8367C_REG_METER4_RATE_CTRL1 0x1409 +#define RTL8367C_METER4_RATE_CTRL1_OFFSET 0 +#define RTL8367C_METER4_RATE_CTRL1_MASK 0x7 + +#define RTL8367C_REG_METER5_RATE_CTRL0 0x140a + +#define RTL8367C_REG_METER5_RATE_CTRL1 0x140b +#define RTL8367C_METER5_RATE_CTRL1_OFFSET 0 +#define RTL8367C_METER5_RATE_CTRL1_MASK 0x7 + +#define RTL8367C_REG_METER6_RATE_CTRL0 0x140c + +#define RTL8367C_REG_METER6_RATE_CTRL1 0x140d +#define RTL8367C_METER6_RATE_CTRL1_OFFSET 0 +#define RTL8367C_METER6_RATE_CTRL1_MASK 0x7 + +#define RTL8367C_REG_METER7_RATE_CTRL0 0x140e + +#define RTL8367C_REG_METER7_RATE_CTRL1 0x140f +#define RTL8367C_METER7_RATE_CTRL1_OFFSET 0 +#define RTL8367C_METER7_RATE_CTRL1_MASK 0x7 + +#define RTL8367C_REG_METER8_RATE_CTRL0 0x1410 + +#define RTL8367C_REG_METER8_RATE_CTRL1 0x1411 +#define RTL8367C_METER8_RATE_CTRL1_OFFSET 0 +#define RTL8367C_METER8_RATE_CTRL1_MASK 0x7 + +#define RTL8367C_REG_METER9_RATE_CTRL0 0x1412 + +#define RTL8367C_REG_METER9_RATE_CTRL1 0x1413 +#define RTL8367C_METER9_RATE_CTRL1_OFFSET 0 +#define RTL8367C_METER9_RATE_CTRL1_MASK 0x7 + +#define RTL8367C_REG_METER10_RATE_CTRL0 0x1414 + +#define RTL8367C_REG_METER10_RATE_CTRL1 0x1415 +#define RTL8367C_METER10_RATE_CTRL1_OFFSET 0 +#define RTL8367C_METER10_RATE_CTRL1_MASK 0x7 + +#define RTL8367C_REG_METER11_RATE_CTRL0 0x1416 + +#define RTL8367C_REG_METER11_RATE_CTRL1 0x1417 +#define RTL8367C_METER11_RATE_CTRL1_OFFSET 0 +#define RTL8367C_METER11_RATE_CTRL1_MASK 0x7 + +#define RTL8367C_REG_METER12_RATE_CTRL0 0x1418 + +#define RTL8367C_REG_METER12_RATE_CTRL1 0x1419 +#define RTL8367C_METER12_RATE_CTRL1_OFFSET 0 +#define RTL8367C_METER12_RATE_CTRL1_MASK 0x7 + +#define RTL8367C_REG_METER13_RATE_CTRL0 0x141a + +#define RTL8367C_REG_METER13_RATE_CTRL1 0x141b +#define RTL8367C_METER13_RATE_CTRL1_OFFSET 0 +#define RTL8367C_METER13_RATE_CTRL1_MASK 0x7 + +#define RTL8367C_REG_METER14_RATE_CTRL0 0x141c + +#define RTL8367C_REG_METER14_RATE_CTRL1 0x141d +#define RTL8367C_METER14_RATE_CTRL1_OFFSET 0 +#define RTL8367C_METER14_RATE_CTRL1_MASK 0x7 + +#define RTL8367C_REG_METER15_RATE_CTRL0 0x141e + +#define RTL8367C_REG_METER15_RATE_CTRL1 0x141f +#define RTL8367C_METER15_RATE_CTRL1_OFFSET 0 +#define RTL8367C_METER15_RATE_CTRL1_MASK 0x7 + +#define RTL8367C_REG_METER16_RATE_CTRL0 0x1420 + +#define RTL8367C_REG_METER16_RATE_CTRL1 0x1421 +#define RTL8367C_METER16_RATE_CTRL1_OFFSET 0 +#define RTL8367C_METER16_RATE_CTRL1_MASK 0x7 + +#define RTL8367C_REG_METER17_RATE_CTRL0 0x1422 + +#define RTL8367C_REG_METER17_RATE_CTRL1 0x1423 +#define RTL8367C_METER17_RATE_CTRL1_OFFSET 0 +#define RTL8367C_METER17_RATE_CTRL1_MASK 0x7 + +#define RTL8367C_REG_METER18_RATE_CTRL0 0x1424 + +#define RTL8367C_REG_METER18_RATE_CTRL1 0x1425 +#define RTL8367C_METER18_RATE_CTRL1_OFFSET 0 +#define RTL8367C_METER18_RATE_CTRL1_MASK 0x7 + +#define RTL8367C_REG_METER19_RATE_CTRL0 0x1426 + +#define RTL8367C_REG_METER19_RATE_CTRL1 0x1427 +#define RTL8367C_METER19_RATE_CTRL1_OFFSET 0 +#define RTL8367C_METER19_RATE_CTRL1_MASK 0x7 + +#define RTL8367C_REG_METER20_RATE_CTRL0 0x1428 + +#define RTL8367C_REG_METER20_RATE_CTRL1 0x1429 +#define RTL8367C_METER20_RATE_CTRL1_OFFSET 0 +#define RTL8367C_METER20_RATE_CTRL1_MASK 0x7 + +#define RTL8367C_REG_METER21_RATE_CTRL0 0x142a + +#define RTL8367C_REG_METER21_RATE_CTRL1 0x142b +#define RTL8367C_METER21_RATE_CTRL1_OFFSET 0 +#define RTL8367C_METER21_RATE_CTRL1_MASK 0x7 + +#define RTL8367C_REG_METER22_RATE_CTRL0 0x142c + +#define RTL8367C_REG_METER22_RATE_CTRL1 0x142d +#define RTL8367C_METER22_RATE_CTRL1_OFFSET 0 +#define RTL8367C_METER22_RATE_CTRL1_MASK 0x7 + +#define RTL8367C_REG_METER23_RATE_CTRL0 0x142e + +#define RTL8367C_REG_METER23_RATE_CTRL1 0x142f +#define RTL8367C_METER23_RATE_CTRL1_OFFSET 0 +#define RTL8367C_METER23_RATE_CTRL1_MASK 0x7 + +#define RTL8367C_REG_METER24_RATE_CTRL0 0x1430 + +#define RTL8367C_REG_METER24_RATE_CTRL1 0x1431 +#define RTL8367C_METER24_RATE_CTRL1_OFFSET 0 +#define RTL8367C_METER24_RATE_CTRL1_MASK 0x7 + +#define RTL8367C_REG_METER25_RATE_CTRL0 0x1432 + +#define RTL8367C_REG_METER25_RATE_CTRL1 0x1433 +#define RTL8367C_METER25_RATE_CTRL1_OFFSET 0 +#define RTL8367C_METER25_RATE_CTRL1_MASK 0x7 + +#define RTL8367C_REG_METER26_RATE_CTRL0 0x1434 + +#define RTL8367C_REG_METER26_RATE_CTRL1 0x1435 +#define RTL8367C_METER26_RATE_CTRL1_OFFSET 0 +#define RTL8367C_METER26_RATE_CTRL1_MASK 0x7 + +#define RTL8367C_REG_METER27_RATE_CTRL0 0x1436 + +#define RTL8367C_REG_METER27_RATE_CTRL1 0x1437 +#define RTL8367C_METER27_RATE_CTRL1_OFFSET 0 +#define RTL8367C_METER27_RATE_CTRL1_MASK 0x7 + +#define RTL8367C_REG_METER28_RATE_CTRL0 0x1438 + +#define RTL8367C_REG_METER28_RATE_CTRL1 0x1439 +#define RTL8367C_METER28_RATE_CTRL1_OFFSET 0 +#define RTL8367C_METER28_RATE_CTRL1_MASK 0x7 + +#define RTL8367C_REG_METER29_RATE_CTRL0 0x143a + +#define RTL8367C_REG_METER29_RATE_CTRL1 0x143b +#define RTL8367C_METER29_RATE_CTRL1_OFFSET 0 +#define RTL8367C_METER29_RATE_CTRL1_MASK 0x7 + +#define RTL8367C_REG_METER30_RATE_CTRL0 0x143c + +#define RTL8367C_REG_METER30_RATE_CTRL1 0x143d +#define RTL8367C_METER30_RATE_CTRL1_OFFSET 0 +#define RTL8367C_METER30_RATE_CTRL1_MASK 0x7 + +#define RTL8367C_REG_METER31_RATE_CTRL0 0x143e + +#define RTL8367C_REG_METER31_RATE_CTRL1 0x143f +#define RTL8367C_METER31_RATE_CTRL1_OFFSET 0 +#define RTL8367C_METER31_RATE_CTRL1_MASK 0x7 + +#define RTL8367C_REG_METER_MODE_SETTING0 0x1440 + +#define RTL8367C_REG_METER_MODE_SETTING1 0x1441 + +#define RTL8367C_REG_METER_MODE_TOKEN_CFG 0x1442 +#define RTL8367C_METER_MODE_TOKEN_CFG_OFFSET 0 +#define RTL8367C_METER_MODE_TOKEN_CFG_MASK 0x7FF + +#define RTL8367C_REG_METER0_BUCKET_SIZE 0x1600 + +#define RTL8367C_REG_METER1_BUCKET_SIZE 0x1601 + +#define RTL8367C_REG_METER2_BUCKET_SIZE 0x1602 + +#define RTL8367C_REG_METER3_BUCKET_SIZE 0x1603 + +#define RTL8367C_REG_METER4_BUCKET_SIZE 0x1604 + +#define RTL8367C_REG_METER5_BUCKET_SIZE 0x1605 + +#define RTL8367C_REG_METER6_BUCKET_SIZE 0x1606 + +#define RTL8367C_REG_METER7_BUCKET_SIZE 0x1607 + +#define RTL8367C_REG_METER8_BUCKET_SIZE 0x1608 + +#define RTL8367C_REG_METER9_BUCKET_SIZE 0x1609 + +#define RTL8367C_REG_METER10_BUCKET_SIZE 0x160a + +#define RTL8367C_REG_METER11_BUCKET_SIZE 0x160b + +#define RTL8367C_REG_METER12_BUCKET_SIZE 0x160c + +#define RTL8367C_REG_METER13_BUCKET_SIZE 0x160d + +#define RTL8367C_REG_METER14_BUCKET_SIZE 0x160e + +#define RTL8367C_REG_METER15_BUCKET_SIZE 0x160f + +#define RTL8367C_REG_METER16_BUCKET_SIZE 0x1610 + +#define RTL8367C_REG_METER17_BUCKET_SIZE 0x1611 + +#define RTL8367C_REG_METER18_BUCKET_SIZE 0x1612 + +#define RTL8367C_REG_METER19_BUCKET_SIZE 0x1613 + +#define RTL8367C_REG_METER20_BUCKET_SIZE 0x1614 + +#define RTL8367C_REG_METER21_BUCKET_SIZE 0x1615 + +#define RTL8367C_REG_METER22_BUCKET_SIZE 0x1616 + +#define RTL8367C_REG_METER23_BUCKET_SIZE 0x1617 + +#define RTL8367C_REG_METER24_BUCKET_SIZE 0x1618 + +#define RTL8367C_REG_METER25_BUCKET_SIZE 0x1619 + +#define RTL8367C_REG_METER26_BUCKET_SIZE 0x161a + +#define RTL8367C_REG_METER27_BUCKET_SIZE 0x161b + +#define RTL8367C_REG_METER28_BUCKET_SIZE 0x161c + +#define RTL8367C_REG_METER29_BUCKET_SIZE 0x161d + +#define RTL8367C_REG_METER30_BUCKET_SIZE 0x161e + +#define RTL8367C_REG_METER31_BUCKET_SIZE 0x161f + +#define RTL8367C_REG_METER_CTRL0 0x1700 +#define RTL8367C_METER_OP_OFFSET 8 +#define RTL8367C_METER_OP_MASK 0x100 +#define RTL8367C_METER_TICK_OFFSET 0 +#define RTL8367C_METER_TICK_MASK 0xFF + +#define RTL8367C_REG_METER_CTRL1 0x1701 +#define RTL8367C_METER_CTRL1_OFFSET 0 +#define RTL8367C_METER_CTRL1_MASK 0xFF + +#define RTL8367C_REG_METER_OVERRATE_INDICATOR0 0x1702 + +#define RTL8367C_REG_METER_OVERRATE_INDICATOR1 0x1703 + +#define RTL8367C_REG_METER_OVERRATE_INDICATOR0_8051 0x1704 + +#define RTL8367C_REG_METER_OVERRATE_INDICATOR1_8051 0x1705 + +#define RTL8367C_REG_METER_IFG_CTRL0 0x1712 +#define RTL8367C_METER15_IFG_OFFSET 15 +#define RTL8367C_METER15_IFG_MASK 0x8000 +#define RTL8367C_METER14_IFG_OFFSET 14 +#define RTL8367C_METER14_IFG_MASK 0x4000 +#define RTL8367C_METER13_IFG_OFFSET 13 +#define RTL8367C_METER13_IFG_MASK 0x2000 +#define RTL8367C_METER12_IFG_OFFSET 12 +#define RTL8367C_METER12_IFG_MASK 0x1000 +#define RTL8367C_METER11_IFG_OFFSET 11 +#define RTL8367C_METER11_IFG_MASK 0x800 +#define RTL8367C_METER10_IFG_OFFSET 10 +#define RTL8367C_METER10_IFG_MASK 0x400 +#define RTL8367C_METER9_IFG_OFFSET 9 +#define RTL8367C_METER9_IFG_MASK 0x200 +#define RTL8367C_METER8_IFG_OFFSET 8 +#define RTL8367C_METER8_IFG_MASK 0x100 +#define RTL8367C_METER7_IFG_OFFSET 7 +#define RTL8367C_METER7_IFG_MASK 0x80 +#define RTL8367C_METER6_IFG_OFFSET 6 +#define RTL8367C_METER6_IFG_MASK 0x40 +#define RTL8367C_METER5_IFG_OFFSET 5 +#define RTL8367C_METER5_IFG_MASK 0x20 +#define RTL8367C_METER4_IFG_OFFSET 4 +#define RTL8367C_METER4_IFG_MASK 0x10 +#define RTL8367C_METER3_IFG_OFFSET 3 +#define RTL8367C_METER3_IFG_MASK 0x8 +#define RTL8367C_METER2_IFG_OFFSET 2 +#define RTL8367C_METER2_IFG_MASK 0x4 +#define RTL8367C_METER1_IFG_OFFSET 1 +#define RTL8367C_METER1_IFG_MASK 0x2 +#define RTL8367C_METER0_IFG_OFFSET 0 +#define RTL8367C_METER0_IFG_MASK 0x1 + +#define RTL8367C_REG_METER_IFG_CTRL1 0x1713 +#define RTL8367C_METER31_IFG_OFFSET 15 +#define RTL8367C_METER31_IFG_MASK 0x8000 +#define RTL8367C_METER30_IFG_OFFSET 14 +#define RTL8367C_METER30_IFG_MASK 0x4000 +#define RTL8367C_METER29_IFG_OFFSET 13 +#define RTL8367C_METER29_IFG_MASK 0x2000 +#define RTL8367C_METER28_IFG_OFFSET 12 +#define RTL8367C_METER28_IFG_MASK 0x1000 +#define RTL8367C_METER27_IFG_OFFSET 11 +#define RTL8367C_METER27_IFG_MASK 0x800 +#define RTL8367C_METER26_IFG_OFFSET 10 +#define RTL8367C_METER26_IFG_MASK 0x400 +#define RTL8367C_METER25_IFG_OFFSET 9 +#define RTL8367C_METER25_IFG_MASK 0x200 +#define RTL8367C_METER24_IFG_OFFSET 8 +#define RTL8367C_METER24_IFG_MASK 0x100 +#define RTL8367C_METER23_IFG_OFFSET 7 +#define RTL8367C_METER23_IFG_MASK 0x80 +#define RTL8367C_METER22_IFG_OFFSET 6 +#define RTL8367C_METER22_IFG_MASK 0x40 +#define RTL8367C_METER21_IFG_OFFSET 5 +#define RTL8367C_METER21_IFG_MASK 0x20 +#define RTL8367C_METER20_IFG_OFFSET 4 +#define RTL8367C_METER20_IFG_MASK 0x10 +#define RTL8367C_METER19_IFG_OFFSET 3 +#define RTL8367C_METER19_IFG_MASK 0x8 +#define RTL8367C_METER18_IFG_OFFSET 2 +#define RTL8367C_METER18_IFG_MASK 0x4 +#define RTL8367C_METER17_IFG_OFFSET 1 +#define RTL8367C_METER17_IFG_MASK 0x2 +#define RTL8367C_METER16_IFG_OFFSET 0 +#define RTL8367C_METER16_IFG_MASK 0x1 + +#define RTL8367C_REG_METER_CTRL2 0x1722 +#define RTL8367C_cfg_mtr_tick_8g_OFFSET 8 +#define RTL8367C_cfg_mtr_tick_8g_MASK 0xFF00 +#define RTL8367C_cfg_mtr_dec_cnt_8g_OFFSET 0 +#define RTL8367C_cfg_mtr_dec_cnt_8g_MASK 0xFF + +#define RTL8367C_REG_DUMMY_1723 0x1723 + +#define RTL8367C_REG_DUMMY_1724 0x1724 + +#define RTL8367C_REG_DUMMY_1725 0x1725 + +#define RTL8367C_REG_DUMMY_1726 0x1726 + +#define RTL8367C_REG_DUMMY_1727 0x1727 + +#define RTL8367C_REG_DUMMY_1728 0x1728 + +#define RTL8367C_REG_DUMMY_1729 0x1729 + +#define RTL8367C_REG_DUMMY_172A 0x172a + +#define RTL8367C_REG_DUMMY_172B 0x172b + +#define RTL8367C_REG_DUMMY_172C 0x172c + +#define RTL8367C_REG_DUMMY_172D 0x172d + +#define RTL8367C_REG_DUMMY_172E 0x172e + +#define RTL8367C_REG_DUMMY_172F 0x172f + +#define RTL8367C_REG_DUMMY_1730 0x1730 + +#define RTL8367C_REG_DUMMY_1731 0x1731 + +#define RTL8367C_REG_METER32_RATE_CTRL0 0x1740 + +#define RTL8367C_REG_METER32_RATE_CTRL1 0x1741 +#define RTL8367C_METER32_RATE_CTRL1_OFFSET 0 +#define RTL8367C_METER32_RATE_CTRL1_MASK 0x7 + +#define RTL8367C_REG_METER33_RATE_CTRL0 0x1742 + +#define RTL8367C_REG_METER33_RATE_CTRL1 0x1743 +#define RTL8367C_METER33_RATE_CTRL1_OFFSET 0 +#define RTL8367C_METER33_RATE_CTRL1_MASK 0x7 + +#define RTL8367C_REG_METER34_RATE_CTRL0 0x1744 + +#define RTL8367C_REG_METER34_RATE_CTRL1 0x1745 +#define RTL8367C_METER34_RATE_CTRL1_OFFSET 0 +#define RTL8367C_METER34_RATE_CTRL1_MASK 0x7 + +#define RTL8367C_REG_METER35_RATE_CTRL0 0x1746 + +#define RTL8367C_REG_METER35_RATE_CTRL1 0x1747 +#define RTL8367C_METER35_RATE_CTRL1_OFFSET 0 +#define RTL8367C_METER35_RATE_CTRL1_MASK 0x7 + +#define RTL8367C_REG_METER36_RATE_CTRL0 0x1748 + +#define RTL8367C_REG_METER36_RATE_CTRL1 0x1749 +#define RTL8367C_METER36_RATE_CTRL1_OFFSET 0 +#define RTL8367C_METER36_RATE_CTRL1_MASK 0x7 + +#define RTL8367C_REG_METER37_RATE_CTRL0 0x174a + +#define RTL8367C_REG_METER37_RATE_CTRL1 0x174b +#define RTL8367C_METER37_RATE_CTRL1_OFFSET 0 +#define RTL8367C_METER37_RATE_CTRL1_MASK 0x7 + +#define RTL8367C_REG_METER38_RATE_CTRL0 0x174c + +#define RTL8367C_REG_METER38_RATE_CTRL1 0x174d +#define RTL8367C_METER38_RATE_CTRL1_OFFSET 0 +#define RTL8367C_METER38_RATE_CTRL1_MASK 0x7 + +#define RTL8367C_REG_METER39_RATE_CTRL0 0x174e + +#define RTL8367C_REG_METER39_RATE_CTRL1 0x174f +#define RTL8367C_METER39_RATE_CTRL1_OFFSET 0 +#define RTL8367C_METER39_RATE_CTRL1_MASK 0x7 + +#define RTL8367C_REG_METER40_RATE_CTRL0 0x1750 + +#define RTL8367C_REG_METER40_RATE_CTRL1 0x1751 +#define RTL8367C_METER40_RATE_CTRL1_OFFSET 0 +#define RTL8367C_METER40_RATE_CTRL1_MASK 0x7 + +#define RTL8367C_REG_METER41_RATE_CTRL0 0x1752 + +#define RTL8367C_REG_METER41_RATE_CTRL1 0x1753 +#define RTL8367C_METER41_RATE_CTRL1_OFFSET 0 +#define RTL8367C_METER41_RATE_CTRL1_MASK 0x7 + +#define RTL8367C_REG_METER42_RATE_CTRL0 0x1754 + +#define RTL8367C_REG_METER42_RATE_CTRL1 0x1755 +#define RTL8367C_METER42_RATE_CTRL1_OFFSET 0 +#define RTL8367C_METER42_RATE_CTRL1_MASK 0x7 + +#define RTL8367C_REG_METER43_RATE_CTRL0 0x1756 + +#define RTL8367C_REG_METER43_RATE_CTRL1 0x1757 +#define RTL8367C_METER43_RATE_CTRL1_OFFSET 0 +#define RTL8367C_METER43_RATE_CTRL1_MASK 0x7 + +#define RTL8367C_REG_METER44_RATE_CTRL0 0x1758 + +#define RTL8367C_REG_METER44_RATE_CTRL1 0x1759 +#define RTL8367C_METER44_RATE_CTRL1_OFFSET 0 +#define RTL8367C_METER44_RATE_CTRL1_MASK 0x7 + +#define RTL8367C_REG_METER45_RATE_CTRL0 0x175a + +#define RTL8367C_REG_METER45_RATE_CTRL1 0x175b +#define RTL8367C_METER45_RATE_CTRL1_OFFSET 0 +#define RTL8367C_METER45_RATE_CTRL1_MASK 0x7 + +#define RTL8367C_REG_METER46_RATE_CTRL0 0x175c + +#define RTL8367C_REG_METER46_RATE_CTRL1 0x175d +#define RTL8367C_METER46_RATE_CTRL1_OFFSET 0 +#define RTL8367C_METER46_RATE_CTRL1_MASK 0x7 + +#define RTL8367C_REG_METER47_RATE_CTRL0 0x175e + +#define RTL8367C_REG_METER47_RATE_CTRL1 0x175f +#define RTL8367C_METER47_RATE_CTRL1_OFFSET 0 +#define RTL8367C_METER47_RATE_CTRL1_MASK 0x7 + +#define RTL8367C_REG_METER48_RATE_CTRL0 0x1760 + +#define RTL8367C_REG_METER48_RATE_CTRL1 0x1761 +#define RTL8367C_METER48_RATE_CTRL1_OFFSET 0 +#define RTL8367C_METER48_RATE_CTRL1_MASK 0x7 + +#define RTL8367C_REG_METER49_RATE_CTRL0 0x1762 + +#define RTL8367C_REG_METER49_RATE_CTRL1 0x1763 +#define RTL8367C_METER49_RATE_CTRL1_OFFSET 0 +#define RTL8367C_METER49_RATE_CTRL1_MASK 0x7 + +#define RTL8367C_REG_METER50_RATE_CTRL0 0x1764 + +#define RTL8367C_REG_METER50_RATE_CTRL1 0x1765 +#define RTL8367C_METER50_RATE_CTRL1_OFFSET 0 +#define RTL8367C_METER50_RATE_CTRL1_MASK 0x7 + +#define RTL8367C_REG_METER51_RATE_CTRL0 0x1766 + +#define RTL8367C_REG_METER51_RATE_CTRL1 0x1767 +#define RTL8367C_METER51_RATE_CTRL1_OFFSET 0 +#define RTL8367C_METER51_RATE_CTRL1_MASK 0x7 + +#define RTL8367C_REG_METER52_RATE_CTRL0 0x1768 + +#define RTL8367C_REG_METER52_RATE_CTRL1 0x1769 +#define RTL8367C_METER52_RATE_CTRL1_OFFSET 0 +#define RTL8367C_METER52_RATE_CTRL1_MASK 0x7 + +#define RTL8367C_REG_METER53_RATE_CTRL0 0x176a + +#define RTL8367C_REG_METER53_RATE_CTRL1 0x176b +#define RTL8367C_METER53_RATE_CTRL1_OFFSET 0 +#define RTL8367C_METER53_RATE_CTRL1_MASK 0x7 + +#define RTL8367C_REG_METER54_RATE_CTRL0 0x176c + +#define RTL8367C_REG_METER54_RATE_CTRL1 0x176d +#define RTL8367C_METER54_RATE_CTRL1_OFFSET 0 +#define RTL8367C_METER54_RATE_CTRL1_MASK 0x7 + +#define RTL8367C_REG_METER55_RATE_CTRL0 0x176e + +#define RTL8367C_REG_METER55_RATE_CTRL1 0x176f +#define RTL8367C_METER55_RATE_CTRL1_OFFSET 0 +#define RTL8367C_METER55_RATE_CTRL1_MASK 0x7 + +#define RTL8367C_REG_METER56_RATE_CTRL0 0x1770 + +#define RTL8367C_REG_METER56_RATE_CTRL1 0x1771 +#define RTL8367C_METER56_RATE_CTRL1_OFFSET 0 +#define RTL8367C_METER56_RATE_CTRL1_MASK 0x7 + +#define RTL8367C_REG_METER57_RATE_CTRL0 0x1772 + +#define RTL8367C_REG_METER57_RATE_CTRL1 0x1773 +#define RTL8367C_METER57_RATE_CTRL1_OFFSET 0 +#define RTL8367C_METER57_RATE_CTRL1_MASK 0x7 + +#define RTL8367C_REG_METER58_RATE_CTRL0 0x1774 + +#define RTL8367C_REG_METER58_RATE_CTRL1 0x1775 +#define RTL8367C_METER58_RATE_CTRL1_OFFSET 0 +#define RTL8367C_METER58_RATE_CTRL1_MASK 0x7 + +#define RTL8367C_REG_METER59_RATE_CTRL0 0x1776 + +#define RTL8367C_REG_METER59_RATE_CTRL1 0x1777 +#define RTL8367C_METER59_RATE_CTRL1_OFFSET 0 +#define RTL8367C_METER59_RATE_CTRL1_MASK 0x7 + +#define RTL8367C_REG_METER60_RATE_CTRL0 0x1778 + +#define RTL8367C_REG_METER60_RATE_CTRL1 0x1779 +#define RTL8367C_METER60_RATE_CTRL1_OFFSET 0 +#define RTL8367C_METER60_RATE_CTRL1_MASK 0x7 + +#define RTL8367C_REG_METER61_RATE_CTRL0 0x177a + +#define RTL8367C_REG_METER61_RATE_CTRL1 0x177b +#define RTL8367C_METER61_RATE_CTRL1_OFFSET 0 +#define RTL8367C_METER61_RATE_CTRL1_MASK 0x7 + +#define RTL8367C_REG_METER62_RATE_CTRL0 0x177c + +#define RTL8367C_REG_METER62_RATE_CTRL1 0x177d +#define RTL8367C_METER62_RATE_CTRL1_OFFSET 0 +#define RTL8367C_METER62_RATE_CTRL1_MASK 0x7 + +#define RTL8367C_REG_METER63_RATE_CTRL0 0x177e + +#define RTL8367C_REG_METER63_RATE_CTRL1 0x177f +#define RTL8367C_METER63_RATE_CTRL1_OFFSET 0 +#define RTL8367C_METER63_RATE_CTRL1_MASK 0x7 + +#define RTL8367C_REG_METER_MODE_SETTING2 0x1780 + +#define RTL8367C_REG_METER_MODE_SETTING3 0x1781 + +#define RTL8367C_REG_METER32_BUCKET_SIZE 0x1790 + +#define RTL8367C_REG_METER33_BUCKET_SIZE 0x1791 + +#define RTL8367C_REG_METER34_BUCKET_SIZE 0x1792 + +#define RTL8367C_REG_METER35_BUCKET_SIZE 0x1793 + +#define RTL8367C_REG_METER36_BUCKET_SIZE 0x1794 + +#define RTL8367C_REG_METER37_BUCKET_SIZE 0x1795 + +#define RTL8367C_REG_METER38_BUCKET_SIZE 0x1796 + +#define RTL8367C_REG_METER39_BUCKET_SIZE 0x1797 + +#define RTL8367C_REG_METER40_BUCKET_SIZE 0x1798 + +#define RTL8367C_REG_METER41_BUCKET_SIZE 0x1799 + +#define RTL8367C_REG_METER42_BUCKET_SIZE 0x179a + +#define RTL8367C_REG_METER43_BUCKET_SIZE 0x179b + +#define RTL8367C_REG_METER44_BUCKET_SIZE 0x179c + +#define RTL8367C_REG_METER45_BUCKET_SIZE 0x179d + +#define RTL8367C_REG_METER46_BUCKET_SIZE 0x179e + +#define RTL8367C_REG_METER47_BUCKET_SIZE 0x179f + +#define RTL8367C_REG_METER48_BUCKET_SIZE 0x17a0 + +#define RTL8367C_REG_METER49_BUCKET_SIZE 0x17a1 + +#define RTL8367C_REG_METER50_BUCKET_SIZE 0x17a2 + +#define RTL8367C_REG_METER51_BUCKET_SIZE 0x17a3 + +#define RTL8367C_REG_METER52_BUCKET_SIZE 0x17a4 + +#define RTL8367C_REG_METER53_BUCKET_SIZE 0x17a5 + +#define RTL8367C_REG_METER54_BUCKET_SIZE 0x17a6 + +#define RTL8367C_REG_METER55_BUCKET_SIZE 0x17a7 + +#define RTL8367C_REG_METER56_BUCKET_SIZE 0x17a8 + +#define RTL8367C_REG_METER57_BUCKET_SIZE 0x17a9 + +#define RTL8367C_REG_METER58_BUCKET_SIZE 0x17aa + +#define RTL8367C_REG_METER59_BUCKET_SIZE 0x17ab + +#define RTL8367C_REG_METER60_BUCKET_SIZE 0x17ac + +#define RTL8367C_REG_METER61_BUCKET_SIZE 0x17ad + +#define RTL8367C_REG_METER62_BUCKET_SIZE 0x17ae + +#define RTL8367C_REG_METER63_BUCKET_SIZE 0x17af + +#define RTL8367C_REG_METER_OVERRATE_INDICATOR2 0x17b0 + +#define RTL8367C_REG_METER_OVERRATE_INDICATOR3 0x17b1 + +#define RTL8367C_REG_METER_OVERRATE_INDICATOR2_8051 0x17b2 + +#define RTL8367C_REG_METER_OVERRATE_INDICATOR3_8051 0x17b3 + +#define RTL8367C_REG_METER_IFG_CTRL2 0x17b4 +#define RTL8367C_METER47_IFG_OFFSET 15 +#define RTL8367C_METER47_IFG_MASK 0x8000 +#define RTL8367C_METER46_IFG_OFFSET 14 +#define RTL8367C_METER46_IFG_MASK 0x4000 +#define RTL8367C_METER45_IFG_OFFSET 13 +#define RTL8367C_METER45_IFG_MASK 0x2000 +#define RTL8367C_METER44_IFG_OFFSET 12 +#define RTL8367C_METER44_IFG_MASK 0x1000 +#define RTL8367C_METER43_IFG_OFFSET 11 +#define RTL8367C_METER43_IFG_MASK 0x800 +#define RTL8367C_METER42_IFG_OFFSET 10 +#define RTL8367C_METER42_IFG_MASK 0x400 +#define RTL8367C_METER41_IFG_OFFSET 9 +#define RTL8367C_METER41_IFG_MASK 0x200 +#define RTL8367C_METER40_IFG_OFFSET 8 +#define RTL8367C_METER40_IFG_MASK 0x100 +#define RTL8367C_METER39_IFG_OFFSET 7 +#define RTL8367C_METER39_IFG_MASK 0x80 +#define RTL8367C_METER38_IFG_OFFSET 6 +#define RTL8367C_METER38_IFG_MASK 0x40 +#define RTL8367C_METER37_IFG_OFFSET 5 +#define RTL8367C_METER37_IFG_MASK 0x20 +#define RTL8367C_METER36_IFG_OFFSET 4 +#define RTL8367C_METER36_IFG_MASK 0x10 +#define RTL8367C_METER35_IFG_OFFSET 3 +#define RTL8367C_METER35_IFG_MASK 0x8 +#define RTL8367C_METER34_IFG_OFFSET 2 +#define RTL8367C_METER34_IFG_MASK 0x4 +#define RTL8367C_METER33_IFG_OFFSET 1 +#define RTL8367C_METER33_IFG_MASK 0x2 +#define RTL8367C_METER32_IFG_OFFSET 0 +#define RTL8367C_METER32_IFG_MASK 0x1 + +#define RTL8367C_REG_METER_IFG_CTRL3 0x17b5 +#define RTL8367C_METER63_IFG_OFFSET 15 +#define RTL8367C_METER63_IFG_MASK 0x8000 +#define RTL8367C_METER62_IFG_OFFSET 14 +#define RTL8367C_METER62_IFG_MASK 0x4000 +#define RTL8367C_METER61_IFG_OFFSET 13 +#define RTL8367C_METER61_IFG_MASK 0x2000 +#define RTL8367C_METER60_IFG_OFFSET 12 +#define RTL8367C_METER60_IFG_MASK 0x1000 +#define RTL8367C_METER59_IFG_OFFSET 11 +#define RTL8367C_METER59_IFG_MASK 0x800 +#define RTL8367C_METER58_IFG_OFFSET 10 +#define RTL8367C_METER58_IFG_MASK 0x400 +#define RTL8367C_METER57_IFG_OFFSET 9 +#define RTL8367C_METER57_IFG_MASK 0x200 +#define RTL8367C_METER56_IFG_OFFSET 8 +#define RTL8367C_METER56_IFG_MASK 0x100 +#define RTL8367C_METER55_IFG_OFFSET 7 +#define RTL8367C_METER55_IFG_MASK 0x80 +#define RTL8367C_METER54_IFG_OFFSET 6 +#define RTL8367C_METER54_IFG_MASK 0x40 +#define RTL8367C_METER53_IFG_OFFSET 5 +#define RTL8367C_METER53_IFG_MASK 0x20 +#define RTL8367C_METER52_IFG_OFFSET 4 +#define RTL8367C_METER52_IFG_MASK 0x10 +#define RTL8367C_METER51_IFG_OFFSET 3 +#define RTL8367C_METER51_IFG_MASK 0x8 +#define RTL8367C_METER50_IFG_OFFSET 2 +#define RTL8367C_METER50_IFG_MASK 0x4 +#define RTL8367C_METER49_IFG_OFFSET 1 +#define RTL8367C_METER49_IFG_MASK 0x2 +#define RTL8367C_METER48_IFG_OFFSET 0 +#define RTL8367C_METER48_IFG_MASK 0x1 + +#define RTL8367C_REG_METER_MISC 0x17b6 +#define RTL8367C_METER_MISC_OFFSET 0 +#define RTL8367C_METER_MISC_MASK 0x1 + +/* (16'h1800)8051_RLDP_EEE_reg */ + +#define RTL8367C_REG_EEELLDP_CTRL0 0x1820 +#define RTL8367C_EEELLDP_SUBTYPE_OFFSET 6 +#define RTL8367C_EEELLDP_SUBTYPE_MASK 0x3FC0 +#define RTL8367C_EEELLDP_TRAP_8051_OFFSET 2 +#define RTL8367C_EEELLDP_TRAP_8051_MASK 0x4 +#define RTL8367C_EEELLDP_TRAP_CPU_OFFSET 1 +#define RTL8367C_EEELLDP_TRAP_CPU_MASK 0x2 +#define RTL8367C_EEELLDP_ENABLE_OFFSET 0 +#define RTL8367C_EEELLDP_ENABLE_MASK 0x1 + +#define RTL8367C_REG_EEELLDP_PMSK 0x1822 +#define RTL8367C_EEELLDP_PMSK_OFFSET 0 +#define RTL8367C_EEELLDP_PMSK_MASK 0x7FF + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P00_08 0x1843 + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P00_07 0x1844 + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P00_06 0x1845 + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P00_05 0x1846 + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P00_04 0x1847 + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P00_03 0x1848 + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P00_02 0x1849 + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P00_01 0x184a + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P00_00 0x184b + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P01_08 0x184c + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P01_07 0x184d + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P01_06 0x184e + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P01_05 0x184f + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P01_04 0x1850 + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P01_03 0x1851 + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P01_02 0x1852 + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P01_01 0x1853 + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P01_00 0x1854 + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P02_08 0x1855 + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P02_07 0x1856 + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P02_06 0x1857 + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P02_05 0x1858 + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P02_04 0x1859 + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P02_03 0x185a + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P02_02 0x185b + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P02_01 0x185c + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P02_00 0x185d + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P03_08 0x185e + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P03_07 0x185f + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P03_06 0x1860 + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P03_05 0x1861 + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P03_04 0x1862 + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P03_03 0x1863 + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P03_02 0x1864 + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P03_01 0x1865 + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P03_00 0x1866 + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P04_08 0x1867 + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P04_07 0x1868 + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P04_06 0x1869 + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P04_05 0x186a + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P04_04 0x186b + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P04_03 0x186c + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P04_02 0x186d + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P04_01 0x186e + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P04_00 0x186f + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P05_08 0x1870 + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P05_07 0x1871 + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P05_06 0x1872 + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P05_05 0x1873 + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P05_04 0x1874 + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P05_03 0x1875 + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P05_02 0x1876 + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P05_01 0x1877 + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P05_00 0x1878 + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P06_08 0x1879 + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P06_07 0x187a + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P06_06 0x187b + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P06_05 0x187c + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P06_04 0x187d + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P06_03 0x187e + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P06_02 0x187f + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P06_01 0x1880 + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P06_00 0x1881 + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P07_08 0x1882 + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P07_07 0x1883 + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P07_06 0x1884 + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P07_05 0x1885 + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P07_04 0x1886 + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P07_03 0x1887 + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P07_02 0x1888 + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P07_01 0x1889 + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P07_00 0x188a + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P08_08 0x188b + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P08_07 0x188c + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P08_06 0x188d + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P08_05 0x188e + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P08_04 0x188f + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P08_03 0x1890 + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P08_02 0x1891 + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P08_01 0x1892 + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P08_00 0x1893 + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P09_08 0x1894 + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P09_07 0x1895 + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P09_06 0x1896 + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P09_05 0x1897 + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P09_04 0x1898 + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P09_03 0x1899 + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P09_02 0x189a + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P09_01 0x189b + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P09_00 0x189c + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P10_08 0x189d + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P10_07 0x189e + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P10_06 0x189f + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P10_05 0x18a0 + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P10_04 0x18a1 + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P10_03 0x18a2 + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P10_02 0x18a3 + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P10_01 0x18a4 + +#define RTL8367C_REG_EEELLDP_RX_VALUE_P10_00 0x18a5 + +#define RTL8367C_REG_RLDP_CTRL0 0x18e0 +#define RTL8367C_RLDP_TRIGGER_MODE_OFFSET 14 +#define RTL8367C_RLDP_TRIGGER_MODE_MASK 0x4000 +#define RTL8367C_RLDP_8051_LOOP_PORTMSK_OFFSET 6 +#define RTL8367C_RLDP_8051_LOOP_PORTMSK_MASK 0x3FC0 +#define RTL8367C_RLPP_8051_TRAP_OFFSET 5 +#define RTL8367C_RLPP_8051_TRAP_MASK 0x20 +#define RTL8367C_RLDP_INDICATOR_SOURCE_OFFSET 4 +#define RTL8367C_RLDP_INDICATOR_SOURCE_MASK 0x10 +#define RTL8367C_RLDP_GEN_RANDOM_OFFSET 3 +#define RTL8367C_RLDP_GEN_RANDOM_MASK 0x8 +#define RTL8367C_RLDP_COMP_ID_OFFSET 2 +#define RTL8367C_RLDP_COMP_ID_MASK 0x4 +#define RTL8367C_RLDP_8051_ENABLE_OFFSET 1 +#define RTL8367C_RLDP_8051_ENABLE_MASK 0x2 +#define RTL8367C_RLDP_ENABLE_OFFSET 0 +#define RTL8367C_RLDP_ENABLE_MASK 0x1 + +#define RTL8367C_REG_RLDP_CTRL1 0x18e1 +#define RTL8367C_RLDP_RETRY_COUNT_LOOPSTATE_OFFSET 8 +#define RTL8367C_RLDP_RETRY_COUNT_LOOPSTATE_MASK 0xFF00 +#define RTL8367C_RLDP_RETRY_COUNT_CHKSTATE_OFFSET 0 +#define RTL8367C_RLDP_RETRY_COUNT_CHKSTATE_MASK 0xFF + +#define RTL8367C_REG_RLDP_CTRL2 0x18e2 + +#define RTL8367C_REG_RLDP_CTRL3 0x18e3 + +#define RTL8367C_REG_RLDP_CTRL4 0x18e4 +#define RTL8367C_RLDP_CTRL4_OFFSET 0 +#define RTL8367C_RLDP_CTRL4_MASK 0x7FF + +#define RTL8367C_REG_RLDP_RAND_NUM0 0x18e5 + +#define RTL8367C_REG_RLDP_RAND_NUM1 0x18e6 + +#define RTL8367C_REG_RLDP_RAND_NUM2 0x18e7 + +#define RTL8367C_REG_RLDP_MAGIC_NUM0 0x18e8 + +#define RTL8367C_REG_RLDP_MAGIC_NUM1 0x18e9 + +#define RTL8367C_REG_RLDP_MAGIC_NUM2 0x18ea + +#define RTL8367C_REG_RLDP_LOOPED_INDICATOR 0x18eb +#define RTL8367C_RLDP_LOOPED_INDICATOR_OFFSET 0 +#define RTL8367C_RLDP_LOOPED_INDICATOR_MASK 0x7FF + +#define RTL8367C_REG_RLDP_LOOP_PORT_REG0 0x18ec +#define RTL8367C_RLDP_LOOP_PORT_01_OFFSET 8 +#define RTL8367C_RLDP_LOOP_PORT_01_MASK 0xF00 +#define RTL8367C_RLDP_LOOP_PORT_00_OFFSET 0 +#define RTL8367C_RLDP_LOOP_PORT_00_MASK 0xF + +#define RTL8367C_REG_RLDP_LOOP_PORT_REG1 0x18ed +#define RTL8367C_RLDP_LOOP_PORT_03_OFFSET 8 +#define RTL8367C_RLDP_LOOP_PORT_03_MASK 0xF00 +#define RTL8367C_RLDP_LOOP_PORT_02_OFFSET 0 +#define RTL8367C_RLDP_LOOP_PORT_02_MASK 0xF + +#define RTL8367C_REG_RLDP_LOOP_PORT_REG2 0x18ee +#define RTL8367C_RLDP_LOOP_PORT_05_OFFSET 8 +#define RTL8367C_RLDP_LOOP_PORT_05_MASK 0xF00 +#define RTL8367C_RLDP_LOOP_PORT_04_OFFSET 0 +#define RTL8367C_RLDP_LOOP_PORT_04_MASK 0xF + +#define RTL8367C_REG_RLDP_LOOP_PORT_REG3 0x18ef +#define RTL8367C_RLDP_LOOP_PORT_07_OFFSET 8 +#define RTL8367C_RLDP_LOOP_PORT_07_MASK 0xF00 +#define RTL8367C_RLDP_LOOP_PORT_06_OFFSET 0 +#define RTL8367C_RLDP_LOOP_PORT_06_MASK 0xF + +#define RTL8367C_REG_RLDP_RELEASED_INDICATOR 0x18f0 +#define RTL8367C_RLDP_RELEASED_INDICATOR_OFFSET 0 +#define RTL8367C_RLDP_RELEASED_INDICATOR_MASK 0x7FF + +#define RTL8367C_REG_RLDP_LOOPSTATUS_INDICATOR 0x18f1 +#define RTL8367C_RLDP_LOOPSTATUS_INDICATOR_OFFSET 0 +#define RTL8367C_RLDP_LOOPSTATUS_INDICATOR_MASK 0x7FF + +#define RTL8367C_REG_RLDP_LOOP_PORT_REG4 0x18f2 +#define RTL8367C_RLDP_LOOP_PORT_9_OFFSET 8 +#define RTL8367C_RLDP_LOOP_PORT_9_MASK 0xF00 +#define RTL8367C_RLDP_LOOP_PORT_8_OFFSET 0 +#define RTL8367C_RLDP_LOOP_PORT_8_MASK 0xF + +#define RTL8367C_REG_RLDP_LOOP_PORT_REG5 0x18f3 +#define RTL8367C_RLDP_LOOP_PORT_REG5_OFFSET 0 +#define RTL8367C_RLDP_LOOP_PORT_REG5_MASK 0xF + +#define RTL8367C_REG_RLDP_CTRL5 0x18f4 +#define RTL8367C_RLDP_CTRL5_OFFSET 0 +#define RTL8367C_RLDP_CTRL5_MASK 0x7 + +/* (16'h1900)EEE_EEEP_reg */ + +#define RTL8367C_REG_EEE_500M_CTRL0 0x1900 +#define RTL8367C_EEE_500M_CTRL0_OFFSET 0 +#define RTL8367C_EEE_500M_CTRL0_MASK 0xFF + +#define RTL8367C_REG_EEE_RXIDLE_GIGA_CTRL 0x1901 +#define RTL8367C_EEE_RXIDLE_GIGA_EN_OFFSET 8 +#define RTL8367C_EEE_RXIDLE_GIGA_EN_MASK 0x100 +#define RTL8367C_EEE_RXIDLE_GIGA_OFFSET 0 +#define RTL8367C_EEE_RXIDLE_GIGA_MASK 0xFF + +#define RTL8367C_REG_EEE_RXIDLE_500M_CTRL 0x1902 +#define RTL8367C_EEE_RXIDLE_500M_EN_OFFSET 8 +#define RTL8367C_EEE_RXIDLE_500M_EN_MASK 0x100 +#define RTL8367C_EEE_RXIDLE_500M_OFFSET 0 +#define RTL8367C_EEE_RXIDLE_500M_MASK 0xFF + +#define RTL8367C_REG_EEE_DECISION_GIGA_500M 0x1903 +#define RTL8367C_EEE_DECISION_GIGA_OFFSET 8 +#define RTL8367C_EEE_DECISION_GIGA_MASK 0xFF00 +#define RTL8367C_EEE_DECISION_500M_OFFSET 0 +#define RTL8367C_EEE_DECISION_500M_MASK 0xFF + +#define RTL8367C_REG_EEE_DECISION_100M 0x1904 +#define RTL8367C_EEE_DECISION_100M_OFFSET 0 +#define RTL8367C_EEE_DECISION_100M_MASK 0xFF + +#define RTL8367C_REG_EEEP_DEFER_TXLPI 0x1905 +#define RTL8367C_EEEP_DEFER_TXLPI_OFFSET 0 +#define RTL8367C_EEEP_DEFER_TXLPI_MASK 0x1 + +#define RTL8367C_REG_EEEP_EN 0x1906 +#define RTL8367C_EEEP_SLAVE_EN_OFFSET 3 +#define RTL8367C_EEEP_SLAVE_EN_MASK 0x8 +#define RTL8367C_EEEP_100M_OFFSET 2 +#define RTL8367C_EEEP_100M_MASK 0x4 +#define RTL8367C_EEEP_500M_OFFSET 1 +#define RTL8367C_EEEP_500M_MASK 0x2 +#define RTL8367C_EEEP_GIGA_OFFSET 0 +#define RTL8367C_EEEP_GIGA_MASK 0x1 + +#define RTL8367C_REG_EEEP_TI_GIGA_500M 0x1907 +#define RTL8367C_EEEP_TI_GIGA_OFFSET 8 +#define RTL8367C_EEEP_TI_GIGA_MASK 0xFF00 +#define RTL8367C_EEEP_TI_500M_OFFSET 0 +#define RTL8367C_EEEP_TI_500M_MASK 0xFF + +#define RTL8367C_REG_EEEP_TI_100M 0x1908 +#define RTL8367C_EEEP_TI_100M_OFFSET 0 +#define RTL8367C_EEEP_TI_100M_MASK 0xFF + +#define RTL8367C_REG_EEEP_CTRL2 0x1909 +#define RTL8367C_EEEP_CTRL2_OFFSET 0 +#define RTL8367C_EEEP_CTRL2_MASK 0xFF + +#define RTL8367C_REG_EEEP_RX_RATE_500M 0x190b + +#define RTL8367C_REG_EEEP_RW_GIGA_SLV 0x190c +#define RTL8367C_EEEP_RW_GIGA_SLV_OFFSET 0 +#define RTL8367C_EEEP_RW_GIGA_SLV_MASK 0xFF + +#define RTL8367C_REG_EEEP_TMR_GIGA 0x190d +#define RTL8367C_RX_IDLE_EEEP_GIGA_OFFSET 8 +#define RTL8367C_RX_IDLE_EEEP_GIGA_MASK 0xFF00 +#define RTL8367C_RX_MIN_SLP_TMR_GIGA_OFFSET 0 +#define RTL8367C_RX_MIN_SLP_TMR_GIGA_MASK 0xFF + +#define RTL8367C_REG_EEEP_TMR_500M 0x190e +#define RTL8367C_RX_IDLE_EEEP_500M_OFFSET 8 +#define RTL8367C_RX_IDLE_EEEP_500M_MASK 0xFF00 +#define RTL8367C_RX_MIN_SLP_TMR_500M_OFFSET 0 +#define RTL8367C_RX_MIN_SLP_TMR_500M_MASK 0xFF + +#define RTL8367C_REG_EEEP_TMR_100M 0x190f +#define RTL8367C_RX_IDLE_EEEP_100M_OFFSET 8 +#define RTL8367C_RX_IDLE_EEEP_100M_MASK 0xFF00 +#define RTL8367C_RX_MIN_SLP_TMR_100M_OFFSET 0 +#define RTL8367C_RX_MIN_SLP_TMR_100M_MASK 0xFF + +#define RTL8367C_REG_EEEP_RW_500M_MST_SLV 0x1910 +#define RTL8367C_EEEP_RW_500M_MST_OFFSET 8 +#define RTL8367C_EEEP_RW_500M_MST_MASK 0xFF00 +#define RTL8367C_EEEP_RW_500M_SLV_OFFSET 0 +#define RTL8367C_EEEP_RW_500M_SLV_MASK 0xFF + +#define RTL8367C_REG_EEEP_500M_CTRL0 0x1911 +#define RTL8367C_EEEP_500M_CTRL0_OFFSET 0 +#define RTL8367C_EEEP_500M_CTRL0_MASK 0xFF + +#define RTL8367C_REG_EEEP_500M_CTRL1 0x1912 +#define RTL8367C_EEEP_TW_500M_OFFSET 8 +#define RTL8367C_EEEP_TW_500M_MASK 0xFF00 +#define RTL8367C_EEEP_TP_500M_OFFSET 0 +#define RTL8367C_EEEP_TP_500M_MASK 0xFF + +#define RTL8367C_REG_EEEP_500M_CTRL2 0x1913 +#define RTL8367C_EEEP_TXEN_500M_OFFSET 12 +#define RTL8367C_EEEP_TXEN_500M_MASK 0x1000 +#define RTL8367C_EEEP_TU_500M_OFFSET 8 +#define RTL8367C_EEEP_TU_500M_MASK 0x300 +#define RTL8367C_EEEP_TS_500M_OFFSET 0 +#define RTL8367C_EEEP_TS_500M_MASK 0xFF + +#define RTL8367C_REG_EEE_NEW_CTRL0 0x1914 +#define RTL8367C_LINK_UP_DELAY_OFFSET 3 +#define RTL8367C_LINK_UP_DELAY_MASK 0x18 +#define RTL8367C_EEE_TXLPI_ORI_OFFSET 2 +#define RTL8367C_EEE_TXLPI_ORI_MASK 0x4 +#define RTL8367C_REALTX_SEL_OFFSET 1 +#define RTL8367C_REALTX_SEL_MASK 0x2 +#define RTL8367C_EN_FC_EFCT_OFFSET 0 +#define RTL8367C_EN_FC_EFCT_MASK 0x1 + +#define RTL8367C_REG_EEE_LONGIDLE_100M 0x1915 +#define RTL8367C_EEE_LONGIDLE_100M_OFFSET 0 +#define RTL8367C_EEE_LONGIDLE_100M_MASK 0x3FF + +#define RTL8367C_REG_EEE_LONGIDLE_500M 0x1916 +#define RTL8367C_EEE_LONGIDLE_500M_OFFSET 0 +#define RTL8367C_EEE_LONGIDLE_500M_MASK 0x3FF + +#define RTL8367C_REG_EEE_LONGIDLE_GIGA 0x1917 +#define RTL8367C_EEE_LONGIDLE_GIGA_OFFSET 0 +#define RTL8367C_EEE_LONGIDLE_GIGA_MASK 0x3FF + +#define RTL8367C_REG_EEE_MINIPG_100M 0x1918 + +#define RTL8367C_REG_EEE_MINIPG_500M 0x1919 + +#define RTL8367C_REG_EEE_MINIPG_GIGA 0x191A + +#define RTL8367C_REG_EEE_LONGIDLE_CTRL0 0x191B +#define RTL8367C_TX_IDLEN_REQ_100M_OFFSET 10 +#define RTL8367C_TX_IDLEN_REQ_100M_MASK 0x400 +#define RTL8367C_TX_IDLEN_REQ_500M_OFFSET 9 +#define RTL8367C_TX_IDLEN_REQ_500M_MASK 0x200 +#define RTL8367C_TX_IDLEN_REQ_GIGA_OFFSET 8 +#define RTL8367C_TX_IDLEN_REQ_GIGA_MASK 0x100 +#define RTL8367C_EEE_LONGIDLE_CTRL0_TX_LPI_MINIPG_100M_OFFSET 0 +#define RTL8367C_EEE_LONGIDLE_CTRL0_TX_LPI_MINIPG_100M_MASK 0xFF + +#define RTL8367C_REG_EEE_LONGIDLE_CTRL1 0x191C +#define RTL8367C_EEE_LONGIDLE_CTRL1_TX_LPI_MINIPG_GELITE_OFFSET 8 +#define RTL8367C_EEE_LONGIDLE_CTRL1_TX_LPI_MINIPG_GELITE_MASK 0xFF00 +#define RTL8367C_EEE_LONGIDLE_CTRL1_TX_LPI_MINIPG_GIGA_OFFSET 0 +#define RTL8367C_EEE_LONGIDLE_CTRL1_TX_LPI_MINIPG_GIGA_MASK 0xFF + +#define RTL8367C_REG_EEE_TD_CTRL_H 0x191d +#define RTL8367C_REF_RXLPI_OFFSET 8 +#define RTL8367C_REF_RXLPI_MASK 0x100 +#define RTL8367C_LOW_Q_TX_DELAY_GE_500M_H_OFFSET 4 +#define RTL8367C_LOW_Q_TX_DELAY_GE_500M_H_MASK 0xF0 +#define RTL8367C_LOW_Q_TX_DELAY_FE_H_OFFSET 0 +#define RTL8367C_LOW_Q_TX_DELAY_FE_H_MASK 0xF + +/* (16'h1a00)nic_reg */ + +#define RTL8367C_REG_NIC_RXRDRL 0x1a04 +#define RTL8367C_NIC_RXRDRL_OFFSET 0 +#define RTL8367C_NIC_RXRDRL_MASK 0xFF + +#define RTL8367C_REG_NIC_RXRDRH 0x1a05 +#define RTL8367C_NIC_RXRDRH_OFFSET 0 +#define RTL8367C_NIC_RXRDRH_MASK 0xFF + +#define RTL8367C_REG_NIC_TXASRL 0x1a08 +#define RTL8367C_NIC_TXASRL_OFFSET 0 +#define RTL8367C_NIC_TXASRL_MASK 0xFF + +#define RTL8367C_REG_NIC_TXASRH 0x1a09 +#define RTL8367C_NIC_TXASRH_OFFSET 0 +#define RTL8367C_NIC_TXASRH_MASK 0xFF + +#define RTL8367C_REG_NIC_RXCMDR 0x1a0c +#define RTL8367C_NIC_RXCMDR_OFFSET 0 +#define RTL8367C_NIC_RXCMDR_MASK 0x1 + +#define RTL8367C_REG_NIC_TXCMDR 0x1a0d +#define RTL8367C_NIC_TXCMDR_OFFSET 0 +#define RTL8367C_NIC_TXCMDR_MASK 0x1 + +#define RTL8367C_REG_NIC_IMS 0x1a0e +#define RTL8367C_NIC_RXIS_OFFSET 7 +#define RTL8367C_NIC_RXIS_MASK 0x80 +#define RTL8367C_NIC_TXIS_OFFSET 6 +#define RTL8367C_NIC_TXIS_MASK 0x40 +#define RTL8367C_NIC_TXES_OFFSET 5 +#define RTL8367C_NIC_TXES_MASK 0x20 +#define RTL8367C_NIC_IMS_DMY_OFFSET 4 +#define RTL8367C_NIC_IMS_DMY_MASK 0x10 +#define RTL8367C_NIC_RXBUS_OFFSET 3 +#define RTL8367C_NIC_RXBUS_MASK 0x8 +#define RTL8367C_NIC_TXBOS_OFFSET 2 +#define RTL8367C_NIC_TXBOS_MASK 0x4 +#define RTL8367C_NIC_RXMIS_OFFSET 1 +#define RTL8367C_NIC_RXMIS_MASK 0x2 +#define RTL8367C_NIC_TXNLS_OFFSET 0 +#define RTL8367C_NIC_TXNLS_MASK 0x1 + +#define RTL8367C_REG_NIC_IMR 0x1a0f +#define RTL8367C_NIC_RXIE_OFFSET 7 +#define RTL8367C_NIC_RXIE_MASK 0x80 +#define RTL8367C_NIC_TXIE_OFFSET 6 +#define RTL8367C_NIC_TXIE_MASK 0x40 +#define RTL8367C_NIC_TXEE_OFFSET 5 +#define RTL8367C_NIC_TXEE_MASK 0x20 +#define RTL8367C_NIC_IMR_DMY_OFFSET 4 +#define RTL8367C_NIC_IMR_DMY_MASK 0x10 +#define RTL8367C_NIC_RXBUE_OFFSET 3 +#define RTL8367C_NIC_RXBUE_MASK 0x8 +#define RTL8367C_NIC_TXBOE_OFFSET 2 +#define RTL8367C_NIC_TXBOE_MASK 0x4 +#define RTL8367C_NIC_RXMIE_OFFSET 1 +#define RTL8367C_NIC_RXMIE_MASK 0x2 +#define RTL8367C_NIC_TXNLE_OFFSET 0 +#define RTL8367C_NIC_TXNLE_MASK 0x1 + +#define RTL8367C_REG_NIC_RXCR0 0x1a14 +#define RTL8367C_NIC_HFPPE_OFFSET 7 +#define RTL8367C_NIC_HFPPE_MASK 0x80 +#define RTL8367C_NIC_HFMPE_OFFSET 6 +#define RTL8367C_NIC_HFMPE_MASK 0x40 +#define RTL8367C_NIC_RXBPE_OFFSET 5 +#define RTL8367C_NIC_RXBPE_MASK 0x20 +#define RTL8367C_NIC_RXMPE_OFFSET 4 +#define RTL8367C_NIC_RXMPE_MASK 0x10 +#define RTL8367C_NIC_RXPPS_OFFSET 2 +#define RTL8367C_NIC_RXPPS_MASK 0xC +#define RTL8367C_NIC_RXAPE_OFFSET 1 +#define RTL8367C_NIC_RXAPE_MASK 0x2 +#define RTL8367C_NIC_ARPPE_OFFSET 0 +#define RTL8367C_NIC_ARPPE_MASK 0x1 + +#define RTL8367C_REG_NIC_RXCR1 0x1a15 +#define RTL8367C_NIC_RL4CEPE_OFFSET 4 +#define RTL8367C_NIC_RL4CEPE_MASK 0x10 +#define RTL8367C_NIC_RL3CEPE_OFFSET 3 +#define RTL8367C_NIC_RL3CEPE_MASK 0x8 +#define RTL8367C_NIC_RCRCEPE_OFFSET 2 +#define RTL8367C_NIC_RCRCEPE_MASK 0x4 +#define RTL8367C_NIC_RMCRC_OFFSET 1 +#define RTL8367C_NIC_RMCRC_MASK 0x2 +#define RTL8367C_NIC_RXENABLE_OFFSET 0 +#define RTL8367C_NIC_RXENABLE_MASK 0x1 + +#define RTL8367C_REG_NIC_TXCR 0x1a16 +#define RTL8367C_NIC_LBE_OFFSET 2 +#define RTL8367C_NIC_LBE_MASK 0x4 +#define RTL8367C_NIC_TXMFM_OFFSET 1 +#define RTL8367C_NIC_TXMFM_MASK 0x2 +#define RTL8367C_NIC_TXENABLE_OFFSET 0 +#define RTL8367C_NIC_TXENABLE_MASK 0x1 + +#define RTL8367C_REG_NIC_GCR 0x1a17 +#define RTL8367C_DUMMY_7_6_OFFSET 6 +#define RTL8367C_DUMMY_7_6_MASK 0xC0 +#define RTL8367C_NIC_RXMTU_OFFSET 4 +#define RTL8367C_NIC_RXMTU_MASK 0x30 +#define RTL8367C_NIC_GCR_DUMMY_0_OFFSET 0 +#define RTL8367C_NIC_GCR_DUMMY_0_MASK 0x1 + +#define RTL8367C_REG_NIC_MHR0 0x1a24 +#define RTL8367C_NIC_MHR0_OFFSET 0 +#define RTL8367C_NIC_MHR0_MASK 0xFF + +#define RTL8367C_REG_NIC_MHR1 0x1a25 +#define RTL8367C_NIC_MHR1_OFFSET 0 +#define RTL8367C_NIC_MHR1_MASK 0xFF + +#define RTL8367C_REG_NIC_MHR2 0x1a26 +#define RTL8367C_NIC_MHR2_OFFSET 0 +#define RTL8367C_NIC_MHR2_MASK 0xFF + +#define RTL8367C_REG_NIC_MHR3 0x1a27 +#define RTL8367C_NIC_MHR3_OFFSET 0 +#define RTL8367C_NIC_MHR3_MASK 0xFF + +#define RTL8367C_REG_NIC_MHR4 0x1a28 +#define RTL8367C_NIC_MHR4_OFFSET 0 +#define RTL8367C_NIC_MHR4_MASK 0xFF + +#define RTL8367C_REG_NIC_MHR5 0x1a29 +#define RTL8367C_NIC_MHR5_OFFSET 0 +#define RTL8367C_NIC_MHR5_MASK 0xFF + +#define RTL8367C_REG_NIC_MHR6 0x1a2a +#define RTL8367C_NIC_MHR6_OFFSET 0 +#define RTL8367C_NIC_MHR6_MASK 0xFF + +#define RTL8367C_REG_NIC_MHR7 0x1a2b +#define RTL8367C_NIC_MHR7_OFFSET 0 +#define RTL8367C_NIC_MHR7_MASK 0xFF + +#define RTL8367C_REG_NIC_PAHR0 0x1a2c +#define RTL8367C_NIC_PAHR0_OFFSET 0 +#define RTL8367C_NIC_PAHR0_MASK 0xFF + +#define RTL8367C_REG_NIC_PAHR1 0x1a2d +#define RTL8367C_NIC_PAHR1_OFFSET 0 +#define RTL8367C_NIC_PAHR1_MASK 0xFF + +#define RTL8367C_REG_NIC_PAHR2 0x1a2e +#define RTL8367C_NIC_PAHR2_OFFSET 0 +#define RTL8367C_NIC_PAHR2_MASK 0xFF + +#define RTL8367C_REG_NIC_PAHR3 0x1a2f +#define RTL8367C_NIC_PAHR3_OFFSET 0 +#define RTL8367C_NIC_PAHR3_MASK 0xFF + +#define RTL8367C_REG_NIC_PAHR4 0x1a30 +#define RTL8367C_NIC_PAHR4_OFFSET 0 +#define RTL8367C_NIC_PAHR4_MASK 0xFF + +#define RTL8367C_REG_NIC_PAHR5 0x1a31 +#define RTL8367C_NIC_PAHR5_OFFSET 0 +#define RTL8367C_NIC_PAHR5_MASK 0xFF + +#define RTL8367C_REG_NIC_PAHR6 0x1a32 +#define RTL8367C_NIC_PAHR6_OFFSET 0 +#define RTL8367C_NIC_PAHR6_MASK 0xFF + +#define RTL8367C_REG_NIC_PAHR7 0x1a33 +#define RTL8367C_NIC_PAHR7_OFFSET 0 +#define RTL8367C_NIC_PAHR7_MASK 0xFF + +#define RTL8367C_REG_NIC_TXSTOPRL 0x1a44 +#define RTL8367C_NIC_TXSTOPRL_OFFSET 0 +#define RTL8367C_NIC_TXSTOPRL_MASK 0xFF + +#define RTL8367C_REG_NIC_TXSTOPRH 0x1a45 +#define RTL8367C_NIC_TXSTOPRH_OFFSET 0 +#define RTL8367C_NIC_TXSTOPRH_MASK 0x3 + +#define RTL8367C_REG_NIC_RXSTOPRL 0x1a46 +#define RTL8367C_NIC_RXSTOPRL_OFFSET 0 +#define RTL8367C_NIC_RXSTOPRL_MASK 0xFF + +#define RTL8367C_REG_NIC_RXSTOPRH 0x1a47 +#define RTL8367C_NIC_RXSTOPRH_OFFSET 0 +#define RTL8367C_NIC_RXSTOPRH_MASK 0x3 + +#define RTL8367C_REG_NIC_RXFSTR 0x1a48 +#define RTL8367C_NIC_RXFSTR_OFFSET 0 +#define RTL8367C_NIC_RXFSTR_MASK 0xFF + +#define RTL8367C_REG_NIC_RXMBTRL 0x1a4c +#define RTL8367C_NIC_RXMBTRL_OFFSET 0 +#define RTL8367C_NIC_RXMBTRL_MASK 0xFF + +#define RTL8367C_REG_NIC_RXMBTRH 0x1a4d +#define RTL8367C_NIC_RXMBTRH_OFFSET 0 +#define RTL8367C_NIC_RXMBTRH_MASK 0x7F + +#define RTL8367C_REG_NIC_RXMPTR 0x1a4e +#define RTL8367C_NIC_RXMPTR_OFFSET 0 +#define RTL8367C_NIC_RXMPTR_MASK 0xFF + +#define RTL8367C_REG_NIC_T0TR 0x1a4f +#define RTL8367C_NIC_T0TR_OFFSET 0 +#define RTL8367C_NIC_T0TR_MASK 0xFF + +#define RTL8367C_REG_NIC_CRXCPRL 0x1a50 +#define RTL8367C_NIC_CRXCPRL_OFFSET 0 +#define RTL8367C_NIC_CRXCPRL_MASK 0xFF + +#define RTL8367C_REG_NIC_CRXCPRH 0x1a51 +#define RTL8367C_NIC_CRXCPRH_OFFSET 0 +#define RTL8367C_NIC_CRXCPRH_MASK 0xFF + +#define RTL8367C_REG_NIC_CTXCPRL 0x1a52 +#define RTL8367C_NIC_CTXCPRL_OFFSET 0 +#define RTL8367C_NIC_CTXCPRL_MASK 0xFF + +#define RTL8367C_REG_NIC_CTXPCRH 0x1a53 +#define RTL8367C_NIC_CTXPCRH_OFFSET 0 +#define RTL8367C_NIC_CTXPCRH_MASK 0xFF + +#define RTL8367C_REG_NIC_SRXCURPKTRL 0x1a54 +#define RTL8367C_NIC_SRXCURPKTRL_OFFSET 0 +#define RTL8367C_NIC_SRXCURPKTRL_MASK 0xFF + +#define RTL8367C_REG_NIC_SRXCURPKTRH 0x1a55 +#define RTL8367C_NIC_SRXCURPKTRH_OFFSET 0 +#define RTL8367C_NIC_SRXCURPKTRH_MASK 0xFF + +#define RTL8367C_REG_NIC_STXCURPKTRL 0x1a56 +#define RTL8367C_NIC_STXCURPKTRL_OFFSET 0 +#define RTL8367C_NIC_STXCURPKTRL_MASK 0xFF + +#define RTL8367C_REG_NIC_STXCURPKTRH 0x1a57 +#define RTL8367C_NIC_STXCURPKTRH_OFFSET 0 +#define RTL8367C_NIC_STXCURPKTRH_MASK 0xFF + +#define RTL8367C_REG_NIC_STXPKTLENRL 0x1a58 +#define RTL8367C_NIC_STXPKTLENRL_OFFSET 0 +#define RTL8367C_NIC_STXPKTLENRL_MASK 0xFF + +#define RTL8367C_REG_NIC_STXPKTLENRH 0x1a59 +#define RTL8367C_NIC_STXPKTLENRH_OFFSET 0 +#define RTL8367C_NIC_STXPKTLENRH_MASK 0xFF + +#define RTL8367C_REG_NIC_STXCURUNITRL 0x1a5a +#define RTL8367C_NIC_STXCURUNITRL_OFFSET 0 +#define RTL8367C_NIC_STXCURUNITRL_MASK 0xFF + +#define RTL8367C_REG_NIC_STXCURUNITRH 0x1a5b +#define RTL8367C_NIC_STXCURUNITRH_OFFSET 0 +#define RTL8367C_NIC_STXCURUNITRH_MASK 0xFF + +#define RTL8367C_REG_NIC_DROP_MODE 0x1a5c +#define RTL8367C_NIC_RXDV_MODE_OFFSET 1 +#define RTL8367C_NIC_RXDV_MODE_MASK 0x2 +#define RTL8367C_NIC_DROP_MODE_OFFSET 0 +#define RTL8367C_NIC_DROP_MODE_MASK 0x1 + +/* (16'h1b00)LED */ + +#define RTL8367C_REG_LED_SYS_CONFIG 0x1b00 +#define RTL8367C_LED_SYS_CONFIG_DUMMY_15_OFFSET 15 +#define RTL8367C_LED_SYS_CONFIG_DUMMY_15_MASK 0x8000 +#define RTL8367C_LED_SERIAL_OUT_MODE_OFFSET 14 +#define RTL8367C_LED_SERIAL_OUT_MODE_MASK 0x4000 +#define RTL8367C_LED_EEE_LPI_MODE_OFFSET 13 +#define RTL8367C_LED_EEE_LPI_MODE_MASK 0x2000 +#define RTL8367C_LED_EEE_LPI_EN_OFFSET 12 +#define RTL8367C_LED_EEE_LPI_EN_MASK 0x1000 +#define RTL8367C_LED_EEE_LPI_10_OFFSET 11 +#define RTL8367C_LED_EEE_LPI_10_MASK 0x800 +#define RTL8367C_LED_EEE_CAP_10_OFFSET 10 +#define RTL8367C_LED_EEE_CAP_10_MASK 0x400 +#define RTL8367C_LED_LPI_SEL_OFFSET 8 +#define RTL8367C_LED_LPI_SEL_MASK 0x300 +#define RTL8367C_SERI_LED_ACT_LOW_OFFSET 7 +#define RTL8367C_SERI_LED_ACT_LOW_MASK 0x80 +#define RTL8367C_LED_POWERON_2_OFFSET 6 +#define RTL8367C_LED_POWERON_2_MASK 0x40 +#define RTL8367C_LED_POWERON_1_OFFSET 5 +#define RTL8367C_LED_POWERON_1_MASK 0x20 +#define RTL8367C_LED_POWERON_0_OFFSET 4 +#define RTL8367C_LED_POWERON_0_MASK 0x10 +#define RTL8367C_LED_IO_DISABLE_OFFSET 3 +#define RTL8367C_LED_IO_DISABLE_MASK 0x8 +#define RTL8367C_DUMMY_2_2_OFFSET 2 +#define RTL8367C_DUMMY_2_2_MASK 0x4 +#define RTL8367C_LED_SELECT_OFFSET 0 +#define RTL8367C_LED_SELECT_MASK 0x3 + +#define RTL8367C_REG_LED_SYS_CONFIG2 0x1b01 +#define RTL8367C_LED_SYS_CONFIG2_DUMMY_OFFSET 2 +#define RTL8367C_LED_SYS_CONFIG2_DUMMY_MASK 0xFFFC +#define RTL8367C_GATE_LPTD_BYPASS_OFFSET 1 +#define RTL8367C_GATE_LPTD_BYPASS_MASK 0x2 +#define RTL8367C_LED_SPD_MODE_OFFSET 0 +#define RTL8367C_LED_SPD_MODE_MASK 0x1 + +#define RTL8367C_REG_LED_MODE 0x1b02 +#define RTL8367C_DLINK_TIME_OFFSET 15 +#define RTL8367C_DLINK_TIME_MASK 0x8000 +#define RTL8367C_LED_BUZZ_DUTY_OFFSET 14 +#define RTL8367C_LED_BUZZ_DUTY_MASK 0x4000 +#define RTL8367C_BUZZER_RATE_OFFSET 12 +#define RTL8367C_BUZZER_RATE_MASK 0x3000 +#define RTL8367C_LOOP_DETECT_MODE_OFFSET 11 +#define RTL8367C_LOOP_DETECT_MODE_MASK 0x800 +#define RTL8367C_SEL_PWRON_TIME_OFFSET 9 +#define RTL8367C_SEL_PWRON_TIME_MASK 0x600 +#define RTL8367C_EN_DLINK_LED_OFFSET 8 +#define RTL8367C_EN_DLINK_LED_MASK 0x100 +#define RTL8367C_LOOP_DETECT_RATE_OFFSET 6 +#define RTL8367C_LOOP_DETECT_RATE_MASK 0xC0 +#define RTL8367C_FORCE_RATE_OFFSET 4 +#define RTL8367C_FORCE_RATE_MASK 0x30 +#define RTL8367C_SEL_LEDRATE_OFFSET 1 +#define RTL8367C_SEL_LEDRATE_MASK 0xE +#define RTL8367C_SPEED_UP_OFFSET 0 +#define RTL8367C_SPEED_UP_MASK 0x1 + +#define RTL8367C_REG_LED_CONFIGURATION 0x1b03 +#define RTL8367C_LED_CONFIGURATION_DUMMY_OFFSET 15 +#define RTL8367C_LED_CONFIGURATION_DUMMY_MASK 0x8000 +#define RTL8367C_LED_CONFIG_SEL_OFFSET 14 +#define RTL8367C_LED_CONFIG_SEL_MASK 0x4000 +#define RTL8367C_DATA_LED_OFFSET 12 +#define RTL8367C_DATA_LED_MASK 0x3000 +#define RTL8367C_LED2_CFG_OFFSET 8 +#define RTL8367C_LED2_CFG_MASK 0xF00 +#define RTL8367C_LED1_CFG_OFFSET 4 +#define RTL8367C_LED1_CFG_MASK 0xF0 +#define RTL8367C_LED0_CFG_OFFSET 0 +#define RTL8367C_LED0_CFG_MASK 0xF + +#define RTL8367C_REG_RTCT_RESULTS_CFG 0x1b04 +#define RTL8367C_RTCT_2PAIR_FTT_OFFSET 15 +#define RTL8367C_RTCT_2PAIR_FTT_MASK 0x8000 +#define RTL8367C_RTCT_2PAIR_MODE_OFFSET 14 +#define RTL8367C_RTCT_2PAIR_MODE_MASK 0x4000 +#define RTL8367C_BLINK_EN_OFFSET 13 +#define RTL8367C_BLINK_EN_MASK 0x2000 +#define RTL8367C_TIMEOUT_OFFSET 12 +#define RTL8367C_TIMEOUT_MASK 0x1000 +#define RTL8367C_EN_CD_SAME_SHORT_OFFSET 11 +#define RTL8367C_EN_CD_SAME_SHORT_MASK 0x800 +#define RTL8367C_EN_CD_SAME_OPEN_OFFSET 10 +#define RTL8367C_EN_CD_SAME_OPEN_MASK 0x400 +#define RTL8367C_EN_CD_SAME_LINEDRIVER_OFFSET 9 +#define RTL8367C_EN_CD_SAME_LINEDRIVER_MASK 0x200 +#define RTL8367C_EN_CD_SAME_MISMATCH_OFFSET 8 +#define RTL8367C_EN_CD_SAME_MISMATCH_MASK 0x100 +#define RTL8367C_EN_CD_SHORT_OFFSET 7 +#define RTL8367C_EN_CD_SHORT_MASK 0x80 +#define RTL8367C_EN_AB_SHORT_OFFSET 6 +#define RTL8367C_EN_AB_SHORT_MASK 0x40 +#define RTL8367C_EN_CD_OPEN_OFFSET 5 +#define RTL8367C_EN_CD_OPEN_MASK 0x20 +#define RTL8367C_EN_AB_OPEN_OFFSET 4 +#define RTL8367C_EN_AB_OPEN_MASK 0x10 +#define RTL8367C_EN_CD_MISMATCH_OFFSET 3 +#define RTL8367C_EN_CD_MISMATCH_MASK 0x8 +#define RTL8367C_EN_AB_MISMATCH_OFFSET 2 +#define RTL8367C_EN_AB_MISMATCH_MASK 0x4 +#define RTL8367C_EN_CD_LINEDRIVER_OFFSET 1 +#define RTL8367C_EN_CD_LINEDRIVER_MASK 0x2 +#define RTL8367C_EN_AB_LINEDRIVER_OFFSET 0 +#define RTL8367C_EN_AB_LINEDRIVER_MASK 0x1 + +#define RTL8367C_REG_RTCT_LED 0x1b05 +#define RTL8367C_DUMMY_1b05a_OFFSET 12 +#define RTL8367C_DUMMY_1b05a_MASK 0xF000 +#define RTL8367C_RTCT_LED2_OFFSET 8 +#define RTL8367C_RTCT_LED2_MASK 0xF00 +#define RTL8367C_RTCT_LED1_OFFSET 4 +#define RTL8367C_RTCT_LED1_MASK 0xF0 +#define RTL8367C_RTCT_LED0_OFFSET 0 +#define RTL8367C_RTCT_LED0_MASK 0xF + +#define RTL8367C_REG_CPU_FORCE_LED_CFG 0x1b07 +#define RTL8367C_DUMMY_1b07a_OFFSET 8 +#define RTL8367C_DUMMY_1b07a_MASK 0xFF00 +#define RTL8367C_LED_FORCE_MODE_OFFSET 2 +#define RTL8367C_LED_FORCE_MODE_MASK 0xFC +#define RTL8367C_FORCE_MODE_OFFSET 0 +#define RTL8367C_FORCE_MODE_MASK 0x3 + +#define RTL8367C_REG_CPU_FORCE_LED0_CFG0 0x1b08 +#define RTL8367C_PORT7_LED0_MODE_OFFSET 14 +#define RTL8367C_PORT7_LED0_MODE_MASK 0xC000 +#define RTL8367C_PORT6_LED0_MODE_OFFSET 12 +#define RTL8367C_PORT6_LED0_MODE_MASK 0x3000 +#define RTL8367C_PORT5_LED0_MODE_OFFSET 10 +#define RTL8367C_PORT5_LED0_MODE_MASK 0xC00 +#define RTL8367C_PORT4_LED0_MODE_OFFSET 8 +#define RTL8367C_PORT4_LED0_MODE_MASK 0x300 +#define RTL8367C_PORT3_LED0_MODE_OFFSET 6 +#define RTL8367C_PORT3_LED0_MODE_MASK 0xC0 +#define RTL8367C_PORT2_LED0_MODE_OFFSET 4 +#define RTL8367C_PORT2_LED0_MODE_MASK 0x30 +#define RTL8367C_PORT1_LED0_MODE_OFFSET 2 +#define RTL8367C_PORT1_LED0_MODE_MASK 0xC +#define RTL8367C_PORT0_LED0_MODE_OFFSET 0 +#define RTL8367C_PORT0_LED0_MODE_MASK 0x3 + +#define RTL8367C_REG_CPU_FORCE_LED0_CFG1 0x1b09 +#define RTL8367C_DUMMY_1b09a_OFFSET 4 +#define RTL8367C_DUMMY_1b09a_MASK 0xFFF0 +#define RTL8367C_PORT9_LED0_MODE_OFFSET 2 +#define RTL8367C_PORT9_LED0_MODE_MASK 0xC +#define RTL8367C_PORT8_LED0_MODE_OFFSET 0 +#define RTL8367C_PORT8_LED0_MODE_MASK 0x3 + +#define RTL8367C_REG_CPU_FORCE_LED1_CFG0 0x1b0a +#define RTL8367C_PORT7_LED1_MODE_OFFSET 14 +#define RTL8367C_PORT7_LED1_MODE_MASK 0xC000 +#define RTL8367C_PORT6_LED1_MODE_OFFSET 12 +#define RTL8367C_PORT6_LED1_MODE_MASK 0x3000 +#define RTL8367C_PORT5_LED1_MODE_OFFSET 10 +#define RTL8367C_PORT5_LED1_MODE_MASK 0xC00 +#define RTL8367C_PORT4_LED1_MODE_OFFSET 8 +#define RTL8367C_PORT4_LED1_MODE_MASK 0x300 +#define RTL8367C_PORT3_LED1_MODE_OFFSET 6 +#define RTL8367C_PORT3_LED1_MODE_MASK 0xC0 +#define RTL8367C_PORT2_LED1_MODE_OFFSET 4 +#define RTL8367C_PORT2_LED1_MODE_MASK 0x30 +#define RTL8367C_PORT1_LED1_MODE_OFFSET 2 +#define RTL8367C_PORT1_LED1_MODE_MASK 0xC +#define RTL8367C_PORT0_LED1_MODE_OFFSET 0 +#define RTL8367C_PORT0_LED1_MODE_MASK 0x3 + +#define RTL8367C_REG_CPU_FORCE_LED1_CFG1 0x1b0b +#define RTL8367C_DUMMY_1b0ba_OFFSET 4 +#define RTL8367C_DUMMY_1b0ba_MASK 0xFFF0 +#define RTL8367C_PORT9_LED1_MODE_OFFSET 2 +#define RTL8367C_PORT9_LED1_MODE_MASK 0xC +#define RTL8367C_PORT8_LED1_MODE_OFFSET 0 +#define RTL8367C_PORT8_LED1_MODE_MASK 0x3 + +#define RTL8367C_REG_CPU_FORCE_LED2_CFG0 0x1b0c +#define RTL8367C_PORT7_LED2_MODE_OFFSET 14 +#define RTL8367C_PORT7_LED2_MODE_MASK 0xC000 +#define RTL8367C_PORT6_LED2_MODE_OFFSET 12 +#define RTL8367C_PORT6_LED2_MODE_MASK 0x3000 +#define RTL8367C_PORT5_LED2_MODE_OFFSET 10 +#define RTL8367C_PORT5_LED2_MODE_MASK 0xC00 +#define RTL8367C_PORT4_LED2_MODE_OFFSET 8 +#define RTL8367C_PORT4_LED2_MODE_MASK 0x300 +#define RTL8367C_PORT3_LED2_MODE_OFFSET 6 +#define RTL8367C_PORT3_LED2_MODE_MASK 0xC0 +#define RTL8367C_PORT2_LED2_MODE_OFFSET 4 +#define RTL8367C_PORT2_LED2_MODE_MASK 0x30 +#define RTL8367C_PORT1_LED2_MODE_OFFSET 2 +#define RTL8367C_PORT1_LED2_MODE_MASK 0xC +#define RTL8367C_PORT0_LED2_MODE_OFFSET 0 +#define RTL8367C_PORT0_LED2_MODE_MASK 0x3 + +#define RTL8367C_REG_CPU_FORCE_LED2_CFG1 0x1b0d +#define RTL8367C_DUMMY_1b0da_OFFSET 4 +#define RTL8367C_DUMMY_1b0da_MASK 0xFFF0 +#define RTL8367C_PORT9_LED2_MODE_OFFSET 2 +#define RTL8367C_PORT9_LED2_MODE_MASK 0xC +#define RTL8367C_PORT8_LED2_MODE_OFFSET 0 +#define RTL8367C_PORT8_LED2_MODE_MASK 0x3 + +#define RTL8367C_REG_LED_ACTIVE_LOW_CFG0 0x1b0e +#define RTL8367C_LED_ACTIVE_LOW_CFG0_DUMMY_15_OFFSET 15 +#define RTL8367C_LED_ACTIVE_LOW_CFG0_DUMMY_15_MASK 0x8000 +#define RTL8367C_PORT3_LED_ACTIVE_LOW_OFFSET 12 +#define RTL8367C_PORT3_LED_ACTIVE_LOW_MASK 0x7000 +#define RTL8367C_LED_ACTIVE_LOW_CFG0_DUMMY_11_OFFSET 11 +#define RTL8367C_LED_ACTIVE_LOW_CFG0_DUMMY_11_MASK 0x800 +#define RTL8367C_PORT2_LED_ACTIVE_LOW_OFFSET 8 +#define RTL8367C_PORT2_LED_ACTIVE_LOW_MASK 0x700 +#define RTL8367C_DUMMY_7_OFFSET 7 +#define RTL8367C_DUMMY_7_MASK 0x80 +#define RTL8367C_PORT1_LED_ACTIVE_LOW_OFFSET 4 +#define RTL8367C_PORT1_LED_ACTIVE_LOW_MASK 0x70 +#define RTL8367C_DUMMY_3_OFFSET 3 +#define RTL8367C_DUMMY_3_MASK 0x8 +#define RTL8367C_PORT0_LED_ACTIVE_LOW_OFFSET 0 +#define RTL8367C_PORT0_LED_ACTIVE_LOW_MASK 0x7 + +#define RTL8367C_REG_LED_ACTIVE_LOW_CFG1 0x1b0f +#define RTL8367C_LED_ACTIVE_LOW_CFG1_DUMMY_15_OFFSET 15 +#define RTL8367C_LED_ACTIVE_LOW_CFG1_DUMMY_15_MASK 0x8000 +#define RTL8367C_PORT7_LED_ACTIVE_LOW_OFFSET 12 +#define RTL8367C_PORT7_LED_ACTIVE_LOW_MASK 0x7000 +#define RTL8367C_LED_ACTIVE_LOW_CFG1_DUMMY_11_OFFSET 11 +#define RTL8367C_LED_ACTIVE_LOW_CFG1_DUMMY_11_MASK 0x800 +#define RTL8367C_PORT6_LED_ACTIVE_LOW_OFFSET 8 +#define RTL8367C_PORT6_LED_ACTIVE_LOW_MASK 0x700 +#define RTL8367C_DUMMY_1b0f_b_OFFSET 7 +#define RTL8367C_DUMMY_1b0f_b_MASK 0x80 +#define RTL8367C_PORT5_LED_ACTIVE_LOW_OFFSET 4 +#define RTL8367C_PORT5_LED_ACTIVE_LOW_MASK 0x70 +#define RTL8367C_DUMMY_1b0f_a_OFFSET 3 +#define RTL8367C_DUMMY_1b0f_a_MASK 0x8 +#define RTL8367C_PORT4_LED_ACTIVE_LOW_OFFSET 0 +#define RTL8367C_PORT4_LED_ACTIVE_LOW_MASK 0x7 + +#define RTL8367C_REG_LED_ACTIVE_LOW_CFG2 0x1b10 +#define RTL8367C_DUMMY_1b10_b_OFFSET 7 +#define RTL8367C_DUMMY_1b10_b_MASK 0xFF80 +#define RTL8367C_PORT9_LED_ACTIVE_LOW_OFFSET 4 +#define RTL8367C_PORT9_LED_ACTIVE_LOW_MASK 0x70 +#define RTL8367C_DUMMY_1b10_a_OFFSET 3 +#define RTL8367C_DUMMY_1b10_a_MASK 0x8 +#define RTL8367C_PORT8_LED_ACTIVE_LOW_OFFSET 0 +#define RTL8367C_PORT8_LED_ACTIVE_LOW_MASK 0x7 + +#define RTL8367C_REG_SEL_RTCT_PARA 0x1b21 +#define RTL8367C_DO_RTCT_COMMAND_OFFSET 15 +#define RTL8367C_DO_RTCT_COMMAND_MASK 0x8000 +#define RTL8367C_SEL_RTCT_PARA_DUMMY_OFFSET 12 +#define RTL8367C_SEL_RTCT_PARA_DUMMY_MASK 0x7000 +#define RTL8367C_SEL_RTCT_RLSTLED_TIME_OFFSET 10 +#define RTL8367C_SEL_RTCT_RLSTLED_TIME_MASK 0xC00 +#define RTL8367C_SEL_RTCT_TEST_LED_TIME_OFFSET 8 +#define RTL8367C_SEL_RTCT_TEST_LED_TIME_MASK 0x300 +#define RTL8367C_EN_SCAN_RTCT_OFFSET 7 +#define RTL8367C_EN_SCAN_RTCT_MASK 0x80 +#define RTL8367C_EN_RTCT_TIMOUT_OFFSET 6 +#define RTL8367C_EN_RTCT_TIMOUT_MASK 0x40 +#define RTL8367C_EN_ALL_RTCT_OFFSET 5 +#define RTL8367C_EN_ALL_RTCT_MASK 0x20 +#define RTL8367C_SEL_RTCT_PLE_WID_OFFSET 0 +#define RTL8367C_SEL_RTCT_PLE_WID_MASK 0x1F + +#define RTL8367C_REG_RTCT_ENABLE 0x1b22 +#define RTL8367C_RTCT_ENABLE_DUMMY_OFFSET 8 +#define RTL8367C_RTCT_ENABLE_DUMMY_MASK 0xFF00 +#define RTL8367C_RTCT_ENABLE_PORT_MASK_OFFSET 0 +#define RTL8367C_RTCT_ENABLE_PORT_MASK_MASK 0xFF + +#define RTL8367C_REG_RTCT_TIMEOUT 0x1b23 + +#define RTL8367C_REG_PARA_LED_IO_EN1 0x1b24 +#define RTL8367C_LED1_PARA_P07_00_OFFSET 8 +#define RTL8367C_LED1_PARA_P07_00_MASK 0xFF00 +#define RTL8367C_LED0_PARA_P07_00_OFFSET 0 +#define RTL8367C_LED0_PARA_P07_00_MASK 0xFF + +#define RTL8367C_REG_PARA_LED_IO_EN2 0x1b25 +#define RTL8367C_DUMMY_15_8_OFFSET 8 +#define RTL8367C_DUMMY_15_8_MASK 0xFF00 +#define RTL8367C_LED2_PARA_P07_00_OFFSET 0 +#define RTL8367C_LED2_PARA_P07_00_MASK 0xFF + +#define RTL8367C_REG_SCAN0_LED_IO_EN1 0x1b26 +#define RTL8367C_SCAN0_LED_IO_EN1_DUMMY_OFFSET 3 +#define RTL8367C_SCAN0_LED_IO_EN1_DUMMY_MASK 0xFFF8 +#define RTL8367C_LED_LOOP_DET_BUZZER_EN_OFFSET 2 +#define RTL8367C_LED_LOOP_DET_BUZZER_EN_MASK 0x4 +#define RTL8367C_LED_SERI_DATA_EN_OFFSET 1 +#define RTL8367C_LED_SERI_DATA_EN_MASK 0x2 +#define RTL8367C_LED_SERI_CLK_EN_OFFSET 0 +#define RTL8367C_LED_SERI_CLK_EN_MASK 0x1 + +#define RTL8367C_REG_SCAN1_LED_IO_EN2 0x1b27 +#define RTL8367C_LED_SCAN1_BI_PORT_EN_OFFSET 8 +#define RTL8367C_LED_SCAN1_BI_PORT_EN_MASK 0xFF00 +#define RTL8367C_LED_SCAN1_BI_STA_EN_OFFSET 7 +#define RTL8367C_LED_SCAN1_BI_STA_EN_MASK 0x80 +#define RTL8367C_SCAN1_LED_IO_EN2_DUMMY_0_OFFSET 6 +#define RTL8367C_SCAN1_LED_IO_EN2_DUMMY_0_MASK 0x40 +#define RTL8367C_LED_SCAN1_SI_PORT_EN_OFFSET 2 +#define RTL8367C_LED_SCAN1_SI_PORT_EN_MASK 0x3C +#define RTL8367C_LED_SCAN1_SI_STA_EN_OFFSET 0 +#define RTL8367C_LED_SCAN1_SI_STA_EN_MASK 0x3 + +#define RTL8367C_REG_LPI_LED_OPT1 0x1b28 +#define RTL8367C_LPI_TAG4_OFFSET 12 +#define RTL8367C_LPI_TAG4_MASK 0xF000 +#define RTL8367C_LPI_TAG3_OFFSET 8 +#define RTL8367C_LPI_TAG3_MASK 0xF00 +#define RTL8367C_LPI_TAG2_OFFSET 4 +#define RTL8367C_LPI_TAG2_MASK 0xF0 +#define RTL8367C_LPI_TAG1_OFFSET 0 +#define RTL8367C_LPI_TAG1_MASK 0xF + +#define RTL8367C_REG_LPI_LED_OPT2 0x1b29 +#define RTL8367C_LPI_LED_OPT2_DUMMY_OFFSET 15 +#define RTL8367C_LPI_LED_OPT2_DUMMY_MASK 0x8000 +#define RTL8367C_LPI_LED2_WEAK_OFFSET 14 +#define RTL8367C_LPI_LED2_WEAK_MASK 0x4000 +#define RTL8367C_LPI_LED1_WEAK_OFFSET 13 +#define RTL8367C_LPI_LED1_WEAK_MASK 0x2000 +#define RTL8367C_LPI_LED0_WEAK_OFFSET 12 +#define RTL8367C_LPI_LED0_WEAK_MASK 0x1000 +#define RTL8367C_LPI_LED2_OFFSET 11 +#define RTL8367C_LPI_LED2_MASK 0x800 +#define RTL8367C_LPI_LED1_OFFSET 10 +#define RTL8367C_LPI_LED1_MASK 0x400 +#define RTL8367C_LPI_LED0_OFFSET 9 +#define RTL8367C_LPI_LED0_MASK 0x200 +#define RTL8367C_LPI_TAG8_OFFSET 8 +#define RTL8367C_LPI_TAG8_MASK 0x100 +#define RTL8367C_LPI_TAG7_OFFSET 6 +#define RTL8367C_LPI_TAG7_MASK 0xC0 +#define RTL8367C_LPI_TAG6_OFFSET 4 +#define RTL8367C_LPI_TAG6_MASK 0x30 +#define RTL8367C_LPI_TAG5_OFFSET 0 +#define RTL8367C_LPI_TAG5_MASK 0xF + +#define RTL8367C_REG_LPI_LED_OPT3 0x1b2a +#define RTL8367C_LPI_LED_OPT3_DUMMY_OFFSET 3 +#define RTL8367C_LPI_LED_OPT3_DUMMY_MASK 0xFFF8 +#define RTL8367C_RESTORE_LED_RATE_SEL_OFFSET 1 +#define RTL8367C_RESTORE_LED_RATE_SEL_MASK 0x6 +#define RTL8367C_RESTORE_LED_SEL_OFFSET 0 +#define RTL8367C_RESTORE_LED_SEL_MASK 0x1 + +#define RTL8367C_REG_P0_LED_MUX 0x1b2b +#define RTL8367C_CFG_P0_LED2_MUX_OFFSET 10 +#define RTL8367C_CFG_P0_LED2_MUX_MASK 0x7C00 +#define RTL8367C_CFG_P0_LED1_MUX_OFFSET 5 +#define RTL8367C_CFG_P0_LED1_MUX_MASK 0x3E0 +#define RTL8367C_CFG_P0_LED0_MUX_OFFSET 0 +#define RTL8367C_CFG_P0_LED0_MUX_MASK 0x1F + +#define RTL8367C_REG_P1_LED_MUX 0x1b2c +#define RTL8367C_CFG_P1_LED2_MUX_OFFSET 10 +#define RTL8367C_CFG_P1_LED2_MUX_MASK 0x7C00 +#define RTL8367C_CFG_P1_LED1_MUX_OFFSET 5 +#define RTL8367C_CFG_P1_LED1_MUX_MASK 0x3E0 +#define RTL8367C_CFG_P1_LED0_MUX_OFFSET 0 +#define RTL8367C_CFG_P1_LED0_MUX_MASK 0x1F + +#define RTL8367C_REG_P2_LED_MUX 0x1b2d +#define RTL8367C_CFG_P2_LED2_MUX_OFFSET 10 +#define RTL8367C_CFG_P2_LED2_MUX_MASK 0x7C00 +#define RTL8367C_CFG_P2_LED1_MUX_OFFSET 5 +#define RTL8367C_CFG_P2_LED1_MUX_MASK 0x3E0 +#define RTL8367C_CFG_P2_LED0_MUX_OFFSET 0 +#define RTL8367C_CFG_P2_LED0_MUX_MASK 0x1F + +#define RTL8367C_REG_P3_LED_MUX 0x1b2e +#define RTL8367C_CFG_P3_LED2_MUX_OFFSET 10 +#define RTL8367C_CFG_P3_LED2_MUX_MASK 0x7C00 +#define RTL8367C_CFG_P3_LED1_MUX_OFFSET 5 +#define RTL8367C_CFG_P3_LED1_MUX_MASK 0x3E0 +#define RTL8367C_CFG_P3_LED0_MUX_OFFSET 0 +#define RTL8367C_CFG_P3_LED0_MUX_MASK 0x1F + +#define RTL8367C_REG_P4_LED_MUX 0x1b2f +#define RTL8367C_CFG_P4_LED2_MUX_OFFSET 10 +#define RTL8367C_CFG_P4_LED2_MUX_MASK 0x7C00 +#define RTL8367C_CFG_P4_LED1_MUX_OFFSET 5 +#define RTL8367C_CFG_P4_LED1_MUX_MASK 0x3E0 +#define RTL8367C_CFG_P4_LED0_MUX_OFFSET 0 +#define RTL8367C_CFG_P4_LED0_MUX_MASK 0x1F + +#define RTL8367C_REG_LED0_DATA_CTRL 0x1b30 +#define RTL8367C_CFG_DATA_LED0_SEL_OFFSET 6 +#define RTL8367C_CFG_DATA_LED0_SEL_MASK 0x40 +#define RTL8367C_CFG_DATA_LED0_ACT_OFFSET 4 +#define RTL8367C_CFG_DATA_LED0_ACT_MASK 0x30 +#define RTL8367C_CFG_DATA_LED0_SPD_OFFSET 0 +#define RTL8367C_CFG_DATA_LED0_SPD_MASK 0xF + +#define RTL8367C_REG_LED1_DATA_CTRL 0x1b31 +#define RTL8367C_CFG_DATA_LED1_SEL_OFFSET 6 +#define RTL8367C_CFG_DATA_LED1_SEL_MASK 0x40 +#define RTL8367C_CFG_DATA_LED1_ACT_OFFSET 4 +#define RTL8367C_CFG_DATA_LED1_ACT_MASK 0x30 +#define RTL8367C_CFG_DATA_LED1_SPD_OFFSET 0 +#define RTL8367C_CFG_DATA_LED1_SPD_MASK 0xF + +#define RTL8367C_REG_LED2_DATA_CTRL 0x1b32 +#define RTL8367C_CFG_DATA_LED2_SEL_OFFSET 6 +#define RTL8367C_CFG_DATA_LED2_SEL_MASK 0x40 +#define RTL8367C_CFG_DATA_LED2_ACT_OFFSET 4 +#define RTL8367C_CFG_DATA_LED2_ACT_MASK 0x30 +#define RTL8367C_CFG_DATA_LED2_SPD_OFFSET 0 +#define RTL8367C_CFG_DATA_LED2_SPD_MASK 0xF + +#define RTL8367C_REG_PARA_LED_IO_EN3 0x1b33 +#define RTL8367C_dummy_1b33a_OFFSET 6 +#define RTL8367C_dummy_1b33a_MASK 0xFFC0 +#define RTL8367C_LED2_PARA_P09_08_OFFSET 4 +#define RTL8367C_LED2_PARA_P09_08_MASK 0x30 +#define RTL8367C_LED1_PARA_P09_08_OFFSET 2 +#define RTL8367C_LED1_PARA_P09_08_MASK 0xC +#define RTL8367C_LED0_PARA_P09_08_OFFSET 0 +#define RTL8367C_LED0_PARA_P09_08_MASK 0x3 + +#define RTL8367C_REG_SCAN1_LED_IO_EN3 0x1b34 +#define RTL8367C_dummy_1b34a_OFFSET 3 +#define RTL8367C_dummy_1b34a_MASK 0xFFF8 +#define RTL8367C_LED_SCAN1_BI_PORT9_8_EN_OFFSET 1 +#define RTL8367C_LED_SCAN1_BI_PORT9_8_EN_MASK 0x6 +#define RTL8367C_LED_SCAN1_SI_PORT9_8_EN_OFFSET 0 +#define RTL8367C_LED_SCAN1_SI_PORT9_8_EN_MASK 0x1 + +#define RTL8367C_REG_P5_LED_MUX 0x1b35 +#define RTL8367C_CFG_P5_LED2_MUX_OFFSET 10 +#define RTL8367C_CFG_P5_LED2_MUX_MASK 0x7C00 +#define RTL8367C_CFG_P5_LED1_MUX_OFFSET 5 +#define RTL8367C_CFG_P5_LED1_MUX_MASK 0x3E0 +#define RTL8367C_CFG_P5_LED0_MUX_OFFSET 0 +#define RTL8367C_CFG_P5_LED0_MUX_MASK 0x1F + +#define RTL8367C_REG_P6_LED_MUX 0x1b36 +#define RTL8367C_CFG_P6_LED2_MUX_OFFSET 10 +#define RTL8367C_CFG_P6_LED2_MUX_MASK 0x7C00 +#define RTL8367C_CFG_P6_LED1_MUX_OFFSET 5 +#define RTL8367C_CFG_P6_LED1_MUX_MASK 0x3E0 +#define RTL8367C_CFG_P6_LED0_MUX_OFFSET 0 +#define RTL8367C_CFG_P6_LED0_MUX_MASK 0x1F + +#define RTL8367C_REG_P7_LED_MUX 0x1b37 +#define RTL8367C_CFG_P7_LED2_MUX_OFFSET 10 +#define RTL8367C_CFG_P7_LED2_MUX_MASK 0x7C00 +#define RTL8367C_CFG_P7_LED1_MUX_OFFSET 5 +#define RTL8367C_CFG_P7_LED1_MUX_MASK 0x3E0 +#define RTL8367C_CFG_P7_LED0_MUX_OFFSET 0 +#define RTL8367C_CFG_P7_LED0_MUX_MASK 0x1F + +#define RTL8367C_REG_P8_LED_MUX 0x1b38 +#define RTL8367C_CFG_P8_LED2_MUX_OFFSET 10 +#define RTL8367C_CFG_P8_LED2_MUX_MASK 0x7C00 +#define RTL8367C_CFG_P8_LED1_MUX_OFFSET 5 +#define RTL8367C_CFG_P8_LED1_MUX_MASK 0x3E0 +#define RTL8367C_CFG_P8_LED0_MUX_OFFSET 0 +#define RTL8367C_CFG_P8_LED0_MUX_MASK 0x1F + +#define RTL8367C_REG_P9_LED_MUX 0x1b39 +#define RTL8367C_CFG_P9_LED2_MUX_OFFSET 10 +#define RTL8367C_CFG_P9_LED2_MUX_MASK 0x7C00 +#define RTL8367C_CFG_P9_LED1_MUX_OFFSET 5 +#define RTL8367C_CFG_P9_LED1_MUX_MASK 0x3E0 +#define RTL8367C_CFG_P9_LED0_MUX_OFFSET 0 +#define RTL8367C_CFG_P9_LED0_MUX_MASK 0x1F + +#define RTL8367C_REG_SERIAL_LED_CTRL 0x1b3a +#define RTL8367C_SERIAL_LED_SHIFT_SEQUENCE_OFFSET 13 +#define RTL8367C_SERIAL_LED_SHIFT_SEQUENCE_MASK 0x6000 +#define RTL8367C_SERIAL_LED_SHIFT_SEQUENCE_EN_OFFSET 12 +#define RTL8367C_SERIAL_LED_SHIFT_SEQUENCE_EN_MASK 0x1000 +#define RTL8367C_SERIAL_LED_GROUP_NUM_OFFSET 10 +#define RTL8367C_SERIAL_LED_GROUP_NUM_MASK 0xC00 +#define RTL8367C_SERIAL_LED_PORT_EN_OFFSET 0 +#define RTL8367C_SERIAL_LED_PORT_EN_MASK 0x3FF + +/* (16'h1c00)IGMP_EAV */ + +#define RTL8367C_REG_IGMP_MLD_CFG0 0x1c00 +#define RTL8367C_IGMP_MLD_PORTISO_LEAKY_OFFSET 15 +#define RTL8367C_IGMP_MLD_PORTISO_LEAKY_MASK 0x8000 +#define RTL8367C_IGMP_MLD_VLAN_LEAKY_OFFSET 14 +#define RTL8367C_IGMP_MLD_VLAN_LEAKY_MASK 0x4000 +#define RTL8367C_IGMP_MLD_DISCARD_STORM_FILTER_OFFSET 13 +#define RTL8367C_IGMP_MLD_DISCARD_STORM_FILTER_MASK 0x2000 +#define RTL8367C_REPORT_FORWARD_OFFSET 12 +#define RTL8367C_REPORT_FORWARD_MASK 0x1000 +#define RTL8367C_ROBURSTNESS_VAR_OFFSET 9 +#define RTL8367C_ROBURSTNESS_VAR_MASK 0xE00 +#define RTL8367C_LEAVE_SUPPRESSION_OFFSET 8 +#define RTL8367C_LEAVE_SUPPRESSION_MASK 0x100 +#define RTL8367C_REPORT_SUPPRESSION_OFFSET 7 +#define RTL8367C_REPORT_SUPPRESSION_MASK 0x80 +#define RTL8367C_LEAVE_TIMER_OFFSET 4 +#define RTL8367C_LEAVE_TIMER_MASK 0x70 +#define RTL8367C_FAST_LEAVE_EN_OFFSET 3 +#define RTL8367C_FAST_LEAVE_EN_MASK 0x8 +#define RTL8367C_CKS_ERR_OP_OFFSET 1 +#define RTL8367C_CKS_ERR_OP_MASK 0x6 +#define RTL8367C_IGMP_MLD_EN_OFFSET 0 +#define RTL8367C_IGMP_MLD_EN_MASK 0x1 + +#define RTL8367C_REG_IGMP_MLD_CFG1 0x1c01 +#define RTL8367C_DROP_LEAVE_ZERO_OFFSET 2 +#define RTL8367C_DROP_LEAVE_ZERO_MASK 0x4 +#define RTL8367C_TABLE_FULL_OP_OFFSET 0 +#define RTL8367C_TABLE_FULL_OP_MASK 0x3 + +#define RTL8367C_REG_IGMP_MLD_CFG2 0x1c02 + +#define RTL8367C_REG_IGMP_DYNAMIC_ROUTER_PORT 0x1c03 +#define RTL8367C_D_ROUTER_PORT_2_OFFSET 11 +#define RTL8367C_D_ROUTER_PORT_2_MASK 0x7800 +#define RTL8367C_D_ROUTER_PORT_TMR_2_OFFSET 8 +#define RTL8367C_D_ROUTER_PORT_TMR_2_MASK 0x700 +#define RTL8367C_D_ROUTER_PORT_1_OFFSET 3 +#define RTL8367C_D_ROUTER_PORT_1_MASK 0x78 +#define RTL8367C_D_ROUTER_PORT_TMR_1_OFFSET 0 +#define RTL8367C_D_ROUTER_PORT_TMR_1_MASK 0x7 + +#define RTL8367C_REG_IGMP_STATIC_ROUTER_PORT 0x1c04 +#define RTL8367C_IGMP_STATIC_ROUTER_PORT_OFFSET 0 +#define RTL8367C_IGMP_STATIC_ROUTER_PORT_MASK 0x7FF + +#define RTL8367C_REG_IGMP_PORT0_CONTROL 0x1c05 +#define RTL8367C_IGMP_PORT0_CONTROL_ALLOW_QUERY_OFFSET 14 +#define RTL8367C_IGMP_PORT0_CONTROL_ALLOW_QUERY_MASK 0x4000 +#define RTL8367C_IGMP_PORT0_CONTROL_ALLOW_REPORT_OFFSET 13 +#define RTL8367C_IGMP_PORT0_CONTROL_ALLOW_REPORT_MASK 0x2000 +#define RTL8367C_IGMP_PORT0_CONTROL_ALLOW_LEAVE_OFFSET 12 +#define RTL8367C_IGMP_PORT0_CONTROL_ALLOW_LEAVE_MASK 0x1000 +#define RTL8367C_IGMP_PORT0_CONTROL_ALLOW_MRP_OFFSET 11 +#define RTL8367C_IGMP_PORT0_CONTROL_ALLOW_MRP_MASK 0x800 +#define RTL8367C_IGMP_PORT0_CONTROL_ALLOW_MC_DATA_OFFSET 10 +#define RTL8367C_IGMP_PORT0_CONTROL_ALLOW_MC_DATA_MASK 0x400 +#define RTL8367C_IGMP_PORT0_CONTROL_MLDv2_OP_OFFSET 8 +#define RTL8367C_IGMP_PORT0_CONTROL_MLDv2_OP_MASK 0x300 +#define RTL8367C_IGMP_PORT0_CONTROL_MLDv1_OP_OFFSET 6 +#define RTL8367C_IGMP_PORT0_CONTROL_MLDv1_OP_MASK 0xC0 +#define RTL8367C_IGMP_PORT0_CONTROL_IGMPV3_OP_OFFSET 4 +#define RTL8367C_IGMP_PORT0_CONTROL_IGMPV3_OP_MASK 0x30 +#define RTL8367C_IGMP_PORT0_CONTROL_IGMPV2_OP_OFFSET 2 +#define RTL8367C_IGMP_PORT0_CONTROL_IGMPV2_OP_MASK 0xC +#define RTL8367C_IGMP_PORT0_CONTROL_IGMPV1_OP_OFFSET 0 +#define RTL8367C_IGMP_PORT0_CONTROL_IGMPV1_OP_MASK 0x3 + +#define RTL8367C_REG_IGMP_PORT1_CONTROL 0x1c06 +#define RTL8367C_IGMP_PORT1_CONTROL_ALLOW_QUERY_OFFSET 14 +#define RTL8367C_IGMP_PORT1_CONTROL_ALLOW_QUERY_MASK 0x4000 +#define RTL8367C_IGMP_PORT1_CONTROL_ALLOW_REPORT_OFFSET 13 +#define RTL8367C_IGMP_PORT1_CONTROL_ALLOW_REPORT_MASK 0x2000 +#define RTL8367C_IGMP_PORT1_CONTROL_ALLOW_LEAVE_OFFSET 12 +#define RTL8367C_IGMP_PORT1_CONTROL_ALLOW_LEAVE_MASK 0x1000 +#define RTL8367C_IGMP_PORT1_CONTROL_ALLOW_MRP_OFFSET 11 +#define RTL8367C_IGMP_PORT1_CONTROL_ALLOW_MRP_MASK 0x800 +#define RTL8367C_IGMP_PORT1_CONTROL_ALLOW_MC_DATA_OFFSET 10 +#define RTL8367C_IGMP_PORT1_CONTROL_ALLOW_MC_DATA_MASK 0x400 +#define RTL8367C_IGMP_PORT1_CONTROL_MLDv2_OP_OFFSET 8 +#define RTL8367C_IGMP_PORT1_CONTROL_MLDv2_OP_MASK 0x300 +#define RTL8367C_IGMP_PORT1_CONTROL_MLDv1_OP_OFFSET 6 +#define RTL8367C_IGMP_PORT1_CONTROL_MLDv1_OP_MASK 0xC0 +#define RTL8367C_IGMP_PORT1_CONTROL_IGMPV3_OP_OFFSET 4 +#define RTL8367C_IGMP_PORT1_CONTROL_IGMPV3_OP_MASK 0x30 +#define RTL8367C_IGMP_PORT1_CONTROL_IGMPV2_OP_OFFSET 2 +#define RTL8367C_IGMP_PORT1_CONTROL_IGMPV2_OP_MASK 0xC +#define RTL8367C_IGMP_PORT1_CONTROL_IGMPV1_OP_OFFSET 0 +#define RTL8367C_IGMP_PORT1_CONTROL_IGMPV1_OP_MASK 0x3 + +#define RTL8367C_REG_IGMP_PORT2_CONTROL 0x1c07 +#define RTL8367C_IGMP_PORT2_CONTROL_ALLOW_QUERY_OFFSET 14 +#define RTL8367C_IGMP_PORT2_CONTROL_ALLOW_QUERY_MASK 0x4000 +#define RTL8367C_IGMP_PORT2_CONTROL_ALLOW_REPORT_OFFSET 13 +#define RTL8367C_IGMP_PORT2_CONTROL_ALLOW_REPORT_MASK 0x2000 +#define RTL8367C_IGMP_PORT2_CONTROL_ALLOW_LEAVE_OFFSET 12 +#define RTL8367C_IGMP_PORT2_CONTROL_ALLOW_LEAVE_MASK 0x1000 +#define RTL8367C_IGMP_PORT2_CONTROL_ALLOW_MRP_OFFSET 11 +#define RTL8367C_IGMP_PORT2_CONTROL_ALLOW_MRP_MASK 0x800 +#define RTL8367C_IGMP_PORT2_CONTROL_ALLOW_MC_DATA_OFFSET 10 +#define RTL8367C_IGMP_PORT2_CONTROL_ALLOW_MC_DATA_MASK 0x400 +#define RTL8367C_IGMP_PORT2_CONTROL_MLDv2_OP_OFFSET 8 +#define RTL8367C_IGMP_PORT2_CONTROL_MLDv2_OP_MASK 0x300 +#define RTL8367C_IGMP_PORT2_CONTROL_MLDv1_OP_OFFSET 6 +#define RTL8367C_IGMP_PORT2_CONTROL_MLDv1_OP_MASK 0xC0 +#define RTL8367C_IGMP_PORT2_CONTROL_IGMPV3_OP_OFFSET 4 +#define RTL8367C_IGMP_PORT2_CONTROL_IGMPV3_OP_MASK 0x30 +#define RTL8367C_IGMP_PORT2_CONTROL_IGMPV2_OP_OFFSET 2 +#define RTL8367C_IGMP_PORT2_CONTROL_IGMPV2_OP_MASK 0xC +#define RTL8367C_IGMP_PORT2_CONTROL_IGMPV1_OP_OFFSET 0 +#define RTL8367C_IGMP_PORT2_CONTROL_IGMPV1_OP_MASK 0x3 + +#define RTL8367C_REG_IGMP_PORT3_CONTROL 0x1c08 +#define RTL8367C_IGMP_PORT3_CONTROL_ALLOW_QUERY_OFFSET 14 +#define RTL8367C_IGMP_PORT3_CONTROL_ALLOW_QUERY_MASK 0x4000 +#define RTL8367C_IGMP_PORT3_CONTROL_ALLOW_REPORT_OFFSET 13 +#define RTL8367C_IGMP_PORT3_CONTROL_ALLOW_REPORT_MASK 0x2000 +#define RTL8367C_IGMP_PORT3_CONTROL_ALLOW_LEAVE_OFFSET 12 +#define RTL8367C_IGMP_PORT3_CONTROL_ALLOW_LEAVE_MASK 0x1000 +#define RTL8367C_IGMP_PORT3_CONTROL_ALLOW_MRP_OFFSET 11 +#define RTL8367C_IGMP_PORT3_CONTROL_ALLOW_MRP_MASK 0x800 +#define RTL8367C_IGMP_PORT3_CONTROL_ALLOW_MC_DATA_OFFSET 10 +#define RTL8367C_IGMP_PORT3_CONTROL_ALLOW_MC_DATA_MASK 0x400 +#define RTL8367C_IGMP_PORT3_CONTROL_MLDv2_OP_OFFSET 8 +#define RTL8367C_IGMP_PORT3_CONTROL_MLDv2_OP_MASK 0x300 +#define RTL8367C_IGMP_PORT3_CONTROL_MLDv1_OP_OFFSET 6 +#define RTL8367C_IGMP_PORT3_CONTROL_MLDv1_OP_MASK 0xC0 +#define RTL8367C_IGMP_PORT3_CONTROL_IGMPV3_OP_OFFSET 4 +#define RTL8367C_IGMP_PORT3_CONTROL_IGMPV3_OP_MASK 0x30 +#define RTL8367C_IGMP_PORT3_CONTROL_IGMPV2_OP_OFFSET 2 +#define RTL8367C_IGMP_PORT3_CONTROL_IGMPV2_OP_MASK 0xC +#define RTL8367C_IGMP_PORT3_CONTROL_IGMPV1_OP_OFFSET 0 +#define RTL8367C_IGMP_PORT3_CONTROL_IGMPV1_OP_MASK 0x3 + +#define RTL8367C_REG_IGMP_PORT4_CONTROL 0x1c09 +#define RTL8367C_IGMP_PORT4_CONTROL_ALLOW_QUERY_OFFSET 14 +#define RTL8367C_IGMP_PORT4_CONTROL_ALLOW_QUERY_MASK 0x4000 +#define RTL8367C_IGMP_PORT4_CONTROL_ALLOW_REPORT_OFFSET 13 +#define RTL8367C_IGMP_PORT4_CONTROL_ALLOW_REPORT_MASK 0x2000 +#define RTL8367C_IGMP_PORT4_CONTROL_ALLOW_LEAVE_OFFSET 12 +#define RTL8367C_IGMP_PORT4_CONTROL_ALLOW_LEAVE_MASK 0x1000 +#define RTL8367C_IGMP_PORT4_CONTROL_ALLOW_MRP_OFFSET 11 +#define RTL8367C_IGMP_PORT4_CONTROL_ALLOW_MRP_MASK 0x800 +#define RTL8367C_IGMP_PORT4_CONTROL_ALLOW_MC_DATA_OFFSET 10 +#define RTL8367C_IGMP_PORT4_CONTROL_ALLOW_MC_DATA_MASK 0x400 +#define RTL8367C_IGMP_PORT4_CONTROL_MLDv2_OP_OFFSET 8 +#define RTL8367C_IGMP_PORT4_CONTROL_MLDv2_OP_MASK 0x300 +#define RTL8367C_IGMP_PORT4_CONTROL_MLDv1_OP_OFFSET 6 +#define RTL8367C_IGMP_PORT4_CONTROL_MLDv1_OP_MASK 0xC0 +#define RTL8367C_IGMP_PORT4_CONTROL_IGMPV3_OP_OFFSET 4 +#define RTL8367C_IGMP_PORT4_CONTROL_IGMPV3_OP_MASK 0x30 +#define RTL8367C_IGMP_PORT4_CONTROL_IGMPV2_OP_OFFSET 2 +#define RTL8367C_IGMP_PORT4_CONTROL_IGMPV2_OP_MASK 0xC +#define RTL8367C_IGMP_PORT4_CONTROL_IGMPV1_OP_OFFSET 0 +#define RTL8367C_IGMP_PORT4_CONTROL_IGMPV1_OP_MASK 0x3 + +#define RTL8367C_REG_IGMP_PORT5_CONTROL 0x1c0a +#define RTL8367C_IGMP_PORT5_CONTROL_ALLOW_QUERY_OFFSET 14 +#define RTL8367C_IGMP_PORT5_CONTROL_ALLOW_QUERY_MASK 0x4000 +#define RTL8367C_IGMP_PORT5_CONTROL_ALLOW_REPORT_OFFSET 13 +#define RTL8367C_IGMP_PORT5_CONTROL_ALLOW_REPORT_MASK 0x2000 +#define RTL8367C_IGMP_PORT5_CONTROL_ALLOW_LEAVE_OFFSET 12 +#define RTL8367C_IGMP_PORT5_CONTROL_ALLOW_LEAVE_MASK 0x1000 +#define RTL8367C_IGMP_PORT5_CONTROL_ALLOW_MRP_OFFSET 11 +#define RTL8367C_IGMP_PORT5_CONTROL_ALLOW_MRP_MASK 0x800 +#define RTL8367C_IGMP_PORT5_CONTROL_ALLOW_MC_DATA_OFFSET 10 +#define RTL8367C_IGMP_PORT5_CONTROL_ALLOW_MC_DATA_MASK 0x400 +#define RTL8367C_IGMP_PORT5_CONTROL_MLDv2_OP_OFFSET 8 +#define RTL8367C_IGMP_PORT5_CONTROL_MLDv2_OP_MASK 0x300 +#define RTL8367C_IGMP_PORT5_CONTROL_MLDv1_OP_OFFSET 6 +#define RTL8367C_IGMP_PORT5_CONTROL_MLDv1_OP_MASK 0xC0 +#define RTL8367C_IGMP_PORT5_CONTROL_IGMPV3_OP_OFFSET 4 +#define RTL8367C_IGMP_PORT5_CONTROL_IGMPV3_OP_MASK 0x30 +#define RTL8367C_IGMP_PORT5_CONTROL_IGMPV2_OP_OFFSET 2 +#define RTL8367C_IGMP_PORT5_CONTROL_IGMPV2_OP_MASK 0xC +#define RTL8367C_IGMP_PORT5_CONTROL_IGMPV1_OP_OFFSET 0 +#define RTL8367C_IGMP_PORT5_CONTROL_IGMPV1_OP_MASK 0x3 + +#define RTL8367C_REG_IGMP_PORT6_CONTROL 0x1c0b +#define RTL8367C_IGMP_PORT6_CONTROL_ALLOW_QUERY_OFFSET 14 +#define RTL8367C_IGMP_PORT6_CONTROL_ALLOW_QUERY_MASK 0x4000 +#define RTL8367C_IGMP_PORT6_CONTROL_ALLOW_REPORT_OFFSET 13 +#define RTL8367C_IGMP_PORT6_CONTROL_ALLOW_REPORT_MASK 0x2000 +#define RTL8367C_IGMP_PORT6_CONTROL_ALLOW_LEAVE_OFFSET 12 +#define RTL8367C_IGMP_PORT6_CONTROL_ALLOW_LEAVE_MASK 0x1000 +#define RTL8367C_IGMP_PORT6_CONTROL_ALLOW_MRP_OFFSET 11 +#define RTL8367C_IGMP_PORT6_CONTROL_ALLOW_MRP_MASK 0x800 +#define RTL8367C_IGMP_PORT6_CONTROL_ALLOW_MC_DATA_OFFSET 10 +#define RTL8367C_IGMP_PORT6_CONTROL_ALLOW_MC_DATA_MASK 0x400 +#define RTL8367C_IGMP_PORT6_CONTROL_MLDv2_OP_OFFSET 8 +#define RTL8367C_IGMP_PORT6_CONTROL_MLDv2_OP_MASK 0x300 +#define RTL8367C_IGMP_PORT6_CONTROL_MLDv1_OP_OFFSET 6 +#define RTL8367C_IGMP_PORT6_CONTROL_MLDv1_OP_MASK 0xC0 +#define RTL8367C_IGMP_PORT6_CONTROL_IGMPV3_OP_OFFSET 4 +#define RTL8367C_IGMP_PORT6_CONTROL_IGMPV3_OP_MASK 0x30 +#define RTL8367C_IGMP_PORT6_CONTROL_IGMPV2_OP_OFFSET 2 +#define RTL8367C_IGMP_PORT6_CONTROL_IGMPV2_OP_MASK 0xC +#define RTL8367C_IGMP_PORT6_CONTROL_IGMPV1_OP_OFFSET 0 +#define RTL8367C_IGMP_PORT6_CONTROL_IGMPV1_OP_MASK 0x3 + +#define RTL8367C_REG_IGMP_PORT7_CONTROL 0x1c0c +#define RTL8367C_IGMP_PORT7_CONTROL_ALLOW_QUERY_OFFSET 14 +#define RTL8367C_IGMP_PORT7_CONTROL_ALLOW_QUERY_MASK 0x4000 +#define RTL8367C_IGMP_PORT7_CONTROL_ALLOW_REPORT_OFFSET 13 +#define RTL8367C_IGMP_PORT7_CONTROL_ALLOW_REPORT_MASK 0x2000 +#define RTL8367C_IGMP_PORT7_CONTROL_ALLOW_LEAVE_OFFSET 12 +#define RTL8367C_IGMP_PORT7_CONTROL_ALLOW_LEAVE_MASK 0x1000 +#define RTL8367C_IGMP_PORT7_CONTROL_ALLOW_MRP_OFFSET 11 +#define RTL8367C_IGMP_PORT7_CONTROL_ALLOW_MRP_MASK 0x800 +#define RTL8367C_IGMP_PORT7_CONTROL_ALLOW_MC_DATA_OFFSET 10 +#define RTL8367C_IGMP_PORT7_CONTROL_ALLOW_MC_DATA_MASK 0x400 +#define RTL8367C_IGMP_PORT7_CONTROL_MLDv2_OP_OFFSET 8 +#define RTL8367C_IGMP_PORT7_CONTROL_MLDv2_OP_MASK 0x300 +#define RTL8367C_IGMP_PORT7_CONTROL_MLDv1_OP_OFFSET 6 +#define RTL8367C_IGMP_PORT7_CONTROL_MLDv1_OP_MASK 0xC0 +#define RTL8367C_IGMP_PORT7_CONTROL_IGMPV3_OP_OFFSET 4 +#define RTL8367C_IGMP_PORT7_CONTROL_IGMPV3_OP_MASK 0x30 +#define RTL8367C_IGMP_PORT7_CONTROL_IGMPV2_OP_OFFSET 2 +#define RTL8367C_IGMP_PORT7_CONTROL_IGMPV2_OP_MASK 0xC +#define RTL8367C_IGMP_PORT7_CONTROL_IGMPV1_OP_OFFSET 0 +#define RTL8367C_IGMP_PORT7_CONTROL_IGMPV1_OP_MASK 0x3 + +#define RTL8367C_REG_IGMP_PORT01_MAX_GROUP 0x1c0d +#define RTL8367C_PORT1_MAX_GROUP_OFFSET 8 +#define RTL8367C_PORT1_MAX_GROUP_MASK 0xFF00 +#define RTL8367C_PORT0_MAX_GROUP_OFFSET 0 +#define RTL8367C_PORT0_MAX_GROUP_MASK 0xFF + +#define RTL8367C_REG_IGMP_PORT23_MAX_GROUP 0x1c0e +#define RTL8367C_PORT3_MAX_GROUP_OFFSET 8 +#define RTL8367C_PORT3_MAX_GROUP_MASK 0xFF00 +#define RTL8367C_PORT2_MAX_GROUP_OFFSET 0 +#define RTL8367C_PORT2_MAX_GROUP_MASK 0xFF + +#define RTL8367C_REG_IGMP_PORT45_MAX_GROUP 0x1c0f +#define RTL8367C_PORT5_MAX_GROUP_OFFSET 8 +#define RTL8367C_PORT5_MAX_GROUP_MASK 0xFF00 +#define RTL8367C_PORT4_MAX_GROUP_OFFSET 0 +#define RTL8367C_PORT4_MAX_GROUP_MASK 0xFF + +#define RTL8367C_REG_IGMP_PORT67_MAX_GROUP 0x1c10 +#define RTL8367C_PORT7_MAX_GROUP_OFFSET 8 +#define RTL8367C_PORT7_MAX_GROUP_MASK 0xFF00 +#define RTL8367C_PORT6_MAX_GROUP_OFFSET 0 +#define RTL8367C_PORT6_MAX_GROUP_MASK 0xFF + +#define RTL8367C_REG_IGMP_PORT01_CURRENT_GROUP 0x1c11 +#define RTL8367C_PORT1_CURRENT_GROUP_OFFSET 8 +#define RTL8367C_PORT1_CURRENT_GROUP_MASK 0xFF00 +#define RTL8367C_PORT0_CURRENT_GROUP_OFFSET 0 +#define RTL8367C_PORT0_CURRENT_GROUP_MASK 0xFF + +#define RTL8367C_REG_IGMP_PORT23_CURRENT_GROUP 0x1c12 +#define RTL8367C_PORT3_CURRENT_GROUP_OFFSET 8 +#define RTL8367C_PORT3_CURRENT_GROUP_MASK 0xFF00 +#define RTL8367C_PORT2_CURRENT_GROUP_OFFSET 0 +#define RTL8367C_PORT2_CURRENT_GROUP_MASK 0xFF + +#define RTL8367C_REG_IGMP_PORT45_CURRENT_GROUP 0x1c13 +#define RTL8367C_PORT5_CURRENT_GROUP_OFFSET 8 +#define RTL8367C_PORT5_CURRENT_GROUP_MASK 0xFF00 +#define RTL8367C_PORT4_CURRENT_GROUP_OFFSET 0 +#define RTL8367C_PORT4_CURRENT_GROUP_MASK 0xFF + +#define RTL8367C_REG_IGMP_PORT67_CURRENT_GROUP 0x1c14 +#define RTL8367C_PORT7_CURRENT_GROUP_OFFSET 8 +#define RTL8367C_PORT7_CURRENT_GROUP_MASK 0xFF00 +#define RTL8367C_PORT6_CURRENT_GROUP_OFFSET 0 +#define RTL8367C_PORT6_CURRENT_GROUP_MASK 0xFF + +#define RTL8367C_REG_IGMP_MLD_CFG3 0x1c15 +#define RTL8367C_IGMP_MLD_IP6_BYPASS_OFFSET 5 +#define RTL8367C_IGMP_MLD_IP6_BYPASS_MASK 0x20 +#define RTL8367C_IGMP_MLD_IP4_BYPASS_239_255_255_OFFSET 4 +#define RTL8367C_IGMP_MLD_IP4_BYPASS_239_255_255_MASK 0x10 +#define RTL8367C_IGMP_MLD_IP4_BYPASS_224_0_1_OFFSET 3 +#define RTL8367C_IGMP_MLD_IP4_BYPASS_224_0_1_MASK 0x8 +#define RTL8367C_IGMP_MLD_IP4_BYPASS_224_0_0_OFFSET 2 +#define RTL8367C_IGMP_MLD_IP4_BYPASS_224_0_0_MASK 0x4 +#define RTL8367C_REPORT_LEAVE_FORWARD_OFFSET 0 +#define RTL8367C_REPORT_LEAVE_FORWARD_MASK 0x3 + +#define RTL8367C_REG_IGMP_MLD_CFG4 0x1c16 +#define RTL8367C_IGMP_MLD_CFG4_OFFSET 0 +#define RTL8367C_IGMP_MLD_CFG4_MASK 0x7FF + +#define RTL8367C_REG_IGMP_GROUP_USAGE_LIST0 0x1c20 + +#define RTL8367C_REG_IGMP_GROUP_USAGE_LIST1 0x1c21 + +#define RTL8367C_REG_IGMP_GROUP_USAGE_LIST2 0x1c22 + +#define RTL8367C_REG_IGMP_GROUP_USAGE_LIST3 0x1c23 + +#define RTL8367C_REG_IGMP_GROUP_USAGE_LIST4 0x1c24 + +#define RTL8367C_REG_IGMP_GROUP_USAGE_LIST5 0x1c25 + +#define RTL8367C_REG_IGMP_GROUP_USAGE_LIST6 0x1c26 + +#define RTL8367C_REG_IGMP_GROUP_USAGE_LIST7 0x1c27 + +#define RTL8367C_REG_IGMP_GROUP_USAGE_LIST8 0x1c28 + +#define RTL8367C_REG_IGMP_GROUP_USAGE_LIST9 0x1c29 + +#define RTL8367C_REG_IGMP_GROUP_USAGE_LIST10 0x1c2a + +#define RTL8367C_REG_IGMP_GROUP_USAGE_LIST11 0x1c2b + +#define RTL8367C_REG_IGMP_GROUP_USAGE_LIST12 0x1c2c + +#define RTL8367C_REG_IGMP_GROUP_USAGE_LIST13 0x1c2d + +#define RTL8367C_REG_IGMP_GROUP_USAGE_LIST14 0x1c2e + +#define RTL8367C_REG_IGMP_GROUP_USAGE_LIST15 0x1c2f + +#define RTL8367C_REG_EAV_CTRL0 0x1c30 +#define RTL8367C_EAV_CTRL0_OFFSET 0 +#define RTL8367C_EAV_CTRL0_MASK 0xFF + +#define RTL8367C_REG_EAV_CTRL1 0x1c31 +#define RTL8367C_REMAP_EAV_PRI3_REGEN_OFFSET 9 +#define RTL8367C_REMAP_EAV_PRI3_REGEN_MASK 0xE00 +#define RTL8367C_REMAP_EAV_PRI2_REGEN_OFFSET 6 +#define RTL8367C_REMAP_EAV_PRI2_REGEN_MASK 0x1C0 +#define RTL8367C_REMAP_EAV_PRI1_REGEN_OFFSET 3 +#define RTL8367C_REMAP_EAV_PRI1_REGEN_MASK 0x38 +#define RTL8367C_REMAP_EAV_PRI0_REGEN_OFFSET 0 +#define RTL8367C_REMAP_EAV_PRI0_REGEN_MASK 0x7 + +#define RTL8367C_REG_EAV_CTRL2 0x1c32 +#define RTL8367C_REMAP_EAV_PRI7_REGEN_OFFSET 9 +#define RTL8367C_REMAP_EAV_PRI7_REGEN_MASK 0xE00 +#define RTL8367C_REMAP_EAV_PRI6_REGEN_OFFSET 6 +#define RTL8367C_REMAP_EAV_PRI6_REGEN_MASK 0x1C0 +#define RTL8367C_REMAP_EAV_PRI5_REGEN_OFFSET 3 +#define RTL8367C_REMAP_EAV_PRI5_REGEN_MASK 0x38 +#define RTL8367C_REMAP_EAV_PRI4_REGEN_OFFSET 0 +#define RTL8367C_REMAP_EAV_PRI4_REGEN_MASK 0x7 + +#define RTL8367C_REG_SYS_TIME_FREQ 0x1c43 + +#define RTL8367C_REG_SYS_TIME_OFFSET_L 0x1c44 + +#define RTL8367C_REG_SYS_TIME_OFFSET_H 0x1c45 + +#define RTL8367C_REG_SYS_TIME_OFFSET_512NS_L 0x1c46 + +#define RTL8367C_REG_SYS_TIME_OFFSET_512NS_H 0x1c47 +#define RTL8367C_SYS_TIME_OFFSET_TUNE_OFFSET 5 +#define RTL8367C_SYS_TIME_OFFSET_TUNE_MASK 0x20 +#define RTL8367C_SYS_TIME_OFFSET_512NS_H_SYS_TIME_OFFSET_512NS_OFFSET 0 +#define RTL8367C_SYS_TIME_OFFSET_512NS_H_SYS_TIME_OFFSET_512NS_MASK 0x1F + +#define RTL8367C_REG_SYS_TIME_SEC_TRANSIT 0x1c48 +#define RTL8367C_SYS_TIME_SEC_TRANSIT_OFFSET 0 +#define RTL8367C_SYS_TIME_SEC_TRANSIT_MASK 0x1 + +#define RTL8367C_REG_SYS_TIME_SEC_HIGH_L 0x1c49 + +#define RTL8367C_REG_SYS_TIME_SEC_HIGH_H 0x1c4a + +#define RTL8367C_REG_SYS_TIME_512NS_L 0x1c4b + +#define RTL8367C_REG_SYS_TIME_512NS_H 0x1c4c +#define RTL8367C_SYS_TIME_512NS_H_OFFSET 0 +#define RTL8367C_SYS_TIME_512NS_H_MASK 0x1F + +#define RTL8367C_REG_FALLBACK_CTRL 0x1c70 +#define RTL8367C_FALLBACK_PL_DEC_EN_OFFSET 15 +#define RTL8367C_FALLBACK_PL_DEC_EN_MASK 0x8000 +#define RTL8367C_FALLBACK_MONITOR_TIMEOUT_IGNORE_OFFSET 14 +#define RTL8367C_FALLBACK_MONITOR_TIMEOUT_IGNORE_MASK 0x4000 +#define RTL8367C_FALLBACK_ERROR_RATIO_THRESHOLD_OFFSET 11 +#define RTL8367C_FALLBACK_ERROR_RATIO_THRESHOLD_MASK 0x3800 +#define RTL8367C_FALLBACK_MONITORMAX_OFFSET 8 +#define RTL8367C_FALLBACK_MONITORMAX_MASK 0x700 +#define RTL8367C_FALLBACK_MONITOR_TIMEOUT_OFFSET 0 +#define RTL8367C_FALLBACK_MONITOR_TIMEOUT_MASK 0xFF + +#define RTL8367C_REG_FALLBACK_PORT0_CFG0 0x1c71 +#define RTL8367C_FALLBACK_PORT0_CFG0_RESET_POWER_LEVEL_OFFSET 15 +#define RTL8367C_FALLBACK_PORT0_CFG0_RESET_POWER_LEVEL_MASK 0x8000 +#define RTL8367C_FALLBACK_PORT0_CFG0_ENABLE_OFFSET 14 +#define RTL8367C_FALLBACK_PORT0_CFG0_ENABLE_MASK 0x4000 + +#define RTL8367C_REG_FALLBACK_PORT0_CFG1 0x1c72 + +#define RTL8367C_REG_FALLBACK_PORT0_CFG2 0x1c73 +#define RTL8367C_FALLBACK_PORT0_CFG2_OFFSET 0 +#define RTL8367C_FALLBACK_PORT0_CFG2_MASK 0xFFF + +#define RTL8367C_REG_FALLBACK_PORT0_CFG3 0x1c74 +#define RTL8367C_FALLBACK_PORT0_CFG3_OFFSET 0 +#define RTL8367C_FALLBACK_PORT0_CFG3_MASK 0xFF + +#define RTL8367C_REG_FALLBACK_PORT1_CFG0 0x1c75 +#define RTL8367C_FALLBACK_PORT1_CFG0_RESET_POWER_LEVEL_OFFSET 15 +#define RTL8367C_FALLBACK_PORT1_CFG0_RESET_POWER_LEVEL_MASK 0x8000 +#define RTL8367C_FALLBACK_PORT1_CFG0_ENABLE_OFFSET 14 +#define RTL8367C_FALLBACK_PORT1_CFG0_ENABLE_MASK 0x4000 + +#define RTL8367C_REG_FALLBACK_PORT1_CFG1 0x1c76 + +#define RTL8367C_REG_FALLBACK_PORT1_CFG2 0x1c77 +#define RTL8367C_FALLBACK_PORT1_CFG2_OFFSET 0 +#define RTL8367C_FALLBACK_PORT1_CFG2_MASK 0xFFF + +#define RTL8367C_REG_FALLBACK_PORT1_CFG3 0x1c78 +#define RTL8367C_FALLBACK_PORT1_CFG3_OFFSET 0 +#define RTL8367C_FALLBACK_PORT1_CFG3_MASK 0xFF + +#define RTL8367C_REG_FALLBACK_PORT2_CFG0 0x1c79 +#define RTL8367C_FALLBACK_PORT2_CFG0_RESET_POWER_LEVEL_OFFSET 15 +#define RTL8367C_FALLBACK_PORT2_CFG0_RESET_POWER_LEVEL_MASK 0x8000 +#define RTL8367C_FALLBACK_PORT2_CFG0_ENABLE_OFFSET 14 +#define RTL8367C_FALLBACK_PORT2_CFG0_ENABLE_MASK 0x4000 + +#define RTL8367C_REG_FALLBACK_PORT2_CFG1 0x1c7a + +#define RTL8367C_REG_FALLBACK_PORT2_CFG2 0x1c7b +#define RTL8367C_FALLBACK_PORT2_CFG2_OFFSET 0 +#define RTL8367C_FALLBACK_PORT2_CFG2_MASK 0xFFF + +#define RTL8367C_REG_FALLBACK_PORT2_CFG3 0x1c7c +#define RTL8367C_FALLBACK_PORT2_CFG3_OFFSET 0 +#define RTL8367C_FALLBACK_PORT2_CFG3_MASK 0xFF + +#define RTL8367C_REG_FALLBACK_PORT3_CFG0 0x1c7d +#define RTL8367C_FALLBACK_PORT3_CFG0_RESET_POWER_LEVEL_OFFSET 15 +#define RTL8367C_FALLBACK_PORT3_CFG0_RESET_POWER_LEVEL_MASK 0x8000 +#define RTL8367C_FALLBACK_PORT3_CFG0_ENABLE_OFFSET 14 +#define RTL8367C_FALLBACK_PORT3_CFG0_ENABLE_MASK 0x4000 + +#define RTL8367C_REG_FALLBACK_PORT3_CFG1 0x1c7e + +#define RTL8367C_REG_FALLBACK_PORT3_CFG2 0x1c7f +#define RTL8367C_FALLBACK_PORT3_CFG2_OFFSET 0 +#define RTL8367C_FALLBACK_PORT3_CFG2_MASK 0xFFF + +#define RTL8367C_REG_FALLBACK_PORT3_CFG3 0x1c80 +#define RTL8367C_FALLBACK_PORT3_CFG3_OFFSET 0 +#define RTL8367C_FALLBACK_PORT3_CFG3_MASK 0xFF + +#define RTL8367C_REG_FALLBACK_PORT4_CFG0 0x1c81 +#define RTL8367C_FALLBACK_PORT4_CFG0_RESET_POWER_LEVEL_OFFSET 15 +#define RTL8367C_FALLBACK_PORT4_CFG0_RESET_POWER_LEVEL_MASK 0x8000 +#define RTL8367C_FALLBACK_PORT4_CFG0_ENABLE_OFFSET 14 +#define RTL8367C_FALLBACK_PORT4_CFG0_ENABLE_MASK 0x4000 + +#define RTL8367C_REG_FALLBACK_PORT4_CFG1 0x1c82 + +#define RTL8367C_REG_FALLBACK_PORT4_CFG2 0x1c83 +#define RTL8367C_FALLBACK_PORT4_CFG2_OFFSET 0 +#define RTL8367C_FALLBACK_PORT4_CFG2_MASK 0xFFF + +#define RTL8367C_REG_FALLBACK_PORT4_CFG3 0x1c84 +#define RTL8367C_FALLBACK_PORT4_CFG3_OFFSET 0 +#define RTL8367C_FALLBACK_PORT4_CFG3_MASK 0xFF + +#define RTL8367C_REG_FALLBACK_CTRL1 0x1c85 +#define RTL8367C_FALLBACK_VALIDFLOW_OFFSET 8 +#define RTL8367C_FALLBACK_VALIDFLOW_MASK 0xFF00 +#define RTL8367C_FALLBACK_STOP_TMR_OFFSET 0 +#define RTL8367C_FALLBACK_STOP_TMR_MASK 0x1 + +#define RTL8367C_REG_FALLBACK_CPL 0x1c86 +#define RTL8367C_PORT4_CPL_OFFSET 4 +#define RTL8367C_PORT4_CPL_MASK 0x10 +#define RTL8367C_PORT3_CPL_OFFSET 3 +#define RTL8367C_PORT3_CPL_MASK 0x8 +#define RTL8367C_PORT2_CPL_OFFSET 2 +#define RTL8367C_PORT2_CPL_MASK 0x4 +#define RTL8367C_PORT1_CPL_OFFSET 1 +#define RTL8367C_PORT1_CPL_MASK 0x2 +#define RTL8367C_PORT0_CPL_OFFSET 0 +#define RTL8367C_PORT0_CPL_MASK 0x1 + +#define RTL8367C_REG_FALLBACK_PHY_PAGE 0x1c87 +#define RTL8367C_FALLBACK_PHY_PAGE_OFFSET 0 +#define RTL8367C_FALLBACK_PHY_PAGE_MASK 0xFFF + +#define RTL8367C_REG_FALLBACK_PHY_REG 0x1c88 +#define RTL8367C_FALLBACK_PHY_REG_OFFSET 0 +#define RTL8367C_FALLBACK_PHY_REG_MASK 0x1F + +#define RTL8367C_REG_AFBK_INFO_X0 0x1c89 + +#define RTL8367C_REG_AFBK_INFO_X1 0x1c8a + +#define RTL8367C_REG_AFBK_INFO_X2 0x1c8b + +#define RTL8367C_REG_AFBK_INFO_X3 0x1c8c + +#define RTL8367C_REG_AFBK_INFO_X4 0x1c8d + +#define RTL8367C_REG_AFBK_INFO_X5 0x1c8e + +#define RTL8367C_REG_AFBK_INFO_X6 0x1c8f + +#define RTL8367C_REG_AFBK_INFO_X7 0x1c90 + +#define RTL8367C_REG_AFBK_INFO_X8 0x1c91 + +#define RTL8367C_REG_AFBK_INFO_X9 0x1c92 + +#define RTL8367C_REG_AFBK_INFO_X10 0x1c93 + +#define RTL8367C_REG_AFBK_INFO_X11 0x1c94 + +#define RTL8367C_REG_FALLBACK_PORT5_CFG0 0x1ca0 +#define RTL8367C_FALLBACK_PORT5_CFG0_RESET_POWER_LEVEL_OFFSET 15 +#define RTL8367C_FALLBACK_PORT5_CFG0_RESET_POWER_LEVEL_MASK 0x8000 +#define RTL8367C_FALLBACK_PORT5_CFG0_ENABLE_OFFSET 14 +#define RTL8367C_FALLBACK_PORT5_CFG0_ENABLE_MASK 0x4000 + +#define RTL8367C_REG_FALLBACK_PORT5_CFG1 0x1ca1 + +#define RTL8367C_REG_FALLBACK_PORT5_CFG2 0x1ca2 +#define RTL8367C_FALLBACK_PORT5_CFG2_OFFSET 0 +#define RTL8367C_FALLBACK_PORT5_CFG2_MASK 0xFFF + +#define RTL8367C_REG_FALLBACK_PORT5_CFG3 0x1ca3 +#define RTL8367C_FALLBACK_PORT5_CFG3_OFFSET 0 +#define RTL8367C_FALLBACK_PORT5_CFG3_MASK 0xFF + +#define RTL8367C_REG_FALLBACK_PORT6_CFG0 0x1ca4 +#define RTL8367C_FALLBACK_PORT6_CFG0_RESET_POWER_LEVEL_OFFSET 15 +#define RTL8367C_FALLBACK_PORT6_CFG0_RESET_POWER_LEVEL_MASK 0x8000 +#define RTL8367C_FALLBACK_PORT6_CFG0_ENABLE_OFFSET 14 +#define RTL8367C_FALLBACK_PORT6_CFG0_ENABLE_MASK 0x4000 + +#define RTL8367C_REG_FALLBACK_PORT6_CFG1 0x1ca5 + +#define RTL8367C_REG_FALLBACK_PORT6_CFG2 0x1ca6 +#define RTL8367C_FALLBACK_PORT6_CFG2_OFFSET 0 +#define RTL8367C_FALLBACK_PORT6_CFG2_MASK 0xFFF + +#define RTL8367C_REG_FALLBACK_PORT6_CFG3 0x1ca7 +#define RTL8367C_FALLBACK_PORT6_CFG3_OFFSET 0 +#define RTL8367C_FALLBACK_PORT6_CFG3_MASK 0xFF + +#define RTL8367C_REG_FALLBACK_PORT7_CFG0 0x1ca8 +#define RTL8367C_FALLBACK_PORT7_CFG0_RESET_POWER_LEVEL_OFFSET 15 +#define RTL8367C_FALLBACK_PORT7_CFG0_RESET_POWER_LEVEL_MASK 0x8000 +#define RTL8367C_FALLBACK_PORT7_CFG0_ENABLE_OFFSET 14 +#define RTL8367C_FALLBACK_PORT7_CFG0_ENABLE_MASK 0x4000 + +#define RTL8367C_REG_FALLBACK_PORT7_CFG1 0x1ca9 + +#define RTL8367C_REG_FALLBACK_PORT7_CFG2 0x1caa +#define RTL8367C_FALLBACK_PORT7_CFG2_OFFSET 0 +#define RTL8367C_FALLBACK_PORT7_CFG2_MASK 0xFFF + +#define RTL8367C_REG_FALLBACK_PORT7_CFG3 0x1cab +#define RTL8367C_FALLBACK_PORT7_CFG3_OFFSET 0 +#define RTL8367C_FALLBACK_PORT7_CFG3_MASK 0xFF + +#define RTL8367C_REG_IGMP_PORT8_CONTROL 0x1cb0 +#define RTL8367C_IGMP_PORT8_CONTROL_ALLOW_QUERY_OFFSET 14 +#define RTL8367C_IGMP_PORT8_CONTROL_ALLOW_QUERY_MASK 0x4000 +#define RTL8367C_IGMP_PORT8_CONTROL_ALLOW_REPORT_OFFSET 13 +#define RTL8367C_IGMP_PORT8_CONTROL_ALLOW_REPORT_MASK 0x2000 +#define RTL8367C_IGMP_PORT8_CONTROL_ALLOW_LEAVE_OFFSET 12 +#define RTL8367C_IGMP_PORT8_CONTROL_ALLOW_LEAVE_MASK 0x1000 +#define RTL8367C_IGMP_PORT8_CONTROL_ALLOW_MRP_OFFSET 11 +#define RTL8367C_IGMP_PORT8_CONTROL_ALLOW_MRP_MASK 0x800 +#define RTL8367C_IGMP_PORT8_CONTROL_ALLOW_MC_DATA_OFFSET 10 +#define RTL8367C_IGMP_PORT8_CONTROL_ALLOW_MC_DATA_MASK 0x400 +#define RTL8367C_IGMP_PORT8_CONTROL_MLDv2_OP_OFFSET 8 +#define RTL8367C_IGMP_PORT8_CONTROL_MLDv2_OP_MASK 0x300 +#define RTL8367C_IGMP_PORT8_CONTROL_MLDv1_OP_OFFSET 6 +#define RTL8367C_IGMP_PORT8_CONTROL_MLDv1_OP_MASK 0xC0 +#define RTL8367C_IGMP_PORT8_CONTROL_IGMPV3_OP_OFFSET 4 +#define RTL8367C_IGMP_PORT8_CONTROL_IGMPV3_OP_MASK 0x30 +#define RTL8367C_IGMP_PORT8_CONTROL_IGMPV2_OP_OFFSET 2 +#define RTL8367C_IGMP_PORT8_CONTROL_IGMPV2_OP_MASK 0xC +#define RTL8367C_IGMP_PORT8_CONTROL_IGMPV1_OP_OFFSET 0 +#define RTL8367C_IGMP_PORT8_CONTROL_IGMPV1_OP_MASK 0x3 + +#define RTL8367C_REG_IGMP_PORT9_CONTROL 0x1cb1 +#define RTL8367C_IGMP_PORT9_CONTROL_ALLOW_QUERY_OFFSET 14 +#define RTL8367C_IGMP_PORT9_CONTROL_ALLOW_QUERY_MASK 0x4000 +#define RTL8367C_IGMP_PORT9_CONTROL_ALLOW_REPORT_OFFSET 13 +#define RTL8367C_IGMP_PORT9_CONTROL_ALLOW_REPORT_MASK 0x2000 +#define RTL8367C_IGMP_PORT9_CONTROL_ALLOW_LEAVE_OFFSET 12 +#define RTL8367C_IGMP_PORT9_CONTROL_ALLOW_LEAVE_MASK 0x1000 +#define RTL8367C_IGMP_PORT9_CONTROL_ALLOW_MRP_OFFSET 11 +#define RTL8367C_IGMP_PORT9_CONTROL_ALLOW_MRP_MASK 0x800 +#define RTL8367C_IGMP_PORT9_CONTROL_ALLOW_MC_DATA_OFFSET 10 +#define RTL8367C_IGMP_PORT9_CONTROL_ALLOW_MC_DATA_MASK 0x400 +#define RTL8367C_IGMP_PORT9_CONTROL_MLDv2_OP_OFFSET 8 +#define RTL8367C_IGMP_PORT9_CONTROL_MLDv2_OP_MASK 0x300 +#define RTL8367C_IGMP_PORT9_CONTROL_MLDv1_OP_OFFSET 6 +#define RTL8367C_IGMP_PORT9_CONTROL_MLDv1_OP_MASK 0xC0 +#define RTL8367C_IGMP_PORT9_CONTROL_IGMPV3_OP_OFFSET 4 +#define RTL8367C_IGMP_PORT9_CONTROL_IGMPV3_OP_MASK 0x30 +#define RTL8367C_IGMP_PORT9_CONTROL_IGMPV2_OP_OFFSET 2 +#define RTL8367C_IGMP_PORT9_CONTROL_IGMPV2_OP_MASK 0xC +#define RTL8367C_IGMP_PORT9_CONTROL_IGMPV1_OP_OFFSET 0 +#define RTL8367C_IGMP_PORT9_CONTROL_IGMPV1_OP_MASK 0x3 + +#define RTL8367C_REG_IGMP_PORT10_CONTROL 0x1cb2 +#define RTL8367C_IGMP_PORT10_CONTROL_ALLOW_QUERY_OFFSET 14 +#define RTL8367C_IGMP_PORT10_CONTROL_ALLOW_QUERY_MASK 0x4000 +#define RTL8367C_IGMP_PORT10_CONTROL_ALLOW_REPORT_OFFSET 13 +#define RTL8367C_IGMP_PORT10_CONTROL_ALLOW_REPORT_MASK 0x2000 +#define RTL8367C_IGMP_PORT10_CONTROL_ALLOW_LEAVE_OFFSET 12 +#define RTL8367C_IGMP_PORT10_CONTROL_ALLOW_LEAVE_MASK 0x1000 +#define RTL8367C_IGMP_PORT10_CONTROL_ALLOW_MRP_OFFSET 11 +#define RTL8367C_IGMP_PORT10_CONTROL_ALLOW_MRP_MASK 0x800 +#define RTL8367C_IGMP_PORT10_CONTROL_ALLOW_MC_DATA_OFFSET 10 +#define RTL8367C_IGMP_PORT10_CONTROL_ALLOW_MC_DATA_MASK 0x400 +#define RTL8367C_IGMP_PORT10_CONTROL_MLDv2_OP_OFFSET 8 +#define RTL8367C_IGMP_PORT10_CONTROL_MLDv2_OP_MASK 0x300 +#define RTL8367C_IGMP_PORT10_CONTROL_MLDv1_OP_OFFSET 6 +#define RTL8367C_IGMP_PORT10_CONTROL_MLDv1_OP_MASK 0xC0 +#define RTL8367C_IGMP_PORT10_CONTROL_IGMPV3_OP_OFFSET 4 +#define RTL8367C_IGMP_PORT10_CONTROL_IGMPV3_OP_MASK 0x30 +#define RTL8367C_IGMP_PORT10_CONTROL_IGMPV2_OP_OFFSET 2 +#define RTL8367C_IGMP_PORT10_CONTROL_IGMPV2_OP_MASK 0xC +#define RTL8367C_IGMP_PORT10_CONTROL_IGMPV1_OP_OFFSET 0 +#define RTL8367C_IGMP_PORT10_CONTROL_IGMPV1_OP_MASK 0x3 + +#define RTL8367C_REG_IGMP_PORT89_MAX_GROUP 0x1cb3 +#define RTL8367C_PORT9_MAX_GROUP_OFFSET 8 +#define RTL8367C_PORT9_MAX_GROUP_MASK 0xFF00 +#define RTL8367C_PORT8_MAX_GROUP_OFFSET 0 +#define RTL8367C_PORT8_MAX_GROUP_MASK 0xFF + +#define RTL8367C_REG_IGMP_PORT10_MAX_GROUP 0x1cb4 +#define RTL8367C_IGMP_PORT10_MAX_GROUP_OFFSET 0 +#define RTL8367C_IGMP_PORT10_MAX_GROUP_MASK 0xFF + +#define RTL8367C_REG_IGMP_PORT89_CURRENT_GROUP 0x1cb5 +#define RTL8367C_PORT9_CURRENT_GROUP_OFFSET 8 +#define RTL8367C_PORT9_CURRENT_GROUP_MASK 0xFF00 +#define RTL8367C_PORT8_CURRENT_GROUP_OFFSET 0 +#define RTL8367C_PORT8_CURRENT_GROUP_MASK 0xFF + +#define RTL8367C_REG_IGMP_PORT10_CURRENT_GROUP 0x1cb6 +#define RTL8367C_IGMP_PORT10_CURRENT_GROUP_OFFSET 0 +#define RTL8367C_IGMP_PORT10_CURRENT_GROUP_MASK 0xFF + +#define RTL8367C_REG_IGMP_L3_CHECKSUM_CHECK 0x1cb7 +#define RTL8367C_IGMP_L3_CHECKSUM_CHECK_OFFSET 0 +#define RTL8367C_IGMP_L3_CHECKSUM_CHECK_MASK 0x1 + +/* (16'h1d00)chip_70b_reg */ + +#define RTL8367C_REG_PCSXF_CFG 0x1d00 +#define RTL8367C_PCSXF_CFG_Reserved_OFFSET 15 +#define RTL8367C_PCSXF_CFG_Reserved_MASK 0x8000 +#define RTL8367C_CFG_RST_RXFIFO_P7_5_OFFSET 12 +#define RTL8367C_CFG_RST_RXFIFO_P7_5_MASK 0x7000 +#define RTL8367C_CFG_PCSXF_OFFSET 8 +#define RTL8367C_CFG_PCSXF_MASK 0xF00 +#define RTL8367C_CFG_RST_RXFIFO_OFFSET 3 +#define RTL8367C_CFG_RST_RXFIFO_MASK 0xF8 +#define RTL8367C_CFG_COL2RXDV_OFFSET 2 +#define RTL8367C_CFG_COL2RXDV_MASK 0x4 +#define RTL8367C_CFG_PHY_SDET_OFFSET 0 +#define RTL8367C_CFG_PHY_SDET_MASK 0x3 + +#define RTL8367C_REG_PHYID_CFG0 0x1d01 +#define RTL8367C_CFG_PHY_BRD_MODE_P7_5_OFFSET 11 +#define RTL8367C_CFG_PHY_BRD_MODE_P7_5_MASK 0x3800 +#define RTL8367C_CFG_PHYAD_14C_OFFSET 10 +#define RTL8367C_CFG_PHYAD_14C_MASK 0x400 +#define RTL8367C_CFG_PHY_BRD_MODE_OFFSET 5 +#define RTL8367C_CFG_PHY_BRD_MODE_MASK 0x3E0 +#define RTL8367C_CFG_BRD_PHYAD_OFFSET 0 +#define RTL8367C_CFG_BRD_PHYAD_MASK 0x1F + +#define RTL8367C_REG_PHYID_CFG1 0x1d02 +#define RTL8367C_CFG_MSK_MDI_OFFSET 5 +#define RTL8367C_CFG_MSK_MDI_MASK 0x1FE0 +#define RTL8367C_CFG_BASE_PHYAD_OFFSET 0 +#define RTL8367C_CFG_BASE_PHYAD_MASK 0x1F + +#define RTL8367C_REG_PHY_POLL_CFG0 0x1d03 +#define RTL8367C_CFG_HOTCMD_PRD_EN_OFFSET 15 +#define RTL8367C_CFG_HOTCMD_PRD_EN_MASK 0x8000 +#define RTL8367C_CFG_HOTCMD_EN_OFFSET 12 +#define RTL8367C_CFG_HOTCMD_EN_MASK 0x7000 +#define RTL8367C_CFG_POLL_PERIOD_OFFSET 8 +#define RTL8367C_CFG_POLL_PERIOD_MASK 0xF00 +#define RTL8367C_CFG_PERI_CMDS_RD_OFFSET 4 +#define RTL8367C_CFG_PERI_CMDS_RD_MASK 0xF0 +#define RTL8367C_CFG_PERI_CMDS_WR_OFFSET 0 +#define RTL8367C_CFG_PERI_CMDS_WR_MASK 0xF + +#define RTL8367C_REG_PHY_POLL_CFG1 0x1d04 + +#define RTL8367C_REG_PHY_POLL_CFG2 0x1d05 + +#define RTL8367C_REG_PHY_POLL_CFG3 0x1d06 + +#define RTL8367C_REG_PHY_POLL_CFG4 0x1d07 + +#define RTL8367C_REG_PHY_POLL_CFG5 0x1d08 + +#define RTL8367C_REG_PHY_POLL_CFG6 0x1d09 + +#define RTL8367C_REG_PHY_POLL_CFG7 0x1d0a + +#define RTL8367C_REG_PHY_POLL_CFG8 0x1d0b + +#define RTL8367C_REG_PHY_POLL_CFG9 0x1d0c + +#define RTL8367C_REG_PHY_POLL_CFG10 0x1d0d + +#define RTL8367C_REG_PHY_POLL_CFG11 0x1d0e + +#define RTL8367C_REG_PHY_POLL_CFG12 0x1d0f + +#define RTL8367C_REG_EFUSE_MISC 0x1d10 +#define RTL8367C_CFG_SA_SEL_OFFSET 5 +#define RTL8367C_CFG_SA_SEL_MASK 0x20 +#define RTL8367C_CFG_PHYAD00_OFFSET 0 +#define RTL8367C_CFG_PHYAD00_MASK 0x1F + +#define RTL8367C_REG_SDS_MISC 0x1d11 +#define RTL8367C_CFG_SGMII_RXFC_OFFSET 14 +#define RTL8367C_CFG_SGMII_RXFC_MASK 0x4000 +#define RTL8367C_CFG_SGMII_TXFC_OFFSET 13 +#define RTL8367C_CFG_SGMII_TXFC_MASK 0x2000 +#define RTL8367C_INB_ARB_OFFSET 12 +#define RTL8367C_INB_ARB_MASK 0x1000 +#define RTL8367C_CFG_MAC8_SEL_HSGMII_OFFSET 11 +#define RTL8367C_CFG_MAC8_SEL_HSGMII_MASK 0x800 +#define RTL8367C_CFG_SGMII_FDUP_OFFSET 10 +#define RTL8367C_CFG_SGMII_FDUP_MASK 0x400 +#define RTL8367C_CFG_SGMII_LINK_OFFSET 9 +#define RTL8367C_CFG_SGMII_LINK_MASK 0x200 +#define RTL8367C_CFG_SGMII_SPD_OFFSET 7 +#define RTL8367C_CFG_SGMII_SPD_MASK 0x180 +#define RTL8367C_CFG_MAC8_SEL_SGMII_OFFSET 6 +#define RTL8367C_CFG_MAC8_SEL_SGMII_MASK 0x40 +#define RTL8367C_CFG_INB_SEL_OFFSET 3 +#define RTL8367C_CFG_INB_SEL_MASK 0x38 +#define RTL8367C_CFG_SDS_MODE_18C_OFFSET 0 +#define RTL8367C_CFG_SDS_MODE_18C_MASK 0x7 + +#define RTL8367C_REG_FIFO_CTRL 0x1d12 +#define RTL8367C_CFG_LINK_DOWN_CLR_FIFO_OFFSET 11 +#define RTL8367C_CFG_LINK_DOWN_CLR_FIFO_MASK 0x800 +#define RTL8367C_CFG_LPBK_OFFSET 10 +#define RTL8367C_CFG_LPBK_MASK 0x400 +#define RTL8367C_CFG_NOT_FF_OUT_OFFSET 9 +#define RTL8367C_CFG_NOT_FF_OUT_MASK 0x200 +#define RTL8367C_CFG_WATER_LEVEL_FD_OFFSET 6 +#define RTL8367C_CFG_WATER_LEVEL_FD_MASK 0x1C0 +#define RTL8367C_CFG_WATER_LEVEL_Y2X_OFFSET 3 +#define RTL8367C_CFG_WATER_LEVEL_Y2X_MASK 0x38 +#define RTL8367C_CFG_WATER_LEVEL_X2Y_OFFSET 0 +#define RTL8367C_CFG_WATER_LEVEL_X2Y_MASK 0x7 + +#define RTL8367C_REG_BCAM_SETTING 0x1d13 +#define RTL8367C_CFG_BCAM_MDS_OFFSET 3 +#define RTL8367C_CFG_BCAM_MDS_MASK 0x18 +#define RTL8367C_CFG_BCAM_RDS_OFFSET 0 +#define RTL8367C_CFG_BCAM_RDS_MASK 0x7 + +#define RTL8367C_REG_GPHY_ACS_MISC 0x1d14 +#define RTL8367C_CFG_SEL_GPHY_SMI_OFFSET 3 +#define RTL8367C_CFG_SEL_GPHY_SMI_MASK 0x8 +#define RTL8367C_CFG_BRD_PHYIDX_OFFSET 0 +#define RTL8367C_CFG_BRD_PHYIDX_MASK 0x7 + +#define RTL8367C_REG_GPHY_OCP_MSB_0 0x1d15 +#define RTL8367C_CFG_CPU_OCPADR_MSB_OFFSET 6 +#define RTL8367C_CFG_CPU_OCPADR_MSB_MASK 0xFC0 +#define RTL8367C_CFG_DW8051_OCPADR_MSB_OFFSET 0 +#define RTL8367C_CFG_DW8051_OCPADR_MSB_MASK 0x3F + +#define RTL8367C_REG_GPHY_OCP_MSB_1 0x1d16 +#define RTL8367C_CFG_PATCH_OCPADR_MSB_OFFSET 6 +#define RTL8367C_CFG_PATCH_OCPADR_MSB_MASK 0xFC0 +#define RTL8367C_CFG_PHYSTS_OCPADR_MSB_OFFSET 0 +#define RTL8367C_CFG_PHYSTS_OCPADR_MSB_MASK 0x3F + +#define RTL8367C_REG_GPHY_OCP_MSB_2 0x1d17 +#define RTL8367C_CFG_RRCP_OCPADR_MSB_OFFSET 6 +#define RTL8367C_CFG_RRCP_OCPADR_MSB_MASK 0xFC0 +#define RTL8367C_CFG_RTCT_OCPADR_MSB_OFFSET 0 +#define RTL8367C_CFG_RTCT_OCPADR_MSB_MASK 0x3F + +#define RTL8367C_REG_GPHY_OCP_MSB_3 0x1d18 +#define RTL8367C_GPHY_OCP_MSB_3_OFFSET 0 +#define RTL8367C_GPHY_OCP_MSB_3_MASK 0x3F + +#define RTL8367C_REG_GPIO_67C_I_X0 0x1d19 + +#define RTL8367C_REG_GPIO_67C_I_X1 0x1d1a + +#define RTL8367C_REG_GPIO_67C_I_X2 0x1d1b + +#define RTL8367C_REG_GPIO_67C_I_X3 0x1d1c +#define RTL8367C_GPIO_67C_I_X3_OFFSET 0 +#define RTL8367C_GPIO_67C_I_X3_MASK 0x3FFF + +#define RTL8367C_REG_GPIO_67C_O_X0 0x1d1d + +#define RTL8367C_REG_GPIO_67C_O_X1 0x1d1e + +#define RTL8367C_REG_GPIO_67C_O_X2 0x1d1f + +#define RTL8367C_REG_GPIO_67C_O_X3 0x1d20 +#define RTL8367C_GPIO_67C_O_X3_OFFSET 0 +#define RTL8367C_GPIO_67C_O_X3_MASK 0x3FFF + +#define RTL8367C_REG_GPIO_67C_OE_X0 0x1d21 + +#define RTL8367C_REG_GPIO_67C_OE_X1 0x1d22 + +#define RTL8367C_REG_GPIO_67C_OE_X2 0x1d23 + +#define RTL8367C_REG_GPIO_67C_OE_X3 0x1d24 +#define RTL8367C_GPIO_67C_OE_X3_OFFSET 0 +#define RTL8367C_GPIO_67C_OE_X3_MASK 0x3FFF + +#define RTL8367C_REG_GPIO_MODE_67C_X0 0x1d25 + +#define RTL8367C_REG_GPIO_MODE_67C_X1 0x1d26 + +#define RTL8367C_REG_GPIO_MODE_67C_X2 0x1d27 + +#define RTL8367C_REG_GPIO_MODE_67C_X3 0x1d28 +#define RTL8367C_GPIO_MODE_67C_X3_OFFSET 0 +#define RTL8367C_GPIO_MODE_67C_X3_MASK 0x3FFF + +#define RTL8367C_REG_WGPHY_MISC_0 0x1d29 +#define RTL8367C_CFG_INIPHY_DISGIGA_P7_5_OFFSET 13 +#define RTL8367C_CFG_INIPHY_DISGIGA_P7_5_MASK 0xE000 +#define RTL8367C_CFG_INIPHY_PWRUP_OFFSET 5 +#define RTL8367C_CFG_INIPHY_PWRUP_MASK 0x1FE0 +#define RTL8367C_CFG_INIPHY_DISGIGA_OFFSET 0 +#define RTL8367C_CFG_INIPHY_DISGIGA_MASK 0x1F + +#define RTL8367C_REG_WGPHY_MISC_1 0x1d2a +#define RTL8367C_WGPHY_MISC_1_OFFSET 0 +#define RTL8367C_WGPHY_MISC_1_MASK 0xFF + +#define RTL8367C_REG_WGPHY_MISC_2 0x1d2b +#define RTL8367C_WGPHY_MISC_2_OFFSET 0 +#define RTL8367C_WGPHY_MISC_2_MASK 0x3FF + +#define RTL8367C_REG_CFG_AFBK_GPHY_0 0x1d2c +#define RTL8367C_CFG_AFBK_GPHY_0_OFFSET 0 +#define RTL8367C_CFG_AFBK_GPHY_0_MASK 0x1F + +#define RTL8367C_REG_CFG_AFBK_GPHY_1 0x1d2d +#define RTL8367C_CFG_AFBK_GPHY_1_OFFSET 0 +#define RTL8367C_CFG_AFBK_GPHY_1_MASK 0xFFF + +#define RTL8367C_REG_EF_SLV_CTRL_0 0x1d2e +#define RTL8367C_EF_SLV_BUSY_OFFSET 11 +#define RTL8367C_EF_SLV_BUSY_MASK 0x800 +#define RTL8367C_EF_SLV_ACK_OFFSET 10 +#define RTL8367C_EF_SLV_ACK_MASK 0x400 +#define RTL8367C_EF_SLV_A_OFFSET 2 +#define RTL8367C_EF_SLV_A_MASK 0x3FC +#define RTL8367C_EF_SLV_WE_OFFSET 1 +#define RTL8367C_EF_SLV_WE_MASK 0x2 +#define RTL8367C_EF_SLV_CE_OFFSET 0 +#define RTL8367C_EF_SLV_CE_MASK 0x1 + +#define RTL8367C_REG_EF_SLV_CTRL_1 0x1d2f + +#define RTL8367C_REG_EF_SLV_CTRL_2 0x1d30 + +#define RTL8367C_REG_EFUSE_MISC_1 0x1d31 +#define RTL8367C_EF_EN_EFUSE_OFFSET 10 +#define RTL8367C_EF_EN_EFUSE_MASK 0x400 +#define RTL8367C_EF_MODEL_ID_OFFSET 6 +#define RTL8367C_EF_MODEL_ID_MASK 0x3C0 +#define RTL8367C_EF_RSVD_OFFSET 2 +#define RTL8367C_EF_RSVD_MASK 0x3C +#define RTL8367C_EF_SYS_CLK_OFFSET 0 +#define RTL8367C_EF_SYS_CLK_MASK 0x3 + +#define RTL8367C_REG_IO_MISC_FUNC 0x1d32 +#define RTL8367C_TST_MODE_OFFSET 3 +#define RTL8367C_TST_MODE_MASK 0x8 +#define RTL8367C_UART_EN_OFFSET 2 +#define RTL8367C_UART_EN_MASK 0x4 +#define RTL8367C_INT_EN_OFFSET 1 +#define RTL8367C_INT_EN_MASK 0x2 +#define RTL8367C_BUZ_EN_OFFSET 0 +#define RTL8367C_BUZ_EN_MASK 0x1 + +#define RTL8367C_REG_HTRAM_DVS 0x1d33 +#define RTL8367C_HTRAM_DVS_OFFSET 0 +#define RTL8367C_HTRAM_DVS_MASK 0x1 + +#define RTL8367C_REG_EF_SLV_CTRL_3 0x1d34 +#define RTL8367C_EF_SLV_CTRL_3_OFFSET 0 +#define RTL8367C_EF_SLV_CTRL_3_MASK 0x1 + +#define RTL8367C_REG_INBAND_EN14C 0x1d35 +#define RTL8367C_INBAND_EN14C_OFFSET 0 +#define RTL8367C_INBAND_EN14C_MASK 0x1 + +#define RTL8367C_REG_CFG_SWR_L 0x1d36 +#define RTL8367C_ANARG_RDY_SWR_L_OFFSET 14 +#define RTL8367C_ANARG_RDY_SWR_L_MASK 0x4000 +#define RTL8367C_ANARG_VALID_SWR_L_OFFSET 13 +#define RTL8367C_ANARG_VALID_SWR_L_MASK 0x2000 +#define RTL8367C_SAW_SWR_L_OFFSET 9 +#define RTL8367C_SAW_SWR_L_MASK 0x1E00 +#define RTL8367C_SAW_VALID_SWR_L_OFFSET 8 +#define RTL8367C_SAW_VALID_SWR_L_MASK 0x100 +#define RTL8367C_UPS_DBGO_L_OFFSET 0 +#define RTL8367C_UPS_DBGO_L_MASK 0xFF + +#define RTL8367C_REG_BTCAM_CTRL 0x1d37 +#define RTL8367C_TCAM_RDS_OFFSET 2 +#define RTL8367C_TCAM_RDS_MASK 0x1C +#define RTL8367C_TCAM_MDS_OFFSET 0 +#define RTL8367C_TCAM_MDS_MASK 0x3 + +#define RTL8367C_REG_PBRAM_BISR_CTRL 0x1d38 +#define RTL8367C_HAS_HLDRMP_MD_OFFSET 9 +#define RTL8367C_HAS_HLDRMP_MD_MASK 0x200 +#define RTL8367C_PB_HLDRMP_MD_OFFSET 8 +#define RTL8367C_PB_HLDRMP_MD_MASK 0x100 +#define RTL8367C_HAS_BISR_BIRSTN_OFFSET 7 +#define RTL8367C_HAS_BISR_BIRSTN_MASK 0x80 +#define RTL8367C_SEC_RUN_HSA_OFFSET 6 +#define RTL8367C_SEC_RUN_HSA_MASK 0x40 +#define RTL8367C_HAS_HLDRMP_VAL_OFFSET 5 +#define RTL8367C_HAS_HLDRMP_VAL_MASK 0x20 +#define RTL8367C_HAS_BISR_PWRSTN_OFFSET 4 +#define RTL8367C_HAS_BISR_PWRSTN_MASK 0x10 +#define RTL8367C_SEC_RUN_PB_OFFSET 3 +#define RTL8367C_SEC_RUN_PB_MASK 0x8 +#define RTL8367C_PB_HLDRMP_VAL_OFFSET 2 +#define RTL8367C_PB_HLDRMP_VAL_MASK 0x4 +#define RTL8367C_PB_BISR_BIRSTN_OFFSET 1 +#define RTL8367C_PB_BISR_BIRSTN_MASK 0x2 +#define RTL8367C_PB_BISR_PWRSTN_OFFSET 0 +#define RTL8367C_PB_BISR_PWRSTN_MASK 0x1 + +#define RTL8367C_REG_CVLANRAM_BISR_CTRL 0x1d39 +#define RTL8367C_SEC_RUN_CVLAN_OFFSET 4 +#define RTL8367C_SEC_RUN_CVLAN_MASK 0x10 +#define RTL8367C_CVALN_HLDRMP_MD_OFFSET 3 +#define RTL8367C_CVALN_HLDRMP_MD_MASK 0x8 +#define RTL8367C_CVALN_HLDRMP_VAL_OFFSET 2 +#define RTL8367C_CVALN_HLDRMP_VAL_MASK 0x4 +#define RTL8367C_CVLAN_BISR_BIRSTN_OFFSET 1 +#define RTL8367C_CVLAN_BISR_BIRSTN_MASK 0x2 +#define RTL8367C_CVLAN_BISR_PWRSTN_OFFSET 0 +#define RTL8367C_CVLAN_BISR_PWRSTN_MASK 0x1 + +#define RTL8367C_REG_CFG_1588_TIMER_EN_GPI 0x1d3a +#define RTL8367C_CFG_1588_TIMER_EN_GPI_OFFSET 0 +#define RTL8367C_CFG_1588_TIMER_EN_GPI_MASK 0x1 + +#define RTL8367C_REG_MDIO_PRMB_SUPP 0x1d3b +#define RTL8367C_FIB_HIPRI_OFFSET 14 +#define RTL8367C_FIB_HIPRI_MASK 0x4000 +#define RTL8367C_SMT_EN_OFFSET 13 +#define RTL8367C_SMT_EN_MASK 0x2000 +#define RTL8367C_P4_FB_CPL_OFFSET 12 +#define RTL8367C_P4_FB_CPL_MASK 0x1000 +#define RTL8367C_P3_FB_CPL_OFFSET 11 +#define RTL8367C_P3_FB_CPL_MASK 0x800 +#define RTL8367C_P2_FB_CPL_OFFSET 10 +#define RTL8367C_P2_FB_CPL_MASK 0x400 +#define RTL8367C_P1_FB_CPL_OFFSET 9 +#define RTL8367C_P1_FB_CPL_MASK 0x200 +#define RTL8367C_P0_FB_CPL_OFFSET 8 +#define RTL8367C_P0_FB_CPL_MASK 0x100 +#define RTL8367C_DBG_PKG_8367N_OFFSET 7 +#define RTL8367C_DBG_PKG_8367N_MASK 0x80 +#define RTL8367C_DBG_PKG_8367VB_OFFSET 6 +#define RTL8367C_DBG_PKG_8367VB_MASK 0x40 +#define RTL8367C_CFG_DEBUG_EN_OFFSET 5 +#define RTL8367C_CFG_DEBUG_EN_MASK 0x20 +#define RTL8367C_CFG_TMR_ACK_OFFSET 1 +#define RTL8367C_CFG_TMR_ACK_MASK 0x1E +#define RTL8367C_CFG_PRMB_SUPP_OFFSET 0 +#define RTL8367C_CFG_PRMB_SUPP_MASK 0x1 + +#define RTL8367C_REG_BOND4READ 0x1d3c +#define RTL8367C_BOND_BOID0_OFFSET 8 +#define RTL8367C_BOND_BOID0_MASK 0x100 +#define RTL8367C_BOND_SYSCLK_OFFSET 7 +#define RTL8367C_BOND_SYSCLK_MASK 0x80 +#define RTL8367C_BOND_PHYMODE_OFFSET 6 +#define RTL8367C_BOND_PHYMODE_MASK 0x40 +#define RTL8367C_BOND_DIS_PON_BIST_OFFSET 5 +#define RTL8367C_BOND_DIS_PON_BIST_MASK 0x20 +#define RTL8367C_BOND_DIS_TABLE_INIT_OFFSET 4 +#define RTL8367C_BOND_DIS_TABLE_INIT_MASK 0x10 +#define RTL8367C_BOND_BYP_AFE_PLL_OFFSET 3 +#define RTL8367C_BOND_BYP_AFE_PLL_MASK 0x8 +#define RTL8367C_BOND_BYP_AFE_POR_OFFSET 2 +#define RTL8367C_BOND_BYP_AFE_POR_MASK 0x4 +#define RTL8367C_BOND_BISR_COND_OFFSET 1 +#define RTL8367C_BOND_BISR_COND_MASK 0x2 +#define RTL8367C_BOND_EF_EN_OFFSET 0 +#define RTL8367C_BOND_EF_EN_MASK 0x1 + +#define RTL8367C_REG_REG_TO_ECO0 0x1d3d + +#define RTL8367C_REG_REG_TO_ECO1 0x1d3e + +#define RTL8367C_REG_REG_TO_ECO2 0x1d3f + +#define RTL8367C_REG_REG_TO_ECO3 0x1d40 + +#define RTL8367C_REG_REG_TO_ECO4 0x1d41 + +#define RTL8367C_REG_PHYSTS_CTRL0 0x1d42 +#define RTL8367C_MACRX_DUPDET_EN_OFFSET 5 +#define RTL8367C_MACRX_DUPDET_EN_MASK 0x20 +#define RTL8367C_LNKUP_DLY_EN_OFFSET 4 +#define RTL8367C_LNKUP_DLY_EN_MASK 0x10 +#define RTL8367C_GE_100M_LNKUP_DLY_OFFSET 2 +#define RTL8367C_GE_100M_LNKUP_DLY_MASK 0xC +#define RTL8367C_PHYSTS_10M_LNKUP_DLY_OFFSET 0 +#define RTL8367C_PHYSTS_10M_LNKUP_DLY_MASK 0x3 + +#define RTL8367C_REG_SSC_CTRL0_0 0x1d44 +#define RTL8367C_SSC_CTRL0_0_SSC_TYPE_OFFSET 13 +#define RTL8367C_SSC_CTRL0_0_SSC_TYPE_MASK 0x2000 +#define RTL8367C_SSC_CTRL0_0_PHASE_LIM_SEL_OFFSET 5 +#define RTL8367C_SSC_CTRL0_0_PHASE_LIM_SEL_MASK 0x1FE0 +#define RTL8367C_SSC_CTRL0_0_PHASE_LIM_EN_OFFSET 4 +#define RTL8367C_SSC_CTRL0_0_PHASE_LIM_EN_MASK 0x10 +#define RTL8367C_SSC_CTRL0_0_DLL_MODE_OFFSET 2 +#define RTL8367C_SSC_CTRL0_0_DLL_MODE_MASK 0xC +#define RTL8367C_SSC_CTRL0_0_SSC_EN_OFFSET 1 +#define RTL8367C_SSC_CTRL0_0_SSC_EN_MASK 0x2 +#define RTL8367C_SSC_CTRL0_0_SSC_MODE_OFFSET 0 +#define RTL8367C_SSC_CTRL0_0_SSC_MODE_MASK 0x1 + +#define RTL8367C_REG_SSC_RDM_SEED 0x1d45 + +#define RTL8367C_REG_SSC_PN_POLY_SEL 0x1d46 + +#define RTL8367C_REG_SSC_CTRL0_3 0x1d47 +#define RTL8367C_SSC_CTRL0_3_PHSFT_CNT_OFFSET 8 +#define RTL8367C_SSC_CTRL0_3_PHSFT_CNT_MASK 0x7F00 +#define RTL8367C_SSC_CTRL0_3_PHSFT_A_OFFSET 7 +#define RTL8367C_SSC_CTRL0_3_PHSFT_A_MASK 0x80 +#define RTL8367C_SSC_CTRL0_3_PHSFT_B_OFFSET 6 +#define RTL8367C_SSC_CTRL0_3_PHSFT_B_MASK 0x40 +#define RTL8367C_SSC_CTRL0_3_PHSFT_UPDN_OFFSET 5 +#define RTL8367C_SSC_CTRL0_3_PHSFT_UPDN_MASK 0x20 +#define RTL8367C_SSC_CTRL0_3_PHSFT_PRD_OFFSET 4 +#define RTL8367C_SSC_CTRL0_3_PHSFT_PRD_MASK 0x10 +#define RTL8367C_SSC_CTRL0_3_PN_POLY_DEG_OFFSET 0 +#define RTL8367C_SSC_CTRL0_3_PN_POLY_DEG_MASK 0xF + +#define RTL8367C_REG_SSC_CTRL0_4 0x1d48 +#define RTL8367C_SSC_CTRL0_4_SSC_UP1DN0_OFFSET 15 +#define RTL8367C_SSC_CTRL0_4_SSC_UP1DN0_MASK 0x8000 +#define RTL8367C_SSC_CTRL0_4_SSC_PERIOD_OFFSET 8 +#define RTL8367C_SSC_CTRL0_4_SSC_PERIOD_MASK 0x7F00 +#define RTL8367C_SSC_CTRL0_4_SSC_OFFSET_OFFSET 0 +#define RTL8367C_SSC_CTRL0_4_SSC_OFFSET_MASK 0xFF + +#define RTL8367C_REG_SSC_CTRL0_5 0x1d49 +#define RTL8367C_SSC_CTRL0_5_PH_OFS_TOG_OFFSET 15 +#define RTL8367C_SSC_CTRL0_5_PH_OFS_TOG_MASK 0x8000 +#define RTL8367C_SSC_CTRL0_5_PH_OFS_OFFSET 10 +#define RTL8367C_SSC_CTRL0_5_PH_OFS_MASK 0x7C00 +#define RTL8367C_SSC_CTRL0_5_SSC_STEP_OFFSET 4 +#define RTL8367C_SSC_CTRL0_5_SSC_STEP_MASK 0x3F0 +#define RTL8367C_SSC_CTRL0_5_SSC_TEST_MODE_OFFSET 2 +#define RTL8367C_SSC_CTRL0_5_SSC_TEST_MODE_MASK 0xC +#define RTL8367C_SSC_CTRL0_5_SSC_PH_CFG_OFFSET 0 +#define RTL8367C_SSC_CTRL0_5_SSC_PH_CFG_MASK 0x3 + +#define RTL8367C_REG_SSC_STS0 0x1d4a +#define RTL8367C_SSC_STS0_OFS_BUSY_OFFSET 13 +#define RTL8367C_SSC_STS0_OFS_BUSY_MASK 0x2000 +#define RTL8367C_SSC_STS0_OFS_TOTAL_R_OFFSET 8 +#define RTL8367C_SSC_STS0_OFS_TOTAL_R_MASK 0x1F00 +#define RTL8367C_SSC_STS0_CNT_GRY0_OFFSET 4 +#define RTL8367C_SSC_STS0_CNT_GRY0_MASK 0xF0 +#define RTL8367C_SSC_STS0_OFS_GRY0_OFFSET 0 +#define RTL8367C_SSC_STS0_OFS_GRY0_MASK 0xF + +#define RTL8367C_REG_SSC_CTRL1_0 0x1d4b +#define RTL8367C_SSC_CTRL1_0_SSC_TYPE_OFFSET 13 +#define RTL8367C_SSC_CTRL1_0_SSC_TYPE_MASK 0x2000 +#define RTL8367C_SSC_CTRL1_0_PHASE_LIM_SEL_OFFSET 5 +#define RTL8367C_SSC_CTRL1_0_PHASE_LIM_SEL_MASK 0x1FE0 +#define RTL8367C_SSC_CTRL1_0_PHASE_LIM_EN_OFFSET 4 +#define RTL8367C_SSC_CTRL1_0_PHASE_LIM_EN_MASK 0x10 +#define RTL8367C_SSC_CTRL1_0_DLL_MODE_OFFSET 2 +#define RTL8367C_SSC_CTRL1_0_DLL_MODE_MASK 0xC +#define RTL8367C_SSC_CTRL1_0_SSC_EN_OFFSET 1 +#define RTL8367C_SSC_CTRL1_0_SSC_EN_MASK 0x2 +#define RTL8367C_SSC_CTRL1_0_SSC_MODE_OFFSET 0 +#define RTL8367C_SSC_CTRL1_0_SSC_MODE_MASK 0x1 + +#define RTL8367C_REG_SSC_RDM_SEED1 0x1d4c + +#define RTL8367C_REG_SSC_PN_POLY_SEL1 0x1d4d + +#define RTL8367C_REG_SSC_CTRL1_3 0x1d4e +#define RTL8367C_SSC_CTRL1_3_PHSFT_CNT_OFFSET 8 +#define RTL8367C_SSC_CTRL1_3_PHSFT_CNT_MASK 0x7F00 +#define RTL8367C_SSC_CTRL1_3_PHSFT_A_OFFSET 7 +#define RTL8367C_SSC_CTRL1_3_PHSFT_A_MASK 0x80 +#define RTL8367C_SSC_CTRL1_3_PHSFT_B_OFFSET 6 +#define RTL8367C_SSC_CTRL1_3_PHSFT_B_MASK 0x40 +#define RTL8367C_SSC_CTRL1_3_PHSFT_UPDN_OFFSET 5 +#define RTL8367C_SSC_CTRL1_3_PHSFT_UPDN_MASK 0x20 +#define RTL8367C_SSC_CTRL1_3_PHSFT_PRD_OFFSET 4 +#define RTL8367C_SSC_CTRL1_3_PHSFT_PRD_MASK 0x10 +#define RTL8367C_SSC_CTRL1_3_PN_POLY_DEG_OFFSET 0 +#define RTL8367C_SSC_CTRL1_3_PN_POLY_DEG_MASK 0xF + +#define RTL8367C_REG_SSC_CTRL1_4 0x1d4f +#define RTL8367C_SSC_CTRL1_4_SSC_UP1DN0_OFFSET 15 +#define RTL8367C_SSC_CTRL1_4_SSC_UP1DN0_MASK 0x8000 +#define RTL8367C_SSC_CTRL1_4_SSC_PERIOD_OFFSET 8 +#define RTL8367C_SSC_CTRL1_4_SSC_PERIOD_MASK 0x7F00 +#define RTL8367C_SSC_CTRL1_4_SSC_OFFSET_OFFSET 0 +#define RTL8367C_SSC_CTRL1_4_SSC_OFFSET_MASK 0xFF + +#define RTL8367C_REG_SSC_CTRL1_5 0x1d50 +#define RTL8367C_SSC_CTRL1_5_PH_OFS_TOG_OFFSET 15 +#define RTL8367C_SSC_CTRL1_5_PH_OFS_TOG_MASK 0x8000 +#define RTL8367C_SSC_CTRL1_5_PH_OFS_OFFSET 10 +#define RTL8367C_SSC_CTRL1_5_PH_OFS_MASK 0x7C00 +#define RTL8367C_SSC_CTRL1_5_SSC_STEP_OFFSET 4 +#define RTL8367C_SSC_CTRL1_5_SSC_STEP_MASK 0x3F0 +#define RTL8367C_SSC_CTRL1_5_SSC_TEST_MODE_OFFSET 2 +#define RTL8367C_SSC_CTRL1_5_SSC_TEST_MODE_MASK 0xC +#define RTL8367C_SSC_CTRL1_5_SSC_PH_CFG_OFFSET 0 +#define RTL8367C_SSC_CTRL1_5_SSC_PH_CFG_MASK 0x3 + +#define RTL8367C_REG_SSC_STS1 0x1d51 +#define RTL8367C_SSC_STS1_OFS_BUSY_OFFSET 13 +#define RTL8367C_SSC_STS1_OFS_BUSY_MASK 0x2000 +#define RTL8367C_SSC_STS1_OFS_TOTAL_R_OFFSET 8 +#define RTL8367C_SSC_STS1_OFS_TOTAL_R_MASK 0x1F00 +#define RTL8367C_SSC_STS1_CNT_GRY0_OFFSET 4 +#define RTL8367C_SSC_STS1_CNT_GRY0_MASK 0xF0 +#define RTL8367C_SSC_STS1_OFS_GRY0_OFFSET 0 +#define RTL8367C_SSC_STS1_OFS_GRY0_MASK 0xF + +#define RTL8367C_REG_SSC_CTRL2_0 0x1d52 +#define RTL8367C_SSC_CTRL2_0_SSC_TYPE_OFFSET 13 +#define RTL8367C_SSC_CTRL2_0_SSC_TYPE_MASK 0x2000 +#define RTL8367C_SSC_CTRL2_0_PHASE_LIM_SEL_OFFSET 5 +#define RTL8367C_SSC_CTRL2_0_PHASE_LIM_SEL_MASK 0x1FE0 +#define RTL8367C_SSC_CTRL2_0_PHASE_LIM_EN_OFFSET 4 +#define RTL8367C_SSC_CTRL2_0_PHASE_LIM_EN_MASK 0x10 +#define RTL8367C_SSC_CTRL2_0_DLL_MODE_OFFSET 2 +#define RTL8367C_SSC_CTRL2_0_DLL_MODE_MASK 0xC +#define RTL8367C_SSC_CTRL2_0_SSC_EN_OFFSET 1 +#define RTL8367C_SSC_CTRL2_0_SSC_EN_MASK 0x2 +#define RTL8367C_SSC_CTRL2_0_SSC_MODE_OFFSET 0 +#define RTL8367C_SSC_CTRL2_0_SSC_MODE_MASK 0x1 + +#define RTL8367C_REG_SSC_RDM_SEED2 0x1d53 + +#define RTL8367C_REG_SSC_PN_POLY_SEL2 0x1d54 + +#define RTL8367C_REG_SSC_CTRL2_3 0x1d55 +#define RTL8367C_SSC_CTRL2_3_PHSFT_CNT_OFFSET 8 +#define RTL8367C_SSC_CTRL2_3_PHSFT_CNT_MASK 0x7F00 +#define RTL8367C_SSC_CTRL2_3_PHSFT_A_OFFSET 7 +#define RTL8367C_SSC_CTRL2_3_PHSFT_A_MASK 0x80 +#define RTL8367C_SSC_CTRL2_3_PHSFT_B_OFFSET 6 +#define RTL8367C_SSC_CTRL2_3_PHSFT_B_MASK 0x40 +#define RTL8367C_SSC_CTRL2_3_PHSFT_UPDN_OFFSET 5 +#define RTL8367C_SSC_CTRL2_3_PHSFT_UPDN_MASK 0x20 +#define RTL8367C_SSC_CTRL2_3_PHSFT_PRD_OFFSET 4 +#define RTL8367C_SSC_CTRL2_3_PHSFT_PRD_MASK 0x10 +#define RTL8367C_SSC_CTRL2_3_PN_POLY_DEG_OFFSET 0 +#define RTL8367C_SSC_CTRL2_3_PN_POLY_DEG_MASK 0xF + +#define RTL8367C_REG_SSC_CTRL2_4 0x1d56 +#define RTL8367C_SSC_CTRL2_4_SSC_UP1DN0_OFFSET 15 +#define RTL8367C_SSC_CTRL2_4_SSC_UP1DN0_MASK 0x8000 +#define RTL8367C_SSC_CTRL2_4_SSC_PERIOD_OFFSET 8 +#define RTL8367C_SSC_CTRL2_4_SSC_PERIOD_MASK 0x7F00 +#define RTL8367C_SSC_CTRL2_4_SSC_OFFSET_OFFSET 0 +#define RTL8367C_SSC_CTRL2_4_SSC_OFFSET_MASK 0xFF + +#define RTL8367C_REG_SSC_CTRL2_5 0x1d57 +#define RTL8367C_SSC_CTRL2_5_PH_OFS_TOG_OFFSET 15 +#define RTL8367C_SSC_CTRL2_5_PH_OFS_TOG_MASK 0x8000 +#define RTL8367C_SSC_CTRL2_5_PH_OFS_OFFSET 10 +#define RTL8367C_SSC_CTRL2_5_PH_OFS_MASK 0x7C00 +#define RTL8367C_SSC_CTRL2_5_SSC_STEP_OFFSET 4 +#define RTL8367C_SSC_CTRL2_5_SSC_STEP_MASK 0x3F0 +#define RTL8367C_SSC_CTRL2_5_SSC_TEST_MODE_OFFSET 2 +#define RTL8367C_SSC_CTRL2_5_SSC_TEST_MODE_MASK 0xC +#define RTL8367C_SSC_CTRL2_5_SSC_PH_CFG_OFFSET 0 +#define RTL8367C_SSC_CTRL2_5_SSC_PH_CFG_MASK 0x3 + +#define RTL8367C_REG_SSC_STS2 0x1d58 +#define RTL8367C_SSC_STS2_OFS_BUSY_OFFSET 13 +#define RTL8367C_SSC_STS2_OFS_BUSY_MASK 0x2000 +#define RTL8367C_SSC_STS2_OFS_TOTAL_R_OFFSET 8 +#define RTL8367C_SSC_STS2_OFS_TOTAL_R_MASK 0x1F00 +#define RTL8367C_SSC_STS2_CNT_GRY0_OFFSET 4 +#define RTL8367C_SSC_STS2_CNT_GRY0_MASK 0xF0 +#define RTL8367C_SSC_STS2_OFS_GRY0_OFFSET 0 +#define RTL8367C_SSC_STS2_OFS_GRY0_MASK 0xF + +#define RTL8367C_REG_SSC_CTRL3_0 0x1d59 +#define RTL8367C_SSC_CTRL3_0_SSC_TYPE_OFFSET 13 +#define RTL8367C_SSC_CTRL3_0_SSC_TYPE_MASK 0x2000 +#define RTL8367C_SSC_CTRL3_0_PHASE_LIM_SEL_OFFSET 5 +#define RTL8367C_SSC_CTRL3_0_PHASE_LIM_SEL_MASK 0x1FE0 +#define RTL8367C_SSC_CTRL3_0_PHASE_LIM_EN_OFFSET 4 +#define RTL8367C_SSC_CTRL3_0_PHASE_LIM_EN_MASK 0x10 +#define RTL8367C_SSC_CTRL3_0_DLL_MODE_OFFSET 2 +#define RTL8367C_SSC_CTRL3_0_DLL_MODE_MASK 0xC +#define RTL8367C_SSC_CTRL3_0_SSC_EN_OFFSET 1 +#define RTL8367C_SSC_CTRL3_0_SSC_EN_MASK 0x2 +#define RTL8367C_SSC_CTRL3_0_SSC_MODE_OFFSET 0 +#define RTL8367C_SSC_CTRL3_0_SSC_MODE_MASK 0x1 + +#define RTL8367C_REG_SSC_RDM_SEED3 0x1d5a + +#define RTL8367C_REG_SSC_PN_POLY_SEL3 0x1d5b + +#define RTL8367C_REG_SSC_CTRL3_3 0x1d5c +#define RTL8367C_SSC_CTRL3_3_PHSFT_CNT_OFFSET 8 +#define RTL8367C_SSC_CTRL3_3_PHSFT_CNT_MASK 0x7F00 +#define RTL8367C_SSC_CTRL3_3_PHSFT_A_OFFSET 7 +#define RTL8367C_SSC_CTRL3_3_PHSFT_A_MASK 0x80 +#define RTL8367C_SSC_CTRL3_3_PHSFT_B_OFFSET 6 +#define RTL8367C_SSC_CTRL3_3_PHSFT_B_MASK 0x40 +#define RTL8367C_SSC_CTRL3_3_PHSFT_UPDN_OFFSET 5 +#define RTL8367C_SSC_CTRL3_3_PHSFT_UPDN_MASK 0x20 +#define RTL8367C_SSC_CTRL3_3_PHSFT_PRD_OFFSET 4 +#define RTL8367C_SSC_CTRL3_3_PHSFT_PRD_MASK 0x10 +#define RTL8367C_SSC_CTRL3_3_PN_POLY_DEG_OFFSET 0 +#define RTL8367C_SSC_CTRL3_3_PN_POLY_DEG_MASK 0xF + +#define RTL8367C_REG_SSC_CTRL3_4 0x1d5d +#define RTL8367C_SSC_CTRL3_4_SSC_UP1DN0_OFFSET 15 +#define RTL8367C_SSC_CTRL3_4_SSC_UP1DN0_MASK 0x8000 +#define RTL8367C_SSC_CTRL3_4_SSC_PERIOD_OFFSET 8 +#define RTL8367C_SSC_CTRL3_4_SSC_PERIOD_MASK 0x7F00 +#define RTL8367C_SSC_CTRL3_4_SSC_OFFSET_OFFSET 0 +#define RTL8367C_SSC_CTRL3_4_SSC_OFFSET_MASK 0xFF + +#define RTL8367C_REG_SSC_CTRL3_5 0x1d5e +#define RTL8367C_SSC_CTRL3_5_PH_OFS_TOG_OFFSET 15 +#define RTL8367C_SSC_CTRL3_5_PH_OFS_TOG_MASK 0x8000 +#define RTL8367C_SSC_CTRL3_5_PH_OFS_OFFSET 10 +#define RTL8367C_SSC_CTRL3_5_PH_OFS_MASK 0x7C00 +#define RTL8367C_SSC_CTRL3_5_SSC_STEP_OFFSET 4 +#define RTL8367C_SSC_CTRL3_5_SSC_STEP_MASK 0x3F0 +#define RTL8367C_SSC_CTRL3_5_SSC_TEST_MODE_OFFSET 2 +#define RTL8367C_SSC_CTRL3_5_SSC_TEST_MODE_MASK 0xC +#define RTL8367C_SSC_CTRL3_5_SSC_PH_CFG_OFFSET 0 +#define RTL8367C_SSC_CTRL3_5_SSC_PH_CFG_MASK 0x3 + +#define RTL8367C_REG_SSC_STS3 0x1d5f +#define RTL8367C_SSC_STS3_OFS_BUSY_OFFSET 13 +#define RTL8367C_SSC_STS3_OFS_BUSY_MASK 0x2000 +#define RTL8367C_SSC_STS3_OFS_TOTAL_R_OFFSET 8 +#define RTL8367C_SSC_STS3_OFS_TOTAL_R_MASK 0x1F00 +#define RTL8367C_SSC_STS3_CNT_GRY0_OFFSET 4 +#define RTL8367C_SSC_STS3_CNT_GRY0_MASK 0xF0 +#define RTL8367C_SSC_STS3_OFS_GRY0_OFFSET 0 +#define RTL8367C_SSC_STS3_OFS_GRY0_MASK 0xF + +#define RTL8367C_REG_PHY_POLL_CFG13 0x1d60 + +#define RTL8367C_REG_PHY_POLL_CFG14 0x1d61 + +#define RTL8367C_REG_FRC_SYS_CLK 0x1d62 +#define RTL8367C_SYSCLK_FRC_MD_OFFSET 1 +#define RTL8367C_SYSCLK_FRC_MD_MASK 0x2 +#define RTL8367C_SYSCLK_FRC_VAL_OFFSET 0 +#define RTL8367C_SYSCLK_FRC_VAL_MASK 0x1 + +#define RTL8367C_REG_AFE_SSC_CTRL 0x1d63 +#define RTL8367C_PH_RSTB_TXD1_OFFSET 9 +#define RTL8367C_PH_RSTB_TXD1_MASK 0x200 +#define RTL8367C_PH_RSTB_TXC1_OFFSET 8 +#define RTL8367C_PH_RSTB_TXC1_MASK 0x100 +#define RTL8367C_PH_RSTB_TXD0_OFFSET 7 +#define RTL8367C_PH_RSTB_TXD0_MASK 0x80 +#define RTL8367C_PH_RSTB_TXC0_OFFSET 6 +#define RTL8367C_PH_RSTB_TXC0_MASK 0x40 +#define RTL8367C_PH_RSTBSYS_OFFSET 5 +#define RTL8367C_PH_RSTBSYS_MASK 0x20 +#define RTL8367C_PH_RSTB8051_OFFSET 4 +#define RTL8367C_PH_RSTB8051_MASK 0x10 +#define RTL8367C_OREG_SSC_OFFSET 0 +#define RTL8367C_OREG_SSC_MASK 0xF + +#define RTL8367C_REG_BUFF_RST_CTRL0 0x1d64 +#define RTL8367C_BUFFRST_TXESD_EN_OFFSET 13 +#define RTL8367C_BUFFRST_TXESD_EN_MASK 0x2000 +#define RTL8367C_BUFF_RST_TIME_LONG_OFFSET 8 +#define RTL8367C_BUFF_RST_TIME_LONG_MASK 0x1F00 +#define RTL8367C_BUFF_RST_TIME_SHORT_OFFSET 3 +#define RTL8367C_BUFF_RST_TIME_SHORT_MASK 0xF8 +#define RTL8367C_SW_BUFF_RST_OFFSET 2 +#define RTL8367C_SW_BUFF_RST_MASK 0x4 +#define RTL8367C_IMS_BUFF_RST_OFFSET 1 +#define RTL8367C_IMS_BUFF_RST_MASK 0x2 +#define RTL8367C_IMR_BUFF_RST_OFFSET 0 +#define RTL8367C_IMR_BUFF_RST_MASK 0x1 + +#define RTL8367C_REG_BUFF_RST_CTRL1 0x1d65 +#define RTL8367C_BUFFRST_SYSOVER_EN_OFFSET 10 +#define RTL8367C_BUFFRST_SYSOVER_EN_MASK 0x400 +#define RTL8367C_BUFFRST_SYSOVER_THR_OFFSET 0 +#define RTL8367C_BUFFRST_SYSOVER_THR_MASK 0x3FF + +#define RTL8367C_REG_BUFF_RST_CTRL2 0x1d66 +#define RTL8367C_BUFFRST_QOVER_EN_OFFSET 10 +#define RTL8367C_BUFFRST_QOVER_EN_MASK 0x400 +#define RTL8367C_BUFFRST_QOVER_THR_OFFSET 0 +#define RTL8367C_BUFFRST_QOVER_THR_MASK 0x3FF + +#define RTL8367C_REG_BUFF_RST_CTRL3 0x1d67 +#define RTL8367C_DSC_TIMER_OFFSET 11 +#define RTL8367C_DSC_TIMER_MASK 0x7800 +#define RTL8367C_BUFFRST_DSCOVER_THR_OFFSET 1 +#define RTL8367C_BUFFRST_DSCOVER_THR_MASK 0x7FE +#define RTL8367C_BUFFRST_DSCOVER_EN_OFFSET 0 +#define RTL8367C_BUFFRST_DSCOVER_EN_MASK 0x1 + +#define RTL8367C_REG_BUFF_RST_CTRL4 0x1d68 +#define RTL8367C_INDSC_TIMER_OFFSET 11 +#define RTL8367C_INDSC_TIMER_MASK 0x7800 +#define RTL8367C_BUFFRST_INDSCOVER_THR_OFFSET 1 +#define RTL8367C_BUFFRST_INDSCOVER_THR_MASK 0x7FE +#define RTL8367C_BUFFRST_INDSCOVER_EN_OFFSET 0 +#define RTL8367C_BUFFRST_INDSCOVER_EN_MASK 0x1 + +#define RTL8367C_REG_BUFF_RST_CTRL5 0x1d69 +#define RTL8367C_TX_ESD_MODE_OFFSET 8 +#define RTL8367C_TX_ESD_MODE_MASK 0x100 +#define RTL8367C_TX_ESD_LVL_OFFSET 0 +#define RTL8367C_TX_ESD_LVL_MASK 0xFF + +#define RTL8367C_REG_TOP_CON0 0x1d70 +#define RTL8367C_TOP_CON0_SDS_PWR_ISO_1_OFFSET 15 +#define RTL8367C_TOP_CON0_SDS_PWR_ISO_1_MASK 0x8000 +#define RTL8367C_OCP_TIMEOUT_P7_5_OFFSET 12 +#define RTL8367C_OCP_TIMEOUT_P7_5_MASK 0x7000 +#define RTL8367C_FIB_EEE_AB_OFFSET 11 +#define RTL8367C_FIB_EEE_AB_MASK 0x800 +#define RTL8367C_ADCCKIEN_OFFSET 10 +#define RTL8367C_ADCCKIEN_MASK 0x400 +#define RTL8367C_OCP_TIMEOUT_OFFSET 5 +#define RTL8367C_OCP_TIMEOUT_MASK 0x3E0 +#define RTL8367C_TOP_CON0_SDS_PWR_ISO_OFFSET 4 +#define RTL8367C_TOP_CON0_SDS_PWR_ISO_MASK 0x10 +#define RTL8367C_RG2_TXC_SEL_OFFSET 3 +#define RTL8367C_RG2_TXC_SEL_MASK 0x8 +#define RTL8367C_RG1TXC_SEL_OFFSET 2 +#define RTL8367C_RG1TXC_SEL_MASK 0x4 +#define RTL8367C_SYNC_1588_EN_OFFSET 1 +#define RTL8367C_SYNC_1588_EN_MASK 0x2 +#define RTL8367C_LS_MODE_OFFSET 0 +#define RTL8367C_LS_MODE_MASK 0x1 + +#define RTL8367C_REG_TOP_CON1 0x1d71 +#define RTL8367C_TA_CHK_EN_OFFSET 2 +#define RTL8367C_TA_CHK_EN_MASK 0x4 +#define RTL8367C_SLV_EG_SEL_OFFSET 1 +#define RTL8367C_SLV_EG_SEL_MASK 0x2 +#define RTL8367C_IIC_OP_DRAIN_OFFSET 0 +#define RTL8367C_IIC_OP_DRAIN_MASK 0x1 + +#define RTL8367C_REG_SWR_FPWM 0x1d72 +#define RTL8367C_SWR_FPWM_OFFSET 0 +#define RTL8367C_SWR_FPWM_MASK 0x1 + +#define RTL8367C_REG_EEEP_CTRL_500M 0x1d73 + +#define RTL8367C_REG_SHORT_PRMB 0x1d74 +#define RTL8367C_SHORT_PRMB_OFFSET 0 +#define RTL8367C_SHORT_PRMB_MASK 0x1 + +#define RTL8367C_REG_INDSC_THR_CTRL 0x1d75 +#define RTL8367C_INDSC_THR_CTRL_OFFSET 0 +#define RTL8367C_INDSC_THR_CTRL_MASK 0x7FF + +#define RTL8367C_REG_SET_PAD_CTRL_NEW 0x1d80 +#define RTL8367C_SET_PAD_CTRL_NEW_OFFSET 0 +#define RTL8367C_SET_PAD_CTRL_NEW_MASK 0x1 + +#define RTL8367C_REG_SET_PAD_DRI_0 0x1d81 + +#define RTL8367C_REG_SET_PAD_DRI_1 0x1d82 + +#define RTL8367C_REG_SET_PAD_DRI_2 0x1d83 + +#define RTL8367C_REG_SET_PAD_SLEW_0 0x1d84 + +#define RTL8367C_REG_SET_PAD_SLEW_1 0x1d85 + +#define RTL8367C_REG_SET_PAD_SLEW_2 0x1d86 + +#define RTL8367C_REG_SET_PAD_SMT_0 0x1d87 + +#define RTL8367C_REG_SET_PAD_SMT_1 0x1d88 + +#define RTL8367C_REG_SET_PAD_SMT_2 0x1d89 + +#define RTL8367C_REG_M_I2C_CTL_STA_REG 0x1d8a +#define RTL8367C_TX_RX_DATA_OFFSET 8 +#define RTL8367C_TX_RX_DATA_MASK 0xFF00 +#define RTL8367C_DUMB_RW_ERR_OFFSET 7 +#define RTL8367C_DUMB_RW_ERR_MASK 0x80 +#define RTL8367C_SLV_ACK_FLAG_OFFSET 6 +#define RTL8367C_SLV_ACK_FLAG_MASK 0x40 +#define RTL8367C_M_I2C_BUS_IDLE_OFFSET 5 +#define RTL8367C_M_I2C_BUS_IDLE_MASK 0x20 +#define RTL8367C_I2C_CMD_TYPE_OFFSET 1 +#define RTL8367C_I2C_CMD_TYPE_MASK 0x1E +#define RTL8367C_I2C_CMD_EXEC_OFFSET 0 +#define RTL8367C_I2C_CMD_EXEC_MASK 0x1 + +#define RTL8367C_REG_M_I2C_DUMB_RW_ADDR_0 0x1d8b + +#define RTL8367C_REG_M_I2C_DUMB_RW_ADDR_1 0x1d8c + +#define RTL8367C_REG_M_I2C_DUMB_RW_DATA_0 0x1d8d + +#define RTL8367C_REG_M_I2C_DUMB_RW_DATA_1 0x1d8e + +#define RTL8367C_REG_M_I2C_DUMB_RW_CTL 0x1d8f +#define RTL8367C_DUMB_I2C_CTL_CODE_OFFSET 8 +#define RTL8367C_DUMB_I2C_CTL_CODE_MASK 0x7F00 +#define RTL8367C_DUMB_RW_I2C_FORMAT_OFFSET 4 +#define RTL8367C_DUMB_RW_I2C_FORMAT_MASK 0x10 +#define RTL8367C_DUMB_RW_DATA_MODE_OFFSET 2 +#define RTL8367C_DUMB_RW_DATA_MODE_MASK 0xC +#define RTL8367C_DUMB_RW_ADDR_MODE_OFFSET 0 +#define RTL8367C_DUMB_RW_ADDR_MODE_MASK 0x3 + +#define RTL8367C_REG_M_I2C_SYS_CTL 0x1d90 +#define RTL8367C_M_I2C_SCL_IO_MUX_OFFSET 12 +#define RTL8367C_M_I2C_SCL_IO_MUX_MASK 0x3000 +#define RTL8367C_M_I2C_SDA_IO_MUX_OFFSET 10 +#define RTL8367C_M_I2C_SDA_IO_MUX_MASK 0xC00 +#define RTL8367C_M_I2C_SDA_OD_EN_OFFSET 9 +#define RTL8367C_M_I2C_SDA_OD_EN_MASK 0x200 +#define RTL8367C_M_I2C_SCL_OD_EN_OFFSET 8 +#define RTL8367C_M_I2C_SCL_OD_EN_MASK 0x100 +#define RTL8367C_M_I2C_SCL_F_DIV_OFFSET 0 +#define RTL8367C_M_I2C_SCL_F_DIV_MASK 0xFF + +#define RTL8367C_REG_HT_PB_SRAM_CTRL 0x1da0 +#define RTL8367C_HTPB_RW_OFFSET 2 +#define RTL8367C_HTPB_RW_MASK 0x4 +#define RTL8367C_HTPB_SEL_OFFSET 1 +#define RTL8367C_HTPB_SEL_MASK 0x2 +#define RTL8367C_HTPB_CE_OFFSET 0 +#define RTL8367C_HTPB_CE_MASK 0x1 + +#define RTL8367C_REG_HT_PB_SRAM_ADDR 0x1da1 + +#define RTL8367C_REG_HT_PB_SRAM_DIN0 0x1da2 + +#define RTL8367C_REG_HT_PB_SRAM_DIN1 0x1da3 + +#define RTL8367C_REG_HT_PB_SRAM_DOUT0 0x1da4 + +#define RTL8367C_REG_HT_PB_SRAM_DOUT1 0x1da5 + +#define RTL8367C_REG_PHY_STAT_0 0x1db0 + +#define RTL8367C_REG_PHY_STAT_1 0x1db1 + +#define RTL8367C_REG_PHY_STAT_2 0x1db2 + +#define RTL8367C_REG_PHY_STAT_3 0x1db3 + +#define RTL8367C_REG_PHY_STAT_4 0x1db4 + +#define RTL8367C_REG_PHY_STAT_5 0x1db5 + +#define RTL8367C_REG_PHY_STAT_6 0x1db6 + +#define RTL8367C_REG_PHY_STAT_7 0x1db7 + +#define RTL8367C_REG_SDS_STAT_0 0x1db8 + +#define RTL8367C_REG_SDS_STAT_1 0x1db9 + +#define RTL8367C_REG_MAC_LINK_STAT_0 0x1dba +#define RTL8367C_MAC_LINK_STAT_CUR_0_OFFSET 8 +#define RTL8367C_MAC_LINK_STAT_CUR_0_MASK 0xFF00 +#define RTL8367C_MAC_LINK_STAT_LATCH_0_OFFSET 0 +#define RTL8367C_MAC_LINK_STAT_LATCH_0_MASK 0xFF + +#define RTL8367C_REG_MAC_LINK_STAT_1 0x1dbb +#define RTL8367C_MAC_LINK_STAT_1_Reserved_OFFSET 6 +#define RTL8367C_MAC_LINK_STAT_1_Reserved_MASK 0xFFC0 +#define RTL8367C_MAC_LINK_STAT_CUR_1_OFFSET 3 +#define RTL8367C_MAC_LINK_STAT_CUR_1_MASK 0x38 +#define RTL8367C_MAC_LINK_STAT_LATCH_1_OFFSET 0 +#define RTL8367C_MAC_LINK_STAT_LATCH_1_MASK 0x7 + +#define RTL8367C_REG_MISC_CONTROL_1 0x1dc0 +#define RTL8367C_P7_FB_CPL_OFFSET 2 +#define RTL8367C_P7_FB_CPL_MASK 0x4 +#define RTL8367C_P6_FB_CPL_OFFSET 1 +#define RTL8367C_P6_FB_CPL_MASK 0x2 +#define RTL8367C_P5_FB_CPL_OFFSET 0 +#define RTL8367C_P5_FB_CPL_MASK 0x1 + +#define RTL8367C_REG_SDS_MISC_1 0x1dc1 +#define RTL8367C_CFG_SGMII_RXFC_1_OFFSET 14 +#define RTL8367C_CFG_SGMII_RXFC_1_MASK 0x4000 +#define RTL8367C_CFG_SGMII_TXFC_1_OFFSET 13 +#define RTL8367C_CFG_SGMII_TXFC_1_MASK 0x2000 +#define RTL8367C_CFG_MAC9_SEL_HSGMII_OFFSET 11 +#define RTL8367C_CFG_MAC9_SEL_HSGMII_MASK 0x800 +#define RTL8367C_CFG_SGMII_FDUP_1_OFFSET 10 +#define RTL8367C_CFG_SGMII_FDUP_1_MASK 0x400 +#define RTL8367C_CFG_SGMII_LINK_1_OFFSET 9 +#define RTL8367C_CFG_SGMII_LINK_1_MASK 0x200 +#define RTL8367C_CFG_SGMII_SPD_1_OFFSET 7 +#define RTL8367C_CFG_SGMII_SPD_1_MASK 0x180 +#define RTL8367C_CFG_MAC9_SEL_SGMII_OFFSET 6 +#define RTL8367C_CFG_MAC9_SEL_SGMII_MASK 0x40 +#define RTL8367C_CFG_SDS_MODE_14C_1_OFFSET 0 +#define RTL8367C_CFG_SDS_MODE_14C_1_MASK 0x7 + +#define RTL8367C_REG_FIBER_CFG_2_1 0x1dc2 +#define RTL8367C_SDS_RX_DISABLE_1_OFFSET 6 +#define RTL8367C_SDS_RX_DISABLE_1_MASK 0xC0 +#define RTL8367C_SDS_TX_DISABLE_1_OFFSET 4 +#define RTL8367C_SDS_TX_DISABLE_1_MASK 0x30 +#define RTL8367C_FIBER_CFG_2_1_SDS_PWR_ISO_1_OFFSET 2 +#define RTL8367C_FIBER_CFG_2_1_SDS_PWR_ISO_1_MASK 0xC +#define RTL8367C_SDS_FRC_LD_1_OFFSET 0 +#define RTL8367C_SDS_FRC_LD_1_MASK 0x3 + +#define RTL8367C_REG_FIBER_CFG_1_1 0x1dc3 +#define RTL8367C_SDS_FRC_REG4_1_OFFSET 12 +#define RTL8367C_SDS_FRC_REG4_1_MASK 0x1000 +#define RTL8367C_SDS_FRC_REG4_FIB100_1_OFFSET 11 +#define RTL8367C_SDS_FRC_REG4_FIB100_1_MASK 0x800 +#define RTL8367C_SDS_FRC_MODE_1_OFFSET 3 +#define RTL8367C_SDS_FRC_MODE_1_MASK 0x8 +#define RTL8367C_SDS_MODE_1_OFFSET 0 +#define RTL8367C_SDS_MODE_1_MASK 0x7 + +#define RTL8367C_REG_PHYSTS_CTRL0_1 0x1dc4 +#define RTL8367C_LNKUP_DLY_EN_EXT2_OFFSET 9 +#define RTL8367C_LNKUP_DLY_EN_EXT2_MASK 0x200 +#define RTL8367C_GE_100M_LNKUP_DLY_EXT2_OFFSET 7 +#define RTL8367C_GE_100M_LNKUP_DLY_EXT2_MASK 0x180 +#define RTL8367C_PHYSTS_10M_LNKUP_DLY_EXT2_OFFSET 5 +#define RTL8367C_PHYSTS_10M_LNKUP_DLY_EXT2_MASK 0x60 +#define RTL8367C_LNKUP_DLY_EN_EXT1_OFFSET 4 +#define RTL8367C_LNKUP_DLY_EN_EXT1_MASK 0x10 +#define RTL8367C_GE_100M_LNKUP_DLY_EXT1_OFFSET 2 +#define RTL8367C_GE_100M_LNKUP_DLY_EXT1_MASK 0xC +#define RTL8367C_PHYSTS_10M_LNKUP_DLY_EXT1_OFFSET 0 +#define RTL8367C_PHYSTS_10M_LNKUP_DLY_EXT1_MASK 0x3 + +#define RTL8367C_REG_FIBER_CFG_3_1 0x1dc5 +#define RTL8367C_FIBER_CFG_3_1_OFFSET 0 +#define RTL8367C_FIBER_CFG_3_1_MASK 0xFFF + +#define RTL8367C_REG_FIBER_CFG_4_1 0x1dc6 + +#define RTL8367C_REG_BUFF_RST_CTRL2_2 0x1dc7 +#define RTL8367C_Cfg_buffrst_sysover_thr_1_OFFSET 3 +#define RTL8367C_Cfg_buffrst_sysover_thr_1_MASK 0x8 +#define RTL8367C_Cfg_buffrst_qover_thr_OFFSET 2 +#define RTL8367C_Cfg_buffrst_qover_thr_MASK 0x4 +#define RTL8367C_Cfg_buffrst_indscover_thr_1_OFFSET 1 +#define RTL8367C_Cfg_buffrst_indscover_thr_1_MASK 0x2 +#define RTL8367C_Cfg_buffrst_dscover_thr_1_OFFSET 0 +#define RTL8367C_Cfg_buffrst_dscover_thr_1_MASK 0x1 + +#define RTL8367C_REG_PHY_DEBUG_CNT_CTRL 0x1dc8 +#define RTL8367C_PHY_MIB_RST_7_OFFSET 15 +#define RTL8367C_PHY_MIB_RST_7_MASK 0x8000 +#define RTL8367C_PHY_MIB_RST_6_OFFSET 14 +#define RTL8367C_PHY_MIB_RST_6_MASK 0x4000 +#define RTL8367C_PHY_MIB_RST_5_OFFSET 13 +#define RTL8367C_PHY_MIB_RST_5_MASK 0x2000 +#define RTL8367C_PHY_MIB_RST_4_OFFSET 12 +#define RTL8367C_PHY_MIB_RST_4_MASK 0x1000 +#define RTL8367C_PHY_MIB_RST_3_OFFSET 11 +#define RTL8367C_PHY_MIB_RST_3_MASK 0x800 +#define RTL8367C_PHY_MIB_RST_2_OFFSET 10 +#define RTL8367C_PHY_MIB_RST_2_MASK 0x400 +#define RTL8367C_PHY_MIB_RST_1_OFFSET 9 +#define RTL8367C_PHY_MIB_RST_1_MASK 0x200 +#define RTL8367C_PHY_MIB_RST_0_OFFSET 8 +#define RTL8367C_PHY_MIB_RST_0_MASK 0x100 +#define RTL8367C_PHY_MIB_EN_7_OFFSET 7 +#define RTL8367C_PHY_MIB_EN_7_MASK 0x80 +#define RTL8367C_PHY_MIB_EN_6_OFFSET 6 +#define RTL8367C_PHY_MIB_EN_6_MASK 0x40 +#define RTL8367C_PHY_MIB_EN_5_OFFSET 5 +#define RTL8367C_PHY_MIB_EN_5_MASK 0x20 +#define RTL8367C_PHY_MIB_EN_4_OFFSET 4 +#define RTL8367C_PHY_MIB_EN_4_MASK 0x10 +#define RTL8367C_PHY_MIB_EN_3_OFFSET 3 +#define RTL8367C_PHY_MIB_EN_3_MASK 0x8 +#define RTL8367C_PHY_MIB_EN_2_OFFSET 2 +#define RTL8367C_PHY_MIB_EN_2_MASK 0x4 +#define RTL8367C_PHY_MIB_EN_1_OFFSET 1 +#define RTL8367C_PHY_MIB_EN_1_MASK 0x2 +#define RTL8367C_PHY_MIB_EN_0_OFFSET 0 +#define RTL8367C_PHY_MIB_EN_0_MASK 0x1 + +#define RTL8367C_REG_TXPKT_CNT_L_0 0x1dc9 + +#define RTL8367C_REG_TXPKT_CNT_H_0 0x1dca + +#define RTL8367C_REG_RXPKT_CNT_L_0 0x1dcb + +#define RTL8367C_REG_RXPKT_CNT_H_0 0x1dcc + +#define RTL8367C_REG_TX_CRC_0 0x1dcd + +#define RTL8367C_REG_RX_CRC_0 0x1dce + +#define RTL8367C_REG_TXPKT_CNT_L_1 0x1dcf + +#define RTL8367C_REG_TXPKT_CNT_H_1 0x1dd0 + +#define RTL8367C_REG_RXPKT_CNT_L_1 0x1dd1 + +#define RTL8367C_REG_RXPKT_CNT_H_1 0x1dd2 + +#define RTL8367C_REG_TX_CRC_1 0x1dd3 + +#define RTL8367C_REG_RX_CRC_1 0x1dd4 + +#define RTL8367C_REG_TXPKT_CNT_L_2 0x1dd5 + +#define RTL8367C_REG_TXPKT_CNT_H_2 0x1dd6 + +#define RTL8367C_REG_RXPKT_CNT_L_2 0x1dd7 + +#define RTL8367C_REG_RXPKT_CNT_H_2 0x1dd8 + +#define RTL8367C_REG_TX_CRC_2 0x1dd9 + +#define RTL8367C_REG_RX_CRC_2 0x1dda + +#define RTL8367C_REG_TXPKT_CNT_L_3 0x1ddb + +#define RTL8367C_REG_TXPKT_CNT_H_3 0x1ddc + +#define RTL8367C_REG_RXPKT_CNT_L_3 0x1ddd + +#define RTL8367C_REG_RXPKT_CNT_H_3 0x1dde + +#define RTL8367C_REG_TX_CRC_3 0x1ddf + +#define RTL8367C_REG_RX_CRC_3 0x1de0 + +#define RTL8367C_REG_TXPKT_CNT_L_4 0x1de1 + +#define RTL8367C_REG_TXPKT_CNT_H_4 0x1de2 + +#define RTL8367C_REG_RXPKT_CNT_L_4 0x1de3 + +#define RTL8367C_REG_RXPKT_CNT_H_4 0x1de4 + +#define RTL8367C_REG_TX_CRC_4 0x1de5 + +#define RTL8367C_REG_RX_CRC_4 0x1de6 + +#define RTL8367C_REG_TXPKT_CNT_L_5 0x1de7 + +#define RTL8367C_REG_TXPKT_CNT_H_5 0x1de8 + +#define RTL8367C_REG_RXPKT_CNT_L_5 0x1de9 + +#define RTL8367C_REG_RXPKT_CNT_H_5 0x1dea + +#define RTL8367C_REG_TX_CRC_5 0x1deb + +#define RTL8367C_REG_RX_CRC_5 0x1dec + +#define RTL8367C_REG_TXPKT_CNT_L_6 0x1ded + +#define RTL8367C_REG_TXPKT_CNT_H_6 0x1dee + +#define RTL8367C_REG_RXPKT_CNT_L_6 0x1def + +#define RTL8367C_REG_RXPKT_CNT_H_6 0x1df0 + +#define RTL8367C_REG_TX_CRC_6 0x1df1 + +#define RTL8367C_REG_RX_CRC_6 0x1df2 + +#define RTL8367C_REG_TXPKT_CNT_L_7 0x1df3 + +#define RTL8367C_REG_TXPKT_CNT_H_7 0x1df4 + +#define RTL8367C_REG_RXPKT_CNT_L_7 0x1df5 + +#define RTL8367C_REG_RXPKT_CNT_H_7 0x1df6 + +#define RTL8367C_REG_TX_CRC_7 0x1df7 + +#define RTL8367C_REG_RX_CRC_7 0x1df8 + +#define RTL8367C_REG_BOND_DBG_0 0x1df9 + +#define RTL8367C_REG_BOND_DBG_1 0x1dfa + +#define RTL8367C_REG_STRP_DBG_0 0x1dfb + +#define RTL8367C_REG_STRP_DBG_1 0x1dfc + +#define RTL8367C_REG_STRP_DBG_2 0x1dfd + +/* (16'h1f00)patch_reg */ + +#define RTL8367C_REG_INDRECT_ACCESS_CTRL 0x1f00 +#define RTL8367C_RW_OFFSET 1 +#define RTL8367C_RW_MASK 0x2 +#define RTL8367C_CMD_OFFSET 0 +#define RTL8367C_CMD_MASK 0x1 + +#define RTL8367C_REG_INDRECT_ACCESS_STATUS 0x1f01 +#define RTL8367C_INDRECT_ACCESS_STATUS_OFFSET 2 +#define RTL8367C_INDRECT_ACCESS_STATUS_MASK 0x7 + +#define RTL8367C_REG_INDRECT_ACCESS_ADDRESS 0x1f02 + +#define RTL8367C_REG_INDRECT_ACCESS_WRITE_DATA 0x1f03 + +#define RTL8367C_REG_INDRECT_ACCESS_READ_DATA 0x1f04 + +/* (16'h6200)fib_page */ + +#define RTL8367C_REG_FIB0_CFG00 0x6200 +#define RTL8367C_FIB0_CFG00_CFG_FIB_RST_OFFSET 15 +#define RTL8367C_FIB0_CFG00_CFG_FIB_RST_MASK 0x8000 +#define RTL8367C_FIB0_CFG00_CFG_FIB_LPK_OFFSET 14 +#define RTL8367C_FIB0_CFG00_CFG_FIB_LPK_MASK 0x4000 +#define RTL8367C_FIB0_CFG00_CFG_FIB_SPD_RD_0_OFFSET 13 +#define RTL8367C_FIB0_CFG00_CFG_FIB_SPD_RD_0_MASK 0x2000 +#define RTL8367C_FIB0_CFG00_CFG_FIB_ANEN_OFFSET 12 +#define RTL8367C_FIB0_CFG00_CFG_FIB_ANEN_MASK 0x1000 +#define RTL8367C_FIB0_CFG00_CFG_FIB_PDOWN_OFFSET 11 +#define RTL8367C_FIB0_CFG00_CFG_FIB_PDOWN_MASK 0x800 +#define RTL8367C_FIB0_CFG00_CFG_FIB_ISO_OFFSET 10 +#define RTL8367C_FIB0_CFG00_CFG_FIB_ISO_MASK 0x400 +#define RTL8367C_FIB0_CFG00_CFG_FIB_RESTART_OFFSET 9 +#define RTL8367C_FIB0_CFG00_CFG_FIB_RESTART_MASK 0x200 +#define RTL8367C_FIB0_CFG00_CFG_FIB_FULLDUP_OFFSET 8 +#define RTL8367C_FIB0_CFG00_CFG_FIB_FULLDUP_MASK 0x100 +#define RTL8367C_FIB0_CFG00_CFG_FIB_SPD_RD_1_OFFSET 6 +#define RTL8367C_FIB0_CFG00_CFG_FIB_SPD_RD_1_MASK 0x40 +#define RTL8367C_FIB0_CFG00_CFG_FIB_FRCTX_OFFSET 5 +#define RTL8367C_FIB0_CFG00_CFG_FIB_FRCTX_MASK 0x20 + +#define RTL8367C_REG_FIB0_CFG01 0x6201 +#define RTL8367C_FIB0_CFG01_CAPBILITY_OFFSET 6 +#define RTL8367C_FIB0_CFG01_CAPBILITY_MASK 0xFFC0 +#define RTL8367C_FIB0_CFG01_AN_COMPLETE_OFFSET 5 +#define RTL8367C_FIB0_CFG01_AN_COMPLETE_MASK 0x20 +#define RTL8367C_FIB0_CFG01_R_FAULT_OFFSET 4 +#define RTL8367C_FIB0_CFG01_R_FAULT_MASK 0x10 +#define RTL8367C_FIB0_CFG01_NWAY_ABILITY_OFFSET 3 +#define RTL8367C_FIB0_CFG01_NWAY_ABILITY_MASK 0x8 +#define RTL8367C_FIB0_CFG01_LINK_STATUS_OFFSET 2 +#define RTL8367C_FIB0_CFG01_LINK_STATUS_MASK 0x4 +#define RTL8367C_FIB0_CFG01_JABBER_DETECT_OFFSET 1 +#define RTL8367C_FIB0_CFG01_JABBER_DETECT_MASK 0x2 +#define RTL8367C_FIB0_CFG01_EXTENDED_CAPBILITY_OFFSET 0 +#define RTL8367C_FIB0_CFG01_EXTENDED_CAPBILITY_MASK 0x1 + +#define RTL8367C_REG_FIB0_CFG02 0x6202 + +#define RTL8367C_REG_FIB0_CFG03 0x6203 +#define RTL8367C_FIB0_CFG03_REALTEK_OUI5_0_OFFSET 10 +#define RTL8367C_FIB0_CFG03_REALTEK_OUI5_0_MASK 0xFC00 +#define RTL8367C_FIB0_CFG03_MODEL_NO_OFFSET 4 +#define RTL8367C_FIB0_CFG03_MODEL_NO_MASK 0x3F0 +#define RTL8367C_FIB0_CFG03_REVISION_NO_OFFSET 0 +#define RTL8367C_FIB0_CFG03_REVISION_NO_MASK 0xF + +#define RTL8367C_REG_FIB0_CFG04 0x6204 + +#define RTL8367C_REG_FIB0_CFG05 0x6205 + +#define RTL8367C_REG_FIB0_CFG06 0x6206 +#define RTL8367C_FIB0_CFG06_FIB_NP_EN_OFFSET 2 +#define RTL8367C_FIB0_CFG06_FIB_NP_EN_MASK 0x4 +#define RTL8367C_FIB0_CFG06_RXPAGE_OFFSET 1 +#define RTL8367C_FIB0_CFG06_RXPAGE_MASK 0x2 + +#define RTL8367C_REG_FIB0_CFG07 0x6207 + +#define RTL8367C_REG_FIB0_CFG08 0x6208 + +#define RTL8367C_REG_FIB0_CFG09 0x6209 + +#define RTL8367C_REG_FIB0_CFG10 0x620a + +#define RTL8367C_REG_FIB0_CFG11 0x620b + +#define RTL8367C_REG_FIB0_CFG12 0x620c + +#define RTL8367C_REG_FIB0_CFG13 0x620d +#define RTL8367C_FIB0_CFG13_INDR_FUNC_OFFSET 14 +#define RTL8367C_FIB0_CFG13_INDR_FUNC_MASK 0xC000 +#define RTL8367C_FIB0_CFG13_DUMMY_OFFSET 5 +#define RTL8367C_FIB0_CFG13_DUMMY_MASK 0x3FE0 +#define RTL8367C_FIB0_CFG13_INDR_DEVAD_OFFSET 0 +#define RTL8367C_FIB0_CFG13_INDR_DEVAD_MASK 0x1F + +#define RTL8367C_REG_FIB0_CFG14 0x620e + +#define RTL8367C_REG_FIB0_CFG15 0x620f + +#define RTL8367C_REG_FIB1_CFG00 0x6210 +#define RTL8367C_FIB1_CFG00_CFG_FIB_RST_OFFSET 15 +#define RTL8367C_FIB1_CFG00_CFG_FIB_RST_MASK 0x8000 +#define RTL8367C_FIB1_CFG00_CFG_FIB_LPK_OFFSET 14 +#define RTL8367C_FIB1_CFG00_CFG_FIB_LPK_MASK 0x4000 +#define RTL8367C_FIB1_CFG00_CFG_FIB_SPD_RD_0_OFFSET 13 +#define RTL8367C_FIB1_CFG00_CFG_FIB_SPD_RD_0_MASK 0x2000 +#define RTL8367C_FIB1_CFG00_CFG_FIB_ANEN_OFFSET 12 +#define RTL8367C_FIB1_CFG00_CFG_FIB_ANEN_MASK 0x1000 +#define RTL8367C_FIB1_CFG00_CFG_FIB_PDOWN_OFFSET 11 +#define RTL8367C_FIB1_CFG00_CFG_FIB_PDOWN_MASK 0x800 +#define RTL8367C_FIB1_CFG00_CFG_FIB_ISO_OFFSET 10 +#define RTL8367C_FIB1_CFG00_CFG_FIB_ISO_MASK 0x400 +#define RTL8367C_FIB1_CFG00_CFG_FIB_RESTART_OFFSET 9 +#define RTL8367C_FIB1_CFG00_CFG_FIB_RESTART_MASK 0x200 +#define RTL8367C_FIB1_CFG00_CFG_FIB_FULLDUP_OFFSET 8 +#define RTL8367C_FIB1_CFG00_CFG_FIB_FULLDUP_MASK 0x100 +#define RTL8367C_FIB1_CFG00_CFG_FIB_SPD_RD_1_OFFSET 6 +#define RTL8367C_FIB1_CFG00_CFG_FIB_SPD_RD_1_MASK 0x40 +#define RTL8367C_FIB1_CFG00_CFG_FIB_FRCTX_OFFSET 5 +#define RTL8367C_FIB1_CFG00_CFG_FIB_FRCTX_MASK 0x20 + +#define RTL8367C_REG_FIB1_CFG01 0x6211 +#define RTL8367C_FIB1_CFG01_CAPBILITY_OFFSET 6 +#define RTL8367C_FIB1_CFG01_CAPBILITY_MASK 0xFFC0 +#define RTL8367C_FIB1_CFG01_AN_COMPLETE_OFFSET 5 +#define RTL8367C_FIB1_CFG01_AN_COMPLETE_MASK 0x20 +#define RTL8367C_FIB1_CFG01_R_FAULT_OFFSET 4 +#define RTL8367C_FIB1_CFG01_R_FAULT_MASK 0x10 +#define RTL8367C_FIB1_CFG01_NWAY_ABILITY_OFFSET 3 +#define RTL8367C_FIB1_CFG01_NWAY_ABILITY_MASK 0x8 +#define RTL8367C_FIB1_CFG01_LINK_STATUS_OFFSET 2 +#define RTL8367C_FIB1_CFG01_LINK_STATUS_MASK 0x4 +#define RTL8367C_FIB1_CFG01_JABBER_DETECT_OFFSET 1 +#define RTL8367C_FIB1_CFG01_JABBER_DETECT_MASK 0x2 +#define RTL8367C_FIB1_CFG01_EXTENDED_CAPBILITY_OFFSET 0 +#define RTL8367C_FIB1_CFG01_EXTENDED_CAPBILITY_MASK 0x1 + +#define RTL8367C_REG_FIB1_CFG02 0x6212 + +#define RTL8367C_REG_FIB1_CFG03 0x6213 +#define RTL8367C_FIB1_CFG03_REALTEK_OUI5_0_OFFSET 10 +#define RTL8367C_FIB1_CFG03_REALTEK_OUI5_0_MASK 0xFC00 +#define RTL8367C_FIB1_CFG03_MODEL_NO_OFFSET 4 +#define RTL8367C_FIB1_CFG03_MODEL_NO_MASK 0x3F0 +#define RTL8367C_FIB1_CFG03_REVISION_NO_OFFSET 0 +#define RTL8367C_FIB1_CFG03_REVISION_NO_MASK 0xF + +#define RTL8367C_REG_FIB1_CFG04 0x6214 + +#define RTL8367C_REG_FIB1_CFG05 0x6215 + +#define RTL8367C_REG_FIB1_CFG06 0x6216 +#define RTL8367C_FIB1_CFG06_FIB_NP_EN_OFFSET 2 +#define RTL8367C_FIB1_CFG06_FIB_NP_EN_MASK 0x4 +#define RTL8367C_FIB1_CFG06_RXPAGE_OFFSET 1 +#define RTL8367C_FIB1_CFG06_RXPAGE_MASK 0x2 + +#define RTL8367C_REG_FIB1_CFG07 0x6217 + +#define RTL8367C_REG_FIB1_CFG08 0x6218 + +#define RTL8367C_REG_FIB1_CFG09 0x6219 + +#define RTL8367C_REG_FIB1_CFG10 0x621a + +#define RTL8367C_REG_FIB1_CFG11 0x621b + +#define RTL8367C_REG_FIB1_CFG12 0x621c + +#define RTL8367C_REG_FIB1_CFG13 0x621d +#define RTL8367C_FIB1_CFG13_INDR_FUNC_OFFSET 14 +#define RTL8367C_FIB1_CFG13_INDR_FUNC_MASK 0xC000 +#define RTL8367C_FIB1_CFG13_DUMMY_OFFSET 5 +#define RTL8367C_FIB1_CFG13_DUMMY_MASK 0x3FE0 +#define RTL8367C_FIB1_CFG13_INDR_DEVAD_OFFSET 0 +#define RTL8367C_FIB1_CFG13_INDR_DEVAD_MASK 0x1F + +#define RTL8367C_REG_FIB1_CFG14 0x621e + +#define RTL8367C_REG_FIB1_CFG15 0x621f + +/* (16'h6400)timer_1588 */ + +#define RTL8367C_REG_PTP_TIME_NSEC_L_NSEC 0x6400 + +#define RTL8367C_REG_PTP_TIME_NSEC_H_NSEC 0x6401 +#define RTL8367C_PTP_TIME_NSEC_H_EXEC_OFFSET 15 +#define RTL8367C_PTP_TIME_NSEC_H_EXEC_MASK 0x8000 +#define RTL8367C_PTP_TIME_NSEC_H_CMD_OFFSET 12 +#define RTL8367C_PTP_TIME_NSEC_H_CMD_MASK 0x3000 +#define RTL8367C_PTP_TIME_NSEC_H_NSEC_OFFSET 0 +#define RTL8367C_PTP_TIME_NSEC_H_NSEC_MASK 0x7FF + +#define RTL8367C_REG_PTP_TIME_SEC_L_SEC 0x6402 + +#define RTL8367C_REG_PTP_TIME_SEC_H_SEC 0x6403 + +#define RTL8367C_REG_PTP_TIME_CFG 0x6404 +#define RTL8367C_CFG_TIMER_EN_FRC_OFFSET 2 +#define RTL8367C_CFG_TIMER_EN_FRC_MASK 0x4 +#define RTL8367C_CFG_TIMER_1588_EN_OFFSET 1 +#define RTL8367C_CFG_TIMER_1588_EN_MASK 0x2 +#define RTL8367C_CFG_CLK_SRC_OFFSET 0 +#define RTL8367C_CFG_CLK_SRC_MASK 0x1 + +#define RTL8367C_REG_OTAG_TPID 0x6405 + +#define RTL8367C_REG_ITAG_TPID 0x6406 + +#define RTL8367C_REG_MAC_ADDR_L 0x6407 + +#define RTL8367C_REG_MAC_ADDR_M 0x6408 + +#define RTL8367C_REG_MAC_ADDR_H 0x6409 + +#define RTL8367C_REG_PTP_TIME_NSEC_L_NSEC_RD 0x640a + +#define RTL8367C_REG_PTP_TIME_NSEC_H_NSEC_RD 0x640b +#define RTL8367C_PTP_TIME_NSEC_H_NSEC_RD_OFFSET 0 +#define RTL8367C_PTP_TIME_NSEC_H_NSEC_RD_MASK 0x7FF + +#define RTL8367C_REG_PTP_TIME_SEC_L_SEC_RD 0x640c + +#define RTL8367C_REG_PTP_TIME_SEC_H_SEC_RD 0x640d + +#define RTL8367C_REG_PTP_TIME_CFG2 0x640e +#define RTL8367C_CFG_EN_OFFLOAD_OFFSET 9 +#define RTL8367C_CFG_EN_OFFLOAD_MASK 0x200 +#define RTL8367C_CFG_SAVE_OFF_TS_OFFSET 8 +#define RTL8367C_CFG_SAVE_OFF_TS_MASK 0x100 +#define RTL8367C_CFG_IMR_OFFSET 0 +#define RTL8367C_CFG_IMR_MASK 0xFF + +#define RTL8367C_REG_PTP_INTERRUPT_CFG 0x640f +#define RTL8367C_P9_INTERRUPT_OFFSET 9 +#define RTL8367C_P9_INTERRUPT_MASK 0x200 +#define RTL8367C_P8_INTERRUPT_OFFSET 8 +#define RTL8367C_P8_INTERRUPT_MASK 0x100 +#define RTL8367C_P7_INTERRUPT_OFFSET 7 +#define RTL8367C_P7_INTERRUPT_MASK 0x80 +#define RTL8367C_P6_INTERRUPT_OFFSET 6 +#define RTL8367C_P6_INTERRUPT_MASK 0x40 +#define RTL8367C_P5_INTERRUPT_OFFSET 5 +#define RTL8367C_P5_INTERRUPT_MASK 0x20 +#define RTL8367C_P4_INTERRUPT_OFFSET 4 +#define RTL8367C_P4_INTERRUPT_MASK 0x10 +#define RTL8367C_P3_INTERRUPT_OFFSET 3 +#define RTL8367C_P3_INTERRUPT_MASK 0x8 +#define RTL8367C_P2_INTERRUPT_OFFSET 2 +#define RTL8367C_P2_INTERRUPT_MASK 0x4 +#define RTL8367C_P1_INTERRUPT_OFFSET 1 +#define RTL8367C_P1_INTERRUPT_MASK 0x2 +#define RTL8367C_P0_INTERRUPT_OFFSET 0 +#define RTL8367C_P0_INTERRUPT_MASK 0x1 + +#define RTL8367C_REG_P0_TX_SYNC_SEQ_ID 0x6410 + +#define RTL8367C_REG_P0_TX_DELAY_REQ_SEQ_ID 0x6411 + +#define RTL8367C_REG_P0_TX_PDELAY_REQ_SEQ_ID 0x6412 + +#define RTL8367C_REG_P0_TX_PDELAY_RESP_SEQ_ID 0x6413 + +#define RTL8367C_REG_P0_RX_SYNC_SEQ_ID 0x6414 + +#define RTL8367C_REG_P0_RX_DELAY_REQ_SEQ_ID 0x6415 + +#define RTL8367C_REG_P0_RX_PDELAY_REQ_SEQ_ID 0x6416 + +#define RTL8367C_REG_P0_RX_PDELAY_RESP_SEQ_ID 0x6417 + +#define RTL8367C_REG_P0_PORT_NSEC_15_0 0x6418 + +#define RTL8367C_REG_P0_PORT_NSEC_26_16 0x6419 +#define RTL8367C_P0_PORT_NSEC_26_16_OFFSET 0 +#define RTL8367C_P0_PORT_NSEC_26_16_MASK 0x7FF + +#define RTL8367C_REG_P0_PORT_SEC_15_0 0x641a + +#define RTL8367C_REG_P0_PORT_SEC_31_16 0x641b + +#define RTL8367C_REG_P0_EAV_CFG 0x641c +#define RTL8367C_P0_EAV_CFG_PTP_PHY_EN_EN_OFFSET 8 +#define RTL8367C_P0_EAV_CFG_PTP_PHY_EN_EN_MASK 0x100 +#define RTL8367C_P0_EAV_CFG_RX_PDELAY_RESP_OFFSET 7 +#define RTL8367C_P0_EAV_CFG_RX_PDELAY_RESP_MASK 0x80 +#define RTL8367C_P0_EAV_CFG_RX_PDELAY_REQ_OFFSET 6 +#define RTL8367C_P0_EAV_CFG_RX_PDELAY_REQ_MASK 0x40 +#define RTL8367C_P0_EAV_CFG_RX_DELAY_REQ_OFFSET 5 +#define RTL8367C_P0_EAV_CFG_RX_DELAY_REQ_MASK 0x20 +#define RTL8367C_P0_EAV_CFG_RX_SYNC_OFFSET 4 +#define RTL8367C_P0_EAV_CFG_RX_SYNC_MASK 0x10 +#define RTL8367C_P0_EAV_CFG_TX_PDELAY_RESP_OFFSET 3 +#define RTL8367C_P0_EAV_CFG_TX_PDELAY_RESP_MASK 0x8 +#define RTL8367C_P0_EAV_CFG_TX_PDELAY_REQ_OFFSET 2 +#define RTL8367C_P0_EAV_CFG_TX_PDELAY_REQ_MASK 0x4 +#define RTL8367C_P0_EAV_CFG_TX_DELAY_REQ_OFFSET 1 +#define RTL8367C_P0_EAV_CFG_TX_DELAY_REQ_MASK 0x2 +#define RTL8367C_P0_EAV_CFG_TX_SYNC_OFFSET 0 +#define RTL8367C_P0_EAV_CFG_TX_SYNC_MASK 0x1 + +#define RTL8367C_REG_P1_TX_SYNC_SEQ_ID 0x6420 + +#define RTL8367C_REG_P1_TX_DELAY_REQ_SEQ_ID 0x6421 + +#define RTL8367C_REG_P1_TX_PDELAY_REQ_SEQ_ID 0x6422 + +#define RTL8367C_REG_P1_TX_PDELAY_RESP_SEQ_ID 0x6423 + +#define RTL8367C_REG_P1_RX_SYNC_SEQ_ID 0x6424 + +#define RTL8367C_REG_P1_RX_DELAY_REQ_SEQ_ID 0x6425 + +#define RTL8367C_REG_P1_RX_PDELAY_REQ_SEQ_ID 0x6426 + +#define RTL8367C_REG_P1_RX_PDELAY_RESP_SEQ_ID 0x6427 + +#define RTL8367C_REG_P1_PORT_NSEC_15_0 0x6428 + +#define RTL8367C_REG_P1_PORT_NSEC_26_16 0x6429 +#define RTL8367C_P1_PORT_NSEC_26_16_OFFSET 0 +#define RTL8367C_P1_PORT_NSEC_26_16_MASK 0x7FF + +#define RTL8367C_REG_P1_PORT_SEC_15_0 0x642a + +#define RTL8367C_REG_P1_PORT_SEC_31_16 0x642b + +#define RTL8367C_REG_P1_EAV_CFG 0x642c +#define RTL8367C_P1_EAV_CFG_PTP_PHY_EN_EN_OFFSET 8 +#define RTL8367C_P1_EAV_CFG_PTP_PHY_EN_EN_MASK 0x100 +#define RTL8367C_P1_EAV_CFG_RX_PDELAY_RESP_OFFSET 7 +#define RTL8367C_P1_EAV_CFG_RX_PDELAY_RESP_MASK 0x80 +#define RTL8367C_P1_EAV_CFG_RX_PDELAY_REQ_OFFSET 6 +#define RTL8367C_P1_EAV_CFG_RX_PDELAY_REQ_MASK 0x40 +#define RTL8367C_P1_EAV_CFG_RX_DELAY_REQ_OFFSET 5 +#define RTL8367C_P1_EAV_CFG_RX_DELAY_REQ_MASK 0x20 +#define RTL8367C_P1_EAV_CFG_RX_SYNC_OFFSET 4 +#define RTL8367C_P1_EAV_CFG_RX_SYNC_MASK 0x10 +#define RTL8367C_P1_EAV_CFG_TX_PDELAY_RESP_OFFSET 3 +#define RTL8367C_P1_EAV_CFG_TX_PDELAY_RESP_MASK 0x8 +#define RTL8367C_P1_EAV_CFG_TX_PDELAY_REQ_OFFSET 2 +#define RTL8367C_P1_EAV_CFG_TX_PDELAY_REQ_MASK 0x4 +#define RTL8367C_P1_EAV_CFG_TX_DELAY_REQ_OFFSET 1 +#define RTL8367C_P1_EAV_CFG_TX_DELAY_REQ_MASK 0x2 +#define RTL8367C_P1_EAV_CFG_TX_SYNC_OFFSET 0 +#define RTL8367C_P1_EAV_CFG_TX_SYNC_MASK 0x1 + +#define RTL8367C_REG_P2_TX_SYNC_SEQ_ID 0x6430 + +#define RTL8367C_REG_P2_TX_DELAY_REQ_SEQ_ID 0x6431 + +#define RTL8367C_REG_P2_TX_PDELAY_REQ_SEQ_ID 0x6432 + +#define RTL8367C_REG_P2_TX_PDELAY_RESP_SEQ_ID 0x6433 + +#define RTL8367C_REG_P2_RX_SYNC_SEQ_ID 0x6434 + +#define RTL8367C_REG_P2_RX_DELAY_REQ_SEQ_ID 0x6435 + +#define RTL8367C_REG_P2_RX_PDELAY_REQ_SEQ_ID 0x6436 + +#define RTL8367C_REG_P2_RX_PDELAY_RESP_SEQ_ID 0x6437 + +#define RTL8367C_REG_P2_PORT_NSEC_15_0 0x6438 + +#define RTL8367C_REG_P2_PORT_NSEC_26_16 0x6439 +#define RTL8367C_P2_PORT_NSEC_26_16_OFFSET 0 +#define RTL8367C_P2_PORT_NSEC_26_16_MASK 0x7FF + +#define RTL8367C_REG_P2_PORT_SEC_15_0 0x643a + +#define RTL8367C_REG_P2_PORT_SEC_31_16 0x643b + +#define RTL8367C_REG_P2_EAV_CFG 0x643c +#define RTL8367C_P2_EAV_CFG_PTP_PHY_EN_EN_OFFSET 8 +#define RTL8367C_P2_EAV_CFG_PTP_PHY_EN_EN_MASK 0x100 +#define RTL8367C_P2_EAV_CFG_RX_PDELAY_RESP_OFFSET 7 +#define RTL8367C_P2_EAV_CFG_RX_PDELAY_RESP_MASK 0x80 +#define RTL8367C_P2_EAV_CFG_RX_PDELAY_REQ_OFFSET 6 +#define RTL8367C_P2_EAV_CFG_RX_PDELAY_REQ_MASK 0x40 +#define RTL8367C_P2_EAV_CFG_RX_DELAY_REQ_OFFSET 5 +#define RTL8367C_P2_EAV_CFG_RX_DELAY_REQ_MASK 0x20 +#define RTL8367C_P2_EAV_CFG_RX_SYNC_OFFSET 4 +#define RTL8367C_P2_EAV_CFG_RX_SYNC_MASK 0x10 +#define RTL8367C_P2_EAV_CFG_TX_PDELAY_RESP_OFFSET 3 +#define RTL8367C_P2_EAV_CFG_TX_PDELAY_RESP_MASK 0x8 +#define RTL8367C_P2_EAV_CFG_TX_PDELAY_REQ_OFFSET 2 +#define RTL8367C_P2_EAV_CFG_TX_PDELAY_REQ_MASK 0x4 +#define RTL8367C_P2_EAV_CFG_TX_DELAY_REQ_OFFSET 1 +#define RTL8367C_P2_EAV_CFG_TX_DELAY_REQ_MASK 0x2 +#define RTL8367C_P2_EAV_CFG_TX_SYNC_OFFSET 0 +#define RTL8367C_P2_EAV_CFG_TX_SYNC_MASK 0x1 + +#define RTL8367C_REG_P3_TX_SYNC_SEQ_ID 0x6440 + +#define RTL8367C_REG_P3_TX_DELAY_REQ_SEQ_ID 0x6441 + +#define RTL8367C_REG_P3_TX_PDELAY_REQ_SEQ_ID 0x6442 + +#define RTL8367C_REG_P3_TX_PDELAY_RESP_SEQ_ID 0x6443 + +#define RTL8367C_REG_P3_RX_SYNC_SEQ_ID 0x6444 + +#define RTL8367C_REG_P3_RX_DELAY_REQ_SEQ_ID 0x6445 + +#define RTL8367C_REG_P3_RX_PDELAY_REQ_SEQ_ID 0x6446 + +#define RTL8367C_REG_P3_RX_PDELAY_RESP_SEQ_ID 0x6447 + +#define RTL8367C_REG_P3_PORT_NSEC_15_0 0x6448 + +#define RTL8367C_REG_P3_PORT_NSEC_26_16 0x6449 +#define RTL8367C_P3_PORT_NSEC_26_16_OFFSET 0 +#define RTL8367C_P3_PORT_NSEC_26_16_MASK 0x7FF + +#define RTL8367C_REG_P3_PORT_SEC_15_0 0x644a + +#define RTL8367C_REG_P3_PORT_SEC_31_16 0x644b + +#define RTL8367C_REG_P3_EAV_CFG 0x644c +#define RTL8367C_P3_EAV_CFG_PTP_PHY_EN_EN_OFFSET 8 +#define RTL8367C_P3_EAV_CFG_PTP_PHY_EN_EN_MASK 0x100 +#define RTL8367C_P3_EAV_CFG_RX_PDELAY_RESP_OFFSET 7 +#define RTL8367C_P3_EAV_CFG_RX_PDELAY_RESP_MASK 0x80 +#define RTL8367C_P3_EAV_CFG_RX_PDELAY_REQ_OFFSET 6 +#define RTL8367C_P3_EAV_CFG_RX_PDELAY_REQ_MASK 0x40 +#define RTL8367C_P3_EAV_CFG_RX_DELAY_REQ_OFFSET 5 +#define RTL8367C_P3_EAV_CFG_RX_DELAY_REQ_MASK 0x20 +#define RTL8367C_P3_EAV_CFG_RX_SYNC_OFFSET 4 +#define RTL8367C_P3_EAV_CFG_RX_SYNC_MASK 0x10 +#define RTL8367C_P3_EAV_CFG_TX_PDELAY_RESP_OFFSET 3 +#define RTL8367C_P3_EAV_CFG_TX_PDELAY_RESP_MASK 0x8 +#define RTL8367C_P3_EAV_CFG_TX_PDELAY_REQ_OFFSET 2 +#define RTL8367C_P3_EAV_CFG_TX_PDELAY_REQ_MASK 0x4 +#define RTL8367C_P3_EAV_CFG_TX_DELAY_REQ_OFFSET 1 +#define RTL8367C_P3_EAV_CFG_TX_DELAY_REQ_MASK 0x2 +#define RTL8367C_P3_EAV_CFG_TX_SYNC_OFFSET 0 +#define RTL8367C_P3_EAV_CFG_TX_SYNC_MASK 0x1 + +#define RTL8367C_REG_P4_TX_SYNC_SEQ_ID 0x6450 + +#define RTL8367C_REG_P4_TX_DELAY_REQ_SEQ_ID 0x6451 + +#define RTL8367C_REG_P4_TX_PDELAY_REQ_SEQ_ID 0x6452 + +#define RTL8367C_REG_P4_TX_PDELAY_RESP_SEQ_ID 0x6453 + +#define RTL8367C_REG_P4_RX_SYNC_SEQ_ID 0x6454 + +#define RTL8367C_REG_P4_RX_DELAY_REQ_SEQ_ID 0x6455 + +#define RTL8367C_REG_P4_RX_PDELAY_REQ_SEQ_ID 0x6456 + +#define RTL8367C_REG_P4_RX_PDELAY_RESP_SEQ_ID 0x6457 + +#define RTL8367C_REG_P4_PORT_NSEC_15_0 0x6458 + +#define RTL8367C_REG_P4_PORT_NSEC_26_16 0x6459 +#define RTL8367C_P4_PORT_NSEC_26_16_OFFSET 0 +#define RTL8367C_P4_PORT_NSEC_26_16_MASK 0x7FF + +#define RTL8367C_REG_P4_PORT_SEC_15_0 0x645a + +#define RTL8367C_REG_P4_PORT_SEC_31_16 0x645b + +#define RTL8367C_REG_P4_EAV_CFG 0x645c +#define RTL8367C_P4_EAV_CFG_PTP_PHY_EN_EN_OFFSET 8 +#define RTL8367C_P4_EAV_CFG_PTP_PHY_EN_EN_MASK 0x100 +#define RTL8367C_P4_EAV_CFG_RX_PDELAY_RESP_OFFSET 7 +#define RTL8367C_P4_EAV_CFG_RX_PDELAY_RESP_MASK 0x80 +#define RTL8367C_P4_EAV_CFG_RX_PDELAY_REQ_OFFSET 6 +#define RTL8367C_P4_EAV_CFG_RX_PDELAY_REQ_MASK 0x40 +#define RTL8367C_P4_EAV_CFG_RX_DELAY_REQ_OFFSET 5 +#define RTL8367C_P4_EAV_CFG_RX_DELAY_REQ_MASK 0x20 +#define RTL8367C_P4_EAV_CFG_RX_SYNC_OFFSET 4 +#define RTL8367C_P4_EAV_CFG_RX_SYNC_MASK 0x10 +#define RTL8367C_P4_EAV_CFG_TX_PDELAY_RESP_OFFSET 3 +#define RTL8367C_P4_EAV_CFG_TX_PDELAY_RESP_MASK 0x8 +#define RTL8367C_P4_EAV_CFG_TX_PDELAY_REQ_OFFSET 2 +#define RTL8367C_P4_EAV_CFG_TX_PDELAY_REQ_MASK 0x4 +#define RTL8367C_P4_EAV_CFG_TX_DELAY_REQ_OFFSET 1 +#define RTL8367C_P4_EAV_CFG_TX_DELAY_REQ_MASK 0x2 +#define RTL8367C_P4_EAV_CFG_TX_SYNC_OFFSET 0 +#define RTL8367C_P4_EAV_CFG_TX_SYNC_MASK 0x1 + +#define RTL8367C_REG_P6_TX_SYNC_SEQ_ID 0x6460 + +#define RTL8367C_REG_P6_TX_DELAY_REQ_SEQ_ID 0x6461 + +#define RTL8367C_REG_P6_TX_PDELAY_REQ_SEQ_ID 0x6462 + +#define RTL8367C_REG_P6_TX_PDELAY_RESP_SEQ_ID 0x6463 + +#define RTL8367C_REG_P6_RX_SYNC_SEQ_ID 0x6464 + +#define RTL8367C_REG_P6_RX_DELAY_REQ_SEQ_ID 0x6465 + +#define RTL8367C_REG_P6_RX_PDELAY_REQ_SEQ_ID 0x6466 + +#define RTL8367C_REG_P6_RX_PDELAY_RESP_SEQ_ID 0x6467 + +#define RTL8367C_REG_P6_PORT_NSEC_15_0 0x6468 + +#define RTL8367C_REG_P6_PORT_NSEC_26_16 0x6469 +#define RTL8367C_P6_PORT_NSEC_26_16_OFFSET 0 +#define RTL8367C_P6_PORT_NSEC_26_16_MASK 0x7FF + +#define RTL8367C_REG_P6_PORT_SEC_15_0 0x646a + +#define RTL8367C_REG_P6_PORT_SEC_31_16 0x646b + +#define RTL8367C_REG_P6_EAV_CFG 0x646c +#define RTL8367C_P6_EAV_CFG_PTP_PHY_EN_EN_OFFSET 8 +#define RTL8367C_P6_EAV_CFG_PTP_PHY_EN_EN_MASK 0x100 +#define RTL8367C_P6_EAV_CFG_RX_PDELAY_RESP_OFFSET 7 +#define RTL8367C_P6_EAV_CFG_RX_PDELAY_RESP_MASK 0x80 +#define RTL8367C_P6_EAV_CFG_RX_PDELAY_REQ_OFFSET 6 +#define RTL8367C_P6_EAV_CFG_RX_PDELAY_REQ_MASK 0x40 +#define RTL8367C_P6_EAV_CFG_RX_DELAY_REQ_OFFSET 5 +#define RTL8367C_P6_EAV_CFG_RX_DELAY_REQ_MASK 0x20 +#define RTL8367C_P6_EAV_CFG_RX_SYNC_OFFSET 4 +#define RTL8367C_P6_EAV_CFG_RX_SYNC_MASK 0x10 +#define RTL8367C_P6_EAV_CFG_TX_PDELAY_RESP_OFFSET 3 +#define RTL8367C_P6_EAV_CFG_TX_PDELAY_RESP_MASK 0x8 +#define RTL8367C_P6_EAV_CFG_TX_PDELAY_REQ_OFFSET 2 +#define RTL8367C_P6_EAV_CFG_TX_PDELAY_REQ_MASK 0x4 +#define RTL8367C_P6_EAV_CFG_TX_DELAY_REQ_OFFSET 1 +#define RTL8367C_P6_EAV_CFG_TX_DELAY_REQ_MASK 0x2 +#define RTL8367C_P6_EAV_CFG_TX_SYNC_OFFSET 0 +#define RTL8367C_P6_EAV_CFG_TX_SYNC_MASK 0x1 + +#define RTL8367C_REG_P7_TX_SYNC_SEQ_ID 0x6470 + +#define RTL8367C_REG_P7_TX_DELAY_REQ_SEQ_ID 0x6471 + +#define RTL8367C_REG_P7_TX_PDELAY_REQ_SEQ_ID 0x6472 + +#define RTL8367C_REG_P7_TX_PDELAY_RESP_SEQ_ID 0x6473 + +#define RTL8367C_REG_P7_RX_SYNC_SEQ_ID 0x6474 + +#define RTL8367C_REG_P7_RX_DELAY_REQ_SEQ_ID 0x6475 + +#define RTL8367C_REG_P7_RX_PDELAY_REQ_SEQ_ID 0x6476 + +#define RTL8367C_REG_P7_RX_PDELAY_RESP_SEQ_ID 0x6477 + +#define RTL8367C_REG_P7_PORT_NSEC_15_0 0x6478 + +#define RTL8367C_REG_P7_PORT_NSEC_26_16 0x6479 +#define RTL8367C_P7_PORT_NSEC_26_16_OFFSET 0 +#define RTL8367C_P7_PORT_NSEC_26_16_MASK 0x7FF + +#define RTL8367C_REG_P7_PORT_SEC_15_0 0x647a + +#define RTL8367C_REG_P7_PORT_SEC_31_16 0x647b + +#define RTL8367C_REG_P7_EAV_CFG 0x647c +#define RTL8367C_P7_EAV_CFG_PTP_PHY_EN_EN_OFFSET 8 +#define RTL8367C_P7_EAV_CFG_PTP_PHY_EN_EN_MASK 0x100 +#define RTL8367C_P7_EAV_CFG_RX_PDELAY_RESP_OFFSET 7 +#define RTL8367C_P7_EAV_CFG_RX_PDELAY_RESP_MASK 0x80 +#define RTL8367C_P7_EAV_CFG_RX_PDELAY_REQ_OFFSET 6 +#define RTL8367C_P7_EAV_CFG_RX_PDELAY_REQ_MASK 0x40 +#define RTL8367C_P7_EAV_CFG_RX_DELAY_REQ_OFFSET 5 +#define RTL8367C_P7_EAV_CFG_RX_DELAY_REQ_MASK 0x20 +#define RTL8367C_P7_EAV_CFG_RX_SYNC_OFFSET 4 +#define RTL8367C_P7_EAV_CFG_RX_SYNC_MASK 0x10 +#define RTL8367C_P7_EAV_CFG_TX_PDELAY_RESP_OFFSET 3 +#define RTL8367C_P7_EAV_CFG_TX_PDELAY_RESP_MASK 0x8 +#define RTL8367C_P7_EAV_CFG_TX_PDELAY_REQ_OFFSET 2 +#define RTL8367C_P7_EAV_CFG_TX_PDELAY_REQ_MASK 0x4 +#define RTL8367C_P7_EAV_CFG_TX_DELAY_REQ_OFFSET 1 +#define RTL8367C_P7_EAV_CFG_TX_DELAY_REQ_MASK 0x2 +#define RTL8367C_P7_EAV_CFG_TX_SYNC_OFFSET 0 +#define RTL8367C_P7_EAV_CFG_TX_SYNC_MASK 0x1 + +#define RTL8367C_REG_P5_TX_SYNC_SEQ_ID 0x6480 + +#define RTL8367C_REG_P5_TX_DELAY_REQ_SEQ_ID 0x6481 + +#define RTL8367C_REG_P5_TX_PDELAY_REQ_SEQ_ID 0x6482 + +#define RTL8367C_REG_P5_TX_PDELAY_RESP_SEQ_ID 0x6483 + +#define RTL8367C_REG_P5_RX_SYNC_SEQ_ID 0x6484 + +#define RTL8367C_REG_P5_RX_DELAY_REQ_SEQ_ID 0x6485 + +#define RTL8367C_REG_P5_RX_PDELAY_REQ_SEQ_ID 0x6486 + +#define RTL8367C_REG_P5_RX_PDELAY_RESP_SEQ_ID 0x6487 + +#define RTL8367C_REG_P5_PORT_NSEC_15_0 0x6488 + +#define RTL8367C_REG_P5_PORT_NSEC_26_16 0x6489 +#define RTL8367C_P5_PORT_NSEC_26_16_OFFSET 0 +#define RTL8367C_P5_PORT_NSEC_26_16_MASK 0x7FF + +#define RTL8367C_REG_P5_PORT_SEC_15_0 0x648a + +#define RTL8367C_REG_P5_PORT_SEC_31_16 0x648b + +#define RTL8367C_REG_P5_EAV_CFG 0x648c +#define RTL8367C_P5_EAV_CFG_PTP_PHY_EN_EN_OFFSET 8 +#define RTL8367C_P5_EAV_CFG_PTP_PHY_EN_EN_MASK 0x100 +#define RTL8367C_P5_EAV_CFG_RX_PDELAY_RESP_OFFSET 7 +#define RTL8367C_P5_EAV_CFG_RX_PDELAY_RESP_MASK 0x80 +#define RTL8367C_P5_EAV_CFG_RX_PDELAY_REQ_OFFSET 6 +#define RTL8367C_P5_EAV_CFG_RX_PDELAY_REQ_MASK 0x40 +#define RTL8367C_P5_EAV_CFG_RX_DELAY_REQ_OFFSET 5 +#define RTL8367C_P5_EAV_CFG_RX_DELAY_REQ_MASK 0x20 +#define RTL8367C_P5_EAV_CFG_RX_SYNC_OFFSET 4 +#define RTL8367C_P5_EAV_CFG_RX_SYNC_MASK 0x10 +#define RTL8367C_P5_EAV_CFG_TX_PDELAY_RESP_OFFSET 3 +#define RTL8367C_P5_EAV_CFG_TX_PDELAY_RESP_MASK 0x8 +#define RTL8367C_P5_EAV_CFG_TX_PDELAY_REQ_OFFSET 2 +#define RTL8367C_P5_EAV_CFG_TX_PDELAY_REQ_MASK 0x4 +#define RTL8367C_P5_EAV_CFG_TX_DELAY_REQ_OFFSET 1 +#define RTL8367C_P5_EAV_CFG_TX_DELAY_REQ_MASK 0x2 +#define RTL8367C_P5_EAV_CFG_TX_SYNC_OFFSET 0 +#define RTL8367C_P5_EAV_CFG_TX_SYNC_MASK 0x1 + +#define RTL8367C_REG_P8_TX_SYNC_SEQ_ID 0x6490 + +#define RTL8367C_REG_P8_TX_DELAY_REQ_SEQ_ID 0x6491 + +#define RTL8367C_REG_P8_TX_PDELAY_REQ_SEQ_ID 0x6492 + +#define RTL8367C_REG_P8_TX_PDELAY_RESP_SEQ_ID 0x6493 + +#define RTL8367C_REG_P8_RX_SYNC_SEQ_ID 0x6494 + +#define RTL8367C_REG_P8_RX_DELAY_REQ_SEQ_ID 0x6495 + +#define RTL8367C_REG_P8_RX_PDELAY_REQ_SEQ_ID 0x6496 + +#define RTL8367C_REG_P8_RX_PDELAY_RESP_SEQ_ID 0x6497 + +#define RTL8367C_REG_P8_PORT_NSEC_15_0 0x6498 + +#define RTL8367C_REG_P8_PORT_NSEC_26_16 0x6499 +#define RTL8367C_P8_PORT_NSEC_26_16_OFFSET 0 +#define RTL8367C_P8_PORT_NSEC_26_16_MASK 0x7FF + +#define RTL8367C_REG_P8_PORT_SEC_15_0 0x649a + +#define RTL8367C_REG_P8_PORT_SEC_31_16 0x649b + +#define RTL8367C_REG_P8_EAV_CFG 0x649c +#define RTL8367C_P8_EAV_CFG_PTP_PHY_EN_EN_OFFSET 8 +#define RTL8367C_P8_EAV_CFG_PTP_PHY_EN_EN_MASK 0x100 +#define RTL8367C_P8_EAV_CFG_RX_PDELAY_RESP_OFFSET 7 +#define RTL8367C_P8_EAV_CFG_RX_PDELAY_RESP_MASK 0x80 +#define RTL8367C_P8_EAV_CFG_RX_PDELAY_REQ_OFFSET 6 +#define RTL8367C_P8_EAV_CFG_RX_PDELAY_REQ_MASK 0x40 +#define RTL8367C_P8_EAV_CFG_RX_DELAY_REQ_OFFSET 5 +#define RTL8367C_P8_EAV_CFG_RX_DELAY_REQ_MASK 0x20 +#define RTL8367C_P8_EAV_CFG_RX_SYNC_OFFSET 4 +#define RTL8367C_P8_EAV_CFG_RX_SYNC_MASK 0x10 +#define RTL8367C_P8_EAV_CFG_TX_PDELAY_RESP_OFFSET 3 +#define RTL8367C_P8_EAV_CFG_TX_PDELAY_RESP_MASK 0x8 +#define RTL8367C_P8_EAV_CFG_TX_PDELAY_REQ_OFFSET 2 +#define RTL8367C_P8_EAV_CFG_TX_PDELAY_REQ_MASK 0x4 +#define RTL8367C_P8_EAV_CFG_TX_DELAY_REQ_OFFSET 1 +#define RTL8367C_P8_EAV_CFG_TX_DELAY_REQ_MASK 0x2 +#define RTL8367C_P8_EAV_CFG_TX_SYNC_OFFSET 0 +#define RTL8367C_P8_EAV_CFG_TX_SYNC_MASK 0x1 + +#define RTL8367C_REG_P9_TX_SYNC_SEQ_ID 0x64a0 + +#define RTL8367C_REG_P9_TX_DELAY_REQ_SEQ_ID 0x64a1 + +#define RTL8367C_REG_P9_TX_PDELAY_REQ_SEQ_ID 0x64a2 + +#define RTL8367C_REG_P9_TX_PDELAY_RESP_SEQ_ID 0x64a3 + +#define RTL8367C_REG_P9_RX_SYNC_SEQ_ID 0x64a4 + +#define RTL8367C_REG_P9_RX_DELAY_REQ_SEQ_ID 0x64a5 + +#define RTL8367C_REG_P9_RX_PDELAY_REQ_SEQ_ID 0x64a6 + +#define RTL8367C_REG_P9_RX_PDELAY_RESP_SEQ_ID 0x64a7 + +#define RTL8367C_REG_P9_PORT_NSEC_15_0 0x64a8 + +#define RTL8367C_REG_P9_PORT_NSEC_26_16 0x64a9 +#define RTL8367C_P9_PORT_NSEC_26_16_OFFSET 0 +#define RTL8367C_P9_PORT_NSEC_26_16_MASK 0x7FF + +#define RTL8367C_REG_P9_PORT_SEC_15_0 0x64aa + +#define RTL8367C_REG_P9_PORT_SEC_31_16 0x64ab + +#define RTL8367C_REG_P9_EAV_CFG 0x64ac +#define RTL8367C_P9_EAV_CFG_PTP_PHY_EN_EN_OFFSET 8 +#define RTL8367C_P9_EAV_CFG_PTP_PHY_EN_EN_MASK 0x100 +#define RTL8367C_P9_EAV_CFG_RX_PDELAY_RESP_OFFSET 7 +#define RTL8367C_P9_EAV_CFG_RX_PDELAY_RESP_MASK 0x80 +#define RTL8367C_P9_EAV_CFG_RX_PDELAY_REQ_OFFSET 6 +#define RTL8367C_P9_EAV_CFG_RX_PDELAY_REQ_MASK 0x40 +#define RTL8367C_P9_EAV_CFG_RX_DELAY_REQ_OFFSET 5 +#define RTL8367C_P9_EAV_CFG_RX_DELAY_REQ_MASK 0x20 +#define RTL8367C_P9_EAV_CFG_RX_SYNC_OFFSET 4 +#define RTL8367C_P9_EAV_CFG_RX_SYNC_MASK 0x10 +#define RTL8367C_P9_EAV_CFG_TX_PDELAY_RESP_OFFSET 3 +#define RTL8367C_P9_EAV_CFG_TX_PDELAY_RESP_MASK 0x8 +#define RTL8367C_P9_EAV_CFG_TX_PDELAY_REQ_OFFSET 2 +#define RTL8367C_P9_EAV_CFG_TX_PDELAY_REQ_MASK 0x4 +#define RTL8367C_P9_EAV_CFG_TX_DELAY_REQ_OFFSET 1 +#define RTL8367C_P9_EAV_CFG_TX_DELAY_REQ_MASK 0x2 +#define RTL8367C_P9_EAV_CFG_TX_SYNC_OFFSET 0 +#define RTL8367C_P9_EAV_CFG_TX_SYNC_MASK 0x1 + +/* (16'h6600)sds_indacs_reg */ + +#define RTL8367C_REG_SDS_INDACS_CMD 0x6600 +#define RTL8367C_SDS_CMD_BUSY_OFFSET 8 +#define RTL8367C_SDS_CMD_BUSY_MASK 0x100 +#define RTL8367C_SDS_CMD_OFFSET 7 +#define RTL8367C_SDS_CMD_MASK 0x80 +#define RTL8367C_SDS_RWOP_OFFSET 6 +#define RTL8367C_SDS_RWOP_MASK 0x40 +#define RTL8367C_SDS_INDEX_OFFSET 0 +#define RTL8367C_SDS_INDEX_MASK 0x3F + +#define RTL8367C_REG_SDS_INDACS_ADR 0x6601 +#define RTL8367C_SDS_PAGE_OFFSET 5 +#define RTL8367C_SDS_PAGE_MASK 0x7E0 +#define RTL8367C_SDS_REGAD_OFFSET 0 +#define RTL8367C_SDS_REGAD_MASK 0x1F + +#define RTL8367C_REG_SDS_INDACS_DATA 0x6602 + + +#endif /*#ifndef _RTL8367C_REG_H_*/ + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_smi.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_smi.c new file mode 100644 index 00000000..8219536f --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_smi.c @@ -0,0 +1,441 @@ +/* +* Copyright c Realtek Semiconductor Corporation, 2006 +* All rights reserved. +* +* Program : Control smi connected RTL8366 +* Abstract : +* Author : Yu-Mei Pan (ympan@realtek.com.cn) +* $Id: smi.c,v 1.2 2008-04-10 03:04:19 shiehyy Exp $ +*/ +#include +#include +#include "rtk_error.h" + + +#if defined(MDC_MDIO_OPERATION) +/*******************************************************************************/ +/* MDC/MDIO porting */ +/*******************************************************************************/ +/* define the PHY ID currently used */ +#define MDC_MDIO_PHY_ID 29 /* PHY ID 0 or 29 */ + +extern int ipq_mdio_read(int mii_id, int regnum, unsigned short *data); +extern int ipq_mdio_write(int mii_id, int regnum, unsigned short value); + +static inline unsigned int rtk_mdio_write(int mii_id, int regnum, unsigned int value) +{ + return ipq_mdio_write(mii_id, regnum, (unsigned short)value); +} + +static inline int rtk_mdio_read(int mii_id, int regnum, unsigned int *data) +{ + unsigned short temp_data = 0; + + ipq_mdio_read(mii_id, regnum, &temp_data); + + if (data != NULL) + *data = temp_data; + + return temp_data; +} + +/* MDC/MDIO, redefine/implement the following Macro */ +#define MDC_MDIO_WRITE(preamableLength, phyID, regID, data) rtk_mdio_write(phyID, regID, data) +#define MDC_MDIO_READ(preamableLength, phyID, regID, pData) rtk_mdio_read(phyID, regID, pData) + + + +#elif defined(SPI_OPERATION) +/*******************************************************************************/ +/* SPI porting */ +/*******************************************************************************/ +/* SPI, redefine/implement the following Macro */ +#define SPI_WRITE(data, length) +#define SPI_READ(pData, length) + + + + + +#else +/*******************************************************************************/ +/* I2C porting */ +/*******************************************************************************/ +/* Define the GPIO ID for SCK & SDA */ +rtk_uint32 smi_SCK = 1; /* GPIO used for SMI Clock Generation */ +rtk_uint32 smi_SDA = 2; /* GPIO used for SMI Data signal */ + +/* I2C, redefine/implement the following Macro */ +#define GPIO_DIRECTION_SET(gpioID, direction) +#define GPIO_DATA_SET(gpioID, data) +#define GPIO_DATA_GET(gpioID, pData) + + + + + +#endif + +static void rtlglue_drvMutexLock(void) +{ + /* It is empty currently. Implement this function if Lock/Unlock function is needed */ + return; +} + +static void rtlglue_drvMutexUnlock(void) +{ + /* It is empty currently. Implement this function if Lock/Unlock function is needed */ + return; +} + + + +#if defined(MDC_MDIO_OPERATION) || defined(SPI_OPERATION) + /* No local function in MDC/MDIO & SPI mode */ +#else +static void _smi_start(void) +{ + + /* change GPIO pin to Output only */ + GPIO_DIRECTION_SET(smi_SCK, GPIO_DIR_OUT); + GPIO_DIRECTION_SET(smi_SDA, GPIO_DIR_OUT); + + /* Initial state: SCK: 0, SDA: 1 */ + GPIO_DATA_SET(smi_SCK, 0); + GPIO_DATA_SET(smi_SDA, 1); + CLK_DURATION(DELAY); + + /* CLK 1: 0 -> 1, 1 -> 0 */ + GPIO_DATA_SET(smi_SCK, 1); + CLK_DURATION(DELAY); + GPIO_DATA_SET(smi_SCK, 0); + CLK_DURATION(DELAY); + + /* CLK 2: */ + GPIO_DATA_SET(smi_SCK, 1); + CLK_DURATION(DELAY); + GPIO_DATA_SET(smi_SDA, 0); + CLK_DURATION(DELAY); + GPIO_DATA_SET(smi_SCK, 0); + CLK_DURATION(DELAY); + GPIO_DATA_SET(smi_SDA, 1); + +} + + + +static void _smi_writeBit(rtk_uint16 signal, rtk_uint32 bitLen) +{ + for( ; bitLen > 0; bitLen--) + { + CLK_DURATION(DELAY); + + /* prepare data */ + if ( signal & (1<<(bitLen-1)) ) + { + GPIO_DATA_SET(smi_SDA, 1); + } + else + { + GPIO_DATA_SET(smi_SDA, 0); + } + CLK_DURATION(DELAY); + + /* clocking */ + GPIO_DATA_SET(smi_SCK, 1); + CLK_DURATION(DELAY); + GPIO_DATA_SET(smi_SCK, 0); + } +} + + + +static void _smi_readBit(rtk_uint32 bitLen, rtk_uint32 *rData) +{ + rtk_uint32 u = 0; + + /* change GPIO pin to Input only */ + GPIO_DIRECTION_SET(smi_SDA, GPIO_DIR_IN); + + for (*rData = 0; bitLen > 0; bitLen--) + { + CLK_DURATION(DELAY); + + /* clocking */ + GPIO_DATA_SET(smi_SCK, 1); + CLK_DURATION(DELAY); + GPIO_DATA_GET(smi_SDA, &u); + GPIO_DATA_SET(smi_SCK, 0); + + *rData |= (u << (bitLen - 1)); + } + + /* change GPIO pin to Output only */ + GPIO_DIRECTION_SET(smi_SDA, GPIO_DIR_OUT); +} + + + +static void _smi_stop(void) +{ + + CLK_DURATION(DELAY); + GPIO_DATA_SET(smi_SDA, 0); + GPIO_DATA_SET(smi_SCK, 1); + CLK_DURATION(DELAY); + GPIO_DATA_SET(smi_SDA, 1); + CLK_DURATION(DELAY); + GPIO_DATA_SET(smi_SCK, 1); + CLK_DURATION(DELAY); + GPIO_DATA_SET(smi_SCK, 0); + CLK_DURATION(DELAY); + GPIO_DATA_SET(smi_SCK, 1); + + /* add a click */ + CLK_DURATION(DELAY); + GPIO_DATA_SET(smi_SCK, 0); + CLK_DURATION(DELAY); + GPIO_DATA_SET(smi_SCK, 1); + + + /* change GPIO pin to Input only */ + GPIO_DIRECTION_SET(smi_SDA, GPIO_DIR_IN); + GPIO_DIRECTION_SET(smi_SCK, GPIO_DIR_IN); +} + +#endif /* End of #if defined(MDC_MDIO_OPERATION) || defined(SPI_OPERATION) */ + +rtk_int32 rtl8367c_smi_read(rtk_uint32 mAddrs, rtk_uint32 *rData) +{ +#if (!defined(MDC_MDIO_OPERATION) && !defined(SPI_OPERATION)) + rtk_uint32 rawData=0, ACK; + rtk_uint8 con; + rtk_uint32 ret = RT_ERR_OK; +#endif + + if(mAddrs > 0xFFFF) + return RT_ERR_INPUT; + + if(rData == NULL) + return RT_ERR_NULL_POINTER; + + *rData = 0; + +#if defined(MDC_MDIO_OPERATION) + /* Lock */ + rtlglue_drvMutexLock(); + + /* Write address control code to register 31 */ + MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_PHY_ID, MDC_MDIO_CTRL0_REG, MDC_MDIO_ADDR_OP); + + /* Write address to register 23 */ + MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_PHY_ID, MDC_MDIO_ADDRESS_REG, mAddrs); + + /* Write read control code to register 21 */ + MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_PHY_ID, MDC_MDIO_CTRL1_REG, MDC_MDIO_READ_OP); + + /* Read data from register 25 */ + MDC_MDIO_READ(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_PHY_ID, MDC_MDIO_DATA_READ_REG, rData); + + /* Unlock */ + rtlglue_drvMutexUnlock(); + + return RT_ERR_OK; + +#elif defined(SPI_OPERATION) + /* Lock */ + rtlglue_drvMutexLock(); + + /* Write 8 bits READ OP_CODE */ + SPI_WRITE(SPI_READ_OP, SPI_READ_OP_LEN); + + /* Write 16 bits register address */ + SPI_WRITE(mAddrs, SPI_REG_LEN); + + /* Read 16 bits data */ + SPI_READ(rData, SPI_DATA_LEN); + + /* Unlock */ + rtlglue_drvMutexUnlock(); + + return RT_ERR_OK; + +#else + /*Disable CPU interrupt to ensure that the SMI operation is atomic. + The API is based on RTL865X, rewrite the API if porting to other platform.*/ + rtlglue_drvMutexLock(); + + _smi_start(); /* Start SMI */ + + _smi_writeBit(0x0b, 4); /* CTRL code: 4'b1011 for RTL8370 */ + + _smi_writeBit(0x4, 3); /* CTRL code: 3'b100 */ + + _smi_writeBit(0x1, 1); /* 1: issue READ command */ + + con = 0; + do { + con++; + _smi_readBit(1, &ACK); /* ACK for issuing READ command*/ + } while ((ACK != 0) && (con < ack_timer)); + + if (ACK != 0) ret = RT_ERR_FAILED; + + _smi_writeBit((mAddrs&0xff), 8); /* Set reg_addr[7:0] */ + + con = 0; + do { + con++; + _smi_readBit(1, &ACK); /* ACK for setting reg_addr[7:0] */ + } while ((ACK != 0) && (con < ack_timer)); + + if (ACK != 0) ret = RT_ERR_FAILED; + + _smi_writeBit((mAddrs>>8), 8); /* Set reg_addr[15:8] */ + + con = 0; + do { + con++; + _smi_readBit(1, &ACK); /* ACK by RTL8369 */ + } while ((ACK != 0) && (con < ack_timer)); + if (ACK != 0) ret = RT_ERR_FAILED; + + _smi_readBit(8, &rawData); /* Read DATA [7:0] */ + *rData = rawData&0xff; + + _smi_writeBit(0x00, 1); /* ACK by CPU */ + + _smi_readBit(8, &rawData); /* Read DATA [15: 8] */ + + _smi_writeBit(0x01, 1); /* ACK by CPU */ + *rData |= (rawData<<8); + + _smi_stop(); + + rtlglue_drvMutexUnlock();/*enable CPU interrupt*/ + + return ret; +#endif /* end of #if defined(MDC_MDIO_OPERATION) */ +} + + + +rtk_int32 rtl8367c_smi_write(rtk_uint32 mAddrs, rtk_uint32 rData) +{ +#if (!defined(MDC_MDIO_OPERATION) && !defined(SPI_OPERATION)) + rtk_int8 con; + rtk_uint32 ACK; + rtk_uint32 ret = RT_ERR_OK; +#endif + + if(mAddrs > 0xFFFF) + return RT_ERR_INPUT; + + if(rData > 0xFFFF) + return RT_ERR_INPUT; + +#if defined(MDC_MDIO_OPERATION) + + /* Lock */ + rtlglue_drvMutexLock(); + + /* Write address control code to register 31 */ + MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_PHY_ID, MDC_MDIO_CTRL0_REG, MDC_MDIO_ADDR_OP); + + /* Write address to register 23 */ + MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_PHY_ID, MDC_MDIO_ADDRESS_REG, mAddrs); + + /* Write data to register 24 */ + MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_PHY_ID, MDC_MDIO_DATA_WRITE_REG, rData); + + /* Write data control code to register 21 */ + MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_PHY_ID, MDC_MDIO_CTRL1_REG, MDC_MDIO_WRITE_OP); + + /* Unlock */ + rtlglue_drvMutexUnlock(); + + return RT_ERR_OK; + +#elif defined(SPI_OPERATION) + + /* Lock */ + rtlglue_drvMutexLock(); + + /* Write 8 bits WRITE OP_CODE */ + SPI_WRITE(SPI_WRITE_OP, SPI_WRITE_OP_LEN); + + /* Write 16 bits register address */ + SPI_WRITE(mAddrs, SPI_REG_LEN); + + /* Write 16 bits data */ + SPI_WRITE(rData, SPI_DATA_LEN); + + /* Unlock */ + rtlglue_drvMutexUnlock(); + + return RT_ERR_OK; +#else + + /*Disable CPU interrupt to ensure that the SMI operation is atomic. + The API is based on RTL865X, rewrite the API if porting to other platform.*/ + rtlglue_drvMutexLock(); + + _smi_start(); /* Start SMI */ + + _smi_writeBit(0x0b, 4); /* CTRL code: 4'b1011 for RTL8370*/ + + _smi_writeBit(0x4, 3); /* CTRL code: 3'b100 */ + + _smi_writeBit(0x0, 1); /* 0: issue WRITE command */ + + con = 0; + do { + con++; + _smi_readBit(1, &ACK); /* ACK for issuing WRITE command*/ + } while ((ACK != 0) && (con < ack_timer)); + if (ACK != 0) ret = RT_ERR_FAILED; + + _smi_writeBit((mAddrs&0xff), 8); /* Set reg_addr[7:0] */ + + con = 0; + do { + con++; + _smi_readBit(1, &ACK); /* ACK for setting reg_addr[7:0] */ + } while ((ACK != 0) && (con < ack_timer)); + if (ACK != 0) ret = RT_ERR_FAILED; + + _smi_writeBit((mAddrs>>8), 8); /* Set reg_addr[15:8] */ + + con = 0; + do { + con++; + _smi_readBit(1, &ACK); /* ACK for setting reg_addr[15:8] */ + } while ((ACK != 0) && (con < ack_timer)); + if (ACK != 0) ret = RT_ERR_FAILED; + + _smi_writeBit(rData&0xff, 8); /* Write Data [7:0] out */ + + con = 0; + do { + con++; + _smi_readBit(1, &ACK); /* ACK for writting data [7:0] */ + } while ((ACK != 0) && (con < ack_timer)); + if (ACK != 0) ret = RT_ERR_FAILED; + + _smi_writeBit(rData>>8, 8); /* Write Data [15:8] out */ + + con = 0; + do { + con++; + _smi_readBit(1, &ACK); /* ACK for writting data [15:8] */ + } while ((ACK != 0) && (con < ack_timer)); + if (ACK != 0) ret = RT_ERR_FAILED; + + _smi_stop(); + + rtlglue_drvMutexUnlock();/*enable CPU interrupt*/ + + return ret; +#endif /* end of #if defined(MDC_MDIO_OPERATION) */ +} + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_smi.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_smi.h new file mode 100644 index 00000000..e6e8550f --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367c/rtl8367c_smi.h @@ -0,0 +1,41 @@ + +#ifndef __SMI_H__ +#define __SMI_H__ + +#include +#include "rtk_error.h" + +#define MDC_MDIO_CTRL0_REG 31 +#define MDC_MDIO_START_REG 29 +#define MDC_MDIO_CTRL1_REG 21 +#define MDC_MDIO_ADDRESS_REG 23 +#define MDC_MDIO_DATA_WRITE_REG 24 +#define MDC_MDIO_DATA_READ_REG 25 +#define MDC_MDIO_PREAMBLE_LEN 32 + +#define MDC_MDIO_START_OP 0xFFFF +#define MDC_MDIO_ADDR_OP 0x000E +#define MDC_MDIO_READ_OP 0x0001 +#define MDC_MDIO_WRITE_OP 0x0003 + +#define SPI_READ_OP 0x3 +#define SPI_WRITE_OP 0x2 +#define SPI_READ_OP_LEN 0x8 +#define SPI_WRITE_OP_LEN 0x8 +#define SPI_REG_LEN 16 +#define SPI_DATA_LEN 16 + +#define GPIO_DIR_IN 1 +#define GPIO_DIR_OUT 0 + +#define ack_timer 5 + +#define DELAY 10000 +#define CLK_DURATION(clk) { int i; for(i=0; i +#include +#include +#include +#include + +#include + +#if defined(CONFIG_RTL8367D_ASICDRV_TEST) +rtl8367d_aclrulesmi Rtl8370sVirtualAclRuleTable[RTL8367D_ACLRULENO]; +rtk_uint16 Rtl8370sVirtualAclActTable[RTL8367D_ACLRULENO][RTL8367D_ACL_ACT_TABLE_LEN]; +#endif + + +CONST_T rtk_uint8 rtl8367D_filter_templateField[RTL8367D_ACLTEMPLATENO][RTL8367D_ACLRULEFIELDNO] = { + {RTL8367D_ACL_DMAC0, RTL8367D_ACL_DMAC1, RTL8367D_ACL_DMAC2, RTL8367D_ACL_SMAC0, RTL8367D_ACL_SMAC1, RTL8367D_ACL_SMAC2, RTL8367D_ACL_ETHERTYPE, RTL8367D_ACL_FIELD_SELECT07}, + {RTL8367D_ACL_IP4SIP0, RTL8367D_ACL_IP4SIP1, RTL8367D_ACL_IP4DIP0, RTL8367D_ACL_IP4DIP1, RTL8367D_ACL_L4SPORT, RTL8367D_ACL_L4DPORT, RTL8367D_ACL_FIELD_SELECT02, RTL8367D_ACL_FIELD_SELECT07}, + {RTL8367D_ACL_IP6SIP0WITHIPV4, RTL8367D_ACL_IP6SIP1WITHIPV4,RTL8367D_ACL_L4SPORT, RTL8367D_ACL_L4DPORT, RTL8367D_ACL_FIELD_SELECT05, RTL8367D_ACL_FIELD_SELECT06, RTL8367D_ACL_FIELD_SELECT00, RTL8367D_ACL_FIELD_SELECT01}, + {RTL8367D_ACL_IP6DIP0WITHIPV4, RTL8367D_ACL_IP6DIP1WITHIPV4,RTL8367D_ACL_L4SPORT, RTL8367D_ACL_L4DPORT, RTL8367D_ACL_FIELD_SELECT00, RTL8367D_ACL_FIELD_SELECT03, RTL8367D_ACL_FIELD_SELECT04, RTL8367D_ACL_FIELD_SELECT07}, + {RTL8367D_ACL_FIELD_SELECT01, RTL8367D_ACL_IPRANGE, RTL8367D_ACL_FIELD_SELECT02, RTL8367D_ACL_CTAG, RTL8367D_ACL_STAG, RTL8367D_ACL_FIELD_SELECT04, RTL8367D_ACL_FIELD_SELECT03, RTL8367D_ACL_FIELD_SELECT07} +}; + +CONST_T rtk_uint8 rtl8367D_filter_advanceCaretagField[RTL8367D_ACLTEMPLATENO][2] = { + {TRUE, 7}, + {TRUE, 7}, + {FALSE, 0}, + {TRUE, 7}, + {TRUE, 7}, +}; + + +CONST_T rtk_uint8 rtl8367D_filter_fieldTemplateIndex[FILTER_FIELD_END][RTK_FILTER_FIELD_USED_MAX] = { + {0x00, 0x01,0x02}, + {0x03, 0x04,0x05}, + {0x06}, + {0x43}, + {0x44}, + {0x10, 0x11}, + {0x12, 0x13}, + {0x24}, + {0x25}, + {0x35}, + {0x35}, + {0x20, 0x21}, + {0x30, 0x31}, + {0x26}, + {0x27}, + {0x14}, + {0x15}, + {0x16}, + {0x14}, + {0x15}, + {0x14}, + {0x14}, + {0x14}, + + {0}, + {0x41}, + {0}, + + {0x26}, + {0x27}, + {0x16}, + {0x35}, + {0x36}, + {0x24}, + {0x25}, + {0x47}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + + {0xFF} /* Pattern Match */ +}; + +CONST_T rtk_uint8 rtl8367D_filter_fieldSize[FILTER_FIELD_END] = { + 3, 3, 1, 1, 1, + 2, 2, 1, 1, 1, 1, 2, 2, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, + 0,1,0, + 1, 1, 1, 1, 1, 1, 1, 1, + 0, 0, 0, 0, 0, 0, 0, 0, + 8 +}; + +CONST_T rtk_uint16 rtl8367D_field_selector[RTL8367D_FIELDSEL_FORMAT_NUMBER][2] = +{ + {RTL8367D_FIELDSEL_FORMAT_IPV6, 0}, /* Field Selector 0 */ + {RTL8367D_FIELDSEL_FORMAT_IPV6, 6}, /* Field Selector 1 */ + {RTL8367D_FIELDSEL_FORMAT_IPPAYLOAD, 12}, /* Field Selector 2 */ + {RTL8367D_FIELDSEL_FORMAT_IPV4, 6}, /* Field Selector 3 */ + {RTL8367D_FIELDSEL_FORMAT_IPPAYLOAD, 0}, /* Field Selector 4 */ + {RTL8367D_FIELDSEL_FORMAT_IPV4, 0}, /* Field Selector 5 */ + {RTL8367D_FIELDSEL_FORMAT_IPV4, 8}, /* Field Selector 6 */ + {RTL8367D_FIELDSEL_FORMAT_DEFAULT, 0} /* Field Selector 7 */ +}; + +/* + Exchange structure type define with MMI and SMI +*/ +static void _rtl8367d_aclRuleStSmi2User( rtl8367d_aclrule *pAclUser, rtl8367d_aclrulesmi *pAclSmi) +{ + rtk_uint8 *care_ptr, *data_ptr; + rtk_uint8 care_tmp, data_tmp; + rtk_uint8 care_pmask, data_pmask; + rtk_uint32 i; + + care_ptr = (rtk_uint8*)&pAclSmi->care_bits; + data_ptr = (rtk_uint8*)&pAclSmi->data_bits; + + for ( i = 0; i < sizeof(struct rtl8367d_acl_rule_smi_st); i++) + { + care_tmp = *(care_ptr + i) ^ (*(data_ptr + i)); + data_tmp = ~(*(care_ptr + i)) & *(data_ptr + i); + + *(care_ptr + i) = care_tmp; + *(data_ptr + i) = data_tmp; + } + + pAclUser->data_bits.active_portmsk = ((pAclSmi->data_bits.rule_info >> 8) & 0x00FF); + pAclUser->data_bits.type = (pAclSmi->data_bits.rule_info & 0x0007); + pAclUser->data_bits.tag_exist = (pAclSmi->data_bits.rule_info & 0x00F8) >> 3; + + for(i = 0; i < RTL8367D_ACLRULEFIELDNO; i++) + pAclUser->data_bits.field[i] = pAclSmi->data_bits.field[i]; + + pAclUser->valid = pAclSmi->valid; + + pAclUser->care_bits.active_portmsk = ((pAclSmi->care_bits.rule_info >> 8) & 0x00FF); + pAclUser->care_bits.type = (pAclSmi->care_bits.rule_info & 0x0007); + pAclUser->care_bits.tag_exist = (pAclSmi->care_bits.rule_info & 0x00F8) >> 3; + + + care_pmask = pAclUser->care_bits.active_portmsk & 0xff; + data_pmask = pAclUser->data_bits.active_portmsk & 0xff; + + for (i = 0; i <= 7; i++) + { + if( ((care_pmask & (0x01 << i)) == 0 )&&( (data_pmask & (0x01 << i)) == 0) ) + { + care_pmask |= (0x01 << i); + data_pmask |= (0x01 << i); + } + } + + pAclUser->care_bits.active_portmsk = care_pmask; + pAclUser->data_bits.active_portmsk = data_pmask; + + for(i = 0; i < RTL8367D_ACLRULEFIELDNO; i++) + pAclUser->care_bits.field[i] = pAclSmi->care_bits.field[i]; +} + +/* + Exchange structure type define with MMI and SMI +*/ +static void _rtl8367d_aclRuleStUser2Smi(rtl8367d_aclrule *pAclUser, rtl8367d_aclrulesmi *pAclSmi) +{ + rtk_uint8 *care_ptr, *data_ptr; + rtk_uint8 care_tmp, data_tmp; + rtk_uint8 care_pmask, data_pmask; + rtk_uint32 i; + + care_pmask = pAclUser->care_bits.active_portmsk & 0xff; + data_pmask = pAclUser->data_bits.active_portmsk & 0xff; + + for (i = 0; i <= 7; i++) + { + if( (care_pmask & (0x01 << i)) && (data_pmask & (0x01 << i)) ) + { + care_pmask &= ~(0x01 << i); + data_pmask &= ~(0x01 << i); + } + } + pAclSmi->data_bits.rule_info = (data_pmask << 8) | ((pAclUser->data_bits.tag_exist & 0x1F) << 3) | (pAclUser->data_bits.type & 0x07); + + for(i = 0;i < RTL8367D_ACLRULEFIELDNO; i++) + pAclSmi->data_bits.field[i] = pAclUser->data_bits.field[i]; + + pAclSmi->valid = pAclUser->valid; + + pAclSmi->care_bits.rule_info = (care_pmask << 8) | ((pAclUser->care_bits.tag_exist & 0x1F) << 3) | (pAclUser->care_bits.type & 0x07); + + for(i = 0; i < RTL8367D_ACLRULEFIELDNO; i++) + pAclSmi->care_bits.field[i] = pAclUser->care_bits.field[i]; + + care_ptr = (rtk_uint8*)&pAclSmi->care_bits; + data_ptr = (rtk_uint8*)&pAclSmi->data_bits; + + for ( i = 0; i < sizeof(struct rtl8367d_acl_rule_smi_st); i++) + { + care_tmp = ~(*(care_ptr + i)) | ~(*(data_ptr + i)); + data_tmp = ~(*(care_ptr + i)) | *(data_ptr + i); + + *(care_ptr + i) = care_tmp; + *(data_ptr + i) = data_tmp; + } +} + +/* + Exchange structure type define with MMI and SMI +*/ +static void _rtl8367d_aclActStSmi2User(rtl8367d_acl_act_t *pAclUser, rtk_uint16 *pAclSmi) +{ + + pAclUser->cact = (pAclSmi[0] & 0x3000) >> 12; + pAclUser->cvidx_cact = (pAclSmi[0] & 0x0FFF); + + pAclUser->sact = (pAclSmi[1] & 0x0C00) >> 10; + pAclUser->svidx_sact = ((pAclSmi[0] & 0xC000) >> 14) | ((pAclSmi[1] & 0x03FF) << 2); + + pAclUser->aclmeteridx = ((pAclSmi[1] & 0xF000) >> 12) | ((pAclSmi[2] & 0x0003) << 4); + + pAclUser->fwdact = (pAclSmi[2] & 0x0C00) >> 10; + pAclUser->fwdpmask = ((pAclSmi[2] & 0x03FC) >> 2); + + pAclUser->priact = (pAclSmi[3] & 0x000C) >> 2; + pAclUser->pridx = ((pAclSmi[2] & 0xF000) >> 12) | ((pAclSmi[3] & 0x0003) << 4); + + pAclUser->aclint = (pAclSmi[3] & 0x0400) >> 10; + pAclUser->gpio_pin = (pAclSmi[3] & 0x03F0) >> 4; + if(pAclUser->gpio_pin == 0) + pAclUser->gpio_en = DISABLED; + else + pAclUser->gpio_en = ENABLED; + + pAclUser->cact_ext = (pAclSmi[3] & 0x1800) >> 11; + pAclUser->tag_fmt = (pAclSmi[3] & 0x6000) >> 13; + pAclUser->fwdact_ext = (pAclSmi[3] & 0x8000) >> 15; +} + +/* + Exchange structure type define with MMI and SMI +*/ +static void _rtl8367d_aclActStUser2Smi(rtl8367d_acl_act_t *pAclUser, rtk_uint16 *pAclSmi) +{ + if(pAclUser->gpio_en == DISABLED) + pAclUser->gpio_pin = 0; + pAclSmi[0] |= (pAclUser->cvidx_cact & 0x0FFF); + pAclSmi[0] |= (pAclUser->cact & 0x0003) << 12; + pAclSmi[0] |= (pAclUser->svidx_sact & 0x0003) << 14; + + pAclSmi[1] |= (pAclUser->svidx_sact & 0x0FFC) >> 2; + pAclSmi[1] |= (pAclUser->sact & 0x0003) << 10; + pAclSmi[1] |= (pAclUser->aclmeteridx & 0x000F) << 12; + pAclSmi[2] |= (pAclUser->aclmeteridx & 0x0030) >> 4; + pAclSmi[2] |= (pAclUser->fwdpmask & 0x00FF) << 2; + pAclSmi[2] |= (pAclUser->fwdact & 0x0003) << 10; + pAclSmi[2] |= (pAclUser->pridx & 0x000F) << 12; + + pAclSmi[3] |= (pAclUser->pridx & 0x0030) >> 4; + pAclSmi[3] |= (pAclUser->priact & 0x0003) << 2; + pAclSmi[3] |= (pAclUser->gpio_pin & 0x003F) << 4; + pAclSmi[3] |= (pAclUser->aclint & 0x0001) << 10; + pAclSmi[3] |= (pAclUser->cact_ext & 0x0003) << 11; + pAclSmi[3] |= (pAclUser->tag_fmt & 0x0003) << 13; + pAclSmi[3] |= (pAclUser->fwdact_ext & 0x0001) << 15; +} + +static rtk_api_ret_t _rtl8367d_getAsicAclTemplate(rtk_uint32 index, rtl8367d_acltemplate_t *pAclType) +{ + ret_t retVal; + rtk_uint32 i; + rtk_uint32 regData, regAddr; + + if(index >= RTL8367D_ACLTEMPLATENO) + return RT_ERR_OUT_OF_RANGE; + + regAddr = (RTL8367D_REG_ACL_RULE_TEMPLATE0_CTRL0 + index * 0x4); + + for(i = 0; i < (RTL8367D_ACLRULEFIELDNO/2); i++) + { + retVal = rtl8367d_getAsicReg(regAddr + i,®Data); + if(retVal != RT_ERR_OK) + return retVal; + + pAclType->field[i*2] = regData & 0xFF; + pAclType->field[i*2 + 1] = (regData >> 8) & 0xFF; + } + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8367d_filter_igrAcl_cfg_delAll + * Description: + * Delete all ACL entries from ASIC + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This function delete all ACL configuration from ASIC. + */ +rtk_api_ret_t dal_rtl8367d_filter_igrAcl_cfg_delAll(void) +{ + rtk_uint32 i; + rtk_api_ret_t ret; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + for(i = 0; i < RTL8367D_ACLRULENO; i++) + { + if((ret = rtl8367d_setAsicRegBits(RTL8367D_REG_ACL_ACTION_CTRL0 + (i >> 1), (0x3F << ((i & 0x1) << 3)), FILTER_ENACT_INIT_MASK))!= RT_ERR_OK) + return ret; + + if((ret = rtl8367d_setAsicRegBit(RTL8367D_REG_ACL_ACTION_CTRL0 + (i >> 1), (6 + ((i & 0x1) << 3)), DISABLED)) != RT_ERR_OK ) + return ret; + } + + return rtl8367d_setAsicRegBit(RTL8367D_REG_ACL_RESET_CFG, RTL8367D_ACL_RESET_CFG_OFFSET, TRUE);; +} + +static rtk_api_ret_t _rtl8367d_setAclTemplate(rtk_uint32 index, rtl8367d_acltemplate_t* pAclType) +{ + ret_t retVal; + rtk_uint32 i; + rtk_uint32 regAddr, regData; + + if(index >= RTL8367D_ACLTEMPLATENO) + return RT_ERR_OUT_OF_RANGE; + + regAddr = (RTL8367D_REG_ACL_RULE_TEMPLATE0_CTRL0 + index * 0x4); + + for(i = 0; i < (RTL8367D_ACLRULEFIELDNO/2); i++) + { + regData = pAclType->field[i*2+1]; + regData = regData << 8 | pAclType->field[i*2]; + + retVal = rtl8367d_setAsicReg(regAddr + i, regData); + + if(retVal != RT_ERR_OK) + return retVal; + } + + return retVal; +} + + +/* Function Name: + * dal_rtl8367d_filter_igrAcl_init + * Description: + * ACL initialization function + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Pointer pFilter_field or pFilter_cfg point to NULL. + * Note: + * This function enable and intialize ACL function + */ +rtk_api_ret_t dal_rtl8367d_filter_igrAcl_init(void) +{ + rtl8367d_acltemplate_t aclTemp; + rtk_uint32 i, j; + rtk_api_ret_t ret; + rtk_uint32 regData; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if ((ret = dal_rtl8367d_filter_igrAcl_cfg_delAll()) != RT_ERR_OK) + return ret; + + for(i = 0; i < RTL8367D_ACLTEMPLATENO; i++) + { + for(j = 0; j < RTL8367D_ACLRULEFIELDNO;j++) + aclTemp.field[j] = rtl8367D_filter_templateField[i][j]; + + if ((ret = _rtl8367d_setAclTemplate(i, &aclTemp)) != RT_ERR_OK) + return ret; + } + + for(i = 0; i < RTL8367D_FIELDSEL_FORMAT_NUMBER; i++) + { + regData = (((rtl8367D_field_selector[i][0] << RTL8367D_FIELD_SELECTOR0_FORMAT_OFFSET) & RTL8367D_FIELD_SELECTOR0_FORMAT_MASK ) | + ((rtl8367D_field_selector[i][1] << RTL8367D_FIELD_SELECTOR0_OFFSET_OFFSET) & RTL8367D_FIELD_SELECTOR0_OFFSET_MASK )); + + if ((ret = rtl8367d_setAsicReg((RTL8367D_REG_FIELD_SELECTOR0 + i), regData)) != RT_ERR_OK) + return ret; + } + + RTK_SCAN_ALL_PHY_PORTMASK(i) + { + + if ((ret = rtl8367d_setAsicRegBit(RTL8367D_REG_ACL_ENABLE, i, TRUE)) != RT_ERR_OK) + return ret; + + if ((ret = rtl8367d_setAsicRegBit(RTL8367D_REG_ACL_UNMATCH_PERMIT, i, TRUE)) != RT_ERR_OK) + return ret; + } + +#ifdef CONFIG_RTL8367D_ASICDRV_TEST + for(i=0;ifieldType >= FILTER_FIELD_END) + return RT_ERR_ENTRY_INDEX; + + + if(0 == pFilter_field->fieldTemplateNo) + { + pFilter_field->fieldTemplateNo = rtl8367D_filter_fieldSize[pFilter_field->fieldType]; + + for(i = 0; i < pFilter_field->fieldTemplateNo; i++) + { + pFilter_field->fieldTemplateIdx[i] = rtl8367D_filter_fieldTemplateIndex[pFilter_field->fieldType][i]; + } + } + + if(NULL == pFilter_cfg->fieldHead) + { + pFilter_cfg->fieldHead = pFilter_field; + } + else + { + if (pFilter_cfg->fieldHead->next == NULL) + { + pFilter_cfg->fieldHead->next = pFilter_field; + } + else + { + tailPtr = pFilter_cfg->fieldHead->next; + while( tailPtr->next != NULL) + { + tailPtr = tailPtr->next; + } + tailPtr->next = pFilter_field; + } + } + + return RT_ERR_OK; +} + +static rtk_api_ret_t _rtk_filter_igrAcl_writeDataField(rtl8367d_aclrule *aclRule, rtk_filter_field_t *fieldPtr) +{ + rtk_uint32 i, tempIdx,fieldIdx, ipValue, ipMask; + rtk_uint32 ip6addr[RTL8367D_RTK_IPV6_ADDR_WORD_LENGTH]; + rtk_uint32 ip6mask[RTL8367D_RTK_IPV6_ADDR_WORD_LENGTH]; + + for(i = 0; i < fieldPtr->fieldTemplateNo; i++) + { + tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4; + + aclRule[tempIdx].valid = TRUE; + } + + switch (fieldPtr->fieldType) + { + /* use DMAC structure as representative for mac structure */ + case FILTER_FIELD_DMAC: + case FILTER_FIELD_SMAC: + + for(i = 0; i < fieldPtr->fieldTemplateNo; i++) + { + tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4; + fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F; + + aclRule[tempIdx].data_bits.field[fieldIdx] = fieldPtr->filter_pattern_union.mac.value.octet[5 - i*2] | (fieldPtr->filter_pattern_union.mac.value.octet[5 - (i*2 + 1)] << 8); + aclRule[tempIdx].care_bits.field[fieldIdx] = fieldPtr->filter_pattern_union.mac.mask.octet[5 - i*2] | (fieldPtr->filter_pattern_union.mac.mask.octet[5 - (i*2 + 1)] << 8); + } + break; + case FILTER_FIELD_ETHERTYPE: + for(i = 0; i < fieldPtr->fieldTemplateNo; i++) + { + tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4; + fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F; + + aclRule[tempIdx].data_bits.field[fieldIdx] = fieldPtr->filter_pattern_union.etherType.value; + aclRule[tempIdx].care_bits.field[fieldIdx] = fieldPtr->filter_pattern_union.etherType.mask; + } + break; + case FILTER_FIELD_IPV4_SIP: + case FILTER_FIELD_IPV4_DIP: + + ipValue = fieldPtr->filter_pattern_union.sip.value; + ipMask = fieldPtr->filter_pattern_union.sip.mask; + + for(i = 0; i < fieldPtr->fieldTemplateNo; i++) + { + tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4; + fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F; + + aclRule[tempIdx].data_bits.field[fieldIdx] = (0xFFFF & (ipValue >> (i*16))); + aclRule[tempIdx].care_bits.field[fieldIdx] = (0xFFFF & (ipMask >> (i*16))); + } + break; + case FILTER_FIELD_IPV4_TOS: + for(i = 0; i < fieldPtr->fieldTemplateNo; i++) + { + tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4; + fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F; + + aclRule[tempIdx].data_bits.field[fieldIdx] = fieldPtr->filter_pattern_union.ipTos.value & 0xFF; + aclRule[tempIdx].care_bits.field[fieldIdx] = fieldPtr->filter_pattern_union.ipTos.mask & 0xFF; + } + break; + case FILTER_FIELD_IPV4_PROTOCOL: + for(i = 0; i < fieldPtr->fieldTemplateNo; i++) + { + tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4; + fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F; + + aclRule[tempIdx].data_bits.field[fieldIdx] = fieldPtr->filter_pattern_union.protocol.value & 0xFF; + aclRule[tempIdx].care_bits.field[fieldIdx] = fieldPtr->filter_pattern_union.protocol.mask & 0xFF; + } + break; + case FILTER_FIELD_IPV6_SIPV6: + case FILTER_FIELD_IPV6_DIPV6: + for(i = 0; i < RTL8367D_RTK_IPV6_ADDR_WORD_LENGTH; i++) + { + ip6addr[i] = fieldPtr->filter_pattern_union.sipv6.value.addr[i]; + ip6mask[i] = fieldPtr->filter_pattern_union.sipv6.mask.addr[i]; + } + + for(i = 0; i < fieldPtr->fieldTemplateNo; i++) + { + tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4; + fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F; + + if(i < 2) + { + aclRule[tempIdx].data_bits.field[fieldIdx] = ((ip6addr[0] & (0xFFFF << (i * 16))) >> (i * 16)); + aclRule[tempIdx].care_bits.field[fieldIdx] = ((ip6mask[0] & (0xFFFF << (i * 16))) >> (i * 16)); + } + } + + break; + case FILTER_FIELD_CTAG: + case FILTER_FIELD_STAG: + + for(i = 0; i < fieldPtr->fieldTemplateNo; i++) + { + tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4; + fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F; + + aclRule[tempIdx].data_bits.field[fieldIdx] = (fieldPtr->filter_pattern_union.l2tag.pri.value << 13) | (fieldPtr->filter_pattern_union.l2tag.cfi.value << 12) | fieldPtr->filter_pattern_union.l2tag.vid.value; + aclRule[tempIdx].care_bits.field[fieldIdx] = (fieldPtr->filter_pattern_union.l2tag.pri.mask << 13) | (fieldPtr->filter_pattern_union.l2tag.cfi.mask << 12) | fieldPtr->filter_pattern_union.l2tag.vid.mask; + } + break; + case FILTER_FIELD_IPV4_FLAG: + + for(i = 0; i < fieldPtr->fieldTemplateNo; i++) + { + tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4; + fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F; + + aclRule[tempIdx].data_bits.field[fieldIdx] &= 0x1FFF; + aclRule[tempIdx].data_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.ipFlag.xf.value << 15); + aclRule[tempIdx].data_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.ipFlag.df.value << 14); + aclRule[tempIdx].data_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.ipFlag.mf.value << 13); + + aclRule[tempIdx].care_bits.field[fieldIdx] &= 0x1FFF; + aclRule[tempIdx].care_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.ipFlag.xf.mask << 15); + aclRule[tempIdx].care_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.ipFlag.df.mask << 14); + aclRule[tempIdx].care_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.ipFlag.mf.mask << 13); + } + + break; + case FILTER_FIELD_IPV4_OFFSET: + + for(i = 0; i < fieldPtr->fieldTemplateNo; i++) + { + tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4; + fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F; + + aclRule[tempIdx].data_bits.field[fieldIdx] &= 0xE000; + aclRule[tempIdx].data_bits.field[fieldIdx] |= fieldPtr->filter_pattern_union.inData.value; + + aclRule[tempIdx].care_bits.field[fieldIdx] &= 0xE000; + aclRule[tempIdx].care_bits.field[fieldIdx] |= fieldPtr->filter_pattern_union.inData.mask; + } + + break; + + case FILTER_FIELD_IPV6_TRAFFIC_CLASS: + for(i = 0; i < fieldPtr->fieldTemplateNo; i++) + { + tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4; + fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F; + + + aclRule[tempIdx].data_bits.field[fieldIdx] = (fieldPtr->filter_pattern_union.inData.value << 4)&0x0FF0; + aclRule[tempIdx].care_bits.field[fieldIdx] = (fieldPtr->filter_pattern_union.inData.mask << 4)&0x0FF0; + } + break; + case FILTER_FIELD_IPV6_NEXT_HEADER: + for(i = 0; i < fieldPtr->fieldTemplateNo; i++) + { + tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4; + fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F; + + aclRule[tempIdx].data_bits.field[fieldIdx] = fieldPtr->filter_pattern_union.inData.value << 8; + aclRule[tempIdx].care_bits.field[fieldIdx] = fieldPtr->filter_pattern_union.inData.mask << 8; + } + break; + case FILTER_FIELD_TCP_SPORT: + for(i = 0; i < fieldPtr->fieldTemplateNo; i++) + { + tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4; + fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F; + + aclRule[tempIdx].data_bits.field[fieldIdx] = fieldPtr->filter_pattern_union.tcpSrcPort.value; + aclRule[tempIdx].care_bits.field[fieldIdx] = fieldPtr->filter_pattern_union.tcpSrcPort.mask; + } + break; + case FILTER_FIELD_TCP_DPORT: + for(i = 0; i < fieldPtr->fieldTemplateNo; i++) + { + tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4; + fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F; + + aclRule[tempIdx].data_bits.field[fieldIdx] = fieldPtr->filter_pattern_union.tcpDstPort.value; + aclRule[tempIdx].care_bits.field[fieldIdx] = fieldPtr->filter_pattern_union.tcpDstPort.mask; + } + break; + case FILTER_FIELD_TCP_FLAG: + + for(i = 0; i < fieldPtr->fieldTemplateNo; i++) + { + tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4; + fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F; + + aclRule[tempIdx].data_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.tcpFlag.cwr.value << 7); + aclRule[tempIdx].data_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.tcpFlag.ece.value << 6); + aclRule[tempIdx].data_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.tcpFlag.urg.value << 5); + aclRule[tempIdx].data_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.tcpFlag.ack.value << 4); + aclRule[tempIdx].data_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.tcpFlag.psh.value << 3); + aclRule[tempIdx].data_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.tcpFlag.rst.value << 2); + aclRule[tempIdx].data_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.tcpFlag.syn.value << 1); + aclRule[tempIdx].data_bits.field[fieldIdx] |= fieldPtr->filter_pattern_union.tcpFlag.fin.value; + + aclRule[tempIdx].care_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.tcpFlag.cwr.mask << 7); + aclRule[tempIdx].care_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.tcpFlag.ece.mask << 6); + aclRule[tempIdx].care_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.tcpFlag.urg.mask << 5); + aclRule[tempIdx].care_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.tcpFlag.ack.mask << 4); + aclRule[tempIdx].care_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.tcpFlag.psh.mask << 3); + aclRule[tempIdx].care_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.tcpFlag.rst.mask << 2); + aclRule[tempIdx].care_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.tcpFlag.syn.mask << 1); + aclRule[tempIdx].care_bits.field[fieldIdx] |= fieldPtr->filter_pattern_union.tcpFlag.fin.mask; + } + break; + case FILTER_FIELD_UDP_SPORT: + for(i = 0; i < fieldPtr->fieldTemplateNo; i++) + { + tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4; + fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F; + + aclRule[tempIdx].data_bits.field[fieldIdx] = fieldPtr->filter_pattern_union.udpSrcPort.value; + aclRule[tempIdx].care_bits.field[fieldIdx] = fieldPtr->filter_pattern_union.udpSrcPort.mask; + } + break; + case FILTER_FIELD_UDP_DPORT: + for(i = 0; i < fieldPtr->fieldTemplateNo; i++) + { + tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4; + fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F; + + aclRule[tempIdx].data_bits.field[fieldIdx] = fieldPtr->filter_pattern_union.udpDstPort.value; + aclRule[tempIdx].care_bits.field[fieldIdx] = fieldPtr->filter_pattern_union.udpDstPort.mask; + } + break; + case FILTER_FIELD_ICMP_CODE: + for(i = 0; i < fieldPtr->fieldTemplateNo; i++) + { + tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4; + fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F; + + aclRule[tempIdx].data_bits.field[fieldIdx] &= 0xFF00; + aclRule[tempIdx].data_bits.field[fieldIdx] |= fieldPtr->filter_pattern_union.icmpCode.value; + aclRule[tempIdx].care_bits.field[fieldIdx] &= 0xFF00; + aclRule[tempIdx].care_bits.field[fieldIdx] |= fieldPtr->filter_pattern_union.icmpCode.mask; + } + break; + case FILTER_FIELD_ICMP_TYPE: + for(i = 0; i < fieldPtr->fieldTemplateNo; i++) + { + tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4; + fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F; + + aclRule[tempIdx].data_bits.field[fieldIdx] &= 0x00FF; + aclRule[tempIdx].data_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.icmpType.value << 8); + aclRule[tempIdx].care_bits.field[fieldIdx] &= 0x00FF; + aclRule[tempIdx].care_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.icmpType.mask << 8); + } + break; + case FILTER_FIELD_IGMP_TYPE: + for(i = 0; i < fieldPtr->fieldTemplateNo; i++) + { + tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4; + fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F; + + aclRule[tempIdx].data_bits.field[fieldIdx] = (fieldPtr->filter_pattern_union.igmpType.value << 8); + aclRule[tempIdx].care_bits.field[fieldIdx] = (fieldPtr->filter_pattern_union.igmpType.mask << 8); + } + break; + case FILTER_FIELD_PATTERN_MATCH: + for(i = 0; i < fieldPtr->fieldTemplateNo; i++) + { + tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4; + fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F; + + aclRule[tempIdx].data_bits.field[fieldIdx] = ((fieldPtr->filter_pattern_union.pattern.value[i/2] >> (16 * (i%2))) & 0x0000FFFF ); + aclRule[tempIdx].care_bits.field[fieldIdx] = ((fieldPtr->filter_pattern_union.pattern.mask[i/2] >> (16 * (i%2))) & 0x0000FFFF ); + } + break; + case FILTER_FIELD_IP_RANGE: + default: + tempIdx = (fieldPtr->fieldTemplateIdx[0] & 0xF0) >> 4; + fieldIdx = fieldPtr->fieldTemplateIdx[0] & 0x0F; + + aclRule[tempIdx].data_bits.field[fieldIdx] = fieldPtr->filter_pattern_union.inData.value; + aclRule[tempIdx].care_bits.field[fieldIdx] = fieldPtr->filter_pattern_union.inData.mask; + break; + } + + return RT_ERR_OK; +} + +static rtk_api_ret_t _rtl8367d_getAclRule(rtk_uint32 index, rtl8367d_aclrule *pAclRule) +{ + rtl8367d_aclrulesmi aclRuleSmi; + rtk_uint32 regAddr, regData; + ret_t retVal; + rtk_uint16* tableAddr; + rtk_uint32 i; + + if(index > RTL8367D_ACLRULEMAX) + return RT_ERR_OUT_OF_RANGE; + + memset(&aclRuleSmi, 0x00, sizeof(rtl8367d_aclrulesmi)); + + /* Write ACS_ADR register for data bits */ + regAddr = RTL8367D_REG_TABLE_ACCESS_ADDR; + + regData = RTL8367D_ACLRULETBADDR(RTL8367D_DATABITS, index); + + retVal = rtl8367d_setAsicReg(regAddr, regData); + if(retVal != RT_ERR_OK) + return retVal; + + + /* Write ACS_CMD register */ + regAddr = RTL8367D_REG_TABLE_ACCESS_CTRL; + regData = RTL8367D_TABLE_ACCESS_REG_DATA(RTL8367D_TB_OP_READ, RTL8367D_TB_TARGET_ACLRULE); + retVal = rtl8367d_setAsicRegBits(regAddr, RTL8367D_TABLE_TYPE_MASK | RTL8367D_COMMAND_TYPE_MASK, regData); + if(retVal != RT_ERR_OK) + return retVal; + + /* Read Data Bits */ + regAddr = RTL8367D_REG_TABLE_READ_DATA0; + tableAddr = (rtk_uint16*)&aclRuleSmi.data_bits; + for(i = 0; i < RTL8367D_ACLRULETBLEN; i++) + { + retVal = rtl8367d_getAsicReg(regAddr, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + *tableAddr = regData; + + regAddr ++; + tableAddr ++; + } + + /* Read Valid Bit */ + retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_TABLE_READ_DATA0+RTL8367D_ACLRULETBLEN, 0, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + aclRuleSmi.valid = regData & 0x1; + + /* Write ACS_ADR register for carebits*/ + regAddr = RTL8367D_REG_TABLE_ACCESS_ADDR; + regData = RTL8367D_ACLRULETBADDR(RTL8367D_CAREBITS, index); + retVal = rtl8367d_setAsicReg(regAddr, regData); + if(retVal != RT_ERR_OK) + return retVal; + + /* Write ACS_CMD register */ + regAddr = RTL8367D_REG_TABLE_ACCESS_CTRL; + regData = RTL8367D_TABLE_ACCESS_REG_DATA(RTL8367D_TB_OP_READ, RTL8367D_TB_TARGET_ACLRULE); + retVal = rtl8367d_setAsicRegBits(regAddr, RTL8367D_TABLE_TYPE_MASK | RTL8367D_COMMAND_TYPE_MASK, regData); + if(retVal != RT_ERR_OK) + return retVal; + + /* Read Care Bits */ + regAddr = RTL8367D_REG_TABLE_READ_DATA0; + tableAddr = (rtk_uint16*)&aclRuleSmi.care_bits; + for(i = 0; i < RTL8367D_ACLRULETBLEN; i++) + { + retVal = rtl8367d_getAsicReg(regAddr, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + *tableAddr = regData; + + regAddr ++; + tableAddr ++; + } + +#ifdef CONFIG_RTL8367D_ASICDRV_TEST + memcpy(&aclRuleSmi,&Rtl8370sVirtualAclRuleTable[index], sizeof(rtl8367d_aclrulesmi)); +#endif + + _rtl8367d_aclRuleStSmi2User(pAclRule, &aclRuleSmi); + + return RT_ERR_OK; +} + +static rtk_api_ret_t _rtl8367d_setAclAct(rtk_uint32 index, rtl8367d_acl_act_t* pAclAct) +{ + rtk_uint16 aclActSmi[RTL8367D_ACL_ACT_TABLE_LEN]; + ret_t retVal; + rtk_uint32 regAddr, regData; + rtk_uint16* tableAddr; + rtk_uint32 i; + + if(index > RTL8367D_ACLRULEMAX) + return RT_ERR_OUT_OF_RANGE; + + memset(aclActSmi, 0x00, sizeof(rtk_uint16) * RTL8367D_ACL_ACT_TABLE_LEN); + _rtl8367d_aclActStUser2Smi(pAclAct, aclActSmi); + + /* Write ACS_ADR register for data bits */ + regAddr = RTL8367D_REG_TABLE_ACCESS_ADDR; + regData = index; + retVal = rtl8367d_setAsicReg(regAddr, regData); + if(retVal != RT_ERR_OK) + return retVal; + + /* Write Data Bits to ACS_DATA registers */ + tableAddr = aclActSmi; + regAddr = RTL8367D_REG_TABLE_WRITE_DATA0; + + for(i = 0; i < RTL8367D_ACLACTTBLEN; i++) + { + regData = *tableAddr; + retVal = rtl8367d_setAsicReg(regAddr, regData); + if(retVal != RT_ERR_OK) + return retVal; + + regAddr++; + tableAddr++; + } + + /* Write ACS_CMD register for care bits*/ + regAddr = RTL8367D_REG_TABLE_ACCESS_CTRL; + regData = RTL8367D_TABLE_ACCESS_REG_DATA(RTL8367D_TB_OP_WRITE, RTL8367D_TB_TARGET_ACLACT); + retVal = rtl8367d_setAsicRegBits(regAddr, RTL8367D_TABLE_TYPE_MASK | RTL8367D_COMMAND_TYPE_MASK, regData); + if(retVal != RT_ERR_OK) + return retVal; + +#ifdef CONFIG_RTL8367D_ASICDRV_TEST + memcpy(&Rtl8370sVirtualAclActTable[index][0], aclActSmi, sizeof(rtk_uint16) * RTL8367D_ACL_ACT_TABLE_LEN); +#endif + + return RT_ERR_OK; +} + +static rtk_api_ret_t _rtl8367d_setAclRule(rtk_uint32 index, rtl8367d_aclrule* pAclRule) +{ + rtl8367d_aclrulesmi aclRuleSmi; + rtk_uint16* tableAddr; + rtk_uint32 regAddr; + rtk_uint32 regData; + rtk_uint32 i; + ret_t retVal; + + if(index > RTL8367D_ACLRULEMAX) + return RT_ERR_OUT_OF_RANGE; + + memset(&aclRuleSmi, 0x00, sizeof(rtl8367d_aclrulesmi)); + + _rtl8367d_aclRuleStUser2Smi(pAclRule, &aclRuleSmi); + + /* Write valid bit = 0 */ + regAddr = RTL8367D_REG_TABLE_ACCESS_ADDR; + regData = RTL8367D_ACLRULETBADDR(RTL8367D_DATABITS, index); + retVal = rtl8367d_setAsicReg(regAddr,regData); + if(retVal !=RT_ERR_OK) + return retVal; + + retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_TABLE_WRITE_DATA0+RTL8367D_ACLRULETBLEN, 0x1, 0); + if(retVal !=RT_ERR_OK) + return retVal; + + regAddr = RTL8367D_REG_TABLE_ACCESS_CTRL; + regData = RTL8367D_TABLE_ACCESS_REG_DATA(RTL8367D_TB_OP_WRITE, RTL8367D_TB_TARGET_ACLRULE); + retVal = rtl8367d_setAsicReg(regAddr, regData); + if(retVal !=RT_ERR_OK) + return retVal; + + + + /* Write ACS_ADR register */ + regAddr = RTL8367D_REG_TABLE_ACCESS_ADDR; + regData = RTL8367D_ACLRULETBADDR(RTL8367D_CAREBITS, index); + retVal = rtl8367d_setAsicReg(regAddr, regData); + if(retVal != RT_ERR_OK) + return retVal; + + /* Write Care Bits to ACS_DATA registers */ + tableAddr = (rtk_uint16*)&aclRuleSmi.care_bits; + regAddr = RTL8367D_REG_TABLE_WRITE_DATA0; + + for(i = 0; i < RTL8367D_ACLRULETBLEN; i++) + { + regData = *tableAddr; + retVal = rtl8367d_setAsicReg(regAddr, regData); + if(retVal != RT_ERR_OK) + return retVal; + + regAddr++; + tableAddr++; + } + + /* Write ACS_CMD register */ + regAddr = RTL8367D_REG_TABLE_ACCESS_CTRL; + regData = RTL8367D_TABLE_ACCESS_REG_DATA(RTL8367D_TB_OP_WRITE, RTL8367D_TB_TARGET_ACLRULE); + retVal = rtl8367d_setAsicRegBits(regAddr, RTL8367D_TABLE_TYPE_MASK | RTL8367D_COMMAND_TYPE_MASK,regData); + if(retVal != RT_ERR_OK) + return retVal; + + + + /* Write ACS_ADR register for data bits */ + regAddr = RTL8367D_REG_TABLE_ACCESS_ADDR; + regData = RTL8367D_ACLRULETBADDR(RTL8367D_DATABITS, index); + retVal = rtl8367d_setAsicReg(regAddr, regData); + if(retVal != RT_ERR_OK) + return retVal; + + /* Write Data Bits to ACS_DATA registers */ + tableAddr = (rtk_uint16*)&aclRuleSmi.data_bits; + regAddr = RTL8367D_REG_TABLE_WRITE_DATA0; + + for(i = 0; i < RTL8367D_ACLRULETBLEN; i++) + { + regData = *tableAddr; + retVal = rtl8367d_setAsicReg(regAddr, regData); + if(retVal != RT_ERR_OK) + return retVal; + + regAddr++; + tableAddr++; + } + + retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_TABLE_WRITE_DATA0+RTL8367D_ACLRULETBLEN, 0, aclRuleSmi.valid); + if(retVal != RT_ERR_OK) + return retVal; + + /* Write ACS_CMD register for care bits*/ + regAddr = RTL8367D_REG_TABLE_ACCESS_CTRL; + regData = RTL8367D_TABLE_ACCESS_REG_DATA(RTL8367D_TB_OP_WRITE, RTL8367D_TB_TARGET_ACLRULE); + retVal = rtl8367d_setAsicRegBits(regAddr, RTL8367D_TABLE_TYPE_MASK | RTL8367D_COMMAND_TYPE_MASK, regData); + if(retVal != RT_ERR_OK) + return retVal; + +#ifdef CONFIG_RTL8367D_ASICDRV_TEST + memcpy(&Rtl8370sVirtualAclRuleTable[index], &aclRuleSmi, sizeof(rtl8367d_aclrulesmi)); +#endif + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_filter_igrAcl_cfg_add + * Description: + * Add an ACL configuration to ASIC + * Input: + * filter_id - Start index of ACL configuration. + * pFilter_cfg - The ACL configuration that this function will add comparison rule + * pFilter_action - Action(s) of ACL configuration. + * Output: + * ruleNum - number of rules written in acl table + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Pointer pFilter_field or pFilter_cfg point to NULL. + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_ENTRY_INDEX - Invalid filter_id . + * RT_ERR_NULL_POINTER - Pointer pFilter_action or pFilter_cfg point to NULL. + * RT_ERR_FILTER_INACL_ACT_NOT_SUPPORT - Action is not supported in this chip. + * RT_ERR_FILTER_INACL_RULE_NOT_SUPPORT - Rule is not supported. + * Note: + * This function store pFilter_cfg, pFilter_action into ASIC. The starting + * index(es) is filter_id. + */ +rtk_api_ret_t dal_rtl8367d_filter_igrAcl_cfg_add(rtk_filter_id_t filter_id, rtk_filter_cfg_t* pFilter_cfg, rtk_filter_action_t* pFilter_action, rtk_filter_number_t *ruleNum) +{ + rtk_api_ret_t retVal; + rtk_uint32 careTagData, careTagMask; + rtk_uint32 i,actType, ruleId; + rtk_uint32 aclActCtrl; + rtk_uint32 cpuPort; + rtk_filter_field_t* fieldPtr; + rtl8367d_aclrule aclRule[RTL8367D_ACLTEMPLATENO]; + rtl8367d_aclrule tempRule; + rtl8367d_acl_act_t aclAct; + rtk_uint32 noRulesAdd; + rtk_uint32 portmask; + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(filter_id > RTL8367D_ACLRULEMAX ) + return RT_ERR_ENTRY_INDEX; + + if((NULL == pFilter_cfg) || (NULL == pFilter_action) || (NULL == ruleNum)) + return RT_ERR_NULL_POINTER; + + fieldPtr = pFilter_cfg->fieldHead; + + /* init RULE */ + for(i = 0; i < RTL8367D_ACLTEMPLATENO; i++) + { + memset(&aclRule[i], 0, sizeof(rtl8367d_aclrule)); + + aclRule[i].data_bits.type= i; + aclRule[i].care_bits.type= 0x7; + } + + while(NULL != fieldPtr) + { + _rtk_filter_igrAcl_writeDataField(aclRule, fieldPtr); + + fieldPtr = fieldPtr->next; + } + + /*set care tag mask in User Defined Field 15*/ + /*Follow care tag should not be used while ACL template and User defined fields are fully control by system designer*/ + /*those advanced packet type care tag is used in default template design structure only*/ + careTagData = 0; + careTagMask = 0; + + for(i = CARE_TAG_TCP; i < CARE_TAG_END; i++) + { + if(pFilter_cfg->careTag.tagType[i].mask) + careTagMask = careTagMask | (1 << (i-CARE_TAG_TCP)); + + if(pFilter_cfg->careTag.tagType[i].value) + careTagData = careTagData | (1 << (i-CARE_TAG_TCP)); + } + + if(careTagData || careTagMask) + { + i = 0; + while(i < RTL8367D_ACLTEMPLATENO) + { + if(aclRule[i].valid == 1 && rtl8367D_filter_advanceCaretagField[i][0] == TRUE) + { + + aclRule[i].data_bits.field[rtl8367D_filter_advanceCaretagField[i][1]] = careTagData & 0xFFFF; + aclRule[i].care_bits.field[rtl8367D_filter_advanceCaretagField[i][1]] = careTagMask & 0xFFFF; + break; + } + i++; + } + /*none of previous used template containing field 15*/ + if(i == RTL8367D_ACLTEMPLATENO) + { + i = 0; + while(i < RTL8367D_ACLTEMPLATENO) + { + if(rtl8367D_filter_advanceCaretagField[i][0] == TRUE) + { + aclRule[i].data_bits.field[rtl8367D_filter_advanceCaretagField[i][1]] = careTagData & 0xFFFF; + aclRule[i].care_bits.field[rtl8367D_filter_advanceCaretagField[i][1]] = careTagMask & 0xFFFF; + aclRule[i].valid = 1; + break; + } + i++; + } + } + } + + /*Check rule number*/ + noRulesAdd = 0; + for(i = 0; i < RTL8367D_ACLTEMPLATENO; i++) + { + if(1 == aclRule[i].valid) + { + noRulesAdd ++; + } + } + + *ruleNum = noRulesAdd; + + if((filter_id + noRulesAdd - 1) > RTL8367D_ACLRULEMAX) + { + return RT_ERR_ENTRY_INDEX; + } + + /*set care tag mask in TAG Indicator*/ + careTagData = 0; + careTagMask = 0; + + for(i = 0; i <= CARE_TAG_IPV6;i++) + { + if(0 == pFilter_cfg->careTag.tagType[i].mask ) + { + careTagMask &= ~(1 << i); + } + else + { + careTagMask |= (1 << i); + if(0 == pFilter_cfg->careTag.tagType[i].value ) + careTagData &= ~(1 << i); + else + careTagData |= (1 << i); + } + } + + for(i = 0; i < RTL8367D_ACLTEMPLATENO; i++) + { + aclRule[i].data_bits.tag_exist = (careTagData) & ACL_RULE_CARETAG_MASK; + aclRule[i].care_bits.tag_exist = (careTagMask) & ACL_RULE_CARETAG_MASK; + } + + RTK_CHK_PORTMASK_VALID(&pFilter_cfg->activeport.value); + RTK_CHK_PORTMASK_VALID(&pFilter_cfg->activeport.mask); + + for(i = 0; i < RTL8367D_ACLTEMPLATENO; i++) + { + if(TRUE == aclRule[i].valid) + { + if(rtk_switch_portmask_L2P_get(&pFilter_cfg->activeport.value, &portmask) != RT_ERR_OK) + return RT_ERR_PORT_MASK; + + aclRule[i].data_bits.active_portmsk = portmask; + + if(rtk_switch_portmask_L2P_get(&pFilter_cfg->activeport.mask, &portmask) != RT_ERR_OK) + return RT_ERR_PORT_MASK; + + aclRule[i].care_bits.active_portmsk = portmask; + } + } + + if(pFilter_cfg->invert >= FILTER_INVERT_END ) + return RT_ERR_INPUT; + + + /*Last action gets high priority if actions are the same*/ + memset(&aclAct, 0, sizeof(rtl8367d_acl_act_t)); + aclActCtrl = 0; + for(actType = 0; actType < FILTER_ENACT_END; actType ++) + { + if(pFilter_action->actEnable[actType]) + { + switch (actType) + { + case FILTER_ENACT_CVLAN_INGRESS: + if(pFilter_action->filterCvlanVid > RTL8367D_VIDMAX) + return RT_ERR_INPUT; + aclAct.cact = FILTER_ENACT_CVLAN_TYPE(actType); + aclAct.cvidx_cact = pFilter_action->filterCvlanVid; + + if(aclActCtrl &(FILTER_ENACT_CVLAN_MASK)) + { + if(aclAct.cact_ext == FILTER_ENACT_CACTEXT_TAGONLY) + aclAct.cact_ext = FILTER_ENACT_CACTEXT_BOTHVLANTAG; + } + else + { + aclAct.cact_ext = FILTER_ENACT_CACTEXT_VLANONLY; + } + + aclActCtrl |= FILTER_ENACT_CVLAN_MASK; + break; + case FILTER_ENACT_CVLAN_EGRESS: + if(pFilter_action->filterCvlanVid > RTL8367D_VIDMAX) + return RT_ERR_INPUT; + + aclAct.cact = FILTER_ENACT_CVLAN_TYPE(actType); + aclAct.cvidx_cact = pFilter_action->filterCvlanVid; + + if(aclActCtrl &(FILTER_ENACT_CVLAN_MASK)) + { + if(aclAct.cact_ext == FILTER_ENACT_CACTEXT_TAGONLY) + aclAct.cact_ext = FILTER_ENACT_CACTEXT_BOTHVLANTAG; + } + else + { + aclAct.cact_ext = FILTER_ENACT_CACTEXT_VLANONLY; + } + + aclActCtrl |= FILTER_ENACT_CVLAN_MASK; + break; + case FILTER_ENACT_CVLAN_SVID: + + aclAct.cact = FILTER_ENACT_CVLAN_TYPE(actType); + + if(aclActCtrl &(FILTER_ENACT_CVLAN_MASK)) + { + if(aclAct.cact_ext == FILTER_ENACT_CACTEXT_TAGONLY) + aclAct.cact_ext = FILTER_ENACT_CACTEXT_BOTHVLANTAG; + } + else + { + aclAct.cact_ext = FILTER_ENACT_CACTEXT_VLANONLY; + } + + aclActCtrl |= FILTER_ENACT_CVLAN_MASK; + break; + case FILTER_ENACT_POLICING_1: + if(pFilter_action->filterPolicingIdx[1] >= ((RTK_MAX_METER_ID + 1) + RTL8367D_MAX_LOG_CNT_NUM)) + return RT_ERR_INPUT; + + aclAct.cact = FILTER_ENACT_CVLAN_TYPE(actType); + aclAct.cvidx_cact = pFilter_action->filterPolicingIdx[1]; + + if(aclActCtrl &(FILTER_ENACT_CVLAN_MASK)) + { + if(aclAct.cact_ext == FILTER_ENACT_CACTEXT_TAGONLY) + aclAct.cact_ext = FILTER_ENACT_CACTEXT_BOTHVLANTAG; + } + else + { + aclAct.cact_ext = FILTER_ENACT_CACTEXT_VLANONLY; + } + + aclActCtrl |= FILTER_ENACT_CVLAN_MASK; + break; + + case FILTER_ENACT_SVLAN_INGRESS: + case FILTER_ENACT_SVLAN_EGRESS: + aclAct.sact = FILTER_ENACT_SVLAN_TYPE(actType); + aclAct.svidx_sact = pFilter_action->filterSvlanVid; + aclActCtrl |= FILTER_ENACT_SVLAN_MASK; + break; + case FILTER_ENACT_SVLAN_CVID: + + aclAct.sact = FILTER_ENACT_SVLAN_TYPE(actType); + aclActCtrl |= FILTER_ENACT_SVLAN_MASK; + break; + case FILTER_ENACT_POLICING_2: + if(pFilter_action->filterPolicingIdx[2] >= ((RTK_MAX_METER_ID + 1) + RTL8367D_MAX_LOG_CNT_NUM)) + return RT_ERR_INPUT; + + aclAct.sact = FILTER_ENACT_SVLAN_TYPE(actType); + aclAct.svidx_sact = pFilter_action->filterPolicingIdx[2]; + aclActCtrl |= FILTER_ENACT_SVLAN_MASK; + break; + case FILTER_ENACT_POLICING_0: + if(pFilter_action->filterPolicingIdx[0] >= ((RTK_MAX_METER_ID + 1) + RTL8367D_MAX_LOG_CNT_NUM)) + return RT_ERR_INPUT; + + aclAct.aclmeteridx = pFilter_action->filterPolicingIdx[0]; + aclActCtrl |= FILTER_ENACT_POLICING_MASK; + break; + case FILTER_ENACT_PRIORITY: + case FILTER_ENACT_1P_REMARK: + if(pFilter_action->filterPriority > RTL8367D_PRIMAX) + return RT_ERR_INPUT; + + aclAct.priact = FILTER_ENACT_PRI_TYPE(actType); + aclAct.pridx = pFilter_action->filterPriority; + aclActCtrl |= FILTER_ENACT_PRIORITY_MASK; + break; + case FILTER_ENACT_DSCP_REMARK: + if(pFilter_action->filterPriority > RTL8367D_DSCPMAX) + return RT_ERR_INPUT; + + aclAct.priact = FILTER_ENACT_PRI_TYPE(actType); + aclAct.pridx = pFilter_action->filterPriority; + aclActCtrl |= FILTER_ENACT_PRIORITY_MASK; + break; + case FILTER_ENACT_POLICING_3: + if(pFilter_action->filterPriority >= ((RTK_MAX_METER_ID + 1) + RTL8367D_MAX_LOG_CNT_NUM)) + return RT_ERR_INPUT; + + aclAct.priact = FILTER_ENACT_PRI_TYPE(actType); + aclAct.pridx = pFilter_action->filterPolicingIdx[3]; + aclActCtrl |= FILTER_ENACT_PRIORITY_MASK; + break; + case FILTER_ENACT_DROP: + + aclAct.fwdact = FILTER_ENACT_FWD_TYPE(FILTER_ENACT_REDIRECT); + aclAct.fwdact_ext = FALSE; + + aclAct.fwdpmask = 0; + aclActCtrl |= FILTER_ENACT_FWD_MASK; + break; + case FILTER_ENACT_REDIRECT: + RTK_CHK_PORTMASK_VALID(&pFilter_action->filterPortmask); + + aclAct.fwdact = FILTER_ENACT_FWD_TYPE(actType); + aclAct.fwdact_ext = FALSE; + + if(rtk_switch_portmask_L2P_get(&pFilter_action->filterPortmask, &portmask) != RT_ERR_OK) + return RT_ERR_PORT_MASK; + aclAct.fwdpmask = portmask; + + aclActCtrl |= FILTER_ENACT_FWD_MASK; + break; + + case FILTER_ENACT_ADD_DSTPORT: + RTK_CHK_PORTMASK_VALID(&pFilter_action->filterPortmask); + + aclAct.fwdact = FILTER_ENACT_FWD_TYPE(actType); + aclAct.fwdact_ext = FALSE; + + if(rtk_switch_portmask_L2P_get(&pFilter_action->filterPortmask, &portmask) != RT_ERR_OK) + return RT_ERR_PORT_MASK; + aclAct.fwdpmask = portmask; + + aclActCtrl |= FILTER_ENACT_FWD_MASK; + break; + case FILTER_ENACT_MIRROR: + RTK_CHK_PORTMASK_VALID(&pFilter_action->filterPortmask); + + aclAct.fwdact = FILTER_ENACT_FWD_TYPE(actType); + aclAct.cact_ext = FALSE; + + if(rtk_switch_portmask_L2P_get(&pFilter_action->filterPortmask, &portmask) != RT_ERR_OK) + return RT_ERR_PORT_MASK; + aclAct.fwdpmask = portmask; + + aclActCtrl |= FILTER_ENACT_FWD_MASK; + break; + case FILTER_ENACT_TRAP_CPU: + + aclAct.fwdact = FILTER_ENACT_FWD_TYPE(actType); + aclAct.fwdact_ext = FALSE; + + aclActCtrl |= FILTER_ENACT_FWD_MASK; + break; + case FILTER_ENACT_COPY_CPU: + if((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_CPU_CTRL, RTL8367D_CPU_TRAP_PORT_MASK, &cpuPort)) != RT_ERR_OK) + return retVal; + + aclAct.fwdact = FILTER_ENACT_FWD_TYPE(FILTER_ENACT_MIRROR); + aclAct.fwdact_ext = FALSE; + + aclAct.fwdpmask = 1 << cpuPort; + aclActCtrl |= FILTER_ENACT_FWD_MASK; + break; + case FILTER_ENACT_ISOLATION: + RTK_CHK_PORTMASK_VALID(&pFilter_action->filterPortmask); + + aclAct.fwdact_ext = TRUE; + + if(rtk_switch_portmask_L2P_get(&pFilter_action->filterPortmask, &portmask) != RT_ERR_OK) + return RT_ERR_PORT_MASK; + aclAct.fwdpmask = portmask; + + aclActCtrl |= FILTER_ENACT_FWD_MASK; + break; + + case FILTER_ENACT_INTERRUPT: + + aclAct.aclint = TRUE; + aclActCtrl |= FILTER_ENACT_INTGPIO_MASK; + break; + case FILTER_ENACT_GPO: + if((pFilter_action->filterPin > RTL8367D_ACLGPIOPINNO) || ((pFilter_action->filterPin == 0))) + return RT_ERR_INPUT; + aclAct.gpio_en = TRUE; + aclAct.gpio_pin = pFilter_action->filterPin; + aclActCtrl |= FILTER_ENACT_INTGPIO_MASK; + break; + case FILTER_ENACT_EGRESSCTAG_TAG: + + if(aclActCtrl &(FILTER_ENACT_CVLAN_MASK)) + { + if(aclAct.cact_ext == FILTER_ENACT_CACTEXT_VLANONLY) + aclAct.cact_ext = FILTER_ENACT_CACTEXT_BOTHVLANTAG; + } + else + { + aclAct.cact_ext = FILTER_ENACT_CACTEXT_TAGONLY; + } + aclAct.tag_fmt = FILTER_CTAGFMT_TAG; + aclActCtrl |= FILTER_ENACT_CVLAN_MASK; + break; + case FILTER_ENACT_EGRESSCTAG_UNTAG: + + if(aclActCtrl &(FILTER_ENACT_CVLAN_MASK)) + { + if(aclAct.cact_ext == FILTER_ENACT_CACTEXT_VLANONLY) + aclAct.cact_ext = FILTER_ENACT_CACTEXT_BOTHVLANTAG; + } + else + { + aclAct.cact_ext = FILTER_ENACT_CACTEXT_TAGONLY; + } + aclAct.tag_fmt = FILTER_CTAGFMT_UNTAG; + aclActCtrl |= FILTER_ENACT_CVLAN_MASK; + break; + case FILTER_ENACT_EGRESSCTAG_KEEP: + + if(aclActCtrl &(FILTER_ENACT_CVLAN_MASK)) + { + if(aclAct.cact_ext == FILTER_ENACT_CACTEXT_VLANONLY) + aclAct.cact_ext = FILTER_ENACT_CACTEXT_BOTHVLANTAG; + } + else + { + aclAct.cact_ext = FILTER_ENACT_CACTEXT_TAGONLY; + } + aclAct.tag_fmt = FILTER_CTAGFMT_KEEP; + aclActCtrl |= FILTER_ENACT_CVLAN_MASK; + break; + case FILTER_ENACT_EGRESSCTAG_KEEPAND1PRMK: + + if(aclActCtrl &(FILTER_ENACT_CVLAN_MASK)) + { + if(aclAct.cact_ext == FILTER_ENACT_CACTEXT_VLANONLY) + aclAct.cact_ext = FILTER_ENACT_CACTEXT_BOTHVLANTAG; + } + else + { + aclAct.cact_ext = FILTER_ENACT_CACTEXT_TAGONLY; + } + aclAct.tag_fmt = FILTER_CTAGFMT_KEEP1PRMK; + aclActCtrl |= FILTER_ENACT_CVLAN_MASK; + break; + default: + return RT_ERR_FILTER_INACL_ACT_NOT_SUPPORT; + } + } + } + + + /*check if free ACL rules are enough*/ + for(i = filter_id; i < (filter_id + noRulesAdd); i++) + { + if((retVal = _rtl8367d_getAclRule(i, &tempRule)) != RT_ERR_OK ) + return retVal; + + if(tempRule.valid == TRUE) + { + return RT_ERR_TBL_FULL; + } + } + + ruleId = 0; + for(i = 0; i < RTL8367D_ACLTEMPLATENO; i++) + { + if(aclRule[i].valid == TRUE) + { + /* write ACL action control */ + if((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_ACL_ACTION_CTRL0 + ((filter_id + ruleId) >> 1), (0x3F << (((filter_id + ruleId) & 0x1) << 3)), aclActCtrl)) != RT_ERR_OK ) + return retVal; + /* write ACL action */ + if((retVal = _rtl8367d_setAclAct(filter_id + ruleId, &aclAct)) != RT_ERR_OK ) + return retVal; + + /* write ACL not */ + if((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_ACL_ACTION_CTRL0 + ((filter_id + ruleId) >> 1), (6 + (((filter_id + ruleId) & 0x1) << 3)), pFilter_cfg->invert)) != RT_ERR_OK ) + return retVal; + /* write ACL rule */ + if((retVal = _rtl8367d_setAclRule(filter_id + ruleId, &aclRule[i])) != RT_ERR_OK ) + return retVal; + + /* only the first rule will be written with input action control, aclActCtrl of other rules will be zero */ + aclActCtrl = 0; + memset(&aclAct, 0, sizeof(rtl8367d_acl_act_t)); + + ruleId ++; + } + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_filter_igrAcl_cfg_del + * Description: + * Delete an ACL configuration from ASIC + * Input: + * filter_id - Start index of ACL configuration. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_ENTRYIDX - Invalid filter_id. + * Note: + * This function delete a group of ACL rules starting from filter_id. + */ +rtk_api_ret_t dal_rtl8367d_filter_igrAcl_cfg_del(rtk_filter_id_t filter_id) +{ + rtl8367d_aclrule initRule; + rtl8367d_acl_act_t initAct; + rtk_api_ret_t ret; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(filter_id > RTL8367D_ACLRULEMAX ) + return RT_ERR_FILTER_ENTRYIDX; + + memset(&initRule, 0, sizeof(rtl8367d_aclrule)); + memset(&initAct, 0, sizeof(rtl8367d_acl_act_t)); + + if((ret = _rtl8367d_setAclRule(filter_id, &initRule)) != RT_ERR_OK) + return ret; + + + if((ret = rtl8367d_setAsicRegBits(RTL8367D_REG_ACL_ACTION_CTRL0 + (filter_id >> 1), (0x3F << ((filter_id & 0x1) << 3)), FILTER_ENACT_INIT_MASK))!= RT_ERR_OK) + return ret; + if((ret = _rtl8367d_setAclAct(filter_id, &initAct)) != RT_ERR_OK) + return ret; + if((ret = rtl8367d_setAsicRegBit(RTL8367D_REG_ACL_ACTION_CTRL0 + (filter_id >> 1), (6 + ((filter_id & 0x1) << 3)), DISABLED)) != RT_ERR_OK ) + return ret; + + return RT_ERR_OK; +} + +static rtk_api_ret_t _rtl8367d_getAclAct(rtk_uint32 index, rtl8367d_acl_act_t *pAclAct) +{ + rtk_uint16 aclActSmi[RTL8367D_ACL_ACT_TABLE_LEN]; + ret_t retVal; + rtk_uint32 regAddr, regData; + rtk_uint16 *tableAddr; + rtk_uint32 i; + + if(index > RTL8367D_ACLRULEMAX) + return RT_ERR_OUT_OF_RANGE; + + memset(aclActSmi, 0x00, sizeof(rtk_uint16) * RTL8367D_ACL_ACT_TABLE_LEN); + + /* Write ACS_ADR register for data bits */ + regAddr = RTL8367D_REG_TABLE_ACCESS_ADDR; + regData = index; + retVal = rtl8367d_setAsicReg(regAddr, regData); + if(retVal != RT_ERR_OK) + return retVal; + + /* Write ACS_CMD register */ + regAddr = RTL8367D_REG_TABLE_ACCESS_CTRL; + regData = RTL8367D_TABLE_ACCESS_REG_DATA(RTL8367D_TB_OP_READ, RTL8367D_TB_TARGET_ACLACT); + retVal = rtl8367d_setAsicRegBits(regAddr, RTL8367D_TABLE_TYPE_MASK | RTL8367D_COMMAND_TYPE_MASK, regData); + if(retVal != RT_ERR_OK) + return retVal; + + /* Read Data Bits */ + regAddr = RTL8367D_REG_TABLE_READ_DATA0; + tableAddr = aclActSmi; + for(i = 0; i < RTL8367D_ACLACTTBLEN; i++) + { + retVal = rtl8367d_getAsicReg(regAddr, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + *tableAddr = regData; + + regAddr ++; + tableAddr ++; + } + +#ifdef CONFIG_RTL8367D_ASICDRV_TEST + memcpy(aclActSmi, &Rtl8370sVirtualAclActTable[index][0], sizeof(rtk_uint16) * RTL8367D_ACL_ACT_TABLE_LEN); +#endif + + _rtl8367d_aclActStSmi2User(pAclAct, aclActSmi); + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_filter_igrAcl_cfg_get + * Description: + * Get one ingress acl configuration from ASIC. + * Input: + * filter_id - Start index of ACL configuration. + * Output: + * pFilter_cfg - buffer pointer of ingress acl data + * pFilter_action - buffer pointer of ingress acl action + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Pointer pFilter_action or pFilter_cfg point to NULL. + * RT_ERR_FILTER_ENTRYIDX - Invalid entry index. + * Note: + * This function get configuration from ASIC. + */ +rtk_api_ret_t dal_rtl8367d_filter_igrAcl_cfg_get(rtk_filter_id_t filter_id, rtk_filter_cfg_raw_t *pFilter_cfg, rtk_filter_action_t *pAction) +{ + rtk_api_ret_t retVal; + rtk_uint32 i, tmp; + rtl8367d_aclrule aclRule; + rtl8367d_acl_act_t aclAct; + rtk_uint32 cpuPort; + rtl8367d_acltemplate_t type; + rtk_uint32 phyPmask; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pFilter_cfg || NULL == pAction) + return RT_ERR_NULL_POINTER; + + if(filter_id > RTL8367D_ACLRULEMAX) + return RT_ERR_ENTRY_INDEX; + + if ((retVal = _rtl8367d_getAclRule(filter_id, &aclRule)) != RT_ERR_OK) + return retVal; + + /* Check valid */ + if(aclRule.valid == 0) + { + pFilter_cfg->valid = DISABLED; + return RT_ERR_OK; + } + + phyPmask = aclRule.data_bits.active_portmsk; + if(rtk_switch_portmask_P2L_get(phyPmask,&(pFilter_cfg->activeport.value)) != RT_ERR_OK) + return RT_ERR_FAILED; + + phyPmask = aclRule.care_bits.active_portmsk; + if(rtk_switch_portmask_P2L_get(phyPmask,&(pFilter_cfg->activeport.mask)) != RT_ERR_OK) + return RT_ERR_FAILED; + + for(i = 0; i <= CARE_TAG_IPV6; i++) + { + if(aclRule.data_bits.tag_exist & (1 << i)) + pFilter_cfg->careTag.tagType[i].value = 1; + else + pFilter_cfg->careTag.tagType[i].value = 0; + + if (aclRule.care_bits.tag_exist & (1 << i)) + pFilter_cfg->careTag.tagType[i].mask = 1; + else + pFilter_cfg->careTag.tagType[i].mask = 0; + } + + if(rtl8367D_filter_advanceCaretagField[aclRule.data_bits.type][0] == TRUE) + { + /* Advanced Care tag setting */ + for(i = CARE_TAG_TCP; i < CARE_TAG_END; i++) + { + if(aclRule.data_bits.field[rtl8367D_filter_advanceCaretagField[aclRule.data_bits.type][1]] & (0x0001 << (i-CARE_TAG_TCP)) ) + pFilter_cfg->careTag.tagType[i].value = 1; + else + pFilter_cfg->careTag.tagType[i].value = 0; + + if(aclRule.care_bits.field[rtl8367D_filter_advanceCaretagField[aclRule.care_bits.type][1]] & (0x0001 << (i-CARE_TAG_TCP)) ) + pFilter_cfg->careTag.tagType[i].mask = 1; + else + pFilter_cfg->careTag.tagType[i].mask = 0; + } + } + + for(i = 0; i < RTL8367D_ACLRULEFIELDNO; i++) + { + pFilter_cfg->careFieldRaw[i] = aclRule.care_bits.field[i]; + pFilter_cfg->dataFieldRaw[i] = aclRule.data_bits.field[i]; + } + + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_ACL_ACTION_CTRL0 + (filter_id >> 1), (6 + ((filter_id & 0x1) << 3)), &tmp))!= RT_ERR_OK) + return retVal; + + pFilter_cfg->invert = tmp; + + pFilter_cfg->valid = aclRule.valid; + + memset(pAction, 0, sizeof(rtk_filter_action_t)); + memset(&aclAct, 0, sizeof(rtl8367d_acl_act_t)); + + if ((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_ACL_ACTION_CTRL0 + (filter_id >> 1), (0x3F << ((filter_id & 0x1) << 3)), &tmp))!= RT_ERR_OK) + return retVal; + + if ((retVal = _rtl8367d_getAclAct(filter_id, &aclAct)) != RT_ERR_OK) + return retVal; + + if(tmp & FILTER_ENACT_FWD_MASK) + { + if(TRUE == aclAct.fwdact_ext) + { + pAction->actEnable[FILTER_ENACT_ISOLATION] = TRUE; + + phyPmask = aclAct.fwdpmask; + if(rtk_switch_portmask_P2L_get(phyPmask,&(pAction->filterPortmask)) != RT_ERR_OK) + return RT_ERR_FAILED; + } + else if(aclAct.fwdact == RTL8367D_ACL_FWD_TRAP) + { + pAction->actEnable[FILTER_ENACT_TRAP_CPU] = TRUE; + } + else if (aclAct.fwdact == RTL8367D_ACL_FWD_MIRRORFUNTION ) + { + pAction->actEnable[FILTER_ENACT_MIRROR] = TRUE; + + phyPmask = aclAct.fwdpmask; + if(rtk_switch_portmask_P2L_get(phyPmask,&(pAction->filterPortmask)) != RT_ERR_OK) + return RT_ERR_FAILED; + } + else if (aclAct.fwdact == RTL8367D_ACL_FWD_REDIRECT) + { + if(aclAct.fwdpmask == 0 ) + pAction->actEnable[FILTER_ENACT_DROP] = TRUE; + else + { + pAction->actEnable[FILTER_ENACT_REDIRECT] = TRUE; + + phyPmask = aclAct.fwdpmask; + if(rtk_switch_portmask_P2L_get(phyPmask,&(pAction->filterPortmask)) != RT_ERR_OK) + return RT_ERR_FAILED; + } + } + else if (aclAct.fwdact == RTL8367D_ACL_FWD_MIRROR) + { + if((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_CPU_CTRL, RTL8367D_CPU_TRAP_PORT_MASK, &cpuPort)) != RT_ERR_OK) + return retVal; + if (aclAct.fwdpmask == (1UL << cpuPort)) + { + pAction->actEnable[FILTER_ENACT_COPY_CPU] = TRUE; + } + else + { + pAction->actEnable[FILTER_ENACT_ADD_DSTPORT] = TRUE; + + phyPmask = aclAct.fwdpmask; + if(rtk_switch_portmask_P2L_get(phyPmask,&(pAction->filterPortmask)) != RT_ERR_OK) + return RT_ERR_FAILED; + } + } + else + { + return RT_ERR_FAILED; + } + } + + if(tmp & FILTER_ENACT_POLICING_MASK) + { + pAction->actEnable[FILTER_ENACT_POLICING_0] = TRUE; + pAction->filterPolicingIdx[0] = aclAct.aclmeteridx; + } + + if(tmp & FILTER_ENACT_PRIORITY_MASK) + { + if(aclAct.priact == FILTER_ENACT_PRI_TYPE(FILTER_ENACT_PRIORITY)) + { + pAction->actEnable[FILTER_ENACT_PRIORITY] = TRUE; + pAction->filterPriority = aclAct.pridx; + } + else if(aclAct.priact == FILTER_ENACT_PRI_TYPE(FILTER_ENACT_1P_REMARK)) + { + pAction->actEnable[FILTER_ENACT_1P_REMARK] = TRUE; + pAction->filterPriority = aclAct.pridx; + } + else if(aclAct.priact == FILTER_ENACT_PRI_TYPE(FILTER_ENACT_DSCP_REMARK)) + { + pAction->actEnable[FILTER_ENACT_DSCP_REMARK] = TRUE; + pAction->filterPriority = aclAct.pridx; + } + else if(aclAct.priact == FILTER_ENACT_PRI_TYPE(FILTER_ENACT_POLICING_3)) + { + pAction->actEnable[FILTER_ENACT_POLICING_3] = TRUE; + pAction->filterPolicingIdx[3] = aclAct.pridx; + } + } + + if(tmp & FILTER_ENACT_SVLAN_MASK) + { + if(aclAct.sact == FILTER_ENACT_SVLAN_TYPE(FILTER_ENACT_SVLAN_INGRESS)) + { + pAction->actEnable[FILTER_ENACT_SVLAN_INGRESS] = TRUE; + pAction->filterSvlanIdx = aclAct.svidx_sact; + pAction->filterSvlanVid = aclAct.svidx_sact; + } + else if(aclAct.sact == FILTER_ENACT_SVLAN_TYPE(FILTER_ENACT_SVLAN_EGRESS)) + { + pAction->actEnable[FILTER_ENACT_SVLAN_EGRESS] = TRUE; + pAction->filterSvlanIdx = aclAct.svidx_sact; + pAction->filterSvlanVid = aclAct.svidx_sact; + } + else if(aclAct.sact == FILTER_ENACT_SVLAN_TYPE(FILTER_ENACT_SVLAN_CVID)) + pAction->actEnable[FILTER_ENACT_SVLAN_CVID] = TRUE; + else if(aclAct.sact == FILTER_ENACT_SVLAN_TYPE(FILTER_ENACT_POLICING_2)) + { + pAction->actEnable[FILTER_ENACT_POLICING_2] = TRUE; + pAction->filterPolicingIdx[2] = aclAct.svidx_sact; + } + } + + + if(tmp & FILTER_ENACT_CVLAN_MASK) + { + if(FILTER_ENACT_CACTEXT_TAGONLY == aclAct.cact_ext || + FILTER_ENACT_CACTEXT_BOTHVLANTAG == aclAct.cact_ext ) + { + if(FILTER_CTAGFMT_UNTAG == aclAct.tag_fmt) + { + pAction->actEnable[FILTER_ENACT_EGRESSCTAG_UNTAG] = TRUE; + } + else if(FILTER_CTAGFMT_TAG == aclAct.tag_fmt) + { + pAction->actEnable[FILTER_ENACT_EGRESSCTAG_TAG] = TRUE; + } + else if(FILTER_CTAGFMT_KEEP == aclAct.tag_fmt) + { + pAction->actEnable[FILTER_ENACT_EGRESSCTAG_KEEP] = TRUE; + } + else if(FILTER_CTAGFMT_KEEP1PRMK== aclAct.tag_fmt) + { + pAction->actEnable[FILTER_ENACT_EGRESSCTAG_KEEPAND1PRMK] = TRUE; + } + + } + + if(FILTER_ENACT_CACTEXT_VLANONLY == aclAct.cact_ext || + FILTER_ENACT_CACTEXT_BOTHVLANTAG == aclAct.cact_ext ) + { + if(aclAct.cact == FILTER_ENACT_CVLAN_TYPE(FILTER_ENACT_CVLAN_INGRESS)) + { + pAction->actEnable[FILTER_ENACT_CVLAN_INGRESS] = TRUE; + pAction->filterCvlanIdx = aclAct.cvidx_cact; + pAction->filterCvlanVid = aclAct.cvidx_cact; + } + else if(aclAct.cact == FILTER_ENACT_CVLAN_TYPE(FILTER_ENACT_CVLAN_EGRESS)) + { + pAction->actEnable[FILTER_ENACT_CVLAN_EGRESS] = TRUE; + pAction->filterCvlanIdx = aclAct.cvidx_cact; + pAction->filterCvlanVid = aclAct.cvidx_cact; + } + else if(aclAct.cact == FILTER_ENACT_CVLAN_TYPE(FILTER_ENACT_CVLAN_SVID)) + { + pAction->actEnable[FILTER_ENACT_CVLAN_SVID] = TRUE; + } + else if(aclAct.cact == FILTER_ENACT_CVLAN_TYPE(FILTER_ENACT_POLICING_1)) + { + pAction->actEnable[FILTER_ENACT_POLICING_1] = TRUE; + pAction->filterPolicingIdx[1] = aclAct.cvidx_cact; + } + } + } + + if(tmp & FILTER_ENACT_INTGPIO_MASK) + { + if(TRUE == aclAct.aclint) + { + pAction->actEnable[FILTER_ENACT_INTERRUPT] = TRUE; + } + + if(TRUE == aclAct.gpio_en) + { + pAction->actEnable[FILTER_ENACT_GPO] = TRUE; + pAction->filterPin = aclAct.gpio_pin; + } + } + + /* Get field type of RAW data */ + if ((retVal = _rtl8367d_getAsicAclTemplate(aclRule.data_bits.type, &type))!= RT_ERR_OK) + return retVal; + + for(i = 0; i < RTL8367D_ACLRULEFIELDNO; i++) + { + pFilter_cfg->fieldRawType[i] = type.field[i]; + }/* end of for(i...) */ + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_filter_igrAcl_unmatchAction_set + * Description: + * Set action to packets when no ACL configuration match + * Input: + * port - Port id. + * action - Action. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port id. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This function sets action of packets when no ACL configruation matches. + */ +rtk_api_ret_t dal_rtl8367d_filter_igrAcl_unmatchAction_set(rtk_port_t port, rtk_filter_unmatch_action_t action) +{ + rtk_api_ret_t ret; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check port valid */ + RTK_CHK_PORT_VALID(port); + + if(action >= FILTER_UNMATCH_END) + return RT_ERR_INPUT; + + if((ret = rtl8367d_setAsicRegBit(RTL8367D_REG_ACL_UNMATCH_PERMIT, rtk_switch_port_L2P_get(port), action)) != RT_ERR_OK) + return ret; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_filter_igrAcl_unmatchAction_get + * Description: + * Get action to packets when no ACL configuration match + * Input: + * port - Port id. + * Output: + * pAction - Action. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port id. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This function gets action of packets when no ACL configruation matches. + */ +rtk_api_ret_t dal_rtl8367d_filter_igrAcl_unmatchAction_get(rtk_port_t port, rtk_filter_unmatch_action_t* pAction) +{ + rtk_api_ret_t ret; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pAction) + return RT_ERR_NULL_POINTER; + + /* Check port valid */ + RTK_CHK_PORT_VALID(port); + + if((ret = rtl8367d_getAsicRegBit(RTL8367D_REG_ACL_UNMATCH_PERMIT, rtk_switch_port_L2P_get(port), pAction)) != RT_ERR_OK) + return ret; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_filter_igrAcl_state_set + * Description: + * Set state of ingress ACL. + * Input: + * port - Port id. + * state - Ingress ACL state. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port id. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This function gets action of packets when no ACL configruation matches. + */ +rtk_api_ret_t dal_rtl8367d_filter_igrAcl_state_set(rtk_port_t port, rtk_filter_state_t state) +{ + rtk_api_ret_t ret; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check port valid */ + RTK_CHK_PORT_VALID(port); + + if(state >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if((ret = rtl8367d_setAsicRegBit(RTL8367D_REG_ACL_ENABLE, rtk_switch_port_L2P_get(port), state)) != RT_ERR_OK) + return ret; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_filter_igrAcl_state_get + * Description: + * Get state of ingress ACL. + * Input: + * port - Port id. + * Output: + * pState - Ingress ACL state. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port id. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This function gets action of packets when no ACL configruation matches. + */ +rtk_api_ret_t dal_rtl8367d_filter_igrAcl_state_get(rtk_port_t port, rtk_filter_state_t* pState) +{ + rtk_api_ret_t ret; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pState) + return RT_ERR_NULL_POINTER; + + /* Check port valid */ + RTK_CHK_PORT_VALID(port); + + if((ret = rtl8367d_getAsicRegBit(RTL8367D_REG_ACL_ENABLE, rtk_switch_port_L2P_get(port), pState)) != RT_ERR_OK) + return ret; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_filter_igrAcl_template_set + * Description: + * Set template of ingress ACL. + * Input: + * template - Ingress ACL template + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This function set ACL template. + */ +rtk_api_ret_t dal_rtl8367d_filter_igrAcl_template_set(rtk_filter_template_t *aclTemplate) +{ + rtk_api_ret_t retVal; + rtk_uint32 idxField; + rtl8367d_acltemplate_t aclType; + rtk_uint32 i; + rtk_uint32 regAddr, regData; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(aclTemplate->index >= RTK_MAX_NUM_OF_FILTER_TYPE) + return RT_ERR_INPUT; + + for(idxField = 0; idxField < RTK_MAX_NUM_OF_FILTER_FIELD; idxField++) + { + if(aclTemplate->fieldType[idxField] < FILTER_FIELD_RAW_DMAC_15_0 || + (aclTemplate->fieldType[idxField] > FILTER_FIELD_RAW_CTAG && aclTemplate->fieldType[idxField] < FILTER_FIELD_RAW_IPV4_SIP_15_0 ) || + (aclTemplate->fieldType[idxField] > FILTER_FIELD_RAW_IPV4_DIP_31_16 && aclTemplate->fieldType[idxField] < FILTER_FIELD_RAW_IPV6_SIP_15_0 ) || + (aclTemplate->fieldType[idxField] > FILTER_FIELD_RAW_FIELD_VALID && aclTemplate->fieldType[idxField] < FILTER_FIELD_RAW_FIELD_SELECT00 ) || + aclTemplate->fieldType[idxField] >= FILTER_FIELD_RAW_END) + { + return RT_ERR_INPUT; + } + } + + for(idxField = 0; idxField < RTK_MAX_NUM_OF_FILTER_FIELD; idxField++) + { + aclType.field[idxField] = aclTemplate->fieldType[idxField]; + } + + regAddr = (RTL8367D_REG_ACL_RULE_TEMPLATE0_CTRL0 + aclTemplate->index * 0x4); + + for(i = 0; i < (RTL8367D_ACLRULEFIELDNO/2); i++) + { + regData = aclType.field[i*2+1]; + regData = regData << 8 | aclType.field[i*2]; + + if((retVal = rtl8367d_setAsicReg(regAddr + i, regData)) != RT_ERR_OK) + return retVal; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_filter_igrAcl_template_get + * Description: + * Get template of ingress ACL. + * Input: + * template - Ingress ACL template + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This function gets template of ACL. + */ +rtk_api_ret_t dal_rtl8367d_filter_igrAcl_template_get(rtk_filter_template_t *aclTemplate) +{ + rtk_api_ret_t ret; + rtk_uint32 idxField; + rtl8367d_acltemplate_t aclType; + rtk_uint32 i; + rtk_uint32 regData, regAddr; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == aclTemplate) + return RT_ERR_NULL_POINTER; + + if(aclTemplate->index >= RTK_MAX_NUM_OF_FILTER_TYPE) + return RT_ERR_INPUT; + + regAddr = (RTL8367D_REG_ACL_RULE_TEMPLATE0_CTRL0 + aclTemplate->index * 0x4); + + for(i = 0; i < (RTL8367D_ACLRULEFIELDNO/2); i++) + { + if((ret = rtl8367d_getAsicReg(regAddr + i,®Data)) != RT_ERR_OK) + return ret; + + aclType.field[i*2] = regData & 0xFF; + aclType.field[i*2 + 1] = (regData >> 8) & 0xFF; + } + + for(idxField = 0; idxField < RTK_MAX_NUM_OF_FILTER_FIELD; idxField ++) + { + aclTemplate->fieldType[idxField] = aclType.field[idxField]; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_filter_igrAcl_field_sel_set + * Description: + * Set user defined field selectors in HSB + * Input: + * index - index of field selector 0-15 + * format - Format of field selector + * offset - Retrieving data offset + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * System support 16 user defined field selctors. + * Each selector can be enabled or disable. + * User can defined retrieving 16-bits in many predefiend + * standard l2/l3/l4 payload. + */ +rtk_api_ret_t dal_rtl8367d_filter_igrAcl_field_sel_set(rtk_uint32 index, rtk_field_sel_t format, rtk_uint32 offset) +{ + rtk_api_ret_t ret; + rtk_uint32 regData; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(index >= RTL8367D_FIELDSEL_FORMAT_NUMBER) + return RT_ERR_OUT_OF_RANGE; + + if(format >= FORMAT_END) + return RT_ERR_OUT_OF_RANGE; + + if(offset > RTL8367D_FIELDSEL_MAX_OFFSET) + return RT_ERR_OUT_OF_RANGE; + + regData = ((((rtk_uint32)format << RTL8367D_FIELD_SELECTOR0_FORMAT_OFFSET) & RTL8367D_FIELD_SELECTOR0_FORMAT_MASK ) | + ((offset << RTL8367D_FIELD_SELECTOR0_OFFSET_OFFSET) & RTL8367D_FIELD_SELECTOR0_OFFSET_MASK )); + + if((ret = rtl8367d_setAsicReg((RTL8367D_REG_FIELD_SELECTOR0 + index), regData)) != RT_ERR_OK) + return ret; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_filter_igrAcl_field_sel_get + * Description: + * Get user defined field selectors in HSB + * Input: + * index - index of field selector 0-15 + * Output: + * pFormat - Format of field selector + * pOffset - Retrieving data offset + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * None. + */ +rtk_api_ret_t dal_rtl8367d_filter_igrAcl_field_sel_get(rtk_uint32 index, rtk_field_sel_t *pFormat, rtk_uint32 *pOffset) +{ + rtk_api_ret_t ret; + rtk_uint32 regData; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pFormat || NULL == pOffset) + return RT_ERR_NULL_POINTER; + + if(index >= RTL8367D_FIELDSEL_FORMAT_NUMBER) + return RT_ERR_OUT_OF_RANGE; + + if((ret = rtl8367d_getAsicReg(RTL8367D_REG_FIELD_SELECTOR0 + index, ®Data)) != RT_ERR_OK) + return ret; + + *pFormat = ((regData & RTL8367D_FIELD_SELECTOR0_FORMAT_MASK) >> RTL8367D_FIELD_SELECTOR0_FORMAT_OFFSET); + *pOffset = ((regData & RTL8367D_FIELD_SELECTOR0_OFFSET_MASK) >> RTL8367D_FIELD_SELECTOR0_OFFSET_OFFSET); + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_filter_iprange_set + * Description: + * Set IP Range check + * Input: + * index - index of IP Range 0-15 + * type - IP Range check type, 0:Delete a entry, 1: IPv4_SIP, 2: IPv4_DIP, 3:IPv6_SIP, 4:IPv6_DIP + * upperIp - The upper bound of IP range + * lowerIp - The lower Bound of IP range + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - The parameter is out of range + * RT_ERR_INPUT - Input error + * Note: + * upperIp must be larger or equal than lowerIp. + */ +rtk_api_ret_t dal_rtl8367d_filter_iprange_set(rtk_uint32 index, rtk_filter_iprange_t type, ipaddr_t upperIp, ipaddr_t lowerIp) +{ + rtk_api_ret_t ret; + rtk_uint32 regData; + ipaddr_t ipData; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(index > RTL8367D_ACLRANGEMAX) + return RT_ERR_OUT_OF_RANGE; + + if(type >= IPRANGE_END) + return RT_ERR_OUT_OF_RANGE; + + if(lowerIp > upperIp) + return RT_ERR_INPUT; + + if((ret = rtl8367d_setAsicRegBits(RTL8367D_REG_ACL_IP_RANGE_ENTRY0_CTRL4 + index*5, RTL8367D_ACL_IP_RANGE_ENTRY0_CTRL4_MASK, type)) != RT_ERR_OK) + return ret; + + ipData = upperIp; + + regData = ipData & 0xFFFF; + if((ret = rtl8367d_setAsicReg(RTL8367D_REG_ACL_IP_RANGE_ENTRY0_CTRL2 + index*5, regData)) != RT_ERR_OK) + return ret; + + regData = (ipData>>16) & 0xFFFF; + if((ret = rtl8367d_setAsicReg(RTL8367D_REG_ACL_IP_RANGE_ENTRY0_CTRL3 + index*5, regData)) != RT_ERR_OK) + return ret; + + ipData = lowerIp; + + regData = ipData & 0xFFFF; + if((ret = rtl8367d_setAsicReg(RTL8367D_REG_ACL_IP_RANGE_ENTRY0_CTRL0 + index*5, regData)) != RT_ERR_OK) + return ret; + + regData = (ipData>>16) & 0xFFFF; + if((ret = rtl8367d_setAsicReg(RTL8367D_REG_ACL_IP_RANGE_ENTRY0_CTRL1 + index*5, regData)) != RT_ERR_OK) + return ret; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_filter_iprange_get + * Description: + * Set IP Range check + * Input: + * index - index of IP Range 0-15 + * Output: + * pType - IP Range check type, 0:Delete a entry, 1: IPv4_SIP, 2: IPv4_DIP, 3:IPv6_SIP, 4:IPv6_DIP + * pUpperIp - The upper bound of IP range + * pLowerIp - The lower Bound of IP range + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - The parameter is out of range + * Note: + * None. + */ +rtk_api_ret_t dal_rtl8367d_filter_iprange_get(rtk_uint32 index, rtk_filter_iprange_t *pType, ipaddr_t *pUpperIp, ipaddr_t *pLowerIp) +{ + rtk_api_ret_t ret; + rtk_uint32 regData; + ipaddr_t ipData; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if((NULL == pType) || (NULL == pUpperIp) || (NULL == pLowerIp)) + return RT_ERR_NULL_POINTER; + + if(index > RTL8367D_ACLRANGEMAX) + return RT_ERR_OUT_OF_RANGE; + + if((ret = rtl8367d_getAsicRegBits(RTL8367D_REG_ACL_IP_RANGE_ENTRY0_CTRL4 + index*5, RTL8367D_ACL_IP_RANGE_ENTRY0_CTRL4_MASK, pType)) != RT_ERR_OK) + return ret; + + if((ret = rtl8367d_getAsicReg(RTL8367D_REG_ACL_IP_RANGE_ENTRY0_CTRL2 + index*5, ®Data)) != RT_ERR_OK) + return ret; + + ipData = regData; + + if((ret = rtl8367d_getAsicReg(RTL8367D_REG_ACL_IP_RANGE_ENTRY0_CTRL3 + index*5, ®Data)) != RT_ERR_OK) + return ret; + + ipData = (regData <<16) | ipData; + *pUpperIp = ipData; + + if((ret = rtl8367d_getAsicReg(RTL8367D_REG_ACL_IP_RANGE_ENTRY0_CTRL0 + index*5, ®Data)) != RT_ERR_OK) + return ret; + + ipData = regData; + + if((ret = rtl8367d_getAsicReg(RTL8367D_REG_ACL_IP_RANGE_ENTRY0_CTRL1 + index*5, ®Data)) != RT_ERR_OK) + return ret; + + ipData = (regData << 16) | ipData; + *pLowerIp = ipData; + + return RT_ERR_OK; +} + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_acl.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_acl.h new file mode 100644 index 00000000..65cf1592 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_acl.h @@ -0,0 +1,507 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8367/RTL8367D switch high-level API + * + * Feature : The file includes ACL module high-layer API defination + * + */ + +#ifndef __DAL_RTL8367D_ACL_H__ +#define __DAL_RTL8367D_ACL_H__ + +#include + +#define RTL8367D_ACLRULENO 64 + +#define RTL8367D_ACLRULEMAX (RTL8367D_ACLRULENO-1) +#define RTL8367D_ACLRULEFIELDNO 8 +#define RTL8367D_ACLTEMPLATENO 5 +#define RTL8367D_ACLTYPEMAX (RTL8367D_ACLTEMPLATENO-1) + +#define RTL8367D_ACLRULETBLEN 9 +#define RTL8367D_ACLACTTBLEN 4 +#define RTL8367D_ACLRULETBADDR(type, rule) ((type << 6) | rule) +#define RTL8367D_ACLRULETBADDR2(type, rule) ((type << 5) | (rule + 64)) + +#define ACL_ACT_CVLAN_ENABLE_MASK 0x1 +#define ACL_ACT_SVLAN_ENABLE_MASK 0x2 +#define ACL_ACT_PRIORITY_ENABLE_MASK 0x4 +#define ACL_ACT_POLICING_ENABLE_MASK 0x8 +#define ACL_ACT_FWD_ENABLE_MASK 0x10 +#define ACL_ACT_INTGPIO_ENABLE_MASK 0x20 + +#define RTL8367D_ACLRULETAGBITS 5 + +#define RTL8367D_ACLRANGENO 8 + +#define RTL8367D_ACLRANGEMAX (RTL8367D_ACLRANGENO-1) + +#define RTL8367D_ACL_PORTRANGEMAX (0xFFFF) +#define RTL8367D_ACL_ACT_TABLE_LEN (4) + +#define RTL8367D_FIELDSEL_FORMAT_NUMBER (8) +#define RTL8367D_FIELDSEL_MAX_OFFSET (255) + +#define RTL8367D_MAX_LOG_CNT_NUM (16) + +#define RTL8367D_RTK_IPV6_ADDR_WORD_LENGTH 2UL + +#define RTL8367D_ACLGPIOPINNO 61 + + +enum RTL8367D_FIELDSEL_FORMAT_FORMAT +{ + RTL8367D_FIELDSEL_FORMAT_DEFAULT = 0, + RTL8367D_FIELDSEL_FORMAT_RAW, + RTL8367D_FIELDSEL_FORMAT_LLC, + RTL8367D_FIELDSEL_FORMAT_IPV4, + RTL8367D_FIELDSEL_FORMAT_ARP, + RTL8367D_FIELDSEL_FORMAT_IPV6, + RTL8367D_FIELDSEL_FORMAT_IPPAYLOAD, + RTL8367D_FIELDSEL_FORMAT_L4PAYLOAD, + RTL8367D_FIELDSEL_FORMAT_END +}; + +enum RTL8367D_ACLFIELDTYPES +{ + RTL8367D_ACL_UNUSED, + RTL8367D_ACL_DMAC0, + RTL8367D_ACL_DMAC1, + RTL8367D_ACL_DMAC2, + RTL8367D_ACL_SMAC0, + RTL8367D_ACL_SMAC1, + RTL8367D_ACL_SMAC2, + RTL8367D_ACL_ETHERTYPE, + RTL8367D_ACL_STAG, + RTL8367D_ACL_CTAG, + RTL8367D_ACL_IP4SIP0 = 0x10, + RTL8367D_ACL_IP4SIP1, + RTL8367D_ACL_IP4DIP0, + RTL8367D_ACL_IP4DIP1, + RTL8367D_ACL_IP6SIP0WITHIPV4 = 0x20, + RTL8367D_ACL_IP6SIP1WITHIPV4, + RTL8367D_ACL_IP6DIP0WITHIPV4 = 0x28, + RTL8367D_ACL_IP6DIP1WITHIPV4, + RTL8367D_ACL_L4DPORT = 0x2a, + RTL8367D_ACL_L4SPORT = 0x2b, + RTL8367D_ACL_IPRANGE = 0x31, + RTL8367D_ACL_FIELD_VALID = 0x33, + RTL8367D_ACL_FIELD_SELECT00 = 0x40, + RTL8367D_ACL_FIELD_SELECT01, + RTL8367D_ACL_FIELD_SELECT02, + RTL8367D_ACL_FIELD_SELECT03, + RTL8367D_ACL_FIELD_SELECT04, + RTL8367D_ACL_FIELD_SELECT05, + RTL8367D_ACL_FIELD_SELECT06, + RTL8367D_ACL_FIELD_SELECT07, + RTL8367D_ACL_TYPE_END +}; + +enum RTL8367D_ACLTCAMTYPES +{ + RTL8367D_CAREBITS= 0, + RTL8367D_DATABITS +}; + +typedef enum rtl8367d_aclFwd +{ + RTL8367D_ACL_FWD_MIRROR = 0, + RTL8367D_ACL_FWD_REDIRECT, + RTL8367D_ACL_FWD_MIRRORFUNTION, + RTL8367D_ACL_FWD_TRAP, +} rtl8367d_aclFwd_t; + + +struct rtl8367d_acl_rule_smi_st{ + rtk_uint16 rule_info; + rtk_uint16 field[RTL8367D_ACLRULEFIELDNO]; +}; + +struct rtl8367d_acl_rule_smi_ext_st{ + rtk_uint16 rule_info; +}; + +typedef struct RTL8367D_ACLRULESMI{ + struct rtl8367d_acl_rule_smi_st care_bits; + rtk_uint32 valid; + struct rtl8367d_acl_rule_smi_st data_bits; + +}rtl8367d_aclrulesmi; + +struct rtl8367d_acl_rule_st{ + rtk_uint32 active_portmsk; + rtk_uint32 type; + rtk_uint32 tag_exist; + rtk_uint16 field[RTL8367D_ACLRULEFIELDNO]; +}; + +typedef struct RTL8367D_ACLRULE{ + struct rtl8367d_acl_rule_st data_bits; + rtk_uint32 valid; + struct rtl8367d_acl_rule_st care_bits; +}rtl8367d_aclrule; + + +typedef struct rtl8367d_acltemplate_s{ + rtk_uint8 field[8]; +}rtl8367d_acltemplate_t; + + +typedef struct rtl8367d_acl_act_s{ + rtk_uint32 cvidx_cact; + rtk_uint32 cact; + rtk_uint32 svidx_sact; + rtk_uint32 sact; + + + rtk_uint32 aclmeteridx; + rtk_uint32 fwdpmask; + rtk_uint32 fwdact; + + rtk_uint32 pridx; + rtk_uint32 priact; + rtk_uint32 gpio_pin; + rtk_uint32 gpio_en; + rtk_uint32 aclint; + + rtk_uint32 cact_ext; + rtk_uint32 fwdact_ext; + rtk_uint32 tag_fmt; +}rtl8367d_acl_act_t; + +typedef struct rtl8367d_acl_rule_union_s +{ + rtl8367d_aclrule aclRule; + rtl8367d_acl_act_t aclAct; + rtk_uint32 aclActCtrl; + rtk_uint32 aclNot; +}rtl8367d_acl_rule_union_t; + + +/* Function Name: + * dal_rtl8367d_filter_igrAcl_init + * Description: + * ACL initialization function + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Pointer pFilter_field or pFilter_cfg point to NULL. + * Note: + * This function enable and intialize ACL function + */ +extern rtk_api_ret_t dal_rtl8367d_filter_igrAcl_init(void); + +/* Function Name: + * dal_rtl8367d_filter_igrAcl_field_add + * Description: + * Add comparison rule to an ACL configuration + * Input: + * pFilter_cfg - The ACL configuration that this function will add comparison rule + * pFilter_field - The comparison rule that will be added. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Pointer pFilter_field or pFilter_cfg point to NULL. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This function add a comparison rule (*pFilter_field) to an ACL configuration (*pFilter_cfg). + * Pointer pFilter_cfg points to an ACL configuration structure, this structure keeps multiple ACL + * comparison rules by means of linked list. Pointer pFilter_field will be added to linked + * list keeped by structure that pFilter_cfg points to. + */ +extern rtk_api_ret_t dal_rtl8367d_filter_igrAcl_field_add(rtk_filter_cfg_t *pFilter_cfg, rtk_filter_field_t *pFilter_field); + +/* Function Name: + * dal_rtl8367d_filter_igrAcl_cfg_add + * Description: + * Add an ACL configuration to ASIC + * Input: + * filter_id - Start index of ACL configuration. + * pFilter_cfg - The ACL configuration that this function will add comparison rule + * pFilter_action - Action(s) of ACL configuration. + * Output: + * ruleNum - number of rules written in acl table + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Pointer pFilter_field or pFilter_cfg point to NULL. + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_ENTRY_INDEX - Invalid filter_id . + * RT_ERR_NULL_POINTER - Pointer pFilter_action or pFilter_cfg point to NULL. + * RT_ERR_FILTER_INACL_ACT_NOT_SUPPORT - Action is not supported in this chip. + * RT_ERR_FILTER_INACL_RULE_NOT_SUPPORT - Rule is not supported. + * Note: + * This function store pFilter_cfg, pFilter_action into ASIC. The starting + * index(es) is filter_id. + */ +extern rtk_api_ret_t dal_rtl8367d_filter_igrAcl_cfg_add(rtk_filter_id_t filter_id, rtk_filter_cfg_t *pFilter_cfg, rtk_filter_action_t *pAction, rtk_filter_number_t *ruleNum); + +/* Function Name: + * dal_rtl8367d_filter_igrAcl_cfg_del + * Description: + * Delete an ACL configuration from ASIC + * Input: + * filter_id - Start index of ACL configuration. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_ENTRYIDX - Invalid filter_id. + * Note: + * This function delete a group of ACL rules starting from filter_id. + */ +extern rtk_api_ret_t dal_rtl8367d_filter_igrAcl_cfg_del(rtk_filter_id_t filter_id); + +/* Function Name: + * dal_rtl8367d_filter_igrAcl_cfg_delAll + * Description: + * Delete all ACL entries from ASIC + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This function delete all ACL configuration from ASIC. + */ +extern rtk_api_ret_t dal_rtl8367d_filter_igrAcl_cfg_delAll(void); + +/* Function Name: + * dal_rtl8367d_filter_igrAcl_cfg_get + * Description: + * Get one ingress acl configuration from ASIC. + * Input: + * filter_id - Start index of ACL configuration. + * Output: + * pFilter_cfg - buffer pointer of ingress acl data + * pFilter_action - buffer pointer of ingress acl action + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Pointer pFilter_action or pFilter_cfg point to NULL. + * RT_ERR_FILTER_ENTRYIDX - Invalid entry index. + * Note: + * This function delete all ACL configuration from ASIC. + */ +extern rtk_api_ret_t dal_rtl8367d_filter_igrAcl_cfg_get(rtk_filter_id_t filter_id, rtk_filter_cfg_raw_t *pFilter_cfg, rtk_filter_action_t *pAction); + +/* Function Name: + * dal_rtl8367d_filter_igrAcl_unmatchAction_set + * Description: + * Set action to packets when no ACL configuration match + * Input: + * port - Port id. + * action - Action. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port id. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This function sets action of packets when no ACL configruation matches. + */ +extern rtk_api_ret_t dal_rtl8367d_filter_igrAcl_unmatchAction_set(rtk_port_t port, rtk_filter_unmatch_action_t action); + +/* Function Name: + * dal_rtl8367d_filter_igrAcl_unmatchAction_get + * Description: + * Get action to packets when no ACL configuration match + * Input: + * port - Port id. + * Output: + * pAction - Action. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port id. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This function gets action of packets when no ACL configruation matches. + */ +extern rtk_api_ret_t dal_rtl8367d_filter_igrAcl_unmatchAction_get(rtk_port_t port, rtk_filter_unmatch_action_t* action); + +/* Function Name: + * dal_rtl8367d_filter_igrAcl_state_set + * Description: + * Set state of ingress ACL. + * Input: + * port - Port id. + * state - Ingress ACL state. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port id. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This function gets action of packets when no ACL configruation matches. + */ +extern rtk_api_ret_t dal_rtl8367d_filter_igrAcl_state_set(rtk_port_t port, rtk_filter_state_t state); + +/* Function Name: + * dal_rtl8367d_filter_igrAcl_state_get + * Description: + * Get state of ingress ACL. + * Input: + * port - Port id. + * Output: + * pState - Ingress ACL state. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port id. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This function gets action of packets when no ACL configruation matches. + */ +extern rtk_api_ret_t dal_rtl8367d_filter_igrAcl_state_get(rtk_port_t port, rtk_filter_state_t* state); + +/* Function Name: + * dal_rtl8367d_filter_igrAcl_template_set + * Description: + * Set template of ingress ACL. + * Input: + * template - Ingress ACL template + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This function set ACL template. + */ +extern rtk_api_ret_t dal_rtl8367d_filter_igrAcl_template_set(rtk_filter_template_t *aclTemplate); + +/* Function Name: + * dal_rtl8367d_filter_igrAcl_template_get + * Description: + * Get template of ingress ACL. + * Input: + * template - Ingress ACL template + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This function gets template of ACL. + */ +extern rtk_api_ret_t dal_rtl8367d_filter_igrAcl_template_get(rtk_filter_template_t *aclTemplate); + +/* Function Name: + * dal_rtl8367d_filter_igrAcl_field_sel_set + * Description: + * Set user defined field selectors in HSB + * Input: + * index - index of field selector 0-15 + * format - Format of field selector + * offset - Retrieving data offset + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * System support 16 user defined field selctors. + * Each selector can be enabled or disable. + * User can defined retrieving 16-bits in many predefiend + * standard l2/l3/l4 payload. + */ +extern rtk_api_ret_t dal_rtl8367d_filter_igrAcl_field_sel_set(rtk_uint32 index, rtk_field_sel_t format, rtk_uint32 offset); + +/* Function Name: + * dal_rtl8367d_filter_igrAcl_field_sel_get + * Description: + * Get user defined field selectors in HSB + * Input: + * index - index of field selector 0-15 + * Output: + * pFormat - Format of field selector + * pOffset - Retrieving data offset + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * None. + */ +extern rtk_api_ret_t dal_rtl8367d_filter_igrAcl_field_sel_get(rtk_uint32 index, rtk_field_sel_t *pFormat, rtk_uint32 *pOffset); + +/* Function Name: + * dal_rtl8367d_filter_iprange_set + * Description: + * Set IP Range check + * Input: + * index - index of IP Range 0-15 + * type - IP Range check type, 0:Delete a entry, 1: IPv4_SIP, 2: IPv4_DIP, 3:IPv6_SIP, 4:IPv6_DIP + * upperIp - The upper bound of IP range + * lowerIp - The lower Bound of IP range + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - The parameter is out of range + * RT_ERR_INPUT - Input error + * Note: + * upperIp must be larger or equal than lowerIp. + */ +extern rtk_api_ret_t dal_rtl8367d_filter_iprange_set(rtk_uint32 index, rtk_filter_iprange_t type, ipaddr_t upperIp, ipaddr_t lowerIp); + +/* Function Name: + * dal_rtl8367d_filter_iprange_get + * Description: + * Set IP Range check + * Input: + * index - index of IP Range 0-15 + * Output: + * pType - IP Range check type, 0:Delete a entry, 1: IPv4_SIP, 2: IPv4_DIP, 3:IPv6_SIP, 4:IPv6_DIP + * pUpperIp - The upper bound of IP range + * pLowerIp - The lower Bound of IP range + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - The parameter is out of range + * Note: + * upperIp must be larger or equal than lowerIp. + */ +extern rtk_api_ret_t dal_rtl8367d_filter_iprange_get(rtk_uint32 index, rtk_filter_iprange_t *pType, ipaddr_t *pUpperIp, ipaddr_t *pLowerIp); + +#endif /* __DAL_RTL8367D_ACL_H__ */ diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_cpu.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_cpu.c new file mode 100644 index 00000000..3f7e97c1 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_cpu.c @@ -0,0 +1,576 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8367D + * Feature : Here is a list of all functions and variables in CPU module. + * + */ + +#include +#include +#include + +#include + +#include + +/* Function Name: + * dal_rtl8367d_cpu_enable_set + * Description: + * Set CPU port function enable/disable. + * Input: + * enable - CPU port function enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can set CPU port function enable/disable. + */ +rtk_api_ret_t dal_rtl8367d_cpu_enable_set(rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (enable >= RTK_ENABLE_END) + return RT_ERR_ENABLE; + + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_CPU_CTRL, RTL8367D_CPU_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + + if (DISABLED == enable) + { + if ((retVal = rtl8367d_setAsicReg(RTL8367D_REG_CPU_PORT_MASK, 0)) != RT_ERR_OK) + return retVal; + } + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8367d_cpu_enable_get + * Description: + * Get CPU port and its setting. + * Input: + * None + * Output: + * pEnable - CPU port function enable + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_L2_NO_CPU_PORT - CPU port is not exist + * Note: + * The API can get CPU port function enable/disable. + */ +rtk_api_ret_t dal_rtl8367d_cpu_enable_get(rtk_enable_t *pEnable) + +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pEnable) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_CPU_CTRL, RTL8367D_CPU_EN_OFFSET, pEnable)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_cpu_tagPort_set + * Description: + * Set CPU port and CPU tag insert mode. + * Input: + * port - Port id. + * mode - CPU tag insert for packets egress from CPU port. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can set CPU port and inserting proprietary CPU tag mode (Length/Type 0x8899) + * to the frame that transmitting to CPU port. + * The inset cpu tag mode is as following: + * - CPU_INSERT_TO_ALL + * - CPU_INSERT_TO_TRAPPING + * - CPU_INSERT_TO_NONE + */ +rtk_api_ret_t dal_rtl8367d_cpu_tagPort_set(rtk_port_t port, rtk_cpu_insert_t mode) +{ + rtk_api_ret_t retVal; + rtk_uint32 phyPort; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check port Valid */ + RTK_CHK_PORT_VALID(port); + + if (mode >= CPU_INSERT_END) + return RT_ERR_INPUT; + + phyPort = rtk_switch_port_L2P_get(port); + if (phyPort == UNDEFINE_PHY_PORT) + return RT_ERR_PORT_ID; + + if ((retVal = rtl8367d_setAsicReg(RTL8367D_REG_CPU_PORT_MASK, (1 << phyPort))) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_CPU_CTRL, RTL8367D_CPU_TRAP_PORT_MASK, (phyPort & 7))) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_CPU_CTRL, RTL8367D_CPU_INSERTMODE_MASK, mode)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_cpu_tagPort_get + * Description: + * Get CPU port and CPU tag insert mode. + * Input: + * None + * Output: + * pPort - Port id. + * pMode - CPU tag insert for packets egress from CPU port, 0:all insert 1:Only for trapped packets 2:no insert. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_L2_NO_CPU_PORT - CPU port is not exist + * Note: + * The API can get configured CPU port and its setting. + * The inset cpu tag mode is as following: + * - CPU_INSERT_TO_ALL + * - CPU_INSERT_TO_TRAPPING + * - CPU_INSERT_TO_NONE + */ +rtk_api_ret_t dal_rtl8367d_cpu_tagPort_get(rtk_port_t *pPort, rtk_cpu_insert_t *pMode) +{ + rtk_api_ret_t retVal; + rtk_uint32 pmsk, port; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pPort) + return RT_ERR_NULL_POINTER; + + if(NULL == pMode) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367d_getAsicReg(RTL8367D_REG_CPU_PORT_MASK, &pmsk)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_CPU_CTRL, RTL8367D_CPU_TRAP_PORT_MASK, &port)) != RT_ERR_OK) + return retVal; + + *pPort = rtk_switch_port_P2L_get(port); + + if ((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_CPU_CTRL, RTL8367D_CPU_INSERTMODE_MASK, pMode)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_cpu_awarePort_set + * Description: + * Set CPU aware port mask. + * Input: + * portmask - Port mask. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Invalid port mask. + * Note: + * The API can set configured CPU aware port mask. + */ +rtk_api_ret_t dal_rtl8367d_cpu_awarePort_set(rtk_portmask_t *pPortmask) +{ + rtk_api_ret_t retVal; + rtk_uint32 phyMbrPmask; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Valid port mask */ + if(NULL == pPortmask) + return RT_ERR_NULL_POINTER; + + /* Check port mask valid */ + RTK_CHK_PORTMASK_VALID(pPortmask); + + if(rtk_switch_portmask_L2P_get(pPortmask, &phyMbrPmask) != RT_ERR_OK) + return RT_ERR_FAILED; + + if ((retVal = rtl8367d_setAsicReg(RTL8367D_REG_CPU_PORT_MASK, phyMbrPmask)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_cpu_awarePort_get + * Description: + * Get CPU aware port mask. + * Input: + * None + * Output: + * pPortmask - Port mask. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can get configured CPU aware port mask. + */ +rtk_api_ret_t dal_rtl8367d_cpu_awarePort_get(rtk_portmask_t *pPortmask) +{ + rtk_api_ret_t retVal; + rtk_uint32 pmsk; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pPortmask) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367d_getAsicReg(RTL8367D_REG_CPU_PORT_MASK, &pmsk)) != RT_ERR_OK) + return retVal; + + if(rtk_switch_portmask_P2L_get(pmsk, pPortmask) != RT_ERR_OK) + return RT_ERR_FAILED; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_cpu_tagPosition_set + * Description: + * Set CPU tag position. + * Input: + * position - CPU tag position. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input. + * Note: + * The API can set CPU tag position. + */ +rtk_api_ret_t dal_rtl8367d_cpu_tagPosition_set(rtk_cpu_position_t position) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (position >= CPU_POS_END) + return RT_ERR_INPUT; + + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_CPU_CTRL, RTL8367D_CPU_TAG_POSITION_OFFSET, position)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_cpu_tagPosition_get + * Description: + * Get CPU tag position. + * Input: + * None + * Output: + * pPosition - CPU tag position. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input. + * Note: + * The API can get CPU tag position. + */ +rtk_api_ret_t dal_rtl8367d_cpu_tagPosition_get(rtk_cpu_position_t *pPosition) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pPosition) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_CPU_CTRL, RTL8367D_CPU_TAG_POSITION_OFFSET, pPosition)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_cpu_tagLength_set + * Description: + * Set CPU tag length. + * Input: + * length - CPU tag length. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input. + * Note: + * The API can set CPU tag length. + */ +rtk_api_ret_t dal_rtl8367d_cpu_tagLength_set(rtk_cpu_tag_length_t length) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + switch (length) + { + case CPU_LEN_8BYTES: + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_CPU_CTRL, RTL8367D_CPU_TAG_FORMAT_OFFSET, 0)) != RT_ERR_OK) + return retVal; + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_CPU_CTRL, RTL8367D_CPU_TAG_FORMAT_PRI_OFFSET, 0)) != RT_ERR_OK) + return retVal; + break; + case CPU_LEN_4BYTES: + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_CPU_CTRL, RTL8367D_CPU_TAG_FORMAT_OFFSET, 1)) != RT_ERR_OK) + return retVal; + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_CPU_CTRL, RTL8367D_CPU_TAG_FORMAT_PRI_OFFSET, 0)) != RT_ERR_OK) + return retVal; + break; + case CPU_LEN_4BYTES_PRIORITY: + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_CPU_CTRL, RTL8367D_CPU_TAG_FORMAT_OFFSET, 1)) != RT_ERR_OK) + return retVal; + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_CPU_CTRL, RTL8367D_CPU_TAG_FORMAT_PRI_OFFSET, 1)) != RT_ERR_OK) + return retVal; + break; + default: + return RT_ERR_INPUT; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_cpu_tagLength_get + * Description: + * Get CPU tag length. + * Input: + * None + * Output: + * pLength - CPU tag length. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input. + * Note: + * The API can get CPU tag length. + */ +rtk_api_ret_t dal_rtl8367d_cpu_tagLength_get(rtk_cpu_tag_length_t *pLength) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + rtk_uint32 regData2; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pLength) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_CPU_CTRL, RTL8367D_CPU_TAG_FORMAT_OFFSET, ®Data)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_CPU_CTRL, RTL8367D_CPU_TAG_FORMAT_PRI_OFFSET, ®Data2)) != RT_ERR_OK) + return retVal; + + if (regData == 0) + *pLength = CPU_LEN_8BYTES; + else + { + if (regData2 == 0) + *pLength = CPU_LEN_4BYTES; + else + *pLength = CPU_LEN_4BYTES_PRIORITY; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_cpu_priRemap_set + * Description: + * Configure CPU priorities mapping to internal absolute priority. + * Input: + * int_pri - internal priority value. + * new_pri - new internal priority value. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_VLAN_PRIORITY - Invalid 1p priority. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * Priority of CPU tag assignment for internal asic priority, and it is used for queue usage and packet scheduling. + */ +rtk_api_ret_t dal_rtl8367d_cpu_priRemap_set(rtk_pri_t int_pri, rtk_pri_t new_pri) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (new_pri > RTL8367D_PRIMAX || int_pri > RTL8367D_PRIMAX) + return RT_ERR_VLAN_PRIORITY; + + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL0 + (int_pri >> 2), RTL8367D_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL0_PRIORITY0_MASK << ((int_pri & 0x3) << 2), new_pri)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_cpu_priRemap_get + * Description: + * Configure CPU priorities mapping to internal absolute priority. + * Input: + * int_pri - internal priority value. + * Output: + * pNew_pri - new internal priority value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_VLAN_PRIORITY - Invalid 1p priority. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * Priority of CPU tag assignment for internal asic priority, and it is used for queue usage and packet scheduling. + */ +rtk_api_ret_t dal_rtl8367d_cpu_priRemap_get(rtk_pri_t int_pri, rtk_pri_t *pNew_pri) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pNew_pri) + return RT_ERR_NULL_POINTER; + + if (int_pri > RTL8367D_PRIMAX) + return RT_ERR_QOS_INT_PRIORITY; + + if ((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL0 + (int_pri >> 2), RTL8367D_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL0_PRIORITY0_MASK << ((int_pri & 0x3) << 2), pNew_pri)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_cpu_acceptLength_set + * Description: + * Set CPU accept length. + * Input: + * length - CPU tag length. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input. + * Note: + * The API can set CPU accept length. + */ +rtk_api_ret_t dal_rtl8367d_cpu_acceptLength_set(rtk_cpu_rx_length_t length) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (length >= CPU_RX_END) + return RT_ERR_INPUT; + + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_CPU_CTRL, RTL8367D_CPU_TAG_RXBYTECOUNT_OFFSET, length)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_cpu_acceptLength_get + * Description: + * Get CPU accept length. + * Input: + * None + * Output: + * pLength - CPU tag length. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input. + * Note: + * The API can get CPU accept length. + */ +rtk_api_ret_t dal_rtl8367d_cpu_acceptLength_get(rtk_cpu_rx_length_t *pLength) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pLength) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_CPU_CTRL, RTL8367D_CPU_TAG_RXBYTECOUNT_OFFSET, pLength)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_cpu.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_cpu.h new file mode 100644 index 00000000..0dc47657 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_cpu.h @@ -0,0 +1,295 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8367/RTL8367D switch high-level API + * + * Feature : The file includes CPU module high-layer API defination + * + */ + +#ifndef __DAL_RTL8367D_CPU_H__ +#define __DAL_RTL8367D_CPU_H__ +#include <../../cpu.h> + +/* Function Name: + * dal_rtl8367d_cpu_enable_set + * Description: + * Set CPU port function enable/disable. + * Input: + * enable - CPU port function enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can set CPU port function enable/disable. + */ +extern rtk_api_ret_t dal_rtl8367d_cpu_enable_set(rtk_enable_t enable); + +/* Function Name: + * dal_rtl8367d_cpu_enable_get + * Description: + * Get CPU port and its setting. + * Input: + * None + * Output: + * pEnable - CPU port function enable + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_L2_NO_CPU_PORT - CPU port is not exist + * Note: + * The API can get CPU port function enable/disable. + */ +extern rtk_api_ret_t dal_rtl8367d_cpu_enable_get(rtk_enable_t *pEnable); + +/* Function Name: + * dal_rtl8367d_cpu_tagPort_set + * Description: + * Set CPU port and CPU tag insert mode. + * Input: + * port - Port id. + * mode - CPU tag insert for packets egress from CPU port. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can set CPU port and inserting proprietary CPU tag mode (Length/Type 0x8899) + * to the frame that transmitting to CPU port. + * The inset cpu tag mode is as following: + * - CPU_INSERT_TO_ALL + * - CPU_INSERT_TO_TRAPPING + * - CPU_INSERT_TO_NONE + */ +extern rtk_api_ret_t dal_rtl8367d_cpu_tagPort_set(rtk_port_t port, rtk_cpu_insert_t mode); + +/* Function Name: + * dal_rtl8367d_cpu_tagPort_get + * Description: + * Get CPU port and CPU tag insert mode. + * Input: + * None + * Output: + * pPort - Port id. + * pMode - CPU tag insert for packets egress from CPU port, 0:all insert 1:Only for trapped packets 2:no insert. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_L2_NO_CPU_PORT - CPU port is not exist + * Note: + * The API can get configured CPU port and its setting. + * The inset cpu tag mode is as following: + * - CPU_INSERT_TO_ALL + * - CPU_INSERT_TO_TRAPPING + * - CPU_INSERT_TO_NONE + */ +extern rtk_api_ret_t dal_rtl8367d_cpu_tagPort_get(rtk_port_t *pPort, rtk_cpu_insert_t *pMode); + +/* Function Name: + * dal_rtl8367d_cpu_awarePort_set + * Description: + * Set CPU aware port mask. + * Input: + * portmask - Port mask. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Invalid port mask. + * Note: + * The API can set configured CPU aware port mask. + */ +extern rtk_api_ret_t dal_rtl8367d_cpu_awarePort_set(rtk_portmask_t *pPortmask); + + +/* Function Name: + * dal_rtl8367d_cpu_awarePort_get + * Description: + * Get CPU aware port mask. + * Input: + * None + * Output: + * pPortmask - Port mask. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can get configured CPU aware port mask. + */ +extern rtk_api_ret_t dal_rtl8367d_cpu_awarePort_get(rtk_portmask_t *pPortmask); + +/* Function Name: + * dal_rtl8367d_cpu_tagPosition_set + * Description: + * Set CPU tag position. + * Input: + * position - CPU tag position. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input. + * Note: + * The API can set CPU tag position. + */ +extern rtk_api_ret_t dal_rtl8367d_cpu_tagPosition_set(rtk_cpu_position_t position); + +/* Function Name: + * dal_rtl8367d_cpu_tagPosition_get + * Description: + * Get CPU tag position. + * Input: + * None + * Output: + * pPosition - CPU tag position. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input. + * Note: + * The API can get CPU tag position. + */ +extern rtk_api_ret_t dal_rtl8367d_cpu_tagPosition_get(rtk_cpu_position_t *pPosition); + +/* Function Name: + * dal_rtl8367d_cpu_tagLength_set + * Description: + * Set CPU tag length. + * Input: + * length - CPU tag length. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input. + * Note: + * The API can set CPU tag length. + */ +extern rtk_api_ret_t dal_rtl8367d_cpu_tagLength_set(rtk_cpu_tag_length_t length); + +/* Function Name: + * dal_rtl8367d_cpu_tagLength_get + * Description: + * Get CPU tag length. + * Input: + * None + * Output: + * pLength - CPU tag length. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input. + * Note: + * The API can get CPU tag length. + */ +extern rtk_api_ret_t dal_rtl8367d_cpu_tagLength_get(rtk_cpu_tag_length_t *pLength); + +/* Function Name: + * dal_rtl8367d_cpu_acceptLength_set + * Description: + * Set CPU accept length. + * Input: + * length - CPU tag length. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input. + * Note: + * The API can set CPU accept length. + */ +extern rtk_api_ret_t dal_rtl8367d_cpu_acceptLength_set(rtk_cpu_rx_length_t length); + +/* Function Name: + * dal_rtl8367d_cpu_acceptLength_get + * Description: + * Get CPU accept length. + * Input: + * None + * Output: + * pLength - CPU tag length. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input. + * Note: + * The API can get CPU accept length. + */ +extern rtk_api_ret_t dal_rtl8367d_cpu_acceptLength_get(rtk_cpu_rx_length_t *pLength); + +/* Function Name: + * dal_rtl8367d_cpu_priRemap_set + * Description: + * Configure CPU priorities mapping to internal absolute priority. + * Input: + * int_pri - internal priority value. + * new_pri - new internal priority value. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_VLAN_PRIORITY - Invalid 1p priority. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * Priority of CPU tag assignment for internal asic priority, and it is used for queue usage and packet scheduling. + */ +extern rtk_api_ret_t dal_rtl8367d_cpu_priRemap_set(rtk_pri_t int_pri, rtk_pri_t new_pri); + +/* Function Name: + * dal_rtl8367d_cpu_priRemap_get + * Description: + * Configure CPU priorities mapping to internal absolute priority. + * Input: + * int_pri - internal priority value. + * Output: + * pNew_pri - new internal priority value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_VLAN_PRIORITY - Invalid 1p priority. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * Priority of CPU tag assignment for internal asic priority, and it is used for queue usage and packet scheduling. + */ +extern rtk_api_ret_t dal_rtl8367d_cpu_priRemap_get(rtk_pri_t int_pri, rtk_pri_t *pNew_pri); + + +#endif /* __DAL_RTL8367D_CPU_H__ */ diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_dot1x.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_dot1x.c new file mode 100644 index 00000000..0d3b1b3d --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_dot1x.c @@ -0,0 +1,438 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8367C + * Feature : Here is a list of all functions and variables in 1X module. + * + */ + +#include +#include +#include +#include +#include +#include +#include + +/* Function Name: + * dal_rtl8367d_dot1x_unauthPacketOper_set + * Description: + * Set 802.1x unauth action configuration. + * Input: + * port - Port id. + * unauth_action - 802.1X unauth action. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameter. + * Note: + * This API can set 802.1x unauth action configuration. + * The unauth action is as following: + * - DOT1X_ACTION_DROP + * - DOT1X_ACTION_TRAP2CPU + * - DOT1X_ACTION_GUESTVLAN + */ +rtk_api_ret_t dal_rtl8367d_dot1x_unauthPacketOper_set(rtk_port_t port, rtk_dot1x_unauth_action_t unauth_action) +{ + rtk_api_ret_t retVal; + rtk_uint32 phyPort; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check port Valid */ + RTK_CHK_PORT_VALID(port); + + if (unauth_action >= DOT1X_ACTION_GUESTVLAN) + return RT_ERR_DOT1X_PROC; + + phyPort = rtk_switch_port_L2P_get(port); + if (phyPort == UNDEFINE_PHY_PORT) + return RT_ERR_PORT_ID; + + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_DOT1X_UNAUTH_ACT_W0, RTL8367D_DOT1X_PORT0_UNAUTHBH_MASK << phyPort, unauth_action)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_dot1x_unauthPacketOper_get + * Description: + * Get 802.1x unauth action configuration. + * Input: + * port - Port id. + * Output: + * pUnauth_action - 802.1X unauth action. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can get 802.1x unauth action configuration. + * The unauth action is as following: + * - DOT1X_ACTION_DROP + * - DOT1X_ACTION_TRAP2CPU + * - DOT1X_ACTION_GUESTVLAN + */ +rtk_api_ret_t dal_rtl8367d_dot1x_unauthPacketOper_get(rtk_port_t port, rtk_dot1x_unauth_action_t *pUnauth_action) +{ + rtk_api_ret_t retVal; + rtk_uint32 phyPort; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check port Valid */ + RTK_CHK_PORT_VALID(port); + + if(NULL == pUnauth_action) + return RT_ERR_NULL_POINTER; + + phyPort = rtk_switch_port_L2P_get(port); + if (phyPort == UNDEFINE_PHY_PORT) + return RT_ERR_PORT_ID; + + if ((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_DOT1X_UNAUTH_ACT_W0, RTL8367D_DOT1X_PORT0_UNAUTHBH_MASK << phyPort, pUnauth_action)) != RT_ERR_OK) + return retVal; + + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_dot1x_eapolFrame2CpuEnable_set + * Description: + * Set 802.1x EAPOL packet trap to CPU configuration + * Input: + * enable - The status of 802.1x EAPOL packet. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * To support 802.1x authentication functionality, EAPOL frame (ether type = 0x888E) has to + * be trapped to CPU. + * The status of EAPOL frame trap to CPU is as following: + * - DISABLED + * - ENABLED + */ +rtk_api_ret_t dal_rtl8367d_dot1x_eapolFrame2CpuEnable_set(rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + rtk_uint32 action; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (enable >= RTK_ENABLE_END) + return RT_ERR_ENABLE; + + if ((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_RMA_CTRL03,RTL8367D_RMA_CTRL03_OPERATION_MASK, &action)) != RT_ERR_OK) + return retVal; + + if (ENABLED == enable) + action = RMA_ACTION_TRAP2CPU; + else if (DISABLED == enable) + { + if (RMA_ACTION_TRAP2CPU == action) + action = RMA_ACTION_FORWARD; + } + + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_RMA_CTRL03,RTL8367D_RMA_CTRL03_OPERATION_MASK, action)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_dot1x_eapolFrame2CpuEnable_get + * Description: + * Get 802.1x EAPOL packet trap to CPU configuration + * Input: + * None + * Output: + * pEnable - The status of 802.1x EAPOL packet. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * To support 802.1x authentication functionality, EAPOL frame (ether type = 0x888E) has to + * be trapped to CPU. + * The status of EAPOL frame trap to CPU is as following: + * - DISABLED + * - ENABLED + */ +rtk_api_ret_t dal_rtl8367d_dot1x_eapolFrame2CpuEnable_get(rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + rtk_uint32 action; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pEnable) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_RMA_CTRL03,RTL8367D_RMA_CTRL03_OPERATION_MASK, &action)) != RT_ERR_OK) + return retVal; + + if (RMA_ACTION_TRAP2CPU == action) + *pEnable = ENABLED; + else + *pEnable = DISABLED; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_dot1x_portBasedEnable_set + * Description: + * Set 802.1x port-based enable configuration + * Input: + * port - Port id. + * enable - The status of 802.1x port. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * RT_ERR_DOT1X_PORTBASEDPNEN - 802.1X port-based enable error + * Note: + * The API can update the port-based port enable register content. If a port is 802.1x + * port based network access control "enabled", it should be authenticated so packets + * from that port won't be dropped or trapped to CPU. + * The status of 802.1x port-based network access control is as following: + * - DISABLED + * - ENABLED + */ +rtk_api_ret_t dal_rtl8367d_dot1x_portBasedEnable_set(rtk_port_t port, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check port Valid */ + RTK_CHK_PORT_VALID(port); + + if (enable >= RTK_ENABLE_END) + return RT_ERR_ENABLE; + + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_DOT1X_PORT_ENABLE, rtk_switch_port_L2P_get(port), enable)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_dot1x_portBasedEnable_get + * Description: + * Get 802.1x port-based enable configuration + * Input: + * port - Port id. + * Output: + * pEnable - The status of 802.1x port. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get the 802.1x port-based port status. + */ +rtk_api_ret_t dal_rtl8367d_dot1x_portBasedEnable_get(rtk_port_t port, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check port Valid */ + RTK_CHK_PORT_VALID(port); + + if(NULL == pEnable) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_DOT1X_PORT_ENABLE, rtk_switch_port_L2P_get(port), pEnable)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_dot1x_portBasedAuthStatus_set + * Description: + * Set 802.1x port-based auth. port configuration + * Input: + * port - Port id. + * port_auth - The status of 802.1x port. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_DOT1X_PORTBASEDAUTH - 802.1X port-based auth error + * Note: + * The authenticated status of 802.1x port-based network access control is as following: + * - UNAUTH + * - AUTH + */ +rtk_api_ret_t dal_rtl8367d_dot1x_portBasedAuthStatus_set(rtk_port_t port, rtk_dot1x_auth_status_t port_auth) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check port Valid */ + RTK_CHK_PORT_VALID(port); + + if (port_auth >= AUTH_STATUS_END) + return RT_ERR_DOT1X_PORTBASEDAUTH; + + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_DOT1X_PORT_AUTH, rtk_switch_port_L2P_get(port), port_auth)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_dot1x_portBasedAuthStatus_get + * Description: + * Get 802.1x port-based auth. port configuration + * Input: + * port - Port id. + * Output: + * pPort_auth - The status of 802.1x port. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get 802.1x port-based port auth.information. + */ +rtk_api_ret_t dal_rtl8367d_dot1x_portBasedAuthStatus_get(rtk_port_t port, rtk_dot1x_auth_status_t *pPort_auth) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pPort_auth) + return RT_ERR_NULL_POINTER; + + /* Check port Valid */ + RTK_CHK_PORT_VALID(port); + + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_DOT1X_PORT_AUTH, rtk_switch_port_L2P_get(port), pPort_auth)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_dot1x_portBasedDirection_set + * Description: + * Set 802.1x port-based operational direction configuration + * Input: + * port - Port id. + * port_direction - Operation direction + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_DOT1X_PORTBASEDOPDIR - 802.1X port-based operation direction error + * Note: + * The operate controlled direction of 802.1x port-based network access control is as following: + * - BOTH + * - IN + */ +rtk_api_ret_t dal_rtl8367d_dot1x_portBasedDirection_set(rtk_port_t port, rtk_dot1x_direction_t port_direction) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check port Valid */ + RTK_CHK_PORT_VALID(port); + + if (port_direction >= DIRECTION_END) + return RT_ERR_DOT1X_PORTBASEDOPDIR; + + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_DOT1X_PORT_OPDIR, rtk_switch_port_L2P_get(port), port_direction)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_dot1x_portBasedDirection_get + * Description: + * Get 802.1X port-based operational direction configuration + * Input: + * port - Port id. + * Output: + * pPort_direction - Operation direction + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get 802.1x port-based operational direction information. + */ +rtk_api_ret_t dal_rtl8367d_dot1x_portBasedDirection_get(rtk_port_t port, rtk_dot1x_direction_t *pPort_direction) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pPort_direction) + return RT_ERR_NULL_POINTER; + + /* Check port Valid */ + RTK_CHK_PORT_VALID(port); + + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_DOT1X_PORT_OPDIR, rtk_switch_port_L2P_get(port), pPort_direction)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_dot1x.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_dot1x.h new file mode 100644 index 00000000..1d9f3bea --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_dot1x.h @@ -0,0 +1,243 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8367/RTL8367C switch high-level API + * + * Feature : The file includes 1X module high-layer API defination + * + */ + +#ifndef __DAL_RTL8367D_DOT1X_H__ +#define __DAL_RTL8367D_DOT1X_H__ + +#include + +/* Function Name: + * dal_rtl8367d_dot1x_unauthPacketOper_set + * Description: + * Set 802.1x unauth action configuration. + * Input: + * port - Port id. + * unauth_action - 802.1X unauth action. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameter. + * Note: + * This API can set 802.1x unauth action configuration. + * The unauth action is as following: + * - DOT1X_ACTION_DROP + * - DOT1X_ACTION_TRAP2CPU + * - DOT1X_ACTION_GUESTVLAN + */ +extern rtk_api_ret_t dal_rtl8367d_dot1x_unauthPacketOper_set(rtk_port_t port, rtk_dot1x_unauth_action_t unauth_action); + +/* Function Name: + * dal_rtl8367d_dot1x_unauthPacketOper_get + * Description: + * Get 802.1x unauth action configuration. + * Input: + * port - Port id. + * Output: + * pUnauth_action - 802.1X unauth action. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can get 802.1x unauth action configuration. + * The unauth action is as following: + * - DOT1X_ACTION_DROP + * - DOT1X_ACTION_TRAP2CPU + * - DOT1X_ACTION_GUESTVLAN + */ +extern rtk_api_ret_t dal_rtl8367d_dot1x_unauthPacketOper_get(rtk_port_t port, rtk_dot1x_unauth_action_t *pUnauth_action); + +/* Function Name: + * dal_rtl8367d_dot1x_eapolFrame2CpuEnable_set + * Description: + * Set 802.1x EAPOL packet trap to CPU configuration + * Input: + * enable - The status of 802.1x EAPOL packet. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * To support 802.1x authentication functionality, EAPOL frame (ether type = 0x888E) has to + * be trapped to CPU. + * The status of EAPOL frame trap to CPU is as following: + * - DISABLED + * - ENABLED + */ +extern rtk_api_ret_t dal_rtl8367d_dot1x_eapolFrame2CpuEnable_set(rtk_enable_t enable); + +/* Function Name: + * dal_rtl8367d_dot1x_eapolFrame2CpuEnable_get + * Description: + * Get 802.1x EAPOL packet trap to CPU configuration + * Input: + * None + * Output: + * pEnable - The status of 802.1x EAPOL packet. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * To support 802.1x authentication functionality, EAPOL frame (ether type = 0x888E) has to + * be trapped to CPU. + * The status of EAPOL frame trap to CPU is as following: + * - DISABLED + * - ENABLED + */ +extern rtk_api_ret_t dal_rtl8367d_dot1x_eapolFrame2CpuEnable_get(rtk_enable_t *pEnable); + +/* Function Name: + * dal_rtl8367d_dot1x_portBasedEnable_set + * Description: + * Set 802.1x port-based enable configuration + * Input: + * port - Port id. + * enable - The status of 802.1x port. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * RT_ERR_DOT1X_PORTBASEDPNEN - 802.1X port-based enable error + * Note: + * The API can update the port-based port enable register content. If a port is 802.1x + * port based network access control "enabled", it should be authenticated so packets + * from that port won't be dropped or trapped to CPU. + * The status of 802.1x port-based network access control is as following: + * - DISABLED + * - ENABLED + */ +extern rtk_api_ret_t dal_rtl8367d_dot1x_portBasedEnable_set(rtk_port_t port, rtk_enable_t enable); + +/* Function Name: + * dal_rtl8367d_dot1x_portBasedEnable_get + * Description: + * Get 802.1x port-based enable configuration + * Input: + * port - Port id. + * Output: + * pEnable - The status of 802.1x port. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get the 802.1x port-based port status. + */ +extern rtk_api_ret_t dal_rtl8367d_dot1x_portBasedEnable_get(rtk_port_t port, rtk_enable_t *pEnable); + +/* Function Name: + * dal_rtl8367d_dot1x_portBasedAuthStatus_set + * Description: + * Set 802.1x port-based auth. port configuration + * Input: + * port - Port id. + * port_auth - The status of 802.1x port. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_DOT1X_PORTBASEDAUTH - 802.1X port-based auth error + * Note: + * The authenticated status of 802.1x port-based network access control is as following: + * - UNAUTH + * - AUTH + */ +extern rtk_api_ret_t dal_rtl8367d_dot1x_portBasedAuthStatus_set(rtk_port_t port, rtk_dot1x_auth_status_t port_auth); + +/* Function Name: + * dal_rtl8367d_dot1x_portBasedAuthStatus_get + * Description: + * Get 802.1x port-based auth. port configuration + * Input: + * port - Port id. + * Output: + * pPort_auth - The status of 802.1x port. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get 802.1x port-based port auth.information. + */ +extern rtk_api_ret_t dal_rtl8367d_dot1x_portBasedAuthStatus_get(rtk_port_t port, rtk_dot1x_auth_status_t *pPort_auth); + +/* Function Name: + * dal_rtl8367d_dot1x_portBasedDirection_set + * Description: + * Set 802.1x port-based operational direction configuration + * Input: + * port - Port id. + * port_direction - Operation direction + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_DOT1X_PORTBASEDOPDIR - 802.1X port-based operation direction error + * Note: + * The operate controlled direction of 802.1x port-based network access control is as following: + * - BOTH + * - IN + */ +extern rtk_api_ret_t dal_rtl8367d_dot1x_portBasedDirection_set(rtk_port_t port, rtk_dot1x_direction_t port_direction); + +/* Function Name: + * dal_rtl8367d_dot1x_portBasedDirection_get + * Description: + * Get 802.1X port-based operational direction configuration + * Input: + * port - Port id. + * Output: + * pPort_direction - Operation direction + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get 802.1x port-based operational direction information. + */ +extern rtk_api_ret_t dal_rtl8367d_dot1x_portBasedDirection_get(rtk_port_t port, rtk_dot1x_direction_t *pPort_direction); + + +#endif /* __DAL_RTL8367D_DOT1X_H__ */ + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_eee.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_eee.c new file mode 100644 index 00000000..c30b379b --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_eee.c @@ -0,0 +1,134 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8367C + * Feature : Here is a list of all functions and variables in EEE module. + * + */ + +#include +#include +#include +#include +#include + +#include + +/* Function Name: + * dal_rtl8367d_eee_portEnable_set + * Description: + * Set enable status of EEE function. + * Input: + * port - port id. + * enable - enable EEE status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * This API can set EEE function to the specific port. + * The configuration of the port is as following: + * - DISABLE + * - ENABLE + */ +rtk_api_ret_t dal_rtl8367d_eee_portEnable_set(rtk_port_t port, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check port is UTP port */ + RTK_CHK_PORT_IS_UTP(port); + + if (enable >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if((retVal = dal_rtl8367d_port_phyOCPReg_get(port, 0xA5D0, ®Data)) != RT_ERR_OK) + return retVal; + + if(enable) + { + regData |= (0x0001 << 1); + regData |= (0x0001 << 2); + } + else + { + regData &= ~(0x0001 << 1); + regData &= ~(0x0001 << 2); + } + + if((retVal = dal_rtl8367d_port_phyOCPReg_set(port, 0xA5D0, regData)) != RT_ERR_OK) + return retVal; + + /* Restart Nway */ + if ((retVal = dal_rtl8367d_port_phyReg_get(port, 0, ®Data))!=RT_ERR_OK) + return retVal; + + regData |= 0x0200; + if ((retVal = dal_rtl8367d_port_phyReg_set(port, 0, regData))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_eee_portEnable_get + * Description: + * Get enable status of EEE function + * Input: + * port - Port id. + * Output: + * pEnable - Back pressure status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can get EEE function to the specific port. + * The configuration of the port is as following: + * - DISABLE + * - ENABLE + */ +rtk_api_ret_t dal_rtl8367d_eee_portEnable_get(rtk_port_t port, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check port is UTP port */ + RTK_CHK_PORT_IS_UTP(port); + + if(NULL == pEnable) + return RT_ERR_NULL_POINTER; + + if((retVal = dal_rtl8367d_port_phyOCPReg_get(port, 0xA5D0, ®Data)) != RT_ERR_OK) + return retVal; + + if ((regData & 0x0006) == 0x0006) + *pEnable = ENABLED; + else + *pEnable = DISABLED; + + return RT_ERR_OK; +} + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_eee.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_eee.h new file mode 100644 index 00000000..4df6d894 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_eee.h @@ -0,0 +1,67 @@ +/* + * Copyright (C) 2019 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8367/RTL8367D switch high-level API + * + * Feature : The file includes EEE module high-layer API defination + * + */ + +#ifndef __DAL_RTL8367D_EEE_H__ +#define __DAL_RTL8367D_EEE_H__ + +/* Function Name: + * dal_rtl8367d_eee_portEnable_set + * Description: + * Set enable status of EEE function. + * Input: + * port - port id. + * enable - enable EEE status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * This API can set EEE function to the specific port. + * The configuration of the port is as following: + * - DISABLE + * - ENABLE + */ +extern rtk_api_ret_t dal_rtl8367d_eee_portEnable_set(rtk_port_t port, rtk_enable_t enable); + +/* Function Name: + * dal_rtl8367d_eee_portEnable_get + * Description: + * Get port admin configuration of the specific port. + * Input: + * port - Port id. + * Output: + * pEnable - Back pressure status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can set EEE function to the specific port. + * The configuration of the port is as following: + * - DISABLE + * - ENABLE + */ +extern rtk_api_ret_t dal_rtl8367d_eee_portEnable_get(rtk_port_t port, rtk_enable_t *pEnable); + + +#endif /* __DAL_RTL8367D_EEE_H__ */ + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_gpio.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_gpio.c new file mode 100644 index 00000000..32bb4de6 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_gpio.c @@ -0,0 +1,400 @@ +/* + * Copyright (C) 2019 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8367D + * Feature : Here is a list of all functions and variables in GPIO module. + * + */ + +#include +#include +#include +#include +#include + +/* Function Name: + * dal_rtl8367d_gpio_input_get + * Description: + * Get gpio input + * Input: + * pin - GPIO pin + * Output: + * pInput - GPIO input + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_NULL_POINTER - input parameter is null pointer. + * Note: + * None + */ +rtk_api_ret_t dal_rtl8367d_gpio_input_get(rtk_uint32 pin, rtk_uint32 *pInput) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(pin >= RTL8367D_GPIOPINNO) + return RT_ERR_OUT_OF_RANGE; + + if(NULL == pInput) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_GPIO_67C_I_X0 + (pin / 16), (pin % 16), pInput)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_gpio_output_set + * Description: + * Set GPIO output value. + * Input: + * pin - GPIO pin + * output - 1 or 0 + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_OUT_OF_RANGE - input parameter out of range. + * Note: + * The API can set GPIO pin output 1 or 0. + */ +rtk_api_ret_t dal_rtl8367d_gpio_output_set(rtk_uint32 pin, rtk_uint32 output) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(pin >= RTL8367D_GPIOPINNO) + return RT_ERR_OUT_OF_RANGE; + + if (output > 1) + return RT_ERR_INPUT; + + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_GPIO_67C_O_X0 + (pin / 16), (pin % 16), output)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_gpio_output_get + * Description: + * Get GPIO output. + * Input: + * pin - GPIO pin + * Output: + * pOutput - GPIO output + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_OUT_OF_RANGE - input parameter out of range. + * RT_ERR_NULL_POINTER - input parameter is null pointer. + * Note: + * The API can get GPIO output. + */ +rtk_api_ret_t dal_rtl8367d_gpio_output_get(rtk_uint32 pin, rtk_uint32 *pOutput) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(pin >= RTL8367D_GPIOPINNO) + return RT_ERR_OUT_OF_RANGE; + + if(NULL == pOutput) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_GPIO_67C_O_X0 + (pin / 16), (pin % 16), pOutput)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_gpio_state_set + * Description: + * Set GPIO control. + * Input: + * pin - GPIO pin + * state - GPIO enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_OUT_OF_RANGE - input parameter out of range. + * RT_ERR_ENABLE - invalid enable parameter . + * Note: + * The API can set GPIO pin output 1 or 0. + */ +rtk_api_ret_t dal_rtl8367d_gpio_state_set(rtk_uint32 pin, rtk_enable_t state) +{ + rtk_api_ret_t retVal; + rtk_uint32 gpioState; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(pin >= RTL8367D_GPIOPINNO) + return RT_ERR_OUT_OF_RANGE; + + switch (state) + { + case DISABLED: + gpioState = 0; + break; + case ENABLED: + gpioState = 1; + break; + default: + return RT_ERR_ENABLE; + } + + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_GPIO_MODE_67C_X0 + (pin / 16), (pin % 16), gpioState)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_gpio_state_get + * Description: + * Get GPIO enable state. + * Input: + * pin - GPIO pin + * Output: + * pState - GPIO enable + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_OUT_OF_RANGE - input parameter out of range. + * RT_ERR_NULL_POINTER - input parameter is null pointer. + * Note: + * The API can get GPIO enable state. + */ +rtk_api_ret_t dal_rtl8367d_gpio_state_get(rtk_uint32 pin, rtk_enable_t *pState) +{ + rtk_api_ret_t retVal; + rtk_uint32 gpioState; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(pin >= RTL8367D_GPIOPINNO) + return RT_ERR_OUT_OF_RANGE; + + if(NULL == pState) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_GPIO_MODE_67C_X0 + (pin / 16), (pin % 16), &gpioState)) != RT_ERR_OK) + return retVal; + + switch (gpioState) + { + case 0: + *pState = DISABLED; + break; + case 1: + *pState = ENABLED; + break; + default: + return RT_ERR_FAILED; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_gpio_mode_set + * Description: + * Set GPIO mode. + * Input: + * pin - GPIO pin + * mode - 1 or 0 + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_OUT_OF_RANGE - input parameter out of range. + * Note: + * The API can set GPIO to input or output mode. + */ +rtk_api_ret_t dal_rtl8367d_gpio_mode_set(rtk_uint32 pin, rtk_gpio_mode_t mode) +{ + rtk_api_ret_t retVal; + rtk_uint32 gpioMode; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(pin >= RTL8367D_GPIOPINNO) + return RT_ERR_OUT_OF_RANGE; + + switch (mode) + { + case GPIO_MODE_OUTPUT: + gpioMode = 0; + break; + case GPIO_MODE_INPUT: + gpioMode = 1; + break; + default: + return RT_ERR_INPUT; + } + + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_GPIO_67C_OE_X0 + (pin / 16), (pin % 16), gpioMode)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_gpio_mode_get + * Description: + * Get GPIO mode. + * Input: + * pin - GPIO pin + * Output: + * pMode - GPIO mode + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_OUT_OF_RANGE - input parameter out of range. + * RT_ERR_NULL_POINTER - input parameter is null pointer. + * Note: + * The API can get GPIO mode. + */ +rtk_api_ret_t dal_rtl8367d_gpio_mode_get(rtk_uint32 pin, rtk_gpio_mode_t *pMode) +{ + rtk_api_ret_t retVal; + rtk_uint32 gpioMode; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(pin >= RTL8367D_GPIOPINNO) + return RT_ERR_OUT_OF_RANGE; + + if(NULL == pMode) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_GPIO_67C_OE_X0 + (pin / 16), (pin % 16), &gpioMode)) != RT_ERR_OK) + return retVal; + + switch (gpioMode) + { + case 0: + *pMode = GPIO_MODE_OUTPUT; + break; + case 1: + *pMode = GPIO_MODE_INPUT; + break; + default: + return RT_ERR_FAILED; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_gpio_aclEnClear_set + * Description: + * Set GPIO acl clear. + * Input: + * pin - GPIO pin + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_OUT_OF_RANGE - input parameter out of range. + * Note: + * The API can set GPIO ACL clear. + */ +rtk_api_ret_t dal_rtl8367d_gpio_aclEnClear_set(rtk_uint32 pin) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(pin >= RTL8367D_GPIOPINNO) + return RT_ERR_OUT_OF_RANGE; + + /* ACL clear */ + if((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_ACL_GPIO0 + (pin / 16), (pin % 16), 1)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_gpio_aclEnClear_get + * Description: + * Get GPIO acl clear. + * Input: + * pin - GPIO pin + * Output: + * pAclEn - GPIO acl enable + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_OUT_OF_RANGE - input parameter out of range. + * RT_ERR_NULL_POINTER - input parameter is null pointer. + * Note: + * The API can get GPIO acl enable clear. + */ +rtk_api_ret_t dal_rtl8367d_gpio_aclEnClear_get(rtk_uint32 pin, rtk_enable_t *pAclEn) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(pin >= RTL8367D_GPIOPINNO) + return RT_ERR_OUT_OF_RANGE; + + if(NULL == pAclEn) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_ACL_GPIO0 + (pin / 16), (pin % 16), (rtk_uint32 *)pAclEn)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_gpio.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_gpio.h new file mode 100644 index 00000000..0f647aec --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_gpio.h @@ -0,0 +1,193 @@ + + +#ifndef __DAL_RTL8367D_GPIO_H__ +#define __DAL_RTL8367D_GPIO_H__ + +/* + * Include Files + */ +#include + +#define RTL8367D_GPIOPINNO 62 +#define RTL8367D_GPIOPINMAX (RTL8367D_GPIOPINNO-1) + +/* Function Name: + * dal_rtl8367d_gpio_input_get + * Description: + * Get gpio input + * Input: + * pin - GPIO pin + * Output: + * pInput - GPIO input + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_NULL_POINTER - input parameter is null pointer. + * Note: + * None + */ +extern rtk_api_ret_t dal_rtl8367d_gpio_input_get(rtk_uint32 pin, rtk_uint32 *pInput); + +/* Function Name: + * dal_rtl8367d_gpio_output_set + * Description: + * Set GPIO output value. + * Input: + * pin - GPIO pin + * output - 1 or 0 + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_OUT_OF_RANGE - input parameter out of range. + * Note: + * The API can set GPIO pin output 1 or 0. + */ +extern rtk_api_ret_t dal_rtl8367d_gpio_output_set(rtk_uint32 pin, rtk_uint32 output); + +/* Function Name: + * dal_rtl8367d_gpio_output_get + * Description: + * Get GPIO output. + * Input: + * pin - GPIO pin + * Output: + * pOutput - GPIO output + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_OUT_OF_RANGE - input parameter out of range. + * RT_ERR_NULL_POINTER - input parameter is null pointer. + * Note: + * The API can get GPIO output. + */ +extern rtk_api_ret_t dal_rtl8367d_gpio_output_get(rtk_uint32 pin, rtk_uint32 *pOutput); + +/* Function Name: + * dal_rtl8367d_gpio_state_set + * Description: + * Set GPIO control. + * Input: + * pin - GPIO pin + * state - GPIO enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_OUT_OF_RANGE - input parameter out of range. + * RT_ERR_ENABLE - invalid enable parameter . + * Note: + * The API can set GPIO pin output 1 or 0. + */ +extern rtk_api_ret_t dal_rtl8367d_gpio_state_set(rtk_uint32 pin, rtk_enable_t state); + +/* Function Name: + * dal_rtl8367d_gpio_state_get + * Description: + * Get GPIO enable state. + * Input: + * pin - GPIO pin + * Output: + * pState - GPIO enable + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_OUT_OF_RANGE - input parameter out of range. + * RT_ERR_NULL_POINTER - input parameter is null pointer. + * Note: + * The API can get GPIO enable state. + */ +extern rtk_api_ret_t dal_rtl8367d_gpio_state_get(rtk_uint32 pin, rtk_enable_t *pState); + +/* Function Name: + * dal_rtl8367d_gpio_mode_set + * Description: + * Set GPIO mode. + * Input: + * pin - GPIO pin + * mode - 1 or 0 + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_OUT_OF_RANGE - input parameter out of range. + * Note: + * The API can set GPIO to input or output mode. + */ +extern rtk_api_ret_t dal_rtl8367d_gpio_mode_set(rtk_uint32 pin, rtk_gpio_mode_t mode); + +/* Function Name: + * dal_rtl8367d_gpio_mode_get + * Description: + * Get GPIO mode. + * Input: + * pin - GPIO pin + * Output: + * pMode - GPIO mode + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_OUT_OF_RANGE - input parameter out of range. + * RT_ERR_NULL_POINTER - input parameter is null pointer. + * Note: + * The API can get GPIO mode. + */ +extern rtk_api_ret_t dal_rtl8367d_gpio_mode_get(rtk_uint32 pin, rtk_gpio_mode_t *pMode); + +/* Function Name: + * dal_rtl8367d_gpio_aclEnClear_set + * Description: + * Set GPIO acl clear. + * Input: + * pin - GPIO pin + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_OUT_OF_RANGE - input parameter out of range. + * Note: + * The API can set GPIO ACL clear. + */ +extern rtk_api_ret_t dal_rtl8367d_gpio_aclEnClear_set(rtk_uint32 pin); + +/* Function Name: + * dal_rtl8367d_gpio_aclEnClear_get + * Description: + * Get GPIO acl clear. + * Input: + * pin - GPIO pin + * Output: + * pAclEn - GPIO acl enable + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_OUT_OF_RANGE - input parameter out of range. + * RT_ERR_NULL_POINTER - input parameter is null pointer. + * Note: + * The API can get GPIO acl enable clear. + */ +extern rtk_api_ret_t dal_rtl8367d_gpio_aclEnClear_get(rtk_uint32 pin, rtk_enable_t *pAclEn); + +#endif /* __DAL_RTL8367D_GPIO_H__ */ + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_igmp.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_igmp.c new file mode 100644 index 00000000..0121e72a --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_igmp.c @@ -0,0 +1,300 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8367C + * Feature : Here is a list of all functions and variables in IGMP module. + * + */ + +#include +#include +#include +#include +#include + +#define RTL8367D_PROTOCOL_OP_FLOOD 1 +#define RTL8367D_PROTOCOL_OP_TRAP 2 +#define RTL8367D_PROTOCOL_OP_DROP 3 + +/* Function Name: + * dal_rtl8367d_igmp_protocol_set + * Description: + * set IGMP/MLD protocol action + * Input: + * port - Port ID + * protocol - IGMP/MLD protocol + * action - Per-port and per-protocol IGMP action seeting + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Error parameter + * Note: + * This API set IGMP/MLD protocol action + */ +rtk_api_ret_t dal_rtl8367d_igmp_protocol_set(rtk_port_t port, rtk_igmp_protocol_t protocol, rtk_igmp_action_t action) +{ + rtk_uint32 operation; + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check port valid */ + RTK_CHK_PORT_VALID(port); + + if(protocol >= PROTOCOL_END) + return RT_ERR_INPUT; + + if(action >= IGMP_ACTION_END) + return RT_ERR_INPUT; + + switch(action) + { + case IGMP_ACTION_FORWARD: + operation = RTL8367D_PROTOCOL_OP_FLOOD; + break; + case IGMP_ACTION_TRAP2CPU: + operation = RTL8367D_PROTOCOL_OP_TRAP; + break; + case IGMP_ACTION_DROP: + operation = RTL8367D_PROTOCOL_OP_DROP; + break; + case IGMP_ACTION_ASIC: + default: + return RT_ERR_INPUT; + } + + switch(protocol) + { + case PROTOCOL_IGMPv1: + if ((retVal = rtl8367d_setAsicRegBits((RTL8367D_REG_IGMP_PORT0_CONTROL + rtk_switch_port_L2P_get(port)), RTL8367D_IGMP_PORT0_CONTROL_IGMPV1_OP_MASK, operation))!=RT_ERR_OK) + return retVal; + break; + case PROTOCOL_IGMPv2: + if ((retVal = rtl8367d_setAsicRegBits((RTL8367D_REG_IGMP_PORT0_CONTROL + rtk_switch_port_L2P_get(port)), RTL8367D_IGMP_PORT0_CONTROL_IGMPV2_OP_MASK, operation))!=RT_ERR_OK) + return retVal; + break; + case PROTOCOL_IGMPv3: + if ((retVal = rtl8367d_setAsicRegBits((RTL8367D_REG_IGMP_PORT0_CONTROL + rtk_switch_port_L2P_get(port)), RTL8367D_IGMP_PORT0_CONTROL_IGMPV3_OP_MASK, operation))!=RT_ERR_OK) + return retVal; + break; + case PROTOCOL_MLDv1: + if ((retVal = rtl8367d_setAsicRegBits((RTL8367D_REG_IGMP_PORT0_CONTROL + rtk_switch_port_L2P_get(port)), RTL8367D_IGMP_PORT0_CONTROL_MLDv1_OP_MASK, operation))!=RT_ERR_OK) + return retVal; + break; + case PROTOCOL_MLDv2: + if ((retVal = rtl8367d_setAsicRegBits((RTL8367D_REG_IGMP_PORT0_CONTROL + rtk_switch_port_L2P_get(port)), RTL8367D_IGMP_PORT0_CONTROL_MLDv2_OP_MASK, operation))!=RT_ERR_OK) + return retVal; + break; + default: + return RT_ERR_INPUT; + + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_igmp_protocol_get + * Description: + * set IGMP/MLD protocol action + * Input: + * port - Port ID + * protocol - IGMP/MLD protocol + * action - Per-port and per-protocol IGMP action seeting + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Error parameter + * Note: + * This API set IGMP/MLD protocol action + */ +rtk_api_ret_t dal_rtl8367d_igmp_protocol_get(rtk_port_t port, rtk_igmp_protocol_t protocol, rtk_igmp_action_t *pAction) +{ + rtk_uint32 operation; + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check port valid */ + RTK_CHK_PORT_VALID(port); + + if(protocol >= PROTOCOL_END) + return RT_ERR_INPUT; + + if(pAction == NULL) + return RT_ERR_NULL_POINTER; + + switch(protocol) + { + case PROTOCOL_IGMPv1: + if ((retVal = rtl8367d_getAsicRegBits((RTL8367D_REG_IGMP_PORT0_CONTROL + rtk_switch_port_L2P_get(port)), RTL8367D_IGMP_PORT0_CONTROL_IGMPV1_OP_MASK, &operation))!=RT_ERR_OK) + return retVal; + break; + case PROTOCOL_IGMPv2: + if ((retVal = rtl8367d_getAsicRegBits((RTL8367D_REG_IGMP_PORT0_CONTROL + rtk_switch_port_L2P_get(port)), RTL8367D_IGMP_PORT0_CONTROL_IGMPV2_OP_MASK, &operation))!=RT_ERR_OK) + return retVal; + break; + case PROTOCOL_IGMPv3: + if ((retVal = rtl8367d_getAsicRegBits((RTL8367D_REG_IGMP_PORT0_CONTROL + rtk_switch_port_L2P_get(port)), RTL8367D_IGMP_PORT0_CONTROL_IGMPV3_OP_MASK, &operation))!=RT_ERR_OK) + return retVal; + break; + case PROTOCOL_MLDv1: + if ((retVal = rtl8367d_getAsicRegBits((RTL8367D_REG_IGMP_PORT0_CONTROL + rtk_switch_port_L2P_get(port)), RTL8367D_IGMP_PORT0_CONTROL_MLDv1_OP_MASK, &operation))!=RT_ERR_OK) + return retVal; + break; + case PROTOCOL_MLDv2: + if ((retVal = rtl8367d_getAsicRegBits((RTL8367D_REG_IGMP_PORT0_CONTROL + rtk_switch_port_L2P_get(port)), RTL8367D_IGMP_PORT0_CONTROL_MLDv2_OP_MASK, &operation))!=RT_ERR_OK) + return retVal; + break; + default: + return RT_ERR_INPUT; + + } + + switch(operation) + { + case RTL8367D_PROTOCOL_OP_FLOOD: + *pAction = IGMP_ACTION_FORWARD; + break; + case RTL8367D_PROTOCOL_OP_TRAP: + *pAction = IGMP_ACTION_TRAP2CPU; + break; + case RTL8367D_PROTOCOL_OP_DROP: + *pAction = IGMP_ACTION_DROP; + break; + default: + return RT_ERR_FAILED; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_igmp_bypassGroupRange_set + * Description: + * Set Bypass group + * Input: + * group - bypassed group + * enabled - enabled 1: Bypassed, 0: not bypass + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + * + */ +rtk_api_ret_t dal_rtl8367d_igmp_bypassGroupRange_set(rtk_igmp_bypassGroup_t group, rtk_enable_t enabled) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(group >= IGMP_BYPASS_GROUP_END) + return RT_ERR_INPUT; + + if(enabled >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + switch (group) + { + case IGMP_BYPASS_224_0_0_X: + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_IGMP_MLD_CFG3, RTL8367D_IGMP_MLD_IP4_BYPASS_224_0_0_OFFSET, (rtk_uint32)enabled)) != RT_ERR_OK) + return retVal; + break; + case IGMP_BYPASS_224_0_1_X: + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_IGMP_MLD_CFG3, RTL8367D_IGMP_MLD_IP4_BYPASS_224_0_1_OFFSET, (rtk_uint32)enabled)) != RT_ERR_OK) + return retVal; + break; + case IGMP_BYPASS_239_255_255_X: + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_IGMP_MLD_CFG3, RTL8367D_IGMP_MLD_IP4_BYPASS_239_255_255_OFFSET, (rtk_uint32)enabled)) != RT_ERR_OK) + return retVal; + break; + case IGMP_BYPASS_IPV6_00XX: + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_IGMP_MLD_CFG3, RTL8367D_IGMP_MLD_IP6_BYPASS_OFFSET, (rtk_uint32)enabled)) != RT_ERR_OK) + return retVal; + break; + default: + return RT_ERR_INPUT; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_igmp_bypassGroupRange_get + * Description: + * get Bypass group + * Input: + * group - bypassed group + * Output: + * pEnable - enabled 1: Bypassed, 0: not bypass + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * RT_ERR_NULL_POINTER - Null Pointer + * Note: + * + */ +rtk_api_ret_t dal_rtl8367d_igmp_bypassGroupRange_get(rtk_igmp_bypassGroup_t group, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(group >= IGMP_BYPASS_GROUP_END) + return RT_ERR_INPUT; + + if(NULL == pEnable) + return RT_ERR_NULL_POINTER; + + switch (group) + { + case IGMP_BYPASS_224_0_0_X: + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_IGMP_MLD_CFG3, RTL8367D_IGMP_MLD_IP4_BYPASS_224_0_0_OFFSET, (rtk_uint32 *)pEnable)) != RT_ERR_OK) + return retVal; + break; + case IGMP_BYPASS_224_0_1_X: + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_IGMP_MLD_CFG3, RTL8367D_IGMP_MLD_IP4_BYPASS_224_0_1_OFFSET, (rtk_uint32 *)pEnable)) != RT_ERR_OK) + return retVal; + break; + case IGMP_BYPASS_239_255_255_X: + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_IGMP_MLD_CFG3, RTL8367D_IGMP_MLD_IP4_BYPASS_239_255_255_OFFSET, (rtk_uint32 *)pEnable)) != RT_ERR_OK) + return retVal; + break; + case IGMP_BYPASS_IPV6_00XX: + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_IGMP_MLD_CFG3, RTL8367D_IGMP_MLD_IP6_BYPASS_OFFSET, (rtk_uint32 *)pEnable)) != RT_ERR_OK) + return retVal; + break; + default: + return RT_ERR_INPUT; + } + + return RT_ERR_OK; +} + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_igmp.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_igmp.h new file mode 100644 index 00000000..247da76b --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_igmp.h @@ -0,0 +1,101 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8367/RTL8367D switch high-level API + * + * Feature : The file includes IGMP module high-layer API defination + * + */ + +#ifndef __DAL_RTL8367D_IGMP_H__ +#define __DAL_RTL8367D_IGMP_H__ + +#include + +/* Function Name: + * dal_rtl8367d_igmp_protocol_set + * Description: + * set IGMP/MLD protocol action + * Input: + * port - Port ID + * protocol - IGMP/MLD protocol + * action - Per-port and per-protocol IGMP action seeting + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Error parameter + * Note: + * This API set IGMP/MLD protocol action + */ +extern rtk_api_ret_t dal_rtl8367d_igmp_protocol_set(rtk_port_t port, rtk_igmp_protocol_t protocol, rtk_igmp_action_t action); + +/* Function Name: + * dal_rtl8367d_igmp_protocol_get + * Description: + * set IGMP/MLD protocol action + * Input: + * port - Port ID + * protocol - IGMP/MLD protocol + * action - Per-port and per-protocol IGMP action seeting + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Error parameter + * Note: + * This API set IGMP/MLD protocol action + */ +extern rtk_api_ret_t dal_rtl8367d_igmp_protocol_get(rtk_port_t port, rtk_igmp_protocol_t protocol, rtk_igmp_action_t *pAction); + +/* Function Name: + * dal_rtl8367d_igmp_bypassGroupRange_set + * Description: + * Set Bypass group + * Input: + * group - bypassed group + * enabled - enabled 1: Bypassed, 0: not bypass + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367d_igmp_bypassGroupRange_set(rtk_igmp_bypassGroup_t group, rtk_enable_t enabled); + +/* Function Name: + * dal_rtl8367d_igmp_bypassGroupRange_get + * Description: + * get Bypass group + * Input: + * group - bypassed group + * Output: + * pEnable - enabled 1: Bypassed, 0: not bypass + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * RT_ERR_NULL_POINTER - Null Pointer + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367d_igmp_bypassGroupRange_get(rtk_igmp_bypassGroup_t group, rtk_enable_t *pEnable); + +#endif /* __DAL_RTL8367D_IGMP_H__ */ diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_interrupt.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_interrupt.c new file mode 100644 index 00000000..cc1099d7 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_interrupt.c @@ -0,0 +1,490 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8367D + * Feature : Here is a list of all functions and variables in Interrupt module. + * + */ + +#include +#include +#include +#include + +#include + +/* Function Name: + * dal_rtl8367d_int_polarity_set + * Description: + * Set interrupt polarity configuration. + * Input: + * type - Interruptpolarity type. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can set interrupt polarity configuration. + */ +rtk_api_ret_t dal_rtl8367d_int_polarity_set(rtk_int_polarity_t type) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(type >= INT_POLAR_END) + return RT_ERR_INPUT; + + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_INTR_CTRL, RTL8367D_INTR_POLARITY_OFFSET, type)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_int_polarity_get + * Description: + * Get interrupt polarity configuration. + * Input: + * None + * Output: + * pType - Interruptpolarity type. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can get interrupt polarity configuration. + */ +rtk_api_ret_t dal_rtl8367d_int_polarity_get(rtk_int_polarity_t *pType) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pType) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_INTR_CTRL, RTL8367D_INTR_POLARITY_OFFSET, pType)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_int_control_set + * Description: + * Set interrupt trigger status configuration. + * Input: + * type - Interrupt type. + * enable - Interrupt status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * The API can set interrupt status configuration. + * The interrupt trigger status is shown in the following: + * - INT_TYPE_LINK_STATUS + * - INT_TYPE_METER_EXCEED + * - INT_TYPE_LEARN_LIMIT + * - INT_TYPE_LINK_SPEED + * - INT_TYPE_CONGEST + * - INT_TYPE_GREEN_FEATURE + * - INT_TYPE_LOOP_DETECT + * - INT_TYPE_8051, + * - INT_TYPE_CABLE_DIAG, + * - INT_TYPE_ACL, + * - INT_TYPE_SLIENT + + */ +rtk_api_ret_t dal_rtl8367d_int_control_set(rtk_int_type_t type, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + rtk_uint32 mask; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (type >= INT_TYPE_END) + return RT_ERR_INPUT; + + if (type == INT_TYPE_RESERVED) + return RT_ERR_INPUT; + + if ((retVal = rtl8367d_getAsicReg(RTL8367D_REG_INTR_IMR, &mask)) != RT_ERR_OK) + return retVal; + + if (ENABLED == enable) + mask = mask | (1<value[0] & (0x0001 << INT_TYPE_RESERVED)) + return RT_ERR_INPUT; + + if(pStatusMask->value[0] >= (0x0001 << INT_TYPE_END)) + return RT_ERR_INPUT; + + if ((retVal = rtl8367d_setAsicReg(RTL8367D_REG_INTR_IMS, (rtk_uint32)pStatusMask->value[0]))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_int_status_get + * Description: + * Get interrupt trigger status. + * Input: + * None + * Output: + * pStatusMask - Interrupt status bit mask. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get interrupt trigger status when interrupt happened. + * The interrupt trigger status is shown in the following: + * - INT_TYPE_LINK_STATUS (value[0] (Bit0)) + * - INT_TYPE_METER_EXCEED (value[0] (Bit1)) + * - INT_TYPE_LEARN_LIMIT (value[0] (Bit2)) + * - INT_TYPE_LINK_SPEED (value[0] (Bit3)) + * - INT_TYPE_CONGEST (value[0] (Bit4)) + * - INT_TYPE_GREEN_FEATURE (value[0] (Bit5)) + * - INT_TYPE_LOOP_DETECT (value[0] (Bit6)) + * - INT_TYPE_8051 (value[0] (Bit7)) + * - INT_TYPE_CABLE_DIAG (value[0] (Bit8)) + * - INT_TYPE_ACL (value[0] (Bit9)) + * - INT_TYPE_SLIENT (value[0] (Bit11)) + + * + */ +rtk_api_ret_t dal_rtl8367d_int_status_get(rtk_int_status_t* pStatusMask) +{ + rtk_api_ret_t retVal; + rtk_uint32 ims_mask; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pStatusMask) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367d_getAsicReg(RTL8367D_REG_INTR_IMS, &ims_mask)) != RT_ERR_OK) + return retVal; + + pStatusMask->value[0] = (ims_mask & 0x00000FFF); + return RT_ERR_OK; +} + +#define ADV_NOT_SUPPORT (0xFFFF) +static rtk_api_ret_t _rtk_int_Advidx_get(rtk_int_advType_t adv_type, rtk_uint32 *pAsic_idx) +{ + rtk_uint32 asic_idx[ADV_END] = + { + RTL8367D_INTRST_L2_LEARN, + RTL8367D_INTRST_SPEED_CHANGE, + RTL8367D_INTRST_SPECIAL_CONGESTION, + RTL8367D_INTRST_PORT_LINKDOWN, + RTL8367D_INTRST_PORT_LINKUP, + ADV_NOT_SUPPORT, + RTL8367D_INTRST_RLDP_LOOPED, + RTL8367D_INTRST_RLDP_RELEASED, + }; + + if(adv_type >= ADV_END) + return RT_ERR_INPUT; + + if(asic_idx[adv_type] == ADV_NOT_SUPPORT) + return RT_ERR_CHIP_NOT_SUPPORTED; + + *pAsic_idx = asic_idx[adv_type]; + return RT_ERR_OK; +} + +static rtk_api_ret_t _rtl8367d_getInterruptRelatedStatus(rtk_uint32 type, rtk_uint32* pStatus) +{ + CONST rtk_uint32 indicatorAddress[RTL8367D_INTRST_END] = {RTL8367D_REG_LEARN_OVER_INDICATOR, + RTL8367D_REG_SPEED_CHANGE_INDICATOR, + RTL8367D_REG_SPECIAL_CONGEST_INDICATOR, + RTL8367D_REG_PORT_LINKDOWN_INDICATOR, + RTL8367D_REG_PORT_LINKUP_INDICATOR, + RTL8367D_REG_METER_OVERRATE_INDICATOR0, + RTL8367D_REG_METER_OVERRATE_INDICATOR1, + RTL8367D_REG_METER_OVERRATE_INDICATOR2, + RTL8367D_REG_RLDP_LOOPED_INDICATOR, + RTL8367D_REG_RLDP_RELEASED_INDICATOR, + RTL8367D_REG_SYSTEM_LEARN_OVER_INDICATOR}; + + if(type >= RTL8367D_INTRST_END ) + return RT_ERR_OUT_OF_RANGE; + + return rtl8367d_getAsicReg(indicatorAddress[type], pStatus); +} + +static rtk_api_ret_t _rtl8367d_setInterruptRelatedStatus(rtk_uint32 type, rtk_uint32 status) +{ + CONST rtk_uint32 indicatorAddress[RTL8367D_INTRST_END] = {RTL8367D_REG_LEARN_OVER_INDICATOR, + RTL8367D_REG_SPEED_CHANGE_INDICATOR, + RTL8367D_REG_SPECIAL_CONGEST_INDICATOR, + RTL8367D_REG_PORT_LINKDOWN_INDICATOR, + RTL8367D_REG_PORT_LINKUP_INDICATOR, + RTL8367D_REG_METER_OVERRATE_INDICATOR0, + RTL8367D_REG_METER_OVERRATE_INDICATOR1, + RTL8367D_REG_METER_OVERRATE_INDICATOR2, + RTL8367D_REG_RLDP_LOOPED_INDICATOR, + RTL8367D_REG_RLDP_RELEASED_INDICATOR, + RTL8367D_REG_SYSTEM_LEARN_OVER_INDICATOR}; + + if(type >= RTL8367D_INTRST_END ) + return RT_ERR_OUT_OF_RANGE; + + return rtl8367d_setAsicReg(indicatorAddress[type], status); +} + + +/* Function Name: + * dal_rtl8367d_int_advanceInfo_get + * Description: + * Get interrupt advanced information. + * Input: + * adv_type - Advanced interrupt type. + * Output: + * info - Information per type. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can get advanced information when interrupt happened. + * The status will be cleared after execute this API. + */ +rtk_api_ret_t dal_rtl8367d_int_advanceInfo_get(rtk_int_advType_t adv_type, rtk_int_info_t *pInfo) +{ + rtk_api_ret_t retVal; + rtk_uint32 data; + rtk_uint32 intAdvType = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(adv_type >= ADV_END) + return RT_ERR_INPUT; + + if(NULL == pInfo) + return RT_ERR_NULL_POINTER; + + if(adv_type != ADV_METER_EXCEED_MASK) + { + if((retVal = _rtk_int_Advidx_get(adv_type, &intAdvType)) != RT_ERR_OK) + return retVal; + } + + switch(adv_type) + { + case ADV_L2_LEARN_PORT_MASK: + /* Get physical portmask */ + if((retVal = _rtl8367d_getInterruptRelatedStatus(intAdvType, &data)) != RT_ERR_OK) + return retVal; + + /* Clear Advanced Info */ + if((retVal = _rtl8367d_setInterruptRelatedStatus(intAdvType, 0xFFFF)) != RT_ERR_OK) + return retVal; + + /* Translate to logical portmask */ + if((retVal = rtk_switch_portmask_P2L_get(data, &(pInfo->portMask))) != RT_ERR_OK) + return retVal; + + /* Get system learn */ + if((retVal = _rtl8367d_getInterruptRelatedStatus(RTL8367D_INTRST_SYS_LEARN, &data)) != RT_ERR_OK) + return retVal; + + /* Clear system learn */ + if((retVal = _rtl8367d_setInterruptRelatedStatus(RTL8367D_INTRST_SYS_LEARN, 0x0001)) != RT_ERR_OK) + return retVal; + + pInfo->systemLearnOver = data; + break; + case ADV_SPEED_CHANGE_PORT_MASK: + case ADV_SPECIAL_CONGESTION_PORT_MASK: + case ADV_PORT_LINKDOWN_PORT_MASK: + case ADV_PORT_LINKUP_PORT_MASK: + case ADV_RLDP_LOOPED: + case ADV_RLDP_RELEASED: + /* Get physical portmask */ + if((retVal = _rtl8367d_getInterruptRelatedStatus(intAdvType, &data)) != RT_ERR_OK) + return retVal; + + /* Clear Advanced Info */ + if((retVal = _rtl8367d_setInterruptRelatedStatus(intAdvType, 0xFFFF)) != RT_ERR_OK) + return retVal; + + /* Translate to logical portmask */ + if((retVal = rtk_switch_portmask_P2L_get(data, &(pInfo->portMask))) != RT_ERR_OK) + return retVal; + + break; + case ADV_METER_EXCEED_MASK: + /* Get Meter Mask */ + if((retVal = _rtl8367d_getInterruptRelatedStatus(RTL8367D_INTRST_METER0_15, &data)) != RT_ERR_OK) + return retVal; + + /* Clear Advanced Info */ + if((retVal = _rtl8367d_setInterruptRelatedStatus(RTL8367D_INTRST_METER0_15, 0xFFFF)) != RT_ERR_OK) + return retVal; + + pInfo->meterMask[0] = data & 0xFFFF; + + /* Get Meter Mask */ + if((retVal = _rtl8367d_getInterruptRelatedStatus(RTL8367D_INTRST_METER16_31, &data)) != RT_ERR_OK) + return retVal; + + /* Clear Advanced Info */ + if((retVal = _rtl8367d_setInterruptRelatedStatus(RTL8367D_INTRST_METER16_31, 0xFFFF)) != RT_ERR_OK) + return retVal; + + pInfo->meterMask[0] = pInfo->meterMask[0] | ((data << 16) & 0xFFFF0000); + + /* Get Meter Mask */ + if((retVal = _rtl8367d_getInterruptRelatedStatus(RTL8367D_INTRST_METER32_39, &data)) != RT_ERR_OK) + return retVal; + + /* Clear Advanced Info */ + if((retVal = _rtl8367d_setInterruptRelatedStatus(RTL8367D_INTRST_METER32_39, 0xFFFF)) != RT_ERR_OK) + return retVal; + + pInfo->meterMask[1] = data & 0x00FF; + + break; + default: + return RT_ERR_INPUT; + } + + return RT_ERR_OK; +} + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_interrupt.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_interrupt.h new file mode 100644 index 00000000..a890d883 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_interrupt.h @@ -0,0 +1,220 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8367/RTL8367D switch high-level API + * + * Feature : The file includes Interrupt module high-layer API defination + * + */ + +#ifndef __DAL_RTL8367D_INTERRUPT_H__ +#define __DAL_RTL8367D_INTERRUPT_H__ + +#include + +#define RTL8367D_INTRST_L2_LEARN 0 +#define RTL8367D_INTRST_SPEED_CHANGE 1 +#define RTL8367D_INTRST_SPECIAL_CONGESTION 2 +#define RTL8367D_INTRST_PORT_LINKDOWN 3 +#define RTL8367D_INTRST_PORT_LINKUP 4 +#define RTL8367D_INTRST_METER0_15 5 +#define RTL8367D_INTRST_METER16_31 6 +#define RTL8367D_INTRST_METER32_39 7 +#define RTL8367D_INTRST_RLDP_LOOPED 8 +#define RTL8367D_INTRST_RLDP_RELEASED 9 +#define RTL8367D_INTRST_SYS_LEARN 10 +#define RTL8367D_INTRST_END 11 + + +/* Function Name: + * dal_rtl8367d_int_polarity_set + * Description: + * Set interrupt polarity configuration. + * Input: + * type - Interruptpolarity type. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can set interrupt polarity configuration. + */ +extern rtk_api_ret_t dal_rtl8367d_int_polarity_set(rtk_int_polarity_t type); + +/* Function Name: + * dal_rtl8367d_int_polarity_get + * Description: + * Get interrupt polarity configuration. + * Input: + * None + * Output: + * pType - Interruptpolarity type. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can get interrupt polarity configuration. + */ +extern rtk_api_ret_t dal_rtl8367d_int_polarity_get(rtk_int_polarity_t *pType); + +/* Function Name: + * dal_rtl8367d_int_control_set + * Description: + * Set interrupt trigger status configuration. + * Input: + * type - Interrupt type. + * enable - Interrupt status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * The API can set interrupt status configuration. + * The interrupt trigger status is shown in the following: + * - INT_TYPE_LINK_STATUS + * - INT_TYPE_METER_EXCEED + * - INT_TYPE_LEARN_LIMIT + * - INT_TYPE_LINK_SPEED + * - INT_TYPE_CONGEST + * - INT_TYPE_GREEN_FEATURE + * - INT_TYPE_LOOP_DETECT + * - INT_TYPE_8051, + * - INT_TYPE_CABLE_DIAG, + * - INT_TYPE_ACL, + * - INT_TYPE_SLIENT + + */ +extern rtk_api_ret_t dal_rtl8367d_int_control_set(rtk_int_type_t type, rtk_enable_t enable); + +/* Function Name: + * dal_rtl8367d_int_control_get + * Description: + * Get interrupt trigger status configuration. + * Input: + * type - Interrupt type. + * Output: + * pEnable - Interrupt status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get interrupt status configuration. + * The interrupt trigger status is shown in the following: + * - INT_TYPE_LINK_STATUS + * - INT_TYPE_METER_EXCEED + * - INT_TYPE_LEARN_LIMIT + * - INT_TYPE_LINK_SPEED + * - INT_TYPE_CONGEST + * - INT_TYPE_GREEN_FEATURE + * - INT_TYPE_LOOP_DETECT + * - INT_TYPE_8051, + * - INT_TYPE_CABLE_DIAG, + * - INT_TYPE_ACL, + * - INT_TYPE_SLIENT + + */ +extern rtk_api_ret_t dal_rtl8367d_int_control_get(rtk_int_type_t type, rtk_enable_t* pEnable); + +/* Function Name: + * dal_rtl8367d_int_status_set + * Description: + * Set interrupt trigger status to clean. + * Input: + * None + * Output: + * pStatusMask - Interrupt status bit mask. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can clean interrupt trigger status when interrupt happened. + * The interrupt trigger status is shown in the following: + * - INT_TYPE_LINK_STATUS (value[0] (Bit0)) + * - INT_TYPE_METER_EXCEED (value[0] (Bit1)) + * - INT_TYPE_LEARN_LIMIT (value[0] (Bit2)) + * - INT_TYPE_LINK_SPEED (value[0] (Bit3)) + * - INT_TYPE_CONGEST (value[0] (Bit4)) + * - INT_TYPE_GREEN_FEATURE (value[0] (Bit5)) + * - INT_TYPE_LOOP_DETECT (value[0] (Bit6)) + * - INT_TYPE_8051 (value[0] (Bit7)) + * - INT_TYPE_CABLE_DIAG (value[0] (Bit8)) + * - INT_TYPE_ACL (value[0] (Bit9)) + * - INT_TYPE_SLIENT (value[0] (Bit11)) + + * The status will be cleared after execute this API. + */ +extern rtk_api_ret_t dal_rtl8367d_int_status_set(rtk_int_status_t *pStatusMask); + +/* Function Name: + * dal_rtl8367d_int_status_get + * Description: + * Get interrupt trigger status. + * Input: + * None + * Output: + * pStatusMask - Interrupt status bit mask. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get interrupt trigger status when interrupt happened. + * The interrupt trigger status is shown in the following: + * - INT_TYPE_LINK_STATUS (value[0] (Bit0)) + * - INT_TYPE_METER_EXCEED (value[0] (Bit1)) + * - INT_TYPE_LEARN_LIMIT (value[0] (Bit2)) + * - INT_TYPE_LINK_SPEED (value[0] (Bit3)) + * - INT_TYPE_CONGEST (value[0] (Bit4)) + * - INT_TYPE_GREEN_FEATURE (value[0] (Bit5)) + * - INT_TYPE_LOOP_DETECT (value[0] (Bit6)) + * - INT_TYPE_8051 (value[0] (Bit7)) + * - INT_TYPE_CABLE_DIAG (value[0] (Bit8)) + * - INT_TYPE_ACL (value[0] (Bit9)) + * - INT_TYPE_SLIENT (value[0] (Bit11)) + + * + */ +extern rtk_api_ret_t dal_rtl8367d_int_status_get(rtk_int_status_t* pStatusMask); + +/* Function Name: + * dal_rtl8367d_int_advanceInfo_get + * Description: + * Get interrupt advanced information. + * Input: + * adv_type - Advanced interrupt type. + * Output: + * info - Information per type. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can get advanced information when interrupt happened. + * The status will be cleared after execute this API. + */ +extern rtk_api_ret_t dal_rtl8367d_int_advanceInfo_get(rtk_int_advType_t adv_type, rtk_int_info_t* info); + + +#endif /* __DAL_RTL8367D_INTERRUPT_H__ */ diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_l2.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_l2.c new file mode 100644 index 00000000..2cc6fc20 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_l2.c @@ -0,0 +1,2950 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8367D + * Feature : Here is a list of all functions and variables in L2 module. + * + */ + +#include +#include +#include +#include + +#include + +static void _rtl8367d_fdbStUser2Smi( rtl8367d_luttb *pLutSt, rtk_uint16 *pFdbSmi) +{ + /* L3 lookup */ + if(pLutSt->l3lookup) + { + pFdbSmi[0] = (pLutSt->sip & 0x0000FFFF); + + pFdbSmi[1] = (pLutSt->sip & 0xFFFF0000) >> 16; + + pFdbSmi[2] = (pLutSt->dip & 0x0000FFFF); + + pFdbSmi[3] = (pLutSt->dip & 0x0FFF0000) >> 16; + pFdbSmi[3] |= (pLutSt->l3lookup & 0x0001) << 12; + pFdbSmi[3] |= (pLutSt->mbr & 0x0003) << 14; + + pFdbSmi[4] |= (pLutSt->mbr & 0x00FC) >> 2; + pFdbSmi[4] |= (pLutSt->nosalearn & 0x0001) << 6; + } + else if(pLutSt->mac.octet[0] & 0x01) /*Multicast L2 Lookup*/ + { + pFdbSmi[0] |= pLutSt->mac.octet[5]; + pFdbSmi[0] |= pLutSt->mac.octet[4] << 8; + + pFdbSmi[1] |= pLutSt->mac.octet[3]; + pFdbSmi[1] |= pLutSt->mac.octet[2] << 8; + + pFdbSmi[2] |= pLutSt->mac.octet[1]; + pFdbSmi[2] |= pLutSt->mac.octet[0] << 8; + + pFdbSmi[3] |= pLutSt->cvid_fid; + pFdbSmi[3] |= (pLutSt->l3lookup & 0x0001) << 12; + pFdbSmi[3] |= (pLutSt->ivl_svl & 0x0001) << 13; + pFdbSmi[3] |= (pLutSt->mbr & 0x0003) << 14; + + pFdbSmi[4] |= (pLutSt->mbr & 0x00FC) >> 2; + pFdbSmi[4] |= (pLutSt->nosalearn & 0x0001) << 6; + } + else /*Asic auto-learning*/ + { + pFdbSmi[0] |= pLutSt->mac.octet[5]; + pFdbSmi[0] |= pLutSt->mac.octet[4] << 8; + + pFdbSmi[1] |= pLutSt->mac.octet[3]; + pFdbSmi[1] |= pLutSt->mac.octet[2] << 8; + + pFdbSmi[2] |= pLutSt->mac.octet[1]; + pFdbSmi[2] |= pLutSt->mac.octet[0] << 8; + + pFdbSmi[3] |= pLutSt->cvid_fid; + pFdbSmi[3] |= (pLutSt->l3lookup & 0x0001) << 12; + pFdbSmi[3] |= (pLutSt->ivl_svl & 0x0001) << 13; + pFdbSmi[3] |= (pLutSt->spa & 0x0003) << 14; + + pFdbSmi[4] |= (pLutSt->spa & 0x0004) >> 2; + pFdbSmi[4] |= (pLutSt->age & 0x0007) << 1; + pFdbSmi[4] |= (pLutSt->nosalearn & 0x0001) << 6; + } +} + + +static void _rtl8367d_fdbStSmi2User( rtl8367d_luttb *pLutSt, rtk_uint16 *pFdbSmi) +{ + /*L3 lookup*/ + if(pFdbSmi[3] & 0x1000) + { + pLutSt->sip = pFdbSmi[0] | (pFdbSmi[1] << 16); + pLutSt->dip = 0xE0000000 | pFdbSmi[2] | ((pFdbSmi[3] & 0x0FFF) << 16); + pLutSt->mbr = ((pFdbSmi[4] & 0x003F) << 2) | ((pFdbSmi[3] & 0xC000) >> 14); + pLutSt->l3lookup = (pFdbSmi[3] & 0x1000) >> 12; + pLutSt->nosalearn = (pFdbSmi[4] & 0x0040) >> 6; + } + else if(pFdbSmi[2] & 0x0100) /*Multicast L2 Lookup*/ + { + pLutSt->mac.octet[0] = (pFdbSmi[2] & 0xFF00) >> 8; + pLutSt->mac.octet[1] = (pFdbSmi[2] & 0x00FF); + pLutSt->mac.octet[2] = (pFdbSmi[1] & 0xFF00) >> 8; + pLutSt->mac.octet[3] = (pFdbSmi[1] & 0x00FF); + pLutSt->mac.octet[4] = (pFdbSmi[0] & 0xFF00) >> 8; + pLutSt->mac.octet[5] = (pFdbSmi[0] & 0x00FF); + + pLutSt->cvid_fid = pFdbSmi[3] & 0x0FFF; + pLutSt->mbr = ((pFdbSmi[4] & 0x003F) << 2) | ((pFdbSmi[3] & 0xC000) >> 14); + + pLutSt->l3lookup = (pFdbSmi[3] & 0x1000) >> 12; + pLutSt->ivl_svl = (pFdbSmi[3] & 0x2000) >> 13; + pLutSt->nosalearn = (pFdbSmi[4] & 0x0040) >> 6; + } + else /*Asic auto-learning*/ + { + pLutSt->mac.octet[0] = (pFdbSmi[2] & 0xFF00) >> 8; + pLutSt->mac.octet[1] = (pFdbSmi[2] & 0x00FF); + pLutSt->mac.octet[2] = (pFdbSmi[1] & 0xFF00) >> 8; + pLutSt->mac.octet[3] = (pFdbSmi[1] & 0x00FF); + pLutSt->mac.octet[4] = (pFdbSmi[0] & 0xFF00) >> 8; + pLutSt->mac.octet[5] = (pFdbSmi[0] & 0x00FF); + + pLutSt->cvid_fid = pFdbSmi[3] & 0x0FFF; + + pLutSt->spa = ((pFdbSmi[4] & 0x0001) << 2) | ((pFdbSmi[3] & 0xC000) >> 14); + pLutSt->age = (pFdbSmi[4] & 0x000E) >> 1; + + pLutSt->l3lookup = (pFdbSmi[3] & 0x1000) >> 12; + pLutSt->ivl_svl = (pFdbSmi[3] & 0x2000) >> 13; + pLutSt->nosalearn = (pFdbSmi[4] & 0x0040) >> 6; + } +} + + +static rtk_api_ret_t _rtl8367d_getL2LookupTb(rtk_uint32 method, rtl8367d_luttb *pL2Table) +{ + ret_t retVal; + rtk_uint32 regData; + rtk_uint16* accessPtr; + rtk_uint32 i; + rtk_uint16 smil2Table[RTL8367D_LUT_TABLE_SIZE]; + rtk_uint32 busyCounter; + rtk_uint32 tblCmd; + + if(pL2Table->wait_time == 0) + busyCounter = RTL8367D_LUT_BUSY_CHECK_NO; + else + busyCounter = pL2Table->wait_time; + + while(busyCounter) + { + retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_TABLE_LUT_ADDR, RTL8367D_TABLE_LUT_ADDR_BUSY_FLAG_OFFSET,®Data); + if(retVal != RT_ERR_OK) + return retVal; + + pL2Table->lookup_busy = regData; + if(!pL2Table->lookup_busy) + break; + + busyCounter --; + if(busyCounter == 0) + return RT_ERR_BUSYWAIT_TIMEOUT; + } + + + tblCmd = (method << RTL8367D_ACCESS_METHOD_OFFSET) & RTL8367D_ACCESS_METHOD_MASK; + + switch(method) + { + case RTL8367D_LUTREADMETHOD_ADDRESS: + case RTL8367D_LUTREADMETHOD_NEXT_ADDRESS: + case RTL8367D_LUTREADMETHOD_NEXT_L2UC: + case RTL8367D_LUTREADMETHOD_NEXT_L2MC: + case RTL8367D_LUTREADMETHOD_NEXT_L3MC: + case RTL8367D_LUTREADMETHOD_NEXT_L2L3MC: + retVal = rtl8367d_setAsicReg(RTL8367D_REG_TABLE_ACCESS_ADDR, pL2Table->address); + if(retVal != RT_ERR_OK) + return retVal; + break; + case RTL8367D_LUTREADMETHOD_MAC: + memset(smil2Table, 0x00, sizeof(rtk_uint16) * RTL8367D_LUT_TABLE_SIZE); + _rtl8367d_fdbStUser2Smi(pL2Table, smil2Table); + + accessPtr = smil2Table; + regData = *accessPtr; + for(i=0; iaddress); + if(retVal != RT_ERR_OK) + return retVal; + + tblCmd = tblCmd | ((pL2Table->spa << RTL8367D_TABLE_ACCESS_CTRL_SPA_OFFSET) & RTL8367D_TABLE_ACCESS_CTRL_SPA_MASK); + + break; + default: + return RT_ERR_INPUT; + } + + tblCmd = tblCmd | ((RTL8367D_TABLE_ACCESS_REG_DATA(RTL8367D_TB_OP_READ,RTL8367D_TB_TARGET_L2)) & (RTL8367D_TABLE_TYPE_MASK | RTL8367D_COMMAND_TYPE_MASK)); + /* Read Command */ + retVal = rtl8367d_setAsicReg(RTL8367D_REG_TABLE_ACCESS_CTRL, tblCmd); + if(retVal != RT_ERR_OK) + return retVal; + + if(pL2Table->wait_time == 0) + busyCounter = RTL8367D_LUT_BUSY_CHECK_NO; + else + busyCounter = pL2Table->wait_time; + + while(busyCounter) + { + retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_TABLE_LUT_ADDR, RTL8367D_TABLE_LUT_ADDR_BUSY_FLAG_OFFSET,®Data); + if(retVal != RT_ERR_OK) + return retVal; + + pL2Table->lookup_busy = regData; + if(!pL2Table->lookup_busy) + break; + + busyCounter --; + if(busyCounter == 0) + return RT_ERR_BUSYWAIT_TIMEOUT; + } + + retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_TABLE_LUT_ADDR, RTL8367D_HIT_STATUS_OFFSET,®Data); + if(retVal != RT_ERR_OK) + return retVal; + pL2Table->lookup_hit = regData; + if(!pL2Table->lookup_hit) + return RT_ERR_L2_ENTRY_NOTFOUND; + + /*Read access address*/ + retVal = rtl8367d_getAsicReg(RTL8367D_REG_TABLE_LUT_ADDR, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + pL2Table->address = (regData & 0xfff); + + /*read L2 entry */ + memset(smil2Table, 0x00, sizeof(rtk_uint16) * RTL8367D_LUT_TABLE_SIZE); + + accessPtr = smil2Table; + + for(i = 0; i < RTL8367D_LUT_TABLE_SIZE; i++) + { + retVal = rtl8367d_getAsicReg(RTL8367D_REG_TABLE_READ_DATA0 + i, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + *accessPtr = regData; + + accessPtr ++; + } + + _rtl8367d_fdbStSmi2User(pL2Table, smil2Table); + + return RT_ERR_OK; +} + +static rtk_api_ret_t _rtl8367d_setL2LookupTb(rtl8367d_luttb *pL2Table) +{ + ret_t retVal; + rtk_uint32 regData; + rtk_uint16 *accessPtr; + rtk_uint32 i; + rtk_uint16 smil2Table[RTL8367D_LUT_TABLE_SIZE]; + rtk_uint32 tblCmd; + rtk_uint32 busyCounter; + + memset(smil2Table, 0x00, sizeof(rtk_uint16) * RTL8367D_LUT_TABLE_SIZE); + _rtl8367d_fdbStUser2Smi(pL2Table, smil2Table); + + if(pL2Table->wait_time == 0) + busyCounter = RTL8367D_LUT_BUSY_CHECK_NO; + else + busyCounter = pL2Table->wait_time; + + while(busyCounter) + { + retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_TABLE_LUT_ADDR, RTL8367D_TABLE_LUT_ADDR_BUSY_FLAG_OFFSET,®Data); + if(retVal != RT_ERR_OK) + return retVal; + + pL2Table->lookup_busy = regData; + if(!regData) + break; + + busyCounter --; + if(busyCounter == 0) + return RT_ERR_BUSYWAIT_TIMEOUT; + } + + accessPtr = smil2Table; + + for(i = 0; i < RTL8367D_LUT_TABLE_SIZE; i++) + { + regData = *(accessPtr + i); + retVal = rtl8367d_setAsicReg(RTL8367D_REG_TABLE_WRITE_DATA0 + i, regData); + if(retVal != RT_ERR_OK) + return retVal; + } + + tblCmd = (RTL8367D_TABLE_ACCESS_REG_DATA(RTL8367D_TB_OP_WRITE,RTL8367D_TB_TARGET_L2)) & (RTL8367D_TABLE_TYPE_MASK | RTL8367D_COMMAND_TYPE_MASK); + /* Write Command */ + retVal = rtl8367d_setAsicReg(RTL8367D_REG_TABLE_ACCESS_CTRL, tblCmd); + if(retVal != RT_ERR_OK) + return retVal; + + if(pL2Table->wait_time == 0) + busyCounter = RTL8367D_LUT_BUSY_CHECK_NO; + else + busyCounter = pL2Table->wait_time; + + while(busyCounter) + { + retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_TABLE_LUT_ADDR, RTL8367D_TABLE_LUT_ADDR_BUSY_FLAG_OFFSET,®Data); + if(retVal != RT_ERR_OK) + return retVal; + + pL2Table->lookup_busy = regData; + if(!regData) + break; + + busyCounter --; + if(busyCounter == 0) + return RT_ERR_BUSYWAIT_TIMEOUT; + } + + /*Read access status*/ + retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_TABLE_LUT_ADDR, RTL8367D_HIT_STATUS_OFFSET, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + pL2Table->lookup_hit = regData; + if(!pL2Table->lookup_hit) + return RT_ERR_FAILED; + + /*Read access address*/ + retVal = rtl8367d_getAsicReg(RTL8367D_REG_TABLE_LUT_ADDR, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + pL2Table->address = (regData & 0xfff); + pL2Table->lookup_busy = 0; + + return RT_ERR_OK; +} + +static rtk_api_ret_t _rtl8367d_getLutIPMCGroup(rtk_uint32 index, ipaddr_t *pGroup_addr, rtk_uint32 *pPmask, rtk_uint32 *pValid) +{ + rtk_uint32 regAddr, regData, bitoffset; + ipaddr_t ipData; + ret_t retVal; + + if(index > RTL8367D_LUT_IPMCGRP_TABLE_MAX) + return RT_ERR_INPUT; + + if (NULL == pGroup_addr) + return RT_ERR_NULL_POINTER; + + if (NULL == pPmask) + return RT_ERR_NULL_POINTER; + + /* Group address */ + regAddr = RTL8367D_REG_IPMC_GROUP_ENTRY0_H + (index * 2); + if( (retVal = rtl8367d_getAsicReg(regAddr, ®Data)) != RT_ERR_OK) + return retVal; + + *pGroup_addr = (((regData & 0x00000FFF) << 16) | 0xE0000000); + + regAddr++; + if( (retVal = rtl8367d_getAsicReg(regAddr, ®Data)) != RT_ERR_OK) + return retVal; + + ipData = (*pGroup_addr | (regData & 0x0000FFFF)); + *pGroup_addr = ipData; + + /* portmask */ + regAddr = RTL8367D_REG_IPMC_GROUP_PMSK_00 + index; + if( (retVal = rtl8367d_getAsicReg(regAddr, ®Data)) != RT_ERR_OK) + return retVal; + + *pPmask = regData; + + /* valid */ + regAddr = RTL8367D_REG_IPMC_GROUP_VALID_15_0 + (index / 16); + bitoffset = index % 16; + if( (retVal = rtl8367d_getAsicRegBit(regAddr, bitoffset, ®Data)) != RT_ERR_OK) + return retVal; + + *pValid = regData; + + return RT_ERR_OK; +} + +static rtk_api_ret_t _rtl8367d_setLutIPMCGroup(rtk_uint32 index, ipaddr_t group_addr, rtk_uint32 pmask, rtk_uint32 valid) +{ + rtk_uint32 regAddr, regData, bitoffset; + ipaddr_t ipData; + ret_t retVal; + + if(index > RTL8367D_LUT_IPMCGRP_TABLE_MAX) + return RT_ERR_INPUT; + + ipData = group_addr; + + if( (ipData & 0xF0000000) != 0xE0000000) /* not in 224.0.0.0 ~ 239.255.255.255 */ + return RT_ERR_INPUT; + + /* Group Address */ + regAddr = RTL8367D_REG_IPMC_GROUP_ENTRY0_H + (index * 2); + regData = ((ipData & 0x0FFFFFFF) >> 16); + + if( (retVal = rtl8367d_setAsicReg(regAddr, regData)) != RT_ERR_OK) + return retVal; + + regAddr++; + regData = (ipData & 0x0000FFFF); + + if( (retVal = rtl8367d_setAsicReg(regAddr, regData)) != RT_ERR_OK) + return retVal; + + /* portmask */ + regAddr = RTL8367D_REG_IPMC_GROUP_PMSK_00 + index; + regData = pmask; + + if( (retVal = rtl8367d_setAsicReg(regAddr, regData)) != RT_ERR_OK) + return retVal; + + /* valid */ + regAddr = RTL8367D_REG_IPMC_GROUP_VALID_15_0 + (index / 16); + bitoffset = index % 16; + if( (retVal = rtl8367d_setAsicRegBit(regAddr, bitoffset, valid)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8367d_l2_init + * Description: + * Initialize l2 module of the specified device. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * Initialize l2 module before calling any l2 APIs. + */ +rtk_api_ret_t dal_rtl8367d_l2_init(void) +{ + rtk_api_ret_t retVal; + rtk_uint32 port; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_LUT_CFG, RTL8367D_LUT_IPMC_HASH_OFFSET, DISABLED)) != RT_ERR_OK) + return retVal; + + /*Enable CAM Usage*/ + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_LUT_CFG, RTL8367D_BCAM_DISABLE_OFFSET, ENABLED ? 0 : 1)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicReg(RTL8367D_REG_LUT_CFG2, 3000)) != RT_ERR_OK) + return retVal; + + RTK_SCAN_ALL_LOG_PORT(port) + { + if ((retVal = rtl8367d_setAsicReg(RTL8367D_REG_LUT_PORT0_LEARN_LIMITNO + rtk_switch_port_L2P_get(port), rtk_switch_maxLutAddrNumber_get())) != RT_ERR_OK) + return retVal; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_l2_addr_add + * Description: + * Add LUT unicast entry. + * Input: + * pMac - 6 bytes unicast(I/G bit is 0) mac address to be written into LUT. + * pL2_data - Unicast entry parameter + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_L2_FID - Invalid FID . + * RT_ERR_L2_INDEXTBL_FULL - hashed index is full of entries. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * If the unicast mac address already existed in LUT, it will udpate the status of the entry. + * Otherwise, it will find an empty or asic auto learned entry to write. If all the entries + * with the same hash value can't be replaced, ASIC will return a RT_ERR_L2_INDEXTBL_FULL error. + */ +rtk_api_ret_t dal_rtl8367d_l2_addr_add(rtk_mac_t *pMac, rtk_l2_ucastAddr_t *pL2_data) +{ + rtk_api_ret_t retVal; + rtk_uint32 method; + rtl8367d_luttb l2Table; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* must be unicast address */ + if ((pMac == NULL) || (pMac->octet[0] & 0x1)) + return RT_ERR_MAC; + + if(pL2_data == NULL) + return RT_ERR_MAC; + + RTK_CHK_PORT_VALID(pL2_data->port); + + if (pL2_data->ivl >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if (pL2_data->cvid > RTL8367D_VIDMAX) + return RT_ERR_L2_VID; + + if (pL2_data->fid > RTL8367D_FIDMAX) + return RT_ERR_L2_FID; + + if (pL2_data->is_static>= RTK_ENABLE_END) + return RT_ERR_INPUT; + + memset(&l2Table, 0, sizeof(rtl8367d_luttb)); + + /* fill key (MAC,FID) to get L2 entry */ + memcpy(l2Table.mac.octet, pMac->octet, ETHER_ADDR_LEN); + l2Table.ivl_svl = pL2_data->ivl; + l2Table.cvid_fid = (pL2_data->ivl ? pL2_data->cvid : pL2_data->fid); + method = RTL8367D_LUTREADMETHOD_MAC; + retVal = _rtl8367d_getL2LookupTb(method, &l2Table); + if (RT_ERR_OK == retVal ) + { + memcpy(l2Table.mac.octet, pMac->octet, ETHER_ADDR_LEN); + l2Table.ivl_svl = pL2_data->ivl; + l2Table.cvid_fid = (pL2_data->ivl ? pL2_data->cvid : pL2_data->fid); + l2Table.spa = rtk_switch_port_L2P_get(pL2_data->port); + l2Table.nosalearn = pL2_data->is_static; + l2Table.l3lookup = 0; + l2Table.age = 6; + if((retVal = _rtl8367d_setL2LookupTb(&l2Table)) != RT_ERR_OK) + return retVal; + + pL2_data->address = l2Table.address; + return RT_ERR_OK; + } + else if (RT_ERR_L2_ENTRY_NOTFOUND == retVal ) + { + memset(&l2Table, 0, sizeof(rtl8367d_luttb)); + memcpy(l2Table.mac.octet, pMac->octet, ETHER_ADDR_LEN); + l2Table.ivl_svl = pL2_data->ivl; + l2Table.cvid_fid = (pL2_data->ivl ? pL2_data->cvid : pL2_data->fid); + l2Table.spa = rtk_switch_port_L2P_get(pL2_data->port); + l2Table.nosalearn = pL2_data->is_static; + l2Table.l3lookup = 0; + l2Table.age = 6; + + if ((retVal = _rtl8367d_setL2LookupTb(&l2Table)) != RT_ERR_OK) + return retVal; + + pL2_data->address = l2Table.address; + + method = RTL8367D_LUTREADMETHOD_MAC; + retVal = _rtl8367d_getL2LookupTb(method, &l2Table); + if (RT_ERR_L2_ENTRY_NOTFOUND == retVal ) + return RT_ERR_L2_INDEXTBL_FULL; + else + return retVal; + } + else + return retVal; + +} + +/* Function Name: + * dal_rtl8367d_l2_addr_get + * Description: + * Get LUT unicast entry. + * Input: + * pMac - 6 bytes unicast(I/G bit is 0) mac address to be written into LUT. + * Output: + * pL2_data - Unicast entry parameter + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_L2_FID - Invalid FID . + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * If the unicast mac address existed in LUT, it will return the port and fid where + * the mac is learned. Otherwise, it will return a RT_ERR_L2_ENTRY_NOTFOUND error. + */ +rtk_api_ret_t dal_rtl8367d_l2_addr_get(rtk_mac_t *pMac, rtk_l2_ucastAddr_t *pL2_data) +{ + rtk_api_ret_t retVal; + rtk_uint32 method; + rtl8367d_luttb l2Table; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* must be unicast address */ + if ((pMac == NULL) || (pMac->octet[0] & 0x1)) + return RT_ERR_MAC; + + if (pL2_data->ivl >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if (pL2_data->ivl == 1) + { + if (pL2_data->cvid > RTL8367D_VIDMAX) + return RT_ERR_L2_VID; + } + else + { + if (pL2_data->fid > RTL8367D_FIDMAX) + return RT_ERR_L2_FID; + } + + memset(&l2Table, 0, sizeof(rtl8367d_luttb)); + + memcpy(l2Table.mac.octet, pMac->octet, ETHER_ADDR_LEN); + l2Table.ivl_svl = pL2_data->ivl; + l2Table.cvid_fid = (pL2_data->ivl ? pL2_data->cvid : pL2_data->fid); + method = RTL8367D_LUTREADMETHOD_MAC; + + if ((retVal = _rtl8367d_getL2LookupTb(method, &l2Table)) != RT_ERR_OK) + return retVal; + + memcpy(pL2_data->mac.octet, pMac->octet,ETHER_ADDR_LEN); + pL2_data->port = rtk_switch_port_P2L_get(l2Table.spa); + pL2_data->ivl = l2Table.ivl_svl; + + if (pL2_data->ivl == 1) + pL2_data->cvid = l2Table.cvid_fid; + else + pL2_data->fid = l2Table.cvid_fid; + + pL2_data->is_static = l2Table.nosalearn; + pL2_data->address = l2Table.address; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_l2_addr_next_get + * Description: + * Get Next LUT unicast entry. + * Input: + * read_method - The reading method. + * port - The port number if the read_metohd is READMETHOD_NEXT_L2UCSPA + * pAddress - The Address ID + * Output: + * pL2_data - Unicast entry parameter + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_L2_FID - Invalid FID . + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * Get the next unicast entry after the current entry pointed by pAddress. + * The address of next entry is returned by pAddress. User can use (address + 1) + * as pAddress to call this API again for dumping all entries is LUT. + */ +rtk_api_ret_t dal_rtl8367d_l2_addr_next_get(rtk_l2_read_method_t read_method, rtk_port_t port, rtk_uint32 *pAddress, rtk_l2_ucastAddr_t *pL2_data) +{ + rtk_api_ret_t retVal; + rtk_uint32 method; + rtl8367d_luttb l2Table; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Error Checking */ + if ((pL2_data == NULL) || (pAddress == NULL)) + return RT_ERR_MAC; + + if(read_method == READMETHOD_NEXT_L2UC) + method = RTL8367D_LUTREADMETHOD_NEXT_L2UC; + else if(read_method == READMETHOD_NEXT_L2UCSPA) + method = RTL8367D_LUTREADMETHOD_NEXT_L2UCSPA; + else + return RT_ERR_INPUT; + + if(read_method == READMETHOD_NEXT_L2UCSPA) + { + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + } + + if(*pAddress > RTK_MAX_LUT_ADDR_ID ) + return RT_ERR_L2_L2UNI_PARAM; + + memset(pL2_data, 0, sizeof(rtk_l2_ucastAddr_t)); + memset(&l2Table, 0, sizeof(rtl8367d_luttb)); + l2Table.address = *pAddress; + + if(read_method == READMETHOD_NEXT_L2UCSPA) + l2Table.spa = rtk_switch_port_L2P_get(port); + + if ((retVal = _rtl8367d_getL2LookupTb(method, &l2Table)) != RT_ERR_OK) + return retVal; + + if(l2Table.address < *pAddress) + return RT_ERR_L2_ENTRY_NOTFOUND; + + memcpy(pL2_data->mac.octet, l2Table.mac.octet, ETHER_ADDR_LEN); + pL2_data->port = rtk_switch_port_P2L_get(l2Table.spa); + pL2_data->ivl = l2Table.ivl_svl; + + if (pL2_data->ivl == 1) + pL2_data->cvid = l2Table.cvid_fid; + else + pL2_data->fid = l2Table.cvid_fid; + + pL2_data->is_static = l2Table.nosalearn; + pL2_data->address = l2Table.address; + + *pAddress = l2Table.address; + + return RT_ERR_OK; + +} + +/* Function Name: + * dal_rtl8367d_l2_addr_del + * Description: + * Delete LUT unicast entry. + * Input: + * pMac - 6 bytes unicast(I/G bit is 0) mac address to be written into LUT. + * fid - Filtering database + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_L2_FID - Invalid FID . + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * If the mac has existed in the LUT, it will be deleted. Otherwise, it will return RT_ERR_L2_ENTRY_NOTFOUND. + */ +rtk_api_ret_t dal_rtl8367d_l2_addr_del(rtk_mac_t *pMac, rtk_l2_ucastAddr_t *pL2_data) +{ + rtk_api_ret_t retVal; + rtk_uint32 method; + rtl8367d_luttb l2Table; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* must be unicast address */ + if ((pMac == NULL) || (pMac->octet[0] & 0x1)) + return RT_ERR_MAC; + + if (pL2_data->ivl >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if (pL2_data->ivl == 1) + { + if (pL2_data->cvid > RTL8367D_VIDMAX) + return RT_ERR_L2_VID; + } + else + { + if (pL2_data->fid > RTL8367D_FIDMAX) + return RT_ERR_L2_FID; + } + + memset(&l2Table, 0, sizeof(rtl8367d_luttb)); + + /* fill key (MAC,FID) to get L2 entry */ + memcpy(l2Table.mac.octet, pMac->octet, ETHER_ADDR_LEN); + l2Table.ivl_svl = pL2_data->ivl; + l2Table.cvid_fid = (pL2_data->ivl ? pL2_data->cvid : pL2_data->fid); + method = RTL8367D_LUTREADMETHOD_MAC; + retVal = _rtl8367d_getL2LookupTb(method, &l2Table); + if (RT_ERR_OK == retVal) + { + memcpy(l2Table.mac.octet, pMac->octet, ETHER_ADDR_LEN); + l2Table.ivl_svl = pL2_data->ivl; + l2Table.cvid_fid = (pL2_data->ivl ? pL2_data->cvid : pL2_data->fid); + l2Table.spa = 0; + l2Table.nosalearn = 0; + l2Table.age = 0; + if((retVal = _rtl8367d_setL2LookupTb(&l2Table)) != RT_ERR_OK) + return retVal; + + pL2_data->address = l2Table.address; + return RT_ERR_OK; + } + else + return retVal; +} + +/* Function Name: + * dal_rtl8367d_l2_mcastAddr_add + * Description: + * Add LUT multicast entry. + * Input: + * pMcastAddr - L2 multicast entry structure + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_L2_FID - Invalid FID . + * RT_ERR_L2_VID - Invalid VID . + * RT_ERR_L2_INDEXTBL_FULL - hashed index is full of entries. + * RT_ERR_PORT_MASK - Invalid portmask. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * If the multicast mac address already existed in the LUT, it will udpate the + * port mask of the entry. Otherwise, it will find an empty or asic auto learned + * entry to write. If all the entries with the same hash value can't be replaced, + * ASIC will return a RT_ERR_L2_INDEXTBL_FULL error. + */ +rtk_api_ret_t dal_rtl8367d_l2_mcastAddr_add(rtk_l2_mcastAddr_t *pMcastAddr) +{ + rtk_api_ret_t retVal; + rtk_uint32 method; + rtl8367d_luttb l2Table; + rtk_uint32 pmask; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pMcastAddr) + return RT_ERR_NULL_POINTER; + + /* must be L2 multicast address */ + if( (pMcastAddr->mac.octet[0] & 0x01) != 0x01) + return RT_ERR_MAC; + + RTK_CHK_PORTMASK_VALID(&pMcastAddr->portmask); + + if(pMcastAddr->ivl == 1) + { + if (pMcastAddr->vid > RTL8367D_VIDMAX) + return RT_ERR_L2_VID; + } + else if(pMcastAddr->ivl == 0) + { + if (pMcastAddr->fid > RTL8367D_FIDMAX) + return RT_ERR_L2_FID; + } + else + return RT_ERR_INPUT; + + /* Get physical port mask */ + if ((retVal = rtk_switch_portmask_L2P_get(&pMcastAddr->portmask, &pmask)) != RT_ERR_OK) + return retVal; + + memset(&l2Table, 0, sizeof(rtl8367d_luttb)); + + /* fill key (MAC,FID) to get L2 entry */ + memcpy(l2Table.mac.octet, pMcastAddr->mac.octet, ETHER_ADDR_LEN); + l2Table.ivl_svl = pMcastAddr->ivl; + + if(pMcastAddr->ivl) + l2Table.cvid_fid = pMcastAddr->vid; + else + l2Table.cvid_fid = pMcastAddr->fid; + + method = RTL8367D_LUTREADMETHOD_MAC; + retVal = _rtl8367d_getL2LookupTb(method, &l2Table); + if (RT_ERR_OK == retVal) + { + memcpy(l2Table.mac.octet, pMcastAddr->mac.octet, ETHER_ADDR_LEN); + l2Table.ivl_svl = pMcastAddr->ivl; + + if(pMcastAddr->ivl) + l2Table.cvid_fid = pMcastAddr->vid; + else + l2Table.cvid_fid = pMcastAddr->fid; + + l2Table.mbr = pmask; + l2Table.nosalearn = 1; + l2Table.l3lookup = 0; + if((retVal = _rtl8367d_setL2LookupTb(&l2Table)) != RT_ERR_OK) + return retVal; + + pMcastAddr->address = l2Table.address; + return RT_ERR_OK; + } + else if (RT_ERR_L2_ENTRY_NOTFOUND == retVal) + { + memset(&l2Table, 0, sizeof(rtl8367d_luttb)); + memcpy(l2Table.mac.octet, pMcastAddr->mac.octet, ETHER_ADDR_LEN); + l2Table.ivl_svl = pMcastAddr->ivl; + if(pMcastAddr->ivl) + l2Table.cvid_fid = pMcastAddr->vid; + else + l2Table.cvid_fid = pMcastAddr->fid; + + l2Table.mbr = pmask; + l2Table.nosalearn = 1; + l2Table.l3lookup = 0; + if ((retVal = _rtl8367d_setL2LookupTb(&l2Table)) != RT_ERR_OK) + return retVal; + + pMcastAddr->address = l2Table.address; + + method = RTL8367D_LUTREADMETHOD_MAC; + retVal = _rtl8367d_getL2LookupTb(method, &l2Table); + if (RT_ERR_L2_ENTRY_NOTFOUND == retVal) + return RT_ERR_L2_INDEXTBL_FULL; + else + return retVal; + } + else + return retVal; + +} + +/* Function Name: + * dal_rtl8367d_l2_mcastAddr_get + * Description: + * Get LUT multicast entry. + * Input: + * pMcastAddr - L2 multicast entry structure + * Output: + * pMcastAddr - L2 multicast entry structure + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_L2_FID - Invalid FID . + * RT_ERR_L2_VID - Invalid VID . + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * If the multicast mac address existed in the LUT, it will return the port where + * the mac is learned. Otherwise, it will return a RT_ERR_L2_ENTRY_NOTFOUND error. + */ +rtk_api_ret_t dal_rtl8367d_l2_mcastAddr_get(rtk_l2_mcastAddr_t *pMcastAddr) +{ + rtk_api_ret_t retVal; + rtk_uint32 method; + rtl8367d_luttb l2Table; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pMcastAddr) + return RT_ERR_NULL_POINTER; + + /* must be L2 multicast address */ + if( (pMcastAddr->mac.octet[0] & 0x01) != 0x01) + return RT_ERR_MAC; + + if(pMcastAddr->ivl == 1) + { + if (pMcastAddr->vid > RTL8367D_VIDMAX) + return RT_ERR_L2_VID; + } + else if(pMcastAddr->ivl == 0) + { + if (pMcastAddr->fid > RTL8367D_FIDMAX) + return RT_ERR_L2_FID; + } + else + return RT_ERR_INPUT; + + memset(&l2Table, 0, sizeof(rtl8367d_luttb)); + memcpy(l2Table.mac.octet, pMcastAddr->mac.octet, ETHER_ADDR_LEN); + l2Table.ivl_svl = pMcastAddr->ivl; + + if(pMcastAddr->ivl) + l2Table.cvid_fid = pMcastAddr->vid; + else + l2Table.cvid_fid = pMcastAddr->fid; + + method = RTL8367D_LUTREADMETHOD_MAC; + + if ((retVal = _rtl8367d_getL2LookupTb(method, &l2Table)) != RT_ERR_OK) + return retVal; + + pMcastAddr->address = l2Table.address; + + /* Get Logical port mask */ + if ((retVal = rtk_switch_portmask_P2L_get(l2Table.mbr, &pMcastAddr->portmask)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_l2_mcastAddr_next_get + * Description: + * Get Next L2 Multicast entry. + * Input: + * pAddress - The Address ID + * Output: + * pMcastAddr - L2 multicast entry structure + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * Get the next L2 multicast entry after the current entry pointed by pAddress. + * The address of next entry is returned by pAddress. User can use (address + 1) + * as pAddress to call this API again for dumping all multicast entries is LUT. + */ +rtk_api_ret_t dal_rtl8367d_l2_mcastAddr_next_get(rtk_uint32 *pAddress, rtk_l2_mcastAddr_t *pMcastAddr) +{ + rtk_api_ret_t retVal; + rtl8367d_luttb l2Table; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Error Checking */ + if ((pAddress == NULL) || (pMcastAddr == NULL)) + return RT_ERR_INPUT; + + if(*pAddress > RTK_MAX_LUT_ADDR_ID ) + return RT_ERR_L2_L2UNI_PARAM; + + memset(pMcastAddr, 0, sizeof(rtk_l2_mcastAddr_t)); + memset(&l2Table, 0, sizeof(rtl8367d_luttb)); + l2Table.address = *pAddress; + + if ((retVal = _rtl8367d_getL2LookupTb(RTL8367D_LUTREADMETHOD_NEXT_L2MC, &l2Table)) != RT_ERR_OK) + return retVal; + + if(l2Table.address < *pAddress) + return RT_ERR_L2_ENTRY_NOTFOUND; + + memcpy(pMcastAddr->mac.octet, l2Table.mac.octet, ETHER_ADDR_LEN); + pMcastAddr->ivl = l2Table.ivl_svl; + + if(pMcastAddr->ivl) + pMcastAddr->vid = l2Table.cvid_fid; + else + pMcastAddr->fid = l2Table.cvid_fid; + + pMcastAddr->address = l2Table.address; + + /* Get Logical port mask */ + if ((retVal = rtk_switch_portmask_P2L_get(l2Table.mbr, &pMcastAddr->portmask)) != RT_ERR_OK) + return retVal; + + *pAddress = l2Table.address; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_l2_mcastAddr_del + * Description: + * Delete LUT multicast entry. + * Input: + * pMcastAddr - L2 multicast entry structure + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_L2_FID - Invalid FID . + * RT_ERR_L2_VID - Invalid VID . + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * If the mac has existed in the LUT, it will be deleted. Otherwise, it will return RT_ERR_L2_ENTRY_NOTFOUND. + */ +rtk_api_ret_t dal_rtl8367d_l2_mcastAddr_del(rtk_l2_mcastAddr_t *pMcastAddr) +{ + rtk_api_ret_t retVal; + rtk_uint32 method; + rtl8367d_luttb l2Table; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pMcastAddr) + return RT_ERR_NULL_POINTER; + + /* must be L2 multicast address */ + if( (pMcastAddr->mac.octet[0] & 0x01) != 0x01) + return RT_ERR_MAC; + + if(pMcastAddr->ivl == 1) + { + if (pMcastAddr->vid > RTL8367D_VIDMAX) + return RT_ERR_L2_VID; + } + else if(pMcastAddr->ivl == 0) + { + if (pMcastAddr->fid > RTL8367D_FIDMAX) + return RT_ERR_L2_FID; + } + else + return RT_ERR_INPUT; + + memset(&l2Table, 0, sizeof(rtl8367d_luttb)); + + /* fill key (MAC,FID) to get L2 entry */ + memcpy(l2Table.mac.octet, pMcastAddr->mac.octet, ETHER_ADDR_LEN); + l2Table.ivl_svl = pMcastAddr->ivl; + + if(pMcastAddr->ivl) + l2Table.cvid_fid = pMcastAddr->vid; + else + l2Table.cvid_fid = pMcastAddr->fid; + + method = RTL8367D_LUTREADMETHOD_MAC; + retVal = _rtl8367d_getL2LookupTb(method, &l2Table); + if (RT_ERR_OK == retVal) + { + memcpy(l2Table.mac.octet, pMcastAddr->mac.octet, ETHER_ADDR_LEN); + l2Table.ivl_svl = pMcastAddr->ivl; + + if(pMcastAddr->ivl) + l2Table.cvid_fid = pMcastAddr->vid; + else + l2Table.cvid_fid = pMcastAddr->fid; + + l2Table.mbr = 0; + l2Table.nosalearn = 0; +// l2Table.sa_block = 0; + l2Table.l3lookup = 0; + if((retVal = _rtl8367d_setL2LookupTb(&l2Table)) != RT_ERR_OK) + return retVal; + + pMcastAddr->address = l2Table.address; + return RT_ERR_OK; + } + else + return retVal; +} + +/* Function Name: + * dal_rtl8367d_l2_ipMcastAddr_add + * Description: + * Add Lut IP multicast entry + * Input: + * pIpMcastAddr - IP Multicast entry + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_L2_INDEXTBL_FULL - hashed index is full of entries. + * RT_ERR_PORT_MASK - Invalid portmask. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * System supports L2 entry with IP multicast DIP/SIP to forward IP multicasting frame as user + * desired. If this function is enabled, then system will be looked up L2 IP multicast entry to + * forward IP multicast frame directly without flooding. + */ +rtk_api_ret_t dal_rtl8367d_l2_ipMcastAddr_add(rtk_l2_ipMcastAddr_t *pIpMcastAddr) +{ + rtk_api_ret_t retVal; + rtk_uint32 method; + rtl8367d_luttb l2Table; + rtk_uint32 pmask; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pIpMcastAddr) + return RT_ERR_NULL_POINTER; + + /* check port mask */ + RTK_CHK_PORTMASK_VALID(&pIpMcastAddr->portmask); + + if( (pIpMcastAddr->dip & 0xF0000000) != 0xE0000000) + return RT_ERR_INPUT; + + /* Get Physical port mask */ + if ((retVal = rtk_switch_portmask_L2P_get(&pIpMcastAddr->portmask, &pmask)) != RT_ERR_OK) + return retVal; + + memset(&l2Table, 0x00, sizeof(rtl8367d_luttb)); + l2Table.sip = pIpMcastAddr->sip; + l2Table.dip = pIpMcastAddr->dip; + l2Table.l3lookup = 1; + method = RTL8367D_LUTREADMETHOD_MAC; + retVal = _rtl8367d_getL2LookupTb(method, &l2Table); + if (RT_ERR_OK == retVal) + { + l2Table.sip = pIpMcastAddr->sip; + l2Table.dip = pIpMcastAddr->dip; + l2Table.mbr = pmask; + l2Table.nosalearn = 1; + l2Table.l3lookup = 1; + if((retVal = _rtl8367d_setL2LookupTb(&l2Table)) != RT_ERR_OK) + return retVal; + + pIpMcastAddr->address = l2Table.address; + return RT_ERR_OK; + } + else if (RT_ERR_L2_ENTRY_NOTFOUND == retVal) + { + memset(&l2Table, 0, sizeof(rtl8367d_luttb)); + l2Table.sip = pIpMcastAddr->sip; + l2Table.dip = pIpMcastAddr->dip; + l2Table.mbr = pmask; + l2Table.nosalearn = 1; + l2Table.l3lookup = 1; + if ((retVal = _rtl8367d_setL2LookupTb(&l2Table)) != RT_ERR_OK) + return retVal; + + pIpMcastAddr->address = l2Table.address; + + method = RTL8367D_LUTREADMETHOD_MAC; + retVal = _rtl8367d_getL2LookupTb(method, &l2Table); + if (RT_ERR_L2_ENTRY_NOTFOUND == retVal) + return RT_ERR_L2_INDEXTBL_FULL; + else + return retVal; + + } + else + return retVal; + +} + +/* Function Name: + * dal_rtl8367d_l2_ipMcastAddr_get + * Description: + * Get LUT IP multicast entry. + * Input: + * pIpMcastAddr - IP Multicast entry + * Output: + * pIpMcastAddr - IP Multicast entry + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get Lut table of IP multicast entry. + */ +rtk_api_ret_t dal_rtl8367d_l2_ipMcastAddr_get(rtk_l2_ipMcastAddr_t *pIpMcastAddr) +{ + rtk_api_ret_t retVal; + rtk_uint32 method; + rtl8367d_luttb l2Table; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pIpMcastAddr) + return RT_ERR_NULL_POINTER; + + if( (pIpMcastAddr->dip & 0xF0000000) != 0xE0000000) + return RT_ERR_INPUT; + + memset(&l2Table, 0x00, sizeof(rtl8367d_luttb)); + l2Table.sip = pIpMcastAddr->sip; + l2Table.dip = pIpMcastAddr->dip; + l2Table.l3lookup = 1; + method = RTL8367D_LUTREADMETHOD_MAC; + if ((retVal = _rtl8367d_getL2LookupTb(method, &l2Table)) != RT_ERR_OK) + return retVal; + + /* Get Logical port mask */ + if ((retVal = rtk_switch_portmask_P2L_get(l2Table.mbr, &pIpMcastAddr->portmask)) != RT_ERR_OK) + return retVal; + + pIpMcastAddr->address = l2Table.address; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_l2_ipMcastAddr_next_get + * Description: + * Get Next IP Multicast entry. + * Input: + * pAddress - The Address ID + * Output: + * pIpMcastAddr - IP Multicast entry + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * Get the next IP multicast entry after the current entry pointed by pAddress. + * The address of next entry is returned by pAddress. User can use (address + 1) + * as pAddress to call this API again for dumping all IP multicast entries is LUT. + */ +rtk_api_ret_t dal_rtl8367d_l2_ipMcastAddr_next_get(rtk_uint32 *pAddress, rtk_l2_ipMcastAddr_t *pIpMcastAddr) +{ + rtk_api_ret_t retVal; + rtl8367d_luttb l2Table; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Error Checking */ + if ((pAddress == NULL) || (pIpMcastAddr == NULL) ) + return RT_ERR_INPUT; + + if(*pAddress > RTK_MAX_LUT_ADDR_ID ) + return RT_ERR_L2_L2UNI_PARAM; + + memset(pIpMcastAddr, 0, sizeof(rtk_l2_ipMcastAddr_t)); + memset(&l2Table, 0, sizeof(rtl8367d_luttb)); + l2Table.address = *pAddress; + + if ((retVal = _rtl8367d_getL2LookupTb(RTL8367D_LUTREADMETHOD_NEXT_L3MC, &l2Table)) != RT_ERR_OK) + return retVal; + + if(l2Table.address < *pAddress) + return RT_ERR_L2_ENTRY_NOTFOUND; + + pIpMcastAddr->sip = l2Table.sip; + pIpMcastAddr->dip = l2Table.dip; + + /* Get Logical port mask */ + if ((retVal = rtk_switch_portmask_P2L_get(l2Table.mbr, &pIpMcastAddr->portmask)) != RT_ERR_OK) + return retVal; + + pIpMcastAddr->address = l2Table.address; + *pAddress = l2Table.address; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_l2_ipMcastAddr_del + * Description: + * Delete a ip multicast address entry from the specified device. + * Input: + * pIpMcastAddr - IP Multicast entry + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can delete a IP multicast address entry from the specified device. + */ +rtk_api_ret_t dal_rtl8367d_l2_ipMcastAddr_del(rtk_l2_ipMcastAddr_t *pIpMcastAddr) +{ + rtk_api_ret_t retVal; + rtk_uint32 method; + rtl8367d_luttb l2Table; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Error Checking */ + if (pIpMcastAddr == NULL) + return RT_ERR_INPUT; + + if( (pIpMcastAddr->dip & 0xF0000000) != 0xE0000000) + return RT_ERR_INPUT; + + memset(&l2Table, 0x00, sizeof(rtl8367d_luttb)); + l2Table.sip = pIpMcastAddr->sip; + l2Table.dip = pIpMcastAddr->dip; + l2Table.l3lookup = 1; + method = RTL8367D_LUTREADMETHOD_MAC; + retVal = _rtl8367d_getL2LookupTb(method, &l2Table); + if (RT_ERR_OK == retVal) + { + l2Table.sip = pIpMcastAddr->sip; + l2Table.dip = pIpMcastAddr->dip; + l2Table.mbr = 0; + l2Table.nosalearn = 0; + l2Table.l3lookup = 1; + if((retVal = _rtl8367d_setL2LookupTb(&l2Table)) != RT_ERR_OK) + return retVal; + + pIpMcastAddr->address = l2Table.address; + return RT_ERR_OK; + } + else + return retVal; +} + +/* Function Name: + * dal_rtl8367d_l2_ucastAddr_flush + * Description: + * Flush L2 mac address by type in the specified device (both dynamic and static). + * Input: + * pConfig - flush configuration + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * flushByVid - 1: Flush by VID, 0: Don't flush by VID + * vid - VID (0 ~ 4095) + * flushByFid - 1: Flush by FID, 0: Don't flush by FID + * fid - FID (0 ~ 15) + * flushByPort - 1: Flush by Port, 0: Don't flush by Port + * port - Port ID + * flushByMac - Not Supported + * ucastAddr - Not Supported + * flushStaticAddr - 1: Flush both Static and Dynamic entries, 0: Flush only Dynamic entries + * flushAddrOnAllPorts - 1: Flush VID-matched entries at all ports, 0: Flush VID-matched entries per port. + */ +rtk_api_ret_t dal_rtl8367d_l2_ucastAddr_flush(rtk_l2_flushCfg_t *pConfig) +{ + rtk_api_ret_t retVal; + rtk_uint32 phyPort; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(pConfig == NULL) + return RT_ERR_NULL_POINTER; + + if(pConfig->flushByVid >= RTK_ENABLE_END) + return RT_ERR_ENABLE; + + if(pConfig->flushByFid >= RTK_ENABLE_END) + return RT_ERR_ENABLE; + + if(pConfig->flushByPort >= RTK_ENABLE_END) + return RT_ERR_ENABLE; + + if(pConfig->flushByMac >= RTK_ENABLE_END) + return RT_ERR_ENABLE; + + if(pConfig->flushStaticAddr >= RTK_ENABLE_END) + return RT_ERR_ENABLE; + + if(pConfig->flushAddrOnAllPorts >= RTK_ENABLE_END) + return RT_ERR_ENABLE; + + if(pConfig->vid > RTL8367D_VIDMAX) + return RT_ERR_VLAN_VID; + + if(pConfig->fid > RTL8367D_FIDMAX) + return RT_ERR_INPUT; + + /* check port valid */ + RTK_CHK_PORT_VALID(pConfig->port); + + phyPort = rtk_switch_port_L2P_get(pConfig->port); + if (phyPort == UNDEFINE_PHY_PORT) + return RT_ERR_PORT_ID; + + if(pConfig->flushByVid == ENABLED) + { + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_L2_FLUSH_CTRL2, RTL8367D_LUT_FLUSH_MODE_MASK, RTL8367D_FLUSHMDOE_VID)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_L2_FLUSH_CTRL1, RTL8367D_LUT_FLUSH_VID_MASK, pConfig->vid)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_L2_FLUSH_CTRL2, RTL8367D_LUT_FLUSH_TYPE_OFFSET,((pConfig->flushStaticAddr == ENABLED) ? RTL8367D_FLUSHTYPE_BOTH : RTL8367D_FLUSHTYPE_DYNAMIC))) != RT_ERR_OK) + return retVal; + + if(pConfig->flushAddrOnAllPorts == ENABLED) + { + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_FORCE_FLUSH, RTL8367D_FORCE_FLUSH_PORTMASK_MASK, RTL8367D_PORTMASK)) != RT_ERR_OK) + return retVal; + } + else if(pConfig->flushByPort == ENABLED) + { + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_FORCE_FLUSH, RTL8367D_FORCE_FLUSH_PORTMASK_MASK, (1 << phyPort) & 0xff)) != RT_ERR_OK) + return retVal; + } + else + return RT_ERR_INPUT; + } + else if(pConfig->flushByFid == ENABLED) + { + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_L2_FLUSH_CTRL2, RTL8367D_LUT_FLUSH_MODE_MASK, RTL8367D_FLUSHMDOE_FID)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_L2_FLUSH_CTRL1, RTL8367D_LUT_FLUSH_FID_MASK, pConfig->fid)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_L2_FLUSH_CTRL2, RTL8367D_LUT_FLUSH_TYPE_OFFSET,((pConfig->flushStaticAddr == ENABLED) ? RTL8367D_FLUSHTYPE_BOTH : RTL8367D_FLUSHTYPE_DYNAMIC))) != RT_ERR_OK) + return retVal; + + if(pConfig->flushAddrOnAllPorts == ENABLED) + { + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_FORCE_FLUSH, RTL8367D_FORCE_FLUSH_PORTMASK_MASK, RTL8367D_PORTMASK)) != RT_ERR_OK) + return retVal; + } + else if(pConfig->flushByPort == ENABLED) + { + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_FORCE_FLUSH, RTL8367D_FORCE_FLUSH_PORTMASK_MASK, (1 << phyPort) & 0xff)) != RT_ERR_OK) + return retVal; + } + else + return RT_ERR_INPUT; + } + else if(pConfig->flushByPort == ENABLED) + { + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_L2_FLUSH_CTRL2, RTL8367D_LUT_FLUSH_TYPE_OFFSET,((pConfig->flushStaticAddr == ENABLED) ? RTL8367D_FLUSHTYPE_BOTH : RTL8367D_FLUSHTYPE_DYNAMIC))) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_L2_FLUSH_CTRL2, RTL8367D_LUT_FLUSH_MODE_MASK, RTL8367D_FLUSHMDOE_PORT)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_FORCE_FLUSH, RTL8367D_FORCE_FLUSH_PORTMASK_MASK, (1 << phyPort) & 0xff)) != RT_ERR_OK) + return retVal; + } + else if(pConfig->flushByMac == ENABLED) + { + /* Should use API "rtk_l2_addr_del" to remove a specified entry*/ + return RT_ERR_CHIP_NOT_SUPPORTED; + } + else + return RT_ERR_INPUT; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_l2_table_clear + * Description: + * Flush all static & dynamic entries in LUT. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * + */ +rtk_api_ret_t dal_rtl8367d_l2_table_clear(void) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_L2_FLUSH_CTRL3, RTL8367D_L2_FLUSH_CTRL3_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_l2_table_clearStatus_get + * Description: + * Get table clear status + * Input: + * None + * Output: + * pStatus - Clear status, 1:Busy, 0:finish + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * + */ +rtk_api_ret_t dal_rtl8367d_l2_table_clearStatus_get(rtk_l2_clearStatus_t *pStatus) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pStatus) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_L2_FLUSH_CTRL3, RTL8367D_L2_FLUSH_CTRL3_OFFSET, (rtk_uint32 *)pStatus)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_l2_flushLinkDownPortAddrEnable_set + * Description: + * Set HW flush linkdown port mac configuration of the specified device. + * Input: + * port - Port id. + * enable - link down flush status + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * The status of flush linkdown port address is as following: + * - DISABLED + * - ENABLED + */ +rtk_api_ret_t dal_rtl8367d_l2_flushLinkDownPortAddrEnable_set(rtk_port_t port, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (port != RTK_WHOLE_SYSTEM) + return RT_ERR_PORT_ID; + + if (enable >= RTK_ENABLE_END) + return RT_ERR_ENABLE; + + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_LUT_CFG, RTL8367D_LINKDOWN_AGEOUT_OFFSET, enable ? 0 : 1)) != RT_ERR_OK) + return retVal; + + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_l2_flushLinkDownPortAddrEnable_get + * Description: + * Get HW flush linkdown port mac configuration of the specified device. + * Input: + * port - Port id. + * Output: + * pEnable - link down flush status + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The status of flush linkdown port address is as following: + * - DISABLED + * - ENABLED + */ +rtk_api_ret_t dal_rtl8367d_l2_flushLinkDownPortAddrEnable_get(rtk_port_t port, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + rtk_uint32 value; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (port != RTK_WHOLE_SYSTEM) + return RT_ERR_PORT_ID; + + if(NULL == pEnable) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_LUT_CFG, RTL8367D_LINKDOWN_AGEOUT_OFFSET, &value)) != RT_ERR_OK) + return retVal; + + *pEnable = value ? 0 : 1; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_l2_agingEnable_set + * Description: + * Set L2 LUT aging status per port setting. + * Input: + * port - Port id. + * enable - Aging status + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * This API can be used to set L2 LUT aging status per port. + */ +rtk_api_ret_t dal_rtl8367d_l2_agingEnable_set(rtk_port_t port, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* check port valid */ + RTK_CHK_PORT_VALID(port); + + if (enable >= RTK_ENABLE_END) + return RT_ERR_ENABLE; + + if(enable == 1) + enable = 0; + else + enable = 1; + + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_LUT_AGEOUT_CTRL, rtk_switch_port_L2P_get(port), enable)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_l2_agingEnable_get + * Description: + * Get L2 LUT aging status per port setting. + * Input: + * port - Port id. + * Output: + * pEnable - Aging status + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can be used to get L2 LUT aging function per port. + */ +rtk_api_ret_t dal_rtl8367d_l2_agingEnable_get(rtk_port_t port, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* check port valid */ + RTK_CHK_PORT_VALID(port); + + if(NULL == pEnable) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_LUT_AGEOUT_CTRL, rtk_switch_port_L2P_get(port), pEnable)) != RT_ERR_OK) + return retVal; + + if(*pEnable == 1) + *pEnable = 0; + else + *pEnable = 1; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_l2_limitLearningCnt_set + * Description: + * Set per-Port auto learning limit number + * Input: + * port - Port id. + * mac_cnt - Auto learning entries limit number + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_LIMITED_L2ENTRY_NUM - Invalid auto learning limit number + * Note: + * The API can set per-port ASIC auto learning limit number from 0(disable learning) + * to 2112. + */ +rtk_api_ret_t dal_rtl8367d_l2_limitLearningCnt_set(rtk_port_t port, rtk_mac_cnt_t mac_cnt) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* check port valid */ + RTK_CHK_PORT_VALID(port); + + if (mac_cnt > rtk_switch_maxLutAddrNumber_get()) + return RT_ERR_LIMITED_L2ENTRY_NUM; + + if ((retVal = rtl8367d_setAsicReg(RTL8367D_REG_LUT_PORT0_LEARN_LIMITNO + rtk_switch_port_L2P_get(port), mac_cnt)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_l2_limitLearningCnt_get + * Description: + * Get per-Port auto learning limit number + * Input: + * port - Port id. + * Output: + * pMac_cnt - Auto learning entries limit number + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get per-port ASIC auto learning limit number. + */ +rtk_api_ret_t dal_rtl8367d_l2_limitLearningCnt_get(rtk_port_t port, rtk_mac_cnt_t *pMac_cnt) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* check port valid */ + RTK_CHK_PORT_VALID(port); + + if(NULL == pMac_cnt) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367d_getAsicReg(RTL8367D_REG_LUT_PORT0_LEARN_LIMITNO + rtk_switch_port_L2P_get(port), ®Data)) != RT_ERR_OK) + return retVal; + + *pMac_cnt = (rtk_mac_cnt_t)((regData > rtk_switch_maxLutAddrNumber_get()) ? rtk_switch_maxLutAddrNumber_get() : regData); + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_l2_limitSystemLearningCnt_set + * Description: + * Set System auto learning limit number + * Input: + * mac_cnt - Auto learning entries limit number + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_LIMITED_L2ENTRY_NUM - Invalid auto learning limit number + * Note: + * The API can set system ASIC auto learning limit number from 0(disable learning) + * to 2112. + */ +rtk_api_ret_t dal_rtl8367d_l2_limitSystemLearningCnt_set(rtk_mac_cnt_t mac_cnt) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (mac_cnt > rtk_switch_maxLutAddrNumber_get()) + return RT_ERR_LIMITED_L2ENTRY_NUM; + + if ((retVal = rtl8367d_setAsicReg(RTL8367D_REG_LUT_SYS_LEARN_LIMITNO, mac_cnt)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_l2_limitSystemLearningCnt_get + * Description: + * Get System auto learning limit number + * Input: + * None + * Output: + * pMac_cnt - Auto learning entries limit number + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get system ASIC auto learning limit number. + */ +rtk_api_ret_t dal_rtl8367d_l2_limitSystemLearningCnt_get(rtk_mac_cnt_t *pMac_cnt) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pMac_cnt) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367d_getAsicReg(RTL8367D_REG_LUT_SYS_LEARN_LIMITNO, pMac_cnt)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_l2_limitLearningCntAction_set + * Description: + * Configure auto learn over limit number action. + * Input: + * port - Port id. + * action - Auto learning entries limit number + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_NOT_ALLOWED - Invalid learn over action + * Note: + * The API can set SA unknown packet action while auto learn limit number is over + * The action symbol as following: + * - LIMIT_LEARN_CNT_ACTION_DROP, + * - LIMIT_LEARN_CNT_ACTION_FORWARD, + * - LIMIT_LEARN_CNT_ACTION_TO_CPU, + */ +rtk_api_ret_t dal_rtl8367d_l2_limitLearningCntAction_set(rtk_port_t port, rtk_l2_limitLearnCntAction_t action) +{ + rtk_api_ret_t retVal; + rtk_uint32 data; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (port != RTK_WHOLE_SYSTEM) + return RT_ERR_PORT_ID; + + if ( LIMIT_LEARN_CNT_ACTION_DROP == action ) + data = 1; + else if ( LIMIT_LEARN_CNT_ACTION_FORWARD == action ) + data = 0; + else if ( LIMIT_LEARN_CNT_ACTION_TO_CPU == action ) + data = 2; + else + return RT_ERR_NOT_ALLOWED; + + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_PORT_SECURITY_CTRL, RTL8367D_PORT_SECURITY_CTRL_MASK, data)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_l2_limitLearningCntAction_get + * Description: + * Get auto learn over limit number action. + * Input: + * port - Port id. + * Output: + * pAction - Learn over action + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get SA unknown packet action while auto learn limit number is over + * The action symbol as following: + * - LIMIT_LEARN_CNT_ACTION_DROP, + * - LIMIT_LEARN_CNT_ACTION_FORWARD, + * - LIMIT_LEARN_CNT_ACTION_TO_CPU, + */ +rtk_api_ret_t dal_rtl8367d_l2_limitLearningCntAction_get(rtk_port_t port, rtk_l2_limitLearnCntAction_t *pAction) +{ + rtk_api_ret_t retVal; + rtk_uint32 action; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (port != RTK_WHOLE_SYSTEM) + return RT_ERR_PORT_ID; + + if(NULL == pAction) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_PORT_SECURITY_CTRL, RTL8367D_PORT_SECURITY_CTRL_MASK, &action)) != RT_ERR_OK) + return retVal; + + if ( 1 == action ) + *pAction = LIMIT_LEARN_CNT_ACTION_DROP; + else if ( 0 == action ) + *pAction = LIMIT_LEARN_CNT_ACTION_FORWARD; + else if ( 2 == action ) + *pAction = LIMIT_LEARN_CNT_ACTION_TO_CPU; + else + *pAction = action; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_l2_limitSystemLearningCntAction_set + * Description: + * Configure system auto learn over limit number action. + * Input: + * port - Port id. + * action - Auto learning entries limit number + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_NOT_ALLOWED - Invalid learn over action + * Note: + * The API can set SA unknown packet action while auto learn limit number is over + * The action symbol as following: + * - LIMIT_LEARN_CNT_ACTION_DROP, + * - LIMIT_LEARN_CNT_ACTION_FORWARD, + * - LIMIT_LEARN_CNT_ACTION_TO_CPU, + */ +rtk_api_ret_t dal_rtl8367d_l2_limitSystemLearningCntAction_set(rtk_l2_limitLearnCntAction_t action) +{ + rtk_api_ret_t retVal; + rtk_uint32 data; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if ( LIMIT_LEARN_CNT_ACTION_DROP == action ) + data = 1; + else if ( LIMIT_LEARN_CNT_ACTION_FORWARD == action ) + data = 0; + else if ( LIMIT_LEARN_CNT_ACTION_TO_CPU == action ) + data = 2; + else + return RT_ERR_NOT_ALLOWED; + + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_LUT_LRN_SYS_LMT_CTRL, RTL8367D_LUT_SYSTEM_LEARN_OVER_ACT_MASK, data)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_l2_limitSystemLearningCntAction_get + * Description: + * Get system auto learn over limit number action. + * Input: + * None. + * Output: + * pAction - Learn over action + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get SA unknown packet action while auto learn limit number is over + * The action symbol as following: + * - LIMIT_LEARN_CNT_ACTION_DROP, + * - LIMIT_LEARN_CNT_ACTION_FORWARD, + * - LIMIT_LEARN_CNT_ACTION_TO_CPU, + */ +rtk_api_ret_t dal_rtl8367d_l2_limitSystemLearningCntAction_get(rtk_l2_limitLearnCntAction_t *pAction) +{ + rtk_api_ret_t retVal; + rtk_uint32 action; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pAction) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_LUT_LRN_SYS_LMT_CTRL, RTL8367D_LUT_SYSTEM_LEARN_OVER_ACT_MASK, &action)) != RT_ERR_OK) + return retVal; + + if ( 1 == action ) + *pAction = LIMIT_LEARN_CNT_ACTION_DROP; + else if ( 0 == action ) + *pAction = LIMIT_LEARN_CNT_ACTION_FORWARD; + else if ( 2 == action ) + *pAction = LIMIT_LEARN_CNT_ACTION_TO_CPU; + else + *pAction = action; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_l2_limitSystemLearningCntPortMask_set + * Description: + * Configure system auto learn portmask + * Input: + * pPortmask - Port Mask + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Invalid port mask. + * Note: + * + */ +rtk_api_ret_t dal_rtl8367d_l2_limitSystemLearningCntPortMask_set(rtk_portmask_t *pPortmask) +{ + rtk_api_ret_t retVal; + rtk_uint32 pmask; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pPortmask) + return RT_ERR_NULL_POINTER; + + /* Check port mask */ + RTK_CHK_PORTMASK_VALID(pPortmask); + + if ((retVal = rtk_switch_portmask_L2P_get(pPortmask, &pmask)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_LUT_LRN_SYS_LMT_CTRL, RTL8367D_LUT_SYSTEM_LEARN_PMASK_MASK, pmask & 0xff)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_l2_limitSystemLearningCntPortMask_get + * Description: + * get system auto learn portmask + * Input: + * None + * Output: + * pPortmask - Port Mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Null pointer. + * Note: + * + */ +rtk_api_ret_t dal_rtl8367d_l2_limitSystemLearningCntPortMask_get(rtk_portmask_t *pPortmask) +{ + rtk_api_ret_t retVal; + rtk_uint32 pmask; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pPortmask) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_LUT_LRN_SYS_LMT_CTRL, RTL8367D_LUT_SYSTEM_LEARN_PMASK_MASK, &pmask)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtk_switch_portmask_P2L_get(pmask, pPortmask)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_l2_learningCnt_get + * Description: + * Get per-Port current auto learning number + * Input: + * port - Port id. + * Output: + * pMac_cnt - ASIC auto learning entries number + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get per-port ASIC auto learning number + */ +rtk_api_ret_t dal_rtl8367d_l2_learningCnt_get(rtk_port_t port, rtk_mac_cnt_t *pMac_cnt) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* check port valid */ + RTK_CHK_PORT_VALID(port); + + if(NULL == pMac_cnt) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367d_getAsicReg(RTL8367D_REG_L2_LRN_CNT_CTRL0 + rtk_switch_port_L2P_get(port), pMac_cnt)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_l2_floodPortMask_set + * Description: + * Set flooding portmask + * Input: + * type - flooding type. + * pFlood_portmask - flooding porkmask + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Invalid portmask. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can set the flooding mask. + * The flooding type is as following: + * - FLOOD_UNKNOWNDA + * - FLOOD_UNKNOWNMC + * - FLOOD_BC + */ +rtk_api_ret_t dal_rtl8367d_l2_floodPortMask_set(rtk_l2_flood_type_t floood_type, rtk_portmask_t *pFlood_portmask) +{ + rtk_api_ret_t retVal; + rtk_uint32 pmask; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (floood_type >= FLOOD_END) + return RT_ERR_INPUT; + + /* check port valid */ + RTK_CHK_PORTMASK_VALID(pFlood_portmask); + + /* Get Physical port mask */ + if ((retVal = rtk_switch_portmask_L2P_get(pFlood_portmask, &pmask))!=RT_ERR_OK) + return retVal; + + switch (floood_type) + { + case FLOOD_UNKNOWNDA: + if ((retVal = rtl8367d_setAsicReg(RTL8367D_REG_UNDA_FLOODING_PMSK, pmask)) != RT_ERR_OK) + return retVal; + break; + case FLOOD_UNKNOWNMC: + if ((retVal = rtl8367d_setAsicReg(RTL8367D_REG_UNMCAST_FLOADING_PMSK, pmask)) != RT_ERR_OK) + return retVal; + break; + case FLOOD_BC: + if ((retVal = rtl8367d_setAsicReg(RTL8367D_REG_BCAST_FLOADING_PMSK, pmask)) != RT_ERR_OK) + return retVal; + break; + default: + break; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_l2_floodPortMask_get + * Description: + * Get flooding portmask + * Input: + * type - flooding type. + * Output: + * pFlood_portmask - flooding porkmask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can get the flooding mask. + * The flooding type is as following: + * - FLOOD_UNKNOWNDA + * - FLOOD_UNKNOWNMC + * - FLOOD_BC + */ +rtk_api_ret_t dal_rtl8367d_l2_floodPortMask_get(rtk_l2_flood_type_t floood_type, rtk_portmask_t *pFlood_portmask) +{ + rtk_api_ret_t retVal; + rtk_uint32 pmask; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (floood_type >= FLOOD_END) + return RT_ERR_INPUT; + + if(NULL == pFlood_portmask) + return RT_ERR_NULL_POINTER; + + switch (floood_type) + { + case FLOOD_UNKNOWNDA: + if ((retVal = rtl8367d_getAsicReg(RTL8367D_REG_UNDA_FLOODING_PMSK, &pmask)) != RT_ERR_OK) + return retVal; + break; + case FLOOD_UNKNOWNMC: + if ((retVal = rtl8367d_getAsicReg(RTL8367D_REG_UNMCAST_FLOADING_PMSK, &pmask)) != RT_ERR_OK) + return retVal; + break; + case FLOOD_BC: + if ((retVal = rtl8367d_getAsicReg(RTL8367D_REG_BCAST_FLOADING_PMSK, &pmask)) != RT_ERR_OK) + return retVal; + break; + default: + break; + } + + /* Get Logical port mask */ + if ((retVal = rtk_switch_portmask_P2L_get(pmask, pFlood_portmask))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_l2_localPktPermit_set + * Description: + * Set permittion of frames if source port and destination port are the same. + * Input: + * port - Port id. + * permit - permittion status + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid permit value. + * Note: + * This API is setted to permit frame if its source port is equal to destination port. + */ +rtk_api_ret_t dal_rtl8367d_l2_localPktPermit_set(rtk_port_t port, rtk_enable_t permit) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* check port valid */ + RTK_CHK_PORT_VALID(port); + + if (permit >= RTK_ENABLE_END) + return RT_ERR_ENABLE; + + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_SOURCE_PORT_PERMIT, rtk_switch_port_L2P_get(port), permit)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_l2_localPktPermit_get + * Description: + * Get permittion of frames if source port and destination port are the same. + * Input: + * port - Port id. + * Output: + * pPermit - permittion status + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API is to get permittion status for frames if its source port is equal to destination port. + */ +rtk_api_ret_t dal_rtl8367d_l2_localPktPermit_get(rtk_port_t port, rtk_enable_t *pPermit) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* check port valid */ + RTK_CHK_PORT_VALID(port); + + if(NULL == pPermit) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_SOURCE_PORT_PERMIT, rtk_switch_port_L2P_get(port), pPermit)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_l2_aging_set + * Description: + * Set LUT agging out speed + * Input: + * aging_time - Agging out time. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - input out of range. + * Note: + * The API can set LUT agging out period for each entry and the range is from 45s to 458s. + */ +rtk_api_ret_t dal_rtl8367d_l2_aging_set(rtk_l2_age_time_t aging_time) +{ + rtk_api_ret_t retVal; + + if(aging_time > RTL8367D_LUTAGINGTIMER_MAX) + return RT_ERR_OUT_OF_RANGE; + + if((retVal = rtl8367d_setAsicReg(RTL8367D_REG_LUT_CFG2, aging_time * 10)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_l2_aging_get + * Description: + * Get LUT agging out time + * Input: + * None + * Output: + * pEnable - Aging status + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get LUT agging out period for each entry. + */ +rtk_api_ret_t dal_rtl8367d_l2_aging_get(rtk_l2_age_time_t *pAging_time) +{ + rtk_api_ret_t retVal; + rtk_uint32 pAge; + + if((retVal = rtl8367d_getAsicReg(RTL8367D_REG_LUT_CFG2, &pAge)) != RT_ERR_OK) + return retVal; + + *pAging_time = pAge / 10; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_l2_ipMcastAddrLookup_set + * Description: + * Set Lut IP multicast lookup function + * Input: + * type - Lookup type for IPMC packet. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * LOOKUP_MAC - Lookup by MAC address + * LOOKUP_IP - Lookup by IP address + */ +rtk_api_ret_t dal_rtl8367d_l2_ipMcastAddrLookup_set(rtk_l2_ipmc_lookup_type_t type) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(type == LOOKUP_MAC) + { + if((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_LUT_CFG, RTL8367D_LUT_IPMC_HASH_OFFSET, DISABLED)) != RT_ERR_OK) + return retVal; + } + else if(type == LOOKUP_IP) + { + if((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_LUT_CFG, RTL8367D_LUT_IPMC_HASH_OFFSET, ENABLED)) != RT_ERR_OK) + return retVal; + } + else + return RT_ERR_INPUT; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_l2_ipMcastAddrLookup_get + * Description: + * Get Lut IP multicast lookup function + * Input: + * None. + * Output: + * pType - Lookup type for IPMC packet. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * None. + */ +rtk_api_ret_t dal_rtl8367d_l2_ipMcastAddrLookup_get(rtk_l2_ipmc_lookup_type_t *pType) +{ + rtk_api_ret_t retVal; + rtk_uint32 enabled; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pType) + return RT_ERR_NULL_POINTER; + + if((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_LUT_CFG, RTL8367D_LUT_IPMC_HASH_OFFSET, &enabled)) != RT_ERR_OK) + return retVal; + + if(enabled == ENABLED) + *pType = LOOKUP_IP; + else + *pType = LOOKUP_MAC; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_l2_ipMcastGroupEntry_add + * Description: + * Add an IP Multicast entry to group table + * Input: + * ip_addr - IP address + * vid - VLAN ID + * pPortmask - portmask + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_TBL_FULL - Table Full + * Note: + * Add an entry to IP Multicast Group table. + */ +rtk_api_ret_t dal_rtl8367d_l2_ipMcastGroupEntry_add(ipaddr_t ip_addr, rtk_uint32 vid, rtk_portmask_t *pPortmask) +{ + rtk_uint32 empty_idx = 0xFFFF; + rtk_int32 index; + ipaddr_t group_addr; + rtk_uint32 pmask; + rtk_uint32 valid; + rtk_uint32 physicalPortmask; + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(vid)//remove warning + { + } + + if(NULL == pPortmask) + return RT_ERR_NULL_POINTER; + + if((ip_addr & 0xF0000000) != 0xE0000000) + return RT_ERR_INPUT; + + /* Get Physical port mask */ + if ((retVal = rtk_switch_portmask_L2P_get(pPortmask, &physicalPortmask))!=RT_ERR_OK) + return retVal; + + for(index = 0; index <= RTL8367D_LUT_IPMCGRP_TABLE_MAX; index++) + { + if ((retVal = _rtl8367d_getLutIPMCGroup((rtk_uint32)index, &group_addr, &pmask, &valid))!=RT_ERR_OK) + return retVal; + + if( (valid == ENABLED) && (group_addr == ip_addr)) + { + if(pmask != physicalPortmask) + { + pmask = physicalPortmask; + if ((retVal = _rtl8367d_setLutIPMCGroup(index, ip_addr, pmask, valid))!=RT_ERR_OK) + return retVal; + } + + return RT_ERR_OK; + } + + if( (valid == DISABLED) && (empty_idx == 0xFFFF) ) /* Unused */ + empty_idx = (rtk_uint32)index; + } + + if(empty_idx == 0xFFFF) + return RT_ERR_TBL_FULL; + + pmask = physicalPortmask; + if ((retVal = _rtl8367d_setLutIPMCGroup(empty_idx, ip_addr, pmask, ENABLED))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_l2_ipMcastGroupEntry_del + * Description: + * Delete an entry from IP Multicast group table + * Input: + * ip_addr - IP address + * vid - VLAN ID + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_TBL_FULL - Table Full + * Note: + * Delete an entry from IP Multicast group table. + */ +rtk_api_ret_t dal_rtl8367d_l2_ipMcastGroupEntry_del(ipaddr_t ip_addr, rtk_uint32 vid) +{ + rtk_int32 index; + ipaddr_t group_addr; + rtk_uint32 pmask; + rtk_uint32 valid; + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(vid)//remove warning + { + } + + if((ip_addr & 0xF0000000) != 0xE0000000) + return RT_ERR_INPUT; + + for(index = 0; index <= RTL8367D_LUT_IPMCGRP_TABLE_MAX; index++) + { + if ((retVal = _rtl8367d_getLutIPMCGroup((rtk_uint32)index, &group_addr, &pmask, &valid))!=RT_ERR_OK) + return retVal; + + if( (valid == ENABLED) && (group_addr == ip_addr) ) + { + group_addr = 0xE0000000; + pmask = 0; + if ((retVal = _rtl8367d_setLutIPMCGroup(index, group_addr, pmask, DISABLED))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; + } + } + + return RT_ERR_FAILED; +} + +/* Function Name: + * dal_rtl8367d_l2_ipMcastGroupEntry_get + * Description: + * get an entry from IP Multicast group table + * Input: + * ip_addr - IP address + * vid - VLAN ID + * Output: + * pPortmask - member port mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_TBL_FULL - Table Full + * Note: + * Delete an entry from IP Multicast group table. + */ +rtk_api_ret_t dal_rtl8367d_l2_ipMcastGroupEntry_get(ipaddr_t ip_addr, rtk_uint32 vid, rtk_portmask_t *pPortmask) +{ + rtk_int32 index; + ipaddr_t group_addr; + rtk_uint32 valid; + rtk_uint32 pmask; + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(vid)//remove warning + { + } + + if((ip_addr & 0xF0000000) != 0xE0000000) + return RT_ERR_INPUT; + + if(NULL == pPortmask) + return RT_ERR_NULL_POINTER; + + for(index = 0; index <= RTL8367D_LUT_IPMCGRP_TABLE_MAX; index++) + { + if ((retVal = _rtl8367d_getLutIPMCGroup((rtk_uint32)index, &group_addr, &pmask, &valid))!=RT_ERR_OK) + return retVal; + + if( (valid == ENABLED) && (group_addr == ip_addr) ) + { + if ((retVal = rtk_switch_portmask_P2L_get(pmask, pPortmask))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; + } + } + + return RT_ERR_FAILED; +} + +/* Function Name: + * dal_rtl8367d_l2_entry_get + * Description: + * Get LUT unicast entry. + * Input: + * pL2_entry - Index field in the structure. + * Output: + * pL2_entry - other fields such as MAC, port, age... + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_EMPTY_ENTRY - Empty LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API is used to get address by index from 0~2111. + */ +rtk_api_ret_t dal_rtl8367d_l2_entry_get(rtk_l2_addr_table_t *pL2_entry) +{ + rtk_api_ret_t retVal; + rtk_uint32 method; + rtl8367d_luttb l2Table; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (pL2_entry->index >= rtk_switch_maxLutAddrNumber_get()) + return RT_ERR_INPUT; + + memset(&l2Table, 0x00, sizeof(rtl8367d_luttb)); + l2Table.address= pL2_entry->index; + method = RTL8367D_LUTREADMETHOD_ADDRESS; + if ((retVal = _rtl8367d_getL2LookupTb(method, &l2Table)) != RT_ERR_OK) + return retVal; + + if ((pL2_entry->index>0x800)&&(l2Table.lookup_hit==0)) + return RT_ERR_L2_EMPTY_ENTRY; + + if(l2Table.l3lookup) + { + memset(&pL2_entry->mac, 0, sizeof(rtk_mac_t)); + pL2_entry->is_ipmul = l2Table.l3lookup; + pL2_entry->sip = l2Table.sip; + pL2_entry->dip = l2Table.dip; + pL2_entry->is_static = l2Table.nosalearn; + + /* Get Logical port mask */ + if ((retVal = rtk_switch_portmask_P2L_get(l2Table.mbr, &(pL2_entry->portmask)))!=RT_ERR_OK) + return retVal; + + pL2_entry->fid = 0; + pL2_entry->age = 0; + pL2_entry->sa_block = 0; + pL2_entry->is_ipvidmul = 0; + pL2_entry->l3_vid = 0; + + } + else if(l2Table.mac.octet[0]&0x01) + { + memset(&pL2_entry->sip, 0, sizeof(ipaddr_t)); + memset(&pL2_entry->dip, 0, sizeof(ipaddr_t)); + pL2_entry->mac.octet[0] = l2Table.mac.octet[0]; + pL2_entry->mac.octet[1] = l2Table.mac.octet[1]; + pL2_entry->mac.octet[2] = l2Table.mac.octet[2]; + pL2_entry->mac.octet[3] = l2Table.mac.octet[3]; + pL2_entry->mac.octet[4] = l2Table.mac.octet[4]; + pL2_entry->mac.octet[5] = l2Table.mac.octet[5]; + pL2_entry->is_ipmul = l2Table.l3lookup; + pL2_entry->is_static = l2Table.nosalearn; + + /* Get Logical port mask */ + if ((retVal = rtk_switch_portmask_P2L_get(l2Table.mbr, &(pL2_entry->portmask)))!=RT_ERR_OK) + return retVal; + + pL2_entry->ivl = l2Table.ivl_svl; + if(l2Table.ivl_svl == 1) /* IVL */ + { + pL2_entry->cvid = l2Table.cvid_fid; + pL2_entry->fid = 0; + } + else /* SVL*/ + { + pL2_entry->cvid = 0; + pL2_entry->fid = l2Table.cvid_fid; + } + pL2_entry->age = 0; + pL2_entry->is_ipvidmul = 0; + pL2_entry->l3_vid = 0; + } + else if((l2Table.age != 0)||(l2Table.nosalearn == 1)) + { + memset(&pL2_entry->sip, 0, sizeof(ipaddr_t)); + memset(&pL2_entry->dip, 0, sizeof(ipaddr_t)); + pL2_entry->mac.octet[0] = l2Table.mac.octet[0]; + pL2_entry->mac.octet[1] = l2Table.mac.octet[1]; + pL2_entry->mac.octet[2] = l2Table.mac.octet[2]; + pL2_entry->mac.octet[3] = l2Table.mac.octet[3]; + pL2_entry->mac.octet[4] = l2Table.mac.octet[4]; + pL2_entry->mac.octet[5] = l2Table.mac.octet[5]; + pL2_entry->is_ipmul = l2Table.l3lookup; + pL2_entry->is_static = l2Table.nosalearn; + + /* Get Logical port mask */ + if ((retVal = rtk_switch_portmask_P2L_get(1<<(l2Table.spa), &(pL2_entry->portmask)))!=RT_ERR_OK) + return retVal; + + pL2_entry->ivl = l2Table.ivl_svl; + if(l2Table.ivl_svl == 1) /* IVL */ + { + pL2_entry->cvid = l2Table.cvid_fid; + pL2_entry->fid = 0; + } + else /* SVL*/ + { + pL2_entry->cvid = 0; + pL2_entry->fid = l2Table.cvid_fid; + } + + pL2_entry->age = l2Table.age; + pL2_entry->is_ipvidmul = 0; + pL2_entry->l3_vid = 0; + } + else + return RT_ERR_L2_EMPTY_ENTRY; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_l2_lookupHitIsolationAction_set + * Description: + * Set action of lookup hit & isolation. + * Input: + * action - The action + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API is used to configure the action of packet which is lookup hit + * in L2 table but the destination port/portmask are not in the port isolation + * group. + */ +rtk_api_ret_t dal_rtl8367d_l2_lookupHitIsolationAction_set(rtk_l2_lookupHitIsolationAction_t action) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + switch (action) + { + case L2_LOOKUPHIT_ISOACTION_NOP: + regData = 0; + break; + case L2_LOOKUPHIT_ISOACTION_UNKNOWN: + regData = 1; + break; + default: + return RT_ERR_INPUT; + } + + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_LOOKUP_HIT_ISO_ACT, RTL8367D_LOOKUP_HIT_ISO_ACT_OFFSET, regData)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_l2_lookupHitIsolationAction_get + * Description: + * Get action of lookup hit & isolation. + * Input: + * None. + * Output: + * pAction - The action + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API is used to get the action of packet which is lookup hit + * in L2 table but the destination port/portmask are not in the port isolation + * group. + */ +rtk_api_ret_t dal_rtl8367d_l2_lookupHitIsolationAction_get(rtk_l2_lookupHitIsolationAction_t *pAction) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (pAction == NULL) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_LOOKUP_HIT_ISO_ACT, RTL8367D_LOOKUP_HIT_ISO_ACT_OFFSET, ®Data)) != RT_ERR_OK) + return retVal; + + switch (regData) + { + case 0: + *pAction = L2_LOOKUPHIT_ISOACTION_NOP; + break; + case 1: + *pAction = L2_LOOKUPHIT_ISOACTION_UNKNOWN; + break; + default: + return RT_ERR_FAILED; + } + + return RT_ERR_OK; +} diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_l2.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_l2.h new file mode 100644 index 00000000..2c65062e --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_l2.h @@ -0,0 +1,1011 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8367/RTL8367D switch high-level API + * + * Feature : The file includes L2 module high-layer API defination + * + */ + +#ifndef __DAL_RTL8367D_L2_H__ +#define __DAL_RTL8367D_L2_H__ + +#include + +/* + * Data Type Declaration + */ +#define RTK_MAX_NUM_OF_LEARN_LIMIT (rtk_switch_maxLutAddrNumber_get()) + +#define RTK_MAC_ADDR_LEN 6 +#define RTK_MAX_LUT_ADDRESS (RTK_MAX_NUM_OF_LEARN_LIMIT) +#define RTK_MAX_LUT_ADDR_ID (RTK_MAX_LUT_ADDRESS - 1) + +#define RTL8367D_LUT_IPMCGRP_TABLE_MAX (0x3F) + +#define RTL8367D_LUT_BUSY_CHECK_NO (10) + +#define RTL8367D_LUT_TABLE_SIZE (5) + +#define RTL8367D_LUTREADMETHOD_MAC 0 +#define RTL8367D_LUTREADMETHOD_ADDRESS 1 +#define RTL8367D_LUTREADMETHOD_NEXT_ADDRESS 2 +#define RTL8367D_LUTREADMETHOD_NEXT_L2UC 3 +#define RTL8367D_LUTREADMETHOD_NEXT_L2MC 4 +#define RTL8367D_LUTREADMETHOD_NEXT_L3MC 5 +#define RTL8367D_LUTREADMETHOD_NEXT_L2L3MC 6 +#define RTL8367D_LUTREADMETHOD_NEXT_L2UCSPA 7 + + +#define RTL8367D_FLUSHMDOE_PORT 0 +#define RTL8367D_FLUSHMDOE_VID 1 +#define RTL8367D_FLUSHMDOE_FID 2 +#define RTL8367D_FLUSHMDOE_END 3 + +#define RTL8367D_FLUSHTYPE_DYNAMIC 0 +#define RTL8367D_FLUSHTYPE_BOTH 1 +#define RTL8367D_FLUSHTYPE_END 2 + +#define RTL8367D_LUTAGINGTIMER_MAX (0xFFFF/10) + +typedef struct LUTTABLE{ + + ipaddr_t sip; + ipaddr_t dip; + ether_addr_t mac; + rtk_uint16 ivl_svl; + rtk_uint16 cvid_fid; + rtk_uint16 nosalearn; + rtk_uint16 mbr; + rtk_uint16 spa; + rtk_uint16 age; + rtk_uint16 l3lookup; + + rtk_uint16 lookup_hit; + rtk_uint16 lookup_busy; + rtk_uint16 address; + rtk_uint16 wait_time; + +}rtl8367d_luttb; + +/* Function Name: + * dal_rtl8367d_l2_init + * Description: + * Initialize l2 module of the specified device. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * Initialize l2 module before calling any l2 APIs. + */ +extern rtk_api_ret_t dal_rtl8367d_l2_init(void); + +/* Function Name: + * dal_rtl8367d_l2_addr_add + * Description: + * Add LUT unicast entry. + * Input: + * pMac - 6 bytes unicast(I/G bit is 0) mac address to be written into LUT. + * pL2_data - Unicast entry parameter + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_L2_FID - Invalid FID . + * RT_ERR_L2_INDEXTBL_FULL - hashed index is full of entries. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * If the unicast mac address already existed in LUT, it will udpate the status of the entry. + * Otherwise, it will find an empty or asic auto learned entry to write. If all the entries + * with the same hash value can't be replaced, ASIC will return a RT_ERR_L2_INDEXTBL_FULL error. + */ +extern rtk_api_ret_t dal_rtl8367d_l2_addr_add(rtk_mac_t *pMac, rtk_l2_ucastAddr_t *pL2_data); + +/* Function Name: + * dal_rtl8367d_l2_addr_get + * Description: + * Get LUT unicast entry. + * Input: + * pMac - 6 bytes unicast(I/G bit is 0) mac address to be written into LUT. + * Output: + * pL2_data - Unicast entry parameter + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_L2_FID - Invalid FID . + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * If the unicast mac address existed in LUT, it will return the port and fid where + * the mac is learned. Otherwise, it will return a RT_ERR_L2_ENTRY_NOTFOUND error. + */ +extern rtk_api_ret_t dal_rtl8367d_l2_addr_get(rtk_mac_t *pMac, rtk_l2_ucastAddr_t *pL2_data); + +/* Function Name: + * dal_rtl8367d_l2_addr_next_get + * Description: + * Get Next LUT unicast entry. + * Input: + * read_method - The reading method. + * port - The port number if the read_metohd is READMETHOD_NEXT_L2UCSPA + * pAddress - The Address ID + * Output: + * pL2_data - Unicast entry parameter + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_L2_FID - Invalid FID . + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * Get the next unicast entry after the current entry pointed by pAddress. + * The address of next entry is returned by pAddress. User can use (address + 1) + * as pAddress to call this API again for dumping all entries is LUT. + */ +extern rtk_api_ret_t dal_rtl8367d_l2_addr_next_get(rtk_l2_read_method_t read_method, rtk_port_t port, rtk_uint32 *pAddress, rtk_l2_ucastAddr_t *pL2_data); + +/* Function Name: + * dal_rtl8367d_l2_addr_del + * Description: + * Delete LUT unicast entry. + * Input: + * pMac - 6 bytes unicast(I/G bit is 0) mac address to be written into LUT. + * fid - Filtering database + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_L2_FID - Invalid FID . + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * If the mac has existed in the LUT, it will be deleted. Otherwise, it will return RT_ERR_L2_ENTRY_NOTFOUND. + */ +extern rtk_api_ret_t dal_rtl8367d_l2_addr_del(rtk_mac_t *pMac, rtk_l2_ucastAddr_t *pL2_data); + +/* Function Name: + * dal_rtl8367d_l2_mcastAddr_add + * Description: + * Add LUT multicast entry. + * Input: + * pMcastAddr - L2 multicast entry structure + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_L2_FID - Invalid FID . + * RT_ERR_L2_VID - Invalid VID . + * RT_ERR_L2_INDEXTBL_FULL - hashed index is full of entries. + * RT_ERR_PORT_MASK - Invalid portmask. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * If the multicast mac address already existed in the LUT, it will udpate the + * port mask of the entry. Otherwise, it will find an empty or asic auto learned + * entry to write. If all the entries with the same hash value can't be replaced, + * ASIC will return a RT_ERR_L2_INDEXTBL_FULL error. + */ +extern rtk_api_ret_t dal_rtl8367d_l2_mcastAddr_add(rtk_l2_mcastAddr_t *pMcastAddr); + +/* Function Name: + * dal_rtl8367d_l2_mcastAddr_get + * Description: + * Get LUT multicast entry. + * Input: + * pMcastAddr - L2 multicast entry structure + * Output: + * pMcastAddr - L2 multicast entry structure + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_L2_FID - Invalid FID . + * RT_ERR_L2_VID - Invalid VID . + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * If the multicast mac address existed in the LUT, it will return the port where + * the mac is learned. Otherwise, it will return a RT_ERR_L2_ENTRY_NOTFOUND error. + */ +extern rtk_api_ret_t dal_rtl8367d_l2_mcastAddr_get(rtk_l2_mcastAddr_t *pMcastAddr); + +/* Function Name: + * dal_rtl8367d_l2_mcastAddr_next_get + * Description: + * Get Next L2 Multicast entry. + * Input: + * pAddress - The Address ID + * Output: + * pMcastAddr - L2 multicast entry structure + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * Get the next L2 multicast entry after the current entry pointed by pAddress. + * The address of next entry is returned by pAddress. User can use (address + 1) + * as pAddress to call this API again for dumping all multicast entries is LUT. + */ +extern rtk_api_ret_t dal_rtl8367d_l2_mcastAddr_next_get(rtk_uint32 *pAddress, rtk_l2_mcastAddr_t *pMcastAddr); + +/* Function Name: + * dal_rtl8367d_l2_mcastAddr_del + * Description: + * Delete LUT multicast entry. + * Input: + * pMcastAddr - L2 multicast entry structure + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_L2_FID - Invalid FID . + * RT_ERR_L2_VID - Invalid VID . + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * If the mac has existed in the LUT, it will be deleted. Otherwise, it will return RT_ERR_L2_ENTRY_NOTFOUND. + */ +extern rtk_api_ret_t dal_rtl8367d_l2_mcastAddr_del(rtk_l2_mcastAddr_t *pMcastAddr); + +/* Function Name: + * dal_rtl8367d_l2_ipMcastAddr_add + * Description: + * Add Lut IP multicast entry + * Input: + * pIpMcastAddr - IP Multicast entry + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_L2_INDEXTBL_FULL - hashed index is full of entries. + * RT_ERR_PORT_MASK - Invalid portmask. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * System supports L2 entry with IP multicast DIP/SIP to forward IP multicasting frame as user + * desired. If this function is enabled, then system will be looked up L2 IP multicast entry to + * forward IP multicast frame directly without flooding. + */ +extern rtk_api_ret_t dal_rtl8367d_l2_ipMcastAddr_add(rtk_l2_ipMcastAddr_t *pIpMcastAddr); + +/* Function Name: + * dal_rtl8367d_l2_ipMcastAddr_get + * Description: + * Get LUT IP multicast entry. + * Input: + * pIpMcastAddr - IP Multicast entry + * Output: + * pIpMcastAddr - IP Multicast entry + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get Lut table of IP multicast entry. + */ +extern rtk_api_ret_t dal_rtl8367d_l2_ipMcastAddr_get(rtk_l2_ipMcastAddr_t *pIpMcastAddr); + +/* Function Name: + * dal_rtl8367d_l2_ipMcastAddr_next_get + * Description: + * Get Next IP Multicast entry. + * Input: + * pAddress - The Address ID + * Output: + * pIpMcastAddr - IP Multicast entry + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * Get the next IP multicast entry after the current entry pointed by pAddress. + * The address of next entry is returned by pAddress. User can use (address + 1) + * as pAddress to call this API again for dumping all IP multicast entries is LUT. + */ +extern rtk_api_ret_t dal_rtl8367d_l2_ipMcastAddr_next_get(rtk_uint32 *pAddress, rtk_l2_ipMcastAddr_t *pIpMcastAddr); + +/* Function Name: + * dal_rtl8367d_l2_ipMcastAddr_del + * Description: + * Delete a ip multicast address entry from the specified device. + * Input: + * pIpMcastAddr - IP Multicast entry + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can delete a IP multicast address entry from the specified device. + */ +extern rtk_api_ret_t dal_rtl8367d_l2_ipMcastAddr_del(rtk_l2_ipMcastAddr_t *pIpMcastAddr); + +/* Function Name: + * dal_rtl8367d_l2_ucastAddr_flush + * Description: + * Flush L2 mac address by type in the specified device (both dynamic and static). + * Input: + * pConfig - flush configuration + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * flushByVid - 1: Flush by VID, 0: Don't flush by VID + * vid - VID (0 ~ 4095) + * flushByFid - 1: Flush by FID, 0: Don't flush by FID + * fid - FID (0 ~ 15) + * flushByPort - 1: Flush by Port, 0: Don't flush by Port + * port - Port ID + * flushByMac - Not Supported + * ucastAddr - Not Supported + * flushStaticAddr - 1: Flush both Static and Dynamic entries, 0: Flush only Dynamic entries + * flushAddrOnAllPorts - 1: Flush VID-matched entries at all ports, 0: Flush VID-matched entries per port. + */ +extern rtk_api_ret_t dal_rtl8367d_l2_ucastAddr_flush(rtk_l2_flushCfg_t *pConfig); + +/* Function Name: + * dal_rtl8367d_l2_table_clear + * Description: + * Flush all static & dynamic entries in LUT. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367d_l2_table_clear(void); + +/* Function Name: + * dal_rtl8367d_l2_table_clearStatus_get + * Description: + * Get table clear status + * Input: + * None + * Output: + * pStatus - Clear status, 1:Busy, 0:finish + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367d_l2_table_clearStatus_get(rtk_l2_clearStatus_t *pStatus); + +/* Function Name: + * dal_rtl8367d_l2_flushLinkDownPortAddrEnable_set + * Description: + * Set HW flush linkdown port mac configuration of the specified device. + * Input: + * port - Port id. + * enable - link down flush status + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * The status of flush linkdown port address is as following: + * - DISABLED + * - ENABLED + */ +extern rtk_api_ret_t dal_rtl8367d_l2_flushLinkDownPortAddrEnable_set(rtk_port_t port, rtk_enable_t enable); + +/* Function Name: + * dal_rtl8367d_l2_flushLinkDownPortAddrEnable_get + * Description: + * Get HW flush linkdown port mac configuration of the specified device. + * Input: + * port - Port id. + * Output: + * pEnable - link down flush status + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The status of flush linkdown port address is as following: + * - DISABLED + * - ENABLED + */ +extern rtk_api_ret_t dal_rtl8367d_l2_flushLinkDownPortAddrEnable_get(rtk_port_t port, rtk_enable_t *pEnable); + +/* Function Name: + * dal_rtl8367d_l2_agingEnable_set + * Description: + * Set L2 LUT aging status per port setting. + * Input: + * port - Port id. + * enable - Aging status + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * This API can be used to set L2 LUT aging status per port. + */ +extern rtk_api_ret_t dal_rtl8367d_l2_agingEnable_set(rtk_port_t port, rtk_enable_t enable); + +/* Function Name: + * dal_rtl8367d_l2_agingEnable_get + * Description: + * Get L2 LUT aging status per port setting. + * Input: + * port - Port id. + * Output: + * pEnable - Aging status + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can be used to get L2 LUT aging function per port. + */ +extern rtk_api_ret_t dal_rtl8367d_l2_agingEnable_get(rtk_port_t port, rtk_enable_t *pEnable); + +/* Function Name: + * dal_rtl8367d_l2_limitLearningCnt_set + * Description: + * Set per-Port auto learning limit number + * Input: + * port - Port id. + * mac_cnt - Auto learning entries limit number + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_LIMITED_L2ENTRY_NUM - Invalid auto learning limit number + * Note: + * The API can set per-port ASIC auto learning limit number from 0(disable learning) + * to 8k. + */ +extern rtk_api_ret_t dal_rtl8367d_l2_limitLearningCnt_set(rtk_port_t port, rtk_mac_cnt_t mac_cnt); + +/* Function Name: + * dal_rtl8367d_l2_limitLearningCnt_get + * Description: + * Get per-Port auto learning limit number + * Input: + * port - Port id. + * Output: + * pMac_cnt - Auto learning entries limit number + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get per-port ASIC auto learning limit number. + */ +extern rtk_api_ret_t dal_rtl8367d_l2_limitLearningCnt_get(rtk_port_t port, rtk_mac_cnt_t *pMac_cnt); + +/* Function Name: + * dal_rtl8367d_l2_limitSystemLearningCnt_set + * Description: + * Set System auto learning limit number + * Input: + * mac_cnt - Auto learning entries limit number + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_LIMITED_L2ENTRY_NUM - Invalid auto learning limit number + * Note: + * The API can set system ASIC auto learning limit number from 0(disable learning) + * to 2112. + */ +extern rtk_api_ret_t dal_rtl8367d_l2_limitSystemLearningCnt_set(rtk_mac_cnt_t mac_cnt); + +/* Function Name: + * dal_rtl8367d_l2_limitSystemLearningCnt_get + * Description: + * Get System auto learning limit number + * Input: + * None + * Output: + * pMac_cnt - Auto learning entries limit number + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get system ASIC auto learning limit number. + */ +extern rtk_api_ret_t dal_rtl8367d_l2_limitSystemLearningCnt_get(rtk_mac_cnt_t *pMac_cnt); + +/* Function Name: + * dal_rtl8367d_l2_limitLearningCntAction_set + * Description: + * Configure auto learn over limit number action. + * Input: + * port - Port id. + * action - Auto learning entries limit number + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_NOT_ALLOWED - Invalid learn over action + * Note: + * The API can set SA unknown packet action while auto learn limit number is over + * The action symbol as following: + * - LIMIT_LEARN_CNT_ACTION_DROP, + * - LIMIT_LEARN_CNT_ACTION_FORWARD, + * - LIMIT_LEARN_CNT_ACTION_TO_CPU, + */ +extern rtk_api_ret_t dal_rtl8367d_l2_limitLearningCntAction_set(rtk_port_t port, rtk_l2_limitLearnCntAction_t action); + +/* Function Name: + * dal_rtl8367d_l2_limitLearningCntAction_get + * Description: + * Get auto learn over limit number action. + * Input: + * port - Port id. + * Output: + * pAction - Learn over action + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get SA unknown packet action while auto learn limit number is over + * The action symbol as following: + * - LIMIT_LEARN_CNT_ACTION_DROP, + * - LIMIT_LEARN_CNT_ACTION_FORWARD, + * - LIMIT_LEARN_CNT_ACTION_TO_CPU, + */ +extern rtk_api_ret_t dal_rtl8367d_l2_limitLearningCntAction_get(rtk_port_t port, rtk_l2_limitLearnCntAction_t *pAction); + +/* Function Name: + * dal_rtl8367d_l2_limitSystemLearningCntAction_set + * Description: + * Configure system auto learn over limit number action. + * Input: + * port - Port id. + * action - Auto learning entries limit number + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_NOT_ALLOWED - Invalid learn over action + * Note: + * The API can set SA unknown packet action while auto learn limit number is over + * The action symbol as following: + * - LIMIT_LEARN_CNT_ACTION_DROP, + * - LIMIT_LEARN_CNT_ACTION_FORWARD, + * - LIMIT_LEARN_CNT_ACTION_TO_CPU, + */ +extern rtk_api_ret_t dal_rtl8367d_l2_limitSystemLearningCntAction_set(rtk_l2_limitLearnCntAction_t action); + +/* Function Name: + * dal_rtl8367d_l2_limitSystemLearningCntAction_get + * Description: + * Get system auto learn over limit number action. + * Input: + * None. + * Output: + * pAction - Learn over action + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get SA unknown packet action while auto learn limit number is over + * The action symbol as following: + * - LIMIT_LEARN_CNT_ACTION_DROP, + * - LIMIT_LEARN_CNT_ACTION_FORWARD, + * - LIMIT_LEARN_CNT_ACTION_TO_CPU, + */ +extern rtk_api_ret_t dal_rtl8367d_l2_limitSystemLearningCntAction_get(rtk_l2_limitLearnCntAction_t *pAction); + +/* Function Name: + * dal_rtl8367d_l2_limitSystemLearningCntPortMask_set + * Description: + * Configure system auto learn portmask + * Input: + * pPortmask - Port Mask + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Invalid port mask. + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367d_l2_limitSystemLearningCntPortMask_set(rtk_portmask_t *pPortmask); + +/* Function Name: + * dal_rtl8367d_l2_limitSystemLearningCntPortMask_get + * Description: + * get system auto learn portmask + * Input: + * None + * Output: + * pPortmask - Port Mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Null pointer. + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367d_l2_limitSystemLearningCntPortMask_get(rtk_portmask_t *pPortmask); + +/* Function Name: + * dal_rtl8367d_l2_learningCnt_get + * Description: + * Get per-Port current auto learning number + * Input: + * port - Port id. + * Output: + * pMac_cnt - ASIC auto learning entries number + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get per-port ASIC auto learning number + */ +extern rtk_api_ret_t dal_rtl8367d_l2_learningCnt_get(rtk_port_t port, rtk_mac_cnt_t *pMac_cnt); + +/* Function Name: + * dal_rtl8367d_l2_floodPortMask_set + * Description: + * Set flooding portmask + * Input: + * type - flooding type. + * pFlood_portmask - flooding porkmask + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Invalid portmask. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can set the flooding mask. + * The flooding type is as following: + * - FLOOD_UNKNOWNDA + * - FLOOD_UNKNOWNMC + * - FLOOD_BC + */ +extern rtk_api_ret_t dal_rtl8367d_l2_floodPortMask_set(rtk_l2_flood_type_t floood_type, rtk_portmask_t *pFlood_portmask); + +/* Function Name: + * dal_rtl8367d_l2_floodPortMask_get + * Description: + * Get flooding portmask + * Input: + * type - flooding type. + * Output: + * pFlood_portmask - flooding porkmask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can get the flooding mask. + * The flooding type is as following: + * - FLOOD_UNKNOWNDA + * - FLOOD_UNKNOWNMC + * - FLOOD_BC + */ +extern rtk_api_ret_t dal_rtl8367d_l2_floodPortMask_get(rtk_l2_flood_type_t floood_type, rtk_portmask_t *pFlood_portmask); + +/* Function Name: + * dal_rtl8367d_l2_localPktPermit_set + * Description: + * Set permittion of frames if source port and destination port are the same. + * Input: + * port - Port id. + * permit - permittion status + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid permit value. + * Note: + * This API is setted to permit frame if its source port is equal to destination port. + */ +extern rtk_api_ret_t dal_rtl8367d_l2_localPktPermit_set(rtk_port_t port, rtk_enable_t permit); + +/* Function Name: + * dal_rtl8367d_l2_localPktPermit_get + * Description: + * Get permittion of frames if source port and destination port are the same. + * Input: + * port - Port id. + * Output: + * pPermit - permittion status + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API is to get permittion status for frames if its source port is equal to destination port. + */ +extern rtk_api_ret_t dal_rtl8367d_l2_localPktPermit_get(rtk_port_t port, rtk_enable_t *pPermit); + +/* Function Name: + * dal_rtl8367d_l2_aging_set + * Description: + * Set LUT agging out speed + * Input: + * aging_time - Agging out time. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - input out of range. + * Note: + * The API can set LUT agging out period for each entry and the range is from 14s to 800s. + */ +extern rtk_api_ret_t dal_rtl8367d_l2_aging_set(rtk_l2_age_time_t aging_time); + +/* Function Name: + * dal_rtl8367d_l2_aging_get + * Description: + * Get LUT agging out time + * Input: + * None + * Output: + * pEnable - Aging status + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get LUT agging out period for each entry. + */ +extern rtk_api_ret_t dal_rtl8367d_l2_aging_get(rtk_l2_age_time_t *pAging_time); + +/* Function Name: + * dal_rtl8367d_l2_ipMcastAddrLookup_set + * Description: + * Set Lut IP multicast lookup function + * Input: + * type - Lookup type for IPMC packet. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API can work with rtk_l2_ipMcastAddrLookupException_add. + * If users set the lookup type to DIP, the group in exception table + * will be lookup by DIP+SIP + * If users set the lookup type to DIP+SIP, the group in exception table + * will be lookup by only DIP + */ +extern rtk_api_ret_t dal_rtl8367d_l2_ipMcastAddrLookup_set(rtk_l2_ipmc_lookup_type_t type); + +/* Function Name: + * dal_rtl8367d_l2_ipMcastAddrLookup_get + * Description: + * Get Lut IP multicast lookup function + * Input: + * None. + * Output: + * pType - Lookup type for IPMC packet. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * None. + */ +extern rtk_api_ret_t dal_rtl8367d_l2_ipMcastAddrLookup_get(rtk_l2_ipmc_lookup_type_t *pType); + +/* Function Name: + * dal_rtl8367d_l2_ipMcastGroupEntry_add + * Description: + * Add an IP Multicast entry to group table + * Input: + * ip_addr - IP address + * vid - VLAN ID + * pPortmask - portmask + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_TBL_FULL - Table Full + * Note: + * Add an entry to IP Multicast Group table. + */ +extern rtk_api_ret_t dal_rtl8367d_l2_ipMcastGroupEntry_add(ipaddr_t ip_addr, rtk_uint32 vid, rtk_portmask_t *pPortmask); + +/* Function Name: + * dal_rtl8367d_l2_ipMcastGroupEntry_del + * Description: + * Delete an entry from IP Multicast group table + * Input: + * ip_addr - IP address + * vid - VLAN ID + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_TBL_FULL - Table Full + * Note: + * Delete an entry from IP Multicast group table. + */ +extern rtk_api_ret_t dal_rtl8367d_l2_ipMcastGroupEntry_del(ipaddr_t ip_addr, rtk_uint32 vid); + +/* Function Name: + * dal_rtl8367d_l2_ipMcastGroupEntry_get + * Description: + * get an entry from IP Multicast group table + * Input: + * ip_addr - IP address + * vid - VLAN ID + * Output: + * pPortmask - member port mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_TBL_FULL - Table Full + * Note: + * Delete an entry from IP Multicast group table. + */ +extern rtk_api_ret_t dal_rtl8367d_l2_ipMcastGroupEntry_get(ipaddr_t ip_addr, rtk_uint32 vid, rtk_portmask_t *pPortmask); + +/* Function Name: + * dal_rtl8367d_l2_entry_get + * Description: + * Get LUT unicast entry. + * Input: + * pL2_entry - Index field in the structure. + * Output: + * pL2_entry - other fields such as MAC, port, age... + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_EMPTY_ENTRY - Empty LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API is used to get address by index from 0~2111. + */ +extern rtk_api_ret_t dal_rtl8367d_l2_entry_get(rtk_l2_addr_table_t *pL2_entry); + +/* Function Name: + * dal_rtl8367d_l2_lookupHitIsolationAction_set + * Description: + * Set action of lookup hit & isolation. + * Input: + * action - The action + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API is used to configure the action of packet which is lookup hit + * in L2 table but the destination port/portmask are not in the port isolation + * group. + */ +extern rtk_api_ret_t dal_rtl8367d_l2_lookupHitIsolationAction_set(rtk_l2_lookupHitIsolationAction_t action); + +/* Function Name: + * dal_rtl8367d_l2_lookupHitIsolationAction_get + * Description: + * Get action of lookup hit & isolation. + * Input: + * None. + * Output: + * pAction - The action + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API is used to get the action of packet which is lookup hit + * in L2 table but the destination port/portmask are not in the port isolation + * group. + */ +extern rtk_api_ret_t dal_rtl8367d_l2_lookupHitIsolationAction_get(rtk_l2_lookupHitIsolationAction_t *pAction); + + +#endif /* __DAL_RTL8367D_L2_H__ */ + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_leaky.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_leaky.c new file mode 100644 index 00000000..28b34030 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_leaky.c @@ -0,0 +1,566 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8367C + * Feature : Here is a list of all functions and variables in Leaky module. + * + */ + +#include +#include +#include +#include +#include + +/* Function Name: + * dal_rtl8367d_leaky_vlan_set + * Description: + * Set VLAN leaky. + * Input: + * type - Packet type for VLAN leaky. + * enable - Leaky status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_ENABLE - Invalid enable input + * Note: + * This API can set VLAN leaky for RMA ,IGMP/MLD, CDP, CSSTP, and LLDP packets. + * The leaky frame types are as following: + * - LEAKY_BRG_GROUP, + * - LEAKY_FD_PAUSE, + * - LEAKY_SP_MCAST, + * - LEAKY_1X_PAE, + * - LEAKY_UNDEF_BRG_04, + * - LEAKY_UNDEF_BRG_05, + * - LEAKY_UNDEF_BRG_06, + * - LEAKY_UNDEF_BRG_07, + * - LEAKY_PROVIDER_BRIDGE_GROUP_ADDRESS, + * - LEAKY_UNDEF_BRG_09, + * - LEAKY_UNDEF_BRG_0A, + * - LEAKY_UNDEF_BRG_0B, + * - LEAKY_UNDEF_BRG_0C, + * - LEAKY_PROVIDER_BRIDGE_GVRP_ADDRESS, + * - LEAKY_8021AB, + * - LEAKY_UNDEF_BRG_0F, + * - LEAKY_BRG_MNGEMENT, + * - LEAKY_UNDEFINED_11, + * - LEAKY_UNDEFINED_12, + * - LEAKY_UNDEFINED_13, + * - LEAKY_UNDEFINED_14, + * - LEAKY_UNDEFINED_15, + * - LEAKY_UNDEFINED_16, + * - LEAKY_UNDEFINED_17, + * - LEAKY_UNDEFINED_18, + * - LEAKY_UNDEFINED_19, + * - LEAKY_UNDEFINED_1A, + * - LEAKY_UNDEFINED_1B, + * - LEAKY_UNDEFINED_1C, + * - LEAKY_UNDEFINED_1D, + * - LEAKY_UNDEFINED_1E, + * - LEAKY_UNDEFINED_1F, + * - LEAKY_GMRP, + * - LEAKY_GVRP, + * - LEAKY_UNDEF_GARP_22, + * - LEAKY_UNDEF_GARP_23, + * - LEAKY_UNDEF_GARP_24, + * - LEAKY_UNDEF_GARP_25, + * - LEAKY_UNDEF_GARP_26, + * - LEAKY_UNDEF_GARP_27, + * - LEAKY_UNDEF_GARP_28, + * - LEAKY_UNDEF_GARP_29, + * - LEAKY_UNDEF_GARP_2A, + * - LEAKY_UNDEF_GARP_2B, + * - LEAKY_UNDEF_GARP_2C, + * - LEAKY_UNDEF_GARP_2D, + * - LEAKY_UNDEF_GARP_2E, + * - LEAKY_UNDEF_GARP_2F, + * - LEAKY_IGMP, + * - LEAKY_IPMULTICAST. + * - LEAKY_CDP, + * - LEAKY_CSSTP, + * - LEAKY_LLDP. + */ +rtk_api_ret_t dal_rtl8367d_leaky_vlan_set(rtk_leaky_type_t type, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + rtk_uint32 port; + rtk_uint32 index; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (type >= LEAKY_END) + return RT_ERR_INPUT; + + if (enable >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if( (type >= 0x4 && type <= 0x7) || (type >= 0x9 && type <= 0x0C) || (0x0F == type)) + index = 0x04; + else if((type >= 0x13 && type <= 0x17) || (0x19 == type) || (type >= 0x1B && type <= 0x1f)) + index = 0x13; + else if(type >= 0x22 && type <= 0x2F) + index = 0x22; + else + index = type; + + if (index <= LEAKY_UNDEF_GARP_2F) + { + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_RMA_CTRL00+index, RTL8367D_RMA_CTRL00_VLAN_LEAKY_OFFSET, enable)) != RT_ERR_OK) + return retVal; + } + else if (LEAKY_IPMULTICAST == index) + { + for (port = 0; port <= RTK_PORT_ID_MAX; port++) + { + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_IPMCAST_VLAN_LEAKY, port, enable)) != RT_ERR_OK) + return retVal; + } + } + else if (LEAKY_IGMP == index) + { + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_IGMP_MLD_CFG0, RTL8367D_IGMP_MLD_VLAN_LEAKY_OFFSET, enable)) != RT_ERR_OK) + return retVal; + } + else if (LEAKY_CDP == index) + { + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_RMA_CTRL_CDP, RTL8367D_RMA_CTRL_CDP_VLAN_LEAKY_OFFSET, enable)) != RT_ERR_OK) + return retVal; + } + else if (LEAKY_CSSTP == index) + { + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_RMA_CTRL_CSSTP, RTL8367D_RMA_CTRL_CSSTP_VLAN_LEAKY_OFFSET, enable)) != RT_ERR_OK) + return retVal; + } + else if (LEAKY_LLDP == index) + { + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_RMA_CTRL_LLDP, RTL8367D_RMA_CTRL_LLDP_VLAN_LEAKY_OFFSET, enable)) != RT_ERR_OK) + return retVal; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_leaky_vlan_get + * Description: + * Get VLAN leaky. + * Input: + * type - Packet type for VLAN leaky. + * Output: + * pEnable - Leaky status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can get VLAN leaky status for RMA ,IGMP/MLD, CDP, CSSTP, and LLDP packets. + * The leaky frame types are as following: + * - LEAKY_BRG_GROUP, + * - LEAKY_FD_PAUSE, + * - LEAKY_SP_MCAST, + * - LEAKY_1X_PAE, + * - LEAKY_UNDEF_BRG_04, + * - LEAKY_UNDEF_BRG_05, + * - LEAKY_UNDEF_BRG_06, + * - LEAKY_UNDEF_BRG_07, + * - LEAKY_PROVIDER_BRIDGE_GROUP_ADDRESS, + * - LEAKY_UNDEF_BRG_09, + * - LEAKY_UNDEF_BRG_0A, + * - LEAKY_UNDEF_BRG_0B, + * - LEAKY_UNDEF_BRG_0C, + * - LEAKY_PROVIDER_BRIDGE_GVRP_ADDRESS, + * - LEAKY_8021AB, + * - LEAKY_UNDEF_BRG_0F, + * - LEAKY_BRG_MNGEMENT, + * - LEAKY_UNDEFINED_11, + * - LEAKY_UNDEFINED_12, + * - LEAKY_UNDEFINED_13, + * - LEAKY_UNDEFINED_14, + * - LEAKY_UNDEFINED_15, + * - LEAKY_UNDEFINED_16, + * - LEAKY_UNDEFINED_17, + * - LEAKY_UNDEFINED_18, + * - LEAKY_UNDEFINED_19, + * - LEAKY_UNDEFINED_1A, + * - LEAKY_UNDEFINED_1B, + * - LEAKY_UNDEFINED_1C, + * - LEAKY_UNDEFINED_1D, + * - LEAKY_UNDEFINED_1E, + * - LEAKY_UNDEFINED_1F, + * - LEAKY_GMRP, + * - LEAKY_GVRP, + * - LEAKY_UNDEF_GARP_22, + * - LEAKY_UNDEF_GARP_23, + * - LEAKY_UNDEF_GARP_24, + * - LEAKY_UNDEF_GARP_25, + * - LEAKY_UNDEF_GARP_26, + * - LEAKY_UNDEF_GARP_27, + * - LEAKY_UNDEF_GARP_28, + * - LEAKY_UNDEF_GARP_29, + * - LEAKY_UNDEF_GARP_2A, + * - LEAKY_UNDEF_GARP_2B, + * - LEAKY_UNDEF_GARP_2C, + * - LEAKY_UNDEF_GARP_2D, + * - LEAKY_UNDEF_GARP_2E, + * - LEAKY_UNDEF_GARP_2F, + * - LEAKY_IGMP, + * - LEAKY_IPMULTICAST. + * - LEAKY_CDP, + * - LEAKY_CSSTP, + * - LEAKY_LLDP. + */ +rtk_api_ret_t dal_rtl8367d_leaky_vlan_get(rtk_leaky_type_t type, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + rtk_uint32 port,tmp, index; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (type >= LEAKY_END) + return RT_ERR_INPUT; + + if(NULL == pEnable) + return RT_ERR_NULL_POINTER; + + if( (type >= 0x4 && type <= 0x7) || (type >= 0x9 && type <= 0x0C) || (0x0F == type)) + index = 0x04; + else if((type >= 0x13 && type <= 0x17) || (0x19 == type) || (type >= 0x1B && type <= 0x1f)) + index = 0x13; + else if(type >= 0x22 && type <= 0x2F) + index = 0x22; + else + index = type; + + if (index <= LEAKY_UNDEF_GARP_2F) + { + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_RMA_CTRL00+index, RTL8367D_RMA_CTRL00_VLAN_LEAKY_OFFSET, &tmp)) != RT_ERR_OK) + return retVal; + *pEnable = tmp; + } + else if (LEAKY_IPMULTICAST == index) + { + for (port = 0; port <= RTK_PORT_ID_MAX; port++) + { + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_IPMCAST_VLAN_LEAKY, port, &tmp)) != RT_ERR_OK) + return retVal; + if (port>0&&(tmp!=*pEnable)) + return RT_ERR_FAILED; + *pEnable = tmp; + } + } + else if (LEAKY_IGMP == index) + { + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_IGMP_MLD_CFG0, RTL8367D_IGMP_MLD_VLAN_LEAKY_OFFSET, &tmp)) != RT_ERR_OK) + return retVal; + *pEnable = tmp; + } + else if (LEAKY_CDP == index) + { + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_RMA_CTRL_CDP, RTL8367D_RMA_CTRL_CDP_VLAN_LEAKY_OFFSET, &tmp)) != RT_ERR_OK) + return retVal; + *pEnable = tmp; + } + else if (LEAKY_CSSTP == index) + { + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_RMA_CTRL_CSSTP, RTL8367D_RMA_CTRL_CSSTP_VLAN_LEAKY_OFFSET, &tmp)) != RT_ERR_OK) + return retVal; + *pEnable = tmp; + } + else if (LEAKY_LLDP == index) + { + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_RMA_CTRL_LLDP, RTL8367D_RMA_CTRL_LLDP_VLAN_LEAKY_OFFSET, &tmp)) != RT_ERR_OK) + return retVal; + *pEnable = tmp; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_leaky_portIsolation_set + * Description: + * Set port isolation leaky. + * Input: + * type - Packet type for port isolation leaky. + * enable - Leaky status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_ENABLE - Invalid enable input + * Note: + * This API can set port isolation leaky for RMA ,IGMP/MLD, CDP, CSSTP, and LLDP packets. + * The leaky frame types are as following: + * - LEAKY_BRG_GROUP, + * - LEAKY_FD_PAUSE, + * - LEAKY_SP_MCAST, + * - LEAKY_1X_PAE, + * - LEAKY_UNDEF_BRG_04, + * - LEAKY_UNDEF_BRG_05, + * - LEAKY_UNDEF_BRG_06, + * - LEAKY_UNDEF_BRG_07, + * - LEAKY_PROVIDER_BRIDGE_GROUP_ADDRESS, + * - LEAKY_UNDEF_BRG_09, + * - LEAKY_UNDEF_BRG_0A, + * - LEAKY_UNDEF_BRG_0B, + * - LEAKY_UNDEF_BRG_0C, + * - LEAKY_PROVIDER_BRIDGE_GVRP_ADDRESS, + * - LEAKY_8021AB, + * - LEAKY_UNDEF_BRG_0F, + * - LEAKY_BRG_MNGEMENT, + * - LEAKY_UNDEFINED_11, + * - LEAKY_UNDEFINED_12, + * - LEAKY_UNDEFINED_13, + * - LEAKY_UNDEFINED_14, + * - LEAKY_UNDEFINED_15, + * - LEAKY_UNDEFINED_16, + * - LEAKY_UNDEFINED_17, + * - LEAKY_UNDEFINED_18, + * - LEAKY_UNDEFINED_19, + * - LEAKY_UNDEFINED_1A, + * - LEAKY_UNDEFINED_1B, + * - LEAKY_UNDEFINED_1C, + * - LEAKY_UNDEFINED_1D, + * - LEAKY_UNDEFINED_1E, + * - LEAKY_UNDEFINED_1F, + * - LEAKY_GMRP, + * - LEAKY_GVRP, + * - LEAKY_UNDEF_GARP_22, + * - LEAKY_UNDEF_GARP_23, + * - LEAKY_UNDEF_GARP_24, + * - LEAKY_UNDEF_GARP_25, + * - LEAKY_UNDEF_GARP_26, + * - LEAKY_UNDEF_GARP_27, + * - LEAKY_UNDEF_GARP_28, + * - LEAKY_UNDEF_GARP_29, + * - LEAKY_UNDEF_GARP_2A, + * - LEAKY_UNDEF_GARP_2B, + * - LEAKY_UNDEF_GARP_2C, + * - LEAKY_UNDEF_GARP_2D, + * - LEAKY_UNDEF_GARP_2E, + * - LEAKY_UNDEF_GARP_2F, + * - LEAKY_IGMP, + * - LEAKY_IPMULTICAST. + * - LEAKY_CDP, + * - LEAKY_CSSTP, + * - LEAKY_LLDP. + */ +rtk_api_ret_t dal_rtl8367d_leaky_portIsolation_set(rtk_leaky_type_t type, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + rtk_uint32 port, index; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (type >= LEAKY_END) + return RT_ERR_INPUT; + + if (enable >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if( (type >= 0x4 && type <= 0x7) || (type >= 0x9 && type <= 0x0C) || (0x0F == type)) + index = 0x04; + else if((type >= 0x13 && type <= 0x17) || (0x19 == type) || (type >= 0x1B && type <= 0x1f)) + index = 0x13; + else if(type >= 0x22 && type <= 0x2F) + index = 0x22; + else + index = type; + + if (index <= LEAKY_UNDEF_GARP_2F) + { + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_RMA_CTRL00+index, RTL8367D_RMA_CTRL00_PORTISO_LEAKY_OFFSET, enable)) != RT_ERR_OK) + return retVal; + } + else if (LEAKY_IPMULTICAST == index) + { + for (port = 0; port <= RTK_PORT_ID_MAX; port++) + { + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_IPMCAST_PORTISO_LEAKY, port, enable)) != RT_ERR_OK) + return retVal; + } + } + else if (LEAKY_IGMP == index) + { + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_IGMP_MLD_CFG0, RTL8367D_IGMP_MLD_PORTISO_LEAKY_OFFSET, enable)) != RT_ERR_OK) + return retVal; + } + else if (LEAKY_CDP == index) + { + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_RMA_CTRL_CDP, RTL8367D_RMA_CTRL_CDP_PORTISO_LEAKY_OFFSET, enable)) != RT_ERR_OK) + return retVal; + } + else if (LEAKY_CSSTP == index) + { + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_RMA_CTRL_CSSTP, RTL8367D_RMA_CTRL_CSSTP_PORTISO_LEAKY_OFFSET, enable)) != RT_ERR_OK) + return retVal; + } + else if (LEAKY_LLDP == index) + { + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_RMA_CTRL_LLDP, RTL8367D_RMA_CTRL_LLDP_PORTISO_LEAKY_OFFSET, enable)) != RT_ERR_OK) + return retVal; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_leaky_portIsolation_get + * Description: + * Get port isolation leaky. + * Input: + * type - Packet type for port isolation leaky. + * Output: + * pEnable - Leaky status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can get port isolation leaky status for RMA ,IGMP/MLD, CDP, CSSTP, and LLDP packets. + * The leaky frame types are as following: + * - LEAKY_BRG_GROUP, + * - LEAKY_FD_PAUSE, + * - LEAKY_SP_MCAST, + * - LEAKY_1X_PAE, + * - LEAKY_UNDEF_BRG_04, + * - LEAKY_UNDEF_BRG_05, + * - LEAKY_UNDEF_BRG_06, + * - LEAKY_UNDEF_BRG_07, + * - LEAKY_PROVIDER_BRIDGE_GROUP_ADDRESS, + * - LEAKY_UNDEF_BRG_09, + * - LEAKY_UNDEF_BRG_0A, + * - LEAKY_UNDEF_BRG_0B, + * - LEAKY_UNDEF_BRG_0C, + * - LEAKY_PROVIDER_BRIDGE_GVRP_ADDRESS, + * - LEAKY_8021AB, + * - LEAKY_UNDEF_BRG_0F, + * - LEAKY_BRG_MNGEMENT, + * - LEAKY_UNDEFINED_11, + * - LEAKY_UNDEFINED_12, + * - LEAKY_UNDEFINED_13, + * - LEAKY_UNDEFINED_14, + * - LEAKY_UNDEFINED_15, + * - LEAKY_UNDEFINED_16, + * - LEAKY_UNDEFINED_17, + * - LEAKY_UNDEFINED_18, + * - LEAKY_UNDEFINED_19, + * - LEAKY_UNDEFINED_1A, + * - LEAKY_UNDEFINED_1B, + * - LEAKY_UNDEFINED_1C, + * - LEAKY_UNDEFINED_1D, + * - LEAKY_UNDEFINED_1E, + * - LEAKY_UNDEFINED_1F, + * - LEAKY_GMRP, + * - LEAKY_GVRP, + * - LEAKY_UNDEF_GARP_22, + * - LEAKY_UNDEF_GARP_23, + * - LEAKY_UNDEF_GARP_24, + * - LEAKY_UNDEF_GARP_25, + * - LEAKY_UNDEF_GARP_26, + * - LEAKY_UNDEF_GARP_27, + * - LEAKY_UNDEF_GARP_28, + * - LEAKY_UNDEF_GARP_29, + * - LEAKY_UNDEF_GARP_2A, + * - LEAKY_UNDEF_GARP_2B, + * - LEAKY_UNDEF_GARP_2C, + * - LEAKY_UNDEF_GARP_2D, + * - LEAKY_UNDEF_GARP_2E, + * - LEAKY_UNDEF_GARP_2F, + * - LEAKY_IGMP, + * - LEAKY_IPMULTICAST. + * - LEAKY_CDP, + * - LEAKY_CSSTP, + * - LEAKY_LLDP. + */ +rtk_api_ret_t dal_rtl8367d_leaky_portIsolation_get(rtk_leaky_type_t type, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + rtk_uint32 port, tmp, index; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (type >= LEAKY_END) + return RT_ERR_INPUT; + + if(NULL == pEnable) + return RT_ERR_NULL_POINTER; + + if( (type >= 0x4 && type <= 0x7) || (type >= 0x9 && type <= 0x0C) || (0x0F == type)) + index = 0x04; + else if((type >= 0x13 && type <= 0x17) || (0x19 == type) || (type >= 0x1B && type <= 0x1f)) + index = 0x13; + else if(type >= 0x22 && type <= 0x2F) + index = 0x22; + else + index = type; + + if (index <= LEAKY_UNDEF_GARP_2F) + { + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_RMA_CTRL00+index, RTL8367D_RMA_CTRL00_PORTISO_LEAKY_OFFSET, &tmp)) != RT_ERR_OK) + return retVal; + *pEnable = tmp; + } + else if (LEAKY_IPMULTICAST == index) + { + for (port = 0; port <= RTK_PORT_ID_MAX; port++) + { + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_IPMCAST_PORTISO_LEAKY, port, &tmp)) != RT_ERR_OK) + return retVal; + if (port>0&&(tmp!=*pEnable)) + return RT_ERR_FAILED; + *pEnable = tmp; + } + } + else if (LEAKY_IGMP == index) + { + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_IGMP_MLD_CFG0, RTL8367D_IGMP_MLD_PORTISO_LEAKY_OFFSET, &tmp)) != RT_ERR_OK) + return retVal; + *pEnable = tmp; + } + else if (LEAKY_CDP == index) + { + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_RMA_CTRL_CDP, RTL8367D_RMA_CTRL_CDP_PORTISO_LEAKY_OFFSET, &tmp)) != RT_ERR_OK) + return retVal; + *pEnable = tmp; + } + else if (LEAKY_CSSTP == index) + { + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_RMA_CTRL_CSSTP, RTL8367D_RMA_CTRL_CSSTP_PORTISO_LEAKY_OFFSET, &tmp)) != RT_ERR_OK) + return retVal; + *pEnable = tmp; + } + else if (LEAKY_LLDP == index) + { + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_RMA_CTRL_LLDP, RTL8367D_RMA_CTRL_LLDP_PORTISO_LEAKY_OFFSET, &tmp)) != RT_ERR_OK) + return retVal; + *pEnable = tmp; + } + + return RT_ERR_OK; +} + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_leaky.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_leaky.h new file mode 100644 index 00000000..d2e2260a --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_leaky.h @@ -0,0 +1,316 @@ + /* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8367/RTL8367C switch high-level API + * + * Feature : The file includes Leaky module high-layer API defination + * + */ + +#ifndef __DAL_RTL8367D_API_LEAKY_H__ +#define __DAL_RTL8367D_API_LEAKY_H__ + +#include + +/* Function Name: + * dal_rtl8367d_leaky_vlan_set + * Description: + * Set VLAN leaky. + * Input: + * type - Packet type for VLAN leaky. + * enable - Leaky status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_ENABLE - Invalid enable input + * Note: + * This API can set VLAN leaky for RMA ,IGMP/MLD, CDP, CSSTP, and LLDP packets. + * The leaky frame types are as following: + * - LEAKY_BRG_GROUP, + * - LEAKY_FD_PAUSE, + * - LEAKY_SP_MCAST, + * - LEAKY_1X_PAE, + * - LEAKY_UNDEF_BRG_04, + * - LEAKY_UNDEF_BRG_05, + * - LEAKY_UNDEF_BRG_06, + * - LEAKY_UNDEF_BRG_07, + * - LEAKY_PROVIDER_BRIDGE_GROUP_ADDRESS, + * - LEAKY_UNDEF_BRG_09, + * - LEAKY_UNDEF_BRG_0A, + * - LEAKY_UNDEF_BRG_0B, + * - LEAKY_UNDEF_BRG_0C, + * - LEAKY_PROVIDER_BRIDGE_GVRP_ADDRESS, + * - LEAKY_8021AB, + * - LEAKY_UNDEF_BRG_0F, + * - LEAKY_BRG_MNGEMENT, + * - LEAKY_UNDEFINED_11, + * - LEAKY_UNDEFINED_12, + * - LEAKY_UNDEFINED_13, + * - LEAKY_UNDEFINED_14, + * - LEAKY_UNDEFINED_15, + * - LEAKY_UNDEFINED_16, + * - LEAKY_UNDEFINED_17, + * - LEAKY_UNDEFINED_18, + * - LEAKY_UNDEFINED_19, + * - LEAKY_UNDEFINED_1A, + * - LEAKY_UNDEFINED_1B, + * - LEAKY_UNDEFINED_1C, + * - LEAKY_UNDEFINED_1D, + * - LEAKY_UNDEFINED_1E, + * - LEAKY_UNDEFINED_1F, + * - LEAKY_GMRP, + * - LEAKY_GVRP, + * - LEAKY_UNDEF_GARP_22, + * - LEAKY_UNDEF_GARP_23, + * - LEAKY_UNDEF_GARP_24, + * - LEAKY_UNDEF_GARP_25, + * - LEAKY_UNDEF_GARP_26, + * - LEAKY_UNDEF_GARP_27, + * - LEAKY_UNDEF_GARP_28, + * - LEAKY_UNDEF_GARP_29, + * - LEAKY_UNDEF_GARP_2A, + * - LEAKY_UNDEF_GARP_2B, + * - LEAKY_UNDEF_GARP_2C, + * - LEAKY_UNDEF_GARP_2D, + * - LEAKY_UNDEF_GARP_2E, + * - LEAKY_UNDEF_GARP_2F, + * - LEAKY_IGMP, + * - LEAKY_IPMULTICAST. + * - LEAKY_CDP, + * - LEAKY_CSSTP, + * - LEAKY_LLDP. + */ +extern rtk_api_ret_t dal_rtl8367d_leaky_vlan_set(rtk_leaky_type_t type, rtk_enable_t enable); + +/* Function Name: + * dal_rtl8367d_leaky_vlan_get + * Description: + * Get VLAN leaky. + * Input: + * type - Packet type for VLAN leaky. + * Output: + * pEnable - Leaky status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can get VLAN leaky status for RMA ,IGMP/MLD, CDP, CSSTP, and LLDP packets. + * The leaky frame types are as following: + * - LEAKY_BRG_GROUP, + * - LEAKY_FD_PAUSE, + * - LEAKY_SP_MCAST, + * - LEAKY_1X_PAE, + * - LEAKY_UNDEF_BRG_04, + * - LEAKY_UNDEF_BRG_05, + * - LEAKY_UNDEF_BRG_06, + * - LEAKY_UNDEF_BRG_07, + * - LEAKY_PROVIDER_BRIDGE_GROUP_ADDRESS, + * - LEAKY_UNDEF_BRG_09, + * - LEAKY_UNDEF_BRG_0A, + * - LEAKY_UNDEF_BRG_0B, + * - LEAKY_UNDEF_BRG_0C, + * - LEAKY_PROVIDER_BRIDGE_GVRP_ADDRESS, + * - LEAKY_8021AB, + * - LEAKY_UNDEF_BRG_0F, + * - LEAKY_BRG_MNGEMENT, + * - LEAKY_UNDEFINED_11, + * - LEAKY_UNDEFINED_12, + * - LEAKY_UNDEFINED_13, + * - LEAKY_UNDEFINED_14, + * - LEAKY_UNDEFINED_15, + * - LEAKY_UNDEFINED_16, + * - LEAKY_UNDEFINED_17, + * - LEAKY_UNDEFINED_18, + * - LEAKY_UNDEFINED_19, + * - LEAKY_UNDEFINED_1A, + * - LEAKY_UNDEFINED_1B, + * - LEAKY_UNDEFINED_1C, + * - LEAKY_UNDEFINED_1D, + * - LEAKY_UNDEFINED_1E, + * - LEAKY_UNDEFINED_1F, + * - LEAKY_GMRP, + * - LEAKY_GVRP, + * - LEAKY_UNDEF_GARP_22, + * - LEAKY_UNDEF_GARP_23, + * - LEAKY_UNDEF_GARP_24, + * - LEAKY_UNDEF_GARP_25, + * - LEAKY_UNDEF_GARP_26, + * - LEAKY_UNDEF_GARP_27, + * - LEAKY_UNDEF_GARP_28, + * - LEAKY_UNDEF_GARP_29, + * - LEAKY_UNDEF_GARP_2A, + * - LEAKY_UNDEF_GARP_2B, + * - LEAKY_UNDEF_GARP_2C, + * - LEAKY_UNDEF_GARP_2D, + * - LEAKY_UNDEF_GARP_2E, + * - LEAKY_UNDEF_GARP_2F, + * - LEAKY_IGMP, + * - LEAKY_IPMULTICAST. + * - LEAKY_CDP, + * - LEAKY_CSSTP, + * - LEAKY_LLDP. + */ +extern rtk_api_ret_t dal_rtl8367d_leaky_vlan_get(rtk_leaky_type_t type, rtk_enable_t *pEnable); + +/* Function Name: + * dal_rtl8367d_leaky_portIsolation_set + * Description: + * Set port isolation leaky. + * Input: + * type - Packet type for port isolation leaky. + * enable - Leaky status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_ENABLE - Invalid enable input + * Note: + * This API can set port isolation leaky for RMA ,IGMP/MLD, CDP, CSSTP, and LLDP packets. + * The leaky frame types are as following: + * - LEAKY_BRG_GROUP, + * - LEAKY_FD_PAUSE, + * - LEAKY_SP_MCAST, + * - LEAKY_1X_PAE, + * - LEAKY_UNDEF_BRG_04, + * - LEAKY_UNDEF_BRG_05, + * - LEAKY_UNDEF_BRG_06, + * - LEAKY_UNDEF_BRG_07, + * - LEAKY_PROVIDER_BRIDGE_GROUP_ADDRESS, + * - LEAKY_UNDEF_BRG_09, + * - LEAKY_UNDEF_BRG_0A, + * - LEAKY_UNDEF_BRG_0B, + * - LEAKY_UNDEF_BRG_0C, + * - LEAKY_PROVIDER_BRIDGE_GVRP_ADDRESS, + * - LEAKY_8021AB, + * - LEAKY_UNDEF_BRG_0F, + * - LEAKY_BRG_MNGEMENT, + * - LEAKY_UNDEFINED_11, + * - LEAKY_UNDEFINED_12, + * - LEAKY_UNDEFINED_13, + * - LEAKY_UNDEFINED_14, + * - LEAKY_UNDEFINED_15, + * - LEAKY_UNDEFINED_16, + * - LEAKY_UNDEFINED_17, + * - LEAKY_UNDEFINED_18, + * - LEAKY_UNDEFINED_19, + * - LEAKY_UNDEFINED_1A, + * - LEAKY_UNDEFINED_1B, + * - LEAKY_UNDEFINED_1C, + * - LEAKY_UNDEFINED_1D, + * - LEAKY_UNDEFINED_1E, + * - LEAKY_UNDEFINED_1F, + * - LEAKY_GMRP, + * - LEAKY_GVRP, + * - LEAKY_UNDEF_GARP_22, + * - LEAKY_UNDEF_GARP_23, + * - LEAKY_UNDEF_GARP_24, + * - LEAKY_UNDEF_GARP_25, + * - LEAKY_UNDEF_GARP_26, + * - LEAKY_UNDEF_GARP_27, + * - LEAKY_UNDEF_GARP_28, + * - LEAKY_UNDEF_GARP_29, + * - LEAKY_UNDEF_GARP_2A, + * - LEAKY_UNDEF_GARP_2B, + * - LEAKY_UNDEF_GARP_2C, + * - LEAKY_UNDEF_GARP_2D, + * - LEAKY_UNDEF_GARP_2E, + * - LEAKY_UNDEF_GARP_2F, + * - LEAKY_IGMP, + * - LEAKY_IPMULTICAST. + * - LEAKY_CDP, + * - LEAKY_CSSTP, + * - LEAKY_LLDP. + */ +extern rtk_api_ret_t dal_rtl8367d_leaky_portIsolation_set(rtk_leaky_type_t type, rtk_enable_t enable); + +/* Function Name: + * dal_rtl8367d_leaky_portIsolation_get + * Description: + * Get port isolation leaky. + * Input: + * type - Packet type for port isolation leaky. + * Output: + * pEnable - Leaky status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can get port isolation leaky status for RMA ,IGMP/MLD, CDP, CSSTP, and LLDP packets. + * The leaky frame types are as following: + * - LEAKY_BRG_GROUP, + * - LEAKY_FD_PAUSE, + * - LEAKY_SP_MCAST, + * - LEAKY_1X_PAE, + * - LEAKY_UNDEF_BRG_04, + * - LEAKY_UNDEF_BRG_05, + * - LEAKY_UNDEF_BRG_06, + * - LEAKY_UNDEF_BRG_07, + * - LEAKY_PROVIDER_BRIDGE_GROUP_ADDRESS, + * - LEAKY_UNDEF_BRG_09, + * - LEAKY_UNDEF_BRG_0A, + * - LEAKY_UNDEF_BRG_0B, + * - LEAKY_UNDEF_BRG_0C, + * - LEAKY_PROVIDER_BRIDGE_GVRP_ADDRESS, + * - LEAKY_8021AB, + * - LEAKY_UNDEF_BRG_0F, + * - LEAKY_BRG_MNGEMENT, + * - LEAKY_UNDEFINED_11, + * - LEAKY_UNDEFINED_12, + * - LEAKY_UNDEFINED_13, + * - LEAKY_UNDEFINED_14, + * - LEAKY_UNDEFINED_15, + * - LEAKY_UNDEFINED_16, + * - LEAKY_UNDEFINED_17, + * - LEAKY_UNDEFINED_18, + * - LEAKY_UNDEFINED_19, + * - LEAKY_UNDEFINED_1A, + * - LEAKY_UNDEFINED_1B, + * - LEAKY_UNDEFINED_1C, + * - LEAKY_UNDEFINED_1D, + * - LEAKY_UNDEFINED_1E, + * - LEAKY_UNDEFINED_1F, + * - LEAKY_GMRP, + * - LEAKY_GVRP, + * - LEAKY_UNDEF_GARP_22, + * - LEAKY_UNDEF_GARP_23, + * - LEAKY_UNDEF_GARP_24, + * - LEAKY_UNDEF_GARP_25, + * - LEAKY_UNDEF_GARP_26, + * - LEAKY_UNDEF_GARP_27, + * - LEAKY_UNDEF_GARP_28, + * - LEAKY_UNDEF_GARP_29, + * - LEAKY_UNDEF_GARP_2A, + * - LEAKY_UNDEF_GARP_2B, + * - LEAKY_UNDEF_GARP_2C, + * - LEAKY_UNDEF_GARP_2D, + * - LEAKY_UNDEF_GARP_2E, + * - LEAKY_UNDEF_GARP_2F, + * - LEAKY_IGMP, + * - LEAKY_IPMULTICAST. + * - LEAKY_CDP, + * - LEAKY_CSSTP, + * - LEAKY_LLDP. + */ +extern rtk_api_ret_t dal_rtl8367d_leaky_portIsolation_get(rtk_leaky_type_t type, rtk_enable_t *pEnable); + +#endif /* __DAL_RTL8367D_API_LEAKY_H__ */ + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_led.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_led.c new file mode 100644 index 00000000..67e08aed --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_led.c @@ -0,0 +1,790 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8367D + * Feature : Here is a list of all functions and variables in LED module. + * + */ + +#include +#include +#include +#include + +#include + +/* Function Name: + * dal_rtl8367d_led_enable_set + * Description: + * Set Led enable congiuration + * Input: + * group - LED group id. + * pPortmask - LED enable port mask. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_MASK - Error portmask + * Note: + * The API can be used to enable LED per port per group. + */ +rtk_api_ret_t dal_rtl8367d_led_enable_set(rtk_led_group_t group, rtk_portmask_t *pPortmask) +{ + rtk_api_ret_t retVal; + rtk_uint32 pmask; + rtk_port_t port; + rtk_uint32 regAddr; + rtk_uint32 regDataMask; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (group >= LED_GROUP_END) + return RT_ERR_INPUT; + + RTK_CHK_PORTMASK_VALID(pPortmask); + + RTK_PORTMASK_SCAN((*pPortmask), port) + { + if(rtk_switch_isCPUPort(port) == RT_ERR_OK) + return RT_ERR_PORT_MASK; + } + + if((retVal = rtk_switch_portmask_L2P_get(pPortmask, &pmask)) != RT_ERR_OK) + return retVal; + + regAddr = RTL8367D_REG_PARA_LED_IO_EN1 + group/2; + regDataMask = 0xFF << ((group%2)*8); + + if ((retVal = rtl8367d_setAsicRegBits(regAddr, regDataMask, pmask&0xff)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_led_enable_get + * Description: + * Get Led enable congiuration + * Input: + * group - LED group id. + * Output: + * pPortmask - LED enable port mask. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can be used to get LED enable status. + */ +rtk_api_ret_t dal_rtl8367d_led_enable_get(rtk_led_group_t group, rtk_portmask_t *pPortmask) +{ + rtk_api_ret_t retVal; + rtk_uint32 pmask; + rtk_uint32 regAddr; + rtk_uint32 regDataMask; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (group >= LED_GROUP_END) + return RT_ERR_INPUT; + + regAddr = RTL8367D_REG_PARA_LED_IO_EN1 + group/2; + regDataMask = 0xFF << ((group%2)*8); + if ((retVal = rtl8367d_getAsicRegBits(regAddr, regDataMask, &pmask)) != RT_ERR_OK) + return retVal; + + if((retVal = rtk_switch_portmask_P2L_get(pmask, pPortmask)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; + +} + +/* Function Name: + * dal_rtl8367d_led_operation_set + * Description: + * Set Led operation mode + * Input: + * mode - LED operation mode. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can set Led operation mode. + * The modes that can be set are as following: + * - LED_OP_SCAN, + * - LED_OP_PARALLEL, + * - LED_OP_SERIAL, + */ +rtk_api_ret_t dal_rtl8367d_led_operation_set(rtk_led_operation_t mode) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if ( mode >= LED_OP_END) + return RT_ERR_INPUT; + + switch (mode) + { + case LED_OP_PARALLEL: + if((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_LED_SYS_CONFIG, RTL8367D_LED_SELECT_OFFSET, 0))!= RT_ERR_OK) + return retVal; + /*Disable serial CLK mode*/ + if((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_SCAN0_LED_IO_EN,RTL8367D_LED_SERI_CLK_EN_OFFSET, 0))!= RT_ERR_OK) + return retVal; + /*Disable serial DATA mode*/ + if((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_SCAN0_LED_IO_EN,RTL8367D_LED_SERI_DATA_EN_OFFSET, 0))!= RT_ERR_OK) + return retVal; + break; + case LED_OP_SERIAL: + if((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_LED_SYS_CONFIG, RTL8367D_LED_SELECT_OFFSET, 1))!= RT_ERR_OK) + return retVal; + /*Enable serial CLK mode*/ + if((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_SCAN0_LED_IO_EN,RTL8367D_LED_SERI_CLK_EN_OFFSET, 1))!= RT_ERR_OK) + return retVal; + /*Enable serial DATA mode*/ + if((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_SCAN0_LED_IO_EN,RTL8367D_LED_SERI_DATA_EN_OFFSET, 1))!= RT_ERR_OK) + return retVal; + break; + default: + return RT_ERR_CHIP_NOT_SUPPORTED; + break; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_led_operation_get + * Description: + * Get Led operation mode + * Input: + * None + * Output: + * pMode - Support LED operation mode. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get Led operation mode. + * The modes that can be set are as following: + * - LED_OP_SCAN, + * - LED_OP_PARALLEL, + * - LED_OP_SERIAL, + */ +rtk_api_ret_t dal_rtl8367d_led_operation_get(rtk_led_operation_t *pMode) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pMode) + return RT_ERR_NULL_POINTER; + + if((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_LED_SYS_CONFIG, RTL8367D_LED_SELECT_OFFSET, ®Data))!= RT_ERR_OK) + return retVal; + + if (regData == RTL8367D_LEDOP_SERIAL) + *pMode = LED_OP_SERIAL; + else if (regData == RTL8367D_LEDOP_PARALLEL) + *pMode = LED_OP_PARALLEL; + else + return RT_ERR_FAILED; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_led_modeForce_set + * Description: + * Set Led group to congiuration force mode + * Input: + * port - port ID + * group - Support LED group id. + * mode - Support LED force mode. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Error Port ID + * Note: + * The API can force to one force mode. + * The force modes that can be set are as following: + * - LED_FORCE_NORMAL, + * - LED_FORCE_BLINK, + * - LED_FORCE_OFF, + * - LED_FORCE_ON. + */ +rtk_api_ret_t dal_rtl8367d_led_modeForce_set(rtk_port_t port, rtk_led_group_t group, rtk_led_force_mode_t mode) +{ + rtk_api_ret_t retVal; + rtk_uint16 regAddr; + rtk_uint32 phyPort; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + /* No LED for CPU port */ + if(rtk_switch_isCPUPort(port) == RT_ERR_OK) + return RT_ERR_PORT_ID; + + if (group >= LED_GROUP_END) + return RT_ERR_INPUT; + + if (mode >= LED_FORCE_END) + return RT_ERR_NOT_ALLOWED; + + phyPort = rtk_switch_port_L2P_get(port); + if (phyPort == UNDEFINE_PHY_PORT) + return RT_ERR_PORT_ID; + + /* Set Related Registers */ + regAddr = RTL8367D_LED_FORCE_MODE_BASE + (group << 1); + if((retVal = rtl8367d_setAsicRegBits(regAddr, 0x3 << (phyPort * 2), mode)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_led_modeForce_get + * Description: + * Get Led group to congiuration force mode + * Input: + * port - port ID + * group - Support LED group id. + * pMode - Support LED force mode. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Error Port ID + * Note: + * The API can get forced Led group mode. + * The force modes that can be set are as following: + * - LED_FORCE_NORMAL, + * - LED_FORCE_BLINK, + * - LED_FORCE_OFF, + * - LED_FORCE_ON. + */ +rtk_api_ret_t dal_rtl8367d_led_modeForce_get(rtk_port_t port, rtk_led_group_t group, rtk_led_force_mode_t *pMode) +{ + rtk_api_ret_t retVal; + rtk_uint16 regAddr; + rtk_uint32 phyPort; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + /* No LED for CPU port */ + if(rtk_switch_isCPUPort(port) == RT_ERR_OK) + return RT_ERR_PORT_ID; + + if (group >= LED_GROUP_END) + return RT_ERR_INPUT; + + if (NULL == pMode) + return RT_ERR_NULL_POINTER; + + phyPort = rtk_switch_port_L2P_get(port); + if (phyPort == UNDEFINE_PHY_PORT) + return RT_ERR_PORT_ID; + + /* Get Related Registers */ + regAddr = RTL8367D_LED_FORCE_MODE_BASE + (group << 1); + if((retVal = rtl8367d_getAsicRegBits(regAddr, 0x3 << (phyPort * 2), pMode)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_led_blinkRate_set + * Description: + * Set LED blinking rate + * Input: + * blinkRate - blinking rate. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API configure LED blinking rate: + * - LED_BLINKRATE_32MS + * - LED_BLINKRATE_64MS, + * - LED_BLINKRATE_128MS, + * - LED_BLINKRATE_256MS, + * - LED_BLINKRATE_512MS, + * - LED_BLINKRATE_1024MS, + * - LED_BLINKRATE_48MS, + * - LED_BLINKRATE_96MS, + */ +rtk_api_ret_t dal_rtl8367d_led_blinkRate_set(rtk_led_blink_rate_t blinkRate) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (blinkRate >= LED_BLINKRATE_END) + return RT_ERR_FAILED; + + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_LED_MODE, RTL8367D_SEL_LEDRATE_MASK, blinkRate)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_led_blinkRate_get + * Description: + * Get LED blinking rate at mode 0 to mode 3 + * Input: + * None + * Output: + * pBlinkRate - blinking rate. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API get LED blinking rate: + * - LED_BLINKRATE_32MS + * - LED_BLINKRATE_64MS, + * - LED_BLINKRATE_128MS, + * - LED_BLINKRATE_256MS, + * - LED_BLINKRATE_512MS, + * - LED_BLINKRATE_1024MS, + * - LED_BLINKRATE_48MS, + * - LED_BLINKRATE_96MS, + */ +rtk_api_ret_t dal_rtl8367d_led_blinkRate_get(rtk_led_blink_rate_t *pBlinkRate) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pBlinkRate) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_LED_MODE, RTL8367D_SEL_LEDRATE_MASK, pBlinkRate)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_led_groupConfig_set + * Description: + * Set per group Led to congiuration mode + * Input: + * group - LED group. + * config - LED configuration + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can set LED indicated information configuration for each LED group with 1 to 1 led mapping to each port. + * - Definition LED Statuses Description + * - 0000 LED_Off LED pin Tri-State. + * - 0001 Dup/Col Collision, Full duplex Indicator. + * - 0010 Link/Act Link, Activity Indicator. + * - 0011 Spd1000 1000Mb/s Speed Indicator. + * - 0100 Spd100 100Mb/s Speed Indicator. + * - 0101 Spd10 10Mb/s Speed Indicator. + * - 0110 Spd1000/Act 1000Mb/s Speed/Activity Indicator. + * - 0111 Spd100/Act 100Mb/s Speed/Activity Indicator. + * - 1000 Spd10/Act 10Mb/s Speed/Activity Indicator. + * - 1001 Spd100 (10)/Act 10/100Mb/s Speed/Activity Indicator. + * - 1010 LoopDetect LoopDetect Indicator. + * - 1011 EEE EEE Indicator. + * - 1100 Link/Rx Link, Activity Indicator. + * - 1101 Link/Tx Link, Activity Indicator. + * - 1110 Master Link on Master Indicator. + * - 1111 Act Activity Indicator. Low for link established. + */ +rtk_api_ret_t dal_rtl8367d_led_groupConfig_set(rtk_led_group_t group, rtk_led_congig_t config) +{ + rtk_api_ret_t retVal; + CONST rtk_uint16 bits[RTL8367D_LEDGROUPNO] = {RTL8367D_LED0_CFG_MASK, RTL8367D_LED1_CFG_MASK, RTL8367D_LED2_CFG_MASK}; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (LED_GROUP_END <= group) + return RT_ERR_FAILED; + + if (LED_CONFIG_END <= config) + return RT_ERR_FAILED; + + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_LED_CONFIGURATION, RTL8367D_LED_CONFIG_SEL_OFFSET, 0)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_LED_CONFIGURATION, bits[group], config)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_led_groupConfig_get + * Description: + * Get Led group congiuration mode + * Input: + * group - LED group. + * Output: + * pConfig - LED configuration. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get LED indicated information configuration for each LED group. + */ +rtk_api_ret_t dal_rtl8367d_led_groupConfig_get(rtk_led_group_t group, rtk_led_congig_t *pConfig) +{ + rtk_api_ret_t retVal; + CONST rtk_uint16 bits[RTL8367D_LEDGROUPNO]= {RTL8367D_LED0_CFG_MASK, RTL8367D_LED1_CFG_MASK, RTL8367D_LED2_CFG_MASK}; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (LED_GROUP_END <= group) + return RT_ERR_FAILED; + + if(NULL == pConfig) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_LED_CONFIGURATION, bits[group], pConfig)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_led_groupAbility_set + * Description: + * Configure per group Led ability + * Input: + * group - LED group. + * pAbility - LED ability + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * None. + */ + +rtk_api_ret_t dal_rtl8367d_led_groupAbility_set(rtk_led_group_t group, rtk_led_ability_t *pAbility) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (LED_GROUP_END <= group) + return RT_ERR_FAILED; + + if(pAbility == NULL) + return RT_ERR_NULL_POINTER; + + if( (pAbility->link_10m >= RTK_ENABLE_END) || (pAbility->link_100m >= RTK_ENABLE_END) || + (pAbility->link_500m >= RTK_ENABLE_END) || (pAbility->link_1000m >= RTK_ENABLE_END) || (pAbility->link_2500m >= RTK_ENABLE_END) || + (pAbility->act_rx >= RTK_ENABLE_END) || (pAbility->act_tx >= RTK_ENABLE_END) ) + { + return RT_ERR_INPUT; + } + + if ((retVal = rtl8367d_getAsicReg(RTL8367D_REG_LED0_DATA_CTRL + (rtk_uint32)group, ®Data)) != RT_ERR_OK) + return retVal; + + if(pAbility->link_10m == ENABLED) + regData |= 0x0001; + else + regData &= ~0x0001; + + if(pAbility->link_100m == ENABLED) + regData |= 0x0002; + else + regData &= ~0x0002; + + if(pAbility->link_500m == ENABLED) + regData |= 0x0004; + else + regData &= ~0x0004; + + if(pAbility->link_1000m == ENABLED) + regData |= 0x0008; + else + regData &= ~0x0008; + + if(pAbility->link_2500m == ENABLED) + regData |= 0x0010; + else + regData &= ~0x0010; + + if(pAbility->act_rx == ENABLED) + regData |= 0x0020; + else + regData &= ~0x0020; + + if(pAbility->act_tx == ENABLED) + regData |= 0x0040; + else + regData &= ~0x0040; + + regData |= (0x0001 << 7); + + if ((retVal = rtl8367d_setAsicReg(RTL8367D_REG_LED0_DATA_CTRL + (rtk_uint32)group, regData)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_led_groupAbility_get + * Description: + * Get per group Led ability + * Input: + * group - LED group. + * pAbility - LED ability + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * None. + */ + +rtk_api_ret_t dal_rtl8367d_led_groupAbility_get(rtk_led_group_t group, rtk_led_ability_t *pAbility) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (LED_GROUP_END <= group) + return RT_ERR_FAILED; + + if(pAbility == NULL) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367d_getAsicReg(RTL8367D_REG_LED0_DATA_CTRL + (rtk_uint32)group, ®Data)) != RT_ERR_OK) + return retVal; + + pAbility->link_10m = (regData & 0x0001) ? ENABLED : DISABLED; + pAbility->link_100m = (regData & 0x0002) ? ENABLED : DISABLED; + pAbility->link_500m = (regData & 0x0004) ? ENABLED : DISABLED; + pAbility->link_1000m = (regData & 0x0008) ? ENABLED : DISABLED; + pAbility->link_2500m = (regData & 0x0010) ? ENABLED : DISABLED; + pAbility->act_rx = (regData & 0x0020) ? ENABLED : DISABLED; + pAbility->act_tx = (regData & 0x0040) ? ENABLED : DISABLED; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_led_serialMode_set + * Description: + * Set Led serial mode active congiuration + * Input: + * active - LED group. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can set LED serial mode active congiuration. + */ +rtk_api_ret_t dal_rtl8367d_led_serialMode_set(rtk_led_active_t active) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if ( active >= LED_ACTIVE_END) + return RT_ERR_INPUT; + + /* Set Active High or Low */ + if((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_LED_SYS_CONFIG, RTL8367D_SERI_LED_ACT_LOW_OFFSET, active)) != RT_ERR_OK) + return retVal; + + /*set to 8G mode (not 16G mode)*/ + if((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_LED_MODE, RTL8367D_DLINK_TIME_OFFSET, 1))!= RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_led_serialMode_get + * Description: + * Get Led group congiuration mode + * Input: + * group - LED group. + * Output: + * pConfig - LED configuration. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get LED serial mode active configuration. + */ +rtk_api_ret_t dal_rtl8367d_led_serialMode_get(rtk_led_active_t *pActive) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pActive) + return RT_ERR_NULL_POINTER; + + if((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_LED_SYS_CONFIG, RTL8367D_SERI_LED_ACT_LOW_OFFSET, pActive))!= RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_led_OutputEnable_set + * Description: + * This API set LED I/O state. + * Input: + * enabled - LED I/O state + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error parameter + * Note: + * This API set LED I/O state. + */ +rtk_api_ret_t dal_rtl8367d_led_OutputEnable_set(rtk_enable_t state) +{ + rtk_api_ret_t retVal; + rtk_uint32 regdata; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (state >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if (state == 1) + regdata = 0; + else + regdata = 1; + + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_LED_SYS_CONFIG, RTL8367D_LED_IO_DISABLE_OFFSET, regdata))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_led_OutputEnable_get + * Description: + * This API get LED I/O state. + * Input: + * None. + * Output: + * pEnabled - LED I/O state + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error parameter + * Note: + * This API set current LED I/O state. + */ +rtk_api_ret_t dal_rtl8367d_led_OutputEnable_get(rtk_enable_t *pState) +{ + rtk_api_ret_t retVal; + rtk_uint32 regdata; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(pState == NULL) + return RT_ERR_NULL_POINTER; + + + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_LED_SYS_CONFIG, RTL8367D_LED_IO_DISABLE_OFFSET, ®data))!=RT_ERR_OK) + return retVal; + + if (regdata == 1) + *pState = 0; + else + *pState = 1; + + return RT_ERR_OK; + +} + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_led.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_led.h new file mode 100644 index 00000000..82e39bef --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_led.h @@ -0,0 +1,384 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8367/RTL8367D switch high-level API + * + * Feature : The file includes LED module high-layer API defination + * + */ + +#ifndef __DAL_RTL8367D_LED_H__ +#define __DAL_RTL8367D_LED_H__ +#include <../../led.h> + +#define RTL8367D_LEDOP_PARALLEL 0 +#define RTL8367D_LEDOP_SERIAL 1 +#define RTL8367D_LEDOP_END 2 + +#define RTL8367D_LEDGROUPNO 3 +#define RTL8367D_LEDGROUPMASK 0x7 +#define RTL8367D_LED_FORCE_MODE_BASE RTL8367D_REG_CPU_FORCE_LED0_CFG0 +#define RTL8367D_LED_FORCE_CTRL RTL8367D_REG_CPU_FORCE_LED_CFG + + +/* Function Name: + * dal_rtl8367d_led_enable_set + * Description: + * Set Led enable congiuration + * Input: + * group - LED group id. + * pPortmask - LED enable port mask. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can be used to enable LED per port per group. + */ +extern rtk_api_ret_t dal_rtl8367d_led_enable_set(rtk_led_group_t group, rtk_portmask_t *pPortmask); + +/* Function Name: + * dal_rtl8367d_led_enable_get + * Description: + * Get Led enable congiuration + * Input: + * group - LED group id. + * Output: + * pPortmask - LED enable port mask. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can be used to get LED enable status. + */ +extern rtk_api_ret_t dal_rtl8367d_led_enable_get(rtk_led_group_t group, rtk_portmask_t *pPortmask); + +/* Function Name: + * dal_rtl8367d_led_operation_set + * Description: + * Set Led operation mode + * Input: + * mode - LED operation mode. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can set Led operation mode. + * The modes that can be set are as following: + * - LED_OP_SCAN, + * - LED_OP_PARALLEL, + * - LED_OP_SERIAL, + */ +extern rtk_api_ret_t dal_rtl8367d_led_operation_set(rtk_led_operation_t mode); + +/* Function Name: + * dal_rtl8367d_led_operation_get + * Description: + * Get Led operation mode + * Input: + * None + * Output: + * pMode - Support LED operation mode. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get Led operation mode. + * The modes that can be set are as following: + * - LED_OP_SCAN, + * - LED_OP_PARALLEL, + * - LED_OP_SERIAL, + */ +extern rtk_api_ret_t dal_rtl8367d_led_operation_get(rtk_led_operation_t *pMode); + +/* Function Name: + * dal_rtl8367d_led_modeForce_set + * Description: + * Set Led group to congiuration force mode + * Input: + * port - port ID + * group - Support LED group id. + * mode - Support LED force mode. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Error Port ID + * Note: + * The API can force to one force mode. + * The force modes that can be set are as following: + * - LED_FORCE_NORMAL, + * - LED_FORCE_BLINK, + * - LED_FORCE_OFF, + * - LED_FORCE_ON. + */ +extern rtk_api_ret_t dal_rtl8367d_led_modeForce_set(rtk_port_t port, rtk_led_group_t group, rtk_led_force_mode_t mode); + +/* Function Name: + * dal_rtl8367d_led_modeForce_get + * Description: + * Get Led group to congiuration force mode + * Input: + * port - port ID + * group - Support LED group id. + * pMode - Support LED force mode. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Error Port ID + * Note: + * The API can get forced Led group mode. + * The force modes that can be set are as following: + * - LED_FORCE_NORMAL, + * - LED_FORCE_BLINK, + * - LED_FORCE_OFF, + * - LED_FORCE_ON. + */ +extern rtk_api_ret_t dal_rtl8367d_led_modeForce_get(rtk_port_t port, rtk_led_group_t group, rtk_led_force_mode_t *pMode); + +/* Function Name: + * dal_rtl8367d_led_blinkRate_set + * Description: + * Set LED blinking rate + * Input: + * blinkRate - blinking rate. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API configure LED blinking rate: + * - LED_BLINKRATE_32MS + * - LED_BLINKRATE_64MS, + * - LED_BLINKRATE_128MS, + * - LED_BLINKRATE_256MS, + * - LED_BLINKRATE_512MS, + * - LED_BLINKRATE_1024MS, + * - LED_BLINKRATE_48MS, + * - LED_BLINKRATE_96MS, + */ +extern rtk_api_ret_t dal_rtl8367d_led_blinkRate_set(rtk_led_blink_rate_t blinkRate); + +/* Function Name: + * dal_rtl8367d_led_blinkRate_get + * Description: + * Get LED blinking rate at mode 0 to mode 3 + * Input: + * None + * Output: + * pBlinkRate - blinking rate. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API get LED blinking rate: + * - LED_BLINKRATE_32MS + * - LED_BLINKRATE_64MS, + * - LED_BLINKRATE_128MS, + * - LED_BLINKRATE_256MS, + * - LED_BLINKRATE_512MS, + * - LED_BLINKRATE_1024MS, + * - LED_BLINKRATE_48MS, + * - LED_BLINKRATE_96MS, + */ +extern rtk_api_ret_t dal_rtl8367d_led_blinkRate_get(rtk_led_blink_rate_t *pBlinkRate); + +/* Function Name: + * dal_rtl8367d_led_groupConfig_set + * Description: + * Set per group Led to congiuration mode + * Input: + * group - LED group. + * config - LED configuration + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can set LED indicated information configuration for each LED group with 1 to 1 led mapping to each port. + * - Definition LED Statuses Description + * - 0000 LED_Off LED pin Tri-State. + * - 0001 Dup/Col Collision, Full duplex Indicator. + * - 0010 Link/Act Link, Activity Indicator. + * - 0011 Spd1000 1000Mb/s Speed Indicator. + * - 0100 Spd100 100Mb/s Speed Indicator. + * - 0101 Spd10 10Mb/s Speed Indicator. + * - 0110 Spd1000/Act 1000Mb/s Speed/Activity Indicator. + * - 0111 Spd100/Act 100Mb/s Speed/Activity Indicator. + * - 1000 Spd10/Act 10Mb/s Speed/Activity Indicator. + * - 1001 Spd100 (10)/Act 10/100Mb/s Speed/Activity Indicator. + * - 1010 LoopDetect LoopDetect Indicator. + * - 1011 EEE EEE Indicator. + * - 1100 Link/Rx Link, Activity Indicator. + * - 1101 Link/Tx Link, Activity Indicator. + * - 1110 Master Link on Master Indicator. + * - 1111 Act Activity Indicator. Low for link established. + */ +extern rtk_api_ret_t dal_rtl8367d_led_groupConfig_set(rtk_led_group_t group, rtk_led_congig_t config); + +/* Function Name: + * dal_rtl8367d_led_groupConfig_get + * Description: + * Get Led group congiuration mode + * Input: + * group - LED group. + * Output: + * pConfig - LED configuration. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get LED indicated information configuration for each LED group. + */ +extern rtk_api_ret_t dal_rtl8367d_led_groupConfig_get(rtk_led_group_t group, rtk_led_congig_t *pConfig); + +/* Function Name: + * dal_rtl8367d_led_groupAbility_set + * Description: + * Configure per group Led ability + * Input: + * group - LED group. + * pAbility - LED ability + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * None. + */ + +extern rtk_api_ret_t dal_rtl8367d_led_groupAbility_set(rtk_led_group_t group, rtk_led_ability_t *pAbility); + +/* Function Name: + * dal_rtl8367d_led_groupAbility_get + * Description: + * Get per group Led ability + * Input: + * group - LED group. + * pAbility - LED ability + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * None. + */ + +extern rtk_api_ret_t dal_rtl8367d_led_groupAbility_get(rtk_led_group_t group, rtk_led_ability_t *pAbility); + +/* Function Name: + * dal_rtl8367d_led_serialMode_set + * Description: + * Set Led serial mode active congiuration + * Input: + * active - LED group. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can set LED serial mode active congiuration. + */ +extern rtk_api_ret_t dal_rtl8367d_led_serialMode_set(rtk_led_active_t active); + +/* Function Name: + * dal_rtl8367d_led_serialMode_get + * Description: + * Get Led group congiuration mode + * Input: + * group - LED group. + * Output: + * pConfig - LED configuration. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get LED serial mode active configuration. + */ +extern rtk_api_ret_t dal_rtl8367d_led_serialMode_get(rtk_led_active_t *pActive); + +/* Function Name: + * dal_rtl8367d_led_OutputEnable_set + * Description: + * This API set LED I/O state. + * Input: + * enabled - LED I/O state + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error parameter + * Note: + * This API set LED I/O state. + */ +extern rtk_api_ret_t dal_rtl8367d_led_OutputEnable_set(rtk_enable_t state); + + +/* Function Name: + * dal_rtl8367d_led_OutputEnable_get + * Description: + * This API get LED I/O state. + * Input: + * None. + * Output: + * pEnabled - LED I/O state + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error parameter + * Note: + * This API set current LED I/O state. + */ +extern rtk_api_ret_t dal_rtl8367d_led_OutputEnable_get(rtk_enable_t *pState); + +#endif /* __DAL_RTL8367D_LED_H__ */ diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_mapper.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_mapper.c new file mode 100644 index 00000000..aa063638 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_mapper.c @@ -0,0 +1,614 @@ + +/* + * Copyright (C) 2012 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + */ + +/* + * Include Files + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * Symbol Definition + */ + +/* + * Data Declaration + */ +static dal_mapper_t dal_rtl8367d_mapper = +{ + /* Switch */ + .switch_init = dal_rtl8367d_switch_init, + .switch_portMaxPktLen_set = dal_rtl8367d_switch_portMaxPktLen_set, + .switch_portMaxPktLen_get = dal_rtl8367d_switch_portMaxPktLen_get, + .switch_maxPktLenCfg_set = dal_rtl8367d_switch_maxPktLenCfg_set, + .switch_maxPktLenCfg_get = dal_rtl8367d_switch_maxPktLenCfg_get, + .switch_greenEthernet_set = NULL, + .switch_greenEthernet_get = NULL, + + /* eee */ + .eee_init = NULL, + .eee_portEnable_set = dal_rtl8367d_eee_portEnable_set, + .eee_portEnable_get = dal_rtl8367d_eee_portEnable_get, + + /* led */ + .led_enable_set = dal_rtl8367d_led_enable_set, + .led_enable_get = dal_rtl8367d_led_enable_get, + .led_operation_set = dal_rtl8367d_led_operation_set, + .led_operation_get = dal_rtl8367d_led_operation_get, + .led_modeForce_set = dal_rtl8367d_led_modeForce_set, + .led_modeForce_get = dal_rtl8367d_led_modeForce_get, + .led_blinkRate_set = dal_rtl8367d_led_blinkRate_set, + .led_blinkRate_get = dal_rtl8367d_led_blinkRate_get, + .led_groupConfig_set = dal_rtl8367d_led_groupConfig_set, + .led_groupConfig_get = dal_rtl8367d_led_groupConfig_get, + .led_groupAbility_set = dal_rtl8367d_led_groupAbility_set, + .led_groupAbility_get = dal_rtl8367d_led_groupAbility_get, + .led_serialMode_set = dal_rtl8367d_led_serialMode_set, + .led_serialMode_get = dal_rtl8367d_led_serialMode_get, + .led_OutputEnable_set = dal_rtl8367d_led_OutputEnable_set, + .led_OutputEnable_get = dal_rtl8367d_led_OutputEnable_get, + .led_serialModePortmask_set = NULL, + .led_serialModePortmask_get = NULL, + + /* oam */ + .oam_init = NULL, + .oam_state_set = NULL, + .oam_state_get = NULL, + .oam_parserAction_set = NULL, + .oam_parserAction_get = NULL, + .oam_multiplexerAction_set = NULL, + .oam_multiplexerAction_get = NULL, + + /* cpu */ + .cpu_enable_set = dal_rtl8367d_cpu_enable_set, + .cpu_enable_get = dal_rtl8367d_cpu_enable_get, + .cpu_tagPort_set = dal_rtl8367d_cpu_tagPort_set, + .cpu_tagPort_get = dal_rtl8367d_cpu_tagPort_get, + .cpu_awarePort_set = dal_rtl8367d_cpu_awarePort_set, + .cpu_awarePort_get = dal_rtl8367d_cpu_awarePort_get, + .cpu_tagPosition_set = dal_rtl8367d_cpu_tagPosition_set, + .cpu_tagPosition_get = dal_rtl8367d_cpu_tagPosition_get, + .cpu_tagLength_set = dal_rtl8367d_cpu_tagLength_set, + .cpu_tagLength_get = dal_rtl8367d_cpu_tagLength_get, + .cpu_acceptLength_set = dal_rtl8367d_cpu_acceptLength_set, + .cpu_acceptLength_get = dal_rtl8367d_cpu_acceptLength_get, + .cpu_priRemap_set = dal_rtl8367d_cpu_priRemap_set, + .cpu_priRemap_get = dal_rtl8367d_cpu_priRemap_get, + + /* stat */ + .stat_global_reset = dal_rtl8367d_stat_global_reset, + .stat_port_reset = dal_rtl8367d_stat_port_reset, + .stat_queueManage_reset = dal_rtl8367d_stat_queueManage_reset, + .stat_global_get = dal_rtl8367d_stat_global_get, + .stat_global_getAll = dal_rtl8367d_stat_global_getAll, + .stat_port_get = dal_rtl8367d_stat_port_get, + .stat_port_getAll = dal_rtl8367d_stat_port_getAll, + .stat_logging_counterCfg_set = dal_rtl8367d_stat_logging_counterCfg_set, + .stat_logging_counterCfg_get = dal_rtl8367d_stat_logging_counterCfg_get, + .stat_logging_counter_reset = dal_rtl8367d_stat_logging_counter_reset, + .stat_logging_counter_get = dal_rtl8367d_stat_logging_counter_get, + .stat_lengthMode_set = dal_rtl8367d_stat_lengthMode_set, + .stat_lengthMode_get = dal_rtl8367d_stat_lengthMode_get, + + /* l2 */ + .l2_init = dal_rtl8367d_l2_init, + .l2_addr_add = dal_rtl8367d_l2_addr_add, + .l2_addr_get = dal_rtl8367d_l2_addr_get, + .l2_addr_next_get = dal_rtl8367d_l2_addr_next_get, + .l2_addr_del = dal_rtl8367d_l2_addr_del, + .l2_mcastAddr_add = dal_rtl8367d_l2_mcastAddr_add, + .l2_mcastAddr_get = dal_rtl8367d_l2_mcastAddr_get, + .l2_mcastAddr_next_get = dal_rtl8367d_l2_mcastAddr_next_get, + .l2_mcastAddr_del = dal_rtl8367d_l2_mcastAddr_del, + .l2_ipMcastAddr_add = dal_rtl8367d_l2_ipMcastAddr_add, + .l2_ipMcastAddr_get = dal_rtl8367d_l2_ipMcastAddr_get, + .l2_ipMcastAddr_next_get = dal_rtl8367d_l2_ipMcastAddr_next_get, + .l2_ipMcastAddr_del = dal_rtl8367d_l2_ipMcastAddr_del, + .l2_ipVidMcastAddr_add = NULL, + .l2_ipVidMcastAddr_get = NULL, + .l2_ipVidMcastAddr_next_get = NULL, + .l2_ipVidMcastAddr_del = NULL, + .l2_ucastAddr_flush = dal_rtl8367d_l2_ucastAddr_flush, + .l2_table_clear = dal_rtl8367d_l2_table_clear, + .l2_table_clearStatus_get = dal_rtl8367d_l2_table_clearStatus_get, + .l2_flushLinkDownPortAddrEnable_set = dal_rtl8367d_l2_flushLinkDownPortAddrEnable_set, + .l2_flushLinkDownPortAddrEnable_get = dal_rtl8367d_l2_flushLinkDownPortAddrEnable_get, + .l2_agingEnable_set = dal_rtl8367d_l2_agingEnable_set, + .l2_agingEnable_get = dal_rtl8367d_l2_agingEnable_get, + .l2_limitLearningCnt_set = dal_rtl8367d_l2_limitLearningCnt_set, + .l2_limitLearningCnt_get = dal_rtl8367d_l2_limitLearningCnt_get, + .l2_limitSystemLearningCnt_set = dal_rtl8367d_l2_limitSystemLearningCnt_set, + .l2_limitSystemLearningCnt_get = dal_rtl8367d_l2_limitSystemLearningCnt_get, + .l2_limitLearningCntAction_set = dal_rtl8367d_l2_limitLearningCntAction_set, + .l2_limitLearningCntAction_get = dal_rtl8367d_l2_limitLearningCntAction_get, + .l2_limitSystemLearningCntAction_set = dal_rtl8367d_l2_limitSystemLearningCntAction_set, + .l2_limitSystemLearningCntAction_get = dal_rtl8367d_l2_limitSystemLearningCntAction_get, + .l2_limitSystemLearningCntPortMask_set = dal_rtl8367d_l2_limitSystemLearningCntPortMask_set, + .l2_limitSystemLearningCntPortMask_get = dal_rtl8367d_l2_limitSystemLearningCntPortMask_get, + .l2_learningCnt_get = dal_rtl8367d_l2_learningCnt_get, + .l2_floodPortMask_set = dal_rtl8367d_l2_floodPortMask_set, + .l2_floodPortMask_get = dal_rtl8367d_l2_floodPortMask_get, + .l2_localPktPermit_set = dal_rtl8367d_l2_localPktPermit_set, + .l2_localPktPermit_get = dal_rtl8367d_l2_localPktPermit_get, + .l2_aging_set = dal_rtl8367d_l2_aging_set, + .l2_aging_get = dal_rtl8367d_l2_aging_get, + .l2_ipMcastAddrLookup_set = dal_rtl8367d_l2_ipMcastAddrLookup_set, + .l2_ipMcastAddrLookup_get = dal_rtl8367d_l2_ipMcastAddrLookup_get, + .l2_ipMcastForwardRouterPort_set = NULL, + .l2_ipMcastForwardRouterPort_get = NULL, + .l2_ipMcastGroupEntry_add = dal_rtl8367d_l2_ipMcastGroupEntry_add, + .l2_ipMcastGroupEntry_del = dal_rtl8367d_l2_ipMcastGroupEntry_del, + .l2_ipMcastGroupEntry_get = dal_rtl8367d_l2_ipMcastGroupEntry_get, + .l2_entry_get = dal_rtl8367d_l2_entry_get, + .l2_lookupHitIsolationAction_set = dal_rtl8367d_l2_lookupHitIsolationAction_set, + .l2_lookupHitIsolationAction_get = dal_rtl8367d_l2_lookupHitIsolationAction_get, + + /* interrupt */ + .int_polarity_set = dal_rtl8367d_int_polarity_set, + .int_polarity_get = dal_rtl8367d_int_polarity_get, + .int_control_set = dal_rtl8367d_int_control_set, + .int_control_get = dal_rtl8367d_int_control_get, + .int_status_set = dal_rtl8367d_int_status_set, + .int_status_get = dal_rtl8367d_int_status_get, + .int_advanceInfo_get = dal_rtl8367d_int_advanceInfo_get, + + /* acl */ + .filter_igrAcl_init = dal_rtl8367d_filter_igrAcl_init, + .filter_igrAcl_field_add = dal_rtl8367d_filter_igrAcl_field_add, + .filter_igrAcl_cfg_add = dal_rtl8367d_filter_igrAcl_cfg_add, + .filter_igrAcl_cfg_del = dal_rtl8367d_filter_igrAcl_cfg_del, + .filter_igrAcl_cfg_delAll = dal_rtl8367d_filter_igrAcl_cfg_delAll, + .filter_igrAcl_cfg_get = dal_rtl8367d_filter_igrAcl_cfg_get, + .filter_igrAcl_unmatchAction_set = dal_rtl8367d_filter_igrAcl_unmatchAction_set, + .filter_igrAcl_unmatchAction_get = dal_rtl8367d_filter_igrAcl_unmatchAction_get, + .filter_igrAcl_state_set = dal_rtl8367d_filter_igrAcl_state_set, + .filter_igrAcl_state_get = dal_rtl8367d_filter_igrAcl_state_get, + .filter_igrAcl_template_set = dal_rtl8367d_filter_igrAcl_template_set, + .filter_igrAcl_template_get = dal_rtl8367d_filter_igrAcl_template_get, + .filter_igrAcl_field_sel_set = dal_rtl8367d_filter_igrAcl_field_sel_set, + .filter_igrAcl_field_sel_get = dal_rtl8367d_filter_igrAcl_field_sel_get, + .filter_iprange_set = dal_rtl8367d_filter_iprange_set, + .filter_iprange_get = dal_rtl8367d_filter_iprange_get, + .filter_vidrange_set = NULL, + .filter_vidrange_get = NULL, + .filter_portrange_set = NULL, + .filter_portrange_get = NULL, + .filter_igrAclPolarity_set = NULL, + .filter_igrAclPolarity_get = NULL, + + /* mirror */ + .mirror_portBased_set = dal_rtl8367d_mirror_portBased_set, + .mirror_portBased_get = dal_rtl8367d_mirror_portBased_get, + .mirror_portIso_set = dal_rtl8367d_mirror_portIso_set, + .mirror_portIso_get = dal_rtl8367d_mirror_portIso_get, + .mirror_vlanLeaky_set = dal_rtl8367d_mirror_vlanLeaky_set, + .mirror_vlanLeaky_get = dal_rtl8367d_mirror_vlanLeaky_get, + .mirror_isolationLeaky_set = dal_rtl8367d_mirror_isolationLeaky_set, + .mirror_isolationLeaky_get = dal_rtl8367d_mirror_isolationLeaky_get, + .mirror_keep_set = dal_rtl8367d_mirror_keep_set, + .mirror_keep_get = dal_rtl8367d_mirror_keep_get, + .mirror_override_set = dal_rtl8367d_mirror_override_set, + .mirror_override_get = dal_rtl8367d_mirror_override_get, + + /* port */ + .port_phyAutoNegoAbility_set = dal_rtl8367d_port_phyAutoNegoAbility_set, + .port_phyAutoNegoAbility_get = dal_rtl8367d_port_phyAutoNegoAbility_get, + .port_phyForceModeAbility_set = dal_rtl8367d_port_phyForceModeAbility_set, + .port_phyForceModeAbility_get = dal_rtl8367d_port_phyForceModeAbility_get, + .port_phyStatus_get = dal_rtl8367d_port_phyStatus_get, + .port_macForceLink_set = dal_rtl8367d_port_macForceLink_set, + .port_macForceLink_get = dal_rtl8367d_port_macForceLink_get, + .port_macForceLinkExt_set = dal_rtl8367d_port_macForceLinkExt_set, + .port_macForceLinkExt_get = dal_rtl8367d_port_macForceLinkExt_get, + .port_macStatus_get = dal_rtl8367d_port_macStatus_get, + .port_macLocalLoopbackEnable_set = dal_rtl8367d_port_macLocalLoopbackEnable_set, + .port_macLocalLoopbackEnable_get = dal_rtl8367d_port_macLocalLoopbackEnable_get, + .port_phyReg_set = dal_rtl8367d_port_phyReg_set, + .port_phyReg_get = dal_rtl8367d_port_phyReg_get, + .port_phyOCPReg_set = dal_rtl8367d_port_phyOCPReg_set, + .port_phyOCPReg_get = dal_rtl8367d_port_phyOCPReg_get, + .port_backpressureEnable_set = dal_rtl8367d_port_backpressureEnable_set, + .port_backpressureEnable_get = dal_rtl8367d_port_backpressureEnable_get, + .port_adminEnable_set = dal_rtl8367d_port_adminEnable_set, + .port_adminEnable_get = dal_rtl8367d_port_adminEnable_get, + .port_isolation_set = dal_rtl8367d_port_isolation_set, + .port_isolation_get = dal_rtl8367d_port_isolation_get, + .port_rgmiiDelayExt_set = dal_rtl8367d_port_rgmiiDelayExt_set, + .port_rgmiiDelayExt_get = dal_rtl8367d_port_rgmiiDelayExt_get, + .port_phyEnableAll_set = dal_rtl8367d_port_phyEnableAll_set, + .port_phyEnableAll_get = dal_rtl8367d_port_phyEnableAll_get, + .port_efid_set = NULL, + .port_efid_get = NULL, + .port_phyComboPortMedia_set = dal_rtl8367d_port_phyComboPortMedia_set, + .port_phyComboPortMedia_get = dal_rtl8367d_port_phyComboPortMedia_get, + .port_rtctEnable_set = dal_rtl8367d_port_rtctEnable_set, + .port_rtctDisable_set = dal_rtl8367d_port_rtctDisable_set, + .port_rtctResult_get = dal_rtl8367d_port_rtctResult_get, + .port_sds_reset = NULL, + .port_sgmiiLinkStatus_get = dal_rtl8367d_port_sgmiiLinkStatus_get, + .port_sgmiiNway_set = dal_rtl8367d_port_sgmiiNway_set, + .port_sgmiiNway_get = dal_rtl8367d_port_sgmiiNway_get, + .port_fiberAbilityExt_set = NULL, + .port_fiberAbilityExt_get = NULL, + .port_autoDos_set = dal_rtl8367d_port_autoDos_set, + .port_autoDos_get = dal_rtl8367d_port_autoDos_get, + .port_fiberAbility_set = dal_rtl8367d_port_fiberAbility_set, + .port_fiberAbility_get = dal_rtl8367d_port_fiberAbility_get, + .port_phyMdx_set = dal_rtl8367d_port_phyMdx_set, + .port_phyMdx_get = dal_rtl8367d_port_phyMdx_get, + .port_phyMdxStatus_get = dal_rtl8367d_port_phyMdxStatus_get, + .port_phyTestMode_set = dal_rtl8367d_port_phyTestMode_set, + .port_phyTestMode_get = dal_rtl8367d_port_phyTestMode_get, + + /* Trap */ + .trap_unknownUnicastPktAction_set = dal_rtl8367d_trap_unknownUnicastPktAction_set, + .trap_unknownUnicastPktAction_get = dal_rtl8367d_trap_unknownUnicastPktAction_get, + .trap_unknownMacPktAction_set = NULL, + .trap_unknownMacPktAction_get = NULL, + .trap_unmatchMacPktAction_set = NULL, + .trap_unmatchMacPktAction_get = NULL, + .trap_unmatchMacMoving_set = dal_rtl8367d_trap_unmatchMacMoving_set, + .trap_unmatchMacMoving_get = dal_rtl8367d_trap_unmatchMacMoving_get, + .trap_unknownMcastPktAction_set = dal_rtl8367d_trap_unknownMcastPktAction_set, + .trap_unknownMcastPktAction_get = dal_rtl8367d_trap_unknownMcastPktAction_get, + .trap_lldpEnable_set = dal_rtl8367d_trap_lldpEnable_set, + .trap_lldpEnable_get = dal_rtl8367d_trap_lldpEnable_get, + .trap_reasonTrapToCpuPriority_set = dal_rtl8367d_trap_reasonTrapToCpuPriority_set, + .trap_reasonTrapToCpuPriority_get = dal_rtl8367d_trap_reasonTrapToCpuPriority_get, + .trap_rmaAction_set = dal_rtl8367d_trap_rmaAction_set, + .trap_rmaAction_get = dal_rtl8367d_trap_rmaAction_get, + .trap_rmaKeepFormat_set = dal_rtl8367d_trap_rmaKeepFormat_set, + .trap_rmaKeepFormat_get = dal_rtl8367d_trap_rmaKeepFormat_get, + .trap_portUnknownMacPktAction_set = dal_rtl8367d_trap_portUnknownMacPktAction_set, + .trap_portUnknownMacPktAction_get = dal_rtl8367d_trap_portUnknownMacPktAction_get, + .trap_portUnmatchMacPktAction_set = dal_rtl8367d_trap_portUnmatchMacPktAction_set, + .trap_portUnmatchMacPktAction_get = dal_rtl8367d_trap_portUnmatchMacPktAction_get, + + /* IGMP */ + .igmp_init = NULL, + .igmp_state_set = NULL, + .igmp_state_get = NULL, + .igmp_static_router_port_set = NULL, + .igmp_static_router_port_get = NULL, + .igmp_protocol_set = dal_rtl8367d_igmp_protocol_set, + .igmp_protocol_get = dal_rtl8367d_igmp_protocol_get, + .igmp_fastLeave_set = NULL, + .igmp_fastLeave_get = NULL, + .igmp_maxGroup_set = NULL, + .igmp_maxGroup_get = NULL, + .igmp_currentGroup_get = NULL, + .igmp_tableFullAction_set = NULL, + .igmp_tableFullAction_get = NULL, + .igmp_checksumErrorAction_set = NULL, + .igmp_checksumErrorAction_get = NULL, + .igmp_leaveTimer_set = NULL, + .igmp_leaveTimer_get = NULL, + .igmp_queryInterval_set = NULL, + .igmp_queryInterval_get = NULL, + .igmp_robustness_set = NULL, + .igmp_robustness_get = NULL, + .igmp_dynamicRouterPortAllow_set = NULL, + .igmp_dynamicRouterPortAllow_get = NULL, + .igmp_dynamicRouterPort_get = NULL, + .igmp_suppressionEnable_set = NULL, + .igmp_suppressionEnable_get = NULL, + .igmp_portRxPktEnable_set = NULL, + .igmp_portRxPktEnable_get = NULL, + .igmp_groupInfo_get = NULL, + .igmp_ReportLeaveFwdAction_set = NULL, + .igmp_ReportLeaveFwdAction_get = NULL, + .igmp_dropLeaveZeroEnable_set = NULL, + .igmp_dropLeaveZeroEnable_get = NULL, + .igmp_bypassGroupRange_set = dal_rtl8367d_igmp_bypassGroupRange_set, + .igmp_bypassGroupRange_get = dal_rtl8367d_igmp_bypassGroupRange_get, + + /* Storm */ + .rate_stormControlMeterIdx_set = dal_rtl8367d_rate_stormControlMeterIdx_set, + .rate_stormControlMeterIdx_get = dal_rtl8367d_rate_stormControlMeterIdx_get, + .rate_stormControlPortEnable_set = dal_rtl8367d_rate_stormControlPortEnable_set, + .rate_stormControlPortEnable_get = dal_rtl8367d_rate_stormControlPortEnable_get, + .storm_bypass_set = dal_rtl8367d_storm_bypass_set, + .storm_bypass_get = dal_rtl8367d_storm_bypass_get, + .rate_stormControlExtPortmask_set = dal_rtl8367d_rate_stormControlExtPortmask_set, + .rate_stormControlExtPortmask_get = dal_rtl8367d_rate_stormControlExtPortmask_get, + .rate_stormControlExtEnable_set = dal_rtl8367d_rate_stormControlExtEnable_set, + .rate_stormControlExtEnable_get = dal_rtl8367d_rate_stormControlExtEnable_get, + .rate_stormControlExtMeterIdx_set = dal_rtl8367d_rate_stormControlExtMeterIdx_set, + .rate_stormControlExtMeterIdx_get = dal_rtl8367d_rate_stormControlExtMeterIdx_get, + + /* Rate */ + .rate_shareMeter_set = dal_rtl8367d_rate_shareMeter_set, + .rate_shareMeter_get = dal_rtl8367d_rate_shareMeter_get, + .rate_shareMeterBucket_set = dal_rtl8367d_rate_shareMeterBucket_set, + .rate_shareMeterBucket_get = dal_rtl8367d_rate_shareMeterBucket_get, + .rate_igrBandwidthCtrlRate_set = dal_rtl8367d_rate_igrBandwidthCtrlRate_set, + .rate_igrBandwidthCtrlRate_get = dal_rtl8367d_rate_igrBandwidthCtrlRate_get, + .rate_egrBandwidthCtrlRate_set = dal_rtl8367d_rate_egrBandwidthCtrlRate_set, + .rate_egrBandwidthCtrlRate_get = dal_rtl8367d_rate_egrBandwidthCtrlRate_get, + .rate_egrQueueBwCtrlEnable_set = dal_rtl8367d_rate_egrQueueBwCtrlEnable_set, + .rate_egrQueueBwCtrlEnable_get = dal_rtl8367d_rate_egrQueueBwCtrlEnable_get, + .rate_egrQueueBwCtrlRate_set = dal_rtl8367d_rate_egrQueueBwCtrlRate_set, + .rate_egrQueueBwCtrlRate_get = dal_rtl8367d_rate_egrQueueBwCtrlRate_get, + + /* I2C */ + .i2c_init = NULL, + .i2c_data_read = NULL, + .i2c_data_write = NULL, + .i2c_mode_set = NULL, + .i2c_mode_get = NULL, + .i2c_gpioPinGroup_set = NULL, + .i2c_gpioPinGroup_get = NULL, +#if 0 + /*PTP*/ + .ptp_init = dal_rtl8367d_ptp_init, + .ptp_mac_set = dal_rtl8367d_ptp_mac_set, + .ptp_mac_get = dal_rtl8367d_ptp_mac_get, + .ptp_tpid_set = dal_rtl8367d_ptp_tpid_set, + .ptp_tpid_get = dal_rtl8367d_ptp_tpid_get, + .ptp_refTime_set = dal_rtl8367d_ptp_refTime_set, + .ptp_refTime_get = dal_rtl8367d_ptp_refTime_get, + .ptp_refTimeAdjust_set = dal_rtl8367d_ptp_refTimeAdjust_set, + .ptp_refTimeEnable_set = dal_rtl8367d_ptp_refTimeEnable_set, + .ptp_refTimeEnable_get = dal_rtl8367d_ptp_refTimeEnable_get, + .ptp_portEnable_set = dal_rtl8367d_ptp_portEnable_set, + .ptp_portEnable_get = dal_rtl8367d_ptp_portEnable_get, + .ptp_portTimestamp_get = dal_rtl8367d_ptp_portTimestamp_get, + .ptp_intControl_set = dal_rtl8367d_ptp_intControl_set, + .ptp_intControl_get = dal_rtl8367d_ptp_intControl_get, + .ptp_intStatus_get = dal_rtl8367d_ptp_intStatus_get, + .ptp_portIntStatus_set = dal_rtl8367d_ptp_portIntStatus_set, + .ptp_portIntStatus_get = dal_rtl8367d_ptp_portIntStatus_get, + .ptp_portTrap_set = dal_rtl8367d_ptp_portTrap_set, + .ptp_portTrap_get = dal_rtl8367d_ptp_portTrap_get, +#endif + /*QoS*/ + .qos_init = dal_rtl8367d_qos_init, + .qos_priSel_set = dal_rtl8367d_qos_priSel_set, + .qos_priSel_get = dal_rtl8367d_qos_priSel_get, + .qos_1pPriRemap_set = dal_rtl8367d_qos_1pPriRemap_set, + .qos_1pPriRemap_get = dal_rtl8367d_qos_1pPriRemap_get, + .qos_1pRemarkSrcSel_set = dal_rtl8367d_qos_1pRemarkSrcSel_set, + .qos_1pRemarkSrcSel_get = dal_rtl8367d_qos_1pRemarkSrcSel_get, + .qos_dscpPriRemap_set = dal_rtl8367d_qos_dscpPriRemap_set, + .qos_dscpPriRemap_get = dal_rtl8367d_qos_dscpPriRemap_get, + .qos_portPri_set = dal_rtl8367d_qos_portPri_set, + .qos_portPri_get = dal_rtl8367d_qos_portPri_get, + .qos_queueNum_set = dal_rtl8367d_qos_queueNum_set, + .qos_queueNum_get = dal_rtl8367d_qos_queueNum_get, + .qos_priMap_set = dal_rtl8367d_qos_priMap_set, + .qos_priMap_get = dal_rtl8367d_qos_priMap_get, + .qos_schedulingQueue_set = dal_rtl8367d_qos_schedulingQueue_set, + .qos_schedulingQueue_get = dal_rtl8367d_qos_schedulingQueue_get, + .qos_1pRemarkEnable_set = dal_rtl8367d_qos_1pRemarkEnable_set, + .qos_1pRemarkEnable_get = dal_rtl8367d_qos_1pRemarkEnable_get, + .qos_1pRemark_set = dal_rtl8367d_qos_1pRemark_set, + .qos_1pRemark_get = dal_rtl8367d_qos_1pRemark_get, + .qos_dscpRemarkEnable_set = dal_rtl8367d_qos_dscpRemarkEnable_set, + .qos_dscpRemarkEnable_get = dal_rtl8367d_qos_dscpRemarkEnable_get, + .qos_dscpRemark_set = dal_rtl8367d_qos_dscpRemark_set, + .qos_dscpRemark_get = dal_rtl8367d_qos_dscpRemark_get, + .qos_dscpRemarkSrcSel_set = dal_rtl8367d_qos_dscpRemarkSrcSel_set, + .qos_dscpRemarkSrcSel_get = dal_rtl8367d_qos_dscpRemarkSrcSel_get, + .qos_dscpRemark2Dscp_set = NULL, + .qos_dscpRemark2Dscp_get = NULL, + .qos_portPriSelIndex_set = dal_rtl8367d_qos_portPriSelIndex_set, + .qos_portPriSelIndex_get = dal_rtl8367d_qos_portPriSelIndex_get, + .qos_schedulingType_set = dal_rtl8367d_qos_schedulingType_set, + .qos_schedulingType_get = dal_rtl8367d_qos_schedulingType_get, + + + /*VLAN*/ + .vlan_init = dal_rtl8367d_vlan_init, + .vlan_set = dal_rtl8367d_vlan_set, + .vlan_get = dal_rtl8367d_vlan_get, + .vlan_egrFilterEnable_set = dal_rtl8367d_vlan_egrFilterEnable_set, + .vlan_egrFilterEnable_get = dal_rtl8367d_vlan_egrFilterEnable_get, + .vlan_mbrCfg_set = NULL, + .vlan_mbrCfg_get = NULL, + .vlan_portPvid_set = dal_rtl8367d_vlan_portPvid_set, + .vlan_portPvid_get = dal_rtl8367d_vlan_portPvid_get, + .vlan_portIgrFilterEnable_set = dal_rtl8367d_vlan_portIgrFilterEnable_set, + .vlan_portIgrFilterEnable_get = dal_rtl8367d_vlan_portIgrFilterEnable_get, + .vlan_portAcceptFrameType_set = dal_rtl8367d_vlan_portAcceptFrameType_set, + .vlan_portAcceptFrameType_get = dal_rtl8367d_vlan_portAcceptFrameType_get, + .vlan_tagMode_set = dal_rtl8367d_vlan_tagMode_set, + .vlan_tagMode_get = dal_rtl8367d_vlan_tagMode_get, + .vlan_transparent_set = dal_rtl8367d_vlan_transparent_set, + .vlan_transparent_get = dal_rtl8367d_vlan_transparent_get, + .vlan_keep_set = dal_rtl8367d_vlan_keep_set, + .vlan_keep_get = dal_rtl8367d_vlan_keep_get, + .vlan_stg_set = dal_rtl8367d_vlan_stg_set, + .vlan_stg_get = dal_rtl8367d_vlan_stg_get, + .vlan_protoAndPortBasedVlan_add = NULL, + .vlan_protoAndPortBasedVlan_get = NULL, + .vlan_protoAndPortBasedVlan_del = NULL, + .vlan_protoAndPortBasedVlan_delAll = NULL, + .vlan_portFid_set = dal_rtl8367d_vlan_portFid_set, + .vlan_portFid_get = dal_rtl8367d_vlan_portFid_get, + .vlan_UntagDscpPriorityEnable_set = NULL, + .vlan_UntagDscpPriorityEnable_get = NULL, + .stp_mstpState_set = dal_rtl8367d_stp_mstpState_set, + .stp_mstpState_get = dal_rtl8367d_stp_mstpState_get, + .vlan_reservedVidAction_set = dal_rtl8367d_vlan_reservedVidAction_set, + .vlan_reservedVidAction_get = dal_rtl8367d_vlan_reservedVidAction_get, + .vlan_realKeepRemarkEnable_set = dal_rtl8367d_vlan_realKeepRemarkEnable_set, + .vlan_realKeepRemarkEnable_get = dal_rtl8367d_vlan_realKeepRemarkEnable_get, + .vlan_reset = dal_rtl8367d_vlan_reset, + + /*dot1x*/ + .dot1x_unauthPacketOper_set = dal_rtl8367d_dot1x_unauthPacketOper_set, + .dot1x_unauthPacketOper_get = dal_rtl8367d_dot1x_unauthPacketOper_get, + .dot1x_eapolFrame2CpuEnable_set = dal_rtl8367d_dot1x_eapolFrame2CpuEnable_set, + .dot1x_eapolFrame2CpuEnable_get = dal_rtl8367d_dot1x_eapolFrame2CpuEnable_get, + .dot1x_portBasedEnable_set = dal_rtl8367d_dot1x_portBasedEnable_set, + .dot1x_portBasedEnable_get = dal_rtl8367d_dot1x_portBasedEnable_get, + .dot1x_portBasedAuthStatus_set = dal_rtl8367d_dot1x_portBasedAuthStatus_set, + .dot1x_portBasedAuthStatus_get = dal_rtl8367d_dot1x_portBasedAuthStatus_get, + .dot1x_portBasedDirection_set = dal_rtl8367d_dot1x_portBasedDirection_set, + .dot1x_portBasedDirection_get = dal_rtl8367d_dot1x_portBasedDirection_get, + .dot1x_macBasedEnable_set = NULL, + .dot1x_macBasedEnable_get = NULL, + .dot1x_macBasedAuthMac_add = NULL, + .dot1x_macBasedAuthMac_del = NULL, + .dot1x_macBasedDirection_set = NULL, + .dot1x_macBasedDirection_get = NULL, + .dot1x_guestVlan_set = NULL, + .dot1x_guestVlan_get = NULL, + .dot1x_guestVlan2Auth_set = NULL, + .dot1x_guestVlan2Auth_get = NULL, + + /*SVLAN*/ + .svlan_init = dal_rtl8367d_svlaninit, + .svlan_servicePort_add = dal_rtl8367d_svlanservicePort_add, + .svlan_servicePort_get = dal_rtl8367d_svlanservicePort_get, + .svlan_servicePort_del = dal_rtl8367d_svlanservicePort_del, + .svlan_tpidEntry_set = dal_rtl8367d_svlantpidEntry_set, + .svlan_tpidEntry_get = dal_rtl8367d_svlantpidEntry_get, + .svlan_priorityRef_set = dal_rtl8367d_svlanpriorityRef_set, + .svlan_priorityRef_get = dal_rtl8367d_svlanpriorityRef_get, + .svlan_memberPortEntry_set = dal_rtl8367d_svlanmemberPortEntry_set, + .svlan_memberPortEntry_get = dal_rtl8367d_svlanmemberPortEntry_get, + .svlan_memberPortEntry_adv_set = NULL, + .svlan_memberPortEntry_adv_get = NULL, + .svlan_defaultSvlan_set = dal_rtl8367d_svlandefaultSvlan_set, + .svlan_defaultSvlan_get = dal_rtl8367d_svlandefaultSvlan_get, + .svlan_c2s_add = dal_rtl8367d_svlanc2s_add, + .svlan_c2s_del = dal_rtl8367d_svlanc2s_del, + .svlan_c2s_get = dal_rtl8367d_svlanc2s_get, + .svlan_untag_action_set = dal_rtl8367d_svlanuntag_action_set, + .svlan_untag_action_get = dal_rtl8367d_svlanuntag_action_get, + .svlan_unmatch_action_set = NULL, + .svlan_unmatch_action_get = NULL, + .svlan_dmac_vidsel_set = NULL, + .svlan_dmac_vidsel_get = NULL, + .svlan_ipmc2s_add = NULL, + .svlan_ipmc2s_del = NULL, + .svlan_ipmc2s_get = NULL, + .svlan_l2mc2s_add = NULL, + .svlan_l2mc2s_del = NULL, + .svlan_l2mc2s_get = NULL, + .svlan_sp2c_add = dal_rtl8367d_svlan_sp2c_add, + .svlan_sp2c_get = dal_rtl8367d_svlan_sp2c_get, + .svlan_sp2c_del = dal_rtl8367d_svlan_sp2c_del, + .svlan_lookupType_set = NULL, + .svlan_lookupType_get = NULL, + .svlan_trapPri_set = dal_rtl8367d_svlantrapPri_set, + .svlan_trapPri_get = dal_rtl8367d_svlantrapPri_get, + .svlan_unassign_action_set = dal_rtl8367d_svlanunassign_action_set, + .svlan_unassign_action_get = dal_rtl8367d_svlanunassign_action_get, + + /*RLDP*/ + .rldp_config_set = dal_rtl8367d_rldp_config_set, + .rldp_config_get = dal_rtl8367d_rldp_config_get, + .rldp_portConfig_set = dal_rtl8367d_rldp_portConfig_set, + .rldp_portConfig_get = dal_rtl8367d_rldp_portConfig_get, + .rldp_status_get = dal_rtl8367d_rldp_status_get, + .rldp_portStatus_get = dal_rtl8367d_rldp_portStatus_get, + .rldp_portStatus_set = dal_rtl8367d_rldp_portStatus_set, + .rldp_portLoopPair_get = dal_rtl8367d_rldp_portLoopPair_get, + + + /*trunk*/ + .trunk_port_set = dal_rtl8367d_trunk_port_set, + .trunk_port_get = dal_rtl8367d_trunk_port_get, + .trunk_distributionAlgorithm_set = dal_rtl8367d_trunk_distributionAlgorithm_set, + .trunk_distributionAlgorithm_get = dal_rtl8367d_trunk_distributionAlgorithm_get, + .trunk_trafficSeparate_set = dal_rtl8367d_trunk_trafficSeparate_set, + .trunk_trafficSeparate_get = dal_rtl8367d_trunk_trafficSeparate_get, + .trunk_mode_set = dal_rtl8367d_trunk_mode_set, + .trunk_mode_get = dal_rtl8367d_trunk_mode_get, + .trunk_trafficPause_set = dal_rtl8367d_trunk_trafficPause_set, + .trunk_trafficPause_get = dal_rtl8367d_trunk_trafficPause_get, + .trunk_hashMappingTable_set = dal_rtl8367d_trunk_hashMappingTable_set, + .trunk_hashMappingTable_get = dal_rtl8367d_trunk_hashMappingTable_get, + .trunk_portQueueEmpty_get = dal_rtl8367d_trunk_portQueueEmpty_get, + + /*leaky*/ + .leaky_vlan_set = dal_rtl8367d_leaky_vlan_set, + .leaky_vlan_get = dal_rtl8367d_leaky_vlan_get, + .leaky_portIsolation_set = dal_rtl8367d_leaky_portIsolation_set, + .leaky_portIsolation_get = dal_rtl8367d_leaky_portIsolation_get, + + /*GPIO*/ + .gpio_input_get = dal_rtl8367d_gpio_input_get, + .gpio_output_set = dal_rtl8367d_gpio_output_set, + .gpio_output_get = dal_rtl8367d_gpio_output_get, + .gpio_state_set = dal_rtl8367d_gpio_state_set, + .gpio_state_get = dal_rtl8367d_gpio_state_get, + .gpio_mode_set = dal_rtl8367d_gpio_mode_set, + .gpio_mode_get = dal_rtl8367d_gpio_mode_get, + .gpio_aclEnClear_set = dal_rtl8367d_gpio_aclEnClear_set, + .gpio_aclEnClear_get = dal_rtl8367d_gpio_aclEnClear_get, + + /*ASIC*/ + .asic_setAsicReg = rtl8367d_setAsicReg, + .asic_getAsicReg = rtl8367d_getAsicReg, + .asic_setAsicPHYOCPReg = dal_rtl8367d_setAsicPHYOCPReg, + .asic_getAsicPHYOCPReg = dal_rtl8367d_getAsicPHYOCPReg, + .asic_setAsicPHYReg = dal_rtl8367d_setAsicPHYReg, + .asic_getAsicPHYReg = dal_rtl8367d_getAsicPHYReg, + +}; + +/* + * Macro Declaration + */ + +/* + * Function Declaration + */ + + +/* Module Name : */ + +/* Function Name: + * dal_rtl8367d_mapper_get + * Description: + * Get DAL mapper function + * Input: + * None + * Output: + * None + * Return: + * dal_mapper_t * - mapper pointer + * Note: + */ +dal_mapper_t *dal_rtl8367d_mapper_get(void) +{ + + return &dal_rtl8367d_mapper; +} /* end of dal_rtl8367d_mapper_get */ + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_mapper.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_mapper.h new file mode 100644 index 00000000..cdf318c3 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_mapper.h @@ -0,0 +1,54 @@ + +/* + * Copyright(c) Realtek Semiconductor Corporation, 2011 + * All rights reserved. + * + * Purpose : Enterprise Switch RTK API mapper table + * + * Feature : + * + */ + +#ifndef __DAL_RTL8367D_MAPPER_H__ +#define __DAL_RTL8367D_MAPPER_H__ + +/* + * Include Files + */ +#include +#include +#include + + +/* + * Symbol Definition + */ + +/* + * Data Declaration + */ + +/* + * Macro Declaration + */ + +/* + * Function Declaration + */ + + +/* Function Name: + * dal_rtl8367d_mapper_get + * Description: + * Get DAL mapper function + * Input: + * None + * Output: + * None + * Return: + * dal_mapper_t * - mapper pointer + * Note: + */ +extern dal_mapper_t *dal_rtl8367d_mapper_get(void); + +#endif /* __DAL_RTL8367D_MAPPER_H__ */ diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_mirror.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_mirror.c new file mode 100644 index 00000000..0424a35b --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_mirror.c @@ -0,0 +1,534 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8367C + * Feature : Here is a list of all functions and variables in Mirror module. + * + */ + +#include +#include +#include +#include + + +/* Function Name: + * dal_rtl8367d_mirror_portBased_set + * Description: + * Set port mirror function. + * Input: + * mirroring_port - Monitor port. + * pMirrored_rx_portmask - Rx mirror port mask. + * pMirrored_tx_portmask - Tx mirror port mask. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * RT_ERR_PORT_MASK - Invalid portmask. + * Note: + * The API is to set mirror function of source port and mirror port. + * The mirror port can only be set to one port and the TX and RX mirror ports + * should be identical. + */ +rtk_api_ret_t dal_rtl8367d_mirror_portBased_set(rtk_port_t mirroring_port, rtk_portmask_t *pMirrored_rx_portmask, rtk_portmask_t *pMirrored_tx_portmask) +{ + rtk_api_ret_t retVal; + rtk_uint32 rxPmask; + rtk_uint32 txPmask; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check port valid */ + RTK_CHK_PORT_VALID(mirroring_port); + + if(NULL == pMirrored_rx_portmask) + return RT_ERR_NULL_POINTER; + + if(NULL == pMirrored_tx_portmask) + return RT_ERR_NULL_POINTER; + + RTK_CHK_PORTMASK_VALID(pMirrored_rx_portmask); + + RTK_CHK_PORTMASK_VALID(pMirrored_tx_portmask); + + /*mirror port != source port*/ + if(RTK_PORTMASK_IS_PORT_SET((*pMirrored_tx_portmask), mirroring_port) || RTK_PORTMASK_IS_PORT_SET((*pMirrored_rx_portmask), mirroring_port)) + return RT_ERR_PORT_MASK; + + /* Configure source portmask */ + if ((retVal = rtk_switch_portmask_L2P_get(pMirrored_rx_portmask, &rxPmask)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtk_switch_portmask_L2P_get(pMirrored_tx_portmask, &txPmask)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_MIRROR_SRC_PMSK, RTL8367D_MIRROR_TX_PMSK_MASK, txPmask)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_MIRROR_SRC_PMSK, RTL8367D_MIRROR_RX_PMSK_MASK, rxPmask)) != RT_ERR_OK) + return retVal; + + /* Configure monitor(destination) port */ + if((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_MIRROR_CTRL, RTL8367D_MIRROR_MONITOR_PORT_MASK, rtk_switch_port_L2P_get(mirroring_port))) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; + +} + +/* Function Name: + * dal_rtl8367d_mirror_portBased_get + * Description: + * Get port mirror function. + * Input: + * None + * Output: + * pMirroring_port - Monitor port. + * pMirrored_rx_portmask - Rx mirror port mask. + * pMirrored_tx_portmask - Tx mirror port mask. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API is to get mirror function of source port and mirror port. + */ +rtk_api_ret_t dal_rtl8367d_mirror_portBased_get(rtk_port_t *pMirroring_port, rtk_portmask_t *pMirrored_rx_portmask, rtk_portmask_t *pMirrored_tx_portmask) +{ + rtk_api_ret_t retVal; + rtk_uint32 rxPmask; + rtk_uint32 txPmask; + rtk_uint32 mport; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pMirrored_rx_portmask) + return RT_ERR_NULL_POINTER; + + if(NULL == pMirrored_tx_portmask) + return RT_ERR_NULL_POINTER; + + if(NULL == pMirroring_port) + return RT_ERR_NULL_POINTER; + + /* Get source portmask */ + if((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_MIRROR_SRC_PMSK, RTL8367D_MIRROR_TX_PMSK_MASK, &txPmask)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_MIRROR_SRC_PMSK, RTL8367D_MIRROR_RX_PMSK_MASK, &rxPmask)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtk_switch_portmask_P2L_get(txPmask, pMirrored_tx_portmask)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtk_switch_portmask_P2L_get(rxPmask, pMirrored_rx_portmask)) != RT_ERR_OK) + return retVal; + + /* Get monitor(destination) port */ + if((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_MIRROR_CTRL, RTL8367D_MIRROR_MONITOR_PORT_MASK, &mport)) != RT_ERR_OK) + return retVal; + + *pMirroring_port = rtk_switch_port_P2L_get(mport); + return RT_ERR_OK; + +} + +/* Function Name: + * dal_rtl8367d_mirror_portIso_set + * Description: + * Set mirror port isolation. + * Input: + * enable |Mirror isolation status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid enable input + * Note: + * The API is to set mirror isolation function that prevent normal forwarding packets to miror port. + */ +rtk_api_ret_t dal_rtl8367d_mirror_portIso_set(rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + rtk_uint32 isoEn; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (enable >= RTK_ENABLE_END) + return RT_ERR_ENABLE; + + isoEn = (enable == ENABLED) ? 1 : 0; + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_MIRROR_CTRL, RTL8367D_MIRROR_ISO_OFFSET, isoEn)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_mirror_portIso_get + * Description: + * Get mirror port isolation. + * Input: + * None + * Output: + * pEnable |Mirror isolation status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API is to get mirror isolation status. + */ +rtk_api_ret_t dal_rtl8367d_mirror_portIso_get(rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + rtk_uint32 isoEn; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pEnable) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_MIRROR_CTRL, RTL8367D_MIRROR_ISO_OFFSET, &isoEn)) != RT_ERR_OK) + return retVal; + + *pEnable = (isoEn == 1) ? ENABLED : DISABLED; + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_mirror_vlanLeaky_set + * Description: + * Set mirror VLAN leaky. + * Input: + * txenable -TX leaky enable. + * rxenable - RX leaky enable. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid enable input + * Note: + * The API is to set mirror VLAN leaky function forwarding packets to miror port. + */ +rtk_api_ret_t dal_rtl8367d_mirror_vlanLeaky_set(rtk_enable_t txenable, rtk_enable_t rxenable) +{ + rtk_api_ret_t retVal; + rtk_uint32 txEn, rxEn; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if ((txenable >= RTK_ENABLE_END) ||(rxenable >= RTK_ENABLE_END)) + return RT_ERR_ENABLE; + + txEn = (txenable == ENABLED) ? 1 : 0; + rxEn = (rxenable == ENABLED) ? 1 : 0; + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_MIRROR_CTRL2, RTL8367D_MIRROR_TX_VLAN_LEAKY_OFFSET, txEn)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_MIRROR_CTRL2, RTL8367D_MIRROR_RX_VLAN_LEAKY_OFFSET, rxEn)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_mirror_vlanLeaky_get + * Description: + * Get mirror VLAN leaky. + * Input: + * None + * Output: + * pTxenable - TX leaky enable. + * pRxenable - RX leaky enable. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API is to get mirror VLAN leaky status. + */ +rtk_api_ret_t dal_rtl8367d_mirror_vlanLeaky_get(rtk_enable_t *pTxenable, rtk_enable_t *pRxenable) +{ + rtk_api_ret_t retVal; + rtk_uint32 txEn, rxEn; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if( (NULL == pTxenable) || (NULL == pRxenable) ) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_MIRROR_CTRL2, RTL8367D_MIRROR_TX_VLAN_LEAKY_OFFSET, &txEn)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_MIRROR_CTRL2, RTL8367D_MIRROR_RX_VLAN_LEAKY_OFFSET, &rxEn)) != RT_ERR_OK) + return retVal; + + *pTxenable = (txEn == 1) ? ENABLED : DISABLED; + *pRxenable = (rxEn == 1) ? ENABLED : DISABLED; + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_mirror_isolationLeaky_set + * Description: + * Set mirror Isolation leaky. + * Input: + * txenable -TX leaky enable. + * rxenable - RX leaky enable. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid enable input + * Note: + * The API is to set mirror VLAN leaky function forwarding packets to miror port. + */ +rtk_api_ret_t dal_rtl8367d_mirror_isolationLeaky_set(rtk_enable_t txenable, rtk_enable_t rxenable) +{ + rtk_api_ret_t retVal; + rtk_uint32 txEn, rxEn; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if ((txenable >= RTK_ENABLE_END) ||(rxenable >= RTK_ENABLE_END)) + return RT_ERR_ENABLE; + + txEn = (txenable == ENABLED) ? 1 : 0; + rxEn = (rxenable == ENABLED) ? 1 : 0; + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_MIRROR_CTRL2, RTL8367D_MIRROR_TX_ISOLATION_LEAKY_OFFSET, txEn)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_MIRROR_CTRL2, RTL8367D_MIRROR_RX_ISOLATION_LEAKY_OFFSET, rxEn)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_mirror_isolationLeaky_get + * Description: + * Get mirror isolation leaky. + * Input: + * None + * Output: + * pTxenable - TX leaky enable. + * pRxenable - RX leaky enable. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API is to get mirror isolation leaky status. + */ +rtk_api_ret_t dal_rtl8367d_mirror_isolationLeaky_get(rtk_enable_t *pTxenable, rtk_enable_t *pRxenable) +{ + rtk_api_ret_t retVal; + rtk_uint32 txEn, rxEn; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if( (NULL == pTxenable) || (NULL == pRxenable) ) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_MIRROR_CTRL2, RTL8367D_MIRROR_TX_ISOLATION_LEAKY_OFFSET, &txEn)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_MIRROR_CTRL2, RTL8367D_MIRROR_RX_ISOLATION_LEAKY_OFFSET, &rxEn)) != RT_ERR_OK) + return retVal; + + *pTxenable = (txEn == 1) ? ENABLED : DISABLED; + *pRxenable = (rxEn == 1) ? ENABLED : DISABLED; + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_mirror_keep_set + * Description: + * Set mirror packet format keep. + * Input: + * mode - -mirror keep mode. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid enable input + * Note: + * The API is to set -mirror keep mode. + * The mirror keep mode is as following: + * - MIRROR_FOLLOW_VLAN + * - MIRROR_KEEP_ORIGINAL + * - MIRROR_KEEP_END + */ +rtk_api_ret_t dal_rtl8367d_mirror_keep_set(rtk_mirror_keep_t mode) +{ + rtk_api_ret_t retVal; + rtk_uint32 keepMode; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (mode >= MIRROR_KEEP_END) + return RT_ERR_ENABLE; + + keepMode = (mode == MIRROR_FOLLOW_VLAN) ? 0 : 1; + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_MIRROR_CTRL2, RTL8367D_MIRROR_REALKEEP_EN_OFFSET, keepMode)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_mirror_keep_get + * Description: + * Get mirror packet format keep. + * Input: + * None + * Output: + * pMode -mirror keep mode. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API is to get mirror keep mode. + * The mirror keep mode is as following: + * - MIRROR_FOLLOW_VLAN + * - MIRROR_KEEP_ORIGINAL + * - MIRROR_KEEP_END + */ +rtk_api_ret_t dal_rtl8367d_mirror_keep_get(rtk_mirror_keep_t *pMode) +{ + rtk_api_ret_t retVal; + rtk_uint32 keepMode; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pMode) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_MIRROR_CTRL2, RTL8367D_MIRROR_REALKEEP_EN_OFFSET, &keepMode)) != RT_ERR_OK) + return retVal; + + *pMode = (keepMode == 0) ? MIRROR_FOLLOW_VLAN : MIRROR_KEEP_ORIGINAL; + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_mirror_override_set + * Description: + * Set port mirror override function. + * Input: + * rxMirror - 1: output mirrored packet, 0: output normal forward packet + * txMirror - 1: output mirrored packet, 0: output normal forward packet + * aclMirror - 1: output mirrored packet, 0: output normal forward packet + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API is to set mirror override function. + * This function control the output format when a port output + * normal forward & mirrored packet at the same time. + */ +rtk_api_ret_t dal_rtl8367d_mirror_override_set(rtk_enable_t rxMirror, rtk_enable_t txMirror, rtk_enable_t aclMirror) +{ + rtk_api_ret_t retVal; + + if( (rxMirror >= RTK_ENABLE_END) || (txMirror >= RTK_ENABLE_END) || (aclMirror >= RTK_ENABLE_END)) + return RT_ERR_ENABLE; + + if((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_MIRROR_OVERRIDE_CFG, RTL8367D_MIRROR_RX_OVERRIDE_EN_OFFSET, (rxMirror == ENABLED) ? 1 : 0)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_MIRROR_OVERRIDE_CFG, RTL8367D_MIRROR_TX_OVERRIDE_EN_OFFSET, (txMirror == ENABLED) ? 1 : 0)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_MIRROR_OVERRIDE_CFG, RTL8367D_MIRROR_ACL_OVERRIDE_EN_OFFSET, (aclMirror == ENABLED) ? 1 : 0)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_mirror_override_get + * Description: + * Get port mirror override function. + * Input: + * None + * Output: + * pRxMirror - 1: output mirrored packet, 0: output normal forward packet + * pTxMirror - 1: output mirrored packet, 0: output normal forward packet + * pAclMirror - 1: output mirrored packet, 0: output normal forward packet + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Null Pointer + * Note: + * The API is to Get mirror override function. + * This function control the output format when a port output + * normal forward & mirrored packet at the same time. + */ +rtk_api_ret_t dal_rtl8367d_mirror_override_get(rtk_enable_t *pRxMirror, rtk_enable_t *pTxMirror, rtk_enable_t *pAclMirror) +{ + rtk_api_ret_t retVal; + rtk_uint32 txEn, rxEn, aclEn; + + if( (pRxMirror == NULL) || (pTxMirror == NULL) || (pAclMirror == NULL)) + return RT_ERR_ENABLE; + + if((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_MIRROR_OVERRIDE_CFG, RTL8367D_MIRROR_RX_OVERRIDE_EN_OFFSET, &rxEn)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_MIRROR_OVERRIDE_CFG, RTL8367D_MIRROR_TX_OVERRIDE_EN_OFFSET, &txEn)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_MIRROR_OVERRIDE_CFG, RTL8367D_MIRROR_ACL_OVERRIDE_EN_OFFSET, &aclEn)) != RT_ERR_OK) + return retVal; + + *pRxMirror = (rxEn == 1) ? ENABLED : DISABLED; + *pTxMirror = (txEn == 1) ? ENABLED : DISABLED; + *pAclMirror = (aclEn == 1) ? ENABLED : DISABLED; + return RT_ERR_OK; +} + + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_mirror.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_mirror.h new file mode 100644 index 00000000..c869df48 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_mirror.h @@ -0,0 +1,268 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8367/RTL8367C switch high-level API + * + * Feature : The file includes Mirror module high-layer API defination + * + */ + +#ifndef __DAL_RTL8367D_MIRROR_H__ +#define __DAL_RTL8367D_MIRROR_H__ + +#include + +/* Function Name: + * dal_rtl8367d_mirror_portBased_set + * Description: + * Set port mirror function. + * Input: + * mirroring_port - Monitor port. + * pMirrored_rx_portmask - Rx mirror port mask. + * pMirrored_tx_portmask - Tx mirror port mask. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * RT_ERR_PORT_MASK - Invalid portmask. + * Note: + * The API is to set mirror function of source port and mirror port. + * The mirror port can only be set to one port and the TX and RX mirror ports + * should be identical. + */ +extern rtk_api_ret_t dal_rtl8367d_mirror_portBased_set(rtk_port_t mirroring_port, rtk_portmask_t *pMirrored_rx_portmask, rtk_portmask_t *pMirrored_tx_portmask); + +/* Function Name: + * dal_rtl8367d_mirror_portBased_get + * Description: + * Get port mirror function. + * Input: + * None + * Output: + * pMirroring_port - Monitor port. + * pMirrored_rx_portmask - Rx mirror port mask. + * pMirrored_tx_portmask - Tx mirror port mask. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API is to get mirror function of source port and mirror port. + */ +extern rtk_api_ret_t dal_rtl8367d_mirror_portBased_get(rtk_port_t* pMirroring_port, rtk_portmask_t *pMirrored_rx_portmask, rtk_portmask_t *pMirrored_tx_portmask); + +/* Function Name: + * dal_rtl8367d_mirror_portIso_set + * Description: + * Set mirror port isolation. + * Input: + * enable |Mirror isolation status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid enable input + * Note: + * The API is to set mirror isolation function that prevent normal forwarding packets to miror port. + */ +extern rtk_api_ret_t dal_rtl8367d_mirror_portIso_set(rtk_enable_t enable); + +/* Function Name: + * dal_rtl8367d_mirror_portIso_get + * Description: + * Get mirror port isolation. + * Input: + * None + * Output: + * pEnable |Mirror isolation status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API is to get mirror isolation status. + */ +extern rtk_api_ret_t dal_rtl8367d_mirror_portIso_get(rtk_enable_t *pEnable); + +/* Function Name: + * dal_rtl8367d_mirror_vlanLeaky_set + * Description: + * Set mirror VLAN leaky. + * Input: + * txenable -TX leaky enable. + * rxenable - RX leaky enable. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid enable input + * Note: + * The API is to set mirror VLAN leaky function forwarding packets to miror port. + */ +extern rtk_api_ret_t dal_rtl8367d_mirror_vlanLeaky_set(rtk_enable_t txenable, rtk_enable_t rxenable); + + +/* Function Name: + * dal_rtl8367d_mirror_vlanLeaky_get + * Description: + * Get mirror VLAN leaky. + * Input: + * None + * Output: + * pTxenable - TX leaky enable. + * pRxenable - RX leaky enable. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API is to get mirror VLAN leaky status. + */ +extern rtk_api_ret_t dal_rtl8367d_mirror_vlanLeaky_get(rtk_enable_t *pTxenable, rtk_enable_t *pRxenable); + +/* Function Name: + * dal_rtl8367d_mirror_isolationLeaky_set + * Description: + * Set mirror Isolation leaky. + * Input: + * txenable -TX leaky enable. + * rxenable - RX leaky enable. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid enable input + * Note: + * The API is to set mirror VLAN leaky function forwarding packets to miror port. + */ +extern rtk_api_ret_t dal_rtl8367d_mirror_isolationLeaky_set(rtk_enable_t txenable, rtk_enable_t rxenable); + +/* Function Name: + * dal_rtl8367d_mirror_isolationLeaky_get + * Description: + * Get mirror isolation leaky. + * Input: + * None + * Output: + * pTxenable - TX leaky enable. + * pRxenable - RX leaky enable. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API is to get mirror isolation leaky status. + */ +extern rtk_api_ret_t dal_rtl8367d_mirror_isolationLeaky_get(rtk_enable_t *pTxenable, rtk_enable_t *pRxenable); + +/* Function Name: + * dal_rtl8367d_mirror_keep_set + * Description: + * Set mirror packet format keep. + * Input: + * mode - -mirror keep mode. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid enable input + * Note: + * The API is to set -mirror keep mode. + * The mirror keep mode is as following: + * - MIRROR_FOLLOW_VLAN + * - MIRROR_KEEP_ORIGINAL + * - MIRROR_KEEP_END + */ +extern rtk_api_ret_t dal_rtl8367d_mirror_keep_set(rtk_mirror_keep_t mode); + + +/* Function Name: + * dal_rtl8367d_mirror_keep_get + * Description: + * Get mirror packet format keep. + * Input: + * None + * Output: + * pMode -mirror keep mode. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API is to get mirror keep mode. + * The mirror keep mode is as following: + * - MIRROR_FOLLOW_VLAN + * - MIRROR_KEEP_ORIGINAL + * - MIRROR_KEEP_END + */ +extern rtk_api_ret_t dal_rtl8367d_mirror_keep_get(rtk_mirror_keep_t *pMode); + +/* Function Name: + * dal_rtl8367d_mirror_override_set + * Description: + * Set port mirror override function. + * Input: + * rxMirror - 1: output mirrored packet, 0: output normal forward packet + * txMirror - 1: output mirrored packet, 0: output normal forward packet + * aclMirror - 1: output mirrored packet, 0: output normal forward packet + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API is to set mirror override function. + * This function control the output format when a port output + * normal forward & mirrored packet at the same time. + */ +extern rtk_api_ret_t dal_rtl8367d_mirror_override_set(rtk_enable_t rxMirror, rtk_enable_t txMirror, rtk_enable_t aclMirror); + +/* Function Name: + * dal_rtl8367d_mirror_override_get + * Description: + * Get port mirror override function. + * Input: + * None + * Output: + * pRxMirror - 1: output mirrored packet, 0: output normal forward packet + * pTxMirror - 1: output mirrored packet, 0: output normal forward packet + * pAclMirror - 1: output mirrored packet, 0: output normal forward packet + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Null Pointer + * Note: + * The API is to Get mirror override function. + * This function control the output format when a port output + * normal forward & mirrored packet at the same time. + */ +extern rtk_api_ret_t dal_rtl8367d_mirror_override_get(rtk_enable_t *pRxMirror, rtk_enable_t *pTxMirror, rtk_enable_t *pAclMirror); + +#endif /* __DAL_RTL8367D_MIRROR_H__ */ + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_port.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_port.c new file mode 100644 index 00000000..637e50af --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_port.c @@ -0,0 +1,4392 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8367D + * Feature : Here is a list of all functions and variables in Port module. + * + */ + +#include +#include +#include +#include +#include + +#define RTL8367D_PORT_SDS_MODE_DISABLE 0x1f +#define RTL8367D_PORT_SDS_MODE_SGMII 0x2 +#define RTL8367D_PORT_SDS_MODE_HSGMII 0x12 +#define RTL8367D_PORT_SDS_MODE_1000X 0x4 +#define RTL8367D_PORT_SDS_MODE_100FX 0x5 +#define RTL8367D_PORT_SDS_MODE_1000X_100FX 0x7 +#define RTL8367D_PORT_SDS_MODE_FIBER_2P5G 0x16 + +#define RTL8367D_EXT_PORT_SPEED_10M 0x0 +#define RTL8367D_EXT_PORT_SPEED_100M 0x1 +#define RTL8367D_EXT_PORT_SPEED_1000M 0x2 +#define RTL8367D_EXT_PORT_SPEED_500M 0x3 +#define RTL8367D_EXT_PORT_SPEED_2500M 0x5 + +const rtk_uint32 HSGCfg[][2] = { {0x0427, 0x4E0C}, {0x0428, 0xAA00}, {0x0425, 0x5189}, {0x0424, 0x8414}, {0x0423, 0x1020}, {0x0410, 0x0002}, {0x0504, 0x051B}, {0x0421, 0x8E13}, {0x0422, 0x1140}}; +const rtk_uint32 SGCfg[][2] = { {0x0427, 0x4E0C}, {0x0428, 0xAA00}, {0x0425, 0x5189}, {0x0424, 0x8414}, {0x0423, 0x1020}, {0x0410, 0x0002}, {0x0484, 0x011B}, {0x0421, 0x8E13}, {0x0422, 0x1140}}; +const rtk_uint32 Fiber1000M100MCfg[][2] = { {0x0427, 0x4E0C}, {0x0428, 0xAA00}, {0x0425, 0x5189}, {0x0424, 0x8414}, {0x0423, 0x1020}, {0x0410, 0x0002}, {0x0484, 0x011B}, {0x0421, 0x8E13}, {0x0422, 0x1140}, {0x0040, 0x2100}, {0x0044, 0x0C01}, {0x0040, 0x1140}, {0x0044, 0x01A0}, {0x0001, 0x0F20}}; +const rtk_uint32 Fiber1000MCfg[][2] = { {0x0427, 0x4E0C}, {0x0428, 0xAA00}, {0x0425, 0x5189}, {0x0424, 0x8414}, {0x0423, 0x1020}, {0x0410, 0x0002}, {0x0484, 0x011B}, {0x0421, 0x8E13}, {0x0422, 0x1140}, {0x0040, 0x1140}, {0x0044, 0x01A0}}; +const rtk_uint32 Fiber100MCfg[][2] = { {0x0427, 0x4E0C}, {0x0428, 0xAA00}, {0x0425, 0x5189}, {0x0424, 0x8414}, {0x0423, 0x1020}, {0x0410, 0x0002}, {0x0484, 0x011B}, {0x0421, 0x8E13}, {0x0422, 0x1140}, {0x0040, 0x2100}, {0x0044, 0x0C01}}; +const rtk_uint32 Fiber2P5GCfg[][2] = { {0x0427, 0x4E0C}, {0x0428, 0xAA00}, {0x0425, 0x5189}, {0x0424, 0x8414}, {0x0423, 0x1020}, {0x0410, 0x0002}, {0x0504, 0x051B}, {0x0421, 0x8E13}, {0x0422, 0x1140}, {0x0040, 0x1140}, {0x0044, 0x01A0}}; +const rtk_uint32 SDSNctrlPatch[][2] = +{ + {0x6100, 0x2800}, + {0x6136, 0x0000}, + {0x6135, 0x7000}, + {0x6136, 0xc008}, + {0x6135, 0x7001}, + {0x6136, 0x405f}, + {0x6135, 0x7002}, + {0x6136, 0x1205}, + {0x6135, 0x7003}, + {0x6136, 0x2200}, + {0x6135, 0x7004}, + {0x6136, 0x4274}, + {0x6135, 0x7005}, + {0x6136, 0x4755}, + {0x6135, 0x7006}, + {0x6136, 0x2200}, + {0x6135, 0x7007}, + {0x6136, 0xc008}, + {0x6135, 0x7008}, + {0x6136, 0x6011}, + {0x6135, 0x7009}, + {0x6136, 0xac01}, + {0x6135, 0x700a}, + {0x6136, 0x0000}, + {0x6135, 0x700b}, + {0x6136, 0x8c01}, + {0x6135, 0x700c}, + {0x6136, 0x0000}, + {0x6135, 0x700d}, + {0x6136, 0x0800}, + {0x6135, 0x700e}, + {0x6136, 0xd301}, + {0x6135, 0x700f}, + {0x6136, 0xd4ff}, + {0x6135, 0x7010}, + {0x6136, 0xc007}, + {0x6135, 0x7011}, + {0x6136, 0x6000}, + {0x6135, 0x7012}, + {0x6136, 0x4000}, + {0x6135, 0x7013}, + {0x6136, 0x6000}, + {0x6135, 0x7014}, + {0x6136, 0x4000}, + {0x6135, 0x7015}, + {0x6136, 0xc008}, + {0x6135, 0x7016}, + {0x6136, 0x0800}, + {0x6135, 0x7017}, + {0x6136, 0xc008}, + {0x6135, 0x7018}, + {0x6136, 0x64f4}, + {0x6135, 0x7019}, + {0x6136, 0x120f}, + {0x6135, 0x701a}, + {0x6136, 0x64b4}, + {0x6135, 0x701b}, + {0x6136, 0xd000}, + {0x6135, 0x701c}, + {0x6136, 0xcf02}, + {0x6135, 0x701d}, + {0x6136, 0xce93}, + {0x6135, 0x701e}, + {0x6136, 0xcd4a}, + {0x6135, 0x701f}, + {0x6136, 0x1208}, + {0x6135, 0x7020}, + {0x6136, 0xd000}, + {0x6135, 0x7021}, + {0x6136, 0xcf20}, + {0x6135, 0x7022}, + {0x6136, 0xcee6}, + {0x6135, 0x7023}, + {0x6136, 0xcd02}, + {0x6135, 0x7024}, + {0x6136, 0x1208}, + {0x6135, 0x7025}, + {0x6136, 0xd000}, + {0x6135, 0x7026}, + {0x6136, 0xcf3f}, + {0x6135, 0x7027}, + {0x6136, 0xcd01}, + {0x6135, 0x7028}, + {0x6136, 0x1208}, + {0x6135, 0x7029}, + {0x6136, 0xd000}, + {0x6135, 0x702a}, + {0x6136, 0xcfcd}, + {0x6135, 0x702b}, + {0x6136, 0xcd00}, + {0x6135, 0x702c}, + {0x6136, 0x1208}, + {0x6135, 0x702d}, + {0x6136, 0xd000}, + {0x6135, 0x702e}, + {0x6136, 0xcf04}, + {0x6135, 0x702f}, + {0x6136, 0xcd02}, + {0x6135, 0x7030}, + {0x6136, 0x1208}, + {0x6135, 0x7031}, + {0x6136, 0xd004}, + {0x6135, 0x7032}, + {0x6136, 0xcf00}, + {0x6135, 0x7033}, + {0x6136, 0xcd01}, + {0x6135, 0x7034}, + {0x6136, 0x1208}, + {0x6135, 0x7035}, + {0x6136, 0xd000}, + {0x6135, 0x7036}, + {0x6136, 0xcfcd}, + {0x6135, 0x7037}, + {0x6136, 0xcd00}, + {0x6135, 0x7038}, + {0x6136, 0x1208}, + {0x6135, 0x7039}, + {0x6136, 0xcf00}, + {0x6135, 0x703a}, + {0x6136, 0xcd02}, + {0x6135, 0x703b}, + {0x6136, 0x1208}, + {0x6135, 0x703c}, + {0x6136, 0xcfcd}, + {0x6135, 0x703d}, + {0x6136, 0xcd00}, + {0x6135, 0x703e}, + {0x6136, 0x1208}, + {0x6135, 0x703f}, + {0x6136, 0xc008}, + {0x6135, 0x7040}, + {0x6136, 0x64f5}, + {0x6135, 0x7041}, + {0x6136, 0x120f}, + {0x6135, 0x7042}, + {0x6136, 0x64b5}, + {0x6135, 0x7043}, + {0x6136, 0xd000}, + {0x6135, 0x7044}, + {0x6136, 0xcf04}, + {0x6135, 0x7045}, + {0x6136, 0xce93}, + {0x6135, 0x7046}, + {0x6136, 0xcd4a}, + {0x6135, 0x7047}, + {0x6136, 0x1208}, + {0x6135, 0x7048}, + {0x6136, 0xd000}, + {0x6135, 0x7049}, + {0x6136, 0xcf20}, + {0x6135, 0x704a}, + {0x6136, 0xcee6}, + {0x6135, 0x704b}, + {0x6136, 0xcd02}, + {0x6135, 0x704c}, + {0x6136, 0x1208}, + {0x6135, 0x704d}, + {0x6136, 0xd000}, + {0x6135, 0x704e}, + {0x6136, 0xcf3f}, + {0x6135, 0x704f}, + {0x6136, 0xcd01}, + {0x6135, 0x7050}, + {0x6136, 0x1208}, + {0x6135, 0x7051}, + {0x6136, 0xd000}, + {0x6135, 0x7052}, + {0x6136, 0xcfcf}, + {0x6135, 0x7053}, + {0x6136, 0xcd00}, + {0x6135, 0x7054}, + {0x6136, 0x1208}, + {0x6135, 0x7055}, + {0x6136, 0xd000}, + {0x6135, 0x7056}, + {0x6136, 0xcf04}, + {0x6135, 0x7057}, + {0x6136, 0xcd02}, + {0x6135, 0x7058}, + {0x6136, 0x1208}, + {0x6135, 0x7059}, + {0x6136, 0xd004}, + {0x6135, 0x705a}, + {0x6136, 0xcf00}, + {0x6135, 0x705b}, + {0x6136, 0xcd01}, + {0x6135, 0x705c}, + {0x6136, 0x1208}, + {0x6135, 0x705d}, + {0x6136, 0xd000}, + {0x6135, 0x705e}, + {0x6136, 0xcfcf}, + {0x6135, 0x705f}, + {0x6136, 0xcd00}, + {0x6135, 0x7060}, + {0x6136, 0x1208}, + {0x6135, 0x7061}, + {0x6136, 0xcf00}, + {0x6135, 0x7062}, + {0x6136, 0xcd02}, + {0x6135, 0x7063}, + {0x6136, 0x1208}, + {0x6135, 0x7064}, + {0x6136, 0xcfcf}, + {0x6135, 0x7065}, + {0x6136, 0xcd00}, + {0x6135, 0x7066}, + {0x6136, 0x1208}, + {0x6135, 0x7067}, + {0x6136, 0xd000}, + {0x6135, 0x7068}, + {0x6136, 0xcf00}, + {0x6135, 0x7069}, + {0x6136, 0xce93}, + {0x6135, 0x706a}, + {0x6136, 0xcd4a}, + {0x6135, 0x706b}, + {0x6136, 0x1208}, + {0x6135, 0x706c}, + {0x6136, 0xd000}, + {0x6135, 0x706d}, + {0x6136, 0xcf00}, + {0x6135, 0x706e}, + {0x6136, 0xcee6}, + {0x6135, 0x706f}, + {0x6136, 0xcd02}, + {0x6135, 0x7070}, + {0x6136, 0x1208}, + {0x6135, 0x7071}, + {0x6136, 0xd000}, + {0x6135, 0x7072}, + {0x6136, 0xcf3f}, + {0x6135, 0x7073}, + {0x6136, 0xcd01}, + {0x6135, 0x7074}, + {0x6136, 0x1208}, + {0x6135, 0x7075}, + {0x6136, 0xd000}, + {0x6135, 0x7076}, + {0x6136, 0xcfcd}, + {0x6135, 0x7077}, + {0x6136, 0xcd00}, + {0x6135, 0x7078}, + {0x6136, 0x1208}, + {0x6135, 0x7079}, + {0x6136, 0xcfcf}, + {0x6135, 0x707a}, + {0x6136, 0x1208}, + {0x6135, 0x707b}, + {0x6136, 0x2200}, + {0x6135, 0x707c}, + {0x6102, 0x0000}, + {0x6101, 0x0420}, + {0x6100, 0x0000}, + {0x6102, 0x0000}, + {0x6104, 0x0200}, + {0x6103, 0x0400}, + {0x6101, 0x0000} +}; + +const rtk_uint32 RTCTPatch[][2] = +{ + {0xa436, 0x8160}, + {0xa438, 0x6de5}, + {0xa436, 0x8162}, + {0xa438, 0x9b52}, + {0xa436, 0x8164}, + {0xa438, 0x428f}, + {0xa436, 0x8166}, + {0xa438, 0xe961}, + {0xa436, 0x8174}, + {0xa438, 0x054b}, + {0xa436, 0x8176}, + {0xa438, 0x009a}, + {0xa436, 0x8178}, + {0xa438, 0xf5a9}, + {0xa436, 0x817a}, + {0xa438, 0xe69c}, + {0xa436, 0x8211}, + {0xa438, 0x2a9b}, + {0xa436, 0x8213}, + {0xa438, 0xa9cd}, + {0xa436, 0x8215}, + {0xa438, 0x7935}, + {0xa436, 0x8217}, + {0xa438, 0xaadf}, + {0xa436, 0x819f}, + {0xa438, 0xc313}, + {0xa436, 0x81b5}, + {0xa438, 0x1010}, + {0xa436, 0x81b7}, + {0xa438, 0xea03}, + {0xa436, 0x8186}, + {0xa438, 0x3501} +}; + +static rtk_api_ret_t _dal_rtl8367d_setAsicPHYOCPReg(rtk_uint32 phyNo, rtk_uint32 ocpAddr, rtk_uint32 ocpData ) +{ + ret_t retVal; + rtk_uint32 regData; + rtk_uint32 busyFlag, checkCounter; + rtk_uint32 ocpAddrPrefix, ocpAddr9_6, ocpAddr5_1; + + /*Check internal phy access busy or not*/ + retVal = rtl8367d_getAsicReg(RTL8367D_REG_INDRECT_ACCESS_STATUS, &busyFlag); + if(retVal != RT_ERR_OK) + return retVal; + + if(busyFlag) + return RT_ERR_BUSYWAIT_TIMEOUT; + + if ((retVal = rtl8367d_getAsicReg(RTL8367D_REG_FPGA_VER_CEN, ®Data)) != RT_ERR_OK) + return retVal; + + /* OCP prefix */ + if (regData == 0) + ocpAddrPrefix = ((ocpAddr & 0xFC00) >> 10); /* ASIC */ + else + ocpAddrPrefix = 0; /* FPGA */ + + if((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_GPHY_OCP_MSB_0, RTL8367D_CFG_CPU_OCPADR_MSB_MASK, ocpAddrPrefix)) != RT_ERR_OK) + return retVal; + + /*prepare access data*/ + retVal = rtl8367d_setAsicReg(RTL8367D_REG_INDRECT_ACCESS_WRITE_DATA, ocpData); + if(retVal != RT_ERR_OK) + return retVal; + + /*prepare access address*/ + ocpAddr9_6 = ((ocpAddr >> 6) & 0x000F); + ocpAddr5_1 = ((ocpAddr >> 1) & 0x001F); + regData = RTL8367D_PHY_BASE | (ocpAddr9_6 << 8) | (phyNo << RTL8367D_PHY_OFFSET) | ocpAddr5_1; + retVal = rtl8367d_setAsicReg(RTL8367D_REG_INDRECT_ACCESS_ADDRESS, regData); + if(retVal != RT_ERR_OK) + return retVal; + + /*Set WRITE Command*/ + retVal = rtl8367d_setAsicReg(RTL8367D_REG_INDRECT_ACCESS_CTRL, RTL8367D_CMD_MASK | RTL8367D_RW_MASK); + + checkCounter = 100; + while(checkCounter) + { + retVal = rtl8367d_getAsicReg(RTL8367D_REG_INDRECT_ACCESS_STATUS, &busyFlag); + if((retVal != RT_ERR_OK) || busyFlag) + { + checkCounter --; + if(0 == checkCounter) + return RT_ERR_BUSYWAIT_TIMEOUT; + } + else + { + checkCounter = 0; + } + } + + return retVal; +} + +static rtk_api_ret_t _dal_rtl8367d_getAsicPHYOCPReg(rtk_uint32 phyNo, rtk_uint32 ocpAddr, rtk_uint32 *pRegData ) +{ + ret_t retVal; + rtk_uint32 regData; + rtk_uint32 busyFlag,checkCounter; + rtk_uint32 ocpAddrPrefix, ocpAddr9_6, ocpAddr5_1; + + /*Check internal phy access busy or not*/ + retVal = rtl8367d_getAsicReg(RTL8367D_REG_INDRECT_ACCESS_STATUS, &busyFlag); + if(retVal != RT_ERR_OK) + return retVal; + + if(busyFlag) + return RT_ERR_BUSYWAIT_TIMEOUT; + + if ((retVal = rtl8367d_getAsicReg(RTL8367D_REG_FPGA_VER_CEN, ®Data)) != RT_ERR_OK) + return retVal; + + /* OCP prefix */ + if (regData == 0) + ocpAddrPrefix = ((ocpAddr & 0xFC00) >> 10); /* ASIC */ + else + ocpAddrPrefix = 0; /* FPGA */ + + if((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_GPHY_OCP_MSB_0, RTL8367D_CFG_CPU_OCPADR_MSB_MASK, ocpAddrPrefix)) != RT_ERR_OK) + return retVal; + + /*prepare access address*/ + ocpAddr9_6 = ((ocpAddr >> 6) & 0x000F); + ocpAddr5_1 = ((ocpAddr >> 1) & 0x001F); + regData = RTL8367D_PHY_BASE | (ocpAddr9_6 << 8) | (phyNo << RTL8367D_PHY_OFFSET) | ocpAddr5_1; + retVal = rtl8367d_setAsicReg(RTL8367D_REG_INDRECT_ACCESS_ADDRESS, regData); + if(retVal != RT_ERR_OK) + return retVal; + + /*Set READ Command*/ + retVal = rtl8367d_setAsicReg(RTL8367D_REG_INDRECT_ACCESS_CTRL, RTL8367D_CMD_MASK ); + if(retVal != RT_ERR_OK) + return retVal; + + checkCounter = 100; + while(checkCounter) + { + retVal = rtl8367d_getAsicReg(RTL8367D_REG_INDRECT_ACCESS_STATUS, &busyFlag); + if((retVal != RT_ERR_OK) || busyFlag) + { + checkCounter --; + if(0 == checkCounter) + return RT_ERR_FAILED; + } + else + { + checkCounter = 0; + } + } + + /*get PHY register*/ + retVal = rtl8367d_getAsicReg(RTL8367D_REG_INDRECT_ACCESS_READ_DATA, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + *pRegData = regData; + return RT_ERR_OK; +} + +static rtk_api_ret_t _dal_rtl8367d_setAsicPHYReg(rtk_uint32 phyNo, rtk_uint32 phyAddr, rtk_uint32 phyData ) +{ + rtk_uint32 ocp_addr; + + if(phyAddr > RTL8367D_PHY_REGNOMAX) + return RT_ERR_PHY_REG_ID; + + ocp_addr = 0xa400 + phyAddr*2; + + return _dal_rtl8367d_setAsicPHYOCPReg(phyNo, ocp_addr, phyData); +} + +static rtk_api_ret_t _dal_rtl8367d_getAsicPHYReg(rtk_uint32 phyNo, rtk_uint32 phyAddr, rtk_uint32 *pRegData ) +{ + rtk_uint32 ocp_addr; + + if(phyAddr > RTL8367D_PHY_REGNOMAX) + return RT_ERR_PHY_REG_ID; + + ocp_addr = 0xa400 + phyAddr*2; + + return _dal_rtl8367d_getAsicPHYOCPReg(phyNo, ocp_addr, pRegData); +} + +static rtk_api_ret_t _dal_rtl8367d_setAsicPortExtMode(rtk_uint32 id, rtk_uint32 mode) +{ + rtk_api_ret_t retVal; + rtk_uint32 mux; + rtk_uint32 i; + rtk_port_media_t media_type; + + if ((id >= 3) || (id == 0)) + return RT_ERR_OUT_OF_RANGE; + + if( (mode == MODE_EXT_TMII_MAC) || (mode == MODE_EXT_TMII_PHY) ) + { + if( (retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_BYPASS_LINE_RATE, id, 1)) != RT_ERR_OK) + return retVal; + } + else + { + if( (retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_BYPASS_LINE_RATE, id, 0)) != RT_ERR_OK) + return retVal; + } + + if (id == 1) + { + if (mode == MODE_EXT_DISABLE) + { + if((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_SDS_MISC, RTL8367D_CFG_SDS_MODE_MASK, RTL8367D_PORT_SDS_MODE_DISABLE)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_SDS_MISC, RTL8367D_MAC6_SEL_SDS0_OFFSET, 0)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_FIBER_CFG_2, RTL8367D_SDS_RX_DISABLE_MASK, 0)) != RT_ERR_OK) + return retVal; + } + else if ((mode == MODE_EXT_SGMII) || (mode == MODE_EXT_HSGMII) || (mode == MODE_EXT_1000X_100FX) || (mode == MODE_EXT_1000X) || (mode == MODE_EXT_100FX) || (mode == MODE_EXT_FIBER_2P5G)) + { + if ((retVal = dal_rtl8367d_port_phyComboPortMedia_get(UTP_PORT4, &media_type)) != RT_ERR_OK) + return retVal; + + if (media_type == PORT_MEDIA_FIBER) + { + /* SDS0 already used by port 4 */ + return RT_ERR_PORT_ID; + } + + if((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_SDS_MISC, RTL8367D_MAC6_SEL_SDS0_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + for(i = 0; i < sizeof(SDSNctrlPatch) / (sizeof(rtk_uint32) * 2); i++) + { + if( (retVal = rtl8367d_setAsicReg(SDSNctrlPatch[i][0], SDSNctrlPatch[i][1])) != RT_ERR_OK) + return retVal; + } + + switch (mode) + { + case MODE_EXT_SGMII: + for(i = 0; i < sizeof(SGCfg) / (sizeof(rtk_uint32) * 2); i++) + { + if( (retVal = rtl8367d_setAsicReg(RTL8367D_REG_SDS_INDACS_DATA, SGCfg[i][1])) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367d_setAsicReg(RTL8367D_REG_SDS_INDACS_ADR, SGCfg[i][0])) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367d_setAsicReg(RTL8367D_REG_SDS_INDACS_CMD, 0x00CD)) != RT_ERR_OK) + return retVal; + } + + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_FIBER_CFG_2, RTL8367D_SDS_RX_DISABLE_MASK, 0x1)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_SDS_MISC, RTL8367D_PA12PC_EN_S0_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_SDS_MISC, RTL8367D_PA33PC_EN_S0_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_SDS_MISC, RTL8367D_CFG_SDS_MODE_MASK, RTL8367D_PORT_SDS_MODE_SGMII)) != RT_ERR_OK) + return retVal; + + break; + case MODE_EXT_HSGMII: + for(i = 0; i < sizeof(HSGCfg) / (sizeof(rtk_uint32) * 2); i++) + { + if( (retVal = rtl8367d_setAsicReg(RTL8367D_REG_SDS_INDACS_DATA, HSGCfg[i][1])) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367d_setAsicReg(RTL8367D_REG_SDS_INDACS_ADR, HSGCfg[i][0])) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367d_setAsicReg(RTL8367D_REG_SDS_INDACS_CMD, 0x00CD)) != RT_ERR_OK) + return retVal; + } + + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_FIBER_CFG_2, RTL8367D_SDS_RX_DISABLE_MASK, 0x1)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_SDS_MISC, RTL8367D_PA12PC_EN_S0_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_SDS_MISC, RTL8367D_PA33PC_EN_S0_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_SDS_MISC, RTL8367D_CFG_SDS_MODE_MASK, RTL8367D_PORT_SDS_MODE_HSGMII)) != RT_ERR_OK) + return retVal; + + break; + case MODE_EXT_1000X_100FX: + for(i = 0; i < sizeof(Fiber1000M100MCfg) / (sizeof(rtk_uint32) * 2); i++) + { + if( (retVal = rtl8367d_setAsicReg(RTL8367D_REG_SDS_INDACS_DATA, Fiber1000M100MCfg[i][1])) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367d_setAsicReg(RTL8367D_REG_SDS_INDACS_ADR, Fiber1000M100MCfg[i][0])) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367d_setAsicReg(RTL8367D_REG_SDS_INDACS_CMD, 0x00CD)) != RT_ERR_OK) + return retVal; + } + + if( (retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_FIBER_CFG_2, RTL8367D_SDS_RX_DISABLE_MASK, 1)) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_SDS_MISC, RTL8367D_PA12PC_EN_S0_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_SDS_MISC, RTL8367D_PA33PC_EN_S0_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_SDS_MISC, RTL8367D_CFG_SDS_MODE_MASK, RTL8367D_PORT_SDS_MODE_1000X_100FX)) != RT_ERR_OK) + return retVal; + + break; + case MODE_EXT_1000X: + for(i = 0; i < sizeof(Fiber1000MCfg) / (sizeof(rtk_uint32) * 2); i++) + { + if( (retVal = rtl8367d_setAsicReg(RTL8367D_REG_SDS_INDACS_DATA, Fiber1000MCfg[i][1])) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367d_setAsicReg(RTL8367D_REG_SDS_INDACS_ADR, Fiber1000MCfg[i][0])) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367d_setAsicReg(RTL8367D_REG_SDS_INDACS_CMD, 0x00CD)) != RT_ERR_OK) + return retVal; + } + + if( (retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_FIBER_CFG_2, RTL8367D_SDS_RX_DISABLE_MASK, 1)) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_SDS_MISC, RTL8367D_PA12PC_EN_S0_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_SDS_MISC, RTL8367D_PA33PC_EN_S0_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_SDS_MISC, RTL8367D_CFG_SDS_MODE_MASK, RTL8367D_PORT_SDS_MODE_1000X)) != RT_ERR_OK) + return retVal; + + break; + case MODE_EXT_100FX: + for(i = 0; i < sizeof(Fiber100MCfg) / (sizeof(rtk_uint32) * 2); i++) + { + if( (retVal = rtl8367d_setAsicReg(RTL8367D_REG_SDS_INDACS_DATA, Fiber100MCfg[i][1])) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367d_setAsicReg(RTL8367D_REG_SDS_INDACS_ADR, Fiber100MCfg[i][0])) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367d_setAsicReg(RTL8367D_REG_SDS_INDACS_CMD, 0x00CD)) != RT_ERR_OK) + return retVal; + } + + if( (retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_FIBER_CFG_2, RTL8367D_SDS_RX_DISABLE_MASK, 1)) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_SDS_MISC, RTL8367D_PA12PC_EN_S0_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_SDS_MISC, RTL8367D_PA33PC_EN_S0_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_SDS_MISC, RTL8367D_CFG_SDS_MODE_MASK, RTL8367D_PORT_SDS_MODE_100FX)) != RT_ERR_OK) + return retVal; + + break; + case MODE_EXT_FIBER_2P5G: + for(i = 0; i < sizeof(Fiber2P5GCfg) / (sizeof(rtk_uint32) * 2); i++) + { + if( (retVal = rtl8367d_setAsicReg(RTL8367D_REG_SDS_INDACS_DATA, Fiber2P5GCfg[i][1])) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367d_setAsicReg(RTL8367D_REG_SDS_INDACS_ADR, Fiber2P5GCfg[i][0])) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367d_setAsicReg(RTL8367D_REG_SDS_INDACS_CMD, 0x00CD)) != RT_ERR_OK) + return retVal; + } + + if( (retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_FIBER_CFG_2, RTL8367D_SDS_RX_DISABLE_MASK, 1)) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_SDS_MISC, RTL8367D_PA12PC_EN_S0_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_SDS_MISC, RTL8367D_PA33PC_EN_S0_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_SDS_MISC, RTL8367D_CFG_SDS_MODE_MASK, RTL8367D_PORT_SDS_MODE_FIBER_2P5G)) != RT_ERR_OK) + return retVal; + + break; + default: + return RT_ERR_INPUT; + } + + if( (retVal = rtl8367d_setAsicReg(0x612F, 0x000C)) != RT_ERR_OK) + return retVal; + } + else + return RT_ERR_INPUT; + } + + if (id == 2) + { + if (mode == MODE_EXT_DISABLE) + { + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_TOP_CON0, RTL8367D_MAC7_SEL_EXT1_OFFSET, 0)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_DIGITAL_INTERFACE_SELECT, RTL8367D_SELECT_GMII_1_MASK, 0x0)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_SDS1_MISC0, RTL8367D_SDS1_MODE_MASK, RTL8367D_PORT_SDS_MODE_DISABLE)) != RT_ERR_OK) + return retVal; + } + else if ((mode == MODE_EXT_RGMII) || (mode == MODE_EXT_MII_MAC) || (mode == MODE_EXT_MII_PHY) || (mode == MODE_EXT_TMII_MAC) || + (mode == MODE_EXT_TMII_PHY) || (mode == MODE_EXT_RMII_MAC) || (mode == MODE_EXT_RMII_PHY)) + { + /* Configure RGMII DP, DN, E2, MODE */ + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_CHIP_DEBUG0, RTL8367D_SEL33_EXT1_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_CHIP_DEBUG0, RTL8367D_DRI_EXT1_RG_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_CHIP_DEBUG0, RTL8367D_DRI_EXT1_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_CHIP_DEBUG0, RTL8367D_SLR_EXT1_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_CHIP_DEBUG1, RTL8367D_RG1_DN_MASK, 7)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_CHIP_DEBUG1, RTL8367D_RG1_DP_MASK, 5)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_EXT_TXC_DLY, RTL8367D_EXT1_RGMII_TX_DELAY_MASK, 0)) != RT_ERR_OK) + return retVal; + + /* Configure RGMII/MII mux to port 7 if UTP_PORT4 is not RGMII mode */ + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_TOP_CON0, RTL8367D_MAC4_SEL_EXT1_OFFSET, &mux)) != RT_ERR_OK) + return retVal; + + if (mux == 0) + { + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_TOP_CON0, RTL8367D_MAC7_SEL_EXT1_OFFSET, 1)) != RT_ERR_OK) + return retVal; + } + + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_DIGITAL_INTERFACE_SELECT, RTL8367D_SELECT_GMII_1_MASK, mode)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_SDS1_MISC0, RTL8367D_SDS1_MODE_MASK, RTL8367D_PORT_SDS_MODE_DISABLE)) != RT_ERR_OK) + return retVal; + } + else if ((mode == MODE_EXT_SGMII) || (mode == MODE_EXT_HSGMII) || (mode == MODE_EXT_1000X_100FX) || (mode == MODE_EXT_1000X) || (mode == MODE_EXT_100FX) || (mode == MODE_EXT_FIBER_2P5G)) + { + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_DIGITAL_INTERFACE_SELECT, RTL8367D_SELECT_GMII_1_MASK, 0x0)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_TOP_CON0, RTL8367D_MAC7_SEL_EXT1_OFFSET, 0)) != RT_ERR_OK) + return retVal; + + for(i = 0; i < sizeof(SDSNctrlPatch) / (sizeof(rtk_uint32) * 2); i++) + { + if( (retVal = rtl8367d_setAsicReg(SDSNctrlPatch[i][0], SDSNctrlPatch[i][1])) != RT_ERR_OK) + return retVal; + } + + switch (mode) + { + case MODE_EXT_SGMII: + for(i = 0; i < sizeof(SGCfg) / (sizeof(rtk_uint32) * 2); i++) + { + if( (retVal = rtl8367d_setAsicReg(RTL8367D_REG_SDS_INDACS_DATA, SGCfg[i][1])) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367d_setAsicReg(RTL8367D_REG_SDS_INDACS_ADR, SGCfg[i][0])) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367d_setAsicReg(RTL8367D_REG_SDS_INDACS_CMD, 0x00CF)) != RT_ERR_OK) + return retVal; + } + + if((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_SDS1_MISC0, RTL8367D_PA12PC_EN_S1_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_SDS1_MISC0, RTL8367D_PA33PC_EN_S1_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_SDS1_MISC0, RTL8367D_SDS1_MODE_MASK, RTL8367D_PORT_SDS_MODE_SGMII)) != RT_ERR_OK) + return retVal; + + break; + case MODE_EXT_HSGMII: + for(i = 0; i < sizeof(HSGCfg) / (sizeof(rtk_uint32) * 2); i++) + { + if( (retVal = rtl8367d_setAsicReg(RTL8367D_REG_SDS_INDACS_DATA, HSGCfg[i][1])) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367d_setAsicReg(RTL8367D_REG_SDS_INDACS_ADR, HSGCfg[i][0])) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367d_setAsicReg(RTL8367D_REG_SDS_INDACS_CMD, 0x00CF)) != RT_ERR_OK) + return retVal; + } + + if((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_SDS1_MISC0, RTL8367D_PA12PC_EN_S1_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_SDS1_MISC0, RTL8367D_PA33PC_EN_S1_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_SDS1_MISC0, RTL8367D_SDS1_MODE_MASK, RTL8367D_PORT_SDS_MODE_HSGMII)) != RT_ERR_OK) + return retVal; + break; + case MODE_EXT_1000X_100FX: + for(i = 0; i < sizeof(Fiber1000M100MCfg) / (sizeof(rtk_uint32) * 2); i++) + { + if( (retVal = rtl8367d_setAsicReg(RTL8367D_REG_SDS_INDACS_DATA, Fiber1000M100MCfg[i][1])) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367d_setAsicReg(RTL8367D_REG_SDS_INDACS_ADR, Fiber1000M100MCfg[i][0])) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367d_setAsicReg(RTL8367D_REG_SDS_INDACS_CMD, 0x00CF)) != RT_ERR_OK) + return retVal; + } + + if( (retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_SDS1_MISC0, RTL8367D_PA12PC_EN_S1_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_SDS1_MISC0, RTL8367D_PA33PC_EN_S1_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_SDS1_MISC0, RTL8367D_SDS1_MODE_MASK, RTL8367D_PORT_SDS_MODE_1000X_100FX)) != RT_ERR_OK) + return retVal; + + break; + case MODE_EXT_1000X: + for(i = 0; i < sizeof(Fiber1000MCfg) / (sizeof(rtk_uint32) * 2); i++) + { + if( (retVal = rtl8367d_setAsicReg(RTL8367D_REG_SDS_INDACS_DATA, Fiber1000MCfg[i][1])) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367d_setAsicReg(RTL8367D_REG_SDS_INDACS_ADR, Fiber1000MCfg[i][0])) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367d_setAsicReg(RTL8367D_REG_SDS_INDACS_CMD, 0x00CF)) != RT_ERR_OK) + return retVal; + } + + if( (retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_SDS1_MISC0, RTL8367D_PA12PC_EN_S1_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_SDS1_MISC0, RTL8367D_PA33PC_EN_S1_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_SDS1_MISC0, RTL8367D_SDS1_MODE_MASK, RTL8367D_PORT_SDS_MODE_1000X)) != RT_ERR_OK) + return retVal; + + break; + case MODE_EXT_100FX: + for(i = 0; i < sizeof(Fiber100MCfg) / (sizeof(rtk_uint32) * 2); i++) + { + if( (retVal = rtl8367d_setAsicReg(RTL8367D_REG_SDS_INDACS_DATA, Fiber100MCfg[i][1])) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367d_setAsicReg(RTL8367D_REG_SDS_INDACS_ADR, Fiber100MCfg[i][0])) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367d_setAsicReg(RTL8367D_REG_SDS_INDACS_CMD, 0x00CF)) != RT_ERR_OK) + return retVal; + } + + if( (retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_SDS1_MISC0, RTL8367D_PA12PC_EN_S1_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_SDS1_MISC0, RTL8367D_PA33PC_EN_S1_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_SDS1_MISC0, RTL8367D_SDS1_MODE_MASK, RTL8367D_PORT_SDS_MODE_100FX)) != RT_ERR_OK) + return retVal; + + break; + case MODE_EXT_FIBER_2P5G: + for(i = 0; i < sizeof(Fiber2P5GCfg) / (sizeof(rtk_uint32) * 2); i++) + { + if( (retVal = rtl8367d_setAsicReg(RTL8367D_REG_SDS_INDACS_DATA, Fiber2P5GCfg[i][1])) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367d_setAsicReg(RTL8367D_REG_SDS_INDACS_ADR, Fiber2P5GCfg[i][0])) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367d_setAsicReg(RTL8367D_REG_SDS_INDACS_CMD, 0x00CF)) != RT_ERR_OK) + return retVal; + } + + if( (retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_SDS1_MISC0, RTL8367D_PA12PC_EN_S1_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_SDS1_MISC0, RTL8367D_PA33PC_EN_S1_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_SDS1_MISC0, RTL8367D_SDS1_MODE_MASK, RTL8367D_PORT_SDS_MODE_FIBER_2P5G)) != RT_ERR_OK) + return retVal; + + break; + default: + return RT_ERR_INPUT; + } + + if( (retVal = rtl8367d_setAsicReg(0x612F, 0x000C)) != RT_ERR_OK) + return retVal; + } + else + return RT_ERR_INPUT; + } + + return RT_ERR_OK; +} + +static rtk_api_ret_t _dal_rtl8367d_getAsicPortExtMode(rtk_uint32 id, rtk_uint32 *pMode) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + + switch (id) + { + case 1: + if( (retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_SDS_MISC, RTL8367D_CFG_SDS_MODE_MASK, ®Data)) != RT_ERR_OK) + return retVal; + break; + case 2: + if( (retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_SDS1_MISC0, RTL8367D_SDS1_MODE_MASK, ®Data)) != RT_ERR_OK) + return retVal; + break; + default: + return RT_ERR_OUT_OF_RANGE; + } + + switch (regData) + { + case RTL8367D_PORT_SDS_MODE_SGMII: + *pMode = MODE_EXT_SGMII; + break; + case RTL8367D_PORT_SDS_MODE_HSGMII: + *pMode = MODE_EXT_HSGMII; + break; + case RTL8367D_PORT_SDS_MODE_1000X: + *pMode = MODE_EXT_1000X; + break; + case RTL8367D_PORT_SDS_MODE_100FX: + *pMode = MODE_EXT_100FX; + break; + case RTL8367D_PORT_SDS_MODE_1000X_100FX: + *pMode = MODE_EXT_1000X_100FX; + break; + case RTL8367D_PORT_SDS_MODE_FIBER_2P5G: + *pMode = MODE_EXT_FIBER_2P5G; + break; + case RTL8367D_PORT_SDS_MODE_DISABLE: + if(id == 2) + { + if ((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_DIGITAL_INTERFACE_SELECT, RTL8367D_SELECT_GMII_1_MASK, pMode)) != RT_ERR_OK) + return retVal; + } + else + *pMode = MODE_EXT_DISABLE; + break; + default: + return RT_ERR_FAILED; + } + + return RT_ERR_OK; +} + +static rtk_api_ret_t _dal_rtl8367d_port_sgmiiLinkStatus_get(rtk_port_t port, rtk_data_t *pSignalDetect, rtk_data_t *pSync, rtk_port_linkStatus_t *pLink) +{ + rtk_api_ret_t retVal; + rtk_uint32 regValue; + + /* Check Port Valid */ + if(rtk_switch_isSgmiiPort(port) != RT_ERR_OK) + return RT_ERR_PORT_ID; + + if(NULL == pSignalDetect) + return RT_ERR_NULL_POINTER; + + if(NULL == pSync) + return RT_ERR_NULL_POINTER; + + if(NULL == pLink) + return RT_ERR_NULL_POINTER; + + switch (port) + { + case EXT_PORT0: + if ((retVal = rtl8367d_setAsicReg(0x6601, 0x003D)) != RT_ERR_OK) + break; + + if ((retVal = rtl8367d_setAsicReg(0x6600, 0x008D)) != RT_ERR_OK) + break; + + if ((retVal = rtl8367d_getAsicReg(0x6602, ®Value)) != RT_ERR_OK) + break; + break; + case EXT_PORT1: + if ((retVal = rtl8367d_setAsicReg(0x6601, 0x003D)) != RT_ERR_OK) + break; + + if ((retVal = rtl8367d_setAsicReg(0x6600, 0x008F)) != RT_ERR_OK) + break; + + if ((retVal = rtl8367d_getAsicReg(0x6602, ®Value)) != RT_ERR_OK) + break; + break; + default: + retVal = RT_ERR_PORT_ID; + } + + if (retVal == RT_ERR_OK) + { + *pSignalDetect = (regValue & 0x0100) ? 1 : 0; + *pSync = (regValue & 0x0001) ? 1 : 0; + *pLink = (regValue & 0x0010) ? 1 : 0; + } + + return retVal; +} + +static rtk_api_ret_t _dal_rtl8367d_port_sgmiiNway_set(rtk_port_t port, rtk_enable_t state) +{ + rtk_api_ret_t retVal; + rtk_uint32 regValue; + rtk_uint32 serdesAddr; + + /* Check Port Valid */ + if(rtk_switch_isSgmiiPort(port) != RT_ERR_OK) + return RT_ERR_PORT_ID; + + if(state >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + switch (port) + { + case EXT_PORT0: + serdesAddr = 0x0D; + break; + case EXT_PORT1: + serdesAddr = 0x0F; + break; + default: + return RT_ERR_PORT_ID; + } + + if ((retVal = rtl8367d_setAsicReg(0x6601, 0x0002)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicReg(0x6600, 0x0080 | serdesAddr)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_getAsicReg(0x6602, ®Value)) != RT_ERR_OK) + return retVal; + + if(state) + regValue |= 0x0200; + else + regValue &= ~0x0200; + + regValue |= 0x0100; + + if ((retVal = rtl8367d_setAsicReg(0x6602, regValue)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicReg(0x6601, 0x0002)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicReg(0x6600, 0x00C0 | serdesAddr)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +static rtk_api_ret_t _dal_rtl8367d_port_sgmiiNway_get(rtk_port_t port, rtk_enable_t *pState) +{ + rtk_api_ret_t retVal; + rtk_uint32 regValue; + rtk_uint32 serdesAddr; + + /* Check Port Valid */ + if(rtk_switch_isSgmiiPort(port) != RT_ERR_OK) + return RT_ERR_PORT_ID; + + if(NULL == pState) + return RT_ERR_NULL_POINTER; + + switch (port) + { + case EXT_PORT0: + serdesAddr = 0x0D; + break; + case EXT_PORT1: + serdesAddr = 0x0F; + break; + default: + return RT_ERR_PORT_ID; + } + + if ((retVal = rtl8367d_setAsicReg(0x6601, 0x0002)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicReg(0x6600, 0x0080 | serdesAddr)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_getAsicReg(0x6602, ®Value)) != RT_ERR_OK) + return retVal; + + if((regValue & 0x0300) == 0x0300) + *pState = ENABLED; + else if((regValue & 0x0300) == 0x0000) + *pState = ENABLED; + else + *pState = DISABLED; + + return RT_ERR_OK; +} + +static rtk_api_ret_t _dal_rtl8367d_port_fiberAbility_set(rtk_port_t port, rtk_port_fiber_ability_t *pAbility) +{ + rtk_api_ret_t retVal; + rtk_port_media_t media_type; + rtk_mode_ext_t mode; + rtk_port_mac_ability_t portAbility; + rtk_uint32 regData; + rtk_uint32 sdsId; + rtk_uint32 i; + + /* Check Port Valid and the port is already configured to fiber mode*/ + if (port == UTP_PORT4) + { + if ((retVal = dal_rtl8367d_port_phyComboPortMedia_get(port, &media_type)) != RT_ERR_OK) + return retVal; + + if (media_type != PORT_MEDIA_FIBER) + return RT_ERR_PORT_ID; + + sdsId = 0xD; + } + else if (port == EXT_PORT0) + { + if ((retVal = dal_rtl8367d_port_macForceLinkExt_get(port, &mode, &portAbility)) != RT_ERR_OK) + return retVal; + + if ((mode != MODE_EXT_1000X_100FX) && (mode != MODE_EXT_1000X) && (mode != MODE_EXT_100FX) && (mode != MODE_EXT_FIBER_2P5G)) + return RT_ERR_PORT_ID; + + sdsId = 0xD; + } + else if (port == EXT_PORT1) + { + if ((retVal = dal_rtl8367d_port_macForceLinkExt_get(port, &mode, &portAbility)) != RT_ERR_OK) + return retVal; + + if ((mode != MODE_EXT_1000X_100FX) && (mode != MODE_EXT_1000X) && (mode != MODE_EXT_100FX) && (mode != MODE_EXT_FIBER_2P5G)) + return RT_ERR_PORT_ID; + + sdsId = 0xF; + } + else + return RT_ERR_PORT_ID; + + /* NULL pointer checking */ + if (pAbility == NULL) + return RT_ERR_NULL_POINTER; + + /* UTP_PORT4 doesn't support 2.5G Fiber */ + if ((port == UTP_PORT4) && (pAbility->Full_2P5G == 1)) + return RT_ERR_PORT_ID; + + /* if 2.5G is set, all other speed should be cleared */ + if (pAbility->Full_2P5G == 1) + { + if ((pAbility->Full_1000 == 1) || (pAbility->Full_100 == 1)) + return RT_ERR_INPUT; + } + + /* if Full_100 is the only speed set, AutoNegotiation & FC+AsyFC should be cleared */ + if ((pAbility->Full_100 == 1) && (pAbility->Full_1000 == 0) && (pAbility->Full_2P5G == 0)) + { + if ((pAbility->AutoNegotiation == 1) || (pAbility->FC == 1) || (pAbility->AsyFC == 1)) + return RT_ERR_INPUT; + } + + /* Speed ability & Flow Control */ + if (pAbility->Full_2P5G == 1) + { + for (i = 0; i < sizeof(Fiber2P5GCfg) / (sizeof(rtk_uint32) * 2); i++) + { + regData = Fiber2P5GCfg[i][1]; + if (regData == 0x01A0) + { + if (pAbility->AsyFC == 0) + regData &= ~(0x0001 << 8); + + if (pAbility->FC == 0) + regData &= ~(0x0001 << 7); + } + + if( (retVal = rtl8367d_setAsicReg(RTL8367D_REG_SDS_INDACS_DATA, regData)) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367d_setAsicReg(RTL8367D_REG_SDS_INDACS_ADR, Fiber2P5GCfg[i][0])) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367d_setAsicReg(RTL8367D_REG_SDS_INDACS_CMD, (0x00C0 | sdsId))) != RT_ERR_OK) + return retVal; + } + + if (sdsId == 0xD) + { + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_SDS_MISC, RTL8367D_CFG_SDS_MODE_MASK, RTL8367D_PORT_SDS_MODE_FIBER_2P5G)) != RT_ERR_OK) + return retVal; + } + else + { + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_SDS1_MISC0, RTL8367D_SDS1_MODE_MASK, RTL8367D_PORT_SDS_MODE_FIBER_2P5G)) != RT_ERR_OK) + return retVal; + } + } + else if ((pAbility->Full_1000 == 1) && (pAbility->Full_100 == 1)) + { + for(i = 0; i < sizeof(Fiber1000M100MCfg) / (sizeof(rtk_uint32) * 2); i++) + { + regData = Fiber1000M100MCfg[i][1]; + if (regData == 0x0C01) + { + if (pAbility->AsyFC == 0) + regData &= ~(0x0001 << 11); + + if (pAbility->FC == 0) + regData &= ~(0x0001 << 10); + } + + if (regData == 0x01A0) + { + if (pAbility->AsyFC == 0) + regData &= ~(0x0001 << 8); + + if (pAbility->FC == 0) + regData &= ~(0x0001 << 7); + } + + if( (retVal = rtl8367d_setAsicReg(RTL8367D_REG_SDS_INDACS_DATA, regData)) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367d_setAsicReg(RTL8367D_REG_SDS_INDACS_ADR, Fiber1000M100MCfg[i][0])) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367d_setAsicReg(RTL8367D_REG_SDS_INDACS_CMD, (0x00C0 | sdsId))) != RT_ERR_OK) + return retVal; + } + + if (sdsId == 0xD) + { + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_SDS_MISC, RTL8367D_CFG_SDS_MODE_MASK, RTL8367D_PORT_SDS_MODE_1000X_100FX)) != RT_ERR_OK) + return retVal; + } + else + { + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_SDS1_MISC0, RTL8367D_SDS1_MODE_MASK, RTL8367D_PORT_SDS_MODE_1000X_100FX)) != RT_ERR_OK) + return retVal; + } + } + else if(pAbility->Full_1000 == 1) + { + for(i = 0; i < sizeof(Fiber1000MCfg) / (sizeof(rtk_uint32) * 2); i++) + { + regData = Fiber1000MCfg[i][1]; + if (regData == 0x01A0) + { + if (pAbility->AsyFC == 0) + regData &= ~(0x0001 << 8); + + if (pAbility->FC == 0) + regData &= ~(0x0001 << 7); + } + + if( (retVal = rtl8367d_setAsicReg(RTL8367D_REG_SDS_INDACS_DATA, regData)) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367d_setAsicReg(RTL8367D_REG_SDS_INDACS_ADR, Fiber1000MCfg[i][0])) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367d_setAsicReg(RTL8367D_REG_SDS_INDACS_CMD, (0x00C0 | sdsId))) != RT_ERR_OK) + return retVal; + } + + if (sdsId == 0xD) + { + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_SDS_MISC, RTL8367D_CFG_SDS_MODE_MASK, RTL8367D_PORT_SDS_MODE_1000X)) != RT_ERR_OK) + return retVal; + } + else + { + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_SDS1_MISC0, RTL8367D_SDS1_MODE_MASK, RTL8367D_PORT_SDS_MODE_1000X)) != RT_ERR_OK) + return retVal; + } + } + else if(pAbility->Full_100 == 1) + { + for(i = 0; i < sizeof(Fiber100MCfg) / (sizeof(rtk_uint32) * 2); i++) + { + regData = Fiber100MCfg[i][1]; + if (regData == 0x0C01) + { + if (pAbility->AsyFC == 0) + regData &= ~(0x0001 << 11); + + if (pAbility->FC == 0) + regData &= ~(0x0001 << 10); + } + + if( (retVal = rtl8367d_setAsicReg(RTL8367D_REG_SDS_INDACS_DATA, regData)) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367d_setAsicReg(RTL8367D_REG_SDS_INDACS_ADR, Fiber100MCfg[i][0])) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367d_setAsicReg(RTL8367D_REG_SDS_INDACS_CMD, (0x00C0 | sdsId))) != RT_ERR_OK) + return retVal; + } + + if (sdsId == 0xD) + { + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_SDS_MISC, RTL8367D_CFG_SDS_MODE_MASK, RTL8367D_PORT_SDS_MODE_100FX)) != RT_ERR_OK) + return retVal; + } + else + { + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_SDS1_MISC0, RTL8367D_SDS1_MODE_MASK, RTL8367D_PORT_SDS_MODE_100FX)) != RT_ERR_OK) + return retVal; + } + } + + /* Restart N-way & AutoNegotiation */ + if ((retVal = rtl8367d_setAsicReg(RTL8367D_REG_SDS_INDACS_ADR, 0x0040)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicReg(RTL8367D_REG_SDS_INDACS_CMD, (0x0080 | sdsId))) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_getAsicReg(RTL8367D_REG_SDS_INDACS_DATA, ®Data)) != RT_ERR_OK) + return retVal; + + /* AutoNegotiation */ + if (pAbility->AutoNegotiation == 1) + regData |= (0x0001 << 12); + else + regData &= ~(0x0001 << 12); + + /* Restart N-way */ + regData |= (0x0001 << 9); + + if ((retVal = rtl8367d_setAsicReg(RTL8367D_REG_SDS_INDACS_DATA, regData)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicReg(RTL8367D_REG_SDS_INDACS_ADR, 0x0040)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicReg(RTL8367D_REG_SDS_INDACS_CMD, (0x00C0 | sdsId))) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +static rtk_api_ret_t _dal_rtl8367d_port_fiberAbility_get(rtk_port_t port, rtk_port_fiber_ability_t *pAbility) +{ + rtk_api_ret_t retVal; + rtk_port_media_t media_type; + rtk_mode_ext_t mode; + rtk_port_mac_ability_t portAbility; + rtk_uint32 regData; + rtk_uint32 sdsId; + rtk_uint32 sdsMode; + + /* Check Port Valid and the port is already configured to fiber mode*/ + if (port == UTP_PORT4) + { + if ((retVal = dal_rtl8367d_port_phyComboPortMedia_get(port, &media_type)) != RT_ERR_OK) + return retVal; + + if (media_type != PORT_MEDIA_FIBER) + return RT_ERR_PORT_ID; + + sdsId = 0xD; + } + else if (port == EXT_PORT0) + { + if ((retVal = dal_rtl8367d_port_macForceLinkExt_get(port, &mode, &portAbility)) != RT_ERR_OK) + return retVal; + + if ((mode != MODE_EXT_1000X_100FX) && (mode != MODE_EXT_1000X) && (mode != MODE_EXT_100FX) && (mode != MODE_EXT_FIBER_2P5G)) + return RT_ERR_PORT_ID; + + sdsId = 0xD; + } + else if (port == EXT_PORT1) + { + if ((retVal = dal_rtl8367d_port_macForceLinkExt_get(port, &mode, &portAbility)) != RT_ERR_OK) + return retVal; + + if ((mode != MODE_EXT_1000X_100FX) && (mode != MODE_EXT_1000X) && (mode != MODE_EXT_100FX) && (mode != MODE_EXT_FIBER_2P5G)) + return RT_ERR_PORT_ID; + + sdsId = 0xF; + } + else + return RT_ERR_PORT_ID; + + /* NULL pointer checking */ + if (pAbility == NULL) + return RT_ERR_NULL_POINTER; + + memset(pAbility, 0x00, sizeof(rtk_port_fiber_ability_t)); + + /* Speed */ + if ((port == UTP_PORT4) || (port == EXT_PORT0)) + { + if ((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_SDS_MISC, RTL8367D_CFG_SDS_MODE_MASK, &sdsMode)) != RT_ERR_OK) + return retVal; + } + else + { + if ((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_SDS1_MISC0, RTL8367D_SDS1_MODE_MASK, &sdsMode)) != RT_ERR_OK) + return retVal; + } + + switch (sdsMode) + { + case RTL8367D_PORT_SDS_MODE_FIBER_2P5G: + pAbility->Full_2P5G = 1; + break; + case RTL8367D_PORT_SDS_MODE_1000X_100FX: + pAbility->Full_1000 = 1; + pAbility->Full_100 = 1; + break; + case RTL8367D_PORT_SDS_MODE_1000X: + pAbility->Full_1000 = 1; + break; + case RTL8367D_PORT_SDS_MODE_100FX: + pAbility->Full_100 = 1; + break; + default: + return RT_ERR_FAILED; + } + + /* AutoNegotiation */ + if ((retVal = rtl8367d_setAsicReg(RTL8367D_REG_SDS_INDACS_ADR, 0x0040)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicReg(RTL8367D_REG_SDS_INDACS_CMD, (0x0080 | sdsId))) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_getAsicReg(RTL8367D_REG_SDS_INDACS_DATA, ®Data)) != RT_ERR_OK) + return retVal; + + if(regData & 0x1000) + pAbility->AutoNegotiation = 1; + else + pAbility->AutoNegotiation = 0; + + /* Flow Control */ + if ((retVal = rtl8367d_setAsicReg(RTL8367D_REG_SDS_INDACS_ADR, 0x0044)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicReg(RTL8367D_REG_SDS_INDACS_CMD, (0x0080 | sdsId))) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_getAsicReg(RTL8367D_REG_SDS_INDACS_DATA, ®Data)) != RT_ERR_OK) + return retVal; + + if (sdsMode == RTL8367D_PORT_SDS_MODE_100FX) + { + if (regData & (0x0001 << 11)) + pAbility->AsyFC = 1; + + if(regData & (0x0001 << 10)) + pAbility->FC = 1; + } + else + { + if (regData & (0x0001 << 8)) + pAbility->AsyFC = 1; + + if(regData & (0x0001 << 7)) + pAbility->FC = 1; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_port_phyAutoNegoAbility_set + * Description: + * Set ethernet PHY auto-negotiation desired ability. + * Input: + * port - port id. + * pAbility - Ability structure + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_PHY_REG_ID - Invalid PHY address + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy + * Note: + * If Full_1000 bit is set to 1, the AutoNegotiation will be automatic set to 1. While both AutoNegotiation and Full_1000 are set to 0, the PHY speed and duplex selection will + * be set as following 100F > 100H > 10F > 10H priority sequence. + */ +rtk_api_ret_t dal_rtl8367d_port_phyAutoNegoAbility_set(rtk_port_t port, rtk_port_phy_ability_t *pAbility) +{ + rtk_api_ret_t retVal; + rtk_uint32 phyData; + rtk_uint32 phyEnMsk0; + rtk_uint32 phyEnMsk4; + rtk_uint32 phyEnMsk9; + rtk_port_media_t media_type; + rtk_port_fiber_ability_t fiberAbility; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_IS_UTP(port); + + if(NULL == pAbility) + return RT_ERR_NULL_POINTER; + + if (pAbility->Half_10 >= RTK_ENABLE_END || pAbility->Full_10 >= RTK_ENABLE_END || + pAbility->Half_100 >= RTK_ENABLE_END || pAbility->Full_100 >= RTK_ENABLE_END || + pAbility->Full_1000 >= RTK_ENABLE_END || pAbility->AutoNegotiation >= RTK_ENABLE_END || + pAbility->AsyFC >= RTK_ENABLE_END || pAbility->FC >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if (rtk_switch_isComboPort(port) == RT_ERR_OK) + { + if ((retVal = dal_rtl8367d_port_phyComboPortMedia_get(port, &media_type)) != RT_ERR_OK) + return retVal; + + if(media_type == PORT_MEDIA_FIBER) + { + memset(&fiberAbility, 0x00, sizeof(rtk_port_fiber_ability_t)); + fiberAbility.AutoNegotiation = pAbility->AutoNegotiation; + fiberAbility.AsyFC = pAbility->AsyFC; + fiberAbility.FC = pAbility->FC; + fiberAbility.Full_1000 = pAbility->Full_1000; + fiberAbility.Full_100 = pAbility->Full_100; + return dal_rtl8367d_port_fiberAbility_set(port, &fiberAbility); + } + else if (media_type == PORT_MEDIA_RGMII) + return RT_ERR_PORT_ID; + } + + /*for PHY auto mode setup*/ + pAbility->AutoNegotiation = 1; + + phyEnMsk0 = 0; + phyEnMsk4 = 0; + phyEnMsk9 = 0; + + if (1 == pAbility->Half_10) + { + /*10BASE-TX half duplex capable in reg 4.5*/ + phyEnMsk4 = phyEnMsk4 | (1 << 5); + + /*Speed selection [1:0] */ + /* 11=Reserved*/ + /* 10= 1000Mpbs*/ + /* 01= 100Mpbs*/ + /* 00= 10Mpbs*/ + phyEnMsk0 = phyEnMsk0 & (~(1 << 6)); + phyEnMsk0 = phyEnMsk0 & (~(1 << 13)); + } + + if (1 == pAbility->Full_10) + { + /*10BASE-TX full duplex capable in reg 4.6*/ + phyEnMsk4 = phyEnMsk4 | (1 << 6); + /*Speed selection [1:0] */ + /* 11=Reserved*/ + /* 10= 1000Mpbs*/ + /* 01= 100Mpbs*/ + /* 00= 10Mpbs*/ + phyEnMsk0 = phyEnMsk0 & (~(1 << 6)); + phyEnMsk0 = phyEnMsk0 & (~(1 << 13)); + + /*Full duplex mode in reg 0.8*/ + phyEnMsk0 = phyEnMsk0 | (1 << 8); + + } + + if (1 == pAbility->Half_100) + { + /*100BASE-TX half duplex capable in reg 4.7*/ + phyEnMsk4 = phyEnMsk4 | (1 << 7); + /*Speed selection [1:0] */ + /* 11=Reserved*/ + /* 10= 1000Mpbs*/ + /* 01= 100Mpbs*/ + /* 00= 10Mpbs*/ + phyEnMsk0 = phyEnMsk0 & (~(1 << 6)); + phyEnMsk0 = phyEnMsk0 | (1 << 13); + } + + + if (1 == pAbility->Full_100) + { + /*100BASE-TX full duplex capable in reg 4.8*/ + phyEnMsk4 = phyEnMsk4 | (1 << 8); + /*Speed selection [1:0] */ + /* 11=Reserved*/ + /* 10= 1000Mpbs*/ + /* 01= 100Mpbs*/ + /* 00= 10Mpbs*/ + phyEnMsk0 = phyEnMsk0 & (~(1 << 6)); + phyEnMsk0 = phyEnMsk0 | (1 << 13); + /*Full duplex mode in reg 0.8*/ + phyEnMsk0 = phyEnMsk0 | (1 << 8); + } + + + if (1 == pAbility->Full_1000) + { + /*1000 BASE-T FULL duplex capable setting in reg 9.9*/ + phyEnMsk9 = phyEnMsk9 | (1 << 9); + + /*Speed selection [1:0] */ + /* 11=Reserved*/ + /* 10= 1000Mpbs*/ + /* 01= 100Mpbs*/ + /* 00= 10Mpbs*/ + phyEnMsk0 = phyEnMsk0 | (1 << 6); + phyEnMsk0 = phyEnMsk0 & (~(1 << 13)); + + + /*Auto-Negotiation setting in reg 0.12*/ + phyEnMsk0 = phyEnMsk0 | (1 << 12); + + } + + if (1 == pAbility->AutoNegotiation) + { + /*Auto-Negotiation setting in reg 0.12*/ + phyEnMsk0 = phyEnMsk0 | (1 << 12); + } + + if (1 == pAbility->AsyFC) + { + /*Asymetric flow control in reg 4.11*/ + phyEnMsk4 = phyEnMsk4 | (1 << 11); + } + if (1 == pAbility->FC) + { + /*Flow control in reg 4.10*/ + phyEnMsk4 = phyEnMsk4 | (1 << 10); + } + + /*1000 BASE-T control register setting*/ + if ((retVal = _dal_rtl8367d_getAsicPHYReg(rtk_switch_port_L2P_get(port), PHY_1000_BASET_CONTROL_REG, &phyData)) != RT_ERR_OK) + return retVal; + + phyData = (phyData & (~0x0200)) | phyEnMsk9 ; + + if ((retVal = _dal_rtl8367d_setAsicPHYReg(rtk_switch_port_L2P_get(port), PHY_1000_BASET_CONTROL_REG, phyData)) != RT_ERR_OK) + return retVal; + + /*Auto-Negotiation control register setting*/ + if ((retVal = _dal_rtl8367d_getAsicPHYReg(rtk_switch_port_L2P_get(port), PHY_AN_ADVERTISEMENT_REG, &phyData)) != RT_ERR_OK) + return retVal; + + phyData = (phyData & (~0x0DE0)) | phyEnMsk4; + if ((retVal = _dal_rtl8367d_setAsicPHYReg(rtk_switch_port_L2P_get(port), PHY_AN_ADVERTISEMENT_REG, phyData)) != RT_ERR_OK) + return retVal; + + /*Control register setting and restart auto*/ + if ((retVal = _dal_rtl8367d_getAsicPHYReg(rtk_switch_port_L2P_get(port), PHY_CONTROL_REG, &phyData)) != RT_ERR_OK) + return retVal; + + phyData = (phyData & (~0x3140)) | phyEnMsk0; + /*If have auto-negotiation capable, then restart auto negotiation*/ + if (1 == pAbility->AutoNegotiation) + { + phyData = phyData | (1 << 9); + } + + if ((retVal = _dal_rtl8367d_setAsicPHYReg(rtk_switch_port_L2P_get(port), PHY_CONTROL_REG, phyData)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_port_phyAutoNegoAbility_get + * Description: + * Get PHY ability through PHY registers. + * Input: + * port - Port id. + * Output: + * pAbility - Ability structure + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_PHY_REG_ID - Invalid PHY address + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy + * Note: + * Get the capablity of specified PHY. + */ +rtk_api_ret_t dal_rtl8367d_port_phyAutoNegoAbility_get(rtk_port_t port, rtk_port_phy_ability_t *pAbility) +{ + rtk_api_ret_t retVal; + rtk_uint32 phyData0; + rtk_uint32 phyData4; + rtk_uint32 phyData9; + rtk_port_media_t media_type; + rtk_port_fiber_ability_t fiberAbility; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_IS_UTP(port); + + if(NULL == pAbility) + return RT_ERR_NULL_POINTER; + + if (rtk_switch_isComboPort(port) == RT_ERR_OK) + { + if ((retVal = dal_rtl8367d_port_phyComboPortMedia_get(port, &media_type)) != RT_ERR_OK) + return retVal; + + if(media_type == PORT_MEDIA_FIBER) + { + memset(&fiberAbility, 0x00, sizeof(rtk_port_fiber_ability_t)); + if ((retVal = dal_rtl8367d_port_fiberAbility_get(port, &fiberAbility)) != RT_ERR_OK) + return retVal; + + memset(pAbility, 0x00, sizeof(rtk_port_phy_ability_t)); + pAbility->AutoNegotiation = fiberAbility.AutoNegotiation; + pAbility->AsyFC = fiberAbility.AsyFC; + pAbility->FC = fiberAbility.FC; + pAbility->Full_1000 = fiberAbility.Full_1000; + pAbility->Full_100 = fiberAbility.Full_100; + return RT_ERR_OK; + } + } + + /*Control register setting and restart auto*/ + if ((retVal = _dal_rtl8367d_getAsicPHYReg(rtk_switch_port_L2P_get(port), PHY_CONTROL_REG, &phyData0)) != RT_ERR_OK) + return retVal; + + /*Auto-Negotiation control register setting*/ + if ((retVal = _dal_rtl8367d_getAsicPHYReg(rtk_switch_port_L2P_get(port), PHY_AN_ADVERTISEMENT_REG, &phyData4)) != RT_ERR_OK) + return retVal; + + /*1000 BASE-T control register setting*/ + if ((retVal = _dal_rtl8367d_getAsicPHYReg(rtk_switch_port_L2P_get(port), PHY_1000_BASET_CONTROL_REG, &phyData9)) != RT_ERR_OK) + return retVal; + + if (phyData9 & (1 << 9)) + pAbility->Full_1000 = 1; + else + pAbility->Full_1000 = 0; + + if (phyData4 & (1 << 11)) + pAbility->AsyFC = 1; + else + pAbility->AsyFC = 0; + + if (phyData4 & (1 << 10)) + pAbility->FC = 1; + else + pAbility->FC = 0; + + + if (phyData4 & (1 << 8)) + pAbility->Full_100 = 1; + else + pAbility->Full_100 = 0; + + if (phyData4 & (1 << 7)) + pAbility->Half_100 = 1; + else + pAbility->Half_100 = 0; + + if (phyData4 & (1 << 6)) + pAbility->Full_10 = 1; + else + pAbility->Full_10 = 0; + + if (phyData4 & (1 << 5)) + pAbility->Half_10 = 1; + else + pAbility->Half_10 = 0; + + + if (phyData0 & (1 << 12)) + pAbility->AutoNegotiation = 1; + else + pAbility->AutoNegotiation = 0; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_port_phyForceModeAbility_set + * Description: + * Set the port speed/duplex mode/pause/asy_pause in the PHY force mode. + * Input: + * port - port id. + * pAbility - Ability structure + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_PHY_REG_ID - Invalid PHY address + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy + * Note: + * While both AutoNegotiation and Full_1000 are set to 0, the PHY speed and duplex selection will + * be set as following 100F > 100H > 10F > 10H priority sequence. + * This API can be used to configure combo port in fiber mode. + * The possible parameters in fiber mode are Full_1000 and Full 100. + * All the other fields in rtk_port_phy_ability_t will be ignored in fiber port. + */ +rtk_api_ret_t dal_rtl8367d_port_phyForceModeAbility_set(rtk_port_t port, rtk_port_phy_ability_t *pAbility) +{ + rtk_api_ret_t retVal; + rtk_uint32 phyData; + rtk_uint32 phyEnMsk0; + rtk_uint32 phyEnMsk4; + rtk_uint32 phyEnMsk9; + rtk_port_media_t media_type; + rtk_port_fiber_ability_t fiberAbility; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_IS_UTP(port); + + if(NULL == pAbility) + return RT_ERR_NULL_POINTER; + + if (pAbility->Half_10 >= RTK_ENABLE_END || pAbility->Full_10 >= RTK_ENABLE_END || + pAbility->Half_100 >= RTK_ENABLE_END || pAbility->Full_100 >= RTK_ENABLE_END || + pAbility->Full_1000 >= RTK_ENABLE_END || pAbility->AutoNegotiation >= RTK_ENABLE_END || + pAbility->AsyFC >= RTK_ENABLE_END || pAbility->FC >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if (rtk_switch_isComboPort(port) == RT_ERR_OK) + { + if ((retVal = dal_rtl8367d_port_phyComboPortMedia_get(port, &media_type)) != RT_ERR_OK) + return retVal; + + if(media_type == PORT_MEDIA_FIBER) + { + memset(&fiberAbility, 0x00, sizeof(rtk_port_fiber_ability_t)); + fiberAbility.AutoNegotiation = pAbility->AutoNegotiation; + fiberAbility.AsyFC = pAbility->AsyFC; + fiberAbility.FC = pAbility->FC; + fiberAbility.Full_1000 = pAbility->Full_1000; + fiberAbility.Full_100 = pAbility->Full_100; + return dal_rtl8367d_port_fiberAbility_set(port, &fiberAbility); + } + } + + if (1 == pAbility->Full_1000) + return RT_ERR_INPUT; + + /*for PHY force mode setup*/ + pAbility->AutoNegotiation = 0; + + phyEnMsk0 = 0; + phyEnMsk4 = 0; + phyEnMsk9 = 0; + + if (1 == pAbility->Half_10) + { + /*10BASE-TX half duplex capable in reg 4.5*/ + phyEnMsk4 = phyEnMsk4 | (1 << 5); + + /*Speed selection [1:0] */ + /* 11=Reserved*/ + /* 10= 1000Mpbs*/ + /* 01= 100Mpbs*/ + /* 00= 10Mpbs*/ + phyEnMsk0 = phyEnMsk0 & (~(1 << 6)); + phyEnMsk0 = phyEnMsk0 & (~(1 << 13)); + } + + if (1 == pAbility->Full_10) + { + /*10BASE-TX full duplex capable in reg 4.6*/ + phyEnMsk4 = phyEnMsk4 | (1 << 6); + /*Speed selection [1:0] */ + /* 11=Reserved*/ + /* 10= 1000Mpbs*/ + /* 01= 100Mpbs*/ + /* 00= 10Mpbs*/ + phyEnMsk0 = phyEnMsk0 & (~(1 << 6)); + phyEnMsk0 = phyEnMsk0 & (~(1 << 13)); + + /*Full duplex mode in reg 0.8*/ + phyEnMsk0 = phyEnMsk0 | (1 << 8); + + } + + if (1 == pAbility->Half_100) + { + /*100BASE-TX half duplex capable in reg 4.7*/ + phyEnMsk4 = phyEnMsk4 | (1 << 7); + /*Speed selection [1:0] */ + /* 11=Reserved*/ + /* 10= 1000Mpbs*/ + /* 01= 100Mpbs*/ + /* 00= 10Mpbs*/ + phyEnMsk0 = phyEnMsk0 & (~(1 << 6)); + phyEnMsk0 = phyEnMsk0 | (1 << 13); + } + + + if (1 == pAbility->Full_100) + { + /*100BASE-TX full duplex capable in reg 4.8*/ + phyEnMsk4 = phyEnMsk4 | (1 << 8); + /*Speed selection [1:0] */ + /* 11=Reserved*/ + /* 10= 1000Mpbs*/ + /* 01= 100Mpbs*/ + /* 00= 10Mpbs*/ + phyEnMsk0 = phyEnMsk0 & (~(1 << 6)); + phyEnMsk0 = phyEnMsk0 | (1 << 13); + /*Full duplex mode in reg 0.8*/ + phyEnMsk0 = phyEnMsk0 | (1 << 8); + } + + if (1 == pAbility->AsyFC) + { + /*Asymetric flow control in reg 4.11*/ + phyEnMsk4 = phyEnMsk4 | (1 << 11); + } + if (1 == pAbility->FC) + { + /*Flow control in reg 4.10*/ + phyEnMsk4 = phyEnMsk4 | ((1 << 10)); + } + + /*1000 BASE-T control register setting*/ + if ((retVal = _dal_rtl8367d_getAsicPHYReg(rtk_switch_port_L2P_get(port), PHY_1000_BASET_CONTROL_REG, &phyData)) != RT_ERR_OK) + return retVal; + + phyData = (phyData & (~0x0200)) | phyEnMsk9 ; + + if ((retVal = _dal_rtl8367d_setAsicPHYReg(rtk_switch_port_L2P_get(port), PHY_1000_BASET_CONTROL_REG, phyData)) != RT_ERR_OK) + return retVal; + + /*Auto-Negotiation control register setting*/ + if ((retVal = _dal_rtl8367d_getAsicPHYReg(rtk_switch_port_L2P_get(port), PHY_AN_ADVERTISEMENT_REG, &phyData)) != RT_ERR_OK) + return retVal; + + phyData = (phyData & (~0x0DE0)) | phyEnMsk4; + if ((retVal = _dal_rtl8367d_setAsicPHYReg(rtk_switch_port_L2P_get(port), PHY_AN_ADVERTISEMENT_REG, phyData)) != RT_ERR_OK) + return retVal; + + /*Control register setting and power off/on*/ + phyData = phyEnMsk0 & (~(1 << 12)); + phyData |= (1 << 11); /* power down PHY, bit 11 should be set to 1 */ + if ((retVal = _dal_rtl8367d_setAsicPHYReg(rtk_switch_port_L2P_get(port), PHY_CONTROL_REG, phyData)) != RT_ERR_OK) + return retVal; + + phyData = phyData & (~(1 << 11)); /* power on PHY, bit 11 should be set to 0*/ + if ((retVal = _dal_rtl8367d_setAsicPHYReg(rtk_switch_port_L2P_get(port), PHY_CONTROL_REG, phyData)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_port_phyForceModeAbility_get + * Description: + * Get PHY ability through PHY registers. + * Input: + * port - Port id. + * Output: + * pAbility - Ability structure + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_PHY_REG_ID - Invalid PHY address + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy + * Note: + * Get the capablity of specified PHY. + */ +rtk_api_ret_t dal_rtl8367d_port_phyForceModeAbility_get(rtk_port_t port, rtk_port_phy_ability_t *pAbility) +{ + rtk_api_ret_t retVal; + rtk_uint32 phyData0; + rtk_uint32 phyData4; + rtk_uint32 phyData9; + rtk_port_media_t media_type; + rtk_port_fiber_ability_t fiberAbility; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_IS_UTP(port); + + if(NULL == pAbility) + return RT_ERR_NULL_POINTER; + + if (rtk_switch_isComboPort(port) == RT_ERR_OK) + { + if ((retVal = dal_rtl8367d_port_phyComboPortMedia_get(port, &media_type)) != RT_ERR_OK) + return retVal; + + if(media_type == PORT_MEDIA_FIBER) + { + memset(&fiberAbility, 0x00, sizeof(rtk_port_fiber_ability_t)); + if ((retVal = dal_rtl8367d_port_fiberAbility_get(port, &fiberAbility)) != RT_ERR_OK) + return retVal; + + memset(pAbility, 0x00, sizeof(rtk_port_phy_ability_t)); + pAbility->AutoNegotiation = fiberAbility.AutoNegotiation; + pAbility->AsyFC = fiberAbility.AsyFC; + pAbility->FC = fiberAbility.FC; + pAbility->Full_1000 = fiberAbility.Full_1000; + pAbility->Full_100 = fiberAbility.Full_100; + return RT_ERR_OK; + } + } + + /*Control register setting and restart auto*/ + if ((retVal = _dal_rtl8367d_getAsicPHYReg(rtk_switch_port_L2P_get(port), PHY_CONTROL_REG, &phyData0)) != RT_ERR_OK) + return retVal; + + /*Auto-Negotiation control register setting*/ + if ((retVal = _dal_rtl8367d_getAsicPHYReg(rtk_switch_port_L2P_get(port), PHY_AN_ADVERTISEMENT_REG, &phyData4)) != RT_ERR_OK) + return retVal; + + /*1000 BASE-T control register setting*/ + if ((retVal = _dal_rtl8367d_getAsicPHYReg(rtk_switch_port_L2P_get(port), PHY_1000_BASET_CONTROL_REG, &phyData9)) != RT_ERR_OK) + return retVal; + + if (phyData9 & (1 << 9)) + pAbility->Full_1000 = 1; + else + pAbility->Full_1000 = 0; + + if (phyData4 & (1 << 11)) + pAbility->AsyFC = 1; + else + pAbility->AsyFC = 0; + + if (phyData4 & ((1 << 10))) + pAbility->FC = 1; + else + pAbility->FC = 0; + + + if (phyData4 & (1 << 8)) + pAbility->Full_100 = 1; + else + pAbility->Full_100 = 0; + + if (phyData4 & (1 << 7)) + pAbility->Half_100 = 1; + else + pAbility->Half_100 = 0; + + if (phyData4 & (1 << 6)) + pAbility->Full_10 = 1; + else + pAbility->Full_10 = 0; + + if (phyData4 & (1 << 5)) + pAbility->Half_10 = 1; + else + pAbility->Half_10 = 0; + + + if (phyData0 & (1 << 12)) + pAbility->AutoNegotiation = 1; + else + pAbility->AutoNegotiation = 0; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_port_phyStatus_get + * Description: + * Get ethernet PHY linking status + * Input: + * port - Port id. + * Output: + * linkStatus - PHY link status + * speed - PHY link speed + * duplex - PHY duplex mode + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_PHY_REG_ID - Invalid PHY address + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy + * Note: + * API will return auto negotiation status of phy. + */ +rtk_api_ret_t dal_rtl8367d_port_phyStatus_get(rtk_port_t port, rtk_port_linkStatus_t *pLinkStatus, rtk_port_speed_t *pSpeed, rtk_port_duplex_t *pDuplex) +{ + rtk_api_ret_t retVal; + rtk_uint32 phyData; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_IS_UTP(port); + + if( (NULL == pLinkStatus) || (NULL == pSpeed) || (NULL == pDuplex) ) + return RT_ERR_NULL_POINTER; + + /*Get PHY resolved register*/ + if ((retVal = _dal_rtl8367d_getAsicPHYReg(rtk_switch_port_L2P_get(port), PHY_RESOLVED_REG, &phyData)) != RT_ERR_OK) + return retVal; + + /*check link status*/ + if (phyData & (1<<2)) + { + *pLinkStatus = 1; + + /*check link speed*/ + *pSpeed = (phyData&0x0030) >> 4; + + /*check link duplex*/ + *pDuplex = (phyData&0x0008) >> 3; + } + else + { + *pLinkStatus = 0; + *pSpeed = 0; + *pDuplex = 0; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_port_macForceLink_set + * Description: + * Set port force linking configuration. + * Input: + * port - port id. + * pPortability - port ability configuration + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can set Port/MAC force mode properties. + */ +rtk_api_ret_t dal_rtl8367d_port_macForceLink_set(rtk_port_t port, rtk_port_mac_ability_t *pPortability) +{ + rtk_api_ret_t retVal; + rtk_uint32 reg_data = 0; + rtk_uint32 reg_data2; + rtk_uint32 rtl8367d_speed; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pPortability) + return RT_ERR_NULL_POINTER; + + if (pPortability->forcemode >1|| pPortability->speed >= PORT_SPEED_END || pPortability->duplex > 1 || + pPortability->link > 1 || pPortability->nway > 1 || pPortability->txpause > 1 || pPortability->rxpause > 1) + return RT_ERR_INPUT; + + switch (pPortability->speed) + { + case PORT_SPEED_10M: + rtl8367d_speed = RTL8367D_EXT_PORT_SPEED_10M; + break; + case PORT_SPEED_100M: + rtl8367d_speed = RTL8367D_EXT_PORT_SPEED_100M; + break; + case PORT_SPEED_1000M: + rtl8367d_speed = RTL8367D_EXT_PORT_SPEED_1000M; + break; + case PORT_SPEED_500M: + rtl8367d_speed = RTL8367D_EXT_PORT_SPEED_500M; + break; + case PORT_SPEED_2500M: + rtl8367d_speed = RTL8367D_EXT_PORT_SPEED_2500M; + break; + default: + return RT_ERR_INPUT; + } + + reg_data |= ((rtl8367d_speed & 0x0C) >> 2) << 12; + reg_data |= pPortability->nway << 7; + reg_data |= pPortability->txpause << 6; + reg_data |= pPortability->rxpause << 5; + reg_data |= pPortability->link << 4; + reg_data |= pPortability->duplex << 2; + reg_data |= rtl8367d_speed & 0x03; + + if(pPortability->forcemode) + reg_data2 = 0xFFFF; + else + reg_data2 = 0; + + if((retVal = rtl8367d_setAsicReg(RTL8367D_REG_MAC0_FORCE_SELECT + rtk_switch_port_L2P_get(port), reg_data)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367d_setAsicReg(RTL8367D_REG_MAC0_FORCE_SELECT_EN + rtk_switch_port_L2P_get(port), reg_data2)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_port_macForceLink_get + * Description: + * Get port force linking configuration. + * Input: + * port - Port id. + * Output: + * pPortability - port ability configuration + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can get Port/MAC force mode properties. + */ +rtk_api_ret_t dal_rtl8367d_port_macForceLink_get(rtk_port_t port, rtk_port_mac_ability_t *pPortability) +{ + rtk_api_ret_t retVal; + rtk_uint32 reg_data; + rtk_uint32 reg_data2; + rtk_uint32 rtl8367d_speed; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pPortability) + return RT_ERR_NULL_POINTER; + + if((retVal = rtl8367d_getAsicReg(RTL8367D_REG_MAC0_FORCE_SELECT + rtk_switch_port_L2P_get(port), ®_data)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367d_getAsicReg(RTL8367D_REG_MAC0_FORCE_SELECT_EN + rtk_switch_port_L2P_get(port), ®_data2)) != RT_ERR_OK) + return retVal; + + if ((reg_data == 0x1000) && (reg_data2 == 0x3000) && (rtk_switch_isExtPort(port) == RT_ERR_OK)) + { + pPortability->forcemode = 0; + pPortability->nway = 0; + pPortability->txpause = 0; + pPortability->rxpause = 0; + pPortability->link = 0; + pPortability->duplex = 0; + return RT_ERR_OK; + } + + pPortability->forcemode = (reg_data2 == 0) ? 0 : 1; + pPortability->nway = (reg_data >> 7) & 0x0001; + pPortability->txpause = (reg_data >> 6) & 0x0001; + pPortability->rxpause = (reg_data >> 5) & 0x0001; + pPortability->link = (reg_data >> 4) & 0x0001; + pPortability->duplex = (reg_data >> 2) & 0x0001; + + rtl8367d_speed = (reg_data & 0x0003) | (((reg_data & 0x3000) >> 12) << 2); + switch (rtl8367d_speed) + { + case RTL8367D_EXT_PORT_SPEED_10M: + pPortability->speed = PORT_SPEED_10M; + break; + case RTL8367D_EXT_PORT_SPEED_100M: + pPortability->speed = PORT_SPEED_100M; + break; + case RTL8367D_EXT_PORT_SPEED_1000M: + pPortability->speed = PORT_SPEED_1000M; + break; + case RTL8367D_EXT_PORT_SPEED_500M: + pPortability->speed = PORT_SPEED_500M; + break; + case RTL8367D_EXT_PORT_SPEED_2500M: + pPortability->speed = PORT_SPEED_2500M; + break; + default: + return RT_ERR_INPUT; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_port_macForceLinkExt_set + * Description: + * Set external interface force linking configuration. + * Input: + * port - external port ID + * mode - external interface mode + * pPortability - port ability configuration + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can set external interface force mode properties. + * The external interface can be set to: + * - MODE_EXT_DISABLE, + * - MODE_EXT_RGMII, + * - MODE_EXT_MII_MAC, + * - MODE_EXT_MII_PHY, + * - MODE_EXT_TMII_MAC, + * - MODE_EXT_TMII_PHY, + * - MODE_EXT_GMII, + * - MODE_EXT_RMII_MAC, + * - MODE_EXT_RMII_PHY, + * - MODE_EXT_SGMII, + * - MODE_EXT_HSGMII, + */ +rtk_api_ret_t dal_rtl8367d_port_macForceLinkExt_set(rtk_port_t port, rtk_mode_ext_t mode, rtk_port_mac_ability_t *pPortability) +{ + rtk_api_ret_t retVal; + rtk_port_mac_ability_t ability; + rtk_uint32 ext_id; + rtk_port_media_t media_type; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + if (port == UTP_PORT4) + { + if (mode != MODE_EXT_RGMII) + return RT_ERR_INPUT; + + if ((retVal = dal_rtl8367d_port_phyComboPortMedia_get(port, &media_type)) != RT_ERR_OK) + return retVal; + + if (media_type != PORT_MEDIA_RGMII) + return RT_ERR_PORT_ID; + } + else + { + RTK_CHK_PORT_IS_EXT(port); + + if ((port == EXT_PORT1) && (mode == MODE_EXT_RGMII)) + { + if ((retVal = dal_rtl8367d_port_phyComboPortMedia_get(UTP_PORT4, &media_type)) != RT_ERR_OK) + return retVal; + + if (media_type == PORT_MEDIA_RGMII) + return RT_ERR_PORT_ID; + } + } + + if (NULL == pPortability) + return RT_ERR_NULL_POINTER; + + if ((mode > MODE_EXT_100FX) && (mode != MODE_EXT_FIBER_2P5G)) + return RT_ERR_INPUT; + + if (mode == MODE_EXT_GMII) + return RT_ERR_INPUT; + + if(mode == MODE_EXT_HSGMII) + { + if (pPortability->forcemode > 1 || pPortability->speed != PORT_SPEED_2500M || pPortability->duplex != PORT_FULL_DUPLEX || + pPortability->link >= PORT_LINKSTATUS_END || pPortability->nway > 1 || pPortability->txpause > 1 || pPortability->rxpause > 1) + return RT_ERR_INPUT; + + if(rtk_switch_isHsgPort(port) != RT_ERR_OK) + return RT_ERR_PORT_ID; + } + else if (mode == MODE_EXT_RGMII) + { + if (pPortability->forcemode > 1 || pPortability->speed > PORT_SPEED_1000M || pPortability->duplex >= PORT_DUPLEX_END || + pPortability->link >= PORT_LINKSTATUS_END || pPortability->nway > 1 || pPortability->txpause > 1 || pPortability->rxpause > 1) + return RT_ERR_INPUT; + } + else if (mode != MODE_EXT_DISABLE) + { + if (pPortability->forcemode > 1 || pPortability->speed > PORT_SPEED_1000M || pPortability->duplex >= PORT_DUPLEX_END || + pPortability->link >= PORT_LINKSTATUS_END || pPortability->nway > 1 || pPortability->txpause > 1 || pPortability->rxpause > 1) + return RT_ERR_INPUT; + } + + if ((port == UTP_PORT4) && (mode == MODE_EXT_RGMII)) + ext_id = 2; + else + ext_id = port - 15; + + /* Configure EXT port mode */ + if ((retVal = _dal_rtl8367d_setAsicPortExtMode(ext_id, mode)) != RT_ERR_OK) + return retVal; + + /* Configure Ability */ + memset(&ability, 0x00, sizeof(rtk_port_mac_ability_t)); + if ((retVal = dal_rtl8367d_port_macForceLink_get(port, &ability)) != RT_ERR_OK) + return retVal; + + if (pPortability->link == 0) + { + if (mode == MODE_EXT_FIBER_2P5G) + { + if((retVal = rtl8367d_setAsicReg(RTL8367D_REG_MAC0_FORCE_SELECT + rtk_switch_port_L2P_get(port), 0x1000)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367d_setAsicReg(RTL8367D_REG_MAC0_FORCE_SELECT_EN + rtk_switch_port_L2P_get(port), 0x3000)) != RT_ERR_OK) + return retVal; + } + else + { + ability.forcemode = pPortability->forcemode; + ability.duplex = pPortability->duplex; + ability.link = pPortability->link; + ability.nway = pPortability->nway; + ability.txpause = pPortability->txpause; + ability.rxpause = pPortability->rxpause; + ability.speed = pPortability->speed; + + if ((retVal = dal_rtl8367d_port_macForceLink_set(port, &ability)) != RT_ERR_OK) + return retVal; + } + } + else + { + ability.forcemode = pPortability->forcemode; + ability.duplex = pPortability->duplex; + ability.link = pPortability->link; + ability.nway = pPortability->nway; + ability.txpause = pPortability->txpause; + ability.rxpause = pPortability->rxpause; + ability.speed = pPortability->speed; + + if ((retVal = dal_rtl8367d_port_macForceLink_set(port, &ability)) != RT_ERR_OK) + return retVal; + } + + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_port_macForceLinkExt_get + * Description: + * Set external interface force linking configuration. + * Input: + * port - external port ID + * Output: + * pMode - external interface mode + * pPortability - port ability configuration + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can get external interface force mode properties. + */ +rtk_api_ret_t dal_rtl8367d_port_macForceLinkExt_get(rtk_port_t port, rtk_mode_ext_t *pMode, rtk_port_mac_ability_t *pPortability) +{ + rtk_api_ret_t retVal; + rtk_port_mac_ability_t ability; + rtk_uint32 ext_id; + rtk_port_media_t media_type; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + if (port == UTP_PORT4) + ext_id = 2; + else + { + RTK_CHK_PORT_IS_EXT(port); + ext_id = port - 15; + } + + if(NULL == pMode) + return RT_ERR_NULL_POINTER; + + if(NULL == pPortability) + return RT_ERR_NULL_POINTER; + + if ((retVal = _dal_rtl8367d_getAsicPortExtMode(ext_id, (rtk_uint32 *)pMode)) != RT_ERR_OK) + return retVal; + + if ( (ext_id == 1) && ((*pMode == MODE_EXT_1000X_100FX) || (*pMode == MODE_EXT_1000X) || (*pMode == MODE_EXT_100FX)) ) + { + if ((retVal = dal_rtl8367d_port_phyComboPortMedia_get(UTP_PORT4, &media_type)) != RT_ERR_OK) + return retVal; + + if (media_type == PORT_MEDIA_FIBER) + { + *pMode = MODE_EXT_DISABLE; + } + } + + if ((ext_id == 2) && (*pMode == MODE_EXT_RGMII)) + { + if ((retVal = dal_rtl8367d_port_phyComboPortMedia_get(UTP_PORT4, &media_type)) != RT_ERR_OK) + return retVal; + + if (port == UTP_PORT4) + { + if (media_type != PORT_MEDIA_RGMII) + *pMode = MODE_EXT_DISABLE; + } + else + { + if (media_type == PORT_MEDIA_RGMII) + *pMode = MODE_EXT_DISABLE; + } + } + + memset(&ability, 0x00, sizeof(rtk_port_mac_ability_t)); + if ((retVal = dal_rtl8367d_port_macForceLink_get(port, &ability)) != RT_ERR_OK) + return retVal; + + pPortability->forcemode = ability.forcemode; + pPortability->duplex = ability.duplex; + pPortability->link = ability.link; + pPortability->nway = ability.nway; + pPortability->txpause = ability.txpause; + pPortability->rxpause = ability.rxpause; + pPortability->speed = ability.speed; + + return RT_ERR_OK; + +} + +/* Function Name: + * dal_rtl8367d_port_macStatus_get + * Description: + * Get port link status. + * Input: + * port - Port id. + * Output: + * pPortstatus - port ability configuration + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can get Port/PHY properties. + */ +rtk_api_ret_t dal_rtl8367d_port_macStatus_get(rtk_port_t port, rtk_port_mac_ability_t *pPortstatus) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + rtk_uint32 rtl8367d_speed; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if(NULL == pPortstatus) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367d_getAsicReg(RTL8367D_REG_PORT0_STATUS+rtk_switch_port_L2P_get(port), ®Data)) != RT_ERR_OK) + return retVal; + + memset(pPortstatus, 0x00, sizeof(rtk_port_mac_ability_t)); + pPortstatus->link = (regData >> 4) & 0x0001; + + if (pPortstatus->link == 1) + { + pPortstatus->duplex = (regData >> 2) & 0x0001; + pPortstatus->nway = (regData >> 7) & 0x0001; + pPortstatus->txpause = (regData >> 6) & 0x0001; + pPortstatus->rxpause = (regData >> 5) & 0x0001; + + rtl8367d_speed = (regData & 0x0003) | (((regData & 0x3000) >> 12) << 2); + switch (rtl8367d_speed) + { + case RTL8367D_EXT_PORT_SPEED_10M: + pPortstatus->speed = PORT_SPEED_10M; + break; + case RTL8367D_EXT_PORT_SPEED_100M: + pPortstatus->speed = PORT_SPEED_100M; + break; + case RTL8367D_EXT_PORT_SPEED_1000M: + pPortstatus->speed = PORT_SPEED_1000M; + break; + case RTL8367D_EXT_PORT_SPEED_500M: + pPortstatus->speed = PORT_SPEED_500M; + break; + case RTL8367D_EXT_PORT_SPEED_2500M: + pPortstatus->speed = PORT_SPEED_2500M; + break; + default: + return RT_ERR_INPUT; + } + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_port_macLocalLoopbackEnable_set + * Description: + * Set Port Local Loopback. (Redirect TX to RX.) + * Input: + * port - Port id. + * enable - Loopback state, 0:disable, 1:enable + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can enable/disable Local loopback in MAC. + * For UTP port, This API will also enable the digital + * loopback bit in PHY register for sync of speed between + * PHY and MAC. For EXT port, users need to force the + * link state by themself. + */ +rtk_api_ret_t dal_rtl8367d_port_macLocalLoopbackEnable_set(rtk_port_t port, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + rtk_uint32 data; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if(enable >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_PORT0_MISC_CFG + (rtk_switch_port_L2P_get(port) << 5), RTL8367D_PORT0_MISC_CFG_MAC_LOOPBACK_OFFSET, (enable == ENABLED) ? 1 : 0)) != RT_ERR_OK) + return retVal; + + if(rtk_switch_isUtpPort(port) == RT_ERR_OK) + { + if ((retVal = _dal_rtl8367d_getAsicPHYReg(rtk_switch_port_L2P_get(port), PHY_CONTROL_REG, &data)) != RT_ERR_OK) + return retVal; + + if(enable == ENABLED) + data |= (0x0001 << 14); + else + data &= ~(0x0001 << 14); + + if ((retVal = _dal_rtl8367d_setAsicPHYReg(rtk_switch_port_L2P_get(port), PHY_CONTROL_REG, data)) != RT_ERR_OK) + return retVal; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_port_macLocalLoopbackEnable_get + * Description: + * Get Port Local Loopback. (Redirect TX to RX.) + * Input: + * port - Port id. + * Output: + * pEnable - Loopback state, 0:disable, 1:enable + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * None. + */ +rtk_api_ret_t dal_rtl8367d_port_macLocalLoopbackEnable_get(rtk_port_t port, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if (NULL == pEnable) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_PORT0_MISC_CFG + (rtk_switch_port_L2P_get(port) << 5), RTL8367D_PORT0_MISC_CFG_MAC_LOOPBACK_OFFSET, ®Data)) != RT_ERR_OK) + return retVal; + + *pEnable = (regData == 1) ? ENABLED : DISABLED; + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_port_phyReg_set + * Description: + * Set PHY register data of the specific port. + * Input: + * port - port id. + * reg - Register id + * regData - Register data + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_PHY_REG_ID - Invalid PHY address + * RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy + * Note: + * This API can set PHY register data of the specific port. + */ +rtk_api_ret_t dal_rtl8367d_port_phyReg_set(rtk_port_t port, rtk_port_phy_reg_t reg, rtk_port_phy_data_t regData) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_IS_UTP(port); + + if ((retVal = _dal_rtl8367d_setAsicPHYReg(rtk_switch_port_L2P_get(port), reg, regData)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_port_phyReg_get + * Description: + * Get PHY register data of the specific port. + * Input: + * port - Port id. + * reg - Register id + * Output: + * pData - Register data + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_PHY_REG_ID - Invalid PHY address + * RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy + * Note: + * This API can get PHY register data of the specific port. + */ +rtk_api_ret_t dal_rtl8367d_port_phyReg_get(rtk_port_t port, rtk_port_phy_reg_t reg, rtk_port_phy_data_t *pData) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_IS_UTP(port); + + if ((retVal = _dal_rtl8367d_getAsicPHYReg(rtk_switch_port_L2P_get(port), reg, pData)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8367d_port_phyOCPReg_set + * Description: + * Set PHY OCP register + * Input: + * port - PHY ID + * ocpAddr - OCP register address + * ocpData - OCP Data. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_BUSYWAIT_TIMEOUT - Timeout + * Note: + * None. + */ +rtk_api_ret_t dal_rtl8367d_port_phyOCPReg_set(rtk_port_t port, rtk_uint32 ocpAddr, rtk_uint32 ocpData ) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_IS_UTP(port); + + if ((retVal = _dal_rtl8367d_setAsicPHYOCPReg(rtk_switch_port_L2P_get(port), ocpAddr, ocpData)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_port_phyOCPReg_get + * Description: + * Set PHY OCP register + * Input: + * phyNo - PHY ID + * ocpAddr - OCP register address + * Output: + * pRegData - OCP data. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * None. + */ +rtk_api_ret_t dal_rtl8367d_port_phyOCPReg_get(rtk_port_t port, rtk_uint32 ocpAddr, rtk_uint32 *pRegData ) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_IS_UTP(port); + + if (pRegData == NULL) + return RT_ERR_NULL_POINTER; + + if ((retVal = _dal_rtl8367d_getAsicPHYOCPReg(rtk_switch_port_L2P_get(port), ocpAddr, pRegData)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8367d_port_backpressureEnable_set + * Description: + * Set the half duplex backpressure enable status of the specific port. + * Input: + * port - port id. + * enable - Back pressure status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * This API can set the half duplex backpressure enable status of the specific port. + * The half duplex backpressure enable status of the port is as following: + * - DISABLE(Defer) + * - ENABLE (Backpressure) + */ +rtk_api_ret_t dal_rtl8367d_port_backpressureEnable_set(rtk_port_t port, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (port != RTK_WHOLE_SYSTEM) + return RT_ERR_PORT_ID; + + if (enable >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_CFG_BACKPRESSURE, RTL8367D_LONGTXE_OFFSET, (enable == ENABLED) ? 0 : 1)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_port_backpressureEnable_get + * Description: + * Get the half duplex backpressure enable status of the specific port. + * Input: + * port - Port id. + * Output: + * pEnable - Back pressure status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can get the half duplex backpressure enable status of the specific port. + * The half duplex backpressure enable status of the port is as following: + * - DISABLE(Defer) + * - ENABLE (Backpressure) + */ +rtk_api_ret_t dal_rtl8367d_port_backpressureEnable_get(rtk_port_t port, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (port != RTK_WHOLE_SYSTEM) + return RT_ERR_PORT_ID; + + if(NULL == pEnable) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_CFG_BACKPRESSURE, RTL8367D_LONGTXE_OFFSET, ®Data)) != RT_ERR_OK) + return retVal; + + *pEnable = (regData == 1) ? DISABLED : ENABLED; + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_port_adminEnable_set + * Description: + * Set port admin configuration of the specific port. + * Input: + * port - port id. + * enable - Back pressure status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * This API can set port admin configuration of the specific port. + * The port admin configuration of the port is as following: + * - DISABLE + * - ENABLE + */ +rtk_api_ret_t dal_rtl8367d_port_adminEnable_set(rtk_port_t port, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + rtk_uint32 data; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_IS_UTP(port); + + if (enable >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if ((retVal = _dal_rtl8367d_getAsicPHYReg(rtk_switch_port_L2P_get(port), PHY_CONTROL_REG, &data)) != RT_ERR_OK) + return retVal; + + if (ENABLED == enable) + { + data &= 0xF7FF; + data |= 0x0200; + } + else if (DISABLED == enable) + { + data |= 0x0800; + } + + if ((retVal = _dal_rtl8367d_setAsicPHYReg(rtk_switch_port_L2P_get(port), PHY_CONTROL_REG, data)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_port_adminEnable_get + * Description: + * Get port admin configurationof the specific port. + * Input: + * port - Port id. + * Output: + * pEnable - Back pressure status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can get port admin configuration of the specific port. + * The port admin configuration of the port is as following: + * - DISABLE + * - ENABLE + */ +rtk_api_ret_t dal_rtl8367d_port_adminEnable_get(rtk_port_t port, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + rtk_uint32 data; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_IS_UTP(port); + + if(NULL == pEnable) + return RT_ERR_NULL_POINTER; + + if ((retVal = _dal_rtl8367d_getAsicPHYReg(port, PHY_CONTROL_REG, &data)) != RT_ERR_OK) + return retVal; + + if ( (data & 0x0800) == 0x0800) + { + *pEnable = DISABLED; + } + else + { + *pEnable = ENABLED; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_port_isolation_set + * Description: + * Set permitted port isolation portmask + * Input: + * port - port id. + * pPortmask - Permit port mask + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_PORT_MASK - Invalid portmask. + * Note: + * This API set the port mask that a port can trasmit packet to of each port + * A port can only transmit packet to ports included in permitted portmask + */ +rtk_api_ret_t dal_rtl8367d_port_isolation_set(rtk_port_t port, rtk_portmask_t *pPortmask) +{ + rtk_api_ret_t retVal; + rtk_uint32 pmask; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if(NULL == pPortmask) + return RT_ERR_NULL_POINTER; + + /* check port mask */ + RTK_CHK_PORTMASK_VALID(pPortmask); + + if ((retVal = rtk_switch_portmask_L2P_get(pPortmask, &pmask)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicReg(RTL8367D_REG_PORT_ISOLATION_PORT0_MASK + rtk_switch_port_L2P_get(port), pmask)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_port_isolation_get + * Description: + * Get permitted port isolation portmask + * Input: + * port - Port id. + * Output: + * pPortmask - Permit port mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API get the port mask that a port can trasmit packet to of each port + * A port can only transmit packet to ports included in permitted portmask + */ +rtk_api_ret_t dal_rtl8367d_port_isolation_get(rtk_port_t port, rtk_portmask_t *pPortmask) +{ + rtk_api_ret_t retVal; + rtk_uint32 pmask; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if(NULL == pPortmask) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367d_getAsicReg(RTL8367D_REG_PORT_ISOLATION_PORT0_MASK + rtk_switch_port_L2P_get(port), &pmask)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtk_switch_portmask_P2L_get(pmask, pPortmask)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_port_rgmiiDelayExt_set + * Description: + * Set RGMII interface delay value for TX and RX. + * Input: + * txDelay - TX delay value, 1 for delay 2ns and 0 for no-delay + * rxDelay - RX delay value, 0~7 for delay setup. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can set external interface 2 RGMII delay. + * In TX delay, there are 2 selection: no-delay and 2ns delay. + * In RX dekay, there are 8 steps for delay tunning. 0 for no-delay, and 7 for maximum delay. + * Note. This API should be called before rtk_port_macForceLinkExt_set(). + */ +rtk_api_ret_t dal_rtl8367d_port_rgmiiDelayExt_set(rtk_port_t port, rtk_data_t txDelay, rtk_data_t rxDelay) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + if ((port != EXT_PORT1) && (port != UTP_PORT4)) + return RT_ERR_PORT_ID; + + if ((txDelay > 1) || (rxDelay > 7)) + return RT_ERR_INPUT; + + if ((retVal = rtl8367d_getAsicReg(RTL8367D_REG_EXT1_RGMXF, ®Data)) != RT_ERR_OK) + return retVal; + + regData = (regData & 0xFFF0) | ((txDelay << 3) & 0x0008) | (rxDelay & 0x0007); + + if ((retVal = rtl8367d_setAsicReg(RTL8367D_REG_EXT1_RGMXF, regData)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_port_rgmiiDelayExt_get + * Description: + * Get RGMII interface delay value for TX and RX. + * Input: + * None + * Output: + * pTxDelay - TX delay value + * pRxDelay - RX delay value + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can set external interface 2 RGMII delay. + * In TX delay, there are 2 selection: no-delay and 2ns delay. + * In RX dekay, there are 8 steps for delay tunning. 0 for n0-delay, and 7 for maximum delay. + */ +rtk_api_ret_t dal_rtl8367d_port_rgmiiDelayExt_get(rtk_port_t port, rtk_data_t *pTxDelay, rtk_data_t *pRxDelay) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + if ((port != EXT_PORT1) && (port != UTP_PORT4)) + return RT_ERR_PORT_ID; + + if( (NULL == pTxDelay) || (NULL == pRxDelay) ) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367d_getAsicReg(RTL8367D_REG_EXT1_RGMXF, ®Data)) != RT_ERR_OK) + return retVal; + + *pTxDelay = (regData & 0x0008) >> 3; + *pRxDelay = regData & 0x0007; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_port_phyEnableAll_set + * Description: + * Set all PHY enable status. + * Input: + * enable - PHY Enable State. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * This API can set all PHY status. + * The configuration of all PHY is as following: + * - DISABLE + * - ENABLE + */ +rtk_api_ret_t dal_rtl8367d_port_phyEnableAll_set(rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + rtk_uint32 data; + rtk_uint32 port; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (enable >= RTK_ENABLE_END) + return RT_ERR_ENABLE; + + RTK_SCAN_ALL_LOG_PORT(port) + { + if(rtk_switch_isUtpPort(port) == RT_ERR_OK) + { + if ((retVal = _dal_rtl8367d_getAsicPHYReg(port, PHY_CONTROL_REG, &data)) != RT_ERR_OK) + { + return retVal; + } + if (ENABLED == enable) + { + data &= 0xF7FF; + data |= 0x0200; + } + else + { + data |= 0x0800; + } + + if ((retVal = _dal_rtl8367d_setAsicPHYReg(port, PHY_CONTROL_REG, data)) != RT_ERR_OK) + { + return retVal; + } + } + } + + return RT_ERR_OK; + +} + +/* Function Name: + * dal_rtl8367d_port_phyEnableAll_get + * Description: + * Get all PHY enable status. + * Input: + * None + * Output: + * pEnable - PHY Enable State. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API can set all PHY status. + * The configuration of all PHY is as following: + * - DISABLE + * - ENABLE + */ +rtk_api_ret_t dal_rtl8367d_port_phyEnableAll_get(rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + rtk_uint32 data; + rtk_uint32 port; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pEnable) + return RT_ERR_NULL_POINTER; + + RTK_SCAN_ALL_LOG_PORT(port) + { + if(rtk_switch_isUtpPort(port) == RT_ERR_OK) + { + if ((retVal = _dal_rtl8367d_getAsicPHYReg(port, PHY_CONTROL_REG, &data)) != RT_ERR_OK) + return retVal; + + if (data & 0x0800) + { + *pEnable = DISABLED; + return RT_ERR_OK; + } + } + } + + *pEnable = ENABLED; + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_port_phyComboPortMedia_set + * Description: + * Set Combo port media type + * Input: + * port - Port id. + * media - Media (COPPER or FIBER or AUTO) + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API can Set Combo port media type. + */ +rtk_api_ret_t dal_rtl8367d_port_phyComboPortMedia_set(rtk_port_t port, rtk_port_media_t media) +{ + rtk_api_ret_t retVal; + rtk_uint32 i; + rtk_uint32 mux; + rtk_port_media_t currentMedia; + rtk_uint32 regData; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_IS_UTP(port); + + /* Check Combo Port ID */ + RTK_CHK_PORT_IS_COMBO(port); + + if ((retVal = dal_rtl8367d_port_phyComboPortMedia_get(port, ¤tMedia)) != RT_ERR_OK) + return retVal; + + if (media == currentMedia) + return RT_ERR_OK; + + /* if SDS0 used by EXT_PORT0, can't configure combo = Fiber*/ + if (media == PORT_MEDIA_FIBER) + { + if( (retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_SDS_MISC, RTL8367D_CFG_SDS_MODE_MASK, ®Data)) != RT_ERR_OK) + return retVal; + + if (regData != RTL8367D_PORT_SDS_MODE_DISABLE) + return RT_ERR_INPUT; + } + + /* Different media type, always set to copper then set to new media type */ + if (currentMedia == PORT_MEDIA_FIBER) + { + if( (retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_FIBER_CFG_2, RTL8367D_SDS_RX_DISABLE_MASK, 0)) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_SDS_MISC, RTL8367D_PA12PC_EN_S0_OFFSET, 0)) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_SDS_MISC, RTL8367D_PA33PC_EN_S0_OFFSET, 0)) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_SDS_MISC, RTL8367D_CFG_SDS_MODE_MASK, RTL8367D_PORT_SDS_MODE_DISABLE)) != RT_ERR_OK) + return retVal; + + /* Clear Fiber mux setting */ + if( (retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_UTP_FIB_DET, RTL8367D_FORCE_SEL_FIBER_MASK, 0)) != RT_ERR_OK) + return retVal; + + /* Clear Force Link down MAC6 setting */ + if ((retVal = rtl8367d_setAsicReg(RTL8367D_REG_MAC6_FORCE_SELECT, 0x0000)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicReg(RTL8367D_REG_MAC6_FORCE_SELECT_EN, 0x0000)) != RT_ERR_OK) + return retVal; + } + else if (currentMedia == PORT_MEDIA_RGMII) + { + /* Disable RGMII */ + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_DIGITAL_INTERFACE_SELECT, RTL8367D_SELECT_GMII_1_MASK, 0)) != RT_ERR_OK) + return retVal; + + /* Clear MAC4 force ability */ + if ((retVal = rtl8367d_setAsicReg(RTL8367D_REG_MAC4_FORCE_SELECT, 0)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicReg(RTL8367D_REG_MAC4_FORCE_SELECT_EN, 0)) != RT_ERR_OK) + return retVal; + + /* Clear RGMII/MII mux setting */ + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_TOP_CON0, RTL8367D_MAC4_SEL_EXT1_OFFSET, 0)) != RT_ERR_OK) + return retVal; + } + + /* Configure new medida type */ + if(media == PORT_MEDIA_FIBER) + { + for(i = 0; i < sizeof(SDSNctrlPatch) / (sizeof(rtk_uint32) * 2); i++) + { + if( (retVal = rtl8367d_setAsicReg(SDSNctrlPatch[i][0], SDSNctrlPatch[i][1])) != RT_ERR_OK) + return retVal; + } + + for(i = 0; i < sizeof(Fiber1000M100MCfg) / (sizeof(rtk_uint32) * 2); i++) + { + if( (retVal = rtl8367d_setAsicReg(RTL8367D_REG_SDS_INDACS_DATA, Fiber1000M100MCfg[i][1])) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367d_setAsicReg(RTL8367D_REG_SDS_INDACS_ADR, Fiber1000M100MCfg[i][0])) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367d_setAsicReg(RTL8367D_REG_SDS_INDACS_CMD, 0x00CD)) != RT_ERR_OK) + return retVal; + } + + if( (retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_FIBER_CFG_2, RTL8367D_SDS_RX_DISABLE_MASK, 1)) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_UTP_FIB_DET, RTL8367D_FORCE_SEL_FIBER_MASK, 0x3)) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_SDS_MISC, RTL8367D_PA12PC_EN_S0_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_SDS_MISC, RTL8367D_PA33PC_EN_S0_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_SDS_MISC, RTL8367D_MAC6_SEL_SDS0_OFFSET, 0)) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_SDS_MISC, RTL8367D_CFG_SDS_MODE_MASK, RTL8367D_PORT_SDS_MODE_1000X_100FX)) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367d_setAsicReg(0x612F, 0x000C)) != RT_ERR_OK) + return retVal; + + /* Force Link down MAC6 */ + if ((retVal = rtl8367d_setAsicReg(RTL8367D_REG_MAC6_FORCE_SELECT, 0x0000)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicReg(RTL8367D_REG_MAC6_FORCE_SELECT_EN, 0xFFFF)) != RT_ERR_OK) + return retVal; + + } + else if(media == PORT_MEDIA_RGMII) + { + /* Make sure RGMII/MII mux is not at port 7 */ + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_TOP_CON0, RTL8367D_MAC7_SEL_EXT1_OFFSET, &mux)) != RT_ERR_OK) + return retVal; + + if (mux == 1) + return RT_ERR_INPUT; + + /* Configure RGMII DP, DN, E2, MODE */ + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_CHIP_DEBUG0, RTL8367D_SEL33_EXT1_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_CHIP_DEBUG0, RTL8367D_DRI_EXT1_RG_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_CHIP_DEBUG0, RTL8367D_DRI_EXT1_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_CHIP_DEBUG0, RTL8367D_SLR_EXT1_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_CHIP_DEBUG1, RTL8367D_RG1_DN_MASK, 7)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_CHIP_DEBUG1, RTL8367D_RG1_DP_MASK, 5)) != RT_ERR_OK) + return retVal; + + /* Configure RGMII/MII mux to port 4 */ + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_TOP_CON0, RTL8367D_MAC4_SEL_EXT1_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_DIGITAL_INTERFACE_SELECT, RTL8367D_SELECT_GMII_1_MASK, 1)) != RT_ERR_OK) + return retVal; + } + else if (media == PORT_MEDIA_COPPER) + { + /* Do nothing */ + } + else + return RT_ERR_INPUT; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_port_phyComboPortMedia_get + * Description: + * Get Combo port media type + * Input: + * port - Port id. + * Output: + * pMedia - Media (COPPER or FIBER or AUTO) + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API can Set Combo port media type. + */ +rtk_api_ret_t dal_rtl8367d_port_phyComboPortMedia_get(rtk_port_t port, rtk_port_media_t *pMedia) +{ + rtk_api_ret_t retVal; + rtk_uint32 data; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_IS_UTP(port); + + /* Check Combo Port ID */ + RTK_CHK_PORT_IS_COMBO(port); + + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_TOP_CON0, RTL8367D_MAC4_SEL_EXT1_OFFSET, &data)) != RT_ERR_OK) + return retVal; + + if (data == 1) + *pMedia = PORT_MEDIA_RGMII; + else + { + if( (retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_UTP_FIB_DET, RTL8367D_FORCE_SEL_FIBER_MASK, &data)) != RT_ERR_OK) + return retVal; + + if (data == 3) + *pMedia = PORT_MEDIA_FIBER; + else + *pMedia = PORT_MEDIA_COPPER; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_port_rtctEnable_set + * Description: + * Enable RTCT test + * Input: + * pPortmask - Port mask of RTCT enabled port + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Invalid port mask. + * Note: + * The API can enable RTCT Test + */ +rtk_api_ret_t dal_rtl8367d_port_rtctEnable_set(rtk_portmask_t *pPortmask) +{ + rtk_api_ret_t retVal; + rtk_port_t port; + rtk_uint32 regData; + rtk_uint32 i; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Mask Valid */ + RTK_CHK_PORTMASK_VALID_ONLY_UTP(pPortmask); + + RTK_PORTMASK_SCAN((*pPortmask), port) + { + /* Initialize RTCT */ + for(i = 0; i < sizeof(RTCTPatch) / (sizeof(rtk_uint32) * 2); i++) + { + if( (retVal = dal_rtl8367d_port_phyOCPReg_set(port, RTCTPatch[i][0], RTCTPatch[i][1])) != RT_ERR_OK) + return retVal; + } + + regData = 0x00F2; /*RTCT set to echo response mode*/ + if((retVal = dal_rtl8367d_port_phyOCPReg_set(port, 0xa422, regData)) != RT_ERR_OK) + return retVal; + + regData = 0x00F3; + if((retVal = dal_rtl8367d_port_phyOCPReg_set(port, 0xa422, regData)) != RT_ERR_OK) + return retVal; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_port_rtctDisable_set + * Description: + * Disable RTCT test + * Input: + * pPortmask - Port mask of RTCT disabled port + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Invalid port mask. + * Note: + * The API can disable RTCT Test + */ +rtk_api_ret_t dal_rtl8367d_port_rtctDisable_set(rtk_portmask_t *pPortmask) +{ + rtk_api_ret_t retVal; + rtk_port_t port; + rtk_uint32 regData; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Mask Valid */ + RTK_CHK_PORTMASK_VALID_ONLY_UTP(pPortmask); + + RTK_PORTMASK_SCAN((*pPortmask), port) + { + if((retVal = dal_rtl8367d_port_phyOCPReg_get(port, 0xa422, ®Data)) != RT_ERR_OK) + return retVal; + + regData &= 0x7FFF; + if((retVal = dal_rtl8367d_port_phyOCPReg_set(port, 0xa422, regData)) != RT_ERR_OK) + return retVal; + + regData |= 0x00F0; + if((retVal = dal_rtl8367d_port_phyOCPReg_set(port, 0xa422, regData)) != RT_ERR_OK) + return retVal; + + regData &= ~0x0001; + if((retVal = dal_rtl8367d_port_phyOCPReg_set(port, 0xa422, regData)) != RT_ERR_OK) + return retVal; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_port_rtctResult_get + * Description: + * Get the result of RTCT test + * Input: + * port - Port ID + * Output: + * pRtctResult - The result of RTCT result + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port ID. + * RT_ERR_PHY_RTCT_NOT_FINISH - Testing does not finish. + * Note: + * The API can get RTCT test result. + * RTCT test may takes 4.8 seconds to finish its test at most. + * Thus, if this API return RT_ERR_PHY_RTCT_NOT_FINISH or + * other error code, the result can not be referenced and + * user should call this API again until this API returns + * a RT_ERR_OK. + * The result is stored at pRtctResult->ge_result + * pRtctResult->linkType is unused. + * The unit of channel length is 2.5cm. Ex. 300 means 300 * 2.5 = 750cm = 7.5M + */ +rtk_api_ret_t dal_rtl8367d_port_rtctResult_get(rtk_port_t port, rtk_rtctResult_t *pRtctResult) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData, finish = 1; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_IS_UTP(port); + + if((retVal = dal_rtl8367d_port_phyOCPReg_get(port, 0xa422, ®Data)) != RT_ERR_OK) + return retVal; + + if((regData & 0x8000) == 0x8000) + { + /* Channel A */ + if((retVal = dal_rtl8367d_port_phyOCPReg_set(port, 0xa436, 0x802b)) != RT_ERR_OK) + return retVal; + + if((retVal = dal_rtl8367d_port_phyOCPReg_get(port, 0xa438, ®Data)) != RT_ERR_OK) + return retVal; + + pRtctResult->result.ge_result.channelAOpen = (regData == 0x0048) ? 1 : 0; + pRtctResult->result.ge_result.channelAShort = (regData == 0x0050) ? 1 : 0; + pRtctResult->result.ge_result.channelAMismatch = ((regData == 0x0042) || (regData == 0x0044)) ? 1 : 0; + pRtctResult->result.ge_result.channelALinedriver = (regData == 0x0041) ? 1 : 0; + + /* Channel B */ + if((retVal = dal_rtl8367d_port_phyOCPReg_set(port, 0xa436, 0x802f)) != RT_ERR_OK) + return retVal; + + if((retVal = dal_rtl8367d_port_phyOCPReg_get(port, 0xa438, ®Data)) != RT_ERR_OK) + return retVal; + + pRtctResult->result.ge_result.channelBOpen = (regData == 0x0048) ? 1 : 0; + pRtctResult->result.ge_result.channelBShort = (regData == 0x0050) ? 1 : 0; + pRtctResult->result.ge_result.channelBMismatch = ((regData == 0x0042) || (regData == 0x0044)) ? 1 : 0; + pRtctResult->result.ge_result.channelBLinedriver = (regData == 0x0041) ? 1 : 0; + + /* Channel C */ + if((retVal = dal_rtl8367d_port_phyOCPReg_set(port, 0xa436, 0x8033)) != RT_ERR_OK) + return retVal; + + if((retVal = dal_rtl8367d_port_phyOCPReg_get(port, 0xa438, ®Data)) != RT_ERR_OK) + return retVal; + + pRtctResult->result.ge_result.channelCOpen = (regData == 0x0048) ? 1 : 0; + pRtctResult->result.ge_result.channelCShort = (regData == 0x0050) ? 1 : 0; + pRtctResult->result.ge_result.channelCMismatch = ((regData == 0x0042) || (regData == 0x0044)) ? 1 : 0; + pRtctResult->result.ge_result.channelCLinedriver = (regData == 0x0041) ? 1 : 0; + + /* Channel D */ + if((retVal = dal_rtl8367d_port_phyOCPReg_set(port, 0xa436, 0x8037)) != RT_ERR_OK) + return retVal; + + if((retVal = dal_rtl8367d_port_phyOCPReg_get(port, 0xa438, ®Data)) != RT_ERR_OK) + return retVal; + + pRtctResult->result.ge_result.channelDOpen = (regData == 0x0048) ? 1 : 0; + pRtctResult->result.ge_result.channelDShort = (regData == 0x0050) ? 1 : 0; + pRtctResult->result.ge_result.channelDMismatch = ((regData == 0x0042) || (regData == 0x0044)) ? 1 : 0; + pRtctResult->result.ge_result.channelDLinedriver = (regData == 0x0041) ? 1 : 0; + + /* Channel A Length */ + if((retVal = dal_rtl8367d_port_phyOCPReg_set(port, 0xa436, 0x802d)) != RT_ERR_OK) + return retVal; + + if((retVal = dal_rtl8367d_port_phyOCPReg_get(port, 0xa438, ®Data)) != RT_ERR_OK) + return retVal; + + pRtctResult->result.ge_result.channelALen = (regData / 2); + + /* Channel B Length */ + if((retVal = dal_rtl8367d_port_phyOCPReg_set(port, 0xa436, 0x8031)) != RT_ERR_OK) + return retVal; + + if((retVal = dal_rtl8367d_port_phyOCPReg_get(port, 0xa438, ®Data)) != RT_ERR_OK) + return retVal; + + pRtctResult->result.ge_result.channelBLen = (regData / 2); + + /* Channel C Length */ + if((retVal = dal_rtl8367d_port_phyOCPReg_set(port, 0xa436, 0x8035)) != RT_ERR_OK) + return retVal; + + if((retVal = dal_rtl8367d_port_phyOCPReg_get(port, 0xa438, ®Data)) != RT_ERR_OK) + return retVal; + + pRtctResult->result.ge_result.channelCLen = (regData / 2); + + /* Channel D Length */ + if((retVal = dal_rtl8367d_port_phyOCPReg_set(port, 0xa436, 0x8039)) != RT_ERR_OK) + return retVal; + + if((retVal = dal_rtl8367d_port_phyOCPReg_get(port, 0xa438, ®Data)) != RT_ERR_OK) + return retVal; + + pRtctResult->result.ge_result.channelDLen = (regData / 2); + } + else + finish = 0; + + if(finish == 0) + return RT_ERR_PHY_RTCT_NOT_FINISH; + else + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_port_sgmiiLinkStatus_get + * Description: + * Get SGMII status + * Input: + * port - Port ID + * Output: + * pSignalDetect - Signal detect + * pSync - Sync + * pLink - Link + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API can reset Serdes + */ +rtk_api_ret_t dal_rtl8367d_port_sgmiiLinkStatus_get(rtk_port_t port, rtk_data_t *pSignalDetect, rtk_data_t *pSync, rtk_port_linkStatus_t *pLink) +{ + rtk_api_ret_t retVal; + rtk_uint32 nCtrlValue; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if ((retVal = rtl8367d_getAsicReg(0x612f, &nCtrlValue)) != RT_ERR_OK) + return retVal; + + if (nCtrlValue != 0x0000) + { + if ((retVal = rtl8367d_setAsicReg(0x612f, 0)) != RT_ERR_OK) + return retVal; + } + + if ((retVal = _dal_rtl8367d_port_sgmiiLinkStatus_get(port, pSignalDetect, pSync, pLink)) != RT_ERR_OK) + return retVal; + + if (nCtrlValue != 0x0000) + { + if ((retVal = rtl8367d_setAsicReg(0x612f, nCtrlValue)) != RT_ERR_OK) + return retVal; + } + + return retVal; +} + +/* Function Name: + * dal_rtl8367d_port_sgmiiNway_set + * Description: + * Configure SGMII/HSGMII port Nway state + * Input: + * port - Port ID + * state - Nway state + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API configure SGMII/HSGMII port Nway state + */ +rtk_api_ret_t dal_rtl8367d_port_sgmiiNway_set(rtk_port_t port, rtk_enable_t state) +{ + rtk_api_ret_t retVal; + rtk_uint32 nCtrlValue; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if ((retVal = rtl8367d_getAsicReg(0x612f, &nCtrlValue)) != RT_ERR_OK) + return retVal; + + if (nCtrlValue != 0x0000) + { + if ((retVal = rtl8367d_setAsicReg(0x612f, 0)) != RT_ERR_OK) + return retVal; + } + + if ((retVal = _dal_rtl8367d_port_sgmiiNway_set(port, state)) != RT_ERR_OK) + return retVal; + + if (nCtrlValue != 0x0000) + { + if ((retVal = rtl8367d_setAsicReg(0x612f, nCtrlValue)) != RT_ERR_OK) + return retVal; + } + + return retVal; +} + +/* Function Name: + * dal_rtl8367d_port_sgmiiNway_get + * Description: + * Get SGMII/HSGMII port Nway state + * Input: + * port - Port ID + * Output: + * pState - Nway state + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API can get SGMII/HSGMII port Nway state + */ +rtk_api_ret_t dal_rtl8367d_port_sgmiiNway_get(rtk_port_t port, rtk_enable_t *pState) +{ + rtk_api_ret_t retVal; + rtk_uint32 nCtrlValue; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if ((retVal = rtl8367d_getAsicReg(0x612f, &nCtrlValue)) != RT_ERR_OK) + return retVal; + + if (nCtrlValue != 0x0000) + { + if ((retVal = rtl8367d_setAsicReg(0x612f, 0)) != RT_ERR_OK) + return retVal; + } + + if ((retVal = _dal_rtl8367d_port_sgmiiNway_get(port, pState)) != RT_ERR_OK) + return retVal; + + if (nCtrlValue != 0x0000) + { + if ((retVal = rtl8367d_setAsicReg(0x612f, nCtrlValue)) != RT_ERR_OK) + return retVal; + } + + return retVal; +} + +/* Function Name: + * dal_rtl8367d_port_autoDos_set + * Description: + * Set Auto Dos state + * Input: + * type - Auto DoS type + * state - 1: Eanble(Drop), 0: Disable(Forward) + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set Auto Dos state + */ +rtk_api_ret_t dal_rtl8367d_port_autoDos_set(rtk_port_autoDosType_t type, rtk_enable_t state) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (type >= AUTODOS_END) + return RT_ERR_INPUT; + + if (state >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_DOS_CFG, RTL8367D_DROP_DAEQSA_OFFSET + type, (state == ENABLED) ? 1 : 0)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_port_autoDos_get + * Description: + * Get Auto Dos state + * Input: + * type - Auto DoS type + * Output: + * pState - 1: Eanble(Drop), 0: Disable(Forward) + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Null Pointer + * Note: + * The API can get Auto Dos state + */ +rtk_api_ret_t dal_rtl8367d_port_autoDos_get(rtk_port_autoDosType_t type, rtk_enable_t *pState) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (type >= AUTODOS_END) + return RT_ERR_INPUT; + + if (pState == NULL) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_DOS_CFG, RTL8367D_DROP_DAEQSA_OFFSET + type, ®Data)) != RT_ERR_OK) + return retVal; + + *pState = (regData == 1) ? ENABLED : DISABLED; + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8367d_port_fiberAbility_set + * Description: + * Configure fiber port ability + * Input: + * port - Port ID + * pAbility - Fiber port ability + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API can configure fiber port ability + */ +rtk_api_ret_t dal_rtl8367d_port_fiberAbility_set(rtk_port_t port, rtk_port_fiber_ability_t *pAbility) +{ + rtk_api_ret_t retVal; + rtk_uint32 nCtrlValue; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if ((retVal = rtl8367d_getAsicReg(0x612f, &nCtrlValue)) != RT_ERR_OK) + return retVal; + + if (nCtrlValue != 0x0000) + { + if ((retVal = rtl8367d_setAsicReg(0x612f, 0)) != RT_ERR_OK) + return retVal; + } + + if ((retVal = _dal_rtl8367d_port_fiberAbility_set(port, pAbility)) != RT_ERR_OK) + return retVal; + + if (nCtrlValue != 0x0000) + { + if ((retVal = rtl8367d_setAsicReg(0x612f, nCtrlValue)) != RT_ERR_OK) + return retVal; + } + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8367d_port_fiberAbility_get + * Description: + * Get fiber port ability + * Input: + * port - Port ID + * Output: + * pAbility - Fiber port ability + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API can get fiber port ability + */ +rtk_api_ret_t dal_rtl8367d_port_fiberAbility_get(rtk_port_t port, rtk_port_fiber_ability_t *pAbility) +{ + rtk_api_ret_t retVal; + rtk_uint32 nCtrlValue; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if ((retVal = rtl8367d_getAsicReg(0x612f, &nCtrlValue)) != RT_ERR_OK) + return retVal; + + if (nCtrlValue != 0x0000) + { + if ((retVal = rtl8367d_setAsicReg(0x612f, 0)) != RT_ERR_OK) + return retVal; + } + + if ((retVal = _dal_rtl8367d_port_fiberAbility_get(port, pAbility)) != RT_ERR_OK) + return retVal; + + if (nCtrlValue != 0x0000) + { + if ((retVal = rtl8367d_setAsicReg(0x612f, nCtrlValue)) != RT_ERR_OK) + return retVal; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_port_phyMdx_set + * Description: + * Set PHY MDI/MDIX state + * Input: + * port - port ID + * mode - PHY MDI/MDIX mode + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set PHY MDI/MDIX state + */ +rtk_api_ret_t dal_rtl8367d_port_phyMdx_set(rtk_port_t port, rtk_port_phy_mdix_mode_t mode) +{ + rtk_uint32 regData; + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_IS_UTP(port); + + if ((retVal = dal_rtl8367d_port_phyOCPReg_get(port, 0xa430, ®Data))!=RT_ERR_OK) + return retVal; + + switch (mode) + { + case PHY_AUTO_CROSSOVER_MODE: + regData &= ~(0x0001 << 9); + break; + case PHY_FORCE_MDI_MODE: + regData |= (0x0001 << 9); + regData |= (0x0001 << 8); + break; + case PHY_FORCE_MDIX_MODE: + regData |= (0x0001 << 9); + regData &= ~(0x0001 << 8); + break; + default: + return RT_ERR_INPUT; + break; + } + + if ((retVal = dal_rtl8367d_port_phyOCPReg_set(port, 0xa430, regData))!=RT_ERR_OK) + return retVal; + + /* Restart N-way */ + if ((retVal = dal_rtl8367d_port_phyReg_get(port, 0, ®Data))!=RT_ERR_OK) + return retVal; + + regData |= (0x0001 << 9); + + if ((retVal = dal_rtl8367d_port_phyReg_set(port, 0, regData))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_port_phyMdx_get + * Description: + * Get PHY MDI/MDIX state + * Input: + * port - port ID + * Output: + * pMode - PHY MDI/MDIX mode + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can get PHY MDI/MDIX state + */ +rtk_api_ret_t dal_rtl8367d_port_phyMdx_get(rtk_port_t port, rtk_port_phy_mdix_mode_t *pMode) +{ + rtk_uint32 regData; + rtk_api_ret_t retVal; + + if ((retVal = dal_rtl8367d_port_phyOCPReg_get(port, 0xa430, ®Data))!=RT_ERR_OK) + return retVal; + + if(regData & (0x0001 << 9)) + { + if(regData & (0x0001 << 8)) + *pMode = PHY_FORCE_MDI_MODE; + else + *pMode = PHY_FORCE_MDIX_MODE; + } + else + *pMode = PHY_AUTO_CROSSOVER_MODE; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_port_phyMdxStatus_get + * Description: + * Get PHY MDI/MDIX status + * Input: + * port - port ID + * Output: + * pStatus - PHY MDI/MDIX status + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can get PHY MDI/MDIX status + */ +rtk_api_ret_t dal_rtl8367d_port_phyMdxStatus_get(rtk_port_t port, rtk_port_phy_mdix_status_t *pStatus) +{ + rtk_uint32 regData; + rtk_api_ret_t retVal; + + if ((retVal = dal_rtl8367d_port_phyOCPReg_get(port, 0xa430, ®Data))!=RT_ERR_OK) + return retVal; + + if (regData & (0x0001 << 9)) + { + if (regData & (0x0001 << 8)) + *pStatus = PHY_STATUS_FORCE_MDI_MODE; + else + *pStatus = PHY_STATUS_FORCE_MDIX_MODE; + } + else + { + if ((retVal = dal_rtl8367d_port_phyOCPReg_get(port, 0xa434, ®Data))!=RT_ERR_OK) + return retVal; + + if (regData & (0x0001 << 1)) + *pStatus = PHY_STATUS_AUTO_MDI_MODE; + else + *pStatus = PHY_STATUS_AUTO_MDIX_MODE; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_port_phyTestMode_set + * Description: + * Set PHY in test mode. + * Input: + * port - port id. + * mode - PHY test mode 0:normal 1:test mode 1 2:test mode 2 3: test mode 3 4:test mode 4 5~7:reserved + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy + * RT_ERR_NOT_ALLOWED - The Setting is not allowed, caused by set more than 1 port in Test mode. + * Note: + * Set PHY in test mode and only one PHY can be in test mode at the same time. + * It means API will return FAILED if other PHY is in test mode. + * This API only provide test mode 1 & 4 setup. + */ +rtk_api_ret_t dal_rtl8367d_port_phyTestMode_set(rtk_port_t port, rtk_port_phy_test_mode_t mode) +{ + rtk_uint32 data, i; + rtk_api_ret_t retVal; + + RTK_CHK_PORT_IS_UTP(port); + + if(mode >= PHY_TEST_MODE_END) + return RT_ERR_INPUT; + + if( (mode == PHY_TEST_MODE_2) || (mode == PHY_TEST_MODE_3) ) + return RT_ERR_INPUT; + + if (PHY_TEST_MODE_NORMAL != mode) + { + /* Other port should be Normal mode */ + RTK_SCAN_ALL_LOG_PORT(i) + { + if(rtk_switch_isUtpPort(i) == RT_ERR_OK) + { + if(i != port) + { + if ((retVal = dal_rtl8367d_port_phyReg_get(i, 9, &data)) != RT_ERR_OK) + return retVal; + + if((data & 0xE000) != 0) + return RT_ERR_NOT_ALLOWED; + } + } + } + } + + + if ((retVal = dal_rtl8367d_port_phyReg_get(port, 9, &data)) != RT_ERR_OK) + return retVal; + + data &= ~0xE000; + data |= (mode << 13); + if ((retVal = dal_rtl8367d_port_phyReg_set(port, 9, data)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_port_phyTestMode_get + * Description: + * Get PHY in which test mode. + * Input: + * port - Port id. + * Output: + * mode - PHY test mode 0:normal 1:test mode 1 2:test mode 2 3: test mode 3 4:test mode 4 5~7:reserved + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy + * Note: + * Get test mode of PHY from register setting 9.15 to 9.13. + */ +rtk_api_ret_t dal_rtl8367d_port_phyTestMode_get(rtk_port_t port, rtk_port_phy_test_mode_t *pMode) +{ + rtk_uint32 data; + rtk_api_ret_t retVal; + + RTK_CHK_PORT_IS_UTP(port); + + if (pMode == NULL) + return RT_ERR_NULL_POINTER; + + if ((retVal = dal_rtl8367d_port_phyReg_get(port, 9, &data)) != RT_ERR_OK) + return retVal; + + *pMode = (data & 0xE000) >> 13; + + return RT_ERR_OK; +} + +/* add Implement */ +rtk_api_ret_t dal_rtl8367d_setAsicPHYOCPReg(rtk_uint32 phyNo, rtk_uint32 ocpAddr, rtk_uint32 ocpData) +{ + return _dal_rtl8367d_setAsicPHYOCPReg(phyNo, ocpAddr, ocpData); +} +rtk_api_ret_t dal_rtl8367d_getAsicPHYOCPReg(rtk_uint32 phyNo, rtk_uint32 ocpAddr, rtk_uint32 *pRegData) +{ + return _dal_rtl8367d_getAsicPHYOCPReg(phyNo, ocpAddr, pRegData); +} +rtk_api_ret_t dal_rtl8367d_setAsicPHYReg(rtk_uint32 phyNo, rtk_uint32 phyAddr, rtk_uint32 phyData) +{ + return _dal_rtl8367d_setAsicPHYReg(phyNo, phyAddr, phyData); +} +rtk_api_ret_t dal_rtl8367d_getAsicPHYReg(rtk_uint32 phyNo, rtk_uint32 phyAddr, rtk_uint32 *pRegData) +{ + return _dal_rtl8367d_getAsicPHYReg(phyNo, phyAddr, pRegData); +} + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_port.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_port.h new file mode 100644 index 00000000..54a2ace4 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_port.h @@ -0,0 +1,918 @@ + /* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8367/RTL8367D switch high-level API + * + * Feature : The file includes port module high-layer API defination + * + */ + +#ifndef __DAL_RTL8367D_PORT_H__ +#define __DAL_RTL8367D_PORT_H__ + +#include + +#define RTL8367D_PHY_REGNOMAX 0x1F +#define RTL8367D_PHY_BASE 0x2000 +#define RTL8367D_PHY_OFFSET 5 + +/* + * Data Type Declaration + */ + +/* Function Name: + * dal_rtl8367d_port_phyAutoNegoAbility_set + * Description: + * Set ethernet PHY auto-negotiation desired ability. + * Input: + * port - port id. + * pAbility - Ability structure + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_PHY_REG_ID - Invalid PHY address + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy + * Note: + * If Full_1000 bit is set to 1, the AutoNegotiation will be automatic set to 1. While both AutoNegotiation and Full_1000 are set to 0, the PHY speed and duplex selection will + * be set as following 100F > 100H > 10F > 10H priority sequence. + */ +extern rtk_api_ret_t dal_rtl8367d_port_phyAutoNegoAbility_set(rtk_port_t port, rtk_port_phy_ability_t *pAbility); + +/* Function Name: + * dal_rtl8367d_port_phyAutoNegoAbility_get + * Description: + * Get PHY ability through PHY registers. + * Input: + * port - Port id. + * Output: + * pAbility - Ability structure + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_PHY_REG_ID - Invalid PHY address + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy + * Note: + * Get the capablity of specified PHY. + */ +extern rtk_api_ret_t dal_rtl8367d_port_phyAutoNegoAbility_get(rtk_port_t port, rtk_port_phy_ability_t *pAbility); + +/* Function Name: + * dal_rtl8367d_port_phyForceModeAbility_set + * Description: + * Set the port speed/duplex mode/pause/asy_pause in the PHY force mode. + * Input: + * port - port id. + * pAbility - Ability structure + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_PHY_REG_ID - Invalid PHY address + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy + * Note: + * While both AutoNegotiation and Full_1000 are set to 0, the PHY speed and duplex selection will + * be set as following 100F > 100H > 10F > 10H priority sequence. + */ +extern rtk_api_ret_t dal_rtl8367d_port_phyForceModeAbility_set(rtk_port_t port, rtk_port_phy_ability_t *pAbility); + +/* Function Name: + * dal_rtl8367d_port_phyForceModeAbility_get + * Description: + * Get PHY ability through PHY registers. + * Input: + * port - Port id. + * Output: + * pAbility - Ability structure + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_PHY_REG_ID - Invalid PHY address + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy + * Note: + * Get the capablity of specified PHY. + */ +extern rtk_api_ret_t dal_rtl8367d_port_phyForceModeAbility_get(rtk_port_t port, rtk_port_phy_ability_t *pAbility); + +/* Function Name: + * dal_rtl8367d_port_phyStatus_get + * Description: + * Get ethernet PHY linking status + * Input: + * port - Port id. + * Output: + * linkStatus - PHY link status + * speed - PHY link speed + * duplex - PHY duplex mode + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_PHY_REG_ID - Invalid PHY address + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy + * Note: + * API will return auto negotiation status of phy. + */ +extern rtk_api_ret_t dal_rtl8367d_port_phyStatus_get(rtk_port_t port, rtk_port_linkStatus_t *pLinkStatus, rtk_port_speed_t *pSpeed, rtk_port_duplex_t *pDuplex); + +/* Function Name: + * dal_rtl8367d_port_macForceLink_set + * Description: + * Set port force linking configuration. + * Input: + * port - port id. + * pPortability - port ability configuration + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can set Port/MAC force mode properties. + */ +extern rtk_api_ret_t dal_rtl8367d_port_macForceLink_set(rtk_port_t port, rtk_port_mac_ability_t *pPortability); + +/* Function Name: + * dal_rtl8367d_port_macForceLink_get + * Description: + * Get port force linking configuration. + * Input: + * port - Port id. + * Output: + * pPortability - port ability configuration + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can get Port/MAC force mode properties. + */ +extern rtk_api_ret_t dal_rtl8367d_port_macForceLink_get(rtk_port_t port, rtk_port_mac_ability_t *pPortability); + +/* Function Name: + * dal_rtl8367d_port_macForceLinkExt_set + * Description: + * Set external interface force linking configuration. + * Input: + * port - external port ID + * mode - external interface mode + * pPortability - port ability configuration + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can set external interface force mode properties. + * The external interface can be set to: + * - MODE_EXT_DISABLE, + * - MODE_EXT_RGMII, + * - MODE_EXT_MII_MAC, + * - MODE_EXT_MII_PHY, + * - MODE_EXT_TMII_MAC, + * - MODE_EXT_TMII_PHY, + * - MODE_EXT_GMII, + * - MODE_EXT_RMII_MAC, + * - MODE_EXT_RMII_PHY, + * - MODE_EXT_SGMII, + * - MODE_EXT_HSGMII, + */ +extern rtk_api_ret_t dal_rtl8367d_port_macForceLinkExt_set(rtk_port_t port, rtk_mode_ext_t mode, rtk_port_mac_ability_t *pPortability); + +/* Function Name: + * dal_rtl8367d_port_macForceLinkExt_get + * Description: + * Set external interface force linking configuration. + * Input: + * port - external port ID + * Output: + * pMode - external interface mode + * pPortability - port ability configuration + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can get external interface force mode properties. + */ +extern rtk_api_ret_t dal_rtl8367d_port_macForceLinkExt_get(rtk_port_t port, rtk_mode_ext_t *pMode, rtk_port_mac_ability_t *pPortability); + +/* Function Name: + * dal_rtl8367d_port_macStatus_get + * Description: + * Get port link status. + * Input: + * port - Port id. + * Output: + * pPortstatus - port ability configuration + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can get Port/PHY properties. + */ +extern rtk_api_ret_t dal_rtl8367d_port_macStatus_get(rtk_port_t port, rtk_port_mac_ability_t *pPortstatus); + +/* Function Name: + * dal_rtl8367d_port_macLocalLoopbackEnable_set + * Description: + * Set Port Local Loopback. (Redirect TX to RX.) + * Input: + * port - Port id. + * enable - Loopback state, 0:disable, 1:enable + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can enable/disable Local loopback in MAC. + * For UTP port, This API will also enable the digital + * loopback bit in PHY register for sync of speed between + * PHY and MAC. For EXT port, users need to force the + * link state by themself. + */ +extern rtk_api_ret_t dal_rtl8367d_port_macLocalLoopbackEnable_set(rtk_port_t port, rtk_enable_t enable); + +/* Function Name: + * dal_rtl8367d_port_macLocalLoopbackEnable_get + * Description: + * Get Port Local Loopback. (Redirect TX to RX.) + * Input: + * port - Port id. + * Output: + * pEnable - Loopback state, 0:disable, 1:enable + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * None. + */ +extern rtk_api_ret_t dal_rtl8367d_port_macLocalLoopbackEnable_get(rtk_port_t port, rtk_enable_t *pEnable); + +/* Function Name: + * dal_rtl8367d_port_phyReg_set + * Description: + * Set PHY register data of the specific port. + * Input: + * port - port id. + * reg - Register id + * regData - Register data + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_PHY_REG_ID - Invalid PHY address + * RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy + * Note: + * This API can set PHY register data of the specific port. + */ +extern rtk_api_ret_t dal_rtl8367d_port_phyReg_set(rtk_port_t port, rtk_port_phy_reg_t reg, rtk_port_phy_data_t value); + +/* Function Name: + * dal_rtl8367d_port_phyReg_get + * Description: + * Get PHY register data of the specific port. + * Input: + * port - Port id. + * reg - Register id + * Output: + * pData - Register data + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_PHY_REG_ID - Invalid PHY address + * RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy + * Note: + * This API can get PHY register data of the specific port. + */ +extern rtk_api_ret_t dal_rtl8367d_port_phyReg_get(rtk_port_t port, rtk_port_phy_reg_t reg, rtk_port_phy_data_t *pData); + +/* Function Name: + * dal_rtl8367d_port_phyOCPReg_set + * Description: + * Set PHY OCP register + * Input: + * port - PHY ID + * ocpAddr - OCP register address + * ocpData - OCP Data. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_BUSYWAIT_TIMEOUT - Timeout + * Note: + * None. + */ +extern rtk_api_ret_t dal_rtl8367d_port_phyOCPReg_set(rtk_port_t port, rtk_uint32 ocpAddr, rtk_uint32 ocpData); + +/* Function Name: + * dal_rtl8367d_port_phyOCPReg_get + * Description: + * Set PHY OCP register + * Input: + * phyNo - PHY ID + * ocpAddr - OCP register address + * Output: + * pRegData - OCP data. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * None. + */ +extern rtk_api_ret_t dal_rtl8367d_port_phyOCPReg_get(rtk_port_t port, rtk_uint32 ocpAddr, rtk_uint32 *pRegData); + +/* Function Name: + * dal_rtl8367d_port_backpressureEnable_set + * Description: + * Set the half duplex backpressure enable status of the specific port. + * Input: + * port - port id. + * enable - Back pressure status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * This API can set the half duplex backpressure enable status of the specific port. + * The half duplex backpressure enable status of the port is as following: + * - DISABLE + * - ENABLE + */ +extern rtk_api_ret_t dal_rtl8367d_port_backpressureEnable_set(rtk_port_t port, rtk_enable_t enable); + +/* Function Name: + * dal_rtl8367d_port_backpressureEnable_get + * Description: + * Get the half duplex backpressure enable status of the specific port. + * Input: + * port - Port id. + * Output: + * pEnable - Back pressure status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can get the half duplex backpressure enable status of the specific port. + * The half duplex backpressure enable status of the port is as following: + * - DISABLE + * - ENABLE + */ +extern rtk_api_ret_t dal_rtl8367d_port_backpressureEnable_get(rtk_port_t port, rtk_enable_t *pEnable); + +/* Function Name: + * dal_rtl8367d_port_adminEnable_set + * Description: + * Set port admin configuration of the specific port. + * Input: + * port - port id. + * enable - Back pressure status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * This API can set port admin configuration of the specific port. + * The port admin configuration of the port is as following: + * - DISABLE + * - ENABLE + */ +extern rtk_api_ret_t dal_rtl8367d_port_adminEnable_set(rtk_port_t port, rtk_enable_t enable); + +/* Function Name: + * dal_rtl8367d_port_adminEnable_get + * Description: + * Get port admin configurationof the specific port. + * Input: + * port - Port id. + * Output: + * pEnable - Back pressure status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can get port admin configuration of the specific port. + * The port admin configuration of the port is as following: + * - DISABLE + * - ENABLE + */ +extern rtk_api_ret_t dal_rtl8367d_port_adminEnable_get(rtk_port_t port, rtk_enable_t *pEnable); + +/* Function Name: + * dal_rtl8367d_port_isolation_set + * Description: + * Set permitted port isolation portmask + * Input: + * port - port id. + * pPortmask - Permit port mask + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_PORT_MASK - Invalid portmask. + * Note: + * This API set the port mask that a port can trasmit packet to of each port + * A port can only transmit packet to ports included in permitted portmask + */ +extern rtk_api_ret_t dal_rtl8367d_port_isolation_set(rtk_port_t port, rtk_portmask_t *pPortmask); + +/* Function Name: + * dal_rtl8367d_port_isolation_get + * Description: + * Get permitted port isolation portmask + * Input: + * port - Port id. + * Output: + * pPortmask - Permit port mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API get the port mask that a port can trasmit packet to of each port + * A port can only transmit packet to ports included in permitted portmask + */ +extern rtk_api_ret_t dal_rtl8367d_port_isolation_get(rtk_port_t port, rtk_portmask_t *pPortmask); + +/* Function Name: + * dal_rtl8367d_port_rgmiiDelayExt_set + * Description: + * Set RGMII interface delay value for TX and RX. + * Input: + * txDelay - TX delay value, 1 for delay 2ns and 0 for no-delay + * rxDelay - RX delay value, 0~7 for delay setup. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can set external interface 2 RGMII delay. + * In TX delay, there are 2 selection: no-delay and 2ns delay. + * In RX dekay, there are 8 steps for delay tunning. 0 for no-delay, and 7 for maximum delay. + * Note. This API should be called before rtk_port_macForceLinkExt_set(). + */ +extern rtk_api_ret_t dal_rtl8367d_port_rgmiiDelayExt_set(rtk_port_t port, rtk_data_t txDelay, rtk_data_t rxDelay); + +/* Function Name: + * dal_rtl8367d_port_rgmiiDelayExt_get + * Description: + * Get RGMII interface delay value for TX and RX. + * Input: + * None + * Output: + * pTxDelay - TX delay value + * pRxDelay - RX delay value + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can set external interface 2 RGMII delay. + * In TX delay, there are 2 selection: no-delay and 2ns delay. + * In RX dekay, there are 8 steps for delay tunning. 0 for n0-delay, and 7 for maximum delay. + */ +extern rtk_api_ret_t dal_rtl8367d_port_rgmiiDelayExt_get(rtk_port_t port, rtk_data_t *pTxDelay, rtk_data_t *pRxDelay); + +/* Function Name: + * dal_rtl8367d_port_phyEnableAll_set + * Description: + * Set all PHY enable status. + * Input: + * enable - PHY Enable State. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * This API can set all PHY status. + * The configuration of all PHY is as following: + * - DISABLE + * - ENABLE + */ +extern rtk_api_ret_t dal_rtl8367d_port_phyEnableAll_set(rtk_enable_t enable); + +/* Function Name: + * dal_rtl8367d_port_phyEnableAll_get + * Description: + * Get all PHY enable status. + * Input: + * None + * Output: + * pEnable - PHY Enable State. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API can set all PHY status. + * The configuration of all PHY is as following: + * - DISABLE + * - ENABLE + */ +extern rtk_api_ret_t dal_rtl8367d_port_phyEnableAll_get(rtk_enable_t *pEnable); + +/* Function Name: + * dal_rtl8367d_port_phyComboPortMedia_set + * Description: + * Set Combo port media type + * Input: + * port - Port id. (Should be Port 4) + * media - Media (COPPER or FIBER or AUTO) + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API can Set Combo port media type. + */ +extern rtk_api_ret_t dal_rtl8367d_port_phyComboPortMedia_set(rtk_port_t port, rtk_port_media_t media); + +/* Function Name: + * dal_rtl8367d_port_phyComboPortMedia_get + * Description: + * Get Combo port media type + * Input: + * port - Port id. (Should be Port 4) + * Output: + * pMedia - Media (COPPER or FIBER or AUTO) + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API can Set Combo port media type. + */ +extern rtk_api_ret_t dal_rtl8367d_port_phyComboPortMedia_get(rtk_port_t port, rtk_port_media_t *pMedia); + +/* Function Name: + * dal_rtl8367d_port_rtctEnable_set + * Description: + * Enable RTCT test + * Input: + * pPortmask - Port mask of RTCT enabled port + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Invalid port mask. + * Note: + * The API can enable RTCT Test + */ +extern rtk_api_ret_t dal_rtl8367d_port_rtctEnable_set(rtk_portmask_t *pPortmask); + +/* Function Name: + * dal_rtl8367d_port_rtctDisable_set + * Description: + * Disable RTCT test + * Input: + * pPortmask - Port mask of RTCT disabled port + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Invalid port mask. + * Note: + * The API can disable RTCT Test + */ +extern rtk_api_ret_t dal_rtl8367d_port_rtctDisable_set(rtk_portmask_t *pPortmask); + +/* Function Name: + * dal_rtl8367d_port_rtctResult_get + * Description: + * Get the result of RTCT test + * Input: + * port - Port ID + * Output: + * pRtctResult - The result of RTCT result + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port ID. + * RT_ERR_PHY_RTCT_NOT_FINISH - Testing does not finish. + * Note: + * The API can get RTCT test result. + * RTCT test may takes 4.8 seconds to finish its test at most. + * Thus, if this API return RT_ERR_PHY_RTCT_NOT_FINISH or + * other error code, the result can not be referenced and + * user should call this API again until this API returns + * a RT_ERR_OK. + * The result is stored at pRtctResult->ge_result + * pRtctResult->linkType is unused. + * The unit of channel length is 2.5cm. Ex. 300 means 300 * 2.5 = 750cm = 7.5M + */ +extern rtk_api_ret_t dal_rtl8367d_port_rtctResult_get(rtk_port_t port, rtk_rtctResult_t *pRtctResult); + +/* Function Name: + * dal_rtl8367d_port_sgmiiLinkStatus_get + * Description: + * Get SGMII status + * Input: + * port - Port ID + * Output: + * pSignalDetect - Signal detect + * pSync - Sync + * pLink - Link + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API can reset Serdes + */ +extern rtk_api_ret_t dal_rtl8367d_port_sgmiiLinkStatus_get(rtk_port_t port, rtk_data_t *pSignalDetect, rtk_data_t *pSync, rtk_port_linkStatus_t *pLink); + +/* Function Name: + * dal_rtl8367d_port_sgmiiNway_set + * Description: + * Configure SGMII/HSGMII port Nway state + * Input: + * port - Port ID + * state - Nway state + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API configure SGMII/HSGMII port Nway state + */ +extern rtk_api_ret_t dal_rtl8367d_port_sgmiiNway_set(rtk_port_t port, rtk_enable_t state); + +/* Function Name: + * dal_rtl8367d_port_sgmiiNway_get + * Description: + * Get SGMII/HSGMII port Nway state + * Input: + * port - Port ID + * Output: + * pState - Nway state + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API can get SGMII/HSGMII port Nway state + */ +extern rtk_api_ret_t dal_rtl8367d_port_sgmiiNway_get(rtk_port_t port, rtk_enable_t *pState); + +/* Function Name: + * dal_rtl8367d_port_autoDos_set + * Description: + * Set Auto Dos state + * Input: + * type - Auto DoS type + * state - 1: Eanble(Drop), 0: Disable(Forward) + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set Auto Dos state + */ +extern rtk_api_ret_t dal_rtl8367d_port_autoDos_set(rtk_port_autoDosType_t type, rtk_enable_t state); + +/* Function Name: + * dal_rtl8367d_port_autoDos_get + * Description: + * Get Auto Dos state + * Input: + * type - Auto DoS type + * Output: + * pState - 1: Eanble(Drop), 0: Disable(Forward) + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Null Pointer + * Note: + * The API can get Auto Dos state + */ +extern rtk_api_ret_t dal_rtl8367d_port_autoDos_get(rtk_port_autoDosType_t type, rtk_enable_t *pState); + +/* Function Name: + * dal_rtl8367d_port_fiberAbility_set + * Description: + * Configure fiber port ability + * Input: + * port - Port ID + * pAbility - Fiber port ability + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API can configure fiber port ability + */ +extern rtk_api_ret_t dal_rtl8367d_port_fiberAbility_set(rtk_port_t port, rtk_port_fiber_ability_t *pAbility); + +/* Function Name: + * dal_rtl8367d_port_fiberAbility_get + * Description: + * Get fiber port ability + * Input: + * port - Port ID + * Output: + * pAbility - Fiber port ability + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API can get fiber port ability + */ +extern rtk_api_ret_t dal_rtl8367d_port_fiberAbility_get(rtk_port_t port, rtk_port_fiber_ability_t *pAbility); + +/* Function Name: + * dal_rtl8367d_port_phyMdx_set + * Description: + * Set PHY MDI/MDIX state + * Input: + * port - port ID + * mode - PHY MDI/MDIX mode + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set PHY MDI/MDIX state + */ +extern rtk_api_ret_t dal_rtl8367d_port_phyMdx_set(rtk_port_t port, rtk_port_phy_mdix_mode_t mode); + +/* Function Name: + * dal_rtl8367d_port_phyMdx_get + * Description: + * Get PHY MDI/MDIX state + * Input: + * port - port ID + * Output: + * pMode - PHY MDI/MDIX mode + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can get PHY MDI/MDIX state + */ +extern rtk_api_ret_t dal_rtl8367d_port_phyMdx_get(rtk_port_t port, rtk_port_phy_mdix_mode_t *pMode); + +/* Function Name: + * dal_rtl8367d_port_phyMdxStatus_get + * Description: + * Get PHY MDI/MDIX status + * Input: + * port - port ID + * Output: + * pStatus - PHY MDI/MDIX status + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can get PHY MDI/MDIX status + */ +extern rtk_api_ret_t dal_rtl8367d_port_phyMdxStatus_get(rtk_port_t port, rtk_port_phy_mdix_status_t *pStatus); + +/* Function Name: + * dal_rtl8367d_port_phyTestMode_set + * Description: + * Set PHY in test mode. + * Input: + * port - port id. + * mode - PHY test mode 0:normal 1:test mode 1 2:test mode 2 3: test mode 3 4:test mode 4 5~7:reserved + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy + * RT_ERR_NOT_ALLOWED - The Setting is not allowed, caused by set more than 1 port in Test mode. + * Note: + * Set PHY in test mode and only one PHY can be in test mode at the same time. + * It means API will return FAILED if other PHY is in test mode. + * This API only provide test mode 1 & 4 setup. + */ +extern rtk_api_ret_t dal_rtl8367d_port_phyTestMode_set(rtk_port_t port, rtk_port_phy_test_mode_t mode); + +/* Function Name: + * dal_rtl8367d_port_phyTestMode_get + * Description: + * Get PHY in which test mode. + * Input: + * port - Port id. + * Output: + * mode - PHY test mode 0:normal 1:test mode 1 2:test mode 2 3: test mode 3 4:test mode 4 5~7:reserved + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy + * Note: + * Get test mode of PHY from register setting 9.15 to 9.13. + */ +extern rtk_api_ret_t dal_rtl8367d_port_phyTestMode_get(rtk_port_t port, rtk_port_phy_test_mode_t *pMode); + +/* add Implement */ +extern rtk_api_ret_t dal_rtl8367d_setAsicPHYOCPReg(rtk_uint32 phyNo, rtk_uint32 ocpAddr, rtk_uint32 ocpData); +extern rtk_api_ret_t dal_rtl8367d_getAsicPHYOCPReg(rtk_uint32 phyNo, rtk_uint32 ocpAddr, rtk_uint32 *pRegData); +extern rtk_api_ret_t dal_rtl8367d_setAsicPHYReg(rtk_uint32 phyNo, rtk_uint32 phyAddr, rtk_uint32 phyData); +extern rtk_api_ret_t dal_rtl8367d_getAsicPHYReg(rtk_uint32 phyNo, rtk_uint32 phyAddr, rtk_uint32 *pRegData); + +#endif /* __DAL_RTL8367D_PORT_H__ */ + + + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_qos.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_qos.c new file mode 100644 index 00000000..f264bb2c --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_qos.c @@ -0,0 +1,1490 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8367D + * Feature : Here is a list of all functions and variables in QoS module. + * + */ + +#include +#include +#include +#include + +#include + +/* Function Name: + * dal_rtl8367d_qos_init + * Description: + * Configure Qos default settings with queue number assigment to each port. + * Input: + * queueNum - Queue number of each port. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will initialize related Qos setting with queue number assigment. + * The queue number is from 1 to 8. + */ +rtk_api_ret_t dal_rtl8367d_qos_init(rtk_queue_num_t queueNum) +{ + CONST_T rtk_uint16 g_prioritytToQid[8][8]= { + {0, 0,0,0,0,0,0,0}, + {0, 0,0,0,7,7,7,7}, + {0, 0,0,0,1,1,7,7}, + {0, 0,1,1,2,2,7,7}, + {0, 0,1,1,2,3,7,7}, + {0, 0,1,2,3,4,7,7}, + {0, 0,1,2,3,4,5,7}, + {0, 1,2,3,4,5,6,7} + }; + + CONST_T rtk_uint32 g_priorityDecision[8] = {0x01, 0x80,0x04,0x02,0x20,0x40,0x10,0x08}; + CONST_T rtk_uint32 g_prioritytRemap[8] = {0,1,2,3,4,5,6,7}; + + rtk_api_ret_t retVal; + rtk_uint32 qmapidx; + rtk_uint32 priority; + rtk_uint32 priDec; + rtk_uint32 port; + rtk_uint32 dscp; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (queueNum <= 0 || queueNum > RTK_MAX_NUM_OF_QUEUE) + return RT_ERR_QUEUE_NUM; + + /*Set Output Queue Number*/ + if (RTK_MAX_NUM_OF_QUEUE == queueNum) + qmapidx = 0; + else + qmapidx = queueNum; + + RTK_SCAN_ALL_PHY_PORTMASK(port) + { + if ((retVal = rtl8367d_setAsicRegBits((RTL8367D_REG_QOS_PORT_QUEUE_NUMBER_CTRL0 + (port >> 2)), (0x7 << ((port & 0x3) << 2)), qmapidx)) != RT_ERR_OK) + return retVal; + } + + /*Set Priority to Qid*/ + for (priority = 0; priority <= RTK_PRIMAX; priority++) + { + if ((retVal = rtl8367d_setAsicRegBits((RTL8367D_REG_QOS_1Q_PRIORITY_TO_QID_CTRL0 + ((queueNum - 1) << 1) + (priority >> 2)), (RTL8367D_QOS_1Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_MASK << ((priority & 0x3) << 2)), g_prioritytToQid[queueNum - 1][priority])) != RT_ERR_OK) + return retVal; + } + + /*Priority Decision Order*/ + for (priDec = 0;priDec < RTL8367D_PRIDEC_END;priDec++) + { + if ((retVal = rtl8367d_setAsicRegBits((RTL8367D_REG_QOS_INTERNAL_PRIORITY_DECISION_CTRL0 + (priDec >> 1)), (RTL8367D_QOS_INTERNAL_PRIORITY_DECISION_CTRL0_QOS_PORT_WEIGHT_MASK << ((priDec & 1) << 3)), g_priorityDecision[priDec])) != RT_ERR_OK) + return retVal; + if ((retVal = rtl8367d_setAsicRegBits((RTL8367D_REG_QOS_INTERNAL_PRIORITY_DECISION_CTRL1 + (priDec >> 1)), (RTL8367D_QOS_INTERNAL_PRIORITY_DECISION_CTRL0_QOS_PORT_WEIGHT_MASK << ((priDec & 1) << 3)), g_priorityDecision[priDec])) != RT_ERR_OK) + return retVal; + } + + /*Set Port-based Priority to 0*/ + RTK_SCAN_ALL_PHY_PORTMASK(port) + { + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_QOS_PORTBASED_PRIORITY_CTRL0 + (port >> 2), (0x7 << ((port & 0x3) << 2)), 0)) != RT_ERR_OK) + return retVal; + } + + RTK_SCAN_ALL_PHY_PORTMASK(port) + { + /*Disable 1p Remarking*/ + if ((retVal = rtl8367d_setAsicRegBit((RTL8367D_REG_PORT0_MISC_CFG + (port << 5)), RTL8367D_PORT0_MISC_CFG_DOT1Q_REMARK_ENABLE_OFFSET, DISABLED)) != RT_ERR_OK) + return retVal; + /*Disable DSCP Remarking*/ + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_SWITCH_CTRL0, RTL8367D_PORT0_REMARKING_DSCP_ENABLE_OFFSET + port, DISABLED)) != RT_ERR_OK) + return retVal; + } + + /*Set 1p & DSCP Priority Remapping & Remarking*/ + for (priority = 0; priority <= RTL8367D_PRIMAX; priority++) + { + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_QOS_1Q_PRIORITY_REMAPPING_CTRL0 + (priority >> 2), (0x7 << ((priority & 0x3) << 2)), g_prioritytRemap[priority])) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicRegBits((RTL8367D_REG_QOS_1Q_REMARK_CTRL0 + (priority >> 2)), (0x7 << ((priority & 0x3) << 2)), 0)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicRegBits((RTL8367D_REG_QOS_DSCP_REMARK_CTRL0 + (priority >> 1)), (0x3F << (((priority) & 0x1) << 3)), 0)) != RT_ERR_OK) + return retVal; + } + + /*Set DSCP Priority*/ + for (dscp = 0; dscp <= 63; dscp++) + { + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_QOS_DSCP_TO_PRIORITY_CTRL0 + (dscp >> 2), (0x7 << ((dscp & 0x3) << 2)), 0)) != RT_ERR_OK) + return retVal; + } + + /* Finetune B/T value */ + if((retVal = rtl8367d_setAsicReg(0x1722, 0x1158)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_qos_priSel_set + * Description: + * Configure the priority order among different priority mechanism. + * Input: + * index - Priority decision table index (0~1) + * pPriDec - Priority assign for port, dscp, 802.1p, cvlan, svlan, acl based priority decision. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_SEL_PRI_SOURCE - Invalid priority decision source parameter. + * Note: + * ASIC will follow user priority setting of mechanisms to select mapped queue priority for receiving frame. + * If two priority mechanisms are the same, the ASIC will chose the highest priority from mechanisms to + * assign queue priority to receiving frame. + * The priority sources are: + * - RTL8367D_PRIDEC_PORT + * - RTL8367D_PRIDEC_ACL + * - RTL8367D_PRIDEC_DSCP + * - RTL8367D_PRIDEC_1Q + * - RTL8367D_PRIDEC_1AD + */ +rtk_api_ret_t dal_rtl8367d_qos_priSel_set(rtk_qos_priDecTbl_t index, rtk_priority_select_t *pPriDec) +{ + rtk_api_ret_t retVal; + rtk_uint32 port_pow; + rtk_uint32 dot1q_pow; + rtk_uint32 dscp_pow; + rtk_uint32 acl_pow; + rtk_uint32 svlan_pow; + rtk_uint32 i; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (index < 0 || index >= PRIDECTBL_END) + return RT_ERR_ENTRY_INDEX; + + if (pPriDec->port_pri >= 5 || pPriDec->dot1q_pri >= 5 || pPriDec->acl_pri >= 5 || pPriDec->dscp_pri >= 5 || + pPriDec->svlan_pri >= 5) + return RT_ERR_QOS_SEL_PRI_SOURCE; + + port_pow = 1; + for (i = pPriDec->port_pri; i > 0; i--) + port_pow = (port_pow)*2; + + dot1q_pow = 1; + for (i = pPriDec->dot1q_pri; i > 0; i--) + dot1q_pow = (dot1q_pow)*2; + + acl_pow = 1; + for (i = pPriDec->acl_pri; i > 0; i--) + acl_pow = (acl_pow)*2; + + dscp_pow = 1; + for (i = pPriDec->dscp_pri; i > 0; i--) + dscp_pow = (dscp_pow)*2; + + svlan_pow = 1; + for (i = pPriDec->svlan_pri; i > 0; i--) + svlan_pow = (svlan_pow)*2; + + switch(index) + { + case PRIDECTBL_IDX0: + if ((retVal = rtl8367d_setAsicRegBits((RTL8367D_REG_QOS_INTERNAL_PRIORITY_DECISION_CTRL0 + (RTL8367D_PRIDEC_PORT >> 1)), (RTL8367D_QOS_INTERNAL_PRIORITY_DECISION_CTRL0_QOS_PORT_WEIGHT_MASK << ((RTL8367D_PRIDEC_PORT & 1) << 3)), port_pow)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicRegBits((RTL8367D_REG_QOS_INTERNAL_PRIORITY_DECISION_CTRL0 + (RTL8367D_PRIDEC_ACL >> 1)), (RTL8367D_QOS_INTERNAL_PRIORITY_DECISION_CTRL0_QOS_PORT_WEIGHT_MASK << ((RTL8367D_PRIDEC_ACL & 1) << 3)), acl_pow)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicRegBits((RTL8367D_REG_QOS_INTERNAL_PRIORITY_DECISION_CTRL0 + (RTL8367D_PRIDEC_DSCP >> 1)), (RTL8367D_QOS_INTERNAL_PRIORITY_DECISION_CTRL0_QOS_PORT_WEIGHT_MASK << ((RTL8367D_PRIDEC_DSCP & 1) << 3)), dscp_pow)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicRegBits((RTL8367D_REG_QOS_INTERNAL_PRIORITY_DECISION_CTRL0 + (RTL8367D_PRIDEC_1Q >> 1)), (RTL8367D_QOS_INTERNAL_PRIORITY_DECISION_CTRL0_QOS_PORT_WEIGHT_MASK << ((RTL8367D_PRIDEC_1Q & 1) << 3)), dot1q_pow)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicRegBits((RTL8367D_REG_QOS_INTERNAL_PRIORITY_DECISION_CTRL0 + (RTL8367D_PRIDEC_1AD >> 1)), (RTL8367D_QOS_INTERNAL_PRIORITY_DECISION_CTRL0_QOS_PORT_WEIGHT_MASK << ((RTL8367D_PRIDEC_1AD & 1) << 3)), svlan_pow)) != RT_ERR_OK) + return retVal; + break; + + case PRIDECTBL_IDX1: + if ((retVal = rtl8367d_setAsicRegBits((RTL8367D_REG_QOS_INTERNAL_PRIORITY_DECISION2_CTRL0 + (RTL8367D_PRIDEC_PORT >> 1)), (RTL8367D_QOS_INTERNAL_PRIORITY_DECISION2_CTRL0_QOS_PORT_WEIGHT_MASK << ((RTL8367D_PRIDEC_PORT & 1) << 3)), port_pow)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicRegBits((RTL8367D_REG_QOS_INTERNAL_PRIORITY_DECISION2_CTRL0 + (RTL8367D_PRIDEC_ACL >> 1)), (RTL8367D_QOS_INTERNAL_PRIORITY_DECISION2_CTRL0_QOS_PORT_WEIGHT_MASK << ((RTL8367D_PRIDEC_ACL & 1) << 3)), acl_pow)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicRegBits((RTL8367D_REG_QOS_INTERNAL_PRIORITY_DECISION2_CTRL0 + (RTL8367D_PRIDEC_DSCP >> 1)), (RTL8367D_QOS_INTERNAL_PRIORITY_DECISION2_CTRL0_QOS_PORT_WEIGHT_MASK << ((RTL8367D_PRIDEC_DSCP & 1) << 3)), dscp_pow)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicRegBits((RTL8367D_REG_QOS_INTERNAL_PRIORITY_DECISION2_CTRL0 + (RTL8367D_PRIDEC_1Q >> 1)), (RTL8367D_QOS_INTERNAL_PRIORITY_DECISION2_CTRL0_QOS_PORT_WEIGHT_MASK << ((RTL8367D_PRIDEC_1Q & 1) << 3)), dot1q_pow)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicRegBits((RTL8367D_REG_QOS_INTERNAL_PRIORITY_DECISION2_CTRL0 + (RTL8367D_PRIDEC_1AD >> 1)), (RTL8367D_QOS_INTERNAL_PRIORITY_DECISION2_CTRL0_QOS_PORT_WEIGHT_MASK << ((RTL8367D_PRIDEC_1AD & 1) << 3)), svlan_pow)) != RT_ERR_OK) + return retVal; + break; + default: + return RT_ERR_INPUT; + + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_qos_priSel_get + * Description: + * Get the priority order configuration among different priority mechanism. + * Input: + * index - Priority decision table index (0~1) + * Output: + * pPriDec - Priority assign for port, dscp, 802.1p, cvlan, svlan, acl based priority decision . + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * ASIC will follow user priority setting of mechanisms to select mapped queue priority for receiving frame. + * If two priority mechanisms are the same, the ASIC will chose the highest priority from mechanisms to + * assign queue priority to receiving frame. + * The priority sources are: + * - RTL8367D_PRIDEC_PORT, + * - RTL8367D_PRIDEC_ACL, + * - RTL8367D_PRIDEC_DSCP, + * - RTL8367D_PRIDEC_1Q, + * - RTL8367D_PRIDEC_1AD, + */ +rtk_api_ret_t dal_rtl8367d_qos_priSel_get(rtk_qos_priDecTbl_t index, rtk_priority_select_t *pPriDec) +{ + + rtk_api_ret_t retVal; + rtk_int32 i; + rtk_uint32 port_pow; + rtk_uint32 dot1q_pow; + rtk_uint32 dscp_pow; + rtk_uint32 acl_pow; + rtk_uint32 svlan_pow; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (index < 0 || index >= PRIDECTBL_END) + return RT_ERR_ENTRY_INDEX; + + memset(pPriDec, 0x00, sizeof(rtk_priority_select_t)); + + switch(index) + { + case PRIDECTBL_IDX0: + if ((retVal = rtl8367d_getAsicRegBits((RTL8367D_REG_QOS_INTERNAL_PRIORITY_DECISION_CTRL0 + (RTL8367D_PRIDEC_PORT >> 1)), (RTL8367D_QOS_INTERNAL_PRIORITY_DECISION_CTRL0_QOS_PORT_WEIGHT_MASK << ((RTL8367D_PRIDEC_PORT & 1) << 3)), &port_pow)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_getAsicRegBits((RTL8367D_REG_QOS_INTERNAL_PRIORITY_DECISION_CTRL0 + (RTL8367D_PRIDEC_ACL >> 1)), (RTL8367D_QOS_INTERNAL_PRIORITY_DECISION_CTRL0_QOS_PORT_WEIGHT_MASK << ((RTL8367D_PRIDEC_ACL & 1) << 3)), &acl_pow)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_getAsicRegBits((RTL8367D_REG_QOS_INTERNAL_PRIORITY_DECISION_CTRL0 + (RTL8367D_PRIDEC_DSCP >> 1)), (RTL8367D_QOS_INTERNAL_PRIORITY_DECISION_CTRL0_QOS_PORT_WEIGHT_MASK << ((RTL8367D_PRIDEC_DSCP & 1) << 3)), &dscp_pow)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_getAsicRegBits((RTL8367D_REG_QOS_INTERNAL_PRIORITY_DECISION_CTRL0 + (RTL8367D_PRIDEC_1Q >> 1)), (RTL8367D_QOS_INTERNAL_PRIORITY_DECISION_CTRL0_QOS_PORT_WEIGHT_MASK << ((RTL8367D_PRIDEC_1Q & 1) << 3)), &dot1q_pow)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_getAsicRegBits((RTL8367D_REG_QOS_INTERNAL_PRIORITY_DECISION_CTRL0 + (RTL8367D_PRIDEC_1AD >> 1)), (RTL8367D_QOS_INTERNAL_PRIORITY_DECISION_CTRL0_QOS_PORT_WEIGHT_MASK << ((RTL8367D_PRIDEC_1AD & 1) << 3)), &svlan_pow)) != RT_ERR_OK) + return retVal; + break; + + case PRIDECTBL_IDX1: + if ((retVal = rtl8367d_getAsicRegBits((RTL8367D_REG_QOS_INTERNAL_PRIORITY_DECISION2_CTRL0 + (RTL8367D_PRIDEC_PORT >> 1)), (RTL8367D_QOS_INTERNAL_PRIORITY_DECISION2_CTRL0_QOS_PORT_WEIGHT_MASK << ((RTL8367D_PRIDEC_PORT & 1) << 3)), &port_pow)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_getAsicRegBits((RTL8367D_REG_QOS_INTERNAL_PRIORITY_DECISION2_CTRL0 + (RTL8367D_PRIDEC_ACL >> 1)), (RTL8367D_QOS_INTERNAL_PRIORITY_DECISION2_CTRL0_QOS_PORT_WEIGHT_MASK << ((RTL8367D_PRIDEC_ACL & 1) << 3)), &acl_pow)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_getAsicRegBits((RTL8367D_REG_QOS_INTERNAL_PRIORITY_DECISION2_CTRL0 + (RTL8367D_PRIDEC_DSCP >> 1)), (RTL8367D_QOS_INTERNAL_PRIORITY_DECISION2_CTRL0_QOS_PORT_WEIGHT_MASK << ((RTL8367D_PRIDEC_DSCP & 1) << 3)), &dscp_pow)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_getAsicRegBits((RTL8367D_REG_QOS_INTERNAL_PRIORITY_DECISION2_CTRL0 + (RTL8367D_PRIDEC_1Q >> 1)), (RTL8367D_QOS_INTERNAL_PRIORITY_DECISION2_CTRL0_QOS_PORT_WEIGHT_MASK << ((RTL8367D_PRIDEC_1Q & 1) << 3)), &dot1q_pow)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_getAsicRegBits((RTL8367D_REG_QOS_INTERNAL_PRIORITY_DECISION2_CTRL0 + (RTL8367D_PRIDEC_1AD >> 1)), (RTL8367D_QOS_INTERNAL_PRIORITY_DECISION2_CTRL0_QOS_PORT_WEIGHT_MASK << ((RTL8367D_PRIDEC_1AD & 1) << 3)), &svlan_pow)) != RT_ERR_OK) + return retVal; + break; + + default: + return RT_ERR_INPUT; + + } + + for (i = 31; i >= 0; i--) + { + if (port_pow & (1 << i)) + { + pPriDec->port_pri = i; + break; + } + } + + for (i = 31; i >= 0; i--) + { + if (dot1q_pow & (1 << i)) + { + pPriDec->dot1q_pri = i; + break; + } + } + + for (i = 31; i >= 0; i--) + { + if (acl_pow & (1 << i)) + { + pPriDec->acl_pri = i; + break; + } + } + + for (i = 31; i >= 0; i--) + { + if (dscp_pow & (1 << i)) + { + pPriDec->dscp_pri = i; + break; + } + } + + for (i = 31; i >= 0; i--) + { + if (svlan_pow & (1 << i)) + { + pPriDec->svlan_pri = i; + break; + } + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_qos_1pPriRemap_set + * Description: + * Configure 1Q priorities mapping to internal absolute priority. + * Input: + * dot1p_pri - 802.1p priority value. + * int_pri - internal priority value. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_VLAN_PRIORITY - Invalid 1p priority. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * Priority of 802.1Q assignment for internal asic priority, and it is used for queue usage and packet scheduling. + */ +rtk_api_ret_t dal_rtl8367d_qos_1pPriRemap_set(rtk_pri_t dot1p_pri, rtk_pri_t int_pri) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (dot1p_pri > RTL8367D_PRIMAX || int_pri > RTL8367D_PRIMAX) + return RT_ERR_VLAN_PRIORITY; + + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_QOS_1Q_PRIORITY_REMAPPING_CTRL0 + (dot1p_pri >> 2), (0x7 << ((dot1p_pri & 0x3) << 2)), int_pri)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_qos_1pPriRemap_get + * Description: + * Get 1Q priorities mapping to internal absolute priority. + * Input: + * dot1p_pri - 802.1p priority value . + * Output: + * pInt_pri - internal priority value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_VLAN_PRIORITY - Invalid priority. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * Priority of 802.1Q assigment for internal asic priority, and it is uesed for queue usage and packet scheduling. + */ +rtk_api_ret_t dal_rtl8367d_qos_1pPriRemap_get(rtk_pri_t dot1p_pri, rtk_pri_t *pInt_pri) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (dot1p_pri > RTL8367D_PRIMAX) + return RT_ERR_QOS_INT_PRIORITY; + + if ((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_QOS_1Q_PRIORITY_REMAPPING_CTRL0 + (dot1p_pri >> 2), (0x7 << ((dot1p_pri & 0x3) << 2)), pInt_pri)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_qos_dscpPriRemap_set + * Description: + * Map dscp value to internal priority. + * Input: + * dscp - Dscp value of receiving frame + * int_pri - internal priority value . + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_QOS_DSCP_VALUE - Invalid DSCP value. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * The Differentiated Service Code Point is a selector for router's per-hop behaviors. As a selector, there is no implication that a numerically + * greater DSCP implies a better network service. As can be seen, the DSCP totally overlaps the old precedence field of TOS. So if values of + * DSCP are carefully chosen then backward compatibility can be achieved. + */ +rtk_api_ret_t dal_rtl8367d_qos_dscpPriRemap_set(rtk_dscp_t dscp, rtk_pri_t int_pri) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (int_pri > RTL8367D_PRIMAX ) + return RT_ERR_QOS_INT_PRIORITY; + + if (dscp > RTL8367D_DSCPMAX) + return RT_ERR_QOS_DSCP_VALUE; + + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_QOS_DSCP_TO_PRIORITY_CTRL0 + (dscp >> 2), (0x7 << ((dscp & 0x3) << 2)), int_pri)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_qos_dscpPriRemap_get + * Description: + * Get dscp value to internal priority. + * Input: + * dscp - Dscp value of receiving frame + * Output: + * pInt_pri - internal priority value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_DSCP_VALUE - Invalid DSCP value. + * Note: + * The Differentiated Service Code Point is a selector for router's per-hop behaviors. As a selector, there is no implication that a numerically + * greater DSCP implies a better network service. As can be seen, the DSCP totally overlaps the old precedence field of TOS. So if values of + * DSCP are carefully chosen then backward compatibility can be achieved. + */ +rtk_api_ret_t dal_rtl8367d_qos_dscpPriRemap_get(rtk_dscp_t dscp, rtk_pri_t *pInt_pri) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (dscp > RTL8367D_DSCPMAX) + return RT_ERR_QOS_DSCP_VALUE; + + if ((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_QOS_DSCP_TO_PRIORITY_CTRL0 + (dscp >> 2), (0x7 << ((dscp & 0x3) << 2)), pInt_pri)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_qos_portPri_set + * Description: + * Configure priority usage to each port. + * Input: + * port - Port id. + * int_pri - internal priority value. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_QOS_SEL_PORT_PRI - Invalid port priority. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * The API can set priority of port assignments for queue usage and packet scheduling. + */ +rtk_api_ret_t dal_rtl8367d_qos_portPri_set(rtk_port_t port, rtk_pri_t int_pri) +{ + rtk_api_ret_t retVal; + rtk_uint32 phy_port; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if (int_pri > RTL8367D_PRIMAX ) + return RT_ERR_QOS_INT_PRIORITY; + + phy_port = rtk_switch_port_L2P_get(port); + + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_QOS_PORTBASED_PRIORITY_CTRL0 + (phy_port >> 2), (0x7 << ((phy_port & 0x3) << 2)), int_pri)) != RT_ERR_OK) + + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_qos_portPri_get + * Description: + * Get priority usage to each port. + * Input: + * port - Port id. + * Output: + * pInt_pri - internal priority value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get priority of port assignments for queue usage and packet scheduling. + */ +rtk_api_ret_t dal_rtl8367d_qos_portPri_get(rtk_port_t port, rtk_pri_t *pInt_pri) +{ + rtk_api_ret_t retVal; + rtk_uint32 phy_port; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + phy_port = rtk_switch_port_L2P_get(port); + + if ((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_QOS_PORTBASED_PRIORITY_CTRL0 + (phy_port >> 2), (0x7 << ((phy_port & 0x3) << 2)), pInt_pri)) != RT_ERR_OK) + return retVal; + + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_qos_queueNum_set + * Description: + * Set output queue number for each port. + * Input: + * port - Port id. + * index - Mapping queue number (1~8) + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_QUEUE_NUM - Invalid queue number. + * Note: + * The API can set the output queue number of the specified port. The queue number is from 1 to 8. + */ +rtk_api_ret_t dal_rtl8367d_qos_queueNum_set(rtk_port_t port, rtk_queue_num_t queue_num) +{ + rtk_api_ret_t retVal; + rtk_uint32 phy_port; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if ((0 == queue_num) || (queue_num > RTK_MAX_NUM_OF_QUEUE)) + return RT_ERR_FAILED; + + if (RTK_MAX_NUM_OF_QUEUE == queue_num) + queue_num = 0; + + phy_port = rtk_switch_port_L2P_get(port); + + if ((retVal = rtl8367d_setAsicRegBits((RTL8367D_REG_QOS_PORT_QUEUE_NUMBER_CTRL0 + (phy_port >> 2)), (0x7 << ((phy_port & 0x3) << 2)), queue_num)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_qos_queueNum_get + * Description: + * Get output queue number. + * Input: + * port - Port id. + * Output: + * pQueue_num - Mapping queue number + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API will return the output queue number of the specified port. The queue number is from 1 to 8. + */ +rtk_api_ret_t dal_rtl8367d_qos_queueNum_get(rtk_port_t port, rtk_queue_num_t *pQueue_num) +{ + rtk_api_ret_t retVal; + rtk_uint32 qidx; + rtk_uint32 phy_port; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + phy_port = rtk_switch_port_L2P_get(port); + + if ((retVal = rtl8367d_getAsicRegBits((RTL8367D_REG_QOS_PORT_QUEUE_NUMBER_CTRL0 + (phy_port >> 2)), (0x7 << ((phy_port & 0x3) << 2)), &qidx)) != RT_ERR_OK) + return retVal; + + if (0 == qidx) + *pQueue_num = 8; + else + *pQueue_num = qidx; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_qos_priMap_set + * Description: + * Set output queue number for each port. + * Input: + * queue_num - Queue number usage. + * pPri2qid - Priority mapping to queue ID. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_QUEUE_ID - Invalid queue id. + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * ASIC supports priority mapping to queue with different queue number from 1 to 8. + * For different queue numbers usage, ASIC supports different internal available queue IDs. + */ +rtk_api_ret_t dal_rtl8367d_qos_priMap_set(rtk_queue_num_t queue_num, rtk_qos_pri2queue_t *pPri2qid) +{ + rtk_api_ret_t retVal; + rtk_uint32 pri; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if ((0 == queue_num) || (queue_num > RTK_MAX_NUM_OF_QUEUE)) + return RT_ERR_QUEUE_NUM; + + for (pri = 0; pri <= RTK_PRIMAX; pri++) + { + if (pPri2qid->pri2queue[pri] > RTK_QIDMAX) + return RT_ERR_QUEUE_ID; + + if ((retVal = rtl8367d_setAsicRegBits((RTL8367D_REG_QOS_1Q_PRIORITY_TO_QID_CTRL0 + ((queue_num - 1) << 1) + (pri >> 2)), (RTL8367D_QOS_1Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_MASK << ((pri & 0x3) << 2)), pPri2qid->pri2queue[pri])) != RT_ERR_OK) + return retVal; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_qos_priMap_get + * Description: + * Get priority to queue ID mapping table parameters. + * Input: + * queue_num - Queue number usage. + * Output: + * pPri2qid - Priority mapping to queue ID. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_QUEUE_NUM - Invalid queue number. + * Note: + * The API can return the mapping queue id of the specified priority and queue number. + * The queue number is from 1 to 8. + */ +rtk_api_ret_t dal_rtl8367d_qos_priMap_get(rtk_queue_num_t queue_num, rtk_qos_pri2queue_t *pPri2qid) +{ + rtk_api_ret_t retVal; + rtk_uint32 pri; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if ((0 == queue_num) || (queue_num > RTK_MAX_NUM_OF_QUEUE)) + return RT_ERR_QUEUE_NUM; + + for (pri = 0; pri <= RTK_PRIMAX; pri++) + { + + if ((retVal = rtl8367d_getAsicRegBits((RTL8367D_REG_QOS_1Q_PRIORITY_TO_QID_CTRL0 + ((queue_num-1) << 1) + (pri >> 2)), (RTL8367D_QOS_1Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_MASK << ((pri & 0x3) << 2)), &pPri2qid->pri2queue[pri])) != RT_ERR_OK) + return retVal; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_qos_schedulingQueue_set + * Description: + * Set weight and type of queues in dedicated port. + * Input: + * port - Port id. + * pQweights - The array of weights for WRR/WFQ queue (0 for STRICT_PRIORITY queue). + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_QOS_QUEUE_WEIGHT - Invalid queue weight. + * Note: + * The API can set weight and type, strict priority or weight fair queue (WFQ) for + * dedicated port for using queues. If queue id is not included in queue usage, + * then its type and weight setting in dummy for setting. There are priorities + * as queue id in strict queues. It means strict queue id 5 carrying higher priority + * than strict queue id 4. The WFQ queue weight is from 1 to 127, and weight 0 is + * for strict priority queue type. + */ +rtk_api_ret_t dal_rtl8367d_qos_schedulingQueue_set(rtk_port_t port, rtk_qos_queue_weights_t *pQweights) +{ + rtk_api_ret_t retVal; + rtk_uint32 qid; + rtk_uint32 phy_port; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + for (qid = 0; qid < RTL8367D_QUEUENO; qid ++) + { + + if (pQweights->weights[qid] > QOS_WEIGHT_MAX) + return RT_ERR_QOS_QUEUE_WEIGHT; + + phy_port = rtk_switch_port_L2P_get(port); + + if (0 == pQweights->weights[qid]) + { + if ((retVal = rtl8367d_setAsicRegBit((RTL8367D_REG_SCHEDULE_QUEUE_TYPE_CTRL0 + (phy_port >> 1)), (((phy_port & 0x1) << 3) + qid),RTL8367D_QTYPE_STRICT)) != RT_ERR_OK) + return retVal; + } + else + { + if ((retVal = rtl8367d_setAsicRegBit((RTL8367D_REG_SCHEDULE_QUEUE_TYPE_CTRL0 + (phy_port >> 1)), (((phy_port & 0x1) << 3) + qid),RTL8367D_QTYPE_WFQ)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicReg((RTL8367D_REG_SCHEDULE_PORT0_QUEUE0_WFQ_WEIGHT + (phy_port << 3) + qid), pQweights->weights[qid])) != RT_ERR_OK) + return retVal; + } + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_qos_schedulingQueue_get + * Description: + * Get weight and type of queues in dedicated port. + * Input: + * port - Port id. + * Output: + * pQweights - The array of weights for WRR/WFQ queue (0 for STRICT_PRIORITY queue). + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get weight and type, strict priority or weight fair queue (WFQ) for dedicated port for using queues. + * The WFQ queue weight is from 1 to 127, and weight 0 is for strict priority queue type. + */ +rtk_api_ret_t dal_rtl8367d_qos_schedulingQueue_get(rtk_port_t port, rtk_qos_queue_weights_t *pQweights) +{ + rtk_api_ret_t retVal; + rtk_uint32 qid,qtype,qweight,phy_port; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + phy_port = rtk_switch_port_L2P_get(port); + + for (qid = 0; qid < RTL8367D_QUEUENO; qid++) + { + if ((retVal = rtl8367d_getAsicRegBit((RTL8367D_REG_SCHEDULE_QUEUE_TYPE_CTRL0 + (phy_port >> 1)), (((phy_port & 0x1) << 3) + qid),&qtype)) != RT_ERR_OK) + return retVal; + + if (RTL8367D_QTYPE_STRICT == qtype) + { + pQweights->weights[qid] = 0; + } + else if (RTL8367D_QTYPE_WFQ == qtype) + { + if ((retVal = rtl8367d_getAsicReg((RTL8367D_REG_SCHEDULE_PORT0_QUEUE0_WFQ_WEIGHT + (phy_port << 3) + qid), &qweight)) != RT_ERR_OK) + return retVal; + pQweights->weights[qid] = qweight; + } + } + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_qos_1pRemarkEnable_set + * Description: + * Set 1p Remarking state + * Input: + * port - Port id. + * enable - State of per-port 1p Remarking + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable parameter. + * Note: + * The API can enable or disable 802.1p remarking ability for whole system. + * The status of 802.1p remark: + * - DISABLED + * - ENABLED + */ +rtk_api_ret_t dal_rtl8367d_qos_1pRemarkEnable_set(rtk_port_t port, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + rtk_uint32 phy_port; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if (enable >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + phy_port = rtk_switch_port_L2P_get(port); + + if ((retVal = rtl8367d_setAsicRegBit((RTL8367D_REG_PORT0_MISC_CFG + (phy_port << 5)), RTL8367D_PORT0_MISC_CFG_DOT1Q_REMARK_ENABLE_OFFSET, enable)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_qos_1pRemarkEnable_get + * Description: + * Get 802.1p remarking ability. + * Input: + * port - Port id. + * Output: + * pEnable - Status of 802.1p remark. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get 802.1p remarking ability. + * The status of 802.1p remark: + * - DISABLED + * - ENABLED + */ +rtk_api_ret_t dal_rtl8367d_qos_1pRemarkEnable_get(rtk_port_t port, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + rtk_uint32 phy_port; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + phy_port = rtk_switch_port_L2P_get(port); + + if ((retVal = rtl8367d_getAsicRegBit((RTL8367D_REG_PORT0_MISC_CFG + (phy_port << 5)), RTL8367D_PORT0_MISC_CFG_DOT1Q_REMARK_ENABLE_OFFSET, pEnable)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_qos_1pRemark_set + * Description: + * Set 802.1p remarking parameter. + * Input: + * int_pri - Internal priority value. + * dot1p_pri - 802.1p priority value. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_VLAN_PRIORITY - Invalid 1p priority. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * The API can set 802.1p parameters source priority and new priority. + */ +rtk_api_ret_t dal_rtl8367d_qos_1pRemark_set(rtk_pri_t int_pri, rtk_pri_t dot1p_pri) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (int_pri > RTL8367D_PRIMAX ) + return RT_ERR_QOS_INT_PRIORITY; + + if (dot1p_pri > RTL8367D_PRIMAX) + return RT_ERR_VLAN_PRIORITY; + + if ((retVal = rtl8367d_setAsicRegBits((RTL8367D_REG_QOS_1Q_REMARK_CTRL0 + (int_pri >> 2)), (0x7 << ((int_pri & 0x3) << 2)), dot1p_pri)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_qos_1pRemark_get + * Description: + * Get 802.1p remarking parameter. + * Input: + * int_pri - Internal priority value. + * Output: + * pDot1p_pri - 802.1p priority value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * The API can get 802.1p remarking parameters. It would return new priority of ingress priority. + */ +rtk_api_ret_t dal_rtl8367d_qos_1pRemark_get(rtk_pri_t int_pri, rtk_pri_t *pDot1p_pri) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (int_pri > RTL8367D_PRIMAX ) + return RT_ERR_QOS_INT_PRIORITY; + + if ((retVal = rtl8367d_getAsicRegBits((RTL8367D_REG_QOS_1Q_REMARK_CTRL0 + (int_pri >> 2)), (0x7 << ((int_pri & 0x3) << 2)), pDot1p_pri)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_qos_1pRemarkSrcSel_set + * Description: + * Set remarking source of 802.1p remarking. + * Input: + * type - remarking source + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + + * Note: + * The API can configure 802.1p remark functionality to map original 802.1p value or internal + * priority to TX DSCP value. + */ +rtk_api_ret_t dal_rtl8367d_qos_1pRemarkSrcSel_set(rtk_qos_1pRmkSrc_t type) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (type >= DOT1P_RMK_SRC_END ) + return RT_ERR_QOS_INT_PRIORITY; + + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_RMK_CFG_SEL_CTRL, RTL8367D_RMK_1Q_CFG_SEL_OFFSET, type)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_qos_1pRemarkSrcSel_get + * Description: + * Get remarking source of 802.1p remarking. + * Input: + * none + * Output: + * pType - remarking source + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * RT_ERR_NULL_POINTER - input parameter may be null pointer + + * Note: + * None + */ +rtk_api_ret_t dal_rtl8367d_qos_1pRemarkSrcSel_get(rtk_qos_1pRmkSrc_t *pType) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_RMK_CFG_SEL_CTRL, RTL8367D_RMK_1Q_CFG_SEL_OFFSET, pType)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_qos_dscpRemarkEnable_set + * Description: + * Set DSCP remarking ability. + * Input: + * port - Port id. + * enable - status of DSCP remark. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * RT_ERR_ENABLE - Invalid enable parameter. + * Note: + * The API can enable or disable DSCP remarking ability for whole system. + * The status of DSCP remark: + * - DISABLED + * - ENABLED + */ +rtk_api_ret_t dal_rtl8367d_qos_dscpRemarkEnable_set(rtk_port_t port, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + rtk_uint32 phy_port; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if (enable >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + phy_port = rtk_switch_port_L2P_get(port); + + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_SWITCH_CTRL0, RTL8367D_PORT0_REMARKING_DSCP_ENABLE_OFFSET + phy_port, enable)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_qos_dscpRemarkEnable_get + * Description: + * Get DSCP remarking ability. + * Input: + * port - Port id. + * Output: + * pEnable - status of DSCP remarking. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get DSCP remarking ability. + * The status of DSCP remark: + * - DISABLED + * - ENABLED + */ +rtk_api_ret_t dal_rtl8367d_qos_dscpRemarkEnable_get(rtk_port_t port, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + rtk_uint32 phy_port; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + phy_port = rtk_switch_port_L2P_get(port); + + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_SWITCH_CTRL0, RTL8367D_PORT0_REMARKING_DSCP_ENABLE_OFFSET + phy_port, pEnable)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_qos_dscpRemark_set + * Description: + * Set DSCP remarking parameter. + * Input: + * int_pri - Internal priority value. + * dscp - DSCP value. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * RT_ERR_QOS_DSCP_VALUE - Invalid DSCP value. + * Note: + * The API can set DSCP value and mapping priority. + */ +rtk_api_ret_t dal_rtl8367d_qos_dscpRemark_set(rtk_pri_t int_pri, rtk_dscp_t dscp) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (int_pri > RTK_PRIMAX ) + return RT_ERR_QOS_INT_PRIORITY; + + if (dscp > RTK_DSCPMAX) + return RT_ERR_QOS_DSCP_VALUE; + + if ((retVal = rtl8367d_setAsicRegBits((RTL8367D_REG_QOS_DSCP_REMARK_CTRL0 + (int_pri >> 1)), (0x3F << (((int_pri) & 0x1) << 3)), dscp)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_qos_dscpRemark_get + * Description: + * Get DSCP remarking parameter. + * Input: + * int_pri - Internal priority value. + * Output: + * Dscp - DSCP value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * The API can get DSCP parameters. It would return DSCP value for mapping priority. + */ + +rtk_api_ret_t dal_rtl8367d_qos_dscpRemark_get(rtk_pri_t int_pri, rtk_dscp_t *pDscp) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (int_pri > RTK_PRIMAX ) + return RT_ERR_QOS_INT_PRIORITY; + + if ((retVal = rtl8367d_getAsicRegBits((RTL8367D_REG_QOS_DSCP_REMARK_CTRL0 + (int_pri >> 1)), (0x3F << (((int_pri) & 0x1) << 3)), pDscp)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_qos_dscpRemarkSrcSel_set + * Description: + * Set remarking source of DSCP remarking. + * Input: + * type - remarking source + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + + * Note: + * The API can configure DSCP remark functionality to map original DSCP value or internal + * priority to TX DSCP value. + */ +rtk_api_ret_t dal_rtl8367d_qos_dscpRemarkSrcSel_set(rtk_qos_dscpRmkSrc_t type) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (type >= DSCP_RMK_SRC_END ) + return RT_ERR_QOS_INT_PRIORITY; + + if (type == DSCP_RMK_SRC_DSCP ) + return RT_ERR_QOS_INT_PRIORITY; + + switch (type) + { + case DSCP_RMK_SRC_INT_PRI: + regData = 0; + break; + case DSCP_RMK_SRC_USER_PRI: + regData = 1; + break; + default: + return RT_ERR_QOS_INT_PRIORITY; + } + + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_RMK_CFG_SEL_CTRL, RTL8367D_RMK_DSCP_CFG_SEL_MASK, regData)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_qos_dscpRemarkSrcSel_get + * Description: + * Get remarking source of DSCP remarking. + * Input: + * none + * Output: + * pType - remarking source + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * RT_ERR_NULL_POINTER - input parameter may be null pointer + + * Note: + * None + */ +rtk_api_ret_t dal_rtl8367d_qos_dscpRemarkSrcSel_get(rtk_qos_dscpRmkSrc_t *pType) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if ((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_RMK_CFG_SEL_CTRL, RTL8367D_RMK_DSCP_CFG_SEL_MASK, ®Data)) != RT_ERR_OK) + return retVal; + + switch (regData) + { + case 0: + *pType = DSCP_RMK_SRC_INT_PRI; + break; + case 1: + *pType = DSCP_RMK_SRC_USER_PRI; + break; + default: + return RT_ERR_FAILED; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_qos_schedulingType_set + * Description: + * Set scheduling type. + * Input: + * type - scheduling type + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + + * Note: + * The API can configure QoS scheduling type. + */ +rtk_api_ret_t dal_rtl8367d_qos_schedulingType_set(rtk_qos_scheduling_type_t type) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (type >= SCHEDULING_TYPE_END ) + return RT_ERR_QOS_SCHE_TYPE; + + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_SCH_WRR_OPT, RTL8367D_CFG_WRR_MODE_OFFSET, type)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_qos_schedulingType_get + * Description: + * Get type of scheduling. + * Input: + * none + * Output: + * pType - scheduling type + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_NULL_POINTER - input parameter may be null pointer + + * Note: + * The API can get QoS scheduling type + */ +rtk_api_ret_t dal_rtl8367d_qos_schedulingType_get(rtk_qos_scheduling_type_t *pType) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_SCH_WRR_OPT, RTL8367D_CFG_WRR_MODE_OFFSET, pType)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_qos_portPriSelIndex_set + * Description: + * Configure priority decision index to each port. + * Input: + * port - Port id. + * index - priority decision index. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENTRY_INDEX - Invalid entry index. + * Note: + * The API can set priority of port assignments for queue usage and packet scheduling. + */ +rtk_api_ret_t dal_rtl8367d_qos_portPriSelIndex_set(rtk_port_t port, rtk_qos_priDecTbl_t index) +{ + rtk_api_ret_t retVal; + rtk_uint32 phy_port; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if (index >= PRIDECTBL_END ) + return RT_ERR_ENTRY_INDEX; + + phy_port = rtk_switch_port_L2P_get(port); + + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_QOS_INTERNAL_PRIORITY_DECISION_IDX, phy_port, index)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_qos_portPriSelIndex_get + * Description: + * Get priority decision index from each port. + * Input: + * port - Port id. + * Output: + * pIndex - priority decision index. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get priority of port assignments for queue usage and packet scheduling. + */ +rtk_api_ret_t dal_rtl8367d_qos_portPriSelIndex_get(rtk_port_t port, rtk_qos_priDecTbl_t *pIndex) +{ + rtk_api_ret_t retVal; + rtk_uint32 phy_port; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + phy_port = rtk_switch_port_L2P_get(port); + + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_QOS_INTERNAL_PRIORITY_DECISION_IDX, phy_port, pIndex)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_qos.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_qos.h new file mode 100644 index 00000000..2dd8ff8a --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_qos.h @@ -0,0 +1,687 @@ + /* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8367/RTL8367D switch high-level API + * + * Feature : The file includes QoS module high-layer API defination + * + */ + +#ifndef __DAL_RTL8367D_QOS_H__ +#define __DAL_RTL8367D_QOS_H__ + +#include + +#define RTL8367D_QTYPE_STRICT 0 +#define RTL8367D_QTYPE_WFQ 1 + +#define RTL8367D_PRIDEC_PORT 0 +#define RTL8367D_PRIDEC_ACL 1 +#define RTL8367D_PRIDEC_DSCP 2 +#define RTL8367D_PRIDEC_1Q 3 +#define RTL8367D_PRIDEC_1AD 4 +#define RTL8367D_PRIDEC_END 5 + + + +/* Function Name: + * dal_rtl8367d_qos_init + * Description: + * Configure Qos default settings with queue number assigment to each port. + * Input: + * queueNum - Queue number of each port. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will initialize related Qos setting with queue number assigment. + * The queue number is from 1 to 8. + */ +extern rtk_api_ret_t dal_rtl8367d_qos_init(rtk_queue_num_t queueNum); + +/* Function Name: + * dal_rtl8367d_qos_priSel_set + * Description: + * Configure the priority order among different priority mechanism. + * Input: + * index - Priority decision table index (0~1) + * pPriDec - Priority assign for port, dscp, 802.1p, cvlan, svlan, acl based priority decision. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_SEL_PRI_SOURCE - Invalid priority decision source parameter. + * Note: + * ASIC will follow user priority setting of mechanisms to select mapped queue priority for receiving frame. + * If two priority mechanisms are the same, the ASIC will chose the highest priority from mechanisms to + * assign queue priority to receiving frame. + * The priority sources are: + * - RTL8367D_PRIDEC_PORT + * - RTL8367D_PRIDEC_ACL + * - RTL8367D_PRIDEC_DSCP + * - RTL8367D_PRIDEC_1Q + * - RTL8367D_PRIDEC_1AD + */ +extern rtk_api_ret_t dal_rtl8367d_qos_priSel_set(rtk_qos_priDecTbl_t index, rtk_priority_select_t *pPriDec); + + +/* Function Name: + * dal_rtl8367d_qos_priSel_get + * Description: + * Get the priority order configuration among different priority mechanism. + * Input: + * index - Priority decision table index (0~1) + * Output: + * pPriDec - Priority assign for port, dscp, 802.1p, cvlan, svlan, acl based priority decision . + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * ASIC will follow user priority setting of mechanisms to select mapped queue priority for receiving frame. + * If two priority mechanisms are the same, the ASIC will chose the highest priority from mechanisms to + * assign queue priority to receiving frame. + * The priority sources are: + * - RTL8367D_PRIDEC_PORT, + * - RTL8367D_PRIDEC_ACL, + * - RTL8367D_PRIDEC_DSCP, + * - RTL8367D_PRIDEC_1Q, + * - RTL8367D_PRIDEC_1AD, + */ +extern rtk_api_ret_t dal_rtl8367d_qos_priSel_get(rtk_qos_priDecTbl_t index, rtk_priority_select_t *pPriDec); + +/* Function Name: + * dal_rtl8367d_qos_1pPriRemap_set + * Description: + * Configure 1Q priorities mapping to internal absolute priority. + * Input: + * dot1p_pri - 802.1p priority value. + * int_pri - internal priority value. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_VLAN_PRIORITY - Invalid 1p priority. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * Priority of 802.1Q assignment for internal asic priority, and it is used for queue usage and packet scheduling. + */ +extern rtk_api_ret_t dal_rtl8367d_qos_1pPriRemap_set(rtk_pri_t dot1p_pri, rtk_pri_t int_pri); + +/* Function Name: + * dal_rtl8367d_qos_1pPriRemap_get + * Description: + * Get 1Q priorities mapping to internal absolute priority. + * Input: + * dot1p_pri - 802.1p priority value . + * Output: + * pInt_pri - internal priority value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_VLAN_PRIORITY - Invalid priority. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * Priority of 802.1Q assigment for internal asic priority, and it is uesed for queue usage and packet scheduling. + */ +extern rtk_api_ret_t dal_rtl8367d_qos_1pPriRemap_get(rtk_pri_t dot1p_pri, rtk_pri_t *pInt_pri); + + +/* Function Name: + * dal_rtl8367d_qos_1pRemarkSrcSel_set + * Description: + * Set remarking source of 802.1p remarking. + * Input: + * type - remarking source + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + + * Note: + * The API can configure 802.1p remark functionality to map original 802.1p value or internal + * priority to TX DSCP value. + */ +extern rtk_api_ret_t dal_rtl8367d_qos_1pRemarkSrcSel_set(rtk_qos_1pRmkSrc_t type); + +/* Function Name: + * dal_rtl8367d_qos_1pRemarkSrcSel_get + * Description: + * Get remarking source of 802.1p remarking. + * Input: + * none + * Output: + * pType - remarking source + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * RT_ERR_NULL_POINTER - input parameter may be null pointer + + * Note: + * None + */ +extern rtk_api_ret_t dal_rtl8367d_qos_1pRemarkSrcSel_get(rtk_qos_1pRmkSrc_t *pType); + +/* Function Name: + * dal_rtl8367d_qos_dscpPriRemap_set + * Description: + * Map dscp value to internal priority. + * Input: + * dscp - Dscp value of receiving frame + * int_pri - internal priority value . + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_QOS_DSCP_VALUE - Invalid DSCP value. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * The Differentiated Service Code Point is a selector for router's per-hop behaviors. As a selector, there is no implication that a numerically + * greater DSCP implies a better network service. As can be seen, the DSCP totally overlaps the old precedence field of TOS. So if values of + * DSCP are carefully chosen then backward compatibility can be achieved. + */ +extern rtk_api_ret_t dal_rtl8367d_qos_dscpPriRemap_set(rtk_dscp_t dscp, rtk_pri_t int_pri); + +/* Function Name: + * dal_rtl8367d_qos_dscpPriRemap_get + * Description: + * Get dscp value to internal priority. + * Input: + * dscp - Dscp value of receiving frame + * Output: + * pInt_pri - internal priority value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_DSCP_VALUE - Invalid DSCP value. + * Note: + * The Differentiated Service Code Point is a selector for router's per-hop behaviors. As a selector, there is no implication that a numerically + * greater DSCP implies a better network service. As can be seen, the DSCP totally overlaps the old precedence field of TOS. So if values of + * DSCP are carefully chosen then backward compatibility can be achieved. + */ +extern rtk_api_ret_t dal_rtl8367d_qos_dscpPriRemap_get(rtk_dscp_t dscp, rtk_pri_t *pInt_pri); + +/* Function Name: + * dal_rtl8367d_qos_portPri_set + * Description: + * Configure priority usage to each port. + * Input: + * port - Port id. + * int_pri - internal priority value. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_QOS_SEL_PORT_PRI - Invalid port priority. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * The API can set priority of port assignments for queue usage and packet scheduling. + */ +extern rtk_api_ret_t dal_rtl8367d_qos_portPri_set(rtk_port_t port, rtk_pri_t int_pri) ; + +/* Function Name: + * dal_rtl8367d_qos_portPri_get + * Description: + * Get priority usage to each port. + * Input: + * port - Port id. + * Output: + * pInt_pri - internal priority value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get priority of port assignments for queue usage and packet scheduling. + */ +extern rtk_api_ret_t dal_rtl8367d_qos_portPri_get(rtk_port_t port, rtk_pri_t *pInt_pri) ; + +/* Function Name: + * dal_rtl8367d_qos_queueNum_set + * Description: + * Set output queue number for each port. + * Input: + * port - Port id. + * index - Mapping queue number (1~8) + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_QUEUE_NUM - Invalid queue number. + * Note: + * The API can set the output queue number of the specified port. The queue number is from 1 to 8. + */ +extern rtk_api_ret_t dal_rtl8367d_qos_queueNum_set(rtk_port_t port, rtk_queue_num_t queue_num); + +/* Function Name: + * dal_rtl8367d_qos_queueNum_get + * Description: + * Get output queue number. + * Input: + * port - Port id. + * Output: + * pQueue_num - Mapping queue number + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API will return the output queue number of the specified port. The queue number is from 1 to 8. + */ +extern rtk_api_ret_t dal_rtl8367d_qos_queueNum_get(rtk_port_t port, rtk_queue_num_t *pQueue_num); + +/* Function Name: + * dal_rtl8367d_qos_priMap_set + * Description: + * Set output queue number for each port. + * Input: + * queue_num - Queue number usage. + * pPri2qid - Priority mapping to queue ID. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_QUEUE_ID - Invalid queue id. + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * ASIC supports priority mapping to queue with different queue number from 1 to 8. + * For different queue numbers usage, ASIC supports different internal available queue IDs. + */ +extern rtk_api_ret_t dal_rtl8367d_qos_priMap_set(rtk_queue_num_t queue_num, rtk_qos_pri2queue_t *pPri2qid); + + +/* Function Name: + * dal_rtl8367d_qos_priMap_get + * Description: + * Get priority to queue ID mapping table parameters. + * Input: + * queue_num - Queue number usage. + * Output: + * pPri2qid - Priority mapping to queue ID. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_QUEUE_NUM - Invalid queue number. + * Note: + * The API can return the mapping queue id of the specified priority and queue number. + * The queue number is from 1 to 8. + */ +extern rtk_api_ret_t dal_rtl8367d_qos_priMap_get(rtk_queue_num_t queue_num, rtk_qos_pri2queue_t *pPri2qid); + +/* Function Name: + * dal_rtl8367d_qos_schedulingQueue_set + * Description: + * Set weight and type of queues in dedicated port. + * Input: + * port - Port id. + * pQweights - The array of weights for WRR/WFQ queue (0 for STRICT_PRIORITY queue). + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_QOS_QUEUE_WEIGHT - Invalid queue weight. + * Note: + * The API can set weight and type, strict priority or weight fair queue (WFQ) for + * dedicated port for using queues. If queue id is not included in queue usage, + * then its type and weight setting in dummy for setting. There are priorities + * as queue id in strict queues. It means strict queue id 5 carrying higher priority + * than strict queue id 4. The WFQ queue weight is from 1 to 128, and weight 0 is + * for strict priority queue type. + */ +extern rtk_api_ret_t dal_rtl8367d_qos_schedulingQueue_set(rtk_port_t port, rtk_qos_queue_weights_t *pQweights); + +/* Function Name: + * dal_rtl8367d_qos_schedulingQueue_get + * Description: + * Get weight and type of queues in dedicated port. + * Input: + * port - Port id. + * Output: + * pQweights - The array of weights for WRR/WFQ queue (0 for STRICT_PRIORITY queue). + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get weight and type, strict priority or weight fair queue (WFQ) for dedicated port for using queues. + * The WFQ queue weight is from 1 to 128, and weight 0 is for strict priority queue type. + */ +extern rtk_api_ret_t dal_rtl8367d_qos_schedulingQueue_get(rtk_port_t port, rtk_qos_queue_weights_t *pQweights); + +/* Function Name: + * dal_rtl8367d_qos_1pRemarkEnable_set + * Description: + * Set 1p Remarking state + * Input: + * port - Port id. + * enable - State of per-port 1p Remarking + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable parameter. + * Note: + * The API can enable or disable 802.1p remarking ability for whole system. + * The status of 802.1p remark: + * - DISABLED + * - ENABLED + */ +extern rtk_api_ret_t dal_rtl8367d_qos_1pRemarkEnable_set(rtk_port_t port, rtk_enable_t enable); + +/* Function Name: + * dal_rtl8367d_qos_1pRemarkEnable_get + * Description: + * Get 802.1p remarking ability. + * Input: + * port - Port id. + * Output: + * pEnable - Status of 802.1p remark. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get 802.1p remarking ability. + * The status of 802.1p remark: + * - DISABLED + * - ENABLED + */ +extern rtk_api_ret_t dal_rtl8367d_qos_1pRemarkEnable_get(rtk_port_t port, rtk_enable_t *pEnable); + +/* Function Name: + * dal_rtl8367d_qos_1pRemark_set + * Description: + * Set 802.1p remarking parameter. + * Input: + * int_pri - Internal priority value. + * dot1p_pri - 802.1p priority value. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_VLAN_PRIORITY - Invalid 1p priority. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * The API can set 802.1p parameters source priority and new priority. + */ +extern rtk_api_ret_t dal_rtl8367d_qos_1pRemark_set(rtk_pri_t int_pri, rtk_pri_t dot1p_pri); + +/* Function Name: + * dal_rtl8367d_qos_1pRemark_get + * Description: + * Get 802.1p remarking parameter. + * Input: + * int_pri - Internal priority value. + * Output: + * pDot1p_pri - 802.1p priority value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * The API can get 802.1p remarking parameters. It would return new priority of ingress priority. + */ +extern rtk_api_ret_t dal_rtl8367d_qos_1pRemark_get(rtk_pri_t int_pri, rtk_pri_t *pDot1p_pri); + +/* Function Name: + * dal_rtl8367d_qos_dscpRemarkEnable_set + * Description: + * Set DSCP remarking ability. + * Input: + * port - Port id. + * enable - status of DSCP remark. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * RT_ERR_ENABLE - Invalid enable parameter. + * Note: + * The API can enable or disable DSCP remarking ability for whole system. + * The status of DSCP remark: + * - DISABLED + * - ENABLED + */ +extern rtk_api_ret_t dal_rtl8367d_qos_dscpRemarkEnable_set(rtk_port_t port, rtk_enable_t enable); + +/* Function Name: + * dal_rtl8367d_qos_dscpRemarkEnable_get + * Description: + * Get DSCP remarking ability. + * Input: + * port - Port id. + * Output: + * pEnable - status of DSCP remarking. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get DSCP remarking ability. + * The status of DSCP remark: + * - DISABLED + * - ENABLED + */ +extern rtk_api_ret_t dal_rtl8367d_qos_dscpRemarkEnable_get(rtk_port_t port, rtk_enable_t *pEnable); + +/* Function Name: + * dal_rtl8367d_qos_dscpRemark_set + * Description: + * Set DSCP remarking parameter. + * Input: + * int_pri - Internal priority value. + * dscp - DSCP value. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * RT_ERR_QOS_DSCP_VALUE - Invalid DSCP value. + * Note: + * The API can set DSCP value and mapping priority. + */ +extern rtk_api_ret_t dal_rtl8367d_qos_dscpRemark_set(rtk_pri_t int_pri, rtk_dscp_t dscp); + +/* Function Name: + * dal_rtl8367d_qos_dscpRemark_get + * Description: + * Get DSCP remarking parameter. + * Input: + * int_pri - Internal priority value. + * Output: + * Dscp - DSCP value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * The API can get DSCP parameters. It would return DSCP value for mapping priority. + */ +extern rtk_api_ret_t dal_rtl8367d_qos_dscpRemark_get(rtk_pri_t int_pri, rtk_dscp_t *pDscp); + +/* Function Name: + * dal_rtl8367d_qos_dscpRemarkSrcSel_set + * Description: + * Set remarking source of DSCP remarking. + * Input: + * type - remarking source + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + + * Note: + * The API can configure DSCP remark functionality to map original DSCP value or internal + * priority to TX DSCP value. + */ +extern rtk_api_ret_t dal_rtl8367d_qos_dscpRemarkSrcSel_set(rtk_qos_dscpRmkSrc_t type); + +/* Function Name: + * dal_rtl8367d_qos_dcpRemarkSrcSel_get + * Description: + * Get remarking source of DSCP remarking. + * Input: + * none + * Output: + * pType - remarking source + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * RT_ERR_NULL_POINTER - input parameter may be null pointer + + * Note: + * None + */ +extern rtk_api_ret_t dal_rtl8367d_qos_dscpRemarkSrcSel_get(rtk_qos_dscpRmkSrc_t *pType); + +/* Function Name: + * dal_rtl8367d_qos_schedulingType_set + * Description: + * Set scheduling type. + * Input: + * type - scheduling type + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + + * Note: + * The API can configure QoS scheduling type. + */ +extern rtk_api_ret_t dal_rtl8367d_qos_schedulingType_set(rtk_qos_scheduling_type_t type); + +/* Function Name: + * dal_rtl8367d_qos_schedulingType_get + * Description: + * Get type of scheduling. + * Input: + * none + * Output: + * pType - scheduling type + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_NULL_POINTER - input parameter may be null pointer + + * Note: + * The API can get QoS scheduling type + */ +extern rtk_api_ret_t dal_rtl8367d_qos_schedulingType_get(rtk_qos_scheduling_type_t *pType); + +/* Function Name: + * dal_rtl8367d_qos_portPriSelIndex_set + * Description: + * Configure priority decision index to each port. + * Input: + * port - Port id. + * index - priority decision index. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENTRY_INDEX - Invalid entry index. + * Note: + * The API can set priority of port assignments for queue usage and packet scheduling. + */ + extern rtk_api_ret_t dal_rtl8367d_qos_portPriSelIndex_set(rtk_port_t port, rtk_qos_priDecTbl_t index); + +/* Function Name: + * dal_rtl8367d_qos_portPriSelIndex_get + * Description: + * Get priority decision index from each port. + * Input: + * port - Port id. + * Output: + * pIndex - priority decision index. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get priority of port assignments for queue usage and packet scheduling. + */ + extern rtk_api_ret_t dal_rtl8367d_qos_portPriSelIndex_get(rtk_port_t port, rtk_qos_priDecTbl_t *pIndex); + +#endif /* __DAL_RTL8367D_QOS_H__*/ diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_rate.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_rate.c new file mode 100644 index 00000000..dea4e239 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_rate.c @@ -0,0 +1,697 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8367C + * Feature : Here is a list of all functions and variables in rate module. + * + */ + +#include +#include +#include +#include + +#define RTL8367D_SCHEDULE_PORT_APR_METER_REG(port, queue) (RTL8367D_REG_SCHEDULE_PORT0_APR_METER_CTRL0 + (port << 2) + (queue / 5)) +#define RTL8367D_SCHEDULE_PORT_APR_METER_MASK(queue) (RTL8367D_SCHEDULE_PORT0_APR_METER_CTRL0_QUEUE0_APR_METER_MASK << (3 * (queue % 5))) + +#define RTL8367D_MAX_NUM_OF_QUEUE (8) + +/* Function Name: + * dal_rtl8367d_rate_shareMeter_set + * Description: + * Set meter configuration + * Input: + * index - shared meter index + * type - shared meter type + * rate - rate of share meter + * ifg_include - include IFG or not, ENABLE:include DISABLE:exclude + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_METER_ID - Invalid meter + * RT_ERR_RATE - Invalid rate + * RT_ERR_INPUT - Invalid input parameters + * Note: + * The API can set shared meter rate and ifg include for each meter. + * The rate unit is 1 kbps and the range is from 8k to 1048568k if type is METER_TYPE_KBPS and + * the granularity of rate is 8 kbps. + * The rate unit is packets per second and the range is 1 ~ 0x7FFFF if type is METER_TYPE_PPS. + * The ifg_include parameter is used + * for rate calculation with/without inter-frame-gap and preamble. + */ +rtk_api_ret_t dal_rtl8367d_rate_shareMeter_set(rtk_meter_id_t index, rtk_meter_type_t type, rtk_rate_t rate, rtk_enable_t ifg_include) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (index > RTK_MAX_METER_ID) + return RT_ERR_FILTER_METER_ID; + + if (type >= METER_TYPE_END) + return RT_ERR_INPUT; + + if (ifg_include >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + switch (type) + { + case METER_TYPE_KBPS: + if (rate > RTL8367D_QOS_RATE_INPUT_MAX_HSG) + return RT_ERR_RATE ; + + if((retVal = rtl8367d_setAsicReg((RTL8367D_REG_METER0_RATE_CTRL0 + (index * 2)), ((rate >> 3) & 0xFFFF))) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367d_setAsicReg((RTL8367D_REG_METER0_RATE_CTRL0 + (index * 2) + 1), ((rate >> 3) & 0x70000) >> 16)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_METER_IFG_CTRL0 + (index / 16), (index % 16), (ifg_include == ENABLED) ? 1 : 0)) != RT_ERR_OK) + return retVal; + + break; + case METER_TYPE_PPS: + if (rate > RTL8367D_QOS_PPS_INPUT_MAX) + return RT_ERR_RATE ; + + if((retVal = rtl8367d_setAsicReg((RTL8367D_REG_METER0_RATE_CTRL0 + (index * 2)), (rate & 0xFFFF))) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367d_setAsicReg((RTL8367D_REG_METER0_RATE_CTRL0 + (index * 2) + 1), (rate & 0x70000) >> 16)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_METER_IFG_CTRL0 + (index / 16), (index % 16), (ifg_include == ENABLED) ? 1 : 0)) != RT_ERR_OK) + return retVal; + + break; + default: + return RT_ERR_INPUT; + } + + /* Set Type */ + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_METER_MODE_SETTING0 + (index / 16), (index % 16), (rtk_uint32)type)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_rate_shareMeter_get + * Description: + * Get meter configuration + * Input: + * index - shared meter index + * Output: + * pType - Meter Type + * pRate - pointer of rate of share meter + * pIfg_include - include IFG or not, ENABLE:include DISABLE:exclude + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_METER_ID - Invalid meter + * Note: + * + */ +rtk_api_ret_t dal_rtl8367d_rate_shareMeter_get(rtk_meter_id_t index, rtk_meter_type_t *pType, rtk_rate_t *pRate, rtk_enable_t *pIfg_include) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData, regData2; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (index > RTK_MAX_METER_ID) + return RT_ERR_FILTER_METER_ID; + + if(NULL == pType) + return RT_ERR_NULL_POINTER; + + if(NULL == pRate) + return RT_ERR_NULL_POINTER; + + if(NULL == pIfg_include) + return RT_ERR_NULL_POINTER; + + /* 19-bits Rate */ + if((retVal = rtl8367d_getAsicReg((RTL8367D_REG_METER0_RATE_CTRL0 + (index * 2)), ®Data)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367d_getAsicReg((RTL8367D_REG_METER0_RATE_CTRL0 + (index * 2) + 1), ®Data2)) != RT_ERR_OK) + return retVal; + + *pRate = ((regData2 << 16) & 0x70000) | regData; + + /* IFG */ + if((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_METER_IFG_CTRL0 + (index / 16), (index % 16), ®Data)) != RT_ERR_OK) + return retVal; + + *pIfg_include = (regData == 1) ? ENABLED : DISABLED; + + /* Type */ + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_METER_MODE_SETTING0 + (index / 16), (index % 16), ®Data)) != RT_ERR_OK) + return retVal; + + *pType = (regData == 0) ? METER_TYPE_KBPS : METER_TYPE_PPS; + + if(*pType == METER_TYPE_KBPS) + *pRate = *pRate << 3; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_rate_shareMeterBucket_set + * Description: + * Set meter Bucket Size + * Input: + * index - shared meter index + * bucket_size - Bucket Size + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_INPUT - Error Input + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_METER_ID - Invalid meter + * Note: + * The API can set shared meter bucket size. + */ +rtk_api_ret_t dal_rtl8367d_rate_shareMeterBucket_set(rtk_meter_id_t index, rtk_uint32 bucket_size) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (index > RTK_MAX_METER_ID) + return RT_ERR_FILTER_METER_ID; + + if(bucket_size > RTL8367D_METERBUCKETSIZEMAX) + return RT_ERR_INPUT; + + if ((retVal = rtl8367d_setAsicReg(RTL8367D_REG_METER0_BUCKET_SIZE + index, bucket_size)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_rate_shareMeterBucket_get + * Description: + * Get meter Bucket Size + * Input: + * index - shared meter index + * Output: + * pBucket_size - Bucket Size + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_METER_ID - Invalid meter + * Note: + * The API can get shared meter bucket size. + */ +rtk_api_ret_t dal_rtl8367d_rate_shareMeterBucket_get(rtk_meter_id_t index, rtk_uint32 *pBucket_size) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (index > RTK_MAX_METER_ID) + return RT_ERR_FILTER_METER_ID; + + if(NULL == pBucket_size) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367d_getAsicReg(RTL8367D_REG_METER0_BUCKET_SIZE + index, pBucket_size)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_rate_igrBandwidthCtrlRate_set + * Description: + * Set port ingress bandwidth control + * Input: + * port - Port id + * rate - Rate of share meter + * ifg_include - include IFG or not, ENABLE:include DISABLE:exclude + * fc_enable - enable flow control or not, ENABLE:use flow control DISABLE:drop + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid IFG parameter. + * RT_ERR_INBW_RATE - Invalid ingress rate parameter. + * Note: + * The rate unit is 1 kbps and the range is from 8k to 1048568k. The granularity of rate is 8 kbps. + * The ifg_include parameter is used for rate calculation with/without inter-frame-gap and preamble. + */ +rtk_api_ret_t dal_rtl8367d_rate_igrBandwidthCtrlRate_set(rtk_port_t port, rtk_rate_t rate, rtk_enable_t ifg_include, rtk_enable_t fc_enable) +{ + rtk_api_ret_t retVal; + rtk_uint32 regAddr, regData; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if(ifg_include >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if(fc_enable >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if(rtk_switch_isHsgPort(port) == RT_ERR_OK) + { + if (rate > RTL8367D_QOS_RATE_INPUT_MAX_HSG) + return RT_ERR_QOS_EBW_RATE ; + } + else + { + if (rate > RTL8367D_QOS_RATE_INPUT_MAX) + return RT_ERR_QOS_EBW_RATE ; + } + + regAddr = RTL8367D_REG_INGRESSBW_PORT0_RATE_CTRL0 + (rtk_switch_port_L2P_get(port) * 0x20); + regData = (rate >> 3) & 0xFFFF; + if((retVal = rtl8367d_setAsicReg(regAddr, regData)) != RT_ERR_OK) + return retVal; + + regAddr += 1; + regData = ((rate >> 3) & 0x70000) >> 16; + if((retVal = rtl8367d_setAsicRegBits(regAddr, RTL8367D_INGRESSBW_PORT0_RATE_CTRL1_INGRESSBW_RATE16_MASK, regData)) != RT_ERR_OK) + return retVal; + + regAddr = RTL8367D_REG_PORT0_MISC_CFG + (rtk_switch_port_L2P_get(port) * 0x20); + if((retVal = rtl8367d_setAsicRegBit(regAddr, RTL8367D_PORT0_MISC_CFG_INGRESSBW_IFG_OFFSET, (ifg_include == ENABLED) ? 1 : 0)) != RT_ERR_OK) + return retVal; + + regAddr = RTL8367D_REG_PORT0_MISC_CFG + (rtk_switch_port_L2P_get(port) * 0x20); + if((retVal = rtl8367d_setAsicRegBit(regAddr, RTL8367D_PORT0_MISC_CFG_INGRESSBW_FLOWCTRL_OFFSET, (fc_enable == ENABLED) ? 1 : 0)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_rate_igrBandwidthCtrlRate_get + * Description: + * Get port ingress bandwidth control + * Input: + * port - Port id + * Output: + * pRate - Rate of share meter + * pIfg_include - Rate's calculation including IFG, ENABLE:include DISABLE:exclude + * pFc_enable - enable flow control or not, ENABLE:use flow control DISABLE:drop + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The rate unit is 1 kbps and the range is from 8k to 1048568k. The granularity of rate is 8 kbps. + * The ifg_include parameter is used for rate calculation with/without inter-frame-gap and preamble. + */ +rtk_api_ret_t dal_rtl8367d_rate_igrBandwidthCtrlRate_get(rtk_port_t port, rtk_rate_t *pRate, rtk_enable_t *pIfg_include, rtk_enable_t *pFc_enable) +{ + rtk_api_ret_t retVal; + rtk_uint32 regAddr, regData; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if(NULL == pIfg_include) + return RT_ERR_NULL_POINTER; + + if(NULL == pFc_enable) + return RT_ERR_NULL_POINTER; + + regAddr = RTL8367D_REG_INGRESSBW_PORT0_RATE_CTRL0 + (rtk_switch_port_L2P_get(port) * 0x20); + if((retVal = rtl8367d_getAsicReg(regAddr, ®Data)) != RT_ERR_OK) + return retVal; + + *pRate = regData; + + regAddr += 1; + if((retVal = rtl8367d_getAsicRegBits(regAddr, RTL8367D_INGRESSBW_PORT0_RATE_CTRL1_INGRESSBW_RATE16_MASK, ®Data)) != RT_ERR_OK) + return retVal; + + *pRate |= (regData << 16); + *pRate = (*pRate << 3); + + regAddr = RTL8367D_REG_PORT0_MISC_CFG + (rtk_switch_port_L2P_get(port) * 0x20); + if((retVal = rtl8367d_getAsicRegBit(regAddr, RTL8367D_PORT0_MISC_CFG_INGRESSBW_IFG_OFFSET, ®Data)) != RT_ERR_OK) + return retVal; + + *pIfg_include = (regData == 1) ? ENABLED : DISABLED; + + regAddr = RTL8367D_REG_PORT0_MISC_CFG + (rtk_switch_port_L2P_get(port) * 0x20); + if((retVal = rtl8367d_getAsicRegBit(regAddr, RTL8367D_PORT0_MISC_CFG_INGRESSBW_FLOWCTRL_OFFSET, ®Data)) != RT_ERR_OK) + return retVal; + + *pFc_enable = (regData == 1) ? ENABLED : DISABLED; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_rate_egrBandwidthCtrlRate_set + * Description: + * Set port egress bandwidth control + * Input: + * port - Port id + * rate - Rate of egress bandwidth + * ifg_include - include IFG or not, ENABLE:include DISABLE:exclude + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_QOS_EBW_RATE - Invalid egress bandwidth/rate + * Note: + * The rate unit is 1 kbps and the range is from 8k to 1048568k. The granularity of rate is 8 kbps. + * The ifg_include parameter is used for rate calculation with/without inter-frame-gap and preamble. + */ +rtk_api_ret_t dal_rtl8367d_rate_egrBandwidthCtrlRate_set( rtk_port_t port, rtk_rate_t rate, rtk_enable_t ifg_include) +{ + rtk_api_ret_t retVal; + rtk_uint32 regAddr, regData; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if(rtk_switch_isHsgPort(port) == RT_ERR_OK) + { + if (rate > RTL8367D_QOS_RATE_INPUT_MAX_HSG) + return RT_ERR_QOS_EBW_RATE ; + } + else + { + if (rate > RTL8367D_QOS_RATE_INPUT_MAX) + return RT_ERR_QOS_EBW_RATE ; + } + + if (ifg_include >= RTK_ENABLE_END) + return RT_ERR_ENABLE; + + regAddr = RTL8367D_REG_PORT0_EGRESSBW_CTRL0 + (rtk_switch_port_L2P_get(port) * 2); + regData = (rate >> 3) & 0xFFFF; + + if((retVal = rtl8367d_setAsicReg(regAddr, regData)) != RT_ERR_OK) + return retVal; + + if(rtk_switch_isHsgPort(port) == RT_ERR_OK) + { + regAddr = RTL8367D_REG_PORT0_EGRESSBW_CTRL1 + (rtk_switch_port_L2P_get(port) * 2); + regData = ((rate >> 3) & 0x70000) >> 16; + + if((retVal = rtl8367d_setAsicRegBits(regAddr, RTL8367D_PORT6_EGRESSBW_CTRL1_MASK, regData)) != RT_ERR_OK) + return retVal; + } + else + { + regAddr = RTL8367D_REG_PORT0_EGRESSBW_CTRL1 + (rtk_switch_port_L2P_get(port) * 2); + regData = ((rate >> 3) & 0x10000) >> 16; + + if((retVal = rtl8367d_setAsicRegBits(regAddr, RTL8367D_PORT0_EGRESSBW_CTRL1_MASK, regData)) != RT_ERR_OK) + return retVal; + } + + if((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_SCHEDULE_WFQ_CTRL, RTL8367D_SCHEDULE_WFQ_CTRL_OFFSET, (ifg_include == ENABLED) ? 1 : 0)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_rate_egrBandwidthCtrlRate_get + * Description: + * Get port egress bandwidth control + * Input: + * port - Port id + * Output: + * pRate - Rate of egress bandwidth + * pIfg_include - Rate's calculation including IFG, ENABLE:include DISABLE:exclude + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The rate unit is 1 kbps and the range is from 8k to 1048568k. The granularity of rate is 8 kbps. + * The ifg_include parameter is used for rate calculation with/without inter-frame-gap and preamble. + */ +rtk_api_ret_t dal_rtl8367d_rate_egrBandwidthCtrlRate_get(rtk_port_t port, rtk_rate_t *pRate, rtk_enable_t *pIfg_include) +{ + rtk_api_ret_t retVal; + rtk_uint32 regAddr, regData, regData2; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if(NULL == pRate) + return RT_ERR_NULL_POINTER; + + if(NULL == pIfg_include) + return RT_ERR_NULL_POINTER; + + regAddr = RTL8367D_REG_PORT0_EGRESSBW_CTRL0 + (rtk_switch_port_L2P_get(port) * 2); + if((retVal = rtl8367d_getAsicReg(regAddr, ®Data)) != RT_ERR_OK) + return retVal; + + regAddr = RTL8367D_REG_PORT0_EGRESSBW_CTRL1 + (rtk_switch_port_L2P_get(port) * 2); + retVal = rtl8367d_getAsicRegBits(regAddr, RTL8367D_PORT6_EGRESSBW_CTRL1_MASK, ®Data2); + if(retVal != RT_ERR_OK) + return retVal; + + *pRate = ((regData | (regData2 << 16)) << 3); + + if((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_SCHEDULE_WFQ_CTRL, RTL8367D_SCHEDULE_WFQ_CTRL_OFFSET, ®Data)) != RT_ERR_OK) + return retVal; + + *pIfg_include = (regData == 1) ? ENABLED : DISABLED; + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_rate_egrQueueBwCtrlEnable_get + * Description: + * Get enable status of egress bandwidth control on specified queue. + * Input: + * unit - unit id + * port - port id + * queue - queue id + * Output: + * pEnable - Pointer to enable status of egress queue bandwidth control + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_QUEUE_ID - invalid queue id + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None + */ +rtk_api_ret_t dal_rtl8367d_rate_egrQueueBwCtrlEnable_get(rtk_port_t port, rtk_qid_t queue, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + rtk_uint32 aprEnable; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + /*for whole port function, the queue value should be 0xFF*/ + if (queue != RTK_WHOLE_SYSTEM) + return RT_ERR_QUEUE_ID; + + if(NULL == pEnable) + return RT_ERR_NULL_POINTER; + + if((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_SCHEDULE_APR_CTRL0, rtk_switch_port_L2P_get(port), &aprEnable)) != RT_ERR_OK) + return retVal; + + *pEnable = (aprEnable == 1) ? ENABLED : DISABLED; + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_rate_egrQueueBwCtrlEnable_set + * Description: + * Set enable status of egress bandwidth control on specified queue. + * Input: + * port - port id + * queue - queue id + * enable - enable status of egress queue bandwidth control + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_QUEUE_ID - invalid queue id + * RT_ERR_INPUT - invalid input parameter + * Note: + * None + */ +rtk_api_ret_t dal_rtl8367d_rate_egrQueueBwCtrlEnable_set(rtk_port_t port, rtk_qid_t queue, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + /*for whole port function, the queue value should be 0xFF*/ + if (queue != RTK_WHOLE_SYSTEM) + return RT_ERR_QUEUE_ID; + + if (enable>=RTK_ENABLE_END) + return RT_ERR_INPUT; + + if((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_SCHEDULE_APR_CTRL0, rtk_switch_port_L2P_get(port), (enable == ENABLED) ? 1 : 0)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_rate_egrQueueBwCtrlRate_get + * Description: + * Get rate of egress bandwidth control on specified queue. + * Input: + * port - port id + * queue - queue id + * pIndex - shared meter index + * Output: + * pRate - pointer to rate of egress queue bandwidth control + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_QUEUE_ID - invalid queue id + * RT_ERR_FILTER_METER_ID - Invalid meter id + * Note: + * The actual rate control is set in shared meters. + * The unit of granularity is 8Kbps. + */ +rtk_api_ret_t dal_rtl8367d_rate_egrQueueBwCtrlRate_get(rtk_port_t port, rtk_qid_t queue, rtk_meter_id_t *pIndex) +{ + rtk_api_ret_t retVal; + rtk_uint32 apridx; + rtk_uint32 phy_port; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if (queue >= RTL8367D_MAX_NUM_OF_QUEUE) + return RT_ERR_QUEUE_ID; + + if(NULL == pIndex) + return RT_ERR_NULL_POINTER; + + phy_port = rtk_switch_port_L2P_get(port); + if((retVal = rtl8367d_getAsicRegBits(RTL8367D_SCHEDULE_PORT_APR_METER_REG(phy_port, queue), RTL8367D_SCHEDULE_PORT_APR_METER_MASK(phy_port), &apridx)) != RT_ERR_OK) + return retVal; + + *pIndex = apridx + ((rtk_switch_port_L2P_get(port) % 4) * 8); + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_rate_egrQueueBwCtrlRate_set + * Description: + * Set rate of egress bandwidth control on specified queue. + * Input: + * port - port id + * queue - queue id + * index - shared meter index + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_QUEUE_ID - invalid queue id + * RT_ERR_FILTER_METER_ID - Invalid meter id + * Note: + * The actual rate control is set in shared meters. + * The unit of granularity is 8Kbps. + */ +rtk_api_ret_t dal_rtl8367d_rate_egrQueueBwCtrlRate_set(rtk_port_t port, rtk_qid_t queue, rtk_meter_id_t index) +{ + rtk_api_ret_t retVal; + rtk_uint32 offset_idx; + rtk_uint32 phy_port; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if (queue >= RTL8367D_MAX_NUM_OF_QUEUE) + return RT_ERR_QUEUE_ID; + + if (index > RTK_MAX_METER_ID) + return RT_ERR_FILTER_METER_ID; + + phy_port = rtk_switch_port_L2P_get(port); + if (index < ((phy_port % 4) * 8) || index > (7 + ((phy_port % 4) * 8))) + return RT_ERR_FILTER_METER_ID; + + offset_idx = index - ((phy_port % 4) * 8); + + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_SCHEDULE_PORT_APR_METER_REG(phy_port, queue), RTL8367D_SCHEDULE_PORT_APR_METER_MASK(queue), offset_idx))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_rate.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_rate.h new file mode 100644 index 00000000..a1b879ad --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_rate.h @@ -0,0 +1,299 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8367/RTL8367D switch high-level API + * + * Feature : The file includes rate module high-layer API defination + * + */ + +#ifndef __DAL_RTL8367D_RATE_H__ +#define __DAL_RTL8367D_RATE_H__ + +/* + * Include Files + */ +#include + +/* + * Data Type Declaration + */ +#define RTL8367D_METERBUCKETSIZEMAX 0xFFFF + +/* + * Function Declaration + */ + + /* Rate */ +/* Function Name: + * dal_rtl8367d_rate_shareMeter_set + * Description: + * Set meter configuration + * Input: + * index - shared meter index + * type - shared meter type + * rate - rate of share meter + * ifg_include - include IFG or not, ENABLE:include DISABLE:exclude + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_METER_ID - Invalid meter + * RT_ERR_RATE - Invalid rate + * RT_ERR_INPUT - Invalid input parameters + * Note: + * The API can set shared meter rate and ifg include for each meter. + * The rate unit is 1 kbps and the range is from 8k to 1048568k if type is METER_TYPE_KBPS and + * the granularity of rate is 8 kbps. + * The rate unit is packets per second and the range is 1 ~ 0x7FFFF if type is METER_TYPE_PPS. + * The ifg_include parameter is used + * for rate calculation with/without inter-frame-gap and preamble. + */ +extern rtk_api_ret_t dal_rtl8367d_rate_shareMeter_set(rtk_meter_id_t index, rtk_meter_type_t type, rtk_rate_t rate, rtk_enable_t ifg_include); + +/* Function Name: + * dal_rtl8367d_rate_shareMeter_get + * Description: + * Get meter configuration + * Input: + * index - shared meter index + * Output: + * pType - Meter Type + * pRate - pointer of rate of share meter + * pIfg_include - include IFG or not, ENABLE:include DISABLE:exclude + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_METER_ID - Invalid meter + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367d_rate_shareMeter_get(rtk_meter_id_t index, rtk_meter_type_t *pType, rtk_rate_t *pRate, rtk_enable_t *pIfg_include); + +/* Function Name: + * dal_rtl8367d_rate_shareMeterBucket_set + * Description: + * Set meter Bucket Size + * Input: + * index - shared meter index + * bucket_size - Bucket Size + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_INPUT - Error Input + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_METER_ID - Invalid meter + * Note: + * The API can set shared meter bucket size. + */ +extern rtk_api_ret_t dal_rtl8367d_rate_shareMeterBucket_set(rtk_meter_id_t index, rtk_uint32 bucket_size); + +/* Function Name: + * dal_rtl8367d_rate_shareMeterBucket_get + * Description: + * Get meter Bucket Size + * Input: + * index - shared meter index + * Output: + * pBucket_size - Bucket Size + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_METER_ID - Invalid meter + * Note: + * The API can get shared meter bucket size. + */ +extern rtk_api_ret_t dal_rtl8367d_rate_shareMeterBucket_get(rtk_meter_id_t index, rtk_uint32 *pBucket_size); + +/* Function Name: + * dal_rtl8367d_rate_igrBandwidthCtrlRate_set + * Description: + * Set port ingress bandwidth control + * Input: + * port - Port id + * rate - Rate of share meter + * ifg_include - include IFG or not, ENABLE:include DISABLE:exclude + * fc_enable - enable flow control or not, ENABLE:use flow control DISABLE:drop + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid IFG parameter. + * RT_ERR_INBW_RATE - Invalid ingress rate parameter. + * Note: + * The rate unit is 1 kbps and the range is from 8k to 1048568k. The granularity of rate is 8 kbps. + * The ifg_include parameter is used for rate calculation with/without inter-frame-gap and preamble. + */ +extern rtk_api_ret_t dal_rtl8367d_rate_igrBandwidthCtrlRate_set( rtk_port_t port, rtk_rate_t rate, rtk_enable_t ifg_include, rtk_enable_t fc_enable); + +/* Function Name: + * dal_rtl8367d_rate_igrBandwidthCtrlRate_get + * Description: + * Get port ingress bandwidth control + * Input: + * port - Port id + * Output: + * pRate - Rate of share meter + * pIfg_include - Rate's calculation including IFG, ENABLE:include DISABLE:exclude + * pFc_enable - enable flow control or not, ENABLE:use flow control DISABLE:drop + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The rate unit is 1 kbps and the range is from 8k to 1048568k. The granularity of rate is 8 kbps. + * The ifg_include parameter is used for rate calculation with/without inter-frame-gap and preamble. + */ +extern rtk_api_ret_t dal_rtl8367d_rate_igrBandwidthCtrlRate_get(rtk_port_t port, rtk_rate_t *pRate, rtk_enable_t *pIfg_include, rtk_enable_t *pFc_enable); + +/* Function Name: + * dal_rtl8367d_rate_egrBandwidthCtrlRate_set + * Description: + * Set port egress bandwidth control + * Input: + * port - Port id + * rate - Rate of egress bandwidth + * ifg_include - include IFG or not, ENABLE:include DISABLE:exclude + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_QOS_EBW_RATE - Invalid egress bandwidth/rate + * Note: + * The rate unit is 1 kbps and the range is from 8k to 1048568k. The granularity of rate is 8 kbps. + * The ifg_include parameter is used for rate calculation with/without inter-frame-gap and preamble. + */ +extern rtk_api_ret_t dal_rtl8367d_rate_egrBandwidthCtrlRate_set(rtk_port_t port, rtk_rate_t rate, rtk_enable_t ifg_includ); + +/* Function Name: + * dal_rtl8367d_rate_egrBandwidthCtrlRate_get + * Description: + * Get port egress bandwidth control + * Input: + * port - Port id + * Output: + * pRate - Rate of egress bandwidth + * pIfg_include - Rate's calculation including IFG, ENABLE:include DISABLE:exclude + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The rate unit is 1 kbps and the range is from 8k to 1048568k. The granularity of rate is 8 kbps. + * The ifg_include parameter is used for rate calculation with/without inter-frame-gap and preamble. + */ +extern rtk_api_ret_t dal_rtl8367d_rate_egrBandwidthCtrlRate_get(rtk_port_t port, rtk_rate_t *pRate, rtk_enable_t *pIfg_include); + +/* Function Name: + * dal_rtl8367d_rate_egrQueueBwCtrlEnable_set + * Description: + * Set enable status of egress bandwidth control on specified queue. + * Input: + * port - port id + * queue - queue id + * enable - enable status of egress queue bandwidth control + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_QUEUE_ID - invalid queue id + * RT_ERR_INPUT - invalid input parameter + * Note: + * None + */ +extern rtk_api_ret_t dal_rtl8367d_rate_egrQueueBwCtrlEnable_set(rtk_port_t port, rtk_qid_t queue, rtk_enable_t enable); + +/* Function Name: + * dal_rtl8367d_rate_egrQueueBwCtrlRate_get + * Description: + * Get rate of egress bandwidth control on specified queue. + * Input: + * port - port id + * queue - queue id + * pIndex - shared meter index + * Output: + * pRate - pointer to rate of egress queue bandwidth control + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_QUEUE_ID - invalid queue id + * RT_ERR_FILTER_METER_ID - Invalid meter id + * Note: + * None. + */ +extern rtk_api_ret_t dal_rtl8367d_rate_egrQueueBwCtrlEnable_get(rtk_port_t port, rtk_qid_t queue, rtk_enable_t *pEnable); + +/* Function Name: + * dal_rtl8367d_rate_egrQueueBwCtrlRate_set + * Description: + * Set rate of egress bandwidth control on specified queue. + * Input: + * port - port id + * queue - queue id + * index - shared meter index + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_QUEUE_ID - invalid queue id + * RT_ERR_FILTER_METER_ID - Invalid meter id + * Note: + * The actual rate control is set in shared meters. + * The unit of granularity is 8Kbps. + */ +extern rtk_api_ret_t dal_rtl8367d_rate_egrQueueBwCtrlRate_set(rtk_port_t port, rtk_qid_t queue, rtk_meter_id_t index); + +/* Function Name: + * dal_rtl8367d_rate_egrQueueBwCtrlRate_get + * Description: + * Get rate of egress bandwidth control on specified queue. + * Input: + * port - port id + * queue - queue id + * pIndex - shared meter index + * Output: + * pRate - pointer to rate of egress queue bandwidth control + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_QUEUE_ID - invalid queue id + * RT_ERR_FILTER_METER_ID - Invalid meter id + * Note: + * The actual rate control is set in shared meters. + * The unit of granularity is 8Kbps. + */ +extern rtk_api_ret_t dal_rtl8367d_rate_egrQueueBwCtrlRate_get(rtk_port_t port, rtk_qid_t queue, rtk_meter_id_t *pIndex); + +#endif /* __DAL_RTL8367D_RATE_H__ */ + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_rldp.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_rldp.c new file mode 100644 index 00000000..84857366 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_rldp.c @@ -0,0 +1,479 @@ +/* + * Copyright (C) 2012 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision: $ + * $Date: $ + * + * Purpose : Declaration of RLDP and RLPP API + * + * Feature : The file have include the following module and sub-modules + * 1) RLDP and RLPP configuration and status + * + */ + + +/* + * Include Files + */ +#include +#include +#include +#include + + +/* Function Name: + * dal_rtl8367d_rldp_config_set + * Description: + * Set RLDP module configuration + * Input: + * pConfig - configuration structure of RLDP + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT + * RT_ERR_NULL_POINTER + * Note: + * None + */ +rtk_api_ret_t dal_rtl8367d_rldp_config_set(rtk_rldp_config_t *pConfig) +{ + rtk_api_ret_t retVal; + rtk_uint16 *magic; + rtk_uint32 regData, i; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (pConfig->rldp_enable >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if (pConfig->trigger_mode >= RTK_RLDP_TRIGGER_END) + return RT_ERR_INPUT; + + if (pConfig->compare_type >= RTK_RLDP_CMPTYPE_END) + return RT_ERR_INPUT; + + if (pConfig->num_check >= RTK_RLDP_NUM_MAX) + return RT_ERR_INPUT; + + if (pConfig->interval_check >= RTK_RLDP_INTERVAL_MAX) + return RT_ERR_INPUT; + + if (pConfig->num_loop >= RTK_RLDP_NUM_MAX) + return RT_ERR_INPUT; + + if (pConfig->interval_loop >= RTK_RLDP_INTERVAL_MAX) + return RT_ERR_INPUT; + + + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_RLDP_CTRL0, RTL8367D_RLDP_ENABLE_OFFSET, pConfig->rldp_enable))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_RLDP_CTRL0, RTL8367D_RLDP_TRIGGER_MODE_OFFSET, pConfig->trigger_mode))!=RT_ERR_OK) + return retVal; + + magic = (rtk_uint16*)&pConfig->magic; + for (i = 0; i < 3; i++) + { + regData = *magic; + retVal = rtl8367d_setAsicReg(RTL8367D_REG_RLDP_MAGIC_NUM0 + i, regData); + if(retVal != RT_ERR_OK) + return retVal; + + magic++; + } + + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_RLDP_CTRL0, RTL8367D_RLDP_COMP_ID_OFFSET, pConfig->compare_type))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_RLDP_CTRL1, RTL8367D_RLDP_RETRY_COUNT_CHKSTATE_MASK, pConfig->num_check))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicReg(RTL8367D_REG_RLDP_CTRL3, pConfig->interval_check))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_RLDP_CTRL1, RTL8367D_RLDP_RETRY_COUNT_LOOPSTATE_MASK, pConfig->num_loop))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicReg(RTL8367D_REG_RLDP_CTRL2, pConfig->interval_loop))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_rldp_config_get + * Description: + * Get RLDP module configuration + * Input: + * None + * Output: + * pConfig - configuration structure of RLDP + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT + * RT_ERR_NULL_POINTER + * Note: + * None + */ +rtk_api_ret_t dal_rtl8367d_rldp_config_get(rtk_rldp_config_t *pConfig) +{ + rtk_api_ret_t retVal; + rtk_uint16 *magic; + rtk_uint32 regData, i; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_RLDP_CTRL0, RTL8367D_RLDP_ENABLE_OFFSET, &pConfig->rldp_enable))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_RLDP_CTRL0, RTL8367D_RLDP_TRIGGER_MODE_OFFSET, &pConfig->trigger_mode))!=RT_ERR_OK) + return retVal; + + magic = (rtk_uint16*)&pConfig->magic; + for (i = 0; i < 3; i++) + { + retVal = rtl8367d_getAsicReg(RTL8367D_REG_RLDP_MAGIC_NUM0 + i, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + *magic = regData; + magic++; + } + + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_RLDP_CTRL0, RTL8367D_RLDP_COMP_ID_OFFSET, &pConfig->compare_type))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_RLDP_CTRL1, RTL8367D_RLDP_RETRY_COUNT_CHKSTATE_MASK, &pConfig->num_check))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_getAsicReg(RTL8367D_REG_RLDP_CTRL3, &pConfig->interval_check))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_RLDP_CTRL1, RTL8367D_RLDP_RETRY_COUNT_LOOPSTATE_MASK, &pConfig->num_loop))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_getAsicReg(RTL8367D_REG_RLDP_CTRL2, &pConfig->interval_loop))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8367d_rldp_portConfig_set + * Description: + * Set per port RLDP module configuration + * Input: + * port - port number to be configured + * pPortConfig - per port configuration structure of RLDP + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT + * RT_ERR_NULL_POINTER + * Note: + * None + */ +rtk_api_ret_t dal_rtl8367d_rldp_portConfig_set(rtk_port_t port, rtk_rldp_portConfig_t *pPortConfig) +{ + rtk_api_ret_t retVal; + rtk_uint32 portmask; + rtk_uint32 phy_port; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if (pPortConfig->tx_enable>= RTK_ENABLE_END) + return RT_ERR_INPUT; + + phy_port = rtk_switch_port_L2P_get(port); + if (phy_port == UNDEFINE_PHY_PORT) + return RT_ERR_PORT_ID; + + if ((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_RLDP_CTRL4, RTL8367D_RLDP_CTRL4_MASK, &portmask))!=RT_ERR_OK) + return retVal; + + if (pPortConfig->tx_enable) + { + portmask |=(1<tx_enable = ENABLED; + } + else + { + pPortConfig->tx_enable = DISABLED; + } + + return RT_ERR_OK; +} + + + +/* Function Name: + * dal_rtl8367d_rldp_status_get + * Description: + * Get RLDP module status + * Input: + * None + * Output: + * pStatus - status structure of RLDP + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NULL_POINTER + * Note: + * None + */ +rtk_api_ret_t dal_rtl8367d_rldp_status_get(rtk_rldp_status_t *pStatus) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + rtk_uint16 *accessPtr; + rtk_uint32 i; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + accessPtr = (rtk_uint16*)&pStatus->id; + for(i = 0; i < 3; i++) + { + retVal = rtl8367d_getAsicReg(RTL8367D_REG_RLDP_RAND_NUM0+ i, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + *accessPtr = regData; + accessPtr++; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_rldp_portStatus_get + * Description: + * Get RLDP module status + * Input: + * port - port number to be get + * Output: + * pPortStatus - per port status structure of RLDP + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT + * RT_ERR_NULL_POINTER + * Note: + * None + */ +rtk_api_ret_t dal_rtl8367d_rldp_portStatus_get(rtk_port_t port, rtk_rldp_portStatus_t *pPortStatus) +{ + rtk_api_ret_t retVal; + rtk_uint32 portmask; + rtk_portmask_t logicalPmask; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if ((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_RLDP_LOOPSTATUS_INDICATOR, RTL8367D_RLDP_LOOPSTATUS_INDICATOR_MASK, &portmask))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtk_switch_portmask_P2L_get(portmask, &logicalPmask)) != RT_ERR_OK) + return retVal; + + if (logicalPmask.bits[0] & (1<loop_status = RTK_RLDP_LOOPSTS_LOOPING; + } + else + { + pPortStatus->loop_status = RTK_RLDP_LOOPSTS_NONE; + } + + if ((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_RLDP_LOOPED_INDICATOR, RTL8367D_RLDP_LOOPED_INDICATOR_MASK, &portmask))!=RT_ERR_OK) + return retVal; + if ((retVal = rtk_switch_portmask_P2L_get(portmask, &logicalPmask)) != RT_ERR_OK) + return retVal; + + if (logicalPmask.bits[0] & (1<loop_enter = RTK_RLDP_LOOPSTS_LOOPING; + } + else + { + pPortStatus->loop_enter = RTK_RLDP_LOOPSTS_NONE; + } + + if ((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_RLDP_RELEASED_INDICATOR, RTL8367D_RLDP_RELEASED_INDICATOR_MASK, &portmask))!=RT_ERR_OK) + return retVal; + if ((retVal = rtk_switch_portmask_P2L_get(portmask, &logicalPmask)) != RT_ERR_OK) + return retVal; + + if (logicalPmask.bits[0] & (1<loop_leave = RTK_RLDP_LOOPSTS_LOOPING; + } + else + { + pPortStatus->loop_leave = RTK_RLDP_LOOPSTS_NONE; + } + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8367d_rldp_portStatus_clear + * Description: + * Clear RLDP module status + * Input: + * port - port number to be clear + * pPortStatus - per port status structure of RLDP + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT + * RT_ERR_NULL_POINTER + * Note: + * Clear operation effect loop_enter and loop_leave only, other field in + * the structure are don't care + */ +rtk_api_ret_t dal_rtl8367d_rldp_portStatus_set(rtk_port_t port, rtk_rldp_portStatus_t *pPortStatus) +{ + rtk_api_ret_t retVal; + rtk_uint32 pmsk; + rtk_uint32 phyPort; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + phyPort = rtk_switch_port_L2P_get(port); + if (phyPort == UNDEFINE_PHY_PORT) + return RT_ERR_PORT_ID; + + pmsk = (pPortStatus->loop_enter) << phyPort; + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_RLDP_LOOPED_INDICATOR, RTL8367D_RLDP_LOOPED_INDICATOR_MASK, pmsk))!=RT_ERR_OK) + return retVal; + pmsk = (pPortStatus->loop_leave) << phyPort; + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_RLDP_RELEASED_INDICATOR, RTL8367D_RLDP_RELEASED_INDICATOR_MASK, pmsk))!=RT_ERR_OK) + return retVal; + + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8367d_rldp_portLoopPair_get + * Description: + * Get RLDP port loop pairs + * Input: + * port - port number to be get + * Output: + * pPortmask - per port related loop ports + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT + * RT_ERR_NULL_POINTER + * Note: + * None + */ +rtk_api_ret_t dal_rtl8367d_rldp_portLoopPair_get(rtk_port_t port, rtk_portmask_t *pPortmask) +{ + rtk_api_ret_t retVal; + rtk_uint32 pmsk; + rtk_uint32 phy_port; + rtk_uint32 loopedPair; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + phy_port = rtk_switch_port_L2P_get(port); + + if ((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_RLDP_LOOP_PORT_REG0 + (phy_port>>1), RTL8367D_RLDP_LOOP_PORT_00_MASK<<((phy_port&1)<<3), &loopedPair))!=RT_ERR_OK) + return retVal; + + pmsk = 1 << loopedPair; + if ((retVal = rtk_switch_portmask_P2L_get(pmsk, pPortmask)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_rldp.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_rldp.h new file mode 100644 index 00000000..9ea1ab0e --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_rldp.h @@ -0,0 +1,194 @@ +/* + * Copyright (C) 2012 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision: $ + * $Date: $ + * + * Purpose : Declaration of RLDP and RLPP API + * + * Feature : The file have include the following module and sub-modules + * 1) RLDP and RLPP configuration and status + * + */ + + +#ifndef __DAL_RTL8367D_RLDP_H__ +#define __DAL_RTL8367D_RLDP_H__ + + +/* + * Include Files + */ + +#include + +/* + * Function Declaration + */ + +/* Module Name : RLDP */ + + +/* Function Name: + * dal_rtl8367d_rldp_config_set + * Description: + * Set RLDP module configuration + * Input: + * pConfig - configuration structure of RLDP + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT + * RT_ERR_NULL_POINTER + * Note: + * None + */ +extern rtk_api_ret_t dal_rtl8367d_rldp_config_set(rtk_rldp_config_t *pConfig); + + +/* Function Name: + * dal_rtl8367d_rldp_config_get + * Description: + * Get RLDP module configuration + * Input: + * None + * Output: + * pConfig - configuration structure of RLDP + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT + * RT_ERR_NULL_POINTER + * Note: + * None + */ +extern rtk_api_ret_t dal_rtl8367d_rldp_config_get(rtk_rldp_config_t *pConfig); + + +/* Function Name: + * dal_rtl8367d_rldp_portConfig_set + * Description: + * Set per port RLDP module configuration + * Input: + * port - port number to be configured + * pPortConfig - per port configuration structure of RLDP + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT + * RT_ERR_NULL_POINTER + * Note: + * None + */ +extern rtk_api_ret_t dal_rtl8367d_rldp_portConfig_set(rtk_port_t port, rtk_rldp_portConfig_t *pPortConfig); + + +/* Function Name: + * dal_rtl8367d_rldp_portConfig_get + * Description: + * Get per port RLDP module configuration + * Input: + * port - port number to be get + * Output: + * pPortConfig - per port configuration structure of RLDP + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT + * RT_ERR_NULL_POINTER + * Note: + * None + */ +extern rtk_api_ret_t dal_rtl8367d_rldp_portConfig_get(rtk_port_t port, rtk_rldp_portConfig_t *pPortConfig); + + +/* Function Name: + * dal_rtl8367d_rldp_status_get + * Description: + * Get RLDP module status + * Input: + * None + * Output: + * pStatus - status structure of RLDP + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NULL_POINTER + * Note: + * None + */ +extern rtk_api_ret_t dal_rtl8367d_rldp_status_get(rtk_rldp_status_t *pStatus); + + +/* Function Name: + * dal_rtl8367d_rldp_portStatus_get + * Description: + * Get RLDP module status + * Input: + * port - port number to be get + * Output: + * pPortStatus - per port status structure of RLDP + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT + * RT_ERR_NULL_POINTER + * Note: + * None + */ +extern rtk_api_ret_t dal_rtl8367d_rldp_portStatus_get(rtk_port_t port, rtk_rldp_portStatus_t *pPortStatus); + + +/* Function Name: + * dal_rtl8367d_rldp_portStatus_clear + * Description: + * Clear RLDP module status + * Input: + * port - port number to be clear + * pPortStatus - per port status structure of RLDP + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT + * RT_ERR_NULL_POINTER + * Note: + * Clear operation effect loop_enter and loop_leave only, other field in + * the structure are don't care + */ +extern rtk_api_ret_t dal_rtl8367d_rldp_portStatus_set(rtk_port_t port, rtk_rldp_portStatus_t *pPortStatus); + + +/* Function Name: + * dal_rtl8367d_rldp_portLoopPair_get + * Description: + * Get RLDP port loop pairs + * Input: + * port - port number to be get + * Output: + * pPortmask - per port related loop ports + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT + * RT_ERR_NULL_POINTER + * Note: + * None + */ +extern rtk_api_ret_t dal_rtl8367d_rldp_portLoopPair_get(rtk_port_t port, rtk_portmask_t *pPortmask); + +#endif /* __DAL_RTL8367D_RLDP_H__ */ + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_stat.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_stat.c new file mode 100644 index 00000000..5d0351aa --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_stat.c @@ -0,0 +1,889 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8367D + * Feature : Here is a list of all functions and variables in MIB module. + * + */ + +#include +#include +#include + +#include + +#include + +#define MIB_NOT_SUPPORT (0xFFFF) +static rtk_api_ret_t _get_asic_mib_idx(rtk_stat_port_type_t cnt_idx, RTL8367D_MIBCOUNTER *pMib_idx) +{ + RTL8367D_MIBCOUNTER mib_asic_idx[STAT_PORT_CNTR_END]= + { + ifInOctets, /* STAT_IfInOctets */ + dot3StatsFCSErrors, /* STAT_Dot3StatsFCSErrors */ + dot3StatsSymbolErrors, /* STAT_Dot3StatsSymbolErrors */ + dot3InPauseFrames, /* STAT_Dot3InPauseFrames */ + dot3ControlInUnknownOpcodes, /* STAT_Dot3ControlInUnknownOpcodes */ + etherStatsFragments, /* STAT_EtherStatsFragments */ + etherStatsJabbers, /* STAT_EtherStatsJabbers */ + ifInUcastPkts, /* STAT_IfInUcastPkts */ + etherStatsDropEvents, /* STAT_EtherStatsDropEvents */ + etherStatsOctets, /* STAT_EtherStatsOctets */ + etherStatsUnderSizePkts, /* STAT_EtherStatsUnderSizePkts */ + etherOversizeStats, /* STAT_EtherOversizeStats */ + etherStatsPkts64Octets, /* STAT_EtherStatsPkts64Octets */ + etherStatsPkts65to127Octets, /* STAT_EtherStatsPkts65to127Octets */ + etherStatsPkts128to255Octets, /* STAT_EtherStatsPkts128to255Octets */ + etherStatsPkts256to511Octets, /* STAT_EtherStatsPkts256to511Octets */ + etherStatsPkts512to1023Octets, /* STAT_EtherStatsPkts512to1023Octets */ + etherStatsPkts1024to1518Octets, /* STAT_EtherStatsPkts1024to1518Octets */ + ifInMulticastPkts, /* STAT_EtherStatsMulticastPkts */ + ifInBroadcastPkts, /* STAT_EtherStatsBroadcastPkts */ + ifOutOctets, /* STAT_IfOutOctets */ + dot3StatsSingleCollisionFrames, /* STAT_Dot3StatsSingleCollisionFrames */ + dot3StatMultipleCollisionFrames,/* STAT_Dot3StatsMultipleCollisionFrames */ + dot3sDeferredTransmissions, /* STAT_Dot3StatsDeferredTransmissions */ + dot3StatsLateCollisions, /* STAT_Dot3StatsLateCollisions */ + etherStatsCollisions, /* STAT_EtherStatsCollisions */ + dot3StatsExcessiveCollisions, /* STAT_Dot3StatsExcessiveCollisions */ + dot3OutPauseFrames, /* STAT_Dot3OutPauseFrames */ + MIB_NOT_SUPPORT, /* STAT_Dot1dBasePortDelayExceededDiscards */ + dot1dTpPortInDiscards, /* STAT_Dot1dTpPortInDiscards */ + ifOutUcastPkts, /* STAT_IfOutUcastPkts */ + ifOutMulticastPkts, /* STAT_IfOutMulticastPkts */ + ifOutBroadcastPkts, /* STAT_IfOutBroadcastPkts */ + outOampduPkts, /* STAT_OutOampduPkts */ + inOampduPkts, /* STAT_InOampduPkts */ + MIB_NOT_SUPPORT, /* STAT_PktgenPkts */ + inMldChecksumError, /* STAT_InMldChecksumError */ + inIgmpChecksumError, /* STAT_InIgmpChecksumError */ + inMldSpecificQuery, /* STAT_InMldSpecificQuery */ + inMldGeneralQuery, /* STAT_InMldGeneralQuery */ + inIgmpSpecificQuery, /* STAT_InIgmpSpecificQuery */ + inIgmpGeneralQuery, /* STAT_InIgmpGeneralQuery */ + inMldLeaves, /* STAT_InMldLeaves */ + inIgmpLeaves, /* STAT_InIgmpInterfaceLeaves */ + inIgmpJoinsSuccess, /* STAT_InIgmpJoinsSuccess */ + inIgmpJoinsFail, /* STAT_InIgmpJoinsFail */ + inMldJoinsSuccess, /* STAT_InMldJoinsSuccess */ + inMldJoinsFail, /* STAT_InMldJoinsFail */ + inReportSuppressionDrop, /* STAT_InReportSuppressionDrop */ + inLeaveSuppressionDrop, /* STAT_InLeaveSuppressionDrop */ + outIgmpReports, /* STAT_OutIgmpReports */ + outIgmpLeaves, /* STAT_OutIgmpLeaves */ + outIgmpGeneralQuery, /* STAT_OutIgmpGeneralQuery */ + outIgmpSpecificQuery, /* STAT_OutIgmpSpecificQuery */ + outMldReports, /* STAT_OutMldReports */ + outMldLeaves, /* STAT_OutMldLeaves */ + outMldGeneralQuery, /* STAT_OutMldGeneralQuery */ + outMldSpecificQuery, /* STAT_OutMldSpecificQuery */ + inKnownMulticastPkts, /* STAT_InKnownMulticastPkts */ + ifInMulticastPkts, /* STAT_IfInMulticastPkts */ + ifInBroadcastPkts, /* STAT_IfInBroadcastPkts */ + ifOutDiscards /* STAT_IfOutDiscards */ + }; + + if(cnt_idx >= STAT_PORT_CNTR_END) + return RT_ERR_STAT_INVALID_PORT_CNTR; + + if(mib_asic_idx[cnt_idx] == MIB_NOT_SUPPORT) + return RT_ERR_CHIP_NOT_SUPPORTED; + + *pMib_idx = mib_asic_idx[cnt_idx]; + return RT_ERR_OK; +} + +static rtk_api_ret_t _rtl8367d_getMIBsCounter(rtk_uint32 port, RTL8367D_MIBCOUNTER mibIdx, rtk_uint64* pCounter) +{ + ret_t retVal; + rtk_uint32 regAddr; + rtk_uint32 regData; + rtk_uint32 mibAddr; + rtk_uint32 mibOff=0; + + /* address offset to MIBs counter */ + CONST rtk_uint16 mibLength[RTL8367D_MIBS_NUMBER]= { + 4,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2, + 4,2,2,2,2,2,2,2,2, + 4,2,2,2,2,2,2,2,2,2,2,2,2,2,2, + 2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2}; + + rtk_uint16 i; + rtk_uint64 mibCounter; + + + if(port > RTL8367D_PORTIDMAX) + return RT_ERR_PORT_ID; + + if(mibIdx >= RTL8367D_MIBS_NUMBER) + return RT_ERR_STAT_INVALID_CNTR; + + if(dot1dTpLearnedEntryDiscards == mibIdx) + { + mibAddr = RTL8367D_MIB_LEARNENTRYDISCARD_OFFSET; + } + else + { + i = 0; + mibOff = RTL8367D_MIB_PORT_OFFSET * port; + + if(port > 7) + mibOff = mibOff + 68; + + while(i < mibIdx) + { + mibOff += mibLength[i]; + i++; + } + + mibAddr = mibOff; + } + + /* Read MIB addr before writing */ + retVal = rtl8367d_getAsicReg(RTL8367D_REG_MIB_ADDRESS, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + if (regData == (mibAddr >> 2)) + { + /* Write MIB addr to an alternate value */ + retVal = rtl8367d_setAsicReg(RTL8367D_REG_MIB_ADDRESS, (mibAddr >> 2) + 1); + if(retVal != RT_ERR_OK) + return retVal; + + while(1) + { + retVal = rtl8367d_getAsicReg(RTL8367D_REG_MIB_ADDRESS, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + if(regData == ((mibAddr >> 2) + 1)) + { + break; + } + + retVal = rtl8367d_setAsicReg(RTL8367D_REG_MIB_ADDRESS, (mibAddr >> 2) + 1); + if(retVal != RT_ERR_OK) + return retVal; + } + + /* polling busy flag */ + i = 100; + while(i > 0) + { + /*read MIB control register*/ + retVal = rtl8367d_getAsicReg(RTL8367D_REG_MIB_CTRL0,®Data); + if(retVal != RT_ERR_OK) + return retVal; + + if((regData & RTL8367D_MIB_CTRL0_BUSY_FLAG_MASK) == 0) + { + break; + } + + i--; + } + + if(regData & RTL8367D_MIB_CTRL0_BUSY_FLAG_MASK) + return RT_ERR_BUSYWAIT_TIMEOUT; + + if(regData & RTL8367D_RESET_FLAG_MASK) + return RT_ERR_STAT_CNTR_FAIL; + } + + /*writing access counter address first*/ + /*This address is SRAM address, and SRAM address = MIB register address >> 2*/ + /*then ASIC will prepare 64bits counter wait for being retrived*/ + /*Write Mib related address to access control register*/ + retVal = rtl8367d_setAsicReg(RTL8367D_REG_MIB_ADDRESS, (mibAddr >> 2)); + if(retVal != RT_ERR_OK) + return retVal; + + /* polling MIB Addr register */ + while(1) + { + retVal = rtl8367d_getAsicReg(RTL8367D_REG_MIB_ADDRESS, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + if(regData == (mibAddr >> 2)) + { + break; + } + + retVal = rtl8367d_setAsicReg(RTL8367D_REG_MIB_ADDRESS, (mibAddr >> 2)); + if(retVal != RT_ERR_OK) + return retVal; + } + + /* polling busy flag */ + i = 100; + while(i > 0) + { + /*read MIB control register*/ + retVal = rtl8367d_getAsicReg(RTL8367D_REG_MIB_CTRL0,®Data); + if(retVal != RT_ERR_OK) + return retVal; + + if((regData & RTL8367D_MIB_CTRL0_BUSY_FLAG_MASK) == 0) + { + break; + } + + i--; + } + + if(regData & RTL8367D_MIB_CTRL0_BUSY_FLAG_MASK) + return RT_ERR_BUSYWAIT_TIMEOUT; + + if(regData & RTL8367D_RESET_FLAG_MASK) + return RT_ERR_STAT_CNTR_FAIL; + + mibCounter = 0; + i = mibLength[mibIdx]; + if(4 == i) + regAddr = RTL8367D_REG_MIB_COUNTER0 + 3; + else + regAddr = RTL8367D_REG_MIB_COUNTER0 + ((mibOff + 1) % 4); + + while(i) + { + retVal = rtl8367d_getAsicReg(regAddr, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + mibCounter = (mibCounter << 16) | (regData & 0xFFFF); + + regAddr --; + i --; + + } + + *pCounter = mibCounter; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8367d_stat_global_reset + * Description: + * Reset global MIB counter. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * Reset MIB counter of ports. API will use global reset while port mask is all-ports. + */ +rtk_api_ret_t dal_rtl8367d_stat_global_reset(void) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + rtk_uint32 regBits; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + regBits = RTL8367D_GLOBAL_RESET_MASK | + RTL8367D_QM_RESET_MASK | + (0xFF<> 8)&0x7) << 13); + + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_MIB_CTRL0, regBits, (regData >> RTL8367D_PORT0_RESET_OFFSET))) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_stat_port_reset + * Description: + * Reset per port MIB counter by port. + * Input: + * port - port id. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * + */ +rtk_api_ret_t dal_rtl8367d_stat_port_reset(rtk_port_t port) +{ + rtk_api_ret_t retVal; + rtk_uint32 portmask; + rtk_uint32 regData; + rtk_uint32 regBits; + rtk_uint32 phyPort; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check port valid */ + RTK_CHK_PORT_VALID(port); + + phyPort = rtk_switch_port_L2P_get(port); + if (phyPort == UNDEFINE_PHY_PORT) + return RT_ERR_PORT_ID; + + portmask = 1 << phyPort; + + regBits = RTL8367D_GLOBAL_RESET_MASK | + RTL8367D_QM_RESET_MASK | + (0xFF<> 8)&0x7) << 13); + + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_MIB_CTRL0, regBits, (regData >> RTL8367D_PORT0_RESET_OFFSET))) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_stat_queueManage_reset + * Description: + * Reset queue manage MIB counter. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * + */ +rtk_api_ret_t dal_rtl8367d_stat_queueManage_reset(void) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + rtk_uint32 regBits; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + + regBits = RTL8367D_GLOBAL_RESET_MASK | + RTL8367D_QM_RESET_MASK | + (0xFF<> 8)&0x7) << 13); + + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_MIB_CTRL0, regBits, (regData >> RTL8367D_PORT0_RESET_OFFSET))) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_stat_global_get + * Description: + * Get global MIB counter + * Input: + * cntr_idx - global counter index. + * Output: + * pCntr - global counter value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * Get global MIB counter by index definition. + */ +rtk_api_ret_t dal_rtl8367d_stat_global_get(rtk_stat_global_type_t cntr_idx, rtk_stat_counter_t *pCntr) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pCntr) + return RT_ERR_NULL_POINTER; + + if (cntr_idx!=DOT1D_TP_LEARNED_ENTRY_DISCARDS_INDEX) + return RT_ERR_STAT_INVALID_GLOBAL_CNTR; + + if ((retVal = _rtl8367d_getMIBsCounter(0, dot1dTpLearnedEntryDiscards, pCntr)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8367d_stat_global_getAll + * Description: + * Get all global MIB counter + * Input: + * None + * Output: + * pGlobal_cntrs - global counter structure. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * Get all global MIB counter by index definition. + */ +rtk_api_ret_t dal_rtl8367d_stat_global_getAll(rtk_stat_global_cntr_t *pGlobal_cntrs) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pGlobal_cntrs) + return RT_ERR_NULL_POINTER; + + if ((retVal = _rtl8367d_getMIBsCounter(0, (RTL8367D_MIBCOUNTER)DOT1D_TP_LEARNED_ENTRY_DISCARDS_INDEX, &pGlobal_cntrs->dot1dTpLearnedEntryDiscards)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8367d_stat_port_get + * Description: + * Get per port MIB counter by index + * Input: + * port - port id. + * cntr_idx - port counter index. + * Output: + * pCntr - MIB retrived counter. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * Get per port MIB counter by index definition. + */ +rtk_api_ret_t dal_rtl8367d_stat_port_get(rtk_port_t port, rtk_stat_port_type_t cntr_idx, rtk_stat_counter_t *pCntr) +{ + rtk_api_ret_t retVal; + RTL8367D_MIBCOUNTER mib_idx; + rtk_stat_counter_t second_cnt; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pCntr) + return RT_ERR_NULL_POINTER; + + /* Check port valid */ + RTK_CHK_PORT_VALID(port); + + if (cntr_idx>=STAT_PORT_CNTR_END) + return RT_ERR_STAT_INVALID_PORT_CNTR; + + if((retVal = _get_asic_mib_idx(cntr_idx, &mib_idx)) != RT_ERR_OK) + return retVal; + + if(mib_idx == MIB_NOT_SUPPORT) + return RT_ERR_CHIP_NOT_SUPPORTED; + + if ((retVal = _rtl8367d_getMIBsCounter(rtk_switch_port_L2P_get(port), mib_idx, pCntr)) != RT_ERR_OK) + return retVal; + + if(cntr_idx == STAT_EtherStatsMulticastPkts) + { + if((retVal = _get_asic_mib_idx(STAT_IfOutMulticastPkts, &mib_idx)) != RT_ERR_OK) + return retVal; + + if((retVal = _rtl8367d_getMIBsCounter(rtk_switch_port_L2P_get(port), mib_idx, &second_cnt)) != RT_ERR_OK) + return retVal; + + *pCntr += second_cnt; + } + + if(cntr_idx == STAT_EtherStatsBroadcastPkts) + { + if((retVal = _get_asic_mib_idx(STAT_IfOutBroadcastPkts, &mib_idx)) != RT_ERR_OK) + return retVal; + + if((retVal = _rtl8367d_getMIBsCounter(rtk_switch_port_L2P_get(port), mib_idx, &second_cnt)) != RT_ERR_OK) + return retVal; + + *pCntr += second_cnt; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_stat_port_getAll + * Description: + * Get all counters of one specified port in the specified device. + * Input: + * port - port id. + * Output: + * pPort_cntrs - buffer pointer of counter value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * Get all MIB counters of one port. + */ +rtk_api_ret_t dal_rtl8367d_stat_port_getAll(rtk_port_t port, rtk_stat_port_cntr_t *pPort_cntrs) +{ + rtk_api_ret_t retVal; + rtk_uint32 mibIndex; + rtk_uint64 mibCounter; + rtk_uint32 *accessPtr; + /* address offset to MIBs counter */ + CONST_T rtk_uint16 mibLength[STAT_PORT_CNTR_END]= { + 2,1,1,1,1,1,1,1,1, + 2,1,1,1,1,1,1,1,1,1,1, + 2,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, + 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1}; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pPort_cntrs) + return RT_ERR_NULL_POINTER; + + /* Check port valid */ + RTK_CHK_PORT_VALID(port); + + accessPtr = (rtk_uint32*)pPort_cntrs; + for (mibIndex=0;mibIndex RTL8367D_MIB_MAX_LOG_CNT_IDX) + return RT_ERR_OUT_OF_RANGE; + + if((idx % 2) == 1) + return RT_ERR_INPUT; + + if(mode >= LOGGING_MODE_END) + return RT_ERR_OUT_OF_RANGE; + + if(type >= LOGGING_TYPE_END) + return RT_ERR_OUT_OF_RANGE; + + if((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_MIB_CTRL5, (idx / 2),(rtk_uint32)type)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_MIB_CTRL3, (idx / 2),(rtk_uint32)mode)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_stat_logging_counterCfg_get + * Description: + * Get the type and mode of Logging Counter + * Input: + * idx - The index of Logging Counter. Should be even number only.(0,2,4,6,8.....14) + * Output: + * pMode - 32 bits or 64 bits mode + * pType - Packet counter or byte counter + * Return: + * RT_ERR_OK - OK + * RT_ERR_OUT_OF_RANGE - Out of range. + * RT_ERR_FAILED - Failed + * RT_ERR_NULL_POINTER - NULL Pointer + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * Get the type and mode of Logging Counter. + */ +rtk_api_ret_t dal_rtl8367d_stat_logging_counterCfg_get(rtk_uint32 idx, rtk_logging_counter_mode_t *pMode, rtk_logging_counter_type_t *pType) +{ + rtk_api_ret_t retVal; + rtk_uint32 type, mode; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(idx > RTL8367D_MIB_MAX_LOG_CNT_IDX) + return RT_ERR_OUT_OF_RANGE; + + if((idx % 2) == 1) + return RT_ERR_INPUT; + + if(pMode == NULL) + return RT_ERR_NULL_POINTER; + + if(pType == NULL) + return RT_ERR_NULL_POINTER; + + + if((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_MIB_CTRL5, (idx / 2),&type)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_MIB_CTRL3, (idx / 2),&mode)) != RT_ERR_OK) + return retVal; + + *pMode = (rtk_logging_counter_mode_t)mode; + *pType = (rtk_logging_counter_type_t)type; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_stat_logging_counter_reset + * Description: + * Reset Logging Counter + * Input: + * idx - The index of Logging Counter. (0~15) + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_OUT_OF_RANGE - Out of range. + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * Reset Logging Counter. + */ +rtk_api_ret_t dal_rtl8367d_stat_logging_counter_reset(rtk_uint32 idx) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(idx > RTL8367D_MIB_MAX_LOG_CNT_IDX) + return RT_ERR_OUT_OF_RANGE; + + if((retVal = rtl8367d_setAsicReg(RTL8367D_REG_MIB_CTRL1, 1< RTL8367D_MIB_MAX_LOG_CNT_IDX) + return RT_ERR_OUT_OF_RANGE; + + mibAddr = RTL8367D_MIB_LOG_CNT_OFFSET + ((idx / 2) * 4); + + retVal = rtl8367d_setAsicReg(RTL8367D_REG_MIB_ADDRESS, (mibAddr >> 2)); + if(retVal != RT_ERR_OK) + return retVal; + + /*read MIB control register*/ + retVal = rtl8367d_getAsicReg(RTL8367D_REG_MIB_CTRL0, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + if(regData & RTL8367D_MIB_CTRL0_BUSY_FLAG_MASK) + return RT_ERR_BUSYWAIT_TIMEOUT; + + if(regData & RTL8367D_RESET_FLAG_MASK) + return RT_ERR_STAT_CNTR_FAIL; + + mibCounter = 0; + if((idx % 2) == 1) + regAddr = RTL8367D_REG_MIB_COUNTER0 + 3; + else + regAddr = RTL8367D_REG_MIB_COUNTER0 + 1; + + for(i = 0; i <= 1; i++) + { + retVal = rtl8367d_getAsicReg(regAddr, ®Data); + + if(retVal != RT_ERR_OK) + return retVal; + + mibCounter = (mibCounter << 16) | (regData & 0xFFFF); + + regAddr --; + } + + *pCnt = mibCounter; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_stat_lengthMode_set + * Description: + * Set Legnth mode. + * Input: + * txMode - The length counting mode + * rxMode - The length counting mode + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_INPUT - Out of range. + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * + */ +rtk_api_ret_t dal_rtl8367d_stat_lengthMode_set(rtk_stat_lengthMode_t txMode, rtk_stat_lengthMode_t rxMode) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(txMode >= LENGTH_MODE_END) + return RT_ERR_INPUT; + + if(rxMode >= LENGTH_MODE_END) + return RT_ERR_INPUT; + + if( (retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_MIB_RMON_LEN_CTRL, RTL8367D_TX_LENGTH_CTRL_OFFSET, (rtk_uint32)txMode)) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_MIB_RMON_LEN_CTRL, RTL8367D_RX_LENGTH_CTRL_OFFSET, (rtk_uint32)rxMode)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_stat_lengthMode_get + * Description: + * Get Legnth mode. + * Input: + * None. + * Output: + * pTxMode - The length counting mode + * pRxMode - The length counting mode + * Return: + * RT_ERR_OK - OK + * RT_ERR_INPUT - Out of range. + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +rtk_api_ret_t dal_rtl8367d_stat_lengthMode_get(rtk_stat_lengthMode_t *pTxMode, rtk_stat_lengthMode_t *pRxMode) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pTxMode) + return RT_ERR_NULL_POINTER; + + if(NULL == pRxMode) + return RT_ERR_NULL_POINTER; + + if( (retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_MIB_RMON_LEN_CTRL, RTL8367D_TX_LENGTH_CTRL_OFFSET, (rtk_uint32 *)pTxMode)) != RT_ERR_OK) + return retVal; + + if( (retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_MIB_RMON_LEN_CTRL, RTL8367D_RX_LENGTH_CTRL_OFFSET, (rtk_uint32 *)pRxMode)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_stat.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_stat.h new file mode 100644 index 00000000..24aa276b --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_stat.h @@ -0,0 +1,350 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8367/RTL8367D switch high-level API + * + * Feature : The file includes MIB module high-layer API defination + * + */ + +#ifndef __DAL_RTL8367D_STAT_H__ +#define __DAL_RTL8367D_STAT_H__ + +#include + +#define RTL8367D_MIB_PORT_OFFSET (0x7C) +#define RTL8367D_MIB_LEARNENTRYDISCARD_OFFSET (0x420) + +#define RTL8367D_MAX_LOG_CNT_NUM (16) +#define RTL8367D_MIB_MAX_LOG_CNT_IDX (RTL8367D_MAX_LOG_CNT_NUM - 1) +#define RTL8367D_MIB_LOG_CNT_OFFSET (0x3E0) +#define RTL8367D_MIB_MAX_LOG_MODE_IDX (8-1) + +typedef enum RTL8367D_MIBCOUNTER_E{ + + /* RX */ + ifInOctets = 0, + + dot3StatsFCSErrors, + dot3StatsSymbolErrors, + dot3InPauseFrames, + dot3ControlInUnknownOpcodes, + + etherStatsFragments, + etherStatsJabbers, + ifInUcastPkts, + etherStatsDropEvents, + + ifInMulticastPkts, + ifInBroadcastPkts, + inMldChecksumError, + inIgmpChecksumError, + inMldSpecificQuery, + inMldGeneralQuery, + inIgmpSpecificQuery, + inIgmpGeneralQuery, + inMldLeaves, + inIgmpLeaves, + + /* TX/RX */ + etherStatsOctets, + + etherStatsUnderSizePkts, + etherOversizeStats, + etherStatsPkts64Octets, + etherStatsPkts65to127Octets, + etherStatsPkts128to255Octets, + etherStatsPkts256to511Octets, + etherStatsPkts512to1023Octets, + etherStatsPkts1024to1518Octets, + + /* TX */ + ifOutOctets, + + dot3StatsSingleCollisionFrames, + dot3StatMultipleCollisionFrames, + dot3sDeferredTransmissions, + dot3StatsLateCollisions, + etherStatsCollisions, + dot3StatsExcessiveCollisions, + dot3OutPauseFrames, + ifOutDiscards, + + /* ALE */ + dot1dTpPortInDiscards, + ifOutUcastPkts, + ifOutMulticastPkts, + ifOutBroadcastPkts, + outOampduPkts, + inOampduPkts, + + inIgmpJoinsSuccess, + inIgmpJoinsFail, + inMldJoinsSuccess, + inMldJoinsFail, + inReportSuppressionDrop, + inLeaveSuppressionDrop, + outIgmpReports, + outIgmpLeaves, + outIgmpGeneralQuery, + outIgmpSpecificQuery, + outMldReports, + outMldLeaves, + outMldGeneralQuery, + outMldSpecificQuery, + inKnownMulticastPkts, + + /*Device only */ + dot1dTpLearnedEntryDiscards, + RTL8367D_MIBS_NUMBER, + +}RTL8367D_MIBCOUNTER; + +/* Function Name: + * dal_rtl8367d_stat_global_reset + * Description: + * Reset global MIB counter. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * Reset MIB counter of ports. API will use global reset while port mask is all-ports. + */ +extern rtk_api_ret_t dal_rtl8367d_stat_global_reset(void); + +/* Function Name: + * dal_rtl8367d_stat_port_reset + * Description: + * Reset per port MIB counter by port. + * Input: + * port - port id. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367d_stat_port_reset(rtk_port_t port); + +/* Function Name: + * dal_rtl8367d_stat_queueManage_reset + * Description: + * Reset queue manage MIB counter. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367d_stat_queueManage_reset(void); + +/* Function Name: + * dal_rtl8367d_stat_global_get + * Description: + * Get global MIB counter + * Input: + * cntr_idx - global counter index. + * Output: + * pCntr - global counter value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * Get global MIB counter by index definition. + */ +extern rtk_api_ret_t dal_rtl8367d_stat_global_get(rtk_stat_global_type_t cntr_idx, rtk_stat_counter_t *pCntr); + +/* Function Name: + * dal_rtl8367d_stat_global_getAll + * Description: + * Get all global MIB counter + * Input: + * None + * Output: + * pGlobal_cntrs - global counter structure. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * Get all global MIB counter by index definition. + */ +extern rtk_api_ret_t dal_rtl8367d_stat_global_getAll(rtk_stat_global_cntr_t *pGlobal_cntrs); + +/* Function Name: + * dal_rtl8367d_stat_port_get + * Description: + * Get per port MIB counter by index + * Input: + * port - port id. + * cntr_idx - port counter index. + * Output: + * pCntr - MIB retrived counter. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * Get per port MIB counter by index definition. + */ +extern rtk_api_ret_t dal_rtl8367d_stat_port_get(rtk_port_t port, rtk_stat_port_type_t cntr_idx, rtk_stat_counter_t *pCntr); + +/* Function Name: + * dal_rtl8367d_stat_port_getAll + * Description: + * Get all counters of one specified port in the specified device. + * Input: + * port - port id. + * Output: + * pPort_cntrs - buffer pointer of counter value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * Get all MIB counters of one port. + */ +extern rtk_api_ret_t dal_rtl8367d_stat_port_getAll(rtk_port_t port, rtk_stat_port_cntr_t *pPort_cntrs); + +/* Function Name: + * dal_rtl8367d_stat_logging_counterCfg_set + * Description: + * Set the type and mode of Logging Counter + * Input: + * idx - The index of Logging Counter. Should be even number only.(0,2,4,6,8.....14) + * mode - 32 bits or 64 bits mode + * type - Packet counter or byte counter + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_OUT_OF_RANGE - Out of range. + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * Set the type and mode of Logging Counter. + */ +extern rtk_api_ret_t dal_rtl8367d_stat_logging_counterCfg_set(rtk_uint32 idx, rtk_logging_counter_mode_t mode, rtk_logging_counter_type_t type); + +/* Function Name: + * dal_rtl8367d_stat_logging_counterCfg_get + * Description: + * Get the type and mode of Logging Counter + * Input: + * idx - The index of Logging Counter. Should be even number only.(0,2,4,6,8.....14) + * Output: + * pMode - 32 bits or 64 bits mode + * pType - Packet counter or byte counter + * Return: + * RT_ERR_OK - OK + * RT_ERR_OUT_OF_RANGE - Out of range. + * RT_ERR_FAILED - Failed + * RT_ERR_NULL_POINTER - NULL Pointer + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * Get the type and mode of Logging Counter. + */ +extern rtk_api_ret_t dal_rtl8367d_stat_logging_counterCfg_get(rtk_uint32 idx, rtk_logging_counter_mode_t *pMode, rtk_logging_counter_type_t *pType); + +/* Function Name: + * dal_rtl8367d_stat_logging_counter_reset + * Description: + * Reset Logging Counter + * Input: + * idx - The index of Logging Counter. (0~15) + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_OUT_OF_RANGE - Out of range. + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * Reset Logging Counter. + */ +extern rtk_api_ret_t dal_rtl8367d_stat_logging_counter_reset(rtk_uint32 idx); + +/* Function Name: + * dal_rtl8367d_stat_logging_counter_get + * Description: + * Get Logging Counter + * Input: + * idx - The index of Logging Counter. (0~15) + * Output: + * pCnt - Logging counter value + * Return: + * RT_ERR_OK - OK + * RT_ERR_OUT_OF_RANGE - Out of range. + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * Get Logging Counter. + */ +extern rtk_api_ret_t dal_rtl8367d_stat_logging_counter_get(rtk_uint32 idx, rtk_uint32 *pCnt); + +/* Function Name: + * dal_rtl8367d_stat_lengthMode_set + * Description: + * Set Legnth mode. + * Input: + * txMode - The length counting mode + * rxMode - The length counting mode + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_INPUT - Out of range. + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367d_stat_lengthMode_set(rtk_stat_lengthMode_t txMode, rtk_stat_lengthMode_t rxMode); + +/* Function Name: + * dal_rtl8367d_stat_lengthMode_get + * Description: + * Get Legnth mode. + * Input: + * None. + * Output: + * pTxMode - The length counting mode + * pRxMode - The length counting mode + * Return: + * RT_ERR_OK - OK + * RT_ERR_INPUT - Out of range. + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +extern rtk_api_ret_t dal_rtl8367d_stat_lengthMode_get(rtk_stat_lengthMode_t *pTxMode, rtk_stat_lengthMode_t *pRxMode); + +#endif /* __DAL_RTL8367D_STAT_H__ */ + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_storm.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_storm.c new file mode 100644 index 00000000..77081373 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_storm.c @@ -0,0 +1,824 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8367C + * Feature : Here is a list of all functions and variables in Storm module. + * + */ + +#include +#include +#include +#include + +#define RTL8367D_STORM_UNDA_METER_CTRL_REG(port) (RTL8367D_REG_STORM_UNDA_METER_CTRL0 + (port >> 1)) +#define RTL8367D_STORM_UNDA_METER_CTRL_MASK(port) (RTL8367D_STORM_UNDA_METER_CTRL0_PORT0_METERIDX_MASK << ((port & 0x1) << 3)) + +#define RTL8367D_STORM_UNMC_METER_CTRL_REG(port) (RTL8367D_REG_STORM_UNMC_METER_CTRL0 + (port >> 1)) +#define RTL8367D_STORM_UNMC_METER_CTRL_MASK(port) (RTL8367D_STORM_UNMC_METER_CTRL0_PORT0_METERIDX_MASK << ((port & 0x1) << 3)) + +#define RTL8367D_STORM_MCAST_METER_CTRL_REG(port) (RTL8367D_REG_STORM_MCAST_METER_CTRL0 + (port >> 1)) +#define RTL8367D_STORM_MCAST_METER_CTRL_MASK(port) (RTL8367D_STORM_MCAST_METER_CTRL0_PORT0_METERIDX_MASK << ((port & 0x1) << 3)) + +#define RTL8367D_STORM_BCAST_METER_CTRL_REG(port) (RTL8367D_REG_STORM_BCAST_METER_CTRL0 + (port >> 1)) +#define RTL8367D_STORM_BCAST_METER_CTRL_MASK(port) (RTL8367D_STORM_BCAST_METER_CTRL0_PORT0_METERIDX_MASK << ((port & 0x1) << 3)) + +/* Function Name: + * dal_rtl8367d_rate_stormControlMeterIdx_set + * Description: + * Set the storm control meter index. + * Input: + * port - port id + * storm_type - storm group type + * index - storm control meter index. + * Output: + * None. + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - Invalid port id + * RT_ERR_FILTER_METER_ID - Invalid meter + * Note: + * + */ +rtk_api_ret_t dal_rtl8367d_rate_stormControlMeterIdx_set(rtk_port_t port, rtk_rate_storm_group_t stormType, rtk_uint32 index) +{ + rtk_api_ret_t retVal; + rtk_uint32 phy_port; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if (stormType >= STORM_GROUP_END) + return RT_ERR_SFC_UNKNOWN_GROUP; + + if (index > RTK_MAX_METER_ID) + return RT_ERR_FILTER_METER_ID; + + phy_port = rtk_switch_port_L2P_get(port); + + switch (stormType) + { + case STORM_GROUP_UNKNOWN_UNICAST: + if((retVal = rtl8367d_setAsicRegBits(RTL8367D_STORM_UNDA_METER_CTRL_REG(phy_port), RTL8367D_STORM_UNDA_METER_CTRL_MASK(phy_port), index)) != RT_ERR_OK) + return retVal; + break; + case STORM_GROUP_UNKNOWN_MULTICAST: + if((retVal = rtl8367d_setAsicRegBits(RTL8367D_STORM_UNMC_METER_CTRL_REG(phy_port), RTL8367D_STORM_UNMC_METER_CTRL_MASK(phy_port), index)) != RT_ERR_OK) + return retVal; + break; + case STORM_GROUP_MULTICAST: + if((retVal = rtl8367d_setAsicRegBits(RTL8367D_STORM_MCAST_METER_CTRL_REG(phy_port), RTL8367D_STORM_MCAST_METER_CTRL_MASK(phy_port), index)) != RT_ERR_OK) + return retVal; + break; + case STORM_GROUP_BROADCAST: + if((retVal = rtl8367d_setAsicRegBits(RTL8367D_STORM_BCAST_METER_CTRL_REG(phy_port), RTL8367D_STORM_BCAST_METER_CTRL_MASK(phy_port), index)) != RT_ERR_OK) + return retVal; + break; + default: + break; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_rate_stormControlMeterIdx_get + * Description: + * Get the storm control meter index. + * Input: + * port - port id + * storm_type - storm group type + * Output: + * pIndex - storm control meter index. + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - Invalid port id + * RT_ERR_FILTER_METER_ID - Invalid meter + * Note: + * + */ +rtk_api_ret_t dal_rtl8367d_rate_stormControlMeterIdx_get(rtk_port_t port, rtk_rate_storm_group_t stormType, rtk_uint32 *pIndex) +{ + rtk_api_ret_t retVal; + rtk_uint32 phy_port; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if (stormType >= STORM_GROUP_END) + return RT_ERR_SFC_UNKNOWN_GROUP; + + if (NULL == pIndex ) + return RT_ERR_NULL_POINTER; + + phy_port = rtk_switch_port_L2P_get(port); + + switch (stormType) + { + case STORM_GROUP_UNKNOWN_UNICAST: + if((retVal = rtl8367d_getAsicRegBits(RTL8367D_STORM_UNDA_METER_CTRL_REG(phy_port), RTL8367D_STORM_UNDA_METER_CTRL_MASK(phy_port), pIndex)) != RT_ERR_OK) + return retVal; + break; + case STORM_GROUP_UNKNOWN_MULTICAST: + if((retVal = rtl8367d_getAsicRegBits(RTL8367D_STORM_UNMC_METER_CTRL_REG(phy_port), RTL8367D_STORM_UNMC_METER_CTRL_MASK(phy_port), pIndex)) != RT_ERR_OK) + return retVal; + break; + case STORM_GROUP_MULTICAST: + if((retVal = rtl8367d_getAsicRegBits(RTL8367D_STORM_MCAST_METER_CTRL_REG(phy_port), RTL8367D_STORM_MCAST_METER_CTRL_MASK(phy_port), pIndex)) != RT_ERR_OK) + return retVal; + break; + case STORM_GROUP_BROADCAST: + if((retVal = rtl8367d_getAsicRegBits(RTL8367D_STORM_BCAST_METER_CTRL_REG(phy_port), RTL8367D_STORM_BCAST_METER_CTRL_MASK(phy_port), pIndex)) != RT_ERR_OK) + return retVal; + break; + default: + break; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_rate_stormControlPortEnable_set + * Description: + * Set enable status of storm control on specified port. + * Input: + * port - port id + * stormType - storm group type + * enable - enable status of storm control + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +rtk_api_ret_t dal_rtl8367d_rate_stormControlPortEnable_set(rtk_port_t port, rtk_rate_storm_group_t stormType, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if (stormType >= STORM_GROUP_END) + return RT_ERR_SFC_UNKNOWN_GROUP; + + if (enable >= RTK_ENABLE_END) + return RT_ERR_ENABLE; + + switch (stormType) + { + case STORM_GROUP_UNKNOWN_UNICAST: + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_STORM_UNKOWN_UCAST, rtk_switch_port_L2P_get(port), (enable == ENABLED) ? 1 : 0)) != RT_ERR_OK) + return retVal; + break; + case STORM_GROUP_UNKNOWN_MULTICAST: + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_STORM_UNKOWN_MCAST, rtk_switch_port_L2P_get(port), (enable == ENABLED) ? 1 : 0)) != RT_ERR_OK) + return retVal; + break; + case STORM_GROUP_MULTICAST: + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_STORM_MCAST, rtk_switch_port_L2P_get(port), (enable == ENABLED) ? 1 : 0)) != RT_ERR_OK) + return retVal; + break; + case STORM_GROUP_BROADCAST: + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_STORM_BCAST, rtk_switch_port_L2P_get(port), (enable == ENABLED) ? 1 : 0)) != RT_ERR_OK) + return retVal; + break; + default: + break; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_rate_stormControlPortEnable_set + * Description: + * Set enable status of storm control on specified port. + * Input: + * port - port id + * stormType - storm group type + * Output: + * pEnable - enable status of storm control + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +rtk_api_ret_t dal_rtl8367d_rate_stormControlPortEnable_get(rtk_port_t port, rtk_rate_storm_group_t stormType, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if (stormType >= STORM_GROUP_END) + return RT_ERR_SFC_UNKNOWN_GROUP; + + if (NULL == pEnable) + return RT_ERR_ENABLE; + + switch (stormType) + { + case STORM_GROUP_UNKNOWN_UNICAST: + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_STORM_UNKOWN_UCAST, rtk_switch_port_L2P_get(port), ®Data)) != RT_ERR_OK) + return retVal; + break; + case STORM_GROUP_UNKNOWN_MULTICAST: + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_STORM_UNKOWN_MCAST, rtk_switch_port_L2P_get(port), ®Data)) != RT_ERR_OK) + return retVal; + break; + case STORM_GROUP_MULTICAST: + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_STORM_MCAST, rtk_switch_port_L2P_get(port), ®Data)) != RT_ERR_OK) + return retVal; + break; + case STORM_GROUP_BROADCAST: + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_STORM_BCAST, rtk_switch_port_L2P_get(port), ®Data)) != RT_ERR_OK) + return retVal; + break; + default: + break; + } + + *pEnable = (regData == 1) ? ENABLED : DISABLED; + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_storm_bypass_set + * Description: + * Set bypass storm filter control configuration. + * Input: + * type - Bypass storm filter control type. + * enable - Bypass status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_ENABLE - Invalid IFG parameter + * Note: + * + * This API can set per-port bypass stomr filter control frame type including RMA and igmp. + * The bypass frame type is as following: + * - BYPASS_BRG_GROUP, + * - BYPASS_FD_PAUSE, + * - BYPASS_SP_MCAST, + * - BYPASS_1X_PAE, + * - BYPASS_UNDEF_BRG_04, + * - BYPASS_UNDEF_BRG_05, + * - BYPASS_UNDEF_BRG_06, + * - BYPASS_UNDEF_BRG_07, + * - BYPASS_PROVIDER_BRIDGE_GROUP_ADDRESS, + * - BYPASS_UNDEF_BRG_09, + * - BYPASS_UNDEF_BRG_0A, + * - BYPASS_UNDEF_BRG_0B, + * - BYPASS_UNDEF_BRG_0C, + * - BYPASS_PROVIDER_BRIDGE_GVRP_ADDRESS, + * - BYPASS_8021AB, + * - BYPASS_UNDEF_BRG_0F, + * - BYPASS_BRG_MNGEMENT, + * - BYPASS_UNDEFINED_11, + * - BYPASS_UNDEFINED_12, + * - BYPASS_UNDEFINED_13, + * - BYPASS_UNDEFINED_14, + * - BYPASS_UNDEFINED_15, + * - BYPASS_UNDEFINED_16, + * - BYPASS_UNDEFINED_17, + * - BYPASS_UNDEFINED_18, + * - BYPASS_UNDEFINED_19, + * - BYPASS_UNDEFINED_1A, + * - BYPASS_UNDEFINED_1B, + * - BYPASS_UNDEFINED_1C, + * - BYPASS_UNDEFINED_1D, + * - BYPASS_UNDEFINED_1E, + * - BYPASS_UNDEFINED_1F, + * - BYPASS_GMRP, + * - BYPASS_GVRP, + * - BYPASS_UNDEF_GARP_22, + * - BYPASS_UNDEF_GARP_23, + * - BYPASS_UNDEF_GARP_24, + * - BYPASS_UNDEF_GARP_25, + * - BYPASS_UNDEF_GARP_26, + * - BYPASS_UNDEF_GARP_27, + * - BYPASS_UNDEF_GARP_28, + * - BYPASS_UNDEF_GARP_29, + * - BYPASS_UNDEF_GARP_2A, + * - BYPASS_UNDEF_GARP_2B, + * - BYPASS_UNDEF_GARP_2C, + * - BYPASS_UNDEF_GARP_2D, + * - BYPASS_UNDEF_GARP_2E, + * - BYPASS_UNDEF_GARP_2F, + * - BYPASS_IGMP. + * - BYPASS_CDP. + * - BYPASS_CSSTP. + * - BYPASS_LLDP. + */ +rtk_api_ret_t dal_rtl8367d_storm_bypass_set(rtk_storm_bypass_t type, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + rtk_uint32 index; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (type >= BYPASS_END) + return RT_ERR_INPUT; + + if (enable >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if (type >= 0 && type <= BYPASS_UNDEF_GARP_2F) + { + if( (type >= 0x4 && type <= 0x7) || (type >= 0x9 && type <= 0x0C) || (0x0F == type)) + index = 0x04; + else if((type >= 0x13 && type <= 0x17) || (0x19 == type) || (type >= 0x1B && type <= 0x1f)) + index = 0x13; + else if(type >= 0x22 && type <= 0x2F) + index = 0x22; + else + index = (rtk_uint32)type; + + if((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_RMA_CTRL00 + index, RTL8367D_RMA_CTRL00_DISCARD_STORM_FILTER_OFFSET, (enable == ENABLED) ? 1 : 0)) != RT_ERR_OK) + return retVal; + } + else if(type == BYPASS_IGMP) + { + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_IGMP_MLD_CFG0, RTL8367D_IGMP_MLD_DISCARD_STORM_FILTER_OFFSET, (enable == ENABLED) ? 1 : 0)) != RT_ERR_OK) + return retVal; + } + else if (type == BYPASS_CDP) + { + if((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_RMA_CTRL_CDP, RTL8367D_RMA_CTRL_CDP_DISCARD_STORM_FILTER_OFFSET, (enable == ENABLED) ? 1 : 0)) != RT_ERR_OK) + return retVal; + } + else if (type == BYPASS_CSSTP) + { + if((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_RMA_CTRL_CSSTP, RTL8367D_RMA_CTRL_CSSTP_DISCARD_STORM_FILTER_OFFSET, (enable == ENABLED) ? 1 : 0)) != RT_ERR_OK) + return retVal; + } + else if (type == BYPASS_LLDP) + { + if((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_RMA_CTRL_LLDP, RTL8367D_RMA_CTRL_LLDP_DISCARD_STORM_FILTER_OFFSET, (enable == ENABLED) ? 1 : 0)) != RT_ERR_OK) + return retVal; + } + else + return RT_ERR_INPUT; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_storm_bypass_get + * Description: + * Get bypass storm filter control configuration. + * Input: + * type - Bypass storm filter control type. + * Output: + * pEnable - Bypass status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can get per-port bypass stomr filter control frame type including RMA and igmp. + * The bypass frame type is as following: + * - BYPASS_BRG_GROUP, + * - BYPASS_FD_PAUSE, + * - BYPASS_SP_MCAST, + * - BYPASS_1X_PAE, + * - BYPASS_UNDEF_BRG_04, + * - BYPASS_UNDEF_BRG_05, + * - BYPASS_UNDEF_BRG_06, + * - BYPASS_UNDEF_BRG_07, + * - BYPASS_PROVIDER_BRIDGE_GROUP_ADDRESS, + * - BYPASS_UNDEF_BRG_09, + * - BYPASS_UNDEF_BRG_0A, + * - BYPASS_UNDEF_BRG_0B, + * - BYPASS_UNDEF_BRG_0C, + * - BYPASS_PROVIDER_BRIDGE_GVRP_ADDRESS, + * - BYPASS_8021AB, + * - BYPASS_UNDEF_BRG_0F, + * - BYPASS_BRG_MNGEMENT, + * - BYPASS_UNDEFINED_11, + * - BYPASS_UNDEFINED_12, + * - BYPASS_UNDEFINED_13, + * - BYPASS_UNDEFINED_14, + * - BYPASS_UNDEFINED_15, + * - BYPASS_UNDEFINED_16, + * - BYPASS_UNDEFINED_17, + * - BYPASS_UNDEFINED_18, + * - BYPASS_UNDEFINED_19, + * - BYPASS_UNDEFINED_1A, + * - BYPASS_UNDEFINED_1B, + * - BYPASS_UNDEFINED_1C, + * - BYPASS_UNDEFINED_1D, + * - BYPASS_UNDEFINED_1E, + * - BYPASS_UNDEFINED_1F, + * - BYPASS_GMRP, + * - BYPASS_GVRP, + * - BYPASS_UNDEF_GARP_22, + * - BYPASS_UNDEF_GARP_23, + * - BYPASS_UNDEF_GARP_24, + * - BYPASS_UNDEF_GARP_25, + * - BYPASS_UNDEF_GARP_26, + * - BYPASS_UNDEF_GARP_27, + * - BYPASS_UNDEF_GARP_28, + * - BYPASS_UNDEF_GARP_29, + * - BYPASS_UNDEF_GARP_2A, + * - BYPASS_UNDEF_GARP_2B, + * - BYPASS_UNDEF_GARP_2C, + * - BYPASS_UNDEF_GARP_2D, + * - BYPASS_UNDEF_GARP_2E, + * - BYPASS_UNDEF_GARP_2F, + * - BYPASS_IGMP. + * - BYPASS_CDP. + * - BYPASS_CSSTP. + * - BYPASS_LLDP. + */ +rtk_api_ret_t dal_rtl8367d_storm_bypass_get(rtk_storm_bypass_t type, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + rtk_uint32 index; + rtk_uint32 regData; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (type >= BYPASS_END) + return RT_ERR_INPUT; + + if(NULL == pEnable) + return RT_ERR_NULL_POINTER; + + if (type >= 0 && type <= BYPASS_UNDEF_GARP_2F) + { + if( (type >= 0x4 && type <= 0x7) || (type >= 0x9 && type <= 0x0C) || (0x0F == type)) + index = 0x04; + else if((type >= 0x13 && type <= 0x17) || (0x19 == type) || (type >= 0x1B && type <= 0x1f)) + index = 0x13; + else if(type >= 0x22 && type <= 0x2F) + index = 0x22; + else + index = (rtk_uint32)type; + + if((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_RMA_CTRL00 + index, RTL8367D_RMA_CTRL00_DISCARD_STORM_FILTER_OFFSET, ®Data)) != RT_ERR_OK) + return retVal; + } + else if(type == BYPASS_IGMP) + { + if((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_IGMP_MLD_CFG0, RTL8367D_IGMP_MLD_DISCARD_STORM_FILTER_OFFSET, ®Data)) != RT_ERR_OK) + return retVal; + } + else if (type == BYPASS_CDP) + { + if((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_RMA_CTRL_CDP, RTL8367D_RMA_CTRL_CDP_DISCARD_STORM_FILTER_OFFSET, ®Data)) != RT_ERR_OK) + return retVal; + } + else if (type == BYPASS_CSSTP) + { + if((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_RMA_CTRL_CSSTP, RTL8367D_RMA_CTRL_CSSTP_DISCARD_STORM_FILTER_OFFSET, ®Data)) != RT_ERR_OK) + return retVal; + } + else if (type == BYPASS_LLDP) + { + if((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_RMA_CTRL_LLDP, RTL8367D_RMA_CTRL_LLDP_DISCARD_STORM_FILTER_OFFSET, ®Data)) != RT_ERR_OK) + return retVal; + } + else + return RT_ERR_INPUT; + + *pEnable = (regData == 1) ? ENABLED : DISABLED; + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_rate_stormControlExtPortmask_set + * Description: + * Set externsion storm control port mask + * Input: + * pPortmask - port mask + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +rtk_api_ret_t dal_rtl8367d_rate_stormControlExtPortmask_set(rtk_portmask_t *pPortmask) +{ + rtk_api_ret_t retVal; + rtk_uint32 pmask; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pPortmask) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtk_switch_portmask_L2P_get(pPortmask, &pmask)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_STORM_EXT_CFG, RTL8367D_STORM_EXT_EN_PORTMASK_MASK, pmask)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_rate_stormControlExtPortmask_get + * Description: + * Set externsion storm control port mask + * Input: + * None + * Output: + * pPortmask - port mask + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +rtk_api_ret_t dal_rtl8367d_rate_stormControlExtPortmask_get(rtk_portmask_t *pPortmask) +{ + rtk_api_ret_t retVal; + rtk_uint32 pmask; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pPortmask) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_STORM_EXT_CFG, RTL8367D_STORM_EXT_EN_PORTMASK_MASK, &pmask)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtk_switch_portmask_P2L_get(pmask, pPortmask)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_rate_stormControlExtEnable_set + * Description: + * Set externsion storm control state + * Input: + * stormType - storm group type + * enable - externsion storm control state + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +rtk_api_ret_t dal_rtl8367d_rate_stormControlExtEnable_set(rtk_rate_storm_group_t stormType, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (stormType >= STORM_GROUP_END) + return RT_ERR_SFC_UNKNOWN_GROUP; + + if (enable >= RTK_ENABLE_END) + return RT_ERR_ENABLE; + + switch (stormType) + { + case STORM_GROUP_UNKNOWN_UNICAST: + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_STORM_EXT_CFG, RTL8367D_STORM_UNKNOWN_UCAST_EXT_EN_OFFSET, (enable == ENABLED) ? 1 : 0)) != RT_ERR_OK) + return retVal; + break; + case STORM_GROUP_UNKNOWN_MULTICAST: + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_STORM_EXT_CFG, RTL8367D_STORM_UNKNOWN_MCAST_EXT_EN_OFFSET, (enable == ENABLED) ? 1 : 0)) != RT_ERR_OK) + return retVal; + break; + case STORM_GROUP_MULTICAST: + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_STORM_EXT_CFG, RTL8367D_STORM_MCAST_EXT_EN_OFFSET, (enable == ENABLED) ? 1 : 0)) != RT_ERR_OK) + return retVal; + break; + case STORM_GROUP_BROADCAST: + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_STORM_EXT_CFG, RTL8367D_STORM_BCAST_EXT_EN_OFFSET, (enable == ENABLED) ? 1 : 0)) != RT_ERR_OK) + return retVal; + break; + default: + break; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_rate_stormControlExtEnable_get + * Description: + * Get externsion storm control state + * Input: + * stormType - storm group type + * Output: + * pEnable - externsion storm control state + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +rtk_api_ret_t dal_rtl8367d_rate_stormControlExtEnable_get(rtk_rate_storm_group_t stormType, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (stormType >= STORM_GROUP_END) + return RT_ERR_SFC_UNKNOWN_GROUP; + + if (NULL == pEnable) + return RT_ERR_NULL_POINTER; + + switch (stormType) + { + case STORM_GROUP_UNKNOWN_UNICAST: + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_STORM_EXT_CFG, RTL8367D_STORM_UNKNOWN_UCAST_EXT_EN_OFFSET, ®Data)) != RT_ERR_OK) + return retVal; + break; + case STORM_GROUP_UNKNOWN_MULTICAST: + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_STORM_EXT_CFG, RTL8367D_STORM_UNKNOWN_MCAST_EXT_EN_OFFSET, ®Data)) != RT_ERR_OK) + return retVal; + break; + case STORM_GROUP_MULTICAST: + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_STORM_EXT_CFG, RTL8367D_STORM_MCAST_EXT_EN_OFFSET, ®Data)) != RT_ERR_OK) + return retVal; + break; + case STORM_GROUP_BROADCAST: + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_STORM_EXT_CFG, RTL8367D_STORM_BCAST_EXT_EN_OFFSET, ®Data)) != RT_ERR_OK) + return retVal; + break; + default: + break; + } + + *pEnable = (regData == 1) ? ENABLED : DISABLED; + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_rate_stormControlExtMeterIdx_set + * Description: + * Set externsion storm control meter index + * Input: + * stormType - storm group type + * index - externsion storm control state + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +rtk_api_ret_t dal_rtl8367d_rate_stormControlExtMeterIdx_set(rtk_rate_storm_group_t stormType, rtk_uint32 index) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (stormType >= STORM_GROUP_END) + return RT_ERR_SFC_UNKNOWN_GROUP; + + if (index > RTK_MAX_METER_ID) + return RT_ERR_FILTER_METER_ID; + + switch (stormType) + { + case STORM_GROUP_UNKNOWN_UNICAST: + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_STORM_EXT_MTRIDX_CFG1, RTL8367D_UNUC_STORM_EXT_METERIDX_MASK, index))!=RT_ERR_OK) + return retVal; + break; + case STORM_GROUP_UNKNOWN_MULTICAST: + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_STORM_EXT_MTRIDX_CFG1, RTL8367D_UNMC_STORM_EXT_METERIDX_MASK, index))!=RT_ERR_OK) + return retVal; + break; + case STORM_GROUP_MULTICAST: + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_STORM_EXT_MTRIDX_CFG0, RTL8367D_MC_STORM_EXT_METERIDX_MASK, index))!=RT_ERR_OK) + return retVal; + break; + case STORM_GROUP_BROADCAST: + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_STORM_EXT_MTRIDX_CFG0, RTL8367D_BC_STORM_EXT_METERIDX_MASK, index))!=RT_ERR_OK) + return retVal; + break; + default: + break; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_rate_stormControlExtMeterIdx_get + * Description: + * Get externsion storm control meter index + * Input: + * stormType - storm group type + * pIndex - externsion storm control state + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +rtk_api_ret_t dal_rtl8367d_rate_stormControlExtMeterIdx_get(rtk_rate_storm_group_t stormType, rtk_uint32 *pIndex) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (stormType >= STORM_GROUP_END) + return RT_ERR_SFC_UNKNOWN_GROUP; + + if(NULL == pIndex) + return RT_ERR_NULL_POINTER; + + switch (stormType) + { + case STORM_GROUP_UNKNOWN_UNICAST: + if ((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_STORM_EXT_MTRIDX_CFG1, RTL8367D_UNUC_STORM_EXT_METERIDX_MASK, pIndex))!=RT_ERR_OK) + return retVal; + break; + case STORM_GROUP_UNKNOWN_MULTICAST: + if ((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_STORM_EXT_MTRIDX_CFG1, RTL8367D_UNMC_STORM_EXT_METERIDX_MASK, pIndex))!=RT_ERR_OK) + return retVal; + break; + case STORM_GROUP_MULTICAST: + if ((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_STORM_EXT_MTRIDX_CFG0, RTL8367D_MC_STORM_EXT_METERIDX_MASK, pIndex))!=RT_ERR_OK) + return retVal; + break; + case STORM_GROUP_BROADCAST: + if ((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_STORM_EXT_MTRIDX_CFG0, RTL8367D_BC_STORM_EXT_METERIDX_MASK, pIndex))!=RT_ERR_OK) + return retVal; + break; + default: + break; + } + + return RT_ERR_OK; +} + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_storm.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_storm.h new file mode 100644 index 00000000..9be202be --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_storm.h @@ -0,0 +1,355 @@ + /* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8367/RTL8367C switch high-level API + * + * Feature : The file includes Storm module high-layer API defination + * + */ + +#ifndef __DAL_RTL8367D_STORM_H__ +#define __DAL_RTL8367D_STORM_H__ + +#include + +/* Function Name: + * dal_rtl8367d_rate_stormControlMeterIdx_set + * Description: + * Set the storm control meter index. + * Input: + * port - port id + * storm_type - storm group type + * index - storm control meter index. + * Output: + * None. + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - Invalid port id + * RT_ERR_FILTER_METER_ID - Invalid meter + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367d_rate_stormControlMeterIdx_set(rtk_port_t port, rtk_rate_storm_group_t stormType, rtk_uint32 index); + +/* Function Name: + * dal_rtl8367d_rate_stormControlMeterIdx_get + * Description: + * Get the storm control meter index. + * Input: + * port - port id + * storm_type - storm group type + * Output: + * pIndex - storm control meter index. + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - Invalid port id + * RT_ERR_FILTER_METER_ID - Invalid meter + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367d_rate_stormControlMeterIdx_get(rtk_port_t port, rtk_rate_storm_group_t stormType, rtk_uint32 *pIndex); + +/* Function Name: + * dal_rtl8367d_rate_stormControlPortEnable_set + * Description: + * Set enable status of storm control on specified port. + * Input: + * port - port id + * stormType - storm group type + * enable - enable status of storm control + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367d_rate_stormControlPortEnable_set(rtk_port_t port, rtk_rate_storm_group_t stormType, rtk_enable_t enable); + +/* Function Name: + * dal_rtl8367d_rate_stormControlPortEnable_set + * Description: + * Set enable status of storm control on specified port. + * Input: + * port - port id + * stormType - storm group type + * Output: + * pEnable - enable status of storm control + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367d_rate_stormControlPortEnable_get(rtk_port_t port, rtk_rate_storm_group_t stormType, rtk_enable_t *pEnable); + +/* Function Name: + * dal_rtl8367d_storm_bypass_set + * Description: + * Set bypass storm filter control configuration. + * Input: + * type - Bypass storm filter control type. + * enable - Bypass status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_ENABLE - Invalid IFG parameter + * Note: + * + * This API can set per-port bypass stomr filter control frame type including RMA and igmp. + * The bypass frame type is as following: + * - BYPASS_BRG_GROUP, + * - BYPASS_FD_PAUSE, + * - BYPASS_SP_MCAST, + * - BYPASS_1X_PAE, + * - BYPASS_UNDEF_BRG_04, + * - BYPASS_UNDEF_BRG_05, + * - BYPASS_UNDEF_BRG_06, + * - BYPASS_UNDEF_BRG_07, + * - BYPASS_PROVIDER_BRIDGE_GROUP_ADDRESS, + * - BYPASS_UNDEF_BRG_09, + * - BYPASS_UNDEF_BRG_0A, + * - BYPASS_UNDEF_BRG_0B, + * - BYPASS_UNDEF_BRG_0C, + * - BYPASS_PROVIDER_BRIDGE_GVRP_ADDRESS, + * - BYPASS_8021AB, + * - BYPASS_UNDEF_BRG_0F, + * - BYPASS_BRG_MNGEMENT, + * - BYPASS_UNDEFINED_11, + * - BYPASS_UNDEFINED_12, + * - BYPASS_UNDEFINED_13, + * - BYPASS_UNDEFINED_14, + * - BYPASS_UNDEFINED_15, + * - BYPASS_UNDEFINED_16, + * - BYPASS_UNDEFINED_17, + * - BYPASS_UNDEFINED_18, + * - BYPASS_UNDEFINED_19, + * - BYPASS_UNDEFINED_1A, + * - BYPASS_UNDEFINED_1B, + * - BYPASS_UNDEFINED_1C, + * - BYPASS_UNDEFINED_1D, + * - BYPASS_UNDEFINED_1E, + * - BYPASS_UNDEFINED_1F, + * - BYPASS_GMRP, + * - BYPASS_GVRP, + * - BYPASS_UNDEF_GARP_22, + * - BYPASS_UNDEF_GARP_23, + * - BYPASS_UNDEF_GARP_24, + * - BYPASS_UNDEF_GARP_25, + * - BYPASS_UNDEF_GARP_26, + * - BYPASS_UNDEF_GARP_27, + * - BYPASS_UNDEF_GARP_28, + * - BYPASS_UNDEF_GARP_29, + * - BYPASS_UNDEF_GARP_2A, + * - BYPASS_UNDEF_GARP_2B, + * - BYPASS_UNDEF_GARP_2C, + * - BYPASS_UNDEF_GARP_2D, + * - BYPASS_UNDEF_GARP_2E, + * - BYPASS_UNDEF_GARP_2F, + * - BYPASS_IGMP. + */ +extern rtk_api_ret_t dal_rtl8367d_storm_bypass_set(rtk_storm_bypass_t type, rtk_enable_t enable); + +/* Function Name: + * dal_rtl8367d_storm_bypass_get + * Description: + * Get bypass storm filter control configuration. + * Input: + * type - Bypass storm filter control type. + * Output: + * pEnable - Bypass status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can get per-port bypass stomr filter control frame type including RMA and igmp. + * The bypass frame type is as following: + * - BYPASS_BRG_GROUP, + * - BYPASS_FD_PAUSE, + * - BYPASS_SP_MCAST, + * - BYPASS_1X_PAE, + * - BYPASS_UNDEF_BRG_04, + * - BYPASS_UNDEF_BRG_05, + * - BYPASS_UNDEF_BRG_06, + * - BYPASS_UNDEF_BRG_07, + * - BYPASS_PROVIDER_BRIDGE_GROUP_ADDRESS, + * - BYPASS_UNDEF_BRG_09, + * - BYPASS_UNDEF_BRG_0A, + * - BYPASS_UNDEF_BRG_0B, + * - BYPASS_UNDEF_BRG_0C, + * - BYPASS_PROVIDER_BRIDGE_GVRP_ADDRESS, + * - BYPASS_8021AB, + * - BYPASS_UNDEF_BRG_0F, + * - BYPASS_BRG_MNGEMENT, + * - BYPASS_UNDEFINED_11, + * - BYPASS_UNDEFINED_12, + * - BYPASS_UNDEFINED_13, + * - BYPASS_UNDEFINED_14, + * - BYPASS_UNDEFINED_15, + * - BYPASS_UNDEFINED_16, + * - BYPASS_UNDEFINED_17, + * - BYPASS_UNDEFINED_18, + * - BYPASS_UNDEFINED_19, + * - BYPASS_UNDEFINED_1A, + * - BYPASS_UNDEFINED_1B, + * - BYPASS_UNDEFINED_1C, + * - BYPASS_UNDEFINED_1D, + * - BYPASS_UNDEFINED_1E, + * - BYPASS_UNDEFINED_1F, + * - BYPASS_GMRP, + * - BYPASS_GVRP, + * - BYPASS_UNDEF_GARP_22, + * - BYPASS_UNDEF_GARP_23, + * - BYPASS_UNDEF_GARP_24, + * - BYPASS_UNDEF_GARP_25, + * - BYPASS_UNDEF_GARP_26, + * - BYPASS_UNDEF_GARP_27, + * - BYPASS_UNDEF_GARP_28, + * - BYPASS_UNDEF_GARP_29, + * - BYPASS_UNDEF_GARP_2A, + * - BYPASS_UNDEF_GARP_2B, + * - BYPASS_UNDEF_GARP_2C, + * - BYPASS_UNDEF_GARP_2D, + * - BYPASS_UNDEF_GARP_2E, + * - BYPASS_UNDEF_GARP_2F, + * - BYPASS_IGMP. + */ +extern rtk_api_ret_t dal_rtl8367d_storm_bypass_get(rtk_storm_bypass_t type, rtk_enable_t *pEnable); + +/* Function Name: + * dal_rtl8367d_rate_stormControlExtPortmask_set + * Description: + * Set externsion storm control port mask + * Input: + * pPortmask - port mask + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367d_rate_stormControlExtPortmask_set(rtk_portmask_t *pPortmask); + +/* Function Name: + * dal_rtl8367d_rate_stormControlExtPortmask_get + * Description: + * Set externsion storm control port mask + * Input: + * None + * Output: + * pPortmask - port mask + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367d_rate_stormControlExtPortmask_get(rtk_portmask_t *pPortmask); + +/* Function Name: + * dal_rtl8367d_rate_stormControlExtEnable_set + * Description: + * Set externsion storm control state + * Input: + * stormType - storm group type + * enable - externsion storm control state + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367d_rate_stormControlExtEnable_set(rtk_rate_storm_group_t stormType, rtk_enable_t enable); + +/* Function Name: + * dal_rtl8367d_rate_stormControlExtEnable_get + * Description: + * Get externsion storm control state + * Input: + * stormType - storm group type + * Output: + * pEnable - externsion storm control state + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367d_rate_stormControlExtEnable_get(rtk_rate_storm_group_t stormType, rtk_enable_t *pEnable); + +/* Function Name: + * dal_rtl8367d_rate_stormControlExtMeterIdx_set + * Description: + * Set externsion storm control meter index + * Input: + * stormType - storm group type + * index - externsion storm control state + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367d_rate_stormControlExtMeterIdx_set(rtk_rate_storm_group_t stormType, rtk_uint32 index); + +/* Function Name: + * dal_rtl8367d_rate_stormControlExtMeterIdx_get + * Description: + * Get externsion storm control meter index + * Input: + * stormType - storm group type + * pIndex - externsion storm control state + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367d_rate_stormControlExtMeterIdx_get(rtk_rate_storm_group_t stormType, rtk_uint32 *pIndex); + + + +#endif /* __DAL_RTL8367D_STORM_H__ */ diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_svlan.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_svlan.c new file mode 100644 index 00000000..c710c9a1 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_svlan.c @@ -0,0 +1,1270 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8367D + * Feature : Here is a list of all functions and variables in SVLAN module. + * + */ + +#include +#include +#include +#include +#include +#include + + +/* Function Name: + * dal_rtl8367d_svlaninit + * Description: + * Initialize SVLAN Configuration + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * Ether type of S-tag in 802.1ad is 0x88a8 and there are existed ether type 0x9100 and 0x9200 for Q-in-Q SLAN design. + * User can set mathced ether type as service provider supported protocol. + */ +rtk_api_ret_t dal_rtl8367d_svlaninit(void) +{ + rtk_uint32 i; + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /*default use C-priority*/ + if ((retVal = dal_rtl8367d_svlanpriorityRef_set(REF_CTAG_PRI)) != RT_ERR_OK) + return retVal; + + /*Drop SVLAN untag frame*/ + if ((retVal = dal_rtl8367d_svlanuntag_action_set(UNTAG_DROP, 0)) != RT_ERR_OK) + return retVal; + + /*Set TPID to 0x88a8*/ + if ((retVal = dal_rtl8367d_svlantpidEntry_set(0x88a8)) != RT_ERR_OK) + return retVal; + + /*Clean Uplink Port Mask to none*/ + if ((retVal = rtl8367d_setAsicReg(RTL8367D_REG_SVLAN_UPLINK_PORTMASK, 0)) != RT_ERR_OK) + return retVal; + + /*Clean C2S Configuration*/ + for (i=0; i<= RTL8367D_C2SIDXMAX; i++) + { + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_SVLAN_C2SCFG0_CTRL0 + (i*3), RTL8367D_SVLAN_C2SCFG0_CTRL0_MASK, 0)) != RT_ERR_OK) + return retVal; + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_SVLAN_C2SCFG0_CTRL1 + (i*3), RTL8367D_SVLAN_C2SCFG0_CTRL1_MASK, 0)) != RT_ERR_OK) + return retVal; + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_SVLAN_C2SCFG0_CTRL2 + (i*3), RTL8367D_SVLAN_C2SCFG0_CTRL2_MASK, 0)) != RT_ERR_OK) + return retVal; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_svlanservicePort_add + * Description: + * Add one service port in the specified device + * Input: + * port - Port id. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API is setting which port is connected to provider switch. All frames receiving from this port must + * contain accept SVID in S-tag field. + */ +rtk_api_ret_t dal_rtl8367d_svlanservicePort_add(rtk_port_t port) +{ + rtk_api_ret_t retVal; + rtk_uint32 pmsk; + rtk_uint32 phyPort; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* check port valid */ + RTK_CHK_PORT_VALID(port); + + phyPort = rtk_switch_port_L2P_get(port); + if (phyPort == UNDEFINE_PHY_PORT) + return RT_ERR_PORT_ID; + + if ((retVal = rtl8367d_getAsicReg(RTL8367D_REG_SVLAN_UPLINK_PORTMASK, &pmsk)) != RT_ERR_OK) + return retVal; + + pmsk = pmsk | (1<RTK_MAX_NUM_OF_PROTO_TYPE) + return RT_ERR_INPUT; + + if ((retVal = rtl8367d_setAsicReg(RTL8367D_REG_VS_TPID, svlan_tag_id)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_svlantpidEntry_get + * Description: + * Get accepted S-VLAN ether type setting. + * Input: + * None + * Output: + * pSvlan_tag_id - Ether type of S-tag frame parsing in uplink ports. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API is setting which port is connected to provider switch. All frames receiving from this port must + * contain accept SVID in S-tag field. + */ +rtk_api_ret_t dal_rtl8367d_svlantpidEntry_get(rtk_uint32 *pSvlan_tag_id) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pSvlan_tag_id) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367d_getAsicReg(RTL8367D_REG_VS_TPID, pSvlan_tag_id)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_svlanpriorityRef_set + * Description: + * Set S-VLAN upstream priority reference setting. + * Input: + * ref - reference selection parameter. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * Note: + * The API can set the upstream SVLAN tag priority reference source. The related priority + * sources are as following: + * - REF_INTERNAL_PRI, + * - REF_CTAG_PRI, + * - REF_SVLAN_PRI, + * - REF_PB_PRI. + */ +rtk_api_ret_t dal_rtl8367d_svlanpriorityRef_set(rtk_svlan_pri_ref_t ref) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (ref >= REF_PRI_END) + return RT_ERR_INPUT; + + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_SVLAN_CFG, RTL8367D_VS_SPRISEL_MASK, ref)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_svlanpriorityRef_get + * Description: + * Get S-VLAN upstream priority reference setting. + * Input: + * None + * Output: + * pRef - reference selection parameter. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can get the upstream SVLAN tag priority reference source. The related priority + * sources are as following: + * - REF_INTERNAL_PRI, + * - REF_CTAG_PRI, + * - REF_SVLAN_PRI, + * - REF_PB_PRI + */ +rtk_api_ret_t dal_rtl8367d_svlanpriorityRef_get(rtk_svlan_pri_ref_t *pRef) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pRef) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_SVLAN_CFG, RTL8367D_VS_SPRISEL_MASK, pRef)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_svlanmemberPortEntry_set + * Description: + * Configure system SVLAN member content + * Input: + * svid - SVLAN id + * psvlan_cfg - SVLAN member configuration + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_PORT_MASK - Invalid portmask. + * RT_ERR_SVLAN_TABLE_FULL - SVLAN configuration is full. + * Note: + * The API can set system 64 accepted s-tag frame format. Only 64 SVID S-tag frame will be accpeted + * to receiving from uplink ports. Other SVID S-tag frame or S-untagged frame will be droped by default setup. + * - rtk_svlan_memberCfg_t->svid is SVID of SVLAN member configuration. + * - rtk_svlan_memberCfg_t->memberport is member port mask of SVLAN member configuration. + * - rtk_svlan_memberCfg_t->fid is filtering database of SVLAN member configuration. + * - rtk_svlan_memberCfg_t->priority is priority of SVLAN member configuration. + */ +rtk_api_ret_t dal_rtl8367d_svlanmemberPortEntry_set(rtk_vlan_t svid, rtk_svlan_memberCfg_t *pSvlan_cfg) +{ + rtk_api_ret_t retVal; + rtk_uint32 phyMbrPmask, phyUntagPmask; + dal_rtl8367d_user_vlan4kentry vlan4kEntry; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pSvlan_cfg) + return RT_ERR_NULL_POINTER; + + if(svid > RTL8367D_VIDMAX) + return RT_ERR_SVLAN_VID; + + RTK_CHK_PORTMASK_VALID(&(pSvlan_cfg->memberport)); + + RTK_CHK_PORTMASK_VALID(&(pSvlan_cfg->untagport)); + + if (pSvlan_cfg->fid > RTL8367D_FIDMAX) + return RT_ERR_L2_FID; + + if (pSvlan_cfg->chk_ivl_svl> ENABLED) + return RT_ERR_INPUT; + + if (pSvlan_cfg->ivl_svl> ENABLED) + return RT_ERR_INPUT; + + if (pSvlan_cfg->fiden !=0) + return RT_ERR_CHIP_NOT_SUPPORTED; + + if (pSvlan_cfg->priority != 0) + return RT_ERR_CHIP_NOT_SUPPORTED; + + if (pSvlan_cfg->efiden != 0) + return RT_ERR_CHIP_NOT_SUPPORTED; + + if (pSvlan_cfg->efid != 0) + return RT_ERR_CHIP_NOT_SUPPORTED; + + /* Get physical port mask */ + if(rtk_switch_portmask_L2P_get(&(pSvlan_cfg->memberport), &phyMbrPmask) != RT_ERR_OK) + return RT_ERR_FAILED; + if(rtk_switch_portmask_L2P_get(&(pSvlan_cfg->untagport), &phyUntagPmask) != RT_ERR_OK) + return RT_ERR_FAILED; + + memset(&vlan4kEntry, 0, sizeof(dal_rtl8367d_user_vlan4kentry)); + vlan4kEntry.vid = svid; + if ((retVal = _dal_rtl8367d_getAsicVlan4kEntry(&vlan4kEntry)) != RT_ERR_OK) + return retVal; + + vlan4kEntry.vid = svid; + vlan4kEntry.mbr = phyMbrPmask; + vlan4kEntry.untag = phyUntagPmask; + vlan4kEntry.svlan_chk_ivl_svl = pSvlan_cfg->chk_ivl_svl; + vlan4kEntry.ivl_svl = pSvlan_cfg->ivl_svl; + vlan4kEntry.fid_msti = pSvlan_cfg->fid; + + if ((retVal = _dal_rtl8367d_setAsicVlan4kEntry(&vlan4kEntry)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_svlanmemberPortEntry_get + * Description: + * Get SVLAN member Configure. + * Input: + * svid - SVLAN id + * Output: + * pSvlan_cfg - SVLAN member configuration + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get system 64 accepted s-tag frame format. Only 64 SVID S-tag frame will be accpeted + * to receiving from uplink ports. Other SVID S-tag frame or S-untagged frame will be droped. + */ +rtk_api_ret_t dal_rtl8367d_svlanmemberPortEntry_get(rtk_vlan_t svid, rtk_svlan_memberCfg_t *pSvlan_cfg) +{ + rtk_api_ret_t retVal; + dal_rtl8367d_user_vlan4kentry vlan4kEntry; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pSvlan_cfg) + return RT_ERR_NULL_POINTER; + + if (svid > RTL8367D_VIDMAX) + return RT_ERR_SVLAN_VID; + + memset(&vlan4kEntry, 0, sizeof(dal_rtl8367d_user_vlan4kentry)); + vlan4kEntry.vid = svid; + if ((retVal = _dal_rtl8367d_getAsicVlan4kEntry(&vlan4kEntry)) != RT_ERR_OK) + return retVal; + + memset(pSvlan_cfg, 0, sizeof(rtk_svlan_memberCfg_t)); + pSvlan_cfg->svid = vlan4kEntry.vid; + if(rtk_switch_portmask_P2L_get(vlan4kEntry.mbr,&(pSvlan_cfg->memberport)) != RT_ERR_OK) + return RT_ERR_FAILED; + if(rtk_switch_portmask_P2L_get(vlan4kEntry.untag,&(pSvlan_cfg->untagport)) != RT_ERR_OK) + return RT_ERR_FAILED; + pSvlan_cfg->chk_ivl_svl = vlan4kEntry.svlan_chk_ivl_svl; + pSvlan_cfg->ivl_svl = vlan4kEntry.ivl_svl; + pSvlan_cfg->fid = vlan4kEntry.fid_msti; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_svlandefaultSvlan_set + * Description: + * Configure default egress SVLAN. + * Input: + * port - Source port + * svid - SVLAN id + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found. + * Note: + * The API can set port n S-tag format index while receiving frame from port n + * is transmit through uplink port with s-tag field + */ +rtk_api_ret_t dal_rtl8367d_svlandefaultSvlan_set(rtk_port_t port, rtk_vlan_t svid) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check port Valid */ + RTK_CHK_PORT_VALID(port); + + /* svid must be 0~4095 */ + if (svid > RTL8367D_VIDMAX) + return RT_ERR_SVLAN_VID; + + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_SVLAN_PORTBASED_SVID_CTRL0 + rtk_switch_port_L2P_get(port), RTL8367D_SVLAN_PORTBASED_SVID_CTRL0_MASK, svid)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_svlandefaultSvlan_get + * Description: + * Get the configure default egress SVLAN. + * Input: + * port - Source port + * Output: + * pSvid - SVLAN VID + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get port n S-tag format index while receiving frame from port n + * is transmit through uplink port with s-tag field + */ +rtk_api_ret_t dal_rtl8367d_svlandefaultSvlan_get(rtk_port_t port, rtk_vlan_t *pSvid) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pSvid) + return RT_ERR_NULL_POINTER; + + /* Check port Valid */ + RTK_CHK_PORT_VALID(port); + + if ((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_SVLAN_PORTBASED_SVID_CTRL0 + rtk_switch_port_L2P_get(port), RTL8367D_SVLAN_PORTBASED_SVID_CTRL0_MASK, pSvid)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_svlanc2s_add + * Description: + * Configure SVLAN C2S table + * Input: + * vid - VLAN ID + * src_port - Ingress Port + * svid - SVLAN VID + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port ID. + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can set system C2S configuration. ASIC will check upstream's VID and assign related + * SVID to mathed packet. There are 128 SVLAN C2S configurations. + */ +rtk_api_ret_t dal_rtl8367d_svlanc2s_add(rtk_vlan_t vid, rtk_port_t src_port, rtk_vlan_t svid) +{ + rtk_api_ret_t retVal, i; + rtk_uint32 empty_idx; + rtk_port_t phyPort; + rtk_uint16 doneFlag; + rtk_uint32 idx_svid, idx_pmsk, idx_cvid; + + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + + if (vid > RTL8367D_VIDMAX) + return RT_ERR_VLAN_VID; + + if (svid > RTL8367D_VIDMAX) + return RT_ERR_SVLAN_VID; + + /* Check port Valid */ + RTK_CHK_PORT_VALID(src_port); + + phyPort = rtk_switch_port_L2P_get(src_port); + if (phyPort == UNDEFINE_PHY_PORT) + return RT_ERR_PORT_ID; + + empty_idx = 0xFFFF; + doneFlag = FALSE; + + for (i = RTL8367D_C2SIDXMAX; i>=0; i--) + { + if ((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_SVLAN_C2SCFG0_CTRL0 + (i*3), RTL8367D_SVLAN_C2SCFG0_CTRL0_MASK, &idx_svid)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_SVLAN_C2SCFG0_CTRL1 + (i*3), RTL8367D_SVLAN_C2SCFG0_CTRL1_MASK, &idx_pmsk)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_SVLAN_C2SCFG0_CTRL2 + (i*3), RTL8367D_SVLAN_C2SCFG0_CTRL2_MASK, &idx_cvid)) != RT_ERR_OK) + return retVal; + + + if (idx_cvid == vid) + { + /* Check Src_port */ + if(idx_pmsk & (1 << phyPort)) + { + /* Check SVIDX */ + if(idx_svid == svid) + { + /* All the same, do nothing */ + } + else + { + /* New svidx, remove src_port and find a new slot to add a new enrty */ + idx_pmsk = idx_pmsk & ~(1 << phyPort); + if(idx_pmsk == 0) + idx_svid = 0; + + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_SVLAN_C2SCFG0_CTRL0 + (i*3), RTL8367D_SVLAN_C2SCFG0_CTRL0_MASK, idx_svid)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_SVLAN_C2SCFG0_CTRL1 + (i*3), RTL8367D_SVLAN_C2SCFG0_CTRL1_MASK, idx_pmsk)) != RT_ERR_OK) + return retVal; + } + } + else + { + if(idx_svid == svid && doneFlag == FALSE) + { + idx_pmsk = idx_pmsk | (1 << phyPort); + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_SVLAN_C2SCFG0_CTRL1 + (i*3), RTL8367D_SVLAN_C2SCFG0_CTRL1_MASK, idx_pmsk)) != RT_ERR_OK) + return retVal; + + doneFlag = TRUE; + } + } + } + else if (idx_svid==0&&idx_pmsk==0) + { + empty_idx = i; + } + } + + if (0xFFFF != empty_idx && doneFlag ==FALSE) + { + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_SVLAN_C2SCFG0_CTRL0 + (empty_idx*3), RTL8367D_SVLAN_C2SCFG0_CTRL0_MASK, svid)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_SVLAN_C2SCFG0_CTRL1 + (empty_idx*3), RTL8367D_SVLAN_C2SCFG0_CTRL1_MASK, (1< RTL8367D_VIDMAX) + return RT_ERR_VLAN_VID; + + /* Check port Valid */ + RTK_CHK_PORT_VALID(src_port); + phyPort = rtk_switch_port_L2P_get(src_port); + if (phyPort == UNDEFINE_PHY_PORT) + return RT_ERR_PORT_ID; + + for (i = 0; i <= RTL8367D_C2SIDXMAX; i++) + { + if ((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_SVLAN_C2SCFG0_CTRL0 + (i*3), RTL8367D_SVLAN_C2SCFG0_CTRL0_MASK, &idx_svid)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_SVLAN_C2SCFG0_CTRL1 + (i*3), RTL8367D_SVLAN_C2SCFG0_CTRL1_MASK, &idx_pmsk)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_SVLAN_C2SCFG0_CTRL2 + (i*3), RTL8367D_SVLAN_C2SCFG0_CTRL2_MASK, &idx_cvid)) != RT_ERR_OK) + return retVal; + + if (idx_cvid == vid) + { + if(idx_pmsk & (1 << phyPort)) + { + idx_pmsk = idx_pmsk & ~(1 << phyPort); + if(idx_pmsk == 0) + { + idx_cvid = 0; + idx_svid = 0; + } + + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_SVLAN_C2SCFG0_CTRL0 + (i*3), RTL8367D_SVLAN_C2SCFG0_CTRL0_MASK, idx_svid)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_SVLAN_C2SCFG0_CTRL1 + (i*3), RTL8367D_SVLAN_C2SCFG0_CTRL1_MASK, idx_pmsk)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_SVLAN_C2SCFG0_CTRL2 + (i*3), RTL8367D_SVLAN_C2SCFG0_CTRL2_MASK, idx_cvid)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; + } + } + } + + return RT_ERR_OUT_OF_RANGE; +} + +/* Function Name: + * dal_rtl8367d_svlanc2s_get + * Description: + * Get configure SVLAN C2S table + * Input: + * vid - VLAN ID + * src_port - Ingress Port + * Output: + * pSvid - SVLAN ID + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port ID. + * RT_ERR_OUT_OF_RANGE - input out of range. + * Note: + * The API can get system C2S configuration. There are 128 SVLAN C2S configurations. + */ +rtk_api_ret_t dal_rtl8367d_svlanc2s_get(rtk_vlan_t vid, rtk_port_t src_port, rtk_vlan_t *pSvid) +{ + rtk_api_ret_t retVal; + rtk_uint32 i; + rtk_uint32 idx_svid, idx_pmsk, idx_cvid; + rtk_port_t phyPort; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pSvid) + return RT_ERR_NULL_POINTER; + + if (vid > RTL8367D_VIDMAX) + return RT_ERR_VLAN_VID; + + /* Check port Valid */ + RTK_CHK_PORT_VALID(src_port); + phyPort = rtk_switch_port_L2P_get(src_port); + if (phyPort == UNDEFINE_PHY_PORT) + return RT_ERR_PORT_ID; + + for (i = 0; i <= RTL8367D_C2SIDXMAX; i++) + { + if ((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_SVLAN_C2SCFG0_CTRL0 + (i*3), RTL8367D_SVLAN_C2SCFG0_CTRL0_MASK, &idx_svid)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_SVLAN_C2SCFG0_CTRL1 + (i*3), RTL8367D_SVLAN_C2SCFG0_CTRL1_MASK, &idx_pmsk)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_SVLAN_C2SCFG0_CTRL2 + (i*3), RTL8367D_SVLAN_C2SCFG0_CTRL2_MASK, &idx_cvid)) != RT_ERR_OK) + return retVal; + + if (idx_cvid == vid) + { + if(idx_pmsk & (1 << phyPort)) + { + *pSvid = idx_svid; + return RT_ERR_OK; + } + } + } + + return RT_ERR_OUT_OF_RANGE; +} + +/* Function Name: + * dal_rtl8367d_svlan_sp2c_add + * Description: + * Add system SP2C configuration + * Input: + * cvid - VLAN ID + * dst_port - Destination port of SVLAN to CVLAN configuration + * svid - SVLAN VID + * + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can add SVID & Destination Port to CVLAN configuration. The downstream frames with assigned + * SVID will be add C-tag with assigned CVID if the output port is the assigned destination port. + * There are 128 SP2C configurations. + */ +rtk_api_ret_t dal_rtl8367d_svlan_sp2c_add(rtk_vlan_t svid, rtk_port_t dst_port, rtk_vlan_t cvid) +{ + rtk_api_ret_t retVal, i; + rtk_uint32 empty_idx; + rtk_port_t port; + rtk_uint32 idx_svid, idx_port; + rtk_uint32 valid_flag; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (svid > RTL8367D_VIDMAX) + return RT_ERR_SVLAN_VID; + + if (cvid > RTL8367D_VIDMAX) + return RT_ERR_VLAN_VID; + + /* Check port Valid */ + RTK_CHK_PORT_VALID(dst_port); + port = rtk_switch_port_L2P_get(dst_port); + empty_idx = 0xFFFF; + + for (i = RTL8367D_SP2CMAX; i>=0; i--) + { + if ((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_SVLAN_SP2C_ENTRY0_CTRL0 + (i*2), RTL8367D_SVLAN_SP2C_ENTRY0_CTRL0_SVID_MASK, &idx_svid)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_SVLAN_SP2C_ENTRY0_CTRL0 + (i*2), RTL8367D_SVLAN_SP2C_ENTRY0_CTRL0_DST_PORT_MASK, &idx_port)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_SVLAN_SP2C_ENTRY0_CTRL1 + (i*2), RTL8367D_SVLAN_SP2C_ENTRY0_CTRL1_VALID_OFFSET, &valid_flag)) != RT_ERR_OK) + return retVal; + + if ( (idx_svid == svid) && (idx_port == port) && (valid_flag == 1)) + { + empty_idx = i; + break; + } + else if (valid_flag == 0) + { + empty_idx = i; + } + + } + + if (empty_idx!=0xFFFF) + { + valid_flag = 1; + + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_SVLAN_SP2C_ENTRY0_CTRL0 + (empty_idx*2), RTL8367D_SVLAN_SP2C_ENTRY0_CTRL0_SVID_MASK, svid)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_SVLAN_SP2C_ENTRY0_CTRL0 + (empty_idx*2), RTL8367D_SVLAN_SP2C_ENTRY0_CTRL0_DST_PORT_MASK, port)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_SVLAN_SP2C_ENTRY0_CTRL1 + (empty_idx*2), RTL8367D_SVLAN_SP2C_ENTRY0_CTRL1_VID_MASK, cvid)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_SVLAN_SP2C_ENTRY0_CTRL1 + (empty_idx*2), RTL8367D_SVLAN_SP2C_ENTRY0_CTRL1_VALID_OFFSET, valid_flag)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; + } + + return RT_ERR_OUT_OF_RANGE; + +} + +/* Function Name: + * dal_rtl8367d_svlan_sp2c_get + * Description: + * Get configure system SP2C content + * Input: + * svid - SVLAN VID + * dst_port - Destination port of SVLAN to CVLAN configuration + * Output: + * pCvid - VLAN ID + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * Note: + * The API can get SVID & Destination Port to CVLAN configuration. There are 128 SP2C configurations. + */ +rtk_api_ret_t dal_rtl8367d_svlan_sp2c_get(rtk_vlan_t svid, rtk_port_t dst_port, rtk_vlan_t *pCvid) +{ + rtk_api_ret_t retVal; + rtk_uint32 i; + rtk_uint32 idx_svid, idx_cvid, idx_port; + rtk_uint32 valid_flag; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pCvid) + return RT_ERR_NULL_POINTER; + + if (svid > RTL8367D_VIDMAX) + return RT_ERR_SVLAN_VID; + + /* Check port Valid */ + RTK_CHK_PORT_VALID(dst_port); + dst_port = rtk_switch_port_L2P_get(dst_port); + + for (i = 0; i <= RTL8367D_SP2CMAX; i++) + { + if ((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_SVLAN_SP2C_ENTRY0_CTRL0 + (i*2), RTL8367D_SVLAN_SP2C_ENTRY0_CTRL0_SVID_MASK, &idx_svid)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_SVLAN_SP2C_ENTRY0_CTRL0 + (i*2), RTL8367D_SVLAN_SP2C_ENTRY0_CTRL0_DST_PORT_MASK, &idx_port)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_SVLAN_SP2C_ENTRY0_CTRL1 + (i*2), RTL8367D_SVLAN_SP2C_ENTRY0_CTRL1_VALID_OFFSET, &valid_flag)) != RT_ERR_OK) + return retVal; + + if ( (idx_svid == svid) && (idx_port == dst_port) && (valid_flag == 1)) + { + if ((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_SVLAN_SP2C_ENTRY0_CTRL1 + (i*2), RTL8367D_SVLAN_SP2C_ENTRY0_CTRL1_VID_MASK, &idx_cvid)) != RT_ERR_OK) + return retVal; + + *pCvid = idx_cvid; + return RT_ERR_OK; + } + } + + return RT_ERR_OUT_OF_RANGE; +} + +/* Function Name: + * dal_rtl8367d_svlan_sp2c_del + * Description: + * Delete system SP2C configuration + * Input: + * svid - SVLAN VID + * dst_port - Destination port of SVLAN to CVLAN configuration + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_OUT_OF_RANGE - input out of range. + * Note: + * The API can delete SVID & Destination Port to CVLAN configuration. There are 128 SP2C configurations. + */ +rtk_api_ret_t dal_rtl8367d_svlan_sp2c_del(rtk_vlan_t svid, rtk_port_t dst_port) +{ + rtk_api_ret_t retVal; + rtk_uint32 i; + rtk_uint32 idx_svid, idx_port; + rtk_uint32 valid_flag; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (svid > RTL8367D_VIDMAX) + return RT_ERR_SVLAN_VID; + + /* Check port Valid */ + RTK_CHK_PORT_VALID(dst_port); + dst_port = rtk_switch_port_L2P_get(dst_port); + + + + for (i = 0; i <= RTL8367D_SP2CMAX; i++) + { + if ((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_SVLAN_SP2C_ENTRY0_CTRL0 + (i*2), RTL8367D_SVLAN_SP2C_ENTRY0_CTRL0_SVID_MASK, &idx_svid)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_SVLAN_SP2C_ENTRY0_CTRL0 + (i*2), RTL8367D_SVLAN_SP2C_ENTRY0_CTRL0_DST_PORT_MASK, &idx_port)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_SVLAN_SP2C_ENTRY0_CTRL1 + (i*2), RTL8367D_SVLAN_SP2C_ENTRY0_CTRL1_VALID_OFFSET, &valid_flag)) != RT_ERR_OK) + return retVal; + + if ( (idx_svid == svid) && (idx_port == dst_port) && (valid_flag == 1)) + { + if ((retVal = rtl8367d_setAsicReg(RTL8367D_REG_SVLAN_SP2C_ENTRY0_CTRL0 + (i*2), 0)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicReg(RTL8367D_REG_SVLAN_SP2C_ENTRY0_CTRL1 + (i*2), 0)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; + } + + } + + return RT_ERR_OUT_OF_RANGE; +} + + + + +/* Function Name: + * dal_rtl8367d_svlanuntag_action_set + * Description: + * Configure Action of downstream Un-Stag packet + * Input: + * action - Action for UnStag + * svid - The SVID assigned to UnStag packet + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found. + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can configure action of downstream Un-Stag packet. A SVID assigned + * to the un-stag is also supported by this API. The parameter of svid is + * only referenced when the action is set to UNTAG_ASSIGN + */ +rtk_api_ret_t dal_rtl8367d_svlanuntag_action_set(rtk_svlan_untag_action_t action, rtk_vlan_t svid) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (action >= UNTAG_END) + return RT_ERR_OUT_OF_RANGE; + + if(action == UNTAG_ASSIGN) + { + if (svid > RTL8367D_VIDMAX) + return RT_ERR_SVLAN_VID; + } + + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_SVLAN_CFG, RTL8367D_VS_UNTAG_MASK, action)) != RT_ERR_OK) + return retVal; + + if(action == UNTAG_ASSIGN) + { + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_SVLAN_UNTAG_UNMAT_CFG, RTL8367D_SVLAN_UNTAG_UNMAT_CFG_MASK, svid)) != RT_ERR_OK) + return retVal; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_svlanuntag_action_get + * Description: + * Get Action of downstream Un-Stag packet + * Input: + * None + * Output: + * pAction - Action for UnStag + * pSvid - The SVID assigned to UnStag packet + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found. + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can Get action of downstream Un-Stag packet. A SVID assigned + * to the un-stag is also retrieved by this API. The parameter pSvid is + * only refernced when the action is UNTAG_ASSIGN + */ +rtk_api_ret_t dal_rtl8367d_svlanuntag_action_get(rtk_svlan_untag_action_t *pAction, rtk_vlan_t *pSvid) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pAction || NULL == pSvid) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_SVLAN_CFG, RTL8367D_VS_UNTAG_MASK, pAction)) != RT_ERR_OK) + return retVal; + + if(*pAction == UNTAG_ASSIGN) + { + if ((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_SVLAN_UNTAG_UNMAT_CFG, RTL8367D_SVLAN_UNTAG_UNMAT_CFG_MASK, pSvid)) != RT_ERR_OK) + return retVal; + } + + return RT_ERR_OK; +} + + + +/* Function Name: + * dal_rtl8367d_svlanunassign_action_set + * Description: + * Configure Action of upstream without svid assign action + * Input: + * action - Action for Un-assign + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can configure action of upstream Un-assign svid packet. If action is not + * trap to CPU, the port-based SVID sure be assign as system need + */ +rtk_api_ret_t dal_rtl8367d_svlanunassign_action_set(rtk_svlan_unassign_action_t action) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (action >= UNASSIGN_END) + return RT_ERR_OUT_OF_RANGE; + + retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_SVLAN_CFG, RTL8367D_VS_UIFSEG_OFFSET, action); + + return retVal; +} + +/* Function Name: + * dal_rtl8367d_svlanunassign_action_get + * Description: + * Get action of upstream without svid assignment + * Input: + * None + * Output: + * pAction - Action for Un-assign + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * Note: + * None + */ +rtk_api_ret_t dal_rtl8367d_svlanunassign_action_get(rtk_svlan_unassign_action_t *pAction) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pAction) + return RT_ERR_NULL_POINTER; + + retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_SVLAN_CFG, RTL8367D_VS_UIFSEG_OFFSET, pAction); + + return retVal; +} + +/* Function Name: + * dal_rtl8367d_svlantrapPri_set + * Description: + * Set svlan trap priority + * Input: + * priority - priority for trap packets + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_QOS_INT_PRIORITY + * Note: + * None + */ +rtk_api_ret_t dal_rtl8367d_svlantrapPri_set(rtk_pri_t priority) +{ + rtk_api_ret_t retVal; + + RTK_CHK_INIT_STATE(); + + if(priority > RTL8367D_PRIMAX) + return RT_ERR_OUT_OF_RANGE; + + retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_QOS_TRAP_PRIORITY0, RTL8367D_SVLAN_PRIOIRTY_MASK, priority); + + return retVal; +} + +/* Function Name: + * dal_rtl8367d_svlantrapPri_get + * Description: + * Get svlan trap priority + * Input: + * None + * Output: + * pPriority - priority for trap packets + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None + */ +rtk_api_ret_t dal_rtl8367d_svlantrapPri_get(rtk_pri_t *pPriority) +{ + rtk_api_ret_t retVal; + + RTK_CHK_INIT_STATE(); + + if(NULL == pPriority) + return RT_ERR_NULL_POINTER; + + retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_QOS_TRAP_PRIORITY0, RTL8367D_SVLAN_PRIOIRTY_MASK, pPriority); + + return retVal; +} /* end of rtk_svlan_trapPri_get */ + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_svlan.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_svlan.h new file mode 100644 index 00000000..c111e574 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_svlan.h @@ -0,0 +1,524 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8367/RTL8367C switch high-level API + * + * Feature : The file includes SVLAN module high-layer API defination + * + */ + +#ifndef __DAL_RTL8367D_SVLAN_H__ +#define __DAL_RTL8367D_SVLAN_H__ + +#include + +/* Function Name: + * dal_rtl8367d_svlaninit + * Description: + * Initialize SVLAN Configuration + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * Ether type of S-tag in 802.1ad is 0x88a8 and there are existed ether type 0x9100 and 0x9200 for Q-in-Q SLAN design. + * User can set mathced ether type as service provider supported protocol. + */ +extern rtk_api_ret_t dal_rtl8367d_svlaninit(void); + +/* Function Name: + * dal_rtl8367d_svlanservicePort_add + * Description: + * Add one service port in the specified device + * Input: + * port - Port id. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API is setting which port is connected to provider switch. All frames receiving from this port must + * contain accept SVID in S-tag field. + */ +extern rtk_api_ret_t dal_rtl8367d_svlanservicePort_add(rtk_port_t port); + +/* Function Name: + * dal_rtl8367d_svlanservicePort_get + * Description: + * Get service ports in the specified device. + * Input: + * None + * Output: + * pSvlan_portmask - pointer buffer of svlan ports. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API is setting which port is connected to provider switch. All frames receiving from this port must + * contain accept SVID in S-tag field. + */ +extern rtk_api_ret_t dal_rtl8367d_svlanservicePort_get(rtk_portmask_t *pSvlan_portmask); + +/* Function Name: + * dal_rtl8367d_svlanservicePort_del + * Description: + * Delete one service port in the specified device + * Input: + * port - Port id. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API is removing SVLAN service port in the specified device. + */ +extern rtk_api_ret_t dal_rtl8367d_svlanservicePort_del(rtk_port_t port); + +/* Function Name: + * dal_rtl8367d_svlantpidEntry_set + * Description: + * Configure accepted S-VLAN ether type. + * Input: + * svlan_tag_id - Ether type of S-tag frame parsing in uplink ports. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * Note: + * Ether type of S-tag in 802.1ad is 0x88a8 and there are existed ether type 0x9100 and 0x9200 for Q-in-Q SLAN design. + * User can set mathced ether type as service provider supported protocol. + */ +extern rtk_api_ret_t dal_rtl8367d_svlantpidEntry_set(rtk_uint32 svlan_tag_id); + +/* Function Name: + * dal_rtl8367d_svlantpidEntry_get + * Description: + * Get accepted S-VLAN ether type setting. + * Input: + * None + * Output: + * pSvlan_tag_id - Ether type of S-tag frame parsing in uplink ports. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API is setting which port is connected to provider switch. All frames receiving from this port must + * contain accept SVID in S-tag field. + */ +extern rtk_api_ret_t dal_rtl8367d_svlantpidEntry_get(rtk_uint32 *pSvlan_tag_id); + +/* Function Name: + * dal_rtl8367d_svlanpriorityRef_set + * Description: + * Set S-VLAN upstream priority reference setting. + * Input: + * ref - reference selection parameter. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * Note: + * The API can set the upstream SVLAN tag priority reference source. The related priority + * sources are as following: + * - REF_INTERNAL_PRI, + * - REF_CTAG_PRI, + * - REF_SVLAN_PRI, + * - REF_PB_PRI. + */ +extern rtk_api_ret_t dal_rtl8367d_svlanpriorityRef_set(rtk_svlan_pri_ref_t ref); + +/* Function Name: + * dal_rtl8367d_svlanpriorityRef_get + * Description: + * Get S-VLAN upstream priority reference setting. + * Input: + * None + * Output: + * pRef - reference selection parameter. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can get the upstream SVLAN tag priority reference source. The related priority + * sources are as following: + * - REF_INTERNAL_PRI, + * - REF_CTAG_PRI, + * - REF_SVLAN_PRI, + * - REF_PB_PRI + */ +extern rtk_api_ret_t dal_rtl8367d_svlanpriorityRef_get(rtk_svlan_pri_ref_t *pRef); + +/* Function Name: + * dal_rtl8367d_svlanmemberPortEntry_set + * Description: + * Configure system SVLAN member content + * Input: + * svid - SVLAN id + * psvlan_cfg - SVLAN member configuration + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_PORT_MASK - Invalid portmask. + * RT_ERR_SVLAN_TABLE_FULL - SVLAN configuration is full. + * Note: + * The API can set system 64 accepted s-tag frame format. Only 64 SVID S-tag frame will be accpeted + * to receiving from uplink ports. Other SVID S-tag frame or S-untagged frame will be droped by default setup. + * - rtk_svlan_memberCfg_t->svid is SVID of SVLAN member configuration. + * - rtk_svlan_memberCfg_t->memberport is member port mask of SVLAN member configuration. + * - rtk_svlan_memberCfg_t->fid is filtering database of SVLAN member configuration. + * - rtk_svlan_memberCfg_t->priority is priority of SVLAN member configuration. + */ +extern rtk_api_ret_t dal_rtl8367d_svlanmemberPortEntry_set(rtk_uint32 svid_idx, rtk_svlan_memberCfg_t *psvlan_cfg); + +/* Function Name: + * dal_rtl8367d_svlanmemberPortEntry_get + * Description: + * Get SVLAN member Configure. + * Input: + * svid - SVLAN id + * Output: + * pSvlan_cfg - SVLAN member configuration + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get system 64 accepted s-tag frame format. Only 64 SVID S-tag frame will be accpeted + * to receiving from uplink ports. Other SVID S-tag frame or S-untagged frame will be droped. + */ +extern rtk_api_ret_t dal_rtl8367d_svlanmemberPortEntry_get(rtk_uint32 svid_idx, rtk_svlan_memberCfg_t *pSvlan_cfg); + +/* Function Name: + * dal_rtl8367d_svlandefaultSvlan_set + * Description: + * Configure default egress SVLAN. + * Input: + * port - Source port + * svid - SVLAN id + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found. + * Note: + * The API can set port n S-tag format index while receiving frame from port n + * is transmit through uplink port with s-tag field + */ +extern rtk_api_ret_t dal_rtl8367d_svlandefaultSvlan_set(rtk_port_t port, rtk_vlan_t svid); + +/* Function Name: + * dal_rtl8367d_svlandefaultSvlan_get + * Description: + * Get the configure default egress SVLAN. + * Input: + * port - Source port + * Output: + * pSvid - SVLAN VID + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get port n S-tag format index while receiving frame from port n + * is transmit through uplink port with s-tag field + */ +extern rtk_api_ret_t dal_rtl8367d_svlandefaultSvlan_get(rtk_port_t port, rtk_vlan_t *pSvid); + +/* Function Name: + * dal_rtl8367d_svlanc2s_add + * Description: + * Configure SVLAN C2S table + * Input: + * vid - VLAN ID + * src_port - Ingress Port + * svid - SVLAN VID + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port ID. + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can set system C2S configuration. ASIC will check upstream's VID and assign related + * SVID to mathed packet. There are 128 SVLAN C2S configurations. + */ +extern rtk_api_ret_t dal_rtl8367d_svlanc2s_add(rtk_vlan_t vid, rtk_port_t src_port, rtk_vlan_t svid); + +/* Function Name: + * dal_rtl8367d_svlanc2s_del + * Description: + * Delete one C2S entry + * Input: + * vid - VLAN ID + * src_port - Ingress Port + * svid - SVLAN VID + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_VLAN_VID - Invalid VID parameter. + * RT_ERR_PORT_ID - Invalid port ID. + * RT_ERR_OUT_OF_RANGE - input out of range. + * Note: + * The API can delete system C2S configuration. There are 128 SVLAN C2S configurations. + */ +extern rtk_api_ret_t dal_rtl8367d_svlanc2s_del(rtk_vlan_t vid, rtk_port_t src_port); + +/* Function Name: + * dal_rtl8367d_svlanc2s_get + * Description: + * Get configure SVLAN C2S table + * Input: + * vid - VLAN ID + * src_port - Ingress Port + * Output: + * pSvid - SVLAN ID + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port ID. + * RT_ERR_OUT_OF_RANGE - input out of range. + * Note: + * The API can get system C2S configuration. There are 128 SVLAN C2S configurations. + */ +extern rtk_api_ret_t dal_rtl8367d_svlanc2s_get(rtk_vlan_t vid, rtk_port_t src_port, rtk_vlan_t *pSvid); + + +/* Function Name: + * dal_rtl8367d_svlan_sp2c_add + * Description: + * Add system SP2C configuration + * Input: + * cvid - VLAN ID + * dst_port - Destination port of SVLAN to CVLAN configuration + * svid - SVLAN VID + * + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can add SVID & Destination Port to CVLAN configuration. The downstream frames with assigned + * SVID will be add C-tag with assigned CVID if the output port is the assigned destination port. + * There are 128 SP2C configurations. + */ +extern rtk_api_ret_t dal_rtl8367d_svlan_sp2c_add(rtk_vlan_t svid, rtk_port_t dst_port, rtk_vlan_t cvid); + +/* Function Name: + * dal_rtl8367d_svlan_sp2c_get + * Description: + * Get configure system SP2C content + * Input: + * svid - SVLAN VID + * dst_port - Destination port of SVLAN to CVLAN configuration + * Output: + * pCvid - VLAN ID + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * Note: + * The API can get SVID & Destination Port to CVLAN configuration. There are 128 SP2C configurations. + */ +extern rtk_api_ret_t dal_rtl8367d_svlan_sp2c_get(rtk_vlan_t svid, rtk_port_t dst_port, rtk_vlan_t *pCvid); + +/* Function Name: + * dal_rtl8367d_svlan_sp2c_del + * Description: + * Delete system SP2C configuration + * Input: + * svid - SVLAN VID + * dst_port - Destination port of SVLAN to CVLAN configuration + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_OUT_OF_RANGE - input out of range. + * Note: + * The API can delete SVID & Destination Port to CVLAN configuration. There are 128 SP2C configurations. + */ +extern rtk_api_ret_t dal_rtl8367d_svlan_sp2c_del(rtk_vlan_t svid, rtk_port_t dst_port); + +/* Function Name: + * dal_rtl8367d_svlanuntag_action_set + * Description: + * Configure Action of downstream Un-Stag packet + * Input: + * action - Action for UnStag + * svid - The SVID assigned to UnStag packet + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found. + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can configure action of downstream Un-Stag packet. A SVID assigned + * to the un-stag is also supported by this API. The parameter of svid is + * only referenced when the action is set to UNTAG_ASSIGN + */ +extern rtk_api_ret_t dal_rtl8367d_svlanuntag_action_set(rtk_svlan_untag_action_t action, rtk_vlan_t svid); + +/* Function Name: + * dal_rtl8367d_svlanuntag_action_get + * Description: + * Get Action of downstream Un-Stag packet + * Input: + * None + * Output: + * pAction - Action for UnStag + * pSvid - The SVID assigned to UnStag packet + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found. + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can Get action of downstream Un-Stag packet. A SVID assigned + * to the un-stag is also retrieved by this API. The parameter pSvid is + * only refernced when the action is UNTAG_ASSIGN + */ +extern rtk_api_ret_t dal_rtl8367d_svlanuntag_action_get(rtk_svlan_untag_action_t *pAction, rtk_vlan_t *pSvid); + +/* Function Name: + * dal_rtl8367d_svlantrapPri_set + * Description: + * Set svlan trap priority + * Input: + * priority - priority for trap packets + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_QOS_INT_PRIORITY + * Note: + * None + */ +extern rtk_api_ret_t dal_rtl8367d_svlantrapPri_set(rtk_pri_t priority); + +/* Function Name: + * dal_rtl8367d_svlantrapPri_get + * Description: + * Get svlan trap priority + * Input: + * None + * Output: + * pPriority - priority for trap packets + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None + */ +extern rtk_api_ret_t dal_rtl8367d_svlantrapPri_get(rtk_pri_t *pPriority); + +/* Function Name: + * dal_rtl8367d_svlanunassign_action_set + * Description: + * Configure Action of upstream without svid assign action + * Input: + * action - Action for Un-assign + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can configure action of upstream Un-assign svid packet. If action is not + * trap to CPU, the port-based SVID sure be assign as system need + */ +extern rtk_api_ret_t dal_rtl8367d_svlanunassign_action_set(rtk_svlan_unassign_action_t action); + +/* Function Name: + * dal_rtl8367d_svlanunassign_action_get + * Description: + * Get action of upstream without svid assignment + * Input: + * None + * Output: + * pAction - Action for Un-assign + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * Note: + * None + */ +extern rtk_api_ret_t dal_rtl8367d_svlanunassign_action_get(rtk_svlan_unassign_action_t *pAction); + + +#endif /* __DAL_RTL8367D_SVLAN_H__ */ diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_switch.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_switch.c new file mode 100644 index 00000000..a1389c40 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_switch.c @@ -0,0 +1,204 @@ +/* + * Copyright (C) 2012 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : Definition of Switch Global API + * + * Feature : The file have include the following module and sub-modules + * (1) Switch parameter settings + * + */ + + +/* + * Include Files + */ +#include +#include + +/* + * Symbol Definition + */ + +/* + * Data Declaration + */ + +/* + * Function Declaration + */ +/* Function Name: + * dal_rtl8367d_switch_init + * Description: + * Set chip to default configuration enviroment + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set chip registers to default configuration for different release chip model. + */ +rtk_api_ret_t dal_rtl8367d_switch_init(void) +{ + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_switch_portMaxPktLen_set + * Description: + * Set Max packet length + * Input: + * port - Port ID + * speed - Speed + * cfgId - Configuration ID + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + */ +rtk_api_ret_t dal_rtl8367d_switch_portMaxPktLen_set(rtk_port_t port, rtk_switch_maxPktLen_linkSpeed_t speed, rtk_uint32 cfgId) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if(speed >= MAXPKTLEN_LINK_SPEED_END) + return RT_ERR_INPUT; + + if(cfgId > MAXPKTLEN_CFG_ID_MAX) + return RT_ERR_INPUT; + + if((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_MAX_LENGTH_CFG, (speed * 8) + rtk_switch_port_L2P_get(port), cfgId)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_switch_portMaxPktLen_get + * Description: + * Get Max packet length + * Input: + * port - Port ID + * speed - Speed + * Output: + * pCfgId - Configuration ID + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + */ +rtk_api_ret_t dal_rtl8367d_switch_portMaxPktLen_get(rtk_port_t port, rtk_switch_maxPktLen_linkSpeed_t speed, rtk_uint32 *pCfgId) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if(speed >= MAXPKTLEN_LINK_SPEED_END) + return RT_ERR_INPUT; + + if(NULL == pCfgId) + return RT_ERR_NULL_POINTER; + + if((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_MAX_LENGTH_CFG, (speed * 8) + rtk_switch_port_L2P_get(port), pCfgId)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8367d_switch_maxPktLenCfg_set + * Description: + * Set Max packet length configuration + * Input: + * cfgId - Configuration ID + * pktLen - Max packet length + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + */ +rtk_api_ret_t dal_rtl8367d_switch_maxPktLenCfg_set(rtk_uint32 cfgId, rtk_uint32 pktLen) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(cfgId > MAXPKTLEN_CFG_ID_MAX) + return RT_ERR_INPUT; + + if(pktLen > RTK_SWITCH_MAX_PKTLEN) + return RT_ERR_INPUT; + + if((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_MAX_LEN_RX_TX_CFG0 + cfgId, RTL8367D_MAX_LEN_RX_TX_CFG0_MASK, pktLen)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_switch_maxPktLenCfg_get + * Description: + * Get Max packet length configuration + * Input: + * cfgId - Configuration ID + * pPktLen - Max packet length + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + */ +rtk_api_ret_t dal_rtl8367d_switch_maxPktLenCfg_get(rtk_uint32 cfgId, rtk_uint32 *pPktLen) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(cfgId > MAXPKTLEN_CFG_ID_MAX) + return RT_ERR_INPUT; + + if(NULL == pPktLen) + return RT_ERR_NULL_POINTER; + + if((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_MAX_LEN_RX_TX_CFG0 + cfgId, RTL8367D_MAX_LEN_RX_TX_CFG0_MASK, pPktLen)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_switch.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_switch.h new file mode 100644 index 00000000..9ac2b5a4 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_switch.h @@ -0,0 +1,142 @@ + +/* + * Copyright (C) 2012 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : Definition of Switch Global API + * + * Feature : The file have include the following module and sub-modules + * (1) Switch parameter settings + * + */ + +#ifndef __DAL_RTL8367D_SWITCH_H__ +#define __DAL_RTL8367D_SWITCH_H__ + +/* + * Include Files + */ +#include +#include + +/* + * Symbol Definition + */ + +/* + * Data Declaration + */ + +/* + * Function Declaration + */ + +/* Module Name : Switch */ +/* Sub-module Name: Switch parameter settings */ + +/* Function Name: + * dal_rtl8367d_switch_init + * Description: + * Initialize switch module of the specified device. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * Note: + * Module must be initialized before using all of APIs in this module + */ +extern rtk_api_ret_t +dal_rtl8367d_switch_init(void); + +/* Module Name : Switch */ +/* Sub-module Name: Switch parameter settings */ +/* Function Name: + * dal_rtl8367d_switch_portMaxPktLen_set + * Description: + * Set Max packet length + * Input: + * port - Port ID + * speed - Speed + * cfgId - Configuration ID + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + */ +extern rtk_api_ret_t +dal_rtl8367d_switch_portMaxPktLen_set(rtk_port_t port, rtk_switch_maxPktLen_linkSpeed_t speed, rtk_uint32 cfgId); + +/* Function Name: + * dal_rtl8367d_switch_portMaxPktLen_get + * Description: + * Get Max packet length + * Input: + * port - Port ID + * speed - Speed + * Output: + * pCfgId - Configuration ID + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + */ +extern rtk_api_ret_t +dal_rtl8367d_switch_portMaxPktLen_get(rtk_port_t port, rtk_switch_maxPktLen_linkSpeed_t speed, rtk_uint32 *pCfgId); + +/* Function Name: + * dal_rtl8367d_switch_maxPktLenCfg_set + * Description: + * Set Max packet length configuration + * Input: + * cfgId - Configuration ID + * pktLen - Max packet length + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + */ +extern rtk_api_ret_t +dal_rtl8367d_switch_maxPktLenCfg_set(rtk_uint32 cfgId, rtk_uint32 pktLen); + +/* Function Name: + * dal_rtl8367d_switch_maxPktLenCfg_get + * Description: + * Get Max packet length configuration + * Input: + * cfgId - Configuration ID + * pPktLen - Max packet length + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + */ +extern rtk_api_ret_t +dal_rtl8367d_switch_maxPktLenCfg_get(rtk_uint32 cfgId, rtk_uint32 *pPktLen); + + +#endif /* __DAL_RTL8367D_SWITCH_H__ */ + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_trap.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_trap.c new file mode 100644 index 00000000..4e1ef9e2 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_trap.c @@ -0,0 +1,1291 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8367C + * Feature : Here is a list of all functions and variables in Trap module. + * + */ + +#include +#include +#include +#include + +/* Function Name: + * dal_rtl8367d_trap_unknownUnicastPktAction_set + * Description: + * Set unknown unicast packet action configuration. + * Input: + * port - ingress port ID for unknown unicast packet + * ucast_action - Unknown unicast action. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid action. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can set unknown unicast packet action configuration. + * The unknown unicast action is as following: + * - UCAST_ACTION_FORWARD_PMASK + * - UCAST_ACTION_DROP + * - UCAST_ACTION_TRAP2CPU + * - UCAST_ACTION_FLOODING + */ +rtk_api_ret_t dal_rtl8367d_trap_unknownUnicastPktAction_set(rtk_port_t port, rtk_trap_ucast_action_t ucast_action) +{ + rtk_api_ret_t retVal; + rtk_uint32 phyPort; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* check port valid */ + RTK_CHK_PORT_VALID(port); + + if (ucast_action >= UCAST_ACTION_COPY28051) + return RT_ERR_INPUT; + + phyPort = rtk_switch_port_L2P_get(port); + if (phyPort == UNDEFINE_PHY_PORT) + return RT_ERR_PORT_ID; + + if((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_UNKNOWN_UNICAST_DA_PORT_BEHAVE, RTL8367D_Port0_ACTION_MASK << (phyPort * 2), (rtk_uint32)ucast_action)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_trap_unknownUnicastPktAction_get + * Description: + * Get unknown unicast packet action configuration. + * Input: + * port - ingress port ID for unknown unicast packet + * Output: + * pUcast_action - Unknown unicast action. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid action. + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * This API can get unknown unicast packet action configuration. + * The unknown unicast action is as following: + * - UCAST_ACTION_FORWARD_PMASK + * - UCAST_ACTION_DROP + * - UCAST_ACTION_TRAP2CPU + * - UCAST_ACTION_FLOODING + */ +rtk_api_ret_t dal_rtl8367d_trap_unknownUnicastPktAction_get(rtk_port_t port, rtk_trap_ucast_action_t *pUcast_action) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + rtk_uint32 phyPort; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* check port valid */ + RTK_CHK_PORT_VALID(port); + + if (NULL == pUcast_action) + return RT_ERR_NULL_POINTER; + + phyPort = rtk_switch_port_L2P_get(port); + if (phyPort == UNDEFINE_PHY_PORT) + return RT_ERR_PORT_ID; + + if((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_UNKNOWN_UNICAST_DA_PORT_BEHAVE, RTL8367D_Port0_ACTION_MASK << (phyPort * 2), ®Data)) != RT_ERR_OK) + return retVal; + + switch (regData) + { + case 0: + *pUcast_action = UCAST_ACTION_FORWARD_PMASK; + break; + case 1: + *pUcast_action = UCAST_ACTION_DROP; + break; + case 2: + *pUcast_action = UCAST_ACTION_TRAP2CPU; + break; + case 3: + *pUcast_action = UCAST_ACTION_FLOODING; + break; + default: + return RT_ERR_FAILED; + break; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_trap_unmatchMacMoving_set + * Description: + * Set unmatch source MAC packet moving state. + * Input: + * port - Port ID. + * enable - ENABLED: allow SA moving, DISABLE: don't allow SA moving. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid action. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + */ +rtk_api_ret_t dal_rtl8367d_trap_unmatchMacMoving_set(rtk_port_t port, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* check port valid */ + RTK_CHK_PORT_VALID(port); + + if(enable >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_L2_SA_MOVING_FORBID, rtk_switch_port_L2P_get(port), (enable == ENABLED) ? 0 : 1)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_trap_unmatchMacMoving_get + * Description: + * Set unmatch source MAC packet moving state. + * Input: + * port - Port ID. + * Output: + * pEnable - ENABLED: allow SA moving, DISABLE: don't allow SA moving. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid action. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + */ +rtk_api_ret_t dal_rtl8367d_trap_unmatchMacMoving_get(rtk_port_t port, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* check port valid */ + RTK_CHK_PORT_VALID(port); + + if(NULL == pEnable) + return RT_ERR_NULL_POINTER; + + if((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_L2_SA_MOVING_FORBID, rtk_switch_port_L2P_get(port), ®Data)) != RT_ERR_OK) + return retVal; + + *pEnable = (regData == 0) ? ENABLED : DISABLED; + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_trap_unknownMcastPktAction_set + * Description: + * Set behavior of unknown multicast + * Input: + * port - Port id. + * type - unknown multicast packet type. + * mcast_action - unknown multicast action. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_NOT_ALLOWED - Invalid action. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * When receives an unknown multicast packet, switch may trap, drop or flood this packet + * (1) The unknown multicast packet type is as following: + * - MCAST_L2 + * - MCAST_IPV4 + * - MCAST_IPV6 + * (2) The unknown multicast action is as following: + * - MCAST_ACTION_FORWARD + * - MCAST_ACTION_DROP + * - MCAST_ACTION_TRAP2CPU + */ +rtk_api_ret_t dal_rtl8367d_trap_unknownMcastPktAction_set(rtk_port_t port, rtk_mcast_type_t type, rtk_trap_mcast_action_t mcast_action) +{ + rtk_api_ret_t retVal; + rtk_uint32 rawAction; + rtk_uint32 phyPort; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if (type >= MCAST_END) + return RT_ERR_INPUT; + + if (mcast_action >= MCAST_ACTION_END) + return RT_ERR_INPUT; + + phyPort = rtk_switch_port_L2P_get(port); + if (phyPort == UNDEFINE_PHY_PORT) + return RT_ERR_PORT_ID; + + switch (type) + { + case MCAST_L2: + if (MCAST_ACTION_ROUTER_PORT == mcast_action) + return RT_ERR_INPUT; + else if(MCAST_ACTION_DROP_EX_RMA == mcast_action) + rawAction = RTL8367D_L2_UNKOWN_MULTICAST_DROP_EXCLUDE_RMA; + else + rawAction = (rtk_uint32)mcast_action; + + if((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_UNKNOWN_L2_MULTICAST_CTRL0, (RTL8367D_PORT0_UNKNOWN_L2_MCAST_MASK << (phyPort * 2)), rawAction)) != RT_ERR_OK) + return retVal; + + break; + case MCAST_IPV4: + if ((MCAST_ACTION_DROP_EX_RMA == mcast_action) || (MCAST_ACTION_ROUTER_PORT == mcast_action)) + return RT_ERR_INPUT; + else + rawAction = (rtk_uint32)mcast_action; + + if((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_UNKNOWN_IPV4_MULTICAST_CTRL0, (RTL8367D_PORT0_UNKNOWN_IP4_MCAST_MASK << (phyPort * 2)), rawAction)) != RT_ERR_OK) + return retVal; + + break; + case MCAST_IPV6: + if ((MCAST_ACTION_DROP_EX_RMA == mcast_action) || (MCAST_ACTION_ROUTER_PORT == mcast_action)) + return RT_ERR_INPUT; + else + rawAction = (rtk_uint32)mcast_action; + + if((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_UNKNOWN_IPV6_MULTICAST_CTRL0, (RTL8367D_PORT0_UNKNOWN_IP6_MCAST_MASK << (phyPort * 2)), rawAction)) != RT_ERR_OK) + return retVal; + + break; + default: + break; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_trap_unknownMcastPktAction_get + * Description: + * Get behavior of unknown multicast + * Input: + * type - unknown multicast packet type. + * Output: + * pMcast_action - unknown multicast action. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_NOT_ALLOWED - Invalid operation. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * When receives an unknown multicast packet, switch may trap, drop or flood this packet + * (1) The unknown multicast packet type is as following: + * - MCAST_L2 + * - MCAST_IPV4 + * - MCAST_IPV6 + * (2) The unknown multicast action is as following: + * - MCAST_ACTION_FORWARD + * - MCAST_ACTION_DROP + * - MCAST_ACTION_TRAP2CPU + */ +rtk_api_ret_t dal_rtl8367d_trap_unknownMcastPktAction_get(rtk_port_t port, rtk_mcast_type_t type, rtk_trap_mcast_action_t *pMcast_action) +{ + rtk_api_ret_t retVal; + rtk_uint32 rawAction; + rtk_uint32 phyPort; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if (type >= MCAST_END) + return RT_ERR_INPUT; + + if(NULL == pMcast_action) + return RT_ERR_NULL_POINTER; + + phyPort = rtk_switch_port_L2P_get(port); + if (phyPort == UNDEFINE_PHY_PORT) + return RT_ERR_PORT_ID; + + switch (type) + { + case MCAST_L2: + if((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_UNKNOWN_L2_MULTICAST_CTRL0, (RTL8367D_PORT0_UNKNOWN_L2_MCAST_MASK << (phyPort * 2)), &rawAction)) != RT_ERR_OK) + return retVal; + + if(RTL8367D_L2_UNKOWN_MULTICAST_DROP_EXCLUDE_RMA == rawAction) + *pMcast_action = MCAST_ACTION_DROP_EX_RMA; + else + *pMcast_action = (rtk_trap_mcast_action_t)rawAction; + + break; + case MCAST_IPV4: + if((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_UNKNOWN_IPV4_MULTICAST_CTRL0, (RTL8367D_PORT0_UNKNOWN_IP4_MCAST_MASK << (phyPort * 2)), &rawAction)) != RT_ERR_OK) + return retVal; + + *pMcast_action = (rtk_trap_mcast_action_t)rawAction; + break; + case MCAST_IPV6: + if((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_UNKNOWN_IPV6_MULTICAST_CTRL0, (RTL8367D_PORT0_UNKNOWN_IP6_MCAST_MASK << (phyPort * 2)), &rawAction)) != RT_ERR_OK) + return retVal; + + *pMcast_action = (rtk_trap_mcast_action_t)rawAction; + break; + default: + break; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_trap_lldpEnable_set + * Description: + * Set LLDP enable. + * Input: + * enabled - LLDP enable, 0: follow RMA, 1: use LLDP action. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid action. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * - DMAC Assignment + * - 01:80:c2:00:00:0e ethertype = 0x88CC LLDP + * - 01:80:c2:00:00:03 ethertype = 0x88CC + * - 01:80:c2:00:00:00 ethertype = 0x88CC + + */ +rtk_api_ret_t dal_rtl8367d_trap_lldpEnable_set(rtk_enable_t enabled) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (enabled >= RTK_ENABLE_END) + return RT_ERR_ENABLE; + + if((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_RMA_LLDP_EN, RTL8367D_RMA_LLDP_EN_OFFSET, (enabled == ENABLED) ? 1 : 0)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_trap_lldpEnable_get + * Description: + * Get LLDP status. + * Input: + * None + * Output: + * pEnabled - LLDP enable, 0: follow RMA, 1: use LLDP action. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * LLDP is as following definition. + * - DMAC Assignment + * - 01:80:c2:00:00:0e ethertype = 0x88CC LLDP + * - 01:80:c2:00:00:03 ethertype = 0x88CC + * - 01:80:c2:00:00:00 ethertype = 0x88CC + */ +rtk_api_ret_t dal_rtl8367d_trap_lldpEnable_get(rtk_enable_t *pEnabled) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pEnabled) + return RT_ERR_NULL_POINTER; + + if((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_RMA_LLDP_EN, RTL8367D_RMA_LLDP_EN_OFFSET, ®Data)) != RT_ERR_OK) + return retVal; + + *pEnabled = (regData == 1) ? ENABLED : DISABLED; + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_trap_reasonTrapToCpuPriority_set + * Description: + * Set priority value of a packet that trapped to CPU port according to specific reason. + * Input: + * type - reason that trap to CPU port. + * priority - internal priority that is going to be set for specific trap reason. + * Output: + * None. + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - Invalid input parameter + * Note: + * Currently the trap reason that supported are listed as follows: + * - TRAP_REASON_RMA + * - TRAP_REASON_1XUNAUTH + * - TRAP_REASON_VLANSTACK + * - TRAP_REASON_UNKNOWNMC + * - TRAP_REASON_IGMPMLD + */ +rtk_api_ret_t dal_rtl8367d_trap_reasonTrapToCpuPriority_set(rtk_trap_reason_type_t type, rtk_pri_t priority) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (type >= TRAP_REASON_END) + return RT_ERR_INPUT; + + if (type == TRAP_REASON_OAM) + return RT_ERR_INPUT; + + if (priority > RTL8367D_TRAP_PRIMAX) + return RT_ERR_QOS_INT_PRIORITY; + + switch (type) + { + case TRAP_REASON_RMA: + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_RMA_CTRL00, RTL8367D_TRAP_PRIORITY_MASK, priority)) != RT_ERR_OK) + return retVal; + break; + case TRAP_REASON_1XUNAUTH: + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_QOS_TRAP_PRIORITY0, RTL8367D_DOT1X_PRIORTY_MASK, priority)) != RT_ERR_OK) + return retVal; + break; + case TRAP_REASON_VLANSTACK: + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_QOS_TRAP_PRIORITY0, RTL8367D_SVLAN_PRIOIRTY_MASK, priority)) != RT_ERR_OK) + return retVal; + break; + case TRAP_REASON_UNKNOWNMC: + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_QOS_TRAP_PRIORITY0, RTL8367D_UNKNOWN_MC_PRIORTY_MASK, priority)) != RT_ERR_OK) + return retVal; + break; + case TRAP_REASON_IGMPMLD: + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_QOS_TRAP_PRIORITY1, RTL8367D_QOS_TRAP_PRIORITY1_MASK, priority)) != RT_ERR_OK) + return retVal; + break; + default: + return RT_ERR_INPUT; + } + + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_trap_reasonTrapToCpuPriority_get + * Description: + * Get priority value of a packet that trapped to CPU port according to specific reason. + * Input: + * type - reason that trap to CPU port. + * Output: + * pPriority - configured internal priority for such reason. + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - Invalid input parameter + * RT_ERR_NULL_POINTER - NULL pointer + * Note: + * Currently the trap reason that supported are listed as follows: + * - TRAP_REASON_RMA + * - TRAP_REASON_1XUNAUTH + * - TRAP_REASON_VLANSTACK + * - TRAP_REASON_UNKNOWNMC + * - TRAP_REASON_IGMPMLD + */ +rtk_api_ret_t dal_rtl8367d_trap_reasonTrapToCpuPriority_get(rtk_trap_reason_type_t type, rtk_pri_t *pPriority) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (type >= TRAP_REASON_END) + return RT_ERR_INPUT; + + if (type == TRAP_REASON_OAM) + return RT_ERR_INPUT; + + if(NULL == pPriority) + return RT_ERR_NULL_POINTER; + + switch (type) + { + case TRAP_REASON_RMA: + if ((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_RMA_CTRL00, RTL8367D_TRAP_PRIORITY_MASK, ®Data)) != RT_ERR_OK) + return retVal; + break; + case TRAP_REASON_1XUNAUTH: + if ((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_QOS_TRAP_PRIORITY0, RTL8367D_DOT1X_PRIORTY_MASK, ®Data)) != RT_ERR_OK) + return retVal; + break; + case TRAP_REASON_VLANSTACK: + if ((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_QOS_TRAP_PRIORITY0, RTL8367D_SVLAN_PRIOIRTY_MASK, ®Data)) != RT_ERR_OK) + return retVal; + break; + case TRAP_REASON_UNKNOWNMC: + if ((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_QOS_TRAP_PRIORITY0, RTL8367D_UNKNOWN_MC_PRIORTY_MASK, ®Data)) != RT_ERR_OK) + return retVal; + break; + case TRAP_REASON_IGMPMLD: + if ((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_QOS_TRAP_PRIORITY1, RTL8367D_QOS_TRAP_PRIORITY1_MASK, ®Data)) != RT_ERR_OK) + return retVal; + break; + default: + return RT_ERR_INPUT; + } + + *pPriority = (rtk_pri_t)regData; + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_trap_rmaAction_set + * Description: + * Set Reserved multicast address action configuration. + * Input: + * type - rma type. + * rma_action - RMA action. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * + * There are 48 types of Reserved Multicast Address frame for application usage. + * (1)They are as following definition. + * - TRAP_BRG_GROUP, + * - TRAP_FD_PAUSE, + * - TRAP_SP_MCAST, + * - TRAP_1X_PAE, + * - TRAP_UNDEF_BRG_04, + * - TRAP_UNDEF_BRG_05, + * - TRAP_UNDEF_BRG_06, + * - TRAP_UNDEF_BRG_07, + * - TRAP_PROVIDER_BRIDGE_GROUP_ADDRESS, + * - TRAP_UNDEF_BRG_09, + * - TRAP_UNDEF_BRG_0A, + * - TRAP_UNDEF_BRG_0B, + * - TRAP_UNDEF_BRG_0C, + * - TRAP_PROVIDER_BRIDGE_GVRP_ADDRESS, + * - TRAP_8021AB, + * - TRAP_UNDEF_BRG_0F, + * - TRAP_BRG_MNGEMENT, + * - TRAP_UNDEFINED_11, + * - TRAP_UNDEFINED_12, + * - TRAP_UNDEFINED_13, + * - TRAP_UNDEFINED_14, + * - TRAP_UNDEFINED_15, + * - TRAP_UNDEFINED_16, + * - TRAP_UNDEFINED_17, + * - TRAP_UNDEFINED_18, + * - TRAP_UNDEFINED_19, + * - TRAP_UNDEFINED_1A, + * - TRAP_UNDEFINED_1B, + * - TRAP_UNDEFINED_1C, + * - TRAP_UNDEFINED_1D, + * - TRAP_UNDEFINED_1E, + * - TRAP_UNDEFINED_1F, + * - TRAP_GMRP, + * - TRAP_GVRP, + * - TRAP_UNDEF_GARP_22, + * - TRAP_UNDEF_GARP_23, + * - TRAP_UNDEF_GARP_24, + * - TRAP_UNDEF_GARP_25, + * - TRAP_UNDEF_GARP_26, + * - TRAP_UNDEF_GARP_27, + * - TRAP_UNDEF_GARP_28, + * - TRAP_UNDEF_GARP_29, + * - TRAP_UNDEF_GARP_2A, + * - TRAP_UNDEF_GARP_2B, + * - TRAP_UNDEF_GARP_2C, + * - TRAP_UNDEF_GARP_2D, + * - TRAP_UNDEF_GARP_2E, + * - TRAP_UNDEF_GARP_2F, + * - TRAP_CDP. + * - TRAP_CSSTP. + * - TRAP_LLDP. + * (2) The RMA action is as following: + * - RMA_ACTION_FORWARD + * - RMA_ACTION_TRAP2CPU + * - RMA_ACTION_DROP + * - RMA_ACTION_FORWARD_EXCLUDE_CPU + */ +rtk_api_ret_t dal_rtl8367d_trap_rmaAction_set(rtk_trap_type_t type, rtk_trap_rma_action_t rma_action) +{ + rtk_api_ret_t retVal; + rtk_uint32 index; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (type >= TRAP_END) + return RT_ERR_INPUT; + + if (rma_action >= RMA_ACTION_END) + return RT_ERR_RMA_ACTION; + + if (type >= 0 && type <= TRAP_UNDEF_GARP_2F) + { + if( (type >= 0x4 && type <= 0x7) || (type >= 0x9 && type <= 0x0C) || (0x0F == type)) + index = 0x04; + else if((type >= 0x13 && type <= 0x17) || (0x19 == type) || (type >= 0x1B && type <= 0x1f)) + index = 0x13; + else if(type >= 0x22 && type <= 0x2F) + index = 0x22; + else + index = (rtk_uint32)type; + + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_RMA_CTRL00 + index, RTL8367D_RMA_CTRL00_OPERATION_MASK, (rtk_uint32)rma_action)) != RT_ERR_OK) + return retVal; + } + else if (type == TRAP_CDP) + { + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_RMA_CTRL_CDP, RTL8367D_RMA_CTRL_CDP_OPERATION_MASK, (rtk_uint32)rma_action)) != RT_ERR_OK) + return retVal; + } + else if (type == TRAP_CSSTP) + { + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_RMA_CTRL_CSSTP, RTL8367D_RMA_CTRL_CSSTP_OPERATION_MASK, (rtk_uint32)rma_action)) != RT_ERR_OK) + return retVal; + } + else if (type == TRAP_LLDP) + { + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_RMA_CTRL_LLDP, RTL8367D_RMA_CTRL_LLDP_OPERATION_MASK, (rtk_uint32)rma_action)) != RT_ERR_OK) + return retVal; + } + else + return RT_ERR_INPUT; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_trap_rmaAction_get + * Description: + * Get Reserved multicast address action configuration. + * Input: + * type - rma type. + * Output: + * pRma_action - RMA action. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * There are 48 types of Reserved Multicast Address frame for application usage. + * (1)They are as following definition. + * - TRAP_BRG_GROUP, + * - TRAP_FD_PAUSE, + * - TRAP_SP_MCAST, + * - TRAP_1X_PAE, + * - TRAP_UNDEF_BRG_04, + * - TRAP_UNDEF_BRG_05, + * - TRAP_UNDEF_BRG_06, + * - TRAP_UNDEF_BRG_07, + * - TRAP_PROVIDER_BRIDGE_GROUP_ADDRESS, + * - TRAP_UNDEF_BRG_09, + * - TRAP_UNDEF_BRG_0A, + * - TRAP_UNDEF_BRG_0B, + * - TRAP_UNDEF_BRG_0C, + * - TRAP_PROVIDER_BRIDGE_GVRP_ADDRESS, + * - TRAP_8021AB, + * - TRAP_UNDEF_BRG_0F, + * - TRAP_BRG_MNGEMENT, + * - TRAP_UNDEFINED_11, + * - TRAP_UNDEFINED_12, + * - TRAP_UNDEFINED_13, + * - TRAP_UNDEFINED_14, + * - TRAP_UNDEFINED_15, + * - TRAP_UNDEFINED_16, + * - TRAP_UNDEFINED_17, + * - TRAP_UNDEFINED_18, + * - TRAP_UNDEFINED_19, + * - TRAP_UNDEFINED_1A, + * - TRAP_UNDEFINED_1B, + * - TRAP_UNDEFINED_1C, + * - TRAP_UNDEFINED_1D, + * - TRAP_UNDEFINED_1E, + * - TRAP_UNDEFINED_1F, + * - TRAP_GMRP, + * - TRAP_GVRP, + * - TRAP_UNDEF_GARP_22, + * - TRAP_UNDEF_GARP_23, + * - TRAP_UNDEF_GARP_24, + * - TRAP_UNDEF_GARP_25, + * - TRAP_UNDEF_GARP_26, + * - TRAP_UNDEF_GARP_27, + * - TRAP_UNDEF_GARP_28, + * - TRAP_UNDEF_GARP_29, + * - TRAP_UNDEF_GARP_2A, + * - TRAP_UNDEF_GARP_2B, + * - TRAP_UNDEF_GARP_2C, + * - TRAP_UNDEF_GARP_2D, + * - TRAP_UNDEF_GARP_2E, + * - TRAP_UNDEF_GARP_2F, + * - TRAP_CDP. + * - TRAP_CSSTP. + * - TRAP_LLDP. + * (2) The RMA action is as following: + * - RMA_ACTION_FORWARD + * - RMA_ACTION_TRAP2CPU + * - RMA_ACTION_DROP + * - RMA_ACTION_FORWARD_EXCLUDE_CPU + */ +rtk_api_ret_t dal_rtl8367d_trap_rmaAction_get(rtk_trap_type_t type, rtk_trap_rma_action_t *pRma_action) +{ + rtk_api_ret_t retVal; + rtk_uint32 index; + rtk_uint32 regData; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (type >= TRAP_END) + return RT_ERR_INPUT; + + if(NULL == pRma_action) + return RT_ERR_NULL_POINTER; + + if (type >= 0 && type <= TRAP_UNDEF_GARP_2F) + { + if( (type >= 0x4 && type <= 0x7) || (type >= 0x9 && type <= 0x0C) || (0x0F == type)) + index = 0x04; + else if((type >= 0x13 && type <= 0x17) || (0x19 == type) || (type >= 0x1B && type <= 0x1f)) + index = 0x13; + else if(type >= 0x22 && type <= 0x2F) + index = 0x22; + else + index = (rtk_uint32)type; + + if ((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_RMA_CTRL00 + index, RTL8367D_RMA_CTRL00_OPERATION_MASK, ®Data)) != RT_ERR_OK) + return retVal; + } + else if (type == TRAP_CDP) + { + if ((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_RMA_CTRL_CDP, RTL8367D_RMA_CTRL_CDP_OPERATION_MASK, ®Data)) != RT_ERR_OK) + return retVal; + } + else if (type == TRAP_CSSTP) + { + if ((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_RMA_CTRL_CSSTP, RTL8367D_RMA_CTRL_CSSTP_OPERATION_MASK, ®Data)) != RT_ERR_OK) + return retVal; + } + else if (type == TRAP_LLDP) + { + if ((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_RMA_CTRL_LLDP, RTL8367D_RMA_CTRL_LLDP_OPERATION_MASK, ®Data)) != RT_ERR_OK) + return retVal; + } + else + return RT_ERR_INPUT; + + *pRma_action = (rtk_trap_rma_action_t)regData; + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_trap_rmaKeepFormat_set + * Description: + * Set Reserved multicast address keep format configuration. + * Input: + * type - rma type. + * enable - enable keep format. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_ENABLE - Invalid IFG parameter + * Note: + * + * There are 48 types of Reserved Multicast Address frame for application usage. + * They are as following definition. + * - TRAP_BRG_GROUP, + * - TRAP_FD_PAUSE, + * - TRAP_SP_MCAST, + * - TRAP_1X_PAE, + * - TRAP_UNDEF_BRG_04, + * - TRAP_UNDEF_BRG_05, + * - TRAP_UNDEF_BRG_06, + * - TRAP_UNDEF_BRG_07, + * - TRAP_PROVIDER_BRIDGE_GROUP_ADDRESS, + * - TRAP_UNDEF_BRG_09, + * - TRAP_UNDEF_BRG_0A, + * - TRAP_UNDEF_BRG_0B, + * - TRAP_UNDEF_BRG_0C, + * - TRAP_PROVIDER_BRIDGE_GVRP_ADDRESS, + * - TRAP_8021AB, + * - TRAP_UNDEF_BRG_0F, + * - TRAP_BRG_MNGEMENT, + * - TRAP_UNDEFINED_11, + * - TRAP_UNDEFINED_12, + * - TRAP_UNDEFINED_13, + * - TRAP_UNDEFINED_14, + * - TRAP_UNDEFINED_15, + * - TRAP_UNDEFINED_16, + * - TRAP_UNDEFINED_17, + * - TRAP_UNDEFINED_18, + * - TRAP_UNDEFINED_19, + * - TRAP_UNDEFINED_1A, + * - TRAP_UNDEFINED_1B, + * - TRAP_UNDEFINED_1C, + * - TRAP_UNDEFINED_1D, + * - TRAP_UNDEFINED_1E, + * - TRAP_UNDEFINED_1F, + * - TRAP_GMRP, + * - TRAP_GVRP, + * - TRAP_UNDEF_GARP_22, + * - TRAP_UNDEF_GARP_23, + * - TRAP_UNDEF_GARP_24, + * - TRAP_UNDEF_GARP_25, + * - TRAP_UNDEF_GARP_26, + * - TRAP_UNDEF_GARP_27, + * - TRAP_UNDEF_GARP_28, + * - TRAP_UNDEF_GARP_29, + * - TRAP_UNDEF_GARP_2A, + * - TRAP_UNDEF_GARP_2B, + * - TRAP_UNDEF_GARP_2C, + * - TRAP_UNDEF_GARP_2D, + * - TRAP_UNDEF_GARP_2E, + * - TRAP_UNDEF_GARP_2F, + * - TRAP_CDP. + * - TRAP_CSSTP. + * - TRAP_LLDP. + */ +rtk_api_ret_t dal_rtl8367d_trap_rmaKeepFormat_set(rtk_trap_type_t type, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + rtk_uint32 index; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (type >= TRAP_END) + return RT_ERR_INPUT; + + if (enable >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if (type >= 0 && type <= TRAP_UNDEF_GARP_2F) + { + if( (type >= 0x4 && type <= 0x7) || (type >= 0x9 && type <= 0x0C) || (0x0F == type)) + index = 0x04; + else if((type >= 0x13 && type <= 0x17) || (0x19 == type) || (type >= 0x1B && type <= 0x1f)) + index = 0x13; + else if(type >= 0x22 && type <= 0x2F) + index = 0x22; + else + index = (rtk_uint32)type; + + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_RMA_CTRL00 + index, RTL8367D_RMA_CTRL00_KEEP_FORMAT_OFFSET, (enable == ENABLED) ? 1 : 0)) != RT_ERR_OK) + return retVal; + } + else if (type == TRAP_CDP) + { + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_RMA_CTRL_CDP, RTL8367D_RMA_CTRL_CDP_KEEP_FORMAT_OFFSET, (enable == ENABLED) ? 1 : 0)) != RT_ERR_OK) + return retVal; + } + else if (type == TRAP_CSSTP) + { + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_RMA_CTRL_CSSTP, RTL8367D_RMA_CTRL_CSSTP_KEEP_FORMAT_OFFSET,(enable == ENABLED) ? 1 : 0)) != RT_ERR_OK) + return retVal; + } + else if (type == TRAP_LLDP) + { + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_RMA_CTRL_LLDP, RTL8367D_RMA_CTRL_LLDP_KEEP_FORMAT_OFFSET, (enable == ENABLED) ? 1 : 0)) != RT_ERR_OK) + return retVal; + } + else + return RT_ERR_INPUT; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_trap_rmaKeepFormat_get + * Description: + * Get Reserved multicast address action configuration. + * Input: + * type - rma type. + * Output: + * pEnable - keep format status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * There are 48 types of Reserved Multicast Address frame for application usage. + * They are as following definition. + * - TRAP_BRG_GROUP, + * - TRAP_FD_PAUSE, + * - TRAP_SP_MCAST, + * - TRAP_1X_PAE, + * - TRAP_UNDEF_BRG_04, + * - TRAP_UNDEF_BRG_05, + * - TRAP_UNDEF_BRG_06, + * - TRAP_UNDEF_BRG_07, + * - TRAP_PROVIDER_BRIDGE_GROUP_ADDRESS, + * - TRAP_UNDEF_BRG_09, + * - TRAP_UNDEF_BRG_0A, + * - TRAP_UNDEF_BRG_0B, + * - TRAP_UNDEF_BRG_0C, + * - TRAP_PROVIDER_BRIDGE_GVRP_ADDRESS, + * - TRAP_8021AB, + * - TRAP_UNDEF_BRG_0F, + * - TRAP_BRG_MNGEMENT, + * - TRAP_UNDEFINED_11, + * - TRAP_UNDEFINED_12, + * - TRAP_UNDEFINED_13, + * - TRAP_UNDEFINED_14, + * - TRAP_UNDEFINED_15, + * - TRAP_UNDEFINED_16, + * - TRAP_UNDEFINED_17, + * - TRAP_UNDEFINED_18, + * - TRAP_UNDEFINED_19, + * - TRAP_UNDEFINED_1A, + * - TRAP_UNDEFINED_1B, + * - TRAP_UNDEFINED_1C, + * - TRAP_UNDEFINED_1D, + * - TRAP_UNDEFINED_1E, + * - TRAP_UNDEFINED_1F, + * - TRAP_GMRP, + * - TRAP_GVRP, + * - TRAP_UNDEF_GARP_22, + * - TRAP_UNDEF_GARP_23, + * - TRAP_UNDEF_GARP_24, + * - TRAP_UNDEF_GARP_25, + * - TRAP_UNDEF_GARP_26, + * - TRAP_UNDEF_GARP_27, + * - TRAP_UNDEF_GARP_28, + * - TRAP_UNDEF_GARP_29, + * - TRAP_UNDEF_GARP_2A, + * - TRAP_UNDEF_GARP_2B, + * - TRAP_UNDEF_GARP_2C, + * - TRAP_UNDEF_GARP_2D, + * - TRAP_UNDEF_GARP_2E, + * - TRAP_UNDEF_GARP_2F, + * - TRAP_CDP. + * - TRAP_CSSTP. + * - TRAP_LLDP. + */ +rtk_api_ret_t dal_rtl8367d_trap_rmaKeepFormat_get(rtk_trap_type_t type, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + rtk_uint32 index; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (type >= TRAP_END) + return RT_ERR_INPUT; + + if(NULL == pEnable) + return RT_ERR_NULL_POINTER; + + if (type >= 0 && type <= TRAP_UNDEF_GARP_2F) + { + if( (type >= 0x4 && type <= 0x7) || (type >= 0x9 && type <= 0x0C) || (0x0F == type)) + index = 0x04; + else if((type >= 0x13 && type <= 0x17) || (0x19 == type) || (type >= 0x1B && type <= 0x1f)) + index = 0x13; + else if(type >= 0x22 && type <= 0x2F) + index = 0x22; + else + index = (rtk_uint32)type; + + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_RMA_CTRL00 + index, RTL8367D_RMA_CTRL00_KEEP_FORMAT_OFFSET, ®Data)) != RT_ERR_OK) + return retVal; + } + else if (type == TRAP_CDP) + { + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_RMA_CTRL_CDP, RTL8367D_RMA_CTRL_CDP_KEEP_FORMAT_OFFSET, ®Data)) != RT_ERR_OK) + return retVal; + } + else if (type == TRAP_CSSTP) + { + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_RMA_CTRL_CSSTP, RTL8367D_RMA_CTRL_CSSTP_KEEP_FORMAT_OFFSET, ®Data)) != RT_ERR_OK) + return retVal; + } + else if (type == TRAP_LLDP) + { + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_RMA_CTRL_LLDP, RTL8367D_RMA_CTRL_LLDP_KEEP_FORMAT_OFFSET, ®Data)) != RT_ERR_OK) + return retVal; + } + else + return RT_ERR_INPUT; + + *pEnable = (regData == 1) ? ENABLED : DISABLED; + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_trap_portUnknownMacPktAction_set + * Description: + * Set unknown source MAC packet action configuration. + * Input: + * port - Port ID. + * ucast_action - Unknown source MAC action. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid action. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can set unknown unicast packet action configuration. + * The unknown unicast action is as following: + * - UCAST_ACTION_FORWARD_PMASK + * - UCAST_ACTION_DROP + * - UCAST_ACTION_TRAP2CPU + */ +rtk_api_ret_t dal_rtl8367d_trap_portUnknownMacPktAction_set(rtk_port_t port, rtk_trap_ucast_action_t ucast_action) +{ + rtk_api_ret_t retVal; + rtk_uint32 phyPort; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* check port valid */ + RTK_CHK_PORT_VALID(port); + + if (ucast_action >= UCAST_ACTION_FLOODING) + return RT_ERR_INPUT; + + phyPort = rtk_switch_port_L2P_get(port); + if (phyPort == UNDEFINE_PHY_PORT) + return RT_ERR_PORT_ID; + + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_LUT_UNKN_SA_CTRL, RTL8367D_LUT_UNKN_SA_CTRL_PORT0_ACT_MASK << (phyPort * 2), (rtk_uint32)ucast_action)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_trap_portUnknownMacPktAction_get + * Description: + * Get unknown source MAC packet action configuration. + * Input: + * port - Port ID. + * Output: + * pUcast_action - Unknown source MAC action. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Null Pointer. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * + */ +rtk_api_ret_t dal_rtl8367d_trap_portUnknownMacPktAction_get(rtk_port_t port, rtk_trap_ucast_action_t *pUcast_action) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + rtk_uint32 phyPort; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* check port valid */ + RTK_CHK_PORT_VALID(port); + + if(NULL == pUcast_action) + return RT_ERR_NULL_POINTER; + + phyPort = rtk_switch_port_L2P_get(port); + if (phyPort == UNDEFINE_PHY_PORT) + return RT_ERR_PORT_ID; + + if ((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_LUT_UNKN_SA_CTRL, RTL8367D_LUT_UNKN_SA_CTRL_PORT0_ACT_MASK << (phyPort * 2), ®Data)) != RT_ERR_OK) + return retVal; + + switch (regData) + { + case 0: + *pUcast_action = UCAST_ACTION_FORWARD_PMASK; + break; + case 1: + *pUcast_action = UCAST_ACTION_DROP; + break; + case 2: + *pUcast_action = UCAST_ACTION_TRAP2CPU; + break; + default: + return RT_ERR_FAILED; + break; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_trap_portUnmatchMacPktAction_set + * Description: + * Set unmatch source MAC packet action configuration. + * Input: + * port - Port ID. + * ucast_action - Unmatch source MAC action. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid action. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can set unknown unicast packet action configuration. + * The unknown unicast action is as following: + * - UCAST_ACTION_FORWARD_PMASK + * - UCAST_ACTION_DROP + * - UCAST_ACTION_TRAP2CPU + */ +rtk_api_ret_t dal_rtl8367d_trap_portUnmatchMacPktAction_set(rtk_port_t port, rtk_trap_ucast_action_t ucast_action) +{ + rtk_api_ret_t retVal; + rtk_uint32 phyPort; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* check port valid */ + RTK_CHK_PORT_VALID(port); + + if (ucast_action >= UCAST_ACTION_FLOODING) + return RT_ERR_INPUT; + + phyPort = rtk_switch_port_L2P_get(port); + if (phyPort == UNDEFINE_PHY_PORT) + return RT_ERR_PORT_ID; + + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_LUT_UNMATCHED_SA_CTRL, RTL8367D_LUT_UNMATCHED_SA_CTRL_PORT0_ACT_MASK << (phyPort * 2), (rtk_uint32)ucast_action)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_trap_portUnmatchMacPktAction_get + * Description: + * Get unmatch source MAC packet action configuration. + * Input: + * port - Port ID. + * Output: + * pUcast_action - Unmatch source MAC action. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid action. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can set unknown unicast packet action configuration. + * The unknown unicast action is as following: + * - UCAST_ACTION_FORWARD_PMASK + * - UCAST_ACTION_DROP + * - UCAST_ACTION_TRAP2CPU + */ +rtk_api_ret_t dal_rtl8367d_trap_portUnmatchMacPktAction_get(rtk_port_t port, rtk_trap_ucast_action_t *pUcast_action) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + rtk_uint32 phyPort; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* check port valid */ + RTK_CHK_PORT_VALID(port); + + if(NULL == pUcast_action) + return RT_ERR_NULL_POINTER; + + phyPort = rtk_switch_port_L2P_get(port); + if (phyPort == UNDEFINE_PHY_PORT) + return RT_ERR_PORT_ID; + + if ((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_LUT_UNMATCHED_SA_CTRL, RTL8367D_LUT_UNMATCHED_SA_CTRL_PORT0_ACT_MASK << (phyPort * 2), ®Data)) != RT_ERR_OK) + return retVal; + + switch (regData) + { + case 0: + *pUcast_action = UCAST_ACTION_FORWARD_PMASK; + break; + case 1: + *pUcast_action = UCAST_ACTION_DROP; + break; + case 2: + *pUcast_action = UCAST_ACTION_TRAP2CPU; + break; + default: + return RT_ERR_FAILED; + break; + } + + return RT_ERR_OK; +} diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_trap.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_trap.h new file mode 100644 index 00000000..9436da98 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_trap.h @@ -0,0 +1,660 @@ + /* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8367/RTL8367C switch high-level API + * + * Feature : The file includes Trap module high-layer API defination + * + */ + +#ifndef __DAL_RTL8367D_TRAP_H__ +#define __DAL_RTL8367D_TRAP_H__ + +#include + +enum RTL8367D_L2_UNKOWN_MULTICAST_BEHAVE +{ + RTL8367D_L2_UNKOWN_MULTICAST_FLOODING = 0, + RTL8367D_L2_UNKOWN_MULTICAST_DROP, + RTL8367D_L2_UNKOWN_MULTICAST_TRAP, + RTL8367D_L2_UNKOWN_MULTICAST_DROP_EXCLUDE_RMA, + RTL8367D_L2_UNKOWN_MULTICAST_END +}; + +#define RTL8367D_TRAP_PRIMAX 7 + +/* Function Name: + * dal_rtl8367d_trap_unknownUnicastPktAction_set + * Description: + * Set unknown unicast packet action configuration. + * Input: + * port - ingress port ID for unknown unicast packet + * ucast_action - Unknown unicast action. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid action. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can set unknown unicast packet action configuration. + * The unknown unicast action is as following: + * - UCAST_ACTION_FORWARD_PMASK + * - UCAST_ACTION_DROP + * - UCAST_ACTION_TRAP2CPU + * - UCAST_ACTION_FLOODING + */ +extern rtk_api_ret_t dal_rtl8367d_trap_unknownUnicastPktAction_set(rtk_port_t port, rtk_trap_ucast_action_t ucast_action); + +/* Function Name: + * dal_rtl8367d_trap_unknownUnicastPktAction_get + * Description: + * Get unknown unicast packet action configuration. + * Input: + * port - ingress port ID for unknown unicast packet + * Output: + * pUcast_action - Unknown unicast action. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid action. + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * This API can get unknown unicast packet action configuration. + * The unknown unicast action is as following: + * - UCAST_ACTION_FORWARD_PMASK + * - UCAST_ACTION_DROP + * - UCAST_ACTION_TRAP2CPU + * - UCAST_ACTION_FLOODING + */ +extern rtk_api_ret_t dal_rtl8367d_trap_unknownUnicastPktAction_get(rtk_port_t port, rtk_trap_ucast_action_t *pUcast_action); + +/* Function Name: + * dal_rtl8367d_trap_unmatchMacMoving_set + * Description: + * Set unmatch source MAC packet moving state. + * Input: + * port - Port ID. + * enable - ENABLED: allow SA moving, DISABLE: don't allow SA moving. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid action. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + */ +extern rtk_api_ret_t dal_rtl8367d_trap_unmatchMacMoving_set(rtk_port_t port, rtk_enable_t enable); + +/* Function Name: + * dal_rtl8367d_trap_unmatchMacMoving_get + * Description: + * Set unmatch source MAC packet moving state. + * Input: + * port - Port ID. + * Output: + * pEnable - ENABLED: allow SA moving, DISABLE: don't allow SA moving. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid action. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + */ +extern rtk_api_ret_t dal_rtl8367d_trap_unmatchMacMoving_get(rtk_port_t port, rtk_enable_t *pEnable); + +/* Function Name: + * dal_rtl8367d_trap_unknownMcastPktAction_set + * Description: + * Set behavior of unknown multicast + * Input: + * port - Port id. + * type - unknown multicast packet type. + * mcast_action - unknown multicast action. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_NOT_ALLOWED - Invalid action. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * When receives an unknown multicast packet, switch may trap, drop or flood this packet + * (1) The unknown multicast packet type is as following: + * - MCAST_L2 + * - MCAST_IPV4 + * - MCAST_IPV6 + * (2) The unknown multicast action is as following: + * - MCAST_ACTION_FORWARD + * - MCAST_ACTION_DROP + * - MCAST_ACTION_TRAP2CPU + */ +extern rtk_api_ret_t dal_rtl8367d_trap_unknownMcastPktAction_set(rtk_port_t port, rtk_mcast_type_t type, rtk_trap_mcast_action_t mcast_action); + +/* Function Name: + * dal_rtl8367d_trap_unknownMcastPktAction_get + * Description: + * Get behavior of unknown multicast + * Input: + * type - unknown multicast packet type. + * Output: + * pMcast_action - unknown multicast action. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_NOT_ALLOWED - Invalid operation. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * When receives an unknown multicast packet, switch may trap, drop or flood this packet + * (1) The unknown multicast packet type is as following: + * - MCAST_L2 + * - MCAST_IPV4 + * - MCAST_IPV6 + * (2) The unknown multicast action is as following: + * - MCAST_ACTION_FORWARD + * - MCAST_ACTION_DROP + * - MCAST_ACTION_TRAP2CPU + */ +extern rtk_api_ret_t dal_rtl8367d_trap_unknownMcastPktAction_get(rtk_port_t port, rtk_mcast_type_t type, rtk_trap_mcast_action_t *pMcast_action); + +/* Function Name: + * dal_rtl8367d_trap_lldpEnable_set + * Description: + * Set LLDP enable. + * Input: + * enabled - LLDP enable, 0: follow RMA, 1: use LLDP action. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid action. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * - DMAC Assignment + * - 01:80:c2:00:00:0e ethertype = 0x88CC LLDP + * - 01:80:c2:00:00:03 ethertype = 0x88CC + * - 01:80:c2:00:00:00 ethertype = 0x88CC + + */ +extern rtk_api_ret_t dal_rtl8367d_trap_lldpEnable_set(rtk_enable_t enabled); + +/* Function Name: + * dal_rtl8367d_trap_lldpEnable_get + * Description: + * Get LLDP status. + * Input: + * None + * Output: + * pEnabled - LLDP enable, 0: follow RMA, 1: use LLDP action. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * LLDP is as following definition. + * - DMAC Assignment + * - 01:80:c2:00:00:0e ethertype = 0x88CC LLDP + * - 01:80:c2:00:00:03 ethertype = 0x88CC + * - 01:80:c2:00:00:00 ethertype = 0x88CC + */ +extern rtk_api_ret_t dal_rtl8367d_trap_lldpEnable_get(rtk_enable_t *pEnabled); + +/* Function Name: + * dal_rtl8367d_trap_reasonTrapToCpuPriority_set + * Description: + * Set priority value of a packet that trapped to CPU port according to specific reason. + * Input: + * type - reason that trap to CPU port. + * priority - internal priority that is going to be set for specific trap reason. + * Output: + * None. + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - Invalid input parameter + * Note: + * Currently the trap reason that supported are listed as follows: + * - TRAP_REASON_RMA + * - TRAP_REASON_1XUNAUTH + * - TRAP_REASON_VLANSTACK + * - TRAP_REASON_UNKNOWNMC + * - TRAP_REASON_IGMPMLD + */ +extern rtk_api_ret_t dal_rtl8367d_trap_reasonTrapToCpuPriority_set(rtk_trap_reason_type_t type, rtk_pri_t priority); + +/* Function Name: + * dal_rtl8367d_trap_reasonTrapToCpuPriority_get + * Description: + * Get priority value of a packet that trapped to CPU port according to specific reason. + * Input: + * type - reason that trap to CPU port. + * Output: + * pPriority - configured internal priority for such reason. + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - Invalid input parameter + * RT_ERR_NULL_POINTER - NULL pointer + * Note: + * Currently the trap reason that supported are listed as follows: + * - TRAP_REASON_RMA + * - TRAP_REASON_1XUNAUTH + * - TRAP_REASON_VLANSTACK + * - TRAP_REASON_UNKNOWNMC + * - TRAP_REASON_IGMPMLD + */ +extern rtk_api_ret_t dal_rtl8367d_trap_reasonTrapToCpuPriority_get(rtk_trap_reason_type_t type, rtk_pri_t *pPriority); + +/* Function Name: + * dal_rtl8367d_trap_rmaAction_set + * Description: + * Set Reserved multicast address action configuration. + * Input: + * type - rma type. + * rma_action - RMA action. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_ENABLE - Invalid IFG parameter + * Note: + * + * There are 48 types of Reserved Multicast Address frame for application usage. + * (1)They are as following definition. + * - TRAP_BRG_GROUP, + * - TRAP_FD_PAUSE, + * - TRAP_SP_MCAST, + * - TRAP_1X_PAE, + * - TRAP_UNDEF_BRG_04, + * - TRAP_UNDEF_BRG_05, + * - TRAP_UNDEF_BRG_06, + * - TRAP_UNDEF_BRG_07, + * - TRAP_PROVIDER_BRIDGE_GROUP_ADDRESS, + * - TRAP_UNDEF_BRG_09, + * - TRAP_UNDEF_BRG_0A, + * - TRAP_UNDEF_BRG_0B, + * - TRAP_UNDEF_BRG_0C, + * - TRAP_PROVIDER_BRIDGE_GVRP_ADDRESS, + * - TRAP_8021AB, + * - TRAP_UNDEF_BRG_0F, + * - TRAP_BRG_MNGEMENT, + * - TRAP_UNDEFINED_11, + * - TRAP_UNDEFINED_12, + * - TRAP_UNDEFINED_13, + * - TRAP_UNDEFINED_14, + * - TRAP_UNDEFINED_15, + * - TRAP_UNDEFINED_16, + * - TRAP_UNDEFINED_17, + * - TRAP_UNDEFINED_18, + * - TRAP_UNDEFINED_19, + * - TRAP_UNDEFINED_1A, + * - TRAP_UNDEFINED_1B, + * - TRAP_UNDEFINED_1C, + * - TRAP_UNDEFINED_1D, + * - TRAP_UNDEFINED_1E, + * - TRAP_UNDEFINED_1F, + * - TRAP_GMRP, + * - TRAP_GVRP, + * - TRAP_UNDEF_GARP_22, + * - TRAP_UNDEF_GARP_23, + * - TRAP_UNDEF_GARP_24, + * - TRAP_UNDEF_GARP_25, + * - TRAP_UNDEF_GARP_26, + * - TRAP_UNDEF_GARP_27, + * - TRAP_UNDEF_GARP_28, + * - TRAP_UNDEF_GARP_29, + * - TRAP_UNDEF_GARP_2A, + * - TRAP_UNDEF_GARP_2B, + * - TRAP_UNDEF_GARP_2C, + * - TRAP_UNDEF_GARP_2D, + * - TRAP_UNDEF_GARP_2E, + * - TRAP_UNDEF_GARP_2F, + * - TRAP_CDP. + * - TRAP_CSSTP. + * - TRAP_LLDP. + * (2) The RMA action is as following: + * - RMA_ACTION_FORWARD + * - RMA_ACTION_TRAP2CPU + * - RMA_ACTION_DROP + * - RMA_ACTION_FORWARD_EXCLUDE_CPU + */ +extern rtk_api_ret_t dal_rtl8367d_trap_rmaAction_set(rtk_trap_type_t type, rtk_trap_rma_action_t rma_action); + +/* Function Name: + * dal_rtl8367d_trap_rmaAction_get + * Description: + * Get Reserved multicast address action configuration. + * Input: + * type - rma type. + * Output: + * pRma_action - RMA action. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * There are 48 types of Reserved Multicast Address frame for application usage. + * (1)They are as following definition. + * - TRAP_BRG_GROUP, + * - TRAP_FD_PAUSE, + * - TRAP_SP_MCAST, + * - TRAP_1X_PAE, + * - TRAP_UNDEF_BRG_04, + * - TRAP_UNDEF_BRG_05, + * - TRAP_UNDEF_BRG_06, + * - TRAP_UNDEF_BRG_07, + * - TRAP_PROVIDER_BRIDGE_GROUP_ADDRESS, + * - TRAP_UNDEF_BRG_09, + * - TRAP_UNDEF_BRG_0A, + * - TRAP_UNDEF_BRG_0B, + * - TRAP_UNDEF_BRG_0C, + * - TRAP_PROVIDER_BRIDGE_GVRP_ADDRESS, + * - TRAP_8021AB, + * - TRAP_UNDEF_BRG_0F, + * - TRAP_BRG_MNGEMENT, + * - TRAP_UNDEFINED_11, + * - TRAP_UNDEFINED_12, + * - TRAP_UNDEFINED_13, + * - TRAP_UNDEFINED_14, + * - TRAP_UNDEFINED_15, + * - TRAP_UNDEFINED_16, + * - TRAP_UNDEFINED_17, + * - TRAP_UNDEFINED_18, + * - TRAP_UNDEFINED_19, + * - TRAP_UNDEFINED_1A, + * - TRAP_UNDEFINED_1B, + * - TRAP_UNDEFINED_1C, + * - TRAP_UNDEFINED_1D, + * - TRAP_UNDEFINED_1E, + * - TRAP_UNDEFINED_1F, + * - TRAP_GMRP, + * - TRAP_GVRP, + * - TRAP_UNDEF_GARP_22, + * - TRAP_UNDEF_GARP_23, + * - TRAP_UNDEF_GARP_24, + * - TRAP_UNDEF_GARP_25, + * - TRAP_UNDEF_GARP_26, + * - TRAP_UNDEF_GARP_27, + * - TRAP_UNDEF_GARP_28, + * - TRAP_UNDEF_GARP_29, + * - TRAP_UNDEF_GARP_2A, + * - TRAP_UNDEF_GARP_2B, + * - TRAP_UNDEF_GARP_2C, + * - TRAP_UNDEF_GARP_2D, + * - TRAP_UNDEF_GARP_2E, + * - TRAP_UNDEF_GARP_2F, + * - TRAP_CDP. + * - TRAP_CSSTP. + * - TRAP_LLDP. + * (2) The RMA action is as following: + * - RMA_ACTION_FORWARD + * - RMA_ACTION_TRAP2CPU + * - RMA_ACTION_DROP + * - RMA_ACTION_FORWARD_EXCLUDE_CPU + */ +extern rtk_api_ret_t dal_rtl8367d_trap_rmaAction_get(rtk_trap_type_t type, rtk_trap_rma_action_t *pRma_action); + +/* Function Name: + * dal_rtl8367d_trap_rmaKeepFormat_set + * Description: + * Set Reserved multicast address keep format configuration. + * Input: + * type - rma type. + * enable - enable keep format. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_ENABLE - Invalid IFG parameter + * Note: + * + * There are 48 types of Reserved Multicast Address frame for application usage. + * They are as following definition. + * - TRAP_BRG_GROUP, + * - TRAP_FD_PAUSE, + * - TRAP_SP_MCAST, + * - TRAP_1X_PAE, + * - TRAP_UNDEF_BRG_04, + * - TRAP_UNDEF_BRG_05, + * - TRAP_UNDEF_BRG_06, + * - TRAP_UNDEF_BRG_07, + * - TRAP_PROVIDER_BRIDGE_GROUP_ADDRESS, + * - TRAP_UNDEF_BRG_09, + * - TRAP_UNDEF_BRG_0A, + * - TRAP_UNDEF_BRG_0B, + * - TRAP_UNDEF_BRG_0C, + * - TRAP_PROVIDER_BRIDGE_GVRP_ADDRESS, + * - TRAP_8021AB, + * - TRAP_UNDEF_BRG_0F, + * - TRAP_BRG_MNGEMENT, + * - TRAP_UNDEFINED_11, + * - TRAP_UNDEFINED_12, + * - TRAP_UNDEFINED_13, + * - TRAP_UNDEFINED_14, + * - TRAP_UNDEFINED_15, + * - TRAP_UNDEFINED_16, + * - TRAP_UNDEFINED_17, + * - TRAP_UNDEFINED_18, + * - TRAP_UNDEFINED_19, + * - TRAP_UNDEFINED_1A, + * - TRAP_UNDEFINED_1B, + * - TRAP_UNDEFINED_1C, + * - TRAP_UNDEFINED_1D, + * - TRAP_UNDEFINED_1E, + * - TRAP_UNDEFINED_1F, + * - TRAP_GMRP, + * - TRAP_GVRP, + * - TRAP_UNDEF_GARP_22, + * - TRAP_UNDEF_GARP_23, + * - TRAP_UNDEF_GARP_24, + * - TRAP_UNDEF_GARP_25, + * - TRAP_UNDEF_GARP_26, + * - TRAP_UNDEF_GARP_27, + * - TRAP_UNDEF_GARP_28, + * - TRAP_UNDEF_GARP_29, + * - TRAP_UNDEF_GARP_2A, + * - TRAP_UNDEF_GARP_2B, + * - TRAP_UNDEF_GARP_2C, + * - TRAP_UNDEF_GARP_2D, + * - TRAP_UNDEF_GARP_2E, + * - TRAP_UNDEF_GARP_2F, + * - TRAP_CDP. + * - TRAP_CSSTP. + * - TRAP_LLDP. + */ +extern rtk_api_ret_t dal_rtl8367d_trap_rmaKeepFormat_set(rtk_trap_type_t type, rtk_enable_t enable); + +/* Function Name: + * dal_rtl8367d_trap_rmaKeepFormat_get + * Description: + * Get Reserved multicast address action configuration. + * Input: + * type - rma type. + * Output: + * pEnable - keep format status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * There are 48 types of Reserved Multicast Address frame for application usage. + * They are as following definition. + * - TRAP_BRG_GROUP, + * - TRAP_FD_PAUSE, + * - TRAP_SP_MCAST, + * - TRAP_1X_PAE, + * - TRAP_UNDEF_BRG_04, + * - TRAP_UNDEF_BRG_05, + * - TRAP_UNDEF_BRG_06, + * - TRAP_UNDEF_BRG_07, + * - TRAP_PROVIDER_BRIDGE_GROUP_ADDRESS, + * - TRAP_UNDEF_BRG_09, + * - TRAP_UNDEF_BRG_0A, + * - TRAP_UNDEF_BRG_0B, + * - TRAP_UNDEF_BRG_0C, + * - TRAP_PROVIDER_BRIDGE_GVRP_ADDRESS, + * - TRAP_8021AB, + * - TRAP_UNDEF_BRG_0F, + * - TRAP_BRG_MNGEMENT, + * - TRAP_UNDEFINED_11, + * - TRAP_UNDEFINED_12, + * - TRAP_UNDEFINED_13, + * - TRAP_UNDEFINED_14, + * - TRAP_UNDEFINED_15, + * - TRAP_UNDEFINED_16, + * - TRAP_UNDEFINED_17, + * - TRAP_UNDEFINED_18, + * - TRAP_UNDEFINED_19, + * - TRAP_UNDEFINED_1A, + * - TRAP_UNDEFINED_1B, + * - TRAP_UNDEFINED_1C, + * - TRAP_UNDEFINED_1D, + * - TRAP_UNDEFINED_1E, + * - TRAP_UNDEFINED_1F, + * - TRAP_GMRP, + * - TRAP_GVRP, + * - TRAP_UNDEF_GARP_22, + * - TRAP_UNDEF_GARP_23, + * - TRAP_UNDEF_GARP_24, + * - TRAP_UNDEF_GARP_25, + * - TRAP_UNDEF_GARP_26, + * - TRAP_UNDEF_GARP_27, + * - TRAP_UNDEF_GARP_28, + * - TRAP_UNDEF_GARP_29, + * - TRAP_UNDEF_GARP_2A, + * - TRAP_UNDEF_GARP_2B, + * - TRAP_UNDEF_GARP_2C, + * - TRAP_UNDEF_GARP_2D, + * - TRAP_UNDEF_GARP_2E, + * - TRAP_UNDEF_GARP_2F, + * - TRAP_CDP. + * - TRAP_CSSTP. + * - TRAP_LLDP. + */ +extern rtk_api_ret_t dal_rtl8367d_trap_rmaKeepFormat_get(rtk_trap_type_t type, rtk_enable_t *pEnable); + +/* Function Name: + * dal_rtl8367d_trap_portUnknownMacPktAction_set + * Description: + * Set unknown source MAC packet action configuration. + * Input: + * port - Port ID. + * ucast_action - Unknown source MAC action. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid action. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can set unknown unicast packet action configuration. + * The unknown unicast action is as following: + * - UCAST_ACTION_FORWARD_PMASK + * - UCAST_ACTION_DROP + * - UCAST_ACTION_TRAP2CPU + */ +extern rtk_api_ret_t dal_rtl8367d_trap_portUnknownMacPktAction_set(rtk_port_t port, rtk_trap_ucast_action_t ucast_action); + +/* Function Name: + * dal_rtl8367d_trap_portUnknownMacPktAction_get + * Description: + * Get unknown source MAC packet action configuration. + * Input: + * port - Port ID. + * Output: + * pUcast_action - Unknown source MAC action. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Null Pointer. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367d_trap_portUnknownMacPktAction_get(rtk_port_t port, rtk_trap_ucast_action_t *pUcast_action); + +/* Function Name: + * dal_rtl8367d_trap_portUnmatchMacPktAction_set + * Description: + * Set unmatch source MAC packet action configuration. + * Input: + * port - Port ID. + * ucast_action - Unmatch source MAC action. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid action. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can set unknown unicast packet action configuration. + * The unknown unicast action is as following: + * - UCAST_ACTION_FORWARD_PMASK + * - UCAST_ACTION_DROP + * - UCAST_ACTION_TRAP2CPU + */ +extern rtk_api_ret_t dal_rtl8367d_trap_portUnmatchMacPktAction_set(rtk_port_t port, rtk_trap_ucast_action_t ucast_action); + +/* Function Name: + * dal_rtl8367d_trap_portUnmatchMacPktAction_get + * Description: + * Get unmatch source MAC packet action configuration. + * Input: + * port - Port ID. + * Output: + * pUcast_action - Unmatch source MAC action. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid action. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can set unknown unicast packet action configuration. + * The unknown unicast action is as following: + * - UCAST_ACTION_FORWARD_PMASK + * - UCAST_ACTION_DROP + * - UCAST_ACTION_TRAP2CPU + */ +extern rtk_api_ret_t dal_rtl8367d_trap_portUnmatchMacPktAction_get(rtk_port_t port, rtk_trap_ucast_action_t *pUcast_action); + +#endif /* __DAL_RTL8367D_TRAP_H__ */ + + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_trunk.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_trunk.c new file mode 100644 index 00000000..d88b30ec --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_trunk.c @@ -0,0 +1,560 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8367C + * Feature : Here is a list of all functions and variables in Trunk module. + * + */ + +#include +#include +#include +#include +#include + +/* Function Name: + * dal_rtl8367d_trunk_port_set + * Description: + * Set trunking group available port mask + * Input: + * trk_gid - trunk group id + * pTrunk_member_portmask - Logic trunking member port mask + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_LA_TRUNK_ID - Invalid trunking group + * RT_ERR_PORT_MASK - Invalid portmask. + * Note: + * The API can set port trunking group port mask. Each port trunking group has max 4 ports. + * If enabled port mask has less than 2 ports available setting, then this trunking group function is disabled. + */ +rtk_api_ret_t dal_rtl8367d_trunk_port_set(rtk_trunk_group_t trk_gid, rtk_portmask_t *pTrunk_member_portmask) +{ + rtk_api_ret_t retVal; + rtk_uint32 pmsk, gmask; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Trunk Group Valid */ + RTK_CHK_TRUNK_GROUP_VALID(trk_gid); + + if(NULL == pTrunk_member_portmask) + return RT_ERR_NULL_POINTER; + + RTK_CHK_PORTMASK_VALID(pTrunk_member_portmask); + + if((retVal = rtk_switch_portmask_L2P_get(pTrunk_member_portmask, &pmsk)) != RT_ERR_OK) + return retVal; + + gmask = RTL8367D_PORT_TRUNK_GROUP0_MASK_MASK << (trk_gid * 4); + + if ((pmsk | gmask) != gmask) + return RT_ERR_PORT_MASK; + + pmsk = (pmsk & gmask) >> (trk_gid * 4); + + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_PORT_TRUNK_GROUP_MASK, gmask, pmsk)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_trunk_port_get + * Description: + * Get trunking group available port mask + * Input: + * trk_gid - trunk group id + * Output: + * pTrunk_member_portmask - Logic trunking member port mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_LA_TRUNK_ID - Invalid trunking group + * Note: + * The API can get 2 port trunking group. + */ +rtk_api_ret_t dal_rtl8367d_trunk_port_get(rtk_trunk_group_t trk_gid, rtk_portmask_t *pTrunk_member_portmask) +{ + rtk_api_ret_t retVal; + rtk_uint32 pmsk, gmask; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Trunk Group Valid */ + RTK_CHK_TRUNK_GROUP_VALID(trk_gid); + + gmask = RTL8367D_PORT_TRUNK_GROUP0_MASK_MASK << (trk_gid * 4); + if ((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_PORT_TRUNK_GROUP_MASK, gmask, &pmsk)) != RT_ERR_OK) + return retVal; + + pmsk = pmsk << (trk_gid * 4); + + if((retVal = rtk_switch_portmask_P2L_get(pmsk, pTrunk_member_portmask)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_trunk_distributionAlgorithm_set + * Description: + * Set port trunking hash select sources + * Input: + * trk_gid - trunk group id + * algo_bitmask - Bitmask of the distribution algorithm + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_LA_TRUNK_ID - Invalid trunking group + * RT_ERR_LA_HASHMASK - Hash algorithm selection error. + * RT_ERR_PORT_MASK - Invalid portmask. + * Note: + * The API can set port trunking hash algorithm sources. + * 7 bits mask for link aggregation group0 hash parameter selection {DIP, SIP, DMAC, SMAC, SPA} + * - 0b0000001: SPA + * - 0b0000010: SMAC + * - 0b0000100: DMAC + * - 0b0001000: SIP + * - 0b0010000: DIP + * - 0b0100000: TCP/UDP Source Port + * - 0b1000000: TCP/UDP Destination Port + * Example: + * - 0b0000011: SMAC & SPA + * - Note that it could be an arbitrary combination or independent set + */ +rtk_api_ret_t dal_rtl8367d_trunk_distributionAlgorithm_set(rtk_trunk_group_t trk_gid, rtk_uint32 algo_bitmask) +{ + rtk_api_ret_t retVal; + rtk_uint32 hashmask; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Trunk Group Valid */ + RTK_CHK_TRUNK_GROUP_VALID(trk_gid); + + if (algo_bitmask >= 128) + return RT_ERR_LA_HASHMASK; + + hashmask = RTL8367D_GROUP0_SPA_HASH_MASK | RTL8367D_GROUP0_SMAC_HASH_MASK | RTL8367D_GROUP0_DMAC_HASH_MASK | RTL8367D_GROUP0_SIP_HASH_MASK | RTL8367D_GROUP0_DIP_HASH_MASK | RTL8367D_GROUP0_SPORT_HASH_MASK | RTL8367D_GROUP0_DPORT_HASH_MASK; + + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_PORT_TRUNK_CTRL, hashmask<<(RTL8367D_GROUP1_SPA_HASH_OFFSET*trk_gid), algo_bitmask)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_trunk_distributionAlgorithm_get + * Description: + * Get port trunking hash select sources + * Input: + * trk_gid - trunk group id + * Output: + * pAlgo_bitmask - Bitmask of the distribution algorithm + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_LA_TRUNK_ID - Invalid trunking group + * Note: + * The API can get port trunking hash algorithm sources. + */ +rtk_api_ret_t dal_rtl8367d_trunk_distributionAlgorithm_get(rtk_trunk_group_t trk_gid, rtk_uint32 *pAlgo_bitmask) +{ + rtk_api_ret_t retVal; + rtk_uint32 hashmask; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Trunk Group Valid */ + RTK_CHK_TRUNK_GROUP_VALID(trk_gid); + + if(NULL == pAlgo_bitmask) + return RT_ERR_NULL_POINTER; + + hashmask = RTL8367D_GROUP0_SPA_HASH_MASK | RTL8367D_GROUP0_SMAC_HASH_MASK | RTL8367D_GROUP0_DMAC_HASH_MASK | RTL8367D_GROUP0_SIP_HASH_MASK | RTL8367D_GROUP0_DIP_HASH_MASK | RTL8367D_GROUP0_SPORT_HASH_MASK | RTL8367D_GROUP0_DPORT_HASH_MASK; + + if ((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_PORT_TRUNK_CTRL, hashmask<<(RTL8367D_GROUP1_SPA_HASH_OFFSET*trk_gid), pAlgo_bitmask)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_trunk_trafficSeparate_set + * Description: + * Set the traffic separation setting of a trunk group from the specified device. + * Input: + * trk_gid - trunk group id + * separateType - traffic separation setting + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_LA_TRUNK_ID - invalid trunk ID + * RT_ERR_LA_HASHMASK - invalid hash mask + * Note: + * SEPARATE_NONE: disable traffic separation + * SEPARATE_FLOOD: trunk MSB link up port is dedicated to TX flooding (L2 lookup miss) traffic + */ +rtk_api_ret_t dal_rtl8367d_trunk_trafficSeparate_set(rtk_trunk_group_t trk_gid, rtk_trunk_separateType_t separateType) +{ + rtk_api_ret_t retVal; + rtk_uint32 enabled; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (trk_gid != RTK_WHOLE_SYSTEM) + return RT_ERR_LA_TRUNK_ID; + + if(separateType >= SEPARATE_END) + return RT_ERR_INPUT; + + enabled = (separateType == SEPARATE_FLOOD) ? ENABLED : DISABLED; + + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_PORT_TRUNK_CTRL, RTL8367D_PORT_TRUNK_FLOOD_OFFSET, enabled)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_trunk_trafficSeparate_get + * Description: + * Get the traffic separation setting of a trunk group from the specified device. + * Input: + * trk_gid - trunk group id + * Output: + * pSeparateType - pointer separated traffic type + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_LA_TRUNK_ID - invalid trunk ID + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * SEPARATE_NONE: disable traffic separation + * SEPARATE_FLOOD: trunk MSB link up port is dedicated to TX flooding (L2 lookup miss) traffic + */ +rtk_api_ret_t dal_rtl8367d_trunk_trafficSeparate_get(rtk_trunk_group_t trk_gid, rtk_trunk_separateType_t *pSeparateType) +{ + rtk_api_ret_t retVal; + rtk_uint32 enabled; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (trk_gid != RTK_WHOLE_SYSTEM) + return RT_ERR_LA_TRUNK_ID; + + if(NULL == pSeparateType) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_PORT_TRUNK_CTRL, RTL8367D_PORT_TRUNK_FLOOD_OFFSET, &enabled)) != RT_ERR_OK) + return retVal; + + *pSeparateType = (enabled == ENABLED) ? SEPARATE_FLOOD : SEPARATE_NONE; + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_trunk_mode_set + * Description: + * Set the trunk mode to the specified device. + * Input: + * mode - trunk mode + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT - invalid input parameter + * Note: + * The enum of the trunk mode as following + * - TRUNK_MODE_NORMAL + * - TRUNK_MODE_DUMB + */ +rtk_api_ret_t dal_rtl8367d_trunk_mode_set(rtk_trunk_mode_t mode) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(mode >= TRUNK_MODE_END) + return RT_ERR_INPUT; + + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_PORT_TRUNK_CTRL, RTL8367D_PORT_TRUNK_DUMB_OFFSET, mode)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_trunk_mode_get + * Description: + * Get the trunk mode from the specified device. + * Input: + * None + * Output: + * pMode - pointer buffer of trunk mode + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * The enum of the trunk mode as following + * - TRUNK_MODE_NORMAL + * - TRUNK_MODE_DUMB + */ +rtk_api_ret_t dal_rtl8367d_trunk_mode_get(rtk_trunk_mode_t *pMode) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pMode) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_PORT_TRUNK_CTRL, RTL8367D_PORT_TRUNK_DUMB_OFFSET, pMode)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_trunk_trafficPause_set + * Description: + * Set the traffic pause setting of a trunk group. + * Input: + * trk_gid - trunk group id + * enable - traffic pause state + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_LA_TRUNK_ID - invalid trunk ID + * Note: + * None. + */ +rtk_api_ret_t dal_rtl8367d_trunk_trafficPause_set(rtk_trunk_group_t trk_gid, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Trunk Group Valid */ + RTK_CHK_TRUNK_GROUP_VALID(trk_gid); + + if(enable >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_PORT_TRUNK_DROP_CTRL, RTL8367D_PORT_TRUNK_DROP_CTRL_OFFSET, ENABLED)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_PORT_TRUNK_FLOWCTRL, (RTL8367D_EN_FLOWCTRL_TG0_OFFSET + trk_gid), enable)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_trunk_trafficPause_get + * Description: + * Get the traffic pause setting of a trunk group. + * Input: + * trk_gid - trunk group id + * Output: + * pEnable - pointer of traffic pause state. + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_LA_TRUNK_ID - invalid trunk ID + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None. + */ +rtk_api_ret_t dal_rtl8367d_trunk_trafficPause_get(rtk_trunk_group_t trk_gid, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Trunk Group Valid */ + RTK_CHK_TRUNK_GROUP_VALID(trk_gid); + + if(NULL == pEnable) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_PORT_TRUNK_FLOWCTRL, (RTL8367D_EN_FLOWCTRL_TG0_OFFSET + trk_gid), pEnable)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_trunk_hashMappingTable_set + * Description: + * Set hash value to port array in the trunk group id from the specified device. + * Input: + * trk_gid - trunk group id + * pHash2Port_array - ports associate with the hash value + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_LA_TRUNK_ID - invalid trunk ID + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * RT_ERR_LA_TRUNK_NOT_EXIST - the trunk doesn't exist + * RT_ERR_LA_NOT_MEMBER_PORT - the port is not a member port of the trunk + * RT_ERR_LA_CPUPORT - CPU port can not be aggregated port + * Note: + * Trunk group 0 & 1 shares the same hash mapping table. + * Trunk group 2 uses a independent table. + */ +rtk_api_ret_t dal_rtl8367d_trunk_hashMappingTable_set(rtk_trunk_group_t trk_gid, rtk_trunk_hashVal2Port_t *pHash2Port_array) +{ + rtk_api_ret_t retVal; + rtk_uint32 hashValue; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Trunk Group Valid */ + RTK_CHK_TRUNK_GROUP_VALID(trk_gid); + + if(NULL == pHash2Port_array) + return RT_ERR_NULL_POINTER; + + for(hashValue = 0; hashValue < 8; hashValue++) + { + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_PORT_TRUNK_HASH_MAPPING_CTRL0, RTL8367D_HASH0_MASK<<(hashValue*2), pHash2Port_array->value[hashValue])) != RT_ERR_OK) + return retVal; + } + + for(hashValue = 8; hashValue < RTK_MAX_NUM_OF_TRUNK_HASH_VAL; hashValue++) + { + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_PORT_TRUNK_HASH_MAPPING_CTRL1, RTL8367D_HASH8_MASK<<((hashValue-8)*2), pHash2Port_array->value[hashValue])) != RT_ERR_OK) + return retVal; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_trunk_hashMappingTable_get + * Description: + * Get hash value to port array in the trunk group id from the specified device. + * Input: + * trk_gid - trunk group id + * Output: + * pHash2Port_array - pointer buffer of ports associate with the hash value + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_LA_TRUNK_ID - invalid trunk ID + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * Trunk group 0 & 1 shares the same hash mapping table. + * Trunk group 2 uses a independent table. + */ +rtk_api_ret_t dal_rtl8367d_trunk_hashMappingTable_get(rtk_trunk_group_t trk_gid, rtk_trunk_hashVal2Port_t *pHash2Port_array) +{ + rtk_api_ret_t retVal; + rtk_uint32 hashValue; + rtk_uint32 hashPort; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Trunk Group Valid */ + RTK_CHK_TRUNK_GROUP_VALID(trk_gid); + + if(NULL == pHash2Port_array) + return RT_ERR_NULL_POINTER; + + for(hashValue = 0; hashValue < 8; hashValue++) + { + if ((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_PORT_TRUNK_HASH_MAPPING_CTRL0, RTL8367D_HASH0_MASK<<(hashValue*2), &hashPort)) != RT_ERR_OK) + return retVal; + pHash2Port_array->value[hashValue] = hashPort; + } + + for(hashValue = 8; hashValue < RTK_MAX_NUM_OF_TRUNK_HASH_VAL; hashValue++) + { + if ((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_PORT_TRUNK_HASH_MAPPING_CTRL1, RTL8367D_HASH8_MASK<<((hashValue-8)*2), &hashPort)) != RT_ERR_OK) + return retVal; + pHash2Port_array->value[hashValue] = hashPort; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_trunk_portQueueEmpty_get + * Description: + * Get the port mask which all queues are empty. + * Input: + * None. + * Output: + * pEmpty_portmask - pointer empty port mask + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None. + */ +rtk_api_ret_t dal_rtl8367d_trunk_portQueueEmpty_get(rtk_portmask_t *pEmpty_portmask) +{ + rtk_api_ret_t retVal; + rtk_uint32 pmask; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pEmpty_portmask) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367d_getAsicReg(RTL8367D_REG_PORT_QEMPTY, &pmask)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtk_switch_portmask_P2L_get(pmask, pEmpty_portmask)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_trunk.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_trunk.h new file mode 100644 index 00000000..2b8c4b19 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_trunk.h @@ -0,0 +1,289 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8367/RTL8367C switch high-level API + * + * Feature : The file includes Trunk module high-layer TRUNK defination + * + */ + +#ifndef __DAL_RTL8367D_TRUNK_H__ +#define __DAL_RTL8367D_TRUNK_H__ + +#include + +/* Function Name: + * dal_rtl8367d_trunk_port_set + * Description: + * Set trunking group available port mask + * Input: + * trk_gid - trunk group id + * pTrunk_member_portmask - Logic trunking member port mask + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_LA_TRUNK_ID - Invalid trunking group + * RT_ERR_PORT_MASK - Invalid portmask. + * Note: + * The API can set port trunking group port mask. Each port trunking group has max 4 ports. + * If enabled port mask has less than 2 ports available setting, then this trunking group function is disabled. + */ +extern rtk_api_ret_t dal_rtl8367d_trunk_port_set(rtk_trunk_group_t trk_gid, rtk_portmask_t *pTrunk_member_portmask); + +/* Function Name: + * dal_rtl8367d_trunk_port_get + * Description: + * Get trunking group available port mask + * Input: + * trk_gid - trunk group id + * Output: + * pTrunk_member_portmask - Logic trunking member port mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_LA_TRUNK_ID - Invalid trunking group + * Note: + * The API can get 2 port trunking group. + */ +extern rtk_api_ret_t dal_rtl8367d_trunk_port_get(rtk_trunk_group_t trk_gid, rtk_portmask_t *pTrunk_member_portmask); + +/* Function Name: + * dal_rtl8367d_trunk_distributionAlgorithm_set + * Description: + * Set port trunking hash select sources + * Input: + * trk_gid - trunk group id + * algo_bitmask - Bitmask of the distribution algorithm + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_LA_TRUNK_ID - Invalid trunking group + * RT_ERR_LA_HASHMASK - Hash algorithm selection error. + * RT_ERR_PORT_MASK - Invalid portmask. + * Note: + * The API can set port trunking hash algorithm sources. + * 7 bits mask for link aggregation group0 hash parameter selection {DIP, SIP, DMAC, SMAC, SPA} + * - 0b0000001: SPA + * - 0b0000010: SMAC + * - 0b0000100: DMAC + * - 0b0001000: SIP + * - 0b0010000: DIP + * - 0b0100000: TCP/UDP Source Port + * - 0b1000000: TCP/UDP Destination Port + * Example: + * - 0b0000011: SMAC & SPA + * - Note that it could be an arbitrary combination or independent set + */ +extern rtk_api_ret_t dal_rtl8367d_trunk_distributionAlgorithm_set(rtk_trunk_group_t trk_gid, rtk_uint32 algo_bitmask); + +/* Function Name: + * dal_rtl8367d_trunk_distributionAlgorithm_get + * Description: + * Get port trunking hash select sources + * Input: + * trk_gid - trunk group id + * Output: + * pAlgo_bitmask - Bitmask of the distribution algorithm + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_LA_TRUNK_ID - Invalid trunking group + * Note: + * The API can get port trunking hash algorithm sources. + */ +extern rtk_api_ret_t dal_rtl8367d_trunk_distributionAlgorithm_get(rtk_trunk_group_t trk_gid, rtk_uint32 *pAlgo_bitmask); + +/* Function Name: + * dal_rtl8367d_trunk_trafficSeparate_set + * Description: + * Set the traffic separation setting of a trunk group from the specified device. + * Input: + * trk_gid - trunk group id + * separateType - traffic separation setting + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_LA_TRUNK_ID - invalid trunk ID + * RT_ERR_LA_HASHMASK - invalid hash mask + * Note: + * SEPARATE_NONE: disable traffic separation + * SEPARATE_FLOOD: trunk MSB link up port is dedicated to TX flooding (L2 lookup miss) traffic + */ +extern rtk_api_ret_t dal_rtl8367d_trunk_trafficSeparate_set(rtk_trunk_group_t trk_gid, rtk_trunk_separateType_t separateType); + +/* Function Name: + * dal_rtl8367d_trunk_trafficSeparate_get + * Description: + * Get the traffic separation setting of a trunk group from the specified device. + * Input: + * trk_gid - trunk group id + * Output: + * pSeparateType - pointer separated traffic type + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_LA_TRUNK_ID - invalid trunk ID + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * SEPARATE_NONE: disable traffic separation + * SEPARATE_FLOOD: trunk MSB link up port is dedicated to TX flooding (L2 lookup miss) traffic + */ +extern rtk_api_ret_t dal_rtl8367d_trunk_trafficSeparate_get(rtk_trunk_group_t trk_gid, rtk_trunk_separateType_t *pSeparateType); + + +/* Function Name: + * dal_rtl8367d_trunk_mode_set + * Description: + * Set the trunk mode to the specified device. + * Input: + * mode - trunk mode + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT - invalid input parameter + * Note: + * The enum of the trunk mode as following + * - TRUNK_MODE_NORMAL + * - TRUNK_MODE_DUMB + */ +extern rtk_api_ret_t dal_rtl8367d_trunk_mode_set(rtk_trunk_mode_t mode); + +/* Function Name: + * dal_rtl8367d_trunk_mode_get + * Description: + * Get the trunk mode from the specified device. + * Input: + * None + * Output: + * pMode - pointer buffer of trunk mode + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * The enum of the trunk mode as following + * - TRUNK_MODE_NORMAL + * - TRUNK_MODE_DUMB + */ +extern rtk_api_ret_t dal_rtl8367d_trunk_mode_get(rtk_trunk_mode_t *pMode); + +/* Function Name: + * dal_rtl8367d_trunk_trafficPause_set + * Description: + * Set the traffic pause setting of a trunk group. + * Input: + * trk_gid - trunk group id + * enable - traffic pause state + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_LA_TRUNK_ID - invalid trunk ID + * Note: + * None. + */ +extern rtk_api_ret_t dal_rtl8367d_trunk_trafficPause_set(rtk_trunk_group_t trk_gid, rtk_enable_t enable); + +/* Function Name: + * dal_rtl8367d_trunk_trafficPause_get + * Description: + * Get the traffic pause setting of a trunk group. + * Input: + * trk_gid - trunk group id + * Output: + * pEnable - pointer of traffic pause state. + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_LA_TRUNK_ID - invalid trunk ID + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None. + */ +extern rtk_api_ret_t dal_rtl8367d_trunk_trafficPause_get(rtk_trunk_group_t trk_gid, rtk_enable_t *pEnable); + +/* Function Name: + * dal_rtl8367d_trunk_hashMappingTable_set + * Description: + * Set hash value to port array in the trunk group id from the specified device. + * Input: + * trk_gid - trunk group id + * pHash2Port_array - ports associate with the hash value + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_LA_TRUNK_ID - invalid trunk ID + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * RT_ERR_LA_TRUNK_NOT_EXIST - the trunk doesn't exist + * RT_ERR_LA_NOT_MEMBER_PORT - the port is not a member port of the trunk + * RT_ERR_LA_CPUPORT - CPU port can not be aggregated port + * Note: + * Trunk group 0 & 1 shares the same hash mapping table. + * Trunk group 2 uses a independent table. + */ +extern rtk_api_ret_t dal_rtl8367d_trunk_hashMappingTable_set(rtk_trunk_group_t trk_gid, rtk_trunk_hashVal2Port_t *pHash2Port_array); + +/* Function Name: + * dal_rtl8367d_trunk_hashMappingTable_get + * Description: + * Get hash value to port array in the trunk group id from the specified device. + * Input: + * trk_gid - trunk group id + * Output: + * pHash2Port_array - pointer buffer of ports associate with the hash value + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_LA_TRUNK_ID - invalid trunk ID + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * Trunk group 0 & 1 shares the same hash mapping table. + * Trunk group 2 uses a independent table. + */ +extern rtk_api_ret_t dal_rtl8367d_trunk_hashMappingTable_get(rtk_trunk_group_t trk_gid, rtk_trunk_hashVal2Port_t *pHash2Port_array); + +/* Function Name: + * dal_rtl8367d_trunk_portQueueEmpty_get + * Description: + * Get the port mask which all queues are empty. + * Input: + * None. + * Output: + * pEmpty_portmask - pointer empty port mask + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None. + */ +extern rtk_api_ret_t dal_rtl8367d_trunk_portQueueEmpty_get(rtk_portmask_t *pEmpty_portmask); + +#endif /* __DAL_RTL8367D_TRUNK_H__ */ diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_vlan.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_vlan.c new file mode 100644 index 00000000..e16f94b6 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_vlan.c @@ -0,0 +1,1429 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8367D + * Feature : Here is a list of all functions and variables in VLAN module. + * + */ + +#include +#include +#include +#include +#include + + +#if defined(CONFIG_RTL8367D_ASICDRV_TEST) +dal_rtl8367d_user_vlan4kentry Rtl8367dVirtualVlanTable[RTL8367D_VIDMAX + 1]; +#endif + +static void _dal_rtl8367d_Vlan4kStUser2Smi(dal_rtl8367d_user_vlan4kentry *pUserVlan4kEntry, rtk_uint16 *pSmiVlan4kEntry) +{ + pSmiVlan4kEntry[0] |= (pUserVlan4kEntry->mbr & 0x00FF); + pSmiVlan4kEntry[0] |= (pUserVlan4kEntry->untag & 0x00FF) << 8; + + pSmiVlan4kEntry[1] |= (pUserVlan4kEntry->fid_msti & 0x0003); + pSmiVlan4kEntry[1] |= (pUserVlan4kEntry->svlan_chk_ivl_svl & 0x0001) << 2; + pSmiVlan4kEntry[1] |= (pUserVlan4kEntry->ivl_svl & 0x0001) << 3; +} + + +static void _dal_rtl8367d_Vlan4kStSmi2User(rtk_uint16 *pSmiVlan4kEntry, dal_rtl8367d_user_vlan4kentry *pUserVlan4kEntry) +{ + pUserVlan4kEntry->mbr = (pSmiVlan4kEntry[0] & 0x00FF); + pUserVlan4kEntry->untag = (pSmiVlan4kEntry[0] & 0xFF00) >> 8; + + pUserVlan4kEntry->fid_msti = (pSmiVlan4kEntry[1] & 0x0003); + pUserVlan4kEntry->svlan_chk_ivl_svl = (pSmiVlan4kEntry[1] & 0x0004) >> 2; + pUserVlan4kEntry->ivl_svl = (pSmiVlan4kEntry[1] & 0x0008) >> 3; +} +ret_t _dal_rtl8367d_setAsicVlan4kEntry(dal_rtl8367d_user_vlan4kentry *pVlan4kEntry ) +{ + rtk_uint16 vlan_4k_entry[RTL8367D_VLAN_4KTABLE_LEN]; + rtk_uint32 page_idx; + rtk_uint16 *tableAddr; + ret_t retVal; + rtk_uint32 regData; + + if(pVlan4kEntry->vid > RTL8367D_VIDMAX) + return RT_ERR_VLAN_VID; + + if(pVlan4kEntry->mbr > RTL8367D_PORTMASK) + return RT_ERR_PORT_MASK; + + if(pVlan4kEntry->untag > RTL8367D_PORTMASK) + return RT_ERR_PORT_MASK; + + if(pVlan4kEntry->fid_msti > RTL8367D_FIDMAX) + return RT_ERR_L2_FID; + + if(pVlan4kEntry->ivl_svl> RTK_ENABLE_END) + return RT_ERR_INPUT; + + if(pVlan4kEntry->svlan_chk_ivl_svl> RTK_ENABLE_END) + return RT_ERR_INPUT; + + memset(vlan_4k_entry, 0x00, sizeof(rtk_uint16) * RTL8367D_VLAN_4KTABLE_LEN); + _dal_rtl8367d_Vlan4kStUser2Smi(pVlan4kEntry, vlan_4k_entry); + //PRINT("\n %s %d\n",__FUNCTION__,__LINE__); + + /* Prepare Data */ + tableAddr = vlan_4k_entry; + for(page_idx = 0; page_idx < RTL8367D_VLAN_4KTABLE_LEN; page_idx++) + { + regData = *tableAddr; + retVal = rtl8367d_setAsicReg(RTL8367D_REG_TABLE_WRITE_DATA0 + page_idx, regData); + if(retVal != RT_ERR_OK) + return retVal; + + tableAddr++; + } + + /* Write Address (VLAN_ID) */ + regData = pVlan4kEntry->vid; + retVal = rtl8367d_setAsicReg(RTL8367D_REG_TABLE_ACCESS_ADDR, regData); + if(retVal != RT_ERR_OK) + return retVal; + + /* Write Command */ + retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_TABLE_ACCESS_CTRL, RTL8367D_TABLE_TYPE_MASK | RTL8367D_COMMAND_TYPE_MASK, RTL8367D_TABLE_ACCESS_REG_DATA(RTL8367D_TB_OP_WRITE,RTL8367D_TB_TARGET_CVLAN)); + if(retVal != RT_ERR_OK) + return retVal; + +#if defined(CONFIG_RTL8367D_ASICDRV_TEST) + memcpy(&Rtl8367dVirtualVlanTable[pVlan4kEntry->vid], pVlan4kEntry, sizeof(dal_rtl8367d_user_vlan4kentry)); +#endif + + return RT_ERR_OK; +} + + +ret_t _dal_rtl8367d_getAsicVlan4kEntry(dal_rtl8367d_user_vlan4kentry *pVlan4kEntry ) +{ + rtk_uint16 vlan_4k_entry[RTL8367D_VLAN_4KTABLE_LEN]; + rtk_uint32 page_idx; + rtk_uint16 *tableAddr; + ret_t retVal; + rtk_uint32 regData; + rtk_uint32 busyCounter; + + if(pVlan4kEntry->vid > RTL8367D_VIDMAX) + return RT_ERR_VLAN_VID; + + /* Polling status */ + busyCounter = RTL8367D_VLAN_BUSY_CHECK_NO; + while(busyCounter) + { + retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_TABLE_LUT_ADDR, RTL8367D_TABLE_LUT_ADDR_BUSY_FLAG_OFFSET,®Data); + if(retVal != RT_ERR_OK) + return retVal; + + if(regData == 0) + break; + + busyCounter --; + if(busyCounter == 0) + return RT_ERR_BUSYWAIT_TIMEOUT; + } + + /* Write Address (VLAN_ID) */ + regData = pVlan4kEntry->vid; + retVal = rtl8367d_setAsicReg(RTL8367D_REG_TABLE_ACCESS_ADDR, regData); + if(retVal != RT_ERR_OK) + return retVal; + + /* Read Command */ + retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_TABLE_ACCESS_CTRL, RTL8367D_TABLE_TYPE_MASK | RTL8367D_COMMAND_TYPE_MASK, RTL8367D_TABLE_ACCESS_REG_DATA(RTL8367D_TB_OP_READ,RTL8367D_TB_TARGET_CVLAN)); + if(retVal != RT_ERR_OK) + return retVal; + + /* Polling status */ + busyCounter = RTL8367D_VLAN_BUSY_CHECK_NO; + while(busyCounter) + { + retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_TABLE_LUT_ADDR, RTL8367D_TABLE_LUT_ADDR_BUSY_FLAG_OFFSET,®Data); + if(retVal != RT_ERR_OK) + return retVal; + + if(regData == 0) + break; + + busyCounter --; + if(busyCounter == 0) + return RT_ERR_BUSYWAIT_TIMEOUT; + } + + /* Read VLAN data from register */ + tableAddr = vlan_4k_entry; + for(page_idx = 0; page_idx < RTL8367D_VLAN_4KTABLE_LEN; page_idx++) + { + retVal = rtl8367d_getAsicReg(RTL8367D_REG_TABLE_READ_DATA0 + page_idx, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + *tableAddr = regData; + tableAddr++; + } + + _dal_rtl8367d_Vlan4kStSmi2User(vlan_4k_entry, pVlan4kEntry); + +#if defined(CONFIG_RTL8367D_ASICDRV_TEST) + memcpy(pVlan4kEntry, &Rtl8367dVirtualVlanTable[pVlan4kEntry->vid], sizeof(dal_rtl8367d_user_vlan4kentry)); +#endif + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8367d_vlan_init + * Description: + * Initialize VLAN. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * VLAN is disabled by default. User has to call this API to enable VLAN before + * using it. And It will set a default VLAN(vid 1) including all ports and set + * all ports PVID to the default VLAN. + */ +rtk_api_ret_t dal_rtl8367d_vlan_init(void) +{ + rtk_api_ret_t retVal; + rtk_uint32 i; + dal_rtl8367d_user_vlan4kentry vlan4K; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Set a default VLAN with vid 1 to 4K table for all ports */ + memset(&vlan4K, 0, sizeof(dal_rtl8367d_user_vlan4kentry)); + vlan4K.vid = 1; + vlan4K.mbr = RTK_PHY_PORTMASK_ALL; + vlan4K.untag = RTK_PHY_PORTMASK_ALL; + vlan4K.fid_msti = 0; + if ((retVal = _dal_rtl8367d_setAsicVlan4kEntry(&vlan4K)) != RT_ERR_OK) + return retVal; + + /* Set all ports PVID to default VLAN and tag-mode to original */ + RTK_SCAN_ALL_LOG_PORT(i) + { + if ((retVal = dal_rtl8367d_vlan_portPvid_set(i, 1, 0)) != RT_ERR_OK) + return retVal; + if ((retVal = dal_rtl8367d_vlan_tagMode_set(i, VLAN_TAG_MODE_ORIGINAL)) != RT_ERR_OK) + return retVal; + } + + /* Enable Ingress filter */ + RTK_SCAN_ALL_LOG_PORT(i) + { + if ((retVal = dal_rtl8367d_vlan_portIgrFilterEnable_set(i, ENABLED)) != RT_ERR_OK) + return retVal; + } + + /* enable VLAN */ + if ((retVal = dal_rtl8367d_vlan_egrFilterEnable_set(ENABLED)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_vlan_set + * Description: + * Set a VLAN entry. + * Input: + * vid - VLAN ID to configure. + * pVlanCfg - VLAN Configuration + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_L2_FID - Invalid FID. + * RT_ERR_VLAN_PORT_MBR_EXIST - Invalid member port mask. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * Note: + * + */ +rtk_api_ret_t dal_rtl8367d_vlan_set(rtk_vlan_t vid, rtk_vlan_cfg_t *pVlanCfg) +{ + rtk_api_ret_t retVal; + rtk_uint32 phyMbrPmask; + rtk_uint32 phyUntagPmask; + dal_rtl8367d_user_vlan4kentry vlan4K; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* vid must be 0~8191 */ + if (vid > RTL8367D_VIDMAX) + return RT_ERR_VLAN_VID; + + /* Null pointer check */ + if(NULL == pVlanCfg) + return RT_ERR_NULL_POINTER; + + /* Check port mask valid */ + RTK_CHK_PORTMASK_VALID(&(pVlanCfg->mbr)); + + /* Check untag port mask valid */ + RTK_CHK_PORTMASK_VALID(&(pVlanCfg->untag)); + + /* IVL_EN */ + if(pVlanCfg->ivl_en >= RTK_ENABLE_END) + return RT_ERR_ENABLE; + + /* fid must be 0~3 */ + if(pVlanCfg->fid_msti > RTL8367D_FIDMAX) + return RT_ERR_L2_FID; + + /* Policing, Meter ID , VLAN based priority ar not supported in RTL8367D*/ + if((pVlanCfg->envlanpol != 0)||(pVlanCfg->meteridx != 0) || (pVlanCfg->vbpen != 0) ||(pVlanCfg->vbpri != 0)) + return RT_ERR_INPUT; + + /* Get physical port mask */ + if(rtk_switch_portmask_L2P_get(&(pVlanCfg->mbr), &phyMbrPmask) != RT_ERR_OK) + return RT_ERR_FAILED; + + if(rtk_switch_portmask_L2P_get(&(pVlanCfg->untag), &phyUntagPmask) != RT_ERR_OK) + return RT_ERR_FAILED; + + /* update 4K table */ + memset(&vlan4K, 0, sizeof(dal_rtl8367d_user_vlan4kentry)); + vlan4K.vid = vid; + + vlan4K.mbr = (phyMbrPmask & 0xFFFF); + vlan4K.untag = (phyUntagPmask & 0xFFFF); + + vlan4K.ivl_svl = pVlanCfg->ivl_en; + vlan4K.fid_msti = pVlanCfg->fid_msti; + + if ((retVal = _dal_rtl8367d_setAsicVlan4kEntry(&vlan4K)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_vlan_get + * Description: + * Get a VLAN entry. + * Input: + * vid - VLAN ID to configure. + * Output: + * pVlanCfg - VLAN Configuration + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * Note: + * + */ +rtk_api_ret_t dal_rtl8367d_vlan_get(rtk_vlan_t vid, rtk_vlan_cfg_t *pVlanCfg) +{ + rtk_api_ret_t retVal; + rtk_uint32 phyMbrPmask; + rtk_uint32 phyUntagPmask; + dal_rtl8367d_user_vlan4kentry vlan4K; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* vid must be 0~8191 */ + if (vid > RTL8367D_VIDMAX) + return RT_ERR_VLAN_VID; + + /* Null pointer check */ + if(NULL == pVlanCfg) + return RT_ERR_NULL_POINTER; + + vlan4K.vid = vid; + + if ((retVal = _dal_rtl8367d_getAsicVlan4kEntry(&vlan4K)) != RT_ERR_OK) + return retVal; + + phyMbrPmask = vlan4K.mbr; + phyUntagPmask = vlan4K.untag; + if(rtk_switch_portmask_P2L_get(phyMbrPmask, &(pVlanCfg->mbr)) != RT_ERR_OK) + return RT_ERR_FAILED; + + if(rtk_switch_portmask_P2L_get(phyUntagPmask, &(pVlanCfg->untag)) != RT_ERR_OK) + return RT_ERR_FAILED; + + pVlanCfg->ivl_en = vlan4K.ivl_svl; + pVlanCfg->fid_msti = vlan4K.fid_msti; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_vlan_egrFilterEnable_set + * Description: + * Set VLAN egress filter. + * Input: + * egrFilter - Egress filtering + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid input parameters. + * Note: + * + */ +rtk_api_ret_t dal_rtl8367d_vlan_egrFilterEnable_set(rtk_enable_t egrFilter) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(egrFilter >= RTK_ENABLE_END) + return RT_ERR_ENABLE; + + /* enable VLAN */ + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_VLAN_CTRL, RTL8367D_VLAN_CTRL_OFFSET, egrFilter)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_vlan_egrFilterEnable_get + * Description: + * Get VLAN egress filter. + * Input: + * pEgrFilter - Egress filtering + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - NULL Pointer. + * Note: + * + */ +rtk_api_ret_t dal_rtl8367d_vlan_egrFilterEnable_get(rtk_enable_t *pEgrFilter) +{ + rtk_api_ret_t retVal; + rtk_uint32 state; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pEgrFilter) + return RT_ERR_NULL_POINTER; + + /* enable VLAN */ + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_VLAN_CTRL, RTL8367D_VLAN_CTRL_OFFSET, &state)) != RT_ERR_OK) + return retVal; + + *pEgrFilter = (rtk_enable_t)state; + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_vlan_portPvid_set + * Description: + * Set port to specified VLAN ID(PVID). + * Input: + * port - Port id. + * pvid - Specified VLAN ID. + * priority - 802.1p priority for the PVID. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_VLAN_PRIORITY - Invalid priority. + * RT_ERR_VLAN_ENTRY_NOT_FOUND - VLAN entry not found. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * Note: + * The API is used for Port-based VLAN. The untagged frame received from the + * port will be classified to the specified VLAN and assigned to the specified priority. + */ +rtk_api_ret_t dal_rtl8367d_vlan_portPvid_set(rtk_port_t port, rtk_vlan_t pvid, rtk_pri_t priority) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + /* vid must be 0~8191 */ + if (pvid > RTL8367D_VIDMAX) + return RT_ERR_VLAN_VID; + + /* priority is not supported in RTL8367D */ + if (priority > 0) + return RT_ERR_INPUT; + + retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_VLAN_PVID_CTRL0 + rtk_switch_port_L2P_get(port), RTL8367D_VLAN_PVID_CTRL0_MASK, pvid); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_vlan_portPvid_get + * Description: + * Get VLAN ID(PVID) on specified port. + * Input: + * port - Port id. + * Output: + * pPvid - Specified VLAN ID. + * pPriority - 802.1p priority for the PVID. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get the PVID and 802.1p priority for the PVID of Port-based VLAN. + */ +rtk_api_ret_t dal_rtl8367d_vlan_portPvid_get(rtk_port_t port, rtk_vlan_t *pPvid, rtk_pri_t *pPriority) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if(NULL == pPvid) + return RT_ERR_NULL_POINTER; + + if(NULL == pPriority) + return RT_ERR_NULL_POINTER; + + *pPriority = 0; + + retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_VLAN_PVID_CTRL0 + rtk_switch_port_L2P_get(port), RTL8367D_VLAN_PVID_CTRL0_MASK, pPvid); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_vlan_portIgrFilterEnable_set + * Description: + * Set VLAN ingress for each port. + * Input: + * port - Port id. + * igr_filter - VLAN ingress function enable status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * RT_ERR_ENABLE - Invalid enable input + * Note: + * The status of vlan ingress filter is as following: + * - DISABLED + * - ENABLED + * While VLAN function is enabled, ASIC will decide VLAN ID for each received frame and get belonged member + * ports from VLAN table. If received port is not belonged to VLAN member ports, ASIC will drop received frame if VLAN ingress function is enabled. + */ +rtk_api_ret_t dal_rtl8367d_vlan_portIgrFilterEnable_set(rtk_port_t port, rtk_enable_t igr_filter) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if (igr_filter >= RTK_ENABLE_END) + return RT_ERR_ENABLE; + + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_VLAN_INGRESS, rtk_switch_port_L2P_get(port), igr_filter)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_vlan_portIgrFilterEnable_get + * Description: + * Get VLAN Ingress Filter + * Input: + * port - Port id. + * Output: + * pIgr_filter - VLAN ingress function enable status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can Get the VLAN ingress filter status. + * The status of vlan ingress filter is as following: + * - DISABLED + * - ENABLED + */ +rtk_api_ret_t dal_rtl8367d_vlan_portIgrFilterEnable_get(rtk_port_t port, rtk_enable_t *pIgr_filter) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if(NULL == pIgr_filter) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_VLAN_INGRESS, rtk_switch_port_L2P_get(port), pIgr_filter)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_vlan_portAcceptFrameType_set + * Description: + * Set VLAN accept_frame_type + * Input: + * port - Port id. + * accept_frame_type - accept frame type + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_VLAN_ACCEPT_FRAME_TYPE - Invalid frame type. + * Note: + * The API is used for checking 802.1Q tagged frames. + * The accept frame type as following: + * - ACCEPT_FRAME_TYPE_ALL + * - ACCEPT_FRAME_TYPE_TAG_ONLY + * - ACCEPT_FRAME_TYPE_UNTAG_ONLY + */ +rtk_api_ret_t dal_rtl8367d_vlan_portAcceptFrameType_set(rtk_port_t port, rtk_vlan_acceptFrameType_t accept_frame_type) +{ + rtk_api_ret_t retVal; + rtk_uint32 mask; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if (accept_frame_type >= ACCEPT_FRAME_TYPE_END) + return RT_ERR_VLAN_ACCEPT_FRAME_TYPE; + + mask = RTL8367D_PORT0_FRAME_TYPE_MASK << ((rtk_switch_port_L2P_get(port) & 0x7) << 1); + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_VLAN_ACCEPT_FRAME_TYPE_CTRL0, mask, accept_frame_type)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_vlan_portAcceptFrameType_get + * Description: + * Get VLAN accept_frame_type + * Input: + * port - Port id. + * Output: + * pAccept_frame_type - accept frame type + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can Get the VLAN ingress filter. + * The accept frame type as following: + * - ACCEPT_FRAME_TYPE_ALL + * - ACCEPT_FRAME_TYPE_TAG_ONLY + * - ACCEPT_FRAME_TYPE_UNTAG_ONLY + */ +rtk_api_ret_t dal_rtl8367d_vlan_portAcceptFrameType_get(rtk_port_t port, rtk_vlan_acceptFrameType_t *pAccept_frame_type) +{ + rtk_api_ret_t retVal; + rtk_uint32 mask; + rtk_uint32 type; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if(NULL == pAccept_frame_type) + return RT_ERR_NULL_POINTER; + + mask = RTL8367D_PORT0_FRAME_TYPE_MASK << ((rtk_switch_port_L2P_get(port) & 0x7) << 1); + if((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_VLAN_ACCEPT_FRAME_TYPE_CTRL0, mask, &type)) != RT_ERR_OK) + return retVal; + + *pAccept_frame_type = (rtk_vlan_acceptFrameType_t)type; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_vlan_tagMode_set + * Description: + * Set CVLAN egress tag mode + * Input: + * port - Port id. + * tag_mode - The egress tag mode. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * The API can set Egress tag mode. There are 4 mode for egress tag: + * - VLAN_TAG_MODE_ORIGINAL, + * - VLAN_TAG_MODE_KEEP_FORMAT, + * - VLAN_TAG_MODE_PRI. + * - VLAN_TAG_MODE_REAL_KEEP_FORMAT, + */ +rtk_api_ret_t dal_rtl8367d_vlan_tagMode_set(rtk_port_t port, rtk_vlan_tagMode_t tag_mode) +{ + rtk_api_ret_t retVal; + rtk_uint32 addr; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if (tag_mode >= VLAN_TAG_MODE_END) + return RT_ERR_PORT_ID; + + addr = (RTL8367D_REG_PORT0_MISC_CFG + (rtk_switch_port_L2P_get(port) << 5)); + if ((retVal = rtl8367d_setAsicRegBits(addr, RTL8367D_PORT0_MISC_CFG_VLAN_EGRESS_MODE_MASK, tag_mode)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_vlan_tagMode_get + * Description: + * Get CVLAN egress tag mode + * Input: + * port - Port id. + * Output: + * pTag_mode - The egress tag mode. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get Egress tag mode. There are 4 mode for egress tag: + * - VLAN_TAG_MODE_ORIGINAL, + * - VLAN_TAG_MODE_KEEP_FORMAT, + * - VLAN_TAG_MODE_PRI. + * - VLAN_TAG_MODE_REAL_KEEP_FORMAT, + */ +rtk_api_ret_t dal_rtl8367d_vlan_tagMode_get(rtk_port_t port, rtk_vlan_tagMode_t *pTag_mode) +{ + rtk_api_ret_t retVal; + rtk_uint32 mode; + rtk_uint32 addr; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if(NULL == pTag_mode) + return RT_ERR_NULL_POINTER; + + addr = (RTL8367D_REG_PORT0_MISC_CFG + (rtk_switch_port_L2P_get(port) << 5)); + if ((retVal = rtl8367d_getAsicRegBits(addr, RTL8367D_PORT0_MISC_CFG_VLAN_EGRESS_MODE_MASK, &mode)) != RT_ERR_OK) + return retVal; + + *pTag_mode = (rtk_vlan_tagMode_t)mode; + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_vlan_transparent_set + * Description: + * Set VLAN transparent mode + * Input: + * egr_port - Egress Port id. + * pIgr_pmask - Ingress Port Mask. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * None. + */ +rtk_api_ret_t dal_rtl8367d_vlan_transparent_set(rtk_port_t egr_port, rtk_portmask_t *pIgr_pmask) +{ + rtk_api_ret_t retVal; + rtk_uint32 pmask; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(egr_port); + + if(NULL == pIgr_pmask) + return RT_ERR_NULL_POINTER; + + RTK_CHK_PORTMASK_VALID(pIgr_pmask); + + if(rtk_switch_portmask_L2P_get(pIgr_pmask, &pmask) != RT_ERR_OK) + return RT_ERR_FAILED; + + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_VLAN_EGRESS_TRANS_CTRL0 + rtk_switch_port_L2P_get(egr_port), RTL8367D_VLAN_EGRESS_TRANS_CTRL0_MASK, pmask)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_vlan_transparent_get + * Description: + * Get VLAN transparent mode + * Input: + * egr_port - Egress Port id. + * Output: + * pIgr_pmask - Ingress Port Mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * None. + */ +rtk_api_ret_t dal_rtl8367d_vlan_transparent_get(rtk_port_t egr_port, rtk_portmask_t *pIgr_pmask) +{ + rtk_api_ret_t retVal; + rtk_uint32 pmask; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(egr_port); + + if(NULL == pIgr_pmask) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_VLAN_EGRESS_TRANS_CTRL0 + rtk_switch_port_L2P_get(egr_port), RTL8367D_VLAN_EGRESS_TRANS_CTRL0_MASK, &pmask)) != RT_ERR_OK) + return retVal; + + if(rtk_switch_portmask_P2L_get(pmask, pIgr_pmask) != RT_ERR_OK) + return RT_ERR_FAILED; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_vlan_keep_set + * Description: + * Set VLAN egress keep mode + * Input: + * egr_port - Egress Port id. + * pIgr_pmask - Ingress Port Mask. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * None. + */ +rtk_api_ret_t dal_rtl8367d_vlan_keep_set(rtk_port_t egr_port, rtk_portmask_t *pIgr_pmask) +{ + rtk_api_ret_t retVal; + rtk_uint32 pmask; + rtk_uint32 regAddr, bitMask; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(egr_port); + + if(NULL == pIgr_pmask) + return RT_ERR_NULL_POINTER; + + RTK_CHK_PORTMASK_VALID(pIgr_pmask); + + if(rtk_switch_portmask_L2P_get(pIgr_pmask, &pmask) != RT_ERR_OK) + return RT_ERR_FAILED; + + regAddr = RTL8367D_REG_VLAN_EGRESS_KEEP_CTRL0 + (rtk_switch_port_L2P_get(egr_port)>>1); + bitMask = RTL8367D_PORT0_VLAN_KEEP_MASK_MASK<<((rtk_switch_port_L2P_get(egr_port)&1)*8); + retVal = rtl8367d_setAsicRegBits(regAddr, bitMask, pmask); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_vlan_keep_get + * Description: + * Get VLAN egress keep mode + * Input: + * egr_port - Egress Port id. + * Output: + * pIgr_pmask - Ingress Port Mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * None. + */ +rtk_api_ret_t dal_rtl8367d_vlan_keep_get(rtk_port_t egr_port, rtk_portmask_t *pIgr_pmask) +{ + rtk_api_ret_t retVal; + rtk_uint32 pmask; + rtk_uint32 regAddr, bitMask; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(egr_port); + + if(NULL == pIgr_pmask) + return RT_ERR_NULL_POINTER; + + regAddr = RTL8367D_REG_VLAN_EGRESS_KEEP_CTRL0 + (rtk_switch_port_L2P_get(egr_port)>>1); + bitMask = RTL8367D_PORT0_VLAN_KEEP_MASK_MASK<<((rtk_switch_port_L2P_get(egr_port)&1)*8); + retVal = rtl8367d_getAsicRegBits(regAddr, bitMask, &pmask); + if(retVal != RT_ERR_OK) + return retVal; + + if(rtk_switch_portmask_P2L_get(pmask, pIgr_pmask) != RT_ERR_OK) + return RT_ERR_FAILED; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_vlan_stg_set + * Description: + * Set spanning tree group instance of the vlan to the specified device + * Input: + * vid - Specified VLAN ID. + * stg - spanning tree group instance. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_MSTI - Invalid msti parameter + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * Note: + * The API can set spanning tree group instance of the vlan to the specified device. + */ +rtk_api_ret_t dal_rtl8367d_vlan_stg_set(rtk_vlan_t vid, rtk_stp_msti_id_t stg) +{ + rtk_api_ret_t retVal; + dal_rtl8367d_user_vlan4kentry vlan4K; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* vid must be 0~4095 */ + if (vid > RTL8367D_VIDMAX) + return RT_ERR_VLAN_VID; + + /* stg must be 0~3 */ + if (stg > RTL8367D_MSTIMAX) + return RT_ERR_MSTI; + + /* update 4K table */ + vlan4K.vid = vid; + if ((retVal = _dal_rtl8367d_getAsicVlan4kEntry(&vlan4K)) != RT_ERR_OK) + return retVal; + + vlan4K.fid_msti= stg; + if ((retVal = _dal_rtl8367d_setAsicVlan4kEntry(&vlan4K)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_vlan_stg_get + * Description: + * Get spanning tree group instance of the vlan to the specified device + * Input: + * vid - Specified VLAN ID. + * Output: + * pStg - spanning tree group instance. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * Note: + * The API can get spanning tree group instance of the vlan to the specified device. + */ +rtk_api_ret_t dal_rtl8367d_vlan_stg_get(rtk_vlan_t vid, rtk_stp_msti_id_t *pStg) +{ + rtk_api_ret_t retVal; + dal_rtl8367d_user_vlan4kentry vlan4K; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* vid must be 0~4095 */ + if (vid > RTL8367D_VIDMAX) + return RT_ERR_VLAN_VID; + + if(NULL == pStg) + return RT_ERR_NULL_POINTER; + + /* update 4K table */ + vlan4K.vid = vid; + if ((retVal = _dal_rtl8367d_getAsicVlan4kEntry(&vlan4K)) != RT_ERR_OK) + return retVal; + + *pStg = vlan4K.fid_msti; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_vlan_portFid_set + * Description: + * Set port-based filtering database + * Input: + * port - Port id. + * enable - ebable port-based FID + * fid - Specified filtering database. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_FID - Invalid fid. + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API can set port-based filtering database. If the function is enabled, all input + * packets will be assigned to the port-based fid regardless vlan tag. + */ +rtk_api_ret_t dal_rtl8367d_vlan_portFid_set(rtk_port_t port, rtk_enable_t enable, rtk_fid_t fid) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if (enable>=RTK_ENABLE_END) + return RT_ERR_ENABLE; + + /* fid must be 0~3 */ + if (fid > RTL8367D_FIDMAX) + return RT_ERR_L2_FID; + + if ((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_PORT_PBFIDEN, rtk_switch_port_L2P_get(port), enable))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_setAsicReg(RTL8367D_REG_PORT0_PBFID + rtk_switch_port_L2P_get(port), fid))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_vlan_portFid_get + * Description: + * Get port-based filtering database + * Input: + * port - Port id. + * Output: + * pEnable - ebable port-based FID + * pFid - Specified filtering database. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API can get port-based filtering database status. If the function is enabled, all input + * packets will be assigned to the port-based fid regardless vlan tag. + */ +rtk_api_ret_t dal_rtl8367d_vlan_portFid_get(rtk_port_t port, rtk_enable_t *pEnable, rtk_fid_t *pFid) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if(NULL == pEnable) + return RT_ERR_NULL_POINTER; + + if(NULL == pFid) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_PORT_PBFIDEN, rtk_switch_port_L2P_get(port), pEnable))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8367d_getAsicReg(RTL8367D_REG_PORT0_PBFID + rtk_switch_port_L2P_get(port), pFid))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/*Spanning Tree*/ +/* Function Name: + * dal_rtl8367d_stp_mstpState_set + * Description: + * Configure spanning tree state per each port. + * Input: + * port - Port id + * msti - Multiple spanning tree instance. + * stp_state - Spanning tree state for msti + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_MSTI - Invalid msti parameter. + * RT_ERR_MSTP_STATE - Invalid STP state. + * Note: + * System supports per-port multiple spanning tree state for each msti. + * There are four states supported by ASIC. + * - STP_STATE_DISABLED + * - STP_STATE_BLOCKING + * - STP_STATE_LEARNING + * - STP_STATE_FORWARDING + */ +rtk_api_ret_t dal_rtl8367d_stp_mstpState_set(rtk_stp_msti_id_t msti, rtk_port_t port, rtk_stp_state_t stp_state) +{ + rtk_api_ret_t retVal; + rtk_uint32 bitMask; + rtk_uint32 phyPort; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if (msti > RTL8367D_MSTIMAX) + return RT_ERR_MSTI; + + if (stp_state >= STP_STATE_END) + return RT_ERR_MSTP_STATE; + + phyPort = rtk_switch_port_L2P_get(port); + if (phyPort == UNDEFINE_PHY_PORT) + return RT_ERR_PORT_ID; + + bitMask = RTL8367D_VLAN_MSTI0_CTRL0_PORT0_STATE_MASK << (phyPort * 2); + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_VLAN_MSTI0_CTRL0 + (msti * 2), bitMask, stp_state)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_stp_mstpState_get + * Description: + * Get spanning tree state per each port. + * Input: + * port - Port id. + * msti - Multiple spanning tree instance. + * Output: + * pStp_state - Spanning tree state for msti + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_MSTI - Invalid msti parameter. + * Note: + * System supports per-port multiple spanning tree state for each msti. + * There are four states supported by ASIC. + * - STP_STATE_DISABLED + * - STP_STATE_BLOCKING + * - STP_STATE_LEARNING + * - STP_STATE_FORWARDING + */ +rtk_api_ret_t dal_rtl8367d_stp_mstpState_get(rtk_stp_msti_id_t msti, rtk_port_t port, rtk_stp_state_t *pStp_state) +{ + rtk_api_ret_t retVal; + rtk_uint32 bitMask; + rtk_uint32 phyPort; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if (msti > RTL8367D_MSTIMAX) + return RT_ERR_MSTI; + + if(NULL == pStp_state) + return RT_ERR_NULL_POINTER; + + phyPort = rtk_switch_port_L2P_get(port); + if (phyPort == UNDEFINE_PHY_PORT) + return RT_ERR_PORT_ID; + + bitMask = RTL8367D_VLAN_MSTI0_CTRL0_PORT0_STATE_MASK << (phyPort * 2); + if ((retVal = rtl8367d_getAsicRegBits(RTL8367D_REG_VLAN_MSTI0_CTRL0 + (msti * 2), bitMask, pStp_state)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8367d_vlan_reservedVidAction_set + * Description: + * Set Action of VLAN ID = 0 & 4095 tagged packet + * Input: + * action_vid0 - Action for VID 0. + * action_vid4095 - Action for VID 4095. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + * + */ +rtk_api_ret_t dal_rtl8367d_vlan_reservedVidAction_set(rtk_vlan_resVidAction_t action_vid0, rtk_vlan_resVidAction_t action_vid4095) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(action_vid0 >= RESVID_ACTION_END) + return RT_ERR_INPUT; + + if(action_vid4095 >= RESVID_ACTION_END) + return RT_ERR_INPUT; + + if((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_VLAN_EXT_CTRL, RTL8367D_VLAN_VID0_TYPE_OFFSET, action_vid0)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_VLAN_EXT_CTRL, RTL8367D_VLAN_VID4095_TYPE_OFFSET, action_vid4095)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_vlan_reservedVidAction_get + * Description: + * Get Action of VLAN ID = 0 & 4095 tagged packet + * Input: + * pAction_vid0 - Action for VID 0. + * pAction_vid4095 - Action for VID 4095. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - NULL Pointer + * Note: + * + */ +rtk_api_ret_t dal_rtl8367d_vlan_reservedVidAction_get(rtk_vlan_resVidAction_t *pAction_vid0, rtk_vlan_resVidAction_t *pAction_vid4095) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(pAction_vid0 == NULL) + return RT_ERR_NULL_POINTER; + + if(pAction_vid4095 == NULL) + return RT_ERR_NULL_POINTER; + + if((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_VLAN_EXT_CTRL, RTL8367D_VLAN_VID0_TYPE_OFFSET, (rtk_uint32 *)pAction_vid0)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_VLAN_EXT_CTRL, RTL8367D_VLAN_VID4095_TYPE_OFFSET, (rtk_uint32 *)pAction_vid4095)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_vlan_realKeepRemarkEnable_set + * Description: + * Set Real keep 1p remarking feature + * Input: + * enabled - State of 1p remarking at real keep packet + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + * + */ +rtk_api_ret_t dal_rtl8367d_vlan_realKeepRemarkEnable_set(rtk_enable_t enabled) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(enabled >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_VLAN_EXT_CTRL, RTL8367D_VLAN_1P_REMARK_BYPASS_REALKEEP_OFFSET, enabled)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367d_vlan_realKeepRemarkEnable_get + * Description: + * Get Real keep 1p remarking feature + * Input: + * None. + * Output: + * pEnabled - State of 1p remarking at real keep packet + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + * + */ +rtk_api_ret_t dal_rtl8367d_vlan_realKeepRemarkEnable_get(rtk_enable_t *pEnabled) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pEnabled) + return RT_ERR_NULL_POINTER; + + if((retVal = rtl8367d_getAsicRegBit(RTL8367D_REG_VLAN_EXT_CTRL, RTL8367D_VLAN_1P_REMARK_BYPASS_REALKEEP_OFFSET, (rtk_uint32 *)pEnabled)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8367d_vlan_reset + * Description: + * Reset VLAN + * Input: + * None. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + * + */ +rtk_api_ret_t dal_rtl8367d_vlan_reset(void) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if((retVal = rtl8367d_setAsicRegBit(RTL8367D_REG_VLAN_EXT_CTRL2, RTL8367D_VLAN_EXT_CTRL2_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_vlan.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_vlan.h new file mode 100644 index 00000000..91f9e6eb --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/dal_rtl8367d_vlan.h @@ -0,0 +1,626 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8367/RTL8367C switch high-level API + * + * Feature : The file includes Trap module high-layer VLAN defination + * + */ + +#ifndef __DAL_RTL8367D_VLAN_H__ +#define __DAL_RTL8367D_VLAN_H__ + +#include + +typedef struct USER_VLANTABLE{ + + rtk_uint16 vid; + rtk_uint16 mbr; + rtk_uint16 untag; + rtk_uint16 fid_msti; + rtk_uint16 svlan_chk_ivl_svl; + rtk_uint16 ivl_svl; + +}dal_rtl8367d_user_vlan4kentry; + +extern ret_t _dal_rtl8367d_setAsicVlan4kEntry(dal_rtl8367d_user_vlan4kentry *pVlan4kEntry); +extern ret_t _dal_rtl8367d_getAsicVlan4kEntry(dal_rtl8367d_user_vlan4kentry *pVlan4kEntry); + +/* Function Name: + * dal_rtl8367d_vlan_init + * Description: + * Initialize VLAN. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * VLAN is disabled by default. User has to call this API to enable VLAN before + * using it. And It will set a default VLAN(vid 1) including all ports and set + * all ports PVID to the default VLAN. + */ +extern rtk_api_ret_t dal_rtl8367d_vlan_init(void); + +/* Function Name: + * dal_rtl8367d_vlan_set + * Description: + * Set a VLAN entry. + * Input: + * vid - VLAN ID to configure. + * pVlanCfg - VLAN Configuration + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_L2_FID - Invalid FID. + * RT_ERR_VLAN_PORT_MBR_EXIST - Invalid member port mask. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367d_vlan_set(rtk_vlan_t vid, rtk_vlan_cfg_t *pVlanCfg); + +/* Function Name: + * dal_rtl8367d_vlan_get + * Description: + * Get a VLAN entry. + * Input: + * vid - VLAN ID to configure. + * Output: + * pVlanCfg - VLAN Configuration + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367d_vlan_get(rtk_vlan_t vid, rtk_vlan_cfg_t *pVlanCfg); + +/* Function Name: + * dal_rtl8367d_vlan_egrFilterEnable_set + * Description: + * Set VLAN egress filter. + * Input: + * egrFilter - Egress filtering + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid input parameters. + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367d_vlan_egrFilterEnable_set(rtk_enable_t egrFilter); + +/* Function Name: + * dal_rtl8367d_vlan_egrFilterEnable_get + * Description: + * Get VLAN egress filter. + * Input: + * pEgrFilter - Egress filtering + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - NULL Pointer. + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367d_vlan_egrFilterEnable_get(rtk_enable_t *pEgrFilter); + +/* Function Name: + * dal_rtl8367d_vlan_portPvid_set + * Description: + * Set port to specified VLAN ID(PVID). + * Input: + * port - Port id. + * pvid - Specified VLAN ID. + * priority - 802.1p priority for the PVID. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_VLAN_PRIORITY - Invalid priority. + * RT_ERR_VLAN_ENTRY_NOT_FOUND - VLAN entry not found. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * Note: + * The API is used for Port-based VLAN. The untagged frame received from the + * port will be classified to the specified VLAN and assigned to the specified priority. + */ +extern rtk_api_ret_t dal_rtl8367d_vlan_portPvid_set(rtk_port_t port, rtk_vlan_t pvid, rtk_pri_t priority); + +/* Function Name: + * dal_rtl8367d_vlan_portPvid_get + * Description: + * Get VLAN ID(PVID) on specified port. + * Input: + * port - Port id. + * Output: + * pPvid - Specified VLAN ID. + * pPriority - 802.1p priority for the PVID. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get the PVID and 802.1p priority for the PVID of Port-based VLAN. + */ +extern rtk_api_ret_t dal_rtl8367d_vlan_portPvid_get(rtk_port_t port, rtk_vlan_t *pPvid, rtk_pri_t *pPriority); + +/* Function Name: + * dal_rtl8367d_vlan_portIgrFilterEnable_set + * Description: + * Set VLAN ingress for each port. + * Input: + * port - Port id. + * igr_filter - VLAN ingress function enable status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * RT_ERR_ENABLE - Invalid enable input + * Note: + * The status of vlan ingress filter is as following: + * - DISABLED + * - ENABLED + * While VLAN function is enabled, ASIC will decide VLAN ID for each received frame and get belonged member + * ports from VLAN table. If received port is not belonged to VLAN member ports, ASIC will drop received frame if VLAN ingress function is enabled. + */ +extern rtk_api_ret_t dal_rtl8367d_vlan_portIgrFilterEnable_set(rtk_port_t port, rtk_enable_t igr_filter); + +/* Function Name: + * dal_rtl8367d_vlan_portIgrFilterEnable_get + * Description: + * Get VLAN Ingress Filter + * Input: + * port - Port id. + * Output: + * pIgr_filter - VLAN ingress function enable status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can Get the VLAN ingress filter status. + * The status of vlan ingress filter is as following: + * - DISABLED + * - ENABLED + */ +extern rtk_api_ret_t dal_rtl8367d_vlan_portIgrFilterEnable_get(rtk_port_t port, rtk_enable_t *pIgr_filter); + +/* Function Name: + * dal_rtl8367d_vlan_portAcceptFrameType_set + * Description: + * Set VLAN accept_frame_type + * Input: + * port - Port id. + * accept_frame_type - accept frame type + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_VLAN_ACCEPT_FRAME_TYPE - Invalid frame type. + * Note: + * The API is used for checking 802.1Q tagged frames. + * The accept frame type as following: + * - ACCEPT_FRAME_TYPE_ALL + * - ACCEPT_FRAME_TYPE_TAG_ONLY + * - ACCEPT_FRAME_TYPE_UNTAG_ONLY + */ +extern rtk_api_ret_t dal_rtl8367d_vlan_portAcceptFrameType_set(rtk_port_t port, rtk_vlan_acceptFrameType_t accept_frame_type); + +/* Function Name: + * dal_rtl8367d_vlan_portAcceptFrameType_get + * Description: + * Get VLAN accept_frame_type + * Input: + * port - Port id. + * Output: + * pAccept_frame_type - accept frame type + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can Get the VLAN ingress filter. + * The accept frame type as following: + * - ACCEPT_FRAME_TYPE_ALL + * - ACCEPT_FRAME_TYPE_TAG_ONLY + * - ACCEPT_FRAME_TYPE_UNTAG_ONLY + */ +extern rtk_api_ret_t dal_rtl8367d_vlan_portAcceptFrameType_get(rtk_port_t port, rtk_vlan_acceptFrameType_t *pAccept_frame_type); + +/* Function Name: + * dal_rtl8367d_vlan_tagMode_set + * Description: + * Set CVLAN egress tag mode + * Input: + * port - Port id. + * tag_mode - The egress tag mode. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * The API can set Egress tag mode. There are 4 mode for egress tag: + * - VLAN_TAG_MODE_ORIGINAL, + * - VLAN_TAG_MODE_KEEP_FORMAT, + * - VLAN_TAG_MODE_PRI. + * - VLAN_TAG_MODE_REAL_KEEP_FORMAT, + */ +extern rtk_api_ret_t dal_rtl8367d_vlan_tagMode_set(rtk_port_t port, rtk_vlan_tagMode_t tag_mode); + +/* Function Name: + * dal_rtl8367d_vlan_tagMode_get + * Description: + * Get CVLAN egress tag mode + * Input: + * port - Port id. + * Output: + * pTag_mode - The egress tag mode. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get Egress tag mode. There are 4 mode for egress tag: + * - VLAN_TAG_MODE_ORIGINAL, + * - VLAN_TAG_MODE_KEEP_FORMAT, + * - VLAN_TAG_MODE_PRI. + * - VLAN_TAG_MODE_REAL_KEEP_FORMAT, + */ +extern rtk_api_ret_t dal_rtl8367d_vlan_tagMode_get(rtk_port_t port, rtk_vlan_tagMode_t *pTag_mode); + +/* Function Name: + * dal_rtl8367d_vlan_transparent_set + * Description: + * Set VLAN transparent mode + * Input: + * egr_port - Egress Port id. + * pIgr_pmask - Ingress Port Mask. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * None. + */ +extern rtk_api_ret_t dal_rtl8367d_vlan_transparent_set(rtk_port_t egr_port, rtk_portmask_t *pIgr_pmask); + +/* Function Name: + * dal_rtl8367d_vlan_transparent_get + * Description: + * Get VLAN transparent mode + * Input: + * egr_port - Egress Port id. + * Output: + * pIgr_pmask - Ingress Port Mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * None. + */ +extern rtk_api_ret_t dal_rtl8367d_vlan_transparent_get(rtk_port_t egr_port, rtk_portmask_t *pIgr_pmask); + +/* Function Name: + * dal_rtl8367d_vlan_keep_set + * Description: + * Set VLAN egress keep mode + * Input: + * egr_port - Egress Port id. + * pIgr_pmask - Ingress Port Mask. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * None. + */ +extern rtk_api_ret_t dal_rtl8367d_vlan_keep_set(rtk_port_t egr_port, rtk_portmask_t *pIgr_pmask); + +/* Function Name: + * dal_rtl8367d_vlan_keep_get + * Description: + * Get VLAN egress keep mode + * Input: + * egr_port - Egress Port id. + * Output: + * pIgr_pmask - Ingress Port Mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * None. + */ +extern rtk_api_ret_t dal_rtl8367d_vlan_keep_get(rtk_port_t egr_port, rtk_portmask_t *pIgr_pmask); + +/* Function Name: + * dal_rtl8367d_vlan_stg_set + * Description: + * Set spanning tree group instance of the vlan to the specified device + * Input: + * vid - Specified VLAN ID. + * stg - spanning tree group instance. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_MSTI - Invalid msti parameter + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * Note: + * The API can set spanning tree group instance of the vlan to the specified device. + */ +extern rtk_api_ret_t dal_rtl8367d_vlan_stg_set(rtk_vlan_t vid, rtk_stp_msti_id_t stg); + +/* Function Name: + * dal_rtl8367d_vlan_stg_get + * Description: + * Get spanning tree group instance of the vlan to the specified device + * Input: + * vid - Specified VLAN ID. + * Output: + * pStg - spanning tree group instance. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * Note: + * The API can get spanning tree group instance of the vlan to the specified device. + */ +extern rtk_api_ret_t dal_rtl8367d_vlan_stg_get(rtk_vlan_t vid, rtk_stp_msti_id_t *pStg); + +/* Function Name: + * dal_rtl8367d_vlan_portFid_set + * Description: + * Set port-based filtering database + * Input: + * port - Port id. + * enable - ebable port-based FID + * fid - Specified filtering database. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_FID - Invalid fid. + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API can set port-based filtering database. If the function is enabled, all input + * packets will be assigned to the port-based fid regardless vlan tag. + */ +extern rtk_api_ret_t dal_rtl8367d_vlan_portFid_set(rtk_port_t port, rtk_enable_t enable, rtk_fid_t fid); + +/* Function Name: + * dal_rtl8367d_vlan_portFid_get + * Description: + * Get port-based filtering database + * Input: + * port - Port id. + * Output: + * pEnable - ebable port-based FID + * pFid - Specified filtering database. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API can get port-based filtering database status. If the function is enabled, all input + * packets will be assigned to the port-based fid regardless vlan tag. + */ +extern rtk_api_ret_t dal_rtl8367d_vlan_portFid_get(rtk_port_t port, rtk_enable_t *pEnable, rtk_fid_t *pFid); + + +/*Spanning Tree*/ +/* Function Name: + * dal_rtl8367d_stp_mstpState_set + * Description: + * Configure spanning tree state per each port. + * Input: + * port - Port id + * msti - Multiple spanning tree instance. + * stp_state - Spanning tree state for msti + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_MSTI - Invalid msti parameter. + * RT_ERR_MSTP_STATE - Invalid STP state. + * Note: + * System supports per-port multiple spanning tree state for each msti. + * There are four states supported by ASIC. + * - STP_STATE_DISABLED + * - STP_STATE_BLOCKING + * - STP_STATE_LEARNING + * - STP_STATE_FORWARDING + */ +extern rtk_api_ret_t dal_rtl8367d_stp_mstpState_set(rtk_stp_msti_id_t msti, rtk_port_t port, rtk_stp_state_t stp_state); + +/* Function Name: + * dal_rtl8367d_stp_mstpState_get + * Description: + * Get spanning tree state per each port. + * Input: + * port - Port id. + * msti - Multiple spanning tree instance. + * Output: + * pStp_state - Spanning tree state for msti + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_MSTI - Invalid msti parameter. + * Note: + * System supports per-port multiple spanning tree state for each msti. + * There are four states supported by ASIC. + * - STP_STATE_DISABLED + * - STP_STATE_BLOCKING + * - STP_STATE_LEARNING + * - STP_STATE_FORWARDING + */ +extern rtk_api_ret_t dal_rtl8367d_stp_mstpState_get(rtk_stp_msti_id_t msti, rtk_port_t port, rtk_stp_state_t *pStp_state); + +/* Function Name: + * dal_rtl8367d_vlan_reservedVidAction_set + * Description: + * Set Action of VLAN ID = 0 & 4095 tagged packet + * Input: + * action_vid0 - Action for VID 0. + * action_vid4095 - Action for VID 4095. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367d_vlan_reservedVidAction_set(rtk_vlan_resVidAction_t action_vid0, rtk_vlan_resVidAction_t action_vid4095); + +/* Function Name: + * dal_rtl8367d_vlan_reservedVidAction_get + * Description: + * Get Action of VLAN ID = 0 & 4095 tagged packet + * Input: + * pAction_vid0 - Action for VID 0. + * pAction_vid4095 - Action for VID 4095. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - NULL Pointer + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367d_vlan_reservedVidAction_get(rtk_vlan_resVidAction_t *pAction_vid0, rtk_vlan_resVidAction_t *pAction_vid4095); + +/* Function Name: + * dal_rtl8367d_vlan_realKeepRemarkEnable_set + * Description: + * Set Real keep 1p remarking feature + * Input: + * enabled - State of 1p remarking at real keep packet + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367d_vlan_realKeepRemarkEnable_set(rtk_enable_t enabled); + +/* Function Name: + * dal_rtl8367d_vlan_realKeepRemarkEnable_get + * Description: + * Get Real keep 1p remarking feature + * Input: + * None. + * Output: + * pEnabled - State of 1p remarking at real keep packet + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367d_vlan_realKeepRemarkEnable_get(rtk_enable_t *pEnabled); + +/* Function Name: + * dal_rtl8367d_vlan_reset + * Description: + * Reset VLAN + * Input: + * None. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8367d_vlan_reset(void); + +#endif /* __DAL_RTL8367D_VLAN_H__ */ diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/rtl8367d_asicdrv.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/rtl8367d_asicdrv.c new file mode 100644 index 00000000..691da93a --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/rtl8367d_asicdrv.c @@ -0,0 +1,641 @@ +/* + * Copyright (C) 2019 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTL8367D switch high-level API for RTL8367D + * Feature : + * + */ + +#include + +#if defined(RTK_X86_ASICDRV) +#include +#else +#include +#endif + +/*for driver verify testing only*/ +#ifdef CONFIG_RTL8367D_ASICDRV_TEST +#define CLE_VIRTUAL_REG_SIZE 0x10000 +rtk_uint16 CleVirtualReg[CLE_VIRTUAL_REG_SIZE]; +#endif + +#if defined(CONFIG_RTL865X_CLE) || defined (RTK_X86_CLE) +extern rtk_uint32 cleDebuggingDisplay; +#endif + +#ifdef EMBEDDED_SUPPORT +extern void setReg(rtk_uint16, rtk_uint16); +extern rtk_uint16 getReg(rtk_uint16); +#endif + +/* Function Name: + * rtl8367d_setAsicRegBit + * Description: + * Set a bit value of a specified register + * Input: + * reg - register's address + * bit - bit location + * value - value to set. It can be value 0 or 1. + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter + * Note: + * Set a bit of a specified register to 1 or 0. + */ +ret_t rtl8367d_setAsicRegBit(rtk_uint32 reg, rtk_uint32 bit, rtk_uint32 value) +{ + +#if defined(RTK_X86_ASICDRV) + rtk_uint32 regData; + ret_t retVal; + + if(bit >= RTL8367D_REGBITLENGTH) + return RT_ERR_INPUT; + + retVal = Access_Read(reg, 2, ®Data); + if(TRUE != retVal) + return RT_ERR_SMI; + + if(0x8367B == cleDebuggingDisplay) + PRINT("R[0x%4.4x]=0x%4.4x\n", reg, regData); + + if(value) + regData = regData | (1 << bit); + else + regData = regData & (~(1 << bit)); + + retVal = Access_Write(reg,2, regData); + if(TRUE != retVal) + return RT_ERR_SMI; + + if(0x8367B == cleDebuggingDisplay) + PRINT("W[0x%4.4x]=0x%4.4x\n", reg, regData); + + +#elif defined(CONFIG_RTL8367D_ASICDRV_TEST) + + if(bit >= RTL8367D_REGBITLENGTH) + return RT_ERR_INPUT; + + else if(reg >= CLE_VIRTUAL_REG_SIZE) + return RT_ERR_OUT_OF_RANGE; + + if(value) + { + CleVirtualReg[reg] = CleVirtualReg[reg] | (1 << bit); + } + else + { + CleVirtualReg[reg] = CleVirtualReg[reg] & (~(1 << bit)); + } + + if(0x8367B == cleDebuggingDisplay) + PRINT("W[0x%4.4x]=0x%4.4x\n", reg, CleVirtualReg[reg]); + +#elif defined(EMBEDDED_SUPPORT) + rtk_uint16 tmp; + + if(reg > RTL8367D_REGDATAMAX || value > 1) + return RT_ERR_INPUT; + + tmp = getReg(reg); + tmp &= (1 << bitIdx); + tmp |= (value << bitIdx); + setReg(reg, tmp); + +#else + rtk_uint32 regData; + ret_t retVal; + + if(bit >= RTL8367D_REGBITLENGTH) + return RT_ERR_INPUT; + + retVal = rtl8367d_smi_read(reg, ®Data); + if(retVal != RT_ERR_OK) + return RT_ERR_SMI; + + #ifdef CONFIG_RTL865X_CLE + if(0x8367B == cleDebuggingDisplay) + PRINT("R[0x%4.4x]=0x%4.4x\n", reg, regData); + #endif + if(value) + regData = regData | (1 << bit); + else + regData = regData & (~(1 << bit)); + + retVal = rtl8367d_smi_write(reg, regData); + if(retVal != RT_ERR_OK) + return RT_ERR_SMI; + + #ifdef CONFIG_RTL865X_CLE + if(0x8367B == cleDebuggingDisplay) + PRINT("W[0x%4.4x]=0x%4.4x\n", reg, regData); + #endif + +#endif + return RT_ERR_OK; +} +/* Function Name: + * rtl8367d_getAsicRegBit + * Description: + * Get a bit value of a specified register + * Input: + * reg - register's address + * bit - bit location + * value - value to get. + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter + * Note: + * None + */ +ret_t rtl8367d_getAsicRegBit(rtk_uint32 reg, rtk_uint32 bit, rtk_uint32 *pValue) +{ + +#if defined(RTK_X86_ASICDRV) + + rtk_uint32 regData; + ret_t retVal; + + if(bit >= RTL8367D_REGBITLENGTH) + return RT_ERR_INPUT; + + retVal = Access_Read(reg, 2, ®Data); + if(TRUE != retVal) + return RT_ERR_SMI; + + *pValue = (regData & (0x1 << bit)) >> bit; + + if(0x8367B == cleDebuggingDisplay) + PRINT("R[0x%4.4x]=0x%4.4x\n", reg, regData); + +#elif defined(CONFIG_RTL8367D_ASICDRV_TEST) + + if(bit >= RTL8367D_REGBITLENGTH) + return RT_ERR_INPUT; + + if(reg >= CLE_VIRTUAL_REG_SIZE) + return RT_ERR_OUT_OF_RANGE; + + *pValue = (CleVirtualReg[reg] & (0x1 << bit)) >> bit; + + if(0x8367B == cleDebuggingDisplay) + PRINT("R[0x%4.4x]=0x%4.4x\n", reg, CleVirtualReg[reg]); + +#elif defined(EMBEDDED_SUPPORT) + rtk_uint16 tmp; + + if(reg > RTL8367D_REGDATAMAX ) + return RT_ERR_INPUT; + + tmp = getReg(reg); + tmp = tmp >> bitIdx; + tmp &= 1; + *value = tmp; +#else + rtk_uint32 regData; + ret_t retVal; + + retVal = rtl8367d_smi_read(reg, ®Data); + if(retVal != RT_ERR_OK) + return RT_ERR_SMI; + + #ifdef CONFIG_RTL865X_CLE + if(0x8367B == cleDebuggingDisplay) + PRINT("R[0x%4.4x]=0x%4.4x\n", reg, regData); + #endif + + *pValue = (regData & (0x1 << bit)) >> bit; + +#endif + return RT_ERR_OK; +} +/* Function Name: + * rtl8367d_setAsicRegBits + * Description: + * Set bits value of a specified register + * Input: + * reg - register's address + * bits - bits mask for setting + * value - bits value for setting + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter + * Note: + * Set bits of a specified register to value. Both bits and value are be treated as bit-mask + */ +ret_t rtl8367d_setAsicRegBits(rtk_uint32 reg, rtk_uint32 bits, rtk_uint32 value) +{ + +#if defined(RTK_X86_ASICDRV) + + rtk_uint32 regData; + ret_t retVal; + rtk_uint32 bitsShift; + rtk_uint32 valueShifted; + + if(bits >= (1 << RTL8367D_REGBITLENGTH) ) + return RT_ERR_INPUT; + + bitsShift = 0; + while(!(bits & (1 << bitsShift))) + { + bitsShift++; + if(bitsShift >= RTL8367D_REGBITLENGTH) + return RT_ERR_INPUT; + } + + valueShifted = value << bitsShift; + if(valueShifted > RTL8367D_REGDATAMAX) + return RT_ERR_INPUT; + + retVal = Access_Read(reg, 2, ®Data); + if(TRUE != retVal) + return RT_ERR_SMI; + + if(0x8367B == cleDebuggingDisplay) + PRINT("R[0x%4.4x]=0x%4.4x\n", reg, regData); + + regData = regData & (~bits); + regData = regData | (valueShifted & bits); + + retVal = Access_Write(reg,2, regData); + if(TRUE != retVal) + return RT_ERR_SMI; + + if(0x8367B == cleDebuggingDisplay) + PRINT("W[0x%4.4x]=0x%4.4x\n", reg, regData); + +#elif defined(CONFIG_RTL8367D_ASICDRV_TEST) + rtk_uint32 regData; + rtk_uint32 bitsShift; + rtk_uint32 valueShifted; + + if(bits >= (1 << RTL8367D_REGBITLENGTH) ) + return RT_ERR_INPUT; + + bitsShift = 0; + while(!(bits & (1 << bitsShift))) + { + bitsShift++; + if(bitsShift >= RTL8367D_REGBITLENGTH) + return RT_ERR_INPUT; + } + valueShifted = value << bitsShift; + + if(valueShifted > RTL8367D_REGDATAMAX) + return RT_ERR_INPUT; + + if(reg >= CLE_VIRTUAL_REG_SIZE) + return RT_ERR_OUT_OF_RANGE; + + regData = CleVirtualReg[reg] & (~bits); + regData = regData | (valueShifted & bits); + + CleVirtualReg[reg] = regData; + + if(0x8367B == cleDebuggingDisplay) + PRINT("W[0x%4.4x]=0x%4.4x\n", reg, regData); + +#elif defined(EMBEDDED_SUPPORT) + rtk_uint32 regData; + rtk_uint32 bitsShift; + rtk_uint32 valueShifted; + + if(reg > RTL8367D_REGDATAMAX ) + return RT_ERR_INPUT; + + if(bits >= (1 << RTL8367D_REGBITLENGTH) ) + return RT_ERR_INPUT; + + bitsShift = 0; + while(!(bits & (1 << bitsShift))) + { + bitsShift++; + if(bitsShift >= RTL8367D_REGBITLENGTH) + return RT_ERR_INPUT; + } + + valueShifted = value << bitsShift; + if(valueShifted > RTL8367D_REGDATAMAX) + return RT_ERR_INPUT; + + regData = getReg(reg); + regData = regData & (~bits); + regData = regData | (valueShifted & bits); + + setReg(reg, regData); + +#else + rtk_uint32 regData; + ret_t retVal; + rtk_uint32 bitsShift; + rtk_uint32 valueShifted; + + if(bits >= (1 << RTL8367D_REGBITLENGTH) ) + return RT_ERR_INPUT; + + bitsShift = 0; + while(!(bits & (1 << bitsShift))) + { + bitsShift++; + if(bitsShift >= RTL8367D_REGBITLENGTH) + return RT_ERR_INPUT; + } + valueShifted = value << bitsShift; + + if(valueShifted > RTL8367D_REGDATAMAX) + return RT_ERR_INPUT; + + retVal = rtl8367d_smi_read(reg, ®Data); + if(retVal != RT_ERR_OK) + return RT_ERR_SMI; + #ifdef CONFIG_RTL865X_CLE + if(0x8367B == cleDebuggingDisplay) + PRINT("R[0x%4.4x]=0x%4.4x\n", reg, regData); + #endif + + regData = regData & (~bits); + regData = regData | (valueShifted & bits); + + retVal = rtl8367d_smi_write(reg, regData); + if(retVal != RT_ERR_OK) + return RT_ERR_SMI; + #ifdef CONFIG_RTL865X_CLE + if(0x8367B == cleDebuggingDisplay) + PRINT("W[0x%4.4x]=0x%4.4x\n", reg, regData); + #endif +#endif + return RT_ERR_OK; +} +/* Function Name: + * rtl8367d_getAsicRegBits + * Description: + * Get bits value of a specified register + * Input: + * reg - register's address + * bits - bits mask for setting + * value - bits value for setting + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter + * Note: + * None + */ +ret_t rtl8367d_getAsicRegBits(rtk_uint32 reg, rtk_uint32 bits, rtk_uint32 *pValue) +{ + +#if defined(RTK_X86_ASICDRV) + + rtk_uint32 regData; + ret_t retVal; + rtk_uint32 bitsShift; + + if(bits >= (1 << RTL8367D_REGBITLENGTH) ) + return RT_ERR_INPUT; + + bitsShift = 0; + while(!(bits & (1 << bitsShift))) + { + bitsShift++; + if(bitsShift >= RTL8367D_REGBITLENGTH) + return RT_ERR_INPUT; + } + + retVal = Access_Read(reg, 2, ®Data); + if(TRUE != retVal) + return RT_ERR_SMI; + + *pValue = (regData & bits) >> bitsShift; + + if(0x8367B == cleDebuggingDisplay) + PRINT("R[0x%4.4x]=0x%4.4x\n", reg, regData); + +#elif defined(CONFIG_RTL8367D_ASICDRV_TEST) + rtk_uint32 bitsShift; + + if(bits >= (1 << RTL8367D_REGBITLENGTH) ) + return RT_ERR_INPUT; + + bitsShift = 0; + while(!(bits & (1 << bitsShift))) + { + bitsShift++; + if(bitsShift >= RTL8367D_REGBITLENGTH) + return RT_ERR_INPUT; + } + + if(reg >= CLE_VIRTUAL_REG_SIZE) + return RT_ERR_OUT_OF_RANGE; + + *pValue = (CleVirtualReg[reg] & bits) >> bitsShift; + + if(0x8367B == cleDebuggingDisplay) + PRINT("R[0x%4.4x]=0x%4.4x\n", reg, CleVirtualReg[reg]); + +#elif defined(EMBEDDED_SUPPORT) + rtk_uint32 regData; + rtk_uint32 bitsShift; + + if(reg > RTL8367D_REGDATAMAX ) + return RT_ERR_INPUT; + + if(bits >= (1UL << RTL8367D_REGBITLENGTH) ) + return RT_ERR_INPUT; + + bitsShift = 0; + while(!(bits & (1UL << bitsShift))) + { + bitsShift++; + if(bitsShift >= RTL8367D_REGBITLENGTH) + return RT_ERR_INPUT; + } + + regData = getReg(reg); + *value = (regData & bits) >> bitsShift; + +#else + rtk_uint32 regData; + ret_t retVal; + rtk_uint32 bitsShift; + + if(bits>= (1<= RTL8367D_REGBITLENGTH) + return RT_ERR_INPUT; + } + + retVal = rtl8367d_smi_read(reg, ®Data); + if(retVal != RT_ERR_OK) return RT_ERR_SMI; + + *pValue = (regData & bits) >> bitsShift; + #ifdef CONFIG_RTL865X_CLE + if(0x8367B == cleDebuggingDisplay) + PRINT("R[0x%4.4x]=0x%4.4x\n",reg, regData); + #endif + +#endif + return RT_ERR_OK; +} +/* Function Name: + * rtl8367d_setAsicReg + * Description: + * Set content of asic register + * Input: + * reg - register's address + * value - Value setting to register + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * The value will be set to ASIC mapping address only and it is always return RT_ERR_OK while setting un-mapping address registers + */ +ret_t rtl8367d_setAsicReg(rtk_uint32 reg, rtk_uint32 value) +{ +#if defined(RTK_X86_ASICDRV)/*RTK-CNSD2-NickWu-20061222: for x86 compile*/ + + ret_t retVal; + + retVal = Access_Write(reg,2,value); + if(TRUE != retVal) return RT_ERR_SMI; + + if(0x8367B == cleDebuggingDisplay) + PRINT("W[0x%4.4x]=0x%4.4x\n",reg,value); + +#elif defined(CONFIG_RTL8367D_ASICDRV_TEST) + + /*MIBs emulating*/ + if(reg == RTL8367D_REG_MIB_ADDRESS) + { + CleVirtualReg[RTL8367D_REG_MIB_COUNTER0] = 0x1; + CleVirtualReg[RTL8367D_REG_MIB_COUNTER0+1] = 0x2; + CleVirtualReg[RTL8367D_REG_MIB_COUNTER0+2] = 0x3; + CleVirtualReg[RTL8367D_REG_MIB_COUNTER0+3] = 0x4; + } + + if(reg >= CLE_VIRTUAL_REG_SIZE) + return RT_ERR_OUT_OF_RANGE; + + CleVirtualReg[reg] = value; + + if(0x8367B == cleDebuggingDisplay) + PRINT("W[0x%4.4x]=0x%4.4x\n",reg,CleVirtualReg[reg]); + +#elif defined(EMBEDDED_SUPPORT) + if(reg > RTL8367D_REGDATAMAX || value > RTL8367D_REGDATAMAX ) + return RT_ERR_INPUT; + + setReg(reg, value); + +#else + ret_t retVal; + + retVal = rtl8367d_smi_write(reg, value); + if(retVal != RT_ERR_OK) + return RT_ERR_SMI; + #ifdef CONFIG_RTL865X_CLE + if(0x8367B == cleDebuggingDisplay) + PRINT("W[0x%4.4x]=0x%4.4x\n",reg,value); + #endif + +#endif + + return RT_ERR_OK; +} +/* Function Name: + * rtl8367d_getAsicReg + * Description: + * Get content of asic register + * Input: + * reg - register's address + * value - Value setting to register + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * Value 0x0000 will be returned for ASIC un-mapping address + */ +ret_t rtl8367d_getAsicReg(rtk_uint32 reg, rtk_uint32 *pValue) +{ + +#if defined(RTK_X86_ASICDRV) + + rtk_uint32 regData; + ret_t retVal; + + retVal = Access_Read(reg, 2, ®Data); + if(TRUE != retVal) + return RT_ERR_SMI; + + *pValue = regData; + + if(0x8367B == cleDebuggingDisplay) + PRINT("R[0x%4.4x]=0x%4.4x\n", reg, regData); + +#elif defined(CONFIG_RTL8367D_ASICDRV_TEST) + if(reg >= CLE_VIRTUAL_REG_SIZE) + return RT_ERR_OUT_OF_RANGE; + + *pValue = CleVirtualReg[reg]; + + if(0x8367B == cleDebuggingDisplay) + PRINT("R[0x%4.4x]=0x%4.4x\n", reg, CleVirtualReg[reg]); + +#elif defined(EMBEDDED_SUPPORT) + if(reg > RTL8367D_REGDATAMAX ) + return RT_ERR_INPUT; + + *value = getReg(reg); + +#else + rtk_uint32 regData; + ret_t retVal; + + retVal = rtl8367d_smi_read(reg, ®Data); + if(retVal != RT_ERR_OK) + return RT_ERR_SMI; + + *pValue = regData; + #ifdef CONFIG_RTL865X_CLE + if(0x8367B == cleDebuggingDisplay) + PRINT("R[0x%4.4x]=0x%4.4x\n", reg, regData); + #endif + +#endif + + return RT_ERR_OK; +} + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/rtl8367d_asicdrv.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/rtl8367d_asicdrv.h new file mode 100644 index 00000000..e33f6a3f --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/rtl8367d_asicdrv.h @@ -0,0 +1,76 @@ +#ifndef _RTL8367D_ASICDRV_H_ +#define _RTL8367D_ASICDRV_H_ + +#include +#include +#include + +#define RTL8367D_REGBITLENGTH 16 +#define RTL8367D_REGDATAMAX 0xFFFF + +#define RTL8367D_QOS_RATE_INPUT_MAX (0x1FFFF * 8) +#define RTL8367D_QOS_RATE_INPUT_MAX_HSG (0x7FFFF * 8) +#define RTL8367D_QOS_PPS_INPUT_MAX (0x7FFFF) + +#define RTL8367D_PORTNO 11 +#define RTL8367D_PORTIDMAX (RTL8367D_PORTNO-1) +#define RTL8367D_PMSKMAX ((1<<(RTL8367D_PORTNO))-1) +#define RTL8367D_PORTMASK 0xFF + +#define RTL8367D_PRIMAX 7 +#define RTL8367D_DSCPMAX 63 + +#define RTL8367D_VIDMAX 0xFFF +#define RTL8367D_FIDMAX 3 +#define RTL8367D_MSTIMAX 3 + +#define RTL8367D_VLAN_4KTABLE_LEN (2) +#define RTL8367D_VLAN_BUSY_CHECK_NO (10) + +#define RTL8367D_QUEUENO 8 +#define RTL8367D_QIDMAX (RTL8367D_QUEUENO-1) + +#define RTL8367D_TB_OP_READ 0 +#define RTL8367D_TB_OP_WRITE 1 + +#define RTL8367D_TB_TARGET_ACLRULE 1 +#define RTL8367D_TB_TARGET_ACLACT 2 +#define RTL8367D_TB_TARGET_CVLAN 3 +#define RTL8367D_TB_TARGET_L2 4 +#define RTL8367D_TB_TARGET_IGMP_GROUP 5 + +#define RTL8367D_C2SIDXMAX 31 +#define RTL8367D_SP2CMAX 63 + +/*======================================================================= + * Enum + *========================================================================*/ + + +#define RTL8367D_TABLE_ACCESS_REG_DATA(op, target) ((op << 3) | target) + +/*======================================================================= + * Structures + *========================================================================*/ + + +#ifdef __cplusplus +extern "C" { +#endif +extern ret_t rtl8367d_setAsicRegBit(rtk_uint32 reg, rtk_uint32 bit, rtk_uint32 value); +extern ret_t rtl8367d_getAsicRegBit(rtk_uint32 reg, rtk_uint32 bit, rtk_uint32 *pValue); + +extern ret_t rtl8367d_setAsicRegBits(rtk_uint32 reg, rtk_uint32 bits, rtk_uint32 value); +extern ret_t rtl8367d_getAsicRegBits(rtk_uint32 reg, rtk_uint32 bits, rtk_uint32 *pValue); + +extern ret_t rtl8367d_setAsicReg(rtk_uint32 reg, rtk_uint32 value); +extern ret_t rtl8367d_getAsicReg(rtk_uint32 reg, rtk_uint32 *pValue); + +#ifdef __cplusplus +} +#endif + + + +#endif /*#ifndef _RTL8367D_ASICDRV_H_*/ + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/rtl8367d_reg.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/rtl8367d_reg.h new file mode 100644 index 00000000..e35e8347 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/rtl8367d_reg.h @@ -0,0 +1,12393 @@ +#ifndef _RTL8367D_REG_H_ +#define _RTL8367D_REG_H_ + +/************************************************************ +auto-generated register address and field data +*************************************************************/ + +/* (16'h0000)port_reg */ + +#define RTL8367D_REG_PORT0_CGST_HALF_CFG 0x0000 +#define RTL8367D_PORT0_CGST_HALF_CFG_CONGESTION_TIME_OFFSET 4 +#define RTL8367D_PORT0_CGST_HALF_CFG_CONGESTION_TIME_MASK 0xF0 +#define RTL8367D_PORT0_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_OFFSET 0 +#define RTL8367D_PORT0_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_MASK 0xF + +#define RTL8367D_REG_PKTGEN_PORT0_TIMER 0x000d +#define RTL8367D_PKTGEN_PORT0_TIMER_TIMER_OFFSET 4 +#define RTL8367D_PKTGEN_PORT0_TIMER_TIMER_MASK 0xF0 +#define RTL8367D_PKTGEN_PORT0_TIMER_RX_DMA_ERR_FLAG_OFFSET 3 +#define RTL8367D_PKTGEN_PORT0_TIMER_RX_DMA_ERR_FLAG_MASK 0x8 + +#define RTL8367D_REG_PORT0_MISC_CFG 0x000e +#define RTL8367D_PORT0_MISC_CFG_SMALL_TAG_IPG_OFFSET 15 +#define RTL8367D_PORT0_MISC_CFG_SMALL_TAG_IPG_MASK 0x8000 +#define RTL8367D_PORT0_MISC_CFG_TX_ITFSP_MODE_OFFSET 14 +#define RTL8367D_PORT0_MISC_CFG_TX_ITFSP_MODE_MASK 0x4000 +#define RTL8367D_PORT0_MISC_CFG_DOT1Q_REMARK_ENABLE_OFFSET 12 +#define RTL8367D_PORT0_MISC_CFG_DOT1Q_REMARK_ENABLE_MASK 0x1000 +#define RTL8367D_PORT0_MISC_CFG_INGRESSBW_FLOWCTRL_OFFSET 11 +#define RTL8367D_PORT0_MISC_CFG_INGRESSBW_FLOWCTRL_MASK 0x800 +#define RTL8367D_PORT0_MISC_CFG_INGRESSBW_IFG_OFFSET 10 +#define RTL8367D_PORT0_MISC_CFG_INGRESSBW_IFG_MASK 0x400 +#define RTL8367D_PORT0_MISC_CFG_RX_SPC_OFFSET 9 +#define RTL8367D_PORT0_MISC_CFG_RX_SPC_MASK 0x200 +#define RTL8367D_PORT0_MISC_CFG_CRC_SKIP_OFFSET 8 +#define RTL8367D_PORT0_MISC_CFG_CRC_SKIP_MASK 0x100 +#define RTL8367D_PORT0_MISC_CFG_MAC_LOOPBACK_OFFSET 6 +#define RTL8367D_PORT0_MISC_CFG_MAC_LOOPBACK_MASK 0x40 +#define RTL8367D_PORT0_MISC_CFG_VLAN_EGRESS_MODE_OFFSET 4 +#define RTL8367D_PORT0_MISC_CFG_VLAN_EGRESS_MODE_MASK 0x30 +#define RTL8367D_PORT0_MISC_CFG_CONGESTION_SUSTAIN_TIME_OFFSET 0 +#define RTL8367D_PORT0_MISC_CFG_CONGESTION_SUSTAIN_TIME_MASK 0xF + +#define RTL8367D_REG_INGRESSBW_PORT0_RATE_CTRL0 0x000f + +#define RTL8367D_REG_INGRESSBW_PORT0_RATE_CTRL1 0x0010 +#define RTL8367D_INGRESSBW_PORT0_RATE_CTRL1_BYPASS_ABILITY_LOCK_OFFSET 3 +#define RTL8367D_INGRESSBW_PORT0_RATE_CTRL1_BYPASS_ABILITY_LOCK_MASK 0x8 +#define RTL8367D_INGRESSBW_PORT0_RATE_CTRL1_INGRESSBW_RATE16_OFFSET 0 +#define RTL8367D_INGRESSBW_PORT0_RATE_CTRL1_INGRESSBW_RATE16_MASK 0x7 + +#define RTL8367D_REG_PORT0_FORCE_RATE0 0x0011 + +#define RTL8367D_REG_PORT0_FORCE_RATE1 0x0012 + +#define RTL8367D_REG_PORT0_CURENT_RATE0 0x0013 + +#define RTL8367D_REG_PORT0_CURENT_RATE1 0x0014 + +#define RTL8367D_REG_PORT0_PAGE_COUNTER 0x0015 +#define RTL8367D_PORT0_PAGE_COUNTER_OFFSET 0 +#define RTL8367D_PORT0_PAGE_COUNTER_MASK 0x7F + +#define RTL8367D_REG_PAGEMETER_PORT0_CTRL0 0x0016 + +#define RTL8367D_REG_PAGEMETER_PORT0_CTRL1 0x0017 + +#define RTL8367D_REG_PORT0_EEECFG 0x0018 +#define RTL8367D_PORT0_EEECFG_EEE_PORT_TX_EN_OFFSET 9 +#define RTL8367D_PORT0_EEECFG_EEE_PORT_TX_EN_MASK 0x200 +#define RTL8367D_PORT0_EEECFG_EEE_PORT_RX_EN_OFFSET 8 +#define RTL8367D_PORT0_EEECFG_EEE_PORT_RX_EN_MASK 0x100 +#define RTL8367D_PORT0_EEECFG_EEE_LPI_OFFSET 5 +#define RTL8367D_PORT0_EEECFG_EEE_LPI_MASK 0x20 +#define RTL8367D_PORT0_EEECFG_EEE_TX_STS_OFFSET 4 +#define RTL8367D_PORT0_EEECFG_EEE_TX_STS_MASK 0x10 +#define RTL8367D_PORT0_EEECFG_EEE_RX_STS_OFFSET 3 +#define RTL8367D_PORT0_EEECFG_EEE_RX_STS_MASK 0x8 +#define RTL8367D_PORT0_EEECFG_EEE_PAUSE_INDICATOR_OFFSET 2 +#define RTL8367D_PORT0_EEECFG_EEE_PAUSE_INDICATOR_MASK 0x4 + +#define RTL8367D_REG_PORT0_EEETXMTR 0x0019 + +#define RTL8367D_REG_PORT0_EEERXMTR 0x001a + +#define RTL8367D_REG_PORT0_DUMMY 0x001e + +#define RTL8367D_REG_P0_MSIC1 0x001f +#define RTL8367D_P0_MSIC1_OFFSET 0 +#define RTL8367D_P0_MSIC1_MASK 0x1 + +#define RTL8367D_REG_PORT1_CGST_HALF_CFG 0x0020 +#define RTL8367D_PORT1_CGST_HALF_CFG_CONGESTION_TIME_OFFSET 4 +#define RTL8367D_PORT1_CGST_HALF_CFG_CONGESTION_TIME_MASK 0xF0 +#define RTL8367D_PORT1_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_OFFSET 0 +#define RTL8367D_PORT1_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_MASK 0xF + +#define RTL8367D_REG_PKTGEN_PORT1_TIMER 0x002d +#define RTL8367D_PKTGEN_PORT1_TIMER_TIMER_OFFSET 4 +#define RTL8367D_PKTGEN_PORT1_TIMER_TIMER_MASK 0xF0 +#define RTL8367D_PKTGEN_PORT1_TIMER_RX_DMA_ERR_FLAG_OFFSET 3 +#define RTL8367D_PKTGEN_PORT1_TIMER_RX_DMA_ERR_FLAG_MASK 0x8 + +#define RTL8367D_REG_PORT1_MISC_CFG 0x002e +#define RTL8367D_PORT1_MISC_CFG_SMALL_TAG_IPG_OFFSET 15 +#define RTL8367D_PORT1_MISC_CFG_SMALL_TAG_IPG_MASK 0x8000 +#define RTL8367D_PORT1_MISC_CFG_TX_ITFSP_MODE_OFFSET 14 +#define RTL8367D_PORT1_MISC_CFG_TX_ITFSP_MODE_MASK 0x4000 +#define RTL8367D_PORT1_MISC_CFG_DOT1Q_REMARK_ENABLE_OFFSET 12 +#define RTL8367D_PORT1_MISC_CFG_DOT1Q_REMARK_ENABLE_MASK 0x1000 +#define RTL8367D_PORT1_MISC_CFG_INGRESSBW_FLOWCTRL_OFFSET 11 +#define RTL8367D_PORT1_MISC_CFG_INGRESSBW_FLOWCTRL_MASK 0x800 +#define RTL8367D_PORT1_MISC_CFG_INGRESSBW_IFG_OFFSET 10 +#define RTL8367D_PORT1_MISC_CFG_INGRESSBW_IFG_MASK 0x400 +#define RTL8367D_PORT1_MISC_CFG_RX_SPC_OFFSET 9 +#define RTL8367D_PORT1_MISC_CFG_RX_SPC_MASK 0x200 +#define RTL8367D_PORT1_MISC_CFG_CRC_SKIP_OFFSET 8 +#define RTL8367D_PORT1_MISC_CFG_CRC_SKIP_MASK 0x100 +#define RTL8367D_PORT1_MISC_CFG_MAC_LOOPBACK_OFFSET 6 +#define RTL8367D_PORT1_MISC_CFG_MAC_LOOPBACK_MASK 0x40 +#define RTL8367D_PORT1_MISC_CFG_VLAN_EGRESS_MODE_OFFSET 4 +#define RTL8367D_PORT1_MISC_CFG_VLAN_EGRESS_MODE_MASK 0x30 +#define RTL8367D_PORT1_MISC_CFG_CONGESTION_SUSTAIN_TIME_OFFSET 0 +#define RTL8367D_PORT1_MISC_CFG_CONGESTION_SUSTAIN_TIME_MASK 0xF + +#define RTL8367D_REG_INGRESSBW_PORT1_RATE_CTRL0 0x002f + +#define RTL8367D_REG_INGRESSBW_PORT1_RATE_CTRL1 0x0030 +#define RTL8367D_INGRESSBW_PORT1_RATE_CTRL1_BYPASS_ABILITY_LOCK_OFFSET 3 +#define RTL8367D_INGRESSBW_PORT1_RATE_CTRL1_BYPASS_ABILITY_LOCK_MASK 0x8 +#define RTL8367D_INGRESSBW_PORT1_RATE_CTRL1_INGRESSBW_RATE16_OFFSET 0 +#define RTL8367D_INGRESSBW_PORT1_RATE_CTRL1_INGRESSBW_RATE16_MASK 0x7 + +#define RTL8367D_REG_PORT1_FORCE_RATE0 0x0031 + +#define RTL8367D_REG_PORT1_FORCE_RATE1 0x0032 + +#define RTL8367D_REG_PORT1_CURENT_RATE0 0x0033 + +#define RTL8367D_REG_PORT1_CURENT_RATE1 0x0034 + +#define RTL8367D_REG_PORT1_PAGE_COUNTER 0x0035 +#define RTL8367D_PORT1_PAGE_COUNTER_OFFSET 0 +#define RTL8367D_PORT1_PAGE_COUNTER_MASK 0x7F + +#define RTL8367D_REG_PAGEMETER_PORT1_CTRL0 0x0036 + +#define RTL8367D_REG_PAGEMETER_PORT1_CTRL1 0x0037 + +#define RTL8367D_REG_PORT1_EEECFG 0x0038 +#define RTL8367D_PORT1_EEECFG_EEE_PORT_TX_EN_OFFSET 9 +#define RTL8367D_PORT1_EEECFG_EEE_PORT_TX_EN_MASK 0x200 +#define RTL8367D_PORT1_EEECFG_EEE_PORT_RX_EN_OFFSET 8 +#define RTL8367D_PORT1_EEECFG_EEE_PORT_RX_EN_MASK 0x100 +#define RTL8367D_PORT1_EEECFG_EEE_LPI_OFFSET 5 +#define RTL8367D_PORT1_EEECFG_EEE_LPI_MASK 0x20 +#define RTL8367D_PORT1_EEECFG_EEE_TX_STS_OFFSET 4 +#define RTL8367D_PORT1_EEECFG_EEE_TX_STS_MASK 0x10 +#define RTL8367D_PORT1_EEECFG_EEE_RX_STS_OFFSET 3 +#define RTL8367D_PORT1_EEECFG_EEE_RX_STS_MASK 0x8 +#define RTL8367D_PORT1_EEECFG_EEE_PAUSE_INDICATOR_OFFSET 2 +#define RTL8367D_PORT1_EEECFG_EEE_PAUSE_INDICATOR_MASK 0x4 + +#define RTL8367D_REG_PORT1_EEETXMTR 0x0039 + +#define RTL8367D_REG_PORT1_EEERXMTR 0x003a + +#define RTL8367D_REG_PORT1_DUMMY 0x003e + +#define RTL8367D_REG_P1_MSIC1 0x003f +#define RTL8367D_P1_MSIC1_OFFSET 0 +#define RTL8367D_P1_MSIC1_MASK 0x1 + +#define RTL8367D_REG_PORT2_CGST_HALF_CFG 0x0040 +#define RTL8367D_PORT2_CGST_HALF_CFG_CONGESTION_TIME_OFFSET 4 +#define RTL8367D_PORT2_CGST_HALF_CFG_CONGESTION_TIME_MASK 0xF0 +#define RTL8367D_PORT2_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_OFFSET 0 +#define RTL8367D_PORT2_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_MASK 0xF + +#define RTL8367D_REG_PKTGEN_PORT2_TIMER 0x004d +#define RTL8367D_PKTGEN_PORT2_TIMER_TIMER_OFFSET 4 +#define RTL8367D_PKTGEN_PORT2_TIMER_TIMER_MASK 0xF0 +#define RTL8367D_PKTGEN_PORT2_TIMER_RX_DMA_ERR_FLAG_OFFSET 3 +#define RTL8367D_PKTGEN_PORT2_TIMER_RX_DMA_ERR_FLAG_MASK 0x8 + +#define RTL8367D_REG_PORT2_MISC_CFG 0x004e +#define RTL8367D_PORT2_MISC_CFG_SMALL_TAG_IPG_OFFSET 15 +#define RTL8367D_PORT2_MISC_CFG_SMALL_TAG_IPG_MASK 0x8000 +#define RTL8367D_PORT2_MISC_CFG_TX_ITFSP_MODE_OFFSET 14 +#define RTL8367D_PORT2_MISC_CFG_TX_ITFSP_MODE_MASK 0x4000 +#define RTL8367D_PORT2_MISC_CFG_DOT1Q_REMARK_ENABLE_OFFSET 12 +#define RTL8367D_PORT2_MISC_CFG_DOT1Q_REMARK_ENABLE_MASK 0x1000 +#define RTL8367D_PORT2_MISC_CFG_INGRESSBW_FLOWCTRL_OFFSET 11 +#define RTL8367D_PORT2_MISC_CFG_INGRESSBW_FLOWCTRL_MASK 0x800 +#define RTL8367D_PORT2_MISC_CFG_INGRESSBW_IFG_OFFSET 10 +#define RTL8367D_PORT2_MISC_CFG_INGRESSBW_IFG_MASK 0x400 +#define RTL8367D_PORT2_MISC_CFG_RX_SPC_OFFSET 9 +#define RTL8367D_PORT2_MISC_CFG_RX_SPC_MASK 0x200 +#define RTL8367D_PORT2_MISC_CFG_CRC_SKIP_OFFSET 8 +#define RTL8367D_PORT2_MISC_CFG_CRC_SKIP_MASK 0x100 +#define RTL8367D_PORT2_MISC_CFG_MAC_LOOPBACK_OFFSET 6 +#define RTL8367D_PORT2_MISC_CFG_MAC_LOOPBACK_MASK 0x40 +#define RTL8367D_PORT2_MISC_CFG_VLAN_EGRESS_MODE_OFFSET 4 +#define RTL8367D_PORT2_MISC_CFG_VLAN_EGRESS_MODE_MASK 0x30 +#define RTL8367D_PORT2_MISC_CFG_CONGESTION_SUSTAIN_TIME_OFFSET 0 +#define RTL8367D_PORT2_MISC_CFG_CONGESTION_SUSTAIN_TIME_MASK 0xF + +#define RTL8367D_REG_INGRESSBW_PORT2_RATE_CTRL0 0x004f + +#define RTL8367D_REG_INGRESSBW_PORT2_RATE_CTRL1 0x0050 +#define RTL8367D_INGRESSBW_PORT2_RATE_CTRL1_BYPASS_ABILITY_LOCK_OFFSET 3 +#define RTL8367D_INGRESSBW_PORT2_RATE_CTRL1_BYPASS_ABILITY_LOCK_MASK 0x8 +#define RTL8367D_INGRESSBW_PORT2_RATE_CTRL1_INGRESSBW_RATE16_OFFSET 0 +#define RTL8367D_INGRESSBW_PORT2_RATE_CTRL1_INGRESSBW_RATE16_MASK 0x7 + +#define RTL8367D_REG_PORT2_FORCE_RATE0 0x0051 + +#define RTL8367D_REG_PORT2_FORCE_RATE1 0x0052 + +#define RTL8367D_REG_PORT2_CURENT_RATE0 0x0053 + +#define RTL8367D_REG_PORT2_CURENT_RATE1 0x0054 + +#define RTL8367D_REG_PORT2_PAGE_COUNTER 0x0055 +#define RTL8367D_PORT2_PAGE_COUNTER_OFFSET 0 +#define RTL8367D_PORT2_PAGE_COUNTER_MASK 0x7F + +#define RTL8367D_REG_PAGEMETER_PORT2_CTRL0 0x0056 + +#define RTL8367D_REG_PAGEMETER_PORT2_CTRL1 0x0057 + +#define RTL8367D_REG_PORT2_EEECFG 0x0058 +#define RTL8367D_PORT2_EEECFG_EEE_PORT_TX_EN_OFFSET 9 +#define RTL8367D_PORT2_EEECFG_EEE_PORT_TX_EN_MASK 0x200 +#define RTL8367D_PORT2_EEECFG_EEE_PORT_RX_EN_OFFSET 8 +#define RTL8367D_PORT2_EEECFG_EEE_PORT_RX_EN_MASK 0x100 +#define RTL8367D_PORT2_EEECFG_EEE_LPI_OFFSET 5 +#define RTL8367D_PORT2_EEECFG_EEE_LPI_MASK 0x20 +#define RTL8367D_PORT2_EEECFG_EEE_TX_STS_OFFSET 4 +#define RTL8367D_PORT2_EEECFG_EEE_TX_STS_MASK 0x10 +#define RTL8367D_PORT2_EEECFG_EEE_RX_STS_OFFSET 3 +#define RTL8367D_PORT2_EEECFG_EEE_RX_STS_MASK 0x8 +#define RTL8367D_PORT2_EEECFG_EEE_PAUSE_INDICATOR_OFFSET 2 +#define RTL8367D_PORT2_EEECFG_EEE_PAUSE_INDICATOR_MASK 0x4 + +#define RTL8367D_REG_PORT2_EEETXMTR 0x0059 + +#define RTL8367D_REG_PORT2_EEERXMTR 0x005a + +#define RTL8367D_REG_PORT2_DUMMY 0x005e + +#define RTL8367D_REG_P2_MSIC1 0x005f +#define RTL8367D_P2_MSIC1_OFFSET 0 +#define RTL8367D_P2_MSIC1_MASK 0x1 + +#define RTL8367D_REG_PORT3_CGST_HALF_CFG 0x0060 +#define RTL8367D_PORT3_CGST_HALF_CFG_CONGESTION_TIME_OFFSET 4 +#define RTL8367D_PORT3_CGST_HALF_CFG_CONGESTION_TIME_MASK 0xF0 +#define RTL8367D_PORT3_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_OFFSET 0 +#define RTL8367D_PORT3_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_MASK 0xF + +#define RTL8367D_REG_PKTGEN_PORT3_TIMER 0x006d +#define RTL8367D_PKTGEN_PORT3_TIMER_TIMER_OFFSET 4 +#define RTL8367D_PKTGEN_PORT3_TIMER_TIMER_MASK 0xF0 +#define RTL8367D_PKTGEN_PORT3_TIMER_RX_DMA_ERR_FLAG_OFFSET 3 +#define RTL8367D_PKTGEN_PORT3_TIMER_RX_DMA_ERR_FLAG_MASK 0x8 + +#define RTL8367D_REG_PORT3_MISC_CFG 0x006e +#define RTL8367D_PORT3_MISC_CFG_SMALL_TAG_IPG_OFFSET 15 +#define RTL8367D_PORT3_MISC_CFG_SMALL_TAG_IPG_MASK 0x8000 +#define RTL8367D_PORT3_MISC_CFG_TX_ITFSP_MODE_OFFSET 14 +#define RTL8367D_PORT3_MISC_CFG_TX_ITFSP_MODE_MASK 0x4000 +#define RTL8367D_PORT3_MISC_CFG_DOT1Q_REMARK_ENABLE_OFFSET 12 +#define RTL8367D_PORT3_MISC_CFG_DOT1Q_REMARK_ENABLE_MASK 0x1000 +#define RTL8367D_PORT3_MISC_CFG_INGRESSBW_FLOWCTRL_OFFSET 11 +#define RTL8367D_PORT3_MISC_CFG_INGRESSBW_FLOWCTRL_MASK 0x800 +#define RTL8367D_PORT3_MISC_CFG_INGRESSBW_IFG_OFFSET 10 +#define RTL8367D_PORT3_MISC_CFG_INGRESSBW_IFG_MASK 0x400 +#define RTL8367D_PORT3_MISC_CFG_RX_SPC_OFFSET 9 +#define RTL8367D_PORT3_MISC_CFG_RX_SPC_MASK 0x200 +#define RTL8367D_PORT3_MISC_CFG_CRC_SKIP_OFFSET 8 +#define RTL8367D_PORT3_MISC_CFG_CRC_SKIP_MASK 0x100 +#define RTL8367D_PORT3_MISC_CFG_MAC_LOOPBACK_OFFSET 6 +#define RTL8367D_PORT3_MISC_CFG_MAC_LOOPBACK_MASK 0x40 +#define RTL8367D_PORT3_MISC_CFG_VLAN_EGRESS_MODE_OFFSET 4 +#define RTL8367D_PORT3_MISC_CFG_VLAN_EGRESS_MODE_MASK 0x30 +#define RTL8367D_PORT3_MISC_CFG_CONGESTION_SUSTAIN_TIME_OFFSET 0 +#define RTL8367D_PORT3_MISC_CFG_CONGESTION_SUSTAIN_TIME_MASK 0xF + +#define RTL8367D_REG_INGRESSBW_PORT3_RATE_CTRL0 0x006f + +#define RTL8367D_REG_INGRESSBW_PORT3_RATE_CTRL1 0x0070 +#define RTL8367D_INGRESSBW_PORT3_RATE_CTRL1_BYPASS_ABILITY_LOCK_OFFSET 3 +#define RTL8367D_INGRESSBW_PORT3_RATE_CTRL1_BYPASS_ABILITY_LOCK_MASK 0x8 +#define RTL8367D_INGRESSBW_PORT3_RATE_CTRL1_INGRESSBW_RATE16_OFFSET 0 +#define RTL8367D_INGRESSBW_PORT3_RATE_CTRL1_INGRESSBW_RATE16_MASK 0x7 + +#define RTL8367D_REG_PORT3_FORCE_RATE0 0x0071 + +#define RTL8367D_REG_PORT3_FORCE_RATE1 0x0072 + +#define RTL8367D_REG_PORT3_CURENT_RATE0 0x0073 + +#define RTL8367D_REG_PORT3_CURENT_RATE1 0x0074 + +#define RTL8367D_REG_PORT3_PAGE_COUNTER 0x0075 +#define RTL8367D_PORT3_PAGE_COUNTER_OFFSET 0 +#define RTL8367D_PORT3_PAGE_COUNTER_MASK 0x7F + +#define RTL8367D_REG_PAGEMETER_PORT3_CTRL0 0x0076 + +#define RTL8367D_REG_PAGEMETER_PORT3_CTRL1 0x0077 + +#define RTL8367D_REG_PORT3_EEECFG 0x0078 +#define RTL8367D_PORT3_EEECFG_EEE_PORT_TX_EN_OFFSET 9 +#define RTL8367D_PORT3_EEECFG_EEE_PORT_TX_EN_MASK 0x200 +#define RTL8367D_PORT3_EEECFG_EEE_PORT_RX_EN_OFFSET 8 +#define RTL8367D_PORT3_EEECFG_EEE_PORT_RX_EN_MASK 0x100 +#define RTL8367D_PORT3_EEECFG_EEE_LPI_OFFSET 5 +#define RTL8367D_PORT3_EEECFG_EEE_LPI_MASK 0x20 +#define RTL8367D_PORT3_EEECFG_EEE_TX_STS_OFFSET 4 +#define RTL8367D_PORT3_EEECFG_EEE_TX_STS_MASK 0x10 +#define RTL8367D_PORT3_EEECFG_EEE_RX_STS_OFFSET 3 +#define RTL8367D_PORT3_EEECFG_EEE_RX_STS_MASK 0x8 +#define RTL8367D_PORT3_EEECFG_EEE_PAUSE_INDICATOR_OFFSET 2 +#define RTL8367D_PORT3_EEECFG_EEE_PAUSE_INDICATOR_MASK 0x4 + +#define RTL8367D_REG_PORT3_EEETXMTR 0x0079 + +#define RTL8367D_REG_PORT3_EEERXMTR 0x007a + +#define RTL8367D_REG_PORT3_DUMMY 0x007e + +#define RTL8367D_REG_P3_MSIC1 0x007f +#define RTL8367D_P3_MSIC1_OFFSET 0 +#define RTL8367D_P3_MSIC1_MASK 0x1 + +#define RTL8367D_REG_PORT4_CGST_HALF_CFG 0x0080 +#define RTL8367D_PORT4_CGST_HALF_CFG_CONGESTION_TIME_OFFSET 4 +#define RTL8367D_PORT4_CGST_HALF_CFG_CONGESTION_TIME_MASK 0xF0 +#define RTL8367D_PORT4_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_OFFSET 0 +#define RTL8367D_PORT4_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_MASK 0xF + +#define RTL8367D_REG_PKTGEN_PORT4_TIMER 0x008d +#define RTL8367D_PKTGEN_PORT4_TIMER_TIMER_OFFSET 4 +#define RTL8367D_PKTGEN_PORT4_TIMER_TIMER_MASK 0xF0 +#define RTL8367D_PKTGEN_PORT4_TIMER_RX_DMA_ERR_FLAG_OFFSET 3 +#define RTL8367D_PKTGEN_PORT4_TIMER_RX_DMA_ERR_FLAG_MASK 0x8 + +#define RTL8367D_REG_PORT4_MISC_CFG 0x008e +#define RTL8367D_PORT4_MISC_CFG_SMALL_TAG_IPG_OFFSET 15 +#define RTL8367D_PORT4_MISC_CFG_SMALL_TAG_IPG_MASK 0x8000 +#define RTL8367D_PORT4_MISC_CFG_TX_ITFSP_MODE_OFFSET 14 +#define RTL8367D_PORT4_MISC_CFG_TX_ITFSP_MODE_MASK 0x4000 +#define RTL8367D_PORT4_MISC_CFG_DOT1Q_REMARK_ENABLE_OFFSET 12 +#define RTL8367D_PORT4_MISC_CFG_DOT1Q_REMARK_ENABLE_MASK 0x1000 +#define RTL8367D_PORT4_MISC_CFG_INGRESSBW_FLOWCTRL_OFFSET 11 +#define RTL8367D_PORT4_MISC_CFG_INGRESSBW_FLOWCTRL_MASK 0x800 +#define RTL8367D_PORT4_MISC_CFG_INGRESSBW_IFG_OFFSET 10 +#define RTL8367D_PORT4_MISC_CFG_INGRESSBW_IFG_MASK 0x400 +#define RTL8367D_PORT4_MISC_CFG_RX_SPC_OFFSET 9 +#define RTL8367D_PORT4_MISC_CFG_RX_SPC_MASK 0x200 +#define RTL8367D_PORT4_MISC_CFG_CRC_SKIP_OFFSET 8 +#define RTL8367D_PORT4_MISC_CFG_CRC_SKIP_MASK 0x100 +#define RTL8367D_PORT4_MISC_CFG_MAC_LOOPBACK_OFFSET 6 +#define RTL8367D_PORT4_MISC_CFG_MAC_LOOPBACK_MASK 0x40 +#define RTL8367D_PORT4_MISC_CFG_VLAN_EGRESS_MODE_OFFSET 4 +#define RTL8367D_PORT4_MISC_CFG_VLAN_EGRESS_MODE_MASK 0x30 +#define RTL8367D_PORT4_MISC_CFG_CONGESTION_SUSTAIN_TIME_OFFSET 0 +#define RTL8367D_PORT4_MISC_CFG_CONGESTION_SUSTAIN_TIME_MASK 0xF + +#define RTL8367D_REG_INGRESSBW_PORT4_RATE_CTRL0 0x008f + +#define RTL8367D_REG_INGRESSBW_PORT4_RATE_CTRL1 0x0090 +#define RTL8367D_INGRESSBW_PORT4_RATE_CTRL1_BYPASS_ABILITY_LOCK_OFFSET 3 +#define RTL8367D_INGRESSBW_PORT4_RATE_CTRL1_BYPASS_ABILITY_LOCK_MASK 0x8 +#define RTL8367D_INGRESSBW_PORT4_RATE_CTRL1_INGRESSBW_RATE16_OFFSET 0 +#define RTL8367D_INGRESSBW_PORT4_RATE_CTRL1_INGRESSBW_RATE16_MASK 0x7 + +#define RTL8367D_REG_PORT4_FORCE_RATE0 0x0091 + +#define RTL8367D_REG_PORT4_FORCE_RATE1 0x0092 + +#define RTL8367D_REG_PORT4_CURENT_RATE0 0x0093 + +#define RTL8367D_REG_PORT4_CURENT_RATE1 0x0094 + +#define RTL8367D_REG_PORT4_PAGE_COUNTER 0x0095 +#define RTL8367D_PORT4_PAGE_COUNTER_OFFSET 0 +#define RTL8367D_PORT4_PAGE_COUNTER_MASK 0x7F + +#define RTL8367D_REG_PAGEMETER_PORT4_CTRL0 0x0096 + +#define RTL8367D_REG_PAGEMETER_PORT4_CTRL1 0x0097 + +#define RTL8367D_REG_PORT4_EEECFG 0x0098 +#define RTL8367D_PORT4_EEECFG_EEE_PORT_TX_EN_OFFSET 9 +#define RTL8367D_PORT4_EEECFG_EEE_PORT_TX_EN_MASK 0x200 +#define RTL8367D_PORT4_EEECFG_EEE_PORT_RX_EN_OFFSET 8 +#define RTL8367D_PORT4_EEECFG_EEE_PORT_RX_EN_MASK 0x100 +#define RTL8367D_PORT4_EEECFG_EEE_LPI_OFFSET 5 +#define RTL8367D_PORT4_EEECFG_EEE_LPI_MASK 0x20 +#define RTL8367D_PORT4_EEECFG_EEE_TX_STS_OFFSET 4 +#define RTL8367D_PORT4_EEECFG_EEE_TX_STS_MASK 0x10 +#define RTL8367D_PORT4_EEECFG_EEE_RX_STS_OFFSET 3 +#define RTL8367D_PORT4_EEECFG_EEE_RX_STS_MASK 0x8 +#define RTL8367D_PORT4_EEECFG_EEE_PAUSE_INDICATOR_OFFSET 2 +#define RTL8367D_PORT4_EEECFG_EEE_PAUSE_INDICATOR_MASK 0x4 + +#define RTL8367D_REG_PORT4_EEETXMTR 0x0099 + +#define RTL8367D_REG_PORT4_EEERXMTR 0x009a + +#define RTL8367D_REG_PORT4_DUMMY 0x009e + +#define RTL8367D_REG_P4_MSIC1 0x009f +#define RTL8367D_P4_MSIC1_OFFSET 0 +#define RTL8367D_P4_MSIC1_MASK 0x1 + +#define RTL8367D_REG_PORT5_CGST_HALF_CFG 0x00a0 +#define RTL8367D_PORT5_CGST_HALF_CFG_CONGESTION_TIME_OFFSET 4 +#define RTL8367D_PORT5_CGST_HALF_CFG_CONGESTION_TIME_MASK 0xF0 +#define RTL8367D_PORT5_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_OFFSET 0 +#define RTL8367D_PORT5_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_MASK 0xF + +#define RTL8367D_REG_PKTGEN_PORT5_TIMER 0x00ad +#define RTL8367D_PKTGEN_PORT5_TIMER_TIMER_OFFSET 4 +#define RTL8367D_PKTGEN_PORT5_TIMER_TIMER_MASK 0xF0 +#define RTL8367D_PKTGEN_PORT5_TIMER_RX_DMA_ERR_FLAG_OFFSET 3 +#define RTL8367D_PKTGEN_PORT5_TIMER_RX_DMA_ERR_FLAG_MASK 0x8 + +#define RTL8367D_REG_PORT5_MISC_CFG 0x00ae +#define RTL8367D_PORT5_MISC_CFG_SMALL_TAG_IPG_OFFSET 15 +#define RTL8367D_PORT5_MISC_CFG_SMALL_TAG_IPG_MASK 0x8000 +#define RTL8367D_PORT5_MISC_CFG_TX_ITFSP_MODE_OFFSET 14 +#define RTL8367D_PORT5_MISC_CFG_TX_ITFSP_MODE_MASK 0x4000 +#define RTL8367D_PORT5_MISC_CFG_DOT1Q_REMARK_ENABLE_OFFSET 12 +#define RTL8367D_PORT5_MISC_CFG_DOT1Q_REMARK_ENABLE_MASK 0x1000 +#define RTL8367D_PORT5_MISC_CFG_INGRESSBW_FLOWCTRL_OFFSET 11 +#define RTL8367D_PORT5_MISC_CFG_INGRESSBW_FLOWCTRL_MASK 0x800 +#define RTL8367D_PORT5_MISC_CFG_INGRESSBW_IFG_OFFSET 10 +#define RTL8367D_PORT5_MISC_CFG_INGRESSBW_IFG_MASK 0x400 +#define RTL8367D_PORT5_MISC_CFG_RX_SPC_OFFSET 9 +#define RTL8367D_PORT5_MISC_CFG_RX_SPC_MASK 0x200 +#define RTL8367D_PORT5_MISC_CFG_CRC_SKIP_OFFSET 8 +#define RTL8367D_PORT5_MISC_CFG_CRC_SKIP_MASK 0x100 +#define RTL8367D_PORT5_MISC_CFG_MAC_LOOPBACK_OFFSET 6 +#define RTL8367D_PORT5_MISC_CFG_MAC_LOOPBACK_MASK 0x40 +#define RTL8367D_PORT5_MISC_CFG_VLAN_EGRESS_MODE_OFFSET 4 +#define RTL8367D_PORT5_MISC_CFG_VLAN_EGRESS_MODE_MASK 0x30 +#define RTL8367D_PORT5_MISC_CFG_CONGESTION_SUSTAIN_TIME_OFFSET 0 +#define RTL8367D_PORT5_MISC_CFG_CONGESTION_SUSTAIN_TIME_MASK 0xF + +#define RTL8367D_REG_INGRESSBW_PORT5_RATE_CTRL0 0x00af + +#define RTL8367D_REG_INGRESSBW_PORT5_RATE_CTRL1 0x00b0 +#define RTL8367D_INGRESSBW_PORT5_RATE_CTRL1_BYPASS_ABILITY_LOCK_OFFSET 3 +#define RTL8367D_INGRESSBW_PORT5_RATE_CTRL1_BYPASS_ABILITY_LOCK_MASK 0x8 +#define RTL8367D_INGRESSBW_PORT5_RATE_CTRL1_INGRESSBW_RATE16_OFFSET 0 +#define RTL8367D_INGRESSBW_PORT5_RATE_CTRL1_INGRESSBW_RATE16_MASK 0x7 + +#define RTL8367D_REG_PORT5_FORCE_RATE0 0x00b1 + +#define RTL8367D_REG_PORT5_FORCE_RATE1 0x00b2 + +#define RTL8367D_REG_PORT5_CURENT_RATE0 0x00b3 + +#define RTL8367D_REG_PORT5_CURENT_RATE1 0x00b4 + +#define RTL8367D_REG_PORT5_PAGE_COUNTER 0x00b5 +#define RTL8367D_PORT5_PAGE_COUNTER_OFFSET 0 +#define RTL8367D_PORT5_PAGE_COUNTER_MASK 0x7F + +#define RTL8367D_REG_PAGEMETER_PORT5_CTRL0 0x00b6 + +#define RTL8367D_REG_PAGEMETER_PORT5_CTRL1 0x00b7 + +#define RTL8367D_REG_PORT5_EEECFG 0x00b8 +#define RTL8367D_PORT5_EEECFG_EEE_PORT_TX_EN_OFFSET 9 +#define RTL8367D_PORT5_EEECFG_EEE_PORT_TX_EN_MASK 0x200 +#define RTL8367D_PORT5_EEECFG_EEE_PORT_RX_EN_OFFSET 8 +#define RTL8367D_PORT5_EEECFG_EEE_PORT_RX_EN_MASK 0x100 +#define RTL8367D_PORT5_EEECFG_EEE_LPI_OFFSET 5 +#define RTL8367D_PORT5_EEECFG_EEE_LPI_MASK 0x20 +#define RTL8367D_PORT5_EEECFG_EEE_TX_STS_OFFSET 4 +#define RTL8367D_PORT5_EEECFG_EEE_TX_STS_MASK 0x10 +#define RTL8367D_PORT5_EEECFG_EEE_RX_STS_OFFSET 3 +#define RTL8367D_PORT5_EEECFG_EEE_RX_STS_MASK 0x8 +#define RTL8367D_PORT5_EEECFG_EEE_PAUSE_INDICATOR_OFFSET 2 +#define RTL8367D_PORT5_EEECFG_EEE_PAUSE_INDICATOR_MASK 0x4 + +#define RTL8367D_REG_PORT5_EEETXMTR 0x00b9 + +#define RTL8367D_REG_PORT5_EEERXMTR 0x00ba + +#define RTL8367D_REG_PORT5_DUMMY 0x00be + +#define RTL8367D_REG_P5_MSIC1 0x00bf +#define RTL8367D_P5_MSIC1_OFFSET 0 +#define RTL8367D_P5_MSIC1_MASK 0x1 + +#define RTL8367D_REG_PORT6_CGST_HALF_CFG 0x00c0 +#define RTL8367D_PORT6_CGST_HALF_CFG_CONGESTION_TIME_OFFSET 4 +#define RTL8367D_PORT6_CGST_HALF_CFG_CONGESTION_TIME_MASK 0xF0 +#define RTL8367D_PORT6_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_OFFSET 0 +#define RTL8367D_PORT6_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_MASK 0xF + +#define RTL8367D_REG_PKTGEN_PORT6_TIMER 0x00cd +#define RTL8367D_PKTGEN_PORT6_TIMER_TIMER_OFFSET 4 +#define RTL8367D_PKTGEN_PORT6_TIMER_TIMER_MASK 0xF0 +#define RTL8367D_PKTGEN_PORT6_TIMER_RX_DMA_ERR_FLAG_OFFSET 3 +#define RTL8367D_PKTGEN_PORT6_TIMER_RX_DMA_ERR_FLAG_MASK 0x8 + +#define RTL8367D_REG_PORT6_MISC_CFG 0x00ce +#define RTL8367D_PORT6_MISC_CFG_SMALL_TAG_IPG_OFFSET 15 +#define RTL8367D_PORT6_MISC_CFG_SMALL_TAG_IPG_MASK 0x8000 +#define RTL8367D_PORT6_MISC_CFG_TX_ITFSP_MODE_OFFSET 14 +#define RTL8367D_PORT6_MISC_CFG_TX_ITFSP_MODE_MASK 0x4000 +#define RTL8367D_PORT6_MISC_CFG_DOT1Q_REMARK_ENABLE_OFFSET 12 +#define RTL8367D_PORT6_MISC_CFG_DOT1Q_REMARK_ENABLE_MASK 0x1000 +#define RTL8367D_PORT6_MISC_CFG_INGRESSBW_FLOWCTRL_OFFSET 11 +#define RTL8367D_PORT6_MISC_CFG_INGRESSBW_FLOWCTRL_MASK 0x800 +#define RTL8367D_PORT6_MISC_CFG_INGRESSBW_IFG_OFFSET 10 +#define RTL8367D_PORT6_MISC_CFG_INGRESSBW_IFG_MASK 0x400 +#define RTL8367D_PORT6_MISC_CFG_RX_SPC_OFFSET 9 +#define RTL8367D_PORT6_MISC_CFG_RX_SPC_MASK 0x200 +#define RTL8367D_PORT6_MISC_CFG_CRC_SKIP_OFFSET 8 +#define RTL8367D_PORT6_MISC_CFG_CRC_SKIP_MASK 0x100 +#define RTL8367D_PORT6_MISC_CFG_MAC_LOOPBACK_OFFSET 6 +#define RTL8367D_PORT6_MISC_CFG_MAC_LOOPBACK_MASK 0x40 +#define RTL8367D_PORT6_MISC_CFG_VLAN_EGRESS_MODE_OFFSET 4 +#define RTL8367D_PORT6_MISC_CFG_VLAN_EGRESS_MODE_MASK 0x30 +#define RTL8367D_PORT6_MISC_CFG_CONGESTION_SUSTAIN_TIME_OFFSET 0 +#define RTL8367D_PORT6_MISC_CFG_CONGESTION_SUSTAIN_TIME_MASK 0xF + +#define RTL8367D_REG_INGRESSBW_PORT6_RATE_CTRL0 0x00cf + +#define RTL8367D_REG_INGRESSBW_PORT6_RATE_CTRL1 0x00d0 +#define RTL8367D_INGRESSBW_PORT6_RATE_CTRL1_BYPASS_ABILITY_LOCK_OFFSET 3 +#define RTL8367D_INGRESSBW_PORT6_RATE_CTRL1_BYPASS_ABILITY_LOCK_MASK 0x8 +#define RTL8367D_INGRESSBW_PORT6_RATE_CTRL1_INGRESSBW_RATE16_OFFSET 0 +#define RTL8367D_INGRESSBW_PORT6_RATE_CTRL1_INGRESSBW_RATE16_MASK 0x7 + +#define RTL8367D_REG_PORT6_FORCE_RATE0 0x00d1 + +#define RTL8367D_REG_PORT6_FORCE_RATE1 0x00d2 + +#define RTL8367D_REG_PORT6_CURENT_RATE0 0x00d3 + +#define RTL8367D_REG_PORT6_CURENT_RATE1 0x00d4 + +#define RTL8367D_REG_PORT6_PAGE_COUNTER 0x00d5 +#define RTL8367D_PORT6_PAGE_COUNTER_OFFSET 0 +#define RTL8367D_PORT6_PAGE_COUNTER_MASK 0x7F + +#define RTL8367D_REG_PAGEMETER_PORT6_CTRL0 0x00d6 + +#define RTL8367D_REG_PAGEMETER_PORT6_CTRL1 0x00d7 + +#define RTL8367D_REG_PORT6_EEECFG 0x00d8 +#define RTL8367D_PORT6_EEECFG_EEE_PORT_TX_EN_OFFSET 9 +#define RTL8367D_PORT6_EEECFG_EEE_PORT_TX_EN_MASK 0x200 +#define RTL8367D_PORT6_EEECFG_EEE_PORT_RX_EN_OFFSET 8 +#define RTL8367D_PORT6_EEECFG_EEE_PORT_RX_EN_MASK 0x100 +#define RTL8367D_PORT6_EEECFG_EEE_LPI_OFFSET 5 +#define RTL8367D_PORT6_EEECFG_EEE_LPI_MASK 0x20 +#define RTL8367D_PORT6_EEECFG_EEE_TX_STS_OFFSET 4 +#define RTL8367D_PORT6_EEECFG_EEE_TX_STS_MASK 0x10 +#define RTL8367D_PORT6_EEECFG_EEE_RX_STS_OFFSET 3 +#define RTL8367D_PORT6_EEECFG_EEE_RX_STS_MASK 0x8 +#define RTL8367D_PORT6_EEECFG_EEE_PAUSE_INDICATOR_OFFSET 2 +#define RTL8367D_PORT6_EEECFG_EEE_PAUSE_INDICATOR_MASK 0x4 + +#define RTL8367D_REG_PORT6_EEETXMTR 0x00d9 + +#define RTL8367D_REG_PORT6_EEERXMTR 0x00da + +#define RTL8367D_REG_PORT6_DUMMY 0x00de + +#define RTL8367D_REG_P6_MSIC1 0x00df +#define RTL8367D_P6_MSIC1_OFFSET 0 +#define RTL8367D_P6_MSIC1_MASK 0x1 + +#define RTL8367D_REG_PORT7_CGST_HALF_CFG 0x00e0 +#define RTL8367D_PORT7_CGST_HALF_CFG_CONGESTION_TIME_OFFSET 4 +#define RTL8367D_PORT7_CGST_HALF_CFG_CONGESTION_TIME_MASK 0xF0 +#define RTL8367D_PORT7_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_OFFSET 0 +#define RTL8367D_PORT7_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_MASK 0xF + +#define RTL8367D_REG_PKTGEN_PORT7_TIMER 0x00ed +#define RTL8367D_PKTGEN_PORT7_TIMER_TIMER_OFFSET 4 +#define RTL8367D_PKTGEN_PORT7_TIMER_TIMER_MASK 0xF0 +#define RTL8367D_PKTGEN_PORT7_TIMER_RX_DMA_ERR_FLAG_OFFSET 3 +#define RTL8367D_PKTGEN_PORT7_TIMER_RX_DMA_ERR_FLAG_MASK 0x8 + +#define RTL8367D_REG_PORT7_MISC_CFG 0x00ee +#define RTL8367D_PORT7_MISC_CFG_SMALL_TAG_IPG_OFFSET 15 +#define RTL8367D_PORT7_MISC_CFG_SMALL_TAG_IPG_MASK 0x8000 +#define RTL8367D_PORT7_MISC_CFG_TX_ITFSP_MODE_OFFSET 14 +#define RTL8367D_PORT7_MISC_CFG_TX_ITFSP_MODE_MASK 0x4000 +#define RTL8367D_PORT7_MISC_CFG_DOT1Q_REMARK_ENABLE_OFFSET 12 +#define RTL8367D_PORT7_MISC_CFG_DOT1Q_REMARK_ENABLE_MASK 0x1000 +#define RTL8367D_PORT7_MISC_CFG_INGRESSBW_FLOWCTRL_OFFSET 11 +#define RTL8367D_PORT7_MISC_CFG_INGRESSBW_FLOWCTRL_MASK 0x800 +#define RTL8367D_PORT7_MISC_CFG_INGRESSBW_IFG_OFFSET 10 +#define RTL8367D_PORT7_MISC_CFG_INGRESSBW_IFG_MASK 0x400 +#define RTL8367D_PORT7_MISC_CFG_RX_SPC_OFFSET 9 +#define RTL8367D_PORT7_MISC_CFG_RX_SPC_MASK 0x200 +#define RTL8367D_PORT7_MISC_CFG_CRC_SKIP_OFFSET 8 +#define RTL8367D_PORT7_MISC_CFG_CRC_SKIP_MASK 0x100 +#define RTL8367D_PORT7_MISC_CFG_MAC_LOOPBACK_OFFSET 6 +#define RTL8367D_PORT7_MISC_CFG_MAC_LOOPBACK_MASK 0x40 +#define RTL8367D_PORT7_MISC_CFG_VLAN_EGRESS_MODE_OFFSET 4 +#define RTL8367D_PORT7_MISC_CFG_VLAN_EGRESS_MODE_MASK 0x30 +#define RTL8367D_PORT7_MISC_CFG_CONGESTION_SUSTAIN_TIME_OFFSET 0 +#define RTL8367D_PORT7_MISC_CFG_CONGESTION_SUSTAIN_TIME_MASK 0xF + +#define RTL8367D_REG_INGRESSBW_PORT7_RATE_CTRL0 0x00ef + +#define RTL8367D_REG_INGRESSBW_PORT7_RATE_CTRL1 0x00f0 +#define RTL8367D_INGRESSBW_PORT7_RATE_CTRL1_BYPASS_ABILITY_LOCK_OFFSET 3 +#define RTL8367D_INGRESSBW_PORT7_RATE_CTRL1_BYPASS_ABILITY_LOCK_MASK 0x8 +#define RTL8367D_INGRESSBW_PORT7_RATE_CTRL1_INGRESSBW_RATE16_OFFSET 0 +#define RTL8367D_INGRESSBW_PORT7_RATE_CTRL1_INGRESSBW_RATE16_MASK 0x7 + +#define RTL8367D_REG_PORT7_FORCE_RATE0 0x00f1 + +#define RTL8367D_REG_PORT7_FORCE_RATE1 0x00f2 + +#define RTL8367D_REG_PORT7_CURENT_RATE0 0x00f3 + +#define RTL8367D_REG_PORT7_CURENT_RATE1 0x00f4 + +#define RTL8367D_REG_PORT7_PAGE_COUNTER 0x00f5 +#define RTL8367D_PORT7_PAGE_COUNTER_OFFSET 0 +#define RTL8367D_PORT7_PAGE_COUNTER_MASK 0x7F + +#define RTL8367D_REG_PAGEMETER_PORT7_CTRL0 0x00f6 + +#define RTL8367D_REG_PAGEMETER_PORT7_CTRL1 0x00f7 + +#define RTL8367D_REG_PORT7_EEECFG 0x00f8 +#define RTL8367D_PORT7_EEECFG_EEE_PORT_TX_EN_OFFSET 9 +#define RTL8367D_PORT7_EEECFG_EEE_PORT_TX_EN_MASK 0x200 +#define RTL8367D_PORT7_EEECFG_EEE_PORT_RX_EN_OFFSET 8 +#define RTL8367D_PORT7_EEECFG_EEE_PORT_RX_EN_MASK 0x100 +#define RTL8367D_PORT7_EEECFG_EEE_LPI_OFFSET 5 +#define RTL8367D_PORT7_EEECFG_EEE_LPI_MASK 0x20 +#define RTL8367D_PORT7_EEECFG_EEE_TX_STS_OFFSET 4 +#define RTL8367D_PORT7_EEECFG_EEE_TX_STS_MASK 0x10 +#define RTL8367D_PORT7_EEECFG_EEE_RX_STS_OFFSET 3 +#define RTL8367D_PORT7_EEECFG_EEE_RX_STS_MASK 0x8 +#define RTL8367D_PORT7_EEECFG_EEE_PAUSE_INDICATOR_OFFSET 2 +#define RTL8367D_PORT7_EEECFG_EEE_PAUSE_INDICATOR_MASK 0x4 + +#define RTL8367D_REG_PORT7_EEETXMTR 0x00f9 + +#define RTL8367D_REG_PORT7_EEERXMTR 0x00fa + +#define RTL8367D_REG_PORT7_DUMMY 0x00fe + +#define RTL8367D_REG_P7_MSIC1 0x00ff +#define RTL8367D_P7_MSIC1_OFFSET 0 +#define RTL8367D_P7_MSIC1_MASK 0x1 + +/* (16'h0200)outq_reg */ + +#define RTL8367D_REG_FLOWCTRL_QUEUE0_DROP_ON 0x0200 +#define RTL8367D_FLOWCTRL_QUEUE0_DROP_ON_OFFSET 0 +#define RTL8367D_FLOWCTRL_QUEUE0_DROP_ON_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_QUEUE1_DROP_ON 0x0201 +#define RTL8367D_FLOWCTRL_QUEUE1_DROP_ON_OFFSET 0 +#define RTL8367D_FLOWCTRL_QUEUE1_DROP_ON_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_QUEUE2_DROP_ON 0x0202 +#define RTL8367D_FLOWCTRL_QUEUE2_DROP_ON_OFFSET 0 +#define RTL8367D_FLOWCTRL_QUEUE2_DROP_ON_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_QUEUE3_DROP_ON 0x0203 +#define RTL8367D_FLOWCTRL_QUEUE3_DROP_ON_OFFSET 0 +#define RTL8367D_FLOWCTRL_QUEUE3_DROP_ON_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_QUEUE4_DROP_ON 0x0204 +#define RTL8367D_FLOWCTRL_QUEUE4_DROP_ON_OFFSET 0 +#define RTL8367D_FLOWCTRL_QUEUE4_DROP_ON_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_QUEUE5_DROP_ON 0x0205 +#define RTL8367D_FLOWCTRL_QUEUE5_DROP_ON_OFFSET 0 +#define RTL8367D_FLOWCTRL_QUEUE5_DROP_ON_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_QUEUE6_DROP_ON 0x0206 +#define RTL8367D_FLOWCTRL_QUEUE6_DROP_ON_OFFSET 0 +#define RTL8367D_FLOWCTRL_QUEUE6_DROP_ON_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_QUEUE7_DROP_ON 0x0207 +#define RTL8367D_FLOWCTRL_QUEUE7_DROP_ON_OFFSET 0 +#define RTL8367D_FLOWCTRL_QUEUE7_DROP_ON_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_PORT0_DROP_ON 0x0208 +#define RTL8367D_FLOWCTRL_PORT0_DROP_ON_OFFSET 0 +#define RTL8367D_FLOWCTRL_PORT0_DROP_ON_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_PORT1_DROP_ON 0x0209 +#define RTL8367D_FLOWCTRL_PORT1_DROP_ON_OFFSET 0 +#define RTL8367D_FLOWCTRL_PORT1_DROP_ON_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_PORT2_DROP_ON 0x020a +#define RTL8367D_FLOWCTRL_PORT2_DROP_ON_OFFSET 0 +#define RTL8367D_FLOWCTRL_PORT2_DROP_ON_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_PORT3_DROP_ON 0x020b +#define RTL8367D_FLOWCTRL_PORT3_DROP_ON_OFFSET 0 +#define RTL8367D_FLOWCTRL_PORT3_DROP_ON_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_PORT4_DROP_ON 0x020c +#define RTL8367D_FLOWCTRL_PORT4_DROP_ON_OFFSET 0 +#define RTL8367D_FLOWCTRL_PORT4_DROP_ON_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_PORT5_DROP_ON 0x020d +#define RTL8367D_FLOWCTRL_PORT5_DROP_ON_OFFSET 0 +#define RTL8367D_FLOWCTRL_PORT5_DROP_ON_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_PORT6_DROP_ON 0x020e +#define RTL8367D_FLOWCTRL_PORT6_DROP_ON_OFFSET 0 +#define RTL8367D_FLOWCTRL_PORT6_DROP_ON_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_PORT7_DROP_ON 0x020f +#define RTL8367D_FLOWCTRL_PORT7_DROP_ON_OFFSET 0 +#define RTL8367D_FLOWCTRL_PORT7_DROP_ON_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_PORT_GAP 0x0218 +#define RTL8367D_FLOWCTRL_PORT_GAP_OFFSET 0 +#define RTL8367D_FLOWCTRL_PORT_GAP_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_QUEUE_GAP 0x0219 +#define RTL8367D_FLOWCTRL_QUEUE_GAP_OFFSET 0 +#define RTL8367D_FLOWCTRL_QUEUE_GAP_MASK 0x7FF + +#define RTL8367D_REG_PORT_QEMPTY 0x022d +#define RTL8367D_PORT_QEMPTY_OFFSET 0 +#define RTL8367D_PORT_QEMPTY_MASK 0xFF + +#define RTL8367D_REG_FLOWCTRL_DEBUG_CTRL0 0x022e +#define RTL8367D_FLOWCTRL_DEBUG_CTRL0_OFFSET 0 +#define RTL8367D_FLOWCTRL_DEBUG_CTRL0_MASK 0x7 + +#define RTL8367D_REG_FLOWCTRL_DEBUG_CTRL1 0x022f +#define RTL8367D_TOTAL_OFFSET 9 +#define RTL8367D_TOTAL_MASK 0x200 +#define RTL8367D_PORT_MAX_OFFSET 8 +#define RTL8367D_PORT_MAX_MASK 0x100 +#define RTL8367D_QMAX_MASK_OFFSET 0 +#define RTL8367D_QMAX_MASK_MASK 0xFF + +#define RTL8367D_REG_FLOWCTRL_QUEUE0_PAGE_COUNT 0x0230 +#define RTL8367D_FLOWCTRL_QUEUE0_PAGE_COUNT_OFFSET 0 +#define RTL8367D_FLOWCTRL_QUEUE0_PAGE_COUNT_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_QUEUE1_PAGE_COUNT 0x0231 +#define RTL8367D_FLOWCTRL_QUEUE1_PAGE_COUNT_OFFSET 0 +#define RTL8367D_FLOWCTRL_QUEUE1_PAGE_COUNT_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_QUEUE2_PAGE_COUNT 0x0232 +#define RTL8367D_FLOWCTRL_QUEUE2_PAGE_COUNT_OFFSET 0 +#define RTL8367D_FLOWCTRL_QUEUE2_PAGE_COUNT_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_QUEUE3_PAGE_COUNT 0x0233 +#define RTL8367D_FLOWCTRL_QUEUE3_PAGE_COUNT_OFFSET 0 +#define RTL8367D_FLOWCTRL_QUEUE3_PAGE_COUNT_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_QUEUE4_PAGE_COUNT 0x0234 +#define RTL8367D_FLOWCTRL_QUEUE4_PAGE_COUNT_OFFSET 0 +#define RTL8367D_FLOWCTRL_QUEUE4_PAGE_COUNT_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_QUEUE5_PAGE_COUNT 0x0235 +#define RTL8367D_FLOWCTRL_QUEUE5_PAGE_COUNT_OFFSET 0 +#define RTL8367D_FLOWCTRL_QUEUE5_PAGE_COUNT_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_QUEUE6_PAGE_COUNT 0x0236 +#define RTL8367D_FLOWCTRL_QUEUE6_PAGE_COUNT_OFFSET 0 +#define RTL8367D_FLOWCTRL_QUEUE6_PAGE_COUNT_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_QUEUE7_PAGE_COUNT 0x0237 +#define RTL8367D_FLOWCTRL_QUEUE7_PAGE_COUNT_OFFSET 0 +#define RTL8367D_FLOWCTRL_QUEUE7_PAGE_COUNT_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_PORT_PAGE_COUNT 0x0238 +#define RTL8367D_FLOWCTRL_PORT_PAGE_COUNT_OFFSET 0 +#define RTL8367D_FLOWCTRL_PORT_PAGE_COUNT_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_QUEUE0_MAX_PAGE_COUNT 0x0239 +#define RTL8367D_FLOWCTRL_QUEUE0_MAX_PAGE_COUNT_OFFSET 0 +#define RTL8367D_FLOWCTRL_QUEUE0_MAX_PAGE_COUNT_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_QUEUE1_MAX_PAGE_COUNT 0x023a +#define RTL8367D_FLOWCTRL_QUEUE1_MAX_PAGE_COUNT_OFFSET 0 +#define RTL8367D_FLOWCTRL_QUEUE1_MAX_PAGE_COUNT_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_QUEUE2_MAX_PAGE_COUNT 0x023b +#define RTL8367D_FLOWCTRL_QUEUE2_MAX_PAGE_COUNT_OFFSET 0 +#define RTL8367D_FLOWCTRL_QUEUE2_MAX_PAGE_COUNT_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_QUEUE3_MAX_PAGE_COUNT 0x023c +#define RTL8367D_FLOWCTRL_QUEUE3_MAX_PAGE_COUNT_OFFSET 0 +#define RTL8367D_FLOWCTRL_QUEUE3_MAX_PAGE_COUNT_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_QUEUE4_MAX_PAGE_COUNT 0x023d +#define RTL8367D_FLOWCTRL_QUEUE4_MAX_PAGE_COUNT_OFFSET 0 +#define RTL8367D_FLOWCTRL_QUEUE4_MAX_PAGE_COUNT_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_QUEUE5_MAX_PAGE_COUNT 0x023e +#define RTL8367D_FLOWCTRL_QUEUE5_MAX_PAGE_COUNT_OFFSET 0 +#define RTL8367D_FLOWCTRL_QUEUE5_MAX_PAGE_COUNT_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_QUEUE6_MAX_PAGE_COUNT 0x023f +#define RTL8367D_FLOWCTRL_QUEUE6_MAX_PAGE_COUNT_OFFSET 0 +#define RTL8367D_FLOWCTRL_QUEUE6_MAX_PAGE_COUNT_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_QUEUE7_MAX_PAGE_COUNT 0x0240 +#define RTL8367D_FLOWCTRL_QUEUE7_MAX_PAGE_COUNT_OFFSET 0 +#define RTL8367D_FLOWCTRL_QUEUE7_MAX_PAGE_COUNT_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_PORT_MAX_PAGE_COUNT 0x0241 +#define RTL8367D_FLOWCTRL_PORT_MAX_PAGE_COUNT_OFFSET 0 +#define RTL8367D_FLOWCTRL_PORT_MAX_PAGE_COUNT_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_TOTAL_PACKET_COUNT 0x0243 + +#define RTL8367D_REG_HIGH_QUEUE_MASK0 0x0244 +#define RTL8367D_PORT1_HIGH_QUEUE_MASK_OFFSET 8 +#define RTL8367D_PORT1_HIGH_QUEUE_MASK_MASK 0xFF00 +#define RTL8367D_PORT0_HIGH_QUEUE_MASK_OFFSET 0 +#define RTL8367D_PORT0_HIGH_QUEUE_MASK_MASK 0xFF + +#define RTL8367D_REG_HIGH_QUEUE_MASK1 0x0245 +#define RTL8367D_PORT3_HIGH_QUEUE_MASK_OFFSET 8 +#define RTL8367D_PORT3_HIGH_QUEUE_MASK_MASK 0xFF00 +#define RTL8367D_PORT2_HIGH_QUEUE_MASK_OFFSET 0 +#define RTL8367D_PORT2_HIGH_QUEUE_MASK_MASK 0xFF + +#define RTL8367D_REG_HIGH_QUEUE_MASK2 0x0246 +#define RTL8367D_PORT5_HIGH_QUEUE_MASK_OFFSET 8 +#define RTL8367D_PORT5_HIGH_QUEUE_MASK_MASK 0xFF00 +#define RTL8367D_PORT4_HIGH_QUEUE_MASK_OFFSET 0 +#define RTL8367D_PORT4_HIGH_QUEUE_MASK_MASK 0xFF + +#define RTL8367D_REG_HIGH_QUEUE_MASK3 0x0247 +#define RTL8367D_PORT7_HIGH_QUEUE_MASK_OFFSET 8 +#define RTL8367D_PORT7_HIGH_QUEUE_MASK_MASK 0xFF00 +#define RTL8367D_PORT6_HIGH_QUEUE_MASK_OFFSET 0 +#define RTL8367D_PORT6_HIGH_QUEUE_MASK_MASK 0xFF + +#define RTL8367D_REG_LOW_QUEUE_TH 0x024c +#define RTL8367D_LOW_QUEUE_TH_OFFSET 0 +#define RTL8367D_LOW_QUEUE_TH_MASK 0x7FF + +#define RTL8367D_REG_TH_TX_PREFET 0x0250 +#define RTL8367D_TH_TX_PREFET_OFFSET 0 +#define RTL8367D_TH_TX_PREFET_MASK 0xFF + +/* (16'h0300)sch_reg */ + +#define RTL8367D_REG_SCHEDULE_WFQ_CTRL 0x0300 +#define RTL8367D_SCHEDULE_WFQ_CTRL_OFFSET 0 +#define RTL8367D_SCHEDULE_WFQ_CTRL_MASK 0x1 + +#define RTL8367D_REG_SCHEDULE_WFQ_BURST_SIZE 0x0301 + +#define RTL8367D_REG_SCHEDULE_QUEUE_TYPE_CTRL0 0x0302 +#define RTL8367D_PORT1_QUEUE7_TYPE_OFFSET 15 +#define RTL8367D_PORT1_QUEUE7_TYPE_MASK 0x8000 +#define RTL8367D_PORT1_QUEUE6_TYPE_OFFSET 14 +#define RTL8367D_PORT1_QUEUE6_TYPE_MASK 0x4000 +#define RTL8367D_PORT1_QUEUE5_TYPE_OFFSET 13 +#define RTL8367D_PORT1_QUEUE5_TYPE_MASK 0x2000 +#define RTL8367D_PORT1_QUEUE4_TYPE_OFFSET 12 +#define RTL8367D_PORT1_QUEUE4_TYPE_MASK 0x1000 +#define RTL8367D_PORT1_QUEUE3_TYPE_OFFSET 11 +#define RTL8367D_PORT1_QUEUE3_TYPE_MASK 0x800 +#define RTL8367D_PORT1_QUEUE2_TYPE_OFFSET 10 +#define RTL8367D_PORT1_QUEUE2_TYPE_MASK 0x400 +#define RTL8367D_PORT1_QUEUE1_TYPE_OFFSET 9 +#define RTL8367D_PORT1_QUEUE1_TYPE_MASK 0x200 +#define RTL8367D_PORT1_QUEUE0_TYPE_OFFSET 8 +#define RTL8367D_PORT1_QUEUE0_TYPE_MASK 0x100 +#define RTL8367D_PORT0_QUEUE7_TYPE_OFFSET 7 +#define RTL8367D_PORT0_QUEUE7_TYPE_MASK 0x80 +#define RTL8367D_PORT0_QUEUE6_TYPE_OFFSET 6 +#define RTL8367D_PORT0_QUEUE6_TYPE_MASK 0x40 +#define RTL8367D_PORT0_QUEUE5_TYPE_OFFSET 5 +#define RTL8367D_PORT0_QUEUE5_TYPE_MASK 0x20 +#define RTL8367D_PORT0_QUEUE4_TYPE_OFFSET 4 +#define RTL8367D_PORT0_QUEUE4_TYPE_MASK 0x10 +#define RTL8367D_PORT0_QUEUE3_TYPE_OFFSET 3 +#define RTL8367D_PORT0_QUEUE3_TYPE_MASK 0x8 +#define RTL8367D_PORT0_QUEUE2_TYPE_OFFSET 2 +#define RTL8367D_PORT0_QUEUE2_TYPE_MASK 0x4 +#define RTL8367D_PORT0_QUEUE1_TYPE_OFFSET 1 +#define RTL8367D_PORT0_QUEUE1_TYPE_MASK 0x2 +#define RTL8367D_PORT0_QUEUE0_TYPE_OFFSET 0 +#define RTL8367D_PORT0_QUEUE0_TYPE_MASK 0x1 + +#define RTL8367D_REG_SCHEDULE_QUEUE_TYPE_CTRL1 0x0303 +#define RTL8367D_PORT3_QUEUE7_TYPE_OFFSET 15 +#define RTL8367D_PORT3_QUEUE7_TYPE_MASK 0x8000 +#define RTL8367D_PORT3_QUEUE6_TYPE_OFFSET 14 +#define RTL8367D_PORT3_QUEUE6_TYPE_MASK 0x4000 +#define RTL8367D_PORT3_QUEUE5_TYPE_OFFSET 13 +#define RTL8367D_PORT3_QUEUE5_TYPE_MASK 0x2000 +#define RTL8367D_PORT3_QUEUE4_TYPE_OFFSET 12 +#define RTL8367D_PORT3_QUEUE4_TYPE_MASK 0x1000 +#define RTL8367D_PORT3_QUEUE3_TYPE_OFFSET 11 +#define RTL8367D_PORT3_QUEUE3_TYPE_MASK 0x800 +#define RTL8367D_PORT3_QUEUE2_TYPE_OFFSET 10 +#define RTL8367D_PORT3_QUEUE2_TYPE_MASK 0x400 +#define RTL8367D_PORT3_QUEUE1_TYPE_OFFSET 9 +#define RTL8367D_PORT3_QUEUE1_TYPE_MASK 0x200 +#define RTL8367D_PORT3_QUEUE0_TYPE_OFFSET 8 +#define RTL8367D_PORT3_QUEUE0_TYPE_MASK 0x100 +#define RTL8367D_PORT2_QUEUE7_TYPE_OFFSET 7 +#define RTL8367D_PORT2_QUEUE7_TYPE_MASK 0x80 +#define RTL8367D_PORT2_QUEUE6_TYPE_OFFSET 6 +#define RTL8367D_PORT2_QUEUE6_TYPE_MASK 0x40 +#define RTL8367D_PORT2_QUEUE5_TYPE_OFFSET 5 +#define RTL8367D_PORT2_QUEUE5_TYPE_MASK 0x20 +#define RTL8367D_PORT2_QUEUE4_TYPE_OFFSET 4 +#define RTL8367D_PORT2_QUEUE4_TYPE_MASK 0x10 +#define RTL8367D_PORT2_QUEUE3_TYPE_OFFSET 3 +#define RTL8367D_PORT2_QUEUE3_TYPE_MASK 0x8 +#define RTL8367D_PORT2_QUEUE2_TYPE_OFFSET 2 +#define RTL8367D_PORT2_QUEUE2_TYPE_MASK 0x4 +#define RTL8367D_PORT2_QUEUE1_TYPE_OFFSET 1 +#define RTL8367D_PORT2_QUEUE1_TYPE_MASK 0x2 +#define RTL8367D_PORT2_QUEUE0_TYPE_OFFSET 0 +#define RTL8367D_PORT2_QUEUE0_TYPE_MASK 0x1 + +#define RTL8367D_REG_SCHEDULE_QUEUE_TYPE_CTRL2 0x0304 +#define RTL8367D_PORT5_QUEUE7_TYPE_OFFSET 15 +#define RTL8367D_PORT5_QUEUE7_TYPE_MASK 0x8000 +#define RTL8367D_PORT5_QUEUE6_TYPE_OFFSET 14 +#define RTL8367D_PORT5_QUEUE6_TYPE_MASK 0x4000 +#define RTL8367D_PORT5_QUEUE5_TYPE_OFFSET 13 +#define RTL8367D_PORT5_QUEUE5_TYPE_MASK 0x2000 +#define RTL8367D_PORT5_QUEUE4_TYPE_OFFSET 12 +#define RTL8367D_PORT5_QUEUE4_TYPE_MASK 0x1000 +#define RTL8367D_PORT5_QUEUE3_TYPE_OFFSET 11 +#define RTL8367D_PORT5_QUEUE3_TYPE_MASK 0x800 +#define RTL8367D_PORT5_QUEUE2_TYPE_OFFSET 10 +#define RTL8367D_PORT5_QUEUE2_TYPE_MASK 0x400 +#define RTL8367D_PORT5_QUEUE1_TYPE_OFFSET 9 +#define RTL8367D_PORT5_QUEUE1_TYPE_MASK 0x200 +#define RTL8367D_PORT5_QUEUE0_TYPE_OFFSET 8 +#define RTL8367D_PORT5_QUEUE0_TYPE_MASK 0x100 +#define RTL8367D_PORT4_QUEUE7_TYPE_OFFSET 7 +#define RTL8367D_PORT4_QUEUE7_TYPE_MASK 0x80 +#define RTL8367D_PORT4_QUEUE6_TYPE_OFFSET 6 +#define RTL8367D_PORT4_QUEUE6_TYPE_MASK 0x40 +#define RTL8367D_PORT4_QUEUE5_TYPE_OFFSET 5 +#define RTL8367D_PORT4_QUEUE5_TYPE_MASK 0x20 +#define RTL8367D_PORT4_QUEUE4_TYPE_OFFSET 4 +#define RTL8367D_PORT4_QUEUE4_TYPE_MASK 0x10 +#define RTL8367D_PORT4_QUEUE3_TYPE_OFFSET 3 +#define RTL8367D_PORT4_QUEUE3_TYPE_MASK 0x8 +#define RTL8367D_PORT4_QUEUE2_TYPE_OFFSET 2 +#define RTL8367D_PORT4_QUEUE2_TYPE_MASK 0x4 +#define RTL8367D_PORT4_QUEUE1_TYPE_OFFSET 1 +#define RTL8367D_PORT4_QUEUE1_TYPE_MASK 0x2 +#define RTL8367D_PORT4_QUEUE0_TYPE_OFFSET 0 +#define RTL8367D_PORT4_QUEUE0_TYPE_MASK 0x1 + +#define RTL8367D_REG_SCHEDULE_QUEUE_TYPE_CTRL3 0x0305 +#define RTL8367D_PORT7_QUEUE7_TYPE_OFFSET 15 +#define RTL8367D_PORT7_QUEUE7_TYPE_MASK 0x8000 +#define RTL8367D_PORT7_QUEUE6_TYPE_OFFSET 14 +#define RTL8367D_PORT7_QUEUE6_TYPE_MASK 0x4000 +#define RTL8367D_PORT7_QUEUE5_TYPE_OFFSET 13 +#define RTL8367D_PORT7_QUEUE5_TYPE_MASK 0x2000 +#define RTL8367D_PORT7_QUEUE4_TYPE_OFFSET 12 +#define RTL8367D_PORT7_QUEUE4_TYPE_MASK 0x1000 +#define RTL8367D_PORT7_QUEUE3_TYPE_OFFSET 11 +#define RTL8367D_PORT7_QUEUE3_TYPE_MASK 0x800 +#define RTL8367D_PORT7_QUEUE2_TYPE_OFFSET 10 +#define RTL8367D_PORT7_QUEUE2_TYPE_MASK 0x400 +#define RTL8367D_PORT7_QUEUE1_TYPE_OFFSET 9 +#define RTL8367D_PORT7_QUEUE1_TYPE_MASK 0x200 +#define RTL8367D_PORT7_QUEUE0_TYPE_OFFSET 8 +#define RTL8367D_PORT7_QUEUE0_TYPE_MASK 0x100 +#define RTL8367D_PORT6_QUEUE7_TYPE_OFFSET 7 +#define RTL8367D_PORT6_QUEUE7_TYPE_MASK 0x80 +#define RTL8367D_PORT6_QUEUE6_TYPE_OFFSET 6 +#define RTL8367D_PORT6_QUEUE6_TYPE_MASK 0x40 +#define RTL8367D_PORT6_QUEUE5_TYPE_OFFSET 5 +#define RTL8367D_PORT6_QUEUE5_TYPE_MASK 0x20 +#define RTL8367D_PORT6_QUEUE4_TYPE_OFFSET 4 +#define RTL8367D_PORT6_QUEUE4_TYPE_MASK 0x10 +#define RTL8367D_PORT6_QUEUE3_TYPE_OFFSET 3 +#define RTL8367D_PORT6_QUEUE3_TYPE_MASK 0x8 +#define RTL8367D_PORT6_QUEUE2_TYPE_OFFSET 2 +#define RTL8367D_PORT6_QUEUE2_TYPE_MASK 0x4 +#define RTL8367D_PORT6_QUEUE1_TYPE_OFFSET 1 +#define RTL8367D_PORT6_QUEUE1_TYPE_MASK 0x2 +#define RTL8367D_PORT6_QUEUE0_TYPE_OFFSET 0 +#define RTL8367D_PORT6_QUEUE0_TYPE_MASK 0x1 + +#define RTL8367D_REG_SCHEDULE_APR_CTRL0 0x030a +#define RTL8367D_PORT7_APR_ENABLE_OFFSET 7 +#define RTL8367D_PORT7_APR_ENABLE_MASK 0x80 +#define RTL8367D_PORT6_APR_ENABLE_OFFSET 6 +#define RTL8367D_PORT6_APR_ENABLE_MASK 0x40 +#define RTL8367D_PORT5_APR_ENABLE_OFFSET 5 +#define RTL8367D_PORT5_APR_ENABLE_MASK 0x20 +#define RTL8367D_PORT4_APR_ENABLE_OFFSET 4 +#define RTL8367D_PORT4_APR_ENABLE_MASK 0x10 +#define RTL8367D_PORT3_APR_ENABLE_OFFSET 3 +#define RTL8367D_PORT3_APR_ENABLE_MASK 0x8 +#define RTL8367D_PORT2_APR_ENABLE_OFFSET 2 +#define RTL8367D_PORT2_APR_ENABLE_MASK 0x4 +#define RTL8367D_PORT1_APR_ENABLE_OFFSET 1 +#define RTL8367D_PORT1_APR_ENABLE_MASK 0x2 +#define RTL8367D_PORT0_APR_ENABLE_OFFSET 0 +#define RTL8367D_PORT0_APR_ENABLE_MASK 0x1 + +#define RTL8367D_REG_SCHEDULE_PORT0_QUEUE0_WFQ_WEIGHT 0x030c + +#define RTL8367D_REG_SCHEDULE_PORT0_QUEUE1_WFQ_WEIGHT 0x030d +#define RTL8367D_SCHEDULE_PORT0_QUEUE1_WFQ_WEIGHT_OFFSET 0 +#define RTL8367D_SCHEDULE_PORT0_QUEUE1_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367D_REG_SCHEDULE_PORT0_QUEUE2_WFQ_WEIGHT 0x030e +#define RTL8367D_SCHEDULE_PORT0_QUEUE2_WFQ_WEIGHT_OFFSET 0 +#define RTL8367D_SCHEDULE_PORT0_QUEUE2_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367D_REG_SCHEDULE_PORT0_QUEUE3_WFQ_WEIGHT 0x030f +#define RTL8367D_SCHEDULE_PORT0_QUEUE3_WFQ_WEIGHT_OFFSET 0 +#define RTL8367D_SCHEDULE_PORT0_QUEUE3_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367D_REG_SCHEDULE_PORT0_QUEUE4_WFQ_WEIGHT 0x0310 +#define RTL8367D_SCHEDULE_PORT0_QUEUE4_WFQ_WEIGHT_OFFSET 0 +#define RTL8367D_SCHEDULE_PORT0_QUEUE4_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367D_REG_SCHEDULE_PORT0_QUEUE5_WFQ_WEIGHT 0x0311 +#define RTL8367D_SCHEDULE_PORT0_QUEUE5_WFQ_WEIGHT_OFFSET 0 +#define RTL8367D_SCHEDULE_PORT0_QUEUE5_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367D_REG_SCHEDULE_PORT0_QUEUE6_WFQ_WEIGHT 0x0312 +#define RTL8367D_SCHEDULE_PORT0_QUEUE6_WFQ_WEIGHT_OFFSET 0 +#define RTL8367D_SCHEDULE_PORT0_QUEUE6_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367D_REG_SCHEDULE_PORT0_QUEUE7_WFQ_WEIGHT 0x0313 +#define RTL8367D_SCHEDULE_PORT0_QUEUE7_WFQ_WEIGHT_OFFSET 0 +#define RTL8367D_SCHEDULE_PORT0_QUEUE7_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367D_REG_SCHEDULE_PORT1_QUEUE0_WFQ_WEIGHT 0x0314 + +#define RTL8367D_REG_SCHEDULE_PORT1_QUEUE1_WFQ_WEIGHT 0x0315 +#define RTL8367D_SCHEDULE_PORT1_QUEUE1_WFQ_WEIGHT_OFFSET 0 +#define RTL8367D_SCHEDULE_PORT1_QUEUE1_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367D_REG_SCHEDULE_PORT1_QUEUE2_WFQ_WEIGHT 0x0316 +#define RTL8367D_SCHEDULE_PORT1_QUEUE2_WFQ_WEIGHT_OFFSET 0 +#define RTL8367D_SCHEDULE_PORT1_QUEUE2_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367D_REG_SCHEDULE_PORT1_QUEUE3_WFQ_WEIGHT 0x0317 +#define RTL8367D_SCHEDULE_PORT1_QUEUE3_WFQ_WEIGHT_OFFSET 0 +#define RTL8367D_SCHEDULE_PORT1_QUEUE3_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367D_REG_SCHEDULE_PORT1_QUEUE4_WFQ_WEIGHT 0x0318 +#define RTL8367D_SCHEDULE_PORT1_QUEUE4_WFQ_WEIGHT_OFFSET 0 +#define RTL8367D_SCHEDULE_PORT1_QUEUE4_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367D_REG_SCHEDULE_PORT1_QUEUE5_WFQ_WEIGHT 0x0319 +#define RTL8367D_SCHEDULE_PORT1_QUEUE5_WFQ_WEIGHT_OFFSET 0 +#define RTL8367D_SCHEDULE_PORT1_QUEUE5_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367D_REG_SCHEDULE_PORT1_QUEUE6_WFQ_WEIGHT 0x031a +#define RTL8367D_SCHEDULE_PORT1_QUEUE6_WFQ_WEIGHT_OFFSET 0 +#define RTL8367D_SCHEDULE_PORT1_QUEUE6_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367D_REG_SCHEDULE_PORT1_QUEUE7_WFQ_WEIGHT 0x031b +#define RTL8367D_SCHEDULE_PORT1_QUEUE7_WFQ_WEIGHT_OFFSET 0 +#define RTL8367D_SCHEDULE_PORT1_QUEUE7_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367D_REG_SCHEDULE_PORT2_QUEUE0_WFQ_WEIGHT 0x031c + +#define RTL8367D_REG_SCHEDULE_PORT2_QUEUE1_WFQ_WEIGHT 0x031d +#define RTL8367D_SCHEDULE_PORT2_QUEUE1_WFQ_WEIGHT_OFFSET 0 +#define RTL8367D_SCHEDULE_PORT2_QUEUE1_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367D_REG_SCHEDULE_PORT2_QUEUE2_WFQ_WEIGHT 0x031e +#define RTL8367D_SCHEDULE_PORT2_QUEUE2_WFQ_WEIGHT_OFFSET 0 +#define RTL8367D_SCHEDULE_PORT2_QUEUE2_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367D_REG_SCHEDULE_PORT2_QUEUE3_WFQ_WEIGHT 0x031f +#define RTL8367D_SCHEDULE_PORT2_QUEUE3_WFQ_WEIGHT_OFFSET 0 +#define RTL8367D_SCHEDULE_PORT2_QUEUE3_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367D_REG_SCHEDULE_PORT2_QUEUE4_WFQ_WEIGHT 0x0320 +#define RTL8367D_SCHEDULE_PORT2_QUEUE4_WFQ_WEIGHT_OFFSET 0 +#define RTL8367D_SCHEDULE_PORT2_QUEUE4_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367D_REG_SCHEDULE_PORT2_QUEUE5_WFQ_WEIGHT 0x0321 +#define RTL8367D_SCHEDULE_PORT2_QUEUE5_WFQ_WEIGHT_OFFSET 0 +#define RTL8367D_SCHEDULE_PORT2_QUEUE5_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367D_REG_SCHEDULE_PORT2_QUEUE6_WFQ_WEIGHT 0x0322 +#define RTL8367D_SCHEDULE_PORT2_QUEUE6_WFQ_WEIGHT_OFFSET 0 +#define RTL8367D_SCHEDULE_PORT2_QUEUE6_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367D_REG_SCHEDULE_PORT2_QUEUE7_WFQ_WEIGHT 0x0323 +#define RTL8367D_SCHEDULE_PORT2_QUEUE7_WFQ_WEIGHT_OFFSET 0 +#define RTL8367D_SCHEDULE_PORT2_QUEUE7_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367D_REG_SCHEDULE_PORT3_QUEUE0_WFQ_WEIGHT 0x0324 + +#define RTL8367D_REG_SCHEDULE_PORT3_QUEUE1_WFQ_WEIGHT 0x0325 +#define RTL8367D_SCHEDULE_PORT3_QUEUE1_WFQ_WEIGHT_OFFSET 0 +#define RTL8367D_SCHEDULE_PORT3_QUEUE1_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367D_REG_SCHEDULE_PORT3_QUEUE2_WFQ_WEIGHT 0x0326 +#define RTL8367D_SCHEDULE_PORT3_QUEUE2_WFQ_WEIGHT_OFFSET 0 +#define RTL8367D_SCHEDULE_PORT3_QUEUE2_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367D_REG_SCHEDULE_PORT3_QUEUE3_WFQ_WEIGHT 0x0327 +#define RTL8367D_SCHEDULE_PORT3_QUEUE3_WFQ_WEIGHT_OFFSET 0 +#define RTL8367D_SCHEDULE_PORT3_QUEUE3_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367D_REG_SCHEDULE_PORT3_QUEUE4_WFQ_WEIGHT 0x0328 +#define RTL8367D_SCHEDULE_PORT3_QUEUE4_WFQ_WEIGHT_OFFSET 0 +#define RTL8367D_SCHEDULE_PORT3_QUEUE4_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367D_REG_SCHEDULE_PORT3_QUEUE5_WFQ_WEIGHT 0x0329 +#define RTL8367D_SCHEDULE_PORT3_QUEUE5_WFQ_WEIGHT_OFFSET 0 +#define RTL8367D_SCHEDULE_PORT3_QUEUE5_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367D_REG_SCHEDULE_PORT3_QUEUE6_WFQ_WEIGHT 0x032a +#define RTL8367D_SCHEDULE_PORT3_QUEUE6_WFQ_WEIGHT_OFFSET 0 +#define RTL8367D_SCHEDULE_PORT3_QUEUE6_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367D_REG_SCHEDULE_PORT3_QUEUE7_WFQ_WEIGHT 0x032b +#define RTL8367D_SCHEDULE_PORT3_QUEUE7_WFQ_WEIGHT_OFFSET 0 +#define RTL8367D_SCHEDULE_PORT3_QUEUE7_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367D_REG_SCHEDULE_PORT4_QUEUE0_WFQ_WEIGHT 0x032c + +#define RTL8367D_REG_SCHEDULE_PORT4_QUEUE1_WFQ_WEIGHT 0x032d +#define RTL8367D_SCHEDULE_PORT4_QUEUE1_WFQ_WEIGHT_OFFSET 0 +#define RTL8367D_SCHEDULE_PORT4_QUEUE1_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367D_REG_SCHEDULE_PORT4_QUEUE2_WFQ_WEIGHT 0x032e +#define RTL8367D_SCHEDULE_PORT4_QUEUE2_WFQ_WEIGHT_OFFSET 0 +#define RTL8367D_SCHEDULE_PORT4_QUEUE2_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367D_REG_SCHEDULE_PORT4_QUEUE3_WFQ_WEIGHT 0x032f +#define RTL8367D_SCHEDULE_PORT4_QUEUE3_WFQ_WEIGHT_OFFSET 0 +#define RTL8367D_SCHEDULE_PORT4_QUEUE3_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367D_REG_SCHEDULE_PORT4_QUEUE4_WFQ_WEIGHT 0x0330 +#define RTL8367D_SCHEDULE_PORT4_QUEUE4_WFQ_WEIGHT_OFFSET 0 +#define RTL8367D_SCHEDULE_PORT4_QUEUE4_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367D_REG_SCHEDULE_PORT4_QUEUE5_WFQ_WEIGHT 0x0331 +#define RTL8367D_SCHEDULE_PORT4_QUEUE5_WFQ_WEIGHT_OFFSET 0 +#define RTL8367D_SCHEDULE_PORT4_QUEUE5_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367D_REG_SCHEDULE_PORT4_QUEUE6_WFQ_WEIGHT 0x0332 +#define RTL8367D_SCHEDULE_PORT4_QUEUE6_WFQ_WEIGHT_OFFSET 0 +#define RTL8367D_SCHEDULE_PORT4_QUEUE6_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367D_REG_SCHEDULE_PORT4_QUEUE7_WFQ_WEIGHT 0x0333 +#define RTL8367D_SCHEDULE_PORT4_QUEUE7_WFQ_WEIGHT_OFFSET 0 +#define RTL8367D_SCHEDULE_PORT4_QUEUE7_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367D_REG_SCHEDULE_PORT5_QUEUE0_WFQ_WEIGHT 0x0334 + +#define RTL8367D_REG_SCHEDULE_PORT5_QUEUE1_WFQ_WEIGHT 0x0335 +#define RTL8367D_SCHEDULE_PORT5_QUEUE1_WFQ_WEIGHT_OFFSET 0 +#define RTL8367D_SCHEDULE_PORT5_QUEUE1_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367D_REG_SCHEDULE_PORT5_QUEUE2_WFQ_WEIGHT 0x0336 +#define RTL8367D_SCHEDULE_PORT5_QUEUE2_WFQ_WEIGHT_OFFSET 0 +#define RTL8367D_SCHEDULE_PORT5_QUEUE2_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367D_REG_SCHEDULE_PORT5_QUEUE3_WFQ_WEIGHT 0x0337 +#define RTL8367D_SCHEDULE_PORT5_QUEUE3_WFQ_WEIGHT_OFFSET 0 +#define RTL8367D_SCHEDULE_PORT5_QUEUE3_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367D_REG_SCHEDULE_PORT5_QUEUE4_WFQ_WEIGHT 0x0338 +#define RTL8367D_SCHEDULE_PORT5_QUEUE4_WFQ_WEIGHT_OFFSET 0 +#define RTL8367D_SCHEDULE_PORT5_QUEUE4_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367D_REG_SCHEDULE_PORT5_QUEUE5_WFQ_WEIGHT 0x0339 +#define RTL8367D_SCHEDULE_PORT5_QUEUE5_WFQ_WEIGHT_OFFSET 0 +#define RTL8367D_SCHEDULE_PORT5_QUEUE5_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367D_REG_SCHEDULE_PORT5_QUEUE6_WFQ_WEIGHT 0x033a +#define RTL8367D_SCHEDULE_PORT5_QUEUE6_WFQ_WEIGHT_OFFSET 0 +#define RTL8367D_SCHEDULE_PORT5_QUEUE6_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367D_REG_SCHEDULE_PORT5_QUEUE7_WFQ_WEIGHT 0x033b +#define RTL8367D_SCHEDULE_PORT5_QUEUE7_WFQ_WEIGHT_OFFSET 0 +#define RTL8367D_SCHEDULE_PORT5_QUEUE7_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367D_REG_SCHEDULE_PORT6_QUEUE0_WFQ_WEIGHT 0x033c + +#define RTL8367D_REG_SCHEDULE_PORT6_QUEUE1_WFQ_WEIGHT 0x033d +#define RTL8367D_SCHEDULE_PORT6_QUEUE1_WFQ_WEIGHT_OFFSET 0 +#define RTL8367D_SCHEDULE_PORT6_QUEUE1_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367D_REG_SCHEDULE_PORT6_QUEUE2_WFQ_WEIGHT 0x033e +#define RTL8367D_SCHEDULE_PORT6_QUEUE2_WFQ_WEIGHT_OFFSET 0 +#define RTL8367D_SCHEDULE_PORT6_QUEUE2_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367D_REG_SCHEDULE_PORT6_QUEUE3_WFQ_WEIGHT 0x033f +#define RTL8367D_SCHEDULE_PORT6_QUEUE3_WFQ_WEIGHT_OFFSET 0 +#define RTL8367D_SCHEDULE_PORT6_QUEUE3_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367D_REG_SCHEDULE_PORT6_QUEUE4_WFQ_WEIGHT 0x0340 +#define RTL8367D_SCHEDULE_PORT6_QUEUE4_WFQ_WEIGHT_OFFSET 0 +#define RTL8367D_SCHEDULE_PORT6_QUEUE4_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367D_REG_SCHEDULE_PORT6_QUEUE5_WFQ_WEIGHT 0x0341 +#define RTL8367D_SCHEDULE_PORT6_QUEUE5_WFQ_WEIGHT_OFFSET 0 +#define RTL8367D_SCHEDULE_PORT6_QUEUE5_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367D_REG_SCHEDULE_PORT6_QUEUE6_WFQ_WEIGHT 0x0342 +#define RTL8367D_SCHEDULE_PORT6_QUEUE6_WFQ_WEIGHT_OFFSET 0 +#define RTL8367D_SCHEDULE_PORT6_QUEUE6_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367D_REG_SCHEDULE_PORT6_QUEUE7_WFQ_WEIGHT 0x0343 +#define RTL8367D_SCHEDULE_PORT6_QUEUE7_WFQ_WEIGHT_OFFSET 0 +#define RTL8367D_SCHEDULE_PORT6_QUEUE7_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367D_REG_SCHEDULE_PORT7_QUEUE0_WFQ_WEIGHT 0x0344 + +#define RTL8367D_REG_SCHEDULE_PORT7_QUEUE1_WFQ_WEIGHT 0x0345 +#define RTL8367D_SCHEDULE_PORT7_QUEUE1_WFQ_WEIGHT_OFFSET 0 +#define RTL8367D_SCHEDULE_PORT7_QUEUE1_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367D_REG_SCHEDULE_PORT7_QUEUE2_WFQ_WEIGHT 0x0346 +#define RTL8367D_SCHEDULE_PORT7_QUEUE2_WFQ_WEIGHT_OFFSET 0 +#define RTL8367D_SCHEDULE_PORT7_QUEUE2_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367D_REG_SCHEDULE_PORT7_QUEUE3_WFQ_WEIGHT 0x0347 +#define RTL8367D_SCHEDULE_PORT7_QUEUE3_WFQ_WEIGHT_OFFSET 0 +#define RTL8367D_SCHEDULE_PORT7_QUEUE3_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367D_REG_SCHEDULE_PORT7_QUEUE4_WFQ_WEIGHT 0x0348 +#define RTL8367D_SCHEDULE_PORT7_QUEUE4_WFQ_WEIGHT_OFFSET 0 +#define RTL8367D_SCHEDULE_PORT7_QUEUE4_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367D_REG_SCHEDULE_PORT7_QUEUE5_WFQ_WEIGHT 0x0349 +#define RTL8367D_SCHEDULE_PORT7_QUEUE5_WFQ_WEIGHT_OFFSET 0 +#define RTL8367D_SCHEDULE_PORT7_QUEUE5_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367D_REG_SCHEDULE_PORT7_QUEUE6_WFQ_WEIGHT 0x034a +#define RTL8367D_SCHEDULE_PORT7_QUEUE6_WFQ_WEIGHT_OFFSET 0 +#define RTL8367D_SCHEDULE_PORT7_QUEUE6_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367D_REG_SCHEDULE_PORT7_QUEUE7_WFQ_WEIGHT 0x034b +#define RTL8367D_SCHEDULE_PORT7_QUEUE7_WFQ_WEIGHT_OFFSET 0 +#define RTL8367D_SCHEDULE_PORT7_QUEUE7_WFQ_WEIGHT_MASK 0x7F + +#define RTL8367D_REG_PORT0_EGRESSBW_CTRL0 0x038c + +#define RTL8367D_REG_PORT0_EGRESSBW_CTRL1 0x038d +#define RTL8367D_PORT0_EGRESSBW_CTRL1_OFFSET 0 +#define RTL8367D_PORT0_EGRESSBW_CTRL1_MASK 0x1 + +#define RTL8367D_REG_PORT1_EGRESSBW_CTRL0 0x038e + +#define RTL8367D_REG_PORT1_EGRESSBW_CTRL1 0x038f +#define RTL8367D_PORT1_EGRESSBW_CTRL1_OFFSET 0 +#define RTL8367D_PORT1_EGRESSBW_CTRL1_MASK 0x1 + +#define RTL8367D_REG_PORT2_EGRESSBW_CTRL0 0x0390 + +#define RTL8367D_REG_PORT2_EGRESSBW_CTRL1 0x0391 +#define RTL8367D_PORT2_EGRESSBW_CTRL1_OFFSET 0 +#define RTL8367D_PORT2_EGRESSBW_CTRL1_MASK 0x1 + +#define RTL8367D_REG_PORT3_EGRESSBW_CTRL0 0x0392 + +#define RTL8367D_REG_PORT3_EGRESSBW_CTRL1 0x0393 +#define RTL8367D_PORT3_EGRESSBW_CTRL1_OFFSET 0 +#define RTL8367D_PORT3_EGRESSBW_CTRL1_MASK 0x1 + +#define RTL8367D_REG_PORT4_EGRESSBW_CTRL0 0x0394 + +#define RTL8367D_REG_PORT4_EGRESSBW_CTRL1 0x0395 +#define RTL8367D_PORT4_EGRESSBW_CTRL1_OFFSET 0 +#define RTL8367D_PORT4_EGRESSBW_CTRL1_MASK 0x1 + +#define RTL8367D_REG_PORT5_EGRESSBW_CTRL0 0x0396 + +#define RTL8367D_REG_PORT5_EGRESSBW_CTRL1 0x0397 +#define RTL8367D_PORT5_EGRESSBW_CTRL1_OFFSET 0 +#define RTL8367D_PORT5_EGRESSBW_CTRL1_MASK 0x1 + +#define RTL8367D_REG_PORT6_EGRESSBW_CTRL0 0x0398 + +#define RTL8367D_REG_PORT6_EGRESSBW_CTRL1 0x0399 +#define RTL8367D_PORT6_EGRESSBW_CTRL1_OFFSET 0 +#define RTL8367D_PORT6_EGRESSBW_CTRL1_MASK 0x7 + +#define RTL8367D_REG_PORT7_EGRESSBW_CTRL0 0x039a + +#define RTL8367D_REG_PORT7_EGRESSBW_CTRL1 0x039b +#define RTL8367D_PORT7_EGRESSBW_CTRL1_OFFSET 0 +#define RTL8367D_PORT7_EGRESSBW_CTRL1_MASK 0x7 + +#define RTL8367D_REG_SCHEDULE_PORT0_APR_METER_CTRL0 0x03ac +#define RTL8367D_SCHEDULE_PORT0_APR_METER_CTRL0_QUEUE4_APR_METER_OFFSET 12 +#define RTL8367D_SCHEDULE_PORT0_APR_METER_CTRL0_QUEUE4_APR_METER_MASK 0x7000 +#define RTL8367D_SCHEDULE_PORT0_APR_METER_CTRL0_QUEUE3_APR_METER_OFFSET 9 +#define RTL8367D_SCHEDULE_PORT0_APR_METER_CTRL0_QUEUE3_APR_METER_MASK 0xE00 +#define RTL8367D_SCHEDULE_PORT0_APR_METER_CTRL0_QUEUE2_APR_METER_OFFSET 6 +#define RTL8367D_SCHEDULE_PORT0_APR_METER_CTRL0_QUEUE2_APR_METER_MASK 0x1C0 +#define RTL8367D_SCHEDULE_PORT0_APR_METER_CTRL0_QUEUE1_APR_METER_OFFSET 3 +#define RTL8367D_SCHEDULE_PORT0_APR_METER_CTRL0_QUEUE1_APR_METER_MASK 0x38 +#define RTL8367D_SCHEDULE_PORT0_APR_METER_CTRL0_QUEUE0_APR_METER_OFFSET 0 +#define RTL8367D_SCHEDULE_PORT0_APR_METER_CTRL0_QUEUE0_APR_METER_MASK 0x7 + +#define RTL8367D_REG_SCHEDULE_PORT0_APR_METER_CTRL1 0x03ad +#define RTL8367D_SCHEDULE_PORT0_APR_METER_CTRL1_QUEUE7_APR_METER_OFFSET 6 +#define RTL8367D_SCHEDULE_PORT0_APR_METER_CTRL1_QUEUE7_APR_METER_MASK 0x1C0 +#define RTL8367D_SCHEDULE_PORT0_APR_METER_CTRL1_QUEUE6_APR_METER_OFFSET 3 +#define RTL8367D_SCHEDULE_PORT0_APR_METER_CTRL1_QUEUE6_APR_METER_MASK 0x38 +#define RTL8367D_SCHEDULE_PORT0_APR_METER_CTRL1_QUEUE5_APR_METER_OFFSET 0 +#define RTL8367D_SCHEDULE_PORT0_APR_METER_CTRL1_QUEUE5_APR_METER_MASK 0x7 + +#define RTL8367D_REG_SCHEDULE_PORT1_APR_METER_CTRL0 0x03b0 +#define RTL8367D_SCHEDULE_PORT1_APR_METER_CTRL0_QUEUE4_APR_METER_OFFSET 12 +#define RTL8367D_SCHEDULE_PORT1_APR_METER_CTRL0_QUEUE4_APR_METER_MASK 0x7000 +#define RTL8367D_SCHEDULE_PORT1_APR_METER_CTRL0_QUEUE3_APR_METER_OFFSET 9 +#define RTL8367D_SCHEDULE_PORT1_APR_METER_CTRL0_QUEUE3_APR_METER_MASK 0xE00 +#define RTL8367D_SCHEDULE_PORT1_APR_METER_CTRL0_QUEUE2_APR_METER_OFFSET 6 +#define RTL8367D_SCHEDULE_PORT1_APR_METER_CTRL0_QUEUE2_APR_METER_MASK 0x1C0 +#define RTL8367D_SCHEDULE_PORT1_APR_METER_CTRL0_QUEUE1_APR_METER_OFFSET 3 +#define RTL8367D_SCHEDULE_PORT1_APR_METER_CTRL0_QUEUE1_APR_METER_MASK 0x38 +#define RTL8367D_SCHEDULE_PORT1_APR_METER_CTRL0_QUEUE0_APR_METER_OFFSET 0 +#define RTL8367D_SCHEDULE_PORT1_APR_METER_CTRL0_QUEUE0_APR_METER_MASK 0x7 + +#define RTL8367D_REG_SCHEDULE_PORT1_APR_METER_CTRL1 0x03b1 +#define RTL8367D_SCHEDULE_PORT1_APR_METER_CTRL1_QUEUE7_APR_METER_OFFSET 6 +#define RTL8367D_SCHEDULE_PORT1_APR_METER_CTRL1_QUEUE7_APR_METER_MASK 0x1C0 +#define RTL8367D_SCHEDULE_PORT1_APR_METER_CTRL1_QUEUE6_APR_METER_OFFSET 3 +#define RTL8367D_SCHEDULE_PORT1_APR_METER_CTRL1_QUEUE6_APR_METER_MASK 0x38 +#define RTL8367D_SCHEDULE_PORT1_APR_METER_CTRL1_QUEUE5_APR_METER_OFFSET 0 +#define RTL8367D_SCHEDULE_PORT1_APR_METER_CTRL1_QUEUE5_APR_METER_MASK 0x7 + +#define RTL8367D_REG_SCHEDULE_PORT2_APR_METER_CTRL0 0x03b4 +#define RTL8367D_SCHEDULE_PORT2_APR_METER_CTRL0_QUEUE4_APR_METER_OFFSET 12 +#define RTL8367D_SCHEDULE_PORT2_APR_METER_CTRL0_QUEUE4_APR_METER_MASK 0x7000 +#define RTL8367D_SCHEDULE_PORT2_APR_METER_CTRL0_QUEUE3_APR_METER_OFFSET 9 +#define RTL8367D_SCHEDULE_PORT2_APR_METER_CTRL0_QUEUE3_APR_METER_MASK 0xE00 +#define RTL8367D_SCHEDULE_PORT2_APR_METER_CTRL0_QUEUE2_APR_METER_OFFSET 6 +#define RTL8367D_SCHEDULE_PORT2_APR_METER_CTRL0_QUEUE2_APR_METER_MASK 0x1C0 +#define RTL8367D_SCHEDULE_PORT2_APR_METER_CTRL0_QUEUE1_APR_METER_OFFSET 3 +#define RTL8367D_SCHEDULE_PORT2_APR_METER_CTRL0_QUEUE1_APR_METER_MASK 0x38 +#define RTL8367D_SCHEDULE_PORT2_APR_METER_CTRL0_QUEUE0_APR_METER_OFFSET 0 +#define RTL8367D_SCHEDULE_PORT2_APR_METER_CTRL0_QUEUE0_APR_METER_MASK 0x7 + +#define RTL8367D_REG_SCHEDULE_PORT2_APR_METER_CTRL1 0x03b5 +#define RTL8367D_SCHEDULE_PORT2_APR_METER_CTRL1_QUEUE7_APR_METER_OFFSET 6 +#define RTL8367D_SCHEDULE_PORT2_APR_METER_CTRL1_QUEUE7_APR_METER_MASK 0x1C0 +#define RTL8367D_SCHEDULE_PORT2_APR_METER_CTRL1_QUEUE6_APR_METER_OFFSET 3 +#define RTL8367D_SCHEDULE_PORT2_APR_METER_CTRL1_QUEUE6_APR_METER_MASK 0x38 +#define RTL8367D_SCHEDULE_PORT2_APR_METER_CTRL1_QUEUE5_APR_METER_OFFSET 0 +#define RTL8367D_SCHEDULE_PORT2_APR_METER_CTRL1_QUEUE5_APR_METER_MASK 0x7 + +#define RTL8367D_REG_SCHEDULE_PORT3_APR_METER_CTRL0 0x03b8 +#define RTL8367D_SCHEDULE_PORT3_APR_METER_CTRL0_QUEUE4_APR_METER_OFFSET 12 +#define RTL8367D_SCHEDULE_PORT3_APR_METER_CTRL0_QUEUE4_APR_METER_MASK 0x7000 +#define RTL8367D_SCHEDULE_PORT3_APR_METER_CTRL0_QUEUE3_APR_METER_OFFSET 9 +#define RTL8367D_SCHEDULE_PORT3_APR_METER_CTRL0_QUEUE3_APR_METER_MASK 0xE00 +#define RTL8367D_SCHEDULE_PORT3_APR_METER_CTRL0_QUEUE2_APR_METER_OFFSET 6 +#define RTL8367D_SCHEDULE_PORT3_APR_METER_CTRL0_QUEUE2_APR_METER_MASK 0x1C0 +#define RTL8367D_SCHEDULE_PORT3_APR_METER_CTRL0_QUEUE1_APR_METER_OFFSET 3 +#define RTL8367D_SCHEDULE_PORT3_APR_METER_CTRL0_QUEUE1_APR_METER_MASK 0x38 +#define RTL8367D_SCHEDULE_PORT3_APR_METER_CTRL0_QUEUE0_APR_METER_OFFSET 0 +#define RTL8367D_SCHEDULE_PORT3_APR_METER_CTRL0_QUEUE0_APR_METER_MASK 0x7 + +#define RTL8367D_REG_SCHEDULE_PORT3_APR_METER_CTRL1 0x03b9 +#define RTL8367D_SCHEDULE_PORT3_APR_METER_CTRL1_QUEUE7_APR_METER_OFFSET 6 +#define RTL8367D_SCHEDULE_PORT3_APR_METER_CTRL1_QUEUE7_APR_METER_MASK 0x1C0 +#define RTL8367D_SCHEDULE_PORT3_APR_METER_CTRL1_QUEUE6_APR_METER_OFFSET 3 +#define RTL8367D_SCHEDULE_PORT3_APR_METER_CTRL1_QUEUE6_APR_METER_MASK 0x38 +#define RTL8367D_SCHEDULE_PORT3_APR_METER_CTRL1_QUEUE5_APR_METER_OFFSET 0 +#define RTL8367D_SCHEDULE_PORT3_APR_METER_CTRL1_QUEUE5_APR_METER_MASK 0x7 + +#define RTL8367D_REG_SCHEDULE_PORT4_APR_METER_CTRL0 0x03bc +#define RTL8367D_SCHEDULE_PORT4_APR_METER_CTRL0_QUEUE4_APR_METER_OFFSET 12 +#define RTL8367D_SCHEDULE_PORT4_APR_METER_CTRL0_QUEUE4_APR_METER_MASK 0x7000 +#define RTL8367D_SCHEDULE_PORT4_APR_METER_CTRL0_QUEUE3_APR_METER_OFFSET 9 +#define RTL8367D_SCHEDULE_PORT4_APR_METER_CTRL0_QUEUE3_APR_METER_MASK 0xE00 +#define RTL8367D_SCHEDULE_PORT4_APR_METER_CTRL0_QUEUE2_APR_METER_OFFSET 6 +#define RTL8367D_SCHEDULE_PORT4_APR_METER_CTRL0_QUEUE2_APR_METER_MASK 0x1C0 +#define RTL8367D_SCHEDULE_PORT4_APR_METER_CTRL0_QUEUE1_APR_METER_OFFSET 3 +#define RTL8367D_SCHEDULE_PORT4_APR_METER_CTRL0_QUEUE1_APR_METER_MASK 0x38 +#define RTL8367D_SCHEDULE_PORT4_APR_METER_CTRL0_QUEUE0_APR_METER_OFFSET 0 +#define RTL8367D_SCHEDULE_PORT4_APR_METER_CTRL0_QUEUE0_APR_METER_MASK 0x7 + +#define RTL8367D_REG_SCHEDULE_PORT4_APR_METER_CTRL1 0x03bd +#define RTL8367D_SCHEDULE_PORT4_APR_METER_CTRL1_QUEUE7_APR_METER_OFFSET 6 +#define RTL8367D_SCHEDULE_PORT4_APR_METER_CTRL1_QUEUE7_APR_METER_MASK 0x1C0 +#define RTL8367D_SCHEDULE_PORT4_APR_METER_CTRL1_QUEUE6_APR_METER_OFFSET 3 +#define RTL8367D_SCHEDULE_PORT4_APR_METER_CTRL1_QUEUE6_APR_METER_MASK 0x38 +#define RTL8367D_SCHEDULE_PORT4_APR_METER_CTRL1_QUEUE5_APR_METER_OFFSET 0 +#define RTL8367D_SCHEDULE_PORT4_APR_METER_CTRL1_QUEUE5_APR_METER_MASK 0x7 + +#define RTL8367D_REG_SCHEDULE_PORT5_APR_METER_CTRL0 0x03c0 +#define RTL8367D_SCHEDULE_PORT5_APR_METER_CTRL0_QUEUE4_APR_METER_OFFSET 12 +#define RTL8367D_SCHEDULE_PORT5_APR_METER_CTRL0_QUEUE4_APR_METER_MASK 0x7000 +#define RTL8367D_SCHEDULE_PORT5_APR_METER_CTRL0_QUEUE3_APR_METER_OFFSET 9 +#define RTL8367D_SCHEDULE_PORT5_APR_METER_CTRL0_QUEUE3_APR_METER_MASK 0xE00 +#define RTL8367D_SCHEDULE_PORT5_APR_METER_CTRL0_QUEUE2_APR_METER_OFFSET 6 +#define RTL8367D_SCHEDULE_PORT5_APR_METER_CTRL0_QUEUE2_APR_METER_MASK 0x1C0 +#define RTL8367D_SCHEDULE_PORT5_APR_METER_CTRL0_QUEUE1_APR_METER_OFFSET 3 +#define RTL8367D_SCHEDULE_PORT5_APR_METER_CTRL0_QUEUE1_APR_METER_MASK 0x38 +#define RTL8367D_SCHEDULE_PORT5_APR_METER_CTRL0_QUEUE0_APR_METER_OFFSET 0 +#define RTL8367D_SCHEDULE_PORT5_APR_METER_CTRL0_QUEUE0_APR_METER_MASK 0x7 + +#define RTL8367D_REG_SCHEDULE_PORT5_APR_METER_CTRL1 0x03c1 +#define RTL8367D_SCHEDULE_PORT5_APR_METER_CTRL1_QUEUE7_APR_METER_OFFSET 6 +#define RTL8367D_SCHEDULE_PORT5_APR_METER_CTRL1_QUEUE7_APR_METER_MASK 0x1C0 +#define RTL8367D_SCHEDULE_PORT5_APR_METER_CTRL1_QUEUE6_APR_METER_OFFSET 3 +#define RTL8367D_SCHEDULE_PORT5_APR_METER_CTRL1_QUEUE6_APR_METER_MASK 0x38 +#define RTL8367D_SCHEDULE_PORT5_APR_METER_CTRL1_QUEUE5_APR_METER_OFFSET 0 +#define RTL8367D_SCHEDULE_PORT5_APR_METER_CTRL1_QUEUE5_APR_METER_MASK 0x7 + +#define RTL8367D_REG_SCHEDULE_PORT6_APR_METER_CTRL0 0x03c4 +#define RTL8367D_SCHEDULE_PORT6_APR_METER_CTRL0_QUEUE4_APR_METER_OFFSET 12 +#define RTL8367D_SCHEDULE_PORT6_APR_METER_CTRL0_QUEUE4_APR_METER_MASK 0x7000 +#define RTL8367D_SCHEDULE_PORT6_APR_METER_CTRL0_QUEUE3_APR_METER_OFFSET 9 +#define RTL8367D_SCHEDULE_PORT6_APR_METER_CTRL0_QUEUE3_APR_METER_MASK 0xE00 +#define RTL8367D_SCHEDULE_PORT6_APR_METER_CTRL0_QUEUE2_APR_METER_OFFSET 6 +#define RTL8367D_SCHEDULE_PORT6_APR_METER_CTRL0_QUEUE2_APR_METER_MASK 0x1C0 +#define RTL8367D_SCHEDULE_PORT6_APR_METER_CTRL0_QUEUE1_APR_METER_OFFSET 3 +#define RTL8367D_SCHEDULE_PORT6_APR_METER_CTRL0_QUEUE1_APR_METER_MASK 0x38 +#define RTL8367D_SCHEDULE_PORT6_APR_METER_CTRL0_QUEUE0_APR_METER_OFFSET 0 +#define RTL8367D_SCHEDULE_PORT6_APR_METER_CTRL0_QUEUE0_APR_METER_MASK 0x7 + +#define RTL8367D_REG_SCHEDULE_PORT6_APR_METER_CTRL1 0x03c5 +#define RTL8367D_SCHEDULE_PORT6_APR_METER_CTRL1_QUEUE7_APR_METER_OFFSET 6 +#define RTL8367D_SCHEDULE_PORT6_APR_METER_CTRL1_QUEUE7_APR_METER_MASK 0x1C0 +#define RTL8367D_SCHEDULE_PORT6_APR_METER_CTRL1_QUEUE6_APR_METER_OFFSET 3 +#define RTL8367D_SCHEDULE_PORT6_APR_METER_CTRL1_QUEUE6_APR_METER_MASK 0x38 +#define RTL8367D_SCHEDULE_PORT6_APR_METER_CTRL1_QUEUE5_APR_METER_OFFSET 0 +#define RTL8367D_SCHEDULE_PORT6_APR_METER_CTRL1_QUEUE5_APR_METER_MASK 0x7 + +#define RTL8367D_REG_SCHEDULE_PORT7_APR_METER_CTRL0 0x03c8 +#define RTL8367D_SCHEDULE_PORT7_APR_METER_CTRL0_QUEUE4_APR_METER_OFFSET 12 +#define RTL8367D_SCHEDULE_PORT7_APR_METER_CTRL0_QUEUE4_APR_METER_MASK 0x7000 +#define RTL8367D_SCHEDULE_PORT7_APR_METER_CTRL0_QUEUE3_APR_METER_OFFSET 9 +#define RTL8367D_SCHEDULE_PORT7_APR_METER_CTRL0_QUEUE3_APR_METER_MASK 0xE00 +#define RTL8367D_SCHEDULE_PORT7_APR_METER_CTRL0_QUEUE2_APR_METER_OFFSET 6 +#define RTL8367D_SCHEDULE_PORT7_APR_METER_CTRL0_QUEUE2_APR_METER_MASK 0x1C0 +#define RTL8367D_SCHEDULE_PORT7_APR_METER_CTRL0_QUEUE1_APR_METER_OFFSET 3 +#define RTL8367D_SCHEDULE_PORT7_APR_METER_CTRL0_QUEUE1_APR_METER_MASK 0x38 +#define RTL8367D_SCHEDULE_PORT7_APR_METER_CTRL0_QUEUE0_APR_METER_OFFSET 0 +#define RTL8367D_SCHEDULE_PORT7_APR_METER_CTRL0_QUEUE0_APR_METER_MASK 0x7 + +#define RTL8367D_REG_SCHEDULE_PORT7_APR_METER_CTRL1 0x03c9 +#define RTL8367D_SCHEDULE_PORT7_APR_METER_CTRL1_QUEUE7_APR_METER_OFFSET 6 +#define RTL8367D_SCHEDULE_PORT7_APR_METER_CTRL1_QUEUE7_APR_METER_MASK 0x1C0 +#define RTL8367D_SCHEDULE_PORT7_APR_METER_CTRL1_QUEUE6_APR_METER_OFFSET 3 +#define RTL8367D_SCHEDULE_PORT7_APR_METER_CTRL1_QUEUE6_APR_METER_MASK 0x38 +#define RTL8367D_SCHEDULE_PORT7_APR_METER_CTRL1_QUEUE5_APR_METER_OFFSET 0 +#define RTL8367D_SCHEDULE_PORT7_APR_METER_CTRL1_QUEUE5_APR_METER_MASK 0x7 + +#define RTL8367D_REG_LINE_RATE_1G_L 0x03ec + +#define RTL8367D_REG_LINE_RATE_1G_H 0x03ed +#define RTL8367D_LINE_RATE_1G_H_OFFSET 0 +#define RTL8367D_LINE_RATE_1G_H_MASK 0x1 + +#define RTL8367D_REG_LINE_RATE_100_L 0x03ee + +#define RTL8367D_REG_LINE_RATE_100_H 0x03ef +#define RTL8367D_LINE_RATE_100_H_OFFSET 0 +#define RTL8367D_LINE_RATE_100_H_MASK 0x1 + +#define RTL8367D_REG_LINE_RATE_10_L 0x03f0 + +#define RTL8367D_REG_LINE_RATE_10_H 0x03f1 +#define RTL8367D_LINE_RATE_10_H_OFFSET 0 +#define RTL8367D_LINE_RATE_10_H_MASK 0x1 + +#define RTL8367D_REG_BYPASS_LINE_RATE 0x03f7 +#define RTL8367D_BYPASS_PORT7_CONSTRAINT_OFFSET 2 +#define RTL8367D_BYPASS_PORT7_CONSTRAINT_MASK 0x4 +#define RTL8367D_BYPASS_PORT6_CONSTRAINT_OFFSET 1 +#define RTL8367D_BYPASS_PORT6_CONSTRAINT_MASK 0x2 +#define RTL8367D_BYPASS_PORT5_CONSTRAINT_OFFSET 0 +#define RTL8367D_BYPASS_PORT5_CONSTRAINT_MASK 0x1 + +#define RTL8367D_REG_LINE_RATE_500_H 0x03f8 +#define RTL8367D_LINE_RATE_500_H_OFFSET 0 +#define RTL8367D_LINE_RATE_500_H_MASK 0x7 + +#define RTL8367D_REG_LINE_RATE_500_L 0x03f9 + +#define RTL8367D_REG_LINE_RATE_HSG_H 0x03fa +#define RTL8367D_LINE_RATE_HSG_H_OFFSET 0 +#define RTL8367D_LINE_RATE_HSG_H_MASK 0x7 + +#define RTL8367D_REG_LINE_RATE_HSG_L 0x03fb + +#define RTL8367D_REG_SCH_WRR_OPT 0x03fc +#define RTL8367D_CFG_WRR_MODE_OFFSET 14 +#define RTL8367D_CFG_WRR_MODE_MASK 0x4000 +#define RTL8367D_CFG_WRR_PKTLEN_OFFSET 0 +#define RTL8367D_CFG_WRR_PKTLEN_MASK 0x3FFF + +/* (16'h0500)table_reg */ + +#define RTL8367D_REG_TABLE_ACCESS_CTRL 0x0500 +#define RTL8367D_TABLE_ACCESS_CTRL_SPA_OFFSET 8 +#define RTL8367D_TABLE_ACCESS_CTRL_SPA_MASK 0x700 +#define RTL8367D_ACCESS_METHOD_OFFSET 4 +#define RTL8367D_ACCESS_METHOD_MASK 0x70 +#define RTL8367D_COMMAND_TYPE_OFFSET 3 +#define RTL8367D_COMMAND_TYPE_MASK 0x8 +#define RTL8367D_TABLE_TYPE_OFFSET 0 +#define RTL8367D_TABLE_TYPE_MASK 0x7 + +#define RTL8367D_REG_TABLE_ACCESS_ADDR 0x0501 +#define RTL8367D_TABLE_ACCESS_ADDR_OFFSET 0 +#define RTL8367D_TABLE_ACCESS_ADDR_MASK 0xFFF + +#define RTL8367D_REG_TABLE_LUT_ADDR 0x0502 +#define RTL8367D_TABLE_LUT_ADDR_BUSY_FLAG_OFFSET 13 +#define RTL8367D_TABLE_LUT_ADDR_BUSY_FLAG_MASK 0x2000 +#define RTL8367D_HIT_STATUS_OFFSET 12 +#define RTL8367D_HIT_STATUS_MASK 0x1000 +#define RTL8367D_TYPE_OFFSET 11 +#define RTL8367D_TYPE_MASK 0x800 +#define RTL8367D_TABLE_LUT_ADDR_ADDRESS_OFFSET 0 +#define RTL8367D_TABLE_LUT_ADDR_ADDRESS_MASK 0x7FF + +#define RTL8367D_REG_HSA_HSB_LATCH 0x0503 +#define RTL8367D_LATCH_ALWAYS_OFFSET 15 +#define RTL8367D_LATCH_ALWAYS_MASK 0x8000 +#define RTL8367D_LATCH_FIRST_OFFSET 14 +#define RTL8367D_LATCH_FIRST_MASK 0x4000 +#define RTL8367D_SPA_EN_OFFSET 13 +#define RTL8367D_SPA_EN_MASK 0x2000 +#define RTL8367D_FORWARD_EN_OFFSET 12 +#define RTL8367D_FORWARD_EN_MASK 0x1000 +#define RTL8367D_REASON_EN_OFFSET 11 +#define RTL8367D_REASON_EN_MASK 0x800 +#define RTL8367D_HSA_HSB_LATCH_SPA_OFFSET 8 +#define RTL8367D_HSA_HSB_LATCH_SPA_MASK 0x700 +#define RTL8367D_FORWARD_OFFSET 6 +#define RTL8367D_FORWARD_MASK 0xC0 +#define RTL8367D_REASON_OFFSET 0 +#define RTL8367D_REASON_MASK 0x3F + +#define RTL8367D_REG_TABLE_WRITE_DATA0 0x0510 + +#define RTL8367D_REG_TABLE_WRITE_DATA1 0x0511 + +#define RTL8367D_REG_TABLE_WRITE_DATA2 0x0512 + +#define RTL8367D_REG_TABLE_WRITE_DATA3 0x0513 + +#define RTL8367D_REG_TABLE_WRITE_DATA4 0x0514 + +#define RTL8367D_REG_TABLE_WRITE_DATA5 0x0515 + +#define RTL8367D_REG_TABLE_WRITE_DATA6 0x0516 + +#define RTL8367D_REG_TABLE_WRITE_DATA7 0x0517 + +#define RTL8367D_REG_TABLE_WRITE_DATA8 0x0518 + +#define RTL8367D_REG_TABLE_WRITE_DATA9 0x0519 +#define RTL8367D_TABLE_WRITE_DATA9_OFFSET 0 +#define RTL8367D_TABLE_WRITE_DATA9_MASK 0x1 + +#define RTL8367D_REG_TABLE_READ_DATA0 0x0520 + +#define RTL8367D_REG_TABLE_READ_DATA1 0x0521 + +#define RTL8367D_REG_TABLE_READ_DATA2 0x0522 + +#define RTL8367D_REG_TABLE_READ_DATA3 0x0523 + +#define RTL8367D_REG_TABLE_READ_DATA4 0x0524 + +#define RTL8367D_REG_TABLE_READ_DATA5 0x0525 + +#define RTL8367D_REG_TABLE_READ_DATA6 0x0526 + +#define RTL8367D_REG_TABLE_READ_DATA7 0x0527 + +#define RTL8367D_REG_TABLE_READ_DATA8 0x0528 + +#define RTL8367D_REG_TABLE_READ_DATA9 0x0529 +#define RTL8367D_TABLE_READ_DATA9_OFFSET 0 +#define RTL8367D_TABLE_READ_DATA9_MASK 0x1 + +/* (16'h0600)acl_reg */ + +#define RTL8367D_REG_ACL_RULE_TEMPLATE0_CTRL0 0x0600 +#define RTL8367D_ACL_RULE_TEMPLATE0_CTRL0_FIELD1_OFFSET 8 +#define RTL8367D_ACL_RULE_TEMPLATE0_CTRL0_FIELD1_MASK 0x7F00 +#define RTL8367D_ACL_RULE_TEMPLATE0_CTRL0_FIELD0_OFFSET 0 +#define RTL8367D_ACL_RULE_TEMPLATE0_CTRL0_FIELD0_MASK 0x7F + +#define RTL8367D_REG_ACL_RULE_TEMPLATE0_CTRL1 0x0601 +#define RTL8367D_ACL_RULE_TEMPLATE0_CTRL1_FIELD3_OFFSET 8 +#define RTL8367D_ACL_RULE_TEMPLATE0_CTRL1_FIELD3_MASK 0x7F00 +#define RTL8367D_ACL_RULE_TEMPLATE0_CTRL1_FIELD2_OFFSET 0 +#define RTL8367D_ACL_RULE_TEMPLATE0_CTRL1_FIELD2_MASK 0x7F + +#define RTL8367D_REG_ACL_RULE_TEMPLATE0_CTRL2 0x0602 +#define RTL8367D_ACL_RULE_TEMPLATE0_CTRL2_FIELD5_OFFSET 8 +#define RTL8367D_ACL_RULE_TEMPLATE0_CTRL2_FIELD5_MASK 0x7F00 +#define RTL8367D_ACL_RULE_TEMPLATE0_CTRL2_FIELD4_OFFSET 0 +#define RTL8367D_ACL_RULE_TEMPLATE0_CTRL2_FIELD4_MASK 0x7F + +#define RTL8367D_REG_ACL_RULE_TEMPLATE0_CTRL3 0x0603 +#define RTL8367D_ACL_RULE_TEMPLATE0_CTRL3_FIELD7_OFFSET 8 +#define RTL8367D_ACL_RULE_TEMPLATE0_CTRL3_FIELD7_MASK 0x7F00 +#define RTL8367D_ACL_RULE_TEMPLATE0_CTRL3_FIELD6_OFFSET 0 +#define RTL8367D_ACL_RULE_TEMPLATE0_CTRL3_FIELD6_MASK 0x7F + +#define RTL8367D_REG_ACL_RULE_TEMPLATE1_CTRL0 0x0604 +#define RTL8367D_ACL_RULE_TEMPLATE1_CTRL0_FIELD1_OFFSET 8 +#define RTL8367D_ACL_RULE_TEMPLATE1_CTRL0_FIELD1_MASK 0x7F00 +#define RTL8367D_ACL_RULE_TEMPLATE1_CTRL0_FIELD0_OFFSET 0 +#define RTL8367D_ACL_RULE_TEMPLATE1_CTRL0_FIELD0_MASK 0x7F + +#define RTL8367D_REG_ACL_RULE_TEMPLATE1_CTRL1 0x0605 +#define RTL8367D_ACL_RULE_TEMPLATE1_CTRL1_FIELD3_OFFSET 8 +#define RTL8367D_ACL_RULE_TEMPLATE1_CTRL1_FIELD3_MASK 0x7F00 +#define RTL8367D_ACL_RULE_TEMPLATE1_CTRL1_FIELD2_OFFSET 0 +#define RTL8367D_ACL_RULE_TEMPLATE1_CTRL1_FIELD2_MASK 0x7F + +#define RTL8367D_REG_ACL_RULE_TEMPLATE1_CTRL2 0x0606 +#define RTL8367D_ACL_RULE_TEMPLATE1_CTRL2_FIELD5_OFFSET 8 +#define RTL8367D_ACL_RULE_TEMPLATE1_CTRL2_FIELD5_MASK 0x7F00 +#define RTL8367D_ACL_RULE_TEMPLATE1_CTRL2_FIELD4_OFFSET 0 +#define RTL8367D_ACL_RULE_TEMPLATE1_CTRL2_FIELD4_MASK 0x7F + +#define RTL8367D_REG_ACL_RULE_TEMPLATE1_CTRL3 0x0607 +#define RTL8367D_ACL_RULE_TEMPLATE1_CTRL3_FIELD7_OFFSET 8 +#define RTL8367D_ACL_RULE_TEMPLATE1_CTRL3_FIELD7_MASK 0x7F00 +#define RTL8367D_ACL_RULE_TEMPLATE1_CTRL3_FIELD6_OFFSET 0 +#define RTL8367D_ACL_RULE_TEMPLATE1_CTRL3_FIELD6_MASK 0x7F + +#define RTL8367D_REG_ACL_RULE_TEMPLATE2_CTRL0 0x0608 +#define RTL8367D_ACL_RULE_TEMPLATE2_CTRL0_FIELD1_OFFSET 8 +#define RTL8367D_ACL_RULE_TEMPLATE2_CTRL0_FIELD1_MASK 0x7F00 +#define RTL8367D_ACL_RULE_TEMPLATE2_CTRL0_FIELD0_OFFSET 0 +#define RTL8367D_ACL_RULE_TEMPLATE2_CTRL0_FIELD0_MASK 0x7F + +#define RTL8367D_REG_ACL_RULE_TEMPLATE2_CTRL1 0x0609 +#define RTL8367D_ACL_RULE_TEMPLATE2_CTRL1_FIELD3_OFFSET 8 +#define RTL8367D_ACL_RULE_TEMPLATE2_CTRL1_FIELD3_MASK 0x7F00 +#define RTL8367D_ACL_RULE_TEMPLATE2_CTRL1_FIELD2_OFFSET 0 +#define RTL8367D_ACL_RULE_TEMPLATE2_CTRL1_FIELD2_MASK 0x7F + +#define RTL8367D_REG_ACL_RULE_TEMPLATE2_CTRL2 0x060a +#define RTL8367D_ACL_RULE_TEMPLATE2_CTRL2_FIELD5_OFFSET 8 +#define RTL8367D_ACL_RULE_TEMPLATE2_CTRL2_FIELD5_MASK 0x7F00 +#define RTL8367D_ACL_RULE_TEMPLATE2_CTRL2_FIELD4_OFFSET 0 +#define RTL8367D_ACL_RULE_TEMPLATE2_CTRL2_FIELD4_MASK 0x7F + +#define RTL8367D_REG_ACL_RULE_TEMPLATE2_CTRL3 0x060b +#define RTL8367D_ACL_RULE_TEMPLATE2_CTRL3_FIELD7_OFFSET 8 +#define RTL8367D_ACL_RULE_TEMPLATE2_CTRL3_FIELD7_MASK 0x7F00 +#define RTL8367D_ACL_RULE_TEMPLATE2_CTRL3_FIELD6_OFFSET 0 +#define RTL8367D_ACL_RULE_TEMPLATE2_CTRL3_FIELD6_MASK 0x7F + +#define RTL8367D_REG_ACL_RULE_TEMPLATE3_CTRL0 0x060c +#define RTL8367D_ACL_RULE_TEMPLATE3_CTRL0_FIELD1_OFFSET 8 +#define RTL8367D_ACL_RULE_TEMPLATE3_CTRL0_FIELD1_MASK 0x7F00 +#define RTL8367D_ACL_RULE_TEMPLATE3_CTRL0_FIELD0_OFFSET 0 +#define RTL8367D_ACL_RULE_TEMPLATE3_CTRL0_FIELD0_MASK 0x7F + +#define RTL8367D_REG_ACL_RULE_TEMPLATE3_CTRL1 0x060d +#define RTL8367D_ACL_RULE_TEMPLATE3_CTRL1_FIELD3_OFFSET 8 +#define RTL8367D_ACL_RULE_TEMPLATE3_CTRL1_FIELD3_MASK 0x7F00 +#define RTL8367D_ACL_RULE_TEMPLATE3_CTRL1_FIELD2_OFFSET 0 +#define RTL8367D_ACL_RULE_TEMPLATE3_CTRL1_FIELD2_MASK 0x7F + +#define RTL8367D_REG_ACL_RULE_TEMPLATE3_CTRL2 0x060e +#define RTL8367D_ACL_RULE_TEMPLATE3_CTRL2_FIELD5_OFFSET 8 +#define RTL8367D_ACL_RULE_TEMPLATE3_CTRL2_FIELD5_MASK 0x7F00 +#define RTL8367D_ACL_RULE_TEMPLATE3_CTRL2_FIELD4_OFFSET 0 +#define RTL8367D_ACL_RULE_TEMPLATE3_CTRL2_FIELD4_MASK 0x7F + +#define RTL8367D_REG_ACL_RULE_TEMPLATE3_CTRL3 0x060f +#define RTL8367D_ACL_RULE_TEMPLATE3_CTRL3_FIELD7_OFFSET 8 +#define RTL8367D_ACL_RULE_TEMPLATE3_CTRL3_FIELD7_MASK 0x7F00 +#define RTL8367D_ACL_RULE_TEMPLATE3_CTRL3_FIELD6_OFFSET 0 +#define RTL8367D_ACL_RULE_TEMPLATE3_CTRL3_FIELD6_MASK 0x7F + +#define RTL8367D_REG_ACL_RULE_TEMPLATE4_CTRL0 0x0610 +#define RTL8367D_ACL_RULE_TEMPLATE4_CTRL0_FIELD1_OFFSET 8 +#define RTL8367D_ACL_RULE_TEMPLATE4_CTRL0_FIELD1_MASK 0x7F00 +#define RTL8367D_ACL_RULE_TEMPLATE4_CTRL0_FIELD0_OFFSET 0 +#define RTL8367D_ACL_RULE_TEMPLATE4_CTRL0_FIELD0_MASK 0x7F + +#define RTL8367D_REG_ACL_RULE_TEMPLATE4_CTRL1 0x0611 +#define RTL8367D_ACL_RULE_TEMPLATE4_CTRL1_FIELD3_OFFSET 8 +#define RTL8367D_ACL_RULE_TEMPLATE4_CTRL1_FIELD3_MASK 0x7F00 +#define RTL8367D_ACL_RULE_TEMPLATE4_CTRL1_FIELD2_OFFSET 0 +#define RTL8367D_ACL_RULE_TEMPLATE4_CTRL1_FIELD2_MASK 0x7F + +#define RTL8367D_REG_ACL_RULE_TEMPLATE4_CTRL2 0x0612 +#define RTL8367D_ACL_RULE_TEMPLATE4_CTRL2_FIELD5_OFFSET 8 +#define RTL8367D_ACL_RULE_TEMPLATE4_CTRL2_FIELD5_MASK 0x7F00 +#define RTL8367D_ACL_RULE_TEMPLATE4_CTRL2_FIELD4_OFFSET 0 +#define RTL8367D_ACL_RULE_TEMPLATE4_CTRL2_FIELD4_MASK 0x7F + +#define RTL8367D_REG_ACL_RULE_TEMPLATE4_CTRL3 0x0613 +#define RTL8367D_ACL_RULE_TEMPLATE4_CTRL3_FIELD7_OFFSET 8 +#define RTL8367D_ACL_RULE_TEMPLATE4_CTRL3_FIELD7_MASK 0x7F00 +#define RTL8367D_ACL_RULE_TEMPLATE4_CTRL3_FIELD6_OFFSET 0 +#define RTL8367D_ACL_RULE_TEMPLATE4_CTRL3_FIELD6_MASK 0x7F + +#define RTL8367D_REG_ACL_ACTION_CTRL0 0x0614 +#define RTL8367D_OP1_NOT_OFFSET 14 +#define RTL8367D_OP1_NOT_MASK 0x4000 +#define RTL8367D_ACT1_GPIO_OFFSET 13 +#define RTL8367D_ACT1_GPIO_MASK 0x2000 +#define RTL8367D_ACT1_FORWARD_OFFSET 12 +#define RTL8367D_ACT1_FORWARD_MASK 0x1000 +#define RTL8367D_ACT1_POLICING_OFFSET 11 +#define RTL8367D_ACT1_POLICING_MASK 0x800 +#define RTL8367D_ACT1_PRIORITY_OFFSET 10 +#define RTL8367D_ACT1_PRIORITY_MASK 0x400 +#define RTL8367D_ACT1_SVID_OFFSET 9 +#define RTL8367D_ACT1_SVID_MASK 0x200 +#define RTL8367D_ACT1_CVID_OFFSET 8 +#define RTL8367D_ACT1_CVID_MASK 0x100 +#define RTL8367D_OP0_NOT_OFFSET 6 +#define RTL8367D_OP0_NOT_MASK 0x40 +#define RTL8367D_ACT0_GPIO_OFFSET 5 +#define RTL8367D_ACT0_GPIO_MASK 0x20 +#define RTL8367D_ACT0_FORWARD_OFFSET 4 +#define RTL8367D_ACT0_FORWARD_MASK 0x10 +#define RTL8367D_ACT0_POLICING_OFFSET 3 +#define RTL8367D_ACT0_POLICING_MASK 0x8 +#define RTL8367D_ACT0_PRIORITY_OFFSET 2 +#define RTL8367D_ACT0_PRIORITY_MASK 0x4 +#define RTL8367D_ACT0_SVID_OFFSET 1 +#define RTL8367D_ACT0_SVID_MASK 0x2 +#define RTL8367D_ACT0_CVID_OFFSET 0 +#define RTL8367D_ACT0_CVID_MASK 0x1 + +#define RTL8367D_REG_ACL_ACTION_CTRL1 0x0615 +#define RTL8367D_OP3_NOT_OFFSET 14 +#define RTL8367D_OP3_NOT_MASK 0x4000 +#define RTL8367D_ACT3_GPIO_OFFSET 13 +#define RTL8367D_ACT3_GPIO_MASK 0x2000 +#define RTL8367D_ACT3_FORWARD_OFFSET 12 +#define RTL8367D_ACT3_FORWARD_MASK 0x1000 +#define RTL8367D_ACT3_POLICING_OFFSET 11 +#define RTL8367D_ACT3_POLICING_MASK 0x800 +#define RTL8367D_ACT3_PRIORITY_OFFSET 10 +#define RTL8367D_ACT3_PRIORITY_MASK 0x400 +#define RTL8367D_ACT3_SVID_OFFSET 9 +#define RTL8367D_ACT3_SVID_MASK 0x200 +#define RTL8367D_ACT3_CVID_OFFSET 8 +#define RTL8367D_ACT3_CVID_MASK 0x100 +#define RTL8367D_OP2_NOT_OFFSET 6 +#define RTL8367D_OP2_NOT_MASK 0x40 +#define RTL8367D_ACT2_GPIO_OFFSET 5 +#define RTL8367D_ACT2_GPIO_MASK 0x20 +#define RTL8367D_ACT2_FORWARD_OFFSET 4 +#define RTL8367D_ACT2_FORWARD_MASK 0x10 +#define RTL8367D_ACT2_POLICING_OFFSET 3 +#define RTL8367D_ACT2_POLICING_MASK 0x8 +#define RTL8367D_ACT2_PRIORITY_OFFSET 2 +#define RTL8367D_ACT2_PRIORITY_MASK 0x4 +#define RTL8367D_ACT2_SVID_OFFSET 1 +#define RTL8367D_ACT2_SVID_MASK 0x2 +#define RTL8367D_ACT2_CVID_OFFSET 0 +#define RTL8367D_ACT2_CVID_MASK 0x1 + +#define RTL8367D_REG_ACL_ACTION_CTRL2 0x0616 +#define RTL8367D_OP5_NOT_OFFSET 14 +#define RTL8367D_OP5_NOT_MASK 0x4000 +#define RTL8367D_ACT5_GPIO_OFFSET 13 +#define RTL8367D_ACT5_GPIO_MASK 0x2000 +#define RTL8367D_ACT5_FORWARD_OFFSET 12 +#define RTL8367D_ACT5_FORWARD_MASK 0x1000 +#define RTL8367D_ACT5_POLICING_OFFSET 11 +#define RTL8367D_ACT5_POLICING_MASK 0x800 +#define RTL8367D_ACT5_PRIORITY_OFFSET 10 +#define RTL8367D_ACT5_PRIORITY_MASK 0x400 +#define RTL8367D_ACT5_SVID_OFFSET 9 +#define RTL8367D_ACT5_SVID_MASK 0x200 +#define RTL8367D_ACT5_CVID_OFFSET 8 +#define RTL8367D_ACT5_CVID_MASK 0x100 +#define RTL8367D_OP4_NOT_OFFSET 6 +#define RTL8367D_OP4_NOT_MASK 0x40 +#define RTL8367D_ACT4_GPIO_OFFSET 5 +#define RTL8367D_ACT4_GPIO_MASK 0x20 +#define RTL8367D_ACT4_FORWARD_OFFSET 4 +#define RTL8367D_ACT4_FORWARD_MASK 0x10 +#define RTL8367D_ACT4_POLICING_OFFSET 3 +#define RTL8367D_ACT4_POLICING_MASK 0x8 +#define RTL8367D_ACT4_PRIORITY_OFFSET 2 +#define RTL8367D_ACT4_PRIORITY_MASK 0x4 +#define RTL8367D_ACT4_SVID_OFFSET 1 +#define RTL8367D_ACT4_SVID_MASK 0x2 +#define RTL8367D_ACT4_CVID_OFFSET 0 +#define RTL8367D_ACT4_CVID_MASK 0x1 + +#define RTL8367D_REG_ACL_ACTION_CTRL3 0x0617 +#define RTL8367D_OP7_NOT_OFFSET 14 +#define RTL8367D_OP7_NOT_MASK 0x4000 +#define RTL8367D_ACT7_GPIO_OFFSET 13 +#define RTL8367D_ACT7_GPIO_MASK 0x2000 +#define RTL8367D_ACT7_FORWARD_OFFSET 12 +#define RTL8367D_ACT7_FORWARD_MASK 0x1000 +#define RTL8367D_ACT7_POLICING_OFFSET 11 +#define RTL8367D_ACT7_POLICING_MASK 0x800 +#define RTL8367D_ACT7_PRIORITY_OFFSET 10 +#define RTL8367D_ACT7_PRIORITY_MASK 0x400 +#define RTL8367D_ACT7_SVID_OFFSET 9 +#define RTL8367D_ACT7_SVID_MASK 0x200 +#define RTL8367D_ACT7_CVID_OFFSET 8 +#define RTL8367D_ACT7_CVID_MASK 0x100 +#define RTL8367D_OP6_NOT_OFFSET 6 +#define RTL8367D_OP6_NOT_MASK 0x40 +#define RTL8367D_ACT6_GPIO_OFFSET 5 +#define RTL8367D_ACT6_GPIO_MASK 0x20 +#define RTL8367D_ACT6_FORWARD_OFFSET 4 +#define RTL8367D_ACT6_FORWARD_MASK 0x10 +#define RTL8367D_ACT6_POLICING_OFFSET 3 +#define RTL8367D_ACT6_POLICING_MASK 0x8 +#define RTL8367D_ACT6_PRIORITY_OFFSET 2 +#define RTL8367D_ACT6_PRIORITY_MASK 0x4 +#define RTL8367D_ACT6_SVID_OFFSET 1 +#define RTL8367D_ACT6_SVID_MASK 0x2 +#define RTL8367D_ACT6_CVID_OFFSET 0 +#define RTL8367D_ACT6_CVID_MASK 0x1 + +#define RTL8367D_REG_ACL_ACTION_CTRL4 0x0618 +#define RTL8367D_OP9_NOT_OFFSET 14 +#define RTL8367D_OP9_NOT_MASK 0x4000 +#define RTL8367D_ACT9_GPIO_OFFSET 13 +#define RTL8367D_ACT9_GPIO_MASK 0x2000 +#define RTL8367D_ACT9_FORWARD_OFFSET 12 +#define RTL8367D_ACT9_FORWARD_MASK 0x1000 +#define RTL8367D_ACT9_POLICING_OFFSET 11 +#define RTL8367D_ACT9_POLICING_MASK 0x800 +#define RTL8367D_ACT9_PRIORITY_OFFSET 10 +#define RTL8367D_ACT9_PRIORITY_MASK 0x400 +#define RTL8367D_ACT9_SVID_OFFSET 9 +#define RTL8367D_ACT9_SVID_MASK 0x200 +#define RTL8367D_ACT9_CVID_OFFSET 8 +#define RTL8367D_ACT9_CVID_MASK 0x100 +#define RTL8367D_OP8_NOT_OFFSET 6 +#define RTL8367D_OP8_NOT_MASK 0x40 +#define RTL8367D_ACT8_GPIO_OFFSET 5 +#define RTL8367D_ACT8_GPIO_MASK 0x20 +#define RTL8367D_ACT8_FORWARD_OFFSET 4 +#define RTL8367D_ACT8_FORWARD_MASK 0x10 +#define RTL8367D_ACT8_POLICING_OFFSET 3 +#define RTL8367D_ACT8_POLICING_MASK 0x8 +#define RTL8367D_ACT8_PRIORITY_OFFSET 2 +#define RTL8367D_ACT8_PRIORITY_MASK 0x4 +#define RTL8367D_ACT8_SVID_OFFSET 1 +#define RTL8367D_ACT8_SVID_MASK 0x2 +#define RTL8367D_ACT8_CVID_OFFSET 0 +#define RTL8367D_ACT8_CVID_MASK 0x1 + +#define RTL8367D_REG_ACL_ACTION_CTRL5 0x0619 +#define RTL8367D_OP11_NOT_OFFSET 14 +#define RTL8367D_OP11_NOT_MASK 0x4000 +#define RTL8367D_ACT11_GPIO_OFFSET 13 +#define RTL8367D_ACT11_GPIO_MASK 0x2000 +#define RTL8367D_ACT11_FORWARD_OFFSET 12 +#define RTL8367D_ACT11_FORWARD_MASK 0x1000 +#define RTL8367D_ACT11_POLICING_OFFSET 11 +#define RTL8367D_ACT11_POLICING_MASK 0x800 +#define RTL8367D_ACT11_PRIORITY_OFFSET 10 +#define RTL8367D_ACT11_PRIORITY_MASK 0x400 +#define RTL8367D_ACT11_SVID_OFFSET 9 +#define RTL8367D_ACT11_SVID_MASK 0x200 +#define RTL8367D_ACT11_CVID_OFFSET 8 +#define RTL8367D_ACT11_CVID_MASK 0x100 +#define RTL8367D_OP10_NOT_OFFSET 6 +#define RTL8367D_OP10_NOT_MASK 0x40 +#define RTL8367D_ACT10_GPIO_OFFSET 5 +#define RTL8367D_ACT10_GPIO_MASK 0x20 +#define RTL8367D_ACT10_FORWARD_OFFSET 4 +#define RTL8367D_ACT10_FORWARD_MASK 0x10 +#define RTL8367D_ACT10_POLICING_OFFSET 3 +#define RTL8367D_ACT10_POLICING_MASK 0x8 +#define RTL8367D_ACT10_PRIORITY_OFFSET 2 +#define RTL8367D_ACT10_PRIORITY_MASK 0x4 +#define RTL8367D_ACT10_SVID_OFFSET 1 +#define RTL8367D_ACT10_SVID_MASK 0x2 +#define RTL8367D_ACT10_CVID_OFFSET 0 +#define RTL8367D_ACT10_CVID_MASK 0x1 + +#define RTL8367D_REG_ACL_ACTION_CTRL6 0x061a +#define RTL8367D_OP13_NOT_OFFSET 14 +#define RTL8367D_OP13_NOT_MASK 0x4000 +#define RTL8367D_ACT13_GPIO_OFFSET 13 +#define RTL8367D_ACT13_GPIO_MASK 0x2000 +#define RTL8367D_ACT13_FORWARD_OFFSET 12 +#define RTL8367D_ACT13_FORWARD_MASK 0x1000 +#define RTL8367D_ACT13_POLICING_OFFSET 11 +#define RTL8367D_ACT13_POLICING_MASK 0x800 +#define RTL8367D_ACT13_PRIORITY_OFFSET 10 +#define RTL8367D_ACT13_PRIORITY_MASK 0x400 +#define RTL8367D_ACT13_SVID_OFFSET 9 +#define RTL8367D_ACT13_SVID_MASK 0x200 +#define RTL8367D_ACT13_CVID_OFFSET 8 +#define RTL8367D_ACT13_CVID_MASK 0x100 +#define RTL8367D_OP12_NOT_OFFSET 6 +#define RTL8367D_OP12_NOT_MASK 0x40 +#define RTL8367D_ACT12_GPIO_OFFSET 5 +#define RTL8367D_ACT12_GPIO_MASK 0x20 +#define RTL8367D_ACT12_FORWARD_OFFSET 4 +#define RTL8367D_ACT12_FORWARD_MASK 0x10 +#define RTL8367D_ACT12_POLICING_OFFSET 3 +#define RTL8367D_ACT12_POLICING_MASK 0x8 +#define RTL8367D_ACT12_PRIORITY_OFFSET 2 +#define RTL8367D_ACT12_PRIORITY_MASK 0x4 +#define RTL8367D_ACT12_SVID_OFFSET 1 +#define RTL8367D_ACT12_SVID_MASK 0x2 +#define RTL8367D_ACT12_CVID_OFFSET 0 +#define RTL8367D_ACT12_CVID_MASK 0x1 + +#define RTL8367D_REG_ACL_ACTION_CTRL7 0x061b +#define RTL8367D_OP15_NOT_OFFSET 14 +#define RTL8367D_OP15_NOT_MASK 0x4000 +#define RTL8367D_ACT15_GPIO_OFFSET 13 +#define RTL8367D_ACT15_GPIO_MASK 0x2000 +#define RTL8367D_ACT15_FORWARD_OFFSET 12 +#define RTL8367D_ACT15_FORWARD_MASK 0x1000 +#define RTL8367D_ACT15_POLICING_OFFSET 11 +#define RTL8367D_ACT15_POLICING_MASK 0x800 +#define RTL8367D_ACT15_PRIORITY_OFFSET 10 +#define RTL8367D_ACT15_PRIORITY_MASK 0x400 +#define RTL8367D_ACT15_SVID_OFFSET 9 +#define RTL8367D_ACT15_SVID_MASK 0x200 +#define RTL8367D_ACT15_CVID_OFFSET 8 +#define RTL8367D_ACT15_CVID_MASK 0x100 +#define RTL8367D_OP14_NOT_OFFSET 6 +#define RTL8367D_OP14_NOT_MASK 0x40 +#define RTL8367D_ACT14_GPIO_OFFSET 5 +#define RTL8367D_ACT14_GPIO_MASK 0x20 +#define RTL8367D_ACT14_FORWARD_OFFSET 4 +#define RTL8367D_ACT14_FORWARD_MASK 0x10 +#define RTL8367D_ACT14_POLICING_OFFSET 3 +#define RTL8367D_ACT14_POLICING_MASK 0x8 +#define RTL8367D_ACT14_PRIORITY_OFFSET 2 +#define RTL8367D_ACT14_PRIORITY_MASK 0x4 +#define RTL8367D_ACT14_SVID_OFFSET 1 +#define RTL8367D_ACT14_SVID_MASK 0x2 +#define RTL8367D_ACT14_CVID_OFFSET 0 +#define RTL8367D_ACT14_CVID_MASK 0x1 + +#define RTL8367D_REG_ACL_ACTION_CTRL8 0x061c +#define RTL8367D_OP17_NOT_OFFSET 14 +#define RTL8367D_OP17_NOT_MASK 0x4000 +#define RTL8367D_ACT17_GPIO_OFFSET 13 +#define RTL8367D_ACT17_GPIO_MASK 0x2000 +#define RTL8367D_ACT17_FORWARD_OFFSET 12 +#define RTL8367D_ACT17_FORWARD_MASK 0x1000 +#define RTL8367D_ACT17_POLICING_OFFSET 11 +#define RTL8367D_ACT17_POLICING_MASK 0x800 +#define RTL8367D_ACT17_PRIORITY_OFFSET 10 +#define RTL8367D_ACT17_PRIORITY_MASK 0x400 +#define RTL8367D_ACT17_SVID_OFFSET 9 +#define RTL8367D_ACT17_SVID_MASK 0x200 +#define RTL8367D_ACT17_CVID_OFFSET 8 +#define RTL8367D_ACT17_CVID_MASK 0x100 +#define RTL8367D_OP16_NOT_OFFSET 6 +#define RTL8367D_OP16_NOT_MASK 0x40 +#define RTL8367D_ACT16_GPIO_OFFSET 5 +#define RTL8367D_ACT16_GPIO_MASK 0x20 +#define RTL8367D_ACT16_FORWARD_OFFSET 4 +#define RTL8367D_ACT16_FORWARD_MASK 0x10 +#define RTL8367D_ACT16_POLICING_OFFSET 3 +#define RTL8367D_ACT16_POLICING_MASK 0x8 +#define RTL8367D_ACT16_PRIORITY_OFFSET 2 +#define RTL8367D_ACT16_PRIORITY_MASK 0x4 +#define RTL8367D_ACT16_SVID_OFFSET 1 +#define RTL8367D_ACT16_SVID_MASK 0x2 +#define RTL8367D_ACT16_CVID_OFFSET 0 +#define RTL8367D_ACT16_CVID_MASK 0x1 + +#define RTL8367D_REG_ACL_ACTION_CTRL9 0x061d +#define RTL8367D_OP19_NOT_OFFSET 14 +#define RTL8367D_OP19_NOT_MASK 0x4000 +#define RTL8367D_ACT19_GPIO_OFFSET 13 +#define RTL8367D_ACT19_GPIO_MASK 0x2000 +#define RTL8367D_ACT19_FORWARD_OFFSET 12 +#define RTL8367D_ACT19_FORWARD_MASK 0x1000 +#define RTL8367D_ACT19_POLICING_OFFSET 11 +#define RTL8367D_ACT19_POLICING_MASK 0x800 +#define RTL8367D_ACT19_PRIORITY_OFFSET 10 +#define RTL8367D_ACT19_PRIORITY_MASK 0x400 +#define RTL8367D_ACT19_SVID_OFFSET 9 +#define RTL8367D_ACT19_SVID_MASK 0x200 +#define RTL8367D_ACT19_CVID_OFFSET 8 +#define RTL8367D_ACT19_CVID_MASK 0x100 +#define RTL8367D_OP18_NOT_OFFSET 6 +#define RTL8367D_OP18_NOT_MASK 0x40 +#define RTL8367D_ACT18_GPIO_OFFSET 5 +#define RTL8367D_ACT18_GPIO_MASK 0x20 +#define RTL8367D_ACT18_FORWARD_OFFSET 4 +#define RTL8367D_ACT18_FORWARD_MASK 0x10 +#define RTL8367D_ACT18_POLICING_OFFSET 3 +#define RTL8367D_ACT18_POLICING_MASK 0x8 +#define RTL8367D_ACT18_PRIORITY_OFFSET 2 +#define RTL8367D_ACT18_PRIORITY_MASK 0x4 +#define RTL8367D_ACT18_SVID_OFFSET 1 +#define RTL8367D_ACT18_SVID_MASK 0x2 +#define RTL8367D_ACT18_CVID_OFFSET 0 +#define RTL8367D_ACT18_CVID_MASK 0x1 + +#define RTL8367D_REG_ACL_ACTION_CTRL10 0x061e +#define RTL8367D_OP21_NOT_OFFSET 14 +#define RTL8367D_OP21_NOT_MASK 0x4000 +#define RTL8367D_ACT21_GPIO_OFFSET 13 +#define RTL8367D_ACT21_GPIO_MASK 0x2000 +#define RTL8367D_ACT21_FORWARD_OFFSET 12 +#define RTL8367D_ACT21_FORWARD_MASK 0x1000 +#define RTL8367D_ACT21_POLICING_OFFSET 11 +#define RTL8367D_ACT21_POLICING_MASK 0x800 +#define RTL8367D_ACT21_PRIORITY_OFFSET 10 +#define RTL8367D_ACT21_PRIORITY_MASK 0x400 +#define RTL8367D_ACT21_SVID_OFFSET 9 +#define RTL8367D_ACT21_SVID_MASK 0x200 +#define RTL8367D_ACT21_CVID_OFFSET 8 +#define RTL8367D_ACT21_CVID_MASK 0x100 +#define RTL8367D_OP20_NOT_OFFSET 6 +#define RTL8367D_OP20_NOT_MASK 0x40 +#define RTL8367D_ACT20_GPIO_OFFSET 5 +#define RTL8367D_ACT20_GPIO_MASK 0x20 +#define RTL8367D_ACT20_FORWARD_OFFSET 4 +#define RTL8367D_ACT20_FORWARD_MASK 0x10 +#define RTL8367D_ACT20_POLICING_OFFSET 3 +#define RTL8367D_ACT20_POLICING_MASK 0x8 +#define RTL8367D_ACT20_PRIORITY_OFFSET 2 +#define RTL8367D_ACT20_PRIORITY_MASK 0x4 +#define RTL8367D_ACT20_SVID_OFFSET 1 +#define RTL8367D_ACT20_SVID_MASK 0x2 +#define RTL8367D_ACT20_CVID_OFFSET 0 +#define RTL8367D_ACT20_CVID_MASK 0x1 + +#define RTL8367D_REG_ACL_ACTION_CTRL11 0x061f +#define RTL8367D_OP23_NOT_OFFSET 14 +#define RTL8367D_OP23_NOT_MASK 0x4000 +#define RTL8367D_ACT23_GPIO_OFFSET 13 +#define RTL8367D_ACT23_GPIO_MASK 0x2000 +#define RTL8367D_ACT23_FORWARD_OFFSET 12 +#define RTL8367D_ACT23_FORWARD_MASK 0x1000 +#define RTL8367D_ACT23_POLICING_OFFSET 11 +#define RTL8367D_ACT23_POLICING_MASK 0x800 +#define RTL8367D_ACT23_PRIORITY_OFFSET 10 +#define RTL8367D_ACT23_PRIORITY_MASK 0x400 +#define RTL8367D_ACT23_SVID_OFFSET 9 +#define RTL8367D_ACT23_SVID_MASK 0x200 +#define RTL8367D_ACT23_CVID_OFFSET 8 +#define RTL8367D_ACT23_CVID_MASK 0x100 +#define RTL8367D_OP22_NOT_OFFSET 6 +#define RTL8367D_OP22_NOT_MASK 0x40 +#define RTL8367D_ACT22_GPIO_OFFSET 5 +#define RTL8367D_ACT22_GPIO_MASK 0x20 +#define RTL8367D_ACT22_FORWARD_OFFSET 4 +#define RTL8367D_ACT22_FORWARD_MASK 0x10 +#define RTL8367D_ACT22_POLICING_OFFSET 3 +#define RTL8367D_ACT22_POLICING_MASK 0x8 +#define RTL8367D_ACT22_PRIORITY_OFFSET 2 +#define RTL8367D_ACT22_PRIORITY_MASK 0x4 +#define RTL8367D_ACT22_SVID_OFFSET 1 +#define RTL8367D_ACT22_SVID_MASK 0x2 +#define RTL8367D_ACT22_CVID_OFFSET 0 +#define RTL8367D_ACT22_CVID_MASK 0x1 + +#define RTL8367D_REG_ACL_ACTION_CTRL12 0x0620 +#define RTL8367D_OP25_NOT_OFFSET 14 +#define RTL8367D_OP25_NOT_MASK 0x4000 +#define RTL8367D_ACT25_GPIO_OFFSET 13 +#define RTL8367D_ACT25_GPIO_MASK 0x2000 +#define RTL8367D_ACT25_FORWARD_OFFSET 12 +#define RTL8367D_ACT25_FORWARD_MASK 0x1000 +#define RTL8367D_ACT25_POLICING_OFFSET 11 +#define RTL8367D_ACT25_POLICING_MASK 0x800 +#define RTL8367D_ACT25_PRIORITY_OFFSET 10 +#define RTL8367D_ACT25_PRIORITY_MASK 0x400 +#define RTL8367D_ACT25_SVID_OFFSET 9 +#define RTL8367D_ACT25_SVID_MASK 0x200 +#define RTL8367D_ACT25_CVID_OFFSET 8 +#define RTL8367D_ACT25_CVID_MASK 0x100 +#define RTL8367D_OP24_NOT_OFFSET 6 +#define RTL8367D_OP24_NOT_MASK 0x40 +#define RTL8367D_ACT24_GPIO_OFFSET 5 +#define RTL8367D_ACT24_GPIO_MASK 0x20 +#define RTL8367D_ACT24_FORWARD_OFFSET 4 +#define RTL8367D_ACT24_FORWARD_MASK 0x10 +#define RTL8367D_ACT24_POLICING_OFFSET 3 +#define RTL8367D_ACT24_POLICING_MASK 0x8 +#define RTL8367D_ACT24_PRIORITY_OFFSET 2 +#define RTL8367D_ACT24_PRIORITY_MASK 0x4 +#define RTL8367D_ACT24_SVID_OFFSET 1 +#define RTL8367D_ACT24_SVID_MASK 0x2 +#define RTL8367D_ACT24_CVID_OFFSET 0 +#define RTL8367D_ACT24_CVID_MASK 0x1 + +#define RTL8367D_REG_ACL_ACTION_CTRL13 0x0621 +#define RTL8367D_OP27_NOT_OFFSET 14 +#define RTL8367D_OP27_NOT_MASK 0x4000 +#define RTL8367D_ACT27_GPIO_OFFSET 13 +#define RTL8367D_ACT27_GPIO_MASK 0x2000 +#define RTL8367D_ACT27_FORWARD_OFFSET 12 +#define RTL8367D_ACT27_FORWARD_MASK 0x1000 +#define RTL8367D_ACT27_POLICING_OFFSET 11 +#define RTL8367D_ACT27_POLICING_MASK 0x800 +#define RTL8367D_ACT27_PRIORITY_OFFSET 10 +#define RTL8367D_ACT27_PRIORITY_MASK 0x400 +#define RTL8367D_ACT27_SVID_OFFSET 9 +#define RTL8367D_ACT27_SVID_MASK 0x200 +#define RTL8367D_ACT27_CVID_OFFSET 8 +#define RTL8367D_ACT27_CVID_MASK 0x100 +#define RTL8367D_OP26_NOT_OFFSET 6 +#define RTL8367D_OP26_NOT_MASK 0x40 +#define RTL8367D_ACT26_GPIO_OFFSET 5 +#define RTL8367D_ACT26_GPIO_MASK 0x20 +#define RTL8367D_ACT26_FORWARD_OFFSET 4 +#define RTL8367D_ACT26_FORWARD_MASK 0x10 +#define RTL8367D_ACT26_POLICING_OFFSET 3 +#define RTL8367D_ACT26_POLICING_MASK 0x8 +#define RTL8367D_ACT26_PRIORITY_OFFSET 2 +#define RTL8367D_ACT26_PRIORITY_MASK 0x4 +#define RTL8367D_ACT26_SVID_OFFSET 1 +#define RTL8367D_ACT26_SVID_MASK 0x2 +#define RTL8367D_ACT26_CVID_OFFSET 0 +#define RTL8367D_ACT26_CVID_MASK 0x1 + +#define RTL8367D_REG_ACL_ACTION_CTRL14 0x0622 +#define RTL8367D_OP29_NOT_OFFSET 14 +#define RTL8367D_OP29_NOT_MASK 0x4000 +#define RTL8367D_ACT29_GPIO_OFFSET 13 +#define RTL8367D_ACT29_GPIO_MASK 0x2000 +#define RTL8367D_ACT29_FORWARD_OFFSET 12 +#define RTL8367D_ACT29_FORWARD_MASK 0x1000 +#define RTL8367D_ACT29_POLICING_OFFSET 11 +#define RTL8367D_ACT29_POLICING_MASK 0x800 +#define RTL8367D_ACT29_PRIORITY_OFFSET 10 +#define RTL8367D_ACT29_PRIORITY_MASK 0x400 +#define RTL8367D_ACT29_SVID_OFFSET 9 +#define RTL8367D_ACT29_SVID_MASK 0x200 +#define RTL8367D_ACT29_CVID_OFFSET 8 +#define RTL8367D_ACT29_CVID_MASK 0x100 +#define RTL8367D_OP28_NOT_OFFSET 6 +#define RTL8367D_OP28_NOT_MASK 0x40 +#define RTL8367D_ACT28_GPIO_OFFSET 5 +#define RTL8367D_ACT28_GPIO_MASK 0x20 +#define RTL8367D_ACT28_FORWARD_OFFSET 4 +#define RTL8367D_ACT28_FORWARD_MASK 0x10 +#define RTL8367D_ACT28_POLICING_OFFSET 3 +#define RTL8367D_ACT28_POLICING_MASK 0x8 +#define RTL8367D_ACT28_PRIORITY_OFFSET 2 +#define RTL8367D_ACT28_PRIORITY_MASK 0x4 +#define RTL8367D_ACT28_SVID_OFFSET 1 +#define RTL8367D_ACT28_SVID_MASK 0x2 +#define RTL8367D_ACT28_CVID_OFFSET 0 +#define RTL8367D_ACT28_CVID_MASK 0x1 + +#define RTL8367D_REG_ACL_ACTION_CTRL15 0x0623 +#define RTL8367D_OP31_NOT_OFFSET 14 +#define RTL8367D_OP31_NOT_MASK 0x4000 +#define RTL8367D_ACT31_GPIO_OFFSET 13 +#define RTL8367D_ACT31_GPIO_MASK 0x2000 +#define RTL8367D_ACT31_FORWARD_OFFSET 12 +#define RTL8367D_ACT31_FORWARD_MASK 0x1000 +#define RTL8367D_ACT31_POLICING_OFFSET 11 +#define RTL8367D_ACT31_POLICING_MASK 0x800 +#define RTL8367D_ACT31_PRIORITY_OFFSET 10 +#define RTL8367D_ACT31_PRIORITY_MASK 0x400 +#define RTL8367D_ACT31_SVID_OFFSET 9 +#define RTL8367D_ACT31_SVID_MASK 0x200 +#define RTL8367D_ACT31_CVID_OFFSET 8 +#define RTL8367D_ACT31_CVID_MASK 0x100 +#define RTL8367D_OP30_NOT_OFFSET 6 +#define RTL8367D_OP30_NOT_MASK 0x40 +#define RTL8367D_ACT30_GPIO_OFFSET 5 +#define RTL8367D_ACT30_GPIO_MASK 0x20 +#define RTL8367D_ACT30_FORWARD_OFFSET 4 +#define RTL8367D_ACT30_FORWARD_MASK 0x10 +#define RTL8367D_ACT30_POLICING_OFFSET 3 +#define RTL8367D_ACT30_POLICING_MASK 0x8 +#define RTL8367D_ACT30_PRIORITY_OFFSET 2 +#define RTL8367D_ACT30_PRIORITY_MASK 0x4 +#define RTL8367D_ACT30_SVID_OFFSET 1 +#define RTL8367D_ACT30_SVID_MASK 0x2 +#define RTL8367D_ACT30_CVID_OFFSET 0 +#define RTL8367D_ACT30_CVID_MASK 0x1 + +#define RTL8367D_REG_ACL_ACTION_CTRL16 0x0624 +#define RTL8367D_OP33_NOT_OFFSET 14 +#define RTL8367D_OP33_NOT_MASK 0x4000 +#define RTL8367D_ACT33_GPIO_OFFSET 13 +#define RTL8367D_ACT33_GPIO_MASK 0x2000 +#define RTL8367D_ACT33_FORWARD_OFFSET 12 +#define RTL8367D_ACT33_FORWARD_MASK 0x1000 +#define RTL8367D_ACT33_POLICING_OFFSET 11 +#define RTL8367D_ACT33_POLICING_MASK 0x800 +#define RTL8367D_ACT33_PRIORITY_OFFSET 10 +#define RTL8367D_ACT33_PRIORITY_MASK 0x400 +#define RTL8367D_ACT33_SVID_OFFSET 9 +#define RTL8367D_ACT33_SVID_MASK 0x200 +#define RTL8367D_ACT33_CVID_OFFSET 8 +#define RTL8367D_ACT33_CVID_MASK 0x100 +#define RTL8367D_OP32_NOT_OFFSET 6 +#define RTL8367D_OP32_NOT_MASK 0x40 +#define RTL8367D_ACT32_GPIO_OFFSET 5 +#define RTL8367D_ACT32_GPIO_MASK 0x20 +#define RTL8367D_ACT32_FORWARD_OFFSET 4 +#define RTL8367D_ACT32_FORWARD_MASK 0x10 +#define RTL8367D_ACT32_POLICING_OFFSET 3 +#define RTL8367D_ACT32_POLICING_MASK 0x8 +#define RTL8367D_ACT32_PRIORITY_OFFSET 2 +#define RTL8367D_ACT32_PRIORITY_MASK 0x4 +#define RTL8367D_ACT32_SVID_OFFSET 1 +#define RTL8367D_ACT32_SVID_MASK 0x2 +#define RTL8367D_ACT32_CVID_OFFSET 0 +#define RTL8367D_ACT32_CVID_MASK 0x1 + +#define RTL8367D_REG_ACL_ACTION_CTRL17 0x0625 +#define RTL8367D_OP35_NOT_OFFSET 14 +#define RTL8367D_OP35_NOT_MASK 0x4000 +#define RTL8367D_ACT35_GPIO_OFFSET 13 +#define RTL8367D_ACT35_GPIO_MASK 0x2000 +#define RTL8367D_ACT35_FORWARD_OFFSET 12 +#define RTL8367D_ACT35_FORWARD_MASK 0x1000 +#define RTL8367D_ACT35_POLICING_OFFSET 11 +#define RTL8367D_ACT35_POLICING_MASK 0x800 +#define RTL8367D_ACT35_PRIORITY_OFFSET 10 +#define RTL8367D_ACT35_PRIORITY_MASK 0x400 +#define RTL8367D_ACT35_SVID_OFFSET 9 +#define RTL8367D_ACT35_SVID_MASK 0x200 +#define RTL8367D_ACT35_CVID_OFFSET 8 +#define RTL8367D_ACT35_CVID_MASK 0x100 +#define RTL8367D_OP34_NOT_OFFSET 6 +#define RTL8367D_OP34_NOT_MASK 0x40 +#define RTL8367D_ACT34_GPIO_OFFSET 5 +#define RTL8367D_ACT34_GPIO_MASK 0x20 +#define RTL8367D_ACT34_FORWARD_OFFSET 4 +#define RTL8367D_ACT34_FORWARD_MASK 0x10 +#define RTL8367D_ACT34_POLICING_OFFSET 3 +#define RTL8367D_ACT34_POLICING_MASK 0x8 +#define RTL8367D_ACT34_PRIORITY_OFFSET 2 +#define RTL8367D_ACT34_PRIORITY_MASK 0x4 +#define RTL8367D_ACT34_SVID_OFFSET 1 +#define RTL8367D_ACT34_SVID_MASK 0x2 +#define RTL8367D_ACT34_CVID_OFFSET 0 +#define RTL8367D_ACT34_CVID_MASK 0x1 + +#define RTL8367D_REG_ACL_ACTION_CTRL18 0x0626 +#define RTL8367D_OP37_NOT_OFFSET 14 +#define RTL8367D_OP37_NOT_MASK 0x4000 +#define RTL8367D_ACT37_GPIO_OFFSET 13 +#define RTL8367D_ACT37_GPIO_MASK 0x2000 +#define RTL8367D_ACT37_FORWARD_OFFSET 12 +#define RTL8367D_ACT37_FORWARD_MASK 0x1000 +#define RTL8367D_ACT37_POLICING_OFFSET 11 +#define RTL8367D_ACT37_POLICING_MASK 0x800 +#define RTL8367D_ACT37_PRIORITY_OFFSET 10 +#define RTL8367D_ACT37_PRIORITY_MASK 0x400 +#define RTL8367D_ACT37_SVID_OFFSET 9 +#define RTL8367D_ACT37_SVID_MASK 0x200 +#define RTL8367D_ACT37_CVID_OFFSET 8 +#define RTL8367D_ACT37_CVID_MASK 0x100 +#define RTL8367D_OP36_NOT_OFFSET 6 +#define RTL8367D_OP36_NOT_MASK 0x40 +#define RTL8367D_ACT36_GPIO_OFFSET 5 +#define RTL8367D_ACT36_GPIO_MASK 0x20 +#define RTL8367D_ACT36_FORWARD_OFFSET 4 +#define RTL8367D_ACT36_FORWARD_MASK 0x10 +#define RTL8367D_ACT36_POLICING_OFFSET 3 +#define RTL8367D_ACT36_POLICING_MASK 0x8 +#define RTL8367D_ACT36_PRIORITY_OFFSET 2 +#define RTL8367D_ACT36_PRIORITY_MASK 0x4 +#define RTL8367D_ACT36_SVID_OFFSET 1 +#define RTL8367D_ACT36_SVID_MASK 0x2 +#define RTL8367D_ACT36_CVID_OFFSET 0 +#define RTL8367D_ACT36_CVID_MASK 0x1 + +#define RTL8367D_REG_ACL_ACTION_CTRL19 0x0627 +#define RTL8367D_OP39_NOT_OFFSET 14 +#define RTL8367D_OP39_NOT_MASK 0x4000 +#define RTL8367D_ACT39_GPIO_OFFSET 13 +#define RTL8367D_ACT39_GPIO_MASK 0x2000 +#define RTL8367D_ACT39_FORWARD_OFFSET 12 +#define RTL8367D_ACT39_FORWARD_MASK 0x1000 +#define RTL8367D_ACT39_POLICING_OFFSET 11 +#define RTL8367D_ACT39_POLICING_MASK 0x800 +#define RTL8367D_ACT39_PRIORITY_OFFSET 10 +#define RTL8367D_ACT39_PRIORITY_MASK 0x400 +#define RTL8367D_ACT39_SVID_OFFSET 9 +#define RTL8367D_ACT39_SVID_MASK 0x200 +#define RTL8367D_ACT39_CVID_OFFSET 8 +#define RTL8367D_ACT39_CVID_MASK 0x100 +#define RTL8367D_OP38_NOT_OFFSET 6 +#define RTL8367D_OP38_NOT_MASK 0x40 +#define RTL8367D_ACT38_GPIO_OFFSET 5 +#define RTL8367D_ACT38_GPIO_MASK 0x20 +#define RTL8367D_ACT38_FORWARD_OFFSET 4 +#define RTL8367D_ACT38_FORWARD_MASK 0x10 +#define RTL8367D_ACT38_POLICING_OFFSET 3 +#define RTL8367D_ACT38_POLICING_MASK 0x8 +#define RTL8367D_ACT38_PRIORITY_OFFSET 2 +#define RTL8367D_ACT38_PRIORITY_MASK 0x4 +#define RTL8367D_ACT38_SVID_OFFSET 1 +#define RTL8367D_ACT38_SVID_MASK 0x2 +#define RTL8367D_ACT38_CVID_OFFSET 0 +#define RTL8367D_ACT38_CVID_MASK 0x1 + +#define RTL8367D_REG_ACL_ACTION_CTRL20 0x0628 +#define RTL8367D_OP41_NOT_OFFSET 14 +#define RTL8367D_OP41_NOT_MASK 0x4000 +#define RTL8367D_ACT41_GPIO_OFFSET 13 +#define RTL8367D_ACT41_GPIO_MASK 0x2000 +#define RTL8367D_ACT41_FORWARD_OFFSET 12 +#define RTL8367D_ACT41_FORWARD_MASK 0x1000 +#define RTL8367D_ACT41_POLICING_OFFSET 11 +#define RTL8367D_ACT41_POLICING_MASK 0x800 +#define RTL8367D_ACT41_PRIORITY_OFFSET 10 +#define RTL8367D_ACT41_PRIORITY_MASK 0x400 +#define RTL8367D_ACT41_SVID_OFFSET 9 +#define RTL8367D_ACT41_SVID_MASK 0x200 +#define RTL8367D_ACT41_CVID_OFFSET 8 +#define RTL8367D_ACT41_CVID_MASK 0x100 +#define RTL8367D_OP40_NOT_OFFSET 6 +#define RTL8367D_OP40_NOT_MASK 0x40 +#define RTL8367D_ACT40_GPIO_OFFSET 5 +#define RTL8367D_ACT40_GPIO_MASK 0x20 +#define RTL8367D_ACT40_FORWARD_OFFSET 4 +#define RTL8367D_ACT40_FORWARD_MASK 0x10 +#define RTL8367D_ACT40_POLICING_OFFSET 3 +#define RTL8367D_ACT40_POLICING_MASK 0x8 +#define RTL8367D_ACT40_PRIORITY_OFFSET 2 +#define RTL8367D_ACT40_PRIORITY_MASK 0x4 +#define RTL8367D_ACT40_SVID_OFFSET 1 +#define RTL8367D_ACT40_SVID_MASK 0x2 +#define RTL8367D_ACT40_CVID_OFFSET 0 +#define RTL8367D_ACT40_CVID_MASK 0x1 + +#define RTL8367D_REG_ACL_ACTION_CTRL21 0x0629 +#define RTL8367D_OP43_NOT_OFFSET 14 +#define RTL8367D_OP43_NOT_MASK 0x4000 +#define RTL8367D_ACT43_GPIO_OFFSET 13 +#define RTL8367D_ACT43_GPIO_MASK 0x2000 +#define RTL8367D_ACT43_FORWARD_OFFSET 12 +#define RTL8367D_ACT43_FORWARD_MASK 0x1000 +#define RTL8367D_ACT43_POLICING_OFFSET 11 +#define RTL8367D_ACT43_POLICING_MASK 0x800 +#define RTL8367D_ACT43_PRIORITY_OFFSET 10 +#define RTL8367D_ACT43_PRIORITY_MASK 0x400 +#define RTL8367D_ACT43_SVID_OFFSET 9 +#define RTL8367D_ACT43_SVID_MASK 0x200 +#define RTL8367D_ACT43_CVID_OFFSET 8 +#define RTL8367D_ACT43_CVID_MASK 0x100 +#define RTL8367D_OP42_NOT_OFFSET 6 +#define RTL8367D_OP42_NOT_MASK 0x40 +#define RTL8367D_ACT42_GPIO_OFFSET 5 +#define RTL8367D_ACT42_GPIO_MASK 0x20 +#define RTL8367D_ACT42_FORWARD_OFFSET 4 +#define RTL8367D_ACT42_FORWARD_MASK 0x10 +#define RTL8367D_ACT42_POLICING_OFFSET 3 +#define RTL8367D_ACT42_POLICING_MASK 0x8 +#define RTL8367D_ACT42_PRIORITY_OFFSET 2 +#define RTL8367D_ACT42_PRIORITY_MASK 0x4 +#define RTL8367D_ACT42_SVID_OFFSET 1 +#define RTL8367D_ACT42_SVID_MASK 0x2 +#define RTL8367D_ACT42_CVID_OFFSET 0 +#define RTL8367D_ACT42_CVID_MASK 0x1 + +#define RTL8367D_REG_ACL_ACTION_CTRL22 0x062a +#define RTL8367D_OP45_NOT_OFFSET 14 +#define RTL8367D_OP45_NOT_MASK 0x4000 +#define RTL8367D_ACT45_GPIO_OFFSET 13 +#define RTL8367D_ACT45_GPIO_MASK 0x2000 +#define RTL8367D_ACT45_FORWARD_OFFSET 12 +#define RTL8367D_ACT45_FORWARD_MASK 0x1000 +#define RTL8367D_ACT45_POLICING_OFFSET 11 +#define RTL8367D_ACT45_POLICING_MASK 0x800 +#define RTL8367D_ACT45_PRIORITY_OFFSET 10 +#define RTL8367D_ACT45_PRIORITY_MASK 0x400 +#define RTL8367D_ACT45_SVID_OFFSET 9 +#define RTL8367D_ACT45_SVID_MASK 0x200 +#define RTL8367D_ACT45_CVID_OFFSET 8 +#define RTL8367D_ACT45_CVID_MASK 0x100 +#define RTL8367D_OP44_NOT_OFFSET 6 +#define RTL8367D_OP44_NOT_MASK 0x40 +#define RTL8367D_ACT44_GPIO_OFFSET 5 +#define RTL8367D_ACT44_GPIO_MASK 0x20 +#define RTL8367D_ACT44_FORWARD_OFFSET 4 +#define RTL8367D_ACT44_FORWARD_MASK 0x10 +#define RTL8367D_ACT44_POLICING_OFFSET 3 +#define RTL8367D_ACT44_POLICING_MASK 0x8 +#define RTL8367D_ACT44_PRIORITY_OFFSET 2 +#define RTL8367D_ACT44_PRIORITY_MASK 0x4 +#define RTL8367D_ACT44_SVID_OFFSET 1 +#define RTL8367D_ACT44_SVID_MASK 0x2 +#define RTL8367D_ACT44_CVID_OFFSET 0 +#define RTL8367D_ACT44_CVID_MASK 0x1 + +#define RTL8367D_REG_ACL_ACTION_CTRL23 0x062b +#define RTL8367D_OP47_NOT_OFFSET 14 +#define RTL8367D_OP47_NOT_MASK 0x4000 +#define RTL8367D_ACT47_GPIO_OFFSET 13 +#define RTL8367D_ACT47_GPIO_MASK 0x2000 +#define RTL8367D_ACT47_FORWARD_OFFSET 12 +#define RTL8367D_ACT47_FORWARD_MASK 0x1000 +#define RTL8367D_ACT47_POLICING_OFFSET 11 +#define RTL8367D_ACT47_POLICING_MASK 0x800 +#define RTL8367D_ACT47_PRIORITY_OFFSET 10 +#define RTL8367D_ACT47_PRIORITY_MASK 0x400 +#define RTL8367D_ACT47_SVID_OFFSET 9 +#define RTL8367D_ACT47_SVID_MASK 0x200 +#define RTL8367D_ACT47_CVID_OFFSET 8 +#define RTL8367D_ACT47_CVID_MASK 0x100 +#define RTL8367D_OP46_NOT_OFFSET 6 +#define RTL8367D_OP46_NOT_MASK 0x40 +#define RTL8367D_ACT46_GPIO_OFFSET 5 +#define RTL8367D_ACT46_GPIO_MASK 0x20 +#define RTL8367D_ACT46_FORWARD_OFFSET 4 +#define RTL8367D_ACT46_FORWARD_MASK 0x10 +#define RTL8367D_ACT46_POLICING_OFFSET 3 +#define RTL8367D_ACT46_POLICING_MASK 0x8 +#define RTL8367D_ACT46_PRIORITY_OFFSET 2 +#define RTL8367D_ACT46_PRIORITY_MASK 0x4 +#define RTL8367D_ACT46_SVID_OFFSET 1 +#define RTL8367D_ACT46_SVID_MASK 0x2 +#define RTL8367D_ACT46_CVID_OFFSET 0 +#define RTL8367D_ACT46_CVID_MASK 0x1 + +#define RTL8367D_REG_ACL_ACTION_CTRL24 0x062c +#define RTL8367D_OP49_NOT_OFFSET 14 +#define RTL8367D_OP49_NOT_MASK 0x4000 +#define RTL8367D_ACT49_GPIO_OFFSET 13 +#define RTL8367D_ACT49_GPIO_MASK 0x2000 +#define RTL8367D_ACT49_FORWARD_OFFSET 12 +#define RTL8367D_ACT49_FORWARD_MASK 0x1000 +#define RTL8367D_ACT49_POLICING_OFFSET 11 +#define RTL8367D_ACT49_POLICING_MASK 0x800 +#define RTL8367D_ACT49_PRIORITY_OFFSET 10 +#define RTL8367D_ACT49_PRIORITY_MASK 0x400 +#define RTL8367D_ACT49_SVID_OFFSET 9 +#define RTL8367D_ACT49_SVID_MASK 0x200 +#define RTL8367D_ACT49_CVID_OFFSET 8 +#define RTL8367D_ACT49_CVID_MASK 0x100 +#define RTL8367D_OP48_NOT_OFFSET 6 +#define RTL8367D_OP48_NOT_MASK 0x40 +#define RTL8367D_ACT48_GPIO_OFFSET 5 +#define RTL8367D_ACT48_GPIO_MASK 0x20 +#define RTL8367D_ACT48_FORWARD_OFFSET 4 +#define RTL8367D_ACT48_FORWARD_MASK 0x10 +#define RTL8367D_ACT48_POLICING_OFFSET 3 +#define RTL8367D_ACT48_POLICING_MASK 0x8 +#define RTL8367D_ACT48_PRIORITY_OFFSET 2 +#define RTL8367D_ACT48_PRIORITY_MASK 0x4 +#define RTL8367D_ACT48_SVID_OFFSET 1 +#define RTL8367D_ACT48_SVID_MASK 0x2 +#define RTL8367D_ACT48_CVID_OFFSET 0 +#define RTL8367D_ACT48_CVID_MASK 0x1 + +#define RTL8367D_REG_ACL_ACTION_CTRL25 0x062d +#define RTL8367D_OP51_NOT_OFFSET 14 +#define RTL8367D_OP51_NOT_MASK 0x4000 +#define RTL8367D_ACT51_GPIO_OFFSET 13 +#define RTL8367D_ACT51_GPIO_MASK 0x2000 +#define RTL8367D_ACT51_FORWARD_OFFSET 12 +#define RTL8367D_ACT51_FORWARD_MASK 0x1000 +#define RTL8367D_ACT51_POLICING_OFFSET 11 +#define RTL8367D_ACT51_POLICING_MASK 0x800 +#define RTL8367D_ACT51_PRIORITY_OFFSET 10 +#define RTL8367D_ACT51_PRIORITY_MASK 0x400 +#define RTL8367D_ACT51_SVID_OFFSET 9 +#define RTL8367D_ACT51_SVID_MASK 0x200 +#define RTL8367D_ACT51_CVID_OFFSET 8 +#define RTL8367D_ACT51_CVID_MASK 0x100 +#define RTL8367D_OP50_NOT_OFFSET 6 +#define RTL8367D_OP50_NOT_MASK 0x40 +#define RTL8367D_ACT50_GPIO_OFFSET 5 +#define RTL8367D_ACT50_GPIO_MASK 0x20 +#define RTL8367D_ACT50_FORWARD_OFFSET 4 +#define RTL8367D_ACT50_FORWARD_MASK 0x10 +#define RTL8367D_ACT50_POLICING_OFFSET 3 +#define RTL8367D_ACT50_POLICING_MASK 0x8 +#define RTL8367D_ACT50_PRIORITY_OFFSET 2 +#define RTL8367D_ACT50_PRIORITY_MASK 0x4 +#define RTL8367D_ACT50_SVID_OFFSET 1 +#define RTL8367D_ACT50_SVID_MASK 0x2 +#define RTL8367D_ACT50_CVID_OFFSET 0 +#define RTL8367D_ACT50_CVID_MASK 0x1 + +#define RTL8367D_REG_ACL_ACTION_CTRL26 0x062e +#define RTL8367D_OP53_NOT_OFFSET 14 +#define RTL8367D_OP53_NOT_MASK 0x4000 +#define RTL8367D_ACT53_GPIO_OFFSET 13 +#define RTL8367D_ACT53_GPIO_MASK 0x2000 +#define RTL8367D_ACT53_FORWARD_OFFSET 12 +#define RTL8367D_ACT53_FORWARD_MASK 0x1000 +#define RTL8367D_ACT53_POLICING_OFFSET 11 +#define RTL8367D_ACT53_POLICING_MASK 0x800 +#define RTL8367D_ACT53_PRIORITY_OFFSET 10 +#define RTL8367D_ACT53_PRIORITY_MASK 0x400 +#define RTL8367D_ACT53_SVID_OFFSET 9 +#define RTL8367D_ACT53_SVID_MASK 0x200 +#define RTL8367D_ACT53_CVID_OFFSET 8 +#define RTL8367D_ACT53_CVID_MASK 0x100 +#define RTL8367D_OP52_NOT_OFFSET 6 +#define RTL8367D_OP52_NOT_MASK 0x40 +#define RTL8367D_ACT52_GPIO_OFFSET 5 +#define RTL8367D_ACT52_GPIO_MASK 0x20 +#define RTL8367D_ACT52_FORWARD_OFFSET 4 +#define RTL8367D_ACT52_FORWARD_MASK 0x10 +#define RTL8367D_ACT52_POLICING_OFFSET 3 +#define RTL8367D_ACT52_POLICING_MASK 0x8 +#define RTL8367D_ACT52_PRIORITY_OFFSET 2 +#define RTL8367D_ACT52_PRIORITY_MASK 0x4 +#define RTL8367D_ACT52_SVID_OFFSET 1 +#define RTL8367D_ACT52_SVID_MASK 0x2 +#define RTL8367D_ACT52_CVID_OFFSET 0 +#define RTL8367D_ACT52_CVID_MASK 0x1 + +#define RTL8367D_REG_ACL_ACTION_CTRL27 0x062f +#define RTL8367D_OP55_NOT_OFFSET 14 +#define RTL8367D_OP55_NOT_MASK 0x4000 +#define RTL8367D_ACT55_GPIO_OFFSET 13 +#define RTL8367D_ACT55_GPIO_MASK 0x2000 +#define RTL8367D_ACT55_FORWARD_OFFSET 12 +#define RTL8367D_ACT55_FORWARD_MASK 0x1000 +#define RTL8367D_ACT55_POLICING_OFFSET 11 +#define RTL8367D_ACT55_POLICING_MASK 0x800 +#define RTL8367D_ACT55_PRIORITY_OFFSET 10 +#define RTL8367D_ACT55_PRIORITY_MASK 0x400 +#define RTL8367D_ACT55_SVID_OFFSET 9 +#define RTL8367D_ACT55_SVID_MASK 0x200 +#define RTL8367D_ACT55_CVID_OFFSET 8 +#define RTL8367D_ACT55_CVID_MASK 0x100 +#define RTL8367D_OP54_NOT_OFFSET 6 +#define RTL8367D_OP54_NOT_MASK 0x40 +#define RTL8367D_ACT54_GPIO_OFFSET 5 +#define RTL8367D_ACT54_GPIO_MASK 0x20 +#define RTL8367D_ACT54_FORWARD_OFFSET 4 +#define RTL8367D_ACT54_FORWARD_MASK 0x10 +#define RTL8367D_ACT54_POLICING_OFFSET 3 +#define RTL8367D_ACT54_POLICING_MASK 0x8 +#define RTL8367D_ACT54_PRIORITY_OFFSET 2 +#define RTL8367D_ACT54_PRIORITY_MASK 0x4 +#define RTL8367D_ACT54_SVID_OFFSET 1 +#define RTL8367D_ACT54_SVID_MASK 0x2 +#define RTL8367D_ACT54_CVID_OFFSET 0 +#define RTL8367D_ACT54_CVID_MASK 0x1 + +#define RTL8367D_REG_ACL_ACTION_CTRL28 0x0630 +#define RTL8367D_OP57_NOT_OFFSET 14 +#define RTL8367D_OP57_NOT_MASK 0x4000 +#define RTL8367D_ACT57_GPIO_OFFSET 13 +#define RTL8367D_ACT57_GPIO_MASK 0x2000 +#define RTL8367D_ACT57_FORWARD_OFFSET 12 +#define RTL8367D_ACT57_FORWARD_MASK 0x1000 +#define RTL8367D_ACT57_POLICING_OFFSET 11 +#define RTL8367D_ACT57_POLICING_MASK 0x800 +#define RTL8367D_ACT57_PRIORITY_OFFSET 10 +#define RTL8367D_ACT57_PRIORITY_MASK 0x400 +#define RTL8367D_ACT57_SVID_OFFSET 9 +#define RTL8367D_ACT57_SVID_MASK 0x200 +#define RTL8367D_ACT57_CVID_OFFSET 8 +#define RTL8367D_ACT57_CVID_MASK 0x100 +#define RTL8367D_OP56_NOT_OFFSET 6 +#define RTL8367D_OP56_NOT_MASK 0x40 +#define RTL8367D_ACT56_GPIO_OFFSET 5 +#define RTL8367D_ACT56_GPIO_MASK 0x20 +#define RTL8367D_ACT56_FORWARD_OFFSET 4 +#define RTL8367D_ACT56_FORWARD_MASK 0x10 +#define RTL8367D_ACT56_POLICING_OFFSET 3 +#define RTL8367D_ACT56_POLICING_MASK 0x8 +#define RTL8367D_ACT56_PRIORITY_OFFSET 2 +#define RTL8367D_ACT56_PRIORITY_MASK 0x4 +#define RTL8367D_ACT56_SVID_OFFSET 1 +#define RTL8367D_ACT56_SVID_MASK 0x2 +#define RTL8367D_ACT56_CVID_OFFSET 0 +#define RTL8367D_ACT56_CVID_MASK 0x1 + +#define RTL8367D_REG_ACL_ACTION_CTRL29 0x0631 +#define RTL8367D_OP59_NOT_OFFSET 14 +#define RTL8367D_OP59_NOT_MASK 0x4000 +#define RTL8367D_ACT59_GPIO_OFFSET 13 +#define RTL8367D_ACT59_GPIO_MASK 0x2000 +#define RTL8367D_ACT59_FORWARD_OFFSET 12 +#define RTL8367D_ACT59_FORWARD_MASK 0x1000 +#define RTL8367D_ACT59_POLICING_OFFSET 11 +#define RTL8367D_ACT59_POLICING_MASK 0x800 +#define RTL8367D_ACT59_PRIORITY_OFFSET 10 +#define RTL8367D_ACT59_PRIORITY_MASK 0x400 +#define RTL8367D_ACT59_SVID_OFFSET 9 +#define RTL8367D_ACT59_SVID_MASK 0x200 +#define RTL8367D_ACT59_CVID_OFFSET 8 +#define RTL8367D_ACT59_CVID_MASK 0x100 +#define RTL8367D_OP58_NOT_OFFSET 6 +#define RTL8367D_OP58_NOT_MASK 0x40 +#define RTL8367D_ACT58_GPIO_OFFSET 5 +#define RTL8367D_ACT58_GPIO_MASK 0x20 +#define RTL8367D_ACT58_FORWARD_OFFSET 4 +#define RTL8367D_ACT58_FORWARD_MASK 0x10 +#define RTL8367D_ACT58_POLICING_OFFSET 3 +#define RTL8367D_ACT58_POLICING_MASK 0x8 +#define RTL8367D_ACT58_PRIORITY_OFFSET 2 +#define RTL8367D_ACT58_PRIORITY_MASK 0x4 +#define RTL8367D_ACT58_SVID_OFFSET 1 +#define RTL8367D_ACT58_SVID_MASK 0x2 +#define RTL8367D_ACT58_CVID_OFFSET 0 +#define RTL8367D_ACT58_CVID_MASK 0x1 + +#define RTL8367D_REG_ACL_ACTION_CTRL30 0x0632 +#define RTL8367D_OP61_NOT_OFFSET 14 +#define RTL8367D_OP61_NOT_MASK 0x4000 +#define RTL8367D_ACT61_GPIO_OFFSET 13 +#define RTL8367D_ACT61_GPIO_MASK 0x2000 +#define RTL8367D_ACT61_FORWARD_OFFSET 12 +#define RTL8367D_ACT61_FORWARD_MASK 0x1000 +#define RTL8367D_ACT61_POLICING_OFFSET 11 +#define RTL8367D_ACT61_POLICING_MASK 0x800 +#define RTL8367D_ACT61_PRIORITY_OFFSET 10 +#define RTL8367D_ACT61_PRIORITY_MASK 0x400 +#define RTL8367D_ACT61_SVID_OFFSET 9 +#define RTL8367D_ACT61_SVID_MASK 0x200 +#define RTL8367D_ACT61_CVID_OFFSET 8 +#define RTL8367D_ACT61_CVID_MASK 0x100 +#define RTL8367D_OP60_NOT_OFFSET 6 +#define RTL8367D_OP60_NOT_MASK 0x40 +#define RTL8367D_ACT60_GPIO_OFFSET 5 +#define RTL8367D_ACT60_GPIO_MASK 0x20 +#define RTL8367D_ACT60_FORWARD_OFFSET 4 +#define RTL8367D_ACT60_FORWARD_MASK 0x10 +#define RTL8367D_ACT60_POLICING_OFFSET 3 +#define RTL8367D_ACT60_POLICING_MASK 0x8 +#define RTL8367D_ACT60_PRIORITY_OFFSET 2 +#define RTL8367D_ACT60_PRIORITY_MASK 0x4 +#define RTL8367D_ACT60_SVID_OFFSET 1 +#define RTL8367D_ACT60_SVID_MASK 0x2 +#define RTL8367D_ACT60_CVID_OFFSET 0 +#define RTL8367D_ACT60_CVID_MASK 0x1 + +#define RTL8367D_REG_ACL_ACTION_CTRL31 0x0633 +#define RTL8367D_OP63_NOT_OFFSET 14 +#define RTL8367D_OP63_NOT_MASK 0x4000 +#define RTL8367D_ACT63_GPIO_OFFSET 13 +#define RTL8367D_ACT63_GPIO_MASK 0x2000 +#define RTL8367D_ACT63_FORWARD_OFFSET 12 +#define RTL8367D_ACT63_FORWARD_MASK 0x1000 +#define RTL8367D_ACT63_POLICING_OFFSET 11 +#define RTL8367D_ACT63_POLICING_MASK 0x800 +#define RTL8367D_ACT63_PRIORITY_OFFSET 10 +#define RTL8367D_ACT63_PRIORITY_MASK 0x400 +#define RTL8367D_ACT63_SVID_OFFSET 9 +#define RTL8367D_ACT63_SVID_MASK 0x200 +#define RTL8367D_ACT63_CVID_OFFSET 8 +#define RTL8367D_ACT63_CVID_MASK 0x100 +#define RTL8367D_OP62_NOT_OFFSET 6 +#define RTL8367D_OP62_NOT_MASK 0x40 +#define RTL8367D_ACT62_GPIO_OFFSET 5 +#define RTL8367D_ACT62_GPIO_MASK 0x20 +#define RTL8367D_ACT62_FORWARD_OFFSET 4 +#define RTL8367D_ACT62_FORWARD_MASK 0x10 +#define RTL8367D_ACT62_POLICING_OFFSET 3 +#define RTL8367D_ACT62_POLICING_MASK 0x8 +#define RTL8367D_ACT62_PRIORITY_OFFSET 2 +#define RTL8367D_ACT62_PRIORITY_MASK 0x4 +#define RTL8367D_ACT62_SVID_OFFSET 1 +#define RTL8367D_ACT62_SVID_MASK 0x2 +#define RTL8367D_ACT62_CVID_OFFSET 0 +#define RTL8367D_ACT62_CVID_MASK 0x1 + +#define RTL8367D_REG_ACL_IP_RANGE_ENTRY0_CTRL0 0x0685 + +#define RTL8367D_REG_ACL_IP_RANGE_ENTRY0_CTRL1 0x0686 + +#define RTL8367D_REG_ACL_IP_RANGE_ENTRY0_CTRL2 0x0687 + +#define RTL8367D_REG_ACL_IP_RANGE_ENTRY0_CTRL3 0x0688 + +#define RTL8367D_REG_ACL_IP_RANGE_ENTRY0_CTRL4 0x0689 +#define RTL8367D_ACL_IP_RANGE_ENTRY0_CTRL4_OFFSET 0 +#define RTL8367D_ACL_IP_RANGE_ENTRY0_CTRL4_MASK 0x7 + +#define RTL8367D_REG_ACL_IP_RANGE_ENTRY1_CTRL0 0x068a + +#define RTL8367D_REG_ACL_IP_RANGE_ENTRY1_CTRL1 0x068b + +#define RTL8367D_REG_ACL_IP_RANGE_ENTRY1_CTRL2 0x068c + +#define RTL8367D_REG_ACL_IP_RANGE_ENTRY1_CTRL3 0x068d + +#define RTL8367D_REG_ACL_IP_RANGE_ENTRY1_CTRL4 0x068e +#define RTL8367D_ACL_IP_RANGE_ENTRY1_CTRL4_OFFSET 0 +#define RTL8367D_ACL_IP_RANGE_ENTRY1_CTRL4_MASK 0x7 + +#define RTL8367D_REG_ACL_IP_RANGE_ENTRY2_CTRL0 0x068f + +#define RTL8367D_REG_ACL_IP_RANGE_ENTRY2_CTRL1 0x0690 + +#define RTL8367D_REG_ACL_IP_RANGE_ENTRY2_CTRL2 0x0691 + +#define RTL8367D_REG_ACL_IP_RANGE_ENTRY2_CTRL3 0x0692 + +#define RTL8367D_REG_ACL_IP_RANGE_ENTRY2_CTRL4 0x0693 +#define RTL8367D_ACL_IP_RANGE_ENTRY2_CTRL4_OFFSET 0 +#define RTL8367D_ACL_IP_RANGE_ENTRY2_CTRL4_MASK 0x7 + +#define RTL8367D_REG_ACL_IP_RANGE_ENTRY3_CTRL0 0x0694 + +#define RTL8367D_REG_ACL_IP_RANGE_ENTRY3_CTRL1 0x0695 + +#define RTL8367D_REG_ACL_IP_RANGE_ENTRY3_CTRL2 0x0696 + +#define RTL8367D_REG_ACL_IP_RANGE_ENTRY3_CTRL3 0x0697 + +#define RTL8367D_REG_ACL_IP_RANGE_ENTRY3_CTRL4 0x0698 +#define RTL8367D_ACL_IP_RANGE_ENTRY3_CTRL4_OFFSET 0 +#define RTL8367D_ACL_IP_RANGE_ENTRY3_CTRL4_MASK 0x7 + +#define RTL8367D_REG_ACL_IP_RANGE_ENTRY4_CTRL0 0x0699 + +#define RTL8367D_REG_ACL_IP_RANGE_ENTRY4_CTRL1 0x069a + +#define RTL8367D_REG_ACL_IP_RANGE_ENTRY4_CTRL2 0x069b + +#define RTL8367D_REG_ACL_IP_RANGE_ENTRY4_CTRL3 0x069c + +#define RTL8367D_REG_ACL_IP_RANGE_ENTRY4_CTRL4 0x069d +#define RTL8367D_ACL_IP_RANGE_ENTRY4_CTRL4_OFFSET 0 +#define RTL8367D_ACL_IP_RANGE_ENTRY4_CTRL4_MASK 0x7 + +#define RTL8367D_REG_ACL_IP_RANGE_ENTRY5_CTRL0 0x069e + +#define RTL8367D_REG_ACL_IP_RANGE_ENTRY5_CTRL1 0x069f + +#define RTL8367D_REG_ACL_IP_RANGE_ENTRY5_CTRL2 0x06a0 + +#define RTL8367D_REG_ACL_IP_RANGE_ENTRY5_CTRL3 0x06a1 + +#define RTL8367D_REG_ACL_IP_RANGE_ENTRY5_CTRL4 0x06a2 +#define RTL8367D_ACL_IP_RANGE_ENTRY5_CTRL4_OFFSET 0 +#define RTL8367D_ACL_IP_RANGE_ENTRY5_CTRL4_MASK 0x7 + +#define RTL8367D_REG_ACL_IP_RANGE_ENTRY6_CTRL0 0x06a3 + +#define RTL8367D_REG_ACL_IP_RANGE_ENTRY6_CTRL1 0x06a4 + +#define RTL8367D_REG_ACL_IP_RANGE_ENTRY6_CTRL2 0x06a5 + +#define RTL8367D_REG_ACL_IP_RANGE_ENTRY6_CTRL3 0x06a6 + +#define RTL8367D_REG_ACL_IP_RANGE_ENTRY6_CTRL4 0x06a7 +#define RTL8367D_ACL_IP_RANGE_ENTRY6_CTRL4_OFFSET 0 +#define RTL8367D_ACL_IP_RANGE_ENTRY6_CTRL4_MASK 0x7 + +#define RTL8367D_REG_ACL_IP_RANGE_ENTRY7_CTRL0 0x06a8 + +#define RTL8367D_REG_ACL_IP_RANGE_ENTRY7_CTRL1 0x06a9 + +#define RTL8367D_REG_ACL_IP_RANGE_ENTRY7_CTRL2 0x06aa + +#define RTL8367D_REG_ACL_IP_RANGE_ENTRY7_CTRL3 0x06ab + +#define RTL8367D_REG_ACL_IP_RANGE_ENTRY7_CTRL4 0x06ac +#define RTL8367D_ACL_IP_RANGE_ENTRY7_CTRL4_OFFSET 0 +#define RTL8367D_ACL_IP_RANGE_ENTRY7_CTRL4_MASK 0x7 + +#define RTL8367D_REG_ACL_ENABLE 0x06d5 +#define RTL8367D_PORT7_ENABLE_OFFSET 7 +#define RTL8367D_PORT7_ENABLE_MASK 0x80 +#define RTL8367D_PORT6_ENABLE_OFFSET 6 +#define RTL8367D_PORT6_ENABLE_MASK 0x40 +#define RTL8367D_PORT5_ENABLE_OFFSET 5 +#define RTL8367D_PORT5_ENABLE_MASK 0x20 +#define RTL8367D_PORT4_ENABLE_OFFSET 4 +#define RTL8367D_PORT4_ENABLE_MASK 0x10 +#define RTL8367D_PORT3_ENABLE_OFFSET 3 +#define RTL8367D_PORT3_ENABLE_MASK 0x8 +#define RTL8367D_PORT2_ENABLE_OFFSET 2 +#define RTL8367D_PORT2_ENABLE_MASK 0x4 +#define RTL8367D_PORT1_ENABLE_OFFSET 1 +#define RTL8367D_PORT1_ENABLE_MASK 0x2 +#define RTL8367D_PORT0_ENABLE_OFFSET 0 +#define RTL8367D_PORT0_ENABLE_MASK 0x1 + +#define RTL8367D_REG_ACL_UNMATCH_PERMIT 0x06d6 +#define RTL8367D_PORT7_PERMIT_OFFSET 7 +#define RTL8367D_PORT7_PERMIT_MASK 0x80 +#define RTL8367D_PORT6_PERMIT_OFFSET 6 +#define RTL8367D_PORT6_PERMIT_MASK 0x40 +#define RTL8367D_PORT5_PERMIT_OFFSET 5 +#define RTL8367D_PORT5_PERMIT_MASK 0x20 +#define RTL8367D_PORT4_PERMIT_OFFSET 4 +#define RTL8367D_PORT4_PERMIT_MASK 0x10 +#define RTL8367D_PORT3_PERMIT_OFFSET 3 +#define RTL8367D_PORT3_PERMIT_MASK 0x8 +#define RTL8367D_PORT2_PERMIT_OFFSET 2 +#define RTL8367D_PORT2_PERMIT_MASK 0x4 +#define RTL8367D_PORT1_PERMIT_OFFSET 1 +#define RTL8367D_PORT1_PERMIT_MASK 0x2 +#define RTL8367D_PORT0_PERMIT_OFFSET 0 +#define RTL8367D_PORT0_PERMIT_MASK 0x1 + +#define RTL8367D_REG_ACL_RESET_CFG 0x06d9 +#define RTL8367D_ACL_RESET_CFG_OFFSET 0 +#define RTL8367D_ACL_RESET_CFG_MASK 0x1 + +#define RTL8367D_REG_ACL_REASON_01 0x06E8 +#define RTL8367D_ACL_ACT_1_OFFSET 8 +#define RTL8367D_ACL_ACT_1_MASK 0xFF00 +#define RTL8367D_ACL_ACT_0_OFFSET 0 +#define RTL8367D_ACL_ACT_0_MASK 0xFF + +#define RTL8367D_REG_ACL_REASON_23 0x06E9 +#define RTL8367D_ACL_ACT_3_OFFSET 8 +#define RTL8367D_ACL_ACT_3_MASK 0xFF00 +#define RTL8367D_ACL_ACT_2_OFFSET 0 +#define RTL8367D_ACL_ACT_2_MASK 0xFF + +#define RTL8367D_REG_ACL_REASON_45 0x06EA +#define RTL8367D_ACL_ACT_5_OFFSET 8 +#define RTL8367D_ACL_ACT_5_MASK 0xFF00 +#define RTL8367D_ACL_ACT_4_OFFSET 0 +#define RTL8367D_ACL_ACT_4_MASK 0xFF + +/* (16'h0700)cvlan_reg */ + +#define RTL8367D_REG_VLAN_PVID_CTRL0 0x0700 +#define RTL8367D_VLAN_PVID_CTRL0_OFFSET 0 +#define RTL8367D_VLAN_PVID_CTRL0_MASK 0xFFF + +#define RTL8367D_REG_VLAN_PVID_CTRL1 0x0701 +#define RTL8367D_VLAN_PVID_CTRL1_OFFSET 0 +#define RTL8367D_VLAN_PVID_CTRL1_MASK 0xFFF + +#define RTL8367D_REG_VLAN_PVID_CTRL2 0x0702 +#define RTL8367D_VLAN_PVID_CTRL2_OFFSET 0 +#define RTL8367D_VLAN_PVID_CTRL2_MASK 0xFFF + +#define RTL8367D_REG_VLAN_PVID_CTRL3 0x0703 +#define RTL8367D_VLAN_PVID_CTRL3_OFFSET 0 +#define RTL8367D_VLAN_PVID_CTRL3_MASK 0xFFF + +#define RTL8367D_REG_VLAN_PVID_CTRL4 0x0704 +#define RTL8367D_VLAN_PVID_CTRL4_OFFSET 0 +#define RTL8367D_VLAN_PVID_CTRL4_MASK 0xFFF + +#define RTL8367D_REG_VLAN_PVID_CTRL5 0x0705 +#define RTL8367D_VLAN_PVID_CTRL5_OFFSET 0 +#define RTL8367D_VLAN_PVID_CTRL5_MASK 0xFFF + +#define RTL8367D_REG_VLAN_PVID_CTRL6 0x0706 +#define RTL8367D_VLAN_PVID_CTRL6_OFFSET 0 +#define RTL8367D_VLAN_PVID_CTRL6_MASK 0xFFF + +#define RTL8367D_REG_VLAN_PVID_CTRL7 0x0707 +#define RTL8367D_VLAN_PVID_CTRL7_OFFSET 0 +#define RTL8367D_VLAN_PVID_CTRL7_MASK 0xFFF + +#define RTL8367D_REG_VLAN_CTRL 0x07a8 +#define RTL8367D_VLAN_CTRL_OFFSET 0 +#define RTL8367D_VLAN_CTRL_MASK 0x1 + +#define RTL8367D_REG_VLAN_INGRESS 0x07a9 +#define RTL8367D_VLAN_INGRESS_OFFSET 0 +#define RTL8367D_VLAN_INGRESS_MASK 0xFF + +#define RTL8367D_REG_VLAN_ACCEPT_FRAME_TYPE_CTRL0 0x07aa +#define RTL8367D_PORT7_FRAME_TYPE_OFFSET 14 +#define RTL8367D_PORT7_FRAME_TYPE_MASK 0xC000 +#define RTL8367D_PORT6_FRAME_TYPE_OFFSET 12 +#define RTL8367D_PORT6_FRAME_TYPE_MASK 0x3000 +#define RTL8367D_PORT5_FRAME_TYPE_OFFSET 10 +#define RTL8367D_PORT5_FRAME_TYPE_MASK 0xC00 +#define RTL8367D_PORT4_FRAME_TYPE_OFFSET 8 +#define RTL8367D_PORT4_FRAME_TYPE_MASK 0x300 +#define RTL8367D_PORT3_FRAME_TYPE_OFFSET 6 +#define RTL8367D_PORT3_FRAME_TYPE_MASK 0xC0 +#define RTL8367D_PORT2_FRAME_TYPE_OFFSET 4 +#define RTL8367D_PORT2_FRAME_TYPE_MASK 0x30 +#define RTL8367D_PORT1_FRAME_TYPE_OFFSET 2 +#define RTL8367D_PORT1_FRAME_TYPE_MASK 0xC +#define RTL8367D_PORT0_FRAME_TYPE_OFFSET 0 +#define RTL8367D_PORT0_FRAME_TYPE_MASK 0x3 + +#define RTL8367D_REG_PORT_PBFIDEN 0x07ac +#define RTL8367D_PORT_PBFIDEN_OFFSET 0 +#define RTL8367D_PORT_PBFIDEN_MASK 0xFF + +#define RTL8367D_REG_PORT0_PBFID 0x07ad +#define RTL8367D_PORT0_PBFID_OFFSET 0 +#define RTL8367D_PORT0_PBFID_MASK 0x3 + +#define RTL8367D_REG_PORT1_PBFID 0x07ae +#define RTL8367D_PORT1_PBFID_OFFSET 0 +#define RTL8367D_PORT1_PBFID_MASK 0x3 + +#define RTL8367D_REG_PORT2_PBFID 0x07af +#define RTL8367D_PORT2_PBFID_OFFSET 0 +#define RTL8367D_PORT2_PBFID_MASK 0x3 + +#define RTL8367D_REG_PORT3_PBFID 0x07b0 +#define RTL8367D_PORT3_PBFID_OFFSET 0 +#define RTL8367D_PORT3_PBFID_MASK 0x3 + +#define RTL8367D_REG_PORT4_PBFID 0x07b1 +#define RTL8367D_PORT4_PBFID_OFFSET 0 +#define RTL8367D_PORT4_PBFID_MASK 0x3 + +#define RTL8367D_REG_PORT5_PBFID 0x07b2 +#define RTL8367D_PORT5_PBFID_OFFSET 0 +#define RTL8367D_PORT5_PBFID_MASK 0x3 + +#define RTL8367D_REG_PORT6_PBFID 0x07b3 +#define RTL8367D_PORT6_PBFID_OFFSET 0 +#define RTL8367D_PORT6_PBFID_MASK 0x3 + +#define RTL8367D_REG_PORT7_PBFID 0x07b4 +#define RTL8367D_PORT7_PBFID_OFFSET 0 +#define RTL8367D_PORT7_PBFID_MASK 0x3 + +#define RTL8367D_REG_VLAN_EXT_CTRL 0x07b5 +#define RTL8367D_VLAN_1P_REMARK_BYPASS_REALKEEP_OFFSET 2 +#define RTL8367D_VLAN_1P_REMARK_BYPASS_REALKEEP_MASK 0x4 +#define RTL8367D_VLAN_VID4095_TYPE_OFFSET 1 +#define RTL8367D_VLAN_VID4095_TYPE_MASK 0x2 +#define RTL8367D_VLAN_VID0_TYPE_OFFSET 0 +#define RTL8367D_VLAN_VID0_TYPE_MASK 0x1 + +#define RTL8367D_REG_VLAN_EXT_CTRL2 0x07b6 +#define RTL8367D_VLAN_EXT_CTRL2_OFFSET 0 +#define RTL8367D_VLAN_EXT_CTRL2_MASK 0x1 + +#define RTL8367D_REG_CVL_BISD_CTRL0 0x0780 +#define RTL8367D_CVL_FRCTL_OFFSET 14 +#define RTL8367D_CVL_FRCTL_MASK 0x4000 +#define RTL8367D_CVL_TGL_OFFSET 13 +#define RTL8367D_CVL_TGL_MASK 0x2000 +#define RTL8367D_CVL_WR_OFFSET 12 +#define RTL8367D_CVL_WR_MASK 0x1000 +#define RTL8367D_CVL_ADR_OFFSET 0 +#define RTL8367D_CVL_ADR_MASK 0xFFF + +#define RTL8367D_REG_CVL_BISD_CTRL1 0x0781 + +#define RTL8367D_REG_CVL_BISD_CTRL2 0x0782 + +#define RTL8367D_REG_CVL_BISD_CTRL3 0x0783 +#define RTL8367D_CVL_BISD_EN_OFFSET 3 +#define RTL8367D_CVL_BISD_EN_MASK 0x8 +#define RTL8367D_CVL_CONS_VAL_OFFSET 2 +#define RTL8367D_CVL_CONS_VAL_MASK 0x4 +#define RTL8367D_CVL_CONS_ACS_OFFSET 1 +#define RTL8367D_CVL_CONS_ACS_MASK 0x2 +#define RTL8367D_CVL_SEL16BNK_OFFSET 0 +#define RTL8367D_CVL_SEL16BNK_MASK 0x1 + +#define RTL8367D_REG_CVL_BISD_CTRL4 0x0784 + +/* (16'h0800)dpm_reg */ + +#define RTL8367D_REG_RMA_CTRL00 0x0800 +#define RTL8367D_RMA_CTRL00_OPERATION_OFFSET 7 +#define RTL8367D_RMA_CTRL00_OPERATION_MASK 0x180 +#define RTL8367D_RMA_CTRL00_DISCARD_STORM_FILTER_OFFSET 6 +#define RTL8367D_RMA_CTRL00_DISCARD_STORM_FILTER_MASK 0x40 +#define RTL8367D_TRAP_PRIORITY_OFFSET 3 +#define RTL8367D_TRAP_PRIORITY_MASK 0x38 +#define RTL8367D_RMA_CTRL00_KEEP_FORMAT_OFFSET 2 +#define RTL8367D_RMA_CTRL00_KEEP_FORMAT_MASK 0x4 +#define RTL8367D_RMA_CTRL00_VLAN_LEAKY_OFFSET 1 +#define RTL8367D_RMA_CTRL00_VLAN_LEAKY_MASK 0x2 +#define RTL8367D_RMA_CTRL00_PORTISO_LEAKY_OFFSET 0 +#define RTL8367D_RMA_CTRL00_PORTISO_LEAKY_MASK 0x1 + +#define RTL8367D_REG_RMA_CTRL01 0x0801 +#define RTL8367D_RMA_CTRL01_OPERATION_OFFSET 7 +#define RTL8367D_RMA_CTRL01_OPERATION_MASK 0x180 +#define RTL8367D_RMA_CTRL01_DISCARD_STORM_FILTER_OFFSET 6 +#define RTL8367D_RMA_CTRL01_DISCARD_STORM_FILTER_MASK 0x40 +#define RTL8367D_RMA_CTRL01_KEEP_FORMAT_OFFSET 2 +#define RTL8367D_RMA_CTRL01_KEEP_FORMAT_MASK 0x4 +#define RTL8367D_RMA_CTRL01_VLAN_LEAKY_OFFSET 1 +#define RTL8367D_RMA_CTRL01_VLAN_LEAKY_MASK 0x2 +#define RTL8367D_RMA_CTRL01_PORTISO_LEAKY_OFFSET 0 +#define RTL8367D_RMA_CTRL01_PORTISO_LEAKY_MASK 0x1 + +#define RTL8367D_REG_RMA_CTRL02 0x0802 +#define RTL8367D_RMA_CTRL02_OPERATION_OFFSET 7 +#define RTL8367D_RMA_CTRL02_OPERATION_MASK 0x180 +#define RTL8367D_RMA_CTRL02_DISCARD_STORM_FILTER_OFFSET 6 +#define RTL8367D_RMA_CTRL02_DISCARD_STORM_FILTER_MASK 0x40 +#define RTL8367D_RMA_CTRL02_KEEP_FORMAT_OFFSET 2 +#define RTL8367D_RMA_CTRL02_KEEP_FORMAT_MASK 0x4 +#define RTL8367D_RMA_CTRL02_VLAN_LEAKY_OFFSET 1 +#define RTL8367D_RMA_CTRL02_VLAN_LEAKY_MASK 0x2 +#define RTL8367D_RMA_CTRL02_PORTISO_LEAKY_OFFSET 0 +#define RTL8367D_RMA_CTRL02_PORTISO_LEAKY_MASK 0x1 + +#define RTL8367D_REG_RMA_CTRL03 0x0803 +#define RTL8367D_RMA_CTRL03_OPERATION_OFFSET 7 +#define RTL8367D_RMA_CTRL03_OPERATION_MASK 0x180 +#define RTL8367D_RMA_CTRL03_DISCARD_STORM_FILTER_OFFSET 6 +#define RTL8367D_RMA_CTRL03_DISCARD_STORM_FILTER_MASK 0x40 +#define RTL8367D_RMA_CTRL03_KEEP_FORMAT_OFFSET 2 +#define RTL8367D_RMA_CTRL03_KEEP_FORMAT_MASK 0x4 +#define RTL8367D_RMA_CTRL03_VLAN_LEAKY_OFFSET 1 +#define RTL8367D_RMA_CTRL03_VLAN_LEAKY_MASK 0x2 +#define RTL8367D_RMA_CTRL03_PORTISO_LEAKY_OFFSET 0 +#define RTL8367D_RMA_CTRL03_PORTISO_LEAKY_MASK 0x1 + +#define RTL8367D_REG_RMA_CTRL04 0x0804 +#define RTL8367D_RMA_CTRL04_OPERATION_OFFSET 7 +#define RTL8367D_RMA_CTRL04_OPERATION_MASK 0x180 +#define RTL8367D_RMA_CTRL04_DISCARD_STORM_FILTER_OFFSET 6 +#define RTL8367D_RMA_CTRL04_DISCARD_STORM_FILTER_MASK 0x40 +#define RTL8367D_RMA_CTRL04_KEEP_FORMAT_OFFSET 2 +#define RTL8367D_RMA_CTRL04_KEEP_FORMAT_MASK 0x4 +#define RTL8367D_RMA_CTRL04_VLAN_LEAKY_OFFSET 1 +#define RTL8367D_RMA_CTRL04_VLAN_LEAKY_MASK 0x2 +#define RTL8367D_RMA_CTRL04_PORTISO_LEAKY_OFFSET 0 +#define RTL8367D_RMA_CTRL04_PORTISO_LEAKY_MASK 0x1 + +#define RTL8367D_REG_RMA_CTRL08 0x0808 +#define RTL8367D_RMA_CTRL08_OPERATION_OFFSET 7 +#define RTL8367D_RMA_CTRL08_OPERATION_MASK 0x180 +#define RTL8367D_RMA_CTRL08_DISCARD_STORM_FILTER_OFFSET 6 +#define RTL8367D_RMA_CTRL08_DISCARD_STORM_FILTER_MASK 0x40 +#define RTL8367D_RMA_CTRL08_KEEP_FORMAT_OFFSET 2 +#define RTL8367D_RMA_CTRL08_KEEP_FORMAT_MASK 0x4 +#define RTL8367D_RMA_CTRL08_VLAN_LEAKY_OFFSET 1 +#define RTL8367D_RMA_CTRL08_VLAN_LEAKY_MASK 0x2 +#define RTL8367D_RMA_CTRL08_PORTISO_LEAKY_OFFSET 0 +#define RTL8367D_RMA_CTRL08_PORTISO_LEAKY_MASK 0x1 + +#define RTL8367D_REG_RMA_CTRL0D 0x080d +#define RTL8367D_RMA_CTRL0D_OPERATION_OFFSET 7 +#define RTL8367D_RMA_CTRL0D_OPERATION_MASK 0x180 +#define RTL8367D_RMA_CTRL0D_DISCARD_STORM_FILTER_OFFSET 6 +#define RTL8367D_RMA_CTRL0D_DISCARD_STORM_FILTER_MASK 0x40 +#define RTL8367D_RMA_CTRL0D_KEEP_FORMAT_OFFSET 2 +#define RTL8367D_RMA_CTRL0D_KEEP_FORMAT_MASK 0x4 +#define RTL8367D_RMA_CTRL0D_VLAN_LEAKY_OFFSET 1 +#define RTL8367D_RMA_CTRL0D_VLAN_LEAKY_MASK 0x2 +#define RTL8367D_RMA_CTRL0D_PORTISO_LEAKY_OFFSET 0 +#define RTL8367D_RMA_CTRL0D_PORTISO_LEAKY_MASK 0x1 + +#define RTL8367D_REG_RMA_CTRL0E 0x080e +#define RTL8367D_RMA_CTRL0E_OPERATION_OFFSET 7 +#define RTL8367D_RMA_CTRL0E_OPERATION_MASK 0x180 +#define RTL8367D_RMA_CTRL0E_DISCARD_STORM_FILTER_OFFSET 6 +#define RTL8367D_RMA_CTRL0E_DISCARD_STORM_FILTER_MASK 0x40 +#define RTL8367D_RMA_CTRL0E_KEEP_FORMAT_OFFSET 2 +#define RTL8367D_RMA_CTRL0E_KEEP_FORMAT_MASK 0x4 +#define RTL8367D_RMA_CTRL0E_VLAN_LEAKY_OFFSET 1 +#define RTL8367D_RMA_CTRL0E_VLAN_LEAKY_MASK 0x2 +#define RTL8367D_RMA_CTRL0E_PORTISO_LEAKY_OFFSET 0 +#define RTL8367D_RMA_CTRL0E_PORTISO_LEAKY_MASK 0x1 + +#define RTL8367D_REG_RMA_CTRL10 0x0810 +#define RTL8367D_RMA_CTRL10_OPERATION_OFFSET 7 +#define RTL8367D_RMA_CTRL10_OPERATION_MASK 0x180 +#define RTL8367D_RMA_CTRL10_DISCARD_STORM_FILTER_OFFSET 6 +#define RTL8367D_RMA_CTRL10_DISCARD_STORM_FILTER_MASK 0x40 +#define RTL8367D_RMA_CTRL10_KEEP_FORMAT_OFFSET 2 +#define RTL8367D_RMA_CTRL10_KEEP_FORMAT_MASK 0x4 +#define RTL8367D_RMA_CTRL10_VLAN_LEAKY_OFFSET 1 +#define RTL8367D_RMA_CTRL10_VLAN_LEAKY_MASK 0x2 +#define RTL8367D_RMA_CTRL10_PORTISO_LEAKY_OFFSET 0 +#define RTL8367D_RMA_CTRL10_PORTISO_LEAKY_MASK 0x1 + +#define RTL8367D_REG_RMA_CTRL11 0x0811 +#define RTL8367D_RMA_CTRL11_OPERATION_OFFSET 7 +#define RTL8367D_RMA_CTRL11_OPERATION_MASK 0x180 +#define RTL8367D_RMA_CTRL11_DISCARD_STORM_FILTER_OFFSET 6 +#define RTL8367D_RMA_CTRL11_DISCARD_STORM_FILTER_MASK 0x40 +#define RTL8367D_RMA_CTRL11_KEEP_FORMAT_OFFSET 2 +#define RTL8367D_RMA_CTRL11_KEEP_FORMAT_MASK 0x4 +#define RTL8367D_RMA_CTRL11_VLAN_LEAKY_OFFSET 1 +#define RTL8367D_RMA_CTRL11_VLAN_LEAKY_MASK 0x2 +#define RTL8367D_RMA_CTRL11_PORTISO_LEAKY_OFFSET 0 +#define RTL8367D_RMA_CTRL11_PORTISO_LEAKY_MASK 0x1 + +#define RTL8367D_REG_RMA_CTRL12 0x0812 +#define RTL8367D_RMA_CTRL12_OPERATION_OFFSET 7 +#define RTL8367D_RMA_CTRL12_OPERATION_MASK 0x180 +#define RTL8367D_RMA_CTRL12_DISCARD_STORM_FILTER_OFFSET 6 +#define RTL8367D_RMA_CTRL12_DISCARD_STORM_FILTER_MASK 0x40 +#define RTL8367D_RMA_CTRL12_KEEP_FORMAT_OFFSET 2 +#define RTL8367D_RMA_CTRL12_KEEP_FORMAT_MASK 0x4 +#define RTL8367D_RMA_CTRL12_VLAN_LEAKY_OFFSET 1 +#define RTL8367D_RMA_CTRL12_VLAN_LEAKY_MASK 0x2 +#define RTL8367D_RMA_CTRL12_PORTISO_LEAKY_OFFSET 0 +#define RTL8367D_RMA_CTRL12_PORTISO_LEAKY_MASK 0x1 + +#define RTL8367D_REG_RMA_CTRL13 0x0813 +#define RTL8367D_RMA_CTRL13_OPERATION_OFFSET 7 +#define RTL8367D_RMA_CTRL13_OPERATION_MASK 0x180 +#define RTL8367D_RMA_CTRL13_DISCARD_STORM_FILTER_OFFSET 6 +#define RTL8367D_RMA_CTRL13_DISCARD_STORM_FILTER_MASK 0x40 +#define RTL8367D_RMA_CTRL13_KEEP_FORMAT_OFFSET 2 +#define RTL8367D_RMA_CTRL13_KEEP_FORMAT_MASK 0x4 +#define RTL8367D_RMA_CTRL13_VLAN_LEAKY_OFFSET 1 +#define RTL8367D_RMA_CTRL13_VLAN_LEAKY_MASK 0x2 +#define RTL8367D_RMA_CTRL13_PORTISO_LEAKY_OFFSET 0 +#define RTL8367D_RMA_CTRL13_PORTISO_LEAKY_MASK 0x1 + +#define RTL8367D_REG_RMA_CTRL18 0x0818 +#define RTL8367D_RMA_CTRL18_OPERATION_OFFSET 7 +#define RTL8367D_RMA_CTRL18_OPERATION_MASK 0x180 +#define RTL8367D_RMA_CTRL18_DISCARD_STORM_FILTER_OFFSET 6 +#define RTL8367D_RMA_CTRL18_DISCARD_STORM_FILTER_MASK 0x40 +#define RTL8367D_RMA_CTRL18_KEEP_FORMAT_OFFSET 2 +#define RTL8367D_RMA_CTRL18_KEEP_FORMAT_MASK 0x4 +#define RTL8367D_RMA_CTRL18_VLAN_LEAKY_OFFSET 1 +#define RTL8367D_RMA_CTRL18_VLAN_LEAKY_MASK 0x2 +#define RTL8367D_RMA_CTRL18_PORTISO_LEAKY_OFFSET 0 +#define RTL8367D_RMA_CTRL18_PORTISO_LEAKY_MASK 0x1 + +#define RTL8367D_REG_RMA_CTRL1A 0x081a +#define RTL8367D_RMA_CTRL1A_OPERATION_OFFSET 7 +#define RTL8367D_RMA_CTRL1A_OPERATION_MASK 0x180 +#define RTL8367D_RMA_CTRL1A_DISCARD_STORM_FILTER_OFFSET 6 +#define RTL8367D_RMA_CTRL1A_DISCARD_STORM_FILTER_MASK 0x40 +#define RTL8367D_RMA_CTRL1A_KEEP_FORMAT_OFFSET 2 +#define RTL8367D_RMA_CTRL1A_KEEP_FORMAT_MASK 0x4 +#define RTL8367D_RMA_CTRL1A_VLAN_LEAKY_OFFSET 1 +#define RTL8367D_RMA_CTRL1A_VLAN_LEAKY_MASK 0x2 +#define RTL8367D_RMA_CTRL1A_PORTISO_LEAKY_OFFSET 0 +#define RTL8367D_RMA_CTRL1A_PORTISO_LEAKY_MASK 0x1 + +#define RTL8367D_REG_RMA_CTRL20 0x0820 +#define RTL8367D_RMA_CTRL20_OPERATION_OFFSET 7 +#define RTL8367D_RMA_CTRL20_OPERATION_MASK 0x180 +#define RTL8367D_RMA_CTRL20_DISCARD_STORM_FILTER_OFFSET 6 +#define RTL8367D_RMA_CTRL20_DISCARD_STORM_FILTER_MASK 0x40 +#define RTL8367D_RMA_CTRL20_KEEP_FORMAT_OFFSET 2 +#define RTL8367D_RMA_CTRL20_KEEP_FORMAT_MASK 0x4 +#define RTL8367D_RMA_CTRL20_VLAN_LEAKY_OFFSET 1 +#define RTL8367D_RMA_CTRL20_VLAN_LEAKY_MASK 0x2 +#define RTL8367D_RMA_CTRL20_PORTISO_LEAKY_OFFSET 0 +#define RTL8367D_RMA_CTRL20_PORTISO_LEAKY_MASK 0x1 + +#define RTL8367D_REG_RMA_CTRL21 0x0821 +#define RTL8367D_RMA_CTRL21_OPERATION_OFFSET 7 +#define RTL8367D_RMA_CTRL21_OPERATION_MASK 0x180 +#define RTL8367D_RMA_CTRL21_DISCARD_STORM_FILTER_OFFSET 6 +#define RTL8367D_RMA_CTRL21_DISCARD_STORM_FILTER_MASK 0x40 +#define RTL8367D_RMA_CTRL21_KEEP_FORMAT_OFFSET 2 +#define RTL8367D_RMA_CTRL21_KEEP_FORMAT_MASK 0x4 +#define RTL8367D_RMA_CTRL21_VLAN_LEAKY_OFFSET 1 +#define RTL8367D_RMA_CTRL21_VLAN_LEAKY_MASK 0x2 +#define RTL8367D_RMA_CTRL21_PORTISO_LEAKY_OFFSET 0 +#define RTL8367D_RMA_CTRL21_PORTISO_LEAKY_MASK 0x1 + +#define RTL8367D_REG_RMA_CTRL22 0x0822 +#define RTL8367D_RMA_CTRL22_OPERATION_OFFSET 7 +#define RTL8367D_RMA_CTRL22_OPERATION_MASK 0x180 +#define RTL8367D_RMA_CTRL22_DISCARD_STORM_FILTER_OFFSET 6 +#define RTL8367D_RMA_CTRL22_DISCARD_STORM_FILTER_MASK 0x40 +#define RTL8367D_RMA_CTRL22_KEEP_FORMAT_OFFSET 2 +#define RTL8367D_RMA_CTRL22_KEEP_FORMAT_MASK 0x4 +#define RTL8367D_RMA_CTRL22_VLAN_LEAKY_OFFSET 1 +#define RTL8367D_RMA_CTRL22_VLAN_LEAKY_MASK 0x2 +#define RTL8367D_RMA_CTRL22_PORTISO_LEAKY_OFFSET 0 +#define RTL8367D_RMA_CTRL22_PORTISO_LEAKY_MASK 0x1 + +#define RTL8367D_REG_RMA_CTRL_CDP 0x0830 +#define RTL8367D_RMA_CTRL_CDP_OPERATION_OFFSET 7 +#define RTL8367D_RMA_CTRL_CDP_OPERATION_MASK 0x180 +#define RTL8367D_RMA_CTRL_CDP_DISCARD_STORM_FILTER_OFFSET 6 +#define RTL8367D_RMA_CTRL_CDP_DISCARD_STORM_FILTER_MASK 0x40 +#define RTL8367D_RMA_CTRL_CDP_KEEP_FORMAT_OFFSET 2 +#define RTL8367D_RMA_CTRL_CDP_KEEP_FORMAT_MASK 0x4 +#define RTL8367D_RMA_CTRL_CDP_VLAN_LEAKY_OFFSET 1 +#define RTL8367D_RMA_CTRL_CDP_VLAN_LEAKY_MASK 0x2 +#define RTL8367D_RMA_CTRL_CDP_PORTISO_LEAKY_OFFSET 0 +#define RTL8367D_RMA_CTRL_CDP_PORTISO_LEAKY_MASK 0x1 + +#define RTL8367D_REG_RMA_CTRL_CSSTP 0x0831 +#define RTL8367D_RMA_CTRL_CSSTP_OPERATION_OFFSET 7 +#define RTL8367D_RMA_CTRL_CSSTP_OPERATION_MASK 0x180 +#define RTL8367D_RMA_CTRL_CSSTP_DISCARD_STORM_FILTER_OFFSET 6 +#define RTL8367D_RMA_CTRL_CSSTP_DISCARD_STORM_FILTER_MASK 0x40 +#define RTL8367D_RMA_CTRL_CSSTP_KEEP_FORMAT_OFFSET 2 +#define RTL8367D_RMA_CTRL_CSSTP_KEEP_FORMAT_MASK 0x4 +#define RTL8367D_RMA_CTRL_CSSTP_VLAN_LEAKY_OFFSET 1 +#define RTL8367D_RMA_CTRL_CSSTP_VLAN_LEAKY_MASK 0x2 +#define RTL8367D_RMA_CTRL_CSSTP_PORTISO_LEAKY_OFFSET 0 +#define RTL8367D_RMA_CTRL_CSSTP_PORTISO_LEAKY_MASK 0x1 + +#define RTL8367D_REG_RMA_CTRL_LLDP 0x0832 +#define RTL8367D_RMA_CTRL_LLDP_OPERATION_OFFSET 7 +#define RTL8367D_RMA_CTRL_LLDP_OPERATION_MASK 0x180 +#define RTL8367D_RMA_CTRL_LLDP_DISCARD_STORM_FILTER_OFFSET 6 +#define RTL8367D_RMA_CTRL_LLDP_DISCARD_STORM_FILTER_MASK 0x40 +#define RTL8367D_RMA_CTRL_LLDP_KEEP_FORMAT_OFFSET 2 +#define RTL8367D_RMA_CTRL_LLDP_KEEP_FORMAT_MASK 0x4 +#define RTL8367D_RMA_CTRL_LLDP_VLAN_LEAKY_OFFSET 1 +#define RTL8367D_RMA_CTRL_LLDP_VLAN_LEAKY_MASK 0x2 +#define RTL8367D_RMA_CTRL_LLDP_PORTISO_LEAKY_OFFSET 0 +#define RTL8367D_RMA_CTRL_LLDP_PORTISO_LEAKY_MASK 0x1 + +#define RTL8367D_REG_RMA_LLDP_EN 0x0833 +#define RTL8367D_RMA_LLDP_EN_OFFSET 0 +#define RTL8367D_RMA_LLDP_EN_MASK 0x1 + +#define RTL8367D_REG_QOS_1Q_PRIORITY_REMAPPING_CTRL0 0x0865 +#define RTL8367D_QOS_1Q_PRIORITY_REMAPPING_CTRL0_PRIORITY3_OFFSET 12 +#define RTL8367D_QOS_1Q_PRIORITY_REMAPPING_CTRL0_PRIORITY3_MASK 0x7000 +#define RTL8367D_QOS_1Q_PRIORITY_REMAPPING_CTRL0_PRIORITY2_OFFSET 8 +#define RTL8367D_QOS_1Q_PRIORITY_REMAPPING_CTRL0_PRIORITY2_MASK 0x700 +#define RTL8367D_QOS_1Q_PRIORITY_REMAPPING_CTRL0_PRIORITY1_OFFSET 4 +#define RTL8367D_QOS_1Q_PRIORITY_REMAPPING_CTRL0_PRIORITY1_MASK 0x70 +#define RTL8367D_QOS_1Q_PRIORITY_REMAPPING_CTRL0_PRIORITY0_OFFSET 0 +#define RTL8367D_QOS_1Q_PRIORITY_REMAPPING_CTRL0_PRIORITY0_MASK 0x7 + +#define RTL8367D_REG_QOS_1Q_PRIORITY_REMAPPING_CTRL1 0x0866 +#define RTL8367D_QOS_1Q_PRIORITY_REMAPPING_CTRL1_PRIORITY7_OFFSET 12 +#define RTL8367D_QOS_1Q_PRIORITY_REMAPPING_CTRL1_PRIORITY7_MASK 0x7000 +#define RTL8367D_QOS_1Q_PRIORITY_REMAPPING_CTRL1_PRIORITY6_OFFSET 8 +#define RTL8367D_QOS_1Q_PRIORITY_REMAPPING_CTRL1_PRIORITY6_MASK 0x700 +#define RTL8367D_QOS_1Q_PRIORITY_REMAPPING_CTRL1_PRIORITY5_OFFSET 4 +#define RTL8367D_QOS_1Q_PRIORITY_REMAPPING_CTRL1_PRIORITY5_MASK 0x70 +#define RTL8367D_QOS_1Q_PRIORITY_REMAPPING_CTRL1_PRIORITY4_OFFSET 0 +#define RTL8367D_QOS_1Q_PRIORITY_REMAPPING_CTRL1_PRIORITY4_MASK 0x7 + +#define RTL8367D_REG_QOS_DSCP_TO_PRIORITY_CTRL0 0x0867 +#define RTL8367D_DSCP3_PRIORITY_OFFSET 12 +#define RTL8367D_DSCP3_PRIORITY_MASK 0x7000 +#define RTL8367D_DSCP2_PRIORITY_OFFSET 8 +#define RTL8367D_DSCP2_PRIORITY_MASK 0x700 +#define RTL8367D_DSCP1_PRIORITY_OFFSET 4 +#define RTL8367D_DSCP1_PRIORITY_MASK 0x70 +#define RTL8367D_DSCP0_PRIORITY_OFFSET 0 +#define RTL8367D_DSCP0_PRIORITY_MASK 0x7 + +#define RTL8367D_REG_QOS_DSCP_TO_PRIORITY_CTRL1 0x0868 +#define RTL8367D_DSCP7_PRIORITY_OFFSET 12 +#define RTL8367D_DSCP7_PRIORITY_MASK 0x7000 +#define RTL8367D_DSCP6_PRIORITY_OFFSET 8 +#define RTL8367D_DSCP6_PRIORITY_MASK 0x700 +#define RTL8367D_DSCP5_PRIORITY_OFFSET 4 +#define RTL8367D_DSCP5_PRIORITY_MASK 0x70 +#define RTL8367D_DSCP4_PRIORITY_OFFSET 0 +#define RTL8367D_DSCP4_PRIORITY_MASK 0x7 + +#define RTL8367D_REG_QOS_DSCP_TO_PRIORITY_CTRL2 0x0869 +#define RTL8367D_DSCP11_PRIORITY_OFFSET 12 +#define RTL8367D_DSCP11_PRIORITY_MASK 0x7000 +#define RTL8367D_DSCP10_PRIORITY_OFFSET 8 +#define RTL8367D_DSCP10_PRIORITY_MASK 0x700 +#define RTL8367D_DSCP9_PRIORITY_OFFSET 4 +#define RTL8367D_DSCP9_PRIORITY_MASK 0x70 +#define RTL8367D_DSCP8_PRIORITY_OFFSET 0 +#define RTL8367D_DSCP8_PRIORITY_MASK 0x7 + +#define RTL8367D_REG_QOS_DSCP_TO_PRIORITY_CTRL3 0x086a +#define RTL8367D_DSCP15_PRIORITY_OFFSET 12 +#define RTL8367D_DSCP15_PRIORITY_MASK 0x7000 +#define RTL8367D_DSCP14_PRIORITY_OFFSET 8 +#define RTL8367D_DSCP14_PRIORITY_MASK 0x700 +#define RTL8367D_DSCP13_PRIORITY_OFFSET 4 +#define RTL8367D_DSCP13_PRIORITY_MASK 0x70 +#define RTL8367D_DSCP12_PRIORITY_OFFSET 0 +#define RTL8367D_DSCP12_PRIORITY_MASK 0x7 + +#define RTL8367D_REG_QOS_DSCP_TO_PRIORITY_CTRL4 0x086b +#define RTL8367D_DSCP19_PRIORITY_OFFSET 12 +#define RTL8367D_DSCP19_PRIORITY_MASK 0x7000 +#define RTL8367D_DSCP18_PRIORITY_OFFSET 8 +#define RTL8367D_DSCP18_PRIORITY_MASK 0x700 +#define RTL8367D_DSCP17_PRIORITY_OFFSET 4 +#define RTL8367D_DSCP17_PRIORITY_MASK 0x70 +#define RTL8367D_DSCP16_PRIORITY_OFFSET 0 +#define RTL8367D_DSCP16_PRIORITY_MASK 0x7 + +#define RTL8367D_REG_QOS_DSCP_TO_PRIORITY_CTRL5 0x086c +#define RTL8367D_DSCP23_PRIORITY_OFFSET 12 +#define RTL8367D_DSCP23_PRIORITY_MASK 0x7000 +#define RTL8367D_DSCP22_PRIORITY_OFFSET 8 +#define RTL8367D_DSCP22_PRIORITY_MASK 0x700 +#define RTL8367D_DSCP21_PRIORITY_OFFSET 4 +#define RTL8367D_DSCP21_PRIORITY_MASK 0x70 +#define RTL8367D_DSCP20_PRIORITY_OFFSET 0 +#define RTL8367D_DSCP20_PRIORITY_MASK 0x7 + +#define RTL8367D_REG_QOS_DSCP_TO_PRIORITY_CTRL6 0x086d +#define RTL8367D_DSCP27_PRIORITY_OFFSET 12 +#define RTL8367D_DSCP27_PRIORITY_MASK 0x7000 +#define RTL8367D_DSCP26_PRIORITY_OFFSET 8 +#define RTL8367D_DSCP26_PRIORITY_MASK 0x700 +#define RTL8367D_DSCP25_PRIORITY_OFFSET 4 +#define RTL8367D_DSCP25_PRIORITY_MASK 0x70 +#define RTL8367D_DSCP24_PRIORITY_OFFSET 0 +#define RTL8367D_DSCP24_PRIORITY_MASK 0x7 + +#define RTL8367D_REG_QOS_DSCP_TO_PRIORITY_CTRL7 0x086e +#define RTL8367D_DSCP31_PRIORITY_OFFSET 12 +#define RTL8367D_DSCP31_PRIORITY_MASK 0x7000 +#define RTL8367D_DSCP30_PRIORITY_OFFSET 8 +#define RTL8367D_DSCP30_PRIORITY_MASK 0x700 +#define RTL8367D_DSCP29_PRIORITY_OFFSET 4 +#define RTL8367D_DSCP29_PRIORITY_MASK 0x70 +#define RTL8367D_DSCP28_PRIORITY_OFFSET 0 +#define RTL8367D_DSCP28_PRIORITY_MASK 0x7 + +#define RTL8367D_REG_QOS_DSCP_TO_PRIORITY_CTRL8 0x086f +#define RTL8367D_DSCP35_PRIORITY_OFFSET 12 +#define RTL8367D_DSCP35_PRIORITY_MASK 0x7000 +#define RTL8367D_DSCP34_PRIORITY_OFFSET 8 +#define RTL8367D_DSCP34_PRIORITY_MASK 0x700 +#define RTL8367D_DSCP33_PRIORITY_OFFSET 4 +#define RTL8367D_DSCP33_PRIORITY_MASK 0x70 +#define RTL8367D_DSCP32_PRIORITY_OFFSET 0 +#define RTL8367D_DSCP32_PRIORITY_MASK 0x7 + +#define RTL8367D_REG_QOS_DSCP_TO_PRIORITY_CTRL9 0x0870 +#define RTL8367D_DSCP39_PRIORITY_OFFSET 12 +#define RTL8367D_DSCP39_PRIORITY_MASK 0x7000 +#define RTL8367D_DSCP38_PRIORITY_OFFSET 8 +#define RTL8367D_DSCP38_PRIORITY_MASK 0x700 +#define RTL8367D_DSCP37_PRIORITY_OFFSET 4 +#define RTL8367D_DSCP37_PRIORITY_MASK 0x70 +#define RTL8367D_DSCP36_PRIORITY_OFFSET 0 +#define RTL8367D_DSCP36_PRIORITY_MASK 0x7 + +#define RTL8367D_REG_QOS_DSCP_TO_PRIORITY_CTRL10 0x0871 +#define RTL8367D_DSCP43_PRIORITY_OFFSET 12 +#define RTL8367D_DSCP43_PRIORITY_MASK 0x7000 +#define RTL8367D_DSCP42_PRIORITY_OFFSET 8 +#define RTL8367D_DSCP42_PRIORITY_MASK 0x700 +#define RTL8367D_DSCP41_PRIORITY_OFFSET 4 +#define RTL8367D_DSCP41_PRIORITY_MASK 0x70 +#define RTL8367D_DSCP40_PRIORITY_OFFSET 0 +#define RTL8367D_DSCP40_PRIORITY_MASK 0x7 + +#define RTL8367D_REG_QOS_DSCP_TO_PRIORITY_CTRL11 0x0872 +#define RTL8367D_DSCP47_PRIORITY_OFFSET 12 +#define RTL8367D_DSCP47_PRIORITY_MASK 0x7000 +#define RTL8367D_DSCP46_PRIORITY_OFFSET 8 +#define RTL8367D_DSCP46_PRIORITY_MASK 0x700 +#define RTL8367D_DSCP45_PRIORITY_OFFSET 4 +#define RTL8367D_DSCP45_PRIORITY_MASK 0x70 +#define RTL8367D_DSCP44_PRIORITY_OFFSET 0 +#define RTL8367D_DSCP44_PRIORITY_MASK 0x7 + +#define RTL8367D_REG_QOS_DSCP_TO_PRIORITY_CTRL12 0x0873 +#define RTL8367D_DSCP51_PRIORITY_OFFSET 12 +#define RTL8367D_DSCP51_PRIORITY_MASK 0x7000 +#define RTL8367D_DSCP50_PRIORITY_OFFSET 8 +#define RTL8367D_DSCP50_PRIORITY_MASK 0x700 +#define RTL8367D_DSCP49_PRIORITY_OFFSET 4 +#define RTL8367D_DSCP49_PRIORITY_MASK 0x70 +#define RTL8367D_DSCP48_PRIORITY_OFFSET 0 +#define RTL8367D_DSCP48_PRIORITY_MASK 0x7 + +#define RTL8367D_REG_QOS_DSCP_TO_PRIORITY_CTRL13 0x0874 +#define RTL8367D_DSCP55_PRIORITY_OFFSET 12 +#define RTL8367D_DSCP55_PRIORITY_MASK 0x7000 +#define RTL8367D_DSCP54_PRIORITY_OFFSET 8 +#define RTL8367D_DSCP54_PRIORITY_MASK 0x700 +#define RTL8367D_DSCP53_PRIORITY_OFFSET 4 +#define RTL8367D_DSCP53_PRIORITY_MASK 0x70 +#define RTL8367D_DSCP52_PRIORITY_OFFSET 0 +#define RTL8367D_DSCP52_PRIORITY_MASK 0x7 + +#define RTL8367D_REG_QOS_DSCP_TO_PRIORITY_CTRL14 0x0875 +#define RTL8367D_DSCP59_PRIORITY_OFFSET 12 +#define RTL8367D_DSCP59_PRIORITY_MASK 0x7000 +#define RTL8367D_DSCP58_PRIORITY_OFFSET 8 +#define RTL8367D_DSCP58_PRIORITY_MASK 0x700 +#define RTL8367D_DSCP57_PRIORITY_OFFSET 4 +#define RTL8367D_DSCP57_PRIORITY_MASK 0x70 +#define RTL8367D_DSCP56_PRIORITY_OFFSET 0 +#define RTL8367D_DSCP56_PRIORITY_MASK 0x7 + +#define RTL8367D_REG_QOS_DSCP_TO_PRIORITY_CTRL15 0x0876 +#define RTL8367D_DSCP63_PRIORITY_OFFSET 12 +#define RTL8367D_DSCP63_PRIORITY_MASK 0x7000 +#define RTL8367D_DSCP62_PRIORITY_OFFSET 8 +#define RTL8367D_DSCP62_PRIORITY_MASK 0x700 +#define RTL8367D_DSCP61_PRIORITY_OFFSET 4 +#define RTL8367D_DSCP61_PRIORITY_MASK 0x70 +#define RTL8367D_DSCP60_PRIORITY_OFFSET 0 +#define RTL8367D_DSCP60_PRIORITY_MASK 0x7 + +#define RTL8367D_REG_QOS_PORTBASED_PRIORITY_CTRL0 0x0877 +#define RTL8367D_PORT3_PRIORITY_OFFSET 12 +#define RTL8367D_PORT3_PRIORITY_MASK 0x7000 +#define RTL8367D_PORT2_PRIORITY_OFFSET 8 +#define RTL8367D_PORT2_PRIORITY_MASK 0x700 +#define RTL8367D_PORT1_PRIORITY_OFFSET 4 +#define RTL8367D_PORT1_PRIORITY_MASK 0x70 +#define RTL8367D_PORT0_PRIORITY_OFFSET 0 +#define RTL8367D_PORT0_PRIORITY_MASK 0x7 + +#define RTL8367D_REG_QOS_PORTBASED_PRIORITY_CTRL1 0x0878 +#define RTL8367D_PORT7_PRIORITY_OFFSET 12 +#define RTL8367D_PORT7_PRIORITY_MASK 0x7000 +#define RTL8367D_PORT6_PRIORITY_OFFSET 8 +#define RTL8367D_PORT6_PRIORITY_MASK 0x700 +#define RTL8367D_PORT5_PRIORITY_OFFSET 4 +#define RTL8367D_PORT5_PRIORITY_MASK 0x70 +#define RTL8367D_PORT4_PRIORITY_OFFSET 0 +#define RTL8367D_PORT4_PRIORITY_MASK 0x7 + +#define RTL8367D_REG_QOS_INTERNAL_PRIORITY_DECISION_CTRL0 0x087b +#define RTL8367D_QOS_INTERNAL_PRIORITY_DECISION_CTRL0_QOS_ACL_WEIGHT_OFFSET 8 +#define RTL8367D_QOS_INTERNAL_PRIORITY_DECISION_CTRL0_QOS_ACL_WEIGHT_MASK 0x1F00 +#define RTL8367D_QOS_INTERNAL_PRIORITY_DECISION_CTRL0_QOS_PORT_WEIGHT_OFFSET 0 +#define RTL8367D_QOS_INTERNAL_PRIORITY_DECISION_CTRL0_QOS_PORT_WEIGHT_MASK 0x1F + +#define RTL8367D_REG_QOS_INTERNAL_PRIORITY_DECISION_CTRL1 0x087c +#define RTL8367D_QOS_INTERNAL_PRIORITY_DECISION_CTRL1_QOS_DOT1Q_WEIGHT_OFFSET 8 +#define RTL8367D_QOS_INTERNAL_PRIORITY_DECISION_CTRL1_QOS_DOT1Q_WEIGHT_MASK 0x1F00 +#define RTL8367D_QOS_INTERNAL_PRIORITY_DECISION_CTRL1_QOS_DSCP_WEIGHT_OFFSET 0 +#define RTL8367D_QOS_INTERNAL_PRIORITY_DECISION_CTRL1_QOS_DSCP_WEIGHT_MASK 0x1F + +#define RTL8367D_REG_QOS_INTERNAL_PRIORITY_DECISION_CTRL2 0x087d +#define RTL8367D_QOS_INTERNAL_PRIORITY_DECISION_CTRL2_OFFSET 0 +#define RTL8367D_QOS_INTERNAL_PRIORITY_DECISION_CTRL2_MASK 0x1F + +#define RTL8367D_REG_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL0 0x087f +#define RTL8367D_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL0_PRIORITY3_OFFSET 12 +#define RTL8367D_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL0_PRIORITY3_MASK 0x7000 +#define RTL8367D_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL0_PRIORITY2_OFFSET 8 +#define RTL8367D_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL0_PRIORITY2_MASK 0x700 +#define RTL8367D_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL0_PRIORITY1_OFFSET 4 +#define RTL8367D_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL0_PRIORITY1_MASK 0x70 +#define RTL8367D_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL0_PRIORITY0_OFFSET 0 +#define RTL8367D_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL0_PRIORITY0_MASK 0x7 + +#define RTL8367D_REG_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL1 0x0880 +#define RTL8367D_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL1_PRIORITY7_OFFSET 12 +#define RTL8367D_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL1_PRIORITY7_MASK 0x7000 +#define RTL8367D_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL1_PRIORITY6_OFFSET 8 +#define RTL8367D_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL1_PRIORITY6_MASK 0x700 +#define RTL8367D_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL1_PRIORITY5_OFFSET 4 +#define RTL8367D_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL1_PRIORITY5_MASK 0x70 +#define RTL8367D_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL1_PRIORITY4_OFFSET 0 +#define RTL8367D_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL1_PRIORITY4_MASK 0x7 + +#define RTL8367D_REG_QOS_TRAP_PRIORITY0 0x0881 +#define RTL8367D_UNKNOWN_MC_PRIORTY_OFFSET 12 +#define RTL8367D_UNKNOWN_MC_PRIORTY_MASK 0x7000 +#define RTL8367D_SVLAN_PRIOIRTY_OFFSET 8 +#define RTL8367D_SVLAN_PRIOIRTY_MASK 0x700 +#define RTL8367D_DOT1X_PRIORTY_OFFSET 0 +#define RTL8367D_DOT1X_PRIORTY_MASK 0x7 + +#define RTL8367D_REG_QOS_TRAP_PRIORITY1 0x0882 +#define RTL8367D_QOS_TRAP_PRIORITY1_OFFSET 0 +#define RTL8367D_QOS_TRAP_PRIORITY1_MASK 0x7 + +#define RTL8367D_REG_MAX_LENGTH_CFG 0x0883 +#define RTL8367D_MAX_LENGTH_GIGA_OFFSET 8 +#define RTL8367D_MAX_LENGTH_GIGA_MASK 0xFF00 +#define RTL8367D_MAX_LENGTH_10_100M_OFFSET 0 +#define RTL8367D_MAX_LENGTH_10_100M_MASK 0xFF + +#define RTL8367D_REG_QOS_INTERNAL_PRIORITY_DECISION2_CTRL0 0x0885 +#define RTL8367D_QOS_INTERNAL_PRIORITY_DECISION2_CTRL0_QOS_ACL_WEIGHT_OFFSET 8 +#define RTL8367D_QOS_INTERNAL_PRIORITY_DECISION2_CTRL0_QOS_ACL_WEIGHT_MASK 0x1F00 +#define RTL8367D_QOS_INTERNAL_PRIORITY_DECISION2_CTRL0_QOS_PORT_WEIGHT_OFFSET 0 +#define RTL8367D_QOS_INTERNAL_PRIORITY_DECISION2_CTRL0_QOS_PORT_WEIGHT_MASK 0x1F + +#define RTL8367D_REG_QOS_INTERNAL_PRIORITY_DECISION2_CTRL1 0x0886 +#define RTL8367D_QOS_INTERNAL_PRIORITY_DECISION2_CTRL1_QOS_DOT1Q_WEIGHT_OFFSET 8 +#define RTL8367D_QOS_INTERNAL_PRIORITY_DECISION2_CTRL1_QOS_DOT1Q_WEIGHT_MASK 0x1F00 +#define RTL8367D_QOS_INTERNAL_PRIORITY_DECISION2_CTRL1_QOS_DSCP_WEIGHT_OFFSET 0 +#define RTL8367D_QOS_INTERNAL_PRIORITY_DECISION2_CTRL1_QOS_DSCP_WEIGHT_MASK 0x1F + +#define RTL8367D_REG_QOS_INTERNAL_PRIORITY_DECISION2_CTRL2 0x0887 +#define RTL8367D_QOS_INTERNAL_PRIORITY_DECISION2_CTRL2_OFFSET 0 +#define RTL8367D_QOS_INTERNAL_PRIORITY_DECISION2_CTRL2_MASK 0x1F + +#define RTL8367D_REG_QOS_INTERNAL_PRIORITY_DECISION_IDX 0x0889 +#define RTL8367D_QOS_INTERNAL_PRIORITY_DECISION_IDX_OFFSET 0 +#define RTL8367D_QOS_INTERNAL_PRIORITY_DECISION_IDX_MASK 0xFF + +#define RTL8367D_REG_MAX_LEN_RX_TX_CFG0 0x088c +#define RTL8367D_MAX_LEN_RX_TX_CFG0_OFFSET 0 +#define RTL8367D_MAX_LEN_RX_TX_CFG0_MASK 0x3FFF + +#define RTL8367D_REG_MAX_LEN_RX_TX_CFG1 0x088d +#define RTL8367D_MAX_LEN_RX_TX_CFG1_OFFSET 0 +#define RTL8367D_MAX_LEN_RX_TX_CFG1_MASK 0x3FFF + +#define RTL8367D_REG_UNDA_FLOODING_PMSK 0x0890 +#define RTL8367D_UNDA_FLOODING_PMSK_OFFSET 0 +#define RTL8367D_UNDA_FLOODING_PMSK_MASK 0xFF + +#define RTL8367D_REG_UNMCAST_FLOADING_PMSK 0x0891 +#define RTL8367D_UNMCAST_FLOADING_PMSK_OFFSET 0 +#define RTL8367D_UNMCAST_FLOADING_PMSK_MASK 0xFF + +#define RTL8367D_REG_BCAST_FLOADING_PMSK 0x0892 +#define RTL8367D_BCAST_FLOADING_PMSK_OFFSET 0 +#define RTL8367D_BCAST_FLOADING_PMSK_MASK 0xFF + +#define RTL8367D_REG_PORT_ISOLATION_PORT0_MASK 0x08a2 +#define RTL8367D_PORT_ISOLATION_PORT0_MASK_OFFSET 0 +#define RTL8367D_PORT_ISOLATION_PORT0_MASK_MASK 0xFF + +#define RTL8367D_REG_PORT_ISOLATION_PORT1_MASK 0x08a3 +#define RTL8367D_PORT_ISOLATION_PORT1_MASK_OFFSET 0 +#define RTL8367D_PORT_ISOLATION_PORT1_MASK_MASK 0xFF + +#define RTL8367D_REG_PORT_ISOLATION_PORT2_MASK 0x08a4 +#define RTL8367D_PORT_ISOLATION_PORT2_MASK_OFFSET 0 +#define RTL8367D_PORT_ISOLATION_PORT2_MASK_MASK 0xFF + +#define RTL8367D_REG_PORT_ISOLATION_PORT3_MASK 0x08a5 +#define RTL8367D_PORT_ISOLATION_PORT3_MASK_OFFSET 0 +#define RTL8367D_PORT_ISOLATION_PORT3_MASK_MASK 0xFF + +#define RTL8367D_REG_PORT_ISOLATION_PORT4_MASK 0x08a6 +#define RTL8367D_PORT_ISOLATION_PORT4_MASK_OFFSET 0 +#define RTL8367D_PORT_ISOLATION_PORT4_MASK_MASK 0xFF + +#define RTL8367D_REG_PORT_ISOLATION_PORT5_MASK 0x08a7 +#define RTL8367D_PORT_ISOLATION_PORT5_MASK_OFFSET 0 +#define RTL8367D_PORT_ISOLATION_PORT5_MASK_MASK 0xFF + +#define RTL8367D_REG_PORT_ISOLATION_PORT6_MASK 0x08a8 +#define RTL8367D_PORT_ISOLATION_PORT6_MASK_OFFSET 0 +#define RTL8367D_PORT_ISOLATION_PORT6_MASK_MASK 0xFF + +#define RTL8367D_REG_PORT_ISOLATION_PORT7_MASK 0x08a9 +#define RTL8367D_PORT_ISOLATION_PORT7_MASK_OFFSET 0 +#define RTL8367D_PORT_ISOLATION_PORT7_MASK_MASK 0xFF + +#define RTL8367D_REG_FORCE_CTRL 0x08b4 +#define RTL8367D_FORCE_CTRL_OFFSET 0 +#define RTL8367D_FORCE_CTRL_MASK 0xFF + +#define RTL8367D_REG_FORCE_PORT0_MASK 0x08b5 +#define RTL8367D_FORCE_PORT0_MASK_OFFSET 0 +#define RTL8367D_FORCE_PORT0_MASK_MASK 0xFF + +#define RTL8367D_REG_FORCE_PORT1_MASK 0x08b6 +#define RTL8367D_FORCE_PORT1_MASK_OFFSET 0 +#define RTL8367D_FORCE_PORT1_MASK_MASK 0xFF + +#define RTL8367D_REG_FORCE_PORT2_MASK 0x08b7 +#define RTL8367D_FORCE_PORT2_MASK_OFFSET 0 +#define RTL8367D_FORCE_PORT2_MASK_MASK 0xFF + +#define RTL8367D_REG_FORCE_PORT3_MASK 0x08b8 +#define RTL8367D_FORCE_PORT3_MASK_OFFSET 0 +#define RTL8367D_FORCE_PORT3_MASK_MASK 0xFF + +#define RTL8367D_REG_FORCE_PORT4_MASK 0x08b9 +#define RTL8367D_FORCE_PORT4_MASK_OFFSET 0 +#define RTL8367D_FORCE_PORT4_MASK_MASK 0xFF + +#define RTL8367D_REG_FORCE_PORT5_MASK 0x08ba +#define RTL8367D_FORCE_PORT5_MASK_OFFSET 0 +#define RTL8367D_FORCE_PORT5_MASK_MASK 0xFF + +#define RTL8367D_REG_FORCE_PORT6_MASK 0x08bb +#define RTL8367D_FORCE_PORT6_MASK_OFFSET 0 +#define RTL8367D_FORCE_PORT6_MASK_MASK 0xFF + +#define RTL8367D_REG_FORCE_PORT7_MASK 0x08bc +#define RTL8367D_FORCE_PORT7_MASK_OFFSET 0 +#define RTL8367D_FORCE_PORT7_MASK_MASK 0xFF + +#define RTL8367D_REG_LUT_UNKN_SA_CTRL 0x08c0 +#define RTL8367D_LUT_UNKN_SA_CTRL_PORT7_ACT_OFFSET 14 +#define RTL8367D_LUT_UNKN_SA_CTRL_PORT7_ACT_MASK 0xC000 +#define RTL8367D_LUT_UNKN_SA_CTRL_PORT6_ACT_OFFSET 12 +#define RTL8367D_LUT_UNKN_SA_CTRL_PORT6_ACT_MASK 0x3000 +#define RTL8367D_LUT_UNKN_SA_CTRL_PORT5_ACT_OFFSET 10 +#define RTL8367D_LUT_UNKN_SA_CTRL_PORT5_ACT_MASK 0xC00 +#define RTL8367D_LUT_UNKN_SA_CTRL_PORT4_ACT_OFFSET 8 +#define RTL8367D_LUT_UNKN_SA_CTRL_PORT4_ACT_MASK 0x300 +#define RTL8367D_LUT_UNKN_SA_CTRL_PORT3_ACT_OFFSET 6 +#define RTL8367D_LUT_UNKN_SA_CTRL_PORT3_ACT_MASK 0xC0 +#define RTL8367D_LUT_UNKN_SA_CTRL_PORT2_ACT_OFFSET 4 +#define RTL8367D_LUT_UNKN_SA_CTRL_PORT2_ACT_MASK 0x30 +#define RTL8367D_LUT_UNKN_SA_CTRL_PORT1_ACT_OFFSET 2 +#define RTL8367D_LUT_UNKN_SA_CTRL_PORT1_ACT_MASK 0xC +#define RTL8367D_LUT_UNKN_SA_CTRL_PORT0_ACT_OFFSET 0 +#define RTL8367D_LUT_UNKN_SA_CTRL_PORT0_ACT_MASK 0x3 + +#define RTL8367D_REG_LUT_UNMATCHED_SA_CTRL 0x08c1 +#define RTL8367D_LUT_UNMATCHED_SA_CTRL_PORT7_ACT_OFFSET 14 +#define RTL8367D_LUT_UNMATCHED_SA_CTRL_PORT7_ACT_MASK 0xC000 +#define RTL8367D_LUT_UNMATCHED_SA_CTRL_PORT6_ACT_OFFSET 12 +#define RTL8367D_LUT_UNMATCHED_SA_CTRL_PORT6_ACT_MASK 0x3000 +#define RTL8367D_LUT_UNMATCHED_SA_CTRL_PORT5_ACT_OFFSET 10 +#define RTL8367D_LUT_UNMATCHED_SA_CTRL_PORT5_ACT_MASK 0xC00 +#define RTL8367D_LUT_UNMATCHED_SA_CTRL_PORT4_ACT_OFFSET 8 +#define RTL8367D_LUT_UNMATCHED_SA_CTRL_PORT4_ACT_MASK 0x300 +#define RTL8367D_LUT_UNMATCHED_SA_CTRL_PORT3_ACT_OFFSET 6 +#define RTL8367D_LUT_UNMATCHED_SA_CTRL_PORT3_ACT_MASK 0xC0 +#define RTL8367D_LUT_UNMATCHED_SA_CTRL_PORT2_ACT_OFFSET 4 +#define RTL8367D_LUT_UNMATCHED_SA_CTRL_PORT2_ACT_MASK 0x30 +#define RTL8367D_LUT_UNMATCHED_SA_CTRL_PORT1_ACT_OFFSET 2 +#define RTL8367D_LUT_UNMATCHED_SA_CTRL_PORT1_ACT_MASK 0xC +#define RTL8367D_LUT_UNMATCHED_SA_CTRL_PORT0_ACT_OFFSET 0 +#define RTL8367D_LUT_UNMATCHED_SA_CTRL_PORT0_ACT_MASK 0x3 + +#define RTL8367D_REG_SOURCE_PORT_PERMIT 0x08c5 +#define RTL8367D_SOURCE_PORT_PERMIT_OFFSET 0 +#define RTL8367D_SOURCE_PORT_PERMIT_MASK 0xFF + +#define RTL8367D_REG_IPMCAST_VLAN_LEAKY 0x08c6 +#define RTL8367D_IPMCAST_VLAN_LEAKY_OFFSET 0 +#define RTL8367D_IPMCAST_VLAN_LEAKY_MASK 0xFF + +#define RTL8367D_REG_IPMCAST_PORTISO_LEAKY 0x08c7 +#define RTL8367D_IPMCAST_PORTISO_LEAKY_OFFSET 0 +#define RTL8367D_IPMCAST_PORTISO_LEAKY_MASK 0xFF + +#define RTL8367D_REG_PORT_SECURITY_CTRL 0x08c8 +#define RTL8367D_PORT_SECURITY_CTRL_OFFSET 4 +#define RTL8367D_PORT_SECURITY_CTRL_MASK 0x30 + +#define RTL8367D_REG_UNKNOWN_IPV4_MULTICAST_CTRL0 0x08c9 +#define RTL8367D_PORT7_UNKNOWN_IP4_MCAST_OFFSET 14 +#define RTL8367D_PORT7_UNKNOWN_IP4_MCAST_MASK 0xC000 +#define RTL8367D_PORT6_UNKNOWN_IP4_MCAST_OFFSET 12 +#define RTL8367D_PORT6_UNKNOWN_IP4_MCAST_MASK 0x3000 +#define RTL8367D_PORT5_UNKNOWN_IP4_MCAST_OFFSET 10 +#define RTL8367D_PORT5_UNKNOWN_IP4_MCAST_MASK 0xC00 +#define RTL8367D_PORT4_UNKNOWN_IP4_MCAST_OFFSET 8 +#define RTL8367D_PORT4_UNKNOWN_IP4_MCAST_MASK 0x300 +#define RTL8367D_PORT3_UNKNOWN_IP4_MCAST_OFFSET 6 +#define RTL8367D_PORT3_UNKNOWN_IP4_MCAST_MASK 0xC0 +#define RTL8367D_PORT2_UNKNOWN_IP4_MCAST_OFFSET 4 +#define RTL8367D_PORT2_UNKNOWN_IP4_MCAST_MASK 0x30 +#define RTL8367D_PORT1_UNKNOWN_IP4_MCAST_OFFSET 2 +#define RTL8367D_PORT1_UNKNOWN_IP4_MCAST_MASK 0xC +#define RTL8367D_PORT0_UNKNOWN_IP4_MCAST_OFFSET 0 +#define RTL8367D_PORT0_UNKNOWN_IP4_MCAST_MASK 0x3 + +#define RTL8367D_REG_UNKNOWN_IPV6_MULTICAST_CTRL0 0x08cb +#define RTL8367D_PORT7_UNKNOWN_IP6_MCAST_OFFSET 14 +#define RTL8367D_PORT7_UNKNOWN_IP6_MCAST_MASK 0xC000 +#define RTL8367D_PORT6_UNKNOWN_IP6_MCAST_OFFSET 12 +#define RTL8367D_PORT6_UNKNOWN_IP6_MCAST_MASK 0x3000 +#define RTL8367D_PORT5_UNKNOWN_IP6_MCAST_OFFSET 10 +#define RTL8367D_PORT5_UNKNOWN_IP6_MCAST_MASK 0xC00 +#define RTL8367D_PORT4_UNKNOWN_IP6_MCAST_OFFSET 8 +#define RTL8367D_PORT4_UNKNOWN_IP6_MCAST_MASK 0x300 +#define RTL8367D_PORT3_UNKNOWN_IP6_MCAST_OFFSET 6 +#define RTL8367D_PORT3_UNKNOWN_IP6_MCAST_MASK 0xC0 +#define RTL8367D_PORT2_UNKNOWN_IP6_MCAST_OFFSET 4 +#define RTL8367D_PORT2_UNKNOWN_IP6_MCAST_MASK 0x30 +#define RTL8367D_PORT1_UNKNOWN_IP6_MCAST_OFFSET 2 +#define RTL8367D_PORT1_UNKNOWN_IP6_MCAST_MASK 0xC +#define RTL8367D_PORT0_UNKNOWN_IP6_MCAST_OFFSET 0 +#define RTL8367D_PORT0_UNKNOWN_IP6_MCAST_MASK 0x3 + +#define RTL8367D_REG_UNKNOWN_L2_MULTICAST_CTRL0 0x08cd +#define RTL8367D_PORT7_UNKNOWN_L2_MCAST_OFFSET 14 +#define RTL8367D_PORT7_UNKNOWN_L2_MCAST_MASK 0xC000 +#define RTL8367D_PORT6_UNKNOWN_L2_MCAST_OFFSET 12 +#define RTL8367D_PORT6_UNKNOWN_L2_MCAST_MASK 0x3000 +#define RTL8367D_PORT5_UNKNOWN_L2_MCAST_OFFSET 10 +#define RTL8367D_PORT5_UNKNOWN_L2_MCAST_MASK 0xC00 +#define RTL8367D_PORT4_UNKNOWN_L2_MCAST_OFFSET 8 +#define RTL8367D_PORT4_UNKNOWN_L2_MCAST_MASK 0x300 +#define RTL8367D_PORT3_UNKNOWN_L2_MCAST_OFFSET 6 +#define RTL8367D_PORT3_UNKNOWN_L2_MCAST_MASK 0xC0 +#define RTL8367D_PORT2_UNKNOWN_L2_MCAST_OFFSET 4 +#define RTL8367D_PORT2_UNKNOWN_L2_MCAST_MASK 0x30 +#define RTL8367D_PORT1_UNKNOWN_L2_MCAST_OFFSET 2 +#define RTL8367D_PORT1_UNKNOWN_L2_MCAST_MASK 0xC +#define RTL8367D_PORT0_UNKNOWN_L2_MCAST_OFFSET 0 +#define RTL8367D_PORT0_UNKNOWN_L2_MCAST_MASK 0x3 + +#define RTL8367D_REG_PORT_TRUNK_DROP_CTRL 0x08ce +#define RTL8367D_PORT_TRUNK_DROP_CTRL_OFFSET 0 +#define RTL8367D_PORT_TRUNK_DROP_CTRL_MASK 0x1 + +#define RTL8367D_REG_PORT_TRUNK_CTRL 0x08cf +#define RTL8367D_GROUP1_DPORT_HASH_OFFSET 15 +#define RTL8367D_GROUP1_DPORT_HASH_MASK 0x8000 +#define RTL8367D_GROUP1_SPORT_HASH_OFFSET 14 +#define RTL8367D_GROUP1_SPORT_HASH_MASK 0x4000 +#define RTL8367D_GROUP1_DIP_HASH_OFFSET 13 +#define RTL8367D_GROUP1_DIP_HASH_MASK 0x2000 +#define RTL8367D_GROUP1_SIP_HASH_OFFSET 12 +#define RTL8367D_GROUP1_SIP_HASH_MASK 0x1000 +#define RTL8367D_GROUP1_DMAC_HASH_OFFSET 11 +#define RTL8367D_GROUP1_DMAC_HASH_MASK 0x800 +#define RTL8367D_GROUP1_SMAC_HASH_OFFSET 10 +#define RTL8367D_GROUP1_SMAC_HASH_MASK 0x400 +#define RTL8367D_GROUP1_SPA_HASH_OFFSET 9 +#define RTL8367D_GROUP1_SPA_HASH_MASK 0x200 +#define RTL8367D_PORT_TRUNK_DUMB_OFFSET 8 +#define RTL8367D_PORT_TRUNK_DUMB_MASK 0x100 +#define RTL8367D_PORT_TRUNK_FLOOD_OFFSET 7 +#define RTL8367D_PORT_TRUNK_FLOOD_MASK 0x80 +#define RTL8367D_GROUP0_DPORT_HASH_OFFSET 6 +#define RTL8367D_GROUP0_DPORT_HASH_MASK 0x40 +#define RTL8367D_GROUP0_SPORT_HASH_OFFSET 5 +#define RTL8367D_GROUP0_SPORT_HASH_MASK 0x20 +#define RTL8367D_GROUP0_DIP_HASH_OFFSET 4 +#define RTL8367D_GROUP0_DIP_HASH_MASK 0x10 +#define RTL8367D_GROUP0_SIP_HASH_OFFSET 3 +#define RTL8367D_GROUP0_SIP_HASH_MASK 0x8 +#define RTL8367D_GROUP0_DMAC_HASH_OFFSET 2 +#define RTL8367D_GROUP0_DMAC_HASH_MASK 0x4 +#define RTL8367D_GROUP0_SMAC_HASH_OFFSET 1 +#define RTL8367D_GROUP0_SMAC_HASH_MASK 0x2 +#define RTL8367D_GROUP0_SPA_HASH_OFFSET 0 +#define RTL8367D_GROUP0_SPA_HASH_MASK 0x1 + +#define RTL8367D_REG_PORT_TRUNK_GROUP_MASK 0x08d0 +#define RTL8367D_PORT_TRUNK_GROUP1_MASK_OFFSET 4 +#define RTL8367D_PORT_TRUNK_GROUP1_MASK_MASK 0xF0 +#define RTL8367D_PORT_TRUNK_GROUP0_MASK_OFFSET 0 +#define RTL8367D_PORT_TRUNK_GROUP0_MASK_MASK 0xF + +#define RTL8367D_REG_PORT_TRUNK_FLOWCTRL 0x08d1 +#define RTL8367D_EN_FLOWCTRL_TG1_OFFSET 1 +#define RTL8367D_EN_FLOWCTRL_TG1_MASK 0x2 +#define RTL8367D_EN_FLOWCTRL_TG0_OFFSET 0 +#define RTL8367D_EN_FLOWCTRL_TG0_MASK 0x1 + +#define RTL8367D_REG_PORT_TRUNK_HASH_MAPPING_CTRL0 0x08d2 +#define RTL8367D_HASH7_OFFSET 14 +#define RTL8367D_HASH7_MASK 0xC000 +#define RTL8367D_HASH6_OFFSET 12 +#define RTL8367D_HASH6_MASK 0x3000 +#define RTL8367D_HASH5_OFFSET 10 +#define RTL8367D_HASH5_MASK 0xC00 +#define RTL8367D_HASH4_OFFSET 8 +#define RTL8367D_HASH4_MASK 0x300 +#define RTL8367D_HASH3_OFFSET 6 +#define RTL8367D_HASH3_MASK 0xC0 +#define RTL8367D_HASH2_OFFSET 4 +#define RTL8367D_HASH2_MASK 0x30 +#define RTL8367D_HASH1_OFFSET 2 +#define RTL8367D_HASH1_MASK 0xC +#define RTL8367D_HASH0_OFFSET 0 +#define RTL8367D_HASH0_MASK 0x3 + +#define RTL8367D_REG_PORT_TRUNK_HASH_MAPPING_CTRL1 0x08d3 +#define RTL8367D_HASH15_OFFSET 14 +#define RTL8367D_HASH15_MASK 0xC000 +#define RTL8367D_HASH14_OFFSET 12 +#define RTL8367D_HASH14_MASK 0x3000 +#define RTL8367D_HASH13_OFFSET 10 +#define RTL8367D_HASH13_MASK 0xC00 +#define RTL8367D_HASH12_OFFSET 8 +#define RTL8367D_HASH12_MASK 0x300 +#define RTL8367D_HASH11_OFFSET 6 +#define RTL8367D_HASH11_MASK 0xC0 +#define RTL8367D_HASH10_OFFSET 4 +#define RTL8367D_HASH10_MASK 0x30 +#define RTL8367D_HASH9_OFFSET 2 +#define RTL8367D_HASH9_MASK 0xC +#define RTL8367D_HASH8_OFFSET 0 +#define RTL8367D_HASH8_MASK 0x3 + +#define RTL8367D_REG_DOS_CFG 0x08d4 +#define RTL8367D_DROP_ICMPFRAGMENT_OFFSET 9 +#define RTL8367D_DROP_ICMPFRAGMENT_MASK 0x200 +#define RTL8367D_DROP_TCPFRAGERROR_OFFSET 8 +#define RTL8367D_DROP_TCPFRAGERROR_MASK 0x100 +#define RTL8367D_DROP_TCPSHORTHDR_OFFSET 7 +#define RTL8367D_DROP_TCPSHORTHDR_MASK 0x80 +#define RTL8367D_DROP_SYN1024_OFFSET 6 +#define RTL8367D_DROP_SYN1024_MASK 0x40 +#define RTL8367D_DROP_NULLSCAN_OFFSET 5 +#define RTL8367D_DROP_NULLSCAN_MASK 0x20 +#define RTL8367D_DROP_XMASCAN_OFFSET 4 +#define RTL8367D_DROP_XMASCAN_MASK 0x10 +#define RTL8367D_DROP_SYNFINSCAN_OFFSET 3 +#define RTL8367D_DROP_SYNFINSCAN_MASK 0x8 +#define RTL8367D_DROP_BLATATTACKS_OFFSET 2 +#define RTL8367D_DROP_BLATATTACKS_MASK 0x4 +#define RTL8367D_DROP_LANDATTACKS_OFFSET 1 +#define RTL8367D_DROP_LANDATTACKS_MASK 0x2 +#define RTL8367D_DROP_DAEQSA_OFFSET 0 +#define RTL8367D_DROP_DAEQSA_MASK 0x1 + +#define RTL8367D_REG_FPGA_VER_CEN 0x08e0 + +#define RTL8367D_REG_FPGA_TIME_CEN 0x08e1 + +#define RTL8367D_REG_FPGA_DATE_CEN 0x08e2 + +#define RTL8367D_REG_QOS_PORT_QUEUE_NUMBER_CTRL0 0x0900 +#define RTL8367D_PORT3_NUMBER_OFFSET 12 +#define RTL8367D_PORT3_NUMBER_MASK 0x7000 +#define RTL8367D_PORT2_NUMBER_OFFSET 8 +#define RTL8367D_PORT2_NUMBER_MASK 0x700 +#define RTL8367D_PORT1_NUMBER_OFFSET 4 +#define RTL8367D_PORT1_NUMBER_MASK 0x70 +#define RTL8367D_PORT0_NUMBER_OFFSET 0 +#define RTL8367D_PORT0_NUMBER_MASK 0x7 + +#define RTL8367D_REG_QOS_PORT_QUEUE_NUMBER_CTRL1 0x0901 +#define RTL8367D_PORT7_NUMBER_OFFSET 12 +#define RTL8367D_PORT7_NUMBER_MASK 0x7000 +#define RTL8367D_PORT6_NUMBER_OFFSET 8 +#define RTL8367D_PORT6_NUMBER_MASK 0x700 +#define RTL8367D_PORT5_NUMBER_OFFSET 4 +#define RTL8367D_PORT5_NUMBER_MASK 0x70 +#define RTL8367D_PORT4_NUMBER_OFFSET 0 +#define RTL8367D_PORT4_NUMBER_MASK 0x7 + +#define RTL8367D_REG_QOS_1Q_PRIORITY_TO_QID_CTRL0 0x0904 +#define RTL8367D_QOS_1Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_OFFSET 12 +#define RTL8367D_QOS_1Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_MASK 0x7000 +#define RTL8367D_QOS_1Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_OFFSET 8 +#define RTL8367D_QOS_1Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_MASK 0x700 +#define RTL8367D_QOS_1Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_OFFSET 4 +#define RTL8367D_QOS_1Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_MASK 0x70 +#define RTL8367D_QOS_1Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_OFFSET 0 +#define RTL8367D_QOS_1Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_MASK 0x7 + +#define RTL8367D_REG_QOS_1Q_PRIORITY_TO_QID_CTRL1 0x0905 +#define RTL8367D_QOS_1Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_OFFSET 12 +#define RTL8367D_QOS_1Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_MASK 0x7000 +#define RTL8367D_QOS_1Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_OFFSET 8 +#define RTL8367D_QOS_1Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_MASK 0x700 +#define RTL8367D_QOS_1Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_OFFSET 4 +#define RTL8367D_QOS_1Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_MASK 0x70 +#define RTL8367D_QOS_1Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_OFFSET 0 +#define RTL8367D_QOS_1Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_MASK 0x7 + +#define RTL8367D_REG_QOS_2Q_PRIORITY_TO_QID_CTRL0 0x0906 +#define RTL8367D_QOS_2Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_OFFSET 12 +#define RTL8367D_QOS_2Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_MASK 0x7000 +#define RTL8367D_QOS_2Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_OFFSET 8 +#define RTL8367D_QOS_2Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_MASK 0x700 +#define RTL8367D_QOS_2Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_OFFSET 4 +#define RTL8367D_QOS_2Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_MASK 0x70 +#define RTL8367D_QOS_2Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_OFFSET 0 +#define RTL8367D_QOS_2Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_MASK 0x7 + +#define RTL8367D_REG_QOS_2Q_PRIORITY_TO_QID_CTRL1 0x0907 +#define RTL8367D_QOS_2Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_OFFSET 12 +#define RTL8367D_QOS_2Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_MASK 0x7000 +#define RTL8367D_QOS_2Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_OFFSET 8 +#define RTL8367D_QOS_2Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_MASK 0x700 +#define RTL8367D_QOS_2Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_OFFSET 4 +#define RTL8367D_QOS_2Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_MASK 0x70 +#define RTL8367D_QOS_2Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_OFFSET 0 +#define RTL8367D_QOS_2Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_MASK 0x7 + +#define RTL8367D_REG_QOS_3Q_PRIORITY_TO_QID_CTRL0 0x0908 +#define RTL8367D_QOS_3Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_OFFSET 12 +#define RTL8367D_QOS_3Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_MASK 0x7000 +#define RTL8367D_QOS_3Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_OFFSET 8 +#define RTL8367D_QOS_3Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_MASK 0x700 +#define RTL8367D_QOS_3Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_OFFSET 4 +#define RTL8367D_QOS_3Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_MASK 0x70 +#define RTL8367D_QOS_3Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_OFFSET 0 +#define RTL8367D_QOS_3Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_MASK 0x7 + +#define RTL8367D_REG_QOS_3Q_PRIORITY_TO_QID_CTRL1 0x0909 +#define RTL8367D_QOS_3Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_OFFSET 12 +#define RTL8367D_QOS_3Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_MASK 0x7000 +#define RTL8367D_QOS_3Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_OFFSET 8 +#define RTL8367D_QOS_3Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_MASK 0x700 +#define RTL8367D_QOS_3Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_OFFSET 4 +#define RTL8367D_QOS_3Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_MASK 0x70 +#define RTL8367D_QOS_3Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_OFFSET 0 +#define RTL8367D_QOS_3Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_MASK 0x7 + +#define RTL8367D_REG_QOS_4Q_PRIORITY_TO_QID_CTRL0 0x090a +#define RTL8367D_QOS_4Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_OFFSET 12 +#define RTL8367D_QOS_4Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_MASK 0x7000 +#define RTL8367D_QOS_4Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_OFFSET 8 +#define RTL8367D_QOS_4Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_MASK 0x700 +#define RTL8367D_QOS_4Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_OFFSET 4 +#define RTL8367D_QOS_4Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_MASK 0x70 +#define RTL8367D_QOS_4Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_OFFSET 0 +#define RTL8367D_QOS_4Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_MASK 0x7 + +#define RTL8367D_REG_QOS_4Q_PRIORITY_TO_QID_CTRL1 0x090b +#define RTL8367D_QOS_4Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_OFFSET 12 +#define RTL8367D_QOS_4Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_MASK 0x7000 +#define RTL8367D_QOS_4Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_OFFSET 8 +#define RTL8367D_QOS_4Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_MASK 0x700 +#define RTL8367D_QOS_4Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_OFFSET 4 +#define RTL8367D_QOS_4Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_MASK 0x70 +#define RTL8367D_QOS_4Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_OFFSET 0 +#define RTL8367D_QOS_4Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_MASK 0x7 + +#define RTL8367D_REG_QOS_5Q_PRIORITY_TO_QID_CTRL0 0x090c +#define RTL8367D_QOS_5Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_OFFSET 12 +#define RTL8367D_QOS_5Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_MASK 0x7000 +#define RTL8367D_QOS_5Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_OFFSET 8 +#define RTL8367D_QOS_5Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_MASK 0x700 +#define RTL8367D_QOS_5Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_OFFSET 4 +#define RTL8367D_QOS_5Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_MASK 0x70 +#define RTL8367D_QOS_5Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_OFFSET 0 +#define RTL8367D_QOS_5Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_MASK 0x7 + +#define RTL8367D_REG_QOS_5Q_PRIORITY_TO_QID_CTRL1 0x090d +#define RTL8367D_QOS_5Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_OFFSET 12 +#define RTL8367D_QOS_5Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_MASK 0x7000 +#define RTL8367D_QOS_5Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_OFFSET 8 +#define RTL8367D_QOS_5Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_MASK 0x700 +#define RTL8367D_QOS_5Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_OFFSET 4 +#define RTL8367D_QOS_5Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_MASK 0x70 +#define RTL8367D_QOS_5Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_OFFSET 0 +#define RTL8367D_QOS_5Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_MASK 0x7 + +#define RTL8367D_REG_QOS_6Q_PRIORITY_TO_QID_CTRL0 0x090e +#define RTL8367D_QOS_6Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_OFFSET 12 +#define RTL8367D_QOS_6Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_MASK 0x7000 +#define RTL8367D_QOS_6Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_OFFSET 8 +#define RTL8367D_QOS_6Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_MASK 0x700 +#define RTL8367D_QOS_6Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_OFFSET 4 +#define RTL8367D_QOS_6Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_MASK 0x70 +#define RTL8367D_QOS_6Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_OFFSET 0 +#define RTL8367D_QOS_6Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_MASK 0x7 + +#define RTL8367D_REG_QOS_6Q_PRIORITY_TO_QID_CTRL1 0x090f +#define RTL8367D_QOS_6Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_OFFSET 12 +#define RTL8367D_QOS_6Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_MASK 0x7000 +#define RTL8367D_QOS_6Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_OFFSET 8 +#define RTL8367D_QOS_6Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_MASK 0x700 +#define RTL8367D_QOS_6Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_OFFSET 4 +#define RTL8367D_QOS_6Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_MASK 0x70 +#define RTL8367D_QOS_6Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_OFFSET 0 +#define RTL8367D_QOS_6Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_MASK 0x7 + +#define RTL8367D_REG_QOS_7Q_PRIORITY_TO_QID_CTRL0 0x0910 +#define RTL8367D_QOS_7Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_OFFSET 12 +#define RTL8367D_QOS_7Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_MASK 0x7000 +#define RTL8367D_QOS_7Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_OFFSET 8 +#define RTL8367D_QOS_7Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_MASK 0x700 +#define RTL8367D_QOS_7Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_OFFSET 4 +#define RTL8367D_QOS_7Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_MASK 0x70 +#define RTL8367D_QOS_7Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_OFFSET 0 +#define RTL8367D_QOS_7Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_MASK 0x7 + +#define RTL8367D_REG_QOS_7Q_PRIORITY_TO_QID_CTRL1 0x0911 +#define RTL8367D_QOS_7Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_OFFSET 12 +#define RTL8367D_QOS_7Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_MASK 0x7000 +#define RTL8367D_QOS_7Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_OFFSET 8 +#define RTL8367D_QOS_7Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_MASK 0x700 +#define RTL8367D_QOS_7Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_OFFSET 4 +#define RTL8367D_QOS_7Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_MASK 0x70 +#define RTL8367D_QOS_7Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_OFFSET 0 +#define RTL8367D_QOS_7Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_MASK 0x7 + +#define RTL8367D_REG_QOS_8Q_PRIORITY_TO_QID_CTRL0 0x0912 +#define RTL8367D_QOS_8Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_OFFSET 12 +#define RTL8367D_QOS_8Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_MASK 0x7000 +#define RTL8367D_QOS_8Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_OFFSET 8 +#define RTL8367D_QOS_8Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_MASK 0x700 +#define RTL8367D_QOS_8Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_OFFSET 4 +#define RTL8367D_QOS_8Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_MASK 0x70 +#define RTL8367D_QOS_8Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_OFFSET 0 +#define RTL8367D_QOS_8Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_MASK 0x7 + +#define RTL8367D_REG_QOS_8Q_PRIORITY_TO_QID_CTRL1 0x0913 +#define RTL8367D_QOS_8Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_OFFSET 12 +#define RTL8367D_QOS_8Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_MASK 0x7000 +#define RTL8367D_QOS_8Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_OFFSET 8 +#define RTL8367D_QOS_8Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_MASK 0x700 +#define RTL8367D_QOS_8Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_OFFSET 4 +#define RTL8367D_QOS_8Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_MASK 0x70 +#define RTL8367D_QOS_8Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_OFFSET 0 +#define RTL8367D_QOS_8Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_MASK 0x7 + +#define RTL8367D_REG_PORT_DEBUG_INFO_CTRL0 0x0917 +#define RTL8367D_PORT1_DEBUG_INFO_OFFSET 8 +#define RTL8367D_PORT1_DEBUG_INFO_MASK 0xFF00 +#define RTL8367D_PORT0_DEBUG_INFO_OFFSET 0 +#define RTL8367D_PORT0_DEBUG_INFO_MASK 0xFF + +#define RTL8367D_REG_PORT_DEBUG_INFO_CTRL1 0x0918 +#define RTL8367D_PORT3_DEBUG_INFO_OFFSET 8 +#define RTL8367D_PORT3_DEBUG_INFO_MASK 0xFF00 +#define RTL8367D_PORT2_DEBUG_INFO_OFFSET 0 +#define RTL8367D_PORT2_DEBUG_INFO_MASK 0xFF + +#define RTL8367D_REG_PORT_DEBUG_INFO_CTRL2 0x0919 +#define RTL8367D_PORT5_DEBUG_INFO_OFFSET 8 +#define RTL8367D_PORT5_DEBUG_INFO_MASK 0xFF00 +#define RTL8367D_PORT4_DEBUG_INFO_OFFSET 0 +#define RTL8367D_PORT4_DEBUG_INFO_MASK 0xFF + +#define RTL8367D_REG_PORT_DEBUG_INFO_CTRL3 0x091a +#define RTL8367D_PORT7_DEBUG_INFO_OFFSET 8 +#define RTL8367D_PORT7_DEBUG_INFO_MASK 0xFF00 +#define RTL8367D_PORT6_DEBUG_INFO_OFFSET 0 +#define RTL8367D_PORT6_DEBUG_INFO_MASK 0xFF + +#define RTL8367D_REG_PORT_DEBUG_INFO_CTRL4 0x091d +#define RTL8367D_PORT7_DEBUG_INDICATOR_OFFSET 14 +#define RTL8367D_PORT7_DEBUG_INDICATOR_MASK 0xC000 +#define RTL8367D_PORT6_DEBUG_INDICATOR_OFFSET 12 +#define RTL8367D_PORT6_DEBUG_INDICATOR_MASK 0x3000 +#define RTL8367D_PORT5_DEBUG_INDICATOR_OFFSET 10 +#define RTL8367D_PORT5_DEBUG_INDICATOR_MASK 0xC00 +#define RTL8367D_PORT4_DEBUG_INDICATOR_OFFSET 8 +#define RTL8367D_PORT4_DEBUG_INDICATOR_MASK 0x300 +#define RTL8367D_PORT3_DEBUG_INDICATOR_OFFSET 6 +#define RTL8367D_PORT3_DEBUG_INDICATOR_MASK 0xC0 +#define RTL8367D_PORT2_DEBUG_INDICATOR_OFFSET 4 +#define RTL8367D_PORT2_DEBUG_INDICATOR_MASK 0x30 +#define RTL8367D_PORT1_DEBUG_INDICATOR_OFFSET 2 +#define RTL8367D_PORT1_DEBUG_INDICATOR_MASK 0xC +#define RTL8367D_PORT0_DEBUG_INDICATOR_OFFSET 0 +#define RTL8367D_PORT0_DEBUG_INDICATOR_MASK 0x3 + +#define RTL8367D_REG_FLOWCRTL_EGRESS_QUEUE_ENABLE_CTRL0 0x0930 +#define RTL8367D_PORT1_QUEUE_MASK_OFFSET 8 +#define RTL8367D_PORT1_QUEUE_MASK_MASK 0xFF00 +#define RTL8367D_PORT0_QUEUE_MASK_OFFSET 0 +#define RTL8367D_PORT0_QUEUE_MASK_MASK 0xFF + +#define RTL8367D_REG_FLOWCRTL_EGRESS_QUEUE_ENABLE_CTRL1 0x0931 +#define RTL8367D_PORT3_QUEUE_MASK_OFFSET 8 +#define RTL8367D_PORT3_QUEUE_MASK_MASK 0xFF00 +#define RTL8367D_PORT2_QUEUE_MASK_OFFSET 0 +#define RTL8367D_PORT2_QUEUE_MASK_MASK 0xFF + +#define RTL8367D_REG_FLOWCRTL_EGRESS_QUEUE_ENABLE_CTRL2 0x0932 +#define RTL8367D_PORT5_QUEUE_MASK_OFFSET 8 +#define RTL8367D_PORT5_QUEUE_MASK_MASK 0xFF00 +#define RTL8367D_PORT4_QUEUE_MASK_OFFSET 0 +#define RTL8367D_PORT4_QUEUE_MASK_MASK 0xFF + +#define RTL8367D_REG_FLOWCRTL_EGRESS_QUEUE_ENABLE_CTRL3 0x0933 +#define RTL8367D_PORT7_QUEUE_MASK_OFFSET 8 +#define RTL8367D_PORT7_QUEUE_MASK_MASK 0xFF00 +#define RTL8367D_PORT6_QUEUE_MASK_OFFSET 0 +#define RTL8367D_PORT6_QUEUE_MASK_MASK 0xFF + +#define RTL8367D_REG_VLAN_EGRESS_KEEP_CTRL0 0x093b +#define RTL8367D_PORT1_VLAN_KEEP_MASK_OFFSET 8 +#define RTL8367D_PORT1_VLAN_KEEP_MASK_MASK 0xFF00 +#define RTL8367D_PORT0_VLAN_KEEP_MASK_OFFSET 0 +#define RTL8367D_PORT0_VLAN_KEEP_MASK_MASK 0xFF + +#define RTL8367D_REG_VLAN_EGRESS_KEEP_CTRL1 0x093c +#define RTL8367D_PORT3_VLAN_KEEP_MASK_OFFSET 8 +#define RTL8367D_PORT3_VLAN_KEEP_MASK_MASK 0xFF00 +#define RTL8367D_PORT2_VLAN_KEEP_MASK_OFFSET 0 +#define RTL8367D_PORT2_VLAN_KEEP_MASK_MASK 0xFF + +#define RTL8367D_REG_VLAN_EGRESS_KEEP_CTRL2 0x093d +#define RTL8367D_PORT5_VLAN_KEEP_MASK_OFFSET 8 +#define RTL8367D_PORT5_VLAN_KEEP_MASK_MASK 0xFF00 +#define RTL8367D_PORT4_VLAN_KEEP_MASK_OFFSET 0 +#define RTL8367D_PORT4_VLAN_KEEP_MASK_MASK 0xFF + +#define RTL8367D_REG_VLAN_EGRESS_KEEP_CTRL3 0x093e +#define RTL8367D_PORT7_VLAN_KEEP_MASK_OFFSET 8 +#define RTL8367D_PORT7_VLAN_KEEP_MASK_MASK 0xFF00 +#define RTL8367D_PORT6_VLAN_KEEP_MASK_OFFSET 0 +#define RTL8367D_PORT6_VLAN_KEEP_MASK_MASK 0xFF + +#define RTL8367D_REG_IPMC_GROUP_ENTRY0_H 0x0940 +#define RTL8367D_IPMC_GROUP_ENTRY0_H_OFFSET 0 +#define RTL8367D_IPMC_GROUP_ENTRY0_H_MASK 0xFFF + +#define RTL8367D_REG_IPMC_GROUP_ENTRY0_L 0x0941 + +#define RTL8367D_REG_IPMC_GROUP_ENTRY1_H 0x0942 +#define RTL8367D_IPMC_GROUP_ENTRY1_H_OFFSET 0 +#define RTL8367D_IPMC_GROUP_ENTRY1_H_MASK 0xFFF + +#define RTL8367D_REG_IPMC_GROUP_ENTRY1_L 0x0943 + +#define RTL8367D_REG_IPMC_GROUP_ENTRY2_H 0x0944 +#define RTL8367D_IPMC_GROUP_ENTRY2_H_OFFSET 0 +#define RTL8367D_IPMC_GROUP_ENTRY2_H_MASK 0xFFF + +#define RTL8367D_REG_IPMC_GROUP_ENTRY2_L 0x0945 + +#define RTL8367D_REG_IPMC_GROUP_ENTRY3_H 0x0946 +#define RTL8367D_IPMC_GROUP_ENTRY3_H_OFFSET 0 +#define RTL8367D_IPMC_GROUP_ENTRY3_H_MASK 0xFFF + +#define RTL8367D_REG_IPMC_GROUP_ENTRY3_L 0x0947 + +#define RTL8367D_REG_IPMC_GROUP_ENTRY4_H 0x0948 +#define RTL8367D_IPMC_GROUP_ENTRY4_H_OFFSET 0 +#define RTL8367D_IPMC_GROUP_ENTRY4_H_MASK 0xFFF + +#define RTL8367D_REG_IPMC_GROUP_ENTRY4_L 0x0949 + +#define RTL8367D_REG_IPMC_GROUP_ENTRY5_H 0x094a +#define RTL8367D_IPMC_GROUP_ENTRY5_H_OFFSET 0 +#define RTL8367D_IPMC_GROUP_ENTRY5_H_MASK 0xFFF + +#define RTL8367D_REG_IPMC_GROUP_ENTRY5_L 0x094b + +#define RTL8367D_REG_IPMC_GROUP_ENTRY6_H 0x094c +#define RTL8367D_IPMC_GROUP_ENTRY6_H_OFFSET 0 +#define RTL8367D_IPMC_GROUP_ENTRY6_H_MASK 0xFFF + +#define RTL8367D_REG_IPMC_GROUP_ENTRY6_L 0x094d + +#define RTL8367D_REG_IPMC_GROUP_ENTRY7_H 0x094e +#define RTL8367D_IPMC_GROUP_ENTRY7_H_OFFSET 0 +#define RTL8367D_IPMC_GROUP_ENTRY7_H_MASK 0xFFF + +#define RTL8367D_REG_IPMC_GROUP_ENTRY7_L 0x094f + +#define RTL8367D_REG_IPMC_GROUP_ENTRY8_H 0x0950 +#define RTL8367D_IPMC_GROUP_ENTRY8_H_OFFSET 0 +#define RTL8367D_IPMC_GROUP_ENTRY8_H_MASK 0xFFF + +#define RTL8367D_REG_IPMC_GROUP_ENTRY8_L 0x0951 + +#define RTL8367D_REG_IPMC_GROUP_ENTRY9_H 0x0952 +#define RTL8367D_IPMC_GROUP_ENTRY9_H_OFFSET 0 +#define RTL8367D_IPMC_GROUP_ENTRY9_H_MASK 0xFFF + +#define RTL8367D_REG_IPMC_GROUP_ENTRY9_L 0x0953 + +#define RTL8367D_REG_IPMC_GROUP_ENTRY10_H 0x0954 +#define RTL8367D_IPMC_GROUP_ENTRY10_H_OFFSET 0 +#define RTL8367D_IPMC_GROUP_ENTRY10_H_MASK 0xFFF + +#define RTL8367D_REG_IPMC_GROUP_ENTRY10_L 0x0955 + +#define RTL8367D_REG_IPMC_GROUP_ENTRY11_H 0x0956 +#define RTL8367D_IPMC_GROUP_ENTRY11_H_OFFSET 0 +#define RTL8367D_IPMC_GROUP_ENTRY11_H_MASK 0xFFF + +#define RTL8367D_REG_IPMC_GROUP_ENTRY11_L 0x0957 + +#define RTL8367D_REG_IPMC_GROUP_ENTRY12_H 0x0958 +#define RTL8367D_IPMC_GROUP_ENTRY12_H_OFFSET 0 +#define RTL8367D_IPMC_GROUP_ENTRY12_H_MASK 0xFFF + +#define RTL8367D_REG_IPMC_GROUP_ENTRY12_L 0x0959 + +#define RTL8367D_REG_IPMC_GROUP_ENTRY13_H 0x095a +#define RTL8367D_IPMC_GROUP_ENTRY13_H_OFFSET 0 +#define RTL8367D_IPMC_GROUP_ENTRY13_H_MASK 0xFFF + +#define RTL8367D_REG_IPMC_GROUP_ENTRY13_L 0x095b + +#define RTL8367D_REG_IPMC_GROUP_ENTRY14_H 0x095c +#define RTL8367D_IPMC_GROUP_ENTRY14_H_OFFSET 0 +#define RTL8367D_IPMC_GROUP_ENTRY14_H_MASK 0xFFF + +#define RTL8367D_REG_IPMC_GROUP_ENTRY14_L 0x095d + +#define RTL8367D_REG_IPMC_GROUP_ENTRY15_H 0x095e +#define RTL8367D_IPMC_GROUP_ENTRY15_H_OFFSET 0 +#define RTL8367D_IPMC_GROUP_ENTRY15_H_MASK 0xFFF + +#define RTL8367D_REG_IPMC_GROUP_ENTRY15_L 0x095f + +#define RTL8367D_REG_IPMC_GROUP_ENTRY16_H 0x0960 +#define RTL8367D_IPMC_GROUP_ENTRY16_H_OFFSET 0 +#define RTL8367D_IPMC_GROUP_ENTRY16_H_MASK 0xFFF + +#define RTL8367D_REG_IPMC_GROUP_ENTRY16_L 0x0961 + +#define RTL8367D_REG_IPMC_GROUP_ENTRY17_H 0x0962 +#define RTL8367D_IPMC_GROUP_ENTRY17_H_OFFSET 0 +#define RTL8367D_IPMC_GROUP_ENTRY17_H_MASK 0xFFF + +#define RTL8367D_REG_IPMC_GROUP_ENTRY17_L 0x0963 + +#define RTL8367D_REG_IPMC_GROUP_ENTRY18_H 0x0964 +#define RTL8367D_IPMC_GROUP_ENTRY18_H_OFFSET 0 +#define RTL8367D_IPMC_GROUP_ENTRY18_H_MASK 0xFFF + +#define RTL8367D_REG_IPMC_GROUP_ENTRY18_L 0x0965 + +#define RTL8367D_REG_IPMC_GROUP_ENTRY19_H 0x0966 +#define RTL8367D_IPMC_GROUP_ENTRY19_H_OFFSET 0 +#define RTL8367D_IPMC_GROUP_ENTRY19_H_MASK 0xFFF + +#define RTL8367D_REG_IPMC_GROUP_ENTRY19_L 0x0967 + +#define RTL8367D_REG_IPMC_GROUP_ENTRY20_H 0x0968 +#define RTL8367D_IPMC_GROUP_ENTRY20_H_OFFSET 0 +#define RTL8367D_IPMC_GROUP_ENTRY20_H_MASK 0xFFF + +#define RTL8367D_REG_IPMC_GROUP_ENTRY20_L 0x0969 + +#define RTL8367D_REG_IPMC_GROUP_ENTRY21_H 0x096a +#define RTL8367D_IPMC_GROUP_ENTRY21_H_OFFSET 0 +#define RTL8367D_IPMC_GROUP_ENTRY21_H_MASK 0xFFF + +#define RTL8367D_REG_IPMC_GROUP_ENTRY21_L 0x096b + +#define RTL8367D_REG_IPMC_GROUP_ENTRY22_H 0x096c +#define RTL8367D_IPMC_GROUP_ENTRY22_H_OFFSET 0 +#define RTL8367D_IPMC_GROUP_ENTRY22_H_MASK 0xFFF + +#define RTL8367D_REG_IPMC_GROUP_ENTRY22_L 0x096d + +#define RTL8367D_REG_IPMC_GROUP_ENTRY23_H 0x096e +#define RTL8367D_IPMC_GROUP_ENTRY23_H_OFFSET 0 +#define RTL8367D_IPMC_GROUP_ENTRY23_H_MASK 0xFFF + +#define RTL8367D_REG_IPMC_GROUP_ENTRY23_L 0x096f + +#define RTL8367D_REG_IPMC_GROUP_ENTRY24_H 0x0970 +#define RTL8367D_IPMC_GROUP_ENTRY24_H_OFFSET 0 +#define RTL8367D_IPMC_GROUP_ENTRY24_H_MASK 0xFFF + +#define RTL8367D_REG_IPMC_GROUP_ENTRY24_L 0x0971 + +#define RTL8367D_REG_IPMC_GROUP_ENTRY25_H 0x0972 +#define RTL8367D_IPMC_GROUP_ENTRY25_H_OFFSET 0 +#define RTL8367D_IPMC_GROUP_ENTRY25_H_MASK 0xFFF + +#define RTL8367D_REG_IPMC_GROUP_ENTRY25_L 0x0973 + +#define RTL8367D_REG_IPMC_GROUP_ENTRY26_H 0x0974 +#define RTL8367D_IPMC_GROUP_ENTRY26_H_OFFSET 0 +#define RTL8367D_IPMC_GROUP_ENTRY26_H_MASK 0xFFF + +#define RTL8367D_REG_IPMC_GROUP_ENTRY26_L 0x0975 + +#define RTL8367D_REG_IPMC_GROUP_ENTRY27_H 0x0976 +#define RTL8367D_IPMC_GROUP_ENTRY27_H_OFFSET 0 +#define RTL8367D_IPMC_GROUP_ENTRY27_H_MASK 0xFFF + +#define RTL8367D_REG_IPMC_GROUP_ENTRY27_L 0x0977 + +#define RTL8367D_REG_IPMC_GROUP_ENTRY28_H 0x0978 +#define RTL8367D_IPMC_GROUP_ENTRY28_H_OFFSET 0 +#define RTL8367D_IPMC_GROUP_ENTRY28_H_MASK 0xFFF + +#define RTL8367D_REG_IPMC_GROUP_ENTRY28_L 0x0979 + +#define RTL8367D_REG_IPMC_GROUP_ENTRY29_H 0x097a +#define RTL8367D_IPMC_GROUP_ENTRY29_H_OFFSET 0 +#define RTL8367D_IPMC_GROUP_ENTRY29_H_MASK 0xFFF + +#define RTL8367D_REG_IPMC_GROUP_ENTRY29_L 0x097b + +#define RTL8367D_REG_IPMC_GROUP_ENTRY30_H 0x097c +#define RTL8367D_IPMC_GROUP_ENTRY30_H_OFFSET 0 +#define RTL8367D_IPMC_GROUP_ENTRY30_H_MASK 0xFFF + +#define RTL8367D_REG_IPMC_GROUP_ENTRY30_L 0x097d + +#define RTL8367D_REG_IPMC_GROUP_ENTRY31_H 0x097e +#define RTL8367D_IPMC_GROUP_ENTRY31_H_OFFSET 0 +#define RTL8367D_IPMC_GROUP_ENTRY31_H_MASK 0xFFF + +#define RTL8367D_REG_IPMC_GROUP_ENTRY31_L 0x097f + +#define RTL8367D_REG_IPMC_GROUP_ENTRY32_H 0x0980 +#define RTL8367D_IPMC_GROUP_ENTRY32_H_OFFSET 0 +#define RTL8367D_IPMC_GROUP_ENTRY32_H_MASK 0xFFF + +#define RTL8367D_REG_IPMC_GROUP_ENTRY32_L 0x0981 + +#define RTL8367D_REG_IPMC_GROUP_ENTRY33_H 0x0982 +#define RTL8367D_IPMC_GROUP_ENTRY33_H_OFFSET 0 +#define RTL8367D_IPMC_GROUP_ENTRY33_H_MASK 0xFFF + +#define RTL8367D_REG_IPMC_GROUP_ENTRY33_L 0x0983 + +#define RTL8367D_REG_IPMC_GROUP_ENTRY34_H 0x0984 +#define RTL8367D_IPMC_GROUP_ENTRY34_H_OFFSET 0 +#define RTL8367D_IPMC_GROUP_ENTRY34_H_MASK 0xFFF + +#define RTL8367D_REG_IPMC_GROUP_ENTRY34_L 0x0985 + +#define RTL8367D_REG_IPMC_GROUP_ENTRY35_H 0x0986 +#define RTL8367D_IPMC_GROUP_ENTRY35_H_OFFSET 0 +#define RTL8367D_IPMC_GROUP_ENTRY35_H_MASK 0xFFF + +#define RTL8367D_REG_IPMC_GROUP_ENTRY35_L 0x0987 + +#define RTL8367D_REG_IPMC_GROUP_ENTRY36_H 0x0988 +#define RTL8367D_IPMC_GROUP_ENTRY36_H_OFFSET 0 +#define RTL8367D_IPMC_GROUP_ENTRY36_H_MASK 0xFFF + +#define RTL8367D_REG_IPMC_GROUP_ENTRY36_L 0x0989 + +#define RTL8367D_REG_IPMC_GROUP_ENTRY37_H 0x098a +#define RTL8367D_IPMC_GROUP_ENTRY37_H_OFFSET 0 +#define RTL8367D_IPMC_GROUP_ENTRY37_H_MASK 0xFFF + +#define RTL8367D_REG_IPMC_GROUP_ENTRY37_L 0x098b + +#define RTL8367D_REG_IPMC_GROUP_ENTRY38_H 0x098c +#define RTL8367D_IPMC_GROUP_ENTRY38_H_OFFSET 0 +#define RTL8367D_IPMC_GROUP_ENTRY38_H_MASK 0xFFF + +#define RTL8367D_REG_IPMC_GROUP_ENTRY38_L 0x098d + +#define RTL8367D_REG_IPMC_GROUP_ENTRY39_H 0x098e +#define RTL8367D_IPMC_GROUP_ENTRY39_H_OFFSET 0 +#define RTL8367D_IPMC_GROUP_ENTRY39_H_MASK 0xFFF + +#define RTL8367D_REG_IPMC_GROUP_ENTRY39_L 0x098f + +#define RTL8367D_REG_IPMC_GROUP_ENTRY40_H 0x0990 +#define RTL8367D_IPMC_GROUP_ENTRY40_H_OFFSET 0 +#define RTL8367D_IPMC_GROUP_ENTRY40_H_MASK 0xFFF + +#define RTL8367D_REG_IPMC_GROUP_ENTRY40_L 0x0991 + +#define RTL8367D_REG_IPMC_GROUP_ENTRY41_H 0x0992 +#define RTL8367D_IPMC_GROUP_ENTRY41_H_OFFSET 0 +#define RTL8367D_IPMC_GROUP_ENTRY41_H_MASK 0xFFF + +#define RTL8367D_REG_IPMC_GROUP_ENTRY41_L 0x0993 + +#define RTL8367D_REG_IPMC_GROUP_ENTRY42_H 0x0994 +#define RTL8367D_IPMC_GROUP_ENTRY42_H_OFFSET 0 +#define RTL8367D_IPMC_GROUP_ENTRY42_H_MASK 0xFFF + +#define RTL8367D_REG_IPMC_GROUP_ENTRY42_L 0x0995 + +#define RTL8367D_REG_IPMC_GROUP_ENTRY43_H 0x0996 +#define RTL8367D_IPMC_GROUP_ENTRY43_H_OFFSET 0 +#define RTL8367D_IPMC_GROUP_ENTRY43_H_MASK 0xFFF + +#define RTL8367D_REG_IPMC_GROUP_ENTRY43_L 0x0997 + +#define RTL8367D_REG_IPMC_GROUP_ENTRY44_H 0x0998 +#define RTL8367D_IPMC_GROUP_ENTRY44_H_OFFSET 0 +#define RTL8367D_IPMC_GROUP_ENTRY44_H_MASK 0xFFF + +#define RTL8367D_REG_IPMC_GROUP_ENTRY44_L 0x0999 + +#define RTL8367D_REG_IPMC_GROUP_ENTRY45_H 0x099a +#define RTL8367D_IPMC_GROUP_ENTRY45_H_OFFSET 0 +#define RTL8367D_IPMC_GROUP_ENTRY45_H_MASK 0xFFF + +#define RTL8367D_REG_IPMC_GROUP_ENTRY45_L 0x099b + +#define RTL8367D_REG_IPMC_GROUP_ENTRY46_H 0x099c +#define RTL8367D_IPMC_GROUP_ENTRY46_H_OFFSET 0 +#define RTL8367D_IPMC_GROUP_ENTRY46_H_MASK 0xFFF + +#define RTL8367D_REG_IPMC_GROUP_ENTRY46_L 0x099d + +#define RTL8367D_REG_IPMC_GROUP_ENTRY47_H 0x099e +#define RTL8367D_IPMC_GROUP_ENTRY47_H_OFFSET 0 +#define RTL8367D_IPMC_GROUP_ENTRY47_H_MASK 0xFFF + +#define RTL8367D_REG_IPMC_GROUP_ENTRY47_L 0x099f + +#define RTL8367D_REG_IPMC_GROUP_ENTRY48_H 0x09a0 +#define RTL8367D_IPMC_GROUP_ENTRY48_H_OFFSET 0 +#define RTL8367D_IPMC_GROUP_ENTRY48_H_MASK 0xFFF + +#define RTL8367D_REG_IPMC_GROUP_ENTRY48_L 0x09a1 + +#define RTL8367D_REG_IPMC_GROUP_ENTRY49_H 0x09a2 +#define RTL8367D_IPMC_GROUP_ENTRY49_H_OFFSET 0 +#define RTL8367D_IPMC_GROUP_ENTRY49_H_MASK 0xFFF + +#define RTL8367D_REG_IPMC_GROUP_ENTRY49_L 0x09a3 + +#define RTL8367D_REG_IPMC_GROUP_ENTRY50_H 0x09a4 +#define RTL8367D_IPMC_GROUP_ENTRY50_H_OFFSET 0 +#define RTL8367D_IPMC_GROUP_ENTRY50_H_MASK 0xFFF + +#define RTL8367D_REG_IPMC_GROUP_ENTRY50_L 0x09a5 + +#define RTL8367D_REG_IPMC_GROUP_ENTRY51_H 0x09a6 +#define RTL8367D_IPMC_GROUP_ENTRY51_H_OFFSET 0 +#define RTL8367D_IPMC_GROUP_ENTRY51_H_MASK 0xFFF + +#define RTL8367D_REG_IPMC_GROUP_ENTRY51_L 0x09a7 + +#define RTL8367D_REG_IPMC_GROUP_ENTRY52_H 0x09a8 +#define RTL8367D_IPMC_GROUP_ENTRY52_H_OFFSET 0 +#define RTL8367D_IPMC_GROUP_ENTRY52_H_MASK 0xFFF + +#define RTL8367D_REG_IPMC_GROUP_ENTRY52_L 0x09a9 + +#define RTL8367D_REG_IPMC_GROUP_ENTRY53_H 0x09aa +#define RTL8367D_IPMC_GROUP_ENTRY53_H_OFFSET 0 +#define RTL8367D_IPMC_GROUP_ENTRY53_H_MASK 0xFFF + +#define RTL8367D_REG_IPMC_GROUP_ENTRY53_L 0x09ab + +#define RTL8367D_REG_IPMC_GROUP_ENTRY54_H 0x09ac +#define RTL8367D_IPMC_GROUP_ENTRY54_H_OFFSET 0 +#define RTL8367D_IPMC_GROUP_ENTRY54_H_MASK 0xFFF + +#define RTL8367D_REG_IPMC_GROUP_ENTRY54_L 0x09ad + +#define RTL8367D_REG_IPMC_GROUP_ENTRY55_H 0x09ae +#define RTL8367D_IPMC_GROUP_ENTRY55_H_OFFSET 0 +#define RTL8367D_IPMC_GROUP_ENTRY55_H_MASK 0xFFF + +#define RTL8367D_REG_IPMC_GROUP_ENTRY55_L 0x09af + +#define RTL8367D_REG_IPMC_GROUP_ENTRY56_H 0x09b0 +#define RTL8367D_IPMC_GROUP_ENTRY56_H_OFFSET 0 +#define RTL8367D_IPMC_GROUP_ENTRY56_H_MASK 0xFFF + +#define RTL8367D_REG_IPMC_GROUP_ENTRY56_L 0x09b1 + +#define RTL8367D_REG_IPMC_GROUP_ENTRY57_H 0x09b2 +#define RTL8367D_IPMC_GROUP_ENTRY57_H_OFFSET 0 +#define RTL8367D_IPMC_GROUP_ENTRY57_H_MASK 0xFFF + +#define RTL8367D_REG_IPMC_GROUP_ENTRY57_L 0x09b3 + +#define RTL8367D_REG_IPMC_GROUP_ENTRY58_H 0x09b4 +#define RTL8367D_IPMC_GROUP_ENTRY58_H_OFFSET 0 +#define RTL8367D_IPMC_GROUP_ENTRY58_H_MASK 0xFFF + +#define RTL8367D_REG_IPMC_GROUP_ENTRY58_L 0x09b5 + +#define RTL8367D_REG_IPMC_GROUP_ENTRY59_H 0x09b6 +#define RTL8367D_IPMC_GROUP_ENTRY59_H_OFFSET 0 +#define RTL8367D_IPMC_GROUP_ENTRY59_H_MASK 0xFFF + +#define RTL8367D_REG_IPMC_GROUP_ENTRY59_L 0x09b7 + +#define RTL8367D_REG_IPMC_GROUP_ENTRY60_H 0x09b8 +#define RTL8367D_IPMC_GROUP_ENTRY60_H_OFFSET 0 +#define RTL8367D_IPMC_GROUP_ENTRY60_H_MASK 0xFFF + +#define RTL8367D_REG_IPMC_GROUP_ENTRY60_L 0x09b9 + +#define RTL8367D_REG_IPMC_GROUP_ENTRY61_H 0x09ba +#define RTL8367D_IPMC_GROUP_ENTRY61_H_OFFSET 0 +#define RTL8367D_IPMC_GROUP_ENTRY61_H_MASK 0xFFF + +#define RTL8367D_REG_IPMC_GROUP_ENTRY61_L 0x09bb + +#define RTL8367D_REG_IPMC_GROUP_ENTRY62_H 0x09bc +#define RTL8367D_IPMC_GROUP_ENTRY62_H_OFFSET 0 +#define RTL8367D_IPMC_GROUP_ENTRY62_H_MASK 0xFFF + +#define RTL8367D_REG_IPMC_GROUP_ENTRY62_L 0x09bd + +#define RTL8367D_REG_IPMC_GROUP_ENTRY63_H 0x09be +#define RTL8367D_IPMC_GROUP_ENTRY63_H_OFFSET 0 +#define RTL8367D_IPMC_GROUP_ENTRY63_H_MASK 0xFFF + +#define RTL8367D_REG_IPMC_GROUP_ENTRY63_L 0x09bf + +#define RTL8367D_REG_UNKNOWN_UNICAST_DA_PORT_BEHAVE 0x09C0 +#define RTL8367D_Port7_ACTION_OFFSET 14 +#define RTL8367D_Port7_ACTION_MASK 0xC000 +#define RTL8367D_Port6_ACTION_OFFSET 12 +#define RTL8367D_Port6_ACTION_MASK 0x3000 +#define RTL8367D_Port5_ACTION_OFFSET 10 +#define RTL8367D_Port5_ACTION_MASK 0xC00 +#define RTL8367D_Port4_ACTION_OFFSET 8 +#define RTL8367D_Port4_ACTION_MASK 0x300 +#define RTL8367D_Port3_ACTION_OFFSET 6 +#define RTL8367D_Port3_ACTION_MASK 0xC0 +#define RTL8367D_Port2_ACTION_OFFSET 4 +#define RTL8367D_Port2_ACTION_MASK 0x30 +#define RTL8367D_Port1_ACTION_OFFSET 2 +#define RTL8367D_Port1_ACTION_MASK 0xC +#define RTL8367D_Port0_ACTION_OFFSET 0 +#define RTL8367D_Port0_ACTION_MASK 0x3 + +#define RTL8367D_REG_MIRROR_OVERRIDE_CFG 0x09C1 +#define RTL8367D_MIRROR_ACL_OVERRIDE_EN_OFFSET 2 +#define RTL8367D_MIRROR_ACL_OVERRIDE_EN_MASK 0x4 +#define RTL8367D_MIRROR_TX_OVERRIDE_EN_OFFSET 1 +#define RTL8367D_MIRROR_TX_OVERRIDE_EN_MASK 0x2 +#define RTL8367D_MIRROR_RX_OVERRIDE_EN_OFFSET 0 +#define RTL8367D_MIRROR_RX_OVERRIDE_EN_MASK 0x1 + +#define RTL8367D_REG_VLAN_EGRESS_TRANS_CTRL0 0x09D0 +#define RTL8367D_VLAN_EGRESS_TRANS_CTRL0_OFFSET 0 +#define RTL8367D_VLAN_EGRESS_TRANS_CTRL0_MASK 0xFF + +#define RTL8367D_REG_VLAN_EGRESS_TRANS_CTRL1 0x09D1 +#define RTL8367D_VLAN_EGRESS_TRANS_CTRL1_OFFSET 0 +#define RTL8367D_VLAN_EGRESS_TRANS_CTRL1_MASK 0xFF + +#define RTL8367D_REG_VLAN_EGRESS_TRANS_CTRL2 0x09D2 +#define RTL8367D_VLAN_EGRESS_TRANS_CTRL2_OFFSET 0 +#define RTL8367D_VLAN_EGRESS_TRANS_CTRL2_MASK 0xFF + +#define RTL8367D_REG_VLAN_EGRESS_TRANS_CTRL3 0x09D3 +#define RTL8367D_VLAN_EGRESS_TRANS_CTRL3_OFFSET 0 +#define RTL8367D_VLAN_EGRESS_TRANS_CTRL3_MASK 0xFF + +#define RTL8367D_REG_VLAN_EGRESS_TRANS_CTRL4 0x09D4 +#define RTL8367D_VLAN_EGRESS_TRANS_CTRL4_OFFSET 0 +#define RTL8367D_VLAN_EGRESS_TRANS_CTRL4_MASK 0xFF + +#define RTL8367D_REG_VLAN_EGRESS_TRANS_CTRL5 0x09D5 +#define RTL8367D_VLAN_EGRESS_TRANS_CTRL5_OFFSET 0 +#define RTL8367D_VLAN_EGRESS_TRANS_CTRL5_MASK 0xFF + +#define RTL8367D_REG_VLAN_EGRESS_TRANS_CTRL6 0x09D6 +#define RTL8367D_VLAN_EGRESS_TRANS_CTRL6_OFFSET 0 +#define RTL8367D_VLAN_EGRESS_TRANS_CTRL6_MASK 0xFF + +#define RTL8367D_REG_VLAN_EGRESS_TRANS_CTRL7 0x09D7 +#define RTL8367D_VLAN_EGRESS_TRANS_CTRL7_OFFSET 0 +#define RTL8367D_VLAN_EGRESS_TRANS_CTRL7_MASK 0xFF + +#define RTL8367D_REG_MIRROR_CTRL2 0x09DA +#define RTL8367D_MIRROR_REALKEEP_EN_OFFSET 4 +#define RTL8367D_MIRROR_REALKEEP_EN_MASK 0x10 +#define RTL8367D_MIRROR_RX_ISOLATION_LEAKY_OFFSET 3 +#define RTL8367D_MIRROR_RX_ISOLATION_LEAKY_MASK 0x8 +#define RTL8367D_MIRROR_TX_ISOLATION_LEAKY_OFFSET 2 +#define RTL8367D_MIRROR_TX_ISOLATION_LEAKY_MASK 0x4 +#define RTL8367D_MIRROR_RX_VLAN_LEAKY_OFFSET 1 +#define RTL8367D_MIRROR_RX_VLAN_LEAKY_MASK 0x2 +#define RTL8367D_MIRROR_TX_VLAN_LEAKY_OFFSET 0 +#define RTL8367D_MIRROR_TX_VLAN_LEAKY_MASK 0x1 + +#define RTL8367D_REG_OUTPUT_DROP_CFG 0x09DB +#define RTL8367D_ENABLE_BC_OFFSET 12 +#define RTL8367D_ENABLE_BC_MASK 0x1000 +#define RTL8367D_ENABLE_MC_OFFSET 11 +#define RTL8367D_ENABLE_MC_MASK 0x800 +#define RTL8367D_ENABLE_UC_OFFSET 10 +#define RTL8367D_ENABLE_UC_MASK 0x400 +#define RTL8367D_ENABLE_PMASK_OFFSET 0 +#define RTL8367D_ENABLE_PMASK_MASK 0xFF + +#define RTL8367D_REG_RMK_CFG_SEL_CTRL 0x09DF +#define RTL8367D_RMK_1Q_CFG_SEL_OFFSET 2 +#define RTL8367D_RMK_1Q_CFG_SEL_MASK 0x4 +#define RTL8367D_RMK_DSCP_CFG_SEL_OFFSET 0 +#define RTL8367D_RMK_DSCP_CFG_SEL_MASK 0x1 + +/* (16'h0a00)l2_reg */ + +#define RTL8367D_REG_VLAN_MSTI0_CTRL0 0x0a00 +#define RTL8367D_VLAN_MSTI0_CTRL0_PORT7_STATE_OFFSET 14 +#define RTL8367D_VLAN_MSTI0_CTRL0_PORT7_STATE_MASK 0xC000 +#define RTL8367D_VLAN_MSTI0_CTRL0_PORT6_STATE_OFFSET 12 +#define RTL8367D_VLAN_MSTI0_CTRL0_PORT6_STATE_MASK 0x3000 +#define RTL8367D_VLAN_MSTI0_CTRL0_PORT5_STATE_OFFSET 10 +#define RTL8367D_VLAN_MSTI0_CTRL0_PORT5_STATE_MASK 0xC00 +#define RTL8367D_VLAN_MSTI0_CTRL0_PORT4_STATE_OFFSET 8 +#define RTL8367D_VLAN_MSTI0_CTRL0_PORT4_STATE_MASK 0x300 +#define RTL8367D_VLAN_MSTI0_CTRL0_PORT3_STATE_OFFSET 6 +#define RTL8367D_VLAN_MSTI0_CTRL0_PORT3_STATE_MASK 0xC0 +#define RTL8367D_VLAN_MSTI0_CTRL0_PORT2_STATE_OFFSET 4 +#define RTL8367D_VLAN_MSTI0_CTRL0_PORT2_STATE_MASK 0x30 +#define RTL8367D_VLAN_MSTI0_CTRL0_PORT1_STATE_OFFSET 2 +#define RTL8367D_VLAN_MSTI0_CTRL0_PORT1_STATE_MASK 0xC +#define RTL8367D_VLAN_MSTI0_CTRL0_PORT0_STATE_OFFSET 0 +#define RTL8367D_VLAN_MSTI0_CTRL0_PORT0_STATE_MASK 0x3 + +#define RTL8367D_REG_VLAN_MSTI1_CTRL0 0x0a02 +#define RTL8367D_VLAN_MSTI1_CTRL0_PORT7_STATE_OFFSET 14 +#define RTL8367D_VLAN_MSTI1_CTRL0_PORT7_STATE_MASK 0xC000 +#define RTL8367D_VLAN_MSTI1_CTRL0_PORT6_STATE_OFFSET 12 +#define RTL8367D_VLAN_MSTI1_CTRL0_PORT6_STATE_MASK 0x3000 +#define RTL8367D_VLAN_MSTI1_CTRL0_PORT5_STATE_OFFSET 10 +#define RTL8367D_VLAN_MSTI1_CTRL0_PORT5_STATE_MASK 0xC00 +#define RTL8367D_VLAN_MSTI1_CTRL0_PORT4_STATE_OFFSET 8 +#define RTL8367D_VLAN_MSTI1_CTRL0_PORT4_STATE_MASK 0x300 +#define RTL8367D_VLAN_MSTI1_CTRL0_PORT3_STATE_OFFSET 6 +#define RTL8367D_VLAN_MSTI1_CTRL0_PORT3_STATE_MASK 0xC0 +#define RTL8367D_VLAN_MSTI1_CTRL0_PORT2_STATE_OFFSET 4 +#define RTL8367D_VLAN_MSTI1_CTRL0_PORT2_STATE_MASK 0x30 +#define RTL8367D_VLAN_MSTI1_CTRL0_PORT1_STATE_OFFSET 2 +#define RTL8367D_VLAN_MSTI1_CTRL0_PORT1_STATE_MASK 0xC +#define RTL8367D_VLAN_MSTI1_CTRL0_PORT0_STATE_OFFSET 0 +#define RTL8367D_VLAN_MSTI1_CTRL0_PORT0_STATE_MASK 0x3 + +#define RTL8367D_REG_VLAN_MSTI2_CTRL0 0x0a04 +#define RTL8367D_VLAN_MSTI2_CTRL0_PORT7_STATE_OFFSET 14 +#define RTL8367D_VLAN_MSTI2_CTRL0_PORT7_STATE_MASK 0xC000 +#define RTL8367D_VLAN_MSTI2_CTRL0_PORT6_STATE_OFFSET 12 +#define RTL8367D_VLAN_MSTI2_CTRL0_PORT6_STATE_MASK 0x3000 +#define RTL8367D_VLAN_MSTI2_CTRL0_PORT5_STATE_OFFSET 10 +#define RTL8367D_VLAN_MSTI2_CTRL0_PORT5_STATE_MASK 0xC00 +#define RTL8367D_VLAN_MSTI2_CTRL0_PORT4_STATE_OFFSET 8 +#define RTL8367D_VLAN_MSTI2_CTRL0_PORT4_STATE_MASK 0x300 +#define RTL8367D_VLAN_MSTI2_CTRL0_PORT3_STATE_OFFSET 6 +#define RTL8367D_VLAN_MSTI2_CTRL0_PORT3_STATE_MASK 0xC0 +#define RTL8367D_VLAN_MSTI2_CTRL0_PORT2_STATE_OFFSET 4 +#define RTL8367D_VLAN_MSTI2_CTRL0_PORT2_STATE_MASK 0x30 +#define RTL8367D_VLAN_MSTI2_CTRL0_PORT1_STATE_OFFSET 2 +#define RTL8367D_VLAN_MSTI2_CTRL0_PORT1_STATE_MASK 0xC +#define RTL8367D_VLAN_MSTI2_CTRL0_PORT0_STATE_OFFSET 0 +#define RTL8367D_VLAN_MSTI2_CTRL0_PORT0_STATE_MASK 0x3 + +#define RTL8367D_REG_VLAN_MSTI3_CTRL0 0x0a06 +#define RTL8367D_VLAN_MSTI3_CTRL0_PORT7_STATE_OFFSET 14 +#define RTL8367D_VLAN_MSTI3_CTRL0_PORT7_STATE_MASK 0xC000 +#define RTL8367D_VLAN_MSTI3_CTRL0_PORT6_STATE_OFFSET 12 +#define RTL8367D_VLAN_MSTI3_CTRL0_PORT6_STATE_MASK 0x3000 +#define RTL8367D_VLAN_MSTI3_CTRL0_PORT5_STATE_OFFSET 10 +#define RTL8367D_VLAN_MSTI3_CTRL0_PORT5_STATE_MASK 0xC00 +#define RTL8367D_VLAN_MSTI3_CTRL0_PORT4_STATE_OFFSET 8 +#define RTL8367D_VLAN_MSTI3_CTRL0_PORT4_STATE_MASK 0x300 +#define RTL8367D_VLAN_MSTI3_CTRL0_PORT3_STATE_OFFSET 6 +#define RTL8367D_VLAN_MSTI3_CTRL0_PORT3_STATE_MASK 0xC0 +#define RTL8367D_VLAN_MSTI3_CTRL0_PORT2_STATE_OFFSET 4 +#define RTL8367D_VLAN_MSTI3_CTRL0_PORT2_STATE_MASK 0x30 +#define RTL8367D_VLAN_MSTI3_CTRL0_PORT1_STATE_OFFSET 2 +#define RTL8367D_VLAN_MSTI3_CTRL0_PORT1_STATE_MASK 0xC +#define RTL8367D_VLAN_MSTI3_CTRL0_PORT0_STATE_OFFSET 0 +#define RTL8367D_VLAN_MSTI3_CTRL0_PORT0_STATE_MASK 0x3 + +#define RTL8367D_REG_LOOKUP_HIT_ISO_ACT 0x0a10 +#define RTL8367D_LOOKUP_HIT_ISO_ACT_OFFSET 0 +#define RTL8367D_LOOKUP_HIT_ISO_ACT_MASK 0x1 + +#define RTL8367D_REG_LUT_PORT0_LEARN_LIMITNO 0x0a20 +#define RTL8367D_LUT_PORT0_LEARN_LIMITNO_OFFSET 0 +#define RTL8367D_LUT_PORT0_LEARN_LIMITNO_MASK 0xFFF + +#define RTL8367D_REG_LUT_PORT1_LEARN_LIMITNO 0x0a21 +#define RTL8367D_LUT_PORT1_LEARN_LIMITNO_OFFSET 0 +#define RTL8367D_LUT_PORT1_LEARN_LIMITNO_MASK 0xFFF + +#define RTL8367D_REG_LUT_PORT2_LEARN_LIMITNO 0x0a22 +#define RTL8367D_LUT_PORT2_LEARN_LIMITNO_OFFSET 0 +#define RTL8367D_LUT_PORT2_LEARN_LIMITNO_MASK 0xFFF + +#define RTL8367D_REG_LUT_PORT3_LEARN_LIMITNO 0x0a23 +#define RTL8367D_LUT_PORT3_LEARN_LIMITNO_OFFSET 0 +#define RTL8367D_LUT_PORT3_LEARN_LIMITNO_MASK 0xFFF + +#define RTL8367D_REG_LUT_PORT4_LEARN_LIMITNO 0x0a24 +#define RTL8367D_LUT_PORT4_LEARN_LIMITNO_OFFSET 0 +#define RTL8367D_LUT_PORT4_LEARN_LIMITNO_MASK 0xFFF + +#define RTL8367D_REG_LUT_PORT5_LEARN_LIMITNO 0x0a25 +#define RTL8367D_LUT_PORT5_LEARN_LIMITNO_OFFSET 0 +#define RTL8367D_LUT_PORT5_LEARN_LIMITNO_MASK 0xFFF + +#define RTL8367D_REG_LUT_PORT6_LEARN_LIMITNO 0x0a26 +#define RTL8367D_LUT_PORT6_LEARN_LIMITNO_OFFSET 0 +#define RTL8367D_LUT_PORT6_LEARN_LIMITNO_MASK 0xFFF + +#define RTL8367D_REG_LUT_PORT7_LEARN_LIMITNO 0x0a27 +#define RTL8367D_LUT_PORT7_LEARN_LIMITNO_OFFSET 0 +#define RTL8367D_LUT_PORT7_LEARN_LIMITNO_MASK 0xFFF + +#define RTL8367D_REG_LUT_SYS_LEARN_LIMITNO 0x0a28 +#define RTL8367D_LUT_SYS_LEARN_LIMITNO_OFFSET 0 +#define RTL8367D_LUT_SYS_LEARN_LIMITNO_MASK 0xFFF + +#define RTL8367D_REG_LUT_LRN_SYS_LMT_CTRL 0x0a29 +#define RTL8367D_LUT_SYSTEM_LEARN_OVER_ACT_OFFSET 10 +#define RTL8367D_LUT_SYSTEM_LEARN_OVER_ACT_MASK 0xC00 +#define RTL8367D_LUT_SYSTEM_LEARN_PMASK_OFFSET 0 +#define RTL8367D_LUT_SYSTEM_LEARN_PMASK_MASK 0xFF + +#define RTL8367D_REG_LUT_CFG 0x0a30 +#define RTL8367D_BCAM_DISABLE_OFFSET 6 +#define RTL8367D_BCAM_DISABLE_MASK 0x40 +#define RTL8367D_LINKDOWN_AGEOUT_OFFSET 5 +#define RTL8367D_LINKDOWN_AGEOUT_MASK 0x20 +#define RTL8367D_LUT_IPMC_HASH_OFFSET 4 +#define RTL8367D_LUT_IPMC_HASH_MASK 0x10 +#define RTL8367D_LUT_CFG_AGE_TIMER_OFFSET 0 +#define RTL8367D_LUT_CFG_AGE_TIMER_MASK 0x7 + +#define RTL8367D_REG_LUT_AGEOUT_CTRL 0x0a31 +#define RTL8367D_LUT_AGEOUT_CTRL_OFFSET 0 +#define RTL8367D_LUT_AGEOUT_CTRL_MASK 0xFF + +#define RTL8367D_REG_LUT_CFG2 0x0a32 + +#define RTL8367D_REG_FORCE_FLUSH 0x0a36 +#define RTL8367D_BUSY_STATUS_OFFSET 8 +#define RTL8367D_BUSY_STATUS_MASK 0xFF00 +#define RTL8367D_FORCE_FLUSH_PORTMASK_OFFSET 0 +#define RTL8367D_FORCE_FLUSH_PORTMASK_MASK 0xFF + +#define RTL8367D_REG_L2_FLUSH_CTRL1 0x0a37 +#define RTL8367D_LUT_FLUSH_FID_OFFSET 12 +#define RTL8367D_LUT_FLUSH_FID_MASK 0x3000 +#define RTL8367D_LUT_FLUSH_VID_OFFSET 0 +#define RTL8367D_LUT_FLUSH_VID_MASK 0xFFF + +#define RTL8367D_REG_L2_FLUSH_CTRL2 0x0a38 +#define RTL8367D_LUT_FLUSH_TYPE_OFFSET 2 +#define RTL8367D_LUT_FLUSH_TYPE_MASK 0x4 +#define RTL8367D_LUT_FLUSH_MODE_OFFSET 0 +#define RTL8367D_LUT_FLUSH_MODE_MASK 0x3 + +#define RTL8367D_REG_L2_FLUSH_CTRL3 0x0a39 +#define RTL8367D_L2_FLUSH_CTRL3_OFFSET 0 +#define RTL8367D_L2_FLUSH_CTRL3_MASK 0x1 + +#define RTL8367D_REG_FLUSH_STATUS 0x0a3f +#define RTL8367D_FLUSH_STATUS_OFFSET 0 +#define RTL8367D_FLUSH_STATUS_MASK 0x1 + +#define RTL8367D_REG_STORM_BCAST 0x0a40 +#define RTL8367D_STORM_BCAST_OFFSET 0 +#define RTL8367D_STORM_BCAST_MASK 0xFF + +#define RTL8367D_REG_STORM_MCAST 0x0a41 +#define RTL8367D_STORM_MCAST_OFFSET 0 +#define RTL8367D_STORM_MCAST_MASK 0xFF + +#define RTL8367D_REG_STORM_UNKOWN_UCAST 0x0a42 +#define RTL8367D_STORM_UNKOWN_UCAST_OFFSET 0 +#define RTL8367D_STORM_UNKOWN_UCAST_MASK 0xFF + +#define RTL8367D_REG_STORM_UNKOWN_MCAST 0x0a43 +#define RTL8367D_STORM_UNKOWN_MCAST_OFFSET 0 +#define RTL8367D_STORM_UNKOWN_MCAST_MASK 0xFF + +#define RTL8367D_REG_STORM_BCAST_METER_CTRL0 0x0a44 +#define RTL8367D_STORM_BCAST_METER_CTRL0_PORT1_METERIDX_OFFSET 8 +#define RTL8367D_STORM_BCAST_METER_CTRL0_PORT1_METERIDX_MASK 0x3F00 +#define RTL8367D_STORM_BCAST_METER_CTRL0_PORT0_METERIDX_OFFSET 0 +#define RTL8367D_STORM_BCAST_METER_CTRL0_PORT0_METERIDX_MASK 0x3F + +#define RTL8367D_REG_STORM_BCAST_METER_CTRL1 0x0a45 +#define RTL8367D_STORM_BCAST_METER_CTRL1_PORT3_METERIDX_OFFSET 8 +#define RTL8367D_STORM_BCAST_METER_CTRL1_PORT3_METERIDX_MASK 0x3F00 +#define RTL8367D_STORM_BCAST_METER_CTRL1_PORT2_METERIDX_OFFSET 0 +#define RTL8367D_STORM_BCAST_METER_CTRL1_PORT2_METERIDX_MASK 0x3F + +#define RTL8367D_REG_STORM_BCAST_METER_CTRL2 0x0a46 +#define RTL8367D_STORM_BCAST_METER_CTRL2_PORT5_METERIDX_OFFSET 8 +#define RTL8367D_STORM_BCAST_METER_CTRL2_PORT5_METERIDX_MASK 0x3F00 +#define RTL8367D_STORM_BCAST_METER_CTRL2_PORT4_METERIDX_OFFSET 0 +#define RTL8367D_STORM_BCAST_METER_CTRL2_PORT4_METERIDX_MASK 0x3F + +#define RTL8367D_REG_STORM_BCAST_METER_CTRL3 0x0a47 +#define RTL8367D_STORM_BCAST_METER_CTRL3_PORT7_METERIDX_OFFSET 8 +#define RTL8367D_STORM_BCAST_METER_CTRL3_PORT7_METERIDX_MASK 0x3F00 +#define RTL8367D_STORM_BCAST_METER_CTRL3_PORT6_METERIDX_OFFSET 0 +#define RTL8367D_STORM_BCAST_METER_CTRL3_PORT6_METERIDX_MASK 0x3F + +#define RTL8367D_REG_STORM_MCAST_METER_CTRL0 0x0a4c +#define RTL8367D_STORM_MCAST_METER_CTRL0_PORT1_METERIDX_OFFSET 8 +#define RTL8367D_STORM_MCAST_METER_CTRL0_PORT1_METERIDX_MASK 0x3F00 +#define RTL8367D_STORM_MCAST_METER_CTRL0_PORT0_METERIDX_OFFSET 0 +#define RTL8367D_STORM_MCAST_METER_CTRL0_PORT0_METERIDX_MASK 0x3F + +#define RTL8367D_REG_STORM_MCAST_METER_CTRL1 0x0a4d +#define RTL8367D_STORM_MCAST_METER_CTRL1_PORT3_METERIDX_OFFSET 8 +#define RTL8367D_STORM_MCAST_METER_CTRL1_PORT3_METERIDX_MASK 0x3F00 +#define RTL8367D_STORM_MCAST_METER_CTRL1_PORT2_METERIDX_OFFSET 0 +#define RTL8367D_STORM_MCAST_METER_CTRL1_PORT2_METERIDX_MASK 0x3F + +#define RTL8367D_REG_STORM_MCAST_METER_CTRL2 0x0a4e +#define RTL8367D_STORM_MCAST_METER_CTRL2_PORT5_METERIDX_OFFSET 8 +#define RTL8367D_STORM_MCAST_METER_CTRL2_PORT5_METERIDX_MASK 0x3F00 +#define RTL8367D_STORM_MCAST_METER_CTRL2_PORT4_METERIDX_OFFSET 0 +#define RTL8367D_STORM_MCAST_METER_CTRL2_PORT4_METERIDX_MASK 0x3F + +#define RTL8367D_REG_STORM_MCAST_METER_CTRL3 0x0a4f +#define RTL8367D_STORM_MCAST_METER_CTRL3_PORT7_METERIDX_OFFSET 8 +#define RTL8367D_STORM_MCAST_METER_CTRL3_PORT7_METERIDX_MASK 0x3F00 +#define RTL8367D_STORM_MCAST_METER_CTRL3_PORT6_METERIDX_OFFSET 0 +#define RTL8367D_STORM_MCAST_METER_CTRL3_PORT6_METERIDX_MASK 0x3F + +#define RTL8367D_REG_STORM_UNDA_METER_CTRL0 0x0a54 +#define RTL8367D_STORM_UNDA_METER_CTRL0_PORT1_METERIDX_OFFSET 8 +#define RTL8367D_STORM_UNDA_METER_CTRL0_PORT1_METERIDX_MASK 0x3F00 +#define RTL8367D_STORM_UNDA_METER_CTRL0_PORT0_METERIDX_OFFSET 0 +#define RTL8367D_STORM_UNDA_METER_CTRL0_PORT0_METERIDX_MASK 0x3F + +#define RTL8367D_REG_STORM_UNDA_METER_CTRL1 0x0a55 +#define RTL8367D_STORM_UNDA_METER_CTRL1_PORT3_METERIDX_OFFSET 8 +#define RTL8367D_STORM_UNDA_METER_CTRL1_PORT3_METERIDX_MASK 0x3F00 +#define RTL8367D_STORM_UNDA_METER_CTRL1_PORT2_METERIDX_OFFSET 0 +#define RTL8367D_STORM_UNDA_METER_CTRL1_PORT2_METERIDX_MASK 0x3F + +#define RTL8367D_REG_STORM_UNDA_METER_CTRL2 0x0a56 +#define RTL8367D_STORM_UNDA_METER_CTRL2_PORT5_METERIDX_OFFSET 8 +#define RTL8367D_STORM_UNDA_METER_CTRL2_PORT5_METERIDX_MASK 0x3F00 +#define RTL8367D_STORM_UNDA_METER_CTRL2_PORT4_METERIDX_OFFSET 0 +#define RTL8367D_STORM_UNDA_METER_CTRL2_PORT4_METERIDX_MASK 0x3F + +#define RTL8367D_REG_STORM_UNDA_METER_CTRL3 0x0a57 +#define RTL8367D_STORM_UNDA_METER_CTRL3_PORT7_METERIDX_OFFSET 8 +#define RTL8367D_STORM_UNDA_METER_CTRL3_PORT7_METERIDX_MASK 0x3F00 +#define RTL8367D_STORM_UNDA_METER_CTRL3_PORT6_METERIDX_OFFSET 0 +#define RTL8367D_STORM_UNDA_METER_CTRL3_PORT6_METERIDX_MASK 0x3F + +#define RTL8367D_REG_STORM_UNMC_METER_CTRL0 0x0a5c +#define RTL8367D_STORM_UNMC_METER_CTRL0_PORT1_METERIDX_OFFSET 8 +#define RTL8367D_STORM_UNMC_METER_CTRL0_PORT1_METERIDX_MASK 0x3F00 +#define RTL8367D_STORM_UNMC_METER_CTRL0_PORT0_METERIDX_OFFSET 0 +#define RTL8367D_STORM_UNMC_METER_CTRL0_PORT0_METERIDX_MASK 0x3F + +#define RTL8367D_REG_STORM_UNMC_METER_CTRL1 0x0a5d +#define RTL8367D_STORM_UNMC_METER_CTRL1_PORT3_METERIDX_OFFSET 8 +#define RTL8367D_STORM_UNMC_METER_CTRL1_PORT3_METERIDX_MASK 0x3F00 +#define RTL8367D_STORM_UNMC_METER_CTRL1_PORT2_METERIDX_OFFSET 0 +#define RTL8367D_STORM_UNMC_METER_CTRL1_PORT2_METERIDX_MASK 0x3F + +#define RTL8367D_REG_STORM_UNMC_METER_CTRL2 0x0a5e +#define RTL8367D_STORM_UNMC_METER_CTRL2_PORT5_METERIDX_OFFSET 8 +#define RTL8367D_STORM_UNMC_METER_CTRL2_PORT5_METERIDX_MASK 0x3F00 +#define RTL8367D_STORM_UNMC_METER_CTRL2_PORT4_METERIDX_OFFSET 0 +#define RTL8367D_STORM_UNMC_METER_CTRL2_PORT4_METERIDX_MASK 0x3F + +#define RTL8367D_REG_STORM_UNMC_METER_CTRL3 0x0a5f +#define RTL8367D_STORM_UNMC_METER_CTRL3_PORT7_METERIDX_OFFSET 8 +#define RTL8367D_STORM_UNMC_METER_CTRL3_PORT7_METERIDX_MASK 0x3F00 +#define RTL8367D_STORM_UNMC_METER_CTRL3_PORT6_METERIDX_OFFSET 0 +#define RTL8367D_STORM_UNMC_METER_CTRL3_PORT6_METERIDX_MASK 0x3F + +#define RTL8367D_REG_STORM_EXT_CFG 0x0a60 +#define RTL8367D_STORM_UNKNOWN_MCAST_EXT_EN_OFFSET 13 +#define RTL8367D_STORM_UNKNOWN_MCAST_EXT_EN_MASK 0x2000 +#define RTL8367D_STORM_UNKNOWN_UCAST_EXT_EN_OFFSET 12 +#define RTL8367D_STORM_UNKNOWN_UCAST_EXT_EN_MASK 0x1000 +#define RTL8367D_STORM_MCAST_EXT_EN_OFFSET 11 +#define RTL8367D_STORM_MCAST_EXT_EN_MASK 0x800 +#define RTL8367D_STORM_BCAST_EXT_EN_OFFSET 10 +#define RTL8367D_STORM_BCAST_EXT_EN_MASK 0x400 +#define RTL8367D_STORM_EXT_EN_PORTMASK_OFFSET 0 +#define RTL8367D_STORM_EXT_EN_PORTMASK_MASK 0xFF + +#define RTL8367D_REG_STORM_EXT_MTRIDX_CFG0 0x0a61 +#define RTL8367D_MC_STORM_EXT_METERIDX_OFFSET 8 +#define RTL8367D_MC_STORM_EXT_METERIDX_MASK 0x3F00 +#define RTL8367D_BC_STORM_EXT_METERIDX_OFFSET 0 +#define RTL8367D_BC_STORM_EXT_METERIDX_MASK 0x3F + +#define RTL8367D_REG_STORM_EXT_MTRIDX_CFG1 0x0a62 +#define RTL8367D_UNMC_STORM_EXT_METERIDX_OFFSET 8 +#define RTL8367D_UNMC_STORM_EXT_METERIDX_MASK 0x3F00 +#define RTL8367D_UNUC_STORM_EXT_METERIDX_OFFSET 0 +#define RTL8367D_UNUC_STORM_EXT_METERIDX_MASK 0x3F + +#define RTL8367D_REG_DOT1X_PORT_ENABLE 0x0a80 +#define RTL8367D_DOT1X_PORT_ENABLE_OFFSET 0 +#define RTL8367D_DOT1X_PORT_ENABLE_MASK 0xFF + +#define RTL8367D_REG_DOT1X_PORT_AUTH 0x0a82 +#define RTL8367D_DOT1X_PORT_AUTH_OFFSET 0 +#define RTL8367D_DOT1X_PORT_AUTH_MASK 0xFF + +#define RTL8367D_REG_DOT1X_PORT_OPDIR 0x0a83 +#define RTL8367D_DOT1X_PORT_OPDIR_OFFSET 0 +#define RTL8367D_DOT1X_PORT_OPDIR_MASK 0xFF + +#define RTL8367D_REG_DOT1X_UNAUTH_ACT_W0 0x0a84 +#define RTL8367D_DOT1X_PORT7_UNAUTHBH_OFFSET 7 +#define RTL8367D_DOT1X_PORT7_UNAUTHBH_MASK 0x80 +#define RTL8367D_DOT1X_PORT6_UNAUTHBH_OFFSET 6 +#define RTL8367D_DOT1X_PORT6_UNAUTHBH_MASK 0x40 +#define RTL8367D_DOT1X_PORT5_UNAUTHBH_OFFSET 5 +#define RTL8367D_DOT1X_PORT5_UNAUTHBH_MASK 0x20 +#define RTL8367D_DOT1X_PORT4_UNAUTHBH_OFFSET 4 +#define RTL8367D_DOT1X_PORT4_UNAUTHBH_MASK 0x10 +#define RTL8367D_DOT1X_PORT3_UNAUTHBH_OFFSET 3 +#define RTL8367D_DOT1X_PORT3_UNAUTHBH_MASK 0x8 +#define RTL8367D_DOT1X_PORT2_UNAUTHBH_OFFSET 2 +#define RTL8367D_DOT1X_PORT2_UNAUTHBH_MASK 0x4 +#define RTL8367D_DOT1X_PORT1_UNAUTHBH_OFFSET 1 +#define RTL8367D_DOT1X_PORT1_UNAUTHBH_MASK 0x2 +#define RTL8367D_DOT1X_PORT0_UNAUTHBH_OFFSET 0 +#define RTL8367D_DOT1X_PORT0_UNAUTHBH_MASK 0x1 + +#define RTL8367D_REG_L2_LRN_CNT_CTRL0 0x0a87 +#define RTL8367D_L2_LRN_CNT_CTRL0_OFFSET 0 +#define RTL8367D_L2_LRN_CNT_CTRL0_MASK 0xFFF + +#define RTL8367D_REG_L2_LRN_CNT_CTRL1 0x0a88 +#define RTL8367D_L2_LRN_CNT_CTRL1_OFFSET 0 +#define RTL8367D_L2_LRN_CNT_CTRL1_MASK 0xFFF + +#define RTL8367D_REG_L2_LRN_CNT_CTRL2 0x0a89 +#define RTL8367D_L2_LRN_CNT_CTRL2_OFFSET 0 +#define RTL8367D_L2_LRN_CNT_CTRL2_MASK 0xFFF + +#define RTL8367D_REG_L2_LRN_CNT_CTRL3 0x0a8a +#define RTL8367D_L2_LRN_CNT_CTRL3_OFFSET 0 +#define RTL8367D_L2_LRN_CNT_CTRL3_MASK 0xFFF + +#define RTL8367D_REG_L2_LRN_CNT_CTRL4 0x0a8b +#define RTL8367D_L2_LRN_CNT_CTRL4_OFFSET 0 +#define RTL8367D_L2_LRN_CNT_CTRL4_MASK 0xFFF + +#define RTL8367D_REG_L2_LRN_CNT_CTRL5 0x0a8c +#define RTL8367D_L2_LRN_CNT_CTRL5_OFFSET 0 +#define RTL8367D_L2_LRN_CNT_CTRL5_MASK 0xFFF + +#define RTL8367D_REG_L2_LRN_CNT_CTRL6 0x0a8d +#define RTL8367D_L2_LRN_CNT_CTRL6_OFFSET 0 +#define RTL8367D_L2_LRN_CNT_CTRL6_MASK 0xFFF + +#define RTL8367D_REG_L2_LRN_CNT_CTRL7 0x0a8e +#define RTL8367D_L2_LRN_CNT_CTRL7_OFFSET 0 +#define RTL8367D_L2_LRN_CNT_CTRL7_MASK 0xFFF + +#define RTL8367D_REG_LUT_LRN_UNDER_STATUS 0x0a91 +#define RTL8367D_LUT_LRN_UNDER_STATUS_OFFSET 0 +#define RTL8367D_LUT_LRN_UNDER_STATUS_MASK 0xFF + +#define RTL8367D_REG_L2_SA_MOVING_FORBID 0x0aa0 +#define RTL8367D_L2_SA_MOVING_FORBID_OFFSET 0 +#define RTL8367D_L2_SA_MOVING_FORBID_MASK 0xFF + +#define RTL8367D_REG_IPMC_GROUP_PMSK_00 0x0AC0 +#define RTL8367D_IPMC_GROUP_PMSK_00_OFFSET 0 +#define RTL8367D_IPMC_GROUP_PMSK_00_MASK 0xFF + +#define RTL8367D_REG_IPMC_GROUP_PMSK_01 0x0AC1 +#define RTL8367D_IPMC_GROUP_PMSK_01_OFFSET 0 +#define RTL8367D_IPMC_GROUP_PMSK_01_MASK 0xFF + +#define RTL8367D_REG_IPMC_GROUP_PMSK_02 0x0AC2 +#define RTL8367D_IPMC_GROUP_PMSK_02_OFFSET 0 +#define RTL8367D_IPMC_GROUP_PMSK_02_MASK 0xFF + +#define RTL8367D_REG_IPMC_GROUP_PMSK_03 0x0AC3 +#define RTL8367D_IPMC_GROUP_PMSK_03_OFFSET 0 +#define RTL8367D_IPMC_GROUP_PMSK_03_MASK 0xFF + +#define RTL8367D_REG_IPMC_GROUP_PMSK_04 0x0AC4 +#define RTL8367D_IPMC_GROUP_PMSK_04_OFFSET 0 +#define RTL8367D_IPMC_GROUP_PMSK_04_MASK 0xFF + +#define RTL8367D_REG_IPMC_GROUP_PMSK_05 0x0AC5 +#define RTL8367D_IPMC_GROUP_PMSK_05_OFFSET 0 +#define RTL8367D_IPMC_GROUP_PMSK_05_MASK 0xFF + +#define RTL8367D_REG_IPMC_GROUP_PMSK_06 0x0AC6 +#define RTL8367D_IPMC_GROUP_PMSK_06_OFFSET 0 +#define RTL8367D_IPMC_GROUP_PMSK_06_MASK 0xFF + +#define RTL8367D_REG_IPMC_GROUP_PMSK_07 0x0AC7 +#define RTL8367D_IPMC_GROUP_PMSK_07_OFFSET 0 +#define RTL8367D_IPMC_GROUP_PMSK_07_MASK 0xFF + +#define RTL8367D_REG_IPMC_GROUP_PMSK_08 0x0AC8 +#define RTL8367D_IPMC_GROUP_PMSK_08_OFFSET 0 +#define RTL8367D_IPMC_GROUP_PMSK_08_MASK 0xFF + +#define RTL8367D_REG_IPMC_GROUP_PMSK_09 0x0AC9 +#define RTL8367D_IPMC_GROUP_PMSK_09_OFFSET 0 +#define RTL8367D_IPMC_GROUP_PMSK_09_MASK 0xFF + +#define RTL8367D_REG_IPMC_GROUP_PMSK_10 0x0ACA +#define RTL8367D_IPMC_GROUP_PMSK_10_OFFSET 0 +#define RTL8367D_IPMC_GROUP_PMSK_10_MASK 0xFF + +#define RTL8367D_REG_IPMC_GROUP_PMSK_11 0x0ACB +#define RTL8367D_IPMC_GROUP_PMSK_11_OFFSET 0 +#define RTL8367D_IPMC_GROUP_PMSK_11_MASK 0xFF + +#define RTL8367D_REG_IPMC_GROUP_PMSK_12 0x0ACC +#define RTL8367D_IPMC_GROUP_PMSK_12_OFFSET 0 +#define RTL8367D_IPMC_GROUP_PMSK_12_MASK 0xFF + +#define RTL8367D_REG_IPMC_GROUP_PMSK_13 0x0ACD +#define RTL8367D_IPMC_GROUP_PMSK_13_OFFSET 0 +#define RTL8367D_IPMC_GROUP_PMSK_13_MASK 0xFF + +#define RTL8367D_REG_IPMC_GROUP_PMSK_14 0x0ACE +#define RTL8367D_IPMC_GROUP_PMSK_14_OFFSET 0 +#define RTL8367D_IPMC_GROUP_PMSK_14_MASK 0xFF + +#define RTL8367D_REG_IPMC_GROUP_PMSK_15 0x0ACF +#define RTL8367D_IPMC_GROUP_PMSK_15_OFFSET 0 +#define RTL8367D_IPMC_GROUP_PMSK_15_MASK 0xFF + +#define RTL8367D_REG_IPMC_GROUP_PMSK_16 0x0AD0 +#define RTL8367D_IPMC_GROUP_PMSK_16_OFFSET 0 +#define RTL8367D_IPMC_GROUP_PMSK_16_MASK 0xFF + +#define RTL8367D_REG_IPMC_GROUP_PMSK_17 0x0AD1 +#define RTL8367D_IPMC_GROUP_PMSK_17_OFFSET 0 +#define RTL8367D_IPMC_GROUP_PMSK_17_MASK 0xFF + +#define RTL8367D_REG_IPMC_GROUP_PMSK_18 0x0AD2 +#define RTL8367D_IPMC_GROUP_PMSK_18_OFFSET 0 +#define RTL8367D_IPMC_GROUP_PMSK_18_MASK 0xFF + +#define RTL8367D_REG_IPMC_GROUP_PMSK_19 0x0AD3 +#define RTL8367D_IPMC_GROUP_PMSK_19_OFFSET 0 +#define RTL8367D_IPMC_GROUP_PMSK_19_MASK 0xFF + +#define RTL8367D_REG_IPMC_GROUP_PMSK_20 0x0AD4 +#define RTL8367D_IPMC_GROUP_PMSK_20_OFFSET 0 +#define RTL8367D_IPMC_GROUP_PMSK_20_MASK 0xFF + +#define RTL8367D_REG_IPMC_GROUP_PMSK_21 0x0AD5 +#define RTL8367D_IPMC_GROUP_PMSK_21_OFFSET 0 +#define RTL8367D_IPMC_GROUP_PMSK_21_MASK 0xFF + +#define RTL8367D_REG_IPMC_GROUP_PMSK_22 0x0AD6 +#define RTL8367D_IPMC_GROUP_PMSK_22_OFFSET 0 +#define RTL8367D_IPMC_GROUP_PMSK_22_MASK 0xFF + +#define RTL8367D_REG_IPMC_GROUP_PMSK_23 0x0AD7 +#define RTL8367D_IPMC_GROUP_PMSK_23_OFFSET 0 +#define RTL8367D_IPMC_GROUP_PMSK_23_MASK 0xFF + +#define RTL8367D_REG_IPMC_GROUP_PMSK_24 0x0AD8 +#define RTL8367D_IPMC_GROUP_PMSK_24_OFFSET 0 +#define RTL8367D_IPMC_GROUP_PMSK_24_MASK 0xFF + +#define RTL8367D_REG_IPMC_GROUP_PMSK_25 0x0AD9 +#define RTL8367D_IPMC_GROUP_PMSK_25_OFFSET 0 +#define RTL8367D_IPMC_GROUP_PMSK_25_MASK 0xFF + +#define RTL8367D_REG_IPMC_GROUP_PMSK_26 0x0ADA +#define RTL8367D_IPMC_GROUP_PMSK_26_OFFSET 0 +#define RTL8367D_IPMC_GROUP_PMSK_26_MASK 0xFF + +#define RTL8367D_REG_IPMC_GROUP_PMSK_27 0x0ADB +#define RTL8367D_IPMC_GROUP_PMSK_27_OFFSET 0 +#define RTL8367D_IPMC_GROUP_PMSK_27_MASK 0xFF + +#define RTL8367D_REG_IPMC_GROUP_PMSK_28 0x0ADC +#define RTL8367D_IPMC_GROUP_PMSK_28_OFFSET 0 +#define RTL8367D_IPMC_GROUP_PMSK_28_MASK 0xFF + +#define RTL8367D_REG_IPMC_GROUP_PMSK_29 0x0ADD +#define RTL8367D_IPMC_GROUP_PMSK_29_OFFSET 0 +#define RTL8367D_IPMC_GROUP_PMSK_29_MASK 0xFF + +#define RTL8367D_REG_IPMC_GROUP_PMSK_30 0x0ADE +#define RTL8367D_IPMC_GROUP_PMSK_30_OFFSET 0 +#define RTL8367D_IPMC_GROUP_PMSK_30_MASK 0xFF + +#define RTL8367D_REG_IPMC_GROUP_PMSK_31 0x0ADF +#define RTL8367D_IPMC_GROUP_PMSK_31_OFFSET 0 +#define RTL8367D_IPMC_GROUP_PMSK_31_MASK 0xFF + +#define RTL8367D_REG_IPMC_GROUP_PMSK_32 0x0AE0 +#define RTL8367D_IPMC_GROUP_PMSK_32_OFFSET 0 +#define RTL8367D_IPMC_GROUP_PMSK_32_MASK 0xFF + +#define RTL8367D_REG_IPMC_GROUP_PMSK_33 0x0AE1 +#define RTL8367D_IPMC_GROUP_PMSK_33_OFFSET 0 +#define RTL8367D_IPMC_GROUP_PMSK_33_MASK 0xFF + +#define RTL8367D_REG_IPMC_GROUP_PMSK_34 0x0AE2 +#define RTL8367D_IPMC_GROUP_PMSK_34_OFFSET 0 +#define RTL8367D_IPMC_GROUP_PMSK_34_MASK 0xFF + +#define RTL8367D_REG_IPMC_GROUP_PMSK_35 0x0AE3 +#define RTL8367D_IPMC_GROUP_PMSK_35_OFFSET 0 +#define RTL8367D_IPMC_GROUP_PMSK_35_MASK 0xFF + +#define RTL8367D_REG_IPMC_GROUP_PMSK_36 0x0AE4 +#define RTL8367D_IPMC_GROUP_PMSK_36_OFFSET 0 +#define RTL8367D_IPMC_GROUP_PMSK_36_MASK 0xFF + +#define RTL8367D_REG_IPMC_GROUP_PMSK_37 0x0AE5 +#define RTL8367D_IPMC_GROUP_PMSK_37_OFFSET 0 +#define RTL8367D_IPMC_GROUP_PMSK_37_MASK 0xFF + +#define RTL8367D_REG_IPMC_GROUP_PMSK_38 0x0AE6 +#define RTL8367D_IPMC_GROUP_PMSK_38_OFFSET 0 +#define RTL8367D_IPMC_GROUP_PMSK_38_MASK 0xFF + +#define RTL8367D_REG_IPMC_GROUP_PMSK_39 0x0AE7 +#define RTL8367D_IPMC_GROUP_PMSK_39_OFFSET 0 +#define RTL8367D_IPMC_GROUP_PMSK_39_MASK 0xFF + +#define RTL8367D_REG_IPMC_GROUP_PMSK_40 0x0AE8 +#define RTL8367D_IPMC_GROUP_PMSK_40_OFFSET 0 +#define RTL8367D_IPMC_GROUP_PMSK_40_MASK 0xFF + +#define RTL8367D_REG_IPMC_GROUP_PMSK_41 0x0AE9 +#define RTL8367D_IPMC_GROUP_PMSK_41_OFFSET 0 +#define RTL8367D_IPMC_GROUP_PMSK_41_MASK 0xFF + +#define RTL8367D_REG_IPMC_GROUP_PMSK_42 0x0AEA +#define RTL8367D_IPMC_GROUP_PMSK_42_OFFSET 0 +#define RTL8367D_IPMC_GROUP_PMSK_42_MASK 0xFF + +#define RTL8367D_REG_IPMC_GROUP_PMSK_43 0x0AEB +#define RTL8367D_IPMC_GROUP_PMSK_43_OFFSET 0 +#define RTL8367D_IPMC_GROUP_PMSK_43_MASK 0xFF + +#define RTL8367D_REG_IPMC_GROUP_PMSK_44 0x0AEC +#define RTL8367D_IPMC_GROUP_PMSK_44_OFFSET 0 +#define RTL8367D_IPMC_GROUP_PMSK_44_MASK 0xFF + +#define RTL8367D_REG_IPMC_GROUP_PMSK_45 0x0AED +#define RTL8367D_IPMC_GROUP_PMSK_45_OFFSET 0 +#define RTL8367D_IPMC_GROUP_PMSK_45_MASK 0xFF + +#define RTL8367D_REG_IPMC_GROUP_PMSK_46 0x0AEE +#define RTL8367D_IPMC_GROUP_PMSK_46_OFFSET 0 +#define RTL8367D_IPMC_GROUP_PMSK_46_MASK 0xFF + +#define RTL8367D_REG_IPMC_GROUP_PMSK_47 0x0AEF +#define RTL8367D_IPMC_GROUP_PMSK_47_OFFSET 0 +#define RTL8367D_IPMC_GROUP_PMSK_47_MASK 0xFF + +#define RTL8367D_REG_IPMC_GROUP_PMSK_48 0x0AF0 +#define RTL8367D_IPMC_GROUP_PMSK_48_OFFSET 0 +#define RTL8367D_IPMC_GROUP_PMSK_48_MASK 0xFF + +#define RTL8367D_REG_IPMC_GROUP_PMSK_49 0x0AF1 +#define RTL8367D_IPMC_GROUP_PMSK_49_OFFSET 0 +#define RTL8367D_IPMC_GROUP_PMSK_49_MASK 0xFF + +#define RTL8367D_REG_IPMC_GROUP_PMSK_50 0x0AF2 +#define RTL8367D_IPMC_GROUP_PMSK_50_OFFSET 0 +#define RTL8367D_IPMC_GROUP_PMSK_50_MASK 0xFF + +#define RTL8367D_REG_IPMC_GROUP_PMSK_51 0x0AF3 +#define RTL8367D_IPMC_GROUP_PMSK_51_OFFSET 0 +#define RTL8367D_IPMC_GROUP_PMSK_51_MASK 0xFF + +#define RTL8367D_REG_IPMC_GROUP_PMSK_52 0x0AF4 +#define RTL8367D_IPMC_GROUP_PMSK_52_OFFSET 0 +#define RTL8367D_IPMC_GROUP_PMSK_52_MASK 0xFF + +#define RTL8367D_REG_IPMC_GROUP_PMSK_53 0x0AF5 +#define RTL8367D_IPMC_GROUP_PMSK_53_OFFSET 0 +#define RTL8367D_IPMC_GROUP_PMSK_53_MASK 0xFF + +#define RTL8367D_REG_IPMC_GROUP_PMSK_54 0x0AF6 +#define RTL8367D_IPMC_GROUP_PMSK_54_OFFSET 0 +#define RTL8367D_IPMC_GROUP_PMSK_54_MASK 0xFF + +#define RTL8367D_REG_IPMC_GROUP_PMSK_55 0x0AF7 +#define RTL8367D_IPMC_GROUP_PMSK_55_OFFSET 0 +#define RTL8367D_IPMC_GROUP_PMSK_55_MASK 0xFF + +#define RTL8367D_REG_IPMC_GROUP_PMSK_56 0x0AF8 +#define RTL8367D_IPMC_GROUP_PMSK_56_OFFSET 0 +#define RTL8367D_IPMC_GROUP_PMSK_56_MASK 0xFF + +#define RTL8367D_REG_IPMC_GROUP_PMSK_57 0x0AF9 +#define RTL8367D_IPMC_GROUP_PMSK_57_OFFSET 0 +#define RTL8367D_IPMC_GROUP_PMSK_57_MASK 0xFF + +#define RTL8367D_REG_IPMC_GROUP_PMSK_58 0x0AFA +#define RTL8367D_IPMC_GROUP_PMSK_58_OFFSET 0 +#define RTL8367D_IPMC_GROUP_PMSK_58_MASK 0xFF + +#define RTL8367D_REG_IPMC_GROUP_PMSK_59 0x0AFB +#define RTL8367D_IPMC_GROUP_PMSK_59_OFFSET 0 +#define RTL8367D_IPMC_GROUP_PMSK_59_MASK 0xFF + +#define RTL8367D_REG_IPMC_GROUP_PMSK_60 0x0AFC +#define RTL8367D_IPMC_GROUP_PMSK_60_OFFSET 0 +#define RTL8367D_IPMC_GROUP_PMSK_60_MASK 0xFF + +#define RTL8367D_REG_IPMC_GROUP_PMSK_61 0x0AFD +#define RTL8367D_IPMC_GROUP_PMSK_61_OFFSET 0 +#define RTL8367D_IPMC_GROUP_PMSK_61_MASK 0xFF + +#define RTL8367D_REG_IPMC_GROUP_PMSK_62 0x0AFE +#define RTL8367D_IPMC_GROUP_PMSK_62_OFFSET 0 +#define RTL8367D_IPMC_GROUP_PMSK_62_MASK 0xFF + +#define RTL8367D_REG_IPMC_GROUP_PMSK_63 0x0AFF +#define RTL8367D_IPMC_GROUP_PMSK_63_OFFSET 0 +#define RTL8367D_IPMC_GROUP_PMSK_63_MASK 0xFF + +/* (16'h0c00)svlan_reg */ + +#define RTL8367D_REG_SVLAN_C2SCFG0_CTRL0 0x0d00 +#define RTL8367D_SVLAN_C2SCFG0_CTRL0_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG0_CTRL0_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_C2SCFG0_CTRL1 0x0d01 +#define RTL8367D_SVLAN_C2SCFG0_CTRL1_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG0_CTRL1_MASK 0xFF + +#define RTL8367D_REG_SVLAN_C2SCFG0_CTRL2 0x0d02 +#define RTL8367D_SVLAN_C2SCFG0_CTRL2_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG0_CTRL2_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_C2SCFG1_CTRL0 0x0d03 +#define RTL8367D_SVLAN_C2SCFG1_CTRL0_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG1_CTRL0_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_C2SCFG1_CTRL1 0x0d04 +#define RTL8367D_SVLAN_C2SCFG1_CTRL1_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG1_CTRL1_MASK 0xFF + +#define RTL8367D_REG_SVLAN_C2SCFG1_CTRL2 0x0d05 +#define RTL8367D_SVLAN_C2SCFG1_CTRL2_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG1_CTRL2_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_C2SCFG2_CTRL0 0x0d06 +#define RTL8367D_SVLAN_C2SCFG2_CTRL0_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG2_CTRL0_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_C2SCFG2_CTRL1 0x0d07 +#define RTL8367D_SVLAN_C2SCFG2_CTRL1_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG2_CTRL1_MASK 0xFF + +#define RTL8367D_REG_SVLAN_C2SCFG2_CTRL2 0x0d08 +#define RTL8367D_SVLAN_C2SCFG2_CTRL2_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG2_CTRL2_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_C2SCFG3_CTRL0 0x0d09 +#define RTL8367D_SVLAN_C2SCFG3_CTRL0_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG3_CTRL0_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_C2SCFG3_CTRL1 0x0d0a +#define RTL8367D_SVLAN_C2SCFG3_CTRL1_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG3_CTRL1_MASK 0xFF + +#define RTL8367D_REG_SVLAN_C2SCFG3_CTRL2 0x0d0b +#define RTL8367D_SVLAN_C2SCFG3_CTRL2_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG3_CTRL2_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_C2SCFG4_CTRL0 0x0d0c +#define RTL8367D_SVLAN_C2SCFG4_CTRL0_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG4_CTRL0_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_C2SCFG4_CTRL1 0x0d0d +#define RTL8367D_SVLAN_C2SCFG4_CTRL1_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG4_CTRL1_MASK 0xFF + +#define RTL8367D_REG_SVLAN_C2SCFG4_CTRL2 0x0d0e +#define RTL8367D_SVLAN_C2SCFG4_CTRL2_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG4_CTRL2_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_C2SCFG5_CTRL0 0x0d0f +#define RTL8367D_SVLAN_C2SCFG5_CTRL0_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG5_CTRL0_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_C2SCFG5_CTRL1 0x0d10 +#define RTL8367D_SVLAN_C2SCFG5_CTRL1_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG5_CTRL1_MASK 0xFF + +#define RTL8367D_REG_SVLAN_C2SCFG5_CTRL2 0x0d11 +#define RTL8367D_SVLAN_C2SCFG5_CTRL2_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG5_CTRL2_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_C2SCFG6_CTRL0 0x0d12 +#define RTL8367D_SVLAN_C2SCFG6_CTRL0_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG6_CTRL0_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_C2SCFG6_CTRL1 0x0d13 +#define RTL8367D_SVLAN_C2SCFG6_CTRL1_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG6_CTRL1_MASK 0xFF + +#define RTL8367D_REG_SVLAN_C2SCFG6_CTRL2 0x0d14 +#define RTL8367D_SVLAN_C2SCFG6_CTRL2_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG6_CTRL2_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_C2SCFG7_CTRL0 0x0d15 +#define RTL8367D_SVLAN_C2SCFG7_CTRL0_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG7_CTRL0_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_C2SCFG7_CTRL1 0x0d16 +#define RTL8367D_SVLAN_C2SCFG7_CTRL1_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG7_CTRL1_MASK 0xFF + +#define RTL8367D_REG_SVLAN_C2SCFG7_CTRL2 0x0d17 +#define RTL8367D_SVLAN_C2SCFG7_CTRL2_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG7_CTRL2_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_C2SCFG8_CTRL0 0x0d18 +#define RTL8367D_SVLAN_C2SCFG8_CTRL0_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG8_CTRL0_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_C2SCFG8_CTRL1 0x0d19 +#define RTL8367D_SVLAN_C2SCFG8_CTRL1_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG8_CTRL1_MASK 0xFF + +#define RTL8367D_REG_SVLAN_C2SCFG8_CTRL2 0x0d1a +#define RTL8367D_SVLAN_C2SCFG8_CTRL2_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG8_CTRL2_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_C2SCFG9_CTRL0 0x0d1b +#define RTL8367D_SVLAN_C2SCFG9_CTRL0_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG9_CTRL0_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_C2SCFG9_CTRL1 0x0d1c +#define RTL8367D_SVLAN_C2SCFG9_CTRL1_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG9_CTRL1_MASK 0xFF + +#define RTL8367D_REG_SVLAN_C2SCFG9_CTRL2 0x0d1d +#define RTL8367D_SVLAN_C2SCFG9_CTRL2_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG9_CTRL2_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_C2SCFG10_CTRL0 0x0d1e +#define RTL8367D_SVLAN_C2SCFG10_CTRL0_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG10_CTRL0_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_C2SCFG10_CTRL1 0x0d1f +#define RTL8367D_SVLAN_C2SCFG10_CTRL1_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG10_CTRL1_MASK 0xFF + +#define RTL8367D_REG_SVLAN_C2SCFG10_CTRL2 0x0d20 +#define RTL8367D_SVLAN_C2SCFG10_CTRL2_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG10_CTRL2_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_C2SCFG11_CTRL0 0x0d21 +#define RTL8367D_SVLAN_C2SCFG11_CTRL0_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG11_CTRL0_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_C2SCFG11_CTRL1 0x0d22 +#define RTL8367D_SVLAN_C2SCFG11_CTRL1_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG11_CTRL1_MASK 0xFF + +#define RTL8367D_REG_SVLAN_C2SCFG11_CTRL2 0x0d23 +#define RTL8367D_SVLAN_C2SCFG11_CTRL2_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG11_CTRL2_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_C2SCFG12_CTRL0 0x0d24 +#define RTL8367D_SVLAN_C2SCFG12_CTRL0_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG12_CTRL0_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_C2SCFG12_CTRL1 0x0d25 +#define RTL8367D_SVLAN_C2SCFG12_CTRL1_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG12_CTRL1_MASK 0xFF + +#define RTL8367D_REG_SVLAN_C2SCFG12_CTRL2 0x0d26 +#define RTL8367D_SVLAN_C2SCFG12_CTRL2_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG12_CTRL2_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_C2SCFG13_CTRL0 0x0d27 +#define RTL8367D_SVLAN_C2SCFG13_CTRL0_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG13_CTRL0_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_C2SCFG13_CTRL1 0x0d28 +#define RTL8367D_SVLAN_C2SCFG13_CTRL1_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG13_CTRL1_MASK 0xFF + +#define RTL8367D_REG_SVLAN_C2SCFG13_CTRL2 0x0d29 +#define RTL8367D_SVLAN_C2SCFG13_CTRL2_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG13_CTRL2_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_C2SCFG14_CTRL0 0x0d2a +#define RTL8367D_SVLAN_C2SCFG14_CTRL0_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG14_CTRL0_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_C2SCFG14_CTRL1 0x0d2b +#define RTL8367D_SVLAN_C2SCFG14_CTRL1_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG14_CTRL1_MASK 0xFF + +#define RTL8367D_REG_SVLAN_C2SCFG14_CTRL2 0x0d2c +#define RTL8367D_SVLAN_C2SCFG14_CTRL2_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG14_CTRL2_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_C2SCFG15_CTRL0 0x0d2d +#define RTL8367D_SVLAN_C2SCFG15_CTRL0_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG15_CTRL0_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_C2SCFG15_CTRL1 0x0d2e +#define RTL8367D_SVLAN_C2SCFG15_CTRL1_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG15_CTRL1_MASK 0xFF + +#define RTL8367D_REG_SVLAN_C2SCFG15_CTRL2 0x0d2f +#define RTL8367D_SVLAN_C2SCFG15_CTRL2_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG15_CTRL2_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_C2SCFG16_CTRL0 0x0d30 +#define RTL8367D_SVLAN_C2SCFG16_CTRL0_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG16_CTRL0_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_C2SCFG16_CTRL1 0x0d31 +#define RTL8367D_SVLAN_C2SCFG16_CTRL1_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG16_CTRL1_MASK 0xFF + +#define RTL8367D_REG_SVLAN_C2SCFG16_CTRL2 0x0d32 +#define RTL8367D_SVLAN_C2SCFG16_CTRL2_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG16_CTRL2_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_C2SCFG17_CTRL0 0x0d33 +#define RTL8367D_SVLAN_C2SCFG17_CTRL0_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG17_CTRL0_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_C2SCFG17_CTRL1 0x0d34 +#define RTL8367D_SVLAN_C2SCFG17_CTRL1_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG17_CTRL1_MASK 0xFF + +#define RTL8367D_REG_SVLAN_C2SCFG17_CTRL2 0x0d35 +#define RTL8367D_SVLAN_C2SCFG17_CTRL2_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG17_CTRL2_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_C2SCFG18_CTRL0 0x0d36 +#define RTL8367D_SVLAN_C2SCFG18_CTRL0_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG18_CTRL0_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_C2SCFG18_CTRL1 0x0d37 +#define RTL8367D_SVLAN_C2SCFG18_CTRL1_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG18_CTRL1_MASK 0xFF + +#define RTL8367D_REG_SVLAN_C2SCFG18_CTRL2 0x0d38 +#define RTL8367D_SVLAN_C2SCFG18_CTRL2_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG18_CTRL2_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_C2SCFG19_CTRL0 0x0d39 +#define RTL8367D_SVLAN_C2SCFG19_CTRL0_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG19_CTRL0_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_C2SCFG19_CTRL1 0x0d3a +#define RTL8367D_SVLAN_C2SCFG19_CTRL1_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG19_CTRL1_MASK 0xFF + +#define RTL8367D_REG_SVLAN_C2SCFG19_CTRL2 0x0d3b +#define RTL8367D_SVLAN_C2SCFG19_CTRL2_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG19_CTRL2_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_C2SCFG20_CTRL0 0x0d3c +#define RTL8367D_SVLAN_C2SCFG20_CTRL0_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG20_CTRL0_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_C2SCFG20_CTRL1 0x0d3d +#define RTL8367D_SVLAN_C2SCFG20_CTRL1_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG20_CTRL1_MASK 0xFF + +#define RTL8367D_REG_SVLAN_C2SCFG20_CTRL2 0x0d3e +#define RTL8367D_SVLAN_C2SCFG20_CTRL2_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG20_CTRL2_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_C2SCFG21_CTRL0 0x0d3f +#define RTL8367D_SVLAN_C2SCFG21_CTRL0_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG21_CTRL0_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_C2SCFG21_CTRL1 0x0d40 +#define RTL8367D_SVLAN_C2SCFG21_CTRL1_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG21_CTRL1_MASK 0xFF + +#define RTL8367D_REG_SVLAN_C2SCFG21_CTRL2 0x0d41 +#define RTL8367D_SVLAN_C2SCFG21_CTRL2_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG21_CTRL2_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_C2SCFG22_CTRL0 0x0d42 +#define RTL8367D_SVLAN_C2SCFG22_CTRL0_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG22_CTRL0_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_C2SCFG22_CTRL1 0x0d43 +#define RTL8367D_SVLAN_C2SCFG22_CTRL1_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG22_CTRL1_MASK 0xFF + +#define RTL8367D_REG_SVLAN_C2SCFG22_CTRL2 0x0d44 +#define RTL8367D_SVLAN_C2SCFG22_CTRL2_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG22_CTRL2_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_C2SCFG23_CTRL0 0x0d45 +#define RTL8367D_SVLAN_C2SCFG23_CTRL0_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG23_CTRL0_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_C2SCFG23_CTRL1 0x0d46 +#define RTL8367D_SVLAN_C2SCFG23_CTRL1_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG23_CTRL1_MASK 0xFF + +#define RTL8367D_REG_SVLAN_C2SCFG23_CTRL2 0x0d47 +#define RTL8367D_SVLAN_C2SCFG23_CTRL2_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG23_CTRL2_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_C2SCFG24_CTRL0 0x0d48 +#define RTL8367D_SVLAN_C2SCFG24_CTRL0_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG24_CTRL0_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_C2SCFG24_CTRL1 0x0d49 +#define RTL8367D_SVLAN_C2SCFG24_CTRL1_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG24_CTRL1_MASK 0xFF + +#define RTL8367D_REG_SVLAN_C2SCFG24_CTRL2 0x0d4a +#define RTL8367D_SVLAN_C2SCFG24_CTRL2_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG24_CTRL2_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_C2SCFG25_CTRL0 0x0d4b +#define RTL8367D_SVLAN_C2SCFG25_CTRL0_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG25_CTRL0_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_C2SCFG25_CTRL1 0x0d4c +#define RTL8367D_SVLAN_C2SCFG25_CTRL1_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG25_CTRL1_MASK 0xFF + +#define RTL8367D_REG_SVLAN_C2SCFG25_CTRL2 0x0d4d +#define RTL8367D_SVLAN_C2SCFG25_CTRL2_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG25_CTRL2_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_C2SCFG26_CTRL0 0x0d4e +#define RTL8367D_SVLAN_C2SCFG26_CTRL0_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG26_CTRL0_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_C2SCFG26_CTRL1 0x0d4f +#define RTL8367D_SVLAN_C2SCFG26_CTRL1_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG26_CTRL1_MASK 0xFF + +#define RTL8367D_REG_SVLAN_C2SCFG26_CTRL2 0x0d50 +#define RTL8367D_SVLAN_C2SCFG26_CTRL2_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG26_CTRL2_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_C2SCFG27_CTRL0 0x0d51 +#define RTL8367D_SVLAN_C2SCFG27_CTRL0_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG27_CTRL0_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_C2SCFG27_CTRL1 0x0d52 +#define RTL8367D_SVLAN_C2SCFG27_CTRL1_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG27_CTRL1_MASK 0xFF + +#define RTL8367D_REG_SVLAN_C2SCFG27_CTRL2 0x0d53 +#define RTL8367D_SVLAN_C2SCFG27_CTRL2_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG27_CTRL2_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_C2SCFG28_CTRL0 0x0d54 +#define RTL8367D_SVLAN_C2SCFG28_CTRL0_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG28_CTRL0_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_C2SCFG28_CTRL1 0x0d55 +#define RTL8367D_SVLAN_C2SCFG28_CTRL1_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG28_CTRL1_MASK 0xFF + +#define RTL8367D_REG_SVLAN_C2SCFG28_CTRL2 0x0d56 +#define RTL8367D_SVLAN_C2SCFG28_CTRL2_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG28_CTRL2_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_C2SCFG29_CTRL0 0x0d57 +#define RTL8367D_SVLAN_C2SCFG29_CTRL0_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG29_CTRL0_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_C2SCFG29_CTRL1 0x0d58 +#define RTL8367D_SVLAN_C2SCFG29_CTRL1_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG29_CTRL1_MASK 0xFF + +#define RTL8367D_REG_SVLAN_C2SCFG29_CTRL2 0x0d59 +#define RTL8367D_SVLAN_C2SCFG29_CTRL2_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG29_CTRL2_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_C2SCFG30_CTRL0 0x0d5a +#define RTL8367D_SVLAN_C2SCFG30_CTRL0_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG30_CTRL0_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_C2SCFG30_CTRL1 0x0d5b +#define RTL8367D_SVLAN_C2SCFG30_CTRL1_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG30_CTRL1_MASK 0xFF + +#define RTL8367D_REG_SVLAN_C2SCFG30_CTRL2 0x0d5c +#define RTL8367D_SVLAN_C2SCFG30_CTRL2_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG30_CTRL2_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_C2SCFG31_CTRL0 0x0d5d +#define RTL8367D_SVLAN_C2SCFG31_CTRL0_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG31_CTRL0_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_C2SCFG31_CTRL1 0x0d5e +#define RTL8367D_SVLAN_C2SCFG31_CTRL1_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG31_CTRL1_MASK 0xFF + +#define RTL8367D_REG_SVLAN_C2SCFG31_CTRL2 0x0d5f +#define RTL8367D_SVLAN_C2SCFG31_CTRL2_OFFSET 0 +#define RTL8367D_SVLAN_C2SCFG31_CTRL2_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_CFG 0x0e80 +#define RTL8367D_VS_UIFSEG_OFFSET 6 +#define RTL8367D_VS_UIFSEG_MASK 0x40 +#define RTL8367D_VS_UNTAG_OFFSET 2 +#define RTL8367D_VS_UNTAG_MASK 0xC +#define RTL8367D_VS_SPRISEL_OFFSET 0 +#define RTL8367D_VS_SPRISEL_MASK 0x3 + +#define RTL8367D_REG_SVLAN_UNTAG_UNMAT_CFG 0x0e85 +#define RTL8367D_SVLAN_UNTAG_UNMAT_CFG_OFFSET 0 +#define RTL8367D_SVLAN_UNTAG_UNMAT_CFG_MASK 0xFFF + +#define RTL8367D_REG_IPMC_GROUP_VALID_15_0 0x0e87 + +#define RTL8367D_REG_IPMC_GROUP_VALID_31_16 0x0e88 + +#define RTL8367D_REG_IPMC_GROUP_VALID_47_32 0x0e89 + +#define RTL8367D_REG_IPMC_GROUP_VALID_63_48 0x0e8a + +#define RTL8367D_REG_SVLAN_PORTBASED_SVID_CTRL0 0x0e90 +#define RTL8367D_SVLAN_PORTBASED_SVID_CTRL0_OFFSET 0 +#define RTL8367D_SVLAN_PORTBASED_SVID_CTRL0_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_PORTBASED_SVID_CTRL1 0x0e91 +#define RTL8367D_SVLAN_PORTBASED_SVID_CTRL1_OFFSET 0 +#define RTL8367D_SVLAN_PORTBASED_SVID_CTRL1_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_PORTBASED_SVID_CTRL2 0x0e92 +#define RTL8367D_SVLAN_PORTBASED_SVID_CTRL2_OFFSET 0 +#define RTL8367D_SVLAN_PORTBASED_SVID_CTRL2_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_PORTBASED_SVID_CTRL3 0x0e93 +#define RTL8367D_SVLAN_PORTBASED_SVID_CTRL3_OFFSET 0 +#define RTL8367D_SVLAN_PORTBASED_SVID_CTRL3_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_PORTBASED_SVID_CTRL4 0x0e94 +#define RTL8367D_SVLAN_PORTBASED_SVID_CTRL4_OFFSET 0 +#define RTL8367D_SVLAN_PORTBASED_SVID_CTRL4_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_PORTBASED_SVID_CTRL5 0x0e95 +#define RTL8367D_SVLAN_PORTBASED_SVID_CTRL5_OFFSET 0 +#define RTL8367D_SVLAN_PORTBASED_SVID_CTRL5_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_PORTBASED_SVID_CTRL6 0x0e96 +#define RTL8367D_SVLAN_PORTBASED_SVID_CTRL6_OFFSET 0 +#define RTL8367D_SVLAN_PORTBASED_SVID_CTRL6_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_PORTBASED_SVID_CTRL7 0x0e97 +#define RTL8367D_SVLAN_PORTBASED_SVID_CTRL7_OFFSET 0 +#define RTL8367D_SVLAN_PORTBASED_SVID_CTRL7_MASK 0xFFF + +/* (16'h0f00)hsactrl_reg */ + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY0_CTRL0 0x0f00 +#define RTL8367D_SVLAN_SP2C_ENTRY0_CTRL0_SVID_OFFSET 3 +#define RTL8367D_SVLAN_SP2C_ENTRY0_CTRL0_SVID_MASK 0x7FF8 +#define RTL8367D_SVLAN_SP2C_ENTRY0_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY0_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY0_CTRL1 0x0f01 +#define RTL8367D_SVLAN_SP2C_ENTRY0_CTRL1_VALID_OFFSET 12 +#define RTL8367D_SVLAN_SP2C_ENTRY0_CTRL1_VALID_MASK 0x1000 +#define RTL8367D_SVLAN_SP2C_ENTRY0_CTRL1_VID_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY0_CTRL1_VID_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY1_CTRL0 0x0f02 +#define RTL8367D_SVLAN_SP2C_ENTRY1_CTRL0_SVID_OFFSET 3 +#define RTL8367D_SVLAN_SP2C_ENTRY1_CTRL0_SVID_MASK 0x7FF8 +#define RTL8367D_SVLAN_SP2C_ENTRY1_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY1_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY1_CTRL1 0x0f03 +#define RTL8367D_SVLAN_SP2C_ENTRY1_CTRL1_VALID_OFFSET 12 +#define RTL8367D_SVLAN_SP2C_ENTRY1_CTRL1_VALID_MASK 0x1000 +#define RTL8367D_SVLAN_SP2C_ENTRY1_CTRL1_VID_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY1_CTRL1_VID_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY2_CTRL0 0x0f04 +#define RTL8367D_SVLAN_SP2C_ENTRY2_CTRL0_SVID_OFFSET 3 +#define RTL8367D_SVLAN_SP2C_ENTRY2_CTRL0_SVID_MASK 0x7FF8 +#define RTL8367D_SVLAN_SP2C_ENTRY2_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY2_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY2_CTRL1 0x0f05 +#define RTL8367D_SVLAN_SP2C_ENTRY2_CTRL1_VALID_OFFSET 12 +#define RTL8367D_SVLAN_SP2C_ENTRY2_CTRL1_VALID_MASK 0x1000 +#define RTL8367D_SVLAN_SP2C_ENTRY2_CTRL1_VID_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY2_CTRL1_VID_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY3_CTRL0 0x0f06 +#define RTL8367D_SVLAN_SP2C_ENTRY3_CTRL0_SVID_OFFSET 3 +#define RTL8367D_SVLAN_SP2C_ENTRY3_CTRL0_SVID_MASK 0x7FF8 +#define RTL8367D_SVLAN_SP2C_ENTRY3_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY3_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY3_CTRL1 0x0f07 +#define RTL8367D_SVLAN_SP2C_ENTRY3_CTRL1_VALID_OFFSET 12 +#define RTL8367D_SVLAN_SP2C_ENTRY3_CTRL1_VALID_MASK 0x1000 +#define RTL8367D_SVLAN_SP2C_ENTRY3_CTRL1_VID_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY3_CTRL1_VID_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY4_CTRL0 0x0f08 +#define RTL8367D_SVLAN_SP2C_ENTRY4_CTRL0_SVID_OFFSET 3 +#define RTL8367D_SVLAN_SP2C_ENTRY4_CTRL0_SVID_MASK 0x7FF8 +#define RTL8367D_SVLAN_SP2C_ENTRY4_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY4_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY4_CTRL1 0x0f09 +#define RTL8367D_SVLAN_SP2C_ENTRY4_CTRL1_VALID_OFFSET 12 +#define RTL8367D_SVLAN_SP2C_ENTRY4_CTRL1_VALID_MASK 0x1000 +#define RTL8367D_SVLAN_SP2C_ENTRY4_CTRL1_VID_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY4_CTRL1_VID_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY5_CTRL0 0x0f0a +#define RTL8367D_SVLAN_SP2C_ENTRY5_CTRL0_SVID_OFFSET 3 +#define RTL8367D_SVLAN_SP2C_ENTRY5_CTRL0_SVID_MASK 0x7FF8 +#define RTL8367D_SVLAN_SP2C_ENTRY5_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY5_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY5_CTRL1 0x0f0b +#define RTL8367D_SVLAN_SP2C_ENTRY5_CTRL1_VALID_OFFSET 12 +#define RTL8367D_SVLAN_SP2C_ENTRY5_CTRL1_VALID_MASK 0x1000 +#define RTL8367D_SVLAN_SP2C_ENTRY5_CTRL1_VID_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY5_CTRL1_VID_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY6_CTRL0 0x0f0c +#define RTL8367D_SVLAN_SP2C_ENTRY6_CTRL0_SVID_OFFSET 3 +#define RTL8367D_SVLAN_SP2C_ENTRY6_CTRL0_SVID_MASK 0x7FF8 +#define RTL8367D_SVLAN_SP2C_ENTRY6_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY6_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY6_CTRL1 0x0f0d +#define RTL8367D_SVLAN_SP2C_ENTRY6_CTRL1_VALID_OFFSET 12 +#define RTL8367D_SVLAN_SP2C_ENTRY6_CTRL1_VALID_MASK 0x1000 +#define RTL8367D_SVLAN_SP2C_ENTRY6_CTRL1_VID_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY6_CTRL1_VID_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY7_CTRL0 0x0f0e +#define RTL8367D_SVLAN_SP2C_ENTRY7_CTRL0_SVID_OFFSET 3 +#define RTL8367D_SVLAN_SP2C_ENTRY7_CTRL0_SVID_MASK 0x7FF8 +#define RTL8367D_SVLAN_SP2C_ENTRY7_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY7_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY7_CTRL1 0x0f0f +#define RTL8367D_SVLAN_SP2C_ENTRY7_CTRL1_VALID_OFFSET 12 +#define RTL8367D_SVLAN_SP2C_ENTRY7_CTRL1_VALID_MASK 0x1000 +#define RTL8367D_SVLAN_SP2C_ENTRY7_CTRL1_VID_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY7_CTRL1_VID_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY8_CTRL0 0x0f10 +#define RTL8367D_SVLAN_SP2C_ENTRY8_CTRL0_SVID_OFFSET 3 +#define RTL8367D_SVLAN_SP2C_ENTRY8_CTRL0_SVID_MASK 0x7FF8 +#define RTL8367D_SVLAN_SP2C_ENTRY8_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY8_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY8_CTRL1 0x0f11 +#define RTL8367D_SVLAN_SP2C_ENTRY8_CTRL1_VALID_OFFSET 12 +#define RTL8367D_SVLAN_SP2C_ENTRY8_CTRL1_VALID_MASK 0x1000 +#define RTL8367D_SVLAN_SP2C_ENTRY8_CTRL1_VID_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY8_CTRL1_VID_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY9_CTRL0 0x0f12 +#define RTL8367D_SVLAN_SP2C_ENTRY9_CTRL0_SVID_OFFSET 3 +#define RTL8367D_SVLAN_SP2C_ENTRY9_CTRL0_SVID_MASK 0x7FF8 +#define RTL8367D_SVLAN_SP2C_ENTRY9_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY9_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY9_CTRL1 0x0f13 +#define RTL8367D_SVLAN_SP2C_ENTRY9_CTRL1_VALID_OFFSET 12 +#define RTL8367D_SVLAN_SP2C_ENTRY9_CTRL1_VALID_MASK 0x1000 +#define RTL8367D_SVLAN_SP2C_ENTRY9_CTRL1_VID_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY9_CTRL1_VID_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY10_CTRL0 0x0f14 +#define RTL8367D_SVLAN_SP2C_ENTRY10_CTRL0_SVID_OFFSET 3 +#define RTL8367D_SVLAN_SP2C_ENTRY10_CTRL0_SVID_MASK 0x7FF8 +#define RTL8367D_SVLAN_SP2C_ENTRY10_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY10_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY10_CTRL1 0x0f15 +#define RTL8367D_SVLAN_SP2C_ENTRY10_CTRL1_VALID_OFFSET 12 +#define RTL8367D_SVLAN_SP2C_ENTRY10_CTRL1_VALID_MASK 0x1000 +#define RTL8367D_SVLAN_SP2C_ENTRY10_CTRL1_VID_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY10_CTRL1_VID_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY11_CTRL0 0x0f16 +#define RTL8367D_SVLAN_SP2C_ENTRY11_CTRL0_SVID_OFFSET 3 +#define RTL8367D_SVLAN_SP2C_ENTRY11_CTRL0_SVID_MASK 0x7FF8 +#define RTL8367D_SVLAN_SP2C_ENTRY11_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY11_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY11_CTRL1 0x0f17 +#define RTL8367D_SVLAN_SP2C_ENTRY11_CTRL1_VALID_OFFSET 12 +#define RTL8367D_SVLAN_SP2C_ENTRY11_CTRL1_VALID_MASK 0x1000 +#define RTL8367D_SVLAN_SP2C_ENTRY11_CTRL1_VID_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY11_CTRL1_VID_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY12_CTRL0 0x0f18 +#define RTL8367D_SVLAN_SP2C_ENTRY12_CTRL0_SVID_OFFSET 3 +#define RTL8367D_SVLAN_SP2C_ENTRY12_CTRL0_SVID_MASK 0x7FF8 +#define RTL8367D_SVLAN_SP2C_ENTRY12_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY12_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY12_CTRL1 0x0f19 +#define RTL8367D_SVLAN_SP2C_ENTRY12_CTRL1_VALID_OFFSET 12 +#define RTL8367D_SVLAN_SP2C_ENTRY12_CTRL1_VALID_MASK 0x1000 +#define RTL8367D_SVLAN_SP2C_ENTRY12_CTRL1_VID_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY12_CTRL1_VID_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY13_CTRL0 0x0f1a +#define RTL8367D_SVLAN_SP2C_ENTRY13_CTRL0_SVID_OFFSET 3 +#define RTL8367D_SVLAN_SP2C_ENTRY13_CTRL0_SVID_MASK 0x7FF8 +#define RTL8367D_SVLAN_SP2C_ENTRY13_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY13_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY13_CTRL1 0x0f1b +#define RTL8367D_SVLAN_SP2C_ENTRY13_CTRL1_VALID_OFFSET 12 +#define RTL8367D_SVLAN_SP2C_ENTRY13_CTRL1_VALID_MASK 0x1000 +#define RTL8367D_SVLAN_SP2C_ENTRY13_CTRL1_VID_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY13_CTRL1_VID_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY14_CTRL0 0x0f1c +#define RTL8367D_SVLAN_SP2C_ENTRY14_CTRL0_SVID_OFFSET 3 +#define RTL8367D_SVLAN_SP2C_ENTRY14_CTRL0_SVID_MASK 0x7FF8 +#define RTL8367D_SVLAN_SP2C_ENTRY14_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY14_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY14_CTRL1 0x0f1d +#define RTL8367D_SVLAN_SP2C_ENTRY14_CTRL1_VALID_OFFSET 12 +#define RTL8367D_SVLAN_SP2C_ENTRY14_CTRL1_VALID_MASK 0x1000 +#define RTL8367D_SVLAN_SP2C_ENTRY14_CTRL1_VID_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY14_CTRL1_VID_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY15_CTRL0 0x0f1e +#define RTL8367D_SVLAN_SP2C_ENTRY15_CTRL0_SVID_OFFSET 3 +#define RTL8367D_SVLAN_SP2C_ENTRY15_CTRL0_SVID_MASK 0x7FF8 +#define RTL8367D_SVLAN_SP2C_ENTRY15_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY15_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY15_CTRL1 0x0f1f +#define RTL8367D_SVLAN_SP2C_ENTRY15_CTRL1_VALID_OFFSET 12 +#define RTL8367D_SVLAN_SP2C_ENTRY15_CTRL1_VALID_MASK 0x1000 +#define RTL8367D_SVLAN_SP2C_ENTRY15_CTRL1_VID_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY15_CTRL1_VID_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY16_CTRL0 0x0f20 +#define RTL8367D_SVLAN_SP2C_ENTRY16_CTRL0_SVID_OFFSET 3 +#define RTL8367D_SVLAN_SP2C_ENTRY16_CTRL0_SVID_MASK 0x7FF8 +#define RTL8367D_SVLAN_SP2C_ENTRY16_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY16_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY16_CTRL1 0x0f21 +#define RTL8367D_SVLAN_SP2C_ENTRY16_CTRL1_VALID_OFFSET 12 +#define RTL8367D_SVLAN_SP2C_ENTRY16_CTRL1_VALID_MASK 0x1000 +#define RTL8367D_SVLAN_SP2C_ENTRY16_CTRL1_VID_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY16_CTRL1_VID_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY17_CTRL0 0x0f22 +#define RTL8367D_SVLAN_SP2C_ENTRY17_CTRL0_SVID_OFFSET 3 +#define RTL8367D_SVLAN_SP2C_ENTRY17_CTRL0_SVID_MASK 0x7FF8 +#define RTL8367D_SVLAN_SP2C_ENTRY17_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY17_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY17_CTRL1 0x0f23 +#define RTL8367D_SVLAN_SP2C_ENTRY17_CTRL1_VALID_OFFSET 12 +#define RTL8367D_SVLAN_SP2C_ENTRY17_CTRL1_VALID_MASK 0x1000 +#define RTL8367D_SVLAN_SP2C_ENTRY17_CTRL1_VID_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY17_CTRL1_VID_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY18_CTRL0 0x0f24 +#define RTL8367D_SVLAN_SP2C_ENTRY18_CTRL0_SVID_OFFSET 3 +#define RTL8367D_SVLAN_SP2C_ENTRY18_CTRL0_SVID_MASK 0x7FF8 +#define RTL8367D_SVLAN_SP2C_ENTRY18_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY18_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY18_CTRL1 0x0f25 +#define RTL8367D_SVLAN_SP2C_ENTRY18_CTRL1_VALID_OFFSET 12 +#define RTL8367D_SVLAN_SP2C_ENTRY18_CTRL1_VALID_MASK 0x1000 +#define RTL8367D_SVLAN_SP2C_ENTRY18_CTRL1_VID_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY18_CTRL1_VID_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY19_CTRL0 0x0f26 +#define RTL8367D_SVLAN_SP2C_ENTRY19_CTRL0_SVID_OFFSET 3 +#define RTL8367D_SVLAN_SP2C_ENTRY19_CTRL0_SVID_MASK 0x7FF8 +#define RTL8367D_SVLAN_SP2C_ENTRY19_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY19_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY19_CTRL1 0x0f27 +#define RTL8367D_SVLAN_SP2C_ENTRY19_CTRL1_VALID_OFFSET 12 +#define RTL8367D_SVLAN_SP2C_ENTRY19_CTRL1_VALID_MASK 0x1000 +#define RTL8367D_SVLAN_SP2C_ENTRY19_CTRL1_VID_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY19_CTRL1_VID_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY20_CTRL0 0x0f28 +#define RTL8367D_SVLAN_SP2C_ENTRY20_CTRL0_SVID_OFFSET 3 +#define RTL8367D_SVLAN_SP2C_ENTRY20_CTRL0_SVID_MASK 0x7FF8 +#define RTL8367D_SVLAN_SP2C_ENTRY20_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY20_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY20_CTRL1 0x0f29 +#define RTL8367D_SVLAN_SP2C_ENTRY20_CTRL1_VALID_OFFSET 12 +#define RTL8367D_SVLAN_SP2C_ENTRY20_CTRL1_VALID_MASK 0x1000 +#define RTL8367D_SVLAN_SP2C_ENTRY20_CTRL1_VID_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY20_CTRL1_VID_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY21_CTRL0 0x0f2a +#define RTL8367D_SVLAN_SP2C_ENTRY21_CTRL0_SVID_OFFSET 3 +#define RTL8367D_SVLAN_SP2C_ENTRY21_CTRL0_SVID_MASK 0x7FF8 +#define RTL8367D_SVLAN_SP2C_ENTRY21_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY21_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY21_CTRL1 0x0f2b +#define RTL8367D_SVLAN_SP2C_ENTRY21_CTRL1_VALID_OFFSET 12 +#define RTL8367D_SVLAN_SP2C_ENTRY21_CTRL1_VALID_MASK 0x1000 +#define RTL8367D_SVLAN_SP2C_ENTRY21_CTRL1_VID_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY21_CTRL1_VID_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY22_CTRL0 0x0f2c +#define RTL8367D_SVLAN_SP2C_ENTRY22_CTRL0_SVID_OFFSET 3 +#define RTL8367D_SVLAN_SP2C_ENTRY22_CTRL0_SVID_MASK 0x7FF8 +#define RTL8367D_SVLAN_SP2C_ENTRY22_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY22_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY22_CTRL1 0x0f2d +#define RTL8367D_SVLAN_SP2C_ENTRY22_CTRL1_VALID_OFFSET 12 +#define RTL8367D_SVLAN_SP2C_ENTRY22_CTRL1_VALID_MASK 0x1000 +#define RTL8367D_SVLAN_SP2C_ENTRY22_CTRL1_VID_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY22_CTRL1_VID_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY23_CTRL0 0x0f2e +#define RTL8367D_SVLAN_SP2C_ENTRY23_CTRL0_SVID_OFFSET 3 +#define RTL8367D_SVLAN_SP2C_ENTRY23_CTRL0_SVID_MASK 0x7FF8 +#define RTL8367D_SVLAN_SP2C_ENTRY23_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY23_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY23_CTRL1 0x0f2f +#define RTL8367D_SVLAN_SP2C_ENTRY23_CTRL1_VALID_OFFSET 12 +#define RTL8367D_SVLAN_SP2C_ENTRY23_CTRL1_VALID_MASK 0x1000 +#define RTL8367D_SVLAN_SP2C_ENTRY23_CTRL1_VID_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY23_CTRL1_VID_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY24_CTRL0 0x0f30 +#define RTL8367D_SVLAN_SP2C_ENTRY24_CTRL0_SVID_OFFSET 3 +#define RTL8367D_SVLAN_SP2C_ENTRY24_CTRL0_SVID_MASK 0x7FF8 +#define RTL8367D_SVLAN_SP2C_ENTRY24_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY24_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY24_CTRL1 0x0f31 +#define RTL8367D_SVLAN_SP2C_ENTRY24_CTRL1_VALID_OFFSET 12 +#define RTL8367D_SVLAN_SP2C_ENTRY24_CTRL1_VALID_MASK 0x1000 +#define RTL8367D_SVLAN_SP2C_ENTRY24_CTRL1_VID_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY24_CTRL1_VID_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY25_CTRL0 0x0f32 +#define RTL8367D_SVLAN_SP2C_ENTRY25_CTRL0_SVID_OFFSET 3 +#define RTL8367D_SVLAN_SP2C_ENTRY25_CTRL0_SVID_MASK 0x7FF8 +#define RTL8367D_SVLAN_SP2C_ENTRY25_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY25_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY25_CTRL1 0x0f33 +#define RTL8367D_SVLAN_SP2C_ENTRY25_CTRL1_VALID_OFFSET 12 +#define RTL8367D_SVLAN_SP2C_ENTRY25_CTRL1_VALID_MASK 0x1000 +#define RTL8367D_SVLAN_SP2C_ENTRY25_CTRL1_VID_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY25_CTRL1_VID_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY26_CTRL0 0x0f34 +#define RTL8367D_SVLAN_SP2C_ENTRY26_CTRL0_SVID_OFFSET 3 +#define RTL8367D_SVLAN_SP2C_ENTRY26_CTRL0_SVID_MASK 0x7FF8 +#define RTL8367D_SVLAN_SP2C_ENTRY26_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY26_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY26_CTRL1 0x0f35 +#define RTL8367D_SVLAN_SP2C_ENTRY26_CTRL1_VALID_OFFSET 12 +#define RTL8367D_SVLAN_SP2C_ENTRY26_CTRL1_VALID_MASK 0x1000 +#define RTL8367D_SVLAN_SP2C_ENTRY26_CTRL1_VID_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY26_CTRL1_VID_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY27_CTRL0 0x0f36 +#define RTL8367D_SVLAN_SP2C_ENTRY27_CTRL0_SVID_OFFSET 3 +#define RTL8367D_SVLAN_SP2C_ENTRY27_CTRL0_SVID_MASK 0x7FF8 +#define RTL8367D_SVLAN_SP2C_ENTRY27_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY27_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY27_CTRL1 0x0f37 +#define RTL8367D_SVLAN_SP2C_ENTRY27_CTRL1_VALID_OFFSET 12 +#define RTL8367D_SVLAN_SP2C_ENTRY27_CTRL1_VALID_MASK 0x1000 +#define RTL8367D_SVLAN_SP2C_ENTRY27_CTRL1_VID_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY27_CTRL1_VID_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY28_CTRL0 0x0f38 +#define RTL8367D_SVLAN_SP2C_ENTRY28_CTRL0_SVID_OFFSET 3 +#define RTL8367D_SVLAN_SP2C_ENTRY28_CTRL0_SVID_MASK 0x7FF8 +#define RTL8367D_SVLAN_SP2C_ENTRY28_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY28_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY28_CTRL1 0x0f39 +#define RTL8367D_SVLAN_SP2C_ENTRY28_CTRL1_VALID_OFFSET 12 +#define RTL8367D_SVLAN_SP2C_ENTRY28_CTRL1_VALID_MASK 0x1000 +#define RTL8367D_SVLAN_SP2C_ENTRY28_CTRL1_VID_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY28_CTRL1_VID_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY29_CTRL0 0x0f3a +#define RTL8367D_SVLAN_SP2C_ENTRY29_CTRL0_SVID_OFFSET 3 +#define RTL8367D_SVLAN_SP2C_ENTRY29_CTRL0_SVID_MASK 0x7FF8 +#define RTL8367D_SVLAN_SP2C_ENTRY29_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY29_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY29_CTRL1 0x0f3b +#define RTL8367D_SVLAN_SP2C_ENTRY29_CTRL1_VALID_OFFSET 12 +#define RTL8367D_SVLAN_SP2C_ENTRY29_CTRL1_VALID_MASK 0x1000 +#define RTL8367D_SVLAN_SP2C_ENTRY29_CTRL1_VID_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY29_CTRL1_VID_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY30_CTRL0 0x0f3c +#define RTL8367D_SVLAN_SP2C_ENTRY30_CTRL0_SVID_OFFSET 3 +#define RTL8367D_SVLAN_SP2C_ENTRY30_CTRL0_SVID_MASK 0x7FF8 +#define RTL8367D_SVLAN_SP2C_ENTRY30_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY30_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY30_CTRL1 0x0f3d +#define RTL8367D_SVLAN_SP2C_ENTRY30_CTRL1_VALID_OFFSET 12 +#define RTL8367D_SVLAN_SP2C_ENTRY30_CTRL1_VALID_MASK 0x1000 +#define RTL8367D_SVLAN_SP2C_ENTRY30_CTRL1_VID_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY30_CTRL1_VID_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY31_CTRL0 0x0f3e +#define RTL8367D_SVLAN_SP2C_ENTRY31_CTRL0_SVID_OFFSET 3 +#define RTL8367D_SVLAN_SP2C_ENTRY31_CTRL0_SVID_MASK 0x7FF8 +#define RTL8367D_SVLAN_SP2C_ENTRY31_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY31_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY31_CTRL1 0x0f3f +#define RTL8367D_SVLAN_SP2C_ENTRY31_CTRL1_VALID_OFFSET 12 +#define RTL8367D_SVLAN_SP2C_ENTRY31_CTRL1_VALID_MASK 0x1000 +#define RTL8367D_SVLAN_SP2C_ENTRY31_CTRL1_VID_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY31_CTRL1_VID_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY32_CTRL0 0x0f40 +#define RTL8367D_SVLAN_SP2C_ENTRY32_CTRL0_SVID_OFFSET 3 +#define RTL8367D_SVLAN_SP2C_ENTRY32_CTRL0_SVID_MASK 0x7FF8 +#define RTL8367D_SVLAN_SP2C_ENTRY32_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY32_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY32_CTRL1 0x0f41 +#define RTL8367D_SVLAN_SP2C_ENTRY32_CTRL1_VALID_OFFSET 12 +#define RTL8367D_SVLAN_SP2C_ENTRY32_CTRL1_VALID_MASK 0x1000 +#define RTL8367D_SVLAN_SP2C_ENTRY32_CTRL1_VID_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY32_CTRL1_VID_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY33_CTRL0 0x0f42 +#define RTL8367D_SVLAN_SP2C_ENTRY33_CTRL0_SVID_OFFSET 3 +#define RTL8367D_SVLAN_SP2C_ENTRY33_CTRL0_SVID_MASK 0x7FF8 +#define RTL8367D_SVLAN_SP2C_ENTRY33_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY33_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY33_CTRL1 0x0f43 +#define RTL8367D_SVLAN_SP2C_ENTRY33_CTRL1_VALID_OFFSET 12 +#define RTL8367D_SVLAN_SP2C_ENTRY33_CTRL1_VALID_MASK 0x1000 +#define RTL8367D_SVLAN_SP2C_ENTRY33_CTRL1_VID_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY33_CTRL1_VID_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY34_CTRL0 0x0f44 +#define RTL8367D_SVLAN_SP2C_ENTRY34_CTRL0_SVID_OFFSET 3 +#define RTL8367D_SVLAN_SP2C_ENTRY34_CTRL0_SVID_MASK 0x7FF8 +#define RTL8367D_SVLAN_SP2C_ENTRY34_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY34_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY34_CTRL1 0x0f45 +#define RTL8367D_SVLAN_SP2C_ENTRY34_CTRL1_VALID_OFFSET 12 +#define RTL8367D_SVLAN_SP2C_ENTRY34_CTRL1_VALID_MASK 0x1000 +#define RTL8367D_SVLAN_SP2C_ENTRY34_CTRL1_VID_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY34_CTRL1_VID_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY35_CTRL0 0x0f46 +#define RTL8367D_SVLAN_SP2C_ENTRY35_CTRL0_SVID_OFFSET 3 +#define RTL8367D_SVLAN_SP2C_ENTRY35_CTRL0_SVID_MASK 0x7FF8 +#define RTL8367D_SVLAN_SP2C_ENTRY35_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY35_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY35_CTRL1 0x0f47 +#define RTL8367D_SVLAN_SP2C_ENTRY35_CTRL1_VALID_OFFSET 12 +#define RTL8367D_SVLAN_SP2C_ENTRY35_CTRL1_VALID_MASK 0x1000 +#define RTL8367D_SVLAN_SP2C_ENTRY35_CTRL1_VID_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY35_CTRL1_VID_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY36_CTRL0 0x0f48 +#define RTL8367D_SVLAN_SP2C_ENTRY36_CTRL0_SVID_OFFSET 3 +#define RTL8367D_SVLAN_SP2C_ENTRY36_CTRL0_SVID_MASK 0x7FF8 +#define RTL8367D_SVLAN_SP2C_ENTRY36_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY36_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY36_CTRL1 0x0f49 +#define RTL8367D_SVLAN_SP2C_ENTRY36_CTRL1_VALID_OFFSET 12 +#define RTL8367D_SVLAN_SP2C_ENTRY36_CTRL1_VALID_MASK 0x1000 +#define RTL8367D_SVLAN_SP2C_ENTRY36_CTRL1_VID_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY36_CTRL1_VID_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY37_CTRL0 0x0f4a +#define RTL8367D_SVLAN_SP2C_ENTRY37_CTRL0_SVID_OFFSET 3 +#define RTL8367D_SVLAN_SP2C_ENTRY37_CTRL0_SVID_MASK 0x7FF8 +#define RTL8367D_SVLAN_SP2C_ENTRY37_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY37_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY37_CTRL1 0x0f4b +#define RTL8367D_SVLAN_SP2C_ENTRY37_CTRL1_VALID_OFFSET 12 +#define RTL8367D_SVLAN_SP2C_ENTRY37_CTRL1_VALID_MASK 0x1000 +#define RTL8367D_SVLAN_SP2C_ENTRY37_CTRL1_VID_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY37_CTRL1_VID_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY38_CTRL0 0x0f4c +#define RTL8367D_SVLAN_SP2C_ENTRY38_CTRL0_SVID_OFFSET 3 +#define RTL8367D_SVLAN_SP2C_ENTRY38_CTRL0_SVID_MASK 0x7FF8 +#define RTL8367D_SVLAN_SP2C_ENTRY38_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY38_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY38_CTRL1 0x0f4d +#define RTL8367D_SVLAN_SP2C_ENTRY38_CTRL1_VALID_OFFSET 12 +#define RTL8367D_SVLAN_SP2C_ENTRY38_CTRL1_VALID_MASK 0x1000 +#define RTL8367D_SVLAN_SP2C_ENTRY38_CTRL1_VID_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY38_CTRL1_VID_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY39_CTRL0 0x0f4e +#define RTL8367D_SVLAN_SP2C_ENTRY39_CTRL0_SVID_OFFSET 3 +#define RTL8367D_SVLAN_SP2C_ENTRY39_CTRL0_SVID_MASK 0x7FF8 +#define RTL8367D_SVLAN_SP2C_ENTRY39_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY39_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY39_CTRL1 0x0f4f +#define RTL8367D_SVLAN_SP2C_ENTRY39_CTRL1_VALID_OFFSET 12 +#define RTL8367D_SVLAN_SP2C_ENTRY39_CTRL1_VALID_MASK 0x1000 +#define RTL8367D_SVLAN_SP2C_ENTRY39_CTRL1_VID_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY39_CTRL1_VID_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY40_CTRL0 0x0f50 +#define RTL8367D_SVLAN_SP2C_ENTRY40_CTRL0_SVID_OFFSET 3 +#define RTL8367D_SVLAN_SP2C_ENTRY40_CTRL0_SVID_MASK 0x7FF8 +#define RTL8367D_SVLAN_SP2C_ENTRY40_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY40_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY40_CTRL1 0x0f51 +#define RTL8367D_SVLAN_SP2C_ENTRY40_CTRL1_VALID_OFFSET 12 +#define RTL8367D_SVLAN_SP2C_ENTRY40_CTRL1_VALID_MASK 0x1000 +#define RTL8367D_SVLAN_SP2C_ENTRY40_CTRL1_VID_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY40_CTRL1_VID_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY41_CTRL0 0x0f52 +#define RTL8367D_SVLAN_SP2C_ENTRY41_CTRL0_SVID_OFFSET 3 +#define RTL8367D_SVLAN_SP2C_ENTRY41_CTRL0_SVID_MASK 0x7FF8 +#define RTL8367D_SVLAN_SP2C_ENTRY41_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY41_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY41_CTRL1 0x0f53 +#define RTL8367D_SVLAN_SP2C_ENTRY41_CTRL1_VALID_OFFSET 12 +#define RTL8367D_SVLAN_SP2C_ENTRY41_CTRL1_VALID_MASK 0x1000 +#define RTL8367D_SVLAN_SP2C_ENTRY41_CTRL1_VID_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY41_CTRL1_VID_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY42_CTRL0 0x0f54 +#define RTL8367D_SVLAN_SP2C_ENTRY42_CTRL0_SVID_OFFSET 3 +#define RTL8367D_SVLAN_SP2C_ENTRY42_CTRL0_SVID_MASK 0x7FF8 +#define RTL8367D_SVLAN_SP2C_ENTRY42_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY42_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY42_CTRL1 0x0f55 +#define RTL8367D_SVLAN_SP2C_ENTRY42_CTRL1_VALID_OFFSET 12 +#define RTL8367D_SVLAN_SP2C_ENTRY42_CTRL1_VALID_MASK 0x1000 +#define RTL8367D_SVLAN_SP2C_ENTRY42_CTRL1_VID_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY42_CTRL1_VID_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY43_CTRL0 0x0f56 +#define RTL8367D_SVLAN_SP2C_ENTRY43_CTRL0_SVID_OFFSET 3 +#define RTL8367D_SVLAN_SP2C_ENTRY43_CTRL0_SVID_MASK 0x7FF8 +#define RTL8367D_SVLAN_SP2C_ENTRY43_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY43_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY43_CTRL1 0x0f57 +#define RTL8367D_SVLAN_SP2C_ENTRY43_CTRL1_VALID_OFFSET 12 +#define RTL8367D_SVLAN_SP2C_ENTRY43_CTRL1_VALID_MASK 0x1000 +#define RTL8367D_SVLAN_SP2C_ENTRY43_CTRL1_VID_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY43_CTRL1_VID_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY44_CTRL0 0x0f58 +#define RTL8367D_SVLAN_SP2C_ENTRY44_CTRL0_SVID_OFFSET 3 +#define RTL8367D_SVLAN_SP2C_ENTRY44_CTRL0_SVID_MASK 0x7FF8 +#define RTL8367D_SVLAN_SP2C_ENTRY44_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY44_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY44_CTRL1 0x0f59 +#define RTL8367D_SVLAN_SP2C_ENTRY44_CTRL1_VALID_OFFSET 12 +#define RTL8367D_SVLAN_SP2C_ENTRY44_CTRL1_VALID_MASK 0x1000 +#define RTL8367D_SVLAN_SP2C_ENTRY44_CTRL1_VID_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY44_CTRL1_VID_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY45_CTRL0 0x0f5a +#define RTL8367D_SVLAN_SP2C_ENTRY45_CTRL0_SVID_OFFSET 3 +#define RTL8367D_SVLAN_SP2C_ENTRY45_CTRL0_SVID_MASK 0x7FF8 +#define RTL8367D_SVLAN_SP2C_ENTRY45_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY45_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY45_CTRL1 0x0f5b +#define RTL8367D_SVLAN_SP2C_ENTRY45_CTRL1_VALID_OFFSET 12 +#define RTL8367D_SVLAN_SP2C_ENTRY45_CTRL1_VALID_MASK 0x1000 +#define RTL8367D_SVLAN_SP2C_ENTRY45_CTRL1_VID_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY45_CTRL1_VID_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY46_CTRL0 0x0f5c +#define RTL8367D_SVLAN_SP2C_ENTRY46_CTRL0_SVID_OFFSET 3 +#define RTL8367D_SVLAN_SP2C_ENTRY46_CTRL0_SVID_MASK 0x7FF8 +#define RTL8367D_SVLAN_SP2C_ENTRY46_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY46_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY46_CTRL1 0x0f5d +#define RTL8367D_SVLAN_SP2C_ENTRY46_CTRL1_VALID_OFFSET 12 +#define RTL8367D_SVLAN_SP2C_ENTRY46_CTRL1_VALID_MASK 0x1000 +#define RTL8367D_SVLAN_SP2C_ENTRY46_CTRL1_VID_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY46_CTRL1_VID_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY47_CTRL0 0x0f5e +#define RTL8367D_SVLAN_SP2C_ENTRY47_CTRL0_SVID_OFFSET 3 +#define RTL8367D_SVLAN_SP2C_ENTRY47_CTRL0_SVID_MASK 0x7FF8 +#define RTL8367D_SVLAN_SP2C_ENTRY47_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY47_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY47_CTRL1 0x0f5f +#define RTL8367D_SVLAN_SP2C_ENTRY47_CTRL1_VALID_OFFSET 12 +#define RTL8367D_SVLAN_SP2C_ENTRY47_CTRL1_VALID_MASK 0x1000 +#define RTL8367D_SVLAN_SP2C_ENTRY47_CTRL1_VID_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY47_CTRL1_VID_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY48_CTRL0 0x0f60 +#define RTL8367D_SVLAN_SP2C_ENTRY48_CTRL0_SVID_OFFSET 3 +#define RTL8367D_SVLAN_SP2C_ENTRY48_CTRL0_SVID_MASK 0x7FF8 +#define RTL8367D_SVLAN_SP2C_ENTRY48_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY48_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY48_CTRL1 0x0f61 +#define RTL8367D_SVLAN_SP2C_ENTRY48_CTRL1_VALID_OFFSET 12 +#define RTL8367D_SVLAN_SP2C_ENTRY48_CTRL1_VALID_MASK 0x1000 +#define RTL8367D_SVLAN_SP2C_ENTRY48_CTRL1_VID_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY48_CTRL1_VID_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY49_CTRL0 0x0f62 +#define RTL8367D_SVLAN_SP2C_ENTRY49_CTRL0_SVID_OFFSET 3 +#define RTL8367D_SVLAN_SP2C_ENTRY49_CTRL0_SVID_MASK 0x7FF8 +#define RTL8367D_SVLAN_SP2C_ENTRY49_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY49_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY49_CTRL1 0x0f63 +#define RTL8367D_SVLAN_SP2C_ENTRY49_CTRL1_VALID_OFFSET 12 +#define RTL8367D_SVLAN_SP2C_ENTRY49_CTRL1_VALID_MASK 0x1000 +#define RTL8367D_SVLAN_SP2C_ENTRY49_CTRL1_VID_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY49_CTRL1_VID_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY50_CTRL0 0x0f64 +#define RTL8367D_SVLAN_SP2C_ENTRY50_CTRL0_SVID_OFFSET 3 +#define RTL8367D_SVLAN_SP2C_ENTRY50_CTRL0_SVID_MASK 0x7FF8 +#define RTL8367D_SVLAN_SP2C_ENTRY50_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY50_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY50_CTRL1 0x0f65 +#define RTL8367D_SVLAN_SP2C_ENTRY50_CTRL1_VALID_OFFSET 12 +#define RTL8367D_SVLAN_SP2C_ENTRY50_CTRL1_VALID_MASK 0x1000 +#define RTL8367D_SVLAN_SP2C_ENTRY50_CTRL1_VID_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY50_CTRL1_VID_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY51_CTRL0 0x0f66 +#define RTL8367D_SVLAN_SP2C_ENTRY51_CTRL0_SVID_OFFSET 3 +#define RTL8367D_SVLAN_SP2C_ENTRY51_CTRL0_SVID_MASK 0x7FF8 +#define RTL8367D_SVLAN_SP2C_ENTRY51_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY51_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY51_CTRL1 0x0f67 +#define RTL8367D_SVLAN_SP2C_ENTRY51_CTRL1_VALID_OFFSET 12 +#define RTL8367D_SVLAN_SP2C_ENTRY51_CTRL1_VALID_MASK 0x1000 +#define RTL8367D_SVLAN_SP2C_ENTRY51_CTRL1_VID_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY51_CTRL1_VID_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY52_CTRL0 0x0f68 +#define RTL8367D_SVLAN_SP2C_ENTRY52_CTRL0_SVID_OFFSET 3 +#define RTL8367D_SVLAN_SP2C_ENTRY52_CTRL0_SVID_MASK 0x7FF8 +#define RTL8367D_SVLAN_SP2C_ENTRY52_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY52_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY52_CTRL1 0x0f69 +#define RTL8367D_SVLAN_SP2C_ENTRY52_CTRL1_VALID_OFFSET 12 +#define RTL8367D_SVLAN_SP2C_ENTRY52_CTRL1_VALID_MASK 0x1000 +#define RTL8367D_SVLAN_SP2C_ENTRY52_CTRL1_VID_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY52_CTRL1_VID_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY53_CTRL0 0x0f6a +#define RTL8367D_SVLAN_SP2C_ENTRY53_CTRL0_SVID_OFFSET 3 +#define RTL8367D_SVLAN_SP2C_ENTRY53_CTRL0_SVID_MASK 0x7FF8 +#define RTL8367D_SVLAN_SP2C_ENTRY53_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY53_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY53_CTRL1 0x0f6b +#define RTL8367D_SVLAN_SP2C_ENTRY53_CTRL1_VALID_OFFSET 12 +#define RTL8367D_SVLAN_SP2C_ENTRY53_CTRL1_VALID_MASK 0x1000 +#define RTL8367D_SVLAN_SP2C_ENTRY53_CTRL1_VID_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY53_CTRL1_VID_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY54_CTRL0 0x0f6c +#define RTL8367D_SVLAN_SP2C_ENTRY54_CTRL0_SVID_OFFSET 3 +#define RTL8367D_SVLAN_SP2C_ENTRY54_CTRL0_SVID_MASK 0x7FF8 +#define RTL8367D_SVLAN_SP2C_ENTRY54_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY54_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY54_CTRL1 0x0f6d +#define RTL8367D_SVLAN_SP2C_ENTRY54_CTRL1_VALID_OFFSET 12 +#define RTL8367D_SVLAN_SP2C_ENTRY54_CTRL1_VALID_MASK 0x1000 +#define RTL8367D_SVLAN_SP2C_ENTRY54_CTRL1_VID_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY54_CTRL1_VID_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY55_CTRL0 0x0f6e +#define RTL8367D_SVLAN_SP2C_ENTRY55_CTRL0_SVID_OFFSET 3 +#define RTL8367D_SVLAN_SP2C_ENTRY55_CTRL0_SVID_MASK 0x7FF8 +#define RTL8367D_SVLAN_SP2C_ENTRY55_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY55_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY55_CTRL1 0x0f6f +#define RTL8367D_SVLAN_SP2C_ENTRY55_CTRL1_VALID_OFFSET 12 +#define RTL8367D_SVLAN_SP2C_ENTRY55_CTRL1_VALID_MASK 0x1000 +#define RTL8367D_SVLAN_SP2C_ENTRY55_CTRL1_VID_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY55_CTRL1_VID_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY56_CTRL0 0x0f70 +#define RTL8367D_SVLAN_SP2C_ENTRY56_CTRL0_SVID_OFFSET 3 +#define RTL8367D_SVLAN_SP2C_ENTRY56_CTRL0_SVID_MASK 0x7FF8 +#define RTL8367D_SVLAN_SP2C_ENTRY56_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY56_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY56_CTRL1 0x0f71 +#define RTL8367D_SVLAN_SP2C_ENTRY56_CTRL1_VALID_OFFSET 12 +#define RTL8367D_SVLAN_SP2C_ENTRY56_CTRL1_VALID_MASK 0x1000 +#define RTL8367D_SVLAN_SP2C_ENTRY56_CTRL1_VID_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY56_CTRL1_VID_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY57_CTRL0 0x0f72 +#define RTL8367D_SVLAN_SP2C_ENTRY57_CTRL0_SVID_OFFSET 3 +#define RTL8367D_SVLAN_SP2C_ENTRY57_CTRL0_SVID_MASK 0x7FF8 +#define RTL8367D_SVLAN_SP2C_ENTRY57_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY57_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY57_CTRL1 0x0f73 +#define RTL8367D_SVLAN_SP2C_ENTRY57_CTRL1_VALID_OFFSET 12 +#define RTL8367D_SVLAN_SP2C_ENTRY57_CTRL1_VALID_MASK 0x1000 +#define RTL8367D_SVLAN_SP2C_ENTRY57_CTRL1_VID_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY57_CTRL1_VID_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY58_CTRL0 0x0f74 +#define RTL8367D_SVLAN_SP2C_ENTRY58_CTRL0_SVID_OFFSET 3 +#define RTL8367D_SVLAN_SP2C_ENTRY58_CTRL0_SVID_MASK 0x7FF8 +#define RTL8367D_SVLAN_SP2C_ENTRY58_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY58_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY58_CTRL1 0x0f75 +#define RTL8367D_SVLAN_SP2C_ENTRY58_CTRL1_VALID_OFFSET 12 +#define RTL8367D_SVLAN_SP2C_ENTRY58_CTRL1_VALID_MASK 0x1000 +#define RTL8367D_SVLAN_SP2C_ENTRY58_CTRL1_VID_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY58_CTRL1_VID_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY59_CTRL0 0x0f76 +#define RTL8367D_SVLAN_SP2C_ENTRY59_CTRL0_SVID_OFFSET 3 +#define RTL8367D_SVLAN_SP2C_ENTRY59_CTRL0_SVID_MASK 0x7FF8 +#define RTL8367D_SVLAN_SP2C_ENTRY59_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY59_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY59_CTRL1 0x0f77 +#define RTL8367D_SVLAN_SP2C_ENTRY59_CTRL1_VALID_OFFSET 12 +#define RTL8367D_SVLAN_SP2C_ENTRY59_CTRL1_VALID_MASK 0x1000 +#define RTL8367D_SVLAN_SP2C_ENTRY59_CTRL1_VID_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY59_CTRL1_VID_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY60_CTRL0 0x0f78 +#define RTL8367D_SVLAN_SP2C_ENTRY60_CTRL0_SVID_OFFSET 3 +#define RTL8367D_SVLAN_SP2C_ENTRY60_CTRL0_SVID_MASK 0x7FF8 +#define RTL8367D_SVLAN_SP2C_ENTRY60_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY60_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY60_CTRL1 0x0f79 +#define RTL8367D_SVLAN_SP2C_ENTRY60_CTRL1_VALID_OFFSET 12 +#define RTL8367D_SVLAN_SP2C_ENTRY60_CTRL1_VALID_MASK 0x1000 +#define RTL8367D_SVLAN_SP2C_ENTRY60_CTRL1_VID_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY60_CTRL1_VID_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY61_CTRL0 0x0f7a +#define RTL8367D_SVLAN_SP2C_ENTRY61_CTRL0_SVID_OFFSET 3 +#define RTL8367D_SVLAN_SP2C_ENTRY61_CTRL0_SVID_MASK 0x7FF8 +#define RTL8367D_SVLAN_SP2C_ENTRY61_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY61_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY61_CTRL1 0x0f7b +#define RTL8367D_SVLAN_SP2C_ENTRY61_CTRL1_VALID_OFFSET 12 +#define RTL8367D_SVLAN_SP2C_ENTRY61_CTRL1_VALID_MASK 0x1000 +#define RTL8367D_SVLAN_SP2C_ENTRY61_CTRL1_VID_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY61_CTRL1_VID_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY62_CTRL0 0x0f7c +#define RTL8367D_SVLAN_SP2C_ENTRY62_CTRL0_SVID_OFFSET 3 +#define RTL8367D_SVLAN_SP2C_ENTRY62_CTRL0_SVID_MASK 0x7FF8 +#define RTL8367D_SVLAN_SP2C_ENTRY62_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY62_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY62_CTRL1 0x0f7d +#define RTL8367D_SVLAN_SP2C_ENTRY62_CTRL1_VALID_OFFSET 12 +#define RTL8367D_SVLAN_SP2C_ENTRY62_CTRL1_VALID_MASK 0x1000 +#define RTL8367D_SVLAN_SP2C_ENTRY62_CTRL1_VID_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY62_CTRL1_VID_MASK 0xFFF + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY63_CTRL0 0x0f7e +#define RTL8367D_SVLAN_SP2C_ENTRY63_CTRL0_SVID_OFFSET 3 +#define RTL8367D_SVLAN_SP2C_ENTRY63_CTRL0_SVID_MASK 0x7FF8 +#define RTL8367D_SVLAN_SP2C_ENTRY63_CTRL0_DST_PORT_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY63_CTRL0_DST_PORT_MASK 0x7 + +#define RTL8367D_REG_SVLAN_SP2C_ENTRY63_CTRL1 0x0f7f +#define RTL8367D_SVLAN_SP2C_ENTRY63_CTRL1_VALID_OFFSET 12 +#define RTL8367D_SVLAN_SP2C_ENTRY63_CTRL1_VALID_MASK 0x1000 +#define RTL8367D_SVLAN_SP2C_ENTRY63_CTRL1_VID_OFFSET 0 +#define RTL8367D_SVLAN_SP2C_ENTRY63_CTRL1_VID_MASK 0xFFF + +/* (16'h1000)mib_reg */ + +#define RTL8367D_REG_MIB_COUNTER0 0x1000 + +#define RTL8367D_REG_MIB_COUNTER1 0x1001 + +#define RTL8367D_REG_MIB_COUNTER2 0x1002 + +#define RTL8367D_REG_MIB_COUNTER3 0x1003 + +#define RTL8367D_REG_MIB_ADDRESS 0x1004 +#define RTL8367D_MIB_ADDRESS_OFFSET 0 +#define RTL8367D_MIB_ADDRESS_MASK 0x1FF + +#define RTL8367D_REG_MIB_CTRL0 0x1005 +#define RTL8367D_RESET_VALUE_OFFSET 12 +#define RTL8367D_RESET_VALUE_MASK 0x1000 +#define RTL8367D_GLOBAL_RESET_OFFSET 11 +#define RTL8367D_GLOBAL_RESET_MASK 0x800 +#define RTL8367D_QM_RESET_OFFSET 10 +#define RTL8367D_QM_RESET_MASK 0x400 +#define RTL8367D_PORT7_RESET_OFFSET 9 +#define RTL8367D_PORT7_RESET_MASK 0x200 +#define RTL8367D_PORT6_RESET_OFFSET 8 +#define RTL8367D_PORT6_RESET_MASK 0x100 +#define RTL8367D_PORT5_RESET_OFFSET 7 +#define RTL8367D_PORT5_RESET_MASK 0x80 +#define RTL8367D_PORT4_RESET_OFFSET 6 +#define RTL8367D_PORT4_RESET_MASK 0x40 +#define RTL8367D_PORT3_RESET_OFFSET 5 +#define RTL8367D_PORT3_RESET_MASK 0x20 +#define RTL8367D_PORT2_RESET_OFFSET 4 +#define RTL8367D_PORT2_RESET_MASK 0x10 +#define RTL8367D_PORT1_RESET_OFFSET 3 +#define RTL8367D_PORT1_RESET_MASK 0x8 +#define RTL8367D_PORT0_RESET_OFFSET 2 +#define RTL8367D_PORT0_RESET_MASK 0x4 +#define RTL8367D_RESET_FLAG_OFFSET 1 +#define RTL8367D_RESET_FLAG_MASK 0x2 +#define RTL8367D_MIB_CTRL0_BUSY_FLAG_OFFSET 0 +#define RTL8367D_MIB_CTRL0_BUSY_FLAG_MASK 0x1 + +#define RTL8367D_REG_MIB_CTRL1 0x1007 +#define RTL8367D_COUNTER15_RESET_OFFSET 15 +#define RTL8367D_COUNTER15_RESET_MASK 0x8000 +#define RTL8367D_COUNTER14_RESET_OFFSET 14 +#define RTL8367D_COUNTER14_RESET_MASK 0x4000 +#define RTL8367D_COUNTER13_RESET_OFFSET 13 +#define RTL8367D_COUNTER13_RESET_MASK 0x2000 +#define RTL8367D_COUNTER12_RESET_OFFSET 12 +#define RTL8367D_COUNTER12_RESET_MASK 0x1000 +#define RTL8367D_COUNTER11_RESET_OFFSET 11 +#define RTL8367D_COUNTER11_RESET_MASK 0x800 +#define RTL8367D_COUNTER10_RESET_OFFSET 10 +#define RTL8367D_COUNTER10_RESET_MASK 0x400 +#define RTL8367D_COUNTER9_RESET_OFFSET 9 +#define RTL8367D_COUNTER9_RESET_MASK 0x200 +#define RTL8367D_COUNTER8_RESET_OFFSET 8 +#define RTL8367D_COUNTER8_RESET_MASK 0x100 +#define RTL8367D_COUNTER7_RESET_OFFSET 7 +#define RTL8367D_COUNTER7_RESET_MASK 0x80 +#define RTL8367D_COUNTER6_RESET_OFFSET 6 +#define RTL8367D_COUNTER6_RESET_MASK 0x40 +#define RTL8367D_COUNTER5_RESET_OFFSET 5 +#define RTL8367D_COUNTER5_RESET_MASK 0x20 +#define RTL8367D_COUNTER4_RESET_OFFSET 4 +#define RTL8367D_COUNTER4_RESET_MASK 0x10 +#define RTL8367D_COUNTER3_RESET_OFFSET 3 +#define RTL8367D_COUNTER3_RESET_MASK 0x8 +#define RTL8367D_COUNTER2_RESET_OFFSET 2 +#define RTL8367D_COUNTER2_RESET_MASK 0x4 +#define RTL8367D_COUNTER1_RESET_OFFSET 1 +#define RTL8367D_COUNTER1_RESET_MASK 0x2 +#define RTL8367D_COUNTER0_RESET_OFFSET 0 +#define RTL8367D_COUNTER0_RESET_MASK 0x1 + +#define RTL8367D_REG_MIB_CTRL3 0x1009 +#define RTL8367D_COUNTER7_MODE_OFFSET 7 +#define RTL8367D_COUNTER7_MODE_MASK 0x80 +#define RTL8367D_COUNTER6_MODE_OFFSET 6 +#define RTL8367D_COUNTER6_MODE_MASK 0x40 +#define RTL8367D_COUNTER5_MODE_OFFSET 5 +#define RTL8367D_COUNTER5_MODE_MASK 0x20 +#define RTL8367D_COUNTER4_MODE_OFFSET 4 +#define RTL8367D_COUNTER4_MODE_MASK 0x10 +#define RTL8367D_COUNTER3_MODE_OFFSET 3 +#define RTL8367D_COUNTER3_MODE_MASK 0x8 +#define RTL8367D_COUNTER2_MODE_OFFSET 2 +#define RTL8367D_COUNTER2_MODE_MASK 0x4 +#define RTL8367D_COUNTER1_MODE_OFFSET 1 +#define RTL8367D_COUNTER1_MODE_MASK 0x2 +#define RTL8367D_COUNTER0_MODE_OFFSET 0 +#define RTL8367D_COUNTER0_MODE_MASK 0x1 + +#define RTL8367D_REG_MIB_CTRL4 0x100a +#define RTL8367D_MIB_USAGE_MODE_OFFSET 8 +#define RTL8367D_MIB_USAGE_MODE_MASK 0x100 +#define RTL8367D_MIB_TIMER_OFFSET 0 +#define RTL8367D_MIB_TIMER_MASK 0xFF + +#define RTL8367D_REG_MIB_CTRL5 0x100b +#define RTL8367D_COUNTER7_TYPE_OFFSET 7 +#define RTL8367D_COUNTER7_TYPE_MASK 0x80 +#define RTL8367D_COUNTER6_TYPE_OFFSET 6 +#define RTL8367D_COUNTER6_TYPE_MASK 0x40 +#define RTL8367D_COUNTER5_TYPE_OFFSET 5 +#define RTL8367D_COUNTER5_TYPE_MASK 0x20 +#define RTL8367D_COUNTER4_TYPE_OFFSET 4 +#define RTL8367D_COUNTER4_TYPE_MASK 0x10 +#define RTL8367D_COUNTER3_TYPE_OFFSET 3 +#define RTL8367D_COUNTER3_TYPE_MASK 0x8 +#define RTL8367D_COUNTER2_TYPE_OFFSET 2 +#define RTL8367D_COUNTER2_TYPE_MASK 0x4 +#define RTL8367D_COUNTER1_TYPE_OFFSET 1 +#define RTL8367D_COUNTER1_TYPE_MASK 0x2 +#define RTL8367D_COUNTER0_TYPE_OFFSET 0 +#define RTL8367D_COUNTER0_TYPE_MASK 0x1 + +/* (16'h1100)intrpt_reg */ + +#define RTL8367D_REG_INTR_CTRL 0x1100 +#define RTL8367D_CFG_INT_TM_NEG_OFFSET 1 +#define RTL8367D_CFG_INT_TM_NEG_MASK 0x2 +#define RTL8367D_INTR_POLARITY_OFFSET 0 +#define RTL8367D_INTR_POLARITY_MASK 0x1 + +#define RTL8367D_REG_INTR_IMR 0x1101 +#define RTL8367D_INTR_IMR_THERMAL_ALARM_OFFSET 12 +#define RTL8367D_INTR_IMR_THERMAL_ALARM_MASK 0x1000 +#define RTL8367D_INTR_IMR_SLIENT_START_OFFSET 11 +#define RTL8367D_INTR_IMR_SLIENT_START_MASK 0x800 +#define RTL8367D_INTR_IMR_ACL_ACTION_OFFSET 9 +#define RTL8367D_INTR_IMR_ACL_ACTION_MASK 0x200 +#define RTL8367D_INTR_IMR_CABLE_DIAG_FIN_OFFSET 8 +#define RTL8367D_INTR_IMR_CABLE_DIAG_FIN_MASK 0x100 +#define RTL8367D_INTR_IMR_INTERRUPT_8051_OFFSET 7 +#define RTL8367D_INTR_IMR_INTERRUPT_8051_MASK 0x80 +#define RTL8367D_INTR_IMR_LOOP_DETECTION_OFFSET 6 +#define RTL8367D_INTR_IMR_LOOP_DETECTION_MASK 0x40 +#define RTL8367D_INTR_IMR_SPECIAL_CONGEST_OFFSET 4 +#define RTL8367D_INTR_IMR_SPECIAL_CONGEST_MASK 0x10 +#define RTL8367D_INTR_IMR_SPEED_CHANGE_OFFSET 3 +#define RTL8367D_INTR_IMR_SPEED_CHANGE_MASK 0x8 +#define RTL8367D_INTR_IMR_LEARN_OVER_OFFSET 2 +#define RTL8367D_INTR_IMR_LEARN_OVER_MASK 0x4 +#define RTL8367D_INTR_IMR_METER_EXCEEDED_OFFSET 1 +#define RTL8367D_INTR_IMR_METER_EXCEEDED_MASK 0x2 +#define RTL8367D_INTR_IMR_LINK_CHANGE_OFFSET 0 +#define RTL8367D_INTR_IMR_LINK_CHANGE_MASK 0x1 + +#define RTL8367D_REG_INTR_IMS 0x1102 +#define RTL8367D_INTR_IMS_THERMAL_ALARM_OFFSET 12 +#define RTL8367D_INTR_IMS_THERMAL_ALARM_MASK 0x1000 +#define RTL8367D_INTR_IMS_SLIENT_START_OFFSET 11 +#define RTL8367D_INTR_IMS_SLIENT_START_MASK 0x800 +#define RTL8367D_INTR_IMS_ACL_ACTION_OFFSET 9 +#define RTL8367D_INTR_IMS_ACL_ACTION_MASK 0x200 +#define RTL8367D_INTR_IMS_CABLE_DIAG_FIN_OFFSET 8 +#define RTL8367D_INTR_IMS_CABLE_DIAG_FIN_MASK 0x100 +#define RTL8367D_INTR_IMS_INTERRUPT_8051_OFFSET 7 +#define RTL8367D_INTR_IMS_INTERRUPT_8051_MASK 0x80 +#define RTL8367D_INTR_IMS_LOOP_DETECTION_OFFSET 6 +#define RTL8367D_INTR_IMS_LOOP_DETECTION_MASK 0x40 +#define RTL8367D_INTR_IMS_SPECIAL_CONGEST_OFFSET 4 +#define RTL8367D_INTR_IMS_SPECIAL_CONGEST_MASK 0x10 +#define RTL8367D_INTR_IMS_SPEED_CHANGE_OFFSET 3 +#define RTL8367D_INTR_IMS_SPEED_CHANGE_MASK 0x8 +#define RTL8367D_INTR_IMS_LEARN_OVER_OFFSET 2 +#define RTL8367D_INTR_IMS_LEARN_OVER_MASK 0x4 +#define RTL8367D_INTR_IMS_METER_EXCEEDED_OFFSET 1 +#define RTL8367D_INTR_IMS_METER_EXCEEDED_MASK 0x2 +#define RTL8367D_INTR_IMS_LINK_CHANGE_OFFSET 0 +#define RTL8367D_INTR_IMS_LINK_CHANGE_MASK 0x1 + +#define RTL8367D_REG_LEARN_OVER_INDICATOR 0x1103 +#define RTL8367D_LEARN_OVER_INDICATOR_OFFSET 0 +#define RTL8367D_LEARN_OVER_INDICATOR_MASK 0xFF + +#define RTL8367D_REG_SPEED_CHANGE_INDICATOR 0x1104 +#define RTL8367D_SPEED_CHANGE_INDICATOR_OFFSET 0 +#define RTL8367D_SPEED_CHANGE_INDICATOR_MASK 0xFF + +#define RTL8367D_REG_SPECIAL_CONGEST_INDICATOR 0x1105 +#define RTL8367D_SPECIAL_CONGEST_INDICATOR_OFFSET 0 +#define RTL8367D_SPECIAL_CONGEST_INDICATOR_MASK 0xFF + +#define RTL8367D_REG_PORT_LINKDOWN_INDICATOR 0x1106 +#define RTL8367D_PORT_LINKDOWN_INDICATOR_OFFSET 0 +#define RTL8367D_PORT_LINKDOWN_INDICATOR_MASK 0xFF + +#define RTL8367D_REG_PORT_LINKUP_INDICATOR 0x1107 +#define RTL8367D_PORT_LINKUP_INDICATOR_OFFSET 0 +#define RTL8367D_PORT_LINKUP_INDICATOR_MASK 0xFF + +#define RTL8367D_REG_SYSTEM_LEARN_OVER_INDICATOR 0x1108 +#define RTL8367D_SYSTEM_LEARN_OVER_INDICATOR_OFFSET 0 +#define RTL8367D_SYSTEM_LEARN_OVER_INDICATOR_MASK 0x1 + +#define RTL8367D_REG_THERMAL_ALARM_INDICATOR 0x1109 +#define RTL8367D_THERMAL_ALARM_INDICATOR_OFFSET 0 +#define RTL8367D_THERMAL_ALARM_INDICATOR_MASK 0xF + +#define RTL8367D_REG_INTR_IMR_8051 0x1118 +#define RTL8367D_INTR_IMR_8051_THERMAL_ALARM_OFFSET 13 +#define RTL8367D_INTR_IMR_8051_THERMAL_ALARM_MASK 0x2000 +#define RTL8367D_INTR_IMR_8051_SLIENT_START_OFFSET 12 +#define RTL8367D_INTR_IMR_8051_SLIENT_START_MASK 0x1000 +#define RTL8367D_INTR_IMR_8051_ACL_ACTION_OFFSET 10 +#define RTL8367D_INTR_IMR_8051_ACL_ACTION_MASK 0x400 +#define RTL8367D_INTR_IMR_8051_SAMOVING_8051_OFFSET 9 +#define RTL8367D_INTR_IMR_8051_SAMOVING_8051_MASK 0x200 +#define RTL8367D_INTR_IMR_8051_CABLE_DIAG_FIN_8051_OFFSET 8 +#define RTL8367D_INTR_IMR_8051_CABLE_DIAG_FIN_8051_MASK 0x100 +#define RTL8367D_INTR_IMR_8051_LOOP_DETECTION_8051_OFFSET 6 +#define RTL8367D_INTR_IMR_8051_LOOP_DETECTION_8051_MASK 0x40 +#define RTL8367D_INTR_IMR_8051_SPECIAL_CONGEST_8051_OFFSET 4 +#define RTL8367D_INTR_IMR_8051_SPECIAL_CONGEST_8051_MASK 0x10 +#define RTL8367D_INTR_IMR_8051_SPEED_CHANGE_8051_OFFSET 3 +#define RTL8367D_INTR_IMR_8051_SPEED_CHANGE_8051_MASK 0x8 +#define RTL8367D_INTR_IMR_8051_LEARN_OVER_8051_OFFSET 2 +#define RTL8367D_INTR_IMR_8051_LEARN_OVER_8051_MASK 0x4 +#define RTL8367D_INTR_IMR_8051_METER_EXCEEDED_8051_OFFSET 1 +#define RTL8367D_INTR_IMR_8051_METER_EXCEEDED_8051_MASK 0x2 +#define RTL8367D_INTR_IMR_8051_LINK_CHANGE_8051_OFFSET 0 +#define RTL8367D_INTR_IMR_8051_LINK_CHANGE_8051_MASK 0x1 + +#define RTL8367D_REG_INTR_IMS_8051 0x1119 +#define RTL8367D_INTR_IMS_8051_THERMAL_ALARM_OFFSET 13 +#define RTL8367D_INTR_IMS_8051_THERMAL_ALARM_MASK 0x2000 +#define RTL8367D_INTR_IMS_8051_SLIENT_START_OFFSET 12 +#define RTL8367D_INTR_IMS_8051_SLIENT_START_MASK 0x1000 +#define RTL8367D_INTR_IMS_8051_ACL_ACTION_OFFSET 10 +#define RTL8367D_INTR_IMS_8051_ACL_ACTION_MASK 0x400 +#define RTL8367D_INTR_IMS_8051_SAMOVING_8051_OFFSET 9 +#define RTL8367D_INTR_IMS_8051_SAMOVING_8051_MASK 0x200 +#define RTL8367D_INTR_IMS_8051_CABLE_DIAG_FIN_8051_OFFSET 8 +#define RTL8367D_INTR_IMS_8051_CABLE_DIAG_FIN_8051_MASK 0x100 +#define RTL8367D_INTR_IMS_8051_LOOP_DETECTION_8051_OFFSET 6 +#define RTL8367D_INTR_IMS_8051_LOOP_DETECTION_8051_MASK 0x40 +#define RTL8367D_INTR_IMS_8051_SPECIAL_CONGEST_8051_OFFSET 4 +#define RTL8367D_INTR_IMS_8051_SPECIAL_CONGEST_8051_MASK 0x10 +#define RTL8367D_INTR_IMS_8051_SPEED_CHANGE_8051_OFFSET 3 +#define RTL8367D_INTR_IMS_8051_SPEED_CHANGE_8051_MASK 0x8 +#define RTL8367D_INTR_IMS_8051_LEARN_OVER_8051_OFFSET 2 +#define RTL8367D_INTR_IMS_8051_LEARN_OVER_8051_MASK 0x4 +#define RTL8367D_INTR_IMS_8051_METER_EXCEEDED_8051_OFFSET 1 +#define RTL8367D_INTR_IMS_8051_METER_EXCEEDED_8051_MASK 0x2 +#define RTL8367D_INTR_IMS_8051_LINK_CHANGE_8051_OFFSET 0 +#define RTL8367D_INTR_IMS_8051_LINK_CHANGE_8051_MASK 0x1 + +#define RTL8367D_REG_DW8051_INT_CPU 0x111a +#define RTL8367D_DW8051_INT_CPU_OFFSET 0 +#define RTL8367D_DW8051_INT_CPU_MASK 0x1 + +#define RTL8367D_REG_LEARN_OVER_INDICATOR_8051 0x1120 +#define RTL8367D_LEARN_OVER_INDICATOR_8051_OFFSET 0 +#define RTL8367D_LEARN_OVER_INDICATOR_8051_MASK 0xFF + +#define RTL8367D_REG_SPEED_CHANGE_INDICATOR_8051 0x1121 +#define RTL8367D_SPEED_CHANGE_INDICATOR_8051_OFFSET 0 +#define RTL8367D_SPEED_CHANGE_INDICATOR_8051_MASK 0xFF + +#define RTL8367D_REG_SPECIAL_CONGEST_INDICATOR_8051 0x1122 +#define RTL8367D_SPECIAL_CONGEST_INDICATOR_8051_OFFSET 0 +#define RTL8367D_SPECIAL_CONGEST_INDICATOR_8051_MASK 0xFF + +#define RTL8367D_REG_PORT_LINKDOWN_INDICATOR_8051 0x1123 +#define RTL8367D_PORT_LINKDOWN_INDICATOR_8051_OFFSET 0 +#define RTL8367D_PORT_LINKDOWN_INDICATOR_8051_MASK 0xFF + +#define RTL8367D_REG_PORT_LINKUP_INDICATOR_8051 0x1124 +#define RTL8367D_PORT_LINKUP_INDICATOR_8051_OFFSET 0 +#define RTL8367D_PORT_LINKUP_INDICATOR_8051_MASK 0xFF + +#define RTL8367D_REG_THERMAL_ALARM_INDICATOR_8051 0x1125 +#define RTL8367D_THERMAL_ALARM_INDICATOR_8051_OFFSET 0 +#define RTL8367D_THERMAL_ALARM_INDICATOR_8051_MASK 0xF + +#define RTL8367D_REG_INTR_IMS_BUFFER_RESET 0x112a +#define RTL8367D_INTR_IMS_BUFFER_RESET_IMR_BUFF_RESET_OFFSET 1 +#define RTL8367D_INTR_IMS_BUFFER_RESET_IMR_BUFF_RESET_MASK 0x2 +#define RTL8367D_INTR_IMS_BUFFER_RESET_BUFFER_RESET_OFFSET 0 +#define RTL8367D_INTR_IMS_BUFFER_RESET_BUFFER_RESET_MASK 0x1 + +#define RTL8367D_REG_INTR_IMS_8051_BUFFER_RESET 0x112b +#define RTL8367D_INTR_IMS_8051_BUFFER_RESET_IMR_BUFF_RESET_OFFSET 1 +#define RTL8367D_INTR_IMS_8051_BUFFER_RESET_IMR_BUFF_RESET_MASK 0x2 +#define RTL8367D_INTR_IMS_8051_BUFFER_RESET_BUFFER_RESET_OFFSET 0 +#define RTL8367D_INTR_IMS_8051_BUFFER_RESET_BUFFER_RESET_MASK 0x1 + +#define RTL8367D_REG_GPHY_INTRPT_8051 0x112c +#define RTL8367D_IMS_GPHY_8051_OFFSET 5 +#define RTL8367D_IMS_GPHY_8051_MASK 0x3E0 +#define RTL8367D_IMR_GPHY_8051_OFFSET 0 +#define RTL8367D_IMR_GPHY_8051_MASK 0x1F + +#define RTL8367D_REG_GPHY_INTRPT 0x112d +#define RTL8367D_IMS_GPHY_OFFSET 5 +#define RTL8367D_IMS_GPHY_MASK 0x3E0 +#define RTL8367D_IMR_GPHY_OFFSET 0 +#define RTL8367D_IMR_GPHY_MASK 0x1F + +/* (16'h1200)swcore_reg */ + +#define RTL8367D_REG_MAX_LENGTH_LIMINT_IPG 0x1200 +#define RTL8367D_EGSFC_SHARE_PKT_THRESHOLD_OFFSET 6 +#define RTL8367D_EGSFC_SHARE_PKT_THRESHOLD_MASK 0x1FC0 +#define RTL8367D_CHECK_MIN_IPG_RXDV_OFFSET 5 +#define RTL8367D_CHECK_MIN_IPG_RXDV_MASK 0x20 +#define RTL8367D_LIMIT_IPG_CFG_OFFSET 0 +#define RTL8367D_LIMIT_IPG_CFG_MASK 0x1F + +#define RTL8367D_REG_IOL_RXDROP_CFG 0x1201 +#define RTL8367D_RX_IOL_MAX_LENGTH_CFG_OFFSET 13 +#define RTL8367D_RX_IOL_MAX_LENGTH_CFG_MASK 0x2000 +#define RTL8367D_RX_IOL_ERROR_LENGTH_CFG_OFFSET 12 +#define RTL8367D_RX_IOL_ERROR_LENGTH_CFG_MASK 0x1000 +#define RTL8367D_RX_NODROP_PAUSE_CFG_OFFSET 8 +#define RTL8367D_RX_NODROP_PAUSE_CFG_MASK 0x100 +#define RTL8367D_RX_DV_CNT_CFG_OFFSET 0 +#define RTL8367D_RX_DV_CNT_CFG_MASK 0x3F + +#define RTL8367D_REG_VS_TPID 0x1202 + +#define RTL8367D_REG_INBW_HBOUND 0x1203 +#define RTL8367D_INBW_HBOUND_OFFSET 0 +#define RTL8367D_INBW_HBOUND_MASK 0xFF + +#define RTL8367D_REG_CFG_TX_ITFSP_OP 0x1204 +#define RTL8367D_MASK_OFFSET 1 +#define RTL8367D_MASK_MASK 0x2 +#define RTL8367D_OP_OFFSET 0 +#define RTL8367D_OP_MASK 0x1 + +#define RTL8367D_REG_INBW_LBOUND 0x1205 +#define RTL8367D_INBW_LBOUND_OFFSET 0 +#define RTL8367D_INBW_LBOUND_MASK 0xFF + +#define RTL8367D_REG_CFG_48PASS1_DROP 0x1206 +#define RTL8367D_CFG_48PASS1_DROP_OFFSET 0 +#define RTL8367D_CFG_48PASS1_DROP_MASK 0x1 + +#define RTL8367D_REG_CFG_BACKPRESSURE 0x1207 +#define RTL8367D_LONGTXE_OFFSET 12 +#define RTL8367D_LONGTXE_MASK 0x1000 +#define RTL8367D_EN_BYPASS_ERROR_OFFSET 8 +#define RTL8367D_EN_BYPASS_ERROR_MASK 0x100 +#define RTL8367D_EN_BACKPRESSURE_OFFSET 4 +#define RTL8367D_EN_BACKPRESSURE_MASK 0x10 +#define RTL8367D_EN_48_PASS_1_OFFSET 0 +#define RTL8367D_EN_48_PASS_1_MASK 0x1 + +#define RTL8367D_REG_CFG_UNHIOL 0x1208 +#define RTL8367D_IOL_BACKOFF_OFFSET 12 +#define RTL8367D_IOL_BACKOFF_MASK 0x1000 +#define RTL8367D_BACKOFF_RANDOM_TIME_OFFSET 8 +#define RTL8367D_BACKOFF_RANDOM_TIME_MASK 0x100 +#define RTL8367D_DISABLE_BACK_OFF_OFFSET 4 +#define RTL8367D_DISABLE_BACK_OFF_MASK 0x10 +#define RTL8367D_IPG_COMPENSATION_OFFSET 0 +#define RTL8367D_IPG_COMPENSATION_MASK 0x1 + +#define RTL8367D_REG_SWITCH_MAC0 0x1209 + +#define RTL8367D_REG_SWITCH_MAC1 0x120a + +#define RTL8367D_REG_SWITCH_MAC2 0x120b + +#define RTL8367D_REG_SWITCH_CTRL0 0x120c +#define RTL8367D_PORT7_REMARKING_DSCP_ENABLE_OFFSET 15 +#define RTL8367D_PORT7_REMARKING_DSCP_ENABLE_MASK 0x8000 +#define RTL8367D_PORT6_REMARKING_DSCP_ENABLE_OFFSET 14 +#define RTL8367D_PORT6_REMARKING_DSCP_ENABLE_MASK 0x4000 +#define RTL8367D_PORT5_REMARKING_DSCP_ENABLE_OFFSET 13 +#define RTL8367D_PORT5_REMARKING_DSCP_ENABLE_MASK 0x2000 +#define RTL8367D_PORT4_REMARKING_DSCP_ENABLE_OFFSET 12 +#define RTL8367D_PORT4_REMARKING_DSCP_ENABLE_MASK 0x1000 +#define RTL8367D_PORT3_REMARKING_DSCP_ENABLE_OFFSET 11 +#define RTL8367D_PORT3_REMARKING_DSCP_ENABLE_MASK 0x800 +#define RTL8367D_PORT2_REMARKING_DSCP_ENABLE_OFFSET 10 +#define RTL8367D_PORT2_REMARKING_DSCP_ENABLE_MASK 0x400 +#define RTL8367D_PORT1_REMARKING_DSCP_ENABLE_OFFSET 9 +#define RTL8367D_PORT1_REMARKING_DSCP_ENABLE_MASK 0x200 +#define RTL8367D_PORT0_REMARKING_DSCP_ENABLE_OFFSET 8 +#define RTL8367D_PORT0_REMARKING_DSCP_ENABLE_MASK 0x100 +#define RTL8367D_SHORT_IPG_OFFSET 4 +#define RTL8367D_SHORT_IPG_MASK 0x10 +#define RTL8367D_PAUSE_MAX128_OFFSET 0 +#define RTL8367D_PAUSE_MAX128_MASK 0x1 + +#define RTL8367D_REG_QOS_DSCP_REMARK_CTRL0 0x120d +#define RTL8367D_INTPRI1_DSCP_OFFSET 8 +#define RTL8367D_INTPRI1_DSCP_MASK 0x3F00 +#define RTL8367D_INTPRI0_DSCP_OFFSET 0 +#define RTL8367D_INTPRI0_DSCP_MASK 0x3F + +#define RTL8367D_REG_QOS_DSCP_REMARK_CTRL1 0x120e +#define RTL8367D_INTPRI3_DSCP_OFFSET 8 +#define RTL8367D_INTPRI3_DSCP_MASK 0x3F00 +#define RTL8367D_INTPRI2_DSCP_OFFSET 0 +#define RTL8367D_INTPRI2_DSCP_MASK 0x3F + +#define RTL8367D_REG_QOS_DSCP_REMARK_CTRL2 0x120f +#define RTL8367D_INTPRI5_DSCP_OFFSET 8 +#define RTL8367D_INTPRI5_DSCP_MASK 0x3F00 +#define RTL8367D_INTPRI4_DSCP_OFFSET 0 +#define RTL8367D_INTPRI4_DSCP_MASK 0x3F + +#define RTL8367D_REG_QOS_DSCP_REMARK_CTRL3 0x1210 +#define RTL8367D_INTPRI7_DSCP_OFFSET 8 +#define RTL8367D_INTPRI7_DSCP_MASK 0x3F00 +#define RTL8367D_INTPRI6_DSCP_OFFSET 0 +#define RTL8367D_INTPRI6_DSCP_MASK 0x3F + +#define RTL8367D_REG_QOS_1Q_REMARK_CTRL0 0x1211 +#define RTL8367D_INTPRI3_PRI_OFFSET 12 +#define RTL8367D_INTPRI3_PRI_MASK 0x7000 +#define RTL8367D_INTPRI2_PRI_OFFSET 8 +#define RTL8367D_INTPRI2_PRI_MASK 0x700 +#define RTL8367D_INTPRI1_PRI_OFFSET 4 +#define RTL8367D_INTPRI1_PRI_MASK 0x70 +#define RTL8367D_INTPRI0_PRI_OFFSET 0 +#define RTL8367D_INTPRI0_PRI_MASK 0x7 + +#define RTL8367D_REG_QOS_1Q_REMARK_CTRL1 0x1212 +#define RTL8367D_INTPRI7_PRI_OFFSET 12 +#define RTL8367D_INTPRI7_PRI_MASK 0x7000 +#define RTL8367D_INTPRI6_PRI_OFFSET 8 +#define RTL8367D_INTPRI6_PRI_MASK 0x700 +#define RTL8367D_INTPRI5_PRI_OFFSET 4 +#define RTL8367D_INTPRI5_PRI_MASK 0x70 +#define RTL8367D_INTPRI4_PRI_OFFSET 0 +#define RTL8367D_INTPRI4_PRI_MASK 0x7 + +#define RTL8367D_REG_PKTGEN_COMMAND 0x1213 +#define RTL8367D_PKTGEN_STOP_OFFSET 8 +#define RTL8367D_PKTGEN_STOP_MASK 0x100 +#define RTL8367D_PKTGEN_START_OFFSET 4 +#define RTL8367D_PKTGEN_START_MASK 0x10 +#define RTL8367D_PKTGEN_BYPASS_FLOWCONTROL_OFFSET 0 +#define RTL8367D_PKTGEN_BYPASS_FLOWCONTROL_MASK 0x1 + +#define RTL8367D_REG_SW_DUMMY0 0x1214 +#define RTL8367D_SW_DUMMY0_DUMMY_OFFSET 4 +#define RTL8367D_SW_DUMMY0_DUMMY_MASK 0xFFF0 +#define RTL8367D_EEE_DEFER_TXLPI_OFFSET 3 +#define RTL8367D_EEE_DEFER_TXLPI_MASK 0x8 +#define RTL8367D_INGRESSBW_BYPASS_EN_OFFSET 2 +#define RTL8367D_INGRESSBW_BYPASS_EN_MASK 0x4 +#define RTL8367D_CFG_RX_MIN_OFFSET 0 +#define RTL8367D_CFG_RX_MIN_MASK 0x3 + +#define RTL8367D_REG_SW_DUMMY1 0x1215 + +#define RTL8367D_REG_PKTGEN_PAUSE_TIME 0x1216 + +#define RTL8367D_REG_SVLAN_UPLINK_PORTMASK 0x1218 +#define RTL8367D_SVLAN_UPLINK_PORTMASK_OFFSET 0 +#define RTL8367D_SVLAN_UPLINK_PORTMASK_MASK 0xFF + +#define RTL8367D_REG_CPU_PORT_MASK 0x1219 +#define RTL8367D_CPU_PORT_MASK_OFFSET 0 +#define RTL8367D_CPU_PORT_MASK_MASK 0xFF + +#define RTL8367D_REG_CPU_CTRL 0x121a +#define RTL8367D_CPU_TAG_FORMAT_PRI_OFFSET 10 +#define RTL8367D_CPU_TAG_FORMAT_PRI_MASK 0x400 +#define RTL8367D_CPU_TAG_FORMAT_OFFSET 9 +#define RTL8367D_CPU_TAG_FORMAT_MASK 0x200 +#define RTL8367D_IOL_16DROP_OFFSET 8 +#define RTL8367D_IOL_16DROP_MASK 0x100 +#define RTL8367D_CPU_TAG_RXBYTECOUNT_OFFSET 7 +#define RTL8367D_CPU_TAG_RXBYTECOUNT_MASK 0x80 +#define RTL8367D_CPU_TAG_POSITION_OFFSET 6 +#define RTL8367D_CPU_TAG_POSITION_MASK 0x40 +#define RTL8367D_CPU_TRAP_PORT_OFFSET 3 +#define RTL8367D_CPU_TRAP_PORT_MASK 0x38 +#define RTL8367D_CPU_INSERTMODE_OFFSET 1 +#define RTL8367D_CPU_INSERTMODE_MASK 0x6 +#define RTL8367D_CPU_EN_OFFSET 0 +#define RTL8367D_CPU_EN_MASK 0x1 + +#define RTL8367D_REG_MIRROR_CTRL 0x121c +#define RTL8367D_MIRROR_CTRL_DUMMY_OFFSET 12 +#define RTL8367D_MIRROR_CTRL_DUMMY_MASK 0xF000 +#define RTL8367D_MIRROR_ISO_OFFSET 11 +#define RTL8367D_MIRROR_ISO_MASK 0x800 +#define RTL8367D_MIRROR_MONITOR_PORT_OFFSET 4 +#define RTL8367D_MIRROR_MONITOR_PORT_MASK 0x70 + +#define RTL8367D_REG_FLOWCTRL_CTRL0 0x121d +#define RTL8367D_DROP_ALL_THRESHOLD_OFFSET 5 +#define RTL8367D_DROP_ALL_THRESHOLD_MASK 0xFFE0 +#define RTL8367D_ITFSP_REG_OFFSET 0 +#define RTL8367D_ITFSP_REG_MASK 0x7 + +#define RTL8367D_REG_FLOWCTRL_ALL_ON 0x121e +#define RTL8367D_CFG_RLDPACT_OFFSET 12 +#define RTL8367D_CFG_RLDPACT_MASK 0x1000 +#define RTL8367D_FLOWCTRL_ALL_ON_THRESHOLD_OFFSET 0 +#define RTL8367D_FLOWCTRL_ALL_ON_THRESHOLD_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_SYS_ON 0x121f +#define RTL8367D_FLOWCTRL_SYS_ON_OFFSET 0 +#define RTL8367D_FLOWCTRL_SYS_ON_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_SYS_OFF 0x1220 +#define RTL8367D_FLOWCTRL_SYS_OFF_OFFSET 0 +#define RTL8367D_FLOWCTRL_SYS_OFF_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_SHARE_ON 0x1221 +#define RTL8367D_FLOWCTRL_SHARE_ON_OFFSET 0 +#define RTL8367D_FLOWCTRL_SHARE_ON_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_SHARE_OFF 0x1222 +#define RTL8367D_FLOWCTRL_SHARE_OFF_OFFSET 0 +#define RTL8367D_FLOWCTRL_SHARE_OFF_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_FCOFF_SYS_ON 0x1223 +#define RTL8367D_FLOWCTRL_FCOFF_SYS_ON_OFFSET 0 +#define RTL8367D_FLOWCTRL_FCOFF_SYS_ON_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_FCOFF_SYS_OFF 0x1224 +#define RTL8367D_FLOWCTRL_FCOFF_SYS_OFF_OFFSET 0 +#define RTL8367D_FLOWCTRL_FCOFF_SYS_OFF_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_FCOFF_SHARE_ON 0x1225 +#define RTL8367D_FLOWCTRL_FCOFF_SHARE_ON_OFFSET 0 +#define RTL8367D_FLOWCTRL_FCOFF_SHARE_ON_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_FCOFF_SHARE_OFF 0x1226 +#define RTL8367D_FLOWCTRL_FCOFF_SHARE_OFF_OFFSET 0 +#define RTL8367D_FLOWCTRL_FCOFF_SHARE_OFF_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_PORT_ON 0x1227 +#define RTL8367D_FLOWCTRL_PORT_ON_OFFSET 0 +#define RTL8367D_FLOWCTRL_PORT_ON_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_PORT_OFF 0x1228 +#define RTL8367D_FLOWCTRL_PORT_OFF_OFFSET 0 +#define RTL8367D_FLOWCTRL_PORT_OFF_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_PORT_PRIVATE_ON 0x1229 +#define RTL8367D_FLOWCTRL_PORT_PRIVATE_ON_OFFSET 0 +#define RTL8367D_FLOWCTRL_PORT_PRIVATE_ON_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_PORT_PRIVATE_OFF 0x122a +#define RTL8367D_FLOWCTRL_PORT_PRIVATE_OFF_OFFSET 0 +#define RTL8367D_FLOWCTRL_PORT_PRIVATE_OFF_MASK 0x7FF + +#define RTL8367D_REG_RRCP_CTRL0 0x122b +#define RTL8367D_OCPDIR_EN_OFFSET 15 +#define RTL8367D_OCPDIR_EN_MASK 0x8000 +#define RTL8367D_COL_SEL_OFFSET 14 +#define RTL8367D_COL_SEL_MASK 0x4000 +#define RTL8367D_CRS_SEL_OFFSET 13 +#define RTL8367D_CRS_SEL_MASK 0x2000 + +#define RTL8367D_REG_FLOWCTRL_FCOFF_PORT_ON 0x122f +#define RTL8367D_FLOWCTRL_FCOFF_PORT_ON_OFFSET 0 +#define RTL8367D_FLOWCTRL_FCOFF_PORT_ON_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_FCOFF_PORT_OFF 0x1230 +#define RTL8367D_FLOWCTRL_FCOFF_PORT_OFF_OFFSET 0 +#define RTL8367D_FLOWCTRL_FCOFF_PORT_OFF_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_FCOFF_PORT_PRIVATE_ON 0x1231 +#define RTL8367D_FLOWCTRL_FCOFF_PORT_PRIVATE_ON_OFFSET 0 +#define RTL8367D_FLOWCTRL_FCOFF_PORT_PRIVATE_ON_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_FCOFF_PORT_PRIVATE_OFF 0x1232 +#define RTL8367D_FLOWCTRL_FCOFF_PORT_PRIVATE_OFF_OFFSET 0 +#define RTL8367D_FLOWCTRL_FCOFF_PORT_PRIVATE_OFF_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_JUMBO_SYS_ON 0x1233 +#define RTL8367D_FLOWCTRL_JUMBO_SYS_ON_OFFSET 0 +#define RTL8367D_FLOWCTRL_JUMBO_SYS_ON_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_JUMBO_SYS_OFF 0x1234 +#define RTL8367D_FLOWCTRL_JUMBO_SYS_OFF_OFFSET 0 +#define RTL8367D_FLOWCTRL_JUMBO_SYS_OFF_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_JUMBO_SHARE_ON 0x1235 +#define RTL8367D_FLOWCTRL_JUMBO_SHARE_ON_OFFSET 0 +#define RTL8367D_FLOWCTRL_JUMBO_SHARE_ON_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_JUMBO_SHARE_OFF 0x1236 +#define RTL8367D_FLOWCTRL_JUMBO_SHARE_OFF_OFFSET 0 +#define RTL8367D_FLOWCTRL_JUMBO_SHARE_OFF_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_JUMBO_PORT_ON 0x1237 +#define RTL8367D_FLOWCTRL_JUMBO_PORT_ON_OFFSET 0 +#define RTL8367D_FLOWCTRL_JUMBO_PORT_ON_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_JUMBO_PORT_OFF 0x1238 +#define RTL8367D_FLOWCTRL_JUMBO_PORT_OFF_OFFSET 0 +#define RTL8367D_FLOWCTRL_JUMBO_PORT_OFF_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_JUMBO_PORT_PRIVATE_ON 0x1239 +#define RTL8367D_FLOWCTRL_JUMBO_PORT_PRIVATE_ON_OFFSET 0 +#define RTL8367D_FLOWCTRL_JUMBO_PORT_PRIVATE_ON_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_JUMBO_PORT_PRIVATE_OFF 0x123a +#define RTL8367D_FLOWCTRL_JUMBO_PORT_PRIVATE_OFF_OFFSET 0 +#define RTL8367D_FLOWCTRL_JUMBO_PORT_PRIVATE_OFF_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_JUMBO_SIZE 0x123b +#define RTL8367D_JUMBO_MODE_OFFSET 2 +#define RTL8367D_JUMBO_MODE_MASK 0x4 +#define RTL8367D_JUMBO_SIZE_OFFSET 0 +#define RTL8367D_JUMBO_SIZE_MASK 0x3 + +#define RTL8367D_REG_FLOWCTRL_TOTAL_PAGE_COUNTER 0x124c +#define RTL8367D_FLOWCTRL_TOTAL_PAGE_COUNTER_OFFSET 0 +#define RTL8367D_FLOWCTRL_TOTAL_PAGE_COUNTER_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_PUBLIC_PAGE_COUNTER 0x124d +#define RTL8367D_FLOWCTRL_PUBLIC_PAGE_COUNTER_OFFSET 0 +#define RTL8367D_FLOWCTRL_PUBLIC_PAGE_COUNTER_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_TOTAL_PAGE_MAX 0x124e +#define RTL8367D_FLOWCTRL_TOTAL_PAGE_MAX_OFFSET 0 +#define RTL8367D_FLOWCTRL_TOTAL_PAGE_MAX_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_PUBLIC_PAGE_MAX 0x124f +#define RTL8367D_FLOWCTRL_PUBLIC_PAGE_MAX_OFFSET 0 +#define RTL8367D_FLOWCTRL_PUBLIC_PAGE_MAX_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_PORT0_PAGE_COUNTER 0x1250 +#define RTL8367D_FLOWCTRL_PORT0_PAGE_COUNTER_OFFSET 0 +#define RTL8367D_FLOWCTRL_PORT0_PAGE_COUNTER_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_PORT1_PAGE_COUNTER 0x1251 +#define RTL8367D_FLOWCTRL_PORT1_PAGE_COUNTER_OFFSET 0 +#define RTL8367D_FLOWCTRL_PORT1_PAGE_COUNTER_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_PORT2_PAGE_COUNTER 0x1252 +#define RTL8367D_FLOWCTRL_PORT2_PAGE_COUNTER_OFFSET 0 +#define RTL8367D_FLOWCTRL_PORT2_PAGE_COUNTER_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_PORT3_PAGE_COUNTER 0x1253 +#define RTL8367D_FLOWCTRL_PORT3_PAGE_COUNTER_OFFSET 0 +#define RTL8367D_FLOWCTRL_PORT3_PAGE_COUNTER_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_PORT4_PAGE_COUNTER 0x1254 +#define RTL8367D_FLOWCTRL_PORT4_PAGE_COUNTER_OFFSET 0 +#define RTL8367D_FLOWCTRL_PORT4_PAGE_COUNTER_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_PORT5_PAGE_COUNTER 0x1255 +#define RTL8367D_FLOWCTRL_PORT5_PAGE_COUNTER_OFFSET 0 +#define RTL8367D_FLOWCTRL_PORT5_PAGE_COUNTER_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_PORT6_PAGE_COUNTER 0x1256 +#define RTL8367D_FLOWCTRL_PORT6_PAGE_COUNTER_OFFSET 0 +#define RTL8367D_FLOWCTRL_PORT6_PAGE_COUNTER_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_PORT7_PAGE_COUNTER 0x1257 +#define RTL8367D_FLOWCTRL_PORT7_PAGE_COUNTER_OFFSET 0 +#define RTL8367D_FLOWCTRL_PORT7_PAGE_COUNTER_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_PUBLIC_FCOFF_PAGE_COUNTER 0x1258 +#define RTL8367D_FLOWCTRL_PUBLIC_FCOFF_PAGE_COUNTER_OFFSET 0 +#define RTL8367D_FLOWCTRL_PUBLIC_FCOFF_PAGE_COUNTER_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_PUBLIC_JUMBO_PAGE_COUNTER 0x1259 +#define RTL8367D_FLOWCTRL_PUBLIC_JUMBO_PAGE_COUNTER_OFFSET 0 +#define RTL8367D_FLOWCTRL_PUBLIC_JUMBO_PAGE_COUNTER_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_MAX_PUBLIC_FCOFF_PAGE_COUNTER 0x125a +#define RTL8367D_FLOWCTRL_MAX_PUBLIC_FCOFF_PAGE_COUNTER_OFFSET 0 +#define RTL8367D_FLOWCTRL_MAX_PUBLIC_FCOFF_PAGE_COUNTER_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_MAX_PUBLIC_JUMBO_PAGE_COUNTER 0x125b +#define RTL8367D_FLOWCTRL_MAX_PUBLIC_JUMBO_PAGE_COUNTER_OFFSET 0 +#define RTL8367D_FLOWCTRL_MAX_PUBLIC_JUMBO_PAGE_COUNTER_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_PORT0_PAGE_MAX 0x1260 +#define RTL8367D_FLOWCTRL_PORT0_PAGE_MAX_OFFSET 0 +#define RTL8367D_FLOWCTRL_PORT0_PAGE_MAX_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_PORT1_PAGE_MAX 0x1261 +#define RTL8367D_FLOWCTRL_PORT1_PAGE_MAX_OFFSET 0 +#define RTL8367D_FLOWCTRL_PORT1_PAGE_MAX_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_PORT2_PAGE_MAX 0x1262 +#define RTL8367D_FLOWCTRL_PORT2_PAGE_MAX_OFFSET 0 +#define RTL8367D_FLOWCTRL_PORT2_PAGE_MAX_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_PORT3_PAGE_MAX 0x1263 +#define RTL8367D_FLOWCTRL_PORT3_PAGE_MAX_OFFSET 0 +#define RTL8367D_FLOWCTRL_PORT3_PAGE_MAX_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_PORT4_PAGE_MAX 0x1264 +#define RTL8367D_FLOWCTRL_PORT4_PAGE_MAX_OFFSET 0 +#define RTL8367D_FLOWCTRL_PORT4_PAGE_MAX_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_PORT5_PAGE_MAX 0x1265 +#define RTL8367D_FLOWCTRL_PORT5_PAGE_MAX_OFFSET 0 +#define RTL8367D_FLOWCTRL_PORT5_PAGE_MAX_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_PORT6_PAGE_MAX 0x1266 +#define RTL8367D_FLOWCTRL_PORT6_PAGE_MAX_OFFSET 0 +#define RTL8367D_FLOWCTRL_PORT6_PAGE_MAX_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_PORT7_PAGE_MAX 0x1267 +#define RTL8367D_FLOWCTRL_PORT7_PAGE_MAX_OFFSET 0 +#define RTL8367D_FLOWCTRL_PORT7_PAGE_MAX_MASK 0x7FF + +#define RTL8367D_REG_FLOWCTRL_PAGE_COUNT_CLEAR 0x1268 +#define RTL8367D_DIS_SKIP_FP_OFFSET 1 +#define RTL8367D_DIS_SKIP_FP_MASK 0x2 +#define RTL8367D_PAGE_COUNT_CLEAR_OFFSET 0 +#define RTL8367D_PAGE_COUNT_CLEAR_MASK 0x1 + +#define RTL8367D_REG_WOL_CFG 0x1270 +#define RTL8367D_WOL_EN_OFFSET 8 +#define RTL8367D_WOL_EN_MASK 0x100 +#define RTL8367D_WOL_RX_MGGIC_PORTMASK_OFFSET 0 +#define RTL8367D_WOL_RX_MGGIC_PORTMASK_MASK 0xFF + +#define RTL8367D_REG_WOL_MAC0 0x1271 + +#define RTL8367D_REG_WOL_MAC1 0x1272 + +#define RTL8367D_REG_WOL_MAC2 0x1273 + +#define RTL8367D_REG_MIB_RMON_LEN_CTRL 0x128a +#define RTL8367D_RX_LENGTH_CTRL_OFFSET 1 +#define RTL8367D_RX_LENGTH_CTRL_MASK 0x2 +#define RTL8367D_TX_LENGTH_CTRL_OFFSET 0 +#define RTL8367D_TX_LENGTH_CTRL_MASK 0x1 + +#define RTL8367D_REG_CHG_DUPLEX_CFG 0x1296 +#define RTL8367D_CFG_CHG_DUP_EN_OFFSET 7 +#define RTL8367D_CFG_CHG_DUP_EN_MASK 0x80 +#define RTL8367D_CFG_CHG_DUP_THR_OFFSET 2 +#define RTL8367D_CFG_CHG_DUP_THR_MASK 0x7C +#define RTL8367D_CFG_CHG_DUP_CONGEST_OFFSET 1 +#define RTL8367D_CFG_CHG_DUP_CONGEST_MASK 0x2 + +#define RTL8367D_REG_RX_FC_REG 0x12aa +#define RTL8367D_RX_FC_REG_OFFSET 0 +#define RTL8367D_RX_FC_REG_MASK 0xFF + +#define RTL8367D_REG_MAX_FIFO_SIZE 0x12af +#define RTL8367D_MAX_FIFO_SIZE_OFFSET 0 +#define RTL8367D_MAX_FIFO_SIZE_MASK 0xF + +#define RTL8367D_REG_DUMMY_REG_12_2 0x12b2 + +#define RTL8367D_REG_BACK_PRESSURE_IPG 0x12be +#define RTL8367D_FIX_PAUSE_ISSUE_OFFSET 3 +#define RTL8367D_FIX_PAUSE_ISSUE_MASK 0x8 +#define RTL8367D_REPLACE_L3_CRC_OFFSET 2 +#define RTL8367D_REPLACE_L3_CRC_MASK 0x4 +#define RTL8367D_IPG_BIT_TIME_OFFSET 0 +#define RTL8367D_IPG_BIT_TIME_MASK 0x3 + +#define RTL8367D_REG_TX_ESD_LEVEL 0x12bf +#define RTL8367D_TX_ESD_LEVEL_MODE_OFFSET 8 +#define RTL8367D_TX_ESD_LEVEL_MODE_MASK 0x100 +#define RTL8367D_LEVEL_OFFSET 0 +#define RTL8367D_LEVEL_MASK 0xFF + +#define RTL8367D_REG_MAC0_FORCE_SELECT 0x12c0 +#define RTL8367D_MAC0_FORCE_SELECT_EEE_ABLTY_OFFSET 15 +#define RTL8367D_MAC0_FORCE_SELECT_EEE_ABLTY_MASK 0x8000 +#define RTL8367D_MAC0_FORCE_SELECT_UNUSED_OFFSET 14 +#define RTL8367D_MAC0_FORCE_SELECT_UNUSED_MASK 0x4000 +#define RTL8367D_MAC0_FORCE_SELECT_SPEED23_ABLTY_OFFSET 12 +#define RTL8367D_MAC0_FORCE_SELECT_SPEED23_ABLTY_MASK 0x3000 +#define RTL8367D_MAC0_FORCE_SELECT_LPI_1000_ABLTY_OFFSET 11 +#define RTL8367D_MAC0_FORCE_SELECT_LPI_1000_ABLTY_MASK 0x800 +#define RTL8367D_MAC0_FORCE_SELECT_LPI_100_ABLTY_OFFSET 10 +#define RTL8367D_MAC0_FORCE_SELECT_LPI_100_ABLTY_MASK 0x400 +#define RTL8367D_MAC0_FORCE_SELECT_MST_FAULT_ABLTY_OFFSET 9 +#define RTL8367D_MAC0_FORCE_SELECT_MST_FAULT_ABLTY_MASK 0x200 +#define RTL8367D_MAC0_FORCE_SELECT_MST_MOD_ABLTY_OFFSET 8 +#define RTL8367D_MAC0_FORCE_SELECT_MST_MOD_ABLTY_MASK 0x100 +#define RTL8367D_MAC0_FORCE_SELECT_NWAY_ABLTY_OFFSET 7 +#define RTL8367D_MAC0_FORCE_SELECT_NWAY_ABLTY_MASK 0x80 +#define RTL8367D_MAC0_FORCE_SELECT_TXPAUSE_ABLTY_OFFSET 6 +#define RTL8367D_MAC0_FORCE_SELECT_TXPAUSE_ABLTY_MASK 0x40 +#define RTL8367D_MAC0_FORCE_SELECT_RXPAUSE_ABLTY_OFFSET 5 +#define RTL8367D_MAC0_FORCE_SELECT_RXPAUSE_ABLTY_MASK 0x20 +#define RTL8367D_MAC0_FORCE_SELECT_LINK_ABLTY_OFFSET 4 +#define RTL8367D_MAC0_FORCE_SELECT_LINK_ABLTY_MASK 0x10 +#define RTL8367D_MAC0_FORCE_SELECT_FIB1G_ABLTY_OFFSET 3 +#define RTL8367D_MAC0_FORCE_SELECT_FIB1G_ABLTY_MASK 0x8 +#define RTL8367D_MAC0_FORCE_SELECT_DUPLEX_ABLTY_OFFSET 2 +#define RTL8367D_MAC0_FORCE_SELECT_DUPLEX_ABLTY_MASK 0x4 +#define RTL8367D_MAC0_FORCE_SELECT_SPEED01_ABLTY_OFFSET 0 +#define RTL8367D_MAC0_FORCE_SELECT_SPEED01_ABLTY_MASK 0x3 + +#define RTL8367D_REG_MAC1_FORCE_SELECT 0x12c1 +#define RTL8367D_MAC1_FORCE_SELECT_EEE_ABLTY_OFFSET 15 +#define RTL8367D_MAC1_FORCE_SELECT_EEE_ABLTY_MASK 0x8000 +#define RTL8367D_MAC1_FORCE_SELECT_UNUSED_OFFSET 14 +#define RTL8367D_MAC1_FORCE_SELECT_UNUSED_MASK 0x4000 +#define RTL8367D_MAC1_FORCE_SELECT_SPEED23_ABLTY_OFFSET 12 +#define RTL8367D_MAC1_FORCE_SELECT_SPEED23_ABLTY_MASK 0x3000 +#define RTL8367D_MAC1_FORCE_SELECT_LPI_1000_ABLTY_OFFSET 11 +#define RTL8367D_MAC1_FORCE_SELECT_LPI_1000_ABLTY_MASK 0x800 +#define RTL8367D_MAC1_FORCE_SELECT_LPI_100_ABLTY_OFFSET 10 +#define RTL8367D_MAC1_FORCE_SELECT_LPI_100_ABLTY_MASK 0x400 +#define RTL8367D_MAC1_FORCE_SELECT_MST_FAULT_ABLTY_OFFSET 9 +#define RTL8367D_MAC1_FORCE_SELECT_MST_FAULT_ABLTY_MASK 0x200 +#define RTL8367D_MAC1_FORCE_SELECT_MST_MOD_ABLTY_OFFSET 8 +#define RTL8367D_MAC1_FORCE_SELECT_MST_MOD_ABLTY_MASK 0x100 +#define RTL8367D_MAC1_FORCE_SELECT_NWAY_ABLTY_OFFSET 7 +#define RTL8367D_MAC1_FORCE_SELECT_NWAY_ABLTY_MASK 0x80 +#define RTL8367D_MAC1_FORCE_SELECT_TXPAUSE_ABLTY_OFFSET 6 +#define RTL8367D_MAC1_FORCE_SELECT_TXPAUSE_ABLTY_MASK 0x40 +#define RTL8367D_MAC1_FORCE_SELECT_RXPAUSE_ABLTY_OFFSET 5 +#define RTL8367D_MAC1_FORCE_SELECT_RXPAUSE_ABLTY_MASK 0x20 +#define RTL8367D_MAC1_FORCE_SELECT_LINK_ABLTY_OFFSET 4 +#define RTL8367D_MAC1_FORCE_SELECT_LINK_ABLTY_MASK 0x10 +#define RTL8367D_MAC1_FORCE_SELECT_FIB1G_ABLTY_OFFSET 3 +#define RTL8367D_MAC1_FORCE_SELECT_FIB1G_ABLTY_MASK 0x8 +#define RTL8367D_MAC1_FORCE_SELECT_DUPLEX_ABLTY_OFFSET 2 +#define RTL8367D_MAC1_FORCE_SELECT_DUPLEX_ABLTY_MASK 0x4 +#define RTL8367D_MAC1_FORCE_SELECT_SPEED01_ABLTY_OFFSET 0 +#define RTL8367D_MAC1_FORCE_SELECT_SPEED01_ABLTY_MASK 0x3 + +#define RTL8367D_REG_MAC2_FORCE_SELECT 0x12c2 +#define RTL8367D_MAC2_FORCE_SELECT_EEE_ABLTY_OFFSET 15 +#define RTL8367D_MAC2_FORCE_SELECT_EEE_ABLTY_MASK 0x8000 +#define RTL8367D_MAC2_FORCE_SELECT_UNUSED_OFFSET 14 +#define RTL8367D_MAC2_FORCE_SELECT_UNUSED_MASK 0x4000 +#define RTL8367D_MAC2_FORCE_SELECT_SPEED23_ABLTY_OFFSET 12 +#define RTL8367D_MAC2_FORCE_SELECT_SPEED23_ABLTY_MASK 0x3000 +#define RTL8367D_MAC2_FORCE_SELECT_LPI_1000_ABLTY_OFFSET 11 +#define RTL8367D_MAC2_FORCE_SELECT_LPI_1000_ABLTY_MASK 0x800 +#define RTL8367D_MAC2_FORCE_SELECT_LPI_100_ABLTY_OFFSET 10 +#define RTL8367D_MAC2_FORCE_SELECT_LPI_100_ABLTY_MASK 0x400 +#define RTL8367D_MAC2_FORCE_SELECT_MST_FAULT_ABLTY_OFFSET 9 +#define RTL8367D_MAC2_FORCE_SELECT_MST_FAULT_ABLTY_MASK 0x200 +#define RTL8367D_MAC2_FORCE_SELECT_MST_MOD_ABLTY_OFFSET 8 +#define RTL8367D_MAC2_FORCE_SELECT_MST_MOD_ABLTY_MASK 0x100 +#define RTL8367D_MAC2_FORCE_SELECT_NWAY_ABLTY_OFFSET 7 +#define RTL8367D_MAC2_FORCE_SELECT_NWAY_ABLTY_MASK 0x80 +#define RTL8367D_MAC2_FORCE_SELECT_TXPAUSE_ABLTY_OFFSET 6 +#define RTL8367D_MAC2_FORCE_SELECT_TXPAUSE_ABLTY_MASK 0x40 +#define RTL8367D_MAC2_FORCE_SELECT_RXPAUSE_ABLTY_OFFSET 5 +#define RTL8367D_MAC2_FORCE_SELECT_RXPAUSE_ABLTY_MASK 0x20 +#define RTL8367D_MAC2_FORCE_SELECT_LINK_ABLTY_OFFSET 4 +#define RTL8367D_MAC2_FORCE_SELECT_LINK_ABLTY_MASK 0x10 +#define RTL8367D_MAC2_FORCE_SELECT_FIB1G_ABLTY_OFFSET 3 +#define RTL8367D_MAC2_FORCE_SELECT_FIB1G_ABLTY_MASK 0x8 +#define RTL8367D_MAC2_FORCE_SELECT_DUPLEX_ABLTY_OFFSET 2 +#define RTL8367D_MAC2_FORCE_SELECT_DUPLEX_ABLTY_MASK 0x4 +#define RTL8367D_MAC2_FORCE_SELECT_SPEED01_ABLTY_OFFSET 0 +#define RTL8367D_MAC2_FORCE_SELECT_SPEED01_ABLTY_MASK 0x3 + +#define RTL8367D_REG_MAC3_FORCE_SELECT 0x12c3 +#define RTL8367D_MAC3_FORCE_SELECT_EEE_ABLTY_OFFSET 15 +#define RTL8367D_MAC3_FORCE_SELECT_EEE_ABLTY_MASK 0x8000 +#define RTL8367D_MAC3_FORCE_SELECT_UNUSED_OFFSET 14 +#define RTL8367D_MAC3_FORCE_SELECT_UNUSED_MASK 0x4000 +#define RTL8367D_MAC3_FORCE_SELECT_SPEED23_ABLTY_OFFSET 12 +#define RTL8367D_MAC3_FORCE_SELECT_SPEED23_ABLTY_MASK 0x3000 +#define RTL8367D_MAC3_FORCE_SELECT_LPI_1000_ABLTY_OFFSET 11 +#define RTL8367D_MAC3_FORCE_SELECT_LPI_1000_ABLTY_MASK 0x800 +#define RTL8367D_MAC3_FORCE_SELECT_LPI_100_ABLTY_OFFSET 10 +#define RTL8367D_MAC3_FORCE_SELECT_LPI_100_ABLTY_MASK 0x400 +#define RTL8367D_MAC3_FORCE_SELECT_MST_FAULT_ABLTY_OFFSET 9 +#define RTL8367D_MAC3_FORCE_SELECT_MST_FAULT_ABLTY_MASK 0x200 +#define RTL8367D_MAC3_FORCE_SELECT_MST_MOD_ABLTY_OFFSET 8 +#define RTL8367D_MAC3_FORCE_SELECT_MST_MOD_ABLTY_MASK 0x100 +#define RTL8367D_MAC3_FORCE_SELECT_NWAY_ABLTY_OFFSET 7 +#define RTL8367D_MAC3_FORCE_SELECT_NWAY_ABLTY_MASK 0x80 +#define RTL8367D_MAC3_FORCE_SELECT_TXPAUSE_ABLTY_OFFSET 6 +#define RTL8367D_MAC3_FORCE_SELECT_TXPAUSE_ABLTY_MASK 0x40 +#define RTL8367D_MAC3_FORCE_SELECT_RXPAUSE_ABLTY_OFFSET 5 +#define RTL8367D_MAC3_FORCE_SELECT_RXPAUSE_ABLTY_MASK 0x20 +#define RTL8367D_MAC3_FORCE_SELECT_LINK_ABLTY_OFFSET 4 +#define RTL8367D_MAC3_FORCE_SELECT_LINK_ABLTY_MASK 0x10 +#define RTL8367D_MAC3_FORCE_SELECT_FIB1G_ABLTY_OFFSET 3 +#define RTL8367D_MAC3_FORCE_SELECT_FIB1G_ABLTY_MASK 0x8 +#define RTL8367D_MAC3_FORCE_SELECT_DUPLEX_ABLTY_OFFSET 2 +#define RTL8367D_MAC3_FORCE_SELECT_DUPLEX_ABLTY_MASK 0x4 +#define RTL8367D_MAC3_FORCE_SELECT_SPEED01_ABLTY_OFFSET 0 +#define RTL8367D_MAC3_FORCE_SELECT_SPEED01_ABLTY_MASK 0x3 + +#define RTL8367D_REG_MAC4_FORCE_SELECT 0x12c4 +#define RTL8367D_MAC4_FORCE_SELECT_EEE_ABLTY_OFFSET 15 +#define RTL8367D_MAC4_FORCE_SELECT_EEE_ABLTY_MASK 0x8000 +#define RTL8367D_MAC4_FORCE_SELECT_UNUSED_OFFSET 14 +#define RTL8367D_MAC4_FORCE_SELECT_UNUSED_MASK 0x4000 +#define RTL8367D_MAC4_FORCE_SELECT_SPEED23_ABLTY_OFFSET 12 +#define RTL8367D_MAC4_FORCE_SELECT_SPEED23_ABLTY_MASK 0x3000 +#define RTL8367D_MAC4_FORCE_SELECT_LPI_1000_ABLTY_OFFSET 11 +#define RTL8367D_MAC4_FORCE_SELECT_LPI_1000_ABLTY_MASK 0x800 +#define RTL8367D_MAC4_FORCE_SELECT_LPI_100_ABLTY_OFFSET 10 +#define RTL8367D_MAC4_FORCE_SELECT_LPI_100_ABLTY_MASK 0x400 +#define RTL8367D_MAC4_FORCE_SELECT_MST_FAULT_ABLTY_OFFSET 9 +#define RTL8367D_MAC4_FORCE_SELECT_MST_FAULT_ABLTY_MASK 0x200 +#define RTL8367D_MAC4_FORCE_SELECT_MST_MOD_ABLTY_OFFSET 8 +#define RTL8367D_MAC4_FORCE_SELECT_MST_MOD_ABLTY_MASK 0x100 +#define RTL8367D_MAC4_FORCE_SELECT_NWAY_ABLTY_OFFSET 7 +#define RTL8367D_MAC4_FORCE_SELECT_NWAY_ABLTY_MASK 0x80 +#define RTL8367D_MAC4_FORCE_SELECT_TXPAUSE_ABLTY_OFFSET 6 +#define RTL8367D_MAC4_FORCE_SELECT_TXPAUSE_ABLTY_MASK 0x40 +#define RTL8367D_MAC4_FORCE_SELECT_RXPAUSE_ABLTY_OFFSET 5 +#define RTL8367D_MAC4_FORCE_SELECT_RXPAUSE_ABLTY_MASK 0x20 +#define RTL8367D_MAC4_FORCE_SELECT_LINK_ABLTY_OFFSET 4 +#define RTL8367D_MAC4_FORCE_SELECT_LINK_ABLTY_MASK 0x10 +#define RTL8367D_MAC4_FORCE_SELECT_FIB1G_ABLTY_OFFSET 3 +#define RTL8367D_MAC4_FORCE_SELECT_FIB1G_ABLTY_MASK 0x8 +#define RTL8367D_MAC4_FORCE_SELECT_DUPLEX_ABLTY_OFFSET 2 +#define RTL8367D_MAC4_FORCE_SELECT_DUPLEX_ABLTY_MASK 0x4 +#define RTL8367D_MAC4_FORCE_SELECT_SPEED01_ABLTY_OFFSET 0 +#define RTL8367D_MAC4_FORCE_SELECT_SPEED01_ABLTY_MASK 0x3 + +#define RTL8367D_REG_MAC5_FORCE_SELECT 0x12c5 +#define RTL8367D_MAC5_FORCE_SELECT_EEE_ABLTY_OFFSET 15 +#define RTL8367D_MAC5_FORCE_SELECT_EEE_ABLTY_MASK 0x8000 +#define RTL8367D_MAC5_FORCE_SELECT_UNUSED_OFFSET 14 +#define RTL8367D_MAC5_FORCE_SELECT_UNUSED_MASK 0x4000 +#define RTL8367D_MAC5_FORCE_SELECT_SPEED23_ABLTY_OFFSET 12 +#define RTL8367D_MAC5_FORCE_SELECT_SPEED23_ABLTY_MASK 0x3000 +#define RTL8367D_MAC5_FORCE_SELECT_LPI_1000_ABLTY_OFFSET 11 +#define RTL8367D_MAC5_FORCE_SELECT_LPI_1000_ABLTY_MASK 0x800 +#define RTL8367D_MAC5_FORCE_SELECT_LPI_100_ABLTY_OFFSET 10 +#define RTL8367D_MAC5_FORCE_SELECT_LPI_100_ABLTY_MASK 0x400 +#define RTL8367D_MAC5_FORCE_SELECT_MST_FAULT_ABLTY_OFFSET 9 +#define RTL8367D_MAC5_FORCE_SELECT_MST_FAULT_ABLTY_MASK 0x200 +#define RTL8367D_MAC5_FORCE_SELECT_MST_MOD_ABLTY_OFFSET 8 +#define RTL8367D_MAC5_FORCE_SELECT_MST_MOD_ABLTY_MASK 0x100 +#define RTL8367D_MAC5_FORCE_SELECT_NWAY_ABLTY_OFFSET 7 +#define RTL8367D_MAC5_FORCE_SELECT_NWAY_ABLTY_MASK 0x80 +#define RTL8367D_MAC5_FORCE_SELECT_TXPAUSE_ABLTY_OFFSET 6 +#define RTL8367D_MAC5_FORCE_SELECT_TXPAUSE_ABLTY_MASK 0x40 +#define RTL8367D_MAC5_FORCE_SELECT_RXPAUSE_ABLTY_OFFSET 5 +#define RTL8367D_MAC5_FORCE_SELECT_RXPAUSE_ABLTY_MASK 0x20 +#define RTL8367D_MAC5_FORCE_SELECT_LINK_ABLTY_OFFSET 4 +#define RTL8367D_MAC5_FORCE_SELECT_LINK_ABLTY_MASK 0x10 +#define RTL8367D_MAC5_FORCE_SELECT_FIB1G_ABLTY_OFFSET 3 +#define RTL8367D_MAC5_FORCE_SELECT_FIB1G_ABLTY_MASK 0x8 +#define RTL8367D_MAC5_FORCE_SELECT_DUPLEX_ABLTY_OFFSET 2 +#define RTL8367D_MAC5_FORCE_SELECT_DUPLEX_ABLTY_MASK 0x4 +#define RTL8367D_MAC5_FORCE_SELECT_SPEED01_ABLTY_OFFSET 0 +#define RTL8367D_MAC5_FORCE_SELECT_SPEED01_ABLTY_MASK 0x3 + +#define RTL8367D_REG_MAC6_FORCE_SELECT 0x12c6 +#define RTL8367D_MAC6_FORCE_SELECT_EEE_ABLTY_OFFSET 15 +#define RTL8367D_MAC6_FORCE_SELECT_EEE_ABLTY_MASK 0x8000 +#define RTL8367D_MAC6_FORCE_SELECT_UNUSED_OFFSET 14 +#define RTL8367D_MAC6_FORCE_SELECT_UNUSED_MASK 0x4000 +#define RTL8367D_MAC6_FORCE_SELECT_SPEED23_ABLTY_OFFSET 12 +#define RTL8367D_MAC6_FORCE_SELECT_SPEED23_ABLTY_MASK 0x3000 +#define RTL8367D_MAC6_FORCE_SELECT_LPI_1000_ABLTY_OFFSET 11 +#define RTL8367D_MAC6_FORCE_SELECT_LPI_1000_ABLTY_MASK 0x800 +#define RTL8367D_MAC6_FORCE_SELECT_LPI_100_ABLTY_OFFSET 10 +#define RTL8367D_MAC6_FORCE_SELECT_LPI_100_ABLTY_MASK 0x400 +#define RTL8367D_MAC6_FORCE_SELECT_MST_FAULT_ABLTY_OFFSET 9 +#define RTL8367D_MAC6_FORCE_SELECT_MST_FAULT_ABLTY_MASK 0x200 +#define RTL8367D_MAC6_FORCE_SELECT_MST_MOD_ABLTY_OFFSET 8 +#define RTL8367D_MAC6_FORCE_SELECT_MST_MOD_ABLTY_MASK 0x100 +#define RTL8367D_MAC6_FORCE_SELECT_NWAY_ABLTY_OFFSET 7 +#define RTL8367D_MAC6_FORCE_SELECT_NWAY_ABLTY_MASK 0x80 +#define RTL8367D_MAC6_FORCE_SELECT_TXPAUSE_ABLTY_OFFSET 6 +#define RTL8367D_MAC6_FORCE_SELECT_TXPAUSE_ABLTY_MASK 0x40 +#define RTL8367D_MAC6_FORCE_SELECT_RXPAUSE_ABLTY_OFFSET 5 +#define RTL8367D_MAC6_FORCE_SELECT_RXPAUSE_ABLTY_MASK 0x20 +#define RTL8367D_MAC6_FORCE_SELECT_LINK_ABLTY_OFFSET 4 +#define RTL8367D_MAC6_FORCE_SELECT_LINK_ABLTY_MASK 0x10 +#define RTL8367D_MAC6_FORCE_SELECT_FIB1G_ABLTY_OFFSET 3 +#define RTL8367D_MAC6_FORCE_SELECT_FIB1G_ABLTY_MASK 0x8 +#define RTL8367D_MAC6_FORCE_SELECT_DUPLEX_ABLTY_OFFSET 2 +#define RTL8367D_MAC6_FORCE_SELECT_DUPLEX_ABLTY_MASK 0x4 +#define RTL8367D_MAC6_FORCE_SELECT_SPEED01_ABLTY_OFFSET 0 +#define RTL8367D_MAC6_FORCE_SELECT_SPEED01_ABLTY_MASK 0x3 + +#define RTL8367D_REG_MAC7_FORCE_SELECT 0x12c7 +#define RTL8367D_MAC7_FORCE_SELECT_EEE_ABLTY_OFFSET 15 +#define RTL8367D_MAC7_FORCE_SELECT_EEE_ABLTY_MASK 0x8000 +#define RTL8367D_MAC7_FORCE_SELECT_UNUSED_OFFSET 14 +#define RTL8367D_MAC7_FORCE_SELECT_UNUSED_MASK 0x4000 +#define RTL8367D_MAC7_FORCE_SELECT_SPEED23_ABLTY_OFFSET 12 +#define RTL8367D_MAC7_FORCE_SELECT_SPEED23_ABLTY_MASK 0x3000 +#define RTL8367D_MAC7_FORCE_SELECT_LPI_1000_ABLTY_OFFSET 11 +#define RTL8367D_MAC7_FORCE_SELECT_LPI_1000_ABLTY_MASK 0x800 +#define RTL8367D_MAC7_FORCE_SELECT_LPI_100_ABLTY_OFFSET 10 +#define RTL8367D_MAC7_FORCE_SELECT_LPI_100_ABLTY_MASK 0x400 +#define RTL8367D_MAC7_FORCE_SELECT_MST_FAULT_ABLTY_OFFSET 9 +#define RTL8367D_MAC7_FORCE_SELECT_MST_FAULT_ABLTY_MASK 0x200 +#define RTL8367D_MAC7_FORCE_SELECT_MST_MOD_ABLTY_OFFSET 8 +#define RTL8367D_MAC7_FORCE_SELECT_MST_MOD_ABLTY_MASK 0x100 +#define RTL8367D_MAC7_FORCE_SELECT_NWAY_ABLTY_OFFSET 7 +#define RTL8367D_MAC7_FORCE_SELECT_NWAY_ABLTY_MASK 0x80 +#define RTL8367D_MAC7_FORCE_SELECT_TXPAUSE_ABLTY_OFFSET 6 +#define RTL8367D_MAC7_FORCE_SELECT_TXPAUSE_ABLTY_MASK 0x40 +#define RTL8367D_MAC7_FORCE_SELECT_RXPAUSE_ABLTY_OFFSET 5 +#define RTL8367D_MAC7_FORCE_SELECT_RXPAUSE_ABLTY_MASK 0x20 +#define RTL8367D_MAC7_FORCE_SELECT_LINK_ABLTY_OFFSET 4 +#define RTL8367D_MAC7_FORCE_SELECT_LINK_ABLTY_MASK 0x10 +#define RTL8367D_MAC7_FORCE_SELECT_FIB1G_ABLTY_OFFSET 3 +#define RTL8367D_MAC7_FORCE_SELECT_FIB1G_ABLTY_MASK 0x8 +#define RTL8367D_MAC7_FORCE_SELECT_DUPLEX_ABLTY_OFFSET 2 +#define RTL8367D_MAC7_FORCE_SELECT_DUPLEX_ABLTY_MASK 0x4 +#define RTL8367D_MAC7_FORCE_SELECT_SPEED01_ABLTY_OFFSET 0 +#define RTL8367D_MAC7_FORCE_SELECT_SPEED01_ABLTY_MASK 0x3 + +#define RTL8367D_REG_MAC0_FORCE_SELECT_EN 0x12c8 +#define RTL8367D_MAC0_FORCE_SELECT_EN_FORCE_EEE_ABLTY_OFFSET 15 +#define RTL8367D_MAC0_FORCE_SELECT_EN_FORCE_EEE_ABLTY_MASK 0x8000 +#define RTL8367D_MAC0_FORCE_SELECT_EN_UNUSED_OFFSET 14 +#define RTL8367D_MAC0_FORCE_SELECT_EN_UNUSED_MASK 0x4000 +#define RTL8367D_MAC0_FORCE_SELECT_EN_FORCE_SPEED3_ABLTY_OFFSET 13 +#define RTL8367D_MAC0_FORCE_SELECT_EN_FORCE_SPEED3_ABLTY_MASK 0x2000 +#define RTL8367D_MAC0_FORCE_SELECT_EN_FORCE_SPEED2_ABLTY_OFFSET 12 +#define RTL8367D_MAC0_FORCE_SELECT_EN_FORCE_SPEED2_ABLTY_MASK 0x1000 +#define RTL8367D_MAC0_FORCE_SELECT_EN_FORCE_LPI_1000_ABLTY_OFFSET 11 +#define RTL8367D_MAC0_FORCE_SELECT_EN_FORCE_LPI_1000_ABLTY_MASK 0x800 +#define RTL8367D_MAC0_FORCE_SELECT_EN_FORCE_LPI_100_ABLTY_OFFSET 10 +#define RTL8367D_MAC0_FORCE_SELECT_EN_FORCE_LPI_100_ABLTY_MASK 0x400 +#define RTL8367D_MAC0_FORCE_SELECT_EN_FORCE_MST_FAULT_ABLTY_OFFSET 9 +#define RTL8367D_MAC0_FORCE_SELECT_EN_FORCE_MST_FAULT_ABLTY_MASK 0x200 +#define RTL8367D_MAC0_FORCE_SELECT_EN_FORCE_MST_MOD_ABLTY_OFFSET 8 +#define RTL8367D_MAC0_FORCE_SELECT_EN_FORCE_MST_MOD_ABLTY_MASK 0x100 +#define RTL8367D_MAC0_FORCE_SELECT_EN_FORCE_NWAY_ABLTY_OFFSET 7 +#define RTL8367D_MAC0_FORCE_SELECT_EN_FORCE_NWAY_ABLTY_MASK 0x80 +#define RTL8367D_MAC0_FORCE_SELECT_EN_FORCE_TXPAUSE_ABLTY_OFFSET 6 +#define RTL8367D_MAC0_FORCE_SELECT_EN_FORCE_TXPAUSE_ABLTY_MASK 0x40 +#define RTL8367D_MAC0_FORCE_SELECT_EN_FORCE_RXPAUSE_ABLTY_OFFSET 5 +#define RTL8367D_MAC0_FORCE_SELECT_EN_FORCE_RXPAUSE_ABLTY_MASK 0x20 +#define RTL8367D_MAC0_FORCE_SELECT_EN_FORCE_LINK_ABLTY_OFFSET 4 +#define RTL8367D_MAC0_FORCE_SELECT_EN_FORCE_LINK_ABLTY_MASK 0x10 +#define RTL8367D_MAC0_FORCE_SELECT_EN_FORCE_FIB1G_ABLTY_OFFSET 3 +#define RTL8367D_MAC0_FORCE_SELECT_EN_FORCE_FIB1G_ABLTY_MASK 0x8 +#define RTL8367D_MAC0_FORCE_SELECT_EN_FORCE_DUPLEX_ABLTY_OFFSET 2 +#define RTL8367D_MAC0_FORCE_SELECT_EN_FORCE_DUPLEX_ABLTY_MASK 0x4 +#define RTL8367D_MAC0_FORCE_SELECT_EN_FORCE_SPEED1_ABLTY_OFFSET 1 +#define RTL8367D_MAC0_FORCE_SELECT_EN_FORCE_SPEED1_ABLTY_MASK 0x2 +#define RTL8367D_MAC0_FORCE_SELECT_EN_FORCE_SPEED0_ABLTY_OFFSET 0 +#define RTL8367D_MAC0_FORCE_SELECT_EN_FORCE_SPEED0_ABLTY_MASK 0x1 + +#define RTL8367D_REG_MAC1_FORCE_SELECT_EN 0x12c9 +#define RTL8367D_MAC1_FORCE_SELECT_EN_FORCE_EEE_ABLTY_OFFSET 15 +#define RTL8367D_MAC1_FORCE_SELECT_EN_FORCE_EEE_ABLTY_MASK 0x8000 +#define RTL8367D_MAC1_FORCE_SELECT_EN_UNUSED_OFFSET 14 +#define RTL8367D_MAC1_FORCE_SELECT_EN_UNUSED_MASK 0x4000 +#define RTL8367D_MAC1_FORCE_SELECT_EN_FORCE_SPEED3_ABLTY_OFFSET 13 +#define RTL8367D_MAC1_FORCE_SELECT_EN_FORCE_SPEED3_ABLTY_MASK 0x2000 +#define RTL8367D_MAC1_FORCE_SELECT_EN_FORCE_SPEED2_ABLTY_OFFSET 12 +#define RTL8367D_MAC1_FORCE_SELECT_EN_FORCE_SPEED2_ABLTY_MASK 0x1000 +#define RTL8367D_MAC1_FORCE_SELECT_EN_FORCE_LPI_1000_ABLTY_OFFSET 11 +#define RTL8367D_MAC1_FORCE_SELECT_EN_FORCE_LPI_1000_ABLTY_MASK 0x800 +#define RTL8367D_MAC1_FORCE_SELECT_EN_FORCE_LPI_100_ABLTY_OFFSET 10 +#define RTL8367D_MAC1_FORCE_SELECT_EN_FORCE_LPI_100_ABLTY_MASK 0x400 +#define RTL8367D_MAC1_FORCE_SELECT_EN_FORCE_MST_FAULT_ABLTY_OFFSET 9 +#define RTL8367D_MAC1_FORCE_SELECT_EN_FORCE_MST_FAULT_ABLTY_MASK 0x200 +#define RTL8367D_MAC1_FORCE_SELECT_EN_FORCE_MST_MOD_ABLTY_OFFSET 8 +#define RTL8367D_MAC1_FORCE_SELECT_EN_FORCE_MST_MOD_ABLTY_MASK 0x100 +#define RTL8367D_MAC1_FORCE_SELECT_EN_FORCE_NWAY_ABLTY_OFFSET 7 +#define RTL8367D_MAC1_FORCE_SELECT_EN_FORCE_NWAY_ABLTY_MASK 0x80 +#define RTL8367D_MAC1_FORCE_SELECT_EN_FORCE_TXPAUSE_ABLTY_OFFSET 6 +#define RTL8367D_MAC1_FORCE_SELECT_EN_FORCE_TXPAUSE_ABLTY_MASK 0x40 +#define RTL8367D_MAC1_FORCE_SELECT_EN_FORCE_RXPAUSE_ABLTY_OFFSET 5 +#define RTL8367D_MAC1_FORCE_SELECT_EN_FORCE_RXPAUSE_ABLTY_MASK 0x20 +#define RTL8367D_MAC1_FORCE_SELECT_EN_FORCE_LINK_ABLTY_OFFSET 4 +#define RTL8367D_MAC1_FORCE_SELECT_EN_FORCE_LINK_ABLTY_MASK 0x10 +#define RTL8367D_MAC1_FORCE_SELECT_EN_FORCE_FIB1G_ABLTY_OFFSET 3 +#define RTL8367D_MAC1_FORCE_SELECT_EN_FORCE_FIB1G_ABLTY_MASK 0x8 +#define RTL8367D_MAC1_FORCE_SELECT_EN_FORCE_DUPLEX_ABLTY_OFFSET 2 +#define RTL8367D_MAC1_FORCE_SELECT_EN_FORCE_DUPLEX_ABLTY_MASK 0x4 +#define RTL8367D_MAC1_FORCE_SELECT_EN_FORCE_SPEED1_ABLTY_OFFSET 1 +#define RTL8367D_MAC1_FORCE_SELECT_EN_FORCE_SPEED1_ABLTY_MASK 0x2 +#define RTL8367D_MAC1_FORCE_SELECT_EN_FORCE_SPEED0_ABLTY_OFFSET 0 +#define RTL8367D_MAC1_FORCE_SELECT_EN_FORCE_SPEED0_ABLTY_MASK 0x1 + +#define RTL8367D_REG_MAC2_FORCE_SELECT_EN 0x12ca +#define RTL8367D_MAC2_FORCE_SELECT_EN_FORCE_EEE_ABLTY_OFFSET 15 +#define RTL8367D_MAC2_FORCE_SELECT_EN_FORCE_EEE_ABLTY_MASK 0x8000 +#define RTL8367D_MAC2_FORCE_SELECT_EN_UNUSED_OFFSET 14 +#define RTL8367D_MAC2_FORCE_SELECT_EN_UNUSED_MASK 0x4000 +#define RTL8367D_MAC2_FORCE_SELECT_EN_FORCE_SPEED3_ABLTY_OFFSET 13 +#define RTL8367D_MAC2_FORCE_SELECT_EN_FORCE_SPEED3_ABLTY_MASK 0x2000 +#define RTL8367D_MAC2_FORCE_SELECT_EN_FORCE_SPEED2_ABLTY_OFFSET 12 +#define RTL8367D_MAC2_FORCE_SELECT_EN_FORCE_SPEED2_ABLTY_MASK 0x1000 +#define RTL8367D_MAC2_FORCE_SELECT_EN_FORCE_LPI_1000_ABLTY_OFFSET 11 +#define RTL8367D_MAC2_FORCE_SELECT_EN_FORCE_LPI_1000_ABLTY_MASK 0x800 +#define RTL8367D_MAC2_FORCE_SELECT_EN_FORCE_LPI_100_ABLTY_OFFSET 10 +#define RTL8367D_MAC2_FORCE_SELECT_EN_FORCE_LPI_100_ABLTY_MASK 0x400 +#define RTL8367D_MAC2_FORCE_SELECT_EN_FORCE_MST_FAULT_ABLTY_OFFSET 9 +#define RTL8367D_MAC2_FORCE_SELECT_EN_FORCE_MST_FAULT_ABLTY_MASK 0x200 +#define RTL8367D_MAC2_FORCE_SELECT_EN_FORCE_MST_MOD_ABLTY_OFFSET 8 +#define RTL8367D_MAC2_FORCE_SELECT_EN_FORCE_MST_MOD_ABLTY_MASK 0x100 +#define RTL8367D_MAC2_FORCE_SELECT_EN_FORCE_NWAY_ABLTY_OFFSET 7 +#define RTL8367D_MAC2_FORCE_SELECT_EN_FORCE_NWAY_ABLTY_MASK 0x80 +#define RTL8367D_MAC2_FORCE_SELECT_EN_FORCE_TXPAUSE_ABLTY_OFFSET 6 +#define RTL8367D_MAC2_FORCE_SELECT_EN_FORCE_TXPAUSE_ABLTY_MASK 0x40 +#define RTL8367D_MAC2_FORCE_SELECT_EN_FORCE_RXPAUSE_ABLTY_OFFSET 5 +#define RTL8367D_MAC2_FORCE_SELECT_EN_FORCE_RXPAUSE_ABLTY_MASK 0x20 +#define RTL8367D_MAC2_FORCE_SELECT_EN_FORCE_LINK_ABLTY_OFFSET 4 +#define RTL8367D_MAC2_FORCE_SELECT_EN_FORCE_LINK_ABLTY_MASK 0x10 +#define RTL8367D_MAC2_FORCE_SELECT_EN_FORCE_FIB1G_ABLTY_OFFSET 3 +#define RTL8367D_MAC2_FORCE_SELECT_EN_FORCE_FIB1G_ABLTY_MASK 0x8 +#define RTL8367D_MAC2_FORCE_SELECT_EN_FORCE_DUPLEX_ABLTY_OFFSET 2 +#define RTL8367D_MAC2_FORCE_SELECT_EN_FORCE_DUPLEX_ABLTY_MASK 0x4 +#define RTL8367D_MAC2_FORCE_SELECT_EN_FORCE_SPEED1_ABLTY_OFFSET 1 +#define RTL8367D_MAC2_FORCE_SELECT_EN_FORCE_SPEED1_ABLTY_MASK 0x2 +#define RTL8367D_MAC2_FORCE_SELECT_EN_FORCE_SPEED0_ABLTY_OFFSET 0 +#define RTL8367D_MAC2_FORCE_SELECT_EN_FORCE_SPEED0_ABLTY_MASK 0x1 + +#define RTL8367D_REG_MAC3_FORCE_SELECT_EN 0x12cb +#define RTL8367D_MAC3_FORCE_SELECT_EN_FORCE_EEE_ABLTY_OFFSET 15 +#define RTL8367D_MAC3_FORCE_SELECT_EN_FORCE_EEE_ABLTY_MASK 0x8000 +#define RTL8367D_MAC3_FORCE_SELECT_EN_UNUSED_OFFSET 14 +#define RTL8367D_MAC3_FORCE_SELECT_EN_UNUSED_MASK 0x4000 +#define RTL8367D_MAC3_FORCE_SELECT_EN_FORCE_SPEED3_ABLTY_OFFSET 13 +#define RTL8367D_MAC3_FORCE_SELECT_EN_FORCE_SPEED3_ABLTY_MASK 0x2000 +#define RTL8367D_MAC3_FORCE_SELECT_EN_FORCE_SPEED2_ABLTY_OFFSET 12 +#define RTL8367D_MAC3_FORCE_SELECT_EN_FORCE_SPEED2_ABLTY_MASK 0x1000 +#define RTL8367D_MAC3_FORCE_SELECT_EN_FORCE_LPI_1000_ABLTY_OFFSET 11 +#define RTL8367D_MAC3_FORCE_SELECT_EN_FORCE_LPI_1000_ABLTY_MASK 0x800 +#define RTL8367D_MAC3_FORCE_SELECT_EN_FORCE_LPI_100_ABLTY_OFFSET 10 +#define RTL8367D_MAC3_FORCE_SELECT_EN_FORCE_LPI_100_ABLTY_MASK 0x400 +#define RTL8367D_MAC3_FORCE_SELECT_EN_FORCE_MST_FAULT_ABLTY_OFFSET 9 +#define RTL8367D_MAC3_FORCE_SELECT_EN_FORCE_MST_FAULT_ABLTY_MASK 0x200 +#define RTL8367D_MAC3_FORCE_SELECT_EN_FORCE_MST_MOD_ABLTY_OFFSET 8 +#define RTL8367D_MAC3_FORCE_SELECT_EN_FORCE_MST_MOD_ABLTY_MASK 0x100 +#define RTL8367D_MAC3_FORCE_SELECT_EN_FORCE_NWAY_ABLTY_OFFSET 7 +#define RTL8367D_MAC3_FORCE_SELECT_EN_FORCE_NWAY_ABLTY_MASK 0x80 +#define RTL8367D_MAC3_FORCE_SELECT_EN_FORCE_TXPAUSE_ABLTY_OFFSET 6 +#define RTL8367D_MAC3_FORCE_SELECT_EN_FORCE_TXPAUSE_ABLTY_MASK 0x40 +#define RTL8367D_MAC3_FORCE_SELECT_EN_FORCE_RXPAUSE_ABLTY_OFFSET 5 +#define RTL8367D_MAC3_FORCE_SELECT_EN_FORCE_RXPAUSE_ABLTY_MASK 0x20 +#define RTL8367D_MAC3_FORCE_SELECT_EN_FORCE_LINK_ABLTY_OFFSET 4 +#define RTL8367D_MAC3_FORCE_SELECT_EN_FORCE_LINK_ABLTY_MASK 0x10 +#define RTL8367D_MAC3_FORCE_SELECT_EN_FORCE_FIB1G_ABLTY_OFFSET 3 +#define RTL8367D_MAC3_FORCE_SELECT_EN_FORCE_FIB1G_ABLTY_MASK 0x8 +#define RTL8367D_MAC3_FORCE_SELECT_EN_FORCE_DUPLEX_ABLTY_OFFSET 2 +#define RTL8367D_MAC3_FORCE_SELECT_EN_FORCE_DUPLEX_ABLTY_MASK 0x4 +#define RTL8367D_MAC3_FORCE_SELECT_EN_FORCE_SPEED1_ABLTY_OFFSET 1 +#define RTL8367D_MAC3_FORCE_SELECT_EN_FORCE_SPEED1_ABLTY_MASK 0x2 +#define RTL8367D_MAC3_FORCE_SELECT_EN_FORCE_SPEED0_ABLTY_OFFSET 0 +#define RTL8367D_MAC3_FORCE_SELECT_EN_FORCE_SPEED0_ABLTY_MASK 0x1 + +#define RTL8367D_REG_MAC4_FORCE_SELECT_EN 0x12cc +#define RTL8367D_MAC4_FORCE_SELECT_EN_FORCE_EEE_ABLTY_OFFSET 15 +#define RTL8367D_MAC4_FORCE_SELECT_EN_FORCE_EEE_ABLTY_MASK 0x8000 +#define RTL8367D_MAC4_FORCE_SELECT_EN_UNUSED_OFFSET 14 +#define RTL8367D_MAC4_FORCE_SELECT_EN_UNUSED_MASK 0x4000 +#define RTL8367D_MAC4_FORCE_SELECT_EN_FORCE_SPEED3_ABLTY_OFFSET 13 +#define RTL8367D_MAC4_FORCE_SELECT_EN_FORCE_SPEED3_ABLTY_MASK 0x2000 +#define RTL8367D_MAC4_FORCE_SELECT_EN_FORCE_SPEED2_ABLTY_OFFSET 12 +#define RTL8367D_MAC4_FORCE_SELECT_EN_FORCE_SPEED2_ABLTY_MASK 0x1000 +#define RTL8367D_MAC4_FORCE_SELECT_EN_FORCE_LPI_1000_ABLTY_OFFSET 11 +#define RTL8367D_MAC4_FORCE_SELECT_EN_FORCE_LPI_1000_ABLTY_MASK 0x800 +#define RTL8367D_MAC4_FORCE_SELECT_EN_FORCE_LPI_100_ABLTY_OFFSET 10 +#define RTL8367D_MAC4_FORCE_SELECT_EN_FORCE_LPI_100_ABLTY_MASK 0x400 +#define RTL8367D_MAC4_FORCE_SELECT_EN_FORCE_MST_FAULT_ABLTY_OFFSET 9 +#define RTL8367D_MAC4_FORCE_SELECT_EN_FORCE_MST_FAULT_ABLTY_MASK 0x200 +#define RTL8367D_MAC4_FORCE_SELECT_EN_FORCE_MST_MOD_ABLTY_OFFSET 8 +#define RTL8367D_MAC4_FORCE_SELECT_EN_FORCE_MST_MOD_ABLTY_MASK 0x100 +#define RTL8367D_MAC4_FORCE_SELECT_EN_FORCE_NWAY_ABLTY_OFFSET 7 +#define RTL8367D_MAC4_FORCE_SELECT_EN_FORCE_NWAY_ABLTY_MASK 0x80 +#define RTL8367D_MAC4_FORCE_SELECT_EN_FORCE_TXPAUSE_ABLTY_OFFSET 6 +#define RTL8367D_MAC4_FORCE_SELECT_EN_FORCE_TXPAUSE_ABLTY_MASK 0x40 +#define RTL8367D_MAC4_FORCE_SELECT_EN_FORCE_RXPAUSE_ABLTY_OFFSET 5 +#define RTL8367D_MAC4_FORCE_SELECT_EN_FORCE_RXPAUSE_ABLTY_MASK 0x20 +#define RTL8367D_MAC4_FORCE_SELECT_EN_FORCE_LINK_ABLTY_OFFSET 4 +#define RTL8367D_MAC4_FORCE_SELECT_EN_FORCE_LINK_ABLTY_MASK 0x10 +#define RTL8367D_MAC4_FORCE_SELECT_EN_FORCE_FIB1G_ABLTY_OFFSET 3 +#define RTL8367D_MAC4_FORCE_SELECT_EN_FORCE_FIB1G_ABLTY_MASK 0x8 +#define RTL8367D_MAC4_FORCE_SELECT_EN_FORCE_DUPLEX_ABLTY_OFFSET 2 +#define RTL8367D_MAC4_FORCE_SELECT_EN_FORCE_DUPLEX_ABLTY_MASK 0x4 +#define RTL8367D_MAC4_FORCE_SELECT_EN_FORCE_SPEED1_ABLTY_OFFSET 1 +#define RTL8367D_MAC4_FORCE_SELECT_EN_FORCE_SPEED1_ABLTY_MASK 0x2 +#define RTL8367D_MAC4_FORCE_SELECT_EN_FORCE_SPEED0_ABLTY_OFFSET 0 +#define RTL8367D_MAC4_FORCE_SELECT_EN_FORCE_SPEED0_ABLTY_MASK 0x1 + +#define RTL8367D_REG_MAC5_FORCE_SELECT_EN 0x12cd +#define RTL8367D_MAC5_FORCE_SELECT_EN_FORCE_EEE_ABLTY_OFFSET 15 +#define RTL8367D_MAC5_FORCE_SELECT_EN_FORCE_EEE_ABLTY_MASK 0x8000 +#define RTL8367D_MAC5_FORCE_SELECT_EN_UNUSED_OFFSET 14 +#define RTL8367D_MAC5_FORCE_SELECT_EN_UNUSED_MASK 0x4000 +#define RTL8367D_MAC5_FORCE_SELECT_EN_FORCE_SPEED3_ABLTY_OFFSET 13 +#define RTL8367D_MAC5_FORCE_SELECT_EN_FORCE_SPEED3_ABLTY_MASK 0x2000 +#define RTL8367D_MAC5_FORCE_SELECT_EN_FORCE_SPEED2_ABLTY_OFFSET 12 +#define RTL8367D_MAC5_FORCE_SELECT_EN_FORCE_SPEED2_ABLTY_MASK 0x1000 +#define RTL8367D_MAC5_FORCE_SELECT_EN_FORCE_LPI_1000_ABLTY_OFFSET 11 +#define RTL8367D_MAC5_FORCE_SELECT_EN_FORCE_LPI_1000_ABLTY_MASK 0x800 +#define RTL8367D_MAC5_FORCE_SELECT_EN_FORCE_LPI_100_ABLTY_OFFSET 10 +#define RTL8367D_MAC5_FORCE_SELECT_EN_FORCE_LPI_100_ABLTY_MASK 0x400 +#define RTL8367D_MAC5_FORCE_SELECT_EN_FORCE_MST_FAULT_ABLTY_OFFSET 9 +#define RTL8367D_MAC5_FORCE_SELECT_EN_FORCE_MST_FAULT_ABLTY_MASK 0x200 +#define RTL8367D_MAC5_FORCE_SELECT_EN_FORCE_MST_MOD_ABLTY_OFFSET 8 +#define RTL8367D_MAC5_FORCE_SELECT_EN_FORCE_MST_MOD_ABLTY_MASK 0x100 +#define RTL8367D_MAC5_FORCE_SELECT_EN_FORCE_NWAY_ABLTY_OFFSET 7 +#define RTL8367D_MAC5_FORCE_SELECT_EN_FORCE_NWAY_ABLTY_MASK 0x80 +#define RTL8367D_MAC5_FORCE_SELECT_EN_FORCE_TXPAUSE_ABLTY_OFFSET 6 +#define RTL8367D_MAC5_FORCE_SELECT_EN_FORCE_TXPAUSE_ABLTY_MASK 0x40 +#define RTL8367D_MAC5_FORCE_SELECT_EN_FORCE_RXPAUSE_ABLTY_OFFSET 5 +#define RTL8367D_MAC5_FORCE_SELECT_EN_FORCE_RXPAUSE_ABLTY_MASK 0x20 +#define RTL8367D_MAC5_FORCE_SELECT_EN_FORCE_LINK_ABLTY_OFFSET 4 +#define RTL8367D_MAC5_FORCE_SELECT_EN_FORCE_LINK_ABLTY_MASK 0x10 +#define RTL8367D_MAC5_FORCE_SELECT_EN_FORCE_FIB1G_ABLTY_OFFSET 3 +#define RTL8367D_MAC5_FORCE_SELECT_EN_FORCE_FIB1G_ABLTY_MASK 0x8 +#define RTL8367D_MAC5_FORCE_SELECT_EN_FORCE_DUPLEX_ABLTY_OFFSET 2 +#define RTL8367D_MAC5_FORCE_SELECT_EN_FORCE_DUPLEX_ABLTY_MASK 0x4 +#define RTL8367D_MAC5_FORCE_SELECT_EN_FORCE_SPEED1_ABLTY_OFFSET 1 +#define RTL8367D_MAC5_FORCE_SELECT_EN_FORCE_SPEED1_ABLTY_MASK 0x2 +#define RTL8367D_MAC5_FORCE_SELECT_EN_FORCE_SPEED0_ABLTY_OFFSET 0 +#define RTL8367D_MAC5_FORCE_SELECT_EN_FORCE_SPEED0_ABLTY_MASK 0x1 + +#define RTL8367D_REG_MAC6_FORCE_SELECT_EN 0x12ce +#define RTL8367D_MAC6_FORCE_SELECT_EN_FORCE_EEE_ABLTY_OFFSET 15 +#define RTL8367D_MAC6_FORCE_SELECT_EN_FORCE_EEE_ABLTY_MASK 0x8000 +#define RTL8367D_MAC6_FORCE_SELECT_EN_UNUSED_OFFSET 14 +#define RTL8367D_MAC6_FORCE_SELECT_EN_UNUSED_MASK 0x4000 +#define RTL8367D_MAC6_FORCE_SELECT_EN_FORCE_SPEED3_ABLTY_OFFSET 13 +#define RTL8367D_MAC6_FORCE_SELECT_EN_FORCE_SPEED3_ABLTY_MASK 0x2000 +#define RTL8367D_MAC6_FORCE_SELECT_EN_FORCE_SPEED2_ABLTY_OFFSET 12 +#define RTL8367D_MAC6_FORCE_SELECT_EN_FORCE_SPEED2_ABLTY_MASK 0x1000 +#define RTL8367D_MAC6_FORCE_SELECT_EN_FORCE_LPI_1000_ABLTY_OFFSET 11 +#define RTL8367D_MAC6_FORCE_SELECT_EN_FORCE_LPI_1000_ABLTY_MASK 0x800 +#define RTL8367D_MAC6_FORCE_SELECT_EN_FORCE_LPI_100_ABLTY_OFFSET 10 +#define RTL8367D_MAC6_FORCE_SELECT_EN_FORCE_LPI_100_ABLTY_MASK 0x400 +#define RTL8367D_MAC6_FORCE_SELECT_EN_FORCE_MST_FAULT_ABLTY_OFFSET 9 +#define RTL8367D_MAC6_FORCE_SELECT_EN_FORCE_MST_FAULT_ABLTY_MASK 0x200 +#define RTL8367D_MAC6_FORCE_SELECT_EN_FORCE_MST_MOD_ABLTY_OFFSET 8 +#define RTL8367D_MAC6_FORCE_SELECT_EN_FORCE_MST_MOD_ABLTY_MASK 0x100 +#define RTL8367D_MAC6_FORCE_SELECT_EN_FORCE_NWAY_ABLTY_OFFSET 7 +#define RTL8367D_MAC6_FORCE_SELECT_EN_FORCE_NWAY_ABLTY_MASK 0x80 +#define RTL8367D_MAC6_FORCE_SELECT_EN_FORCE_TXPAUSE_ABLTY_OFFSET 6 +#define RTL8367D_MAC6_FORCE_SELECT_EN_FORCE_TXPAUSE_ABLTY_MASK 0x40 +#define RTL8367D_MAC6_FORCE_SELECT_EN_FORCE_RXPAUSE_ABLTY_OFFSET 5 +#define RTL8367D_MAC6_FORCE_SELECT_EN_FORCE_RXPAUSE_ABLTY_MASK 0x20 +#define RTL8367D_MAC6_FORCE_SELECT_EN_FORCE_LINK_ABLTY_OFFSET 4 +#define RTL8367D_MAC6_FORCE_SELECT_EN_FORCE_LINK_ABLTY_MASK 0x10 +#define RTL8367D_MAC6_FORCE_SELECT_EN_FORCE_FIB1G_ABLTY_OFFSET 3 +#define RTL8367D_MAC6_FORCE_SELECT_EN_FORCE_FIB1G_ABLTY_MASK 0x8 +#define RTL8367D_MAC6_FORCE_SELECT_EN_FORCE_DUPLEX_ABLTY_OFFSET 2 +#define RTL8367D_MAC6_FORCE_SELECT_EN_FORCE_DUPLEX_ABLTY_MASK 0x4 +#define RTL8367D_MAC6_FORCE_SELECT_EN_FORCE_SPEED1_ABLTY_OFFSET 1 +#define RTL8367D_MAC6_FORCE_SELECT_EN_FORCE_SPEED1_ABLTY_MASK 0x2 +#define RTL8367D_MAC6_FORCE_SELECT_EN_FORCE_SPEED0_ABLTY_OFFSET 0 +#define RTL8367D_MAC6_FORCE_SELECT_EN_FORCE_SPEED0_ABLTY_MASK 0x1 + +#define RTL8367D_REG_MAC7_FORCE_SELECT_EN 0x12cf +#define RTL8367D_MAC7_FORCE_SELECT_EN_FORCE_EEE_ABLTY_OFFSET 15 +#define RTL8367D_MAC7_FORCE_SELECT_EN_FORCE_EEE_ABLTY_MASK 0x8000 +#define RTL8367D_MAC7_FORCE_SELECT_EN_UNUSED_OFFSET 14 +#define RTL8367D_MAC7_FORCE_SELECT_EN_UNUSED_MASK 0x4000 +#define RTL8367D_MAC7_FORCE_SELECT_EN_FORCE_SPEED3_ABLTY_OFFSET 13 +#define RTL8367D_MAC7_FORCE_SELECT_EN_FORCE_SPEED3_ABLTY_MASK 0x2000 +#define RTL8367D_MAC7_FORCE_SELECT_EN_FORCE_SPEED2_ABLTY_OFFSET 12 +#define RTL8367D_MAC7_FORCE_SELECT_EN_FORCE_SPEED2_ABLTY_MASK 0x1000 +#define RTL8367D_MAC7_FORCE_SELECT_EN_FORCE_LPI_1000_ABLTY_OFFSET 11 +#define RTL8367D_MAC7_FORCE_SELECT_EN_FORCE_LPI_1000_ABLTY_MASK 0x800 +#define RTL8367D_MAC7_FORCE_SELECT_EN_FORCE_LPI_100_ABLTY_OFFSET 10 +#define RTL8367D_MAC7_FORCE_SELECT_EN_FORCE_LPI_100_ABLTY_MASK 0x400 +#define RTL8367D_MAC7_FORCE_SELECT_EN_FORCE_MST_FAULT_ABLTY_OFFSET 9 +#define RTL8367D_MAC7_FORCE_SELECT_EN_FORCE_MST_FAULT_ABLTY_MASK 0x200 +#define RTL8367D_MAC7_FORCE_SELECT_EN_FORCE_MST_MOD_ABLTY_OFFSET 8 +#define RTL8367D_MAC7_FORCE_SELECT_EN_FORCE_MST_MOD_ABLTY_MASK 0x100 +#define RTL8367D_MAC7_FORCE_SELECT_EN_FORCE_NWAY_ABLTY_OFFSET 7 +#define RTL8367D_MAC7_FORCE_SELECT_EN_FORCE_NWAY_ABLTY_MASK 0x80 +#define RTL8367D_MAC7_FORCE_SELECT_EN_FORCE_TXPAUSE_ABLTY_OFFSET 6 +#define RTL8367D_MAC7_FORCE_SELECT_EN_FORCE_TXPAUSE_ABLTY_MASK 0x40 +#define RTL8367D_MAC7_FORCE_SELECT_EN_FORCE_RXPAUSE_ABLTY_OFFSET 5 +#define RTL8367D_MAC7_FORCE_SELECT_EN_FORCE_RXPAUSE_ABLTY_MASK 0x20 +#define RTL8367D_MAC7_FORCE_SELECT_EN_FORCE_LINK_ABLTY_OFFSET 4 +#define RTL8367D_MAC7_FORCE_SELECT_EN_FORCE_LINK_ABLTY_MASK 0x10 +#define RTL8367D_MAC7_FORCE_SELECT_EN_FORCE_FIB1G_ABLTY_OFFSET 3 +#define RTL8367D_MAC7_FORCE_SELECT_EN_FORCE_FIB1G_ABLTY_MASK 0x8 +#define RTL8367D_MAC7_FORCE_SELECT_EN_FORCE_DUPLEX_ABLTY_OFFSET 2 +#define RTL8367D_MAC7_FORCE_SELECT_EN_FORCE_DUPLEX_ABLTY_MASK 0x4 +#define RTL8367D_MAC7_FORCE_SELECT_EN_FORCE_SPEED1_ABLTY_OFFSET 1 +#define RTL8367D_MAC7_FORCE_SELECT_EN_FORCE_SPEED1_ABLTY_MASK 0x2 +#define RTL8367D_MAC7_FORCE_SELECT_EN_FORCE_SPEED0_ABLTY_OFFSET 0 +#define RTL8367D_MAC7_FORCE_SELECT_EN_FORCE_SPEED0_ABLTY_MASK 0x1 + +#define RTL8367D_REG_PORT0_STATUS 0x12d0 +#define RTL8367D_PORT0_STATUS_EN_EEE_LPI_OFFSET 15 +#define RTL8367D_PORT0_STATUS_EN_EEE_LPI_MASK 0x8000 +#define RTL8367D_PORT0_STATUS_UNUSED_OFFSET 14 +#define RTL8367D_PORT0_STATUS_UNUSED_MASK 0x4000 +#define RTL8367D_PORT0_STATUS_LINK_SPEED_3_OFFSET 13 +#define RTL8367D_PORT0_STATUS_LINK_SPEED_3_MASK 0x2000 +#define RTL8367D_PORT0_STATUS_LINK_SPEED_2_OFFSET 12 +#define RTL8367D_PORT0_STATUS_LINK_SPEED_2_MASK 0x1000 +#define RTL8367D_PORT0_STATUS_EN_1000_LPI_OFFSET 11 +#define RTL8367D_PORT0_STATUS_EN_1000_LPI_MASK 0x800 +#define RTL8367D_PORT0_STATUS_EN_100_LPI_OFFSET 10 +#define RTL8367D_PORT0_STATUS_EN_100_LPI_MASK 0x400 +#define RTL8367D_PORT0_STATUS_NWAY_FAULT_OFFSET 9 +#define RTL8367D_PORT0_STATUS_NWAY_FAULT_MASK 0x200 +#define RTL8367D_PORT0_STATUS_LINK_ON_MASTER_OFFSET 8 +#define RTL8367D_PORT0_STATUS_LINK_ON_MASTER_MASK 0x100 +#define RTL8367D_PORT0_STATUS_NWAY_CAP_OFFSET 7 +#define RTL8367D_PORT0_STATUS_NWAY_CAP_MASK 0x80 +#define RTL8367D_PORT0_STATUS_TX_FLOWCTRL_CAP_OFFSET 6 +#define RTL8367D_PORT0_STATUS_TX_FLOWCTRL_CAP_MASK 0x40 +#define RTL8367D_PORT0_STATUS_RX_FLOWCTRL_CAP_OFFSET 5 +#define RTL8367D_PORT0_STATUS_RX_FLOWCTRL_CAP_MASK 0x20 +#define RTL8367D_PORT0_STATUS_LINK_STATE_OFFSET 4 +#define RTL8367D_PORT0_STATUS_LINK_STATE_MASK 0x10 +#define RTL8367D_PORT0_STATUS_FULL_DUPLUX_CAP_OFFSET 2 +#define RTL8367D_PORT0_STATUS_FULL_DUPLUX_CAP_MASK 0x4 +#define RTL8367D_PORT0_STATUS_LINK_SPEED_OFFSET 0 +#define RTL8367D_PORT0_STATUS_LINK_SPEED_MASK 0x3 + +#define RTL8367D_REG_PORT1_STATUS 0x12d1 +#define RTL8367D_PORT1_STATUS_EN_EEE_LPI_OFFSET 15 +#define RTL8367D_PORT1_STATUS_EN_EEE_LPI_MASK 0x8000 +#define RTL8367D_PORT1_STATUS_UNUSED_OFFSET 14 +#define RTL8367D_PORT1_STATUS_UNUSED_MASK 0x4000 +#define RTL8367D_PORT1_STATUS_LINK_SPEED_3_OFFSET 13 +#define RTL8367D_PORT1_STATUS_LINK_SPEED_3_MASK 0x2000 +#define RTL8367D_PORT1_STATUS_LINK_SPEED_2_OFFSET 12 +#define RTL8367D_PORT1_STATUS_LINK_SPEED_2_MASK 0x1000 +#define RTL8367D_PORT1_STATUS_EN_1000_LPI_OFFSET 11 +#define RTL8367D_PORT1_STATUS_EN_1000_LPI_MASK 0x800 +#define RTL8367D_PORT1_STATUS_EN_100_LPI_OFFSET 10 +#define RTL8367D_PORT1_STATUS_EN_100_LPI_MASK 0x400 +#define RTL8367D_PORT1_STATUS_NWAY_FAULT_OFFSET 9 +#define RTL8367D_PORT1_STATUS_NWAY_FAULT_MASK 0x200 +#define RTL8367D_PORT1_STATUS_LINK_ON_MASTER_OFFSET 8 +#define RTL8367D_PORT1_STATUS_LINK_ON_MASTER_MASK 0x100 +#define RTL8367D_PORT1_STATUS_NWAY_CAP_OFFSET 7 +#define RTL8367D_PORT1_STATUS_NWAY_CAP_MASK 0x80 +#define RTL8367D_PORT1_STATUS_TX_FLOWCTRL_CAP_OFFSET 6 +#define RTL8367D_PORT1_STATUS_TX_FLOWCTRL_CAP_MASK 0x40 +#define RTL8367D_PORT1_STATUS_RX_FLOWCTRL_CAP_OFFSET 5 +#define RTL8367D_PORT1_STATUS_RX_FLOWCTRL_CAP_MASK 0x20 +#define RTL8367D_PORT1_STATUS_LINK_STATE_OFFSET 4 +#define RTL8367D_PORT1_STATUS_LINK_STATE_MASK 0x10 +#define RTL8367D_PORT1_STATUS_FULL_DUPLUX_CAP_OFFSET 2 +#define RTL8367D_PORT1_STATUS_FULL_DUPLUX_CAP_MASK 0x4 +#define RTL8367D_PORT1_STATUS_LINK_SPEED_OFFSET 0 +#define RTL8367D_PORT1_STATUS_LINK_SPEED_MASK 0x3 + +#define RTL8367D_REG_PORT2_STATUS 0x12d2 +#define RTL8367D_PORT2_STATUS_EN_EEE_LPI_OFFSET 15 +#define RTL8367D_PORT2_STATUS_EN_EEE_LPI_MASK 0x8000 +#define RTL8367D_PORT2_STATUS_UNUSED_OFFSET 14 +#define RTL8367D_PORT2_STATUS_UNUSED_MASK 0x4000 +#define RTL8367D_PORT2_STATUS_LINK_SPEED_3_OFFSET 13 +#define RTL8367D_PORT2_STATUS_LINK_SPEED_3_MASK 0x2000 +#define RTL8367D_PORT2_STATUS_LINK_SPEED_2_OFFSET 12 +#define RTL8367D_PORT2_STATUS_LINK_SPEED_2_MASK 0x1000 +#define RTL8367D_PORT2_STATUS_EN_1000_LPI_OFFSET 11 +#define RTL8367D_PORT2_STATUS_EN_1000_LPI_MASK 0x800 +#define RTL8367D_PORT2_STATUS_EN_100_LPI_OFFSET 10 +#define RTL8367D_PORT2_STATUS_EN_100_LPI_MASK 0x400 +#define RTL8367D_PORT2_STATUS_NWAY_FAULT_OFFSET 9 +#define RTL8367D_PORT2_STATUS_NWAY_FAULT_MASK 0x200 +#define RTL8367D_PORT2_STATUS_LINK_ON_MASTER_OFFSET 8 +#define RTL8367D_PORT2_STATUS_LINK_ON_MASTER_MASK 0x100 +#define RTL8367D_PORT2_STATUS_NWAY_CAP_OFFSET 7 +#define RTL8367D_PORT2_STATUS_NWAY_CAP_MASK 0x80 +#define RTL8367D_PORT2_STATUS_TX_FLOWCTRL_CAP_OFFSET 6 +#define RTL8367D_PORT2_STATUS_TX_FLOWCTRL_CAP_MASK 0x40 +#define RTL8367D_PORT2_STATUS_RX_FLOWCTRL_CAP_OFFSET 5 +#define RTL8367D_PORT2_STATUS_RX_FLOWCTRL_CAP_MASK 0x20 +#define RTL8367D_PORT2_STATUS_LINK_STATE_OFFSET 4 +#define RTL8367D_PORT2_STATUS_LINK_STATE_MASK 0x10 +#define RTL8367D_PORT2_STATUS_FULL_DUPLUX_CAP_OFFSET 2 +#define RTL8367D_PORT2_STATUS_FULL_DUPLUX_CAP_MASK 0x4 +#define RTL8367D_PORT2_STATUS_LINK_SPEED_OFFSET 0 +#define RTL8367D_PORT2_STATUS_LINK_SPEED_MASK 0x3 + +#define RTL8367D_REG_PORT3_STATUS 0x12d3 +#define RTL8367D_PORT3_STATUS_EN_EEE_LPI_OFFSET 15 +#define RTL8367D_PORT3_STATUS_EN_EEE_LPI_MASK 0x8000 +#define RTL8367D_PORT3_STATUS_UNUSED_OFFSET 14 +#define RTL8367D_PORT3_STATUS_UNUSED_MASK 0x4000 +#define RTL8367D_PORT3_STATUS_LINK_SPEED_3_OFFSET 13 +#define RTL8367D_PORT3_STATUS_LINK_SPEED_3_MASK 0x2000 +#define RTL8367D_PORT3_STATUS_LINK_SPEED_2_OFFSET 12 +#define RTL8367D_PORT3_STATUS_LINK_SPEED_2_MASK 0x1000 +#define RTL8367D_PORT3_STATUS_EN_1000_LPI_OFFSET 11 +#define RTL8367D_PORT3_STATUS_EN_1000_LPI_MASK 0x800 +#define RTL8367D_PORT3_STATUS_EN_100_LPI_OFFSET 10 +#define RTL8367D_PORT3_STATUS_EN_100_LPI_MASK 0x400 +#define RTL8367D_PORT3_STATUS_NWAY_FAULT_OFFSET 9 +#define RTL8367D_PORT3_STATUS_NWAY_FAULT_MASK 0x200 +#define RTL8367D_PORT3_STATUS_LINK_ON_MASTER_OFFSET 8 +#define RTL8367D_PORT3_STATUS_LINK_ON_MASTER_MASK 0x100 +#define RTL8367D_PORT3_STATUS_NWAY_CAP_OFFSET 7 +#define RTL8367D_PORT3_STATUS_NWAY_CAP_MASK 0x80 +#define RTL8367D_PORT3_STATUS_TX_FLOWCTRL_CAP_OFFSET 6 +#define RTL8367D_PORT3_STATUS_TX_FLOWCTRL_CAP_MASK 0x40 +#define RTL8367D_PORT3_STATUS_RX_FLOWCTRL_CAP_OFFSET 5 +#define RTL8367D_PORT3_STATUS_RX_FLOWCTRL_CAP_MASK 0x20 +#define RTL8367D_PORT3_STATUS_LINK_STATE_OFFSET 4 +#define RTL8367D_PORT3_STATUS_LINK_STATE_MASK 0x10 +#define RTL8367D_PORT3_STATUS_FULL_DUPLUX_CAP_OFFSET 2 +#define RTL8367D_PORT3_STATUS_FULL_DUPLUX_CAP_MASK 0x4 +#define RTL8367D_PORT3_STATUS_LINK_SPEED_OFFSET 0 +#define RTL8367D_PORT3_STATUS_LINK_SPEED_MASK 0x3 + +#define RTL8367D_REG_PORT4_STATUS 0x12d4 +#define RTL8367D_PORT4_STATUS_EN_EEE_LPI_OFFSET 15 +#define RTL8367D_PORT4_STATUS_EN_EEE_LPI_MASK 0x8000 +#define RTL8367D_PORT4_STATUS_UNUSED_OFFSET 14 +#define RTL8367D_PORT4_STATUS_UNUSED_MASK 0x4000 +#define RTL8367D_PORT4_STATUS_LINK_SPEED_3_OFFSET 13 +#define RTL8367D_PORT4_STATUS_LINK_SPEED_3_MASK 0x2000 +#define RTL8367D_PORT4_STATUS_LINK_SPEED_2_OFFSET 12 +#define RTL8367D_PORT4_STATUS_LINK_SPEED_2_MASK 0x1000 +#define RTL8367D_PORT4_STATUS_EN_1000_LPI_OFFSET 11 +#define RTL8367D_PORT4_STATUS_EN_1000_LPI_MASK 0x800 +#define RTL8367D_PORT4_STATUS_EN_100_LPI_OFFSET 10 +#define RTL8367D_PORT4_STATUS_EN_100_LPI_MASK 0x400 +#define RTL8367D_PORT4_STATUS_NWAY_FAULT_OFFSET 9 +#define RTL8367D_PORT4_STATUS_NWAY_FAULT_MASK 0x200 +#define RTL8367D_PORT4_STATUS_LINK_ON_MASTER_OFFSET 8 +#define RTL8367D_PORT4_STATUS_LINK_ON_MASTER_MASK 0x100 +#define RTL8367D_PORT4_STATUS_NWAY_CAP_OFFSET 7 +#define RTL8367D_PORT4_STATUS_NWAY_CAP_MASK 0x80 +#define RTL8367D_PORT4_STATUS_TX_FLOWCTRL_CAP_OFFSET 6 +#define RTL8367D_PORT4_STATUS_TX_FLOWCTRL_CAP_MASK 0x40 +#define RTL8367D_PORT4_STATUS_RX_FLOWCTRL_CAP_OFFSET 5 +#define RTL8367D_PORT4_STATUS_RX_FLOWCTRL_CAP_MASK 0x20 +#define RTL8367D_PORT4_STATUS_LINK_STATE_OFFSET 4 +#define RTL8367D_PORT4_STATUS_LINK_STATE_MASK 0x10 +#define RTL8367D_PORT4_STATUS_FULL_DUPLUX_CAP_OFFSET 2 +#define RTL8367D_PORT4_STATUS_FULL_DUPLUX_CAP_MASK 0x4 +#define RTL8367D_PORT4_STATUS_LINK_SPEED_OFFSET 0 +#define RTL8367D_PORT4_STATUS_LINK_SPEED_MASK 0x3 + +#define RTL8367D_REG_PORT5_STATUS 0x12d5 +#define RTL8367D_PORT5_STATUS_EN_EEE_LPI_OFFSET 15 +#define RTL8367D_PORT5_STATUS_EN_EEE_LPI_MASK 0x8000 +#define RTL8367D_PORT5_STATUS_UNUSED_OFFSET 14 +#define RTL8367D_PORT5_STATUS_UNUSED_MASK 0x4000 +#define RTL8367D_PORT5_STATUS_LINK_SPEED_3_OFFSET 13 +#define RTL8367D_PORT5_STATUS_LINK_SPEED_3_MASK 0x2000 +#define RTL8367D_PORT5_STATUS_LINK_SPEED_2_OFFSET 12 +#define RTL8367D_PORT5_STATUS_LINK_SPEED_2_MASK 0x1000 +#define RTL8367D_PORT5_STATUS_EN_1000_LPI_OFFSET 11 +#define RTL8367D_PORT5_STATUS_EN_1000_LPI_MASK 0x800 +#define RTL8367D_PORT5_STATUS_EN_100_LPI_OFFSET 10 +#define RTL8367D_PORT5_STATUS_EN_100_LPI_MASK 0x400 +#define RTL8367D_PORT5_STATUS_NWAY_FAULT_OFFSET 9 +#define RTL8367D_PORT5_STATUS_NWAY_FAULT_MASK 0x200 +#define RTL8367D_PORT5_STATUS_LINK_ON_MASTER_OFFSET 8 +#define RTL8367D_PORT5_STATUS_LINK_ON_MASTER_MASK 0x100 +#define RTL8367D_PORT5_STATUS_NWAY_CAP_OFFSET 7 +#define RTL8367D_PORT5_STATUS_NWAY_CAP_MASK 0x80 +#define RTL8367D_PORT5_STATUS_TX_FLOWCTRL_CAP_OFFSET 6 +#define RTL8367D_PORT5_STATUS_TX_FLOWCTRL_CAP_MASK 0x40 +#define RTL8367D_PORT5_STATUS_RX_FLOWCTRL_CAP_OFFSET 5 +#define RTL8367D_PORT5_STATUS_RX_FLOWCTRL_CAP_MASK 0x20 +#define RTL8367D_PORT5_STATUS_LINK_STATE_OFFSET 4 +#define RTL8367D_PORT5_STATUS_LINK_STATE_MASK 0x10 +#define RTL8367D_PORT5_STATUS_FULL_DUPLUX_CAP_OFFSET 2 +#define RTL8367D_PORT5_STATUS_FULL_DUPLUX_CAP_MASK 0x4 +#define RTL8367D_PORT5_STATUS_LINK_SPEED_OFFSET 0 +#define RTL8367D_PORT5_STATUS_LINK_SPEED_MASK 0x3 + +#define RTL8367D_REG_PORT6_STATUS 0x12d6 +#define RTL8367D_PORT6_STATUS_EN_EEE_LPI_OFFSET 15 +#define RTL8367D_PORT6_STATUS_EN_EEE_LPI_MASK 0x8000 +#define RTL8367D_PORT6_STATUS_UNUSED_OFFSET 14 +#define RTL8367D_PORT6_STATUS_UNUSED_MASK 0x4000 +#define RTL8367D_PORT6_STATUS_LINK_SPEED_3_OFFSET 13 +#define RTL8367D_PORT6_STATUS_LINK_SPEED_3_MASK 0x2000 +#define RTL8367D_PORT6_STATUS_LINK_SPEED_2_OFFSET 12 +#define RTL8367D_PORT6_STATUS_LINK_SPEED_2_MASK 0x1000 +#define RTL8367D_PORT6_STATUS_EN_1000_LPI_OFFSET 11 +#define RTL8367D_PORT6_STATUS_EN_1000_LPI_MASK 0x800 +#define RTL8367D_PORT6_STATUS_EN_100_LPI_OFFSET 10 +#define RTL8367D_PORT6_STATUS_EN_100_LPI_MASK 0x400 +#define RTL8367D_PORT6_STATUS_NWAY_FAULT_OFFSET 9 +#define RTL8367D_PORT6_STATUS_NWAY_FAULT_MASK 0x200 +#define RTL8367D_PORT6_STATUS_LINK_ON_MASTER_OFFSET 8 +#define RTL8367D_PORT6_STATUS_LINK_ON_MASTER_MASK 0x100 +#define RTL8367D_PORT6_STATUS_NWAY_CAP_OFFSET 7 +#define RTL8367D_PORT6_STATUS_NWAY_CAP_MASK 0x80 +#define RTL8367D_PORT6_STATUS_TX_FLOWCTRL_CAP_OFFSET 6 +#define RTL8367D_PORT6_STATUS_TX_FLOWCTRL_CAP_MASK 0x40 +#define RTL8367D_PORT6_STATUS_RX_FLOWCTRL_CAP_OFFSET 5 +#define RTL8367D_PORT6_STATUS_RX_FLOWCTRL_CAP_MASK 0x20 +#define RTL8367D_PORT6_STATUS_LINK_STATE_OFFSET 4 +#define RTL8367D_PORT6_STATUS_LINK_STATE_MASK 0x10 +#define RTL8367D_PORT6_STATUS_FULL_DUPLUX_CAP_OFFSET 2 +#define RTL8367D_PORT6_STATUS_FULL_DUPLUX_CAP_MASK 0x4 +#define RTL8367D_PORT6_STATUS_LINK_SPEED_OFFSET 0 +#define RTL8367D_PORT6_STATUS_LINK_SPEED_MASK 0x3 + +#define RTL8367D_REG_PORT7_STATUS 0x12d7 +#define RTL8367D_PORT7_STATUS_EN_EEE_LPI_OFFSET 15 +#define RTL8367D_PORT7_STATUS_EN_EEE_LPI_MASK 0x8000 +#define RTL8367D_PORT7_STATUS_UNUSED_OFFSET 14 +#define RTL8367D_PORT7_STATUS_UNUSED_MASK 0x4000 +#define RTL8367D_PORT7_STATUS_LINK_SPEED_3_OFFSET 13 +#define RTL8367D_PORT7_STATUS_LINK_SPEED_3_MASK 0x2000 +#define RTL8367D_PORT7_STATUS_LINK_SPEED_2_OFFSET 12 +#define RTL8367D_PORT7_STATUS_LINK_SPEED_2_MASK 0x1000 +#define RTL8367D_PORT7_STATUS_EN_1000_LPI_OFFSET 11 +#define RTL8367D_PORT7_STATUS_EN_1000_LPI_MASK 0x800 +#define RTL8367D_PORT7_STATUS_EN_100_LPI_OFFSET 10 +#define RTL8367D_PORT7_STATUS_EN_100_LPI_MASK 0x400 +#define RTL8367D_PORT7_STATUS_NWAY_FAULT_OFFSET 9 +#define RTL8367D_PORT7_STATUS_NWAY_FAULT_MASK 0x200 +#define RTL8367D_PORT7_STATUS_LINK_ON_MASTER_OFFSET 8 +#define RTL8367D_PORT7_STATUS_LINK_ON_MASTER_MASK 0x100 +#define RTL8367D_PORT7_STATUS_NWAY_CAP_OFFSET 7 +#define RTL8367D_PORT7_STATUS_NWAY_CAP_MASK 0x80 +#define RTL8367D_PORT7_STATUS_TX_FLOWCTRL_CAP_OFFSET 6 +#define RTL8367D_PORT7_STATUS_TX_FLOWCTRL_CAP_MASK 0x40 +#define RTL8367D_PORT7_STATUS_RX_FLOWCTRL_CAP_OFFSET 5 +#define RTL8367D_PORT7_STATUS_RX_FLOWCTRL_CAP_MASK 0x20 +#define RTL8367D_PORT7_STATUS_LINK_STATE_OFFSET 4 +#define RTL8367D_PORT7_STATUS_LINK_STATE_MASK 0x10 +#define RTL8367D_PORT7_STATUS_FULL_DUPLUX_CAP_OFFSET 2 +#define RTL8367D_PORT7_STATUS_FULL_DUPLUX_CAP_MASK 0x4 +#define RTL8367D_PORT7_STATUS_LINK_SPEED_OFFSET 0 +#define RTL8367D_PORT7_STATUS_LINK_SPEED_MASK 0x3 + +#define RTL8367D_REG_FIELD_SELECTOR0 0x12e7 +#define RTL8367D_FIELD_SELECTOR0_FORMAT_OFFSET 8 +#define RTL8367D_FIELD_SELECTOR0_FORMAT_MASK 0x700 +#define RTL8367D_FIELD_SELECTOR0_OFFSET_OFFSET 0 +#define RTL8367D_FIELD_SELECTOR0_OFFSET_MASK 0xFF + +#define RTL8367D_REG_FIELD_SELECTOR1 0x12e8 +#define RTL8367D_FIELD_SELECTOR1_FORMAT_OFFSET 8 +#define RTL8367D_FIELD_SELECTOR1_FORMAT_MASK 0x700 +#define RTL8367D_FIELD_SELECTOR1_OFFSET_OFFSET 0 +#define RTL8367D_FIELD_SELECTOR1_OFFSET_MASK 0xFF + +#define RTL8367D_REG_FIELD_SELECTOR2 0x12e9 +#define RTL8367D_FIELD_SELECTOR2_FORMAT_OFFSET 8 +#define RTL8367D_FIELD_SELECTOR2_FORMAT_MASK 0x700 +#define RTL8367D_FIELD_SELECTOR2_OFFSET_OFFSET 0 +#define RTL8367D_FIELD_SELECTOR2_OFFSET_MASK 0xFF + +#define RTL8367D_REG_FIELD_SELECTOR3 0x12ea +#define RTL8367D_FIELD_SELECTOR3_FORMAT_OFFSET 8 +#define RTL8367D_FIELD_SELECTOR3_FORMAT_MASK 0x700 +#define RTL8367D_FIELD_SELECTOR3_OFFSET_OFFSET 0 +#define RTL8367D_FIELD_SELECTOR3_OFFSET_MASK 0xFF + +#define RTL8367D_REG_FIELD_SELECTOR4 0x12eb +#define RTL8367D_FIELD_SELECTOR4_FORMAT_OFFSET 8 +#define RTL8367D_FIELD_SELECTOR4_FORMAT_MASK 0x700 +#define RTL8367D_FIELD_SELECTOR4_OFFSET_OFFSET 0 +#define RTL8367D_FIELD_SELECTOR4_OFFSET_MASK 0xFF + +#define RTL8367D_REG_FIELD_SELECTOR5 0x12ec +#define RTL8367D_FIELD_SELECTOR5_FORMAT_OFFSET 8 +#define RTL8367D_FIELD_SELECTOR5_FORMAT_MASK 0x700 +#define RTL8367D_FIELD_SELECTOR5_OFFSET_OFFSET 0 +#define RTL8367D_FIELD_SELECTOR5_OFFSET_MASK 0xFF + +#define RTL8367D_REG_FIELD_SELECTOR6 0x12ed +#define RTL8367D_FIELD_SELECTOR6_FORMAT_OFFSET 8 +#define RTL8367D_FIELD_SELECTOR6_FORMAT_MASK 0x700 +#define RTL8367D_FIELD_SELECTOR6_OFFSET_OFFSET 0 +#define RTL8367D_FIELD_SELECTOR6_OFFSET_MASK 0xFF + +#define RTL8367D_REG_FIELD_SELECTOR7 0x12ee +#define RTL8367D_FIELD_SELECTOR7_FORMAT_OFFSET 8 +#define RTL8367D_FIELD_SELECTOR7_FORMAT_MASK 0x700 +#define RTL8367D_FIELD_SELECTOR7_OFFSET_OFFSET 0 +#define RTL8367D_FIELD_SELECTOR7_OFFSET_MASK 0xFF + +#define RTL8367D_REG_HAS_BISD_CTRL0 0x12ef +#define RTL8367D_HSARAM_FRCTL_OFFSET 13 +#define RTL8367D_HSARAM_FRCTL_MASK 0x2000 +#define RTL8367D_HSARAM_TGL_OFFSET 12 +#define RTL8367D_HSARAM_TGL_MASK 0x1000 +#define RTL8367D_HSARAM_WR_OFFSET 11 +#define RTL8367D_HSARAM_WR_MASK 0x800 +#define RTL8367D_HSARAM_ADR_OFFSET 0 +#define RTL8367D_HSARAM_ADR_MASK 0x7FF + +#define RTL8367D_REG_HAS_BISD_CTRL1 0x12f0 + +#define RTL8367D_REG_HAS_BISD_CTRL2 0x12f1 + +#define RTL8367D_REG_HAS_BISD_CTRL3 0x12f2 +#define RTL8367D_HSARAM_BISD_EN_OFFSET 6 +#define RTL8367D_HSARAM_BISD_EN_MASK 0x40 +#define RTL8367D_HSARAM_CONS_VAL_OFFSET 5 +#define RTL8367D_HSARAM_CONS_VAL_MASK 0x20 +#define RTL8367D_HSARAM_CONS_ACS_OFFSET 4 +#define RTL8367D_HSARAM_CONS_ACS_MASK 0x10 +#define RTL8367D_HSARAM_SEL16BNK_OFFSET 0 +#define RTL8367D_HSARAM_SEL16BNK_MASK 0xF + +#define RTL8367D_REG_HAS_BISD_CTRL4 0x12f3 + +#define RTL8367D_REG_PB_BISD_CTRL0 0x12f4 +#define RTL8367D_PB_FRCTL_OFFSET 15 +#define RTL8367D_PB_FRCTL_MASK 0x8000 +#define RTL8367D_PB_TGL_OFFSET 14 +#define RTL8367D_PB_TGL_MASK 0x4000 +#define RTL8367D_PB_WR_OFFSET 13 +#define RTL8367D_PB_WR_MASK 0x2000 +#define RTL8367D_PB_ADR_OFFSET 0 +#define RTL8367D_PB_ADR_MASK 0x1FFF + +#define RTL8367D_REG_PB_BISD_CTRL1 0x12f5 + +#define RTL8367D_REG_PB_BISD_CTRL2 0x12f6 + +#define RTL8367D_REG_PB_BISD_CTRL3 0x12f7 +#define RTL8367D_PB_BISD_EN_OFFSET 6 +#define RTL8367D_PB_BISD_EN_MASK 0x40 +#define RTL8367D_PB_CONS_VAL_OFFSET 5 +#define RTL8367D_PB_CONS_VAL_MASK 0x20 +#define RTL8367D_PB_CONS_ACS_OFFSET 4 +#define RTL8367D_PB_CONS_ACS_MASK 0x10 +#define RTL8367D_PB_SEL16BNK_OFFSET 0 +#define RTL8367D_PB_SEL16BNK_MASK 0xF + +#define RTL8367D_REG_PB_BISD_CTRL4 0x12f8 + +#define RTL8367D_REG_MIRROR_SRC_PMSK 0x12fb +#define RTL8367D_MIRROR_RX_PMSK_OFFSET 8 +#define RTL8367D_MIRROR_RX_PMSK_MASK 0xFF00 +#define RTL8367D_MIRROR_TX_PMSK_OFFSET 0 +#define RTL8367D_MIRROR_TX_PMSK_MASK 0xFF + +#define RTL8367D_REG_HWPKT_GEN_MISC 0x12ff +#define RTL8367D_PKT_GEN_SUSPEND_OFFSET 8 +#define RTL8367D_PKT_GEN_SUSPEND_MASK 0xFF00 +#define RTL8367D_PKT_GEN_STATUS_OFFSET 0 +#define RTL8367D_PKT_GEN_STATUS_MASK 0xFF + +/* (16'h1300)chip_reg */ + +#define RTL8367D_REG_CHIP_NUMBER 0x1300 + +#define RTL8367D_REG_CHIP_VER 0x1301 +#define RTL8367D_VERID_OFFSET 12 +#define RTL8367D_VERID_MASK 0xF000 +#define RTL8367D_MCID_OFFSET 8 +#define RTL8367D_MCID_MASK 0xF00 +#define RTL8367D_MODEL_ID_OFFSET 4 +#define RTL8367D_MODEL_ID_MASK 0xF0 +#define RTL8367D_AFE_VERSION_OFFSET 0 +#define RTL8367D_AFE_VERSION_MASK 0x1 + +#define RTL8367D_REG_CFG_SLR_SMT 0x1302 +#define RTL8367D_SMT_SMI1_EN_OFFSET 4 +#define RTL8367D_SMT_SMI1_EN_MASK 0x10 +#define RTL8367D_SMT_EXT1_EN_OFFSET 3 +#define RTL8367D_SMT_EXT1_EN_MASK 0x8 +#define RTL8367D_SMT_NRST_EN_OFFSET 2 +#define RTL8367D_SMT_NRST_EN_MASK 0x4 +#define RTL8367D_SLR_EXT1CK_OFFSET 1 +#define RTL8367D_SLR_EXT1CK_MASK 0x2 +#define RTL8367D_SLR_LED_OFFSET 0 +#define RTL8367D_SLR_LED_MASK 0x1 + +#define RTL8367D_REG_CHIP_DEBUG0 0x1303 +#define RTL8367D_DRI_SPI_OFFSET 14 +#define RTL8367D_DRI_SPI_MASK 0x4000 +#define RTL8367D_DRI_OFFSET 13 +#define RTL8367D_DRI_MASK 0x2000 +#define RTL8367D_SLR_SPI_OFFSET 12 +#define RTL8367D_SLR_SPI_MASK 0x1000 +#define RTL8367D_SLR_OFFSET 11 +#define RTL8367D_SLR_MASK 0x800 +#define RTL8367D_SEL33_EXT2_OFFSET 10 +#define RTL8367D_SEL33_EXT2_MASK 0x400 +#define RTL8367D_SEL33_EXT1_OFFSET 9 +#define RTL8367D_SEL33_EXT1_MASK 0x200 +#define RTL8367D_SEL33_EXT0_OFFSET 8 +#define RTL8367D_SEL33_EXT0_MASK 0x100 +#define RTL8367D_DRI_OTHER_OFFSET 7 +#define RTL8367D_DRI_OTHER_MASK 0x80 +#define RTL8367D_DRI_EXT1_RG_OFFSET 6 +#define RTL8367D_DRI_EXT1_RG_MASK 0x40 +#define RTL8367D_DRI_EXT0_RG_OFFSET 5 +#define RTL8367D_DRI_EXT0_RG_MASK 0x20 +#define RTL8367D_DRI_EXT1_OFFSET 4 +#define RTL8367D_DRI_EXT1_MASK 0x10 +#define RTL8367D_DRI_EXT0_OFFSET 3 +#define RTL8367D_DRI_EXT0_MASK 0x8 +#define RTL8367D_SLR_OTHER_OFFSET 2 +#define RTL8367D_SLR_OTHER_MASK 0x4 +#define RTL8367D_SLR_EXT1_OFFSET 1 +#define RTL8367D_SLR_EXT1_MASK 0x2 +#define RTL8367D_SLR_EXt0_OFFSET 0 +#define RTL8367D_SLR_EXt0_MASK 0x1 + +#define RTL8367D_REG_CHIP_DEBUG1 0x1304 +#define RTL8367D_RG1_DN_OFFSET 12 +#define RTL8367D_RG1_DN_MASK 0x7000 +#define RTL8367D_RG1_DP_OFFSET 8 +#define RTL8367D_RG1_DP_MASK 0x700 +#define RTL8367D_RG0_DN_OFFSET 4 +#define RTL8367D_RG0_DN_MASK 0x70 +#define RTL8367D_RG0_DP_OFFSET 0 +#define RTL8367D_RG0_DP_MASK 0x7 + +#define RTL8367D_REG_DIGITAL_INTERFACE_SELECT 0x1305 +#define RTL8367D_ORG_COL_OFFSET 15 +#define RTL8367D_ORG_COL_MASK 0x8000 +#define RTL8367D_ORG_CRS_OFFSET 14 +#define RTL8367D_ORG_CRS_MASK 0x4000 +#define RTL8367D_SKIP_MII_1_RXER_OFFSET 13 +#define RTL8367D_SKIP_MII_1_RXER_MASK 0x2000 +#define RTL8367D_SKIP_MII_0_RXER_OFFSET 12 +#define RTL8367D_SKIP_MII_0_RXER_MASK 0x1000 +#define RTL8367D_SELECT_GMII_1_OFFSET 4 +#define RTL8367D_SELECT_GMII_1_MASK 0xF0 +#define RTL8367D_SELECT_GMII_0_OFFSET 0 +#define RTL8367D_SELECT_GMII_0_MASK 0xF + +#define RTL8367D_REG_EXT0_RGMXF 0x1306 +#define RTL8367D_EXT0_RGTX_INV_OFFSET 6 +#define RTL8367D_EXT0_RGTX_INV_MASK 0x40 +#define RTL8367D_EXT0_RGRX_INV_OFFSET 5 +#define RTL8367D_EXT0_RGRX_INV_MASK 0x20 +#define RTL8367D_EXT0_RGMXF_OFFSET 0 +#define RTL8367D_EXT0_RGMXF_MASK 0x1F + +#define RTL8367D_REG_EXT1_RGMXF 0x1307 +#define RTL8367D_EXT1_RGTX_INV_OFFSET 6 +#define RTL8367D_EXT1_RGTX_INV_MASK 0x40 +#define RTL8367D_EXT1_RGRX_INV_OFFSET 5 +#define RTL8367D_EXT1_RGRX_INV_MASK 0x20 +#define RTL8367D_EXT1_RGMXF_OFFSET 0 +#define RTL8367D_EXT1_RGMXF_MASK 0x1F + +#define RTL8367D_REG_BISR_CTRL 0x1308 +#define RTL8367D_BISR_CTRL_OFFSET 0 +#define RTL8367D_BISR_CTRL_MASK 0x7 + +#define RTL8367D_REG_I2C_CLOCK_DIV 0x130a +#define RTL8367D_I2C_CLOCK_DIV_OFFSET 0 +#define RTL8367D_I2C_CLOCK_DIV_MASK 0x3FF + +#define RTL8367D_REG_MDX_MDC_DIV 0x130b +#define RTL8367D_MDX_MDC_DIV_OFFSET 0 +#define RTL8367D_MDX_MDC_DIV_MASK 0x3FF + +#define RTL8367D_REG_MISCELLANEOUS_CONFIGURE0 0x130c +#define RTL8367D_FLASH_ENABLE_OFFSET 12 +#define RTL8367D_FLASH_ENABLE_MASK 0x1000 +#define RTL8367D_EEE_ENABLE_OFFSET 11 +#define RTL8367D_EEE_ENABLE_MASK 0x800 +#define RTL8367D_NIC_ENABLE_OFFSET 10 +#define RTL8367D_NIC_ENABLE_MASK 0x400 +#define RTL8367D_FT_ENABLE_OFFSET 9 +#define RTL8367D_FT_ENABLE_MASK 0x200 +#define RTL8367D_OLT_ENABLE_OFFSET 8 +#define RTL8367D_OLT_ENABLE_MASK 0x100 +#define RTL8367D_RTCT_EN_OFFSET 7 +#define RTL8367D_RTCT_EN_MASK 0x80 +#define RTL8367D_PON_LIGHT_EN_OFFSET 6 +#define RTL8367D_PON_LIGHT_EN_MASK 0x40 +#define RTL8367D_DW8051_EN_OFFSET 5 +#define RTL8367D_DW8051_EN_MASK 0x20 +#define RTL8367D_AUTOLOAD_EN_OFFSET 4 +#define RTL8367D_AUTOLOAD_EN_MASK 0x10 +#define RTL8367D_NRESTORE_EN_OFFSET 3 +#define RTL8367D_NRESTORE_EN_MASK 0x8 +#define RTL8367D_DIS_PON_TABLE_INIT_OFFSET 2 +#define RTL8367D_DIS_PON_TABLE_INIT_MASK 0x4 +#define RTL8367D_DIS_PON_BIST_OFFSET 1 +#define RTL8367D_DIS_PON_BIST_MASK 0x2 +#define RTL8367D_EFUSE_EN_OFFSET 0 +#define RTL8367D_EFUSE_EN_MASK 0x1 + +#define RTL8367D_REG_MISCELLANEOUS_CONFIGURE1 0x130d +#define RTL8367D_GPHY_SMI_EN_OFFSET 15 +#define RTL8367D_GPHY_SMI_EN_MASK 0x8000 +#define RTL8367D_EEPROM_DEV_ADR_OFFSET 8 +#define RTL8367D_EEPROM_DEV_ADR_MASK 0x7F00 +#define RTL8367D_EEPROM_MSB_OFFSET 7 +#define RTL8367D_EEPROM_MSB_MASK 0x80 +#define RTL8367D_EEPROM_ADDRESS_16B_OFFSET 6 +#define RTL8367D_EEPROM_ADDRESS_16B_MASK 0x40 +#define RTL8367D_SPI_SLAVE_EN_OFFSET 2 +#define RTL8367D_SPI_SLAVE_EN_MASK 0x4 +#define RTL8367D_SMI_SEL_OFFSET 0 +#define RTL8367D_SMI_SEL_MASK 0x3 + +#define RTL8367D_REG_PHY_AD 0x130f +#define RTL8367D_EN_PHY_MAX_POWER_OFFSET 14 +#define RTL8367D_EN_PHY_MAX_POWER_MASK 0x4000 +#define RTL8367D_EN_PHY_SEL_DEG_OFFSET 13 +#define RTL8367D_EN_PHY_SEL_DEG_MASK 0x2000 +#define RTL8367D_EXTPHY_AD_OFFSET 8 +#define RTL8367D_EXTPHY_AD_MASK 0x1F00 +#define RTL8367D_EN_PHY_LOW_POWER_MODE_OFFSET 7 +#define RTL8367D_EN_PHY_LOW_POWER_MODE_MASK 0x80 +#define RTL8367D_EN_PHY_GREEN_OFFSET 6 +#define RTL8367D_EN_PHY_GREEN_MASK 0x40 +#define RTL8367D_PDNPHY_OFFSET 5 +#define RTL8367D_PDNPHY_MASK 0x20 +#define RTL8367D_INTPHY_AD_OFFSET 0 +#define RTL8367D_INTPHY_AD_MASK 0x1F + +#define RTL8367D_REG_CHIP_RESET 0x1322 +#define RTL8367D_GPHY_RESET_OFFSET 6 +#define RTL8367D_GPHY_RESET_MASK 0x40 +#define RTL8367D_NIC_RST_OFFSET 5 +#define RTL8367D_NIC_RST_MASK 0x20 +#define RTL8367D_DW8051_RST_OFFSET 4 +#define RTL8367D_DW8051_RST_MASK 0x10 +#define RTL8367D_SDS_RST_OFFSET 3 +#define RTL8367D_SDS_RST_MASK 0x8 +#define RTL8367D_CONFIG_RST_OFFSET 2 +#define RTL8367D_CONFIG_RST_MASK 0x4 +#define RTL8367D_SW_RST_OFFSET 1 +#define RTL8367D_SW_RST_MASK 0x2 +#define RTL8367D_CHIP_RST_OFFSET 0 +#define RTL8367D_CHIP_RST_MASK 0x1 + +#define RTL8367D_REG_DIGITAL_DEBUG_0 0x1323 + +#define RTL8367D_REG_DIGITAL_DEBUG_1 0x1324 + +#define RTL8367D_REG_INTERNAL_PHY_MDC_DRIVER 0x1325 +#define RTL8367D_INTERNAL_PHY_MDC_DRIVER_OFFSET 0 +#define RTL8367D_INTERNAL_PHY_MDC_DRIVER_MASK 0x3FF + +#define RTL8367D_REG_LINKDOWN_TIME_CTRL 0x1326 +#define RTL8367D_LINKDOWN_TIME_CFG_OFFSET 9 +#define RTL8367D_LINKDOWN_TIME_CFG_MASK 0x7E00 +#define RTL8367D_LINKDOWN_TIME_ENABLE_OFFSET 8 +#define RTL8367D_LINKDOWN_TIME_ENABLE_MASK 0x100 +#define RTL8367D_LINKDOWN_TIME_OFFSET 0 +#define RTL8367D_LINKDOWN_TIME_MASK 0xFF + +#define RTL8367D_REG_PHYACK_TIMEOUT 0x1331 + +#define RTL8367D_REG_MDXACK_TIMEOUT 0x1333 + +#define RTL8367D_REG_DW8051_RDY 0x1336 +#define RTL8367D_VIAROM_WRITE_EN_OFFSET 9 +#define RTL8367D_VIAROM_WRITE_EN_MASK 0x200 +#define RTL8367D_SPIF_CK2_OFFSET 8 +#define RTL8367D_SPIF_CK2_MASK 0x100 +#define RTL8367D_EEPROM_EN_OFFSET 7 +#define RTL8367D_EEPROM_EN_MASK 0x80 +#define RTL8367D_DW8051_RATE_OFFSET 4 +#define RTL8367D_DW8051_RATE_MASK 0x70 +#define RTL8367D_IROM_MSB_OFFSET 2 +#define RTL8367D_IROM_MSB_MASK 0xC +#define RTL8367D_ACS_IROM_ENABLE_OFFSET 1 +#define RTL8367D_ACS_IROM_ENABLE_MASK 0x2 +#define RTL8367D_DW8051_READY_OFFSET 0 +#define RTL8367D_DW8051_READY_MASK 0x1 + +#define RTL8367D_REG_DIAG_MODE2 0x133d +#define RTL8367D_DIAG_MODE2_ACTRAM_OFFSET 1 +#define RTL8367D_DIAG_MODE2_ACTRAM_MASK 0x2 +#define RTL8367D_DIAG_MODE2_BCAM_ACTION_OFFSET 0 +#define RTL8367D_DIAG_MODE2_BCAM_ACTION_MASK 0x1 + +#define RTL8367D_REG_MDX_PHY_REG0 0x133e +#define RTL8367D_PHY_BRD_MASK_OFFSET 4 +#define RTL8367D_PHY_BRD_MASK_MASK 0x1F0 +#define RTL8367D_MDX_INDACC_PAGE_OFFSET 0 +#define RTL8367D_MDX_INDACC_PAGE_MASK 0xF + +#define RTL8367D_REG_MDX_PHY_REG1 0x133f +#define RTL8367D_PHY_BRD_MODE_OFFSET 5 +#define RTL8367D_PHY_BRD_MODE_MASK 0x20 +#define RTL8367D_BRD_PHYAD_OFFSET 0 +#define RTL8367D_BRD_PHYAD_MASK 0x1F + +#define RTL8367D_REG_DEBUG_SIGNAL_SELECT_A 0x1340 + +#define RTL8367D_REG_DEBUG_SIGNAL_SELECT_B 0x1341 +#define RTL8367D_DEBUG_SEL_OFFSET 4 +#define RTL8367D_DEBUG_SEL_MASK 0x70 +#define RTL8367D_DEBUG_SHIFT_OFFSET 0 +#define RTL8367D_DEBUG_SHIFT_MASK 0xF + +#define RTL8367D_REG_DEBUG_SIGNAL_I 0x1343 + +#define RTL8367D_REG_DEBUG_SIGNAL_H 0x1344 + +#define RTL8367D_REG_SD_TX_IDLE_TMR 0x1349 +#define RTL8367D_SD_TX_IDLE_TMR_OFFSET 0 +#define RTL8367D_SD_TX_IDLE_TMR_MASK 0xFF + +#define RTL8367D_REG_BYPASS_ABLTY_LOCK 0x134a +#define RTL8367D_BYPASS_PHY_OFFSET 3 +#define RTL8367D_BYPASS_PHY_MASK 0xF8 +#define RTL8367D_BYPASS_EXT_OFFSET 0 +#define RTL8367D_BYPASS_EXT_MASK 0x7 + +#define RTL8367D_REG_ACL_GPIO0 0x134c +#define RTL8367D_ACL_GPIO_15_OFFSET 15 +#define RTL8367D_ACL_GPIO_15_MASK 0x8000 +#define RTL8367D_ACL_GPIO_14_OFFSET 14 +#define RTL8367D_ACL_GPIO_14_MASK 0x4000 +#define RTL8367D_ACL_GPIO_13_OFFSET 13 +#define RTL8367D_ACL_GPIO_13_MASK 0x2000 +#define RTL8367D_ACL_GPIO_12_OFFSET 12 +#define RTL8367D_ACL_GPIO_12_MASK 0x1000 +#define RTL8367D_ACL_GPIO_11_OFFSET 11 +#define RTL8367D_ACL_GPIO_11_MASK 0x800 +#define RTL8367D_ACL_GPIO_10_OFFSET 10 +#define RTL8367D_ACL_GPIO_10_MASK 0x400 +#define RTL8367D_ACL_GPIO_9_OFFSET 9 +#define RTL8367D_ACL_GPIO_9_MASK 0x200 +#define RTL8367D_ACL_GPIO_8_OFFSET 8 +#define RTL8367D_ACL_GPIO_8_MASK 0x100 +#define RTL8367D_ACL_GPIO_7_OFFSET 7 +#define RTL8367D_ACL_GPIO_7_MASK 0x80 +#define RTL8367D_ACL_GPIO_6_OFFSET 6 +#define RTL8367D_ACL_GPIO_6_MASK 0x40 +#define RTL8367D_ACL_GPIO_5_OFFSET 5 +#define RTL8367D_ACL_GPIO_5_MASK 0x20 +#define RTL8367D_ACL_GPIO_4_OFFSET 4 +#define RTL8367D_ACL_GPIO_4_MASK 0x10 +#define RTL8367D_ACL_GPIO_3_OFFSET 3 +#define RTL8367D_ACL_GPIO_3_MASK 0x8 +#define RTL8367D_ACL_GPIO_2_OFFSET 2 +#define RTL8367D_ACL_GPIO_2_MASK 0x4 +#define RTL8367D_ACL_GPIO_1_OFFSET 1 +#define RTL8367D_ACL_GPIO_1_MASK 0x2 +#define RTL8367D_ACL_GPIO_0_OFFSET 0 +#define RTL8367D_ACL_GPIO_0_MASK 0x1 + +#define RTL8367D_REG_ACL_GPIO1 0x134d +#define RTL8367D_ACL_GPIO_31_OFFSET 15 +#define RTL8367D_ACL_GPIO_31_MASK 0x8000 +#define RTL8367D_ACL_GPIO_30_OFFSET 14 +#define RTL8367D_ACL_GPIO_30_MASK 0x4000 +#define RTL8367D_ACL_GPIO_29_OFFSET 13 +#define RTL8367D_ACL_GPIO_29_MASK 0x2000 +#define RTL8367D_ACL_GPIO_28_OFFSET 12 +#define RTL8367D_ACL_GPIO_28_MASK 0x1000 +#define RTL8367D_ACL_GPIO_27_OFFSET 11 +#define RTL8367D_ACL_GPIO_27_MASK 0x800 +#define RTL8367D_ACL_GPIO_26_OFFSET 10 +#define RTL8367D_ACL_GPIO_26_MASK 0x400 +#define RTL8367D_ACL_GPIO_25_OFFSET 9 +#define RTL8367D_ACL_GPIO_25_MASK 0x200 +#define RTL8367D_ACL_GPIO_24_OFFSET 8 +#define RTL8367D_ACL_GPIO_24_MASK 0x100 +#define RTL8367D_ACL_GPIO_23_OFFSET 7 +#define RTL8367D_ACL_GPIO_23_MASK 0x80 +#define RTL8367D_ACL_GPIO_22_OFFSET 6 +#define RTL8367D_ACL_GPIO_22_MASK 0x40 +#define RTL8367D_ACL_GPIO_21_OFFSET 5 +#define RTL8367D_ACL_GPIO_21_MASK 0x20 +#define RTL8367D_ACL_GPIO_20_OFFSET 4 +#define RTL8367D_ACL_GPIO_20_MASK 0x10 +#define RTL8367D_ACL_GPIO_19_OFFSET 3 +#define RTL8367D_ACL_GPIO_19_MASK 0x8 +#define RTL8367D_ACL_GPIO_18_OFFSET 2 +#define RTL8367D_ACL_GPIO_18_MASK 0x4 +#define RTL8367D_ACL_GPIO_17_OFFSET 1 +#define RTL8367D_ACL_GPIO_17_MASK 0x2 +#define RTL8367D_ACL_GPIO_16_OFFSET 0 +#define RTL8367D_ACL_GPIO_16_MASK 0x1 + +#define RTL8367D_REG_ACL_GPIO2 0x134e +#define RTL8367D_ACL_GPIO_47_OFFSET 15 +#define RTL8367D_ACL_GPIO_47_MASK 0x8000 +#define RTL8367D_ACL_GPIO_46_OFFSET 14 +#define RTL8367D_ACL_GPIO_46_MASK 0x4000 +#define RTL8367D_ACL_GPIO_45_OFFSET 13 +#define RTL8367D_ACL_GPIO_45_MASK 0x2000 +#define RTL8367D_ACL_GPIO_44_OFFSET 12 +#define RTL8367D_ACL_GPIO_44_MASK 0x1000 +#define RTL8367D_ACL_GPIO_43_OFFSET 11 +#define RTL8367D_ACL_GPIO_43_MASK 0x800 +#define RTL8367D_ACL_GPIO_42_OFFSET 10 +#define RTL8367D_ACL_GPIO_42_MASK 0x400 +#define RTL8367D_ACL_GPIO_41_OFFSET 9 +#define RTL8367D_ACL_GPIO_41_MASK 0x200 +#define RTL8367D_ACL_GPIO_40_OFFSET 8 +#define RTL8367D_ACL_GPIO_40_MASK 0x100 +#define RTL8367D_ACL_GPIO_39_OFFSET 7 +#define RTL8367D_ACL_GPIO_39_MASK 0x80 +#define RTL8367D_ACL_GPIO_38_OFFSET 6 +#define RTL8367D_ACL_GPIO_38_MASK 0x40 +#define RTL8367D_ACL_GPIO_37_OFFSET 5 +#define RTL8367D_ACL_GPIO_37_MASK 0x20 +#define RTL8367D_ACL_GPIO_36_OFFSET 4 +#define RTL8367D_ACL_GPIO_36_MASK 0x10 +#define RTL8367D_ACL_GPIO_35_OFFSET 3 +#define RTL8367D_ACL_GPIO_35_MASK 0x8 +#define RTL8367D_ACL_GPIO_34_OFFSET 2 +#define RTL8367D_ACL_GPIO_34_MASK 0x4 +#define RTL8367D_ACL_GPIO_33_OFFSET 1 +#define RTL8367D_ACL_GPIO_33_MASK 0x2 +#define RTL8367D_ACL_GPIO_32_OFFSET 0 +#define RTL8367D_ACL_GPIO_32_MASK 0x1 + +#define RTL8367D_REG_ACL_GPIO3 0x134f +#define RTL8367D_ACL_GPIO_61_OFFSET 13 +#define RTL8367D_ACL_GPIO_61_MASK 0x2000 +#define RTL8367D_ACL_GPIO_60_OFFSET 12 +#define RTL8367D_ACL_GPIO_60_MASK 0x1000 +#define RTL8367D_ACL_GPIO_59_OFFSET 11 +#define RTL8367D_ACL_GPIO_59_MASK 0x800 +#define RTL8367D_ACL_GPIO_58_OFFSET 10 +#define RTL8367D_ACL_GPIO_58_MASK 0x400 +#define RTL8367D_ACL_GPIO_57_OFFSET 9 +#define RTL8367D_ACL_GPIO_57_MASK 0x200 +#define RTL8367D_ACL_GPIO_56_OFFSET 8 +#define RTL8367D_ACL_GPIO_56_MASK 0x100 +#define RTL8367D_ACL_GPIO_55_OFFSET 7 +#define RTL8367D_ACL_GPIO_55_MASK 0x80 +#define RTL8367D_ACL_GPIO_54_OFFSET 6 +#define RTL8367D_ACL_GPIO_54_MASK 0x40 +#define RTL8367D_ACL_GPIO_53_OFFSET 5 +#define RTL8367D_ACL_GPIO_53_MASK 0x20 +#define RTL8367D_ACL_GPIO_52_OFFSET 4 +#define RTL8367D_ACL_GPIO_52_MASK 0x10 +#define RTL8367D_ACL_GPIO_51_OFFSET 3 +#define RTL8367D_ACL_GPIO_51_MASK 0x8 +#define RTL8367D_ACL_GPIO_50_OFFSET 2 +#define RTL8367D_ACL_GPIO_50_MASK 0x4 +#define RTL8367D_ACL_GPIO_49_OFFSET 1 +#define RTL8367D_ACL_GPIO_49_MASK 0x2 +#define RTL8367D_ACL_GPIO_48_OFFSET 0 +#define RTL8367D_ACL_GPIO_48_MASK 0x1 + +#define RTL8367D_REG_UPS_CTRL0 0x1362 +#define RTL8367D_P3_REF_SD_BIT0_OFFSET 8 +#define RTL8367D_P3_REF_SD_BIT0_MASK 0xFF00 +#define RTL8367D_P2_REF_SD_OFFSET 0 +#define RTL8367D_P2_REF_SD_MASK 0xFF + +#define RTL8367D_REG_UPS_CTRL1 0x1363 +#define RTL8367D_UPS_OUT_OFFSET 8 +#define RTL8367D_UPS_OUT_MASK 0xFF00 +#define RTL8367D_FRC_SLOW_DOWN_EN_OFFSET 7 +#define RTL8367D_FRC_SLOW_DOWN_EN_MASK 0x80 +#define RTL8367D_UPS_WRITE_PULSE_OFFSET 1 +#define RTL8367D_UPS_WRITE_PULSE_MASK 0x2 +#define RTL8367D_UPS_EN_OFFSET 0 +#define RTL8367D_UPS_EN_MASK 0x1 + +#define RTL8367D_REG_UPS_CTRL2 0x1364 +#define RTL8367D_IGNOE_MAC5_LINK_OFFSET 15 +#define RTL8367D_IGNOE_MAC5_LINK_MASK 0x8000 +#define RTL8367D_AGREE_SLEEP_OFFSET 14 +#define RTL8367D_AGREE_SLEEP_MASK 0x4000 +#define RTL8367D_WAIT_FOR_AGREEMENT_OFFSET 13 +#define RTL8367D_WAIT_FOR_AGREEMENT_MASK 0x2000 +#define RTL8367D_WAKE_UP_BY_LINK_OFFSET 12 +#define RTL8367D_WAKE_UP_BY_LINK_MASK 0x1000 +#define RTL8367D_WAKE_UP_BY_PHY_OFFSET 11 +#define RTL8367D_WAKE_UP_BY_PHY_MASK 0x800 +#define RTL8367D_SLOW_CLK_TGL_RATE_OFFSET 7 +#define RTL8367D_SLOW_CLK_TGL_RATE_MASK 0x780 +#define RTL8367D_PLL_G1_CTRL_EN_OFFSET 6 +#define RTL8367D_PLL_G1_CTRL_EN_MASK 0x40 +#define RTL8367D_PLL_G0_CTRL_EN_OFFSET 5 +#define RTL8367D_PLL_G0_CTRL_EN_MASK 0x20 +#define RTL8367D_SLOW_DOWN_PLL_EN_OFFSET 4 +#define RTL8367D_SLOW_DOWN_PLL_EN_MASK 0x10 +#define RTL8367D_SLOW_DOWN_CLK_EN_OFFSET 3 +#define RTL8367D_SLOW_DOWN_CLK_EN_MASK 0x8 +#define RTL8367D_GATING_CLK_SDS_EN_OFFSET 2 +#define RTL8367D_GATING_CLK_SDS_EN_MASK 0x4 +#define RTL8367D_GATING_CLK_CHIP_EN_OFFSET 1 +#define RTL8367D_GATING_CLK_CHIP_EN_MASK 0x2 +#define RTL8367D_GATING_SW_EN_OFFSET 0 +#define RTL8367D_GATING_SW_EN_MASK 0x1 + +#define RTL8367D_REG_GATING_CLK_1 0x1365 +#define RTL8367D_ALDPS_MODE_4_OFFSET 15 +#define RTL8367D_ALDPS_MODE_4_MASK 0x8000 +#define RTL8367D_ALDPS_MODE_3_OFFSET 14 +#define RTL8367D_ALDPS_MODE_3_MASK 0x4000 +#define RTL8367D_ALDPS_MODE_2_OFFSET 13 +#define RTL8367D_ALDPS_MODE_2_MASK 0x2000 +#define RTL8367D_ALDPS_MODE_1_OFFSET 12 +#define RTL8367D_ALDPS_MODE_1_MASK 0x1000 +#define RTL8367D_ALDPS_MODE_0_OFFSET 11 +#define RTL8367D_ALDPS_MODE_0_MASK 0x800 +#define RTL8367D_UPS_DBGO_OFFSET 10 +#define RTL8367D_UPS_DBGO_MASK 0x400 +#define RTL8367D_IFMX_AFF_NOT_FF_OUT_OFFSET 9 +#define RTL8367D_IFMX_AFF_NOT_FF_OUT_MASK 0x200 +#define RTL8367D_WATER_LEVEL_FD_OFFSET 6 +#define RTL8367D_WATER_LEVEL_FD_MASK 0x1C0 +#define RTL8367D_WATER_LEVEL_Y2X_OFFSET 3 +#define RTL8367D_WATER_LEVEL_Y2X_MASK 0x38 +#define RTL8367D_WATER_LEVEL_X2Y_2_OFFSET 2 +#define RTL8367D_WATER_LEVEL_X2Y_2_MASK 0x4 +#define RTL8367D_IGNOE_MAC7_LINK_OFFSET 1 +#define RTL8367D_IGNOE_MAC7_LINK_MASK 0x2 +#define RTL8367D_IGNOE_MAC6_LINK_OFFSET 0 +#define RTL8367D_IGNOE_MAC6_LINK_MASK 0x1 + +#define RTL8367D_REG_UPS_CTRL4 0x1366 +#define RTL8367D_PROB_EN_OFFSET 6 +#define RTL8367D_PROB_EN_MASK 0x40 +#define RTL8367D_PLL_DOWN_OFFSET 1 +#define RTL8367D_PLL_DOWN_MASK 0x2 +#define RTL8367D_XTAL_DOWN_OFFSET 0 +#define RTL8367D_XTAL_DOWN_MASK 0x1 + +#define RTL8367D_REG_UPS_CTRL5 0x1367 +#define RTL8367D_FRC_CPU_ACPT_OFFSET 3 +#define RTL8367D_FRC_CPU_ACPT_MASK 0x8 +#define RTL8367D_UPS_CPU_ACPT_OFFSET 2 +#define RTL8367D_UPS_CPU_ACPT_MASK 0x4 +#define RTL8367D_UPS_DBG_4_OFFSET 0 +#define RTL8367D_UPS_DBG_4_MASK 0x3 + +#define RTL8367D_REG_UPS_CTRL6 0x1368 +#define RTL8367D_UPS_CTRL6_OFFSET 0 +#define RTL8367D_UPS_CTRL6_MASK 0xF + +#define RTL8367D_REG_EFUSE_CMD 0x1370 +#define RTL8367D_CFG_DLYCMD_TIMER_OFFSET 10 +#define RTL8367D_CFG_DLYCMD_TIMER_MASK 0x7C00 +#define RTL8367D_CFG_DLYCMD_SEL_OFFSET 8 +#define RTL8367D_CFG_DLYCMD_SEL_MASK 0x300 +#define RTL8367D_EFUSE_TRMF_OFFSET 3 +#define RTL8367D_EFUSE_TRMF_MASK 0x18 +#define RTL8367D_EFUSE_ACCESS_BUSY_OFFSET 2 +#define RTL8367D_EFUSE_ACCESS_BUSY_MASK 0x4 +#define RTL8367D_EFUSE_COMMAND_EN_OFFSET 1 +#define RTL8367D_EFUSE_COMMAND_EN_MASK 0x2 +#define RTL8367D_EFUSE_WR_OFFSET 0 +#define RTL8367D_EFUSE_WR_MASK 0x1 + +#define RTL8367D_REG_EFUSE_ADR 0x1371 +#define RTL8367D_DUMMY_15_10_OFFSET 8 +#define RTL8367D_DUMMY_15_10_MASK 0xFF00 +#define RTL8367D_EFUSE_ADDRESS_OFFSET 0 +#define RTL8367D_EFUSE_ADDRESS_MASK 0xFF + +#define RTL8367D_REG_EFUSE_WDAT 0x1372 + +#define RTL8367D_REG_EFUSE_RDAT 0x1373 + +#define RTL8367D_REG_I2C_CTRL 0x1374 +#define RTL8367D_MDX_MST_FAIL_LAT_OFFSET 1 +#define RTL8367D_MDX_MST_FAIL_LAT_MASK 0x2 +#define RTL8367D_MDX_MST_FAIL_CLRPS_OFFSET 0 +#define RTL8367D_MDX_MST_FAIL_CLRPS_MASK 0x1 + +#define RTL8367D_REG_EEE_CFG 0x1375 +#define RTL8367D_CFG_BYPASS_GATELPTD_OFFSET 11 +#define RTL8367D_CFG_BYPASS_GATELPTD_MASK 0x800 +#define RTL8367D_EEE_ABT_ADDR2_OFFSET 6 +#define RTL8367D_EEE_ABT_ADDR2_MASK 0x7C0 +#define RTL8367D_EEE_ABT_ADDR1_OFFSET 1 +#define RTL8367D_EEE_ABT_ADDR1_MASK 0x3E +#define RTL8367D_EEE_POLL_EN_OFFSET 0 +#define RTL8367D_EEE_POLL_EN_MASK 0x1 + +#define RTL8367D_REG_EEE_PAGE 0x1376 + +#define RTL8367D_REG_EEE_EXT_PAGE 0x1377 + +#define RTL8367D_REG_EEE_EN_SPD1000 0x1378 + +#define RTL8367D_REG_EEE_EN_SPD100 0x1379 + +#define RTL8367D_REG_EEE_LP_SPD1000 0x137a + +#define RTL8367D_REG_EEE_LP_SPD100 0x137b + +#define RTL8367D_REG_DW8051_PRO_REG0 0x13a0 + +#define RTL8367D_REG_DW8051_PRO_REG1 0x13a1 + +#define RTL8367D_REG_DW8051_PRO_REG2 0x13a2 + +#define RTL8367D_REG_DW8051_PRO_REG3 0x13a3 + +#define RTL8367D_REG_DW8051_PRO_REG4 0x13a4 + +#define RTL8367D_REG_DW8051_PRO_REG5 0x13a5 + +#define RTL8367D_REG_DW8051_PRO_REG6 0x13a6 + +#define RTL8367D_REG_DW8051_PRO_REG7 0x13a7 + +#define RTL8367D_REG_EXT1_RXFIFO 0x13b0 +#define RTL8367D_EXT1_RXFIFO_ERR_CNT_OFFSET 12 +#define RTL8367D_EXT1_RXFIFO_ERR_CNT_MASK 0xF000 +#define RTL8367D_EXT1_RXFIFO_CLR_ERR_CNT_OFFSET 10 +#define RTL8367D_EXT1_RXFIFO_CLR_ERR_CNT_MASK 0x400 +#define RTL8367D_EXT1_RXFIFO_CFG_EDPTR_CHK_OFFSET 9 +#define RTL8367D_EXT1_RXFIFO_CFG_EDPTR_CHK_MASK 0x200 +#define RTL8367D_EXT1_RXFIFO_CFG_BGPTR_CHK_OFFSET 8 +#define RTL8367D_EXT1_RXFIFO_CFG_BGPTR_CHK_MASK 0x100 +#define RTL8367D_EXT1_RXFIFO_CFG_AFO_IPG_CNT_OFFSET 4 +#define RTL8367D_EXT1_RXFIFO_CFG_AFO_IPG_CNT_MASK 0xF0 +#define RTL8367D_EXT1_RXFIFO_CFG_AFO_IPGCOMP_OFFSET 3 +#define RTL8367D_EXT1_RXFIFO_CFG_AFO_IPGCOMP_MASK 0x8 +#define RTL8367D_EXT1_RXFIFO_CFG_WATER_LEVEL_OFFSET 0 +#define RTL8367D_EXT1_RXFIFO_CFG_WATER_LEVEL_MASK 0x7 + +#define RTL8367D_REG_EXT1_TXFIFO 0x13b1 +#define RTL8367D_EXT1_TXFIFO_ERR_CNT_OFFSET 12 +#define RTL8367D_EXT1_TXFIFO_ERR_CNT_MASK 0xF000 +#define RTL8367D_EXT1_TXFIFO_CLR_ERR_CNT_OFFSET 10 +#define RTL8367D_EXT1_TXFIFO_CLR_ERR_CNT_MASK 0x400 +#define RTL8367D_EXT1_TXFIFO_CFG_EDPTR_CHK_OFFSET 9 +#define RTL8367D_EXT1_TXFIFO_CFG_EDPTR_CHK_MASK 0x200 +#define RTL8367D_EXT1_TXFIFO_CFG_BGPTR_CHK_OFFSET 8 +#define RTL8367D_EXT1_TXFIFO_CFG_BGPTR_CHK_MASK 0x100 +#define RTL8367D_EXT1_TXFIFO_CFG_AFO_IPG_CNT_OFFSET 4 +#define RTL8367D_EXT1_TXFIFO_CFG_AFO_IPG_CNT_MASK 0xF0 +#define RTL8367D_EXT1_TXFIFO_CFG_AFO_IPGCOMP_OFFSET 3 +#define RTL8367D_EXT1_TXFIFO_CFG_AFO_IPGCOMP_MASK 0x8 +#define RTL8367D_EXT1_TXFIFO_CFG_WATER_LEVEL_OFFSET 0 +#define RTL8367D_EXT1_TXFIFO_CFG_WATER_LEVEL_MASK 0x7 + +#define RTL8367D_REG_PROTECT_ID 0x13c0 + +#define RTL8367D_REG_CHIP_VER_INTL 0x13c1 +#define RTL8367D_CHIP_VER_INTL_OFFSET 0 +#define RTL8367D_CHIP_VER_INTL_MASK 0xF + +#define RTL8367D_REG_MAGIC_ID 0x13c2 + +#define RTL8367D_REG_DIGITAL_INTERFACE_SELECT_1 0x13c3 +#define RTL8367D_SKIP_MII_2_RXER_OFFSET 4 +#define RTL8367D_SKIP_MII_2_RXER_MASK 0x10 +#define RTL8367D_SELECT_GMII_2_OFFSET 0 +#define RTL8367D_SELECT_GMII_2_MASK 0xF + +#define RTL8367D_REG_EXT2_RGMXF 0x13c5 +#define RTL8367D_EXT2_RGTX_INV_OFFSET 6 +#define RTL8367D_EXT2_RGTX_INV_MASK 0x40 +#define RTL8367D_EXT2_RGRX_INV_OFFSET 5 +#define RTL8367D_EXT2_RGRX_INV_MASK 0x20 +#define RTL8367D_EXT2_RGMXF_OFFSET 0 +#define RTL8367D_EXT2_RGMXF_MASK 0x1F + +#define RTL8367D_REG_ROUTER_UPS_CFG 0x13c6 +#define RTL8367D_UPS_Status_OFFSET 1 +#define RTL8367D_UPS_Status_MASK 0x2 +#define RTL8367D_SoftStart_OFFSET 0 +#define RTL8367D_SoftStart_MASK 0x1 + +#define RTL8367D_REG_STOP_COUNT_TX_MIB 0x13e0 +#define RTL8367D_CFG_STOP_CNTTX_MIB_OFFSET 8 +#define RTL8367D_CFG_STOP_CNTTX_MIB_MASK 0x100 +#define RTL8367D_EN_RTT2_L_OFFSET 5 +#define RTL8367D_EN_RTT2_L_MASK 0x20 +#define RTL8367D_EN_RTT1_L_OFFSET 4 +#define RTL8367D_EN_RTT1_L_MASK 0x10 + +#define RTL8367D_REG_LED_DRI_CFG 0x13e1 +#define RTL8367D_ORG_COL_EXT_OFFSET 3 +#define RTL8367D_ORG_COL_EXT_MASK 0x8 +#define RTL8367D_ORG_CRS_EXT_OFFSET 2 +#define RTL8367D_ORG_CRS_EXT_MASK 0x4 +#define RTL8367D_G1_WAKE_STYLE_OFFSET 1 +#define RTL8367D_G1_WAKE_STYLE_MASK 0x2 +#define RTL8367D_LED_DRIVING_OFFSET 0 +#define RTL8367D_LED_DRIVING_MASK 0x1 + +#define RTL8367D_REG_CHIP_DEBUG2 0x13e2 +#define RTL8367D_RG2_DN_OFFSET 6 +#define RTL8367D_RG2_DN_MASK 0x1C0 +#define RTL8367D_RG2_DP_OFFSET 3 +#define RTL8367D_RG2_DP_MASK 0x38 +#define RTL8367D_DRI_EXT2_RG_OFFSET 2 +#define RTL8367D_DRI_EXT2_RG_MASK 0x4 +#define RTL8367D_DRI_EXT2_OFFSET 1 +#define RTL8367D_DRI_EXT2_MASK 0x2 +#define RTL8367D_SLR_EXt2_OFFSET 0 +#define RTL8367D_SLR_EXt2_MASK 0x1 + +#define RTL8367D_REG_DIGITAL_DEBUG_2 0x13e3 + +#define RTL8367D_REG_FIBER_RTL_OUI_CFG0 0x13e4 +#define RTL8367D_FIBER_RTL_OUI_CFG0_OFFSET 0 +#define RTL8367D_FIBER_RTL_OUI_CFG0_MASK 0xFF + +#define RTL8367D_REG_FIBER_RTL_OUI_CFG1 0x13e5 + +#define RTL8367D_REG_FIBER_CFG_0 0x13e6 +#define RTL8367D_REV_NUM_OFFSET 8 +#define RTL8367D_REV_NUM_MASK 0xF00 +#define RTL8367D_MODEL_NUM_OFFSET 0 +#define RTL8367D_MODEL_NUM_MASK 0x3F + +#define RTL8367D_REG_FIBER_CFG_1 0x13e7 +#define RTL8367D_FIBER_CFG_1_OFFSET 5 +#define RTL8367D_FIBER_CFG_1_MASK 0x20 + +#define RTL8367D_REG_FIBER_CFG_2 0x13e8 +#define RTL8367D_SEL_SDET_PS_OFFSET 12 +#define RTL8367D_SEL_SDET_PS_MASK 0xF000 +#define RTL8367D_UTP_DIS_RX_OFFSET 10 +#define RTL8367D_UTP_DIS_RX_MASK 0xC00 +#define RTL8367D_UTP_FRC_LD_OFFSET 8 +#define RTL8367D_UTP_FRC_LD_MASK 0x300 +#define RTL8367D_SDS_RX_DISABLE_OFFSET 6 +#define RTL8367D_SDS_RX_DISABLE_MASK 0xC0 +#define RTL8367D_SDS_TX_DISABLE_OFFSET 4 +#define RTL8367D_SDS_TX_DISABLE_MASK 0x30 +#define RTL8367D_SDS_PWR_ISO_OFFSET 2 +#define RTL8367D_SDS_PWR_ISO_MASK 0xC +#define RTL8367D_SDS_FRC_LD_OFFSET 0 +#define RTL8367D_SDS_FRC_LD_MASK 0x3 + +#define RTL8367D_REG_FIBER_CFG_3 0x13e9 +#define RTL8367D_FIBER_CFG_3_OFFSET 0 +#define RTL8367D_FIBER_CFG_3_MASK 0xFFF + +#define RTL8367D_REG_FIBER_CFG_4 0x13ea + +#define RTL8367D_REG_UTP_FIB_DET 0x13eb +#define RTL8367D_FORCE_SEL_FIBER_OFFSET 14 +#define RTL8367D_FORCE_SEL_FIBER_MASK 0xC000 +#define RTL8367D_FIB_FINAL_TIMER_OFFSET 12 +#define RTL8367D_FIB_FINAL_TIMER_MASK 0x3000 +#define RTL8367D_FIB_LINK_TIMER_OFFSET 10 +#define RTL8367D_FIB_LINK_TIMER_MASK 0xC00 +#define RTL8367D_FIB_SDET_TIMER_OFFSET 8 +#define RTL8367D_FIB_SDET_TIMER_MASK 0x300 +#define RTL8367D_UTP_LINK_TIMER_OFFSET 6 +#define RTL8367D_UTP_LINK_TIMER_MASK 0xC0 +#define RTL8367D_UTP_SDET_TIMER_OFFSET 4 +#define RTL8367D_UTP_SDET_TIMER_MASK 0x30 +#define RTL8367D_FORCE_AUTODET_OFFSET 3 +#define RTL8367D_FORCE_AUTODET_MASK 0x8 +#define RTL8367D_AUTODET_FSM_CLR_OFFSET 2 +#define RTL8367D_AUTODET_FSM_CLR_MASK 0x4 +#define RTL8367D_UTP_FIRST_OFFSET 1 +#define RTL8367D_UTP_FIRST_MASK 0x2 +#define RTL8367D_UTP_FIB_DISAUTODET_OFFSET 0 +#define RTL8367D_UTP_FIB_DISAUTODET_MASK 0x1 + +#define RTL8367D_REG_NRESTORE_MAGIC_NUM 0x13ec +#define RTL8367D_NRESTORE_MAGIC_NUM_MASK 0xFFFF +#define RTL8367D_EEPROM_PROGRAM_CYCLE_OFFSET 0 +#define RTL8367D_EEPROM_PROGRAM_CYCLE_MASK 0x3 + +#define RTL8367D_REG_MAC_ACTIVE 0x13ee +#define RTL8367D_FRC_MAC_ACTIVE_OFFSET 8 +#define RTL8367D_FRC_MAC_ACTIVE_MASK 0x100 +#define RTL8367D_MAC_ACTIVE_OFFSET 0 +#define RTL8367D_MAC_ACTIVE_MASK 0xFF + +#define RTL8367D_REG_SERDES_RESULT 0x13ef +#define RTL8367D_FIB100_DET_OFFSET 4 +#define RTL8367D_FIB100_DET_MASK 0x10 +#define RTL8367D_FIB_ISO_OFFSET 3 +#define RTL8367D_FIB_ISO_MASK 0x8 +#define RTL8367D_SDS_ANFAULT_OFFSET 2 +#define RTL8367D_SDS_ANFAULT_MASK 0x4 +#define RTL8367D_SDS_INTB_OFFSET 1 +#define RTL8367D_SDS_INTB_MASK 0x2 +#define RTL8367D_SDS_LINK_OK_OFFSET 0 +#define RTL8367D_SDS_LINK_OK_MASK 0x1 + +#define RTL8367D_REG_CHIP_ECO 0x13f0 +#define RTL8367D_CFG_CHIP_ECO_OFFSET 1 +#define RTL8367D_CFG_CHIP_ECO_MASK 0xFFFE +#define RTL8367D_CFG_CKOUTEN_OFFSET 0 +#define RTL8367D_CFG_CKOUTEN_MASK 0x1 + +#define RTL8367D_REG_WAKELPI_SLOT_PRD 0x13f1 +#define RTL8367D_WAKELPI_SLOT_PRD_OFFSET 0 +#define RTL8367D_WAKELPI_SLOT_PRD_MASK 0x1F + +#define RTL8367D_REG_WAKELPI_SLOT_PG0 0x13f2 +#define RTL8367D_WAKELPI_SLOT_P1_OFFSET 8 +#define RTL8367D_WAKELPI_SLOT_P1_MASK 0x1F00 +#define RTL8367D_WAKELPI_SLOT_P0_OFFSET 0 +#define RTL8367D_WAKELPI_SLOT_P0_MASK 0x1F + +#define RTL8367D_REG_WAKELPI_SLOT_PG1 0x13f3 +#define RTL8367D_WAKELPI_SLOT_P3_OFFSET 8 +#define RTL8367D_WAKELPI_SLOT_P3_MASK 0x1F00 +#define RTL8367D_WAKELPI_SLOT_P2_OFFSET 0 +#define RTL8367D_WAKELPI_SLOT_P2_MASK 0x1F + +#define RTL8367D_REG_WAKELPI_SLOT_PG2 0x13f4 +#define RTL8367D_WAKELPI_SLOT_P5_OFFSET 8 +#define RTL8367D_WAKELPI_SLOT_P5_MASK 0x1F00 +#define RTL8367D_WAKELPI_SLOT_P4_OFFSET 0 +#define RTL8367D_WAKELPI_SLOT_P4_MASK 0x1F + +#define RTL8367D_REG_WAKELPI_SLOT_PG3 0x13f5 +#define RTL8367D_WAKELPI_SLOT_P7_OFFSET 8 +#define RTL8367D_WAKELPI_SLOT_P7_MASK 0x1F00 +#define RTL8367D_WAKELPI_SLOT_P6_OFFSET 0 +#define RTL8367D_WAKELPI_SLOT_P6_MASK 0x1F + +#define RTL8367D_REG_SYNC_FIFO_0 0x13f6 +#define RTL8367D_SYNC_FIFO_TX_OFFSET 8 +#define RTL8367D_SYNC_FIFO_TX_MASK 0x700 +#define RTL8367D_SYNC_FIFO_RX_OFFSET 0 +#define RTL8367D_SYNC_FIFO_RX_MASK 0xFF + +#define RTL8367D_REG_SYNC_FIFO_1 0x13f7 +#define RTL8367D_SYNC_FIFO_TX_ERR_OFFSET 8 +#define RTL8367D_SYNC_FIFO_TX_ERR_MASK 0x700 +#define RTL8367D_SYNC_FIFO_RX_ERR_OFFSET 0 +#define RTL8367D_SYNC_FIFO_RX_ERR_MASK 0xFF + +#define RTL8367D_REG_RGM_EEE 0x13f8 +#define RTL8367D_EXT2_PAD_STOP_EN_OFFSET 14 +#define RTL8367D_EXT2_PAD_STOP_EN_MASK 0x4000 +#define RTL8367D_EXT1_PAD_STOP_EN_OFFSET 13 +#define RTL8367D_EXT1_PAD_STOP_EN_MASK 0x2000 +#define RTL8367D_EXT0_PAD_STOP_EN_OFFSET 12 +#define RTL8367D_EXT0_PAD_STOP_EN_MASK 0x1000 +#define RTL8367D_EXT2_CYCLE_PAD_OFFSET 8 +#define RTL8367D_EXT2_CYCLE_PAD_MASK 0xF00 +#define RTL8367D_EXT1_CYCLE_PAD_OFFSET 4 +#define RTL8367D_EXT1_CYCLE_PAD_MASK 0xF0 +#define RTL8367D_EXT0_CYCLE_PAD_OFFSET 0 +#define RTL8367D_EXT0_CYCLE_PAD_MASK 0xF + +#define RTL8367D_REG_EXT_TXC_DLY 0x13f9 +#define RTL8367D_EXT1_GMII_TX_DELAY_OFFSET 12 +#define RTL8367D_EXT1_GMII_TX_DELAY_MASK 0x7000 +#define RTL8367D_EXT0_GMII_TX_DELAY_OFFSET 9 +#define RTL8367D_EXT0_GMII_TX_DELAY_MASK 0xE00 +#define RTL8367D_EXT2_RGMII_TX_DELAY_OFFSET 6 +#define RTL8367D_EXT2_RGMII_TX_DELAY_MASK 0x1C0 +#define RTL8367D_EXT1_RGMII_TX_DELAY_OFFSET 3 +#define RTL8367D_EXT1_RGMII_TX_DELAY_MASK 0x38 +#define RTL8367D_EXT0_RGMII_TX_DELAY_OFFSET 0 +#define RTL8367D_EXT0_RGMII_TX_DELAY_MASK 0x7 + +#define RTL8367D_REG_CHIP_DUMMY_NO 0x13fb +#define RTL8367D_CHIP_DUMMY_NO_OFFSET 0 +#define RTL8367D_CHIP_DUMMY_NO_MASK 0xF + +#define RTL8367D_REG_EFUSE_CHK_0 0x13fc +#define RTL8367D_EFUSE_CHK_STOP_ADR_OFFSET 8 +#define RTL8367D_EFUSE_CHK_STOP_ADR_MASK 0xFF00 +#define RTL8367D_EFUSE_CHK_FAIL_OFFSET 2 +#define RTL8367D_EFUSE_CHK_FAIL_MASK 0x4 +#define RTL8367D_EFUSE_CHK_DONE_OFFSET 1 +#define RTL8367D_EFUSE_CHK_DONE_MASK 0x2 +#define RTL8367D_EFUSE_CHK_0_EFUSE_CHK_PS_OFFSET 0 +#define RTL8367D_EFUSE_CHK_0_EFUSE_CHK_PS_MASK 0x1 + +#define RTL8367D_REG_EFUSE_CHK_1 0x13fd +#define RTL8367D_EFUSE_CHK_END_OFFSET 8 +#define RTL8367D_EFUSE_CHK_END_MASK 0xFF00 +#define RTL8367D_EFUSE_CHK_BGN_OFFSET 0 +#define RTL8367D_EFUSE_CHK_BGN_MASK 0xFF + +#define RTL8367D_REG_EFUSE_CHK_2 0x13fe + +/* (16'h1400)mtrpool_reg */ + +#define RTL8367D_REG_METER0_RATE_CTRL0 0x1400 + +#define RTL8367D_REG_METER0_RATE_CTRL1 0x1401 +#define RTL8367D_METER0_RATE_CTRL1_OFFSET 0 +#define RTL8367D_METER0_RATE_CTRL1_MASK 0x7 + +#define RTL8367D_REG_METER1_RATE_CTRL0 0x1402 + +#define RTL8367D_REG_METER1_RATE_CTRL1 0x1403 +#define RTL8367D_METER1_RATE_CTRL1_OFFSET 0 +#define RTL8367D_METER1_RATE_CTRL1_MASK 0x7 + +#define RTL8367D_REG_METER2_RATE_CTRL0 0x1404 + +#define RTL8367D_REG_METER2_RATE_CTRL1 0x1405 +#define RTL8367D_METER2_RATE_CTRL1_OFFSET 0 +#define RTL8367D_METER2_RATE_CTRL1_MASK 0x7 + +#define RTL8367D_REG_METER3_RATE_CTRL0 0x1406 + +#define RTL8367D_REG_METER3_RATE_CTRL1 0x1407 +#define RTL8367D_METER3_RATE_CTRL1_OFFSET 0 +#define RTL8367D_METER3_RATE_CTRL1_MASK 0x7 + +#define RTL8367D_REG_METER4_RATE_CTRL0 0x1408 + +#define RTL8367D_REG_METER4_RATE_CTRL1 0x1409 +#define RTL8367D_METER4_RATE_CTRL1_OFFSET 0 +#define RTL8367D_METER4_RATE_CTRL1_MASK 0x7 + +#define RTL8367D_REG_METER5_RATE_CTRL0 0x140a + +#define RTL8367D_REG_METER5_RATE_CTRL1 0x140b +#define RTL8367D_METER5_RATE_CTRL1_OFFSET 0 +#define RTL8367D_METER5_RATE_CTRL1_MASK 0x7 + +#define RTL8367D_REG_METER6_RATE_CTRL0 0x140c + +#define RTL8367D_REG_METER6_RATE_CTRL1 0x140d +#define RTL8367D_METER6_RATE_CTRL1_OFFSET 0 +#define RTL8367D_METER6_RATE_CTRL1_MASK 0x7 + +#define RTL8367D_REG_METER7_RATE_CTRL0 0x140e + +#define RTL8367D_REG_METER7_RATE_CTRL1 0x140f +#define RTL8367D_METER7_RATE_CTRL1_OFFSET 0 +#define RTL8367D_METER7_RATE_CTRL1_MASK 0x7 + +#define RTL8367D_REG_METER8_RATE_CTRL0 0x1410 + +#define RTL8367D_REG_METER8_RATE_CTRL1 0x1411 +#define RTL8367D_METER8_RATE_CTRL1_OFFSET 0 +#define RTL8367D_METER8_RATE_CTRL1_MASK 0x7 + +#define RTL8367D_REG_METER9_RATE_CTRL0 0x1412 + +#define RTL8367D_REG_METER9_RATE_CTRL1 0x1413 +#define RTL8367D_METER9_RATE_CTRL1_OFFSET 0 +#define RTL8367D_METER9_RATE_CTRL1_MASK 0x7 + +#define RTL8367D_REG_METER10_RATE_CTRL0 0x1414 + +#define RTL8367D_REG_METER10_RATE_CTRL1 0x1415 +#define RTL8367D_METER10_RATE_CTRL1_OFFSET 0 +#define RTL8367D_METER10_RATE_CTRL1_MASK 0x7 + +#define RTL8367D_REG_METER11_RATE_CTRL0 0x1416 + +#define RTL8367D_REG_METER11_RATE_CTRL1 0x1417 +#define RTL8367D_METER11_RATE_CTRL1_OFFSET 0 +#define RTL8367D_METER11_RATE_CTRL1_MASK 0x7 + +#define RTL8367D_REG_METER12_RATE_CTRL0 0x1418 + +#define RTL8367D_REG_METER12_RATE_CTRL1 0x1419 +#define RTL8367D_METER12_RATE_CTRL1_OFFSET 0 +#define RTL8367D_METER12_RATE_CTRL1_MASK 0x7 + +#define RTL8367D_REG_METER13_RATE_CTRL0 0x141a + +#define RTL8367D_REG_METER13_RATE_CTRL1 0x141b +#define RTL8367D_METER13_RATE_CTRL1_OFFSET 0 +#define RTL8367D_METER13_RATE_CTRL1_MASK 0x7 + +#define RTL8367D_REG_METER14_RATE_CTRL0 0x141c + +#define RTL8367D_REG_METER14_RATE_CTRL1 0x141d +#define RTL8367D_METER14_RATE_CTRL1_OFFSET 0 +#define RTL8367D_METER14_RATE_CTRL1_MASK 0x7 + +#define RTL8367D_REG_METER15_RATE_CTRL0 0x141e + +#define RTL8367D_REG_METER15_RATE_CTRL1 0x141f +#define RTL8367D_METER15_RATE_CTRL1_OFFSET 0 +#define RTL8367D_METER15_RATE_CTRL1_MASK 0x7 + +#define RTL8367D_REG_METER16_RATE_CTRL0 0x1420 + +#define RTL8367D_REG_METER16_RATE_CTRL1 0x1421 +#define RTL8367D_METER16_RATE_CTRL1_OFFSET 0 +#define RTL8367D_METER16_RATE_CTRL1_MASK 0x7 + +#define RTL8367D_REG_METER17_RATE_CTRL0 0x1422 + +#define RTL8367D_REG_METER17_RATE_CTRL1 0x1423 +#define RTL8367D_METER17_RATE_CTRL1_OFFSET 0 +#define RTL8367D_METER17_RATE_CTRL1_MASK 0x7 + +#define RTL8367D_REG_METER18_RATE_CTRL0 0x1424 + +#define RTL8367D_REG_METER18_RATE_CTRL1 0x1425 +#define RTL8367D_METER18_RATE_CTRL1_OFFSET 0 +#define RTL8367D_METER18_RATE_CTRL1_MASK 0x7 + +#define RTL8367D_REG_METER19_RATE_CTRL0 0x1426 + +#define RTL8367D_REG_METER19_RATE_CTRL1 0x1427 +#define RTL8367D_METER19_RATE_CTRL1_OFFSET 0 +#define RTL8367D_METER19_RATE_CTRL1_MASK 0x7 + +#define RTL8367D_REG_METER20_RATE_CTRL0 0x1428 + +#define RTL8367D_REG_METER20_RATE_CTRL1 0x1429 +#define RTL8367D_METER20_RATE_CTRL1_OFFSET 0 +#define RTL8367D_METER20_RATE_CTRL1_MASK 0x7 + +#define RTL8367D_REG_METER21_RATE_CTRL0 0x142a + +#define RTL8367D_REG_METER21_RATE_CTRL1 0x142b +#define RTL8367D_METER21_RATE_CTRL1_OFFSET 0 +#define RTL8367D_METER21_RATE_CTRL1_MASK 0x7 + +#define RTL8367D_REG_METER22_RATE_CTRL0 0x142c + +#define RTL8367D_REG_METER22_RATE_CTRL1 0x142d +#define RTL8367D_METER22_RATE_CTRL1_OFFSET 0 +#define RTL8367D_METER22_RATE_CTRL1_MASK 0x7 + +#define RTL8367D_REG_METER23_RATE_CTRL0 0x142e + +#define RTL8367D_REG_METER23_RATE_CTRL1 0x142f +#define RTL8367D_METER23_RATE_CTRL1_OFFSET 0 +#define RTL8367D_METER23_RATE_CTRL1_MASK 0x7 + +#define RTL8367D_REG_METER24_RATE_CTRL0 0x1430 + +#define RTL8367D_REG_METER24_RATE_CTRL1 0x1431 +#define RTL8367D_METER24_RATE_CTRL1_OFFSET 0 +#define RTL8367D_METER24_RATE_CTRL1_MASK 0x7 + +#define RTL8367D_REG_METER25_RATE_CTRL0 0x1432 + +#define RTL8367D_REG_METER25_RATE_CTRL1 0x1433 +#define RTL8367D_METER25_RATE_CTRL1_OFFSET 0 +#define RTL8367D_METER25_RATE_CTRL1_MASK 0x7 + +#define RTL8367D_REG_METER26_RATE_CTRL0 0x1434 + +#define RTL8367D_REG_METER26_RATE_CTRL1 0x1435 +#define RTL8367D_METER26_RATE_CTRL1_OFFSET 0 +#define RTL8367D_METER26_RATE_CTRL1_MASK 0x7 + +#define RTL8367D_REG_METER27_RATE_CTRL0 0x1436 + +#define RTL8367D_REG_METER27_RATE_CTRL1 0x1437 +#define RTL8367D_METER27_RATE_CTRL1_OFFSET 0 +#define RTL8367D_METER27_RATE_CTRL1_MASK 0x7 + +#define RTL8367D_REG_METER28_RATE_CTRL0 0x1438 + +#define RTL8367D_REG_METER28_RATE_CTRL1 0x1439 +#define RTL8367D_METER28_RATE_CTRL1_OFFSET 0 +#define RTL8367D_METER28_RATE_CTRL1_MASK 0x7 + +#define RTL8367D_REG_METER29_RATE_CTRL0 0x143a + +#define RTL8367D_REG_METER29_RATE_CTRL1 0x143b +#define RTL8367D_METER29_RATE_CTRL1_OFFSET 0 +#define RTL8367D_METER29_RATE_CTRL1_MASK 0x7 + +#define RTL8367D_REG_METER30_RATE_CTRL0 0x143c + +#define RTL8367D_REG_METER30_RATE_CTRL1 0x143d +#define RTL8367D_METER30_RATE_CTRL1_OFFSET 0 +#define RTL8367D_METER30_RATE_CTRL1_MASK 0x7 + +#define RTL8367D_REG_METER31_RATE_CTRL0 0x143e + +#define RTL8367D_REG_METER31_RATE_CTRL1 0x143f +#define RTL8367D_METER31_RATE_CTRL1_OFFSET 0 +#define RTL8367D_METER31_RATE_CTRL1_MASK 0x7 + +#define RTL8367D_REG_METER32_RATE_CTRL0 0x1440 + +#define RTL8367D_REG_METER32_RATE_CTRL1 0x1441 +#define RTL8367D_METER32_RATE_CTRL1_OFFSET 0 +#define RTL8367D_METER32_RATE_CTRL1_MASK 0x7 + +#define RTL8367D_REG_METER33_RATE_CTRL0 0x1442 + +#define RTL8367D_REG_METER33_RATE_CTRL1 0x1443 +#define RTL8367D_METER33_RATE_CTRL1_OFFSET 0 +#define RTL8367D_METER33_RATE_CTRL1_MASK 0x7 + +#define RTL8367D_REG_METER34_RATE_CTRL0 0x1444 + +#define RTL8367D_REG_METER34_RATE_CTRL1 0x1445 +#define RTL8367D_METER34_RATE_CTRL1_OFFSET 0 +#define RTL8367D_METER34_RATE_CTRL1_MASK 0x7 + +#define RTL8367D_REG_METER35_RATE_CTRL0 0x1446 + +#define RTL8367D_REG_METER35_RATE_CTRL1 0x1447 +#define RTL8367D_METER35_RATE_CTRL1_OFFSET 0 +#define RTL8367D_METER35_RATE_CTRL1_MASK 0x7 + +#define RTL8367D_REG_METER36_RATE_CTRL0 0x1448 + +#define RTL8367D_REG_METER36_RATE_CTRL1 0x1449 +#define RTL8367D_METER36_RATE_CTRL1_OFFSET 0 +#define RTL8367D_METER36_RATE_CTRL1_MASK 0x7 + +#define RTL8367D_REG_METER37_RATE_CTRL0 0x144a + +#define RTL8367D_REG_METER37_RATE_CTRL1 0x144b +#define RTL8367D_METER37_RATE_CTRL1_OFFSET 0 +#define RTL8367D_METER37_RATE_CTRL1_MASK 0x7 + +#define RTL8367D_REG_METER38_RATE_CTRL0 0x144c + +#define RTL8367D_REG_METER38_RATE_CTRL1 0x144d +#define RTL8367D_METER38_RATE_CTRL1_OFFSET 0 +#define RTL8367D_METER38_RATE_CTRL1_MASK 0x7 + +#define RTL8367D_REG_METER39_RATE_CTRL0 0x144e + +#define RTL8367D_REG_METER39_RATE_CTRL1 0x144f +#define RTL8367D_METER39_RATE_CTRL1_OFFSET 0 +#define RTL8367D_METER39_RATE_CTRL1_MASK 0x7 + +#define RTL8367D_REG_METER_MODE_SETTING0 0x1460 + +#define RTL8367D_REG_METER_MODE_SETTING1 0x1461 + +#define RTL8367D_REG_METER_MODE_SETTING2 0x1462 +#define RTL8367D_METER_MODE_SETTING2_OFFSET 0 +#define RTL8367D_METER_MODE_SETTING2_MASK 0xFF + +#define RTL8367D_REG_METER_MODE_TOKEN_CFG 0x1463 +#define RTL8367D_METER_MODE_TOKEN_CFG_OFFSET 0 +#define RTL8367D_METER_MODE_TOKEN_CFG_MASK 0x7FF + +#define RTL8367D_REG_METER0_BUCKET_SIZE 0x1600 + +#define RTL8367D_REG_METER1_BUCKET_SIZE 0x1601 + +#define RTL8367D_REG_METER2_BUCKET_SIZE 0x1602 + +#define RTL8367D_REG_METER3_BUCKET_SIZE 0x1603 + +#define RTL8367D_REG_METER4_BUCKET_SIZE 0x1604 + +#define RTL8367D_REG_METER5_BUCKET_SIZE 0x1605 + +#define RTL8367D_REG_METER6_BUCKET_SIZE 0x1606 + +#define RTL8367D_REG_METER7_BUCKET_SIZE 0x1607 + +#define RTL8367D_REG_METER8_BUCKET_SIZE 0x1608 + +#define RTL8367D_REG_METER9_BUCKET_SIZE 0x1609 + +#define RTL8367D_REG_METER10_BUCKET_SIZE 0x160a + +#define RTL8367D_REG_METER11_BUCKET_SIZE 0x160b + +#define RTL8367D_REG_METER12_BUCKET_SIZE 0x160c + +#define RTL8367D_REG_METER13_BUCKET_SIZE 0x160d + +#define RTL8367D_REG_METER14_BUCKET_SIZE 0x160e + +#define RTL8367D_REG_METER15_BUCKET_SIZE 0x160f + +#define RTL8367D_REG_METER16_BUCKET_SIZE 0x1610 + +#define RTL8367D_REG_METER17_BUCKET_SIZE 0x1611 + +#define RTL8367D_REG_METER18_BUCKET_SIZE 0x1612 + +#define RTL8367D_REG_METER19_BUCKET_SIZE 0x1613 + +#define RTL8367D_REG_METER20_BUCKET_SIZE 0x1614 + +#define RTL8367D_REG_METER21_BUCKET_SIZE 0x1615 + +#define RTL8367D_REG_METER22_BUCKET_SIZE 0x1616 + +#define RTL8367D_REG_METER23_BUCKET_SIZE 0x1617 + +#define RTL8367D_REG_METER24_BUCKET_SIZE 0x1618 + +#define RTL8367D_REG_METER25_BUCKET_SIZE 0x1619 + +#define RTL8367D_REG_METER26_BUCKET_SIZE 0x161a + +#define RTL8367D_REG_METER27_BUCKET_SIZE 0x161b + +#define RTL8367D_REG_METER28_BUCKET_SIZE 0x161c + +#define RTL8367D_REG_METER29_BUCKET_SIZE 0x161d + +#define RTL8367D_REG_METER30_BUCKET_SIZE 0x161e + +#define RTL8367D_REG_METER31_BUCKET_SIZE 0x161f + +#define RTL8367D_REG_METER32_BUCKET_SIZE 0x1620 + +#define RTL8367D_REG_METER33_BUCKET_SIZE 0x1621 + +#define RTL8367D_REG_METER34_BUCKET_SIZE 0x1622 + +#define RTL8367D_REG_METER35_BUCKET_SIZE 0x1623 + +#define RTL8367D_REG_METER36_BUCKET_SIZE 0x1624 + +#define RTL8367D_REG_METER37_BUCKET_SIZE 0x1625 + +#define RTL8367D_REG_METER38_BUCKET_SIZE 0x1626 + +#define RTL8367D_REG_METER39_BUCKET_SIZE 0x1627 + +#define RTL8367D_REG_METER_CTRL0 0x1700 +#define RTL8367D_METER_OP_OFFSET 8 +#define RTL8367D_METER_OP_MASK 0x100 +#define RTL8367D_METER_TICK_OFFSET 0 +#define RTL8367D_METER_TICK_MASK 0xFF + +#define RTL8367D_REG_METER_CTRL1 0x1701 +#define RTL8367D_METER_CTRL1_OFFSET 0 +#define RTL8367D_METER_CTRL1_MASK 0xFF + +#define RTL8367D_REG_METER_OVERRATE_INDICATOR0 0x1702 + +#define RTL8367D_REG_METER_OVERRATE_INDICATOR1 0x1703 + +#define RTL8367D_REG_METER_OVERRATE_INDICATOR2 0x1704 +#define RTL8367D_METER_OVERRATE_INDICATOR2_OFFSET 0 +#define RTL8367D_METER_OVERRATE_INDICATOR2_MASK 0xFF + +#define RTL8367D_REG_METER_OVERRATE_INDICATOR0_8051 0x1705 + +#define RTL8367D_REG_METER_OVERRATE_INDICATOR1_8051 0x1706 + +#define RTL8367D_REG_METER_OVERRATE_INDICATOR2_8051 0x1707 +#define RTL8367D_METER_OVERRATE_INDICATOR2_8051_OFFSET 0 +#define RTL8367D_METER_OVERRATE_INDICATOR2_8051_MASK 0xFF + +#define RTL8367D_REG_METER_IFG_CTRL0 0x1712 +#define RTL8367D_METER15_IFG_OFFSET 15 +#define RTL8367D_METER15_IFG_MASK 0x8000 +#define RTL8367D_METER14_IFG_OFFSET 14 +#define RTL8367D_METER14_IFG_MASK 0x4000 +#define RTL8367D_METER13_IFG_OFFSET 13 +#define RTL8367D_METER13_IFG_MASK 0x2000 +#define RTL8367D_METER12_IFG_OFFSET 12 +#define RTL8367D_METER12_IFG_MASK 0x1000 +#define RTL8367D_METER11_IFG_OFFSET 11 +#define RTL8367D_METER11_IFG_MASK 0x800 +#define RTL8367D_METER10_IFG_OFFSET 10 +#define RTL8367D_METER10_IFG_MASK 0x400 +#define RTL8367D_METER9_IFG_OFFSET 9 +#define RTL8367D_METER9_IFG_MASK 0x200 +#define RTL8367D_METER8_IFG_OFFSET 8 +#define RTL8367D_METER8_IFG_MASK 0x100 +#define RTL8367D_METER7_IFG_OFFSET 7 +#define RTL8367D_METER7_IFG_MASK 0x80 +#define RTL8367D_METER6_IFG_OFFSET 6 +#define RTL8367D_METER6_IFG_MASK 0x40 +#define RTL8367D_METER5_IFG_OFFSET 5 +#define RTL8367D_METER5_IFG_MASK 0x20 +#define RTL8367D_METER4_IFG_OFFSET 4 +#define RTL8367D_METER4_IFG_MASK 0x10 +#define RTL8367D_METER3_IFG_OFFSET 3 +#define RTL8367D_METER3_IFG_MASK 0x8 +#define RTL8367D_METER2_IFG_OFFSET 2 +#define RTL8367D_METER2_IFG_MASK 0x4 +#define RTL8367D_METER1_IFG_OFFSET 1 +#define RTL8367D_METER1_IFG_MASK 0x2 +#define RTL8367D_METER0_IFG_OFFSET 0 +#define RTL8367D_METER0_IFG_MASK 0x1 + +#define RTL8367D_REG_METER_IFG_CTRL1 0x1713 +#define RTL8367D_METER31_IFG_OFFSET 15 +#define RTL8367D_METER31_IFG_MASK 0x8000 +#define RTL8367D_METER30_IFG_OFFSET 14 +#define RTL8367D_METER30_IFG_MASK 0x4000 +#define RTL8367D_METER29_IFG_OFFSET 13 +#define RTL8367D_METER29_IFG_MASK 0x2000 +#define RTL8367D_METER28_IFG_OFFSET 12 +#define RTL8367D_METER28_IFG_MASK 0x1000 +#define RTL8367D_METER27_IFG_OFFSET 11 +#define RTL8367D_METER27_IFG_MASK 0x800 +#define RTL8367D_METER26_IFG_OFFSET 10 +#define RTL8367D_METER26_IFG_MASK 0x400 +#define RTL8367D_METER25_IFG_OFFSET 9 +#define RTL8367D_METER25_IFG_MASK 0x200 +#define RTL8367D_METER24_IFG_OFFSET 8 +#define RTL8367D_METER24_IFG_MASK 0x100 +#define RTL8367D_METER23_IFG_OFFSET 7 +#define RTL8367D_METER23_IFG_MASK 0x80 +#define RTL8367D_METER22_IFG_OFFSET 6 +#define RTL8367D_METER22_IFG_MASK 0x40 +#define RTL8367D_METER21_IFG_OFFSET 5 +#define RTL8367D_METER21_IFG_MASK 0x20 +#define RTL8367D_METER20_IFG_OFFSET 4 +#define RTL8367D_METER20_IFG_MASK 0x10 +#define RTL8367D_METER19_IFG_OFFSET 3 +#define RTL8367D_METER19_IFG_MASK 0x8 +#define RTL8367D_METER18_IFG_OFFSET 2 +#define RTL8367D_METER18_IFG_MASK 0x4 +#define RTL8367D_METER17_IFG_OFFSET 1 +#define RTL8367D_METER17_IFG_MASK 0x2 +#define RTL8367D_METER16_IFG_OFFSET 0 +#define RTL8367D_METER16_IFG_MASK 0x1 + +#define RTL8367D_REG_METER_IFG_CTRL2 0x1714 +#define RTL8367D_METER39_IFG_OFFSET 7 +#define RTL8367D_METER39_IFG_MASK 0x80 +#define RTL8367D_METER38_IFG_OFFSET 6 +#define RTL8367D_METER38_IFG_MASK 0x40 +#define RTL8367D_METER37_IFG_OFFSET 5 +#define RTL8367D_METER37_IFG_MASK 0x20 +#define RTL8367D_METER36_IFG_OFFSET 4 +#define RTL8367D_METER36_IFG_MASK 0x10 +#define RTL8367D_METER35_IFG_OFFSET 3 +#define RTL8367D_METER35_IFG_MASK 0x8 +#define RTL8367D_METER34_IFG_OFFSET 2 +#define RTL8367D_METER34_IFG_MASK 0x4 +#define RTL8367D_METER33_IFG_OFFSET 1 +#define RTL8367D_METER33_IFG_MASK 0x2 +#define RTL8367D_METER32_IFG_OFFSET 0 +#define RTL8367D_METER32_IFG_MASK 0x1 + +#define RTL8367D_REG_METER_CTRL2 0x1722 +#define RTL8367D_cfg_mtr_tick_8g_OFFSET 8 +#define RTL8367D_cfg_mtr_tick_8g_MASK 0xFF00 +#define RTL8367D_cfg_mtr_dec_cnt_8g_OFFSET 0 +#define RTL8367D_cfg_mtr_dec_cnt_8g_MASK 0xFF + +#define RTL8367D_REG_METER_CTRL3 0x1723 +#define RTL8367D_cfg_mtr_tick_2hsg_OFFSET 8 +#define RTL8367D_cfg_mtr_tick_2hsg_MASK 0xFF00 +#define RTL8367D_cfg_mtr_dec_cnt_2hsg_OFFSET 0 +#define RTL8367D_cfg_mtr_dec_cnt_2hsg_MASK 0xFF + +/* (16'h1800)8051_RLDP_EEE_reg */ + +#define RTL8367D_REG_RLDP_CTRL0 0x18e0 +#define RTL8367D_RLDP_TRIGGER_MODE_OFFSET 14 +#define RTL8367D_RLDP_TRIGGER_MODE_MASK 0x4000 +#define RTL8367D_RLDP_FRC_LOOP_PORTMSK_OFFSET 6 +#define RTL8367D_RLDP_FRC_LOOP_PORTMSK_MASK 0x3FC0 +#define RTL8367D_RLDP_GEN_RANDOM_OFFSET 3 +#define RTL8367D_RLDP_GEN_RANDOM_MASK 0x8 +#define RTL8367D_RLDP_COMP_ID_OFFSET 2 +#define RTL8367D_RLDP_COMP_ID_MASK 0x4 +#define RTL8367D_RLDP_ENABLE_OFFSET 0 +#define RTL8367D_RLDP_ENABLE_MASK 0x1 + +#define RTL8367D_REG_RLDP_CTRL1 0x18e1 +#define RTL8367D_RLDP_RETRY_COUNT_LOOPSTATE_OFFSET 8 +#define RTL8367D_RLDP_RETRY_COUNT_LOOPSTATE_MASK 0xFF00 +#define RTL8367D_RLDP_RETRY_COUNT_CHKSTATE_OFFSET 0 +#define RTL8367D_RLDP_RETRY_COUNT_CHKSTATE_MASK 0xFF + +#define RTL8367D_REG_RLDP_CTRL2 0x18e2 + +#define RTL8367D_REG_RLDP_CTRL3 0x18e3 + +#define RTL8367D_REG_RLDP_CTRL4 0x18e4 +#define RTL8367D_RLDP_CTRL4_OFFSET 0 +#define RTL8367D_RLDP_CTRL4_MASK 0xFF + +#define RTL8367D_REG_RLDP_RAND_NUM0 0x18e5 + +#define RTL8367D_REG_RLDP_RAND_NUM1 0x18e6 + +#define RTL8367D_REG_RLDP_RAND_NUM2 0x18e7 + +#define RTL8367D_REG_RLDP_MAGIC_NUM0 0x18e8 + +#define RTL8367D_REG_RLDP_MAGIC_NUM1 0x18e9 + +#define RTL8367D_REG_RLDP_MAGIC_NUM2 0x18ea + +#define RTL8367D_REG_RLDP_LOOPED_INDICATOR 0x18eb +#define RTL8367D_RLDP_LOOPED_INDICATOR_OFFSET 0 +#define RTL8367D_RLDP_LOOPED_INDICATOR_MASK 0xFF + +#define RTL8367D_REG_RLDP_LOOP_PORT_REG0 0x18ec +#define RTL8367D_RLDP_LOOP_PORT_01_OFFSET 8 +#define RTL8367D_RLDP_LOOP_PORT_01_MASK 0x700 +#define RTL8367D_RLDP_LOOP_PORT_00_OFFSET 0 +#define RTL8367D_RLDP_LOOP_PORT_00_MASK 0x7 + +#define RTL8367D_REG_RLDP_LOOP_PORT_REG1 0x18ed +#define RTL8367D_RLDP_LOOP_PORT_03_OFFSET 8 +#define RTL8367D_RLDP_LOOP_PORT_03_MASK 0x700 +#define RTL8367D_RLDP_LOOP_PORT_02_OFFSET 0 +#define RTL8367D_RLDP_LOOP_PORT_02_MASK 0x7 + +#define RTL8367D_REG_RLDP_LOOP_PORT_REG2 0x18ee +#define RTL8367D_RLDP_LOOP_PORT_05_OFFSET 8 +#define RTL8367D_RLDP_LOOP_PORT_05_MASK 0x700 +#define RTL8367D_RLDP_LOOP_PORT_04_OFFSET 0 +#define RTL8367D_RLDP_LOOP_PORT_04_MASK 0x7 + +#define RTL8367D_REG_RLDP_LOOP_PORT_REG3 0x18ef +#define RTL8367D_RLDP_LOOP_PORT_07_OFFSET 8 +#define RTL8367D_RLDP_LOOP_PORT_07_MASK 0x700 +#define RTL8367D_RLDP_LOOP_PORT_06_OFFSET 0 +#define RTL8367D_RLDP_LOOP_PORT_06_MASK 0x7 + +#define RTL8367D_REG_RLDP_RELEASED_INDICATOR 0x18f0 +#define RTL8367D_RLDP_RELEASED_INDICATOR_OFFSET 0 +#define RTL8367D_RLDP_RELEASED_INDICATOR_MASK 0xFF + +#define RTL8367D_REG_RLDP_LOOPSTATUS_INDICATOR 0x18f1 +#define RTL8367D_RLDP_LOOPSTATUS_INDICATOR_OFFSET 0 +#define RTL8367D_RLDP_LOOPSTATUS_INDICATOR_MASK 0xFF + +/* (16'h1900)EEE_EEEP_reg */ + +#define RTL8367D_REG_REG_MULTIWAKE 0x1920 +#define RTL8367D_MULTIWAKE_TIME_UNIT_OFFSET 6 +#define RTL8367D_MULTIWAKE_TIME_UNIT_MASK 0xC0 +#define RTL8367D_MULTIWAKE_PORTS_OFFSET 3 +#define RTL8367D_MULTIWAKE_PORTS_MASK 0x38 +#define RTL8367D_MULTIWAKE_INTLV_OFFSET 1 +#define RTL8367D_MULTIWAKE_INTLV_MASK 0x6 +#define RTL8367D_MULTIWAKE_EN_OFFSET 0 +#define RTL8367D_MULTIWAKE_EN_MASK 0x1 + +#define RTL8367D_REG_REG_EEE_MISC 0x1921 +#define RTL8367D_EEE_WAIT_RX_INACTIVE_2P5G_OFFSET 7 +#define RTL8367D_EEE_WAIT_RX_INACTIVE_2P5G_MASK 0x80 +#define RTL8367D_EEE_WAIT_RX_INACTIVE_GE_OFFSET 6 +#define RTL8367D_EEE_WAIT_RX_INACTIVE_GE_MASK 0x40 +#define RTL8367D_EEE_WAIT_RX_INACTIVE_GELITE_OFFSET 5 +#define RTL8367D_EEE_WAIT_RX_INACTIVE_GELITE_MASK 0x20 +#define RTL8367D_EEE_EN_FC_EFCT_OFFSET 4 +#define RTL8367D_EEE_EN_FC_EFCT_MASK 0x10 +#define RTL8367D_EEE_REF_RXLPI_OFFSET 3 +#define RTL8367D_EEE_REF_RXLPI_MASK 0x8 +#define RTL8367D_EEE_LINK_UP_DELAY_OFFSET 1 +#define RTL8367D_EEE_LINK_UP_DELAY_MASK 0x6 +#define RTL8367D_EEE_TX_WAKE_SEL_OFFSET 0 +#define RTL8367D_EEE_TX_WAKE_SEL_MASK 0x1 + +#define RTL8367D_REG_REG_EEE_TX_LPI_MINIPG_GELITE 0x1922 + +#define RTL8367D_REG_REG_EEE_TX_LPI_MINIPG_FE 0x1923 + +#define RTL8367D_REG_REG_EEE_TX_LPI_MINIPG_2P5G 0x1924 + +#define RTL8367D_REG_REG_EEE_TX_LPI_MINIPG_GE 0x1925 + +#define RTL8367D_REG_REG_EEE_WAIT_RX_INACTIVE_TIMER_2P5G 0x1926 +#define RTL8367D_REG_EEE_WAIT_RX_INACTIVE_TIMER_2P5G_OFFSET 0 +#define RTL8367D_REG_EEE_WAIT_RX_INACTIVE_TIMER_2P5G_MASK 0xFF + +#define RTL8367D_REG_REG_EEE_WAIT_RX_INACTIVE_TIMER 0x1927 +#define RTL8367D_EEE_WAIT_RX_INACTIVE_TIMER_GE_OFFSET 8 +#define RTL8367D_EEE_WAIT_RX_INACTIVE_TIMER_GE_MASK 0xFF00 +#define RTL8367D_EEE_WAIT_RX_INACTIVE_TIMER_GELITE_OFFSET 0 +#define RTL8367D_EEE_WAIT_RX_INACTIVE_TIMER_GELITE_MASK 0xFF + +#define RTL8367D_REG_REG_EEE_LOW_Q_TX_DELAY_FE 0x1928 +#define RTL8367D_REG_EEE_LOW_Q_TX_DELAY_FE_OFFSET 0 +#define RTL8367D_REG_EEE_LOW_Q_TX_DELAY_FE_MASK 0xFFF + +#define RTL8367D_REG_REG_EEE_TX_WAKE_TIMER_FE 0x1929 +#define RTL8367D_REG_EEE_TX_WAKE_TIMER_FE_OFFSET 0 +#define RTL8367D_REG_EEE_TX_WAKE_TIMER_FE_MASK 0xFF + +#define RTL8367D_REG_REG_EEE_LOW_Q_TX_DELAY_GELITE 0x192a +#define RTL8367D_REG_EEE_LOW_Q_TX_DELAY_GELITE_OFFSET 0 +#define RTL8367D_REG_EEE_LOW_Q_TX_DELAY_GELITE_MASK 0xFFF + +#define RTL8367D_REG_REG_EEE_TX_WAKE_TIMER_GELITE 0x192b +#define RTL8367D_EEE_TX_PAUSE_WAKE_TIMER_GELITE_OFFSET 8 +#define RTL8367D_EEE_TX_PAUSE_WAKE_TIMER_GELITE_MASK 0xFF00 +#define RTL8367D_EEE_TX_WAKE_TIMER_GELITE_OFFSET 0 +#define RTL8367D_EEE_TX_WAKE_TIMER_GELITE_MASK 0xFF + +#define RTL8367D_REG_REG_EEE_LOW_Q_TX_DELAY_GE 0x192c +#define RTL8367D_REG_EEE_LOW_Q_TX_DELAY_GE_OFFSET 0 +#define RTL8367D_REG_EEE_LOW_Q_TX_DELAY_GE_MASK 0xFFF + +#define RTL8367D_REG_REG_EEE_TX_WAKE_TIMER_GE 0x192d +#define RTL8367D_EEE_TX_PAUSE_WAKE_TIMER_GE_OFFSET 8 +#define RTL8367D_EEE_TX_PAUSE_WAKE_TIMER_GE_MASK 0xFF00 +#define RTL8367D_EEE_TX_WAKE_TIMER_GE_OFFSET 0 +#define RTL8367D_EEE_TX_WAKE_TIMER_GE_MASK 0xFF + +#define RTL8367D_REG_REG_EEE_LOW_Q_TX_DELAY_2P5G 0x192e +#define RTL8367D_REG_EEE_LOW_Q_TX_DELAY_2P5G_OFFSET 0 +#define RTL8367D_REG_EEE_LOW_Q_TX_DELAY_2P5G_MASK 0xFFF + +#define RTL8367D_REG_REG_EEE_TX_WAKE_TIMER_2P5G 0x192f +#define RTL8367D_EEE_TX_PAUSE_WAKE_TIMER_2P5G_OFFSET 8 +#define RTL8367D_EEE_TX_PAUSE_WAKE_TIMER_2P5G_MASK 0xFF00 +#define RTL8367D_EEE_TX_WAKE_TIMER_2P5G_OFFSET 0 +#define RTL8367D_EEE_TX_WAKE_TIMER_2P5G_MASK 0xFF + +/* (16'h1b00)LED */ + +#define RTL8367D_REG_LED_SYS_CONFIG 0x1b00 +#define RTL8367D_LED_SYS_CONFIG_DUMMY_15_OFFSET 15 +#define RTL8367D_LED_SYS_CONFIG_DUMMY_15_MASK 0x8000 +#define RTL8367D_LED_SERIAL_OUT_MODE_OFFSET 14 +#define RTL8367D_LED_SERIAL_OUT_MODE_MASK 0x4000 +#define RTL8367D_LED_EEE_LPI_MODE_OFFSET 13 +#define RTL8367D_LED_EEE_LPI_MODE_MASK 0x2000 +#define RTL8367D_LED_EEE_LPI_EN_OFFSET 12 +#define RTL8367D_LED_EEE_LPI_EN_MASK 0x1000 +#define RTL8367D_LED_EEE_LPI_10_OFFSET 11 +#define RTL8367D_LED_EEE_LPI_10_MASK 0x800 +#define RTL8367D_LED_EEE_CAP_10_OFFSET 10 +#define RTL8367D_LED_EEE_CAP_10_MASK 0x400 +#define RTL8367D_LED_LPI_SEL_OFFSET 8 +#define RTL8367D_LED_LPI_SEL_MASK 0x300 +#define RTL8367D_SERI_LED_ACT_LOW_OFFSET 7 +#define RTL8367D_SERI_LED_ACT_LOW_MASK 0x80 +#define RTL8367D_LED_POWERON_2_OFFSET 6 +#define RTL8367D_LED_POWERON_2_MASK 0x40 +#define RTL8367D_LED_POWERON_1_OFFSET 5 +#define RTL8367D_LED_POWERON_1_MASK 0x20 +#define RTL8367D_LED_POWERON_0_OFFSET 4 +#define RTL8367D_LED_POWERON_0_MASK 0x10 +#define RTL8367D_LED_IO_DISABLE_OFFSET 3 +#define RTL8367D_LED_IO_DISABLE_MASK 0x8 +#define RTL8367D_DUMMY_2_OFFSET 2 +#define RTL8367D_DUMMY_2_MASK 0x4 +#define RTL8367D_LED_SERIAL2_OFFSET 1 +#define RTL8367D_LED_SERIAL2_MASK 0x2 +#define RTL8367D_LED_SELECT_OFFSET 0 +#define RTL8367D_LED_SELECT_MASK 0x1 + +#define RTL8367D_REG_LED_SYS_CONFIG2 0x1b01 +#define RTL8367D_LED_SYS_CONFIG2_DUMMY_OFFSET 2 +#define RTL8367D_LED_SYS_CONFIG2_DUMMY_MASK 0xFFFC +#define RTL8367D_GATE_LPTD_BYPASS_OFFSET 1 +#define RTL8367D_GATE_LPTD_BYPASS_MASK 0x2 +#define RTL8367D_LED_SPD_MODE_OFFSET 0 +#define RTL8367D_LED_SPD_MODE_MASK 0x1 + +#define RTL8367D_REG_LED_MODE 0x1b02 +#define RTL8367D_DLINK_TIME_OFFSET 15 +#define RTL8367D_DLINK_TIME_MASK 0x8000 +#define RTL8367D_LED_BUZZ_DUTY_OFFSET 14 +#define RTL8367D_LED_BUZZ_DUTY_MASK 0x4000 +#define RTL8367D_BUZZER_RATE_OFFSET 12 +#define RTL8367D_BUZZER_RATE_MASK 0x3000 +#define RTL8367D_LOOP_DETECT_MODE_OFFSET 11 +#define RTL8367D_LOOP_DETECT_MODE_MASK 0x800 +#define RTL8367D_SEL_PWRON_TIME_OFFSET 9 +#define RTL8367D_SEL_PWRON_TIME_MASK 0x600 +#define RTL8367D_EN_DLINK_LED_OFFSET 8 +#define RTL8367D_EN_DLINK_LED_MASK 0x100 +#define RTL8367D_LOOP_DETECT_RATE_OFFSET 6 +#define RTL8367D_LOOP_DETECT_RATE_MASK 0xC0 +#define RTL8367D_FORCE_RATE_OFFSET 4 +#define RTL8367D_FORCE_RATE_MASK 0x30 +#define RTL8367D_SEL_LEDRATE_OFFSET 1 +#define RTL8367D_SEL_LEDRATE_MASK 0xE +#define RTL8367D_SPEED_UP_OFFSET 0 +#define RTL8367D_SPEED_UP_MASK 0x1 + +#define RTL8367D_REG_LED_CONFIGURATION 0x1b03 +#define RTL8367D_LED_CONFIGURATION_DUMMY_OFFSET 15 +#define RTL8367D_LED_CONFIGURATION_DUMMY_MASK 0x8000 +#define RTL8367D_LED_CONFIG_SEL_OFFSET 14 +#define RTL8367D_LED_CONFIG_SEL_MASK 0x4000 +#define RTL8367D_DATA_LED_OFFSET 12 +#define RTL8367D_DATA_LED_MASK 0x3000 +#define RTL8367D_LED2_CFG_OFFSET 8 +#define RTL8367D_LED2_CFG_MASK 0xF00 +#define RTL8367D_LED1_CFG_OFFSET 4 +#define RTL8367D_LED1_CFG_MASK 0xF0 +#define RTL8367D_LED0_CFG_OFFSET 0 +#define RTL8367D_LED0_CFG_MASK 0xF + +#define RTL8367D_REG_RTCT_RESULTS_CFG 0x1b04 +#define RTL8367D_RTCT_2PAIR_FTT_OFFSET 15 +#define RTL8367D_RTCT_2PAIR_FTT_MASK 0x8000 +#define RTL8367D_RTCT_2PAIR_MODE_OFFSET 14 +#define RTL8367D_RTCT_2PAIR_MODE_MASK 0x4000 +#define RTL8367D_BLINK_EN_OFFSET 13 +#define RTL8367D_BLINK_EN_MASK 0x2000 +#define RTL8367D_TIMEOUT_OFFSET 12 +#define RTL8367D_TIMEOUT_MASK 0x1000 +#define RTL8367D_EN_CD_SAME_SHORT_OFFSET 11 +#define RTL8367D_EN_CD_SAME_SHORT_MASK 0x800 +#define RTL8367D_EN_CD_SAME_OPEN_OFFSET 10 +#define RTL8367D_EN_CD_SAME_OPEN_MASK 0x400 +#define RTL8367D_EN_CD_SAME_MISMATCH_OFFSET 9 +#define RTL8367D_EN_CD_SAME_MISMATCH_MASK 0x200 +#define RTL8367D_EN_CD_SAME_LINEDRIVER_OFFSET 8 +#define RTL8367D_EN_CD_SAME_LINEDRIVER_MASK 0x100 +#define RTL8367D_EN_CD_SHORT_OFFSET 7 +#define RTL8367D_EN_CD_SHORT_MASK 0x80 +#define RTL8367D_EN_AB_SHORT_OFFSET 6 +#define RTL8367D_EN_AB_SHORT_MASK 0x40 +#define RTL8367D_EN_CD_OPEN_OFFSET 5 +#define RTL8367D_EN_CD_OPEN_MASK 0x20 +#define RTL8367D_EN_AB_OPEN_OFFSET 4 +#define RTL8367D_EN_AB_OPEN_MASK 0x10 +#define RTL8367D_EN_CD_MISMATCH_OFFSET 3 +#define RTL8367D_EN_CD_MISMATCH_MASK 0x8 +#define RTL8367D_EN_AB_MISMATCH_OFFSET 2 +#define RTL8367D_EN_AB_MISMATCH_MASK 0x4 +#define RTL8367D_EN_CD_LINEDRIVER_OFFSET 1 +#define RTL8367D_EN_CD_LINEDRIVER_MASK 0x2 +#define RTL8367D_EN_AB_LINEDRIVER_OFFSET 0 +#define RTL8367D_EN_AB_LINEDRIVER_MASK 0x1 + +#define RTL8367D_REG_RTCT_LED 0x1b05 +#define RTL8367D_RTCT_LED_DUMMY_OFFSET 12 +#define RTL8367D_RTCT_LED_DUMMY_MASK 0xF000 +#define RTL8367D_RTCT_LED2_OFFSET 8 +#define RTL8367D_RTCT_LED2_MASK 0xF00 +#define RTL8367D_RTCT_LED1_OFFSET 4 +#define RTL8367D_RTCT_LED1_MASK 0xF0 +#define RTL8367D_RTCT_LED0_OFFSET 0 +#define RTL8367D_RTCT_LED0_MASK 0xF + +#define RTL8367D_REG_CPU_FORCE_LED_CFG 0x1b07 +#define RTL8367D_CPU_FORCE_LED_CFG_DUMMY_OFFSET 8 +#define RTL8367D_CPU_FORCE_LED_CFG_DUMMY_MASK 0xFF00 +#define RTL8367D_LED_FORCE_MODE_OFFSET 2 +#define RTL8367D_LED_FORCE_MODE_MASK 0xFC +#define RTL8367D_FORCE_MODE_OFFSET 0 +#define RTL8367D_FORCE_MODE_MASK 0x3 + +#define RTL8367D_REG_CPU_FORCE_LED0_CFG0 0x1b08 +#define RTL8367D_PORT7_LED0_MODE_OFFSET 14 +#define RTL8367D_PORT7_LED0_MODE_MASK 0xC000 +#define RTL8367D_PORT6_LED0_MODE_OFFSET 12 +#define RTL8367D_PORT6_LED0_MODE_MASK 0x3000 +#define RTL8367D_PORT5_LED0_MODE_OFFSET 10 +#define RTL8367D_PORT5_LED0_MODE_MASK 0xC00 +#define RTL8367D_PORT4_LED0_MODE_OFFSET 8 +#define RTL8367D_PORT4_LED0_MODE_MASK 0x300 +#define RTL8367D_PORT3_LED0_MODE_OFFSET 6 +#define RTL8367D_PORT3_LED0_MODE_MASK 0xC0 +#define RTL8367D_PORT2_LED0_MODE_OFFSET 4 +#define RTL8367D_PORT2_LED0_MODE_MASK 0x30 +#define RTL8367D_PORT1_LED0_MODE_OFFSET 2 +#define RTL8367D_PORT1_LED0_MODE_MASK 0xC +#define RTL8367D_PORT0_LED0_MODE_OFFSET 0 +#define RTL8367D_PORT0_LED0_MODE_MASK 0x3 + +#define RTL8367D_REG_CPU_FORCE_LED1_CFG0 0x1b0a +#define RTL8367D_PORT7_LED1_MODE_OFFSET 14 +#define RTL8367D_PORT7_LED1_MODE_MASK 0xC000 +#define RTL8367D_PORT6_LED1_MODE_OFFSET 12 +#define RTL8367D_PORT6_LED1_MODE_MASK 0x3000 +#define RTL8367D_PORT5_LED1_MODE_OFFSET 10 +#define RTL8367D_PORT5_LED1_MODE_MASK 0xC00 +#define RTL8367D_PORT4_LED1_MODE_OFFSET 8 +#define RTL8367D_PORT4_LED1_MODE_MASK 0x300 +#define RTL8367D_PORT3_LED1_MODE_OFFSET 6 +#define RTL8367D_PORT3_LED1_MODE_MASK 0xC0 +#define RTL8367D_PORT2_LED1_MODE_OFFSET 4 +#define RTL8367D_PORT2_LED1_MODE_MASK 0x30 +#define RTL8367D_PORT1_LED1_MODE_OFFSET 2 +#define RTL8367D_PORT1_LED1_MODE_MASK 0xC +#define RTL8367D_PORT0_LED1_MODE_OFFSET 0 +#define RTL8367D_PORT0_LED1_MODE_MASK 0x3 + +#define RTL8367D_REG_CPU_FORCE_LED2_CFG0 0x1b0c +#define RTL8367D_PORT7_LED2_MODE_OFFSET 14 +#define RTL8367D_PORT7_LED2_MODE_MASK 0xC000 +#define RTL8367D_PORT6_LED2_MODE_OFFSET 12 +#define RTL8367D_PORT6_LED2_MODE_MASK 0x3000 +#define RTL8367D_PORT5_LED2_MODE_OFFSET 10 +#define RTL8367D_PORT5_LED2_MODE_MASK 0xC00 +#define RTL8367D_PORT4_LED2_MODE_OFFSET 8 +#define RTL8367D_PORT4_LED2_MODE_MASK 0x300 +#define RTL8367D_PORT3_LED2_MODE_OFFSET 6 +#define RTL8367D_PORT3_LED2_MODE_MASK 0xC0 +#define RTL8367D_PORT2_LED2_MODE_OFFSET 4 +#define RTL8367D_PORT2_LED2_MODE_MASK 0x30 +#define RTL8367D_PORT1_LED2_MODE_OFFSET 2 +#define RTL8367D_PORT1_LED2_MODE_MASK 0xC +#define RTL8367D_PORT0_LED2_MODE_OFFSET 0 +#define RTL8367D_PORT0_LED2_MODE_MASK 0x3 + +#define RTL8367D_REG_LED_ACTIVE_LOW_CFG0 0x1b0e +#define RTL8367D_LED_ACTIVE_LOW_CFG0_DUMMY_15_OFFSET 15 +#define RTL8367D_LED_ACTIVE_LOW_CFG0_DUMMY_15_MASK 0x8000 +#define RTL8367D_PORT3_LED_ACTIVE_LOW_OFFSET 12 +#define RTL8367D_PORT3_LED_ACTIVE_LOW_MASK 0x7000 +#define RTL8367D_LED_ACTIVE_LOW_CFG0_DUMMY_11_OFFSET 11 +#define RTL8367D_LED_ACTIVE_LOW_CFG0_DUMMY_11_MASK 0x800 +#define RTL8367D_PORT2_LED_ACTIVE_LOW_OFFSET 8 +#define RTL8367D_PORT2_LED_ACTIVE_LOW_MASK 0x700 +#define RTL8367D_LED_ACTIVE_LOW_CFG0_DUMMY_7_OFFSET 7 +#define RTL8367D_LED_ACTIVE_LOW_CFG0_DUMMY_7_MASK 0x80 +#define RTL8367D_PORT1_LED_ACTIVE_LOW_OFFSET 4 +#define RTL8367D_PORT1_LED_ACTIVE_LOW_MASK 0x70 +#define RTL8367D_LED_ACTIVE_LOW_CFG0_DUMMY_3_OFFSET 3 +#define RTL8367D_LED_ACTIVE_LOW_CFG0_DUMMY_3_MASK 0x8 +#define RTL8367D_PORT0_LED_ACTIVE_LOW_OFFSET 0 +#define RTL8367D_PORT0_LED_ACTIVE_LOW_MASK 0x7 + +#define RTL8367D_REG_LED_ACTIVE_LOW_CFG1 0x1b0f +#define RTL8367D_LED_ACTIVE_LOW_CFG1_DUMMY_15_OFFSET 15 +#define RTL8367D_LED_ACTIVE_LOW_CFG1_DUMMY_15_MASK 0x8000 +#define RTL8367D_PORT7_LED_ACTIVE_LOW_OFFSET 12 +#define RTL8367D_PORT7_LED_ACTIVE_LOW_MASK 0x7000 +#define RTL8367D_LED_ACTIVE_LOW_CFG1_DUMMY_11_OFFSET 11 +#define RTL8367D_LED_ACTIVE_LOW_CFG1_DUMMY_11_MASK 0x800 +#define RTL8367D_PORT6_LED_ACTIVE_LOW_OFFSET 8 +#define RTL8367D_PORT6_LED_ACTIVE_LOW_MASK 0x700 +#define RTL8367D_LED_ACTIVE_LOW_CFG1_DUMMY_7_OFFSET 7 +#define RTL8367D_LED_ACTIVE_LOW_CFG1_DUMMY_7_MASK 0x80 +#define RTL8367D_PORT5_LED_ACTIVE_LOW_OFFSET 4 +#define RTL8367D_PORT5_LED_ACTIVE_LOW_MASK 0x70 +#define RTL8367D_LED_ACTIVE_LOW_CFG1_DUMMY_3_OFFSET 3 +#define RTL8367D_LED_ACTIVE_LOW_CFG1_DUMMY_3_MASK 0x8 +#define RTL8367D_PORT4_LED_ACTIVE_LOW_OFFSET 0 +#define RTL8367D_PORT4_LED_ACTIVE_LOW_MASK 0x7 + +#define RTL8367D_REG_SEL_RTCT_PARA 0x1b21 +#define RTL8367D_DO_RTCT_COMMAND_OFFSET 15 +#define RTL8367D_DO_RTCT_COMMAND_MASK 0x8000 +#define RTL8367D_SEL_RTCT_PARA_DUMMY_OFFSET 12 +#define RTL8367D_SEL_RTCT_PARA_DUMMY_MASK 0x7000 +#define RTL8367D_SEL_RTCT_RLSTLED_TIME_OFFSET 10 +#define RTL8367D_SEL_RTCT_RLSTLED_TIME_MASK 0xC00 +#define RTL8367D_SEL_RTCT_TEST_LED_TIME_OFFSET 8 +#define RTL8367D_SEL_RTCT_TEST_LED_TIME_MASK 0x300 +#define RTL8367D_EN_SCAN_RTCT_OFFSET 7 +#define RTL8367D_EN_SCAN_RTCT_MASK 0x80 +#define RTL8367D_EN_RTCT_TIMOUT_OFFSET 6 +#define RTL8367D_EN_RTCT_TIMOUT_MASK 0x40 +#define RTL8367D_EN_ALL_RTCT_OFFSET 5 +#define RTL8367D_EN_ALL_RTCT_MASK 0x20 +#define RTL8367D_SEL_RTCT_PLE_WID_OFFSET 0 +#define RTL8367D_SEL_RTCT_PLE_WID_MASK 0x1F + +#define RTL8367D_REG_RTCT_ENABLE 0x1b22 +#define RTL8367D_RTCT_ENABLE_DUMMY_OFFSET 5 +#define RTL8367D_RTCT_ENABLE_DUMMY_MASK 0xFFE0 +#define RTL8367D_RTCT_ENABLE_PORT_MASK_OFFSET 0 +#define RTL8367D_RTCT_ENABLE_PORT_MASK_MASK 0x1F + +#define RTL8367D_REG_RTCT_TIMEOUT 0x1b23 + +#define RTL8367D_REG_PARA_LED_IO_EN1 0x1b24 +#define RTL8367D_DUMMY_15_13_OFFSET 13 +#define RTL8367D_DUMMY_15_13_MASK 0xE000 +#define RTL8367D_LED1_PARA_P04_00_OFFSET 8 +#define RTL8367D_LED1_PARA_P04_00_MASK 0x1F00 +#define RTL8367D_DUMMY_7_5_OFFSET 5 +#define RTL8367D_DUMMY_7_5_MASK 0xE0 +#define RTL8367D_LED0_PARA_P04_00_OFFSET 0 +#define RTL8367D_LED0_PARA_P04_00_MASK 0x1F + +#define RTL8367D_REG_PARA_LED_IO_EN2 0x1b25 +#define RTL8367D_DUMMY_15_5_OFFSET 5 +#define RTL8367D_DUMMY_15_5_MASK 0xFFE0 +#define RTL8367D_LED2_PARA_P04_00_OFFSET 0 +#define RTL8367D_LED2_PARA_P04_00_MASK 0x1F + +#define RTL8367D_REG_SCAN0_LED_IO_EN 0x1b26 +#define RTL8367D_SCAN0_LED_IO_EN_DUMMY_OFFSET 3 +#define RTL8367D_SCAN0_LED_IO_EN_DUMMY_MASK 0xFFF8 +#define RTL8367D_LED_LOOP_DET_BUZZER_EN_OFFSET 2 +#define RTL8367D_LED_LOOP_DET_BUZZER_EN_MASK 0x4 +#define RTL8367D_LED_SERI_DATA_EN_OFFSET 1 +#define RTL8367D_LED_SERI_DATA_EN_MASK 0x2 +#define RTL8367D_LED_SERI_CLK_EN_OFFSET 0 +#define RTL8367D_LED_SERI_CLK_EN_MASK 0x1 + +#define RTL8367D_REG_LPI_LED_OPT1 0x1b28 +#define RTL8367D_LPI_TAG4_OFFSET 12 +#define RTL8367D_LPI_TAG4_MASK 0xF000 +#define RTL8367D_LPI_TAG3_OFFSET 8 +#define RTL8367D_LPI_TAG3_MASK 0xF00 +#define RTL8367D_LPI_TAG2_OFFSET 4 +#define RTL8367D_LPI_TAG2_MASK 0xF0 +#define RTL8367D_LPI_TAG1_OFFSET 0 +#define RTL8367D_LPI_TAG1_MASK 0xF + +#define RTL8367D_REG_LPI_LED_OPT2 0x1b29 +#define RTL8367D_LPI_LED_OPT2_DUMMY_OFFSET 15 +#define RTL8367D_LPI_LED_OPT2_DUMMY_MASK 0x8000 +#define RTL8367D_LPI_LED2_WEAK_OFFSET 14 +#define RTL8367D_LPI_LED2_WEAK_MASK 0x4000 +#define RTL8367D_LPI_LED1_WEAK_OFFSET 13 +#define RTL8367D_LPI_LED1_WEAK_MASK 0x2000 +#define RTL8367D_LPI_LED0_WEAK_OFFSET 12 +#define RTL8367D_LPI_LED0_WEAK_MASK 0x1000 +#define RTL8367D_LPI_LED2_OFFSET 11 +#define RTL8367D_LPI_LED2_MASK 0x800 +#define RTL8367D_LPI_LED1_OFFSET 10 +#define RTL8367D_LPI_LED1_MASK 0x400 +#define RTL8367D_LPI_LED0_OFFSET 9 +#define RTL8367D_LPI_LED0_MASK 0x200 +#define RTL8367D_LPI_TAG8_OFFSET 8 +#define RTL8367D_LPI_TAG8_MASK 0x100 +#define RTL8367D_LPI_TAG7_OFFSET 6 +#define RTL8367D_LPI_TAG7_MASK 0xC0 +#define RTL8367D_LPI_TAG6_OFFSET 4 +#define RTL8367D_LPI_TAG6_MASK 0x30 +#define RTL8367D_LPI_TAG5_OFFSET 0 +#define RTL8367D_LPI_TAG5_MASK 0xF + +#define RTL8367D_REG_LPI_LED_OPT3 0x1b2a +#define RTL8367D_LPI_LED_OPT3_DUMMY_OFFSET 3 +#define RTL8367D_LPI_LED_OPT3_DUMMY_MASK 0xFFF8 +#define RTL8367D_RESTORE_LED_RATE_SEL_OFFSET 1 +#define RTL8367D_RESTORE_LED_RATE_SEL_MASK 0x6 +#define RTL8367D_RESTORE_LED_SEL_OFFSET 0 +#define RTL8367D_RESTORE_LED_SEL_MASK 0x1 + +#define RTL8367D_REG_P0_LED_MUX 0x1b2b +#define RTL8367D_P0_LED_MUX_DUMMY_OFFSET 15 +#define RTL8367D_P0_LED_MUX_DUMMY_MASK 0x8000 +#define RTL8367D_CFG_P0_LED2_MUX_OFFSET 10 +#define RTL8367D_CFG_P0_LED2_MUX_MASK 0x7C00 +#define RTL8367D_CFG_P0_LED1_MUX_OFFSET 5 +#define RTL8367D_CFG_P0_LED1_MUX_MASK 0x3E0 +#define RTL8367D_CFG_P0_LED0_MUX_OFFSET 0 +#define RTL8367D_CFG_P0_LED0_MUX_MASK 0x1F + +#define RTL8367D_REG_P1_LED_MUX 0x1b2c +#define RTL8367D_P1_LED_MUX_DUMMY_OFFSET 15 +#define RTL8367D_P1_LED_MUX_DUMMY_MASK 0x8000 +#define RTL8367D_CFG_P1_LED2_MUX_OFFSET 10 +#define RTL8367D_CFG_P1_LED2_MUX_MASK 0x7C00 +#define RTL8367D_CFG_P1_LED1_MUX_OFFSET 5 +#define RTL8367D_CFG_P1_LED1_MUX_MASK 0x3E0 +#define RTL8367D_CFG_P1_LED0_MUX_OFFSET 0 +#define RTL8367D_CFG_P1_LED0_MUX_MASK 0x1F + +#define RTL8367D_REG_P2_LED_MUX 0x1b2d +#define RTL8367D_P2_LED_MUX_DUMMY_OFFSET 15 +#define RTL8367D_P2_LED_MUX_DUMMY_MASK 0x8000 +#define RTL8367D_CFG_P2_LED2_MUX_OFFSET 10 +#define RTL8367D_CFG_P2_LED2_MUX_MASK 0x7C00 +#define RTL8367D_CFG_P2_LED1_MUX_OFFSET 5 +#define RTL8367D_CFG_P2_LED1_MUX_MASK 0x3E0 +#define RTL8367D_CFG_P2_LED0_MUX_OFFSET 0 +#define RTL8367D_CFG_P2_LED0_MUX_MASK 0x1F + +#define RTL8367D_REG_P3_LED_MUX 0x1b2e +#define RTL8367D_P3_LED_MUX_DUMMY_OFFSET 15 +#define RTL8367D_P3_LED_MUX_DUMMY_MASK 0x8000 +#define RTL8367D_CFG_P3_LED2_MUX_OFFSET 10 +#define RTL8367D_CFG_P3_LED2_MUX_MASK 0x7C00 +#define RTL8367D_CFG_P3_LED1_MUX_OFFSET 5 +#define RTL8367D_CFG_P3_LED1_MUX_MASK 0x3E0 +#define RTL8367D_CFG_P3_LED0_MUX_OFFSET 0 +#define RTL8367D_CFG_P3_LED0_MUX_MASK 0x1F + +#define RTL8367D_REG_P4_LED_MUX 0x1b2f +#define RTL8367D_P4_LED_MUX_DUMMY_OFFSET 15 +#define RTL8367D_P4_LED_MUX_DUMMY_MASK 0x8000 +#define RTL8367D_CFG_P4_LED2_MUX_OFFSET 10 +#define RTL8367D_CFG_P4_LED2_MUX_MASK 0x7C00 +#define RTL8367D_CFG_P4_LED1_MUX_OFFSET 5 +#define RTL8367D_CFG_P4_LED1_MUX_MASK 0x3E0 +#define RTL8367D_CFG_P4_LED0_MUX_OFFSET 0 +#define RTL8367D_CFG_P4_LED0_MUX_MASK 0x1F + +#define RTL8367D_REG_LED0_DATA_CTRL 0x1b30 +#define RTL8367D_LED0_DATA_CTRL_DUMMY_OFFSET 9 +#define RTL8367D_LED0_DATA_CTRL_DUMMY_MASK 0xFE00 +#define RTL8367D_CFG_DATA_LED0_DIS_OFFSET 8 +#define RTL8367D_CFG_DATA_LED0_DIS_MASK 0x100 +#define RTL8367D_CFG_DATA_LED0_SEL_OFFSET 7 +#define RTL8367D_CFG_DATA_LED0_SEL_MASK 0x80 +#define RTL8367D_CFG_DATA_LED0_ACT_OFFSET 5 +#define RTL8367D_CFG_DATA_LED0_ACT_MASK 0x60 +#define RTL8367D_CFG_DATA_LED0_SPD_OFFSET 0 +#define RTL8367D_CFG_DATA_LED0_SPD_MASK 0x1F + +#define RTL8367D_REG_LED1_DATA_CTRL 0x1b31 +#define RTL8367D_LED1_DATA_CTRL_DUMMY_OFFSET 9 +#define RTL8367D_LED1_DATA_CTRL_DUMMY_MASK 0xFE00 +#define RTL8367D_CFG_DATA_LED1_DIS_OFFSET 8 +#define RTL8367D_CFG_DATA_LED1_DIS_MASK 0x100 +#define RTL8367D_CFG_DATA_LED1_SEL_OFFSET 7 +#define RTL8367D_CFG_DATA_LED1_SEL_MASK 0x80 +#define RTL8367D_CFG_DATA_LED1_ACT_OFFSET 5 +#define RTL8367D_CFG_DATA_LED1_ACT_MASK 0x60 +#define RTL8367D_CFG_DATA_LED1_SPD_OFFSET 0 +#define RTL8367D_CFG_DATA_LED1_SPD_MASK 0x1F + +#define RTL8367D_REG_LED2_DATA_CTRL 0x1b32 +#define RTL8367D_LED2_DATA_CTRL_DUMMY_OFFSET 9 +#define RTL8367D_LED2_DATA_CTRL_DUMMY_MASK 0xFE00 +#define RTL8367D_CFG_DATA_LED2_DIS_OFFSET 8 +#define RTL8367D_CFG_DATA_LED2_DIS_MASK 0x100 +#define RTL8367D_CFG_DATA_LED2_SEL_OFFSET 7 +#define RTL8367D_CFG_DATA_LED2_SEL_MASK 0x80 +#define RTL8367D_CFG_DATA_LED2_ACT_OFFSET 5 +#define RTL8367D_CFG_DATA_LED2_ACT_MASK 0x60 +#define RTL8367D_CFG_DATA_LED2_SPD_OFFSET 0 +#define RTL8367D_CFG_DATA_LED2_SPD_MASK 0x1F + +/* (16'h1c00)IGMP_EAV */ + +#define RTL8367D_REG_IGMP_MLD_CFG0 0x1c00 +#define RTL8367D_IGMP_MLD_PORTISO_LEAKY_OFFSET 15 +#define RTL8367D_IGMP_MLD_PORTISO_LEAKY_MASK 0x8000 +#define RTL8367D_IGMP_MLD_VLAN_LEAKY_OFFSET 14 +#define RTL8367D_IGMP_MLD_VLAN_LEAKY_MASK 0x4000 +#define RTL8367D_IGMP_MLD_DISCARD_STORM_FILTER_OFFSET 13 +#define RTL8367D_IGMP_MLD_DISCARD_STORM_FILTER_MASK 0x2000 + +#define RTL8367D_REG_IGMP_PORT0_CONTROL 0x1c05 +#define RTL8367D_IGMP_PORT0_CONTROL_MLDv2_OP_OFFSET 8 +#define RTL8367D_IGMP_PORT0_CONTROL_MLDv2_OP_MASK 0x300 +#define RTL8367D_IGMP_PORT0_CONTROL_MLDv1_OP_OFFSET 6 +#define RTL8367D_IGMP_PORT0_CONTROL_MLDv1_OP_MASK 0xC0 +#define RTL8367D_IGMP_PORT0_CONTROL_IGMPV3_OP_OFFSET 4 +#define RTL8367D_IGMP_PORT0_CONTROL_IGMPV3_OP_MASK 0x30 +#define RTL8367D_IGMP_PORT0_CONTROL_IGMPV2_OP_OFFSET 2 +#define RTL8367D_IGMP_PORT0_CONTROL_IGMPV2_OP_MASK 0xC +#define RTL8367D_IGMP_PORT0_CONTROL_IGMPV1_OP_OFFSET 0 +#define RTL8367D_IGMP_PORT0_CONTROL_IGMPV1_OP_MASK 0x3 + +#define RTL8367D_REG_IGMP_PORT1_CONTROL 0x1c06 +#define RTL8367D_IGMP_PORT1_CONTROL_MLDv2_OP_OFFSET 8 +#define RTL8367D_IGMP_PORT1_CONTROL_MLDv2_OP_MASK 0x300 +#define RTL8367D_IGMP_PORT1_CONTROL_MLDv1_OP_OFFSET 6 +#define RTL8367D_IGMP_PORT1_CONTROL_MLDv1_OP_MASK 0xC0 +#define RTL8367D_IGMP_PORT1_CONTROL_IGMPV3_OP_OFFSET 4 +#define RTL8367D_IGMP_PORT1_CONTROL_IGMPV3_OP_MASK 0x30 +#define RTL8367D_IGMP_PORT1_CONTROL_IGMPV2_OP_OFFSET 2 +#define RTL8367D_IGMP_PORT1_CONTROL_IGMPV2_OP_MASK 0xC +#define RTL8367D_IGMP_PORT1_CONTROL_IGMPV1_OP_OFFSET 0 +#define RTL8367D_IGMP_PORT1_CONTROL_IGMPV1_OP_MASK 0x3 + +#define RTL8367D_REG_IGMP_PORT2_CONTROL 0x1c07 +#define RTL8367D_IGMP_PORT2_CONTROL_MLDv2_OP_OFFSET 8 +#define RTL8367D_IGMP_PORT2_CONTROL_MLDv2_OP_MASK 0x300 +#define RTL8367D_IGMP_PORT2_CONTROL_MLDv1_OP_OFFSET 6 +#define RTL8367D_IGMP_PORT2_CONTROL_MLDv1_OP_MASK 0xC0 +#define RTL8367D_IGMP_PORT2_CONTROL_IGMPV3_OP_OFFSET 4 +#define RTL8367D_IGMP_PORT2_CONTROL_IGMPV3_OP_MASK 0x30 +#define RTL8367D_IGMP_PORT2_CONTROL_IGMPV2_OP_OFFSET 2 +#define RTL8367D_IGMP_PORT2_CONTROL_IGMPV2_OP_MASK 0xC +#define RTL8367D_IGMP_PORT2_CONTROL_IGMPV1_OP_OFFSET 0 +#define RTL8367D_IGMP_PORT2_CONTROL_IGMPV1_OP_MASK 0x3 + +#define RTL8367D_REG_IGMP_PORT3_CONTROL 0x1c08 +#define RTL8367D_IGMP_PORT3_CONTROL_MLDv2_OP_OFFSET 8 +#define RTL8367D_IGMP_PORT3_CONTROL_MLDv2_OP_MASK 0x300 +#define RTL8367D_IGMP_PORT3_CONTROL_MLDv1_OP_OFFSET 6 +#define RTL8367D_IGMP_PORT3_CONTROL_MLDv1_OP_MASK 0xC0 +#define RTL8367D_IGMP_PORT3_CONTROL_IGMPV3_OP_OFFSET 4 +#define RTL8367D_IGMP_PORT3_CONTROL_IGMPV3_OP_MASK 0x30 +#define RTL8367D_IGMP_PORT3_CONTROL_IGMPV2_OP_OFFSET 2 +#define RTL8367D_IGMP_PORT3_CONTROL_IGMPV2_OP_MASK 0xC +#define RTL8367D_IGMP_PORT3_CONTROL_IGMPV1_OP_OFFSET 0 +#define RTL8367D_IGMP_PORT3_CONTROL_IGMPV1_OP_MASK 0x3 + +#define RTL8367D_REG_IGMP_PORT4_CONTROL 0x1c09 +#define RTL8367D_IGMP_PORT4_CONTROL_MLDv2_OP_OFFSET 8 +#define RTL8367D_IGMP_PORT4_CONTROL_MLDv2_OP_MASK 0x300 +#define RTL8367D_IGMP_PORT4_CONTROL_MLDv1_OP_OFFSET 6 +#define RTL8367D_IGMP_PORT4_CONTROL_MLDv1_OP_MASK 0xC0 +#define RTL8367D_IGMP_PORT4_CONTROL_IGMPV3_OP_OFFSET 4 +#define RTL8367D_IGMP_PORT4_CONTROL_IGMPV3_OP_MASK 0x30 +#define RTL8367D_IGMP_PORT4_CONTROL_IGMPV2_OP_OFFSET 2 +#define RTL8367D_IGMP_PORT4_CONTROL_IGMPV2_OP_MASK 0xC +#define RTL8367D_IGMP_PORT4_CONTROL_IGMPV1_OP_OFFSET 0 +#define RTL8367D_IGMP_PORT4_CONTROL_IGMPV1_OP_MASK 0x3 + +#define RTL8367D_REG_IGMP_PORT5_CONTROL 0x1c0a +#define RTL8367D_IGMP_PORT5_CONTROL_MLDv2_OP_OFFSET 8 +#define RTL8367D_IGMP_PORT5_CONTROL_MLDv2_OP_MASK 0x300 +#define RTL8367D_IGMP_PORT5_CONTROL_MLDv1_OP_OFFSET 6 +#define RTL8367D_IGMP_PORT5_CONTROL_MLDv1_OP_MASK 0xC0 +#define RTL8367D_IGMP_PORT5_CONTROL_IGMPV3_OP_OFFSET 4 +#define RTL8367D_IGMP_PORT5_CONTROL_IGMPV3_OP_MASK 0x30 +#define RTL8367D_IGMP_PORT5_CONTROL_IGMPV2_OP_OFFSET 2 +#define RTL8367D_IGMP_PORT5_CONTROL_IGMPV2_OP_MASK 0xC +#define RTL8367D_IGMP_PORT5_CONTROL_IGMPV1_OP_OFFSET 0 +#define RTL8367D_IGMP_PORT5_CONTROL_IGMPV1_OP_MASK 0x3 + +#define RTL8367D_REG_IGMP_PORT6_CONTROL 0x1c0b +#define RTL8367D_IGMP_PORT6_CONTROL_MLDv2_OP_OFFSET 8 +#define RTL8367D_IGMP_PORT6_CONTROL_MLDv2_OP_MASK 0x300 +#define RTL8367D_IGMP_PORT6_CONTROL_MLDv1_OP_OFFSET 6 +#define RTL8367D_IGMP_PORT6_CONTROL_MLDv1_OP_MASK 0xC0 +#define RTL8367D_IGMP_PORT6_CONTROL_IGMPV3_OP_OFFSET 4 +#define RTL8367D_IGMP_PORT6_CONTROL_IGMPV3_OP_MASK 0x30 +#define RTL8367D_IGMP_PORT6_CONTROL_IGMPV2_OP_OFFSET 2 +#define RTL8367D_IGMP_PORT6_CONTROL_IGMPV2_OP_MASK 0xC +#define RTL8367D_IGMP_PORT6_CONTROL_IGMPV1_OP_OFFSET 0 +#define RTL8367D_IGMP_PORT6_CONTROL_IGMPV1_OP_MASK 0x3 + +#define RTL8367D_REG_IGMP_PORT7_CONTROL 0x1c0c +#define RTL8367D_IGMP_PORT7_CONTROL_MLDv2_OP_OFFSET 8 +#define RTL8367D_IGMP_PORT7_CONTROL_MLDv2_OP_MASK 0x300 +#define RTL8367D_IGMP_PORT7_CONTROL_MLDv1_OP_OFFSET 6 +#define RTL8367D_IGMP_PORT7_CONTROL_MLDv1_OP_MASK 0xC0 +#define RTL8367D_IGMP_PORT7_CONTROL_IGMPV3_OP_OFFSET 4 +#define RTL8367D_IGMP_PORT7_CONTROL_IGMPV3_OP_MASK 0x30 +#define RTL8367D_IGMP_PORT7_CONTROL_IGMPV2_OP_OFFSET 2 +#define RTL8367D_IGMP_PORT7_CONTROL_IGMPV2_OP_MASK 0xC +#define RTL8367D_IGMP_PORT7_CONTROL_IGMPV1_OP_OFFSET 0 +#define RTL8367D_IGMP_PORT7_CONTROL_IGMPV1_OP_MASK 0x3 + +#define RTL8367D_REG_IGMP_MLD_CFG3 0x1c15 +#define RTL8367D_IGMP_MLD_IP6_BYPASS_OFFSET 5 +#define RTL8367D_IGMP_MLD_IP6_BYPASS_MASK 0x20 +#define RTL8367D_IGMP_MLD_IP4_BYPASS_239_255_255_OFFSET 4 +#define RTL8367D_IGMP_MLD_IP4_BYPASS_239_255_255_MASK 0x10 +#define RTL8367D_IGMP_MLD_IP4_BYPASS_224_0_1_OFFSET 3 +#define RTL8367D_IGMP_MLD_IP4_BYPASS_224_0_1_MASK 0x8 +#define RTL8367D_IGMP_MLD_IP4_BYPASS_224_0_0_OFFSET 2 +#define RTL8367D_IGMP_MLD_IP4_BYPASS_224_0_0_MASK 0x4 + +/* (16'h1d00)chip_67d_reg */ + +#define RTL8367D_REG_PCSXF_CFG 0x1d00 +#define RTL8367D_CFG_PCSXF_OFFSET 8 +#define RTL8367D_CFG_PCSXF_MASK 0xF00 +#define RTL8367D_CFG_RST_RXFIFO_OFFSET 3 +#define RTL8367D_CFG_RST_RXFIFO_MASK 0xF8 +#define RTL8367D_CFG_COL2RXDV_OFFSET 2 +#define RTL8367D_CFG_COL2RXDV_MASK 0x4 +#define RTL8367D_CFG_PHY_SDET_OFFSET 0 +#define RTL8367D_CFG_PHY_SDET_MASK 0x3 + +#define RTL8367D_REG_PHYID_CFG0 0x1d01 +#define RTL8367D_CFG_PHYAD_14C_OFFSET 10 +#define RTL8367D_CFG_PHYAD_14C_MASK 0x400 +#define RTL8367D_CFG_PHY_BRD_MODE_OFFSET 5 +#define RTL8367D_CFG_PHY_BRD_MODE_MASK 0x3E0 +#define RTL8367D_CFG_BRD_PHYAD_OFFSET 0 +#define RTL8367D_CFG_BRD_PHYAD_MASK 0x1F + +#define RTL8367D_REG_PHYID_CFG1 0x1d02 +#define RTL8367D_CFG_MSK_MDI_OFFSET 5 +#define RTL8367D_CFG_MSK_MDI_MASK 0x3E0 +#define RTL8367D_CFG_BASE_PHYAD_OFFSET 0 +#define RTL8367D_CFG_BASE_PHYAD_MASK 0x1F + +#define RTL8367D_REG_PHY_POLL_CFG0 0x1d03 +#define RTL8367D_CFG_HOTCMD_PRD_EN_OFFSET 15 +#define RTL8367D_CFG_HOTCMD_PRD_EN_MASK 0x8000 +#define RTL8367D_CFG_HOTCMD_EN_OFFSET 12 +#define RTL8367D_CFG_HOTCMD_EN_MASK 0x7000 +#define RTL8367D_CFG_POLL_PERIOD_OFFSET 8 +#define RTL8367D_CFG_POLL_PERIOD_MASK 0xF00 +#define RTL8367D_CFG_PERI_CMDS_RD_OFFSET 4 +#define RTL8367D_CFG_PERI_CMDS_RD_MASK 0xF0 +#define RTL8367D_CFG_PERI_CMDS_WR_OFFSET 0 +#define RTL8367D_CFG_PERI_CMDS_WR_MASK 0xF + +#define RTL8367D_REG_PHY_POLL_CFG1 0x1d04 + +#define RTL8367D_REG_PHY_POLL_CFG2 0x1d05 + +#define RTL8367D_REG_PHY_POLL_CFG3 0x1d06 + +#define RTL8367D_REG_PHY_POLL_CFG4 0x1d07 + +#define RTL8367D_REG_PHY_POLL_CFG5 0x1d08 + +#define RTL8367D_REG_PHY_POLL_CFG6 0x1d09 + +#define RTL8367D_REG_PHY_POLL_CFG7 0x1d0a + +#define RTL8367D_REG_PHY_POLL_CFG8 0x1d0b + +#define RTL8367D_REG_PHY_POLL_CFG9 0x1d0c + +#define RTL8367D_REG_PHY_POLL_CFG10 0x1d0d + +#define RTL8367D_REG_PHY_POLL_CFG11 0x1d0e + +#define RTL8367D_REG_PHY_POLL_CFG12 0x1d0f + +#define RTL8367D_REG_EFUSE_MISC 0x1d10 +#define RTL8367D_CFG_SA_SEL_OFFSET 5 +#define RTL8367D_CFG_SA_SEL_MASK 0x20 +#define RTL8367D_CFG_PHYAD00_OFFSET 0 +#define RTL8367D_CFG_PHYAD00_MASK 0x1F + +#define RTL8367D_REG_SDS_MISC 0x1d11 +#define RTL8367D_PA33PC_EN_S0_OFFSET 11 +#define RTL8367D_PA33PC_EN_S0_MASK 0x800 +#define RTL8367D_PA12PC_EN_S0_OFFSET 10 +#define RTL8367D_PA12PC_EN_S0_MASK 0x400 +#define RTL8367D_MAC6_SEL_SDS0_OFFSET 9 +#define RTL8367D_MAC6_SEL_SDS0_MASK 0x200 +#define RTL8367D_SDS_MISC_SDS_PWR_ISO_EN_1_OFFSET 8 +#define RTL8367D_SDS_MISC_SDS_PWR_ISO_EN_1_MASK 0x100 +#define RTL8367D_SDS_MISC_SDS_FRC_REG4_EN_1_OFFSET 7 +#define RTL8367D_SDS_MISC_SDS_FRC_REG4_EN_1_MASK 0x80 +#define RTL8367D_SDS_MISC_SDS_FRC_REG4_FIB100_1_OFFSET 6 +#define RTL8367D_SDS_MISC_SDS_FRC_REG4_FIB100_1_MASK 0x40 +#define RTL8367D_SDS_MISC_CFG_UNIDIR_TX_OFFSET 5 +#define RTL8367D_SDS_MISC_CFG_UNIDIR_TX_MASK 0x20 +#define RTL8367D_CFG_SDS_MODE_OFFSET 0 +#define RTL8367D_CFG_SDS_MODE_MASK 0x1F + +#define RTL8367D_REG_BCAM_SETTING 0x1d13 +#define RTL8367D_CFG_BCAM_MDS_OFFSET 3 +#define RTL8367D_CFG_BCAM_MDS_MASK 0x18 +#define RTL8367D_CFG_BCAM_RDS_OFFSET 0 +#define RTL8367D_CFG_BCAM_RDS_MASK 0x7 + +#define RTL8367D_REG_GPHY_ACS_MISC 0x1d14 +#define RTL8367D_CFG_SEL_GPHY_SMI_OFFSET 3 +#define RTL8367D_CFG_SEL_GPHY_SMI_MASK 0x8 +#define RTL8367D_CFG_BRD_PHYIDX_OFFSET 0 +#define RTL8367D_CFG_BRD_PHYIDX_MASK 0x7 + +#define RTL8367D_REG_GPHY_OCP_MSB_0 0x1d15 +#define RTL8367D_CFG_CPU_OCPADR_MSB_OFFSET 6 +#define RTL8367D_CFG_CPU_OCPADR_MSB_MASK 0xFC0 +#define RTL8367D_CFG_DW8051_OCPADR_MSB_OFFSET 0 +#define RTL8367D_CFG_DW8051_OCPADR_MSB_MASK 0x3F + +#define RTL8367D_REG_GPHY_OCP_MSB_1 0x1d16 +#define RTL8367D_CFG_PATCH_OCPADR_MSB_OFFSET 6 +#define RTL8367D_CFG_PATCH_OCPADR_MSB_MASK 0xFC0 +#define RTL8367D_CFG_PHYSTS_OCPADR_MSB_OFFSET 0 +#define RTL8367D_CFG_PHYSTS_OCPADR_MSB_MASK 0x3F + +#define RTL8367D_REG_GPHY_OCP_MSB_2 0x1d17 +#define RTL8367D_CFG_RRCP_OCPADR_MSB_OFFSET 6 +#define RTL8367D_CFG_RRCP_OCPADR_MSB_MASK 0xFC0 +#define RTL8367D_CFG_RTCT_OCPADR_MSB_OFFSET 0 +#define RTL8367D_CFG_RTCT_OCPADR_MSB_MASK 0x3F + +#define RTL8367D_REG_GPHY_OCP_MSB_3 0x1d18 +#define RTL8367D_GPHY_OCP_MSB_3_OFFSET 0 +#define RTL8367D_GPHY_OCP_MSB_3_MASK 0x3F + +#define RTL8367D_REG_GPIO_67C_I_X0 0x1d19 + +#define RTL8367D_REG_GPIO_67C_I_X1 0x1d1a + +#define RTL8367D_REG_GPIO_67C_I_X2 0x1d1b + +#define RTL8367D_REG_GPIO_67C_I_X3 0x1d1c +#define RTL8367D_GPIO_67C_I_X3_OFFSET 0 +#define RTL8367D_GPIO_67C_I_X3_MASK 0x3FFF + +#define RTL8367D_REG_GPIO_67C_O_X0 0x1d1d + +#define RTL8367D_REG_GPIO_67C_O_X1 0x1d1e + +#define RTL8367D_REG_GPIO_67C_O_X2 0x1d1f + +#define RTL8367D_REG_GPIO_67C_O_X3 0x1d20 +#define RTL8367D_GPIO_67C_O_X3_OFFSET 0 +#define RTL8367D_GPIO_67C_O_X3_MASK 0x3FFF + +#define RTL8367D_REG_GPIO_67C_OE_X0 0x1d21 + +#define RTL8367D_REG_GPIO_67C_OE_X1 0x1d22 + +#define RTL8367D_REG_GPIO_67C_OE_X2 0x1d23 + +#define RTL8367D_REG_GPIO_67C_OE_X3 0x1d24 +#define RTL8367D_GPIO_67C_OE_X3_OFFSET 0 +#define RTL8367D_GPIO_67C_OE_X3_MASK 0x3FFF + +#define RTL8367D_REG_GPIO_MODE_67C_X0 0x1d25 + +#define RTL8367D_REG_GPIO_MODE_67C_X1 0x1d26 + +#define RTL8367D_REG_GPIO_MODE_67C_X2 0x1d27 + +#define RTL8367D_REG_GPIO_MODE_67C_X3 0x1d28 +#define RTL8367D_GPIO_MODE_67C_X3_OFFSET 0 +#define RTL8367D_GPIO_MODE_67C_X3_MASK 0x3FFF + +#define RTL8367D_REG_WGPHY_MISC_0 0x1d29 +#define RTL8367D_CFG_INIPHY_PWRUP_OFFSET 5 +#define RTL8367D_CFG_INIPHY_PWRUP_MASK 0x3E0 +#define RTL8367D_CFG_INIPHY_DISGIGA_OFFSET 0 +#define RTL8367D_CFG_INIPHY_DISGIGA_MASK 0x1F + +#define RTL8367D_REG_WGPHY_MISC_1 0x1d2a +#define RTL8367D_WGPHY_MISC_1_OFFSET 0 +#define RTL8367D_WGPHY_MISC_1_MASK 0xFF + +#define RTL8367D_REG_WGPHY_MISC_2 0x1d2b +#define RTL8367D_WGPHY_MISC_2_OFFSET 0 +#define RTL8367D_WGPHY_MISC_2_MASK 0x3FF + +#define RTL8367D_REG_CFG_AFBK_GPHY_0 0x1d2c +#define RTL8367D_CFG_AFBK_GPHY_0_OFFSET 0 +#define RTL8367D_CFG_AFBK_GPHY_0_MASK 0x1F + +#define RTL8367D_REG_CFG_AFBK_GPHY_1 0x1d2d +#define RTL8367D_CFG_AFBK_GPHY_1_OFFSET 0 +#define RTL8367D_CFG_AFBK_GPHY_1_MASK 0xFFF + +#define RTL8367D_REG_EF_SLV_CTRL_0 0x1d2e +#define RTL8367D_EF_SLV_BUSY_OFFSET 11 +#define RTL8367D_EF_SLV_BUSY_MASK 0x800 +#define RTL8367D_EF_SLV_ACK_OFFSET 10 +#define RTL8367D_EF_SLV_ACK_MASK 0x400 +#define RTL8367D_EF_SLV_A_OFFSET 2 +#define RTL8367D_EF_SLV_A_MASK 0x3FC +#define RTL8367D_EF_SLV_WE_OFFSET 1 +#define RTL8367D_EF_SLV_WE_MASK 0x2 +#define RTL8367D_EF_SLV_CE_OFFSET 0 +#define RTL8367D_EF_SLV_CE_MASK 0x1 + +#define RTL8367D_REG_EF_SLV_CTRL_1 0x1d2f + +#define RTL8367D_REG_EF_SLV_CTRL_2 0x1d30 + +#define RTL8367D_REG_EFUSE_MISC_1 0x1d31 + +#define RTL8367D_REG_IO_MISC_FUNC 0x1d32 +#define RTL8367D_TST_MODE_OFFSET 3 +#define RTL8367D_TST_MODE_MASK 0x8 +#define RTL8367D_UART_EN_OFFSET 2 +#define RTL8367D_UART_EN_MASK 0x4 +#define RTL8367D_INT_EN_OFFSET 1 +#define RTL8367D_INT_EN_MASK 0x2 +#define RTL8367D_BUZ_EN_OFFSET 0 +#define RTL8367D_BUZ_EN_MASK 0x1 + +#define RTL8367D_REG_HTRAM_DVS 0x1d33 +#define RTL8367D_HTRAM_DVS_OFFSET 0 +#define RTL8367D_HTRAM_DVS_MASK 0x1 + +#define RTL8367D_REG_EF_SLV_CTRL_3 0x1d34 +#define RTL8367D_EF_SLV_CTRL_3_OFFSET 0 +#define RTL8367D_EF_SLV_CTRL_3_MASK 0x1 + +#define RTL8367D_REG_INBAND_EN14C 0x1d35 +#define RTL8367D_INBAND_EN14C_OFFSET 0 +#define RTL8367D_INBAND_EN14C_MASK 0x1 + +#define RTL8367D_REG_CFG_SWR_L 0x1d36 +#define RTL8367D_ANARG_RDY_SWR_L_OFFSET 14 +#define RTL8367D_ANARG_RDY_SWR_L_MASK 0x4000 +#define RTL8367D_ANARG_VALID_SWR_L_OFFSET 13 +#define RTL8367D_ANARG_VALID_SWR_L_MASK 0x2000 +#define RTL8367D_SAW_SWR_L_OFFSET 9 +#define RTL8367D_SAW_SWR_L_MASK 0x1E00 +#define RTL8367D_SAW_VALID_SWR_L_OFFSET 8 +#define RTL8367D_SAW_VALID_SWR_L_MASK 0x100 +#define RTL8367D_UPS_DBGO_L_OFFSET 0 +#define RTL8367D_UPS_DBGO_L_MASK 0xFF + +#define RTL8367D_REG_BTCAM_CTRL 0x1d37 +#define RTL8367D_BTCAM_CTRL_TCAM_RDS_OFFSET 2 +#define RTL8367D_BTCAM_CTRL_TCAM_RDS_MASK 0x1C +#define RTL8367D_BTCAM_CTRL_TCAM_MDS_OFFSET 0 +#define RTL8367D_BTCAM_CTRL_TCAM_MDS_MASK 0x3 + +#define RTL8367D_REG_PBRAM_BISR_CTRL 0x1d38 +#define RTL8367D_HAS_HLDRMP_MD_OFFSET 9 +#define RTL8367D_HAS_HLDRMP_MD_MASK 0x200 +#define RTL8367D_PB_HLDRMP_MD_OFFSET 8 +#define RTL8367D_PB_HLDRMP_MD_MASK 0x100 +#define RTL8367D_HAS_BISR_BIRSTN_OFFSET 7 +#define RTL8367D_HAS_BISR_BIRSTN_MASK 0x80 +#define RTL8367D_SEC_RUN_HSA_OFFSET 6 +#define RTL8367D_SEC_RUN_HSA_MASK 0x40 +#define RTL8367D_HAS_HLDRMP_VAL_OFFSET 5 +#define RTL8367D_HAS_HLDRMP_VAL_MASK 0x20 +#define RTL8367D_HAS_BISR_PWRSTN_OFFSET 4 +#define RTL8367D_HAS_BISR_PWRSTN_MASK 0x10 +#define RTL8367D_SEC_RUN_PB_OFFSET 3 +#define RTL8367D_SEC_RUN_PB_MASK 0x8 +#define RTL8367D_PB_HLDRMP_VAL_OFFSET 2 +#define RTL8367D_PB_HLDRMP_VAL_MASK 0x4 +#define RTL8367D_PB_BISR_BIRSTN_OFFSET 1 +#define RTL8367D_PB_BISR_BIRSTN_MASK 0x2 +#define RTL8367D_PB_BISR_PWRSTN_OFFSET 0 +#define RTL8367D_PB_BISR_PWRSTN_MASK 0x1 + +#define RTL8367D_REG_CVLANRAM_BISR_CTRL 0x1d39 +#define RTL8367D_SEC_RUN_CVLAN_OFFSET 4 +#define RTL8367D_SEC_RUN_CVLAN_MASK 0x10 +#define RTL8367D_CVALN_HLDRMP_MD_OFFSET 3 +#define RTL8367D_CVALN_HLDRMP_MD_MASK 0x8 +#define RTL8367D_CVALN_HLDRMP_VAL_OFFSET 2 +#define RTL8367D_CVALN_HLDRMP_VAL_MASK 0x4 +#define RTL8367D_CVLAN_BISR_BIRSTN_OFFSET 1 +#define RTL8367D_CVLAN_BISR_BIRSTN_MASK 0x2 +#define RTL8367D_CVLAN_BISR_PWRSTN_OFFSET 0 +#define RTL8367D_CVLAN_BISR_PWRSTN_MASK 0x1 + +#define RTL8367D_REG_CFG_1588_TIMER_EN_GPI 0x1d3a +#define RTL8367D_CFG_1588_TIMER_EN_GPI_OFFSET 0 +#define RTL8367D_CFG_1588_TIMER_EN_GPI_MASK 0x1 + +#define RTL8367D_REG_MDIO_PRMB_SUPP 0x1d3b +#define RTL8367D_SMT_EXT1CK_EN_OFFSET 15 +#define RTL8367D_SMT_EXT1CK_EN_MASK 0x8000 +#define RTL8367D_FIB_HIPRI_OFFSET 14 +#define RTL8367D_FIB_HIPRI_MASK 0x4000 +#define RTL8367D_SMT_EN_OFFSET 13 +#define RTL8367D_SMT_EN_MASK 0x2000 +#define RTL8367D_P4_FB_CPL_OFFSET 12 +#define RTL8367D_P4_FB_CPL_MASK 0x1000 +#define RTL8367D_P3_FB_CPL_OFFSET 11 +#define RTL8367D_P3_FB_CPL_MASK 0x800 +#define RTL8367D_P2_FB_CPL_OFFSET 10 +#define RTL8367D_P2_FB_CPL_MASK 0x400 +#define RTL8367D_P1_FB_CPL_OFFSET 9 +#define RTL8367D_P1_FB_CPL_MASK 0x200 +#define RTL8367D_P0_FB_CPL_OFFSET 8 +#define RTL8367D_P0_FB_CPL_MASK 0x100 +#define RTL8367D_DBG_PKG_8367N_OFFSET 7 +#define RTL8367D_DBG_PKG_8367N_MASK 0x80 +#define RTL8367D_DBG_PKG_8367VB_OFFSET 6 +#define RTL8367D_DBG_PKG_8367VB_MASK 0x40 +#define RTL8367D_CFG_DEBUG_EN_OFFSET 5 +#define RTL8367D_CFG_DEBUG_EN_MASK 0x20 +#define RTL8367D_CFG_TMR_ACK_OFFSET 1 +#define RTL8367D_CFG_TMR_ACK_MASK 0x1E +#define RTL8367D_CFG_PRMB_SUPP_OFFSET 0 +#define RTL8367D_CFG_PRMB_SUPP_MASK 0x1 + +#define RTL8367D_REG_BOND4READ 0x1d3c +#define RTL8367D_SPDUP_OFFSET 13 +#define RTL8367D_SPDUP_MASK 0x2000 +#define RTL8367D_DBGO_SEL_EN_PAD_OFFSET 12 +#define RTL8367D_DBGO_SEL_EN_PAD_MASK 0x1000 +#define RTL8367D_BOND_DEGLITCH_ENB_OFFSET 11 +#define RTL8367D_BOND_DEGLITCH_ENB_MASK 0x800 +#define RTL8367D_BOND_RSV1_OFFSET 10 +#define RTL8367D_BOND_RSV1_MASK 0x400 +#define RTL8367D_BOND_SYSCLK_OFFSET 7 +#define RTL8367D_BOND_SYSCLK_MASK 0x180 +#define RTL8367D_BOND_DIS_TABLE_INIT_OFFSET 4 +#define RTL8367D_BOND_DIS_TABLE_INIT_MASK 0x10 +#define RTL8367D_BOND_BYP_AFE_PLL_OFFSET 3 +#define RTL8367D_BOND_BYP_AFE_PLL_MASK 0x8 +#define RTL8367D_BOND_BYP_AFE_POR_OFFSET 2 +#define RTL8367D_BOND_BYP_AFE_POR_MASK 0x4 +#define RTL8367D_BOND_EF_EN_OFFSET 0 +#define RTL8367D_BOND_EF_EN_MASK 0x1 + +#define RTL8367D_REG_REG_TO_ECO0 0x1d3d + +#define RTL8367D_REG_REG_TO_ECO1 0x1d3e + +#define RTL8367D_REG_REG_TO_ECO2 0x1d3f + +#define RTL8367D_REG_REG_TO_ECO4 0x1d41 +#define RTL8367D_CFG_SLED_CLKDUTY_OFFSET 15 +#define RTL8367D_CFG_SLED_CLKDUTY_MASK 0x8000 +#define RTL8367D_CFG_ECO_SEL_SPD_OFFSET 12 +#define RTL8367D_CFG_ECO_SEL_SPD_MASK 0x1000 +#define RTL8367D_CFG_DIS_LNKDN_FRC_OFFSET 9 +#define RTL8367D_CFG_DIS_LNKDN_FRC_MASK 0x200 +#define RTL8367D_MAC6_FIB2_OFFSET 7 +#define RTL8367D_MAC6_FIB2_MASK 0x80 +#define RTL8367D_MAC6_FIB_OFFSET 5 +#define RTL8367D_MAC6_FIB_MASK 0x20 +#define RTL8367D_STRAP_EEE_EN_OFFSET 0 +#define RTL8367D_STRAP_EEE_EN_MASK 0x1F + +#define RTL8367D_REG_PHYSTS_CTRL0 0x1d42 +#define RTL8367D_SPD_2P5G_LNKUP_DLY_OFFSET 13 +#define RTL8367D_SPD_2P5G_LNKUP_DLY_MASK 0x6000 +#define RTL8367D_SPD_ABLITY_EN_MAC_OFFSET 7 +#define RTL8367D_SPD_ABLITY_EN_MAC_MASK 0x1F80 +#define RTL8367D_BYPASS_SPD_ABLITY_EN_MAC_OFFSET 6 +#define RTL8367D_BYPASS_SPD_ABLITY_EN_MAC_MASK 0x40 +#define RTL8367D_LNKUP_DLY_EN_OFFSET 4 +#define RTL8367D_LNKUP_DLY_EN_MASK 0x10 +#define RTL8367D_GE_100M_LNKUP_DLY_OFFSET 2 +#define RTL8367D_GE_100M_LNKUP_DLY_MASK 0xC +#define RTL8367D_PHYSTS_10M_LNKUP_DLY_OFFSET 0 +#define RTL8367D_PHYSTS_10M_LNKUP_DLY_MASK 0x3 + +#define RTL8367D_REG_PHYSTS_CTRL1 0x1d43 +#define RTL8367D_PHYSTS_CTRL1_OFFSET 0 +#define RTL8367D_PHYSTS_CTRL1_MASK 0xFF + +#define RTL8367D_REG_SSC_CTRL0_0 0x1d44 +#define RTL8367D_SSC_CTRL0_0_SSC_TYPE_OFFSET 13 +#define RTL8367D_SSC_CTRL0_0_SSC_TYPE_MASK 0x2000 +#define RTL8367D_SSC_CTRL0_0_PHASE_LIM_SEL_OFFSET 5 +#define RTL8367D_SSC_CTRL0_0_PHASE_LIM_SEL_MASK 0x1FE0 +#define RTL8367D_SSC_CTRL0_0_PHASE_LIM_EN_OFFSET 4 +#define RTL8367D_SSC_CTRL0_0_PHASE_LIM_EN_MASK 0x10 +#define RTL8367D_SSC_CTRL0_0_DLL_MODE_OFFSET 2 +#define RTL8367D_SSC_CTRL0_0_DLL_MODE_MASK 0xC +#define RTL8367D_SSC_CTRL0_0_SSC_EN_OFFSET 1 +#define RTL8367D_SSC_CTRL0_0_SSC_EN_MASK 0x2 +#define RTL8367D_SSC_CTRL0_0_SSC_MODE_OFFSET 0 +#define RTL8367D_SSC_CTRL0_0_SSC_MODE_MASK 0x1 + +#define RTL8367D_REG_SSC_RDM_SEED 0x1d45 + +#define RTL8367D_REG_SSC_PN_POLY_SEL 0x1d46 + +#define RTL8367D_REG_SSC_CTRL0_3 0x1d47 +#define RTL8367D_SSC_CTRL0_3_PHSFT_CNT_OFFSET 8 +#define RTL8367D_SSC_CTRL0_3_PHSFT_CNT_MASK 0x7F00 +#define RTL8367D_SSC_CTRL0_3_PHSFT_A_OFFSET 7 +#define RTL8367D_SSC_CTRL0_3_PHSFT_A_MASK 0x80 +#define RTL8367D_SSC_CTRL0_3_PHSFT_B_OFFSET 6 +#define RTL8367D_SSC_CTRL0_3_PHSFT_B_MASK 0x40 +#define RTL8367D_SSC_CTRL0_3_PHSFT_UPDN_OFFSET 5 +#define RTL8367D_SSC_CTRL0_3_PHSFT_UPDN_MASK 0x20 +#define RTL8367D_SSC_CTRL0_3_PHSFT_PRD_OFFSET 4 +#define RTL8367D_SSC_CTRL0_3_PHSFT_PRD_MASK 0x10 +#define RTL8367D_SSC_CTRL0_3_PN_POLY_DEG_OFFSET 0 +#define RTL8367D_SSC_CTRL0_3_PN_POLY_DEG_MASK 0xF + +#define RTL8367D_REG_SSC_CTRL0_4 0x1d48 +#define RTL8367D_SSC_CTRL0_4_SSC_UP1DN0_OFFSET 15 +#define RTL8367D_SSC_CTRL0_4_SSC_UP1DN0_MASK 0x8000 +#define RTL8367D_SSC_CTRL0_4_SSC_PERIOD_OFFSET 8 +#define RTL8367D_SSC_CTRL0_4_SSC_PERIOD_MASK 0x7F00 +#define RTL8367D_SSC_CTRL0_4_SSC_OFFSET_OFFSET 0 +#define RTL8367D_SSC_CTRL0_4_SSC_OFFSET_MASK 0xFF + +#define RTL8367D_REG_SSC_CTRL0_5 0x1d49 +#define RTL8367D_SSC_CTRL0_5_PH_OFS_TOG_OFFSET 15 +#define RTL8367D_SSC_CTRL0_5_PH_OFS_TOG_MASK 0x8000 +#define RTL8367D_SSC_CTRL0_5_PH_OFS_OFFSET 10 +#define RTL8367D_SSC_CTRL0_5_PH_OFS_MASK 0x7C00 +#define RTL8367D_SSC_CTRL0_5_SSC_STEP_OFFSET 4 +#define RTL8367D_SSC_CTRL0_5_SSC_STEP_MASK 0x3F0 +#define RTL8367D_SSC_CTRL0_5_SSC_TEST_MODE_OFFSET 2 +#define RTL8367D_SSC_CTRL0_5_SSC_TEST_MODE_MASK 0xC +#define RTL8367D_SSC_CTRL0_5_SSC_PH_CFG_OFFSET 0 +#define RTL8367D_SSC_CTRL0_5_SSC_PH_CFG_MASK 0x3 + +#define RTL8367D_REG_SSC_STS0 0x1d4a +#define RTL8367D_SSC_STS0_OFS_BUSY_OFFSET 13 +#define RTL8367D_SSC_STS0_OFS_BUSY_MASK 0x2000 +#define RTL8367D_SSC_STS0_OFS_TOTAL_R_OFFSET 8 +#define RTL8367D_SSC_STS0_OFS_TOTAL_R_MASK 0x1F00 +#define RTL8367D_SSC_STS0_CNT_GRY0_OFFSET 4 +#define RTL8367D_SSC_STS0_CNT_GRY0_MASK 0xF0 +#define RTL8367D_SSC_STS0_OFS_GRY0_OFFSET 0 +#define RTL8367D_SSC_STS0_OFS_GRY0_MASK 0xF + +#define RTL8367D_REG_SSC_CTRL1_0 0x1d4b +#define RTL8367D_SSC_CTRL1_0_SSC_TYPE_OFFSET 13 +#define RTL8367D_SSC_CTRL1_0_SSC_TYPE_MASK 0x2000 +#define RTL8367D_SSC_CTRL1_0_PHASE_LIM_SEL_OFFSET 5 +#define RTL8367D_SSC_CTRL1_0_PHASE_LIM_SEL_MASK 0x1FE0 +#define RTL8367D_SSC_CTRL1_0_PHASE_LIM_EN_OFFSET 4 +#define RTL8367D_SSC_CTRL1_0_PHASE_LIM_EN_MASK 0x10 +#define RTL8367D_SSC_CTRL1_0_DLL_MODE_OFFSET 2 +#define RTL8367D_SSC_CTRL1_0_DLL_MODE_MASK 0xC +#define RTL8367D_SSC_CTRL1_0_SSC_EN_OFFSET 1 +#define RTL8367D_SSC_CTRL1_0_SSC_EN_MASK 0x2 +#define RTL8367D_SSC_CTRL1_0_SSC_MODE_OFFSET 0 +#define RTL8367D_SSC_CTRL1_0_SSC_MODE_MASK 0x1 + +#define RTL8367D_REG_SSC_RDM_SEED1 0x1d4c + +#define RTL8367D_REG_SSC_PN_POLY_SEL1 0x1d4d + +#define RTL8367D_REG_SSC_CTRL1_3 0x1d4e +#define RTL8367D_SSC_CTRL1_3_PHSFT_CNT_OFFSET 8 +#define RTL8367D_SSC_CTRL1_3_PHSFT_CNT_MASK 0x7F00 +#define RTL8367D_SSC_CTRL1_3_PHSFT_A_OFFSET 7 +#define RTL8367D_SSC_CTRL1_3_PHSFT_A_MASK 0x80 +#define RTL8367D_SSC_CTRL1_3_PHSFT_B_OFFSET 6 +#define RTL8367D_SSC_CTRL1_3_PHSFT_B_MASK 0x40 +#define RTL8367D_SSC_CTRL1_3_PHSFT_UPDN_OFFSET 5 +#define RTL8367D_SSC_CTRL1_3_PHSFT_UPDN_MASK 0x20 +#define RTL8367D_SSC_CTRL1_3_PHSFT_PRD_OFFSET 4 +#define RTL8367D_SSC_CTRL1_3_PHSFT_PRD_MASK 0x10 +#define RTL8367D_SSC_CTRL1_3_PN_POLY_DEG_OFFSET 0 +#define RTL8367D_SSC_CTRL1_3_PN_POLY_DEG_MASK 0xF + +#define RTL8367D_REG_SSC_CTRL1_4 0x1d4f +#define RTL8367D_SSC_CTRL1_4_SSC_UP1DN0_OFFSET 15 +#define RTL8367D_SSC_CTRL1_4_SSC_UP1DN0_MASK 0x8000 +#define RTL8367D_SSC_CTRL1_4_SSC_PERIOD_OFFSET 8 +#define RTL8367D_SSC_CTRL1_4_SSC_PERIOD_MASK 0x7F00 +#define RTL8367D_SSC_CTRL1_4_SSC_OFFSET_OFFSET 0 +#define RTL8367D_SSC_CTRL1_4_SSC_OFFSET_MASK 0xFF + +#define RTL8367D_REG_SSC_CTRL1_5 0x1d50 +#define RTL8367D_SSC_CTRL1_5_PH_OFS_TOG_OFFSET 15 +#define RTL8367D_SSC_CTRL1_5_PH_OFS_TOG_MASK 0x8000 +#define RTL8367D_SSC_CTRL1_5_PH_OFS_OFFSET 10 +#define RTL8367D_SSC_CTRL1_5_PH_OFS_MASK 0x7C00 +#define RTL8367D_SSC_CTRL1_5_SSC_STEP_OFFSET 4 +#define RTL8367D_SSC_CTRL1_5_SSC_STEP_MASK 0x3F0 +#define RTL8367D_SSC_CTRL1_5_SSC_TEST_MODE_OFFSET 2 +#define RTL8367D_SSC_CTRL1_5_SSC_TEST_MODE_MASK 0xC +#define RTL8367D_SSC_CTRL1_5_SSC_PH_CFG_OFFSET 0 +#define RTL8367D_SSC_CTRL1_5_SSC_PH_CFG_MASK 0x3 + +#define RTL8367D_REG_SSC_STS1 0x1d51 +#define RTL8367D_SSC_STS1_OFS_BUSY_OFFSET 13 +#define RTL8367D_SSC_STS1_OFS_BUSY_MASK 0x2000 +#define RTL8367D_SSC_STS1_OFS_TOTAL_R_OFFSET 8 +#define RTL8367D_SSC_STS1_OFS_TOTAL_R_MASK 0x1F00 +#define RTL8367D_SSC_STS1_CNT_GRY0_OFFSET 4 +#define RTL8367D_SSC_STS1_CNT_GRY0_MASK 0xF0 +#define RTL8367D_SSC_STS1_OFS_GRY0_OFFSET 0 +#define RTL8367D_SSC_STS1_OFS_GRY0_MASK 0xF + +#define RTL8367D_REG_SSC_CTRL2_0 0x1d52 +#define RTL8367D_SSC_CTRL2_0_SSC_TYPE_OFFSET 13 +#define RTL8367D_SSC_CTRL2_0_SSC_TYPE_MASK 0x2000 +#define RTL8367D_SSC_CTRL2_0_PHASE_LIM_SEL_OFFSET 5 +#define RTL8367D_SSC_CTRL2_0_PHASE_LIM_SEL_MASK 0x1FE0 +#define RTL8367D_SSC_CTRL2_0_PHASE_LIM_EN_OFFSET 4 +#define RTL8367D_SSC_CTRL2_0_PHASE_LIM_EN_MASK 0x10 +#define RTL8367D_SSC_CTRL2_0_DLL_MODE_OFFSET 2 +#define RTL8367D_SSC_CTRL2_0_DLL_MODE_MASK 0xC +#define RTL8367D_SSC_CTRL2_0_SSC_EN_OFFSET 1 +#define RTL8367D_SSC_CTRL2_0_SSC_EN_MASK 0x2 +#define RTL8367D_SSC_CTRL2_0_SSC_MODE_OFFSET 0 +#define RTL8367D_SSC_CTRL2_0_SSC_MODE_MASK 0x1 + +#define RTL8367D_REG_SSC_RDM_SEED2 0x1d53 + +#define RTL8367D_REG_SSC_PN_POLY_SEL2 0x1d54 + +#define RTL8367D_REG_SSC_CTRL2_3 0x1d55 +#define RTL8367D_SSC_CTRL2_3_PHSFT_CNT_OFFSET 8 +#define RTL8367D_SSC_CTRL2_3_PHSFT_CNT_MASK 0x7F00 +#define RTL8367D_SSC_CTRL2_3_PHSFT_A_OFFSET 7 +#define RTL8367D_SSC_CTRL2_3_PHSFT_A_MASK 0x80 +#define RTL8367D_SSC_CTRL2_3_PHSFT_B_OFFSET 6 +#define RTL8367D_SSC_CTRL2_3_PHSFT_B_MASK 0x40 +#define RTL8367D_SSC_CTRL2_3_PHSFT_UPDN_OFFSET 5 +#define RTL8367D_SSC_CTRL2_3_PHSFT_UPDN_MASK 0x20 +#define RTL8367D_SSC_CTRL2_3_PHSFT_PRD_OFFSET 4 +#define RTL8367D_SSC_CTRL2_3_PHSFT_PRD_MASK 0x10 +#define RTL8367D_SSC_CTRL2_3_PN_POLY_DEG_OFFSET 0 +#define RTL8367D_SSC_CTRL2_3_PN_POLY_DEG_MASK 0xF + +#define RTL8367D_REG_SSC_CTRL2_4 0x1d56 +#define RTL8367D_SSC_CTRL2_4_SSC_UP1DN0_OFFSET 15 +#define RTL8367D_SSC_CTRL2_4_SSC_UP1DN0_MASK 0x8000 +#define RTL8367D_SSC_CTRL2_4_SSC_PERIOD_OFFSET 8 +#define RTL8367D_SSC_CTRL2_4_SSC_PERIOD_MASK 0x7F00 +#define RTL8367D_SSC_CTRL2_4_SSC_OFFSET_OFFSET 0 +#define RTL8367D_SSC_CTRL2_4_SSC_OFFSET_MASK 0xFF + +#define RTL8367D_REG_SSC_CTRL2_5 0x1d57 +#define RTL8367D_SSC_CTRL2_5_PH_OFS_TOG_OFFSET 15 +#define RTL8367D_SSC_CTRL2_5_PH_OFS_TOG_MASK 0x8000 +#define RTL8367D_SSC_CTRL2_5_PH_OFS_OFFSET 10 +#define RTL8367D_SSC_CTRL2_5_PH_OFS_MASK 0x7C00 +#define RTL8367D_SSC_CTRL2_5_SSC_STEP_OFFSET 4 +#define RTL8367D_SSC_CTRL2_5_SSC_STEP_MASK 0x3F0 +#define RTL8367D_SSC_CTRL2_5_SSC_TEST_MODE_OFFSET 2 +#define RTL8367D_SSC_CTRL2_5_SSC_TEST_MODE_MASK 0xC +#define RTL8367D_SSC_CTRL2_5_SSC_PH_CFG_OFFSET 0 +#define RTL8367D_SSC_CTRL2_5_SSC_PH_CFG_MASK 0x3 + +#define RTL8367D_REG_SSC_STS2 0x1d58 +#define RTL8367D_SSC_STS2_OFS_BUSY_OFFSET 13 +#define RTL8367D_SSC_STS2_OFS_BUSY_MASK 0x2000 +#define RTL8367D_SSC_STS2_OFS_TOTAL_R_OFFSET 8 +#define RTL8367D_SSC_STS2_OFS_TOTAL_R_MASK 0x1F00 +#define RTL8367D_SSC_STS2_CNT_GRY0_OFFSET 4 +#define RTL8367D_SSC_STS2_CNT_GRY0_MASK 0xF0 +#define RTL8367D_SSC_STS2_OFS_GRY0_OFFSET 0 +#define RTL8367D_SSC_STS2_OFS_GRY0_MASK 0xF + +#define RTL8367D_REG_SSC_CTRL3_0 0x1d59 +#define RTL8367D_SSC_CTRL3_0_SSC_TYPE_OFFSET 13 +#define RTL8367D_SSC_CTRL3_0_SSC_TYPE_MASK 0x2000 +#define RTL8367D_SSC_CTRL3_0_PHASE_LIM_SEL_OFFSET 5 +#define RTL8367D_SSC_CTRL3_0_PHASE_LIM_SEL_MASK 0x1FE0 +#define RTL8367D_SSC_CTRL3_0_PHASE_LIM_EN_OFFSET 4 +#define RTL8367D_SSC_CTRL3_0_PHASE_LIM_EN_MASK 0x10 +#define RTL8367D_SSC_CTRL3_0_DLL_MODE_OFFSET 2 +#define RTL8367D_SSC_CTRL3_0_DLL_MODE_MASK 0xC +#define RTL8367D_SSC_CTRL3_0_SSC_EN_OFFSET 1 +#define RTL8367D_SSC_CTRL3_0_SSC_EN_MASK 0x2 +#define RTL8367D_SSC_CTRL3_0_SSC_MODE_OFFSET 0 +#define RTL8367D_SSC_CTRL3_0_SSC_MODE_MASK 0x1 + +#define RTL8367D_REG_SSC_RDM_SEED3 0x1d5a + +#define RTL8367D_REG_SSC_PN_POLY_SEL3 0x1d5b + +#define RTL8367D_REG_SSC_CTRL3_3 0x1d5c +#define RTL8367D_SSC_CTRL3_3_PHSFT_CNT_OFFSET 8 +#define RTL8367D_SSC_CTRL3_3_PHSFT_CNT_MASK 0x7F00 +#define RTL8367D_SSC_CTRL3_3_PHSFT_A_OFFSET 7 +#define RTL8367D_SSC_CTRL3_3_PHSFT_A_MASK 0x80 +#define RTL8367D_SSC_CTRL3_3_PHSFT_B_OFFSET 6 +#define RTL8367D_SSC_CTRL3_3_PHSFT_B_MASK 0x40 +#define RTL8367D_SSC_CTRL3_3_PHSFT_UPDN_OFFSET 5 +#define RTL8367D_SSC_CTRL3_3_PHSFT_UPDN_MASK 0x20 +#define RTL8367D_SSC_CTRL3_3_PHSFT_PRD_OFFSET 4 +#define RTL8367D_SSC_CTRL3_3_PHSFT_PRD_MASK 0x10 +#define RTL8367D_SSC_CTRL3_3_PN_POLY_DEG_OFFSET 0 +#define RTL8367D_SSC_CTRL3_3_PN_POLY_DEG_MASK 0xF + +#define RTL8367D_REG_SSC_CTRL3_4 0x1d5d +#define RTL8367D_SSC_CTRL3_4_SSC_UP1DN0_OFFSET 15 +#define RTL8367D_SSC_CTRL3_4_SSC_UP1DN0_MASK 0x8000 +#define RTL8367D_SSC_CTRL3_4_SSC_PERIOD_OFFSET 8 +#define RTL8367D_SSC_CTRL3_4_SSC_PERIOD_MASK 0x7F00 +#define RTL8367D_SSC_CTRL3_4_SSC_OFFSET_OFFSET 0 +#define RTL8367D_SSC_CTRL3_4_SSC_OFFSET_MASK 0xFF + +#define RTL8367D_REG_SSC_CTRL3_5 0x1d5e +#define RTL8367D_SSC_CTRL3_5_PH_OFS_TOG_OFFSET 15 +#define RTL8367D_SSC_CTRL3_5_PH_OFS_TOG_MASK 0x8000 +#define RTL8367D_SSC_CTRL3_5_PH_OFS_OFFSET 10 +#define RTL8367D_SSC_CTRL3_5_PH_OFS_MASK 0x7C00 +#define RTL8367D_SSC_CTRL3_5_SSC_STEP_OFFSET 4 +#define RTL8367D_SSC_CTRL3_5_SSC_STEP_MASK 0x3F0 +#define RTL8367D_SSC_CTRL3_5_SSC_TEST_MODE_OFFSET 2 +#define RTL8367D_SSC_CTRL3_5_SSC_TEST_MODE_MASK 0xC +#define RTL8367D_SSC_CTRL3_5_SSC_PH_CFG_OFFSET 0 +#define RTL8367D_SSC_CTRL3_5_SSC_PH_CFG_MASK 0x3 + +#define RTL8367D_REG_SSC_STS3 0x1d5f +#define RTL8367D_SSC_STS3_OFS_BUSY_OFFSET 13 +#define RTL8367D_SSC_STS3_OFS_BUSY_MASK 0x2000 +#define RTL8367D_SSC_STS3_OFS_TOTAL_R_OFFSET 8 +#define RTL8367D_SSC_STS3_OFS_TOTAL_R_MASK 0x1F00 +#define RTL8367D_SSC_STS3_CNT_GRY0_OFFSET 4 +#define RTL8367D_SSC_STS3_CNT_GRY0_MASK 0xF0 +#define RTL8367D_SSC_STS3_OFS_GRY0_OFFSET 0 +#define RTL8367D_SSC_STS3_OFS_GRY0_MASK 0xF + +#define RTL8367D_REG_PHY_POLL_CFG13 0x1d60 + +#define RTL8367D_REG_PHY_POLL_CFG14 0x1d61 + +#define RTL8367D_REG_FRC_SYS_CLK 0x1d62 +#define RTL8367D_SYSCLK_FRC_MD_OFFSET 2 +#define RTL8367D_SYSCLK_FRC_MD_MASK 0x4 +#define RTL8367D_SYSCLK_FRC_VAL_OFFSET 0 +#define RTL8367D_SYSCLK_FRC_VAL_MASK 0x3 + +#define RTL8367D_REG_AFE_SSC_CTRL 0x1d63 +#define RTL8367D_PH_RSTB_TXD1_OFFSET 9 +#define RTL8367D_PH_RSTB_TXD1_MASK 0x200 +#define RTL8367D_PH_RSTB_TXC1_OFFSET 8 +#define RTL8367D_PH_RSTB_TXC1_MASK 0x100 +#define RTL8367D_PH_RSTB_TXD0_OFFSET 7 +#define RTL8367D_PH_RSTB_TXD0_MASK 0x80 +#define RTL8367D_PH_RSTB_TXC0_OFFSET 6 +#define RTL8367D_PH_RSTB_TXC0_MASK 0x40 +#define RTL8367D_PH_RSTBSYS_OFFSET 5 +#define RTL8367D_PH_RSTBSYS_MASK 0x20 +#define RTL8367D_PH_RSTB8051_OFFSET 4 +#define RTL8367D_PH_RSTB8051_MASK 0x10 +#define RTL8367D_OREG_SSC_OFFSET 0 +#define RTL8367D_OREG_SSC_MASK 0xF + +#define RTL8367D_REG_BUFF_RST_CTRL0 0x1d64 +#define RTL8367D_BUFFRST_TXESD_EN_OFFSET 13 +#define RTL8367D_BUFFRST_TXESD_EN_MASK 0x2000 +#define RTL8367D_BUFF_RST_TIME_LONG_OFFSET 8 +#define RTL8367D_BUFF_RST_TIME_LONG_MASK 0x1F00 +#define RTL8367D_BUFF_RST_TIME_SHORT_OFFSET 3 +#define RTL8367D_BUFF_RST_TIME_SHORT_MASK 0xF8 +#define RTL8367D_SW_BUFF_RST_OFFSET 2 +#define RTL8367D_SW_BUFF_RST_MASK 0x4 +#define RTL8367D_IMS_BUFF_RST_OFFSET 1 +#define RTL8367D_IMS_BUFF_RST_MASK 0x2 +#define RTL8367D_IMR_BUFF_RST_OFFSET 0 +#define RTL8367D_IMR_BUFF_RST_MASK 0x1 + +#define RTL8367D_REG_BUFF_RST_CTRL1 0x1d65 +#define RTL8367D_BUFFRST_SYSOVER_EN_OFFSET 11 +#define RTL8367D_BUFFRST_SYSOVER_EN_MASK 0x800 +#define RTL8367D_BUFFRST_SYSOVER_THR_OFFSET 0 +#define RTL8367D_BUFFRST_SYSOVER_THR_MASK 0x7FF + +#define RTL8367D_REG_BUFF_RST_CTRL2 0x1d66 +#define RTL8367D_BUFFRST_QOVER_EN_OFFSET 11 +#define RTL8367D_BUFFRST_QOVER_EN_MASK 0x800 +#define RTL8367D_BUFFRST_QOVER_THR_OFFSET 0 +#define RTL8367D_BUFFRST_QOVER_THR_MASK 0x7FF + +#define RTL8367D_REG_BUFF_RST_CTRL3 0x1d67 +#define RTL8367D_DSC_TIMER_OFFSET 12 +#define RTL8367D_DSC_TIMER_MASK 0xF000 +#define RTL8367D_BUFFRST_DSCOVER_THR_OFFSET 1 +#define RTL8367D_BUFFRST_DSCOVER_THR_MASK 0xFFE +#define RTL8367D_BUFFRST_DSCOVER_EN_OFFSET 0 +#define RTL8367D_BUFFRST_DSCOVER_EN_MASK 0x1 + +#define RTL8367D_REG_BUFF_RST_CTRL4 0x1d68 +#define RTL8367D_INDSC_TIMER_OFFSET 12 +#define RTL8367D_INDSC_TIMER_MASK 0xF000 +#define RTL8367D_BUFFRST_INDSCOVER_THR_OFFSET 1 +#define RTL8367D_BUFFRST_INDSCOVER_THR_MASK 0xFFE +#define RTL8367D_BUFFRST_INDSCOVER_EN_OFFSET 0 +#define RTL8367D_BUFFRST_INDSCOVER_EN_MASK 0x1 + +#define RTL8367D_REG_TOP_CON0 0x1d70 +#define RTL8367D_MAC7_SEL_EXT1_OFFSET 13 +#define RTL8367D_MAC7_SEL_EXT1_MASK 0x2000 +#define RTL8367D_MAC4_SEL_EXT1_OFFSET 12 +#define RTL8367D_MAC4_SEL_EXT1_MASK 0x1000 +#define RTL8367D_FIB_EEE_AB_OFFSET 11 +#define RTL8367D_FIB_EEE_AB_MASK 0x800 +#define RTL8367D_ADCCKIEN_OFFSET 10 +#define RTL8367D_ADCCKIEN_MASK 0x400 +#define RTL8367D_OCP_TIMEOUT_OFFSET 5 +#define RTL8367D_OCP_TIMEOUT_MASK 0x3E0 +#define RTL8367D_RG2_TXC_SEL_OFFSET 3 +#define RTL8367D_RG2_TXC_SEL_MASK 0x8 +#define RTL8367D_RG1TXC_SEL_OFFSET 2 +#define RTL8367D_RG1TXC_SEL_MASK 0x4 +#define RTL8367D_SYNC_1588_EN_OFFSET 1 +#define RTL8367D_SYNC_1588_EN_MASK 0x2 +#define RTL8367D_LS_MODE_OFFSET 0 +#define RTL8367D_LS_MODE_MASK 0x1 + +#define RTL8367D_REG_TOP_CON1 0x1d71 +#define RTL8367D_TA_CHK_EN_OFFSET 2 +#define RTL8367D_TA_CHK_EN_MASK 0x4 +#define RTL8367D_SLV_EG_SEL_OFFSET 1 +#define RTL8367D_SLV_EG_SEL_MASK 0x2 +#define RTL8367D_IIC_OP_DRAIN_OFFSET 0 +#define RTL8367D_IIC_OP_DRAIN_MASK 0x1 + +#define RTL8367D_REG_SWR_FPWM 0x1d72 +#define RTL8367D_SWR_FPWM_OFFSET 0 +#define RTL8367D_SWR_FPWM_MASK 0x1 + +#define RTL8367D_REG_EEEP_CTRL_500M 0x1d73 + +#define RTL8367D_REG_SHORT_PRMB 0x1d74 +#define RTL8367D_SHORT_PRMB_OFFSET 0 +#define RTL8367D_SHORT_PRMB_MASK 0x1 + +#define RTL8367D_REG_TOP_ACS_OPT 0x1d75 +#define RTL8367D_CFG_OCP_DIRACS_OFFSET 1 +#define RTL8367D_CFG_OCP_DIRACS_MASK 0x2 +#define RTL8367D_CFG_67D_DIR_MDX_OFFSET 0 +#define RTL8367D_CFG_67D_DIR_MDX_MASK 0x1 + +#define RTL8367D_REG_CAL_CMD_0 0x1d76 +#define RTL8367D_CAL_CME_EN_OFFSET 5 +#define RTL8367D_CAL_CME_EN_MASK 0x20 +#define RTL8367D_CAL_PHYAD_OFFSET 0 +#define RTL8367D_CAL_PHYAD_MASK 0x1F + +#define RTL8367D_REG_CAL_CMD_1 0x1d77 +#define RTL8367D_CAL_CMD7_OFFSET 6 +#define RTL8367D_CAL_CMD7_MASK 0x40 +#define RTL8367D_CAL_CMD6_OFFSET 5 +#define RTL8367D_CAL_CMD6_MASK 0x20 +#define RTL8367D_CAL_CMD5_OFFSET 4 +#define RTL8367D_CAL_CMD5_MASK 0x10 +#define RTL8367D_CAL_CMD4_OFFSET 3 +#define RTL8367D_CAL_CMD4_MASK 0x8 +#define RTL8367D_CAL_CMD3_OFFSET 2 +#define RTL8367D_CAL_CMD3_MASK 0x4 +#define RTL8367D_CAL_CMD2_OFFSET 1 +#define RTL8367D_CAL_CMD2_MASK 0x2 +#define RTL8367D_CAL_CMD1_OFFSET 0 +#define RTL8367D_CAL_CMD1_MASK 0x1 + +#define RTL8367D_REG_SDS1_MISC0 0x1d78 +#define RTL8367D_PA33PC_EN_S1_OFFSET 10 +#define RTL8367D_PA33PC_EN_S1_MASK 0x400 +#define RTL8367D_PA12PC_EN_S1_OFFSET 9 +#define RTL8367D_PA12PC_EN_S1_MASK 0x200 +#define RTL8367D_SDS1_MISC0_SDS_PWR_ISO_EN_1_OFFSET 8 +#define RTL8367D_SDS1_MISC0_SDS_PWR_ISO_EN_1_MASK 0x100 +#define RTL8367D_SDS1_MISC0_SDS_FRC_REG4_EN_1_OFFSET 7 +#define RTL8367D_SDS1_MISC0_SDS_FRC_REG4_EN_1_MASK 0x80 +#define RTL8367D_SDS1_MISC0_SDS_FRC_REG4_FIB100_1_OFFSET 6 +#define RTL8367D_SDS1_MISC0_SDS_FRC_REG4_FIB100_1_MASK 0x40 +#define RTL8367D_SDS1_MISC0_CFG_UNIDIR_TX_OFFSET 5 +#define RTL8367D_SDS1_MISC0_CFG_UNIDIR_TX_MASK 0x20 +#define RTL8367D_SDS1_MODE_OFFSET 0 +#define RTL8367D_SDS1_MODE_MASK 0x1F + +#define RTL8367D_REG_SRAM_CTRL_MISC0 0x1d7a +#define RTL8367D_FRC_HSARAM_TGL_OFFSET 15 +#define RTL8367D_FRC_HSARAM_TGL_MASK 0x8000 +#define RTL8367D_BIST_GRP_EN_OUTQRAM_OFFSET 8 +#define RTL8367D_BIST_GRP_EN_OUTQRAM_MASK 0x7F00 +#define RTL8367D_TEST1_HTRAM_OFFSET 7 +#define RTL8367D_TEST1_HTRAM_MASK 0x80 +#define RTL8367D_TESTRWM_HTRAM_OFFSET 6 +#define RTL8367D_TESTRWM_HTRAM_MASK 0x40 +#define RTL8367D_DYN_READ_EN_HSARAM_OFFSET 5 +#define RTL8367D_DYN_READ_EN_HSARAM_MASK 0x20 +#define RTL8367D_DYN_READ_EN_OUTQRAM_OFFSET 4 +#define RTL8367D_DYN_READ_EN_OUTQRAM_MASK 0x10 +#define RTL8367D_DYN_READ_EN_HTRAM_OFFSET 3 +#define RTL8367D_DYN_READ_EN_HTRAM_MASK 0x8 +#define RTL8367D_BIST_LOOP_MODE_HSARAM_OFFSET 2 +#define RTL8367D_BIST_LOOP_MODE_HSARAM_MASK 0x4 +#define RTL8367D_BIST_LOOP_MODE_OUTQRAM_OFFSET 1 +#define RTL8367D_BIST_LOOP_MODE_OUTQRAM_MASK 0x2 +#define RTL8367D_BIST_LOOP_MODE_HTRAM_OFFSET 0 +#define RTL8367D_BIST_LOOP_MODE_HTRAM_MASK 0x1 + +#define RTL8367D_REG_EF_NRAM_WR_CMD0 0x1d7b + +#define RTL8367D_REG_EF_NRAM_WR_CMD1 0x1d7c + +#define RTL8367D_REG_EF_NRAM_WR_CMD2 0x1d7d + +#define RTL8367D_REG_EF_NRAM_ADR_BGN 0x1d7e +#define RTL8367D_EF_NRAM_ADR_BGN_EFUSE_CHK_PS_OFFSET 8 +#define RTL8367D_EF_NRAM_ADR_BGN_EFUSE_CHK_PS_MASK 0x100 +#define RTL8367D_NRAM_ADR_BGN_OFFSET 0 +#define RTL8367D_NRAM_ADR_BGN_MASK 0xFF + +#define RTL8367D_REG_EFUSE_CHK_CMD0 0x1d7f +#define RTL8367D_EF_CHK_BGN_OFFSET 8 +#define RTL8367D_EF_CHK_BGN_MASK 0xFF00 +#define RTL8367D_EF_CHK_END_OFFSET 0 +#define RTL8367D_EF_CHK_END_MASK 0xFF + +#define RTL8367D_REG_EFUSE_CHK_CMD1 0x1d80 + +#define RTL8367D_REG_TOP_CON_MISC0 0x1d81 +#define RTL8367D_DBG_SEL_SDS01_OFFSET 4 +#define RTL8367D_DBG_SEL_SDS01_MASK 0x10 +#define RTL8367D_PERI_WRMSK_EN_OFFSET 0 +#define RTL8367D_PERI_WRMSK_EN_MASK 0xF + +#define RTL8367D_REG_DSS_0_CTRL0 0x1d82 +#define RTL8367D_DSS_0_RO_SEL_OFFSET 7 +#define RTL8367D_DSS_0_RO_SEL_MASK 0x380 +#define RTL8367D_DSS_0_WIRE_SEL_OFFSET 6 +#define RTL8367D_DSS_0_WIRE_SEL_MASK 0x40 +#define RTL8367D_DSS_0_RST_N_OFFSET 5 +#define RTL8367D_DSS_0_RST_N_MASK 0x20 +#define RTL8367D_DSS_0_SPEED_EN_OFFSET 4 +#define RTL8367D_DSS_0_SPEED_EN_MASK 0x10 +#define RTL8367D_DSS_0_DATA_IN_19_16_OFFSET 0 +#define RTL8367D_DSS_0_DATA_IN_19_16_MASK 0xF + +#define RTL8367D_REG_DSS_0_CTRL1 0x1d83 + +#define RTL8367D_REG_DSS_0_STS0 0x1d84 +#define RTL8367D_DSS_0_WSORT_GO_OFFSET 5 +#define RTL8367D_DSS_0_WSORT_GO_MASK 0x20 +#define RTL8367D_DSS_0_READY_OFFSET 4 +#define RTL8367D_DSS_0_READY_MASK 0x10 +#define RTL8367D_DSS_0_COUNT_OUT_19_16_OFFSET 0 +#define RTL8367D_DSS_0_COUNT_OUT_19_16_MASK 0xF + +#define RTL8367D_REG_DSS_0_STS1 0x1d85 + +#define RTL8367D_REG_DSS_1_CTRL0 0x1d86 +#define RTL8367D_DSS_1_RO_SEL_OFFSET 7 +#define RTL8367D_DSS_1_RO_SEL_MASK 0x380 +#define RTL8367D_DSS_1_WIRE_SEL_OFFSET 6 +#define RTL8367D_DSS_1_WIRE_SEL_MASK 0x40 +#define RTL8367D_DSS_1_RST_N_OFFSET 5 +#define RTL8367D_DSS_1_RST_N_MASK 0x20 +#define RTL8367D_DSS_1_SPEED_EN_OFFSET 4 +#define RTL8367D_DSS_1_SPEED_EN_MASK 0x10 +#define RTL8367D_DSS_1_DATA_IN_19_16_OFFSET 0 +#define RTL8367D_DSS_1_DATA_IN_19_16_MASK 0xF + +#define RTL8367D_REG_DSS_1_CTRL1 0x1d87 + +#define RTL8367D_REG_DSS_1_STS0 0x1d88 +#define RTL8367D_DSS_1_WSORT_GO_OFFSET 5 +#define RTL8367D_DSS_1_WSORT_GO_MASK 0x20 +#define RTL8367D_DSS_1_READY_OFFSET 4 +#define RTL8367D_DSS_1_READY_MASK 0x10 +#define RTL8367D_DSS_1_COUNT_OUT_19_16_OFFSET 0 +#define RTL8367D_DSS_1_COUNT_OUT_19_16_MASK 0xF + +#define RTL8367D_REG_DSS_1_STS1 0x1d89 + +#define RTL8367D_REG_DSS_2_CTRL0 0x1d8a +#define RTL8367D_DSS_2_RO_SEL_OFFSET 7 +#define RTL8367D_DSS_2_RO_SEL_MASK 0x380 +#define RTL8367D_DSS_2_WIRE_SEL_OFFSET 6 +#define RTL8367D_DSS_2_WIRE_SEL_MASK 0x40 +#define RTL8367D_DSS_2_RST_N_OFFSET 5 +#define RTL8367D_DSS_2_RST_N_MASK 0x20 +#define RTL8367D_DSS_2_SPEED_EN_OFFSET 4 +#define RTL8367D_DSS_2_SPEED_EN_MASK 0x10 +#define RTL8367D_DSS_2_DATA_IN_19_16_OFFSET 0 +#define RTL8367D_DSS_2_DATA_IN_19_16_MASK 0xF + +#define RTL8367D_REG_DSS_2_CTRL1 0x1d8b + +#define RTL8367D_REG_DSS_2_STS0 0x1d8c +#define RTL8367D_DSS_2_WSORT_GO_OFFSET 5 +#define RTL8367D_DSS_2_WSORT_GO_MASK 0x20 +#define RTL8367D_DSS_2_READY_OFFSET 4 +#define RTL8367D_DSS_2_READY_MASK 0x10 +#define RTL8367D_DSS_2_COUNT_OUT_19_16_OFFSET 0 +#define RTL8367D_DSS_2_COUNT_OUT_19_16_MASK 0xF + +#define RTL8367D_REG_DSS_2_STS1 0x1d8d + +#define RTL8367D_REG_THERMAL_CTRL_0 0x1d90 +#define RTL8367D_TM_REG_TD_WREP_SEL_OFFSET 14 +#define RTL8367D_TM_REG_TD_WREP_SEL_MASK 0x4000 +#define RTL8367D_TM_REG_PPOW_OFFSET 13 +#define RTL8367D_TM_REG_PPOW_MASK 0x2000 +#define RTL8367D_TM_REG_RSTB_OFFSET 12 +#define RTL8367D_TM_REG_RSTB_MASK 0x1000 +#define RTL8367D_TM_REG_BIASCHOP_OFFSET 11 +#define RTL8367D_TM_REG_BIASCHOP_MASK 0x800 +#define RTL8367D_TM_REG_CHOPEN_OFFSET 10 +#define RTL8367D_TM_REG_CHOPEN_MASK 0x400 +#define RTL8367D_TM_REG_CAL_EN_OFFSET 9 +#define RTL8367D_TM_REG_CAL_EN_MASK 0x200 +#define RTL8367D_TM_REG_HOLD_EN_OFFSET 8 +#define RTL8367D_TM_REG_HOLD_EN_MASK 0x100 +#define RTL8367D_TM_REG_CKSOURCESEL_OFFSET 7 +#define RTL8367D_TM_REG_CKSOURCESEL_MASK 0x80 +#define RTL8367D_TM_REG_BIASDEM_SEL_OFFSET 6 +#define RTL8367D_TM_REG_BIASDEM_SEL_MASK 0x40 +#define RTL8367D_TM_REG_CHOPFREQSEL_OFFSET 2 +#define RTL8367D_TM_REG_CHOPFREQSEL_MASK 0x3C +#define RTL8367D_TM_REG_HOLD_DLY_OFFSET 0 +#define RTL8367D_TM_REG_HOLD_DLY_MASK 0x3 + +#define RTL8367D_REG_THERMAL_CTRL_1 0x1d91 +#define RTL8367D_TM_REG_FILTEREDGESEL_OFFSET 15 +#define RTL8367D_TM_REG_FILTEREDGESEL_MASK 0x8000 +#define RTL8367D_TM_REG_ORDER3_OFFSET 14 +#define RTL8367D_TM_REG_ORDER3_MASK 0x4000 +#define RTL8367D_TM_REG_OPCURSEL_OFFSET 12 +#define RTL8367D_TM_REG_OPCURSEL_MASK 0x3000 +#define RTL8367D_TM_REG_OSCCURSEL_OFFSET 10 +#define RTL8367D_TM_REG_OSCCURSEL_MASK 0xC00 +#define RTL8367D_TM_REG_VBE_BIASSEL_OFFSET 8 +#define RTL8367D_TM_REG_VBE_BIASSEL_MASK 0x300 +#define RTL8367D_TM_REG_ADCCKSEL_OFFSET 5 +#define RTL8367D_TM_REG_ADCCKSEL_MASK 0xE0 +#define RTL8367D_TM_REG_DSR_OFFSET 2 +#define RTL8367D_TM_REG_DSR_MASK 0x1C +#define RTL8367D_TM_REG_RESOL_OFFSET 0 +#define RTL8367D_TM_REG_RESOL_MASK 0x3 + +#define RTL8367D_REG_THERMAL_CTRL_2 0x1d92 +#define RTL8367D_THERMAL_CTRL_2_OFFSET 0 +#define RTL8367D_THERMAL_CTRL_2_MASK 0x3F + +#define RTL8367D_REG_THERMAL_CTRL_3 0x1d93 + +#define RTL8367D_REG_THERMAL_CTRL_4 0x1d94 +#define RTL8367D_THERMAL_CTRL_4_OFFSET 0 +#define RTL8367D_THERMAL_CTRL_4_MASK 0x3F + +#define RTL8367D_REG_THERMAL_CTRL_5 0x1d95 + +#define RTL8367D_REG_THERMAL_CTRL_6 0x1d96 +#define RTL8367D_THERMAL_CTRL_6_OFFSET 0 +#define RTL8367D_THERMAL_CTRL_6_MASK 0x7F + +#define RTL8367D_REG_THERMAL_CTRL_7 0x1d97 + +#define RTL8367D_REG_THERMAL_CTRL_8 0x1d98 +#define RTL8367D_THERMAL_CTRL_8_OFFSET 0 +#define RTL8367D_THERMAL_CTRL_8_MASK 0xFF + +#define RTL8367D_REG_THERMAL_CTRL_9 0x1d99 + +#define RTL8367D_REG_THERMAL_CTRL_10 0x1d9a +#define RTL8367D_THERMAL_CTRL_10_OFFSET 0 +#define RTL8367D_THERMAL_CTRL_10_MASK 0x1FFF + +#define RTL8367D_REG_THERMAL_CTRL_11 0x1d9b + +#define RTL8367D_REG_THERMAL_CTRL_12 0x1d9c +#define RTL8367D_TM_CMP_HIGH_EN0_OFFSET 3 +#define RTL8367D_TM_CMP_HIGH_EN0_MASK 0x8 +#define RTL8367D_TM_HIGH_THR0_18_16_OFFSET 0 +#define RTL8367D_TM_HIGH_THR0_18_16_MASK 0x7 + +#define RTL8367D_REG_THERMAL_CTRL_13 0x1d9d + +#define RTL8367D_REG_THERMAL_CTRL_14 0x1d9e +#define RTL8367D_TM_CMP_LOW_EN0_OFFSET 3 +#define RTL8367D_TM_CMP_LOW_EN0_MASK 0x8 +#define RTL8367D_TM_LOW_THR0_18_16_OFFSET 0 +#define RTL8367D_TM_LOW_THR0_18_16_MASK 0x7 + +#define RTL8367D_REG_THERMAL_CTRL_15 0x1d9f + +#define RTL8367D_REG_THERMAL_CTRL_16 0x1da0 +#define RTL8367D_TM_CMP_HIGH_EN1_OFFSET 3 +#define RTL8367D_TM_CMP_HIGH_EN1_MASK 0x8 +#define RTL8367D_TM_HIGH_THR1_18_16_OFFSET 0 +#define RTL8367D_TM_HIGH_THR1_18_16_MASK 0x7 + +#define RTL8367D_REG_THERMAL_CTRL_17 0x1da1 + +#define RTL8367D_REG_THERMAL_CTRL_18 0x1da2 +#define RTL8367D_TM_CMP_LOW_EN1_OFFSET 3 +#define RTL8367D_TM_CMP_LOW_EN1_MASK 0x8 +#define RTL8367D_TM_LOW_THR1_18_16_OFFSET 0 +#define RTL8367D_TM_LOW_THR1_18_16_MASK 0x7 + +#define RTL8367D_REG_THERMAL_CTRL_19 0x1da3 + +#define RTL8367D_REG_THERMAL_STS_0 0x1da4 +#define RTL8367D_TM_SAMPLE_TOG_OFFSET 3 +#define RTL8367D_TM_SAMPLE_TOG_MASK 0x8 +#define RTL8367D_TM_SENS_OUT_18_16_OFFSET 0 +#define RTL8367D_TM_SENS_OUT_18_16_MASK 0x7 + +#define RTL8367D_REG_THERMAL_STS_1 0x1da5 + +#define RTL8367D_REG_THERMAL_STS_2 0x1da6 +#define RTL8367D_THERMAL_STS_2_OFFSET 0 +#define RTL8367D_THERMAL_STS_2_MASK 0x3F + +#define RTL8367D_REG_THERMAL_STS_3 0x1da7 + +#define RTL8367D_REG_THERMAL_STS_4 0x1da8 +#define RTL8367D_CLR_TM_TEMP_MAX_OFFSET 3 +#define RTL8367D_CLR_TM_TEMP_MAX_MASK 0x8 +#define RTL8367D_TM_TEMP_MAX_18_16_OFFSET 0 +#define RTL8367D_TM_TEMP_MAX_18_16_MASK 0x7 + +#define RTL8367D_REG_THERMAL_STS_5 0x1da9 + +#define RTL8367D_REG_THERMAL_STS_6 0x1daa +#define RTL8367D_CLR_TM_TEMP_MIN_OFFSET 3 +#define RTL8367D_CLR_TM_TEMP_MIN_MASK 0x8 +#define RTL8367D_TM_TEMP_MIN_18_16_OFFSET 0 +#define RTL8367D_TM_TEMP_MIN_18_16_MASK 0x7 + +#define RTL8367D_REG_THERMAL_STS_7 0x1dab + +#define RTL8367D_REG_THERMAL_STS_8 0x1dac +#define RTL8367D_PWRON_ADC_RDY_OFFSET 6 +#define RTL8367D_PWRON_ADC_RDY_MASK 0x40 +#define RTL8367D_PWRON_ADC_OUT_21_16_OFFSET 0 +#define RTL8367D_PWRON_ADC_OUT_21_16_MASK 0x3F + +#define RTL8367D_REG_THERMAL_STS_9 0x1dad + +#define RTL8367D_REG_CFG_GPIO_SRC_X0 0x1db0 + +#define RTL8367D_REG_CFG_GPIO_SRC_X1 0x1db1 + +#define RTL8367D_REG_CFG_GPIO_SRC_X2 0x1db2 + +#define RTL8367D_REG_CFG_GPIO_SRC_X3 0x1db3 +#define RTL8367D_CFG_GPIO_SRC_X3_OFFSET 0 +#define RTL8367D_CFG_GPIO_SRC_X3_MASK 0x3FFF + +#define RTL8367D_REG_GPIO_8051_O_X0 0x1db4 + +#define RTL8367D_REG_GPIO_8051_O_X1 0x1db5 + +#define RTL8367D_REG_GPIO_8051_O_X2 0x1db6 + +#define RTL8367D_REG_GPIO_8051_O_X3 0x1db7 +#define RTL8367D_GPIO_8051_O_X3_OFFSET 0 +#define RTL8367D_GPIO_8051_O_X3_MASK 0x3FFF + +#define RTL8367D_REG_GPIO_8051_OE_X0 0x1db8 + +#define RTL8367D_REG_GPIO_8051_OE_X1 0x1db9 + +#define RTL8367D_REG_GPIO_8051_OE_X2 0x1dba + +#define RTL8367D_REG_GPIO_8051_OE_X3 0x1dbb +#define RTL8367D_GPIO_8051_OE_X3_OFFSET 0 +#define RTL8367D_GPIO_8051_OE_X3_MASK 0x3FFF + +#define RTL8367D_REG_CFG_CHIP_67D_DUMMY0 0x1df0 + +#define RTL8367D_REG_CFG_CHIP_67D_DUMMY1 0x1df1 + +#define RTL8367D_REG_CFG_CHIP_67D_DUMMY2 0x1df2 + +#define RTL8367D_REG_CFG_CHIP_67D_DUMMY3 0x1df3 + +#define RTL8367D_REG_CFG_CHIP_67D_DUMMY4 0x1df4 + +#define RTL8367D_REG_BOND_FOR_READ 0x1df5 +#define RTL8367D_BOND_FOR_READ_OFFSET 0 +#define RTL8367D_BOND_FOR_READ_MASK 0x7FF + +/* (16'h1e00)phy_reg */ + +#define RTL8367D_REG_PHY_RG0X_CEN 0x1e00 + +#define RTL8367D_REG_PHY_RG1X_CEN 0x1e01 + +#define RTL8367D_REG_PHY_RG2X_CEN 0x1e02 + +#define RTL8367D_REG_PHY_RG3X_CEN 0x1e03 + +#define RTL8367D_REG_PHY_RG4X_CEN 0x1e04 + +#define RTL8367D_REG_PHY_RG5X_CEN 0x1e05 + +#define RTL8367D_REG_PHY_RG6X_CEN 0x1e06 + +#define RTL8367D_REG_PHY_RG7X_CEN 0x1e07 + +#define RTL8367D_REG_PHY_RG8X_CEN 0x1e08 + +#define RTL8367D_REG_PHY_RG9X_CEN 0x1e09 + +#define RTL8367D_REG_PHY_RG10X_CEN 0x1e0a + +#define RTL8367D_REG_PHY_RG11X_CEN 0x1e0b + +#define RTL8367D_REG_PHY_RG12X_CEN 0x1e0c + +#define RTL8367D_REG_PHY_RG13X_CEN 0x1e0d + +#define RTL8367D_REG_PHY_RG0X_PLL 0x1e0e + +#define RTL8367D_REG_PHY_RG1X_PLL 0x1e0f + +#define RTL8367D_REG_PHY_RG2X_PLL 0x1e10 + +#define RTL8367D_REG_PHY_RG3X_PLL 0x1e11 + +#define RTL8367D_REG_PHY_RG4X_PLL 0x1e12 + +#define RTL8367D_REG_PHY_RG5X_PLL 0x1e13 + +#define RTL8367D_REG_PHY_RG6X_PLL 0x1e14 + +#define RTL8367D_REG_PHY_RG7X_PLL 0x1e15 + +#define RTL8367D_REG_PHY_RG8X_PLL 0x1e16 + +#define RTL8367D_REG_PHY_RG9X_PLL 0x1e17 + +#define RTL8367D_REG_PHY_POW_PLL 0x1e18 +#define RTL8367D_ADCCKI_EN_OFFSET 2 +#define RTL8367D_ADCCKI_EN_MASK 0xC +#define RTL8367D_POWLDO_PLL_OFFSET 1 +#define RTL8367D_POWLDO_PLL_MASK 0x2 +#define RTL8367D_POWSW_PLL_OFFSET 0 +#define RTL8367D_POWSW_PLL_MASK 0x1 + +#define RTL8367D_REG_PHY_IB_DN_10M_X0 0x1e19 +#define RTL8367D_CFG_IB_ENDN_10M_X0_OFFSET 8 +#define RTL8367D_CFG_IB_ENDN_10M_X0_MASK 0x100 +#define RTL8367D_CFG_IB_DN_10M_X0_OFFSET 0 +#define RTL8367D_CFG_IB_DN_10M_X0_MASK 0xFF + +#define RTL8367D_REG_PHY_IB_UP_10M_X0 0x1e1a +#define RTL8367D_CFG_IB_UPALL_10M_X0_OFFSET 8 +#define RTL8367D_CFG_IB_UPALL_10M_X0_MASK 0x100 +#define RTL8367D_CFG_IB_UP_10M_X0_OFFSET 0 +#define RTL8367D_CFG_IB_UP_10M_X0_MASK 0xFF + +#define RTL8367D_REG_PHY_IB_DN_100M_X0 0x1e1b +#define RTL8367D_CFG_IB_ENDN_100M_X0_OFFSET 8 +#define RTL8367D_CFG_IB_ENDN_100M_X0_MASK 0x100 +#define RTL8367D_CFG_IB_DN_100M_X0_OFFSET 0 +#define RTL8367D_CFG_IB_DN_100M_X0_MASK 0xFF + +#define RTL8367D_REG_PHY_IB_UP_100M_X0 0x1e1c +#define RTL8367D_CFG_IB_UPALL_100M_X0_OFFSET 8 +#define RTL8367D_CFG_IB_UPALL_100M_X0_MASK 0x100 +#define RTL8367D_CFG_IB_UP_100M_X0_OFFSET 0 +#define RTL8367D_CFG_IB_UP_100M_X0_MASK 0xFF + +#define RTL8367D_REG_PHY_IB_DN_1000M_X0 0x1e1d +#define RTL8367D_CFG_IB_ENDN_1000M_X0_OFFSET 8 +#define RTL8367D_CFG_IB_ENDN_1000M_X0_MASK 0x100 +#define RTL8367D_CFG_IB_DN_1000M_X0_OFFSET 0 +#define RTL8367D_CFG_IB_DN_1000M_X0_MASK 0xFF + +#define RTL8367D_REG_PHY_IB_UP_1000M_X0 0x1e1e +#define RTL8367D_CFG_IB_UPALL_1000M_X0_OFFSET 8 +#define RTL8367D_CFG_IB_UPALL_1000M_X0_MASK 0x100 +#define RTL8367D_CFG_IB_UP_1000M_X0_OFFSET 0 +#define RTL8367D_CFG_IB_UP_1000M_X0_MASK 0xFF + +#define RTL8367D_REG_PHY_IB_DN_10M_X1 0x1e1f +#define RTL8367D_CFG_IB_ENDN_10M_X1_OFFSET 8 +#define RTL8367D_CFG_IB_ENDN_10M_X1_MASK 0x100 +#define RTL8367D_CFG_IB_DN_10M_X1_OFFSET 0 +#define RTL8367D_CFG_IB_DN_10M_X1_MASK 0xFF + +#define RTL8367D_REG_PHY_IB_UP_10M_X1 0x1e20 +#define RTL8367D_CFG_IB_UPALL_10M_X1_OFFSET 8 +#define RTL8367D_CFG_IB_UPALL_10M_X1_MASK 0x100 +#define RTL8367D_CFG_IB_UP_10M_X1_OFFSET 0 +#define RTL8367D_CFG_IB_UP_10M_X1_MASK 0xFF + +#define RTL8367D_REG_PHY_IB_DN_100M_X1 0x1e21 +#define RTL8367D_CFG_IB_ENDN_100M_X1_OFFSET 8 +#define RTL8367D_CFG_IB_ENDN_100M_X1_MASK 0x100 +#define RTL8367D_CFG_IB_DN_100M_X1_OFFSET 0 +#define RTL8367D_CFG_IB_DN_100M_X1_MASK 0xFF + +#define RTL8367D_REG_PHY_IB_UP_100M_X1 0x1e22 +#define RTL8367D_CFG_IB_UPALL_100M_X1_OFFSET 8 +#define RTL8367D_CFG_IB_UPALL_100M_X1_MASK 0x100 +#define RTL8367D_CFG_IB_UP_100M_X1_OFFSET 0 +#define RTL8367D_CFG_IB_UP_100M_X1_MASK 0xFF + +#define RTL8367D_REG_PHY_IB_DN_1000M_X1 0x1e23 +#define RTL8367D_CFG_IB_ENDN_1000M_X1_OFFSET 8 +#define RTL8367D_CFG_IB_ENDN_1000M_X1_MASK 0x100 +#define RTL8367D_CFG_IB_DN_1000M_X1_OFFSET 0 +#define RTL8367D_CFG_IB_DN_1000M_X1_MASK 0xFF + +#define RTL8367D_REG_PHY_IB_UP_1000M_X1 0x1e24 +#define RTL8367D_CFG_IB_UPALL_1000M_X1_OFFSET 8 +#define RTL8367D_CFG_IB_UPALL_1000M_X1_MASK 0x100 +#define RTL8367D_CFG_IB_UP_1000M_X1_OFFSET 0 +#define RTL8367D_CFG_IB_UP_1000M_X1_MASK 0xFF + +#define RTL8367D_REG_PHY_IB_DN_10M_X2 0x1e25 +#define RTL8367D_CFG_IB_ENDN_10M_X2_OFFSET 8 +#define RTL8367D_CFG_IB_ENDN_10M_X2_MASK 0x100 +#define RTL8367D_CFG_IB_DN_10M_X2_OFFSET 0 +#define RTL8367D_CFG_IB_DN_10M_X2_MASK 0xFF + +#define RTL8367D_REG_PHY_IB_UP_10M_X2 0x1e26 +#define RTL8367D_CFG_IB_UPALL_10M_X2_OFFSET 8 +#define RTL8367D_CFG_IB_UPALL_10M_X2_MASK 0x100 +#define RTL8367D_CFG_IB_UP_10M_X2_OFFSET 0 +#define RTL8367D_CFG_IB_UP_10M_X2_MASK 0xFF + +#define RTL8367D_REG_PHY_IB_DN_100M_X2 0x1e27 +#define RTL8367D_CFG_IB_ENDN_100M_X2_OFFSET 8 +#define RTL8367D_CFG_IB_ENDN_100M_X2_MASK 0x100 +#define RTL8367D_CFG_IB_DN_100M_X2_OFFSET 0 +#define RTL8367D_CFG_IB_DN_100M_X2_MASK 0xFF + +#define RTL8367D_REG_PHY_IB_UP_100M_X2 0x1e28 +#define RTL8367D_CFG_IB_UPALL_100M_X2_OFFSET 8 +#define RTL8367D_CFG_IB_UPALL_100M_X2_MASK 0x100 +#define RTL8367D_CFG_IB_UP_100M_X2_OFFSET 0 +#define RTL8367D_CFG_IB_UP_100M_X2_MASK 0xFF + +#define RTL8367D_REG_PHY_IB_DN_1000M_X2 0x1e29 +#define RTL8367D_CFG_IB_ENDN_1000M_X2_OFFSET 8 +#define RTL8367D_CFG_IB_ENDN_1000M_X2_MASK 0x100 +#define RTL8367D_CFG_IB_DN_1000M_X2_OFFSET 0 +#define RTL8367D_CFG_IB_DN_1000M_X2_MASK 0xFF + +#define RTL8367D_REG_PHY_IB_UP_1000M_X2 0x1e2a +#define RTL8367D_CFG_IB_UPALL_1000M_X2_OFFSET 8 +#define RTL8367D_CFG_IB_UPALL_1000M_X2_MASK 0x100 +#define RTL8367D_CFG_IB_UP_1000M_X2_OFFSET 0 +#define RTL8367D_CFG_IB_UP_1000M_X2_MASK 0xFF + +#define RTL8367D_REG_PHY_IB_DN_10M_X3 0x1e2b +#define RTL8367D_CFG_IB_ENDN_10M_X3_OFFSET 8 +#define RTL8367D_CFG_IB_ENDN_10M_X3_MASK 0x100 +#define RTL8367D_CFG_IB_DN_10M_X3_OFFSET 0 +#define RTL8367D_CFG_IB_DN_10M_X3_MASK 0xFF + +#define RTL8367D_REG_PHY_IB_UP_10M_X3 0x1e2c +#define RTL8367D_CFG_IB_UPALL_10M_X3_OFFSET 8 +#define RTL8367D_CFG_IB_UPALL_10M_X3_MASK 0x100 +#define RTL8367D_CFG_IB_UP_10M_X3_OFFSET 0 +#define RTL8367D_CFG_IB_UP_10M_X3_MASK 0xFF + +#define RTL8367D_REG_PHY_IB_DN_100M_X3 0x1e2d +#define RTL8367D_CFG_IB_ENDN_100M_X3_OFFSET 8 +#define RTL8367D_CFG_IB_ENDN_100M_X3_MASK 0x100 +#define RTL8367D_CFG_IB_DN_100M_X3_OFFSET 0 +#define RTL8367D_CFG_IB_DN_100M_X3_MASK 0xFF + +#define RTL8367D_REG_PHY_IB_UP_100M_X3 0x1e2e +#define RTL8367D_CFG_IB_UPALL_100M_X3_OFFSET 8 +#define RTL8367D_CFG_IB_UPALL_100M_X3_MASK 0x100 +#define RTL8367D_CFG_IB_UP_100M_X3_OFFSET 0 +#define RTL8367D_CFG_IB_UP_100M_X3_MASK 0xFF + +#define RTL8367D_REG_PHY_IB_DN_1000M_X3 0x1e2f +#define RTL8367D_CFG_IB_ENDN_1000M_X3_OFFSET 8 +#define RTL8367D_CFG_IB_ENDN_1000M_X3_MASK 0x100 +#define RTL8367D_CFG_IB_DN_1000M_X3_OFFSET 0 +#define RTL8367D_CFG_IB_DN_1000M_X3_MASK 0xFF + +#define RTL8367D_REG_PHY_IB_UP_1000M_X3 0x1e30 +#define RTL8367D_CFG_IB_UPALL_1000M_X3_OFFSET 8 +#define RTL8367D_CFG_IB_UPALL_1000M_X3_MASK 0x100 +#define RTL8367D_CFG_IB_UP_1000M_X3_OFFSET 0 +#define RTL8367D_CFG_IB_UP_1000M_X3_MASK 0xFF + +#define RTL8367D_REG_PHY_IB_DN_10M_X4 0x1e31 +#define RTL8367D_CFG_IB_ENDN_10M_X4_OFFSET 8 +#define RTL8367D_CFG_IB_ENDN_10M_X4_MASK 0x100 +#define RTL8367D_CFG_IB_DN_10M_X4_OFFSET 0 +#define RTL8367D_CFG_IB_DN_10M_X4_MASK 0xFF + +#define RTL8367D_REG_PHY_IB_UP_10M_X4 0x1e32 +#define RTL8367D_CFG_IB_UPALL_10M_X4_OFFSET 8 +#define RTL8367D_CFG_IB_UPALL_10M_X4_MASK 0x100 +#define RTL8367D_CFG_IB_UP_10M_X4_OFFSET 0 +#define RTL8367D_CFG_IB_UP_10M_X4_MASK 0xFF + +#define RTL8367D_REG_PHY_IB_DN_100M_X4 0x1e33 +#define RTL8367D_CFG_IB_ENDN_100M_X4_OFFSET 8 +#define RTL8367D_CFG_IB_ENDN_100M_X4_MASK 0x100 +#define RTL8367D_CFG_IB_DN_100M_X4_OFFSET 0 +#define RTL8367D_CFG_IB_DN_100M_X4_MASK 0xFF + +#define RTL8367D_REG_PHY_IB_UP_100M_X4 0x1e34 +#define RTL8367D_CFG_IB_UPALL_100M_X4_OFFSET 8 +#define RTL8367D_CFG_IB_UPALL_100M_X4_MASK 0x100 +#define RTL8367D_CFG_IB_UP_100M_X4_OFFSET 0 +#define RTL8367D_CFG_IB_UP_100M_X4_MASK 0xFF + +#define RTL8367D_REG_PHY_IB_DN_1000M_X4 0x1e35 +#define RTL8367D_CFG_IB_ENDN_1000M_X4_OFFSET 8 +#define RTL8367D_CFG_IB_ENDN_1000M_X4_MASK 0x100 +#define RTL8367D_CFG_IB_DN_1000M_X4_OFFSET 0 +#define RTL8367D_CFG_IB_DN_1000M_X4_MASK 0xFF + +#define RTL8367D_REG_PHY_IB_UP_1000M_X4 0x1e36 +#define RTL8367D_CFG_IB_UPALL_1000M_X4_OFFSET 8 +#define RTL8367D_CFG_IB_UPALL_1000M_X4_MASK 0x100 +#define RTL8367D_CFG_IB_UP_1000M_X4_OFFSET 0 +#define RTL8367D_CFG_IB_UP_1000M_X4_MASK 0xFF + +#define RTL8367D_REG_PHY_STATUS 0x1e37 +#define RTL8367D_PHY_FATAL_OFFSET 10 +#define RTL8367D_PHY_FATAL_MASK 0x7C00 +#define RTL8367D_PHY_LANON_OFFSET 5 +#define RTL8367D_PHY_LANON_MASK 0x3E0 +#define RTL8367D_PHY_EXTINI_OFFSET 0 +#define RTL8367D_PHY_EXTINI_MASK 0x1F + +#define RTL8367D_REG_PHY_PCSXF 0x1e38 +#define RTL8367D_PHY_PCSXF_OFFSET 0 +#define RTL8367D_PHY_PCSXF_MASK 0x1F + +#define RTL8367D_REG_RDM_UPD_PERIOD 0x1e39 +#define RTL8367D_RSUPD_PERIOD_OFFSET 8 +#define RTL8367D_RSUPD_PERIOD_MASK 0xFF00 +#define RTL8367D_RRUPD_PERIOD_OFFSET 0 +#define RTL8367D_RRUPD_PERIOD_MASK 0xFF + +#define RTL8367D_REG_RDM_UPD_CTRL 0x1e3a +#define RTL8367D_TMTENBIT_OFFSET 15 +#define RTL8367D_TMTENBIT_MASK 0x8000 +#define RTL8367D_TMLSB_OFFSET 12 +#define RTL8367D_TMLSB_MASK 0x7000 +#define RTL8367D_RR_SEL_MTHD_OFFSET 11 +#define RTL8367D_RR_SEL_MTHD_MASK 0x800 +#define RTL8367D_RRSTEP_OFFSET 6 +#define RTL8367D_RRSTEP_MASK 0x7C0 +#define RTL8367D_RRRND_SRC_SEL_OFFSET 5 +#define RTL8367D_RRRND_SRC_SEL_MASK 0x20 +#define RTL8367D_RRUPD_ONCE_OFFSET 4 +#define RTL8367D_RRUPD_ONCE_MASK 0x10 +#define RTL8367D_RRUPD_EN_OFFSET 3 +#define RTL8367D_RRUPD_EN_MASK 0x8 +#define RTL8367D_RSRND_SRC_SEL_OFFSET 2 +#define RTL8367D_RSRND_SRC_SEL_MASK 0x4 +#define RTL8367D_RSUPD_ONCE_OFFSET 1 +#define RTL8367D_RSUPD_ONCE_MASK 0x2 +#define RTL8367D_RSUPD_EN_OFFSET 0 +#define RTL8367D_RSUPD_EN_MASK 0x1 + +#define RTL8367D_REG_RG_RDM_SEED_SRC 0x1e3b + +#define RTL8367D_REG_RG_RING_RATE 0x1e3c + +#define RTL8367D_REG_RING_RAGE_MASK_L 0x1e3d + +#define RTL8367D_REG_RING_RAGE_MASK_H 0x1e3e + +#define RTL8367D_REG_BIST_GMACRAM0 0x1e3f +#define RTL8367D_GMACRAM_DRF_BIST_FAIL_OFFSET 15 +#define RTL8367D_GMACRAM_DRF_BIST_FAIL_MASK 0x8000 +#define RTL8367D_GMACRAM_BIST_FAIL_OFFSET 14 +#define RTL8367D_GMACRAM_BIST_FAIL_MASK 0x4000 +#define RTL8367D_GMACRAM_DRF_BIST_DONE_OFFSET 13 +#define RTL8367D_GMACRAM_DRF_BIST_DONE_MASK 0x2000 +#define RTL8367D_GMACRAM_BIST_DONE_OFFSET 12 +#define RTL8367D_GMACRAM_BIST_DONE_MASK 0x1000 +#define RTL8367D_GMACRAM_DRF_START_PAUSE_OFFSET 11 +#define RTL8367D_GMACRAM_DRF_START_PAUSE_MASK 0x800 +#define RTL8367D_GMACRAM_DYN_READ_EN_OFFSET 10 +#define RTL8367D_GMACRAM_DYN_READ_EN_MASK 0x400 +#define RTL8367D_GMACRAM_BIST_LOOP_MODE_OFFSET 9 +#define RTL8367D_GMACRAM_BIST_LOOP_MODE_MASK 0x200 +#define RTL8367D_GMACRAM_RME_OFFSET 8 +#define RTL8367D_GMACRAM_RME_MASK 0x100 +#define RTL8367D_GMACRAM_RM_OFFSET 4 +#define RTL8367D_GMACRAM_RM_MASK 0xF0 +#define RTL8367D_GMACRAM_DRF_TEST_RESUME_OFFSET 3 +#define RTL8367D_GMACRAM_DRF_TEST_RESUME_MASK 0x8 +#define RTL8367D_GMACRAM_DRF_BIST_MODE_OFFSET 2 +#define RTL8367D_GMACRAM_DRF_BIST_MODE_MASK 0x4 +#define RTL8367D_GMACRAM_BIST_MODE_OFFSET 1 +#define RTL8367D_GMACRAM_BIST_MODE_MASK 0x2 +#define RTL8367D_GMACRAM_BIST_RSTN_OFFSET 0 +#define RTL8367D_GMACRAM_BIST_RSTN_MASK 0x1 + +#define RTL8367D_REG_BIST_GMACRAM1 0x1e40 +#define RTL8367D_BISD_CLK_SEL_OFFSET 12 +#define RTL8367D_BISD_CLK_SEL_MASK 0xF000 +#define RTL8367D_GMACRAM_LS_OFFSET 4 +#define RTL8367D_GMACRAM_LS_MASK 0x10 +#define RTL8367D_GMACRAM_TEST1_OFFSET 2 +#define RTL8367D_GMACRAM_TEST1_MASK 0xC +#define RTL8367D_GMACRAM_DIAG_CLK_OFFSET 1 +#define RTL8367D_GMACRAM_DIAG_CLK_MASK 0x2 +#define RTL8367D_GMACRAM_DIAG_MODE_OFFSET 0 +#define RTL8367D_GMACRAM_DIAG_MODE_MASK 0x1 + +#define RTL8367D_REG_BIST_GMACRAM2 0x1e41 + +#define RTL8367D_REG_BIST_GMACRAM3 0x1e42 + +#define RTL8367D_REG_BIST_GMACRAM4 0x1e43 + +#define RTL8367D_REG_BIST_GMACRAM5 0x1e44 + +#define RTL8367D_REG_BIST_GMACRAM6 0x1e45 + +#define RTL8367D_REG_BIST_GMACRAM7 0x1e46 +#define RTL8367D_GMACRAM_MEB_OFFSET 13 +#define RTL8367D_GMACRAM_MEB_MASK 0x2000 +#define RTL8367D_GMACRAM_MEA_OFFSET 12 +#define RTL8367D_GMACRAM_MEA_MASK 0x1000 +#define RTL8367D_GMACRAM_ADRA_OFFSET 0 +#define RTL8367D_GMACRAM_ADRA_MASK 0x1FF + +#define RTL8367D_REG_BIST_GMACRAM8 0x1e47 +#define RTL8367D_BIST_GMACRAM8_OFFSET 0 +#define RTL8367D_BIST_GMACRAM8_MASK 0x1FF + +#define RTL8367D_REG_RDM_SEED_SRC 0x1e48 +#define RTL8367D_RDM_SEED_SRC_OFFSET 0 +#define RTL8367D_RDM_SEED_SRC_MASK 0x3FF + +#define RTL8367D_REG_RDM_FRC_SEED_SRC 0x1e49 +#define RTL8367D_RS_FRC_MODE_OFFSET 10 +#define RTL8367D_RS_FRC_MODE_MASK 0x400 +#define RTL8367D_VAL_SELECTED_RND_SRC_OFFSET 0 +#define RTL8367D_VAL_SELECTED_RND_SRC_MASK 0x3FF + +#define RTL8367D_REG_RDM_RING_SRC_1 0x1e4a +#define RTL8367D_RDM_RING_SRC_1_OFFSET 0 +#define RTL8367D_RDM_RING_SRC_1_MASK 0x3FFF + +#define RTL8367D_REG_RDM_RING_SRC_0 0x1e4b + +#define RTL8367D_REG_RDM_FRC_RING_SRC_1 0x1e4c +#define RTL8367D_RR_FRC_MODE_OFFSET 14 +#define RTL8367D_RR_FRC_MODE_MASK 0x4000 +#define RTL8367D_VAL_SELECTED_RING_SRC_29_16_OFFSET 0 +#define RTL8367D_VAL_SELECTED_RING_SRC_29_16_MASK 0x3FFF + +#define RTL8367D_REG_RDM_FRC_RING_SRC_0 0x1e4d + +/* (16'h1f00)patch_reg */ + +#define RTL8367D_REG_INDRECT_ACCESS_CTRL 0x1f00 +#define RTL8367D_RW_OFFSET 1 +#define RTL8367D_RW_MASK 0x2 +#define RTL8367D_CMD_OFFSET 0 +#define RTL8367D_CMD_MASK 0x1 + +#define RTL8367D_REG_INDRECT_ACCESS_STATUS 0x1f01 +#define RTL8367D_INDRECT_ACCESS_STATUS_OFFSET 2 +#define RTL8367D_INDRECT_ACCESS_STATUS_MASK 0x4 + +#define RTL8367D_REG_INDRECT_ACCESS_ADDRESS 0x1f02 + +#define RTL8367D_REG_INDRECT_ACCESS_WRITE_DATA 0x1f03 + +#define RTL8367D_REG_INDRECT_ACCESS_READ_DATA 0x1f04 + +/* (16'h6100)nctl_reg */ + +#define RTL8367D_REG_NCTL_0 0x6100 +#define RTL8367D_NCTL_CPU_EN_OFFSET 12 +#define RTL8367D_NCTL_CPU_EN_MASK 0x3000 +#define RTL8367D_NCTL_PATCH_MODE_EN_OFFSET 11 +#define RTL8367D_NCTL_PATCH_MODE_EN_MASK 0x800 +#define RTL8367D_NCTL_PC_SPECIFY_EN_OFFSET 10 +#define RTL8367D_NCTL_PC_SPECIFY_EN_MASK 0x400 +#define RTL8367D_NCTL_PC_SPECIFY_OFFSET 0 +#define RTL8367D_NCTL_PC_SPECIFY_MASK 0x3FF + +#define RTL8367D_REG_NCTL_P00_0 0x6101 +#define RTL8367D_NCTL_BP_EN_P00_OFFSET 10 +#define RTL8367D_NCTL_BP_EN_P00_MASK 0x400 +#define RTL8367D_NCTL_BP_ADDR_P00_OFFSET 0 +#define RTL8367D_NCTL_BP_ADDR_P00_MASK 0x3FF + +#define RTL8367D_REG_NCTL_P00_1 0x6102 +#define RTL8367D_NCTL_P00_1_OFFSET 0 +#define RTL8367D_NCTL_P00_1_MASK 0x3FF + +#define RTL8367D_REG_NCTL_P01_0 0x6103 +#define RTL8367D_NCTL_BP_EN_P01_OFFSET 10 +#define RTL8367D_NCTL_BP_EN_P01_MASK 0x400 +#define RTL8367D_NCTL_BP_ADDR_P01_OFFSET 0 +#define RTL8367D_NCTL_BP_ADDR_P01_MASK 0x3FF + +#define RTL8367D_REG_NCTL_P01_1 0x6104 +#define RTL8367D_NCTL_P01_1_OFFSET 0 +#define RTL8367D_NCTL_P01_1_MASK 0x3FF + +#define RTL8367D_REG_NCTL_P02_0 0x6105 +#define RTL8367D_NCTL_BP_EN_P02_OFFSET 10 +#define RTL8367D_NCTL_BP_EN_P02_MASK 0x400 +#define RTL8367D_NCTL_BP_ADDR_P02_OFFSET 0 +#define RTL8367D_NCTL_BP_ADDR_P02_MASK 0x3FF + +#define RTL8367D_REG_NCTL_P02_1 0x6106 +#define RTL8367D_NCTL_P02_1_OFFSET 0 +#define RTL8367D_NCTL_P02_1_MASK 0x3FF + +#define RTL8367D_REG_NCTL_P03_0 0x6107 +#define RTL8367D_NCTL_BP_EN_P03_OFFSET 10 +#define RTL8367D_NCTL_BP_EN_P03_MASK 0x400 +#define RTL8367D_NCTL_BP_ADDR_P03_OFFSET 0 +#define RTL8367D_NCTL_BP_ADDR_P03_MASK 0x3FF + +#define RTL8367D_REG_NCTL_P03_1 0x6108 +#define RTL8367D_NCTL_P03_1_OFFSET 0 +#define RTL8367D_NCTL_P03_1_MASK 0x3FF + +#define RTL8367D_REG_NCTL_P04_0 0x6109 +#define RTL8367D_NCTL_BP_EN_P04_OFFSET 10 +#define RTL8367D_NCTL_BP_EN_P04_MASK 0x400 +#define RTL8367D_NCTL_BP_ADDR_P04_OFFSET 0 +#define RTL8367D_NCTL_BP_ADDR_P04_MASK 0x3FF + +#define RTL8367D_REG_NCTL_P04_1 0x610a +#define RTL8367D_NCTL_P04_1_OFFSET 0 +#define RTL8367D_NCTL_P04_1_MASK 0x3FF + +#define RTL8367D_REG_NCTL_P05_0 0x610b +#define RTL8367D_NCTL_BP_EN_P05_OFFSET 10 +#define RTL8367D_NCTL_BP_EN_P05_MASK 0x400 +#define RTL8367D_NCTL_BP_ADDR_P05_OFFSET 0 +#define RTL8367D_NCTL_BP_ADDR_P05_MASK 0x3FF + +#define RTL8367D_REG_NCTL_P05_1 0x610c +#define RTL8367D_NCTL_P05_1_OFFSET 0 +#define RTL8367D_NCTL_P05_1_MASK 0x3FF + +#define RTL8367D_REG_NCTL_P06_0 0x610d +#define RTL8367D_NCTL_BP_EN_P06_OFFSET 10 +#define RTL8367D_NCTL_BP_EN_P06_MASK 0x400 +#define RTL8367D_NCTL_BP_ADDR_P06_OFFSET 0 +#define RTL8367D_NCTL_BP_ADDR_P06_MASK 0x3FF + +#define RTL8367D_REG_NCTL_P06_1 0x610e +#define RTL8367D_NCTL_P06_1_OFFSET 0 +#define RTL8367D_NCTL_P06_1_MASK 0x3FF + +#define RTL8367D_REG_NCTL_P07_0 0x610f +#define RTL8367D_NCTL_BP_EN_P07_OFFSET 10 +#define RTL8367D_NCTL_BP_EN_P07_MASK 0x400 +#define RTL8367D_NCTL_BP_ADDR_P07_OFFSET 0 +#define RTL8367D_NCTL_BP_ADDR_P07_MASK 0x3FF + +#define RTL8367D_REG_NCTL_P07_1 0x6110 +#define RTL8367D_NCTL_P07_1_OFFSET 0 +#define RTL8367D_NCTL_P07_1_MASK 0x3FF + +#define RTL8367D_REG_NCTL_P08_0 0x6111 +#define RTL8367D_NCTL_BP_EN_P08_OFFSET 10 +#define RTL8367D_NCTL_BP_EN_P08_MASK 0x400 +#define RTL8367D_NCTL_BP_ADDR_P08_OFFSET 0 +#define RTL8367D_NCTL_BP_ADDR_P08_MASK 0x3FF + +#define RTL8367D_REG_NCTL_P08_1 0x6112 +#define RTL8367D_NCTL_P08_1_OFFSET 0 +#define RTL8367D_NCTL_P08_1_MASK 0x3FF + +#define RTL8367D_REG_NCTL_P09_0 0x6113 +#define RTL8367D_NCTL_BP_EN_P09_OFFSET 10 +#define RTL8367D_NCTL_BP_EN_P09_MASK 0x400 +#define RTL8367D_NCTL_BP_ADDR_P09_OFFSET 0 +#define RTL8367D_NCTL_BP_ADDR_P09_MASK 0x3FF + +#define RTL8367D_REG_NCTL_P09_1 0x6114 +#define RTL8367D_NCTL_P09_1_OFFSET 0 +#define RTL8367D_NCTL_P09_1_MASK 0x3FF + +#define RTL8367D_REG_NCTL_P10_0 0x6115 +#define RTL8367D_NCTL_BP_EN_P10_OFFSET 10 +#define RTL8367D_NCTL_BP_EN_P10_MASK 0x400 +#define RTL8367D_NCTL_BP_ADDR_P10_OFFSET 0 +#define RTL8367D_NCTL_BP_ADDR_P10_MASK 0x3FF + +#define RTL8367D_REG_NCTL_P10_1 0x6116 +#define RTL8367D_NCTL_P10_1_OFFSET 0 +#define RTL8367D_NCTL_P10_1_MASK 0x3FF + +#define RTL8367D_REG_NCTL_P11_0 0x6117 +#define RTL8367D_NCTL_BP_EN_P11_OFFSET 10 +#define RTL8367D_NCTL_BP_EN_P11_MASK 0x400 +#define RTL8367D_NCTL_BP_ADDR_P11_OFFSET 0 +#define RTL8367D_NCTL_BP_ADDR_P11_MASK 0x3FF + +#define RTL8367D_REG_NCTL_P11_1 0x6118 +#define RTL8367D_NCTL_P11_1_OFFSET 0 +#define RTL8367D_NCTL_P11_1_MASK 0x3FF + +#define RTL8367D_REG_NCTL_P12_0 0x6119 +#define RTL8367D_NCTL_BP_EN_P12_OFFSET 10 +#define RTL8367D_NCTL_BP_EN_P12_MASK 0x400 +#define RTL8367D_NCTL_BP_ADDR_P12_OFFSET 0 +#define RTL8367D_NCTL_BP_ADDR_P12_MASK 0x3FF + +#define RTL8367D_REG_NCTL_P12_1 0x611a +#define RTL8367D_NCTL_P12_1_OFFSET 0 +#define RTL8367D_NCTL_P12_1_MASK 0x3FF + +#define RTL8367D_REG_NCTL_P13_0 0x611b +#define RTL8367D_NCTL_BP_EN_P13_OFFSET 10 +#define RTL8367D_NCTL_BP_EN_P13_MASK 0x400 +#define RTL8367D_NCTL_BP_ADDR_P13_OFFSET 0 +#define RTL8367D_NCTL_BP_ADDR_P13_MASK 0x3FF + +#define RTL8367D_REG_NCTL_P13_1 0x611c +#define RTL8367D_NCTL_P13_1_OFFSET 0 +#define RTL8367D_NCTL_P13_1_MASK 0x3FF + +#define RTL8367D_REG_NCTL_P14_0 0x611d +#define RTL8367D_NCTL_BP_EN_P14_OFFSET 10 +#define RTL8367D_NCTL_BP_EN_P14_MASK 0x400 +#define RTL8367D_NCTL_BP_ADDR_P14_OFFSET 0 +#define RTL8367D_NCTL_BP_ADDR_P14_MASK 0x3FF + +#define RTL8367D_REG_NCTL_P14_1 0x611e +#define RTL8367D_NCTL_P14_1_OFFSET 0 +#define RTL8367D_NCTL_P14_1_MASK 0x3FF + +#define RTL8367D_REG_NCTL_P15_0 0x611f +#define RTL8367D_NCTL_BP_EN_P15_OFFSET 10 +#define RTL8367D_NCTL_BP_EN_P15_MASK 0x400 +#define RTL8367D_NCTL_BP_ADDR_P15_OFFSET 0 +#define RTL8367D_NCTL_BP_ADDR_P15_MASK 0x3FF + +#define RTL8367D_REG_NCTL_P15_1 0x6120 +#define RTL8367D_NCTL_P15_1_OFFSET 0 +#define RTL8367D_NCTL_P15_1_MASK 0x3FF + +#define RTL8367D_REG_NCTL_SRCA_VAL0 0x6121 + +#define RTL8367D_REG_NCTL_SRCA_VAL1 0x6122 + +#define RTL8367D_REG_NCTL_SRCA_VAL2 0x6123 + +#define RTL8367D_REG_NCTL_SRCB_VAL0 0x6124 + +#define RTL8367D_REG_NCTL_SRCB_VAL1 0x6125 + +#define RTL8367D_REG_NCTL_SRCB_VAL2 0x6126 + +#define RTL8367D_REG_NCTL_CIO_SEL 0x6127 +#define RTL8367D_NCTL_CI_SEL_OFFSET 8 +#define RTL8367D_NCTL_CI_SEL_MASK 0xFF00 +#define RTL8367D_NCTL_CO_SEL_OFFSET 0 +#define RTL8367D_NCTL_CO_SEL_MASK 0xFF + +#define RTL8367D_REG_NCTL_CO_MON 0x6128 + +#define RTL8367D_REG_NCTL_CI_MSB_MON 0x6129 + +#define RTL8367D_REG_NCTL_PC_MON 0x612a +#define RTL8367D_NCTL_PC_MON_OFFSET 0 +#define RTL8367D_NCTL_PC_MON_MASK 0x3FF + +#define RTL8367D_REG_NCTL_SRAM_IN 0x612b + +#define RTL8367D_REG_NCTL_EN 0x612f +#define RTL8367D_NCTL_RSTB_BITERR_EN_OFFSET 3 +#define RTL8367D_NCTL_RSTB_BITERR_EN_MASK 0x8 +#define RTL8367D_NCTL_EN_OFFSET 2 +#define RTL8367D_NCTL_EN_MASK 0x4 +#define RTL8367D_RG_NCTL_SEL_OFFSET 0 +#define RTL8367D_RG_NCTL_SEL_MASK 0x3 + +#define RTL8367D_REG_NCTL_CI_LSB_MON 0x6134 + +#define RTL8367D_REG_NCTL_RAM_INDACS_0 0x6135 +#define RTL8367D_NCTL_CMD_OFFSET 14 +#define RTL8367D_NCTL_CMD_MASK 0x4000 +#define RTL8367D_NCTL_WR_OFFSET 13 +#define RTL8367D_NCTL_WR_MASK 0x2000 +#define RTL8367D_NCTL_CMD_TMOUT_OFFSET 10 +#define RTL8367D_NCTL_CMD_TMOUT_MASK 0x1C00 +#define RTL8367D_NCTL_ADR_OFFSET 0 +#define RTL8367D_NCTL_ADR_MASK 0x3FF + +#define RTL8367D_REG_NCTL_RAM_INDACS_1 0x6136 + +#define RTL8367D_REG_NCTL_RAM_INDACS_2 0x6137 + +/* (16'h6200)fib_page */ + +#define RTL8367D_REG_FIB_CFG00 0x6200 +#define RTL8367D_CFG_FIB_RST_OFFSET 15 +#define RTL8367D_CFG_FIB_RST_MASK 0x8000 +#define RTL8367D_CFG_FIB_LPK_OFFSET 14 +#define RTL8367D_CFG_FIB_LPK_MASK 0x4000 +#define RTL8367D_CFG_FIB_SPD_RD_0_OFFSET 13 +#define RTL8367D_CFG_FIB_SPD_RD_0_MASK 0x2000 +#define RTL8367D_CFG_FIB_ANEN_OFFSET 12 +#define RTL8367D_CFG_FIB_ANEN_MASK 0x1000 +#define RTL8367D_CFG_FIB_PDOWN_OFFSET 11 +#define RTL8367D_CFG_FIB_PDOWN_MASK 0x800 +#define RTL8367D_CFG_FIB_ISO_OFFSET 10 +#define RTL8367D_CFG_FIB_ISO_MASK 0x400 +#define RTL8367D_CFG_FIB_RESTART_OFFSET 9 +#define RTL8367D_CFG_FIB_RESTART_MASK 0x200 +#define RTL8367D_CFG_FIB_FULLDUP_OFFSET 8 +#define RTL8367D_CFG_FIB_FULLDUP_MASK 0x100 +#define RTL8367D_CFG_FIB_SPD_RD_1_OFFSET 6 +#define RTL8367D_CFG_FIB_SPD_RD_1_MASK 0x40 +#define RTL8367D_CFG_FIB_FRCTX_OFFSET 5 +#define RTL8367D_CFG_FIB_FRCTX_MASK 0x20 + +#define RTL8367D_REG_FIB_CFG01 0x6201 +#define RTL8367D_CAPBILITY_OFFSET 6 +#define RTL8367D_CAPBILITY_MASK 0xFFC0 +#define RTL8367D_AN_COMPLETE_OFFSET 5 +#define RTL8367D_AN_COMPLETE_MASK 0x20 +#define RTL8367D_R_FAULT_OFFSET 4 +#define RTL8367D_R_FAULT_MASK 0x10 +#define RTL8367D_NWAY_ABILITY_OFFSET 3 +#define RTL8367D_NWAY_ABILITY_MASK 0x8 +#define RTL8367D_LINK_STATUS_OFFSET 2 +#define RTL8367D_LINK_STATUS_MASK 0x4 +#define RTL8367D_JABBER_DETECT_OFFSET 1 +#define RTL8367D_JABBER_DETECT_MASK 0x2 +#define RTL8367D_EXTENDED_CAPBILITY_OFFSET 0 +#define RTL8367D_EXTENDED_CAPBILITY_MASK 0x1 + +#define RTL8367D_REG_FIB_CFG02 0x6202 + +#define RTL8367D_REG_FIB_CFG03 0x6203 +#define RTL8367D_REALTEK_OUI5_0_OFFSET 10 +#define RTL8367D_REALTEK_OUI5_0_MASK 0xFC00 +#define RTL8367D_MODEL_NO_OFFSET 4 +#define RTL8367D_MODEL_NO_MASK 0x3F0 +#define RTL8367D_REVISION_NO_OFFSET 0 +#define RTL8367D_REVISION_NO_MASK 0xF + +#define RTL8367D_REG_FIB_CFG04 0x6204 + +#define RTL8367D_REG_FIB_CFG05 0x6205 + +#define RTL8367D_REG_FIB_CFG06 0x6206 +#define RTL8367D_FIB_NP_EN_OFFSET 2 +#define RTL8367D_FIB_NP_EN_MASK 0x4 +#define RTL8367D_RXPAGE_OFFSET 1 +#define RTL8367D_RXPAGE_MASK 0x2 + +#define RTL8367D_REG_FIB_CFG07 0x6207 + +#define RTL8367D_REG_FIB_CFG08 0x6208 + +#define RTL8367D_REG_FIB_CFG09 0x6209 + +#define RTL8367D_REG_FIB_CFG10 0x620a + +#define RTL8367D_REG_FIB_CFG11 0x620b + +#define RTL8367D_REG_FIB_CFG12 0x620c + +#define RTL8367D_REG_FIB_CFG13 0x620d +#define RTL8367D_INDR_FUNC_OFFSET 14 +#define RTL8367D_INDR_FUNC_MASK 0xC000 +#define RTL8367D_FIB_CFG13_DUMMY_OFFSET 5 +#define RTL8367D_FIB_CFG13_DUMMY_MASK 0x3FE0 +#define RTL8367D_INDR_DEVAD_OFFSET 0 +#define RTL8367D_INDR_DEVAD_MASK 0x1F + +#define RTL8367D_REG_FIB_CFG14 0x620e + +#define RTL8367D_REG_FIB_CFG15 0x620f + +/* (16'h6500)SWR_reg */ + +#define RTL8367D_REG_SWR_REG0 0x6500 + +#define RTL8367D_REG_SWR_REG1 0x6501 + +#define RTL8367D_REG_SWR_REG2 0x6502 + +#define RTL8367D_REG_SWR_REG3 0x6503 + +#define RTL8367D_REG_SWR_REG4 0x6504 + +#define RTL8367D_REG_SWR_REG5 0x6505 + +/* (16'h6600)sds_indacs_reg */ + +#define RTL8367D_REG_SDS_INDACS_CMD 0x6600 +#define RTL8367D_SDS_CMD_BUSY_OFFSET 8 +#define RTL8367D_SDS_CMD_BUSY_MASK 0x100 +#define RTL8367D_SDS_CMD_OFFSET 7 +#define RTL8367D_SDS_CMD_MASK 0x80 +#define RTL8367D_SDS_RWOP_OFFSET 6 +#define RTL8367D_SDS_RWOP_MASK 0x40 +#define RTL8367D_SDS_INDEX_OFFSET 0 +#define RTL8367D_SDS_INDEX_MASK 0x3F + +#define RTL8367D_REG_SDS_INDACS_ADR 0x6601 +#define RTL8367D_SDS_PAGE_OFFSET 5 +#define RTL8367D_SDS_PAGE_MASK 0x7E0 +#define RTL8367D_SDS_REGAD_OFFSET 0 +#define RTL8367D_SDS_REGAD_MASK 0x1F + +#define RTL8367D_REG_SDS_INDACS_DATA 0x6602 + +/* (16'h6700)bist_reg */ + +#define RTL8367D_REG_BIST_TCAM 0x6700 +#define RTL8367D_TCAM_DRF_BIST_FAIL_OFFSET 15 +#define RTL8367D_TCAM_DRF_BIST_FAIL_MASK 0x8000 +#define RTL8367D_TCAM_BIST_FAIL_OFFSET 14 +#define RTL8367D_TCAM_BIST_FAIL_MASK 0x4000 +#define RTL8367D_TCAM_DRF_BIST_DONE_OFFSET 13 +#define RTL8367D_TCAM_DRF_BIST_DONE_MASK 0x2000 +#define RTL8367D_TCAM_BIST_DONE_OFFSET 12 +#define RTL8367D_TCAM_BIST_DONE_MASK 0x1000 +#define RTL8367D_TCAM_DRF_START_PAUSE_OFFSET 11 +#define RTL8367D_TCAM_DRF_START_PAUSE_MASK 0x800 +#define RTL8367D_TCAM_DRF_TEST_RESUME_OFFSET 3 +#define RTL8367D_TCAM_DRF_TEST_RESUME_MASK 0x8 +#define RTL8367D_TCAM_DRF_BIST_MODE_OFFSET 2 +#define RTL8367D_TCAM_DRF_BIST_MODE_MASK 0x4 +#define RTL8367D_TCAM_BIST_MODE_OFFSET 1 +#define RTL8367D_TCAM_BIST_MODE_MASK 0x2 +#define RTL8367D_TCAM_BIST_RSTN_OFFSET 0 +#define RTL8367D_TCAM_BIST_RSTN_MASK 0x1 + +#define RTL8367D_REG_BIST_L2 0x6701 +#define RTL8367D_L2_DRF_BIST_FAIL_OFFSET 15 +#define RTL8367D_L2_DRF_BIST_FAIL_MASK 0x8000 +#define RTL8367D_L2_BIST_FAIL_OFFSET 14 +#define RTL8367D_L2_BIST_FAIL_MASK 0x4000 +#define RTL8367D_L2_DRF_BIST_DONE_OFFSET 13 +#define RTL8367D_L2_DRF_BIST_DONE_MASK 0x2000 +#define RTL8367D_L2_BIST_DONE_OFFSET 12 +#define RTL8367D_L2_BIST_DONE_MASK 0x1000 +#define RTL8367D_L2_DRF_START_PAUSE_OFFSET 11 +#define RTL8367D_L2_DRF_START_PAUSE_MASK 0x800 +#define RTL8367D_L2_DYN_READ_EN_OFFSET 10 +#define RTL8367D_L2_DYN_READ_EN_MASK 0x400 +#define RTL8367D_L2_BIST_LOOP_MODE_OFFSET 9 +#define RTL8367D_L2_BIST_LOOP_MODE_MASK 0x200 +#define RTL8367D_L2_RME_OFFSET 8 +#define RTL8367D_L2_RME_MASK 0x100 +#define RTL8367D_L2_RM_OFFSET 4 +#define RTL8367D_L2_RM_MASK 0xF0 +#define RTL8367D_L2_DRF_TEST_RESUME_OFFSET 3 +#define RTL8367D_L2_DRF_TEST_RESUME_MASK 0x8 +#define RTL8367D_L2_DRF_BIST_MODE_OFFSET 2 +#define RTL8367D_L2_DRF_BIST_MODE_MASK 0x4 +#define RTL8367D_L2_BIST_MODE_OFFSET 1 +#define RTL8367D_L2_BIST_MODE_MASK 0x2 +#define RTL8367D_L2_BIST_RSTN_OFFSET 0 +#define RTL8367D_L2_BIST_RSTN_MASK 0x1 + +#define RTL8367D_REG_BIST_OUTQ 0x6702 +#define RTL8367D_OUTQ_DRF_BIST_FAIL_OFFSET 15 +#define RTL8367D_OUTQ_DRF_BIST_FAIL_MASK 0x8000 +#define RTL8367D_OUTQ_BIST_FAIL_OFFSET 14 +#define RTL8367D_OUTQ_BIST_FAIL_MASK 0x4000 +#define RTL8367D_OUTQ_DRF_BIST_DONE_OFFSET 13 +#define RTL8367D_OUTQ_DRF_BIST_DONE_MASK 0x2000 +#define RTL8367D_OUTQ_BIST_DONE_OFFSET 12 +#define RTL8367D_OUTQ_BIST_DONE_MASK 0x1000 +#define RTL8367D_OUTQ_DRF_START_PAUSE_OFFSET 11 +#define RTL8367D_OUTQ_DRF_START_PAUSE_MASK 0x800 +#define RTL8367D_OUTQ_DYN_READ_EN_OFFSET 10 +#define RTL8367D_OUTQ_DYN_READ_EN_MASK 0x400 +#define RTL8367D_OUTQ_BIST_LOOP_MODE_OFFSET 9 +#define RTL8367D_OUTQ_BIST_LOOP_MODE_MASK 0x200 +#define RTL8367D_OUTQ_RME_OFFSET 8 +#define RTL8367D_OUTQ_RME_MASK 0x100 +#define RTL8367D_OUTQ_RM_OFFSET 4 +#define RTL8367D_OUTQ_RM_MASK 0xF0 +#define RTL8367D_OUTQ_DRF_TEST_RESUME_OFFSET 3 +#define RTL8367D_OUTQ_DRF_TEST_RESUME_MASK 0x8 +#define RTL8367D_OUTQ_DRF_BIST_MODE_OFFSET 2 +#define RTL8367D_OUTQ_DRF_BIST_MODE_MASK 0x4 +#define RTL8367D_OUTQ_BIST_MODE_OFFSET 1 +#define RTL8367D_OUTQ_BIST_MODE_MASK 0x2 +#define RTL8367D_OUTQ_BIST_RSTN_OFFSET 0 +#define RTL8367D_OUTQ_BIST_RSTN_MASK 0x1 + +#define RTL8367D_REG_BIST_PB 0x6703 +#define RTL8367D_PB_DRF_BIST_FAIL_OFFSET 15 +#define RTL8367D_PB_DRF_BIST_FAIL_MASK 0x8000 +#define RTL8367D_PB_BIST_FAIL_OFFSET 14 +#define RTL8367D_PB_BIST_FAIL_MASK 0x4000 +#define RTL8367D_PB_DRF_BIST_DONE_OFFSET 13 +#define RTL8367D_PB_DRF_BIST_DONE_MASK 0x2000 +#define RTL8367D_PB_BIST_DONE_OFFSET 12 +#define RTL8367D_PB_BIST_DONE_MASK 0x1000 +#define RTL8367D_PB_DRF_START_PAUSE_OFFSET 11 +#define RTL8367D_PB_DRF_START_PAUSE_MASK 0x800 +#define RTL8367D_PB_DYN_READ_EN_OFFSET 10 +#define RTL8367D_PB_DYN_READ_EN_MASK 0x400 +#define RTL8367D_PB_BIST_LOOP_MODE_OFFSET 9 +#define RTL8367D_PB_BIST_LOOP_MODE_MASK 0x200 +#define RTL8367D_PB_RME_OFFSET 8 +#define RTL8367D_PB_RME_MASK 0x100 +#define RTL8367D_PB_RM_OFFSET 4 +#define RTL8367D_PB_RM_MASK 0xF0 +#define RTL8367D_PB_DRF_TEST_RESUME_OFFSET 3 +#define RTL8367D_PB_DRF_TEST_RESUME_MASK 0x8 +#define RTL8367D_PB_DRF_BIST_MODE_OFFSET 2 +#define RTL8367D_PB_DRF_BIST_MODE_MASK 0x4 +#define RTL8367D_PB_BIST_MODE_OFFSET 1 +#define RTL8367D_PB_BIST_MODE_MASK 0x2 +#define RTL8367D_PB_BIST_RSTN_OFFSET 0 +#define RTL8367D_PB_BIST_RSTN_MASK 0x1 + +#define RTL8367D_REG_BIST_ACT 0x6704 +#define RTL8367D_ACT_DRF_BIST_FAIL_OFFSET 15 +#define RTL8367D_ACT_DRF_BIST_FAIL_MASK 0x8000 +#define RTL8367D_ACT_BIST_FAIL_OFFSET 14 +#define RTL8367D_ACT_BIST_FAIL_MASK 0x4000 +#define RTL8367D_ACT_DRF_BIST_DONE_OFFSET 13 +#define RTL8367D_ACT_DRF_BIST_DONE_MASK 0x2000 +#define RTL8367D_ACT_BIST_DONE_OFFSET 12 +#define RTL8367D_ACT_BIST_DONE_MASK 0x1000 +#define RTL8367D_ACT_DRF_START_PAUSE_OFFSET 11 +#define RTL8367D_ACT_DRF_START_PAUSE_MASK 0x800 +#define RTL8367D_ACT_DYN_READ_EN_OFFSET 10 +#define RTL8367D_ACT_DYN_READ_EN_MASK 0x400 +#define RTL8367D_ACT_BIST_LOOP_MODE_OFFSET 9 +#define RTL8367D_ACT_BIST_LOOP_MODE_MASK 0x200 +#define RTL8367D_ACT_RME_OFFSET 8 +#define RTL8367D_ACT_RME_MASK 0x100 +#define RTL8367D_ACT_RM_OFFSET 4 +#define RTL8367D_ACT_RM_MASK 0xF0 +#define RTL8367D_ACT_DRF_TEST_RESUME_OFFSET 3 +#define RTL8367D_ACT_DRF_TEST_RESUME_MASK 0x8 +#define RTL8367D_ACT_DRF_BIST_MODE_OFFSET 2 +#define RTL8367D_ACT_DRF_BIST_MODE_MASK 0x4 +#define RTL8367D_ACT_BIST_MODE_OFFSET 1 +#define RTL8367D_ACT_BIST_MODE_MASK 0x2 +#define RTL8367D_ACT_BIST_RSTN_OFFSET 0 +#define RTL8367D_ACT_BIST_RSTN_MASK 0x1 + +#define RTL8367D_REG_BIST_HT 0x6705 +#define RTL8367D_HT_DRF_BIST_FAIL_OFFSET 15 +#define RTL8367D_HT_DRF_BIST_FAIL_MASK 0x8000 +#define RTL8367D_HT_BIST_FAIL_OFFSET 14 +#define RTL8367D_HT_BIST_FAIL_MASK 0x4000 +#define RTL8367D_HT_DRF_BIST_DONE_OFFSET 13 +#define RTL8367D_HT_DRF_BIST_DONE_MASK 0x2000 +#define RTL8367D_HT_BIST_DONE_OFFSET 12 +#define RTL8367D_HT_BIST_DONE_MASK 0x1000 +#define RTL8367D_HT_DRF_START_PAUSE_OFFSET 11 +#define RTL8367D_HT_DRF_START_PAUSE_MASK 0x800 +#define RTL8367D_HT_DYN_READ_EN_OFFSET 10 +#define RTL8367D_HT_DYN_READ_EN_MASK 0x400 +#define RTL8367D_HT_BIST_LOOP_MODE_OFFSET 9 +#define RTL8367D_HT_BIST_LOOP_MODE_MASK 0x200 +#define RTL8367D_HT_RME_OFFSET 8 +#define RTL8367D_HT_RME_MASK 0x100 +#define RTL8367D_HT_RM_OFFSET 4 +#define RTL8367D_HT_RM_MASK 0xF0 +#define RTL8367D_HT_DRF_TEST_RESUME_OFFSET 3 +#define RTL8367D_HT_DRF_TEST_RESUME_MASK 0x8 +#define RTL8367D_HT_DRF_BIST_MODE_OFFSET 2 +#define RTL8367D_HT_DRF_BIST_MODE_MASK 0x4 +#define RTL8367D_HT_BIST_MODE_OFFSET 1 +#define RTL8367D_HT_BIST_MODE_MASK 0x2 +#define RTL8367D_HT_BIST_RSTN_OFFSET 0 +#define RTL8367D_HT_BIST_RSTN_MASK 0x1 + +#define RTL8367D_REG_BIST_MIB 0x6706 +#define RTL8367D_MIB_DRF_BIST_FAIL_OFFSET 15 +#define RTL8367D_MIB_DRF_BIST_FAIL_MASK 0x8000 +#define RTL8367D_MIB_BIST_FAIL_OFFSET 14 +#define RTL8367D_MIB_BIST_FAIL_MASK 0x4000 +#define RTL8367D_MIB_DRF_BIST_DONE_OFFSET 13 +#define RTL8367D_MIB_DRF_BIST_DONE_MASK 0x2000 +#define RTL8367D_MIB_BIST_DONE_OFFSET 12 +#define RTL8367D_MIB_BIST_DONE_MASK 0x1000 +#define RTL8367D_MIB_DRF_START_PAUSE_OFFSET 11 +#define RTL8367D_MIB_DRF_START_PAUSE_MASK 0x800 +#define RTL8367D_MIB_DYN_READ_EN_OFFSET 10 +#define RTL8367D_MIB_DYN_READ_EN_MASK 0x400 +#define RTL8367D_MIB_BIST_LOOP_MODE_OFFSET 9 +#define RTL8367D_MIB_BIST_LOOP_MODE_MASK 0x200 +#define RTL8367D_MIB_RME_OFFSET 8 +#define RTL8367D_MIB_RME_MASK 0x100 +#define RTL8367D_MIB_RM_OFFSET 4 +#define RTL8367D_MIB_RM_MASK 0xF0 +#define RTL8367D_MIB_DRF_TEST_RESUME_OFFSET 3 +#define RTL8367D_MIB_DRF_TEST_RESUME_MASK 0x8 +#define RTL8367D_MIB_DRF_BIST_MODE_OFFSET 2 +#define RTL8367D_MIB_DRF_BIST_MODE_MASK 0x4 +#define RTL8367D_MIB_BIST_MODE_OFFSET 1 +#define RTL8367D_MIB_BIST_MODE_MASK 0x2 +#define RTL8367D_MIB_BIST_RSTN_OFFSET 0 +#define RTL8367D_MIB_BIST_RSTN_MASK 0x1 + +#define RTL8367D_REG_BIST_CVLAN 0x6707 +#define RTL8367D_CVLAN_DRF_BIST_FAIL_OFFSET 15 +#define RTL8367D_CVLAN_DRF_BIST_FAIL_MASK 0x8000 +#define RTL8367D_CVLAN_BIST_FAIL_OFFSET 14 +#define RTL8367D_CVLAN_BIST_FAIL_MASK 0x4000 +#define RTL8367D_CVLAN_DRF_BIST_DONE_OFFSET 13 +#define RTL8367D_CVLAN_DRF_BIST_DONE_MASK 0x2000 +#define RTL8367D_CVLAN_BIST_DONE_OFFSET 12 +#define RTL8367D_CVLAN_BIST_DONE_MASK 0x1000 +#define RTL8367D_CVLAN_DRF_START_PAUSE_OFFSET 11 +#define RTL8367D_CVLAN_DRF_START_PAUSE_MASK 0x800 +#define RTL8367D_CVLAN_DYN_READ_EN_OFFSET 10 +#define RTL8367D_CVLAN_DYN_READ_EN_MASK 0x400 +#define RTL8367D_CVLAN_BIST_LOOP_MODE_OFFSET 9 +#define RTL8367D_CVLAN_BIST_LOOP_MODE_MASK 0x200 +#define RTL8367D_CVLAN_RME_OFFSET 8 +#define RTL8367D_CVLAN_RME_MASK 0x100 +#define RTL8367D_CVLAN_RM_OFFSET 4 +#define RTL8367D_CVLAN_RM_MASK 0xF0 +#define RTL8367D_CVLAN_DRF_TEST_RESUME_OFFSET 3 +#define RTL8367D_CVLAN_DRF_TEST_RESUME_MASK 0x8 +#define RTL8367D_CVLAN_DRF_BIST_MODE_OFFSET 2 +#define RTL8367D_CVLAN_DRF_BIST_MODE_MASK 0x4 +#define RTL8367D_CVLAN_BIST_MODE_OFFSET 1 +#define RTL8367D_CVLAN_BIST_MODE_MASK 0x2 +#define RTL8367D_CVLAN_BIST_RSTN_OFFSET 0 +#define RTL8367D_CVLAN_BIST_RSTN_MASK 0x1 + +#define RTL8367D_REG_BIST_HSACTRL 0x6708 +#define RTL8367D_HSACTRL_DRF_BIST_FAIL_OFFSET 15 +#define RTL8367D_HSACTRL_DRF_BIST_FAIL_MASK 0x8000 +#define RTL8367D_HSACTRL_BIST_FAIL_OFFSET 14 +#define RTL8367D_HSACTRL_BIST_FAIL_MASK 0x4000 +#define RTL8367D_HSACTRL_DRF_BIST_DONE_OFFSET 13 +#define RTL8367D_HSACTRL_DRF_BIST_DONE_MASK 0x2000 +#define RTL8367D_HSACTRL_BIST_DONE_OFFSET 12 +#define RTL8367D_HSACTRL_BIST_DONE_MASK 0x1000 +#define RTL8367D_HSACTRL_DRF_START_PAUSE_OFFSET 11 +#define RTL8367D_HSACTRL_DRF_START_PAUSE_MASK 0x800 +#define RTL8367D_HSACTRL_DYN_READ_EN_OFFSET 10 +#define RTL8367D_HSACTRL_DYN_READ_EN_MASK 0x400 +#define RTL8367D_HSACTRL_BIST_LOOP_MODE_OFFSET 9 +#define RTL8367D_HSACTRL_BIST_LOOP_MODE_MASK 0x200 +#define RTL8367D_HSACTRL_RME_OFFSET 8 +#define RTL8367D_HSACTRL_RME_MASK 0x100 +#define RTL8367D_HSACTRL_RM_OFFSET 4 +#define RTL8367D_HSACTRL_RM_MASK 0xF0 +#define RTL8367D_HSACTRL_DRF_TEST_RESUME_OFFSET 3 +#define RTL8367D_HSACTRL_DRF_TEST_RESUME_MASK 0x8 +#define RTL8367D_HSACTRL_DRF_BIST_MODE_OFFSET 2 +#define RTL8367D_HSACTRL_DRF_BIST_MODE_MASK 0x4 +#define RTL8367D_HSACTRL_BIST_MODE_OFFSET 1 +#define RTL8367D_HSACTRL_BIST_MODE_MASK 0x2 +#define RTL8367D_HSACTRL_BIST_RSTN_OFFSET 0 +#define RTL8367D_HSACTRL_BIST_RSTN_MASK 0x1 + +#define RTL8367D_REG_BIST_ERAM 0x6709 +#define RTL8367D_ERAM_DRF_BIST_FAIL_OFFSET 15 +#define RTL8367D_ERAM_DRF_BIST_FAIL_MASK 0x8000 +#define RTL8367D_ERAM_BIST_FAIL_OFFSET 14 +#define RTL8367D_ERAM_BIST_FAIL_MASK 0x4000 +#define RTL8367D_ERAM_DRF_BIST_DONE_OFFSET 13 +#define RTL8367D_ERAM_DRF_BIST_DONE_MASK 0x2000 +#define RTL8367D_ERAM_BIST_DONE_OFFSET 12 +#define RTL8367D_ERAM_BIST_DONE_MASK 0x1000 +#define RTL8367D_ERAM_DRF_START_PAUSE_OFFSET 11 +#define RTL8367D_ERAM_DRF_START_PAUSE_MASK 0x800 +#define RTL8367D_ERAM_DYN_READ_EN_OFFSET 10 +#define RTL8367D_ERAM_DYN_READ_EN_MASK 0x400 +#define RTL8367D_ERAM_BIST_LOOP_MODE_OFFSET 9 +#define RTL8367D_ERAM_BIST_LOOP_MODE_MASK 0x200 +#define RTL8367D_ERAM_RME_OFFSET 8 +#define RTL8367D_ERAM_RME_MASK 0x100 +#define RTL8367D_ERAM_RM_OFFSET 4 +#define RTL8367D_ERAM_RM_MASK 0xF0 +#define RTL8367D_ERAM_DRF_TEST_RESUME_OFFSET 3 +#define RTL8367D_ERAM_DRF_TEST_RESUME_MASK 0x8 +#define RTL8367D_ERAM_DRF_BIST_MODE_OFFSET 2 +#define RTL8367D_ERAM_DRF_BIST_MODE_MASK 0x4 +#define RTL8367D_ERAM_BIST_MODE_OFFSET 1 +#define RTL8367D_ERAM_BIST_MODE_MASK 0x2 +#define RTL8367D_ERAM_BIST_RSTN_OFFSET 0 +#define RTL8367D_ERAM_BIST_RSTN_MASK 0x1 + +#define RTL8367D_REG_BIST_IRAM 0x670a +#define RTL8367D_IRAM_DRF_BIST_FAIL_OFFSET 15 +#define RTL8367D_IRAM_DRF_BIST_FAIL_MASK 0x8000 +#define RTL8367D_IRAM_BIST_FAIL_OFFSET 14 +#define RTL8367D_IRAM_BIST_FAIL_MASK 0x4000 +#define RTL8367D_IRAM_DRF_BIST_DONE_OFFSET 13 +#define RTL8367D_IRAM_DRF_BIST_DONE_MASK 0x2000 +#define RTL8367D_IRAM_BIST_DONE_OFFSET 12 +#define RTL8367D_IRAM_BIST_DONE_MASK 0x1000 +#define RTL8367D_IRAM_DRF_START_PAUSE_OFFSET 11 +#define RTL8367D_IRAM_DRF_START_PAUSE_MASK 0x800 +#define RTL8367D_IRAM_DYN_READ_EN_OFFSET 10 +#define RTL8367D_IRAM_DYN_READ_EN_MASK 0x400 +#define RTL8367D_IRAM_BIST_LOOP_MODE_OFFSET 9 +#define RTL8367D_IRAM_BIST_LOOP_MODE_MASK 0x200 +#define RTL8367D_IRAM_RME_OFFSET 8 +#define RTL8367D_IRAM_RME_MASK 0x100 +#define RTL8367D_IRAM_RM_OFFSET 4 +#define RTL8367D_IRAM_RM_MASK 0xF0 +#define RTL8367D_IRAM_DRF_TEST_RESUME_OFFSET 3 +#define RTL8367D_IRAM_DRF_TEST_RESUME_MASK 0x8 +#define RTL8367D_IRAM_DRF_BIST_MODE_OFFSET 2 +#define RTL8367D_IRAM_DRF_BIST_MODE_MASK 0x4 +#define RTL8367D_IRAM_BIST_MODE_OFFSET 1 +#define RTL8367D_IRAM_BIST_MODE_MASK 0x2 +#define RTL8367D_IRAM_BIST_RSTN_OFFSET 0 +#define RTL8367D_IRAM_BIST_RSTN_MASK 0x1 + +#define RTL8367D_REG_BIST_IROM 0x670b +#define RTL8367D_IROM_DRF_BIST_FAIL_OFFSET 15 +#define RTL8367D_IROM_DRF_BIST_FAIL_MASK 0x8000 +#define RTL8367D_IROM_BIST_FAIL_OFFSET 14 +#define RTL8367D_IROM_BIST_FAIL_MASK 0x4000 +#define RTL8367D_IROM_DRF_BIST_DONE_OFFSET 13 +#define RTL8367D_IROM_DRF_BIST_DONE_MASK 0x2000 +#define RTL8367D_IROM_BIST_DONE_OFFSET 12 +#define RTL8367D_IROM_BIST_DONE_MASK 0x1000 +#define RTL8367D_IROM_DRF_START_PAUSE_OFFSET 11 +#define RTL8367D_IROM_DRF_START_PAUSE_MASK 0x800 +#define RTL8367D_IROM_DYN_READ_EN_OFFSET 10 +#define RTL8367D_IROM_DYN_READ_EN_MASK 0x400 +#define RTL8367D_IROM_BIST_LOOP_MODE_OFFSET 9 +#define RTL8367D_IROM_BIST_LOOP_MODE_MASK 0x200 +#define RTL8367D_IROM_RME_OFFSET 8 +#define RTL8367D_IROM_RME_MASK 0x100 +#define RTL8367D_IROM_RM_OFFSET 4 +#define RTL8367D_IROM_RM_MASK 0xF0 +#define RTL8367D_IROM_DRF_TEST_RESUME_OFFSET 3 +#define RTL8367D_IROM_DRF_TEST_RESUME_MASK 0x8 +#define RTL8367D_IROM_DRF_BIST_MODE_OFFSET 2 +#define RTL8367D_IROM_DRF_BIST_MODE_MASK 0x4 +#define RTL8367D_IROM_BIST_MODE_OFFSET 1 +#define RTL8367D_IROM_BIST_MODE_MASK 0x2 +#define RTL8367D_IROM_BIST_RSTN_OFFSET 0 +#define RTL8367D_IROM_BIST_RSTN_MASK 0x1 + +#define RTL8367D_REG_BIST_NCTLRAM 0x670c +#define RTL8367D_NCTLRAM_DRF_BIST_FAIL_OFFSET 15 +#define RTL8367D_NCTLRAM_DRF_BIST_FAIL_MASK 0x8000 +#define RTL8367D_NCTLRAM_BIST_FAIL_OFFSET 14 +#define RTL8367D_NCTLRAM_BIST_FAIL_MASK 0x4000 +#define RTL8367D_NCTLRAM_DRF_BIST_DONE_OFFSET 13 +#define RTL8367D_NCTLRAM_DRF_BIST_DONE_MASK 0x2000 +#define RTL8367D_NCTLRAM_BIST_DONE_OFFSET 12 +#define RTL8367D_NCTLRAM_BIST_DONE_MASK 0x1000 +#define RTL8367D_NCTLRAM_DRF_START_PAUSE_OFFSET 11 +#define RTL8367D_NCTLRAM_DRF_START_PAUSE_MASK 0x800 +#define RTL8367D_NCTLRAM_DYN_READ_EN_OFFSET 10 +#define RTL8367D_NCTLRAM_DYN_READ_EN_MASK 0x400 +#define RTL8367D_NCTLRAM_BIST_LOOP_MODE_OFFSET 9 +#define RTL8367D_NCTLRAM_BIST_LOOP_MODE_MASK 0x200 +#define RTL8367D_NCTLRAM_RME_OFFSET 8 +#define RTL8367D_NCTLRAM_RME_MASK 0x100 +#define RTL8367D_NCTLRAM_RM_OFFSET 4 +#define RTL8367D_NCTLRAM_RM_MASK 0xF0 +#define RTL8367D_NCTLRAM_DRF_TEST_RESUME_OFFSET 3 +#define RTL8367D_NCTLRAM_DRF_TEST_RESUME_MASK 0x8 +#define RTL8367D_NCTLRAM_DRF_BIST_MODE_OFFSET 2 +#define RTL8367D_NCTLRAM_DRF_BIST_MODE_MASK 0x4 +#define RTL8367D_NCTLRAM_BIST_MODE_OFFSET 1 +#define RTL8367D_NCTLRAM_BIST_MODE_MASK 0x2 +#define RTL8367D_NCTLRAM_BIST_RSTN_OFFSET 0 +#define RTL8367D_NCTLRAM_BIST_RSTN_MASK 0x1 + +#define RTL8367D_REG_BIST_NCTLROM 0x670d +#define RTL8367D_NCTLROM_BIST_FAIL_OFFSET 14 +#define RTL8367D_NCTLROM_BIST_FAIL_MASK 0x4000 +#define RTL8367D_NCTLROM_BIST_DONE_OFFSET 12 +#define RTL8367D_NCTLROM_BIST_DONE_MASK 0x1000 +#define RTL8367D_NCTLROM_BIST_LOOP_MODE_OFFSET 9 +#define RTL8367D_NCTLROM_BIST_LOOP_MODE_MASK 0x200 +#define RTL8367D_NCTLROM_RME_OFFSET 8 +#define RTL8367D_NCTLROM_RME_MASK 0x100 +#define RTL8367D_NCTLROM_RM_OFFSET 4 +#define RTL8367D_NCTLROM_RM_MASK 0xF0 +#define RTL8367D_NCTLROM_BIST_MODE_OFFSET 1 +#define RTL8367D_NCTLROM_BIST_MODE_MASK 0x2 +#define RTL8367D_NCTLROM_BIST_RSTN_OFFSET 0 +#define RTL8367D_NCTLROM_BIST_RSTN_MASK 0x1 + +#define RTL8367D_REG_SET_MISR_LSB 0x6710 + +#define RTL8367D_REG_SET_MISR_MSB 0x6711 + +#define RTL8367D_REG_GET_MISR_LSB 0x6712 + +#define RTL8367D_REG_GET_MISR_MSB 0x6713 + +#define RTL8367D_REG_BIST_GRP_L2 0x6714 +#define RTL8367D_BIST_GRP_L2_OFFSET 0 +#define RTL8367D_BIST_GRP_L2_MASK 0xF + +#define RTL8367D_REG_BIST_GRP_OUTQ 0x6715 +#define RTL8367D_BIST_GRP_OUTQ_OFFSET 0 +#define RTL8367D_BIST_GRP_OUTQ_MASK 0x7F + +#define RTL8367D_REG_BIST_GRP_PB 0x6716 +#define RTL8367D_BIST_GRP_PB_OFFSET 0 +#define RTL8367D_BIST_GRP_PB_MASK 0xFF + +#define RTL8367D_REG_BIST_FAIL_L2 0x6717 +#define RTL8367D_BIST_FAIL_L2_OFFSET 0 +#define RTL8367D_BIST_FAIL_L2_MASK 0xF + +#define RTL8367D_REG_BIST_FAIL_OUTQ 0x6718 +#define RTL8367D_BIST_FAIL_OUTQ_OFFSET 0 +#define RTL8367D_BIST_FAIL_OUTQ_MASK 0x7F + +#define RTL8367D_REG_BIST_FAIL_PB 0x6719 +#define RTL8367D_BIST_FAIL_PB_OFFSET 0 +#define RTL8367D_BIST_FAIL_PB_MASK 0xFF + +#define RTL8367D_REG_BIST_DRF_FAIL_L2 0x671a +#define RTL8367D_BIST_DRF_FAIL_L2_OFFSET 0 +#define RTL8367D_BIST_DRF_FAIL_L2_MASK 0xF + +#define RTL8367D_REG_BIST_DRF_FAIL_OUTQ 0x671b +#define RTL8367D_BIST_DRF_FAIL_OUTQ_OFFSET 0 +#define RTL8367D_BIST_DRF_FAIL_OUTQ_MASK 0x7F + +#define RTL8367D_REG_BIST_DRF_FAIL_PB 0x671c +#define RTL8367D_BIST_DRF_FAIL_PB_OFFSET 0 +#define RTL8367D_BIST_DRF_FAIL_PB_MASK 0xFF + +#define RTL8367D_REG_BIST_CFG_LS 0x671d +#define RTL8367D_NCTLROM_LS_OFFSET 13 +#define RTL8367D_NCTLROM_LS_MASK 0x2000 +#define RTL8367D_NCTLRAM_LS_OFFSET 12 +#define RTL8367D_NCTLRAM_LS_MASK 0x1000 +#define RTL8367D_IROM_LS_OFFSET 11 +#define RTL8367D_IROM_LS_MASK 0x800 +#define RTL8367D_IRAM_LS_OFFSET 10 +#define RTL8367D_IRAM_LS_MASK 0x400 +#define RTL8367D_ERAM_LS_OFFSET 9 +#define RTL8367D_ERAM_LS_MASK 0x200 +#define RTL8367D_HSACTRL_LS_OFFSET 8 +#define RTL8367D_HSACTRL_LS_MASK 0x100 +#define RTL8367D_CVLAN_LS_OFFSET 7 +#define RTL8367D_CVLAN_LS_MASK 0x80 +#define RTL8367D_MIB_LS_OFFSET 6 +#define RTL8367D_MIB_LS_MASK 0x40 +#define RTL8367D_HT_LS_OFFSET 5 +#define RTL8367D_HT_LS_MASK 0x20 +#define RTL8367D_ACT_LS_OFFSET 4 +#define RTL8367D_ACT_LS_MASK 0x10 +#define RTL8367D_PB_LS_OFFSET 3 +#define RTL8367D_PB_LS_MASK 0x8 +#define RTL8367D_OUTQ_LS_OFFSET 2 +#define RTL8367D_OUTQ_LS_MASK 0x4 +#define RTL8367D_L2_LS_OFFSET 1 +#define RTL8367D_L2_LS_MASK 0x2 + +#define RTL8367D_REG_BIST_CFG_TEST1 0x671e +#define RTL8367D_HT_TESTRWM_OFFSET 14 +#define RTL8367D_HT_TESTRWM_MASK 0x4000 +#define RTL8367D_NCTLROM_TEST1_OFFSET 13 +#define RTL8367D_NCTLROM_TEST1_MASK 0x2000 +#define RTL8367D_NCTLRAM_TEST1_OFFSET 12 +#define RTL8367D_NCTLRAM_TEST1_MASK 0x1000 +#define RTL8367D_IROM_TEST1_OFFSET 11 +#define RTL8367D_IROM_TEST1_MASK 0x800 +#define RTL8367D_IRAM_TEST1_OFFSET 10 +#define RTL8367D_IRAM_TEST1_MASK 0x400 +#define RTL8367D_ERAM_TEST1_OFFSET 9 +#define RTL8367D_ERAM_TEST1_MASK 0x200 +#define RTL8367D_HSACTRL_TEST1_OFFSET 8 +#define RTL8367D_HSACTRL_TEST1_MASK 0x100 +#define RTL8367D_CVLAN_TEST1_OFFSET 7 +#define RTL8367D_CVLAN_TEST1_MASK 0x80 +#define RTL8367D_MIB_TEST1_OFFSET 6 +#define RTL8367D_MIB_TEST1_MASK 0x40 +#define RTL8367D_HT_TEST1_OFFSET 5 +#define RTL8367D_HT_TEST1_MASK 0x20 +#define RTL8367D_ACT_TEST1_OFFSET 4 +#define RTL8367D_ACT_TEST1_MASK 0x10 +#define RTL8367D_PB_TEST1_OFFSET 3 +#define RTL8367D_PB_TEST1_MASK 0x8 +#define RTL8367D_OUTQ_TEST1_OFFSET 2 +#define RTL8367D_OUTQ_TEST1_MASK 0x4 +#define RTL8367D_L2_TEST1_OFFSET 1 +#define RTL8367D_L2_TEST1_MASK 0x2 + +#define RTL8367D_REG_BIST_CFG_TCAM 0x671f +#define RTL8367D_TCAM_WATS_OFFSET 12 +#define RTL8367D_TCAM_WATS_MASK 0x3000 +#define RTL8367D_TCAM_WAS_OFFSET 9 +#define RTL8367D_TCAM_WAS_MASK 0xE00 +#define RTL8367D_TCAM_WAEN_OFFSET 8 +#define RTL8367D_TCAM_WAEN_MASK 0x100 +#define RTL8367D_TCAM_TM_OFFSET 7 +#define RTL8367D_TCAM_TM_MASK 0x80 +#define RTL8367D_BIST_CFG_TCAM_TCAM_RDS_OFFSET 3 +#define RTL8367D_BIST_CFG_TCAM_TCAM_RDS_MASK 0x78 +#define RTL8367D_BIST_CFG_TCAM_TCAM_MDS_OFFSET 0 +#define RTL8367D_BIST_CFG_TCAM_TCAM_MDS_MASK 0x7 + +#define RTL8367D_REG_BIST_RSLT_PAUSE 0x6720 +#define RTL8367D_NCTLRAM_PAUSE_OFFSET 12 +#define RTL8367D_NCTLRAM_PAUSE_MASK 0x1000 +#define RTL8367D_IROM_PAUSE_OFFSET 11 +#define RTL8367D_IROM_PAUSE_MASK 0x800 +#define RTL8367D_IRAM_PAUSE_OFFSET 10 +#define RTL8367D_IRAM_PAUSE_MASK 0x400 +#define RTL8367D_ERAM_PAUSE_OFFSET 9 +#define RTL8367D_ERAM_PAUSE_MASK 0x200 +#define RTL8367D_HSACTRL_PAUSE_OFFSET 8 +#define RTL8367D_HSACTRL_PAUSE_MASK 0x100 +#define RTL8367D_CVLAN_PAUSE_OFFSET 7 +#define RTL8367D_CVLAN_PAUSE_MASK 0x80 +#define RTL8367D_MIB_PAUSE_OFFSET 6 +#define RTL8367D_MIB_PAUSE_MASK 0x40 +#define RTL8367D_HT_PAUSE_OFFSET 5 +#define RTL8367D_HT_PAUSE_MASK 0x20 +#define RTL8367D_ACT_PAUSE_OFFSET 4 +#define RTL8367D_ACT_PAUSE_MASK 0x10 +#define RTL8367D_PB_PAUSE_OFFSET 3 +#define RTL8367D_PB_PAUSE_MASK 0x8 +#define RTL8367D_OUTQ_PAUSE_OFFSET 2 +#define RTL8367D_OUTQ_PAUSE_MASK 0x4 +#define RTL8367D_L2_PAUSE_OFFSET 1 +#define RTL8367D_L2_PAUSE_MASK 0x2 +#define RTL8367D_TCAM_PAUSE_OFFSET 0 +#define RTL8367D_TCAM_PAUSE_MASK 0x1 + +#define RTL8367D_REG_BIST_RSLT_DONE 0x6721 +#define RTL8367D_NCTLROM_DONE_OFFSET 13 +#define RTL8367D_NCTLROM_DONE_MASK 0x2000 +#define RTL8367D_NCTLRAM_DONE_OFFSET 12 +#define RTL8367D_NCTLRAM_DONE_MASK 0x1000 +#define RTL8367D_IROM_DONE_OFFSET 11 +#define RTL8367D_IROM_DONE_MASK 0x800 +#define RTL8367D_IRAM_DONE_OFFSET 10 +#define RTL8367D_IRAM_DONE_MASK 0x400 +#define RTL8367D_ERAM_DONE_OFFSET 9 +#define RTL8367D_ERAM_DONE_MASK 0x200 +#define RTL8367D_HSACTRL_DONE_OFFSET 8 +#define RTL8367D_HSACTRL_DONE_MASK 0x100 +#define RTL8367D_CVLAN_DONE_OFFSET 7 +#define RTL8367D_CVLAN_DONE_MASK 0x80 +#define RTL8367D_MIB_DONE_OFFSET 6 +#define RTL8367D_MIB_DONE_MASK 0x40 +#define RTL8367D_HT_DONE_OFFSET 5 +#define RTL8367D_HT_DONE_MASK 0x20 +#define RTL8367D_ACT_DONE_OFFSET 4 +#define RTL8367D_ACT_DONE_MASK 0x10 +#define RTL8367D_PB_DONE_OFFSET 3 +#define RTL8367D_PB_DONE_MASK 0x8 +#define RTL8367D_OUTQ_DONE_OFFSET 2 +#define RTL8367D_OUTQ_DONE_MASK 0x4 +#define RTL8367D_L2_DONE_OFFSET 1 +#define RTL8367D_L2_DONE_MASK 0x2 +#define RTL8367D_TCAM_DONE_OFFSET 0 +#define RTL8367D_TCAM_DONE_MASK 0x1 + +#define RTL8367D_REG_BIST_RSLT_DRF_DONE 0x6722 +#define RTL8367D_NCTLRAM_DRF_DONE_OFFSET 12 +#define RTL8367D_NCTLRAM_DRF_DONE_MASK 0x1000 +#define RTL8367D_IROM_DRF_DONE_OFFSET 11 +#define RTL8367D_IROM_DRF_DONE_MASK 0x800 +#define RTL8367D_IRAM_DRF_DONE_OFFSET 10 +#define RTL8367D_IRAM_DRF_DONE_MASK 0x400 +#define RTL8367D_ERAM_DRF_DONE_OFFSET 9 +#define RTL8367D_ERAM_DRF_DONE_MASK 0x200 +#define RTL8367D_HSACTRL_DRF_DONE_OFFSET 8 +#define RTL8367D_HSACTRL_DRF_DONE_MASK 0x100 +#define RTL8367D_CVLAN_DRF_DONE_OFFSET 7 +#define RTL8367D_CVLAN_DRF_DONE_MASK 0x80 +#define RTL8367D_MIB_DRF_DONE_OFFSET 6 +#define RTL8367D_MIB_DRF_DONE_MASK 0x40 +#define RTL8367D_HT_DRF_DONE_OFFSET 5 +#define RTL8367D_HT_DRF_DONE_MASK 0x20 +#define RTL8367D_ACT_DRF_DONE_OFFSET 4 +#define RTL8367D_ACT_DRF_DONE_MASK 0x10 +#define RTL8367D_PB_DRF_DONE_OFFSET 3 +#define RTL8367D_PB_DRF_DONE_MASK 0x8 +#define RTL8367D_OUTQ_DRF_DONE_OFFSET 2 +#define RTL8367D_OUTQ_DRF_DONE_MASK 0x4 +#define RTL8367D_L2_DRF_DONE_OFFSET 1 +#define RTL8367D_L2_DRF_DONE_MASK 0x2 +#define RTL8367D_TCAM_DRF_DONE_OFFSET 0 +#define RTL8367D_TCAM_DRF_DONE_MASK 0x1 + +#define RTL8367D_REG_BIST_RSLT_FAIL 0x6723 +#define RTL8367D_NCTLROM_FAIL_OFFSET 13 +#define RTL8367D_NCTLROM_FAIL_MASK 0x2000 +#define RTL8367D_NCTLRAM_FAIL_OFFSET 12 +#define RTL8367D_NCTLRAM_FAIL_MASK 0x1000 +#define RTL8367D_IROM_FAIL_OFFSET 11 +#define RTL8367D_IROM_FAIL_MASK 0x800 +#define RTL8367D_IRAM_FAIL_OFFSET 10 +#define RTL8367D_IRAM_FAIL_MASK 0x400 +#define RTL8367D_ERAM_FAIL_OFFSET 9 +#define RTL8367D_ERAM_FAIL_MASK 0x200 +#define RTL8367D_HSACTRL_FAIL_OFFSET 8 +#define RTL8367D_HSACTRL_FAIL_MASK 0x100 +#define RTL8367D_CVLAN_FAIL_OFFSET 7 +#define RTL8367D_CVLAN_FAIL_MASK 0x80 +#define RTL8367D_MIB_FAIL_OFFSET 6 +#define RTL8367D_MIB_FAIL_MASK 0x40 +#define RTL8367D_HT_FAIL_OFFSET 5 +#define RTL8367D_HT_FAIL_MASK 0x20 +#define RTL8367D_ACT_FAIL_OFFSET 4 +#define RTL8367D_ACT_FAIL_MASK 0x10 +#define RTL8367D_BIST_RSLT_FAIL_PB_FAIL_OFFSET 3 +#define RTL8367D_BIST_RSLT_FAIL_PB_FAIL_MASK 0x8 +#define RTL8367D_BIST_RSLT_FAIL_OUTQ_FAIL_OFFSET 2 +#define RTL8367D_BIST_RSLT_FAIL_OUTQ_FAIL_MASK 0x4 +#define RTL8367D_BIST_RSLT_FAIL_L2_FAIL_OFFSET 1 +#define RTL8367D_BIST_RSLT_FAIL_L2_FAIL_MASK 0x2 +#define RTL8367D_TCAM_FAIL_OFFSET 0 +#define RTL8367D_TCAM_FAIL_MASK 0x1 + +#define RTL8367D_REG_BIST_RSLT_DRF_FAIL 0x6724 +#define RTL8367D_NCTLRAM_DRF_FAIL_OFFSET 12 +#define RTL8367D_NCTLRAM_DRF_FAIL_MASK 0x1000 +#define RTL8367D_IROM_DRF_FAIL_OFFSET 11 +#define RTL8367D_IROM_DRF_FAIL_MASK 0x800 +#define RTL8367D_IRAM_DRF_FAIL_OFFSET 10 +#define RTL8367D_IRAM_DRF_FAIL_MASK 0x400 +#define RTL8367D_ERAM_DRF_FAIL_OFFSET 9 +#define RTL8367D_ERAM_DRF_FAIL_MASK 0x200 +#define RTL8367D_HSACTRL_DRF_FAIL_OFFSET 8 +#define RTL8367D_HSACTRL_DRF_FAIL_MASK 0x100 +#define RTL8367D_CVLAN_DRF_FAIL_OFFSET 7 +#define RTL8367D_CVLAN_DRF_FAIL_MASK 0x80 +#define RTL8367D_MIB_DRF_FAIL_OFFSET 6 +#define RTL8367D_MIB_DRF_FAIL_MASK 0x40 +#define RTL8367D_HT_DRF_FAIL_OFFSET 5 +#define RTL8367D_HT_DRF_FAIL_MASK 0x20 +#define RTL8367D_ACT_DRF_FAIL_OFFSET 4 +#define RTL8367D_ACT_DRF_FAIL_MASK 0x10 +#define RTL8367D_BIST_RSLT_DRF_FAIL_PB_DRF_FAIL_OFFSET 3 +#define RTL8367D_BIST_RSLT_DRF_FAIL_PB_DRF_FAIL_MASK 0x8 +#define RTL8367D_BIST_RSLT_DRF_FAIL_OUTQ_DRF_FAIL_OFFSET 2 +#define RTL8367D_BIST_RSLT_DRF_FAIL_OUTQ_DRF_FAIL_MASK 0x4 +#define RTL8367D_BIST_RSLT_DRF_FAIL_L2_DRF_FAIL_OFFSET 1 +#define RTL8367D_BIST_RSLT_DRF_FAIL_L2_DRF_FAIL_MASK 0x2 +#define RTL8367D_TCAM_DRF_FAIL_OFFSET 0 +#define RTL8367D_TCAM_DRF_FAIL_MASK 0x1 + + +#endif /*#ifndef _RTL8367D_REG_H_*/ + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/rtl8367d_smi.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/rtl8367d_smi.c new file mode 100644 index 00000000..efc3e7a2 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/rtl8367d_smi.c @@ -0,0 +1,471 @@ +/* +* Copyright c Realtek Semiconductor Corporation, 2006 +* All rights reserved. +* +* Program : Control smi connected RTL8366 +* Abstract : +* Author : Yu-Mei Pan (ympan@realtek.com.cn) +* $Id: smi.c,v 1.2 2008-04-10 03:04:19 shiehyy Exp $ +*/ +#include +#include +#include "rtk_error.h" + +/* Define */ +#define MDC_MDIO_CTRL0_REG 31 +#define MDC_MDIO_START_REG 29 +#define MDC_MDIO_CTRL1_REG 21 +#define MDC_MDIO_ADDRESS_REG 23 +#define MDC_MDIO_DATA_WRITE_REG 24 +#define MDC_MDIO_DATA_READ_REG 25 +#define MDC_MDIO_PREAMBLE_LEN 32 + +#define MDC_MDIO_START_OP 0xFFFF +#define MDC_MDIO_ADDR_OP 0x000E +#define MDC_MDIO_READ_OP 0x0001 +#define MDC_MDIO_WRITE_OP 0x0003 + +#define SPI_READ_OP 0x3 +#define SPI_WRITE_OP 0x2 +#define SPI_READ_OP_LEN 0x8 +#define SPI_WRITE_OP_LEN 0x8 +#define SPI_REG_LEN 16 +#define SPI_DATA_LEN 16 + +#define GPIO_DIR_IN 1 +#define GPIO_DIR_OUT 0 + +#define ack_timer 5 + +#define DELAY 10000 +#define CLK_DURATION(clk) { int i; for(i=0; i 1, 1 -> 0 */ + GPIO_DATA_SET(rtl8367d_smi_SCK, 1); + CLK_DURATION(DELAY); + GPIO_DATA_SET(rtl8367d_smi_SCK, 0); + CLK_DURATION(DELAY); + + /* CLK 2: */ + GPIO_DATA_SET(rtl8367d_smi_SCK, 1); + CLK_DURATION(DELAY); + GPIO_DATA_SET(rtl8367d_smi_SDA, 0); + CLK_DURATION(DELAY); + GPIO_DATA_SET(rtl8367d_smi_SCK, 0); + CLK_DURATION(DELAY); + GPIO_DATA_SET(rtl8367d_smi_SDA, 1); + +} + + + +static void _smi_writeBit(rtk_uint16 signal, rtk_uint32 bitLen) +{ + for( ; bitLen > 0; bitLen--) + { + CLK_DURATION(DELAY); + + /* prepare data */ + if ( signal & (1<<(bitLen-1)) ) + { + GPIO_DATA_SET(rtl8367d_smi_SDA, 1); + } + else + { + GPIO_DATA_SET(rtl8367d_smi_SDA, 0); + } + CLK_DURATION(DELAY); + + /* clocking */ + GPIO_DATA_SET(rtl8367d_smi_SCK, 1); + CLK_DURATION(DELAY); + GPIO_DATA_SET(rtl8367d_smi_SCK, 0); + } +} + + + +static void _smi_readBit(rtk_uint32 bitLen, rtk_uint32 *rData) +{ + rtk_uint32 u = 0; + + /* change GPIO pin to Input only */ + GPIO_DIRECTION_SET(rtl8367d_smi_SDA, GPIO_DIR_IN); + + for (*rData = 0; bitLen > 0; bitLen--) + { + CLK_DURATION(DELAY); + + /* clocking */ + GPIO_DATA_SET(rtl8367d_smi_SCK, 1); + CLK_DURATION(DELAY); + GPIO_DATA_GET(rtl8367d_smi_SDA, &u); + GPIO_DATA_SET(rtl8367d_smi_SCK, 0); + + *rData |= (u << (bitLen - 1)); + } + + /* change GPIO pin to Output only */ + GPIO_DIRECTION_SET(rtl8367d_smi_SDA, GPIO_DIR_OUT); +} + + + +static void _smi_stop(void) +{ + + CLK_DURATION(DELAY); + GPIO_DATA_SET(rtl8367d_smi_SDA, 0); + GPIO_DATA_SET(rtl8367d_smi_SCK, 1); + CLK_DURATION(DELAY); + GPIO_DATA_SET(rtl8367d_smi_SDA, 1); + CLK_DURATION(DELAY); + GPIO_DATA_SET(rtl8367d_smi_SCK, 1); + CLK_DURATION(DELAY); + GPIO_DATA_SET(rtl8367d_smi_SCK, 0); + CLK_DURATION(DELAY); + GPIO_DATA_SET(rtl8367d_smi_SCK, 1); + + /* add a click */ + CLK_DURATION(DELAY); + GPIO_DATA_SET(rtl8367d_smi_SCK, 0); + CLK_DURATION(DELAY); + GPIO_DATA_SET(rtl8367d_smi_SCK, 1); + + + /* change GPIO pin to Input only */ + GPIO_DIRECTION_SET(rtl8367d_smi_SDA, GPIO_DIR_IN); + GPIO_DIRECTION_SET(rtl8367d_smi_SCK, GPIO_DIR_IN); +} + +#endif /* End of #if defined(MDC_MDIO_OPERATION) || defined(SPI_OPERATION) */ + +rtk_int32 rtl8367d_smi_read(rtk_uint32 mAddrs, rtk_uint32 *rData) +{ +#if (!defined(MDC_MDIO_OPERATION) && !defined(SPI_OPERATION)) + rtk_uint32 rawData=0, ACK; + rtk_uint8 con; + rtk_uint32 ret = RT_ERR_OK; +#endif + + if(mAddrs > 0xFFFF) + return RT_ERR_INPUT; + + if(rData == NULL) + return RT_ERR_NULL_POINTER; + + *rData = 0; + +#if defined(MDC_MDIO_OPERATION) + + /* Lock */ + rtlglue_drvMutexLock(); + + /* Write address control code to register 31 */ + MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_PHY_ID, MDC_MDIO_CTRL0_REG, MDC_MDIO_ADDR_OP); + + /* Write address to register 23 */ + MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_PHY_ID, MDC_MDIO_ADDRESS_REG, mAddrs); + + /* Write read control code to register 21 */ + MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_PHY_ID, MDC_MDIO_CTRL1_REG, MDC_MDIO_READ_OP); + + /* Read data from register 25 */ + MDC_MDIO_READ(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_PHY_ID, MDC_MDIO_DATA_READ_REG, rData); + + /* Unlock */ + rtlglue_drvMutexUnlock(); + + return RT_ERR_OK; + +#elif defined(SPI_OPERATION) + + /* Lock */ + rtlglue_drvMutexLock(); + + /* Write 8 bits READ OP_CODE */ + SPI_WRITE(SPI_READ_OP, SPI_READ_OP_LEN); + + /* Write 16 bits register address */ + SPI_WRITE(mAddrs, SPI_REG_LEN); + + /* Read 16 bits data */ + SPI_READ(rData, SPI_DATA_LEN); + + /* Unlock */ + rtlglue_drvMutexUnlock(); + + return RT_ERR_OK; + +#else + + /*Disable CPU interrupt to ensure that the SMI operation is atomic. + The API is based on RTL865X, rewrite the API if porting to other platform.*/ + rtlglue_drvMutexLock(); + + _smi_start(); /* Start SMI */ + + _smi_writeBit(0x0b, 4); /* CTRL code: 4'b1011 for RTL8370 */ + + _smi_writeBit(0x4, 3); /* CTRL code: 3'b100 */ + + _smi_writeBit(0x1, 1); /* 1: issue READ command */ + + con = 0; + do { + con++; + _smi_readBit(1, &ACK); /* ACK for issuing READ command*/ + } while ((ACK != 0) && (con < ack_timer)); + + if (ACK != 0) ret = RT_ERR_FAILED; + + _smi_writeBit((mAddrs&0xff), 8); /* Set reg_addr[7:0] */ + + con = 0; + do { + con++; + _smi_readBit(1, &ACK); /* ACK for setting reg_addr[7:0] */ + } while ((ACK != 0) && (con < ack_timer)); + + if (ACK != 0) ret = RT_ERR_FAILED; + + _smi_writeBit((mAddrs>>8), 8); /* Set reg_addr[15:8] */ + + con = 0; + do { + con++; + _smi_readBit(1, &ACK); /* ACK by RTL8369 */ + } while ((ACK != 0) && (con < ack_timer)); + if (ACK != 0) ret = RT_ERR_FAILED; + + _smi_readBit(8, &rawData); /* Read DATA [7:0] */ + *rData = rawData&0xff; + + _smi_writeBit(0x00, 1); /* ACK by CPU */ + + _smi_readBit(8, &rawData); /* Read DATA [15: 8] */ + + _smi_writeBit(0x01, 1); /* ACK by CPU */ + *rData |= (rawData<<8); + + _smi_stop(); + + rtlglue_drvMutexUnlock();/*enable CPU interrupt*/ + + return ret; +#endif /* end of #if defined(MDC_MDIO_OPERATION) */ +} + + + +rtk_int32 rtl8367d_smi_write(rtk_uint32 mAddrs, rtk_uint32 rData) +{ +#if (!defined(MDC_MDIO_OPERATION) && !defined(SPI_OPERATION)) + rtk_int8 con; + rtk_uint32 ACK; + rtk_uint32 ret = RT_ERR_OK; +#endif + + if(mAddrs > 0xFFFF) + return RT_ERR_INPUT; + + if(rData > 0xFFFF) + return RT_ERR_INPUT; + +#if defined(MDC_MDIO_OPERATION) + + /* Lock */ + rtlglue_drvMutexLock(); + + /* Write address control code to register 31 */ + MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_PHY_ID, MDC_MDIO_CTRL0_REG, MDC_MDIO_ADDR_OP); + + /* Write address to register 23 */ + MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_PHY_ID, MDC_MDIO_ADDRESS_REG, mAddrs); + + /* Write data to register 24 */ + MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_PHY_ID, MDC_MDIO_DATA_WRITE_REG, rData); + + /* Write data control code to register 21 */ + MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_PHY_ID, MDC_MDIO_CTRL1_REG, MDC_MDIO_WRITE_OP); + + /* Unlock */ + rtlglue_drvMutexUnlock(); + + return RT_ERR_OK; + +#elif defined(SPI_OPERATION) + + /* Lock */ + rtlglue_drvMutexLock(); + + /* Write 8 bits WRITE OP_CODE */ + SPI_WRITE(SPI_WRITE_OP, SPI_WRITE_OP_LEN); + + /* Write 16 bits register address */ + SPI_WRITE(mAddrs, SPI_REG_LEN); + + /* Write 16 bits data */ + SPI_WRITE(rData, SPI_DATA_LEN); + + /* Unlock */ + rtlglue_drvMutexUnlock(); + + return RT_ERR_OK; +#else + + /*Disable CPU interrupt to ensure that the SMI operation is atomic. + The API is based on RTL865X, rewrite the API if porting to other platform.*/ + rtlglue_drvMutexLock(); + + _smi_start(); /* Start SMI */ + + _smi_writeBit(0x0b, 4); /* CTRL code: 4'b1011 for RTL8370*/ + + _smi_writeBit(0x4, 3); /* CTRL code: 3'b100 */ + + _smi_writeBit(0x0, 1); /* 0: issue WRITE command */ + + con = 0; + do { + con++; + _smi_readBit(1, &ACK); /* ACK for issuing WRITE command*/ + } while ((ACK != 0) && (con < ack_timer)); + if (ACK != 0) ret = RT_ERR_FAILED; + + _smi_writeBit((mAddrs&0xff), 8); /* Set reg_addr[7:0] */ + + con = 0; + do { + con++; + _smi_readBit(1, &ACK); /* ACK for setting reg_addr[7:0] */ + } while ((ACK != 0) && (con < ack_timer)); + if (ACK != 0) ret = RT_ERR_FAILED; + + _smi_writeBit((mAddrs>>8), 8); /* Set reg_addr[15:8] */ + + con = 0; + do { + con++; + _smi_readBit(1, &ACK); /* ACK for setting reg_addr[15:8] */ + } while ((ACK != 0) && (con < ack_timer)); + if (ACK != 0) ret = RT_ERR_FAILED; + + _smi_writeBit(rData&0xff, 8); /* Write Data [7:0] out */ + + con = 0; + do { + con++; + _smi_readBit(1, &ACK); /* ACK for writting data [7:0] */ + } while ((ACK != 0) && (con < ack_timer)); + if (ACK != 0) ret = RT_ERR_FAILED; + + _smi_writeBit(rData>>8, 8); /* Write Data [15:8] out */ + + con = 0; + do { + con++; + _smi_readBit(1, &ACK); /* ACK for writting data [15:8] */ + } while ((ACK != 0) && (con < ack_timer)); + if (ACK != 0) ret = RT_ERR_FAILED; + + _smi_stop(); + + rtlglue_drvMutexUnlock();/*enable CPU interrupt*/ + + return ret; +#endif /* end of #if defined(MDC_MDIO_OPERATION) */ +} + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/rtl8367d_smi.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/rtl8367d_smi.h new file mode 100644 index 00000000..f3fe9a55 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dal/rtl8367d/rtl8367d_smi.h @@ -0,0 +1,13 @@ + +#ifndef __RTL8367D_SMI_H__ +#define __RTL8367D_SMI_H__ + +#include +#include "rtk_error.h" +//#define MDC_MDIO_OPERATION +rtk_int32 rtl8367d_smi_read(rtk_uint32 mAddrs, rtk_uint32 *rData); +rtk_int32 rtl8367d_smi_write(rtk_uint32 mAddrs, rtk_uint32 rData); + +#endif /* __RTL8367D_SMI_H__ */ + + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dot1x.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dot1x.c new file mode 100644 index 00000000..87d8f402 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dot1x.c @@ -0,0 +1,691 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8367C + * Feature : Here is a list of all functions and variables in 1X module. + * + */ + +#include +#include +#include +#include + +#include + +/* Function Name: + * rtk_dot1x_unauthPacketOper_set + * Description: + * Set 802.1x unauth action configuration. + * Input: + * port - Port id. + * unauth_action - 802.1X unauth action. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameter. + * Note: + * This API can set 802.1x unauth action configuration. + * The unauth action is as following: + * - DOT1X_ACTION_DROP + * - DOT1X_ACTION_TRAP2CPU + * - DOT1X_ACTION_GUESTVLAN + */ +rtk_api_ret_t rtk_dot1x_unauthPacketOper_set(rtk_port_t port, rtk_dot1x_unauth_action_t unauth_action) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->dot1x_unauthPacketOper_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->dot1x_unauthPacketOper_set(port, unauth_action); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_dot1x_unauthPacketOper_get + * Description: + * Get 802.1x unauth action configuration. + * Input: + * port - Port id. + * Output: + * pUnauth_action - 802.1X unauth action. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can get 802.1x unauth action configuration. + * The unauth action is as following: + * - DOT1X_ACTION_DROP + * - DOT1X_ACTION_TRAP2CPU + * - DOT1X_ACTION_GUESTVLAN + */ +rtk_api_ret_t rtk_dot1x_unauthPacketOper_get(rtk_port_t port, rtk_dot1x_unauth_action_t *pUnauth_action) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->dot1x_unauthPacketOper_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->dot1x_unauthPacketOper_get(port, pUnauth_action); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_dot1x_eapolFrame2CpuEnable_set + * Description: + * Set 802.1x EAPOL packet trap to CPU configuration + * Input: + * enable - The status of 802.1x EAPOL packet. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * To support 802.1x authentication functionality, EAPOL frame (ether type = 0x888E) has to + * be trapped to CPU. + * The status of EAPOL frame trap to CPU is as following: + * - DISABLED + * - ENABLED + */ +rtk_api_ret_t rtk_dot1x_eapolFrame2CpuEnable_set(rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->dot1x_eapolFrame2CpuEnable_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->dot1x_eapolFrame2CpuEnable_set(enable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_dot1x_eapolFrame2CpuEnable_get + * Description: + * Get 802.1x EAPOL packet trap to CPU configuration + * Input: + * None + * Output: + * pEnable - The status of 802.1x EAPOL packet. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * To support 802.1x authentication functionality, EAPOL frame (ether type = 0x888E) has to + * be trapped to CPU. + * The status of EAPOL frame trap to CPU is as following: + * - DISABLED + * - ENABLED + */ +rtk_api_ret_t rtk_dot1x_eapolFrame2CpuEnable_get(rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->dot1x_eapolFrame2CpuEnable_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->dot1x_eapolFrame2CpuEnable_get(pEnable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_dot1x_portBasedEnable_set + * Description: + * Set 802.1x port-based enable configuration + * Input: + * port - Port id. + * enable - The status of 802.1x port. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * RT_ERR_DOT1X_PORTBASEDPNEN - 802.1X port-based enable error + * Note: + * The API can update the port-based port enable register content. If a port is 802.1x + * port based network access control "enabled", it should be authenticated so packets + * from that port won't be dropped or trapped to CPU. + * The status of 802.1x port-based network access control is as following: + * - DISABLED + * - ENABLED + */ +rtk_api_ret_t rtk_dot1x_portBasedEnable_set(rtk_port_t port, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->dot1x_portBasedEnable_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->dot1x_portBasedEnable_set(port, enable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_dot1x_portBasedEnable_get + * Description: + * Get 802.1x port-based enable configuration + * Input: + * port - Port id. + * Output: + * pEnable - The status of 802.1x port. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get the 802.1x port-based port status. + */ +rtk_api_ret_t rtk_dot1x_portBasedEnable_get(rtk_port_t port, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->dot1x_portBasedEnable_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->dot1x_portBasedEnable_get(port, pEnable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_dot1x_portBasedAuthStatus_set + * Description: + * Set 802.1x port-based auth. port configuration + * Input: + * port - Port id. + * port_auth - The status of 802.1x port. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_DOT1X_PORTBASEDAUTH - 802.1X port-based auth error + * Note: + * The authenticated status of 802.1x port-based network access control is as following: + * - UNAUTH + * - AUTH + */ +rtk_api_ret_t rtk_dot1x_portBasedAuthStatus_set(rtk_port_t port, rtk_dot1x_auth_status_t port_auth) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->dot1x_portBasedAuthStatus_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->dot1x_portBasedAuthStatus_set(port, port_auth); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_dot1x_portBasedAuthStatus_get + * Description: + * Get 802.1x port-based auth. port configuration + * Input: + * port - Port id. + * Output: + * pPort_auth - The status of 802.1x port. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get 802.1x port-based port auth.information. + */ +rtk_api_ret_t rtk_dot1x_portBasedAuthStatus_get(rtk_port_t port, rtk_dot1x_auth_status_t *pPort_auth) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->dot1x_portBasedAuthStatus_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->dot1x_portBasedAuthStatus_get(port, pPort_auth); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_dot1x_portBasedDirection_set + * Description: + * Set 802.1x port-based operational direction configuration + * Input: + * port - Port id. + * port_direction - Operation direction + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_DOT1X_PORTBASEDOPDIR - 802.1X port-based operation direction error + * Note: + * The operate controlled direction of 802.1x port-based network access control is as following: + * - BOTH + * - IN + */ +rtk_api_ret_t rtk_dot1x_portBasedDirection_set(rtk_port_t port, rtk_dot1x_direction_t port_direction) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->dot1x_portBasedDirection_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->dot1x_portBasedDirection_set(port, port_direction); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_dot1x_portBasedDirection_get + * Description: + * Get 802.1X port-based operational direction configuration + * Input: + * port - Port id. + * Output: + * pPort_direction - Operation direction + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get 802.1x port-based operational direction information. + */ +rtk_api_ret_t rtk_dot1x_portBasedDirection_get(rtk_port_t port, rtk_dot1x_direction_t *pPort_direction) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->dot1x_portBasedDirection_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->dot1x_portBasedDirection_get(port, pPort_direction); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_dot1x_macBasedEnable_set + * Description: + * Set 802.1x mac-based port enable configuration + * Input: + * port - Port id. + * enable - The status of 802.1x port. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * RT_ERR_DOT1X_MACBASEDPNEN - 802.1X mac-based enable error + * Note: + * If a port is 802.1x MAC based network access control "enabled", the incoming packets should + * be authenticated so packets from that port won't be dropped or trapped to CPU. + * The status of 802.1x MAC-based network access control is as following: + * - DISABLED + * - ENABLED + */ +rtk_api_ret_t rtk_dot1x_macBasedEnable_set(rtk_port_t port, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->dot1x_macBasedEnable_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->dot1x_macBasedEnable_set(port, enable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_dot1x_macBasedEnable_get + * Description: + * Get 802.1x mac-based port enable configuration + * Input: + * port - Port id. + * Output: + * pEnable - The status of 802.1x port. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * If a port is 802.1x MAC based network access control "enabled", the incoming packets should + * be authenticated so packets from that port wont be dropped or trapped to CPU. + * The status of 802.1x MAC-based network access control is as following: + * - DISABLED + * - ENABLED + */ +rtk_api_ret_t rtk_dot1x_macBasedEnable_get(rtk_port_t port, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->dot1x_macBasedEnable_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->dot1x_macBasedEnable_get(port, pEnable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_dot1x_macBasedAuthMac_add + * Description: + * Add an authenticated MAC to ASIC + * Input: + * port - Port id. + * pAuth_mac - The authenticated MAC. + * fid - filtering database. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * RT_ERR_DOT1X_MACBASEDPNEN - 802.1X mac-based enable error + * Note: + * The API can add a 802.1x authenticated MAC address to port. If the MAC does not exist in LUT, + * user can't add this MAC to auth status. + */ +rtk_api_ret_t rtk_dot1x_macBasedAuthMac_add(rtk_port_t port, rtk_mac_t *pAuth_mac, rtk_fid_t fid) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->dot1x_macBasedAuthMac_add) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->dot1x_macBasedAuthMac_add(port, pAuth_mac, fid); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_dot1x_macBasedAuthMac_del + * Description: + * Delete an authenticated MAC to ASIC + * Input: + * port - Port id. + * pAuth_mac - The authenticated MAC. + * fid - filtering database. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can delete a 802.1x authenticated MAC address to port. It only change the auth status of + * the MAC and won't delete it from LUT. + */ +rtk_api_ret_t rtk_dot1x_macBasedAuthMac_del(rtk_port_t port, rtk_mac_t *pAuth_mac, rtk_fid_t fid) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->dot1x_macBasedAuthMac_del) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->dot1x_macBasedAuthMac_del(port, pAuth_mac, fid); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_dot1x_macBasedDirection_set + * Description: + * Set 802.1x mac-based operational direction configuration + * Input: + * mac_direction - Operation direction + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_DOT1X_MACBASEDOPDIR - 802.1X mac-based operation direction error + * Note: + * The operate controlled direction of 802.1x mac-based network access control is as following: + * - BOTH + * - IN + */ +rtk_api_ret_t rtk_dot1x_macBasedDirection_set(rtk_dot1x_direction_t mac_direction) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->dot1x_macBasedDirection_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->dot1x_macBasedDirection_set(mac_direction); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_dot1x_macBasedDirection_get + * Description: + * Get 802.1x mac-based operational direction configuration + * Input: + * port - Port id. + * Output: + * pMac_direction - Operation direction + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get 802.1x mac-based operational direction information. + */ +rtk_api_ret_t rtk_dot1x_macBasedDirection_get(rtk_dot1x_direction_t *pMac_direction) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->dot1x_macBasedDirection_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->dot1x_macBasedDirection_get(pMac_direction); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * Set 802.1x guest VLAN configuration + * Description: + * Set 802.1x mac-based operational direction configuration + * Input: + * vid - 802.1x guest VLAN ID + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * Note: + * The operate controlled 802.1x guest VLAN + */ +rtk_api_ret_t rtk_dot1x_guestVlan_set(rtk_vlan_t vid) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->dot1x_guestVlan_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->dot1x_guestVlan_set(vid); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_dot1x_guestVlan_get + * Description: + * Get 802.1x guest VLAN configuration + * Input: + * None + * Output: + * pVid - 802.1x guest VLAN ID + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get 802.1x guest VLAN information. + */ +rtk_api_ret_t rtk_dot1x_guestVlan_get(rtk_vlan_t *pVid) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->dot1x_guestVlan_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->dot1x_guestVlan_get(pVid); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_dot1x_guestVlan2Auth_set + * Description: + * Set 802.1x guest VLAN to auth host configuration + * Input: + * enable - The status of guest VLAN to auth host. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * Note: + * The operational direction of 802.1x guest VLAN to auth host control is as following: + * - ENABLED + * - DISABLED + */ +rtk_api_ret_t rtk_dot1x_guestVlan2Auth_set(rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->dot1x_guestVlan2Auth_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->dot1x_guestVlan2Auth_set(enable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_dot1x_guestVlan2Auth_get + * Description: + * Get 802.1x guest VLAN to auth host configuration + * Input: + * None + * Output: + * pEnable - The status of guest VLAN to auth host. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get 802.1x guest VLAN to auth host information. + */ +rtk_api_ret_t rtk_dot1x_guestVlan2Auth_get(rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->dot1x_guestVlan2Auth_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->dot1x_guestVlan2Auth_get(pEnable); + RTK_API_UNLOCK(); + + return retVal; +} + + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dot1x.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dot1x.h new file mode 100644 index 00000000..667463d5 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/dot1x.h @@ -0,0 +1,472 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8367/RTL8367C switch high-level API + * + * Feature : The file includes 1X module high-layer API defination + * + */ + +#ifndef __RTK_API_DOT1X_H__ +#define __RTK_API_DOT1X_H__ + + +/* Type of port-based dot1x auth/unauth*/ +typedef enum rtk_dot1x_auth_status_e +{ + UNAUTH = 0, + AUTH, + AUTH_STATUS_END +} rtk_dot1x_auth_status_t; + +typedef enum rtk_dot1x_direction_e +{ + DIR_BOTH = 0, + DIR_IN, + DIRECTION_END +} rtk_dot1x_direction_t; + +/* unauth pkt action */ +typedef enum rtk_dot1x_unauth_action_e +{ + DOT1X_ACTION_DROP = 0, + DOT1X_ACTION_TRAP2CPU, + DOT1X_ACTION_GUESTVLAN, + DOT1X_ACTION_END +} rtk_dot1x_unauth_action_t; + +/* Function Name: + * rtk_dot1x_unauthPacketOper_set + * Description: + * Set 802.1x unauth action configuration. + * Input: + * port - Port id. + * unauth_action - 802.1X unauth action. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameter. + * Note: + * This API can set 802.1x unauth action configuration. + * The unauth action is as following: + * - DOT1X_ACTION_DROP + * - DOT1X_ACTION_TRAP2CPU + * - DOT1X_ACTION_GUESTVLAN + */ +extern rtk_api_ret_t rtk_dot1x_unauthPacketOper_set(rtk_port_t port, rtk_dot1x_unauth_action_t unauth_action); + +/* Function Name: + * rtk_dot1x_unauthPacketOper_get + * Description: + * Get 802.1x unauth action configuration. + * Input: + * port - Port id. + * Output: + * pUnauth_action - 802.1X unauth action. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can get 802.1x unauth action configuration. + * The unauth action is as following: + * - DOT1X_ACTION_DROP + * - DOT1X_ACTION_TRAP2CPU + * - DOT1X_ACTION_GUESTVLAN + */ +extern rtk_api_ret_t rtk_dot1x_unauthPacketOper_get(rtk_port_t port, rtk_dot1x_unauth_action_t *pUnauth_action); + +/* Function Name: + * rtk_dot1x_eapolFrame2CpuEnable_set + * Description: + * Set 802.1x EAPOL packet trap to CPU configuration + * Input: + * enable - The status of 802.1x EAPOL packet. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * To support 802.1x authentication functionality, EAPOL frame (ether type = 0x888E) has to + * be trapped to CPU. + * The status of EAPOL frame trap to CPU is as following: + * - DISABLED + * - ENABLED + */ +extern rtk_api_ret_t rtk_dot1x_eapolFrame2CpuEnable_set(rtk_enable_t enable); + +/* Function Name: + * rtk_dot1x_eapolFrame2CpuEnable_get + * Description: + * Get 802.1x EAPOL packet trap to CPU configuration + * Input: + * None + * Output: + * pEnable - The status of 802.1x EAPOL packet. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * To support 802.1x authentication functionality, EAPOL frame (ether type = 0x888E) has to + * be trapped to CPU. + * The status of EAPOL frame trap to CPU is as following: + * - DISABLED + * - ENABLED + */ +extern rtk_api_ret_t rtk_dot1x_eapolFrame2CpuEnable_get(rtk_enable_t *pEnable); + +/* Function Name: + * rtk_dot1x_portBasedEnable_set + * Description: + * Set 802.1x port-based enable configuration + * Input: + * port - Port id. + * enable - The status of 802.1x port. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * RT_ERR_DOT1X_PORTBASEDPNEN - 802.1X port-based enable error + * Note: + * The API can update the port-based port enable register content. If a port is 802.1x + * port based network access control "enabled", it should be authenticated so packets + * from that port won't be dropped or trapped to CPU. + * The status of 802.1x port-based network access control is as following: + * - DISABLED + * - ENABLED + */ +extern rtk_api_ret_t rtk_dot1x_portBasedEnable_set(rtk_port_t port, rtk_enable_t enable); + +/* Function Name: + * rtk_dot1x_portBasedEnable_get + * Description: + * Get 802.1x port-based enable configuration + * Input: + * port - Port id. + * Output: + * pEnable - The status of 802.1x port. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get the 802.1x port-based port status. + */ +extern rtk_api_ret_t rtk_dot1x_portBasedEnable_get(rtk_port_t port, rtk_enable_t *pEnable); + +/* Function Name: + * rtk_dot1x_portBasedAuthStatus_set + * Description: + * Set 802.1x port-based auth. port configuration + * Input: + * port - Port id. + * port_auth - The status of 802.1x port. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_DOT1X_PORTBASEDAUTH - 802.1X port-based auth error + * Note: + * The authenticated status of 802.1x port-based network access control is as following: + * - UNAUTH + * - AUTH + */ +extern rtk_api_ret_t rtk_dot1x_portBasedAuthStatus_set(rtk_port_t port, rtk_dot1x_auth_status_t port_auth); + +/* Function Name: + * rtk_dot1x_portBasedAuthStatus_get + * Description: + * Get 802.1x port-based auth. port configuration + * Input: + * port - Port id. + * Output: + * pPort_auth - The status of 802.1x port. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get 802.1x port-based port auth.information. + */ +extern rtk_api_ret_t rtk_dot1x_portBasedAuthStatus_get(rtk_port_t port, rtk_dot1x_auth_status_t *pPort_auth); + +/* Function Name: + * rtk_dot1x_portBasedDirection_set + * Description: + * Set 802.1x port-based operational direction configuration + * Input: + * port - Port id. + * port_direction - Operation direction + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_DOT1X_PORTBASEDOPDIR - 802.1X port-based operation direction error + * Note: + * The operate controlled direction of 802.1x port-based network access control is as following: + * - BOTH + * - IN + */ +extern rtk_api_ret_t rtk_dot1x_portBasedDirection_set(rtk_port_t port, rtk_dot1x_direction_t port_direction); + +/* Function Name: + * rtk_dot1x_portBasedDirection_get + * Description: + * Get 802.1X port-based operational direction configuration + * Input: + * port - Port id. + * Output: + * pPort_direction - Operation direction + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get 802.1x port-based operational direction information. + */ +extern rtk_api_ret_t rtk_dot1x_portBasedDirection_get(rtk_port_t port, rtk_dot1x_direction_t *pPort_direction); + +/* Function Name: + * rtk_dot1x_macBasedEnable_set + * Description: + * Set 802.1x mac-based port enable configuration + * Input: + * port - Port id. + * enable - The status of 802.1x port. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * RT_ERR_DOT1X_MACBASEDPNEN - 802.1X mac-based enable error + * Note: + * If a port is 802.1x MAC based network access control "enabled", the incoming packets should + * be authenticated so packets from that port won't be dropped or trapped to CPU. + * The status of 802.1x MAC-based network access control is as following: + * - DISABLED + * - ENABLED + */ +extern rtk_api_ret_t rtk_dot1x_macBasedEnable_set(rtk_port_t port, rtk_enable_t enable); + +/* Function Name: + * rtk_dot1x_macBasedEnable_get + * Description: + * Get 802.1x mac-based port enable configuration + * Input: + * port - Port id. + * Output: + * pEnable - The status of 802.1x port. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * If a port is 802.1x MAC based network access control "enabled", the incoming packets should + * be authenticated so packets from that port wont be dropped or trapped to CPU. + * The status of 802.1x MAC-based network access control is as following: + * - DISABLED + * - ENABLED + */ +extern rtk_api_ret_t rtk_dot1x_macBasedEnable_get(rtk_port_t port, rtk_enable_t *pEnable); + +/* Function Name: + * rtk_dot1x_macBasedAuthMac_add + * Description: + * Add an authenticated MAC to ASIC + * Input: + * port - Port id. + * pAuth_mac - The authenticated MAC. + * fid - filtering database. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * RT_ERR_DOT1X_MACBASEDPNEN - 802.1X mac-based enable error + * Note: + * The API can add a 802.1x authenticated MAC address to port. If the MAC does not exist in LUT, + * user can't add this MAC to auth status. + */ +extern rtk_api_ret_t rtk_dot1x_macBasedAuthMac_add(rtk_port_t port, rtk_mac_t *pAuth_mac, rtk_fid_t fid); + +/* Function Name: + * rtk_dot1x_macBasedAuthMac_del + * Description: + * Delete an authenticated MAC to ASIC + * Input: + * port - Port id. + * pAuth_mac - The authenticated MAC. + * fid - filtering database. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can delete a 802.1x authenticated MAC address to port. It only change the auth status of + * the MAC and won't delete it from LUT. + */ +extern rtk_api_ret_t rtk_dot1x_macBasedAuthMac_del(rtk_port_t port, rtk_mac_t *pAuth_mac, rtk_fid_t fid); + +/* Function Name: + * rtk_dot1x_macBasedDirection_set + * Description: + * Set 802.1x mac-based operational direction configuration + * Input: + * mac_direction - Operation direction + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_DOT1X_MACBASEDOPDIR - 802.1X mac-based operation direction error + * Note: + * The operate controlled direction of 802.1x mac-based network access control is as following: + * - BOTH + * - IN + */ +extern rtk_api_ret_t rtk_dot1x_macBasedDirection_set(rtk_dot1x_direction_t mac_direction); + +/* Function Name: + * rtk_dot1x_macBasedDirection_get + * Description: + * Get 802.1x mac-based operational direction configuration + * Input: + * port - Port id. + * Output: + * pMac_direction - Operation direction + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get 802.1x mac-based operational direction information. + */ +extern rtk_api_ret_t rtk_dot1x_macBasedDirection_get(rtk_dot1x_direction_t *pMac_direction); + +/* Function Name: + * Set 802.1x guest VLAN configuration + * Description: + * Set 802.1x mac-based operational direction configuration + * Input: + * vid - 802.1x guest VLAN ID + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * Note: + * The operate controlled 802.1x guest VLAN + */ +extern rtk_api_ret_t rtk_dot1x_guestVlan_set(rtk_vlan_t vid); + +/* Function Name: + * rtk_dot1x_guestVlan_get + * Description: + * Get 802.1x guest VLAN configuration + * Input: + * None + * Output: + * pVid - 802.1x guest VLAN ID + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get 802.1x guest VLAN information. + */ +extern rtk_api_ret_t rtk_dot1x_guestVlan_get(rtk_vlan_t *pVid); + +/* Function Name: + * rtk_dot1x_guestVlan2Auth_set + * Description: + * Set 802.1x guest VLAN to auth host configuration + * Input: + * enable - The status of guest VLAN to auth host. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * Note: + * The operational direction of 802.1x guest VLAN to auth host control is as following: + * - ENABLED + * - DISABLED + */ +extern rtk_api_ret_t rtk_dot1x_guestVlan2Auth_set(rtk_enable_t enable); + +/* Function Name: + * rtk_dot1x_guestVlan2Auth_get + * Description: + * Get 802.1x guest VLAN to auth host configuration + * Input: + * None + * Output: + * pEnable - The status of guest VLAN to auth host. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get 802.1x guest VLAN to auth host information. + */ +extern rtk_api_ret_t rtk_dot1x_guestVlan2Auth_get(rtk_enable_t *pEnable); + + +#endif /* __RTK_API_DOT1X_H__ */ + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/eee.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/eee.c new file mode 100644 index 00000000..e905c502 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/eee.c @@ -0,0 +1,124 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8367C + * Feature : Here is a list of all functions and variables in EEE module. + * + */ + +#include +#include +#include +#include +#include + +/* Function Name: + * rtk_eee_init + * Description: + * EEE function initialization. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API is used to initialize EEE status. + */ +rtk_api_ret_t rtk_eee_init(void) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->eee_init) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->eee_init(); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_eee_portEnable_set + * Description: + * Set enable status of EEE function. + * Input: + * port - port id. + * enable - enable EEE status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * This API can set EEE function to the specific port. + * The configuration of the port is as following: + * - DISABLE + * - ENABLE + */ +rtk_api_ret_t rtk_eee_portEnable_set(rtk_port_t port, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->eee_portEnable_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->eee_portEnable_set(port, enable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_eee_portEnable_get + * Description: + * Get enable status of EEE function + * Input: + * port - Port id. + * Output: + * pEnable - Back pressure status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can get EEE function to the specific port. + * The configuration of the port is as following: + * - DISABLE + * - ENABLE + */ + +rtk_api_ret_t rtk_eee_portEnable_get(rtk_port_t port, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->eee_portEnable_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->eee_portEnable_get(port, pEnable); + RTK_API_UNLOCK(); + + return retVal; +} + + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/eee.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/eee.h new file mode 100644 index 00000000..e82b7448 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/eee.h @@ -0,0 +1,84 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8367/RTL8367C switch high-level API + * + * Feature : The file includes EEE module high-layer API defination + * + */ + +#ifndef __RTK_API_EEE_H__ +#define __RTK_API_EEE_H__ + +/* Function Name: + * rtk_eee_init + * Description: + * EEE function initialization. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API is used to initialize EEE status. + */ +extern rtk_api_ret_t rtk_eee_init(void); + +/* Function Name: + * rtk_eee_portEnable_set + * Description: + * Set enable status of EEE function. + * Input: + * port - port id. + * enable - enable EEE status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * This API can set EEE function to the specific port. + * The configuration of the port is as following: + * - DISABLE + * - ENABLE + */ +extern rtk_api_ret_t rtk_eee_portEnable_set(rtk_port_t port, rtk_enable_t enable); + +/* Function Name: + * rtk_eee_portEnable_get + * Description: + * Get port admin configuration of the specific port. + * Input: + * port - Port id. + * Output: + * pEnable - Back pressure status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can set EEE function to the specific port. + * The configuration of the port is as following: + * - DISABLE + * - ENABLE + */ +extern rtk_api_ret_t rtk_eee_portEnable_get(rtk_port_t port, rtk_enable_t *pEnable); + + +#endif /* __RTK_API_EEE_H__ */ + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/gpio.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/gpio.c new file mode 100644 index 00000000..ee92d35a --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/gpio.c @@ -0,0 +1,312 @@ +/* + * Copyright (C) 2021 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API + * Feature : Here is a list of all functions and variables in GPIO module. + * + */ + +#include +#include +#include +#include + +#include + +/* Function Name: + * rtk_gpio_input_get + * Description: + * Get gpio input + * Input: + * pin - GPIO pin + * Output: + * pInput - GPIO input + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_NULL_POINTER - input parameter is null pointer. + * Note: + * None + */ +rtk_api_ret_t rtk_gpio_input_get(rtk_uint32 pin, rtk_uint32 *pInput) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->gpio_input_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->gpio_input_get(pin, pInput); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_gpio_output_set + * Description: + * Set GPIO output value. + * Input: + * pin - GPIO pin + * output - 1 or 0 + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_OUT_OF_RANGE - input parameter out of range. + * Note: + * The API can set GPIO pin output 1 or 0. + */ +rtk_api_ret_t rtk_gpio_output_set(rtk_uint32 pin, rtk_uint32 output) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->gpio_output_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->gpio_output_set(pin, output); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_gpio_output_get + * Description: + * Get GPIO output. + * Input: + * pin - GPIO pin + * Output: + * pOutput - GPIO output + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_OUT_OF_RANGE - input parameter out of range. + * RT_ERR_NULL_POINTER - input parameter is null pointer. + * Note: + * The API can get GPIO output. + */ +rtk_api_ret_t rtk_gpio_output_get(rtk_uint32 pin, rtk_uint32 *pOutput) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->gpio_output_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->gpio_output_get(pin, pOutput); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_gpio_state_set + * Description: + * Set GPIO control. + * Input: + * pin - GPIO pin + * state - GPIO enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_OUT_OF_RANGE - input parameter out of range. + * RT_ERR_ENABLE - invalid enable parameter . + * Note: + * The API can set GPIO pin output 1 or 0. + */ +rtk_api_ret_t rtk_gpio_state_set(rtk_uint32 pin, rtk_enable_t state) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->gpio_state_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->gpio_state_set(pin, state); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_gpio_state_get + * Description: + * Get GPIO enable state. + * Input: + * pin - GPIO pin + * Output: + * pState - GPIO state + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_OUT_OF_RANGE - input parameter out of range. + * RT_ERR_NULL_POINTER - input parameter is null pointer. + * Note: + * The API can get GPIO enable state. + */ +rtk_api_ret_t rtk_gpio_state_get(rtk_uint32 pin, rtk_enable_t *pState) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->gpio_state_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->gpio_state_get(pin, pState); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_gpio_mode_set + * Description: + * Set GPIO mode. + * Input: + * pin - GPIO pin + * mode - Output or input mode + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_OUT_OF_RANGE - input parameter out of range. + * Note: + * The API can set GPIO to input or output mode. + */ +rtk_api_ret_t rtk_gpio_mode_set(rtk_uint32 pin, rtk_gpio_mode_t mode) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->gpio_mode_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->gpio_mode_set(pin, mode); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_gpio_mode_get + * Description: + * Get GPIO mode. + * Input: + * pin - GPIO pin + * Output: + * pMode - GPIO mode + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_OUT_OF_RANGE - input parameter out of range. + * RT_ERR_NULL_POINTER - input parameter is null pointer. + * Note: + * The API can get GPIO mode. + */ +rtk_api_ret_t rtk_gpio_mode_get(rtk_uint32 pin, rtk_gpio_mode_t *pMode) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->gpio_mode_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->gpio_mode_get(pin, pMode); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_gpio_aclEnClear_set + * Description: + * Set GPIO acl clear. + * Input: + * pin - GPIO pin + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_OUT_OF_RANGE - input parameter out of range. + * Note: + * The API can set GPIO ACL clear. + */ +rtk_api_ret_t rtk_gpio_aclEnClear_set(rtk_uint32 pin) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->gpio_aclEnClear_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->gpio_aclEnClear_set(pin); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_gpio_aclEnClear_get + * Description: + * Get GPIO acl clear. + * Input: + * pin - GPIO pin + * Output: + * pAclEn - GPIO acl enable + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_OUT_OF_RANGE - input parameter out of range. + * RT_ERR_NULL_POINTER - input parameter is null pointer. + * Note: + * The API can get GPIO acl enable clear. + */ +rtk_api_ret_t rtk_gpio_aclEnClear_get(rtk_uint32 pin, rtk_enable_t *pAclEn) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->gpio_aclEnClear_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->gpio_aclEnClear_get(pin, pAclEn); + RTK_API_UNLOCK(); + + return retVal; +} + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/gpio.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/gpio.h new file mode 100644 index 00000000..05e8f717 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/gpio.h @@ -0,0 +1,212 @@ +/* + * Copyright (C) 2021 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API + * Feature : Here is a list of all functions and variables in GPIO module. + * + */ + +#ifndef __RTK_API_GPIO_H__ +#define __RTK_API_GPIO_H__ + +/* + * Data Type Declaration + */ +typedef enum rtk_gpio_mode_e +{ + GPIO_MODE_OUTPUT = 0, + GPIO_MODE_INPUT, + GPIO_MODE_END +} rtk_gpio_mode_t; + +/* Function Name: + * rtk_gpio_input_get + * Description: + * Get gpio input + * Input: + * pin - GPIO pin + * Output: + * pInput - GPIO input + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_NULL_POINTER - input parameter is null pointer. + * Note: + * None + */ +extern rtk_api_ret_t rtk_gpio_input_get(rtk_uint32 pin, rtk_uint32 *pInput); + +/* Function Name: + * rtk_gpio_output_set + * Description: + * Set GPIO output value. + * Input: + * pin - GPIO pin + * output - 1 or 0 + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_OUT_OF_RANGE - input parameter out of range. + * Note: + * The API can set GPIO pin output 1 or 0. + */ +extern rtk_api_ret_t rtk_gpio_output_set(rtk_uint32 pin, rtk_uint32 output); + +/* Function Name: + * rtk_gpio_output_get + * Description: + * Get GPIO output. + * Input: + * pin - GPIO pin + * Output: + * pOutput - GPIO output + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_OUT_OF_RANGE - input parameter out of range. + * RT_ERR_NULL_POINTER - input parameter is null pointer. + * Note: + * The API can get GPIO output. + */ +extern rtk_api_ret_t rtk_gpio_output_get(rtk_uint32 pin, rtk_uint32 *pOutput); + +/* Function Name: + * rtk_gpio_state_set + * Description: + * Set GPIO control. + * Input: + * pin - GPIO pin + * state - GPIO enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_OUT_OF_RANGE - input parameter out of range. + * RT_ERR_ENABLE - invalid enable parameter . + * Note: + * The API can set GPIO pin output 1 or 0. + */ +extern rtk_api_ret_t rtk_gpio_state_set(rtk_uint32 pin, rtk_enable_t state); + +/* Function Name: + * rtk_gpio_state_get + * Description: + * Get GPIO enable state. + * Input: + * pin - GPIO pin + * Output: + * pState - GPIO enable + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_OUT_OF_RANGE - input parameter out of range. + * RT_ERR_NULL_POINTER - input parameter is null pointer. + * Note: + * The API can get GPIO enable state. + */ +extern rtk_api_ret_t rtk_gpio_state_get(rtk_uint32 pin, rtk_enable_t *pState); + +/* Function Name: + * rtk_gpio_mode_set + * Description: + * Set GPIO mode. + * Input: + * pin - GPIO pin + * mode - Output or input mode + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_OUT_OF_RANGE - input parameter out of range. + * Note: + * The API can set GPIO to input or output mode. + */ +extern rtk_api_ret_t rtk_gpio_mode_set(rtk_uint32 pin, rtk_gpio_mode_t mode); + +/* Function Name: + * rtk_gpio_mode_get + * Description: + * Get GPIO mode. + * Input: + * pin - GPIO pin + * Output: + * pMode - GPIO mode + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_OUT_OF_RANGE - input parameter out of range. + * RT_ERR_NULL_POINTER - input parameter is null pointer. + * Note: + * The API can get GPIO mode. + */ +extern rtk_api_ret_t rtk_gpio_mode_get(rtk_uint32 pin, rtk_gpio_mode_t *pMode); + +/* Function Name: + * rtk_gpio_aclEnClear_set + * Description: + * Set GPIO acl clear. + * Input: + * pin - GPIO pin + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_OUT_OF_RANGE - input parameter out of range. + * Note: + * The API can set GPIO ACL clear. + */ +extern rtk_api_ret_t rtk_gpio_aclEnClear_set(rtk_uint32 pin); + +/* Function Name: + * rtk_gpio_aclEnClear_get + * Description: + * Get GPIO acl clear. + * Input: + * pin - GPIO pin + * Output: + * pAclEn - GPIO acl enable + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_OUT_OF_RANGE - input parameter out of range. + * RT_ERR_NULL_POINTER - input parameter is null pointer. + * Note: + * The API can get GPIO acl enable clear. + */ +extern rtk_api_ret_t rtk_gpio_aclEnClear_get(rtk_uint32 pin, rtk_enable_t *pAclEn); + + +#endif /*__RTK_API_GPIO_H__*/ \ No newline at end of file diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/i2c.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/i2c.c new file mode 100644 index 00000000..499331a3 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/i2c.c @@ -0,0 +1,235 @@ +/* Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision: 63932 $ + * $Date: 2015-12-08 14:06:29 +0800 (周二, 08 å二月 2015) $ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8367C + * Feature : Here is a list of all functions and variables in i2c module. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include + + +/* Function Name: + * rtk_i2c_init + * Description: + * I2C smart function initialization. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * Note: + * This API is used to initialize EEE status. + * need used GPIO pins + * OpenDrain and clock + */ +rtk_api_ret_t rtk_i2c_init(void) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->i2c_init) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->i2c_init(); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_i2c_mode_set + * Description: + * Set I2C data byte-order. + * Input: + * i2cmode - byte-order mode + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_INPUT - Invalid input parameter. + * Note: + * This API can set I2c traffic's byte-order . + */ +rtk_api_ret_t rtk_i2c_mode_set( rtk_I2C_16bit_mode_t i2cmode ) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->i2c_mode_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->i2c_mode_set(i2cmode); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_i2c_mode_get + * Description: + * Get i2c traffic byte-order setting. + * Input: + * None + * Output: + * pI2cMode - i2c byte-order + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_NULL_POINTER - input parameter is null pointer + * Note: + * The API can get i2c traffic byte-order setting. + */ +rtk_api_ret_t rtk_i2c_mode_get( rtk_I2C_16bit_mode_t * pI2cMode) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->i2c_mode_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->i2c_mode_get(pI2cMode); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_i2c_gpioPinGroup_set + * Description: + * Set i2c SDA & SCL used GPIO pins group. + * Input: + * pins_group - GPIO pins group + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_INPUT - Invalid input parameter. + * Note: + * The API can set i2c used gpio pins group. + * There are three group pins could be used + */ +rtk_api_ret_t rtk_i2c_gpioPinGroup_set( rtk_I2C_gpio_pin_t pins_group ) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->i2c_gpioPinGroup_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->i2c_gpioPinGroup_set(pins_group); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_i2c_gpioPinGroup_get + * Description: + * Get i2c SDA & SCL used GPIO pins group. + * Input: + * None + * Output: + * pPins_group - GPIO pins group + * Return: + * RT_ERR_OK - OK + * RT_ERR_NULL_POINTER - input parameter is null pointer + * Note: + * The API can get i2c used gpio pins group. + * There are three group pins could be used + */ +rtk_api_ret_t rtk_i2c_gpioPinGroup_get( rtk_I2C_gpio_pin_t * pPins_group ) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->i2c_gpioPinGroup_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->i2c_gpioPinGroup_get(pPins_group); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_i2c_data_read + * Description: + * read i2c slave device register. + * Input: + * deviceAddr - access Slave device address + * slaveRegAddr - access Slave register address + * Output: + * pRegData - read data + * Return: + * RT_ERR_OK - OK + * RT_ERR_NULL_POINTER - input parameter is null pointer + * Note: + * The API can access i2c slave and read i2c slave device register. + */ +rtk_api_ret_t rtk_i2c_data_read(rtk_uint8 deviceAddr, rtk_uint32 slaveRegAddr, rtk_uint32 *pRegData) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->i2c_data_read) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->i2c_data_read(deviceAddr, slaveRegAddr, pRegData); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_i2c_data_write + * Description: + * write data to i2c slave device register + * Input: + * deviceAddr - access Slave device address + * slaveRegAddr - access Slave register address + * regData - data to set + * Output: + * None + * Return: + * RT_ERR_OK - OK + * Note: + * The API can access i2c slave and setting i2c slave device register. + */ +rtk_api_ret_t rtk_i2c_data_write(rtk_uint8 deviceAddr, rtk_uint32 slaveRegAddr, rtk_uint32 regData) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->i2c_data_write) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->i2c_data_write(deviceAddr, slaveRegAddr, regData); + RTK_API_UNLOCK(); + + return retVal; +} + + + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/i2c.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/i2c.h new file mode 100644 index 00000000..3fd8ccf5 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/i2c.h @@ -0,0 +1,170 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8367/RTL8367C switch high-level API + * + * Feature : The file includes I2C module high-layer API defination + * + */ + + +#ifndef __RTK_API_I2C_H__ +#define __RTK_API_I2C_H__ +#include + +#define I2C_GPIO_MAX_GROUP (3) + +typedef enum rtk_I2C_16bit_mode_e{ + I2C_LSB_16BIT_MODE = 0, + I2C_70B_LSB_16BIT_MODE, + I2C_Mode_END +}rtk_I2C_16bit_mode_t; + + +typedef enum rtk_I2C_gpio_pin_e{ + I2C_GPIO_PIN_8_9 = 0, + I2C_GPIO_PIN_15_16 , + I2C_GPIO_PIN_35_36 , + I2C_GPIO_PIN_END +}rtk_I2C_gpio_pin_t; + + +/* Function Name: + * rtk_i2c_data_read + * Description: + * read i2c slave device register. + * Input: + * deviceAddr - access Slave device address + * slaveRegAddr - access Slave register address + * Output: + * pRegData - read data + * Return: + * RT_ERR_OK - OK + * RT_ERR_NULL_POINTER - input parameter is null pointer + * Note: + * The API can access i2c slave and read i2c slave device register. + */ +extern rtk_api_ret_t rtk_i2c_data_read(rtk_uint8 deviceAddr, rtk_uint32 slaveRegAddr, rtk_uint32 *pRegData); + +/* Function Name: + * rtk_i2c_data_write + * Description: + * write data to i2c slave device register + * Input: + * deviceAddr - access Slave device address + * slaveRegAddr - access Slave register address + * regData - data to set + * Output: + * None + * Return: + * RT_ERR_OK - OK + * Note: + * The API can access i2c slave and setting i2c slave device register. + */ +extern rtk_api_ret_t rtk_i2c_data_write(rtk_uint8 deviceAddr, rtk_uint32 slaveRegAddr, rtk_uint32 regData); + + +/* Function Name: + * rtk_i2c_init + * Description: + * I2C smart function initialization. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * Note: + * This API is used to initialize EEE status. + * need used GPIO pins + * OpenDrain and clock + */ +extern rtk_api_ret_t rtk_i2c_init(void); + +/* Function Name: + * rtk_i2c_mode_set + * Description: + * Set I2C data byte-order. + * Input: + * i2cmode - byte-order mode + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_INPUT - Invalid input parameter. + * Note: + * This API can set I2c traffic's byte-order . + */ +extern rtk_api_ret_t rtk_i2c_mode_set( rtk_I2C_16bit_mode_t i2cmode); + +/* Function Name: + * rtk_i2c_mode_get + * Description: + * Get i2c traffic byte-order setting. + * Input: + * None + * Output: + * pI2cMode - i2c byte-order + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_NULL_POINTER - input parameter is null pointer + * Note: + * The API can get i2c traffic byte-order setting. + */ +extern rtk_api_ret_t rtk_i2c_mode_get( rtk_I2C_16bit_mode_t * pI2cMode); + + +/* Function Name: + * rtk_i2c_gpioPinGroup_set + * Description: + * Set i2c SDA & SCL used GPIO pins group. + * Input: + * pins_group - GPIO pins group + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_INPUT - Invalid input parameter. + * Note: + * The API can set i2c used gpio pins group. + * There are three group pins could be used + */ +extern rtk_api_ret_t rtk_i2c_gpioPinGroup_set( rtk_I2C_gpio_pin_t pins_group); + +/* Function Name: + * rtk_i2c_gpioPinGroup_get + * Description: + * Get i2c SDA & SCL used GPIO pins group. + * Input: + * None + * Output: + * pPins_group - GPIO pins group + * Return: + * RT_ERR_OK - OK + * RT_ERR_NULL_POINTER - input parameter is null pointer + * Note: + * The API can get i2c used gpio pins group. + * There are three group pins could be used + */ +extern rtk_api_ret_t rtk_i2c_gpioPinGroup_get(rtk_I2C_gpio_pin_t * pPins_group); + + + + + + + +#endif + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/igmp.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/igmp.c new file mode 100644 index 00000000..ce0e9b60 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/igmp.c @@ -0,0 +1,1117 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8367C + * Feature : Here is a list of all functions and variables in IGMP module. + * + */ + +#include +#include +#include +#include + +#include + +/* Function Name: + * rtk_igmp_init + * Description: + * This API enables H/W IGMP and set a default initial configuration. + * Input: + * None. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API enables H/W IGMP and set a default initial configuration. + */ +rtk_api_ret_t rtk_igmp_init(void) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->igmp_init) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->igmp_init(); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_igmp_state_set + * Description: + * This API set H/W IGMP state. + * Input: + * enabled - H/W IGMP state + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error parameter + * Note: + * This API set H/W IGMP state. + */ +rtk_api_ret_t rtk_igmp_state_set(rtk_enable_t enabled) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->igmp_state_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->igmp_state_set(enabled); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_igmp_state_get + * Description: + * This API get H/W IGMP state. + * Input: + * None. + * Output: + * pEnabled - H/W IGMP state + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error parameter + * Note: + * This API set current H/W IGMP state. + */ +rtk_api_ret_t rtk_igmp_state_get(rtk_enable_t *pEnabled) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->igmp_state_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->igmp_state_get(pEnabled); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_igmp_static_router_port_set + * Description: + * Configure static router port + * Input: + * pPortmask - Static Port mask + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Error parameter + * Note: + * This API set static router port + */ +rtk_api_ret_t rtk_igmp_static_router_port_set(rtk_portmask_t *pPortmask) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->igmp_static_router_port_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->igmp_static_router_port_set(pPortmask); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_igmp_static_router_port_get + * Description: + * Get static router port + * Input: + * None. + * Output: + * pPortmask - Static port mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Error parameter + * Note: + * This API get static router port + */ +rtk_api_ret_t rtk_igmp_static_router_port_get(rtk_portmask_t *pPortmask) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->igmp_static_router_port_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->igmp_static_router_port_get(pPortmask); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_igmp_protocol_set + * Description: + * set IGMP/MLD protocol action + * Input: + * port - Port ID + * protocol - IGMP/MLD protocol + * action - Per-port and per-protocol IGMP action seeting + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Error parameter + * Note: + * This API set IGMP/MLD protocol action + */ +rtk_api_ret_t rtk_igmp_protocol_set(rtk_port_t port, rtk_igmp_protocol_t protocol, rtk_igmp_action_t action) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->igmp_protocol_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->igmp_protocol_set(port, protocol, action); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_igmp_protocol_get + * Description: + * set IGMP/MLD protocol action + * Input: + * port - Port ID + * protocol - IGMP/MLD protocol + * action - Per-port and per-protocol IGMP action seeting + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Error parameter + * Note: + * This API set IGMP/MLD protocol action + */ +rtk_api_ret_t rtk_igmp_protocol_get(rtk_port_t port, rtk_igmp_protocol_t protocol, rtk_igmp_action_t *pAction) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->igmp_protocol_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->igmp_protocol_get(port, protocol, pAction); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_igmp_fastLeave_set + * Description: + * set IGMP/MLD FastLeave state + * Input: + * state - ENABLED: Enable FastLeave, DISABLED: disable FastLeave + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_INPUT - Error Input + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API set IGMP/MLD FastLeave state + */ +rtk_api_ret_t rtk_igmp_fastLeave_set(rtk_enable_t state) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->igmp_fastLeave_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->igmp_fastLeave_set(state); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_igmp_fastLeave_get + * Description: + * get IGMP/MLD FastLeave state + * Input: + * None + * Output: + * pState - ENABLED: Enable FastLeave, DISABLED: disable FastLeave + * Return: + * RT_ERR_OK - OK + * RT_ERR_NULL_POINTER - NULL pointer + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API get IGMP/MLD FastLeave state + */ +rtk_api_ret_t rtk_igmp_fastLeave_get(rtk_enable_t *pState) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->igmp_fastLeave_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->igmp_fastLeave_get(pState); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_igmp_maxGroup_set + * Description: + * Set per port multicast group learning limit. + * Input: + * port - Port ID + * group - The number of multicast group learning limit. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_PORT_ID - Error Port ID + * RT_ERR_OUT_OF_RANGE - parameter out of range + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API set per port multicast group learning limit. + */ +rtk_api_ret_t rtk_igmp_maxGroup_set(rtk_port_t port, rtk_uint32 group) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->igmp_maxGroup_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->igmp_maxGroup_set(port, group); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_igmp_maxGroup_get + * Description: + * Get per port multicast group learning limit. + * Input: + * port - Port ID + * Output: + * pGroup - The number of multicast group learning limit. + * Return: + * RT_ERR_OK - OK + * RT_ERR_PORT_ID - Error Port ID + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API get per port multicast group learning limit. + */ +rtk_api_ret_t rtk_igmp_maxGroup_get(rtk_port_t port, rtk_uint32 *pGroup) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->igmp_maxGroup_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->igmp_maxGroup_get(port, pGroup); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_igmp_currentGroup_get + * Description: + * Get per port multicast group learning count. + * Input: + * port - Port ID + * Output: + * pGroup - The number of multicast group learning count. + * Return: + * RT_ERR_OK - OK + * RT_ERR_PORT_ID - Error Port ID + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API get per port multicast group learning count. + */ +rtk_api_ret_t rtk_igmp_currentGroup_get(rtk_port_t port, rtk_uint32 *pGroup) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->igmp_currentGroup_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->igmp_currentGroup_get(port, pGroup); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_igmp_tableFullAction_set + * Description: + * set IGMP/MLD Table Full Action + * Input: + * action - Table Full Action + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_INPUT - Error Input + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +rtk_api_ret_t rtk_igmp_tableFullAction_set(rtk_igmp_tableFullAction_t action) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->igmp_tableFullAction_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->igmp_tableFullAction_set(action); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_igmp_tableFullAction_get + * Description: + * get IGMP/MLD Table Full Action + * Input: + * None + * Output: + * pAction - Table Full Action + * Return: + * RT_ERR_OK - OK + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +rtk_api_ret_t rtk_igmp_tableFullAction_get(rtk_igmp_tableFullAction_t *pAction) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->igmp_tableFullAction_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->igmp_tableFullAction_get(pAction); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_igmp_checksumErrorAction_set + * Description: + * set IGMP/MLD Checksum Error Action + * Input: + * action - Checksum error Action + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_INPUT - Error Input + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +rtk_api_ret_t rtk_igmp_checksumErrorAction_set(rtk_igmp_checksumErrorAction_t action) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->igmp_checksumErrorAction_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->igmp_checksumErrorAction_set(action); + RTK_API_UNLOCK(); + + return retVal; +} + + +/* Function Name: + * rtk_igmp_checksumErrorAction_get + * Description: + * get IGMP/MLD Checksum Error Action + * Input: + * None + * Output: + * pAction - Checksum error Action + * Return: + * RT_ERR_OK - OK + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +rtk_api_ret_t rtk_igmp_checksumErrorAction_get(rtk_igmp_checksumErrorAction_t *pAction) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->igmp_checksumErrorAction_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->igmp_checksumErrorAction_get(pAction); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_igmp_leaveTimer_set + * Description: + * set IGMP/MLD Leave timer + * Input: + * timer - Leave timer + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_INPUT - Error Input + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +rtk_api_ret_t rtk_igmp_leaveTimer_set(rtk_uint32 timer) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->igmp_leaveTimer_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->igmp_leaveTimer_set(timer); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_igmp_leaveTimer_get + * Description: + * get IGMP/MLD Leave timer + * Input: + * None + * Output: + * pTimer - Leave Timer. + * Return: + * RT_ERR_OK - OK + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +rtk_api_ret_t rtk_igmp_leaveTimer_get(rtk_uint32 *pTimer) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->igmp_leaveTimer_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->igmp_leaveTimer_get(pTimer); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_igmp_queryInterval_set + * Description: + * set IGMP/MLD Query Interval + * Input: + * interval - Query Interval + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_INPUT - Error Input + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +rtk_api_ret_t rtk_igmp_queryInterval_set(rtk_uint32 interval) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->igmp_queryInterval_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->igmp_queryInterval_set(interval); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_igmp_queryInterval_get + * Description: + * get IGMP/MLD Query Interval + * Input: + * None. + * Output: + * pInterval - Query Interval + * Return: + * RT_ERR_OK - OK + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +rtk_api_ret_t rtk_igmp_queryInterval_get(rtk_uint32 *pInterval) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->igmp_queryInterval_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->igmp_queryInterval_get(pInterval); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_igmp_robustness_set + * Description: + * set IGMP/MLD Robustness value + * Input: + * robustness - Robustness value + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_INPUT - Error Input + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +rtk_api_ret_t rtk_igmp_robustness_set(rtk_uint32 robustness) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->igmp_robustness_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->igmp_robustness_set(robustness); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_igmp_robustness_get + * Description: + * get IGMP/MLD Robustness value + * Input: + * None + * Output: + * pRobustness - Robustness value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +rtk_api_ret_t rtk_igmp_robustness_get(rtk_uint32 *pRobustness) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->igmp_robustness_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->igmp_robustness_get(pRobustness); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_igmp_dynamicRouterRortAllow_set + * Description: + * Configure dynamic router port allow option + * Input: + * pPortmask - Dynamic Port allow mask + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Error parameter + * Note: + * + */ +rtk_api_ret_t rtk_igmp_dynamicRouterPortAllow_set(rtk_portmask_t *pPortmask) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->igmp_dynamicRouterPortAllow_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->igmp_dynamicRouterPortAllow_set(pPortmask); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_igmp_dynamicRouterRortAllow_get + * Description: + * Get dynamic router port allow option + * Input: + * None. + * Output: + * pPortmask - Dynamic Port allow mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Error parameter + * Note: + * + */ +rtk_api_ret_t rtk_igmp_dynamicRouterPortAllow_get(rtk_portmask_t *pPortmask) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->igmp_dynamicRouterPortAllow_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->igmp_dynamicRouterPortAllow_get(pPortmask); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_igmp_dynamicRouterPort_get + * Description: + * Get dynamic router port + * Input: + * None. + * Output: + * pDynamicRouterPort - Dynamic Router Port + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Error parameter + * Note: + * + */ +rtk_api_ret_t rtk_igmp_dynamicRouterPort_get(rtk_igmp_dynamicRouterPort_t *pDynamicRouterPort) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->igmp_dynamicRouterPort_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->igmp_dynamicRouterPort_get(pDynamicRouterPort); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_igmp_suppressionEnable_set + * Description: + * Configure IGMPv1/v2 & MLDv1 Report/Leave/Done suppression + * Input: + * reportSuppression - Report suppression + * leaveSuppression - Leave suppression + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + * + */ +rtk_api_ret_t rtk_igmp_suppressionEnable_set(rtk_enable_t reportSuppression, rtk_enable_t leaveSuppression) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->igmp_suppressionEnable_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->igmp_suppressionEnable_set(reportSuppression, leaveSuppression); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_igmp_suppressionEnable_get + * Description: + * Get IGMPv1/v2 & MLDv1 Report/Leave/Done suppression + * Input: + * None + * Output: + * pReportSuppression - Report suppression + * pLeaveSuppression - Leave suppression + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * + */ +rtk_api_ret_t rtk_igmp_suppressionEnable_get(rtk_enable_t *pReportSuppression, rtk_enable_t *pLeaveSuppression) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->igmp_suppressionEnable_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->igmp_suppressionEnable_get(pReportSuppression, pLeaveSuppression); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_igmp_portRxPktEnable_set + * Description: + * Configure IGMP/MLD RX Packet configuration + * Input: + * port - Port ID + * pRxCfg - RX Packet Configuration + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * + */ +rtk_api_ret_t rtk_igmp_portRxPktEnable_set(rtk_port_t port, rtk_igmp_rxPktEnable_t *pRxCfg) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->igmp_portRxPktEnable_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->igmp_portRxPktEnable_set(port, pRxCfg); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_igmp_portRxPktEnable_get + * Description: + * Get IGMP/MLD RX Packet configuration + * Input: + * port - Port ID + * pRxCfg - RX Packet Configuration + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * + */ +rtk_api_ret_t rtk_igmp_portRxPktEnable_get(rtk_port_t port, rtk_igmp_rxPktEnable_t *pRxCfg) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->igmp_portRxPktEnable_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->igmp_portRxPktEnable_get(port, pRxCfg); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_igmp_groupInfo_get + * Description: + * Get IGMP/MLD Group database + * Input: + * indes - Index (0~255) + * Output: + * pGroup - Group database information. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * + */ +rtk_api_ret_t rtk_igmp_groupInfo_get(rtk_uint32 index, rtk_igmp_groupInfo_t *pGroup) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->igmp_groupInfo_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->igmp_groupInfo_get(index, pGroup); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_igmp_ReportLeaveFwdAction_set + * Description: + * Set Report Leave packet forwarding action + * Input: + * action - Action + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + * + */ +rtk_api_ret_t rtk_igmp_ReportLeaveFwdAction_set(rtk_igmp_ReportLeaveFwdAct_t action) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->igmp_ReportLeaveFwdAction_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->igmp_ReportLeaveFwdAction_set(action); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_igmp_ReportLeaveFwdAction_get + * Description: + * Get Report Leave packet forwarding action + * Input: + * action - Action + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * RT_ERR_NULL_POINTER - Null Pointer + * Note: + * + */ +rtk_api_ret_t rtk_igmp_ReportLeaveFwdAction_get(rtk_igmp_ReportLeaveFwdAct_t *pAction) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->igmp_ReportLeaveFwdAction_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->igmp_ReportLeaveFwdAction_get(pAction); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_igmp_dropLeaveZeroEnable_set + * Description: + * Set the function of droppping Leave packet with group IP = 0.0.0.0 + * Input: + * enabled - Action 1: drop, 0:pass + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + * + */ +rtk_api_ret_t rtk_igmp_dropLeaveZeroEnable_set(rtk_enable_t enabled) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->igmp_dropLeaveZeroEnable_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->igmp_dropLeaveZeroEnable_set(enabled); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_igmp_dropLeaveZeroEnable_get + * Description: + * Get the function of droppping Leave packet with group IP = 0.0.0.0 + * Input: + * None + * Output: + * pEnabled. - Action 1: drop, 0:pass + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * RT_ERR_NULL_POINTER - Null Pointer + * Note: + * + */ +rtk_api_ret_t rtk_igmp_dropLeaveZeroEnable_get(rtk_enable_t *pEnabled) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->igmp_dropLeaveZeroEnable_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->igmp_dropLeaveZeroEnable_get(pEnabled); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_igmp_bypassGroupRange_set + * Description: + * Set Bypass group + * Input: + * group - bypassed group + * enabled - enabled 1: Bypassed, 0: not bypass + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + * + */ +rtk_api_ret_t rtk_igmp_bypassGroupRange_set(rtk_igmp_bypassGroup_t group, rtk_enable_t enabled) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->igmp_bypassGroupRange_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->igmp_bypassGroupRange_set(group, enabled); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_igmp_bypassGroupRange_get + * Description: + * get Bypass group + * Input: + * group - bypassed group + * Output: + * pEnable - enabled 1: Bypassed, 0: not bypass + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * RT_ERR_NULL_POINTER - Null Pointer + * Note: + * + */ +rtk_api_ret_t rtk_igmp_bypassGroupRange_get(rtk_igmp_bypassGroup_t group, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->igmp_bypassGroupRange_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->igmp_bypassGroupRange_get(group, pEnable); + RTK_API_UNLOCK(); + + return retVal; +} + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/igmp.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/igmp.h new file mode 100644 index 00000000..dafb482a --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/igmp.h @@ -0,0 +1,771 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8367/RTL8367C switch high-level API + * + * Feature : The file includes IGMP module high-layer API defination + * + */ + +#ifndef __RTK_API_IGMP_H__ +#define __RTK_API_IGMP_H__ + +/* + * Data Type Declaration + */ +typedef enum rtk_igmp_type_e +{ + IGMP_IPV4 = 0, + IGMP_PPPOE_IPV4, + IGMP_MLD, + IGMP_PPPOE_MLD, + IGMP_TYPE_END +} rtk_igmp_type_t; + +typedef enum rtk_trap_igmp_action_e +{ + IGMP_ACTION_FORWARD = 0, + IGMP_ACTION_TRAP2CPU, + IGMP_ACTION_DROP, + IGMP_ACTION_ASIC, + IGMP_ACTION_END +} rtk_igmp_action_t; + +typedef enum rtk_igmp_protocol_e +{ + PROTOCOL_IGMPv1 = 0, + PROTOCOL_IGMPv2, + PROTOCOL_IGMPv3, + PROTOCOL_MLDv1, + PROTOCOL_MLDv2, + PROTOCOL_END +} rtk_igmp_protocol_t; + +typedef enum rtk_igmp_tableFullAction_e +{ + IGMP_TABLE_FULL_FORWARD = 0, + IGMP_TABLE_FULL_DROP, + IGMP_TABLE_FULL_TRAP, + IGMP_TABLE_FULL_OP_END +}rtk_igmp_tableFullAction_t; + +typedef enum rtk_igmp_checksumErrorAction_e +{ + IGMP_CRC_ERR_DROP = 0, + IGMP_CRC_ERR_TRAP, + IGMP_CRC_ERR_FORWARD, + IGMP_CRC_ERR_OP_END +}rtk_igmp_checksumErrorAction_t; + +typedef enum rtk_igmp_bypassGroup_e +{ + IGMP_BYPASS_224_0_0_X = 0, + IGMP_BYPASS_224_0_1_X, + IGMP_BYPASS_239_255_255_X, + IGMP_BYPASS_IPV6_00XX, + IGMP_BYPASS_GROUP_END +}rtk_igmp_bypassGroup_t; + + +typedef struct rtk_igmp_dynamicRouterPort_s +{ + rtk_enable_t dynamicRouterPort0Valid; + rtk_port_t dynamicRouterPort0; + rtk_uint32 dynamicRouterPort0Timer; + rtk_enable_t dynamicRouterPort1Valid; + rtk_port_t dynamicRouterPort1; + rtk_uint32 dynamicRouterPort1Timer; + +}rtk_igmp_dynamicRouterPort_t; + +typedef struct rtk_igmp_rxPktEnable_s +{ + rtk_enable_t rxQuery; + rtk_enable_t rxReport; + rtk_enable_t rxLeave; + rtk_enable_t rxMRP; + rtk_enable_t rxMcast; +}rtk_igmp_rxPktEnable_t; + +typedef struct rtk_igmp_groupInfo_s +{ + rtk_enable_t valid; + rtk_portmask_t member; + rtk_uint32 timer[RTK_PORT_MAX]; + rtk_uint32 reportSuppFlag; +}rtk_igmp_groupInfo_t; + +typedef enum rtk_igmp_ReportLeaveFwdAct_e +{ + IGMP_REPORT_LEAVE_TO_ROUTER = 0, + IGMP_REPORT_LEAVE_TO_ALLPORT, + IGMP_REPORT_LEAVE_TO_ROUTER_PORT_ADV, + IGMP_REPORT_LEAVE_ACT_END +}rtk_igmp_ReportLeaveFwdAct_t; + +/* Function Name: + * rtk_igmp_init + * Description: + * This API enables H/W IGMP and set a default initial configuration. + * Input: + * None. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API enables H/W IGMP and set a default initial configuration. + */ +extern rtk_api_ret_t rtk_igmp_init(void); + +/* Function Name: + * rtk_igmp_state_set + * Description: + * This API set H/W IGMP state. + * Input: + * enabled - H/W IGMP state + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error parameter + * Note: + * This API set H/W IGMP state. + */ +extern rtk_api_ret_t rtk_igmp_state_set(rtk_enable_t enabled); + +/* Function Name: + * rtk_igmp_state_get + * Description: + * This API get H/W IGMP state. + * Input: + * None. + * Output: + * pEnabled - H/W IGMP state + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error parameter + * Note: + * This API set current H/W IGMP state. + */ +extern rtk_api_ret_t rtk_igmp_state_get(rtk_enable_t *pEnabled); + +/* Function Name: + * rtk_igmp_static_router_port_set + * Description: + * Configure static router port + * Input: + * pPortmask - Static Port mask + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Error parameter + * Note: + * This API set static router port + */ +extern rtk_api_ret_t rtk_igmp_static_router_port_set(rtk_portmask_t *pPortmask); + +/* Function Name: + * rtk_igmp_static_router_port_get + * Description: + * Get static router port + * Input: + * None. + * Output: + * pPortmask - Static port mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Error parameter + * Note: + * This API get static router port + */ +extern rtk_api_ret_t rtk_igmp_static_router_port_get(rtk_portmask_t *pPortmask); + +/* Function Name: + * rtk_igmp_protocol_set + * Description: + * set IGMP/MLD protocol action + * Input: + * port - Port ID + * protocol - IGMP/MLD protocol + * action - Per-port and per-protocol IGMP action seeting + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Error parameter + * Note: + * This API set IGMP/MLD protocol action + */ +extern rtk_api_ret_t rtk_igmp_protocol_set(rtk_port_t port, rtk_igmp_protocol_t protocol, rtk_igmp_action_t action); + +/* Function Name: + * rtk_igmp_protocol_get + * Description: + * set IGMP/MLD protocol action + * Input: + * port - Port ID + * protocol - IGMP/MLD protocol + * action - Per-port and per-protocol IGMP action seeting + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Error parameter + * Note: + * This API set IGMP/MLD protocol action + */ +extern rtk_api_ret_t rtk_igmp_protocol_get(rtk_port_t port, rtk_igmp_protocol_t protocol, rtk_igmp_action_t *pAction); + +/* Function Name: + * rtk_igmp_fastLeave_set + * Description: + * set IGMP/MLD FastLeave state + * Input: + * state - ENABLED: Enable FastLeave, DISABLED: disable FastLeave + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_INPUT - Error Input + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API set IGMP/MLD FastLeave state + */ +extern rtk_api_ret_t rtk_igmp_fastLeave_set(rtk_enable_t state); + +/* Function Name: + * rtk_igmp_fastLeave_get + * Description: + * get IGMP/MLD FastLeave state + * Input: + * None + * Output: + * pState - ENABLED: Enable FastLeave, DISABLED: disable FastLeave + * Return: + * RT_ERR_OK - OK + * RT_ERR_NULL_POINTER - NULL pointer + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API get IGMP/MLD FastLeave state + */ +extern rtk_api_ret_t rtk_igmp_fastLeave_get(rtk_enable_t *pState); + +/* Function Name: + * rtk_igmp_maxGroup_set + * Description: + * Set per port multicast group learning limit. + * Input: + * port - Port ID + * group - The number of multicast group learning limit. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_PORT_ID - Error Port ID + * RT_ERR_OUT_OF_RANGE - parameter out of range + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API set per port multicast group learning limit. + */ +extern rtk_api_ret_t rtk_igmp_maxGroup_set(rtk_port_t port, rtk_uint32 group); + +/* Function Name: + * rtk_igmp_maxGroup_get + * Description: + * Get per port multicast group learning limit. + * Input: + * port - Port ID + * Output: + * pGroup - The number of multicast group learning limit. + * Return: + * RT_ERR_OK - OK + * RT_ERR_PORT_ID - Error Port ID + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API get per port multicast group learning limit. + */ +extern rtk_api_ret_t rtk_igmp_maxGroup_get(rtk_port_t port, rtk_uint32 *pGroup); + +/* Function Name: + * rtk_igmp_currentGroup_get + * Description: + * Get per port multicast group learning count. + * Input: + * port - Port ID + * Output: + * pGroup - The number of multicast group learning count. + * Return: + * RT_ERR_OK - OK + * RT_ERR_PORT_ID - Error Port ID + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API get per port multicast group learning count. + */ +extern rtk_api_ret_t rtk_igmp_currentGroup_get(rtk_port_t port, rtk_uint32 *pGroup); + +/* Function Name: + * rtk_igmp_tableFullAction_set + * Description: + * set IGMP/MLD Table Full Action + * Input: + * action - Table Full Action + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_INPUT - Error Input + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +extern rtk_api_ret_t rtk_igmp_tableFullAction_set(rtk_igmp_tableFullAction_t action); + +/* Function Name: + * rtk_igmp_tableFullAction_get + * Description: + * get IGMP/MLD Table Full Action + * Input: + * None + * Output: + * pAction - Table Full Action + * Return: + * RT_ERR_OK - OK + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +extern rtk_api_ret_t rtk_igmp_tableFullAction_get(rtk_igmp_tableFullAction_t *pAction); + +/* Function Name: + * rtk_igmp_checksumErrorAction_set + * Description: + * set IGMP/MLD Checksum Error Action + * Input: + * action - Checksum error Action + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_INPUT - Error Input + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +extern rtk_api_ret_t rtk_igmp_checksumErrorAction_set(rtk_igmp_checksumErrorAction_t action); + +/* Function Name: + * rtk_igmp_checksumErrorAction_get + * Description: + * get IGMP/MLD Checksum Error Action + * Input: + * None + * Output: + * pAction - Checksum error Action + * Return: + * RT_ERR_OK - OK + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +extern rtk_api_ret_t rtk_igmp_checksumErrorAction_get(rtk_igmp_checksumErrorAction_t *pAction); + +/* Function Name: + * rtk_igmp_leaveTimer_set + * Description: + * set IGMP/MLD Leave timer + * Input: + * timer - Leave timer + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_INPUT - Error Input + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +extern rtk_api_ret_t rtk_igmp_leaveTimer_set(rtk_uint32 timer); + +/* Function Name: + * rtk_igmp_leaveTimer_get + * Description: + * get IGMP/MLD Leave timer + * Input: + * None + * Output: + * pTimer - Leave Timer. + * Return: + * RT_ERR_OK - OK + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +extern rtk_api_ret_t rtk_igmp_leaveTimer_get(rtk_uint32 *pTimer); + +/* Function Name: + * rtk_igmp_queryInterval_set + * Description: + * set IGMP/MLD Query Interval + * Input: + * interval - Query Interval + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_INPUT - Error Input + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +extern rtk_api_ret_t rtk_igmp_queryInterval_set(rtk_uint32 interval); + +/* Function Name: + * rtk_igmp_queryInterval_get + * Description: + * get IGMP/MLD Query Interval + * Input: + * None. + * Output: + * pInterval - Query Interval + * Return: + * RT_ERR_OK - OK + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +extern rtk_api_ret_t rtk_igmp_queryInterval_get(rtk_uint32 *pInterval); + +/* Function Name: + * rtk_igmp_robustness_set + * Description: + * set IGMP/MLD Robustness value + * Input: + * robustness - Robustness value + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_INPUT - Error Input + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +extern rtk_api_ret_t rtk_igmp_robustness_set(rtk_uint32 robustness); + +/* Function Name: + * rtk_igmp_robustness_get + * Description: + * get IGMP/MLD Robustness value + * Input: + * None + * Output: + * pRobustness - Robustness value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +extern rtk_api_ret_t rtk_igmp_robustness_get(rtk_uint32 *pRobustness); + +/* Function Name: + * rtk_igmp_dynamicRouterRortAllow_set + * Description: + * Configure dynamic router port allow option + * Input: + * pPortmask - Dynamic Port allow mask + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Error parameter + * Note: + * + */ +extern rtk_api_ret_t rtk_igmp_dynamicRouterPortAllow_set(rtk_portmask_t *pPortmask); + +/* Function Name: + * rtk_igmp_dynamicRouterRortAllow_get + * Description: + * Get dynamic router port allow option + * Input: + * None. + * Output: + * pPortmask - Dynamic Port allow mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Error parameter + * Note: + * + */ +extern rtk_api_ret_t rtk_igmp_dynamicRouterPortAllow_get(rtk_portmask_t *pPortmask); + +/* Function Name: + * rtk_igmp_dynamicRouterPort_get + * Description: + * Get dynamic router port + * Input: + * None. + * Output: + * pDynamicRouterPort - Dynamic Router Port + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Error parameter + * Note: + * + */ +extern rtk_api_ret_t rtk_igmp_dynamicRouterPort_get(rtk_igmp_dynamicRouterPort_t *pDynamicRouterPort); + +/* Function Name: + * rtk_igmp_suppressionEnable_set + * Description: + * Configure IGMPv1/v2 & MLDv1 Report/Leave/Done suppression + * Input: + * reportSuppression - Report suppression + * leaveSuppression - Leave suppression + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + * + */ +extern rtk_api_ret_t rtk_igmp_suppressionEnable_set(rtk_enable_t reportSuppression, rtk_enable_t leaveSuppression); + +/* Function Name: + * rtk_igmp_suppressionEnable_get + * Description: + * Get IGMPv1/v2 & MLDv1 Report/Leave/Done suppression + * Input: + * None + * Output: + * pReportSuppression - Report suppression + * pLeaveSuppression - Leave suppression + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * + */ +extern rtk_api_ret_t rtk_igmp_suppressionEnable_get(rtk_enable_t *pReportSuppression, rtk_enable_t *pLeaveSuppression); + +/* Function Name: + * rtk_igmp_portRxPktEnable_set + * Description: + * Configure IGMP/MLD RX Packet configuration + * Input: + * port - Port ID + * pRxCfg - RX Packet Configuration + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * + */ +extern rtk_api_ret_t rtk_igmp_portRxPktEnable_set(rtk_port_t port, rtk_igmp_rxPktEnable_t *pRxCfg); + +/* Function Name: + * rtk_igmp_portRxPktEnable_get + * Description: + * Get IGMP/MLD RX Packet configuration + * Input: + * port - Port ID + * pRxCfg - RX Packet Configuration + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * + */ +extern rtk_api_ret_t rtk_igmp_portRxPktEnable_get(rtk_port_t port, rtk_igmp_rxPktEnable_t *pRxCfg); + +/* Function Name: + * rtk_igmp_groupInfo_get + * Description: + * Get IGMP/MLD Group database + * Input: + * indes - Index (0~255) + * Output: + * pGroup - Group database information. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * + */ +extern rtk_api_ret_t rtk_igmp_groupInfo_get(rtk_uint32 index, rtk_igmp_groupInfo_t *pGroup); + +/* Function Name: + * rtk_igmp_ReportLeaveFwdAction_set + * Description: + * Set Report Leave packet forwarding action + * Input: + * action - Action + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + * + */ +extern rtk_api_ret_t rtk_igmp_ReportLeaveFwdAction_set(rtk_igmp_ReportLeaveFwdAct_t action); + +/* Function Name: + * rtk_igmp_ReportLeaveFwdAction_get + * Description: + * Get Report Leave packet forwarding action + * Input: + * action - Action + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * RT_ERR_NULL_POINTER - Null Pointer + * Note: + * + */ +extern rtk_api_ret_t rtk_igmp_ReportLeaveFwdAction_get(rtk_igmp_ReportLeaveFwdAct_t *pAction); + +/* Function Name: + * rtk_igmp_dropLeaveZeroEnable_set + * Description: + * Set the function of droppping Leave packet with group IP = 0.0.0.0 + * Input: + * enabled - Action 1: drop, 0:pass + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + * + */ +extern rtk_api_ret_t rtk_igmp_dropLeaveZeroEnable_set(rtk_enable_t enabled); + +/* Function Name: + * rtk_igmp_dropLeaveZeroEnable_get + * Description: + * Get the function of droppping Leave packet with group IP = 0.0.0.0 + * Input: + * None + * Output: + * pEnabled. - Action 1: drop, 0:pass + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * RT_ERR_NULL_POINTER - Null Pointer + * Note: + * + */ +extern rtk_api_ret_t rtk_igmp_dropLeaveZeroEnable_get(rtk_enable_t *pEnabled); + +/* Function Name: + * rtk_igmp_bypassGroupRange_set + * Description: + * Set Bypass group + * Input: + * group - bypassed group + * enabled - enabled 1: Bypassed, 0: not bypass + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + * + */ +extern rtk_api_ret_t rtk_igmp_bypassGroupRange_set(rtk_igmp_bypassGroup_t group, rtk_enable_t enabled); + +/* Function Name: + * rtk_igmp_bypassGroupRange_get + * Description: + * get Bypass group + * Input: + * group - bypassed group + * Output: + * pEnable - enabled 1: Bypassed, 0: not bypass + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * RT_ERR_NULL_POINTER - Null Pointer + * Note: + * + */ +extern rtk_api_ret_t rtk_igmp_bypassGroupRange_get(rtk_igmp_bypassGroup_t group, rtk_enable_t *pEnable); + +#endif /* __RTK_API_IGMP_H__ */ diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/interrupt.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/interrupt.c new file mode 100644 index 00000000..52b45c1a --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/interrupt.c @@ -0,0 +1,289 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8367C + * Feature : Here is a list of all functions and variables in Interrupt module. + * + */ + +#include +#include +#include +#include + +#include + +/* Function Name: + * rtk_int_polarity_set + * Description: + * Set interrupt polarity configuration. + * Input: + * type - Interruptpolarity type. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can set interrupt polarity configuration. + */ +rtk_api_ret_t rtk_int_polarity_set(rtk_int_polarity_t type) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->int_polarity_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->int_polarity_set(type); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_int_polarity_get + * Description: + * Get interrupt polarity configuration. + * Input: + * None + * Output: + * pType - Interruptpolarity type. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can get interrupt polarity configuration. + */ +rtk_api_ret_t rtk_int_polarity_get(rtk_int_polarity_t *pType) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->int_polarity_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->int_polarity_get(pType); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_int_control_set + * Description: + * Set interrupt trigger status configuration. + * Input: + * type - Interrupt type. + * enable - Interrupt status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * The API can set interrupt status configuration. + * The interrupt trigger status is shown in the following: + * - INT_TYPE_LINK_STATUS + * - INT_TYPE_METER_EXCEED + * - INT_TYPE_LEARN_LIMIT + * - INT_TYPE_LINK_SPEED + * - INT_TYPE_CONGEST + * - INT_TYPE_GREEN_FEATURE + * - INT_TYPE_LOOP_DETECT + * - INT_TYPE_8051, + * - INT_TYPE_CABLE_DIAG, + * - INT_TYPE_ACL, + * - INT_TYPE_SLIENT + */ +rtk_api_ret_t rtk_int_control_set(rtk_int_type_t type, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->int_control_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->int_control_set(type, enable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_int_control_get + * Description: + * Get interrupt trigger status configuration. + * Input: + * type - Interrupt type. + * Output: + * pEnable - Interrupt status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get interrupt status configuration. + * The interrupt trigger status is shown in the following: + * - INT_TYPE_LINK_STATUS + * - INT_TYPE_METER_EXCEED + * - INT_TYPE_LEARN_LIMIT + * - INT_TYPE_LINK_SPEED + * - INT_TYPE_CONGEST + * - INT_TYPE_GREEN_FEATURE + * - INT_TYPE_LOOP_DETECT + * - INT_TYPE_8051, + * - INT_TYPE_CABLE_DIAG, + * - INT_TYPE_ACL, + * - INT_TYPE_UPS, + * - INT_TYPE_SLIENT + */ +rtk_api_ret_t rtk_int_control_get(rtk_int_type_t type, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->int_control_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->int_control_get(type, pEnable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_int_status_set + * Description: + * Set interrupt trigger status to clean. + * Input: + * None + * Output: + * pStatusMask - Interrupt status bit mask. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can clean interrupt trigger status when interrupt happened. + * The interrupt trigger status is shown in the following: + * - INT_TYPE_LINK_STATUS (value[0] (Bit0)) + * - INT_TYPE_METER_EXCEED (value[0] (Bit1)) + * - INT_TYPE_LEARN_LIMIT (value[0] (Bit2)) + * - INT_TYPE_LINK_SPEED (value[0] (Bit3)) + * - INT_TYPE_CONGEST (value[0] (Bit4)) + * - INT_TYPE_GREEN_FEATURE (value[0] (Bit5)) + * - INT_TYPE_LOOP_DETECT (value[0] (Bit6)) + * - INT_TYPE_8051 (value[0] (Bit7)) + * - INT_TYPE_CABLE_DIAG (value[0] (Bit8)) + * - INT_TYPE_ACL (value[0] (Bit9)) + * - INT_TYPE_SLIENT (value[0] (Bit11)) + * The status will be cleared after execute this API. + */ +rtk_api_ret_t rtk_int_status_set(rtk_int_status_t *pStatusMask) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->int_status_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->int_status_set(pStatusMask); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_int_status_get + * Description: + * Get interrupt trigger status. + * Input: + * None + * Output: + * pStatusMask - Interrupt status bit mask. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get interrupt trigger status when interrupt happened. + * The interrupt trigger status is shown in the following: + * - INT_TYPE_LINK_STATUS (value[0] (Bit0)) + * - INT_TYPE_METER_EXCEED (value[0] (Bit1)) + * - INT_TYPE_LEARN_LIMIT (value[0] (Bit2)) + * - INT_TYPE_LINK_SPEED (value[0] (Bit3)) + * - INT_TYPE_CONGEST (value[0] (Bit4)) + * - INT_TYPE_GREEN_FEATURE (value[0] (Bit5)) + * - INT_TYPE_LOOP_DETECT (value[0] (Bit6)) + * - INT_TYPE_8051 (value[0] (Bit7)) + * - INT_TYPE_CABLE_DIAG (value[0] (Bit8)) + * - INT_TYPE_ACL (value[0] (Bit9)) + * - INT_TYPE_SLIENT (value[0] (Bit11)) + * + */ +rtk_api_ret_t rtk_int_status_get(rtk_int_status_t* pStatusMask) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->int_status_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->int_status_get(pStatusMask); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_int_advanceInfo_get + * Description: + * Get interrupt advanced information. + * Input: + * adv_type - Advanced interrupt type. + * Output: + * info - Information per type. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can get advanced information when interrupt happened. + * The status will be cleared after execute this API. + */ +rtk_api_ret_t rtk_int_advanceInfo_get(rtk_int_advType_t adv_type, rtk_int_info_t *pInfo) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->int_advanceInfo_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->int_advanceInfo_get(adv_type, pInfo); + RTK_API_UNLOCK(); + + return retVal; +} + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/interrupt.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/interrupt.h new file mode 100644 index 00000000..b94f904d --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/interrupt.h @@ -0,0 +1,257 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8367/RTL8367C switch high-level API + * + * Feature : The file includes Interrupt module high-layer API defination + * + */ + +#ifndef __RTK_API_INTERRUPT_H__ +#define __RTK_API_INTERRUPT_H__ + + +/* + * Data Type Declaration + */ +#define RTK_MAX_NUM_OF_INTERRUPT_TYPE 1 +#define RTK_MAX_NUM_OF_METER_OVER_MASK 2 + + +typedef struct rtk_int_status_s +{ + rtk_uint16 value[RTK_MAX_NUM_OF_INTERRUPT_TYPE]; +} rtk_int_status_t; + +typedef struct rtk_int_info_s +{ + rtk_portmask_t portMask; + rtk_uint32 meterMask[RTK_MAX_NUM_OF_METER_OVER_MASK]; + rtk_uint32 systemLearnOver; +}rtk_int_info_t; + +typedef enum rtk_int_type_e +{ + INT_TYPE_LINK_STATUS = 0, + INT_TYPE_METER_EXCEED, + INT_TYPE_LEARN_LIMIT, + INT_TYPE_LINK_SPEED, + INT_TYPE_CONGEST, + INT_TYPE_GREEN_FEATURE, + INT_TYPE_LOOP_DETECT, + INT_TYPE_8051, + INT_TYPE_CABLE_DIAG, + INT_TYPE_ACL, + INT_TYPE_RESERVED, /* Unused */ + INT_TYPE_SLIENT, + INT_TYPE_END +}rtk_int_type_t; + +typedef enum rtk_int_advType_e +{ + ADV_L2_LEARN_PORT_MASK = 0, + ADV_SPEED_CHANGE_PORT_MASK, + ADV_SPECIAL_CONGESTION_PORT_MASK, + ADV_PORT_LINKDOWN_PORT_MASK, + ADV_PORT_LINKUP_PORT_MASK, + ADV_METER_EXCEED_MASK, + ADV_RLDP_LOOPED, + ADV_RLDP_RELEASED, + ADV_END, +} rtk_int_advType_t; + +typedef enum rtk_int_polarity_e +{ + INT_POLAR_HIGH = 0, + INT_POLAR_LOW, + INT_POLAR_END +} rtk_int_polarity_t; + +/* Function Name: + * rtk_int_polarity_set + * Description: + * Set interrupt polarity configuration. + * Input: + * type - Interruptpolarity type. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can set interrupt polarity configuration. + */ +extern rtk_api_ret_t rtk_int_polarity_set(rtk_int_polarity_t type); + +/* Function Name: + * rtk_int_polarity_get + * Description: + * Get interrupt polarity configuration. + * Input: + * None + * Output: + * pType - Interruptpolarity type. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can get interrupt polarity configuration. + */ +extern rtk_api_ret_t rtk_int_polarity_get(rtk_int_polarity_t *pType); + +/* Function Name: + * rtk_int_control_set + * Description: + * Set interrupt trigger status configuration. + * Input: + * type - Interrupt type. + * enable - Interrupt status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * The API can set interrupt status configuration. + * The interrupt trigger status is shown in the following: + * - INT_TYPE_LINK_STATUS + * - INT_TYPE_METER_EXCEED + * - INT_TYPE_LEARN_LIMIT + * - INT_TYPE_LINK_SPEED + * - INT_TYPE_CONGEST + * - INT_TYPE_GREEN_FEATURE + * - INT_TYPE_LOOP_DETECT + * - INT_TYPE_8051, + * - INT_TYPE_CABLE_DIAG, + * - INT_TYPE_ACL, + * - INT_TYPE_SLIENT + */ +extern rtk_api_ret_t rtk_int_control_set(rtk_int_type_t type, rtk_enable_t enable); + +/* Function Name: + * rtk_int_control_get + * Description: + * Get interrupt trigger status configuration. + * Input: + * type - Interrupt type. + * Output: + * pEnable - Interrupt status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get interrupt status configuration. + * The interrupt trigger status is shown in the following: + * - INT_TYPE_LINK_STATUS + * - INT_TYPE_METER_EXCEED + * - INT_TYPE_LEARN_LIMIT + * - INT_TYPE_LINK_SPEED + * - INT_TYPE_CONGEST + * - INT_TYPE_GREEN_FEATURE + * - INT_TYPE_LOOP_DETECT + * - INT_TYPE_8051, + * - INT_TYPE_CABLE_DIAG, + * - INT_TYPE_ACL, + * - INT_TYPE_SLIENT + */ +extern rtk_api_ret_t rtk_int_control_get(rtk_int_type_t type, rtk_enable_t* pEnable); + +/* Function Name: + * rtk_int_status_set + * Description: + * Set interrupt trigger status to clean. + * Input: + * None + * Output: + * pStatusMask - Interrupt status bit mask. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can clean interrupt trigger status when interrupt happened. + * The interrupt trigger status is shown in the following: + * - INT_TYPE_LINK_STATUS (value[0] (Bit0)) + * - INT_TYPE_METER_EXCEED (value[0] (Bit1)) + * - INT_TYPE_LEARN_LIMIT (value[0] (Bit2)) + * - INT_TYPE_LINK_SPEED (value[0] (Bit3)) + * - INT_TYPE_CONGEST (value[0] (Bit4)) + * - INT_TYPE_GREEN_FEATURE (value[0] (Bit5)) + * - INT_TYPE_LOOP_DETECT (value[0] (Bit6)) + * - INT_TYPE_8051 (value[0] (Bit7)) + * - INT_TYPE_CABLE_DIAG (value[0] (Bit8)) + * - INT_TYPE_ACL (value[0] (Bit9)) + * - INT_TYPE_SLIENT (value[0] (Bit11)) + * The status will be cleared after execute this API. + */ +extern rtk_api_ret_t rtk_int_status_set(rtk_int_status_t *pStatusMask); + +/* Function Name: + * rtk_int_status_get + * Description: + * Get interrupt trigger status. + * Input: + * None + * Output: + * pStatusMask - Interrupt status bit mask. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get interrupt trigger status when interrupt happened. + * The interrupt trigger status is shown in the following: + * - INT_TYPE_LINK_STATUS (value[0] (Bit0)) + * - INT_TYPE_METER_EXCEED (value[0] (Bit1)) + * - INT_TYPE_LEARN_LIMIT (value[0] (Bit2)) + * - INT_TYPE_LINK_SPEED (value[0] (Bit3)) + * - INT_TYPE_CONGEST (value[0] (Bit4)) + * - INT_TYPE_GREEN_FEATURE (value[0] (Bit5)) + * - INT_TYPE_LOOP_DETECT (value[0] (Bit6)) + * - INT_TYPE_8051 (value[0] (Bit7)) + * - INT_TYPE_CABLE_DIAG (value[0] (Bit8)) + * - INT_TYPE_ACL (value[0] (Bit9)) + * - INT_TYPE_SLIENT (value[0] (Bit11)) + * + */ +extern rtk_api_ret_t rtk_int_status_get(rtk_int_status_t* pStatusMask); + +/* Function Name: + * rtk_int_advanceInfo_get + * Description: + * Get interrupt advanced information. + * Input: + * adv_type - Advanced interrupt type. + * Output: + * info - Information per type. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can get advanced information when interrupt happened. + * The status will be cleared after execute this API. + */ +extern rtk_api_ret_t rtk_int_advanceInfo_get(rtk_int_advType_t adv_type, rtk_int_info_t* info); + + +#endif /* __RTK_API_INTERRUPT_H__ */ diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/l2.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/l2.c new file mode 100644 index 00000000..b54e70e1 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/l2.c @@ -0,0 +1,1679 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8367C + * Feature : Here is a list of all functions and variables in L2 module. + * + */ + +#include +#include +#include +#include + +#include + +/* Function Name: + * rtk_l2_init + * Description: + * Initialize l2 module of the specified device. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * Initialize l2 module before calling any l2 APIs. + */ +rtk_api_ret_t rtk_l2_init(void) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_init) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_init(); + RTK_API_UNLOCK(); + + return retVal; +} + + +/* Function Name: + * rtk_l2_addr_add + * Description: + * Add LUT unicast entry. + * Input: + * pMac - 6 bytes unicast(I/G bit is 0) mac address to be written into LUT. + * pL2_data - Unicast entry parameter + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_L2_FID - Invalid FID . + * RT_ERR_L2_INDEXTBL_FULL - hashed index is full of entries. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * If the unicast mac address already existed in LUT, it will udpate the status of the entry. + * Otherwise, it will find an empty or asic auto learned entry to write. If all the entries + * with the same hash value can't be replaced, ASIC will return a RT_ERR_L2_INDEXTBL_FULL error. + */ +rtk_api_ret_t rtk_l2_addr_add(rtk_mac_t *pMac, rtk_l2_ucastAddr_t *pL2_data) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_addr_add) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_addr_add(pMac, pL2_data); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_addr_get + * Description: + * Get LUT unicast entry. + * Input: + * pMac - 6 bytes unicast(I/G bit is 0) mac address to be written into LUT. + * Output: + * pL2_data - Unicast entry parameter + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_L2_FID - Invalid FID . + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * If the unicast mac address existed in LUT, it will return the port and fid where + * the mac is learned. Otherwise, it will return a RT_ERR_L2_ENTRY_NOTFOUND error. + */ +rtk_api_ret_t rtk_l2_addr_get(rtk_mac_t *pMac, rtk_l2_ucastAddr_t *pL2_data) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_addr_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_addr_get(pMac, pL2_data); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_addr_next_get + * Description: + * Get Next LUT unicast entry. + * Input: + * read_method - The reading method. + * port - The port number if the read_metohd is READMETHOD_NEXT_L2UCSPA + * pAddress - The Address ID + * Output: + * pL2_data - Unicast entry parameter + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_L2_FID - Invalid FID . + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * Get the next unicast entry after the current entry pointed by pAddress. + * The address of next entry is returned by pAddress. User can use (address + 1) + * as pAddress to call this API again for dumping all entries is LUT. + */ +rtk_api_ret_t rtk_l2_addr_next_get(rtk_l2_read_method_t read_method, rtk_port_t port, rtk_uint32 *pAddress, rtk_l2_ucastAddr_t *pL2_data) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_addr_next_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_addr_next_get(read_method, port, pAddress, pL2_data); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_addr_del + * Description: + * Delete LUT unicast entry. + * Input: + * pMac - 6 bytes unicast(I/G bit is 0) mac address to be written into LUT. + * fid - Filtering database + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_L2_FID - Invalid FID . + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * If the mac has existed in the LUT, it will be deleted. Otherwise, it will return RT_ERR_L2_ENTRY_NOTFOUND. + */ +rtk_api_ret_t rtk_l2_addr_del(rtk_mac_t *pMac, rtk_l2_ucastAddr_t *pL2_data) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_addr_del) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_addr_del(pMac, pL2_data); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_mcastAddr_add + * Description: + * Add LUT multicast entry. + * Input: + * pMcastAddr - L2 multicast entry structure + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_L2_FID - Invalid FID . + * RT_ERR_L2_VID - Invalid VID . + * RT_ERR_L2_INDEXTBL_FULL - hashed index is full of entries. + * RT_ERR_PORT_MASK - Invalid portmask. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * If the multicast mac address already existed in the LUT, it will udpate the + * port mask of the entry. Otherwise, it will find an empty or asic auto learned + * entry to write. If all the entries with the same hash value can't be replaced, + * ASIC will return a RT_ERR_L2_INDEXTBL_FULL error. + */ +rtk_api_ret_t rtk_l2_mcastAddr_add(rtk_l2_mcastAddr_t *pMcastAddr) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_mcastAddr_add) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_mcastAddr_add(pMcastAddr); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_mcastAddr_get + * Description: + * Get LUT multicast entry. + * Input: + * pMcastAddr - L2 multicast entry structure + * Output: + * pMcastAddr - L2 multicast entry structure + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_L2_FID - Invalid FID . + * RT_ERR_L2_VID - Invalid VID . + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * If the multicast mac address existed in the LUT, it will return the port where + * the mac is learned. Otherwise, it will return a RT_ERR_L2_ENTRY_NOTFOUND error. + */ +rtk_api_ret_t rtk_l2_mcastAddr_get(rtk_l2_mcastAddr_t *pMcastAddr) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_mcastAddr_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_mcastAddr_get(pMcastAddr); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_mcastAddr_next_get + * Description: + * Get Next L2 Multicast entry. + * Input: + * pAddress - The Address ID + * Output: + * pMcastAddr - L2 multicast entry structure + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * Get the next L2 multicast entry after the current entry pointed by pAddress. + * The address of next entry is returned by pAddress. User can use (address + 1) + * as pAddress to call this API again for dumping all multicast entries is LUT. + */ +rtk_api_ret_t rtk_l2_mcastAddr_next_get(rtk_uint32 *pAddress, rtk_l2_mcastAddr_t *pMcastAddr) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_mcastAddr_next_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_mcastAddr_next_get(pAddress, pMcastAddr); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_mcastAddr_del + * Description: + * Delete LUT multicast entry. + * Input: + * pMcastAddr - L2 multicast entry structure + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_L2_FID - Invalid FID . + * RT_ERR_L2_VID - Invalid VID . + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * If the mac has existed in the LUT, it will be deleted. Otherwise, it will return RT_ERR_L2_ENTRY_NOTFOUND. + */ +rtk_api_ret_t rtk_l2_mcastAddr_del(rtk_l2_mcastAddr_t *pMcastAddr) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_mcastAddr_del) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_mcastAddr_del(pMcastAddr); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_ipMcastAddr_add + * Description: + * Add Lut IP multicast entry + * Input: + * pIpMcastAddr - IP Multicast entry + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_L2_INDEXTBL_FULL - hashed index is full of entries. + * RT_ERR_PORT_MASK - Invalid portmask. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * System supports L2 entry with IP multicast DIP/SIP to forward IP multicasting frame as user + * desired. If this function is enabled, then system will be looked up L2 IP multicast entry to + * forward IP multicast frame directly without flooding. + */ +rtk_api_ret_t rtk_l2_ipMcastAddr_add(rtk_l2_ipMcastAddr_t *pIpMcastAddr) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_ipMcastAddr_add) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_ipMcastAddr_add(pIpMcastAddr); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_ipMcastAddr_get + * Description: + * Get LUT IP multicast entry. + * Input: + * pIpMcastAddr - IP Multicast entry + * Output: + * pIpMcastAddr - IP Multicast entry + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get Lut table of IP multicast entry. + */ +rtk_api_ret_t rtk_l2_ipMcastAddr_get(rtk_l2_ipMcastAddr_t *pIpMcastAddr) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_ipMcastAddr_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_ipMcastAddr_get(pIpMcastAddr); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_ipMcastAddr_next_get + * Description: + * Get Next IP Multicast entry. + * Input: + * pAddress - The Address ID + * Output: + * pIpMcastAddr - IP Multicast entry + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * Get the next IP multicast entry after the current entry pointed by pAddress. + * The address of next entry is returned by pAddress. User can use (address + 1) + * as pAddress to call this API again for dumping all IP multicast entries is LUT. + */ +rtk_api_ret_t rtk_l2_ipMcastAddr_next_get(rtk_uint32 *pAddress, rtk_l2_ipMcastAddr_t *pIpMcastAddr) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_ipMcastAddr_next_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_ipMcastAddr_next_get(pAddress, pIpMcastAddr); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_ipMcastAddr_del + * Description: + * Delete a ip multicast address entry from the specified device. + * Input: + * pIpMcastAddr - IP Multicast entry + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can delete a IP multicast address entry from the specified device. + */ +rtk_api_ret_t rtk_l2_ipMcastAddr_del(rtk_l2_ipMcastAddr_t *pIpMcastAddr) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_ipMcastAddr_del) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_ipMcastAddr_del(pIpMcastAddr); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_ipVidMcastAddr_add + * Description: + * Add Lut IP multicast+VID entry + * Input: + * pIpVidMcastAddr - IP & VID multicast Entry + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_L2_INDEXTBL_FULL - hashed index is full of entries. + * RT_ERR_PORT_MASK - Invalid portmask. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * + */ +rtk_api_ret_t rtk_l2_ipVidMcastAddr_add(rtk_l2_ipVidMcastAddr_t *pIpVidMcastAddr) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_ipVidMcastAddr_add) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_ipVidMcastAddr_add(pIpVidMcastAddr); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_ipVidMcastAddr_get + * Description: + * Get LUT IP multicast+VID entry. + * Input: + * pIpVidMcastAddr - IP & VID multicast Entry + * Output: + * pIpVidMcastAddr - IP & VID multicast Entry + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * + */ +rtk_api_ret_t rtk_l2_ipVidMcastAddr_get(rtk_l2_ipVidMcastAddr_t *pIpVidMcastAddr) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_ipVidMcastAddr_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_ipVidMcastAddr_get(pIpVidMcastAddr); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_ipVidMcastAddr_next_get + * Description: + * Get Next IP Multicast+VID entry. + * Input: + * pAddress - The Address ID + * Output: + * pIpVidMcastAddr - IP & VID multicast Entry + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * Get the next IP multicast entry after the current entry pointed by pAddress. + * The address of next entry is returned by pAddress. User can use (address + 1) + * as pAddress to call this API again for dumping all IP multicast entries is LUT. + */ +rtk_api_ret_t rtk_l2_ipVidMcastAddr_next_get(rtk_uint32 *pAddress, rtk_l2_ipVidMcastAddr_t *pIpVidMcastAddr) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_ipVidMcastAddr_next_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_ipVidMcastAddr_next_get(pAddress, pIpVidMcastAddr); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_ipVidMcastAddr_del + * Description: + * Delete a ip multicast+VID address entry from the specified device. + * Input: + * pIpVidMcastAddr - IP & VID multicast Entry + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * + */ +rtk_api_ret_t rtk_l2_ipVidMcastAddr_del(rtk_l2_ipVidMcastAddr_t *pIpVidMcastAddr) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_ipVidMcastAddr_del) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_ipVidMcastAddr_del(pIpVidMcastAddr); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_ucastAddr_flush + * Description: + * Flush L2 mac address by type in the specified device (both dynamic and static). + * Input: + * pConfig - flush configuration + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * flushByVid - 1: Flush by VID, 0: Don't flush by VID + * vid - VID (0 ~ 4095) + * flushByFid - 1: Flush by FID, 0: Don't flush by FID + * fid - FID (0 ~ 15) + * flushByPort - 1: Flush by Port, 0: Don't flush by Port + * port - Port ID + * flushByMac - Not Supported + * ucastAddr - Not Supported + * flushStaticAddr - 1: Flush both Static and Dynamic entries, 0: Flush only Dynamic entries + * flushAddrOnAllPorts - 1: Flush VID-matched entries at all ports, 0: Flush VID-matched entries per port. + */ +rtk_api_ret_t rtk_l2_ucastAddr_flush(rtk_l2_flushCfg_t *pConfig) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_ucastAddr_flush) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_ucastAddr_flush(pConfig); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_table_clear + * Description: + * Flush all static & dynamic entries in LUT. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * + */ +rtk_api_ret_t rtk_l2_table_clear(void) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_table_clear) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_table_clear(); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_table_clearStatus_get + * Description: + * Get table clear status + * Input: + * None + * Output: + * pStatus - Clear status, 1:Busy, 0:finish + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * + */ +rtk_api_ret_t rtk_l2_table_clearStatus_get(rtk_l2_clearStatus_t *pStatus) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_table_clearStatus_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_table_clearStatus_get(pStatus); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_flushLinkDownPortAddrEnable_set + * Description: + * Set HW flush linkdown port mac configuration of the specified device. + * Input: + * port - Port id. + * enable - link down flush status + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * The status of flush linkdown port address is as following: + * - DISABLED + * - ENABLED + */ +rtk_api_ret_t rtk_l2_flushLinkDownPortAddrEnable_set(rtk_port_t port, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_flushLinkDownPortAddrEnable_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_flushLinkDownPortAddrEnable_set(port, enable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_flushLinkDownPortAddrEnable_get + * Description: + * Get HW flush linkdown port mac configuration of the specified device. + * Input: + * port - Port id. + * Output: + * pEnable - link down flush status + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The status of flush linkdown port address is as following: + * - DISABLED + * - ENABLED + */ +rtk_api_ret_t rtk_l2_flushLinkDownPortAddrEnable_get(rtk_port_t port, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_flushLinkDownPortAddrEnable_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_flushLinkDownPortAddrEnable_get(port, pEnable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_agingEnable_set + * Description: + * Set L2 LUT aging status per port setting. + * Input: + * port - Port id. + * enable - Aging status + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * This API can be used to set L2 LUT aging status per port. + */ +rtk_api_ret_t rtk_l2_agingEnable_set(rtk_port_t port, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_agingEnable_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_agingEnable_set(port, enable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_agingEnable_get + * Description: + * Get L2 LUT aging status per port setting. + * Input: + * port - Port id. + * Output: + * pEnable - Aging status + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can be used to get L2 LUT aging function per port. + */ +rtk_api_ret_t rtk_l2_agingEnable_get(rtk_port_t port, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_agingEnable_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_agingEnable_get(port, pEnable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_limitLearningCnt_set + * Description: + * Set per-Port auto learning limit number + * Input: + * port - Port id. + * mac_cnt - Auto learning entries limit number + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_LIMITED_L2ENTRY_NUM - Invalid auto learning limit number + * Note: + * The API can set per-port ASIC auto learning limit number from 0(disable learning) + * to 2112. + */ +rtk_api_ret_t rtk_l2_limitLearningCnt_set(rtk_port_t port, rtk_mac_cnt_t mac_cnt) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_limitLearningCnt_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_limitLearningCnt_set(port, mac_cnt); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_limitLearningCnt_get + * Description: + * Get per-Port auto learning limit number + * Input: + * port - Port id. + * Output: + * pMac_cnt - Auto learning entries limit number + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get per-port ASIC auto learning limit number. + */ +rtk_api_ret_t rtk_l2_limitLearningCnt_get(rtk_port_t port, rtk_mac_cnt_t *pMac_cnt) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_limitLearningCnt_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_limitLearningCnt_get(port, pMac_cnt); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_limitSystemLearningCnt_set + * Description: + * Set System auto learning limit number + * Input: + * mac_cnt - Auto learning entries limit number + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_LIMITED_L2ENTRY_NUM - Invalid auto learning limit number + * Note: + * The API can set system ASIC auto learning limit number from 0(disable learning) + * to 2112. + */ +rtk_api_ret_t rtk_l2_limitSystemLearningCnt_set(rtk_mac_cnt_t mac_cnt) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_limitSystemLearningCnt_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_limitSystemLearningCnt_set(mac_cnt); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_limitSystemLearningCnt_get + * Description: + * Get System auto learning limit number + * Input: + * None + * Output: + * pMac_cnt - Auto learning entries limit number + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get system ASIC auto learning limit number. + */ +rtk_api_ret_t rtk_l2_limitSystemLearningCnt_get(rtk_mac_cnt_t *pMac_cnt) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_limitSystemLearningCnt_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_limitSystemLearningCnt_get(pMac_cnt); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_limitLearningCntAction_set + * Description: + * Configure auto learn over limit number action. + * Input: + * port - Port id. + * action - Auto learning entries limit number + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_NOT_ALLOWED - Invalid learn over action + * Note: + * The API can set SA unknown packet action while auto learn limit number is over + * The action symbol as following: + * - LIMIT_LEARN_CNT_ACTION_DROP, + * - LIMIT_LEARN_CNT_ACTION_FORWARD, + * - LIMIT_LEARN_CNT_ACTION_TO_CPU, + */ +rtk_api_ret_t rtk_l2_limitLearningCntAction_set(rtk_port_t port, rtk_l2_limitLearnCntAction_t action) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_limitLearningCntAction_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_limitLearningCntAction_set(port, action); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_limitLearningCntAction_get + * Description: + * Get auto learn over limit number action. + * Input: + * port - Port id. + * Output: + * pAction - Learn over action + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get SA unknown packet action while auto learn limit number is over + * The action symbol as following: + * - LIMIT_LEARN_CNT_ACTION_DROP, + * - LIMIT_LEARN_CNT_ACTION_FORWARD, + * - LIMIT_LEARN_CNT_ACTION_TO_CPU, + */ +rtk_api_ret_t rtk_l2_limitLearningCntAction_get(rtk_port_t port, rtk_l2_limitLearnCntAction_t *pAction) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_limitLearningCntAction_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_limitLearningCntAction_get(port, pAction); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_limitSystemLearningCntAction_set + * Description: + * Configure system auto learn over limit number action. + * Input: + * port - Port id. + * action - Auto learning entries limit number + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_NOT_ALLOWED - Invalid learn over action + * Note: + * The API can set SA unknown packet action while auto learn limit number is over + * The action symbol as following: + * - LIMIT_LEARN_CNT_ACTION_DROP, + * - LIMIT_LEARN_CNT_ACTION_FORWARD, + * - LIMIT_LEARN_CNT_ACTION_TO_CPU, + */ +rtk_api_ret_t rtk_l2_limitSystemLearningCntAction_set(rtk_l2_limitLearnCntAction_t action) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_limitSystemLearningCntAction_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_limitSystemLearningCntAction_set(action); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_limitSystemLearningCntAction_get + * Description: + * Get system auto learn over limit number action. + * Input: + * None. + * Output: + * pAction - Learn over action + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get SA unknown packet action while auto learn limit number is over + * The action symbol as following: + * - LIMIT_LEARN_CNT_ACTION_DROP, + * - LIMIT_LEARN_CNT_ACTION_FORWARD, + * - LIMIT_LEARN_CNT_ACTION_TO_CPU, + */ +rtk_api_ret_t rtk_l2_limitSystemLearningCntAction_get(rtk_l2_limitLearnCntAction_t *pAction) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_limitSystemLearningCntAction_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_limitSystemLearningCntAction_get(pAction); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_limitSystemLearningCntPortMask_set + * Description: + * Configure system auto learn portmask + * Input: + * pPortmask - Port Mask + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Invalid port mask. + * Note: + * + */ +rtk_api_ret_t rtk_l2_limitSystemLearningCntPortMask_set(rtk_portmask_t *pPortmask) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_limitSystemLearningCntPortMask_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_limitSystemLearningCntPortMask_set(pPortmask); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_limitSystemLearningCntPortMask_get + * Description: + * get system auto learn portmask + * Input: + * None + * Output: + * pPortmask - Port Mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Null pointer. + * Note: + * + */ +rtk_api_ret_t rtk_l2_limitSystemLearningCntPortMask_get(rtk_portmask_t *pPortmask) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_limitSystemLearningCntPortMask_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_limitSystemLearningCntPortMask_get(pPortmask); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_learningCnt_get + * Description: + * Get per-Port current auto learning number + * Input: + * port - Port id. + * Output: + * pMac_cnt - ASIC auto learning entries number + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get per-port ASIC auto learning number + */ +rtk_api_ret_t rtk_l2_learningCnt_get(rtk_port_t port, rtk_mac_cnt_t *pMac_cnt) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_learningCnt_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_learningCnt_get(port, pMac_cnt); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_floodPortMask_set + * Description: + * Set flooding portmask + * Input: + * type - flooding type. + * pFlood_portmask - flooding porkmask + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Invalid portmask. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can set the flooding mask. + * The flooding type is as following: + * - FLOOD_UNKNOWNDA + * - FLOOD_UNKNOWNMC + * - FLOOD_BC + */ +rtk_api_ret_t rtk_l2_floodPortMask_set(rtk_l2_flood_type_t floood_type, rtk_portmask_t *pFlood_portmask) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_floodPortMask_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_floodPortMask_set(floood_type, pFlood_portmask); + RTK_API_UNLOCK(); + + return retVal; +} +/* Function Name: + * rtk_l2_floodPortMask_get + * Description: + * Get flooding portmask + * Input: + * type - flooding type. + * Output: + * pFlood_portmask - flooding porkmask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can get the flooding mask. + * The flooding type is as following: + * - FLOOD_UNKNOWNDA + * - FLOOD_UNKNOWNMC + * - FLOOD_BC + */ +rtk_api_ret_t rtk_l2_floodPortMask_get(rtk_l2_flood_type_t floood_type, rtk_portmask_t *pFlood_portmask) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_floodPortMask_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_floodPortMask_get(floood_type, pFlood_portmask); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_localPktPermit_set + * Description: + * Set permittion of frames if source port and destination port are the same. + * Input: + * port - Port id. + * permit - permittion status + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid permit value. + * Note: + * This API is setted to permit frame if its source port is equal to destination port. + */ +rtk_api_ret_t rtk_l2_localPktPermit_set(rtk_port_t port, rtk_enable_t permit) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_localPktPermit_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_localPktPermit_set(port, permit); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_localPktPermit_get + * Description: + * Get permittion of frames if source port and destination port are the same. + * Input: + * port - Port id. + * Output: + * pPermit - permittion status + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API is to get permittion status for frames if its source port is equal to destination port. + */ +rtk_api_ret_t rtk_l2_localPktPermit_get(rtk_port_t port, rtk_enable_t *pPermit) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_localPktPermit_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_localPktPermit_get(port, pPermit); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_aging_set + * Description: + * Set LUT agging out speed + * Input: + * aging_time - Agging out time. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - input out of range. + * Note: + * The API can set LUT agging out period for each entry and the range is from 45s to 458s. + */ +rtk_api_ret_t rtk_l2_aging_set(rtk_l2_age_time_t aging_time) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_aging_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_aging_set(aging_time); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_aging_get + * Description: + * Get LUT agging out time + * Input: + * None + * Output: + * pEnable - Aging status + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get LUT agging out period for each entry. + */ +rtk_api_ret_t rtk_l2_aging_get(rtk_l2_age_time_t *pAging_time) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_aging_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_aging_get(pAging_time); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_ipMcastAddrLookup_set + * Description: + * Set Lut IP multicast lookup function + * Input: + * type - Lookup type for IPMC packet. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * LOOKUP_MAC - Lookup by MAC address + * LOOKUP_IP - Lookup by IP address + * LOOKUP_IP_VID - Lookup by IP address & VLAN ID + */ +rtk_api_ret_t rtk_l2_ipMcastAddrLookup_set(rtk_l2_ipmc_lookup_type_t type) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_ipMcastAddrLookup_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_ipMcastAddrLookup_set(type); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_ipMcastAddrLookup_get + * Description: + * Get Lut IP multicast lookup function + * Input: + * None. + * Output: + * pType - Lookup type for IPMC packet. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * None. + */ +rtk_api_ret_t rtk_l2_ipMcastAddrLookup_get(rtk_l2_ipmc_lookup_type_t *pType) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_ipMcastAddrLookup_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_ipMcastAddrLookup_get(pType); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_ipMcastForwardRouterPort_set + * Description: + * Set IPMC packet forward to rounter port also or not + * Input: + * enabled - 1: Inlcude router port, 0, exclude router port + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * + */ +rtk_api_ret_t rtk_l2_ipMcastForwardRouterPort_set(rtk_enable_t enabled) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_ipMcastForwardRouterPort_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_ipMcastForwardRouterPort_set(enabled); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_ipMcastForwardRouterPort_get + * Description: + * Get IPMC packet forward to rounter port also or not + * Input: + * None. + * Output: + * pEnabled - 1: Inlcude router port, 0, exclude router port + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * + */ +rtk_api_ret_t rtk_l2_ipMcastForwardRouterPort_get(rtk_enable_t *pEnabled) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_ipMcastForwardRouterPort_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_ipMcastForwardRouterPort_get(pEnabled); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_ipMcastGroupEntry_add + * Description: + * Add an IP Multicast entry to group table + * Input: + * ip_addr - IP address + * vid - VLAN ID + * pPortmask - portmask + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_TBL_FULL - Table Full + * Note: + * Add an entry to IP Multicast Group table. + */ +rtk_api_ret_t rtk_l2_ipMcastGroupEntry_add(ipaddr_t ip_addr, rtk_uint32 vid, rtk_portmask_t *pPortmask) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_ipMcastGroupEntry_add) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_ipMcastGroupEntry_add(ip_addr, vid, pPortmask); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_ipMcastGroupEntry_del + * Description: + * Delete an entry from IP Multicast group table + * Input: + * ip_addr - IP address + * vid - VLAN ID + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_TBL_FULL - Table Full + * Note: + * Delete an entry from IP Multicast group table. + */ +rtk_api_ret_t rtk_l2_ipMcastGroupEntry_del(ipaddr_t ip_addr, rtk_uint32 vid) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_ipMcastGroupEntry_del) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_ipMcastGroupEntry_del(ip_addr, vid); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_ipMcastGroupEntry_get + * Description: + * get an entry from IP Multicast group table + * Input: + * ip_addr - IP address + * vid - VLAN ID + * Output: + * pPortmask - member port mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_TBL_FULL - Table Full + * Note: + * Delete an entry from IP Multicast group table. + */ +rtk_api_ret_t rtk_l2_ipMcastGroupEntry_get(ipaddr_t ip_addr, rtk_uint32 vid, rtk_portmask_t *pPortmask) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_ipMcastGroupEntry_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_ipMcastGroupEntry_get(ip_addr, vid, pPortmask); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_entry_get + * Description: + * Get LUT unicast entry. + * Input: + * pL2_entry - Index field in the structure. + * Output: + * pL2_entry - other fields such as MAC, port, age... + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_EMPTY_ENTRY - Empty LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API is used to get address by index from 0~2111. + */ +rtk_api_ret_t rtk_l2_entry_get(rtk_l2_addr_table_t *pL2_entry) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_entry_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_entry_get(pL2_entry); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_lookupHitIsolationAction_set + * Description: + * Set action of lookup hit & isolation. + * Input: + * action - The action + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API is used to configure the action of packet which is lookup hit + * in L2 table but the destination port/portmask are not in the port isolation + * group. + */ +rtk_api_ret_t rtk_l2_lookupHitIsolationAction_set(rtk_l2_lookupHitIsolationAction_t action) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_lookupHitIsolationAction_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_lookupHitIsolationAction_set(action); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_lookupHitIsolationAction_get + * Description: + * Get action of lookup hit & isolation. + * Input: + * None. + * Output: + * pAction - The action + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API is used to get the action of packet which is lookup hit + * in L2 table but the destination port/portmask are not in the port isolation + * group. + */ +rtk_api_ret_t rtk_l2_lookupHitIsolationAction_get(rtk_l2_lookupHitIsolationAction_t *pAction) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_lookupHitIsolationAction_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_lookupHitIsolationAction_get(pAction); + RTK_API_UNLOCK(); + + return retVal; +} diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/l2.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/l2.h new file mode 100644 index 00000000..988a14bd --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/l2.h @@ -0,0 +1,1230 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8367/RTL8367C switch high-level API + * + * Feature : The file includes L2 module high-layer API defination + * + */ + +#ifndef __RTK_API_L2_H__ +#define __RTK_API_L2_H__ + + +/* + * Data Type Declaration + */ +#define RTK_MAX_NUM_OF_LEARN_LIMIT (rtk_switch_maxLutAddrNumber_get()) + +#define RTK_MAC_ADDR_LEN 6 +#define RTK_MAX_LUT_ADDRESS (RTK_MAX_NUM_OF_LEARN_LIMIT) +#define RTK_MAX_LUT_ADDR_ID (RTK_MAX_LUT_ADDRESS - 1) + +typedef rtk_uint32 rtk_l2_age_time_t; + +typedef enum rtk_l2_flood_type_e +{ + FLOOD_UNKNOWNDA = 0, + FLOOD_UNKNOWNMC, + FLOOD_BC, + FLOOD_END +} rtk_l2_flood_type_t; + +typedef rtk_uint32 rtk_l2_flushItem_t; + +typedef enum rtk_l2_flushType_e +{ + FLUSH_TYPE_BY_PORT = 0, /* physical port */ + FLUSH_TYPE_BY_PORT_VID, /* physical port + VID */ + FLUSH_TYPE_BY_PORT_FID, /* physical port + FID */ + FLUSH_TYPE_END +} rtk_l2_flushType_t; + +typedef struct rtk_l2_flushCfg_s +{ + rtk_enable_t flushByVid; + rtk_vlan_t vid; + rtk_enable_t flushByFid; + rtk_uint32 fid; + rtk_enable_t flushByPort; + rtk_port_t port; + rtk_enable_t flushByMac; + rtk_mac_t ucastAddr; + rtk_enable_t flushStaticAddr; + rtk_enable_t flushAddrOnAllPorts; /* this is used when flushByVid */ +} rtk_l2_flushCfg_t; + +typedef enum rtk_l2_read_method_e{ + + READMETHOD_MAC = 0, + READMETHOD_ADDRESS, + READMETHOD_NEXT_ADDRESS, + READMETHOD_NEXT_L2UC, + READMETHOD_NEXT_L2MC, + READMETHOD_NEXT_L3MC, + READMETHOD_NEXT_L2L3MC, + READMETHOD_NEXT_L2UCSPA, + READMETHOD_END +}rtk_l2_read_method_t; + +/* l2 limit learning count action */ +typedef enum rtk_l2_limitLearnCntAction_e +{ + LIMIT_LEARN_CNT_ACTION_DROP = 0, + LIMIT_LEARN_CNT_ACTION_FORWARD, + LIMIT_LEARN_CNT_ACTION_TO_CPU, + LIMIT_LEARN_CNT_ACTION_END +} rtk_l2_limitLearnCntAction_t; + +typedef enum rtk_l2_ipmc_lookup_type_e +{ + LOOKUP_MAC = 0, + LOOKUP_IP, + LOOKUP_IP_VID, + LOOKUP_END +} rtk_l2_ipmc_lookup_type_t; + +/* l2 address table - unicast data structure */ +typedef struct rtk_l2_ucastAddr_s +{ + rtk_mac_t mac; + rtk_uint32 ivl; + rtk_uint32 cvid; + rtk_uint32 fid; + rtk_uint32 efid; + rtk_uint32 port; + rtk_uint32 sa_block; + rtk_uint32 da_block; + rtk_uint32 auth; + rtk_uint32 is_static; + rtk_uint32 priority; + rtk_uint32 sa_pri_en; + rtk_uint32 fwd_pri_en; + rtk_uint32 address; +}rtk_l2_ucastAddr_t; + +/* l2 address table - multicast data structure */ +typedef struct rtk_l2_mcastAddr_s +{ + rtk_uint32 vid; + rtk_mac_t mac; + rtk_uint32 fid; + rtk_portmask_t portmask; + rtk_uint32 ivl; + rtk_uint32 priority; + rtk_uint32 fwd_pri_en; + rtk_uint32 igmp_asic; + rtk_uint32 igmp_index; + rtk_uint32 address; +}rtk_l2_mcastAddr_t; + +/* l2 address table - ip multicast data structure */ +typedef struct rtk_l2_ipMcastAddr_s +{ + ipaddr_t dip; + ipaddr_t sip; + rtk_portmask_t portmask; + rtk_uint32 priority; + rtk_uint32 fwd_pri_en; + rtk_uint32 igmp_asic; + rtk_uint32 igmp_index; + rtk_uint32 address; +}rtk_l2_ipMcastAddr_t; + +/* l2 address table - ip VID multicast data structure */ +typedef struct rtk_l2_ipVidMcastAddr_s +{ + ipaddr_t dip; + ipaddr_t sip; + rtk_uint32 vid; + rtk_portmask_t portmask; + rtk_uint32 address; +}rtk_l2_ipVidMcastAddr_t; + +typedef struct rtk_l2_addr_table_s +{ + rtk_uint32 index; + ipaddr_t sip; + ipaddr_t dip; + rtk_mac_t mac; + rtk_uint32 sa_block; + rtk_uint32 auth; + rtk_portmask_t portmask; + rtk_uint32 age; + rtk_uint32 ivl; + rtk_uint32 cvid; + rtk_uint32 fid; + rtk_uint32 is_ipmul; + rtk_uint32 is_static; + rtk_uint32 is_ipvidmul; + rtk_uint32 l3_vid; +}rtk_l2_addr_table_t; + +typedef enum rtk_l2_clearStatus_e +{ + L2_CLEAR_STATE_FINISH = 0, + L2_CLEAR_STATE_BUSY, + L2_CLEAR_STATE_END +}rtk_l2_clearStatus_t; + +typedef enum rtk_l2_lookupHitIsolationAction_e +{ + L2_LOOKUPHIT_ISOACTION_NOP = 0, + L2_LOOKUPHIT_ISOACTION_UNKNOWN, + L2_LOOKUPHIT_ISOACTION_END +}rtk_l2_lookupHitIsolationAction_t; + +/* Function Name: + * rtk_l2_init + * Description: + * Initialize l2 module of the specified device. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * Initialize l2 module before calling any l2 APIs. + */ +extern rtk_api_ret_t rtk_l2_init(void); + +/* Function Name: + * rtk_l2_addr_add + * Description: + * Add LUT unicast entry. + * Input: + * pMac - 6 bytes unicast(I/G bit is 0) mac address to be written into LUT. + * pL2_data - Unicast entry parameter + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_L2_FID - Invalid FID . + * RT_ERR_L2_INDEXTBL_FULL - hashed index is full of entries. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * If the unicast mac address already existed in LUT, it will udpate the status of the entry. + * Otherwise, it will find an empty or asic auto learned entry to write. If all the entries + * with the same hash value can't be replaced, ASIC will return a RT_ERR_L2_INDEXTBL_FULL error. + */ +extern rtk_api_ret_t rtk_l2_addr_add(rtk_mac_t *pMac, rtk_l2_ucastAddr_t *pL2_data); + +/* Function Name: + * rtk_l2_addr_get + * Description: + * Get LUT unicast entry. + * Input: + * pMac - 6 bytes unicast(I/G bit is 0) mac address to be written into LUT. + * Output: + * pL2_data - Unicast entry parameter + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_L2_FID - Invalid FID . + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * If the unicast mac address existed in LUT, it will return the port and fid where + * the mac is learned. Otherwise, it will return a RT_ERR_L2_ENTRY_NOTFOUND error. + */ +extern rtk_api_ret_t rtk_l2_addr_get(rtk_mac_t *pMac, rtk_l2_ucastAddr_t *pL2_data); + +/* Function Name: + * rtk_l2_addr_next_get + * Description: + * Get Next LUT unicast entry. + * Input: + * read_method - The reading method. + * port - The port number if the read_metohd is READMETHOD_NEXT_L2UCSPA + * pAddress - The Address ID + * Output: + * pL2_data - Unicast entry parameter + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_L2_FID - Invalid FID . + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * Get the next unicast entry after the current entry pointed by pAddress. + * The address of next entry is returned by pAddress. User can use (address + 1) + * as pAddress to call this API again for dumping all entries is LUT. + */ +extern rtk_api_ret_t rtk_l2_addr_next_get(rtk_l2_read_method_t read_method, rtk_port_t port, rtk_uint32 *pAddress, rtk_l2_ucastAddr_t *pL2_data); + +/* Function Name: + * rtk_l2_addr_del + * Description: + * Delete LUT unicast entry. + * Input: + * pMac - 6 bytes unicast(I/G bit is 0) mac address to be written into LUT. + * fid - Filtering database + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_L2_FID - Invalid FID . + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * If the mac has existed in the LUT, it will be deleted. Otherwise, it will return RT_ERR_L2_ENTRY_NOTFOUND. + */ +extern rtk_api_ret_t rtk_l2_addr_del(rtk_mac_t *pMac, rtk_l2_ucastAddr_t *pL2_data); + +/* Function Name: + * rtk_l2_mcastAddr_add + * Description: + * Add LUT multicast entry. + * Input: + * pMcastAddr - L2 multicast entry structure + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_L2_FID - Invalid FID . + * RT_ERR_L2_VID - Invalid VID . + * RT_ERR_L2_INDEXTBL_FULL - hashed index is full of entries. + * RT_ERR_PORT_MASK - Invalid portmask. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * If the multicast mac address already existed in the LUT, it will udpate the + * port mask of the entry. Otherwise, it will find an empty or asic auto learned + * entry to write. If all the entries with the same hash value can't be replaced, + * ASIC will return a RT_ERR_L2_INDEXTBL_FULL error. + */ +extern rtk_api_ret_t rtk_l2_mcastAddr_add(rtk_l2_mcastAddr_t *pMcastAddr); + +/* Function Name: + * rtk_l2_mcastAddr_get + * Description: + * Get LUT multicast entry. + * Input: + * pMcastAddr - L2 multicast entry structure + * Output: + * pMcastAddr - L2 multicast entry structure + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_L2_FID - Invalid FID . + * RT_ERR_L2_VID - Invalid VID . + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * If the multicast mac address existed in the LUT, it will return the port where + * the mac is learned. Otherwise, it will return a RT_ERR_L2_ENTRY_NOTFOUND error. + */ +extern rtk_api_ret_t rtk_l2_mcastAddr_get(rtk_l2_mcastAddr_t *pMcastAddr); + +/* Function Name: + * rtk_l2_mcastAddr_next_get + * Description: + * Get Next L2 Multicast entry. + * Input: + * pAddress - The Address ID + * Output: + * pMcastAddr - L2 multicast entry structure + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * Get the next L2 multicast entry after the current entry pointed by pAddress. + * The address of next entry is returned by pAddress. User can use (address + 1) + * as pAddress to call this API again for dumping all multicast entries is LUT. + */ +extern rtk_api_ret_t rtk_l2_mcastAddr_next_get(rtk_uint32 *pAddress, rtk_l2_mcastAddr_t *pMcastAddr); + +/* Function Name: + * rtk_l2_mcastAddr_del + * Description: + * Delete LUT multicast entry. + * Input: + * pMcastAddr - L2 multicast entry structure + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_L2_FID - Invalid FID . + * RT_ERR_L2_VID - Invalid VID . + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * If the mac has existed in the LUT, it will be deleted. Otherwise, it will return RT_ERR_L2_ENTRY_NOTFOUND. + */ +extern rtk_api_ret_t rtk_l2_mcastAddr_del(rtk_l2_mcastAddr_t *pMcastAddr); + +/* Function Name: + * rtk_l2_ipMcastAddr_add + * Description: + * Add Lut IP multicast entry + * Input: + * pIpMcastAddr - IP Multicast entry + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_L2_INDEXTBL_FULL - hashed index is full of entries. + * RT_ERR_PORT_MASK - Invalid portmask. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * System supports L2 entry with IP multicast DIP/SIP to forward IP multicasting frame as user + * desired. If this function is enabled, then system will be looked up L2 IP multicast entry to + * forward IP multicast frame directly without flooding. + */ +extern rtk_api_ret_t rtk_l2_ipMcastAddr_add(rtk_l2_ipMcastAddr_t *pIpMcastAddr); + +/* Function Name: + * rtk_l2_ipMcastAddr_get + * Description: + * Get LUT IP multicast entry. + * Input: + * pIpMcastAddr - IP Multicast entry + * Output: + * pIpMcastAddr - IP Multicast entry + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get Lut table of IP multicast entry. + */ +extern rtk_api_ret_t rtk_l2_ipMcastAddr_get(rtk_l2_ipMcastAddr_t *pIpMcastAddr); + +/* Function Name: + * rtk_l2_ipMcastAddr_next_get + * Description: + * Get Next IP Multicast entry. + * Input: + * pAddress - The Address ID + * Output: + * pIpMcastAddr - IP Multicast entry + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * Get the next IP multicast entry after the current entry pointed by pAddress. + * The address of next entry is returned by pAddress. User can use (address + 1) + * as pAddress to call this API again for dumping all IP multicast entries is LUT. + */ +extern rtk_api_ret_t rtk_l2_ipMcastAddr_next_get(rtk_uint32 *pAddress, rtk_l2_ipMcastAddr_t *pIpMcastAddr); + +/* Function Name: + * rtk_l2_ipMcastAddr_del + * Description: + * Delete a ip multicast address entry from the specified device. + * Input: + * pIpMcastAddr - IP Multicast entry + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can delete a IP multicast address entry from the specified device. + */ +extern rtk_api_ret_t rtk_l2_ipMcastAddr_del(rtk_l2_ipMcastAddr_t *pIpMcastAddr); + +/* Function Name: + * rtk_l2_ipVidMcastAddr_add + * Description: + * Add Lut IP multicast+VID entry + * Input: + * pIpVidMcastAddr - IP & VID multicast Entry + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_L2_INDEXTBL_FULL - hashed index is full of entries. + * RT_ERR_PORT_MASK - Invalid portmask. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * + */ +extern rtk_api_ret_t rtk_l2_ipVidMcastAddr_add(rtk_l2_ipVidMcastAddr_t *pIpVidMcastAddr); + +/* Function Name: + * rtk_l2_ipVidMcastAddr_get + * Description: + * Get LUT IP multicast+VID entry. + * Input: + * pIpVidMcastAddr - IP & VID multicast Entry + * Output: + * pIpVidMcastAddr - IP & VID multicast Entry + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * + */ +extern rtk_api_ret_t rtk_l2_ipVidMcastAddr_get(rtk_l2_ipVidMcastAddr_t *pIpVidMcastAddr); + +/* Function Name: + * rtk_l2_ipVidMcastAddr_next_get + * Description: + * Get Next IP Multicast+VID entry. + * Input: + * pAddress - The Address ID + * Output: + * pIpVidMcastAddr - IP & VID multicast Entry + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * Get the next IP multicast entry after the current entry pointed by pAddress. + * The address of next entry is returned by pAddress. User can use (address + 1) + * as pAddress to call this API again for dumping all IP multicast entries is LUT. + */ +extern rtk_api_ret_t rtk_l2_ipVidMcastAddr_next_get(rtk_uint32 *pAddress, rtk_l2_ipVidMcastAddr_t *pIpVidMcastAddr); + +/* Function Name: + * rtk_l2_ipVidMcastAddr_del + * Description: + * Delete a ip multicast+VID address entry from the specified device. + * Input: + * pIpVidMcastAddr - IP & VID multicast Entry + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * + */ +extern rtk_api_ret_t rtk_l2_ipVidMcastAddr_del(rtk_l2_ipVidMcastAddr_t *pIpVidMcastAddr); + +/* Function Name: + * rtk_l2_ucastAddr_flush + * Description: + * Flush L2 mac address by type in the specified device (both dynamic and static). + * Input: + * pConfig - flush configuration + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * flushByVid - 1: Flush by VID, 0: Don't flush by VID + * vid - VID (0 ~ 4095) + * flushByFid - 1: Flush by FID, 0: Don't flush by FID + * fid - FID (0 ~ 15) + * flushByPort - 1: Flush by Port, 0: Don't flush by Port + * port - Port ID + * flushByMac - Not Supported + * ucastAddr - Not Supported + * flushStaticAddr - 1: Flush both Static and Dynamic entries, 0: Flush only Dynamic entries + * flushAddrOnAllPorts - 1: Flush VID-matched entries at all ports, 0: Flush VID-matched entries per port. + */ +extern rtk_api_ret_t rtk_l2_ucastAddr_flush(rtk_l2_flushCfg_t *pConfig); + +/* Function Name: + * rtk_l2_table_clear + * Description: + * Flush all static & dynamic entries in LUT. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * + */ +extern rtk_api_ret_t rtk_l2_table_clear(void); + +/* Function Name: + * rtk_l2_table_clearStatus_get + * Description: + * Get table clear status + * Input: + * None + * Output: + * pStatus - Clear status, 1:Busy, 0:finish + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * + */ +extern rtk_api_ret_t rtk_l2_table_clearStatus_get(rtk_l2_clearStatus_t *pStatus); + +/* Function Name: + * rtk_l2_flushLinkDownPortAddrEnable_set + * Description: + * Set HW flush linkdown port mac configuration of the specified device. + * Input: + * port - Port id. + * enable - link down flush status + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * The status of flush linkdown port address is as following: + * - DISABLED + * - ENABLED + */ +extern rtk_api_ret_t rtk_l2_flushLinkDownPortAddrEnable_set(rtk_port_t port, rtk_enable_t enable); + +/* Function Name: + * rtk_l2_flushLinkDownPortAddrEnable_get + * Description: + * Get HW flush linkdown port mac configuration of the specified device. + * Input: + * port - Port id. + * Output: + * pEnable - link down flush status + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The status of flush linkdown port address is as following: + * - DISABLED + * - ENABLED + */ +extern rtk_api_ret_t rtk_l2_flushLinkDownPortAddrEnable_get(rtk_port_t port, rtk_enable_t *pEnable); + +/* Function Name: + * rtk_l2_agingEnable_set + * Description: + * Set L2 LUT aging status per port setting. + * Input: + * port - Port id. + * enable - Aging status + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * This API can be used to set L2 LUT aging status per port. + */ +extern rtk_api_ret_t rtk_l2_agingEnable_set(rtk_port_t port, rtk_enable_t enable); + +/* Function Name: + * rtk_l2_agingEnable_get + * Description: + * Get L2 LUT aging status per port setting. + * Input: + * port - Port id. + * Output: + * pEnable - Aging status + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can be used to get L2 LUT aging function per port. + */ +extern rtk_api_ret_t rtk_l2_agingEnable_get(rtk_port_t port, rtk_enable_t *pEnable); + +/* Function Name: + * rtk_l2_limitLearningCnt_set + * Description: + * Set per-Port auto learning limit number + * Input: + * port - Port id. + * mac_cnt - Auto learning entries limit number + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_LIMITED_L2ENTRY_NUM - Invalid auto learning limit number + * Note: + * The API can set per-port ASIC auto learning limit number from 0(disable learning) + * to 8k. + */ +extern rtk_api_ret_t rtk_l2_limitLearningCnt_set(rtk_port_t port, rtk_mac_cnt_t mac_cnt); + +/* Function Name: + * rtk_l2_limitLearningCnt_get + * Description: + * Get per-Port auto learning limit number + * Input: + * port - Port id. + * Output: + * pMac_cnt - Auto learning entries limit number + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get per-port ASIC auto learning limit number. + */ +extern rtk_api_ret_t rtk_l2_limitLearningCnt_get(rtk_port_t port, rtk_mac_cnt_t *pMac_cnt); + +/* Function Name: + * rtk_l2_limitSystemLearningCnt_set + * Description: + * Set System auto learning limit number + * Input: + * mac_cnt - Auto learning entries limit number + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_LIMITED_L2ENTRY_NUM - Invalid auto learning limit number + * Note: + * The API can set system ASIC auto learning limit number from 0(disable learning) + * to 2112. + */ +extern rtk_api_ret_t rtk_l2_limitSystemLearningCnt_set(rtk_mac_cnt_t mac_cnt); + +/* Function Name: + * rtk_l2_limitSystemLearningCnt_get + * Description: + * Get System auto learning limit number + * Input: + * None + * Output: + * pMac_cnt - Auto learning entries limit number + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get system ASIC auto learning limit number. + */ +extern rtk_api_ret_t rtk_l2_limitSystemLearningCnt_get(rtk_mac_cnt_t *pMac_cnt); + +/* Function Name: + * rtk_l2_limitLearningCntAction_set + * Description: + * Configure auto learn over limit number action. + * Input: + * port - Port id. + * action - Auto learning entries limit number + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_NOT_ALLOWED - Invalid learn over action + * Note: + * The API can set SA unknown packet action while auto learn limit number is over + * The action symbol as following: + * - LIMIT_LEARN_CNT_ACTION_DROP, + * - LIMIT_LEARN_CNT_ACTION_FORWARD, + * - LIMIT_LEARN_CNT_ACTION_TO_CPU, + */ +extern rtk_api_ret_t rtk_l2_limitLearningCntAction_set(rtk_port_t port, rtk_l2_limitLearnCntAction_t action); + +/* Function Name: + * rtk_l2_limitLearningCntAction_get + * Description: + * Get auto learn over limit number action. + * Input: + * port - Port id. + * Output: + * pAction - Learn over action + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get SA unknown packet action while auto learn limit number is over + * The action symbol as following: + * - LIMIT_LEARN_CNT_ACTION_DROP, + * - LIMIT_LEARN_CNT_ACTION_FORWARD, + * - LIMIT_LEARN_CNT_ACTION_TO_CPU, + */ +extern rtk_api_ret_t rtk_l2_limitLearningCntAction_get(rtk_port_t port, rtk_l2_limitLearnCntAction_t *pAction); + +/* Function Name: + * rtk_l2_limitSystemLearningCntAction_set + * Description: + * Configure system auto learn over limit number action. + * Input: + * port - Port id. + * action - Auto learning entries limit number + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_NOT_ALLOWED - Invalid learn over action + * Note: + * The API can set SA unknown packet action while auto learn limit number is over + * The action symbol as following: + * - LIMIT_LEARN_CNT_ACTION_DROP, + * - LIMIT_LEARN_CNT_ACTION_FORWARD, + * - LIMIT_LEARN_CNT_ACTION_TO_CPU, + */ +extern rtk_api_ret_t rtk_l2_limitSystemLearningCntAction_set(rtk_l2_limitLearnCntAction_t action); + +/* Function Name: + * rtk_l2_limitSystemLearningCntAction_get + * Description: + * Get system auto learn over limit number action. + * Input: + * None. + * Output: + * pAction - Learn over action + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get SA unknown packet action while auto learn limit number is over + * The action symbol as following: + * - LIMIT_LEARN_CNT_ACTION_DROP, + * - LIMIT_LEARN_CNT_ACTION_FORWARD, + * - LIMIT_LEARN_CNT_ACTION_TO_CPU, + */ +extern rtk_api_ret_t rtk_l2_limitSystemLearningCntAction_get(rtk_l2_limitLearnCntAction_t *pAction); + +/* Function Name: + * rtk_l2_limitSystemLearningCntPortMask_set + * Description: + * Configure system auto learn portmask + * Input: + * pPortmask - Port Mask + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Invalid port mask. + * Note: + * + */ +extern rtk_api_ret_t rtk_l2_limitSystemLearningCntPortMask_set(rtk_portmask_t *pPortmask); + +/* Function Name: + * rtk_l2_limitSystemLearningCntPortMask_get + * Description: + * get system auto learn portmask + * Input: + * None + * Output: + * pPortmask - Port Mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Null pointer. + * Note: + * + */ +extern rtk_api_ret_t rtk_l2_limitSystemLearningCntPortMask_get(rtk_portmask_t *pPortmask); + +/* Function Name: + * rtk_l2_learningCnt_get + * Description: + * Get per-Port current auto learning number + * Input: + * port - Port id. + * Output: + * pMac_cnt - ASIC auto learning entries number + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get per-port ASIC auto learning number + */ +extern rtk_api_ret_t rtk_l2_learningCnt_get(rtk_port_t port, rtk_mac_cnt_t *pMac_cnt); + +/* Function Name: + * rtk_l2_floodPortMask_set + * Description: + * Set flooding portmask + * Input: + * type - flooding type. + * pFlood_portmask - flooding porkmask + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Invalid portmask. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can set the flooding mask. + * The flooding type is as following: + * - FLOOD_UNKNOWNDA + * - FLOOD_UNKNOWNMC + * - FLOOD_BC + */ +extern rtk_api_ret_t rtk_l2_floodPortMask_set(rtk_l2_flood_type_t floood_type, rtk_portmask_t *pFlood_portmask); + +/* Function Name: + * rtk_l2_floodPortMask_get + * Description: + * Get flooding portmask + * Input: + * type - flooding type. + * Output: + * pFlood_portmask - flooding porkmask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can get the flooding mask. + * The flooding type is as following: + * - FLOOD_UNKNOWNDA + * - FLOOD_UNKNOWNMC + * - FLOOD_BC + */ +extern rtk_api_ret_t rtk_l2_floodPortMask_get(rtk_l2_flood_type_t floood_type, rtk_portmask_t *pFlood_portmask); + +/* Function Name: + * rtk_l2_localPktPermit_set + * Description: + * Set permittion of frames if source port and destination port are the same. + * Input: + * port - Port id. + * permit - permittion status + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid permit value. + * Note: + * This API is setted to permit frame if its source port is equal to destination port. + */ +extern rtk_api_ret_t rtk_l2_localPktPermit_set(rtk_port_t port, rtk_enable_t permit); + +/* Function Name: + * rtk_l2_localPktPermit_get + * Description: + * Get permittion of frames if source port and destination port are the same. + * Input: + * port - Port id. + * Output: + * pPermit - permittion status + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API is to get permittion status for frames if its source port is equal to destination port. + */ +extern rtk_api_ret_t rtk_l2_localPktPermit_get(rtk_port_t port, rtk_enable_t *pPermit); + +/* Function Name: + * rtk_l2_aging_set + * Description: + * Set LUT agging out speed + * Input: + * aging_time - Agging out time. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - input out of range. + * Note: + * The API can set LUT agging out period for each entry and the range is from 14s to 800s. + */ +extern rtk_api_ret_t rtk_l2_aging_set(rtk_l2_age_time_t aging_time); + +/* Function Name: + * rtk_l2_aging_get + * Description: + * Get LUT agging out time + * Input: + * None + * Output: + * pEnable - Aging status + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get LUT agging out period for each entry. + */ +extern rtk_api_ret_t rtk_l2_aging_get(rtk_l2_age_time_t *pAging_time); + +/* Function Name: + * rtk_l2_ipMcastAddrLookup_set + * Description: + * Set Lut IP multicast lookup function + * Input: + * type - Lookup type for IPMC packet. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API can work with rtk_l2_ipMcastAddrLookupException_add. + * If users set the lookup type to DIP, the group in exception table + * will be lookup by DIP+SIP + * If users set the lookup type to DIP+SIP, the group in exception table + * will be lookup by only DIP + */ +extern rtk_api_ret_t rtk_l2_ipMcastAddrLookup_set(rtk_l2_ipmc_lookup_type_t type); + +/* Function Name: + * rtk_l2_ipMcastAddrLookup_get + * Description: + * Get Lut IP multicast lookup function + * Input: + * None. + * Output: + * pType - Lookup type for IPMC packet. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * None. + */ +extern rtk_api_ret_t rtk_l2_ipMcastAddrLookup_get(rtk_l2_ipmc_lookup_type_t *pType); + +/* Function Name: + * rtk_l2_ipMcastForwardRouterPort_set + * Description: + * Set IPMC packet forward to rounter port also or not + * Input: + * enabled - 1: Inlcude router port, 0, exclude router port + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * + */ +extern rtk_api_ret_t rtk_l2_ipMcastForwardRouterPort_set(rtk_enable_t enabled); + +/* Function Name: + * rtk_l2_ipMcastForwardRouterPort_get + * Description: + * Get IPMC packet forward to rounter port also or not + * Input: + * None. + * Output: + * pEnabled - 1: Inlcude router port, 0, exclude router port + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * + */ +extern rtk_api_ret_t rtk_l2_ipMcastForwardRouterPort_get(rtk_enable_t *pEnabled); + +/* Function Name: + * rtk_l2_ipMcastGroupEntry_add + * Description: + * Add an IP Multicast entry to group table + * Input: + * ip_addr - IP address + * vid - VLAN ID + * pPortmask - portmask + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_TBL_FULL - Table Full + * Note: + * Add an entry to IP Multicast Group table. + */ +extern rtk_api_ret_t rtk_l2_ipMcastGroupEntry_add(ipaddr_t ip_addr, rtk_uint32 vid, rtk_portmask_t *pPortmask); + +/* Function Name: + * rtk_l2_ipMcastGroupEntry_del + * Description: + * Delete an entry from IP Multicast group table + * Input: + * ip_addr - IP address + * vid - VLAN ID + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_TBL_FULL - Table Full + * Note: + * Delete an entry from IP Multicast group table. + */ +extern rtk_api_ret_t rtk_l2_ipMcastGroupEntry_del(ipaddr_t ip_addr, rtk_uint32 vid); + +/* Function Name: + * rtk_l2_ipMcastGroupEntry_get + * Description: + * get an entry from IP Multicast group table + * Input: + * ip_addr - IP address + * vid - VLAN ID + * Output: + * pPortmask - member port mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_TBL_FULL - Table Full + * Note: + * Delete an entry from IP Multicast group table. + */ +extern rtk_api_ret_t rtk_l2_ipMcastGroupEntry_get(ipaddr_t ip_addr, rtk_uint32 vid, rtk_portmask_t *pPortmask); + +/* Function Name: + * rtk_l2_entry_get + * Description: + * Get LUT unicast entry. + * Input: + * pL2_entry - Index field in the structure. + * Output: + * pL2_entry - other fields such as MAC, port, age... + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_EMPTY_ENTRY - Empty LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API is used to get address by index from 0~2111. + */ +extern rtk_api_ret_t rtk_l2_entry_get(rtk_l2_addr_table_t *pL2_entry); + +/* Function Name: + * rtk_l2_lookupHitIsolationAction_set + * Description: + * Set action of lookup hit & isolation. + * Input: + * action - The action + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API is used to configure the action of packet which is lookup hit + * in L2 table but the destination port/portmask are not in the port isolation + * group. + */ +extern rtk_api_ret_t rtk_l2_lookupHitIsolationAction_set(rtk_l2_lookupHitIsolationAction_t action); + +/* Function Name: + * rtk_l2_lookupHitIsolationAction_get + * Description: + * Get action of lookup hit & isolation. + * Input: + * None. + * Output: + * pAction - The action + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API is used to get the action of packet which is lookup hit + * in L2 table but the destination port/portmask are not in the port isolation + * group. + */ +extern rtk_api_ret_t rtk_l2_lookupHitIsolationAction_get(rtk_l2_lookupHitIsolationAction_t *pAction); + +#endif /* __RTK_API_L2_H__ */ + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/leaky.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/leaky.c new file mode 100644 index 00000000..f69804e3 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/leaky.c @@ -0,0 +1,365 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8367C + * Feature : Here is a list of all functions and variables in Leaky module. + * + */ + +#include +#include +#include +#include + +#include + +/* Function Name: + * rtk_leaky_vlan_set + * Description: + * Set VLAN leaky. + * Input: + * type - Packet type for VLAN leaky. + * enable - Leaky status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_ENABLE - Invalid enable input + * Note: + * This API can set VLAN leaky for RMA ,IGMP/MLD, CDP, CSSTP, and LLDP packets. + * The leaky frame types are as following: + * - LEAKY_BRG_GROUP, + * - LEAKY_FD_PAUSE, + * - LEAKY_SP_MCAST, + * - LEAKY_1X_PAE, + * - LEAKY_UNDEF_BRG_04, + * - LEAKY_UNDEF_BRG_05, + * - LEAKY_UNDEF_BRG_06, + * - LEAKY_UNDEF_BRG_07, + * - LEAKY_PROVIDER_BRIDGE_GROUP_ADDRESS, + * - LEAKY_UNDEF_BRG_09, + * - LEAKY_UNDEF_BRG_0A, + * - LEAKY_UNDEF_BRG_0B, + * - LEAKY_UNDEF_BRG_0C, + * - LEAKY_PROVIDER_BRIDGE_GVRP_ADDRESS, + * - LEAKY_8021AB, + * - LEAKY_UNDEF_BRG_0F, + * - LEAKY_BRG_MNGEMENT, + * - LEAKY_UNDEFINED_11, + * - LEAKY_UNDEFINED_12, + * - LEAKY_UNDEFINED_13, + * - LEAKY_UNDEFINED_14, + * - LEAKY_UNDEFINED_15, + * - LEAKY_UNDEFINED_16, + * - LEAKY_UNDEFINED_17, + * - LEAKY_UNDEFINED_18, + * - LEAKY_UNDEFINED_19, + * - LEAKY_UNDEFINED_1A, + * - LEAKY_UNDEFINED_1B, + * - LEAKY_UNDEFINED_1C, + * - LEAKY_UNDEFINED_1D, + * - LEAKY_UNDEFINED_1E, + * - LEAKY_UNDEFINED_1F, + * - LEAKY_GMRP, + * - LEAKY_GVRP, + * - LEAKY_UNDEF_GARP_22, + * - LEAKY_UNDEF_GARP_23, + * - LEAKY_UNDEF_GARP_24, + * - LEAKY_UNDEF_GARP_25, + * - LEAKY_UNDEF_GARP_26, + * - LEAKY_UNDEF_GARP_27, + * - LEAKY_UNDEF_GARP_28, + * - LEAKY_UNDEF_GARP_29, + * - LEAKY_UNDEF_GARP_2A, + * - LEAKY_UNDEF_GARP_2B, + * - LEAKY_UNDEF_GARP_2C, + * - LEAKY_UNDEF_GARP_2D, + * - LEAKY_UNDEF_GARP_2E, + * - LEAKY_UNDEF_GARP_2F, + * - LEAKY_IGMP, + * - LEAKY_IPMULTICAST. + * - LEAKY_CDP, + * - LEAKY_CSSTP, + * - LEAKY_LLDP. + */ +rtk_api_ret_t rtk_leaky_vlan_set(rtk_leaky_type_t type, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->leaky_vlan_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->leaky_vlan_set(type, enable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_leaky_vlan_get + * Description: + * Get VLAN leaky. + * Input: + * type - Packet type for VLAN leaky. + * Output: + * pEnable - Leaky status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can get VLAN leaky status for RMA ,IGMP/MLD, CDP, CSSTP, and LLDP packets. + * The leaky frame types are as following: + * - LEAKY_BRG_GROUP, + * - LEAKY_FD_PAUSE, + * - LEAKY_SP_MCAST, + * - LEAKY_1X_PAE, + * - LEAKY_UNDEF_BRG_04, + * - LEAKY_UNDEF_BRG_05, + * - LEAKY_UNDEF_BRG_06, + * - LEAKY_UNDEF_BRG_07, + * - LEAKY_PROVIDER_BRIDGE_GROUP_ADDRESS, + * - LEAKY_UNDEF_BRG_09, + * - LEAKY_UNDEF_BRG_0A, + * - LEAKY_UNDEF_BRG_0B, + * - LEAKY_UNDEF_BRG_0C, + * - LEAKY_PROVIDER_BRIDGE_GVRP_ADDRESS, + * - LEAKY_8021AB, + * - LEAKY_UNDEF_BRG_0F, + * - LEAKY_BRG_MNGEMENT, + * - LEAKY_UNDEFINED_11, + * - LEAKY_UNDEFINED_12, + * - LEAKY_UNDEFINED_13, + * - LEAKY_UNDEFINED_14, + * - LEAKY_UNDEFINED_15, + * - LEAKY_UNDEFINED_16, + * - LEAKY_UNDEFINED_17, + * - LEAKY_UNDEFINED_18, + * - LEAKY_UNDEFINED_19, + * - LEAKY_UNDEFINED_1A, + * - LEAKY_UNDEFINED_1B, + * - LEAKY_UNDEFINED_1C, + * - LEAKY_UNDEFINED_1D, + * - LEAKY_UNDEFINED_1E, + * - LEAKY_UNDEFINED_1F, + * - LEAKY_GMRP, + * - LEAKY_GVRP, + * - LEAKY_UNDEF_GARP_22, + * - LEAKY_UNDEF_GARP_23, + * - LEAKY_UNDEF_GARP_24, + * - LEAKY_UNDEF_GARP_25, + * - LEAKY_UNDEF_GARP_26, + * - LEAKY_UNDEF_GARP_27, + * - LEAKY_UNDEF_GARP_28, + * - LEAKY_UNDEF_GARP_29, + * - LEAKY_UNDEF_GARP_2A, + * - LEAKY_UNDEF_GARP_2B, + * - LEAKY_UNDEF_GARP_2C, + * - LEAKY_UNDEF_GARP_2D, + * - LEAKY_UNDEF_GARP_2E, + * - LEAKY_UNDEF_GARP_2F, + * - LEAKY_IGMP, + * - LEAKY_IPMULTICAST. + * - LEAKY_CDP, + * - LEAKY_CSSTP, + * - LEAKY_LLDP. + */ +rtk_api_ret_t rtk_leaky_vlan_get(rtk_leaky_type_t type, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->leaky_vlan_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->leaky_vlan_get(type, pEnable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_leaky_portIsolation_set + * Description: + * Set port isolation leaky. + * Input: + * type - Packet type for port isolation leaky. + * enable - Leaky status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_ENABLE - Invalid enable input + * Note: + * This API can set port isolation leaky for RMA ,IGMP/MLD, CDP, CSSTP, and LLDP packets. + * The leaky frame types are as following: + * - LEAKY_BRG_GROUP, + * - LEAKY_FD_PAUSE, + * - LEAKY_SP_MCAST, + * - LEAKY_1X_PAE, + * - LEAKY_UNDEF_BRG_04, + * - LEAKY_UNDEF_BRG_05, + * - LEAKY_UNDEF_BRG_06, + * - LEAKY_UNDEF_BRG_07, + * - LEAKY_PROVIDER_BRIDGE_GROUP_ADDRESS, + * - LEAKY_UNDEF_BRG_09, + * - LEAKY_UNDEF_BRG_0A, + * - LEAKY_UNDEF_BRG_0B, + * - LEAKY_UNDEF_BRG_0C, + * - LEAKY_PROVIDER_BRIDGE_GVRP_ADDRESS, + * - LEAKY_8021AB, + * - LEAKY_UNDEF_BRG_0F, + * - LEAKY_BRG_MNGEMENT, + * - LEAKY_UNDEFINED_11, + * - LEAKY_UNDEFINED_12, + * - LEAKY_UNDEFINED_13, + * - LEAKY_UNDEFINED_14, + * - LEAKY_UNDEFINED_15, + * - LEAKY_UNDEFINED_16, + * - LEAKY_UNDEFINED_17, + * - LEAKY_UNDEFINED_18, + * - LEAKY_UNDEFINED_19, + * - LEAKY_UNDEFINED_1A, + * - LEAKY_UNDEFINED_1B, + * - LEAKY_UNDEFINED_1C, + * - LEAKY_UNDEFINED_1D, + * - LEAKY_UNDEFINED_1E, + * - LEAKY_UNDEFINED_1F, + * - LEAKY_GMRP, + * - LEAKY_GVRP, + * - LEAKY_UNDEF_GARP_22, + * - LEAKY_UNDEF_GARP_23, + * - LEAKY_UNDEF_GARP_24, + * - LEAKY_UNDEF_GARP_25, + * - LEAKY_UNDEF_GARP_26, + * - LEAKY_UNDEF_GARP_27, + * - LEAKY_UNDEF_GARP_28, + * - LEAKY_UNDEF_GARP_29, + * - LEAKY_UNDEF_GARP_2A, + * - LEAKY_UNDEF_GARP_2B, + * - LEAKY_UNDEF_GARP_2C, + * - LEAKY_UNDEF_GARP_2D, + * - LEAKY_UNDEF_GARP_2E, + * - LEAKY_UNDEF_GARP_2F, + * - LEAKY_IGMP, + * - LEAKY_IPMULTICAST. + * - LEAKY_CDP, + * - LEAKY_CSSTP, + * - LEAKY_LLDP. + */ +rtk_api_ret_t rtk_leaky_portIsolation_set(rtk_leaky_type_t type, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->leaky_portIsolation_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->leaky_portIsolation_set(type, enable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_leaky_portIsolation_get + * Description: + * Get port isolation leaky. + * Input: + * type - Packet type for port isolation leaky. + * Output: + * pEnable - Leaky status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can get port isolation leaky status for RMA ,IGMP/MLD, CDP, CSSTP, and LLDP packets. + * The leaky frame types are as following: + * - LEAKY_BRG_GROUP, + * - LEAKY_FD_PAUSE, + * - LEAKY_SP_MCAST, + * - LEAKY_1X_PAE, + * - LEAKY_UNDEF_BRG_04, + * - LEAKY_UNDEF_BRG_05, + * - LEAKY_UNDEF_BRG_06, + * - LEAKY_UNDEF_BRG_07, + * - LEAKY_PROVIDER_BRIDGE_GROUP_ADDRESS, + * - LEAKY_UNDEF_BRG_09, + * - LEAKY_UNDEF_BRG_0A, + * - LEAKY_UNDEF_BRG_0B, + * - LEAKY_UNDEF_BRG_0C, + * - LEAKY_PROVIDER_BRIDGE_GVRP_ADDRESS, + * - LEAKY_8021AB, + * - LEAKY_UNDEF_BRG_0F, + * - LEAKY_BRG_MNGEMENT, + * - LEAKY_UNDEFINED_11, + * - LEAKY_UNDEFINED_12, + * - LEAKY_UNDEFINED_13, + * - LEAKY_UNDEFINED_14, + * - LEAKY_UNDEFINED_15, + * - LEAKY_UNDEFINED_16, + * - LEAKY_UNDEFINED_17, + * - LEAKY_UNDEFINED_18, + * - LEAKY_UNDEFINED_19, + * - LEAKY_UNDEFINED_1A, + * - LEAKY_UNDEFINED_1B, + * - LEAKY_UNDEFINED_1C, + * - LEAKY_UNDEFINED_1D, + * - LEAKY_UNDEFINED_1E, + * - LEAKY_UNDEFINED_1F, + * - LEAKY_GMRP, + * - LEAKY_GVRP, + * - LEAKY_UNDEF_GARP_22, + * - LEAKY_UNDEF_GARP_23, + * - LEAKY_UNDEF_GARP_24, + * - LEAKY_UNDEF_GARP_25, + * - LEAKY_UNDEF_GARP_26, + * - LEAKY_UNDEF_GARP_27, + * - LEAKY_UNDEF_GARP_28, + * - LEAKY_UNDEF_GARP_29, + * - LEAKY_UNDEF_GARP_2A, + * - LEAKY_UNDEF_GARP_2B, + * - LEAKY_UNDEF_GARP_2C, + * - LEAKY_UNDEF_GARP_2D, + * - LEAKY_UNDEF_GARP_2E, + * - LEAKY_UNDEF_GARP_2F, + * - LEAKY_IGMP, + * - LEAKY_IPMULTICAST. + * - LEAKY_CDP, + * - LEAKY_CSSTP, + * - LEAKY_LLDP. + */ +rtk_api_ret_t rtk_leaky_portIsolation_get(rtk_leaky_type_t type, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->leaky_portIsolation_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->leaky_portIsolation_get(type, pEnable); + RTK_API_UNLOCK(); + + return retVal; +} diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/leaky.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/leaky.h new file mode 100644 index 00000000..ce9ea4e5 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/leaky.h @@ -0,0 +1,373 @@ + /* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8367/RTL8367C switch high-level API + * + * Feature : The file includes Leaky module high-layer API defination + * + */ + +#ifndef __RTK_API_LEAKY_H__ +#define __RTK_API_LEAKY_H__ + + +typedef enum rtk_leaky_type_e +{ + LEAKY_BRG_GROUP = 0, + LEAKY_FD_PAUSE, + LEAKY_SP_MCAST, + LEAKY_1X_PAE, + LEAKY_UNDEF_BRG_04, + LEAKY_UNDEF_BRG_05, + LEAKY_UNDEF_BRG_06, + LEAKY_UNDEF_BRG_07, + LEAKY_PROVIDER_BRIDGE_GROUP_ADDRESS, + LEAKY_UNDEF_BRG_09, + LEAKY_UNDEF_BRG_0A, + LEAKY_UNDEF_BRG_0B, + LEAKY_UNDEF_BRG_0C, + LEAKY_PROVIDER_BRIDGE_GVRP_ADDRESS, + LEAKY_8021AB, + LEAKY_UNDEF_BRG_0F, + LEAKY_BRG_MNGEMENT, + LEAKY_UNDEFINED_11, + LEAKY_UNDEFINED_12, + LEAKY_UNDEFINED_13, + LEAKY_UNDEFINED_14, + LEAKY_UNDEFINED_15, + LEAKY_UNDEFINED_16, + LEAKY_UNDEFINED_17, + LEAKY_UNDEFINED_18, + LEAKY_UNDEFINED_19, + LEAKY_UNDEFINED_1A, + LEAKY_UNDEFINED_1B, + LEAKY_UNDEFINED_1C, + LEAKY_UNDEFINED_1D, + LEAKY_UNDEFINED_1E, + LEAKY_UNDEFINED_1F, + LEAKY_GMRP, + LEAKY_GVRP, + LEAKY_UNDEF_GARP_22, + LEAKY_UNDEF_GARP_23, + LEAKY_UNDEF_GARP_24, + LEAKY_UNDEF_GARP_25, + LEAKY_UNDEF_GARP_26, + LEAKY_UNDEF_GARP_27, + LEAKY_UNDEF_GARP_28, + LEAKY_UNDEF_GARP_29, + LEAKY_UNDEF_GARP_2A, + LEAKY_UNDEF_GARP_2B, + LEAKY_UNDEF_GARP_2C, + LEAKY_UNDEF_GARP_2D, + LEAKY_UNDEF_GARP_2E, + LEAKY_UNDEF_GARP_2F, + LEAKY_IGMP, + LEAKY_IPMULTICAST, + LEAKY_CDP, + LEAKY_CSSTP, + LEAKY_LLDP, + LEAKY_END, +}rtk_leaky_type_t; + +/* Function Name: + * rtk_leaky_vlan_set + * Description: + * Set VLAN leaky. + * Input: + * type - Packet type for VLAN leaky. + * enable - Leaky status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_ENABLE - Invalid enable input + * Note: + * This API can set VLAN leaky for RMA ,IGMP/MLD, CDP, CSSTP, and LLDP packets. + * The leaky frame types are as following: + * - LEAKY_BRG_GROUP, + * - LEAKY_FD_PAUSE, + * - LEAKY_SP_MCAST, + * - LEAKY_1X_PAE, + * - LEAKY_UNDEF_BRG_04, + * - LEAKY_UNDEF_BRG_05, + * - LEAKY_UNDEF_BRG_06, + * - LEAKY_UNDEF_BRG_07, + * - LEAKY_PROVIDER_BRIDGE_GROUP_ADDRESS, + * - LEAKY_UNDEF_BRG_09, + * - LEAKY_UNDEF_BRG_0A, + * - LEAKY_UNDEF_BRG_0B, + * - LEAKY_UNDEF_BRG_0C, + * - LEAKY_PROVIDER_BRIDGE_GVRP_ADDRESS, + * - LEAKY_8021AB, + * - LEAKY_UNDEF_BRG_0F, + * - LEAKY_BRG_MNGEMENT, + * - LEAKY_UNDEFINED_11, + * - LEAKY_UNDEFINED_12, + * - LEAKY_UNDEFINED_13, + * - LEAKY_UNDEFINED_14, + * - LEAKY_UNDEFINED_15, + * - LEAKY_UNDEFINED_16, + * - LEAKY_UNDEFINED_17, + * - LEAKY_UNDEFINED_18, + * - LEAKY_UNDEFINED_19, + * - LEAKY_UNDEFINED_1A, + * - LEAKY_UNDEFINED_1B, + * - LEAKY_UNDEFINED_1C, + * - LEAKY_UNDEFINED_1D, + * - LEAKY_UNDEFINED_1E, + * - LEAKY_UNDEFINED_1F, + * - LEAKY_GMRP, + * - LEAKY_GVRP, + * - LEAKY_UNDEF_GARP_22, + * - LEAKY_UNDEF_GARP_23, + * - LEAKY_UNDEF_GARP_24, + * - LEAKY_UNDEF_GARP_25, + * - LEAKY_UNDEF_GARP_26, + * - LEAKY_UNDEF_GARP_27, + * - LEAKY_UNDEF_GARP_28, + * - LEAKY_UNDEF_GARP_29, + * - LEAKY_UNDEF_GARP_2A, + * - LEAKY_UNDEF_GARP_2B, + * - LEAKY_UNDEF_GARP_2C, + * - LEAKY_UNDEF_GARP_2D, + * - LEAKY_UNDEF_GARP_2E, + * - LEAKY_UNDEF_GARP_2F, + * - LEAKY_IGMP, + * - LEAKY_IPMULTICAST. + * - LEAKY_CDP, + * - LEAKY_CSSTP, + * - LEAKY_LLDP. + */ +extern rtk_api_ret_t rtk_leaky_vlan_set(rtk_leaky_type_t type, rtk_enable_t enable); + +/* Function Name: + * rtk_leaky_vlan_get + * Description: + * Get VLAN leaky. + * Input: + * type - Packet type for VLAN leaky. + * Output: + * pEnable - Leaky status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can get VLAN leaky status for RMA ,IGMP/MLD, CDP, CSSTP, and LLDP packets. + * The leaky frame types are as following: + * - LEAKY_BRG_GROUP, + * - LEAKY_FD_PAUSE, + * - LEAKY_SP_MCAST, + * - LEAKY_1X_PAE, + * - LEAKY_UNDEF_BRG_04, + * - LEAKY_UNDEF_BRG_05, + * - LEAKY_UNDEF_BRG_06, + * - LEAKY_UNDEF_BRG_07, + * - LEAKY_PROVIDER_BRIDGE_GROUP_ADDRESS, + * - LEAKY_UNDEF_BRG_09, + * - LEAKY_UNDEF_BRG_0A, + * - LEAKY_UNDEF_BRG_0B, + * - LEAKY_UNDEF_BRG_0C, + * - LEAKY_PROVIDER_BRIDGE_GVRP_ADDRESS, + * - LEAKY_8021AB, + * - LEAKY_UNDEF_BRG_0F, + * - LEAKY_BRG_MNGEMENT, + * - LEAKY_UNDEFINED_11, + * - LEAKY_UNDEFINED_12, + * - LEAKY_UNDEFINED_13, + * - LEAKY_UNDEFINED_14, + * - LEAKY_UNDEFINED_15, + * - LEAKY_UNDEFINED_16, + * - LEAKY_UNDEFINED_17, + * - LEAKY_UNDEFINED_18, + * - LEAKY_UNDEFINED_19, + * - LEAKY_UNDEFINED_1A, + * - LEAKY_UNDEFINED_1B, + * - LEAKY_UNDEFINED_1C, + * - LEAKY_UNDEFINED_1D, + * - LEAKY_UNDEFINED_1E, + * - LEAKY_UNDEFINED_1F, + * - LEAKY_GMRP, + * - LEAKY_GVRP, + * - LEAKY_UNDEF_GARP_22, + * - LEAKY_UNDEF_GARP_23, + * - LEAKY_UNDEF_GARP_24, + * - LEAKY_UNDEF_GARP_25, + * - LEAKY_UNDEF_GARP_26, + * - LEAKY_UNDEF_GARP_27, + * - LEAKY_UNDEF_GARP_28, + * - LEAKY_UNDEF_GARP_29, + * - LEAKY_UNDEF_GARP_2A, + * - LEAKY_UNDEF_GARP_2B, + * - LEAKY_UNDEF_GARP_2C, + * - LEAKY_UNDEF_GARP_2D, + * - LEAKY_UNDEF_GARP_2E, + * - LEAKY_UNDEF_GARP_2F, + * - LEAKY_IGMP, + * - LEAKY_IPMULTICAST. + * - LEAKY_CDP, + * - LEAKY_CSSTP, + * - LEAKY_LLDP. + */ +extern rtk_api_ret_t rtk_leaky_vlan_get(rtk_leaky_type_t type, rtk_enable_t *pEnable); + +/* Function Name: + * rtk_leaky_portIsolation_set + * Description: + * Set port isolation leaky. + * Input: + * type - Packet type for port isolation leaky. + * enable - Leaky status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_ENABLE - Invalid enable input + * Note: + * This API can set port isolation leaky for RMA ,IGMP/MLD, CDP, CSSTP, and LLDP packets. + * The leaky frame types are as following: + * - LEAKY_BRG_GROUP, + * - LEAKY_FD_PAUSE, + * - LEAKY_SP_MCAST, + * - LEAKY_1X_PAE, + * - LEAKY_UNDEF_BRG_04, + * - LEAKY_UNDEF_BRG_05, + * - LEAKY_UNDEF_BRG_06, + * - LEAKY_UNDEF_BRG_07, + * - LEAKY_PROVIDER_BRIDGE_GROUP_ADDRESS, + * - LEAKY_UNDEF_BRG_09, + * - LEAKY_UNDEF_BRG_0A, + * - LEAKY_UNDEF_BRG_0B, + * - LEAKY_UNDEF_BRG_0C, + * - LEAKY_PROVIDER_BRIDGE_GVRP_ADDRESS, + * - LEAKY_8021AB, + * - LEAKY_UNDEF_BRG_0F, + * - LEAKY_BRG_MNGEMENT, + * - LEAKY_UNDEFINED_11, + * - LEAKY_UNDEFINED_12, + * - LEAKY_UNDEFINED_13, + * - LEAKY_UNDEFINED_14, + * - LEAKY_UNDEFINED_15, + * - LEAKY_UNDEFINED_16, + * - LEAKY_UNDEFINED_17, + * - LEAKY_UNDEFINED_18, + * - LEAKY_UNDEFINED_19, + * - LEAKY_UNDEFINED_1A, + * - LEAKY_UNDEFINED_1B, + * - LEAKY_UNDEFINED_1C, + * - LEAKY_UNDEFINED_1D, + * - LEAKY_UNDEFINED_1E, + * - LEAKY_UNDEFINED_1F, + * - LEAKY_GMRP, + * - LEAKY_GVRP, + * - LEAKY_UNDEF_GARP_22, + * - LEAKY_UNDEF_GARP_23, + * - LEAKY_UNDEF_GARP_24, + * - LEAKY_UNDEF_GARP_25, + * - LEAKY_UNDEF_GARP_26, + * - LEAKY_UNDEF_GARP_27, + * - LEAKY_UNDEF_GARP_28, + * - LEAKY_UNDEF_GARP_29, + * - LEAKY_UNDEF_GARP_2A, + * - LEAKY_UNDEF_GARP_2B, + * - LEAKY_UNDEF_GARP_2C, + * - LEAKY_UNDEF_GARP_2D, + * - LEAKY_UNDEF_GARP_2E, + * - LEAKY_UNDEF_GARP_2F, + * - LEAKY_IGMP, + * - LEAKY_IPMULTICAST. + * - LEAKY_CDP, + * - LEAKY_CSSTP, + * - LEAKY_LLDP. + */ +extern rtk_api_ret_t rtk_leaky_portIsolation_set(rtk_leaky_type_t type, rtk_enable_t enable); + +/* Function Name: + * rtk_leaky_portIsolation_get + * Description: + * Get port isolation leaky. + * Input: + * type - Packet type for port isolation leaky. + * Output: + * pEnable - Leaky status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can get port isolation leaky status for RMA ,IGMP/MLD, CDP, CSSTP, and LLDP packets. + * The leaky frame types are as following: + * - LEAKY_BRG_GROUP, + * - LEAKY_FD_PAUSE, + * - LEAKY_SP_MCAST, + * - LEAKY_1X_PAE, + * - LEAKY_UNDEF_BRG_04, + * - LEAKY_UNDEF_BRG_05, + * - LEAKY_UNDEF_BRG_06, + * - LEAKY_UNDEF_BRG_07, + * - LEAKY_PROVIDER_BRIDGE_GROUP_ADDRESS, + * - LEAKY_UNDEF_BRG_09, + * - LEAKY_UNDEF_BRG_0A, + * - LEAKY_UNDEF_BRG_0B, + * - LEAKY_UNDEF_BRG_0C, + * - LEAKY_PROVIDER_BRIDGE_GVRP_ADDRESS, + * - LEAKY_8021AB, + * - LEAKY_UNDEF_BRG_0F, + * - LEAKY_BRG_MNGEMENT, + * - LEAKY_UNDEFINED_11, + * - LEAKY_UNDEFINED_12, + * - LEAKY_UNDEFINED_13, + * - LEAKY_UNDEFINED_14, + * - LEAKY_UNDEFINED_15, + * - LEAKY_UNDEFINED_16, + * - LEAKY_UNDEFINED_17, + * - LEAKY_UNDEFINED_18, + * - LEAKY_UNDEFINED_19, + * - LEAKY_UNDEFINED_1A, + * - LEAKY_UNDEFINED_1B, + * - LEAKY_UNDEFINED_1C, + * - LEAKY_UNDEFINED_1D, + * - LEAKY_UNDEFINED_1E, + * - LEAKY_UNDEFINED_1F, + * - LEAKY_GMRP, + * - LEAKY_GVRP, + * - LEAKY_UNDEF_GARP_22, + * - LEAKY_UNDEF_GARP_23, + * - LEAKY_UNDEF_GARP_24, + * - LEAKY_UNDEF_GARP_25, + * - LEAKY_UNDEF_GARP_26, + * - LEAKY_UNDEF_GARP_27, + * - LEAKY_UNDEF_GARP_28, + * - LEAKY_UNDEF_GARP_29, + * - LEAKY_UNDEF_GARP_2A, + * - LEAKY_UNDEF_GARP_2B, + * - LEAKY_UNDEF_GARP_2C, + * - LEAKY_UNDEF_GARP_2D, + * - LEAKY_UNDEF_GARP_2E, + * - LEAKY_UNDEF_GARP_2F, + * - LEAKY_IGMP, + * - LEAKY_IPMULTICAST. + * - LEAKY_CDP, + * - LEAKY_CSSTP, + * - LEAKY_LLDP. + */ +extern rtk_api_ret_t rtk_leaky_portIsolation_get(rtk_leaky_type_t type, rtk_enable_t *pEnable); + +#endif /* __RTK_API_LEAKY_H__ */ + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/led.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/led.c new file mode 100644 index 00000000..e248deb2 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/led.c @@ -0,0 +1,632 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8367C + * Feature : Here is a list of all functions and variables in LED module. + * + */ + +#include +#include +#include +#include +#include + +/* Function Name: + * rtk_led_enable_set + * Description: + * Set Led enable congiuration + * Input: + * group - LED group id. + * pPortmask - LED enable port mask. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_MASK - Error portmask + * Note: + * The API can be used to enable LED per port per group. + */ +rtk_api_ret_t rtk_led_enable_set(rtk_led_group_t group, rtk_portmask_t *pPortmask) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->led_enable_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->led_enable_set(group, pPortmask); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_led_enable_get + * Description: + * Get Led enable congiuration + * Input: + * group - LED group id. + * Output: + * pPortmask - LED enable port mask. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can be used to get LED enable status. + */ +rtk_api_ret_t rtk_led_enable_get(rtk_led_group_t group, rtk_portmask_t *pPortmask) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->led_enable_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->led_enable_get(group, pPortmask); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_led_operation_set + * Description: + * Set Led operation mode + * Input: + * mode - LED operation mode. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can set Led operation mode. + * The modes that can be set are as following: + * - LED_OP_SCAN, + * - LED_OP_PARALLEL, + * - LED_OP_SERIAL, + */ +rtk_api_ret_t rtk_led_operation_set(rtk_led_operation_t mode) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->led_operation_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->led_operation_set(mode); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_led_operation_get + * Description: + * Get Led operation mode + * Input: + * None + * Output: + * pMode - Support LED operation mode. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get Led operation mode. + * The modes that can be set are as following: + * - LED_OP_SCAN, + * - LED_OP_PARALLEL, + * - LED_OP_SERIAL, + */ +rtk_api_ret_t rtk_led_operation_get(rtk_led_operation_t *pMode) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->led_operation_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->led_operation_get(pMode); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_led_modeForce_set + * Description: + * Set Led group to congiuration force mode + * Input: + * port - port ID + * group - Support LED group id. + * mode - Support LED force mode. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Error Port ID + * Note: + * The API can force to one force mode. + * The force modes that can be set are as following: + * - LED_FORCE_NORMAL, + * - LED_FORCE_BLINK, + * - LED_FORCE_OFF, + * - LED_FORCE_ON. + */ +rtk_api_ret_t rtk_led_modeForce_set(rtk_port_t port, rtk_led_group_t group, rtk_led_force_mode_t mode) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->led_modeForce_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->led_modeForce_set(port, group, mode); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_led_modeForce_get + * Description: + * Get Led group to congiuration force mode + * Input: + * port - port ID + * group - Support LED group id. + * pMode - Support LED force mode. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Error Port ID + * Note: + * The API can get forced Led group mode. + * The force modes that can be set are as following: + * - LED_FORCE_NORMAL, + * - LED_FORCE_BLINK, + * - LED_FORCE_OFF, + * - LED_FORCE_ON. + */ +rtk_api_ret_t rtk_led_modeForce_get(rtk_port_t port, rtk_led_group_t group, rtk_led_force_mode_t *pMode) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->led_modeForce_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->led_modeForce_get(port, group, pMode); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_led_blinkRate_set + * Description: + * Set LED blinking rate + * Input: + * blinkRate - blinking rate. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API configure LED blinking rate: + * - LED_BLINKRATE_32MS + * - LED_BLINKRATE_64MS, + * - LED_BLINKRATE_128MS, + * - LED_BLINKRATE_256MS, + * - LED_BLINKRATE_512MS, + * - LED_BLINKRATE_1024MS, + * - LED_BLINKRATE_48MS, + * - LED_BLINKRATE_96MS, + */ +rtk_api_ret_t rtk_led_blinkRate_set(rtk_led_blink_rate_t blinkRate) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->led_blinkRate_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->led_blinkRate_set(blinkRate); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_led_blinkRate_get + * Description: + * Get LED blinking rate at mode 0 to mode 3 + * Input: + * None + * Output: + * pBlinkRate - blinking rate. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API get LED blinking rate: + * - LED_BLINKRATE_32MS + * - LED_BLINKRATE_64MS, + * - LED_BLINKRATE_128MS, + * - LED_BLINKRATE_256MS, + * - LED_BLINKRATE_512MS, + * - LED_BLINKRATE_1024MS, + * - LED_BLINKRATE_48MS, + * - LED_BLINKRATE_96MS, + */ +rtk_api_ret_t rtk_led_blinkRate_get(rtk_led_blink_rate_t *pBlinkRate) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->led_blinkRate_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->led_blinkRate_get(pBlinkRate); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_led_groupConfig_set + * Description: + * Set per group Led to congiuration mode + * Input: + * group - LED group. + * config - LED configuration + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can set LED indicated information configuration for each LED group with 1 to 1 led mapping to each port. + * - Definition LED Statuses Description + * - 0000 LED_Off LED pin Tri-State. + * - 0001 Dup/Col Collision, Full duplex Indicator. + * - 0010 Link/Act Link, Activity Indicator. + * - 0011 Spd1000 1000Mb/s Speed Indicator. + * - 0100 Spd100 100Mb/s Speed Indicator. + * - 0101 Spd10 10Mb/s Speed Indicator. + * - 0110 Spd1000/Act 1000Mb/s Speed/Activity Indicator. + * - 0111 Spd100/Act 100Mb/s Speed/Activity Indicator. + * - 1000 Spd10/Act 10Mb/s Speed/Activity Indicator. + * - 1001 Spd100 (10)/Act 10/100Mb/s Speed/Activity Indicator. + * - 1010 LoopDetect LoopDetect Indicator. + * - 1011 EEE EEE Indicator. + * - 1100 Link/Rx Link, Activity Indicator. + * - 1101 Link/Tx Link, Activity Indicator. + * - 1110 Master Link on Master Indicator. + * - 1111 Act Activity Indicator. Low for link established. + */ +rtk_api_ret_t rtk_led_groupConfig_set(rtk_led_group_t group, rtk_led_congig_t config) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->led_groupConfig_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->led_groupConfig_set(group, config); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_led_groupConfig_get + * Description: + * Get Led group congiuration mode + * Input: + * group - LED group. + * Output: + * pConfig - LED configuration. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get LED indicated information configuration for each LED group. + */ +rtk_api_ret_t rtk_led_groupConfig_get(rtk_led_group_t group, rtk_led_congig_t *pConfig) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->led_groupConfig_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->led_groupConfig_get(group, pConfig); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_led_groupAbility_set + * Description: + * Configure per group Led ability + * Input: + * group - LED group. + * pAbility - LED ability + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * None. + */ + +rtk_api_ret_t rtk_led_groupAbility_set(rtk_led_group_t group, rtk_led_ability_t *pAbility) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->led_groupAbility_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->led_groupAbility_set(group, pAbility); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_led_groupAbility_get + * Description: + * Get per group Led ability + * Input: + * group - LED group. + * pAbility - LED ability + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * None. + */ + +rtk_api_ret_t rtk_led_groupAbility_get(rtk_led_group_t group, rtk_led_ability_t *pAbility) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->led_groupAbility_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->led_groupAbility_get(group, pAbility); + RTK_API_UNLOCK(); + + return retVal; +} + + +/* Function Name: + * rtk_led_serialMode_set + * Description: + * Set Led serial mode active congiuration + * Input: + * active - LED group. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can set LED serial mode active congiuration. + */ +rtk_api_ret_t rtk_led_serialMode_set(rtk_led_active_t active) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->led_serialMode_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->led_serialMode_set(active); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_led_serialMode_get + * Description: + * Get Led group congiuration mode + * Input: + * group - LED group. + * Output: + * pConfig - LED configuration. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get LED serial mode active configuration. + */ +rtk_api_ret_t rtk_led_serialMode_get(rtk_led_active_t *pActive) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->led_serialMode_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->led_serialMode_get(pActive); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_led_OutputEnable_set + * Description: + * This API set LED I/O state. + * Input: + * enabled - LED I/O state + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error parameter + * Note: + * This API set LED I/O state. + */ +rtk_api_ret_t rtk_led_OutputEnable_set(rtk_enable_t state) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->led_OutputEnable_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->led_OutputEnable_set(state); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_led_OutputEnable_get + * Description: + * This API get LED I/O state. + * Input: + * None. + * Output: + * pEnabled - LED I/O state + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error parameter + * Note: + * This API set current LED I/O state. + */ +rtk_api_ret_t rtk_led_OutputEnable_get(rtk_enable_t *pState) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->led_OutputEnable_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->led_OutputEnable_get(pState); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_led_serialModePortmask_set + * Description: + * This API configure Serial LED output Group and portmask + * Input: + * output - output group + * pPortmask - output portmask + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error parameter + * Note: + * None. + */ +rtk_api_ret_t rtk_led_serialModePortmask_set(rtk_led_serialOutput_t output, rtk_portmask_t *pPortmask) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->led_serialModePortmask_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->led_serialModePortmask_set(output, pPortmask); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_led_serialModePortmask_get + * Description: + * This API get Serial LED output Group and portmask + * Input: + * None. + * Output: + * pOutput - output group + * pPortmask - output portmask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error parameter + * Note: + * None. + */ +rtk_api_ret_t rtk_led_serialModePortmask_get(rtk_led_serialOutput_t *pOutput, rtk_portmask_t *pPortmask) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->led_serialModePortmask_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->led_serialModePortmask_get(pOutput, pPortmask); + RTK_API_UNLOCK(); + + return retVal; +} + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/led.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/led.h new file mode 100644 index 00000000..bffaf0d9 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/led.h @@ -0,0 +1,501 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8367/RTL8367C switch high-level API + * + * Feature : The file includes LED module high-layer API defination + * + */ + +#ifndef __RTK_API_LED_H__ +#define __RTK_API_LED_H__ + +typedef enum rtk_led_operation_e +{ + LED_OP_SCAN=0, + LED_OP_PARALLEL, + LED_OP_SERIAL, + LED_OP_END, +}rtk_led_operation_t; + + +typedef enum rtk_led_active_e +{ + /* conflict with fal/fal_led.h, not used*/ + RTK_LED_ACTIVE_HIGH=0, + LED_ACTIVE_LOW, + LED_ACTIVE_END, +}rtk_led_active_t; + +typedef enum rtk_led_config_e +{ + LED_CONFIG_LEDOFF=0, + LED_CONFIG_DUPCOL, + LED_CONFIG_LINK_ACT, + LED_CONFIG_SPD1000, + LED_CONFIG_SPD100, + LED_CONFIG_SPD10, + LED_CONFIG_SPD1000ACT, + LED_CONFIG_SPD100ACT, + LED_CONFIG_SPD10ACT, + LED_CONFIG_SPD10010ACT, + LED_CONFIG_LOOPDETECT, + LED_CONFIG_EEE, + LED_CONFIG_LINKRX, + LED_CONFIG_LINKTX, + LED_CONFIG_MASTER, + LED_CONFIG_ACT, + LED_CONFIG_END, +}rtk_led_congig_t; + +typedef struct rtk_led_ability_s +{ + rtk_enable_t link_10m; + rtk_enable_t link_100m; + rtk_enable_t link_500m; + rtk_enable_t link_1000m; + rtk_enable_t link_2500m; + rtk_enable_t act_rx; + rtk_enable_t act_tx; +}rtk_led_ability_t; + +typedef enum rtk_led_blink_rate_e +{ + LED_BLINKRATE_32MS=0, + LED_BLINKRATE_64MS, + LED_BLINKRATE_128MS, + LED_BLINKRATE_256MS, + LED_BLINKRATE_512MS, + LED_BLINKRATE_1024MS, + LED_BLINKRATE_48MS, + LED_BLINKRATE_96MS, + LED_BLINKRATE_END, +}rtk_led_blink_rate_t; + +typedef enum rtk_led_group_e +{ + LED_GROUP_0 = 0, + LED_GROUP_1, + LED_GROUP_2, + LED_GROUP_END +}rtk_led_group_t; + + +typedef enum rtk_led_force_mode_e +{ + LED_FORCE_NORMAL=0, + LED_FORCE_BLINK, + LED_FORCE_OFF, + LED_FORCE_ON, + LED_FORCE_END +}rtk_led_force_mode_t; + +typedef enum rtk_led_serialOutput_e +{ + SERIAL_LED_NONE = 0, + SERIAL_LED_0, + SERIAL_LED_0_1, + SERIAL_LED_0_2, + SERIAL_LED_END, +}rtk_led_serialOutput_t; + + +/* Function Name: + * rtk_led_enable_set + * Description: + * Set Led enable congiuration + * Input: + * group - LED group id. + * pPortmask - LED enable port mask. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can be used to enable LED per port per group. + */ +extern rtk_api_ret_t rtk_led_enable_set(rtk_led_group_t group, rtk_portmask_t *pPortmask); + +/* Function Name: + * rtk_led_enable_get + * Description: + * Get Led enable congiuration + * Input: + * group - LED group id. + * Output: + * pPortmask - LED enable port mask. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can be used to get LED enable status. + */ +extern rtk_api_ret_t rtk_led_enable_get(rtk_led_group_t group, rtk_portmask_t *pPortmask); + +/* Function Name: + * rtk_led_operation_set + * Description: + * Set Led operation mode + * Input: + * mode - LED operation mode. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can set Led operation mode. + * The modes that can be set are as following: + * - LED_OP_SCAN, + * - LED_OP_PARALLEL, + * - LED_OP_SERIAL, + */ +extern rtk_api_ret_t rtk_led_operation_set(rtk_led_operation_t mode); + +/* Function Name: + * rtk_led_operation_get + * Description: + * Get Led operation mode + * Input: + * None + * Output: + * pMode - Support LED operation mode. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get Led operation mode. + * The modes that can be set are as following: + * - LED_OP_SCAN, + * - LED_OP_PARALLEL, + * - LED_OP_SERIAL, + */ +extern rtk_api_ret_t rtk_led_operation_get(rtk_led_operation_t *pMode); + +/* Function Name: + * rtk_led_modeForce_set + * Description: + * Set Led group to congiuration force mode + * Input: + * port - port ID + * group - Support LED group id. + * mode - Support LED force mode. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Error Port ID + * Note: + * The API can force to one force mode. + * The force modes that can be set are as following: + * - LED_FORCE_NORMAL, + * - LED_FORCE_BLINK, + * - LED_FORCE_OFF, + * - LED_FORCE_ON. + */ +extern rtk_api_ret_t rtk_led_modeForce_set(rtk_port_t port, rtk_led_group_t group, rtk_led_force_mode_t mode); + +/* Function Name: + * rtk_led_modeForce_get + * Description: + * Get Led group to congiuration force mode + * Input: + * port - port ID + * group - Support LED group id. + * pMode - Support LED force mode. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Error Port ID + * Note: + * The API can get forced Led group mode. + * The force modes that can be set are as following: + * - LED_FORCE_NORMAL, + * - LED_FORCE_BLINK, + * - LED_FORCE_OFF, + * - LED_FORCE_ON. + */ +extern rtk_api_ret_t rtk_led_modeForce_get(rtk_port_t port, rtk_led_group_t group, rtk_led_force_mode_t *pMode); + +/* Function Name: + * rtk_led_blinkRate_set + * Description: + * Set LED blinking rate + * Input: + * blinkRate - blinking rate. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API configure LED blinking rate: + * - LED_BLINKRATE_32MS + * - LED_BLINKRATE_64MS, + * - LED_BLINKRATE_128MS, + * - LED_BLINKRATE_256MS, + * - LED_BLINKRATE_512MS, + * - LED_BLINKRATE_1024MS, + * - LED_BLINKRATE_48MS, + * - LED_BLINKRATE_96MS, + */ +extern rtk_api_ret_t rtk_led_blinkRate_set(rtk_led_blink_rate_t blinkRate); + +/* Function Name: + * rtk_led_blinkRate_get + * Description: + * Get LED blinking rate at mode 0 to mode 3 + * Input: + * None + * Output: + * pBlinkRate - blinking rate. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API get LED blinking rate: + * - LED_BLINKRATE_32MS + * - LED_BLINKRATE_64MS, + * - LED_BLINKRATE_128MS, + * - LED_BLINKRATE_256MS, + * - LED_BLINKRATE_512MS, + * - LED_BLINKRATE_1024MS, + * - LED_BLINKRATE_48MS, + * - LED_BLINKRATE_96MS, + */ +extern rtk_api_ret_t rtk_led_blinkRate_get(rtk_led_blink_rate_t *pBlinkRate); + +/* Function Name: + * rtk_led_groupConfig_set + * Description: + * Set per group Led to congiuration mode + * Input: + * group - LED group. + * config - LED configuration + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can set LED indicated information configuration for each LED group with 1 to 1 led mapping to each port. + * - Definition LED Statuses Description + * - 0000 LED_Off LED pin Tri-State. + * - 0001 Dup/Col Collision, Full duplex Indicator. + * - 0010 Link/Act Link, Activity Indicator. + * - 0011 Spd1000 1000Mb/s Speed Indicator. + * - 0100 Spd100 100Mb/s Speed Indicator. + * - 0101 Spd10 10Mb/s Speed Indicator. + * - 0110 Spd1000/Act 1000Mb/s Speed/Activity Indicator. + * - 0111 Spd100/Act 100Mb/s Speed/Activity Indicator. + * - 1000 Spd10/Act 10Mb/s Speed/Activity Indicator. + * - 1001 Spd100 (10)/Act 10/100Mb/s Speed/Activity Indicator. + * - 1010 LoopDetect LoopDetect Indicator. + * - 1011 EEE EEE Indicator. + * - 1100 Link/Rx Link, Activity Indicator. + * - 1101 Link/Tx Link, Activity Indicator. + * - 1110 Master Link on Master Indicator. + * - 1111 Act Activity Indicator. Low for link established. + */ +extern rtk_api_ret_t rtk_led_groupConfig_set(rtk_led_group_t group, rtk_led_congig_t config); + +/* Function Name: + * rtk_led_groupConfig_get + * Description: + * Get Led group congiuration mode + * Input: + * group - LED group. + * Output: + * pConfig - LED configuration. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get LED indicated information configuration for each LED group. + */ +extern rtk_api_ret_t rtk_led_groupConfig_get(rtk_led_group_t group, rtk_led_congig_t *pConfig); + +/* Function Name: + * rtk_led_groupAbility_set + * Description: + * Configure per group Led ability + * Input: + * group - LED group. + * pAbility - LED ability + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * None. + */ + +extern rtk_api_ret_t rtk_led_groupAbility_set(rtk_led_group_t group, rtk_led_ability_t *pAbility); + +/* Function Name: + * rtk_led_groupAbility_get + * Description: + * Get per group Led ability + * Input: + * group - LED group. + * pAbility - LED ability + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * None. + */ + +extern rtk_api_ret_t rtk_led_groupAbility_get(rtk_led_group_t group, rtk_led_ability_t *pAbility); + +/* Function Name: + * rtk_led_serialMode_set + * Description: + * Set Led serial mode active congiuration + * Input: + * active - LED group. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can set LED serial mode active congiuration. + */ +extern rtk_api_ret_t rtk_led_serialMode_set(rtk_led_active_t active); + +/* Function Name: + * rtk_led_serialMode_get + * Description: + * Get Led group congiuration mode + * Input: + * group - LED group. + * Output: + * pConfig - LED configuration. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get LED serial mode active configuration. + */ +extern rtk_api_ret_t rtk_led_serialMode_get(rtk_led_active_t *pActive); + +/* Function Name: + * rtk_led_OutputEnable_set + * Description: + * This API set LED I/O state. + * Input: + * enabled - LED I/O state + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error parameter + * Note: + * This API set LED I/O state. + */ +extern rtk_api_ret_t rtk_led_OutputEnable_set(rtk_enable_t state); + + +/* Function Name: + * rtk_led_OutputEnable_get + * Description: + * This API get LED I/O state. + * Input: + * None. + * Output: + * pEnabled - LED I/O state + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error parameter + * Note: + * This API set current LED I/O state. + */ +extern rtk_api_ret_t rtk_led_OutputEnable_get(rtk_enable_t *pState); + +/* Function Name: + * rtk_led_serialModePortmask_set + * Description: + * This API configure Serial LED output Group and portmask + * Input: + * output - output group + * pPortmask - output portmask + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error parameter + * Note: + * None. + */ +extern rtk_api_ret_t rtk_led_serialModePortmask_set(rtk_led_serialOutput_t output, rtk_portmask_t *pPortmask); + +/* Function Name: + * rtk_led_serialModePortmask_get + * Description: + * This API get Serial LED output Group and portmask + * Input: + * None. + * Output: + * pOutput - output group + * pPortmask - output portmask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error parameter + * Note: + * None. + */ +extern rtk_api_ret_t rtk_led_serialModePortmask_get(rtk_led_serialOutput_t *pOutput, rtk_portmask_t *pPortmask); + +#endif /* __RTK_API_LED_H__ */ diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/mirror.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/mirror.c new file mode 100644 index 00000000..ba65b668 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/mirror.c @@ -0,0 +1,410 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8367C + * Feature : Here is a list of all functions and variables in Mirror module. + * + */ + +#include +#include +#include +#include +#include + +/* Function Name: + * rtk_mirror_portBased_set + * Description: + * Set port mirror function. + * Input: + * mirroring_port - Monitor port. + * pMirrored_rx_portmask - Rx mirror port mask. + * pMirrored_tx_portmask - Tx mirror port mask. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * RT_ERR_PORT_MASK - Invalid portmask. + * Note: + * The API is to set mirror function of source port and mirror port. + * The mirror port can only be set to one port and the TX and RX mirror ports + * should be identical. + */ +rtk_api_ret_t rtk_mirror_portBased_set(rtk_port_t mirroring_port, rtk_portmask_t *pMirrored_rx_portmask, rtk_portmask_t *pMirrored_tx_portmask) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->mirror_portBased_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->mirror_portBased_set(mirroring_port, pMirrored_rx_portmask, pMirrored_tx_portmask); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_mirror_portBased_get + * Description: + * Get port mirror function. + * Input: + * None + * Output: + * pMirroring_port - Monitor port. + * pMirrored_rx_portmask - Rx mirror port mask. + * pMirrored_tx_portmask - Tx mirror port mask. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API is to get mirror function of source port and mirror port. + */ +rtk_api_ret_t rtk_mirror_portBased_get(rtk_port_t *pMirroring_port, rtk_portmask_t *pMirrored_rx_portmask, rtk_portmask_t *pMirrored_tx_portmask) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->mirror_portBased_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->mirror_portBased_get(pMirroring_port, pMirrored_rx_portmask, pMirrored_tx_portmask); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_mirror_portIso_set + * Description: + * Set mirror port isolation. + * Input: + * enable |Mirror isolation status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid enable input + * Note: + * The API is to set mirror isolation function that prevent normal forwarding packets to miror port. + */ +rtk_api_ret_t rtk_mirror_portIso_set(rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->mirror_portIso_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->mirror_portIso_set(enable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_mirror_portIso_get + * Description: + * Get mirror port isolation. + * Input: + * None + * Output: + * pEnable |Mirror isolation status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API is to get mirror isolation status. + */ +rtk_api_ret_t rtk_mirror_portIso_get(rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->mirror_portIso_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->mirror_portIso_get(pEnable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_mirror_vlanLeaky_set + * Description: + * Set mirror VLAN leaky. + * Input: + * txenable -TX leaky enable. + * rxenable - RX leaky enable. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid enable input + * Note: + * The API is to set mirror VLAN leaky function forwarding packets to miror port. + */ +rtk_api_ret_t rtk_mirror_vlanLeaky_set(rtk_enable_t txenable, rtk_enable_t rxenable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->mirror_vlanLeaky_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->mirror_vlanLeaky_set(txenable, rxenable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_mirror_vlanLeaky_get + * Description: + * Get mirror VLAN leaky. + * Input: + * None + * Output: + * pTxenable - TX leaky enable. + * pRxenable - RX leaky enable. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API is to get mirror VLAN leaky status. + */ +rtk_api_ret_t rtk_mirror_vlanLeaky_get(rtk_enable_t *pTxenable, rtk_enable_t *pRxenable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->mirror_vlanLeaky_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->mirror_vlanLeaky_get(pTxenable, pRxenable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_mirror_isolationLeaky_set + * Description: + * Set mirror Isolation leaky. + * Input: + * txenable -TX leaky enable. + * rxenable - RX leaky enable. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid enable input + * Note: + * The API is to set mirror VLAN leaky function forwarding packets to miror port. + */ +rtk_api_ret_t rtk_mirror_isolationLeaky_set(rtk_enable_t txenable, rtk_enable_t rxenable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->mirror_isolationLeaky_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->mirror_isolationLeaky_set(txenable, rxenable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_mirror_isolationLeaky_get + * Description: + * Get mirror isolation leaky. + * Input: + * None + * Output: + * pTxenable - TX leaky enable. + * pRxenable - RX leaky enable. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API is to get mirror isolation leaky status. + */ +rtk_api_ret_t rtk_mirror_isolationLeaky_get(rtk_enable_t *pTxenable, rtk_enable_t *pRxenable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->mirror_isolationLeaky_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->mirror_isolationLeaky_get(pTxenable, pRxenable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_mirror_keep_set + * Description: + * Set mirror packet format keep. + * Input: + * mode - -mirror keep mode. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid enable input + * Note: + * The API is to set -mirror keep mode. + * The mirror keep mode is as following: + * - MIRROR_FOLLOW_VLAN + * - MIRROR_KEEP_ORIGINAL + * - MIRROR_KEEP_END + */ +rtk_api_ret_t rtk_mirror_keep_set(rtk_mirror_keep_t mode) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->mirror_keep_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->mirror_keep_set(mode); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_mirror_keep_get + * Description: + * Get mirror packet format keep. + * Input: + * None + * Output: + * pMode -mirror keep mode. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API is to get mirror keep mode. + * The mirror keep mode is as following: + * - MIRROR_FOLLOW_VLAN + * - MIRROR_KEEP_ORIGINAL + * - MIRROR_KEEP_END + */ +rtk_api_ret_t rtk_mirror_keep_get(rtk_mirror_keep_t *pMode) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->mirror_keep_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->mirror_keep_get(pMode); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_mirror_override_set + * Description: + * Set port mirror override function. + * Input: + * rxMirror - 1: output mirrored packet, 0: output normal forward packet + * txMirror - 1: output mirrored packet, 0: output normal forward packet + * aclMirror - 1: output mirrored packet, 0: output normal forward packet + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API is to set mirror override function. + * This function control the output format when a port output + * normal forward & mirrored packet at the same time. + */ +rtk_api_ret_t rtk_mirror_override_set(rtk_enable_t rxMirror, rtk_enable_t txMirror, rtk_enable_t aclMirror) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->mirror_override_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->mirror_override_set(rxMirror, txMirror, aclMirror); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_mirror_override_get + * Description: + * Get port mirror override function. + * Input: + * None + * Output: + * pRxMirror - 1: output mirrored packet, 0: output normal forward packet + * pTxMirror - 1: output mirrored packet, 0: output normal forward packet + * pAclMirror - 1: output mirrored packet, 0: output normal forward packet + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Null Pointer + * Note: + * The API is to Get mirror override function. + * This function control the output format when a port output + * normal forward & mirrored packet at the same time. + */ +rtk_api_ret_t rtk_mirror_override_get(rtk_enable_t *pRxMirror, rtk_enable_t *pTxMirror, rtk_enable_t *pAclMirror) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->mirror_override_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->mirror_override_get(pRxMirror, pTxMirror, pAclMirror); + RTK_API_UNLOCK(); + + return retVal; +} diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/mirror.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/mirror.h new file mode 100644 index 00000000..3f364528 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/mirror.h @@ -0,0 +1,274 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8367/RTL8367C switch high-level API + * + * Feature : The file includes Mirror module high-layer API defination + * + */ + +#ifndef __RTK_API_MIRROR_H__ +#define __RTK_API_MIRROR_H__ + +typedef enum rtk_mirror_keep_e +{ + MIRROR_FOLLOW_VLAN = 0, + MIRROR_KEEP_ORIGINAL, + MIRROR_KEEP_END +}rtk_mirror_keep_t; + + +/* Function Name: + * rtk_mirror_portBased_set + * Description: + * Set port mirror function. + * Input: + * mirroring_port - Monitor port. + * pMirrored_rx_portmask - Rx mirror port mask. + * pMirrored_tx_portmask - Tx mirror port mask. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * RT_ERR_PORT_MASK - Invalid portmask. + * Note: + * The API is to set mirror function of source port and mirror port. + * The mirror port can only be set to one port and the TX and RX mirror ports + * should be identical. + */ +extern rtk_api_ret_t rtk_mirror_portBased_set(rtk_port_t mirroring_port, rtk_portmask_t *pMirrored_rx_portmask, rtk_portmask_t *pMirrored_tx_portmask); + +/* Function Name: + * rtk_mirror_portBased_get + * Description: + * Get port mirror function. + * Input: + * None + * Output: + * pMirroring_port - Monitor port. + * pMirrored_rx_portmask - Rx mirror port mask. + * pMirrored_tx_portmask - Tx mirror port mask. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API is to get mirror function of source port and mirror port. + */ +extern rtk_api_ret_t rtk_mirror_portBased_get(rtk_port_t* pMirroring_port, rtk_portmask_t *pMirrored_rx_portmask, rtk_portmask_t *pMirrored_tx_portmask); + +/* Function Name: + * rtk_mirror_portIso_set + * Description: + * Set mirror port isolation. + * Input: + * enable |Mirror isolation status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid enable input + * Note: + * The API is to set mirror isolation function that prevent normal forwarding packets to miror port. + */ +extern rtk_api_ret_t rtk_mirror_portIso_set(rtk_enable_t enable); + +/* Function Name: + * rtk_mirror_portIso_get + * Description: + * Get mirror port isolation. + * Input: + * None + * Output: + * pEnable |Mirror isolation status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API is to get mirror isolation status. + */ +extern rtk_api_ret_t rtk_mirror_portIso_get(rtk_enable_t *pEnable); + +/* Function Name: + * rtk_mirror_vlanLeaky_set + * Description: + * Set mirror VLAN leaky. + * Input: + * txenable -TX leaky enable. + * rxenable - RX leaky enable. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid enable input + * Note: + * The API is to set mirror VLAN leaky function forwarding packets to miror port. + */ +extern rtk_api_ret_t rtk_mirror_vlanLeaky_set(rtk_enable_t txenable, rtk_enable_t rxenable); + + +/* Function Name: + * rtk_mirror_vlanLeaky_get + * Description: + * Get mirror VLAN leaky. + * Input: + * None + * Output: + * pTxenable - TX leaky enable. + * pRxenable - RX leaky enable. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API is to get mirror VLAN leaky status. + */ +extern rtk_api_ret_t rtk_mirror_vlanLeaky_get(rtk_enable_t *pTxenable, rtk_enable_t *pRxenable); + +/* Function Name: + * rtk_mirror_isolationLeaky_set + * Description: + * Set mirror Isolation leaky. + * Input: + * txenable -TX leaky enable. + * rxenable - RX leaky enable. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid enable input + * Note: + * The API is to set mirror VLAN leaky function forwarding packets to miror port. + */ +extern rtk_api_ret_t rtk_mirror_isolationLeaky_set(rtk_enable_t txenable, rtk_enable_t rxenable); + +/* Function Name: + * rtk_mirror_isolationLeaky_get + * Description: + * Get mirror isolation leaky. + * Input: + * None + * Output: + * pTxenable - TX leaky enable. + * pRxenable - RX leaky enable. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API is to get mirror isolation leaky status. + */ +extern rtk_api_ret_t rtk_mirror_isolationLeaky_get(rtk_enable_t *pTxenable, rtk_enable_t *pRxenable); + +/* Function Name: + * rtk_mirror_keep_set + * Description: + * Set mirror packet format keep. + * Input: + * mode - -mirror keep mode. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid enable input + * Note: + * The API is to set -mirror keep mode. + * The mirror keep mode is as following: + * - MIRROR_FOLLOW_VLAN + * - MIRROR_KEEP_ORIGINAL + * - MIRROR_KEEP_END + */ +extern rtk_api_ret_t rtk_mirror_keep_set(rtk_mirror_keep_t mode); + + +/* Function Name: + * rtk_mirror_keep_get + * Description: + * Get mirror packet format keep. + * Input: + * None + * Output: + * pMode -mirror keep mode. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API is to get mirror keep mode. + * The mirror keep mode is as following: + * - MIRROR_FOLLOW_VLAN + * - MIRROR_KEEP_ORIGINAL + * - MIRROR_KEEP_END + */ +extern rtk_api_ret_t rtk_mirror_keep_get(rtk_mirror_keep_t *pMode); + +/* Function Name: + * rtk_mirror_override_set + * Description: + * Set port mirror override function. + * Input: + * rxMirror - 1: output mirrored packet, 0: output normal forward packet + * txMirror - 1: output mirrored packet, 0: output normal forward packet + * aclMirror - 1: output mirrored packet, 0: output normal forward packet + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API is to set mirror override function. + * This function control the output format when a port output + * normal forward & mirrored packet at the same time. + */ +extern rtk_api_ret_t rtk_mirror_override_set(rtk_enable_t rxMirror, rtk_enable_t txMirror, rtk_enable_t aclMirror); + +/* Function Name: + * rtk_mirror_override_get + * Description: + * Get port mirror override function. + * Input: + * None + * Output: + * pRxMirror - 1: output mirrored packet, 0: output normal forward packet + * pTxMirror - 1: output mirrored packet, 0: output normal forward packet + * pAclMirror - 1: output mirrored packet, 0: output normal forward packet + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Null Pointer + * Note: + * The API is to Get mirror override function. + * This function control the output format when a port output + * normal forward & mirrored packet at the same time. + */ +extern rtk_api_ret_t rtk_mirror_override_get(rtk_enable_t *pRxMirror, rtk_enable_t *pTxMirror, rtk_enable_t *pAclMirror); + +#endif /* __RTK_API_MIRROR_H__ */ + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/oam.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/oam.c new file mode 100644 index 00000000..3bc73b2f --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/oam.c @@ -0,0 +1,238 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8367C + * Feature : Here is a list of all functions and variables in OAM(802.3ah) module. + * + */ + +#include +#include +#include +#include + +#include + + +/* Function Name: + * rtk_oam_init + * Description: + * Initialize oam module. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * Note: + * Must initialize oam module before calling any oam APIs. + */ +rtk_api_ret_t rtk_oam_init(void) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->oam_init) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->oam_init(); + RTK_API_UNLOCK(); + + return retVal; +} + + +/* Function Name: + * rtk_oam_state_set + * Description: + * This API set OAM state. + * Input: + * enabled -OAMstate + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error parameter + * Note: + * This API set OAM state. + */ +rtk_api_ret_t rtk_oam_state_set(rtk_enable_t enabled) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->oam_state_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->oam_state_set(enabled); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_oam_state_get + * Description: + * This API get OAM state. + * Input: + * None. + * Output: + * pEnabled - H/W IGMP state + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error parameter + * Note: + * This API set current OAM state. + */ +rtk_api_ret_t rtk_oam_state_get(rtk_enable_t *pEnabled) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->oam_state_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->oam_state_get(pEnabled); + RTK_API_UNLOCK(); + + return retVal; +} + + + +/* Function Name: + * rtk_oam_parserAction_set + * Description: + * Set OAM parser action + * Input: + * port - port id + * action - parser action + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - invalid port id + * Note: + * None + */ +rtk_api_ret_t rtk_oam_parserAction_set(rtk_port_t port, rtk_oam_parser_act_t action) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->oam_parserAction_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->oam_parserAction_set(port, action); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_oam_parserAction_set + * Description: + * Get OAM parser action + * Input: + * port - port id + * Output: + * pAction - parser action + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - invalid port id + * Note: + * None + */ +rtk_api_ret_t rtk_oam_parserAction_get(rtk_port_t port, rtk_oam_parser_act_t *pAction) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->oam_parserAction_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->oam_parserAction_get(port, pAction); + RTK_API_UNLOCK(); + + return retVal; +} + + +/* Function Name: + * rtk_oam_multiplexerAction_set + * Description: + * Set OAM multiplexer action + * Input: + * port - port id + * action - parser action + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - invalid port id + * Note: + * None + */ +rtk_api_ret_t rtk_oam_multiplexerAction_set(rtk_port_t port, rtk_oam_multiplexer_act_t action) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->oam_multiplexerAction_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->oam_multiplexerAction_set(port, action); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_oam_parserAction_set + * Description: + * Get OAM multiplexer action + * Input: + * port - port id + * Output: + * pAction - parser action + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - invalid port id + * Note: + * None + */ +rtk_api_ret_t rtk_oam_multiplexerAction_get(rtk_port_t port, rtk_oam_multiplexer_act_t *pAction) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->oam_multiplexerAction_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->oam_multiplexerAction_get(port, pAction); + RTK_API_UNLOCK(); + + return retVal; +} + + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/oam.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/oam.h new file mode 100644 index 00000000..ef22b03f --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/oam.h @@ -0,0 +1,190 @@ +/* + * Copyright (C) 2012 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTL8367/RTL8367C switch high-level API + * + * Feature : The file includes the following modules and sub-modules + * (1) OAM (802.3ah) configuration + * + */ + +#ifndef __RTK_OAM_H__ +#define __RTK_OAM_H__ + +/* + * Symbol Definition + */ + + +/* + * Data Declaration + */ + + +/* + * Macro Declaration + */ + +typedef enum rtk_oam_parser_act_e +{ + OAM_PARSER_ACTION_FORWARD = 0, + OAM_PARSER_ACTION_LOOPBACK, + OAM_PARSER_ACTION_DISCARD, + OAM_PARSER_ACTION_END, + +} rtk_oam_parser_act_t; + +typedef enum rtk_oam_multiplexer_act_e +{ + OAM_MULTIPLEXER_ACTION_FORWARD = 0, + OAM_MULTIPLEXER_ACTION_DISCARD, + OAM_MULTIPLEXER_ACTION_CPUONLY, + OAM_MULTIPLEXER_ACTION_END, + +} rtk_oam_multiplexer_act_t; + + +/* + * Function Declaration + */ + +/* Function Name: + * rtk_oam_init + * Description: + * Initialize oam module. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * Note: + * Must initialize oam module before calling any oam APIs. + */ +extern rtk_api_ret_t rtk_oam_init(void); + +/* Function Name: + * rtk_oam_state_set + * Description: + * This API set OAM state. + * Input: + * enabled -OAMstate + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error parameter + * Note: + * This API set OAM state. + */ +extern rtk_api_ret_t rtk_oam_state_set(rtk_enable_t enabled); + +/* Function Name: + * rtk_oam_state_get + * Description: + * This API get OAM state. + * Input: + * None. + * Output: + * pEnabled - H/W IGMP state + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error parameter + * Note: + * This API set current OAM state. + */ +extern rtk_api_ret_t rtk_oam_state_get(rtk_enable_t *pEnabled); + + +/* Module Name : OAM */ + +/* Function Name: + * rtk_oam_parserAction_set + * Description: + * Set OAM parser action + * Input: + * port - port id + * action - parser action + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - invalid port id + * Note: + * None + */ +extern rtk_api_ret_t rtk_oam_parserAction_set(rtk_port_t port, rtk_oam_parser_act_t action); + +/* Function Name: + * rtk_oam_parserAction_set + * Description: + * Get OAM parser action + * Input: + * port - port id + * Output: + * pAction - parser action + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - invalid port id + * Note: + * None + */ +extern rtk_api_ret_t rtk_oam_parserAction_get(rtk_port_t port, rtk_oam_parser_act_t *pAction); + + +/* Function Name: + * rtk_oam_multiplexerAction_set + * Description: + * Set OAM multiplexer action + * Input: + * port - port id + * action - parser action + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - invalid port id + * Note: + * None + */ +extern rtk_api_ret_t rtk_oam_multiplexerAction_set(rtk_port_t port, rtk_oam_multiplexer_act_t action); + +/* Function Name: + * rtk_oam_multiplexerAction_set + * Description: + * Get OAM multiplexer action + * Input: + * port - port id + * Output: + * pAction - parser action + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - invalid port id + * Note: + * None + */ +extern rtk_api_ret_t rtk_oam_multiplexerAction_get(rtk_port_t port, rtk_oam_multiplexer_act_t *pAction); + + +#endif /* __RTK_OAM_H__ */ + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/port.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/port.c new file mode 100644 index 00000000..43953a5d --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/port.c @@ -0,0 +1,1586 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8367C + * Feature : Here is a list of all functions and variables in Port module. + * + */ + +#include +#include +#include +#include + +#include + +/* Function Name: + * rtk_port_phyAutoNegoAbility_set + * Description: + * Set ethernet PHY auto-negotiation desired ability. + * Input: + * port - port id. + * pAbility - Ability structure + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_PHY_REG_ID - Invalid PHY address + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy + * Note: + * If Full_1000 bit is set to 1, the AutoNegotiation will be automatic set to 1. While both AutoNegotiation and Full_1000 are set to 0, the PHY speed and duplex selection will + * be set as following 100F > 100H > 10F > 10H priority sequence. + */ +rtk_api_ret_t rtk_port_phyAutoNegoAbility_set(rtk_port_t port, rtk_port_phy_ability_t *pAbility) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->port_phyAutoNegoAbility_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->port_phyAutoNegoAbility_set(port, pAbility); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_port_phyAutoNegoAbility_get + * Description: + * Get PHY ability through PHY registers. + * Input: + * port - Port id. + * Output: + * pAbility - Ability structure + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_PHY_REG_ID - Invalid PHY address + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy + * Note: + * Get the capablity of specified PHY. + */ +rtk_api_ret_t rtk_port_phyAutoNegoAbility_get(rtk_port_t port, rtk_port_phy_ability_t *pAbility) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->port_phyAutoNegoAbility_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->port_phyAutoNegoAbility_get(port, pAbility); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_port_phyForceModeAbility_set + * Description: + * Set the port speed/duplex mode/pause/asy_pause in the PHY force mode. + * Input: + * port - port id. + * pAbility - Ability structure + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_PHY_REG_ID - Invalid PHY address + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy + * Note: + * While both AutoNegotiation and Full_1000 are set to 0, the PHY speed and duplex selection will + * be set as following 100F > 100H > 10F > 10H priority sequence. + * This API can be used to configure combo port in fiber mode. + * The possible parameters in fiber mode are Full_1000 and Full 100. + * All the other fields in rtk_port_phy_ability_t will be ignored in fiber port. + */ +rtk_api_ret_t rtk_port_phyForceModeAbility_set(rtk_port_t port, rtk_port_phy_ability_t *pAbility) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->port_phyForceModeAbility_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->port_phyForceModeAbility_set(port, pAbility); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_port_phyForceModeAbility_get + * Description: + * Get PHY ability through PHY registers. + * Input: + * port - Port id. + * Output: + * pAbility - Ability structure + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_PHY_REG_ID - Invalid PHY address + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy + * Note: + * Get the capablity of specified PHY. + */ +rtk_api_ret_t rtk_port_phyForceModeAbility_get(rtk_port_t port, rtk_port_phy_ability_t *pAbility) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->port_phyForceModeAbility_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->port_phyForceModeAbility_get(port, pAbility); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_port_phyStatus_get + * Description: + * Get ethernet PHY linking status + * Input: + * port - Port id. + * Output: + * linkStatus - PHY link status + * speed - PHY link speed + * duplex - PHY duplex mode + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_PHY_REG_ID - Invalid PHY address + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy + * Note: + * API will return auto negotiation status of phy. + */ +rtk_api_ret_t rtk_port_phyStatus_get(rtk_port_t port, rtk_port_linkStatus_t *pLinkStatus, rtk_port_speed_t *pSpeed, rtk_port_duplex_t *pDuplex) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->port_phyStatus_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->port_phyStatus_get(port, pLinkStatus, pSpeed, pDuplex); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_port_macForceLink_set + * Description: + * Set port force linking configuration. + * Input: + * port - port id. + * pPortability - port ability configuration + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can set Port/MAC force mode properties. + */ +rtk_api_ret_t rtk_port_macForceLink_set(rtk_port_t port, rtk_port_mac_ability_t *pPortability) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->port_macForceLink_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->port_macForceLink_set(port, pPortability); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_port_macForceLink_get + * Description: + * Get port force linking configuration. + * Input: + * port - Port id. + * Output: + * pPortability - port ability configuration + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can get Port/MAC force mode properties. + */ +rtk_api_ret_t rtk_port_macForceLink_get(rtk_port_t port, rtk_port_mac_ability_t *pPortability) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->port_macForceLink_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->port_macForceLink_get(port, pPortability); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_port_macForceLinkExt_set + * Description: + * Set external interface force linking configuration. + * Input: + * port - external port ID + * mode - external interface mode + * pPortability - port ability configuration + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can set external interface force mode properties. + * The external interface can be set to: + * - MODE_EXT_DISABLE, + * - MODE_EXT_RGMII, + * - MODE_EXT_MII_MAC, + * - MODE_EXT_MII_PHY, + * - MODE_EXT_TMII_MAC, + * - MODE_EXT_TMII_PHY, + * - MODE_EXT_GMII, + * - MODE_EXT_RMII_MAC, + * - MODE_EXT_RMII_PHY, + * - MODE_EXT_SGMII, + * - MODE_EXT_HSGMII, + * - MODE_EXT_1000X_100FX, + * - MODE_EXT_1000X, + * - MODE_EXT_100FX, + */ +rtk_api_ret_t rtk_port_macForceLinkExt_set(rtk_port_t port, rtk_mode_ext_t mode, rtk_port_mac_ability_t *pPortability) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->port_macForceLinkExt_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->port_macForceLinkExt_set(port, mode, pPortability); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_port_macForceLinkExt_get + * Description: + * Set external interface force linking configuration. + * Input: + * port - external port ID + * Output: + * pMode - external interface mode + * pPortability - port ability configuration + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can get external interface force mode properties. + */ +rtk_api_ret_t rtk_port_macForceLinkExt_get(rtk_port_t port, rtk_mode_ext_t *pMode, rtk_port_mac_ability_t *pPortability) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->port_macForceLinkExt_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->port_macForceLinkExt_get(port, pMode, pPortability); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_port_macStatus_get + * Description: + * Get port link status. + * Input: + * port - Port id. + * Output: + * pPortstatus - port ability configuration + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can get Port/PHY properties. + */ +rtk_api_ret_t rtk_port_macStatus_get(rtk_port_t port, rtk_port_mac_ability_t *pPortstatus) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->port_macStatus_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->port_macStatus_get(port, pPortstatus); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_port_macLocalLoopbackEnable_set + * Description: + * Set Port Local Loopback. (Redirect TX to RX.) + * Input: + * port - Port id. + * enable - Loopback state, 0:disable, 1:enable + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can enable/disable Local loopback in MAC. + * For UTP port, This API will also enable the digital + * loopback bit in PHY register for sync of speed between + * PHY and MAC. For EXT port, users need to force the + * link state by themself. + */ +rtk_api_ret_t rtk_port_macLocalLoopbackEnable_set(rtk_port_t port, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->port_macLocalLoopbackEnable_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->port_macLocalLoopbackEnable_set(port, enable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_port_macLocalLoopbackEnable_get + * Description: + * Get Port Local Loopback. (Redirect TX to RX.) + * Input: + * port - Port id. + * Output: + * pEnable - Loopback state, 0:disable, 1:enable + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * None. + */ +rtk_api_ret_t rtk_port_macLocalLoopbackEnable_get(rtk_port_t port, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->port_macLocalLoopbackEnable_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->port_macLocalLoopbackEnable_get(port, pEnable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_port_phyReg_set + * Description: + * Set PHY register data of the specific port. + * Input: + * port - port id. + * reg - Register id + * regData - Register data + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_PHY_REG_ID - Invalid PHY address + * RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy + * Note: + * This API can set PHY register data of the specific port. + */ +rtk_api_ret_t rtk_port_phyReg_set(rtk_port_t port, rtk_port_phy_reg_t reg, rtk_port_phy_data_t regData) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->port_phyReg_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->port_phyReg_set(port, reg, regData); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_port_phyReg_get + * Description: + * Get PHY register data of the specific port. + * Input: + * port - Port id. + * reg - Register id + * Output: + * pData - Register data + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_PHY_REG_ID - Invalid PHY address + * RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy + * Note: + * This API can get PHY register data of the specific port. + */ +rtk_api_ret_t rtk_port_phyReg_get(rtk_port_t port, rtk_port_phy_reg_t reg, rtk_port_phy_data_t *pData) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->port_phyReg_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->port_phyReg_get(port, reg, pData); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_port_phyOCPReg_set + * Description: + * Set PHY OCP register + * Input: + * port - PHY ID + * ocpAddr - OCP register address + * ocpData - OCP Data. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_BUSYWAIT_TIMEOUT - Timeout + * Note: + * None. + */ +rtk_api_ret_t rtk_port_phyOCPReg_set(rtk_port_t port, rtk_uint32 ocpAddr, rtk_uint32 ocpData) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->port_phyReg_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->port_phyOCPReg_set(port, ocpAddr, ocpData); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_port_phyOCPReg_get + * Description: + * Set PHY OCP register + * Input: + * phyNo - PHY ID + * ocpAddr - OCP register address + * Output: + * pRegData - OCP data. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * None. + */ +rtk_api_ret_t rtk_port_phyOCPReg_get(rtk_port_t port, rtk_uint32 ocpAddr, rtk_uint32 *pRegData) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->port_phyReg_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->port_phyOCPReg_get(port, ocpAddr, pRegData); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_port_backpressureEnable_set + * Description: + * Set the half duplex backpressure enable status of the specific port. + * Input: + * port - port id. + * enable - Back pressure status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * This API can set the half duplex backpressure enable status of the specific port. + * The half duplex backpressure enable status of the port is as following: + * - DISABLE(Defer) + * - ENABLE (Backpressure) + */ +rtk_api_ret_t rtk_port_backpressureEnable_set(rtk_port_t port, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->port_backpressureEnable_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->port_backpressureEnable_set(port, enable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_port_backpressureEnable_get + * Description: + * Get the half duplex backpressure enable status of the specific port. + * Input: + * port - Port id. + * Output: + * pEnable - Back pressure status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can get the half duplex backpressure enable status of the specific port. + * The half duplex backpressure enable status of the port is as following: + * - DISABLE(Defer) + * - ENABLE (Backpressure) + */ +rtk_api_ret_t rtk_port_backpressureEnable_get(rtk_port_t port, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->port_backpressureEnable_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->port_backpressureEnable_get(port, pEnable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_port_adminEnable_set + * Description: + * Set port admin configuration of the specific port. + * Input: + * port - port id. + * enable - Back pressure status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * This API can set port admin configuration of the specific port. + * The port admin configuration of the port is as following: + * - DISABLE + * - ENABLE + */ +rtk_api_ret_t rtk_port_adminEnable_set(rtk_port_t port, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->port_adminEnable_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->port_adminEnable_set(port, enable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_port_adminEnable_get + * Description: + * Get port admin configurationof the specific port. + * Input: + * port - Port id. + * Output: + * pEnable - Back pressure status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can get port admin configuration of the specific port. + * The port admin configuration of the port is as following: + * - DISABLE + * - ENABLE + */ +rtk_api_ret_t rtk_port_adminEnable_get(rtk_port_t port, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->port_adminEnable_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->port_adminEnable_get(port, pEnable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_port_isolation_set + * Description: + * Set permitted port isolation portmask + * Input: + * port - port id. + * pPortmask - Permit port mask + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_PORT_MASK - Invalid portmask. + * Note: + * This API set the port mask that a port can trasmit packet to of each port + * A port can only transmit packet to ports included in permitted portmask + */ +rtk_api_ret_t rtk_port_isolation_set(rtk_port_t port, rtk_portmask_t *pPortmask) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->port_isolation_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->port_isolation_set(port, pPortmask); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_port_isolation_get + * Description: + * Get permitted port isolation portmask + * Input: + * port - Port id. + * Output: + * pPortmask - Permit port mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API get the port mask that a port can trasmit packet to of each port + * A port can only transmit packet to ports included in permitted portmask + */ +rtk_api_ret_t rtk_port_isolation_get(rtk_port_t port, rtk_portmask_t *pPortmask) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->port_isolation_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->port_isolation_get(port, pPortmask); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_port_rgmiiDelayExt_set + * Description: + * Set RGMII interface delay value for TX and RX. + * Input: + * txDelay - TX delay value, 1 for delay 2ns and 0 for no-delay + * rxDelay - RX delay value, 0~7 for delay setup. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can set external interface 2 RGMII delay. + * In TX delay, there are 2 selection: no-delay and 2ns delay. + * In RX dekay, there are 8 steps for delay tunning. 0 for no-delay, and 7 for maximum delay. + * Note. This API should be called before rtk_port_macForceLinkExt_set(). + */ +rtk_api_ret_t rtk_port_rgmiiDelayExt_set(rtk_port_t port, rtk_data_t txDelay, rtk_data_t rxDelay) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->port_rgmiiDelayExt_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->port_rgmiiDelayExt_set(port, txDelay, rxDelay); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_port_rgmiiDelayExt_get + * Description: + * Get RGMII interface delay value for TX and RX. + * Input: + * None + * Output: + * pTxDelay - TX delay value + * pRxDelay - RX delay value + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can set external interface 2 RGMII delay. + * In TX delay, there are 2 selection: no-delay and 2ns delay. + * In RX dekay, there are 8 steps for delay tunning. 0 for n0-delay, and 7 for maximum delay. + */ +rtk_api_ret_t rtk_port_rgmiiDelayExt_get(rtk_port_t port, rtk_data_t *pTxDelay, rtk_data_t *pRxDelay) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->port_rgmiiDelayExt_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->port_rgmiiDelayExt_get(port, pTxDelay, pRxDelay); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_port_phyEnableAll_set + * Description: + * Set all PHY enable status. + * Input: + * enable - PHY Enable State. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * This API can set all PHY status. + * The configuration of all PHY is as following: + * - DISABLE + * - ENABLE + */ +rtk_api_ret_t rtk_port_phyEnableAll_set(rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->port_phyEnableAll_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->port_phyEnableAll_set(enable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_port_phyEnableAll_get + * Description: + * Get all PHY enable status. + * Input: + * None + * Output: + * pEnable - PHY Enable State. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API can set all PHY status. + * The configuration of all PHY is as following: + * - DISABLE + * - ENABLE + */ +rtk_api_ret_t rtk_port_phyEnableAll_get(rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->port_phyEnableAll_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->port_phyEnableAll_get(pEnable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_port_efid_set + * Description: + * Set port-based enhanced filtering database + * Input: + * port - Port id. + * efid - Specified enhanced filtering database. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_FID - Invalid fid. + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API can set port-based enhanced filtering database. + */ +rtk_api_ret_t rtk_port_efid_set(rtk_port_t port, rtk_data_t efid) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->port_efid_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->port_efid_set(port, efid); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_port_efid_get + * Description: + * Get port-based enhanced filtering database + * Input: + * port - Port id. + * Output: + * pEfid - Specified enhanced filtering database. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API can get port-based enhanced filtering database status. + */ +rtk_api_ret_t rtk_port_efid_get(rtk_port_t port, rtk_data_t *pEfid) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->port_efid_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->port_efid_get(port, pEfid); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_port_phyComboPortMedia_set + * Description: + * Set Combo port media type + * Input: + * port - Port id. + * media - Media (COPPER or FIBER or AUTO) + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API can Set Combo port media type. + */ +rtk_api_ret_t rtk_port_phyComboPortMedia_set(rtk_port_t port, rtk_port_media_t media) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->port_phyComboPortMedia_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->port_phyComboPortMedia_set(port, media); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_port_phyComboPortMedia_get + * Description: + * Get Combo port media type + * Input: + * port - Port id. + * Output: + * pMedia - Media (COPPER or FIBER or AUTO) + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API can Set Combo port media type. + */ +rtk_api_ret_t rtk_port_phyComboPortMedia_get(rtk_port_t port, rtk_port_media_t *pMedia) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->port_phyComboPortMedia_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->port_phyComboPortMedia_get(port, pMedia); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_port_rtctEnable_set + * Description: + * Enable RTCT test + * Input: + * pPortmask - Port mask of RTCT enabled port + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Invalid port mask. + * Note: + * The API can enable RTCT Test + */ +rtk_api_ret_t rtk_port_rtctEnable_set(rtk_portmask_t *pPortmask) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->port_rtctEnable_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->port_rtctEnable_set(pPortmask); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_port_rtctDisable_set + * Description: + * Disable RTCT test + * Input: + * pPortmask - Port mask of RTCT disabled port + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Invalid port mask. + * Note: + * The API can disable RTCT Test + */ +rtk_api_ret_t rtk_port_rtctDisable_set(rtk_portmask_t *pPortmask) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->port_rtctDisable_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->port_rtctDisable_set(pPortmask); + RTK_API_UNLOCK(); + + return retVal; +} + + +/* Function Name: + * rtk_port_rtctResult_get + * Description: + * Get the result of RTCT test + * Input: + * port - Port ID + * Output: + * pRtctResult - The result of RTCT result + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port ID. + * RT_ERR_PHY_RTCT_NOT_FINISH - Testing does not finish. + * Note: + * The API can get RTCT test result. + * RTCT test may takes 4.8 seconds to finish its test at most. + * Thus, if this API return RT_ERR_PHY_RTCT_NOT_FINISH or + * other error code, the result can not be referenced and + * user should call this API again until this API returns + * a RT_ERR_OK. + * The result is stored at pRtctResult->ge_result + * pRtctResult->linkType is unused. + * The unit of channel length is 2.5cm. Ex. 300 means 300 * 2.5 = 750cm = 7.5M + */ +rtk_api_ret_t rtk_port_rtctResult_get(rtk_port_t port, rtk_rtctResult_t *pRtctResult) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->port_rtctResult_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->port_rtctResult_get(port, pRtctResult); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_port_sds_reset + * Description: + * Reset Serdes + * Input: + * port - Port ID + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API can reset Serdes + */ +rtk_api_ret_t rtk_port_sds_reset(rtk_port_t port) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->port_sds_reset) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->port_sds_reset(port); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_port_sgmiiLinkStatus_get + * Description: + * Get SGMII status + * Input: + * port - Port ID + * Output: + * pSignalDetect - Signal detect + * pSync - Sync + * pLink - Link + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API can reset Serdes + */ +rtk_api_ret_t rtk_port_sgmiiLinkStatus_get(rtk_port_t port, rtk_data_t *pSignalDetect, rtk_data_t *pSync, rtk_port_linkStatus_t *pLink) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->port_sgmiiLinkStatus_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->port_sgmiiLinkStatus_get(port, pSignalDetect, pSync, pLink); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_port_sgmiiNway_set + * Description: + * Configure SGMII/HSGMII port Nway state + * Input: + * port - Port ID + * state - Nway state + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API configure SGMII/HSGMII port Nway state + */ +rtk_api_ret_t rtk_port_sgmiiNway_set(rtk_port_t port, rtk_enable_t state) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->port_sgmiiNway_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->port_sgmiiNway_set(port, state); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_port_sgmiiNway_get + * Description: + * Get SGMII/HSGMII port Nway state + * Input: + * port - Port ID + * Output: + * pState - Nway state + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API can get SGMII/HSGMII port Nway state + */ +rtk_api_ret_t rtk_port_sgmiiNway_get(rtk_port_t port, rtk_enable_t *pState) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->port_sgmiiNway_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->port_sgmiiNway_get(port, pState); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_port_fiberAbilityExt_set + * Description: + * Get SGMII/HSGMII port Nway state + * Input: + * port - Port ID + * pause -pause state + * asypause -asypause state + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API can get SGMII/HSGMII port Nway state + */ +rtk_api_ret_t rtk_port_fiberAbilityExt_set(rtk_port_t port, rtk_uint32 pause, rtk_uint32 asypause) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->port_fiberAbilityExt_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->port_fiberAbilityExt_set(port, pause, asypause); + RTK_API_UNLOCK(); + + return retVal; +} + + +/* Function Name: + * rtk_port_fiberAbilityExt_get + * Description: + * Get SGMII/HSGMII port Nway state + * Input: + * port - Port ID + * Output: + * pPause -pause state + * pAsypause -asypause state + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API can get SGMII/HSGMII port Nway state + */ +rtk_api_ret_t rtk_port_fiberAbilityExt_get(rtk_port_t port, rtk_uint32* pPause, rtk_uint32* pAsypause) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->port_fiberAbilityExt_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->port_fiberAbilityExt_get(port, pPause, pAsypause); + RTK_API_UNLOCK(); + + return retVal; +} + + +/* Function Name: + * rtk_port_autoDos_set + * Description: + * Set Auto Dos state + * Input: + * type - Auto DoS type + * state - 1: Eanble(Drop), 0: Disable(Forward) + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set Auto Dos state + */ +rtk_api_ret_t rtk_port_autoDos_set(rtk_port_autoDosType_t type, rtk_enable_t state) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->port_autoDos_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->port_autoDos_set(type, state); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_port_autoDos_get + * Description: + * Get Auto Dos state + * Input: + * type - Auto DoS type + * Output: + * pState - 1: Eanble(Drop), 0: Disable(Forward) + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Null Pointer + * Note: + * The API can get Auto Dos state + */ +rtk_api_ret_t rtk_port_autoDos_get(rtk_port_autoDosType_t type, rtk_enable_t *pState) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->port_autoDos_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->port_autoDos_get(type, pState); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_port_fiberAbility_set + * Description: + * Configure fiber port ability + * Input: + * port - Port ID + * pAbility - Fiber port ability + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API can configure fiber port ability + */ +rtk_api_ret_t rtk_port_fiberAbility_set(rtk_port_t port, rtk_port_fiber_ability_t *pAbility) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->port_fiberAbility_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->port_fiberAbility_set(port, pAbility); + RTK_API_UNLOCK(); + + return retVal; +} + + +/* Function Name: + * rtk_port_fiberAbility_get + * Description: + * Get fiber port ability + * Input: + * port - Port ID + * Output: + * pAbility - Fiber port ability + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API can get fiber port ability + */ +rtk_api_ret_t rtk_port_fiberAbility_get(rtk_port_t port, rtk_port_fiber_ability_t *pAbility) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->port_fiberAbility_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->port_fiberAbility_get(port, pAbility); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_port_phyMdx_set + * Description: + * Set PHY MDI/MDIX state + * Input: + * port - port ID + * mode - PHY MDI/MDIX mode + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set PHY MDI/MDIX state + */ +rtk_api_ret_t rtk_port_phyMdx_set(rtk_port_t port, rtk_port_phy_mdix_mode_t mode) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->port_phyMdx_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->port_phyMdx_set(port, mode); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_port_phyMdx_get + * Description: + * Get PHY MDI/MDIX state + * Input: + * port - port ID + * Output: + * pMode - PHY MDI/MDIX mode + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can get PHY MDI/MDIX state + */ +rtk_api_ret_t rtk_port_phyMdx_get(rtk_port_t port, rtk_port_phy_mdix_mode_t *pMode) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->port_phyMdx_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->port_phyMdx_get(port, pMode); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_port_phyMdxStatus_get + * Description: + * Get PHY MDI/MDIX status + * Input: + * port - port ID + * Output: + * pStatus - PHY MDI/MDIX status + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can get PHY MDI/MDIX status + */ +rtk_api_ret_t rtk_port_phyMdxStatus_get(rtk_port_t port, rtk_port_phy_mdix_status_t *pStatus) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->port_phyMdxStatus_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->port_phyMdxStatus_get(port, pStatus); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_port_phyTestMode_set + * Description: + * Set PHY in test mode. + * Input: + * port - port id. + * mode - PHY test mode 0:normal 1:test mode 1 2:test mode 2 3: test mode 3 4:test mode 4 5~7:reserved + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy + * RT_ERR_NOT_ALLOWED - The Setting is not allowed, caused by set more than 1 port in Test mode. + * Note: + * Set PHY in test mode and only one PHY can be in test mode at the same time. + * It means API will return FAILED if other PHY is in test mode. + * This API only provide test mode 1 & 4 setup. + */ +rtk_api_ret_t rtk_port_phyTestMode_set(rtk_port_t port, rtk_port_phy_test_mode_t mode) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->port_phyTestMode_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->port_phyTestMode_set(port, mode); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_port_phyTestMode_get + * Description: + * Get PHY in which test mode. + * Input: + * port - Port id. + * Output: + * mode - PHY test mode 0:normal 1:test mode 1 2:test mode 2 3: test mode 3 4:test mode 4 5~7:reserved + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy + * Note: + * Get test mode of PHY from register setting 9.15 to 9.13. + */ +rtk_api_ret_t rtk_port_phyTestMode_get(rtk_port_t port, rtk_port_phy_test_mode_t *pMode) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->port_phyTestMode_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->port_phyTestMode_get(port, pMode); + RTK_API_UNLOCK(); + + return retVal; +} diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/port.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/port.h new file mode 100644 index 00000000..63c3f8d5 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/port.h @@ -0,0 +1,1231 @@ + /* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8367/RTL8367C switch high-level API + * + * Feature : The file includes port module high-layer API defination + * + */ + +#ifndef __RTK_API_PORT_H__ +#define __RTK_API_PORT_H__ + +/* + * Data Type Declaration + */ +#define PHY_CONTROL_REG 0 +#define PHY_STATUS_REG 1 +#define PHY_AN_ADVERTISEMENT_REG 4 +#define PHY_AN_LINKPARTNER_REG 5 +#define PHY_1000_BASET_CONTROL_REG 9 +#define PHY_1000_BASET_STATUS_REG 10 +#define PHY_RESOLVED_REG 26 + +#define RTK_EFID_MAX 0x7 + +#define RTK_FIBER_FORCE_1000M 3 +#define RTK_FIBER_FORCE_100M 5 +#define RTK_FIBER_FORCE_100M1000M 7 + +typedef enum rtk_mode_ext_e +{ + MODE_EXT_DISABLE = 0, + MODE_EXT_RGMII, + MODE_EXT_MII_MAC, + MODE_EXT_MII_PHY, + MODE_EXT_TMII_MAC, + MODE_EXT_TMII_PHY, + MODE_EXT_GMII, + MODE_EXT_RMII_MAC, + MODE_EXT_RMII_PHY, + MODE_EXT_SGMII, + MODE_EXT_HSGMII, + MODE_EXT_1000X_100FX, + MODE_EXT_1000X, + MODE_EXT_100FX, + MODE_EXT_RGMII_2, + MODE_EXT_MII_MAC_2, + MODE_EXT_MII_PHY_2, + MODE_EXT_TMII_MAC_2, + MODE_EXT_TMII_PHY_2, + MODE_EXT_RMII_MAC_2, + MODE_EXT_RMII_PHY_2, + MODE_EXT_FIBER_2P5G, + MODE_EXT_END +} rtk_mode_ext_t; + +typedef enum rtk_port_duplex_e +{ + PORT_HALF_DUPLEX = 0, + PORT_FULL_DUPLEX, + PORT_DUPLEX_END +} rtk_port_duplex_t; + +typedef enum rtk_port_macMode_e +{ + PORT_MAC_NORMAL = 0, + PORT_MAC_FORCE, + PORT_MAC_END +}rtk_port_macMode_t; + +typedef enum rtk_port_linkStatus_e +{ + PORT_LINKDOWN = 0, + PORT_LINKUP, + PORT_LINKSTATUS_END +} rtk_port_linkStatus_t; + +typedef struct rtk_port_mac_ability_s +{ + rtk_uint32 forcemode; + rtk_uint32 speed; + rtk_uint32 duplex; + rtk_uint32 link; + rtk_uint32 nway; + rtk_uint32 txpause; + rtk_uint32 rxpause; +}rtk_port_mac_ability_t; + +typedef struct rtk_port_phy_ability_s +{ + rtk_uint32 AutoNegotiation; /*PHY register 0.12 setting for auto-negotiation process*/ + rtk_uint32 Half_10; /*PHY register 4.5 setting for 10BASE-TX half duplex capable*/ + rtk_uint32 Full_10; /*PHY register 4.6 setting for 10BASE-TX full duplex capable*/ + rtk_uint32 Half_100; /*PHY register 4.7 setting for 100BASE-TX half duplex capable*/ + rtk_uint32 Full_100; /*PHY register 4.8 setting for 100BASE-TX full duplex capable*/ + rtk_uint32 Full_1000; /*PHY register 9.9 setting for 1000BASE-T full duplex capable*/ + rtk_uint32 FC; /*PHY register 4.10 setting for flow control capability*/ + rtk_uint32 AsyFC; /*PHY register 4.11 setting for asymmetric flow control capability*/ +} rtk_port_phy_ability_t; + +typedef struct rtk_port_fiber_ability_s +{ + rtk_uint32 AutoNegotiation; + rtk_uint32 Full_100; + rtk_uint32 Full_1000; + rtk_uint32 Full_2P5G; + rtk_uint32 FC; + rtk_uint32 AsyFC; +} rtk_port_fiber_ability_t; + +typedef rtk_uint32 rtk_port_phy_data_t; /* phy page */ +typedef rtk_uint32 rtk_port_phy_page_t; /* phy page */ + +typedef enum rtk_port_phy_reg_e +{ + PHY_REG_CONTROL = 0, + PHY_REG_STATUS, + PHY_REG_IDENTIFIER_1, + PHY_REG_IDENTIFIER_2, + PHY_REG_AN_ADVERTISEMENT, + PHY_REG_AN_LINKPARTNER, + PHY_REG_1000_BASET_CONTROL = 9, + PHY_REG_1000_BASET_STATUS, + PHY_REG_END = 32 +} rtk_port_phy_reg_t; + +typedef enum rtk_port_speed_e +{ + PORT_SPEED_10M = 0, + PORT_SPEED_100M, + PORT_SPEED_1000M, + PORT_SPEED_500M, + PORT_SPEED_2500M, + PORT_SPEED_END +} rtk_port_speed_t; + +typedef enum rtk_port_media_e +{ + PORT_MEDIA_COPPER = 0, + PORT_MEDIA_FIBER, + PORT_MEDIA_AUTO, + PORT_MEDIA_RGMII, + PORT_MEDIA_END +}rtk_port_media_t; + +typedef struct rtk_rtctResult_s +{ + rtk_port_speed_t linkType; + union + { + struct fe_result_s + { + rtk_uint32 isRxShort; + rtk_uint32 isTxShort; + rtk_uint32 isRxOpen; + rtk_uint32 isTxOpen; + rtk_uint32 isRxMismatch; + rtk_uint32 isTxMismatch; + rtk_uint32 isRxLinedriver; + rtk_uint32 isTxLinedriver; + rtk_uint32 rxLen; + rtk_uint32 txLen; + } fe_result; + + struct ge_result_s + { + rtk_uint32 channelAShort; + rtk_uint32 channelBShort; + rtk_uint32 channelCShort; + rtk_uint32 channelDShort; + + rtk_uint32 channelAOpen; + rtk_uint32 channelBOpen; + rtk_uint32 channelCOpen; + rtk_uint32 channelDOpen; + + rtk_uint32 channelAMismatch; + rtk_uint32 channelBMismatch; + rtk_uint32 channelCMismatch; + rtk_uint32 channelDMismatch; + + rtk_uint32 channelALinedriver; + rtk_uint32 channelBLinedriver; + rtk_uint32 channelCLinedriver; + rtk_uint32 channelDLinedriver; + + rtk_uint32 channelALen; + rtk_uint32 channelBLen; + rtk_uint32 channelCLen; + rtk_uint32 channelDLen; + } ge_result; + }result; +} rtk_rtctResult_t; + +typedef enum rtk_port_autoDosType_e +{ + AUTODOS_DAEQSA = 0, + AUTODOS_LANDATTACKS, + AUTODOS_BLATATTACKS, + AUTODOS_SYNFINSCAN, + AUTODOS_XMASCAN, + AUTODOS_NULLSCAN, + AUTODOS_SYN1024, + AUTODOS_TCPSHORTHDR, + AUTODOS_TCPFRAGERROR, + AUTODOS_ICMPFRAGMENT, + AUTODOS_END, + +} rtk_port_autoDosType_t; + +typedef enum rtk_port_phy_mdix_mode_e +{ + PHY_AUTO_CROSSOVER_MODE= 0, + PHY_FORCE_MDI_MODE, + PHY_FORCE_MDIX_MODE, + PHY_FORCE_MODE_END +} rtk_port_phy_mdix_mode_t; + +typedef enum rtk_port_phy_mdix_status_e +{ + PHY_STATUS_AUTO_MDI_MODE= 0, + PHY_STATUS_AUTO_MDIX_MODE, + PHY_STATUS_FORCE_MDI_MODE, + PHY_STATUS_FORCE_MDIX_MODE, + PHY_STATUS_FORCE_MODE_END +} rtk_port_phy_mdix_status_t; + +typedef enum rtk_port_phy_test_mode_e +{ + PHY_TEST_MODE_NORMAL= 0, + PHY_TEST_MODE_1, + PHY_TEST_MODE_2, + PHY_TEST_MODE_3, + PHY_TEST_MODE_4, + PHY_TEST_MODE_END +} rtk_port_phy_test_mode_t; + +/* Function Name: + * rtk_port_phyAutoNegoAbility_set + * Description: + * Set ethernet PHY auto-negotiation desired ability. + * Input: + * port - port id. + * pAbility - Ability structure + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_PHY_REG_ID - Invalid PHY address + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy + * Note: + * If Full_1000 bit is set to 1, the AutoNegotiation will be automatic set to 1. While both AutoNegotiation and Full_1000 are set to 0, the PHY speed and duplex selection will + * be set as following 100F > 100H > 10F > 10H priority sequence. + */ +extern rtk_api_ret_t rtk_port_phyAutoNegoAbility_set(rtk_port_t port, rtk_port_phy_ability_t *pAbility); + +/* Function Name: + * rtk_port_phyAutoNegoAbility_get + * Description: + * Get PHY ability through PHY registers. + * Input: + * port - Port id. + * Output: + * pAbility - Ability structure + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_PHY_REG_ID - Invalid PHY address + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy + * Note: + * Get the capablity of specified PHY. + */ +extern rtk_api_ret_t rtk_port_phyAutoNegoAbility_get(rtk_port_t port, rtk_port_phy_ability_t *pAbility); + +/* Function Name: + * rtk_port_phyForceModeAbility_set + * Description: + * Set the port speed/duplex mode/pause/asy_pause in the PHY force mode. + * Input: + * port - port id. + * pAbility - Ability structure + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_PHY_REG_ID - Invalid PHY address + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy + * Note: + * While both AutoNegotiation and Full_1000 are set to 0, the PHY speed and duplex selection will + * be set as following 100F > 100H > 10F > 10H priority sequence. + */ +extern rtk_api_ret_t rtk_port_phyForceModeAbility_set(rtk_port_t port, rtk_port_phy_ability_t *pAbility); + +/* Function Name: + * rtk_port_phyForceModeAbility_get + * Description: + * Get PHY ability through PHY registers. + * Input: + * port - Port id. + * Output: + * pAbility - Ability structure + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_PHY_REG_ID - Invalid PHY address + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy + * Note: + * Get the capablity of specified PHY. + */ +extern rtk_api_ret_t rtk_port_phyForceModeAbility_get(rtk_port_t port, rtk_port_phy_ability_t *pAbility); + +/* Function Name: + * rtk_port_phyStatus_get + * Description: + * Get ethernet PHY linking status + * Input: + * port - Port id. + * Output: + * linkStatus - PHY link status + * speed - PHY link speed + * duplex - PHY duplex mode + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_PHY_REG_ID - Invalid PHY address + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy + * Note: + * API will return auto negotiation status of phy. + */ +extern rtk_api_ret_t rtk_port_phyStatus_get(rtk_port_t port, rtk_port_linkStatus_t *pLinkStatus, rtk_port_speed_t *pSpeed, rtk_port_duplex_t *pDuplex); + +/* Function Name: + * rtk_port_macForceLink_set + * Description: + * Set port force linking configuration. + * Input: + * port - port id. + * pPortability - port ability configuration + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can set Port/MAC force mode properties. + */ +extern rtk_api_ret_t rtk_port_macForceLink_set(rtk_port_t port, rtk_port_mac_ability_t *pPortability); + +/* Function Name: + * rtk_port_macForceLink_get + * Description: + * Get port force linking configuration. + * Input: + * port - Port id. + * Output: + * pPortability - port ability configuration + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can get Port/MAC force mode properties. + */ +extern rtk_api_ret_t rtk_port_macForceLink_get(rtk_port_t port, rtk_port_mac_ability_t *pPortability); + +/* Function Name: + * rtk_port_macForceLinkExt_set + * Description: + * Set external interface force linking configuration. + * Input: + * port - external port ID + * mode - external interface mode + * pPortability - port ability configuration + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can set external interface force mode properties. + * The external interface can be set to: + * - MODE_EXT_DISABLE, + * - MODE_EXT_RGMII, + * - MODE_EXT_MII_MAC, + * - MODE_EXT_MII_PHY, + * - MODE_EXT_TMII_MAC, + * - MODE_EXT_TMII_PHY, + * - MODE_EXT_GMII, + * - MODE_EXT_RMII_MAC, + * - MODE_EXT_RMII_PHY, + * - MODE_EXT_SGMII, + * - MODE_EXT_HSGMII, + * - MODE_EXT_1000X_100FX, + * - MODE_EXT_1000X, + * - MODE_EXT_100FX, + */ +extern rtk_api_ret_t rtk_port_macForceLinkExt_set(rtk_port_t port, rtk_mode_ext_t mode, rtk_port_mac_ability_t *pPortability); + +/* Function Name: + * rtk_port_macForceLinkExt_get + * Description: + * Set external interface force linking configuration. + * Input: + * port - external port ID + * Output: + * pMode - external interface mode + * pPortability - port ability configuration + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can get external interface force mode properties. + */ +extern rtk_api_ret_t rtk_port_macForceLinkExt_get(rtk_port_t port, rtk_mode_ext_t *pMode, rtk_port_mac_ability_t *pPortability); + +/* Function Name: + * rtk_port_macStatus_get + * Description: + * Get port link status. + * Input: + * port - Port id. + * Output: + * pPortstatus - port ability configuration + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can get Port/PHY properties. + */ +extern rtk_api_ret_t rtk_port_macStatus_get(rtk_port_t port, rtk_port_mac_ability_t *pPortstatus); + +/* Function Name: + * rtk_port_macLocalLoopbackEnable_set + * Description: + * Set Port Local Loopback. (Redirect TX to RX.) + * Input: + * port - Port id. + * enable - Loopback state, 0:disable, 1:enable + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can enable/disable Local loopback in MAC. + * For UTP port, This API will also enable the digital + * loopback bit in PHY register for sync of speed between + * PHY and MAC. For EXT port, users need to force the + * link state by themself. + */ +extern rtk_api_ret_t rtk_port_macLocalLoopbackEnable_set(rtk_port_t port, rtk_enable_t enable); + +/* Function Name: + * rtk_port_macLocalLoopbackEnable_get + * Description: + * Get Port Local Loopback. (Redirect TX to RX.) + * Input: + * port - Port id. + * Output: + * pEnable - Loopback state, 0:disable, 1:enable + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * None. + */ +extern rtk_api_ret_t rtk_port_macLocalLoopbackEnable_get(rtk_port_t port, rtk_enable_t *pEnable); + +/* Function Name: + * rtk_port_phyReg_set + * Description: + * Set PHY register data of the specific port. + * Input: + * port - port id. + * reg - Register id + * regData - Register data + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_PHY_REG_ID - Invalid PHY address + * RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy + * Note: + * This API can set PHY register data of the specific port. + */ +extern rtk_api_ret_t rtk_port_phyReg_set(rtk_port_t port, rtk_port_phy_reg_t reg, rtk_port_phy_data_t value); + +/* Function Name: + * rtk_port_phyReg_get + * Description: + * Get PHY register data of the specific port. + * Input: + * port - Port id. + * reg - Register id + * Output: + * pData - Register data + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_PHY_REG_ID - Invalid PHY address + * RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy + * Note: + * This API can get PHY register data of the specific port. + */ +extern rtk_api_ret_t rtk_port_phyReg_get(rtk_port_t port, rtk_port_phy_reg_t reg, rtk_port_phy_data_t *pData); + +/* Function Name: + * rtk_port_phyOCPReg_set + * Description: + * Set PHY OCP register + * Input: + * port - PHY ID + * ocpAddr - OCP register address + * ocpData - OCP Data. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_BUSYWAIT_TIMEOUT - Timeout + * Note: + * None. + */ +extern rtk_api_ret_t rtk_port_phyOCPReg_set(rtk_port_t port, rtk_uint32 ocpAddr, rtk_uint32 ocpData); + +/* Function Name: + * rtk_port_phyOCPReg_get + * Description: + * Set PHY OCP register + * Input: + * phyNo - PHY ID + * ocpAddr - OCP register address + * Output: + * pRegData - OCP data. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * None. + */ +extern rtk_api_ret_t rtk_port_phyOCPReg_get(rtk_port_t port, rtk_uint32 ocpAddr, rtk_uint32 *pRegData); + +/* Function Name: + * rtk_port_backpressureEnable_set + * Description: + * Set the half duplex backpressure enable status of the specific port. + * Input: + * port - port id. + * enable - Back pressure status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * This API can set the half duplex backpressure enable status of the specific port. + * The half duplex backpressure enable status of the port is as following: + * - DISABLE + * - ENABLE + */ +extern rtk_api_ret_t rtk_port_backpressureEnable_set(rtk_port_t port, rtk_enable_t enable); + +/* Function Name: + * rtk_port_backpressureEnable_get + * Description: + * Get the half duplex backpressure enable status of the specific port. + * Input: + * port - Port id. + * Output: + * pEnable - Back pressure status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can get the half duplex backpressure enable status of the specific port. + * The half duplex backpressure enable status of the port is as following: + * - DISABLE + * - ENABLE + */ +extern rtk_api_ret_t rtk_port_backpressureEnable_get(rtk_port_t port, rtk_enable_t *pEnable); + +/* Function Name: + * rtk_port_adminEnable_set + * Description: + * Set port admin configuration of the specific port. + * Input: + * port - port id. + * enable - Back pressure status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * This API can set port admin configuration of the specific port. + * The port admin configuration of the port is as following: + * - DISABLE + * - ENABLE + */ +extern rtk_api_ret_t rtk_port_adminEnable_set(rtk_port_t port, rtk_enable_t enable); + +/* Function Name: + * rtk_port_adminEnable_get + * Description: + * Get port admin configurationof the specific port. + * Input: + * port - Port id. + * Output: + * pEnable - Back pressure status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can get port admin configuration of the specific port. + * The port admin configuration of the port is as following: + * - DISABLE + * - ENABLE + */ +extern rtk_api_ret_t rtk_port_adminEnable_get(rtk_port_t port, rtk_enable_t *pEnable); + +/* Function Name: + * rtk_port_isolation_set + * Description: + * Set permitted port isolation portmask + * Input: + * port - port id. + * pPortmask - Permit port mask + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_PORT_MASK - Invalid portmask. + * Note: + * This API set the port mask that a port can trasmit packet to of each port + * A port can only transmit packet to ports included in permitted portmask + */ +extern rtk_api_ret_t rtk_port_isolation_set(rtk_port_t port, rtk_portmask_t *pPortmask); + +/* Function Name: + * rtk_port_isolation_get + * Description: + * Get permitted port isolation portmask + * Input: + * port - Port id. + * Output: + * pPortmask - Permit port mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API get the port mask that a port can trasmit packet to of each port + * A port can only transmit packet to ports included in permitted portmask + */ +extern rtk_api_ret_t rtk_port_isolation_get(rtk_port_t port, rtk_portmask_t *pPortmask); + +/* Function Name: + * rtk_port_rgmiiDelayExt_set + * Description: + * Set RGMII interface delay value for TX and RX. + * Input: + * txDelay - TX delay value, 1 for delay 2ns and 0 for no-delay + * rxDelay - RX delay value, 0~7 for delay setup. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can set external interface 2 RGMII delay. + * In TX delay, there are 2 selection: no-delay and 2ns delay. + * In RX dekay, there are 8 steps for delay tunning. 0 for no-delay, and 7 for maximum delay. + * Note. This API should be called before rtk_port_macForceLinkExt_set(). + */ +extern rtk_api_ret_t rtk_port_rgmiiDelayExt_set(rtk_port_t port, rtk_data_t txDelay, rtk_data_t rxDelay); + +/* Function Name: + * rtk_port_rgmiiDelayExt_get + * Description: + * Get RGMII interface delay value for TX and RX. + * Input: + * None + * Output: + * pTxDelay - TX delay value + * pRxDelay - RX delay value + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can set external interface 2 RGMII delay. + * In TX delay, there are 2 selection: no-delay and 2ns delay. + * In RX dekay, there are 8 steps for delay tunning. 0 for n0-delay, and 7 for maximum delay. + */ +extern rtk_api_ret_t rtk_port_rgmiiDelayExt_get(rtk_port_t port, rtk_data_t *pTxDelay, rtk_data_t *pRxDelay); + +/* Function Name: + * rtk_port_phyEnableAll_set + * Description: + * Set all PHY enable status. + * Input: + * enable - PHY Enable State. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * This API can set all PHY status. + * The configuration of all PHY is as following: + * - DISABLE + * - ENABLE + */ +extern rtk_api_ret_t rtk_port_phyEnableAll_set(rtk_enable_t enable); + +/* Function Name: + * rtk_port_phyEnableAll_get + * Description: + * Get all PHY enable status. + * Input: + * None + * Output: + * pEnable - PHY Enable State. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API can set all PHY status. + * The configuration of all PHY is as following: + * - DISABLE + * - ENABLE + */ +extern rtk_api_ret_t rtk_port_phyEnableAll_get(rtk_enable_t *pEnable); + +/* Function Name: + * rtk_port_efid_set + * Description: + * Set port-based enhanced filtering database + * Input: + * port - Port id. + * efid - Specified enhanced filtering database. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_FID - Invalid fid. + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API can set port-based enhanced filtering database. + */ +extern rtk_api_ret_t rtk_port_efid_set(rtk_port_t port, rtk_data_t efid); + +/* Function Name: + * rtk_port_efid_get + * Description: + * Get port-based enhanced filtering database + * Input: + * port - Port id. + * Output: + * pEfid - Specified enhanced filtering database. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API can get port-based enhanced filtering database status. + */ +extern rtk_api_ret_t rtk_port_efid_get(rtk_port_t port, rtk_data_t *pEfid); + +/* Function Name: + * rtk_port_phyComboPortMedia_set + * Description: + * Set Combo port media type + * Input: + * port - Port id. (Should be Port 4) + * media - Media (COPPER or FIBER or AUTO) + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API can Set Combo port media type. + */ +extern rtk_api_ret_t rtk_port_phyComboPortMedia_set(rtk_port_t port, rtk_port_media_t media); + +/* Function Name: + * rtk_port_phyComboPortMedia_get + * Description: + * Get Combo port media type + * Input: + * port - Port id. (Should be Port 4) + * Output: + * pMedia - Media (COPPER or FIBER or AUTO) + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API can Set Combo port media type. + */ +extern rtk_api_ret_t rtk_port_phyComboPortMedia_get(rtk_port_t port, rtk_port_media_t *pMedia); + +/* Function Name: + * rtk_port_rtctEnable_set + * Description: + * Enable RTCT test + * Input: + * pPortmask - Port mask of RTCT enabled port + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Invalid port mask. + * Note: + * The API can enable RTCT Test + */ +extern rtk_api_ret_t rtk_port_rtctEnable_set(rtk_portmask_t *pPortmask); + +/* Function Name: + * rtk_port_rtctDisable_set + * Description: + * Disable RTCT test + * Input: + * pPortmask - Port mask of RTCT disabled port + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Invalid port mask. + * Note: + * The API can disable RTCT Test + */ +extern rtk_api_ret_t rtk_port_rtctDisable_set(rtk_portmask_t *pPortmask); + + +/* Function Name: + * rtk_port_rtctResult_get + * Description: + * Get the result of RTCT test + * Input: + * port - Port ID + * Output: + * pRtctResult - The result of RTCT result + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port ID. + * RT_ERR_PHY_RTCT_NOT_FINISH - Testing does not finish. + * Note: + * The API can get RTCT test result. + * RTCT test may takes 4.8 seconds to finish its test at most. + * Thus, if this API return RT_ERR_PHY_RTCT_NOT_FINISH or + * other error code, the result can not be referenced and + * user should call this API again until this API returns + * a RT_ERR_OK. + * The result is stored at pRtctResult->ge_result + * pRtctResult->linkType is unused. + * The unit of channel length is 2.5cm. Ex. 300 means 300 * 2.5 = 750cm = 7.5M + */ +extern rtk_api_ret_t rtk_port_rtctResult_get(rtk_port_t port, rtk_rtctResult_t *pRtctResult); + +/* Function Name: + * rtk_port_sds_reset + * Description: + * Reset Serdes + * Input: + * port - Port ID + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API can reset Serdes + */ +extern rtk_api_ret_t rtk_port_sds_reset(rtk_port_t port); + +/* Function Name: + * rtk_port_sgmiiLinkStatus_get + * Description: + * Get SGMII status + * Input: + * port - Port ID + * Output: + * pSignalDetect - Signal detect + * pSync - Sync + * pLink - Link + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API can reset Serdes + */ +extern rtk_api_ret_t rtk_port_sgmiiLinkStatus_get(rtk_port_t port, rtk_data_t *pSignalDetect, rtk_data_t *pSync, rtk_port_linkStatus_t *pLink); + +/* Function Name: + * rtk_port_sgmiiNway_set + * Description: + * Configure SGMII/HSGMII port Nway state + * Input: + * port - Port ID + * state - Nway state + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API configure SGMII/HSGMII port Nway state + */ +extern rtk_api_ret_t rtk_port_sgmiiNway_set(rtk_port_t port, rtk_enable_t state); + +/* Function Name: + * rtk_port_sgmiiNway_get + * Description: + * Get SGMII/HSGMII port Nway state + * Input: + * port - Port ID + * Output: + * pState - Nway state + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API can get SGMII/HSGMII port Nway state + */ +extern rtk_api_ret_t rtk_port_sgmiiNway_get(rtk_port_t port, rtk_enable_t *pState); + +/* Function Name: + * rtk_port_fiberAbilityExt_set + * Description: + * Get SGMII/HSGMII port Nway state + * Input: + * port - Port ID + * pause -pause state + * asypause -asypause state + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API can get SGMII/HSGMII port Nway state + */ +extern rtk_api_ret_t rtk_port_fiberAbilityExt_set(rtk_port_t port, rtk_uint32 pause, rtk_uint32 asypause); + + + +/* Function Name: + * rtk_port_fiberAbilityExt_get + * Description: + * Get SGMII/HSGMII port Nway state + * Input: + * port - Port ID + * Output: + * pPause -pause state + * pAsypause -asypause state + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API can get SGMII/HSGMII port Nway state + */ +extern rtk_api_ret_t rtk_port_fiberAbilityExt_get(rtk_port_t port, rtk_uint32* pPause, rtk_uint32* pAsypause); + +/* Function Name: + * rtk_port_autoDos_set + * Description: + * Set Auto Dos state + * Input: + * type - Auto DoS type + * state - 1: Eanble(Drop), 0: Disable(Forward) + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set Auto Dos state + */ +extern rtk_api_ret_t rtk_port_autoDos_set(rtk_port_autoDosType_t type, rtk_enable_t state); + +/* Function Name: + * rtk_port_autoDos_get + * Description: + * Get Auto Dos state + * Input: + * type - Auto DoS type + * Output: + * pState - 1: Eanble(Drop), 0: Disable(Forward) + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Null Pointer + * Note: + * The API can get Auto Dos state + */ +extern rtk_api_ret_t rtk_port_autoDos_get(rtk_port_autoDosType_t type, rtk_enable_t *pState); + +/* Function Name: + * rtk_port_fiberAbility_set + * Description: + * Configure fiber port ability + * Input: + * port - Port ID + * pAbility - Fiber port ability + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API can configure fiber port ability + */ +extern rtk_api_ret_t rtk_port_fiberAbility_set(rtk_port_t port, rtk_port_fiber_ability_t *pAbility); + + +/* Function Name: + * rtk_port_fiberAbility_get + * Description: + * Get fiber port ability + * Input: + * port - Port ID + * Output: + * pAbility - Fiber port ability + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API can get fiber port ability + */ +extern rtk_api_ret_t rtk_port_fiberAbility_get(rtk_port_t port, rtk_port_fiber_ability_t *pAbility); + +/* Function Name: + * rtk_port_phyMdx_set + * Description: + * Set PHY MDI/MDIX state + * Input: + * port - port ID + * mode - PHY MDI/MDIX mode + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set PHY MDI/MDIX state + */ +extern rtk_api_ret_t rtk_port_phyMdx_set(rtk_port_t port, rtk_port_phy_mdix_mode_t mode); + +/* Function Name: + * rtk_port_phyMdx_get + * Description: + * Get PHY MDI/MDIX state + * Input: + * port - port ID + * Output: + * pMode - PHY MDI/MDIX mode + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can get PHY MDI/MDIX state + */ +extern rtk_api_ret_t rtk_port_phyMdx_get(rtk_port_t port, rtk_port_phy_mdix_mode_t *pMode); + +/* Function Name: + * rtk_port_phyMdxStatus_get + * Description: + * Get PHY MDI/MDIX status + * Input: + * port - port ID + * Output: + * pStatus - PHY MDI/MDIX status + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can get PHY MDI/MDIX status + */ +extern rtk_api_ret_t rtk_port_phyMdxStatus_get(rtk_port_t port, rtk_port_phy_mdix_status_t *pStatus); + + /* Function Name: + * rtk_port_phyTestMode_set + * Description: + * Set PHY in test mode. + * Input: + * port - port id. + * mode - PHY test mode 0:normal 1:test mode 1 2:test mode 2 3: test mode 3 4:test mode 4 5~7:reserved + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy + * RT_ERR_NOT_ALLOWED - The Setting is not allowed, caused by set more than 1 port in Test mode. + * Note: + * Set PHY in test mode and only one PHY can be in test mode at the same time. + * It means API will return FAILED if other PHY is in test mode. + * This API only provide test mode 1 & 4 setup. + */ +extern rtk_api_ret_t rtk_port_phyTestMode_set(rtk_port_t port, rtk_port_phy_test_mode_t mode); + +/* Function Name: + * rtk_port_phyTestMode_get + * Description: + * Get PHY in which test mode. + * Input: + * port - Port id. + * Output: + * mode - PHY test mode 0:normal 1:test mode 1 2:test mode 2 3: test mode 3 4:test mode 4 5~7:reserved + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy + * Note: + * Get test mode of PHY from register setting 9.15 to 9.13. + */ +extern rtk_api_ret_t rtk_port_phyTestMode_get(rtk_port_t port, rtk_port_phy_test_mode_t *pMode); + +#endif /* __RTK_API_PORT_H__ */ + + + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/ptp.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/ptp.c new file mode 100644 index 00000000..7e96c46f --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/ptp.c @@ -0,0 +1,698 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision: 39583 $ + * $Date: 2013-05-20 16:59:23 +0800 (星期一, 20 五月 2013) $ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8367C + * Feature : Here is a list of all functions and variables in time module. + * + */ + +#include +#include +#include +#include +#include + +/* Function Name: + * rtk_ptp_init + * Description: + * PTP function initialization. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API is used to initialize PTP status. + */ +rtk_api_ret_t rtk_ptp_init(void) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->ptp_init) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->ptp_init(); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_ptp_mac_set + * Description: + * Configure PTP mac address. + * Input: + * mac - mac address to parser PTP packets. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * Note: + * None + */ +rtk_api_ret_t rtk_ptp_mac_set(rtk_mac_t mac) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->ptp_mac_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->ptp_mac_set(mac); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_ptp_mac_get + * Description: + * Get PTP mac address. + * Input: + * None + * Output: + * pMac - mac address to parser PTP packets. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * Note: + * None + */ +rtk_api_ret_t rtk_ptp_mac_get(rtk_mac_t *pMac) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->ptp_mac_get) + return RT_ERR_DRIVER_NOT_FOUND; + + + RTK_API_LOCK(); + retVal = RT_MAPPER->ptp_mac_get(pMac); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_ptp_tpid_set + * Description: + * Configure PTP accepted outer & inner tag TPID. + * Input: + * outerId - Ether type of S-tag frame parsing in PTP ports. + * innerId - Ether type of C-tag frame parsing in PTP ports. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * Note: + * None + */ +rtk_api_ret_t rtk_ptp_tpid_set(rtk_ptp_tpid_t outerId, rtk_ptp_tpid_t innerId) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->ptp_tpid_set) + return RT_ERR_DRIVER_NOT_FOUND; + + + RTK_API_LOCK(); + retVal = RT_MAPPER->ptp_tpid_set(outerId, innerId); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_ptp_tpid_get + * Description: + * Get PTP accepted outer & inner tag TPID. + * Input: + * None + * Output: + * pOuterId - Ether type of S-tag frame parsing in PTP ports. + * pInnerId - Ether type of C-tag frame parsing in PTP ports. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +rtk_api_ret_t rtk_ptp_tpid_get(rtk_ptp_tpid_t *pOuterId, rtk_ptp_tpid_t *pInnerId) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->ptp_tpid_get) + return RT_ERR_DRIVER_NOT_FOUND; + + + RTK_API_LOCK(); + retVal = RT_MAPPER->ptp_tpid_get(pOuterId, pInnerId); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_ptp_refTime_set + * Description: + * Set the reference time of the specified device. + * Input: + * timeStamp - reference timestamp value + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT - invalid input parameter + * Applicable: + * 8390, 8380 + * Note: + * None + */ +rtk_api_ret_t rtk_ptp_refTime_set(rtk_ptp_timeStamp_t timeStamp) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->ptp_refTime_set) + return RT_ERR_DRIVER_NOT_FOUND; + + + RTK_API_LOCK(); + retVal = RT_MAPPER->ptp_refTime_set(timeStamp); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_ptp_refTime_get + * Description: + * Get the reference time of the specified device. + * Input: + * Output: + * pTimeStamp - pointer buffer of the reference time + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Applicable: + * 8390, 8380 + * Note: + * None + */ +rtk_api_ret_t rtk_ptp_refTime_get(rtk_ptp_timeStamp_t *pTimeStamp) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->ptp_refTime_get) + return RT_ERR_DRIVER_NOT_FOUND; + + + RTK_API_LOCK(); + retVal = RT_MAPPER->ptp_refTime_get(pTimeStamp); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_ptp_refTimeAdjust_set + * Description: + * Adjust the reference time. + * Input: + * unit - unit id + * sign - significant + * timeStamp - reference timestamp value + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Note: + * sign=0 for positive adjustment, sign=1 for negative adjustment. + */ +rtk_api_ret_t rtk_ptp_refTimeAdjust_set(rtk_ptp_sys_adjust_t sign, rtk_ptp_timeStamp_t timeStamp) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->ptp_refTimeAdjust_set) + return RT_ERR_DRIVER_NOT_FOUND; + + + RTK_API_LOCK(); + retVal = RT_MAPPER->ptp_refTimeAdjust_set(sign, timeStamp); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_ptp_refTimeEnable_set + * Description: + * Set the enable state of reference time of the specified device. + * Input: + * enable - status + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT - invalid input parameter + * Note: + * None + */ +rtk_api_ret_t rtk_ptp_refTimeEnable_set(rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->ptp_refTimeEnable_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->ptp_refTimeEnable_set(enable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_ptp_refTimeEnable_get + * Description: + * Get the enable state of reference time of the specified device. + * Input: + * Output: + * pEnable - status + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Applicable: + * 8390, 8380 + * Note: + * None + */ +rtk_api_ret_t rtk_ptp_refTimeEnable_get(rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->ptp_refTimeEnable_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->ptp_refTimeEnable_get(pEnable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_ptp_portEnable_set + * Description: + * Set PTP status of the specified port. + * Input: + * port - port id + * enable - status + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT - invalid port id + * RT_ERR_INPUT - invalid input parameter + * Note: + * None + */ +rtk_api_ret_t rtk_ptp_portEnable_set(rtk_port_t port, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->ptp_portEnable_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->ptp_portEnable_set(port, enable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_ptp_portEnable_get + * Description: + * Get PTP status of the specified port. + * Input: + * port - port id + * Output: + * pEnable - status + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT - invalid port id + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None + */ +rtk_api_ret_t rtk_ptp_portEnable_get(rtk_port_t port, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->ptp_portEnable_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->ptp_portEnable_get(port, pEnable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_ptp_portTimestamp_get + * Description: + * Get PTP timstamp according to the PTP identifier on the dedicated port from the specified device. + * Input: + * unit - unit id + * port - port id + * type - PTP message type + * Output: + * pInfo - pointer buffer of sequence ID and timestamp + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Applicable: + * 8390, 8380 + * Note: + * None + */ +rtk_api_ret_t rtk_ptp_portTimestamp_get( rtk_port_t port, rtk_ptp_msgType_t type, rtk_ptp_info_t *pInfo) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->ptp_portTimestamp_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->ptp_portTimestamp_get(port, type, pInfo); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_ptp_intControl_set + * Description: + * Set PTP interrupt trigger status configuration. + * Input: + * type - Interrupt type. + * enable - Interrupt status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * The API can set PTP interrupt status configuration. + * The interrupt trigger status is shown in the following: + * PTP_INT_TYPE_TX_SYNC = 0, + * PTP_INT_TYPE_TX_DELAY_REQ, + * PTP_INT_TYPE_TX_PDELAY_REQ, + * PTP_INT_TYPE_TX_PDELAY_RESP, + * PTP_INT_TYPE_RX_SYNC, + * PTP_INT_TYPE_RX_DELAY_REQ, + * PTP_INT_TYPE_RX_PDELAY_REQ, + * PTP_INT_TYPE_RX_PDELAY_RESP, + * PTP_INT_TYPE_ALL, + */ +rtk_api_ret_t rtk_ptp_intControl_set(rtk_ptp_intType_t type, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->ptp_intControl_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->ptp_intControl_set(type, enable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_ptp_intControl_get + * Description: + * Get PTP interrupt trigger status configuration. + * Input: + * type - Interrupt type. + * Output: + * pEnable - Interrupt status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get interrupt status configuration. + * The interrupt trigger status is shown in the following: + * PTP_INT_TYPE_TX_SYNC = 0, + * PTP_INT_TYPE_TX_DELAY_REQ, + * PTP_INT_TYPE_TX_PDELAY_REQ, + * PTP_INT_TYPE_TX_PDELAY_RESP, + * PTP_INT_TYPE_RX_SYNC, + * PTP_INT_TYPE_RX_DELAY_REQ, + * PTP_INT_TYPE_RX_PDELAY_REQ, + * PTP_INT_TYPE_RX_PDELAY_RESP, + */ +rtk_api_ret_t rtk_ptp_intControl_get(rtk_ptp_intType_t type, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->ptp_intControl_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->ptp_intControl_get(type, pEnable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_ptp_intStatus_get + * Description: + * Get PTP port interrupt trigger status. + * Input: + * port - physical port + * Output: + * pStatusMask - Interrupt status bit mask. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get interrupt trigger status when interrupt happened. + * The interrupt trigger status is shown in the following: + * - PORT 0 INT (value[0] (Bit0)) + * - PORT 1 INT (value[0] (Bit1)) + * - PORT 2 INT (value[0] (Bit2)) + * - PORT 3 INT (value[0] (Bit3)) + * - PORT 4 INT (value[0] (Bit4)) + + * + */ +rtk_api_ret_t rtk_ptp_intStatus_get(rtk_ptp_intStatus_t *pStatusMask) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->ptp_intStatus_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->ptp_intStatus_get(pStatusMask); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_ptp_portIntStatus_set + * Description: + * Set PTP port interrupt trigger status to clean. + * Input: + * port - physical port + * statusMask - Interrupt status bit mask. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can clean interrupt trigger status when interrupt happened. + * The interrupt trigger status is shown in the following: + * - PTP_INT_TYPE_TX_SYNC (value[0] (Bit0)) + * - PTP_INT_TYPE_TX_DELAY_REQ (value[0] (Bit1)) + * - PTP_INT_TYPE_TX_PDELAY_REQ (value[0] (Bit2)) + * - PTP_INT_TYPE_TX_PDELAY_RESP (value[0] (Bit3)) + * - PTP_INT_TYPE_RX_SYNC (value[0] (Bit4)) + * - PTP_INT_TYPE_RX_DELAY_REQ (value[0] (Bit5)) + * - PTP_INT_TYPE_RX_PDELAY_REQ (value[0] (Bit6)) + * - PTP_INT_TYPE_RX_PDELAY_RESP (value[0] (Bit7)) + * The status will be cleared after execute this API. + */ +rtk_api_ret_t rtk_ptp_portIntStatus_set(rtk_port_t port, rtk_ptp_intStatus_t statusMask) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->ptp_portIntStatus_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->ptp_portIntStatus_set(port, statusMask); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_ptp_portIntStatus_get + * Description: + * Get PTP port interrupt trigger status. + * Input: + * port - physical port + * Output: + * pStatusMask - Interrupt status bit mask. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get interrupt trigger status when interrupt happened. + * The interrupt trigger status is shown in the following: + * - PTP_INT_TYPE_TX_SYNC (value[0] (Bit0)) + * - PTP_INT_TYPE_TX_DELAY_REQ (value[0] (Bit1)) + * - PTP_INT_TYPE_TX_PDELAY_REQ (value[0] (Bit2)) + * - PTP_INT_TYPE_TX_PDELAY_RESP (value[0] (Bit3)) + * - PTP_INT_TYPE_RX_SYNC (value[0] (Bit4)) + * - PTP_INT_TYPE_RX_DELAY_REQ (value[0] (Bit5)) + * - PTP_INT_TYPE_RX_PDELAY_REQ (value[0] (Bit6)) + * - PTP_INT_TYPE_RX_PDELAY_RESP (value[0] (Bit7)) + * + */ +rtk_api_ret_t rtk_ptp_portIntStatus_get(rtk_port_t port, rtk_ptp_intStatus_t *pStatusMask) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->ptp_portIntStatus_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->ptp_portIntStatus_get(port, pStatusMask); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_ptp_portTrap_set + * Description: + * Set PTP packet trap of the specified port. + * Input: + * port - port id + * enable - status + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT - invalid port id + * RT_ERR_INPUT - invalid input parameter + * Note: + * None + */ +rtk_api_ret_t rtk_ptp_portTrap_set(rtk_port_t port, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->ptp_portTrap_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->ptp_portTrap_set(port, enable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_ptp_portTrap_get + * Description: + * Get PTP packet trap of the specified port. + * Input: + * port - port id + * Output: + * pEnable - status + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT - invalid port id + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None + */ +rtk_api_ret_t rtk_ptp_portTrap_get(rtk_port_t port, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->ptp_portTrap_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->ptp_portTrap_get(port, pEnable); + RTK_API_UNLOCK(); + + return retVal; +} + + + + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/ptp.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/ptp.h new file mode 100644 index 00000000..d35347dd --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/ptp.h @@ -0,0 +1,513 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8367/RTL8367C switch high-level API + * + * Feature : The file includes time module high-layer API defination + * + */ + +#ifndef __RTK_API_PTP_H__ +#define __RTK_API_PTP_H__ + +/* + * Symbol Definition + */ +#define RTK_MAX_NUM_OF_NANO_SECOND 0x3B9AC9FF +#define RTK_PTP_INTR_MASK 0xFF +#define RTK_MAX_NUM_OF_TPID 0xFFFF + +/* Message Type */ +typedef enum rtk_ptp_msgType_e +{ + PTP_MSG_TYPE_TX_SYNC = 0, + PTP_MSG_TYPE_TX_DELAY_REQ, + PTP_MSG_TYPE_TX_PDELAY_REQ, + PTP_MSG_TYPE_TX_PDELAY_RESP, + PTP_MSG_TYPE_RX_SYNC, + PTP_MSG_TYPE_RX_DELAY_REQ, + PTP_MSG_TYPE_RX_PDELAY_REQ, + PTP_MSG_TYPE_RX_PDELAY_RESP, + PTP_MSG_TYPE_END +} rtk_ptp_msgType_t; + +typedef enum rtk_ptp_intType_e +{ + PTP_INT_TYPE_TX_SYNC = 0, + PTP_INT_TYPE_TX_DELAY_REQ, + PTP_INT_TYPE_TX_PDELAY_REQ, + PTP_INT_TYPE_TX_PDELAY_RESP, + PTP_INT_TYPE_RX_SYNC, + PTP_INT_TYPE_RX_DELAY_REQ, + PTP_INT_TYPE_RX_PDELAY_REQ, + PTP_INT_TYPE_RX_PDELAY_RESP, + PTP_INT_TYPE_ALL, + PTP_INT_TYPE_END +}rtk_ptp_intType_t; + +typedef enum rtk_ptp_sys_adjust_e +{ + SYS_ADJUST_PLUS = 0, + SYS_ADJUST_MINUS, + SYS_ADJUST_END +} rtk_ptp_sys_adjust_t; + + +/* Reference Time */ +typedef struct rtk_ptp_timeStamp_s +{ + rtk_uint32 sec; + rtk_uint32 nsec; +} rtk_ptp_timeStamp_t; + +typedef struct rtk_ptp_info_s +{ + rtk_uint32 sequenceId; + rtk_ptp_timeStamp_t timeStamp; +} rtk_ptp_info_t; + +typedef rtk_uint32 rtk_ptp_tpid_t; + +typedef rtk_uint32 rtk_ptp_intStatus_t; /* interrupt status mask */ + +/* + * Data Declaration + */ + +/* + * Function Declaration + */ +/* Function Name: + * rtk_time_init + * Description: + * PTP function initialization. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API is used to initialize EEE status. + */ +extern rtk_api_ret_t rtk_ptp_init(void); + +/* Function Name: + * rtk_ptp_mac_set + * Description: + * Configure PTP mac address. + * Input: + * mac - mac address to parser PTP packets. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * Note: + * None + */ +extern rtk_api_ret_t rtk_ptp_mac_set(rtk_mac_t mac); + +/* Function Name: + * rtk_ptp_mac_get + * Description: + * Get PTP mac address. + * Input: + * None + * Output: + * pMac - mac address to parser PTP packets. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * Note: + * None + */ +extern rtk_api_ret_t rtk_ptp_mac_get(rtk_mac_t *pMac); + +/* Function Name: + * rtk_ptp_tpid_set + * Description: + * Configure PTP accepted outer & inner tag TPID. + * Input: + * outerId - Ether type of S-tag frame parsing in PTP ports. + * innerId - Ether type of C-tag frame parsing in PTP ports. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * Note: + * None + */ +extern rtk_api_ret_t rtk_ptp_tpid_set(rtk_ptp_tpid_t outerId, rtk_ptp_tpid_t innerId); + +/* Function Name: + * rtk_ptp_tpid_get + * Description: + * Get PTP accepted outer & inner tag TPID. + * Input: + * None + * Output: + * pOuterId - Ether type of S-tag frame parsing in PTP ports. + * pInnerId - Ether type of C-tag frame parsing in PTP ports. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +extern rtk_api_ret_t rtk_ptp_tpid_get(rtk_ptp_tpid_t *pOuterId, rtk_ptp_tpid_t *pInnerId); + +/* Function Name: + * rtk_ptp_refTime_set + * Description: + * Set the reference time of the specified device. + * Input: + * timeStamp - reference timestamp value + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT - invalid input parameter + * Applicable: + * 8390, 8380 + * Note: + * None + */ +extern rtk_api_ret_t rtk_ptp_refTime_set(rtk_ptp_timeStamp_t timeStamp); + +/* Function Name: + * rtk_ptp_refTime_get + * Description: + * Get the reference time of the specified device. + * Input: + * Output: + * pTimeStamp - pointer buffer of the reference time + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Applicable: + * 8390, 8380 + * Note: + * None + */ +extern rtk_api_ret_t rtk_ptp_refTime_get(rtk_ptp_timeStamp_t *pTimeStamp); + +/* Function Name: + * rtk_ptp_refTimeAdjust_set + * Description: + * Adjust the reference time. + * Input: + * unit - unit id + * sign - significant + * timeStamp - reference timestamp value + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Note: + * sign=0 for positive adjustment, sign=1 for negative adjustment. + */ +extern rtk_api_ret_t rtk_ptp_refTimeAdjust_set(rtk_ptp_sys_adjust_t sign, rtk_ptp_timeStamp_t timeStamp); + +/* Function Name: + * rtk_ptp_refTimeEnable_set + * Description: + * Set the enable state of reference time of the specified device. + * Input: + * enable - status + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT - invalid input parameter + * Note: + * None + */ +extern rtk_api_ret_t rtk_ptp_refTimeEnable_set(rtk_enable_t enable); + +/* Function Name: + * rtk_ptp_refTimeEnable_get + * Description: + * Get the enable state of reference time of the specified device. + * Input: + * Output: + * pEnable - status + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Applicable: + * 8390, 8380 + * Note: + * None + */ +extern rtk_api_ret_t rtk_ptp_refTimeEnable_get(rtk_enable_t *pEnable); + +/* Function Name: + * rtk_ptp_portEnable_set + * Description: + * Set PTP status of the specified port. + * Input: + * port - port id + * enable - status + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT - invalid port id + * RT_ERR_INPUT - invalid input parameter + * Note: + * None + */ +extern rtk_api_ret_t rtk_ptp_portEnable_set(rtk_port_t port, rtk_enable_t enable); + +/* Function Name: + * rtk_ptp_portEnable_get + * Description: + * Get PTP status of the specified port. + * Input: + * port - port id + * Output: + * pEnable - status + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT - invalid port id + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None + */ +extern rtk_api_ret_t rtk_ptp_portEnable_get(rtk_port_t port, rtk_enable_t *pEnable); + +/* Function Name: + * rtk_ptp_portTimestamp_get + * Description: + * Get PTP timstamp according to the PTP identifier on the dedicated port from the specified device. + * Input: + * unit - unit id + * port - port id + * type - PTP message type + * Output: + * pInfo - pointer buffer of sequence ID and timestamp + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Applicable: + * 8390, 8380 + * Note: + * None + */ +extern rtk_api_ret_t rtk_ptp_portTimestamp_get( rtk_port_t port, rtk_ptp_msgType_t type, rtk_ptp_info_t *pInfo); + +/* Function Name: + * rtk_ptp_intControl_set + * Description: + * Set PTP interrupt trigger status configuration. + * Input: + * type - Interrupt type. + * enable - Interrupt status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * The API can set PTP interrupt status configuration. + * The interrupt trigger status is shown in the following: + * PTP_INT_TYPE_TX_SYNC = 0, + * PTP_INT_TYPE_TX_DELAY_REQ, + * PTP_INT_TYPE_TX_PDELAY_REQ, + * PTP_INT_TYPE_TX_PDELAY_RESP, + * PTP_INT_TYPE_RX_SYNC, + * PTP_INT_TYPE_RX_DELAY_REQ, + * PTP_INT_TYPE_RX_PDELAY_REQ, + * PTP_INT_TYPE_RX_PDELAY_RESP, + * PTP_INT_TYPE_ALL, + */ +extern rtk_api_ret_t rtk_ptp_intControl_set(rtk_ptp_intType_t type, rtk_enable_t enable); + +/* Function Name: + * rtk_ptp_intControl_get + * Description: + * Get PTP interrupt trigger status configuration. + * Input: + * type - Interrupt type. + * Output: + * pEnable - Interrupt status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get interrupt status configuration. + * The interrupt trigger status is shown in the following: + * PTP_INT_TYPE_TX_SYNC = 0, + * PTP_INT_TYPE_TX_DELAY_REQ, + * PTP_INT_TYPE_TX_PDELAY_REQ, + * PTP_INT_TYPE_TX_PDELAY_RESP, + * PTP_INT_TYPE_RX_SYNC, + * PTP_INT_TYPE_RX_DELAY_REQ, + * PTP_INT_TYPE_RX_PDELAY_REQ, + * PTP_INT_TYPE_RX_PDELAY_RESP, + */ +extern rtk_api_ret_t rtk_ptp_intControl_get(rtk_ptp_intType_t type, rtk_enable_t *pEnable); + + +/* Function Name: + * rtk_ptp_intStatus_get + * Description: + * Get PTP port interrupt trigger status. + * Input: + * port - physical port + * Output: + * pStatusMask - Interrupt status bit mask. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get interrupt trigger status when interrupt happened. + * The interrupt trigger status is shown in the following: + * - PORT 0 INT (value[0] (Bit0)) + * - PORT 1 INT (value[0] (Bit1)) + * - PORT 2 INT (value[0] (Bit2)) + * - PORT 3 INT (value[0] (Bit3)) + * - PORT 4 INT (value[0] (Bit4)) + + * + */ +extern rtk_api_ret_t rtk_ptp_intStatus_get(rtk_ptp_intStatus_t *pStatusMask); + +/* Function Name: + * rtk_ptp_portIntStatus_set + * Description: + * Set PTP port interrupt trigger status to clean. + * Input: + * port - physical port + * statusMask - Interrupt status bit mask. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can clean interrupt trigger status when interrupt happened. + * The interrupt trigger status is shown in the following: + * - PTP_INT_TYPE_TX_SYNC (value[0] (Bit0)) + * - PTP_INT_TYPE_TX_DELAY_REQ (value[0] (Bit1)) + * - PTP_INT_TYPE_TX_PDELAY_REQ (value[0] (Bit2)) + * - PTP_INT_TYPE_TX_PDELAY_RESP (value[0] (Bit3)) + * - PTP_INT_TYPE_RX_SYNC (value[0] (Bit4)) + * - PTP_INT_TYPE_RX_DELAY_REQ (value[0] (Bit5)) + * - PTP_INT_TYPE_RX_PDELAY_REQ (value[0] (Bit6)) + * - PTP_INT_TYPE_RX_PDELAY_RESP (value[0] (Bit7)) + * The status will be cleared after execute this API. + */ +extern rtk_api_ret_t rtk_ptp_portIntStatus_set(rtk_port_t port, rtk_ptp_intStatus_t statusMask); + +/* Function Name: + * rtk_ptp_portIntStatus_get + * Description: + * Get PTP port interrupt trigger status. + * Input: + * port - physical port + * Output: + * pStatusMask - Interrupt status bit mask. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get interrupt trigger status when interrupt happened. + * The interrupt trigger status is shown in the following: + * - PTP_INT_TYPE_TX_SYNC (value[0] (Bit0)) + * - PTP_INT_TYPE_TX_DELAY_REQ (value[0] (Bit1)) + * - PTP_INT_TYPE_TX_PDELAY_REQ (value[0] (Bit2)) + * - PTP_INT_TYPE_TX_PDELAY_RESP (value[0] (Bit3)) + * - PTP_INT_TYPE_RX_SYNC (value[0] (Bit4)) + * - PTP_INT_TYPE_RX_DELAY_REQ (value[0] (Bit5)) + * - PTP_INT_TYPE_RX_PDELAY_REQ (value[0] (Bit6)) + * - PTP_INT_TYPE_RX_PDELAY_RESP (value[0] (Bit7)) + * + */ +extern rtk_api_ret_t rtk_ptp_portIntStatus_get(rtk_port_t port, rtk_ptp_intStatus_t *pStatusMask); + +/* Function Name: + * rtk_ptp_portPtpTrap_set + * Description: + * Set PTP packet trap of the specified port. + * Input: + * port - port id + * enable - status + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT - invalid port id + * RT_ERR_INPUT - invalid input parameter + * Note: + * None + */ +extern rtk_api_ret_t rtk_ptp_portTrap_set(rtk_port_t port, rtk_enable_t enable); + +/* Function Name: + * rtk_ptp_portPtpEnable_get + * Description: + * Get PTP packet trap of the specified port. + * Input: + * port - port id + * Output: + * pEnable - status + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT - invalid port id + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None + */ +extern rtk_api_ret_t rtk_ptp_portTrap_get(rtk_port_t port, rtk_enable_t *pEnable); + +#endif /* __RTK_API_PTP_H__ */ diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/qos.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/qos.c new file mode 100644 index 00000000..ac72b42e --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/qos.c @@ -0,0 +1,1113 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8367C + * Feature : Here is a list of all functions and variables in QoS module. + * + */ + +#include +#include +#include +#include + +#include + +/* Function Name: + * rtk_qos_init + * Description: + * Configure Qos default settings with queue number assigment to each port. + * Input: + * queueNum - Queue number of each port. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will initialize related Qos setting with queue number assigment. + * The queue number is from 1 to 8. + */ +rtk_api_ret_t rtk_qos_init(rtk_queue_num_t queueNum) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->qos_init) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->qos_init(queueNum); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_qos_priSel_set + * Description: + * Configure the priority order among different priority mechanism. + * Input: + * index - Priority decision table index (0~1) + * pPriDec - Priority assign for port, dscp, 802.1p, cvlan, svlan, acl based priority decision. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_SEL_PRI_SOURCE - Invalid priority decision source parameter. + * Note: + * ASIC will follow user priority setting of mechanisms to select mapped queue priority for receiving frame. + * If two priority mechanisms are the same, the ASIC will chose the highest priority from mechanisms to + * assign queue priority to receiving frame. + * The priority sources are: + * - PRIDEC_PORT + * - PRIDEC_ACL + * - PRIDEC_DSCP + * - PRIDEC_1Q + * - PRIDEC_1AD + * - PRIDEC_CVLAN + * - PRIDEC_DA + * - PRIDEC_SA + */ +rtk_api_ret_t rtk_qos_priSel_set(rtk_qos_priDecTbl_t index, rtk_priority_select_t *pPriDec) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->qos_priSel_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->qos_priSel_set(index, pPriDec); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_qos_priSel_get + * Description: + * Get the priority order configuration among different priority mechanism. + * Input: + * index - Priority decision table index (0~1) + * Output: + * pPriDec - Priority assign for port, dscp, 802.1p, cvlan, svlan, acl based priority decision . + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * ASIC will follow user priority setting of mechanisms to select mapped queue priority for receiving frame. + * If two priority mechanisms are the same, the ASIC will chose the highest priority from mechanisms to + * assign queue priority to receiving frame. + * The priority sources are: + * - PRIDEC_PORT, + * - PRIDEC_ACL, + * - PRIDEC_DSCP, + * - PRIDEC_1Q, + * - PRIDEC_1AD, + * - PRIDEC_CVLAN, + * - PRIDEC_DA, + * - PRIDEC_SA, + */ +rtk_api_ret_t rtk_qos_priSel_get(rtk_qos_priDecTbl_t index, rtk_priority_select_t *pPriDec) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->qos_priSel_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->qos_priSel_get(index, pPriDec); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_qos_1pPriRemap_set + * Description: + * Configure 1Q priorities mapping to internal absolute priority. + * Input: + * dot1p_pri - 802.1p priority value. + * int_pri - internal priority value. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_VLAN_PRIORITY - Invalid 1p priority. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * Priority of 802.1Q assignment for internal asic priority, and it is used for queue usage and packet scheduling. + */ +rtk_api_ret_t rtk_qos_1pPriRemap_set(rtk_pri_t dot1p_pri, rtk_pri_t int_pri) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->qos_1pPriRemap_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->qos_1pPriRemap_set(dot1p_pri, int_pri); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_qos_1pPriRemap_get + * Description: + * Get 1Q priorities mapping to internal absolute priority. + * Input: + * dot1p_pri - 802.1p priority value . + * Output: + * pInt_pri - internal priority value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_VLAN_PRIORITY - Invalid priority. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * Priority of 802.1Q assigment for internal asic priority, and it is uesed for queue usage and packet scheduling. + */ +rtk_api_ret_t rtk_qos_1pPriRemap_get(rtk_pri_t dot1p_pri, rtk_pri_t *pInt_pri) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->qos_1pPriRemap_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->qos_1pPriRemap_get(dot1p_pri, pInt_pri); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_qos_dscpPriRemap_set + * Description: + * Map dscp value to internal priority. + * Input: + * dscp - Dscp value of receiving frame + * int_pri - internal priority value . + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_QOS_DSCP_VALUE - Invalid DSCP value. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * The Differentiated Service Code Point is a selector for router's per-hop behaviors. As a selector, there is no implication that a numerically + * greater DSCP implies a better network service. As can be seen, the DSCP totally overlaps the old precedence field of TOS. So if values of + * DSCP are carefully chosen then backward compatibility can be achieved. + */ +rtk_api_ret_t rtk_qos_dscpPriRemap_set(rtk_dscp_t dscp, rtk_pri_t int_pri) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->qos_dscpPriRemap_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->qos_dscpPriRemap_set(dscp, int_pri); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_qos_dscpPriRemap_get + * Description: + * Get dscp value to internal priority. + * Input: + * dscp - Dscp value of receiving frame + * Output: + * pInt_pri - internal priority value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_DSCP_VALUE - Invalid DSCP value. + * Note: + * The Differentiated Service Code Point is a selector for router's per-hop behaviors. As a selector, there is no implication that a numerically + * greater DSCP implies a better network service. As can be seen, the DSCP totally overlaps the old precedence field of TOS. So if values of + * DSCP are carefully chosen then backward compatibility can be achieved. + */ +rtk_api_ret_t rtk_qos_dscpPriRemap_get(rtk_dscp_t dscp, rtk_pri_t *pInt_pri) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->qos_dscpPriRemap_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->qos_dscpPriRemap_get(dscp, pInt_pri); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_qos_portPri_set + * Description: + * Configure priority usage to each port. + * Input: + * port - Port id. + * int_pri - internal priority value. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_QOS_SEL_PORT_PRI - Invalid port priority. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * The API can set priority of port assignments for queue usage and packet scheduling. + */ +rtk_api_ret_t rtk_qos_portPri_set(rtk_port_t port, rtk_pri_t int_pri) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->qos_portPri_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->qos_portPri_set(port, int_pri); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_qos_portPri_get + * Description: + * Get priority usage to each port. + * Input: + * port - Port id. + * Output: + * pInt_pri - internal priority value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get priority of port assignments for queue usage and packet scheduling. + */ +rtk_api_ret_t rtk_qos_portPri_get(rtk_port_t port, rtk_pri_t *pInt_pri) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->qos_portPri_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->qos_portPri_get(port, pInt_pri); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_qos_queueNum_set + * Description: + * Set output queue number for each port. + * Input: + * port - Port id. + * index - Mapping queue number (1~8) + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_QUEUE_NUM - Invalid queue number. + * Note: + * The API can set the output queue number of the specified port. The queue number is from 1 to 8. + */ +rtk_api_ret_t rtk_qos_queueNum_set(rtk_port_t port, rtk_queue_num_t queue_num) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->qos_queueNum_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->qos_queueNum_set(port, queue_num); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_qos_queueNum_get + * Description: + * Get output queue number. + * Input: + * port - Port id. + * Output: + * pQueue_num - Mapping queue number + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API will return the output queue number of the specified port. The queue number is from 1 to 8. + */ +rtk_api_ret_t rtk_qos_queueNum_get(rtk_port_t port, rtk_queue_num_t *pQueue_num) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->qos_queueNum_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->qos_queueNum_get(port, pQueue_num); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_qos_priMap_set + * Description: + * Set output queue number for each port. + * Input: + * queue_num - Queue number usage. + * pPri2qid - Priority mapping to queue ID. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_QUEUE_ID - Invalid queue id. + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * ASIC supports priority mapping to queue with different queue number from 1 to 8. + * For different queue numbers usage, ASIC supports different internal available queue IDs. + */ +rtk_api_ret_t rtk_qos_priMap_set(rtk_queue_num_t queue_num, rtk_qos_pri2queue_t *pPri2qid) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->qos_priMap_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->qos_priMap_set(queue_num, pPri2qid); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_qos_priMap_get + * Description: + * Get priority to queue ID mapping table parameters. + * Input: + * queue_num - Queue number usage. + * Output: + * pPri2qid - Priority mapping to queue ID. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_QUEUE_NUM - Invalid queue number. + * Note: + * The API can return the mapping queue id of the specified priority and queue number. + * The queue number is from 1 to 8. + */ +rtk_api_ret_t rtk_qos_priMap_get(rtk_queue_num_t queue_num, rtk_qos_pri2queue_t *pPri2qid) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->qos_priMap_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->qos_priMap_get(queue_num, pPri2qid); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_qos_schedulingQueue_set + * Description: + * Set weight and type of queues in dedicated port. + * Input: + * port - Port id. + * pQweights - The array of weights for WRR/WFQ queue (0 for STRICT_PRIORITY queue). + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_QOS_QUEUE_WEIGHT - Invalid queue weight. + * Note: + * The API can set weight and type, strict priority or weight fair queue (WFQ) for + * dedicated port for using queues. If queue id is not included in queue usage, + * then its type and weight setting in dummy for setting. There are priorities + * as queue id in strict queues. It means strict queue id 5 carrying higher priority + * than strict queue id 4. The WFQ queue weight is from 1 to 127, and weight 0 is + * for strict priority queue type. + */ +rtk_api_ret_t rtk_qos_schedulingQueue_set(rtk_port_t port, rtk_qos_queue_weights_t *pQweights) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->qos_schedulingQueue_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->qos_schedulingQueue_set(port, pQweights); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_qos_schedulingQueue_get + * Description: + * Get weight and type of queues in dedicated port. + * Input: + * port - Port id. + * Output: + * pQweights - The array of weights for WRR/WFQ queue (0 for STRICT_PRIORITY queue). + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get weight and type, strict priority or weight fair queue (WFQ) for dedicated port for using queues. + * The WFQ queue weight is from 1 to 127, and weight 0 is for strict priority queue type. + */ +rtk_api_ret_t rtk_qos_schedulingQueue_get(rtk_port_t port, rtk_qos_queue_weights_t *pQweights) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->qos_schedulingQueue_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->qos_schedulingQueue_get(port, pQweights); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_qos_1pRemarkEnable_set + * Description: + * Set 1p Remarking state + * Input: + * port - Port id. + * enable - State of per-port 1p Remarking + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable parameter. + * Note: + * The API can enable or disable 802.1p remarking ability for whole system. + * The status of 802.1p remark: + * - DISABLED + * - ENABLED + */ +rtk_api_ret_t rtk_qos_1pRemarkEnable_set(rtk_port_t port, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->qos_1pRemarkEnable_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->qos_1pRemarkEnable_set(port, enable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_qos_1pRemarkEnable_get + * Description: + * Get 802.1p remarking ability. + * Input: + * port - Port id. + * Output: + * pEnable - Status of 802.1p remark. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get 802.1p remarking ability. + * The status of 802.1p remark: + * - DISABLED + * - ENABLED + */ +rtk_api_ret_t rtk_qos_1pRemarkEnable_get(rtk_port_t port, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->qos_1pRemarkEnable_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->qos_1pRemarkEnable_get(port, pEnable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_qos_1pRemark_set + * Description: + * Set 802.1p remarking parameter. + * Input: + * int_pri - Internal priority value. + * dot1p_pri - 802.1p priority value. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_VLAN_PRIORITY - Invalid 1p priority. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * The API can set 802.1p parameters source priority and new priority. + */ +rtk_api_ret_t rtk_qos_1pRemark_set(rtk_pri_t int_pri, rtk_pri_t dot1p_pri) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->qos_1pRemark_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->qos_1pRemark_set(int_pri, dot1p_pri); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_qos_1pRemark_get + * Description: + * Get 802.1p remarking parameter. + * Input: + * int_pri - Internal priority value. + * Output: + * pDot1p_pri - 802.1p priority value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * The API can get 802.1p remarking parameters. It would return new priority of ingress priority. + */ +rtk_api_ret_t rtk_qos_1pRemark_get(rtk_pri_t int_pri, rtk_pri_t *pDot1p_pri) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->qos_1pRemark_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->qos_1pRemark_get(int_pri, pDot1p_pri); + RTK_API_UNLOCK(); + + return retVal; +} + + +/* Function Name: + * rtk_qos_1pRemarkSrcSel_set + * Description: + * Set remarking source of 802.1p remarking. + * Input: + * type - remarking source + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + + * Note: + * The API can configure 802.1p remark functionality to map original 802.1p value or internal + * priority to TX DSCP value. + */ +rtk_api_ret_t rtk_qos_1pRemarkSrcSel_set(rtk_qos_1pRmkSrc_t type) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->qos_1pRemarkSrcSel_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->qos_1pRemarkSrcSel_set(type); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_qos_1pRemarkSrcSel_get + * Description: + * Get remarking source of 802.1p remarking. + * Input: + * none + * Output: + * pType - remarking source + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * RT_ERR_NULL_POINTER - input parameter may be null pointer + + * Note: + * None + */ +rtk_api_ret_t rtk_qos_1pRemarkSrcSel_get(rtk_qos_1pRmkSrc_t *pType) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->qos_1pRemarkSrcSel_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->qos_1pRemarkSrcSel_get(pType); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_qos_dscpRemarkEnable_set + * Description: + * Set DSCP remarking ability. + * Input: + * port - Port id. + * enable - status of DSCP remark. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * RT_ERR_ENABLE - Invalid enable parameter. + * Note: + * The API can enable or disable DSCP remarking ability for whole system. + * The status of DSCP remark: + * - DISABLED + * - ENABLED + */ +rtk_api_ret_t rtk_qos_dscpRemarkEnable_set(rtk_port_t port, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->qos_dscpRemarkEnable_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->qos_dscpRemarkEnable_set(port, enable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_qos_dscpRemarkEnable_get + * Description: + * Get DSCP remarking ability. + * Input: + * port - Port id. + * Output: + * pEnable - status of DSCP remarking. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get DSCP remarking ability. + * The status of DSCP remark: + * - DISABLED + * - ENABLED + */ +rtk_api_ret_t rtk_qos_dscpRemarkEnable_get(rtk_port_t port, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->qos_dscpRemarkEnable_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->qos_dscpRemarkEnable_get(port, pEnable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_qos_dscpRemark_set + * Description: + * Set DSCP remarking parameter. + * Input: + * int_pri - Internal priority value. + * dscp - DSCP value. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * RT_ERR_QOS_DSCP_VALUE - Invalid DSCP value. + * Note: + * The API can set DSCP value and mapping priority. + */ +rtk_api_ret_t rtk_qos_dscpRemark_set(rtk_pri_t int_pri, rtk_dscp_t dscp) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->qos_dscpRemark_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->qos_dscpRemark_set(int_pri, dscp); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_qos_dscpRemark_get + * Description: + * Get DSCP remarking parameter. + * Input: + * int_pri - Internal priority value. + * Output: + * Dscp - DSCP value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * The API can get DSCP parameters. It would return DSCP value for mapping priority. + */ +rtk_api_ret_t rtk_qos_dscpRemark_get(rtk_pri_t int_pri, rtk_dscp_t *pDscp) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->qos_dscpRemark_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->qos_dscpRemark_get(int_pri, pDscp); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_qos_dscpRemarkSrcSel_set + * Description: + * Set remarking source of DSCP remarking. + * Input: + * type - remarking source + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + + * Note: + * The API can configure DSCP remark functionality to map original DSCP value or internal + * priority to TX DSCP value. + */ +rtk_api_ret_t rtk_qos_dscpRemarkSrcSel_set(rtk_qos_dscpRmkSrc_t type) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->qos_dscpRemarkSrcSel_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->qos_dscpRemarkSrcSel_set(type); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_qos_dscpRemarkSrcSel_get + * Description: + * Get remarking source of DSCP remarking. + * Input: + * none + * Output: + * pType - remarking source + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * RT_ERR_NULL_POINTER - input parameter may be null pointer + + * Note: + * None + */ +rtk_api_ret_t rtk_qos_dscpRemarkSrcSel_get(rtk_qos_dscpRmkSrc_t *pType) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->qos_dscpRemarkSrcSel_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->qos_dscpRemarkSrcSel_get(pType); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_qos_dscpRemark2Dscp_set + * Description: + * Set DSCP to remarked DSCP mapping. + * Input: + * dscp - DSCP value + * rmkDscp - remarked DSCP value + * Output: + * None. + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_QOS_DSCP_VALUE - Invalid dscp value + * Note: + * dscp parameter can be DSCP value or internal priority according to configuration of API + * dal_apollomp_qos_dscpRemarkSrcSel_set(), because DSCP remark functionality can map original DSCP + * value or internal priority to TX DSCP value. + */ +rtk_api_ret_t rtk_qos_dscpRemark2Dscp_set(rtk_dscp_t dscp, rtk_dscp_t rmkDscp) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->qos_dscpRemark2Dscp_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->qos_dscpRemark2Dscp_set(dscp, rmkDscp); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_qos_dscpRemark2Dscp_get + * Description: + * Get DSCP to remarked DSCP mapping. + * Input: + * dscp - DSCP value + * Output: + * pDscp - remarked DSCP value + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_QOS_DSCP_VALUE - Invalid dscp value + * RT_ERR_NULL_POINTER - NULL pointer + * Note: + * None. + */ +rtk_api_ret_t rtk_qos_dscpRemark2Dscp_get(rtk_dscp_t dscp, rtk_dscp_t *pDscp) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->qos_dscpRemark2Dscp_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->qos_dscpRemark2Dscp_get(dscp, pDscp); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_qos_portPriSelIndex_set + * Description: + * Configure priority decision index to each port. + * Input: + * port - Port id. + * index - priority decision index. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENTRY_INDEX - Invalid entry index. + * Note: + * The API can set priority of port assignments for queue usage and packet scheduling. + */ +rtk_api_ret_t rtk_qos_portPriSelIndex_set(rtk_port_t port, rtk_qos_priDecTbl_t index) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->qos_portPriSelIndex_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->qos_portPriSelIndex_set(port, index); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_qos_portPriSelIndex_get + * Description: + * Get priority decision index from each port. + * Input: + * port - Port id. + * Output: + * pIndex - priority decision index. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get priority of port assignments for queue usage and packet scheduling. + */ +rtk_api_ret_t rtk_qos_portPriSelIndex_get(rtk_port_t port, rtk_qos_priDecTbl_t *pIndex) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->qos_portPriSelIndex_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->qos_portPriSelIndex_get(port, pIndex); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_qos_schedulingType_set + * Description: + * Configure type of scheduling. + * Input: + * queueType - Scheduling type. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_SCHE_TYPE - Invalid QoS scheduling type. + * Note: + * The API can set type of scheduling. + */ +rtk_api_ret_t rtk_qos_schedulingType_set(rtk_qos_scheduling_type_t queueType) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->qos_schedulingType_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->qos_schedulingType_set(queueType); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_qos_schedulingType_get + * Description: + * Get type of scheduling. + * Input: + * none. + * Output: + * pIndex - priority decision index. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - NULL pointer + * Note: + * The API can get type of scheduling. + */ +rtk_api_ret_t rtk_qos_schedulingType_get(rtk_qos_scheduling_type_t *pQueueType) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->qos_schedulingType_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->qos_schedulingType_get(pQueueType); + RTK_API_UNLOCK(); + + return retVal; +} + + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/qos.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/qos.h new file mode 100644 index 00000000..477c1e3b --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/qos.h @@ -0,0 +1,816 @@ + /* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8367/RTL8367C switch high-level API + * + * Feature : The file includes QoS module high-layer API defination + * + */ + +#ifndef __RTK_API_QOS_H__ +#define __RTK_API_QOS_H__ + +/* + * Data Type Declaration + */ +#define QOS_DEFAULT_TICK_PERIOD (19-1) +#define QOS_DEFAULT_BYTE_PER_TOKEN 34 +#define QOS_DEFAULT_LK_THRESHOLD (34*3) /* Why use 0x400? */ + + +#define QOS_DEFAULT_INGRESS_BANDWIDTH 0x3FFF /* 0x3FFF => unlimit */ +#define QOS_DEFAULT_EGRESS_BANDWIDTH 0x3D08 /*( 0x3D08 + 1) * 64Kbps => 1Gbps*/ +#define QOS_DEFAULT_PREIFP 1 +#define QOS_DEFAULT_PACKET_USED_PAGES_FC 0x60 +#define QOS_DEFAULT_PACKET_USED_FC_EN 0 +#define QOS_DEFAULT_QUEUE_BASED_FC_EN 1 + +#define QOS_DEFAULT_PRIORITY_SELECT_PORT 8 +#define QOS_DEFAULT_PRIORITY_SELECT_1Q 0 +#define QOS_DEFAULT_PRIORITY_SELECT_ACL 0 +#define QOS_DEFAULT_PRIORITY_SELECT_DSCP 0 + +#define QOS_DEFAULT_DSCP_MAPPING_PRIORITY 0 + +#define QOS_DEFAULT_1Q_REMARKING_ABILITY 0 +#define QOS_DEFAULT_DSCP_REMARKING_ABILITY 0 +#define QOS_DEFAULT_QUEUE_GAP 20 +#define QOS_DEFAULT_QUEUE_NO_MAX 6 +#define QOS_DEFAULT_AVERAGE_PACKET_RATE 0x3FFF +#define QOS_DEFAULT_BURST_SIZE_IN_APR 0x3F +#define QOS_DEFAULT_PEAK_PACKET_RATE 2 +#define QOS_DEFAULT_SCHEDULER_ABILITY_APR 1 /*disable*/ +#define QOS_DEFAULT_SCHEDULER_ABILITY_PPR 1 /*disable*/ +#define QOS_DEFAULT_SCHEDULER_ABILITY_WFQ 1 /*disable*/ + +#define QOS_WEIGHT_MAX 127 + +#define RTK_MAX_NUM_OF_PRIORITY 8 +#define RTK_MAX_NUM_OF_QUEUE 8 + +#define RTK_PRIMAX 7 +#define RTK_QIDMAX 7 +#define RTK_DSCPMAX 63 + + +/* enum Priority Selection Index */ +typedef enum rtk_qos_priDecTbl_e +{ + PRIDECTBL_IDX0 = 0, + PRIDECTBL_IDX1, + PRIDECTBL_END, +}rtk_qos_priDecTbl_t; + + +/* Types of 802.1p remarking source */ +typedef enum rtk_qos_1pRmkSrc_e +{ + DOT1P_RMK_SRC_USER_PRI, + DOT1P_RMK_SRC_TAG_PRI, + DOT1P_RMK_SRC_END +} rtk_qos_1pRmkSrc_t; + + +/* Types of DSCP remarking source */ +typedef enum rtk_qos_dscpRmkSrc_e +{ + DSCP_RMK_SRC_INT_PRI, + DSCP_RMK_SRC_DSCP, + DSCP_RMK_SRC_USER_PRI, + DSCP_RMK_SRC_END +} rtk_qos_dscpRmkSrc_t; + +typedef struct rtk_priority_select_s +{ + rtk_uint32 port_pri; + rtk_uint32 dot1q_pri; + rtk_uint32 acl_pri; + rtk_uint32 dscp_pri; + rtk_uint32 cvlan_pri; + rtk_uint32 svlan_pri; + rtk_uint32 dmac_pri; + rtk_uint32 smac_pri; +} rtk_priority_select_t; + +typedef struct rtk_qos_pri2queue_s +{ + rtk_uint32 pri2queue[RTK_MAX_NUM_OF_PRIORITY]; +} rtk_qos_pri2queue_t; + +typedef struct rtk_qos_queue_weights_s +{ + rtk_uint32 weights[RTK_MAX_NUM_OF_QUEUE]; +} rtk_qos_queue_weights_t; + +typedef enum rtk_qos_scheduling_type_e +{ + RTK_QOS_WFQ = 0, /* Weighted-Fair-Queue */ + RTK_QOS_WRR, /* Weighted-Round-Robin */ + SCHEDULING_TYPE_END +} rtk_qos_scheduling_type_t; + +typedef rtk_uint32 rtk_queue_num_t; /* queue number*/ + +/* Function Name: + * rtk_qos_init + * Description: + * Configure Qos default settings with queue number assigment to each port. + * Input: + * queueNum - Queue number of each port. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will initialize related Qos setting with queue number assigment. + * The queue number is from 1 to 8. + */ +extern rtk_api_ret_t rtk_qos_init(rtk_queue_num_t queueNum); + +/* Function Name: + * rtk_qos_priSel_set + * Description: + * Configure the priority order among different priority mechanism. + * Input: + * index - Priority decision table index (0~1) + * pPriDec - Priority assign for port, dscp, 802.1p, cvlan, svlan, acl based priority decision. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_SEL_PRI_SOURCE - Invalid priority decision source parameter. + * Note: + * ASIC will follow user priority setting of mechanisms to select mapped queue priority for receiving frame. + * If two priority mechanisms are the same, the ASIC will chose the highest priority from mechanisms to + * assign queue priority to receiving frame. + * The priority sources are: + * - PRIDEC_PORT + * - PRIDEC_ACL + * - PRIDEC_DSCP + * - PRIDEC_1Q + * - PRIDEC_1AD + * - PRIDEC_CVLAN + * - PRIDEC_DA + * - PRIDEC_SA + */ +extern rtk_api_ret_t rtk_qos_priSel_set(rtk_qos_priDecTbl_t index, rtk_priority_select_t *pPriDec); + + +/* Function Name: + * rtk_qos_priSel_get + * Description: + * Get the priority order configuration among different priority mechanism. + * Input: + * index - Priority decision table index (0~1) + * Output: + * pPriDec - Priority assign for port, dscp, 802.1p, cvlan, svlan, acl based priority decision . + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * ASIC will follow user priority setting of mechanisms to select mapped queue priority for receiving frame. + * If two priority mechanisms are the same, the ASIC will chose the highest priority from mechanisms to + * assign queue priority to receiving frame. + * The priority sources are: + * - PRIDEC_PORT, + * - PRIDEC_ACL, + * - PRIDEC_DSCP, + * - PRIDEC_1Q, + * - PRIDEC_1AD, + * - PRIDEC_CVLAN, + * - PRIDEC_DA, + * - PRIDEC_SA, + */ +extern rtk_api_ret_t rtk_qos_priSel_get(rtk_qos_priDecTbl_t index, rtk_priority_select_t *pPriDec); + +/* Function Name: + * rtk_qos_1pPriRemap_set + * Description: + * Configure 1Q priorities mapping to internal absolute priority. + * Input: + * dot1p_pri - 802.1p priority value. + * int_pri - internal priority value. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_VLAN_PRIORITY - Invalid 1p priority. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * Priority of 802.1Q assignment for internal asic priority, and it is used for queue usage and packet scheduling. + */ +extern rtk_api_ret_t rtk_qos_1pPriRemap_set(rtk_pri_t dot1p_pri, rtk_pri_t int_pri); + +/* Function Name: + * rtk_qos_1pPriRemap_get + * Description: + * Get 1Q priorities mapping to internal absolute priority. + * Input: + * dot1p_pri - 802.1p priority value . + * Output: + * pInt_pri - internal priority value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_VLAN_PRIORITY - Invalid priority. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * Priority of 802.1Q assigment for internal asic priority, and it is uesed for queue usage and packet scheduling. + */ +extern rtk_api_ret_t rtk_qos_1pPriRemap_get(rtk_pri_t dot1p_pri, rtk_pri_t *pInt_pri); + + +/* Function Name: + * rtk_qos_1pRemarkSrcSel_set + * Description: + * Set remarking source of 802.1p remarking. + * Input: + * type - remarking source + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + + * Note: + * The API can configure 802.1p remark functionality to map original 802.1p value or internal + * priority to TX DSCP value. + */ +extern rtk_api_ret_t rtk_qos_1pRemarkSrcSel_set(rtk_qos_1pRmkSrc_t type); + +/* Function Name: + * rtk_qos_1pRemarkSrcSel_get + * Description: + * Get remarking source of 802.1p remarking. + * Input: + * none + * Output: + * pType - remarking source + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * RT_ERR_NULL_POINTER - input parameter may be null pointer + + * Note: + * None + */ +extern rtk_api_ret_t rtk_qos_1pRemarkSrcSel_get(rtk_qos_1pRmkSrc_t *pType); + +/* Function Name: + * rtk_qos_dscpPriRemap_set + * Description: + * Map dscp value to internal priority. + * Input: + * dscp - Dscp value of receiving frame + * int_pri - internal priority value . + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_QOS_DSCP_VALUE - Invalid DSCP value. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * The Differentiated Service Code Point is a selector for router's per-hop behaviors. As a selector, there is no implication that a numerically + * greater DSCP implies a better network service. As can be seen, the DSCP totally overlaps the old precedence field of TOS. So if values of + * DSCP are carefully chosen then backward compatibility can be achieved. + */ +extern rtk_api_ret_t rtk_qos_dscpPriRemap_set(rtk_dscp_t dscp, rtk_pri_t int_pri); + +/* Function Name: + * rtk_qos_dscpPriRemap_get + * Description: + * Get dscp value to internal priority. + * Input: + * dscp - Dscp value of receiving frame + * Output: + * pInt_pri - internal priority value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_DSCP_VALUE - Invalid DSCP value. + * Note: + * The Differentiated Service Code Point is a selector for router's per-hop behaviors. As a selector, there is no implication that a numerically + * greater DSCP implies a better network service. As can be seen, the DSCP totally overlaps the old precedence field of TOS. So if values of + * DSCP are carefully chosen then backward compatibility can be achieved. + */ +extern rtk_api_ret_t rtk_qos_dscpPriRemap_get(rtk_dscp_t dscp, rtk_pri_t *pInt_pri); + +/* Function Name: + * rtk_qos_portPri_set + * Description: + * Configure priority usage to each port. + * Input: + * port - Port id. + * int_pri - internal priority value. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_QOS_SEL_PORT_PRI - Invalid port priority. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * The API can set priority of port assignments for queue usage and packet scheduling. + */ +extern rtk_api_ret_t rtk_qos_portPri_set(rtk_port_t port, rtk_pri_t int_pri) ; + +/* Function Name: + * rtk_qos_portPri_get + * Description: + * Get priority usage to each port. + * Input: + * port - Port id. + * Output: + * pInt_pri - internal priority value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get priority of port assignments for queue usage and packet scheduling. + */ +extern rtk_api_ret_t rtk_qos_portPri_get(rtk_port_t port, rtk_pri_t *pInt_pri) ; + +/* Function Name: + * rtk_qos_queueNum_set + * Description: + * Set output queue number for each port. + * Input: + * port - Port id. + * index - Mapping queue number (1~8) + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_QUEUE_NUM - Invalid queue number. + * Note: + * The API can set the output queue number of the specified port. The queue number is from 1 to 8. + */ +extern rtk_api_ret_t rtk_qos_queueNum_set(rtk_port_t port, rtk_queue_num_t queue_num); + +/* Function Name: + * rtk_qos_queueNum_get + * Description: + * Get output queue number. + * Input: + * port - Port id. + * Output: + * pQueue_num - Mapping queue number + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API will return the output queue number of the specified port. The queue number is from 1 to 8. + */ +extern rtk_api_ret_t rtk_qos_queueNum_get(rtk_port_t port, rtk_queue_num_t *pQueue_num); + +/* Function Name: + * rtk_qos_priMap_set + * Description: + * Set output queue number for each port. + * Input: + * queue_num - Queue number usage. + * pPri2qid - Priority mapping to queue ID. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_QUEUE_ID - Invalid queue id. + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * ASIC supports priority mapping to queue with different queue number from 1 to 8. + * For different queue numbers usage, ASIC supports different internal available queue IDs. + */ +extern rtk_api_ret_t rtk_qos_priMap_set(rtk_queue_num_t queue_num, rtk_qos_pri2queue_t *pPri2qid); + + +/* Function Name: + * rtk_qos_priMap_get + * Description: + * Get priority to queue ID mapping table parameters. + * Input: + * queue_num - Queue number usage. + * Output: + * pPri2qid - Priority mapping to queue ID. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_QUEUE_NUM - Invalid queue number. + * Note: + * The API can return the mapping queue id of the specified priority and queue number. + * The queue number is from 1 to 8. + */ +extern rtk_api_ret_t rtk_qos_priMap_get(rtk_queue_num_t queue_num, rtk_qos_pri2queue_t *pPri2qid); + +/* Function Name: + * rtk_qos_schedulingQueue_set + * Description: + * Set weight and type of queues in dedicated port. + * Input: + * port - Port id. + * pQweights - The array of weights for WRR/WFQ queue (0 for STRICT_PRIORITY queue). + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_QOS_QUEUE_WEIGHT - Invalid queue weight. + * Note: + * The API can set weight and type, strict priority or weight fair queue (WFQ) for + * dedicated port for using queues. If queue id is not included in queue usage, + * then its type and weight setting in dummy for setting. There are priorities + * as queue id in strict queues. It means strict queue id 5 carrying higher priority + * than strict queue id 4. The WFQ queue weight is from 1 to 128, and weight 0 is + * for strict priority queue type. + */ +extern rtk_api_ret_t rtk_qos_schedulingQueue_set(rtk_port_t port, rtk_qos_queue_weights_t *pQweights); + +/* Function Name: + * rtk_qos_schedulingQueue_get + * Description: + * Get weight and type of queues in dedicated port. + * Input: + * port - Port id. + * Output: + * pQweights - The array of weights for WRR/WFQ queue (0 for STRICT_PRIORITY queue). + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get weight and type, strict priority or weight fair queue (WFQ) for dedicated port for using queues. + * The WFQ queue weight is from 1 to 128, and weight 0 is for strict priority queue type. + */ +extern rtk_api_ret_t rtk_qos_schedulingQueue_get(rtk_port_t port, rtk_qos_queue_weights_t *pQweights); + +/* Function Name: + * rtk_qos_1pRemarkEnable_set + * Description: + * Set 1p Remarking state + * Input: + * port - Port id. + * enable - State of per-port 1p Remarking + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable parameter. + * Note: + * The API can enable or disable 802.1p remarking ability for whole system. + * The status of 802.1p remark: + * - DISABLED + * - ENABLED + */ +extern rtk_api_ret_t rtk_qos_1pRemarkEnable_set(rtk_port_t port, rtk_enable_t enable); + +/* Function Name: + * rtk_qos_1pRemarkEnable_get + * Description: + * Get 802.1p remarking ability. + * Input: + * port - Port id. + * Output: + * pEnable - Status of 802.1p remark. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get 802.1p remarking ability. + * The status of 802.1p remark: + * - DISABLED + * - ENABLED + */ +extern rtk_api_ret_t rtk_qos_1pRemarkEnable_get(rtk_port_t port, rtk_enable_t *pEnable); + +/* Function Name: + * rtk_qos_1pRemark_set + * Description: + * Set 802.1p remarking parameter. + * Input: + * int_pri - Internal priority value. + * dot1p_pri - 802.1p priority value. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_VLAN_PRIORITY - Invalid 1p priority. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * The API can set 802.1p parameters source priority and new priority. + */ +extern rtk_api_ret_t rtk_qos_1pRemark_set(rtk_pri_t int_pri, rtk_pri_t dot1p_pri); + +/* Function Name: + * rtk_qos_1pRemark_get + * Description: + * Get 802.1p remarking parameter. + * Input: + * int_pri - Internal priority value. + * Output: + * pDot1p_pri - 802.1p priority value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * The API can get 802.1p remarking parameters. It would return new priority of ingress priority. + */ +extern rtk_api_ret_t rtk_qos_1pRemark_get(rtk_pri_t int_pri, rtk_pri_t *pDot1p_pri); + +/* Function Name: + * rtk_qos_dscpRemarkEnable_set + * Description: + * Set DSCP remarking ability. + * Input: + * port - Port id. + * enable - status of DSCP remark. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * RT_ERR_ENABLE - Invalid enable parameter. + * Note: + * The API can enable or disable DSCP remarking ability for whole system. + * The status of DSCP remark: + * - DISABLED + * - ENABLED + */ +extern rtk_api_ret_t rtk_qos_dscpRemarkEnable_set(rtk_port_t port, rtk_enable_t enable); + +/* Function Name: + * rtk_qos_dscpRemarkEnable_get + * Description: + * Get DSCP remarking ability. + * Input: + * port - Port id. + * Output: + * pEnable - status of DSCP remarking. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get DSCP remarking ability. + * The status of DSCP remark: + * - DISABLED + * - ENABLED + */ +extern rtk_api_ret_t rtk_qos_dscpRemarkEnable_get(rtk_port_t port, rtk_enable_t *pEnable); + +/* Function Name: + * rtk_qos_dscpRemark_set + * Description: + * Set DSCP remarking parameter. + * Input: + * int_pri - Internal priority value. + * dscp - DSCP value. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * RT_ERR_QOS_DSCP_VALUE - Invalid DSCP value. + * Note: + * The API can set DSCP value and mapping priority. + */ +extern rtk_api_ret_t rtk_qos_dscpRemark_set(rtk_pri_t int_pri, rtk_dscp_t dscp); + +/* Function Name: + * rtk_qos_dscpRemark_get + * Description: + * Get DSCP remarking parameter. + * Input: + * int_pri - Internal priority value. + * Output: + * Dscp - DSCP value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * The API can get DSCP parameters. It would return DSCP value for mapping priority. + */ +extern rtk_api_ret_t rtk_qos_dscpRemark_get(rtk_pri_t int_pri, rtk_dscp_t *pDscp); + +/* Function Name: + * rtk_qos_dscpRemarkSrcSel_set + * Description: + * Set remarking source of DSCP remarking. + * Input: + * type - remarking source + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + + * Note: + * The API can configure DSCP remark functionality to map original DSCP value or internal + * priority to TX DSCP value. + */ +extern rtk_api_ret_t rtk_qos_dscpRemarkSrcSel_set(rtk_qos_dscpRmkSrc_t type); + + +/* Function Name: + * rtk_qos_dcpRemarkSrcSel_get + * Description: + * Get remarking source of DSCP remarking. + * Input: + * none + * Output: + * pType - remarking source + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * RT_ERR_NULL_POINTER - input parameter may be null pointer + + * Note: + * None + */ +extern rtk_api_ret_t rtk_qos_dscpRemarkSrcSel_get(rtk_qos_dscpRmkSrc_t *pType); + + +/* Function Name: + * rtk_qos_dscpRemark2Dscp_set + * Description: + * Set DSCP to remarked DSCP mapping. + * Input: + * dscp - DSCP value + * rmkDscp - remarked DSCP value + * Output: + * None. + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_QOS_DSCP_VALUE - Invalid dscp value + * Note: + * dscp parameter can be DSCP value or internal priority according to configuration of API + * dal_apollomp_qos_dscpRemarkSrcSel_set(), because DSCP remark functionality can map original DSCP + * value or internal priority to TX DSCP value. + */ +extern rtk_api_ret_t rtk_qos_dscpRemark2Dscp_set(rtk_dscp_t dscp, rtk_dscp_t rmkDscp); + +/* Function Name: + * rtk_qos_dscpRemark2Dscp_get + * Description: + * Get DSCP to remarked DSCP mapping. + * Input: + * dscp - DSCP value + * Output: + * pDscp - remarked DSCP value + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_QOS_DSCP_VALUE - Invalid dscp value + * RT_ERR_NULL_POINTER - NULL pointer + * Note: + * None. + */ +extern rtk_api_ret_t rtk_qos_dscpRemark2Dscp_get(rtk_dscp_t dscp, rtk_dscp_t *pDscp); + +/* Function Name: + * rtk_qos_portPriSelIndex_set + * Description: + * Configure priority decision index to each port. + * Input: + * port - Port id. + * index - priority decision index. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENTRY_INDEX - Invalid entry index. + * Note: + * The API can set priority of port assignments for queue usage and packet scheduling. + */ +extern rtk_api_ret_t rtk_qos_portPriSelIndex_set(rtk_port_t port, rtk_qos_priDecTbl_t index); + +/* Function Name: + * rtk_qos_portPriSelIndex_get + * Description: + * Get priority decision index from each port. + * Input: + * port - Port id. + * Output: + * pIndex - priority decision index. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get priority of port assignments for queue usage and packet scheduling. + */ +extern rtk_api_ret_t rtk_qos_portPriSelIndex_get(rtk_port_t port, rtk_qos_priDecTbl_t *pIndex); + +/* Function Name: + * rtk_qos_schedulingType_set + * Description: + * Configure type of scheduling. + * Input: + * queueType - Scheduling type. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_SCHE_TYPE - Invalid QoS scheduling type. + * Note: + * The API can set type of scheduling. + */ +extern rtk_api_ret_t rtk_qos_schedulingType_set(rtk_qos_scheduling_type_t queueType); + +/* Function Name: + * rtk_qos_schedulingType_get + * Description: + * Get type of scheduling. + * Input: + * none. + * Output: + * pIndex - priority decision index. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - NULL pointer + * Note: + * The API can get type of scheduling. + */ +extern rtk_api_ret_t rtk_qos_schedulingType_get(rtk_qos_scheduling_type_t *pQueueType); + +#endif /* __RTK_API_QOS_H__ */ diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/rate.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/rate.c new file mode 100644 index 00000000..438cfbe3 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/rate.c @@ -0,0 +1,433 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8367C + * Feature : Here is a list of all functions and variables in rate module. + * + */ + +#include +#include +#include +#include +#include + +#include + +/* Function Name: + * rtk_rate_shareMeter_set + * Description: + * Set meter configuration + * Input: + * index - shared meter index + * type - shared meter type + * rate - rate of share meter + * ifg_include - include IFG or not, ENABLE:include DISABLE:exclude + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_METER_ID - Invalid meter + * RT_ERR_RATE - Invalid rate + * RT_ERR_INPUT - Invalid input parameters + * Note: + * The API can set shared meter rate and ifg include for each meter. + * The rate unit is 1 kbps and the range is from 8k to 1048568k if type is METER_TYPE_KBPS and + * the granularity of rate is 8 kbps. + * The rate unit is packets per second and the range is 1 ~ 0x1FFF if type is METER_TYPE_PPS. + * The ifg_include parameter is used + * for rate calculation with/without inter-frame-gap and preamble. + */ +rtk_api_ret_t rtk_rate_shareMeter_set(rtk_meter_id_t index, rtk_meter_type_t type, rtk_rate_t rate, rtk_enable_t ifg_include) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rate_shareMeter_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rate_shareMeter_set(index, type, rate, ifg_include); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_rate_shareMeter_get + * Description: + * Get meter configuration + * Input: + * index - shared meter index + * Output: + * pType - Meter Type + * pRate - pointer of rate of share meter + * pIfg_include - include IFG or not, ENABLE:include DISABLE:exclude + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_METER_ID - Invalid meter + * Note: + * + */ +rtk_api_ret_t rtk_rate_shareMeter_get(rtk_meter_id_t index, rtk_meter_type_t *pType, rtk_rate_t *pRate, rtk_enable_t *pIfg_include) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rate_shareMeter_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rate_shareMeter_get(index, pType, pRate, pIfg_include); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_rate_shareMeterBucket_set + * Description: + * Set meter Bucket Size + * Input: + * index - shared meter index + * bucket_size - Bucket Size + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_INPUT - Error Input + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_METER_ID - Invalid meter + * Note: + * The API can set shared meter bucket size. + */ +rtk_api_ret_t rtk_rate_shareMeterBucket_set(rtk_meter_id_t index, rtk_uint32 bucket_size) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rate_shareMeterBucket_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rate_shareMeterBucket_set(index, bucket_size); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_rate_shareMeterBucket_get + * Description: + * Get meter Bucket Size + * Input: + * index - shared meter index + * Output: + * pBucket_size - Bucket Size + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_METER_ID - Invalid meter + * Note: + * The API can get shared meter bucket size. + */ +rtk_api_ret_t rtk_rate_shareMeterBucket_get(rtk_meter_id_t index, rtk_uint32 *pBucket_size) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rate_shareMeterBucket_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rate_shareMeterBucket_get(index, pBucket_size); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_rate_igrBandwidthCtrlRate_set + * Description: + * Set port ingress bandwidth control + * Input: + * port - Port id + * rate - Rate of share meter + * ifg_include - include IFG or not, ENABLE:include DISABLE:exclude + * fc_enable - enable flow control or not, ENABLE:use flow control DISABLE:drop + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid IFG parameter. + * RT_ERR_INBW_RATE - Invalid ingress rate parameter. + * Note: + * The rate unit is 1 kbps and the range is from 8k to 1048568k. The granularity of rate is 8 kbps. + * The ifg_include parameter is used for rate calculation with/without inter-frame-gap and preamble. + */ +rtk_api_ret_t rtk_rate_igrBandwidthCtrlRate_set(rtk_port_t port, rtk_rate_t rate, rtk_enable_t ifg_include, rtk_enable_t fc_enable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rate_igrBandwidthCtrlRate_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rate_igrBandwidthCtrlRate_set(port, rate, ifg_include, fc_enable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_rate_igrBandwidthCtrlRate_get + * Description: + * Get port ingress bandwidth control + * Input: + * port - Port id + * Output: + * pRate - Rate of share meter + * pIfg_include - Rate's calculation including IFG, ENABLE:include DISABLE:exclude + * pFc_enable - enable flow control or not, ENABLE:use flow control DISABLE:drop + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The rate unit is 1 kbps and the range is from 8k to 1048568k. The granularity of rate is 8 kbps. + * The ifg_include parameter is used for rate calculation with/without inter-frame-gap and preamble. + */ +rtk_api_ret_t rtk_rate_igrBandwidthCtrlRate_get(rtk_port_t port, rtk_rate_t *pRate, rtk_enable_t *pIfg_include, rtk_enable_t *pFc_enable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rate_igrBandwidthCtrlRate_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rate_igrBandwidthCtrlRate_get(port, pRate, pIfg_include, pFc_enable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_rate_egrBandwidthCtrlRate_set + * Description: + * Set port egress bandwidth control + * Input: + * port - Port id + * rate - Rate of egress bandwidth + * ifg_include - include IFG or not, ENABLE:include DISABLE:exclude + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_QOS_EBW_RATE - Invalid egress bandwidth/rate + * Note: + * The rate unit is 1 kbps and the range is from 8k to 1048568k. The granularity of rate is 8 kbps. + * The ifg_include parameter is used for rate calculation with/without inter-frame-gap and preamble. + */ +rtk_api_ret_t rtk_rate_egrBandwidthCtrlRate_set( rtk_port_t port, rtk_rate_t rate, rtk_enable_t ifg_include) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rate_egrBandwidthCtrlRate_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rate_egrBandwidthCtrlRate_set(port, rate, ifg_include); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_rate_egrBandwidthCtrlRate_get + * Description: + * Get port egress bandwidth control + * Input: + * port - Port id + * Output: + * pRate - Rate of egress bandwidth + * pIfg_include - Rate's calculation including IFG, ENABLE:include DISABLE:exclude + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The rate unit is 1 kbps and the range is from 8k to 1048568k. The granularity of rate is 8 kbps. + * The ifg_include parameter is used for rate calculation with/without inter-frame-gap and preamble. + */ +rtk_api_ret_t rtk_rate_egrBandwidthCtrlRate_get(rtk_port_t port, rtk_rate_t *pRate, rtk_enable_t *pIfg_include) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rate_egrBandwidthCtrlRate_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rate_egrBandwidthCtrlRate_get(port, pRate, pIfg_include); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_rate_egrQueueBwCtrlEnable_get + * Description: + * Get enable status of egress bandwidth control on specified queue. + * Input: + * unit - unit id + * port - port id + * queue - queue id + * Output: + * pEnable - Pointer to enable status of egress queue bandwidth control + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_QUEUE_ID - invalid queue id + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None + */ +rtk_api_ret_t rtk_rate_egrQueueBwCtrlEnable_get(rtk_port_t port, rtk_qid_t queue, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rate_egrQueueBwCtrlEnable_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rate_egrQueueBwCtrlEnable_get(port, queue, pEnable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_rate_egrQueueBwCtrlEnable_set + * Description: + * Set enable status of egress bandwidth control on specified queue. + * Input: + * port - port id + * queue - queue id + * enable - enable status of egress queue bandwidth control + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_QUEUE_ID - invalid queue id + * RT_ERR_INPUT - invalid input parameter + * Note: + * None + */ +rtk_api_ret_t rtk_rate_egrQueueBwCtrlEnable_set(rtk_port_t port, rtk_qid_t queue, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rate_egrQueueBwCtrlEnable_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rate_egrQueueBwCtrlEnable_set(port, queue, enable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_rate_egrQueueBwCtrlRate_get + * Description: + * Get rate of egress bandwidth control on specified queue. + * Input: + * port - port id + * queue - queue id + * pIndex - shared meter index + * Output: + * pRate - pointer to rate of egress queue bandwidth control + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_QUEUE_ID - invalid queue id + * RT_ERR_FILTER_METER_ID - Invalid meter id + * Note: + * The actual rate control is set in shared meters. + * The unit of granularity is 8Kbps. + */ +rtk_api_ret_t rtk_rate_egrQueueBwCtrlRate_get(rtk_port_t port, rtk_qid_t queue, rtk_meter_id_t *pIndex) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rate_egrQueueBwCtrlRate_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rate_egrQueueBwCtrlRate_get(port, queue, pIndex); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_rate_egrQueueBwCtrlRate_set + * Description: + * Set rate of egress bandwidth control on specified queue. + * Input: + * port - port id + * queue - queue id + * index - shared meter index + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_QUEUE_ID - invalid queue id + * RT_ERR_FILTER_METER_ID - Invalid meter id + * Note: + * The actual rate control is set in shared meters. + * The unit of granularity is 8Kbps. + */ +rtk_api_ret_t rtk_rate_egrQueueBwCtrlRate_set(rtk_port_t port, rtk_qid_t queue, rtk_meter_id_t index) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rate_egrQueueBwCtrlRate_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rate_egrQueueBwCtrlRate_set(port, queue, index); + RTK_API_UNLOCK(); + + return retVal; +} + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/rate.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/rate.h new file mode 100644 index 00000000..72e048f9 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/rate.h @@ -0,0 +1,304 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8367/RTL8367C switch high-level API + * + * Feature : The file includes rate module high-layer API defination + * + */ + +#ifndef __RTK_API_RATE_H__ +#define __RTK_API_RATE_H__ + +/* + * Include Files + */ +//#include + +/* + * Data Type Declaration + */ +typedef enum rtk_meter_type_e{ + METER_TYPE_KBPS = 0, /* Kbps */ + METER_TYPE_PPS, /* Packet per second */ + METER_TYPE_END +}rtk_meter_type_t; + + +/* + * Function Declaration + */ + + /* Rate */ +/* Function Name: + * rtk_rate_shareMeter_set + * Description: + * Set meter configuration + * Input: + * index - shared meter index + * type - shared meter type + * rate - rate of share meter + * ifg_include - include IFG or not, ENABLE:include DISABLE:exclude + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_METER_ID - Invalid meter + * RT_ERR_RATE - Invalid rate + * RT_ERR_INPUT - Invalid input parameters + * Note: + * The API can set shared meter rate and ifg include for each meter. + * The rate unit is 1 kbps and the range is from 8k to 1048568k if type is METER_TYPE_KBPS and + * the granularity of rate is 8 kbps. + * The rate unit is packets per second and the range is 1 ~ 0x1FFF if type is METER_TYPE_PPS. + * The ifg_include parameter is used + * for rate calculation with/without inter-frame-gap and preamble. + */ +extern rtk_api_ret_t rtk_rate_shareMeter_set(rtk_meter_id_t index, rtk_meter_type_t type, rtk_rate_t rate, rtk_enable_t ifg_include); + +/* Function Name: + * rtk_rate_shareMeter_get + * Description: + * Get meter configuration + * Input: + * index - shared meter index + * Output: + * pType - Meter Type + * pRate - pointer of rate of share meter + * pIfg_include - include IFG or not, ENABLE:include DISABLE:exclude + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_METER_ID - Invalid meter + * Note: + * + */ +extern rtk_api_ret_t rtk_rate_shareMeter_get(rtk_meter_id_t index, rtk_meter_type_t *pType, rtk_rate_t *pRate, rtk_enable_t *pIfg_include); + +/* Function Name: + * rtk_rate_shareMeterBucket_set + * Description: + * Set meter Bucket Size + * Input: + * index - shared meter index + * bucket_size - Bucket Size + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_INPUT - Error Input + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_METER_ID - Invalid meter + * Note: + * The API can set shared meter bucket size. + */ +extern rtk_api_ret_t rtk_rate_shareMeterBucket_set(rtk_meter_id_t index, rtk_uint32 bucket_size); + +/* Function Name: + * rtk_rate_shareMeterBucket_get + * Description: + * Get meter Bucket Size + * Input: + * index - shared meter index + * Output: + * pBucket_size - Bucket Size + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_METER_ID - Invalid meter + * Note: + * The API can get shared meter bucket size. + */ +extern rtk_api_ret_t rtk_rate_shareMeterBucket_get(rtk_meter_id_t index, rtk_uint32 *pBucket_size); + +/* Function Name: + * rtk_rate_igrBandwidthCtrlRate_set + * Description: + * Set port ingress bandwidth control + * Input: + * port - Port id + * rate - Rate of share meter + * ifg_include - include IFG or not, ENABLE:include DISABLE:exclude + * fc_enable - enable flow control or not, ENABLE:use flow control DISABLE:drop + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid IFG parameter. + * RT_ERR_INBW_RATE - Invalid ingress rate parameter. + * Note: + * The rate unit is 1 kbps and the range is from 8k to 1048568k. The granularity of rate is 8 kbps. + * The ifg_include parameter is used for rate calculation with/without inter-frame-gap and preamble. + */ +extern rtk_api_ret_t rtk_rate_igrBandwidthCtrlRate_set( rtk_port_t port, rtk_rate_t rate, rtk_enable_t ifg_include, rtk_enable_t fc_enable); + +/* Function Name: + * rtk_rate_igrBandwidthCtrlRate_get + * Description: + * Get port ingress bandwidth control + * Input: + * port - Port id + * Output: + * pRate - Rate of share meter + * pIfg_include - Rate's calculation including IFG, ENABLE:include DISABLE:exclude + * pFc_enable - enable flow control or not, ENABLE:use flow control DISABLE:drop + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The rate unit is 1 kbps and the range is from 8k to 1048568k. The granularity of rate is 8 kbps. + * The ifg_include parameter is used for rate calculation with/without inter-frame-gap and preamble. + */ +extern rtk_api_ret_t rtk_rate_igrBandwidthCtrlRate_get(rtk_port_t port, rtk_rate_t *pRate, rtk_enable_t *pIfg_include, rtk_enable_t *pFc_enable); + +/* Function Name: + * rtk_rate_egrBandwidthCtrlRate_set + * Description: + * Set port egress bandwidth control + * Input: + * port - Port id + * rate - Rate of egress bandwidth + * ifg_include - include IFG or not, ENABLE:include DISABLE:exclude + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_QOS_EBW_RATE - Invalid egress bandwidth/rate + * Note: + * The rate unit is 1 kbps and the range is from 8k to 1048568k. The granularity of rate is 8 kbps. + * The ifg_include parameter is used for rate calculation with/without inter-frame-gap and preamble. + */ +extern rtk_api_ret_t rtk_rate_egrBandwidthCtrlRate_set(rtk_port_t port, rtk_rate_t rate, rtk_enable_t ifg_includ); + +/* Function Name: + * rtk_rate_egrBandwidthCtrlRate_get + * Description: + * Get port egress bandwidth control + * Input: + * port - Port id + * Output: + * pRate - Rate of egress bandwidth + * pIfg_include - Rate's calculation including IFG, ENABLE:include DISABLE:exclude + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The rate unit is 1 kbps and the range is from 8k to 1048568k. The granularity of rate is 8 kbps. + * The ifg_include parameter is used for rate calculation with/without inter-frame-gap and preamble. + */ +extern rtk_api_ret_t rtk_rate_egrBandwidthCtrlRate_get(rtk_port_t port, rtk_rate_t *pRate, rtk_enable_t *pIfg_include); + +/* Function Name: + * rtk_rate_egrQueueBwCtrlEnable_set + * Description: + * Set enable status of egress bandwidth control on specified queue. + * Input: + * port - port id + * queue - queue id + * enable - enable status of egress queue bandwidth control + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_QUEUE_ID - invalid queue id + * RT_ERR_INPUT - invalid input parameter + * Note: + * None + */ +extern rtk_api_ret_t rtk_rate_egrQueueBwCtrlEnable_set(rtk_port_t port, rtk_qid_t queue, rtk_enable_t enable); + +/* Function Name: + * rtk_rate_egrQueueBwCtrlRate_get + * Description: + * Get rate of egress bandwidth control on specified queue. + * Input: + * port - port id + * queue - queue id + * pIndex - shared meter index + * Output: + * pRate - pointer to rate of egress queue bandwidth control + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_QUEUE_ID - invalid queue id + * RT_ERR_FILTER_METER_ID - Invalid meter id + * Note: + * None. + */ +extern rtk_api_ret_t rtk_rate_egrQueueBwCtrlEnable_get(rtk_port_t port, rtk_qid_t queue, rtk_enable_t *pEnable); + +/* Function Name: + * rtk_rate_egrQueueBwCtrlRate_set + * Description: + * Set rate of egress bandwidth control on specified queue. + * Input: + * port - port id + * queue - queue id + * index - shared meter index + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_QUEUE_ID - invalid queue id + * RT_ERR_FILTER_METER_ID - Invalid meter id + * Note: + * The actual rate control is set in shared meters. + * The unit of granularity is 8Kbps. + */ +extern rtk_api_ret_t rtk_rate_egrQueueBwCtrlRate_set(rtk_port_t port, rtk_qid_t queue, rtk_meter_id_t index); + +/* Function Name: + * rtk_rate_egrQueueBwCtrlRate_get + * Description: + * Get rate of egress bandwidth control on specified queue. + * Input: + * port - port id + * queue - queue id + * pIndex - shared meter index + * Output: + * pRate - pointer to rate of egress queue bandwidth control + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_QUEUE_ID - invalid queue id + * RT_ERR_FILTER_METER_ID - Invalid meter id + * Note: + * The actual rate control is set in shared meters. + * The unit of granularity is 8Kbps. + */ +extern rtk_api_ret_t rtk_rate_egrQueueBwCtrlRate_get(rtk_port_t port, rtk_qid_t queue, rtk_meter_id_t *pIndex); + +#endif /* __RTK_API_RATE_H__ */ + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/rldp.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/rldp.c new file mode 100644 index 00000000..dd77ea4d --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/rldp.c @@ -0,0 +1,278 @@ +/* + * Copyright (C) 2012 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision: $ + * $Date: $ + * + * Purpose : Declaration of RLDP and RLPP API + * + * Feature : The file have include the following module and sub-modules + * 1) RLDP and RLPP configuration and status + * + */ + + +/* + * Include Files + */ +#include +#include + +#include + + +/* Function Name: + * rtk_rldp_config_set + * Description: + * Set RLDP module configuration + * Input: + * pConfig - configuration structure of RLDP + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT + * RT_ERR_NULL_POINTER + * Note: + * None + */ +rtk_api_ret_t rtk_rldp_config_set(rtk_rldp_config_t *pConfig) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rldp_config_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rldp_config_set(pConfig); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_rldp_config_get + * Description: + * Get RLDP module configuration + * Input: + * None + * Output: + * pConfig - configuration structure of RLDP + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT + * RT_ERR_NULL_POINTER + * Note: + * None + */ +rtk_api_ret_t rtk_rldp_config_get(rtk_rldp_config_t *pConfig) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rldp_config_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rldp_config_get(pConfig); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_rldp_portConfig_set + * Description: + * Set per port RLDP module configuration + * Input: + * port - port number to be configured + * pPortConfig - per port configuration structure of RLDP + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT + * RT_ERR_NULL_POINTER + * Note: + * None + */ +rtk_api_ret_t rtk_rldp_portConfig_set(rtk_port_t port, rtk_rldp_portConfig_t *pPortConfig) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rldp_portConfig_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rldp_portConfig_set(port, pPortConfig); + RTK_API_UNLOCK(); + + return retVal; +} /* end of rtk_rldp_portConfig_set */ + + +/* Function Name: + * rtk_rldp_portConfig_get + * Description: + * Get per port RLDP module configuration + * Input: + * port - port number to be get + * Output: + * pPortConfig - per port configuration structure of RLDP + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT + * RT_ERR_NULL_POINTER + * Note: + * None + */ +rtk_api_ret_t rtk_rldp_portConfig_get(rtk_port_t port, rtk_rldp_portConfig_t *pPortConfig) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rldp_portConfig_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rldp_portConfig_get(port, pPortConfig); + RTK_API_UNLOCK(); + + return retVal; +} /* end of rtk_rldp_portConfig_get */ + + +/* Function Name: + * rtk_rldp_status_get + * Description: + * Get RLDP module status + * Input: + * None + * Output: + * pStatus - status structure of RLDP + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NULL_POINTER + * Note: + * None + */ +rtk_api_ret_t rtk_rldp_status_get(rtk_rldp_status_t *pStatus) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rldp_status_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rldp_status_get(pStatus); + RTK_API_UNLOCK(); + + return retVal; +} /* end of rtk_rldp_status_get */ + + +/* Function Name: + * rtk_rldp_portStatus_get + * Description: + * Get RLDP module status + * Input: + * port - port number to be get + * Output: + * pPortStatus - per port status structure of RLDP + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT + * RT_ERR_NULL_POINTER + * Note: + * None + */ +rtk_api_ret_t rtk_rldp_portStatus_get(rtk_port_t port, rtk_rldp_portStatus_t *pPortStatus) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rldp_portStatus_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rldp_portStatus_get(port, pPortStatus); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_rldp_portStatus_set + * Description: + * Clear RLDP module status + * Input: + * port - port number to be clear + * pPortStatus - per port status structure of RLDP + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT + * RT_ERR_NULL_POINTER + * Note: + * Clear operation effect loop_enter and loop_leave only, other field in + * the structure are don't care. Loop status cab't be clean. + */ +rtk_api_ret_t rtk_rldp_portStatus_set(rtk_port_t port, rtk_rldp_portStatus_t *pPortStatus) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rldp_portStatus_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rldp_portStatus_set(port, pPortStatus); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_rldp_portLoopPair_get + * Description: + * Get RLDP port loop pairs + * Input: + * port - port number to be get + * Output: + * pPortmask - per port related loop ports + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT + * RT_ERR_NULL_POINTER + * Note: + * None + */ +rtk_api_ret_t rtk_rldp_portLoopPair_get(rtk_port_t port, rtk_portmask_t *pPortmask) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rldp_portLoopPair_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rldp_portLoopPair_get(port, pPortmask); + RTK_API_UNLOCK(); + + return retVal; +} + + + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/rldp.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/rldp.h new file mode 100644 index 00000000..3b42accc --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/rldp.h @@ -0,0 +1,266 @@ +/* + * Copyright (C) 2012 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision: $ + * $Date: $ + * + * Purpose : Declaration of RLDP and RLPP API + * + * Feature : The file have include the following module and sub-modules + * 1) RLDP and RLPP configuration and status + * + */ + + +#ifndef __RTK_RLDP_H__ +#define __RTK_RLDP_H__ + + +/* + * Include Files + */ + + +/* + * Symbol Definition + */ +typedef enum rtk_rldp_trigger_e +{ + RTK_RLDP_TRIGGER_SAMOVING = 0, + RTK_RLDP_TRIGGER_PERIOD, + RTK_RLDP_TRIGGER_END +} rtk_rldp_trigger_t; + +typedef enum rtk_rldp_cmpType_e +{ + RTK_RLDP_CMPTYPE_MAGIC = 0, /* Compare the RLDP with magic only */ + RTK_RLDP_CMPTYPE_MAGIC_ID, /* Compare the RLDP with both magic + ID */ + RTK_RLDP_CMPTYPE_END +} rtk_rldp_cmpType_t; + +typedef enum rtk_rldp_loopStatus_e +{ + RTK_RLDP_LOOPSTS_NONE = 0, + RTK_RLDP_LOOPSTS_LOOPING, + RTK_RLDP_LOOPSTS_END +} rtk_rldp_loopStatus_t; + +typedef enum rtk_rlpp_trapType_e +{ + RTK_RLPP_TRAPTYPE_NONE = 0, + RTK_RLPP_TRAPTYPE_CPU, + RTK_RLPP_TRAPTYPE_END +} rtk_rlpp_trapType_t; + +typedef struct rtk_rldp_config_s +{ + rtk_enable_t rldp_enable; + rtk_rldp_trigger_t trigger_mode; + rtk_mac_t magic; + rtk_rldp_cmpType_t compare_type; + rtk_uint32 interval_check; /* Checking interval for check state */ + rtk_uint32 num_check; /* Checking number for check state */ + rtk_uint32 interval_loop; /* Checking interval for loop state */ + rtk_uint32 num_loop; /* Checking number for loop state */ +} rtk_rldp_config_t; + +typedef struct rtk_rldp_portConfig_s +{ + rtk_enable_t tx_enable; +} rtk_rldp_portConfig_t; + +typedef struct rtk_rldp_status_s +{ + rtk_mac_t id; +} rtk_rldp_status_t; + +typedef struct rtk_rldp_portStatus_s +{ + rtk_rldp_loopStatus_t loop_status; + rtk_rldp_loopStatus_t loop_enter; + rtk_rldp_loopStatus_t loop_leave; +} rtk_rldp_portStatus_t; + +/* + * Data Declaration + */ + + +/* + * Macro Declaration + */ + +#define RTK_RLDP_INTERVAL_MAX 0xffff +#define RTK_RLDP_NUM_MAX 0xff + + +/* + * Function Declaration + */ + +/* Module Name : RLDP */ + + +/* Function Name: + * rtk_rldp_config_set + * Description: + * Set RLDP module configuration + * Input: + * pConfig - configuration structure of RLDP + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT + * RT_ERR_NULL_POINTER + * Note: + * None + */ +extern rtk_api_ret_t rtk_rldp_config_set(rtk_rldp_config_t *pConfig); + + +/* Function Name: + * rtk_rldp_config_get + * Description: + * Get RLDP module configuration + * Input: + * None + * Output: + * pConfig - configuration structure of RLDP + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT + * RT_ERR_NULL_POINTER + * Note: + * None + */ +extern rtk_api_ret_t rtk_rldp_config_get(rtk_rldp_config_t *pConfig); + + +/* Function Name: + * rtk_rldp_portConfig_set + * Description: + * Set per port RLDP module configuration + * Input: + * port - port number to be configured + * pPortConfig - per port configuration structure of RLDP + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT + * RT_ERR_NULL_POINTER + * Note: + * None + */ +extern rtk_api_ret_t rtk_rldp_portConfig_set(rtk_port_t port, rtk_rldp_portConfig_t *pPortConfig); + + +/* Function Name: + * rtk_rldp_portConfig_get + * Description: + * Get per port RLDP module configuration + * Input: + * port - port number to be get + * Output: + * pPortConfig - per port configuration structure of RLDP + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT + * RT_ERR_NULL_POINTER + * Note: + * None + */ +extern rtk_api_ret_t rtk_rldp_portConfig_get(rtk_port_t port, rtk_rldp_portConfig_t *pPortConfig); + + +/* Function Name: + * rtk_rldp_status_get + * Description: + * Get RLDP module status + * Input: + * None + * Output: + * pStatus - status structure of RLDP + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NULL_POINTER + * Note: + * None + */ +extern rtk_api_ret_t rtk_rldp_status_get(rtk_rldp_status_t *pStatus); + + +/* Function Name: + * rtk_rldp_portStatus_get + * Description: + * Get RLDP module status + * Input: + * port - port number to be get + * Output: + * pPortStatus - per port status structure of RLDP + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT + * RT_ERR_NULL_POINTER + * Note: + * None + */ +extern rtk_api_ret_t rtk_rldp_portStatus_get(rtk_port_t port, rtk_rldp_portStatus_t *pPortStatus); + + +/* Function Name: + * rtk_rldp_portStatus_clear + * Description: + * Clear RLDP module status + * Input: + * port - port number to be clear + * pPortStatus - per port status structure of RLDP + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT + * RT_ERR_NULL_POINTER + * Note: + * Clear operation effect loop_enter and loop_leave only, other field in + * the structure are don't care + */ +extern rtk_api_ret_t rtk_rldp_portStatus_set(rtk_port_t port, rtk_rldp_portStatus_t *pPortStatus); + + +/* Function Name: + * rtk_rldp_portLoopPair_get + * Description: + * Get RLDP port loop pairs + * Input: + * port - port number to be get + * Output: + * pPortmask - per port related loop ports + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT + * RT_ERR_NULL_POINTER + * Note: + * None + */ +extern rtk_api_ret_t rtk_rldp_portLoopPair_get(rtk_port_t port, rtk_portmask_t *pPortmask); + +#endif /* __RTK_RLDP_H__ */ + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/rtk_error.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/rtk_error.h new file mode 100644 index 00000000..c4f1c7d6 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/rtk_error.h @@ -0,0 +1,225 @@ +/* + * Copyright(c) Realtek Semiconductor Corporation, 2008 + * All rights reserved. + * + * $Revision$ + * $Date$ + * + * Purpose : Definition the error number in the SDK. + * + * Feature : error definition + * + */ + +#ifndef __COMMON_RT_ERROR_H__ +#define __COMMON_RT_ERROR_H__ + +/* + * Include Files + */ + +/* + * Data Type Declaration + */ +typedef enum rt_error_code_e +{ + RT_ERR_FAILED = -1, /* General Error */ + + /* 0x0000xxxx for common error code */ + RT_ERR_OK = 0, /* 0x00000000, OK */ + RT_ERR_INPUT, /* 0x00000001, invalid input parameter */ + RT_ERR_UNIT_ID, /* 0x00000002, invalid unit id */ + RT_ERR_PORT_ID, /* 0x00000003, invalid port id */ + RT_ERR_PORT_MASK, /* 0x00000004, invalid port mask */ + RT_ERR_PORT_LINKDOWN, /* 0x00000005, link down port status */ + RT_ERR_ENTRY_INDEX, /* 0x00000006, invalid entry index */ + RT_ERR_NULL_POINTER, /* 0x00000007, input parameter is null pointer */ + RT_ERR_QUEUE_ID, /* 0x00000008, invalid queue id */ + RT_ERR_QUEUE_NUM, /* 0x00000009, invalid queue number */ + RT_ERR_BUSYWAIT_TIMEOUT, /* 0x0000000a, busy watting time out */ + RT_ERR_MAC, /* 0x0000000b, invalid mac address */ + RT_ERR_OUT_OF_RANGE, /* 0x0000000c, input parameter out of range */ + RT_ERR_CHIP_NOT_SUPPORTED, /* 0x0000000d, functions not supported by this chip model */ + RT_ERR_SMI, /* 0x0000000e, SMI error */ + RT_ERR_NOT_INIT, /* 0x0000000f, The module is not initial */ + RT_ERR_CHIP_NOT_FOUND, /* 0x00000010, The chip can not found */ + RT_ERR_NOT_ALLOWED, /* 0x00000011, actions not allowed by the function */ + RT_ERR_DRIVER_NOT_FOUND, /* 0x00000012, The driver can not found */ + RT_ERR_SEM_LOCK_FAILED, /* 0x00000013, Failed to lock semaphore */ + RT_ERR_SEM_UNLOCK_FAILED, /* 0x00000014, Failed to unlock semaphore */ + RT_ERR_ENABLE, /* 0x00000015, invalid enable parameter */ + RT_ERR_TBL_FULL, /* 0x00000016, input table full */ + + /* 0x0001xxxx for vlan */ + RT_ERR_VLAN_VID = 0x00010000, /* 0x00010000, invalid vid */ + RT_ERR_VLAN_PRIORITY, /* 0x00010001, invalid 1p priority */ + RT_ERR_VLAN_EMPTY_ENTRY, /* 0x00010002, emtpy entry of vlan table */ + RT_ERR_VLAN_ACCEPT_FRAME_TYPE, /* 0x00010003, invalid accept frame type */ + RT_ERR_VLAN_EXIST, /* 0x00010004, vlan is exist */ + RT_ERR_VLAN_ENTRY_NOT_FOUND, /* 0x00010005, specified vlan entry not found */ + RT_ERR_VLAN_PORT_MBR_EXIST, /* 0x00010006, member port exist in the specified vlan */ + RT_ERR_VLAN_PROTO_AND_PORT, /* 0x00010008, invalid protocol and port based vlan */ + + /* 0x0002xxxx for svlan */ + RT_ERR_SVLAN_ENTRY_INDEX = 0x00020000, /* 0x00020000, invalid svid entry no */ + RT_ERR_SVLAN_ETHER_TYPE, /* 0x00020001, invalid SVLAN ether type */ + RT_ERR_SVLAN_TABLE_FULL, /* 0x00020002, no empty entry in SVLAN table */ + RT_ERR_SVLAN_ENTRY_NOT_FOUND, /* 0x00020003, specified svlan entry not found */ + RT_ERR_SVLAN_EXIST, /* 0x00020004, SVLAN entry is exist */ + RT_ERR_SVLAN_VID, /* 0x00020005, invalid svid */ + + /* 0x0003xxxx for MSTP */ + RT_ERR_MSTI = 0x00030000, /* 0x00030000, invalid msti */ + RT_ERR_MSTP_STATE, /* 0x00030001, invalid spanning tree status */ + RT_ERR_MSTI_EXIST, /* 0x00030002, MSTI exist */ + RT_ERR_MSTI_NOT_EXIST, /* 0x00030003, MSTI not exist */ + + /* 0x0004xxxx for BUCKET */ + RT_ERR_TIMESLOT = 0x00040000, /* 0x00040000, invalid time slot */ + RT_ERR_TOKEN, /* 0x00040001, invalid token amount */ + RT_ERR_RATE, /* 0x00040002, invalid rate */ + RT_ERR_TICK, /* 0x00040003, invalid tick */ + + /* 0x0005xxxx for RMA */ + RT_ERR_RMA_ADDR = 0x00050000, /* 0x00050000, invalid rma mac address */ + RT_ERR_RMA_ACTION, /* 0x00050001, invalid rma action */ + + /* 0x0006xxxx for L2 */ + RT_ERR_L2_HASH_KEY = 0x00060000, /* 0x00060000, invalid L2 Hash key */ + RT_ERR_L2_HASH_INDEX, /* 0x00060001, invalid L2 Hash index */ + RT_ERR_L2_CAM_INDEX, /* 0x00060002, invalid L2 CAM index */ + RT_ERR_L2_ENRTYSEL, /* 0x00060003, invalid EntrySel */ + RT_ERR_L2_INDEXTABLE_INDEX, /* 0x00060004, invalid L2 index table(=portMask table) index */ + RT_ERR_LIMITED_L2ENTRY_NUM, /* 0x00060005, invalid limited L2 entry number */ + RT_ERR_L2_AGGREG_PORT, /* 0x00060006, this aggregated port is not the lowest physical + port of its aggregation group */ + RT_ERR_L2_FID, /* 0x00060007, invalid fid */ + RT_ERR_L2_VID, /* 0x00060008, invalid cvid */ + RT_ERR_L2_NO_EMPTY_ENTRY, /* 0x00060009, no empty entry in L2 table */ + RT_ERR_L2_ENTRY_NOTFOUND, /* 0x0006000a, specified entry not found */ + RT_ERR_L2_INDEXTBL_FULL, /* 0x0006000b, the L2 index table is full */ + RT_ERR_L2_INVALID_FLOWTYPE, /* 0x0006000c, invalid L2 flow type */ + RT_ERR_L2_L2UNI_PARAM, /* 0x0006000d, invalid L2 unicast parameter */ + RT_ERR_L2_L2MULTI_PARAM, /* 0x0006000e, invalid L2 multicast parameter */ + RT_ERR_L2_IPMULTI_PARAM, /* 0x0006000f, invalid L2 ip multicast parameter */ + RT_ERR_L2_PARTIAL_HASH_KEY, /* 0x00060010, invalid L2 partial Hash key */ + RT_ERR_L2_EMPTY_ENTRY, /* 0x00060011, the entry is empty(invalid) */ + RT_ERR_L2_FLUSH_TYPE, /* 0x00060012, the flush type is invalid */ + RT_ERR_L2_NO_CPU_PORT, /* 0x00060013, CPU port not exist */ + + /* 0x0007xxxx for FILTER (PIE) */ + RT_ERR_FILTER_BLOCKNUM = 0x00070000, /* 0x00070000, invalid block number */ + RT_ERR_FILTER_ENTRYIDX, /* 0x00070001, invalid entry index */ + RT_ERR_FILTER_CUTLINE, /* 0x00070002, invalid cutline value */ + RT_ERR_FILTER_FLOWTBLBLOCK, /* 0x00070003, block belongs to flow table */ + RT_ERR_FILTER_INACLBLOCK, /* 0x00070004, block belongs to ingress ACL */ + RT_ERR_FILTER_ACTION, /* 0x00070005, action doesn't consist to entry type */ + RT_ERR_FILTER_INACL_RULENUM, /* 0x00070006, invalid ACL rulenum */ + RT_ERR_FILTER_INACL_TYPE, /* 0x00070007, entry type isn't an ingress ACL rule */ + RT_ERR_FILTER_INACL_EXIST, /* 0x00070008, ACL entry is already exit */ + RT_ERR_FILTER_INACL_EMPTY, /* 0x00070009, ACL entry is empty */ + RT_ERR_FILTER_FLOWTBL_TYPE, /* 0x0007000a, entry type isn't an flow table rule */ + RT_ERR_FILTER_FLOWTBL_RULENUM, /* 0x0007000b, invalid flow table rulenum */ + RT_ERR_FILTER_FLOWTBL_EMPTY, /* 0x0007000c, flow table entry is empty */ + RT_ERR_FILTER_FLOWTBL_EXIST, /* 0x0007000d, flow table entry is already exist */ + RT_ERR_FILTER_METER_ID, /* 0x0007000e, invalid metering id */ + RT_ERR_FILTER_LOG_ID, /* 0x0007000f, invalid log id */ + RT_ERR_FILTER_INACL_NONE_BEGIN_IDX, /* 0x00070010, entry index is not starting index of a group of rules */ + RT_ERR_FILTER_INACL_ACT_NOT_SUPPORT, /* 0x00070011, action not support */ + RT_ERR_FILTER_INACL_RULE_NOT_SUPPORT, /* 0x00070012, rule not support */ + + /* 0x0008xxxx for ACL Rate Limit */ + RT_ERR_ACLRL_HTHR = 0x00080000, /* 0x00080000, invalid high threshold */ + RT_ERR_ACLRL_TIMESLOT, /* 0x00080001, invalid time slot */ + RT_ERR_ACLRL_TOKEN, /* 0x00080002, invalid token amount */ + RT_ERR_ACLRL_RATE, /* 0x00080003, invalid rate */ + + /* 0x0009xxxx for Link aggregation */ + RT_ERR_LA_CPUPORT = 0x00090000, /* 0x00090000, CPU port can not be aggregated port */ + RT_ERR_LA_TRUNK_ID, /* 0x00090001, invalid trunk id */ + RT_ERR_LA_PORTMASK, /* 0x00090002, invalid port mask */ + RT_ERR_LA_HASHMASK, /* 0x00090003, invalid hash mask */ + RT_ERR_LA_DUMB, /* 0x00090004, this API should be used in 802.1ad dumb mode */ + RT_ERR_LA_PORTNUM_DUMB, /* 0x00090005, it can only aggregate at most four ports when 802.1ad dumb mode */ + RT_ERR_LA_PORTNUM_NORMAL, /* 0x00090006, it can only aggregate at most eight ports when 802.1ad normal mode */ + RT_ERR_LA_MEMBER_OVERLAP, /* 0x00090007, the specified port mask is overlapped with other group */ + RT_ERR_LA_NOT_MEMBER_PORT, /* 0x00090008, the port is not a member port of the trunk */ + RT_ERR_LA_TRUNK_NOT_EXIST, /* 0x00090009, the trunk doesn't exist */ + + + /* 0x000axxxx for storm filter */ + RT_ERR_SFC_TICK_PERIOD = 0x000a0000, /* 0x000a0000, invalid SFC tick period */ + RT_ERR_SFC_UNKNOWN_GROUP, /* 0x000a0001, Unknown Storm filter group */ + + /* 0x000bxxxx for pattern match */ + RT_ERR_PM_MASK = 0x000b0000, /* 0x000b0000, invalid pattern length. Pattern length should be 8 */ + RT_ERR_PM_LENGTH, /* 0x000b0001, invalid pattern match mask, first byte must care */ + RT_ERR_PM_MODE, /* 0x000b0002, invalid pattern match mode */ + + /* 0x000cxxxx for input bandwidth control */ + RT_ERR_INBW_TICK_PERIOD = 0x000c0000, /* 0x000c0000, invalid tick period for input bandwidth control */ + RT_ERR_INBW_TOKEN_AMOUNT, /* 0x000c0001, invalid amount of token for input bandwidth control */ + RT_ERR_INBW_FCON_VALUE, /* 0x000c0002, invalid flow control ON threshold value for input bandwidth control */ + RT_ERR_INBW_FCOFF_VALUE, /* 0x000c0003, invalid flow control OFF threshold value for input bandwidth control */ + RT_ERR_INBW_FC_ALLOWANCE, /* 0x000c0004, invalid allowance of incomming packet for input bandwidth control */ + RT_ERR_INBW_RATE, /* 0x000c0005, invalid input bandwidth */ + + /* 0x000dxxxx for QoS */ + RT_ERR_QOS_1P_PRIORITY = 0x000d0000, /* 0x000d0000, invalid 802.1P priority */ + RT_ERR_QOS_DSCP_VALUE, /* 0x000d0001, invalid DSCP value */ + RT_ERR_QOS_INT_PRIORITY, /* 0x000d0002, invalid internal priority */ + RT_ERR_QOS_SEL_DSCP_PRI, /* 0x000d0003, invalid DSCP selection priority */ + RT_ERR_QOS_SEL_PORT_PRI, /* 0x000d0004, invalid port selection priority */ + RT_ERR_QOS_SEL_IN_ACL_PRI, /* 0x000d0005, invalid ingress ACL selection priority */ + RT_ERR_QOS_SEL_CLASS_PRI, /* 0x000d0006, invalid classifier selection priority */ + RT_ERR_QOS_EBW_RATE, /* 0x000d0007, invalid egress bandwidth rate */ + RT_ERR_QOS_SCHE_TYPE, /* 0x000d0008, invalid QoS scheduling type */ + RT_ERR_QOS_QUEUE_WEIGHT, /* 0x000d0009, invalid Queue weight */ + RT_ERR_QOS_SEL_PRI_SOURCE, /* 0x000d000a, invalid selection of priority source */ + + /* 0x000exxxx for port ability */ + RT_ERR_PHY_PAGE_ID = 0x000e0000, /* 0x000e0000, invalid PHY page id */ + RT_ERR_PHY_REG_ID, /* 0x000e0001, invalid PHY reg id */ + RT_ERR_PHY_DATAMASK, /* 0x000e0002, invalid PHY data mask */ + RT_ERR_PHY_AUTO_NEGO_MODE, /* 0x000e0003, invalid PHY auto-negotiation mode*/ + RT_ERR_PHY_SPEED, /* 0x000e0004, invalid PHY speed setting */ + RT_ERR_PHY_DUPLEX, /* 0x000e0005, invalid PHY duplex setting */ + RT_ERR_PHY_FORCE_ABILITY, /* 0x000e0006, invalid PHY force mode ability parameter */ + RT_ERR_PHY_FORCE_1000, /* 0x000e0007, invalid PHY force mode 1G speed setting */ + RT_ERR_PHY_TXRX, /* 0x000e0008, invalid PHY tx/rx */ + RT_ERR_PHY_ID, /* 0x000e0009, invalid PHY id */ + RT_ERR_PHY_RTCT_NOT_FINISH, /* 0x000e000a, PHY RTCT in progress */ + + /* 0x000fxxxx for mirror */ + RT_ERR_MIRROR_DIRECTION = 0x000f0000, /* 0x000f0000, invalid error mirror direction */ + RT_ERR_MIRROR_SESSION_FULL, /* 0x000f0001, mirroring session is full */ + RT_ERR_MIRROR_SESSION_NOEXIST, /* 0x000f0002, mirroring session not exist */ + RT_ERR_MIRROR_PORT_EXIST, /* 0x000f0003, mirroring port already exists */ + RT_ERR_MIRROR_PORT_NOT_EXIST, /* 0x000f0004, mirroring port does not exists */ + RT_ERR_MIRROR_PORT_FULL, /* 0x000f0005, Exceeds maximum number of supported mirroring port */ + + /* 0x0010xxxx for stat */ + RT_ERR_STAT_INVALID_GLOBAL_CNTR = 0x00100000, /* 0x00100000, Invalid Global Counter */ + RT_ERR_STAT_INVALID_PORT_CNTR, /* 0x00100001, Invalid Port Counter */ + RT_ERR_STAT_GLOBAL_CNTR_FAIL, /* 0x00100002, Could not retrieve/reset Global Counter */ + RT_ERR_STAT_PORT_CNTR_FAIL, /* 0x00100003, Could not retrieve/reset Port Counter */ + RT_ERR_STAT_INVALID_CNTR, /* 0x00100004, Invalid Counter */ + RT_ERR_STAT_CNTR_FAIL, /* 0x00100005, Could not retrieve/reset Counter */ + + /* 0x0011xxxx for dot1x */ + RT_ERR_DOT1X_INVALID_DIRECTION = 0x00110000, /* 0x00110000, Invalid Authentication Direction */ + RT_ERR_DOT1X_PORTBASEDPNEN, /* 0x00110001, Port-based enable port error */ + RT_ERR_DOT1X_PORTBASEDAUTH, /* 0x00110002, Port-based auth port error */ + RT_ERR_DOT1X_PORTBASEDOPDIR, /* 0x00110003, Port-based opdir error */ + RT_ERR_DOT1X_MACBASEDPNEN, /* 0x00110004, MAC-based enable port error */ + RT_ERR_DOT1X_MACBASEDOPDIR, /* 0x00110005, MAC-based opdir error */ + RT_ERR_DOT1X_PROC, /* 0x00110006, unauthorized behavior error */ + RT_ERR_DOT1X_GVLANIDX, /* 0x00110007, guest vlan index error */ + RT_ERR_DOT1X_GVLANTALK, /* 0x00110008, guest vlan OPDIR error */ + RT_ERR_DOT1X_MAC_PORT_MISMATCH, /* 0x00110009, Auth MAC and port mismatch eror */ + + RT_ERR_END /* The symbol is the latest symbol */ +} rt_error_code_t; + + +#endif /* __COMMON_RT_ERROR_H__ */ diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/rtk_switch.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/rtk_switch.c new file mode 100644 index 00000000..95b7dfa6 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/rtk_switch.c @@ -0,0 +1,1003 @@ +/* + * Copyright (C) 2010 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API + * Feature : Here is a list of all functions and variables in this module. + * + */ + +#include +#include +#include +#include +#include +#include + + +static init_state_t init_state = INIT_NOT_COMPLETED; + +#if defined(RTK_X86_CLE) +pthread_mutex_t api_mutex = PTHREAD_MUTEX_INITIALIZER; +#endif + +static rtk_switch_halCtrl_t *halCtrl = NULL; + +extern rtk_switch_halCtrl_t *hal_find_device(void); + +static rtk_api_ret_t _rtk_switch_init(void) +{ + rtk_int32 retVal; + switch_chip_t switchChip; + + halCtrl = hal_find_device(); + + /* Find device */ + if(halCtrl== NULL) + { + printf("hal_find_device failed!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n"); + switchChip = 4; + return RT_ERR_FAILED; + } + + + /* Attached DAL mapper */ + switchChip = halCtrl->switch_type; + g_switch_chip = switchChip; + printf("switch debug=========switchChip:%d\n",switchChip); + if((retVal = dal_mgmt_attachDevice(switchChip)) != RT_ERR_OK) + { + printf("dal_mgmt_attachDevice fail! ret = %d\n", retVal); + return retVal; + } + + /* Set initial state */ + if((retVal = rtk_switch_initialState_set(INIT_COMPLETED)) != RT_ERR_OK) + { + printf("dal_mgmt_attachDertk_switch_initialState_setvice fail! ret = %d\n", retVal); + return retVal; + } + + /* Call initial function */ + if((retVal = RT_MAPPER->switch_init()) != RT_ERR_OK) + { + printf("rtk_switch_initialState_set fail! ret = %d\n", retVal); + return retVal; + } + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_switch_initialState_set + * Description: + * Set initial status + * Input: + * state - Initial state; + * Output: + * None + * Return: + * RT_ERR_OK - Initialized + * RT_ERR_FAILED - Uninitialized + * Note: + * + */ +rtk_api_ret_t rtk_switch_initialState_set(init_state_t state) +{ + if(state >= INIT_STATE_END) + return RT_ERR_FAILED; + + init_state = state; + return RT_ERR_OK; +} + +/* Function Name: + * rtk_switch_initialState_get + * Description: + * Get initial status + * Input: + * None + * Output: + * None + * Return: + * INIT_COMPLETED - Initialized + * INIT_NOT_COMPLETED - Uninitialized + * Note: + * + */ +init_state_t rtk_switch_initialState_get(void) +{ + return init_state; +} + +/* Function Name: + * rtk_switch_logicalPortCheck + * Description: + * Check logical port ID. + * Input: + * logicalPort - logical port ID + * Output: + * None + * Return: + * RT_ERR_OK - Port ID is correct + * RT_ERR_FAILED - Port ID is not correct + * RT_ERR_NOT_INIT - Not Initialize + * Note: + * + */ +rtk_api_ret_t rtk_switch_logicalPortCheck(rtk_port_t logicalPort) +{ + if(init_state != INIT_COMPLETED) + return RT_ERR_NOT_INIT; + + if(logicalPort >= RTK_SWITCH_PORT_NUM) + return RT_ERR_FAILED; + + if(halCtrl->l2p_port[logicalPort] == 0xFF) + return RT_ERR_FAILED; + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_switch_isUtpPort + * Description: + * Check is logical port a UTP port + * Input: + * logicalPort - logical port ID + * Output: + * None + * Return: + * RT_ERR_OK - Port ID is a UTP port + * RT_ERR_FAILED - Port ID is not a UTP port + * RT_ERR_NOT_INIT - Not Initialize + * Note: + * + */ +rtk_api_ret_t rtk_switch_isUtpPort(rtk_port_t logicalPort) +{ + if(init_state != INIT_COMPLETED) + return RT_ERR_NOT_INIT; + + if(logicalPort >= RTK_SWITCH_PORT_NUM) + return RT_ERR_FAILED; + + if(halCtrl->log_port_type[logicalPort] == UTP_PORT) + return RT_ERR_OK; + else + return RT_ERR_FAILED; +} + +/* Function Name: + * rtk_switch_isExtPort + * Description: + * Check is logical port a Extension port + * Input: + * logicalPort - logical port ID + * Output: + * None + * Return: + * RT_ERR_OK - Port ID is a EXT port + * RT_ERR_FAILED - Port ID is not a EXT port + * RT_ERR_NOT_INIT - Not Initialize + * Note: + * + */ +rtk_api_ret_t rtk_switch_isExtPort(rtk_port_t logicalPort) +{ + if(init_state != INIT_COMPLETED) + return RT_ERR_NOT_INIT; + + if(logicalPort >= RTK_SWITCH_PORT_NUM) + return RT_ERR_FAILED; + + if(halCtrl->log_port_type[logicalPort] == EXT_PORT) + return RT_ERR_OK; + else + return RT_ERR_FAILED; +} + + +/* Function Name: + * rtk_switch_isHsgPort + * Description: + * Check is logical port a HSG port + * Input: + * logicalPort - logical port ID + * Output: + * None + * Return: + * RT_ERR_OK - Port ID is a HSG port + * RT_ERR_FAILED - Port ID is not a HSG port + * RT_ERR_NOT_INIT - Not Initialize + * Note: + * + */ +rtk_api_ret_t rtk_switch_isHsgPort(rtk_port_t logicalPort) +{ + if(init_state != INIT_COMPLETED) + return RT_ERR_NOT_INIT; + + if(logicalPort >= RTK_SWITCH_PORT_NUM) + return RT_ERR_FAILED; + + if( ((0x01 << logicalPort) & halCtrl->hsg_logical_portmask) != 0) + return RT_ERR_OK; + else + return RT_ERR_FAILED; +} + +/* Function Name: + * rtk_switch_isSgmiiPort + * Description: + * Check is logical port a SGMII port + * Input: + * logicalPort - logical port ID + * Output: + * None + * Return: + * RT_ERR_OK - Port ID is a SGMII port + * RT_ERR_FAILED - Port ID is not a SGMII port + * RT_ERR_NOT_INIT - Not Initialize + * Note: + * + */ +rtk_api_ret_t rtk_switch_isSgmiiPort(rtk_port_t logicalPort) +{ + if(init_state != INIT_COMPLETED) + return RT_ERR_NOT_INIT; + + if(logicalPort >= RTK_SWITCH_PORT_NUM) + return RT_ERR_FAILED; + + if( ((0x01 << logicalPort) & halCtrl->sg_logical_portmask) != 0) + return RT_ERR_OK; + else + return RT_ERR_FAILED; +} + +/* Function Name: + * rtk_switch_isCPUPort + * Description: + * Check is logical port a CPU port + * Input: + * logicalPort - logical port ID + * Output: + * None + * Return: + * RT_ERR_OK - Port ID is a CPU port + * RT_ERR_FAILED - Port ID is not a CPU port + * RT_ERR_NOT_INIT - Not Initialize + * Note: + * + */ +rtk_api_ret_t rtk_switch_isCPUPort(rtk_port_t logicalPort) +{ + if(init_state != INIT_COMPLETED) + return RT_ERR_NOT_INIT; + + if(logicalPort >= RTK_SWITCH_PORT_NUM) + return RT_ERR_FAILED; + + if( ((0x01 << logicalPort) & halCtrl->valid_cpu_portmask) != 0) + return RT_ERR_OK; + else + return RT_ERR_FAILED; +} + +/* Function Name: + * rtk_switch_isComboPort + * Description: + * Check is logical port a Combo port + * Input: + * logicalPort - logical port ID + * Output: + * None + * Return: + * RT_ERR_OK - Port ID is a combo port + * RT_ERR_FAILED - Port ID is not a combo port + * RT_ERR_NOT_INIT - Not Initialize + * Note: + * + */ +rtk_api_ret_t rtk_switch_isComboPort(rtk_port_t logicalPort) +{ + if(init_state != INIT_COMPLETED) + return RT_ERR_NOT_INIT; + + if(logicalPort >= RTK_SWITCH_PORT_NUM) + return RT_ERR_FAILED; + + if(halCtrl->combo_logical_port == logicalPort) + return RT_ERR_OK; + else + return RT_ERR_FAILED; +} + +/* Function Name: + * rtk_switch_ComboPort_get + * Description: + * Get Combo port ID + * Input: + * None + * Output: + * None + * Return: + * Port ID of combo port + * Note: + * + */ +rtk_uint32 rtk_switch_ComboPort_get(void) +{ + return halCtrl->combo_logical_port; +} + +/* Function Name: + * rtk_switch_isPtpPort + * Description: + * Check is logical port a PTP port + * Input: + * logicalPort - logical port ID + * Output: + * None + * Return: + * RT_ERR_OK - Port ID is a PTP port + * RT_ERR_FAILED - Port ID is not a PTP port + * RT_ERR_NOT_INIT - Not Initialize + * Note: + * + */ +rtk_api_ret_t rtk_switch_isPtpPort(rtk_port_t logicalPort) +{ + if(init_state != INIT_COMPLETED) + return RT_ERR_NOT_INIT; + + if(logicalPort >= RTK_SWITCH_PORT_NUM) + return RT_ERR_FAILED; + + if(halCtrl->ptp_port[logicalPort] == 1) + return RT_ERR_OK; + else + return RT_ERR_FAILED; +} + +/* Function Name: + * rtk_switch_port_L2P_get + * Description: + * Get physical port ID + * Input: + * logicalPort - logical port ID + * Output: + * None + * Return: + * Physical port ID + * Note: + * + */ +rtk_uint32 rtk_switch_port_L2P_get(rtk_port_t logicalPort) +{ + if(init_state != INIT_COMPLETED) + return UNDEFINE_PHY_PORT; + + if(logicalPort >= RTK_SWITCH_PORT_NUM) + return UNDEFINE_PHY_PORT; + + return (halCtrl->l2p_port[logicalPort]); +} + +/* Function Name: + * rtk_switch_port_P2L_get + * Description: + * Get logical port ID + * Input: + * physicalPort - physical port ID + * Output: + * None + * Return: + * logical port ID + * Note: + * + */ +rtk_port_t rtk_switch_port_P2L_get(rtk_uint32 physicalPort) +{ + if(init_state != INIT_COMPLETED) + return UNDEFINE_PORT; + + if(physicalPort >= RTK_SWITCH_PORT_NUM) + return UNDEFINE_PORT; + + return (halCtrl->p2l_port[physicalPort]); +} + +/* Function Name: + * rtk_switch_isPortMaskValid + * Description: + * Check portmask is valid or not + * Input: + * pPmask - logical port mask + * Output: + * None + * Return: + * RT_ERR_OK - port mask is valid + * RT_ERR_FAILED - port mask is not valid + * RT_ERR_NOT_INIT - Not Initialize + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * + */ +rtk_api_ret_t rtk_switch_isPortMaskValid(rtk_portmask_t *pPmask) +{ + if(init_state != INIT_COMPLETED) + return RT_ERR_NOT_INIT; + + if(NULL == pPmask) + return RT_ERR_NULL_POINTER; + + if( (pPmask->bits[0] | halCtrl->valid_portmask) != halCtrl->valid_portmask ) + return RT_ERR_FAILED; + else + return RT_ERR_OK; +} + +/* Function Name: + * rtk_switch_isPortMaskUtp + * Description: + * Check all ports in portmask are only UTP port + * Input: + * pPmask - logical port mask + * Output: + * None + * Return: + * RT_ERR_OK - Only UTP port in port mask + * RT_ERR_FAILED - Not only UTP port in port mask + * RT_ERR_NOT_INIT - Not Initialize + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * + */ +rtk_api_ret_t rtk_switch_isPortMaskUtp(rtk_portmask_t *pPmask) +{ + if(init_state != INIT_COMPLETED) + return RT_ERR_NOT_INIT; + + if(NULL == pPmask) + return RT_ERR_NULL_POINTER; + + if( (pPmask->bits[0] | halCtrl->valid_utp_portmask) != halCtrl->valid_utp_portmask ) + return RT_ERR_FAILED; + else + return RT_ERR_OK; +} + +/* Function Name: + * rtk_switch_isPortMaskExt + * Description: + * Check all ports in portmask are only EXT port + * Input: + * pPmask - logical port mask + * Output: + * None + * Return: + * RT_ERR_OK - Only EXT port in port mask + * RT_ERR_FAILED - Not only EXT port in port mask + * RT_ERR_NOT_INIT - Not Initialize + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * + */ +rtk_api_ret_t rtk_switch_isPortMaskExt(rtk_portmask_t *pPmask) +{ + if(init_state != INIT_COMPLETED) + return RT_ERR_NOT_INIT; + + if(NULL == pPmask) + return RT_ERR_NULL_POINTER; + + if( (pPmask->bits[0] | halCtrl->valid_ext_portmask) != halCtrl->valid_ext_portmask ) + return RT_ERR_FAILED; + else + return RT_ERR_OK; +} + +/* Function Name: + * rtk_switch_portmask_L2P_get + * Description: + * Get physicl portmask from logical portmask + * Input: + * pLogicalPmask - logical port mask + * Output: + * pPhysicalPortmask - physical port mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_NOT_INIT - Not Initialize + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_PORT_MASK - Error port mask + * Note: + * + */ +rtk_api_ret_t rtk_switch_portmask_L2P_get(rtk_portmask_t *pLogicalPmask, rtk_uint32 *pPhysicalPortmask) +{ + rtk_uint32 log_port, phyPort; + + if(init_state != INIT_COMPLETED) + return RT_ERR_NOT_INIT; + + if(NULL == pLogicalPmask) + return RT_ERR_NULL_POINTER; + + if(NULL == pPhysicalPortmask) + return RT_ERR_NULL_POINTER; + + if(rtk_switch_isPortMaskValid(pLogicalPmask) != RT_ERR_OK) + return RT_ERR_PORT_MASK; + + /* reset physical port mask */ + *pPhysicalPortmask = 0; + + RTK_PORTMASK_SCAN((*pLogicalPmask), log_port) + { + phyPort = rtk_switch_port_L2P_get((rtk_port_t)log_port); + if (phyPort == UNDEFINE_PHY_PORT) + return RT_ERR_PORT_ID; + + *pPhysicalPortmask |= (0x0001 << phyPort); + } + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_switch_portmask_P2L_get + * Description: + * Get logical portmask from physical portmask + * Input: + * physicalPortmask - physical port mask + * Output: + * pLogicalPmask - logical port mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_NOT_INIT - Not Initialize + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_PORT_MASK - Error port mask + * Note: + * + */ +rtk_api_ret_t rtk_switch_portmask_P2L_get(rtk_uint32 physicalPortmask, rtk_portmask_t *pLogicalPmask) +{ + rtk_uint32 log_port, phy_port; + + if(init_state != INIT_COMPLETED) + return RT_ERR_NOT_INIT; + + if(NULL == pLogicalPmask) + return RT_ERR_NULL_POINTER; + + RTK_PORTMASK_CLEAR(*pLogicalPmask); + + for(phy_port = halCtrl->min_phy_port; phy_port <= halCtrl->max_phy_port; phy_port++) + { + if(physicalPortmask & (0x0001 << phy_port)) + { + log_port = rtk_switch_port_P2L_get(phy_port); + if(log_port != UNDEFINE_PORT) + { + RTK_PORTMASK_PORT_SET(*pLogicalPmask, log_port); + } + } + } + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_switch_phyPortMask_get + * Description: + * Get physical portmask + * Input: + * None + * Output: + * None + * Return: + * 0x00 - Not Initialize + * Other value - Physical port mask + * Note: + * + */ +rtk_uint32 rtk_switch_phyPortMask_get(void) +{ + if(init_state != INIT_COMPLETED) + return 0x00; /* No port in portmask */ + + return (halCtrl->phy_portmask); +} + +/* Function Name: + * rtk_switch_logPortMask_get + * Description: + * Get Logical portmask + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_NOT_INIT - Not Initialize + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * + */ +rtk_api_ret_t rtk_switch_logPortMask_get(rtk_portmask_t *pPortmask) +{ + if(init_state != INIT_COMPLETED) + return RT_ERR_FAILED; + + if(NULL == pPortmask) + return RT_ERR_NULL_POINTER; + + pPortmask->bits[0] = halCtrl->valid_portmask; + return RT_ERR_OK; +} + +/* Function Name: + * rtk_switch_init + * Description: + * Set chip to default configuration enviroment + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set chip registers to default configuration for different release chip model. + */ +rtk_api_ret_t rtk_switch_init(void) +{ + rtk_api_ret_t retVal; + + RTK_API_LOCK(); + retVal = _rtk_switch_init(); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_switch_portMaxPktLen_set + * Description: + * Set Max packet length + * Input: + * port - Port ID + * speed - Speed + * cfgId - Configuration ID + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + */ +rtk_api_ret_t rtk_switch_portMaxPktLen_set(rtk_port_t port, rtk_switch_maxPktLen_linkSpeed_t speed, rtk_uint32 cfgId) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->switch_portMaxPktLen_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->switch_portMaxPktLen_set(port, speed, cfgId); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_switch_portMaxPktLen_get + * Description: + * Get Max packet length + * Input: + * port - Port ID + * speed - Speed + * Output: + * pCfgId - Configuration ID + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + */ +rtk_api_ret_t rtk_switch_portMaxPktLen_get(rtk_port_t port, rtk_switch_maxPktLen_linkSpeed_t speed, rtk_uint32 *pCfgId) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->switch_portMaxPktLen_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->switch_portMaxPktLen_get(port, speed, pCfgId); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_switch_maxPktLenCfg_set + * Description: + * Set Max packet length configuration + * Input: + * cfgId - Configuration ID + * pktLen - Max packet length + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + */ +rtk_api_ret_t rtk_switch_maxPktLenCfg_set(rtk_uint32 cfgId, rtk_uint32 pktLen) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->switch_maxPktLenCfg_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->switch_maxPktLenCfg_set(cfgId, pktLen); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_switch_maxPktLenCfg_get + * Description: + * Get Max packet length configuration + * Input: + * cfgId - Configuration ID + * pPktLen - Max packet length + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + */ +rtk_api_ret_t rtk_switch_maxPktLenCfg_get(rtk_uint32 cfgId, rtk_uint32 *pPktLen) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->switch_maxPktLenCfg_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->switch_maxPktLenCfg_get(cfgId, pPktLen); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_switch_greenEthernet_set + * Description: + * Set all Ports Green Ethernet state. + * Input: + * enable - Green Ethernet state. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * This API can set all Ports Green Ethernet state. + * The configuration is as following: + * - DISABLE + * - ENABLE + */ +rtk_api_ret_t rtk_switch_greenEthernet_set(rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->switch_greenEthernet_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->switch_greenEthernet_set(enable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_switch_greenEthernet_get + * Description: + * Get all Ports Green Ethernet state. + * Input: + * None + * Output: + * pEnable - Green Ethernet state. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API can get Green Ethernet state. + */ +rtk_api_ret_t rtk_switch_greenEthernet_get(rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->switch_greenEthernet_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->switch_greenEthernet_get(pEnable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_switch_maxLogicalPort_get + * Description: + * Get Max logical port ID + * Input: + * None + * Output: + * None + * Return: + * Max logical port + * Note: + * This API can get max logical port + */ +rtk_port_t rtk_switch_maxLogicalPort_get(void) +{ + rtk_port_t port, maxLogicalPort = 0; + + /* Check initialization state */ + if(rtk_switch_initialState_get() != INIT_COMPLETED) + { + return UNDEFINE_PORT; + } + + for(port = 0; port < RTK_SWITCH_PORT_NUM; port++) + { + if( (halCtrl->log_port_type[port] == UTP_PORT) || (halCtrl->log_port_type[port] == EXT_PORT) ) + maxLogicalPort = port; + } + + return maxLogicalPort; +} + +/* Function Name: + * rtk_switch_maxMeterId_get + * Description: + * Get Max Meter ID + * Input: + * None + * Output: + * None + * Return: + * 0x00 - Not Initialize + * Other value - Max Meter ID + * Note: + * + */ +rtk_uint32 rtk_switch_maxMeterId_get(void) +{ + if(init_state != INIT_COMPLETED) + return 0x00; + + return (halCtrl->max_meter_id); +} + +/* Function Name: + * rtk_switch_maxLutAddrNumber_get + * Description: + * Get Max LUT Address number + * Input: + * None + * Output: + * None + * Return: + * 0x00 - Not Initialize + * Other value - Max LUT Address number + * Note: + * + */ +rtk_uint32 rtk_switch_maxLutAddrNumber_get(void) +{ + if(init_state != INIT_COMPLETED) + return 0x00; + + return (halCtrl->max_lut_addr_num); +} + +/* Function Name: + * rtk_switch_isValidTrunkGrpId + * Description: + * Check if trunk group is valid or not + * Input: + * grpId - Group ID + * Output: + * None + * Return: + * RT_ERR_OK - Trunk Group ID is valid + * RT_ERR_LA_TRUNK_ID - Trunk Group ID is not valid + * Note: + * + */ +rtk_uint32 rtk_switch_isValidTrunkGrpId(rtk_uint32 grpId) +{ + if(init_state != INIT_COMPLETED) + return 0x00; + + if( (halCtrl->trunk_group_mask & (0x01 << grpId) ) != 0) + return RT_ERR_OK; + else + return RT_ERR_LA_TRUNK_ID; + +} + +/* Function Name: + * rtk_switch_maxBufferPageNum_get + * Description: + * Get number of packet buffer page + * Input: + * None + * Output: + * None + * Return: + * Number of packet buffer page + * Note: + * + */ +rtk_uint32 rtk_switch_maxBufferPageNum_get(void) +{ + if(init_state != INIT_COMPLETED) + return 0x00; + + return (halCtrl->packet_buffer_page_num); +} + +/* Function Name: + * rtk_switch_chipType_get + * Description: + * Get switch chip type + * Input: + * None + * Output: + * None + * Return: + * CHIP_END - Unknown chip type + * other - Switch chip type + * Note: + * + */ +switch_chip_t rtk_switch_chipType_get(void) +{ + if (halCtrl == NULL) + return CHIP_END; + + return halCtrl->switch_type; +} diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/rtk_switch.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/rtk_switch.h new file mode 100644 index 00000000..a71915be --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/rtk_switch.h @@ -0,0 +1,723 @@ +/* + * Copyright(c) Realtek Semiconductor Corporation, 2008 + * All rights reserved. + * + * $Revision$ + * $Date$ + * + * Purpose : Definition function prototype of RTK switch API. + * + * Feature : Function prototype definition + * + */ + +#ifndef __RTK_SWITCH_H__ +#define __RTK_SWITCH_H__ + +#include +#include + +#if defined(RTK_X86_CLE) +#include +#endif + +#define MAXPKTLEN_CFG_ID_MAX (1) + +#define RTK_SWITCH_MAX_PKTLEN (0x3FFF) + +#if defined(RTK_X86_CLE) +extern pthread_mutex_t api_mutex; +#define RTK_API_LOCK() pthread_mutex_lock(&api_mutex) +#define RTK_API_UNLOCK() pthread_mutex_unlock(&api_mutex) +#else +#define RTK_API_LOCK() +#define RTK_API_UNLOCK() +#endif + +typedef enum init_state_e +{ + INIT_NOT_COMPLETED = 0, + INIT_COMPLETED, + INIT_STATE_END +} init_state_t; + +typedef enum rtk_switch_maxPktLen_linkSpeed_e { + MAXPKTLEN_LINK_SPEED_FE = 0, + MAXPKTLEN_LINK_SPEED_GE, + MAXPKTLEN_LINK_SPEED_END, +} rtk_switch_maxPktLen_linkSpeed_t; + + +/* UTIL MACRO */ +#define RTK_CHK_INIT_STATE() \ + do \ + { \ + if(rtk_switch_initialState_get() != INIT_COMPLETED) \ + { \ + return RT_ERR_NOT_INIT; \ + } \ + }while(0) + +#define RTK_CHK_PORT_VALID(__port__) \ + do \ + { \ + if(rtk_switch_logicalPortCheck(__port__) != RT_ERR_OK) \ + { \ + return RT_ERR_PORT_ID; \ + } \ + }while(0) + +#define RTK_CHK_PORT_IS_UTP(__port__) \ + do \ + { \ + if(rtk_switch_isUtpPort(__port__) != RT_ERR_OK) \ + { \ + return RT_ERR_PORT_ID; \ + } \ + }while(0) + +#define RTK_CHK_PORT_IS_EXT(__port__) \ + do \ + { \ + if(rtk_switch_isExtPort(__port__) != RT_ERR_OK) \ + { \ + return RT_ERR_PORT_ID; \ + } \ + }while(0) + +#define RTK_CHK_PORT_IS_COMBO(__port__) \ + do \ + { \ + if(rtk_switch_isComboPort(__port__) != RT_ERR_OK) \ + { \ + return RT_ERR_PORT_ID; \ + } \ + }while(0) + +#define RTK_CHK_PORT_IS_PTP(__port__) \ + do \ + { \ + if(rtk_switch_isPtpPort(__port__) != RT_ERR_OK) \ + { \ + return RT_ERR_PORT_ID; \ + } \ + }while(0) + +#define RTK_CHK_PORTMASK_VALID(__portmask__) \ + do \ + { \ + if(rtk_switch_isPortMaskValid(__portmask__) != RT_ERR_OK) \ + { \ + return RT_ERR_PORT_MASK; \ + } \ + }while(0) + +#define RTK_CHK_PORTMASK_VALID_ONLY_UTP(__portmask__) \ + do \ + { \ + if(rtk_switch_isPortMaskUtp(__portmask__) != RT_ERR_OK) \ + { \ + return RT_ERR_PORT_MASK; \ + } \ + }while(0) + +#define RTK_CHK_PORTMASK_VALID_ONLY_EXT(__portmask__) \ + do \ + { \ + if(rtk_switch_isPortMaskExt(__portmask__) != RT_ERR_OK) \ + { \ + return RT_ERR_PORT_MASK; \ + } \ + }while(0) + +#define RTK_CHK_TRUNK_GROUP_VALID(__grpId__) \ + do \ + { \ + if(rtk_switch_isValidTrunkGrpId(__grpId__) != RT_ERR_OK) \ + { \ + return RT_ERR_LA_TRUNK_ID; \ + } \ + }while(0) + +#define RTK_PORTMASK_IS_PORT_SET(__portmask__, __port__) (((__portmask__).bits[0] & (0x00000001 << __port__)) ? 1 : 0) +#define RTK_PORTMASK_IS_EMPTY(__portmask__) (((__portmask__).bits[0] == 0) ? 1 : 0) +#define RTK_PORTMASK_CLEAR(__portmask__) ((__portmask__).bits[0] = 0) +#define RTK_PORTMASK_PORT_SET(__portmask__, __port__) ((__portmask__).bits[0] |= (0x00000001 << __port__)) +#define RTK_PORTMASK_PORT_CLEAR(__portmask__, __port__) ((__portmask__).bits[0] &= ~(0x00000001 << __port__)) +#define RTK_PORTMASK_ALLPORT_SET(__portmask__) (rtk_switch_logPortMask_get(&__portmask__)) +#define RTK_PORTMASK_SCAN(__portmask__, __port__) for(__port__ = 0; __port__ < RTK_SWITCH_PORT_NUM; __port__++) if(RTK_PORTMASK_IS_PORT_SET(__portmask__, __port__)) +#define RTK_PORTMASK_COMPARE(__portmask_A__, __portmask_B__) ((__portmask_A__).bits[0] - (__portmask_B__).bits[0]) + +#define RTK_SCAN_ALL_PHY_PORTMASK(__port__) for(__port__ = 0; __port__ < RTK_SWITCH_PORT_NUM; __port__++) if( (rtk_switch_phyPortMask_get() & (0x00000001 << __port__))) +#define RTK_SCAN_ALL_LOG_PORT(__port__) for(__port__ = 0; __port__ < RTK_SWITCH_PORT_NUM; __port__++) if( rtk_switch_logicalPortCheck(__port__) == RT_ERR_OK) +#define RTK_SCAN_ALL_LOG_PORTMASK(__portmask__) for((__portmask__).bits[0] = 0; (__portmask__).bits[0] < 0x7FFFF; (__portmask__).bits[0]++) if( rtk_switch_isPortMaskValid(&__portmask__) == RT_ERR_OK) + +/* Port mask defination */ +#define RTK_PHY_PORTMASK_ALL (rtk_switch_phyPortMask_get()) + +/* Port defination*/ +#define RTK_MAX_LOGICAL_PORT_ID (rtk_switch_maxLogicalPort_get()) + +/* Boundary defination */ +#define RTK_MAX_METER_ID (rtk_switch_maxMeterId_get()) +#define RTK_MAX_BUF_PAGE_NUM (rtk_switch_maxBufferPageNum_get()) + +/* Function Name: + * rtk_switch_initialState_set + * Description: + * Set initial status + * Input: + * state - Initial state; + * Output: + * None + * Return: + * RT_ERR_OK - Initialized + * RT_ERR_FAILED - Uninitialized + * Note: + * + */ +extern rtk_api_ret_t rtk_switch_initialState_set(init_state_t state); + +/* Function Name: + * rtk_switch_initialState_get + * Description: + * Get initial status + * Input: + * None + * Output: + * None + * Return: + * INIT_COMPLETED - Initialized + * INIT_NOT_COMPLETED - Uninitialized + * Note: + * + */ +extern init_state_t rtk_switch_initialState_get(void); + +/* Function Name: + * rtk_switch_logicalPortCheck + * Description: + * Check logical port ID. + * Input: + * logicalPort - logical port ID + * Output: + * None + * Return: + * RT_ERR_OK - Port ID is correct + * RT_ERR_FAILED - Port ID is not correct + * RT_ERR_NOT_INIT - Not Initialize + * Note: + * + */ +extern rtk_api_ret_t rtk_switch_logicalPortCheck(rtk_port_t logicalPort); + +/* Function Name: + * rtk_switch_isUtpPort + * Description: + * Check is logical port a UTP port + * Input: + * logicalPort - logical port ID + * Output: + * None + * Return: + * RT_ERR_OK - Port ID is a UTP port + * RT_ERR_FAILED - Port ID is not a UTP port + * RT_ERR_NOT_INIT - Not Initialize + * Note: + * + */ +extern rtk_api_ret_t rtk_switch_isUtpPort(rtk_port_t logicalPort); + +/* Function Name: + * rtk_switch_isExtPort + * Description: + * Check is logical port a Extension port + * Input: + * logicalPort - logical port ID + * Output: + * None + * Return: + * RT_ERR_OK - Port ID is a EXT port + * RT_ERR_FAILED - Port ID is not a EXT port + * RT_ERR_NOT_INIT - Not Initialize + * Note: + * + */ +extern rtk_api_ret_t rtk_switch_isExtPort(rtk_port_t logicalPort); + +/* Function Name: + * rtk_switch_isHsgPort + * Description: + * Check is logical port a HSG port + * Input: + * logicalPort - logical port ID + * Output: + * None + * Return: + * RT_ERR_OK - Port ID is a HSG port + * RT_ERR_FAILED - Port ID is not a HSG port + * RT_ERR_NOT_INIT - Not Initialize + * Note: + * + */ +extern rtk_api_ret_t rtk_switch_isHsgPort(rtk_port_t logicalPort); + +/* Function Name: + * rtk_switch_isSgmiiPort + * Description: + * Check is logical port a SGMII port + * Input: + * logicalPort - logical port ID + * Output: + * None + * Return: + * RT_ERR_OK - Port ID is a SGMII port + * RT_ERR_FAILED - Port ID is not a SGMII port + * RT_ERR_NOT_INIT - Not Initialize + * Note: + * + */ +extern rtk_api_ret_t rtk_switch_isSgmiiPort(rtk_port_t logicalPort); + +/* Function Name: + * rtk_switch_isCPUPort + * Description: + * Check is logical port a CPU port + * Input: + * logicalPort - logical port ID + * Output: + * None + * Return: + * RT_ERR_OK - Port ID is a CPU port + * RT_ERR_FAILED - Port ID is not a CPU port + * RT_ERR_NOT_INIT - Not Initialize + * Note: + * + */ +extern rtk_api_ret_t rtk_switch_isCPUPort(rtk_port_t logicalPort); + +/* Function Name: + * rtk_switch_isComboPort + * Description: + * Check is logical port a Combo port + * Input: + * logicalPort - logical port ID + * Output: + * None + * Return: + * RT_ERR_OK - Port ID is a combo port + * RT_ERR_FAILED - Port ID is not a combo port + * RT_ERR_NOT_INIT - Not Initialize + * Note: + * + */ +extern rtk_api_ret_t rtk_switch_isComboPort(rtk_port_t logicalPort); + +/* Function Name: + * rtk_switch_ComboPort_get + * Description: + * Get Combo port ID + * Input: + * None + * Output: + * None + * Return: + * Port ID of combo port + * Note: + * + */ +extern rtk_uint32 rtk_switch_ComboPort_get(void); + +/* Function Name: + * rtk_switch_isPtpPort + * Description: + * Check is logical port a PTP port + * Input: + * logicalPort - logical port ID + * Output: + * None + * Return: + * RT_ERR_OK - Port ID is a PTP port + * RT_ERR_FAILED - Port ID is not a PTP port + * RT_ERR_NOT_INIT - Not Initialize + * Note: + * + */ +extern rtk_api_ret_t rtk_switch_isPtpPort(rtk_port_t logicalPort); + +/* Function Name: + * rtk_switch_port_L2P_get + * Description: + * Get physical port ID + * Input: + * logicalPort - logical port ID + * Output: + * None + * Return: + * Physical port ID + * Note: + * + */ +extern rtk_uint32 rtk_switch_port_L2P_get(rtk_port_t logicalPort); + +/* Function Name: + * rtk_switch_port_P2L_get + * Description: + * Get logical port ID + * Input: + * physicalPort - physical port ID + * Output: + * None + * Return: + * logical port ID + * Note: + * + */ +extern rtk_port_t rtk_switch_port_P2L_get(rtk_uint32 physicalPort); + +/* Function Name: + * rtk_switch_isPortMaskValid + * Description: + * Check portmask is valid or not + * Input: + * pPmask - logical port mask + * Output: + * None + * Return: + * RT_ERR_OK - port mask is valid + * RT_ERR_FAILED - port mask is not valid + * RT_ERR_NOT_INIT - Not Initialize + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * + */ +extern rtk_api_ret_t rtk_switch_isPortMaskValid(rtk_portmask_t *pPmask); + +/* Function Name: + * rtk_switch_isPortMaskUtp + * Description: + * Check all ports in portmask are only UTP port + * Input: + * pPmask - logical port mask + * Output: + * None + * Return: + * RT_ERR_OK - Only UTP port in port mask + * RT_ERR_FAILED - Not only UTP port in port mask + * RT_ERR_NOT_INIT - Not Initialize + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * + */ +extern rtk_api_ret_t rtk_switch_isPortMaskUtp(rtk_portmask_t *pPmask); + +/* Function Name: + * rtk_switch_isPortMaskExt + * Description: + * Check all ports in portmask are only EXT port + * Input: + * pPmask - logical port mask + * Output: + * None + * Return: + * RT_ERR_OK - Only EXT port in port mask + * RT_ERR_FAILED - Not only EXT port in port mask + * RT_ERR_NOT_INIT - Not Initialize + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * + */ +extern rtk_api_ret_t rtk_switch_isPortMaskExt(rtk_portmask_t *pPmask); + +/* Function Name: + * rtk_switch_portmask_L2P_get + * Description: + * Get physicl portmask from logical portmask + * Input: + * pLogicalPmask - logical port mask + * Output: + * pPhysicalPortmask - physical port mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_NOT_INIT - Not Initialize + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_PORT_MASK - Error port mask + * Note: + * + */ +extern rtk_api_ret_t rtk_switch_portmask_L2P_get(rtk_portmask_t *pLogicalPmask, rtk_uint32 *pPhysicalPortmask); + +/* Function Name: + * rtk_switch_portmask_P2L_get + * Description: + * Get logical portmask from physical portmask + * Input: + * physicalPortmask - physical port mask + * Output: + * pLogicalPmask - logical port mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_NOT_INIT - Not Initialize + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_PORT_MASK - Error port mask + * Note: + * + */ +extern rtk_api_ret_t rtk_switch_portmask_P2L_get(rtk_uint32 physicalPortmask, rtk_portmask_t *pLogicalPmask); + +/* Function Name: + * rtk_switch_phyPortMask_get + * Description: + * Get physical portmask + * Input: + * None + * Output: + * None + * Return: + * 0x00 - Not Initialize + * Other value - Physical port mask + * Note: + * + */ +rtk_uint32 rtk_switch_phyPortMask_get(void); + +/* Function Name: + * rtk_switch_logPortMask_get + * Description: + * Get Logical portmask + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_NOT_INIT - Not Initialize + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * + */ +rtk_api_ret_t rtk_switch_logPortMask_get(rtk_portmask_t *pPortmask); + +/* Function Name: + * rtk_switch_init + * Description: + * Set chip to default configuration enviroment + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set chip registers to default configuration for different release chip model. + */ +extern rtk_api_ret_t rtk_switch_init(void); + +/* Function Name: + * rtk_switch_portMaxPktLen_set + * Description: + * Set Max packet length + * Input: + * port - Port ID + * speed - Speed + * cfgId - Configuration ID + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + */ +extern rtk_api_ret_t rtk_switch_portMaxPktLen_set(rtk_port_t port, rtk_switch_maxPktLen_linkSpeed_t speed, rtk_uint32 cfgId); + +/* Function Name: + * rtk_switch_portMaxPktLen_get + * Description: + * Get Max packet length + * Input: + * port - Port ID + * speed - Speed + * Output: + * pCfgId - Configuration ID + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + */ +extern rtk_api_ret_t rtk_switch_portMaxPktLen_get(rtk_port_t port, rtk_switch_maxPktLen_linkSpeed_t speed, rtk_uint32 *pCfgId); + +/* Function Name: + * rtk_switch_maxPktLenCfg_set + * Description: + * Set Max packet length configuration + * Input: + * cfgId - Configuration ID + * pktLen - Max packet length + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + */ +extern rtk_api_ret_t rtk_switch_maxPktLenCfg_set(rtk_uint32 cfgId, rtk_uint32 pktLen); + +/* Function Name: + * rtk_switch_maxPktLenCfg_get + * Description: + * Get Max packet length configuration + * Input: + * cfgId - Configuration ID + * pPktLen - Max packet length + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + */ +extern rtk_api_ret_t rtk_switch_maxPktLenCfg_get(rtk_uint32 cfgId, rtk_uint32 *pPktLen); + +/* Function Name: + * rtk_switch_greenEthernet_set + * Description: + * Set all Ports Green Ethernet state. + * Input: + * enable - Green Ethernet state. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * This API can set all Ports Green Ethernet state. + * The configuration is as following: + * - DISABLE + * - ENABLE + */ +extern rtk_api_ret_t rtk_switch_greenEthernet_set(rtk_enable_t enable); + +/* Function Name: + * rtk_switch_greenEthernet_get + * Description: + * Get all Ports Green Ethernet state. + * Input: + * None + * Output: + * pEnable - Green Ethernet state. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API can get Green Ethernet state. + */ +extern rtk_api_ret_t rtk_switch_greenEthernet_get(rtk_enable_t *pEnable); + +/* Function Name: + * rtk_switch_maxLogicalPort_get + * Description: + * Get Max logical port ID + * Input: + * None + * Output: + * None + * Return: + * Max logical port + * Note: + * This API can get max logical port + */ +extern rtk_port_t rtk_switch_maxLogicalPort_get(void); + +/* Function Name: + * rtk_switch_maxMeterId_get + * Description: + * Get Max Meter ID + * Input: + * None + * Output: + * None + * Return: + * 0x00 - Not Initialize + * Other value - Max Meter ID + * Note: + * + */ +extern rtk_uint32 rtk_switch_maxMeterId_get(void); + +/* Function Name: + * rtk_switch_maxLutAddrNumber_get + * Description: + * Get Max LUT Address number + * Input: + * None + * Output: + * None + * Return: + * 0x00 - Not Initialize + * Other value - Max LUT Address number + * Note: + * + */ +extern rtk_uint32 rtk_switch_maxLutAddrNumber_get(void); + +/* Function Name: + * rtk_switch_isValidTrunkGrpId + * Description: + * Check if trunk group is valid or not + * Input: + * grpId - Group ID + * Output: + * None + * Return: + * RT_ERR_OK - Trunk Group ID is valid + * RT_ERR_LA_TRUNK_ID - Trunk Group ID is not valid + * Note: + * + */ +rtk_uint32 rtk_switch_isValidTrunkGrpId(rtk_uint32 grpId); + +/* Function Name: + * rtk_switch_maxBufferPageNum_get + * Description: + * Get number of packet buffer page + * Input: + * None + * Output: + * None + * Return: + * Number of packet buffer page + * Note: + * + */ +rtk_uint32 rtk_switch_maxBufferPageNum_get(void); + +/* Function Name: + * rtk_switch_chipType_get + * Description: + * Get switch chip type + * Input: + * None + * Output: + * None + * Return: + * CHIP_END - Unknown chip type + * other - Switch chip type + * Note: + * + */ +switch_chip_t rtk_switch_chipType_get(void); + +#endif diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/rtk_types.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/rtk_types.h new file mode 100644 index 00000000..1fa7fa60 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/rtk_types.h @@ -0,0 +1,138 @@ +#ifndef _RTL8367C_TYPES_H_ +#define _RTL8367C_TYPES_H_ + +//#include + +typedef unsigned long long rtk_uint64; +typedef long long rtk_int64; +typedef unsigned int rtk_uint32; +typedef int rtk_int32; +typedef unsigned short rtk_uint16; +typedef short rtk_int16; +typedef unsigned char rtk_uint8; +typedef char rtk_int8; + +#define CONST_T const + +#define RTK_TOTAL_NUM_OF_WORD_FOR_1BIT_PORT_LIST 1 + +#define RTK_MAX_NUM_OF_PORT 8 +#define RTK_PORT_ID_MAX (RTK_MAX_NUM_OF_PORT-1) +#define RTK_PHY_ID_MAX (RTK_MAX_NUM_OF_PORT-4) +#define RTK_MAX_PORT_MASK 0xFF + +#define RTK_WHOLE_SYSTEM 0xFF + +typedef struct rtk_portmask_s +{ + rtk_uint32 bits[RTK_TOTAL_NUM_OF_WORD_FOR_1BIT_PORT_LIST]; +} rtk_portmask_t; + +typedef enum rtk_enable_e +{ + DISABLED = 0, + ENABLED, + RTK_ENABLE_END +} rtk_enable_t; + +#ifndef ETHER_ADDR_LEN +#define ETHER_ADDR_LEN 6 +#endif + +/* ethernet address type */ +typedef struct rtk_mac_s +{ + rtk_uint8 octet[ETHER_ADDR_LEN]; +} rtk_mac_t; + +typedef rtk_uint32 rtk_pri_t; /* priority vlaue */ +typedef rtk_uint32 rtk_qid_t; /* queue id type */ +typedef rtk_uint32 rtk_data_t; +typedef rtk_uint32 rtk_dscp_t; /* dscp vlaue */ +typedef rtk_uint32 rtk_fid_t; /* filter id type */ +typedef rtk_uint32 rtk_vlan_t; /* vlan id type */ +typedef rtk_uint32 rtk_mac_cnt_t; /* MAC count type */ +typedef rtk_uint32 rtk_meter_id_t; /* meter id type */ +typedef rtk_uint32 rtk_rate_t; /* rate type */ + +typedef enum rtk_port_e +{ + UTP_PORT0 = 0, + UTP_PORT1, + UTP_PORT2, + UTP_PORT3, + UTP_PORT4, + UTP_PORT5, + UTP_PORT6, + UTP_PORT7, + + EXT_PORT0 = 16, + EXT_PORT1, + EXT_PORT2, + + UNDEFINE_PORT = 30, + RTK_PORT_MAX = 31 +} rtk_port_t; + + +#ifndef _RTL_TYPES_H + +#if 0 +typedef unsigned long long uint64; +typedef long long int64; +typedef unsigned int uint32; +typedef int int32; +typedef unsigned short uint16; +typedef short int16; +typedef unsigned char uint8; +typedef char int8; +#endif + +typedef rtk_uint32 ipaddr_t; +typedef rtk_uint32 memaddr; + +#ifndef ETHER_ADDR_LEN +#define ETHER_ADDR_LEN 6 +#endif + +typedef struct ether_addr_s { + rtk_uint8 octet[ETHER_ADDR_LEN]; +} ether_addr_t; + +#ifdef __KERNEL__ +#define rtlglue_printf printk +#else +#define rtlglue_printf printf +#endif +#define PRINT rtlglue_printf +#endif /*_RTL_TYPES_H*/ + +/* type abstraction */ +#ifdef EMBEDDED_SUPPORT + +typedef rtk_int16 rtk_api_ret_t; +typedef rtk_int16 ret_t; +typedef rtk_uint32 rtk_u_long; + +#else + +typedef rtk_int32 rtk_api_ret_t; +typedef rtk_int32 ret_t; +typedef rtk_uint64 rtk_u_long_t; + +#endif + +#ifndef NULL +#define NULL 0 +#endif + +#ifndef TRUE +#define TRUE 1 +#endif + +#ifndef FALSE +#define FALSE 0 +#endif + +#define CONST const +#endif /* _RTL8367C_TYPES_H_ */ diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/rtl8367s.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/rtl8367s.c new file mode 100644 index 00000000..f53445a2 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/rtl8367s.c @@ -0,0 +1,4748 @@ +//#ifdef CONFIG_TP_EXT_SWITCH_RTL8367S +#include + +#define RTL8367S_HW_LED_FUNCTION +//#define RTL8367S_HW_BRIDGE_PORT_VLAN_DETECT + +#ifdef CONFIG_TP_EXT_SWITCH_RTL8367S_SINGLE +#include "rtl8367s/rtl8367c_asicdrv_port.h" +#include "rtl8367s/rtk_switch.h" +#include "rtl8367s/port.h" +#include "rtl8367s/vlan.h" +#include "rtl8367s/acl.h" +#include "rtl8367s/svlan.h" +#include "rtl8367s/vlan.h" +#include "rtl8367s/l2.h" +#include "rtl8367s/stat.h" +#include "rtl8367s/cpu.h" +#include "rtl8367s/trap.h" +#include "rtl8367s/igmp.h" +#include "rtl8367s/mirror.h" +#ifdef RTL8367S_HW_LED_FUNCTION +#include "rtl8367s/led.h" +#endif /*RTL8367S_HW_LED_FUNCTION */ +#else +#include "rtk_types.h" +#include "rtk_error.h" +#include "rtk_switch.h" +#include "port.h" +#include "vlan.h" +#include "acl.h" +#include "svlan.h" +#include "l2.h" +#include "stat.h" +#include "cpu.h" +#include "trap.h" +#include "igmp.h" +#include "mirror.h" +#include "dal/dal_mgmt.h" +#ifdef RTL8367S_HW_LED_FUNCTION +#include "led.h" +#endif /*RTL8367S_HW_LED_FUNCTION */ +#include "chip.h" +#include "sw.h" +#include "fal_port_ctrl.h" +#include "hsl_api.h" +#include "hsl.h" +#include "hsl_phy.h" +#include "ssdk_plat.h" +#include "qca808x_phy.h" +#include "rtl8367s.h" +#include "eee.h" + +#include +#include +#include +#include +#include +#include +#endif + +#include +#include +#include +#include +#include +#include + +#if 1 +#define RTL8367S_RESET_GPIO_NUM (30) +#else +#define RTL8367S_RESET_GPIO_NUM (33) +#endif + +#define RTL8367S_PHY_LINK_CHECK_INTERVAL (1000) /*ms*/ + +#define RTL8367S_FID_RESERVED_NUM (2) /* fid 0 & 1 not used */ + +#define RTL8367S_VID_RESERVED_NUM (3) /* vid 0 & 1 not used */ + +typedef enum { + PORT_IDX0 = 0, + PORT_IDX1 = 1, + PORT_IDX2 = 2, + PORT_IDX3 = 3, + PORT_IDX4 = 4, + PORT_MAX_NUM, +} port_idx; + +#define RTL8367S_REVERSE_PORT_MAPPING + +static const rtk_port_t rtl8367s_utp_port[PORT_MAX_NUM] = { +#ifdef RTL8367S_REVERSE_PORT_MAPPING + UTP_PORT4, + UTP_PORT3, + UTP_PORT2, + UTP_PORT1, + UTP_PORT0, +#else + UTP_PORT0, + UTP_PORT1, + UTP_PORT2, + EXT_PORT1, +#endif /* RTL8367S_REVERSE_PORT_MAPPING */ +}; + +static const rtk_port_t rtl8367s_cpu_port = EXT_PORT1; + +static const rtk_port_t rtl8367s_lan_2P5G_port = EXT_PORT0; + + +static const char* rtl8367s_dev_name[PORT_MAX_NUM] = { + "eth0.2", + "eth0.3", + "eth0.4", + "eth0.5", + "eth0.6", +}; + +static int rtl8367s_br_group[PORT_MAX_NUM] = { + -1, + -1, + -1, + -1, + -1, +}; + +static int rtl8367s_iso_mode[PORT_MAX_NUM] = { + 0, + 0, + 0, + 0, + 0, +}; + +static int rtl8368s_mc_router[PORT_MAX_NUM] = { + 1, + 1, + 1, + 1, + 1, +}; + +static int rtl8368s_link_status[PORT_MAX_NUM] = { + -1, + -1, + -1, + -1, + -1, +}; + +static int rtl8367s_hw_bridge_port[PORT_MAX_NUM] = { + 1, + 1, + 1, + 1, + 1, +}; + +#ifdef RTL8367S_HW_BRIDGE_PORT_VLAN_DETECT +static int rtl8367s_hw_bridge_vlan_port[PORT_MAX_NUM] = { + 0, + 0, + 0, + 0, + 0, +}; +#endif /**/ + +static int rtl8367s_mii_type = 2; + +static int rtl8367s_mcast_snoop = 1; + +static int rtl8367s_port_mirror = 0; + +static int rtl8367s_hw_bridge = 1; + +static int rtl8367s_eth_forward = 0; /* 0: init forbid forwarding */ + +#ifdef RTL8367S_HW_LED_FUNCTION +static int rtl8367s_hw_led = 1; +#endif /* RTL8367S_HW_LED_FUNCTION */ + +unsigned char rtl8367s_cpu_mac[6] = { 0, 0, 0, 0, 0, 0 }; + +static int rtl8367s_debug_info = 1; + +switch_chip_t g_switch_chip = CHIP_END; + +#ifdef USE_SPIN_LOCK +static spinlock_t rtl8367s_lock; + +#define RTL8367S_LOCK_INIT() \ + do { \ + spin_lock_init(&rtl8367s_lock);\ + } while(0) + +#define RTL8367S_LOCK() \ + do { \ + spin_lock_bh(&rtl8367s_lock);\ + } while(0) + +#define RTL8367S_UNLOCK() \ + do { \ + spin_unlock_bh(&rtl8367s_lock);\ + } while(0) + +#else +static struct mutex rtl8367s_lock; + +#define RTL8367S_LOCK_INIT() \ + do { \ + mutex_init(&rtl8367s_lock);\ + } while(0) + +#define RTL8367S_LOCK() \ + do { \ + mutex_lock(&rtl8367s_lock);\ + } while(0) + +#define RTL8367S_UNLOCK() \ + do { \ + mutex_unlock(&rtl8367s_lock);\ + } while(0) + +#endif + +#define RTL8367S_LOG_ERR(fmt, ...) \ + do { \ + printk("[RTL8367S ERROR] (%s %d) " fmt, __func__, __LINE__, ##__VA_ARGS__);\ + } while(0) + +#define RTL8367S_LOG_INFO(fmt, ...) \ + do { \ + printk("[RTL8367S INFO] " fmt, ##__VA_ARGS__);\ + } while(0) + +#define RTL8367S_LOG_DEBUG(fmt, ...) \ + do { \ + if(rtl8367s_debug_info) \ + { \ + printk("[RTL8367S DEBUG] (%s %d) " fmt, __func__, __LINE__, ##__VA_ARGS__);\ + } \ + }while(0) + + +static struct mii_bus *g_mii_bus = NULL; + +int rtl8367s_mdio_write(unsigned int phy_addr, unsigned int reg, unsigned int data) +{ + if (!g_mii_bus) + { + return -1; + } + + mutex_lock(&g_mii_bus->mdio_lock); + __mdiobus_write(g_mii_bus, 29, reg, data); + mutex_unlock(&g_mii_bus->mdio_lock); + + return 0; +} + +int rtl8367s_mdio_read(unsigned int phy_addr, unsigned int reg, unsigned int* data) +{ + if (!g_mii_bus) + { + return -1; + } + + mutex_lock(&g_mii_bus->mdio_lock); + *data = __mdiobus_read(g_mii_bus, 29, reg); + mutex_unlock(&g_mii_bus->mdio_lock); + + return 0; +} + +static void rtl8367s_gpio_reset(int gpio_num) +{ + gpio_direction_output(gpio_num, 1); + msleep(500); + gpio_set_value(gpio_num, 0); + msleep(200); + gpio_set_value(gpio_num, 1); + msleep(1000); + + return; +} + + +static int _rtl8367s_acl_refresh(void) +{ + rtk_api_ret_t ret = RT_ERR_OK; + + rtk_filter_field_t filter_field; + rtk_filter_cfg_t cfg; + rtk_filter_action_t act; + rtk_filter_number_t ruleNum; + + memset(&cfg, 0, sizeof(rtk_filter_cfg_t)); + memset(&act, 0, sizeof(rtk_filter_action_t)); + memset(&filter_field, 0, sizeof(rtk_filter_field_t)); + + filter_field.fieldType = FILTER_FIELD_DMAC; + filter_field.filter_pattern_union.dmac.dataType = FILTER_FIELD_DATA_MASK; + filter_field.filter_pattern_union.dmac.value.octet[0] = 0x01; /* ieee 1905 message */ + filter_field.filter_pattern_union.dmac.value.octet[1] = 0x80; + filter_field.filter_pattern_union.dmac.value.octet[2] = 0xC2; + filter_field.filter_pattern_union.dmac.value.octet[3] = 0x00; + filter_field.filter_pattern_union.dmac.value.octet[4] = 0x00; + filter_field.filter_pattern_union.dmac.value.octet[5] = 0x13; + + filter_field.filter_pattern_union.dmac.mask.octet[0] = 0xFF; + filter_field.filter_pattern_union.dmac.mask.octet[1] = 0xFF; + filter_field.filter_pattern_union.dmac.mask.octet[2] = 0xFF; + filter_field.filter_pattern_union.dmac.mask.octet[3] = 0xFF; + filter_field.filter_pattern_union.dmac.mask.octet[4] = 0xFF; + filter_field.filter_pattern_union.dmac.mask.octet[5] = 0xFF; + + if ((ret = rtk_filter_igrAcl_field_add(&cfg, &filter_field)) != RT_ERR_OK) + { + RTL8367S_LOG_ERR("rtk_filter_igrAcl_field_add fail...ret=%d\n", ret); + return ret; + } + RTK_PORTMASK_PORT_SET(cfg.activeport.value, EXT_PORT1); + RTK_PORTMASK_PORT_SET(cfg.activeport.value, UTP_PORT0); + RTK_PORTMASK_PORT_SET(cfg.activeport.value, UTP_PORT1); + RTK_PORTMASK_PORT_SET(cfg.activeport.value, UTP_PORT2); + RTK_PORTMASK_PORT_SET(cfg.activeport.value, UTP_PORT3); + RTK_PORTMASK_PORT_SET(cfg.activeport.value, UTP_PORT4); + RTK_PORTMASK_ALLPORT_SET(cfg.activeport.mask); + cfg.invert = FALSE; + act.actEnable[FILTER_ENACT_REDIRECT] = TRUE; + act.filterPortmask.bits[0] = (1<priv_switch_flags & IFF_TP_EXT_SWITCH_DEV) + { + return 1; + } +#endif + return 0; +} + +#if 0 +static int _rtl8367s_device_to_pidx(struct net_device * dev) +{ + int ret = -1; + + if(!_rtl8367s_is_switch_device(dev)) + { + return -1; + } + + ret = (dev->priv_switch_flags & IFF_TP_EXT_SWITCH_IDX_MASK); + if(ret >= PORT_MAX_NUM) + { + return -1; + } + + return ret; +} +#endif + +#ifdef RTL8367S_HW_LED_FUNCTION +static int _rtl8367s_hw_led_refresh(void) +{ + int ret = 0; + int p; + + rtk_led_force_mode_t mode = 0; + + switch(rtl8367s_hw_led) + { + case 0: + mode = LED_FORCE_OFF; + break; + case 1: + mode = LED_FORCE_NORMAL; + break; + case 2: + mode = LED_FORCE_ON; + break; + default: + RTL8367S_LOG_ERR("wrong hw_led %d\n", rtl8367s_hw_led); + return -1; + } + + for(p=PORT_IDX0; pname, dev->name, add); + + RTL8367S_LOCK(); + + p = _rtl8367s_device_to_pidx(dev); + + if(p < 0) + { + RTL8367S_LOG_DEBUG("wrong dev %s\r\n", dev->name); + ret = -1; + goto error; + } + + old_group = rtl8367s_br_group[p]; + + if(add) + { + if(old_group >= 0) + { + RTL8367S_LOG_ERR("wrong old group index %d\r\n", old_group); + ret = -1; + goto error; + } + new_group = br->ifindex; + } + else + { + if(old_group < 0) + { + RTL8367S_LOG_ERR("wrong old group index %d\r\n", old_group); + ret = -1; + goto error; + } + new_group = -1; + } + + if(old_group == new_group) + { + RTL8367S_LOG_ERR("same group %d\r\n", old_group); + ret = -1; + goto error; + } + + rtl8367s_br_group[p] = new_group; + rtl8367s_iso_mode[p] = 0; + rtl8368s_mc_router[p] = 1; + + if(rtl8367s_hw_bridge) + { + _rtl8367s_lookup_refresh(); + } + + if(rtl8367s_mcast_snoop && CHIP_RTL8367D != g_switch_chip) + { + _rtl8367s_mcast_mcr_refresh(); + } + + rtk_l2_table_clear(); + + if(rtl8367s_cpu_mac[0] !=0 || + rtl8367s_cpu_mac[1] !=0 || + rtl8367s_cpu_mac[2] !=0 || + rtl8367s_cpu_mac[3] !=0 || + rtl8367s_cpu_mac[4] !=0 || + rtl8367s_cpu_mac[5] !=0) + { + _rtl8367s_cpumac_refresh(); + } + +error: + RTL8367S_UNLOCK(); + + return ret; +} + +static int rtl8367s_notify_iso_change(struct net_device *br, struct net_device *dev, int iso) +{ + int p; + int cur_group; + int tmp_group; + int ret = 0; + + if(!br || !dev) + { + RTL8367S_LOG_ERR("br or dev null\r\n"); + return -1; + } + + if(!_rtl8367s_is_switch_device(dev)) + { + return 0; + } + + RTL8367S_LOG_DEBUG("%s %s %d\r\n", br->name, dev->name, iso); + + RTL8367S_LOCK(); + + p = _rtl8367s_device_to_pidx(dev); + + if(p < 0) + { + RTL8367S_LOG_DEBUG("wrong dev %s\r\n", dev->name); + ret = -1; + goto error; + } + + cur_group = rtl8367s_br_group[p]; + + tmp_group = br->ifindex; + + if(tmp_group != cur_group) + { + RTL8367S_LOG_ERR("not same group %d\r\n", cur_group); + ret = -1; + goto error; + } + + if(rtl8367s_iso_mode[p] == iso) + { + RTL8367S_LOG_ERR("same iso %d\r\n", iso); + ret = -1; + goto error; + } + + rtl8367s_iso_mode[p] = iso; + + if(rtl8367s_hw_bridge) + { + _rtl8367s_lookup_refresh(); + } + + rtk_l2_table_clear(); + + if(rtl8367s_cpu_mac[0] !=0 || + rtl8367s_cpu_mac[1] !=0 || + rtl8367s_cpu_mac[2] !=0 || + rtl8367s_cpu_mac[3] !=0 || + rtl8367s_cpu_mac[4] !=0 || + rtl8367s_cpu_mac[5] !=0) + { + _rtl8367s_cpumac_refresh(); + } +error: + RTL8367S_UNLOCK(); + + return ret; +} + + +static int rtl8367s_notify_mcr_change(struct net_device *br, struct net_device *dev, int mcr) +{ + int p; + int cur_group; + int tmp_group; + int ret = 0; + +// rtk_portmask_t portmask; + + if(!br || !dev) + { + RTL8367S_LOG_ERR("br or dev null\r\n"); + return -1; + } + + if(!_rtl8367s_is_switch_device(dev)) + { + return 0; + } + + RTL8367S_LOG_DEBUG("%s %s %d\r\n", br->name, dev->name, mcr); + + RTL8367S_LOCK(); + + p = _rtl8367s_device_to_pidx(dev); + + if(p < 0) + { + RTL8367S_LOG_DEBUG("wrong dev %s\r\n", dev->name); + ret = -1; + goto error; + } + + cur_group = rtl8367s_br_group[p]; + + tmp_group = br->ifindex; + + if(tmp_group != cur_group) + { + RTL8367S_LOG_ERR("not same bridge %d\r\n", cur_group); + ret = -1; + goto error; + } + + if(rtl8368s_mc_router[p] == mcr) + { + RTL8367S_LOG_ERR("same mcr %d\r\n", mcr); + ret = -1; + goto error; + } + + rtl8368s_mc_router[p] = mcr; + + if(rtl8367s_mcast_snoop) + { + _rtl8367s_mcast_mcr_refresh(); + } + +error: + RTL8367S_UNLOCK(); + + return ret; +} +#endif +#ifdef RTL8367S_HW_BRIDGE_PORT_VLAN_DETECT +static int rtl8367s_notify_vlan_change(struct net_device *dev, int add) +{ + int p; + int ret = 0; + + if(!dev) + { + RTL8367S_LOG_ERR("br or dev null\r\n"); + return -1; + } + + if(!_rtl8367s_is_switch_device(dev)) + { + return 0; + } + + RTL8367S_LOG_DEBUG("%s %d\r\n", dev->name, add); + + RTL8367S_LOCK(); + + p = _rtl8367s_device_to_pidx(dev); + + if(p < 0) + { + RTL8367S_LOG_DEBUG("wrong dev %s\r\n", dev->name); + ret = -1; + goto error; + } + + if(add) + { + rtl8367s_hw_bridge_vlan_port[p]++; + } + else + { + rtl8367s_hw_bridge_vlan_port[p]--; + if(rtl8367s_hw_bridge_vlan_port[p] < 0) + { + rtl8367s_hw_bridge_vlan_port[p] = 0; + RTL8367S_LOG_ERR("vlan_port %d below zero\r\n", p); + } + } + + if(rtl8367s_hw_bridge) + { + _rtl8367s_lookup_refresh(); + } + + if(rtl8367s_mcast_snoop) + { + _rtl8367s_mcast_mcr_refresh(); + } + + rtk_l2_table_clear(); + + if(rtl8367s_cpu_mac[0] !=0 || + rtl8367s_cpu_mac[1] !=0 || + rtl8367s_cpu_mac[2] !=0 || + rtl8367s_cpu_mac[3] !=0 || + rtl8367s_cpu_mac[4] !=0 || + rtl8367s_cpu_mac[5] !=0) + { + _rtl8367s_cpumac_refresh(); + } + +error: + RTL8367S_UNLOCK(); + + return ret; +} +#endif /* RTL8367S_HW_BRIDGE_PORT_VLAN_DETECT */ +#if 0 +static int rtl8367s_ethtool_get_settings(struct net_device * dev, struct ethtool_cmd * cmd) +{ + rtk_api_ret_t ret; + rtk_port_mac_ability_t ability; + int p; + + if(!dev || !cmd) + { + RTL8367S_LOG_ERR("dev or cmd null\r\n"); + return -1; + } + + if(!_rtl8367s_is_switch_device(dev)) + { + return 0; + } + + RTL8367S_LOG_DEBUG("dev=%s\r\n", dev->name); + + p = _rtl8367s_device_to_pidx(dev); + + if(p < 0) + { + RTL8367S_LOG_DEBUG("wrong dev %s\r\n", dev->name); + return -1; + } + + if((ret = rtk_port_macStatus_get(rtl8367s_utp_port[p], &ability) != RT_ERR_OK)) + { + RTL8367S_LOG_ERR("rtk_port_macStatus_get failed...ret=%d\n", ret); + return -1; + } + + if(ability.link == 0) + { + cmd->speed = 0; + cmd->duplex = DUPLEX_UNKNOWN; + return 0; + } + + switch(ability.speed) + { + case PORT_SPEED_10M: + cmd->speed = SPEED_10; + break; + + case PORT_SPEED_100M: + cmd->speed = SPEED_100; + break; + + case PORT_SPEED_1000M: + cmd->speed = SPEED_1000; + break; + + case PORT_SPEED_500M: + cmd->speed = 500; /* SPEED_500 not defined */ + break; + + case PORT_SPEED_2500M: + cmd->speed = SPEED_2500; + break; + + default: + RTL8367S_LOG_ERR("unknown ethernet speed (%d)\n", ability.speed); + cmd->speed = 0; + return -1; + } + + switch(ability.duplex) + { + case PORT_HALF_DUPLEX: + cmd->duplex = DUPLEX_HALF; + break; + + case PORT_FULL_DUPLEX: + cmd->duplex = DUPLEX_FULL; + break; + + default: + cmd->duplex = DUPLEX_UNKNOWN; + return -1; + } + + return 0; +} + +static int rtl8367s_dev_get_stats(struct net_device *dev, + struct rtnl_link_stats64 *storage) +{ + int p; + rtk_stat_counter_t cnt; + + if(!dev) + { + RTL8367S_LOG_ERR("dev or cmd null\r\n"); + return -1; + } + + if(!_rtl8367s_is_switch_device(dev)) + { + return 0; + } + + RTL8367S_LOG_DEBUG("dev=%s\r\n", dev->name); + + p = _rtl8367s_device_to_pidx(dev); + + if(p < 0) + { + RTL8367S_LOG_DEBUG("wrong dev %s\r\n", dev->name); + return -1; + } + + memset(storage, 0x0, sizeof(*storage)); + + if(RT_ERR_OK != rtk_stat_port_get(rtl8367s_utp_port[p], STAT_IfInUcastPkts, &cnt)) + { + RTL8367S_LOG_ERR("rtk_stat_port_get fail\r\n"); + return -1; + } + + storage->rx_packets += cnt; + + if(RT_ERR_OK != rtk_stat_port_get(rtl8367s_utp_port[p], STAT_IfInMulticastPkts, &cnt)) + { + RTL8367S_LOG_ERR("rtk_stat_port_get fail\r\n"); + return -1; + } + + storage->rx_packets += cnt; + storage->multicast += cnt; + + if(RT_ERR_OK != rtk_stat_port_get(rtl8367s_utp_port[p], STAT_IfInBroadcastPkts, &cnt)) + { + RTL8367S_LOG_ERR("rtk_stat_port_get fail\r\n"); + return -1; + } + + storage->rx_packets += cnt; + + if(RT_ERR_OK != rtk_stat_port_get(rtl8367s_utp_port[p], STAT_IfInOctets, &cnt)) + { + RTL8367S_LOG_ERR("rtk_stat_port_get fail\r\n"); + return -1; + } + + storage->rx_bytes += cnt; + + if(RT_ERR_OK != rtk_stat_port_get(rtl8367s_utp_port[p], STAT_IfOutUcastPkts, &cnt)) + { + RTL8367S_LOG_ERR("rtk_stat_port_get fail\r\n"); + return -1; + } + + storage->tx_packets += cnt; + + if(RT_ERR_OK != rtk_stat_port_get(rtl8367s_utp_port[p], STAT_IfOutMulticastPkts, &cnt)) + { + RTL8367S_LOG_ERR("rtk_stat_port_get fail\r\n"); + return -1; + } + + storage->tx_packets += cnt; + + if(RT_ERR_OK != rtk_stat_port_get(rtl8367s_utp_port[p], STAT_IfOutBroadcastPkts, &cnt)) + { + RTL8367S_LOG_ERR("rtk_stat_port_get fail\r\n"); + return -1; + } + + storage->tx_packets += cnt; + + if(RT_ERR_OK != rtk_stat_port_get(rtl8367s_utp_port[p], STAT_IfOutOctets, &cnt)) + { + RTL8367S_LOG_ERR("rtk_stat_port_get fail\r\n"); + return -1; + } + + storage->tx_bytes += cnt; + + return 0; + +} +#endif + +static int rtl8367s_phy_link_change_notify(void) +{ + rtk_api_ret_t ret; + rtk_port_mac_ability_t ability; + int link_status = 0; + int p; + + struct net_device* port_dev; + + for(p=PORT_IDX0; pname); + } + dev_put(port_dev); + } + } + return 0; +} + +static struct timer_list rtl8367s_phy_link_timer; + +static void rtl8367s_phy_link_work_cb(struct work_struct *work) +{ + rtl8367s_phy_link_change_notify(); + mod_timer(&rtl8367s_phy_link_timer, jiffies + msecs_to_jiffies(RTL8367S_PHY_LINK_CHECK_INTERVAL)); +} + +DECLARE_WORK(_rtl8367s_phy_link_work, rtl8367s_phy_link_work_cb); + +#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 19, 0) +static void rtl8367s_phy_link_timer_cb(unsigned long data) +#else +static void rtl8367s_phy_link_timer_cb(struct timer_list *tl) +#endif +{ + schedule_work(&_rtl8367s_phy_link_work); +} + +static void rtl8367s_phy_link_timer_start(void) +{ +#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 19, 0) + init_timer(&rtl8367s_phy_link_timer); + rtl8367s_phy_link_timer.function = rtl8367s_phy_link_timer_cb; +#else + timer_setup(&rtl8367s_phy_link_timer, rtl8367s_phy_link_timer_cb, 0); +#endif + rtl8367s_phy_link_timer.expires = jiffies + msecs_to_jiffies(RTL8367S_PHY_LINK_CHECK_INTERVAL); + add_timer(&rtl8367s_phy_link_timer); +} + +static ssize_t rtl8367s_switch_reg_write(struct file *file, const char __user *buffer, + size_t count, loff_t * pPos) +{ + char val_string[128]; + rtk_uint32 reg, val; + int argc=0; + + if (count > sizeof(val_string) - 1) + return -EINVAL; + if (copy_from_user(val_string, buffer, count)) + return -EFAULT; + + argc=sscanf(val_string, "%x %x", ®, &val); + if(argc!=1 && argc!=2) + { + printk("usage: reg [val]\n"); + return count; + } + + if(argc==2) + { +#ifdef CONFIG_TP_EXT_SWITCH_RTL8367S_SINGLE + if(RT_ERR_OK != rtl8367c_setAsicReg(reg, val)) +#else + if(RT_ERR_OK != RT_MAPPER->asic_setAsicReg(reg, val)) +#endif + + { + RTL8367S_LOG_ERR("rtl8367c_setAsicReg error\r\n"); + } + } + +#ifdef CONFIG_TP_EXT_SWITCH_RTL8367S_SINGLE + if(RT_ERR_OK != rtl8367c_getAsicReg(reg, &val)) +#else + if(RT_ERR_OK != RT_MAPPER->asic_getAsicReg(reg, &val)) +#endif + { + RTL8367S_LOG_ERR("rtl8367c_getAsicReg error\r\n"); + } + + RTL8367S_LOG_INFO("reg[%08x]=%08x\r\n", reg, val); + + return count; +} + +static struct file_operations rtl8367s_switch_reg_fops = { + .owner = THIS_MODULE, + .open = NULL, + .read = NULL, + .write = rtl8367s_switch_reg_write, + .llseek = NULL, + .release = NULL, +}; + + +static ssize_t rtl8367s_phy_reg_write(struct file *file, const char __user *buffer, + size_t count, loff_t * pPos) +{ + char val_string[128]; + rtk_uint32 phy, reg, val; + int argc=0; + + if (count > sizeof(val_string) - 1) + return -EINVAL; + if (copy_from_user(val_string, buffer, count)) + return -EFAULT; + + argc=sscanf(val_string, "%d %x %x", &phy, ®, &val); + if(argc!=2 && argc!=3) + { + printk("usage: phy reg [val]\n"); + return count; + } + + if(argc==3) + { + if(RT_ERR_OK != rtk_port_phyReg_set(rtl8367s_utp_port[phy], reg, val)) + { + RTL8367S_LOG_ERR("rtk_port_phyReg_set error\r\n"); + } + } + + if(RT_ERR_OK != rtk_port_phyReg_get(rtl8367s_utp_port[phy], reg, &val)) + { + RTL8367S_LOG_ERR("rtk_port_phyReg_get error\r\n"); + } + + RTL8367S_LOG_INFO("phy=%d reg[%08x]=%08x\r\n", phy, reg, val); + + return count; +} + +static struct file_operations rtl8367s_phy_reg_fops = { + .owner = THIS_MODULE, + .open = NULL, + .read = NULL, + .write = rtl8367s_phy_reg_write, + .llseek = NULL, + .release = NULL, +}; + +static int rtl8367s_phy_status_get(struct seq_file *s, void *unused) +{ + char *speed_str[] = {"10M", "100M", "1000M", "500M", "2.5G", "None"}; + char *duplex_str[] = {"HD", "FD", "None"}; + + rtk_port_linkStatus_t pLinkStatus[PORT_MAX_NUM] = {0}; + rtk_port_speed_t pSpeed[PORT_MAX_NUM] = {0}; + rtk_port_duplex_t pDuplex[PORT_MAX_NUM] = {0}; + int ret = 0; + int p = 0; + + for(p=0; pf_path.dentry->d_iname); +} + +static struct file_operations rtl8367s_phy_status_fops = { + .owner = THIS_MODULE, + .open = rtl8367s_phy_status_open, + .read = seq_read, + .write = NULL, + .llseek = seq_lseek, + .release = single_release, +}; + + + + +static rtk_api_ret_t rtl8367s_phy_Patch_set(rtk_uint32 opt) +{ +#define RTL8367C_PHY_CONTROL 0 + + rtk_api_ret_t retVal = -1; + rtk_uint32 port = 0; + rtk_uint32 data = 0; + + if (opt != 0 && opt != 1) + return RT_ERR_FAILED; + + for (port = 0; port <= 4; port++) { +#ifdef CONFIG_TP_EXT_SWITCH_RTL8367S_SINGLE + if ((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xA42C, &data)) != RT_ERR_OK) +#else + if ((retVal = RT_MAPPER->asic_getAsicPHYOCPReg(port, 0xA42C, &data)) != RT_ERR_OK) +#endif + return retVal; + + data |= 0x0010; +#ifdef CONFIG_TP_EXT_SWITCH_RTL8367S_SINGLE + if ((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xA42C, data)) != RT_ERR_OK) +#else + if ((retVal = RT_MAPPER->asic_setAsicPHYOCPReg(port, 0xA42C, data)) != RT_ERR_OK) +#endif + return retVal; + + if (opt == 0) { +#ifdef CONFIG_TP_EXT_SWITCH_RTL8367S_SINGLE + if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xBC02, 0x00D0)) != RT_ERR_OK) +#else + if((retVal = RT_MAPPER->asic_setAsicPHYOCPReg(port, 0xBC02, 0x00D0)) != RT_ERR_OK) +#endif + return retVal; + } + else { +#ifdef CONFIG_TP_EXT_SWITCH_RTL8367S_SINGLE + if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xBC02, 0x00F0)) != RT_ERR_OK) +#else + if((retVal = RT_MAPPER->asic_setAsicPHYOCPReg(port, 0xBC02, 0x00F0)) != RT_ERR_OK) +#endif + return retVal; + } + +#ifdef CONFIG_TP_EXT_SWITCH_RTL8367S_SINGLE + if((retVal = rtl8367c_getAsicPHYReg(port, RTL8367C_PHY_CONTROL, &data)) != RT_ERR_OK) +#else + if ((retVal = RT_MAPPER->asic_getAsicPHYReg(port, RTL8367C_PHY_CONTROL, &data)) != RT_ERR_OK) +#endif + return retVal; + + data |= (0x0001 << 9); +#ifdef CONFIG_TP_EXT_SWITCH_RTL8367S_SINGLE + if((retVal = rtl8367c_setAsicPHYReg(port, RTL8367C_PHY_CONTROL, data)) != RT_ERR_OK) +#else + if ((retVal = RT_MAPPER->asic_setAsicPHYReg(port, RTL8367C_PHY_CONTROL, data)) != RT_ERR_OK) +#endif + return retVal; + } + + return RT_ERR_OK; +} + +static int rtl8367s_mii_type_get(struct seq_file *s, void *unused) +{ + seq_printf(s, "%d\n", rtl8367s_mii_type); + return 0; +} + +static int rtl8367s_mii_type_open(struct inode *inode, struct file *file) +{ + return single_open(file, rtl8367s_mii_type_get, file->f_path.dentry->d_iname); +} + +static ssize_t rtl8367s_mii_type_write(struct file *file, const char __user *buffer, + size_t count, loff_t * pPos) +{ + char val_string[128]; + rtk_uint32 val; + + if (count > sizeof(val_string) - 1) + return -EINVAL; + if (copy_from_user(val_string, buffer, count)) + return -EFAULT; + + if (sscanf(val_string, "%d", &val) != 1) + { + printk("usage: \n"); + return count; + } + + RTL8367S_LOCK(); + + if(rtl8367s_mii_type == val) + { + RTL8367S_LOG_ERR("same mii_type %d\n", val); + goto error; + } + + rtl8367s_mii_type = val; + + _rtl8367s_mii_type_refresh(); + +error: + RTL8367S_UNLOCK(); + + return count; +} + + +static struct file_operations rtl8367s_mii_type_fops = { + .owner = THIS_MODULE, + .open = rtl8367s_mii_type_open, + .read = seq_read, + .write = rtl8367s_mii_type_write, + .llseek = seq_lseek, + .release = single_release, +}; + +static int rtl8367s_ucast_tbl_get(struct seq_file *s, void *unused) +{ + rtk_uint32 address=0; + rtk_l2_ucastAddr_t ucastAddr; + + while(1) + { + if(RT_ERR_OK != rtk_l2_addr_next_get(READMETHOD_NEXT_L2UC, UTP_PORT0, &address, &ucastAddr)) + { + break; + } + seq_printf(s, + "%04d) mac=%02x-%02x-%02x-%02x-%02x-%02x, ivl=%d, fid=%d, efid=%d, cvid=%04x, static=%d, prio=%d, port=%d\n", + ucastAddr.address, + ucastAddr.mac.octet[0], + ucastAddr.mac.octet[1], + ucastAddr.mac.octet[2], + ucastAddr.mac.octet[3], + ucastAddr.mac.octet[4], + ucastAddr.mac.octet[5], + ucastAddr.ivl, + ucastAddr.fid, + ucastAddr.efid, + ucastAddr.cvid, + ucastAddr.is_static, + ucastAddr.priority, + ucastAddr.port); + + address++; + } + + return 0; +} + +static int rtl8367s_ucast_tbl_open(struct inode *inode, struct file *file) +{ + return single_open(file, rtl8367s_ucast_tbl_get, file->f_path.dentry->d_iname); +} + + +static ssize_t rtl8367s_ucast_tbl_write(struct file *file, const char __user *buffer, + size_t count, loff_t * pPos) +{ + char val_string[128]; + rtk_uint32 val; + rtk_uint32 address=0; + rtk_l2_ucastAddr_t ucastAddr; + + if (count > sizeof(val_string) - 1) + return -EINVAL; + if (copy_from_user(val_string, buffer, count)) + return -EFAULT; + + if (sscanf(val_string, "%d", &val) != 1) + { + printk("usage: -1: delete all entry, (0~...): delete specific entry\n"); + return count; + } + + if(val < 0) + { + while(1) + { + address=0; + if(RT_ERR_OK != rtk_l2_addr_next_get(READMETHOD_NEXT_L2UC, UTP_PORT0, &address, &ucastAddr)) + { + RTL8367S_LOG_ERR("rtk_l2_addr_next_get fail\r\n"); + break; + } + rtk_l2_addr_del(&ucastAddr.mac, &ucastAddr); + } + printk("rtk_l2_addr_del delete all done\r\n"); + } + else + { + address=val; + if(RT_ERR_OK != rtk_l2_addr_next_get(READMETHOD_NEXT_L2UC, UTP_PORT0, &address, &ucastAddr)) + { + RTL8367S_LOG_ERR("rtk_l2_addr_next_get fail\r\n"); + return count; + } + rtk_l2_addr_del(&ucastAddr.mac, &ucastAddr); + + printk("rtk_l2_addr_del %02x-%02x-%02x-%02x-%02x-%02x done\r\n", + ucastAddr.mac.octet[0], ucastAddr.mac.octet[1], ucastAddr.mac.octet[2], \ + ucastAddr.mac.octet[3], ucastAddr.mac.octet[4], ucastAddr.mac.octet[5]); + } + + return count; +} + + +static struct file_operations rtl8367s_ucast_tbl_fops = { + .owner = THIS_MODULE, + .open = rtl8367s_ucast_tbl_open, + .read = seq_read, + .write = rtl8367s_ucast_tbl_write, + .llseek = seq_lseek, + .release = single_release, +}; + +static int rtl8367s_mcast_tbl_get(struct seq_file *s, void *unused) +{ + rtk_uint32 address=0; + rtk_l2_ipMcastAddr_t ipMcastAddr; +#if 0 + rtk_l2_ipVidMcastAddr_t ipvidMcastAddr; +#endif + rtk_l2_mcastAddr_t l2McastAddr; + + seq_printf(s, "================IPv4 Mcast Address===========\r\n"); + + while(1) + { + if(RT_ERR_OK != rtk_l2_ipMcastAddr_next_get(&address, &ipMcastAddr)) + { + break; + } + + ipMcastAddr.dip |= 0xe0000000; + + seq_printf(s, "dip=0x%08x, sip=0x%08x, asic=%d index=%d ports=0x%08x\n", + ipMcastAddr.dip, ipMcastAddr.sip, ipMcastAddr.igmp_asic, ipMcastAddr.igmp_index, ipMcastAddr.portmask.bits[0]); + + address++; + } + +#if 0 + seq_printf(s, "================IPv4 VID Mcast Address===========\r\n"); + + address=0; + while(1) + { + if(RT_ERR_OK != rtk_l2_ipVidMcastAddr_next_get(&address, &ipvidMcastAddr)) + { + break; + } + + ipvidMcastAddr.dip |= 0xe0000000; + + seq_printf(s, "dip=0x%08x, sip=0x%08x, vid=%d port=0x%08x\n", + ipvidMcastAddr.dip, ipvidMcastAddr.sip, ipvidMcastAddr.vid, ipvidMcastAddr.portmask.bits[0]); + + address++; + } +#endif + + seq_printf(s, "================IPv6 Mcast Address===========\r\n"); + + address=0; + while(1) + { + if(RT_ERR_OK != rtk_l2_mcastAddr_next_get(&address, &l2McastAddr)) + { + break; + } + + seq_printf(s, "mac=%02x-%02x-%02x-%02x-%02x-%02x fid=%d ivl=%d vid=%04x asic=%d index=%d ports=0x%08x\n", + l2McastAddr.mac.octet[0], l2McastAddr.mac.octet[1], l2McastAddr.mac.octet[2], + l2McastAddr.mac.octet[3], l2McastAddr.mac.octet[4], l2McastAddr.mac.octet[5], + l2McastAddr.fid, l2McastAddr.ivl, l2McastAddr.vid, l2McastAddr.igmp_asic, l2McastAddr.igmp_index, + l2McastAddr.portmask.bits[0]); + + address++; + } + + return 0; + +} + +static int rtl8367s_mcast_tbl_open(struct inode *inode, struct file *file) +{ + return single_open(file, rtl8367s_mcast_tbl_get, file->f_path.dentry->d_iname); +} + + +static ssize_t rtl8367s_mcast_tbl_write(struct file *file, const char __user *buffer, + size_t count, loff_t * pPos) +{ + char val_string[128]; + rtk_uint32 val; + + rtk_uint32 address=0; + rtk_l2_ipMcastAddr_t ipMcastAddr; + rtk_l2_mcastAddr_t l2McastAddr; + + if (count > sizeof(val_string) - 1) + return -EINVAL; + if (copy_from_user(val_string, buffer, count)) + return -EFAULT; + + if (sscanf(val_string, "%d", &val) != 1) + { + printk("usage: \n"); + return count; + } + + memset(&ipMcastAddr, 0x0, sizeof(ipMcastAddr)); + + while(1) + { + address = 0; + if(RT_ERR_OK != rtk_l2_ipMcastAddr_next_get(&address, &ipMcastAddr)) + { + break; + } + + ipMcastAddr.dip |= 0xe0000000; + + if(RT_ERR_OK != rtk_l2_ipMcastAddr_del(&ipMcastAddr)) + { + RTL8367S_LOG_ERR("rtk_l2_ipMcastAddr_del fail\r\n"); + } + } + + while(1) + { + address = 0; + if(RT_ERR_OK != rtk_l2_mcastAddr_next_get(&address, &l2McastAddr)) + { + break; + } + + if(RT_ERR_OK != rtk_l2_mcastAddr_del(&l2McastAddr)) + { + RTL8367S_LOG_ERR("rtk_l2_mcastAddr_del fail\r\n"); + } + } + + return count; +} + + +static struct file_operations rtl8367s_mcast_tbl_fops = { + .owner = THIS_MODULE, + .open = rtl8367s_mcast_tbl_open, + .read = seq_read, + .write = rtl8367s_mcast_tbl_write, + .llseek = seq_lseek, + .release = single_release, +}; + + +static int rtl8367s_mcast_snoop_get(struct seq_file *s, void *unused) +{ + int p; + + seq_printf(s, "mcast_snoop = %d\n", rtl8367s_mcast_snoop); + + seq_printf(s,"============================\n"); + + for(p=PORT_IDX0; pf_path.dentry->d_iname); +} + + +static ssize_t rtl8367s_mcast_snoop_write(struct file *file, const char __user *buffer, + size_t count, loff_t * pPos) +{ + char val_string[128]; + rtk_uint32 val, pidx; + int argc=0; + + if (count > sizeof(val_string) - 1) + return -EINVAL; + + if (copy_from_user(val_string, buffer, count)) + return -EFAULT; + + argc= sscanf(val_string, "%d %d", &val, &pidx); + + if (argc != 1 && argc !=2) + { + printk("usage: enable [ port ]\n"); + return count; + } + + RTL8367S_LOCK(); + + if(argc == 1) + { + if(rtl8367s_mcast_snoop == val) + { + RTL8367S_LOG_ERR("same mcast_snoop %d\r\n", val); + goto error; + } + + rtl8367s_mcast_snoop = val; + + _rtl8367s_mcast_refresh(); + } + else if(argc == 2) + { + if(pidx <0 || pidx >= PORT_MAX_NUM) + { + RTL8367S_LOG_ERR("pidx out of range %d\n", pidx); + goto error; + } + + if(rtl8367s_br_group[pidx] >= 0) + { + RTL8367S_LOG_ERR("do not change bridge port's mc_router\n"); + goto error; + } + + if(rtl8368s_mc_router[pidx] == val) + { + RTL8367S_LOG_ERR("same mc_router %d\n", val); + goto error; + } + + rtl8368s_mc_router[pidx] = val; + + if(rtl8367s_mcast_snoop) + { + _rtl8367s_mcast_mcr_refresh(); + } + } + else + { + RTL8367S_LOG_ERR("wrong argc %d\n", argc); + goto error; + } + +error: + RTL8367S_UNLOCK(); + + return count; +} + + +static struct file_operations rtl8367s_mcast_snoop_fops = { + .owner = THIS_MODULE, + .open = rtl8367s_mcast_snoop_open, + .read = seq_read, + .write = rtl8367s_mcast_snoop_write, + .llseek = seq_lseek, + .release = single_release, +}; + + + +static int rtl8367s_port_mirror_get(struct seq_file *s, void *unused) +{ + seq_printf(s, "port_mirror = %d\n", rtl8367s_port_mirror); + + return 0; +} + +static int rtl8367s_port_mirror_open(struct inode *inode, struct file *file) +{ + return single_open(file, rtl8367s_port_mirror_get, file->f_path.dentry->d_iname); +} + + +static ssize_t rtl8367s_port_mirror_write(struct file *file, const char __user *buffer, + size_t count, loff_t * pPos) +{ + char val_string[128]; + int argc; + + int val, ming_port, mred_port, isolation; + rtk_portmask_t txmask, rxmask; + + if (count > sizeof(val_string) - 1) + return -EINVAL; + if (copy_from_user(val_string, buffer, count)) + return -EFAULT; + + argc = sscanf(val_string, "%d %d %d %d", &val, &ming_port, &mred_port, &isolation); + if(argc!=1 && argc!=4) + { + printk("usage: mirror_en [mirroring_port] [mirrored_port] [isolation]\n"); + return count; + } + + if(val) + { + if(argc < 4) + { + RTL8367S_LOG_ERR("missing mirroring_port mirrored_port isolation\r\n"); + return count; + } + + if(ming_port == mred_port) + { + RTL8367S_LOG_ERR("mirroring_port same with mirrored_port\r\n"); + return count; + } + + if(ming_port < PORT_IDX0 || ming_port >= PORT_MAX_NUM) + { + RTL8367S_LOG_ERR("mirroring_port out of range\r\n"); + return count; + } + + memset(&txmask, 0x0, sizeof(txmask)); + memset(&rxmask, 0x0, sizeof(rxmask)); + if(mred_port < PORT_IDX0 || mred_port >= PORT_MAX_NUM) + { + RTL8367S_LOG_INFO("mirror cpu port -> utp port%d\r\n", ming_port); + + txmask.bits[0] |= (1< utp port%d\r\n", mred_port, ming_port); + txmask.bits[0] |= (1<f_path.dentry->d_iname); +} + +static ssize_t rtl8367s_mib_cnt_write(struct file *file, const char __user *buffer, + size_t count, loff_t * pPos) +{ + char val_string[128]; + rtk_uint32 val; + + rtk_port_t p; + + if (count > sizeof(val_string) - 1) + return -EINVAL; + if (copy_from_user(val_string, buffer, count)) + return -EFAULT; + + if (sscanf(val_string, "%d", &val) != 1) + { + printk("usage: \n"); + return count; + } + + /* reset counter */ + RTK_SCAN_ALL_LOG_PORT(p) + { + if(RT_ERR_OK != rtk_stat_port_reset(p)) + { + RTL8367S_LOG_ERR("rtk_stat_port_reset fail\r\n"); + return 0; + } + } + RTL8367S_LOG_ERR("rtk_stat_port_reset success\r\n"); + return count; +} + + +static struct file_operations rtl8367s_mib_cnt_fops = { + .owner = THIS_MODULE, + .open = rtl8367s_mib_cnt_open, + .read = seq_read, + .write = rtl8367s_mib_cnt_write, + .llseek = seq_lseek, + .release = single_release, +}; + +static int rtl8367s_mib_cnt_partila_get(struct seq_file *s, void *unused) +{ + const char* port_strs[] = { + "UTP0", + "UTP1", + "UTP2", + "UTP3", + "UTP4", + "EXT0", + "EXT1", + }; + + const rtk_port_t ports[] = { + UTP_PORT0, + UTP_PORT1, + UTP_PORT2, + UTP_PORT3, + UTP_PORT4, + EXT_PORT0, + EXT_PORT1, + }; + + const char* ptype_strs[] = { + "InUcast ", + "InMulticast ", + "InBroadcast ", + + "OutUcast ", + "OutMulticast", + "OutBroadcast", + #if 0 + "InMLDSQuery ", + "InMLDGQuery ", + "InMLDLeaves ", + "InMLDJoinOK ", + "InMLDJoinFai", + "InMLDChkErr", + + "OutMLDReport", + "OutMLDLeaves", + "OutMLDGQuery", + "OutMLDSQuery", + + "InIGMPSQuery", + "InIGMPGQuery", + "InIGMPLeaves", + "InIGMPJoinOK", + "InIGMPJoinFai", + "InIGMPChkErr", + + "OutIGMPReport", + "OutIGMPLeaves", + "OutIGMPGQuery", + "OutIGMPSQuery", + + "InKnownMcast", + + "FCSErrors", + "SymbolErrors", + "SingleCollision", + "MultiCollision", + "DeferredTrans", + "LateCollision", + "ExcesCollisions", + + "InPauseFrames", + "OutPauseFrames", + #endif + "InOctets", + "OutOctets", + }; + + const rtk_stat_port_type_t ptypes[] = { + STAT_IfInUcastPkts, + STAT_IfInMulticastPkts, + STAT_IfInBroadcastPkts, + + STAT_IfOutUcastPkts, + STAT_IfOutMulticastPkts, + STAT_IfOutBroadcastPkts, + #if 0 + STAT_InMldSpecificQuery, + STAT_InMldGeneralQuery, + STAT_InMldLeaves, + STAT_InMldJoinsSuccess, + STAT_InMldJoinsFail, + STAT_InMldChecksumError, + + STAT_OutMldReports, + STAT_OutMldLeaves, + STAT_OutMldGeneralQuery, + STAT_OutMldSpecificQuery, + + STAT_InIgmpSpecificQuery, + STAT_InIgmpGeneralQuery, + STAT_InIgmpInterfaceLeaves, + STAT_InIgmpJoinsSuccess, + STAT_InIgmpJoinsFail, + STAT_InIgmpChecksumError, + + STAT_OutIgmpReports, + STAT_OutIgmpLeaves, + STAT_OutIgmpGeneralQuery, + STAT_OutIgmpSpecificQuery, + + STAT_InKnownMulticastPkts, + + STAT_Dot3StatsFCSErrors, + STAT_Dot3StatsSymbolErrors, + STAT_Dot3StatsSingleCollisionFrames, + STAT_Dot3StatsMultipleCollisionFrames, + STAT_Dot3StatsDeferredTransmissions, + STAT_Dot3StatsLateCollisions, + STAT_Dot3StatsExcessiveCollisions, + + STAT_Dot3InPauseFrames, + STAT_Dot3OutPauseFrames, + #endif + STAT_IfInOctets, + STAT_IfOutOctets, + }; + + static rtk_stat_counter_t counters[sizeof(ports)/sizeof(ports[0])] + [sizeof(ptypes)/sizeof(ptypes[0])] = { 0 }; + + int p = 0; + int t = 0; + + rtk_stat_counter_t cnt; + + seq_printf(s, "MIB Counter\t\t"); + + for(p=0; p<(sizeof(ports)/sizeof(ports[0])); p++) + { + seq_printf(s, "%s\t\t", port_strs[p]); + } + seq_printf(s, "\r\n"); + + for(t=0; t<(sizeof(ptypes)/sizeof(ptypes[0])); t++) + { + seq_printf(s, "%s\t\t", ptype_strs[t]); + + for(p=0; p<(sizeof(ports)/sizeof(ports[0])); p++) + { + if(RT_ERR_OK != rtk_stat_port_get(ports[p], ptypes[t], &cnt)) + { + RTL8367S_LOG_ERR("rtk_stat_port_get fail %s %s\r\n", port_strs[p], ptype_strs[t]); + goto next; + } + + seq_printf(s, "%lld\t\t", (rtk_int64)(cnt-counters[p][t])); + counters[p][t] = cnt; + } + + seq_printf(s, "\r\n"); + } + +next: + +#if 0 + /* reset counter */ + for(p=0; p<(sizeof(ports)/sizeof(ports[0])); p++) + { + if(RT_ERR_OK != rtk_stat_port_reset(ports[p])) + { + RTL8367S_LOG_ERR("rtk_stat_port_reset fail %s\r\n", port_strs[p]); + } + } +#endif + + return 0; +} + +static int rtl8367s_mib_cnt_partial_open(struct inode *inode, struct file *file) +{ + return single_open(file, rtl8367s_mib_cnt_partila_get, file->f_path.dentry->d_iname); +} + +static ssize_t rtl8367s_mib_cnt_partial_write(struct file *file, const char __user *buffer, + size_t count, loff_t * pPos) +{ + char val_string[128]; + rtk_uint32 val; + + rtk_port_t p; + + if (count > sizeof(val_string) - 1) + return -EINVAL; + if (copy_from_user(val_string, buffer, count)) + return -EFAULT; + + if (sscanf(val_string, "%d", &val) != 1) + { + printk("usage: \n"); + return count; + } + + /* reset counter */ + RTK_SCAN_ALL_LOG_PORT(p) + { + if(RT_ERR_OK != rtk_stat_port_reset(p)) + { + RTL8367S_LOG_ERR("rtk_stat_port_reset fail\r\n"); + return 0; + } + } + + return count; +} + +static struct file_operations rtl8367s_mib_cnt_partial_fops = { + .owner = THIS_MODULE, + .open = rtl8367s_mib_cnt_partial_open, + .read = seq_read, + .write = rtl8367s_mib_cnt_partial_write, + .llseek = seq_lseek, + .release = single_release, +}; + +static int rtl8367s_hw_bridge_get(struct seq_file *s, void *unused) +{ + rtk_portmask_t permitPort; + rtk_svlan_memberCfg_t svlanCfg; + rtk_uint32 vid; + rtk_uint32 fid; + + int p; + int ret = 0; + + seq_printf(s, "hw_bridge=%d\n", rtl8367s_hw_bridge); + seq_printf(s, "hw_bridge_port="); + for(p=PORT_IDX0; pf_path.dentry->d_iname); +} + +static ssize_t rtl8367s_hw_bridge_write(struct file *file, const char __user *buffer, + size_t count, loff_t * pPos) +{ + char val_string[128]; + rtk_uint32 val, pidx; + int argc=0; + + if (count > sizeof(val_string) - 1) + return -EINVAL; + + if (copy_from_user(val_string, buffer, count)) + return -EFAULT; + + argc= sscanf(val_string, "%d %d", &val, &pidx); + if (argc != 1 && argc !=2) + { + printk("usage: enable [ port ]\n"); + return count; + } + + RTL8367S_LOCK(); + + if(argc == 1) + { + if(rtl8367s_hw_bridge == val) + { + RTL8367S_LOG_ERR("same hw_bridge %d\n", val); + goto error; + } + + rtl8367s_hw_bridge = val; + } + else if(argc == 2) + { + if(pidx <0 || pidx >= PORT_MAX_NUM) + { + RTL8367S_LOG_ERR("pidx out of range %d\n", pidx); + goto error; + } + + if(rtl8367s_hw_bridge_port[pidx] == val) + { + RTL8367S_LOG_ERR("same hw_bridge_port %d\n", val); + goto error; + } + + rtl8367s_hw_bridge_port[pidx] = val; + } + else + { + RTL8367S_LOG_ERR("wrong argc %d\n", argc); + goto error; + } + + _rtl8367s_lookup_refresh(); + + rtk_l2_table_clear(); + + if(rtl8367s_cpu_mac[0] !=0 || + rtl8367s_cpu_mac[1] !=0 || + rtl8367s_cpu_mac[2] !=0 || + rtl8367s_cpu_mac[3] !=0 || + rtl8367s_cpu_mac[4] !=0 || + rtl8367s_cpu_mac[5] !=0) + { + _rtl8367s_cpumac_refresh(); + } + +error: + RTL8367S_UNLOCK(); + + return count; +} + + +static struct file_operations rtl8367s_hw_bridge_fops = { + .owner = THIS_MODULE, + .open = rtl8367s_hw_bridge_open, + .read = seq_read, + .write = rtl8367s_hw_bridge_write, + .llseek = seq_lseek, + .release = single_release, +}; + + +static int rtl8367s_eth_forward_get(struct seq_file *s, void *unused) +{ + seq_printf(s, "eth_forward=%d\n", rtl8367s_eth_forward); + + return 0; +} + +static int rtl8367s_eth_forward_open(struct inode *inode, struct file *file) +{ + return single_open(file, rtl8367s_eth_forward_get, file->f_path.dentry->d_iname); +} + +static ssize_t rtl8367s_eth_forward_write_proc(struct file *file, const char __user *buffer, + size_t count, loff_t * pPos) +{ + char val_string[128]; + rtk_uint32 val; + + if (count > sizeof(val_string) - 1) + return -EINVAL; + if (copy_from_user(val_string, buffer, count)) + return -EFAULT; + + if (sscanf(val_string, "%d", &val) != 1) + { + printk("usage: \n"); + return count; + } + + RTL8367S_LOCK(); + + if(rtl8367s_eth_forward == val) + { + RTL8367S_LOG_ERR("same eth_forward %d\n", val); + goto error; + } + + rtl8367s_eth_forward = val; + + _rtl8367s_lookup_refresh(); + + rtk_l2_table_clear(); + +error: + RTL8367S_UNLOCK(); + + return count; +} + +static struct file_operations rtl8367s_eth_forward_fops = { + .owner = THIS_MODULE, + .open = rtl8367s_eth_forward_open, + .read = seq_read, + .write = rtl8367s_eth_forward_write_proc, + .llseek = seq_lseek, + .release = single_release, +}; + +static int rtl8367s_cpu_mac_get(struct seq_file *s, void *unused) +{ + seq_printf(s, "cpu_mac=%02x:%02x:%02x:%02x:%02x:%02x\n", + rtl8367s_cpu_mac[0], rtl8367s_cpu_mac[1], rtl8367s_cpu_mac[2], + rtl8367s_cpu_mac[3], rtl8367s_cpu_mac[4], rtl8367s_cpu_mac[5]); + + return 0; +} + +static int rtl8367s_cpu_mac_open(struct inode *inode, struct file *file) +{ + return single_open(file, rtl8367s_cpu_mac_get, file->f_path.dentry->d_iname); +} + +static ssize_t rtl8367s_cpu_mac_write_proc(struct file *file, const char __user *buffer, + size_t count, loff_t * pPos) +{ + char val_string[128]; + unsigned char mac[6]; + + if (count > sizeof(val_string) - 1) + return -EINVAL; + if (copy_from_user(val_string, buffer, count)) + return -EFAULT; + + if (sscanf(val_string, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", + &mac[0],&mac[1],&mac[2],&mac[3],&mac[4],&mac[5]) != 6) + { + printk("usage: \n"); + return count; + } + + RTL8367S_LOCK(); + + if(memcmp(rtl8367s_cpu_mac, mac, sizeof(rtl8367s_cpu_mac)) == 0) + { + RTL8367S_LOG_ERR("same cpu_mac %02x%02x%02x%02x%02x%02x\n", + mac[0],mac[1],mac[2],mac[3],mac[4],mac[5]); + goto error; + } + + memcpy(rtl8367s_cpu_mac, mac, sizeof(rtl8367s_cpu_mac)); + + rtk_l2_table_clear(); + + if(rtl8367s_cpu_mac[0] !=0 || + rtl8367s_cpu_mac[1] !=0 || + rtl8367s_cpu_mac[2] !=0 || + rtl8367s_cpu_mac[3] !=0 || + rtl8367s_cpu_mac[4] !=0 || + rtl8367s_cpu_mac[5] !=0) + { + _rtl8367s_cpumac_refresh(); + } + +error: + RTL8367S_UNLOCK(); + + return count; +} + +static struct file_operations rtl8367s_cpu_mac_fops = { + .owner = THIS_MODULE, + .open = rtl8367s_cpu_mac_open, + .read = seq_read, + .write = rtl8367s_cpu_mac_write_proc, + .llseek = seq_lseek, + .release = single_release, +}; + +#ifdef RTL8367S_HW_LED_FUNCTION + +static int rtl8367s_hw_led_get(struct seq_file *s, void *unused) +{ + seq_printf(s,"hw_led=%d\n", rtl8367s_hw_led); + + return 0; +} + +static int rtl8367s_hw_led_open(struct inode *inode, struct file *file) +{ + return single_open(file, rtl8367s_hw_led_get, file->f_path.dentry->d_iname); +} + +static ssize_t rtl8367s_hw_led_write(struct file *file, const char __user *buffer, + size_t count, loff_t * pPos) +{ + char val_string[128]; + rtk_uint32 val; + + if (count > sizeof(val_string) - 1) + return -EINVAL; + if (copy_from_user(val_string, buffer, count)) + return -EFAULT; + + if (sscanf(val_string, "%d", &val) != 1) + { + printk("usage: \n"); + return count; + } + + RTL8367S_LOCK(); + + if(rtl8367s_hw_led == val) + { + RTL8367S_LOG_ERR("same led config %d\n", val); + goto error; + } + + rtl8367s_hw_led = val; + + _rtl8367s_hw_led_refresh(); + +error: + RTL8367S_UNLOCK(); + + return count; +} + +static struct file_operations rtl8367s_hw_led_fops = { + .owner = THIS_MODULE, + .open = rtl8367s_hw_led_open, + .read = seq_read, + .write = rtl8367s_hw_led_write, + .llseek = seq_lseek, + .release = single_release, +}; + +#endif /* RTL8367S_HW_LED_FUNCTION */ + + +static int rtl8367s_debug_info_get(struct seq_file *s, void *unused) +{ + seq_printf(s,"debug_info=%d\n", rtl8367s_debug_info); + + return 0; +} + +static int rtl8367s_debug_info_open(struct inode *inode, struct file *file) +{ + return single_open(file, rtl8367s_debug_info_get, file->f_path.dentry->d_iname); +} + + +static ssize_t rtl8367s_debug_info_write(struct file *file, const char __user *buffer, + size_t count, loff_t * pPos) +{ + char val_string[128]; + rtk_uint32 val; + + if (count > sizeof(val_string) - 1) + return -EINVAL; + if (copy_from_user(val_string, buffer, count)) + return -EFAULT; + + if (sscanf(val_string, "%d", &val) != 1) + { + printk("usage: \n"); + return count; + } + + rtl8367s_debug_info = val; + + return count; +} + +static struct file_operations rtl8367s_debug_info_fops = { + .owner = THIS_MODULE, + .open = rtl8367s_debug_info_open, + .read = seq_read, + .write = rtl8367s_debug_info_write, + .llseek = seq_lseek, + .release = single_release, +}; + + +static ssize_t rtl8367s_vlan_write(struct file *filp, const char __user *ubuf, + size_t usize, loff_t * off) +{ + int ret = -1; + //rtk_enable_t enable = RTK_ENABLE_END; + rtk_uint32 port = 0; + rtk_vlan_acceptFrameType_t type = ACCEPT_FRAME_TYPE_ALL; + rtk_vlan_t vid = 0; + rtk_vlan_cfg_t vlanCfg; + rtk_uint32 member = 0; + rtk_uint32 untag = 0; + rtk_vlan_cfg_t vlan; + char buf[16] = {0}; + char *pBuf = NULL; + char *cmd = NULL; + int cmdLen = 0; + char *substr = NULL; + + + char val_string[128]; + + if (usize > sizeof(val_string) - 1) + return -EINVAL; + if (copy_from_user(val_string, ubuf, usize)) + return -EFAULT; + + printk("cmd is %s\n", val_string); + + switch (val_string[0]) { + case 'i': + cmd = "init"; + cmdLen = strlen(cmd); + if (strncmp(val_string, cmd, cmdLen) != 0) { + goto usage; + } + + if ((ret = rtk_vlan_init()) != RT_ERR_OK) { + printk("init vlan failed...ret=%d\n", ret); + goto Error; + } + + for (port = 0; port < RTK_PORT_MAX; port++) { + if ((ret = rtk_vlan_portAcceptFrameType_set(port, type)) != RT_ERR_OK) { + printk("set portAcceptFrameType failed...ret=%d\n", ret); + goto Error; + } + } + + break; + case 'r': + cmd = "reset"; + cmdLen = strlen(cmd); + if (strncmp(val_string, cmd, cmdLen) != 0) { + goto usage; + } + + if ((ret = rtk_vlan_reset()) != RT_ERR_OK) { + printk("reset vlan failed...ret=%d\n", ret); + goto Error; + } + + break; + case 'g': + cmd = "get"; + cmdLen = strlen(cmd); + if (strncmp(val_string, cmd, cmdLen) != 0) { + goto usage; + } + + cmdLen += 1; + if (copy_from_user(buf, ubuf + cmdLen, usize - cmdLen)) { + printk("copy_from_user failed...\n"); + goto Error; + } + + pBuf = buf; + substr = strsep(&pBuf, " "); + if (!substr) { + goto usage; + } + + if(kstrtouint(substr, 0, &vid)) + { + printk("error!!!!\n"); + goto Error; + } + + if ((ret = rtk_vlan_get(vid, &vlanCfg)) != RT_ERR_OK) { + printk("get vlan %d failed...ret=%d\n", vid, ret); + goto Error; + } + + printk("mbr=%x\n", vlanCfg.mbr.bits[0]); + printk("untag=%x\n", vlanCfg.untag.bits[0]); + printk("fid_msti=%hu\n", vlanCfg.fid_msti); + printk("envlanpol=%hu\n", vlanCfg.envlanpol); + printk("ivl_en=%hu\n", vlanCfg.ivl_en); + printk("meteridx=%hu\n", vlanCfg.meteridx); + printk("vbpen=%hu\n", vlanCfg.vbpen); + printk("vbpri=%hu\n", vlanCfg.vbpri); + + break; + case 's': + cmd = "set"; + cmdLen = strlen(cmd); + if (strncmp(val_string, cmd, cmdLen) != 0) { + goto usage; + } + + cmdLen += 1; + if (copy_from_user(buf, ubuf + cmdLen, usize - cmdLen)) { + printk("copy_from_user failed...\n"); + goto Error; + } + + pBuf = buf; + substr = strsep(&pBuf, " "); + if (!substr) { + goto usage; + } + if (kstrtouint(substr, 0, &vid)) + goto Error; + + substr = strsep(&pBuf, " "); + if (!substr || !pBuf) { + goto usage; + } + + if (kstrtouint(substr, 0, &member)) + goto Error; + + if (kstrtouint(pBuf, 0, &untag)) + goto Error; + + memset(&vlan, 0x0, sizeof(rtk_vlan_cfg_t)); + vlan.ivl_en = ENABLED; + for (port = UTP_PORT0; port < RTK_PORT_MAX; port++) { + if (member & (0x1 << port)) { + RTK_PORTMASK_PORT_SET(vlan.mbr, port); + } + } + + for (port = UTP_PORT0; port < RTK_PORT_MAX; port++) { + if (untag & (0x1 << port)) { + RTK_PORTMASK_PORT_SET(vlan.untag, port); + } + } + + if ((ret = rtk_vlan_set(vid, &vlan)) != RT_ERR_OK) { + printk("set vlan %d failed...ret=%d\n", vid, ret); + goto Error; + } + + break; + default: + usage: + printk("Unknown cmd, vlan support list:\n"); + printk("init\nreset\nget \nset \n"); + break; + } + + Error: + return usize; +} + + + +static struct file_operations rtl8367s_vlan_fops = { + .owner = THIS_MODULE, + .open = NULL, + .read = NULL, + .write = rtl8367s_vlan_write, + .llseek = NULL, + .release = NULL, +}; + + +static ssize_t rtl8367s_port_write(struct file *filp, const char __user *ubuf, + size_t usize, loff_t *off) +{ + int ret = -1; + rtk_enable_t enable = RTK_ENABLE_END; + rtk_uint32 portid = 0; + rtk_vlan_acceptFrameType_t type = ACCEPT_FRAME_TYPE_END; + rtk_vlan_t pvid = 0; + rtk_pri_t priority = 0; + char buf[16] = {0}; + char *pBuf = NULL; + char *cmd = NULL; + int cmdLen = 0; + int preCmdLen = 0; + char *substr = NULL; + + char val_string[128]; + + if (usize > sizeof(val_string) - 1) + return -EINVAL; + if (copy_from_user(val_string, ubuf, usize)) + return -EFAULT; + + printk("cmd is %s\n", val_string); + + switch (val_string[1]) { + case 'v': + cmd = "pvid"; + cmdLen = strlen(cmd); + if (strncmp(val_string, cmd, cmdLen) != 0) { + goto usage; + } + preCmdLen = cmdLen; + + preCmdLen += 1; + cmd = "get"; + cmdLen = strlen(cmd); + if (strncmp(val_string + preCmdLen, cmd, cmdLen) == 0) { + preCmdLen += cmdLen; + preCmdLen += 1; + + if (copy_from_user(buf, ubuf + preCmdLen, usize - preCmdLen)) { + printk("copy_from_user failed...\n"); + goto Error; + } + + pBuf = buf; + substr = strsep(&pBuf, " "); + if (!substr) { + goto usage; + } + + if (kstrtouint(substr, 0, &portid)) + goto Error; + + if ((ret = rtk_vlan_portPvid_get(portid, &pvid, &priority)) != RT_ERR_OK) { + printk("get portPvid failed...ret=%d\n", ret); + goto Error; + } + + printk("pvid=%u priority=%d\n", pvid, priority); + } + else { + cmd = "set"; + cmdLen = strlen(cmd); + if (strncmp(val_string + preCmdLen, cmd, cmdLen) == 0) { + preCmdLen += cmdLen; + preCmdLen += 1; + + if (copy_from_user(buf, ubuf + preCmdLen, usize - preCmdLen)) { + printk("copy_from_user failed...\n"); + goto Error; + } + + pBuf = buf; + substr = strsep(&pBuf, " "); + if (!substr) { + goto usage; + } + + if (kstrtouint(substr, 0, &portid)) + goto Error; + + substr = strsep(&pBuf, " "); + if (!substr || !pBuf) { + goto usage; + } + + if (kstrtouint(substr, 0, &pvid)) + goto Error; + + if (kstrtouint(pBuf, 0, &priority)) + goto Error; + + if ((ret = rtk_vlan_portPvid_set(portid, pvid, priority)) != RT_ERR_OK) { + printk("set portPvid failed...ret=%d\n", ret); + goto Error; + } + } + else { + goto usage; + } + } + + break; + case 't': + cmd = "ptype"; + cmdLen = strlen(cmd); + if (strncmp(val_string, cmd, cmdLen) != 0) { + goto usage; + } + preCmdLen = cmdLen; + + preCmdLen += 1; + cmd = "get"; + cmdLen = strlen(cmd); + if (strncmp(val_string + preCmdLen, cmd, cmdLen) == 0) { + preCmdLen += cmdLen; + preCmdLen += 1; + + if (copy_from_user(buf, ubuf + preCmdLen, usize - preCmdLen)) { + printk("copy_from_user failed...\n"); + goto Error; + } + + pBuf = buf; + substr = strsep(&pBuf, " "); + if (!substr) { + goto usage; + } + + if (kstrtouint(substr, 0, &portid)) + goto Error; + + if ((ret = rtk_vlan_portAcceptFrameType_get(portid, &type)) != RT_ERR_OK) { + printk("get portAcceptFrameType failed...ret=%d\n", ret); + goto Error; + } + + printk("type=%d\n", type); + } + else { + cmd = "set"; + cmdLen = strlen(cmd); + if (strncmp(val_string + preCmdLen, cmd, cmdLen) == 0) { + preCmdLen += cmdLen; + preCmdLen += 1; + + if (copy_from_user(buf, ubuf + preCmdLen, usize - preCmdLen)) { + printk("copy_from_user failed...\n"); + goto Error; + } + + pBuf = buf; + substr = strsep(&pBuf, " "); + if (!substr || !pBuf) { + goto usage; + } + + if (kstrtouint(substr, 0, &portid)) + goto Error; + + if (kstrtouint(pBuf, 0, &type)) + goto Error; + + if ((ret = rtk_vlan_portAcceptFrameType_set(portid, type)) != RT_ERR_OK) { + printk("set portAcceptFrameType failed...ret=%d\n", ret); + goto Error; + } + } + else { + goto usage; + } + } + + break; + case 'e': + cmd = "eee"; + cmdLen = strlen(cmd); + if (strncmp(val_string, cmd, cmdLen) != 0) { + goto usage; + } + preCmdLen = cmdLen; + + preCmdLen += 1; + cmd = "get"; + cmdLen = strlen(cmd); + if (strncmp(val_string + preCmdLen, cmd, cmdLen) == 0) { + preCmdLen += cmdLen; + preCmdLen += 1; + + if (copy_from_user(buf, ubuf + preCmdLen, usize - preCmdLen)) { + printk("copy_from_user failed...\n"); + goto Error; + } + + pBuf = buf; + substr = strsep(&pBuf, " "); + if (!substr) { + goto usage; + } + + if (kstrtouint(substr, 0, &portid)) + goto Error; + + if ((ret = rtk_eee_portEnable_get(portid, &enable)) != RT_ERR_OK) { + printk("get eee portEnable failed...ret=%d\n", ret); + goto Error; + } + + printk("enable=%d\n", enable); + } + else { + cmd = "set"; + cmdLen = strlen(cmd); + if (strncmp(val_string + preCmdLen, cmd, cmdLen) == 0) { + preCmdLen += cmdLen; + preCmdLen += 1; + + if (copy_from_user(buf, ubuf + preCmdLen, usize - preCmdLen)) { + printk("copy_from_user failed...\n"); + goto Error; + } + + pBuf = buf; + substr = strsep(&pBuf, " "); + if (!substr || !pBuf) { + goto usage; + } + + if (kstrtouint(substr, 0, &portid)) + goto Error; + + if (kstrtouint(pBuf, 0, &enable)) + goto Error; + + if ((ret = rtk_eee_portEnable_set(portid, enable)) != RT_ERR_OK) { + printk("set eee portEnable failed...ret=%d\n", ret); + goto Error; + } + } + else { + goto usage; + } + } + break; + case 'r': + cmd = "green"; + cmdLen = strlen(cmd); + if (strncmp(val_string, cmd, cmdLen) != 0) { + goto usage; + } + preCmdLen = cmdLen; + + preCmdLen += 1; + cmd = "get"; + cmdLen = strlen(cmd); + if (strncmp(val_string + preCmdLen, cmd, cmdLen) == 0) { + if ((ret = rtk_switch_greenEthernet_get(&enable)) != RT_ERR_OK) { + if (ret == RT_ERR_DRIVER_NOT_FOUND) { + printk("get switch greenEthernet failed...ret=%d(The driver can not found)," + "Green Ethernet support is removed in rtl8367d DAL since switch driver V1.4.1\n", ret); + } + else{ + printk("get switch greenEthernet failed...ret=%d\n", ret); + } + goto Error; + } + printk("greenEthernet.enable=%d\n", enable); + } + else { + cmd = "set"; + cmdLen = strlen(cmd); + if (strncmp(val_string + preCmdLen, cmd, cmdLen) == 0) { + preCmdLen += cmdLen; + preCmdLen += 1; + + if (copy_from_user(buf, ubuf + preCmdLen, usize - preCmdLen)) { + printk("copy_from_user failed...\n"); + goto Error; + } + + pBuf = buf; + if (!pBuf) { + goto usage; + } + + if (kstrtouint(pBuf, 0, &enable)) + goto Error; + + if ((ret = rtk_switch_greenEthernet_set(enable)) != RT_ERR_OK) { + if (ret == RT_ERR_DRIVER_NOT_FOUND) { + printk("set switch greenEthernet failed...ret=%d(The driver can not found)," + "Green Ethernet support is removed in rtl8367d DAL since switch driver V1.4.1\n", ret); + } + else{ + printk("set switch greenEthernet failed...ret=%d\n", ret); + } + goto Error; + } + } + else { + goto usage; + } + } + + break; + default: +usage: + printk("Unknown cmd, port support list:\n"); + printk("pvid get \npvid set \n"); + printk("ptype get \nptype set \n"); + printk("eee get \neee set \n"); + printk("green get \ngreen set \n"); + break; + } + +Error: + return usize; +} + +static struct file_operations rtl8367s_port_fops = { + .owner = THIS_MODULE, + .open = NULL, + .read = NULL, + .write = rtl8367s_port_write, + .llseek = NULL, + .release = NULL, +}; + +/********************************************************************/ +/* unused function +static int rtl8367s_hw_init(void) +{ + int ret = 0; +#if 0 + RTL8367S_LOG_INFO("reset by gpio%d...", RTL8367S_RESET_GPIO_NUM); + gpio_direction_output(RTL8367S_RESET_GPIO_NUM, SSDK_GPIO_RESET); + msleep(200); + gpio_set_value(RTL8367S_RESET_GPIO_NUM, SSDK_GPIO_RELEASE); + msleep(200); + RTL8367S_LOG_INFO(" done\r\n"); +#endif + return ret; +} +*/ + +static int rtl8367s_mii_init(void) +{ + int ret = 0; + + RTL8367S_LOG_DEBUG("init\r\n"); + + if ((ret = rtk_switch_init()) != RT_ERR_OK) { + RTL8367S_LOG_ERR("rtk_switch_init failed...ret=%d\n", ret); + return ret; + } + + if(CHIP_RTL8367D != g_switch_chip) + { + rtl8367s_phy_Patch_set(0); + } + _rtl8367s_mii_type_refresh(); + + return ret; +} + +/* unused function +static int rtl8367s_vlan_init(void) +{ + int ret = 0; + + RTL8367S_LOG_DEBUG("init\r\n"); + + if ((ret = rtk_svlan_init()) != RT_ERR_OK) { + RTL8367S_LOG_ERR("rtk_svlan_init fail...ret=%d\n", ret); + return ret; + } + + if((ret = rtk_svlan_tpidEntry_set(ETH_P_8021Q)) != RT_ERR_OK) + { + RTL8367S_LOG_ERR("rtk_svlan_tpidEntry_set fail...ret=%d\n", ret); + return ret; + } + + if((ret = rtk_svlan_servicePort_add(rtl8367s_cpu_port)) != RT_ERR_OK) + { + RTL8367S_LOG_ERR("rtk_svlan_servicePort_add fail...ret=%d\n", ret); + return ret; + } + + if((ret = rtk_svlan_untag_action_set(UNTAG_DROP, 0)) != RT_ERR_OK) + { + RTL8367S_LOG_ERR("rtk_svlan_untag_action_set fail...ret=%d\n", ret); + return ret; + } + + if(CHIP_RTL8367D != g_switch_chip) + { + if((ret = rtk_svlan_unmatch_action_set(UNMATCH_DROP, 0)) != RT_ERR_OK) + { + RTL8367S_LOG_ERR("rtk_svlan_unmatch_action_set fail...ret=%d\n", ret); + return ret; + } + } + + + _rtl8367s_lookup_refresh(); + + return 0; +} +*/ + +static int rtl8367s_led_init(void) +{ +#ifdef RTL8367S_HW_LED_FUNCTION + + rtk_portmask_t portmask; + int ret; + int p; + + memset(&portmask, 0x0, sizeof(portmask)); + + for(p=PORT_IDX0; p sizeof(val_string) - 1) + return -EINVAL; + if (copy_from_user(val_string, buffer, count)) + return -EFAULT; + + if (sscanf(val_string, "%d", &val) != 1) + { + printk("usage: \n"); + return count; + } + + //rtl8367s_hw_init(); + + RTL8367S_LOCK(); + + rtl8367s_mii_init(); + //rtl8367s_vlan_init(); + if(CHIP_RTL8367D != g_switch_chip) + { + rtl8367s_mcast_init(); + } + + rtl8367s_led_init(); + + rtk_port_phyEnableAll_set(ENABLED); + + RTL8367S_UNLOCK(); + + return count; +} + +static struct file_operations rtl8367s_reset_fops = { + .owner = THIS_MODULE, + .open = NULL, + .read = NULL, + .write = rtl8367s_reset_write_proc, + .llseek = NULL, + .release = NULL, +}; + +static int rtl8367s_proc_init(void) +{ + struct proc_dir_entry * procRegDir = NULL; + + RTL8367S_LOG_DEBUG("init\r\n"); + + procRegDir = proc_mkdir("rtl8367s", NULL); + + proc_create("switch_reg", 0, procRegDir, &rtl8367s_switch_reg_fops); + + proc_create("phy_reg", 0, procRegDir, &rtl8367s_phy_reg_fops); + + proc_create("phy_status", 0, procRegDir, &rtl8367s_phy_status_fops); + + proc_create("mii_type", 0, procRegDir, &rtl8367s_mii_type_fops); + + proc_create("ucast_tbl", 0, procRegDir, &rtl8367s_ucast_tbl_fops); + + proc_create("mcast_tbl", 0, procRegDir, &rtl8367s_mcast_tbl_fops); + + proc_create("mib_cnt", 0, procRegDir, &rtl8367s_mib_cnt_fops); + + proc_create("mib_cnt_partial", 0, procRegDir, &rtl8367s_mib_cnt_partial_fops); + + if(CHIP_RTL8367D != g_switch_chip) + { + proc_create("mcast_snoop", 0, procRegDir, &rtl8367s_mcast_snoop_fops); + } + + proc_create("port_mirror", 0, procRegDir, &rtl8367s_port_mirror_fops); + + proc_create("hw_bridge", 0, procRegDir, &rtl8367s_hw_bridge_fops); + + proc_create("eth_forward", 0, procRegDir, &rtl8367s_eth_forward_fops); + + proc_create("cpu_mac", 0, procRegDir, &rtl8367s_cpu_mac_fops); + +#ifdef RTL8367S_HW_LED_FUNCTION + proc_create("hw_led", 0, procRegDir, &rtl8367s_hw_led_fops); +#endif /* RTL8367S_HW_LED_FUNCTION */ + + proc_create("reset", 0, procRegDir, &rtl8367s_reset_fops); + + proc_create("debug_info", 0, procRegDir, &rtl8367s_debug_info_fops); + + proc_create("vlan", 0, procRegDir, &rtl8367s_vlan_fops); + + proc_create("port", 0, procRegDir, &rtl8367s_port_fops); + + return 0; +} + + +#define RTL8367C_STATUS_LINK_10M 0 +#define RTL8367C_STATUS_LINK_100M 1 +#define RTL8367C_STATUS_LINK_1000M 2 +#define RTL8367C_CTRL_POWER_DOWN 0x0800 +#define CONFIG_VLAN_PER_PORT 1 +#define RTL8367C_PHY0_ADDR 0x0 +#define RTL8367C_PHY1_ADDR 0x1 +#define RTL8367C_PHY2_ADDR 0x2 +#define RTL8367C_PHY3_ADDR 0x3 +#define RTL8367C_PHY4_ADDR 0x4 +#define NO_WAN_PORT -1 +#define RTL_LAN_PORT_VLAN 1 +#define RTL_WAN_PORT_VLAN 2 +#define ENET_UNIT_GE1 1 +#define ENET_UNIT_GE0 0 /* Connected to the switch */ +#define ENET_UNIT_LAN ENET_UNIT_GE0 +#define ENET_UNIT_WAN ENET_UNIT_GE1 + +#define RTL8367C_IS_ENET_PORT(phyUnit) (rtlPhyInfo[phyUnit].isEnetPort) +#define RTL8367C_IS_PHY_ALIVE(phyUnit) (rtlPhyInfo[phyUnit].isPhyAlive) +#define RTL8367C_ETHUNIT(phyUnit) (rtlPhyInfo[phyUnit].ethUnit) +#define RTL8367C_PHYBASE(phyUnit) (rtlPhyInfo[phyUnit].phyBase) +#define RTL8367C_PHYADDR(phyUnit) (rtlPhyInfo[phyUnit].phyAddr) +#define RTL8367C_VLAN_TABLE_SETTING(phyUnit) (rtlPhyInfo[phyUnit].VLANTableSetting) + + +typedef struct { + bool isEnetPort; /* normal enet port */ + bool isPhyAlive; /* last known state of link */ + int ethUnit; /* MAC associated with this phy port */ + unsigned int phyBase; + unsigned int phyAddr; /* PHY registers associated with this phy port */ + unsigned int VLANTableSetting; /* Value to be written to VLAN table */ +} rtlPhyInfo_t; + +static rtlPhyInfo_t rtlPhyInfo[] = { + + {TRUE, /* port 1 -- LAN port 1 */ + FALSE, +#if defined(WAN_AT_P0) + ENET_UNIT_WAN, +#else + ENET_UNIT_LAN, +#endif + 0, + RTL8367C_PHY0_ADDR, + RTL_LAN_PORT_VLAN + }, + + {TRUE, /* port 2 -- LAN port 2 */ + FALSE, + ENET_UNIT_LAN, + 0, + RTL8367C_PHY1_ADDR, + RTL_LAN_PORT_VLAN + }, + + {TRUE, /* port 3 -- LAN port 3 */ + FALSE, + ENET_UNIT_LAN, + 0, + RTL8367C_PHY2_ADDR, + RTL_LAN_PORT_VLAN + }, + + {TRUE, /* port 4 -- LAN port 4 */ + FALSE, + ENET_UNIT_LAN, + 0, + RTL8367C_PHY3_ADDR, + RTL_LAN_PORT_VLAN /* Send to all ports */ + }, + + {TRUE, /* port 5 -- WAN Port 5 */ + FALSE, + #if defined(WAN_AT_P4) + ENET_UNIT_WAN, + #else + ENET_UNIT_LAN, + #endif + 0, + RTL8367C_PHY4_ADDR, + RTL_LAN_PORT_VLAN /* Send to all ports */ + }, + + {FALSE, /* port 0 -- cpu port 0 */ + TRUE, + ENET_UNIT_LAN, + 0, + 0x00, + RTL_LAN_PORT_VLAN + }, +}; + + +/****************************************************************************** +* +* rtl8211_phy_mii_read - mii register read +* +*/ +static a_uint16_t +rtl8211_phy_reg_read (rtk_uint32 dev_id, rtk_uint32 phy_id, rtk_uint32 reg_id) +{ + return qca808x_phy_reg_read (dev_id, phy_id, reg_id); +} + +/****************************************************************************** +* +* rtl8211_phy_mii_write - mii register write +* +*/ +static sw_error_t +rtl8211_phy_reg_write (rtk_uint32 dev_id, rtk_uint32 phy_id, rtk_uint32 reg_id, + a_uint16_t reg_val) +{ + return qca808x_phy_reg_write (dev_id, phy_id, reg_id, reg_val); +} + +/****************************************************************************** +* +* rtl8211_phy_debug_read - debug port read +* +*/ +static a_uint16_t +rtl8211_phy_debug_read(rtk_uint32 dev_id, rtk_uint32 phy_id, a_uint16_t reg_id) +{ + return qca808x_phy_debug_read(dev_id, phy_id, reg_id); +} + +/****************************************************************************** +* +* rtl8211_phy_debug_write - debug port write +* +*/ +static sw_error_t +rtl8211_phy_debug_write(rtk_uint32 dev_id, rtk_uint32 phy_id, a_uint16_t reg_id, + a_uint16_t reg_val) +{ + return qca808x_phy_debug_write (dev_id, phy_id, reg_id, reg_val); +} + +/****************************************************************************** +* +* rtl8211_phy_mmd_read - PHY MMD register read +* +*/ +static a_uint16_t +rtl8211_phy_mmd_read(rtk_uint32 dev_id, rtk_uint32 phy_id, + a_uint16_t mmd_num, a_uint16_t reg_id) +{ + return qca808x_phy_mmd_read(dev_id, phy_id, mmd_num, reg_id); +} + +/****************************************************************************** +* +* rtl8211_phy_mmd_write - PHY MMD register write +* +*/ +static sw_error_t +rtl8211_phy_mmd_write(rtk_uint32 dev_id, rtk_uint32 phy_id, + a_uint16_t mmd_num, a_uint16_t reg_id, a_uint16_t reg_val) +{ + return qca808x_phy_mmd_write (dev_id, phy_id, mmd_num, + reg_id, reg_val); +} + + +bool +rtl8367c_phy_is_link_alive(int phyUnit, int *plinkStatus, int *pspeed, int *pduplex) +{ + uint32_t phyBase; + uint32_t phyAddr; + rtk_api_ret_t retVal; + int linkStatus, speed, duplex; + + phyBase = RTL8367C_PHYBASE(phyUnit); + phyAddr = RTL8367C_PHYADDR(phyUnit); + + if (phyAddr > RTK_PHY_ID_MAX) + return FALSE; + + retVal = rtk_port_phyStatus_get(phyAddr, (rtk_port_linkStatus_t *)&linkStatus, + (rtk_port_speed_t *)&speed, (rtk_port_duplex_t *)&duplex); + + if (retVal != RT_ERR_OK) + { + printk("rtl8367c_phy_is_link_alive failed!!!\r\n"); + return FALSE; + } + *plinkStatus = linkStatus; + switch(speed) + { + case PORT_SPEED_10M: + *pspeed = FAL_SPEED_10; + break; + case PORT_SPEED_100M: + *pspeed = FAL_SPEED_100; + break; + case PORT_SPEED_1000M: + *pspeed = FAL_SPEED_1000; + break; + case PORT_SPEED_2500M: + *pspeed = FAL_SPEED_2500; + break; + default: + *pspeed = FAL_SPEED_10; + break; + } + switch (duplex) + { + case PORT_HALF_DUPLEX: + *pduplex = FAL_HALF_DUPLEX; + break; + case PORT_FULL_DUPLEX: + *pduplex = FAL_FULL_DUPLEX; + break; + default: + *pduplex = FAL_FULL_DUPLEX; + break; + } + + return linkStatus; +} + + + +/****************************************************************************** +* +* rtl8211_phy_get_status - get the phy status +* +*/ +static sw_error_t +rtl8211_phy_get_status(rtk_uint32 dev_id, rtk_uint32 phy_id, + struct port_phy_status *phy_status) +{ + rtk_port_linkStatus_t pLinkStatus[PORT_MAX_NUM] = {0}; + rtk_port_speed_t pSpeed[PORT_MAX_NUM] = {0}; + rtk_port_duplex_t pDuplex[PORT_MAX_NUM] = {0}; + + int p = 0; + + for(p=0; plink_status = pLinkStatus[p]; + phy_status->speed = pSpeed[p]; + phy_status->duplex = pDuplex[p]; + } + } + +#if 0 + for (i = 0; i < 5; i++) + { + alive = rtl8367c_phy_is_link_alive(i, &linkStatus, &speed, &duplex); + SSDK_DEBUG("[%d] linkstatus=%d speed=%d duplex=%d\n", + i, linkStatus, speed, duplex); + if (linkStatus) + { + phy_status->link_status = linkStatus; + phy_status->speed = speed; + phy_status->duplex = duplex; + } + } + + SSDK_DEBUG("get rtl8211 linkstatus: %u, speed: %d, duplex: %d\n", phy_status->link_status, phy_status->speed, phy_status->duplex); +#endif + + return SW_OK; +} + +/****************************************************************************** +* +* rtl8211_set_autoneg_adv - set the phy autoneg Advertisement +* +*/ +static sw_error_t +rtl8211_phy_set_autoneg_adv(rtk_uint32 dev_id, rtk_uint32 phy_id, + rtk_uint32 autoneg) +{ + SSDK_ERROR("[ZC]===>rtl8211_phy_set_autoneg_adv\n"); + + return SW_OK; +} + +/****************************************************************************** +* +* rtl8211_get_autoneg_adv - get the phy autoneg Advertisement +* +*/ +static sw_error_t +rtl8211_phy_get_autoneg_adv(rtk_uint32 dev_id, rtk_uint32 phy_id, + rtk_uint32 * autoneg) +{ + SSDK_ERROR("[ZC]===>rtl8211_phy_get_autoneg_adv\n"); + + return SW_OK; +} + +/****************************************************************************** +* +* rtl8211_phy_get_speed - Determines the speed of phy ports associated with the +* specified device. +*/ + +static sw_error_t +rtl8211_phy_get_speed(rtk_uint32 dev_id, rtk_uint32 phy_id, + fal_port_speed_t * speed) +{ + SSDK_ERROR("[ZC]===>rtl8211_phy_get_speed\n"); + + return SW_OK; +} + +/****************************************************************************** +* +* rtl8211_phy_get_duplex - Determines the duplex of phy ports associated with the +* specified device. +*/ +static sw_error_t +rtl8211_phy_get_duplex(rtk_uint32 dev_id, rtk_uint32 phy_id, + fal_port_duplex_t * duplex) +{ + SSDK_ERROR("[ZC]===>rtl8211_phy_get_duplex\n"); + + return SW_OK; +} + +/****************************************************************************** +* +* rtl8211_phy_set_speed - Set the speed of phy ports associated with the +* specified device. +*/ +static sw_error_t +rtl8211_phy_set_speed(rtk_uint32 dev_id, rtk_uint32 phy_id, + fal_port_speed_t speed) +{ + SSDK_ERROR("[ZC]===>rtl8211_phy_set_speed\n"); + + return SW_OK; +} + +/****************************************************************************** +* +* rtl8211_phy_set_duplex - Set the duplex of phy ports associated with the +* specified device. +*/ +static sw_error_t +rtl8211_phy_set_duplex(rtk_uint32 dev_id, rtk_uint32 phy_id, + fal_port_duplex_t duplex) +{ + SSDK_ERROR("[ZC]===>rtl8211_phy_set_duplex\n"); + + return SW_OK; +} + +/****************************************************************************** +* +* rtl8211_phy_enable_autoneg - enable the phy autoneg +* +*/ +static sw_error_t +rtl8211_phy_enable_autoneg(rtk_uint32 dev_id, rtk_uint32 phy_id) +{ + SSDK_ERROR("[ZC]===>rtl8211_phy_enable_autoneg\n"); + + return SW_OK; + +} + +/****************************************************************************** +* +* rtl8211_restart_autoneg - restart the phy autoneg +* +*/ +static sw_error_t +rtl8211_phy_restart_autoneg(rtk_uint32 dev_id, rtk_uint32 phy_id) +{ + SSDK_ERROR("[ZC]===>rtl8211_phy_restart_autoneg\n"); + + return SW_OK; +} + +/****************************************************************************** +* +* rtl8211_phy_autoneg_status - get the phy autoneg status +* +*/ +static a_bool_t +rtl8211_phy_autoneg_status(rtk_uint32 dev_id, rtk_uint32 phy_id) +{ + SSDK_ERROR("[ZC]===>rtl8211_phy_autoneg_status\n"); + + return A_FALSE; +} + +/****************************************************************************** +* +* rtl8211_phy_status - get the phy link status +* +* RETURNS: +* A_TRUE --> link is alive +* A_FALSE --> link is down +*/ +static a_bool_t +rtl8211_phy_get_link_status(rtk_uint32 dev_id, rtk_uint32 phy_id) +{ + SSDK_ERROR("[ZC]===>rtl8211_phy_get_link_status\n"); + + return A_FALSE; +} + +/****************************************************************************** +* +* rtl8211_phy_reset - reset the phy +* +*/ +static sw_error_t +rtl8211_phy_reset(rtk_uint32 dev_id, rtk_uint32 phy_id) +{ + SSDK_ERROR("[ZC]===>rtl8211_phy_reset\n"); + + return SW_OK; +} + + +/****************************************************************************** +* +* rtl8211_phy_get_phy_id - get the phy id +* +*/ +static sw_error_t +rtl8211_phy_get_phy_id(rtk_uint32 dev_id, rtk_uint32 phy_id, + rtk_uint32 *phy_data) +{ + return qca808x_phy_get_phy_id (dev_id, phy_id, phy_data); +} + +/****************************************************************************** +* +* rtl8211_phy_off - power off the phy +* +*/ +static sw_error_t +rtl8211_phy_poweroff(rtk_uint32 dev_id, rtk_uint32 phy_id) +{ + SSDK_ERROR("[ZC]===>rtl8211_phy_poweroff\n"); + + return SW_OK; +} + +/****************************************************************************** +* +* rtl8211_phy_on - power on the phy +* +*/ +static sw_error_t +rtl8211_phy_poweron(rtk_uint32 dev_id, rtk_uint32 phy_id) +{ + SSDK_ERROR("[ZC]===>rtl8211_phy_poweron\n"); + + return SW_OK; +} + + +/****************************************************************************** +* +* rtl8211_interface_mode_set +* +*/ +static sw_error_t +rtl8211_phy_interface_mode_set(rtk_uint32 dev_id, rtk_uint32 phy_id, fal_port_interface_mode_t interface_mode) +{ + return SW_OK; +} + +static sw_error_t +rtl8211_phy_interface_mode_get(rtk_uint32 dev_id, rtk_uint32 phy_id, fal_port_interface_mode_t *interface_mode) +{ + SSDK_ERROR("[ZC]===>rtl8211_phy_interface_mode_get\n"); + *interface_mode = PORT_SGMII_PLUS; + return SW_OK; +} + +static sw_error_t +rtl8211_phy_interface_modestatus_get(rtk_uint32 dev_id, rtk_uint32 phy_id, fal_port_interface_mode_t *interface_mode) +{ + SSDK_ERROR("[ZC]===>rtl8211_phy_interface_modestatus_get\n"); + *interface_mode = PORT_SGMII_PLUS; + return SW_OK; +} + +static sw_error_t rtl8367_phy_api_ops_init(void) +{ + sw_error_t ret = SW_OK; + hsl_phy_ops_t *rtl8367_phy_api_ops = NULL; + + rtl8367_phy_api_ops = kzalloc(sizeof(hsl_phy_ops_t), GFP_KERNEL); + if (rtl8367_phy_api_ops == NULL) + { + SSDK_ERROR("rtl8211 phy ops kzalloc failed!\n"); + return -ENOMEM; + } + + phy_api_ops_init(RTL8367S_PHY_CHIP); + + rtl8367_phy_api_ops->phy_reg_write = rtl8211_phy_reg_write; + rtl8367_phy_api_ops->phy_reg_read = rtl8211_phy_reg_read; + rtl8367_phy_api_ops->phy_debug_write = rtl8211_phy_debug_write; + rtl8367_phy_api_ops->phy_debug_read = rtl8211_phy_debug_read; + rtl8367_phy_api_ops->phy_mmd_write = rtl8211_phy_mmd_write; + rtl8367_phy_api_ops->phy_mmd_read = rtl8211_phy_mmd_read; + rtl8367_phy_api_ops->phy_get_status = rtl8211_phy_get_status; + rtl8367_phy_api_ops->phy_speed_get = rtl8211_phy_get_speed; + rtl8367_phy_api_ops->phy_speed_set = rtl8211_phy_set_speed; + rtl8367_phy_api_ops->phy_duplex_get = rtl8211_phy_get_duplex; + rtl8367_phy_api_ops->phy_duplex_set = rtl8211_phy_set_duplex; + rtl8367_phy_api_ops->phy_autoneg_enable_set = rtl8211_phy_enable_autoneg; + rtl8367_phy_api_ops->phy_restart_autoneg = rtl8211_phy_restart_autoneg; + rtl8367_phy_api_ops->phy_autoneg_status_get = rtl8211_phy_autoneg_status; + rtl8367_phy_api_ops->phy_autoneg_adv_set = rtl8211_phy_set_autoneg_adv; + rtl8367_phy_api_ops->phy_autoneg_adv_get = rtl8211_phy_get_autoneg_adv; + rtl8367_phy_api_ops->phy_link_status_get = rtl8211_phy_get_link_status; + rtl8367_phy_api_ops->phy_reset = rtl8211_phy_reset; + rtl8367_phy_api_ops->phy_id_get = rtl8211_phy_get_phy_id; + rtl8367_phy_api_ops->phy_power_off = rtl8211_phy_poweroff; + rtl8367_phy_api_ops->phy_power_on = rtl8211_phy_poweron; + rtl8367_phy_api_ops->phy_interface_mode_set = rtl8211_phy_interface_mode_set; + rtl8367_phy_api_ops->phy_interface_mode_get = rtl8211_phy_interface_mode_get; + rtl8367_phy_api_ops->phy_interface_mode_status_get = rtl8211_phy_interface_modestatus_get; + + ret = hsl_phy_api_ops_register(RTL8367S_PHY_CHIP, rtl8367_phy_api_ops); + + if (ret == SW_OK) + { + SSDK_INFO("qca probe rtl8367 phy driver succeeded!\n"); + } + else + { + SSDK_ERROR("qca probe rtl8367 phy driver failed! (code: %d)\n", ret); + } + + return ret; +} + + +int rtl8367s_init(rtk_uint32 dev_id, rtk_uint32 port_bmp) +{ +#if 0 + int saved = rtl8367s_debug_info; + rtl8367s_debug_info = 1; /* open debug flag while init */ +#endif + static a_bool_t phy_ops_flag = A_FALSE; + + struct device_node *mdio; + struct mii_bus *mdio_bus; + + SSDK_ERROR("Init RTL8367, dev_id: %d, port_bmp: %0x\n", dev_id, port_bmp); + if(phy_ops_flag == A_FALSE && + rtl8367_phy_api_ops_init() == SW_OK) { + phy_ops_flag = A_TRUE; + } + + mdio = of_find_node_by_path("/soc/mdio@90000"); + + if (!mdio) + { + SSDK_ERROR("RTL8367 init error -EINVAL\n"); + return -EINVAL; + } + + mdio_bus = of_mdio_find_bus(mdio); + + if (!mdio_bus) + { + SSDK_ERROR("RTL8367 init error -EPROBE_DEFER\n"); + return -EPROBE_DEFER; + } + + g_mii_bus = mdio_bus; + + rtl8367s_gpio_reset(30); //hardware reset + + RTL8367S_LOG_INFO("init wzx\r\n"); + + RTL8367S_LOCK_INIT(); + +// rtl8367s_hw_init(); + + rtl8367s_mii_init(); + + //rtl8367s_vlan_init(); + + if(CHIP_RTL8367D != g_switch_chip) + { + rtl8367s_acl_init(); + rtl8367s_mcast_snoop = 0; + rtl8367s_mcast_init(); + } + + rtl8367s_led_init(); + + //rtl8367s_event_init(); + + rtl8367s_proc_init(); + + rtk_port_phyEnableAll_set(ENABLED); + + RTL8367S_LOG_INFO("done!\n"); + +#if 0 + rtl8367s_debug_info = saved; /* recover debug flag after init */ +#endif + + return 0; +} + +//#endif /* CONFIG_TP_EXT_SWITCH_RTL8367S */ diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/rtl8367s.c.bak b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/rtl8367s.c.bak new file mode 100644 index 00000000..43389ab3 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/rtl8367s.c.bak @@ -0,0 +1,688 @@ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#include "sw.h" +#include "fal_port_ctrl.h" +#include "hsl_api.h" +#include "hsl.h" +#include "hsl_phy.h" +#include "ssdk_plat.h" +#include "qca808x_phy.h" +#include "rtl8221b.h" + +#include +#include +#include +#include +#include +#include + +#include "rtk_switch.h" +#include "rtl8367c_reg.h" +#include "rtl8367c_asicdrv.h" +#include "rtl8367c_asicdrv_phy.h" +#include "rtl8367c_asicdrv_vlan.h" +#include "rtl8367c_asicdrv_port.h" +#include "port.h" +#include "vlan.h" +#include "l2.h" +#include "acl.h" +#include "eee.h" + + +/* + * + */ +//#define MDC_MDIO_PHY_ID (29) +#define MII_ADDR_C45 (1<<30) + +#define LOG_ERR(fmt, ...) \ + do { \ + printk("[rtl8367s] %s[%d]: "fmt, __func__, __LINE__, ##__VA_ARGS__); \ + } while(0) +#define ERR_PRINT(ret) \ + do { \ + if ( ret != SUCCESS ) printk("[rtl8367s] %s[%d]: error, return. ", __FUNCTION__, __LINE__); \ + } while(0) + + +#define RTL8367C_STATUS_LINK_10M 0 +#define RTL8367C_STATUS_LINK_100M 1 +#define RTL8367C_STATUS_LINK_1000M 2 +#define RTL8367C_CTRL_POWER_DOWN 0x0800 +#define CONFIG_VLAN_PER_PORT 1 +#define RTL8367C_PHY0_ADDR 0x0 +#define RTL8367C_PHY1_ADDR 0x1 +#define RTL8367C_PHY2_ADDR 0x2 +#define RTL8367C_PHY3_ADDR 0x3 +#define RTL8367C_PHY4_ADDR 0x4 +#define NO_WAN_PORT -1 +#define RTL_LAN_PORT_VLAN 1 +#define RTL_WAN_PORT_VLAN 2 +#define ENET_UNIT_GE1 1 +#define ENET_UNIT_GE0 0 /* Connected to the switch */ +#define ENET_UNIT_LAN ENET_UNIT_GE0 +#define ENET_UNIT_WAN ENET_UNIT_GE1 + +#define RTL8367C_IS_ENET_PORT(phyUnit) (rtlPhyInfo[phyUnit].isEnetPort) +#define RTL8367C_IS_PHY_ALIVE(phyUnit) (rtlPhyInfo[phyUnit].isPhyAlive) +#define RTL8367C_ETHUNIT(phyUnit) (rtlPhyInfo[phyUnit].ethUnit) +#define RTL8367C_PHYBASE(phyUnit) (rtlPhyInfo[phyUnit].phyBase) +#define RTL8367C_PHYADDR(phyUnit) (rtlPhyInfo[phyUnit].phyAddr) +#define RTL8367C_VLAN_TABLE_SETTING(phyUnit) (rtlPhyInfo[phyUnit].VLANTableSetting) + + +typedef struct { + bool isEnetPort; /* normal enet port */ + bool isPhyAlive; /* last known state of link */ + int ethUnit; /* MAC associated with this phy port */ + unsigned int phyBase; + unsigned int phyAddr; /* PHY registers associated with this phy port */ + unsigned int VLANTableSetting; /* Value to be written to VLAN table */ +} rtlPhyInfo_t; + +static rtlPhyInfo_t rtlPhyInfo[] = { + + {TRUE, /* port 1 -- LAN port 1 */ + FALSE, +#if defined(WAN_AT_P0) + ENET_UNIT_WAN, +#else + ENET_UNIT_LAN, +#endif + 0, + RTL8367C_PHY0_ADDR, + RTL_LAN_PORT_VLAN + }, + + {TRUE, /* port 2 -- LAN port 2 */ + FALSE, + ENET_UNIT_LAN, + 0, + RTL8367C_PHY1_ADDR, + RTL_LAN_PORT_VLAN + }, + + {TRUE, /* port 3 -- LAN port 3 */ + FALSE, + ENET_UNIT_LAN, + 0, + RTL8367C_PHY2_ADDR, + RTL_LAN_PORT_VLAN + }, + + {TRUE, /* port 4 -- LAN port 4 */ + FALSE, + ENET_UNIT_LAN, + 0, + RTL8367C_PHY3_ADDR, + RTL_LAN_PORT_VLAN /* Send to all ports */ + }, + + {TRUE, /* port 5 -- WAN Port 5 */ + FALSE, + #if defined(WAN_AT_P4) + ENET_UNIT_WAN, + #else + ENET_UNIT_LAN, + #endif + 0, + RTL8367C_PHY4_ADDR, + RTL_LAN_PORT_VLAN /* Send to all ports */ + }, + + {FALSE, /* port 0 -- cpu port 0 */ + TRUE, + ENET_UNIT_LAN, + 0, + 0x00, + RTL_LAN_PORT_VLAN + }, +}; + +/* + * + */ +static struct mii_bus *g_mii_bus = NULL; + +/* + * + */ +int rtl8367s_mdio_write(unsigned int phy_addr, unsigned int reg, unsigned int data) +{ + if (!g_mii_bus) + { + return -1; + } + + mutex_lock(&g_mii_bus->mdio_lock); + __mdiobus_write(g_mii_bus, 29, reg, data); + mutex_unlock(&g_mii_bus->mdio_lock); + + return 0; +} + +int rtl8367s_mdio_read(unsigned int phy_addr, unsigned int reg, unsigned int* data) +{ + if (!g_mii_bus) + { + return -1; + } + + mutex_lock(&g_mii_bus->mdio_lock); + *data = __mdiobus_read(g_mii_bus, 29, reg); + mutex_unlock(&g_mii_bus->mdio_lock); + + return 0; +} + +/****************************************************************************** +* +* rtl8211_phy_mii_read - mii register read +* +*/ +static a_uint16_t +rtl8211_phy_reg_read (rtk_uint32 dev_id, rtk_uint32 phy_id, rtk_uint32 reg_id) +{ + return qca808x_phy_reg_read (dev_id, phy_id, reg_id); +} + +/****************************************************************************** +* +* rtl8211_phy_mii_write - mii register write +* +*/ +static sw_error_t +rtl8211_phy_reg_write (rtk_uint32 dev_id, rtk_uint32 phy_id, rtk_uint32 reg_id, + a_uint16_t reg_val) +{ + return qca808x_phy_reg_write (dev_id, phy_id, reg_id, reg_val); +} + +/****************************************************************************** +* +* rtl8211_phy_debug_read - debug port read +* +*/ +static a_uint16_t +rtl8211_phy_debug_read(rtk_uint32 dev_id, rtk_uint32 phy_id, a_uint16_t reg_id) +{ + return qca808x_phy_debug_read(dev_id, phy_id, reg_id); +} + +/****************************************************************************** +* +* rtl8211_phy_debug_write - debug port write +* +*/ +static sw_error_t +rtl8211_phy_debug_write(rtk_uint32 dev_id, rtk_uint32 phy_id, a_uint16_t reg_id, + a_uint16_t reg_val) +{ + return qca808x_phy_debug_write (dev_id, phy_id, reg_id, reg_val); +} + +/****************************************************************************** +* +* rtl8211_phy_mmd_read - PHY MMD register read +* +*/ +static a_uint16_t +rtl8211_phy_mmd_read(rtk_uint32 dev_id, rtk_uint32 phy_id, + a_uint16_t mmd_num, a_uint16_t reg_id) +{ + return qca808x_phy_mmd_read(dev_id, phy_id, mmd_num, reg_id); +} + +/****************************************************************************** +* +* rtl8211_phy_mmd_write - PHY MMD register write +* +*/ +static sw_error_t +rtl8211_phy_mmd_write(rtk_uint32 dev_id, rtk_uint32 phy_id, + a_uint16_t mmd_num, a_uint16_t reg_id, a_uint16_t reg_val) +{ + return qca808x_phy_mmd_write (dev_id, phy_id, mmd_num, + reg_id, reg_val); +} + + +bool +rtl8367c_phy_is_link_alive(int phyUnit, int *plinkStatus, int *pspeed, int *pduplex) +{ + uint32_t phyBase; + uint32_t phyAddr; + rtk_api_ret_t retVal; + int linkStatus, speed, duplex; + + phyBase = RTL8367C_PHYBASE(phyUnit); + phyAddr = RTL8367C_PHYADDR(phyUnit); + + if (phyAddr > RTK_PHY_ID_MAX) + return FALSE; + + retVal = rtk_port_phyStatus_get(phyAddr, (rtk_port_linkStatus_t *)&linkStatus, + (rtk_port_speed_t *)&speed, (rtk_port_duplex_t *)&duplex); + + if (retVal != RT_ERR_OK) + { + printk("rtl8367c_phy_is_link_alive failed!!!\r\n"); + return FALSE; + } + *plinkStatus = linkStatus; + switch(speed) + { + case PORT_SPEED_10M: + *pspeed = FAL_SPEED_10; + break; + case PORT_SPEED_100M: + *pspeed = FAL_SPEED_100; + break; + case PORT_SPEED_1000M: + *pspeed = FAL_SPEED_1000; + break; + case PORT_SPEED_2500M: + *pspeed = FAL_SPEED_2500; + break; + default: + *pspeed = FAL_SPEED_10; + break; + } + switch (duplex) + { + case PORT_HALF_DUPLEX: + *pduplex = FAL_HALF_DUPLEX; + break; + case PORT_FULL_DUPLEX: + *pduplex = FAL_FULL_DUPLEX; + break; + default: + *pduplex = FAL_FULL_DUPLEX; + break; + } + + return linkStatus; +} + + + +/****************************************************************************** +* +* rtl8211_phy_get_status - get the phy status +* +*/ +static sw_error_t +rtl8211_phy_get_status(rtk_uint32 dev_id, rtk_uint32 phy_id, + struct port_phy_status *phy_status) +{ + int i; + bool alive; + int linkStatus, speed, duplex; + + SSDK_ERROR("[ZC]===>rtl8211_phy_get_status\n"); + + for (i = 0; i < 5; i++) + { + alive = rtl8367c_phy_is_link_alive(i, &linkStatus, &speed, &duplex); + SSDK_DEBUG("[%d] linkstatus=%d speed=%d duplex=%d\n", + i, linkStatus, speed, duplex); + if (linkStatus) + { + phy_status->link_status = linkStatus; + phy_status->speed = speed; + phy_status->duplex = duplex; + } + } + + SSDK_DEBUG("get rtl8211 linkstatus: %u, speed: %d, duplex: %d\n", phy_status->link_status, phy_status->speed, phy_status->duplex); + + return SW_OK; +} + +/****************************************************************************** +* +* rtl8211_set_autoneg_adv - set the phy autoneg Advertisement +* +*/ +static sw_error_t +rtl8211_phy_set_autoneg_adv(rtk_uint32 dev_id, rtk_uint32 phy_id, + rtk_uint32 autoneg) +{ + SSDK_ERROR("[ZC]===>rtl8211_phy_set_autoneg_adv\n"); + + return SW_OK; +} + +/****************************************************************************** +* +* rtl8211_get_autoneg_adv - get the phy autoneg Advertisement +* +*/ +static sw_error_t +rtl8211_phy_get_autoneg_adv(rtk_uint32 dev_id, rtk_uint32 phy_id, + rtk_uint32 * autoneg) +{ + SSDK_ERROR("[ZC]===>rtl8211_phy_get_autoneg_adv\n"); + + return SW_OK; +} + +/****************************************************************************** +* +* rtl8211_phy_get_speed - Determines the speed of phy ports associated with the +* specified device. +*/ + +static sw_error_t +rtl8211_phy_get_speed(rtk_uint32 dev_id, rtk_uint32 phy_id, + fal_port_speed_t * speed) +{ + SSDK_ERROR("[ZC]===>rtl8211_phy_get_speed\n"); + + return SW_OK; +} + +/****************************************************************************** +* +* rtl8211_phy_get_duplex - Determines the duplex of phy ports associated with the +* specified device. +*/ +static sw_error_t +rtl8211_phy_get_duplex(rtk_uint32 dev_id, rtk_uint32 phy_id, + fal_port_duplex_t * duplex) +{ + SSDK_ERROR("[ZC]===>rtl8211_phy_get_duplex\n"); + + return SW_OK; +} + +/****************************************************************************** +* +* rtl8211_phy_set_speed - Set the speed of phy ports associated with the +* specified device. +*/ +static sw_error_t +rtl8211_phy_set_speed(rtk_uint32 dev_id, rtk_uint32 phy_id, + fal_port_speed_t speed) +{ + SSDK_ERROR("[ZC]===>rtl8211_phy_set_speed\n"); + + return SW_OK; +} + +/****************************************************************************** +* +* rtl8211_phy_set_duplex - Set the duplex of phy ports associated with the +* specified device. +*/ +static sw_error_t +rtl8211_phy_set_duplex(rtk_uint32 dev_id, rtk_uint32 phy_id, + fal_port_duplex_t duplex) +{ + SSDK_ERROR("[ZC]===>rtl8211_phy_set_duplex\n"); + + return SW_OK; +} + +/****************************************************************************** +* +* rtl8211_phy_enable_autoneg - enable the phy autoneg +* +*/ +static sw_error_t +rtl8211_phy_enable_autoneg(rtk_uint32 dev_id, rtk_uint32 phy_id) +{ + SSDK_ERROR("[ZC]===>rtl8211_phy_enable_autoneg\n"); + + return SW_OK; + +} + +/****************************************************************************** +* +* rtl8211_restart_autoneg - restart the phy autoneg +* +*/ +static sw_error_t +rtl8211_phy_restart_autoneg(rtk_uint32 dev_id, rtk_uint32 phy_id) +{ + SSDK_ERROR("[ZC]===>rtl8211_phy_restart_autoneg\n"); + + return SW_OK; +} + +/****************************************************************************** +* +* rtl8211_phy_autoneg_status - get the phy autoneg status +* +*/ +static a_bool_t +rtl8211_phy_autoneg_status(rtk_uint32 dev_id, rtk_uint32 phy_id) +{ + SSDK_ERROR("[ZC]===>rtl8211_phy_autoneg_status\n"); + + return A_FALSE; +} + +/****************************************************************************** +* +* rtl8211_phy_status - get the phy link status +* +* RETURNS: +* A_TRUE --> link is alive +* A_FALSE --> link is down +*/ +static a_bool_t +rtl8211_phy_get_link_status(rtk_uint32 dev_id, rtk_uint32 phy_id) +{ + SSDK_ERROR("[ZC]===>rtl8211_phy_get_link_status\n"); + + return A_FALSE; +} + +/****************************************************************************** +* +* rtl8211_phy_reset - reset the phy +* +*/ +static sw_error_t +rtl8211_phy_reset(rtk_uint32 dev_id, rtk_uint32 phy_id) +{ + SSDK_ERROR("[ZC]===>rtl8211_phy_reset\n"); + + return SW_OK; +} + + +/****************************************************************************** +* +* rtl8211_phy_get_phy_id - get the phy id +* +*/ +static sw_error_t +rtl8211_phy_get_phy_id(rtk_uint32 dev_id, rtk_uint32 phy_id, + rtk_uint32 *phy_data) +{ + return qca808x_phy_get_phy_id (dev_id, phy_id, phy_data); +} + +/****************************************************************************** +* +* rtl8211_phy_off - power off the phy +* +*/ +static sw_error_t +rtl8211_phy_poweroff(rtk_uint32 dev_id, rtk_uint32 phy_id) +{ + SSDK_ERROR("[ZC]===>rtl8211_phy_poweroff\n"); + + return SW_OK; +} + +/****************************************************************************** +* +* rtl8211_phy_on - power on the phy +* +*/ +static sw_error_t +rtl8211_phy_poweron(rtk_uint32 dev_id, rtk_uint32 phy_id) +{ + SSDK_ERROR("[ZC]===>rtl8211_phy_poweron\n"); + + return SW_OK; +} + + +/****************************************************************************** +* +* rtl8211_interface_mode_set +* +*/ +static sw_error_t +rtl8211_phy_interface_mode_set(rtk_uint32 dev_id, rtk_uint32 phy_id, fal_port_interface_mode_t interface_mode) +{ + return SW_OK; +} + +static sw_error_t +rtl8211_phy_interface_mode_get(rtk_uint32 dev_id, rtk_uint32 phy_id, fal_port_interface_mode_t *interface_mode) +{ + SSDK_ERROR("[ZC]===>rtl8211_phy_interface_mode_get\n"); + *interface_mode = PORT_SGMII_PLUS; + return SW_OK; +} + +static sw_error_t +rtl8211_phy_interface_modestatus_get(rtk_uint32 dev_id, rtk_uint32 phy_id, fal_port_interface_mode_t *interface_mode) +{ + SSDK_ERROR("[ZC]===>rtl8211_phy_interface_modestatus_get\n"); + *interface_mode = PORT_SGMII_PLUS; + return SW_OK; +} + +static sw_error_t rtl8367_phy_api_ops_init(void) +{ + sw_error_t ret = SW_OK; + hsl_phy_ops_t *rtl8367_phy_api_ops = NULL; + + rtl8367_phy_api_ops = kzalloc(sizeof(hsl_phy_ops_t), GFP_KERNEL); + if (rtl8367_phy_api_ops == NULL) + { + SSDK_ERROR("rtl8211 phy ops kzalloc failed!\n"); + return -ENOMEM; + } + + phy_api_ops_init(RTL8367S_PHY_CHIP); + + rtl8367_phy_api_ops->phy_reg_write = rtl8211_phy_reg_write; + rtl8367_phy_api_ops->phy_reg_read = rtl8211_phy_reg_read; + rtl8367_phy_api_ops->phy_debug_write = rtl8211_phy_debug_write; + rtl8367_phy_api_ops->phy_debug_read = rtl8211_phy_debug_read; + rtl8367_phy_api_ops->phy_mmd_write = rtl8211_phy_mmd_write; + rtl8367_phy_api_ops->phy_mmd_read = rtl8211_phy_mmd_read; + rtl8367_phy_api_ops->phy_get_status = rtl8211_phy_get_status; + rtl8367_phy_api_ops->phy_speed_get = rtl8211_phy_get_speed; + rtl8367_phy_api_ops->phy_speed_set = rtl8211_phy_set_speed; + rtl8367_phy_api_ops->phy_duplex_get = rtl8211_phy_get_duplex; + rtl8367_phy_api_ops->phy_duplex_set = rtl8211_phy_set_duplex; + rtl8367_phy_api_ops->phy_autoneg_enable_set = rtl8211_phy_enable_autoneg; + rtl8367_phy_api_ops->phy_restart_autoneg = rtl8211_phy_restart_autoneg; + rtl8367_phy_api_ops->phy_autoneg_status_get = rtl8211_phy_autoneg_status; + rtl8367_phy_api_ops->phy_autoneg_adv_set = rtl8211_phy_set_autoneg_adv; + rtl8367_phy_api_ops->phy_autoneg_adv_get = rtl8211_phy_get_autoneg_adv; + rtl8367_phy_api_ops->phy_link_status_get = rtl8211_phy_get_link_status; + rtl8367_phy_api_ops->phy_reset = rtl8211_phy_reset; + rtl8367_phy_api_ops->phy_id_get = rtl8211_phy_get_phy_id; + rtl8367_phy_api_ops->phy_power_off = rtl8211_phy_poweroff; + rtl8367_phy_api_ops->phy_power_on = rtl8211_phy_poweron; + rtl8367_phy_api_ops->phy_interface_mode_set = rtl8211_phy_interface_mode_set; + rtl8367_phy_api_ops->phy_interface_mode_get = rtl8211_phy_interface_mode_get; + rtl8367_phy_api_ops->phy_interface_mode_status_get = rtl8211_phy_interface_modestatus_get; + + ret = hsl_phy_api_ops_register(RTL8367S_PHY_CHIP, rtl8367_phy_api_ops); + + if (ret == SW_OK) + { + SSDK_INFO("qca probe rtl8367 phy driver succeeded!\n"); + } + else + { + SSDK_ERROR("qca probe rtl8367 phy driver failed! (code: %d)\n", ret); + } + + return ret; +} + +int rtl8367s_init(rtk_uint32 dev_id, rtk_uint32 port_bmp) +{ + a_int32_t ret = 0; + static a_bool_t phy_ops_flag = A_FALSE; + + rtk_port_mac_ability_t mac_cfg; + rtk_mode_ext_t mode; +// rtk_vlan_cfg_t vlan1, vlan2; +// int i; +// rtk_uint32 rddata = 0; + + struct device_node *mdio; + struct mii_bus *mdio_bus; + + SSDK_ERROR("Init RTL8367, dev_id: %d, port_bmp: %0x\n", dev_id, port_bmp); + if(phy_ops_flag == A_FALSE && + rtl8367_phy_api_ops_init() == SW_OK) { + phy_ops_flag = A_TRUE; + } + + mdio = of_find_node_by_path("/soc/mdio@90000"); + + if (!mdio) + return -EINVAL; + + mdio_bus = of_mdio_find_bus(mdio); + + if (!mdio_bus) + return -EPROBE_DEFER; + + g_mii_bus = mdio_bus; + + rtk_switch_init(); +#if 0 + rtk_vlan_reset(); + rtk_vlan_init(); +#endif + memset(&mac_cfg, 0x0, sizeof(mac_cfg)); + mode = MODE_EXT_HSGMII; + mac_cfg.forcemode = MAC_FORCE; + mac_cfg.speed = PORT_SPEED_2500M; + mac_cfg.duplex = PORT_FULL_DUPLEX; + mac_cfg.link = PORT_LINKUP; + mac_cfg.nway = DISABLED; + mac_cfg.txpause = ENABLED; + mac_cfg.rxpause = ENABLED; +// rtk_port_macForceLinkExt_set(EXT_PORT0, mode, &mac_cfg); +// rtk_port_sgmiiNway_set(EXT_PORT0, DISABLED); +// rtk_port_phyEnableAll_set(ENABLED); + +#if 0 + for (i = UTP_PORT0; i <= UTP_PORT4; i++) + { + rtl8367c_phy_on(i); + } +#endif + return ret; +} + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/rtl8367s.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/rtl8367s.h new file mode 100644 index 00000000..3561c770 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/rtl8367s.h @@ -0,0 +1,14 @@ +#ifndef _RTL8367_PHY_H_ +#define _RTL8367_PHY_H_ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +int rtl8367s_init(rtk_uint32 dev_id, rtk_uint32 port_bmp); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* _RTL8367_PHY_H_ */ \ No newline at end of file diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/stat.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/stat.c new file mode 100644 index 00000000..c45c0fa3 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/stat.c @@ -0,0 +1,426 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8367C + * Feature : Here is a list of all functions and variables in MIB module. + * + */ + +#include +#include +#include +#include + +#include + + +#define MIB_NOT_SUPPORT (0xFFFF) + +/* Function Name: + * rtk_stat_global_reset + * Description: + * Reset global MIB counter. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * Reset MIB counter of ports. API will use global reset while port mask is all-ports. + */ +rtk_api_ret_t rtk_stat_global_reset(void) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->stat_global_reset) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->stat_global_reset(); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_stat_port_reset + * Description: + * Reset per port MIB counter by port. + * Input: + * port - port id. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * + */ +rtk_api_ret_t rtk_stat_port_reset(rtk_port_t port) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->stat_port_reset) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->stat_port_reset(port); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_stat_queueManage_reset + * Description: + * Reset queue manage MIB counter. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * + */ +rtk_api_ret_t rtk_stat_queueManage_reset(void) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->stat_queueManage_reset) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->stat_queueManage_reset(); + RTK_API_UNLOCK(); + + return retVal; +} + + +/* Function Name: + * rtk_stat_global_get + * Description: + * Get global MIB counter + * Input: + * cntr_idx - global counter index. + * Output: + * pCntr - global counter value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * Get global MIB counter by index definition. + */ +rtk_api_ret_t rtk_stat_global_get(rtk_stat_global_type_t cntr_idx, rtk_stat_counter_t *pCntr) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->stat_global_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->stat_global_get(cntr_idx, pCntr); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_stat_global_getAll + * Description: + * Get all global MIB counter + * Input: + * None + * Output: + * pGlobal_cntrs - global counter structure. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * Get all global MIB counter by index definition. + */ +rtk_api_ret_t rtk_stat_global_getAll(rtk_stat_global_cntr_t *pGlobal_cntrs) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->stat_global_getAll) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->stat_global_getAll(pGlobal_cntrs); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_stat_port_get + * Description: + * Get per port MIB counter by index + * Input: + * port - port id. + * cntr_idx - port counter index. + * Output: + * pCntr - MIB retrived counter. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * Get per port MIB counter by index definition. + */ +rtk_api_ret_t rtk_stat_port_get(rtk_port_t port, rtk_stat_port_type_t cntr_idx, rtk_stat_counter_t *pCntr) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->stat_port_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->stat_port_get(port, cntr_idx, pCntr); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_stat_port_getAll + * Description: + * Get all counters of one specified port in the specified device. + * Input: + * port - port id. + * Output: + * pPort_cntrs - buffer pointer of counter value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * Get all MIB counters of one port. + */ +rtk_api_ret_t rtk_stat_port_getAll(rtk_port_t port, rtk_stat_port_cntr_t *pPort_cntrs) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->stat_port_getAll) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->stat_port_getAll(port, pPort_cntrs); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_stat_logging_counterCfg_set + * Description: + * Set the type and mode of Logging Counter + * Input: + * idx - The index of Logging Counter. Should be even number only.(0,2,4,6,8.....30) + * mode - 32 bits or 64 bits mode + * type - Packet counter or byte counter + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_OUT_OF_RANGE - Out of range. + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * Set the type and mode of Logging Counter. + */ +rtk_api_ret_t rtk_stat_logging_counterCfg_set(rtk_uint32 idx, rtk_logging_counter_mode_t mode, rtk_logging_counter_type_t type) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->stat_logging_counterCfg_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->stat_logging_counterCfg_set(idx, mode, type); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_stat_logging_counterCfg_get + * Description: + * Get the type and mode of Logging Counter + * Input: + * idx - The index of Logging Counter. Should be even number only.(0,2,4,6,8.....30) + * Output: + * pMode - 32 bits or 64 bits mode + * pType - Packet counter or byte counter + * Return: + * RT_ERR_OK - OK + * RT_ERR_OUT_OF_RANGE - Out of range. + * RT_ERR_FAILED - Failed + * RT_ERR_NULL_POINTER - NULL Pointer + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * Get the type and mode of Logging Counter. + */ +rtk_api_ret_t rtk_stat_logging_counterCfg_get(rtk_uint32 idx, rtk_logging_counter_mode_t *pMode, rtk_logging_counter_type_t *pType) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->stat_logging_counterCfg_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->stat_logging_counterCfg_get(idx, pMode, pType); + RTK_API_UNLOCK(); + + return retVal; +} + + +/* Function Name: + * rtk_stat_logging_counter_reset + * Description: + * Reset Logging Counter + * Input: + * idx - The index of Logging Counter. (0~31) + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_OUT_OF_RANGE - Out of range. + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * Reset Logging Counter. + */ +rtk_api_ret_t rtk_stat_logging_counter_reset(rtk_uint32 idx) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->stat_logging_counter_reset) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->stat_logging_counter_reset(idx); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_stat_logging_counter_get + * Description: + * Get Logging Counter + * Input: + * idx - The index of Logging Counter. (0~31) + * Output: + * pCnt - Logging counter value + * Return: + * RT_ERR_OK - OK + * RT_ERR_OUT_OF_RANGE - Out of range. + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * Get Logging Counter. + */ +rtk_api_ret_t rtk_stat_logging_counter_get(rtk_uint32 idx, rtk_uint32 *pCnt) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->stat_logging_counter_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->stat_logging_counter_get(idx, pCnt); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_stat_lengthMode_set + * Description: + * Set Legnth mode. + * Input: + * txMode - The length counting mode + * rxMode - The length counting mode + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_INPUT - Out of range. + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * + */ +rtk_api_ret_t rtk_stat_lengthMode_set(rtk_stat_lengthMode_t txMode, rtk_stat_lengthMode_t rxMode) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->stat_lengthMode_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->stat_lengthMode_set(txMode, rxMode); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_stat_lengthMode_get + * Description: + * Get Legnth mode. + * Input: + * None. + * Output: + * pTxMode - The length counting mode + * pRxMode - The length counting mode + * Return: + * RT_ERR_OK - OK + * RT_ERR_INPUT - Out of range. + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +rtk_api_ret_t rtk_stat_lengthMode_get(rtk_stat_lengthMode_t *pTxMode, rtk_stat_lengthMode_t *pRxMode) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->stat_lengthMode_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->stat_lengthMode_get(pTxMode, pRxMode); + RTK_API_UNLOCK(); + + return retVal; +} + + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/stat.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/stat.h new file mode 100644 index 00000000..61c05b12 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/stat.h @@ -0,0 +1,435 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8367/RTL8367C switch high-level API + * + * Feature : The file includes MIB module high-layer API defination + * + */ + +#ifndef __RTK_API_STAT_H__ +#define __RTK_API_STAT_H__ + +/* + * Data Type Declaration + */ +typedef rtk_u_long_t rtk_stat_counter_t; + +/* global statistic counter structure */ +typedef struct rtk_stat_global_cntr_s +{ + rtk_uint64 dot1dTpLearnedEntryDiscards; +}rtk_stat_global_cntr_t; + +typedef enum rtk_stat_global_type_e +{ + DOT1D_TP_LEARNED_ENTRY_DISCARDS_INDEX = 58, + MIB_GLOBAL_CNTR_END +}rtk_stat_global_type_t; + +/* port statistic counter structure */ +typedef struct rtk_stat_port_cntr_s +{ + rtk_uint64 ifInOctets; + rtk_uint32 dot3StatsFCSErrors; + rtk_uint32 dot3StatsSymbolErrors; + rtk_uint32 dot3InPauseFrames; + rtk_uint32 dot3ControlInUnknownOpcodes; + rtk_uint32 etherStatsFragments; + rtk_uint32 etherStatsJabbers; + rtk_uint32 ifInUcastPkts; + rtk_uint32 etherStatsDropEvents; + rtk_uint64 etherStatsOctets; + rtk_uint32 etherStatsUndersizePkts; + rtk_uint32 etherStatsOversizePkts; + rtk_uint32 etherStatsPkts64Octets; + rtk_uint32 etherStatsPkts65to127Octets; + rtk_uint32 etherStatsPkts128to255Octets; + rtk_uint32 etherStatsPkts256to511Octets; + rtk_uint32 etherStatsPkts512to1023Octets; + rtk_uint32 etherStatsPkts1024toMaxOctets; + rtk_uint32 etherStatsMcastPkts; + rtk_uint32 etherStatsBcastPkts; + rtk_uint64 ifOutOctets; + rtk_uint32 dot3StatsSingleCollisionFrames; + rtk_uint32 dot3StatsMultipleCollisionFrames; + rtk_uint32 dot3StatsDeferredTransmissions; + rtk_uint32 dot3StatsLateCollisions; + rtk_uint32 etherStatsCollisions; + rtk_uint32 dot3StatsExcessiveCollisions; + rtk_uint32 dot3OutPauseFrames; + rtk_uint32 dot1dBasePortDelayExceededDiscards; + rtk_uint32 dot1dTpPortInDiscards; + rtk_uint32 ifOutUcastPkts; + rtk_uint32 ifOutMulticastPkts; + rtk_uint32 ifOutBrocastPkts; + rtk_uint32 outOampduPkts; + rtk_uint32 inOampduPkts; + rtk_uint32 pktgenPkts; + rtk_uint32 inMldChecksumError; + rtk_uint32 inIgmpChecksumError; + rtk_uint32 inMldSpecificQuery; + rtk_uint32 inMldGeneralQuery; + rtk_uint32 inIgmpSpecificQuery; + rtk_uint32 inIgmpGeneralQuery; + rtk_uint32 inMldLeaves; + rtk_uint32 inIgmpLeaves; + rtk_uint32 inIgmpJoinsSuccess; + rtk_uint32 inIgmpJoinsFail; + rtk_uint32 inMldJoinsSuccess; + rtk_uint32 inMldJoinsFail; + rtk_uint32 inReportSuppressionDrop; + rtk_uint32 inLeaveSuppressionDrop; + rtk_uint32 outIgmpReports; + rtk_uint32 outIgmpLeaves; + rtk_uint32 outIgmpGeneralQuery; + rtk_uint32 outIgmpSpecificQuery; + rtk_uint32 outMldReports; + rtk_uint32 outMldLeaves; + rtk_uint32 outMldGeneralQuery; + rtk_uint32 outMldSpecificQuery; + rtk_uint32 inKnownMulticastPkts; + rtk_uint32 ifInMulticastPkts; + rtk_uint32 ifInBroadcastPkts; + rtk_uint32 ifOutDiscards; +}rtk_stat_port_cntr_t; + +/* port statistic counter index */ +typedef enum rtk_stat_port_type_e +{ + STAT_IfInOctets = 0, + STAT_Dot3StatsFCSErrors, + STAT_Dot3StatsSymbolErrors, + STAT_Dot3InPauseFrames, + STAT_Dot3ControlInUnknownOpcodes, + STAT_EtherStatsFragments, + STAT_EtherStatsJabbers, + STAT_IfInUcastPkts, + STAT_EtherStatsDropEvents, + STAT_EtherStatsOctets, + STAT_EtherStatsUnderSizePkts, + STAT_EtherOversizeStats, + STAT_EtherStatsPkts64Octets, + STAT_EtherStatsPkts65to127Octets, + STAT_EtherStatsPkts128to255Octets, + STAT_EtherStatsPkts256to511Octets, + STAT_EtherStatsPkts512to1023Octets, + STAT_EtherStatsPkts1024to1518Octets, + STAT_EtherStatsMulticastPkts, + STAT_EtherStatsBroadcastPkts, + STAT_IfOutOctets, + STAT_Dot3StatsSingleCollisionFrames, + STAT_Dot3StatsMultipleCollisionFrames, + STAT_Dot3StatsDeferredTransmissions, + STAT_Dot3StatsLateCollisions, + STAT_EtherStatsCollisions, + STAT_Dot3StatsExcessiveCollisions, + STAT_Dot3OutPauseFrames, + STAT_Dot1dBasePortDelayExceededDiscards, + STAT_Dot1dTpPortInDiscards, + STAT_IfOutUcastPkts, + STAT_IfOutMulticastPkts, + STAT_IfOutBroadcastPkts, + STAT_OutOampduPkts, + STAT_InOampduPkts, + STAT_PktgenPkts, + STAT_InMldChecksumError, + STAT_InIgmpChecksumError, + STAT_InMldSpecificQuery, + STAT_InMldGeneralQuery, + STAT_InIgmpSpecificQuery, + STAT_InIgmpGeneralQuery, + STAT_InMldLeaves, + STAT_InIgmpInterfaceLeaves, + STAT_InIgmpJoinsSuccess, + STAT_InIgmpJoinsFail, + STAT_InMldJoinsSuccess, + STAT_InMldJoinsFail, + STAT_InReportSuppressionDrop, + STAT_InLeaveSuppressionDrop, + STAT_OutIgmpReports, + STAT_OutIgmpLeaves, + STAT_OutIgmpGeneralQuery, + STAT_OutIgmpSpecificQuery, + STAT_OutMldReports, + STAT_OutMldLeaves, + STAT_OutMldGeneralQuery, + STAT_OutMldSpecificQuery, + STAT_InKnownMulticastPkts, + STAT_IfInMulticastPkts, + STAT_IfInBroadcastPkts, + STAT_IfOutDiscards, + STAT_PORT_CNTR_END +}rtk_stat_port_type_t; + +typedef enum rtk_logging_counter_mode_e +{ + LOGGING_MODE_32BIT = 0, + LOGGING_MODE_64BIT, + LOGGING_MODE_END +}rtk_logging_counter_mode_t; + +typedef enum rtk_logging_counter_type_e +{ + LOGGING_TYPE_PACKET = 0, + LOGGING_TYPE_BYTE, + LOGGING_TYPE_END +}rtk_logging_counter_type_t; + +typedef enum rtk_stat_lengthMode_e +{ + LENGTH_MODE_EXC_TAG = 0, + LENGTH_MODE_INC_TAG, + LENGTH_MODE_END +}rtk_stat_lengthMode_t; + + + +/* Function Name: + * rtk_stat_global_reset + * Description: + * Reset global MIB counter. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * Reset MIB counter of ports. API will use global reset while port mask is all-ports. + */ +extern rtk_api_ret_t rtk_stat_global_reset(void); + +/* Function Name: + * rtk_stat_port_reset + * Description: + * Reset per port MIB counter by port. + * Input: + * port - port id. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * + */ +extern rtk_api_ret_t rtk_stat_port_reset(rtk_port_t port); + +/* Function Name: + * rtk_stat_queueManage_reset + * Description: + * Reset queue manage MIB counter. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * + */ +extern rtk_api_ret_t rtk_stat_queueManage_reset(void); + +/* Function Name: + * rtk_stat_global_get + * Description: + * Get global MIB counter + * Input: + * cntr_idx - global counter index. + * Output: + * pCntr - global counter value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * Get global MIB counter by index definition. + */ +extern rtk_api_ret_t rtk_stat_global_get(rtk_stat_global_type_t cntr_idx, rtk_stat_counter_t *pCntr); + +/* Function Name: + * rtk_stat_global_getAll + * Description: + * Get all global MIB counter + * Input: + * None + * Output: + * pGlobal_cntrs - global counter structure. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * Get all global MIB counter by index definition. + */ +extern rtk_api_ret_t rtk_stat_global_getAll(rtk_stat_global_cntr_t *pGlobal_cntrs); + +/* Function Name: + * rtk_stat_port_get + * Description: + * Get per port MIB counter by index + * Input: + * port - port id. + * cntr_idx - port counter index. + * Output: + * pCntr - MIB retrived counter. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * Get per port MIB counter by index definition. + */ +extern rtk_api_ret_t rtk_stat_port_get(rtk_port_t port, rtk_stat_port_type_t cntr_idx, rtk_stat_counter_t *pCntr); + +/* Function Name: + * rtk_stat_port_getAll + * Description: + * Get all counters of one specified port in the specified device. + * Input: + * port - port id. + * Output: + * pPort_cntrs - buffer pointer of counter value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * Get all MIB counters of one port. + */ +extern rtk_api_ret_t rtk_stat_port_getAll(rtk_port_t port, rtk_stat_port_cntr_t *pPort_cntrs); + +/* Function Name: + * rtk_stat_logging_counterCfg_set + * Description: + * Set the type and mode of Logging Counter + * Input: + * idx - The index of Logging Counter. Should be even number only.(0,2,4,6,8.....30) + * mode - 32 bits or 64 bits mode + * type - Packet counter or byte counter + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_OUT_OF_RANGE - Out of range. + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * Set the type and mode of Logging Counter. + */ +extern rtk_api_ret_t rtk_stat_logging_counterCfg_set(rtk_uint32 idx, rtk_logging_counter_mode_t mode, rtk_logging_counter_type_t type); + +/* Function Name: + * rtk_stat_logging_counterCfg_get + * Description: + * Get the type and mode of Logging Counter + * Input: + * idx - The index of Logging Counter. Should be even number only.(0,2,4,6,8.....30) + * Output: + * pMode - 32 bits or 64 bits mode + * pType - Packet counter or byte counter + * Return: + * RT_ERR_OK - OK + * RT_ERR_OUT_OF_RANGE - Out of range. + * RT_ERR_FAILED - Failed + * RT_ERR_NULL_POINTER - NULL Pointer + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * Get the type and mode of Logging Counter. + */ +extern rtk_api_ret_t rtk_stat_logging_counterCfg_get(rtk_uint32 idx, rtk_logging_counter_mode_t *pMode, rtk_logging_counter_type_t *pType); + +/* Function Name: + * rtk_stat_logging_counter_reset + * Description: + * Reset Logging Counter + * Input: + * idx - The index of Logging Counter. (0~31) + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_OUT_OF_RANGE - Out of range. + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * Reset Logging Counter. + */ +extern rtk_api_ret_t rtk_stat_logging_counter_reset(rtk_uint32 idx); + +/* Function Name: + * rtk_stat_logging_counter_get + * Description: + * Get Logging Counter + * Input: + * idx - The index of Logging Counter. (0~31) + * Output: + * pCnt - Logging counter value + * Return: + * RT_ERR_OK - OK + * RT_ERR_OUT_OF_RANGE - Out of range. + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * Get Logging Counter. + */ +extern rtk_api_ret_t rtk_stat_logging_counter_get(rtk_uint32 idx, rtk_uint32 *pCnt); + +/* Function Name: + * rtk_stat_lengthMode_set + * Description: + * Set Legnth mode. + * Input: + * txMode - The length counting mode + * rxMode - The length counting mode + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_INPUT - Out of range. + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * + */ +extern rtk_api_ret_t rtk_stat_lengthMode_set(rtk_stat_lengthMode_t txMode, rtk_stat_lengthMode_t rxMode); + +/* Function Name: + * rtk_stat_lengthMode_get + * Description: + * Get Legnth mode. + * Input: + * None. + * Output: + * pTxMode - The length counting mode + * pRxMode - The length counting mode + * Return: + * RT_ERR_OK - OK + * RT_ERR_INPUT - Out of range. + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +extern rtk_api_ret_t rtk_stat_lengthMode_get(rtk_stat_lengthMode_t *pTxMode, rtk_stat_lengthMode_t *pRxMode); + +#endif /* __RTK_API_STAT_H__ */ + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/storm.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/storm.c new file mode 100644 index 00000000..da398a4d --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/storm.c @@ -0,0 +1,506 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8367C + * Feature : Here is a list of all functions and variables in Storm module. + * + */ + +#include +#include +#include +#include + +#include + +/* Function Name: + * rtk_rate_stormControlMeterIdx_set + * Description: + * Set the storm control meter index. + * Input: + * port - port id + * storm_type - storm group type + * index - storm control meter index. + * Output: + * None. + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - Invalid port id + * RT_ERR_FILTER_METER_ID - Invalid meter + * Note: + * + */ +rtk_api_ret_t rtk_rate_stormControlMeterIdx_set(rtk_port_t port, rtk_rate_storm_group_t stormType, rtk_uint32 index) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rate_stormControlMeterIdx_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rate_stormControlMeterIdx_set(port, stormType, index); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_rate_stormControlMeterIdx_get + * Description: + * Get the storm control meter index. + * Input: + * port - port id + * storm_type - storm group type + * Output: + * pIndex - storm control meter index. + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - Invalid port id + * RT_ERR_FILTER_METER_ID - Invalid meter + * Note: + * + */ +rtk_api_ret_t rtk_rate_stormControlMeterIdx_get(rtk_port_t port, rtk_rate_storm_group_t stormType, rtk_uint32 *pIndex) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rate_stormControlMeterIdx_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rate_stormControlMeterIdx_get(port, stormType, pIndex); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_rate_stormControlPortEnable_set + * Description: + * Set enable status of storm control on specified port. + * Input: + * port - port id + * stormType - storm group type + * enable - enable status of storm control + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +rtk_api_ret_t rtk_rate_stormControlPortEnable_set(rtk_port_t port, rtk_rate_storm_group_t stormType, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rate_stormControlPortEnable_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rate_stormControlPortEnable_set(port, stormType, enable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_rate_stormControlPortEnable_set + * Description: + * Set enable status of storm control on specified port. + * Input: + * port - port id + * stormType - storm group type + * Output: + * pEnable - enable status of storm control + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +rtk_api_ret_t rtk_rate_stormControlPortEnable_get(rtk_port_t port, rtk_rate_storm_group_t stormType, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rate_stormControlPortEnable_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rate_stormControlPortEnable_get(port, stormType, pEnable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_storm_bypass_set + * Description: + * Set bypass storm filter control configuration. + * Input: + * type - Bypass storm filter control type. + * enable - Bypass status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_ENABLE - Invalid IFG parameter + * Note: + * + * This API can set per-port bypass stomr filter control frame type including RMA and igmp. + * The bypass frame type is as following: + * - BYPASS_BRG_GROUP, + * - BYPASS_FD_PAUSE, + * - BYPASS_SP_MCAST, + * - BYPASS_1X_PAE, + * - BYPASS_UNDEF_BRG_04, + * - BYPASS_UNDEF_BRG_05, + * - BYPASS_UNDEF_BRG_06, + * - BYPASS_UNDEF_BRG_07, + * - BYPASS_PROVIDER_BRIDGE_GROUP_ADDRESS, + * - BYPASS_UNDEF_BRG_09, + * - BYPASS_UNDEF_BRG_0A, + * - BYPASS_UNDEF_BRG_0B, + * - BYPASS_UNDEF_BRG_0C, + * - BYPASS_PROVIDER_BRIDGE_GVRP_ADDRESS, + * - BYPASS_8021AB, + * - BYPASS_UNDEF_BRG_0F, + * - BYPASS_BRG_MNGEMENT, + * - BYPASS_UNDEFINED_11, + * - BYPASS_UNDEFINED_12, + * - BYPASS_UNDEFINED_13, + * - BYPASS_UNDEFINED_14, + * - BYPASS_UNDEFINED_15, + * - BYPASS_UNDEFINED_16, + * - BYPASS_UNDEFINED_17, + * - BYPASS_UNDEFINED_18, + * - BYPASS_UNDEFINED_19, + * - BYPASS_UNDEFINED_1A, + * - BYPASS_UNDEFINED_1B, + * - BYPASS_UNDEFINED_1C, + * - BYPASS_UNDEFINED_1D, + * - BYPASS_UNDEFINED_1E, + * - BYPASS_UNDEFINED_1F, + * - BYPASS_GMRP, + * - BYPASS_GVRP, + * - BYPASS_UNDEF_GARP_22, + * - BYPASS_UNDEF_GARP_23, + * - BYPASS_UNDEF_GARP_24, + * - BYPASS_UNDEF_GARP_25, + * - BYPASS_UNDEF_GARP_26, + * - BYPASS_UNDEF_GARP_27, + * - BYPASS_UNDEF_GARP_28, + * - BYPASS_UNDEF_GARP_29, + * - BYPASS_UNDEF_GARP_2A, + * - BYPASS_UNDEF_GARP_2B, + * - BYPASS_UNDEF_GARP_2C, + * - BYPASS_UNDEF_GARP_2D, + * - BYPASS_UNDEF_GARP_2E, + * - BYPASS_UNDEF_GARP_2F, + * - BYPASS_IGMP. + * - BYPASS_CDP. + * - BYPASS_CSSTP. + * - BYPASS_LLDP. + */ +rtk_api_ret_t rtk_storm_bypass_set(rtk_storm_bypass_t type, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->storm_bypass_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->storm_bypass_set(type, enable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_storm_bypass_get + * Description: + * Get bypass storm filter control configuration. + * Input: + * type - Bypass storm filter control type. + * Output: + * pEnable - Bypass status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can get per-port bypass stomr filter control frame type including RMA and igmp. + * The bypass frame type is as following: + * - BYPASS_BRG_GROUP, + * - BYPASS_FD_PAUSE, + * - BYPASS_SP_MCAST, + * - BYPASS_1X_PAE, + * - BYPASS_UNDEF_BRG_04, + * - BYPASS_UNDEF_BRG_05, + * - BYPASS_UNDEF_BRG_06, + * - BYPASS_UNDEF_BRG_07, + * - BYPASS_PROVIDER_BRIDGE_GROUP_ADDRESS, + * - BYPASS_UNDEF_BRG_09, + * - BYPASS_UNDEF_BRG_0A, + * - BYPASS_UNDEF_BRG_0B, + * - BYPASS_UNDEF_BRG_0C, + * - BYPASS_PROVIDER_BRIDGE_GVRP_ADDRESS, + * - BYPASS_8021AB, + * - BYPASS_UNDEF_BRG_0F, + * - BYPASS_BRG_MNGEMENT, + * - BYPASS_UNDEFINED_11, + * - BYPASS_UNDEFINED_12, + * - BYPASS_UNDEFINED_13, + * - BYPASS_UNDEFINED_14, + * - BYPASS_UNDEFINED_15, + * - BYPASS_UNDEFINED_16, + * - BYPASS_UNDEFINED_17, + * - BYPASS_UNDEFINED_18, + * - BYPASS_UNDEFINED_19, + * - BYPASS_UNDEFINED_1A, + * - BYPASS_UNDEFINED_1B, + * - BYPASS_UNDEFINED_1C, + * - BYPASS_UNDEFINED_1D, + * - BYPASS_UNDEFINED_1E, + * - BYPASS_UNDEFINED_1F, + * - BYPASS_GMRP, + * - BYPASS_GVRP, + * - BYPASS_UNDEF_GARP_22, + * - BYPASS_UNDEF_GARP_23, + * - BYPASS_UNDEF_GARP_24, + * - BYPASS_UNDEF_GARP_25, + * - BYPASS_UNDEF_GARP_26, + * - BYPASS_UNDEF_GARP_27, + * - BYPASS_UNDEF_GARP_28, + * - BYPASS_UNDEF_GARP_29, + * - BYPASS_UNDEF_GARP_2A, + * - BYPASS_UNDEF_GARP_2B, + * - BYPASS_UNDEF_GARP_2C, + * - BYPASS_UNDEF_GARP_2D, + * - BYPASS_UNDEF_GARP_2E, + * - BYPASS_UNDEF_GARP_2F, + * - BYPASS_IGMP. + * - BYPASS_CDP. + * - BYPASS_CSSTP. + * - BYPASS_LLDP. + */ +rtk_api_ret_t rtk_storm_bypass_get(rtk_storm_bypass_t type, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->storm_bypass_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->storm_bypass_get(type, pEnable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_rate_stormControlExtPortmask_set + * Description: + * Set externsion storm control port mask + * Input: + * pPortmask - port mask + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +rtk_api_ret_t rtk_rate_stormControlExtPortmask_set(rtk_portmask_t *pPortmask) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rate_stormControlExtPortmask_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rate_stormControlExtPortmask_set(pPortmask); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_rate_stormControlExtPortmask_get + * Description: + * Set externsion storm control port mask + * Input: + * None + * Output: + * pPortmask - port mask + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +rtk_api_ret_t rtk_rate_stormControlExtPortmask_get(rtk_portmask_t *pPortmask) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rate_stormControlExtPortmask_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rate_stormControlExtPortmask_get(pPortmask); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_rate_stormControlExtEnable_set + * Description: + * Set externsion storm control state + * Input: + * stormType - storm group type + * enable - externsion storm control state + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +rtk_api_ret_t rtk_rate_stormControlExtEnable_set(rtk_rate_storm_group_t stormType, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rate_stormControlExtEnable_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rate_stormControlExtEnable_set(stormType, enable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_rate_stormControlExtEnable_get + * Description: + * Get externsion storm control state + * Input: + * stormType - storm group type + * Output: + * pEnable - externsion storm control state + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +rtk_api_ret_t rtk_rate_stormControlExtEnable_get(rtk_rate_storm_group_t stormType, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rate_stormControlExtEnable_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rate_stormControlExtEnable_get(stormType, pEnable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_rate_stormControlExtMeterIdx_set + * Description: + * Set externsion storm control meter index + * Input: + * stormType - storm group type + * index - externsion storm control state + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +rtk_api_ret_t rtk_rate_stormControlExtMeterIdx_set(rtk_rate_storm_group_t stormType, rtk_uint32 index) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rate_stormControlExtMeterIdx_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rate_stormControlExtMeterIdx_set(stormType, index); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_rate_stormControlExtMeterIdx_get + * Description: + * Get externsion storm control meter index + * Input: + * stormType - storm group type + * pIndex - externsion storm control state + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +rtk_api_ret_t rtk_rate_stormControlExtMeterIdx_get(rtk_rate_storm_group_t stormType, rtk_uint32 *pIndex) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rate_stormControlExtMeterIdx_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rate_stormControlExtMeterIdx_get(stormType, pIndex); + RTK_API_UNLOCK(); + + return retVal; +} + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/storm.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/storm.h new file mode 100644 index 00000000..2aff22a8 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/storm.h @@ -0,0 +1,419 @@ + /* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8367/RTL8367C switch high-level API + * + * Feature : The file includes Storm module high-layer API defination + * + */ + +#ifndef __RTK_API_STORM_H__ +#define __RTK_API_STORM_H__ + +typedef enum rtk_rate_storm_group_e +{ + STORM_GROUP_UNKNOWN_UNICAST = 0, + STORM_GROUP_UNKNOWN_MULTICAST, + STORM_GROUP_MULTICAST, + STORM_GROUP_BROADCAST, + STORM_GROUP_END +} rtk_rate_storm_group_t; + +typedef enum rtk_storm_bypass_e +{ + BYPASS_BRG_GROUP = 0, + BYPASS_FD_PAUSE, + BYPASS_SP_MCAST, + BYPASS_1X_PAE, + BYPASS_UNDEF_BRG_04, + BYPASS_UNDEF_BRG_05, + BYPASS_UNDEF_BRG_06, + BYPASS_UNDEF_BRG_07, + BYPASS_PROVIDER_BRIDGE_GROUP_ADDRESS, + BYPASS_UNDEF_BRG_09, + BYPASS_UNDEF_BRG_0A, + BYPASS_UNDEF_BRG_0B, + BYPASS_UNDEF_BRG_0C, + BYPASS_PROVIDER_BRIDGE_GVRP_ADDRESS, + BYPASS_8021AB, + BYPASS_UNDEF_BRG_0F, + BYPASS_BRG_MNGEMENT, + BYPASS_UNDEFINED_11, + BYPASS_UNDEFINED_12, + BYPASS_UNDEFINED_13, + BYPASS_UNDEFINED_14, + BYPASS_UNDEFINED_15, + BYPASS_UNDEFINED_16, + BYPASS_UNDEFINED_17, + BYPASS_UNDEFINED_18, + BYPASS_UNDEFINED_19, + BYPASS_UNDEFINED_1A, + BYPASS_UNDEFINED_1B, + BYPASS_UNDEFINED_1C, + BYPASS_UNDEFINED_1D, + BYPASS_UNDEFINED_1E, + BYPASS_UNDEFINED_1F, + BYPASS_GMRP, + BYPASS_GVRP, + BYPASS_UNDEF_GARP_22, + BYPASS_UNDEF_GARP_23, + BYPASS_UNDEF_GARP_24, + BYPASS_UNDEF_GARP_25, + BYPASS_UNDEF_GARP_26, + BYPASS_UNDEF_GARP_27, + BYPASS_UNDEF_GARP_28, + BYPASS_UNDEF_GARP_29, + BYPASS_UNDEF_GARP_2A, + BYPASS_UNDEF_GARP_2B, + BYPASS_UNDEF_GARP_2C, + BYPASS_UNDEF_GARP_2D, + BYPASS_UNDEF_GARP_2E, + BYPASS_UNDEF_GARP_2F, + BYPASS_IGMP, + BYPASS_CDP, + BYPASS_CSSTP, + BYPASS_LLDP, + BYPASS_END, +}rtk_storm_bypass_t; + +/* Function Name: + * rtk_rate_stormControlMeterIdx_set + * Description: + * Set the storm control meter index. + * Input: + * port - port id + * storm_type - storm group type + * index - storm control meter index. + * Output: + * None. + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - Invalid port id + * RT_ERR_FILTER_METER_ID - Invalid meter + * Note: + * + */ +extern rtk_api_ret_t rtk_rate_stormControlMeterIdx_set(rtk_port_t port, rtk_rate_storm_group_t stormType, rtk_uint32 index); + +/* Function Name: + * rtk_rate_stormControlMeterIdx_get + * Description: + * Get the storm control meter index. + * Input: + * port - port id + * storm_type - storm group type + * Output: + * pIndex - storm control meter index. + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - Invalid port id + * RT_ERR_FILTER_METER_ID - Invalid meter + * Note: + * + */ +extern rtk_api_ret_t rtk_rate_stormControlMeterIdx_get(rtk_port_t port, rtk_rate_storm_group_t stormType, rtk_uint32 *pIndex); + +/* Function Name: + * rtk_rate_stormControlPortEnable_set + * Description: + * Set enable status of storm control on specified port. + * Input: + * port - port id + * stormType - storm group type + * enable - enable status of storm control + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +extern rtk_api_ret_t rtk_rate_stormControlPortEnable_set(rtk_port_t port, rtk_rate_storm_group_t stormType, rtk_enable_t enable); + +/* Function Name: + * rtk_rate_stormControlPortEnable_set + * Description: + * Set enable status of storm control on specified port. + * Input: + * port - port id + * stormType - storm group type + * Output: + * pEnable - enable status of storm control + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +extern rtk_api_ret_t rtk_rate_stormControlPortEnable_get(rtk_port_t port, rtk_rate_storm_group_t stormType, rtk_enable_t *pEnable); + +/* Function Name: + * rtk_storm_bypass_set + * Description: + * Set bypass storm filter control configuration. + * Input: + * type - Bypass storm filter control type. + * enable - Bypass status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_ENABLE - Invalid IFG parameter + * Note: + * + * This API can set per-port bypass stomr filter control frame type including RMA and igmp. + * The bypass frame type is as following: + * - BYPASS_BRG_GROUP, + * - BYPASS_FD_PAUSE, + * - BYPASS_SP_MCAST, + * - BYPASS_1X_PAE, + * - BYPASS_UNDEF_BRG_04, + * - BYPASS_UNDEF_BRG_05, + * - BYPASS_UNDEF_BRG_06, + * - BYPASS_UNDEF_BRG_07, + * - BYPASS_PROVIDER_BRIDGE_GROUP_ADDRESS, + * - BYPASS_UNDEF_BRG_09, + * - BYPASS_UNDEF_BRG_0A, + * - BYPASS_UNDEF_BRG_0B, + * - BYPASS_UNDEF_BRG_0C, + * - BYPASS_PROVIDER_BRIDGE_GVRP_ADDRESS, + * - BYPASS_8021AB, + * - BYPASS_UNDEF_BRG_0F, + * - BYPASS_BRG_MNGEMENT, + * - BYPASS_UNDEFINED_11, + * - BYPASS_UNDEFINED_12, + * - BYPASS_UNDEFINED_13, + * - BYPASS_UNDEFINED_14, + * - BYPASS_UNDEFINED_15, + * - BYPASS_UNDEFINED_16, + * - BYPASS_UNDEFINED_17, + * - BYPASS_UNDEFINED_18, + * - BYPASS_UNDEFINED_19, + * - BYPASS_UNDEFINED_1A, + * - BYPASS_UNDEFINED_1B, + * - BYPASS_UNDEFINED_1C, + * - BYPASS_UNDEFINED_1D, + * - BYPASS_UNDEFINED_1E, + * - BYPASS_UNDEFINED_1F, + * - BYPASS_GMRP, + * - BYPASS_GVRP, + * - BYPASS_UNDEF_GARP_22, + * - BYPASS_UNDEF_GARP_23, + * - BYPASS_UNDEF_GARP_24, + * - BYPASS_UNDEF_GARP_25, + * - BYPASS_UNDEF_GARP_26, + * - BYPASS_UNDEF_GARP_27, + * - BYPASS_UNDEF_GARP_28, + * - BYPASS_UNDEF_GARP_29, + * - BYPASS_UNDEF_GARP_2A, + * - BYPASS_UNDEF_GARP_2B, + * - BYPASS_UNDEF_GARP_2C, + * - BYPASS_UNDEF_GARP_2D, + * - BYPASS_UNDEF_GARP_2E, + * - BYPASS_UNDEF_GARP_2F, + * - BYPASS_IGMP. + */ +extern rtk_api_ret_t rtk_storm_bypass_set(rtk_storm_bypass_t type, rtk_enable_t enable); + +/* Function Name: + * rtk_storm_bypass_get + * Description: + * Get bypass storm filter control configuration. + * Input: + * type - Bypass storm filter control type. + * Output: + * pEnable - Bypass status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can get per-port bypass stomr filter control frame type including RMA and igmp. + * The bypass frame type is as following: + * - BYPASS_BRG_GROUP, + * - BYPASS_FD_PAUSE, + * - BYPASS_SP_MCAST, + * - BYPASS_1X_PAE, + * - BYPASS_UNDEF_BRG_04, + * - BYPASS_UNDEF_BRG_05, + * - BYPASS_UNDEF_BRG_06, + * - BYPASS_UNDEF_BRG_07, + * - BYPASS_PROVIDER_BRIDGE_GROUP_ADDRESS, + * - BYPASS_UNDEF_BRG_09, + * - BYPASS_UNDEF_BRG_0A, + * - BYPASS_UNDEF_BRG_0B, + * - BYPASS_UNDEF_BRG_0C, + * - BYPASS_PROVIDER_BRIDGE_GVRP_ADDRESS, + * - BYPASS_8021AB, + * - BYPASS_UNDEF_BRG_0F, + * - BYPASS_BRG_MNGEMENT, + * - BYPASS_UNDEFINED_11, + * - BYPASS_UNDEFINED_12, + * - BYPASS_UNDEFINED_13, + * - BYPASS_UNDEFINED_14, + * - BYPASS_UNDEFINED_15, + * - BYPASS_UNDEFINED_16, + * - BYPASS_UNDEFINED_17, + * - BYPASS_UNDEFINED_18, + * - BYPASS_UNDEFINED_19, + * - BYPASS_UNDEFINED_1A, + * - BYPASS_UNDEFINED_1B, + * - BYPASS_UNDEFINED_1C, + * - BYPASS_UNDEFINED_1D, + * - BYPASS_UNDEFINED_1E, + * - BYPASS_UNDEFINED_1F, + * - BYPASS_GMRP, + * - BYPASS_GVRP, + * - BYPASS_UNDEF_GARP_22, + * - BYPASS_UNDEF_GARP_23, + * - BYPASS_UNDEF_GARP_24, + * - BYPASS_UNDEF_GARP_25, + * - BYPASS_UNDEF_GARP_26, + * - BYPASS_UNDEF_GARP_27, + * - BYPASS_UNDEF_GARP_28, + * - BYPASS_UNDEF_GARP_29, + * - BYPASS_UNDEF_GARP_2A, + * - BYPASS_UNDEF_GARP_2B, + * - BYPASS_UNDEF_GARP_2C, + * - BYPASS_UNDEF_GARP_2D, + * - BYPASS_UNDEF_GARP_2E, + * - BYPASS_UNDEF_GARP_2F, + * - BYPASS_IGMP. + */ +extern rtk_api_ret_t rtk_storm_bypass_get(rtk_storm_bypass_t type, rtk_enable_t *pEnable); + +/* Function Name: + * rtk_rate_stormControlExtPortmask_set + * Description: + * Set externsion storm control port mask + * Input: + * pPortmask - port mask + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +extern rtk_api_ret_t rtk_rate_stormControlExtPortmask_set(rtk_portmask_t *pPortmask); + +/* Function Name: + * rtk_rate_stormControlExtPortmask_get + * Description: + * Set externsion storm control port mask + * Input: + * None + * Output: + * pPortmask - port mask + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +extern rtk_api_ret_t rtk_rate_stormControlExtPortmask_get(rtk_portmask_t *pPortmask); + +/* Function Name: + * rtk_rate_stormControlExtEnable_set + * Description: + * Set externsion storm control state + * Input: + * stormType - storm group type + * enable - externsion storm control state + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +extern rtk_api_ret_t rtk_rate_stormControlExtEnable_set(rtk_rate_storm_group_t stormType, rtk_enable_t enable); + +/* Function Name: + * rtk_rate_stormControlExtEnable_get + * Description: + * Get externsion storm control state + * Input: + * stormType - storm group type + * Output: + * pEnable - externsion storm control state + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +extern rtk_api_ret_t rtk_rate_stormControlExtEnable_get(rtk_rate_storm_group_t stormType, rtk_enable_t *pEnable); + +/* Function Name: + * rtk_rate_stormControlExtMeterIdx_set + * Description: + * Set externsion storm control meter index + * Input: + * stormType - storm group type + * index - externsion storm control state + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +extern rtk_api_ret_t rtk_rate_stormControlExtMeterIdx_set(rtk_rate_storm_group_t stormType, rtk_uint32 index); + +/* Function Name: + * rtk_rate_stormControlExtMeterIdx_get + * Description: + * Get externsion storm control meter index + * Input: + * stormType - storm group type + * pIndex - externsion storm control state + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +extern rtk_api_ret_t rtk_rate_stormControlExtMeterIdx_get(rtk_rate_storm_group_t stormType, rtk_uint32 *pIndex); + + + +#endif /* __RTK_API_STORM_H__ */ diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/svlan.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/svlan.c new file mode 100644 index 00000000..3784b2b0 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/svlan.c @@ -0,0 +1,1257 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8367C + * Feature : Here is a list of all functions and variables in SVLAN module. + * + */ + +#include +#include +#include +#include +#include + +#include + + +/* Function Name: + * rtk_svlan_init + * Description: + * Initialize SVLAN Configuration + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * Ether type of S-tag in 802.1ad is 0x88a8 and there are existed ether type 0x9100 and 0x9200 for Q-in-Q SLAN design. + * User can set mathced ether type as service provider supported protocol. + */ +rtk_api_ret_t rtk_svlan_init(void) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->svlan_init) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->svlan_init(); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_svlan_servicePort_add + * Description: + * Add one service port in the specified device + * Input: + * port - Port id. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API is setting which port is connected to provider switch. All frames receiving from this port must + * contain accept SVID in S-tag field. + */ +rtk_api_ret_t rtk_svlan_servicePort_add(rtk_port_t port) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->svlan_servicePort_add) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->svlan_servicePort_add(port); + RTK_API_UNLOCK(); + + return retVal; +} +/* Function Name: + * rtk_svlan_servicePort_get + * Description: + * Get service ports in the specified device. + * Input: + * None + * Output: + * pSvlan_portmask - pointer buffer of svlan ports. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API is setting which port is connected to provider switch. All frames receiving from this port must + * contain accept SVID in S-tag field. + */ +rtk_api_ret_t rtk_svlan_servicePort_get(rtk_portmask_t *pSvlan_portmask) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->svlan_servicePort_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->svlan_servicePort_get(pSvlan_portmask); + RTK_API_UNLOCK(); + + return retVal; +} +/* Function Name: + * rtk_svlan_servicePort_del + * Description: + * Delete one service port in the specified device + * Input: + * port - Port id. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API is removing SVLAN service port in the specified device. + */ +rtk_api_ret_t rtk_svlan_servicePort_del(rtk_port_t port) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->svlan_servicePort_del) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->svlan_servicePort_del(port); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_svlan_tpidEntry_set + * Description: + * Configure accepted S-VLAN ether type. + * Input: + * svlan_tag_id - Ether type of S-tag frame parsing in uplink ports. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * Note: + * Ether type of S-tag in 802.1ad is 0x88a8 and there are existed ether type 0x9100 and 0x9200 for Q-in-Q SLAN design. + * User can set mathced ether type as service provider supported protocol. + */ +rtk_api_ret_t rtk_svlan_tpidEntry_set(rtk_svlan_tpid_t svlan_tag_id) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->svlan_tpidEntry_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->svlan_tpidEntry_set(svlan_tag_id); + RTK_API_UNLOCK(); + + return retVal; +} +/* Function Name: + * rtk_svlan_tpidEntry_get + * Description: + * Get accepted S-VLAN ether type setting. + * Input: + * None + * Output: + * pSvlan_tag_id - Ether type of S-tag frame parsing in uplink ports. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API is setting which port is connected to provider switch. All frames receiving from this port must + * contain accept SVID in S-tag field. + */ +rtk_api_ret_t rtk_svlan_tpidEntry_get(rtk_svlan_tpid_t *pSvlan_tag_id) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->svlan_tpidEntry_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->svlan_tpidEntry_get(pSvlan_tag_id); + RTK_API_UNLOCK(); + + return retVal; +} +/* Function Name: + * rtk_svlan_priorityRef_set + * Description: + * Set S-VLAN upstream priority reference setting. + * Input: + * ref - reference selection parameter. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * Note: + * The API can set the upstream SVLAN tag priority reference source. The related priority + * sources are as following: + * - REF_INTERNAL_PRI, + * - REF_CTAG_PRI, + * - REF_SVLAN_PRI, + * - REF_PB_PRI. + */ +rtk_api_ret_t rtk_svlan_priorityRef_set(rtk_svlan_pri_ref_t ref) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->svlan_priorityRef_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->svlan_priorityRef_set(ref); + RTK_API_UNLOCK(); + + return retVal; +} +/* Function Name: + * rtk_svlan_priorityRef_get + * Description: + * Get S-VLAN upstream priority reference setting. + * Input: + * None + * Output: + * pRef - reference selection parameter. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can get the upstream SVLAN tag priority reference source. The related priority + * sources are as following: + * - REF_INTERNAL_PRI, + * - REF_CTAG_PRI, + * - REF_SVLAN_PRI, + * - REF_PB_PRI + */ +rtk_api_ret_t rtk_svlan_priorityRef_get(rtk_svlan_pri_ref_t *pRef) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->svlan_priorityRef_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->svlan_priorityRef_get(pRef); + RTK_API_UNLOCK(); + + return retVal; +} +/* Function Name: + * rtk_svlan_memberPortEntry_set + * Description: + * Configure system SVLAN member content + * Input: + * svid - SVLAN id + * psvlan_cfg - SVLAN member configuration + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_PORT_MASK - Invalid portmask. + * RT_ERR_SVLAN_TABLE_FULL - SVLAN configuration is full. + * Note: + * The API can set system 64 accepted s-tag frame format. Only 64 SVID S-tag frame will be accpeted + * to receiving from uplink ports. Other SVID S-tag frame or S-untagged frame will be droped by default setup. + * - rtk_svlan_memberCfg_t->svid is SVID of SVLAN member configuration. + * - rtk_svlan_memberCfg_t->memberport is member port mask of SVLAN member configuration. + * - rtk_svlan_memberCfg_t->fid is filtering database of SVLAN member configuration. + * - rtk_svlan_memberCfg_t->priority is priority of SVLAN member configuration. + */ +rtk_api_ret_t rtk_svlan_memberPortEntry_set(rtk_vlan_t svid, rtk_svlan_memberCfg_t *pSvlan_cfg) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->svlan_memberPortEntry_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->svlan_memberPortEntry_set(svid, pSvlan_cfg); + RTK_API_UNLOCK(); + + return retVal; +} +/* Function Name: + * rtk_svlan_memberPortEntry_get + * Description: + * Get SVLAN member Configure. + * Input: + * svid - SVLAN id + * Output: + * pSvlan_cfg - SVLAN member configuration + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get system 64 accepted s-tag frame format. Only 64 SVID S-tag frame will be accpeted + * to receiving from uplink ports. Other SVID S-tag frame or S-untagged frame will be droped. + */ +rtk_api_ret_t rtk_svlan_memberPortEntry_get(rtk_vlan_t svid, rtk_svlan_memberCfg_t *pSvlan_cfg) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->svlan_memberPortEntry_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->svlan_memberPortEntry_get(svid, pSvlan_cfg); + RTK_API_UNLOCK(); + + return retVal; +} +/* Function Name: + * rtk_svlan_memberPortEntry_adv_set + * Description: + * Configure system SVLAN member by index + * Input: + * idx - Index (0 ~ 63) + * psvlan_cfg - SVLAN member configuration + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_PORT_MASK - Invalid portmask. + * RT_ERR_SVLAN_TABLE_FULL - SVLAN configuration is full. + * Note: + * The API can set system 64 accepted s-tag frame format by index. + * - rtk_svlan_memberCfg_t->svid is SVID of SVLAN member configuration. + * - rtk_svlan_memberCfg_t->memberport is member port mask of SVLAN member configuration. + * - rtk_svlan_memberCfg_t->fid is filtering database of SVLAN member configuration. + * - rtk_svlan_memberCfg_t->priority is priority of SVLAN member configuration. + */ +rtk_api_ret_t rtk_svlan_memberPortEntry_adv_set(rtk_uint32 idx, rtk_svlan_memberCfg_t *pSvlan_cfg) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->svlan_memberPortEntry_adv_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->svlan_memberPortEntry_adv_set(idx, pSvlan_cfg); + RTK_API_UNLOCK(); + + return retVal; +} +/* Function Name: + * rtk_svlan_memberPortEntry_adv_get + * Description: + * Get SVLAN member Configure by index. + * Input: + * idx - Index (0 ~ 63) + * Output: + * pSvlan_cfg - SVLAN member configuration + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get system 64 accepted s-tag frame format. Only 64 SVID S-tag frame will be accpeted + * to receiving from uplink ports. Other SVID S-tag frame or S-untagged frame will be droped. + */ +rtk_api_ret_t rtk_svlan_memberPortEntry_adv_get(rtk_uint32 idx, rtk_svlan_memberCfg_t *pSvlan_cfg) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->svlan_memberPortEntry_adv_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->svlan_memberPortEntry_adv_get(idx, pSvlan_cfg); + RTK_API_UNLOCK(); + + return retVal; +} +/* Function Name: + * rtk_svlan_defaultSvlan_set + * Description: + * Configure default egress SVLAN. + * Input: + * port - Source port + * svid - SVLAN id + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found. + * Note: + * The API can set port n S-tag format index while receiving frame from port n + * is transmit through uplink port with s-tag field + */ +rtk_api_ret_t rtk_svlan_defaultSvlan_set(rtk_port_t port, rtk_vlan_t svid) +{ + + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->svlan_defaultSvlan_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->svlan_defaultSvlan_set(port, svid); + RTK_API_UNLOCK(); + + return retVal; +} +/* Function Name: + * rtk_svlan_defaultSvlan_get + * Description: + * Get the configure default egress SVLAN. + * Input: + * port - Source port + * Output: + * pSvid - SVLAN VID + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get port n S-tag format index while receiving frame from port n + * is transmit through uplink port with s-tag field + */ +rtk_api_ret_t rtk_svlan_defaultSvlan_get(rtk_port_t port, rtk_vlan_t *pSvid) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->svlan_defaultSvlan_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->svlan_defaultSvlan_get(port, pSvid); + RTK_API_UNLOCK(); + + return retVal; +} +/* Function Name: + * rtk_svlan_c2s_add + * Description: + * Configure SVLAN C2S table + * Input: + * vid - VLAN ID + * src_port - Ingress Port + * svid - SVLAN VID + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port ID. + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can set system C2S configuration. ASIC will check upstream's VID and assign related + * SVID to mathed packet. There are 128 SVLAN C2S configurations. + */ +rtk_api_ret_t rtk_svlan_c2s_add(rtk_vlan_t vid, rtk_port_t src_port, rtk_vlan_t svid) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->svlan_c2s_add) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->svlan_c2s_add(vid, src_port, svid); + RTK_API_UNLOCK(); + + return retVal; +} +/* Function Name: + * rtk_svlan_c2s_del + * Description: + * Delete one C2S entry + * Input: + * vid - VLAN ID + * src_port - Ingress Port + * svid - SVLAN VID + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_VLAN_VID - Invalid VID parameter. + * RT_ERR_PORT_ID - Invalid port ID. + * RT_ERR_OUT_OF_RANGE - input out of range. + * Note: + * The API can delete system C2S configuration. There are 128 SVLAN C2S configurations. + */ +rtk_api_ret_t rtk_svlan_c2s_del(rtk_vlan_t vid, rtk_port_t src_port) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->svlan_c2s_del) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->svlan_c2s_del(vid, src_port); + RTK_API_UNLOCK(); + + return retVal; +} +/* Function Name: + * rtk_svlan_c2s_get + * Description: + * Get configure SVLAN C2S table + * Input: + * vid - VLAN ID + * src_port - Ingress Port + * Output: + * pSvid - SVLAN ID + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port ID. + * RT_ERR_OUT_OF_RANGE - input out of range. + * Note: + * The API can get system C2S configuration. There are 128 SVLAN C2S configurations. + */ +rtk_api_ret_t rtk_svlan_c2s_get(rtk_vlan_t vid, rtk_port_t src_port, rtk_vlan_t *pSvid) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->svlan_c2s_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->svlan_c2s_get(vid, src_port, pSvid); + RTK_API_UNLOCK(); + + return retVal; +} +/* Function Name: + * rtk_svlan_untag_action_set + * Description: + * Configure Action of downstream UnStag packet + * Input: + * action - Action for UnStag + * svid - The SVID assigned to UnStag packet + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found. + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can configure action of downstream Un-Stag packet. A SVID assigned + * to the un-stag is also supported by this API. The parameter of svid is + * only referenced when the action is set to UNTAG_ASSIGN + */ +rtk_api_ret_t rtk_svlan_untag_action_set(rtk_svlan_untag_action_t action, rtk_vlan_t svid) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->svlan_untag_action_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->svlan_untag_action_set(action, svid); + RTK_API_UNLOCK(); + + return retVal; +} +/* Function Name: + * rtk_svlan_untag_action_get + * Description: + * Get Action of downstream UnStag packet + * Input: + * None + * Output: + * pAction - Action for UnStag + * pSvid - The SVID assigned to UnStag packet + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found. + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can Get action of downstream Un-Stag packet. A SVID assigned + * to the un-stag is also retrieved by this API. The parameter pSvid is + * only refernced when the action is UNTAG_ASSIGN + */ +rtk_api_ret_t rtk_svlan_untag_action_get(rtk_svlan_untag_action_t *pAction, rtk_vlan_t *pSvid) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->svlan_untag_action_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->svlan_untag_action_get(pAction, pSvid); + RTK_API_UNLOCK(); + + return retVal; +} +/* Function Name: + * rtk_svlan_unmatch_action_set + * Description: + * Configure Action of downstream Unmatch packet + * Input: + * action - Action for Unmatch + * svid - The SVID assigned to Unmatch packet + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found. + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can configure action of downstream Un-match packet. A SVID assigned + * to the un-match is also supported by this API. The parameter od svid is + * only refernced when the action is set to UNMATCH_ASSIGN + */ +rtk_api_ret_t rtk_svlan_unmatch_action_set(rtk_svlan_unmatch_action_t action, rtk_vlan_t svid) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->svlan_unmatch_action_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->svlan_unmatch_action_set(action, svid); + RTK_API_UNLOCK(); + + return retVal; +} +/* Function Name: + * rtk_svlan_unmatch_action_get + * Description: + * Get Action of downstream Unmatch packet + * Input: + * None + * Output: + * pAction - Action for Unmatch + * pSvid - The SVID assigned to Unmatch packet + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found. + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can Get action of downstream Un-match packet. A SVID assigned + * to the un-match is also retrieved by this API. The parameter pSvid is + * only refernced when the action is UNMATCH_ASSIGN + */ +rtk_api_ret_t rtk_svlan_unmatch_action_get(rtk_svlan_unmatch_action_t *pAction, rtk_vlan_t *pSvid) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->svlan_unmatch_action_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->svlan_unmatch_action_get(pAction, pSvid); + RTK_API_UNLOCK(); + + return retVal; +} +/* Function Name: + * rtk_svlan_unassign_action_set + * Description: + * Configure Action of upstream without svid assign action + * Input: + * action - Action for Un-assign + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can configure action of upstream Un-assign svid packet. If action is not + * trap to CPU, the port-based SVID sure be assign as system need + */ +rtk_api_ret_t rtk_svlan_unassign_action_set(rtk_svlan_unassign_action_t action) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->svlan_unassign_action_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->svlan_unassign_action_set(action); + RTK_API_UNLOCK(); + + return retVal; +} +/* Function Name: + * rtk_svlan_unassign_action_get + * Description: + * Get action of upstream without svid assignment + * Input: + * None + * Output: + * pAction - Action for Un-assign + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * Note: + * None + */ +rtk_api_ret_t rtk_svlan_unassign_action_get(rtk_svlan_unassign_action_t *pAction) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->svlan_unassign_action_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->svlan_unassign_action_get(pAction); + RTK_API_UNLOCK(); + + return retVal; +} +/* Function Name: + * rtk_svlan_dmac_vidsel_set + * Description: + * Set DMAC CVID selection + * Input: + * port - Port + * enable - state of DMAC CVID Selection + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found. + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can set DMAC CVID Selection state + */ +rtk_api_ret_t rtk_svlan_dmac_vidsel_set(rtk_port_t port, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->svlan_dmac_vidsel_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->svlan_dmac_vidsel_set(port, enable); + RTK_API_UNLOCK(); + + return retVal; +} +/* Function Name: + * rtk_svlan_dmac_vidsel_get + * Description: + * Get DMAC CVID selection + * Input: + * port - Port + * Output: + * pEnable - state of DMAC CVID Selection + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found. + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can get DMAC CVID Selection state + */ +rtk_api_ret_t rtk_svlan_dmac_vidsel_get(rtk_port_t port, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->svlan_dmac_vidsel_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->svlan_dmac_vidsel_get(port, pEnable); + RTK_API_UNLOCK(); + + return retVal; +} +/* Function Name: + * rtk_svlan_ipmc2s_add + * Description: + * add ip multicast address to SVLAN + * Input: + * svid - SVLAN VID + * ipmc - ip multicast address + * ipmcMsk - ip multicast mask + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found. + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can set IP mutlicast to SVID configuration. If upstream packet is IPv4 multicast + * packet and DIP is matched MC2S configuration, ASIC will assign egress SVID to the packet. + * There are 32 SVLAN multicast configurations for IP and L2 multicast. + */ +rtk_api_ret_t rtk_svlan_ipmc2s_add(ipaddr_t ipmc, ipaddr_t ipmcMsk,rtk_vlan_t svid) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->svlan_ipmc2s_add) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->svlan_ipmc2s_add(ipmc, ipmcMsk, svid); + RTK_API_UNLOCK(); + + return retVal; +} +/* Function Name: + * rtk_svlan_ipmc2s_del + * Description: + * delete ip multicast address to SVLAN + * Input: + * ipmc - ip multicast address + * ipmcMsk - ip multicast mask + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_OUT_OF_RANGE - input out of range. + * Note: + * The API can delete IP mutlicast to SVID configuration. There are 32 SVLAN multicast configurations for IP and L2 multicast. + */ +rtk_api_ret_t rtk_svlan_ipmc2s_del(ipaddr_t ipmc, ipaddr_t ipmcMsk) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->svlan_ipmc2s_del) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->svlan_ipmc2s_del(ipmc, ipmcMsk); + RTK_API_UNLOCK(); + + return retVal; +} +/* Function Name: + * rtk_svlan_ipmc2s_get + * Description: + * Get ip multicast address to SVLAN + * Input: + * ipmc - ip multicast address + * ipmcMsk - ip multicast mask + * Output: + * pSvid - SVLAN VID + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_OUT_OF_RANGE - input out of range. + * Note: + * The API can get IP mutlicast to SVID configuration. There are 32 SVLAN multicast configurations for IP and L2 multicast. + */ +rtk_api_ret_t rtk_svlan_ipmc2s_get(ipaddr_t ipmc, ipaddr_t ipmcMsk, rtk_vlan_t *pSvid) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->svlan_ipmc2s_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->svlan_ipmc2s_get(ipmc, ipmcMsk, pSvid); + RTK_API_UNLOCK(); + + return retVal; +} +/* Function Name: + * rtk_svlan_l2mc2s_add + * Description: + * Add L2 multicast address to SVLAN + * Input: + * mac - L2 multicast address + * macMsk - L2 multicast address mask + * svid - SVLAN VID + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found. + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can set L2 Mutlicast to SVID configuration. If upstream packet is L2 multicast + * packet and DMAC is matched, ASIC will assign egress SVID to the packet. There are 32 + * SVLAN multicast configurations for IP and L2 multicast. + */ +rtk_api_ret_t rtk_svlan_l2mc2s_add(rtk_mac_t mac, rtk_mac_t macMsk, rtk_vlan_t svid) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->svlan_l2mc2s_add) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->svlan_l2mc2s_add(mac, macMsk, svid); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_svlan_l2mc2s_del + * Description: + * delete L2 multicast address to SVLAN + * Input: + * mac - L2 multicast address + * macMsk - L2 multicast address mask + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_OUT_OF_RANGE - input out of range. + * Note: + * The API can delete Mutlicast to SVID configuration. There are 32 SVLAN multicast configurations for IP and L2 multicast. + */ +rtk_api_ret_t rtk_svlan_l2mc2s_del(rtk_mac_t mac, rtk_mac_t macMsk) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->svlan_l2mc2s_del) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->svlan_l2mc2s_del(mac, macMsk); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_svlan_l2mc2s_get + * Description: + * Get L2 multicast address to SVLAN + * Input: + * mac - L2 multicast address + * macMsk - L2 multicast address mask + * Output: + * pSvid - SVLAN VID + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_OUT_OF_RANGE - input out of range. + * Note: + * The API can get L2 mutlicast to SVID configuration. There are 32 SVLAN multicast configurations for IP and L2 multicast. + */ +rtk_api_ret_t rtk_svlan_l2mc2s_get(rtk_mac_t mac, rtk_mac_t macMsk, rtk_vlan_t *pSvid) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->svlan_l2mc2s_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->svlan_l2mc2s_get(mac, macMsk, pSvid); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_svlan_sp2c_add + * Description: + * Add system SP2C configuration + * Input: + * cvid - VLAN ID + * dst_port - Destination port of SVLAN to CVLAN configuration + * svid - SVLAN VID + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can add SVID & Destination Port to CVLAN configuration. The downstream frames with assigned + * SVID will be add C-tag with assigned CVID if the output port is the assigned destination port. + * There are 128 SP2C configurations. + */ +rtk_api_ret_t rtk_svlan_sp2c_add(rtk_vlan_t svid, rtk_port_t dst_port, rtk_vlan_t cvid) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->svlan_sp2c_add) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->svlan_sp2c_add(svid, dst_port, cvid); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_svlan_sp2c_get + * Description: + * Get configure system SP2C content + * Input: + * svid - SVLAN VID + * dst_port - Destination port of SVLAN to CVLAN configuration + * Output: + * pCvid - VLAN ID + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * Note: + * The API can get SVID & Destination Port to CVLAN configuration. There are 128 SP2C configurations. + */ +rtk_api_ret_t rtk_svlan_sp2c_get(rtk_vlan_t svid, rtk_port_t dst_port, rtk_vlan_t *pCvid) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->svlan_sp2c_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->svlan_sp2c_get(svid, dst_port, pCvid); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_svlan_sp2c_del + * Description: + * Delete system SP2C configuration + * Input: + * svid - SVLAN VID + * dst_port - Destination port of SVLAN to CVLAN configuration + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_OUT_OF_RANGE - input out of range. + * Note: + * The API can delete SVID & Destination Port to CVLAN configuration. There are 128 SP2C configurations. + */ +rtk_api_ret_t rtk_svlan_sp2c_del(rtk_vlan_t svid, rtk_port_t dst_port) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->svlan_sp2c_del) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->svlan_sp2c_del(svid, dst_port); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_svlan_lookupType_set + * Description: + * Set lookup type of SVLAN + * Input: + * type - lookup type + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * Note: + * none + */ +rtk_api_ret_t rtk_svlan_lookupType_set(rtk_svlan_lookupType_t type) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->svlan_lookupType_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->svlan_lookupType_set(type); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_svlan_lookupType_get + * Description: + * Get lookup type of SVLAN + * Input: + * pType - lookup type + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * Note: + * none + */ +rtk_api_ret_t rtk_svlan_lookupType_get(rtk_svlan_lookupType_t *pType) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->svlan_lookupType_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->svlan_lookupType_get(pType); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_svlan_trapPri_set + * Description: + * Set svlan trap priority + * Input: + * priority - priority for trap packets + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_QOS_INT_PRIORITY + * Note: + * None + */ +rtk_api_ret_t rtk_svlan_trapPri_set(rtk_pri_t priority) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->svlan_trapPri_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->svlan_trapPri_set(priority); + RTK_API_UNLOCK(); + + return retVal; +} /* end of rtk_svlan_trapPri_set */ + +/* Function Name: + * rtk_svlan_trapPri_get + * Description: + * Get svlan trap priority + * Input: + * None + * Output: + * pPriority - priority for trap packets + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None + */ +rtk_api_ret_t rtk_svlan_trapPri_get(rtk_pri_t *pPriority) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->svlan_trapPri_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->svlan_trapPri_get(pPriority); + RTK_API_UNLOCK(); + + return retVal; +} /* end of rtk_svlan_trapPri_get */ + + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/svlan.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/svlan.h new file mode 100644 index 00000000..773055ec --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/svlan.h @@ -0,0 +1,879 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8367/RTL8367C switch high-level API + * + * Feature : The file includes SVLAN module high-layer API defination + * + */ + +#ifndef __RTK_API_SVLAN_H__ +#define __RTK_API_SVLAN_H__ + +typedef rtk_uint32 rtk_svlan_index_t; + +typedef struct rtk_svlan_memberCfg_s{ + rtk_uint32 svid; + rtk_portmask_t memberport; + rtk_portmask_t untagport; + rtk_uint32 fiden; + rtk_uint32 fid; + rtk_uint32 priority; + rtk_uint32 efiden; + rtk_uint32 efid; + rtk_uint32 chk_ivl_svl; + rtk_uint32 ivl_svl; +}rtk_svlan_memberCfg_t; + +typedef enum rtk_svlan_pri_ref_e +{ + REF_INTERNAL_PRI = 0, + REF_CTAG_PRI, + REF_SVLAN_PRI, + REF_PB_PRI, + REF_PRI_END +} rtk_svlan_pri_ref_t; + + +typedef rtk_uint32 rtk_svlan_tpid_t; + +typedef enum rtk_svlan_untag_action_e +{ + UNTAG_DROP = 0, + UNTAG_TRAP, + UNTAG_ASSIGN, + UNTAG_END +} rtk_svlan_untag_action_t; + +typedef enum rtk_svlan_unmatch_action_e +{ + UNMATCH_DROP = 0, + UNMATCH_TRAP, + UNMATCH_ASSIGN, + UNMATCH_END +} rtk_svlan_unmatch_action_t; + +typedef enum rtk_svlan_unassign_action_e +{ + UNASSIGN_PBSVID = 0, + UNASSIGN_TRAP, + UNASSIGN_END +} rtk_svlan_unassign_action_t; + + +typedef enum rtk_svlan_lookupType_e +{ + SVLAN_LOOKUP_S64MBRCGF = 0, + SVLAN_LOOKUP_C4KVLAN, + SVLAN_LOOKUP_END, + +} rtk_svlan_lookupType_t; + +/* Function Name: + * rtk_svlan_init + * Description: + * Initialize SVLAN Configuration + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * Ether type of S-tag in 802.1ad is 0x88a8 and there are existed ether type 0x9100 and 0x9200 for Q-in-Q SLAN design. + * User can set mathced ether type as service provider supported protocol. + */ +extern rtk_api_ret_t rtk_svlan_init(void); + +/* Function Name: + * rtk_svlan_servicePort_add + * Description: + * Add one service port in the specified device + * Input: + * port - Port id. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API is setting which port is connected to provider switch. All frames receiving from this port must + * contain accept SVID in S-tag field. + */ +extern rtk_api_ret_t rtk_svlan_servicePort_add(rtk_port_t port); + +/* Function Name: + * rtk_svlan_servicePort_get + * Description: + * Get service ports in the specified device. + * Input: + * None + * Output: + * pSvlan_portmask - pointer buffer of svlan ports. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API is setting which port is connected to provider switch. All frames receiving from this port must + * contain accept SVID in S-tag field. + */ +extern rtk_api_ret_t rtk_svlan_servicePort_get(rtk_portmask_t *pSvlan_portmask); + +/* Function Name: + * rtk_svlan_servicePort_del + * Description: + * Delete one service port in the specified device + * Input: + * port - Port id. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API is removing SVLAN service port in the specified device. + */ +extern rtk_api_ret_t rtk_svlan_servicePort_del(rtk_port_t port); + +/* Function Name: + * rtk_svlan_tpidEntry_set + * Description: + * Configure accepted S-VLAN ether type. + * Input: + * svlan_tag_id - Ether type of S-tag frame parsing in uplink ports. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * Note: + * Ether type of S-tag in 802.1ad is 0x88a8 and there are existed ether type 0x9100 and 0x9200 for Q-in-Q SLAN design. + * User can set mathced ether type as service provider supported protocol. + */ +extern rtk_api_ret_t rtk_svlan_tpidEntry_set(rtk_uint32 svlan_tag_id); + +/* Function Name: + * rtk_svlan_tpidEntry_get + * Description: + * Get accepted S-VLAN ether type setting. + * Input: + * None + * Output: + * pSvlan_tag_id - Ether type of S-tag frame parsing in uplink ports. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API is setting which port is connected to provider switch. All frames receiving from this port must + * contain accept SVID in S-tag field. + */ +extern rtk_api_ret_t rtk_svlan_tpidEntry_get(rtk_uint32 *pSvlan_tag_id); + +/* Function Name: + * rtk_svlan_priorityRef_set + * Description: + * Set S-VLAN upstream priority reference setting. + * Input: + * ref - reference selection parameter. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * Note: + * The API can set the upstream SVLAN tag priority reference source. The related priority + * sources are as following: + * - REF_INTERNAL_PRI, + * - REF_CTAG_PRI, + * - REF_SVLAN_PRI, + * - REF_PB_PRI. + */ +extern rtk_api_ret_t rtk_svlan_priorityRef_set(rtk_svlan_pri_ref_t ref); + +/* Function Name: + * rtk_svlan_priorityRef_get + * Description: + * Get S-VLAN upstream priority reference setting. + * Input: + * None + * Output: + * pRef - reference selection parameter. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can get the upstream SVLAN tag priority reference source. The related priority + * sources are as following: + * - REF_INTERNAL_PRI, + * - REF_CTAG_PRI, + * - REF_SVLAN_PRI, + * - REF_PB_PRI + */ +extern rtk_api_ret_t rtk_svlan_priorityRef_get(rtk_svlan_pri_ref_t *pRef); + +/* Function Name: + * rtk_svlan_memberPortEntry_set + * Description: + * Configure system SVLAN member content + * Input: + * svid - SVLAN id + * psvlan_cfg - SVLAN member configuration + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_PORT_MASK - Invalid portmask. + * RT_ERR_SVLAN_TABLE_FULL - SVLAN configuration is full. + * Note: + * The API can set system 64 accepted s-tag frame format. Only 64 SVID S-tag frame will be accpeted + * to receiving from uplink ports. Other SVID S-tag frame or S-untagged frame will be droped by default setup. + * - rtk_svlan_memberCfg_t->svid is SVID of SVLAN member configuration. + * - rtk_svlan_memberCfg_t->memberport is member port mask of SVLAN member configuration. + * - rtk_svlan_memberCfg_t->fid is filtering database of SVLAN member configuration. + * - rtk_svlan_memberCfg_t->priority is priority of SVLAN member configuration. + */ +extern rtk_api_ret_t rtk_svlan_memberPortEntry_set(rtk_uint32 svid_idx, rtk_svlan_memberCfg_t *psvlan_cfg); + +/* Function Name: + * rtk_svlan_memberPortEntry_get + * Description: + * Get SVLAN member Configure. + * Input: + * svid - SVLAN id + * Output: + * pSvlan_cfg - SVLAN member configuration + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get system 64 accepted s-tag frame format. Only 64 SVID S-tag frame will be accpeted + * to receiving from uplink ports. Other SVID S-tag frame or S-untagged frame will be droped. + */ +extern rtk_api_ret_t rtk_svlan_memberPortEntry_get(rtk_uint32 svid_idx, rtk_svlan_memberCfg_t *pSvlan_cfg); + +/* Function Name: + * rtk_svlan_memberPortEntry_adv_set + * Description: + * Configure system SVLAN member by index + * Input: + * idx - Index (0 ~ 63) + * psvlan_cfg - SVLAN member configuration + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_PORT_MASK - Invalid portmask. + * RT_ERR_SVLAN_TABLE_FULL - SVLAN configuration is full. + * Note: + * The API can set system 64 accepted s-tag frame format by index. + * - rtk_svlan_memberCfg_t->svid is SVID of SVLAN member configuration. + * - rtk_svlan_memberCfg_t->memberport is member port mask of SVLAN member configuration. + * - rtk_svlan_memberCfg_t->fid is filtering database of SVLAN member configuration. + * - rtk_svlan_memberCfg_t->priority is priority of SVLAN member configuration. + */ +extern rtk_api_ret_t rtk_svlan_memberPortEntry_adv_set(rtk_uint32 idx, rtk_svlan_memberCfg_t *pSvlan_cfg); + +/* Function Name: + * rtk_svlan_memberPortEntry_adv_get + * Description: + * Get SVLAN member Configure by index. + * Input: + * idx - Index (0 ~ 63) + * Output: + * pSvlan_cfg - SVLAN member configuration + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get system 64 accepted s-tag frame format. Only 64 SVID S-tag frame will be accpeted + * to receiving from uplink ports. Other SVID S-tag frame or S-untagged frame will be droped. + */ +extern rtk_api_ret_t rtk_svlan_memberPortEntry_adv_get(rtk_uint32 idx, rtk_svlan_memberCfg_t *pSvlan_cfg); + +/* Function Name: + * rtk_svlan_defaultSvlan_set + * Description: + * Configure default egress SVLAN. + * Input: + * port - Source port + * svid - SVLAN id + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found. + * Note: + * The API can set port n S-tag format index while receiving frame from port n + * is transmit through uplink port with s-tag field + */ +extern rtk_api_ret_t rtk_svlan_defaultSvlan_set(rtk_port_t port, rtk_vlan_t svid); + +/* Function Name: + * rtk_svlan_defaultSvlan_get + * Description: + * Get the configure default egress SVLAN. + * Input: + * port - Source port + * Output: + * pSvid - SVLAN VID + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get port n S-tag format index while receiving frame from port n + * is transmit through uplink port with s-tag field + */ +extern rtk_api_ret_t rtk_svlan_defaultSvlan_get(rtk_port_t port, rtk_vlan_t *pSvid); + +/* Function Name: + * rtk_svlan_c2s_add + * Description: + * Configure SVLAN C2S table + * Input: + * vid - VLAN ID + * src_port - Ingress Port + * svid - SVLAN VID + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port ID. + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can set system C2S configuration. ASIC will check upstream's VID and assign related + * SVID to mathed packet. There are 128 SVLAN C2S configurations. + */ +extern rtk_api_ret_t rtk_svlan_c2s_add(rtk_vlan_t vid, rtk_port_t src_port, rtk_vlan_t svid); + +/* Function Name: + * rtk_svlan_c2s_del + * Description: + * Delete one C2S entry + * Input: + * vid - VLAN ID + * src_port - Ingress Port + * svid - SVLAN VID + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_VLAN_VID - Invalid VID parameter. + * RT_ERR_PORT_ID - Invalid port ID. + * RT_ERR_OUT_OF_RANGE - input out of range. + * Note: + * The API can delete system C2S configuration. There are 128 SVLAN C2S configurations. + */ +extern rtk_api_ret_t rtk_svlan_c2s_del(rtk_vlan_t vid, rtk_port_t src_port); + +/* Function Name: + * rtk_svlan_c2s_get + * Description: + * Get configure SVLAN C2S table + * Input: + * vid - VLAN ID + * src_port - Ingress Port + * Output: + * pSvid - SVLAN ID + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port ID. + * RT_ERR_OUT_OF_RANGE - input out of range. + * Note: + * The API can get system C2S configuration. There are 128 SVLAN C2S configurations. + */ +extern rtk_api_ret_t rtk_svlan_c2s_get(rtk_vlan_t vid, rtk_port_t src_port, rtk_vlan_t *pSvid); + +/* Function Name: + * rtk_svlan_untag_action_set + * Description: + * Configure Action of downstream Un-Stag packet + * Input: + * action - Action for UnStag + * svid - The SVID assigned to UnStag packet + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found. + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can configure action of downstream Un-Stag packet. A SVID assigned + * to the un-stag is also supported by this API. The parameter of svid is + * only referenced when the action is set to UNTAG_ASSIGN + */ +extern rtk_api_ret_t rtk_svlan_untag_action_set(rtk_svlan_untag_action_t action, rtk_vlan_t svid); + +/* Function Name: + * rtk_svlan_untag_action_get + * Description: + * Get Action of downstream Un-Stag packet + * Input: + * None + * Output: + * pAction - Action for UnStag + * pSvid - The SVID assigned to UnStag packet + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found. + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can Get action of downstream Un-Stag packet. A SVID assigned + * to the un-stag is also retrieved by this API. The parameter pSvid is + * only refernced when the action is UNTAG_ASSIGN + */ +extern rtk_api_ret_t rtk_svlan_untag_action_get(rtk_svlan_untag_action_t *pAction, rtk_vlan_t *pSvid); + +/* Function Name: + * rtk_svlan_unmatch_action_set + * Description: + * Configure Action of downstream Unmatch packet + * Input: + * action - Action for Unmatch + * svid - The SVID assigned to Unmatch packet + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found. + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can configure action of downstream Un-match packet. A SVID assigned + * to the un-match is also supported by this API. The parameter od svid is + * only refernced when the action is set to UNMATCH_ASSIGN + */ +extern rtk_api_ret_t rtk_svlan_unmatch_action_set(rtk_svlan_unmatch_action_t action, rtk_vlan_t svid); + +/* Function Name: + * rtk_svlan_unmatch_action_get + * Description: + * Get Action of downstream Unmatch packet + * Input: + * None + * Output: + * pAction - Action for Unmatch + * pSvid - The SVID assigned to Unmatch packet + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found. + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can Get action of downstream Un-match packet. A SVID assigned + * to the un-match is also retrieved by this API. The parameter pSvid is + * only refernced when the action is UNMATCH_ASSIGN + */ +extern rtk_api_ret_t rtk_svlan_unmatch_action_get(rtk_svlan_unmatch_action_t *pAction, rtk_vlan_t *pSvid); + +/* Function Name: + * rtk_svlan_dmac_vidsel_set + * Description: + * Set DMAC CVID selection + * Input: + * port - Port + * enable - state of DMAC CVID Selection + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found. + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can set DMAC CVID Selection state + */ +extern rtk_api_ret_t rtk_svlan_dmac_vidsel_set(rtk_port_t port, rtk_enable_t enable); + +/* Function Name: + * rtk_svlan_dmac_vidsel_get + * Description: + * Get DMAC CVID selection + * Input: + * port - Port + * Output: + * pEnable - state of DMAC CVID Selection + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found. + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can get DMAC CVID Selection state + */ +extern rtk_api_ret_t rtk_svlan_dmac_vidsel_get(rtk_port_t port, rtk_enable_t *pEnable); + +/* Function Name: + * rtk_svlan_ipmc2s_add + * Description: + * add ip multicast address to SVLAN + * Input: + * svid - SVLAN VID + * ipmc - ip multicast address + * ipmcMsk - ip multicast mask + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found. + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can set IP mutlicast to SVID configuration. If upstream packet is IPv4 multicast + * packet and DIP is matched MC2S configuration, ASIC will assign egress SVID to the packet. + * There are 32 SVLAN multicast configurations for IP and L2 multicast. + */ +extern rtk_api_ret_t rtk_svlan_ipmc2s_add(ipaddr_t ipmc, ipaddr_t ipmcMsk, rtk_vlan_t svid); + +/* Function Name: + * rtk_svlan_ipmc2s_del + * Description: + * delete ip multicast address to SVLAN + * Input: + * ipmc - ip multicast address + * ipmcMsk - ip multicast mask + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_OUT_OF_RANGE - input out of range. + * Note: + * The API can delete IP mutlicast to SVID configuration. There are 32 SVLAN multicast configurations for IP and L2 multicast. + */ +extern rtk_api_ret_t rtk_svlan_ipmc2s_del(ipaddr_t ipmc, ipaddr_t ipmcMsk); + +/* Function Name: + * rtk_svlan_ipmc2s_get + * Description: + * Get ip multicast address to SVLAN + * Input: + * ipmc - ip multicast address + * ipmcMsk - ip multicast mask + * Output: + * pSvid - SVLAN VID + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_OUT_OF_RANGE - input out of range. + * Note: + * The API can get IP mutlicast to SVID configuration. There are 32 SVLAN multicast configurations for IP and L2 multicast. + */ +extern rtk_api_ret_t rtk_svlan_ipmc2s_get(ipaddr_t ipmc, ipaddr_t ipmcMsk, rtk_vlan_t *pSvid); + +/* Function Name: + * rtk_svlan_l2mc2s_add + * Description: + * Add L2 multicast address to SVLAN + * Input: + * mac - L2 multicast address + * macMsk - L2 multicast address mask + * svid - SVLAN VID + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found. + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can set L2 Mutlicast to SVID configuration. If upstream packet is L2 multicast + * packet and DMAC is matched, ASIC will assign egress SVID to the packet. There are 32 + * SVLAN multicast configurations for IP and L2 multicast. + */ +extern rtk_api_ret_t rtk_svlan_l2mc2s_add(rtk_mac_t mac, rtk_mac_t macMsk, rtk_vlan_t svid); + +/* Function Name: + * rtk_svlan_l2mc2s_del + * Description: + * delete L2 multicast address to SVLAN + * Input: + * mac - L2 multicast address + * macMsk - L2 multicast address mask + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_OUT_OF_RANGE - input out of range. + * Note: + * The API can delete Mutlicast to SVID configuration. There are 32 SVLAN multicast configurations for IP and L2 multicast. + */ +extern rtk_api_ret_t rtk_svlan_l2mc2s_del(rtk_mac_t mac, rtk_mac_t macMsk); + +/* Function Name: + * rtk_svlan_l2mc2s_get + * Description: + * Get L2 multicast address to SVLAN + * Input: + * mac - L2 multicast address + * macMsk - L2 multicast address mask + * Output: + * pSvid - SVLAN VID + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_OUT_OF_RANGE - input out of range. + * Note: + * The API can get L2 mutlicast to SVID configuration. There are 32 SVLAN multicast configurations for IP and L2 multicast. + */ +extern rtk_api_ret_t rtk_svlan_l2mc2s_get(rtk_mac_t mac, rtk_mac_t macMsk, rtk_vlan_t *pSvid); + +/* Function Name: + * rtk_svlan_sp2c_add + * Description: + * Add system SP2C configuration + * Input: + * cvid - VLAN ID + * dst_port - Destination port of SVLAN to CVLAN configuration + * svid - SVLAN VID + * + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can add SVID & Destination Port to CVLAN configuration. The downstream frames with assigned + * SVID will be add C-tag with assigned CVID if the output port is the assigned destination port. + * There are 128 SP2C configurations. + */ +extern rtk_api_ret_t rtk_svlan_sp2c_add(rtk_vlan_t svid, rtk_port_t dst_port, rtk_vlan_t cvid); + +/* Function Name: + * rtk_svlan_sp2c_get + * Description: + * Get configure system SP2C content + * Input: + * svid - SVLAN VID + * dst_port - Destination port of SVLAN to CVLAN configuration + * Output: + * pCvid - VLAN ID + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * Note: + * The API can get SVID & Destination Port to CVLAN configuration. There are 128 SP2C configurations. + */ +extern rtk_api_ret_t rtk_svlan_sp2c_get(rtk_vlan_t svid, rtk_port_t dst_port, rtk_vlan_t *pCvid); + +/* Function Name: + * rtk_svlan_sp2c_del + * Description: + * Delete system SP2C configuration + * Input: + * svid - SVLAN VID + * dst_port - Destination port of SVLAN to CVLAN configuration + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_OUT_OF_RANGE - input out of range. + * Note: + * The API can delete SVID & Destination Port to CVLAN configuration. There are 128 SP2C configurations. + */ +extern rtk_api_ret_t rtk_svlan_sp2c_del(rtk_vlan_t svid, rtk_port_t dst_port); + + +/* Function Name: + * rtk_svlan_lookupType_set + * Description: + * Set lookup type of SVLAN + * Input: + * type - lookup type + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * Note: + * none + */ +extern rtk_api_ret_t rtk_svlan_lookupType_set(rtk_svlan_lookupType_t type); + +/* Function Name: + * rtk_svlan_lookupType_get + * Description: + * Get lookup type of SVLAN + * Input: + * pType - lookup type + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * Note: + * none + */ +extern rtk_api_ret_t rtk_svlan_lookupType_get(rtk_svlan_lookupType_t *pType); + +/* Function Name: + * rtk_svlan_trapPri_set + * Description: + * Set svlan trap priority + * Input: + * priority - priority for trap packets + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_QOS_INT_PRIORITY + * Note: + * None + */ +extern rtk_api_ret_t rtk_svlan_trapPri_set(rtk_pri_t priority); + +/* Function Name: + * rtk_svlan_trapPri_get + * Description: + * Get svlan trap priority + * Input: + * None + * Output: + * pPriority - priority for trap packets + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None + */ +extern rtk_api_ret_t rtk_svlan_trapPri_get(rtk_pri_t *pPriority); + +/* Function Name: + * rtk_svlan_unassign_action_set + * Description: + * Configure Action of upstream without svid assign action + * Input: + * action - Action for Un-assign + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can configure action of upstream Un-assign svid packet. If action is not + * trap to CPU, the port-based SVID sure be assign as system need + */ +extern rtk_api_ret_t rtk_svlan_unassign_action_set(rtk_svlan_unassign_action_t action); + +/* Function Name: + * rtk_svlan_unassign_action_get + * Description: + * Get action of upstream without svid assignment + * Input: + * None + * Output: + * pAction - Action for Un-assign + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * Note: + * None + */ +extern rtk_api_ret_t rtk_svlan_unassign_action_get(rtk_svlan_unassign_action_t *pAction); + +#endif /* __RTK_API_SVLAN_H__ */ diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/trap.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/trap.c new file mode 100644 index 00000000..9740af20 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/trap.c @@ -0,0 +1,1008 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8367C + * Feature : Here is a list of all functions and variables in Trap module. + * + */ + +#include +#include +#include +#include + +#include + + +/* Function Name: + * rtk_trap_unknownUnicastPktAction_set + * Description: + * Set unknown unicast packet action configuration. + * Input: + * port - ingress port ID for unknown unicast packet + * ucast_action - Unknown unicast action. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid action. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can set unknown unicast packet action configuration. + * The unknown unicast action is as following: + * - UCAST_ACTION_FORWARD_PMASK + * - UCAST_ACTION_DROP + * - UCAST_ACTION_TRAP2CPU + * - UCAST_ACTION_FLOODING + */ +rtk_api_ret_t rtk_trap_unknownUnicastPktAction_set(rtk_port_t port, rtk_trap_ucast_action_t ucast_action) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->trap_unknownUnicastPktAction_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->trap_unknownUnicastPktAction_set(port, ucast_action); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_trap_unknownUnicastPktAction_get + * Description: + * Get unknown unicast packet action configuration. + * Input: + * port - ingress port ID for unknown unicast packet + * Output: + * pUcast_action - Unknown unicast action. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid action. + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * This API can get unknown unicast packet action configuration. + * The unknown unicast action is as following: + * - UCAST_ACTION_FORWARD_PMASK + * - UCAST_ACTION_DROP + * - UCAST_ACTION_TRAP2CPU + * - UCAST_ACTION_FLOODING + */ +rtk_api_ret_t rtk_trap_unknownUnicastPktAction_get(rtk_port_t port, rtk_trap_ucast_action_t *pUcast_action) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->trap_unknownUnicastPktAction_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->trap_unknownUnicastPktAction_get(port, pUcast_action); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_trap_unknownMacPktAction_set + * Description: + * Set unknown source MAC packet action configuration. + * Input: + * ucast_action - Unknown source MAC action. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid action. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can set unknown unicast packet action configuration. + * The unknown unicast action is as following: + * - UCAST_ACTION_FORWARD_PMASK + * - UCAST_ACTION_DROP + * - UCAST_ACTION_TRAP2CPU + */ +rtk_api_ret_t rtk_trap_unknownMacPktAction_set(rtk_trap_ucast_action_t ucast_action) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->trap_unknownMacPktAction_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->trap_unknownMacPktAction_set(ucast_action); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_trap_unknownMacPktAction_get + * Description: + * Get unknown source MAC packet action configuration. + * Input: + * None. + * Output: + * pUcast_action - Unknown source MAC action. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Null Pointer. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * + */ +rtk_api_ret_t rtk_trap_unknownMacPktAction_get(rtk_trap_ucast_action_t *pUcast_action) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->trap_unknownMacPktAction_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->trap_unknownMacPktAction_get(pUcast_action); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_trap_unmatchMacPktAction_set + * Description: + * Set unmatch source MAC packet action configuration. + * Input: + * ucast_action - Unmatch source MAC action. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid action. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can set unknown unicast packet action configuration. + * The unknown unicast action is as following: + * - UCAST_ACTION_FORWARD_PMASK + * - UCAST_ACTION_DROP + * - UCAST_ACTION_TRAP2CPU + */ +rtk_api_ret_t rtk_trap_unmatchMacPktAction_set(rtk_trap_ucast_action_t ucast_action) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->trap_unmatchMacPktAction_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->trap_unmatchMacPktAction_set(ucast_action); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_trap_unmatchMacPktAction_get + * Description: + * Get unmatch source MAC packet action configuration. + * Input: + * None. + * Output: + * pUcast_action - Unmatch source MAC action. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid action. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can set unknown unicast packet action configuration. + * The unknown unicast action is as following: + * - UCAST_ACTION_FORWARD_PMASK + * - UCAST_ACTION_DROP + * - UCAST_ACTION_TRAP2CPU + */ +rtk_api_ret_t rtk_trap_unmatchMacPktAction_get(rtk_trap_ucast_action_t *pUcast_action) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->trap_unmatchMacPktAction_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->trap_unmatchMacPktAction_get(pUcast_action); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_trap_unmatchMacMoving_set + * Description: + * Set unmatch source MAC packet moving state. + * Input: + * port - Port ID. + * enable - ENABLED: allow SA moving, DISABLE: don't allow SA moving. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid action. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + */ +rtk_api_ret_t rtk_trap_unmatchMacMoving_set(rtk_port_t port, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->trap_unmatchMacMoving_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->trap_unmatchMacMoving_set(port, enable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_trap_unmatchMacMoving_get + * Description: + * Set unmatch source MAC packet moving state. + * Input: + * port - Port ID. + * Output: + * pEnable - ENABLED: allow SA moving, DISABLE: don't allow SA moving. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid action. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + */ +rtk_api_ret_t rtk_trap_unmatchMacMoving_get(rtk_port_t port, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->trap_unmatchMacMoving_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->trap_unmatchMacMoving_get(port, pEnable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_trap_unknownMcastPktAction_set + * Description: + * Set behavior of unknown multicast + * Input: + * port - Port id. + * type - unknown multicast packet type. + * mcast_action - unknown multicast action. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_NOT_ALLOWED - Invalid action. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * When receives an unknown multicast packet, switch may trap, drop or flood this packet + * (1) The unknown multicast packet type is as following: + * - MCAST_L2 + * - MCAST_IPV4 + * - MCAST_IPV6 + * (2) The unknown multicast action is as following: + * - MCAST_ACTION_FORWARD + * - MCAST_ACTION_DROP + * - MCAST_ACTION_TRAP2CPU + */ +rtk_api_ret_t rtk_trap_unknownMcastPktAction_set(rtk_port_t port, rtk_mcast_type_t type, rtk_trap_mcast_action_t mcast_action) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->trap_unknownMcastPktAction_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->trap_unknownMcastPktAction_set(port, type, mcast_action); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_trap_unknownMcastPktAction_get + * Description: + * Get behavior of unknown multicast + * Input: + * type - unknown multicast packet type. + * Output: + * pMcast_action - unknown multicast action. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_NOT_ALLOWED - Invalid operation. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * When receives an unknown multicast packet, switch may trap, drop or flood this packet + * (1) The unknown multicast packet type is as following: + * - MCAST_L2 + * - MCAST_IPV4 + * - MCAST_IPV6 + * (2) The unknown multicast action is as following: + * - MCAST_ACTION_FORWARD + * - MCAST_ACTION_DROP + * - MCAST_ACTION_TRAP2CPU + */ +rtk_api_ret_t rtk_trap_unknownMcastPktAction_get(rtk_port_t port, rtk_mcast_type_t type, rtk_trap_mcast_action_t *pMcast_action) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->trap_unknownMcastPktAction_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->trap_unknownMcastPktAction_get(port, type, pMcast_action); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_trap_lldpEnable_set + * Description: + * Set LLDP enable. + * Input: + * enabled - LLDP enable, 0: follow RMA, 1: use LLDP action. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid action. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * - DMAC Assignment + * - 01:80:c2:00:00:0e ethertype = 0x88CC LLDP + * - 01:80:c2:00:00:03 ethertype = 0x88CC + * - 01:80:c2:00:00:00 ethertype = 0x88CC + + */ +rtk_api_ret_t rtk_trap_lldpEnable_set(rtk_enable_t enabled) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->trap_lldpEnable_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->trap_lldpEnable_set(enabled); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_trap_lldpEnable_get + * Description: + * Get LLDP status. + * Input: + * None + * Output: + * pEnabled - LLDP enable, 0: follow RMA, 1: use LLDP action. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * LLDP is as following definition. + * - DMAC Assignment + * - 01:80:c2:00:00:0e ethertype = 0x88CC LLDP + * - 01:80:c2:00:00:03 ethertype = 0x88CC + * - 01:80:c2:00:00:00 ethertype = 0x88CC + */ +rtk_api_ret_t rtk_trap_lldpEnable_get(rtk_enable_t *pEnabled) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->trap_lldpEnable_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->trap_lldpEnable_get(pEnabled); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_trap_reasonTrapToCpuPriority_set + * Description: + * Set priority value of a packet that trapped to CPU port according to specific reason. + * Input: + * type - reason that trap to CPU port. + * priority - internal priority that is going to be set for specific trap reason. + * Output: + * None. + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - Invalid input parameter + * Note: + * Currently the trap reason that supported are listed as follows: + * - TRAP_REASON_RMA + * - TRAP_REASON_OAM + * - TRAP_REASON_1XUNAUTH + * - TRAP_REASON_VLANSTACK + * - TRAP_REASON_UNKNOWNMC + * - TRAP_REASON_IGMPMLD + */ +rtk_api_ret_t rtk_trap_reasonTrapToCpuPriority_set(rtk_trap_reason_type_t type, rtk_pri_t priority) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->trap_reasonTrapToCpuPriority_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->trap_reasonTrapToCpuPriority_set(type, priority); + RTK_API_UNLOCK(); + + return retVal; +} + + +/* Function Name: + * rtk_trap_reasonTrapToCpuPriority_get + * Description: + * Get priority value of a packet that trapped to CPU port according to specific reason. + * Input: + * type - reason that trap to CPU port. + * Output: + * pPriority - configured internal priority for such reason. + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - Invalid input parameter + * RT_ERR_NULL_POINTER - NULL pointer + * Note: + * Currently the trap reason that supported are listed as follows: + * - TRAP_REASON_RMA + * - TRAP_REASON_OAM + * - TRAP_REASON_1XUNAUTH + * - TRAP_REASON_VLANSTACK + * - TRAP_REASON_UNKNOWNMC + * - TRAP_REASON_IGMPMLD + */ +rtk_api_ret_t rtk_trap_reasonTrapToCpuPriority_get(rtk_trap_reason_type_t type, rtk_pri_t *pPriority) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->trap_reasonTrapToCpuPriority_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->trap_reasonTrapToCpuPriority_get(type, pPriority); + RTK_API_UNLOCK(); + + return retVal; +} + + + +/* Function Name: + * rtk_trap_rmaAction_set + * Description: + * Set Reserved multicast address action configuration. + * Input: + * type - rma type. + * rma_action - RMA action. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * + * There are 48 types of Reserved Multicast Address frame for application usage. + * (1)They are as following definition. + * - TRAP_BRG_GROUP, + * - TRAP_FD_PAUSE, + * - TRAP_SP_MCAST, + * - TRAP_1X_PAE, + * - TRAP_UNDEF_BRG_04, + * - TRAP_UNDEF_BRG_05, + * - TRAP_UNDEF_BRG_06, + * - TRAP_UNDEF_BRG_07, + * - TRAP_PROVIDER_BRIDGE_GROUP_ADDRESS, + * - TRAP_UNDEF_BRG_09, + * - TRAP_UNDEF_BRG_0A, + * - TRAP_UNDEF_BRG_0B, + * - TRAP_UNDEF_BRG_0C, + * - TRAP_PROVIDER_BRIDGE_GVRP_ADDRESS, + * - TRAP_8021AB, + * - TRAP_UNDEF_BRG_0F, + * - TRAP_BRG_MNGEMENT, + * - TRAP_UNDEFINED_11, + * - TRAP_UNDEFINED_12, + * - TRAP_UNDEFINED_13, + * - TRAP_UNDEFINED_14, + * - TRAP_UNDEFINED_15, + * - TRAP_UNDEFINED_16, + * - TRAP_UNDEFINED_17, + * - TRAP_UNDEFINED_18, + * - TRAP_UNDEFINED_19, + * - TRAP_UNDEFINED_1A, + * - TRAP_UNDEFINED_1B, + * - TRAP_UNDEFINED_1C, + * - TRAP_UNDEFINED_1D, + * - TRAP_UNDEFINED_1E, + * - TRAP_UNDEFINED_1F, + * - TRAP_GMRP, + * - TRAP_GVRP, + * - TRAP_UNDEF_GARP_22, + * - TRAP_UNDEF_GARP_23, + * - TRAP_UNDEF_GARP_24, + * - TRAP_UNDEF_GARP_25, + * - TRAP_UNDEF_GARP_26, + * - TRAP_UNDEF_GARP_27, + * - TRAP_UNDEF_GARP_28, + * - TRAP_UNDEF_GARP_29, + * - TRAP_UNDEF_GARP_2A, + * - TRAP_UNDEF_GARP_2B, + * - TRAP_UNDEF_GARP_2C, + * - TRAP_UNDEF_GARP_2D, + * - TRAP_UNDEF_GARP_2E, + * - TRAP_UNDEF_GARP_2F, + * - TRAP_CDP. + * - TRAP_CSSTP. + * - TRAP_LLDP. + * (2) The RMA action is as following: + * - RMA_ACTION_FORWARD + * - RMA_ACTION_TRAP2CPU + * - RMA_ACTION_DROP + * - RMA_ACTION_FORWARD_EXCLUDE_CPU + */ +rtk_api_ret_t rtk_trap_rmaAction_set(rtk_trap_type_t type, rtk_trap_rma_action_t rma_action) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->trap_rmaAction_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->trap_rmaAction_set(type, rma_action); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_trap_rmaAction_get + * Description: + * Get Reserved multicast address action configuration. + * Input: + * type - rma type. + * Output: + * pRma_action - RMA action. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * There are 48 types of Reserved Multicast Address frame for application usage. + * (1)They are as following definition. + * - TRAP_BRG_GROUP, + * - TRAP_FD_PAUSE, + * - TRAP_SP_MCAST, + * - TRAP_1X_PAE, + * - TRAP_UNDEF_BRG_04, + * - TRAP_UNDEF_BRG_05, + * - TRAP_UNDEF_BRG_06, + * - TRAP_UNDEF_BRG_07, + * - TRAP_PROVIDER_BRIDGE_GROUP_ADDRESS, + * - TRAP_UNDEF_BRG_09, + * - TRAP_UNDEF_BRG_0A, + * - TRAP_UNDEF_BRG_0B, + * - TRAP_UNDEF_BRG_0C, + * - TRAP_PROVIDER_BRIDGE_GVRP_ADDRESS, + * - TRAP_8021AB, + * - TRAP_UNDEF_BRG_0F, + * - TRAP_BRG_MNGEMENT, + * - TRAP_UNDEFINED_11, + * - TRAP_UNDEFINED_12, + * - TRAP_UNDEFINED_13, + * - TRAP_UNDEFINED_14, + * - TRAP_UNDEFINED_15, + * - TRAP_UNDEFINED_16, + * - TRAP_UNDEFINED_17, + * - TRAP_UNDEFINED_18, + * - TRAP_UNDEFINED_19, + * - TRAP_UNDEFINED_1A, + * - TRAP_UNDEFINED_1B, + * - TRAP_UNDEFINED_1C, + * - TRAP_UNDEFINED_1D, + * - TRAP_UNDEFINED_1E, + * - TRAP_UNDEFINED_1F, + * - TRAP_GMRP, + * - TRAP_GVRP, + * - TRAP_UNDEF_GARP_22, + * - TRAP_UNDEF_GARP_23, + * - TRAP_UNDEF_GARP_24, + * - TRAP_UNDEF_GARP_25, + * - TRAP_UNDEF_GARP_26, + * - TRAP_UNDEF_GARP_27, + * - TRAP_UNDEF_GARP_28, + * - TRAP_UNDEF_GARP_29, + * - TRAP_UNDEF_GARP_2A, + * - TRAP_UNDEF_GARP_2B, + * - TRAP_UNDEF_GARP_2C, + * - TRAP_UNDEF_GARP_2D, + * - TRAP_UNDEF_GARP_2E, + * - TRAP_UNDEF_GARP_2F, + * - TRAP_CDP. + * - TRAP_CSSTP. + * - TRAP_LLDP. + * (2) The RMA action is as following: + * - RMA_ACTION_FORWARD + * - RMA_ACTION_TRAP2CPU + * - RMA_ACTION_DROP + * - RMA_ACTION_FORWARD_EXCLUDE_CPU + */ +rtk_api_ret_t rtk_trap_rmaAction_get(rtk_trap_type_t type, rtk_trap_rma_action_t *pRma_action) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->trap_rmaAction_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->trap_rmaAction_get(type, pRma_action); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_trap_rmaKeepFormat_set + * Description: + * Set Reserved multicast address keep format configuration. + * Input: + * type - rma type. + * enable - enable keep format. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_ENABLE - Invalid IFG parameter + * Note: + * + * There are 48 types of Reserved Multicast Address frame for application usage. + * They are as following definition. + * - TRAP_BRG_GROUP, + * - TRAP_FD_PAUSE, + * - TRAP_SP_MCAST, + * - TRAP_1X_PAE, + * - TRAP_UNDEF_BRG_04, + * - TRAP_UNDEF_BRG_05, + * - TRAP_UNDEF_BRG_06, + * - TRAP_UNDEF_BRG_07, + * - TRAP_PROVIDER_BRIDGE_GROUP_ADDRESS, + * - TRAP_UNDEF_BRG_09, + * - TRAP_UNDEF_BRG_0A, + * - TRAP_UNDEF_BRG_0B, + * - TRAP_UNDEF_BRG_0C, + * - TRAP_PROVIDER_BRIDGE_GVRP_ADDRESS, + * - TRAP_8021AB, + * - TRAP_UNDEF_BRG_0F, + * - TRAP_BRG_MNGEMENT, + * - TRAP_UNDEFINED_11, + * - TRAP_UNDEFINED_12, + * - TRAP_UNDEFINED_13, + * - TRAP_UNDEFINED_14, + * - TRAP_UNDEFINED_15, + * - TRAP_UNDEFINED_16, + * - TRAP_UNDEFINED_17, + * - TRAP_UNDEFINED_18, + * - TRAP_UNDEFINED_19, + * - TRAP_UNDEFINED_1A, + * - TRAP_UNDEFINED_1B, + * - TRAP_UNDEFINED_1C, + * - TRAP_UNDEFINED_1D, + * - TRAP_UNDEFINED_1E, + * - TRAP_UNDEFINED_1F, + * - TRAP_GMRP, + * - TRAP_GVRP, + * - TRAP_UNDEF_GARP_22, + * - TRAP_UNDEF_GARP_23, + * - TRAP_UNDEF_GARP_24, + * - TRAP_UNDEF_GARP_25, + * - TRAP_UNDEF_GARP_26, + * - TRAP_UNDEF_GARP_27, + * - TRAP_UNDEF_GARP_28, + * - TRAP_UNDEF_GARP_29, + * - TRAP_UNDEF_GARP_2A, + * - TRAP_UNDEF_GARP_2B, + * - TRAP_UNDEF_GARP_2C, + * - TRAP_UNDEF_GARP_2D, + * - TRAP_UNDEF_GARP_2E, + * - TRAP_UNDEF_GARP_2F, + * - TRAP_CDP. + * - TRAP_CSSTP. + * - TRAP_LLDP. + */ +rtk_api_ret_t rtk_trap_rmaKeepFormat_set(rtk_trap_type_t type, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->trap_rmaKeepFormat_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->trap_rmaKeepFormat_set(type, enable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_trap_rmaKeepFormat_get + * Description: + * Get Reserved multicast address action configuration. + * Input: + * type - rma type. + * Output: + * pEnable - keep format status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * There are 48 types of Reserved Multicast Address frame for application usage. + * They are as following definition. + * - TRAP_BRG_GROUP, + * - TRAP_FD_PAUSE, + * - TRAP_SP_MCAST, + * - TRAP_1X_PAE, + * - TRAP_UNDEF_BRG_04, + * - TRAP_UNDEF_BRG_05, + * - TRAP_UNDEF_BRG_06, + * - TRAP_UNDEF_BRG_07, + * - TRAP_PROVIDER_BRIDGE_GROUP_ADDRESS, + * - TRAP_UNDEF_BRG_09, + * - TRAP_UNDEF_BRG_0A, + * - TRAP_UNDEF_BRG_0B, + * - TRAP_UNDEF_BRG_0C, + * - TRAP_PROVIDER_BRIDGE_GVRP_ADDRESS, + * - TRAP_8021AB, + * - TRAP_UNDEF_BRG_0F, + * - TRAP_BRG_MNGEMENT, + * - TRAP_UNDEFINED_11, + * - TRAP_UNDEFINED_12, + * - TRAP_UNDEFINED_13, + * - TRAP_UNDEFINED_14, + * - TRAP_UNDEFINED_15, + * - TRAP_UNDEFINED_16, + * - TRAP_UNDEFINED_17, + * - TRAP_UNDEFINED_18, + * - TRAP_UNDEFINED_19, + * - TRAP_UNDEFINED_1A, + * - TRAP_UNDEFINED_1B, + * - TRAP_UNDEFINED_1C, + * - TRAP_UNDEFINED_1D, + * - TRAP_UNDEFINED_1E, + * - TRAP_UNDEFINED_1F, + * - TRAP_GMRP, + * - TRAP_GVRP, + * - TRAP_UNDEF_GARP_22, + * - TRAP_UNDEF_GARP_23, + * - TRAP_UNDEF_GARP_24, + * - TRAP_UNDEF_GARP_25, + * - TRAP_UNDEF_GARP_26, + * - TRAP_UNDEF_GARP_27, + * - TRAP_UNDEF_GARP_28, + * - TRAP_UNDEF_GARP_29, + * - TRAP_UNDEF_GARP_2A, + * - TRAP_UNDEF_GARP_2B, + * - TRAP_UNDEF_GARP_2C, + * - TRAP_UNDEF_GARP_2D, + * - TRAP_UNDEF_GARP_2E, + * - TRAP_UNDEF_GARP_2F, + * - TRAP_CDP. + * - TRAP_CSSTP. + * - TRAP_LLDP. + */ +rtk_api_ret_t rtk_trap_rmaKeepFormat_get(rtk_trap_type_t type, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->trap_rmaKeepFormat_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->trap_rmaKeepFormat_get(type, pEnable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_trap_portUnknownMacPktAction_set + * Description: + * Set unknown source MAC packet action configuration. + * Input: + * port - Port ID. + * ucast_action - Unknown source MAC action. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid action. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can set unknown unicast packet action configuration. + * The unknown unicast action is as following: + * - UCAST_ACTION_FORWARD_PMASK + * - UCAST_ACTION_DROP + * - UCAST_ACTION_TRAP2CPU + */ +rtk_api_ret_t rtk_trap_portUnknownMacPktAction_set(rtk_port_t port, rtk_trap_ucast_action_t ucast_action) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->trap_portUnknownMacPktAction_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->trap_portUnknownMacPktAction_set(port, ucast_action); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_trap_portUnknownMacPktAction_get + * Description: + * Get unknown source MAC packet action configuration. + * Input: + * port - Port ID. + * Output: + * pUcast_action - Unknown source MAC action. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Null Pointer. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * + */ +rtk_api_ret_t rtk_trap_portUnknownMacPktAction_get(rtk_port_t port, rtk_trap_ucast_action_t *pUcast_action) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->trap_portUnknownMacPktAction_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->trap_portUnknownMacPktAction_get(port, pUcast_action); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_trap_portUnmatchMacPktAction_set + * Description: + * Set unmatch source MAC packet action configuration. + * Input: + * port - Port ID + * ucast_action - Unmatch source MAC action. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid action. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can set unknown unicast packet action configuration. + * The unknown unicast action is as following: + * - UCAST_ACTION_FORWARD_PMASK + * - UCAST_ACTION_DROP + * - UCAST_ACTION_TRAP2CPU + */ +rtk_api_ret_t rtk_trap_portUnmatchMacPktAction_set(rtk_port_t port, rtk_trap_ucast_action_t ucast_action) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->trap_portUnmatchMacPktAction_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->trap_portUnmatchMacPktAction_set(port, ucast_action); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_trap_portUnmatchMacPktAction_get + * Description: + * Get unmatch source MAC packet action configuration. + * Input: + * port - Port ID + * Output: + * pUcast_action - Unmatch source MAC action. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid action. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can set unknown unicast packet action configuration. + * The unknown unicast action is as following: + * - UCAST_ACTION_FORWARD_PMASK + * - UCAST_ACTION_DROP + * - UCAST_ACTION_TRAP2CPU + */ +rtk_api_ret_t rtk_trap_portUnmatchMacPktAction_get(rtk_port_t port, rtk_trap_ucast_action_t *pUcast_action) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->trap_portUnmatchMacPktAction_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->trap_portUnmatchMacPktAction_get(port, pUcast_action); + RTK_API_UNLOCK(); + + return retVal; +} + + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/trap.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/trap.h new file mode 100644 index 00000000..1e40ed51 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/trap.h @@ -0,0 +1,854 @@ + /* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8367/RTL8367C switch high-level API + * + * Feature : The file includes Trap module high-layer API defination + * + */ + +#ifndef __RTK_API_TRAP_H__ +#define __RTK_API_TRAP_H__ + + +typedef enum rtk_trap_type_e +{ + TRAP_BRG_GROUP = 0, + TRAP_FD_PAUSE, + TRAP_SP_MCAST, + TRAP_1X_PAE, + TRAP_UNDEF_BRG_04, + TRAP_UNDEF_BRG_05, + TRAP_UNDEF_BRG_06, + TRAP_UNDEF_BRG_07, + TRAP_PROVIDER_BRIDGE_GROUP_ADDRESS, + TRAP_UNDEF_BRG_09, + TRAP_UNDEF_BRG_0A, + TRAP_UNDEF_BRG_0B, + TRAP_UNDEF_BRG_0C, + TRAP_PROVIDER_BRIDGE_GVRP_ADDRESS, + TRAP_8021AB, + TRAP_UNDEF_BRG_0F, + TRAP_BRG_MNGEMENT, + TRAP_UNDEFINED_11, + TRAP_UNDEFINED_12, + TRAP_UNDEFINED_13, + TRAP_UNDEFINED_14, + TRAP_UNDEFINED_15, + TRAP_UNDEFINED_16, + TRAP_UNDEFINED_17, + TRAP_UNDEFINED_18, + TRAP_UNDEFINED_19, + TRAP_UNDEFINED_1A, + TRAP_UNDEFINED_1B, + TRAP_UNDEFINED_1C, + TRAP_UNDEFINED_1D, + TRAP_UNDEFINED_1E, + TRAP_UNDEFINED_1F, + TRAP_GMRP, + TRAP_GVRP, + TRAP_UNDEF_GARP_22, + TRAP_UNDEF_GARP_23, + TRAP_UNDEF_GARP_24, + TRAP_UNDEF_GARP_25, + TRAP_UNDEF_GARP_26, + TRAP_UNDEF_GARP_27, + TRAP_UNDEF_GARP_28, + TRAP_UNDEF_GARP_29, + TRAP_UNDEF_GARP_2A, + TRAP_UNDEF_GARP_2B, + TRAP_UNDEF_GARP_2C, + TRAP_UNDEF_GARP_2D, + TRAP_UNDEF_GARP_2E, + TRAP_UNDEF_GARP_2F, + TRAP_CDP, + TRAP_CSSTP, + TRAP_LLDP, + TRAP_END, +}rtk_trap_type_t; + + +typedef enum rtk_mcast_type_e +{ + MCAST_L2 = 0, + MCAST_IPV4, + MCAST_IPV6, + MCAST_END +} rtk_mcast_type_t; + +typedef enum rtk_trap_mcast_action_e +{ + MCAST_ACTION_FORWARD = 0, + MCAST_ACTION_DROP, + MCAST_ACTION_TRAP2CPU, + MCAST_ACTION_ROUTER_PORT, + MCAST_ACTION_DROP_EX_RMA, + MCAST_ACTION_END +} rtk_trap_mcast_action_t; + +typedef enum rtk_trap_rma_action_e +{ + RMA_ACTION_FORWARD = 0, + RMA_ACTION_TRAP2CPU, + RMA_ACTION_DROP, + RMA_ACTION_FORWARD_EXCLUDE_CPU, + RMA_ACTION_END +} rtk_trap_rma_action_t; + +typedef enum rtk_trap_ucast_action_e +{ + UCAST_ACTION_FORWARD_PMASK = 0, + UCAST_ACTION_DROP, + UCAST_ACTION_TRAP2CPU, + UCAST_ACTION_FLOODING, + UCAST_ACTION_COPY28051, + UCAST_ACTION_END +} rtk_trap_ucast_action_t; + +typedef enum rtk_trap_ucast_type_e +{ + UCAST_UNKNOWNDA = 0, + UCAST_UNKNOWNSA, + UCAST_UNMATCHSA, + UCAST_END +} rtk_trap_ucast_type_t; + +typedef enum rtk_trap_reason_type_e +{ + TRAP_REASON_RMA = 0, + TRAP_REASON_OAM, + TRAP_REASON_1XUNAUTH, + TRAP_REASON_VLANSTACK, + TRAP_REASON_UNKNOWNMC, + TRAP_REASON_IGMPMLD, + TRAP_REASON_END, +} rtk_trap_reason_type_t; + + +/* Function Name: + * rtk_trap_unknownUnicastPktAction_set + * Description: + * Set unknown unicast packet action configuration. + * Input: + * port - ingress port ID for unknown unicast packet + * ucast_action - Unknown unicast action. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid action. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can set unknown unicast packet action configuration. + * The unknown unicast action is as following: + * - UCAST_ACTION_FORWARD_PMASK + * - UCAST_ACTION_DROP + * - UCAST_ACTION_TRAP2CPU + * - UCAST_ACTION_FLOODING + */ +extern rtk_api_ret_t rtk_trap_unknownUnicastPktAction_set(rtk_port_t port, rtk_trap_ucast_action_t ucast_action); + +/* Function Name: + * rtk_trap_unknownUnicastPktAction_get + * Description: + * Get unknown unicast packet action configuration. + * Input: + * port - ingress port ID for unknown unicast packet + * Output: + * pUcast_action - Unknown unicast action. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid action. + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * This API can get unknown unicast packet action configuration. + * The unknown unicast action is as following: + * - UCAST_ACTION_FORWARD_PMASK + * - UCAST_ACTION_DROP + * - UCAST_ACTION_TRAP2CPU + * - UCAST_ACTION_FLOODING + */ +extern rtk_api_ret_t rtk_trap_unknownUnicastPktAction_get(rtk_port_t port, rtk_trap_ucast_action_t *pUcast_action); + +/* Function Name: + * rtk_trap_unknownMacPktAction_set + * Description: + * Set unknown source MAC packet action configuration. + * Input: + * ucast_action - Unknown source MAC action. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid action. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can set unknown unicast packet action configuration. + * The unknown unicast action is as following: + * - UCAST_ACTION_FORWARD_PMASK + * - UCAST_ACTION_DROP + * - UCAST_ACTION_TRAP2CPU + */ +extern rtk_api_ret_t rtk_trap_unknownMacPktAction_set(rtk_trap_ucast_action_t ucast_action); + +/* Function Name: + * rtk_trap_unknownMacPktAction_get + * Description: + * Get unknown source MAC packet action configuration. + * Input: + * None. + * Output: + * pUcast_action - Unknown source MAC action. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Null Pointer. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * + */ +extern rtk_api_ret_t rtk_trap_unknownMacPktAction_get(rtk_trap_ucast_action_t *pUcast_action); + +/* Function Name: + * rtk_trap_unmatchMacPktAction_set + * Description: + * Set unmatch source MAC packet action configuration. + * Input: + * ucast_action - Unmatch source MAC action. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid action. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can set unknown unicast packet action configuration. + * The unknown unicast action is as following: + * - UCAST_ACTION_FORWARD_PMASK + * - UCAST_ACTION_DROP + * - UCAST_ACTION_TRAP2CPU + */ +extern rtk_api_ret_t rtk_trap_unmatchMacPktAction_set(rtk_trap_ucast_action_t ucast_action); + +/* Function Name: + * rtk_trap_unmatchMacPktAction_get + * Description: + * Get unmatch source MAC packet action configuration. + * Input: + * None. + * Output: + * pUcast_action - Unmatch source MAC action. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid action. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can set unknown unicast packet action configuration. + * The unknown unicast action is as following: + * - UCAST_ACTION_FORWARD_PMASK + * - UCAST_ACTION_DROP + * - UCAST_ACTION_TRAP2CPU + */ +extern rtk_api_ret_t rtk_trap_unmatchMacPktAction_get(rtk_trap_ucast_action_t *pUcast_action); + +/* Function Name: + * rtk_trap_unmatchMacMoving_set + * Description: + * Set unmatch source MAC packet moving state. + * Input: + * port - Port ID. + * enable - ENABLED: allow SA moving, DISABLE: don't allow SA moving. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid action. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + */ +extern rtk_api_ret_t rtk_trap_unmatchMacMoving_set(rtk_port_t port, rtk_enable_t enable); + +/* Function Name: + * rtk_trap_unmatchMacMoving_get + * Description: + * Set unmatch source MAC packet moving state. + * Input: + * port - Port ID. + * Output: + * pEnable - ENABLED: allow SA moving, DISABLE: don't allow SA moving. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid action. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + */ +extern rtk_api_ret_t rtk_trap_unmatchMacMoving_get(rtk_port_t port, rtk_enable_t *pEnable); + +/* Function Name: + * rtk_trap_unknownMcastPktAction_set + * Description: + * Set behavior of unknown multicast + * Input: + * port - Port id. + * type - unknown multicast packet type. + * mcast_action - unknown multicast action. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_NOT_ALLOWED - Invalid action. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * When receives an unknown multicast packet, switch may trap, drop or flood this packet + * (1) The unknown multicast packet type is as following: + * - MCAST_L2 + * - MCAST_IPV4 + * - MCAST_IPV6 + * (2) The unknown multicast action is as following: + * - MCAST_ACTION_FORWARD + * - MCAST_ACTION_DROP + * - MCAST_ACTION_TRAP2CPU + */ +extern rtk_api_ret_t rtk_trap_unknownMcastPktAction_set(rtk_port_t port, rtk_mcast_type_t type, rtk_trap_mcast_action_t mcast_action); + +/* Function Name: + * rtk_trap_unknownMcastPktAction_get + * Description: + * Get behavior of unknown multicast + * Input: + * type - unknown multicast packet type. + * Output: + * pMcast_action - unknown multicast action. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_NOT_ALLOWED - Invalid operation. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * When receives an unknown multicast packet, switch may trap, drop or flood this packet + * (1) The unknown multicast packet type is as following: + * - MCAST_L2 + * - MCAST_IPV4 + * - MCAST_IPV6 + * (2) The unknown multicast action is as following: + * - MCAST_ACTION_FORWARD + * - MCAST_ACTION_DROP + * - MCAST_ACTION_TRAP2CPU + */ +extern rtk_api_ret_t rtk_trap_unknownMcastPktAction_get(rtk_port_t port, rtk_mcast_type_t type, rtk_trap_mcast_action_t *pMcast_action); + +/* Function Name: + * rtk_trap_lldpEnable_set + * Description: + * Set LLDP enable. + * Input: + * enabled - LLDP enable, 0: follow RMA, 1: use LLDP action. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid action. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * - DMAC Assignment + * - 01:80:c2:00:00:0e ethertype = 0x88CC LLDP + * - 01:80:c2:00:00:03 ethertype = 0x88CC + * - 01:80:c2:00:00:00 ethertype = 0x88CC + + */ +extern rtk_api_ret_t rtk_trap_lldpEnable_set(rtk_enable_t enabled); + +/* Function Name: + * rtk_trap_lldpEnable_get + * Description: + * Get LLDP status. + * Input: + * None + * Output: + * pEnabled - LLDP enable, 0: follow RMA, 1: use LLDP action. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * LLDP is as following definition. + * - DMAC Assignment + * - 01:80:c2:00:00:0e ethertype = 0x88CC LLDP + * - 01:80:c2:00:00:03 ethertype = 0x88CC + * - 01:80:c2:00:00:00 ethertype = 0x88CC + */ +extern rtk_api_ret_t rtk_trap_lldpEnable_get(rtk_enable_t *pEnabled); + +/* Function Name: + * rtk_trap_reasonTrapToCpuPriority_set + * Description: + * Set priority value of a packet that trapped to CPU port according to specific reason. + * Input: + * type - reason that trap to CPU port. + * priority - internal priority that is going to be set for specific trap reason. + * Output: + * None. + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - Invalid input parameter + * Note: + * Currently the trap reason that supported are listed as follows: + * - TRAP_REASON_RMA + * - TRAP_REASON_OAM + * - TRAP_REASON_1XUNAUTH + * - TRAP_REASON_VLANSTACK + * - TRAP_REASON_UNKNOWNMC + * - TRAP_REASON_IGMPMLD + */ +extern rtk_api_ret_t rtk_trap_reasonTrapToCpuPriority_set(rtk_trap_reason_type_t type, rtk_pri_t priority); + +/* Function Name: + * rtk_trap_reasonTrapToCpuPriority_get + * Description: + * Get priority value of a packet that trapped to CPU port according to specific reason. + * Input: + * type - reason that trap to CPU port. + * Output: + * pPriority - configured internal priority for such reason. + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - Invalid input parameter + * RT_ERR_NULL_POINTER - NULL pointer + * Note: + * Currently the trap reason that supported are listed as follows: + * - TRAP_REASON_RMA + * - TRAP_REASON_OAM + * - TRAP_REASON_1XUNAUTH + * - TRAP_REASON_VLANSTACK + * - TRAP_REASON_UNKNOWNMC + * - TRAP_REASON_IGMPMLD + */ +extern rtk_api_ret_t rtk_trap_reasonTrapToCpuPriority_get(rtk_trap_reason_type_t type, rtk_pri_t *pPriority); + +/* Function Name: + * rtk_trap_rmaAction_set + * Description: + * Set Reserved multicast address action configuration. + * Input: + * type - rma type. + * rma_action - RMA action. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_ENABLE - Invalid IFG parameter + * Note: + * + * There are 48 types of Reserved Multicast Address frame for application usage. + * (1)They are as following definition. + * - TRAP_BRG_GROUP, + * - TRAP_FD_PAUSE, + * - TRAP_SP_MCAST, + * - TRAP_1X_PAE, + * - TRAP_UNDEF_BRG_04, + * - TRAP_UNDEF_BRG_05, + * - TRAP_UNDEF_BRG_06, + * - TRAP_UNDEF_BRG_07, + * - TRAP_PROVIDER_BRIDGE_GROUP_ADDRESS, + * - TRAP_UNDEF_BRG_09, + * - TRAP_UNDEF_BRG_0A, + * - TRAP_UNDEF_BRG_0B, + * - TRAP_UNDEF_BRG_0C, + * - TRAP_PROVIDER_BRIDGE_GVRP_ADDRESS, + * - TRAP_8021AB, + * - TRAP_UNDEF_BRG_0F, + * - TRAP_BRG_MNGEMENT, + * - TRAP_UNDEFINED_11, + * - TRAP_UNDEFINED_12, + * - TRAP_UNDEFINED_13, + * - TRAP_UNDEFINED_14, + * - TRAP_UNDEFINED_15, + * - TRAP_UNDEFINED_16, + * - TRAP_UNDEFINED_17, + * - TRAP_UNDEFINED_18, + * - TRAP_UNDEFINED_19, + * - TRAP_UNDEFINED_1A, + * - TRAP_UNDEFINED_1B, + * - TRAP_UNDEFINED_1C, + * - TRAP_UNDEFINED_1D, + * - TRAP_UNDEFINED_1E, + * - TRAP_UNDEFINED_1F, + * - TRAP_GMRP, + * - TRAP_GVRP, + * - TRAP_UNDEF_GARP_22, + * - TRAP_UNDEF_GARP_23, + * - TRAP_UNDEF_GARP_24, + * - TRAP_UNDEF_GARP_25, + * - TRAP_UNDEF_GARP_26, + * - TRAP_UNDEF_GARP_27, + * - TRAP_UNDEF_GARP_28, + * - TRAP_UNDEF_GARP_29, + * - TRAP_UNDEF_GARP_2A, + * - TRAP_UNDEF_GARP_2B, + * - TRAP_UNDEF_GARP_2C, + * - TRAP_UNDEF_GARP_2D, + * - TRAP_UNDEF_GARP_2E, + * - TRAP_UNDEF_GARP_2F, + * - TRAP_CDP. + * - TRAP_CSSTP. + * - TRAP_LLDP. + * (2) The RMA action is as following: + * - RMA_ACTION_FORWARD + * - RMA_ACTION_TRAP2CPU + * - RMA_ACTION_DROP + * - RMA_ACTION_FORWARD_EXCLUDE_CPU + */ +extern rtk_api_ret_t rtk_trap_rmaAction_set(rtk_trap_type_t type, rtk_trap_rma_action_t rma_action); + +/* Function Name: + * rtk_trap_rmaAction_get + * Description: + * Get Reserved multicast address action configuration. + * Input: + * type - rma type. + * Output: + * pRma_action - RMA action. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * There are 48 types of Reserved Multicast Address frame for application usage. + * (1)They are as following definition. + * - TRAP_BRG_GROUP, + * - TRAP_FD_PAUSE, + * - TRAP_SP_MCAST, + * - TRAP_1X_PAE, + * - TRAP_UNDEF_BRG_04, + * - TRAP_UNDEF_BRG_05, + * - TRAP_UNDEF_BRG_06, + * - TRAP_UNDEF_BRG_07, + * - TRAP_PROVIDER_BRIDGE_GROUP_ADDRESS, + * - TRAP_UNDEF_BRG_09, + * - TRAP_UNDEF_BRG_0A, + * - TRAP_UNDEF_BRG_0B, + * - TRAP_UNDEF_BRG_0C, + * - TRAP_PROVIDER_BRIDGE_GVRP_ADDRESS, + * - TRAP_8021AB, + * - TRAP_UNDEF_BRG_0F, + * - TRAP_BRG_MNGEMENT, + * - TRAP_UNDEFINED_11, + * - TRAP_UNDEFINED_12, + * - TRAP_UNDEFINED_13, + * - TRAP_UNDEFINED_14, + * - TRAP_UNDEFINED_15, + * - TRAP_UNDEFINED_16, + * - TRAP_UNDEFINED_17, + * - TRAP_UNDEFINED_18, + * - TRAP_UNDEFINED_19, + * - TRAP_UNDEFINED_1A, + * - TRAP_UNDEFINED_1B, + * - TRAP_UNDEFINED_1C, + * - TRAP_UNDEFINED_1D, + * - TRAP_UNDEFINED_1E, + * - TRAP_UNDEFINED_1F, + * - TRAP_GMRP, + * - TRAP_GVRP, + * - TRAP_UNDEF_GARP_22, + * - TRAP_UNDEF_GARP_23, + * - TRAP_UNDEF_GARP_24, + * - TRAP_UNDEF_GARP_25, + * - TRAP_UNDEF_GARP_26, + * - TRAP_UNDEF_GARP_27, + * - TRAP_UNDEF_GARP_28, + * - TRAP_UNDEF_GARP_29, + * - TRAP_UNDEF_GARP_2A, + * - TRAP_UNDEF_GARP_2B, + * - TRAP_UNDEF_GARP_2C, + * - TRAP_UNDEF_GARP_2D, + * - TRAP_UNDEF_GARP_2E, + * - TRAP_UNDEF_GARP_2F, + * - TRAP_CDP. + * - TRAP_CSSTP. + * - TRAP_LLDP. + * (2) The RMA action is as following: + * - RMA_ACTION_FORWARD + * - RMA_ACTION_TRAP2CPU + * - RMA_ACTION_DROP + * - RMA_ACTION_FORWARD_EXCLUDE_CPU + */ +extern rtk_api_ret_t rtk_trap_rmaAction_get(rtk_trap_type_t type, rtk_trap_rma_action_t *pRma_action); + +/* Function Name: + * rtk_trap_rmaKeepFormat_set + * Description: + * Set Reserved multicast address keep format configuration. + * Input: + * type - rma type. + * enable - enable keep format. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_ENABLE - Invalid IFG parameter + * Note: + * + * There are 48 types of Reserved Multicast Address frame for application usage. + * They are as following definition. + * - TRAP_BRG_GROUP, + * - TRAP_FD_PAUSE, + * - TRAP_SP_MCAST, + * - TRAP_1X_PAE, + * - TRAP_UNDEF_BRG_04, + * - TRAP_UNDEF_BRG_05, + * - TRAP_UNDEF_BRG_06, + * - TRAP_UNDEF_BRG_07, + * - TRAP_PROVIDER_BRIDGE_GROUP_ADDRESS, + * - TRAP_UNDEF_BRG_09, + * - TRAP_UNDEF_BRG_0A, + * - TRAP_UNDEF_BRG_0B, + * - TRAP_UNDEF_BRG_0C, + * - TRAP_PROVIDER_BRIDGE_GVRP_ADDRESS, + * - TRAP_8021AB, + * - TRAP_UNDEF_BRG_0F, + * - TRAP_BRG_MNGEMENT, + * - TRAP_UNDEFINED_11, + * - TRAP_UNDEFINED_12, + * - TRAP_UNDEFINED_13, + * - TRAP_UNDEFINED_14, + * - TRAP_UNDEFINED_15, + * - TRAP_UNDEFINED_16, + * - TRAP_UNDEFINED_17, + * - TRAP_UNDEFINED_18, + * - TRAP_UNDEFINED_19, + * - TRAP_UNDEFINED_1A, + * - TRAP_UNDEFINED_1B, + * - TRAP_UNDEFINED_1C, + * - TRAP_UNDEFINED_1D, + * - TRAP_UNDEFINED_1E, + * - TRAP_UNDEFINED_1F, + * - TRAP_GMRP, + * - TRAP_GVRP, + * - TRAP_UNDEF_GARP_22, + * - TRAP_UNDEF_GARP_23, + * - TRAP_UNDEF_GARP_24, + * - TRAP_UNDEF_GARP_25, + * - TRAP_UNDEF_GARP_26, + * - TRAP_UNDEF_GARP_27, + * - TRAP_UNDEF_GARP_28, + * - TRAP_UNDEF_GARP_29, + * - TRAP_UNDEF_GARP_2A, + * - TRAP_UNDEF_GARP_2B, + * - TRAP_UNDEF_GARP_2C, + * - TRAP_UNDEF_GARP_2D, + * - TRAP_UNDEF_GARP_2E, + * - TRAP_UNDEF_GARP_2F, + * - TRAP_CDP. + * - TRAP_CSSTP. + * - TRAP_LLDP. + */ +extern rtk_api_ret_t rtk_trap_rmaKeepFormat_set(rtk_trap_type_t type, rtk_enable_t enable); + +/* Function Name: + * rtk_trap_rmaKeepFormat_get + * Description: + * Get Reserved multicast address action configuration. + * Input: + * type - rma type. + * Output: + * pEnable - keep format status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * There are 48 types of Reserved Multicast Address frame for application usage. + * They are as following definition. + * - TRAP_BRG_GROUP, + * - TRAP_FD_PAUSE, + * - TRAP_SP_MCAST, + * - TRAP_1X_PAE, + * - TRAP_UNDEF_BRG_04, + * - TRAP_UNDEF_BRG_05, + * - TRAP_UNDEF_BRG_06, + * - TRAP_UNDEF_BRG_07, + * - TRAP_PROVIDER_BRIDGE_GROUP_ADDRESS, + * - TRAP_UNDEF_BRG_09, + * - TRAP_UNDEF_BRG_0A, + * - TRAP_UNDEF_BRG_0B, + * - TRAP_UNDEF_BRG_0C, + * - TRAP_PROVIDER_BRIDGE_GVRP_ADDRESS, + * - TRAP_8021AB, + * - TRAP_UNDEF_BRG_0F, + * - TRAP_BRG_MNGEMENT, + * - TRAP_UNDEFINED_11, + * - TRAP_UNDEFINED_12, + * - TRAP_UNDEFINED_13, + * - TRAP_UNDEFINED_14, + * - TRAP_UNDEFINED_15, + * - TRAP_UNDEFINED_16, + * - TRAP_UNDEFINED_17, + * - TRAP_UNDEFINED_18, + * - TRAP_UNDEFINED_19, + * - TRAP_UNDEFINED_1A, + * - TRAP_UNDEFINED_1B, + * - TRAP_UNDEFINED_1C, + * - TRAP_UNDEFINED_1D, + * - TRAP_UNDEFINED_1E, + * - TRAP_UNDEFINED_1F, + * - TRAP_GMRP, + * - TRAP_GVRP, + * - TRAP_UNDEF_GARP_22, + * - TRAP_UNDEF_GARP_23, + * - TRAP_UNDEF_GARP_24, + * - TRAP_UNDEF_GARP_25, + * - TRAP_UNDEF_GARP_26, + * - TRAP_UNDEF_GARP_27, + * - TRAP_UNDEF_GARP_28, + * - TRAP_UNDEF_GARP_29, + * - TRAP_UNDEF_GARP_2A, + * - TRAP_UNDEF_GARP_2B, + * - TRAP_UNDEF_GARP_2C, + * - TRAP_UNDEF_GARP_2D, + * - TRAP_UNDEF_GARP_2E, + * - TRAP_UNDEF_GARP_2F, + * - TRAP_CDP. + * - TRAP_CSSTP. + * - TRAP_LLDP. + */ +extern rtk_api_ret_t rtk_trap_rmaKeepFormat_get(rtk_trap_type_t type, rtk_enable_t *pEnable); + + +/* Function Name: + * rtk_trap_portUnknownMacPktAction_set + * Description: + * Set unknown source MAC packet action configuration. + * Input: + * port - Port ID. + * ucast_action - Unknown source MAC action. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid action. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can set unknown unicast packet action configuration. + * The unknown unicast action is as following: + * - UCAST_ACTION_FORWARD_PMASK + * - UCAST_ACTION_DROP + * - UCAST_ACTION_TRAP2CPU + */ +extern rtk_api_ret_t rtk_trap_portUnknownMacPktAction_set(rtk_port_t port, rtk_trap_ucast_action_t ucast_action); + +/* Function Name: + * rtk_trap_portUnknownMacPktAction_get + * Description: + * Get unknown source MAC packet action configuration. + * Input: + * port - Port ID. + * Output: + * pUcast_action - Unknown source MAC action. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Null Pointer. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * + */ +extern rtk_api_ret_t rtk_trap_portUnknownMacPktAction_get(rtk_port_t port, rtk_trap_ucast_action_t *pUcast_action); + +/* Function Name: + * rtk_trap_portUnmatchMacPktAction_set + * Description: + * Set unmatch source MAC packet action configuration. + * Input: + * port - Port ID + * ucast_action - Unmatch source MAC action. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid action. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can set unknown unicast packet action configuration. + * The unknown unicast action is as following: + * - UCAST_ACTION_FORWARD_PMASK + * - UCAST_ACTION_DROP + * - UCAST_ACTION_TRAP2CPU + */ +extern rtk_api_ret_t rtk_trap_portUnmatchMacPktAction_set(rtk_port_t port, rtk_trap_ucast_action_t ucast_action); + +/* Function Name: + * rtk_trap_portUnmatchMacPktAction_get + * Description: + * Get unmatch source MAC packet action configuration. + * Input: + * port - Port ID + * Output: + * pUcast_action - Unmatch source MAC action. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid action. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can set unknown unicast packet action configuration. + * The unknown unicast action is as following: + * - UCAST_ACTION_FORWARD_PMASK + * - UCAST_ACTION_DROP + * - UCAST_ACTION_TRAP2CPU + */ +extern rtk_api_ret_t rtk_trap_portUnmatchMacPktAction_get(rtk_port_t port, rtk_trap_ucast_action_t *pUcast_action); + + +#endif /* __RTK_API_TRAP_H__ */ + + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/trunk.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/trunk.c new file mode 100644 index 00000000..77524eed --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/trunk.c @@ -0,0 +1,448 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8367C + * Feature : Here is a list of all functions and variables in Trunk module. + * + */ + +#include +#include +#include +#include + +#include + +/* Function Name: + * rtk_trunk_port_set + * Description: + * Set trunking group available port mask + * Input: + * trk_gid - trunk group id + * pTrunk_member_portmask - Logic trunking member port mask + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_LA_TRUNK_ID - Invalid trunking group + * RT_ERR_PORT_MASK - Invalid portmask. + * Note: + * The API can set port trunking group port mask. Each port trunking group has max 4 ports. + * If enabled port mask has less than 2 ports available setting, then this trunking group function is disabled. + */ +rtk_api_ret_t rtk_trunk_port_set(rtk_trunk_group_t trk_gid, rtk_portmask_t *pTrunk_member_portmask) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->trunk_port_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->trunk_port_set(trk_gid, pTrunk_member_portmask); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_trunk_port_get + * Description: + * Get trunking group available port mask + * Input: + * trk_gid - trunk group id + * Output: + * pTrunk_member_portmask - Logic trunking member port mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_LA_TRUNK_ID - Invalid trunking group + * Note: + * The API can get 2 port trunking group. + */ +rtk_api_ret_t rtk_trunk_port_get(rtk_trunk_group_t trk_gid, rtk_portmask_t *pTrunk_member_portmask) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->trunk_port_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->trunk_port_get(trk_gid, pTrunk_member_portmask); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_trunk_distributionAlgorithm_set + * Description: + * Set port trunking hash select sources + * Input: + * trk_gid - trunk group id + * algo_bitmask - Bitmask of the distribution algorithm + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_LA_TRUNK_ID - Invalid trunking group + * RT_ERR_LA_HASHMASK - Hash algorithm selection error. + * RT_ERR_PORT_MASK - Invalid portmask. + * Note: + * The API can set port trunking hash algorithm sources. + * 7 bits mask for link aggregation group0 hash parameter selection {DIP, SIP, DMAC, SMAC, SPA} + * - 0b0000001: SPA + * - 0b0000010: SMAC + * - 0b0000100: DMAC + * - 0b0001000: SIP + * - 0b0010000: DIP + * - 0b0100000: TCP/UDP Source Port + * - 0b1000000: TCP/UDP Destination Port + * Example: + * - 0b0000011: SMAC & SPA + * - Note that it could be an arbitrary combination or independent set + */ +rtk_api_ret_t rtk_trunk_distributionAlgorithm_set(rtk_trunk_group_t trk_gid, rtk_uint32 algo_bitmask) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->trunk_distributionAlgorithm_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->trunk_distributionAlgorithm_set(trk_gid, algo_bitmask); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_trunk_distributionAlgorithm_get + * Description: + * Get port trunking hash select sources + * Input: + * trk_gid - trunk group id + * Output: + * pAlgo_bitmask - Bitmask of the distribution algorithm + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_LA_TRUNK_ID - Invalid trunking group + * Note: + * The API can get port trunking hash algorithm sources. + */ +rtk_api_ret_t rtk_trunk_distributionAlgorithm_get(rtk_trunk_group_t trk_gid, rtk_uint32 *pAlgo_bitmask) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->trunk_distributionAlgorithm_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->trunk_distributionAlgorithm_get(trk_gid, pAlgo_bitmask); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_trunk_trafficSeparate_set + * Description: + * Set the traffic separation setting of a trunk group from the specified device. + * Input: + * trk_gid - trunk group id + * separateType - traffic separation setting + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_LA_TRUNK_ID - invalid trunk ID + * RT_ERR_LA_HASHMASK - invalid hash mask + * Note: + * SEPARATE_NONE: disable traffic separation + * SEPARATE_FLOOD: trunk MSB link up port is dedicated to TX flooding (L2 lookup miss) traffic + */ +rtk_api_ret_t rtk_trunk_trafficSeparate_set(rtk_trunk_group_t trk_gid, rtk_trunk_separateType_t separateType) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->trunk_trafficSeparate_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->trunk_trafficSeparate_set(trk_gid, separateType); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_trunk_trafficSeparate_get + * Description: + * Get the traffic separation setting of a trunk group from the specified device. + * Input: + * trk_gid - trunk group id + * Output: + * pSeparateType - pointer separated traffic type + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_LA_TRUNK_ID - invalid trunk ID + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * SEPARATE_NONE: disable traffic separation + * SEPARATE_FLOOD: trunk MSB link up port is dedicated to TX flooding (L2 lookup miss) traffic + */ +rtk_api_ret_t rtk_trunk_trafficSeparate_get(rtk_trunk_group_t trk_gid, rtk_trunk_separateType_t *pSeparateType) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->trunk_trafficSeparate_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->trunk_trafficSeparate_get(trk_gid, pSeparateType); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_trunk_mode_set + * Description: + * Set the trunk mode to the specified device. + * Input: + * mode - trunk mode + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT - invalid input parameter + * Note: + * The enum of the trunk mode as following + * - TRUNK_MODE_NORMAL + * - TRUNK_MODE_DUMB + */ +rtk_api_ret_t rtk_trunk_mode_set(rtk_trunk_mode_t mode) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->trunk_mode_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->trunk_mode_set(mode); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_trunk_mode_get + * Description: + * Get the trunk mode from the specified device. + * Input: + * None + * Output: + * pMode - pointer buffer of trunk mode + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * The enum of the trunk mode as following + * - TRUNK_MODE_NORMAL + * - TRUNK_MODE_DUMB + */ +rtk_api_ret_t rtk_trunk_mode_get(rtk_trunk_mode_t *pMode) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->trunk_mode_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->trunk_mode_get(pMode); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_trunk_trafficPause_set + * Description: + * Set the traffic pause setting of a trunk group. + * Input: + * trk_gid - trunk group id + * enable - traffic pause state + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_LA_TRUNK_ID - invalid trunk ID + * Note: + * None. + */ +rtk_api_ret_t rtk_trunk_trafficPause_set(rtk_trunk_group_t trk_gid, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->trunk_trafficPause_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->trunk_trafficPause_set(trk_gid, enable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_trunk_trafficPause_get + * Description: + * Get the traffic pause setting of a trunk group. + * Input: + * trk_gid - trunk group id + * Output: + * pEnable - pointer of traffic pause state. + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_LA_TRUNK_ID - invalid trunk ID + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None. + */ +rtk_api_ret_t rtk_trunk_trafficPause_get(rtk_trunk_group_t trk_gid, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->trunk_trafficPause_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->trunk_trafficPause_get(trk_gid, pEnable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_trunk_hashMappingTable_set + * Description: + * Set hash value to port array in the trunk group id from the specified device. + * Input: + * trk_gid - trunk group id + * pHash2Port_array - ports associate with the hash value + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_LA_TRUNK_ID - invalid trunk ID + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * RT_ERR_LA_TRUNK_NOT_EXIST - the trunk doesn't exist + * RT_ERR_LA_NOT_MEMBER_PORT - the port is not a member port of the trunk + * RT_ERR_LA_CPUPORT - CPU port can not be aggregated port + * Note: + * Trunk group 0 & 1 shares the same hash mapping table. + * Trunk group 2 uses a independent table. + */ +rtk_api_ret_t rtk_trunk_hashMappingTable_set(rtk_trunk_group_t trk_gid, rtk_trunk_hashVal2Port_t *pHash2Port_array) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->trunk_hashMappingTable_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->trunk_hashMappingTable_set(trk_gid, pHash2Port_array); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_trunk_hashMappingTable_get + * Description: + * Get hash value to port array in the trunk group id from the specified device. + * Input: + * trk_gid - trunk group id + * Output: + * pHash2Port_array - pointer buffer of ports associate with the hash value + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_LA_TRUNK_ID - invalid trunk ID + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * Trunk group 0 & 1 shares the same hash mapping table. + * Trunk group 2 uses a independent table. + */ +rtk_api_ret_t rtk_trunk_hashMappingTable_get(rtk_trunk_group_t trk_gid, rtk_trunk_hashVal2Port_t *pHash2Port_array) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->trunk_hashMappingTable_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->trunk_hashMappingTable_get(trk_gid, pHash2Port_array); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_trunk_portQueueEmpty_get + * Description: + * Get the port mask which all queues are empty. + * Input: + * None. + * Output: + * pEmpty_portmask - pointer empty port mask + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None. + */ +rtk_api_ret_t rtk_trunk_portQueueEmpty_get(rtk_portmask_t *pEmpty_portmask) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->trunk_portQueueEmpty_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->trunk_portQueueEmpty_get(pEmpty_portmask); + RTK_API_UNLOCK(); + + return retVal; +} + + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/trunk.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/trunk.h new file mode 100644 index 00000000..cb07236e --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/trunk.h @@ -0,0 +1,330 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8367/RTL8367C switch high-level API + * + * Feature : The file includes Trunk module high-layer TRUNK defination + * + */ + +#ifndef __RTK_API_TRUNK_H__ +#define __RTK_API_TRUNK_H__ + +/* + * Data Type Declaration + */ +#define RTK_TRUNK_DPORT_HASH_MASK 0x40 +#define RTK_TRUNK_SPORT_HASH_MASK 0x20 +#define RTK_TRUNK_DIP_HASH_MASK 0x10 +#define RTK_TRUNK_SIP_HASH_MASK 0x8 +#define RTK_TRUNK_DMAC_HASH_MASK 0x4 +#define RTK_TRUNK_SMAC_HASH_MASK 0x2 +#define RTK_TRUNK_SPA_HASH_MASK 0x1 + + +#define RTK_MAX_NUM_OF_TRUNK_HASH_VAL 16 + +typedef struct rtk_trunk_hashVal2Port_s +{ + rtk_uint8 value[RTK_MAX_NUM_OF_TRUNK_HASH_VAL]; +} rtk_trunk_hashVal2Port_t; + +typedef enum rtk_trunk_group_e +{ + TRUNK_GROUP0 = 0, + TRUNK_GROUP1, + TRUNK_GROUP2, + TRUNK_GROUP3, + TRUNK_GROUP_END +} rtk_trunk_group_t; + +typedef enum rtk_trunk_separateType_e +{ + SEPARATE_NONE = 0, + SEPARATE_FLOOD, + SEPARATE_END + +} rtk_trunk_separateType_t; + +typedef enum rtk_trunk_mode_e +{ + TRUNK_MODE_NORMAL = 0, + TRUNK_MODE_DUMB, + TRUNK_MODE_END +} rtk_trunk_mode_t; + +/* Function Name: + * rtk_trunk_port_set + * Description: + * Set trunking group available port mask + * Input: + * trk_gid - trunk group id + * pTrunk_member_portmask - Logic trunking member port mask + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_LA_TRUNK_ID - Invalid trunking group + * RT_ERR_PORT_MASK - Invalid portmask. + * Note: + * The API can set port trunking group port mask. Each port trunking group has max 4 ports. + * If enabled port mask has less than 2 ports available setting, then this trunking group function is disabled. + */ +extern rtk_api_ret_t rtk_trunk_port_set(rtk_trunk_group_t trk_gid, rtk_portmask_t *pTrunk_member_portmask); + +/* Function Name: + * rtk_trunk_port_get + * Description: + * Get trunking group available port mask + * Input: + * trk_gid - trunk group id + * Output: + * pTrunk_member_portmask - Logic trunking member port mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_LA_TRUNK_ID - Invalid trunking group + * Note: + * The API can get 2 port trunking group. + */ +extern rtk_api_ret_t rtk_trunk_port_get(rtk_trunk_group_t trk_gid, rtk_portmask_t *pTrunk_member_portmask); + +/* Function Name: + * rtk_trunk_distributionAlgorithm_set + * Description: + * Set port trunking hash select sources + * Input: + * trk_gid - trunk group id + * algo_bitmask - Bitmask of the distribution algorithm + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_LA_TRUNK_ID - Invalid trunking group + * RT_ERR_LA_HASHMASK - Hash algorithm selection error. + * RT_ERR_PORT_MASK - Invalid portmask. + * Note: + * The API can set port trunking hash algorithm sources. + * 7 bits mask for link aggregation group0 hash parameter selection {DIP, SIP, DMAC, SMAC, SPA} + * - 0b0000001: SPA + * - 0b0000010: SMAC + * - 0b0000100: DMAC + * - 0b0001000: SIP + * - 0b0010000: DIP + * - 0b0100000: TCP/UDP Source Port + * - 0b1000000: TCP/UDP Destination Port + * Example: + * - 0b0000011: SMAC & SPA + * - Note that it could be an arbitrary combination or independent set + */ +extern rtk_api_ret_t rtk_trunk_distributionAlgorithm_set(rtk_trunk_group_t trk_gid, rtk_uint32 algo_bitmask); + +/* Function Name: + * rtk_trunk_distributionAlgorithm_get + * Description: + * Get port trunking hash select sources + * Input: + * trk_gid - trunk group id + * Output: + * pAlgo_bitmask - Bitmask of the distribution algorithm + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_LA_TRUNK_ID - Invalid trunking group + * Note: + * The API can get port trunking hash algorithm sources. + */ +extern rtk_api_ret_t rtk_trunk_distributionAlgorithm_get(rtk_trunk_group_t trk_gid, rtk_uint32 *pAlgo_bitmask); + +/* Function Name: + * rtk_trunk_trafficSeparate_set + * Description: + * Set the traffic separation setting of a trunk group from the specified device. + * Input: + * trk_gid - trunk group id + * separateType - traffic separation setting + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_LA_TRUNK_ID - invalid trunk ID + * RT_ERR_LA_HASHMASK - invalid hash mask + * Note: + * SEPARATE_NONE: disable traffic separation + * SEPARATE_FLOOD: trunk MSB link up port is dedicated to TX flooding (L2 lookup miss) traffic + */ +extern rtk_api_ret_t rtk_trunk_trafficSeparate_set(rtk_trunk_group_t trk_gid, rtk_trunk_separateType_t separateType); + +/* Function Name: + * rtk_trunk_trafficSeparate_get + * Description: + * Get the traffic separation setting of a trunk group from the specified device. + * Input: + * trk_gid - trunk group id + * Output: + * pSeparateType - pointer separated traffic type + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_LA_TRUNK_ID - invalid trunk ID + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * SEPARATE_NONE: disable traffic separation + * SEPARATE_FLOOD: trunk MSB link up port is dedicated to TX flooding (L2 lookup miss) traffic + */ +extern rtk_api_ret_t rtk_trunk_trafficSeparate_get(rtk_trunk_group_t trk_gid, rtk_trunk_separateType_t *pSeparateType); + + +/* Function Name: + * rtk_trunk_mode_set + * Description: + * Set the trunk mode to the specified device. + * Input: + * mode - trunk mode + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT - invalid input parameter + * Note: + * The enum of the trunk mode as following + * - TRUNK_MODE_NORMAL + * - TRUNK_MODE_DUMB + */ +extern rtk_api_ret_t rtk_trunk_mode_set(rtk_trunk_mode_t mode); + +/* Function Name: + * rtk_trunk_mode_get + * Description: + * Get the trunk mode from the specified device. + * Input: + * None + * Output: + * pMode - pointer buffer of trunk mode + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * The enum of the trunk mode as following + * - TRUNK_MODE_NORMAL + * - TRUNK_MODE_DUMB + */ +extern rtk_api_ret_t rtk_trunk_mode_get(rtk_trunk_mode_t *pMode); + +/* Function Name: + * rtk_trunk_trafficPause_set + * Description: + * Set the traffic pause setting of a trunk group. + * Input: + * trk_gid - trunk group id + * enable - traffic pause state + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_LA_TRUNK_ID - invalid trunk ID + * Note: + * None. + */ +extern rtk_api_ret_t rtk_trunk_trafficPause_set(rtk_trunk_group_t trk_gid, rtk_enable_t enable); + +/* Function Name: + * rtk_trunk_trafficPause_get + * Description: + * Get the traffic pause setting of a trunk group. + * Input: + * trk_gid - trunk group id + * Output: + * pEnable - pointer of traffic pause state. + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_LA_TRUNK_ID - invalid trunk ID + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None. + */ +extern rtk_api_ret_t rtk_trunk_trafficPause_get(rtk_trunk_group_t trk_gid, rtk_enable_t *pEnable); + +/* Function Name: + * rtk_trunk_hashMappingTable_set + * Description: + * Set hash value to port array in the trunk group id from the specified device. + * Input: + * trk_gid - trunk group id + * pHash2Port_array - ports associate with the hash value + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_LA_TRUNK_ID - invalid trunk ID + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * RT_ERR_LA_TRUNK_NOT_EXIST - the trunk doesn't exist + * RT_ERR_LA_NOT_MEMBER_PORT - the port is not a member port of the trunk + * RT_ERR_LA_CPUPORT - CPU port can not be aggregated port + * Note: + * Trunk group 0 & 1 shares the same hash mapping table. + * Trunk group 2 uses a independent table. + */ +extern rtk_api_ret_t rtk_trunk_hashMappingTable_set(rtk_trunk_group_t trk_gid, rtk_trunk_hashVal2Port_t *pHash2Port_array); + +/* Function Name: + * rtk_trunk_hashMappingTable_get + * Description: + * Get hash value to port array in the trunk group id from the specified device. + * Input: + * trk_gid - trunk group id + * Output: + * pHash2Port_array - pointer buffer of ports associate with the hash value + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_LA_TRUNK_ID - invalid trunk ID + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * Trunk group 0 & 1 shares the same hash mapping table. + * Trunk group 2 uses a independent table. + */ +extern rtk_api_ret_t rtk_trunk_hashMappingTable_get(rtk_trunk_group_t trk_gid, rtk_trunk_hashVal2Port_t *pHash2Port_array); + +/* Function Name: + * rtk_trunk_portQueueEmpty_get + * Description: + * Get the port mask which all queues are empty. + * Input: + * None. + * Output: + * pEmpty_portmask - pointer empty port mask + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None. + */ +extern rtk_api_ret_t rtk_trunk_portQueueEmpty_get(rtk_portmask_t *pEmpty_portmask); + +#endif /* __RTK_API_TRUNK_H__ */ diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/vlan.c b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/vlan.c new file mode 100644 index 00000000..985baa58 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/vlan.c @@ -0,0 +1,1229 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8367C + * Feature : Here is a list of all functions and variables in VLAN module. + * + + */ + + + + + + + + + +#include +#include +#include +#include +#include + +#include + +/* Function Name: + * rtk_vlan_init + * Description: + * Initialize VLAN. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * VLAN is disabled by default. User has to call this API to enable VLAN before + * using it. And It will set a default VLAN(vid 1) including all ports and set + * all ports PVID to the default VLAN. + */ +rtk_api_ret_t rtk_vlan_init(void) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->vlan_init) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->vlan_init(); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_vlan_set + * Description: + * Set a VLAN entry. + * Input: + * vid - VLAN ID to configure. + * pVlanCfg - VLAN Configuration + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_L2_FID - Invalid FID. + * RT_ERR_VLAN_PORT_MBR_EXIST - Invalid member port mask. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * Note: + * + */ +rtk_api_ret_t rtk_vlan_set(rtk_vlan_t vid, rtk_vlan_cfg_t *pVlanCfg) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->vlan_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->vlan_set(vid, pVlanCfg); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_vlan_get + * Description: + * Get a VLAN entry. + * Input: + * vid - VLAN ID to configure. + * Output: + * pVlanCfg - VLAN Configuration + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * Note: + * + */ +rtk_api_ret_t rtk_vlan_get(rtk_vlan_t vid, rtk_vlan_cfg_t *pVlanCfg) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->vlan_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->vlan_get(vid, pVlanCfg); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_vlan_egrFilterEnable_set + * Description: + * Set VLAN egress filter. + * Input: + * egrFilter - Egress filtering + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid input parameters. + * Note: + * + */ +rtk_api_ret_t rtk_vlan_egrFilterEnable_set(rtk_enable_t egrFilter) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->vlan_egrFilterEnable_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->vlan_egrFilterEnable_set(egrFilter); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_vlan_egrFilterEnable_get + * Description: + * Get VLAN egress filter. + * Input: + * pEgrFilter - Egress filtering + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - NULL Pointer. + * Note: + * + */ +rtk_api_ret_t rtk_vlan_egrFilterEnable_get(rtk_enable_t *pEgrFilter) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->vlan_egrFilterEnable_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->vlan_egrFilterEnable_get(pEgrFilter); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_vlan_mbrCfg_set + * Description: + * Set a VLAN Member Configuration entry by index. + * Input: + * idx - Index of VLAN Member Configuration. + * pMbrcfg - VLAN member Configuration. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * Note: + * Set a VLAN Member Configuration entry by index. + */ +rtk_api_ret_t rtk_vlan_mbrCfg_set(rtk_uint32 idx, rtk_vlan_mbrcfg_t *pMbrcfg) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->vlan_mbrCfg_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->vlan_mbrCfg_set(idx, pMbrcfg); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_vlan_mbrCfg_get + * Description: + * Get a VLAN Member Configuration entry by index. + * Input: + * idx - Index of VLAN Member Configuration. + * Output: + * pMbrcfg - VLAN member Configuration. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * Note: + * Get a VLAN Member Configuration entry by index. + */ +rtk_api_ret_t rtk_vlan_mbrCfg_get(rtk_uint32 idx, rtk_vlan_mbrcfg_t *pMbrcfg) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->vlan_mbrCfg_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->vlan_mbrCfg_get(idx, pMbrcfg); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_vlan_portPvid_set + * Description: + * Set port to specified VLAN ID(PVID). + * Input: + * port - Port id. + * pvid - Specified VLAN ID. + * priority - 802.1p priority for the PVID. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_VLAN_PRIORITY - Invalid priority. + * RT_ERR_VLAN_ENTRY_NOT_FOUND - VLAN entry not found. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * Note: + * The API is used for Port-based VLAN. The untagged frame received from the + * port will be classified to the specified VLAN and assigned to the specified priority. + */ +rtk_api_ret_t rtk_vlan_portPvid_set(rtk_port_t port, rtk_vlan_t pvid, rtk_pri_t priority) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->vlan_portPvid_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->vlan_portPvid_set(port, pvid, priority); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_vlan_portPvid_get + * Description: + * Get VLAN ID(PVID) on specified port. + * Input: + * port - Port id. + * Output: + * pPvid - Specified VLAN ID. + * pPriority - 802.1p priority for the PVID. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get the PVID and 802.1p priority for the PVID of Port-based VLAN. + */ +rtk_api_ret_t rtk_vlan_portPvid_get(rtk_port_t port, rtk_vlan_t *pPvid, rtk_pri_t *pPriority) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->vlan_portPvid_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->vlan_portPvid_get(port, pPvid, pPriority); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_vlan_portIgrFilterEnable_set + * Description: + * Set VLAN ingress for each port. + * Input: + * port - Port id. + * igr_filter - VLAN ingress function enable status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * RT_ERR_ENABLE - Invalid enable input + * Note: + * The status of vlan ingress filter is as following: + * - DISABLED + * - ENABLED + * While VLAN function is enabled, ASIC will decide VLAN ID for each received frame and get belonged member + * ports from VLAN table. If received port is not belonged to VLAN member ports, ASIC will drop received frame if VLAN ingress function is enabled. + */ +rtk_api_ret_t rtk_vlan_portIgrFilterEnable_set(rtk_port_t port, rtk_enable_t igr_filter) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->vlan_portIgrFilterEnable_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->vlan_portIgrFilterEnable_set(port, igr_filter); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_vlan_portIgrFilterEnable_get + * Description: + * Get VLAN Ingress Filter + * Input: + * port - Port id. + * Output: + * pIgr_filter - VLAN ingress function enable status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can Get the VLAN ingress filter status. + * The status of vlan ingress filter is as following: + * - DISABLED + * - ENABLED + */ +rtk_api_ret_t rtk_vlan_portIgrFilterEnable_get(rtk_port_t port, rtk_enable_t *pIgr_filter) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->vlan_portIgrFilterEnable_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->vlan_portIgrFilterEnable_get(port, pIgr_filter); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_vlan_portAcceptFrameType_set + * Description: + * Set VLAN accept_frame_type + * Input: + * port - Port id. + * accept_frame_type - accept frame type + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_VLAN_ACCEPT_FRAME_TYPE - Invalid frame type. + * Note: + * The API is used for checking 802.1Q tagged frames. + * The accept frame type as following: + * - ACCEPT_FRAME_TYPE_ALL + * - ACCEPT_FRAME_TYPE_TAG_ONLY + * - ACCEPT_FRAME_TYPE_UNTAG_ONLY + */ +rtk_api_ret_t rtk_vlan_portAcceptFrameType_set(rtk_port_t port, rtk_vlan_acceptFrameType_t accept_frame_type) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->vlan_portAcceptFrameType_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->vlan_portAcceptFrameType_set(port, accept_frame_type); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_vlan_portAcceptFrameType_get + * Description: + * Get VLAN accept_frame_type + * Input: + * port - Port id. + * Output: + * pAccept_frame_type - accept frame type + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can Get the VLAN ingress filter. + * The accept frame type as following: + * - ACCEPT_FRAME_TYPE_ALL + * - ACCEPT_FRAME_TYPE_TAG_ONLY + * - ACCEPT_FRAME_TYPE_UNTAG_ONLY + */ +rtk_api_ret_t rtk_vlan_portAcceptFrameType_get(rtk_port_t port, rtk_vlan_acceptFrameType_t *pAccept_frame_type) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->vlan_portAcceptFrameType_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->vlan_portAcceptFrameType_get(port, pAccept_frame_type); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_vlan_protoAndPortBasedVlan_add + * Description: + * Add the protocol-and-port-based vlan to the specified port of device. + * Input: + * port - Port id. + * pInfo - Protocol and port based VLAN configuration information. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * RT_ERR_VLAN_PRIORITY - Invalid priority. + * RT_ERR_TBL_FULL - Table is full. + * RT_ERR_OUT_OF_RANGE - input out of range. + * Note: + * The incoming packet which match the protocol-and-port-based vlan will use the configure vid for ingress pipeline + * The frame type is shown in the following: + * - FRAME_TYPE_ETHERNET + * - FRAME_TYPE_RFC1042 + * - FRAME_TYPE_LLCOTHER + */ +rtk_api_ret_t rtk_vlan_protoAndPortBasedVlan_add(rtk_port_t port, rtk_vlan_protoAndPortInfo_t *pInfo) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->vlan_protoAndPortBasedVlan_add) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->vlan_protoAndPortBasedVlan_add(port, pInfo); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_vlan_protoAndPortBasedVlan_get + * Description: + * Get the protocol-and-port-based vlan to the specified port of device. + * Input: + * port - Port id. + * proto_type - protocol-and-port-based vlan protocol type. + * frame_type - protocol-and-port-based vlan frame type. + * Output: + * pInfo - Protocol and port based VLAN configuration information. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_TBL_FULL - Table is full. + * Note: + * The incoming packet which match the protocol-and-port-based vlan will use the configure vid for ingress pipeline + * The frame type is shown in the following: + * - FRAME_TYPE_ETHERNET + * - FRAME_TYPE_RFC1042 + * - FRAME_TYPE_LLCOTHER + */ +rtk_api_ret_t rtk_vlan_protoAndPortBasedVlan_get(rtk_port_t port, rtk_vlan_proto_type_t proto_type, rtk_vlan_protoVlan_frameType_t frame_type, rtk_vlan_protoAndPortInfo_t *pInfo) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->vlan_protoAndPortBasedVlan_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->vlan_protoAndPortBasedVlan_get(port, proto_type, frame_type, pInfo); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_vlan_protoAndPortBasedVlan_del + * Description: + * Delete the protocol-and-port-based vlan from the specified port of device. + * Input: + * port - Port id. + * proto_type - protocol-and-port-based vlan protocol type. + * frame_type - protocol-and-port-based vlan frame type. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_TBL_FULL - Table is full. + * Note: + * The incoming packet which match the protocol-and-port-based vlan will use the configure vid for ingress pipeline + * The frame type is shown in the following: + * - FRAME_TYPE_ETHERNET + * - FRAME_TYPE_RFC1042 + * - FRAME_TYPE_LLCOTHER + */ +rtk_api_ret_t rtk_vlan_protoAndPortBasedVlan_del(rtk_port_t port, rtk_vlan_proto_type_t proto_type, rtk_vlan_protoVlan_frameType_t frame_type) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->vlan_protoAndPortBasedVlan_del) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->vlan_protoAndPortBasedVlan_del(port, proto_type, frame_type); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_vlan_protoAndPortBasedVlan_delAll + * Description: + * Delete all protocol-and-port-based vlans from the specified port of device. + * Input: + * port - Port id. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_OUT_OF_RANGE - input out of range. + * Note: + * The incoming packet which match the protocol-and-port-based vlan will use the configure vid for ingress pipeline + * Delete all flow table protocol-and-port-based vlan entries. + */ +rtk_api_ret_t rtk_vlan_protoAndPortBasedVlan_delAll(rtk_port_t port) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->vlan_protoAndPortBasedVlan_delAll) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->vlan_protoAndPortBasedVlan_delAll(port); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_vlan_tagMode_set + * Description: + * Set CVLAN egress tag mode + * Input: + * port - Port id. + * tag_mode - The egress tag mode. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * The API can set Egress tag mode. There are 4 mode for egress tag: + * - VLAN_TAG_MODE_ORIGINAL, + * - VLAN_TAG_MODE_KEEP_FORMAT, + * - VLAN_TAG_MODE_PRI. + * - VLAN_TAG_MODE_REAL_KEEP_FORMAT, + */ +rtk_api_ret_t rtk_vlan_tagMode_set(rtk_port_t port, rtk_vlan_tagMode_t tag_mode) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->vlan_tagMode_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->vlan_tagMode_set(port, tag_mode); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_vlan_tagMode_get + * Description: + * Get CVLAN egress tag mode + * Input: + * port - Port id. + * Output: + * pTag_mode - The egress tag mode. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get Egress tag mode. There are 4 mode for egress tag: + * - VLAN_TAG_MODE_ORIGINAL, + * - VLAN_TAG_MODE_KEEP_FORMAT, + * - VLAN_TAG_MODE_PRI. + * - VLAN_TAG_MODE_REAL_KEEP_FORMAT, + */ +rtk_api_ret_t rtk_vlan_tagMode_get(rtk_port_t port, rtk_vlan_tagMode_t *pTag_mode) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->vlan_tagMode_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->vlan_tagMode_get(port, pTag_mode); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_vlan_transparent_set + * Description: + * Set VLAN transparent mode + * Input: + * egr_port - Egress Port id. + * pIgr_pmask - Ingress Port Mask. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * None. + */ +rtk_api_ret_t rtk_vlan_transparent_set(rtk_port_t egr_port, rtk_portmask_t *pIgr_pmask) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->vlan_transparent_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->vlan_transparent_set(egr_port, pIgr_pmask); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_vlan_transparent_get + * Description: + * Get VLAN transparent mode + * Input: + * egr_port - Egress Port id. + * Output: + * pIgr_pmask - Ingress Port Mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * None. + */ +rtk_api_ret_t rtk_vlan_transparent_get(rtk_port_t egr_port, rtk_portmask_t *pIgr_pmask) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->vlan_transparent_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->vlan_transparent_get(egr_port, pIgr_pmask); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_vlan_keep_set + * Description: + * Set VLAN egress keep mode + * Input: + * egr_port - Egress Port id. + * pIgr_pmask - Ingress Port Mask. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * None. + */ +rtk_api_ret_t rtk_vlan_keep_set(rtk_port_t egr_port, rtk_portmask_t *pIgr_pmask) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->vlan_keep_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->vlan_keep_set(egr_port, pIgr_pmask); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_vlan_keep_get + * Description: + * Get VLAN egress keep mode + * Input: + * egr_port - Egress Port id. + * Output: + * pIgr_pmask - Ingress Port Mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * None. + */ +rtk_api_ret_t rtk_vlan_keep_get(rtk_port_t egr_port, rtk_portmask_t *pIgr_pmask) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->vlan_keep_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->vlan_keep_get(egr_port, pIgr_pmask); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_vlan_stg_set + * Description: + * Set spanning tree group instance of the vlan to the specified device + * Input: + * vid - Specified VLAN ID. + * stg - spanning tree group instance. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_MSTI - Invalid msti parameter + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * Note: + * The API can set spanning tree group instance of the vlan to the specified device. + */ +rtk_api_ret_t rtk_vlan_stg_set(rtk_vlan_t vid, rtk_stp_msti_id_t stg) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->vlan_stg_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->vlan_stg_set(vid, stg); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_vlan_stg_get + * Description: + * Get spanning tree group instance of the vlan to the specified device + * Input: + * vid - Specified VLAN ID. + * Output: + * pStg - spanning tree group instance. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * Note: + * The API can get spanning tree group instance of the vlan to the specified device. + */ +rtk_api_ret_t rtk_vlan_stg_get(rtk_vlan_t vid, rtk_stp_msti_id_t *pStg) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->vlan_stg_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->vlan_stg_get(vid, pStg); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_vlan_portFid_set + * Description: + * Set port-based filtering database + * Input: + * port - Port id. + * enable - ebable port-based FID + * fid - Specified filtering database. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_FID - Invalid fid. + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API can set port-based filtering database. If the function is enabled, all input + * packets will be assigned to the port-based fid regardless vlan tag. + */ +rtk_api_ret_t rtk_vlan_portFid_set(rtk_port_t port, rtk_enable_t enable, rtk_fid_t fid) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->vlan_portFid_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->vlan_portFid_set(port, enable, fid); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_vlan_portFid_get + * Description: + * Get port-based filtering database + * Input: + * port - Port id. + * Output: + * pEnable - ebable port-based FID + * pFid - Specified filtering database. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API can get port-based filtering database status. If the function is enabled, all input + * packets will be assigned to the port-based fid regardless vlan tag. + */ +rtk_api_ret_t rtk_vlan_portFid_get(rtk_port_t port, rtk_enable_t *pEnable, rtk_fid_t *pFid) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->vlan_portFid_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->vlan_portFid_get(port, pEnable, pFid); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_vlan_UntagDscpPriorityEnable_set + * Description: + * Set Untag DSCP priority assign + * Input: + * enable - state of Untag DSCP priority assign + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid input parameters. + * Note: + * + */ +rtk_api_ret_t rtk_vlan_UntagDscpPriorityEnable_set(rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->vlan_UntagDscpPriorityEnable_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->vlan_UntagDscpPriorityEnable_set(enable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_vlan_UntagDscpPriorityEnable_get + * Description: + * Get Untag DSCP priority assign + * Input: + * None + * Output: + * pEnable - state of Untag DSCP priority assign + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * + */ +rtk_api_ret_t rtk_vlan_UntagDscpPriorityEnable_get(rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->vlan_UntagDscpPriorityEnable_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->vlan_UntagDscpPriorityEnable_get(pEnable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_stp_mstpState_set + * Description: + * Configure spanning tree state per each port. + * Input: + * port - Port id + * msti - Multiple spanning tree instance. + * stp_state - Spanning tree state for msti + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_MSTI - Invalid msti parameter. + * RT_ERR_MSTP_STATE - Invalid STP state. + * Note: + * System supports per-port multiple spanning tree state for each msti. + * There are four states supported by ASIC. + * - STP_STATE_DISABLED + * - STP_STATE_BLOCKING + * - STP_STATE_LEARNING + * - STP_STATE_FORWARDING + */ +rtk_api_ret_t rtk_stp_mstpState_set(rtk_stp_msti_id_t msti, rtk_port_t port, rtk_stp_state_t stp_state) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->stp_mstpState_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->stp_mstpState_set(msti, port, stp_state); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_stp_mstpState_get + * Description: + * Get spanning tree state per each port. + * Input: + * port - Port id. + * msti - Multiple spanning tree instance. + * Output: + * pStp_state - Spanning tree state for msti + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_MSTI - Invalid msti parameter. + * Note: + * System supports per-port multiple spanning tree state for each msti. + * There are four states supported by ASIC. + * - STP_STATE_DISABLED + * - STP_STATE_BLOCKING + * - STP_STATE_LEARNING + * - STP_STATE_FORWARDING + */ +rtk_api_ret_t rtk_stp_mstpState_get(rtk_stp_msti_id_t msti, rtk_port_t port, rtk_stp_state_t *pStp_state) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->stp_mstpState_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->stp_mstpState_get(msti, port, pStp_state); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_vlan_reservedVidAction_set + * Description: + * Set Action of VLAN ID = 0 & 4095 tagged packet + * Input: + * action_vid0 - Action for VID 0. + * action_vid4095 - Action for VID 4095. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + * + */ +rtk_api_ret_t rtk_vlan_reservedVidAction_set(rtk_vlan_resVidAction_t action_vid0, rtk_vlan_resVidAction_t action_vid4095) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->vlan_reservedVidAction_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->vlan_reservedVidAction_set(action_vid0, action_vid4095); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_vlan_reservedVidAction_get + * Description: + * Get Action of VLAN ID = 0 & 4095 tagged packet + * Input: + * pAction_vid0 - Action for VID 0. + * pAction_vid4095 - Action for VID 4095. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - NULL Pointer + * Note: + * + */ +rtk_api_ret_t rtk_vlan_reservedVidAction_get(rtk_vlan_resVidAction_t *pAction_vid0, rtk_vlan_resVidAction_t *pAction_vid4095) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->vlan_reservedVidAction_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->vlan_reservedVidAction_get(pAction_vid0, pAction_vid4095); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_vlan_realKeepRemarkEnable_set + * Description: + * Set Real keep 1p remarking feature + * Input: + * enabled - State of 1p remarking at real keep packet + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + * + */ +rtk_api_ret_t rtk_vlan_realKeepRemarkEnable_set(rtk_enable_t enabled) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->vlan_realKeepRemarkEnable_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->vlan_realKeepRemarkEnable_set(enabled); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_vlan_realKeepRemarkEnable_get + * Description: + * Get Real keep 1p remarking feature + * Input: + * None. + * Output: + * pEnabled - State of 1p remarking at real keep packet + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + * + */ +rtk_api_ret_t rtk_vlan_realKeepRemarkEnable_get(rtk_enable_t *pEnabled) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->vlan_realKeepRemarkEnable_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->vlan_realKeepRemarkEnable_get(pEnabled); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_vlan_reset + * Description: + * Reset VLAN + * Input: + * None. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + * + */ +rtk_api_ret_t rtk_vlan_reset(void) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->vlan_reset) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->vlan_reset(); + RTK_API_UNLOCK(); + + return retVal; +} + diff --git a/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/vlan.h b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/vlan.h new file mode 100644 index 00000000..21695395 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8367_common_V1_4_2/vlan.h @@ -0,0 +1,874 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8367/RTL8367C switch high-level API + * + * Feature : The file includes Trap module high-layer VLAN defination + * + */ + +#ifndef __RTK_API_VLAN_H__ +#define __RTK_API_VLAN_H__ + + +/* + * Data Type Declaration + */ +#define RTK_MAX_NUM_OF_PROTO_TYPE 0xFFFF +#define RTK_MAX_NUM_OF_MSTI 0xF +#define RTK_FID_MAX 0xF + +typedef struct rtk_vlan_cfg_s +{ + rtk_portmask_t mbr; + rtk_portmask_t untag; + rtk_uint16 ivl_en; + rtk_uint16 fid_msti; + rtk_uint16 envlanpol; + rtk_uint16 meteridx; + rtk_uint16 vbpen; + rtk_uint16 vbpri; +}rtk_vlan_cfg_t; + +typedef struct rtk_vlan_mbrcfg_s +{ + rtk_uint16 evid; + rtk_portmask_t mbr; + rtk_uint16 fid_msti; + rtk_uint16 envlanpol; + rtk_uint16 meteridx; + rtk_uint16 vbpen; + rtk_uint16 vbpri; +}rtk_vlan_mbrcfg_t; + +typedef rtk_uint32 rtk_stp_msti_id_t; /* MSTI ID */ + +typedef enum rtk_stp_state_e +{ + STP_STATE_DISABLED = 0, + STP_STATE_BLOCKING, + STP_STATE_LEARNING, + STP_STATE_FORWARDING, + STP_STATE_END +} rtk_stp_state_t; + +typedef rtk_uint32 rtk_vlan_proto_type_t; /* protocol and port based VLAN protocol type */ + + +typedef enum rtk_vlan_acceptFrameType_e +{ + ACCEPT_FRAME_TYPE_ALL = 0, /* untagged, priority-tagged and tagged */ + ACCEPT_FRAME_TYPE_TAG_ONLY, /* tagged */ + ACCEPT_FRAME_TYPE_UNTAG_ONLY, /* untagged and priority-tagged */ + ACCEPT_FRAME_TYPE_END +} rtk_vlan_acceptFrameType_t; + + +/* frame type of protocol vlan - reference 802.1v standard */ +typedef enum rtk_vlan_protoVlan_frameType_e +{ + FRAME_TYPE_ETHERNET = 0, + FRAME_TYPE_LLCOTHER, + FRAME_TYPE_RFC1042, + FRAME_TYPE_END +} rtk_vlan_protoVlan_frameType_t; + +/* Protocol-and-port-based Vlan structure */ +typedef struct rtk_vlan_protoAndPortInfo_s +{ + rtk_uint32 proto_type; + rtk_vlan_protoVlan_frameType_t frame_type; + rtk_vlan_t cvid; + rtk_pri_t cpri; +}rtk_vlan_protoAndPortInfo_t; + +/* tagged mode of VLAN - reference realtek private specification */ +typedef enum rtk_vlan_tagMode_e +{ + VLAN_TAG_MODE_ORIGINAL = 0, + VLAN_TAG_MODE_KEEP_FORMAT, + VLAN_TAG_MODE_PRI, + VLAN_TAG_MODE_REAL_KEEP_FORMAT, + VLAN_TAG_MODE_END +} rtk_vlan_tagMode_t; + +typedef enum rtk_vlan_resVidAction_e +{ + RESVID_ACTION_UNTAG = 0, + RESVID_ACTION_TAG, + RESVID_ACTION_END +} +rtk_vlan_resVidAction_t; + +/* Function Name: + * rtk_vlan_init + * Description: + * Initialize VLAN. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * VLAN is disabled by default. User has to call this API to enable VLAN before + * using it. And It will set a default VLAN(vid 1) including all ports and set + * all ports PVID to the default VLAN. + */ +extern rtk_api_ret_t rtk_vlan_init(void); + +/* Function Name: + * rtk_vlan_set + * Description: + * Set a VLAN entry. + * Input: + * vid - VLAN ID to configure. + * pVlanCfg - VLAN Configuration + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_L2_FID - Invalid FID. + * RT_ERR_VLAN_PORT_MBR_EXIST - Invalid member port mask. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * Note: + * + */ +extern rtk_api_ret_t rtk_vlan_set(rtk_vlan_t vid, rtk_vlan_cfg_t *pVlanCfg); + +/* Function Name: + * rtk_vlan_get + * Description: + * Get a VLAN entry. + * Input: + * vid - VLAN ID to configure. + * Output: + * pVlanCfg - VLAN Configuration + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * Note: + * + */ +extern rtk_api_ret_t rtk_vlan_get(rtk_vlan_t vid, rtk_vlan_cfg_t *pVlanCfg); + +/* Function Name: + * rtk_vlan_egrFilterEnable_set + * Description: + * Set VLAN egress filter. + * Input: + * egrFilter - Egress filtering + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid input parameters. + * Note: + * + */ +extern rtk_api_ret_t rtk_vlan_egrFilterEnable_set(rtk_enable_t egrFilter); + +/* Function Name: + * rtk_vlan_egrFilterEnable_get + * Description: + * Get VLAN egress filter. + * Input: + * pEgrFilter - Egress filtering + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - NULL Pointer. + * Note: + * + */ +extern rtk_api_ret_t rtk_vlan_egrFilterEnable_get(rtk_enable_t *pEgrFilter); + +/* Function Name: + * rtk_vlan_mbrCfg_set + * Description: + * Set a VLAN Member Configuration entry by index. + * Input: + * idx - Index of VLAN Member Configuration. + * pMbrcfg - VLAN member Configuration. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * Note: + * Set a VLAN Member Configuration entry by index. + */ +extern rtk_api_ret_t rtk_vlan_mbrCfg_set(rtk_uint32 idx, rtk_vlan_mbrcfg_t *pMbrcfg); + +/* Function Name: + * rtk_vlan_mbrCfg_get + * Description: + * Get a VLAN Member Configuration entry by index. + * Input: + * idx - Index of VLAN Member Configuration. + * Output: + * pMbrcfg - VLAN member Configuration. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * Note: + * Get a VLAN Member Configuration entry by index. + */ +extern rtk_api_ret_t rtk_vlan_mbrCfg_get(rtk_uint32 idx, rtk_vlan_mbrcfg_t *pMbrcfg); + +/* Function Name: + * rtk_vlan_portPvid_set + * Description: + * Set port to specified VLAN ID(PVID). + * Input: + * port - Port id. + * pvid - Specified VLAN ID. + * priority - 802.1p priority for the PVID. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_VLAN_PRIORITY - Invalid priority. + * RT_ERR_VLAN_ENTRY_NOT_FOUND - VLAN entry not found. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * Note: + * The API is used for Port-based VLAN. The untagged frame received from the + * port will be classified to the specified VLAN and assigned to the specified priority. + */ +extern rtk_api_ret_t rtk_vlan_portPvid_set(rtk_port_t port, rtk_vlan_t pvid, rtk_pri_t priority); + +/* Function Name: + * rtk_vlan_portPvid_get + * Description: + * Get VLAN ID(PVID) on specified port. + * Input: + * port - Port id. + * Output: + * pPvid - Specified VLAN ID. + * pPriority - 802.1p priority for the PVID. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get the PVID and 802.1p priority for the PVID of Port-based VLAN. + */ +extern rtk_api_ret_t rtk_vlan_portPvid_get(rtk_port_t port, rtk_vlan_t *pPvid, rtk_pri_t *pPriority); + +/* Function Name: + * rtk_vlan_portIgrFilterEnable_set + * Description: + * Set VLAN ingress for each port. + * Input: + * port - Port id. + * igr_filter - VLAN ingress function enable status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * RT_ERR_ENABLE - Invalid enable input + * Note: + * The status of vlan ingress filter is as following: + * - DISABLED + * - ENABLED + * While VLAN function is enabled, ASIC will decide VLAN ID for each received frame and get belonged member + * ports from VLAN table. If received port is not belonged to VLAN member ports, ASIC will drop received frame if VLAN ingress function is enabled. + */ +extern rtk_api_ret_t rtk_vlan_portIgrFilterEnable_set(rtk_port_t port, rtk_enable_t igr_filter); + +/* Function Name: + * rtk_vlan_portIgrFilterEnable_get + * Description: + * Get VLAN Ingress Filter + * Input: + * port - Port id. + * Output: + * pIgr_filter - VLAN ingress function enable status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can Get the VLAN ingress filter status. + * The status of vlan ingress filter is as following: + * - DISABLED + * - ENABLED + */ +extern rtk_api_ret_t rtk_vlan_portIgrFilterEnable_get(rtk_port_t port, rtk_enable_t *pIgr_filter); + +/* Function Name: + * rtk_vlan_portAcceptFrameType_set + * Description: + * Set VLAN accept_frame_type + * Input: + * port - Port id. + * accept_frame_type - accept frame type + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_VLAN_ACCEPT_FRAME_TYPE - Invalid frame type. + * Note: + * The API is used for checking 802.1Q tagged frames. + * The accept frame type as following: + * - ACCEPT_FRAME_TYPE_ALL + * - ACCEPT_FRAME_TYPE_TAG_ONLY + * - ACCEPT_FRAME_TYPE_UNTAG_ONLY + */ +extern rtk_api_ret_t rtk_vlan_portAcceptFrameType_set(rtk_port_t port, rtk_vlan_acceptFrameType_t accept_frame_type); + +/* Function Name: + * rtk_vlan_portAcceptFrameType_get + * Description: + * Get VLAN accept_frame_type + * Input: + * port - Port id. + * Output: + * pAccept_frame_type - accept frame type + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can Get the VLAN ingress filter. + * The accept frame type as following: + * - ACCEPT_FRAME_TYPE_ALL + * - ACCEPT_FRAME_TYPE_TAG_ONLY + * - ACCEPT_FRAME_TYPE_UNTAG_ONLY + */ +extern rtk_api_ret_t rtk_vlan_portAcceptFrameType_get(rtk_port_t port, rtk_vlan_acceptFrameType_t *pAccept_frame_type); + +/* Function Name: + * rtk_vlan_tagMode_set + * Description: + * Set CVLAN egress tag mode + * Input: + * port - Port id. + * tag_mode - The egress tag mode. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * The API can set Egress tag mode. There are 4 mode for egress tag: + * - VLAN_TAG_MODE_ORIGINAL, + * - VLAN_TAG_MODE_KEEP_FORMAT, + * - VLAN_TAG_MODE_PRI. + * - VLAN_TAG_MODE_REAL_KEEP_FORMAT, + */ +extern rtk_api_ret_t rtk_vlan_tagMode_set(rtk_port_t port, rtk_vlan_tagMode_t tag_mode); + +/* Function Name: + * rtk_vlan_tagMode_get + * Description: + * Get CVLAN egress tag mode + * Input: + * port - Port id. + * Output: + * pTag_mode - The egress tag mode. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get Egress tag mode. There are 4 mode for egress tag: + * - VLAN_TAG_MODE_ORIGINAL, + * - VLAN_TAG_MODE_KEEP_FORMAT, + * - VLAN_TAG_MODE_PRI. + * - VLAN_TAG_MODE_REAL_KEEP_FORMAT, + */ +extern rtk_api_ret_t rtk_vlan_tagMode_get(rtk_port_t port, rtk_vlan_tagMode_t *pTag_mode); + +/* Function Name: + * rtk_vlan_transparent_set + * Description: + * Set VLAN transparent mode + * Input: + * egr_port - Egress Port id. + * pIgr_pmask - Ingress Port Mask. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * None. + */ +extern rtk_api_ret_t rtk_vlan_transparent_set(rtk_port_t egr_port, rtk_portmask_t *pIgr_pmask); + +/* Function Name: + * rtk_vlan_transparent_get + * Description: + * Get VLAN transparent mode + * Input: + * egr_port - Egress Port id. + * Output: + * pIgr_pmask - Ingress Port Mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * None. + */ +extern rtk_api_ret_t rtk_vlan_transparent_get(rtk_port_t egr_port, rtk_portmask_t *pIgr_pmask); + +/* Function Name: + * rtk_vlan_keep_set + * Description: + * Set VLAN egress keep mode + * Input: + * egr_port - Egress Port id. + * pIgr_pmask - Ingress Port Mask. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * None. + */ +extern rtk_api_ret_t rtk_vlan_keep_set(rtk_port_t egr_port, rtk_portmask_t *pIgr_pmask); + +/* Function Name: + * rtk_vlan_keep_get + * Description: + * Get VLAN egress keep mode + * Input: + * egr_port - Egress Port id. + * Output: + * pIgr_pmask - Ingress Port Mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * None. + */ +extern rtk_api_ret_t rtk_vlan_keep_get(rtk_port_t egr_port, rtk_portmask_t *pIgr_pmask); + +/* Function Name: + * rtk_vlan_stg_set + * Description: + * Set spanning tree group instance of the vlan to the specified device + * Input: + * vid - Specified VLAN ID. + * stg - spanning tree group instance. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_MSTI - Invalid msti parameter + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * Note: + * The API can set spanning tree group instance of the vlan to the specified device. + */ +extern rtk_api_ret_t rtk_vlan_stg_set(rtk_vlan_t vid, rtk_stp_msti_id_t stg); + +/* Function Name: + * rtk_vlan_stg_get + * Description: + * Get spanning tree group instance of the vlan to the specified device + * Input: + * vid - Specified VLAN ID. + * Output: + * pStg - spanning tree group instance. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * Note: + * The API can get spanning tree group instance of the vlan to the specified device. + */ +extern rtk_api_ret_t rtk_vlan_stg_get(rtk_vlan_t vid, rtk_stp_msti_id_t *pStg); + +/* Function Name: + * rtk_vlan_protoAndPortBasedVlan_add + * Description: + * Add the protocol-and-port-based vlan to the specified port of device. + * Input: + * port - Port id. + * pInfo - Protocol and port based VLAN configuration information. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * RT_ERR_VLAN_PRIORITY - Invalid priority. + * RT_ERR_TBL_FULL - Table is full. + * RT_ERR_OUT_OF_RANGE - input out of range. + * Note: + * The incoming packet which match the protocol-and-port-based vlan will use the configure vid for ingress pipeline + * The frame type is shown in the following: + * - FRAME_TYPE_ETHERNET + * - FRAME_TYPE_RFC1042 + * - FRAME_TYPE_LLCOTHER + */ +extern rtk_api_ret_t rtk_vlan_protoAndPortBasedVlan_add(rtk_port_t port, rtk_vlan_protoAndPortInfo_t *pInfo); + +/* Function Name: + * rtk_vlan_protoAndPortBasedVlan_get + * Description: + * Get the protocol-and-port-based vlan to the specified port of device. + * Input: + * port - Port id. + * proto_type - protocol-and-port-based vlan protocol type. + * frame_type - protocol-and-port-based vlan frame type. + * Output: + * pInfo - Protocol and port based VLAN configuration information. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_TBL_FULL - Table is full. + * Note: + * The incoming packet which match the protocol-and-port-based vlan will use the configure vid for ingress pipeline + * The frame type is shown in the following: + * - FRAME_TYPE_ETHERNET + * - FRAME_TYPE_RFC1042 + * - FRAME_TYPE_LLCOTHER + */ +extern rtk_api_ret_t rtk_vlan_protoAndPortBasedVlan_get(rtk_port_t port, rtk_vlan_proto_type_t proto_type, rtk_vlan_protoVlan_frameType_t frame_type, rtk_vlan_protoAndPortInfo_t *pInfo); + +/* Function Name: + * rtk_vlan_protoAndPortBasedVlan_del + * Description: + * Delete the protocol-and-port-based vlan from the specified port of device. + * Input: + * port - Port id. + * proto_type - protocol-and-port-based vlan protocol type. + * frame_type - protocol-and-port-based vlan frame type. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_TBL_FULL - Table is full. + * Note: + * The incoming packet which match the protocol-and-port-based vlan will use the configure vid for ingress pipeline + * The frame type is shown in the following: + * - FRAME_TYPE_ETHERNET + * - FRAME_TYPE_RFC1042 + * - FRAME_TYPE_LLCOTHER + */ +extern rtk_api_ret_t rtk_vlan_protoAndPortBasedVlan_del(rtk_port_t port, rtk_vlan_proto_type_t proto_type, rtk_vlan_protoVlan_frameType_t frame_type); + +/* Function Name: + * rtk_vlan_protoAndPortBasedVlan_delAll + * Description: + * Delete all protocol-and-port-based vlans from the specified port of device. + * Input: + * port - Port id. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_OUT_OF_RANGE - input out of range. + * Note: + * The incoming packet which match the protocol-and-port-based vlan will use the configure vid for ingress pipeline + * Delete all flow table protocol-and-port-based vlan entries. + */ +extern rtk_api_ret_t rtk_vlan_protoAndPortBasedVlan_delAll(rtk_port_t port); + +/* Function Name: + * rtk_vlan_portFid_set + * Description: + * Set port-based filtering database + * Input: + * port - Port id. + * enable - ebable port-based FID + * fid - Specified filtering database. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_FID - Invalid fid. + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API can set port-based filtering database. If the function is enabled, all input + * packets will be assigned to the port-based fid regardless vlan tag. + */ +extern rtk_api_ret_t rtk_vlan_portFid_set(rtk_port_t port, rtk_enable_t enable, rtk_fid_t fid); + +/* Function Name: + * rtk_vlan_portFid_get + * Description: + * Get port-based filtering database + * Input: + * port - Port id. + * Output: + * pEnable - ebable port-based FID + * pFid - Specified filtering database. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API can get port-based filtering database status. If the function is enabled, all input + * packets will be assigned to the port-based fid regardless vlan tag. + */ +extern rtk_api_ret_t rtk_vlan_portFid_get(rtk_port_t port, rtk_enable_t *pEnable, rtk_fid_t *pFid); + +/* Function Name: + * rtk_vlan_UntagDscpPriorityEnable_set + * Description: + * Set Untag DSCP priority assign + * Input: + * enable - state of Untag DSCP priority assign + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid input parameters. + * Note: + * + */ +extern rtk_api_ret_t rtk_vlan_UntagDscpPriorityEnable_set(rtk_enable_t enable); + +/* Function Name: + * rtk_vlan_UntagDscpPriorityEnable_get + * Description: + * Get Untag DSCP priority assign + * Input: + * None + * Output: + * pEnable - state of Untag DSCP priority assign + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * + */ +extern rtk_api_ret_t rtk_vlan_UntagDscpPriorityEnable_get(rtk_enable_t *pEnable); + + +/*Spanning Tree*/ +/* Function Name: + * rtk_stp_mstpState_set + * Description: + * Configure spanning tree state per each port. + * Input: + * port - Port id + * msti - Multiple spanning tree instance. + * stp_state - Spanning tree state for msti + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_MSTI - Invalid msti parameter. + * RT_ERR_MSTP_STATE - Invalid STP state. + * Note: + * System supports per-port multiple spanning tree state for each msti. + * There are four states supported by ASIC. + * - STP_STATE_DISABLED + * - STP_STATE_BLOCKING + * - STP_STATE_LEARNING + * - STP_STATE_FORWARDING + */ +extern rtk_api_ret_t rtk_stp_mstpState_set(rtk_stp_msti_id_t msti, rtk_port_t port, rtk_stp_state_t stp_state); + +/* Function Name: + * rtk_stp_mstpState_get + * Description: + * Get spanning tree state per each port. + * Input: + * port - Port id. + * msti - Multiple spanning tree instance. + * Output: + * pStp_state - Spanning tree state for msti + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_MSTI - Invalid msti parameter. + * Note: + * System supports per-port multiple spanning tree state for each msti. + * There are four states supported by ASIC. + * - STP_STATE_DISABLED + * - STP_STATE_BLOCKING + * - STP_STATE_LEARNING + * - STP_STATE_FORWARDING + */ +extern rtk_api_ret_t rtk_stp_mstpState_get(rtk_stp_msti_id_t msti, rtk_port_t port, rtk_stp_state_t *pStp_state); + +/* Function Name: + * rtk_vlan_reservedVidAction_set + * Description: + * Set Action of VLAN ID = 0 & 4095 tagged packet + * Input: + * action_vid0 - Action for VID 0. + * action_vid4095 - Action for VID 4095. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + * + */ +extern rtk_api_ret_t rtk_vlan_reservedVidAction_set(rtk_vlan_resVidAction_t action_vid0, rtk_vlan_resVidAction_t action_vid4095); + +/* Function Name: + * rtk_vlan_reservedVidAction_get + * Description: + * Get Action of VLAN ID = 0 & 4095 tagged packet + * Input: + * pAction_vid0 - Action for VID 0. + * pAction_vid4095 - Action for VID 4095. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - NULL Pointer + * Note: + * + */ +extern rtk_api_ret_t rtk_vlan_reservedVidAction_get(rtk_vlan_resVidAction_t *pAction_vid0, rtk_vlan_resVidAction_t *pAction_vid4095); + +/* Function Name: + * rtk_vlan_realKeepRemarkEnable_set + * Description: + * Set Real keep 1p remarking feature + * Input: + * enabled - State of 1p remarking at real keep packet + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + * + */ +extern rtk_api_ret_t rtk_vlan_realKeepRemarkEnable_set(rtk_enable_t enabled); + +/* Function Name: + * rtk_vlan_realKeepRemarkEnable_get + * Description: + * Get Real keep 1p remarking feature + * Input: + * None. + * Output: + * pEnabled - State of 1p remarking at real keep packet + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + * + */ +extern rtk_api_ret_t rtk_vlan_realKeepRemarkEnable_get(rtk_enable_t *pEnabled); + +/* Function Name: + * rtk_vlan_reset + * Description: + * Reset VLAN + * Input: + * None. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + * + */ +rtk_api_ret_t rtk_vlan_reset(void); + +#endif /* __RTK_API_VLAN_H__ */ diff --git a/sources/uboot-be550/drivers/net/rtl8372/Makefile b/sources/uboot-be550/drivers/net/rtl8372/Makefile new file mode 100644 index 00000000..b2597045 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/Makefile @@ -0,0 +1,19 @@ +LOC_DIR=src/hsl/phy/rtl8372 +LIB=HSL + +include $(PRJ_PATH)/make/config.mk + +SRC_LIST= + +ifeq (TRUE, $(IN_RTL8372_PHY)) +SRC_LIST += acl.c cpuTag.c dot1x.c gpio.c identify.c interrupt.c l2.c macsec.c miim.c nic.c port.c qos.c rldp.c rtk_switch.c storm.c trunk.c \ + chip.c dos.c eee.c i2c.c igmp.c isolation.c led.c mib.c mirror.c phy_rtl8224.c ptp.c rate.c rma.c sharemeter.c svlan.c vlan.c + +EXTRA_CFLAGS += -DMDC_MDIO_OPERATION +endif + +include $(PRJ_PATH)/make/components.mk +include $(PRJ_PATH)/make/defs.mk +include $(PRJ_PATH)/make/target.mk + +all: dep obj diff --git a/sources/uboot-be550/drivers/net/rtl8372/acl.c b/sources/uboot-be550/drivers/net/rtl8372/acl.c new file mode 100755 index 00000000..cc6fca67 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/acl.c @@ -0,0 +1,821 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8373 + * Feature : Here is a list of all functions and variables in ACL module. + * + */ + +#include +#include +#include +#include +#include +#include + +#include + +/* Function Name: + * rtk_filter_igrAcl_init + * Description: + * ACL initialization function + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Pointer pFilter_field or pFilter_cfg point to NULL. + * Note: + * This function enable and intialize ACL function + */ +rtk_api_ret_t rtk_filter_igrAcl_init(void) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->filter_igrAcl_init) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->filter_igrAcl_init(); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_filter_igrAcl_field_add + * Description: + * Add comparison rule to an ACL configuration + * Input: + * pFilterCfg - The ACL configuration that this function will add comparison rule + * pFilterField - The comparison rule that will be added. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Pointer pFilter_field or pFilter_cfg point to NULL. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This function add a comparison rule (*pFilter_field) to an ACL configuration (*pFilter_cfg). + * Pointer pFilter_cfg points to an ACL configuration structure, this structure keeps multiple ACL + * comparison rules by means of linked list. Pointer pFilter_field will be added to linked + * list keeped by structure that pFilter_cfg points to. + */ +rtk_api_ret_t rtk_filter_igrAcl_field_add(rtk_filter_cfg_t* pFilterCfg, rtk_filter_field_t* pFilterField) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->filter_igrAcl_field_add) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->filter_igrAcl_field_add(pFilterCfg, pFilterField); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_filter_igrAcl_cfg_add + * Description: + * Add an ACL configuration to ASIC + * Input: + * filterId - Start index of ACL configuration. + * pFilterCfg - The ACL configuration that this function will add comparison rule + * pFilterAction - Action(s) of ACL configuration. + * Output: + * ruleNum - number of rules written in acl table + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Pointer pFilter_field or pFilter_cfg point to NULL. + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_ENTRY_INDEX - Invalid filter_id . + * RT_ERR_NULL_POINTER - Pointer pFilter_action or pFilter_cfg point to NULL. + * RT_ERR_FILTER_INACL_ACT_NOT_SUPPORT - Action is not supported in this chip. + * RT_ERR_FILTER_INACL_RULE_NOT_SUPPORT - Rule is not supported. + * Note: + * This function store pFilter_cfg, pFilter_action into ASIC. The starting + * index(es) is filter_id. + */ +rtk_api_ret_t rtk_filter_igrAcl_cfg_add(rtk_filter_id_t filterId, rtk_filter_cfg_t* pFilterCfg, rtk_filter_action_t* pFilterAction, rtk_filter_number_t *ruleNum) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->filter_igrAcl_cfg_add) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->filter_igrAcl_cfg_add(filterId, pFilterCfg, pFilterAction, ruleNum); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_filter_igrAcl_cfg_del + * Description: + * Delete an ACL configuration from ASIC + * Input: + * filterId - Start index of ACL configuration. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_ENTRYIDX - Invalid filter_id. + * Note: + * This function delete a group of ACL rules starting from filter_id. + */ +rtk_api_ret_t rtk_filter_igrAcl_cfg_del(rtk_filter_id_t filterId) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->filter_igrAcl_cfg_del) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->filter_igrAcl_cfg_del(filterId); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_filter_igrAcl_cfg_delAll + * Description: + * Delete all ACL entries from ASIC + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This function delete all ACL configuration from ASIC. + */ +rtk_api_ret_t rtk_filter_igrAcl_cfg_delAll(void) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->filter_igrAcl_cfg_delAll) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->filter_igrAcl_cfg_delAll(); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_filter_igrAcl_cfg_get + * Description: + * Get one ingress acl configuration from ASIC. + * Input: + * filterId - Start index of ACL configuration. + * Output: + * pFilterCfg - buffer pointer of ingress acl data + * pFilter_action - buffer pointer of ingress acl action + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Pointer pFilter_action or pFilter_cfg point to NULL. + * RT_ERR_FILTER_ENTRYIDX - Invalid entry index. + * Note: + * This function get configuration from ASIC. + */ +rtk_api_ret_t rtk_filter_igrAcl_cfg_get(rtk_filter_id_t filterId, rtk_filter_cfg_raw_t *pFilterCfg, rtk_filter_action_t *pAction) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->filter_igrAcl_cfg_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->filter_igrAcl_cfg_get(filterId, pFilterCfg, pAction); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_filter_igrAcl_unmatchAction_set + * Description: + * Set action to packets when no ACL configuration match + * Input: + * port - Port id. + * action - Action. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port id. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This function sets action of packets when no ACL configruation matches. + */ +rtk_api_ret_t rtk_filter_igrAcl_unmatchAction_set(rtk_port_t port, rtk_filter_unmatch_action_t action) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->filter_igrAcl_unmatchAction_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->filter_igrAcl_unmatchAction_set(port, action); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_filter_igrAcl_unmatchAction_get + * Description: + * Get action to packets when no ACL configuration match + * Input: + * port - Port id. + * Output: + * pAction - Action. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port id. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This function gets action of packets when no ACL configruation matches. + */ +rtk_api_ret_t rtk_filter_igrAcl_unmatchAction_get(rtk_port_t port, rtk_filter_unmatch_action_t* pAction) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->filter_igrAcl_unmatchAction_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->filter_igrAcl_unmatchAction_get(port, pAction); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_filter_igrAcl_state_set + * Description: + * Set state of ingress ACL. + * Input: + * port - Port id. + * state - Ingress ACL state. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port id. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This function gets action of packets when no ACL configruation matches. + */ +rtk_api_ret_t rtk_filter_igrAcl_state_set(rtk_port_t port, rtk_filter_state_t state) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->filter_igrAcl_state_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->filter_igrAcl_state_set(port, state); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_filter_igrAcl_state_get + * Description: + * Get state of ingress ACL. + * Input: + * port - Port id. + * Output: + * pState - Ingress ACL state. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port id. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This function gets action of packets when no ACL configruation matches. + */ +rtk_api_ret_t rtk_filter_igrAcl_state_get(rtk_port_t port, rtk_filter_state_t* pState) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->filter_igrAcl_state_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->filter_igrAcl_state_get(port, pState); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_filter_igrAcl_template_set + * Description: + * Set template of ingress ACL. + * Input: + * template - Ingress ACL template + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This function set ACL template. + */ +rtk_api_ret_t rtk_filter_igrAcl_template_set(rtk_filter_template_t *aclTemplate) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->filter_igrAcl_template_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->filter_igrAcl_template_set(aclTemplate); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_filter_igrAcl_template_get + * Description: + * Get template of ingress ACL. + * Input: + * template - Ingress ACL template + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This function gets template of ACL. + */ +rtk_api_ret_t rtk_filter_igrAcl_template_get(rtk_filter_template_t *aclTemplate) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->filter_igrAcl_template_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->filter_igrAcl_template_get(aclTemplate); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_filter_igrAcl_field_sel_set + * Description: + * Set user defined field selectors in HSB + * Input: + * index - index of field selector 0-15 + * format - Format of field selector + * offset - Retrieving data offset + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * System support 16 user defined field selctors. + * Each selector can be enabled or disable. + * User can defined retrieving 16-bits in many predefiend + * standard l2/l3/l4 payload. + */ +rtk_api_ret_t rtk_filter_igrAcl_field_sel_set(rtk_uint32 index, rtk_field_sel_t format, rtk_uint32 offset) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->filter_igrAcl_field_sel_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->filter_igrAcl_field_sel_set(index, format, offset); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_filter_igrAcl_field_sel_get + * Description: + * Get user defined field selectors in HSB + * Input: + * index - index of field selector 0-15 + * Output: + * pFormat - Format of field selector + * pOffset - Retrieving data offset + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * None. + */ +rtk_api_ret_t rtk_filter_igrAcl_field_sel_get(rtk_uint32 index, rtk_field_sel_t *pFormat, rtk_uint32 *pOffset) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->filter_igrAcl_field_sel_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->filter_igrAcl_field_sel_get(index, pFormat, pOffset); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_filter_iprange_set + * Description: + * Set IP Range check + * Input: + * index - index of IP Range 0-15 + * type - IP Range check type, 0:Delete a entry, 1: IPv4_SIP, 2: IPv4_DIP, 3:IPv6_SIP, 4:IPv6_DIP + * upperIp - The upper bound of IP range + * lowerIp - The lower Bound of IP range + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - The parameter is out of range + * RT_ERR_INPUT - Input error + * Note: + * upperIp must be larger or equal than lowerIp. + */ +rtk_api_ret_t rtk_filter_iprange_set(rtk_uint32 index, rtk_filter_iprange_t type, ipaddr_t upperIp, ipaddr_t lowerIp) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->filter_iprange_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->filter_iprange_set(index, type, upperIp, lowerIp); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_filter_iprange_get + * Description: + * Set IP Range check + * Input: + * index - index of IP Range 0-15 + * Output: + * pType - IP Range check type, 0:Delete a entry, 1: IPv4_SIP, 2: IPv4_DIP, 3:IPv6_SIP, 4:IPv6_DIP + * pUpperIp - The upper bound of IP range + * pLowerIp - The lower Bound of IP range + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - The parameter is out of range + * Note: + * None. + */ +rtk_api_ret_t rtk_filter_iprange_get(rtk_uint32 index, rtk_filter_iprange_t *pType, ipaddr_t *pUpperIp, ipaddr_t *pLowerIp) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->filter_iprange_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->filter_iprange_get(index, pType, pUpperIp, pLowerIp); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_filter_vidrange_set + * Description: + * Set VID Range check + * Input: + * index - index of VID Range 0-15 + * type - IP Range check type, 0:Delete a entry, 1: CVID, 2: SVID + * upperVid - The upper bound of VID range + * lowerVid - The lower Bound of VID range + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - The parameter is out of range + * RT_ERR_INPUT - Input error + * Note: + * upperVid must be larger or equal than lowerVid. + */ +rtk_api_ret_t rtk_filter_vidrange_set(rtk_uint32 index, rtk_filter_vidrange_t type, rtk_uint32 upperVid, rtk_uint32 lowerVid) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->filter_vidrange_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->filter_vidrange_set(index, type, upperVid, lowerVid); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_filter_vidrange_get + * Description: + * Get VID Range check + * Input: + * index - index of VID Range 0-15 + * Output: + * pType - IP Range check type, 0:Unused, 1: CVID, 2: SVID + * pUpperVid - The upper bound of VID range + * pLowerVid - The lower Bound of VID range + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - The parameter is out of range + * Note: + * None. + */ +rtk_api_ret_t rtk_filter_vidrange_get(rtk_uint32 index, rtk_filter_vidrange_t *pType, rtk_uint32 *pUpperVid, rtk_uint32 *pLowerVid) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->filter_vidrange_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->filter_vidrange_get(index, pType, pUpperVid, pLowerVid); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_filter_portrange_set + * Description: + * Set Port Range check + * Input: + * index - index of Port Range 0-15 + * type - IP Range check type, 0:Delete a entry, 1: Source Port, 2: Destnation Port + * upperPort - The upper bound of Port range + * lowerPort - The lower Bound of Port range + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - The parameter is out of range + * RT_ERR_INPUT - Input error + * Note: + * upperPort must be larger or equal than lowerPort. + */ +rtk_api_ret_t rtk_filter_portrange_set(rtk_uint32 index, rtk_filter_portrange_t type, rtk_uint32 upperPort, rtk_uint32 lowerPort) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->filter_portrange_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->filter_portrange_set(index, type, upperPort, lowerPort); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_filter_portrange_get + * Description: + * Set Port Range check + * Input: + * index - index of Port Range 0-15 + * Output: + * pType - IP Range check type, 0:Delete a entry, 1: Source Port, 2: Destnation Port + * pUpperPort - The upper bound of Port range + * pLowerPort - The lower Bound of Port range + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - The parameter is out of range + * RT_ERR_INPUT - Input error + * Note: + * None. + */ +rtk_api_ret_t rtk_filter_portrange_get(rtk_uint32 index, rtk_filter_portrange_t *pType, rtk_uint32 *pUpperPort, rtk_uint32 *pLowerPort) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->filter_portrange_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->filter_portrange_get(index, pType, pUpperPort, pLowerPort); + RTK_API_UNLOCK(); + + return retVal; + +} +/* Function Name: + * rtk_filter_igrAcl_gpioPolarity_set + * Description: + * Set ACL Goip control palarity + * Input: + * polarity - 1: High, 0: Low + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * none + */ +rtk_api_ret_t rtk_filter_igrAcl_gpioPolarity_set(rtk_uint32 polarity) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->filter_igrAcl_gpioPolarity_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->filter_igrAcl_gpioPolarity_set(polarity); + RTK_API_UNLOCK(); + + return retVal; +} +/* Function Name: + * rtk_filter_igrAcl_gpioPolarity_get + * Description: + * Get ACL Goip control palarity + * Input: + * pPolarity - 1: High, 0: Low + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * none + */ +rtk_api_ret_t rtk_filter_igrAcl_gpioPolarity_get(rtk_uint32* pPolarity) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->filter_igrAcl_gpioPolarity_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->filter_igrAcl_gpioPolarity_get(pPolarity); + RTK_API_UNLOCK(); + + return retVal; + +} + +/* Function Name: + * rtk_filter_igrAcl_gpioEn_set + * Description: + * Set acl gpio pin status + * Input: + * gpioPinNum - gpio pin number (0~3) + * enabled - acl gpio pin enable or not + * Output: + * none - + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - The parameter is out of range + * RT_ERR_INPUT - Input error + * Note: + * None. + */ +rtk_api_ret_t rtk_filter_igrAcl_gpioEn_set(rtk_uint32 gpioPinNum, rtk_enable_t enabled) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->filter_igrAcl_gpioEn_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->filter_igrAcl_gpioEn_set(gpioPinNum, enabled); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_filter_igrAcl_gpioEn_get + * Description: + * Get acl gpio pin status + * Input: + * gpioPinNum - gpio pin number (0~3) + * Output: + * *pEnabled - acl gpio pin status + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - The parameter is out of range + * RT_ERR_INPUT - Input error + * Note: + * None. + */ +rtk_api_ret_t rtk_filter_igrAcl_gpioEn_get(rtk_uint32 gpioPinNum, rtk_enable_t *pEnabled) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->filter_igrAcl_gpioEn_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->filter_igrAcl_gpioEn_get(gpioPinNum, pEnabled); + RTK_API_UNLOCK(); + + return retVal; +} + + +/******************************************************************************* +* Function Name: +* rtk_filter_igrAcl_table_Reset +* Description: +* Table reset: both reset acl rule and action +*Input: +* None +*Output: +* None +*Return: +* RT_ERR_OK - OK +* RT_ERR_FAILED - Failed +* RT_ERR_PORT_ID - Error port number +* RT_ERR_ENABLE - Error action +*Note: None +*******************************************************************************/ +rtk_api_ret_t rtk_filter_igrAcl_table_Reset(void) +{ + rtk_api_ret_t retVal = 0; + + if (NULL == RT_MAPPER->filter_igrAcl_tbl_rst) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->filter_igrAcl_tbl_rst(); + RTK_API_UNLOCK(); + + return retVal; + +} + diff --git a/sources/uboot-be550/drivers/net/rtl8372/acl.h b/sources/uboot-be550/drivers/net/rtl8372/acl.h new file mode 100755 index 00000000..951ffbb1 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/acl.h @@ -0,0 +1,1093 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8373 switch high-level API + * + * Feature : The file includes ACL module high-layer API defination + * + */ + +#ifndef __RTK_API_ACL_H__ +#define __RTK_API_ACL_H__ + +/* + * Data Type Declaration + */ +#define RTK_FILTER_RAW_FIELD_NUMBER (8) + +#define ACL_DEFAULT_ABILITY (0) +#define ACL_DEFAULT_UNMATCH_PERMIT (1) + +#define SHARED_METER_NUM (64) +#define ACL_RULE_FREE (0) +#define ACL_RULE_INAVAILABLE (1) +#define ACL_RULE_CARETAG_MASK (0x1F) +#define FILTER_POLICING_MAX (3) +#define FILTER_LOGGING_MAX (SHARED_METER_NUM-1) +#define FILTER_PATTERN_MAX (4) +#define ACL_RULE_TAG_MASK (0x7) +#define ACL_RULE_L3FMT_MASK (0x3) +#define ACL_RULE_L4FMT_MASK (0x7) +#define ACL_GPIO_ACT_PINNUM_MAX (0x4) + + + +#define FILTER_ENACT_CVLAN_MASK (0x01) +#define FILTER_ENACT_SVLAN_MASK (0x02) +#define FILTER_ENACT_PRIORITY_MASK (0x04) +#define FILTER_ENACT_RMK_MASK (0x08) +#define FILTER_ENACT_POLICING_LOGG_MASK (0x10) +#define FILTER_ENACT_FWD_MASK (0x20) +#define FILTER_ENACT_INTGPIO_MASK (0x40) +#define FILTER_ENACT_BYPASS_MASK (0x80) +#define FILTER_ENACT_ALL_MASK (0xFF) + +typedef enum rtk_filter_act_cactext_e +{ + FILTER_ENACT_CACTEXT_VLANONLY=0, + FILTER_ENACT_CACTEXT_BOTHVLANTAG, + FILTER_ENACT_CACTEXT_TAGONLY, + FILTER_ENACT_CACTEXT_END, +}rtk_filter_act_cactext_t; + +typedef enum rtk_filter_act_ctagfmt_e{ + FILTER_CTAGFMT_UNTAG=0, + FILTER_CTAGFMT_TAG, + FILTER_CTAGFMT_KEEP, + FILTER_CTAGFMT_KEEP1PRMK, +}rtk_filter_act_ctag_t; + + +#define RTK_MAX_NUM_OF_FILTER_TYPE (5) +#define RTK_MAX_NUM_OF_FILTER_FIELD (8) + +#define RTK_DOT_1AS_TIMESTAMP_UNIT_IN_WORD_LENGTH (3UL) +#define RTK_IPV6_ADDR_WORD_LENGTH (4UL) + +#define FILTER_ENACT_CVLAN_TYPE(type) (type - FILTER_ENACT_CVLAN_INGRESS) +#define FILTER_ENACT_SVLAN_TYPE(type) (type - FILTER_ENACT_SVLAN_INGRESS) +#define FILTER_ENACT_FWD_TYPE(type) (type - FILTER_ENACT_ADD_DSTPORT) +#define FILTER_ENACT_PRI_TYPE(type) (type - FILTER_ENACT_PRIORITY) + +#define RTK_FILTER_FIELD_USED_MAX (8) +#define RTK_FILTER_FIELD_INDEX(template, index) ((template << 4) + index) + + +typedef enum rtk_filter_act_enable_e +{ + /* CVLAN */ + FILTER_ENACT_CVLAN_INGRESS = 0, + FILTER_ENACT_CVLAN_EGRESS, + FILTER_ENACT_CVLAN_SVID, + FILTER_ENACT_POLICING_1, + + /* SVLAN */ + FILTER_ENACT_SVLAN_INGRESS, + FILTER_ENACT_SVLAN_EGRESS, + FILTER_ENACT_SVLAN_CVID, + FILTER_ENACT_POLICING_2, + + /*acl priority*/ + FILTER_ENACT_PRIORITY, + + /*1P remarking*/ + FILTER_ENACT_1P_RMK, + + /*DSCP remarking*/ + FILTER_ENACT_DSCP_RMK, + + /*Policing --shared meterr*/ + FILTER_ENACT_POLICING_0, + + /* Logging Counter*/ + FILTER_ENACT_LOGGING_CNTR, + + /* Forward */ + FILTER_ENACT_ADD_DSTPORT, + FILTER_ENACT_REDIRECT, + FILTER_ENACT_MIRROR, + FILTER_ENACT_TRAP_INT_CPU, + FILTER_ENACT_TRAP_EXT_CPU, + FILTER_ENACT_TRAP_INT_EXT_CPU, + FILTER_ENACT_ISOLATION, + FILTER_ENACT_DROP, + + /* Interrutp and GPO */ + FILTER_ENACT_INTERRUPT, + FILTER_ENACT_GPO, + + /*VLAN tag*/ + FILTER_ENACT_EGRESSCTAG_UNTAG, + FILTER_ENACT_EGRESSCTAG_TAG, + FILTER_ENACT_EGRESSCTAG_REALKEEP, + FILTER_ENACT_EGRESSCTAG_KEEPAND1PRMK, + + /* Bypass action */ + FILTER_ENACT_BYPASS_IGRBW_STORMCTRL, + FILTER_ENACT_BYPASS_STP_SRC_CHK, + FILTER_ENACT_BYPASS_IGRVLAN_FLTR, + + FILTER_ENACT_END, +} rtk_filter_act_enable_t; + +typedef enum rtk_filter_act_bypass_e +{ + FILTER_BYPASS_IGR_BANDWIDTH_STORM_CTRL=0, + FILTER_BYPASS_STP_SRC_CHECK, + FILTER_BYPASS_INGRESS_VLAN_FILTER, + FILTER_BYPASS_END, +}rtk_filter_act_bypass_t; + +typedef enum rtk_filter_care_tag_index_e +{ + /*ToDo*/ + CARE_TAG_CTAG = 0, + CARE_TAG_STAG, + CARE_TAG_PPPOE, + CARE_TAG_IPV4, + CARE_TAG_IPV6, + CARE_TAG_TCP, + CARE_TAG_UDP, + CARE_TAG_ARP, + CARE_TAG_RSV1, + CARE_TAG_RSV2, + CARE_TAG_ICMP, + CARE_TAG_IGMP, + CARE_TAG_LLC, + CARE_TAG_RSV3, + CARE_TAG_HTTP, + CARE_TAG_RSV4, + CARE_TAG_RSV5, + CARE_TAG_DHCP, + CARE_TAG_DHCPV6, + CARE_TAG_SNMP, + CARE_TAG_OAM, + CARE_TAG_END, +} rtk_filter_care_tag_index_t; + +typedef enum rtk_filter_field_data_type_e +{ + FILTER_FIELD_DATA_MASK = 0, + FILTER_FIELD_DATA_RANGE, + FILTER_FIELD_DATA_END , +} rtk_filter_field_data_type_t; + +typedef enum rtk_filter_field_temple_input_e +{ + FILTER_FIELD_TEMPLE_INPUT_TYPE = 0, + FILTER_FIELD_TEMPLE_INPUT_INDEX, + FILTER_FIELD_TEMPLE_INPUT_MAX , +} rtk_filter_field_temple_input_t; + +typedef enum rtk_filter_field_type_e +{ + FILTER_FIELD_DMAC = 0, + FILTER_FIELD_SMAC, + FILTER_FIELD_ETHERTYPE, + FILTER_FIELD_CTAG, + FILTER_FIELD_STAG, + + FILTER_FIELD_IPV4_SIP, + FILTER_FIELD_IPV4_DIP, + FILTER_FIELD_SENDER_PROTOCOL_ADDR, + FILTER_FIELD_TARGET_PROTOCOL_ADDR, + + FILTER_FIELD_IPV4_TOS, + FILTER_FIELD_IPV4_PROTOCOL, + //FILTER_FIELD_IPV4_FLAG, + //FILTER_FIELD_IPV4_OFFSET, + + FILTER_FIELD_IPV6_SIPV6, + FILTER_FIELD_IPV6_DIPV6, + FILTER_FIELD_IPV6_TRAFFIC_CLASS, + FILTER_FIELD_IPV6_NEXT_HEADER, + + FILTER_FIELD_AFTER_ETHTYPE_BYTE01, + FILTER_FIELD_ARP_RARP_CODE, + + FILTER_FIELD_TCP_UDP_SPORT, + FILTER_FIELD_TCP_UDP_DPORT, + //FILTER_FIELD_TCP_FLAG, + + FILTER_FIELD_ICMP_IGMP_CODE, + FILTER_FIELD_ICMP_IGMP_TYPE, + + FILTER_FIELD_L4HEADER_BYTE01, + FILTER_FIELD_L4HEADER_BYTE23, + + FILTER_FIELD_VID_RANGE, + FILTER_FIELD_IP_RANGE, + FILTER_FIELD_PORT_RANGE, + FILTER_FIELD_PATTERN_MATCH, + + FILTER_FIELD_USER_DEFINED00, + FILTER_FIELD_USER_DEFINED01, + FILTER_FIELD_USER_DEFINED02, + FILTER_FIELD_USER_DEFINED03, + FILTER_FIELD_USER_DEFINED04, + FILTER_FIELD_USER_DEFINED05, + FILTER_FIELD_USER_DEFINED06, + FILTER_FIELD_USER_DEFINED07, + FILTER_FIELD_USER_DEFINED08, + FILTER_FIELD_USER_DEFINED09, + FILTER_FIELD_USER_DEFINED10, + FILTER_FIELD_USER_DEFINED11, + FILTER_FIELD_USER_DEFINED12, + FILTER_FIELD_USER_DEFINED13, + FILTER_FIELD_USER_DEFINED14, + FILTER_FIELD_USER_DEFINED15, + + FILTER_FIELD_END, +} rtk_filter_field_type_t; + +typedef enum rtk_filter_field_type_raw_e +{ + FILTER_FIELD_RAW_DMAC_15_0 = 0, + FILTER_FIELD_RAW_DMAC_31_16, + FILTER_FIELD_RAW_DMAC_47_32, + FILTER_FIELD_RAW_SMAC_15_0, + FILTER_FIELD_RAW_SMAC_31_16, + FILTER_FIELD_RAW_SMAC_47_32, + FILTER_FIELD_RAW_ETHERTYPE, + FILTER_FIELD_RAW_STAG, + FILTER_FIELD_RAW_CTAG, + + FILTER_FIELD_RAW_SIP_15_0 = 0x10, + FILTER_FIELD_RAW_SIP_31_16, + FILTER_FIELD_RAW_DIP_15_0, + FILTER_FIELD_RAW_DIP_31_16, + + FILTER_FIELD_RAW_VIDRANGE = 0x30, + FILTER_FIELD_RAW_IPRANGE, + FILTER_FIELD_RAW_PORTRANGE, + FILTER_FIELD_RAW_FIELD_VALID, + FILTER_FIELD_RAW_IPTOSPROTO, + FILTER_FIELD_RAW_L4SPORT, + FILTER_FIELD_RAW_L4DPORT, + + FILTER_FIELD_RAW_FIELD_SELECT00 = 0x40, + FILTER_FIELD_RAW_FIELD_SELECT01, + FILTER_FIELD_RAW_FIELD_SELECT02, + FILTER_FIELD_RAW_FIELD_SELECT03, + FILTER_FIELD_RAW_FIELD_SELECT04, + FILTER_FIELD_RAW_FIELD_SELECT05, + FILTER_FIELD_RAW_FIELD_SELECT06, + FILTER_FIELD_RAW_FIELD_SELECT07, + FILTER_FIELD_RAW_FIELD_SELECT08, + FILTER_FIELD_RAW_FIELD_SELECT09, + FILTER_FIELD_RAW_FIELD_SELECT10, + FILTER_FIELD_RAW_FIELD_SELECT11, + FILTER_FIELD_RAW_FIELD_SELECT12, + FILTER_FIELD_RAW_FIELD_SELECT13, + FILTER_FIELD_RAW_FIELD_SELECT14, + FILTER_FIELD_RAW_FIELD_SELECT15, + + FILTER_FIELD_RAW_END= 0x60, +} rtk_filter_field_type_raw_t; + +typedef enum rtk_filter_flag_care_type_e +{ + FILTER_FLAG_CARE_DONT_CARE = 0, + FILTER_FLAG_CARE_1, + FILTER_FLAG_CARE_0, + FILTER_FLAG_END +} rtk_filter_flag_care_type_t; + +typedef enum rtk_field_sel_e +{ + FORMAT_DEFAULT = 0, + FORMAT_RAW, + FORMAT_LLC, + FORMAT_IPV4, + FORMAT_ARP, + FORMAT_IPV6, + FORMAT_IPPAYLOAD, + FORMAT_L4PAYLOAD, + FORMAT_END +}rtk_field_sel_t; + +typedef enum rtk_filter_iprange_e +{ + IPRANGE_UNUSED = 0, + IPRANGE_IPV4_SIP, + IPRANGE_IPV4_DIP, + IPRANGE_IPV6_SIP_PREFIX, + IPRANGE_IPV6_DIP_PREFIX, + IPRANGE_END +}rtk_filter_iprange_t; + +typedef enum rtk_filter_vidrange_e +{ + VIDRANGE_UNUSED = 0, + VIDRANGE_CVID, + VIDRANGE_SVID, + VIDRANGE_END +}rtk_filter_vidrange_t; + +typedef enum rtk_filter_portrange_e +{ + PORTRANGE_UNUSED = 0, + PORTRANGE_SPORT, + PORTRANGE_DPORT, + PORTRANGE_END +}rtk_filter_portrange_t; + +typedef enum rtk_filter_invert_e +{ + FILTER_INVERT_DISABLE = 0, + FILTER_INVERT_ENABLE, + FILTER_INVERT_END, +} rtk_filter_invert_t; + +typedef enum rtk_filter_unmatch_action_e +{ + FILTER_UNMATCH_DROP = 0, + FILTER_UNMATCH_PERMIT, + FILTER_UNMATCH_END, +} rtk_filter_unmatch_action_type_t; + +typedef struct +{ + rtk_filter_act_enable_t actEnable[FILTER_ENACT_END]; + + /* CVLAN acton */ + rtk_uint32 filterCvlanVid; + /* SVLAN action */ + rtk_uint32 filterSvlanVid; + + /*acl priority*/ + rtk_uint32 filterAclPri; + + /*1P remarking*/ + rtk_uint32 filter1pRmk; + + /*DSCP remarking*/ + rtk_uint32 filterDscpRmk; + + /*Shared meter*/ + rtk_uint32 filterPolicingIdx[FILTER_POLICING_MAX]; + + /* Logging Counter*/ + rtk_uint32 filterLoggCntr; + + /* Forwarding action */ + rtk_portmask_t filterPortmask; + + /*GPO*/ + rtk_uint32 filterPin; +} rtk_filter_action_t; + +typedef struct rtk_filter_flag_s +{ + rtk_uint32 value; + rtk_uint32 mask; +} rtk_filter_flag_t; + +typedef struct rtk_filter_care_tag_s +{ + rtk_filter_flag_t tagType[CARE_TAG_END]; +} rtk_filter_care_tag_t; + +typedef struct rtk_filter_field rtk_filter_field_t; + +typedef struct +{ + rtk_uint32 value[RTK_DOT_1AS_TIMESTAMP_UNIT_IN_WORD_LENGTH]; +} rtk_filter_dot1as_timestamp_t; + +typedef struct rtk_filter_ip_s +{ + rtk_uint32 dataType; + rtk_uint32 rangeStart; + rtk_uint32 rangeEnd; + rtk_uint32 value; + rtk_uint32 mask; +} rtk_filter_ip_t; + +typedef struct rtk_filter_mac_s +{ + rtk_uint32 dataType; + rtk_mac_t value; + rtk_mac_t mask; + rtk_mac_t rangeStart; + rtk_mac_t rangeEnd; +} rtk_filter_mac_t; + +typedef rtk_uint32 rtk_filter_op_t; + +typedef struct rtk_filter_value_s +{ + rtk_uint32 dataType; + rtk_uint32 value; + rtk_uint32 mask; + rtk_uint32 rangeStart; + rtk_uint32 rangeEnd; + +} rtk_filter_value_t; + +typedef struct rtk_filter_activeport_s +{ + rtk_portmask_t value; + rtk_portmask_t mask; + +} rtk_filter_activeport_t; + +typedef struct rtk_filter_tag_s +{ + rtk_filter_value_t pri; + rtk_filter_flag_t cfi; + rtk_filter_value_t vid; +} rtk_filter_tag_t; + +typedef struct rtk_filter_ipFlag_s +{ + rtk_filter_flag_t xf; + rtk_filter_flag_t mf; + rtk_filter_flag_t df; +} rtk_filter_ipFlag_t; + +typedef struct +{ + rtk_uint32 addr[RTK_IPV6_ADDR_WORD_LENGTH]; +} rtk_filter_ip6_addr_t; + +typedef struct +{ + rtk_uint32 dataType; + rtk_filter_ip6_addr_t value; + rtk_filter_ip6_addr_t mask; + rtk_filter_ip6_addr_t rangeStart; + rtk_filter_ip6_addr_t rangeEnd; +} rtk_filter_ip6_t; + +typedef rtk_uint32 rtk_filter_number_t; + +typedef struct rtk_filter_pattern_s +{ + rtk_uint32 value[FILTER_PATTERN_MAX]; + rtk_uint32 mask[FILTER_PATTERN_MAX]; +} rtk_filter_pattern_t; + +typedef struct rtk_filter_tcpFlag_s +{ + rtk_filter_flag_t urg; + rtk_filter_flag_t ack; + rtk_filter_flag_t psh; + rtk_filter_flag_t rst; + rtk_filter_flag_t syn; + rtk_filter_flag_t fin; + rtk_filter_flag_t cwr; + rtk_filter_flag_t ece; + rtk_filter_flag_t ns; +} rtk_filter_tcpFlag_t; + +typedef rtk_uint16 rtk_filter_field_raw_t; + +struct rtk_filter_field +{ + rtk_uint32 fieldType; + + union + { + /* L2 struct */ + rtk_filter_mac_t dmac; + rtk_filter_mac_t smac; + rtk_filter_value_t etherType; + rtk_filter_tag_t ctag; + rtk_filter_tag_t relayCtag; + rtk_filter_tag_t stag; + rtk_filter_tag_t l2tag; + rtk_filter_dot1as_timestamp_t dot1asTimeStamp; + rtk_filter_mac_t mac; + + /* L3 struct */ + rtk_filter_ip_t sip; + rtk_filter_ip_t dip; + rtk_filter_ip_t ip; + rtk_filter_ip6_t sipv6; + rtk_filter_ip6_t dipv6; + rtk_filter_ip6_t ipv6; + + rtk_filter_value_t afterEthertypeByte0_1; + + rtk_filter_value_t ipTos; + rtk_filter_value_t ipv6TrafficClass; + rtk_filter_value_t protocol; + rtk_filter_value_t ipv6NextHeader; + + rtk_filter_ipFlag_t ipv4Flag; + rtk_filter_value_t ipv4FragmentOffset; +// rtk_filter_value_t ipv4TTL; + +// rtk_filter_value_t ipv4TTLipv6HopLimit; +// rtk_filter_value_t flowLabel; +// rtk_filter_value_t ipv6Res_M; + + rtk_filter_value_t arpRarpOpcode; + + /* L4 struct */ + rtk_filter_value_t tcpUdpSrcPort; + rtk_filter_value_t tcpUdpDstPort; + // rtk_filter_tcpFlag_t tcpFlag; + // rtk_filter_value_t tcpSeqNumber; + // rtk_filter_value_t tcpAckNumber; + + rtk_filter_value_t icmpIgmpCode; + rtk_filter_value_t icmpIgmpType; + + rtk_filter_value_t l4headerByte0_1; + rtk_filter_value_t l4headerByte2_3; + + /* pattern match */ + rtk_filter_value_t inData; + + } filter_pattern_union; + + rtk_uint32 occupyFieldNum; + rtk_uint32 fieldTemplateIdx[RTK_FILTER_FIELD_USED_MAX]; + + struct rtk_filter_field *next; +}; + +typedef rtk_uint32 rtk_filter_id_t; /* filter id type */ + +typedef rtk_uint32 rtk_filter_state_t; + +typedef rtk_uint32 rtk_filter_unmatch_action_t; +typedef struct rtk_filter_frametype_s +{ + rtk_uint32 value; + rtk_uint32 mask; +} rtk_filter_frametype_t; + +typedef struct +{ + rtk_filter_field_t *fieldHead; + rtk_filter_care_tag_t careTag; + rtk_filter_activeport_t activeport; + rtk_filter_frametype_t l3fmt; + rtk_filter_frametype_t l4fmt; + rtk_filter_invert_t invert; +} rtk_filter_cfg_t; + +typedef struct +{ + rtk_filter_field_raw_t dataFieldRaw[RTK_FILTER_RAW_FIELD_NUMBER]; + rtk_filter_field_raw_t careFieldRaw[RTK_FILTER_RAW_FIELD_NUMBER]; + rtk_filter_field_type_raw_t fieldRawType[RTK_FILTER_RAW_FIELD_NUMBER]; + rtk_filter_care_tag_t careTag; + rtk_filter_activeport_t activeport; + rtk_filter_frametype_t l3fmt; + rtk_filter_frametype_t l4fmt; + + rtk_filter_invert_t invert; + rtk_enable_t valid; +} rtk_filter_cfg_raw_t; + +typedef struct +{ + rtk_uint32 index; + rtk_filter_field_type_raw_t fieldType[RTK_FILTER_RAW_FIELD_NUMBER]; +} rtk_filter_template_t; + + +/* Function Name: + * rtk_filter_igrAcl_init + * Description: + * ACL initialization function + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Pointer pFilter_field or pFilter_cfg point to NULL. + * Note: + * This function enable and intialize ACL function + */ +extern rtk_api_ret_t rtk_filter_igrAcl_init(void); + +/* Function Name: + * rtk_filter_igrAcl_field_add + * Description: + * Add comparison rule to an ACL configuration + * Input: + * pFilterCfg - The ACL configuration that this function will add comparison rule + * pFilterField - The comparison rule that will be added. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Pointer pFilter_field or pFilter_cfg point to NULL. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This function add a comparison rule (*pFilter_field) to an ACL configuration (*pFilter_cfg). + * Pointer pFilter_cfg points to an ACL configuration structure, this structure keeps multiple ACL + * comparison rules by means of linked list. Pointer pFilter_field will be added to linked + * list keeped by structure that pFilter_cfg points to. + */ +extern rtk_api_ret_t rtk_filter_igrAcl_field_add(rtk_filter_cfg_t *pFilterCfg, rtk_filter_field_t *pFilterField); + +/* Function Name: + * rtk_filter_igrAcl_cfg_add + * Description: + * Add an ACL configuration to ASIC + * Input: + * filter_id - Start index of ACL configuration. + * pFilterCfg - The ACL configuration that this function will add comparison rule + * pFilter_action - Action(s) of ACL configuration. + * Output: + * ruleNum - number of rules written in acl table + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Pointer pFilter_field or pFilter_cfg point to NULL. + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_ENTRY_INDEX - Invalid filter_id . + * RT_ERR_NULL_POINTER - Pointer pFilter_action or pFilter_cfg point to NULL. + * RT_ERR_FILTER_INACL_ACT_NOT_SUPPORT - Action is not supported in this chip. + * RT_ERR_FILTER_INACL_RULE_NOT_SUPPORT - Rule is not supported. + * Note: + * This function store pFilter_cfg, pFilter_action into ASIC. The starting + * index(es) is filter_id. + */ +extern rtk_api_ret_t rtk_filter_igrAcl_cfg_add(rtk_filter_id_t filterId, rtk_filter_cfg_t *pFilterCfg, rtk_filter_action_t *pAction, rtk_filter_number_t *ruleNum); + +/* Function Name: + * rtk_filter_igrAcl_cfg_del + * Description: + * Delete an ACL configuration from ASIC + * Input: + * filter_id - Start index of ACL configuration. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_ENTRYIDX - Invalid filter_id. + * Note: + * This function delete a group of ACL rules starting from filter_id. + */ +extern rtk_api_ret_t rtk_filter_igrAcl_cfg_del(rtk_filter_id_t filterId); + +/* Function Name: + * rtk_filter_igrAcl_cfg_delAll + * Description: + * Delete all ACL entries from ASIC + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This function delete all ACL configuration from ASIC. + */ +extern rtk_api_ret_t rtk_filter_igrAcl_cfg_delAll(void); + +/* Function Name: + * rtk_filter_igrAcl_cfg_get + * Description: + * Get one ingress acl configuration from ASIC. + * Input: + * filterId - Start index of ACL configuration. + * Output: + * pFilterCfg - buffer pointer of ingress acl data + * pFilter_action - buffer pointer of ingress acl action + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Pointer pFilter_action or pFilter_cfg point to NULL. + * RT_ERR_FILTER_ENTRYIDX - Invalid entry index. + * Note: + * This function delete all ACL configuration from ASIC. + */ +extern rtk_api_ret_t rtk_filter_igrAcl_cfg_get(rtk_filter_id_t filterId, rtk_filter_cfg_raw_t *pFilterCfg, rtk_filter_action_t *pAction); + +/* Function Name: + * rtk_filter_igrAcl_unmatchAction_set + * Description: + * Set action to packets when no ACL configuration match + * Input: + * port - Port id. + * action - Action. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port id. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This function sets action of packets when no ACL configruation matches. + */ +extern rtk_api_ret_t rtk_filter_igrAcl_unmatchAction_set(rtk_port_t port, rtk_filter_unmatch_action_t action); + +/* Function Name: + * rtk_filter_igrAcl_unmatchAction_get + * Description: + * Get action to packets when no ACL configuration match + * Input: + * port - Port id. + * Output: + * pAction - Action. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port id. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This function gets action of packets when no ACL configruation matches. + */ +extern rtk_api_ret_t rtk_filter_igrAcl_unmatchAction_get(rtk_port_t port, rtk_filter_unmatch_action_t* action); + +/* Function Name: + * rtk_filter_igrAcl_state_set + * Description: + * Set state of ingress ACL. + * Input: + * port - Port id. + * state - Ingress ACL state. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port id. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This function gets action of packets when no ACL configruation matches. + */ +extern rtk_api_ret_t rtk_filter_igrAcl_state_set(rtk_port_t port, rtk_filter_state_t state); + +/* Function Name: + * rtk_filter_igrAcl_state_get + * Description: + * Get state of ingress ACL. + * Input: + * port - Port id. + * Output: + * pState - Ingress ACL state. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port id. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This function gets action of packets when no ACL configruation matches. + */ +extern rtk_api_ret_t rtk_filter_igrAcl_state_get(rtk_port_t port, rtk_filter_state_t* state); + +/* Function Name: + * rtk_filter_igrAcl_template_set + * Description: + * Set template of ingress ACL. + * Input: + * template - Ingress ACL template + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This function set ACL template. + */ +extern rtk_api_ret_t rtk_filter_igrAcl_template_set(rtk_filter_template_t *aclTemplate); + +/* Function Name: + * rtk_filter_igrAcl_template_get + * Description: + * Get template of ingress ACL. + * Input: + * template - Ingress ACL template + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This function gets template of ACL. + */ +extern rtk_api_ret_t rtk_filter_igrAcl_template_get(rtk_filter_template_t *aclTemplate); + +/* Function Name: + * rtk_filter_igrAcl_field_sel_set + * Description: + * Set user defined field selectors in HSB + * Input: + * index - index of field selector 0-15 + * format - Format of field selector + * offset - Retrieving data offset + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * System support 16 user defined field selctors. + * Each selector can be enabled or disable. + * User can defined retrieving 16-bits in many predefiend + * standard l2/l3/l4 payload. + */ +extern rtk_api_ret_t rtk_filter_igrAcl_field_sel_set(rtk_uint32 index, rtk_field_sel_t format, rtk_uint32 offset); + +/* Function Name: + * rtk_filter_igrAcl_field_sel_get + * Description: + * Get user defined field selectors in HSB + * Input: + * index - index of field selector 0-15 + * Output: + * pFormat - Format of field selector + * pOffset - Retrieving data offset + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * None. + */ +extern rtk_api_ret_t rtk_filter_igrAcl_field_sel_get(rtk_uint32 index, rtk_field_sel_t *pFormat, rtk_uint32 *pOffset); + +/* Function Name: + * rtk_filter_iprange_set + * Description: + * Set IP Range check + * Input: + * index - index of IP Range 0-15 + * type - IP Range check type, 0:Delete a entry, 1: IPv4_SIP, 2: IPv4_DIP, 3:IPv6_SIP, 4:IPv6_DIP + * upperIp - The upper bound of IP range + * lowerIp - The lower Bound of IP range + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - The parameter is out of range + * RT_ERR_INPUT - Input error + * Note: + * upperIp must be larger or equal than lowerIp. + */ +extern rtk_api_ret_t rtk_filter_iprange_set(rtk_uint32 index, rtk_filter_iprange_t type, ipaddr_t upperIp, ipaddr_t lowerIp); + +/* Function Name: + * rtk_filter_iprange_get + * Description: + * Set IP Range check + * Input: + * index - index of IP Range 0-15 + * Output: + * pType - IP Range check type, 0:Delete a entry, 1: IPv4_SIP, 2: IPv4_DIP, 3:IPv6_SIP, 4:IPv6_DIP + * pUpperIp - The upper bound of IP range + * pLowerIp - The lower Bound of IP range + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - The parameter is out of range + * Note: + * upperIp must be larger or equal than lowerIp. + */ +extern rtk_api_ret_t rtk_filter_iprange_get(rtk_uint32 index, rtk_filter_iprange_t *pType, ipaddr_t *pUpperIp, ipaddr_t *pLowerIp); + +/* Function Name: + * rtk_filter_vidrange_set + * Description: + * Set VID Range check + * Input: + * index - index of VID Range 0-15 + * type - IP Range check type, 0:Delete a entry, 1: CVID, 2: SVID + * upperVid - The upper bound of VID range + * lowerVid - The lower Bound of VID range + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - The parameter is out of range + * RT_ERR_INPUT - Input error + * Note: + * upperVid must be larger or equal than lowerVid. + */ +extern rtk_api_ret_t rtk_filter_vidrange_set(rtk_uint32 index, rtk_filter_vidrange_t type, rtk_uint32 upperVid, rtk_uint32 lowerVid); + +/* Function Name: + * rtk_filter_vidrange_get + * Description: + * Get VID Range check + * Input: + * index - index of VID Range 0-15 + * Output: + * pType - IP Range check type, 0:Unused, 1: CVID, 2: SVID + * pUpperVid - The upper bound of VID range + * pLowerVid - The lower Bound of VID range + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - The parameter is out of range + * Note: + * None. + */ +extern rtk_api_ret_t rtk_filter_vidrange_get(rtk_uint32 index, rtk_filter_vidrange_t *pType, rtk_uint32 *pUpperVid, rtk_uint32 *pLowerVid); + +/* Function Name: + * rtk_filter_portrange_set + * Description: + * Set Port Range check + * Input: + * index - index of Port Range 0-15 + * type - IP Range check type, 0:Delete a entry, 1: Source Port, 2: Destnation Port + * upperPort - The upper bound of Port range + * lowerPort - The lower Bound of Port range + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - The parameter is out of range + * RT_ERR_INPUT - Input error + * Note: + * upperPort must be larger or equal than lowerPort. + */ +extern rtk_api_ret_t rtk_filter_portrange_set(rtk_uint32 index, rtk_filter_portrange_t type, rtk_uint32 upperPort, rtk_uint32 lowerPort); + +/* Function Name: + * rtk_filter_portrange_get + * Description: + * Set Port Range check + * Input: + * index - index of Port Range 0-15 + * Output: + * pType - IP Range check type, 0:Delete a entry, 1: Source Port, 2: Destnation Port + * pUpperPort - The upper bound of Port range + * pLowerPort - The lower Bound of Port range + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - The parameter is out of range + * RT_ERR_INPUT - Input error + * Note: + * None. + */ +extern rtk_api_ret_t rtk_filter_portrange_get(rtk_uint32 index, rtk_filter_portrange_t *pType, rtk_uint32 *pUpperPort, rtk_uint32 *pLowerPort); + +/* Function Name: + * rtk_filter_igrAc_gpiolPolarity_set + * Description: + * Set ACL Goip control palarity + * Input: + * polarity - 1: High, 0: Low + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * none + */ +extern rtk_api_ret_t rtk_filter_igrAcl_gpioPolarity_set(rtk_uint32 polarity); + +/* Function Name: + * rtk_filter_igrAcl_gpioPolarity_get + * Description: + * Get ACL Goip control palarity + * Input: + * pPolarity - 1: High, 0: Low + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * none + */ +extern rtk_api_ret_t rtk_filter_igrAcl_gpioPolarity_get(rtk_uint32* pPolarity); + +/* Function Name: + * rtk_filter_igrAcl_gpioEn_set + * Description: + * Set acl gpio pin status + * Input: + * gpioPinNum - gpio pin number (0~3) + * enabled - acl gpio pin enable or not + * Output: + * none - + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - The parameter is out of range + * RT_ERR_INPUT - Input error + * Note: + * None. + */ +extern rtk_api_ret_t rtk_filter_igrAcl_gpioEn_set(rtk_uint32 gpioPinNum, rtk_enable_t enabled); + +/* Function Name: + * rtk_filter_igrAcl_gpioEn_get + * Description: + * Get acl gpio pin status + * Input: + * gpioPinNum - gpio pin number (0~3) + * Output: + * *pEnabled - acl gpio pin status + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - The parameter is out of range + * RT_ERR_INPUT - Input error + * Note: + * None. + */ +extern rtk_api_ret_t rtk_filter_igrAcl_gpioEn_get(rtk_uint32 gpioPinNum, rtk_enable_t *pEnabled); + +/******************************************************************************* +* Function Name: +* rtk_filter_igrAcl_table_Reset +* Description: +* Table reset: both reset acl rule and action +*Input: +* None +*Output: +* None +*Return: +* RT_ERR_OK - OK +* RT_ERR_FAILED - Failed +* RT_ERR_PORT_ID - Error port number +* RT_ERR_ENABLE - Error action +*Note: None +*******************************************************************************/ +extern rtk_api_ret_t rtk_filter_igrAcl_table_Reset(void); + +#endif /* __RTK_API_ACL_H__ */ diff --git a/sources/uboot-be550/drivers/net/rtl8372/chip.c b/sources/uboot-be550/drivers/net/rtl8372/chip.c new file mode 100755 index 00000000..34d82e98 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/chip.c @@ -0,0 +1,195 @@ +/* + * Copyright (C) 2018 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * Purpose : chip symbol and data type definition in the SDK. + * + * Feature : chip symbol and data type definition + * + */ + +#if (!defined(CONFIG_DAL_RTL8373) && !defined(CONFIG_DAL_RTL8370UG)) +#define CONFIG_DAL_ALL +#endif + + + +#include +#include +#include "identify.h" +#if defined(CONFIG_DAL_RTL8373) || defined(CONFIG_DAL_ALL) +#include +#endif +//#if defined(CONFIG_DAL_RTL8370UG) || defined(CONFIG_DAL_ALL) +//#include +//#endif + +#if (!defined(FORCE_PROBE_RTL8373) && !defined(FORCE_PROBE_RTL8370UG) ) +#define AUTO_PROBE 1 +#else +#define AUTO_PROBE 0 +#endif + +#if (AUTO_PROBE || defined(FORCE_PROBE_RTL8373)) +static rtk_switch_halCtrl_t rtl8371c_hal_Ctrl = +{ + /* Switch Chip */ + CHIP_RTL8373, + + /* Logical to Physical */ + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}, + + /* Physical to Logical */ + {UTP_PORT0, UTP_PORT1, UTP_PORT2, UTP_PORT3, UTP_PORT4, UTP_PORT5, UTP_PORT6, UTP_PORT7, UTP_PORT8, UTP_PORT9}, + + /* Port Type */ + {UTP_PORT, UTP_PORT, UTP_PORT, UTP_PORT, UTP_PORT, UTP_PORT, UTP_PORT, UTP_PORT, UTP_PORT, UTP_PORT}, + + /* PTP port */ + {1, 1, 1, 1, 1, 1, 1, 1, 1, 1 }, + + /* Valid port mask */ + ( (0x1 << UTP_PORT0) | (0x1 << UTP_PORT1) | (0x1 << UTP_PORT2) | (0x1 << UTP_PORT3) | (0x1 << UTP_PORT4) | (0x1 << UTP_PORT5) | (0x1 << UTP_PORT6) | (0x1 << UTP_PORT7) | (0x1 << UTP_PORT8) | (0x1 << UTP_PORT9) ), + + /* Valid UTP port mask */ + ( (0x1 << UTP_PORT0) | (0x1 << UTP_PORT1) | (0x1 << UTP_PORT2) | (0x1 << UTP_PORT3) | (0x1 << UTP_PORT4) | (0x1 << UTP_PORT5) | (0x1 << UTP_PORT6) | (0x1 << UTP_PORT7) | (0x1 << UTP_PORT8) | (0x1 << UTP_PORT9)), + + /* Valid EXT port mask */ + 0x0, + + /* Valid CPU port mask */ + 0x200, + + /* Minimum physical port number */ + 0, + + /* Maxmum physical port number */ + 9, + + /* Physical port mask */ + 0x3FF, + + /* Combo Logical port ID */ + 0, + + /* HSG Logical port ID */ + 1, + + /* SGMII Logical portmask */ + (0x1 ), + + /* Max Meter ID */ + 63, + + /* MAX LUT Address Number */ + 4160, + + /* Trunk Group Mask */ + 0x0f, + + /* Packet buffer page number */ + 1024, + + /* default pPhy_ctrl */ + NULL +}; +#endif + + +/* Function Name: + * switch_probe + * Description: + * Probe switch + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - Switch probed + * RT_ERR_FAILED - Switch Unprobed. + * Note: + * + */ +rtk_api_ret_t switch_probe(switch_chip_t *pSwitchChip) +{ +#if defined(FORCE_PROBE_RTL8373) + + *pSwitchChip = CHIP_RTL8373; + return RT_ERR_OK; + +#else + rtk_uint32 retVal; + rtk_uint32 data; +#if defined(CONFIG_DAL_RTL8373) || defined(CONFIG_DAL_ALL) + rtk_uint32 regValue; + + + if((retVal = rtl8373_getAsicReg(0x4, &data)) != RT_ERR_OK) + { + printf("rtl8373_getAsicReg error!!!!\n"); + return retVal; + } + data = data >> 16; + + printf("data=0x%x\n", data); + + switch (data) + { + case 0x8373: + case 0x8372: + printf("find chip\n"); + *pSwitchChip = CHIP_RTL8373; + return RT_ERR_OK; + default: + break; + } +#endif + +#endif + + return RT_ERR_CHIP_NOT_FOUND; +} + +/* Function Name: + * hal_find_device + * Description: + * Find the mac chip from SDK supported mac device lists. + * Input: + * None + * Output: + * None + * Return: + * NULL - Not found + * Otherwise - Pointer of mac chip HAL structure that found + * Note: + * + */ +rtk_switch_halCtrl_t *hal_find_device(void) +{ + switch_chip_t switchChip; + rtk_uint32 retVal; + + /* probe switch */ + if((retVal = switch_probe(&switchChip)) != RT_ERR_OK) + return NULL; + + switch (switchChip) + { +#if (AUTO_PROBE || defined(FORCE_PROBE_RTL8373)) + case CHIP_RTL8373: + return &rtl8371c_hal_Ctrl; +#endif + + default: + return NULL; + } + + /* Not found */ + return NULL; +} diff --git a/sources/uboot-be550/drivers/net/rtl8372/chip.h b/sources/uboot-be550/drivers/net/rtl8372/chip.h new file mode 100755 index 00000000..f5faabc8 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/chip.h @@ -0,0 +1,123 @@ +/* + * Copyright(c) Realtek Semiconductor Corporation, 2008 + * All rights reserved. + * + * $Revision$ + * $Date$ + * + * Purpose : Definition function prototype of RTK switch API. + * + * Feature : Function prototype definition + * + */ + +#ifndef __CHIP_H__ +#define __CHIP_H__ + + +#include +#include "phydef.h" + +#define UNDEFINE_PHY_PORT (0xFF) +#define RTK_SWITCH_PORT_NUM (10) +#define RTK_MAX_PHYNUM 1 +typedef enum switch_chip_e +{ + CHIP_RTL8373 = 0, + CHIP_RTL8224 = 1, + CHIP_RTL8372, + CHIP_RTL8373N, + CHIP_RTL8221B, + CHIP_RTL8366U, + CHIP_RTL8372N, + CHIP_RTL8224N, + CHIP_END +}switch_chip_t; + +typedef enum port_type_e +{ + UTP_PORT = 0, + EXT_PORT, + UNKNOWN_PORT = 0xFF, + PORT_TYPE_END +}port_type_t; + +typedef struct rtk_switch_halCtrl_s +{ + switch_chip_t switch_type; + rtk_uint32 l2p_port[RTK_SWITCH_PORT_NUM]; + rtk_uint32 p2l_port[RTK_SWITCH_PORT_NUM]; + port_type_t log_port_type[RTK_SWITCH_PORT_NUM]; + rtk_uint32 ptp_port[RTK_SWITCH_PORT_NUM]; + rtk_uint32 valid_portmask; + rtk_uint32 valid_utp_portmask; + rtk_uint32 valid_ext_portmask; + rtk_uint32 valid_cpu_portmask; + rtk_uint32 min_phy_port; + rtk_uint32 max_phy_port; + rtk_uint32 phy_portmask; + rtk_uint32 combo_logical_port; + rtk_uint32 hsg_logical_portmask; + rtk_uint32 sg_logical_portmask; + rtk_uint32 max_meter_id; + rtk_uint32 max_lut_addr_num; + rtk_uint32 trunk_group_mask; + rtk_uint32 packet_buffer_page_num; + rt_phyctrl_t *pPhy_ctrl; + +}rtk_switch_halCtrl_t; + + + +typedef enum rt_port_ethType_id_e +{ + HWP_FE_ID = 0, + HWP_GE_ID, + HWP_2_5GE_ID, + HWP_XGE_ID, + HWP_SXGE_ID, + HWP_ETHTYPE_ID_END, +}rt_port_ethType_id_t; +/* port ethernet type */ +typedef enum rt_port_ethType_e +{ + HWP_FE = (0x1 << HWP_FE_ID), /* Fast ethernet port */ + HWP_GE = (0x1 << HWP_GE_ID), /* Giga ethernet port */ + HWP_2_5GE = (0x1 << HWP_2_5GE_ID), /* 2.5 Giga ethernet port */ + HWP_XGE = (0x1 << HWP_XGE_ID), /* 10 Giga ethernet port */ + HWP_SXGE = (0x1 << HWP_SXGE_ID), /* Cascade Stack port */ + HWP_ETHTYPE_END = (0x1 << HWP_ETHTYPE_ID_END), /* Ether type end*/ +}rt_port_ethType_t; +/* Function Name: + * switch_probe + * Description: + * Probe switch + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - Switch probed + * RT_ERR_FAILED - Switch Unprobed. + * Note: + * + */ +extern rtk_api_ret_t switch_probe(switch_chip_t *pSwitchChip); + +/* Function Name: + * hal_find_device + * Description: + * Find the mac chip from SDK supported mac device lists. + * Input: + * None + * Output: + * None + * Return: + * NULL - Not found + * Otherwise - Pointer of mac chip HAL structure that found + * Note: + * + */ +extern rtk_switch_halCtrl_t *hal_find_device(void); + +#endif /* End of __CHIP_H__ */ diff --git a/sources/uboot-be550/drivers/net/rtl8372/cpuTag.c b/sources/uboot-be550/drivers/net/rtl8372/cpuTag.c new file mode 100755 index 00000000..91bb8892 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/cpuTag.c @@ -0,0 +1,398 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8373 + * Feature : Here is a list of all functions and variables in CPU module. + * + */ + +#include "rtk_switch.h" +#include "rtk_error.h" +#include "cpuTag.h" +#include + +#include + +/* Function Name: + * rtk_cpu_externalCpuPort_set + * Description: + * Set external cpu port + * Input: + * port -port number + * Output: + * None - + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +rtk_api_ret_t rtk_cpu_externalCpuPort_set(rtk_uint32 port) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->cpuTag_externalCpuPort_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->cpuTag_externalCpuPort_set(port); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_cpu_externalCpuPort_get + * Description: + * Get external cpu port + * Input: + * None + * Output: + * pPort - port number + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +rtk_api_ret_t rtk_cpu_externalCpuPort_get(rtk_uint32 *pPort) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->cpuTag_externalCpuPort_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->cpuTag_externalCpuPort_get(pPort); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_cpuTag_tpid_set + * Description: + * Set cpu tag protocol id; default:0x8899 + * Input: + * tpid - protocol ID + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +rtk_api_ret_t rtk_cpuTag_tpid_set(rtk_uint32 tpid) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->cpuTag_tpid_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->cpuTag_tpid_set(tpid); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_cpuTag_tpid_get + * Description: + * Get cpu tag protocol id + * Input: + * None + * Output: + * pTpid - protocol ID + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +rtk_api_ret_t rtk_cpuTag_tpid_get(rtk_uint32 *pTpid) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->cpuTag_tpid_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->cpuTag_tpid_get(pTpid); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_cpuTag_enable_set + * Description: + * Set internal CPU port & external CPU port function enable/disable. + * Input: + * status - CPU port function status: enable or disable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can set internal CPU port & external CPU port function enable/disable. + */ +rtk_api_ret_t rtk_cpuTag_enable_set(rtk_cpu_type_t type, rtk_enable_t status) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->cpuTag_enable_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->cpuTag_enable_set(type, status); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_cpuTag_enable_get + * Description: + * Get internal CPU port & external CPU port status setting. + * Input: + * None + * Output: + * pStatus - CPU port function status + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_L2_NO_CPU_PORT - CPU port is not exist + * Note: + * The API can get internal CPU port & external CPU port function enable/disable. + */ +rtk_api_ret_t rtk_cpuTag_enable_get(rtk_cpu_type_t type, rtk_enable_t *pStatus) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->cpuTag_enable_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->cpuTag_enable_get(type, pStatus); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_cpu_tagPort_set + * Description: + * Set internal & external CPU tag insert mode. + * Input: + * mode - CPU tag insert for packets egress from CPU port. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can set CPU port inserting proprietary CPU tag mode (Length/Type 0x8899) + * to the frame that transmitting to CPU port. + * The inset cpu tag mode is as following: + * - CPU_INSERT_TO_ALL + * - CPU_INSERT_TO_TRAPPING + * - CPU_INSERT_TO_NONE + */ +rtk_api_ret_t rtk_cpuTag_insertMode_set(rtk_cpu_type_t type, rtk_cpuTag_insertMode_t mode) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->cpuTag_insertMode_set) + return RT_ERR_DRIVER_NOT_FOUND; + RTK_API_LOCK(); + retVal = RT_MAPPER->cpuTag_insertMode_set(type, mode); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_cpuTag_insertMode_get + * Description: + * Get CPU tag insert mode. + * Input: + * None + * Output: + * pMode - CPU tag insert for packets egress from CPU port, 0:all insert 1:Only for trapped packets 2:no insert. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_L2_NO_CPU_PORT - CPU port is not exist + * Note: + * The API can get configured CPU tag insert mode. + * The inset cpu tag mode is as following: + * - CPU_INSERT_TO_ALL + * - CPU_INSERT_TO_TRAPPING + * - CPU_INSERT_TO_NONE + */ +rtk_api_ret_t rtk_cpuTag_insertMode_get(rtk_cpu_type_t type, rtk_cpuTag_insertMode_t *pMode) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->cpuTag_insertMode_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->cpuTag_insertMode_get(type, pMode); + RTK_API_UNLOCK(); + + return retVal; +} + + +/* Function Name: + * rtk_cpuTag_awarePort_set + * Description: + * Set CPU aware port mask. + * Input: + * portmask - Port mask. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Invalid port mask. + * Note: + * The API can set configured CPU aware port mask. + */ +rtk_api_ret_t rtk_cpuTag_awarePort_set(rtk_portmask_t *pPortmask) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->cpuTag_awarePort_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->cpuTag_awarePort_set(pPortmask); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_cpuTag_awarePort_get + * Description: + * Get CPU aware port mask. + * Input: + * None + * Output: + * pPortmask - Port mask. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can get configured CPU aware port mask. + */ +rtk_api_ret_t rtk_cpuTag_awarePort_get(rtk_portmask_t *pPortmask) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->cpuTag_awarePort_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->cpuTag_awarePort_get(pPortmask); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_cpuTag_priRemap_set + * Description: + * Configure CPU priorities mapping to internal absolute priority. + * Input: + * type -cpu type: internal or external cpu + * int_pri - internal priority value. + * new_pri - new internal priority value. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_VLAN_PRIORITY - Invalid 1p priority. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * Priority of CPU tag assignment for internal asic priority, and it is used for queue usage and packet scheduling. + */ +rtk_api_ret_t rtk_cpuTag_priRemap_set(rtk_cpu_type_t type, rtk_pri_t intPri, rtk_pri_t newPri) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->cpuTag_priRemap_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->cpuTag_priRemap_set(type, intPri, newPri); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_cpuTag_priRemap_get + * Description: + * Configure CPU priorities mapping to internal absolute priority. + * Input: + * type -cpu type: internal or external cpu + * int_pri - internal priority value. + * Output: + * pNew_pri - new internal priority value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_VLAN_PRIORITY - Invalid 1p priority. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * Priority of CPU tag assignment for internal asic priority, and it is used for queue usage and packet scheduling. + */ +rtk_api_ret_t rtk_cpuTag_priRemap_get(rtk_cpu_type_t type, rtk_pri_t intPri, rtk_pri_t *pNewPri) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->cpuTag_priRemap_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->cpuTag_priRemap_get(type, intPri, pNewPri); + RTK_API_UNLOCK(); + + return retVal; +} + + diff --git a/sources/uboot-be550/drivers/net/rtl8372/cpuTag.h b/sources/uboot-be550/drivers/net/rtl8372/cpuTag.h new file mode 100755 index 00000000..e8ef2640 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/cpuTag.h @@ -0,0 +1,269 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8373 switch high-level API + * + * Feature : The file includes CPU module high-layer API defination + * + */ + +#ifndef __RTK_API_CPU_H__ +#define __RTK_API_CPU_H__ + + +/* + * Data Type Declaration + */ +#define INTERNAL_CPU_PMSK (0x200) + +typedef enum rtk_cpuTag_insertMode_s +{ + CPU_INSERT_TO_ALL = 0, + CPU_INSERT_TO_TRAPPING, + CPU_INSERT_TO_NONE, + CPU_INSERT_END +}rtk_cpuTag_insertMode_t; + +typedef enum rtk_cpu_type_e +{ + INTERNAL_CPU = 0, + EXTERNAL_CPU, + CPU_TYPE_END +}rtk_cpu_type_t; + +/* Function Name: + * rtk_cpu_externalCpuPort_set + * Description: + * Set external cpu port + * Input: + * port -port number + * Output: + * None - + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +extern rtk_api_ret_t rtk_cpu_externalCpuPort_set(rtk_uint32 port); + +/* Function Name: + * rtk_cpu_externalCpuPort_get + * Description: + * Get external cpu port + * Input: + * None + * Output: + * pPort - port number + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +extern rtk_api_ret_t rtk_cpu_externalCpuPort_get(rtk_uint32 *pPort); + +/* Function Name: + * rtk_cpuTag_tpid_set + * Description: + * Set cpu tag protocol id; default:0x8899 + * Input: + * tpid - protocol ID + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +extern rtk_api_ret_t rtk_cpuTag_tpid_set(rtk_uint32 tpid); + +/* Function Name: + * rtk_cpuTag_tpid_get + * Description: + * Get cpu tag protocol id + * Input: + * None + * Output: + * pTpid - protocol ID + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +extern rtk_api_ret_t rtk_cpuTag_tpid_get(rtk_uint32 *pTpid); + +/* Function Name: + * rtk_cpuTag_enable_set + * Description: + * Set internal CPU port & external CPU port function enable/disable. + * Input: + * status - CPU port function status: enable or disable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can set internal CPU port & external CPU port function enable/disable. + */ +extern rtk_api_ret_t rtk_cpuTag_enable_set(rtk_cpu_type_t type, rtk_enable_t status); + +/* Function Name: + * rtk_cpuTag_enable_get + * Description: + * Get internal CPU port & external CPU port status setting. + * Input: + * None + * Output: + * pStatus - CPU port function status + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_L2_NO_CPU_PORT - CPU port is not exist + * Note: + * The API can get internal CPU port & external CPU port function enable/disable. + */ +extern rtk_api_ret_t rtk_cpuTag_enable_get(rtk_cpu_type_t type, rtk_enable_t *pStatus); + +/* Function Name: + * rtk_cpu_tagPort_set + * Description: + * Set internal & external CPU tag insert mode. + * Input: + * mode - CPU tag insert for packets egress from CPU port. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can set CPU port inserting proprietary CPU tag mode (Length/Type 0x8899) + * to the frame that transmitting to CPU port. + * The inset cpu tag mode is as following: + * - CPU_INSERT_TO_ALL + * - CPU_INSERT_TO_TRAPPING + * - CPU_INSERT_TO_NONE + */ +extern rtk_api_ret_t rtk_cpuTag_insertMode_set(rtk_cpu_type_t type, rtk_cpuTag_insertMode_t mode); + +/* Function Name: + * rtk_cpu_tagPort_get + * Description: + * Get CPU tag insert mode. + * Input: + * None + * Output: + * pMode - CPU tag insert for packets egress from CPU port, 0:all insert 1:Only for trapped packets 2:no insert. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_L2_NO_CPU_PORT - CPU port is not exist + * Note: + * The API can get configured CPU tag insert mode. + * The inset cpu tag mode is as following: + * - CPU_INSERT_TO_ALL + * - CPU_INSERT_TO_TRAPPING + * - CPU_INSERT_TO_NONE + */ +extern rtk_api_ret_t rtk_cpuTag_insertMode_get(rtk_cpu_type_t type, rtk_cpuTag_insertMode_t *pMode); + +/* Function Name: + * rtk_cpuTag_awarePort_set + * Description: + * Set CPU aware port mask. + * Input: + * portmask - Port mask. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Invalid port mask. + * Note: + * The API can set configured CPU aware port mask. + */ +extern rtk_api_ret_t rtk_cpuTag_awarePort_set(rtk_portmask_t *pPortmask); + +/* Function Name: + * rtk_cpuTag_awarePort_get + * Description: + * Get CPU aware port mask. + * Input: + * None + * Output: + * pPortmask - Port mask. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can get configured CPU aware port mask. + */ +extern rtk_api_ret_t rtk_cpuTag_awarePort_get(rtk_portmask_t *pPortmask); + +/* Function Name: + * rtk_cpuTag_priRemap_set + * Description: + * Configure CPU priorities mapping to internal absolute priority. + * Input: + * type -cpu type: internal or external cpu + * int_pri - internal priority value. + * new_pri - new internal priority value. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_VLAN_PRIORITY - Invalid 1p priority. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * Priority of CPU tag assignment for internal asic priority, and it is used for queue usage and packet scheduling. + */ +extern rtk_api_ret_t rtk_cpuTag_priRemap_set(rtk_cpu_type_t type, rtk_pri_t intPri, rtk_pri_t newPri); + +/* Function Name: + * rtk_cpuTag_priRemap_get + * Description: + * Configure CPU priorities mapping to internal absolute priority. + * Input: + * type -cpu type: internal or external cpu + * int_pri - internal priority value. + * Output: + * pNew_pri - new internal priority value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_VLAN_PRIORITY - Invalid 1p priority. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * Priority of CPU tag assignment for internal asic priority, and it is used for queue usage and packet scheduling. + */ +extern rtk_api_ret_t rtk_cpuTag_priRemap_get(rtk_cpu_type_t type, rtk_pri_t intPri, rtk_pri_t *pNewPri); + +#endif /* __RTK_API_CPU_H__ */ diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/Makefile b/sources/uboot-be550/drivers/net/rtl8372/dal/Makefile new file mode 100644 index 00000000..524aa7f1 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/Makefile @@ -0,0 +1,18 @@ +LOC_DIR=src/hsl/phy/rtl8372/dal +LIB=HSL + +include $(PRJ_PATH)/make/config.mk + +SRC_LIST= + +ifeq (TRUE, $(IN_RTL8372_PHY)) +SRC_LIST += dal_mgmt.c + +EXTRA_CFLAGS += -DMDC_MDIO_OPERATION +endif + +include $(PRJ_PATH)/make/components.mk +include $(PRJ_PATH)/make/defs.mk +include $(PRJ_PATH)/make/target.mk + +all: dep obj diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/dal_mapper.h b/sources/uboot-be550/drivers/net/rtl8372/dal/dal_mapper.h new file mode 100755 index 00000000..255fe324 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/dal_mapper.h @@ -0,0 +1,759 @@ +/* + * Copyright (C) 2011 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * Purpose : Mapper Layer is used to seperate different kind of software or hardware platform + * + * Feature : Just dispatch information to Multiplex layer + * + */ +#ifndef __DAL_MAPPER_H__ +#define __DAL_MAPPER_H__ + +/* + * Include Files + */ +#include +#include +#include +#include <../acl.h> +#include <../vlan.h> +#include <../svlan.h> +#include <../mirror.h> +#include <../cpuTag.h> +#include <../qos.h> +#include <../isolation.h> +#include <../sharemeter.h> +#include <../storm.h> +#include <../igmp.h> +#include <../dot1x.h> +#include <../nic.h> +#include <../ptp.h> +#include <../l2.h> +#include <../macsec.h> +#include <../trunk.h> +#include <../rldp.h> +#include <../dos.h> +#include <../gpio.h> +#include <../i2c.h> +#include <../rate.h> +#include <../eee.h> +#include <../interrupt.h> +#include <../mib.h> +#include <../rma.h> +#include <../led.h> +#include <../port.h> + + +/* + * Symbol Definition + */ + +/* + * Data Declaration + */ + +typedef struct dal_mapper_s { + + /* switch */ + rtk_api_ret_t (*switch_init)(void); + rtk_api_ret_t (*switch_portMaxPktLen_set)(rtk_port_t, rtk_switch_maxPktLen_linkSpeed_t, rtk_uint32); + rtk_api_ret_t (*switch_portMaxPktLen_get)(rtk_port_t, rtk_switch_maxPktLen_linkSpeed_t, rtk_uint32 *); + rtk_api_ret_t (*switch_maxPktLenCfg_set)(rtk_uint32, rtk_uint32); + rtk_api_ret_t (*switch_maxPktLenCfg_get)(rtk_uint32, rtk_uint32 *); + rtk_api_ret_t (*switch_greenEthernet_set)(rtk_enable_t); + rtk_api_ret_t (*switch_greenEthernet_get)(rtk_enable_t *); + + rtk_api_ret_t (*fMdrv_miim_mmd_read)(rtk_uint32 , rtk_uint32 , rtk_uint32 , rtk_uint32 *); + rtk_api_ret_t (*fMdrv_miim_mmd_write)(rtk_uint32 , rtk_uint32 , rtk_uint32 , rtk_uint32 ); + rtk_api_ret_t (*fMdrv_miim_mmd_readbits)(rtk_uint32 , rtk_uint32 , rtk_uint32 , rtk_uint32,rtk_uint32 *); + rtk_api_ret_t (*fMdrv_miim_mmd_writebits)(rtk_uint32 , rtk_uint32 , rtk_uint32 , rtk_uint32 ,rtk_uint32); + /* cpuTag */ + rtk_api_ret_t (*cpuTag_externalCpuPort_set)(rtk_uint32); + rtk_api_ret_t (*cpuTag_externalCpuPort_get)(rtk_uint32 *); + rtk_api_ret_t (*cpuTag_tpid_set)(rtk_uint32); + rtk_api_ret_t (*cpuTag_tpid_get)(rtk_uint32 *); + rtk_api_ret_t (*cpuTag_enable_set)(rtk_cpu_type_t, rtk_enable_t); + rtk_api_ret_t (*cpuTag_enable_get)(rtk_cpu_type_t, rtk_enable_t *); + rtk_api_ret_t (*cpuTag_insertMode_set)(rtk_cpu_type_t,rtk_cpuTag_insertMode_t ); + rtk_api_ret_t (*cpuTag_insertMode_get)(rtk_cpu_type_t,rtk_cpuTag_insertMode_t *); + rtk_api_ret_t (*cpuTag_awarePort_set)(rtk_portmask_t *); + rtk_api_ret_t (*cpuTag_awarePort_get)(rtk_portmask_t *); + rtk_api_ret_t (*cpuTag_priRemap_set)(rtk_cpu_type_t, rtk_pri_t, rtk_pri_t); + rtk_api_ret_t (*cpuTag_priRemap_get)(rtk_cpu_type_t, rtk_pri_t, rtk_pri_t *); + + /* acl */ + rtk_api_ret_t (*filter_igrAcl_init)(void); + rtk_api_ret_t (*filter_igrAcl_field_add)(rtk_filter_cfg_t *, rtk_filter_field_t *); + rtk_api_ret_t (*filter_igrAcl_cfg_add)(rtk_filter_id_t, rtk_filter_cfg_t *, rtk_filter_action_t *, rtk_filter_number_t *); + rtk_api_ret_t (*filter_igrAcl_cfg_del)(rtk_filter_id_t); + rtk_api_ret_t (*filter_igrAcl_cfg_delAll)(void); + rtk_api_ret_t (*filter_igrAcl_cfg_get)(rtk_filter_id_t, rtk_filter_cfg_raw_t *, rtk_filter_action_t *); + rtk_api_ret_t (*filter_igrAcl_unmatchAction_set)(rtk_port_t, rtk_filter_unmatch_action_t); + rtk_api_ret_t (*filter_igrAcl_unmatchAction_get)(rtk_port_t, rtk_filter_unmatch_action_t *); + rtk_api_ret_t (*filter_igrAcl_state_set)(rtk_port_t, rtk_filter_state_t); + rtk_api_ret_t (*filter_igrAcl_state_get)(rtk_port_t, rtk_filter_state_t *); + rtk_api_ret_t (*filter_igrAcl_template_set)(rtk_filter_template_t *); + rtk_api_ret_t (*filter_igrAcl_template_get)(rtk_filter_template_t *); + rtk_api_ret_t (*filter_igrAcl_field_sel_set)(rtk_uint32, rtk_field_sel_t, rtk_uint32); + rtk_api_ret_t (*filter_igrAcl_field_sel_get)(rtk_uint32, rtk_field_sel_t *, rtk_uint32 *); + rtk_api_ret_t (*filter_iprange_set)(rtk_uint32, rtk_filter_iprange_t, ipaddr_t, ipaddr_t); + rtk_api_ret_t (*filter_iprange_get)(rtk_uint32, rtk_filter_iprange_t *, ipaddr_t *, ipaddr_t *); + rtk_api_ret_t (*filter_vidrange_set)(rtk_uint32, rtk_filter_vidrange_t, rtk_uint32, rtk_uint32); + rtk_api_ret_t (*filter_vidrange_get)(rtk_uint32, rtk_filter_vidrange_t *, rtk_uint32 *, rtk_uint32 *); + rtk_api_ret_t (*filter_portrange_set)(rtk_uint32, rtk_filter_portrange_t, rtk_uint32, rtk_uint32); + rtk_api_ret_t (*filter_portrange_get)(rtk_uint32, rtk_filter_portrange_t *, rtk_uint32 *, rtk_uint32 *); + rtk_api_ret_t (*filter_igrAcl_gpioPolarity_set)(rtk_uint32); + rtk_api_ret_t (*filter_igrAcl_gpioPolarity_get)(rtk_uint32 *); + rtk_api_ret_t (*filter_igrAcl_gpioEn_set)(rtk_uint32, rtk_enable_t); + rtk_api_ret_t (*filter_igrAcl_gpioEn_get)(rtk_uint32, rtk_enable_t *); + rtk_api_ret_t (*filter_igrAcl_tbl_rst)(void); + + /* mirror */ + rtk_api_ret_t (*mirror_set_en)(rtk_enable_t ); + rtk_api_ret_t (*mirror_setStatus_get)(rtk_enable_t *); + rtk_api_ret_t (*mirror_entry_set)(rtk_port_mir_set_t *); + rtk_api_ret_t (*mirror_entry_get)(rtk_port_mir_set_t *); + rtk_api_ret_t (*mirror_portIso_set)(rtk_enable_t); + rtk_api_ret_t (*mirror_portIso_get)(rtk_enable_t *); + rtk_api_ret_t (*mirror_vlanLeaky_set)(rtk_enable_t , rtk_enable_t); + rtk_api_ret_t (*mirror_vlanLeaky_get)(rtk_enable_t *, rtk_enable_t *); + rtk_api_ret_t (*mirror_isolationLeaky_set)(rtk_enable_t, rtk_enable_t ); + rtk_api_ret_t (*mirror_isolationLeaky_get)(rtk_enable_t *, rtk_enable_t *); + rtk_api_ret_t (*mirror_keep_set)(rtk_mirror_keep_t); + rtk_api_ret_t (*mirror_keep_get)(rtk_mirror_keep_t *); + rtk_api_ret_t (*mirror_override_set)(rtk_enable_t, rtk_enable_t, rtk_enable_t); + rtk_api_ret_t (*mirror_override_get)(rtk_enable_t *, rtk_enable_t *, rtk_enable_t *); + rtk_api_ret_t (*mirror_sampleRate_set)(rtk_uint32); + rtk_api_ret_t (*mirror_sampleRate_get)(rtk_uint32 *); + rtk_api_ret_t (*mirror_pktCnt_get)(rtk_uint32 *); + rtk_api_ret_t (*mirror_samplePktCnt_get)(rtk_uint32 *); + rtk_api_ret_t (*rspan_rxTag_en)(rtk_enable_t); + rtk_api_ret_t (*rspan_rxTagEnSts_get)(rtk_enable_t *); + rtk_api_ret_t (*rspan_tagCtxt_set)(rtk_rspan_tag_t *); + rtk_api_ret_t (*rspan_tagCtxt_get)(rtk_rspan_tag_t *); + rtk_api_ret_t (*rspan_tagAdd_set)(rtk_portmask_t); + rtk_api_ret_t (*rspan_tagAdd_get)(rtk_portmask_t *); + rtk_api_ret_t (*rspan_tagRemove_set)(rtk_enable_t); + rtk_api_ret_t (*rspan_tagRemove_get)(rtk_enable_t *); + + rtk_api_ret_t (*port_isolation_set)(rtk_port_t, rtk_uint32 ); + rtk_api_ret_t (*port_isolation_get)(rtk_port_t, rtk_uint32 *); + + /* IGMP */ + rtk_api_ret_t (*igmp_init)(void); + rtk_api_ret_t (*igmp_state_set)(rtk_enable_t); + rtk_api_ret_t (*igmp_state_get)(rtk_enable_t *); + rtk_api_ret_t (*igmp_static_router_port_set)(rtk_portmask_t *); + rtk_api_ret_t (*igmp_static_router_port_get)(rtk_portmask_t *); + rtk_api_ret_t (*igmp_protocol_set)(rtk_port_t, rtk_igmp_protocol_t, rtk_igmp_action_t); + rtk_api_ret_t (*igmp_protocol_get)(rtk_port_t, rtk_igmp_protocol_t, rtk_igmp_action_t *); + rtk_api_ret_t (*igmp_fastLeave_set)(rtk_enable_t); + rtk_api_ret_t (*igmp_fastLeave_get)(rtk_enable_t *); + rtk_api_ret_t (*igmp_maxGroup_set)(rtk_port_t, rtk_uint32); + rtk_api_ret_t (*igmp_maxGroup_get)(rtk_port_t, rtk_uint32 *); + rtk_api_ret_t (*igmp_currentGroup_get)(rtk_port_t, rtk_uint32 *); + rtk_api_ret_t (*igmp_tableFullAction_set)(rtk_igmp_tableFullAction_t); + rtk_api_ret_t (*igmp_tableFullAction_get)(rtk_igmp_tableFullAction_t *); + rtk_api_ret_t (*igmp_checksumErrorAction_set)(rtk_igmp_checksumErrorAction_t); + rtk_api_ret_t (*igmp_checksumErrorAction_get)(rtk_igmp_checksumErrorAction_t *); + rtk_api_ret_t (*igmp_leaveTimer_set)(rtk_uint32); + rtk_api_ret_t (*igmp_leaveTimer_get)(rtk_uint32 *); + rtk_api_ret_t (*igmp_queryInterval_set)(rtk_uint32); + rtk_api_ret_t (*igmp_queryInterval_get)(rtk_uint32 *); + rtk_api_ret_t (*igmp_robustness_set)(rtk_uint32); + rtk_api_ret_t (*igmp_robustness_get)(rtk_uint32 *); + rtk_api_ret_t (*igmp_dynamicRouterPortAllow_set)(rtk_portmask_t *); + rtk_api_ret_t (*igmp_dynamicRouterPortAllow_get)(rtk_portmask_t *); + rtk_api_ret_t (*igmp_dynamicRouterPort_get)(rtk_igmp_dynamicRouterPort_t *); + rtk_api_ret_t (*igmp_suppressionEnable_set)(rtk_enable_t, rtk_enable_t); + rtk_api_ret_t (*igmp_suppressionEnable_get)(rtk_enable_t *, rtk_enable_t *); + rtk_api_ret_t (*igmp_portRxPktEnable_set)(rtk_port_t, rtk_igmp_rxPktEnable_t *); + rtk_api_ret_t (*igmp_portRxPktEnable_get)(rtk_port_t, rtk_igmp_rxPktEnable_t *); + rtk_api_ret_t (*igmp_groupInfo_get)(rtk_uint32, rtk_igmp_groupInfo_t *); + rtk_api_ret_t (*igmp_ReportLeaveFwdAction_set)(rtk_igmp_ReportLeaveFwdAct_t); + rtk_api_ret_t (*igmp_ReportLeaveFwdAction_get)(rtk_igmp_ReportLeaveFwdAct_t *); + rtk_api_ret_t (*igmp_dropLeaveZeroEnable_set)(rtk_enable_t); + rtk_api_ret_t (*igmp_dropLeaveZeroEnable_get)(rtk_enable_t *); + rtk_api_ret_t (*igmp_bypassGroupRange_set)(rtk_igmp_bypassGroup_t, rtk_enable_t); + rtk_api_ret_t (*igmp_bypassGroupRange_get)(rtk_igmp_bypassGroup_t, rtk_enable_t *); + + /* Storm */ + rtk_api_ret_t (*rate_stormControlMeterIdx_set)(rtk_port_t, rtk_rate_storm_group_t, rtk_uint32); + rtk_api_ret_t (*rate_stormControlMeterIdx_get)(rtk_port_t, rtk_rate_storm_group_t, rtk_uint32 *); + rtk_api_ret_t (*rate_stormControlPortEnable_set)(rtk_port_t, rtk_rate_storm_group_t, rtk_enable_t); + rtk_api_ret_t (*rate_stormControlPortEnable_get)(rtk_port_t, rtk_rate_storm_group_t, rtk_enable_t *); + rtk_api_ret_t (*storm_bypass_set)(rtk_storm_bypass_t, rtk_enable_t); + rtk_api_ret_t (*storm_bypass_get)(rtk_storm_bypass_t, rtk_enable_t *); + rtk_api_ret_t (*rate_stormControlExtPortmask_set)(rtk_uint32); + rtk_api_ret_t (*rate_stormControlExtPortmask_get)(rtk_uint32 *); + rtk_api_ret_t (*rate_stormControlExtEnable_set)(rtk_rate_storm_group_t, rtk_enable_t); + rtk_api_ret_t (*rate_stormControlExtEnable_get)(rtk_rate_storm_group_t, rtk_enable_t *); + rtk_api_ret_t (*rate_stormControlExtMeterIdx_set)(rtk_rate_storm_group_t, rtk_uint32); + rtk_api_ret_t (*rate_stormControlExtMeterIdx_get)(rtk_rate_storm_group_t, rtk_uint32 *); + + /* Rate */ + rtk_api_ret_t (*rate_shareMeter_set)(rtk_meter_id_t, rtk_meter_type_t, rtk_rate_t, rtk_enable_t); + rtk_api_ret_t (*rate_shareMeter_get)(rtk_meter_id_t, rtk_meter_type_t *, rtk_rate_t *, rtk_enable_t *); + rtk_api_ret_t (*rate_shareMeterBucket_set)(rtk_meter_id_t, rtk_uint32); + rtk_api_ret_t (*rate_shareMeterBucket_get)(rtk_meter_id_t, rtk_uint32 *); + rtk_api_ret_t (*rate_shareMeterExceedStatus_set)(rtk_uint32); + rtk_api_ret_t (*rate_shareMeterExceedStatus_get)(rtk_uint32, rtk_uint32 *); + rtk_api_ret_t (*rate_shareMeterICPUExceedStatus_set)(rtk_uint32); + rtk_api_ret_t (*rate_shareMeterICPUExceedStatus_get)(rtk_uint32, rtk_uint32 *); + + /*QoS*/ + rtk_api_ret_t (*qos_init)(void); + rtk_api_ret_t (*qos_priSel_set)(rtk_qos_priDecTbl_t, rtk_priority_select_t *); + rtk_api_ret_t (*qos_priSel_get)(rtk_qos_priDecTbl_t, rtk_priority_select_t *); + rtk_api_ret_t (*qos_1pPriRemap_set)(rtk_pri_t, rtk_pri_t); + rtk_api_ret_t (*qos_1pPriRemap_get)(rtk_pri_t, rtk_pri_t *); + rtk_api_ret_t (*qos_1pRemarkSrcSel_set)(rtk_qos_1pRmkSrc_t ); + rtk_api_ret_t (*qos_1pRemarkSrcSel_get)(rtk_qos_1pRmkSrc_t *); + rtk_api_ret_t (*qos_dscpPriRemap_set)(rtk_dscp_t, rtk_pri_t ); + rtk_api_ret_t (*qos_dscpPriRemap_get)(rtk_dscp_t, rtk_pri_t *); + rtk_api_ret_t (*qos_rspanpriRemap_set)(rtk_pri_t, rtk_pri_t); + rtk_api_ret_t (*qos_rspanpriRemap_get)(rtk_pri_t, rtk_pri_t *); + rtk_api_ret_t (*qos_portPri_set)(rtk_port_t, rtk_pri_t ) ; + rtk_api_ret_t (*qos_portPri_get)(rtk_port_t, rtk_pri_t *) ; + rtk_api_ret_t (*qos_priMap_set)(rtk_port_t, rtk_qos_pri2queue_t *); + rtk_api_ret_t (*qos_priMap_get)(rtk_port_t, rtk_qos_pri2queue_t *); + rtk_api_ret_t (*qos_schedulingQueue_set)(rtk_port_t, rtk_qos_queue_weights_t *); + rtk_api_ret_t (*qos_schedulingQueue_get)(rtk_port_t, rtk_qos_queue_weights_t *); + rtk_api_ret_t (*qos_1pRemarkEnable_set)(rtk_port_t, rtk_enable_t); + rtk_api_ret_t (*qos_1pRemarkEnable_get)(rtk_port_t, rtk_enable_t *); + rtk_api_ret_t (*qos_1pRemark_set)(rtk_pri_t, rtk_pri_t); + rtk_api_ret_t (*qos_1pRemark_get)(rtk_pri_t, rtk_pri_t *); + rtk_api_ret_t (*qos_dscpRemarkEnable_set)(rtk_port_t, rtk_enable_t); + rtk_api_ret_t (*qos_dscpRemarkEnable_get)(rtk_port_t, rtk_enable_t *); + rtk_api_ret_t (*qos_intpri2dscpRemark_set)(rtk_pri_t , rtk_dscp_t ); + rtk_api_ret_t (*qos_intpri2dscpRemark_get)(rtk_pri_t, rtk_dscp_t *); + rtk_api_ret_t (*qos_dscp2dscpRemark_set)(rtk_pri_t , rtk_dscp_t ); + rtk_api_ret_t (*qos_dscp2dscpRemark_get)(rtk_pri_t, rtk_dscp_t *); + rtk_api_ret_t (*qos_dscpRemarkSrcSel_set)(rtk_qos_dscpRmkSrc_t); + rtk_api_ret_t (*qos_dscpRemarkSrcSel_get)(rtk_qos_dscpRmkSrc_t *); + rtk_api_ret_t (*qos_portPriSelIndex_set)(rtk_port_t, rtk_qos_priDecTbl_t); + rtk_api_ret_t (*qos_portPriSelIndex_get)(rtk_port_t, rtk_qos_priDecTbl_t *); + rtk_api_ret_t (*qos_schedulingType_set)(rtk_port_t, rtk_qos_scheduling_type_t); + rtk_api_ret_t (*qos_schedulingType_get)(rtk_port_t, rtk_qos_scheduling_type_t *); + + /*VLAN*/ + rtk_api_ret_t (*vlan_init)(void); + rtk_api_ret_t (*vlan_set)(rtk_vlan_t, rtk_vlan_entry_t *); + rtk_api_ret_t (*vlan_get)(rtk_vlan_t, rtk_vlan_entry_t *); + rtk_api_ret_t (*vlan_egrFilterEnable_set)(rtk_enable_t); + rtk_api_ret_t (*vlan_egrFilterEnable_get)(rtk_enable_t *); + rtk_api_ret_t (*vlan_portPvid_set)(rtk_port_t, rtk_vlan_t); + rtk_api_ret_t (*vlan_portPvid_get)(rtk_port_t, rtk_vlan_t *); + rtk_api_ret_t (*vlan_portIgrFilterEnable_set)(rtk_port_t, rtk_enable_t); + rtk_api_ret_t (*vlan_portIgrFilterEnable_get)(rtk_port_t, rtk_enable_t *); + rtk_api_ret_t (*vlan_portAcceptFrameType_set)(rtk_port_t, rtk_vlan_acceptFrameType_t); + rtk_api_ret_t (*vlan_portAcceptFrameType_get)(rtk_port_t, rtk_vlan_acceptFrameType_t *); + rtk_api_ret_t (*vlan_tagMode_set)(rtk_port_t, rtk_vlan_egressTagMode_t); + rtk_api_ret_t (*vlan_tagMode_get)(rtk_port_t, rtk_vlan_egressTagMode_t *); + rtk_api_ret_t (*vlan_transparent_set)(rtk_port_t, rtk_portmask_t *); + rtk_api_ret_t (*vlan_transparent_get)(rtk_port_t , rtk_portmask_t *); + rtk_api_ret_t (*vlan_keep_set)(rtk_port_t, rtk_portmask_t *); + rtk_api_ret_t (*vlan_keep_get)(rtk_port_t, rtk_portmask_t *); + rtk_api_ret_t (*vlan_stg_set)(rtk_vlan_t, rtk_stp_msti_id_t); + rtk_api_ret_t (*vlan_stg_get)(rtk_vlan_t, rtk_stp_msti_id_t *); + rtk_api_ret_t (*vlan_portFid_set)(rtk_port_t port, rtk_enable_t, rtk_fid_t); + rtk_api_ret_t (*vlan_portFid_get)(rtk_port_t port, rtk_enable_t *, rtk_fid_t *); + rtk_api_ret_t (*vlan_reservedVidAction_set)(rtk_vlan_resVidAction_t, rtk_vlan_resVidAction_t); + rtk_api_ret_t (*vlan_reservedVidAction_get)(rtk_vlan_resVidAction_t *, rtk_vlan_resVidAction_t *); + rtk_api_ret_t (*vlan_realKeepRemarkEnable_set)(rtk_enable_t ); + rtk_api_ret_t (*vlan_realKeepRemarkEnable_get)(rtk_enable_t *); + rtk_api_ret_t (*vlan_disL2Learn_entry_set)(rtk_vlan_disL2_learn_t *); + rtk_api_ret_t (*vlan_disL2Learn_entry_get)(rtk_uint32, rtk_vlan_disL2_learn_t *); + rtk_api_ret_t (*vlan_reset)(void); + + /*dot1x*/ + rtk_api_ret_t (*dot1x_unauthPacketOper_set)(rtk_port_t, rtk_dot1x_unauth_action_t); + rtk_api_ret_t (*dot1x_unauthPacketOper_get)(rtk_port_t, rtk_dot1x_unauth_action_t *); + // rtk_api_ret_t (*dot1x_eapolFrame2CpuEnable_set)(rtk_enable_t); + //rtk_api_ret_t (*dot1x_eapolFrame2CpuEnable_get)(rtk_enable_t *); + rtk_api_ret_t (*dot1x_trap2CPU_Sel_set)(rtk_dot1x_cpu_select_t ); + rtk_api_ret_t (*dot1x_trap2CPU_Sel_get)(rtk_dot1x_cpu_select_t *); + rtk_api_ret_t (*dot1x_trap_priority_set)(rtk_pri_t ); + rtk_api_ret_t (*dot1x_trap_priority_get)(rtk_pri_t *); + rtk_api_ret_t (*dot1x_portBasedEnable_set)(rtk_port_t , rtk_enable_t); + rtk_api_ret_t (*dot1x_portBasedEnable_get)(rtk_port_t , rtk_enable_t *); + rtk_api_ret_t (*dot1x_portBasedAuthStatus_set)(rtk_port_t, rtk_dot1x_auth_status_t); + rtk_api_ret_t (*dot1x_portBasedAuthStatus_get)(rtk_port_t, rtk_dot1x_auth_status_t *); + rtk_api_ret_t (*dot1x_portBasedDirection_set)(rtk_port_t, rtk_dot1x_direction_t); + rtk_api_ret_t (*dot1x_portBasedDirection_get)(rtk_port_t, rtk_dot1x_direction_t *); + rtk_api_ret_t (*dot1x_macBasedEnable_set)(rtk_port_t, rtk_enable_t); + rtk_api_ret_t (*dot1x_macBasedEnable_get)(rtk_port_t , rtk_enable_t *); + rtk_api_ret_t (*dot1x_macBasedAuthMac_add)(rtk_port_t, rtk_mac_t *, rtk_fid_t); + rtk_api_ret_t (*dot1x_macBasedAuthMac_del)(rtk_port_t, rtk_mac_t *, rtk_fid_t); + rtk_api_ret_t (*dot1x_macBasedDirection_set)(rtk_dot1x_direction_t); + rtk_api_ret_t (*dot1x_macBasedDirection_get)(rtk_dot1x_direction_t *); + rtk_api_ret_t (*dot1x_guestVlan_set)(rtk_vlan_t ); + rtk_api_ret_t (*dot1x_guestVlan_get)(rtk_vlan_t *); + rtk_api_ret_t (*dot1x_guestVlan2Auth_set)(rtk_enable_t); + rtk_api_ret_t (*dot1x_guestVlan2Auth_get)(rtk_enable_t *); + + /*MACsec*/ + rtk_api_ret_t (*macsec_enable_set)(rtk_uint32, rtk_uint32, rtk_uint32); + rtk_api_ret_t(*macsec_enable_get)(rtk_uint32, rtk_uint32 *, rtk_uint32 *); + rtk_api_ret_t(*macsec_egress_set)(rtk_uint32 , rtk_uint32 , rtk_uint32); + rtk_api_ret_t(*macsec_egress_get)(rtk_uint32 , rtk_uint32 , rtk_uint32 *); + rtk_api_ret_t(*macsec_ingress_set)(rtk_uint32 , rtk_uint32 , rtk_uint32); + rtk_api_ret_t(*macsec_ingress_get)(rtk_uint32 , rtk_uint32 , rtk_uint32 *); + rtk_api_ret_t(*macsec_rxgating_set)(rtk_uint32); + rtk_api_ret_t(*macsec_rxgating_cancel)(rtk_uint32); + rtk_api_ret_t(*macsec_txgating_set)(rtk_uint32); + rtk_api_ret_t(*macsec_txgating_cancel)(rtk_uint32); + rtk_api_ret_t(*macsec_rxIPbypass_set)(rtk_uint32, rtk_uint32); + rtk_api_ret_t(*macsec_rxIPbypass_get)(rtk_uint32, rtk_uint32 *); + rtk_api_ret_t(*macsec_txIPbypass_set)(rtk_uint32, rtk_uint32); + rtk_api_ret_t(*macsec_txIPbypass_get)(rtk_uint32, rtk_uint32 *); + rtk_api_ret_t(*macsec_rxbypass_set)(rtk_uint32, rtk_uint32); + rtk_api_ret_t(*macsec_rxbypass_get)(rtk_uint32, rtk_uint32 *); + rtk_api_ret_t(*macsec_txbypass_set)(rtk_uint32, rtk_uint32); + rtk_api_ret_t(*macsec_txbypass_get)(rtk_uint32, rtk_uint32 *); + rtk_api_ret_t(*wrapper_int_control_set)(rtk_uint32, rtk_macsec_int_type_t, rtk_enable_t); + rtk_api_ret_t(*wrapper_int_control_get)(rtk_uint32, rtk_macsec_int_type_t, rtk_enable_t *); + rtk_api_ret_t(*wrapper_int_status_set)(rtk_uint32, rtk_uint32); + rtk_api_ret_t(*wrapper_int_status_get)(rtk_uint32, rtk_uint32 *); + rtk_api_ret_t(*wrapper_mib_reset)(rtk_uint32, rtk_uint32); + rtk_api_ret_t(*wrapper_mib_counter)(rtk_uint32, RTL8373_WRAPPER_MIBCOUNTER, rtk_uint64 *); + rtk_api_ret_t(*macsec_ipg_len_set)(rtk_uint32, rtk_uint32); + rtk_api_ret_t(*macsec_ipg_len_get)(rtk_uint32, rtk_uint32 *); + rtk_api_ret_t(*macsec_ipg_mode_set)(rtk_uint32, rtk_uint32); + rtk_api_ret_t(*macsec_ipg_mode_get)(rtk_uint32, rtk_uint32 *); + rtk_api_ret_t(*macsec_eth_set)(rtk_uint32, rtk_uint32, rtk_uint32); + rtk_api_ret_t(*macsec_eth_get)(rtk_uint32, rtk_uint32, rtk_uint32 *); + rtk_api_ret_t(*macsec_init)(rtk_uint32); + + /*SVLAN*/ + rtk_api_ret_t (*svlan_init)(void); + rtk_api_ret_t (*svlan_servicePort_add)(rtk_port_t ); + rtk_api_ret_t (*svlan_servicePort_get)(rtk_portmask_t *); + rtk_api_ret_t (*svlan_servicePort_del)(rtk_port_t); + rtk_api_ret_t (*svlan_tpidEntry_set)(rtk_uint32); + rtk_api_ret_t (*svlan_tpidEntry_get)(rtk_uint32 *); + rtk_api_ret_t (*svlan_priorityRef_set)(rtk_svlan_pri_ref_t); + rtk_api_ret_t (*svlan_priorityRef_get)(rtk_svlan_pri_ref_t *); + //rtk_api_ret_t (*svlan_memberPortEntry_set)(rtk_uint32, rtk_svlan_memberCfg_t *); + //rtk_api_ret_t (*svlan_memberPortEntry_get)(rtk_uint32, rtk_svlan_memberCfg_t *); + //rtk_api_ret_t (*svlan_memberPortEntry_adv_set)(rtk_uint32, rtk_svlan_memberCfg_t *); + //rtk_api_ret_t (*svlan_memberPortEntry_adv_get)(rtk_uint32, rtk_svlan_memberCfg_t *); + rtk_api_ret_t (*svlan_defaultSvlan_set)(rtk_port_t, rtk_vlan_t); + rtk_api_ret_t (*svlan_defaultSvlan_get)(rtk_port_t, rtk_vlan_t *); + rtk_api_ret_t (*svlan_c2s_add)(rtk_vlan_t, rtk_port_t, rtk_vlan_t); + rtk_api_ret_t (*svlan_c2s_del)(rtk_vlan_t, rtk_port_t); + rtk_api_ret_t (*svlan_c2s_get)(rtk_vlan_t, rtk_port_t, rtk_vlan_t *); + rtk_api_ret_t (*svlan_untag_action_set)(rtk_svlan_untag_action_t, rtk_vlan_t); + rtk_api_ret_t (*svlan_untag_action_get)(rtk_svlan_untag_action_t *, rtk_vlan_t *); + rtk_api_ret_t (*svlan_trapPri_set)(rtk_pri_t); + rtk_api_ret_t (*svlan_trapPri_get)(rtk_pri_t *); + rtk_api_ret_t (*svlan_unassign_action_set)(rtk_svlan_unassign_action_t); + rtk_api_ret_t (*svlan_unassign_action_get)(rtk_svlan_unassign_action_t *); + rtk_api_ret_t (*svlan_trapCpuMsk_set)(rtk_uint32); + rtk_api_ret_t (*svlan_trapCpuMsk_get)(rtk_uint32 *); + + /*NIC*/ + rtk_api_ret_t (*nic_rst_set)(void); + rtk_api_ret_t (*nic_txStopAddr_set)( rtk_uint32 ); + rtk_api_ret_t (*nic_txStopAddr_get)(rtk_uint32 *); + rtk_api_ret_t (*nic_rxStopAddr_set)( rtk_uint32 ); + rtk_api_ret_t (*nic_rxStopAddr_get)(rtk_uint32 *); + rtk_api_ret_t (*nic_swRxCurPktAddr_get)(rtk_uint32 *); + rtk_api_ret_t (*nic_rxReceivedPktLen_get)(rtk_uint32 *); + rtk_api_ret_t (*nic_txAvailSpace_get)(rtk_uint32 *); + rtk_api_ret_t (*nic_moduleEn_set)(rtk_enable_t ); + rtk_api_ret_t (*nic_moduleEn_get)(rtk_enable_t *); + rtk_api_ret_t (*nic_rxEn_set)(rtk_enable_t ); + rtk_api_ret_t (*nic_rxEn_get)(rtk_enable_t *); + rtk_api_ret_t (*nic_txEn_set)(rtk_enable_t ); + rtk_api_ret_t (*nic_txEn_get)(rtk_enable_t *); + rtk_api_ret_t (*nic_rxRemoveCrc_set)(rtk_enable_t ); + rtk_api_ret_t (*nic_rxRemoveCrc_get)(rtk_enable_t *); + rtk_api_ret_t (*nic_rxPaddingEn_set)(rtk_enable_t ); + rtk_api_ret_t (*nic_rxPaddingEn_get)(rtk_enable_t *); + rtk_api_ret_t (*nic_rxFreeSpaceThd_set)(rtk_uint32 ); + rtk_api_ret_t (*nic_rxFreeSpaceThd_get)(rtk_uint32 *); + rtk_api_ret_t (*nic_rxCrcErrEn_set)(rtk_enable_t ); + rtk_api_ret_t (*nic_rxCrcErrEn_get)(rtk_enable_t *); + rtk_api_ret_t (*nic_rxL3CrcErrEn_set)(rtk_enable_t ); + rtk_api_ret_t (*nic_rxL3CrcErrEn_get)(rtk_enable_t *); + rtk_api_ret_t (*nic_rxL4CrcErrEn_set)(rtk_enable_t ); + rtk_api_ret_t (*nic_rxL4CrcErrEn_get)(rtk_enable_t *); + rtk_api_ret_t (*nic_rxArpEn_set)(rtk_enable_t ); + rtk_api_ret_t (*nic_rxArpEn_get)(rtk_enable_t *); + rtk_api_ret_t (*nic_rxAllPktEn_set)(rtk_enable_t ); + rtk_api_ret_t (*nic_rxAllPktEn_get)(rtk_enable_t *); + rtk_api_ret_t (*nic_rxPhyPktSel_set)(rtk_nic_rxpps_t ); + rtk_api_ret_t (*nic_rxPhyPktSel_get)(rtk_nic_rxpps_t *); + rtk_api_ret_t (*nic_rxMultiPktEn_set)(rtk_enable_t ); + rtk_api_ret_t (*nic_rxMultiPktEn_get)(rtk_enable_t *); + rtk_api_ret_t (*nic_rxBcPktEn_set)(rtk_enable_t ); + rtk_api_ret_t (*nic_rxBcPktEn_get)(rtk_enable_t *); + rtk_api_ret_t (*nic_mcHashFltrEn_set)(rtk_enable_t ); + rtk_api_ret_t (*nic_mcHashFltrEn_get)(rtk_enable_t *); + rtk_api_ret_t (*nic_phyPktHashFltrEn_set)(rtk_enable_t ); + rtk_api_ret_t (*nic_phyPktHashFltrEn_get)(rtk_enable_t *); + rtk_api_ret_t (*nic_mcHashTblVal_set)(rtk_nic_hashValType_t, rtk_uint32 ); + rtk_api_ret_t (*nic_mcHashTblVal_get)(rtk_nic_hashValType_t, rtk_uint32 *); + rtk_api_ret_t (*nic_phyPktHashTblVal_set)(rtk_nic_hashValType_t, rtk_uint32 ); + rtk_api_ret_t (*nic_phyPktHashTblVal_get)(rtk_nic_hashValType_t, rtk_uint32 *); + rtk_api_ret_t (*nic_rxMTU_set)(rtk_nic_RxMTU_t ); + rtk_api_ret_t (*nic_rxMTU_get)(rtk_nic_RxMTU_t *); + rtk_api_ret_t (*nic_loopbackEn_set)(rtk_enable_t ); + rtk_api_ret_t (*nic_loopbackEn_get)(rtk_enable_t *); + rtk_api_ret_t (*nic_interruptEn_set)(rtk_enable_t, rtk_enable_t ); + rtk_api_ret_t (*nic_interruptEn_get)(rtk_enable_t *, rtk_enable_t *); + rtk_api_ret_t (*nic_interruptStatus_get)(rtk_uint32 * , rtk_uint32 *); + rtk_api_ret_t (*nic_interruptStatus_clear)(rtk_uint32 , rtk_uint32 ); + + /* Time */ + rtk_api_ret_t (*time_init)(rtk_portmask_t); + rtk_api_ret_t (*time_portPtpbypassptpEn_get)(rtk_port_t , rtk_enable_t *); + rtk_api_ret_t (*time_portPtpbypassptpEn_set)(rtk_port_t , rtk_enable_t ); + rtk_api_ret_t (*time_portPtpEnable_get)(rtk_port_t ,rtk_ptp_header_t, rtk_enable_t *); + rtk_api_ret_t (*time_portPtpEnable_set)(rtk_port_t ,rtk_ptp_header_t,rtk_enable_t ); + rtk_api_ret_t (*time_portPtpOper_triger)(void); + + rtk_api_ret_t (*time_portRefTime_get)( rtk_time_timeStamp_t *); + rtk_api_ret_t (*time_portRefTime_set)( rtk_time_timeStamp_t ,rtk_enable_t); + rtk_api_ret_t (*time_portRefTimeAdjust_set)( rtk_uint32 , rtk_time_timeStamp_t, rtk_enable_t apply); + rtk_api_ret_t (*time_portRefTimeEnable_get)( rtk_enable_t *); + rtk_api_ret_t (*time_portRefTimeEnable_set)( rtk_enable_t ); + + + + rtk_api_ret_t (*time_portPtpVlanTpid_get)( rtk_vlanType_t , rtk_uint32 , rtk_uint32 *); + rtk_api_ret_t (*time_portPtpVlanTpid_set)(rtk_vlanType_t , rtk_uint32 , rtk_uint32 ); + rtk_api_ret_t (*time_portPtpOper_get)(rtk_time_operCfg_t *); + rtk_api_ret_t (*time_portPtpOper_set)( rtk_time_operCfg_t ); + rtk_api_ret_t (*time_portPtpLatchTime_get)( rtk_time_timeStamp_t *); + rtk_api_ret_t (*time_portPtpRefTimeFreqCfg_get)(rtk_uint32 *, rtk_uint32 *); + rtk_api_ret_t (*time_portPtpRefTimeFreqCfg_set)(rtk_uint32, rtk_enable_t); + rtk_api_ret_t (*time_portPtpTxInterruptStatus_get)( rtk_uint32 *); + rtk_api_ret_t (*time_portPtpTxTimestampFifo_get)(rtk_time_txTimeEntry_t *); + rtk_api_ret_t (*time_portPtp1PPSOutput_get)(rtk_uint32 *, rtk_enable_t *); + rtk_api_ret_t (*time_portPtp1PPSOutput_set)( rtk_uint32, rtk_enable_t); + rtk_api_ret_t (*time_portPtpClockOutput_get)( rtk_time_clkOutput_t*); + rtk_api_ret_t (*time_portPtpClockOutput_set)( rtk_time_clkOutput_t ); + rtk_api_ret_t (*time_portPtpClkSrcCtrl_get)( rtk_enable_t *); + rtk_api_ret_t (*time_portPtpClkSrcCtrl_set)( rtk_enable_t ); + rtk_api_ret_t (*time_portPtpToddelay_get)( rtk_uint32 *); + rtk_api_ret_t (*time_portPtpToddelay_set)( rtk_uint32 ); + rtk_api_ret_t (*time_portPtpOutputSigSel_get)( rtk_time_outSigSel_t *); + rtk_api_ret_t (*time_portPtpOutputSigSel_set)( rtk_time_outSigSel_t); + rtk_api_ret_t (*time_portPtpPortctrl_get)( rtk_port_t, rtk_ptp_port_ctrl_t*); + rtk_api_ret_t (*time_portPtpPortctrl_set)(rtk_port_t, rtk_ptp_port_ctrl_t); + + + + /*PTP*/ + rtk_api_ret_t (*ptp_intControl_set)(rtk_ptp_intType_t , rtk_enable_t); + rtk_api_ret_t (*ptp_intControl_get)(rtk_ptp_intType_t,rtk_enable_t *); + rtk_api_ret_t (*ptp_intStatus_get)( rtk_ptp_intStatus_t *); + rtk_api_ret_t (*ptp_portTrap_set)(rtk_port_t, rtk_ptp_porttrap_ctrl_t *); + rtk_api_ret_t (*ptp_portTrap_get)(rtk_port_t, rtk_ptp_porttrap_ctrl_t *); +#if 1 + /*RLDP*/ + rtk_api_ret_t (*rldp_config_set)(rtk_rldp_config_t *); + rtk_api_ret_t (*rldp_config_get)(rtk_rldp_config_t *); + rtk_api_ret_t (*rldp_portConfig_set)(rtk_port_t, rtk_rldp_portConfig_t *); + rtk_api_ret_t (*rldp_portConfig_get)(rtk_port_t, rtk_rldp_portConfig_t *); + rtk_api_ret_t (*rldp_status_get)(rtk_rldp_status_t *); + rtk_api_ret_t (*rldp_portStatus_get)(rtk_port_t, rtk_rldp_portStatus_t *); + rtk_api_ret_t (*rldp_portStatus_set)(rtk_port_t, rtk_rldp_portStatus_t *); + rtk_api_ret_t (*rldp_portLoopPair_get)(rtk_port_t, rtk_portmask_t *); +#endif + /*trunk*/ + rtk_api_ret_t (*trunk_port_set)(rtk_trunk_group_t, rtk_portmask_t *); + rtk_api_ret_t (*trunk_port_get)(rtk_trunk_group_t, rtk_portmask_t *); + rtk_api_ret_t (*trunk_distributionAlgorithm_set)(rtk_trunk_group_t, rtk_uint32); + rtk_api_ret_t (*trunk_distributionAlgorithm_get)(rtk_trunk_group_t, rtk_uint32 *); + rtk_api_ret_t (*trunk_trafficSeparate_set)(rtk_trunk_group_t, rtk_trunk_separateType_t); + rtk_api_ret_t (*trunk_trafficSeparate_get)(rtk_trunk_group_t, rtk_trunk_separateType_t *); + rtk_api_ret_t (*trunk_mode_set)(rtk_trunk_mode_t); + rtk_api_ret_t (*trunk_mode_get)(rtk_trunk_mode_t *); + rtk_api_ret_t (*trunk_trafficPause_set)(rtk_trunk_group_t, rtk_enable_t); + rtk_api_ret_t (*trunk_trafficPause_get)(rtk_trunk_group_t, rtk_enable_t *); + rtk_api_ret_t (*trunk_hashMappingTable_set)(rtk_trunk_group_t, rtk_trunk_hashVal2Port_t *); + rtk_api_ret_t (*trunk_hashMappingTable_get)(rtk_trunk_group_t, rtk_trunk_hashVal2Port_t *); + rtk_api_ret_t (*trunk_portQueueEmpty_get)(rtk_portmask_t *); + + /* interrupt */ + rtk_api_ret_t (*int_enable)(rtk_enable_t); + rtk_api_ret_t (*int_polarity_set)(rtk_int_polarity_t); + rtk_api_ret_t (*int_polarity_get)(rtk_int_polarity_t *); + rtk_api_ret_t (*int_control_set)(rtk_port_t, rtk_int_cpu_t, rtk_int_type_t, rtk_enable_t); + rtk_api_ret_t (*int_control_get)(rtk_port_t, rtk_int_cpu_t, rtk_int_type_t, rtk_enable_t *); + rtk_api_ret_t (*int_miscIMR_set)(rtk_uint32 , interrupt_misc_t , rtk_uint32 ); + rtk_api_ret_t (*int_miscIMR_get)(rtk_uint32 , interrupt_misc_t , rtk_uint32* ); + rtk_api_ret_t (*int_miscISR_clear)(rtk_uint32 , interrupt_misc_t ); + rtk_api_ret_t (*int_miscISR_get)(rtk_uint32 , interrupt_misc_t , rtk_uint32* ); + + /*RMA*/ + rtk_api_ret_t (*rma_set)(rtk_uint32, rtk_rmaParam_t *); + rtk_api_ret_t (*rma_get)(rtk_uint32, rtk_rmaParam_t *); + + /*led*/ + rtk_api_ret_t (*led_blinkRate_set)(rtk_led_blink_rate_t); + rtk_api_ret_t (*led_blinkRate_get)(rtk_led_blink_rate_t *); + rtk_api_ret_t (*led_groupConfig_set)(rtk_led_set_t, rtk_uint32, rtk_led_config_t *); + rtk_api_ret_t (*led_portSelConfig_set)(rtk_port_t, rtk_led_set_t); + rtk_api_ret_t (*led_portSelConfig_get)(rtk_port_t, rtk_led_set_t * ); +#if 0 + /*leaky*/ + rtk_api_ret_t (*leaky_vlan_set)(rtk_leaky_type_t, rtk_enable_t); + rtk_api_ret_t (*leaky_vlan_get)(rtk_leaky_type_t, rtk_enable_t *); + rtk_api_ret_t (*leaky_portIsolation_set)(rtk_leaky_type_t, rtk_enable_t); + rtk_api_ret_t (*leaky_portIsolation_get)(rtk_leaky_type_t, rtk_enable_t *); + + /* led */ + rtk_api_ret_t (*led_enable_set)(rtk_led_group_t, rtk_portmask_t *); + rtk_api_ret_t (*led_enable_get)(rtk_led_group_t, rtk_portmask_t *); + rtk_api_ret_t (*led_operation_set)(rtk_led_operation_t ); + rtk_api_ret_t (*led_operation_get)(rtk_led_operation_t *); + rtk_api_ret_t (*led_modeForce_set)(rtk_port_t, rtk_led_group_t, rtk_led_force_mode_t); + rtk_api_ret_t (*led_modeForce_get)(rtk_port_t, rtk_led_group_t, rtk_led_force_mode_t *); + rtk_api_ret_t (*led_blinkRate_set)(rtk_led_blink_rate_t); + rtk_api_ret_t (*led_blinkRate_get)(rtk_led_blink_rate_t *); + rtk_api_ret_t (*led_groupConfig_set)(rtk_led_group_t, rtk_led_congig_t); + rtk_api_ret_t (*led_groupConfig_get)(rtk_led_group_t, rtk_led_congig_t *); + rtk_api_ret_t (*led_groupAbility_set)(rtk_led_group_t, rtk_led_ability_t *); + rtk_api_ret_t (*led_groupAbility_get)(rtk_led_group_t, rtk_led_ability_t *); + rtk_api_ret_t (*led_serialMode_set)(rtk_led_active_t); + rtk_api_ret_t (*led_serialMode_get)(rtk_led_active_t *); + rtk_api_ret_t (*led_OutputEnable_set)(rtk_enable_t); + rtk_api_ret_t (*led_OutputEnable_get)(rtk_enable_t *); + rtk_api_ret_t (*led_serialModePortmask_set)(rtk_led_serialOutput_t, rtk_portmask_t *); + rtk_api_ret_t (*led_serialModePortmask_get)(rtk_led_serialOutput_t *, rtk_portmask_t *); + + /* oam */ + rtk_api_ret_t (*oam_init)(void); + rtk_api_ret_t (*oam_state_set)(rtk_enable_t); + rtk_api_ret_t (*oam_state_get)(rtk_enable_t *); + rtk_api_ret_t (*oam_parserAction_set)(rtk_port_t, rtk_oam_parser_act_t ); + rtk_api_ret_t (*oam_parserAction_get)(rtk_port_t, rtk_oam_parser_act_t *); + rtk_api_ret_t (*oam_multiplexerAction_set)(rtk_port_t, rtk_oam_multiplexer_act_t ); + rtk_api_ret_t (*oam_multiplexerAction_get)(rtk_port_t, rtk_oam_multiplexer_act_t *); + + rtk_api_ret_t (*port_rgmiiDelayExt_set)(rtk_port_t, rtk_data_t, rtk_data_t); + rtk_api_ret_t (*port_rgmiiDelayExt_get)(rtk_port_t, rtk_data_t *, rtk_data_t *); + rtk_api_ret_t (*port_phyEnableAll_set)(rtk_enable_t); + rtk_api_ret_t (*port_phyEnableAll_get)(rtk_enable_t *); + rtk_api_ret_t (*port_efid_set)(rtk_port_t, rtk_data_t); + rtk_api_ret_t (*port_efid_get)(rtk_port_t, rtk_data_t *); + rtk_api_ret_t (*port_phyComboPortMedia_set)(rtk_port_t, rtk_port_media_t); + rtk_api_ret_t (*port_phyComboPortMedia_get)(rtk_port_t, rtk_port_media_t *); + rtk_api_ret_t (*port_rtctEnable_set)(rtk_portmask_t *); + rtk_api_ret_t (*port_rtctDisable_set)(rtk_portmask_t *); + rtk_api_ret_t (*port_rtctResult_get)(rtk_port_t, rtk_rtctResult_t *); + rtk_api_ret_t (*port_sds_reset)(rtk_port_t); + rtk_api_ret_t (*port_sgmiiLinkStatus_get)(rtk_port_t, rtk_data_t *, rtk_data_t *, rtk_port_linkStatus_t *); + rtk_api_ret_t (*port_sgmiiNway_set)(rtk_port_t, rtk_enable_t); + rtk_api_ret_t (*port_sgmiiNway_get)(rtk_port_t, rtk_enable_t *); + rtk_api_ret_t (*port_fiberAbilityExt_set)(rtk_port_t, rtk_uint32, rtk_uint32); + rtk_api_ret_t (*port_fiberAbilityExt_get)(rtk_port_t, rtk_uint32 *, rtk_uint32 *); +#endif + + rtk_api_ret_t (*port_autoDos_set)(rtk_port_autoDosType_t, rtk_enable_t); + rtk_api_ret_t (*port_autoDos_get)(rtk_port_autoDosType_t, rtk_enable_t *); +#if 0 + /* stat */ + rtk_api_ret_t (*stat_global_reset)(void); + rtk_api_ret_t (*stat_port_reset)(rtk_port_t); + rtk_api_ret_t (*stat_queueManage_reset)(void); + rtk_api_ret_t (*stat_global_get)(rtk_stat_global_type_t, rtk_stat_counter_t *); + rtk_api_ret_t (*stat_global_getAll)(rtk_stat_global_cntr_t *); + rtk_api_ret_t (*stat_port_get)(rtk_port_t, rtk_stat_port_type_t, rtk_stat_counter_t *); + rtk_api_ret_t (*stat_port_getAll)(rtk_port_t, rtk_stat_port_cntr_t *); + rtk_api_ret_t (*stat_logging_counterCfg_set)(rtk_uint32, rtk_logging_counter_mode_t, rtk_logging_counter_type_t); + rtk_api_ret_t (*stat_logging_counterCfg_get)(rtk_uint32, rtk_logging_counter_mode_t *, rtk_logging_counter_type_t *); + rtk_api_ret_t (*stat_logging_counter_reset)(rtk_uint32); + rtk_api_ret_t (*stat_logging_counter_get)(rtk_uint32, rtk_uint32 *); + rtk_api_ret_t (*stat_lengthMode_set)(rtk_stat_lengthMode_t, rtk_stat_lengthMode_t); + rtk_api_ret_t (*stat_lengthMode_get)(rtk_stat_lengthMode_t *, rtk_stat_lengthMode_t *); +#endif + /* l2 */ + rtk_api_ret_t (*l2_init)(void); + rtk_api_ret_t (*l2_addr_add)(rtk_mac_t *, rtk_l2_ucastAddr_t *); + rtk_api_ret_t (*l2_addr_get)(rtk_mac_t *, rtk_l2_ucastAddr_t *); + rtk_api_ret_t (*l2_addr_next_get)(rtk_l2_read_method_t, rtk_port_t, rtk_uint32 *, rtk_l2_ucastAddr_t *); + rtk_api_ret_t (*l2_addr_del)(rtk_mac_t *, rtk_l2_ucastAddr_t *); + rtk_api_ret_t (*l2_mcastAddr_add)(rtk_l2_mcastAddr_t *); + rtk_api_ret_t (*l2_mcastAddr_get)(rtk_l2_mcastAddr_t *); + rtk_api_ret_t (*l2_mcastAddr_next_get)(rtk_uint32 *, rtk_l2_mcastAddr_t *); + rtk_api_ret_t (*l2_mcastAddr_del)(rtk_l2_mcastAddr_t *); + rtk_api_ret_t (*l2_ipMcastAddr_add)(rtk_l2_ipMcastAddr_t *); + rtk_api_ret_t (*l2_ipMcastAddr_get)(rtk_l2_ipMcastAddr_t *); + rtk_api_ret_t (*l2_ipMcastAddr_next_get)(rtk_uint32 *, rtk_l2_ipMcastAddr_t *); + rtk_api_ret_t (*l2_ipMcastAddr_del)(rtk_l2_ipMcastAddr_t *); + rtk_api_ret_t (*l2_ucastAddr_flush)(rtk_l2_flushCfg_t *); + rtk_api_ret_t (*l2_table_clear)(void); + rtk_api_ret_t (*l2_table_clearStatus_get)(rtk_l2_clearStatus_t *); + rtk_api_ret_t (*l2_flushLinkDownPortAddrEnable_set)(rtk_enable_t); + rtk_api_ret_t (*l2_flushLinkDownPortAddrEnable_get)(rtk_enable_t *); + rtk_api_ret_t (*l2_agingEnable_set)(rtk_port_t, rtk_enable_t); + rtk_api_ret_t (*l2_agingEnable_get)(rtk_port_t, rtk_enable_t *); + rtk_api_ret_t (*l2_limitLearningCnt_set)(rtk_port_t, rtk_mac_cnt_t); + rtk_api_ret_t (*l2_limitLearningCnt_get)(rtk_port_t, rtk_mac_cnt_t *); + rtk_api_ret_t (*l2_limitSystemLearningCnt_set)(rtk_mac_cnt_t); + rtk_api_ret_t (*l2_limitSystemLearningCnt_get)(rtk_mac_cnt_t *); + rtk_api_ret_t (*l2_limitLearningCntAction_set)(rtk_port_t, rtk_l2_limitLearnCntAction_t); + rtk_api_ret_t (*l2_limitLearningCntAction_get)(rtk_port_t, rtk_l2_limitLearnCntAction_t *); + rtk_api_ret_t (*l2_limitSystemLearningCntAction_set)(rtk_l2_limitLearnCntAction_t); + rtk_api_ret_t (*l2_limitSystemLearningCntAction_get)(rtk_l2_limitLearnCntAction_t *); + rtk_api_ret_t (*l2_limitSystemLearningCntPortMask_set)(rtk_portmask_t *); + rtk_api_ret_t (*l2_limitSystemLearningCntPortMask_get)(rtk_portmask_t *); + rtk_api_ret_t (*l2_learningCnt_get)(rtk_port_t port, rtk_mac_cnt_t *); + rtk_api_ret_t (*l2_floodPortMask_set)(rtk_l2_flood_type_t, rtk_portmask_t *); + rtk_api_ret_t (*l2_floodPortMask_get)(rtk_l2_flood_type_t, rtk_portmask_t *); + rtk_api_ret_t (*l2_localPktPermit_set)(rtk_port_t, rtk_enable_t); + rtk_api_ret_t (*l2_localPktPermit_get)(rtk_port_t, rtk_enable_t *); + rtk_api_ret_t (*l2_aging_set)(rtk_l2_age_time_t); + rtk_api_ret_t (*l2_aging_get)(rtk_l2_age_time_t *); + rtk_api_ret_t (*l2_ipMcastAddrLookup_set)(rtk_l2_ipmc_lookup_type_t); + rtk_api_ret_t (*l2_ipMcastAddrLookup_get)(rtk_l2_ipmc_lookup_type_t *); + rtk_api_ret_t (*l2_ipMcastForwardRouterPort_set)(rtk_enable_t); + rtk_api_ret_t (*l2_ipMcastForwardRouterPort_get)(rtk_enable_t *); + rtk_api_ret_t (*l2_ipMcastGroupEntry_add)(ipaddr_t, rtk_portmask_t *); + rtk_api_ret_t (*l2_ipMcastGroupEntry_del)(ipaddr_t); + rtk_api_ret_t (*l2_ipMcastGroupEntry_get)(ipaddr_t, rtk_portmask_t *); + rtk_api_ret_t (*l2_entry_get)(rtk_l2_addr_table_t *); + rtk_api_ret_t (*l2_lookupHitIsolationAction_set)(rtk_l2_lookupHitIsolationAction_t); + rtk_api_ret_t (*l2_lookupHitIsolationAction_get)(rtk_l2_lookupHitIsolationAction_t *); + + rtk_api_ret_t (*l2_unknownUnicastPktAction_set)(rtk_port_t, rtk_uint32); + rtk_api_ret_t (*l2_unknownUnicastPktAction_get)(rtk_port_t, rtk_uint32 *); + rtk_api_ret_t (*l2_unknownMulticastPktAction_set)(rtk_port_t, rtk_uint32); + rtk_api_ret_t (*l2_unknownMulticastPktAction_get)(rtk_port_t, rtk_uint32 *); + rtk_api_ret_t (*l2_unknownV4McPktAction_set)(rtk_port_t, rtk_uint32); + rtk_api_ret_t (*l2_unknownV4McPktAction_get)(rtk_port_t, rtk_uint32 *); + rtk_api_ret_t (*l2_unknownV6McPktAction_set)(rtk_port_t, rtk_uint32); + rtk_api_ret_t (*l2_unknownV6McPktAction_get)(rtk_port_t, rtk_uint32 *); + + + rtk_api_ret_t (*l2_unmatchMacMoving_set)(rtk_port_t, rtk_enable_t); + rtk_api_ret_t (*l2_unmatchMacMoving_get)(rtk_port_t, rtk_enable_t *); + rtk_api_ret_t (*l2_unknownMcastPktAction_set)(rtk_port_t, rtk_uint32, rtk_uint32); + rtk_api_ret_t (*l2_unknownMcastPktAction_get)(rtk_port_t, rtk_uint32, rtk_uint32 *); + + rtk_api_ret_t (*l2_portUnmatchMacPktAction_set)(rtk_port_t, rtk_uint32); + rtk_api_ret_t (*l2_portUnmatchMacPktAction_get)(rtk_port_t, rtk_uint32 *); + + /*gpio*/ + rtk_api_ret_t (*gpio_muxSel_set)(rtk_uint32); + rtk_api_ret_t (*gpio_muxSel_get)(rtk_uint32, rtk_enable_t *); + rtk_api_ret_t (*gpio_groupVal_write)(rtk_gpio_groupReg_t, rtk_uint32); + rtk_api_ret_t (*gpio_groupVal_read)(rtk_gpio_groupReg_t, rtk_uint32 *); + rtk_api_ret_t (*gpio_pinVal_write)(rtk_uint32, rtk_gpio_level_t); + rtk_api_ret_t (*gpio_pinVal_read)(rtk_uint32, rtk_gpio_level_t *pVal); + rtk_api_ret_t (*gpio_pinDir_set)(rtk_uint32, rtk_gpio_direction_t ); + rtk_api_ret_t (*gpio_pinDir_get)(rtk_uint32, rtk_gpio_direction_t *); + rtk_api_ret_t (*gpio_groupDir_get)(rtk_gpio_groupReg_t , rtk_uint32 *); + + /*I2C*/ + + rtk_api_ret_t (*i2c_init)(rtk_i2c_sclClockRate_t, rtk_uint32); + rtk_api_ret_t (*i2c_readMode_set)(rtk_i2c_readMode_t); + rtk_api_ret_t (*i2c_readMode_get)(rtk_i2c_readMode_t *); + rtk_api_ret_t (*i2c_gpioPinGroup_set)(rtk_uint32, rtk_uint32); + rtk_api_ret_t (*i2c_gpioPinGroup_get)(rtk_uint32 *, rtk_uint32 *); + rtk_api_ret_t (*i2c_data_read)(rtk_uint32, rtk_uint32, rtk_uint32, rtk_uint32 *); + rtk_api_ret_t (*i2c_data_write)(rtk_uint32, rtk_uint32, rtk_uint32, rtk_uint32 *); + + /*Rate : ingress BW & egress queue BW*/ + rtk_api_ret_t (*rate_igrBwCtrlPortEn_set)(rtk_port_t, rtk_enable_t); + rtk_api_ret_t (*rate_igrBwCtrlPortEn_get)(rtk_port_t, rtk_enable_t *); + rtk_api_ret_t (*rate_igrBwCtrlRate_set)(rtk_port_t, rtk_rate_t, rtk_enable_t); + rtk_api_ret_t (*rate_igrBwCtrlRate_get)(rtk_port_t, rtk_rate_t *, rtk_enable_t *); + rtk_api_ret_t (*rate_igrBwCtrlIfg_set)(rtk_enable_t); + rtk_api_ret_t (*rate_igrBwCtrlIfg_get)(rtk_enable_t *); + rtk_api_ret_t (*rate_igrBwCtrlCongestSts_get)(rtk_port_t, rtk_rate_igrBwCongestSts_t *); + rtk_api_ret_t (*rate_egrBandwidthCtrlRate_set)(rtk_port_t, rtk_rate_t, rtk_enable_t); + rtk_api_ret_t (*rate_egrBandwidthCtrlRate_get)(rtk_port_t, rtk_rate_t *, rtk_enable_t *); + rtk_api_ret_t (*rate_egrQueueBwCtrlEnable_set)(rtk_port_t, rtk_qid_t, rtk_enable_t); + rtk_api_ret_t (*rate_egrQueueBwCtrlEnable_get)(rtk_port_t, rtk_qid_t, rtk_enable_t *); + rtk_api_ret_t (*rate_egrQueueBwCtrlRate_set)(rtk_port_t, rtk_qid_t, rtk_rate_t); + rtk_api_ret_t (*rate_egrQueueBwCtrlRate_get)(rtk_port_t, rtk_qid_t, rtk_rate_t *); + + /*EEE*/ + rtk_api_ret_t (*eee_init)(void); + rtk_api_ret_t (*eee_macForceSpeedEn_set)(rtk_port_t, rtk_eee_speedInMacForceMode_t, rtk_enable_t); + rtk_api_ret_t (*eee_macForceSpeedEn_get)(rtk_port_t, rtk_eee_speedInMacForceMode_t, rtk_enable_t *); + rtk_api_ret_t (*eee_macForceAllSpeedEn_get)(rtk_port_t, rtk_uint32 *); + rtk_api_ret_t (*eee_portTxRxEn_set)(rtk_port_t, rtk_enable_t, rtk_enable_t); + rtk_api_ret_t (*eee_portTxRxEn_get)(rtk_port_t, rtk_enable_t *, rtk_enable_t *); + + /*mib*/ + rtk_api_ret_t (*stat_global_reset)(void); + rtk_api_ret_t (*stat_port_reset)(rtk_port_t); + rtk_api_ret_t (*stat_port_get)(rtk_port_t, rtk_stat_port_type_t, rtk_stat_counter_t *); + rtk_api_ret_t (*stat_lengthMode_set)(rtk_stat_lengthMode_t, rtk_stat_lengthMode_t); + rtk_api_ret_t (*stat_lengthMode_get)(rtk_stat_lengthMode_t *, rtk_stat_lengthMode_t *); + + /*port*/ + rtk_api_ret_t (*port_macForceLink_set)(rtk_port_t, rtk_port_ability_t *); + rtk_api_ret_t (*port_macForceLink_get)(rtk_port_t, rtk_port_ability_t *); + rtk_api_ret_t (*port_macStatus_get)(rtk_port_t, rtk_port_status_t *); + rtk_api_ret_t (*port_macLocalLoopbackEnable_set)(rtk_port_t, rtk_enable_t); + rtk_api_ret_t (*port_macLocalLoopbackEnable_get)(rtk_port_t, rtk_enable_t *); + rtk_api_ret_t (*port_backpressureEnable_set)(rtk_port_t, rtk_enable_t); + rtk_api_ret_t (*port_backpressureEnable_get)(rtk_port_t, rtk_enable_t *); + rtk_api_ret_t (*port_rtct_init)(void); + rtk_api_ret_t (*port_rtct_start)(rtk_uint32); + rtk_api_ret_t (*port_rtctResult_get)(rtk_port_t, rtk_rtct_result_t *); + rtk_api_ret_t (*port_sdsMode_set)(rtk_uint32, rtk_sds_mode_t); + rtk_api_ret_t (*port_sdsMode_get)(rtk_uint32, rtk_sds_mode_t *); + + +#if 0 + + rtk_api_ret_t (*trap_lldpEnable_set)(rtk_enable_t); + rtk_api_ret_t (*trap_lldpEnable_get)(rtk_enable_t *); + rtk_api_ret_t (*trap_reasonTrapToCpuPriority_set)(rtk_trap_reason_type_t, rtk_pri_t); + rtk_api_ret_t (*trap_reasonTrapToCpuPriority_get)(rtk_trap_reason_type_t, rtk_pri_t *); + rtk_api_ret_t (*trap_rmaAction_set)(rtk_trap_type_t, rtk_trap_rma_action_t); + rtk_api_ret_t (*trap_rmaAction_get)(rtk_trap_type_t, rtk_trap_rma_action_t *); + rtk_api_ret_t (*trap_rmaKeepFormat_set)(rtk_trap_type_t, rtk_enable_t); + rtk_api_ret_t (*trap_rmaKeepFormat_get)(rtk_trap_type_t, rtk_enable_t *); +#endif +#if 0 + /* interrupt */ + rtk_api_ret_t (*int_polarity_set)(rtk_int_polarity_t); + rtk_api_ret_t (*int_polarity_get)(rtk_int_polarity_t *); + rtk_api_ret_t (*int_control_set)(rtk_int_type_t, rtk_enable_t); + rtk_api_ret_t (*int_control_get)(rtk_int_type_t, rtk_enable_t *); + rtk_api_ret_t (*int_status_set)(rtk_int_status_t *); + rtk_api_ret_t (*int_status_get)(rtk_int_status_t *); + rtk_api_ret_t (*int_advanceInfo_get)(rtk_int_advType_t, rtk_int_info_t *); + + /* port */ + rtk_api_ret_t (*port_phyAutoNegoAbility_set)(rtk_port_t, rtk_port_phy_ability_t *); + rtk_api_ret_t (*port_phyAutoNegoAbility_get)(rtk_port_t, rtk_port_phy_ability_t *); + rtk_api_ret_t (*port_phyForceModeAbility_set)(rtk_port_t, rtk_port_phy_ability_t *); + rtk_api_ret_t (*port_phyForceModeAbility_get)(rtk_port_t, rtk_port_phy_ability_t *); + rtk_api_ret_t (*port_phyStatus_get)(rtk_port_t, rtk_port_linkStatus_t *, rtk_port_speed_t *, rtk_port_duplex_t *); + rtk_api_ret_t (*port_macForceLink_set)(rtk_port_t, rtk_port_mac_ability_t *); + rtk_api_ret_t (*port_macForceLink_get)(rtk_port_t, rtk_port_mac_ability_t *); + rtk_api_ret_t (*port_macForceLinkExt_set)(rtk_port_t, rtk_mode_ext_t, rtk_port_mac_ability_t *); + rtk_api_ret_t (*port_macForceLinkExt_get)(rtk_port_t, rtk_mode_ext_t *, rtk_port_mac_ability_t *); + + + rtk_api_ret_t (*port_phyReg_set)(rtk_port_t, rtk_port_phy_reg_t, rtk_port_phy_data_t); + rtk_api_ret_t (*port_phyReg_get)(rtk_port_t, rtk_port_phy_reg_t, rtk_port_phy_data_t *); + + rtk_api_ret_t (*port_adminEnable_set)(rtk_port_t, rtk_enable_t); + rtk_api_ret_t (*port_adminEnable_get)(rtk_port_t, rtk_enable_t *); + #endif + +} dal_mapper_t; + + +#endif /* __DAL_MAPPER_H __ */ + diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/dal_mgmt.c b/sources/uboot-be550/drivers/net/rtl8372/dal/dal_mgmt.c new file mode 100755 index 00000000..c0601f24 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/dal_mgmt.c @@ -0,0 +1,71 @@ +/* + * Copyright (C) 2009 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + */ + +/* + * Include Files + */ +#if (!defined(CONFIG_DAL_RTL8373) && !defined(CONFIG_DAL_RTL8370UG)) +#define CONFIG_DAL_ALL +#endif + +#include +#include +#if defined(CONFIG_DAL_RTL8373) || defined(CONFIG_DAL_ALL) +#include +#endif +//#if defined(CONFIG_DAL_RTL8370UG) || defined(CONFIG_DAL_ALL) +//#include +//#endif + +dal_mgmt_info_t Mgmt_node; +dal_mgmt_info_t *pMgmt_node = &Mgmt_node; + +static dal_mapper_info_t dal_mapper_database[] = +{ + {CHIP_RTL8373, NULL}, + {CHIP_RTL8372, NULL}, +}; + +rtk_int32 dal_mgmt_attachDevice(switch_chip_t switchChip) +{ + rtk_uint32 mapper_size=sizeof(dal_mapper_database)/sizeof(dal_mapper_info_t); + rtk_uint32 mapper_index; + + /*mapper init*/ + for (mapper_index = 0; mapper_index < mapper_size; mapper_index++) + { + if (switchChip == dal_mapper_database[mapper_index].switchChip) + { +#if defined(CONFIG_DAL_RTL8373) || defined(CONFIG_DAL_ALL) + if (switchChip == CHIP_RTL8373) + { + dal_mapper_database[mapper_index].pMapper = dal_rtl8373_mapper_get(); + pMgmt_node->pMapper = dal_mapper_database[mapper_index].pMapper; + return RT_ERR_OK; + } +#endif +#if 0 +#if defined(CONFIG_DAL_RTL8370UG) || defined(CONFIG_DAL_ALL) + if (switchChip == CHIP_RTL8370UG) + { + dal_mapper_database[mapper_index].pMapper = dal_rtl8370ug_mapper_get(); + pMgmt_node->pMapper = dal_mapper_database[mapper_index].pMapper; + return RT_ERR_OK; + } +#endif +#endif + } + } + + return RT_ERR_CHIP_NOT_SUPPORTED; +} diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/dal_mgmt.h b/sources/uboot-be550/drivers/net/rtl8372/dal/dal_mgmt.h new file mode 100755 index 00000000..360ae00b --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/dal_mgmt.h @@ -0,0 +1,81 @@ + +/* + * Copyright (C) 2011 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : Use to Management each device + * + * Feature : The file have include the following module and sub-modules + * 1) Initialize system + * 2) Initialize device + * 3) Mangement Devices + * + */ +#ifndef __DAL_MGMT_H__ +#define __DAL_MGMT_H__ + +/* + * Include Files + */ +#include +#include +#include + +/* + * Symbol Definition + */ +typedef struct dal_mgmt_info_s +{ + dal_mapper_t *pMapper; +} dal_mgmt_info_t; + +typedef struct dal_mapper_info_s +{ + switch_chip_t switchChip; + dal_mapper_t *pMapper; +} dal_mapper_info_t; + +/* + * Data Declaration + */ +extern dal_mgmt_info_t *pMgmt_node; + +/* + * Macro Definition + */ +#define RT_MGMT pMgmt_node +#define RT_MAPPER RT_MGMT->pMapper + +/* + * Function Declaration + */ + +/* Module Name : */ + +/* Function Name: + * dal_mgmt_attachDevice + * Description: + * Attach device(semaphore, database clear) + * Input: + * switchChip - switch type + * Output: + * None + * Return: + * RT_ERR_FAILED - initialize fail + * RT_ERR_OK - initialize success + * Note: + * RTK must call this function before do other kind of action. + */ +extern rtk_int32 +dal_mgmt_attachDevice(switch_chip_t switchChip); + +#endif /* __DAL_MGMT_H__ */ + + diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/Makefile b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/Makefile new file mode 100644 index 00000000..e96812be --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/Makefile @@ -0,0 +1,23 @@ +LOC_DIR=src/hsl/phy/rtl8372/dal/rtl8373 +LIB=HSL + +include $(PRJ_PATH)/make/config.mk + +SRC_LIST= + +ifeq (TRUE, $(IN_RTL8372_PHY)) +SRC_LIST += dal_rtl8373_acl.c dal_rtl8373_fc.c dal_rtl8373_isolation.c dal_rtl8373_mirror.c dal_rtl8373_rate.c dal_rtl8373_svlan.c rtl8373_regField_list.c \ + dal_rtl8373_cpuTag.c dal_rtl8373_gpio.c dal_rtl8373_led.c dal_rtl8373_nic.c dal_rtl8373_rma.c dal_rtl8373_switch.c rtl8373_reg_list.c \ + dal_rtl8373_dos.c dal_rtl8373_hsb.c dal_rtl8373_lut.c dal_rtl8373_parser.c dal_rtl8373_rtkpp.c dal_rtl8373_trunk.c rtl8373_smi.c \ + dal_rtl8373_dot1x.c dal_rtl8373_i2c.c dal_rtl8373_macsec.c dal_rtl8373_port.c dal_rtl8373_sharemeter.c dal_rtl8373_vlan.c rtl8373_tableField_list.c \ + dal_rtl8373_drv.c dal_rtl8373_igmp.c dal_rtl8373_mapper.c dal_rtl8373_ptp.c dal_rtl8373_storm.c dal_rtl8373_wol.c rtl8373_table_list.c \ + dal_rtl8373_eee.c dal_rtl8373_interrupt.c dal_rtl8373_mib.c dal_rtl8373_qos.c dal_rtl8373_stp.c rtl8373_asicdrv.c + +EXTRA_CFLAGS += -DMDC_MDIO_OPERATION +endif + +include $(PRJ_PATH)/make/components.mk +include $(PRJ_PATH)/make/defs.mk +include $(PRJ_PATH)/make/target.mk + +all: dep obj diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_acl.c b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_acl.c new file mode 100755 index 00000000..f338b95c --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_acl.c @@ -0,0 +1,2592 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for rtl8373 + * Feature : Here is a list of all functions and variables in ACL module. + * + */ + +#include +#include +#include +#include +#include + +#include + +#if defined(CONFIG_RTL8373_ASICDRV_TEST) +rtl8373_aclRule_smi_t Rtl8370sVirtualAclRuleTable[RTL8373_ACLRULENO]; +rtk_uint16 Rtl8370sVirtualAclActTable[RTL8373_ACLRULENO][RTL8373_ACL_ACT_ENTRY_LEN]; +#endif + + +CONST_T rtk_uint8 rtl8373_filter_templateField[RTL8373_ACLTEMPLATENO][RTL8373_ACLRULEFIELDNO] = { + {RTL8373_ACL_DMAC0, RTL8373_ACL_DMAC1, RTL8373_ACL_DMAC2, RTL8373_ACL_SMAC0, RTL8373_ACL_SMAC1, RTL8373_ACL_SMAC2, RTL8373_ACL_ETHERTYPE, RTL8373_ACL_FIELD_SELECT15}, + {RTL8373_ACL_IP4SIP0, RTL8373_ACL_IP4SIP1, RTL8373_ACL_IP4DIP0, RTL8373_ACL_IP4DIP1, RTL8373_ACL_IPTOSPROTO, RTL8373_ACL_L4SPORT, RTL8373_ACL_L4DPORT, RTL8373_ACL_FIELD_SELECT00}, + {RTL8373_ACL_IP4DIP0, RTL8373_ACL_IP4DIP1, RTL8373_ACL_FIELD_SELECT03, RTL8373_ACL_FIELD_SELECT04, RTL8373_ACL_FIELD_SELECT05, RTL8373_ACL_FIELD_SELECT06, RTL8373_ACL_FIELD_SELECT07, RTL8373_ACL_FIELD_SELECT08}, + {RTL8373_ACL_IP4SIP0, RTL8373_ACL_IP4SIP1, RTL8373_ACL_FIELD_SELECT09, RTL8373_ACL_FIELD_SELECT10, RTL8373_ACL_FIELD_SELECT11, RTL8373_ACL_FIELD_SELECT12, RTL8373_ACL_FIELD_SELECT13, RTL8373_ACL_FIELD_SELECT14}, +// {RTL8373_ACL_FIELD_SELECT08, RTL8373_ACL_FIELD_SELECT07, RTL8373_ACL_FIELD_SELECT06, RTL8373_ACL_FIELD_SELECT05, RTL8373_ACL_FIELD_SELECT04, RTL8373_ACL_FIELD_SELECT03, RTL8373_ACL_IP4DIP1, RTL8373_ACL_IP4DIP0}, +// {RTL8373_ACL_FIELD_SELECT14, RTL8373_ACL_FIELD_SELECT13, RTL8373_ACL_FIELD_SELECT12, RTL8373_ACL_FIELD_SELECT11, RTL8373_ACL_FIELD_SELECT10, RTL8373_ACL_FIELD_SELECT09, RTL8373_ACL_IP4SIP1, RTL8373_ACL_IP4SIP0}, + {RTL8373_ACL_VIDRANGE, RTL8373_ACL_IPRANGE, RTL8373_ACL_PORTRANGE, RTL8373_ACL_CTAG, RTL8373_ACL_STAG, RTL8373_ACL_FIELD_SELECT01, RTL8373_ACL_FIELD_SELECT02, RTL8373_ACL_FIELD_VALID} +}; + +CONST_T rtk_uint8 rtl8373_filter_advanceCaretagField[RTL8373_ACLTEMPLATENO][2] = { + {TRUE, 7}, + {TRUE, 7}, + {FALSE, 0}, + {TRUE, 7}, + {TRUE, 7}, +}; + +/*MSB_4bit represent template IDX, LSB_4bit represent rule field idx*/ +CONST_T rtk_uint8 rtl8373_filter_fieldTemplateIndex[FILTER_FIELD_END][RTK_FILTER_FIELD_USED_MAX] = { + {0x00, 0x01,0x02}, + {0x03, 0x04,0x05}, + {0x06}, + {0x43}, + {0x44}, + + {0x10, 0x11}, + {0x12, 0x13}, + {0x10, 0x11}, + {0x12, 0x13}, + + {0x14}, + {0x14}, + + {0x30, 0x31,0x32, 0x33,0x34, 0x35, 0x36, 0x37}, + {0x20, 0x21,0x22, 0x23,0x24, 0x25, 0x26, 0x27}, + + {0x14}, + {0x14}, + + {0x14}, + {0x14}, + + {0x15}, + {0x16}, + {0x15}, + {0x15}, + {0x15}, + {0x16}, + + {0x40}, + {0x41}, + {0x42}, + {0x47}, + + {0x17}, + {0x45}, + {0x46}, + {0x22}, + {0x23}, + {0x24}, + {0x25}, + {0x26}, + {0x27}, + {0x32}, + {0x33}, + {0x34}, + {0x35}, + {0x36}, + {0x37}, + {0x07} + // {0xFF} /* Pattern Match */ +}; + +CONST_T rtk_uint8 rtl8373_filter_fieldSize[FILTER_FIELD_END] = { + 3, 3, 1, 1, 1, + 2, 2, 2,2, + 1, 1, 8, 8, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 +}; + +CONST_T rtk_uint16 rtl8373_field_selector[RTL8373_FIELDSEL_FORMAT_NUMBER][2] = +{ + {RTL8373_FIELDSEL_FORMAT_DEFAULT, 0}, /* Field Selector 0 */ + {RTL8373_FIELDSEL_FORMAT_DEFAULT, 0}, /* Field Selector 1 */ + {RTL8373_FIELDSEL_FORMAT_IPPAYLOAD, 12}, /* Field Selector 2 */ + {RTL8373_FIELDSEL_FORMAT_IPV6, 10}, /* Field Selector 3 */ + {RTL8373_FIELDSEL_FORMAT_IPV6, 8}, /* Field Selector 4 */ + {RTL8373_FIELDSEL_FORMAT_IPV4, 0}, /* Field Selector 5 */ + {RTL8373_FIELDSEL_FORMAT_IPV4, 8}, /* Field Selector 6 */ + {RTL8373_FIELDSEL_FORMAT_IPV6, 0}, /* Field Selector 7 */ + {RTL8373_FIELDSEL_FORMAT_IPV6, 6}, /* Field Selector 8 */ + {RTL8373_FIELDSEL_FORMAT_IPV6, 26}, /* Field Selector 9 */ + {RTL8373_FIELDSEL_FORMAT_IPV6, 24}, /* Field Selector 10 */ + {RTL8373_FIELDSEL_FORMAT_DEFAULT, 0}, /* Field Selector 11 */ + {RTL8373_FIELDSEL_FORMAT_IPV4, 6}, /* Field Selector 12 */ + {RTL8373_FIELDSEL_FORMAT_IPPAYLOAD, 0}, /* Field Selector 13 */ + {RTL8373_FIELDSEL_FORMAT_IPPAYLOAD, 2}, /* Field Selector 14 */ + {RTL8373_FIELDSEL_FORMAT_DEFAULT, 0} /* Field Selector 15 */ +}; + +/* + Exchange structure type define with MMI and SMI +*/ +static void _rtl8373_aclRuleStSmi2User( rtl8373_acl_rule_t *pAclUser, rtl8373_aclRule_smi_t *pAclSmi) +{ + rtk_uint8 *care_ptr, *data_ptr; + rtk_uint8 care_tmp, data_tmp; + rtk_uint32 i; + + pAclUser->data_bits.templateIdx = ((pAclSmi->data_bits.rule_info >> ACL_RULE_TEMPLATE_IDX_OFFSET)& 0x7); + pAclUser->data_bits.tagPppoe = ((pAclSmi->data_bits.rule_info >> ACL_RULE_TAG_PPPOE_OFFSET) & 0x7); + pAclUser->data_bits.l3fmt= ((pAclSmi->data_bits.rule_info >> ACL_RULE_L3FMT_OFFSET) & 0x3); + pAclUser->data_bits.l4fmt= ((pAclSmi->data_bits.rule_info >> ACL_RULE_L4FMT_OFFSET) & 0x7); + pAclUser->data_bits.activePmsk = ((pAclSmi->data_bits.rule_info >> ACL_RULE_ACTIVE_PMSK_OFFSET) & RTK_MAX_PORT_MASK); + + care_ptr = (rtk_uint8*)&pAclSmi->care_bits; + data_ptr = (rtk_uint8*)&pAclSmi->data_bits; + + for ( i = 0; i < sizeof(struct acl_rule_smi_st); i++) + { + care_tmp = *(care_ptr + i) ^ (*(data_ptr + i)); + data_tmp = *(data_ptr + i); + + *(care_ptr + i) = care_tmp; + *(data_ptr + i) = data_tmp; + } + + + for(i = 0; i < RTL8373_ACLRULEFIELDNO; i++) + { + if(i%2) + pAclUser->data_bits.field[i] = (rtk_uint16)( pAclSmi->data_bits.field[i/2] >>16 ); + else + pAclUser->data_bits.field[i] = (rtk_uint16)(pAclSmi->data_bits.field[i/2]); + } + + pAclUser->valid = pAclSmi->valid; + + pAclUser->care_bits.templateIdx = ((pAclSmi->care_bits.rule_info >> ACL_RULE_TEMPLATE_IDX_OFFSET) & 0x7); + pAclUser->care_bits.tagPppoe= ((pAclSmi->care_bits.rule_info >> ACL_RULE_TAG_PPPOE_OFFSET) & 0x7); + pAclUser->care_bits.l3fmt = ((pAclSmi->care_bits.rule_info >> ACL_RULE_L3FMT_OFFSET) & 0x3); + pAclUser->care_bits.l4fmt = ((pAclSmi->care_bits.rule_info >> ACL_RULE_L4FMT_OFFSET) & 0x7); + pAclUser->care_bits.activePmsk = ((pAclSmi->care_bits.rule_info >> ACL_RULE_ACTIVE_PMSK_OFFSET) & RTK_MAX_PORT_MASK); + + for(i = 0; i < RTL8373_ACLRULEFIELDNO; i++) + { + if(i%2) + pAclUser->care_bits.field[i] = (rtk_uint16)( pAclSmi->care_bits.field[i/2] >>16 ); + else + pAclUser->care_bits.field[i] = (rtk_uint16)(pAclSmi->care_bits.field[i/2]) ; + } + +} + +/* + Exchange structure type define with MMI and SMI +*/ +static void _rtl8373_aclRuleStUser2Smi(rtl8373_acl_rule_t *pAclUser, rtl8373_aclRule_smi_t *pAclSmi) +{ + rtk_uint8 *care_ptr, *data_ptr; + rtk_uint8 care_tmp, data_tmp; + rtk_uint32 i; + pAclSmi->data_bits.rule_info |= ((pAclUser->data_bits.templateIdx & 0x7) << ACL_RULE_TEMPLATE_IDX_OFFSET); + pAclSmi->data_bits.rule_info |= ((pAclUser->data_bits.tagPppoe & 0x7) << ACL_RULE_TAG_PPPOE_OFFSET); + pAclSmi->data_bits.rule_info |= ((pAclUser->data_bits.l3fmt & 0x3)<< ACL_RULE_L3FMT_OFFSET); + pAclSmi->data_bits.rule_info |= ((pAclUser->data_bits.l4fmt & 0x7)<< ACL_RULE_L4FMT_OFFSET); + pAclSmi->data_bits.rule_info |= ((pAclUser->data_bits.activePmsk & RTK_MAX_PORT_MASK) << ACL_RULE_ACTIVE_PMSK_OFFSET); + + for(i = 0;i < RTL8373_ACLRULEFIELDNO; i++) + { + if ( (i%2==1) ) + pAclSmi->data_bits.field[i/2] |= (rtk_uint32)( (pAclUser->data_bits.field[i]) << 16 ); + else + pAclSmi->data_bits.field[i/2] = (rtk_uint32)(pAclUser->data_bits.field[i] ); + } + + pAclSmi->valid = pAclUser->valid; + pAclSmi->care_bits.rule_info |= ((pAclUser->care_bits.templateIdx & 0x7) << ACL_RULE_TEMPLATE_IDX_OFFSET); + pAclSmi->care_bits.rule_info |= ((pAclUser->care_bits.tagPppoe & 0x7) << ACL_RULE_TAG_PPPOE_OFFSET) ; + pAclSmi->care_bits.rule_info |= ((pAclUser->care_bits.l3fmt & 0x3)<< ACL_RULE_L3FMT_OFFSET) ; + pAclSmi->care_bits.rule_info |= ((pAclUser->care_bits.l4fmt & 0x7)<< ACL_RULE_L4FMT_OFFSET) ; + pAclSmi->care_bits.rule_info |= ((pAclUser->care_bits.activePmsk & RTK_MAX_PORT_MASK) << ACL_RULE_ACTIVE_PMSK_OFFSET) ; + + for(i = 0; i < RTL8373_ACLRULEFIELDNO; i++) + { + if ( (i%2==1) ) + pAclSmi->care_bits.field[i/2] |= (rtk_uint32)( (pAclUser->care_bits.field[i])<<16 ); + else + pAclSmi->care_bits.field[i/2] = (rtk_uint32)(pAclUser->care_bits.field[i]); + } + + care_ptr = (rtk_uint8*)&pAclSmi->care_bits; + data_ptr = (rtk_uint8*)&pAclSmi->data_bits; + + for ( i = 0; i < sizeof(struct acl_rule_smi_st); i++) + { + care_tmp = ~(*(care_ptr + i)) | ~(*(data_ptr + i)); + data_tmp = ~(*(care_ptr + i)) | *(data_ptr + i); + *(care_ptr + i) = care_tmp; + *(data_ptr + i) = data_tmp; + } +} + +/* + Exchange structure type define with MMI and SMI +*/ +static void _rtl8373_aclActStSmi2User(rtl8373_acl_act_t *pAclUser, rtk_uint32 *pAclSmi) +{ + pAclUser->cact = (pAclSmi[0] & 0x3); + pAclUser->cactExt = ((pAclSmi[0] >> 2)& 0x3); + pAclUser->cvid = ((pAclSmi[0] >> 4)& 0xFFF); + pAclUser->tagFmt = ((pAclSmi[0] >> 16)& 0x3); + pAclUser->sact = ((pAclSmi[0] >> 18)& 0x3); + pAclUser->svid = ((pAclSmi[0]>>20) & 0xFFF); + + pAclUser->aclPri = (pAclSmi[1] & 0x7); + pAclUser->aclRmkAct = ((pAclSmi[1] >>3 ) & 1); + pAclUser->aclRmkVal = ((pAclSmi[1] >> 4) & 0x3F); + pAclUser->aclMeterLoggIdx =((pAclSmi[1] >>10) & 0x3F); + pAclUser->aclPolicingLogAct = ((pAclSmi[1] >> 16) & 0x1); + pAclUser->fwdAct = ((pAclSmi[1] >> 17) & 0x7); + pAclUser->fwdActExt = ((pAclSmi[1] >> 20) & 0x1); + pAclUser->fwdPmsk = ((pAclSmi[1] >> 21) & 0x3FF); + pAclUser->aclInt = ((pAclSmi[1] >> 31) & 0x1); + + pAclUser->gpioPin = (pAclSmi[2] & 0xF); + pAclUser->gpioEn = ((pAclSmi[2] >> 4) & 0x1); + pAclUser->bypassAct = ((pAclSmi[2] >> 5) & 0x7); +} + +/* + Exchange structure type define with MMI and SMI +*/ +static void _rtl8373_aclActStUser2Smi(rtl8373_acl_act_t *pAclUser, rtk_uint32 *pAclSmi) +{ + + if(pAclUser->gpioEn == DISABLED) + pAclUser->gpioPin = 0; + + pAclSmi[0] |= (pAclUser->cact & 0x3) ; + pAclSmi[0] |= (pAclUser->cactExt & 0x3) << 2; + pAclSmi[0] |= (pAclUser->cvid & 0xFFF)<<4; + pAclSmi[0] |= (pAclUser->tagFmt & 0x3) <<16; + pAclSmi[0] |= (pAclUser->sact & 0x3) << 18; + pAclSmi[0] |= (pAclUser->svid & 0xFFF)<<20; + + pAclSmi[1] |= (pAclUser->aclPri & 0x7); + pAclSmi[1] |= (pAclUser->aclRmkAct & 0x1)<<3; + pAclSmi[1] |= (pAclUser->aclRmkVal & 0x3F)<< 4; + pAclSmi[1] |= (pAclUser->aclMeterLoggIdx & 0x3F)<<10; + pAclSmi[1] |= (pAclUser->aclPolicingLogAct & 0x1)<<16; + pAclSmi[1] |= (pAclUser->fwdAct & 0x7) << 17; + pAclSmi[1] |= (pAclUser->fwdActExt & 0x1) <<20; + pAclSmi[1] |= (pAclUser->fwdPmsk & 0x3FF) << 21; + pAclSmi[1] |= (pAclUser->aclInt & 0x1) << 31; + + pAclSmi[2] |= (pAclUser->gpioPin & 0xF) ; + pAclSmi[2] |= (pAclUser->gpioEn & 0x1) << 4; + pAclSmi[2] |= (pAclUser->bypassAct & 0x7) << 5; + +} + +static rtk_api_ret_t _rtl8373_getAclTemplate(rtk_uint32 index, rtl8373_acl_template_t *pAclType) +{ + ret_t retVal; + rtk_uint32 i; + rtk_uint32 regData, regAddr; + + regAddr = RTL8373_ACL_TEMPLATE_CTRL_ADDR(index) ; + + for(i = 0; i < (RTL8373_ACLRULEFIELDNO/4); i++) + { + if(i<1) + retVal = rtl8373_getAsicReg(regAddr + 4, ®Data); + else + retVal = rtl8373_getAsicReg(regAddr, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + pAclType->field[i*4] = regData & 0xFF; + pAclType->field[i*4 + 1] = (regData >> 8) & 0xFF; + pAclType->field[i*4 + 2] = (regData >> 16) & 0xFF; + pAclType->field[i*4 + 3] = (regData >> 24) & 0xFF; + } + + return RT_ERR_OK; + +} + +static rtk_api_ret_t _rtl8373_setAclTemplate(rtk_uint32 index, rtl8373_acl_template_t* pAclType) +{ + ret_t retVal; + rtk_uint32 i; + rtk_uint32 regAddr, regData; + + if(index >= RTL8373_ACLTEMPLATENO) + return RT_ERR_OUT_OF_RANGE; + + regAddr = RTL8373_ACL_TEMPLATE_CTRL_ADDR(index) ; + + for(i = 0; i < (RTL8373_ACLRULEFIELDNO/4); i++) + { + regData = pAclType->field[i*4+3]; + regData = (regData << 8) | pAclType->field[i*4+2]; + regData = (regData << 8) | pAclType->field[i*4+1]; + regData = (regData << 8) | pAclType->field[i*4]; + if(i<1) + { + retVal = rtl8373_setAsicReg(regAddr + 4, regData); + } + else + { + retVal = rtl8373_setAsicReg(regAddr, regData); + } + + if(retVal != RT_ERR_OK) + return retVal; + } + return retVal; +} + + +static rtk_api_ret_t _rtk_igrAcl_writeDataField(rtl8373_acl_rule_t *aclRule, rtk_filter_field_t *fieldPtr) +{ + rtk_uint32 i = 0, tempIdx = 0, fieldIdx = 0, ipValue = 0, ipMask = 0; + + for(i = 0; i < fieldPtr->occupyFieldNum; i++) + { + tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4; + + aclRule[tempIdx].valid = TRUE; + } + + switch (fieldPtr->fieldType) + { + /* use DMAC structure as representative for mac structure */ + case FILTER_FIELD_DMAC: + case FILTER_FIELD_SMAC: + + for(i = 0; i < fieldPtr->occupyFieldNum; i++) + { + tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4; + fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F; + + aclRule[tempIdx].data_bits.field[fieldIdx] = fieldPtr->filter_pattern_union.mac.value.octet[5 - i*2] | (fieldPtr->filter_pattern_union.mac.value.octet[5 - (i*2 + 1)] << 8); + aclRule[tempIdx].care_bits.field[fieldIdx] = fieldPtr->filter_pattern_union.mac.mask.octet[5 - i*2] | (fieldPtr->filter_pattern_union.mac.mask.octet[5 - (i*2 + 1)] << 8); + } + break; + case FILTER_FIELD_ETHERTYPE: + for(i = 0; i < fieldPtr->occupyFieldNum; i++) + { + tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4; + fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F; + + aclRule[tempIdx].data_bits.field[fieldIdx] = (fieldPtr->filter_pattern_union.etherType.value & 0xFFFF); + aclRule[tempIdx].care_bits.field[fieldIdx] = (fieldPtr->filter_pattern_union.etherType.mask & 0xFFFF); + } + break; + case FILTER_FIELD_IPV4_SIP: + case FILTER_FIELD_IPV4_DIP: + case FILTER_FIELD_SENDER_PROTOCOL_ADDR: + case FILTER_FIELD_TARGET_PROTOCOL_ADDR: + + ipValue = fieldPtr->filter_pattern_union.sip.value; + ipMask = fieldPtr->filter_pattern_union.sip.mask; + + for(i = 0; i < fieldPtr->occupyFieldNum; i++) + { + tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4; + fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F; + + aclRule[tempIdx].data_bits.field[fieldIdx] = (0xFFFF & (ipValue >> (i*16))); + aclRule[tempIdx].care_bits.field[fieldIdx] = (0xFFFF & (ipMask >> (i*16))); + } + break; + + case FILTER_FIELD_IPV6_SIPV6: + case FILTER_FIELD_IPV6_DIPV6: + for(i = 0; i < fieldPtr->occupyFieldNum; i++) + { + ipValue = fieldPtr->filter_pattern_union.ipv6.value.addr[i/2]; + ipMask = fieldPtr->filter_pattern_union.ipv6.mask.addr[i/2]; + tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4; + fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F; + + aclRule[tempIdx].data_bits.field[fieldIdx] = (0xFFFF & (ipValue >> ((i%2)*16))); + aclRule[tempIdx].care_bits.field[fieldIdx] = (0xFFFF & (ipMask >> ((i%2)*16))); + } + break; + + case FILTER_FIELD_CTAG: + case FILTER_FIELD_STAG: + + for(i = 0; i < fieldPtr->occupyFieldNum; i++) + { + tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4; + fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F; + + aclRule[tempIdx].data_bits.field[fieldIdx] = (fieldPtr->filter_pattern_union.l2tag.pri.value << 13) | (fieldPtr->filter_pattern_union.l2tag.cfi.value << 12) | fieldPtr->filter_pattern_union.l2tag.vid.value; + aclRule[tempIdx].care_bits.field[fieldIdx] = (fieldPtr->filter_pattern_union.l2tag.pri.mask << 13) | (fieldPtr->filter_pattern_union.l2tag.cfi.mask << 12) | fieldPtr->filter_pattern_union.l2tag.vid.mask; + } + break; + + case FILTER_FIELD_IPV4_TOS: + for(i = 0; i < fieldPtr->occupyFieldNum; i++) + { + tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4; + fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F; + + aclRule[tempIdx].data_bits.field[fieldIdx] &= 0xFF; + aclRule[tempIdx].data_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.ipTos.value & 0xFF)<<8 ; + aclRule[tempIdx].care_bits.field[fieldIdx] &= 0xFF; + aclRule[tempIdx].care_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.ipTos.mask & 0xFF)<<8 ; + } + break; + case FILTER_FIELD_IPV4_PROTOCOL: + for(i = 0; i < fieldPtr->occupyFieldNum; i++) + { + tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4; + fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F; + + aclRule[tempIdx].data_bits.field[fieldIdx] &= 0xFF00; + aclRule[tempIdx].data_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.protocol.value & 0xFF); + aclRule[tempIdx].care_bits.field[fieldIdx] &= 0xFF00; + aclRule[tempIdx].care_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.protocol.mask & 0xFF) ; + } + break; + + + case FILTER_FIELD_ARP_RARP_CODE: + for(i = 0; i < fieldPtr->occupyFieldNum; i++) + { + tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4; + fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F; + + aclRule[tempIdx].data_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.arpRarpOpcode.value & 0xFFFF); + aclRule[tempIdx].care_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.arpRarpOpcode.mask & 0xFFFF) ; + } + break; + + case FILTER_FIELD_AFTER_ETHTYPE_BYTE01: + for(i = 0; i < fieldPtr->occupyFieldNum; i++) + { + tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4; + fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F; + + aclRule[tempIdx].data_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.afterEthertypeByte0_1.value & 0xFFFF); + aclRule[tempIdx].care_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.afterEthertypeByte0_1.mask & 0xFFFF) ; + } + break; + + case FILTER_FIELD_IPV6_TRAFFIC_CLASS: + for(i = 0; i < fieldPtr->occupyFieldNum; i++) + { + tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4; + fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F; + + aclRule[tempIdx].data_bits.field[fieldIdx] &= 0xFF; + aclRule[tempIdx].data_bits.field[fieldIdx] |= ((fieldPtr->filter_pattern_union.ipv6TrafficClass.value & 0xFF) << 8); + aclRule[tempIdx].care_bits.field[fieldIdx] &= 0xFF; + aclRule[tempIdx].care_bits.field[fieldIdx] |= ((fieldPtr->filter_pattern_union.ipv6TrafficClass.mask & 0xFF) << 8); + } + break; + + case FILTER_FIELD_IPV6_NEXT_HEADER: + for(i = 0; i < fieldPtr->occupyFieldNum; i++) + { + tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4; + fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F; + + aclRule[tempIdx].data_bits.field[fieldIdx] &= 0xFF00; + aclRule[tempIdx].data_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.ipv6NextHeader.value & 0xFF); + aclRule[tempIdx].care_bits.field[fieldIdx] &= 0xFF00; + aclRule[tempIdx].care_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.ipv6NextHeader.mask & 0xFF) ; + } + break; + case FILTER_FIELD_TCP_UDP_SPORT: + for(i = 0; i < fieldPtr->occupyFieldNum; i++) + { + tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4; + fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F; + + aclRule[tempIdx].data_bits.field[fieldIdx] = (fieldPtr->filter_pattern_union.tcpUdpSrcPort.value & 0xFFFF); + aclRule[tempIdx].care_bits.field[fieldIdx] = (fieldPtr->filter_pattern_union.tcpUdpSrcPort.mask & 0xFFFF); + } + break; + case FILTER_FIELD_TCP_UDP_DPORT: + for(i = 0; i < fieldPtr->occupyFieldNum; i++) + { + tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4; + fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F; + + aclRule[tempIdx].data_bits.field[fieldIdx] = (fieldPtr->filter_pattern_union.tcpUdpDstPort.value & 0xFFFF); + aclRule[tempIdx].care_bits.field[fieldIdx] = (fieldPtr->filter_pattern_union.tcpUdpDstPort.mask & 0xFFFF); + } + break; + case FILTER_FIELD_ICMP_IGMP_CODE: + for(i = 0; i < fieldPtr->occupyFieldNum; i++) + { + tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4; + fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F; + + aclRule[tempIdx].data_bits.field[fieldIdx] &= 0xFF00; + aclRule[tempIdx].data_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.icmpIgmpCode.value & 0xFF); + aclRule[tempIdx].care_bits.field[fieldIdx] &= 0xFF00; + aclRule[tempIdx].care_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.icmpIgmpCode.mask & 0xFF); + } + break; + case FILTER_FIELD_ICMP_IGMP_TYPE: + for(i = 0; i < fieldPtr->occupyFieldNum; i++) + { + tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4; + fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F; + + aclRule[tempIdx].data_bits.field[fieldIdx] &= 0x00FF; + aclRule[tempIdx].data_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.icmpIgmpType.value << 8); + aclRule[tempIdx].care_bits.field[fieldIdx] &= 0x00FF; + aclRule[tempIdx].care_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.icmpIgmpType.mask << 8); + } + break; + case FILTER_FIELD_L4HEADER_BYTE01: + for(i = 0; i < fieldPtr->occupyFieldNum; i++) + { + tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4; + fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F; + + aclRule[tempIdx].data_bits.field[fieldIdx] = ((fieldPtr->filter_pattern_union.l4headerByte0_1.value) & 0xFFFF); + aclRule[tempIdx].care_bits.field[fieldIdx] = ((fieldPtr->filter_pattern_union.l4headerByte0_1.mask) & 0xFFFF); + } + break; + case FILTER_FIELD_L4HEADER_BYTE23: + for(i = 0; i < fieldPtr->occupyFieldNum; i++) + { + tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4; + fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F; + + aclRule[tempIdx].data_bits.field[fieldIdx] = ((fieldPtr->filter_pattern_union.l4headerByte2_3.value) & 0xFFFF); + aclRule[tempIdx].care_bits.field[fieldIdx] = ((fieldPtr->filter_pattern_union.l4headerByte2_3.mask ) & 0xFFFF); + } + break; + + case FILTER_FIELD_PATTERN_MATCH: + case FILTER_FIELD_VID_RANGE: + case FILTER_FIELD_IP_RANGE: + case FILTER_FIELD_PORT_RANGE: + default: + tempIdx = (fieldPtr->fieldTemplateIdx[0] & 0xF0) >> 4; + fieldIdx = fieldPtr->fieldTemplateIdx[0] & 0x0F; + + aclRule[tempIdx].data_bits.field[fieldIdx] = fieldPtr->filter_pattern_union.inData.value; + aclRule[tempIdx].care_bits.field[fieldIdx] = fieldPtr->filter_pattern_union.inData.mask; + break; + } + return RT_ERR_OK; +} + +rtk_api_ret_t _rtl8373_getAclRule(rtk_uint32 index, rtl8373_acl_rule_t *pAclRule) +{ + rtl8373_aclRule_smi_t aclRuleSmi; + rtk_uint32 regAddr = 0, regData = 0; + rtk_uint32* tableAddr = NULL; + rtk_uint32 i = 0; + + if(index > RTL8373_ACLRULEMAX) + return RT_ERR_OUT_OF_RANGE; + + memset(&aclRuleSmi, 0x00, sizeof(rtl8373_aclRule_smi_t)); + + + /* Write ACS_ADR register for carebits*/ + regAddr = RTL8373_ITA_CTRL0_ADDR; + + /*prepare control Data*/ + regData = RTL8373_ACLRULETBADDR(RTL8373_CAREBITS, index) << RTL8373_ITA_CTRL0_TBL_ADDR_OFFSET; + regData |= TB_TARGET_ACLRULE << RTL8373_ITA_CTRL0_TLB_TYPE_OFFSET; + regData |= TB_OP_READ << RTL8373_ITA_CTRL0_TLB_ACT_OFFSET; + regData |= TB_EXECUTE<< RTL8373_ITA_CTRL0_TLB_EXECUTE_OFFSET; + + /*Trigger*/ + RTK_ERR_CHK(rtl8373_setAsicReg(regAddr, regData)); + /*wait access finished */ + do{ + RTK_ERR_CHK(rtl8373_getAsicRegBit(regAddr, RTL8373_ITA_CTRL0_TLB_EXECUTE_OFFSET , ®Data)); + }while(regData); + + /* Read Care Bits */ + tableAddr = (rtk_uint32*)&aclRuleSmi.care_bits; + for(i = 0; i < RTL8373_ACL_RULE_ENTRY_LEN; i++) + { + RTK_ERR_CHK(rtl8373_getAsicReg(RTL8373_ITA_READ_DATA0_ADDR(i), ®Data)); + + *tableAddr = regData; + tableAddr++; + } + + /* Write ACS_ADR register for data bits */ + regAddr = RTL8373_ITA_CTRL0_ADDR; + + /*prepare control Data*/ + regData = RTL8373_ACLRULETBADDR(RTL8373_DATABITS, index) << RTL8373_ITA_CTRL0_TBL_ADDR_OFFSET; + regData |= TB_TARGET_ACLRULE << RTL8373_ITA_CTRL0_TLB_TYPE_OFFSET; + regData |= TB_OP_READ << RTL8373_ITA_CTRL0_TLB_ACT_OFFSET; + regData |= TB_EXECUTE<< RTL8373_ITA_CTRL0_TLB_EXECUTE_OFFSET; + + /*Trigger*/ + RTK_ERR_CHK(rtl8373_setAsicReg(regAddr, regData)); + /*wait access finished */ + do{ + RTK_ERR_CHK(rtl8373_getAsicRegBit(regAddr, RTL8373_ITA_CTRL0_TLB_EXECUTE_OFFSET , ®Data)); + }while(regData); + + /* Read Data Bits */ + tableAddr = (rtk_uint32*)&aclRuleSmi.data_bits; + for(i = 0; i < RTL8373_ACL_RULE_ENTRY_LEN; i++) + { + RTK_ERR_CHK(rtl8373_getAsicReg( RTL8373_ITA_READ_DATA0_ADDR(i), ®Data)); + + *tableAddr = regData; + tableAddr++; + + } + + /* Read Valid Bit */ + + aclRuleSmi.valid = (regData >> RTL8373_ACLRULE_VALIDBIT_OFFSET) & 0x1; + + +#ifdef CONFIG_RTL8373_ASICDRV_TEST + memcpy(&aclRuleSmi,&Rtl8370sVirtualAclRuleTable[index], sizeof(rtl8373_aclRule_smi_t)); +#endif + + _rtl8373_aclRuleStSmi2User(pAclRule, &aclRuleSmi); + + return RT_ERR_OK; +} + +rtk_api_ret_t _rtl8373_setAclRule(rtk_uint32 index, rtl8373_acl_rule_t* pAclRule) +{ + rtl8373_aclRule_smi_t aclRuleSmi; + rtk_uint32* tableAddr; + rtk_uint32 regAddr; + rtk_uint32 regData; + rtk_uint32 i; + + if(index > RTL8373_ACLRULEMAX) + return RT_ERR_OUT_OF_RANGE; + + memset(&aclRuleSmi, 0x00, sizeof(rtl8373_aclRule_smi_t)); + + _rtl8373_aclRuleStUser2Smi(pAclRule, &aclRuleSmi); + + + /*----- Write Valid Bit = 0 -----*/ + /* write data */ + RTK_ERR_CHK(rtl8373_setAsicRegBit(RTL8373_ITA_WRITE_DATA0_ADDR(4), RTL8373_ACLRULE_VALIDBIT_OFFSET, INVALID)); + + /* Prepare Control register */ + regAddr = RTL8373_ITA_CTRL0_ADDR; + regData = RTL8373_ACLRULETBADDR(RTL8373_DATABITS, index) << RTL8373_ITA_CTRL0_TBL_ADDR_OFFSET; + regData |= TB_TARGET_ACLRULE << RTL8373_ITA_CTRL0_TLB_TYPE_OFFSET; + regData |= TB_OP_WRITE<< RTL8373_ITA_CTRL0_TLB_ACT_OFFSET; + regData |= TB_EXECUTE<< RTL8373_ITA_CTRL0_TLB_EXECUTE_OFFSET; + + /*Trigger*/ + RTK_ERR_CHK(rtl8373_setAsicReg(regAddr, regData)); + + /*wait access finished */ + do{ + RTK_ERR_CHK(rtl8373_getAsicReg(regAddr, ®Data)); + }while(regData & 0x1); + + /*----- Write care bit register -----*/ + /* Write Care Bits to ACS_DATA registers */ + tableAddr = (rtk_uint32*)&aclRuleSmi.care_bits; + for(i = 0; i < RTL8373_ACL_RULE_ENTRY_LEN; i++) + { + regData = *tableAddr; + + RTK_ERR_CHK(rtl8373_setAsicReg(RTL8373_ITA_WRITE_DATA0_ADDR(i), regData)); + tableAddr++; + } + + /* Prepare Control register */ + regAddr = RTL8373_ITA_CTRL0_ADDR; + regData = RTL8373_ACLRULETBADDR(RTL8373_CAREBITS, index) << RTL8373_ITA_CTRL0_TBL_ADDR_OFFSET; + regData |= TB_TARGET_ACLRULE << RTL8373_ITA_CTRL0_TLB_TYPE_OFFSET; + regData |= TB_OP_WRITE<< RTL8373_ITA_CTRL0_TLB_ACT_OFFSET; + regData |= TB_EXECUTE<< RTL8373_ITA_CTRL0_TLB_EXECUTE_OFFSET; + /*Trigger*/ + RTK_ERR_CHK(rtl8373_setAsicReg(regAddr,regData)); + + /*wait access finished */ + do{ + RTK_ERR_CHK(rtl8373_getAsicReg(regAddr , ®Data)); + }while(regData & 1); + + + /*----- Write ACL data bits -----*/ + /* Write Data Bits to ACS_DATA registers */ + tableAddr = (rtk_uint32*)&aclRuleSmi.data_bits; + + for(i = 0; i < RTL8373_ACL_RULE_ENTRY_LEN; i++) + { + regData = *tableAddr; + + RTK_ERR_CHK(rtl8373_setAsicReg(RTL8373_ITA_WRITE_DATA0_ADDR(i), regData)); + tableAddr++; + } + RTK_ERR_CHK(rtl8373_setAsicRegBit(RTL8373_ITA_WRITE_DATA0_ADDR(4), RTL8373_ACLRULE_VALIDBIT_OFFSET, aclRuleSmi.valid)); + + /* Prepare Control register */ + regAddr = RTL8373_ITA_CTRL0_ADDR; + regData = RTL8373_ACLRULETBADDR(RTL8373_DATABITS, index) << RTL8373_ITA_CTRL0_TBL_ADDR_OFFSET; + regData |= TB_TARGET_ACLRULE << RTL8373_ITA_CTRL0_TLB_TYPE_OFFSET; + regData |= TB_OP_WRITE<< RTL8373_ITA_CTRL0_TLB_ACT_OFFSET; + regData |= TB_EXECUTE<< RTL8373_ITA_CTRL0_TLB_EXECUTE_OFFSET; + /*Trigger*/ + RTK_ERR_CHK(rtl8373_setAsicReg(regAddr, regData)); + + /*wait access finished */ + do{ + RTK_ERR_CHK(rtl8373_getAsicRegBit(regAddr, RTL8373_ITA_CTRL0_TLB_EXECUTE_OFFSET , ®Data)); + }while(regData); + + +#ifdef CONFIG_RTL8373_ASICDRV_TEST + memcpy(&Rtl8370sVirtualAclRuleTable[index], &aclRuleSmi, sizeof(rtl8373_aclRule_smi_t)); +#endif + + return RT_ERR_OK; +} + +static rtk_api_ret_t _rtl8373_getAclAct(rtk_uint32 index, rtl8373_acl_act_t *pAclAct) +{ + rtk_uint32 aclActSmi[RTL8373_ACL_ACT_ENTRY_LEN]; + rtk_uint32 regAddr, regData; + rtk_uint32 *tableAddr; + rtk_uint32 i; + + if(index > RTL8373_ACLRULEMAX) + return RT_ERR_OUT_OF_RANGE; + + memset(aclActSmi, 0x00, sizeof(rtk_uint32) * RTL8373_ACL_ACT_ENTRY_LEN); + + /* Prepare Control register */ + regAddr = RTL8373_ITA_CTRL0_ADDR; + regData = index << RTL8373_ITA_CTRL0_TBL_ADDR_OFFSET; + regData |= TB_TARGET_ACLACT << RTL8373_ITA_CTRL0_TLB_TYPE_OFFSET; + regData |= TB_OP_READ<< RTL8373_ITA_CTRL0_TLB_ACT_OFFSET; + regData |= TB_EXECUTE << RTL8373_ITA_CTRL0_TLB_EXECUTE_OFFSET; + /*Trigger*/ + RTK_ERR_CHK(rtl8373_setAsicReg(regAddr, regData)); + + /*wait access finished */ + do{ + RTK_ERR_CHK(rtl8373_getAsicRegBit(regAddr, RTL8373_ITA_CTRL0_TLB_EXECUTE_OFFSET , ®Data)); + }while(regData); + + /* Read Data Bits */ + tableAddr = aclActSmi; + for(i = 0; i < RTL8373_ACL_ACT_ENTRY_LEN; i++) + { + RTK_ERR_CHK(rtl8373_getAsicReg(RTL8373_ITA_READ_DATA0_ADDR(i), ®Data)); + *tableAddr = regData; + tableAddr ++; + } + +#ifdef CONFIG_RTL8373_ASICDRV_TEST + memcpy(aclActSmi, &Rtl8370sVirtualAclActTable[index][0], sizeof(rtk_uint32) * RTL8373_ACL_ACT_ENTRY_LEN); +#endif + + _rtl8373_aclActStSmi2User(pAclAct, aclActSmi); + + return RT_ERR_OK; +} + +static rtk_api_ret_t _rtl8373_setAclAct(rtk_uint32 index, rtl8373_acl_act_t* pAclAct) +{ + rtk_uint32 aclActSmi[RTL8373_ACL_ACT_ENTRY_LEN]; + rtk_uint32 regAddr, regData; + rtk_uint32* tableAddr; + rtk_uint32 i; + + if(index > RTL8373_ACLRULEMAX) + return RT_ERR_OUT_OF_RANGE; + + memset(aclActSmi, 0x00, sizeof(rtk_uint32) * RTL8373_ACL_ACT_ENTRY_LEN); + _rtl8373_aclActStUser2Smi(pAclAct, aclActSmi); + + /* Write Data Bits to ACS_DATA registers */ + tableAddr = aclActSmi; + for(i = 0; i < RTL8373_ACL_ACT_ENTRY_LEN; i++) + { + regData = *tableAddr; + RTK_ERR_CHK(rtl8373_setAsicReg(RTL8373_ITA_WRITE_DATA0_ADDR(i) , regData)); + tableAddr++; + + } + + /* Prepare Control register */ + regAddr = RTL8373_ITA_CTRL0_ADDR; + regData = index << RTL8373_ITA_CTRL0_TBL_ADDR_OFFSET; + regData |= TB_TARGET_ACLACT << RTL8373_ITA_CTRL0_TLB_TYPE_OFFSET; + regData |= TB_OP_WRITE << RTL8373_ITA_CTRL0_TLB_ACT_OFFSET; + regData |= TB_EXECUTE << RTL8373_ITA_CTRL0_TLB_EXECUTE_OFFSET; + + /*Trigger*/ + RTK_ERR_CHK(rtl8373_setAsicReg(regAddr, regData)); + + /*wait access finished */ + do{ + RTK_ERR_CHK(rtl8373_getAsicRegBit(regAddr, RTL8373_ITA_CTRL0_TLB_EXECUTE_OFFSET , ®Data)); + }while(regData); + +#ifdef CONFIG_RTL8373_ASICDRV_TEST + memcpy(&Rtl8370sVirtualAclActTable[index][0], aclActSmi, sizeof(rtk_uint32) * RTL8373_ACL_ACT_ENTRY_LEN); +#endif + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_igrAcl_init + * Description: + * ACL initialization function + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Pointer pFilter_field or pFilterCfg point to NULL. + * Note: + * This function enable and intialize ACL function + */ +rtk_api_ret_t dal_rtl8373_igrAcl_init(void) +{ + rtl8373_acl_template_t aclTemp; + rtk_uint32 i, j; + rtk_api_ret_t ret; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if ((ret = dal_rtl8373_igrAcl_cfg_delAll()) != RT_ERR_OK) + return ret; + + /*init template*/ + for(i = 0; i < RTL8373_ACLTEMPLATENO; i++) + { + for(j = 0; j < RTL8373_ACLRULEFIELDNO;j++) + aclTemp.field[j] = rtl8373_filter_templateField[i][j]; + + if ((ret = _rtl8373_setAclTemplate(i, &aclTemp)) != RT_ERR_OK) + return ret; + } + + /*init hsb field selector*/ + /* + for(i = 0; i < RTL8373_FIELDSEL_FORMAT_NUMBER; i++) + { + regData = (((rtl8373_field_selector[i][0] << RTL8373_PARSER_FIELD_SELTOR_CTRL_FMT_OFFSET) & RTL8373_PARSER_FIELD_SELTOR_CTRL_FMT_MASK ) | + ((rtl8373_field_selector[i][1] << RTL8373_PARSER_FIELD_SELTOR_CTRL_OFFSET_OFFSET) & RTL8373_PARSER_FIELD_SELTOR_CTRL_OFFSET_MASK )); + + if ((ret = rtl8373_setAsicReg(RTL8373_PARSER_FIELD_SELTOR_CTRL_ADDR(i), regData)) != RT_ERR_OK) + return ret; + } +*/ + RTK_SCAN_ALL_PHY_PORTMASK(i) + { + + if ((ret = rtl8373_setAsicRegBit(RTL8373_ACL_PORT_EN_ADDR, i, TRUE)) != RT_ERR_OK) + return ret; + + if ((ret = rtl8373_setAsicRegBit(RTL8373_ACL_PORT_UNMATCH_PERMIT_ADDR, i, TRUE)) != RT_ERR_OK) + return ret; + } + +#ifdef CONFIG_RTL8373_ASICDRV_TEST + for(i=0;ifieldType >= FILTER_FIELD_END) + return RT_ERR_ENTRY_INDEX; + + + if(0 == pFilterField->occupyFieldNum) + { + pFilterField->occupyFieldNum = rtl8373_filter_fieldSize[pFilterField->fieldType]; + + for(i = 0; i < pFilterField->occupyFieldNum; i++) + { + pFilterField->fieldTemplateIdx[i] = rtl8373_filter_fieldTemplateIndex[pFilterField->fieldType][i]; + } + } + + if(NULL == pFilterCfg->fieldHead) + { + pFilterCfg->fieldHead = pFilterField; + } + else + { + if (pFilterCfg->fieldHead->next == NULL) + { + pFilterCfg->fieldHead->next = pFilterField; + } + else + { + tailPtr = pFilterCfg->fieldHead->next; + while( tailPtr->next != NULL) + { + tailPtr = tailPtr->next; + } + tailPtr->next = pFilterField; + } + } + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_igrAcl_cfg_add + * Description: + * Add an ACL configuration to ASIC + * Input: + * filterIdx - Start index of ACL configuration. + * pFilterCfg - The ACL configuration that this function will add comparison rule + * pAction - Action(s) of ACL configuration. + * Output: + * ruleNum - number of rules written in acl table + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Pointer pFilter_field or pFilterCfg point to NULL. + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_ENTRY_INDEX - Invalid filterIdx . + * RT_ERR_NULL_POINTER - Pointer pAction or pFilterCfg point to NULL. + * RT_ERR_FILTER_INACL_ACT_NOT_SUPPORT - Action is not supported in this chip. + * RT_ERR_FILTER_INACL_RULE_NOT_SUPPORT - Rule is not supported. + * Note: + * This function store pFilterCfg, pAction into ASIC. The starting + * index(es) is filterIdx. + */ +rtk_api_ret_t dal_rtl8373_igrAcl_cfg_add(rtk_filter_id_t filterIdx, rtk_filter_cfg_t* pFilterCfg, rtk_filter_action_t* pAction, rtk_filter_number_t *ruleNum) +{ + rtk_api_ret_t retVal = 0; + rtk_uint32 careTagData = 0, careTagMask = 0; + rtk_uint32 i = 0, actType = 0, ruleId = 0; + rtk_uint32 aclActCtrl = 0; + rtk_filter_field_t* fieldPtr; + rtl8373_acl_rule_t aclRule[RTL8373_ACLTEMPLATENO]; + rtl8373_acl_rule_t tempRule; + rtl8373_acl_act_t aclAct ; + rtk_uint32 noRulesAdd = 0; + rtk_uint32 portmask = 0; + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(filterIdx > RTL8373_ACLRULEMAX ) + return RT_ERR_ENTRY_INDEX; + + if((NULL == pFilterCfg) || (NULL == pAction) || (NULL == ruleNum)) + return RT_ERR_NULL_POINTER; + + fieldPtr = pFilterCfg->fieldHead; + + /* init RULE */ + for(i = 0; i < RTL8373_ACLTEMPLATENO; i++) + { + memset(&aclRule[i], 0, sizeof(rtl8373_acl_rule_t)); + + aclRule[i].data_bits.templateIdx = i; + aclRule[i].care_bits.templateIdx = RTL8373_ACLTEMPLATE_MASK; + } + + while(NULL != fieldPtr) + { + _rtk_igrAcl_writeDataField(aclRule, fieldPtr); + + fieldPtr = fieldPtr->next; + } + + /*Check rule number*/ + noRulesAdd = 0; + for(i = 0; i < RTL8373_ACLTEMPLATENO; i++) + { + if(1 == aclRule[i].valid) + { + noRulesAdd ++; + } + } + + *ruleNum = noRulesAdd; + + if((filterIdx + noRulesAdd - 1) > RTL8373_ACLRULEMAX) + { + return RT_ERR_ENTRY_INDEX; + } + + /*set care tag mask in TAG Indicator*/ + careTagData = 0; + careTagMask = 0; + + for(i = 0; i <= CARE_TAG_IPV6;i++) + { + if(0 == pFilterCfg->careTag.tagType[i].mask ) + { + careTagMask &= ~(1 << i); + } + else + { + careTagMask |= (1 << i); + if(0 == pFilterCfg->careTag.tagType[i].value ) + careTagData &= ~(1 << i); + else + careTagData |= (1 << i); + } + } + + for(i = 0; i < RTL8373_ACLTEMPLATENO; i++) + { + aclRule[i].data_bits.tagPppoe= (careTagData) & ACL_RULE_TAG_MASK; + aclRule[i].care_bits.tagPppoe = (careTagMask) & ACL_RULE_TAG_MASK; + } + + RTK_CHK_PORTMASK_VALID(&pFilterCfg->activeport.value); + RTK_CHK_PORTMASK_VALID(&pFilterCfg->activeport.mask); + + for(i = 0; i < RTL8373_ACLTEMPLATENO; i++) + { + if(TRUE == aclRule[i].valid) + { + if(rtk_switch_portmask_L2P_get(&pFilterCfg->activeport.value, &portmask) != RT_ERR_OK) + return RT_ERR_PORT_MASK; + + aclRule[i].data_bits.activePmsk = portmask; + + if(rtk_switch_portmask_L2P_get(&pFilterCfg->activeport.mask, &portmask) != RT_ERR_OK) + return RT_ERR_PORT_MASK; + + aclRule[i].care_bits.activePmsk = portmask; + + aclRule[i].data_bits.l3fmt = (pFilterCfg->l3fmt.value & ACL_RULE_L3FMT_MASK); + aclRule[i].care_bits.l3fmt = (pFilterCfg->l3fmt.mask & ACL_RULE_L3FMT_MASK); + aclRule[i].data_bits.l4fmt = (pFilterCfg->l4fmt.value & ACL_RULE_L4FMT_MASK); + aclRule[i].care_bits.l4fmt = (pFilterCfg->l4fmt.mask & ACL_RULE_L4FMT_MASK); + } + } + + if(pFilterCfg->invert >= FILTER_INVERT_END ) + return RT_ERR_INPUT; + + + /*Last action gets high priority if actions are the same*/ + memset(&aclAct, 0, sizeof(rtl8373_acl_act_t)); + aclActCtrl = 0; + for(actType = 0; actType < FILTER_ENACT_END; actType ++) + { + if(pAction->actEnable[actType]) + { + switch (actType) + { + case FILTER_ENACT_CVLAN_INGRESS: + if(pAction->filterCvlanVid > RTL8373_VIDMAX) + return RT_ERR_INPUT; + + aclAct.cact = FILTER_ENACT_CVLAN_TYPE(actType); + aclAct.cvid = pAction->filterCvlanVid; + + if(aclActCtrl &(FILTER_ENACT_CVLAN_MASK)) + { + if(aclAct.cactExt == FILTER_ENACT_CACTEXT_TAGONLY) + aclAct.cactExt = FILTER_ENACT_CACTEXT_BOTHVLANTAG; + } + else + { + aclAct.cactExt = FILTER_ENACT_CACTEXT_VLANONLY; + } + + aclActCtrl |= FILTER_ENACT_CVLAN_MASK; + break; + case FILTER_ENACT_CVLAN_EGRESS: + if(pAction->filterCvlanVid > RTL8373_VIDMAX) + return RT_ERR_INPUT; + + aclAct.cact = FILTER_ENACT_CVLAN_TYPE(actType); + aclAct.cvid = pAction->filterCvlanVid; + + if(aclActCtrl &(FILTER_ENACT_CVLAN_MASK)) + { + if(aclAct.cactExt == FILTER_ENACT_CACTEXT_TAGONLY) + aclAct.cactExt = FILTER_ENACT_CACTEXT_BOTHVLANTAG; + } + else + { + aclAct.cactExt = FILTER_ENACT_CACTEXT_VLANONLY; + } + + aclActCtrl |= FILTER_ENACT_CVLAN_MASK; + break; + case FILTER_ENACT_CVLAN_SVID: + + aclAct.cact = FILTER_ENACT_CVLAN_TYPE(actType); + + if(aclActCtrl &(FILTER_ENACT_CVLAN_MASK)) + { + if(aclAct.cactExt == FILTER_ENACT_CACTEXT_TAGONLY) + aclAct.cactExt = FILTER_ENACT_CACTEXT_BOTHVLANTAG; + } + else + { + aclAct.cactExt = FILTER_ENACT_CACTEXT_VLANONLY; + } + + aclActCtrl |= FILTER_ENACT_CVLAN_MASK; + break; + case FILTER_ENACT_POLICING_1: + if(pAction->filterPolicingIdx[1] > ( RTL8373_METERMAX ) ) + return RT_ERR_INPUT; + + aclAct.cact = FILTER_ENACT_CVLAN_TYPE(actType); + aclAct.cvid = pAction->filterPolicingIdx[1]; + + if(aclActCtrl &(FILTER_ENACT_CVLAN_MASK)) + { + if(aclAct.cactExt == FILTER_ENACT_CACTEXT_TAGONLY) + aclAct.cactExt = FILTER_ENACT_CACTEXT_BOTHVLANTAG; + } + else + { + aclAct.cactExt = FILTER_ENACT_CACTEXT_VLANONLY; + } + + aclActCtrl |= FILTER_ENACT_CVLAN_MASK; + break; + + case FILTER_ENACT_SVLAN_INGRESS: + case FILTER_ENACT_SVLAN_EGRESS: + aclAct.sact = FILTER_ENACT_SVLAN_TYPE(actType); + aclAct.svid = pAction->filterSvlanVid; + aclActCtrl |= FILTER_ENACT_SVLAN_MASK; + break; + + case FILTER_ENACT_SVLAN_CVID: + aclAct.sact = FILTER_ENACT_SVLAN_TYPE(actType); + aclActCtrl |= FILTER_ENACT_SVLAN_MASK; + break; + case FILTER_ENACT_POLICING_2: + if(pAction->filterPolicingIdx[2] > (RTL8373_METERMAX)) + return RT_ERR_INPUT; + + aclAct.sact = FILTER_ENACT_SVLAN_TYPE(actType); + aclAct.svid = pAction->filterPolicingIdx[2]; + aclActCtrl |= FILTER_ENACT_SVLAN_MASK; + break; + case FILTER_ENACT_POLICING_0: + if(pAction->filterPolicingIdx[0] > (RTL8373_METERMAX)) + return RT_ERR_INPUT; + + aclAct.aclMeterLoggIdx = pAction->filterPolicingIdx[0]; + aclAct.aclPolicingLogAct = FALSE; + aclActCtrl |= FILTER_ENACT_POLICING_LOGG_MASK; + break; + case FILTER_ENACT_PRIORITY: + if(pAction->filterAclPri > RTL8373_PRIMAX) + return RT_ERR_INPUT; + + aclAct.aclPri = pAction->filterAclPri; + aclActCtrl |= FILTER_ENACT_PRIORITY_MASK; + break; + + case FILTER_ENACT_1P_RMK: + if(pAction->filter1pRmk > RTL8373_PRIMAX) + return RT_ERR_INPUT; + + aclAct.aclRmkVal = pAction->filter1pRmk; + aclAct.aclRmkAct = FALSE; + aclActCtrl |= FILTER_ENACT_RMK_MASK; + break; + + case FILTER_ENACT_DSCP_RMK: + if(pAction->filterDscpRmk > RTL8373_DSCPMAX) + return RT_ERR_INPUT; + + aclAct.aclRmkVal = pAction->filterDscpRmk; + aclAct.aclRmkAct = TRUE; + aclActCtrl |= FILTER_ENACT_RMK_MASK; + break; + + case FILTER_ENACT_LOGGING_CNTR: + if(pAction->filterLoggCntr> RTL8373_LOGGINGMAX) + return RT_ERR_INPUT; + + aclAct.aclMeterLoggIdx = pAction->filterLoggCntr; + aclAct.aclPolicingLogAct = TRUE; + aclActCtrl |= FILTER_ENACT_POLICING_LOGG_MASK; + break; + + case FILTER_ENACT_ADD_DSTPORT: + RTK_CHK_PORTMASK_VALID(&pAction->filterPortmask); + + aclAct.fwdAct = FILTER_ENACT_FWD_TYPE(actType); + aclAct.fwdActExt = FALSE; + + if(rtk_switch_portmask_L2P_get(&pAction->filterPortmask, &portmask) != RT_ERR_OK) + return RT_ERR_PORT_MASK; + aclAct.fwdPmsk = portmask; + + aclActCtrl |= FILTER_ENACT_FWD_MASK; + break; + + case FILTER_ENACT_REDIRECT: + RTK_CHK_PORTMASK_VALID(&pAction->filterPortmask); + + aclAct.fwdAct = FILTER_ENACT_FWD_TYPE(actType); + aclAct.fwdActExt = FALSE; + + if(rtk_switch_portmask_L2P_get(&pAction->filterPortmask, &portmask) != RT_ERR_OK) + return RT_ERR_PORT_MASK; + aclAct.fwdPmsk = portmask; + + aclActCtrl |= FILTER_ENACT_FWD_MASK; + break; + + case FILTER_ENACT_DROP: + aclAct.fwdAct = FILTER_ENACT_FWD_TYPE(FILTER_ENACT_REDIRECT); + aclAct.fwdActExt = FALSE; + + aclAct.fwdPmsk = 0; + aclActCtrl |= FILTER_ENACT_FWD_MASK; + break; + + case FILTER_ENACT_MIRROR: + RTK_CHK_PORTMASK_VALID(&pAction->filterPortmask); + + aclAct.fwdAct = FILTER_ENACT_FWD_TYPE(actType); + aclAct.fwdActExt = FALSE; + + if(rtk_switch_portmask_L2P_get(&pAction->filterPortmask, &portmask) != RT_ERR_OK) + return RT_ERR_PORT_MASK; + aclAct.fwdPmsk = portmask; + + aclActCtrl |= FILTER_ENACT_FWD_MASK; + break; + + case FILTER_ENACT_TRAP_INT_CPU: + case FILTER_ENACT_TRAP_EXT_CPU: + case FILTER_ENACT_TRAP_INT_EXT_CPU: + aclAct.fwdAct = FILTER_ENACT_FWD_TYPE(actType); + aclAct.fwdActExt = FALSE; + + aclAct.fwdPmsk = 0; + aclActCtrl |= FILTER_ENACT_FWD_MASK; + break; + + case FILTER_ENACT_ISOLATION: + RTK_CHK_PORTMASK_VALID(&pAction->filterPortmask); + + aclAct.fwdActExt = TRUE; + + if(rtk_switch_portmask_L2P_get(&pAction->filterPortmask, &portmask) != RT_ERR_OK) + return RT_ERR_PORT_MASK; + aclAct.fwdPmsk = portmask; + + aclActCtrl |= FILTER_ENACT_FWD_MASK; + break; + + case FILTER_ENACT_INTERRUPT: + aclAct.aclInt = TRUE; + aclActCtrl |= FILTER_ENACT_INTGPIO_MASK; + break; + + case FILTER_ENACT_GPO: + aclAct.gpioEn = TRUE; + aclAct.gpioPin = pAction->filterPin; + aclActCtrl |= FILTER_ENACT_INTGPIO_MASK; + break; + + case FILTER_ENACT_BYPASS_IGRBW_STORMCTRL: + aclAct.bypassAct |= ACL_BYPASS_IGRBW_STORM_MASK; + aclActCtrl |= FILTER_ENACT_BYPASS_MASK; + break; + + case FILTER_ENACT_BYPASS_STP_SRC_CHK: + aclAct.bypassAct |= ACL_BYPASS_STP_SRC_CHK_MASK; + aclActCtrl |= FILTER_ENACT_BYPASS_MASK; + break; + + case FILTER_ENACT_BYPASS_IGRVLAN_FLTR: + aclAct.bypassAct |= ACL_BYPASS_IGRVLAN_FLTR_MASK; + aclActCtrl |= FILTER_ENACT_BYPASS_MASK; + break; + + case FILTER_ENACT_EGRESSCTAG_TAG: + if(aclActCtrl &(FILTER_ENACT_CVLAN_MASK)) + { + if(aclAct.cactExt == FILTER_ENACT_CACTEXT_VLANONLY) + aclAct.cactExt = FILTER_ENACT_CACTEXT_BOTHVLANTAG; + } + else + { + aclAct.cactExt = FILTER_ENACT_CACTEXT_TAGONLY; + } + aclAct.tagFmt = FILTER_CTAGFMT_TAG; + aclActCtrl |= FILTER_ENACT_CVLAN_MASK; + break; + case FILTER_ENACT_EGRESSCTAG_UNTAG: + + if(aclActCtrl &(FILTER_ENACT_CVLAN_MASK)) + { + if(aclAct.cactExt == FILTER_ENACT_CACTEXT_VLANONLY) + aclAct.cactExt = FILTER_ENACT_CACTEXT_BOTHVLANTAG; + } + else + { + aclAct.cactExt = FILTER_ENACT_CACTEXT_TAGONLY; + } + aclAct.tagFmt = FILTER_CTAGFMT_UNTAG; + aclActCtrl |= FILTER_ENACT_CVLAN_MASK; + break; + case FILTER_ENACT_EGRESSCTAG_REALKEEP: + + if(aclActCtrl &(FILTER_ENACT_CVLAN_MASK)) + { + if(aclAct.cactExt == FILTER_ENACT_CACTEXT_VLANONLY) + aclAct.cactExt = FILTER_ENACT_CACTEXT_BOTHVLANTAG; + } + else + { + aclAct.cactExt = FILTER_ENACT_CACTEXT_TAGONLY; + } + aclAct.tagFmt = FILTER_CTAGFMT_KEEP; + aclActCtrl |= FILTER_ENACT_CVLAN_MASK; + break; + case FILTER_ENACT_EGRESSCTAG_KEEPAND1PRMK: + + if(aclActCtrl &(FILTER_ENACT_CVLAN_MASK)) + { + if(aclAct.cactExt == FILTER_ENACT_CACTEXT_VLANONLY) + aclAct.cactExt = FILTER_ENACT_CACTEXT_BOTHVLANTAG; + } + else + { + aclAct.cactExt = FILTER_ENACT_CACTEXT_TAGONLY; + } + aclAct.tagFmt = FILTER_CTAGFMT_KEEP1PRMK; + aclActCtrl |= FILTER_ENACT_CVLAN_MASK; + break; + default: + return RT_ERR_FILTER_INACL_ACT_NOT_SUPPORT; + } + } + } + + /*check if free ACL rules are enough*/ + for(i = filterIdx; i < (filterIdx + noRulesAdd); i++) + { + if((retVal = _rtl8373_getAclRule(i, &tempRule)) != RT_ERR_OK ) + return retVal; + + if(tempRule.valid == TRUE) + { + return RT_ERR_TBL_FULL; + } + } + ruleId = 0; + for(i = 0; i < RTL8373_ACLTEMPLATENO; i++) + { + if(aclRule[i].valid == TRUE) + { + /* write ACL action control */ + RTK_ERR_CHK(rtl8373_setAsicRegBits(RTL8373_ACL_ACT_CTRL_ADDR(filterIdx+ruleId) , FILTER_ENACT_ALL_MASK, aclActCtrl)); + + /* write ACL action */ + if((retVal = _rtl8373_setAclAct(filterIdx + ruleId, &aclAct)) != RT_ERR_OK ) + return retVal; + + /* write ACL not */ + RTK_ERR_CHK(rtl8373_setAsicRegBit(RTL8373_ACL_ACT_CTRL_ADDR(filterIdx+ruleId) , RTL8373_ACL_ACT_CTRL_NOT_OFFSET, pFilterCfg->invert)); + + /* write ACL rule */ + if((retVal = _rtl8373_setAclRule(filterIdx + ruleId, &aclRule[i])) != RT_ERR_OK ) + return retVal; + + /* only the first rule will be written with input action control, aclActCtrl of other rules will be zero */ + aclActCtrl = 0; + memset(&aclAct, 0, sizeof(rtl8373_acl_act_t)); + + ruleId ++; + } + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_igrAcl_cfg_get + * Description: + * Get one ingress acl configuration from ASIC. + * Input: + * filterIdx - Start index of ACL configuration. + * Output: + * pFilterCfg - buffer pointer of ingress acl data + * pAction - buffer pointer of ingress acl action + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Pointer pAction or pFilterCfg point to NULL. + * RT_ERR_FILTER_ENTRYIDX - Invalid entry index. + * Note: + * This function get configuration from ASIC. + */ +rtk_api_ret_t dal_rtl8373_igrAcl_cfg_get(rtk_filter_id_t filterIdx, rtk_filter_cfg_raw_t *pFilterCfg, rtk_filter_action_t *pAction) +{ + rtk_api_ret_t retVal = 0; + rtk_uint32 i = 0, tmp = 0, actCtrlBits = 0; + rtl8373_acl_rule_t aclRule; + rtl8373_acl_act_t aclAct; + rtl8373_acl_template_t type; + rtk_uint32 phyPmask = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pFilterCfg || NULL == pAction) + return RT_ERR_NULL_POINTER; + + if(filterIdx > RTL8373_ACLRULEMAX) + return RT_ERR_ENTRY_INDEX; + + if ((retVal = _rtl8373_getAclRule(filterIdx, &aclRule)) != RT_ERR_OK) + return retVal; + + /* Check valid */ + if(aclRule.valid == INVALID) + { + pFilterCfg->valid = DISABLED; + return RT_ERR_OK; + } + + pFilterCfg->activeport.value.bits[0] = aclRule.data_bits.activePmsk; + pFilterCfg->activeport.mask.bits[0] = aclRule.care_bits.activePmsk; + + for(i = 0; i <= CARE_TAG_PPPOE; i++) + { + if(aclRule.data_bits.tagPppoe & (1 << i)) + pFilterCfg->careTag.tagType[i].value = 1; + else + pFilterCfg->careTag.tagType[i].value = 0; + + if (aclRule.care_bits.tagPppoe & (1 << i)) + pFilterCfg->careTag.tagType[i].mask = 1; + else + pFilterCfg->careTag.tagType[i].mask = 0; + } + + pFilterCfg->l3fmt.value = aclRule.data_bits.l3fmt; + pFilterCfg->l3fmt.mask = aclRule.care_bits.l3fmt; + + pFilterCfg->l4fmt.value = aclRule.data_bits.l4fmt; + pFilterCfg->l4fmt.mask = aclRule.care_bits.l4fmt; + + for(i = 0; i < RTL8373_ACLRULEFIELDNO; i++) + { + pFilterCfg->careFieldRaw[i] = aclRule.care_bits.field[i]; + pFilterCfg->dataFieldRaw[i] = aclRule.data_bits.field[i]; + } + + /*get not bit*/ + RTK_ERR_CHK(rtl8373_getAsicRegBit(RTL8373_ACL_ACT_CTRL_ADDR(filterIdx) , RTL8373_ACL_ACT_CTRL_NOT_OFFSET, &tmp)); + + pFilterCfg->invert = tmp; + pFilterCfg->valid = aclRule.valid; + + memset(pAction, 0, sizeof(rtk_filter_action_t)); + + /*get action control bits*/ + RTK_ERR_CHK(rtl8373_getAsicRegBits(RTL8373_ACL_ACT_CTRL_ADDR(filterIdx) , FILTER_ENACT_ALL_MASK, &actCtrlBits)); + if ((retVal =_rtl8373_getAclAct(filterIdx, &aclAct)) != RT_ERR_OK) + return retVal; + + if(actCtrlBits & FILTER_ENACT_FWD_MASK) + { + if(TRUE == aclAct.fwdActExt) + { + pAction->actEnable[FILTER_ENACT_ISOLATION] = TRUE; + + phyPmask = aclAct.fwdPmsk; + if(rtk_switch_portmask_P2L_get(phyPmask,&(pAction->filterPortmask)) != RT_ERR_OK) + return RT_ERR_FAILED; + } + else + { + if(aclAct.fwdAct == RTL8373_ACL_FWD_INT_TRAP) + { + pAction->actEnable[FILTER_ENACT_TRAP_INT_CPU] = TRUE; + } + else if(aclAct.fwdAct == RTL8373_ACL_FWD_EXT_TRAP) + { + pAction->actEnable[FILTER_ENACT_TRAP_EXT_CPU] = TRUE; + } + else if(aclAct.fwdAct == RTL8373_ACL_FWD_INT_EXT_TRAP) + { + pAction->actEnable[FILTER_ENACT_TRAP_INT_EXT_CPU] = TRUE; + } + else if (aclAct.fwdAct == RTL8373_ACL_FWD_MIRROR ) + { + pAction->actEnable[FILTER_ENACT_MIRROR] = TRUE; + + phyPmask = aclAct.fwdPmsk; + if(rtk_switch_portmask_P2L_get(phyPmask,&(pAction->filterPortmask)) != RT_ERR_OK) + return RT_ERR_FAILED; + } + else if (aclAct.fwdAct == RTL8373_ACL_FWD_REDIRECT) + { + if(aclAct.fwdPmsk == 0 ) + pAction->actEnable[FILTER_ENACT_DROP] = TRUE; + else + { + pAction->actEnable[FILTER_ENACT_REDIRECT] = TRUE; + + phyPmask = aclAct.fwdPmsk; + if(rtk_switch_portmask_P2L_get(phyPmask,&(pAction->filterPortmask)) != RT_ERR_OK) + return RT_ERR_FAILED; + } + } + else if (aclAct.fwdAct == RTL8373_ACL_FWD_COPY) + { + + pAction->actEnable[FILTER_ENACT_ADD_DSTPORT] = TRUE; + phyPmask = aclAct.fwdPmsk; + if(rtk_switch_portmask_P2L_get(phyPmask,&(pAction->filterPortmask)) != RT_ERR_OK) + return RT_ERR_FAILED; + } + else + { + return RT_ERR_FAILED; + } + } + } + + if(actCtrlBits & FILTER_ENACT_PRIORITY_MASK) + { + pAction->actEnable[FILTER_ENACT_PRIORITY] = TRUE; + pAction->filterAclPri = aclAct.aclPri; + } + + if(actCtrlBits & FILTER_ENACT_RMK_MASK) + { + if(TRUE == aclAct.aclRmkAct) + { + pAction->actEnable[FILTER_ENACT_DSCP_RMK] = TRUE; + pAction->filterDscpRmk= aclAct.aclRmkVal & 0x3F; + } + else + { + pAction->actEnable[FILTER_ENACT_1P_RMK] = TRUE; + pAction->filter1pRmk = aclAct.aclRmkVal & 0x7; + + } + } + + if(actCtrlBits & FILTER_ENACT_POLICING_LOGG_MASK) + { + if(TRUE == aclAct.aclPolicingLogAct) + { + pAction->actEnable[FILTER_ENACT_LOGGING_CNTR] = TRUE; + pAction->filterLoggCntr = aclAct.aclMeterLoggIdx & 0x1F; + } + else + { + pAction->actEnable[FILTER_ENACT_POLICING_0] = TRUE; + pAction->filterPolicingIdx[0] = aclAct.aclMeterLoggIdx & 0x3F; + } + } + if(actCtrlBits & FILTER_ENACT_SVLAN_MASK) + { + if(aclAct.sact == FILTER_ENACT_SVLAN_TYPE(FILTER_ENACT_SVLAN_INGRESS)) + { + pAction->actEnable[FILTER_ENACT_SVLAN_INGRESS] = TRUE; + pAction->filterSvlanVid = aclAct.svid; + } + else if(aclAct.sact == FILTER_ENACT_SVLAN_TYPE(FILTER_ENACT_SVLAN_EGRESS)) + { + + pAction->actEnable[FILTER_ENACT_SVLAN_EGRESS] = TRUE; + pAction->filterSvlanVid = aclAct.svid; + } + else if(aclAct.sact == FILTER_ENACT_SVLAN_TYPE(FILTER_ENACT_SVLAN_CVID)) + pAction->actEnable[FILTER_ENACT_SVLAN_CVID] = TRUE; + else if(aclAct.sact == FILTER_ENACT_SVLAN_TYPE(FILTER_ENACT_POLICING_2)) + { + pAction->actEnable[FILTER_ENACT_POLICING_2] = TRUE; + pAction->filterPolicingIdx[2] = aclAct.svid & 0x3F; + } + } + + if(actCtrlBits & FILTER_ENACT_CVLAN_MASK) + { + if(FILTER_ENACT_CACTEXT_TAGONLY == aclAct.cactExt || + FILTER_ENACT_CACTEXT_BOTHVLANTAG == aclAct.cactExt ) + { + if(FILTER_CTAGFMT_UNTAG == aclAct.tagFmt) + { + pAction->actEnable[FILTER_ENACT_EGRESSCTAG_UNTAG] = TRUE; + } + else if(FILTER_CTAGFMT_TAG == aclAct.tagFmt) + { + pAction->actEnable[FILTER_ENACT_EGRESSCTAG_TAG] = TRUE; + } + else if(FILTER_CTAGFMT_KEEP == aclAct.tagFmt) + { + pAction->actEnable[FILTER_ENACT_EGRESSCTAG_REALKEEP] = TRUE; + } + else if(FILTER_CTAGFMT_KEEP1PRMK== aclAct.tagFmt) + { + pAction->actEnable[FILTER_ENACT_EGRESSCTAG_KEEPAND1PRMK] = TRUE; + } + + } + + if(FILTER_ENACT_CACTEXT_VLANONLY == aclAct.cactExt || + FILTER_ENACT_CACTEXT_BOTHVLANTAG == aclAct.cactExt ) + { + if(aclAct.cact == FILTER_ENACT_CVLAN_TYPE(FILTER_ENACT_CVLAN_INGRESS)) + { + pAction->actEnable[FILTER_ENACT_CVLAN_INGRESS] = TRUE; + pAction->filterCvlanVid = aclAct.cvid; + } + else if(aclAct.cact == FILTER_ENACT_CVLAN_TYPE(FILTER_ENACT_CVLAN_EGRESS)) + { + + + pAction->actEnable[FILTER_ENACT_CVLAN_EGRESS] = TRUE; + pAction->filterCvlanVid = aclAct.cvid; + } + else if(aclAct.cact == FILTER_ENACT_CVLAN_TYPE(FILTER_ENACT_CVLAN_SVID)) + { + pAction->actEnable[FILTER_ENACT_CVLAN_SVID] = TRUE; + } + else if(aclAct.cact == FILTER_ENACT_CVLAN_TYPE(FILTER_ENACT_POLICING_1)) + { + pAction->actEnable[FILTER_ENACT_POLICING_1] = TRUE; + pAction->filterPolicingIdx[1] = aclAct.cvid & 0x3F; + } + } + } + + if(actCtrlBits & FILTER_ENACT_INTGPIO_MASK) + { + if(TRUE == aclAct.aclInt) + { + pAction->actEnable[FILTER_ENACT_INTERRUPT] = TRUE; + } + + if(TRUE == aclAct.gpioEn) + { + pAction->actEnable[FILTER_ENACT_GPO] = TRUE; + pAction->filterPin = aclAct.gpioPin; + } + } + + if(actCtrlBits & FILTER_ENACT_BYPASS_MASK) + { + if( (1<actEnable[ FILTER_ENACT_BYPASS_IGRBW_STORMCTRL] = TRUE; + } + if( (1<actEnable[ FILTER_ENACT_BYPASS_STP_SRC_CHK] = TRUE; + } + if( (1<actEnable[ FILTER_ENACT_BYPASS_IGRVLAN_FLTR] = TRUE; + } + } + + /* Get field type of RAW data */ + if ((retVal = _rtl8373_getAclTemplate(aclRule.data_bits.templateIdx, &type))!= RT_ERR_OK) + return retVal; + + for(i = 0; i < RTL8373_ACLRULEFIELDNO; i++) + { + + pFilterCfg->fieldRawType[i] = type.field[i]; + }/* end of for(i...) */ + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_igrAcl_cfg_del + * Description: + * Delete an ACL configuration from ASIC + * Input: + * filterIdx - Start index of ACL configuration. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_ENTRYIDX - Invalid filterIdx. + * Note: + * This function delete a group of ACL rules starting from filterIdx. + */ +rtk_api_ret_t dal_rtl8373_igrAcl_cfg_del(rtk_filter_id_t filterIdx) +{ + rtl8373_acl_rule_t initRule; + rtl8373_acl_act_t initAct; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(filterIdx > RTL8373_ACLRULEMAX ) + return RT_ERR_FILTER_ENTRYIDX; + + memset(&initRule, 0, sizeof(rtl8373_acl_rule_t)); + memset(&initAct, 0, sizeof(rtl8373_acl_act_t)); + + RTK_ERR_CHK( _rtl8373_setAclRule(filterIdx, &initRule)); + + /*set all action control bit = 1 & NOT bit ==disable*/ + RTK_ERR_CHK(rtl8373_setAsicReg(RTL8373_ACL_ACT_CTRL_ADDR(filterIdx), FILTER_ENACT_ALL_MASK)); + + RTK_ERR_CHK( _rtl8373_setAclAct(filterIdx, &initAct)); + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_igrAcl_cfg_delAll + * Description: + * Delete all ACL entries from ASIC + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This function delete all ACL configuration from ASIC. + */ +rtk_api_ret_t dal_rtl8373_igrAcl_cfg_delAll(void) +{ + rtk_uint32 idx = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + for(idx = 0; idx < RTL8373_ACLRULENO; idx++) + { + /*set all action control bit = 1 & NOT bit ==disable*/ + RTK_ERR_CHK(rtl8373_setAsicReg(RTL8373_ACL_ACT_CTRL_ADDR(idx), FILTER_ENACT_ALL_MASK)); + } + + return rtl8373_setAsicRegBit(RTL8373_ACL_CTRL_ADDR, RTL8373_ACL_CTRL_TABLE_RST_OFFSET, TRUE); +} + +/* Function Name: + * dal_rtl8373_igrAcl_unmatchAction_set + * Description: + * Set action to packets when no ACL configuration match + * Input: + * port - Port id. + * action - Action. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port id. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This function sets action of packets when no ACL configruation matches. + */ +rtk_api_ret_t dal_rtl8373_igrAcl_unmatchAction_set(rtk_port_t port, rtk_filter_unmatch_action_t action) +{ + rtk_api_ret_t ret; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check port valid */ + RTK_CHK_PORT_VALID(port); + + if(action >= FILTER_UNMATCH_END) + return RT_ERR_INPUT; + + if((ret = rtl8373_setAsicRegBit(RTL8373_ACL_PORT_UNMATCH_PERMIT_ADDR, rtk_switch_port_L2P_get(port), action)) != RT_ERR_OK) + return ret; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_igrAcl_unmatchAction_get + * Description: + * Get action to packets when no ACL configuration match + * Input: + * port - Port id. + * Output: + * pAction - Action. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port id. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This function gets action of packets when no ACL configruation matches. + */ +rtk_api_ret_t dal_rtl8373_igrAcl_unmatchAction_get(rtk_port_t port, rtk_filter_unmatch_action_t* pAction) +{ + rtk_api_ret_t ret; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pAction) + return RT_ERR_NULL_POINTER; + + /* Check port valid */ + RTK_CHK_PORT_VALID(port); + + if((ret = rtl8373_getAsicRegBit(RTL8373_ACL_PORT_UNMATCH_PERMIT_ADDR, rtk_switch_port_L2P_get(port), pAction)) != RT_ERR_OK) + return ret; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_igrAcl_state_set + * Description: + * Set state of ingress ACL. + * Input: + * port - Port id. + * state - Ingress ACL state. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port id. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This function gets action of packets when no ACL configruation matches. + */ +rtk_api_ret_t dal_rtl8373_igrAcl_state_set(rtk_port_t port, rtk_filter_state_t state) +{ + rtk_api_ret_t ret; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check port valid */ + RTK_CHK_PORT_VALID(port); + + if(state >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if((ret = rtl8373_setAsicRegBit(RTL8373_ACL_PORT_EN_ADDR, rtk_switch_port_L2P_get(port), state)) != RT_ERR_OK) + return ret; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_igrAcl_state_get + * Description: + * Get state of ingress ACL. + * Input: + * port - Port id. + * Output: + * pState - Ingress ACL state. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port id. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This function gets action of packets when no ACL configruation matches. + */ +rtk_api_ret_t dal_rtl8373_igrAcl_state_get(rtk_port_t port, rtk_filter_state_t* pState) +{ + rtk_api_ret_t ret = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pState) + return RT_ERR_NULL_POINTER; + + /* Check port valid */ + RTK_CHK_PORT_VALID(port); + + if((ret = rtl8373_getAsicRegBit(RTL8373_ACL_PORT_EN_ADDR, rtk_switch_port_L2P_get(port), pState)) != RT_ERR_OK) + return ret; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_igrAcl_template_set + * Description: + * Set template of ingress ACL. + * Input: + * template - Ingress ACL template + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This function set ACL template. + */ +rtk_api_ret_t dal_rtl8373_igrAcl_template_set(rtk_filter_template_t *aclTemplate) +{ + rtk_api_ret_t retVal = 0; + rtk_uint32 idxField = 0; + rtl8373_acl_template_t aclType; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(aclTemplate->index >= RTK_MAX_NUM_OF_FILTER_TYPE) + return RT_ERR_INPUT; + + for(idxField = 0; idxField < RTK_MAX_NUM_OF_FILTER_FIELD; idxField++) + { + if(aclTemplate->fieldType[idxField] < FILTER_FIELD_RAW_DMAC_15_0 || + (aclTemplate->fieldType[idxField] > FILTER_FIELD_RAW_CTAG && aclTemplate->fieldType[idxField] < FILTER_FIELD_RAW_SIP_15_0 ) || + (aclTemplate->fieldType[idxField] > FILTER_FIELD_RAW_DIP_31_16 && aclTemplate->fieldType[idxField] < FILTER_FIELD_RAW_VIDRANGE) || + (aclTemplate->fieldType[idxField] > FILTER_FIELD_RAW_L4DPORT && aclTemplate->fieldType[idxField] < FILTER_FIELD_RAW_FIELD_SELECT00 ) || + aclTemplate->fieldType[idxField] >= FILTER_FIELD_RAW_END) + { + return RT_ERR_INPUT; + } + } + + for(idxField = 0; idxField < RTK_MAX_NUM_OF_FILTER_FIELD; idxField++) + { + aclType.field[idxField] = aclTemplate->fieldType[idxField]; + } + + if((retVal = _rtl8373_setAclTemplate(aclTemplate->index, &aclType)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_igrAcl_template_get + * Description: + * Get template of ingress ACL. + * Input: + * template - Ingress ACL template + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This function gets template of ACL. + */ +rtk_api_ret_t dal_rtl8373_igrAcl_template_get(rtk_filter_template_t *aclTemplate) +{ + rtk_api_ret_t retVal; + rtk_uint32 idxField; + rtl8373_acl_template_t aclType; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == aclTemplate) + return RT_ERR_NULL_POINTER; + + if(aclTemplate->index >= RTK_MAX_NUM_OF_FILTER_TYPE) + return RT_ERR_INPUT; + + if((retVal = _rtl8373_getAclTemplate(aclTemplate->index, &aclType)) != RT_ERR_OK) + return retVal; + + for(idxField = 0; idxField < RTK_MAX_NUM_OF_FILTER_FIELD; idxField ++) + { + aclTemplate->fieldType[idxField] = aclType.field[idxField]; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_igrAcl_fieldSel_set + * Description: + * Set user defined field selectors in HSB + * Input: + * index - index of field selector 0-15 + * format - Format of field selector + * offset - Retrieving data offset + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * System support 16 user defined field selctors. + * Each selector can be enabled or disable. + * User can defined retrieving 16-bits in many predefiend + * standard l2/l3/l4 payload. + */ +rtk_api_ret_t dal_rtl8373_igrAcl_fieldSel_set(rtk_uint32 index, rtk_field_sel_t format, rtk_uint32 offset) +{ + rtk_api_ret_t ret; + rtk_uint32 regData; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(index >= RTL8373_FIELDSEL_FORMAT_NUMBER) + return RT_ERR_OUT_OF_RANGE; + + if(format >= FORMAT_END) + return RT_ERR_OUT_OF_RANGE; + + if(offset > RTL8373_FIELDSEL_MAX_OFFSET) + return RT_ERR_OUT_OF_RANGE; + + regData = ((rtk_uint32)format & RTL8373_PARSER_FIELD_SELTOR_CTRL_FMT_MASK ) |\ + ((offset << RTL8373_PARSER_FIELD_SELTOR_CTRL_OFFSET_OFFSET) & RTL8373_PARSER_FIELD_SELTOR_CTRL_OFFSET_MASK ); + + if((ret = rtl8373_setAsicReg(RTL8373_PARSER_FIELD_SELTOR_CTRL_ADDR(index), regData)) != RT_ERR_OK) + return ret; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_igrAcl_fieldSel_get + * Description: + * Get user defined field selectors in HSB + * Input: + * index - index of field selector 0-15 + * Output: + * pFormat - Format of field selector + * pOffset - Retrieving data offset + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * None. + */ +rtk_api_ret_t dal_rtl8373_igrAcl_fieldSel_get(rtk_uint32 index, rtk_field_sel_t *pFormat, rtk_uint32 *pOffset) +{ + rtk_api_ret_t ret = 0; + rtk_uint32 regData = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pFormat || NULL == pOffset) + return RT_ERR_NULL_POINTER; + + if(index >= RTL8373_FIELDSEL_FORMAT_NUMBER) + return RT_ERR_OUT_OF_RANGE; + + if((ret = rtl8373_getAsicReg(RTL8373_PARSER_FIELD_SELTOR_CTRL_ADDR(index), ®Data)) != RT_ERR_OK) + return ret; + + *pFormat = (rtk_field_sel_t)((regData & RTL8373_PARSER_FIELD_SELTOR_CTRL_FMT_MASK) >> RTL8373_PARSER_FIELD_SELTOR_CTRL_FMT_OFFSET); + *pOffset = ((regData & RTL8373_PARSER_FIELD_SELTOR_CTRL_OFFSET_MASK) >> RTL8373_PARSER_FIELD_SELTOR_CTRL_OFFSET_OFFSET); + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_igrAcl_ipRange_set + * Description: + * Set IP Range check + * Input: + * index - index of IP Range 0-15 + * type - IP Range check type, 0:Delete a entry, 1: IPv4_SIP, 2: IPv4_DIP, 3:IPv6_SIP, 4:IPv6_DIP + * upperIp - The upper bound of IP range + * lowerIp - The lower Bound of IP range + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - The parameter is out of range + * RT_ERR_INPUT - Input error + * Note: + * upperIp must be larger or equal than lowerIp. + */ +rtk_api_ret_t dal_rtl8373_igrAcl_ipRange_set(rtk_uint32 index, rtk_filter_iprange_t type, ipaddr_t upperIp, ipaddr_t lowerIp) +{ + rtk_uint32 retVal = 0; + rtk_uint32 regAddr = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(index > RTL8373_ACLRANGEMAX) + return RT_ERR_OUT_OF_RANGE; + + if(type >= IPRANGE_END) + return RT_ERR_OUT_OF_RANGE; + + if(lowerIp > upperIp) + return RT_ERR_INPUT; + + regAddr= RTL8373_RNG_CHK_IP_ADDR(index); + /*set type*/ + retVal = rtl8373_setAsicReg(regAddr, ((rtk_uint32)type) & RTL8373_RNG_CHK_IP_TYPE_MASK); + if(retVal != RT_ERR_OK) + return retVal; + + /*set lower boundary*/ + retVal = rtl8373_setAsicReg(regAddr+8, lowerIp); + if(retVal != RT_ERR_OK) + return retVal; + + /*set upper boundary*/ + retVal = rtl8373_setAsicReg(regAddr+4, upperIp); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_igrAcl_ipRange_get + * Description: + * Set IP Range check + * Input: + * index - index of IP Range 0-15 + * Output: + * pType - IP Range check type, 0:Delete a entry, 1: IPv4_SIP, 2: IPv4_DIP, 3:IPv6_SIP, 4:IPv6_DIP + * pUpperIp - The upper bound of IP range + * pLowerIp - The lower Bound of IP range + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - The parameter is out of range + * Note: + * None. + */ +rtk_api_ret_t dal_rtl8373_igrAcl_ipRange_get(rtk_uint32 index, rtk_filter_iprange_t *pType, ipaddr_t *pUpperIp, ipaddr_t *pLowerIp) +{ + rtk_api_ret_t retVal = 0; + rtk_uint32 regData = 0; + rtk_uint32 regAddr = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if((NULL == pType) || (NULL == pUpperIp) || (NULL == pLowerIp)) + return RT_ERR_NULL_POINTER; + + if(index > RTL8373_ACLRANGEMAX) + return RT_ERR_OUT_OF_RANGE; + + regAddr= RTL8373_RNG_CHK_IP_ADDR(index); + + + /*get type*/ + retVal = rtl8373_getAsicReg(regAddr, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + *pType = (rtk_filter_iprange_t)(regData & RTL8373_RNG_CHK_IP_TYPE_MASK); + + /*get lower boundary*/ + retVal = rtl8373_getAsicReg((regAddr + 8), pLowerIp); + if(retVal != RT_ERR_OK) + return retVal; + + /*get upper boundary*/ + retVal = rtl8373_getAsicReg(regAddr + 4, pUpperIp); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_igrAcl_vidRange_set + * Description: + * Set VID Range check + * Input: + * index - index of VID Range 0-15 + * type - IP Range check type, 0:Delete a entry, 1: CVID, 2: SVID + * upperVid - The upper bound of VID range + * lowerVid - The lower Bound of VID range + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - The parameter is out of range + * RT_ERR_INPUT - Input error + * Note: + * upperVid must be larger or equal than lowerVid. + */ +rtk_api_ret_t dal_rtl8373_igrAcl_vidRange_set(rtk_uint32 index, rtk_filter_vidrange_t type, rtk_uint32 upperVid, rtk_uint32 lowerVid) +{ + rtk_api_ret_t retVal = 0; + rtk_uint32 regData = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(index > RTL8373_ACLRANGEMAX) + return RT_ERR_OUT_OF_RANGE; + + if(type >= VIDRANGE_END) + return RT_ERR_OUT_OF_RANGE; + + if( (upperVid > RTK_VID_MAX ) || (lowerVid > upperVid)) + return RT_ERR_INPUT; + + regData = ( type | (lowerVid << RTL8373_RNG_CHK_VID_LOWER_OFFSET ) | (upperVid << RTL8373_RNG_CHK_VID_UPPER_OFFSET) ); + + retVal = rtl8373_setAsicReg(RTL8373_RNG_CHK_VID_ADDR(index), regData); + if(retVal != RT_ERR_OK) + return retVal; + + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_igrAcl_vidRange_get + * Description: + * Get VID Range check + * Input: + * index - index of VID Range 0-15 + * Output: + * pType - IP Range check type, 0:Unused, 1: CVID, 2: SVID + * pUpperVid - The upper bound of VID range + * pLowerVid - The lower Bound of VID range + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - The parameter is out of range + * Note: + * None. + */ +rtk_api_ret_t dal_rtl8373_igrAcl_vidRange_get(rtk_uint32 index, rtk_filter_vidrange_t *pType, rtk_uint32 *pUpperVid, rtk_uint32 *pLowerVid) +{ + rtk_uint32 regData = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if((NULL == pType) || (NULL == pUpperVid) || (NULL == pLowerVid)) + return RT_ERR_NULL_POINTER; + + if(index > RTL8373_ACLRANGEMAX) + return RT_ERR_OUT_OF_RANGE; + + RTK_ERR_CHK(rtl8373_getAsicReg(RTL8373_RNG_CHK_VID_ADDR(index), ®Data)); + + *pType = (rtk_filter_vidrange_t)(regData & RTL8373_RNG_CHK_VID_TYPE_MASK); + *pLowerVid = (regData & RTL8373_RNG_CHK_VID_LOWER_MASK) >> RTL8373_RNG_CHK_VID_LOWER_OFFSET; + *pUpperVid = (regData & RTL8373_RNG_CHK_VID_UPPER_MASK) >> RTL8373_RNG_CHK_VID_UPPER_OFFSET; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_igrAcl_portRange_set + * Description: + * Set Port Range check + * Input: + * index - index of Port Range 0-15 + * type - IP Range check type, 0:Delete a entry, 1: Source Port, 2: Destnation Port + * upperPort - The upper bound of Port range + * lowerPort - The lower Bound of Port range + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - The parameter is out of range + * RT_ERR_INPUT - Input error + * Note: + * upperPort must be larger or equal than lowerPort. + */ +rtk_api_ret_t dal_rtl8373_igrAcl_portRange_set(rtk_uint32 index, rtk_filter_portrange_t type, rtk_uint32 upperPort, rtk_uint32 lowerPort) +{ + rtk_uint32 regAddr = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(index > RTL8373_ACLRANGEMAX) + return RT_ERR_OUT_OF_RANGE; + + if(type >= PORTRANGE_END) + return RT_ERR_OUT_OF_RANGE; + + if(lowerPort > upperPort) + return RT_ERR_INPUT; + + if(upperPort > RTL8373_ACL_PORTRANGEMAX) + return RT_ERR_INPUT; + + if(lowerPort > RTL8373_ACL_PORTRANGEMAX) + return RT_ERR_INPUT; + + regAddr = RTL8373_RNG_CHK_PORT_ADDR(index); + RTK_ERR_CHK(rtl8373_setAsicReg(regAddr, (rtk_uint32)type)); + RTK_ERR_CHK(rtl8373_setAsicReg((regAddr + 4), ((upperPort << 16) | lowerPort))); + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_igrAcl_portRange_get + * Description: + * Set Port Range check + * Input: + * index - index of Port Range 0-15 + * Output: + * pType - IP Range check type, 0:Delete a entry, 1: Source Port, 2: Destnation Port + * pUpperPort - The upper bound of Port range + * pLowerPort - The lower Bound of Port range + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - The parameter is out of range + * RT_ERR_INPUT - Input error + * Note: + * None. + */ +rtk_api_ret_t dal_rtl8373_igrAcl_portRange_get(rtk_uint32 index, rtk_filter_portrange_t *pType, rtk_uint32 *pUpperPort, rtk_uint32 *pLowerPort) +{ + rtk_uint32 regAddr = 0; + rtk_uint32 regData = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if((NULL == pType) || (NULL == pUpperPort) || (NULL == pLowerPort)) + return RT_ERR_NULL_POINTER; + + if(index > RTL8373_ACLRANGEMAX) + return RT_ERR_OUT_OF_RANGE; + + regAddr = RTL8373_RNG_CHK_PORT_ADDR(index); + + RTK_ERR_CHK(rtl8373_getAsicReg(regAddr, ®Data)); + *pType = (rtk_filter_portrange_t)(regData & RTL8373_RNG_CHK_PORT_TYPE_MASK); + + RTK_ERR_CHK(rtl8373_getAsicReg((regAddr + 4), ®Data)); + *pLowerPort = (regData & 0xFFFF) ; + *pUpperPort = ((regData >> 16 )& 0xFFFF); + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_igrAcl_gpioPolarity_set + * Description: + * Set ACL Goip control palarity + * Input: + * polarity - 1: High, 0: Low + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * none + */ +rtk_api_ret_t dal_rtl8373_igrAcl_gpioPolarity_set(rtk_uint32 polarity) +{ + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(polarity >= RTL8373_GPIO_POLARITY_END) + return RT_ERR_OUT_OF_RANGE; + + RTK_ERR_CHK(rtl8373_setAsicReg(RTL8373_ACL_GPIO_CTRL_ADDR, polarity)); + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_igrAcl_gpioPolarity_get + * Description: + * Get ACL Goip control palarity + * Input: + * pPolarity - 1: High, 0: Low + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * none + */ +rtk_api_ret_t dal_rtl8373_igrAcl_gpioPolarity_get(rtk_uint32* pPolarity) +{ + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pPolarity) + return RT_ERR_NULL_POINTER; + + RTK_ERR_CHK(rtl8373_getAsicReg(RTL8373_ACL_GPIO_CTRL_ADDR, pPolarity)); + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_igrAcl_gpioEn_set + * Description: + * Enable ACL gpio pin + * Input: + * pinNum - gpio pin number + * enabled - enable or disable acl gpio funciton + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * none + */ +rtk_api_ret_t dal_rtl8373_igrAcl_gpioEn_set(rtk_uint32 pinNum, rtk_enable_t enabled) +{ + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(enabled >= RTK_ENABLE_END) + return RT_ERR_OUT_OF_RANGE; + + if(pinNum >= ACL_GPIO_ACT_PINNUM_MAX) + return RT_ERR_OUT_OF_RANGE; + + RTK_ERR_CHK(rtl8373_setAsicRegBit(RTL8373_IO_MUX_SEL_2_ADDR, pinNum, enabled)); + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_igrAcl_gpioEn_get + * Description: + * Get ACL gpio enable or not + * Input: + * pinNum - gpio pin number + * Output: + * *pEnabled - acl gpio pin status + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * none + */ +rtk_api_ret_t dal_rtl8373_igrAcl_gpioEn_get(rtk_uint32 pinNum, rtk_enable_t * pEnabled) +{ + rtk_uint32 regVal = 0; + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if( NULL == pEnabled) + return RT_ERR_NULL_POINTER; + if(pinNum >= ACL_GPIO_ACT_PINNUM_MAX) + return RT_ERR_OUT_OF_RANGE; + + RTK_ERR_CHK(rtl8373_getAsicRegBit(RTL8373_IO_MUX_SEL_2_ADDR, pinNum, ®Val)); + *pEnabled = (rtk_enable_t)regVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_igrAcl_table_rst + * Description: + * reset acl table :include acl rule table and action table + * Input: + * none + * Output: + * + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - The parameter is out of range + * Note: + * None. + */ +rtk_api_ret_t dal_rtl8373_igrAcl_table_rst(void) +{ + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + RTK_ERR_CHK(rtl8373_setAsicReg(RTL8373_ACL_CTRL_ADDR, ENABLED)); + return RT_ERR_OK; +} + diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_acl.h b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_acl.h new file mode 100755 index 00000000..0951f821 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_acl.h @@ -0,0 +1,712 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8373 switch high-level API + * + * Feature : The file includes ACL module high-layer API defination + * + */ + +#ifndef __DAL_RTL8373_ACL_H__ +#define __DAL_RTL8373_ACL_H__ + +#include + +#define RTL8373_ACLRULENO (96) + +#define RTL8373_ACLRULEMAX (RTL8373_ACLRULENO-1) +#define RTL8373_ACLRULEFIELDNO (8) +#define RTL8373_ACLTEMPLATENO (5) +#define RTL8373_ACLTYPEMAX (RTL8373_ACLTEMPLATENO-1) + +#define RTL8373_ACL_RULE_ENTRY_LEN (5) +#define RTL8373_ACL_ACT_ENTRY_LEN (3) +#define RTL8373_ACLRULE_VALIDBIT_OFFSET (21) + +#define RTL8373_ACLRULETBADDR(type, rule) ((type << 7) | rule) +#define RTL8373_ACLRULETBADDR2(type, rule) ((type << 5) | (rule + 64)) + +#define ACL_ACT_CVLAN_ENABLE_MASK (0x1) +#define ACL_ACT_SVLAN_ENABLE_MASK (0x2) +#define ACL_ACT_PRI_ENABLE_MASK (0x4) +#define ACL_ACT_1PRMK_ENABLE_MASK (0x8) +#define ACL_ACT_DSCPRMK_ENABLE_MASK (0x10) +#define ACL_ACT_POLICING_ENABLE_MASK (0x20) +#define ACL_ACT_LOGGING_ENABLE_MASK (0x40) +#define ACL_ACT_FWD_ENABLE_MASK (0x80) +#define ACL_ACT_INTGPIO_ENABLE_MASK (0x100) +#define ACL_ACT_BYPASS_ENABLE_MASK (0x200) + +#define RTL8373_ACLRULETAGBITS (5) +#define RTL8373_ACLRANGENO (16) +#define RTL8373_ACLTEMPLATE_MASK (7) +#define ACL_BYPASS_IGRBW_STORM_MASK (1) +#define ACL_BYPASS_STP_SRC_CHK_MASK (2) +#define ACL_BYPASS_IGRVLAN_FLTR_MASK (4) + + +#define RTL8373_ACLRANGEMAX (RTL8373_ACLRANGENO-1) + +#define RTL8373_ACL_PORTRANGEMAX (0xFFFF) + +#define RTL8373_FIELDSEL_FORMAT_NUMBER (16) +#define RTL8373_FIELDSEL_MAX_OFFSET (255) + +#define RTL8373_MAX_LOG_CNT_NUM (32) +#define RTL8373_RTK_IPV6_ADDR_WORD_LENGTH (2UL) + +#define RTL8373_ACLGPIOPINNO (16) + +#define ACL_RULE_TEMPLATE_IDX_OFFSET (0) +#define ACL_RULE_TAG_PPPOE_OFFSET (3) +#define ACL_RULE_L3FMT_OFFSET (6) +#define ACL_RULE_L4FMT_OFFSET (8) +#define ACL_RULE_ACTIVE_PMSK_OFFSET (11) + +enum RTL8373_ACL_GPIO_POLARITY +{ + RTL8373_GPIO_PULL_LOW = 0, + RTL8373_GPIO_PILL_HIGH, + RTL8373_GPIO_POLARITY_END +}; + +enum RTL8373_FIELDSEL_FORMAT_FORMAT +{ + RTL8373_FIELDSEL_FORMAT_DEFAULT = 0, + RTL8373_FIELDSEL_FORMAT_RAW, + RTL8373_FIELDSEL_FORMAT_LLC, + RTL8373_FIELDSEL_FORMAT_IPV4, + RTL8373_FIELDSEL_FORMAT_ARP, + RTL8373_FIELDSEL_FORMAT_IPV6, + RTL8373_FIELDSEL_FORMAT_IPPAYLOAD, + RTL8373_FIELDSEL_FORMAT_L4PAYLOAD, + RTL8373_FIELDSEL_FORMAT_END +}; + +enum RTL8373_ACLFIELDTYPES +{ + RTL8373_ACL_DMAC0 = 0, + RTL8373_ACL_DMAC1, + RTL8373_ACL_DMAC2, + RTL8373_ACL_SMAC0, + RTL8373_ACL_SMAC1, + RTL8373_ACL_SMAC2, + RTL8373_ACL_ETHERTYPE, + RTL8373_ACL_STAG, + RTL8373_ACL_CTAG, + + RTL8373_ACL_IP4SIP0 = 0x10, + RTL8373_ACL_IP4SIP1, + RTL8373_ACL_IP4DIP0, + RTL8373_ACL_IP4DIP1, + + RTL8373_ACL_VIDRANGE = 0x30, + RTL8373_ACL_IPRANGE, + RTL8373_ACL_PORTRANGE, + RTL8373_ACL_FIELD_VALID, + RTL8373_ACL_IPTOSPROTO, + RTL8373_ACL_L4SPORT, + RTL8373_ACL_L4DPORT, + + RTL8373_ACL_FIELD_SELECT00 = 0x40, + RTL8373_ACL_FIELD_SELECT01, + RTL8373_ACL_FIELD_SELECT02, + RTL8373_ACL_FIELD_SELECT03, + RTL8373_ACL_FIELD_SELECT04, + RTL8373_ACL_FIELD_SELECT05, + RTL8373_ACL_FIELD_SELECT06, + RTL8373_ACL_FIELD_SELECT07, + RTL8373_ACL_FIELD_SELECT08, + RTL8373_ACL_FIELD_SELECT09, + RTL8373_ACL_FIELD_SELECT10, + RTL8373_ACL_FIELD_SELECT11, + RTL8373_ACL_FIELD_SELECT12, + RTL8373_ACL_FIELD_SELECT13, + RTL8373_ACL_FIELD_SELECT14, + RTL8373_ACL_FIELD_SELECT15, + RTL8373_ACL_TYPE_END +}; + +enum RTL8373_ACLTCAMTYPES +{ + RTL8373_CAREBITS= 0, + RTL8373_DATABITS +}; + +typedef enum rtl8373_aclFwd +{ + RTL8373_ACL_FWD_COPY = 0, + RTL8373_ACL_FWD_REDIRECT, + RTL8373_ACL_FWD_MIRROR , + RTL8373_ACL_FWD_INT_TRAP, + RTL8373_ACL_FWD_EXT_TRAP, + RTL8373_ACL_FWD_INT_EXT_TRAP, +} rtl8373_aclFwd_t; + + +struct acl_rule_smi_st{ + rtk_uint32 field[RTL8373_ACLRULEFIELDNO/2]; + rtk_uint32 rule_info; +}; + +typedef struct RTL8373_aclRule_SMI{ + struct acl_rule_smi_st care_bits; + rtk_uint32 valid:1; + struct acl_rule_smi_st data_bits; +}rtl8373_aclRule_smi_t; + +typedef struct acl_ruleContent_s{ + rtk_uint32 templateIdx:3; + rtk_uint32 tagPppoe:3; + rtk_uint32 l3fmt:2; + rtk_uint32 l4fmt:3; + rtk_uint32 activePmsk:10; + + rtk_uint16 field[RTL8373_ACLRULEFIELDNO]; +}acl_ruleContent_t; + +typedef struct rtl8373_acl_rule_s{ + acl_ruleContent_t data_bits; + rtk_uint32 valid:1; + acl_ruleContent_t care_bits; +}rtl8373_acl_rule_t; + + +typedef struct rtl8373_acl_template_s{ + rtk_uint8 field[RTL8373_ACLRULEFIELDNO]; +}rtl8373_acl_template_t; + + +typedef struct rtl8373_acl_act_s{ + rtk_uint32 cact:2; + rtk_uint32 cactExt:2; + rtk_uint32 cvid:12; + rtk_uint32 tagFmt:2; + rtk_uint32 sact:2; + rtk_uint32 svid:12; + + + rtk_uint32 aclPri:3; + rtk_uint32 aclRmkAct:1; + rtk_uint32 aclRmkVal:6; + rtk_uint32 aclPolicingLogAct:1; + rtk_uint32 aclMeterLoggIdx:6; + + rtk_uint32 fwdPmsk:10; + rtk_uint32 fwdAct:3; + rtk_uint32 fwdActExt:1; + rtk_uint32 aclInt:1; + rtk_uint32 gpioEn:1; + rtk_uint32 gpioPin:4; + rtk_uint32 bypassAct:3; + +}rtl8373_acl_act_t; + +typedef struct rtl8373_acl_ruleUnion_s +{ + rtl8373_acl_rule_t aclRule; + rtl8373_acl_act_t aclAct; + rtk_uint32 aclActCtrl; + rtk_uint32 aclNot; +}rtl8373_acl_ruleUnion_t; + +extern rtk_api_ret_t _rtl8373_setAclRule(rtk_uint32 index, rtl8373_acl_rule_t* pAclRule); +extern rtk_api_ret_t _rtl8373_getAclRule(rtk_uint32 index, rtl8373_acl_rule_t* pAclRule); + + +/* Function Name: + * dal_rtl8373_igrAcl_init + * Description: + * ACL initialization function + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Pointer pFilter_field or pFilter_cfg point to NULL. + * Note: + * This function enable and intialize ACL function + */ +extern rtk_api_ret_t dal_rtl8373_igrAcl_init(void); + +/* Function Name: + * dal_rtl8373_igrAcl_field_add + * Description: + * Add comparison rule to an ACL configuration + * Input: + * pFilterCfg - The ACL configuration that this function will add comparison rule + * pFilterField - The comparison rule that will be added. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Pointer pFilter_field or pFilter_cfg point to NULL. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This function add a comparison rule (*pFilter_field) to an ACL configuration (*pFilter_cfg). + * Pointer pFilter_cfg points to an ACL configuration structure, this structure keeps multiple ACL + * comparison rules by means of linked list. Pointer pFilter_field will be added to linked + * list keeped by structure that pFilter_cfg points to. + */ +extern rtk_api_ret_t dal_rtl8373_igrAcl_field_add(rtk_filter_cfg_t* pFilterCfg, rtk_filter_field_t* pFilterField); + +/* Function Name: + * dal_rtl8373_igrAcl_cfg_delAll + * Description: + * Delete all ACL entries from ASIC + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This function delete all ACL configuration from ASIC. + */ +extern rtk_api_ret_t dal_rtl8373_igrAcl_cfg_delAll(void); + +/* Function Name: + * dal_rtl8373_igrAcl_cfg_add + * Description: + * Add an ACL configuration to ASIC + * Input: + * filterIdx - Start index of ACL configuration. + * pFilterCfg - The ACL configuration that this function will add comparison rule + * pAction - Action(s) of ACL configuration. + * Output: + * ruleNum - number of rules written in acl table + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Pointer pFilter_field or pFilter_cfg point to NULL. + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_ENTRY_INDEX - Invalid filter_id . + * RT_ERR_NULL_POINTER - Pointer pFilter_action or pFilter_cfg point to NULL. + * RT_ERR_FILTER_INACL_ACT_NOT_SUPPORT - Action is not supported in this chip. + * RT_ERR_FILTER_INACL_RULE_NOT_SUPPORT - Rule is not supported. + * Note: + * This function store pFilter_cfg, pFilter_action into ASIC. The starting + * index(es) is filter_id. + */ +extern rtk_api_ret_t dal_rtl8373_igrAcl_cfg_add(rtk_filter_id_t filterIdx, rtk_filter_cfg_t* pFilterCfg, rtk_filter_action_t* pAction, rtk_filter_number_t *ruleNum); + +/* Function Name: + * dal_rtl8373_igrAcl_cfg_del + * Description: + * Delete an ACL configuration from ASIC + * Input: + * filterIdx - Start index of ACL configuration. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_ENTRYIDX - Invalid filter_id. + * Note: + * This function delete a group of ACL rules starting from filter_id. + */ +extern rtk_api_ret_t dal_rtl8373_igrAcl_cfg_del(rtk_filter_id_t filterIdx); + + +/* Function Name: + * dal_rtl8373_igrAcl_cfg_get + * Description: + * Get one ingress acl configuration from ASIC. + * Input: + * filterIdx - Start index of ACL configuration. + * Output: + * pFilterCfg - buffer pointer of ingress acl data + * pAction - buffer pointer of ingress acl action + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Pointer pFilter_action or pFilter_cfg point to NULL. + * RT_ERR_FILTER_ENTRYIDX - Invalid entry index. + * Note: + * This function get configuration from ASIC. + */ +extern rtk_api_ret_t dal_rtl8373_igrAcl_cfg_get(rtk_filter_id_t filterIdx, rtk_filter_cfg_raw_t *pFilterCfg, rtk_filter_action_t *pAction); + +/* Function Name: + * dal_rtl8373_igrAcl_unmatchAction_set + * Description: + * Set action to packets when no ACL configuration match + * Input: + * port - Port id. + * action - Action. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port id. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This function sets action of packets when no ACL configruation matches. + */ +extern rtk_api_ret_t dal_rtl8373_igrAcl_unmatchAction_set(rtk_port_t port, rtk_filter_unmatch_action_t action); + +/* Function Name: + * dal_rtl8373_igrAcl_unmatchAction_get + * Description: + * Get action to packets when no ACL configuration match + * Input: + * port - Port id. + * Output: + * pAction - Action. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port id. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This function gets action of packets when no ACL configruation matches. + */ +extern rtk_api_ret_t dal_rtl8373_igrAcl_unmatchAction_get(rtk_port_t port, rtk_filter_unmatch_action_t* pAction); + +/* Function Name: + * dal_rtl8373_igrAcl_state_set + * Description: + * Set state of ingress ACL. + * Input: + * port - Port id. + * state - Ingress ACL state. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port id. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This function gets action of packets when no ACL configruation matches. + */ +extern rtk_api_ret_t dal_rtl8373_igrAcl_state_set(rtk_port_t port, rtk_filter_state_t state); + +/* Function Name: + * dal_rtl8373_igrAcl_state_get + * Description: + * Get state of ingress ACL. + * Input: + * port - Port id. + * Output: + * pState - Ingress ACL state. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port id. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This function gets action of packets when no ACL configruation matches. + */ +extern rtk_api_ret_t dal_rtl8373_igrAcl_state_get(rtk_port_t port, rtk_filter_state_t* pState); + +/* Function Name: + * dal_rtl8373_igrAcl_template_set + * Description: + * Set template of ingress ACL. + * Input: + * template - Ingress ACL template + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This function set ACL template. + */ +extern rtk_api_ret_t dal_rtl8373_igrAcl_template_set(rtk_filter_template_t *aclTemplate); + +/* Function Name: + * dal_rtl8373_igrAcl_template_get + * Description: + * Get template of ingress ACL. + * Input: + * template - Ingress ACL template + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This function gets template of ACL. + */ +extern rtk_api_ret_t dal_rtl8373_igrAcl_template_get(rtk_filter_template_t *aclTemplate); + +/* Function Name: + * dal_rtl8373_igrAcl_fieldSel_set + * Description: + * Set user defined field selectors in HSB + * Input: + * index - index of field selector 0-15 + * format - Format of field selector + * offset - Retrieving data offset + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * System support 16 user defined field selctors. + * Each selector can be enabled or disable. + * User can defined retrieving 16-bits in many predefiend + * standard l2/l3/l4 payload. + */ +extern rtk_api_ret_t dal_rtl8373_igrAcl_fieldSel_set(rtk_uint32 index, rtk_field_sel_t format, rtk_uint32 offset); + +/* Function Name: + * dal_rtl8373_igrAcl_fieldSel_get + * Description: + * Get user defined field selectors in HSB + * Input: + * index - index of field selector 0-15 + * Output: + * pFormat - Format of field selector + * pOffset - Retrieving data offset + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * None. + */ +extern rtk_api_ret_t dal_rtl8373_igrAcl_fieldSel_get(rtk_uint32 index, rtk_field_sel_t *pFormat, rtk_uint32 *pOffset); + +/* Function Name: + * dal_rtl8373_igrAcl_ipRange_set + * Description: + * Set IP Range check + * Input: + * index - index of IP Range 0-15 + * type - IP Range check type, 0:Delete a entry, 1: IPv4_SIP, 2: IPv4_DIP, 3:IPv6_SIP, 4:IPv6_DIP + * upperIp - The upper bound of IP range + * lowerIp - The lower Bound of IP range + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - The parameter is out of range + * RT_ERR_INPUT - Input error + * Note: + * upperIp must be larger or equal than lowerIp. + */ +extern rtk_api_ret_t dal_rtl8373_igrAcl_ipRange_set(rtk_uint32 index, rtk_filter_iprange_t type, ipaddr_t upperIp, ipaddr_t lowerIp); + +/* Function Name: + * dal_rtl8373_igrAcl_ipRange_get + * Description: + * Set IP Range check + * Input: + * index - index of IP Range 0-15 + * Output: + * pType - IP Range check type, 0:Delete a entry, 1: IPv4_SIP, 2: IPv4_DIP, 3:IPv6_SIP, 4:IPv6_DIP + * pUpperIp - The upper bound of IP range + * pLowerIp - The lower Bound of IP range + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - The parameter is out of range + * Note: + * None. + */ +extern rtk_api_ret_t dal_rtl8373_igrAcl_ipRange_get(rtk_uint32 index, rtk_filter_iprange_t *pType, ipaddr_t *pUpperIp, ipaddr_t *pLowerIp); + +/* Function Name: + * dal_rtl8373_igrAcl_vidRange_set + * Description: + * Set VID Range check + * Input: + * index - index of VID Range 0-15 + * type - IP Range check type, 0:Delete a entry, 1: CVID, 2: SVID + * upperVid - The upper bound of VID range + * lowerVid - The lower Bound of VID range + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - The parameter is out of range + * RT_ERR_INPUT - Input error + * Note: + * upperVid must be larger or equal than lowerVid. + */ +extern rtk_api_ret_t dal_rtl8373_igrAcl_vidRange_set(rtk_uint32 index, rtk_filter_vidrange_t type, rtk_uint32 upperVid, rtk_uint32 lowerVid); + +/* Function Name: + * dal_rtl8373_igrAcl_vidRange_get + * Description: + * Get VID Range check + * Input: + * index - index of VID Range 0-15 + * Output: + * pType - IP Range check type, 0:Unused, 1: CVID, 2: SVID + * pUpperVid - The upper bound of VID range + * pLowerVid - The lower Bound of VID range + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - The parameter is out of range + * Note: + * None. + */ +extern rtk_api_ret_t dal_rtl8373_igrAcl_vidRange_get(rtk_uint32 index, rtk_filter_vidrange_t *pType, rtk_uint32 *pUpperVid, rtk_uint32 *pLowerVid); + +/* Function Name: + * dal_rtl8373_igrAcl_portRange_set + * Description: + * Set Port Range check + * Input: + * index - index of Port Range 0-15 + * type - IP Range check type, 0:Delete a entry, 1: Source Port, 2: Destnation Port + * upperPort - The upper bound of Port range + * lowerPort - The lower Bound of Port range + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - The parameter is out of range + * RT_ERR_INPUT - Input error + * Note: + * upperPort must be larger or equal than lowerPort. + */ +extern rtk_api_ret_t dal_rtl8373_igrAcl_portRange_set(rtk_uint32 index, rtk_filter_portrange_t type, rtk_uint32 upperPort, rtk_uint32 lowerPort); + +/* Function Name: + * dal_rtl8373_igrAcl_portRange_get + * Description: + * Set Port Range check + * Input: + * index - index of Port Range 0-15 + * Output: + * pType - IP Range check type, 0:Delete a entry, 1: Source Port, 2: Destnation Port + * pUpperPort - The upper bound of Port range + * pLowerPort - The lower Bound of Port range + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - The parameter is out of range + * RT_ERR_INPUT - Input error + * Note: + * None. + */ +extern rtk_api_ret_t dal_rtl8373_igrAcl_portRange_get(rtk_uint32 index, rtk_filter_portrange_t *pType, rtk_uint32 *pUpperPort, rtk_uint32 *pLowerPort); + +/* Function Name: + * dal_rtl8373_igrAcl_gpioPolarity_set + * Description: + * Set ACL Goip control palarity + * Input: + * polarity - 1: High, 0: Low + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * none + */ +extern rtk_api_ret_t dal_rtl8373_igrAcl_gpioPolarity_set(rtk_uint32 polarity); + +/* Function Name: + * dal_rtl8373_igrAcl_gpioPolarity_get + * Description: + * Get ACL Goip control palarity + * Input: + * pPolarity - 1: High, 0: Low + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * none + */ +extern rtk_api_ret_t dal_rtl8373_igrAcl_gpioPolarity_get(rtk_uint32* pPolarity); + +/* Function Name: + * dal_rtl8373_igrAcl_gpioEn_set + * Description: + * Enable ACL gpio function + * Input: + * pinNum - gpio pin number + * enabled - enable or disable acl gpio funciton + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * none + */ +extern rtk_api_ret_t dal_rtl8373_igrAcl_gpioEn_set(rtk_uint32 pinNum, rtk_enable_t enabled); + +/* Function Name: + * dal_rtl8373_igrAcl_gpioEn_get + * Description: + * Get ACL gpio enable or not + * Input: + * pinNum - gpio pin number + * Output: + * *pEnabled - acl gpio pin status + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * none + */ +extern rtk_api_ret_t dal_rtl8373_igrAcl_gpioEn_get(rtk_uint32 pinNum, rtk_enable_t * pEnabled); + +/* Function Name: + * dal_rtl8373_igrAcl_table_rst + * Description: + * reset acl table :include acl rule table and action table + * Input: + * none + * Output: + * + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - The parameter is out of range + * Note: + * None. + */ +extern rtk_api_ret_t dal_rtl8373_igrAcl_table_rst(void); + + +#endif /* __DAL_RTL8373_ACL_H__ */ diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_cpuTag.c b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_cpuTag.c new file mode 100755 index 00000000..bf646f92 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_cpuTag.c @@ -0,0 +1,516 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8373 + * Feature : Here is a list of all functions and variables in CPU module. + * + */ + +#include +#include +#include +#include +#include + +/* Function Name: + * dal_rtl8373_cpuTag_externalCpuPort_set + * Description: + * Set external cpu port + * Input: + * extCpuPort - port number + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * API can set destination port of trapping frame + */ +rtk_api_ret_t dal_rtl8373_cpuTag_externalCpuPort_set(rtk_uint32 extCpuPort) +{ + rtk_api_ret_t retVal = 0; + + if((extCpuPort > RTK_MAX_NUM_OF_PORT-2) && (extCpuPort != 0xF)) + return RT_ERR_PORT_MASK; + + retVal = rtl8373_setAsicRegBits(RTL8373_EXT_CPU_CTRL_ADDR , RTL8373_EXT_CPU_CTRL_PORT_MASK, extCpuPort); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_cpuTag_externalCpuPort_get + * Description: + * Get external cpu port + * Input: + * None + * Output: + * pExtCpuPort - port number + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +rtk_api_ret_t dal_rtl8373_cpuTag_externalCpuPort_get(rtk_uint32 *pExtCpuPort) +{ + rtk_api_ret_t retVal= 0; + + if(pExtCpuPort == NULL) + return RT_ERR_NULL_POINTER; + + retVal = rtl8373_getAsicRegBits(RTL8373_EXT_CPU_CTRL_ADDR , RTL8373_EXT_CPU_CTRL_PORT_MASK, pExtCpuPort); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_cpuTag_tpid_set + * Description: + * Set cpu tag protocol id + * Input: + * tpid - protocol ID + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +rtk_api_ret_t dal_rtl8373_cpuTag_tpid_set(rtk_uint32 tpid) +{ + rtk_api_ret_t retVal = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + if(tpid >= RTK_MAX_NUM_OF_PROTO_TYPE) + return RT_ERR_INPUT; + + retVal = rtl8373_setAsicRegBits(RTL8373_CPU_TAG_TPID_CTRL_ADDR, RTL8373_CPU_TAG_TPID_CTRL_TPID_MASK, tpid); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_cpuTag_tpid_get + * Description: + * Get cpu tag protocol id + * Input: + * None + * Output: + * pTpid - protocol ID + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +rtk_api_ret_t dal_rtl8373_cpuTag_tpid_get(rtk_uint32 *pTpid) +{ + rtk_api_ret_t retVal = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(pTpid == NULL) + return RT_ERR_NULL_POINTER; + + retVal = rtl8373_getAsicRegBits(RTL8373_CPU_TAG_TPID_CTRL_ADDR, RTL8373_CPU_TAG_TPID_CTRL_TPID_MASK, pTpid); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_cpuTag_enable_set + * Description: + * Set CPU port function enable/disable. + * Input: + * type - CPU type: internal cpu or external cpu + * status - CPU port function enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can set CPU port function enable/disable. + */ +rtk_api_ret_t dal_rtl8373_cpuTag_enable_set(rtk_cpu_type_t type, rtk_enable_t status) +{ + rtk_api_ret_t retVal = 0; + rtk_uint32 extCpuPort = 0, awarePmsk = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if ((type >= CPU_TYPE_END) || (status >= RTK_ENABLE_END)) + return RT_ERR_INPUT; + + /*update cpu tag aware portmask*/ + if ((retVal = rtl8373_getAsicRegBits(RTL8373_CPU_TAG_AWARE_CTRL_ADDR, RTL8373_CPU_TAG_AWARE_CTRL_PMSK_MASK, &awarePmsk)) != RT_ERR_OK) + return retVal; + + if(type) + { + if ((retVal = rtl8373_getAsicRegBits(RTL8373_EXT_CPU_CTRL_ADDR, RTL8373_EXT_CPU_CTRL_PORT_MASK, &extCpuPort)) != RT_ERR_OK) + return retVal; + + if(status == ENABLED) + awarePmsk |= (1 << extCpuPort); + else + awarePmsk &= (~(1 << extCpuPort)); + + /*cfg cpu tag enable status*/ + if ((retVal = rtl8373_setAsicRegBit(RTL8373_CPU_TAG_CTRL_ADDR, RTL8373_CPU_TAG_CTRL_EXT_CPUTAG_EN_OFFSET, (status == ENABLED ? 1:0))) != RT_ERR_OK) + return retVal; + } + else + { + if(status == ENABLED) + awarePmsk |= INTERNAL_CPU_PMSK; + else + awarePmsk &= (INTERNAL_CPU_PMSK-1); + + /*cfg cpu tag enable status*/ + if ((retVal = rtl8373_setAsicRegBit(RTL8373_CPU_TAG_CTRL_ADDR, RTL8373_CPU_TAG_CTRL_INT_CPUTAG_EN_OFFSET, (status == ENABLED ? 1:0))) != RT_ERR_OK) + return retVal; + } + + /*write_back cpu tag aware portmask*/ + if ((retVal = rtl8373_setAsicRegBits(RTL8373_CPU_TAG_AWARE_CTRL_ADDR, RTL8373_CPU_TAG_AWARE_CTRL_PMSK_MASK, awarePmsk)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_cpuTag_enable_get + * Description: + * Get CPU port and its setting. + * Input: + * type - CPU type: internal cpu or external cpu + * Output: + * pStatus - CPU port function enable + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_L2_NO_CPU_PORT - CPU port is not exist + * Note: + * The API can get CPU port function enable/disable. + */ +rtk_api_ret_t dal_rtl8373_cpuTag_enable_get(rtk_cpu_type_t type, rtk_enable_t *pStatus) +{ + rtk_api_ret_t retVal = 0; + rtk_uint32 regData = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pStatus) + return RT_ERR_NULL_POINTER; + + if (type >= CPU_TYPE_END) + return RT_ERR_INPUT; + + if ((retVal = rtl8373_getAsicReg(RTL8373_CPU_TAG_CTRL_ADDR, ®Data)) != RT_ERR_OK) + return retVal; + + if(!type) + *pStatus = (rtk_enable_t)((regData & RTL8373_CPU_TAG_CTRL_INT_CPUTAG_EN_MASK) >> RTL8373_CPU_TAG_CTRL_INT_CPUTAG_EN_OFFSET); + else + *pStatus = (rtk_enable_t)((regData & RTL8373_CPU_TAG_CTRL_EXT_CPUTAG_EN_MASK) >> RTL8373_CPU_TAG_CTRL_EXT_CPUTAG_EN_OFFSET); + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_cpuTag_insertMode_set + * Description: + * Set internal & external CPU port tag insert mode. + * Input: + * type - - CPU type: internal cpu or external cpu + * mode - CPU tag insert for packets egress from CPU port. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can set CPU inserting proprietary CPU tag mode (Length/Type 0x8899) + * to the frame that transmitting to CPU port. + * The inset cpu tag mode is as following: + * - CPU_INSERT_TO_ALL + * - CPU_INSERT_TO_TRAPPING + * - CPU_INSERT_TO_NONE + */ +rtk_api_ret_t dal_rtl8373_cpuTag_insertMode_set(rtk_cpu_type_t type, rtk_cpuTag_insertMode_t mode) +{ + rtk_api_ret_t retVal = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if( (mode >= CPU_INSERT_END) || (type >= CPU_TYPE_END)) + return RT_ERR_INPUT; + if(type) + { + if ((retVal = rtl8373_setAsicRegBits(RTL8373_CPU_TAG_CTRL_ADDR, RTL8373_CPU_TAG_CTRL_EXT_CPUTAG_INSERTMOD_MASK, (rtk_uint32)(mode))) != RT_ERR_OK) + return retVal; + } + else + { + if ((retVal = rtl8373_setAsicRegBits(RTL8373_CPU_TAG_CTRL_ADDR, RTL8373_CPU_TAG_CTRL_INT_CPUTAG_INSERTMOD_MASK, (rtk_uint32)(mode))) != RT_ERR_OK) + return retVal; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_cpuTag_insertMode_get + * Description: + * Get internal & external CPU port tag insert mode. + * Input: + * type - - CPU type: internal cpu or external cpu + * Output: + * pMode - CPU tag insert for packets egress from CPU port, 0:all insert 1:Only for trapped packets 2:no insert. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_L2_NO_CPU_PORT - CPU port is not exist + * Note: + * The API can get configured CPU insert mode. + * The inset cpu tag mode is as following: + * - CPU_INSERT_TO_ALL + * - CPU_INSERT_TO_TRAPPING + * - CPU_INSERT_TO_NONE + */ +rtk_api_ret_t dal_rtl8373_cpuTag_insertMode_get(rtk_cpu_type_t type, rtk_cpuTag_insertMode_t *pMode) +{ + rtk_api_ret_t retVal = 0; + rtk_uint32 regData = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pMode) + return RT_ERR_NULL_POINTER; + + if(type >= CPU_TYPE_END) + return RT_ERR_INPUT; + + if ((retVal = rtl8373_getAsicReg(RTL8373_CPU_TAG_CTRL_ADDR, ®Data)) != RT_ERR_OK) + return retVal; + + if(type) + { + *pMode = (rtk_cpuTag_insertMode_t)((regData & RTL8373_CPU_TAG_CTRL_EXT_CPUTAG_INSERTMOD_MASK) >> RTL8373_CPU_TAG_CTRL_EXT_CPUTAG_INSERTMOD_OFFSET); + } else { + *pMode = (rtk_cpuTag_insertMode_t)((regData & RTL8373_CPU_TAG_CTRL_INT_CPUTAG_INSERTMOD_MASK) >> RTL8373_CPU_TAG_CTRL_INT_CPUTAG_INSERTMOD_OFFSET); + } + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_cpu_awarePort_set + * Description: + * Set CPU aware port mask. + * Input: + * portmask - Port mask. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Invalid port mask. + * Note: + * The API can set configured CPU aware port mask. + */ +rtk_api_ret_t dal_rtl8373_cpuTag_awarePort_set(rtk_portmask_t *pPortmask) +{ + rtk_api_ret_t retVal = 0; + rtk_uint32 phyMbrPmask = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Valid port mask */ + if(NULL == pPortmask) + return RT_ERR_NULL_POINTER; + + /* Check port mask valid */ + RTK_CHK_PORTMASK_VALID(pPortmask); + + if(rtk_switch_portmask_L2P_get(pPortmask, &phyMbrPmask) != RT_ERR_OK) + return RT_ERR_FAILED; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_CPU_TAG_AWARE_CTRL_ADDR, RTL8373_CPU_TAG_AWARE_CTRL_PMSK_MASK, phyMbrPmask)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_cpu_awarePort_get + * Description: + * Get CPU aware port mask. + * Input: + * None + * Output: + * pPortmask - Port mask. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can get configured CPU aware port mask. + */ +rtk_api_ret_t dal_rtl8373_cpuTag_awarePort_get(rtk_portmask_t *pPortmask) +{ + rtk_api_ret_t retVal = 0; + rtk_uint32 pmsk = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pPortmask) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8373_getAsicRegBits(RTL8373_CPU_TAG_AWARE_CTRL_ADDR, RTL8373_CPU_TAG_AWARE_CTRL_PMSK_MASK, &pmsk)) != RT_ERR_OK) + return retVal; + + if(rtk_switch_portmask_P2L_get(pmsk, pPortmask) != RT_ERR_OK) + return RT_ERR_FAILED; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_cpu_priRemap_set + * Description: + * Configure CPU priorities mapping to internal absolute priority For internal CPU. + * Input: + * type - identify internal cpu or external cpu + * intPri - internal priority value. + * newPri - new internal priority value. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_VLAN_PRIORITY - Invalid 1p priority. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * Priority of CPU tag assignment for internal asic priority, and it is used for queue usage and packet scheduling. + */ +rtk_api_ret_t dal_rtl8373_cpuTag_priRemap_set(rtk_cpu_type_t type, rtk_pri_t intPri, rtk_pri_t newPri) +{ + rtk_api_ret_t retVal = 0; + rtk_uint32 regAddr = 0, bitsMask = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if ((newPri > RTL8373_PRIMAX) || (intPri > RTL8373_PRIMAX)) + return RT_ERR_VLAN_PRIORITY; + if(type >= CPU_TYPE_END) + return RT_ERR_INPUT; + + if(type == INTERNAL_CPU) + regAddr = RTL8373_INCPU_PRI_REMAP_ADDR; + else + regAddr = RTL8373_EXCPU_PRI_REMAP_ADDR; + + bitsMask = RTL8373_INCPU_PRI_REMAP_INTPRI0_TO_VAL_MASK << (intPri << 2); + + if ((retVal = rtl8373_setAsicRegBits(regAddr, bitsMask, newPri)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_cpu_priRemap_get + * Description: + * Configure CPU priorities mapping to internal absolute priority. + * Input: + * type - identify internal cpu or external cpu + * intPri - internal priority value. + * Output: + * pNewPri - new internal priority value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_VLAN_PRIORITY - Invalid 1p priority. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * Priority of CPU tag assignment for internal asic priority, and it is used for queue usage and packet scheduling. + */ +rtk_api_ret_t dal_rtl8373_cpuTag_priRemap_get(rtk_cpu_type_t type, rtk_pri_t intPri, rtk_pri_t *pNewPri) +{ + rtk_api_ret_t retVal = 0; + rtk_uint32 regAddr = 0, bitsMask = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pNewPri) + return RT_ERR_NULL_POINTER; + + if(intPri > RTL8373_PRIMAX) + return RT_ERR_QOS_INT_PRIORITY; + + if(type >= CPU_TYPE_END) + return RT_ERR_INPUT; + + if(type == INTERNAL_CPU) + regAddr = RTL8373_INCPU_PRI_REMAP_ADDR; + else + regAddr = RTL8373_EXCPU_PRI_REMAP_ADDR; + + bitsMask = RTL8373_INCPU_PRI_REMAP_INTPRI0_TO_VAL_MASK << (intPri << 2); + + if ((retVal = rtl8373_getAsicRegBits(regAddr, bitsMask, pNewPri)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_cpuTag.h b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_cpuTag.h new file mode 100755 index 00000000..bb621cd6 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_cpuTag.h @@ -0,0 +1,254 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8373 switch high-level API + * + * Feature : The file includes CPU module high-layer API defination + * + */ + +#ifndef __DAL_RTL8373_CPU_H__ +#define __DAL_RTL8373_CPU_H__ + +#include + +/* Function Name: + * dal_rtl8373_cpuTag_externalCpuPort_set + * Description: + * Set external cpu port + * Input: + * extCpuPort - port number + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * API can set destination port of trapping frame + */ +extern rtk_api_ret_t dal_rtl8373_cpuTag_externalCpuPort_set(rtk_uint32 extCpuPort); + +/* Function Name: + * dal_rtl8373_cpuTag_externalCpuPort_get + * Description: + * Get external cpu port + * Input: + * None + * Output: + * pExtCpuPort - port number + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +extern rtk_api_ret_t dal_rtl8373_cpuTag_externalCpuPort_get(rtk_uint32 *pExtCpuPort); + +/* Function Name: + * dal_rtl8373_cpuTag_tpid_set + * Description: + * Set cpu tag protocol id + * Input: + * tpid - protocol ID + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +extern rtk_api_ret_t dal_rtl8373_cpuTag_tpid_set(rtk_uint32 tpid); + +/* Function Name: + * dal_rtl8373_cpuTag_tpid_get + * Description: + * Get cpu tag protocol id + * Input: + * None + * Output: + * pTpid - protocol ID + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +extern rtk_api_ret_t dal_rtl8373_cpuTag_tpid_get(rtk_uint32 *pTpid); + +/* Function Name: + * dal_rtl8373_cpuTag_enable_set + * Description: + * Set CPU port function enable/disable. + * Input: + * type - CPU type: internal cpu or external cpu + * status - CPU port function enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can set CPU port function enable/disable. + */ +extern rtk_api_ret_t dal_rtl8373_cpuTag_enable_set(rtk_cpu_type_t type, rtk_enable_t status); + +/* Function Name: + * dal_rtl8373_cpuTag_enable_get + * Description: + * Get CPU port and its setting. + * Input: + * type - CPU type: internal cpu or external cpu + * Output: + * pStatus - CPU port function enable + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_L2_NO_CPU_PORT - CPU port is not exist + * Note: + * The API can get CPU port function enable/disable. + */ +extern rtk_api_ret_t dal_rtl8373_cpuTag_enable_get(rtk_cpu_type_t type, rtk_enable_t *pStatus); + +/* Function Name: + * dal_rtl8373_cpuTag_insertMode_set + * Description: + * Set internal & external CPU port tag insert mode. + * Input: + * type - CPU type: internal cpu or external cpu + * mode - CPU tag insert for packets egress from CPU port. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can set CPU inserting proprietary CPU tag mode (Length/Type 0x8899) + * to the frame that transmitting to CPU port. + * The inset cpu tag mode is as following: + * - CPU_INSERT_TO_ALL + * - CPU_INSERT_TO_TRAPPING + * - CPU_INSERT_TO_NONE + */ +extern rtk_api_ret_t dal_rtl8373_cpuTag_insertMode_set(rtk_cpu_type_t type, rtk_cpuTag_insertMode_t mode); + +/* Function Name: + * dal_rtl8373_cpuTag_insertMode_get + * Description: + * Get internal & external CPU port tag insert mode. + * Input: + * type - CPU type: internal cpu or external cpu + * Output: + * pMode - CPU tag insert for packets egress from CPU port, 0:all insert 1:Only for trapped packets 2:no insert. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_L2_NO_CPU_PORT - CPU port is not exist + * Note: + * The API can get configured CPU insert mode. + * The inset cpu tag mode is as following: + * - CPU_INSERT_TO_ALL + * - CPU_INSERT_TO_TRAPPING + * - CPU_INSERT_TO_NONE + */ +extern rtk_api_ret_t dal_rtl8373_cpuTag_insertMode_get(rtk_cpu_type_t type, rtk_cpuTag_insertMode_t *pMode); + +/* Function Name: + * dal_rtl8373_cpu_awarePort_set + * Description: + * Set CPU aware port mask. + * Input: + * portmask - Port mask. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Invalid port mask. + * Note: + * The API can set configured CPU aware port mask. + */ +extern rtk_api_ret_t dal_rtl8373_cpuTag_awarePort_set(rtk_portmask_t *pPortmask); + +/* Function Name: + * dal_rtl8373_cpu_awarePort_get + * Description: + * Get CPU aware port mask. + * Input: + * None + * Output: + * pPortmask - Port mask. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can get configured CPU aware port mask. + */ +extern rtk_api_ret_t dal_rtl8373_cpuTag_awarePort_get(rtk_portmask_t *pPortmask); + +/* Function Name: + * dal_rtl8373_cpu_priRemap_set + * Description: + * Configure CPU priorities mapping to internal absolute priority For internal CPU. + * Input: + * type - identify internal cpu or external cpu + * intPri - internal priority value. + * newPri - new internal priority value. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_VLAN_PRIORITY - Invalid 1p priority. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * Priority of CPU tag assignment for internal asic priority, and it is used for queue usage and packet scheduling. + */ +extern rtk_api_ret_t dal_rtl8373_cpuTag_priRemap_set(rtk_cpu_type_t type, rtk_pri_t intPri, rtk_pri_t newPri); + +/* Function Name: + * dal_rtl8373_cpu_priRemap_get + * Description: + * Configure CPU priorities mapping to internal absolute priority. + * Input: + * type - identify internal cpu or external cpu + * intPri - internal priority value. + * Output: + * pNewPri - new internal priority value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_VLAN_PRIORITY - Invalid 1p priority. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * Priority of CPU tag assignment for internal asic priority, and it is used for queue usage and packet scheduling. + */ +extern rtk_api_ret_t dal_rtl8373_cpuTag_priRemap_get(rtk_cpu_type_t type, rtk_pri_t intPri, rtk_pri_t *pNewPri); + + +#endif /* __DAL_RTL8373_CPU_H__ */ diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_dos.c b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_dos.c new file mode 100755 index 00000000..2d3d399a --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_dos.c @@ -0,0 +1,88 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8373 + * Feature : Here is a list of all functions and variables in RMA module. + * + */ + +#include +#include +#include +#include +#include + + +/* Function Name: + * rtl8373_setAsicDos + * Description: + * Set asic dos configuration + * Input: + * index - dos type + * enable - 1:enable, 0:disable + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t dal_rtl8373_asicDos_set(rtk_port_autoDosType_t index, rtk_uint32 enable) +{ + ret_t retVal; + + + retVal = rtl8373_setAsicRegBit(RTL8373_ATK_PRVNT_CTRL_ADDR, index, enable); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * rtl8373_getAsicDos + * Description: + * Get asic dos configuration + * Input: + * index - dos type + * pEnable - 1:enable, 0:disable + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t dal_rtl8373_asicDos_get(rtk_port_autoDosType_t index, rtk_uint32* pEnable) +{ + ret_t retVal; + + retVal = rtl8373_getAsicRegBit(RTL8373_ATK_PRVNT_CTRL_ADDR, index, pEnable); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + + + + + + + + diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_dos.h b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_dos.h new file mode 100755 index 00000000..ac2d3aef --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_dos.h @@ -0,0 +1,44 @@ +#ifndef __DAL_RTL8373_DOS_H__ +#define __DAL_RTL8373_DOS_H__ + +#include "dos.h" + + +/* Function Name: + * rtl8373_setAsicDos + * Description: + * Set asic dos configuration + * Input: + * index - dos type + * enable - 1:enable, 0:disable + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t dal_rtl8373_asicDos_set(rtk_port_autoDosType_t index, rtk_uint32 enable); + + + +/* Function Name: + * rtl8373_getAsicDos + * Description: + * Get asic dos configuration + * Input: + * index - dos type + * pEnable - 1:enable, 0:disable + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t dal_rtl8373_asicDos_get(rtk_port_autoDosType_t index, rtk_uint32* pEnable); + +#endif + diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_dot1x.c b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_dot1x.c new file mode 100755 index 00000000..22aad02a --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_dot1x.c @@ -0,0 +1,980 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8373 + * Feature : Here is a list of all functions and variables in 1X module. + * + */ + +#include +#include +#include +#include +#include +#include +#include +//#include +//#include +//#include + + +/* Function Name: + * dal_rtl8373_dot1x_unauthPacketOper_set + * Description: + * Set 802.1x unauth action configuration. + * Input: + * port - Port id. + * unauth_action - 802.1X unauth action. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameter. + * Note: + * This API can set 802.1x unauth action configuration. + * The unauth action is as following: + * - DOT1X_ACTION_DROP + * - DOT1X_ACTION_TRAP2CPU + * - DOT1X_ACTION_GUESTVLAN + */ +rtk_api_ret_t dal_rtl8373_dot1x_unauthPacketOper_set(rtk_port_t port, rtk_dot1x_unauth_action_t unauth_action) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check port Valid */ + RTK_CHK_PORT_VALID(port); + + if (unauth_action >= DOT1X_ACTION_END) + return RT_ERR_DOT1X_PROC; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_DOT1X_UNAUTH_ACT_ADDR(port), RTL8373_DOT1X_UNAUTH_ACT_PORT_ACT_MASK(port), unauth_action)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_dot1x_unauthPacketOper_get + * Description: + * Get 802.1x unauth action configuration. + * Input: + * port - Port id. + * Output: + * pUnauth_action - 802.1X unauth action. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can get 802.1x unauth action configuration. + * The unauth action is as following: + * - DOT1X_ACTION_DROP + * - DOT1X_ACTION_TRAP2CPU + * - DOT1X_ACTION_GUESTVLAN + */ +rtk_api_ret_t dal_rtl8373_dot1x_unauthPacketOper_get(rtk_port_t port, rtk_dot1x_unauth_action_t *pUnauth_action) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check port Valid */ + RTK_CHK_PORT_VALID(port); + + if(NULL == pUnauth_action) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8373_getAsicRegBits(RTL8373_DOT1X_UNAUTH_ACT_ADDR(port), RTL8373_DOT1X_UNAUTH_ACT_PORT_ACT_MASK(port), pUnauth_action)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_dot1x_trap2CPU_Sel_set + * Description: + * Select cpu config which unauth packet trap. + * Input: + * cpu_sel - select cpu value. + * Output: + * NULL + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can set cpu config which unauth packet trap. + */ +rtk_api_ret_t dal_rtl8373_dot1x_trap2CPU_Sel_set(rtk_dot1x_cpu_select_t cpu_sel) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(cpu_sel >= DOT1X_CPU_SEL_END) + return RT_ERR_INPUT; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_DOT1X_TRAP_CPU_SEL_ADDR, RTL8373_DOT1X_TRAP_CPU_SEL_TRAP_CPU_SEL_MASK, cpu_sel)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_dot1x_trap2CPU_Sel_get + * Description: + * Get cpu config which unauth packet trap. + * Input: + * NULL + * Output: + * pCpu_sel - 802.1X trap cpu select value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can get cpu config which unauth packet trap. + */ +rtk_api_ret_t dal_rtl8373_dot1x_trap2CPU_Sel_get(rtk_dot1x_cpu_select_t *pCpu_sel) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pCpu_sel) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8373_getAsicRegBits(RTL8373_DOT1X_TRAP_CPU_SEL_ADDR, RTL8373_DOT1X_TRAP_CPU_SEL_TRAP_CPU_SEL_MASK, pCpu_sel)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_dot1x_trap_priority_set + * Description: + * Set trap priority for unauth packet. + * Input: + * pri_value - priority value. + * Output: + * NULL + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can set trap priority for unauth packet. + */ +rtk_api_ret_t dal_rtl8373_dot1x_trap_priority_set(rtk_pri_t pri_value) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(pri_value > 7) + return RT_ERR_INPUT; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_DOT1X_TRAP_PRIORITY_ADDR, RTL8373_DOT1X_TRAP_PRIORITY_TRAP_PRI_MASK, pri_value)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_dot1x_trap_priority_get + * Description: + * Get trap priority for unauth packet. + * Input: + * pri_value - priority value. + * Output: + * NULL + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can get trap priority for unauth packet. + */ +rtk_api_ret_t dal_rtl8373_dot1x_trap_priority_get(rtk_pri_t *pri_value) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pri_value) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8373_getAsicRegBits(RTL8373_DOT1X_TRAP_PRIORITY_ADDR, RTL8373_DOT1X_TRAP_PRIORITY_TRAP_PRI_MASK, pri_value)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +#if 0 +/* Function Name: + * dal_rtl8373_dot1x_eapolFrame2CpuEnable_set + * Description: + * Set 802.1x EAPOL packet trap to CPU configuration + * Input: + * enable - The status of 802.1x EAPOL packet. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * To support 802.1x authentication functionality, EAPOL frame (ether type = 0x888E) has to + * be trapped to CPU. + * The status of EAPOL frame trap to CPU is as following: + * - DISABLED + * - ENABLED + */ +rtk_api_ret_t dal_rtl8373_dot1x_eapolFrame2CpuEnable_set(rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + rtk_uint32 action; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (enable >= RTK_ENABLE_END) + return RT_ERR_ENABLE; + + if ((retVal = rtl8373_getAsicRegBits(RTL8373_REG_RMA_CTRL03,RTL8367D_RMA_CTRL03_OPERATION_MASK, &action)) != RT_ERR_OK) + return retVal; + + if (ENABLED == enable) + action = RMA_ACTION_TRAP2CPU; + else if (DISABLED == enable) + { + if (RMA_ACTION_TRAP2CPU == action) + action = RMA_ACTION_FORWARD; + } + + if ((retVal = rtl8367d_setAsicRegBits(RTL8367D_REG_RMA_CTRL03,RTL8367D_RMA_CTRL03_OPERATION_MASK, action)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_dot1x_eapolFrame2CpuEnable_get + * Description: + * Get 802.1x EAPOL packet trap to CPU configuration + * Input: + * None + * Output: + * pEnable - The status of 802.1x EAPOL packet. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * To support 802.1x authentication functionality, EAPOL frame (ether type = 0x888E) has to + * be trapped to CPU. + * The status of EAPOL frame trap to CPU is as following: + * - DISABLED + * - ENABLED + */ +rtk_api_ret_t dal_rtl8373_dot1x_eapolFrame2CpuEnable_get(rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + rtl8373_rma_t rmacfg; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pEnable) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8373_getAsicRma(3, &rmacfg)) != RT_ERR_OK) + return retVal; + + if (RMAOP_TRAP_TO_CPU == rmacfg.operation) + *pEnable = ENABLED; + else + *pEnable = DISABLED; + + return RT_ERR_OK; +} +#endif +/* Function Name: + * dal_rtl8373_dot1x_portBasedEnable_set + * Description: + * Set 802.1x port-based enable configuration + * Input: + * port - Port id. + * enable - The status of 802.1x port. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * RT_ERR_DOT1X_PORTBASEDPNEN - 802.1X port-based enable error + * Note: + * The API can update the port-based port enable register content. If a port is 802.1x + * port based network access control "enabled", it should be authenticated so packets + * from that port won't be dropped or trapped to CPU. + * The status of 802.1x port-based network access control is as following: + * - DISABLED + * - ENABLED + */ +rtk_api_ret_t dal_rtl8373_dot1x_portBasedEnable_set(rtk_port_t port, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check port Valid */ + RTK_CHK_PORT_VALID(port); + + if (enable >= RTK_ENABLE_END) + return RT_ERR_ENABLE; + + if ((retVal = rtl8373_setAsicRegBit(RTL8373_DOT1X_PORT_EN_ADDR(port), RTL8373_DOT1X_PORT_EN_PORT_EN_OFFSET(port), enable)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_dot1x_portBasedEnable_get + * Description: + * Get 802.1x port-based enable configuration + * Input: + * port - Port id. + * Output: + * pEnable - The status of 802.1x port. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get the 802.1x port-based port status. + */ +rtk_api_ret_t dal_rtl8373_dot1x_portBasedEnable_get(rtk_port_t port, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check port Valid */ + RTK_CHK_PORT_VALID(port); + + if(NULL == pEnable) + return RT_ERR_NULL_POINTER; +printf("555. %d\n", port); + if ((retVal = rtl8373_getAsicRegBit(RTL8373_DOT1X_PORT_EN_ADDR(port), RTL8373_DOT1X_PORT_EN_PORT_EN_OFFSET(port), pEnable)) != RT_ERR_OK) + return retVal; +printf("666\n"); + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_dot1x_portBasedAuthStatus_set + * Description: + * Set 802.1x port-based auth. port configuration + * Input: + * port - Port id. + * port_auth - The status of 802.1x port. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_DOT1X_PORTBASEDAUTH - 802.1X port-based auth error + * Note: + * The authenticated status of 802.1x port-based network access control is as following: + * - UNAUTH + * - AUTH + */ +rtk_api_ret_t dal_rtl8373_dot1x_portBasedAuthStatus_set(rtk_port_t port, rtk_dot1x_auth_status_t port_auth) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check port Valid */ + RTK_CHK_PORT_VALID(port); + + if (port_auth >= AUTH_STATUS_END) + return RT_ERR_DOT1X_PORTBASEDAUTH; + + if ((retVal = rtl8373_setAsicRegBit(RTL8373_DOT1X_PORT_AUTH_ADDR(port), RTL8373_DOT1X_PORT_AUTH_PORT_AUTH_OFFSET(port), port_auth)) != RT_ERR_OK) + return retVal; + + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_dot1x_portBasedAuthStatus_get + * Description: + * Get 802.1x port-based auth. port configuration + * Input: + * port - Port id. + * Output: + * pPort_auth - The status of 802.1x port. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get 802.1x port-based port auth.information. + */ +rtk_api_ret_t dal_rtl8373_dot1x_portBasedAuthStatus_get(rtk_port_t port, rtk_dot1x_auth_status_t *pPort_auth) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pPort_auth) + return RT_ERR_NULL_POINTER; + + /* Check port Valid */ + RTK_CHK_PORT_VALID(port); + + if ((retVal = rtl8373_getAsicRegBit(RTL8373_DOT1X_PORT_AUTH_ADDR(port), RTL8373_DOT1X_PORT_AUTH_PORT_AUTH_OFFSET(port), pPort_auth)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_dot1x_portBasedDirection_set + * Description: + * Set 802.1x port-based operational direction configuration + * Input: + * port - Port id. + * port_direction - Operation direction + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_DOT1X_PORTBASEDOPDIR - 802.1X port-based operation direction error + * Note: + * The operate controlled direction of 802.1x port-based network access control is as following: + * - BOTH + * - IN + */ +rtk_api_ret_t dal_rtl8373_dot1x_portBasedDirection_set(rtk_port_t port, rtk_dot1x_direction_t port_direction) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check port Valid */ + RTK_CHK_PORT_VALID(port); + + if (port_direction >= DIRECTION_END) + return RT_ERR_DOT1X_PORTBASEDOPDIR; + + if ((retVal = rtl8373_setAsicRegBit(RTL8373_DOT1X_PORT_DIR_ADDR(port), RTL8373_DOT1X_PORT_DIR_PORT_DIR_OFFSET(port), port_direction)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_dot1x_portBasedDirection_get + * Description: + * Get 802.1X port-based operational direction configuration + * Input: + * port - Port id. + * Output: + * pPort_direction - Operation direction + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get 802.1x port-based operational direction information. + */ +rtk_api_ret_t dal_rtl8373_dot1x_portBasedDirection_get(rtk_port_t port, rtk_dot1x_direction_t *pPort_direction) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pPort_direction) + return RT_ERR_NULL_POINTER; + + /* Check port Valid */ + RTK_CHK_PORT_VALID(port); + + if ((retVal = rtl8373_getAsicRegBit(RTL8373_DOT1X_PORT_DIR_ADDR(port), RTL8373_DOT1X_PORT_DIR_PORT_DIR_OFFSET(port), pPort_direction)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_dot1x_macBasedEnable_set + * Description: + * Set 802.1x mac-based port enable configuration + * Input: + * port - Port id. + * enable - The status of 802.1x port. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * RT_ERR_DOT1X_MACBASEDPNEN - 802.1X mac-based enable error + * Note: + * If a port is 802.1x MAC based network access control "enabled", the incoming packets should + * be authenticated so packets from that port won't be dropped or trapped to CPU. + * The status of 802.1x MAC-based network access control is as following: + * - DISABLED + * - ENABLED + */ +rtk_api_ret_t dal_rtl8373_dot1x_macBasedEnable_set(rtk_port_t port, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check port Valid */ + RTK_CHK_PORT_VALID(port); + + if (enable >= RTK_ENABLE_END) + return RT_ERR_ENABLE; + + if ((retVal = rtl8373_setAsicRegBit(RTL8373_DOT1X_MAC_EN_ADDR(port), RTL8373_DOT1X_MAC_EN_MAC_EN_OFFSET(port), enable)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_dot1x_macBasedEnable_get + * Description: + * Get 802.1x mac-based port enable configuration + * Input: + * port - Port id. + * Output: + * pEnable - The status of 802.1x port. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * If a port is 802.1x MAC based network access control "enabled", the incoming packets should + * be authenticated so packets from that port wont be dropped or trapped to CPU. + * The status of 802.1x MAC-based network access control is as following: + * - DISABLED + * - ENABLED + */ +rtk_api_ret_t dal_rtl8373_dot1x_macBasedEnable_get(rtk_port_t port, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pEnable) + return RT_ERR_NULL_POINTER; + + /* Check port Valid */ + RTK_CHK_PORT_VALID(port); + + if ((retVal = rtl8373_getAsicRegBit(RTL8373_DOT1X_MAC_EN_ADDR(port), RTL8373_DOT1X_MAC_EN_MAC_EN_OFFSET(port), pEnable)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_dot1x_macBasedAuthMac_add + * Description: + * Add an authenticated MAC to ASIC + * Input: + * port - Port id. + * pAuth_mac - The authenticated MAC. + * fid - filtering database. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * RT_ERR_DOT1X_MACBASEDPNEN - 802.1X mac-based enable error + * Note: + * The API can add a 802.1x authenticated MAC address to port. If the MAC does not exist in LUT, + * user can't add this MAC to auth status. + */ +rtk_api_ret_t dal_rtl8373_dot1x_macBasedAuthMac_add(rtk_port_t port, rtk_mac_t *pAuth_mac, rtk_fid_t fid) +{ + rtk_api_ret_t retVal; + rtk_l2_ucastAddr_t l2Table; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* must be unicast address */ + if ((pAuth_mac == NULL) || (pAuth_mac->octet[0] & 0x1)) + return RT_ERR_MAC; + + /* Check port Valid */ + RTK_CHK_PORT_VALID(port); + + if (fid > RTL8373_FIDMAX) + return RT_ERR_L2_FID; + + memset(&l2Table, 0, sizeof(rtk_l2_ucastAddr_t)); + + /* fill key (MAC,FID) to get L2 entry */ + memcpy(l2Table.mac.octet, pAuth_mac->octet, ETHER_ADDR_LEN); + l2Table.ivl = 0; + l2Table.vid_fid = fid; + retVal = dal_rtl8373_l2_addr_get(pAuth_mac, &l2Table); + if ( RT_ERR_OK == retVal) + { + if (l2Table.port != rtk_switch_port_L2P_get(port)) + return RT_ERR_DOT1X_MAC_PORT_MISMATCH; + + memcpy(l2Table.mac.octet, pAuth_mac->octet, ETHER_ADDR_LEN); + l2Table.ivl = 0; + l2Table.vid_fid = fid; + l2Table.auth = 1; + retVal = dal_rtl8373_l2_addr_add(pAuth_mac, &l2Table); + return retVal; + } + else + return retVal; + +} + +/* Function Name: + * dal_rtl8373_dot1x_macBasedAuthMac_del + * Description: + * Delete an authenticated MAC to ASIC + * Input: + * port - Port id. + * pAuth_mac - The authenticated MAC. + * fid - filtering database. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can delete a 802.1x authenticated MAC address to port. It only change the auth status of + * the MAC and won't delete it from LUT. + */ +rtk_api_ret_t dal_rtl8373_dot1x_macBasedAuthMac_del(rtk_port_t port, rtk_mac_t *pAuth_mac, rtk_fid_t fid) +{ + rtk_api_ret_t retVal; + rtk_l2_ucastAddr_t l2Table; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* must be unicast address */ + if ((pAuth_mac == NULL) || (pAuth_mac->octet[0] & 0x1)) + return RT_ERR_MAC; + + /* Check port Valid */ + RTK_CHK_PORT_VALID(port); + + if (fid > RTL8373_FIDMAX) + return RT_ERR_L2_FID; + + memset(&l2Table, 0, sizeof(rtk_l2_ucastAddr_t)); + + /* fill key (MAC,FID) to get L2 entry */ + memcpy(l2Table.mac.octet, pAuth_mac->octet, ETHER_ADDR_LEN); + l2Table.ivl = 0; + l2Table.vid_fid = fid; + retVal = dal_rtl8373_l2_addr_get(pAuth_mac, &l2Table); + if (RT_ERR_OK == retVal) + { + if (l2Table.port != rtk_switch_port_L2P_get(port)) + return RT_ERR_DOT1X_MAC_PORT_MISMATCH; + + memcpy(l2Table.mac.octet, pAuth_mac->octet, ETHER_ADDR_LEN); + l2Table.ivl = 0; + l2Table.vid_fid = fid; + l2Table.auth = 0; + retVal = dal_rtl8373_l2_addr_add(pAuth_mac, &l2Table); + return retVal; + } + else + return retVal; + +} + +/* Function Name: + * dal_rtl8373_dot1x_macBasedDirection_set + * Description: + * Set 802.1x mac-based operational direction configuration + * Input: + * mac_direction - Operation direction + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_DOT1X_MACBASEDOPDIR - 802.1X mac-based operation direction error + * Note: + * The operate controlled direction of 802.1x mac-based network access control is as following: + * - BOTH + * - IN + */ +rtk_api_ret_t dal_rtl8373_dot1x_macBasedDirection_set(rtk_dot1x_direction_t mac_direction) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (mac_direction >= DIRECTION_END) + return RT_ERR_DOT1X_MACBASEDOPDIR; + + if ((retVal = rtl8373_setAsicRegBit(RTL8373_DOT1X_CFG_ADDR, RTL8373_DOT1X_CFG_MAC_DIR_OFFSET, mac_direction)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_dot1x_macBasedDirection_get + * Description: + * Get 802.1x mac-based operational direction configuration + * Input: + * port - Port id. + * Output: + * pMac_direction - Operation direction + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get 802.1x mac-based operational direction information. + */ +rtk_api_ret_t dal_rtl8373_dot1x_macBasedDirection_get(rtk_dot1x_direction_t *pMac_direction) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pMac_direction) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8373_getAsicRegBit(RTL8373_DOT1X_CFG_ADDR, RTL8373_DOT1X_CFG_MAC_DIR_OFFSET, pMac_direction)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * Set 802.1x guest VLAN configuration + * Description: + * Set 802.1x mac-based operational direction configuration + * Input: + * vid - 802.1x guest VLAN ID + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * Note: + * The operate controlled 802.1x guest VLAN + */ +rtk_api_ret_t dal_rtl8373_dot1x_guestVlan_set(rtk_vlan_t vid) +{ + rtk_api_ret_t retVal; + rtk_vlan_entry_t vlancfg; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* vid must be 0~4095 */ + if (vid > RTL8373_VIDMAX) + return RT_ERR_VLAN_VID; + + if((retVal = dal_rtl8373_vlan_get(vid, &vlancfg)) != RT_ERR_OK) + return retVal; + + //No member in vid entry + if (vlancfg.mbr.bits[0] == 0) + return RT_ERR_DOT1X_GVLANIDX; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_DOT1X_CFG_ADDR, RTL8373_DOT1X_CFG_GUEST_VID_MASK, vid)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_dot1x_guestVlan_get + * Description: + * Get 802.1x guest VLAN configuration + * Input: + * None + * Output: + * pVid - 802.1x guest VLAN ID + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get 802.1x guest VLAN information. + */ +rtk_api_ret_t dal_rtl8373_dot1x_guestVlan_get(rtk_vlan_t *pVid) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pVid) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8373_getAsicRegBits(RTL8373_DOT1X_CFG_ADDR, RTL8373_DOT1X_CFG_GUEST_VID_MASK, pVid)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_dot1x_guestVlan2Auth_set + * Description: + * Set 802.1x guest VLAN to auth host configuration + * Input: + * enable - The status of guest VLAN to auth host. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * Note: + * The operational direction of 802.1x guest VLAN to auth host control is as following: + * - ENABLED + * - DISABLED + */ +rtk_api_ret_t dal_rtl8373_dot1x_guestVlan2Auth_set(rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (enable >= RTK_ENABLE_END) + return RT_ERR_ENABLE; + + if ((retVal = rtl8373_setAsicRegBit(RTL8373_DOT1X_CFG_ADDR, RTL8373_DOT1X_CFG_GUSET_OP_OFFSET, enable)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_dot1x_guestVlan2Auth_get + * Description: + * Get 802.1x guest VLAN to auth host configuration + * Input: + * None + * Output: + * pEnable - The status of guest VLAN to auth host. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get 802.1x guest VLAN to auth host information. + */ +rtk_api_ret_t dal_rtl8373_dot1x_guestVlan2Auth_get(rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pEnable) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8373_getAsicRegBit(RTL8373_DOT1X_CFG_ADDR, RTL8373_DOT1X_CFG_GUSET_OP_OFFSET, pEnable)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_dot1x.h b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_dot1x.h new file mode 100755 index 00000000..c74b3862 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_dot1x.h @@ -0,0 +1,482 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8367/RTL8367C switch high-level API + * + * Feature : The file includes 1X module high-layer API defination + * + */ + +#ifndef __DAL_RTL8373_DOT1X_H__ +#define __DAL_RTL8373_DOT1X_H__ + +#include + +/* Function Name: + * dal_rtl8373_dot1x_unauthPacketOper_set + * Description: + * Set 802.1x unauth action configuration. + * Input: + * port - Port id. + * unauth_action - 802.1X unauth action. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameter. + * Note: + * This API can set 802.1x unauth action configuration. + * The unauth action is as following: + * - DOT1X_ACTION_DROP + * - DOT1X_ACTION_TRAP2CPU + * - DOT1X_ACTION_GUESTVLAN + */ +extern rtk_api_ret_t dal_rtl8373_dot1x_unauthPacketOper_set(rtk_port_t port, rtk_dot1x_unauth_action_t unauth_action); + +/* Function Name: + * dal_rtl8373_dot1x_unauthPacketOper_get + * Description: + * Get 802.1x unauth action configuration. + * Input: + * port - Port id. + * Output: + * pUnauth_action - 802.1X unauth action. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can get 802.1x unauth action configuration. + * The unauth action is as following: + * - DOT1X_ACTION_DROP + * - DOT1X_ACTION_TRAP2CPU + * - DOT1X_ACTION_GUESTVLAN + */ +extern rtk_api_ret_t dal_rtl8373_dot1x_unauthPacketOper_get(rtk_port_t port, rtk_dot1x_unauth_action_t *pUnauth_action); + +/* Function Name: + * dal_rtl8373_dot1x_trap2CPU_Sel_set + * Description: + * Select cpu config which unauth packet trap. + * Input: + * cpu_sel - select cpu value. + * Output: + * NULL + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can set cpu config which unauth packet trap. + */ +extern rtk_api_ret_t dal_rtl8373_dot1x_trap2CPU_Sel_set(rtk_dot1x_cpu_select_t cpu_sel); + +/* Function Name: + * dal_rtl8373_dot1x_trap2CPU_Sel_get + * Description: + * Get cpu config which unauth packet trap. + * Input: + * NULL + * Output: + * pCpu_sel - 802.1X trap cpu select value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can get cpu config which unauth packet trap. + */ +extern rtk_api_ret_t dal_rtl8373_dot1x_trap2CPU_Sel_get(rtk_dot1x_cpu_select_t *pCpu_sel); + +/* Function Name: + * dal_rtl8373_dot1x_trap_priority_set + * Description: + * Set trap priority for unauth packet. + * Input: + * pri_value - priority value. + * Output: + * NULL + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can set trap priority for unauth packet. + */ +extern rtk_api_ret_t dal_rtl8373_dot1x_trap_priority_set(rtk_pri_t pri_value); + +/* Function Name: + * dal_rtl8373_dot1x_trap_priority_get + * Description: + * Get trap priority for unauth packet. + * Input: + * pri_value - priority value. + * Output: + * NULL + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can get trap priority for unauth packet. + */ +extern rtk_api_ret_t dal_rtl8373_dot1x_trap_priority_get(rtk_pri_t *pri_value); + +/* Function Name: + * dal_rtl8373_dot1x_portBasedEnable_set + * Description: + * Set 802.1x port-based enable configuration + * Input: + * port - Port id. + * enable - The status of 802.1x port. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * RT_ERR_DOT1X_PORTBASEDPNEN - 802.1X port-based enable error + * Note: + * The API can update the port-based port enable register content. If a port is 802.1x + * port based network access control "enabled", it should be authenticated so packets + * from that port won't be dropped or trapped to CPU. + * The status of 802.1x port-based network access control is as following: + * - DISABLED + * - ENABLED + */ +extern rtk_api_ret_t dal_rtl8373_dot1x_portBasedEnable_set(rtk_port_t port, rtk_enable_t enable); + +/* Function Name: + * dal_rtl8373_dot1x_portBasedEnable_get + * Description: + * Get 802.1x port-based enable configuration + * Input: + * port - Port id. + * Output: + * pEnable - The status of 802.1x port. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get the 802.1x port-based port status. + */ +extern rtk_api_ret_t dal_rtl8373_dot1x_portBasedEnable_get(rtk_port_t port, rtk_enable_t *pEnable); + +/* Function Name: + * dal_rtl8373_dot1x_portBasedAuthStatus_set + * Description: + * Set 802.1x port-based auth. port configuration + * Input: + * port - Port id. + * port_auth - The status of 802.1x port. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_DOT1X_PORTBASEDAUTH - 802.1X port-based auth error + * Note: + * The authenticated status of 802.1x port-based network access control is as following: + * - UNAUTH + * - AUTH + */ +extern rtk_api_ret_t dal_rtl8373_dot1x_portBasedAuthStatus_set(rtk_port_t port, rtk_dot1x_auth_status_t port_auth); + +/* Function Name: + * dal_rtl8373_dot1x_portBasedAuthStatus_get + * Description: + * Get 802.1x port-based auth. port configuration + * Input: + * port - Port id. + * Output: + * pPort_auth - The status of 802.1x port. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get 802.1x port-based port auth.information. + */ +extern rtk_api_ret_t dal_rtl8373_dot1x_portBasedAuthStatus_get(rtk_port_t port, rtk_dot1x_auth_status_t *pPort_auth); + +/* Function Name: + * dal_rtl8373_dot1x_portBasedDirection_set + * Description: + * Set 802.1x port-based operational direction configuration + * Input: + * port - Port id. + * port_direction - Operation direction + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_DOT1X_PORTBASEDOPDIR - 802.1X port-based operation direction error + * Note: + * The operate controlled direction of 802.1x port-based network access control is as following: + * - BOTH + * - IN + */ +extern rtk_api_ret_t dal_rtl8373_dot1x_portBasedDirection_set(rtk_port_t port, rtk_dot1x_direction_t port_direction); + +/* Function Name: + * dal_rtl8373_dot1x_portBasedDirection_get + * Description: + * Get 802.1X port-based operational direction configuration + * Input: + * port - Port id. + * Output: + * pPort_direction - Operation direction + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get 802.1x port-based operational direction information. + */ +extern rtk_api_ret_t dal_rtl8373_dot1x_portBasedDirection_get(rtk_port_t port, rtk_dot1x_direction_t *pPort_direction); + +/* Function Name: + * dal_rtl8373_dot1x_macBasedEnable_set + * Description: + * Set 802.1x mac-based port enable configuration + * Input: + * port - Port id. + * enable - The status of 802.1x port. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * RT_ERR_DOT1X_MACBASEDPNEN - 802.1X mac-based enable error + * Note: + * If a port is 802.1x MAC based network access control "enabled", the incoming packets should + * be authenticated so packets from that port won't be dropped or trapped to CPU. + * The status of 802.1x MAC-based network access control is as following: + * - DISABLED + * - ENABLED + */ +extern rtk_api_ret_t dal_rtl8373_dot1x_macBasedEnable_set(rtk_port_t port, rtk_enable_t enable); + +/* Function Name: + * dal_rtl8373_dot1x_macBasedEnable_get + * Description: + * Get 802.1x mac-based port enable configuration + * Input: + * port - Port id. + * Output: + * pEnable - The status of 802.1x port. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * If a port is 802.1x MAC based network access control "enabled", the incoming packets should + * be authenticated so packets from that port wont be dropped or trapped to CPU. + * The status of 802.1x MAC-based network access control is as following: + * - DISABLED + * - ENABLED + */ +extern rtk_api_ret_t dal_rtl8373_dot1x_macBasedEnable_get(rtk_port_t port, rtk_enable_t *pEnable); + +/* Function Name: + * dal_rtl8373_dot1x_macBasedDirection_set + * Description: + * Set 802.1x mac-based operational direction configuration + * Input: + * mac_direction - Operation direction + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_DOT1X_MACBASEDOPDIR - 802.1X mac-based operation direction error + * Note: + * The operate controlled direction of 802.1x mac-based network access control is as following: + * - BOTH + * - IN + */ +extern rtk_api_ret_t dal_rtl8373_dot1x_macBasedDirection_set(rtk_dot1x_direction_t mac_direction); + +/* Function Name: + * dal_rtl8373_dot1x_macBasedDirection_get + * Description: + * Get 802.1x mac-based operational direction configuration + * Input: + * port - Port id. + * Output: + * pMac_direction - Operation direction + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get 802.1x mac-based operational direction information. + */ +extern rtk_api_ret_t dal_rtl8373_dot1x_macBasedDirection_get(rtk_dot1x_direction_t *pMac_direction); + +/* Function Name: + * dal_rtl8373_dot1x_macBasedAuthMac_add + * Description: + * Add an authenticated MAC to ASIC + * Input: + * port - Port id. + * pAuth_mac - The authenticated MAC. + * fid - filtering database. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * RT_ERR_DOT1X_MACBASEDPNEN - 802.1X mac-based enable error + * Note: + * The API can add a 802.1x authenticated MAC address to port. If the MAC does not exist in LUT, + * user can't add this MAC to auth status. + */ +extern rtk_api_ret_t dal_rtl8373_dot1x_macBasedAuthMac_add(rtk_port_t port, rtk_mac_t *pAuth_mac, rtk_fid_t fid); + +/* Function Name: + * dal_rtl8373_dot1x_macBasedAuthMac_del + * Description: + * Delete an authenticated MAC to ASIC + * Input: + * port - Port id. + * pAuth_mac - The authenticated MAC. + * fid - filtering database. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can delete a 802.1x authenticated MAC address to port. It only change the auth status of + * the MAC and won't delete it from LUT. + */ +rtk_api_ret_t dal_rtl8373_dot1x_macBasedAuthMac_del(rtk_port_t port, rtk_mac_t *pAuth_mac, rtk_fid_t fid); + +/* Function Name: + * Set 802.1x guest VLAN configuration + * Description: + * Set 802.1x mac-based operational direction configuration + * Input: + * vid - 802.1x guest VLAN ID + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * Note: + * The operate controlled 802.1x guest VLAN + */ +extern rtk_api_ret_t dal_rtl8373_dot1x_guestVlan_set(rtk_vlan_t vid); + +/* Function Name: + * dal_rtl8373_dot1x_guestVlan_get + * Description: + * Get 802.1x guest VLAN configuration + * Input: + * None + * Output: + * pVid - 802.1x guest VLAN ID + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get 802.1x guest VLAN information. + */ +extern rtk_api_ret_t dal_rtl8373_dot1x_guestVlan_get(rtk_vlan_t *pVid); + +/* Function Name: + * dal_rtl8373_dot1x_guestVlan2Auth_set + * Description: + * Set 802.1x guest VLAN to auth host configuration + * Input: + * enable - The status of guest VLAN to auth host. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * Note: + * The operational direction of 802.1x guest VLAN to auth host control is as following: + * - ENABLED + * - DISABLED + */ +extern rtk_api_ret_t dal_rtl8373_dot1x_guestVlan2Auth_set(rtk_enable_t enable); + +/* Function Name: + * dal_rtl8373_dot1x_guestVlan2Auth_get + * Description: + * Get 802.1x guest VLAN to auth host configuration + * Input: + * None + * Output: + * pEnable - The status of guest VLAN to auth host. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get 802.1x guest VLAN to auth host information. + */ +rtk_api_ret_t dal_rtl8373_dot1x_guestVlan2Auth_get(rtk_enable_t *pEnable); + + +#endif /* __DAL_RTL8367C_DOT1X_H__ */ + + diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_drv.c b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_drv.c new file mode 100755 index 00000000..37eebb50 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_drv.c @@ -0,0 +1,1313 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8373 + * Feature : Here is a list of all functions and variables in QoS module. + * + */ + +#include +#include +#include +#include +#include +#include +/* Function Name: + * dal_rtl8373_mdc_en + * Description: + * Enbale MDC function. + * Input: + * enable - enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will enbale MDC function. + */ + +rtk_api_ret_t dal_rtl8373_mdc_en(rtk_uint32 enable) +{ + rtk_api_ret_t retVal; + + + if ((retVal = rtl8373_setAsicRegBit(RTL8373_SMI_CTRL_ADDR, RTL8373_SMI_CTRL_SMI0_MDC_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_setAsicRegBit(RTL8373_SMI_CTRL_ADDR, RTL8373_SMI_CTRL_SMI1_MDC_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_setAsicRegBit(RTL8373_SMI_CTRL_ADDR, RTL8373_SMI_CTRL_SMI2_MDC_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_phy_write + * Description: + * Configure phy register data. + * Input: + * phy_mask - phy mask, bit[0:9] + * dev_addr - device address + * reg_addr - register address + * indata - input data + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure phy register data. + */ + +rtk_api_ret_t dal_rtl8373_phy_write(rtk_uint32 phy_mask, rtk_uint32 dev_addr, rtk_uint32 reg_addr, rtk_uint32 indata) +{ + rtk_api_ret_t retVal; + rtk_uint32 tmp; + rtk_uint32 tmp_cmd,tmp_res; + rtk_uint32 pollcnt = 0; + + if ((retVal = rtl8373_setAsicReg(RTL8373_SMI_ACCESS_PHY_CTRL_0_ADDR, phy_mask)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_SMI_ACCESS_PHY_CTRL_3_ADDR, RTL8373_SMI_ACCESS_PHY_CTRL_3_INDATA_15_0_MASK, indata)) != RT_ERR_OK) + return retVal; + + tmp = (dev_addr << 19) | (reg_addr << 3) | 0x7; + + if ((retVal = rtl8373_setAsicReg(RTL8373_SMI_ACCESS_PHY_CTRL_1_ADDR, tmp)) != RT_ERR_OK) + return retVal; + + for(pollcnt = 0; pollcnt < RTL8373_MAX_POLLCNT; pollcnt++) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_SMI_ACCESS_PHY_CTRL_1_ADDR, RTL8373_SMI_ACCESS_PHY_CTRL_1_CMD_OFFSET, &tmp_cmd)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_getAsicRegBits(RTL8373_SMI_ACCESS_PHY_CTRL_1_ADDR, RTL8373_SMI_ACCESS_PHY_CTRL_1_FAIL_MASK, &tmp_res)) != RT_ERR_OK) + return retVal; + + if((tmp_cmd == 0) && (tmp_res == 0)) + break; + } + + if(pollcnt == RTL8373_MAX_POLLCNT) + { + return RT_ERR_BUSYWAIT_TIMEOUT; + } + + return RT_ERR_OK; +} + + + +/* Function Name: + * dal_rtl8373_phy_read + * Description: + * get phy register data. + * Input: + * phy_id - phy id + * dev_addr - device address + * reg_addr - register address + * Output: +* pdata - phy data + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will get phy register data. + */ + +rtk_api_ret_t dal_rtl8373_phy_read(rtk_uint32 phy_id, rtk_uint32 dev_addr, rtk_uint32 reg_addr, rtk_uint32 *pdata) +{ + rtk_api_ret_t retVal; + rtk_uint32 tmp=0; + rtk_uint32 tmp_cmd,tmp_res; + rtk_uint32 pollcnt = 0; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_SMI_ACCESS_PHY_CTRL_3_ADDR, RTL8373_SMI_ACCESS_PHY_CTRL_3_INDATA_15_0_MASK, phy_id)) != RT_ERR_OK) + return retVal; + + tmp = (dev_addr << 19) | (reg_addr << 3) | (0 << 2) | 0x3; + + if ((retVal = rtl8373_setAsicReg(RTL8373_SMI_ACCESS_PHY_CTRL_1_ADDR, tmp)) != RT_ERR_OK) + return retVal; + + for(pollcnt = 0; pollcnt < RTL8373_MAX_POLLCNT; pollcnt++) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_SMI_ACCESS_PHY_CTRL_1_ADDR, RTL8373_SMI_ACCESS_PHY_CTRL_1_CMD_OFFSET, &tmp_cmd)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_getAsicRegBits(RTL8373_SMI_ACCESS_PHY_CTRL_1_ADDR, RTL8373_SMI_ACCESS_PHY_CTRL_1_FAIL_MASK, &tmp_res)) != RT_ERR_OK) + return retVal; + + if((tmp_cmd == 0) && (tmp_res == 0)) + break; + } + + if(pollcnt == RTL8373_MAX_POLLCNT) + { + return RT_ERR_BUSYWAIT_TIMEOUT; + } + + if ((retVal = rtl8373_getAsicRegBits(RTL8373_SMI_ACCESS_PHY_CTRL_2_ADDR, RTL8373_SMI_ACCESS_PHY_CTRL_2_DATA_15_0_MASK, pdata)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_phy_readBits + * Description: + * Configure phy register data. + * Input: + * phy_id - phy id + * dev_addr - device address + * reg_addr - register address + * indata - input data + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure phy register data. + */ + +rtk_api_ret_t dal_rtl8373_phy_readBits(rtk_uint32 phy_id, rtk_uint32 dev_addr, rtk_uint32 reg_addr, rtk_uint32 bitsMask,rtk_uint32 *pdata) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData,regDatal,regDatah; + rtk_uint32 bitsShift; + + if( !bitsMask ) + return RT_ERR_INPUT; + + bitsShift = 0; + while(!(bitsMask & (1 << bitsShift))) + { + bitsShift++; + if(bitsShift >= RTL8373_PHYBITLENGTH) + return RT_ERR_INPUT; + } + + if(dev_addr==RTL8224TOPDEVAD) + { + retVal = dal_rtl8373_phy_read(phy_id,dev_addr, reg_addr,®Datal); + if(retVal != RT_ERR_OK) + return RT_ERR_SMI; + retVal = dal_rtl8373_phy_read(phy_id,dev_addr, reg_addr+1,®Datah); + if(retVal != RT_ERR_OK) + return RT_ERR_SMI; + + regData=regDatal|(regDatah<<16); + } + else + { + retVal = dal_rtl8373_phy_read(phy_id,dev_addr, reg_addr,®Data); + if(retVal != RT_ERR_OK) + return RT_ERR_SMI; + } + *pdata = (regData & bitsMask) >> bitsShift; + return retVal; +} + +/* Function Name: + * rtk_port_phyReg_setBits + * Description: + * Configure phy register data. + * Input: + * phy_mask - phy mask, bit[0:9] + * dev_addr - device address + * reg_addr - register address + * indata - input data + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure phy register data. + */ + +rtk_api_ret_t dal_rtl8373_phy_writeBits(rtk_uint32 phy_mask, rtk_uint32 dev_addr, rtk_uint32 reg_addr, rtk_uint32 bitsMask,rtk_uint32 indata) +{ + rtk_uint32 regDatah,regDatal,regData; + rtk_api_ret_t retVal; + rtk_uint32 bitsShift; + rtk_uint32 valueShifted; + rtk_uint32 phy_id; + + if( !bitsMask ) + return RT_ERR_INPUT; + + bitsShift = 0; + while(!(bitsMask & (1 << bitsShift))) + { + bitsShift++; + if(bitsShift >= RTL8373_REGBITLENGTH) + return RT_ERR_INPUT; + } + valueShifted = indata << bitsShift; + + if(valueShifted > RTL8373_REGDATAMAX) + return RT_ERR_INPUT; + + phy_id =0; + if(dev_addr==RTL8224TOPDEVAD) + { + for(phy_id=0;phy_id>16; + regDatal = regData&0xffff; + retVal = dal_rtl8373_phy_write(1<> 16) & 0xffff; + if ((retVal = dal_rtl8373_phy_write(phymask,30,top_reg_addr,lowdata)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8373_phy_write(phymask,30,top_reg_addr+1,highdata)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8224_top_reg_read + * Description: + * Get RTL8224 top register value. + * Input: + * top_reg_addr - top register address + * pvalue - register value + * Output: +* pdata - None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will get phy register data. + */ + +rtk_api_ret_t dal_rtl8224_top_reg_read(rtk_uint32 top_reg_addr, rtk_uint32* pvalue) +{ + rtk_uint32 phyid; + rtk_uint32 lowdata, highdata; + rtk_api_ret_t retVal; + + phyid=0; + if ((retVal = dal_rtl8373_phy_read(phyid,30,top_reg_addr,&lowdata)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8373_phy_read(phyid,30,top_reg_addr+1,&highdata)) != RT_ERR_OK) + return retVal; + + *pvalue = (lowdata & 0xffff) | ((highdata & 0xffff) << 16); + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8224_top_regbit_write + * Description: + * Set RTL8224 top register bit value. + * Input: + * top_reg_addr - top register address + * offet - bit offset + * value - register bit value + * Output: +* pdata - None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will set phy register data. + */ + +rtk_api_ret_t dal_rtl8224_top_regbit_write(rtk_uint32 top_reg_addr, rtk_uint32 offset, rtk_uint32 value) +{ + rtk_uint32 phyid; + rtk_uint32 phymask; + rtk_uint32 regdata; + rtk_api_ret_t retVal; + + phyid=0; + + if(offset < 16) + { + if ((retVal = dal_rtl8373_phy_read(phyid,30,top_reg_addr, ®data)) != RT_ERR_OK) + return retVal; + if(1 == value) + regdata |= (1 << offset); + else + regdata &= ~(1 << offset); + + phymask = 1; + return dal_rtl8373_phy_write(phymask, 30, top_reg_addr, regdata); + + } + else + { + offset = offset - 16; + + if ((retVal = dal_rtl8373_phy_read(phyid,30,top_reg_addr+1, ®data)) != RT_ERR_OK) + return retVal; + + if(1 == value) + regdata |= (1 << offset); + else + regdata &= ~(1 << offset); + + phymask = 1; + return dal_rtl8373_phy_write(phymask, 30, top_reg_addr+1, regdata); + } +} + + +/* Function Name: + * dal_rtl8224_top_regbit_read + * Description: + * Get RTL8224 top register bit value. + * Input: + * top_reg_addr - top register address + * offet - bit offset + * value - register bit value + * Output: +* pdata - None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will get phy register data. + */ + +rtk_api_ret_t dal_rtl8224_top_regbit_read(rtk_uint32 top_reg_addr, rtk_uint32 offset, rtk_uint32* pvalue) +{ + rtk_uint32 phyid; + rtk_uint32 regdata; + rtk_api_ret_t retVal; + + phyid=0; + + if(offset < 16) + { + if ((retVal = dal_rtl8373_phy_read(phyid,30,top_reg_addr, ®data)) != RT_ERR_OK) + return retVal; + + *pvalue = (regdata >> offset) & 1; + } + else + { + offset = offset - 16; + if ((retVal = dal_rtl8373_phy_read(phyid,30,top_reg_addr+1, ®data)) != RT_ERR_OK) + return retVal; + + *pvalue = (regdata >> offset) & 1; + } + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8224_top_regbits_write + * Description: + * Set RTL8224 top register bits value. + * Input: + * top_reg_addr - top register address + * bitmask - bit mask + * value - register bits value + * Output: +* pdata - None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will set phy register data. + */ + +rtk_api_ret_t dal_rtl8224_top_regbits_write(rtk_uint32 top_reg_addr, rtk_uint32 bitmask, rtk_uint32 value) +{ + rtk_uint32 phymask; + rtk_uint32 phyid; + rtk_uint32 regdata; + rtk_api_ret_t retVal; + rtk_uint32 bitsShift; + rtk_uint32 valueShifted; + + if( !bitmask ) + return RT_ERR_INPUT; + + bitsShift = 0; + while(!(bitmask & (1 << bitsShift))) + { + bitsShift++; + if(bitsShift >= RTL8373_REGBITLENGTH) + return RT_ERR_INPUT; + } + + valueShifted = value << bitsShift; + if(valueShifted > RTL8373_REGDATAMAX) + return RT_ERR_INPUT; + + if(bitsShift < 16) + { + phyid=0; + if ((retVal = dal_rtl8373_phy_read(phyid,30,top_reg_addr, ®data)) != RT_ERR_OK) + return retVal; + + regdata = regdata & (~bitmask); + regdata = regdata | (valueShifted & bitmask); + + phymask = 1; + return dal_rtl8373_phy_write(phymask, 30, top_reg_addr, regdata); + } + else + { + phyid=0; + if ((retVal = dal_rtl8373_phy_read(phyid,30,top_reg_addr+1, ®data)) != RT_ERR_OK) + return retVal; + + bitmask = bitmask >> 16; + valueShifted = valueShifted >> 16; + regdata = regdata & (~bitmask); + regdata = regdata | (valueShifted & bitmask); + + phymask = 1; + return dal_rtl8373_phy_write(phymask, 30, top_reg_addr+1, regdata); + } + +} + + + +/* Function Name: + * dal_rtl8224_top_regbits_read + * Description: + * Get RTL8224 top register bits value. + * Input: + * top_reg_addr - top register address + * bitmask - bit mask + * value - register bits value + * Output: +* pdata - None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will get phy register data. + */ + +rtk_api_ret_t dal_rtl8224_top_regbits_read(rtk_uint32 top_reg_addr, rtk_uint32 bitmask, rtk_uint32* pvalue) +{ + rtk_uint32 phyid; + rtk_uint32 regdata; + rtk_api_ret_t retVal; + rtk_uint32 bitsShift; + + if( !bitmask ) + return RT_ERR_INPUT; + + bitsShift = 0; + while(!(bitmask & (1 << bitsShift))) + { + bitsShift++; + if(bitsShift >= RTL8373_REGBITLENGTH) + return RT_ERR_INPUT; + } + + phyid=0; + + if(bitsShift < 16) + { + if ((retVal = dal_rtl8373_phy_read(phyid,30,top_reg_addr, ®data)) != RT_ERR_OK) + return retVal; + + *pvalue = (regdata & bitmask) >> bitsShift; + } + else + { + if ((retVal = dal_rtl8373_phy_read(phyid,30,top_reg_addr+1, ®data)) != RT_ERR_OK) + return retVal; + + bitsShift = bitsShift - 16; + bitmask = bitmask >> 16; + *pvalue = (regdata & bitmask) >> bitsShift; + } + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_sds_reg_write + * Description: + * Configure phy register data. + * Input: + * sds_index - sds index 0 ~ 1 + * sds_page - page + * sds_geg - register address + * regdata - input data + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure phy register data. + */ + +rtk_api_ret_t dal_rtl8373_sds_reg_write(rtk_uint32 sds_index, rtk_uint32 sds_page, rtk_uint32 sds_reg, rtk_uint32 regdata) +{ + rtk_api_ret_t retVal; + rtk_uint32 tmp_cmd; + rtk_uint32 pollcnt = 0; + + for(pollcnt = 0; pollcnt < RTL8373_MAX_POLLCNT; pollcnt++) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_SDS_INDACS_CMD_ADDR, RTL8373_SDS_INDACS_CMD_SDS_CMD_OFFSET, &tmp_cmd)) != RT_ERR_OK) + return retVal; + + if(tmp_cmd == 0) + break; + } + + if(pollcnt == RTL8373_MAX_POLLCNT) + return RT_ERR_BUSYWAIT_TIMEOUT; + + if ((retVal = rtl8373_setAsicReg(RTL8373_SDS_INDACS_WD_ADDR, regdata)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8373_setAsicRegBit(RTL8373_SDS_INDACS_CMD_ADDR, RTL8373_SDS_INDACS_CMD_SDS_INDEX_OFFSET, sds_index)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_SDS_INDACS_CMD_ADDR, RTL8373_SDS_INDACS_CMD_SDS_PAGE_MASK, sds_page)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_SDS_INDACS_CMD_ADDR, RTL8373_SDS_INDACS_CMD_SDS_REGAD_MASK, sds_reg)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8373_setAsicRegBit(RTL8373_SDS_INDACS_CMD_ADDR, RTL8373_SDS_INDACS_CMD_SDS_RWOP_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8373_setAsicRegBit(RTL8373_SDS_INDACS_CMD_ADDR, RTL8373_SDS_INDACS_CMD_SDS_CMD_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + + for(pollcnt = 0; pollcnt < RTL8373_MAX_POLLCNT; pollcnt++) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_SDS_INDACS_CMD_ADDR, RTL8373_SDS_INDACS_CMD_SDS_CMD_OFFSET, &tmp_cmd)) != RT_ERR_OK) + return retVal; + + if(tmp_cmd == 0) + break; + } + + if(pollcnt == RTL8373_MAX_POLLCNT) + return RT_ERR_BUSYWAIT_TIMEOUT; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_sds_reg_read + * Description: + * Configure phy register data. + * Input: + * sds_index - sds index 0 ~ 1 + * sds_page - page + * sds_geg - register address + * pdata - output data + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure phy register data. + */ + +rtk_api_ret_t dal_rtl8373_sds_reg_read(rtk_uint32 sds_index, rtk_uint32 sds_page, rtk_uint32 sds_reg, rtk_uint32 * pdata) +{ + rtk_api_ret_t retVal; + rtk_uint32 tmp_cmd; + rtk_uint32 pollcnt = 0; + + for(pollcnt = 0; pollcnt < RTL8373_MAX_POLLCNT; pollcnt++) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_SDS_INDACS_CMD_ADDR, RTL8373_SDS_INDACS_CMD_SDS_CMD_OFFSET, &tmp_cmd)) != RT_ERR_OK) + return retVal; + + if(tmp_cmd == 0) + break; + } + + if(pollcnt == RTL8373_MAX_POLLCNT) + return RT_ERR_BUSYWAIT_TIMEOUT; + + + + if ((retVal = rtl8373_setAsicRegBit(RTL8373_SDS_INDACS_CMD_ADDR, RTL8373_SDS_INDACS_CMD_SDS_INDEX_OFFSET, sds_index)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_SDS_INDACS_CMD_ADDR, RTL8373_SDS_INDACS_CMD_SDS_PAGE_MASK, sds_page)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_SDS_INDACS_CMD_ADDR, RTL8373_SDS_INDACS_CMD_SDS_REGAD_MASK, sds_reg)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8373_setAsicRegBit(RTL8373_SDS_INDACS_CMD_ADDR, RTL8373_SDS_INDACS_CMD_SDS_RWOP_OFFSET, 0)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8373_setAsicRegBit(RTL8373_SDS_INDACS_CMD_ADDR, RTL8373_SDS_INDACS_CMD_SDS_CMD_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + + for(pollcnt = 0; pollcnt < RTL8373_MAX_POLLCNT; pollcnt++) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_SDS_INDACS_CMD_ADDR, RTL8373_SDS_INDACS_CMD_SDS_CMD_OFFSET, &tmp_cmd)) != RT_ERR_OK) + return retVal; + + if(tmp_cmd == 0) + break; + } + + if ((retVal = rtl8373_getAsicReg(RTL8373_SDS_INDACS_RD_ADDR, pdata)) != RT_ERR_OK) + return retVal; + + + if(pollcnt == RTL8373_MAX_POLLCNT) + return RT_ERR_BUSYWAIT_TIMEOUT; + + return RT_ERR_OK; +} + + + +/* Function Name: + * dal_rtl8373_sds_regbits_write + * Description: + * Configure phy register data. + * Input: + * sds_index - sds index 0 ~ 1 + * sds_page - page + * sds_geg - register address + * bitmask - bits mask + * value - input data + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure phy register data. + */ + +rtk_api_ret_t dal_rtl8373_sds_regbits_write(rtk_uint32 sds_index, rtk_uint32 sds_page, rtk_uint32 sds_reg, rtk_uint32 bitmask, rtk_uint32 value) +{ + rtk_api_ret_t retVal; + rtk_uint32 regdata; + rtk_uint32 bitsShift; + rtk_uint32 valueShifted; + + + if( !bitmask ) + return RT_ERR_INPUT; + + bitsShift = 0; + while(!(bitmask & (1 << bitsShift))) + { + bitsShift++; + if(bitsShift >= RTL8373_REGBITLENGTH) + return RT_ERR_INPUT; + } + + valueShifted = value << bitsShift; + if(valueShifted > RTL8373_REGDATAMAX) + return RT_ERR_INPUT; + + + if ((retVal = dal_rtl8373_sds_reg_read(sds_index,sds_page,sds_reg,®data)) != RT_ERR_OK) + return retVal; + + regdata = regdata & (~bitmask); + regdata = regdata | (valueShifted & bitmask); + + if ((retVal = dal_rtl8373_sds_reg_write(sds_index,sds_page,sds_reg,regdata)) != RT_ERR_OK) + return retVal; + + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_sds_regbis_read + * Description: + * Configure phy register data. + * Input: + * sds_index - sds index 0 ~ 1 + * sds_page - page + * sds_geg - register address + * pvalue - output data + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure phy register data. + */ + +rtk_api_ret_t dal_rtl8373_sds_regbits_read(rtk_uint32 sds_index, rtk_uint32 sds_page, rtk_uint32 sds_reg, rtk_uint32 bitmask, rtk_uint32 * pvalue) +{ + rtk_api_ret_t retVal; + rtk_uint32 regdata; + rtk_uint32 bitsShift; + + if( !bitmask ) + return RT_ERR_INPUT; + + bitsShift = 0; + while(!(bitmask & (1 << bitsShift))) + { + bitsShift++; + if(bitsShift >= RTL8373_REGBITLENGTH) + return RT_ERR_INPUT; + } + + + if ((retVal = dal_rtl8373_sds_reg_read(sds_index,sds_page,sds_reg, ®data)) != RT_ERR_OK) + return retVal; + + *pvalue = (regdata & bitmask) >> bitsShift; + + + return RT_ERR_OK; +} + + + + +/* Function Name: + * dal_rtl8224_sdsreg_write + * Description: + * Configure phy register data. + * Input: + * sds_index - sds index 0 ~ 1 + * sds_page - page + * sds_geg - register address + * regdata - input data + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure phy register data. + */ + +rtk_api_ret_t dal_rtl8224_sds_reg_write(rtk_uint32 sds_index, rtk_uint32 sds_page, rtk_uint32 sds_reg, rtk_uint32 regdata) +{ + rtk_api_ret_t retVal; + rtk_uint32 tmp_cmd; + rtk_uint32 pollcnt = 0; + + for(pollcnt = 0; pollcnt < RTL8373_MAX_POLLCNT; pollcnt++) + { + if ((retVal = dal_rtl8224_top_regbit_read(RTL8373_SDS_INDACS_CMD_ADDR, RTL8373_SDS_INDACS_CMD_SDS_CMD_OFFSET, &tmp_cmd)) != RT_ERR_OK) + return retVal; + + if(tmp_cmd == 0) + break; + } + + if(pollcnt == RTL8373_MAX_POLLCNT) + return RT_ERR_BUSYWAIT_TIMEOUT; + + if ((retVal = dal_rtl8224_top_reg_write(RTL8373_SDS_INDACS_WD_ADDR, regdata)) != RT_ERR_OK) + return retVal; + + + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_SDS_INDACS_CMD_ADDR, RTL8373_SDS_INDACS_CMD_SDS_INDEX_OFFSET, sds_index)) != RT_ERR_OK) + return retVal; + + + if ((retVal = dal_rtl8224_top_regbits_write(RTL8373_SDS_INDACS_CMD_ADDR, RTL8373_SDS_INDACS_CMD_SDS_PAGE_MASK, sds_page)) != RT_ERR_OK) + return retVal; + + + if ((retVal = dal_rtl8224_top_regbits_write(RTL8373_SDS_INDACS_CMD_ADDR, RTL8373_SDS_INDACS_CMD_SDS_REGAD_MASK, sds_reg)) != RT_ERR_OK) + return retVal; + + + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_SDS_INDACS_CMD_ADDR, RTL8373_SDS_INDACS_CMD_SDS_RWOP_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_SDS_INDACS_CMD_ADDR, RTL8373_SDS_INDACS_CMD_SDS_CMD_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + + for(pollcnt = 0; pollcnt < RTL8373_MAX_POLLCNT; pollcnt++) + { + if ((retVal = dal_rtl8224_top_regbit_read(RTL8373_SDS_INDACS_CMD_ADDR, RTL8373_SDS_INDACS_CMD_SDS_CMD_OFFSET, &tmp_cmd)) != RT_ERR_OK) + return retVal; + + if(tmp_cmd == 0) + break; + } + + if(pollcnt == RTL8373_MAX_POLLCNT) + return RT_ERR_BUSYWAIT_TIMEOUT; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8224_sdsreg_read + * Description: + * Configure phy register data. + * Input: + * sds_index - sds index 0 ~ 1 + * sds_page - page + * sds_geg - register address + * pdata - output data + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure phy register data. + */ + +rtk_api_ret_t dal_rtl8224_sds_reg_read(rtk_uint32 sds_index, rtk_uint32 sds_page, rtk_uint32 sds_reg, rtk_uint32 * pdata) +{ + rtk_api_ret_t retVal; + rtk_uint32 tmp_cmd; + rtk_uint32 pollcnt = 0; + + for(pollcnt = 0; pollcnt < RTL8373_MAX_POLLCNT; pollcnt++) + { + if ((retVal = dal_rtl8224_top_regbit_read(RTL8373_SDS_INDACS_CMD_ADDR, RTL8373_SDS_INDACS_CMD_SDS_CMD_OFFSET, &tmp_cmd)) != RT_ERR_OK) + return retVal; + + if(tmp_cmd == 0) + break; + } + + if(pollcnt == RTL8373_MAX_POLLCNT) + return RT_ERR_BUSYWAIT_TIMEOUT; + + + + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_SDS_INDACS_CMD_ADDR, RTL8373_SDS_INDACS_CMD_SDS_INDEX_OFFSET, sds_index)) != RT_ERR_OK) + return retVal; + + + if ((retVal = dal_rtl8224_top_regbits_write(RTL8373_SDS_INDACS_CMD_ADDR, RTL8373_SDS_INDACS_CMD_SDS_PAGE_MASK, sds_page)) != RT_ERR_OK) + return retVal; + + + if ((retVal = dal_rtl8224_top_regbits_write(RTL8373_SDS_INDACS_CMD_ADDR, RTL8373_SDS_INDACS_CMD_SDS_REGAD_MASK, sds_reg)) != RT_ERR_OK) + return retVal; + + + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_SDS_INDACS_CMD_ADDR, RTL8373_SDS_INDACS_CMD_SDS_RWOP_OFFSET, 0)) != RT_ERR_OK) + return retVal; + + + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_SDS_INDACS_CMD_ADDR, RTL8373_SDS_INDACS_CMD_SDS_CMD_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + + for(pollcnt = 0; pollcnt < RTL8373_MAX_POLLCNT; pollcnt++) + { + if ((retVal = dal_rtl8224_top_regbit_read(RTL8373_SDS_INDACS_CMD_ADDR, RTL8373_SDS_INDACS_CMD_SDS_CMD_OFFSET, &tmp_cmd)) != RT_ERR_OK) + return retVal; + + if(tmp_cmd == 0) + break; + } + + if ((retVal = dal_rtl8224_top_reg_read(RTL8373_SDS_INDACS_RD_ADDR, pdata)) != RT_ERR_OK) + return retVal; + + + if(pollcnt == RTL8373_MAX_POLLCNT) + return RT_ERR_BUSYWAIT_TIMEOUT; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8224_sds_regbits_write + * Description: + * Configure phy register data. + * Input: + * sds_index - sds index 0 ~ 1 + * sds_page - page + * sds_geg - register address + * bitmask - bits mask + * value - input data + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure phy register data. + */ + +rtk_api_ret_t dal_rtl8224_sds_regbits_write(rtk_uint32 sds_index, rtk_uint32 sds_page, rtk_uint32 sds_reg, rtk_uint32 bitmask, rtk_uint32 value) +{ + rtk_api_ret_t retVal; + rtk_uint32 regdata; + rtk_uint32 bitsShift; + rtk_uint32 valueShifted; + + + if( !bitmask ) + return RT_ERR_INPUT; + + bitsShift = 0; + while(!(bitmask & (1 << bitsShift))) + { + bitsShift++; + if(bitsShift >= RTL8373_REGBITLENGTH) + return RT_ERR_INPUT; + } + + valueShifted = value << bitsShift; + if(valueShifted > RTL8373_REGDATAMAX) + return RT_ERR_INPUT; + + + if ((retVal = dal_rtl8224_sds_reg_read(sds_index,sds_page,sds_reg,®data)) != RT_ERR_OK) + return retVal; + + regdata = regdata & (~bitmask); + regdata = regdata | (valueShifted & bitmask); + + if ((retVal = dal_rtl8224_sds_reg_write(sds_index,sds_page,sds_reg,regdata)) != RT_ERR_OK) + return retVal; + + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8224_sds_regbis_read + * Description: + * Configure phy register data. + * Input: + * sds_index - sds index 0 ~ 1 + * sds_page - page + * sds_geg - register address + * pvalue - output data + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure phy register data. + */ + +rtk_api_ret_t dal_rtl8224_sds_regbits_read(rtk_uint32 sds_index, rtk_uint32 sds_page, rtk_uint32 sds_reg, rtk_uint32 bitmask, rtk_uint32 * pvalue) +{ + rtk_api_ret_t retVal; + rtk_uint32 regdata; + rtk_uint32 bitsShift; + + if( !bitmask ) + return RT_ERR_INPUT; + + bitsShift = 0; + while(!(bitmask & (1 << bitsShift))) + { + bitsShift++; + if(bitsShift >= RTL8373_REGBITLENGTH) + return RT_ERR_INPUT; + } + + + if ((retVal = dal_rtl8224_sds_reg_read(sds_index,sds_page,sds_reg, ®data)) != RT_ERR_OK) + return retVal; + + *pvalue = (regdata & bitmask) >> bitsShift; + + + return RT_ERR_OK; +} + + + +/* Function Name: + * dal_rtl8373_phy_regbits_write + * Description: + * Configure phy register data. + * Input: + * phy_mask - phy mask, bit[0:9] + * dev_addr - device address + * reg_addr - register address + * bitmask - bits mask + * indata - input data + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure phy register data. + */ + +rtk_api_ret_t dal_rtl8373_phy_regbits_write(rtk_uint32 phy_mask, rtk_uint32 dev_addr, rtk_uint32 reg_addr, rtk_uint32 bitmask, rtk_uint32 value) +{ + rtk_api_ret_t retVal; + rtk_uint32 regdata; + rtk_uint32 port; + rtk_uint32 bitsShift; + rtk_uint32 valueShifted; + + + if( !bitmask ) + return RT_ERR_INPUT; + + bitsShift = 0; + while(!(bitmask & (1 << bitsShift))) + { + bitsShift++; + if(bitsShift >= RTL8373_REGBITLENGTH) + return RT_ERR_INPUT; + } + + valueShifted = value << bitsShift; + if(valueShifted > RTL8373_REGDATAMAX) + return RT_ERR_INPUT; + + for(port = 0; port < 9; port++) + { + if((1 << port) & phy_mask) + { + if ((retVal = dal_rtl8373_phy_read(port,dev_addr,reg_addr,®data)) != RT_ERR_OK) + return retVal; + + regdata = regdata & (~bitmask); + regdata = regdata | (valueShifted & bitmask); + + if ((retVal = dal_rtl8373_phy_write(phy_mask,dev_addr,reg_addr,regdata)) != RT_ERR_OK) + return retVal; + } + } + + return RT_ERR_OK; + +} + + +/* Function Name: + * dal_rtl8373_phy_regbits_read + * Description: + * get phy register data. + * Input: + * phy_id - phy id + * dev_addr - device address + * reg_addr - register address + * bitmask - bits mask + * Output: + * pdata - phy data + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will get phy register data. + */ + +rtk_api_ret_t dal_rtl8373_phy_regbits_read(rtk_uint32 phy_id, rtk_uint32 dev_addr, rtk_uint32 reg_addr, rtk_uint32 bitmask, rtk_uint32 * pvalue) +{ + rtk_api_ret_t retVal; + rtk_uint32 regdata; + rtk_uint32 bitsShift; + + if( !bitmask ) + return RT_ERR_INPUT; + + bitsShift = 0; + while(!(bitmask & (1 << bitsShift))) + { + bitsShift++; + if(bitsShift >= RTL8373_REGBITLENGTH) + return RT_ERR_INPUT; + } + + + if ((retVal = dal_rtl8373_phy_read(phy_id,dev_addr,reg_addr, ®data)) != RT_ERR_OK) + return retVal; + + *pvalue = (regdata & bitmask) >> bitsShift; + + + return RT_ERR_OK; +} + + + + diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_drv.h b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_drv.h new file mode 100755 index 00000000..5fefeb07 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_drv.h @@ -0,0 +1,510 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8371c switch high-level API + * + * Feature : The file includes phy module high-layer API defination + * + */ + + #ifndef __DAL_RTL8373_PHY_H__ +#define __DAL_RTL8373_PHY_H__ + +#define RTL8373_MAX_POLLCNT 1000UL + + +/* Function Name: + * dal_rtl8373_mdc_en + * Description: + * Enbale MDC function. + * Input: + * enable - enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will enbale MDC function. + */ +extern rtk_api_ret_t dal_rtl8373_mdc_en(rtk_uint32 enable); + + /* Function Name: + * dal_rtl8373_phy_write + * Description: + * Configure phy register data. + * Input: + * phy_mask - phy mask, bit[0:9] + * dev_addr - device address + * reg_addr - register address + * indata - input data + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure phy register data. + */ +extern rtk_api_ret_t dal_rtl8373_phy_write(rtk_uint32 phy_mask, rtk_uint32 dev_addr, rtk_uint32 reg_addr, rtk_uint32 indata); + +/* Function Name: + * dal_rtl8373_phy_read + * Description: + * get phy register data. + * Input: + * phy_id - phy id + * dev_addr - device address + * reg_addr - register address + * Output: +* pdata - phy data + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will get phy register data. + */ +extern rtk_api_ret_t dal_rtl8373_phy_read(rtk_uint32 phy_id, rtk_uint32 dev_addr, rtk_uint32 reg_addr, rtk_uint32 *pdata); +/* Function Name: + * dal_rtl8373_phy_readBits + * Description: + * Configure phy register data. + * Input: + * phy_id - phy id + * dev_addr - device address + * reg_addr - register address + * indata - input data + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure phy register data. + */ + +extern rtk_api_ret_t dal_rtl8373_phy_readBits(rtk_uint32 phy_id, rtk_uint32 dev_addr, rtk_uint32 reg_addr, rtk_uint32 bitsMask,rtk_uint32 *pdata); + +/* Function Name: + * rtk_port_phyReg_setBits + * Description: + * Configure phy register data. + * Input: + * phy_mask - phy mask, bit[0:9] + * dev_addr - device address + * reg_addr - register address + * indata - input data + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure phy register data. + */ + +extern rtk_api_ret_t dal_rtl8373_phy_writeBits(rtk_uint32 phy_mask, rtk_uint32 dev_addr, rtk_uint32 reg_addr, rtk_uint32 bitsMask,rtk_uint32 indata); +/* Function Name: + * dal_rtl8224_top_reg_write + * Description: + * Set RTL8224 top register value. + * Input: + * top_reg_addr - top register address + * value - register value + * Output: +* pdata - None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will set phy register data. + */ + +extern rtk_api_ret_t dal_rtl8224_top_reg_write(rtk_uint32 top_reg_addr, rtk_uint32 value); + +/* Function Name: + * dal_rtl8224_top_reg_read + * Description: + * Get RTL8224 top register value. + * Input: + * top_reg_addr - top register address + * pvalue - register value + * Output: +* pdata - None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will get phy register data. + */ + +extern rtk_api_ret_t dal_rtl8224_top_reg_read(rtk_uint32 top_reg_addr, rtk_uint32* pvalue); + + +/* Function Name: + * dal_rtl8224_top_regbit_write + * Description: + * Set RTL8224 top register bit value. + * Input: + * top_reg_addr - top register address + * offet - bit offset + * value - register bit value + * Output: +* pdata - None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will set phy register data. + */ + +extern rtk_api_ret_t dal_rtl8224_top_regbit_write(rtk_uint32 top_reg_addr, rtk_uint32 offset, rtk_uint32 value); + + +/* Function Name: + * dal_rtl8224_top_regbit_read + * Description: + * Get RTL8224 top register bit value. + * Input: + * top_reg_addr - top register address + * offet - bit offset + * value - register bit value + * Output: +* pdata - None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will get phy register data. + */ + +extern rtk_api_ret_t dal_rtl8224_top_regbit_read(rtk_uint32 top_reg_addr, rtk_uint32 offset, rtk_uint32* pvalue); + + +/* Function Name: + * dal_rtl8224_top_regbits_write + * Description: + * Set RTL8224 top register bits value. + * Input: + * top_reg_addr - top register address + * bitmask - bit mask + * value - register bits value + * Output: +* pdata - None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will set phy register data. + */ + +extern rtk_api_ret_t dal_rtl8224_top_regbits_write(rtk_uint32 top_reg_addr, rtk_uint32 bitmask, rtk_uint32 value); + + + +/* Function Name: + * dal_rtl8224_top_regbits_read + * Description: + * Get RTL8224 top register bits value. + * Input: + * top_reg_addr - top register address + * bitmask - bit mask + * value - register bits value + * Output: +* pdata - None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will get phy register data. + */ + +extern rtk_api_ret_t dal_rtl8224_top_regbits_read(rtk_uint32 top_reg_addr, rtk_uint32 bitmask, rtk_uint32* pvalue); + +/* Function Name: + * dal_rtl8373_sds_reg_write + * Description: + * Configure phy register data. + * Input: + * sds_index - sds index 0 ~ 1 + * sds_page - page + * sds_geg - register address + * regdata - input data + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure phy register data. + */ + +extern rtk_api_ret_t dal_rtl8373_sds_reg_write(rtk_uint32 sds_index, rtk_uint32 sds_page, rtk_uint32 sds_reg, rtk_uint32 regdata); + + +/* Function Name: + * dal_rtl8373_sds_reg_read + * Description: + * Configure phy register data. + * Input: + * sds_index - sds index 0 ~ 1 + * sds_page - page + * sds_geg - register address + * pdata - output data + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure phy register data. + */ + +extern rtk_api_ret_t dal_rtl8373_sds_reg_read(rtk_uint32 sds_index, rtk_uint32 sds_page, rtk_uint32 sds_reg, rtk_uint32 * pdata); + + + +/* Function Name: + * dal_rtl8373_sds_regbits_write + * Description: + * Configure phy register data. + * Input: + * sds_index - sds index 0 ~ 1 + * sds_page - page + * sds_geg - register address + * bitmask - bits mask + * value - input data + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure phy register data. + */ + +extern rtk_api_ret_t dal_rtl8373_sds_regbits_write(rtk_uint32 sds_index, rtk_uint32 sds_page, rtk_uint32 sds_reg, rtk_uint32 bitmask, rtk_uint32 value); + + +/* Function Name: + * dal_rtl8373_sds_regbis_read + * Description: + * Configure phy register data. + * Input: + * sds_index - sds index 0 ~ 1 + * sds_page - page + * sds_geg - register address + * pvalue - output data + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure phy register data. + */ + +extern rtk_api_ret_t dal_rtl8373_sds_regbits_read(rtk_uint32 sds_index, rtk_uint32 sds_page, rtk_uint32 sds_reg, rtk_uint32 bitmask, rtk_uint32 * pvalue); + + + + +/* Function Name: + * dal_rtl8224_sdsreg_write + * Description: + * Configure phy register data. + * Input: + * sds_index - sds index 0 ~ 1 + * sds_page - page + * sds_geg - register address + * regdata - input data + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure phy register data. + */ + +extern rtk_api_ret_t dal_rtl8224_sds_reg_write(rtk_uint32 sds_index, rtk_uint32 sds_page, rtk_uint32 sds_reg, rtk_uint32 regdata); + + +/* Function Name: + * dal_rtl8224_sdsreg_read + * Description: + * Configure phy register data. + * Input: + * sds_index - sds index 0 ~ 1 + * sds_page - page + * sds_geg - register address + * pdata - output data + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure phy register data. + */ + +extern rtk_api_ret_t dal_rtl8224_sds_reg_read(rtk_uint32 sds_index, rtk_uint32 sds_page, rtk_uint32 sds_reg, rtk_uint32 * pdata); + + +/* Function Name: + * dal_rtl8224_sds_regbits_write + * Description: + * Configure phy register data. + * Input: + * sds_index - sds index 0 ~ 1 + * sds_page - page + * sds_geg - register address + * bitmask - bits mask + * value - input data + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure phy register data. + */ + +extern rtk_api_ret_t dal_rtl8224_sds_regbits_write(rtk_uint32 sds_index, rtk_uint32 sds_page, rtk_uint32 sds_reg, rtk_uint32 bitmask, rtk_uint32 value); + + +/* Function Name: + * dal_rtl8224_sds_regbis_read + * Description: + * Configure phy register data. + * Input: + * sds_index - sds index 0 ~ 1 + * sds_page - page + * sds_geg - register address + * pvalue - output data + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure phy register data. + */ + +extern rtk_api_ret_t dal_rtl8224_sds_regbits_read(rtk_uint32 sds_index, rtk_uint32 sds_page, rtk_uint32 sds_reg, rtk_uint32 bitmask, rtk_uint32 * pvalue); + +/* Function Name: + * dal_rtl8373_phy_regbits_write + * Description: + * Configure phy register data. + * Input: + * phy_mask - phy mask, bit[0:9] + * dev_addr - device address + * reg_addr - register address + * bitmask - bits mask + * indata - input data + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure phy register data. + */ + +extern rtk_api_ret_t dal_rtl8373_phy_regbits_write(rtk_uint32 phy_mask, rtk_uint32 dev_addr, rtk_uint32 reg_addr, rtk_uint32 bitmask, rtk_uint32 value); + +/* Function Name: + * dal_rtl8373_phy_regbits_read + * Description: + * get phy register data. + * Input: + * phy_id - phy id + * dev_addr - device address + * reg_addr - register address + * bitmask - bits mask + * Output: + * pdata - phy data + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will get phy register data. + */ + +extern rtk_api_ret_t dal_rtl8373_phy_regbits_read(rtk_uint32 phy_id, rtk_uint32 dev_addr, rtk_uint32 reg_addr, rtk_uint32 bitmask, rtk_uint32 * pvalue); + + +#endif + diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_eee.c b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_eee.c new file mode 100755 index 00000000..008cab5b --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_eee.c @@ -0,0 +1,256 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8373 + * Feature : Here is a list of all functions and variables in EEE module. + * + */ + +#include +#include +#include +#include +#include + +/* Function Name: + * dal_rtl8373_eee_init + * Description: + * Initial EEE function. + * Input: + * None + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * This API can set EEE function to the specific port. + * The configuration of the port is as following: + * - DISABLE + * - ENABLE + */ + +rtk_api_ret_t dal_rtl8373_eee_init(void) +{ + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_eee_macForceSpeedEn_set + * Description: + * Set enable status of EEE for a Specified Speed, + * Input: + * port - port id. + * speed - a specified + * enable - enable EEE status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * This API can set EEE function to the specific port. + * The configuration of the port is as following: + * - DISABLE + * - ENABLE + */ +rtk_api_ret_t dal_rtl8373_eee_macForceSpeedEn_set(rtk_port_t port, rtk_eee_speedInMacForceMode_t speed, rtk_enable_t enable) +{ + rtk_uint32 retVal = 0; + + /* Check port valid */ + RTK_CHK_PORT_VALID(port); + + if((speed >= EEE_MAC_FORCE_SPEED_END) || (enable >=RTK_ENABLE_END)) + return RT_ERR_RANGE; + + if((retVal = rtl8373_setAsicRegBit(RTL8373_MAC_FORCE_MODE_CTRL1_ADDR(port), speed, (rtk_uint32)enable)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_eee_macForceSpeedEn_get + * Description: + * Get port_n status of EEE for a Specified Speed, + * Input: + * port - port id. + * speed - a specified + * Output: + * pEnable - EEE status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * This API can get EEE function to the specific port. + * The configuration of the port is as following: + * - DISABLE + * - ENABLE + */ +rtk_api_ret_t dal_rtl8373_eee_macForceSpeedEn_get(rtk_port_t port, rtk_eee_speedInMacForceMode_t speed, rtk_enable_t *pEnable) +{ + rtk_uint32 regVal = 0, retVal = 0; + + /* Check port valid */ + RTK_CHK_PORT_VALID(port); + + if(speed >= EEE_MAC_FORCE_SPEED_END) + return RT_ERR_RANGE; + if(pEnable == NULL) + return RT_ERR_NULL_POINTER; + + if((retVal = rtl8373_getAsicRegBit(RTL8373_MAC_FORCE_MODE_CTRL1_ADDR(port), speed, ®Val)) != RT_ERR_OK) + return retVal; + + *pEnable = (rtk_enable_t)regVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_eee_macForceAllSpeedEn_get + * Description: + * Get port_n status of EEE for all Speed. + * port - port id. + * Output: + * pState - EEE status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * This API can get EEE function to the specific port. + * The configuration of the port is as following: + * - DISABLE + * - ENABLE + */ +rtk_api_ret_t dal_rtl8373_eee_macForceAllSpeedEn_get(rtk_port_t port, rtk_uint32 *pState) +{ + rtk_uint32 retVal = 0; + + /* Check port valid */ + RTK_CHK_PORT_VALID(port); + + if(pState == NULL) + return RT_ERR_NULL_POINTER; + + if((retVal = rtl8373_getAsicRegBits(RTL8373_MAC_FORCE_MODE_CTRL1_ADDR(port), 0x1FF, pState)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_eee_portTxRxEn_set + * Description: + * Set port_n Tx & Rx EEE capability. + * Input: + * port - port id. + * rxEn - Enable or Disable Rx EEE capability. + * txEn - Enable or Disable Tx EEE capability. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * This API can config tx EEE and rx EEE capability to the specific port. + * The configuration of the port is as following: + * - DISABLE + * - ENABLE + */ +rtk_api_ret_t dal_rtl8373_eee_portTxRxEn_set(rtk_port_t port, rtk_enable_t rxEn, rtk_enable_t txEn) +{ + rtk_uint32 retVal = 0; + + /* Check port valid */ + RTK_CHK_PORT_VALID(port); + + if((rxEn >=RTK_ENABLE_END) || (txEn >=RTK_ENABLE_END)) + return RT_ERR_RANGE; + + if((retVal = rtl8373_setAsicRegBit(RTL8373_EEE_CTRL_ADDR(port), RTL8373_EEE_CTRL_EEE_PORT_RX_EN_OFFSET, (rtk_uint32)rxEn)) != RT_ERR_OK) + return retVal; + if((retVal = rtl8373_setAsicRegBit(RTL8373_EEE_CTRL_ADDR(port), RTL8373_EEE_CTRL_EEE_PORT_TX_EN_OFFSET, (rtk_uint32)txEn)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_eee_portTxRxEn_set + * Description: + * Set port_n Tx & Rx EEE capability. + * Input: + * port - port id. + * rxEn - Enable or Disable Rx EEE capability. + * txEn - Enable or Disable Tx EEE capability. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * This API can config tx EEE and rx EEE capability to the specific port. + * The configuration of the port is as following: + * - DISABLE + * - ENABLE + */ +rtk_api_ret_t dal_rtl8373_eee_portTxRxEn_get(rtk_port_t port, rtk_enable_t *pRxEn, rtk_enable_t *pTxEn) +{ + rtk_uint32 regVal = 0, retVal = 0; + + /* Check port valid */ + RTK_CHK_PORT_VALID(port); + + if((pRxEn == NULL) || (pTxEn == NULL)) + return RT_ERR_NULL_POINTER; + + if((retVal = rtl8373_getAsicRegBit(RTL8373_EEE_CTRL_ADDR(port), RTL8373_EEE_CTRL_EEE_PORT_RX_EN_OFFSET, ®Val)) != RT_ERR_OK) + return retVal; + *pRxEn = (rtk_enable_t)regVal; + + + if((retVal = rtl8373_getAsicRegBit(RTL8373_EEE_CTRL_ADDR(port), RTL8373_EEE_CTRL_EEE_PORT_TX_EN_OFFSET, ®Val)) != RT_ERR_OK) + return retVal; + *pTxEn = (rtk_enable_t)regVal; + + return RT_ERR_OK; +} + + + + + + + diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_eee.h b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_eee.h new file mode 100755 index 00000000..3c72596a --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_eee.h @@ -0,0 +1,163 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8373 switch high-level API + * + * Feature : The file includes EEE module high-layer API defination + * + */ + +#ifndef __DAL_RTL8373_EEE_H__ +#define __DAL_RTL8373_EEE_H__ +#include + + +/* Function Name: + * dal_rtl8373_eee_init + * Description: + * Initial EEE function. + * Input: + * None + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * This API can set EEE function to the specific port. + * The configuration of the port is as following: + * - DISABLE + * - ENABLE + */ + +extern rtk_api_ret_t dal_rtl8373_eee_init(void); + +/* Function Name: + * dal_rtl8373_eee_macForceSpeedEn_set + * Description: + * Set enable status of EEE for a Specified Speed, + * Input: + * port - port id. + * speed - a specified + * enable - enable EEE status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * This API can set EEE function to the specific port. + * The configuration of the port is as following: + * - DISABLE + * - ENABLE + */ +extern rtk_api_ret_t dal_rtl8373_eee_macForceSpeedEn_set(rtk_port_t port, rtk_eee_speedInMacForceMode_t speed, rtk_enable_t enable); + +/* Function Name: + * dal_rtl8373_eee_macForceSpeedEn_get + * Description: + * Get port_n status of EEE for a Specified Speed, + * Input: + * port - port id. + * speed - a specified + * Output: + * pEnable - EEE status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * This API can get EEE function to the specific port. + * The configuration of the port is as following: + * - DISABLE + * - ENABLE + */ +extern rtk_api_ret_t dal_rtl8373_eee_macForceSpeedEn_get(rtk_port_t port, rtk_eee_speedInMacForceMode_t speed, rtk_enable_t *pEnable); + +/* Function Name: + * dal_rtl8373_eee_macForceAllSpeedEn_get + * Description: + * Get port_n status of EEE for all Speed. + * port - port id. + * Output: + * pState - EEE status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * This API can get EEE function to the specific port. + * The configuration of the port is as following: + * - DISABLE + * - ENABLE + */ +extern rtk_api_ret_t dal_rtl8373_eee_macForceAllSpeedEn_get(rtk_port_t port, rtk_uint32 *pState); + +/* Function Name: + * dal_rtl8373_eee_portTxRxEn_set + * Description: + * Set port_n Tx & Rx EEE capability. + * Input: + * port - port id. + * rxEn - Enable or Disable Rx EEE capability. + * txEn - Enable or Disable Tx EEE capability. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * This API can config tx EEE and rx EEE capability to the specific port. + * The configuration of the port is as following: + * - DISABLE + * - ENABLE + */ +extern rtk_api_ret_t dal_rtl8373_eee_portTxRxEn_set(rtk_port_t port, rtk_enable_t rxEn, rtk_enable_t txEn); + +/* Function Name: + * dal_rtl8373_eee_portTxRxEn_set + * Description: + * Set port_n Tx & Rx EEE capability. + * Input: + * port - port id. + * rxEn - Enable or Disable Rx EEE capability. + * txEn - Enable or Disable Tx EEE capability. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * This API can config tx EEE and rx EEE capability to the specific port. + * The configuration of the port is as following: + * - DISABLE + * - ENABLE + */ +extern rtk_api_ret_t dal_rtl8373_eee_portTxRxEn_get(rtk_port_t port, rtk_enable_t *pRxEn, rtk_enable_t *pTxEn); + +#endif /* __DAL_RTL8373_EEE_H__ */ diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_fc.c b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_fc.c new file mode 100755 index 00000000..9909360b --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_fc.c @@ -0,0 +1,1256 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8373 + * Feature : Here is a list of all functions and variables in Flow Control module. + * + */ + +#include +#include +#include +#include +#include + + +/* Function Name: + * dal_rtl8373_asicFCPubPage_set + * Description: + * Set public page number + * Input: + * number - public page number + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t dal_rtl8373_asicFCPubPage_set(rtk_uint32 number) +{ + ret_t retVal; + + + retVal = rtl8373_setAsicRegBits(RTL8373_FC_GLB_DROP_THR_ADDR, RTL8373_FC_GLB_DROP_THR_PUB_PAGE_MASK, number); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + + +/* Function Name: + * dal_rtl8373_asicFCPubPage_get + * Description: + * Get public page number + * Input: + * number - public page number + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t dal_rtl8373_asicFCPubPage_get(rtk_uint32* pNumber) +{ + ret_t retVal; + + + retVal = rtl8373_getAsicRegBits(RTL8373_FC_GLB_DROP_THR_ADDR, RTL8373_FC_GLB_DROP_THR_PUB_PAGE_MASK, pNumber); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_asicFCDropAll_set + * Description: + * Set drop all page number + * Input: + * number - drop all page number + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t dal_rtl8373_asicFCDropAll_set(rtk_uint32 number) +{ + ret_t retVal; + + + retVal = rtl8373_setAsicRegBits(RTL8373_FC_GLB_DROP_THR_ADDR, RTL8373_FC_GLB_DROP_THR_DROP_ALL_MASK, number); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + + +/* Function Name: + * dal_rtl8373_asicFCDropAll_get + * Description: + * get drop all page number + * Input: + * number - drop all page number + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t dal_rtl8373_asicFCDropAll_get(rtk_uint32* pNumber) +{ + ret_t retVal; + + + retVal = rtl8373_getAsicRegBits(RTL8373_FC_GLB_DROP_THR_ADDR, RTL8373_FC_GLB_DROP_THR_DROP_ALL_MASK, pNumber); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + + + +/* Function Name: + * dal_rtl8373_asicFCOnHiThr_set + * Description: + * Set flow control on high threshold page number + * Input: + * onNumber - pause on number + * offNumber - pause off number + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t dal_rtl8373_asicFCOnHiThr_set(rtk_uint32 onNumber, rtk_uint32 offNumber) +{ + ret_t retVal; + + + retVal = rtl8373_setAsicRegBits(RTL8373_FC_GLB_HI_THR_ADDR, RTL8373_FC_GLB_HI_THR_ON_MASK, onNumber); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8373_setAsicRegBits(RTL8373_FC_GLB_HI_THR_ADDR, RTL8373_FC_GLB_HI_THR_OFF_MASK, offNumber); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_asicFCOnHiThr_get + * Description: + * Get flow control on high threshold page number + * Input: + * onNumber - pause on number + * offNumber - pause off number + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t dal_rtl8373_asicFCOnHiThr_get(rtk_uint32* onNumber, rtk_uint32* offNumber) +{ + ret_t retVal; + + + retVal = rtl8373_getAsicRegBits(RTL8373_FC_GLB_HI_THR_ADDR, RTL8373_FC_GLB_HI_THR_ON_MASK, onNumber); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8373_getAsicRegBits(RTL8373_FC_GLB_HI_THR_ADDR, RTL8373_FC_GLB_HI_THR_OFF_MASK, offNumber); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_asicFCOnLoThr_set + * Description: + * Set flow control on low threshold page number + * Input: + * onNumber - pause on number + * offNumber - pause off number + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t dal_rtl8373_asicFCOnLoThr_set(rtk_uint32 onNumber, rtk_uint32 offNumber) +{ + ret_t retVal; + + + retVal = rtl8373_setAsicRegBits(RTL8373_FC_GLB_LO_THR_ADDR, RTL8373_FC_GLB_LO_THR_ON_MASK, onNumber); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8373_setAsicRegBits(RTL8373_FC_GLB_LO_THR_ADDR, RTL8373_FC_GLB_LO_THR_OFF_MASK, offNumber); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_asicFCOnLoThr_get + * Description: + * Get flow control on low threshold page number + * Input: + * onNumber - pause on number + * offNumber - pause off number + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t dal_rtl8373_asicFCOnLoThr_get(rtk_uint32* onNumber, rtk_uint32* offNumber) +{ + ret_t retVal; + + + retVal = rtl8373_getAsicRegBits(RTL8373_FC_GLB_LO_THR_ADDR, RTL8373_FC_GLB_LO_THR_ON_MASK, onNumber); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8373_getAsicRegBits(RTL8373_FC_GLB_LO_THR_ADDR, RTL8373_FC_GLB_LO_THR_OFF_MASK, offNumber); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + + +/* Function Name: + * dal_rtl8373_asicFCOffHiThr_set + * Description: + * Set flow control off high threshold page number + * Input: + * onNumber - pause on number + * offNumber - pause off number + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t dal_rtl8373_asicFCOffHiThr_set(rtk_uint32 onNumber, rtk_uint32 offNumber) +{ + ret_t retVal; + + + retVal = rtl8373_setAsicRegBits(RTL8373_FC_GLB_FCOFF_HI_THR_ADDR, RTL8373_FC_GLB_FCOFF_HI_THR_ON_MASK, onNumber); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8373_setAsicRegBits(RTL8373_FC_GLB_FCOFF_HI_THR_ADDR, RTL8373_FC_GLB_FCOFF_HI_THR_OFF_MASK, offNumber); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_asicFCOffHiThr_get + * Description: + * Get flow control off high threshold page number + * Input: + * onNumber - pause on number + * offNumber - pause off number + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t dal_rtl8373_asicFCOffHiThr_get(rtk_uint32* onNumber, rtk_uint32* offNumber) +{ + ret_t retVal; + + + retVal = rtl8373_getAsicRegBits(RTL8373_FC_GLB_FCOFF_HI_THR_ADDR, RTL8373_FC_GLB_FCOFF_HI_THR_ON_MASK, onNumber); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8373_getAsicRegBits(RTL8373_FC_GLB_FCOFF_HI_THR_ADDR, RTL8373_FC_GLB_FCOFF_HI_THR_OFF_MASK, offNumber); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + + +/* Function Name: + * dal_rtl8373_asicFCOffLoThr_set + * Description: + * Set flow control off low threshold page number + * Input: + * onNumber - pause on number + * offNumber - pause off number + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t dal_rtl8373_asicFCOffLoThr_set(rtk_uint32 onNumber, rtk_uint32 offNumber) +{ + ret_t retVal; + + + retVal = rtl8373_setAsicRegBits(RTL8373_FC_GLB_FCOFF_LO_THR_ADDR, RTL8373_FC_GLB_FCOFF_LO_THR_ON_MASK, onNumber); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8373_setAsicRegBits(RTL8373_FC_GLB_FCOFF_LO_THR_ADDR, RTL8373_FC_GLB_FCOFF_LO_THR_OFF_MASK, offNumber); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_asicFCOffLoThr_get + * Description: + * Get flow control off low threshold page number + * Input: + * onNumber - pause on number + * offNumber - pause off number + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t dal_rtl8373_asicFCOffLoThr_get(rtk_uint32* onNumber, rtk_uint32* offNumber) +{ + ret_t retVal; + + + retVal = rtl8373_getAsicRegBits(RTL8373_FC_GLB_FCOFF_LO_THR_ADDR, RTL8373_FC_GLB_FCOFF_LO_THR_ON_MASK, onNumber); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8373_getAsicRegBits(RTL8373_FC_GLB_FCOFF_LO_THR_ADDR, RTL8373_FC_GLB_FCOFF_LO_THR_OFF_MASK, offNumber); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + + + +/* Function Name: + * dal_rtl8373_asicFCOnPortHiThr_set + * Description: + * Set flow control on high threshold page number + * Input: + * index - 0 ~ 3 + * onNumber - pause on number + * offNumber - pause off number + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t dal_rtl8373_asicFCOnPortHiThr_set(rtk_uint32 index, rtk_uint32 onNumber, rtk_uint32 offNumber) +{ + ret_t retVal; + + + retVal = rtl8373_setAsicRegBits(RTL8373_FC_PORT_HI_THR_ADDR(index), RTL8373_FC_PORT_HI_THR_ON_MASK, onNumber); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8373_setAsicRegBits(RTL8373_FC_PORT_HI_THR_ADDR(index), RTL8373_FC_PORT_HI_THR_OFF_MASK, offNumber); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_asicFCOnPortHiThr_get + * Description: + * Get flow control on high threshold page number + * Input: + * index - 0 ~ 3 + * onNumber - pause on number + * offNumber - pause off number + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t dal_rtl8373_asicFCOnPortHiThr_get(rtk_uint32 index, rtk_uint32* onNumber, rtk_uint32* offNumber) +{ + ret_t retVal; + + + retVal = rtl8373_getAsicRegBits(RTL8373_FC_PORT_HI_THR_ADDR(index), RTL8373_FC_PORT_HI_THR_ON_MASK, onNumber); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8373_getAsicRegBits(RTL8373_FC_PORT_HI_THR_ADDR(index), RTL8373_FC_PORT_HI_THR_OFF_MASK, offNumber); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_asicFCOnPortLoThr_set + * Description: + * Set flow control on low threshold page number + * Input: + * index - 0 ~ 3 + * onNumber - pause on number + * offNumber - pause off number + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t dal_rtl8373_asicFCOnPortLoThr_set(rtk_uint32 index, rtk_uint32 onNumber, rtk_uint32 offNumber) +{ + ret_t retVal; + + + retVal = rtl8373_setAsicRegBits(RTL8373_FC_PORT_LO_THR_ADDR(index), RTL8373_FC_PORT_LO_THR_ON_MASK, onNumber); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8373_setAsicRegBits(RTL8373_FC_PORT_LO_THR_ADDR(index), RTL8373_FC_PORT_LO_THR_OFF_MASK, offNumber); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_asicFCOnPortLoThr_get + * Description: + * Get flow control on low threshold page number + * Input: + * index - 0 ~ 3 + * onNumber - pause on number + * offNumber - pause off number + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t dal_rtl8373_asicFCOnPortLoThr_get(rtk_uint32 index, rtk_uint32* onNumber, rtk_uint32* offNumber) +{ + ret_t retVal; + + + retVal = rtl8373_getAsicRegBits(RTL8373_FC_PORT_LO_THR_ADDR(index), RTL8373_FC_PORT_LO_THR_ON_MASK, onNumber); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8373_getAsicRegBits(RTL8373_FC_PORT_LO_THR_ADDR(index), RTL8373_FC_PORT_LO_THR_OFF_MASK, offNumber); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + + +/* Function Name: + * dal_rtl8373_asicFCOffPortHiThr_set + * Description: + * Set flow control off high threshold page number + * Input: + * index - 0 ~ 3 + * onNumber - pause on number + * offNumber - pause off number + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t dal_rtl8373_asicFCOffPortHiThr_set(rtk_uint32 index, rtk_uint32 onNumber, rtk_uint32 offNumber) +{ + ret_t retVal; + + + retVal = rtl8373_setAsicRegBits(RTL8373_FC_PORT_FCOFF_HI_THR_ADDR(index), RTL8373_FC_PORT_FCOFF_HI_THR_ON_MASK, onNumber); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8373_setAsicRegBits(RTL8373_FC_PORT_FCOFF_HI_THR_ADDR(index), RTL8373_FC_PORT_FCOFF_HI_THR_OFF_MASK, offNumber); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_asicFCOffPortHiThr_get + * Description: + * Get flow control off high threshold page number + * Input: + * index - 0 ~ 3 + * onNumber - pause on number + * offNumber - pause off number + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t dal_rtl8373_asicFCOffPortHiThr_get(rtk_uint32 index, rtk_uint32* onNumber, rtk_uint32* offNumber) +{ + ret_t retVal; + + + retVal = rtl8373_getAsicRegBits(RTL8373_FC_PORT_FCOFF_HI_THR_ADDR(index), RTL8373_FC_PORT_FCOFF_HI_THR_ON_MASK, onNumber); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8373_getAsicRegBits(RTL8373_FC_PORT_FCOFF_HI_THR_ADDR(index), RTL8373_FC_PORT_FCOFF_HI_THR_OFF_MASK, offNumber); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + + +/* Function Name: + * dal_rtl8373_asicFCOffPortLoThr_set + * Description: + * Set flow control off low threshold page number + * Input: + * index - 0 ~ 3 + * onNumber - pause on number + * offNumber - pause off number + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t dal_rtl8373_asicFCOffPortLoThr_set(rtk_uint32 index, rtk_uint32 onNumber, rtk_uint32 offNumber) +{ + ret_t retVal; + + + retVal = rtl8373_setAsicRegBits(RTL8373_FC_PORT_FCOFF_LO_THR_ADDR(index), RTL8373_FC_PORT_FCOFF_LO_THR_ON_MASK, onNumber); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8373_setAsicRegBits(RTL8373_FC_PORT_FCOFF_LO_THR_ADDR(index), RTL8373_FC_PORT_FCOFF_LO_THR_OFF_MASK, offNumber); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_asicFCOffPortLoThr_get + * Description: + * Get flow control off low threshold page number + * Input: + * index - 0 ~ 3 + * onNumber - pause on number + * offNumber - pause off number + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t dal_rtl8373_asicFCOffPortLoThr_get(rtk_uint32 index, rtk_uint32* onNumber, rtk_uint32* offNumber) +{ + ret_t retVal; + + + retVal = rtl8373_getAsicRegBits(RTL8373_FC_PORT_FCOFF_LO_THR_ADDR(index), RTL8373_FC_PORT_FCOFF_LO_THR_ON_MASK, onNumber); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8373_getAsicRegBits(RTL8373_FC_PORT_FCOFF_LO_THR_ADDR(index), RTL8373_FC_PORT_FCOFF_LO_THR_OFF_MASK, offNumber); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + + +/* Function Name: + * dal_rtl8373_asicFCPortGua_set + * Description: + * Set port guarantee page + * Input: + * index - 0 ~ 3 + * number - guarantee + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t dal_rtl8373_asicFCPortGua_set(rtk_uint32 index, rtk_uint32 number) +{ + ret_t retVal; + + + retVal = rtl8373_setAsicRegBits(RTL8373_FC_PORT_GUAR_THR_ADDR(index), RTL8373_FC_PORT_GUAR_THR_THR_MASK, number); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8373_setAsicRegBits(RTL8373_FC_PORT_GUAR_THR_ADDR(index), RTL8373_FC_PORT_GUAR_THR_THR_MASK, number); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + + + +/* Function Name: + * dal_rtl8373_asicFCPortGua_get + * Description: + * Set port guarantee page + * Input: + * index - 0 ~ 3 + * number - guarantee + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t dal_rtl8373_asicFCPortGua_get(rtk_uint32 index, rtk_uint32* pNumber) +{ + ret_t retVal; + + + retVal = rtl8373_getAsicRegBits(RTL8373_FC_PORT_GUAR_THR_ADDR(index), RTL8373_FC_PORT_GUAR_THR_THR_MASK, pNumber); + if(retVal != RT_ERR_OK) + return retVal; + + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_asicFCPortThrSel_set + * Description: + * Set port threshold select + * Input: + * port - 0 ~ 9 + * index - 0 ~ 3 + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t dal_rtl8373_asicFCPortThrSel_set(rtk_uint32 port, rtk_uint32 index) +{ + ret_t retVal; + + + retVal = rtl8373_setAsicRegBits(RTL8373_FC_PORT_THR_SET_SEL_ADDR(port), RTL8373_FC_PORT_THR_SET_SEL_IDX_MASK(port) , index); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_asicFCPortThrSel_get + * Description: + * Set port threshold select + * Input: + * port - 0 ~ 9 + * index - 0 ~ 3 + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t dal_rtl8373_asicFCPortThrSel_get(rtk_uint32 port, rtk_uint32* pIndex) +{ + ret_t retVal; + + + retVal = rtl8373_getAsicRegBits(RTL8373_FC_PORT_THR_SET_SEL_ADDR(port), RTL8373_FC_PORT_THR_SET_SEL_IDX_MASK(port) , pIndex); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + + +/* Function Name: + * dal_rtl8373_asicFCPortThrSel_set + * Description: + * Set port threshold select + * Input: + * type - 0:unknown unicast 1: l2 multicast 2: broadcast + * enable - 0:disable hol prevention 1: enable hol prevention + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t dal_rtl8373_asicFCHOLPrvnt_set(rtk_uint32 type, rtk_uint32 enable) +{ + ret_t retVal; + + + retVal = rtl8373_setAsicRegBit(RTL8373_FC_HOL_PRVNT_CTRL_ADDR, 1 << type , enable); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + + +/* Function Name: + * dal_rtl8373_asicFCPortThrSel_get + * Description: + * Set port threshold select + * Input: + * type - 0:unknown unicast 1: l2 multicast 2: broadcast + * enable - 0:disable hol prevention 1: enable hol prevention + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t dal_rtl8373_asicFCHOLPrvnt_get(rtk_uint32 type, rtk_uint32* pEnable) +{ + ret_t retVal; + + + retVal = rtl8373_getAsicRegBit(RTL8373_FC_HOL_PRVNT_CTRL_ADDR, 1 << type , pEnable); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_asicFCPortHOLPrvntEn_set + * Description: + * Set port threshold select + * Input: + * port - 0 ~ 9 + * enable - 0:disable hol prevention 1: enable hol prevention + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t dal_rtl8373_asicFCPortHOLPrvntEn_set(rtk_uint32 port, rtk_uint32 enable) +{ + ret_t retVal; + + + retVal = rtl8373_setAsicRegBit(RTL8373_FC_PORT_EGR_DROP_CTRL_ADDR(port), RTL8373_FC_PORT_EGR_DROP_CTRL_HOL_PRVNT_EN_OFFSET , enable); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_asicFCPortHOLPrvntEn_get + * Description: + * Get port threshold select + * Input: + * port - 0 ~ 9 + * enable - 0:disable hol prevention 1: enable hol prevention + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t dal_rtl8373_asicFCPortHOLPrvntEn_get(rtk_uint32 port, rtk_uint32* enable) +{ + ret_t retVal; + + + retVal = rtl8373_getAsicRegBit(RTL8373_FC_PORT_EGR_DROP_CTRL_ADDR(port), RTL8373_FC_PORT_EGR_DROP_CTRL_HOL_PRVNT_EN_OFFSET , enable); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + + +/* Function Name: + * dal_rtl8373_asicFCPortAct_set + * Description: + * Set port flow control action + * Input: + * portnum - 0 ~ 9 + * act - 0:receive 1: drop + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t dal_rtl8373_asicFCPortAct_set(rtk_uint32 portnum, rtk_uint32 act) +{ + ret_t retVal; + + + retVal = rtl8373_setAsicRegBits(RTL8373_FC_PORT_ACT_CTRL_ADDR(portnum), RTL8373_FC_PORT_ACT_CTRL_ACT_MASK, act); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_asicFCPortAct_get + * Description: + * Get port flow control action + * Input: + * portnum - 0 ~ 9 + * act - 0:receive 1: drop + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t dal_rtl8373_asicFCPortAct_get(rtk_uint32 portnum, rtk_uint32* pAct) +{ + ret_t retVal; + + + retVal = rtl8373_getAsicRegBits(RTL8373_FC_PORT_ACT_CTRL_ADDR(portnum), RTL8373_FC_PORT_ACT_CTRL_ACT_MASK, pAct); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + + +/* Function Name: + * dal_rtl8373_asicFCPortAllowPage_set + * Description: + * Set port allow page number + * Input: + * portnum - 0 ~ 9 + * pagenum - allow page number + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t dal_rtl8373_asicFCPortAllowPage_set(rtk_uint32 portnum, rtk_uint32 pagenum) +{ + ret_t retVal; + + + retVal = rtl8373_setAsicRegBits(RTL8373_FC_PORT_ACT_CTRL_ADDR(portnum), RTL8373_FC_PORT_ACT_CTRL_ALLOW_PAGE_CNT_MASK, pagenum); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + + +/* Function Name: + * dal_rtl8373_asicFCPortAllowPage_get + * Description: + * Get port allow page number + * Input: + * portnum - 0 ~ 9 + * pagenum - allow page number + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t dal_rtl8373_asicFCPortAllowPage_get(rtk_uint32 portnum, rtk_uint32* pPagenum) +{ + ret_t retVal; + + + retVal = rtl8373_getAsicRegBits(RTL8373_FC_PORT_ACT_CTRL_ADDR(portnum), RTL8373_FC_PORT_ACT_CTRL_ALLOW_PAGE_CNT_MASK, pPagenum); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_asicFCQEgrDropThr_set + * Description: + * Set flow control on high threshold page number + * Input: + * index - 0 ~ 3 + * queueid - 0 ~ 7 + * onNumber - pause on number + * offNumber - pause off number + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t dal_rtl8373_asicFCQEgrDropThr_set(rtk_uint32 index, rtk_uint32 queueid, rtk_uint32 onNumber, rtk_uint32 offNumber) +{ + ret_t retVal; + + + retVal = rtl8373_setAsicRegBits(RTL8373_FC_Q_EGR_DROP_THR_ADDR(queueid, index), RTL8373_FC_Q_EGR_DROP_THR_ON_MASK, onNumber); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8373_setAsicRegBits(RTL8373_FC_Q_EGR_DROP_THR_ADDR(queueid, index), RTL8373_FC_Q_EGR_DROP_THR_OFF_MASK, offNumber); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + + +/* Function Name: + * dal_rtl8373_asicFCQEgrDropThr_get + * Description: + * Get flow control on high threshold page number + * Input: + * index - 0 ~ 3 + * queueid - 0 ~ 7 + * onNumber - pause on number + * offNumber - pause off number + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t dal_rtl8373_asicFCQEgrDropThr_get(rtk_uint32 index, rtk_uint32 queueid, rtk_uint32* onNumber, rtk_uint32* offNumber) +{ + ret_t retVal; + + + retVal = rtl8373_getAsicRegBits(RTL8373_FC_Q_EGR_DROP_THR_ADDR(queueid, index), RTL8373_FC_Q_EGR_DROP_THR_ON_MASK, onNumber); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8373_getAsicRegBits(RTL8373_FC_Q_EGR_DROP_THR_ADDR(queueid, index), RTL8373_FC_Q_EGR_DROP_THR_OFF_MASK, offNumber); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_asicFCPortQEgrDropThrSel_set + * Description: + * Select port queue egress drop threshold + * Input: + * port - 0 ~ 9 + * index - 0 ~ 3 + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t dal_rtl8373_asicFCPortQEgrDropThrSel_set(rtk_uint32 port, rtk_uint32 index) +{ + ret_t retVal; + + + retVal = rtl8373_setAsicRegBits(RTL8373_FC_PORT_EGR_DROP_THR_SET_SEL_ADDR(port), RTL8373_FC_PORT_EGR_DROP_THR_SET_SEL_IDX_MASK(port) , index); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_asicFCPortQEgrDropThrSel_get + * Description: + * Gelect port queue egress drop threshold + * Input: + * port - 0 ~ 9 + * index - 0 ~ 3 + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t dal_rtl8373_asicFCPortQEgrDropThrSel_get(rtk_uint32 port, rtk_uint32* pIndex) +{ + ret_t retVal; + + + retVal = rtl8373_getAsicRegBits(RTL8373_FC_PORT_EGR_DROP_THR_SET_SEL_ADDR(port), RTL8373_FC_PORT_EGR_DROP_THR_SET_SEL_IDX_MASK(port) , pIndex); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_asicFCPortQEgrDropEn_set + * Description: + * Set port queue egress drop enable + * Input: + * port - 0 ~ 9 + * qid - 0 ~ 7 + * enable - 1: enable 0: disable + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t dal_rtl8373_asicFCPortQEgrDropEn_set(rtk_uint32 port, rtk_uint32 qid, rtk_uint32 enable) +{ + ret_t retVal; + + + retVal = rtl8373_setAsicRegBit(RTL8373_FC_PORT_Q_EGR_DROP_CTRL_SET_ADDR(port, qid) , RTL8373_FC_PORT_Q_EGR_DROP_CTRL_SET_EN_OFFSET(qid) , enable); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + + +/* Function Name: + * dal_rtl8373_asicFCPortQEgrDropEn_get + * Description: + * Get port queue egress drop enable + * Input: + * port - 0 ~ 9 + * qid - 0 ~ 7 + * enable - 1: enable 0: disable + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t dal_rtl8373_asicFCPortQEgrDropEn_get(rtk_uint32 port, rtk_uint32 qid, rtk_uint32* enable) +{ + ret_t retVal; + + + retVal = rtl8373_getAsicRegBit(RTL8373_FC_PORT_Q_EGR_DROP_CTRL_SET_ADDR(port, qid) , RTL8373_FC_PORT_Q_EGR_DROP_CTRL_SET_EN_OFFSET(qid) , enable); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + + +/* Function Name: + * dal_rtl8373_asicFCPortQForceEgrDrop_set + * Description: + * Set port queue force egress drop ability + * Input: + * port - 0 ~ 9 + * qid - 0 ~ 7 + * enable - 1: enable 0: disable + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t dal_rtl8373_asicFCPortQForceEgrDrop_set(rtk_uint32 port, rtk_uint32 qid, rtk_uint32 enable) +{ + ret_t retVal; + + + retVal = rtl8373_setAsicRegBit(RTL8373_FC_PORT_Q_EGR_FORCE_DROP_CTRL_SET_ADDR(port, qid) , RTL8373_FC_PORT_Q_EGR_FORCE_DROP_CTRL_SET_EN_OFFSET(qid) , enable); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_asicFCPortQForceEgrDrop_get + * Description: + * Get port queue force egress drop ability + * Input: + * port - 0 ~ 9 + * qid - 0 ~ 7 + * enable - 1: enable 0: disable + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t dal_rtl8373_asicFCPortQForceEgrDrop_get(rtk_uint32 port, rtk_uint32 qid, rtk_uint32* enable) +{ + ret_t retVal; + + + retVal = rtl8373_getAsicRegBit(RTL8373_FC_PORT_Q_EGR_FORCE_DROP_CTRL_SET_ADDR(port, qid) , RTL8373_FC_PORT_Q_EGR_FORCE_DROP_CTRL_SET_EN_OFFSET(qid) , enable); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + + + diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_fc.h b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_fc.h new file mode 100755 index 00000000..c4b56324 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_fc.h @@ -0,0 +1,758 @@ +#ifndef __DAL_RTL8373_FC_H__ +#define __DAL_RTL8373_FC_H__ + + +/* Function Name: + * dal_rtl8373_asicFCPubPage_set + * Description: + * Set public page number + * Input: + * number - public page number + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +extern ret_t dal_rtl8373_asicFCPubPage_set(rtk_uint32 number); + + + +/* Function Name: + * dal_rtl8373_asicFCPubPage_get + * Description: + * Get public page number + * Input: + * number - public page number + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +extern ret_t dal_rtl8373_asicFCPubPage_get(rtk_uint32* pNumber); + + +/* Function Name: + * dal_rtl8373_asicFCDropAll_set + * Description: + * Set drop all page number + * Input: + * number - drop all page number + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +extern ret_t dal_rtl8373_asicFCDropAll_set(rtk_uint32 number); + + + +/* Function Name: + * dal_rtl8373_asicFCDropAll_get + * Description: + * get drop all page number + * Input: + * number - drop all page number + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +extern ret_t dal_rtl8373_asicFCDropAll_get(rtk_uint32* pNumber); + + + + +/* Function Name: + * dal_rtl8373_asicFCOnHiThr_set + * Description: + * Set flow control on high threshold page number + * Input: + * onNumber - pause on number + * offNumber - pause off number + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +extern ret_t dal_rtl8373_asicFCOnHiThr_set(rtk_uint32 onNumber, rtk_uint32 offNumber); + + +/* Function Name: + * dal_rtl8373_asicFCOnHiThr_get + * Description: + * Get flow control on high threshold page number + * Input: + * onNumber - pause on number + * offNumber - pause off number + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +extern ret_t dal_rtl8373_asicFCOnHiThr_get(rtk_uint32* onNumber, rtk_uint32* offNumber); + + +/* Function Name: + * dal_rtl8373_asicFCOnLoThr_set + * Description: + * Set flow control on low threshold page number + * Input: + * onNumber - pause on number + * offNumber - pause off number + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +extern ret_t dal_rtl8373_asicFCOnLoThr_set(rtk_uint32 onNumber, rtk_uint32 offNumber); + + +/* Function Name: + * dal_rtl8373_asicFCOnLoThr_get + * Description: + * Get flow control on low threshold page number + * Input: + * onNumber - pause on number + * offNumber - pause off number + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +extern ret_t dal_rtl8373_asicFCOnLoThr_get(rtk_uint32* onNumber, rtk_uint32* offNumber); + + + +/* Function Name: + * dal_rtl8373_asicFCOffHiThr_set + * Description: + * Set flow control off high threshold page number + * Input: + * onNumber - pause on number + * offNumber - pause off number + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +extern ret_t dal_rtl8373_asicFCOffHiThr_set(rtk_uint32 onNumber, rtk_uint32 offNumber); + + +/* Function Name: + * dal_rtl8373_asicFCOffHiThr_get + * Description: + * Get flow control off high threshold page number + * Input: + * onNumber - pause on number + * offNumber - pause off number + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +extern ret_t dal_rtl8373_asicFCOffHiThr_get(rtk_uint32* onNumber, rtk_uint32* offNumber); + + + +/* Function Name: + * dal_rtl8373_asicFCOffLoThr_set + * Description: + * Set flow control off low threshold page number + * Input: + * onNumber - pause on number + * offNumber - pause off number + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +extern ret_t dal_rtl8373_asicFCOffLoThr_set(rtk_uint32 onNumber, rtk_uint32 offNumber); + + +/* Function Name: + * dal_rtl8373_asicFCOffLoThr_get + * Description: + * Get flow control off low threshold page number + * Input: + * onNumber - pause on number + * offNumber - pause off number + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +extern ret_t dal_rtl8373_asicFCOffLoThr_get(rtk_uint32* onNumber, rtk_uint32* offNumber); + + + + +/* Function Name: + * dal_rtl8373_asicFCOnPortHiThr_set + * Description: + * Set flow control on high threshold page number + * Input: + * index - 0 ~ 3 + * onNumber - pause on number + * offNumber - pause off number + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +extern ret_t dal_rtl8373_asicFCOnPortHiThr_set(rtk_uint32 index, rtk_uint32 onNumber, rtk_uint32 offNumber); + + +/* Function Name: + * dal_rtl8373_asicFCOnPortHiThr_get + * Description: + * Get flow control on high threshold page number + * Input: + * index - 0 ~ 3 + * onNumber - pause on number + * offNumber - pause off number + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +extern ret_t dal_rtl8373_asicFCOnPortHiThr_get(rtk_uint32 index, rtk_uint32* onNumber, rtk_uint32* offNumber); + + +/* Function Name: + * dal_rtl8373_asicFCOnPortLoThr_set + * Description: + * Set flow control on low threshold page number + * Input: + * index - 0 ~ 3 + * onNumber - pause on number + * offNumber - pause off number + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +extern ret_t dal_rtl8373_asicFCOnPortLoThr_set(rtk_uint32 index, rtk_uint32 onNumber, rtk_uint32 offNumber); + + +/* Function Name: + * dal_rtl8373_asicFCOnPortLoThr_get + * Description: + * Get flow control on low threshold page number + * Input: + * index - 0 ~ 3 + * onNumber - pause on number + * offNumber - pause off number + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +extern ret_t dal_rtl8373_asicFCOnPortLoThr_get(rtk_uint32 index, rtk_uint32* onNumber, rtk_uint32* offNumber); + + + +/* Function Name: + * dal_rtl8373_asicFCOffPortHiThr_set + * Description: + * Set flow control off high threshold page number + * Input: + * index - 0 ~ 3 + * onNumber - pause on number + * offNumber - pause off number + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +extern ret_t dal_rtl8373_asicFCOffPortHiThr_set(rtk_uint32 index, rtk_uint32 onNumber, rtk_uint32 offNumber); + + +/* Function Name: + * dal_rtl8373_asicFCOffPortHiThr_get + * Description: + * Get flow control off high threshold page number + * Input: + * index - 0 ~ 3 + * onNumber - pause on number + * offNumber - pause off number + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +extern ret_t dal_rtl8373_asicFCOffPortHiThr_get(rtk_uint32 index, rtk_uint32* onNumber, rtk_uint32* offNumber); + + + +/* Function Name: + * dal_rtl8373_asicFCOffPortLoThr_set + * Description: + * Set flow control off low threshold page number + * Input: + * index - 0 ~ 3 + * onNumber - pause on number + * offNumber - pause off number + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +extern ret_t dal_rtl8373_asicFCOffPortLoThr_set(rtk_uint32 index, rtk_uint32 onNumber, rtk_uint32 offNumber); + + +/* Function Name: + * dal_rtl8373_asicFCOffPortLoThr_get + * Description: + * Get flow control off low threshold page number + * Input: + * index - 0 ~ 3 + * onNumber - pause on number + * offNumber - pause off number + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +extern ret_t dal_rtl8373_asicFCOffPortLoThr_get(rtk_uint32 index, rtk_uint32* onNumber, rtk_uint32* offNumber); + + + +/* Function Name: + * dal_rtl8373_asicFCPortGua_set + * Description: + * Set port guarantee page + * Input: + * index - 0 ~ 3 + * number - guarantee + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +extern ret_t dal_rtl8373_asicFCPortGua_set(rtk_uint32 index, rtk_uint32 number); + + + + +/* Function Name: + * dal_rtl8373_asicFCPortGua_get + * Description: + * Set port guarantee page + * Input: + * index - 0 ~ 3 + * number - guarantee + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +extern ret_t dal_rtl8373_asicFCPortGua_get(rtk_uint32 index, rtk_uint32* pNumber); + + +/* Function Name: + * dal_rtl8373_asicFCPortThrSel_set + * Description: + * Set port threshold select + * Input: + * port - 0 ~ 9 + * index - 0 ~ 3 + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +extern ret_t dal_rtl8373_asicFCPortThrSel_set(rtk_uint32 port, rtk_uint32 index); + + +/* Function Name: + * dal_rtl8373_asicFCPortThrSel_get + * Description: + * Set port threshold select + * Input: + * port - 0 ~ 9 + * index - 0 ~ 3 + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +extern ret_t dal_rtl8373_asicFCPortThrSel_get(rtk_uint32 port, rtk_uint32* pIndex); + + + +/* Function Name: + * dal_rtl8373_asicFCPortThrSel_set + * Description: + * Set port threshold select + * Input: + * type - 0:unknown unicast 1: l2 multicast 2: broadcast + * enable - 0:disable hol prevention 1: enable hol prevention + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +extern ret_t dal_rtl8373_asicFCHOLPrvnt_set(rtk_uint32 type, rtk_uint32 enable); + + + +/* Function Name: + * dal_rtl8373_asicFCPortThrSel_get + * Description: + * Set port threshold select + * Input: + * type - 0:unknown unicast 1: l2 multicast 2: broadcast + * enable - 0:disable hol prevention 1: enable hol prevention + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +extern ret_t dal_rtl8373_asicFCHOLPrvnt_get(rtk_uint32 type, rtk_uint32* pEnable); + + +/* Function Name: + * dal_rtl8373_asicFCPortHOLPrvntEn_set + * Description: + * Set port threshold select + * Input: + * port - 0 ~ 9 + * enable - 0:disable hol prevention 1: enable hol prevention + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +extern ret_t dal_rtl8373_asicFCPortHOLPrvntEn_set(rtk_uint32 port, rtk_uint32 enable); + + +/* Function Name: + * dal_rtl8373_asicFCPortHOLPrvntEn_get + * Description: + * Get port threshold select + * Input: + * port - 0 ~ 9 + * enable - 0:disable hol prevention 1: enable hol prevention + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +extern ret_t dal_rtl8373_asicFCPortHOLPrvntEn_get(rtk_uint32 port, rtk_uint32* enable); + + + +/* Function Name: + * dal_rtl8373_asicFCPortAct_set + * Description: + * Set port flow control action + * Input: + * portnum - 0 ~ 9 + * act - 0:receive 1: drop + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +extern ret_t dal_rtl8373_asicFCPortAct_set(rtk_uint32 portnum, rtk_uint32 act); + +/* Function Name: + * dal_rtl8373_asicFCPortAct_get + * Description: + * Get port flow control action + * Input: + * portnum - 0 ~ 9 + * act - 0:receive 1: drop + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +extern ret_t dal_rtl8373_asicFCPortAct_get(rtk_uint32 portnum, rtk_uint32* pAct); + + + +/* Function Name: + * dal_rtl8373_asicFCPortAllowPage_set + * Description: + * Set port allow page number + * Input: + * portnum - 0 ~ 9 + * pagenum - allow page number + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +extern ret_t dal_rtl8373_asicFCPortAllowPage_set(rtk_uint32 portnum, rtk_uint32 pagenum); + + + +/* Function Name: + * dal_rtl8373_asicFCPortAllowPage_get + * Description: + * Get port allow page number + * Input: + * portnum - 0 ~ 9 + * pagenum - allow page number + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +extern ret_t dal_rtl8373_asicFCPortAllowPage_get(rtk_uint32 portnum, rtk_uint32* pPagenum); + + +/* Function Name: + * dal_rtl8373_asicFCQEgrDropThr_set + * Description: + * Set flow control on high threshold page number + * Input: + * index - 0 ~ 3 + * queueid - 0 ~ 7 + * onNumber - pause on number + * offNumber - pause off number + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +extern ret_t dal_rtl8373_asicFCQEgrDropThr_set(rtk_uint32 index, rtk_uint32 queueid, rtk_uint32 onNumber, rtk_uint32 offNumber); + + + +/* Function Name: + * dal_rtl8373_asicFCQEgrDropThr_get + * Description: + * Get flow control on high threshold page number + * Input: + * index - 0 ~ 3 + * queueid - 0 ~ 7 + * onNumber - pause on number + * offNumber - pause off number + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +extern ret_t dal_rtl8373_asicFCQEgrDropThr_get(rtk_uint32 index, rtk_uint32 queueid, rtk_uint32* onNumber, rtk_uint32* offNumber); + + +/* Function Name: + * dal_rtl8373_asicFCPortQEgrDropThrSel_set + * Description: + * Select port queue egress drop threshold + * Input: + * port - 0 ~ 9 + * index - 0 ~ 3 + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +extern ret_t dal_rtl8373_asicFCPortQEgrDropThrSel_set(rtk_uint32 port, rtk_uint32 index); + + +/* Function Name: + * dal_rtl8373_asicFCPortQEgrDropThrSel_get + * Description: + * Gelect port queue egress drop threshold + * Input: + * port - 0 ~ 9 + * index - 0 ~ 3 + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +extern ret_t dal_rtl8373_asicFCPortQEgrDropThrSel_get(rtk_uint32 port, rtk_uint32* pIndex); + + +/* Function Name: + * dal_rtl8373_asicFCPortQEgrDropEn_set + * Description: + * Set port queue egress drop enable + * Input: + * port - 0 ~ 9 + * qid - 0 ~ 7 + * enable - 1: enable 0: disable + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +extern ret_t dal_rtl8373_asicFCPortQEgrDropEn_set(rtk_uint32 port, rtk_uint32 qid, rtk_uint32 enable); + + + +/* Function Name: + * dal_rtl8373_asicFCPortQEgrDropEn_get + * Description: + * Get port queue egress drop enable + * Input: + * port - 0 ~ 9 + * qid - 0 ~ 7 + * enable - 1: enable 0: disable + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +extern ret_t dal_rtl8373_asicFCPortQEgrDropEn_get(rtk_uint32 port, rtk_uint32 qid, rtk_uint32* enable); + + + +/* Function Name: + * dal_rtl8373_asicFCPortQForceEgrDrop_set + * Description: + * Set port queue force egress drop ability + * Input: + * port - 0 ~ 9 + * qid - 0 ~ 7 + * enable - 1: enable 0: disable + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +extern ret_t dal_rtl8373_asicFCPortQForceEgrDrop_set(rtk_uint32 port, rtk_uint32 qid, rtk_uint32 enable); + +/* Function Name: + * dal_rtl8373_asicFCPortQForceEgrDrop_get + * Description: + * Get port queue force egress drop ability + * Input: + * port - 0 ~ 9 + * qid - 0 ~ 7 + * enable - 1: enable 0: disable + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +extern ret_t dal_rtl8373_asicFCPortQForceEgrDrop_get(rtk_uint32 port, rtk_uint32 qid, rtk_uint32* enable); + + + + +#endif diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_gpio.c b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_gpio.c new file mode 100755 index 00000000..bf1ece94 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_gpio.c @@ -0,0 +1,503 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8373 + * Feature : Here is a list of all functions and variables in GPIO module. + * + */ + +#include +#include +#include +#include +#include + + + +/* Function Name: + * dal_rtl8373_gpio_muxSel_set + * Description: + * enable gpio pin + * Input: + * gpioNum - GPIO pin number + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RANGE - out of range + * Note: + * + */ +rtk_api_ret_t dal_rtl8373_gpio_muxSel_set(rtk_uint32 gpioNum) +{ + rtk_api_ret_t retVal = 0; + rtk_uint32 val = 0, mask = 0; + + if(gpioNum > GPIO_MAX_PIN_NUM) + return RT_ERR_RANGE; + + if(gpioNum < 30) + { + if((retVal = rtl8373_setAsicRegBit(RTL8373_IO_MUX_SEL_0_ADDR, gpioNum, val)) != RT_ERR_OK) + return retVal; + } + else if (gpioNum == 30) + { + if((retVal = rtl8373_setAsicRegBit(RTL8373_IO_MUX_SEL_2_ADDR, RTL8373_IO_MUX_SEL_2_ACL_BIT3_EN_OFFSET, val)) != RT_ERR_OK) + return retVal; + } + else if (gpioNum == 31 || gpioNum == 32) + { + if((retVal = rtl8373_setAsicRegBits(RTL8373_IO_MUX_SEL_1_ADDR, (RTL8373_IO_MUX_SEL_1_PAD_UART0_SEL_0_MASK | RTL8373_IO_MUX_SEL_1_PAD_UART0_SEL_1_MASK), val)) != RT_ERR_OK) + return retVal; + } + else if (gpioNum >= 33 && gpioNum <= 35 ) + { + if((retVal = rtl8373_setAsicRegBit(RTL8373_IO_MUX_SEL_1_ADDR, (gpioNum - 31), val)) != RT_ERR_OK) + return retVal; + } + else if (gpioNum == 36) + { + if((retVal = rtl8373_setAsicRegBit(RTL8373_IO_MUX_SEL_1_ADDR, RTL8373_IO_MUX_SEL_1_GPIO_PWM_OUT_SEL_OFFSET, 1)) != RT_ERR_OK) + return retVal; + } + else if (gpioNum == 37 || gpioNum == 38) + { + ;//do nothing + } + else if (gpioNum == 39) + { + if((retVal = rtl8373_setAsicRegBit(RTL8373_IO_MUX_SEL_1_ADDR, RTL8373_IO_MUX_SEL_1_GPIO_SDA4_SEL_OFFSET, 1)) != RT_ERR_OK) + return retVal; + } + else if (gpioNum == 40 || gpioNum == 41) + { + if((retVal = rtl8373_setAsicRegBits(RTL8373_IO_MUX_SEL_1_ADDR, (RTL8373_IO_MUX_SEL_1_GPIO_MDX1_SEL_0_MASK | RTL8373_IO_MUX_SEL_1_GPIO_MDX1_SEL_1_MASK), val)) != RT_ERR_OK) + return retVal; + } + else if (gpioNum >= 42 && gpioNum <= 45) + { + if((retVal = rtl8373_setAsicRegBits(RTL8373_INI_MODE_ADDR, RTL8373_INI_MODE_INI_MODE_MASK , val)) != RT_ERR_OK) + return retVal; + } + else if (gpioNum >= 46 && gpioNum <= 51) + { + mask = (0x180 << ((gpioNum-46)*2)); + if((retVal = rtl8373_setAsicRegBits(RTL8373_IO_MUX_SEL_1_ADDR, mask , val)) != RT_ERR_OK) + return retVal; + } + else if (gpioNum >= 52 && gpioNum <= 54) + { + if((retVal = rtl8373_setAsicRegBit(RTL8373_IO_MUX_SEL_2_ADDR, gpioNum -52, val)) != RT_ERR_OK) + return retVal; + } + else if (gpioNum >= 55 && gpioNum <= 60) + { + if((retVal = rtl8373_setAsicRegBit(RTL8373_IO_MUX_SEL_1_ADDR, gpioNum -36, val)) != RT_ERR_OK) + return retVal; + } + else if (gpioNum == 61 || gpioNum == 62) + { + if((retVal = rtl8373_setAsicRegBit(RTL8373_IO_MUX_SEL_1_ADDR, gpioNum -34, val)) != RT_ERR_OK) + return retVal; + } + else//gpio63 + { + if((retVal = rtl8373_setAsicRegBit(RTL8373_IO_MUX_SEL_1_ADDR, RTL8373_IO_MUX_SEL_1_GPIO_MDIO0_SEL_OFFSET, val)) != RT_ERR_OK) + return retVal; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_gpio_muxSel_get + * Description: + * Get gpio pin status + * Input: + * gpioNum - GPIO pin number + * Output: + * *pStatus - status + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RANGE - out of range + * Note: + * + */ +rtk_api_ret_t dal_rtl8373_gpio_muxSel_get(rtk_uint32 gpioNum, rtk_enable_t *pStatus ) +{ + rtk_api_ret_t retVal = 0; + rtk_uint32 val = 0, mask = 0; + + if(gpioNum > GPIO_MAX_PIN_NUM) + return RT_ERR_RANGE; + if(NULL == pStatus) + return RT_ERR_NULL_POINTER; + + + if(gpioNum < 30) + { + if((retVal = rtl8373_getAsicRegBit(RTL8373_IO_MUX_SEL_0_ADDR, gpioNum, &val)) != RT_ERR_OK) + return retVal; + } + else if (gpioNum == 30) + { + if((retVal = rtl8373_getAsicRegBit(RTL8373_IO_MUX_SEL_2_ADDR, RTL8373_IO_MUX_SEL_2_ACL_BIT3_EN_OFFSET, &val)) != RT_ERR_OK) + return retVal; + } + else if (gpioNum == 31 || gpioNum == 32) + { + if((retVal = rtl8373_getAsicRegBits(RTL8373_IO_MUX_SEL_1_ADDR, (RTL8373_IO_MUX_SEL_1_PAD_UART0_SEL_0_MASK | RTL8373_IO_MUX_SEL_1_PAD_UART0_SEL_1_MASK), &val)) != RT_ERR_OK) + return retVal; + } + else if (gpioNum >= 33 && gpioNum <= 35 ) + { + if((retVal = rtl8373_getAsicRegBit(RTL8373_IO_MUX_SEL_1_ADDR, (gpioNum - 31), &val)) != RT_ERR_OK) + return retVal; + } + else if (gpioNum == 36) + { + if((retVal = rtl8373_getAsicRegBit(RTL8373_IO_MUX_SEL_1_ADDR, RTL8373_IO_MUX_SEL_1_GPIO_PWM_OUT_SEL_OFFSET, &val)) != RT_ERR_OK) + return retVal; + } + else if (gpioNum == 37 || gpioNum == 38) + { + val = 0; + } + else if (gpioNum == 39) + { + if((retVal = rtl8373_getAsicRegBit(RTL8373_IO_MUX_SEL_1_ADDR, RTL8373_IO_MUX_SEL_1_GPIO_SDA4_SEL_OFFSET, &val)) != RT_ERR_OK) + return retVal; + } + else if (gpioNum == 40 || gpioNum == 41) + { + if((retVal = rtl8373_getAsicRegBits(RTL8373_IO_MUX_SEL_1_ADDR, (RTL8373_IO_MUX_SEL_1_GPIO_MDX1_SEL_0_MASK | RTL8373_IO_MUX_SEL_1_GPIO_MDX1_SEL_1_MASK), &val)) != RT_ERR_OK) + return retVal; + } + else if (gpioNum >= 42 && gpioNum <= 45) + { + if((retVal = rtl8373_getAsicRegBits(RTL8373_INI_MODE_ADDR, RTL8373_INI_MODE_INI_MODE_MASK , &val)) != RT_ERR_OK) + return retVal; + } + else if (gpioNum >= 46 && gpioNum <= 51) + { + mask = (0x180 << ((gpioNum-46)*2)); + if((retVal = rtl8373_getAsicRegBits(RTL8373_IO_MUX_SEL_1_ADDR, mask , &val)) != RT_ERR_OK) + return retVal; + } + else if (gpioNum >= 52 && gpioNum <= 54) + { + if((retVal = rtl8373_getAsicRegBit(RTL8373_IO_MUX_SEL_2_ADDR, gpioNum -52, &val)) != RT_ERR_OK) + return retVal; + } + else if (gpioNum >= 55 && gpioNum <= 60) + { + if((retVal = rtl8373_getAsicRegBit(RTL8373_IO_MUX_SEL_1_ADDR, gpioNum -36, &val)) != RT_ERR_OK) + return retVal; + } + else if (gpioNum == 61 || gpioNum == 62) + { + if((retVal = rtl8373_getAsicRegBit(RTL8373_IO_MUX_SEL_1_ADDR, gpioNum -34, &val)) != RT_ERR_OK) + return retVal; + } + else//gpio63 + { + if((retVal = rtl8373_getAsicRegBit(RTL8373_IO_MUX_SEL_1_ADDR, RTL8373_IO_MUX_SEL_1_GPIO_MDIO0_SEL_OFFSET, &val)) != RT_ERR_OK) + return retVal; + } + + *pStatus = (rtk_enable_t)val ; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_gpio_groupVal_write + * Description: + * write 32bits gpio pin val + * Input: + * idx - GPIO pin LSB 32bits or MSB 31bits + * val - value + * Output: + * none + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RANGE - out of range + * Note: + * + */ +rtk_api_ret_t dal_rtl8373_gpio_groupVal_write(rtk_gpio_groupReg_t idx, rtk_uint32 val ) +{ + rtk_uint32 regAddr = 0 , retVal = 0; + + if(idx >= GPIO_INOUT_REG_END) + return RT_ERR_RANGE; + + if(idx == GPIO_INOUT_LSB_REG) + regAddr = RTL8373_GPIO_OUT0_ADDR; + else + regAddr = RTL8373_GPIO_OUT1_ADDR; + + if((retVal = rtl8373_setAsicReg(regAddr, val)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_gpio_groupVal_read + * Description: + * Read 32bits gpio pin val + * Input: + * idx - GPIO pin LSB 32bits or MSB 31bits + * Output: + * *pVal - value + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RANGE - out of range + * Note: + * + */ +rtk_api_ret_t dal_rtl8373_gpio_groupVal_read(rtk_gpio_groupReg_t idx, rtk_uint32 *pVal ) +{ + rtk_uint32 regAddr = 0 , retVal = 0; + + if(idx >= GPIO_INOUT_REG_END) + return RT_ERR_RANGE; + if(NULL == pVal) + return RT_ERR_NULL_POINTER; + + if(idx == GPIO_INOUT_LSB_REG) + regAddr = RTL8373_GPIO_IN0_ADDR; + else + regAddr = RTL8373_GPIO_IN1_ADDR; + + if((retVal = rtl8373_getAsicReg(regAddr, pVal)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_gpio_pinVal_write + * Description: + * write gpio pin val + * Input: + * idx - GPIO pin LSB 32bits or MSB 31bits + * val - value + * Output: + * none + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RANGE - out of range + * Note: + * + */ +rtk_api_ret_t dal_rtl8373_gpio_pinVal_write(rtk_uint32 gpioNum, rtk_gpio_level_t val ) +{ + rtk_uint32 regAddr = 0 , retVal = 0, offset = 0; + + if(gpioNum >= GPIO_MAX_PIN_NUM) + return RT_ERR_RANGE; + if(val >= GPIO_LEVEL_END) + return RT_ERR_RANGE; + + if(gpioNum < 32 ) + { + regAddr = RTL8373_GPIO_OUT0_ADDR; + offset = gpioNum; + } + else + { + regAddr = RTL8373_GPIO_OUT1_ADDR; + offset = gpioNum - 32; + } + + if((retVal = rtl8373_setAsicRegBit(regAddr, offset, val)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_gpio_pinVal_read + * Description: + * Read gpio pin val + * Input: + * idx - GPIO pin LSB 32bits or MSB 31bits + * Output: + * *pVal - value + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RANGE - out of range + * Note: + * + */ +rtk_api_ret_t dal_rtl8373_gpio_pinVal_read(rtk_uint32 gpioNum, rtk_gpio_level_t *pVal ) +{ + rtk_uint32 regAddr = 0 , retVal = 0, offset = 0, regVal = 0; + + if(gpioNum >= GPIO_MAX_PIN_NUM) + return RT_ERR_RANGE; + if(NULL == pVal) + return RT_ERR_NULL_POINTER; + + if(gpioNum < 32 ) + { + regAddr = RTL8373_GPIO_IN0_ADDR; + offset = gpioNum; + } + else + { + regAddr = RTL8373_GPIO_IN1_ADDR; + offset = gpioNum - 32; + } + + if((retVal = rtl8373_getAsicRegBit(regAddr, offset, ®Val)) != RT_ERR_OK) + return retVal; + + *pVal = (rtk_gpio_level_t)regVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_gpio_pinDir_set + * Description: + * set gpio pin direction + * Input: + * gpioNum - GPIO pin num + * dir - GPIO pin direction + * Output: + * none + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RANGE - out of range + * Note: + * + */ +rtk_api_ret_t dal_rtl8373_gpio_pinDir_set(rtk_uint32 gpioNum, rtk_gpio_direction_t dir ) +{ + rtk_uint32 regAddr = 0 , retVal = 0, offset = 0; + + if((gpioNum >= GPIO_MAX_PIN_NUM) || (dir>= GPIO_DIR_END)) + return RT_ERR_RANGE; + + if(gpioNum < 32) + { + regAddr = RTL8373_GPIO_OE0_ADDR; + offset = gpioNum; + } + else + { + regAddr = RTL8373_GPIO_OE1_ADDR; + offset = gpioNum - 32; + } + + if((retVal = rtl8373_setAsicRegBit(regAddr, offset, dir)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_gpio_pinDir_get + * Description: + * Get gpio pin direction + * Input: + * gpioNum - GPIO pin num + * Output: + * dir - GPIO pin direction + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RANGE - out of range + * Note: + * + */ +rtk_api_ret_t dal_rtl8373_gpio_pinDir_get(rtk_uint32 gpioNum, rtk_gpio_direction_t *pDir ) +{ + rtk_uint32 regAddr = 0 , retVal = 0, offset = 0, regVal = 0; + + if(gpioNum >= GPIO_MAX_PIN_NUM) + return RT_ERR_RANGE; + if(NULL == pDir) + return RT_ERR_NULL_POINTER; + + if(gpioNum < 32) + { + regAddr = RTL8373_GPIO_OE0_ADDR; + offset = gpioNum; + } + else + { + regAddr = RTL8373_GPIO_OE1_ADDR; + offset = gpioNum - 32; + } + + if((retVal = rtl8373_getAsicRegBit(regAddr, offset, ®Val)) != RT_ERR_OK) + return retVal; + + *pDir = (regVal & 1); + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_gpio_groupDir_get + * Description: + * Get gpio pin direction + * Input: + * idx - GPIO pin LSB 32bits or MSB 31bits + * Output: + * pDirVal - Group GPIO pin direction + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RANGE - out of range + * Note: + * + */ +rtk_api_ret_t dal_rtl8373_gpio_groupDir_get(rtk_gpio_groupReg_t idx, rtk_uint32 *pDirVal ) +{ + rtk_uint32 regAddr = 0 , retVal = 0; + + if(idx >= GPIO_INOUT_REG_END) + return RT_ERR_RANGE; + if(NULL == pDirVal) + return RT_ERR_NULL_POINTER; + + if(idx == GPIO_INOUT_LSB_REG) + { + regAddr = RTL8373_GPIO_OE0_ADDR; + } + else + { + regAddr = RTL8373_GPIO_OE1_ADDR; + } + + if((retVal = rtl8373_getAsicReg(regAddr, pDirVal)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_gpio.h b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_gpio.h new file mode 100755 index 00000000..411799f0 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_gpio.h @@ -0,0 +1,181 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8373 switch high-level API + * + * Feature : The file includes GPIO module high-layer API defination + * + */ + +#ifndef __DAL_RTL8373_GPIO_H__ +#define __DAL_RTL8373_GPIO_H__ +#include + + +/* Function Name: + * dal_rtl8373_gpio_muxSel_set + * Description: + * enable gpio pin + * Input: + * gpioNum - GPIO pin number + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RANGE - out of range + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8373_gpio_muxSel_set(rtk_uint32 gpioNum); + +/* Function Name: + * dal_rtl8373_gpio_muxSel_get + * Description: + * Get gpio pin status + * Input: + * gpioNum - GPIO pin number + * Output: + * *pStatus - status + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RANGE - out of range + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8373_gpio_muxSel_get(rtk_uint32 gpioNum, rtk_enable_t *pStatus ); + +/* Function Name: + * dal_rtl8373_gpio_groupVal_write + * Description: + * write 32bits gpio pin val + * Input: + * idx - GPIO pin LSB 32bits or MSB 31bits + * val - value + * Output: + * none + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RANGE - out of range + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8373_gpio_groupVal_write(rtk_gpio_groupReg_t idx, rtk_uint32 val ); + +/* Function Name: + * dal_rtl8373_gpio_groupVal_read + * Description: + * Read 32bits gpio pin val + * Input: + * idx - GPIO pin LSB 32bits or MSB 31bits + * Output: + * *pVal - value + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RANGE - out of range + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8373_gpio_groupVal_read(rtk_gpio_groupReg_t idx, rtk_uint32 *pVal); + +/* Function Name: + * dal_rtl8373_gpio_pinVal_write + * Description: + * write gpio pin val + * Input: + * idx - GPIO pin LSB 32bits or MSB 31bits + * val - value + * Output: + * none + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RANGE - out of range + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8373_gpio_pinVal_write(rtk_uint32 gpioNum, rtk_gpio_level_t val); + +/* Function Name: + * dal_rtl8373_gpio_pinVal_read + * Description: + * Read gpio pin val + * Input: + * idx - GPIO pin LSB 32bits or MSB 31bits + * Output: + * *pVal - value + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RANGE - out of range + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8373_gpio_pinVal_read(rtk_uint32 gpioNum, rtk_gpio_level_t *pVal); + +/* Function Name: + * dal_rtl8373_gpio_pinDir_set + * Description: + * set gpio pin direction + * Input: + * gpioNum - GPIO pin num + * dir - GPIO pin direction + * Output: + * none + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RANGE - out of range + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8373_gpio_pinDir_set(rtk_uint32 gpioNum, rtk_gpio_direction_t dir ); + +/* Function Name: + * dal_rtl8373_gpio_pinDir_get + * Description: + * Get gpio pin direction + * Input: + * gpioNum - GPIO pin num + * Output: + * dir - GPIO pin direction + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RANGE - out of range + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8373_gpio_pinDir_get(rtk_uint32 gpioNum, rtk_gpio_direction_t *pDir); + +/* Function Name: + * dal_rtl8373_gpio_groupDir_get + * Description: + * Get gpio pin direction + * Input: + * idx - GPIO pin LSB 32bits or MSB 31bits + * Output: + * pDirVal - Group GPIO pin direction + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RANGE - out of range + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8373_gpio_groupDir_get(rtk_gpio_groupReg_t idx, rtk_uint32 *pDirVal); + + +#endif /* __DAL_RTL8373_GPIO_H__ */ + diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_hsb.c b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_hsb.c new file mode 100755 index 00000000..24bfe7b6 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_hsb.c @@ -0,0 +1,823 @@ +/* + * Copyright (C) 2012 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision: $ + * $Date: $ + * + * Purpose : Declaration of HSB/HSA + * + * Feature : The file have include the following module and sub-modules + * 1) HSB, HSA get + * + */ + + +/* + * Include Files + */ +#include +#include +#include +#include + + +static rtk_uint32 _bit_op(rtk_uint32 *pSmiHsbData, rtk_uint32 highBit, rtk_uint32 lowBit) +{ + rtk_uint32 data = 0; + rtk_uint32 bit; + rtk_uint32 i; + rtk_uint32 cnt = 0; + + for (i = lowBit; i <= highBit; i++) + { + bit = ((*(pSmiHsbData + (i/32)) & (0x0001 << (i % 32))) != 0) ? 1 : 0; + data |= (bit <<(cnt)); + + cnt++; + } + + return data; +} + + + + + +ret_t rtl8373_aleLatch_set(hsab_latch_t * latchParam) +{ + rtk_uint32 regData; + ret_t retVal; + + if (NULL == latchParam) + return RT_ERR_NULL_POINTER; + + regData = (latchParam->latch_always & 1) << RTL8373_ITA_HSAB_CTRL_LATCH_ALWAYS_OFFSET; + regData |= (latchParam->latch_first & 1) << RTL8373_ITA_HSAB_CTRL_LATCH_FIRST_OFFSET; + regData |= (latchParam->spa_en & 1) << RTL8373_ITA_HSAB_CTRL_SPA_EN_OFFSET; + regData |= (latchParam->spa & 0xf) << RTL8373_ITA_HSAB_CTRL_SPA_OFFSET; + regData |= (latchParam->fwd_en & 1) << RTL8373_ITA_HSAB_CTRL_FORWARD_EN_OFFSET; + regData |= (latchParam->fwd & 3) << RTL8373_ITA_HSAB_CTRL_FORWARD_OFFSET; + regData |= (latchParam->reason_en & 1) << RTL8373_ITA_HSAB_CTRL_REASON_EN_OFFSET; + regData |= (latchParam->reason & 0x3f) << RTL8373_ITA_HSAB_CTRL_REASON_OFFSET; + + retVal = rtl8373_setAsicReg(RTL8373_ITA_HSAB_CTRL_ADDR, regData); + + return retVal; +} + + +ret_t rtl8373_aleLatch_get(hsab_latch_t * latchParam) +{ + rtk_uint32 regData; + ret_t retVal; + + if (NULL == latchParam) + return RT_ERR_NULL_POINTER; + + retVal = rtl8373_getAsicReg(RTL8373_ITA_HSAB_CTRL_ADDR, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + latchParam->latch_always = (regData >> RTL8373_ITA_HSAB_CTRL_LATCH_ALWAYS_OFFSET) & 1; + latchParam->latch_first = (regData >> RTL8373_ITA_HSAB_CTRL_LATCH_FIRST_OFFSET) & 1; + latchParam->spa_en = (regData >> RTL8373_ITA_HSAB_CTRL_SPA_EN_OFFSET) & 1; + latchParam->spa = (regData >> RTL8373_ITA_HSAB_CTRL_SPA_OFFSET) & 0xf; + latchParam->fwd_en = (regData >> RTL8373_ITA_HSAB_CTRL_FORWARD_EN_OFFSET) & 1; + latchParam->fwd = (regData >> RTL8373_ITA_HSAB_CTRL_FORWARD_OFFSET) & 0x3; + latchParam->reason_en = (regData >> RTL8373_ITA_HSAB_CTRL_REASON_EN_OFFSET) & 1; + latchParam->reason = (regData >> RTL8373_ITA_HSAB_CTRL_REASON_OFFSET) & 0x3f; + + return RT_ERR_OK; + + +} + + + +ret_t rtl8373_aleHsb_get(rtl8373_hsb_t * pHsb) +{ + rtk_uint32 regData, i; + ret_t retVal; + rtk_uint32 * tableAddr; + rtk_uint32 smiHsbData[20]; + + tableAddr = (rtk_uint32 *)smiHsbData; +//read the first 5 32bits + regData = 1 | (0 << RTL8373_ITA_CTRL0_TLB_ACT_OFFSET) | (7 << RTL8373_ITA_CTRL0_TLB_TYPE_OFFSET) | (0 << RTL8373_ITA_CTRL0_TBL_ADDR_OFFSET); + retVal = rtl8373_setAsicReg(RTL8373_ITA_CTRL0_ADDR, regData); + if(retVal != RT_ERR_OK) + return retVal; + + for(i=0; i<5; i++) + { + retVal = rtl8373_getAsicReg(RTL8373_ITA_READ_DATA0_ADDR(i), ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + *tableAddr = regData; + tableAddr++; + } + +//read the second 5 32bits + + regData = 1 | (0 << RTL8373_ITA_CTRL0_TLB_ACT_OFFSET) | (7 << RTL8373_ITA_CTRL0_TLB_TYPE_OFFSET) | (1 << RTL8373_ITA_CTRL0_TBL_ADDR_OFFSET); + retVal = rtl8373_setAsicReg(RTL8373_ITA_CTRL0_ADDR, regData); + if(retVal != RT_ERR_OK) + return retVal; + + for(i=0; i<5; i++) + { + retVal = rtl8373_getAsicReg(RTL8373_ITA_READ_DATA0_ADDR(i), ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + *tableAddr = regData; + tableAddr++; + } + +//read the third 5 32bits + + regData = 1 | (0 << RTL8373_ITA_CTRL0_TLB_ACT_OFFSET) | (7 << RTL8373_ITA_CTRL0_TLB_TYPE_OFFSET) | (2 << RTL8373_ITA_CTRL0_TBL_ADDR_OFFSET); + retVal = rtl8373_setAsicReg(RTL8373_ITA_CTRL0_ADDR, regData); + if(retVal != RT_ERR_OK) + return retVal; + + for(i=0; i<5; i++) + { + retVal = rtl8373_getAsicReg(RTL8373_ITA_READ_DATA0_ADDR(i), ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + *tableAddr = regData; + tableAddr++; + } + +//read the forth 5 32bits + + regData = 1 | (0 << RTL8373_ITA_CTRL0_TLB_ACT_OFFSET) | (7 << RTL8373_ITA_CTRL0_TLB_TYPE_OFFSET) | (3 << RTL8373_ITA_CTRL0_TBL_ADDR_OFFSET); + retVal = rtl8373_setAsicReg(RTL8373_ITA_CTRL0_ADDR, regData); + if(retVal != RT_ERR_OK) + return retVal; + + for(i=0; i<5; i++) + { + retVal = rtl8373_getAsicReg(RTL8373_ITA_READ_DATA0_ADDR(i), ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + *tableAddr = regData; + tableAddr++; + } + + pHsb->pktlen = _bit_op(smiHsbData, 13, 0); + pHsb->dmac[0] = _bit_op(smiHsbData, 61, 54); + pHsb->dmac[1] = _bit_op(smiHsbData, 53, 46); + pHsb->dmac[2] = _bit_op(smiHsbData, 45, 38); + pHsb->dmac[3] = _bit_op(smiHsbData, 37, 30); + pHsb->dmac[4] = _bit_op(smiHsbData, 29, 22); + pHsb->dmac[5] = _bit_op(smiHsbData, 21, 14); + pHsb->smac[0] = _bit_op(smiHsbData, 109, 102); + pHsb->smac[1] = _bit_op(smiHsbData, 101, 94); + pHsb->smac[2] = _bit_op(smiHsbData, 93, 86); + pHsb->smac[3] = _bit_op(smiHsbData, 85, 78); + pHsb->smac[4] = _bit_op(smiHsbData, 77, 70); + pHsb->smac[5] = _bit_op(smiHsbData, 69, 62); + pHsb->cputag_if = _bit_op(smiHsbData, 110, 110); + pHsb->cputag = _bit_op(smiHsbData, 142, 111); + pHsb->stag_if = _bit_op(smiHsbData, 143, 143); + pHsb->stag = _bit_op(smiHsbData, 159, 144); + pHsb->ctag_if = _bit_op(smiHsbData, 160, 160); + pHsb->ctag = _bit_op(smiHsbData, 176, 161); + pHsb->rtag_if = _bit_op(smiHsbData, 177, 177); + pHsb->ethertype = _bit_op(smiHsbData, 193, 178); + pHsb->snap = _bit_op(smiHsbData, 194, 194); + pHsb->pppoe = _bit_op(smiHsbData, 195, 195); + pHsb->rrcp = _bit_op(smiHsbData, 196, 196); + pHsb->rldp = _bit_op(smiHsbData, 197, 197); + pHsb->rlpp = _bit_op(smiHsbData, 198, 198); + pHsb->oam = _bit_op(smiHsbData, 199, 199); + pHsb->arp = _bit_op(smiHsbData, 200, 200); + pHsb->ip_type = _bit_op(smiHsbData, 202, 201); + pHsb->tcp = _bit_op(smiHsbData, 203, 203); + pHsb->udp = _bit_op(smiHsbData, 204, 204); + pHsb->igmp = _bit_op(smiHsbData, 205, 205); + pHsb->icmp = _bit_op(smiHsbData, 206, 206); + pHsb->dip = _bit_op(smiHsbData, 238, 207); + pHsb->sip = _bit_op(smiHsbData, 270, 239); + pHsb->l4_dport = _bit_op(smiHsbData, 286, 271); + pHsb->l4_sport = _bit_op(smiHsbData, 302, 287); + pHsb->tos = _bit_op(smiHsbData, 318, 303); + pHsb->usr0_valid = _bit_op(smiHsbData, 319, 319); + pHsb->usr1_valid = _bit_op(smiHsbData, 320, 320); + pHsb->usr2_valid = _bit_op(smiHsbData, 321, 321); + pHsb->usr3_valid = _bit_op(smiHsbData, 322, 322); + pHsb->usr4_valid = _bit_op(smiHsbData, 323, 323); + pHsb->usr5_valid = _bit_op(smiHsbData, 324, 324); + pHsb->usr6_valid = _bit_op(smiHsbData, 325, 325); + pHsb->usr7_valid = _bit_op(smiHsbData, 326, 326); + pHsb->usr8_valid = _bit_op(smiHsbData, 327, 327); + pHsb->usr9_valid = _bit_op(smiHsbData, 328, 328); + pHsb->usr10_valid = _bit_op(smiHsbData, 329, 329); + pHsb->usr11_valid = _bit_op(smiHsbData, 330, 330); + pHsb->usr12_valid = _bit_op(smiHsbData, 331, 331); + pHsb->usr13_valid = _bit_op(smiHsbData, 332, 332); + pHsb->usr14_valid = _bit_op(smiHsbData, 333, 333); + pHsb->usr15_valid = _bit_op(smiHsbData, 334, 334); + pHsb->usr0_field = _bit_op(smiHsbData, 350, 335); + pHsb->usr1_field = _bit_op(smiHsbData, 366, 351); + pHsb->usr2_field = _bit_op(smiHsbData, 382, 367); + pHsb->usr3_field = _bit_op(smiHsbData, 398, 383); + pHsb->usr4_field = _bit_op(smiHsbData, 414, 399); + pHsb->usr5_field = _bit_op(smiHsbData, 430, 415); + pHsb->usr6_field = _bit_op(smiHsbData, 446, 431); + pHsb->usr7_field = _bit_op(smiHsbData, 462, 447); + pHsb->usr8_field = _bit_op(smiHsbData, 478, 463); + pHsb->usr9_field = _bit_op(smiHsbData, 494, 479); + pHsb->usr10_field = _bit_op(smiHsbData, 510, 495); + pHsb->usr11_field = _bit_op(smiHsbData, 526, 511); + pHsb->usr12_field = _bit_op(smiHsbData, 542, 527); + pHsb->usr13_field = _bit_op(smiHsbData, 558, 543); + pHsb->usr14_field = _bit_op(smiHsbData, 574, 559); + pHsb->usr15_field = _bit_op(smiHsbData, 590, 575); + pHsb->spa = _bit_op(smiHsbData, 594, 591); + pHsb->wol = _bit_op(smiHsbData, 595, 595); + pHsb->l2ptp = _bit_op(smiHsbData, 596, 596); + pHsb->udpptp = _bit_op(smiHsbData, 597, 597); + pHsb->ingr_err = _bit_op(smiHsbData, 598, 598); + pHsb->errpkt = _bit_op(smiHsbData, 599, 599); + pHsb->l3err = _bit_op(smiHsbData, 600, 600); + pHsb->begin_dsc = _bit_op(smiHsbData, 612, 601); + pHsb->end_dsc = _bit_op(smiHsbData, 624, 613); + + return RT_ERR_OK; + +} + + +ret_t rtl8373_aleHsb_display(rtl8373_hsb_t * pHsb) +{ + const char *iptypeString[4] = {"not IP", "IPv4", "Ipv6", "Ipv6 Multicast"}; + + + PRINT("---------------HSB----------------\n\n"); + PRINT("pktlen: %d SPA: %d\n", pHsb->pktlen, pHsb->spa); + PRINT("DA: %2.2X:%2.2X:%2.2X:%2.2X:%2.2X:%2.2X\n", pHsb->dmac[0], pHsb->dmac[1], pHsb->dmac[2], pHsb->dmac[3], pHsb->dmac[4], pHsb->dmac[5]); + PRINT("SA: %2.2X:%2.2X:%2.2X:%2.2X:%2.2X:%2.2X\n", pHsb->smac[0], pHsb->smac[1], pHsb->smac[2], pHsb->smac[3], pHsb->smac[4], pHsb->smac[5]); + + PRINT("CPUTAG_IF: %d ",pHsb->cputag_if); + if(pHsb->cputag_if) + { + PRINT("[%2.2X %2.2X %2.2X %2.2X]\n",((pHsb->cputag >> 24) & 0xFF), ((pHsb->cputag >> 16) & 0xFF), ((pHsb->cputag >> 8) & 0xFF), (pHsb->cputag & 0xFF)); + } + else + PRINT("\n"); + + PRINT("STAG_IF: %d ",pHsb->stag_if); + if(pHsb->stag_if) + { + PRINT("[Pri: %d VID: %d]\n",(pHsb->stag >> 13), pHsb->stag & 0xFFF); + } + else + PRINT("\n"); + + PRINT("CTAG_IF: %d ",pHsb->ctag_if); + if(pHsb->ctag_if) + { + PRINT("[Pri: %d VID: %d]\n",(pHsb->ctag >>13), pHsb->ctag & 0xFFF); + } + else + PRINT("\n"); + + PRINT("RSPAN_IF: %d", pHsb->rtag_if); + if(pHsb->rtag_if) + { + PRINT("[Pri: %d]\n",(pHsb->stag >> 13)); + } + else + PRINT("\n"); + + PRINT("EtherType: %x\n", pHsb->ethertype); + PRINT("SNAP PPPOE RRCP RLDP RLPP OAM ARP TCP UDP ICMP IGMP IP\n"); + PRINT("%-4d %-5d %-4d %-4d %-4d %-3d %-3d %-3d %-3d %-4d %-4d %s\n\n", + pHsb->snap, + pHsb->pppoe, + pHsb->rrcp, + pHsb->rldp, + pHsb->rlpp, + pHsb->oam, + pHsb->arp, + pHsb->tcp, + pHsb->udp, + pHsb->icmp, + pHsb->igmp, + iptypeString[pHsb->ip_type]); + + PRINT("SIP: 0x%x.%x.%x.%x ", ((pHsb->sip >> 24) & 0xFF), ((pHsb->sip >> 16) & 0xFF), ((pHsb->sip >> 8) & 0xFF), (pHsb->sip & 0xFF)); + PRINT("( %d.%d.%d.%d )", ((pHsb->sip >> 24) & 0xFF), ((pHsb->sip >> 16) & 0xFF), ((pHsb->sip >> 8) & 0xFF), (pHsb->sip & 0xFF)); + PRINT("DIP: 0x%x.%x.%x.%x ", ((pHsb->dip >> 24) & 0xFF), ((pHsb->dip >> 16) & 0xFF), ((pHsb->dip >> 8) & 0xFF), (pHsb->dip & 0xFF)); + PRINT("( %d.%d.%d.%d )\n", ((pHsb->dip >> 24) & 0xFF), ((pHsb->dip >> 16) & 0xFF), ((pHsb->dip >> 8) & 0xFF), (pHsb->dip & 0xFF)); + PRINT("TOS: 0x%x ",pHsb->tos); + PRINT("L4 SPORT: 0x%x ",pHsb->l4_sport); + PRINT("L4 DPORT: 0x%x \n",pHsb->l4_dport); + + + PRINT("User: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15\n"); + PRINT(" %-3d %-3d %-3d %-3d %-3d %-3d %-3d %-3d %-3d %-3d %-4d %-4d %-4d %-4d %-4d %-4d\n", + pHsb->usr0_valid,pHsb->usr1_valid,pHsb->usr2_valid,pHsb->usr3_valid,pHsb->usr4_valid,pHsb->usr5_valid, + pHsb->usr6_valid,pHsb->usr7_valid,pHsb->usr8_valid,pHsb->usr9_valid,pHsb->usr10_valid,pHsb->usr11_valid, + pHsb->usr12_valid,pHsb->usr13_valid,pHsb->usr14_valid,pHsb->usr15_valid); + + PRINT(" 0x%4.4X ", pHsb->usr0_field); + PRINT("0x%4.4X ", pHsb->usr1_field); + PRINT("0x%4.4X ", pHsb->usr2_field); + PRINT("0x%4.4X ", pHsb->usr3_field); + PRINT("0x%4.4X ", pHsb->usr4_field); + PRINT("0x%4.4X ", pHsb->usr5_field); + PRINT("0x%4.4X ", pHsb->usr6_field); + PRINT("0x%4.4X\n", pHsb->usr7_field); + PRINT(" 0x%4.4X ", pHsb->usr8_field); + PRINT("0x%4.4X ", pHsb->usr9_field); + PRINT("0x%4.4X ", pHsb->usr10_field); + PRINT("0x%4.4X ", pHsb->usr11_field); + PRINT("0x%4.4X ", pHsb->usr12_field); + PRINT("0x%4.4X ", pHsb->usr13_field); + PRINT("0x%4.4X ", pHsb->usr14_field); + PRINT("0x%4.4X\n", pHsb->usr15_field); + + PRINT("WOL L2PTP UDPPTP INGRERR ERRPKT L3ERR\n"); + PRINT("%-3d %-5d %-6d %-7d %-6d %-5d\n\n", + pHsb->wol, + pHsb->l2ptp, + pHsb->udpptp, + pHsb->ingr_err, + pHsb->errpkt, + pHsb->l3err); + + PRINT("Begin_DSC: %d, End_DSC:%d\n", pHsb->begin_dsc, pHsb->end_dsc); + + return RT_ERR_OK; + +} + + + +#if 0 +ret_t rtl8373_dbg_asicHsb_get(rtl8373_hsb_t * pHsb) +{ + rtk_uint32 regAddr, regData, i; + ret_t retVal; + + retVal = rtl8373_setAsicRegBit(RTL8373_HSB_CTRL_ADDR, RTL8373_HSB_CTRL_READHSB_OFFSET,1); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8373_getAsicRegBit(RTL8373_HSB_CTRL_ADDR, RTL8373_HSB_CTRL_READHSB_OFFSET,®Data); + if(retVal != RT_ERR_OK) + return retVal; + + i = 0; + while(regData & 1) + { + + retVal = rtl8373_getAsicRegBit(RTL8373_HSB_CTRL_ADDR, RTL8373_HSB_CTRL_READHSB_OFFSET,®Data); + if(retVal != RT_ERR_OK) + return retVal; + + i++; + if(i>20) + return RT_ERR_BUSYWAIT_TIMEOUT; + } + + retVal = rtl8373_getAsicReg(RTL8373_HSB_DATA0_ADDR, ®Data); + pHsb->pktlen = regData & RTL8373_HSB_DATA0_PKE_LEN_MASK; + pHsb->dmac[0] = (regData >> RTL8373_HSB_DATA0_DMAC17_0_OFFSET)& 0xff; + pHsb->dmac[1] = (regData >> (RTL8373_HSB_DATA0_DMAC17_0_OFFSET + 8))& 0xff; + pHsb->dmac[2] = (regData >> (RTL8373_HSB_DATA0_DMAC17_0_OFFSET + 16))& 0x3; + + retVal = rtl8373_getAsicReg(RTL8373_HSB_DATA1_ADDR, ®Data); + pHsb->dmac[2] |= (regData & 0x3f) << 2; + pHsb->dmac[3] = (regData >> 6) & 0xff; + pHsb->dmac[4] = (regData >> 14) & 0xff; + pHsb->dmac[5] = (regData >> 22) & 0xff; + pHsb->smac[0] = (regData >> 30) & 0x3; + + retVal = rtl8373_getAsicReg(RTL8373_HSB_DATA2_ADDR, ®Data); + pHsb->smac[0] |= (regData & 0x3f ) << 2; + pHsb->smac[1] = (regData >> 6) & 0xff; + pHsb->smac[2] = (regData >> 14) & 0xff; + pHsb->smac[3] = (regData >> 22) & 0xff; + pHsb->smac[4] = (regData >> 30) & 0x3; + + retVal = rtl8373_getAsicReg(RTL8373_HSB_DATA3_ADDR, ®Data); + pHsb->smac[4] |= (regData & 0x3f ) << 2; + pHsb->smac[5] = (regData >> 6) & 0xff; + pHsb->cputag_if = (regData >> RTL8373_HSB_DATA3_CPUTAG_IF_OFFSET) & 1; + pHsb->cputag = (regData >> RTL8373_HSB_DATA3_CPUTAG16_0_OFFSET) & 0x1ffff; + + retVal = rtl8373_getAsicReg(RTL8373_HSB_DATA4_ADDR, ®Data); + pHsb->cputag |= (regData & RTL8373_HSB_DATA4_CPUTAG31_17_MASK) << 17; + pHsb->stag_if = (regData >> RTL8373_HSB_DATA4_STAG_IF_OFFSET) & 1; + pHsb->stag = (regData >> RTL8373_HSB_DATA4_STAG_OFFSET) & 0xff; + + retVal = rtl8373_getAsicReg(RTL8373_HSB_DATA5_ADDR, ®Data); + pHsb->ctag_if = (regData >> RTL8373_HSB_DATA5_CTAG_IF_OFFSET) & 1; + pHsb->ctag = (regData >> RTL8373_HSB_DATA5_CTAG_OFFSET) & 0xffff; + pHsb->rtag_if = (regData >> RTL8373_HSB_DATA5_RTAG_IF_OFFSET) & 0x1; + pHsb->ethertype = (regData >> RTL8373_HSB_DATA5_ETYPE13_0_OFFSET) & 0x3fff; + + retVal = rtl8373_getAsicReg(RTL8373_HSB_DATA6_ADDR, ®Data); + pHsb->ethertype |= (regData & RTL8373_HSB_DATA6_ETYPE15_14_MASK) << 14; + pHsb->snap = (regData >> RTL8373_HSB_DATA6_SNAP_OFFSET) & 1; + pHsb->pppoe = (regData >> RTL8373_HSB_DATA6_PPPOE_OFFSET) & 1; + pHsb->rrcp = (regData >> RTL8373_HSB_DATA6_RRCP_OFFSET) & 1; + pHsb->rldp = (regData >> RTL8373_HSB_DATA6_RLDP_OFFSET) & 1; + pHsb->rlpp = (regData >> RTL8373_HSB_DATA6_RLPP_OFFSET) & 1; + pHsb->oam = (regData >> RTL8373_HSB_DATA6_OAM_OFFSET) & 1; + pHsb->arp = (regData >> RTL8373_HSB_DATA6_ARP_OFFSET) & 1; + pHsb->ip_type= (regData >> RTL8373_HSB_DATA6_IPTYPE_OFFSET) & 3; + pHsb->tcp = (regData >> RTL8373_HSB_DATA6_TCP_OFFSET) & 1; + pHsb->udp = (regData >> RTL8373_HSB_DATA6_UDP_OFFSET) & 1; + pHsb->icmp = (regData >> RTL8373_HSB_DATA6_ICMP_OFFSET) & 1; + pHsb->igmp = (regData >> RTL8373_HSB_DATA6_IGMP_OFFSET) & 1; + pHsb->dip = (regData >> RTL8373_HSB_DATA6_DIP16_0_OFFSET) & 0x1ffff; + + retVal = rtl8373_getAsicReg(RTL8373_HSB_DATA7_ADDR, ®Data); + pHsb->dip |= (regData & RTL8373_HSB_DATA7_DIP31_17_MASK) << 17; + pHsb->sip = (regData >> RTL8373_HSB_DATA7_SIP16_0_OFFSET) & 0x1ffff; + + retVal = rtl8373_getAsicReg(RTL8373_HSB_DATA8_ADDR, ®Data); + pHsb->sip |= (regData & RTL8373_HSB_DATA8_SIP31_17_MASK) << 17; + pHsb->l4_dport = (regData >> RTL8373_HSB_DATA8_L4DPORT_OFFSET)& 0xffff; + pHsb->l4_sport = (regData >> RTL8373_HSB_DATA8_L4SPORT0_OFFSET)& 0xffff; + + retVal = rtl8373_getAsicReg(RTL8373_HSB_DATA9_ADDR, ®Data); + pHsb->l4_sport |= (regData & RTL8373_HSB_DATA9_L4SPORT15_1_MASK) << 1; + pHsb->tos = (regData >> RTL8373_HSB_DATA9_TOS_OFFSET)& 0xffff; + pHsb->usr0_valid = (regData >> RTL8373_HSB_DATA9_UDV0_OFFSET) & 1; + + retVal = rtl8373_getAsicReg(RTL8373_HSB_DATA10_ADDR, ®Data); + pHsb->usr1_valid = (regData >> RTL8373_HSB_DATA10_UDV1_OFFSET) & 1; + pHsb->usr2_valid = (regData >> RTL8373_HSB_DATA10_UDV2_OFFSET) & 1; + pHsb->usr3_valid = (regData >> RTL8373_HSB_DATA10_UDV3_OFFSET) & 1; + pHsb->usr4_valid = (regData >> RTL8373_HSB_DATA10_UDV4_OFFSET) & 1; + pHsb->usr5_valid = (regData >> RTL8373_HSB_DATA10_UDV5_OFFSET) & 1; + pHsb->usr6_valid = (regData >> RTL8373_HSB_DATA10_UDV6_OFFSET) & 1; + pHsb->usr7_valid = (regData >> RTL8373_HSB_DATA10_UDV7_OFFSET) & 1; + pHsb->usr8_valid = (regData >> RTL8373_HSB_DATA10_UDV8_OFFSET) & 1; + pHsb->usr9_valid = (regData >> RTL8373_HSB_DATA10_UDV9_OFFSET) & 1; + pHsb->usr10_valid = (regData >> RTL8373_HSB_DATA10_UDV10_OFFSET) & 1; + pHsb->usr11_valid = (regData >> RTL8373_HSB_DATA10_UDV11_OFFSET) & 1; + pHsb->usr12_valid = (regData >> RTL8373_HSB_DATA10_UDV12_OFFSET) & 1; + pHsb->usr13_valid = (regData >> RTL8373_HSB_DATA10_UDV13_OFFSET) & 1; + pHsb->usr14_valid = (regData >> RTL8373_HSB_DATA10_UDV14_OFFSET) & 1; + pHsb->usr15_valid = (regData >> RTL8373_HSB_DATA10_UDV15_OFFSET) & 1; + pHsb->usr0_field = (regData >> RTL8373_HSB_DATA10_UDF0_OFFSET) & 0xffff; + pHsb->usr1_field = (regData >> RTL8373_HSB_DATA10_UDF1_0_0_OFFSET) & 1; + + retVal = rtl8373_getAsicReg(RTL8373_HSB_DATA11_ADDR, ®Data); + pHsb->usr1_field |= (regData & RTL8373_HSB_DATA11_UDF1_15_1_MASK) << 1; + pHsb->usr2_field = (regData >> RTL8373_HSB_DATA11_UDF2_OFFSET) & 0xffff; + pHsb->usr3_field = (regData >> RTL8373_HSB_DATA11_UDF3_0_0_OFFSET) & 1; + + retVal = rtl8373_getAsicReg(RTL8373_HSB_DATA12_ADDR, ®Data); + pHsb->usr3_field |= (regData & RTL8373_HSB_DATA12_UDF3_15_1_MASK) << 1; + pHsb->usr4_field = (regData >> RTL8373_HSB_DATA12_UDF4_OFFSET) & 0xffff; + pHsb->usr5_field = (regData >> RTL8373_HSB_DATA12_UDF5_0_0_OFFSET) & 1; + + retVal = rtl8373_getAsicReg(RTL8373_HSB_DATA13_ADDR, ®Data); + pHsb->usr5_field |= (regData & RTL8373_HSB_DATA13_UDF5_15_1_MASK) << 1; + pHsb->usr6_field = (regData >> RTL8373_HSB_DATA13_UDF6_OFFSET) & 0xffff; + pHsb->usr7_field = (regData >> RTL8373_HSB_DATA13_UDF7_0_0_OFFSET) & 1; + + retVal = rtl8373_getAsicReg(RTL8373_HSB_DATA14_ADDR, ®Data); + pHsb->usr7_field |= (regData & RTL8373_HSB_DATA14_UDF7_15_1_MASK) << 1; + pHsb->usr8_field = (regData >> RTL8373_HSB_DATA14_UDF8_OFFSET) & 0xffff; + pHsb->usr9_field = (regData >> RTL8373_HSB_DATA14_UDF9_0_0_OFFSET) & 1; + + retVal = rtl8373_getAsicReg(RTL8373_HSB_DATA15_ADDR, ®Data); + pHsb->usr9_field |= (regData & RTL8373_HSB_DATA15_UDF9_15_1_MASK) << 1; + pHsb->usr10_field = (regData >> RTL8373_HSB_DATA15_UDF10_OFFSET) & 0xffff; + pHsb->usr11_field = (regData >> RTL8373_HSB_DATA15_UDF11_0_0_OFFSET) & 1; + + retVal = rtl8373_getAsicReg(RTL8373_HSB_DATA16_ADDR, ®Data); + pHsb->usr11_field |= (regData & RTL8373_HSB_DATA16_UDF11_15_1_MASK) << 1; + pHsb->usr12_field = (regData >> RTL8373_HSB_DATA16_UDF12_OFFSET) & 0xffff; + pHsb->usr13_field = (regData >> RTL8373_HSB_DATA16_UDF13_0_0_OFFSET) & 1; + + retVal = rtl8373_getAsicReg(RTL8373_HSB_DATA17_ADDR, ®Data); + pHsb->usr13_field |= (regData & RTL8373_HSB_DATA17_UDF13_15_1_MASK) << 1; + pHsb->usr14_field = (regData >> RTL8373_HSB_DATA17_UDF14_OFFSET) & 0xffff; + pHsb->usr15_field = (regData >> RTL8373_HSB_DATA17_UDF15_0_0_OFFSET) & 1; + + retVal = rtl8373_getAsicReg(RTL8373_HSB_DATA18_ADDR, ®Data); + pHsb->usr15_field |= (regData & RTL8373_HSB_DATA18_UDF15_15_1_MASK) << 1; + pHsb->spa = (regData >> RTL8373_HSB_DATA18_RXPORT_OFFSET) & 0xF; + pHsb->wol = (regData >> RTL8373_HSB_DATA18_WOL_OFFSET) & 1; + pHsb->l2ptp= (regData >> RTL8373_HSB_DATA18_L2PTP_OFFSET) & 1; + pHsb->udpptp = (regData >> RTL8373_HSB_DATA18_UDPPTP_OFFSET) & 1; + pHsb->ingr_err= (regData >> RTL8373_HSB_DATA18_INGR_ERR_OFFSET) & 1; + pHsb->errpkt= (regData >> RTL8373_HSB_DATA18_ERRPKT_OFFSET) & 1; + pHsb->l3err= (regData >> RTL8373_HSB_DATA18_L3ERR_OFFSET) & 1; + pHsb->begin_dsc= (regData >> RTL8373_HSB_DATA18_BDSC6_0_OFFSET) & 0x7f; + + retVal = rtl8373_getAsicReg(RTL8373_HSB_DATA19_ADDR, ®Data); + pHsb->begin_dsc |= (regData & RTL8373_HSB_DATA19_BDSC11_7_MASK) << 7; + pHsb->end_dsc = (regData >> RTL8373_HSB_DATA19_EDSC_OFFSET) & 0xfff; + + return RT_ERR_OK; +} + +#endif + +ret_t rtl8373_aleHsa_get(rtl8373_hsa_t * pHsa) +{ + rtk_uint32 regData, i; + ret_t retVal; + rtk_uint32 * tableAddr; + rtk_uint32 smiHsaData[20]; + + tableAddr = (rtk_uint32 *)smiHsaData; +//read the first 5 32bits + regData = 1 | (0 << RTL8373_ITA_CTRL0_TLB_ACT_OFFSET) | (6 << RTL8373_ITA_CTRL0_TLB_TYPE_OFFSET) | (0 << RTL8373_ITA_CTRL0_TBL_ADDR_OFFSET); + retVal = rtl8373_setAsicReg(RTL8373_ITA_CTRL0_ADDR, regData); + if(retVal != RT_ERR_OK) + return retVal; + + for(i=0; i<5; i++) + { + retVal = rtl8373_getAsicReg(RTL8373_ITA_READ_DATA0_ADDR(i), ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + *tableAddr = regData; + tableAddr++; + } + +//read the second 5 32bits + + regData = 1 | (0 << RTL8373_ITA_CTRL0_TLB_ACT_OFFSET) | (6 << RTL8373_ITA_CTRL0_TLB_TYPE_OFFSET) | (1 << RTL8373_ITA_CTRL0_TBL_ADDR_OFFSET); + retVal = rtl8373_setAsicReg(RTL8373_ITA_CTRL0_ADDR, regData); + if(retVal != RT_ERR_OK) + return retVal; + + for(i=0; i<5; i++) + { + retVal = rtl8373_getAsicReg(RTL8373_ITA_READ_DATA0_ADDR(i), ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + *tableAddr = regData; + tableAddr++; + } + + + + pHsa->pktlen = _bit_op(smiHsaData, 151, 138); + pHsa->dpm0 = _bit_op(smiHsaData, 156, 155); + pHsa->dpm1 = _bit_op(smiHsaData, 158, 157); + pHsa->dpm2 = _bit_op(smiHsaData, 160, 159); + pHsa->dpm3 = _bit_op(smiHsaData, 162, 161); + pHsa->dpm4 = _bit_op(smiHsaData, 164, 163); + pHsa->dpm5 = _bit_op(smiHsaData, 166, 165); + pHsa->dpm6 = _bit_op(smiHsaData, 168, 167); + pHsa->dpm7 = _bit_op(smiHsaData, 170, 169); + pHsa->dpm8 = _bit_op(smiHsaData, 172, 171); + pHsa->dpm9 = _bit_op(smiHsaData, 174, 173); + pHsa->trappkt = _bit_op(smiHsaData, 90, 90); + pHsa->rfc1024 = _bit_op(smiHsaData, 74, 74); + //pHsa->llcother_if = _bit_op(smiHsaData, 128, 128); + pHsa->pppoe_if = _bit_op(smiHsaData, 73, 73); + pHsa->l3fmt = _bit_op(smiHsaData, 121, 120); + pHsa->acl_dscprmk_en= _bit_op(smiHsaData, 67, 67); + pHsa->dscp_1p = _bit_op(smiHsaData, 66, 61); + pHsa->acl_1prmk_en = _bit_op(smiHsaData, 68, 68); + pHsa->internal_pri = _bit_op(smiHsaData, 231, 229); + pHsa->user_pri0 = _bit_op(smiHsaData, 20, 18); + pHsa->user_pri1 = _bit_op(smiHsaData, 23, 21); + pHsa->user_pri2 = _bit_op(smiHsaData, 26, 24); + pHsa->user_pri3 = _bit_op(smiHsaData, 29, 27); + pHsa->user_pri4 = _bit_op(smiHsaData, 32, 30); + pHsa->user_pri5 = _bit_op(smiHsaData, 35, 33); + pHsa->user_pri6 = _bit_op(smiHsaData, 38, 36); + pHsa->user_pri7 = _bit_op(smiHsaData, 41, 39); + pHsa->user_pri8 = _bit_op(smiHsaData, 44, 42); + pHsa->user_pri9 = _bit_op(smiHsaData, 47, 45); + //pHsa->ingress_cpri = _bit_op(smiHsaData, 20, 18); + pHsa->cvid_en = _bit_op(smiHsaData, 60, 60); + pHsa->ctag_if = _bit_op(smiHsaData, 5, 5); + pHsa->cvid_if = _bit_op(smiHsaData, 71, 71); + pHsa->cvid = _bit_op(smiHsaData, 59, 48); + pHsa->cvlan_untagset= _bit_op(smiHsaData, 15, 6); + //pHsa->cvid_zero = _bit_op(smiHsaData, 97, 97); + pHsa->cfmt_en = _bit_op(smiHsaData, 119, 119); + pHsa->cfmt = _bit_op(smiHsaData, 118, 117); + pHsa->ctag_act = _bit_op(smiHsaData, 17, 16); + pHsa->ingress_ctag = _bit_op(smiHsaData, 137, 122); + pHsa->stag_if = _bit_op(smiHsaData, 72, 72); + pHsa->svid = _bit_op(smiHsaData, 89, 78); + pHsa->spri = _bit_op(smiHsaData, 77, 75); + pHsa->svlan_untag = _bit_op(smiHsaData, 116, 107); + pHsa->ingress_stag = _bit_op(smiHsaData, 106, 91); + pHsa->keep = _bit_op(smiHsaData, 69, 69); + pHsa->cputag_if = _bit_op(smiHsaData, 70, 70); + pHsa->qid0 = _bit_op(smiHsaData, 189, 187); + pHsa->qid1 = _bit_op(smiHsaData, 192, 190); + pHsa->qid2 = _bit_op(smiHsaData, 195, 193); + pHsa->qid3 = _bit_op(smiHsaData, 198, 196); + pHsa->qid4 = _bit_op(smiHsaData, 201, 199); + pHsa->qid5 = _bit_op(smiHsaData, 204, 202); + pHsa->qid6 = _bit_op(smiHsaData, 207, 205); + pHsa->qid7 = _bit_op(smiHsaData, 210, 208); + pHsa->qid8 = _bit_op(smiHsaData, 213, 211); + pHsa->qid9 = _bit_op(smiHsaData, 216, 214); + pHsa->rspan = _bit_op(smiHsaData, 0, 0); + pHsa->spa = _bit_op(smiHsaData, 4, 1); + pHsa->begin_dsc = _bit_op(smiHsaData, 228, 217); + pHsa->end_dsc = _bit_op(smiHsaData, 186, 175); + pHsa->pg_id = _bit_op(smiHsaData, 154, 152); + + pHsa->reason = _bit_op(smiHsaData, 239, 232); + + return RT_ERR_OK; + +} + + + +ret_t rtl8373_aleHsa_display(rtl8373_hsa_t *hsa) +{ + rtk_uint8 tmp; + const char *dpmString[4] = { + + "No", + "Tx", + "Rx", + "FWD", + }; + + + const char *reasonString[RTL8373_REASON_NUMBER] = { + + "Fwd", + "l2 ingress/crcerr", + "StormControl", + "hash full", + "cvlan efilter", + "--", + "cvlan ifilter", + "svlan ifilter", + "VS_UNTAG", + "svlan UIFSEG/efilter", + "port maclimit", + "sys maclimit", + "fld brdcast", + "fld unknmul", + "fld unknuni", + "--", + "unkn uni", + "unkn l2multi", + "unkn v4multi", + "unkn v6multi", + "newsa", + "unmatchsa", + "igmp/mld", + "port_igmp", + "igmp chkerr", + "igmp reportspr", + "igmp leavespr", + "igmp tblfull", + "zero leave", + "dos", + "vlan accepttype", + "rma", + "rspan", + "--", + "ingr bandwith", + "PFC", + "PTP", + "acl unmatch", + "acl policing", + "acl trap", + "hash redir/mir", + "dot1x ingress", + "dot1x egress", + "guset op", + "stp ingress", + "stp egress", + "trunk", + "port isolation", + "wol", + "srcport filter", + "other RLDP", + "RRCP", + "--", + "RLPP", + "RLDP", + "LLDP", + "cputag force", + "pmirror iso", + "--", + "--", + "diff speed", + "egress drop", + "force", + "linkdown", + + }; + + PRINT("---------------HSA----------------\n"); + PRINT("PKTLEN: %d\n", hsa->pktlen); + PRINT("SPA: %d\n\n", hsa->spa); + + PRINT("DPM: 0 1 2 3 4 5 6 7 8 9\n"); + PRINT(" %-4s %-4s %-4s %-4s %-4s %-4s %-4s %-4s %-4s %-4s\n", + dpmString[hsa->dpm0], + dpmString[hsa->dpm1], + dpmString[hsa->dpm2], + dpmString[hsa->dpm3], + dpmString[hsa->dpm4], + dpmString[hsa->dpm5], + dpmString[hsa->dpm6], + dpmString[hsa->dpm7], + dpmString[hsa->dpm8], + dpmString[hsa->dpm9]); + + PRINT("CVLAN: CTAGIF UNTAGSET ACT CPRI CVID CVIDEN CVIDIF CFMT CFMTEN\n"); + PRINT(" %-6d ",hsa->ctag_if); + + PRINT("%-11d ",hsa->cvlan_untagset); + + PRINT("%-3d ",hsa->ctag_act); + + tmp = (hsa->ingress_ctag >> 13) & 0x7; + PRINT("%-4d %-4d %-6d %-6d %-4d %d\n", + tmp, + hsa->cvid, + hsa->cvid_en, + hsa->cvid_if, + hsa->cfmt, + hsa->cfmt_en); + + PRINT("SVLAN: IF SVID SPRI IgrStag SvlanUtag\n"); + PRINT(" %-2d %-4d %-4d ", + hsa->stag_if, + hsa->svid, + hsa->spri); + + PRINT("0x%-5x ", hsa->ingress_stag); + + PRINT("%-11d\n",hsa->svlan_untag); + + PRINT("REM_1Q_EN REM_DSCP_EN REM_PRI_DSCP\n"); + PRINT("%-9d %-11d %d\n", + hsa->acl_1prmk_en, + hsa->acl_dscprmk_en, + hsa->dscp_1p); + + PRINT("KEEP REGEN_CRC PPPOE SNAP RSPAN LLCOTHER TRAP CVID_ZERO\n"); + PRINT("%-4d %-9d %-5d %-4d %-5d %-4d\n", + hsa->keep, + hsa->cputag_if, + hsa->pppoe_if, + hsa->rfc1024, + hsa->rspan, + hsa->trappkt); + + PRINT("IntPri: %d\n",hsa->internal_pri); + PRINT("PORT No. 0 1 2 3 4 5 6 7 8 9\n"); + PRINT("USER PRI: "); + + PRINT("%-3d%-3d%-3d%-3d%-3d%-3d%-3d%-3d%-3d%-3d\n", + hsa->user_pri0, hsa->user_pri1, hsa->user_pri2, hsa->user_pri3, + hsa->user_pri4, hsa->user_pri5, hsa->user_pri6, hsa->user_pri7, hsa->user_pri8, hsa->user_pri9); + + PRINT("QID: "); + PRINT("%-3d%-3d%-3d%-3d%-3d%-3d%-3d%-3d%-3d%-3d\n\n", hsa->qid0, hsa->qid1, hsa->qid2, hsa->qid3, hsa->qid4, hsa->qid5, hsa->qid6, hsa->qid7, hsa->qid8, hsa->qid9); + + PRINT("PG_ID : %d\n", hsa->pg_id); + + if(hsa->reason & 0x80) + PRINT("packet is DROP !!!!!!!\n"); + else if(hsa->reason & 0x40) + PRINT("packet is TRAP !!!!!!!\n"); + + tmp = hsa->reason & 0x3f; + PRINT("reason is : %s\n", reasonString[tmp]); + + PRINT("reason whole value 0x%x\n", hsa->reason); + + return RT_ERR_OK; +} + + + + + diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_hsb.h b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_hsb.h new file mode 100755 index 00000000..7cefca0c --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_hsb.h @@ -0,0 +1,192 @@ +#ifndef __DAL_RTL8373_HSB_H__ +#define __DAL_RTL8373_HSB_H__ + + + +#define RTL8373_REASON_NUMBER 0x40 + +typedef struct hsab_latch_s{ + rtk_uint8 latch_always; + rtk_uint8 latch_first; + rtk_uint8 spa_en; + rtk_uint8 spa; + rtk_uint8 fwd_en; + rtk_uint8 fwd; + rtk_uint8 reason_en; + rtk_uint8 reason; + +}hsab_latch_t; + + +typedef struct rtl8373_hsb_s{ + + rtk_uint16 pktlen; + rtk_uint8 dmac[6]; + rtk_uint8 smac[6]; + rtk_uint8 cputag_if; + rtk_uint32 cputag; + rtk_uint8 stag_if; + rtk_uint16 stag; + rtk_uint8 ctag_if; + rtk_uint16 ctag; + rtk_uint8 rtag_if; + rtk_uint16 ethertype; + rtk_uint8 snap; + rtk_uint8 pppoe; + rtk_uint8 rrcp; + rtk_uint8 rldp; + rtk_uint8 rlpp; + rtk_uint8 oam; + rtk_uint8 arp; + rtk_uint8 ip_type; + rtk_uint8 tcp; + rtk_uint8 udp; + rtk_uint8 igmp; + rtk_uint8 icmp; + rtk_uint32 dip; + rtk_uint32 sip; + rtk_uint16 l4_dport; + rtk_uint16 l4_sport; + rtk_uint16 tos; + rtk_uint8 usr0_valid; + rtk_uint8 usr1_valid; + rtk_uint8 usr2_valid; + rtk_uint8 usr3_valid; + rtk_uint8 usr4_valid; + rtk_uint8 usr5_valid; + rtk_uint8 usr6_valid; + rtk_uint8 usr7_valid; + rtk_uint8 usr8_valid; + rtk_uint8 usr9_valid; + rtk_uint8 usr10_valid; + rtk_uint8 usr11_valid; + rtk_uint8 usr12_valid; + rtk_uint8 usr13_valid; + rtk_uint8 usr14_valid; + rtk_uint8 usr15_valid; + rtk_uint16 usr0_field; + rtk_uint16 usr1_field; + rtk_uint16 usr2_field; + rtk_uint16 usr3_field; + rtk_uint16 usr4_field; + rtk_uint16 usr5_field; + rtk_uint16 usr6_field; + rtk_uint16 usr7_field; + rtk_uint16 usr8_field; + rtk_uint16 usr9_field; + rtk_uint16 usr10_field; + rtk_uint16 usr11_field; + rtk_uint16 usr12_field; + rtk_uint16 usr13_field; + rtk_uint16 usr14_field; + rtk_uint16 usr15_field; + rtk_uint8 spa; + rtk_uint8 wol; + rtk_uint8 l2ptp; + rtk_uint8 udpptp; + rtk_uint8 ingr_err; + rtk_uint8 errpkt; + rtk_uint8 l3err; + rtk_uint16 begin_dsc; + rtk_uint16 end_dsc; + +}rtl8373_hsb_t; + + + +typedef struct rtl8373_hsa_s +{ + rtk_uint16 pktlen; + rtk_uint8 dpm0; + rtk_uint8 dpm1; + rtk_uint8 dpm2; + rtk_uint8 dpm3; + rtk_uint8 dpm4; + rtk_uint8 dpm5; + rtk_uint8 dpm6; + rtk_uint8 dpm7; + rtk_uint8 dpm8; + rtk_uint8 dpm9; + rtk_uint8 trappkt; + rtk_uint8 rfc1024; + rtk_uint8 llcother_if; + rtk_uint8 pppoe_if; + rtk_uint8 l3fmt; + + rtk_uint8 acl_dscprmk_en; + rtk_uint8 acl_1prmk_en; + rtk_uint8 dscp_1p; + rtk_uint8 internal_pri; + rtk_uint8 user_pri0; + rtk_uint8 user_pri1; + rtk_uint8 user_pri2; + rtk_uint8 user_pri3; + rtk_uint8 user_pri4; + rtk_uint8 user_pri5; + rtk_uint8 user_pri6; + rtk_uint8 user_pri7; + rtk_uint8 user_pri8; + rtk_uint8 user_pri9; + rtk_uint8 ingress_cpri; + + rtk_uint8 cvid_en; + rtk_uint8 ctag_if; + rtk_uint8 cvid_if; + rtk_uint16 cvid; + rtk_uint16 cvlan_untagset; + rtk_uint8 cvid_zero; + rtk_uint8 cfmt_en; + rtk_uint8 cfmt; + rtk_uint8 ctag_act; + rtk_uint16 ingress_ctag; + + rtk_uint8 stag_if; + rtk_uint16 svid; + rtk_uint8 spri; + rtk_uint16 svlan_untag; + rtk_uint8 ingress_stag; + + rtk_uint8 keep; + rtk_uint8 cputag_if; + rtk_uint8 qid0; + rtk_uint8 qid1; + rtk_uint8 qid2; + rtk_uint8 qid3; + rtk_uint8 qid4; + rtk_uint8 qid5; + rtk_uint8 qid6; + rtk_uint8 qid7; + rtk_uint8 qid8; + rtk_uint8 qid9; + rtk_uint8 qid10; + rtk_uint8 qid11; + rtk_uint8 qid12; + rtk_uint8 qid13; + rtk_uint8 qid14; + rtk_uint8 qid15; + + rtk_uint8 rspan; + + + rtk_uint8 spa; + rtk_uint16 end_dsc; + rtk_uint16 begin_dsc; + rtk_uint8 pg_id; + + rtk_uint8 reason; + +} rtl8373_hsa_t; + + +extern ret_t rtl8373_aleLatch_set(hsab_latch_t * latchParam); +extern ret_t rtl8373_aleLatch_get(hsab_latch_t * latchParam); +extern ret_t rtl8373_aleHsb_get(rtl8373_hsb_t * pHsb); +extern ret_t rtl8373_aleHsb_display(rtl8373_hsb_t * pHsb); +extern ret_t rtl8373_aleHsa_get(rtl8373_hsa_t * pHsa); +extern ret_t rtl8373_aleHsa_display(rtl8373_hsa_t *hsa); + + + + + +#endif diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_i2c.c b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_i2c.c new file mode 100755 index 00000000..0156a4ed --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_i2c.c @@ -0,0 +1,439 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8373 + * Feature : Here is a list of all functions and variables in I2C module. + * + */ + +#include +#include +#include +#include +#include + +/* Function Name: + * dal_rtl8373_i2c_init + * Description: + * initial i2c config + * Input: + * clkRate - I2C SCL clock rate + * deviceAddr - I2C slave device address + * Output: + * none + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RANGE - out of range + * Note: + * + */ +rtk_api_ret_t dal_rtl8373_i2c_init(rtk_i2c_sclClockRate_t clkRate, rtk_uint32 deviceAddr) +{ + rtk_uint32 retVal = 0; + + if((clkRate >= I2C_SCL_CLK_END) || (deviceAddr >= 0x80)) + return RT_ERR_INPUT; + + /* set i2c clk rate */ + if((retVal = rtl8373_setAsicRegBits(RTL8373_I2C_MST1_CTRL2_ADDR, RTL8373_I2C_MST1_CTRL2_SCL_FREQ_MASK, (rtk_uint32)clkRate)) != RT_ERR_OK) + return retVal; + + /* set device addr */ + if((retVal = rtl8373_setAsicRegBits(RTL8373_I2C_MST1_CTRL1_ADDR, RTL8373_I2C_MST1_CTRL1_DEV_ADDR_MASK, deviceAddr)) != RT_ERR_OK) + return retVal; + + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_i2c_readMode_set + * Description: + * set i2c read mode + * Input: + * mode - standard mode or old mode + * Output: + * none + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RANGE - out of range + * Note: + * + */ +rtk_api_ret_t dal_rtl8373_i2c_readMode_set(rtk_i2c_readMode_t mode) +{ + rtk_uint32 retVal = 0; + if(mode >= I2C_READ_MODE_END) + return RT_ERR_RANGE; + + if((retVal = rtl8373_setAsicRegBit(RTL8373_I2C_MST1_CTRL1_ADDR, RTL8373_I2C_MST1_CTRL1_READ_MODE_OFFSET, mode)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; + +} + +/* Function Name: + * dal_rtl8373_i2c_readMode_get + * Description: + * get i2c read mode + * Input: + * none + * Output: + * pMode - standard mode or old mode + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RANGE - out of range + * Note: + * + */ +rtk_api_ret_t dal_rtl8373_i2c_readMode_get(rtk_i2c_readMode_t *pMode) +{ + rtk_uint32 retVal = 0, regVal = 0; + if(pMode == NULL) + return RT_ERR_NULL_POINTER; + + if((retVal = rtl8373_getAsicRegBit(RTL8373_I2C_MST1_CTRL1_ADDR, RTL8373_I2C_MST1_CTRL1_READ_MODE_OFFSET, ®Val)) != RT_ERR_OK) + return retVal; + + *pMode = (rtk_i2c_readMode_t)(regVal & 0x1); + + return RT_ERR_OK; + +} + + +/* Function Name: + * dal_rtl8373_i2c_gpioPinGroup_set + * Description: + * config i2c scl and sda used gpio pin + * Input: + * sclNum - scl pad num + * sdaNum - sda pad num + * Output: + * none + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RANGE - out of range + * Note: + * + */ +rtk_api_ret_t dal_rtl8373_i2c_gpioPinGroup_set(rtk_uint32 sclNum, rtk_uint32 sdaNum ) +{ + rtk_uint32 retVal = 0, mask = 0; + + if((sclNum > I2C_GROUP_NUM) || (sdaNum > I2C_GROUP_NUM) || (sclNum == 4)) + return RT_ERR_RANGE; + + if((retVal = rtl8373_setAsicRegBits(RTL8373_I2C_MST1_CTRL1_ADDR, RTL8373_I2C_MST1_CTRL1_SCL_OUT_SEL_MASK, sclNum)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8373_setAsicRegBits(RTL8373_I2C_MST1_CTRL1_ADDR, RTL8373_I2C_MST1_CTRL1_SDA_OUT_SEL_MASK, sdaNum)) != RT_ERR_OK) + return retVal; + + /*config gpio pin to scl function*/ + if(sclNum < 3) + { + mask = (0x180 << (sclNum *4)); + if((retVal = rtl8373_setAsicRegBits(RTL8373_IO_MUX_SEL_1_ADDR, mask, 1)) != RT_ERR_OK) + return retVal; + } + else if(sclNum == 3) + { + if((retVal = rtl8373_setAsicRegBits(RTL8373_IO_MUX_SEL_1_ADDR, RTL8373_IO_MUX_SEL_1_GPIO_MDX1_SEL_1_MASK|RTL8373_IO_MUX_SEL_1_GPIO_MDX1_SEL_0_MASK, 2)) != RT_ERR_OK) + return retVal; + } + else //sclNum=5 + { + if((retVal = rtl8373_setAsicRegBit(RTL8373_MAC_IF_CTRL_ADDR, RTL8373_MAC_IF_CTRL_DW8051_INDIRECT_EE_EN_OFFSET, 1)) != RT_ERR_OK) + return retVal; + } + + /*config gpio pin to sda function*/ + if(sdaNum < 3) + { + mask = (0x600 << (sdaNum *4)); + if((retVal = rtl8373_setAsicRegBits(RTL8373_IO_MUX_SEL_1_ADDR, mask , 1)) != RT_ERR_OK) + return retVal; + } + else if(sdaNum == 3) + { + if((retVal = rtl8373_setAsicRegBits(RTL8373_IO_MUX_SEL_1_ADDR, RTL8373_IO_MUX_SEL_1_GPIO_MDX1_SEL_1_MASK|RTL8373_IO_MUX_SEL_1_GPIO_MDX1_SEL_0_MASK, 2)) != RT_ERR_OK) + return retVal; + } + else if(sdaNum == 4) + { + if((retVal = rtl8373_setAsicRegBit(RTL8373_IO_MUX_SEL_1_ADDR, RTL8373_IO_MUX_SEL_1_GPIO_SDA4_SEL_OFFSET, 0)) != RT_ERR_OK) + return retVal; + } + else //sdaNum=5 + { + if((retVal = rtl8373_setAsicRegBit(RTL8373_MAC_IF_CTRL_ADDR, RTL8373_MAC_IF_CTRL_DW8051_INDIRECT_EE_EN_OFFSET, 1)) != RT_ERR_OK) + return retVal; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_i2c_gpioPinGroup_get + * Description: + * config i2c scl and sda used gpio pin + * Input: + * none + * Output: + * pSclNum - scl pad num + * pSdaNum - sda pad num + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RANGE - out of range + * Note: + * + */ +rtk_api_ret_t dal_rtl8373_i2c_gpioPinGroup_get(rtk_uint32 *pSclNum, rtk_uint32 *pSdaNum ) +{ + rtk_uint32 retVal = 0; + + if((pSdaNum == NULL) || (pSclNum == NULL)) + return RT_ERR_NULL_POINTER; + + if((retVal = rtl8373_getAsicRegBits(RTL8373_I2C_MST1_CTRL1_ADDR, RTL8373_I2C_MST1_CTRL1_SCL_OUT_SEL_MASK, pSclNum)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8373_getAsicRegBits(RTL8373_I2C_MST1_CTRL1_ADDR, RTL8373_I2C_MST1_CTRL1_SDA_OUT_SEL_MASK, pSdaNum)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_i2c_data_read + * Description: + * i2c master read slave device data + * Input: + * memAddr - slave device memory address + * dataWidth - want to read data width(1~16) + * memAddrWidth - slave device memory address width(0~3) + * Output: + * pReadData - slave device data that has read + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RANGE - out of range + * Note: + * + */ +rtk_api_ret_t dal_rtl8373_i2c_data_read(rtk_uint32 memAddr, rtk_uint32 dataWidth, rtk_uint32 memAddrWidth, rtk_uint32 *pReadData) +{ + rtk_uint32 retVal = 0, mask = 0, mem_Addr = 0, tmpVal = 0, regVal = 0, i2cFail = 0; + rtk_uint32 tmpData = 0, baseAddr = 0; + + if(pReadData == NULL) + return RT_ERR_NULL_POINTER; + + if((memAddrWidth > I2C_MEM_ADDR_WIDTH_MAX) || (dataWidth > I2C_DATA_WIDTH_MAX)) + return RT_ERR_INPUT; + + /*set memory address*/ + mask = 1 << (8 * memAddrWidth); + mask = mask - 1; + + mem_Addr = memAddr & mask; + if((retVal = rtl8373_setAsicRegBits(RTL8373_I2C_MST1_MEMADDR_CTRL_ADDR, RTL8373_I2C_MST1_MEMADDR_CTRL_MEM_ADDR_MASK, mem_Addr)) != RT_ERR_OK) + return retVal; + + /*set dataWidth + memAddrWidth*/ + tmpVal = (memAddrWidth << 4) | (dataWidth-1); + + if((retVal = rtl8373_setAsicRegBits(RTL8373_I2C_MST1_CTRL1_ADDR, RTL8373_I2C_MST1_CTRL1_DATA_WIDTH_MASK|RTL8373_I2C_MST1_CTRL1_MEM_ADDR_WIDTH_MASK, tmpVal)) != RT_ERR_OK) + return retVal; + + /*set read operation*/ + if((retVal = rtl8373_setAsicRegBit(RTL8373_I2C_MST1_CTRL1_ADDR, RTL8373_I2C_MST1_CTRL1_RWOP_OFFSET, I2C_RW_OP_READ)) != RT_ERR_OK) + return retVal; + + + /*trigger read, and wait finished*/ + if((retVal = rtl8373_setAsicRegBit(RTL8373_I2C_MST1_CTRL1_ADDR, RTL8373_I2C_MST1_CTRL1_I2C_TRIG_OFFSET, I2C_RW_ACT_TRIGGER)) != RT_ERR_OK) + return retVal; + do{ + if((retVal = rtl8373_getAsicRegBit(RTL8373_I2C_MST1_CTRL1_ADDR, RTL8373_I2C_MST1_CTRL1_I2C_TRIG_OFFSET, ®Val)) != RT_ERR_OK) + return retVal; + }while(regVal); + + + /*check i2c react fail or not*/ + if((retVal = rtl8373_getAsicRegBit(RTL8373_I2C_MST1_CTRL1_ADDR, RTL8373_I2C_MST1_CTRL1_I2C_FAIL_OFFSET, &i2cFail)) != RT_ERR_OK) + return retVal; + + if(i2cFail == 0) + { + baseAddr = RTL8373_I2C_MST1_DATA_CTRL_ADDR(0); + if((retVal = rtl8373_getAsicReg(baseAddr, &tmpData)) != RT_ERR_OK) + return retVal; + if(dataWidth <4) + { + mask = (1 << (8 * (dataWidth))) -1; + *pReadData = mask & tmpData; + } + else + *pReadData = tmpData; + + if(dataWidth >= 5) + { + if((retVal = rtl8373_getAsicReg(baseAddr + 4, &tmpData)) != RT_ERR_OK) + return retVal; + if(dataWidth <8) + { + mask = (1 << (8 * (dataWidth-4))) -1; + *pReadData = mask & tmpData; + + } + else + *(pReadData+1) = tmpData; + } + + if(dataWidth >= 9) + { + if((retVal = rtl8373_getAsicReg(baseAddr + 8, &tmpData)) != RT_ERR_OK) + return retVal; + if(dataWidth <12) + { + mask = (1 << (8 * (dataWidth-8))) -1; + *pReadData = mask & tmpData; + + } + else + *(pReadData+2) = tmpData; + } + if(dataWidth >= 13) + { + if((retVal = rtl8373_getAsicReg(baseAddr + 12, &tmpData)) != RT_ERR_OK) + return retVal; + if(dataWidth <16) + { + mask = (1 << (8 * (dataWidth-12))) -1; + *pReadData = mask & tmpData; + + } + else + *(pReadData+3) = tmpData; + } + + } + else + return RT_ERR_I2C_COMMAND_FAIL; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_i2c_data_write + * Description: + * i2c master write data to slave device's memory + * Input: + * memAddr - slave device memory address want to write + * dataWidth - want to write data's width (1~16) + * memAddrWidth - slave device memory address width (0~3) + * pWriteData - the data going to wirte to slave device + * Output: + * none + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RANGE - out of range + * Note: + * + */ +rtk_api_ret_t dal_rtl8373_i2c_data_write(rtk_uint32 memAddr, rtk_uint32 dataWidth, rtk_uint32 memAddrWidth, rtk_uint32 *pWriteData) +{ + rtk_uint32 retVal = 0, mask = 0, mem_Addr = 0, tmpVal = 0, regVal = 0, i2cFail = 0; + rtk_uint32 tmpData = 0, baseAddr = 0; + + if(pWriteData == NULL) + return RT_ERR_NULL_POINTER; + + if((memAddrWidth > I2C_MEM_ADDR_WIDTH_MAX) || (dataWidth > I2C_DATA_WIDTH_MAX)) + return RT_ERR_INPUT; + + /*set memory address*/ + mask = 1 << (8 * memAddrWidth); + mask = mask - 1; + + mem_Addr = memAddr & mask; + if((retVal = rtl8373_setAsicRegBits(RTL8373_I2C_MST1_MEMADDR_CTRL_ADDR, RTL8373_I2C_MST1_MEMADDR_CTRL_MEM_ADDR_MASK, mem_Addr)) != RT_ERR_OK) + return retVal; + + /*set dataWidth + memAddrWidth*/ + tmpVal = (memAddrWidth << 4) | (dataWidth-1); + + if((retVal = rtl8373_setAsicRegBits(RTL8373_I2C_MST1_CTRL1_ADDR, RTL8373_I2C_MST1_CTRL1_DATA_WIDTH_MASK|RTL8373_I2C_MST1_CTRL1_MEM_ADDR_WIDTH_MASK, tmpVal)) != RT_ERR_OK) + return retVal; + + /*set write operation*/ + if((retVal = rtl8373_setAsicRegBit(RTL8373_I2C_MST1_CTRL1_ADDR, RTL8373_I2C_MST1_CTRL1_RWOP_OFFSET, I2C_RW_OP_WRITE)) != RT_ERR_OK) + return retVal; + + /*set data to indirect reg*/ + baseAddr = RTL8373_I2C_MST1_DATA_CTRL_ADDR(0); + tmpData = *pWriteData; + if((retVal = rtl8373_setAsicReg(baseAddr, tmpData)) != RT_ERR_OK) + return retVal; + + if(dataWidth > 4) + { + tmpData = *(pWriteData + 1); + if((retVal = rtl8373_setAsicReg(baseAddr + 4, tmpData)) != RT_ERR_OK) + return retVal; + } + + if(dataWidth > 8) + { + tmpData = *(pWriteData + 2); + if((retVal = rtl8373_setAsicReg(baseAddr + 8, tmpData)) != RT_ERR_OK) + return retVal; + } + + if(dataWidth > 12) + { + tmpData = *(pWriteData + 3); + if((retVal = rtl8373_setAsicReg(baseAddr + 12, tmpData)) != RT_ERR_OK) + return retVal; + } + + /*trigger WRITE , and wait finished*/ + if((retVal = rtl8373_setAsicRegBit(RTL8373_I2C_MST1_CTRL1_ADDR, RTL8373_I2C_MST1_CTRL1_I2C_TRIG_OFFSET, I2C_RW_ACT_TRIGGER)) != RT_ERR_OK) + return retVal; + do{ + if((retVal = rtl8373_getAsicRegBit(RTL8373_I2C_MST1_CTRL1_ADDR, RTL8373_I2C_MST1_CTRL1_I2C_TRIG_OFFSET, ®Val)) != RT_ERR_OK) + return retVal; + }while(regVal); + + + /*check i2c react fail or not*/ + if((retVal = rtl8373_getAsicRegBit(RTL8373_I2C_MST1_CTRL1_ADDR, RTL8373_I2C_MST1_CTRL1_I2C_FAIL_OFFSET, &i2cFail)) != RT_ERR_OK) + return retVal; + if(i2cFail) + return RT_ERR_I2C_COMMAND_FAIL; + + return RT_ERR_OK; +} + + diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_i2c.h b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_i2c.h new file mode 100755 index 00000000..670e465c --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_i2c.h @@ -0,0 +1,152 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8373 switch high-level API + * + * Feature : The file includes I2C module high-layer API defination + * + */ + +#ifndef __DAL_RTL8373_I2C_H__ +#define __DAL_RTL8373_I2C_H__ +#include <../../i2c.h> + + +/* Function Name: + * dal_rtl8373_i2c_init + * Description: + * initial i2c config + * Input: + * clkRate - I2C SCL clock rate + * deviceAddr - I2C slave device address + * Output: + * none + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RANGE - out of range + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8373_i2c_init(rtk_i2c_sclClockRate_t clkRate, rtk_uint32 deviceAddr); + +/* Function Name: + * dal_rtl8373_i2c_readMode_set + * Description: + * set i2c read mode + * Input: + * mode - standard mode or old mode + * Output: + * none + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RANGE - out of range + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8373_i2c_readMode_set(rtk_i2c_readMode_t mode); + +/* Function Name: + * dal_rtl8373_i2c_readMode_get + * Description: + * get i2c read mode + * Input: + * none + * Output: + * pMode - standard mode or old mode + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RANGE - out of range + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8373_i2c_readMode_get(rtk_i2c_readMode_t *pMode); + +/* Function Name: + * dal_rtl8373_i2c_gpioPinGroup_set + * Description: + * config i2c scl and sda used gpio pin + * Input: + * sclNum - scl pad num + * sdaNum - sda pad num + * Output: + * none + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RANGE - out of range + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8373_i2c_gpioPinGroup_set(rtk_uint32 sclNum, rtk_uint32 sdaNum); + +/* Function Name: + * dal_rtl8373_i2c_gpioPinGroup_get + * Description: + * config i2c scl and sda used gpio pin + * Input: + * none + * Output: + * pSclNum - scl pad num + * pSdaNum - sda pad num + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RANGE - out of range + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8373_i2c_gpioPinGroup_get(rtk_uint32 *pSclNum, rtk_uint32 *pSdaNum); + +/* Function Name: + * dal_rtl8373_i2c_data_read + * Description: + * i2c master read slave device data + * Input: + * memAddr - slave device memory address + * dataWidth - want to read data width (1~16) + * memAddrWidth - slave device memory address width (0~3) + * Output: + * pReadData - slave device data that has read + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RANGE - out of range + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8373_i2c_data_read(rtk_uint32 memAddr, rtk_uint32 dataWidth, rtk_uint32 memAddrWidth, rtk_uint32 *pReadData); + +/* Function Name: + * dal_rtl8373_i2c_data_write + * Description: + * i2c master write data to slave device's memory + * Input: + * memAddr - slave device memory address want to write + * dataWidth - want to write data's width (1~16) + * memAddrWidth - slave device memory address width (0~3) + * pWriteData - the data going to wirte to slave device + * Output: + * none + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RANGE - out of range + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8373_i2c_data_write(rtk_uint32 memAddr, rtk_uint32 dataWidth, rtk_uint32 memAddrWidth, rtk_uint32 *pWriteData); + + +#endif /* __DAL_RTL8373_I2C_H__ */ + diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_igmp.c b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_igmp.c new file mode 100755 index 00000000..07048652 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_igmp.c @@ -0,0 +1,1923 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8373 + * Feature : Here is a list of all functions and variables in IGMP module. + * + */ + +#include +#include +#include +#include + +#include +#include +//#include + +/* Function Name: + * rtk_igmp_init + * Description: + * This API enables H/W IGMP and set a default initial configuration. + * Input: + * None. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API enables H/W IGMP and set a default initial configuration. + */ +rtk_api_ret_t dal_rtl8373_igmp_init(void) +{ + rtk_api_ret_t retVal; + rtk_port_t port; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if ((retVal = dal_rtl8373_l2_ipMcastAddrLookup_set(LOOKUP_IP))!=RT_ERR_OK) + return retVal; + + RTK_SCAN_ALL_PHY_PORTMASK(port) + { + + /* IGMPv1 operation */ + retVal = rtl8373_setAsicRegBits(RTL8373_IGMP_PORT_CTRL_ADDR(port), RTL8373_IGMP_PORT_CTRL_IGMPV1_OP_MASK, PROTOCOL_OP_ASIC); + if(retVal != RT_ERR_OK) + return retVal; + + /* IGMPv2 operation */ + retVal = rtl8373_setAsicRegBits(RTL8373_IGMP_PORT_CTRL_ADDR(port), RTL8373_IGMP_PORT_CTRL_IGMPV2_OP_MASK, PROTOCOL_OP_ASIC); + if(retVal != RT_ERR_OK) + return retVal; + + /* IGMPv3 operation */ + retVal = rtl8373_setAsicRegBits(RTL8373_IGMP_PORT_CTRL_ADDR(port), RTL8373_IGMP_PORT_CTRL_IGMPV3_OP_MASK, PROTOCOL_OP_FLOOD); + if(retVal != RT_ERR_OK) + return retVal; + + /* MLDv1 operation */ + retVal = rtl8373_setAsicRegBits(RTL8373_IGMP_PORT_CTRL_ADDR(port), RTL8373_IGMP_PORT_CTRL_MLDV1_OP_MASK, PROTOCOL_OP_ASIC); + if(retVal != RT_ERR_OK) + return retVal; + + /* MLDv2 operation */ + retVal = rtl8373_setAsicRegBits(RTL8373_IGMP_PORT_CTRL_ADDR(port), RTL8373_IGMP_PORT_CTRL_MLDV2_OP_MASK, PROTOCOL_OP_FLOOD); + if(retVal != RT_ERR_OK) + return retVal; + + } + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_IGMP_ROUTER_PORT_CRTL_ADDR, RTL8373_IGMP_ROUTER_PORT_CRTL_ALLOW_DYN_ROTR_PMSK_MASK,rtk_switch_phyPortMask_get()))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_setAsicRegBit(RTL8373_IGMP_CTRL_ADDR, RTL8373_IGMP_CTRL_FAST_LEAVE_EN_OFFSET, ENABLED))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_IGMP_CTRL_ADDR, RTL8373_IGMP_CTRL_REPORT_LEAVE_FWD_MASK, ENABLED))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_setAsicRegBit(RTL8373_IGMP_CTRL_ADDR, RTL8373_IGMP_CTRL_IGMP_MLD_EN_OFFSET, ENABLED))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_igmp_state_set + * Description: + * This API set H/W IGMP state. + * Input: + * enabled - H/W IGMP state + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error parameter + * Note: + * This API set H/W IGMP state. + */ +rtk_api_ret_t dal_rtl8373_igmp_state_set(rtk_enable_t enabled) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (enabled >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if ((retVal = rtl8373_setAsicRegBit(RTL8373_IGMP_CTRL_ADDR, RTL8373_IGMP_CTRL_IGMP_MLD_EN_OFFSET, enabled))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_igmp_state_get + * Description: + * This API get H/W IGMP state. + * Input: + * None. + * Output: + * pEnabled - H/W IGMP state + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error parameter + * Note: + * This API set current H/W IGMP state. + */ +rtk_api_ret_t dal_rtl8373_igmp_state_get(rtk_enable_t *pEnabled) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(pEnabled == NULL) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8373_getAsicRegBit(RTL8373_IGMP_CTRL_ADDR, RTL8373_IGMP_CTRL_IGMP_MLD_EN_OFFSET, pEnabled))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_igmp_static_router_port_set + * Description: + * Configure static router port + * Input: + * pPortmask - Static Port mask + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Error parameter + * Note: + * This API set static router port + */ +rtk_api_ret_t dal_rtl8373_igmp_static_router_port_set(rtk_portmask_t *pPortmask) +{ + rtk_api_ret_t retVal; + rtk_uint32 pmask; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Valid port mask */ + if(pPortmask == NULL) + return RT_ERR_NULL_POINTER; + + RTK_CHK_PORTMASK_VALID(pPortmask); + + if ((retVal = rtk_switch_portmask_L2P_get(pPortmask, &pmask))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_IGMP_ROUTER_PORT_CRTL_ADDR, RTL8373_IGMP_ROUTER_PORT_CRTL_STIC_PMSK_MASK, pmask))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_igmp_static_router_port_get + * Description: + * Get static router port + * Input: + * None. + * Output: + * pPortmask - Static port mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Error parameter + * Note: + * This API get static router port + */ +rtk_api_ret_t dal_rtl8373_igmp_static_router_port_get(rtk_portmask_t *pPortmask) +{ + rtk_api_ret_t retVal; + rtk_uint32 pmask; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(pPortmask == NULL) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8373_getAsicRegBits(RTL8373_IGMP_ROUTER_PORT_CRTL_ADDR, RTL8373_IGMP_ROUTER_PORT_CRTL_STIC_PMSK_MASK, &pmask))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtk_switch_portmask_P2L_get(pmask, pPortmask))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_igmp_protocol_set + * Description: + * set IGMP/MLD protocol action + * Input: + * port - Port ID + * protocol - IGMP/MLD protocol + * action - Per-port and per-protocol IGMP action seeting + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Error parameter + * Note: + * This API set IGMP/MLD protocol action + */ +rtk_api_ret_t dal_rtl8373_igmp_protocol_set(rtk_port_t port, rtk_igmp_protocol_t protocol, rtk_igmp_action_t action) +{ + rtk_uint32 operation; + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check port valid */ + RTK_CHK_PORT_VALID(port); + + if(protocol >= PROTOCOL_END) + return RT_ERR_INPUT; + + if(action >= IGMP_ACTION_END) + return RT_ERR_INPUT; + + switch(action) + { + case IGMP_ACTION_FORWARD: + operation = PROTOCOL_OP_FLOOD; + break; + case IGMP_ACTION_TRAP2CPU: + operation = PROTOCOL_OP_TRAP; + break; + case IGMP_ACTION_DROP: + operation = PROTOCOL_OP_DROP; + break; + case IGMP_ACTION_ASIC: + operation = PROTOCOL_OP_ASIC; + break; + default: + return RT_ERR_INPUT; + } + + switch(protocol) + { + case PROTOCOL_IGMPv1: + if ((retVal = rtl8373_setAsicRegBits(RTL8373_IGMP_PORT_CTRL_ADDR(rtk_switch_port_L2P_get(port)), RTL8373_IGMP_PORT_CTRL_IGMPV1_OP_MASK,operation))!=RT_ERR_OK) + return retVal; + + break; + case PROTOCOL_IGMPv2: + if ((retVal = rtl8373_setAsicRegBits(RTL8373_IGMP_PORT_CTRL_ADDR(rtk_switch_port_L2P_get(port)), RTL8373_IGMP_PORT_CTRL_IGMPV2_OP_MASK,operation))!=RT_ERR_OK) + return retVal; + + break; + case PROTOCOL_IGMPv3: + if ((retVal = rtl8373_setAsicRegBits(RTL8373_IGMP_PORT_CTRL_ADDR(rtk_switch_port_L2P_get(port)), RTL8373_IGMP_PORT_CTRL_IGMPV3_OP_MASK,operation))!=RT_ERR_OK) + return retVal; + + break; + case PROTOCOL_MLDv1: + if ((retVal = rtl8373_setAsicRegBits(RTL8373_IGMP_PORT_CTRL_ADDR(rtk_switch_port_L2P_get(port)), RTL8373_IGMP_PORT_CTRL_MLDV1_OP_MASK,operation))!=RT_ERR_OK) + return retVal; + + break; + case PROTOCOL_MLDv2: + if ((retVal = rtl8373_setAsicRegBits(RTL8373_IGMP_PORT_CTRL_ADDR(rtk_switch_port_L2P_get(port)), RTL8373_IGMP_PORT_CTRL_MLDV2_OP_MASK,operation))!=RT_ERR_OK) + return retVal; + + break; + default: + return RT_ERR_INPUT; + + } + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_igmp_protocol_get + * Description: + * set IGMP/MLD protocol action + * Input: + * port - Port ID + * protocol - IGMP/MLD protocol + * action - Per-port and per-protocol IGMP action seeting + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Error parameter + * Note: + * This API set IGMP/MLD protocol action + */ +rtk_api_ret_t dal_rtl8373_igmp_protocol_get(rtk_port_t port, rtk_igmp_protocol_t protocol, rtk_igmp_action_t *pAction) +{ + rtk_uint32 operation; + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check port valid */ + RTK_CHK_PORT_VALID(port); + + if(protocol >= PROTOCOL_END) + return RT_ERR_INPUT; + + if(pAction == NULL) + return RT_ERR_NULL_POINTER; + + switch(protocol) + { + case PROTOCOL_IGMPv1: + if ((retVal = rtl8373_getAsicRegBits(RTL8373_IGMP_PORT_CTRL_ADDR(rtk_switch_port_L2P_get(port)), RTL8373_IGMP_PORT_CTRL_IGMPV1_OP_MASK, &operation))!=RT_ERR_OK) + return retVal; + + break; + case PROTOCOL_IGMPv2: + if ((retVal = rtl8373_getAsicRegBits(RTL8373_IGMP_PORT_CTRL_ADDR(rtk_switch_port_L2P_get(port)), RTL8373_IGMP_PORT_CTRL_IGMPV2_OP_MASK, &operation))!=RT_ERR_OK) + return retVal; + + break; + case PROTOCOL_IGMPv3: + if ((retVal = rtl8373_getAsicRegBits(RTL8373_IGMP_PORT_CTRL_ADDR(rtk_switch_port_L2P_get(port)), RTL8373_IGMP_PORT_CTRL_IGMPV3_OP_MASK, &operation))!=RT_ERR_OK) + return retVal; + + break; + case PROTOCOL_MLDv1: + if ((retVal = rtl8373_getAsicRegBits(RTL8373_IGMP_PORT_CTRL_ADDR(rtk_switch_port_L2P_get(port)), RTL8373_IGMP_PORT_CTRL_MLDV1_OP_MASK, &operation))!=RT_ERR_OK) + return retVal; + + break; + case PROTOCOL_MLDv2: + if ((retVal = rtl8373_getAsicRegBits(RTL8373_IGMP_PORT_CTRL_ADDR(rtk_switch_port_L2P_get(port)), RTL8373_IGMP_PORT_CTRL_MLDV2_OP_MASK, &operation))!=RT_ERR_OK) + return retVal; + + break; + default: + return RT_ERR_INPUT; + + } + + switch(operation) + { + case PROTOCOL_OP_FLOOD: + *pAction = IGMP_ACTION_FORWARD; + break; + case PROTOCOL_OP_TRAP: + *pAction = IGMP_ACTION_TRAP2CPU; + break; + case PROTOCOL_OP_DROP: + *pAction = IGMP_ACTION_DROP; + break; + case PROTOCOL_OP_ASIC: + *pAction = IGMP_ACTION_ASIC; + break; + default: + return RT_ERR_FAILED; + + } + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_igmp_fastLeave_set + * Description: + * set IGMP/MLD FastLeave state + * Input: + * state - ENABLED: Enable FastLeave, DISABLED: disable FastLeave + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_INPUT - Error Input + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API set IGMP/MLD FastLeave state + */ +rtk_api_ret_t dal_rtl8373_igmp_fastLeave_set(rtk_enable_t state) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(state >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if ((retVal =rtl8373_setAsicRegBit(RTL8373_IGMP_CTRL_ADDR, RTL8373_IGMP_CTRL_FAST_LEAVE_EN_OFFSET, (state >= 1) ? 1 : 0))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_igmp_fastLeave_get + * Description: + * get IGMP/MLD FastLeave state + * Input: + * None + * Output: + * pState - ENABLED: Enable FastLeave, DISABLED: disable FastLeave + * Return: + * RT_ERR_OK - OK + * RT_ERR_NULL_POINTER - NULL pointer + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API get IGMP/MLD FastLeave state + */ +rtk_api_ret_t dal_rtl8373_igmp_fastLeave_get(rtk_enable_t *pState) +{ + rtk_uint32 fast_leave; + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(pState == NULL) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8373_getAsicRegBit(RTL8373_IGMP_CTRL_ADDR, RTL8373_IGMP_CTRL_FAST_LEAVE_EN_OFFSET, &fast_leave))!=RT_ERR_OK) + return retVal; + + *pState = ((fast_leave == 1) ? ENABLED : DISABLED); + return RT_ERR_OK; +} + +/* Function Name: + * rtk_igmp_maxGroup_set + * Description: + * Set per port multicast group learning limit. + * Input: + * port - Port ID + * group - The number of multicast group learning limit. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_PORT_ID - Error Port ID + * RT_ERR_OUT_OF_RANGE - parameter out of range + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API set per port multicast group learning limit. + */ +rtk_api_ret_t dal_rtl8373_igmp_maxGroup_set(rtk_port_t port, rtk_uint32 group) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check port valid */ + RTK_CHK_PORT_VALID(port); + + if(group > RTL8373_IGMP_MAX_GOUP) + return RT_ERR_OUT_OF_RANGE; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_IGMP_PORT_CTRL_ADDR(rtk_switch_port_L2P_get(port)), RTL8373_IGMP_PORT_CTRL_MAX_GROUP_NUM_MASK , group))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_igmp_maxGroup_get + * Description: + * Get per port multicast group learning limit. + * Input: + * port - Port ID + * Output: + * pGroup - The number of multicast group learning limit. + * Return: + * RT_ERR_OK - OK + * RT_ERR_PORT_ID - Error Port ID + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API get per port multicast group learning limit. + */ +rtk_api_ret_t dal_rtl8373_igmp_maxGroup_get(rtk_port_t port, rtk_uint32 *pGroup) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check port valid */ + RTK_CHK_PORT_VALID(port); + + if(pGroup == NULL) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8373_getAsicRegBits(RTL8373_IGMP_PORT_CTRL_ADDR(rtk_switch_port_L2P_get(port)), RTL8373_IGMP_PORT_CTRL_MAX_GROUP_NUM_MASK , pGroup))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_igmp_currentGroup_get + * Description: + * Get per port multicast group learning count. + * Input: + * port - Port ID + * Output: + * pGroup - The number of multicast group learning count. + * Return: + * RT_ERR_OK - OK + * RT_ERR_PORT_ID - Error Port ID + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API get per port multicast group learning count. + */ +rtk_api_ret_t dal_rtl8373_igmp_currentGroup_get(rtk_port_t port, rtk_uint32 *pGroup) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check port valid */ + RTK_CHK_PORT_VALID(port); + + if(pGroup == NULL) + return RT_ERR_NULL_POINTER; + + retVal = rtl8373_getAsicRegBits(RTL8373_PORT_CURR_GROUP_ADDR(port), RTL8373_PORT_CURR_GROUP_NUM_MASK(port) , pGroup); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_igmp_tableFullAction_set + * Description: + * set IGMP/MLD Table Full Action + * Input: + * action - Table Full Action + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_INPUT - Error Input + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +rtk_api_ret_t dal_rtl8373_igmp_tableFullAction_set(rtk_igmp_tableFullAction_t action) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(action >= IGMP_TABLE_FULL_OP_END) + return RT_ERR_INPUT; + + /* Table full Operation */ + retVal = rtl8373_setAsicRegBits(RTL8373_IGMP_CTRL_ADDR, RTL8373_IGMP_CTRL_TABLE_FULL_OP_MASK, action); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_igmp_tableFullAction_get + * Description: + * get IGMP/MLD Table Full Action + * Input: + * None + * Output: + * pAction - Table Full Action + * Return: + * RT_ERR_OK - OK + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +rtk_api_ret_t dal_rtl8373_igmp_tableFullAction_get(rtk_igmp_tableFullAction_t *pAction) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pAction) + return RT_ERR_NULL_POINTER; + + /* Table full Operation */ + retVal = rtl8373_getAsicRegBits(RTL8373_IGMP_CTRL_ADDR, RTL8373_IGMP_CTRL_TABLE_FULL_OP_MASK, pAction); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_igmp_checksumErrorAction_set + * Description: + * set IGMP/MLD Checksum Error Action + * Input: + * action - Checksum error Action + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_INPUT - Error Input + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +rtk_api_ret_t dal_rtl8373_igmp_checksumErrorAction_set(rtk_igmp_checksumErrorAction_t action) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(action >= IGMP_CRC_ERR_OP_END) + return RT_ERR_INPUT; + + /* CRC Error Operation */ + retVal = rtl8373_setAsicRegBits(RTL8373_IGMP_CTRL_ADDR, RTL8373_IGMP_CTRL_CKS_ERR_OP_MASK, action); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_igmp_checksumErrorAction_get + * Description: + * get IGMP/MLD Checksum Error Action + * Input: + * None + * Output: + * pAction - Checksum error Action + * Return: + * RT_ERR_OK - OK + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +rtk_api_ret_t dal_rtl8373_igmp_checksumErrorAction_get(rtk_igmp_checksumErrorAction_t *pAction) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pAction) + return RT_ERR_NULL_POINTER; + + /* CRC Error Operation */ + retVal = rtl8373_getAsicRegBits(RTL8373_IGMP_CTRL_ADDR, RTL8373_IGMP_CTRL_CKS_ERR_OP_MASK, pAction); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_igmp_leaveTimer_set + * Description: + * set IGMP/MLD Leave timer + * Input: + * timer - Leave timer + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_INPUT - Error Input + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +rtk_api_ret_t dal_rtl8373_igmp_leaveTimer_set(rtk_uint32 timer) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(timer > RTL8373_MAX_LEAVE_TIMER) + return RT_ERR_INPUT; + + /* Leave timer */ + retVal = rtl8373_setAsicRegBits(RTL8373_IGMP_CTRL_ADDR, RTL8373_IGMP_CTRL_LEAVE_TIMER_MASK, timer); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_igmp_leaveTimer_get + * Description: + * get IGMP/MLD Leave timer + * Input: + * None + * Output: + * pTimer - Leave Timer. + * Return: + * RT_ERR_OK - OK + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +rtk_api_ret_t dal_rtl8373_igmp_leaveTimer_get(rtk_uint32 *pTimer) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pTimer) + return RT_ERR_NULL_POINTER; + + /* Leave timer */ + retVal = rtl8373_getAsicRegBits(RTL8373_IGMP_CTRL_ADDR, RTL8373_IGMP_CTRL_LEAVE_TIMER_MASK, pTimer); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_igmp_queryInterval_set + * Description: + * set IGMP/MLD Query Interval + * Input: + * interval - Query Interval + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_INPUT - Error Input + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +rtk_api_ret_t dal_rtl8373_igmp_queryInterval_set(rtk_uint32 interval) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(interval > RTL8373_MAX_QUERY_INT) + return RT_ERR_INPUT; + + /* Query Interval */ + retVal = rtl8373_setAsicReg(RTL8373_IGMP_QUERY_INTVL_ADDR, interval); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_igmp_queryInterval_get + * Description: + * get IGMP/MLD Query Interval + * Input: + * None. + * Output: + * pInterval - Query Interval + * Return: + * RT_ERR_OK - OK + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +rtk_api_ret_t dal_rtl8373_igmp_queryInterval_get(rtk_uint32 *pInterval) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pInterval) + return RT_ERR_NULL_POINTER; + + /* Query Interval */ + retVal = rtl8373_getAsicReg(RTL8373_IGMP_QUERY_INTVL_ADDR, pInterval); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_setAsicIGMPIsoLeaky + * Description: + * Set Port Isolation leaky for IGMP/MLD packet + * Input: + * leaky - 1: Leaky, 0:not leaky + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +rtk_api_ret_t dal_rtl8373_setAsicIGMPIsoLeaky(rtk_uint32 leaky) +{ + rtk_api_ret_t retVal; + + retVal = rtl8373_setAsicRegBit(RTL8373_IGMP_CTRL_ADDR, RTL8373_IGMP_CTRL_IGMP_MLD_PORTISO_LKY_OFFSET, leaky); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_getAsicIGMPIsoLeaky + * Description: + * Get Port Isolation leaky for IGMP/MLD packet + * Input: + * Noen + * Output: + * pLeaky - 1: Leaky, 0:not leaky + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +rtk_api_ret_t dal_rtl8373_getAsicIGMPIsoLeaky(rtk_uint32 *pLeaky) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + + retVal = rtl8373_getAsicRegBit(RTL8373_IGMP_CTRL_ADDR, RTL8373_IGMP_CTRL_IGMP_MLD_PORTISO_LKY_OFFSET, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + *pLeaky = regData; + return RT_ERR_OK; +} +/* Function Name: + * rtl8373_setAsicIGMPVLANLeaky + * Description: + * Set VLAN leaky for IGMP/MLD packet + * Input: + * leaky - 1: Leaky, 0:not leaky + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +rtk_api_ret_t dal_rtl8373_setAsicIGMPVLANLeaky(rtk_uint32 leaky) +{ + rtk_api_ret_t retVal; + + retVal = rtl8373_setAsicRegBit(RTL8373_IGMP_CTRL_ADDR, RTL8373_IGMP_CTRL_IGMP_MLD_VLAN_LKY_OFFSET, leaky); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtl8373_getAsicIGMPVLANLeaky + * Description: + * Get VLAN leaky for IGMP/MLD packet + * Input: + * Noen + * Output: + * pLeaky - 1: Leaky, 0:not leaky + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +rtk_api_ret_t dal_rtl8373_getAsicIGMPVLANLeaky(rtk_uint32 *pLeaky) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + + retVal = rtl8373_getAsicRegBit(RTL8373_IGMP_CTRL_ADDR, RTL8373_IGMP_CTRL_IGMP_MLD_VLAN_LKY_OFFSET, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + *pLeaky = regData; + return RT_ERR_OK; +} +/* Function Name: + * dal_rtl8373_setAsicIpMulticastVlanLeaky + * Description: + * Set IP multicast VLAN Leaky function + * Input: + * port - Physical port number (0~7) + * enabled - 1: enabled, 0: disabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * When enabling this function, + * if the lookup result(forwarding portmap) of IP Multicast packet is over VLAN boundary, + * the packet can be forwarded across VLAN + */ +rtk_api_ret_t dal_rtl8373_setAsicIpMulticastVlanLeaky(rtk_uint32 port, rtk_uint32 enabled) +{ + rtk_api_ret_t retVal; + + if(port > RTL8373_PORTIDMAX) + return RT_ERR_PORT_ID; + + retVal = rtl8373_setAsicRegBit(RTL8373_IPMUL_NO_VLAN_EGRESS_ADDR(port),RTL8373_IPMUL_NO_VLAN_EGRESS_IPMUL_VLAN_LEAKY_OFFSET(port),enabled); + + return retVal; +} +/* Function Name: + * dal_rtl8373_getAsicIpMulticastVlanLeaky + * Description: + * Get IP multicast VLAN Leaky function + * Input: + * port - Physical port number (0~7) + * enabled - 1: enabled, 0: disabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +rtk_api_ret_t dal_rtl8373_getAsicIpMulticastVlanLeaky(rtk_uint32 port, rtk_uint32 *ptr_enabled) +{ + rtk_api_ret_t retVal; + + if(port > RTL8373_PORTIDMAX) + return RT_ERR_PORT_ID; + + retVal = rtl8373_getAsicRegBit(RTL8373_IPMUL_NO_VLAN_EGRESS_ADDR(port),RTL8373_IPMUL_NO_VLAN_EGRESS_IPMUL_VLAN_LEAKY_OFFSET(port), ptr_enabled); + + return retVal; +} +/* Function Name: + * dal_rtl8373_setAsicIGMPBypassStormCTRL + * Description: + * Set the function of bypass strom control for IGMP/MLD packet + * Input: + * bypass - 1: Bypass, 0:not bypass + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +rtk_api_ret_t dal_rtl8373_setAsicIGMPBypassStormCTRL(rtk_uint32 bypass) +{ + rtk_api_ret_t retVal; + + retVal = rtl8373_setAsicRegBit(RTL8373_IGMP_CTRL_ADDR, RTL8373_IGMP_CTRL_IGMP_MLD_DISC_STORM_FLTR_OFFSET, bypass); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_getAsicIGMPBypassStormCTRL + * Description: + * Set the function of bypass strom control for IGMP/MLD packet + * Input: + * None + * Output: + * pBypass - 1: Bypass, 0:not bypass + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +rtk_api_ret_t dal_rtl8373_getAsicIGMPBypassStormCTRL(rtk_uint32 *pBypass) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + + retVal = rtl8373_getAsicRegBit(RTL8373_IGMP_CTRL_ADDR, RTL8373_IGMP_CTRL_IGMP_MLD_DISC_STORM_FLTR_OFFSET, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + *pBypass = regData; + return RT_ERR_OK; +} +/* Function Name: + * rtk_igmp_robustness_set + * Description: + * set IGMP/MLD Robustness value + * Input: + * robustness - Robustness value + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_INPUT - Error Input + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +rtk_api_ret_t dal_rtl8373_igmp_robustness_set(rtk_uint32 robustness) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(robustness > RTL8373_MAX_ROB_VAR) + return RT_ERR_INPUT; + + /* Bourstness variable */ + retVal = rtl8373_setAsicRegBits(RTL8373_IGMP_CTRL_ADDR, RTL8373_IGMP_CTRL_ROBUSTNESS_VAR_MASK, robustness); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_igmp_robustness_get + * Description: + * get IGMP/MLD Robustness value + * Input: + * None + * Output: + * pRobustness - Robustness value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +rtk_api_ret_t dal_rtl8373_igmp_robustness_get(rtk_uint32 *pRobustness) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pRobustness) + return RT_ERR_NULL_POINTER; + + /* Bourstness variable */ + retVal = rtl8373_getAsicRegBits(RTL8373_IGMP_CTRL_ADDR, RTL8373_IGMP_CTRL_ROBUSTNESS_VAR_MASK, pRobustness); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_igmp_dynamicRouterRortAllow_set + * Description: + * Configure dynamic router port allow option + * Input: + * pPortmask - Dynamic Port allow mask + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Error parameter + * Note: + * + */ +rtk_api_ret_t dal_rtl8373_igmp_dynamicRouterPortAllow_set(rtk_portmask_t *pPortmask) +{ + rtk_api_ret_t retVal; + rtk_uint32 pmask; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pPortmask) + return RT_ERR_NULL_POINTER; + + RTK_CHK_PORTMASK_VALID(pPortmask); + + if ((retVal = rtk_switch_portmask_L2P_get(pPortmask, &pmask))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_IGMP_ROUTER_PORT_CRTL_ADDR, RTL8373_IGMP_ROUTER_PORT_CRTL_ALLOW_DYN_ROTR_PMSK_MASK,pmask))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_igmp_dynamicRouterRortAllow_get + * Description: + * Get dynamic router port allow option + * Input: + * None. + * Output: + * pPortmask - Dynamic Port allow mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Error parameter + * Note: + * + */ +rtk_api_ret_t dal_rtl8373_igmp_dynamicRouterPortAllow_get(rtk_portmask_t *pPortmask) +{ + rtk_api_ret_t retVal; + rtk_uint32 pmask; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pPortmask) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8373_getAsicRegBits(RTL8373_IGMP_ROUTER_PORT_CRTL_ADDR, RTL8373_IGMP_ROUTER_PORT_CRTL_ALLOW_DYN_ROTR_PMSK_MASK,&pmask))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtk_switch_portmask_P2L_get(pmask, pPortmask))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_igmp_dynamicRouterPort_get + * Description: + * Get dynamic router port + * Input: + * None. + * Output: + * pDynamicRouterPort - Dynamic Router Port + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Error parameter + * Note: + * + */ +rtk_api_ret_t dal_rtl8373_igmp_dynamicRouterPort_get(rtk_igmp_dynamicRouterPort_t *pDynamicRouterPort) +{ + rtk_api_ret_t retVal; + rtk_uint32 port; + rtk_uint32 timer; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pDynamicRouterPort) + return RT_ERR_NULL_POINTER; + + retVal = rtl8373_getAsicRegBits(RTL8373_IGMP_DYN_ROUTER_INFO_ADDR, RTL8373_IGMP_DYN_ROUTER_INFO_PORT1_ID_MASK, &port); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8373_getAsicRegBits(RTL8373_IGMP_DYN_ROUTER_INFO_ADDR, RTL8373_IGMP_DYN_ROUTER_INFO_TIMER1_MASK, &timer); + if(retVal != RT_ERR_OK) + return retVal; + + if (port == RTL8373_ROUTER_PORT_INVALID) + { + pDynamicRouterPort->dynamicRouterPort0Valid = DISABLED; + pDynamicRouterPort->dynamicRouterPort0 = 0; + pDynamicRouterPort->dynamicRouterPort0Timer = 0; + } + else + { + pDynamicRouterPort->dynamicRouterPort0Valid = ENABLED; + pDynamicRouterPort->dynamicRouterPort0 = rtk_switch_port_P2L_get(port); + pDynamicRouterPort->dynamicRouterPort0Timer = timer; + } + + retVal = rtl8373_getAsicRegBits(RTL8373_IGMP_DYN_ROUTER_INFO_ADDR, RTL8373_IGMP_DYN_ROUTER_INFO_PORT2_ID_MASK, &port); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8373_getAsicRegBits(RTL8373_IGMP_DYN_ROUTER_INFO_ADDR, RTL8373_IGMP_DYN_ROUTER_INFO_TIMER2_MASK, &timer); + if(retVal != RT_ERR_OK) + return retVal; + + if (port == RTL8373_ROUTER_PORT_INVALID) + { + pDynamicRouterPort->dynamicRouterPort1Valid = DISABLED; + pDynamicRouterPort->dynamicRouterPort1 = 0; + pDynamicRouterPort->dynamicRouterPort1Timer = 0; + } + else + { + pDynamicRouterPort->dynamicRouterPort1Valid = ENABLED; + pDynamicRouterPort->dynamicRouterPort1 = rtk_switch_port_P2L_get(port); + pDynamicRouterPort->dynamicRouterPort1Timer = timer; + } + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_igmp_suppressionEnable_set + * Description: + * Configure IGMPv1/v2 & MLDv1 Report/Leave/Done suppression + * Input: + * reportSuppression - Report suppression + * leaveSuppression - Leave suppression + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + * + */ +rtk_api_ret_t dal_rtl8373_igmp_suppressionEnable_set(rtk_enable_t reportSuppression, rtk_enable_t leaveSuppression) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(reportSuppression >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if(leaveSuppression >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + retVal = rtl8373_setAsicRegBits(RTL8373_IGMP_CTRL_ADDR, RTL8373_IGMP_CTRL_REPORT_SUPPRESSION_MASK, reportSuppression); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8373_setAsicRegBits(RTL8373_IGMP_CTRL_ADDR, RTL8373_IGMP_CTRL_LEAVE_SUPPRESSION_MASK, leaveSuppression); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_igmp_suppressionEnable_get + * Description: + * Get IGMPv1/v2 & MLDv1 Report/Leave/Done suppression + * Input: + * None + * Output: + * pReportSuppression - Report suppression + * pLeaveSuppression - Leave suppression + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * + */ +rtk_api_ret_t dal_rtl8373_igmp_suppressionEnable_get(rtk_enable_t *pReportSuppression, rtk_enable_t *pLeaveSuppression) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pReportSuppression) + return RT_ERR_NULL_POINTER; + + if(NULL == pLeaveSuppression) + return RT_ERR_NULL_POINTER; + + retVal = rtl8373_getAsicRegBits(RTL8373_IGMP_CTRL_ADDR, RTL8373_IGMP_CTRL_REPORT_SUPPRESSION_MASK, pReportSuppression); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8373_getAsicRegBits(RTL8373_IGMP_CTRL_ADDR, RTL8373_IGMP_CTRL_LEAVE_SUPPRESSION_MASK, pLeaveSuppression); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_igmp_portRxPktEnable_set + * Description: + * Configure IGMP/MLD RX Packet configuration + * Input: + * port - Port ID + * pRxCfg - RX Packet Configuration + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * + */ +rtk_api_ret_t dal_rtl8373_igmp_portRxPktEnable_set(rtk_port_t port, rtk_igmp_rxPktEnable_t *pRxCfg) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check port valid */ + RTK_CHK_PORT_VALID(port); + + if(NULL == pRxCfg) + return RT_ERR_NULL_POINTER; + + if(pRxCfg->rxQuery >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if(pRxCfg->rxReport >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if(pRxCfg->rxLeave >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if(pRxCfg->rxMRP >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if(pRxCfg->rxMcast >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + retVal = rtl8373_setAsicRegBits(RTL8373_IGMP_PORT_CTRL_ADDR(rtk_switch_port_L2P_get(port)), RTL8373_IGMP_PORT_CTRL_ALLOW_QUERY_MASK, (rtk_uint32)pRxCfg->rxQuery); + if(retVal != RT_ERR_OK) + return retVal; + retVal = rtl8373_setAsicRegBits(RTL8373_IGMP_PORT_CTRL_ADDR(rtk_switch_port_L2P_get(port)), RTL8373_IGMP_PORT_CTRL_ALLOW_REPORT_MASK, (rtk_uint32)pRxCfg->rxReport); + if(retVal != RT_ERR_OK) + return retVal; + retVal = rtl8373_setAsicRegBits(RTL8373_IGMP_PORT_CTRL_ADDR(rtk_switch_port_L2P_get(port)), RTL8373_IGMP_PORT_CTRL_ALLOW_LEAVE_MASK, (rtk_uint32)pRxCfg->rxLeave); + if(retVal != RT_ERR_OK) + return retVal; + retVal = rtl8373_setAsicRegBits(RTL8373_IGMP_PORT_CTRL_ADDR(rtk_switch_port_L2P_get(port)), RTL8373_IGMP_PORT_CTRL_ALLOW_MRP_MASK, (rtk_uint32)pRxCfg->rxMRP); + if(retVal != RT_ERR_OK) + return retVal; + retVal = rtl8373_setAsicRegBits(RTL8373_IGMP_PORT_CTRL_ADDR(rtk_switch_port_L2P_get(port)), RTL8373_IGMP_PORT_CTRL_ALLOW_MC_DATA_MASK, (rtk_uint32)pRxCfg->rxMcast); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_igmp_portRxPktEnable_get + * Description: + * Get IGMP/MLD RX Packet configuration + * Input: + * port - Port ID + * pRxCfg - RX Packet Configuration + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * + */ +rtk_api_ret_t dal_rtl8373_igmp_portRxPktEnable_get(rtk_port_t port, rtk_igmp_rxPktEnable_t *pRxCfg) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + /* Check port valid */ + RTK_CHK_PORT_VALID(port); + + if(NULL == pRxCfg) + return RT_ERR_NULL_POINTER; + + retVal = rtl8373_getAsicRegBits(RTL8373_IGMP_PORT_CTRL_ADDR(rtk_switch_port_L2P_get(port)),RTL8373_IGMP_PORT_CTRL_ALLOW_QUERY_MASK, (rtk_uint32 *)&(pRxCfg->rxQuery)); + if(retVal != RT_ERR_OK) + return retVal; + retVal = rtl8373_getAsicRegBits(RTL8373_IGMP_PORT_CTRL_ADDR(rtk_switch_port_L2P_get(port)),RTL8373_IGMP_PORT_CTRL_ALLOW_REPORT_MASK, (rtk_uint32 *)&(pRxCfg->rxReport)); + if(retVal != RT_ERR_OK) + return retVal; + retVal = rtl8373_getAsicRegBits(RTL8373_IGMP_PORT_CTRL_ADDR(rtk_switch_port_L2P_get(port)),RTL8373_IGMP_PORT_CTRL_ALLOW_LEAVE_MASK, (rtk_uint32 *)&(pRxCfg->rxLeave)); + if(retVal != RT_ERR_OK) + return retVal; + retVal = rtl8373_getAsicRegBits(RTL8373_IGMP_PORT_CTRL_ADDR(rtk_switch_port_L2P_get(port)),RTL8373_IGMP_PORT_CTRL_ALLOW_MRP_MASK, (rtk_uint32 *)&(pRxCfg->rxMRP)); + if(retVal != RT_ERR_OK) + return retVal; + retVal = rtl8373_getAsicRegBits(RTL8373_IGMP_PORT_CTRL_ADDR(rtk_switch_port_L2P_get(port)),RTL8373_IGMP_PORT_CTRL_ALLOW_MC_DATA_MASK, (rtk_uint32 *)&(pRxCfg->rxMcast)); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_getAsicIGMPGroup + * Description: + * Get IGMP group + * Input: + * idx - Group index (0~255) + * valid - valid bit + * grp - IGMP group + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - Group index is out of range + * Note: + * None + */ +rtk_api_ret_t dal_rtl8373_getAsicIGMPGroup(rtk_uint32 idx, rtk_uint32 *valid, rtl8373_igmpgroup *grp) +{ + ret_t retVal; + rtk_uint32 regAddr, regData; + rtk_uint32 groupInfo = 0; + + if(idx > RTL8373_IGMP_MAX_GOUP) + return RT_ERR_OUT_OF_RANGE; + + + /* Write ACS_ADR register for data bits */ + regAddr = RTL8373_ITA_CTRL0_ADDR; + regData = (1|(TB_OP_READ << 1)|(TB_TARGET_IGMP_GROUP << 8)|(idx<<16)); + + retVal = rtl8373_setAsicReg(regAddr, regData); + if(retVal != RT_ERR_OK) + return retVal; + + /* Write ACS_CMD register + regAddr = RTL8373_TABLE_ACCESS_CTRL_REG; + regData = RTL8373_TABLE_ACCESS_REG_DATA(TB_OP_READ, TB_TARGET_IGMP_GROUP); + retVal = rtl8373_setAsicRegBits(regAddr, RTL8373_TABLE_TYPE_MASK | RTL8373_COMMAND_TYPE_MASK, regData); + if(retVal != RT_ERR_OK) + return retVal;*/ + + retVal = rtl8373_getAsicReg(RTL8373_ITA_READ_DATA0_ADDR(0), &groupInfo); + if(retVal != RT_ERR_OK) + return retVal; + + grp->p0_timer = groupInfo & 0x00000007; + grp->p1_timer = (groupInfo >> 3) & 0x00000007; + grp->p2_timer = (groupInfo >> 6) & 0x00000007; + grp->p3_timer = (groupInfo >> 9) & 0x00000007; + grp->p4_timer = (groupInfo >> 12) & 0x00000007; + grp->p5_timer = (groupInfo >> 15) & 0x00000007; + grp->p6_timer = (groupInfo >> 18) & 0x00000007; + grp->p7_timer = (groupInfo >> 21) & 0x00000007; + grp->report_supp_flag = (groupInfo >> 24) & 0x00000001; + grp->p8_timer = (groupInfo >> 25) & 0x00000007; + grp->p9_timer = (groupInfo >> 28) & 0x00000007; + grp->p10_timer = (groupInfo >> 31) & 0x00000001; + + + retVal = rtl8373_getAsicReg(RTL8373_ITA_READ_DATA0_ADDR(1), ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + + grp->p10_timer |= (regData & 0x00000003) << 1; + + /* Valid bit */ + retVal = rtl8373_getAsicReg(RTL8373_IGMP_TBL_USAGE_ADDR(idx), ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + *valid = ((regData & (0x0001 << (idx %32))) != 0) ? 1 : 0; + + return RT_ERR_OK; +} +/* Function Name: + * rtk_igmp_groupInfo_get + * Description: + * Get IGMP/MLD Group database + * Input: + * indes - Index (0~255) + * Output: + * pGroup - Group database information. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * + */ +rtk_api_ret_t dal_rtl8373_igmp_groupInfo_get(rtk_uint32 index, rtk_igmp_groupInfo_t *pGroup) +{ + rtk_api_ret_t retVal; + rtk_uint32 valid; + rtl8373_igmpgroup grp; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check index */ + if(index > RTL8373_IGMP_MAX_GOUP) + return RT_ERR_INPUT; + + if(NULL == pGroup) + return RT_ERR_NULL_POINTER; + + if ((retVal = dal_rtl8373_getAsicIGMPGroup(index, &valid, &grp))!=RT_ERR_OK) + return retVal; + + memset(pGroup, 0x00, sizeof(rtk_igmp_groupInfo_t)); + pGroup->valid = valid; + pGroup->reportSuppFlag = grp.report_supp_flag; + + if(grp.p0_timer != 0) + { + RTK_PORTMASK_PORT_SET((pGroup->member), rtk_switch_port_P2L_get(0)); + pGroup->timer[rtk_switch_port_P2L_get(0)] = grp.p0_timer; + } + + if(grp.p1_timer != 0) + { + RTK_PORTMASK_PORT_SET((pGroup->member), rtk_switch_port_P2L_get(1)); + pGroup->timer[rtk_switch_port_P2L_get(1)] = grp.p1_timer; + } + + if(grp.p2_timer != 0) + { + RTK_PORTMASK_PORT_SET((pGroup->member), rtk_switch_port_P2L_get(2)); + pGroup->timer[rtk_switch_port_P2L_get(2)] = grp.p2_timer; + } + + if(grp.p3_timer != 0) + { + RTK_PORTMASK_PORT_SET((pGroup->member), rtk_switch_port_P2L_get(3)); + pGroup->timer[rtk_switch_port_P2L_get(3)] = grp.p3_timer; + } + + if(grp.p4_timer != 0) + { + RTK_PORTMASK_PORT_SET((pGroup->member), rtk_switch_port_P2L_get(4)); + pGroup->timer[rtk_switch_port_P2L_get(4)] = grp.p4_timer; + } + + if(grp.p5_timer != 0) + { + RTK_PORTMASK_PORT_SET((pGroup->member), rtk_switch_port_P2L_get(5)); + pGroup->timer[rtk_switch_port_P2L_get(5)] = grp.p5_timer; + } + + if(grp.p6_timer != 0) + { + RTK_PORTMASK_PORT_SET((pGroup->member), rtk_switch_port_P2L_get(6)); + pGroup->timer[rtk_switch_port_P2L_get(6)] = grp.p6_timer; + } + + if(grp.p7_timer != 0) + { + RTK_PORTMASK_PORT_SET((pGroup->member), rtk_switch_port_P2L_get(7)); + pGroup->timer[rtk_switch_port_P2L_get(7)] = grp.p7_timer; + } + + if(grp.p8_timer != 0) + { + RTK_PORTMASK_PORT_SET((pGroup->member), rtk_switch_port_P2L_get(8)); + pGroup->timer[rtk_switch_port_P2L_get(8)] = grp.p8_timer; + } + + if(grp.p9_timer != 0) + { + RTK_PORTMASK_PORT_SET((pGroup->member), rtk_switch_port_P2L_get(9)); + pGroup->timer[rtk_switch_port_P2L_get(9)] = grp.p9_timer; + } + + if(grp.p10_timer != 0) + { + RTK_PORTMASK_PORT_SET((pGroup->member), rtk_switch_port_P2L_get(10)); + pGroup->timer[rtk_switch_port_P2L_get(10)] = grp.p10_timer; + } + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_igmp_ReportLeaveFwdAction_set + * Description: + * Set Report Leave packet forwarding action + * Input: + * action - Action + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + * + */ +rtk_api_ret_t dal_rtl8373_igmp_ReportLeaveFwdAction_set(rtk_igmp_ReportLeaveFwdAct_t action) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + switch(action) + { + case IGMP_REPORT_LEAVE_TO_ROUTER: + regData = 1; + break; + case IGMP_REPORT_LEAVE_TO_ALLPORT: + regData = 2; + break; + case IGMP_REPORT_LEAVE_TO_ROUTER_PORT_ADV: + regData = 3; + break; + default: + return RT_ERR_INPUT; + } + + retVal = rtl8373_setAsicRegBits(RTL8373_IGMP_CTRL_ADDR, RTL8373_IGMP_CTRL_REPORT_LEAVE_FWD_MASK, regData); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_igmp_ReportLeaveFwdAction_get + * Description: + * Get Report Leave packet forwarding action + * Input: + * action - Action + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * RT_ERR_NULL_POINTER - Null Pointer + * Note: + * + */ +rtk_api_ret_t dal_rtl8373_igmp_ReportLeaveFwdAction_get(rtk_igmp_ReportLeaveFwdAct_t *pAction) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pAction) + return RT_ERR_NULL_POINTER; + + retVal = rtl8373_getAsicRegBits(RTL8373_IGMP_CTRL_ADDR, RTL8373_IGMP_CTRL_REPORT_LEAVE_FWD_MASK, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + + *pAction=regData; + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_igmp_dropLeaveZeroEnable_set + * Description: + * Set the function of droppping Leave packet with group IP = 0.0.0.0 + * Input: + * enabled - Action 1: drop, 0:pass + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + * + */ +rtk_api_ret_t dal_rtl8373_igmp_dropLeaveZeroEnable_set(rtk_enable_t enabled) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(enabled >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + retVal = rtl8373_setAsicRegBit(RTL8373_IGMP_CTRL_ADDR, RTL8373_IGMP_CTRL_DROP_LEAVE_ZERO_OFFSET, enabled); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; + +} + +/* Function Name: + * rtk_igmp_dropLeaveZeroEnable_get + * Description: + * Get the function of droppping Leave packet with group IP = 0.0.0.0 + * Input: + * None + * Output: + * pEnabled. - Action 1: drop, 0:pass + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * RT_ERR_NULL_POINTER - Null Pointer + * Note: + * + */ +rtk_api_ret_t dal_rtl8373_igmp_dropLeaveZeroEnable_get(rtk_enable_t *pEnabled) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pEnabled) + return RT_ERR_NULL_POINTER; + + retVal = rtl8373_getAsicRegBit(RTL8373_IGMP_CTRL_ADDR, RTL8373_IGMP_CTRL_DROP_LEAVE_ZERO_OFFSET, pEnabled); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; + +} + +/* Function Name: + * rtk_igmp_bypassGroupRange_set + * Description: + * Set Bypass group + * Input: + * group - bypassed group + * enabled - enabled 1: Bypassed, 0: not bypass + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + * + */ +rtk_api_ret_t dal_rtl8373_igmp_bypassGroupRange_set(rtk_igmp_bypassGroup_t group, rtk_enable_t enabled) +{ + rtk_api_ret_t retVal; + rtk_uint32 offset; + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(group >= IGMP_BYPASS_GROUP_END) + return RT_ERR_INPUT; + + if(enabled >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + switch(group) + { + case BYPASS_224_0_0_X: + offset = RTL8373_IGMP_CTRL_IGMP_MLD_IP4_BYPASS_224_0_0_OFFSET; + break; + case BYPASS_224_0_1_X: + offset = RTL8373_IGMP_CTRL_IGMP_MLD_IP4_BYPASS_224_0_1_OFFSET; + break; + case BYPASS_239_255_255_X: + offset = RTL8373_IGMP_CTRL_IGMP_MLD_IP4_BYPASS_239_255_255_OFFSET; + break; + case BYPASS_IPV6_00XX: + offset = RTL8373_IGMP_CTRL_IGMP_MLD_IP6_BYPASS_OFFSET; + break; + default: + return RT_ERR_INPUT; + } + + retVal = rtl8373_setAsicRegBit(RTL8373_IGMP_CTRL_ADDR, offset, enabled); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_igmp_bypassGroupRange_get + * Description: + * get Bypass group + * Input: + * group - bypassed group + * Output: + * pEnable - enabled 1: Bypassed, 0: not bypass + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * RT_ERR_NULL_POINTER - Null Pointer + * Note: + * + */ +rtk_api_ret_t dal_rtl8373_igmp_bypassGroupRange_get(rtk_igmp_bypassGroup_t group, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + rtk_uint32 offset; + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(group >= IGMP_BYPASS_GROUP_END) + return RT_ERR_INPUT; + + if(NULL == pEnable) + return RT_ERR_NULL_POINTER; + + switch(group) + { + case BYPASS_224_0_0_X: + offset = RTL8373_IGMP_CTRL_IGMP_MLD_IP4_BYPASS_224_0_0_OFFSET; + break; + case BYPASS_224_0_1_X: + offset = RTL8373_IGMP_CTRL_IGMP_MLD_IP4_BYPASS_224_0_1_OFFSET; + break; + case BYPASS_239_255_255_X: + offset = RTL8373_IGMP_CTRL_IGMP_MLD_IP4_BYPASS_239_255_255_OFFSET; + break; + case BYPASS_IPV6_00XX: + offset = RTL8373_IGMP_CTRL_IGMP_MLD_IP6_BYPASS_OFFSET; + break; + default: + return RT_ERR_INPUT; + } + + retVal = rtl8373_getAsicRegBit(RTL8373_IGMP_CTRL_ADDR, offset, pEnable); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_igmp.h b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_igmp.h new file mode 100755 index 00000000..8ff89e20 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_igmp.h @@ -0,0 +1,893 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8367/RTL8373 switch high-level API + * + * Feature : The file includes IGMP module high-layer API defination + * + */ + +#ifndef __DAL_RTL8373_IGMP_H__ +#define __DAL_RTL8373_IGMP_H__ + +#include +#include +#include + +#define RTL8373_MAX_LEAVE_TIMER (7) +#define RTL8373_MAX_QUERY_INT (0xFFFF) +#define RTL8373_MAX_ROB_VAR (7) + +#define RTL8373_IGMP_GOUP_NO (256) +#define RTL8373_IGMP_MAX_GOUP (0xFF) +#define RTL8373_IGMP_GRP_BLEN (3) +#define RTL8373_ROUTER_PORT_INVALID (0xF) + +enum RTL8373_IGMPTABLE_FULL_OP +{ + TABLE_FULL_FORWARD = 0, + TABLE_FULL_DROP, + TABLE_FULL_TRAP, + TABLE_FULL_OP_END +}; + +enum RTL8373_CRC_ERR_OP +{ + CRC_ERR_DROP = 0, + CRC_ERR_TRAP, + CRC_ERR_FORWARD, + CRC_ERR_OP_END +}; + +enum RTL8373_IGMP_MLD_PROTOCOL_OP +{ + PROTOCOL_OP_ASIC = 0, + PROTOCOL_OP_FLOOD, + PROTOCOL_OP_TRAP, + PROTOCOL_OP_DROP, + PROTOCOL_OP_END +}; + +enum RTL8373_IGMP_MLD_BYPASS_GROUP +{ + BYPASS_224_0_0_X = 0, + BYPASS_224_0_1_X, + BYPASS_239_255_255_X, + BYPASS_IPV6_00XX, + BYPASS_GROUP_END +}; + +typedef struct +{ + rtk_uint32 p0_timer; + rtk_uint32 p1_timer; + rtk_uint32 p2_timer; + rtk_uint32 p3_timer; + rtk_uint32 p4_timer; + rtk_uint32 p5_timer; + rtk_uint32 p6_timer; + rtk_uint32 p7_timer; + rtk_uint32 p8_timer; + rtk_uint32 p9_timer; + rtk_uint32 p10_timer; + rtk_uint32 report_supp_flag; + +}rtl8373_igmpgroup; + +/* Function Name: + * dal_rtl8373_setAsicIGMPIsoLeaky + * Description: + * Set Port Isolation leaky for IGMP/MLD packet + * Input: + * leaky - 1: Leaky, 0:not leaky + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +rtk_api_ret_t dal_rtl8373_setAsicIGMPIsoLeaky(rtk_uint32 leaky); + +/* Function Name: + * dal_rtl8373_getAsicIGMPIsoLeaky + * Description: + * Get Port Isolation leaky for IGMP/MLD packet + * Input: + * Noen + * Output: + * pLeaky - 1: Leaky, 0:not leaky + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +rtk_api_ret_t dal_rtl8373_getAsicIGMPIsoLeaky(rtk_uint32 *pLeaky); +/* Function Name: + * rtl8373_setAsicIGMPVLANLeaky + * Description: + * Set VLAN leaky for IGMP/MLD packet + * Input: + * leaky - 1: Leaky, 0:not leaky + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +rtk_api_ret_t dal_rtl8373_setAsicIGMPVLANLeaky(rtk_uint32 leaky); + +/* Function Name: + * rtl8373_getAsicIGMPVLANLeaky + * Description: + * Get VLAN leaky for IGMP/MLD packet + * Input: + * Noen + * Output: + * pLeaky - 1: Leaky, 0:not leaky + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +rtk_api_ret_t dal_rtl8373_getAsicIGMPVLANLeaky(rtk_uint32 *pLeaky); +/* Function Name: + * dal_rtl8373_setAsicIpMulticastVlanLeaky + * Description: + * Set IP multicast VLAN Leaky function + * Input: + * port - Physical port number (0~7) + * enabled - 1: enabled, 0: disabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * When enabling this function, + * if the lookup result(forwarding portmap) of IP Multicast packet is over VLAN boundary, + * the packet can be forwarded across VLAN + */ +rtk_api_ret_t dal_rtl8373_setAsicIpMulticastVlanLeaky(rtk_uint32 port, rtk_uint32 enabled); + +/* Function Name: + * dal_rtl8373_getAsicIpMulticastVlanLeaky + * Description: + * Get IP multicast VLAN Leaky function + * Input: + * port - Physical port number (0~7) + * enabled - 1: enabled, 0: disabled + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +rtk_api_ret_t dal_rtl8373_getAsicIpMulticastVlanLeaky(rtk_uint32 port, rtk_uint32 *ptr_enabled); + +/* Function Name: + * dal_rtl8373_getAsicIGMPGroup + * Description: + * Get IGMP group + * Input: + * idx - Group index (0~255) + * valid - valid bit + * grp - IGMP group + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - Group index is out of range + * Note: + * None + */ +rtk_api_ret_t dal_rtl8373_getAsicIGMPGroup(rtk_uint32 idx, rtk_uint32 *valid, rtl8373_igmpgroup *grp); + + + +/* Function Name: + * dal_rtl8373_igmp_init + * Description: + * This API enables H/W IGMP and set a default initial configuration. + * Input: + * None. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API enables H/W IGMP and set a default initial configuration. + */ +extern rtk_api_ret_t dal_rtl8373_igmp_init(void); + +/* Function Name: + * dal_rtl8373_igmp_state_set + * Description: + * This API set H/W IGMP state. + * Input: + * enabled - H/W IGMP state + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error parameter + * Note: + * This API set H/W IGMP state. + */ +extern rtk_api_ret_t dal_rtl8373_igmp_state_set(rtk_enable_t enabled); + +/* Function Name: + * dal_rtl8373_igmp_state_get + * Description: + * This API get H/W IGMP state. + * Input: + * None. + * Output: + * pEnabled - H/W IGMP state + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error parameter + * Note: + * This API set current H/W IGMP state. + */ +extern rtk_api_ret_t dal_rtl8373_igmp_state_get(rtk_enable_t *pEnabled); + +/* Function Name: + * dal_rtl8373_igmp_static_router_port_set + * Description: + * Configure static router port + * Input: + * pPortmask - Static Port mask + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Error parameter + * Note: + * This API set static router port + */ +extern rtk_api_ret_t dal_rtl8373_igmp_static_router_port_set(rtk_portmask_t *pPortmask); + +/* Function Name: + * dal_rtl8373_igmp_static_router_port_get + * Description: + * Get static router port + * Input: + * None. + * Output: + * pPortmask - Static port mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Error parameter + * Note: + * This API get static router port + */ +extern rtk_api_ret_t dal_rtl8373_igmp_static_router_port_get(rtk_portmask_t *pPortmask); + +/* Function Name: + * dal_rtl8373_igmp_protocol_set + * Description: + * set IGMP/MLD protocol action + * Input: + * port - Port ID + * protocol - IGMP/MLD protocol + * action - Per-port and per-protocol IGMP action seeting + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Error parameter + * Note: + * This API set IGMP/MLD protocol action + */ +extern rtk_api_ret_t dal_rtl8373_igmp_protocol_set(rtk_port_t port, rtk_igmp_protocol_t protocol, rtk_igmp_action_t action); + +/* Function Name: + * dal_rtl8373_igmp_protocol_get + * Description: + * set IGMP/MLD protocol action + * Input: + * port - Port ID + * protocol - IGMP/MLD protocol + * action - Per-port and per-protocol IGMP action seeting + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Error parameter + * Note: + * This API set IGMP/MLD protocol action + */ +extern rtk_api_ret_t dal_rtl8373_igmp_protocol_get(rtk_port_t port, rtk_igmp_protocol_t protocol, rtk_igmp_action_t *pAction); + +/* Function Name: + * dal_rtl8373_igmp_fastLeave_set + * Description: + * set IGMP/MLD FastLeave state + * Input: + * state - ENABLED: Enable FastLeave, DISABLED: disable FastLeave + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_INPUT - Error Input + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API set IGMP/MLD FastLeave state + */ +extern rtk_api_ret_t dal_rtl8373_igmp_fastLeave_set(rtk_enable_t state); + +/* Function Name: + * dal_rtl8373_igmp_fastLeave_get + * Description: + * get IGMP/MLD FastLeave state + * Input: + * None + * Output: + * pState - ENABLED: Enable FastLeave, DISABLED: disable FastLeave + * Return: + * RT_ERR_OK - OK + * RT_ERR_NULL_POINTER - NULL pointer + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API get IGMP/MLD FastLeave state + */ +extern rtk_api_ret_t dal_rtl8373_igmp_fastLeave_get(rtk_enable_t *pState); + +/* Function Name: + * dal_rtl8373_igmp_maxGroup_set + * Description: + * Set per port multicast group learning limit. + * Input: + * port - Port ID + * group - The number of multicast group learning limit. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_PORT_ID - Error Port ID + * RT_ERR_OUT_OF_RANGE - parameter out of range + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API set per port multicast group learning limit. + */ +extern rtk_api_ret_t dal_rtl8373_igmp_maxGroup_set(rtk_port_t port, rtk_uint32 group); + +/* Function Name: + * dal_rtl8373_igmp_maxGroup_get + * Description: + * Get per port multicast group learning limit. + * Input: + * port - Port ID + * Output: + * pGroup - The number of multicast group learning limit. + * Return: + * RT_ERR_OK - OK + * RT_ERR_PORT_ID - Error Port ID + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API get per port multicast group learning limit. + */ +extern rtk_api_ret_t dal_rtl8373_igmp_maxGroup_get(rtk_port_t port, rtk_uint32 *pGroup); + +/* Function Name: + * dal_rtl8373_igmp_currentGroup_get + * Description: + * Get per port multicast group learning count. + * Input: + * port - Port ID + * Output: + * pGroup - The number of multicast group learning count. + * Return: + * RT_ERR_OK - OK + * RT_ERR_PORT_ID - Error Port ID + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API get per port multicast group learning count. + */ +extern rtk_api_ret_t dal_rtl8373_igmp_currentGroup_get(rtk_port_t port, rtk_uint32 *pGroup); + +/* Function Name: + * dal_rtl8373_igmp_tableFullAction_set + * Description: + * set IGMP/MLD Table Full Action + * Input: + * action - Table Full Action + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_INPUT - Error Input + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +extern rtk_api_ret_t dal_rtl8373_igmp_tableFullAction_set(rtk_igmp_tableFullAction_t action); + +/* Function Name: + * dal_rtl8373_igmp_tableFullAction_get + * Description: + * get IGMP/MLD Table Full Action + * Input: + * None + * Output: + * pAction - Table Full Action + * Return: + * RT_ERR_OK - OK + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +extern rtk_api_ret_t dal_rtl8373_igmp_tableFullAction_get(rtk_igmp_tableFullAction_t *pAction); + +/* Function Name: + * dal_rtl8373_igmp_checksumErrorAction_set + * Description: + * set IGMP/MLD Checksum Error Action + * Input: + * action - Checksum error Action + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_INPUT - Error Input + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +extern rtk_api_ret_t dal_rtl8373_igmp_checksumErrorAction_set(rtk_igmp_checksumErrorAction_t action); + +/* Function Name: + * dal_rtl8373_igmp_checksumErrorAction_get + * Description: + * get IGMP/MLD Checksum Error Action + * Input: + * None + * Output: + * pAction - Checksum error Action + * Return: + * RT_ERR_OK - OK + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +extern rtk_api_ret_t dal_rtl8373_igmp_checksumErrorAction_get(rtk_igmp_checksumErrorAction_t *pAction); + +/* Function Name: + * dal_rtl8373_igmp_leaveTimer_set + * Description: + * set IGMP/MLD Leave timer + * Input: + * timer - Leave timer + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_INPUT - Error Input + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +extern rtk_api_ret_t dal_rtl8373_igmp_leaveTimer_set(rtk_uint32 timer); + +/* Function Name: + * dal_rtl8373_igmp_leaveTimer_get + * Description: + * get IGMP/MLD Leave timer + * Input: + * None + * Output: + * pTimer - Leave Timer. + * Return: + * RT_ERR_OK - OK + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +extern rtk_api_ret_t dal_rtl8373_igmp_leaveTimer_get(rtk_uint32 *pTimer); + +/* Function Name: + * dal_rtl8373_igmp_queryInterval_set + * Description: + * set IGMP/MLD Query Interval + * Input: + * interval - Query Interval + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_INPUT - Error Input + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +extern rtk_api_ret_t dal_rtl8373_igmp_queryInterval_set(rtk_uint32 interval); + +/* Function Name: + * dal_rtl8373_igmp_queryInterval_get + * Description: + * get IGMP/MLD Query Interval + * Input: + * None. + * Output: + * pInterval - Query Interval + * Return: + * RT_ERR_OK - OK + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +extern rtk_api_ret_t dal_rtl8373_igmp_queryInterval_get(rtk_uint32 *pInterval); + +/* Function Name: + * dal_rtl8373_igmp_robustness_set + * Description: + * set IGMP/MLD Robustness value + * Input: + * robustness - Robustness value + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_INPUT - Error Input + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +extern rtk_api_ret_t dal_rtl8373_igmp_robustness_set(rtk_uint32 robustness); + +/* Function Name: + * dal_rtl8373_igmp_robustness_get + * Description: + * get IGMP/MLD Robustness value + * Input: + * None + * Output: + * pRobustness - Robustness value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +extern rtk_api_ret_t dal_rtl8373_igmp_robustness_get(rtk_uint32 *pRobustness); + +/* Function Name: + * dal_rtl8373_igmp_dynamicRouterRortAllow_set + * Description: + * Configure dynamic router port allow option + * Input: + * pPortmask - Dynamic Port allow mask + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Error parameter + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8373_igmp_dynamicRouterPortAllow_set(rtk_portmask_t *pPortmask); + +/* Function Name: + * dal_rtl8373_igmp_dynamicRouterRortAllow_get + * Description: + * Get dynamic router port allow option + * Input: + * None. + * Output: + * pPortmask - Dynamic Port allow mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Error parameter + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8373_igmp_dynamicRouterPortAllow_get(rtk_portmask_t *pPortmask); + +/* Function Name: + * dal_rtl8373_igmp_dynamicRouterPort_get + * Description: + * Get dynamic router port + * Input: + * None. + * Output: + * pDynamicRouterPort - Dynamic Router Port + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Error parameter + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8373_igmp_dynamicRouterPort_get(rtk_igmp_dynamicRouterPort_t *pDynamicRouterPort); + +/* Function Name: + * dal_rtl8373_igmp_suppressionEnable_set + * Description: + * Configure IGMPv1/v2 & MLDv1 Report/Leave/Done suppression + * Input: + * reportSuppression - Report suppression + * leaveSuppression - Leave suppression + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8373_igmp_suppressionEnable_set(rtk_enable_t reportSuppression, rtk_enable_t leaveSuppression); + +/* Function Name: + * dal_rtl8373_igmp_suppressionEnable_get + * Description: + * Get IGMPv1/v2 & MLDv1 Report/Leave/Done suppression + * Input: + * None + * Output: + * pReportSuppression - Report suppression + * pLeaveSuppression - Leave suppression + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8373_igmp_suppressionEnable_get(rtk_enable_t *pReportSuppression, rtk_enable_t *pLeaveSuppression); + +/* Function Name: + * dal_rtl8373_igmp_portRxPktEnable_set + * Description: + * Configure IGMP/MLD RX Packet configuration + * Input: + * port - Port ID + * pRxCfg - RX Packet Configuration + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8373_igmp_portRxPktEnable_set(rtk_port_t port, rtk_igmp_rxPktEnable_t *pRxCfg); + +/* Function Name: + * dal_rtl8373_igmp_portRxPktEnable_get + * Description: + * Get IGMP/MLD RX Packet configuration + * Input: + * port - Port ID + * pRxCfg - RX Packet Configuration + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8373_igmp_portRxPktEnable_get(rtk_port_t port, rtk_igmp_rxPktEnable_t *pRxCfg); +/* Function Name: + * dal_rtl8373_setAsicIGMPBypassStormCTRL + * Description: + * Set the function of bypass strom control for IGMP/MLD packet + * Input: + * bypass - 1: Bypass, 0:not bypass + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +extern rtk_api_ret_t dal_rtl8373_setAsicIGMPBypassStormCTRL(rtk_uint32 bypass); + +/* Function Name: + * dal_rtl8373_getAsicIGMPBypassStormCTRL + * Description: + * Set the function of bypass strom control for IGMP/MLD packet + * Input: + * None + * Output: + * pBypass - 1: Bypass, 0:not bypass + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +extern rtk_api_ret_t dal_rtl8373_getAsicIGMPBypassStormCTRL(rtk_uint32 *pBypass); +/* Function Name: + * dal_rtl8373_igmp_groupInfo_get + * Description: + * Get IGMP/MLD Group database + * Input: + * indes - Index (0~255) + * Output: + * pGroup - Group database information. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8373_igmp_groupInfo_get(rtk_uint32 index, rtk_igmp_groupInfo_t *pGroup); + +/* Function Name: + * dal_rtl8373_igmp_ReportLeaveFwdAction_set + * Description: + * Set Report Leave packet forwarding action + * Input: + * action - Action + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8373_igmp_ReportLeaveFwdAction_set(rtk_igmp_ReportLeaveFwdAct_t action); + +/* Function Name: + * dal_rtl8373_igmp_ReportLeaveFwdAction_get + * Description: + * Get Report Leave packet forwarding action + * Input: + * action - Action + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * RT_ERR_NULL_POINTER - Null Pointer + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8373_igmp_ReportLeaveFwdAction_get(rtk_igmp_ReportLeaveFwdAct_t *pAction); + +/* Function Name: + * dal_rtl8373_igmp_dropLeaveZeroEnable_set + * Description: + * Set the function of droppping Leave packet with group IP = 0.0.0.0 + * Input: + * enabled - Action 1: drop, 0:pass + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8373_igmp_dropLeaveZeroEnable_set(rtk_enable_t enabled); + +/* Function Name: + * dal_rtl8373_igmp_dropLeaveZeroEnable_get + * Description: + * Get the function of droppping Leave packet with group IP = 0.0.0.0 + * Input: + * None + * Output: + * pEnabled. - Action 1: drop, 0:pass + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * RT_ERR_NULL_POINTER - Null Pointer + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8373_igmp_dropLeaveZeroEnable_get(rtk_enable_t *pEnabled); + +/* Function Name: + * dal_rtl8373_igmp_bypassGroupRange_set + * Description: + * Set Bypass group + * Input: + * group - bypassed group + * enabled - enabled 1: Bypassed, 0: not bypass + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8373_igmp_bypassGroupRange_set(rtk_igmp_bypassGroup_t group, rtk_enable_t enabled); + +/* Function Name: + * dal_rtl8373_igmp_bypassGroupRange_get + * Description: + * get Bypass group + * Input: + * group - bypassed group + * Output: + * pEnable - enabled 1: Bypassed, 0: not bypass + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * RT_ERR_NULL_POINTER - Null Pointer + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8373_igmp_bypassGroupRange_get(rtk_igmp_bypassGroup_t group, rtk_enable_t *pEnable); + +#endif /* __DAL_RTL8373_IGMP_H__ */ diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_interrupt.c b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_interrupt.c new file mode 100755 index 00000000..50560240 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_interrupt.c @@ -0,0 +1,2723 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8373 + * Feature : Here is a list of all functions and variables in interrupt module. + * + */ + +#include +#include +#include +#include +#include + + + +/* Function Name: + * dal_rtl8373_intMode_set + * Description: + * Set interrupt mode + * Input: + * mode : 0 high; 1: low; 2 positive pulse; 3 negative pulse + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ +rtk_api_ret_t dal_rtl8373_intMode_set(rtk_int_polarity_t mode) +{ + rtk_api_ret_t retVal; + + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_ISR_SW_INT_MODE_ADDR, RTL8373_ISR_SW_INT_MODE_SW_INT_MODE_MASK, mode)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + + +/* Function Name: + * dal_rtl8373_intMode_get + * Description: + * Set interrupt mode + * Input: + * pMode : 0 high; 1: low; 2 positive pulse; 3 negative pulse + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ +rtk_api_ret_t dal_rtl8373_intMode_get(rtk_int_polarity_t* pMode) +{ + rtk_api_ret_t retVal; + + + if ((retVal = rtl8373_getAsicRegBits(RTL8373_ISR_SW_INT_MODE_ADDR, RTL8373_ISR_SW_INT_MODE_SW_INT_MODE_MASK, pMode)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + + +/* Function Name: + * dal_rtl8373_portLinkChgIMR_set + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ +rtk_api_ret_t dal_rtl8373_portLinkChgIMR_set(rtk_uint32 type, rtk_uint32 port, rtk_uint32 enable) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + + /*internal interrupt*/ + if(type == 0) + { + if ((retVal = rtl8373_getAsicReg(RTL8373_IMR_INT_PORT_LINK_STS_CHG_ADDR, ®Data)) != RT_ERR_OK) + return retVal; + + if(enable == 1) + regData |= (1 << port); + else + regData &= ~(1 << port); + + if ((retVal = rtl8373_setAsicReg(RTL8373_IMR_INT_PORT_LINK_STS_CHG_ADDR, regData)) != RT_ERR_OK) + return retVal; + } + else /*external interrupt*/ + { + if ((retVal = rtl8373_getAsicReg(RTL8373_IMR_EXT_PORT_LINK_STS_CHG_ADDR, ®Data)) != RT_ERR_OK) + return retVal; + + if(enable == 1) + regData |= (1 << port); + else + regData &= ~(1 << port); + + if ((retVal = rtl8373_setAsicReg(RTL8373_IMR_INT_PORT_LINK_STS_CHG_ADDR, regData)) != RT_ERR_OK) + return retVal; + } + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_portLinkChgIMR_get + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ + +rtk_api_ret_t dal_rtl8373_portLinkChgIMR_get(rtk_uint32 type, rtk_uint32 port, rtk_uint32* pEnable) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + + /*internal interrupt*/ + if(type == 0) + { + if ((retVal = rtl8373_getAsicReg(RTL8373_IMR_INT_PORT_LINK_STS_CHG_ADDR, ®Data)) != RT_ERR_OK) + return retVal; + + *pEnable = (regData >> port) & 1; + } + else /*external interrupt*/ + { + if ((retVal = rtl8373_getAsicReg(RTL8373_IMR_EXT_PORT_LINK_STS_CHG_ADDR, ®Data)) != RT_ERR_OK) + return retVal; + + *pEnable = (regData >> port) & 1; + } + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_gphyIMR_set + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * gphy: gphy id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ +rtk_api_ret_t dal_rtl8373_gphyIMR_set(rtk_uint32 type, rtk_uint32 phy, rtk_uint32 enable) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + + /*internal interrupt*/ + if(type == 0) + { + if ((retVal = rtl8373_getAsicReg(RTL8373_IMR_INT_GPHY_ADDR, ®Data)) != RT_ERR_OK) + return retVal; + + if(enable == 1) + regData |= (1 << phy); + else + regData &= ~(1 << phy); + + if ((retVal = rtl8373_setAsicReg(RTL8373_IMR_INT_GPHY_ADDR, regData)) != RT_ERR_OK) + return retVal; + } + else /*external interrupt*/ + { + if ((retVal = rtl8373_getAsicReg(RTL8373_IMR_EXT_GPHY_ADDR, ®Data)) != RT_ERR_OK) + return retVal; + + if(enable == 1) + regData |= (1 << phy); + else + regData &= ~(1 << phy); + + if ((retVal = rtl8373_setAsicReg(RTL8373_IMR_EXT_GPHY_ADDR, regData)) != RT_ERR_OK) + return retVal; + } + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_gphyIMR_get + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ + +rtk_api_ret_t dal_rtl8373_gphyIMR_get(rtk_uint32 type, rtk_uint32 phy, rtk_uint32* pEnable) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + + /*internal interrupt*/ + if(type == 0) + { + if ((retVal = rtl8373_getAsicReg(RTL8373_IMR_INT_GPHY_ADDR, ®Data)) != RT_ERR_OK) + return retVal; + + *pEnable = (regData >> phy) & 1; + } + else /*external interrupt*/ + { + if ((retVal = rtl8373_getAsicReg(RTL8373_IMR_EXT_GPHY_ADDR, ®Data)) != RT_ERR_OK) + return retVal; + + *pEnable = (regData >> phy) & 1; + } + return RT_ERR_OK; +} + + + +/* Function Name: + * dal_rtl8373_portLrnOverIMR_set + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ +rtk_api_ret_t dal_rtl8373_portLrnOverIMR_set(rtk_uint32 type, rtk_uint32 port, rtk_uint32 enable) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + + /*internal interrupt*/ + if(type == 0) + { + if ((retVal = rtl8373_getAsicReg(RTL8373_IMR_INT_LEARNOVER_ADDR, ®Data)) != RT_ERR_OK) + return retVal; + + if(enable == 1) + regData |= (1 << port); + else + regData &= ~(1 << port); + + if ((retVal = rtl8373_setAsicReg(RTL8373_IMR_INT_LEARNOVER_ADDR, regData)) != RT_ERR_OK) + return retVal; + } + else /*external interrupt*/ + { + if ((retVal = rtl8373_getAsicReg(RTL8373_IMR_EXT_LEARNOVER_ADDR, ®Data)) != RT_ERR_OK) + return retVal; + + if(enable == 1) + regData |= (1 << port); + else + regData &= ~(1 << port); + + if ((retVal = rtl8373_setAsicReg(RTL8373_IMR_EXT_LEARNOVER_ADDR, regData)) != RT_ERR_OK) + return retVal; + } + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_portLrnOverIMR_get + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ + +rtk_api_ret_t dal_rtl8373_portLrnOverIMR_get(rtk_uint32 type, rtk_uint32 port, rtk_uint32* pEnable) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + + /*internal interrupt*/ + if(type == 0) + { + if ((retVal = rtl8373_getAsicReg(RTL8373_IMR_INT_LEARNOVER_ADDR, ®Data)) != RT_ERR_OK) + return retVal; + + *pEnable = (regData >> port) & 1; + } + else /*external interrupt*/ + { + if ((retVal = rtl8373_getAsicReg(RTL8373_IMR_EXT_LEARNOVER_ADDR, ®Data)) != RT_ERR_OK) + return retVal; + + *pEnable = (regData >> port) & 1; + } + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_portRLFDIMR_set + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ +rtk_api_ret_t dal_rtl8373_portRLFDIMR_set(rtk_uint32 type, rtk_uint32 port, rtk_uint32 enable) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + + /*internal interrupt*/ + if(type == 0) + { + if ((retVal = rtl8373_getAsicReg(RTL8373_IMR_INT_RLFD_ADDR, ®Data)) != RT_ERR_OK) + return retVal; + + if(enable == 1) + regData |= (1 << port); + else + regData &= ~(1 << port); + + if ((retVal = rtl8373_setAsicReg(RTL8373_IMR_INT_RLFD_ADDR, regData)) != RT_ERR_OK) + return retVal; + } + else /*external interrupt*/ + { + if ((retVal = rtl8373_getAsicReg(RTL8373_IMR_EXT_RLFD_ADDR, ®Data)) != RT_ERR_OK) + return retVal; + + if(enable == 1) + regData |= (1 << port); + else + regData &= ~(1 << port); + + if ((retVal = rtl8373_setAsicReg(RTL8373_IMR_EXT_RLFD_ADDR, regData)) != RT_ERR_OK) + return retVal; + } + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_portRLFDIMR_get + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ + +rtk_api_ret_t dal_rtl8373_portRLFDIMR_get(rtk_uint32 type, rtk_uint32 port, rtk_uint32* pEnable) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + + /*internal interrupt*/ + if(type == 0) + { + if ((retVal = rtl8373_getAsicReg(RTL8373_IMR_INT_RLFD_ADDR, ®Data)) != RT_ERR_OK) + return retVal; + + *pEnable = (regData >> port) & 1; + } + else /*external interrupt*/ + { + if ((retVal = rtl8373_getAsicReg(RTL8373_IMR_EXT_RLFD_ADDR, ®Data)) != RT_ERR_OK) + return retVal; + + *pEnable = (regData >> port) & 1; + } + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_portWolIMR_set + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ +rtk_api_ret_t dal_rtl8373_portWolIMR_set(rtk_uint32 type, rtk_uint32 port, rtk_uint32 enable) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + + /*internal interrupt*/ + if(type == 0) + { + if ((retVal = rtl8373_getAsicReg(RTL8373_IMR_INT_WOL_ADDR, ®Data)) != RT_ERR_OK) + return retVal; + + if(enable == 1) + regData |= (1 << port); + else + regData &= ~(1 << port); + + if ((retVal = rtl8373_setAsicReg(RTL8373_IMR_INT_WOL_ADDR, regData)) != RT_ERR_OK) + return retVal; + } + else /*external interrupt*/ + { + if ((retVal = rtl8373_getAsicReg(RTL8373_IMR_EXT_WOL_ADDR, ®Data)) != RT_ERR_OK) + return retVal; + + if(enable == 1) + regData |= (1 << port); + else + regData &= ~(1 << port); + + if ((retVal = rtl8373_setAsicReg(RTL8373_IMR_EXT_WOL_ADDR, regData)) != RT_ERR_OK) + return retVal; + } + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_portWolIMR_get + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ + +rtk_api_ret_t dal_rtl8373_portWolIMR_get(rtk_uint32 type, rtk_uint32 port, rtk_uint32* pEnable) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + + /*internal interrupt*/ + if(type == 0) + { + if ((retVal = rtl8373_getAsicReg(RTL8373_IMR_INT_WOL_ADDR, ®Data)) != RT_ERR_OK) + return retVal; + + *pEnable = (regData >> port) & 1; + } + else /*external interrupt*/ + { + if ((retVal = rtl8373_getAsicReg(RTL8373_IMR_EXT_WOL_ADDR, ®Data)) != RT_ERR_OK) + return retVal; + + *pEnable = (regData >> port) & 1; + } + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_portSdsLnkFltIMR_set + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ +rtk_api_ret_t dal_rtl8373_portSdsLnkFltIMR_set(rtk_uint32 type, rtk_uint32 sds, rtk_uint32 enable) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + + /*internal interrupt*/ + if(type == 0) + { + if ((retVal = rtl8373_getAsicReg(RTL8373_IMR_INT_SERDES_LINK_FAULT_P_ADDR, ®Data)) != RT_ERR_OK) + return retVal; + + if(enable == 1) + regData |= (1 << sds); + else + regData &= ~(1 << sds); + + if ((retVal = rtl8373_setAsicReg(RTL8373_IMR_INT_SERDES_LINK_FAULT_P_ADDR, regData)) != RT_ERR_OK) + return retVal; + } + else /*external interrupt*/ + { + if ((retVal = rtl8373_getAsicReg(RTL8373_IMR_EXT_SERDES_LINK_FAULT_P_ADDR, ®Data)) != RT_ERR_OK) + return retVal; + + if(enable == 1) + regData |= (1 << sds); + else + regData &= ~(1 << sds); + + if ((retVal = rtl8373_setAsicReg(RTL8373_IMR_EXT_SERDES_LINK_FAULT_P_ADDR, regData)) != RT_ERR_OK) + return retVal; + } + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_portSdsLnkFltIMR_get + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ + +rtk_api_ret_t dal_rtl8373_portSdsLnkFltIMR_get(rtk_uint32 type, rtk_uint32 sds, rtk_uint32* pEnable) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + + /*internal interrupt*/ + if(type == 0) + { + if ((retVal = rtl8373_getAsicReg(RTL8373_IMR_INT_SERDES_LINK_FAULT_P_ADDR, ®Data)) != RT_ERR_OK) + return retVal; + + *pEnable = (regData >> sds) & 1; + } + else /*external interrupt*/ + { + if ((retVal = rtl8373_getAsicReg(RTL8373_IMR_EXT_SERDES_LINK_FAULT_P_ADDR, ®Data)) != RT_ERR_OK) + return retVal; + + *pEnable = (regData >> sds) & 1; + } + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_portSdsUpdPhyIMR_set + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ +rtk_api_ret_t dal_rtl8373_portSdsUpdPhyIMR_set(rtk_uint32 type, rtk_uint32 sds, rtk_uint32 enable) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + + /*internal interrupt*/ + if(type == 0) + { + if ((retVal = rtl8373_getAsicReg(RTL8373_IMR_INT_SDS_UPD_PHYSTS0_ADDR, ®Data)) != RT_ERR_OK) + return retVal; + + if(enable == 1) + regData |= (1 << sds); + else + regData &= ~(1 << sds); + + if ((retVal = rtl8373_setAsicReg(RTL8373_IMR_INT_SDS_UPD_PHYSTS0_ADDR, regData)) != RT_ERR_OK) + return retVal; + } + else /*external interrupt*/ + { + if ((retVal = rtl8373_getAsicReg(RTL8373_IMR_EXT_SDS_UPD_PHYSTS0_ADDR, ®Data)) != RT_ERR_OK) + return retVal; + + if(enable == 1) + regData |= (1 << sds); + else + regData &= ~(1 << sds); + + if ((retVal = rtl8373_setAsicReg(RTL8373_IMR_EXT_SDS_UPD_PHYSTS0_ADDR, regData)) != RT_ERR_OK) + return retVal; + } + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_portSdsUpdPhyIMR_get + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ + +rtk_api_ret_t dal_rtl8373_portSdsUpdPhyIMR_get(rtk_uint32 type, rtk_uint32 sds, rtk_uint32* pEnable) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + + /*internal interrupt*/ + if(type == 0) + { + if ((retVal = rtl8373_getAsicReg(RTL8373_IMR_INT_SDS_UPD_PHYSTS0_ADDR, ®Data)) != RT_ERR_OK) + return retVal; + + *pEnable = (regData >> sds) & 1; + } + else /*external interrupt*/ + { + if ((retVal = rtl8373_getAsicReg(RTL8373_IMR_EXT_SDS_UPD_PHYSTS0_ADDR, ®Data)) != RT_ERR_OK) + return retVal; + + *pEnable = (regData >> sds) & 1; + } + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_gpioIMR_set + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ +rtk_api_ret_t dal_rtl8373_gpioIMR_set(rtk_uint32 type, rtk_uint32 gpio, rtk_uint32 enable) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + + /*internal interrupt*/ + if(type == 0) + { + if ((retVal = rtl8373_getAsicReg(RTL8373_IMR_INT_GPIO_ADDR, ®Data)) != RT_ERR_OK) + return retVal; + + if(enable == 1) + regData |= (1 << gpio); + else + regData &= ~(1 << gpio); + + if ((retVal = rtl8373_setAsicReg(RTL8373_IMR_INT_GPIO_ADDR, regData)) != RT_ERR_OK) + return retVal; + } + else /*external interrupt*/ + { + if ((retVal = rtl8373_getAsicReg(RTL8373_IMR_EXT_GPIO_ADDR, ®Data)) != RT_ERR_OK) + return retVal; + + if(enable == 1) + regData |= (1 << gpio); + else + regData &= ~(1 << gpio); + + if ((retVal = rtl8373_setAsicReg(RTL8373_IMR_EXT_GPIO_ADDR, regData)) != RT_ERR_OK) + return retVal; + } + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_gpioIMR_get + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ + +rtk_api_ret_t dal_rtl8373_gpioIMR_get(rtk_uint32 type, rtk_uint32 gpio, rtk_uint32* pEnable) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + + /*internal interrupt*/ + if(type == 0) + { + if ((retVal = rtl8373_getAsicReg(RTL8373_IMR_INT_GPIO_ADDR, ®Data)) != RT_ERR_OK) + return retVal; + + *pEnable = (regData >> gpio) & 1; + } + else /*external interrupt*/ + { + if ((retVal = rtl8373_getAsicReg(RTL8373_IMR_EXT_GPIO_ADDR, ®Data)) != RT_ERR_OK) + return retVal; + + *pEnable = (regData >> gpio) & 1; + } + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_miscIMR_set + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ +rtk_api_ret_t dal_rtl8373_miscIMR_set(rtk_uint32 type, interrupt_misc_t interrupt, rtk_uint32 enable) +{ + rtk_api_ret_t retVal; + + if(type == 0) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_IMR_INT_MISC_ADDR, interrupt, enable)) != RT_ERR_OK) + return retVal; + } + else + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_IMR_EXT_MISC_ADDR, interrupt, enable)) != RT_ERR_OK) + return retVal; + } + +#if 0 + /*internal interrupt*/ + if(type == 0) + { + if (interrupt == TM_HIGH) + { + if(enable == 1) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_IMR_INT_MISC_ADDR, RTL8373_IMR_INT_MISC_IMR_INT_TM_HIGH_OFFSET, 1)) != RT_ERR_OK) + return retVal; + } + else + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_IMR_INT_MISC_ADDR, RTL8373_IMR_INT_MISC_IMR_INT_TM_HIGH_OFFSET, 0)) != RT_ERR_OK) + return retVal; + } + } + else if (interrupt == TM_LOW) + { + if(enable == 1) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_IMR_INT_MISC_ADDR, RTL8373_IMR_INT_MISC_IMR_INT_TM_LOW_OFFSET, 1)) != RT_ERR_OK) + return retVal; + } + else + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_IMR_INT_MISC_ADDR, RTL8373_IMR_INT_MISC_IMR_INT_TM_LOW_OFFSET, 0)) != RT_ERR_OK) + return retVal; + } + } + else if (interrupt == SMI_CHECK_REG_0) + { + if(enable == 1) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_IMR_INT_MISC_ADDR, (1 << 2), 1)) != RT_ERR_OK) + return retVal; + } + else + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_IMR_INT_MISC_ADDR, (1 << 2), 0)) != RT_ERR_OK) + return retVal; + } + } + else if (interrupt == SMI_CHECK_REG_1) + { + if(enable == 1) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_IMR_INT_MISC_ADDR, (1 << 3), 1)) != RT_ERR_OK) + return retVal; + } + else + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_IMR_INT_MISC_ADDR, (1 << 3), 0)) != RT_ERR_OK) + return retVal; + } + } + else if (interrupt == SMI_CHECK_REG_2) + { + if(enable == 1) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_IMR_INT_MISC_ADDR, (1 << 4), 1)) != RT_ERR_OK) + return retVal; + } + else + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_IMR_INT_MISC_ADDR, (1 << 4), 0)) != RT_ERR_OK) + return retVal; + } + } + else if (interrupt == SMI_CHECK_REG_3) + { + if(enable == 1) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_IMR_INT_MISC_ADDR, (1 << 5), 1)) != RT_ERR_OK) + return retVal; + } + else + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_IMR_INT_MISC_ADDR, (1 << 5), 0)) != RT_ERR_OK) + return retVal; + } + } + else if (interrupt == SMI_CHECK_REG_4) + { + if(enable == 1) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_IMR_INT_MISC_ADDR, (1 << 6), 1)) != RT_ERR_OK) + return retVal; + } + else + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_IMR_INT_MISC_ADDR, (1 << 6), 0)) != RT_ERR_OK) + return retVal; + } + } + else if (interrupt == SDS_RX_SYM_ERR_0) + { + if(enable == 1) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_IMR_INT_MISC_ADDR, (1 << 7), 1)) != RT_ERR_OK) + return retVal; + } + else + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_IMR_INT_MISC_ADDR, (1 << 7), 0)) != RT_ERR_OK) + return retVal; + } + } + else if (interrupt == SDS_RX_SYM_ERR_1) + { + if(enable == 1) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_IMR_INT_MISC_ADDR, (1 << 8), 1)) != RT_ERR_OK) + return retVal; + } + else + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_IMR_INT_MISC_ADDR, (1 << 8), 0)) != RT_ERR_OK) + return retVal; + } + } + else if (interrupt == SAMOVE) + { + if(enable == 1) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_IMR_INT_MISC_ADDR, RTL8373_IMR_INT_MISC_IMR_INT_SAMOVE_OFFSET, 1)) != RT_ERR_OK) + return retVal; + } + else + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_IMR_INT_MISC_ADDR, RTL8373_IMR_INT_MISC_IMR_INT_SAMOVE_OFFSET, 0)) != RT_ERR_OK) + return retVal; + } + } + else if (interrupt == AUTO_REC) + { + if(enable == 1) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_IMR_INT_MISC_ADDR, RTL8373_IMR_INT_MISC_IMR_INT_AUTO_REC_OFFSET, 1)) != RT_ERR_OK) + return retVal; + } + else + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_IMR_INT_MISC_ADDR, RTL8373_IMR_INT_MISC_IMR_INT_AUTO_REC_OFFSET, 0)) != RT_ERR_OK) + return retVal; + } + } + else if (interrupt == ACL) + { + if(enable == 1) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_IMR_INT_MISC_ADDR, RTL8373_IMR_INT_MISC_IMR_INT_ACL_OFFSET, 1)) != RT_ERR_OK) + return retVal; + } + else + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_IMR_INT_MISC_ADDR, RTL8373_IMR_INT_MISC_IMR_INT_ACL_OFFSET, 0)) != RT_ERR_OK) + return retVal; + } + } + else if (interrupt == LOOP_DETEC) + { + if(enable == 1) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_IMR_INT_MISC_ADDR, RTL8373_IMR_INT_MISC_IMR_INT_LOOP_DETECTION_OFFSET, 1)) != RT_ERR_OK) + return retVal; + } + else + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_IMR_INT_MISC_ADDR, RTL8373_IMR_INT_MISC_IMR_INT_LOOP_DETECTION_OFFSET, 0)) != RT_ERR_OK) + return retVal; + } + } + else if (interrupt == METER_EXCEED) + { + if(enable == 1) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_IMR_INT_MISC_ADDR, RTL8373_IMR_INT_MISC_IMR_INT_METER_EXCEED_OFFSET, 1)) != RT_ERR_OK) + return retVal; + } + else + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_IMR_INT_MISC_ADDR, RTL8373_IMR_INT_MISC_IMR_INT_METER_EXCEED_OFFSET, 0)) != RT_ERR_OK) + return retVal; + } + } + else if (interrupt == ROUT_PBUF) + { + if(enable == 1) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_IMR_INT_MISC_ADDR, RTL8373_IMR_INT_MISC_IMR_INT_ROUT_PBUF_OFFSET, 1)) != RT_ERR_OK) + return retVal; + } + else + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_IMR_INT_MISC_ADDR, RTL8373_IMR_INT_MISC_IMR_INT_ROUT_PBUF_OFFSET, 0)) != RT_ERR_OK) + return retVal; + } + } + else if (interrupt == PTP1588) + { + if(enable == 1) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_IMR_INT_MISC_ADDR, RTL8373_IMR_INT_MISC_IMR_INT_PTP1588_OFFSET, 1)) != RT_ERR_OK) + return retVal; + } + else + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_IMR_INT_MISC_ADDR, RTL8373_IMR_INT_MISC_IMR_INT_PTP1588_OFFSET, 0)) != RT_ERR_OK) + return retVal; + } + } + } + else /*external interrupt*/ + { + if (interrupt == TM_HIGH) + { + if(enable == 1) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_IMR_EXT_MISC_ADDR, RTL8373_IMR_EXT_MISC_IMR_EXT_TM_HIGH_OFFSET, 1)) != RT_ERR_OK) + return retVal; + } + else + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_IMR_EXT_MISC_ADDR, RTL8373_IMR_EXT_MISC_IMR_EXT_TM_HIGH_OFFSET, 0)) != RT_ERR_OK) + return retVal; + } + } + else if (interrupt == TM_LOW) + { + if(enable == 1) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_IMR_EXT_MISC_ADDR, RTL8373_IMR_EXT_MISC_IMR_EXT_TM_LOW_OFFSET, 1)) != RT_ERR_OK) + return retVal; + } + else + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_IMR_EXT_MISC_ADDR, RTL8373_IMR_EXT_MISC_IMR_EXT_TM_LOW_OFFSET, 0)) != RT_ERR_OK) + return retVal; + } + } + else if (interrupt == SMI_CHECK_REG_0) + { + if(enable == 1) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_IMR_EXT_MISC_ADDR, (1 << 2), 1)) != RT_ERR_OK) + return retVal; + } + else + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_IMR_EXT_MISC_ADDR, (1 << 2), 0)) != RT_ERR_OK) + return retVal; + } + } + else if (interrupt == SMI_CHECK_REG_1) + { + if(enable == 1) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_IMR_EXT_MISC_ADDR, (1 << 3), 1)) != RT_ERR_OK) + return retVal; + } + else + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_IMR_EXT_MISC_ADDR, (1 << 3), 0)) != RT_ERR_OK) + return retVal; + } + } + else if (interrupt == SMI_CHECK_REG_2) + { + if(enable == 1) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_IMR_EXT_MISC_ADDR, (1 << 4), 1)) != RT_ERR_OK) + return retVal; + } + else + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_IMR_EXT_MISC_ADDR, (1 << 4), 0)) != RT_ERR_OK) + return retVal; + } + } + else if (interrupt == SMI_CHECK_REG_3) + { + if(enable == 1) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_IMR_EXT_MISC_ADDR, (1 << 5), 1)) != RT_ERR_OK) + return retVal; + } + else + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_IMR_EXT_MISC_ADDR, (1 << 5), 0)) != RT_ERR_OK) + return retVal; + } + } + else if (interrupt == SMI_CHECK_REG_4) + { + if(enable == 1) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_IMR_EXT_MISC_ADDR, (1 << 6), 1)) != RT_ERR_OK) + return retVal; + } + else + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_IMR_EXT_MISC_ADDR, (1 << 6), 0)) != RT_ERR_OK) + return retVal; + } + } + else if (interrupt == SDS_RX_SYM_ERR_0) + { + if(enable == 1) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_IMR_EXT_MISC_ADDR, (1 << 7), 1)) != RT_ERR_OK) + return retVal; + } + else + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_IMR_EXT_MISC_ADDR, (1 << 7), 0)) != RT_ERR_OK) + return retVal; + } + } + else if (interrupt == SDS_RX_SYM_ERR_1) + { + if(enable == 1) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_IMR_EXT_MISC_ADDR, (1 << 8), 1)) != RT_ERR_OK) + return retVal; + } + else + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_IMR_EXT_MISC_ADDR, (1 << 8), 0)) != RT_ERR_OK) + return retVal; + } + } + else if (interrupt == SAMOVE) + { + if(enable == 1) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_IMR_EXT_MISC_ADDR, RTL8373_IMR_EXT_MISC_IMR_EXT_SAMOVE_OFFSET, 1)) != RT_ERR_OK) + return retVal; + } + else + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_IMR_EXT_MISC_ADDR, RTL8373_IMR_EXT_MISC_IMR_EXT_SAMOVE_OFFSET, 0)) != RT_ERR_OK) + return retVal; + } + } + else if (interrupt == AUTO_REC) + { + if(enable == 1) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_IMR_EXT_MISC_ADDR, RTL8373_IMR_EXT_MISC_IMR_EXT_AUTO_REC_OFFSET, 1)) != RT_ERR_OK) + return retVal; + } + else + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_IMR_EXT_MISC_ADDR, RTL8373_IMR_EXT_MISC_IMR_EXT_AUTO_REC_OFFSET, 0)) != RT_ERR_OK) + return retVal; + } + } + else if (interrupt == ACL) + { + if(enable == 1) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_IMR_EXT_MISC_ADDR, RTL8373_IMR_EXT_MISC_IMR_EXT_ACL_OFFSET, 1)) != RT_ERR_OK) + return retVal; + } + else + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_IMR_EXT_MISC_ADDR, RTL8373_IMR_EXT_MISC_IMR_EXT_ACL_OFFSET, 0)) != RT_ERR_OK) + return retVal; + } + } + else if (interrupt == INCPU) + { + if(enable == 1) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_IMR_EXT_MISC_ADDR, RTL8373_IMR_EXT_MISC_IMR_EXT_8051_OFFSET, 1)) != RT_ERR_OK) + return retVal; + } + else + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_IMR_EXT_MISC_ADDR, RTL8373_IMR_EXT_MISC_IMR_EXT_8051_OFFSET, 0)) != RT_ERR_OK) + return retVal; + } + } + else if (interrupt == LOOP_DETEC) + { + if(enable == 1) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_IMR_EXT_MISC_ADDR, RTL8373_IMR_EXT_MISC_IMR_EXT_LOOP_DETECTION_OFFSET, 1)) != RT_ERR_OK) + return retVal; + } + else + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_IMR_EXT_MISC_ADDR, RTL8373_IMR_EXT_MISC_IMR_EXT_LOOP_DETECTION_OFFSET, 0)) != RT_ERR_OK) + return retVal; + } + } + else if (interrupt == METER_EXCEED) + { + if(enable == 1) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_IMR_EXT_MISC_ADDR, RTL8373_IMR_EXT_MISC_IMR_EXT_METER_EXCEED_OFFSET, 1)) != RT_ERR_OK) + return retVal; + } + else + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_IMR_EXT_MISC_ADDR, RTL8373_IMR_EXT_MISC_IMR_EXT_METER_EXCEED_OFFSET, 0)) != RT_ERR_OK) + return retVal; + } + } + else if (interrupt == ROUT_PBUF) + { + if(enable == 1) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_IMR_EXT_MISC_ADDR, RTL8373_IMR_EXT_MISC_IMR_EXT_ROUT_PBUF_OFFSET, 1)) != RT_ERR_OK) + return retVal; + } + else + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_IMR_EXT_MISC_ADDR, RTL8373_IMR_EXT_MISC_IMR_EXT_ROUT_PBUF_OFFSET, 0)) != RT_ERR_OK) + return retVal; + } + } + else if (interrupt == PTP1588) + { + if(enable == 1) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_IMR_EXT_MISC_ADDR, RTL8373_IMR_EXT_MISC_IMR_EXT_PTP1588_OFFSET, 1)) != RT_ERR_OK) + return retVal; + } + else + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_IMR_EXT_MISC_ADDR, RTL8373_IMR_EXT_MISC_IMR_EXT_PTP1588_OFFSET, 0)) != RT_ERR_OK) + return retVal; + } + } + } + +#endif + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_miscIMR_get + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ + +rtk_api_ret_t dal_rtl8373_miscIMR_get(rtk_uint32 type, interrupt_misc_t interrupt, rtk_uint32* pEnable) +{ + rtk_api_ret_t retVal; + + + if(type == 0) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_IMR_INT_MISC_ADDR, interrupt, pEnable)) != RT_ERR_OK) + return retVal; + } + else + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_IMR_EXT_MISC_ADDR, interrupt, pEnable)) != RT_ERR_OK) + return retVal; + } + +#if 0 + /*internal interrupt*/ + if(type == 0) + { + if (interrupt == TM_HIGH) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_IMR_INT_MISC_ADDR, RTL8373_IMR_INT_MISC_IMR_INT_TM_HIGH_OFFSET, pEnable)) != RT_ERR_OK) + return retVal; + } + else if (interrupt == TM_LOW) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_IMR_INT_MISC_ADDR, RTL8373_IMR_INT_MISC_IMR_INT_TM_LOW_OFFSET, pEnable)) != RT_ERR_OK) + return retVal; + } + else if (interrupt == SMI_CHECK_REG_0) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_IMR_INT_MISC_ADDR, (1 << 2), pEnable)) != RT_ERR_OK) + return retVal; + } + else if (interrupt == SMI_CHECK_REG_1) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_IMR_INT_MISC_ADDR, (1 << 3), pEnable)) != RT_ERR_OK) + return retVal; + } + else if (interrupt == SMI_CHECK_REG_2) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_IMR_INT_MISC_ADDR, (1 << 4), pEnable)) != RT_ERR_OK) + return retVal; + } + else if (interrupt == SMI_CHECK_REG_3) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_IMR_INT_MISC_ADDR, (1 << 5), pEnable)) != RT_ERR_OK) + return retVal; + } + else if (interrupt == SMI_CHECK_REG_4) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_IMR_INT_MISC_ADDR, (1 << 6), pEnable)) != RT_ERR_OK) + return retVal; + } + else if (interrupt == SDS_RX_SYM_ERR_0) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_IMR_INT_MISC_ADDR, (1 << 7), pEnable)) != RT_ERR_OK) + return retVal; + } + else if (interrupt == SDS_RX_SYM_ERR_1) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_IMR_INT_MISC_ADDR, (1 << 8), pEnable)) != RT_ERR_OK) + return retVal; + } + else if (interrupt == SAMOVE) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_IMR_INT_MISC_ADDR, RTL8373_IMR_INT_MISC_IMR_INT_SAMOVE_OFFSET, pEnable)) != RT_ERR_OK) + return retVal; + } + else if (interrupt == AUTO_REC) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_IMR_INT_MISC_ADDR, RTL8373_IMR_INT_MISC_IMR_INT_AUTO_REC_OFFSET, pEnable)) != RT_ERR_OK) + return retVal; + + } + else if (interrupt == ACL) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_IMR_INT_MISC_ADDR, RTL8373_IMR_INT_MISC_IMR_INT_ACL_OFFSET, pEnable)) != RT_ERR_OK) + return retVal; + + } + else if (interrupt == LOOP_DETEC) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_IMR_INT_MISC_ADDR, RTL8373_IMR_INT_MISC_IMR_INT_LOOP_DETECTION_OFFSET, pEnable)) != RT_ERR_OK) + return retVal; + } + else if (interrupt == METER_EXCEED) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_IMR_INT_MISC_ADDR, RTL8373_IMR_INT_MISC_IMR_INT_METER_EXCEED_OFFSET, pEnable)) != RT_ERR_OK) + return retVal; + } + else if (interrupt == ROUT_PBUF) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_IMR_INT_MISC_ADDR, RTL8373_IMR_INT_MISC_IMR_INT_ROUT_PBUF_OFFSET, pEnable)) != RT_ERR_OK) + return retVal; + + } + else if (interrupt == PTP1588) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_IMR_INT_MISC_ADDR, RTL8373_IMR_INT_MISC_IMR_INT_PTP1588_OFFSET, pEnable)) != RT_ERR_OK) + return retVal; + + } + } + else /*external interrupt*/ + { + if (interrupt == TM_HIGH) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_IMR_EXT_MISC_ADDR, RTL8373_IMR_EXT_MISC_IMR_EXT_TM_HIGH_OFFSET, pEnable)) != RT_ERR_OK) + return retVal; + } + else if (interrupt == TM_LOW) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_IMR_EXT_MISC_ADDR, RTL8373_IMR_EXT_MISC_IMR_EXT_TM_LOW_OFFSET, pEnable)) != RT_ERR_OK) + return retVal; + } + else if (interrupt == SMI_CHECK_REG_0) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_IMR_EXT_MISC_ADDR, (1 << 2), pEnable)) != RT_ERR_OK) + return retVal; + } + else if (interrupt == SMI_CHECK_REG_1) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_IMR_EXT_MISC_ADDR, (1 << 3), pEnable)) != RT_ERR_OK) + return retVal; + } + else if (interrupt == SMI_CHECK_REG_2) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_IMR_EXT_MISC_ADDR, (1 << 4), pEnable)) != RT_ERR_OK) + return retVal; + } + else if (interrupt == SMI_CHECK_REG_3) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_IMR_EXT_MISC_ADDR, (1 << 5), pEnable)) != RT_ERR_OK) + return retVal; + } + else if (interrupt == SMI_CHECK_REG_4) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_IMR_EXT_MISC_ADDR, (1 << 6), pEnable)) != RT_ERR_OK) + return retVal; + } + else if (interrupt == SDS_RX_SYM_ERR_0) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_IMR_EXT_MISC_ADDR, (1 << 7), pEnable)) != RT_ERR_OK) + return retVal; + } + else if (interrupt == SDS_RX_SYM_ERR_1) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_IMR_EXT_MISC_ADDR, (1 << 8), pEnable)) != RT_ERR_OK) + return retVal; + } + else if (interrupt == SAMOVE) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_IMR_EXT_MISC_ADDR, RTL8373_IMR_EXT_MISC_IMR_EXT_SAMOVE_OFFSET, pEnable)) != RT_ERR_OK) + return retVal; + } + else if (interrupt == AUTO_REC) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_IMR_EXT_MISC_ADDR, RTL8373_IMR_EXT_MISC_IMR_EXT_AUTO_REC_OFFSET, pEnable)) != RT_ERR_OK) + return retVal; + + } + else if (interrupt == ACL) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_IMR_EXT_MISC_ADDR, RTL8373_IMR_EXT_MISC_IMR_EXT_ACL_OFFSET, pEnable)) != RT_ERR_OK) + return retVal; + + } + else if (interrupt == INCPU) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_IMR_EXT_MISC_ADDR, RTL8373_IMR_EXT_MISC_IMR_EXT_ACL_OFFSET, pEnable)) != RT_ERR_OK) + return retVal; + + } + else if (interrupt == LOOP_DETEC) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_IMR_EXT_MISC_ADDR, RTL8373_IMR_EXT_MISC_IMR_EXT_LOOP_DETECTION_OFFSET, pEnable)) != RT_ERR_OK) + return retVal; + } + else if (interrupt == METER_EXCEED) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_IMR_EXT_MISC_ADDR, RTL8373_IMR_EXT_MISC_IMR_EXT_METER_EXCEED_OFFSET, pEnable)) != RT_ERR_OK) + return retVal; + } + else if (interrupt == ROUT_PBUF) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_IMR_EXT_MISC_ADDR, RTL8373_IMR_EXT_MISC_IMR_EXT_ROUT_PBUF_OFFSET, pEnable)) != RT_ERR_OK) + return retVal; + + } + else if (interrupt == PTP1588) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_IMR_EXT_MISC_ADDR, RTL8373_IMR_EXT_MISC_IMR_EXT_PTP1588_OFFSET, pEnable)) != RT_ERR_OK) + return retVal; + + } + } + +#endif + return RT_ERR_OK; +} + + + + +/* Function Name: + * dal_rtl8373_portLinkChgISR_get + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * pStatus: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ + +rtk_api_ret_t dal_rtl8373_portLinkChgISR_get(rtk_uint32 type, rtk_uint32 port, rtk_uint32* pStatus) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + + /*internal interrupt*/ + if(type == 0) + { + if ((retVal = rtl8373_getAsicReg(RTL8373_ISR_INT_PORT_LINK_STS_CHG_ADDR, ®Data)) != RT_ERR_OK) + return retVal; + + *pStatus = (regData >> port) & 1; + } + else /*external interrupt*/ + { + if ((retVal = rtl8373_getAsicReg(RTL8373_ISR_EXT_PORT_LINK_STS_CHG_ADDR, ®Data)) != RT_ERR_OK) + return retVal; + + *pStatus = (regData >> port) & 1; + } + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_portLinkChgISR_clear + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ + +rtk_api_ret_t dal_rtl8373_portLinkChgISR_clear(rtk_uint32 type, rtk_uint32 port) +{ + rtk_api_ret_t retVal; + + /*internal interrupt*/ + if(type == 0) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_ISR_INT_PORT_LINK_STS_CHG_ADDR, port,1)) != RT_ERR_OK) + return retVal; + + } + else /*external interrupt*/ + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_ISR_EXT_PORT_LINK_STS_CHG_ADDR, port,1)) != RT_ERR_OK) + return retVal; + } + return RT_ERR_OK; +} + + + +/* Function Name: + * dal_rtl8373_gphyIMR_get + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ + +rtk_api_ret_t dal_rtl8373_gphyISR_get(rtk_uint32 type, rtk_uint32 phy, rtk_uint32* pStatus) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + + /*internal interrupt*/ + if(type == 0) + { + if ((retVal = rtl8373_getAsicReg(RTL8373_ISR_INT_GPHY_ADDR, ®Data)) != RT_ERR_OK) + return retVal; + + *pStatus = (regData >> phy) & 1; + } + else /*external interrupt*/ + { + if ((retVal = rtl8373_getAsicReg(RTL8373_ISR_EXT_GPHY_ADDR, ®Data)) != RT_ERR_OK) + return retVal; + + *pStatus = (regData >> phy) & 1; + } + return RT_ERR_OK; +} + + + +/* Function Name: + * dal_rtl8373_gphyISR_clear + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ + +rtk_api_ret_t dal_rtl8373_gphyISR_clear(rtk_uint32 type, rtk_uint32 phy) +{ + rtk_api_ret_t retVal; + + /*internal interrupt*/ + if(type == 0) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_ISR_INT_GPHY_ADDR, phy, 1)) != RT_ERR_OK) + return retVal; + + } + else /*external interrupt*/ + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_ISR_EXT_GPHY_ADDR, phy, 1)) != RT_ERR_OK) + return retVal; + } + return RT_ERR_OK; +} + + + + +/* Function Name: + * dal_rtl8373_portLrnOverIMR_get + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ + +rtk_api_ret_t dal_rtl8373_portLrnOverISR_get(rtk_uint32 type, rtk_uint32 port, rtk_uint32* pStatus) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + + /*internal interrupt*/ + if(type == 0) + { + if ((retVal = rtl8373_getAsicReg(RTL8373_ISR_INT_LEARNOVER_ADDR, ®Data)) != RT_ERR_OK) + return retVal; + + *pStatus = (regData >> port) & 1; + } + else /*external interrupt*/ + { + if ((retVal = rtl8373_getAsicReg(RTL8373_ISR_EXT_LEARNOVER_ADDR, ®Data)) != RT_ERR_OK) + return retVal; + + *pStatus = (regData >> port) & 1; + } + return RT_ERR_OK; +} + + + + +/* Function Name: + * dal_rtl8373_portLrnOverISR_clear + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ + +rtk_api_ret_t dal_rtl8373_portLrnOverISR_clear(rtk_uint32 type, rtk_uint32 port) +{ + rtk_api_ret_t retVal; + + /*internal interrupt*/ + if(type == 0) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_ISR_INT_LEARNOVER_ADDR, port, 1)) != RT_ERR_OK) + return retVal; + + } + else /*external interrupt*/ + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_ISR_EXT_LEARNOVER_ADDR, port, 1)) != RT_ERR_OK) + return retVal; + } + return RT_ERR_OK; +} + + + +/* Function Name: + * dal_rtl8373_portRLFDIMR_get + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ + +rtk_api_ret_t dal_rtl8373_portRLFDISR_get(rtk_uint32 type, rtk_uint32 port, rtk_uint32* pStatus) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + + /*internal interrupt*/ + if(type == 0) + { + if ((retVal = rtl8373_getAsicReg(RTL8373_ISR_INT_TM_RLFD_ADDR, ®Data)) != RT_ERR_OK) + return retVal; + + *pStatus = (regData >> port) & 1; + } + else /*external interrupt*/ + { + if ((retVal = rtl8373_getAsicReg(RTL8373_ISR_EXT_TM_RLFD_ADDR, ®Data)) != RT_ERR_OK) + return retVal; + + *pStatus = (regData >> port) & 1; + } + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_portRLFDISR_clear + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ + +rtk_api_ret_t dal_rtl8373_portRLFDISR_clear(rtk_uint32 type, rtk_uint32 port) +{ + rtk_api_ret_t retVal; + + /*internal interrupt*/ + if(type == 0) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_ISR_INT_TM_RLFD_ADDR, port, 1)) != RT_ERR_OK) + return retVal; + + } + else /*external interrupt*/ + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_ISR_EXT_TM_RLFD_ADDR, port, 1)) != RT_ERR_OK) + return retVal; + + } + return RT_ERR_OK; +} + + + +/* Function Name: + * dal_rtl8373_portWolIMR_get + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ + +rtk_api_ret_t dal_rtl8373_portWolISR_get(rtk_uint32 type, rtk_uint32 port, rtk_uint32* pStatus) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + + /*internal interrupt*/ + if(type == 0) + { + if ((retVal = rtl8373_getAsicReg(RTL8373_ISR_INT_WOL_ADDR, ®Data)) != RT_ERR_OK) + return retVal; + + *pStatus = (regData >> port) & 1; + } + else /*external interrupt*/ + { + if ((retVal = rtl8373_getAsicReg(RTL8373_ISR_EXT_WOL_ADDR, ®Data)) != RT_ERR_OK) + return retVal; + + *pStatus = (regData >> port) & 1; + } + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_portWolISR_clear + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ + +rtk_api_ret_t dal_rtl8373_portWolISR_clear(rtk_uint32 type, rtk_uint32 port) +{ + rtk_api_ret_t retVal; + + /*internal interrupt*/ + if(type == 0) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_ISR_INT_WOL_ADDR, port, 1)) != RT_ERR_OK) + return retVal; + + } + else /*external interrupt*/ + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_ISR_EXT_WOL_ADDR, port, 1)) != RT_ERR_OK) + return retVal; + + } + return RT_ERR_OK; +} + + + + +/* Function Name: + * dal_rtl8373_portSdsLnkFltIMR_get + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ + +rtk_api_ret_t dal_rtl8373_portSdsLnkFltISR_get(rtk_uint32 type, rtk_uint32 sds, rtk_uint32* pStatus) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + + /*internal interrupt*/ + if(type == 0) + { + if ((retVal = rtl8373_getAsicReg(RTL8373_ISR_INT_SERDES_LINK_FAULT_P_ADDR, ®Data)) != RT_ERR_OK) + return retVal; + + *pStatus = (regData >> sds) & 1; + } + else /*external interrupt*/ + { + if ((retVal = rtl8373_getAsicReg(RTL8373_ISR_EXT_SERDES_LINK_FAULT_P_ADDR, ®Data)) != RT_ERR_OK) + return retVal; + + *pStatus = (regData >> sds) & 1; + } + return RT_ERR_OK; +} + + + +/* Function Name: + * dal_rtl8373_portSdsLnkFltISR_clear + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ + +rtk_api_ret_t dal_rtl8373_portSdsLnkFltISR_clear(rtk_uint32 type, rtk_uint32 sds) +{ + rtk_api_ret_t retVal; + + /*internal interrupt*/ + if(type == 0) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_ISR_INT_SERDES_LINK_FAULT_P_ADDR, sds, 1)) != RT_ERR_OK) + return retVal; + } + else /*external interrupt*/ + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_ISR_EXT_SERDES_LINK_FAULT_P_ADDR, sds, 1)) != RT_ERR_OK) + return retVal; + } + return RT_ERR_OK; +} + + + + + +/* Function Name: + * dal_rtl8373_portSdsUpdPhyIMR_get + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ + +rtk_api_ret_t dal_rtl8373_portSdsUpdPhyISR_get(rtk_uint32 type, rtk_uint32 sds, rtk_uint32* pStatus) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + + /*internal interrupt*/ + if(type == 0) + { + if ((retVal = rtl8373_getAsicReg(RTL8373_ISR_INT_SDS_UPD_PHYSTS0_ADDR, ®Data)) != RT_ERR_OK) + return retVal; + + *pStatus = (regData >> sds) & 1; + } + else /*external interrupt*/ + { + if ((retVal = rtl8373_getAsicReg(RTL8373_ISR_EXT_SDS_UPD_PHYSTS0_ADDR, ®Data)) != RT_ERR_OK) + return retVal; + + *pStatus = (regData >> sds) & 1; + } + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_portSdsUpdPhyISR_clear + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ + +rtk_api_ret_t dal_rtl8373_portSdsUpdPhyISR_clear(rtk_uint32 type, rtk_uint32 sds) +{ + rtk_api_ret_t retVal; + + /*internal interrupt*/ + if(type == 0) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_ISR_EXT_SDS_UPD_PHYSTS0_ADDR, sds, 1)) != RT_ERR_OK) + return retVal; + + } + else /*external interrupt*/ + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_ISR_EXT_SDS_UPD_PHYSTS0_ADDR, sds, 1)) != RT_ERR_OK) + return retVal; + + } + return RT_ERR_OK; +} + + + +/* Function Name: + * dal_rtl8373_gpioIMR_get + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ + +rtk_api_ret_t dal_rtl8373_gpioISR_get(rtk_uint32 type, rtk_uint32 gpio, rtk_uint32* pStatus) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + + /*internal interrupt*/ + if(type == 0) + { + if ((retVal = rtl8373_getAsicReg(RTL8373_ISR_INT_GPIO_ADDR, ®Data)) != RT_ERR_OK) + return retVal; + + *pStatus = (regData >> gpio) & 1; + } + else /*external interrupt*/ + { + if ((retVal = rtl8373_getAsicReg(RTL8373_ISR_EXT_GPIO_ADDR, ®Data)) != RT_ERR_OK) + return retVal; + + *pStatus = (regData >> gpio) & 1; + } + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_gpioISR_clear + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ + +rtk_api_ret_t dal_rtl8373_gpioISR_clear(rtk_uint32 type, rtk_uint32 gpio) +{ + rtk_api_ret_t retVal; + + /*internal interrupt*/ + if(type == 0) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_ISR_INT_GPIO_ADDR, gpio, 1)) != RT_ERR_OK) + return retVal; + + } + else /*external interrupt*/ + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_ISR_EXT_GPIO_ADDR, gpio, 1)) != RT_ERR_OK) + return retVal; + + } + return RT_ERR_OK; +} + + + + +/* Function Name: + * dal_rtl8373_miscIMR_get + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ + +rtk_api_ret_t dal_rtl8373_miscISR_get(rtk_uint32 type, interrupt_misc_t interrupt, rtk_uint32* pStatus) +{ + rtk_api_ret_t retVal; + + if (type == 0) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_ISR_INT_MISC_ADDR, interrupt, pStatus)) != RT_ERR_OK) + return retVal; + } + else + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_ISR_EXT_MISC_ADDR, interrupt, pStatus)) != RT_ERR_OK) + return retVal; + } + + +#if 0 + /*internal interrupt*/ + if(type == 0) + { + if (interrupt == TM_HIGH) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_ISR_INT_MISC_ADDR, RTL8373_ISR_INT_MISC_ISR_EXT_TM_HIGH_OFFSET, pStatus)) != RT_ERR_OK) + return retVal; + } + else if (interrupt == TM_LOW) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_ISR_INT_MISC_ADDR, RTL8373_ISR_INT_MISC_ISR_INT_TM_LOW_OFFSET, pStatus)) != RT_ERR_OK) + return retVal; + } + else if (interrupt == SMI_CHECK_REG_0) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_ISR_INT_MISC_ADDR, (1 << 2), pStatus)) != RT_ERR_OK) + return retVal; + } + else if (interrupt == SMI_CHECK_REG_1) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_ISR_INT_MISC_ADDR, (1 << 3), pStatus)) != RT_ERR_OK) + return retVal; + } + else if (interrupt == SMI_CHECK_REG_2) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_ISR_INT_MISC_ADDR, (1 << 4), pStatus)) != RT_ERR_OK) + return retVal; + } + else if (interrupt == SMI_CHECK_REG_3) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_ISR_INT_MISC_ADDR, (1 << 5), pStatus)) != RT_ERR_OK) + return retVal; + } + else if (interrupt == SMI_CHECK_REG_4) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_ISR_INT_MISC_ADDR, (1 << 6), pStatus)) != RT_ERR_OK) + return retVal; + } + else if (interrupt == SDS_RX_SYM_ERR_0) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_ISR_INT_MISC_ADDR, (1 << 7), pStatus)) != RT_ERR_OK) + return retVal; + } + else if (interrupt == SDS_RX_SYM_ERR_1) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_ISR_INT_MISC_ADDR, (1 << 8), pStatus)) != RT_ERR_OK) + return retVal; + } + else if (interrupt == SAMOVE) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_ISR_INT_MISC_ADDR, RTL8373_ISR_INT_MISC_ISR_INT_SAMOVE_OFFSET, pStatus)) != RT_ERR_OK) + return retVal; + } + else if (interrupt == AUTO_REC) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_ISR_INT_MISC_ADDR, RTL8373_ISR_INT_MISC_ISR_INT_AUTO_REC_OFFSET, pStatus)) != RT_ERR_OK) + return retVal; + + } + else if (interrupt == ACL) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_ISR_INT_MISC_ADDR, RTL8373_ISR_INT_MISC_ISR_INT_ACL_OFFSET, pStatus)) != RT_ERR_OK) + return retVal; + + } + else if (interrupt == LOOP_DETEC) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_ISR_INT_MISC_ADDR, RTL8373_ISR_INT_MISC_ISR_INT_LOOP_DETECTION_OFFSET, pStatus)) != RT_ERR_OK) + return retVal; + } + else if (interrupt == METER_EXCEED) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_ISR_INT_MISC_ADDR, RTL8373_ISR_INT_MISC_ISR_INT_METER_EXCEED_OFFSET, pStatus)) != RT_ERR_OK) + return retVal; + } + else if (interrupt == ROUT_PBUF) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_ISR_INT_MISC_ADDR, RTL8373_ISR_INT_MISC_ISR_INT_ROUT_PBUF_OFFSET, pStatus)) != RT_ERR_OK) + return retVal; + + } + else if (interrupt == PTP1588) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_ISR_INT_MISC_ADDR, RTL8373_ISR_INT_MISC_ISR_INT_PTP1588_OFFSET, pStatus)) != RT_ERR_OK) + return retVal; + + } + } + else /*external interrupt*/ + { + if (interrupt == TM_HIGH) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_ISR_EXT_MISC_ADDR, RTL8373_ISR_EXT_MISC_ISR_EXT_TM_HIGH_OFFSET, pStatus)) != RT_ERR_OK) + return retVal; + } + else if (interrupt == TM_LOW) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_ISR_EXT_MISC_ADDR, RTL8373_ISR_EXT_MISC_ISR_EXT_TM_LOW_OFFSET, pStatus)) != RT_ERR_OK) + return retVal; + } + else if (interrupt == SMI_CHECK_REG_0) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_ISR_EXT_MISC_ADDR, (1 << 2), pStatus)) != RT_ERR_OK) + return retVal; + } + else if (interrupt == SMI_CHECK_REG_1) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_ISR_EXT_MISC_ADDR, (1 << 3), pStatus)) != RT_ERR_OK) + return retVal; + } + else if (interrupt == SMI_CHECK_REG_2) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_ISR_EXT_MISC_ADDR, (1 << 4), pStatus)) != RT_ERR_OK) + return retVal; + } + else if (interrupt == SMI_CHECK_REG_3) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_ISR_EXT_MISC_ADDR, (1 << 5), pStatus)) != RT_ERR_OK) + return retVal; + } + else if (interrupt == SMI_CHECK_REG_4) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_ISR_EXT_MISC_ADDR, (1 << 6), pStatus)) != RT_ERR_OK) + return retVal; + } + else if (interrupt == SDS_RX_SYM_ERR_0) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_ISR_EXT_MISC_ADDR, (1 << 7), pStatus)) != RT_ERR_OK) + return retVal; + } + else if (interrupt == SDS_RX_SYM_ERR_1) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_ISR_EXT_MISC_ADDR, (1 << 8), pStatus)) != RT_ERR_OK) + return retVal; + } + else if (interrupt == SAMOVE) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_ISR_EXT_MISC_ADDR, RTL8373_ISR_EXT_MISC_ISR_EXT_SAMOVE_OFFSET, pStatus)) != RT_ERR_OK) + return retVal; + } + else if (interrupt == AUTO_REC) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_ISR_EXT_MISC_ADDR, RTL8373_ISR_EXT_MISC_ISR_EXT_AUTO_REC_OFFSET, pStatus)) != RT_ERR_OK) + return retVal; + + } + else if (interrupt == ACL) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_ISR_EXT_MISC_ADDR, RTL8373_ISR_EXT_MISC_ISR_EXT_ACL_OFFSET, pStatus)) != RT_ERR_OK) + return retVal; + + } + else if (interrupt == INCPU) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_ISR_EXT_MISC_ADDR, RTL8373_ISR_EXT_MISC_ISR_EXT_ACL_OFFSET, pStatus)) != RT_ERR_OK) + return retVal; + + } + else if (interrupt == LOOP_DETEC) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_ISR_EXT_MISC_ADDR, RTL8373_ISR_EXT_MISC_ISR_EXT_LOOP_DETECTION_OFFSET, pStatus)) != RT_ERR_OK) + return retVal; + } + else if (interrupt == METER_EXCEED) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_ISR_EXT_MISC_ADDR, RTL8373_ISR_EXT_MISC_ISR_EXT_METER_EXCEED_OFFSET, pStatus)) != RT_ERR_OK) + return retVal; + } + else if (interrupt == ROUT_PBUF) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_ISR_EXT_MISC_ADDR, RTL8373_ISR_EXT_MISC_ISR_EXT_ROUT_PBUF_OFFSET, pStatus)) != RT_ERR_OK) + return retVal; + + } + else if (interrupt == PTP1588) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_ISR_EXT_MISC_ADDR, RTL8373_ISR_EXT_MISC_ISR_EXT_PTP1588_OFFSET, pStatus)) != RT_ERR_OK) + return retVal; + + } + } + +#endif + return RT_ERR_OK; +} + + + + +/* Function Name: + * dal_rtl8373_miscISR_clear + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ + +rtk_api_ret_t dal_rtl8373_miscISR_clear(rtk_uint32 type, interrupt_misc_t interrupt) +{ + rtk_api_ret_t retVal; + + if (type == 0) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_ISR_INT_MISC_ADDR, interrupt, 1)) != RT_ERR_OK) + return retVal; + } + else + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_ISR_EXT_MISC_ADDR, interrupt, 1)) != RT_ERR_OK) + return retVal; + } + + + return RT_ERR_OK; +} + + + + + +/* Function Name: + * dal_rtl8373_glbISR_get + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ + +rtk_api_ret_t dal_rtl8373_glbISR_get(rtk_uint32 type, interrupt_glb_t interrupt, rtk_uint32* pStatus) +{ + rtk_api_ret_t retVal; + + /*internal interrupt*/ + if(type == 0) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_ISR_INT_GLB_ADDR, interrupt, pStatus)) != RT_ERR_OK) + return retVal; + + } + else /*external interrupt*/ + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_ISR_EXT_GLB_ADDR, interrupt, pStatus)) != RT_ERR_OK) + return retVal; + } + return RT_ERR_OK; +} + + + + + +/* Function Name: + * dal_rtl8373_IE_set + * Description: + * Set switch interrupt enable + * Input: + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ + +rtk_api_ret_t dal_rtl8373_IE_set(rtk_uint32 enable) +{ + rtk_api_ret_t retVal; + + if ((retVal = rtl8373_setAsicRegBit(RTL8373_ISR_SW_INT_MODE_ADDR, RTL8373_ISR_SW_INT_MODE_SWITCH_IE_OFFSET, enable)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_IE_get + * Description: + * Set switch interrupt enable + * Input: + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ + +rtk_api_ret_t dal_rtl8373_IE_get(rtk_uint32* pEnable) +{ + rtk_api_ret_t retVal; + + if ((retVal = rtl8373_getAsicRegBit(RTL8373_ISR_SW_INT_MODE_ADDR, RTL8373_ISR_SW_INT_MODE_SWITCH_IE_OFFSET, pEnable)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + + +/* Function Name: + * dal_rtl8373_portIntIMR_set + * Description: + * Set per port interrupt IMR + * Input: + * port: port id/ gphy id/ serdes id + * inttype: 0 internal interrupt; 1 external interupt + * int: per port interrupt + * enable: 0 disable IMR; 1 enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ +rtk_api_ret_t dal_rtl8373_portIntIMR_set(rtk_port_t port, rtk_int_cpu_t inttype, rtk_int_type_t intnum, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + /*interrnal interrupt*/ + if(intnum == INT_TYPE_LINK_CHANGE) + { + if ((retVal = dal_rtl8373_portLinkChgIMR_set(inttype, port, enable)) != RT_ERR_OK) + return retVal; + } + else if(intnum == INT_TYPE_GPHY) + { + if ((retVal = dal_rtl8373_gphyIMR_set(inttype, port, enable)) != RT_ERR_OK) + return retVal; + } + else if(intnum == INT_TYPE_LEARN_OVER) + { + if ((retVal = dal_rtl8373_portLrnOverIMR_set(inttype, port, enable)) != RT_ERR_OK) + return retVal; + } + else if(intnum == INT_TYPE_RLFD) + { + if ((retVal = dal_rtl8373_portRLFDIMR_set(inttype, port, enable)) != RT_ERR_OK) + return retVal; + } + else if(intnum == INT_TYPE_WOL) + { + if ((retVal = dal_rtl8373_portWolIMR_set(inttype, port, enable)) != RT_ERR_OK) + return retVal; + } + else if(intnum == INT_TYPE_SDS_LINK_FAULT) + { + if ((retVal = dal_rtl8373_portSdsLnkFltIMR_set(inttype, port, enable)) != RT_ERR_OK) + return retVal; + } + else if(intnum == INT_TYPE_SDS_UPDATE_PHY) + { + if ((retVal = dal_rtl8373_portSdsUpdPhyIMR_set(inttype, port, enable)) != RT_ERR_OK) + return retVal; + } + + + return RT_ERR_OK; +} + + + + +/* Function Name: + * dal_rtl8373_portIntIMR_get + * Description: + * Get per port interrupt IMR + * Input: + * port: port id/ gphy id/ serdes id + * inttype: 0 internal interrupt; 1 external interupt + * int: per port interrupt + * enable: 0 disable IMR; 1 enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ + +rtk_api_ret_t dal_rtl8373_portIntIMR_get(rtk_port_t port, rtk_int_cpu_t inttype, rtk_int_type_t intnum, rtk_enable_t* pEnable) +{ + rtk_api_ret_t retVal; + + /*interrnal interrupt*/ + if(intnum == INT_TYPE_LINK_CHANGE) + { + if ((retVal = dal_rtl8373_portLinkChgIMR_get(inttype, port, pEnable)) != RT_ERR_OK) + return retVal; + } + else if(intnum == INT_TYPE_GPHY) + { + if ((retVal = dal_rtl8373_gphyIMR_get(inttype, port, pEnable)) != RT_ERR_OK) + return retVal; + } + else if(intnum == INT_TYPE_LEARN_OVER) + { + if ((retVal = dal_rtl8373_portLrnOverIMR_get(inttype, port, pEnable)) != RT_ERR_OK) + return retVal; + } + else if(intnum == INT_TYPE_RLFD) + { + if ((retVal = dal_rtl8373_portRLFDIMR_get(inttype, port, pEnable)) != RT_ERR_OK) + return retVal; + } + else if(intnum == INT_TYPE_WOL) + { + if ((retVal = dal_rtl8373_portWolIMR_get(inttype, port, pEnable)) != RT_ERR_OK) + return retVal; + } + else if(intnum == INT_TYPE_SDS_LINK_FAULT) + { + if ((retVal = dal_rtl8373_portSdsLnkFltIMR_get(inttype, port, pEnable)) != RT_ERR_OK) + return retVal; + } + else if(intnum == INT_TYPE_SDS_UPDATE_PHY) + { + if ((retVal = dal_rtl8373_portSdsUpdPhyIMR_get(inttype, port, pEnable)) != RT_ERR_OK) + return retVal; + } + + + return RT_ERR_OK; +} + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_interrupt.h b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_interrupt.h new file mode 100755 index 00000000..8057da4f --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_interrupt.h @@ -0,0 +1,929 @@ +#ifndef __DAL_RTL8373_INTERRUPT_H__ +#define __DAL_RTL8373_INTERRUPT_H__ + +#include + + + + + + + + +/* Function Name: + * dal_rtl8373_intMode_set + * Description: + * Set interrupt mode + * Input: + * mode : 0 high; 1: low; 2 positive pulse; 3 negative pulse + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ +extern rtk_api_ret_t dal_rtl8373_intMode_set(rtk_int_polarity_t mode); + + + +/* Function Name: + * dal_rtl8373_intMode_get + * Description: + * Set interrupt mode + * Input: + * pMode : 0 high; 1: low; 2 positive pulse; 3 negative pulse + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ +extern rtk_api_ret_t dal_rtl8373_intMode_get(rtk_int_polarity_t* pMode); + + + +/* Function Name: + * dal_rtl8373_portLinkChgIMR_set + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ +extern rtk_api_ret_t dal_rtl8373_portLinkChgIMR_set(rtk_uint32 type, rtk_uint32 port, rtk_uint32 enable); + + +/* Function Name: + * dal_rtl8373_portLinkChgIMR_get + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ + +extern rtk_api_ret_t dal_rtl8373_portLinkChgIMR_get(rtk_uint32 type, rtk_uint32 port, rtk_uint32* pEnable); + + +/* Function Name: + * dal_rtl8373_gphyIMR_set + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * gphy: gphy id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ +extern rtk_api_ret_t dal_rtl8373_gphyIMR_set(rtk_uint32 type, rtk_uint32 phy, rtk_uint32 enable); + + +/* Function Name: + * dal_rtl8373_gphyIMR_get + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ + +extern rtk_api_ret_t dal_rtl8373_gphyIMR_get(rtk_uint32 type, rtk_uint32 phy, rtk_uint32* pEnable); + + + +/* Function Name: + * dal_rtl8373_portLrnOverIMR_set + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ +extern rtk_api_ret_t dal_rtl8373_portLrnOverIMR_set(rtk_uint32 type, rtk_uint32 port, rtk_uint32 enable); + + +/* Function Name: + * dal_rtl8373_portLrnOverIMR_get + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ + +extern rtk_api_ret_t dal_rtl8373_portLrnOverIMR_get(rtk_uint32 type, rtk_uint32 port, rtk_uint32* pEnable); + + +/* Function Name: + * dal_rtl8373_portRLFDIMR_set + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ +extern rtk_api_ret_t dal_rtl8373_portRLFDIMR_set(rtk_uint32 type, rtk_uint32 port, rtk_uint32 enable); + + +/* Function Name: + * dal_rtl8373_portRLFDIMR_get + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ + +extern rtk_api_ret_t dal_rtl8373_portRLFDIMR_get(rtk_uint32 type, rtk_uint32 port, rtk_uint32* pEnable); + + +/* Function Name: + * dal_rtl8373_portWolIMR_set + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ +extern rtk_api_ret_t dal_rtl8373_portWolIMR_set(rtk_uint32 type, rtk_uint32 port, rtk_uint32 enable); + + +/* Function Name: + * dal_rtl8373_portWolIMR_get + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ + +extern rtk_api_ret_t dal_rtl8373_portWolIMR_get(rtk_uint32 type, rtk_uint32 port, rtk_uint32* pEnable); + + +/* Function Name: + * dal_rtl8373_portSdsLnkFltIMR_set + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ +extern rtk_api_ret_t dal_rtl8373_portSdsLnkFltIMR_set(rtk_uint32 type, rtk_uint32 sds, rtk_uint32 enable); + + +/* Function Name: + * dal_rtl8373_portSdsLnkFltIMR_get + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ + +extern rtk_api_ret_t dal_rtl8373_portSdsLnkFltIMR_get(rtk_uint32 type, rtk_uint32 sds, rtk_uint32* pEnable); + + +/* Function Name: + * dal_rtl8373_portSdsUpdPhyIMR_set + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ +extern rtk_api_ret_t dal_rtl8373_portSdsUpdPhyIMR_set(rtk_uint32 type, rtk_uint32 sds, rtk_uint32 enable); + + +/* Function Name: + * dal_rtl8373_portSdsUpdPhyIMR_get + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ + +extern rtk_api_ret_t dal_rtl8373_portSdsUpdPhyIMR_get(rtk_uint32 type, rtk_uint32 sds, rtk_uint32* pEnable); + + +/* Function Name: + * dal_rtl8373_gpioIMR_set + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ +extern rtk_api_ret_t dal_rtl8373_gpioIMR_set(rtk_uint32 type, rtk_uint32 gpio, rtk_uint32 enable); + + +/* Function Name: + * dal_rtl8373_gpioIMR_get + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ + +extern rtk_api_ret_t dal_rtl8373_gpioIMR_get(rtk_uint32 type, rtk_uint32 gpio, rtk_uint32* pEnable); + + +/* Function Name: + * dal_rtl8373_miscIMR_set + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ +extern rtk_api_ret_t dal_rtl8373_miscIMR_set(rtk_uint32 type, interrupt_misc_t interrupt, rtk_uint32 enable); + + +/* Function Name: + * dal_rtl8373_miscIMR_get + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ + +extern rtk_api_ret_t dal_rtl8373_miscIMR_get(rtk_uint32 type, interrupt_misc_t interrupt, rtk_uint32* pEnable); + + + + +/* Function Name: + * dal_rtl8373_portLinkChgISR_get + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * pStatus: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ + +extern rtk_api_ret_t dal_rtl8373_portLinkChgISR_get(rtk_uint32 type, rtk_uint32 port, rtk_uint32* pStatus); + + + +/* Function Name: + * dal_rtl8373_gphyIMR_get + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ + +extern rtk_api_ret_t dal_rtl8373_gphyISR_get(rtk_uint32 type, rtk_uint32 phy, rtk_uint32* pStatus); + + + + +/* Function Name: + * dal_rtl8373_portLrnOverIMR_get + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ + +extern rtk_api_ret_t dal_rtl8373_portLrnOverISR_get(rtk_uint32 type, rtk_uint32 port, rtk_uint32* pStatus); + + + +/* Function Name: + * dal_rtl8373_portRLFDIMR_get + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ + +extern rtk_api_ret_t dal_rtl8373_portRLFDISR_get(rtk_uint32 type, rtk_uint32 port, rtk_uint32* pStatus); + + + +/* Function Name: + * dal_rtl8373_portWolIMR_get + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ + +extern rtk_api_ret_t dal_rtl8373_portWolISR_get(rtk_uint32 type, rtk_uint32 port, rtk_uint32* pStatus); + + + +/* Function Name: + * dal_rtl8373_portSdsLnkFltIMR_get + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ + +extern rtk_api_ret_t dal_rtl8373_portSdsLnkFltISR_get(rtk_uint32 type, rtk_uint32 sds, rtk_uint32* pStatus); + + + +/* Function Name: + * dal_rtl8373_portSdsUpdPhyIMR_get + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ + +extern rtk_api_ret_t dal_rtl8373_portSdsUpdPhyISR_get(rtk_uint32 type, rtk_uint32 sds, rtk_uint32* pStatus); + + + +/* Function Name: + * dal_rtl8373_gpioIMR_get + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ + +extern rtk_api_ret_t dal_rtl8373_gpioISR_get(rtk_uint32 type, rtk_uint32 gpio, rtk_uint32* pStatus); + + + +/* Function Name: + * dal_rtl8373_miscIMR_get + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ + +extern rtk_api_ret_t dal_rtl8373_miscISR_get(rtk_uint32 type, interrupt_misc_t interrupt, rtk_uint32* pStatus); + + + +/* Function Name: + * dal_rtl8373_glbISR_get + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ + +extern rtk_api_ret_t dal_rtl8373_glbISR_get(rtk_uint32 type, interrupt_glb_t interrupt, rtk_uint32* pStatus); + + + +/* Function Name: + * dal_rtl8373_IE_set + * Description: + * Set switch interrupt enable + * Input: + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ + +extern rtk_api_ret_t dal_rtl8373_IE_set(rtk_uint32 enable); + + +/* Function Name: + * dal_rtl8373_IE_get + * Description: + * Set switch interrupt enable + * Input: + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ + +extern rtk_api_ret_t dal_rtl8373_IE_get(rtk_uint32* pEnable); + + + + + /* Function Name: + * dal_rtl8373_portLinkChgISR_clear + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * pStatus: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ + + extern rtk_api_ret_t dal_rtl8373_portLinkChgISR_clear(rtk_uint32 type, rtk_uint32 port); + + + + /* Function Name: + * dal_rtl8373_gphyISR_clear + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ + + extern rtk_api_ret_t dal_rtl8373_gphyISR_clear(rtk_uint32 type, rtk_uint32 phy); + + + + + /* Function Name: + * dal_rtl8373_portLrnOverISR_clear + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ + +extern rtk_api_ret_t dal_rtl8373_portLrnOverISR_clear(rtk_uint32 type, rtk_uint32 port); + + + +/* Function Name: + * dal_rtl8373_portRLFDISR_clear + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ + +extern rtk_api_ret_t dal_rtl8373_portRLFDISR_clear(rtk_uint32 type, rtk_uint32 port); + + + +/* Function Name: + * dal_rtl8373_portRLFDISR_clear + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ + +extern rtk_api_ret_t dal_rtl8373_portWolISR_clear(rtk_uint32 type, rtk_uint32 port); + + + +/* Function Name: + * dal_rtl8373_portSdsLnkFltISR_clear + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ + +extern rtk_api_ret_t dal_rtl8373_portSdsLnkFltISR_clear(rtk_uint32 type, rtk_uint32 sds); + + + +/* Function Name: + * dal_rtl8373_portSdsUpdPhyISR_clear + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ + +extern rtk_api_ret_t dal_rtl8373_portSdsUpdPhyISR_clear(rtk_uint32 type, rtk_uint32 sds); + + + +/* Function Name: + * dal_rtl8373_gpioISR_clear + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ + +extern rtk_api_ret_t dal_rtl8373_gpioISR_clear(rtk_uint32 type, rtk_uint32 gpio); + + + +/* Function Name: + * dal_rtl8373_miscISR_clear + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ + +extern rtk_api_ret_t dal_rtl8373_miscISR_clear(rtk_uint32 type, interrupt_misc_t interrupt); + +/* Function Name: + * dal_rtl8373_portIntIMR_set + * Description: + * Set per port interrupt IMR + * Input: + * port: port id/ gphy id/ serdes id + * inttype: 0 internal interrupt; 1 external interupt + * int: per port interrupt + * enable: 0 disable IMR; 1 enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ +extern rtk_api_ret_t dal_rtl8373_portIntIMR_set(rtk_port_t port, rtk_int_cpu_t inttype, rtk_int_type_t intnum, rtk_enable_t enable); + + + + +/* Function Name: + * dal_rtl8373_portIntIMR_get + * Description: + * Get per port interrupt IMR + * Input: + * port: port id/ gphy id/ serdes id + * inttype: 0 internal interrupt; 1 external interupt + * int: per port interrupt + * enable: 0 disable IMR; 1 enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ +extern rtk_api_ret_t dal_rtl8373_portIntIMR_get(rtk_port_t port, rtk_int_cpu_t inttype, rtk_int_type_t intnum, rtk_enable_t* pEnable); + + + + +#endif + diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_isolation.c b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_isolation.c new file mode 100755 index 00000000..77090228 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_isolation.c @@ -0,0 +1,93 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8373 + * Feature : Here is a list of all functions and variables in ISOLATION module. + * + */ + +#include +#include +#include +#include + +#include + +/* Function Name: + * dal_rtl8373_port_isolation_set + * Description: + * Set permitted port isolation portmask + * Input: + * port - Physical port number (0~9) + * permitPortmask - port mask + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * RT_ERR_PORT_MASK - Invalid portmask + * Note: + * None + */ +ret_t dal_rtl8373_port_isolation_set(rtk_port_t port, rtk_uint32 permitPortmask) +{ + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if( permitPortmask > RTL8373_PORTMASK) + return RT_ERR_PORT_MASK; + + return rtl8373_setAsicReg(RTL8373_PORT_ISO_PORT_PMSK_ADDR(port), permitPortmask); +} + +/* Function Name: + * dal_rtl8373_port_isolation_get + * Description: + * Get permitted port isolation portmask + * Input: + * port - Physical port number (0~9) + * pPermitPortmask - port mask + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t dal_rtl8373_port_isolation_get(rtk_port_t port, rtk_uint32 *pPermitPortmask) +{ + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if(NULL == pPermitPortmask) + return RT_ERR_NULL_POINTER; + + return rtl8373_getAsicReg(RTL8373_PORT_ISO_PORT_PMSK_ADDR(port), pPermitPortmask); +} + + + + + + + diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_isolation.h b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_isolation.h new file mode 100755 index 00000000..226dcfea --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_isolation.h @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8373 switch high-level API + * + * Feature : The file includes ISOLATION module high-layer API defination + * + */ + + +/* Function Name: + * dal_rtl8373_port_isolation_set + * Description: + * Set permitted port isolation portmask + * Input: + * port - Physical port number (0~9) + * permitPortmask - port mask + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * RT_ERR_PORT_MASK - Invalid portmask + * Note: + * None + */ +extern ret_t dal_rtl8373_port_isolation_set(rtk_port_t port, rtk_uint32 permitPortmask); + +/* Function Name: + * dal_rtl8373_port_isolation_get + * Description: + * Get permitted port isolation portmask + * Input: + * port - Physical port number (0~9) + * pPermitPortmask - port mask + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +extern ret_t dal_rtl8373_port_isolation_get(rtk_port_t port, rtk_uint32 *pPermitPortmask); + + diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_led.c b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_led.c new file mode 100755 index 00000000..f66fec88 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_led.c @@ -0,0 +1,361 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8373 + * Feature : Here is a list of all functions and variables in LED module. + * + */ + +#include +#include +#include +#include +#include +#include + +/* Function Name: + * dal_rtl8373_led_config_set + * Description: + * Set Led congiuration + * Input: + * setid - 4 groups led setting 0 ~ 3 + * ledid - 4 leds, 0 ~ 3 + * pConfig . + * led_2p5g; + * led_two_pair_1g; + * led_1g; + * led_500m; + * led_100m; + * led_10m; + * led_link; + * led_link_flash; + * led_act; + * led_rx; + * led_tx; + * led_col; + * led_duplex; + * led_training; + * led_master; + * led_10g; + * led_two_pair_5g; + * led_5g; + * led_two_pair_2p5g; + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_MASK - Error portmask + * Note: + * The API can be used to enable LED per port per group. + */ +rtk_api_ret_t dal_rtl8373_led_config_set(rtk_led_set_t setid, rtk_uint32 ledid, rtk_led_config_t *pConfig) +{ + rtk_api_ret_t retVal; + rtk_uint32 sel0, sel1; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pConfig) + return RT_ERR_NULL_POINTER; + sel0 = 0; + sel1 = 0; + if(pConfig->led_2p5g) + sel0|= 1; + if(pConfig->led_two_pair_1g) + sel0|=(1<<1); + if(pConfig->led_1g) + sel0 |= (1<<2); + if(pConfig->led_500m) + sel0 |= (1<<3); + if(pConfig->led_100m) + sel0 |= (1<<4); + if(pConfig->led_10m) + sel0 |= (1<<5); + if(pConfig->led_link) + sel0 |= (1<<6); + if(pConfig->led_link_flash) + sel0 |= (1<<7); + if(pConfig->led_act) + sel0 |= (1<<8); + if(pConfig->led_rx) + sel0 |= (1<<9); + if(pConfig->led_tx) + sel0 |= (1<<10); + if(pConfig->led_col) + sel0 |= (1<<11); + if(pConfig->led_duplex) + sel0 |= (1<<12); + if(pConfig->led_training) + sel0 |= (1<<13); + if(pConfig->led_master) + sel0 |= (1<<14); + if(pConfig->led_10g) + sel1 |= (1<<0); + if(pConfig->led_two_pair_5g) + sel1 |= (1<<1); + if(pConfig->led_5g) + sel1 |= (1<<2); + if(pConfig->led_two_pair_2p5g) + sel1 |= (1<<3); + + if(setid == LED_SET_0) + { + if(ledid == 0) + { + if((retVal = rtl8373_setAsicRegBits(RTL8373_LED1_0_SET0_CTRL0_ADDR, RTL8373_LED1_0_SET0_CTRL0_SET0_LED0_SEL0_MASK, sel0))!= RT_ERR_OK) + return retVal; + if((retVal = rtl8373_setAsicRegBits(RTL8373_LED3_0_SET1_0_CTRL1_ADDR, RTL8373_LED3_0_SET1_0_CTRL1_SET0_LED0_SEL1_MASK, sel1))!= RT_ERR_OK) + return retVal; + } + else if(ledid == 1) + { + if((retVal = rtl8373_setAsicRegBits(RTL8373_LED1_0_SET0_CTRL0_ADDR, RTL8373_LED1_0_SET0_CTRL0_SET0_LED1_SEL0_MASK, sel0))!= RT_ERR_OK) + return retVal; + if((retVal = rtl8373_setAsicRegBits(RTL8373_LED3_0_SET1_0_CTRL1_ADDR, RTL8373_LED3_0_SET1_0_CTRL1_SET0_LED1_SEL1_MASK, sel1))!= RT_ERR_OK) + return retVal; + + } + else if(ledid == 2) + { + if((retVal = rtl8373_setAsicRegBits(RTL8373_LED3_2_SET0_CTRL0_ADDR, RTL8373_LED3_2_SET0_CTRL0_SET0_LED2_SEL0_MASK, sel0))!= RT_ERR_OK) + return retVal; + if((retVal = rtl8373_setAsicRegBits(RTL8373_LED3_0_SET1_0_CTRL1_ADDR, RTL8373_LED3_0_SET1_0_CTRL1_SET0_LED2_SEL1_MASK, sel1))!= RT_ERR_OK) + return retVal; + + } + else if(ledid == 3) + { + if((retVal = rtl8373_setAsicRegBits(RTL8373_LED3_2_SET0_CTRL0_ADDR, RTL8373_LED3_2_SET0_CTRL0_SET0_LED3_SEL0_MASK, sel0))!= RT_ERR_OK) + return retVal; + if((retVal = rtl8373_setAsicRegBits(RTL8373_LED3_0_SET1_0_CTRL1_ADDR, RTL8373_LED3_0_SET1_0_CTRL1_SET0_LED3_SEL1_MASK, sel1))!= RT_ERR_OK) + return retVal; + + } + else + return RT_ERR_INPUT; + } + else if(setid == LED_SET_1) + { + if(ledid == 0) + { + if((retVal = rtl8373_setAsicRegBits(RTL8373_LED1_0_SET1_CTRL0_ADDR, RTL8373_LED1_0_SET1_CTRL0_SET1_LED0_SEL0_MASK, sel0))!= RT_ERR_OK) + return retVal; + if((retVal = rtl8373_setAsicRegBits(RTL8373_LED3_0_SET1_0_CTRL1_ADDR, RTL8373_LED3_0_SET1_0_CTRL1_SET1_LED0_SEL1_MASK, sel1))!= RT_ERR_OK) + return retVal; + } + else if(ledid == 1) + { + if((retVal = rtl8373_setAsicRegBits(RTL8373_LED1_0_SET1_CTRL0_ADDR, RTL8373_LED1_0_SET1_CTRL0_SET1_LED1_SEL0_MASK, sel0))!= RT_ERR_OK) + return retVal; + if((retVal = rtl8373_setAsicRegBits(RTL8373_LED3_0_SET1_0_CTRL1_ADDR, RTL8373_LED3_0_SET1_0_CTRL1_SET1_LED1_SEL1_MASK, sel1))!= RT_ERR_OK) + return retVal; + } + else if(ledid == 2) + { + if((retVal = rtl8373_setAsicRegBits(RTL8373_LED3_2_SET1_CTRL0_ADDR, RTL8373_LED3_2_SET1_CTRL0_SET1_LED2_SEL0_MASK, sel0))!= RT_ERR_OK) + return retVal; + if((retVal = rtl8373_setAsicRegBits(RTL8373_LED3_0_SET1_0_CTRL1_ADDR, RTL8373_LED3_0_SET1_0_CTRL1_SET1_LED2_SEL1_MASK, sel1))!= RT_ERR_OK) + return retVal; + } + else if(ledid == 3) + { + if((retVal = rtl8373_setAsicRegBits(RTL8373_LED3_2_SET1_CTRL0_ADDR, RTL8373_LED3_2_SET1_CTRL0_SET1_LED3_SEL0_MASK, sel0))!= RT_ERR_OK) + return retVal; + if((retVal = rtl8373_setAsicRegBits(RTL8373_LED3_0_SET1_0_CTRL1_ADDR, RTL8373_LED3_0_SET1_0_CTRL1_SET1_LED3_SEL1_MASK, sel1))!= RT_ERR_OK) + return retVal; + } + else + return RT_ERR_INPUT; + } + else if(setid == LED_SET_2) + { + if(ledid == 0) + { + if((retVal = rtl8373_setAsicRegBits(RTL8373_LED1_0_SET2_CTRL0_ADDR, RTL8373_LED1_0_SET2_CTRL0_SET2_LED0_SEL0_MASK, sel0))!= RT_ERR_OK) + return retVal; + if((retVal = rtl8373_setAsicRegBits(RTL8373_LED3_0_SET3_2_CTRL1_ADDR, RTL8373_LED3_0_SET3_2_CTRL1_SET2_LED0_SEL1_MASK, sel1))!= RT_ERR_OK) + return retVal; + } + else if(ledid == 1) + { + if((retVal = rtl8373_setAsicRegBits(RTL8373_LED1_0_SET2_CTRL0_ADDR, RTL8373_LED1_0_SET2_CTRL0_SET2_LED1_SEL0_MASK, sel0))!= RT_ERR_OK) + return retVal; + if((retVal = rtl8373_setAsicRegBits(RTL8373_LED3_0_SET3_2_CTRL1_ADDR, RTL8373_LED3_0_SET3_2_CTRL1_SET2_LED1_SEL1_MASK, sel1))!= RT_ERR_OK) + return retVal; + } + else if(ledid == 2) + { + if((retVal = rtl8373_setAsicRegBits(RTL8373_LED3_2_SET2_CTRL0_ADDR, RTL8373_LED3_2_SET2_CTRL0_SET2_LED2_SEL0_MASK, sel0))!= RT_ERR_OK) + return retVal; + if((retVal = rtl8373_setAsicRegBits(RTL8373_LED3_0_SET3_2_CTRL1_ADDR, RTL8373_LED3_0_SET3_2_CTRL1_SET2_LED2_SEL1_MASK, sel1))!= RT_ERR_OK) + return retVal; + } + else if(ledid == 3) + { + if((retVal = rtl8373_setAsicRegBits(RTL8373_LED3_2_SET2_CTRL0_ADDR, RTL8373_LED3_2_SET2_CTRL0_SET2_LED3_SEL0_MASK, sel0))!= RT_ERR_OK) + return retVal; + if((retVal = rtl8373_setAsicRegBits(RTL8373_LED3_0_SET3_2_CTRL1_ADDR, RTL8373_LED3_0_SET3_2_CTRL1_SET2_LED3_SEL1_MASK, sel1))!= RT_ERR_OK) + return retVal; + } + else + return RT_ERR_INPUT; + } + else if(setid == LED_SET_3) + { + if(ledid == 0) + { + if((retVal = rtl8373_setAsicRegBits(RTL8373_LED1_0_SET3_CTRL0_ADDR, RTL8373_LED1_0_SET3_CTRL0_SET3_LED0_SEL0_MASK, sel0))!= RT_ERR_OK) + return retVal; + if((retVal = rtl8373_setAsicRegBits(RTL8373_LED3_0_SET3_2_CTRL1_ADDR, RTL8373_LED3_0_SET3_2_CTRL1_SET3_LED0_SEL1_MASK, sel1))!= RT_ERR_OK) + return retVal; + } + else if(ledid == 1) + { + if((retVal = rtl8373_setAsicRegBits(RTL8373_LED1_0_SET3_CTRL0_ADDR, RTL8373_LED1_0_SET3_CTRL0_SET3_LED1_SEL0_MASK, sel0))!= RT_ERR_OK) + return retVal; + if((retVal = rtl8373_setAsicRegBits(RTL8373_LED3_0_SET3_2_CTRL1_ADDR, RTL8373_LED3_0_SET3_2_CTRL1_SET3_LED1_SEL1_MASK, sel1))!= RT_ERR_OK) + return retVal; + } + else if(ledid == 2) + { + if((retVal = rtl8373_setAsicRegBits(RTL8373_LED3_2_SET3_CTRL0_ADDR, RTL8373_LED3_2_SET3_CTRL0_SET3_LED2_SEL0_MASK, sel0))!= RT_ERR_OK) + return retVal; + if((retVal = rtl8373_setAsicRegBits(RTL8373_LED3_0_SET3_2_CTRL1_ADDR, RTL8373_LED3_0_SET3_2_CTRL1_SET3_LED2_SEL1_MASK, sel1))!= RT_ERR_OK) + return retVal; + } + else if(ledid == 3) + { + if((retVal = rtl8373_setAsicRegBits(RTL8373_LED3_2_SET3_CTRL0_ADDR, RTL8373_LED3_2_SET3_CTRL0_SET3_LED3_SEL0_MASK, sel0))!= RT_ERR_OK) + return retVal; + if((retVal = rtl8373_setAsicRegBits(RTL8373_LED3_0_SET3_2_CTRL1_ADDR, RTL8373_LED3_0_SET3_2_CTRL1_SET3_LED3_SEL1_MASK, sel1))!= RT_ERR_OK) + return retVal; + } + else + return RT_ERR_INPUT; + } + else + return RT_ERR_INPUT; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_portLedConfig_set + * Description: + * Select led config for per port + * Input: + * port - port 0 ~ 8 + * setid - 4 leds, 0 ~ 3 + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_MASK - Error portmask + * Note: + * The API can be used to set LED per port config. + */ +rtk_api_ret_t dal_rtl8373_portLedConfig_set(rtk_port_t port, rtk_led_set_t setid) +{ + return rtl8373_setAsicRegBits(RTL8373_LED_PORT_SET_SEL_CTRL_ADDR(port), RTL8373_LED_PORT_SET_SEL_CTRL_LED_SET_PSEL_MASK(port), setid); +} + + +/* Function Name: + * dal_rtl8373_portLedConfig_get + * Description: + * Get led config for per port + * Input: + * port - port 0 ~ 8 + * setid - 4 leds, 0 ~ 3 + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_MASK - Error portmask + * Note: + * The API can be used to get LED per port config. + */ +rtk_api_ret_t dal_rtl8373_portLedConfig_get(rtk_port_t port, rtk_led_set_t * pSetid) +{ + return rtl8373_getAsicRegBits(RTL8373_LED_PORT_SET_SEL_CTRL_ADDR(port), RTL8373_LED_PORT_SET_SEL_CTRL_LED_SET_PSEL_MASK(port), pSetid); +} + + + + +/* Function Name: + * dal_rtl8373_led_blinkRate_set + * Description: + * Set Led blink rate + * Input: + * rate - + * LED_BLINKRATE_32MS=1, + * LED_BLINKRATE_64MS, + * LED_BLINKRATE_128MS, + * LED_BLINKRATE_256MS, + * LED_BLINKRATE_512MS, + * LED_BLINKRATE_1024MS,. + * LED_BLINKRATE_END, * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_MASK - Error portmask + * Note: + * The API can be used to enable LED per port per group. + */ +rtk_api_ret_t dal_rtl8373_led_blinkRate_set(rtk_led_blink_rate_t rate) +{ + return rtl8373_setAsicRegBits(RTL8373_LED_GLB_CTRL_ADDR, RTL8373_LED_GLB_CTRL_BLINK_TIME_SEL_MASK, rate); +} + +/* Function Name: + * dal_rtl8373_led_blinkRate_get + * Description: + * Set Led blink rate + * Input: + * pRate - + * LED_BLINKRATE_32MS=1, + * LED_BLINKRATE_64MS, + * LED_BLINKRATE_128MS, + * LED_BLINKRATE_256MS, + * LED_BLINKRATE_512MS, + * LED_BLINKRATE_1024MS,. + * LED_BLINKRATE_END, * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_MASK - Error portmask + * Note: + * The API can be used to enable LED per port per group. + */ +rtk_api_ret_t dal_rtl8373_led_blinkRate_get(rtk_led_blink_rate_t * pRate) +{ + return rtl8373_getAsicRegBits(RTL8373_LED_GLB_CTRL_ADDR, RTL8373_LED_GLB_CTRL_BLINK_TIME_SEL_MASK, pRate); +} + + + diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_led.h b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_led.h new file mode 100755 index 00000000..bd85c8df --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_led.h @@ -0,0 +1,155 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8373 switch high-level API + * + * Feature : The file includes LED module high-layer API defination + * + */ + +#ifndef __DAL_RTL8373_LED_H__ +#define __DAL_RTL8373_LED_H__ +#include <../../led.h> + +/* Function Name: + * dal_rtl8373_led_config_set + * Description: + * Set Led congiuration + * Input: + * setid - 4 groups led setting 0 ~ 3 + * ledid - 4 leds, 0 ~ 3 + * pConfig . + * led_2p5g; + * led_two_pair_1g; + * led_1g; + * led_500m; + * led_100m; + * led_10m; + * led_link; + * led_link_flash; + * led_act; + * led_rx; + * led_tx; + * led_col; + * led_duplex; + * led_training; + * led_master; + * led_10g; + * led_two_pair_5g; + * led_5g; + * led_two_pair_2p5g; * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_MASK - Error portmask + * Note: + * The API can be used to enable LED per port per group. + */ +extern rtk_api_ret_t dal_rtl8373_led_config_set(rtk_led_set_t setid, rtk_uint32 ledid, rtk_led_config_t *pConfig); + + +/* Function Name: + * dal_rtl8373_portLedConfig_set + * Description: + * Select led config for per port + * Input: + * port - port 0 ~ 8 + * setid - 4 leds, 0 ~ 3 + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_MASK - Error portmask + * Note: + * The API can be used to set LED per port config. + */ +extern rtk_api_ret_t dal_rtl8373_portLedConfig_set(rtk_port_t port, rtk_led_set_t setid); + + +/* Function Name: + * dal_rtl8373_portLedConfig_get + * Description: + * Get led config for per port + * Input: + * port - port 0 ~ 8 + * setid - 4 leds, 0 ~ 3 + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_MASK - Error portmask + * Note: + * The API can be used to get LED per port config. + */ +extern rtk_api_ret_t dal_rtl8373_portLedConfig_get(rtk_port_t port, rtk_led_set_t * pSetid); + + + + +/* Function Name: + * dal_rtl8373_led_blinkRate_set + * Description: + * Set Led blink rate + * Input: + * rate - + * LED_BLINKRATE_32MS=1, + * LED_BLINKRATE_64MS, + * LED_BLINKRATE_128MS, + * LED_BLINKRATE_256MS, + * LED_BLINKRATE_512MS, + * LED_BLINKRATE_1024MS,. + * LED_BLINKRATE_END, * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_MASK - Error portmask + * Note: + * The API can be used to enable LED per port per group. + */ +extern rtk_api_ret_t dal_rtl8373_led_blinkRate_set(rtk_led_blink_rate_t rate); + +/* Function Name: + * dal_rtl8373_led_blinkRate_get + * Description: + * Set Led blink rate + * Input: + * pRate - + * LED_BLINKRATE_32MS=1, + * LED_BLINKRATE_64MS, + * LED_BLINKRATE_128MS, + * LED_BLINKRATE_256MS, + * LED_BLINKRATE_512MS, + * LED_BLINKRATE_1024MS,. + * LED_BLINKRATE_END, * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_MASK - Error portmask + * Note: + * The API can be used to enable LED per port per group. + */ +extern rtk_api_ret_t dal_rtl8373_led_blinkRate_get(rtk_led_blink_rate_t * pRate); + + + +#endif /* __DAL_RTL8373_LED_H__ */ + diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_lut.c b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_lut.c new file mode 100755 index 00000000..aedc3cb5 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_lut.c @@ -0,0 +1,4469 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8373 + * Feature : Here is a list of all functions and variables in LUT module. + * + */ + +#include +#include +#include +#include +#include +#include "l2.h" + +static void _rtl8373_fdbStUser2Smi( rtl8373_luttb *pLutSt, rtk_uint32 *pFdbSmi) +{ + /* L3 lookup */ + if(pLutSt->l3lookup) + { + pFdbSmi[0] = pLutSt->sip; + + pFdbSmi[1] = pLutSt->dip & 0xFFFFFFF; + pFdbSmi[1] |= (pLutSt->l3lookup & 0x0001) << 28; + pFdbSmi[1] |= (pLutSt->mbr & 0x0003) << 30; + + pFdbSmi[2] = (pLutSt->mbr >> 2) & 0xFF; + pFdbSmi[2] |= (pLutSt->igmp_idx & 0xFF) << 8; + pFdbSmi[2] |= (pLutSt->igmp_asic & 1) << 16; + + } + else if(pLutSt->mac.octet[0] & 0x01) /*Multicast L2 Lookup*/ + { + pFdbSmi[0] = pLutSt->mac.octet[5]|(pLutSt->mac.octet[4] << 8)|(pLutSt->mac.octet[3] << 16)|(pLutSt->mac.octet[2] << 24); + + pFdbSmi[1] = pLutSt->mac.octet[1]| (pLutSt->mac.octet[0] << 8); + pFdbSmi[1] |= (pLutSt->cvid_fid & 0xFFF) << 16; + pFdbSmi[1] |= (pLutSt->l3lookup & 1) << 28; + pFdbSmi[1] |= (pLutSt->ivl_svl & 1) << 29; + pFdbSmi[1] |= (pLutSt->mbr & 0x3) << 30; + + pFdbSmi[2] = (pLutSt->mbr >> 2) & 0xFF; + pFdbSmi[2] |= (pLutSt->igmp_idx & 0xFF) << 8; + pFdbSmi[2] |= (pLutSt->igmp_asic & 1) << 16; + } + else /*Asic auto-learning*/ + { + pFdbSmi[0] = pLutSt->mac.octet[5]|(pLutSt->mac.octet[4] << 8)|(pLutSt->mac.octet[3] << 16)|(pLutSt->mac.octet[2] << 24); + + pFdbSmi[1] = pLutSt->mac.octet[1]| (pLutSt->mac.octet[0] << 8); + pFdbSmi[1] |= (pLutSt->cvid_fid & 0xFFF) << 16; + pFdbSmi[1] |= (pLutSt->l3lookup & 1) << 28; + pFdbSmi[1] |= (pLutSt->ivl_svl & 1) << 29; + pFdbSmi[1] |= (pLutSt->spa & 0x3) << 30; + + pFdbSmi[2] = pLutSt->spa >> 2; + pFdbSmi[2] |= (pLutSt->age & 7) << 2; + pFdbSmi[2] |= (pLutSt->auth & 1) << 5; + pFdbSmi[2] |= (pLutSt->nosalearn & 1) << 16; + + } +} + + +static void _rtl8373_fdbStSmi2User( rtl8373_luttb *pLutSt, rtk_uint32 *pFdbSmi) +{ + //printf("0x%x-0x%x-0x%x\n", pFdbSmi[0],pFdbSmi[1],pFdbSmi[2]); + /*L3 lookup*/ + if(pFdbSmi[1] & 0x10000000) + { + pLutSt->sip = pFdbSmi[0]; + pLutSt->dip = pFdbSmi[1] & 0xFFFFFFF; + pLutSt->mbr = ((pFdbSmi[2] & 0x00FF) << 2) | ((pFdbSmi[1] >> 30) & 3); + pLutSt->l3lookup = (pFdbSmi[1] >> 28) & 1; + pLutSt->igmp_asic = (pFdbSmi[2] >> 16) & 1; + pLutSt->igmp_idx = (pFdbSmi[2] >> 8) & 0xff; + } + else if((pFdbSmi[1] >> 8) & 0x01) /*Multicast L2 Lookup*/ + { + printf("l2 multicast\n"); + pLutSt->mac.octet[5] = pFdbSmi[0] & 0xFF; + pLutSt->mac.octet[4] = (pFdbSmi[0] & 0xFF00) >> 8; + pLutSt->mac.octet[3] = (pFdbSmi[0] & 0xFF0000) >> 16; + pLutSt->mac.octet[2] = (pFdbSmi[0] & 0xFF000000) >> 24; + pLutSt->mac.octet[1] = (pFdbSmi[1] & 0xFF); + pLutSt->mac.octet[0] = (pFdbSmi[1] & 0xFF00) >> 8; + + pLutSt->cvid_fid = (pFdbSmi[1] >> 16) & 0x0FFF; + pLutSt->l3lookup = (pFdbSmi[1] >> 28) & 1; + pLutSt->ivl_svl = (pFdbSmi[1] >> 29) & 1; + pLutSt->mbr = ((pFdbSmi[2] & 0x00FF) << 2) | ((pFdbSmi[1] >> 30) & 3); + pLutSt->igmp_asic = (pFdbSmi[2] >> 16) & 1; + pLutSt->igmp_idx = (pFdbSmi[2] >> 8) & 0xff; + + } + else /*Asic auto-learning*/ + { + pLutSt->mac.octet[5] = pFdbSmi[0] & 0xFF; + pLutSt->mac.octet[4] = (pFdbSmi[0] & 0xFF00) >> 8; + pLutSt->mac.octet[3] = (pFdbSmi[0] & 0xFF0000) >> 16; + pLutSt->mac.octet[2] = (pFdbSmi[0] & 0xFF000000) >> 24; + pLutSt->mac.octet[1] = (pFdbSmi[1] & 0xFF); + pLutSt->mac.octet[0] = (pFdbSmi[1] & 0xFF00) >> 8; + + pLutSt->cvid_fid = (pFdbSmi[1] >> 16) & 0x0FFF; + pLutSt->l3lookup = (pFdbSmi[1] >> 28) & 1; + pLutSt->ivl_svl = (pFdbSmi[1] >> 29) & 1; + pLutSt->spa = ((pFdbSmi[2] & 0x3) << 2) | ((pFdbSmi[1] >> 30) & 3); + pLutSt->age = ((pFdbSmi[2] >> 2) & 0x7); + pLutSt->auth = ((pFdbSmi[2] >> 5) & 0x1); + + pLutSt->nosalearn = (pFdbSmi[2] >> 16) & 1; + } +} + + + +static rtk_api_ret_t _rtl8373_getL2LookupTb(rtk_uint32 method, rtl8373_luttb *pL2Table) +{ +#if 1 + ret_t retVal; + rtk_uint32 regData; + rtk_uint32* accessPtr; + rtk_uint32 i; + rtk_uint32 smil2Table[RTL8373_LUT_TABLE_SIZE]; + rtk_uint32 busyCounter; + rtk_uint32 tblCmd; + + if(pL2Table->wait_time == 0) + busyCounter = RTL8373_LUT_BUSY_CHECK_NO; + else + busyCounter = pL2Table->wait_time; + + while(busyCounter) + { + retVal = rtl8373_getAsicRegBit(RTL8373_ITA_CTRL0_ADDR, RTL8373_ITA_CTRL0_TLB_EXECUTE_OFFSET,®Data); + if(retVal != RT_ERR_OK) + return retVal; + + pL2Table->lookup_busy = regData; + if(!pL2Table->lookup_busy) + break; + + busyCounter --; + if(busyCounter == 0) + return RT_ERR_BUSYWAIT_TIMEOUT; + } + + retVal = rtl8373_setAsicRegBits(RTL8373_ITA_L2_CTRL_ADDR, RTL8373_ITA_L2_CTRL_READ_MTHD_MASK, method); + if(retVal != RT_ERR_OK) + return retVal; +#if 0 + retVal = rtl8373_setAsicRegBit(RTL8373_ITA_L2_CTRL_ADDR, RTL8373_ITA_L2_CTRL_ENTRY_CLR_OFFSET, 0); + if(retVal != RT_ERR_OK) + return retVal; +#endif + switch(method) + { + case RTL8373_LUTREADMETHOD_ADDRESS: + case RTL8373_LUTREADMETHOD_NEXT_ADDRESS: + case RTL8373_LUTREADMETHOD_NEXT_L2UC: + case RTL8373_LUTREADMETHOD_NEXT_L2MC: + case RTL8373_LUTREADMETHOD_NEXT_L3MC: + case RTL8373_LUTREADMETHOD_NEXT_L2L3MC: + + tblCmd = (1|(0 << 1)|(4 << 8) | (pL2Table->address << RTL8373_ITA_CTRL0_TBL_ADDR_OFFSET)); + retVal = rtl8373_setAsicReg(RTL8373_ITA_CTRL0_ADDR, tblCmd); + if(retVal != RT_ERR_OK) + return retVal; + break; + case RTL8373_LUTREADMETHOD_MAC: + memset(smil2Table, 0x00, sizeof(rtk_uint32) * RTL8373_LUT_TABLE_SIZE); + _rtl8373_fdbStUser2Smi(pL2Table, smil2Table); + + accessPtr = smil2Table; + regData = *accessPtr; + + for(i=0; iaddress); + if(retVal != RT_ERR_OK) + return retVal; + printf("spa is %d\n",pL2Table->spa); + retVal = rtl8373_setAsicRegBits(RTL8373_ITA_L2_CTRL_ADDR, RTL8373_ITA_L2_CTRL_PORT_NUM_MASK, pL2Table->spa); + if(retVal != RT_ERR_OK) + return retVal; + + tblCmd = (1|(0 << 1)|(4 << 8) | (pL2Table->address << RTL8373_ITA_CTRL0_TBL_ADDR_OFFSET)); + retVal = rtl8373_setAsicReg(RTL8373_ITA_CTRL0_ADDR, tblCmd); + if(retVal != RT_ERR_OK) + return retVal; + printf("tblcmd is 0x%x\n",tblCmd); + break; + default: + return RT_ERR_INPUT; + } + + + + if(pL2Table->wait_time == 0) + busyCounter = RTL8373_LUT_BUSY_CHECK_NO; + else + busyCounter = pL2Table->wait_time; + + while(busyCounter) + { + retVal = rtl8373_getAsicRegBit(RTL8373_ITA_CTRL0_ADDR, RTL8373_ITA_CTRL0_TLB_EXECUTE_OFFSET,®Data); + if(retVal != RT_ERR_OK) + return retVal; + + pL2Table->lookup_busy = regData; + if(!pL2Table->lookup_busy) + break; + + busyCounter --; + if(busyCounter == 0) + return RT_ERR_BUSYWAIT_TIMEOUT; + } + + retVal = rtl8373_getAsicRegBit(RTL8373_ITA_L2_CTRL_ADDR, RTL8373_ITA_L2_CTRL_ACT_STS_OFFSET,®Data); + if(retVal != RT_ERR_OK) + return retVal; + pL2Table->lookup_hit = regData; + if(!pL2Table->lookup_hit) + return RT_ERR_L2_ENTRY_NOTFOUND; + + /*Read access address*/ + retVal = rtl8373_getAsicRegBits(RTL8373_ITA_L2_CTRL_ADDR, RTL8373_ITA_L2_CTRL_TBL_ADDR_MASK, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + pL2Table->address = (regData & 0xffff); + + retVal = rtl8373_getAsicReg(RTL8373_ITA_L2_CTRL_ADDR, ®Data); + + /*read L2 entry */ + memset(smil2Table, 0x00, sizeof(rtk_uint32) * RTL8373_LUT_TABLE_SIZE); + + accessPtr = smil2Table; + + for(i = 0; i < RTL8373_LUT_TABLE_SIZE; i++) + { + retVal = rtl8373_getAsicReg(RTL8373_ITA_READ_DATA0_ADDR(i), ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + *accessPtr = regData; + + accessPtr ++; + } + + _rtl8373_fdbStSmi2User(pL2Table, smil2Table); +#endif + return RT_ERR_OK; +} + + +static rtk_api_ret_t _rtl8373_setL2LookupTb(rtl8373_luttb *pL2Table) +{ +#if 1 + + ret_t retVal; + rtk_uint32 regData; + rtk_uint32 *accessPtr; + rtk_uint32 i; + rtk_uint32 smil2Table[RTL8373_LUT_TABLE_SIZE]; + rtk_uint32 tblCmd; + rtk_uint32 busyCounter; + memset(smil2Table, 0x00, sizeof(rtk_uint16) * RTL8373_LUT_TABLE_SIZE); + _rtl8373_fdbStUser2Smi(pL2Table, smil2Table); + + if(pL2Table->wait_time == 0) + busyCounter = RTL8373_LUT_BUSY_CHECK_NO; + else + busyCounter = pL2Table->wait_time; + + while(busyCounter) + { + retVal = rtl8373_getAsicRegBit(RTL8373_ITA_CTRL0_ADDR, RTL8373_ITA_CTRL0_TLB_EXECUTE_OFFSET,®Data); + if(retVal != RT_ERR_OK) + return retVal; + + pL2Table->lookup_busy = regData; + if(!regData) + break; + + busyCounter --; + if(busyCounter == 0) + return RT_ERR_BUSYWAIT_TIMEOUT; + } + + accessPtr = smil2Table; + + for(i = 0; i < RTL8373_LUT_TABLE_SIZE; i++) + { + regData = *(accessPtr + i); + retVal = rtl8373_setAsicReg(RTL8373_ITA_WRITE_DATA0_ADDR(i), regData); + + if(retVal != RT_ERR_OK) + return retVal; + } +#if 0 + retVal = rtl8373_setAsicRegBit(RTL8373_ITA_L2_CTRL_ADDR, RTL8373_ITA_L2_CTRL_ENTRY_CLR_OFFSET, 0); + if(retVal != RT_ERR_OK) + return retVal; +#endif + tblCmd = (1<<1) | (4 << 8) | 1; + /* Write Command */ + + retVal = rtl8373_setAsicReg(RTL8373_ITA_CTRL0_ADDR, tblCmd); + if(retVal != RT_ERR_OK) + return retVal; + + if(pL2Table->wait_time == 0) + busyCounter = RTL8373_LUT_BUSY_CHECK_NO; + else + busyCounter = pL2Table->wait_time; + + while(busyCounter) + { + retVal = rtl8373_getAsicRegBit(RTL8373_ITA_CTRL0_ADDR, RTL8373_ITA_CTRL0_TLB_EXECUTE_OFFSET,®Data); + if(retVal != RT_ERR_OK) + return retVal; + + pL2Table->lookup_busy = regData; + if(!regData) + break; + + busyCounter --; + if(busyCounter == 0) + return RT_ERR_BUSYWAIT_TIMEOUT; + } + + /*Read access status*/ + retVal = rtl8373_getAsicRegBit(RTL8373_ITA_L2_CTRL_ADDR, RTL8373_ITA_L2_CTRL_ACT_STS_OFFSET, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + pL2Table->lookup_hit = regData; + if(!pL2Table->lookup_hit) + return RT_ERR_FAILED; + + /*Read access address*/ + retVal = rtl8373_getAsicRegBits(RTL8373_ITA_L2_CTRL_ADDR, RTL8373_ITA_L2_CTRL_TBL_ADDR_MASK, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + pL2Table->address = (regData & 0xffff); + pL2Table->lookup_busy = 0; +#endif + return RT_ERR_OK; +} + + +static rtk_api_ret_t _rtl8373_clearL2LookupTb(rtk_uint32 index) +{ +#if 1 + + ret_t retVal; + rtk_uint32 regData; + //rtk_uint32 *accessPtr; + //rtk_uint32 smil2Table[RTL8373_LUT_TABLE_SIZE]; + rtk_uint32 tblCmd; + rtk_uint32 busyCounter; + //memset(smil2Table, 0x00, sizeof(rtk_uint16) * RTL8373_LUT_TABLE_SIZE); + + busyCounter = RTL8373_LUT_BUSY_CHECK_NO; + + while(busyCounter) + { + retVal = rtl8373_getAsicRegBit(RTL8373_ITA_CTRL0_ADDR, RTL8373_ITA_CTRL0_TLB_EXECUTE_OFFSET,®Data); + if(retVal != RT_ERR_OK) + return retVal; + + if(!regData) + break; + + busyCounter --; + if(busyCounter == 0) + return RT_ERR_BUSYWAIT_TIMEOUT; + } + + //accessPtr = smil2Table; +#if 0 + retVal = rtl8373_setAsicRegBits(RTL8373_ITA_CTRL0_ADDR, RTL8373_ITA_CTRL0_TBL_ADDR_MASK, index); + if(retVal != RT_ERR_OK) + return retVal; +#endif + + retVal = rtl8373_setAsicRegBit(RTL8373_ITA_L2_CTRL_ADDR, RTL8373_ITA_L2_CTRL_ENTRY_CLR_OFFSET, 1); + if(retVal != RT_ERR_OK) + return retVal; + + + tblCmd = (index << 16)|(1<<1) | (4 << 8) | 1; + /* Write Command */ + retVal = rtl8373_setAsicReg(RTL8373_ITA_CTRL0_ADDR, tblCmd); + if(retVal != RT_ERR_OK) + return retVal; + //printf("cmd data 0x%x\n", tblCmd); + + busyCounter = RTL8373_LUT_BUSY_CHECK_NO; + + while(busyCounter) + { + retVal = rtl8373_getAsicRegBit(RTL8373_ITA_CTRL0_ADDR, RTL8373_ITA_CTRL0_TLB_EXECUTE_OFFSET,®Data); + if(retVal != RT_ERR_OK) + return retVal; + + if(!regData) + break; + + busyCounter --; + if(busyCounter == 0) + return RT_ERR_BUSYWAIT_TIMEOUT; + } + +#if 1 + retVal = rtl8373_setAsicRegBit(RTL8373_ITA_L2_CTRL_ADDR, RTL8373_ITA_L2_CTRL_ENTRY_CLR_OFFSET, 0); + if(retVal != RT_ERR_OK) + return retVal; +#endif + /*Read access status*/ + retVal = rtl8373_getAsicRegBit(RTL8373_ITA_L2_CTRL_ADDR, RTL8373_ITA_L2_CTRL_ACT_STS_OFFSET, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + +#endif + return RT_ERR_OK; +} + + + + + + + +static rtk_api_ret_t _rtl8373_getLutIPMCGroup(rtk_uint32 index, ipaddr_t *pGroup_addr, rtk_uint32 *pPmask, rtk_uint32 *pValid) +{ + rtk_uint32 regAddr, regData; + ret_t retVal; + + if(index > RTL8373_LUT_IPMCGRP_TABLE_MAX) + return RT_ERR_INPUT; + + if (NULL == pGroup_addr) + return RT_ERR_NULL_POINTER; + + if (NULL == pPmask) + return RT_ERR_NULL_POINTER; + + /* Group address */ + regAddr = RTL8373_IPMC_GROUP_DIP_ADDR(index); + if( (retVal = rtl8373_getAsicReg(regAddr, ®Data)) != RT_ERR_OK) + return retVal; + + *pGroup_addr = regData | 0xE0000000; + + + /* portmask */ + regAddr = RTL8373_IPMC_GROUP_PMSK_ADDR(index); + if( (retVal = rtl8373_getAsicReg(regAddr, ®Data)) != RT_ERR_OK) + return retVal; + + *pPmask = regData; + + /* valid */ + regAddr = RTL8373_IPMC_GROUP_VALID_ADDR(index); + if( (retVal = rtl8373_getAsicRegBit(regAddr, RTL8373_IPMC_GROUP_VALID_VALID_OFFSET(index), ®Data)) != RT_ERR_OK) + return retVal; + + *pValid = regData; + + return RT_ERR_OK; +} + +static rtk_api_ret_t _rtl8373_setLutIPMCGroup(rtk_uint32 index, ipaddr_t group_addr, rtk_uint32 pmask, rtk_uint32 valid) +{ + rtk_uint32 regAddr, regData; + ipaddr_t ipData; + ret_t retVal; + + if(index > RTL8373_LUT_IPMCGRP_TABLE_MAX) + return RT_ERR_INPUT; + + ipData = group_addr; + + if( (ipData & 0xF0000000) != 0xE0000000) /* not in 224.0.0.0 ~ 239.255.255.255 */ + return RT_ERR_INPUT; + + /* Group Address */ + regAddr = RTL8373_IPMC_GROUP_DIP_ADDR(index); + + if( (retVal = rtl8373_setAsicReg(regAddr, ipData)) != RT_ERR_OK) + return retVal; + + /* portmask */ + regAddr = RTL8373_IPMC_GROUP_PMSK_ADDR(index); + regData = pmask; + + if( (retVal = rtl8373_setAsicReg(regAddr, regData)) != RT_ERR_OK) + return retVal; + + /* valid */ + regAddr = RTL8373_IPMC_GROUP_VALID_ADDR(index); + if( (retVal = rtl8373_setAsicRegBit(regAddr, RTL8373_IPMC_GROUP_VALID_VALID_OFFSET(index), valid)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + + + +/* Function Name: + * dal_rtl8373_l2_init + * Description: + * Initialize lut function. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * + */ +rtk_api_ret_t dal_rtl8373_l2_init(void) +{ + + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_l2_addr_add + * Description: + * Add LUT unicast entry. + * Input: + * pMac - 6 bytes unicast(I/G bit is 0) mac address to be written into LUT. + * pL2_data - Unicast entry parameter + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_L2_FID - Invalid FID . + * RT_ERR_L2_INDEXTBL_FULL - hashed index is full of entries. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * If the unicast mac address already existed in LUT, it will udpate the status of the entry. + * Otherwise, it will find an empty or asic auto learned entry to write. If all the entries + * with the same hash value can't be replaced, ASIC will return a RT_ERR_L2_INDEXTBL_FULL error. + */ + +rtk_api_ret_t dal_rtl8373_l2_addr_add(rtk_mac_t *pMac, rtk_l2_ucastAddr_t *pL2_data) +{ + + rtk_api_ret_t retVal; + rtk_uint32 method; + rtl8373_luttb l2Table; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* must be unicast address */ + if ((pMac == NULL) || (pMac->octet[0] & 0x1)) + return RT_ERR_MAC; + + if(pL2_data == NULL) + return RT_ERR_MAC; + + RTK_CHK_PORT_VALID(pL2_data->port); + + if (pL2_data->ivl >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if (pL2_data->is_static>= RTK_ENABLE_END) + return RT_ERR_INPUT; + + memset(&l2Table, 0, sizeof(rtl8373_luttb)); + + /* fill key (MAC,FID) to get L2 entry */ + memcpy(l2Table.mac.octet, pMac->octet, ETHER_ADDR_LEN); + l2Table.ivl_svl = pL2_data->ivl; + l2Table.cvid_fid = pL2_data->vid_fid; + method = RTL8373_LUTREADMETHOD_MAC; + retVal = _rtl8373_getL2LookupTb(method, &l2Table); + if (RT_ERR_OK == retVal ) + { + memcpy(l2Table.mac.octet, pMac->octet, ETHER_ADDR_LEN); + l2Table.ivl_svl = pL2_data->ivl; + l2Table.cvid_fid = pL2_data->vid_fid; + l2Table.spa = rtk_switch_port_L2P_get(pL2_data->port); + l2Table.nosalearn = pL2_data->is_static; + l2Table.l3lookup = 0; + l2Table.age = 6; + l2Table.auth = pL2_data->auth; + if((retVal = _rtl8373_setL2LookupTb(&l2Table)) != RT_ERR_OK) + return retVal; + + pL2_data->address = l2Table.address; + return RT_ERR_OK; + } + else if (RT_ERR_L2_ENTRY_NOTFOUND == retVal ) + { + memset(&l2Table, 0, sizeof(rtl8373_luttb)); + memcpy(l2Table.mac.octet, pMac->octet, ETHER_ADDR_LEN); + l2Table.ivl_svl = pL2_data->ivl; + l2Table.cvid_fid = pL2_data->vid_fid; + l2Table.spa = rtk_switch_port_L2P_get(pL2_data->port); + l2Table.nosalearn = pL2_data->is_static; + l2Table.l3lookup = 0; + l2Table.age = 6; + l2Table.auth = pL2_data->auth; + + if ((retVal = _rtl8373_setL2LookupTb(&l2Table)) != RT_ERR_OK) + return retVal; + + pL2_data->address = l2Table.address; + + method = RTL8373_LUTREADMETHOD_MAC; + retVal = _rtl8373_getL2LookupTb(method, &l2Table); + if (RT_ERR_L2_ENTRY_NOTFOUND == retVal ) + return RT_ERR_L2_INDEXTBL_FULL; + else + return retVal; + } + else + return retVal; + + +} + + +/* Function Name: + * dal_rtl8373_l2_addr_get + * Description: + * Get LUT unicast entry. + * Input: + * pMac - 6 bytes unicast(I/G bit is 0) mac address to be written into LUT. + * Output: + * pL2_data - Unicast entry parameter + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_L2_FID - Invalid FID . + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * If the unicast mac address existed in LUT, it will return the port and fid where + * the mac is learned. Otherwise, it will return a RT_ERR_L2_ENTRY_NOTFOUND error. + */ +rtk_api_ret_t dal_rtl8373_l2_addr_get(rtk_mac_t *pMac, rtk_l2_ucastAddr_t *pL2_data) +{ + rtk_api_ret_t retVal; + rtk_uint32 method; + rtl8373_luttb l2Table; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* must be unicast address */ + if ((pMac == NULL) || (pMac->octet[0] & 0x1)) + return RT_ERR_MAC; + + if (pL2_data->ivl >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if (pL2_data->ivl == 1) + { + if (pL2_data->vid_fid> RTL8373_VIDMAX) + return RT_ERR_L2_VID; + } + else + { + if (pL2_data->vid_fid > RTL8373_FIDMAX) + return RT_ERR_L2_FID; + } + + memset(&l2Table, 0, sizeof(rtl8373_luttb)); + + memcpy(l2Table.mac.octet, pMac->octet, ETHER_ADDR_LEN); + l2Table.ivl_svl = pL2_data->ivl; + l2Table.cvid_fid = pL2_data->vid_fid; + method = RTL8373_LUTREADMETHOD_MAC; + //printf("====vid is %d\n", l2Table.cvid_fid ); + if ((retVal = _rtl8373_getL2LookupTb(method, &l2Table)) != RT_ERR_OK) + return retVal; + + memcpy(pL2_data->mac.octet, pMac->octet,ETHER_ADDR_LEN); + pL2_data->port = rtk_switch_port_P2L_get(l2Table.spa); + pL2_data->ivl = l2Table.ivl_svl; + + pL2_data->vid_fid = l2Table.cvid_fid; + + + pL2_data->is_static = l2Table.nosalearn; + pL2_data->address = l2Table.address; + pL2_data->auth = l2Table.auth; + pL2_data->age = l2Table.age; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_l2_addr_next_get + * Description: + * Get Next LUT unicast entry. + * Input: + * read_method - The reading method. + * port - The port number if the read_metohd is READMETHOD_NEXT_L2UCSPA + * pAddress - The Address ID + * Output: + * pL2_data - Unicast entry parameter + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_L2_FID - Invalid FID . + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * Get the next unicast entry after the current entry pointed by pAddress. + * The address of next entry is returned by pAddress. User can use (address + 1) + * as pAddress to call this API again for dumping all entries is LUT. + */ +rtk_api_ret_t dal_rtl8373_l2_addr_next_get(rtk_l2_read_method_t read_method, rtk_port_t port, rtk_uint32 *pAddress, rtk_l2_ucastAddr_t *pL2_data) +{ + rtk_api_ret_t retVal; + rtk_uint32 method; + rtl8373_luttb l2Table; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Error Checking */ + if ((pL2_data == NULL) || (pAddress == NULL)) + return RT_ERR_MAC; + + if(read_method == READMETHOD_NEXT_L2UC) + method = RTL8373_LUTREADMETHOD_NEXT_L2UC; + else if(read_method == READMETHOD_NEXT_L2UCSPA) + method = RTL8373_LUTREADMETHOD_NEXT_L2UCSPA; + else + return RT_ERR_INPUT; + + if(read_method == READMETHOD_NEXT_L2UCSPA) + { + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + } + + if(*pAddress > RTK_MAX_LUT_ADDR_ID ) + return RT_ERR_L2_L2UNI_PARAM; + + memset(pL2_data, 0, sizeof(rtk_l2_ucastAddr_t)); + memset(&l2Table, 0, sizeof(rtl8373_luttb)); + l2Table.address = *pAddress; + + if(read_method == READMETHOD_NEXT_L2UCSPA) + l2Table.spa = rtk_switch_port_L2P_get(port); + + if ((retVal = _rtl8373_getL2LookupTb(method, &l2Table)) != RT_ERR_OK) + return retVal; + + if(l2Table.address < *pAddress) + return RT_ERR_L2_ENTRY_NOTFOUND; + + memcpy(pL2_data->mac.octet, l2Table.mac.octet, ETHER_ADDR_LEN); + pL2_data->port = rtk_switch_port_P2L_get(l2Table.spa); + pL2_data->ivl = l2Table.ivl_svl; + + pL2_data->vid_fid = l2Table.cvid_fid; + + + pL2_data->is_static = l2Table.nosalearn; + pL2_data->address = l2Table.address; + pL2_data->auth = l2Table.auth; + pL2_data->age = l2Table.age; + + *pAddress = l2Table.address; + + return RT_ERR_OK; + +} + + +/* Function Name: + * dal_rtl8373_l2_addr_del + * Description: + * Delete LUT unicast entry. + * Input: + * pMac - 6 bytes unicast(I/G bit is 0) mac address to be written into LUT. + * fid - Filtering database + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_L2_FID - Invalid FID . + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * If the mac has existed in the LUT, it will be deleted. Otherwise, it will return RT_ERR_L2_ENTRY_NOTFOUND. + */ +rtk_api_ret_t dal_rtl8373_l2_addr_del(rtk_mac_t *pMac, rtk_l2_ucastAddr_t *pL2_data) +{ + rtk_api_ret_t retVal; + rtk_uint32 method; + rtl8373_luttb l2Table; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* must be unicast address */ + if ((pMac == NULL) || (pMac->octet[0] & 0x1)) + return RT_ERR_MAC; + + if (pL2_data->ivl >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if (pL2_data->ivl == 1) + { + if (pL2_data->vid_fid > RTL8373_VIDMAX) + return RT_ERR_L2_VID; + } + else + { + if (pL2_data->vid_fid > RTL8373_FIDMAX) + return RT_ERR_L2_FID; + } + + memset(&l2Table, 0, sizeof(rtl8373_luttb)); + + /* fill key (MAC,FID) to get L2 entry */ + memcpy(l2Table.mac.octet, pMac->octet, ETHER_ADDR_LEN); + l2Table.ivl_svl = pL2_data->ivl; + l2Table.cvid_fid = pL2_data->vid_fid; + method = RTL8373_LUTREADMETHOD_MAC; + retVal = _rtl8373_getL2LookupTb(method, &l2Table); + if (RT_ERR_OK == retVal) + { + memcpy(l2Table.mac.octet, pMac->octet, ETHER_ADDR_LEN); + l2Table.ivl_svl = pL2_data->ivl; + l2Table.cvid_fid = pL2_data->vid_fid; + l2Table.spa = 0; + l2Table.nosalearn = 0; + l2Table.age = 0; + l2Table.auth = 0; + if((retVal = _rtl8373_setL2LookupTb(&l2Table)) != RT_ERR_OK) + return retVal; + + pL2_data->address = l2Table.address; + return RT_ERR_OK; + } + else + return retVal; +} + + + +/* Function Name: + * dal_rtl8373_l2_mcastAddr_add + * Description: + * Add LUT multicast entry. + * Input: + * pMcastAddr - L2 multicast entry structure + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_L2_FID - Invalid FID . + * RT_ERR_L2_VID - Invalid VID . + * RT_ERR_L2_INDEXTBL_FULL - hashed index is full of entries. + * RT_ERR_PORT_MASK - Invalid portmask. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * If the multicast mac address already existed in the LUT, it will udpate the + * port mask of the entry. Otherwise, it will find an empty or asic auto learned + * entry to write. If all the entries with the same hash value can't be replaced, + * ASIC will return a RT_ERR_L2_INDEXTBL_FULL error. + */ +rtk_api_ret_t dal_rtl8373_l2_mcastAddr_add(rtk_l2_mcastAddr_t *pMcastAddr) +{ + rtk_api_ret_t retVal; + rtk_uint32 method; + rtl8373_luttb l2Table; + rtk_uint32 pmask; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pMcastAddr) + return RT_ERR_NULL_POINTER; + + /* must be L2 multicast address */ + if( (pMcastAddr->mac.octet[0] & 0x01) != 0x01) + return RT_ERR_MAC; + + RTK_CHK_PORTMASK_VALID(&pMcastAddr->portmask); + + if(pMcastAddr->ivl == 1) + { + if (pMcastAddr->vid_fid > RTL8373_VIDMAX) + return RT_ERR_L2_VID; + } + else if(pMcastAddr->ivl == 0) + { + if (pMcastAddr->vid_fid > RTL8373_FIDMAX) + return RT_ERR_L2_FID; + } + else + return RT_ERR_INPUT; + + /* Get physical port mask */ + if ((retVal = rtk_switch_portmask_L2P_get(&pMcastAddr->portmask, &pmask)) != RT_ERR_OK) + return retVal; + + memset(&l2Table, 0, sizeof(rtl8373_luttb)); + + /* fill key (MAC,FID) to get L2 entry */ + memcpy(l2Table.mac.octet, pMcastAddr->mac.octet, ETHER_ADDR_LEN); + l2Table.ivl_svl = pMcastAddr->ivl; + + l2Table.cvid_fid = pMcastAddr->vid_fid; + + + method = RTL8373_LUTREADMETHOD_MAC; + retVal = _rtl8373_getL2LookupTb(method, &l2Table); + if (RT_ERR_OK == retVal) + { + memcpy(l2Table.mac.octet, pMcastAddr->mac.octet, ETHER_ADDR_LEN); + l2Table.ivl_svl = pMcastAddr->ivl; + + l2Table.cvid_fid = pMcastAddr->vid_fid; + + l2Table.mbr = pmask; + l2Table.igmp_asic = pMcastAddr->igmp_asic; + l2Table.igmp_idx = pMcastAddr->igmp_index; + l2Table.l3lookup = 0; + if((retVal = _rtl8373_setL2LookupTb(&l2Table)) != RT_ERR_OK) + return retVal; + + pMcastAddr->address = l2Table.address; + return RT_ERR_OK; + } + else if (RT_ERR_L2_ENTRY_NOTFOUND == retVal) + { + memset(&l2Table, 0, sizeof(rtl8373_luttb)); + memcpy(l2Table.mac.octet, pMcastAddr->mac.octet, ETHER_ADDR_LEN); + l2Table.ivl_svl = pMcastAddr->ivl; + l2Table.cvid_fid = pMcastAddr->vid_fid; + + l2Table.mbr = pmask; + l2Table.igmp_asic = pMcastAddr->igmp_asic; + l2Table.igmp_idx = pMcastAddr->igmp_index; + l2Table.l3lookup = 0; + if ((retVal = _rtl8373_setL2LookupTb(&l2Table)) != RT_ERR_OK) + return retVal; + + pMcastAddr->address = l2Table.address; + + method = RTL8373_LUTREADMETHOD_MAC; + retVal = _rtl8373_getL2LookupTb(method, &l2Table); + if (RT_ERR_L2_ENTRY_NOTFOUND == retVal) + return RT_ERR_L2_INDEXTBL_FULL; + else + return retVal; + } + else + return retVal; + +} + + +/* Function Name: + * dal_rtl8373_l2_mcastAddr_get + * Description: + * Get LUT multicast entry. + * Input: + * pMcastAddr - L2 multicast entry structure + * Output: + * pMcastAddr - L2 multicast entry structure + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_L2_FID - Invalid FID . + * RT_ERR_L2_VID - Invalid VID . + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * If the multicast mac address existed in the LUT, it will return the port where + * the mac is learned. Otherwise, it will return a RT_ERR_L2_ENTRY_NOTFOUND error. + */ +rtk_api_ret_t dal_rtl8373_l2_mcastAddr_get(rtk_l2_mcastAddr_t *pMcastAddr) +{ + rtk_api_ret_t retVal; + rtk_uint32 method; + rtl8373_luttb l2Table; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pMcastAddr) + return RT_ERR_NULL_POINTER; + + /* must be L2 multicast address */ + if( (pMcastAddr->mac.octet[0] & 0x01) != 0x01) + return RT_ERR_MAC; + + if(pMcastAddr->ivl == 1) + { + if (pMcastAddr->vid_fid> RTL8373_VIDMAX) + return RT_ERR_L2_VID; + } + else if(pMcastAddr->ivl == 0) + { + if (pMcastAddr->vid_fid > RTL8373_FIDMAX) + return RT_ERR_L2_FID; + } + else + return RT_ERR_INPUT; + + memset(&l2Table, 0, sizeof(rtl8373_luttb)); + memcpy(l2Table.mac.octet, pMcastAddr->mac.octet, ETHER_ADDR_LEN); + l2Table.ivl_svl = pMcastAddr->ivl; + + l2Table.cvid_fid = pMcastAddr->vid_fid; + + method = RTL8373_LUTREADMETHOD_MAC; + + if ((retVal = _rtl8373_getL2LookupTb(method, &l2Table)) != RT_ERR_OK) + return retVal; + + pMcastAddr->address = l2Table.address; + pMcastAddr->igmp_asic = l2Table.igmp_asic; + pMcastAddr->igmp_index = l2Table.igmp_idx; + + /* Get Logical port mask */ + if ((retVal = rtk_switch_portmask_P2L_get(l2Table.mbr, &pMcastAddr->portmask)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_l2_mcastAddr_next_get + * Description: + * Get Next L2 Multicast entry. + * Input: + * pAddress - The Address ID + * Output: + * pMcastAddr - L2 multicast entry structure + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * Get the next L2 multicast entry after the current entry pointed by pAddress. + * The address of next entry is returned by pAddress. User can use (address + 1) + * as pAddress to call this API again for dumping all multicast entries is LUT. + */ +rtk_api_ret_t dal_rtl8373_l2_mcastAddr_next_get(rtk_uint32 *pAddress, rtk_l2_mcastAddr_t *pMcastAddr) +{ + rtk_api_ret_t retVal; + rtl8373_luttb l2Table; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Error Checking */ + if ((pAddress == NULL) || (pMcastAddr == NULL)) + return RT_ERR_INPUT; + + if(*pAddress > RTK_MAX_LUT_ADDR_ID ) + return RT_ERR_L2_L2UNI_PARAM; + + memset(pMcastAddr, 0, sizeof(rtk_l2_mcastAddr_t)); + memset(&l2Table, 0, sizeof(rtl8373_luttb)); + l2Table.address = *pAddress; + + if ((retVal = _rtl8373_getL2LookupTb(RTL8373_LUTREADMETHOD_NEXT_L2MC, &l2Table)) != RT_ERR_OK) + return retVal; + + if(l2Table.address < *pAddress) + return RT_ERR_L2_ENTRY_NOTFOUND; + + memcpy(pMcastAddr->mac.octet, l2Table.mac.octet, ETHER_ADDR_LEN); + pMcastAddr->ivl = l2Table.ivl_svl; + + pMcastAddr->vid_fid = l2Table.cvid_fid; + + pMcastAddr->address = l2Table.address; + pMcastAddr->igmp_asic = l2Table.igmp_asic; + pMcastAddr->igmp_index = l2Table.igmp_idx; + + /* Get Logical port mask */ + if ((retVal = rtk_switch_portmask_P2L_get(l2Table.mbr, &pMcastAddr->portmask)) != RT_ERR_OK) + return retVal; + + *pAddress = l2Table.address; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_l2_mcastAddr_del + * Description: + * Delete LUT multicast entry. + * Input: + * pMcastAddr - L2 multicast entry structure + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_L2_FID - Invalid FID . + * RT_ERR_L2_VID - Invalid VID . + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * If the mac has existed in the LUT, it will be deleted. Otherwise, it will return RT_ERR_L2_ENTRY_NOTFOUND. + */ +rtk_api_ret_t dal_rtl8373_l2_mcastAddr_del(rtk_l2_mcastAddr_t *pMcastAddr) +{ + rtk_api_ret_t retVal; + rtk_uint32 method; + rtl8373_luttb l2Table; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pMcastAddr) + return RT_ERR_NULL_POINTER; + + /* must be L2 multicast address */ + if( (pMcastAddr->mac.octet[0] & 0x01) != 0x01) + return RT_ERR_MAC; + + if(pMcastAddr->ivl == 1) + { + if (pMcastAddr->vid_fid > RTL8373_VIDMAX) + return RT_ERR_L2_VID; + } + else if(pMcastAddr->ivl == 0) + { + if (pMcastAddr->vid_fid > RTL8373_FIDMAX) + return RT_ERR_L2_FID; + } + else + return RT_ERR_INPUT; + + memset(&l2Table, 0, sizeof(rtl8373_luttb)); + + /* fill key (MAC,FID) to get L2 entry */ + memcpy(l2Table.mac.octet, pMcastAddr->mac.octet, ETHER_ADDR_LEN); + l2Table.ivl_svl = pMcastAddr->ivl; + + l2Table.cvid_fid = pMcastAddr->vid_fid; + + method = RTL8373_LUTREADMETHOD_MAC; + retVal = _rtl8373_getL2LookupTb(method, &l2Table); + if (RT_ERR_OK == retVal) + { +#if 0 + memcpy(l2Table.mac.octet, pMcastAddr->mac.octet, ETHER_ADDR_LEN); + l2Table.ivl_svl = pMcastAddr->ivl; + + l2Table.cvid_fid = pMcastAddr->vid_fid; + + l2Table.mbr = 0; + l2Table.igmp_asic = 0; + l2Table.igmp_idx = 0; + l2Table.l3lookup = 0; + if((retVal = _rtl8373_setL2LookupTb(&l2Table)) != RT_ERR_OK) + return retVal; + + pMcastAddr->address = l2Table.address; + return RT_ERR_OK; +#endif + pMcastAddr->address = l2Table.address; + return _rtl8373_clearL2LookupTb(l2Table.address); + + } + else + return retVal; +} + + +/* Function Name: + * dal_rtl8373_l2_ipMcastAddr_add + * Description: + * Add Lut IP multicast entry + * Input: + * pIpMcastAddr - IP Multicast entry + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_L2_INDEXTBL_FULL - hashed index is full of entries. + * RT_ERR_PORT_MASK - Invalid portmask. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * System supports L2 entry with IP multicast DIP/SIP to forward IP multicasting frame as user + * desired. If this function is enabled, then system will be looked up L2 IP multicast entry to + * forward IP multicast frame directly without flooding. + */ +rtk_api_ret_t dal_rtl8373_l2_ipMcastAddr_add(rtk_l2_ipMcastAddr_t *pIpMcastAddr) +{ + rtk_api_ret_t retVal; + rtk_uint32 method; + rtl8373_luttb l2Table; + rtk_uint32 pmask; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pIpMcastAddr) + return RT_ERR_NULL_POINTER; + + /* check port mask */ + RTK_CHK_PORTMASK_VALID(&pIpMcastAddr->portmask); + + if( (pIpMcastAddr->dip & 0xF0000000) != 0xE0000000) + return RT_ERR_INPUT; + + /* Get Physical port mask */ + if ((retVal = rtk_switch_portmask_L2P_get(&pIpMcastAddr->portmask, &pmask)) != RT_ERR_OK) + return retVal; + + memset(&l2Table, 0x00, sizeof(rtl8373_luttb)); + l2Table.sip = pIpMcastAddr->sip; + l2Table.dip = pIpMcastAddr->dip; + l2Table.l3lookup = 1; + l2Table.igmp_asic = pIpMcastAddr->igmp_asic; + l2Table.igmp_idx = pIpMcastAddr->igmp_index; + method = RTL8373_LUTREADMETHOD_MAC; + retVal = _rtl8373_getL2LookupTb(method, &l2Table); + if (RT_ERR_OK == retVal) + { + l2Table.sip = pIpMcastAddr->sip; + l2Table.dip = pIpMcastAddr->dip; + l2Table.mbr = pmask; + l2Table.igmp_asic = pIpMcastAddr->igmp_asic; + l2Table.igmp_idx = pIpMcastAddr->igmp_index; + l2Table.l3lookup = 1; + if((retVal = _rtl8373_setL2LookupTb(&l2Table)) != RT_ERR_OK) + return retVal; + + pIpMcastAddr->address = l2Table.address; + return RT_ERR_OK; + } + else if (RT_ERR_L2_ENTRY_NOTFOUND == retVal) + { + memset(&l2Table, 0, sizeof(rtl8373_luttb)); + l2Table.sip = pIpMcastAddr->sip; + l2Table.dip = pIpMcastAddr->dip; + l2Table.mbr = pmask; + l2Table.igmp_asic = pIpMcastAddr->igmp_asic; + l2Table.igmp_idx = pIpMcastAddr->igmp_index; + l2Table.l3lookup = 1; + if ((retVal = _rtl8373_setL2LookupTb(&l2Table)) != RT_ERR_OK) + return retVal; + + pIpMcastAddr->address = l2Table.address; + + method = RTL8373_LUTREADMETHOD_MAC; + retVal = _rtl8373_getL2LookupTb(method, &l2Table); + if (RT_ERR_L2_ENTRY_NOTFOUND == retVal) + return RT_ERR_L2_INDEXTBL_FULL; + else + return retVal; + + } + else + return retVal; + +} + + +/* Function Name: + * dal_rtl8373_l2_ipMcastAddr_get + * Description: + * Get LUT IP multicast entry. + * Input: + * pIpMcastAddr - IP Multicast entry + * Output: + * pIpMcastAddr - IP Multicast entry + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get Lut table of IP multicast entry. + */ +rtk_api_ret_t dal_rtl8373_l2_ipMcastAddr_get(rtk_l2_ipMcastAddr_t *pIpMcastAddr) +{ + rtk_api_ret_t retVal; + rtk_uint32 method; + rtl8373_luttb l2Table; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pIpMcastAddr) + return RT_ERR_NULL_POINTER; + + if( (pIpMcastAddr->dip & 0xF0000000) != 0xE0000000) + return RT_ERR_INPUT; + + memset(&l2Table, 0x00, sizeof(rtl8373_luttb)); + l2Table.sip = pIpMcastAddr->sip; + l2Table.dip = pIpMcastAddr->dip; + l2Table.l3lookup = 1; + method = RTL8373_LUTREADMETHOD_MAC; + if ((retVal = _rtl8373_getL2LookupTb(method, &l2Table)) != RT_ERR_OK) + return retVal; + + /* Get Logical port mask */ + if ((retVal = rtk_switch_portmask_P2L_get(l2Table.mbr, &pIpMcastAddr->portmask)) != RT_ERR_OK) + return retVal; + + pIpMcastAddr->address = l2Table.address; + pIpMcastAddr->igmp_asic = l2Table.igmp_asic; + pIpMcastAddr->igmp_index = l2Table.igmp_idx; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_l2_ipMcastAddr_next_get + * Description: + * Get Next IP Multicast entry. + * Input: + * pAddress - The Address ID + * Output: + * pIpMcastAddr - IP Multicast entry + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * Get the next IP multicast entry after the current entry pointed by pAddress. + * The address of next entry is returned by pAddress. User can use (address + 1) + * as pAddress to call this API again for dumping all IP multicast entries is LUT. + */ +rtk_api_ret_t dal_rtl8373_l2_ipMcastAddr_next_get(rtk_uint32 *pAddress, rtk_l2_ipMcastAddr_t *pIpMcastAddr) +{ + rtk_api_ret_t retVal; + rtl8373_luttb l2Table; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Error Checking */ + if ((pAddress == NULL) || (pIpMcastAddr == NULL) ) + return RT_ERR_INPUT; + + if(*pAddress > RTK_MAX_LUT_ADDR_ID ) + return RT_ERR_L2_L2UNI_PARAM; + + memset(pIpMcastAddr, 0, sizeof(rtk_l2_ipMcastAddr_t)); + memset(&l2Table, 0, sizeof(rtl8373_luttb)); + l2Table.address = *pAddress; + + if ((retVal = _rtl8373_getL2LookupTb(RTL8373_LUTREADMETHOD_NEXT_L3MC, &l2Table)) != RT_ERR_OK) + return retVal; + + if(l2Table.address < *pAddress) + return RT_ERR_L2_ENTRY_NOTFOUND; + + pIpMcastAddr->sip = l2Table.sip; + pIpMcastAddr->dip = l2Table.dip; + + /* Get Logical port mask */ + if ((retVal = rtk_switch_portmask_P2L_get(l2Table.mbr, &pIpMcastAddr->portmask)) != RT_ERR_OK) + return retVal; + + pIpMcastAddr->address = l2Table.address; + pIpMcastAddr->igmp_asic = l2Table.igmp_asic; + pIpMcastAddr->igmp_index = l2Table.igmp_idx; + *pAddress = l2Table.address; + + return RT_ERR_OK; +} + + + +/* Function Name: + * dal_rtl8373_l2_ipMcastAddr_del + * Description: + * Delete a ip multicast address entry from the specified device. + * Input: + * pIpMcastAddr - IP Multicast entry + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can delete a IP multicast address entry from the specified device. + */ +rtk_api_ret_t dal_rtl8373_l2_ipMcastAddr_del(rtk_l2_ipMcastAddr_t *pIpMcastAddr) +{ + rtk_api_ret_t retVal; + rtk_uint32 method; + rtl8373_luttb l2Table; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Error Checking */ + if (pIpMcastAddr == NULL) + return RT_ERR_INPUT; + + if( (pIpMcastAddr->dip & 0xF0000000) != 0xE0000000) + return RT_ERR_INPUT; + + memset(&l2Table, 0x00, sizeof(rtl8373_luttb)); + l2Table.sip = pIpMcastAddr->sip; + l2Table.dip = pIpMcastAddr->dip; + l2Table.l3lookup = 1; + method = RTL8373_LUTREADMETHOD_MAC; + retVal = _rtl8373_getL2LookupTb(method, &l2Table); + if (RT_ERR_OK == retVal) + { +#if 0 + l2Table.sip = pIpMcastAddr->sip; + l2Table.dip = pIpMcastAddr->dip; + l2Table.mbr = 0; + l2Table.igmp_asic = 0; + l2Table.igmp_idx= 0; + l2Table.l3lookup = 0; + if((retVal = _rtl8373_setL2LookupTb(&l2Table)) != RT_ERR_OK) + return retVal; + + pIpMcastAddr->address = l2Table.address; + return RT_ERR_OK; +#endif + pIpMcastAddr->address = l2Table.address; + return _rtl8373_clearL2LookupTb(l2Table.address); + + } + else + return retVal; +} + + + +/* Function Name: + * dal_rtl8373_l2_ucastAddr_flush + * Description: + * Flush L2 mac address by type in the specified device (both dynamic and static). + * Input: + * pConfig - flush configuration + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * flushByVid - 1: Flush by VID, 0: Don't flush by VID + * vid - VID (0 ~ 4095) + * flushByFid - 1: Flush by FID, 0: Don't flush by FID + * fid - FID (0 ~ 15) + * flushByPort - 1: Flush by Port, 0: Don't flush by Port + * port - Port ID + * flushByMac - Not Supported + * ucastAddr - Not Supported + * flushStaticAddr - 1: Flush both Static and Dynamic entries, 0: Flush only Dynamic entries + * flushAddrOnAllPorts - 1: Flush VID-matched entries at all ports, 0: Flush VID-matched entries per port. + */ +rtk_api_ret_t dal_rtl8373_l2_ucastAddr_flush(rtk_l2_flushCfg_t *pConfig) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData, i; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(pConfig == NULL) + return RT_ERR_NULL_POINTER; + + if(pConfig->flushByVid >= RTK_ENABLE_END) + return RT_ERR_ENABLE; + + if(pConfig->flushByFid >= RTK_ENABLE_END) + return RT_ERR_ENABLE; + + if(pConfig->flushByPort >= RTK_ENABLE_END) + return RT_ERR_ENABLE; + + if(pConfig->flushStaticAddr >= RTK_ENABLE_END) + return RT_ERR_ENABLE; + + if(pConfig->vid > RTL8373_VIDMAX) + return RT_ERR_VLAN_VID; + + if(pConfig->fid > RTL8373_FIDMAX) + return RT_ERR_INPUT; + + + + + if(pConfig->flushByVid == ENABLED) + { + if ((retVal = rtl8373_setAsicRegBits(RTL8373_L2_TBL_FLUSH_MODE_ADDR, RTL8373_L2_TBL_FLUSH_MODE_FLUSH_MODE_MASK, FLUSHMDOE_VID)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_L2_TBL_FLUSH_XID_ADDR, RTL8373_L2_TBL_FLUSH_XID_FLUSH_VID_MASK, pConfig->vid)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_L2_TBL_FLUSH_CMD_ADDR, RTL8373_L2_TBL_FLUSH_CMD_FLUSH_PMSK_MASK, pConfig->portmask)) != RT_ERR_OK) + return retVal; + + } + else if(pConfig->flushByFid == ENABLED) + { + if ((retVal = rtl8373_setAsicRegBits(RTL8373_L2_TBL_FLUSH_MODE_ADDR, RTL8373_L2_TBL_FLUSH_MODE_FLUSH_MODE_MASK, FLUSHMDOE_FID)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_L2_TBL_FLUSH_XID_ADDR, RTL8373_L2_TBL_FLUSH_XID_FLUSH_FID_MASK, pConfig->fid)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_L2_TBL_FLUSH_CMD_ADDR, RTL8373_L2_TBL_FLUSH_CMD_FLUSH_PMSK_MASK, pConfig->portmask)) != RT_ERR_OK) + return retVal; + + } + else if(pConfig->flushByPort == ENABLED) + { + if ((retVal = rtl8373_setAsicRegBits(RTL8373_L2_TBL_FLUSH_MODE_ADDR, RTL8373_L2_TBL_FLUSH_MODE_FLUSH_MODE_MASK,FLUSHMDOE_PORT))!= RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_L2_TBL_FLUSH_CMD_ADDR, RTL8373_L2_TBL_FLUSH_CMD_FLUSH_PMSK_MASK, pConfig->portmask)) != RT_ERR_OK) + return retVal; + } + + + if(pConfig->flushStaticAddr) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_L2_TBL_FLUSH_MODE_ADDR, RTL8373_L2_TBL_FLUSH_MODE_FLUSH_TYPE_OFFSET,1)) != RT_ERR_OK) + return retVal; + } + else + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_L2_TBL_FLUSH_MODE_ADDR, RTL8373_L2_TBL_FLUSH_MODE_FLUSH_TYPE_OFFSET,0)) != RT_ERR_OK) + return retVal; + } + + + retVal = rtl8373_getAsicRegBit(RTL8373_L2_TBL_FLUSH_CMD_ADDR, RTL8373_L2_TBL_FLUSH_CMD_FLUSH_BUSY_OFFSET, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + if(regData & 1) + { + return RT_ERR_BUSYWAIT_TIMEOUT; + } + + retVal = rtl8373_setAsicRegBit(RTL8373_L2_TBL_FLUSH_CMD_ADDR, RTL8373_L2_TBL_FLUSH_CMD_FLUSH_ACT_OFFSET, 1); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8373_getAsicRegBit(RTL8373_L2_TBL_FLUSH_CMD_ADDR, RTL8373_L2_TBL_FLUSH_CMD_FLUSH_BUSY_OFFSET, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + i = 0; + while(regData & 1) + { + retVal = rtl8373_getAsicRegBit(RTL8373_L2_TBL_FLUSH_CMD_ADDR, RTL8373_L2_TBL_FLUSH_CMD_FLUSH_BUSY_OFFSET, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + i++; + + if(i > 0xfff) + { + return RT_ERR_BUSYWAIT_TIMEOUT; + } + } + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_l2_table_clear + * Description: + * Flush all static & dynamic entries in LUT. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * + */ +rtk_api_ret_t dal_rtl8373_l2_table_clear(void) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if ((retVal = rtl8373_setAsicRegBit(RTL8373_L2_TBL_FLUSH_ALL_ADDR, RTL8373_L2_TBL_FLUSH_ALL_FLUSH_ALL_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + + +/* Function Name: + * dal_rtl8373_l2_table_clearStatus_get + * Description: + * Get table clear status + * Input: + * None + * Output: + * pStatus - Clear status, 1:Busy, 0:finish + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * + */ +rtk_api_ret_t dal_rtl8373_l2_table_clearStatus_get(rtk_l2_clearStatus_t *pStatus) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pStatus) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8373_getAsicRegBit(RTL8373_L2_TBL_FLUSH_ALL_ADDR, RTL8373_L2_TBL_FLUSH_ALL_FLUSH_ALL_OFFSET, (rtk_uint32 *)pStatus)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_l2_flushLinkDownPortAddrEnable_set + * Description: + * Set HW flush linkdown port mac configuration of the specified device. + * Input: + * enable - link down flush status + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * The status of flush linkdown port address is as following: + * - DISABLED + * - ENABLED + */ +rtk_api_ret_t dal_rtl8373_l2_flushLinkDownPortAddrEnable_set(rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + + if (enable >= RTK_ENABLE_END) + return RT_ERR_ENABLE; + + if ((retVal = rtl8373_setAsicRegBit(RTL8373_L2_CTRL_ADDR, RTL8373_L2_CTRL_LINKDOWN_AGEOUT_OFFSET, enable ? 0 : 1)) != RT_ERR_OK) + return retVal; + + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_l2_flushLinkDownPortAddrEnable_get + * Description: + * Get HW flush linkdown port mac configuration of the specified device. + * Input: + * Output: + * pEnable - link down flush status + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The status of flush linkdown port address is as following: + * - DISABLED + * - ENABLED + */ +rtk_api_ret_t dal_rtl8373_l2_flushLinkDownPortAddrEnable_get(rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + rtk_uint32 value; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pEnable) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8373_getAsicRegBit(RTL8373_L2_CTRL_ADDR, RTL8373_L2_CTRL_LINKDOWN_AGEOUT_OFFSET, &value)) != RT_ERR_OK) + return retVal; + + *pEnable = value ? 0 : 1; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_l2_agingEnable_set + * Description: + * Set L2 LUT aging status per port setting. + * Input: + * port - Port id. + * enable - Aging status + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * This API can be used to set L2 LUT aging status per port. + */ +rtk_api_ret_t dal_rtl8373_l2_agingEnable_set(rtk_port_t port, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* check port valid */ + RTK_CHK_PORT_VALID(port); + + if (enable >= RTK_ENABLE_END) + return RT_ERR_ENABLE; + + if(enable == 1) + enable = 0; + else + enable = 1; + + if ((retVal = rtl8373_setAsicRegBit(RTL8373_L2_PORT_AGE_CTRL_ADDR(port), RTL8373_L2_PORT_AGE_CTRL_DIS_AGE_OFFSET(port), enable)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + + + +/* Function Name: + * dal_rtl8373_l2_agingEnable_get + * Description: + * Get L2 LUT aging status per port setting. + * Input: + * port - Port id. + * Output: + * pEnable - Aging status + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can be used to get L2 LUT aging function per port. + */ +rtk_api_ret_t dal_rtl8373_l2_agingEnable_get(rtk_port_t port, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* check port valid */ + RTK_CHK_PORT_VALID(port); + + if(NULL == pEnable) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8373_getAsicRegBit(RTL8373_L2_PORT_AGE_CTRL_ADDR(port), RTL8373_L2_PORT_AGE_CTRL_DIS_AGE_OFFSET(port), pEnable)) != RT_ERR_OK) + return retVal; + + if(*pEnable == 1) + *pEnable = 0; + else + *pEnable = 1; + + return RT_ERR_OK; +} + + + + +/* Function Name: + * dal_rtl8373_l2_ageout_timer_set + * Description: + * Set L2 LUT entry age out timer. + * Input: + * timer - the time of an lut entry ageout without update. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * This API can be used to set L2 LUT aging status per port. + */ +rtk_api_ret_t dal_rtl8373_l2_ageout_timer_set(rtk_uint32 timer) +{ + rtk_api_ret_t retVal; + rtk_uint32 age_uint; + + age_uint = timer * 5; + + if((retVal = rtl8373_setAsicRegBits(RTL8373_L2_AGE_CTRL_ADDR, RTL8373_L2_AGE_CTRL_AGE_UNIT_MASK, age_uint))!= RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_l2_ageout_timer_get + * Description: + * Get L2 LUT entry age out timer. + * Input: + * pTimer - the time of an lut entry ageout without update. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * This API can be used to set L2 LUT aging status per port. + */ +rtk_api_ret_t dal_rtl8373_l2_ageout_timer_get(rtk_uint32 *pTimer) +{ + rtk_api_ret_t retVal; + rtk_uint32 age_uint; + + + if((retVal = rtl8373_getAsicRegBits(RTL8373_L2_AGE_CTRL_ADDR, RTL8373_L2_AGE_CTRL_AGE_UNIT_MASK, &age_uint))!= RT_ERR_OK) + return retVal; + + *pTimer = age_uint/5; + + return RT_ERR_OK; + + +} + + + +/* Function Name: + * dal_rtl8373_l2_ageout_timer_set + * Description: + * Set L2 LUT entry age field value when address learned in lut table. + * Input: + * timer - the time of an lut entry ageout without update. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * This API can be used to set L2 LUT aging status per port. + */ +rtk_api_ret_t dal_rtl8373_l2_agefield_value_set(rtk_uint32 value) +{ + rtk_api_ret_t retVal; + + + if((retVal = rtl8373_setAsicRegBits(RTL8373_L2_CTRL_ADDR, RTL8373_L2_CTRL_AGE_TIMER_MASK, value))!= RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_l2_agefield_value_get + * Description: + * Get L2 LUT entry age field value when address learned in lut table. + * Input: + * pTimer - the time of an lut entry ageout without update. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * This API can be used to set L2 LUT aging status per port. + */ +rtk_api_ret_t dal_rtl8373_l2_agefield_value_get(rtk_uint32 *pValue) +{ + rtk_api_ret_t retVal; + + if((retVal = rtl8373_getAsicRegBits(RTL8373_L2_CTRL_ADDR, RTL8373_L2_CTRL_AGE_TIMER_MASK, pValue))!= RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + + +/* Function Name: + * dal_rtl8373_l2_limitLearningCnt_set + * Description: + * Set per-Port auto learning limit number + * Input: + * port - Port id. + * mac_cnt - Auto learning entries limit number + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_LIMITED_L2ENTRY_NUM - Invalid auto learning limit number + * Note: + * The API can set per-port ASIC auto learning limit number from 0(disable learning) + * to 2112. + */ +rtk_api_ret_t dal_rtl8373_l2_limitLearningCnt_set(rtk_port_t port, rtk_mac_cnt_t mac_cnt) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* check port valid */ + RTK_CHK_PORT_VALID(port); + + if (mac_cnt > rtk_switch_maxLutAddrNumber_get()) + return RT_ERR_LIMITED_L2ENTRY_NUM; + + if ((retVal = rtl8373_setAsicReg(RTL8373_L2_LRN_PORT_CONSTRT_CTRL_ADDR(port), mac_cnt)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_l2_limitLearningCnt_get + * Description: + * Get per-Port auto learning limit number + * Input: + * port - Port id. + * Output: + * pMac_cnt - Auto learning entries limit number + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get per-port ASIC auto learning limit number. + */ +rtk_api_ret_t dal_rtl8373_l2_limitLearningCnt_get(rtk_port_t port, rtk_mac_cnt_t *pMac_cnt) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* check port valid */ + RTK_CHK_PORT_VALID(port); + + if(NULL == pMac_cnt) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8373_getAsicReg(RTL8373_L2_LRN_PORT_CONSTRT_CTRL_ADDR(port), pMac_cnt)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_l2_limitSystemLearningCnt_set + * Description: + * Set System auto learning limit number + * Input: + * mac_cnt - Auto learning entries limit number + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_LIMITED_L2ENTRY_NUM - Invalid auto learning limit number + * Note: + * The API can set system ASIC auto learning limit number from 0(disable learning) + * to 2112. + */ +rtk_api_ret_t dal_rtl8373_l2_limitSystemLearningCnt_set(rtk_mac_cnt_t mac_cnt) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (mac_cnt > (rtk_switch_maxLutAddrNumber_get() + 64)) + return RT_ERR_LIMITED_L2ENTRY_NUM; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_L2_LRN_CONSTRT_CTRL_ADDR, RTL8373_L2_LRN_CONSTRT_CTRL_CONSTRT_NUM_MASK, mac_cnt)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_l2_limitSystemLearningCnt_get + * Description: + * Get System auto learning limit number + * Input: + * None + * Output: + * pMac_cnt - Auto learning entries limit number + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get system ASIC auto learning limit number. + */ +rtk_api_ret_t dal_rtl8373_l2_limitSystemLearningCnt_get(rtk_mac_cnt_t *pMac_cnt) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pMac_cnt) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8373_getAsicRegBits(RTL8373_L2_LRN_CONSTRT_CTRL_ADDR, RTL8373_L2_LRN_CONSTRT_CTRL_CONSTRT_NUM_MASK, pMac_cnt)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_l2_limitLearningCntAction_set + * Description: + * Configure auto learn over limit number action. + * Input: + * port - Port id. + * action - Auto learning entries limit number + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_NOT_ALLOWED - Invalid learn over action + * Note: + * The API can set SA unknown packet action while auto learn limit number is over + * The action symbol as following: + * - LIMIT_LEARN_CNT_ACTION_DROP, + * - LIMIT_LEARN_CNT_ACTION_FORWARD, + * - LIMIT_LEARN_CNT_ACTION_TO_CPU, + */ +rtk_api_ret_t dal_rtl8373_l2_limitLearningCntAction_set(rtk_port_t port, rtk_l2_limitLearnCntAction_t action) +{ + rtk_api_ret_t retVal; + rtk_uint32 data; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(port > RTL8373_PORTIDMAX) + return RT_ERR_INPUT; + + + if ( LIMIT_LEARN_CNT_ACTION_DROP == action ) + data = 1; + else if ( LIMIT_LEARN_CNT_ACTION_FORWARD == action ) + data = 0; + else if ( LIMIT_LEARN_CNT_ACTION_TO_CPU == action ) + data = 2; + else + return RT_ERR_NOT_ALLOWED; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_L2_LRN_PORT_CONSTRT_ACT_ADDR, RTL8373_L2_LRN_PORT_CONSTRT_ACT_LRN_ACT_MASK, data)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_l2_limitLearningCntAction_get + * Description: + * Get auto learn over limit number action. + * Input: + * port - Port id. + * Output: + * pAction - Learn over action + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get SA unknown packet action while auto learn limit number is over + * The action symbol as following: + * - LIMIT_LEARN_CNT_ACTION_DROP, + * - LIMIT_LEARN_CNT_ACTION_FORWARD, + * - LIMIT_LEARN_CNT_ACTION_TO_CPU, + */ +rtk_api_ret_t dal_rtl8373_l2_limitLearningCntAction_get(rtk_port_t port, rtk_l2_limitLearnCntAction_t *pAction) +{ + rtk_api_ret_t retVal; + rtk_uint32 action; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(port > RTL8373_PORTIDMAX) + return RT_ERR_INPUT; + + if(NULL == pAction) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8373_getAsicRegBits(RTL8373_L2_LRN_PORT_CONSTRT_ACT_ADDR, RTL8373_L2_LRN_PORT_CONSTRT_ACT_LRN_ACT_MASK, &action)) != RT_ERR_OK) + return retVal; + + if ( 1 == action ) + *pAction = LIMIT_LEARN_CNT_ACTION_DROP; + else if ( 0 == action ) + *pAction = LIMIT_LEARN_CNT_ACTION_FORWARD; + else if ( 2 == action ) + *pAction = LIMIT_LEARN_CNT_ACTION_TO_CPU; + else + *pAction = action; + + return RT_ERR_OK; +} + + + +/* Function Name: + * dal_rtl8373_l2_limitSystemLearningCntAction_set + * Description: + * Configure system auto learn over limit number action. + * Input: + * port - Port id. + * action - Auto learning entries limit number + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_NOT_ALLOWED - Invalid learn over action + * Note: + * The API can set SA unknown packet action while auto learn limit number is over + * The action symbol as following: + * - LIMIT_LEARN_CNT_ACTION_DROP, + * - LIMIT_LEARN_CNT_ACTION_FORWARD, + * - LIMIT_LEARN_CNT_ACTION_TO_CPU, + */ +rtk_api_ret_t dal_rtl8373_l2_limitSystemLearningCntAction_set(rtk_l2_limitLearnCntAction_t action) +{ + rtk_api_ret_t retVal; + rtk_uint32 data; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if ( LIMIT_LEARN_CNT_ACTION_DROP == action ) + data = 1; + else if ( LIMIT_LEARN_CNT_ACTION_FORWARD == action ) + data = 0; + else if ( LIMIT_LEARN_CNT_ACTION_TO_CPU == action ) + data = 2; + else + return RT_ERR_NOT_ALLOWED; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_L2_LRN_CONSTRT_ACT_ADDR, RTL8373_L2_LRN_CONSTRT_ACT_LRN_ACT_MASK, data)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_l2_limitSystemLearningCntAction_get + * Description: + * Get system auto learn over limit number action. + * Input: + * None. + * Output: + * pAction - Learn over action + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get SA unknown packet action while auto learn limit number is over + * The action symbol as following: + * - LIMIT_LEARN_CNT_ACTION_DROP, + * - LIMIT_LEARN_CNT_ACTION_FORWARD, + * - LIMIT_LEARN_CNT_ACTION_TO_CPU, + */ +rtk_api_ret_t dal_rtl8373_l2_limitSystemLearningCntAction_get(rtk_l2_limitLearnCntAction_t *pAction) +{ + rtk_api_ret_t retVal; + rtk_uint32 action; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pAction) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8373_getAsicRegBits(RTL8373_L2_LRN_CONSTRT_ACT_ADDR, RTL8373_L2_LRN_CONSTRT_ACT_LRN_ACT_MASK, &action)) != RT_ERR_OK) + return retVal; + + if ( 1 == action ) + *pAction = LIMIT_LEARN_CNT_ACTION_DROP; + else if ( 0 == action ) + *pAction = LIMIT_LEARN_CNT_ACTION_FORWARD; + else if ( 2 == action ) + *pAction = LIMIT_LEARN_CNT_ACTION_TO_CPU; + else + *pAction = action; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_l2_limitSystemLearningCntPortMask_set + * Description: + * Configure system auto learn portmask + * Input: + * pPortmask - Port Mask + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Invalid port mask. + * Note: + * + */ +rtk_api_ret_t dal_rtl8373_l2_limitSystemLearningCntPortMask_set(rtk_portmask_t *pPortmask) +{ + rtk_api_ret_t retVal; + rtk_uint32 pmask; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pPortmask) + return RT_ERR_NULL_POINTER; + + /* Check port mask */ + RTK_CHK_PORTMASK_VALID(pPortmask); + + if ((retVal = rtk_switch_portmask_L2P_get(pPortmask, &pmask)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_L2_LRN_CONSTRT_CTRL_ADDR, RTL8373_L2_LRN_CONSTRT_CTRL_PORT_MASK_MASK, pmask & 0x3ff)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_l2_limitSystemLearningCntPortMask_get + * Description: + * get system auto learn portmask + * Input: + * None + * Output: + * pPortmask - Port Mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Null pointer. + * Note: + * + */ +rtk_api_ret_t dal_rtl8373_l2_limitSystemLearningCntPortMask_get(rtk_portmask_t *pPortmask) +{ + rtk_api_ret_t retVal; + rtk_uint32 pmask; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pPortmask) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8373_getAsicRegBits(RTL8373_L2_LRN_CONSTRT_CTRL_ADDR, RTL8373_L2_LRN_CONSTRT_CTRL_PORT_MASK_MASK, &pmask)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtk_switch_portmask_P2L_get(pmask, pPortmask)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8367d_l2_learningCnt_get + * Description: + * Get per-Port current auto learning number + * Input: + * port - Port id. + * Output: + * pMac_cnt - ASIC auto learning entries number + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get per-port ASIC auto learning number + */ +rtk_api_ret_t dal_rtl8373_l2_learningCnt_get(rtk_port_t port, rtk_mac_cnt_t *pMac_cnt) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* check port valid */ + RTK_CHK_PORT_VALID(port); + + if(NULL == pMac_cnt) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8373_getAsicReg(RTL8373_L2_LRN_PORT_CONSTRT_CNT_ADDR(port), pMac_cnt)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_l2_ipMcastAddrLookup_set + * Description: + * Set Lut IP multicast lookup function + * Input: + * type - Lookup type for IPMC packet. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * LOOKUP_MAC - Lookup by MAC address + * LOOKUP_IP - Lookup by IP address + */ +rtk_api_ret_t dal_rtl8373_l2_ipMcastAddrLookup_set(rtk_l2_ipmc_lookup_type_t type) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(type == LOOKUP_MAC) + { + if((retVal = rtl8373_setAsicRegBit(RTL8373_L2_CTRL_ADDR, RTL8373_L2_CTRL_LUT_IPMC_HASH_OFFSET, DISABLED)) != RT_ERR_OK) + return retVal; + } + else if(type == LOOKUP_IP) + { + if((retVal = rtl8373_setAsicRegBit(RTL8373_L2_CTRL_ADDR, RTL8373_L2_CTRL_LUT_IPMC_HASH_OFFSET, ENABLED)) != RT_ERR_OK) + return retVal; + } + else + return RT_ERR_INPUT; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_l2_ipMcastAddrLookup_get + * Description: + * Get Lut IP multicast lookup function + * Input: + * None. + * Output: + * pType - Lookup type for IPMC packet. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * None. + */ +rtk_api_ret_t dal_rtl8373_l2_ipMcastAddrLookup_get(rtk_l2_ipmc_lookup_type_t *pType) +{ + rtk_api_ret_t retVal; + rtk_uint32 enabled; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pType) + return RT_ERR_NULL_POINTER; + + if((retVal = rtl8373_getAsicRegBit(RTL8373_L2_CTRL_ADDR, RTL8373_L2_CTRL_LUT_IPMC_HASH_OFFSET, &enabled)) != RT_ERR_OK) + return retVal; + + if(enabled == ENABLED) + *pType = LOOKUP_IP; + else + *pType = LOOKUP_MAC; + + return RT_ERR_OK; +} + + + +/* Function Name: + * dal_rtl8373_l2_ipMcastGroupEntry_add + * Description: + * Add an IP Multicast entry to group table + * Input: + * ip_addr - IP address + * vid - VLAN ID + * pPortmask - portmask + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_TBL_FULL - Table Full + * Note: + * Add an entry to IP Multicast Group table. + */ +rtk_api_ret_t dal_rtl8373_l2_ipMcastGroupEntry_add(ipaddr_t ip_addr, rtk_portmask_t * portmask) +{ + rtk_uint32 empty_idx = 0xFFFF; + rtk_int32 index; + ipaddr_t group_addr; + rtk_uint32 pmask; + rtk_uint32 valid; + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + + if((ip_addr & 0xF0000000) != 0xE0000000) + return RT_ERR_INPUT; + + + for(index = 0; index <= RTL8373_LUT_IPMCGRP_TABLE_MAX; index++) + { + if ((retVal = _rtl8373_getLutIPMCGroup((rtk_uint32)index, &group_addr, &pmask, &valid))!=RT_ERR_OK) + return retVal; + + if( (valid == ENABLED) && (group_addr == ip_addr)) + { + if(pmask != portmask->bits[0]) + { + pmask = portmask->bits[0]; + if ((retVal = _rtl8373_setLutIPMCGroup(index, ip_addr, pmask, valid))!=RT_ERR_OK) + return retVal; + } + + return RT_ERR_OK; + } + + if( (valid == DISABLED) && (empty_idx == 0xFFFF) ) /* Unused */ + empty_idx = (rtk_uint32)index; + } + + if(empty_idx == 0xFFFF) + return RT_ERR_TBL_FULL; + + pmask = portmask->bits[0]; + if ((retVal = _rtl8373_setLutIPMCGroup(empty_idx, ip_addr, pmask, ENABLED))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_l2_ipMcastGroupEntry_del + * Description: + * Delete an entry from IP Multicast group table + * Input: + * ip_addr - IP address + * vid - VLAN ID + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_TBL_FULL - Table Full + * Note: + * Delete an entry from IP Multicast group table. + */ +rtk_api_ret_t dal_rtl8373_l2_ipMcastGroupEntry_del(ipaddr_t ip_addr) +{ + rtk_int32 index; + ipaddr_t group_addr; + rtk_uint32 pmask; + rtk_uint32 valid; + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + + if((ip_addr & 0xF0000000) != 0xE0000000) + return RT_ERR_INPUT; + + for(index = 0; index <= RTL8373_LUT_IPMCGRP_TABLE_MAX; index++) + { + if ((retVal = _rtl8373_getLutIPMCGroup((rtk_uint32)index, &group_addr, &pmask, &valid))!=RT_ERR_OK) + return retVal; + + if( (valid == ENABLED) && (group_addr == ip_addr) ) + { + group_addr = 0xE0000000; + pmask = 0; + if ((retVal = _rtl8373_setLutIPMCGroup(index, group_addr, pmask, DISABLED))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; + } + } + + return RT_ERR_FAILED; +} + + +/* Function Name: + * dal_rtl8373_l2_ipMcastGroupEntry_get + * Description: + * get an entry from IP Multicast group table + * Input: + * ip_addr - IP address + * vid - VLAN ID + * Output: + * pPortmask - member port mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_TBL_FULL - Table Full + * Note: + * Delete an entry from IP Multicast group table. + */ +rtk_api_ret_t dal_rtl8373_l2_ipMcastGroupEntry_get(ipaddr_t ip_addr, rtk_portmask_t *pPortmask) +{ + rtk_int32 index; + ipaddr_t group_addr; + rtk_uint32 valid; + rtk_uint32 pmask; + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + + if((ip_addr & 0xF0000000) != 0xE0000000) + return RT_ERR_INPUT; + + if(NULL == pPortmask) + return RT_ERR_NULL_POINTER; + + for(index = 0; index <= RTL8373_LUT_IPMCGRP_TABLE_MAX; index++) + { + if ((retVal = _rtl8373_getLutIPMCGroup((rtk_uint32)index, &group_addr, &pmask, &valid))!=RT_ERR_OK) + return retVal; + + if( (valid == ENABLED) && (group_addr == ip_addr) ) + { + pPortmask->bits[0]= pmask; + + return RT_ERR_OK; + } + } + + return RT_ERR_FAILED; +} + + +/* Function Name: + * dal_rtl8373_l2_entry_get + * Description: + * Get LUT entry. + * Input: + * pL2_entry - Index field in the structure. + * Output: + * pL2_entry - other fields such as MAC, port, age... + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_EMPTY_ENTRY - Empty LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API is used to get address by index from 0~2111. + */ +rtk_api_ret_t dal_rtl8373_l2_entry_get(rtk_l2_addr_table_t *pL2_entry) +{ + rtk_api_ret_t retVal; + rtk_uint32 method; + rtl8373_luttb l2Table; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (pL2_entry->index >= rtk_switch_maxLutAddrNumber_get()) + return RT_ERR_INPUT; + + memset(&l2Table, 0x00, sizeof(rtl8373_luttb)); + l2Table.address= pL2_entry->index; + method = RTL8373_LUTREADMETHOD_ADDRESS; + if ((retVal = _rtl8373_getL2LookupTb(method, &l2Table)) != RT_ERR_OK) + return retVal; + + + if ((pL2_entry->index>4160)&&(l2Table.lookup_hit==0)) + return RT_ERR_L2_EMPTY_ENTRY; + + if(l2Table.l3lookup) + { + memset(&pL2_entry->mac, 0, sizeof(rtk_mac_t)); + pL2_entry->is_ipmul = l2Table.l3lookup; + pL2_entry->sip = l2Table.sip; + pL2_entry->dip = l2Table.dip; + pL2_entry->igmp_asic = l2Table.igmp_asic; + pL2_entry->igmp_idx = l2Table.igmp_idx; + + /* Get Logical port mask */ + if ((retVal = rtk_switch_portmask_P2L_get(l2Table.mbr, &(pL2_entry->portmask)))!=RT_ERR_OK) + return retVal; + + pL2_entry->vid_fid = 0; + pL2_entry->age = 0; + } + else if(l2Table.mac.octet[0]&0x01) + { + memset(&pL2_entry->sip, 0, sizeof(ipaddr_t)); + memset(&pL2_entry->dip, 0, sizeof(ipaddr_t)); + pL2_entry->mac.octet[0] = l2Table.mac.octet[0]; + pL2_entry->mac.octet[1] = l2Table.mac.octet[1]; + pL2_entry->mac.octet[2] = l2Table.mac.octet[2]; + pL2_entry->mac.octet[3] = l2Table.mac.octet[3]; + pL2_entry->mac.octet[4] = l2Table.mac.octet[4]; + pL2_entry->mac.octet[5] = l2Table.mac.octet[5]; + pL2_entry->is_ipmul = l2Table.l3lookup; + pL2_entry->igmp_asic = l2Table.igmp_asic; + pL2_entry->igmp_idx = l2Table.igmp_idx; + + /* Get Logical port mask */ + if ((retVal = rtk_switch_portmask_P2L_get(l2Table.mbr, &(pL2_entry->portmask)))!=RT_ERR_OK) + return retVal; + + pL2_entry->ivl = l2Table.ivl_svl; + if(l2Table.ivl_svl == 1) /* IVL */ + { + pL2_entry->vid_fid= l2Table.cvid_fid; + } + else /* SVL*/ + { + pL2_entry->vid_fid = l2Table.cvid_fid; + } + pL2_entry->age = 0; + } + else if((l2Table.age != 0)||(l2Table.nosalearn == 1)||(l2Table.auth== 1)) + { + memset(&pL2_entry->sip, 0, sizeof(ipaddr_t)); + memset(&pL2_entry->dip, 0, sizeof(ipaddr_t)); + pL2_entry->mac.octet[0] = l2Table.mac.octet[0]; + pL2_entry->mac.octet[1] = l2Table.mac.octet[1]; + pL2_entry->mac.octet[2] = l2Table.mac.octet[2]; + pL2_entry->mac.octet[3] = l2Table.mac.octet[3]; + pL2_entry->mac.octet[4] = l2Table.mac.octet[4]; + pL2_entry->mac.octet[5] = l2Table.mac.octet[5]; + pL2_entry->is_ipmul = l2Table.l3lookup; + pL2_entry->is_static = l2Table.nosalearn; + + /* Get Logical port mask */ + if ((retVal = rtk_switch_portmask_P2L_get(1<<(l2Table.spa), &(pL2_entry->portmask)))!=RT_ERR_OK) + return retVal; + + pL2_entry->ivl = l2Table.ivl_svl; + pL2_entry->vid_fid = l2Table.cvid_fid; +#if 0 + if(l2Table.ivl_svl == 1) /* IVL */ + { + pL2_entry->cvid = l2Table.cvid_fid; + pL2_entry->fid = 0; + } + else /* SVL*/ + { + pL2_entry->cvid = 0; + pL2_entry->fid = l2Table.cvid_fid; + } +#endif + pL2_entry->age = l2Table.age; + pL2_entry->auth = l2Table.auth; + pL2_entry->srcport = l2Table.spa; + + } + else + return RT_ERR_L2_EMPTY_ENTRY; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_l2_entry_getNext + * Description: + * Get LUT entry. + * Input: + * pL2_entry - Index field in the structure. + * Output: + * pL2_entry - other fields such as MAC, port, age... + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_EMPTY_ENTRY - Empty LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API is used to get address by index from 0~2111. + */ +rtk_api_ret_t dal_rtl8373_l2_entry_getNext(rtk_l2_addr_table_t *pL2_entry, rtk_uint32 method) +{ + rtk_api_ret_t retVal; + rtl8373_luttb l2Table; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (pL2_entry->index >= rtk_switch_maxLutAddrNumber_get()) + return RT_ERR_INPUT; + + memset(&l2Table, 0x00, sizeof(rtl8373_luttb)); + l2Table.address= pL2_entry->index; + l2Table.spa = pL2_entry->srcport; + if ((retVal = _rtl8373_getL2LookupTb(method, &l2Table)) != RT_ERR_OK) + return retVal; + +#if 0 + if ((l2Table.address>4160)&&(l2Table.lookup_hit==0)) + return RT_ERR_L2_EMPTY_ENTRY; +#endif + if ((pL2_entry->index>4160)&&(l2Table.lookup_hit==0)) + return RT_ERR_L2_EMPTY_ENTRY; + + + pL2_entry->index = l2Table.address; + + if(l2Table.l3lookup) + { + memset(&pL2_entry->mac, 0, sizeof(rtk_mac_t)); + pL2_entry->is_ipmul = l2Table.l3lookup; + pL2_entry->sip = l2Table.sip; + pL2_entry->dip = l2Table.dip; + pL2_entry->igmp_asic = l2Table.igmp_asic; + pL2_entry->igmp_idx = l2Table.igmp_idx; + + /* Get Logical port mask */ + if ((retVal = rtk_switch_portmask_P2L_get(l2Table.mbr, &(pL2_entry->portmask)))!=RT_ERR_OK) + return retVal; + + pL2_entry->vid_fid = 0; + pL2_entry->age = 0; + + } + else if(l2Table.mac.octet[0]&0x01) + { + memset(&pL2_entry->sip, 0, sizeof(ipaddr_t)); + memset(&pL2_entry->dip, 0, sizeof(ipaddr_t)); + pL2_entry->mac.octet[0] = l2Table.mac.octet[0]; + pL2_entry->mac.octet[1] = l2Table.mac.octet[1]; + pL2_entry->mac.octet[2] = l2Table.mac.octet[2]; + pL2_entry->mac.octet[3] = l2Table.mac.octet[3]; + pL2_entry->mac.octet[4] = l2Table.mac.octet[4]; + pL2_entry->mac.octet[5] = l2Table.mac.octet[5]; + pL2_entry->is_ipmul = l2Table.l3lookup; + pL2_entry->igmp_asic = l2Table.igmp_asic; + pL2_entry->igmp_idx = l2Table.igmp_idx; + + /* Get Logical port mask */ + if ((retVal = rtk_switch_portmask_P2L_get(l2Table.mbr, &(pL2_entry->portmask)))!=RT_ERR_OK) + return retVal; + + pL2_entry->ivl = l2Table.ivl_svl; + if(l2Table.ivl_svl == 1) /* IVL */ + { + pL2_entry->vid_fid= l2Table.cvid_fid; + } + else /* SVL*/ + { + pL2_entry->vid_fid = l2Table.cvid_fid; + } + pL2_entry->age = 0; + } + else if((l2Table.age != 0)||(l2Table.nosalearn == 1)||(l2Table.auth== 1)) + { + memset(&pL2_entry->sip, 0, sizeof(ipaddr_t)); + memset(&pL2_entry->dip, 0, sizeof(ipaddr_t)); + pL2_entry->mac.octet[0] = l2Table.mac.octet[0]; + pL2_entry->mac.octet[1] = l2Table.mac.octet[1]; + pL2_entry->mac.octet[2] = l2Table.mac.octet[2]; + pL2_entry->mac.octet[3] = l2Table.mac.octet[3]; + pL2_entry->mac.octet[4] = l2Table.mac.octet[4]; + pL2_entry->mac.octet[5] = l2Table.mac.octet[5]; + pL2_entry->is_ipmul = l2Table.l3lookup; + pL2_entry->is_static = l2Table.nosalearn; + + /* Get Logical port mask */ + if ((retVal = rtk_switch_portmask_P2L_get(1<<(l2Table.spa), &(pL2_entry->portmask)))!=RT_ERR_OK) + return retVal; + + pL2_entry->ivl = l2Table.ivl_svl; + pL2_entry->vid_fid = l2Table.cvid_fid; +#if 0 + if(l2Table.ivl_svl == 1) /* IVL */ + { + pL2_entry->cvid = l2Table.cvid_fid; + pL2_entry->fid = 0; + } + else /* SVL*/ + { + pL2_entry->cvid = 0; + pL2_entry->fid = l2Table.cvid_fid; + } +#endif + pL2_entry->age = l2Table.age; + pL2_entry->auth = l2Table.auth; + pL2_entry->srcport = l2Table.spa; + + } + else + return RT_ERR_L2_EMPTY_ENTRY; + + return RT_ERR_OK; +} + + + +/* Function Name: + * dal_rtl8373_l2_entry_del + * Description: + * Del LUT entry. + * Input: + * pL2_entry - Index field in the structure. + * Output: + * pL2_entry - other fields such as MAC, port, age... + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_EMPTY_ENTRY - Empty LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API is used to get address by index from 0~4096. + */ +rtk_api_ret_t dal_rtl8373_l2_entry_del(rtk_l2_addr_table_t *pL2_entry) +{ + rtk_api_ret_t retVal; + rtk_uint32 method; + rtl8373_luttb l2Table; + rtk_l2_ipMcastAddr_t ipMul; + rtk_l2_mcastAddr_t l2Mul; + rtk_l2_ucastAddr_t l2Uni; + rtk_mac_t macAddr; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (pL2_entry->index >= rtk_switch_maxLutAddrNumber_get()) + return RT_ERR_INPUT; + + memset(&l2Table, 0x00, sizeof(rtl8373_luttb)); + l2Table.address= pL2_entry->index; + method = RTL8373_LUTREADMETHOD_ADDRESS; + if ((retVal = _rtl8373_getL2LookupTb(method, &l2Table)) != RT_ERR_OK) + return retVal; + + + if ((pL2_entry->index>4160)&&(l2Table.lookup_hit==0)) + return RT_ERR_L2_EMPTY_ENTRY; + + if(l2Table.l3lookup) + { + memset(&pL2_entry->mac, 0, sizeof(rtk_mac_t)); + pL2_entry->is_ipmul = l2Table.l3lookup; + pL2_entry->sip = l2Table.sip; + pL2_entry->dip = l2Table.dip; + pL2_entry->igmp_asic = l2Table.igmp_asic; + pL2_entry->igmp_idx = l2Table.igmp_idx; + + /* Get Logical port mask */ + if ((retVal = rtk_switch_portmask_P2L_get(l2Table.mbr, &(pL2_entry->portmask)))!=RT_ERR_OK) + return retVal; + + pL2_entry->vid_fid = 0; + pL2_entry->age = 0; + + memset(&ipMul, 0, sizeof(rtk_l2_ipMcastAddr_t)); + ipMul.dip = pL2_entry->dip; + ipMul.sip = pL2_entry->sip; +// retVal = dal_rtl8373_l2_ipMcastAddr_del(&ipMul); + +// return retVal; + + } + else if(l2Table.mac.octet[0]&0x01) + { + memset(&pL2_entry->sip, 0, sizeof(ipaddr_t)); + memset(&pL2_entry->dip, 0, sizeof(ipaddr_t)); + pL2_entry->mac.octet[0] = l2Table.mac.octet[0]; + pL2_entry->mac.octet[1] = l2Table.mac.octet[1]; + pL2_entry->mac.octet[2] = l2Table.mac.octet[2]; + pL2_entry->mac.octet[3] = l2Table.mac.octet[3]; + pL2_entry->mac.octet[4] = l2Table.mac.octet[4]; + pL2_entry->mac.octet[5] = l2Table.mac.octet[5]; + pL2_entry->is_ipmul = l2Table.l3lookup; + pL2_entry->igmp_asic = l2Table.igmp_asic; + pL2_entry->igmp_idx = l2Table.igmp_idx; + + /* Get Logical port mask */ + if ((retVal = rtk_switch_portmask_P2L_get(l2Table.mbr, &(pL2_entry->portmask)))!=RT_ERR_OK) + return retVal; + + pL2_entry->ivl = l2Table.ivl_svl; + if(l2Table.ivl_svl == 1) /* IVL */ + { + pL2_entry->vid_fid= l2Table.cvid_fid; + } + else /* SVL*/ + { + pL2_entry->vid_fid = l2Table.cvid_fid; + } + pL2_entry->age = 0; + + memset(&l2Mul, 0, sizeof(rtk_l2_mcastAddr_t)); + l2Mul.mac.octet[0] = l2Table.mac.octet[0]; + l2Mul.mac.octet[1] = l2Table.mac.octet[1]; + l2Mul.mac.octet[2] = l2Table.mac.octet[2]; + l2Mul.mac.octet[3] = l2Table.mac.octet[3]; + l2Mul.mac.octet[4] = l2Table.mac.octet[4]; + l2Mul.mac.octet[5] = l2Table.mac.octet[5]; + l2Mul.ivl = l2Table.ivl_svl; + l2Mul.vid_fid = l2Table.cvid_fid; +// retVal = dal_rtl8373_l2_mcastAddr_del(&l2Mul); + +// return retVal; + } + else if((l2Table.age != 0)||(l2Table.nosalearn == 1)||(l2Table.auth== 1)) + { + memset(&pL2_entry->sip, 0, sizeof(ipaddr_t)); + memset(&pL2_entry->dip, 0, sizeof(ipaddr_t)); + pL2_entry->mac.octet[0] = l2Table.mac.octet[0]; + pL2_entry->mac.octet[1] = l2Table.mac.octet[1]; + pL2_entry->mac.octet[2] = l2Table.mac.octet[2]; + pL2_entry->mac.octet[3] = l2Table.mac.octet[3]; + pL2_entry->mac.octet[4] = l2Table.mac.octet[4]; + pL2_entry->mac.octet[5] = l2Table.mac.octet[5]; + pL2_entry->is_ipmul = l2Table.l3lookup; + pL2_entry->is_static = l2Table.nosalearn; + + /* Get Logical port mask */ + if ((retVal = rtk_switch_portmask_P2L_get(1<<(l2Table.spa), &(pL2_entry->portmask)))!=RT_ERR_OK) + return retVal; + + pL2_entry->ivl = l2Table.ivl_svl; + pL2_entry->vid_fid = l2Table.cvid_fid; + pL2_entry->age = l2Table.age; + pL2_entry->auth = l2Table.auth; + pL2_entry->srcport = l2Table.spa; + + memset(&l2Uni, 0, sizeof(l2Uni)); + memset(&macAddr, 0, sizeof(macAddr)); + + macAddr.octet[0] = l2Table.mac.octet[0]; + macAddr.octet[1] = l2Table.mac.octet[1]; + macAddr.octet[2] = l2Table.mac.octet[2]; + macAddr.octet[3] = l2Table.mac.octet[3]; + macAddr.octet[4] = l2Table.mac.octet[4]; + macAddr.octet[5] = l2Table.mac.octet[5]; + + l2Uni.ivl = l2Table.ivl_svl; + l2Uni.vid_fid = l2Table.cvid_fid; + +// retVal = dal_rtl8373_l2_addr_del(&macAddr, &l2Uni); + +// return retVal; + + } + + return _rtl8373_clearL2LookupTb(pL2_entry->index); + +} + + + +/* Function Name: + * dal_rtl8373_l2_lookupHitIsolationAction_set + * Description: + * Set action of lookup hit & isolation. + * Input: + * action - The action + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API is used to configure the action of packet which is lookup hit + * in L2 table but the destination port/portmask are not in the port isolation + * group. + */ +rtk_api_ret_t dal_rtl8373_l2_lookupHitIsolationAction_set(rtk_l2_lookupHitIsolationAction_t action) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + switch (action) + { + case L2_LOOKUPHIT_ISOACTION_NOP: + regData = 0; + break; + case L2_LOOKUPHIT_ISOACTION_UNKNOWN: + regData = 1; + break; + default: + return RT_ERR_INPUT; + } + + if ((retVal = rtl8373_setAsicRegBit(RTL8373_L2_CTRL_ADDR, RTL8373_L2_CTRL_CFG_LOOKUP_HIT_ISO_ACT_OFFSET, regData)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + + + + +/* Function Name: + * dal_rtl8373_l2_lookupHitIsolationAction_get + * Description: + * Get action of lookup hit & isolation. + * Input: + * None. + * Output: + * pAction - The action + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API is used to get the action of packet which is lookup hit + * in L2 table but the destination port/portmask are not in the port isolation + * group. + */ +rtk_api_ret_t dal_rtl8373_l2_lookupHitIsolationAction_get(rtk_l2_lookupHitIsolationAction_t *pAction) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (pAction == NULL) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8373_getAsicRegBit(RTL8373_L2_CTRL_ADDR, RTL8373_L2_CTRL_CFG_LOOKUP_HIT_ISO_ACT_OFFSET, ®Data)) != RT_ERR_OK) + return retVal; + + switch (regData) + { + case 0: + *pAction = L2_LOOKUPHIT_ISOACTION_NOP; + break; + case 1: + *pAction = L2_LOOKUPHIT_ISOACTION_UNKNOWN; + break; + default: + return RT_ERR_FAILED; + } + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_l2_portNewSaBehavior_set + * Description: + * Set UNSA behavior + * Input: + * port - port 0~9 + * behavior - 0: flooding; 1: drop; 2:trap + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid behavior + * Note: + * None + */ +ret_t dal_rtl8373_l2_portNewSaBehavior_set(rtk_uint32 port, rtk_uint32 behavior) +{ + if(behavior >= L2_BEHAVE_SA_END) + return RT_ERR_NOT_ALLOWED; + + return rtl8373_setAsicRegBits(RTL8373_L2_NEWSA_CTRL_ADDR(port), RTL8373_L2_NEWSA_CTRL_NEW_SA_MASK(port), behavior); +} + + +/* Function Name: + * dal_rtl8373_l2_portNewSaBehavior_get + * Description: + * Get UNSA behavior + * Input: + * port - port 0~9 + * pBehavior - 0: flooding; 1: drop; 2:trap + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t dal_rtl8373_l2_portNewSaBehavior_get(rtk_uint32 port, rtk_uint32 *pBehavior) +{ + return rtl8373_getAsicRegBits(RTL8373_L2_NEWSA_CTRL_ADDR(port), RTL8373_L2_NEWSA_CTRL_NEW_SA_MASK(port), pBehavior); +} + + +/* Function Name: + * dal_rtl8373_l2_portUnmatchedSaBehavior_set + * Description: + * Set Unmatched SA behavior + * Input: + * port - port 0~9 + * behavior - 0: flooding; 1: drop; 2:trap + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid behavior + * Note: + * None + */ +ret_t dal_rtl8373_l2_portUnmatchedSaBehavior_set(rtk_uint32 port, rtk_uint32 behavior) +{ + if(behavior >= L2_BEHAVE_SA_END) + return RT_ERR_NOT_ALLOWED; + + return rtl8373_setAsicRegBits(RTL8373_L2_UNMATCH_SA_CTRL_ADDR(port), RTL8373_L2_UNMATCH_SA_CTRL_UNMATCH_SA_MASK(port), behavior); +} +/* Function Name: + * dal_rtl8373_l2_portUnmatchedSaBehavior_get + * Description: + * Get Unmatched SA behavior + * Input: + * port - port 0~9 + * pBehavior - 0: flooding; 1: drop; 2:trap + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t dal_rtl8373_l2_portUnmatchedSaBehavior_get(rtk_uint32 port, rtk_uint32 *pBehavior) +{ + return rtl8373_getAsicRegBits(RTL8373_L2_UNMATCH_SA_CTRL_ADDR(port), RTL8373_L2_UNMATCH_SA_CTRL_UNMATCH_SA_MASK(port), pBehavior); +} + + + +/* Function Name: + * dal_rtl8373_l2_portSaMovingForbid_set + * Description: + * Set Unmatched SA moving state + * Input: + * port - Port ID + * enabled - 0: can't move to new port; 1: can move to new port + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Error Port ID + * Note: + * None + */ +ret_t dal_rtl8373_l2_portSaMovingForbid_set(rtk_uint32 port, rtk_uint32 forbid) +{ + if(port >= RTL8373_PORTNO) + return RT_ERR_PORT_ID; + + return rtl8373_setAsicRegBit(RTL8373_L2_SA_MOVING_FORBID_ADDR(port), RTL8373_L2_SA_MOVING_FORBID_FORBID_OFFSET(port), forbid); +} + + +/* Function Name: + * dal_rtl8373_getAsicPortUnmatchedSaMoving + * Description: + * Get Unmatched SA moving state + * Input: + * port - Port ID + * Output: + * pEnabled - 0: can't move to new port; 1: can move to new port + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Error Port ID + * Note: + * None + */ +ret_t dal_rtl8373_l2_portSaMovingForbid_get(rtk_uint32 port, rtk_uint32 *pForbid) +{ + ret_t retVal; + + if(port >= RTL8373_PORTNO) + return RT_ERR_PORT_ID; + + if((retVal = rtl8373_getAsicRegBit(RTL8373_L2_SA_MOVING_FORBID_ADDR(port), RTL8373_L2_SA_MOVING_FORBID_FORBID_OFFSET(port), pForbid)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + + +/* Function Name: + * dal_rtl8373_srcPortPermit_set + * Description: + * Set Unmatched SA moving state + * Input: + * port - Port ID + * enabled - 0: pkt cannot tx from rx port; 1: pkt can tx from rx port + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Error Port ID + * Note: + * None + */ +ret_t dal_rtl8373_srcPortPermit_set(rtk_uint32 port, rtk_uint32 enable) +{ + if(port >= RTL8373_PORTNO) + return RT_ERR_PORT_ID; + + return rtl8373_setAsicRegBit(RTL8373_SOURCE_PORT_PERMIT_ADDR(port), RTL8373_SOURCE_PORT_PERMIT_SRC_PERMIT_EN_OFFSET(port), enable); +} + + +/* Function Name: + * dal_rtl8373_srcPortPermit_get + * Description: + * Get Unmatched SA moving state + * Input: + * port - Port ID + * Output: + * pEnabled -0: pkt cannot tx from rx port; 1: pkt can tx from rx port + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Error Port ID + * Note: + * None + */ +ret_t dal_rtl8373_srcPortPermit_get(rtk_uint32 port, rtk_uint32 *pEnable) +{ + ret_t retVal; + + if(port >= RTL8373_PORTNO) + return RT_ERR_PORT_ID; + + if((retVal = rtl8373_getAsicRegBit(RTL8373_SOURCE_PORT_PERMIT_ADDR(port), RTL8373_SOURCE_PORT_PERMIT_SRC_PERMIT_EN_OFFSET(port), pEnable)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_l2_unknUc_fldMsk_set + * Description: + * Set unicast pkt lookup miss action + * Input: + * portmask - l2 unicast pkt lookup miss flood portmask + * Output: + * + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Error Port ID + * Note: + * None + */ +ret_t dal_rtl8373_l2_unknUc_fldMsk_set(rtk_uint32 portMask) +{ + ret_t retVal; + + + if((retVal = rtl8373_setAsicReg(RTL8373_L2_UNKN_UC_FLD_PMSK_ADDR, portMask)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_l2_unknUc_fldMsk_get + * Description: + * get unicast pkt lookup miss action + * Input: + * portmask - l2 unicast pkt lookup miss flood portmask + * Output: + * + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Error Port ID + * Note: + * None + */ +ret_t dal_rtl8373_l2_unknUc_fldMsk_get(rtk_uint32* pMask) +{ + ret_t retVal; + + + if((retVal = rtl8373_getAsicReg(RTL8373_L2_UNKN_UC_FLD_PMSK_ADDR, pMask)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + + + + +/* Function Name: + * dal_rtl8373_l2_unknUc_action_set + * Description: + * Set unicast pkt lookup miss action + * Input: + * port - Port ID + * pAction - 0b00:fwd in L2_UNKNOW_UC_FLD_PMSK 0b01 drop 0b10 trap 0b11 flood + * Output: + * + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Error Port ID + * Note: + * None + */ +ret_t dal_rtl8373_l2_unknUc_action_set(rtk_uint32 port, rtk_uint32 action) +{ + ret_t retVal; + + if(port >= RTL8373_PORTNO) + return RT_ERR_PORT_ID; + + if((retVal = rtl8373_setAsicRegBits(RTL8373_L2_PORT_UC_LM_ACT_ADDR(port), RTL8373_L2_PORT_UC_LM_ACT_ACT_MASK(port), action)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + + +/* Function Name: + * dal_rtl8373_l2_unknUc_action_get + * Description: + * Get unicast pkt lookup miss action + * Input: + * port - Port ID + * pAction - 0b00:fwd in L2_UNKNOW_UC_FLD_PMSK 0b01 drop 0b10 trap 0b11 flood + * Output: + * + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Error Port ID + * Note: + * None + */ +ret_t dal_rtl8373_l2_unknUc_action_get(rtk_uint32 port, rtk_uint32 *pAction) +{ + ret_t retVal; + + if(port >= RTL8373_PORTNO) + return RT_ERR_PORT_ID; + + if((retVal = rtl8373_getAsicRegBits(RTL8373_L2_PORT_UC_LM_ACT_ADDR(port), RTL8373_L2_PORT_UC_LM_ACT_ACT_MASK(port), pAction)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_l2_unknMc_fldMsk_set + * Description: + * Set multicast pkt lookup miss action + * Input: + * portmask - l2 multicast pkt lookup miss flood portmask + * Output: + * + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Error Port ID + * Note: + * None + */ +ret_t dal_rtl8373_l2_unknMc_fldMsk_set(rtk_uint32 portMask) +{ + ret_t retVal; + + + if((retVal = rtl8373_setAsicReg(RTL8373_L2_UNKN_MC_FLD_PMSK_ADDR, portMask)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_l2_unknMc_fldMsk_get + * Description: + * get multicast pkt lookup miss action + * Input: + * portmask - l2 multicast pkt lookup miss flood portmask + * Output: + * + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Error Port ID + * Note: + * None + */ +ret_t dal_rtl8373_l2_unknMc_fldMsk_get(rtk_uint32* pMask) +{ + ret_t retVal; + + + if((retVal = rtl8373_getAsicReg(RTL8373_L2_UNKN_MC_FLD_PMSK_ADDR, pMask)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + + + + +/* Function Name: + * dal_rtl8373_l2_unknMc_action_set + * Description: + * Set multicast pkt lookup miss action + * Input: + * port - Port ID + * pAction - 0b00:fwd in L2_UNKNOW_MC_FLD_PMSK 0b01 drop 0b10 trap 0b11 drop exclude RMA + * Output: + * + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Error Port ID + * Note: + * None + */ +ret_t dal_rtl8373_l2_unknMc_action_set(rtk_uint32 port, rtk_uint32 action) +{ + ret_t retVal; + + if(port >= RTL8373_PORTNO) + return RT_ERR_PORT_ID; + + if((retVal = rtl8373_setAsicRegBits(RTL8373_L2_PORT_MC_LM_ACT_ADDR(port), RTL8373_L2_PORT_MC_LM_ACT_ACT_MASK(port), action)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + + +/* Function Name: + * dal_rtl8373_l2_unknMc_action_get + * Description: + * Get multicast pkt lookup miss action + * Input: + * port - Port ID + * pAction - 0b00:fwd in L2_UNKNOW_MC_FLD_PMSK 0b01 drop 0b10 trap 0b11 drop exclude RMA + * Output: + * + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Error Port ID + * Note: + * None + */ +ret_t dal_rtl8373_l2_unknMc_action_get(rtk_uint32 port, rtk_uint32 *pAction) +{ + ret_t retVal; + + if(port >= RTL8373_PORTNO) + return RT_ERR_PORT_ID; + + if((retVal = rtl8373_getAsicRegBits(RTL8373_L2_PORT_MC_LM_ACT_ADDR(port), RTL8373_L2_PORT_MC_LM_ACT_ACT_MASK(port), pAction)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + + +/* Function Name: + * dal_rtl8373_l2_unknV4Mc_fldMsk_set + * Description: + * Set ipv4 multicast pkt lookup miss action + * Input: + * portmask - ipv4 multicast pkt lookup miss flood portmask + * Output: + * + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Error Port ID + * Note: + * None + */ +ret_t dal_rtl8373_l2_unknV4Mc_fldMsk_set(rtk_uint32 portMask) +{ + ret_t retVal; + + + if((retVal = rtl8373_setAsicReg(RTL8373_IPV4_UNKN_MC_FLD_PMSK_ADDR, portMask)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_l2_unknV4Mc_fldMsk_get + * Description: + * get ipv4 multicast pkt lookup miss action + * Input: + * portmask - ipv4 multicast pkt lookup miss flood portmask + * Output: + * + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Error Port ID + * Note: + * None + */ +ret_t dal_rtl8373_l2_unknV4Mc_fldMsk_get(rtk_uint32* pMask) +{ + ret_t retVal; + + + if((retVal = rtl8373_getAsicReg(RTL8373_IPV4_UNKN_MC_FLD_PMSK_ADDR, pMask)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + + + + +/* Function Name: + * dal_rtl8373_l2_unknV4Mc_action_set + * Description: + * Set ipv4 multicast pkt lookup miss action + * Input: + * port - Port ID + * action - 0b00:fwd in IPV4_UNKNOW_MC_FLD_PMSK 0b01 drop 0b10 trap 0b11 to router port + * Output: + * + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Error Port ID + * Note: + * None + */ +ret_t dal_rtl8373_l2_unknV4Mc_action_set(rtk_uint32 port, rtk_uint32 action) +{ + ret_t retVal; + + if(port >= RTL8373_PORTNO) + return RT_ERR_PORT_ID; + + if((retVal = rtl8373_setAsicRegBits(RTL8373_IPV4_PORT_MC_LM_ACT_ADDR(port), RTL8373_IPV4_PORT_MC_LM_ACT_ACT_MASK(port), action)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + + +/* Function Name: + * dal_rtl8373_l2_unknV4Mc_action_get + * Description: + * Get ipv4 multicast pkt lookup miss action + * Input: + * port - Port ID + * pAction - 0b00:fwd in IPV4_UNKNOW_MC_FLD_PMSK 0b01 drop 0b10 trap 0b11 to router port + * Output: + * + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Error Port ID + * Note: + * None + */ +ret_t dal_rtl8373_l2_unknV4Mc_action_get(rtk_uint32 port, rtk_uint32 *pAction) +{ + ret_t retVal; + + if(port >= RTL8373_PORTNO) + return RT_ERR_PORT_ID; + + if((retVal = rtl8373_getAsicRegBits(RTL8373_IPV4_PORT_MC_LM_ACT_ADDR(port), RTL8373_IPV4_PORT_MC_LM_ACT_ACT_MASK(port), pAction)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + + + +/* Function Name: + * dal_rtl8373_l2_unknV6Mc_fldMsk_set + * Description: + * Set ipv6 multicast pkt lookup miss action + * Input: + * portmask - ipv6 multicast pkt lookup miss flood portmask + * Output: + * + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Error Port ID + * Note: + * None + */ +ret_t dal_rtl8373_l2_unknV6Mc_fldMsk_set(rtk_uint32 portMask) +{ + ret_t retVal; + + + if((retVal = rtl8373_setAsicReg(RTL8373_IPV6_UNKN_MC_FLD_PMSK_ADDR, portMask)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_l2_unknV6Mc_fldMsk_get + * Description: + * get ipv6 multicast pkt lookup miss action + * Input: + * portmask - ipv6 multicast pkt lookup miss flood portmask + * Output: + * + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Error Port ID + * Note: + * None + */ +ret_t dal_rtl8373_l2_unknV6Mc_fldMsk_get(rtk_uint32* pMask) +{ + ret_t retVal; + + + if((retVal = rtl8373_getAsicReg(RTL8373_IPV6_UNKN_MC_FLD_PMSK_ADDR, pMask)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + + + + +/* Function Name: + * dal_rtl8373_l2_unknV6Mc_action_set + * Description: + * Set ipv6 multicast pkt lookup miss action + * Input: + * port - Port ID + * action - 0b00:fwd in IPV6_UNKNOW_MC_FLD_PMSK 0b01 drop 0b10 trap 0b11 to router port + * Output: + * + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Error Port ID + * Note: + * None + */ +ret_t dal_rtl8373_l2_unknV6Mc_action_set(rtk_uint32 port, rtk_uint32 action) +{ + ret_t retVal; + + if(port >= RTL8373_PORTNO) + return RT_ERR_PORT_ID; + + if((retVal = rtl8373_setAsicRegBits(RTL8373_IPV6_PORT_MC_LM_ACT_ADDR(port), RTL8373_IPV6_PORT_MC_LM_ACT_ACT_MASK(port), action)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + + +/* Function Name: + * dal_rtl8373_l2_unknV6Mc_action_get + * Description: + * Get ipv6 multicast pkt lookup miss action + * Input: + * port - Port ID + * pAction - 0b00:fwd in IPV6_UNKNOW_MC_FLD_PMSK 0b01 drop 0b10 trap 0b11 to router port + * Output: + * + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Error Port ID + * Note: + * None + */ +ret_t dal_rtl8373_l2_unknV6Mc_action_get(rtk_uint32 port, rtk_uint32 *pAction) +{ + ret_t retVal; + + if(port >= RTL8373_PORTNO) + return RT_ERR_PORT_ID; + + if((retVal = rtl8373_getAsicRegBits(RTL8373_IPV6_PORT_MC_LM_ACT_ADDR(port), RTL8373_IPV6_PORT_MC_LM_ACT_ACT_MASK(port), pAction)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_l2_brdcast_fldMsk_set + * Description: + * set brdcast pkt flood port mask + * Input: + * portMask - brdcast pkt flood port mask + * Output: + * + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Error Port ID + * Note: + * None + */ +ret_t dal_rtl8373_l2_brdcast_fldMsk_set(rtk_uint32 portMask) +{ + ret_t retVal; + + + if((retVal = rtl8373_setAsicReg(RTL8373_L2_BC_FLD_PMSK_ADDR, portMask)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + + +/* Function Name: + * dal_rtl8373_l2_brdcast_fldMsk_get + * Description: + * get brdcast pkt flood port mask + * Input: + * pMask - brdcast pkt flood port mask + * Output: + * + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Error Port ID + * Note: + * None + */ +ret_t dal_rtl8373_l2_brdcast_fldMsk_get(rtk_uint32* pMask) +{ + ret_t retVal; + + + if((retVal = rtl8373_getAsicReg(RTL8373_L2_BC_FLD_PMSK_ADDR, pMask)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + + +/* Function Name: + * dal_rtl8373_l2_trapPort_set + * Description: + * set l2 trap cpu port mask + * Input: + * trapport - 0b00 none 0b01:8051 0b10:external cpu 0b11: 8051&external + * Output: + * + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ + +rtk_api_ret_t dal_rtl8373_l2_trapPort_set(rtk_uint32 trapport) +{ + ret_t retVal; + + if(trapport > TRAP_BOTH) + return RT_ERR_INPUT; + + if((retVal = rtl8373_setAsicRegBits(RTL8373_L2_CTRL_ADDR, RTL8373_L2_CTRL_CPU_PMSK_MASK, trapport)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_l2_trapPort_Get + * Description: + * get l2 trap cpu port mask + * Input: + * trapport - 0b00 none 0b01:8051 0b10:external cpu 0b11: 8051&external + * Output: + * + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ + +rtk_api_ret_t dal_rtl8373_l2_trapPort_get(rtk_uint32 * pTrapport) +{ + ret_t retVal; + + if(pTrapport == NULL) + return RT_ERR_NULL_POINTER; + + if((retVal = rtl8373_getAsicRegBits(RTL8373_L2_CTRL_ADDR, RTL8373_L2_CTRL_CPU_PMSK_MASK, pTrapport)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_l2_trapPri_set + * Description: + * set l2 trap cpu port mask + * Input: + * type - 0: normal pkt 1: multicast + * trappri - trap priority + * Output: + * + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ + +rtk_api_ret_t dal_rtl8373_l2_trapPri_set(rtk_uint32 type, rtk_uint32 trappri) +{ + + if (type == 0) + return rtl8373_setAsicRegBits(RTL8373_L2_CTRL_ADDR, RTL8373_L2_CTRL_TRAP_PRI_MASK, trappri); + + else if (type == 1) + return rtl8373_setAsicRegBits(RTL8373_L2_CTRL_ADDR, RTL8373_L2_CTRL_MUL_TRAP_PRI_MASK, trappri); + + return RT_ERR_OK; +} + + + +/* Function Name: + * dal_rtl8373_l2_trapPri_get + * Description: + * set l2 trap cpu port mask + * Input: + * type - 0: normal pkt 1: multicast + * pTrappri - trap priority + * Output: + * + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ + +rtk_api_ret_t dal_rtl8373_l2_trapPri_get(rtk_uint32 type, rtk_uint32* pTrappri) +{ + + if (type == 0) + return rtl8373_getAsicRegBits(RTL8373_L2_CTRL_ADDR, RTL8373_L2_CTRL_TRAP_PRI_MASK, pTrappri); + + else if (type == 1) + return rtl8373_getAsicRegBits(RTL8373_L2_CTRL_ADDR, RTL8373_L2_CTRL_MUL_TRAP_PRI_MASK, pTrappri); + + return RT_ERR_OK; +} + + + + +/* Function Name: + * dal_rtl8373_l2_hashFull_set + * Description: + * set l2 hsah full acti + * Input: + * act - 0b00 fwd 0b01:drop 0b10:trap + * Output: + * + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ + +rtk_api_ret_t dal_rtl8373_l2_hashFull_set(rtk_uint32 act) +{ + ret_t retVal; + + if((retVal = rtl8373_setAsicRegBits(RTL8373_L2_CTRL_ADDR, RTL8373_L2_CTRL_HASH_FULL_ACT_MASK, act)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_l2_hashFull_get + * Description: + * get l2 hsah full acti + * Input: + * pAct - 0b00 fwd 0b01:drop 0b10:trap + * Output: + * + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ + +rtk_api_ret_t dal_rtl8373_l2_hashFull_get(rtk_uint32* pAct) +{ + ret_t retVal; + + if((retVal = rtl8373_getAsicRegBits(RTL8373_L2_CTRL_ADDR, RTL8373_L2_CTRL_HASH_FULL_ACT_MASK, pAct)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + + +/* Function Name: + * dal_rtl8373_l2_ipMul_noVlanEgr_set + * Description: + * set ipmulticast bypass vlanegress filter + * Input: + * port - port number + * enable - 0 disable vlan egress filter 1 enable vlan egress filter + * Output: + * + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ + +rtk_api_ret_t dal_rtl8373_l2_ipMul_noVlanEgr_set(rtk_uint32 port, rtk_uint32 enable) +{ + ret_t retVal; + + if((retVal = rtl8373_setAsicRegBit(RTL8373_IPMUL_NO_VLAN_EGRESS_ADDR(port), RTL8373_IPMUL_NO_VLAN_EGRESS_IPMUL_VLAN_LEAKY_OFFSET(port), enable)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_l2_ipMul_noVlanEgr_get + * Description: + * get ipmulticast bypass vlanegress filter + * Input: + * port - port number + * pEnable - 0 disable vlan egress filter 1 enable vlan egress filter + * Output: + * + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ + +rtk_api_ret_t dal_rtl8373_l2_ipMul_noVlanEgr_get(rtk_uint32 port, rtk_uint32* pEnable) +{ + ret_t retVal; + + if((retVal = rtl8373_getAsicRegBit(RTL8373_IPMUL_NO_VLAN_EGRESS_ADDR(port), RTL8373_IPMUL_NO_VLAN_EGRESS_IPMUL_VLAN_LEAKY_OFFSET(port), pEnable)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_l2_ipMul_noPortIso_set + * Description: + * set ipmulticast bypass port isolation filter + * Input: + * port - port number + * enable - 0 disable port isolation filter 1 enable port isolation filter + * Output: + * + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ + +rtk_api_ret_t dal_rtl8373_l2_ipMul_noPortIso_set(rtk_uint32 port, rtk_uint32 enable) +{ + ret_t retVal; + + if((retVal = rtl8373_setAsicRegBit(RTL8373_IPMUL_NO_PORTISO_ADDR(port), RTL8373_IPMUL_NO_PORTISO_IPMUL_PORTISO_LEAKY_OFFSET(port), enable)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_l2_ipMul_noPortIso_get + * Description: + * get ipmulticast bypass port isolation filter + * Input: + * port - port number + * pEnable - 0 disable port isolation filter 1 enable port isolation filter + * Output: + * + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ + +rtk_api_ret_t dal_rtl8373_l2_ipMul_noPortIso_get(rtk_uint32 port, rtk_uint32* pEnable) +{ + ret_t retVal; + + if((retVal = rtl8373_getAsicRegBit(RTL8373_IPMUL_NO_PORTISO_ADDR(port), RTL8373_IPMUL_NO_PORTISO_IPMUL_PORTISO_LEAKY_OFFSET(port), pEnable)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_l2_forceMode_set + * Description: + * set l2 force mode + * Input: + * port - port number + * enable - 0 disable port force mode 1 enable port force mode + * Output: + * + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ + +rtk_api_ret_t dal_rtl8373_l2_forceMode_set(rtk_uint32 port, rtk_uint32 enable) +{ + ret_t retVal; + + if((retVal = rtl8373_setAsicRegBit(RTL8373_L2_FORCE_MODE_ADDR(port), RTL8373_L2_FORCE_MODE_FORCE_CTRL_OFFSET(port), enable)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_l2_forceMode_get + * Description: + * get l2 force mode + * Input: + * port - port number + * enable - 0 disable port force mode 1 enable port force mode + * Output: + * + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ + +rtk_api_ret_t dal_rtl8373_l2_forceMode_get(rtk_uint32 port, rtk_uint32* pEnable) +{ + ret_t retVal; + + if((retVal = rtl8373_getAsicRegBit(RTL8373_L2_FORCE_MODE_ADDR(port), RTL8373_L2_FORCE_MODE_FORCE_CTRL_OFFSET(port), pEnable)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_l2_forceMode_portMsk_set + * Description: + * set l2 force mode + * Input: + * port - port number + * portmask - port mask + * Output: + * + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ + +rtk_api_ret_t dal_rtl8373_l2_forceMode_portMsk_set(rtk_uint32 port, rtk_uint32 portmask) +{ + ret_t retVal; + + if((retVal = rtl8373_setAsicRegBits(RTL8373_L2_FORCE_DPM_PORT_ADDR(port), RTL8373_L2_FORCE_DPM_PORT_FORCE_PORT_MASK_MASK, portmask)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_l2_forceMode_portMsk_get + * Description: + * get l2 force mode + * Input: + * port - port number + * portmask - port mask + * Output: + * + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ + +rtk_api_ret_t dal_rtl8373_l2_forceMode_portMsk_get(rtk_uint32 port, rtk_uint32* pMask) +{ + ret_t retVal; + + if((retVal = rtl8373_getAsicRegBits(RTL8373_L2_FORCE_DPM_PORT_ADDR(port), RTL8373_L2_FORCE_DPM_PORT_FORCE_PORT_MASK_MASK, pMask)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + + +/* Function Name: + * dal_rtl8373_l2_floodPortMsk_set + * Description: + * set flood portmask + * Input: + * flood_type - unknown unicast, unknown l2 multicast, unknown IPV4 multicast, unknown IPV6 multicast, broadcast + * pFlood_portmask - port mask + * Output: + * + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ + +rtk_api_ret_t dal_rtl8373_l2_floodPortMsk_set(rtk_l2_flood_type_t flood_type, rtk_portmask_t *pFlood_portmask) +{ + rtk_api_ret_t retVal; + rtk_uint32 pmask; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pFlood_portmask) + return RT_ERR_NULL_POINTER; + + /* Check port mask */ + RTK_CHK_PORTMASK_VALID(pFlood_portmask); + + if ((retVal = rtk_switch_portmask_L2P_get(pFlood_portmask, &pmask)) != RT_ERR_OK) + return retVal; + + if(flood_type == FLOOD_UNKNOWNDA) + return dal_rtl8373_l2_unknUc_fldMsk_set(pmask); + else if(flood_type == FLOOD_UNKNOWNL2MC) + return dal_rtl8373_l2_unknMc_fldMsk_set(pmask); + else if(flood_type == FLOOD_UNKNOWNV4MC) + return dal_rtl8373_l2_unknV4Mc_fldMsk_set(pmask); + else if(flood_type == FLOOD_UNKNOWNV6MC) + return dal_rtl8373_l2_unknV6Mc_fldMsk_set(pmask); + else if(flood_type == FLOOD_BC) + return dal_rtl8373_l2_brdcast_fldMsk_set(pmask); + else + return RT_ERR_INPUT; + + return RT_ERR_OK; +} + + + + + +/* Function Name: + * dal_rtl8373_l2_floodPortMsk_get + * Description: + * Get flood portmask + * Input: + * flood_type - unknown unicast, unknown l2 multicast, unknown IPV4 multicast, unknown IPV6 multicast, broadcast + * pFlood_portmask - port mask + * Output: + * + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ + +rtk_api_ret_t dal_rtl8373_l2_floodPortMsk_get(rtk_l2_flood_type_t flood_type, rtk_portmask_t *pFlood_portmask) +{ + rtk_api_ret_t retVal; + rtk_uint32 pmask; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pFlood_portmask) + return RT_ERR_NULL_POINTER; + + + if(flood_type == FLOOD_UNKNOWNDA) + { + retVal = dal_rtl8373_l2_unknUc_fldMsk_get(&pmask); + if(retVal != RT_ERR_OK) + return retVal; + } + else if(flood_type == FLOOD_UNKNOWNL2MC) + { + retVal = dal_rtl8373_l2_unknMc_fldMsk_get(&pmask); + if(retVal != RT_ERR_OK) + return retVal; + } + else if(flood_type == FLOOD_UNKNOWNV4MC) + { + retVal = dal_rtl8373_l2_unknV4Mc_fldMsk_get(&pmask); + if(retVal != RT_ERR_OK) + return retVal; + } + else if(flood_type == FLOOD_UNKNOWNV6MC) + { + retVal = dal_rtl8373_l2_unknV6Mc_fldMsk_get(&pmask); + if(retVal != RT_ERR_OK) + return retVal; + } + else if(flood_type == FLOOD_BC) + { + retVal = dal_rtl8373_l2_brdcast_fldMsk_get(&pmask); + if(retVal != RT_ERR_OK) + return retVal; + } + else + return RT_ERR_INPUT; + + if ((retVal = rtk_switch_portmask_P2L_get(pmask, pFlood_portmask)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + + + + + + + + + + + + + + + diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_lut.h b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_lut.h new file mode 100755 index 00000000..4d9ba0df --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_lut.h @@ -0,0 +1,1873 @@ +#ifndef __DAL_RTL8373_LUT_H__ +#define __DAL_RTL8373_LUT_H__ + + +#include + + +#define RTL8373_LUT_IPMCGRP_TABLE_MAX (0x3F) + +#define RTL8373_LUT_BUSY_CHECK_NO (10) + +#define RTL8373_LUT_TABLE_SIZE (3) + + + +#define RTL8373_LUTREADMETHOD_MAC 0 +#define RTL8373_LUTREADMETHOD_ADDRESS 1 +#define RTL8373_LUTREADMETHOD_NEXT_ADDRESS 2 +#define RTL8373_LUTREADMETHOD_NEXT_L2UC 3 +#define RTL8373_LUTREADMETHOD_NEXT_L2MC 4 +#define RTL8373_LUTREADMETHOD_NEXT_L3MC 5 +#define RTL8373_LUTREADMETHOD_NEXT_L2L3MC 6 +#define RTL8373_LUTREADMETHOD_NEXT_L2UCSPA 7 + + +enum L2_NEWSA_BEHAVE +{ + L2_NEWSA_FWD = 0, + L2_NEWSA_DROP, + L2_NEWSA_TRAP, + L2_BEHAVE_SA_END +}; + + +enum RTL8373_FLUSHMODE +{ + FLUSHMDOE_PORT = 0, + FLUSHMDOE_VID, + FLUSHMDOE_FID, + FLUSHMDOE_END, +}; + +enum RTL8373_L2_TRAPPORT +{ + TRAP_NONE = 0, + TRAP_8051, + TRAP_EXTERNAL, + TRAP_BOTH, +}; + + + +typedef struct LUTTABLE{ + + ipaddr_t sip; + ipaddr_t dip; + ether_addr_t mac; + rtk_uint16 ivl_svl; + rtk_uint16 cvid_fid; + rtk_uint16 nosalearn; + rtk_uint16 mbr; + rtk_uint16 spa; + rtk_uint16 age; + rtk_uint16 l3lookup; + rtk_uint16 auth; + rtk_uint16 igmp_idx; + rtk_uint16 igmp_asic; + + rtk_uint16 lookup_hit; + rtk_uint16 lookup_busy; + rtk_uint16 address; + rtk_uint16 wait_time; + +}rtl8373_luttb; + + +typedef struct IPMCTBL{ + rtk_uint32 ipaddr; + rtk_uint32 portmask; + rtk_uint32 index; +}rtl8373_ipmctbl; + + +/* Function Name: + * dal_rtl8373_l2_init + * Description: + * Initialize lut function. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8373_l2_init(void); + + + +/* Function Name: + * dal_rtl8373_l2_addr_add + * Description: + * Add LUT unicast entry. + * Input: + * pMac - 6 bytes unicast(I/G bit is 0) mac address to be written into LUT. + * pL2_data - Unicast entry parameter + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_L2_FID - Invalid FID . + * RT_ERR_L2_INDEXTBL_FULL - hashed index is full of entries. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * If the unicast mac address already existed in LUT, it will udpate the status of the entry. + * Otherwise, it will find an empty or asic auto learned entry to write. If all the entries + * with the same hash value can't be replaced, ASIC will return a RT_ERR_L2_INDEXTBL_FULL error. + */ + +extern rtk_api_ret_t dal_rtl8373_l2_addr_add(rtk_mac_t *pMac, rtk_l2_ucastAddr_t *pL2_data); + + +/* Function Name: + * dal_rtl8373_l2_addr_get + * Description: + * Get LUT unicast entry. + * Input: + * pMac - 6 bytes unicast(I/G bit is 0) mac address to be written into LUT. + * Output: + * pL2_data - Unicast entry parameter + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_L2_FID - Invalid FID . + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * If the unicast mac address existed in LUT, it will return the port and fid where + * the mac is learned. Otherwise, it will return a RT_ERR_L2_ENTRY_NOTFOUND error. + */ +extern rtk_api_ret_t dal_rtl8373_l2_addr_get(rtk_mac_t *pMac, rtk_l2_ucastAddr_t *pL2_data); + +/* Function Name: + * dal_rtl8373_l2_addr_next_get + * Description: + * Get Next LUT unicast entry. + * Input: + * read_method - The reading method. + * port - The port number if the read_metohd is READMETHOD_NEXT_L2UCSPA + * pAddress - The Address ID + * Output: + * pL2_data - Unicast entry parameter + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_L2_FID - Invalid FID . + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * Get the next unicast entry after the current entry pointed by pAddress. + * The address of next entry is returned by pAddress. User can use (address + 1) + * as pAddress to call this API again for dumping all entries is LUT. + */ +extern rtk_api_ret_t dal_rtl8373_l2_addr_next_get(rtk_l2_read_method_t read_method, rtk_port_t port, rtk_uint32 *pAddress, rtk_l2_ucastAddr_t *pL2_data); + + +/* Function Name: + * dal_rtl8373_l2_addr_del + * Description: + * Delete LUT unicast entry. + * Input: + * pMac - 6 bytes unicast(I/G bit is 0) mac address to be written into LUT. + * fid - Filtering database + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_L2_FID - Invalid FID . + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * If the mac has existed in the LUT, it will be deleted. Otherwise, it will return RT_ERR_L2_ENTRY_NOTFOUND. + */ +extern rtk_api_ret_t dal_rtl8373_l2_addr_del(rtk_mac_t *pMac, rtk_l2_ucastAddr_t *pL2_data); + + + +/* Function Name: + * dal_rtl8373_l2_mcastAddr_add + * Description: + * Add LUT multicast entry. + * Input: + * pMcastAddr - L2 multicast entry structure + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_L2_FID - Invalid FID . + * RT_ERR_L2_VID - Invalid VID . + * RT_ERR_L2_INDEXTBL_FULL - hashed index is full of entries. + * RT_ERR_PORT_MASK - Invalid portmask. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * If the multicast mac address already existed in the LUT, it will udpate the + * port mask of the entry. Otherwise, it will find an empty or asic auto learned + * entry to write. If all the entries with the same hash value can't be replaced, + * ASIC will return a RT_ERR_L2_INDEXTBL_FULL error. + */ +extern rtk_api_ret_t dal_rtl8373_l2_mcastAddr_add(rtk_l2_mcastAddr_t *pMcastAddr); + +/* Function Name: + * dal_rtl8373_l2_mcastAddr_get + * Description: + * Get LUT multicast entry. + * Input: + * pMcastAddr - L2 multicast entry structure + * Output: + * pMcastAddr - L2 multicast entry structure + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_L2_FID - Invalid FID . + * RT_ERR_L2_VID - Invalid VID . + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * If the multicast mac address existed in the LUT, it will return the port where + * the mac is learned. Otherwise, it will return a RT_ERR_L2_ENTRY_NOTFOUND error. + */ +extern rtk_api_ret_t dal_rtl8373_l2_mcastAddr_get(rtk_l2_mcastAddr_t *pMcastAddr); + + +/* Function Name: + * dal_rtl8373_l2_mcastAddr_next_get + * Description: + * Get Next L2 Multicast entry. + * Input: + * pAddress - The Address ID + * Output: + * pMcastAddr - L2 multicast entry structure + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * Get the next L2 multicast entry after the current entry pointed by pAddress. + * The address of next entry is returned by pAddress. User can use (address + 1) + * as pAddress to call this API again for dumping all multicast entries is LUT. + */ +extern rtk_api_ret_t dal_rtl8373_l2_mcastAddr_next_get(rtk_uint32 *pAddress, rtk_l2_mcastAddr_t *pMcastAddr); + + +/* Function Name: + * dal_rtl8373_l2_mcastAddr_del + * Description: + * Delete LUT multicast entry. + * Input: + * pMcastAddr - L2 multicast entry structure + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_L2_FID - Invalid FID . + * RT_ERR_L2_VID - Invalid VID . + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * If the mac has existed in the LUT, it will be deleted. Otherwise, it will return RT_ERR_L2_ENTRY_NOTFOUND. + */ +extern rtk_api_ret_t dal_rtl8373_l2_mcastAddr_del(rtk_l2_mcastAddr_t *pMcastAddr); + + +/* Function Name: + * dal_rtl8373_l2_ipMcastAddr_add + * Description: + * Add Lut IP multicast entry + * Input: + * pIpMcastAddr - IP Multicast entry + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_L2_INDEXTBL_FULL - hashed index is full of entries. + * RT_ERR_PORT_MASK - Invalid portmask. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * System supports L2 entry with IP multicast DIP/SIP to forward IP multicasting frame as user + * desired. If this function is enabled, then system will be looked up L2 IP multicast entry to + * forward IP multicast frame directly without flooding. + */ +extern rtk_api_ret_t dal_rtl8373_l2_ipMcastAddr_add(rtk_l2_ipMcastAddr_t *pIpMcastAddr); + + +/* Function Name: + * dal_rtl8373_l2_ipMcastAddr_get + * Description: + * Get LUT IP multicast entry. + * Input: + * pIpMcastAddr - IP Multicast entry + * Output: + * pIpMcastAddr - IP Multicast entry + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get Lut table of IP multicast entry. + */ +extern rtk_api_ret_t dal_rtl8373_l2_ipMcastAddr_get(rtk_l2_ipMcastAddr_t *pIpMcastAddr); + +/* Function Name: + * dal_rtl8373_l2_ipMcastAddr_next_get + * Description: + * Get Next IP Multicast entry. + * Input: + * pAddress - The Address ID + * Output: + * pIpMcastAddr - IP Multicast entry + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * Get the next IP multicast entry after the current entry pointed by pAddress. + * The address of next entry is returned by pAddress. User can use (address + 1) + * as pAddress to call this API again for dumping all IP multicast entries is LUT. + */ +extern rtk_api_ret_t dal_rtl8373_l2_ipMcastAddr_next_get(rtk_uint32 *pAddress, rtk_l2_ipMcastAddr_t *pIpMcastAddr); + + + +/* Function Name: + * dal_rtl8373_l2_ipMcastAddr_del + * Description: + * Delete a ip multicast address entry from the specified device. + * Input: + * pIpMcastAddr - IP Multicast entry + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can delete a IP multicast address entry from the specified device. + */ +extern rtk_api_ret_t dal_rtl8373_l2_ipMcastAddr_del(rtk_l2_ipMcastAddr_t *pIpMcastAddr); + +/* Function Name: + * dal_rtl8373_l2_ucastAddr_flush + * Description: + * Flush L2 mac address by type in the specified device (both dynamic and static). + * Input: + * pConfig - flush configuration + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * flushByVid - 1: Flush by VID, 0: Don't flush by VID + * vid - VID (0 ~ 4095) + * flushByFid - 1: Flush by FID, 0: Don't flush by FID + * fid - FID (0 ~ 15) + * flushByPort - 1: Flush by Port, 0: Don't flush by Port + * port - Port ID + * flushByMac - Not Supported + * ucastAddr - Not Supported + * flushStaticAddr - 1: Flush both Static and Dynamic entries, 0: Flush only Dynamic entries + * flushAddrOnAllPorts - 1: Flush VID-matched entries at all ports, 0: Flush VID-matched entries per port. + */ +extern rtk_api_ret_t dal_rtl8373_l2_ucastAddr_flush(rtk_l2_flushCfg_t *pConfig); + + + +/* Function Name: + * dal_rtl8373_l2_table_clear + * Description: + * Flush all static & dynamic entries in LUT. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * + */ + +extern rtk_api_ret_t dal_rtl8373_l2_table_clear(void); + + + +/* Function Name: + * dal_rtl8373_l2_table_clearStatus_get + * Description: + * Get table clear status + * Input: + * None + * Output: + * pStatus - Clear status, 1:Busy, 0:finish + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8373_l2_table_clearStatus_get(rtk_l2_clearStatus_t *pStatus); + + +/* Function Name: + * dal_rtl8373_l2_flushLinkDownPortAddrEnable_set + * Description: + * Set HW flush linkdown port mac configuration of the specified device. + * Input: + * enable - link down flush status + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * The status of flush linkdown port address is as following: + * - DISABLED + * - ENABLED + */ +extern rtk_api_ret_t dal_rtl8373_l2_flushLinkDownPortAddrEnable_set(rtk_enable_t enable); + + +/* Function Name: + * dal_rtl8373_l2_flushLinkDownPortAddrEnable_get + * Description: + * Get HW flush linkdown port mac configuration of the specified device. + * Input: + * Output: + * pEnable - link down flush status + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The status of flush linkdown port address is as following: + * - DISABLED + * - ENABLED + */ +extern rtk_api_ret_t dal_rtl8373_l2_flushLinkDownPortAddrEnable_get(rtk_enable_t *pEnable); + + +/* Function Name: + * dal_rtl8373_l2_agingEnable_set + * Description: + * Set L2 LUT aging status per port setting. + * Input: + * port - Port id. + * enable - Aging status + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * This API can be used to set L2 LUT aging status per port. + */ +extern rtk_api_ret_t dal_rtl8373_l2_agingEnable_set(rtk_port_t port, rtk_enable_t enable); + + + + +/* Function Name: + * dal_rtl8373_l2_agingEnable_get + * Description: + * Get L2 LUT aging status per port setting. + * Input: + * port - Port id. + * Output: + * pEnable - Aging status + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can be used to get L2 LUT aging function per port. + */ +extern rtk_api_ret_t dal_rtl8373_l2_agingEnable_get(rtk_port_t port, rtk_enable_t *pEnable); + + + + +/* Function Name: + * dal_rtl8373_l2_ageout_timer_set + * Description: + * Set L2 LUT entry age out timer. + * Input: + * timer - the time of an lut entry ageout without update. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * This API can be used to set L2 LUT aging status per port. + */ +extern rtk_api_ret_t dal_rtl8373_l2_ageout_timer_set(rtk_uint32 timer); + +/* Function Name: + * dal_rtl8373_l2_ageout_timer_get + * Description: + * Get L2 LUT entry age out timer. + * Input: + * pTimer - the time of an lut entry ageout without update. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * This API can be used to set L2 LUT aging status per port. + */ +extern rtk_api_ret_t dal_rtl8373_l2_ageout_timer_get(rtk_uint32 *pTimer); + + + +/* Function Name: + * dal_rtl8373_l2_ageout_timer_set + * Description: + * Set L2 LUT entry age field value when address learned in lut table. + * Input: + * timer - the time of an lut entry ageout without update. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * This API can be used to set L2 LUT aging status per port. + */ +extern rtk_api_ret_t dal_rtl8373_l2_agefield_value_set(rtk_uint32 value); + +/* Function Name: + * dal_rtl8373_l2_agefield_value_get + * Description: + * Get L2 LUT entry age field value when address learned in lut table. + * Input: + * pTimer - the time of an lut entry ageout without update. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * This API can be used to set L2 LUT aging status per port. + */ +extern rtk_api_ret_t dal_rtl8373_l2_agefield_value_get(rtk_uint32 *pValue); + + + +/* Function Name: + * dal_rtl8373_l2_limitLearningCnt_set + * Description: + * Set per-Port auto learning limit number + * Input: + * port - Port id. + * mac_cnt - Auto learning entries limit number + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_LIMITED_L2ENTRY_NUM - Invalid auto learning limit number + * Note: + * The API can set per-port ASIC auto learning limit number from 0(disable learning) + * to 2112. + */ +extern rtk_api_ret_t dal_rtl8373_l2_limitLearningCnt_set(rtk_port_t port, rtk_mac_cnt_t mac_cnt); + + +/* Function Name: + * dal_rtl8373_l2_limitLearningCnt_get + * Description: + * Get per-Port auto learning limit number + * Input: + * port - Port id. + * Output: + * pMac_cnt - Auto learning entries limit number + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get per-port ASIC auto learning limit number. + */ +extern rtk_api_ret_t dal_rtl8373_l2_limitLearningCnt_get(rtk_port_t port, rtk_mac_cnt_t *pMac_cnt); + + +/* Function Name: + * dal_rtl8373_l2_limitSystemLearningCnt_set + * Description: + * Set System auto learning limit number + * Input: + * mac_cnt - Auto learning entries limit number + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_LIMITED_L2ENTRY_NUM - Invalid auto learning limit number + * Note: + * The API can set system ASIC auto learning limit number from 0(disable learning) + * to 2112. + */ +extern rtk_api_ret_t dal_rtl8373_l2_limitSystemLearningCnt_set(rtk_mac_cnt_t mac_cnt); + + +/* Function Name: + * dal_rtl8373_l2_limitSystemLearningCnt_get + * Description: + * Get System auto learning limit number + * Input: + * None + * Output: + * pMac_cnt - Auto learning entries limit number + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get system ASIC auto learning limit number. + */ +extern rtk_api_ret_t dal_rtl8373_l2_limitSystemLearningCnt_get(rtk_mac_cnt_t *pMac_cnt); + + +/* Function Name: + * dal_rtl8373_l2_limitLearningCntAction_set + * Description: + * Configure auto learn over limit number action. + * Input: + * port - Port id. + * action - Auto learning entries limit number + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_NOT_ALLOWED - Invalid learn over action + * Note: + * The API can set SA unknown packet action while auto learn limit number is over + * The action symbol as following: + * - LIMIT_LEARN_CNT_ACTION_DROP, + * - LIMIT_LEARN_CNT_ACTION_FORWARD, + * - LIMIT_LEARN_CNT_ACTION_TO_CPU, + */ +extern rtk_api_ret_t dal_rtl8373_l2_limitLearningCntAction_set(rtk_port_t port, rtk_l2_limitLearnCntAction_t action); + + +/* Function Name: + * dal_rtl8373_l2_limitLearningCntAction_get + * Description: + * Get auto learn over limit number action. + * Input: + * port - Port id. + * Output: + * pAction - Learn over action + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get SA unknown packet action while auto learn limit number is over + * The action symbol as following: + * - LIMIT_LEARN_CNT_ACTION_DROP, + * - LIMIT_LEARN_CNT_ACTION_FORWARD, + * - LIMIT_LEARN_CNT_ACTION_TO_CPU, + */ +extern rtk_api_ret_t dal_rtl8373_l2_limitLearningCntAction_get(rtk_port_t port, rtk_l2_limitLearnCntAction_t *pAction); + + + +/* Function Name: + * dal_rtl8373_l2_limitSystemLearningCntAction_set + * Description: + * Configure system auto learn over limit number action. + * Input: + * port - Port id. + * action - Auto learning entries limit number + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_NOT_ALLOWED - Invalid learn over action + * Note: + * The API can set SA unknown packet action while auto learn limit number is over + * The action symbol as following: + * - LIMIT_LEARN_CNT_ACTION_DROP, + * - LIMIT_LEARN_CNT_ACTION_FORWARD, + * - LIMIT_LEARN_CNT_ACTION_TO_CPU, + */ +extern rtk_api_ret_t dal_rtl8373_l2_limitSystemLearningCntAction_set(rtk_l2_limitLearnCntAction_t action); + + +/* Function Name: + * dal_rtl8373_l2_limitSystemLearningCntAction_get + * Description: + * Get system auto learn over limit number action. + * Input: + * None. + * Output: + * pAction - Learn over action + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get SA unknown packet action while auto learn limit number is over + * The action symbol as following: + * - LIMIT_LEARN_CNT_ACTION_DROP, + * - LIMIT_LEARN_CNT_ACTION_FORWARD, + * - LIMIT_LEARN_CNT_ACTION_TO_CPU, + */ +extern rtk_api_ret_t dal_rtl8373_l2_limitSystemLearningCntAction_get(rtk_l2_limitLearnCntAction_t *pAction); + + +/* Function Name: + * dal_rtl8373_l2_limitSystemLearningCntPortMask_set + * Description: + * Configure system auto learn portmask + * Input: + * pPortmask - Port Mask + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Invalid port mask. + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8373_l2_limitSystemLearningCntPortMask_set(rtk_portmask_t *pPortmask); + + +/* Function Name: + * dal_rtl8373_l2_limitSystemLearningCntPortMask_get + * Description: + * get system auto learn portmask + * Input: + * None + * Output: + * pPortmask - Port Mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Null pointer. + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8373_l2_limitSystemLearningCntPortMask_get(rtk_portmask_t *pPortmask); + + +/* Function Name: + * dal_rtl8367d_l2_learningCnt_get + * Description: + * Get per-Port current auto learning number + * Input: + * port - Port id. + * Output: + * pMac_cnt - ASIC auto learning entries number + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get per-port ASIC auto learning number + */ +extern rtk_api_ret_t dal_rtl8373_l2_learningCnt_get(rtk_port_t port, rtk_mac_cnt_t *pMac_cnt); + + +/* Function Name: + * dal_rtl8373_l2_ipMcastAddrLookup_set + * Description: + * Set Lut IP multicast lookup function + * Input: + * type - Lookup type for IPMC packet. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * LOOKUP_MAC - Lookup by MAC address + * LOOKUP_IP - Lookup by IP address + */ +extern rtk_api_ret_t dal_rtl8373_l2_ipMcastAddrLookup_set(rtk_l2_ipmc_lookup_type_t type); + + +/* Function Name: + * dal_rtl8373_l2_ipMcastAddrLookup_get + * Description: + * Get Lut IP multicast lookup function + * Input: + * None. + * Output: + * pType - Lookup type for IPMC packet. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * None. + */ +extern rtk_api_ret_t dal_rtl8373_l2_ipMcastAddrLookup_get(rtk_l2_ipmc_lookup_type_t *pType); + + + +/* Function Name: + * dal_rtl8373_l2_ipMcastGroupEntry_add + * Description: + * Add an IP Multicast entry to group table + * Input: + * ip_addr - IP address + * vid - VLAN ID + * pPortmask - portmask + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_TBL_FULL - Table Full + * Note: + * Add an entry to IP Multicast Group table. + */ +extern rtk_api_ret_t dal_rtl8373_l2_ipMcastGroupEntry_add(ipaddr_t ip_addr, rtk_portmask_t * portmask); + + +/* Function Name: + * dal_rtl8373_l2_ipMcastGroupEntry_del + * Description: + * Delete an entry from IP Multicast group table + * Input: + * ip_addr - IP address + * vid - VLAN ID + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_TBL_FULL - Table Full + * Note: + * Delete an entry from IP Multicast group table. + */ +extern rtk_api_ret_t dal_rtl8373_l2_ipMcastGroupEntry_del(ipaddr_t ip_addr); + + +/* Function Name: + * dal_rtl8373_l2_ipMcastGroupEntry_get + * Description: + * get an entry from IP Multicast group table + * Input: + * ip_addr - IP address + * vid - VLAN ID + * Output: + * pPortmask - member port mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_TBL_FULL - Table Full + * Note: + * Delete an entry from IP Multicast group table. + */ +extern rtk_api_ret_t dal_rtl8373_l2_ipMcastGroupEntry_get(ipaddr_t ip_addr, rtk_portmask_t *pPortmask); + + +/* Function Name: + * dal_rtl8373_l2_entry_get + * Description: + * Get LUT unicast entry. + * Input: + * pL2_entry - Index field in the structure. + * Output: + * pL2_entry - other fields such as MAC, port, age... + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_EMPTY_ENTRY - Empty LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API is used to get address by index from 0~2111. + */ +extern rtk_api_ret_t dal_rtl8373_l2_entry_get(rtk_l2_addr_table_t *pL2_entry); + + +extern rtk_api_ret_t dal_rtl8373_l2_entry_getNext(rtk_l2_addr_table_t *pL2_entry, rtk_uint32 method); + +/* Function Name: + * dal_rtl8373_l2_entry_del + * Description: + * Del LUT entry. + * Input: + * pL2_entry - Index field in the structure. + * Output: + * pL2_entry - other fields such as MAC, port, age... + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_EMPTY_ENTRY - Empty LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API is used to get address by index from 0~4096. + */ +extern rtk_api_ret_t dal_rtl8373_l2_entry_del(rtk_l2_addr_table_t *pL2_entry); + + + + +/* Function Name: + * dal_rtl8373_l2_lookupHitIsolationAction_set + * Description: + * Set action of lookup hit & isolation. + * Input: + * action - The action + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API is used to configure the action of packet which is lookup hit + * in L2 table but the destination port/portmask are not in the port isolation + * group. + */ +extern rtk_api_ret_t dal_rtl8373_l2_lookupHitIsolationAction_set(rtk_l2_lookupHitIsolationAction_t action); + + + + + +/* Function Name: + * dal_rtl8373_l2_lookupHitIsolationAction_get + * Description: + * Get action of lookup hit & isolation. + * Input: + * None. + * Output: + * pAction - The action + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API is used to get the action of packet which is lookup hit + * in L2 table but the destination port/portmask are not in the port isolation + * group. + */ +extern rtk_api_ret_t dal_rtl8373_l2_lookupHitIsolationAction_get(rtk_l2_lookupHitIsolationAction_t *pAction); + + +/* Function Name: + * dal_rtl8373_l2_portNewSaBehavior_set + * Description: + * Set UNSA behavior + * Input: + * port - port 0~9 + * behavior - 0: flooding; 1: drop; 2:trap + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid behavior + * Note: + * None + */ +extern ret_t dal_rtl8373_l2_portNewSaBehavior_set(rtk_uint32 port, rtk_uint32 behavior); + + +/* Function Name: + * dal_rtl8373_l2_portNewSaBehavior_get + * Description: + * Get UNSA behavior + * Input: + * port - port 0~9 + * pBehavior - 0: flooding; 1: drop; 2:trap + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +extern ret_t dal_rtl8373_l2_portNewSaBehavior_get(rtk_uint32 port, rtk_uint32 *pBehavior); + + +/* Function Name: + * dal_rtl8373_l2_portUnmatchedSaBehavior_set + * Description: + * Set Unmatched SA behavior + * Input: + * port - port 0~9 + * behavior - 0: flooding; 1: drop; 2:trap + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid behavior + * Note: + * None + */ +extern ret_t dal_rtl8373_l2_portUnmatchedSaBehavior_set(rtk_uint32 port, rtk_uint32 behavior); +/* Function Name: + * dal_rtl8373_l2_portUnmatchedSaBehavior_get + * Description: + * Get Unmatched SA behavior + * Input: + * port - port 0~9 + * pBehavior - 0: flooding; 1: drop; 2:trap + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +extern ret_t dal_rtl8373_l2_portUnmatchedSaBehavior_get(rtk_uint32 port, rtk_uint32 *pBehavior); + + + +/* Function Name: + * dal_rtl8373_l2_portSaMovingForbid_set + * Description: + * Set Unmatched SA moving state + * Input: + * port - Port ID + * enabled - 0: can't move to new port; 1: can move to new port + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Error Port ID + * Note: + * None + */ +extern ret_t dal_rtl8373_l2_portSaMovingForbid_set(rtk_uint32 port, rtk_uint32 forbid); + + +/* Function Name: + * dal_rtl8373_getAsicPortUnmatchedSaMoving + * Description: + * Get Unmatched SA moving state + * Input: + * port - Port ID + * Output: + * pEnabled - 0: can't move to new port; 1: can move to new port + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Error Port ID + * Note: + * None + */ +extern ret_t dal_rtl8373_l2_portSaMovingForbid_get(rtk_uint32 port, rtk_uint32 *pForbid); + + + +/* Function Name: + * dal_rtl8373_srcPortPermit_set + * Description: + * Set Unmatched SA moving state + * Input: + * port - Port ID + * enabled - 0: pkt cannot tx from rx port; 1: pkt can tx from rx port + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Error Port ID + * Note: + * None + */ +extern ret_t dal_rtl8373_srcPortPermit_set(rtk_uint32 port, rtk_uint32 enable); + + +/* Function Name: + * dal_rtl8373_srcPortPermit_get + * Description: + * Get Unmatched SA moving state + * Input: + * port - Port ID + * Output: + * pEnabled -0: pkt cannot tx from rx port; 1: pkt can tx from rx port + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Error Port ID + * Note: + * None + */ +extern ret_t dal_rtl8373_srcPortPermit_get(rtk_uint32 port, rtk_uint32 *pEnable); + + +/* Function Name: + * dal_rtl8373_l2_unknUc_fldMsk_set + * Description: + * Set unicast pkt lookup miss action + * Input: + * portmask - l2 unicast pkt lookup miss flood portmask + * Output: + * + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Error Port ID + * Note: + * None + */ +extern ret_t dal_rtl8373_l2_unknUc_fldMsk_set(rtk_uint32 portMask); + + + +/* Function Name: + * dal_rtl8373_l2_unknUc_fldMsk_get + * Description: + * get unicast pkt lookup miss action + * Input: + * portmask - l2 unicast pkt lookup miss flood portmask + * Output: + * + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Error Port ID + * Note: + * None + */ +extern ret_t dal_rtl8373_l2_unknUc_fldMsk_get(rtk_uint32* pMask); + + + +/* Function Name: + * dal_rtl8373_l2_unknUc_action_set + * Description: + * Set unicast pkt lookup miss action + * Input: + * port - Port ID * - 0b00:fwd in L2_UNKNOW_UC_FLD_PMSK 0b01 drop 0b10 trap 0b11 flood + * Output: + * + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Error Port ID + * Note: + * None + */extern ret_t dal_rtl8373_l2_unknUc_action_set(rtk_uint32 port, rtk_uint32 ); + + + + +/* Function Name: + * dal_rtl8373_l2_unknUc_action_get + * Description: + * Get unicast pkt lookup miss action + * Input: + * port - Port ID + * pAction - 0b00:fwd in L2_UNKNOW_UC_FLD_PMSK 0b01 drop 0b10 trap 0b11 flood + * Output: + * + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Error Port ID + * Note: + * None + */ +extern ret_t dal_rtl8373_l2_unknUc_action_get(rtk_uint32 port, rtk_uint32 *pAction); + + + +/* Function Name: + * dal_rtl8373_l2_unknMc_fldMsk_set + * Description: + * Set multicast pkt lookup miss action + * Input: + * portmask - l2 multicast pkt lookup miss flood portmask + * Output: + * + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Error Port ID + * Note: + * None + */ +extern ret_t dal_rtl8373_l2_unknMc_fldMsk_set(rtk_uint32 portMask); + + + +/* Function Name: + * dal_rtl8373_l2_unknMc_fldMsk_get + * Description: + * get multicast pkt lookup miss action + * Input: + * portmask - l2 multicast pkt lookup miss flood portmask + * Output: + * + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Error Port ID + * Note: + * None + */ +extern ret_t dal_rtl8373_l2_unknMc_fldMsk_get(rtk_uint32* pMask); + + + + +/* Function Name: + * dal_rtl8373_l2_unknMc_action_set + * Description: + * Set multicast pkt lookup miss action + * Input: + * port - Port ID * - 0b00:fwd in L2_UNKNOW_MC_FLD_PMSK 0b01 drop 0b10 trap 0b11 drop exclude RMA + * Output: + * + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Error Port ID + * Note: + * None + */extern ret_t dal_rtl8373_l2_unknMc_action_set(rtk_uint32 port, rtk_uint32 ); + + + + +/* Function Name: + * dal_rtl8373_l2_unknMc_action_get + * Description: + * Get multicast pkt lookup miss action + * Input: + * port - Port ID + * pAction - 0b00:fwd in L2_UNKNOW_MC_FLD_PMSK 0b01 drop 0b10 trap 0b11 drop exclude RMA + * Output: + * + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Error Port ID + * Note: + * None + */ +extern ret_t dal_rtl8373_l2_unknMc_action_get(rtk_uint32 port, rtk_uint32 *pAction); + + + + +/* Function Name: + * dal_rtl8373_l2_unknV4Mc_fldMsk_set + * Description: + * Set ipv4 multicast pkt lookup miss action + * Input: + * portmask - ipv4 multicast pkt lookup miss flood portmask + * Output: + * + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Error Port ID + * Note: + * None + */ +extern ret_t dal_rtl8373_l2_unknV4Mc_fldMsk_set(rtk_uint32 portMask); + + + +/* Function Name: + * dal_rtl8373_l2_unknV4Mc_fldMsk_get + * Description: + * get ipv4 multicast pkt lookup miss action + * Input: + * portmask - ipv4 multicast pkt lookup miss flood portmask + * Output: + * + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Error Port ID + * Note: + * None + */ +extern ret_t dal_rtl8373_l2_unknV4Mc_fldMsk_get(rtk_uint32* pMask); + + + + + + +/* Function Name: + * dal_rtl8373_l2_unknV4Mc_action_set + * Description: + * Set ipv4 multicast pkt lookup miss action + * Input: + * port - Port ID * - 0b00:fwd in IPV4_UNKNOW_MC_FLD_PMSK 0b01 drop 0b10 trap 0b11 to router port + * Output: + * + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Error Port ID + * Note: + * None + */extern ret_t dal_rtl8373_l2_unknV4Mc_action_set(rtk_uint32 port, rtk_uint32 ); + + + +/* Function Name: + * dal_rtl8373_l2_unknV4Mc_action_get + * Description: + * Get ipv4 multicast pkt lookup miss action + * Input: + * port - Port ID + * pAction - 0b00:fwd in IPV4_UNKNOW_MC_FLD_PMSK 0b01 drop 0b10 trap 0b11 to router port + * Output: + * + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Error Port ID + * Note: + * None + */ +extern ret_t dal_rtl8373_l2_unknV4Mc_action_get(rtk_uint32 port, rtk_uint32 *pAction); + + + +/* Function Name: + * dal_rtl8373_l2_unknV6Mc_fldMsk_set + * Description: + * Set ipv6 multicast pkt lookup miss action + * Input: + * portmask - ipv6 multicast pkt lookup miss flood portmask + * Output: + * + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Error Port ID + * Note: + * None + */ +extern ret_t dal_rtl8373_l2_unknV6Mc_fldMsk_set(rtk_uint32 portMask); + + +/* Function Name: + * dal_rtl8373_l2_unknV6Mc_fldMsk_get + * Description: + * get ipv6 multicast pkt lookup miss action + * Input: + * portmask - ipv6 multicast pkt lookup miss flood portmask + * Output: + * + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Error Port ID + * Note: + * None + */ +extern ret_t dal_rtl8373_l2_unknV6Mc_fldMsk_get(rtk_uint32* pMask); + + +/* Function Name: + * dal_rtl8373_l2_unknV6Mc_action_set + * Description: + * Set ipv6 multicast pkt lookup miss action + * Input: + * port - Port ID * - 0b00:fwd in IPV6_UNKNOW_MC_FLD_PMSK 0b01 drop 0b10 trap 0b11 to router port + * Output: + * + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Error Port ID + * Note: + * None + */extern ret_t dal_rtl8373_l2_unknV6Mc_action_set(rtk_uint32 port, rtk_uint32 ); + + +/* Function Name: + * dal_rtl8373_l2_unknV6Mc_action_get + * Description: + * Get ipv6 multicast pkt lookup miss action + * Input: + * port - Port ID + * pAction - 0b00:fwd in IPV6_UNKNOW_MC_FLD_PMSK 0b01 drop 0b10 trap 0b11 to router port + * Output: + * + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Error Port ID + * Note: + * None + */ +extern ret_t dal_rtl8373_l2_unknV6Mc_action_get(rtk_uint32 port, rtk_uint32 *pAction); + +/* Function Name: + * dal_rtl8373_l2_brdcast_fldMsk_set + * Description: + * set brdcast pkt flood port mask + * Input: + * portMask - brdcast pkt flood port mask + * Output: + * + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Error Port ID + * Note: + * None + */ +extern ret_t dal_rtl8373_l2_brdcast_fldMsk_set(rtk_uint32 portMask); + +/* Function Name: + * dal_rtl8373_l2_brdcast_fldMsk_get + * Description: + * get brdcast pkt flood port mask + * Input: + * pMask - brdcast pkt flood port mask + * Output: + * + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Error Port ID + * Note: + * None + */ +extern ret_t dal_rtl8373_l2_brdcast_fldMsk_get(rtk_uint32* pMask); + + +/* Function Name: + * dal_rtl8373_l2_trapPort_set + * Description: + * set l2 trap cpu port mask + * Input: + * trapport - 0b00 none 0b01:8051 0b10:external cpu 0b11: 8051&external + * Output: + * + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ + +extern rtk_api_ret_t dal_rtl8373_l2_trapPort_set(rtk_uint32 trapport); + + +/* Function Name: + * dal_rtl8373_l2_trapPort_Get + * Description: + * get l2 trap cpu port mask + * Input: + * trapport - 0b00 none 0b01:8051 0b10:external cpu 0b11: 8051&external + * Output: + * + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ + +extern rtk_api_ret_t dal_rtl8373_l2_trapPort_get(rtk_uint32 * pTrapport); + + + +/* Function Name: + * dal_rtl8373_l2_hashFull_set + * Description: + * set l2 hsah full acti + * Input: + * act - 0b00 fwd 0b01:drop 0b10:trap + * Output: + * + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ + +extern rtk_api_ret_t dal_rtl8373_l2_hashFull_set(rtk_uint32 act); + + +/* Function Name: + * dal_rtl8373_l2_hashFull_get + * Description: + * get l2 hsah full acti + * Input: + * pAct - 0b00 fwd 0b01:drop 0b10:trap + * Output: + * + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ + +extern rtk_api_ret_t dal_rtl8373_l2_hashFull_get(rtk_uint32* pAct); + + +/* Function Name: + * dal_rtl8373_l2_ipMul_noVlanEgr_set + * Description: + * set ipmulticast bypass vlanegress filter + * Input: + * port - port number + * enable - 0 disable vlan egress filter 1 enable vlan egress filter + * Output: + * + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ + +extern rtk_api_ret_t dal_rtl8373_l2_ipMul_noVlanEgr_set(rtk_uint32 port, rtk_uint32 enable); + + +/* Function Name: + * dal_rtl8373_l2_ipMul_noVlanEgr_get + * Description: + * get ipmulticast bypass vlanegress filter + * Input: + * port - port number + * pEnable - 0 disable vlan egress filter 1 enable vlan egress filter + * Output: + * + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ + +extern rtk_api_ret_t dal_rtl8373_l2_ipMul_noVlanEgr_get(rtk_uint32 port, rtk_uint32* pEnable); + + +/* Function Name: + * dal_rtl8373_l2_ipMul_noPortIso_set + * Description: + * set ipmulticast bypass port isolation filter + * Input: + * port - port number + * enable - 0 disable port isolation filter 1 enable port isolation filter + * Output: + * + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ + +extern rtk_api_ret_t dal_rtl8373_l2_ipMul_noPortIso_set(rtk_uint32 port, rtk_uint32 enable); + + +/* Function Name: + * dal_rtl8373_l2_ipMul_noPortIso_get + * Description: + * get ipmulticast bypass port isolation filter + * Input: + * port - port number + * pEnable - 0 disable port isolation filter 1 enable port isolation filter + * Output: + * + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ + +extern rtk_api_ret_t dal_rtl8373_l2_ipMul_noPortIso_get(rtk_uint32 port, rtk_uint32* pEnable); + + +/* Function Name: + * dal_rtl8373_l2_forceMode_set + * Description: + * set l2 force mode + * Input: + * port - port number + * enable - 0 disable port force mode 1 enable port force mode + * Output: + * + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ + +extern rtk_api_ret_t dal_rtl8373_l2_forceMode_set(rtk_uint32 port, rtk_uint32 enable); + + +/* Function Name: + * dal_rtl8373_l2_forceMode_get + * Description: + * get l2 force mode + * Input: + * port - port number + * enable - 0 disable port force mode 1 enable port force mode + * Output: + * + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ + +extern rtk_api_ret_t dal_rtl8373_l2_forceMode_get(rtk_uint32 port, rtk_uint32* pEnable); + + +/* Function Name: + * dal_rtl8373_l2_forceMode_portMsk_set + * Description: + * set l2 force mode + * Input: + * port - port number + * portmask - port mask + * Output: + * + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ + +extern rtk_api_ret_t dal_rtl8373_l2_forceMode_portMsk_set(rtk_uint32 port, rtk_uint32 portmask); + +/* Function Name: + * dal_rtl8373_l2_forceMode_portMsk_get + * Description: + * get l2 force mode + * Input: + * port - port number + * portmask - port mask + * Output: + * + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ + +extern rtk_api_ret_t dal_rtl8373_l2_forceMode_portMsk_get(rtk_uint32 port, rtk_uint32* pMask); + + + +/* Function Name: + * dal_rtl8373_l2_entry_del + * Description: + * Get LUT entry. + * Input: + * pL2_entry - Index field in the structure. + * Output: + * pL2_entry - other fields such as MAC, port, age... + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_EMPTY_ENTRY - Empty LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API is used to get address by index from 0~2111. + */ +extern rtk_api_ret_t dal_rtl8373_l2_entry_del(rtk_l2_addr_table_t *pL2_entry); + + + + + +/* Function Name: + * dal_rtl8373_l2_trapPri_set + * Description: + * set l2 trap cpu port mask + * Input: + * type - 0: normal pkt 1: multicast + * trappri - trap priority + * Output: + * + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ + +extern rtk_api_ret_t dal_rtl8373_l2_trapPri_set(rtk_uint32 type, rtk_uint32 trappri); + + + +/* Function Name: + * dal_rtl8373_l2_trapPri_get + * Description: + * set l2 trap cpu port mask + * Input: + * type - 0: normal pkt 1: multicast + * pTrappri - trap priority + * Output: + * + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ + +extern rtk_api_ret_t dal_rtl8373_l2_trapPri_get(rtk_uint32 type, rtk_uint32* pTrappri); + + + +/* Function Name: + * dal_rtl8373_l2_floodPortMsk_set + * Description: + * set flood portmask + * Input: + * flood_type - unknown unicast, unknown l2 multicast, unknown IPV4 multicast, unknown IPV6 multicast, broadcast + * pFlood_portmask - port mask + * Output: + * + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ + +extern rtk_api_ret_t dal_rtl8373_l2_floodPortMsk_set(rtk_l2_flood_type_t flood_type, rtk_portmask_t *pFlood_portmask); + + + + + +/* Function Name: + * dal_rtl8373_l2_floodPortMsk_get + * Description: + * Get flood portmask + * Input: + * flood_type - unknown unicast, unknown l2 multicast, unknown IPV4 multicast, unknown IPV6 multicast, broadcast + * pFlood_portmask - port mask + * Output: + * + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ + +extern rtk_api_ret_t dal_rtl8373_l2_floodPortMsk_get(rtk_l2_flood_type_t flood_type, rtk_portmask_t *pFlood_portmask); + + + + + + + + + + + + +#endif + diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_macsec.c b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_macsec.c new file mode 100755 index 00000000..a5a1fce6 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_macsec.c @@ -0,0 +1,3767 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8373 + * Feature : Here is a list of all functions and variables in LUT module. + * + */ + +#include +#include +#include +#include +#include +#include +#include + +/* Function Name: + * dal_rtl8373_macsec_enable_set + * Description: + * Configure macsec enable. + * Input: + * port - port id + * ingress_en - ingress enable + * egress_en - egress enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure macsec enable. + */ +rtk_api_ret_t dal_rtl8373_macsec_enable_set(rtk_uint32 port, rtk_uint32 ingress_en, rtk_uint32 egress_en) +{ + rtk_api_ret_t retVal; + + if(port == 0) + { + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_PM_CTRL_PORT4_ADDR, RTL8373_MACSEC_PM_CTRL_PORT4_MACSEC_TX_ICG_EN_OFFSET, egress_en)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_PM_CTRL_PORT4_ADDR, RTL8373_MACSEC_PM_CTRL_PORT4_MACSEC_RX_ICG_EN_OFFSET, ingress_en)) != RT_ERR_OK) + return retVal; + } + else if(port == 1) + { + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_PM_CTRL_PORT5_ADDR, RTL8373_MACSEC_PM_CTRL_PORT5_MACSEC_TX_ICG_EN_OFFSET, egress_en)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_PM_CTRL_PORT5_ADDR, RTL8373_MACSEC_PM_CTRL_PORT5_MACSEC_RX_ICG_EN_OFFSET, ingress_en)) != RT_ERR_OK) + return retVal; + } + else if(port == 2) + { + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_PM_CTRL_PORT6_ADDR, RTL8373_MACSEC_PM_CTRL_PORT6_MACSEC_TX_ICG_EN_OFFSET, egress_en)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_PM_CTRL_PORT6_ADDR, RTL8373_MACSEC_PM_CTRL_PORT6_MACSEC_RX_ICG_EN_OFFSET, ingress_en)) != RT_ERR_OK) + return retVal; + } + else if(port == 3) + { + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_PM_CTRL_PORT7_ADDR, RTL8373_MACSEC_PM_CTRL_PORT7_MACSEC_TX_ICG_EN_OFFSET, egress_en)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_PM_CTRL_PORT7_ADDR, RTL8373_MACSEC_PM_CTRL_PORT7_MACSEC_RX_ICG_EN_OFFSET, ingress_en)) != RT_ERR_OK) + return retVal; + } + + else if(port == 4) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_PM_CTRL_PORT4_ADDR, RTL8373_MACSEC_PM_CTRL_PORT4_MACSEC_TX_ICG_EN_OFFSET, egress_en)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_PM_CTRL_PORT4_ADDR, RTL8373_MACSEC_PM_CTRL_PORT4_MACSEC_RX_ICG_EN_OFFSET, ingress_en)) != RT_ERR_OK) + return retVal; + } + else if(port == 5) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_PM_CTRL_PORT5_ADDR, RTL8373_MACSEC_PM_CTRL_PORT5_MACSEC_TX_ICG_EN_OFFSET, egress_en)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_PM_CTRL_PORT5_ADDR, RTL8373_MACSEC_PM_CTRL_PORT5_MACSEC_RX_ICG_EN_OFFSET, ingress_en)) != RT_ERR_OK) + return retVal; + } + else if(port == 6) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_PM_CTRL_PORT6_ADDR, RTL8373_MACSEC_PM_CTRL_PORT6_MACSEC_TX_ICG_EN_OFFSET, egress_en)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_PM_CTRL_PORT6_ADDR, RTL8373_MACSEC_PM_CTRL_PORT6_MACSEC_RX_ICG_EN_OFFSET, ingress_en)) != RT_ERR_OK) + return retVal; + } + else if(port == 7) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_PM_CTRL_PORT7_ADDR, RTL8373_MACSEC_PM_CTRL_PORT7_MACSEC_TX_ICG_EN_OFFSET, egress_en)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_PM_CTRL_PORT7_ADDR, RTL8373_MACSEC_PM_CTRL_PORT7_MACSEC_RX_ICG_EN_OFFSET, ingress_en)) != RT_ERR_OK) + return retVal; + } + else + return RT_ERR_INPUT; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_macsec_enable_get + * Description: + * get macsec enable status. + * Input: + * port - port id + * Output: + * ingress_en - ingress enable + * egress_en - egress enable + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will get macsec enable status. + */ +rtk_api_ret_t dal_rtl8373_macsec_enable_get(rtk_uint32 port, rtk_uint32 *ingress_en, rtk_uint32 *egress_en) +{ + rtk_api_ret_t retVal; + + if(port == 0) + { + if ((retVal = dal_rtl8224_top_regbit_read(RTL8373_MACSEC_PM_CTRL_PORT4_ADDR, RTL8373_MACSEC_PM_CTRL_PORT4_MACSEC_TX_ICG_EN_OFFSET, egress_en)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_regbit_read(RTL8373_MACSEC_PM_CTRL_PORT4_ADDR, RTL8373_MACSEC_PM_CTRL_PORT4_MACSEC_RX_ICG_EN_OFFSET, ingress_en)) != RT_ERR_OK) + return retVal; + } + else if(port == 1) + { + if ((retVal = dal_rtl8224_top_regbit_read(RTL8373_MACSEC_PM_CTRL_PORT5_ADDR, RTL8373_MACSEC_PM_CTRL_PORT5_MACSEC_TX_ICG_EN_OFFSET, egress_en)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_regbit_read(RTL8373_MACSEC_PM_CTRL_PORT5_ADDR, RTL8373_MACSEC_PM_CTRL_PORT5_MACSEC_RX_ICG_EN_OFFSET, ingress_en)) != RT_ERR_OK) + return retVal; + } + else if(port == 2) + { + if ((retVal = dal_rtl8224_top_regbit_read(RTL8373_MACSEC_PM_CTRL_PORT6_ADDR, RTL8373_MACSEC_PM_CTRL_PORT6_MACSEC_TX_ICG_EN_OFFSET, egress_en)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_regbit_read(RTL8373_MACSEC_PM_CTRL_PORT6_ADDR, RTL8373_MACSEC_PM_CTRL_PORT6_MACSEC_RX_ICG_EN_OFFSET, ingress_en)) != RT_ERR_OK) + return retVal; + } + else if(port == 3) + { + if ((retVal = dal_rtl8224_top_regbit_read(RTL8373_MACSEC_PM_CTRL_PORT7_ADDR, RTL8373_MACSEC_PM_CTRL_PORT7_MACSEC_TX_ICG_EN_OFFSET, egress_en)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_regbit_read(RTL8373_MACSEC_PM_CTRL_PORT7_ADDR, RTL8373_MACSEC_PM_CTRL_PORT7_MACSEC_RX_ICG_EN_OFFSET, ingress_en)) != RT_ERR_OK) + return retVal; + } + else if(port == 4) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_MACSEC_PM_CTRL_PORT4_ADDR, RTL8373_MACSEC_PM_CTRL_PORT4_MACSEC_TX_ICG_EN_OFFSET, egress_en)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_getAsicRegBit(RTL8373_MACSEC_PM_CTRL_PORT4_ADDR, RTL8373_MACSEC_PM_CTRL_PORT4_MACSEC_RX_ICG_EN_OFFSET, ingress_en)) != RT_ERR_OK) + return retVal; + } + else if(port == 5) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_MACSEC_PM_CTRL_PORT5_ADDR, RTL8373_MACSEC_PM_CTRL_PORT5_MACSEC_TX_ICG_EN_OFFSET, egress_en)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_getAsicRegBit(RTL8373_MACSEC_PM_CTRL_PORT5_ADDR, RTL8373_MACSEC_PM_CTRL_PORT5_MACSEC_RX_ICG_EN_OFFSET, ingress_en)) != RT_ERR_OK) + return retVal; + } + else if(port == 6) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_MACSEC_PM_CTRL_PORT6_ADDR, RTL8373_MACSEC_PM_CTRL_PORT6_MACSEC_TX_ICG_EN_OFFSET, egress_en)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_getAsicRegBit(RTL8373_MACSEC_PM_CTRL_PORT6_ADDR, RTL8373_MACSEC_PM_CTRL_PORT6_MACSEC_RX_ICG_EN_OFFSET, ingress_en)) != RT_ERR_OK) + return retVal; + } + else if(port == 7) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_MACSEC_PM_CTRL_PORT7_ADDR, RTL8373_MACSEC_PM_CTRL_PORT7_MACSEC_TX_ICG_EN_OFFSET, egress_en)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_getAsicRegBit(RTL8373_MACSEC_PM_CTRL_PORT7_ADDR, RTL8373_MACSEC_PM_CTRL_PORT7_MACSEC_RX_ICG_EN_OFFSET, ingress_en)) != RT_ERR_OK) + return retVal; + } + else + return RT_ERR_INPUT; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_macsec_reset + * Description: + * reset macsec ip. + * Input: + * port - port id + * ingress_rst - ingress reset + * egress_rst - egress reset + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will reset macsec. + */ +rtk_api_ret_t dal_rtl8373_macsec_reset(rtk_uint32 port, rtk_uint32 ingress_rst, rtk_uint32 egress_rst) +{ + rtk_api_ret_t retVal; + + if(port == 0) + { + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_REG_GLB_SET1_PORT4_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT4_TX_IPRST_N_OFFSET, egress_rst)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_REG_GLB_SET1_PORT4_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT4_RX_IPRST_N_OFFSET, ingress_rst)) != RT_ERR_OK) + return retVal; + } + else if(port == 1) + { + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_REG_GLB_SET1_PORT5_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT5_TX_IPRST_N_OFFSET, egress_rst)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_REG_GLB_SET1_PORT5_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT5_RX_IPRST_N_OFFSET, ingress_rst)) != RT_ERR_OK) + return retVal; + } + else if(port == 2) + { + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_REG_GLB_SET1_PORT6_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT6_TX_IPRST_N_OFFSET, egress_rst)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_REG_GLB_SET1_PORT6_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT6_RX_IPRST_N_OFFSET, ingress_rst)) != RT_ERR_OK) + return retVal; + } + else if(port == 3) + { + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_REG_GLB_SET1_PORT7_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT7_TX_IPRST_N_OFFSET, egress_rst)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_REG_GLB_SET1_PORT7_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT7_RX_IPRST_N_OFFSET, ingress_rst)) != RT_ERR_OK) + return retVal; + } + else if(port == 4) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_REG_GLB_SET1_PORT4_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT4_TX_IPRST_N_OFFSET, egress_rst)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_REG_GLB_SET1_PORT4_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT4_RX_IPRST_N_OFFSET, ingress_rst)) != RT_ERR_OK) + return retVal; + } + else if(port == 5) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_REG_GLB_SET1_PORT5_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT5_TX_IPRST_N_OFFSET, egress_rst)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_REG_GLB_SET1_PORT5_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT5_RX_IPRST_N_OFFSET, ingress_rst)) != RT_ERR_OK) + return retVal; + } + else if(port == 6) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_REG_GLB_SET1_PORT6_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT6_TX_IPRST_N_OFFSET, egress_rst)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_REG_GLB_SET1_PORT6_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT6_RX_IPRST_N_OFFSET, ingress_rst)) != RT_ERR_OK) + return retVal; + } + else if(port == 7) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_REG_GLB_SET1_PORT7_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT7_TX_IPRST_N_OFFSET, egress_rst)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_REG_GLB_SET1_PORT7_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT7_RX_IPRST_N_OFFSET, ingress_rst)) != RT_ERR_OK) + return retVal; + } + else + return RT_ERR_INPUT; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_macsec_egress_set + * Description: + * Configure macsec egress rule. + * Input: + * port - port id + * addr - macsec ip core register address + * value - data for rule + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure macsec egress rule:SA match rule, flow control register and transform record. + */ +rtk_api_ret_t dal_rtl8373_macsec_egress_set(rtk_uint32 port, rtk_uint32 addr, rtk_uint32 value) +{ + rtk_api_ret_t retVal; + rtk_uint32 phy_data; + + if(port == 0) + { +#if 1 //pending + if ((retVal = dal_rtl8373_phy_read(0, 7, 1, &phy_data)) != RT_ERR_OK) + return retVal; + + if(((phy_data >> 2) & 0x1) != 1) + return RT_ERR_PHY_LINK_DOWN; +#endif + if ((retVal = dal_rtl8224_top_regbits_write(RTL8373_MACSEC_REG_ADDR_AE_PORT4_ADDR, RTL8373_MACSEC_REG_ADDR_AE_PORT4_REG_ADDR_AE_MASK, addr)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_regbits_write(RTL8373_MACSEC_REG_RWDH_AE_PORT4_ADDR, RTL8373_MACSEC_REG_RWDH_AE_PORT4_REG_DATA_AE_L_MASK, value & 0xffff)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_regbits_write(RTL8373_MACSEC_REG_RWDH_AE_PORT4_ADDR, RTL8373_MACSEC_REG_RWDH_AE_PORT4_REG_DATA_AE_H_MASK, (value >> 16) & 0xffff)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_REG_CMD_AE_PORT4_ADDR, RTL8373_MACSEC_REG_CMD_AE_PORT4_REG_WR_REQ_AE_OFFSET, 1)) != RT_ERR_OK) + return retVal; + } + else if(port == 1) + { +#if 1 //pending + if ((retVal = dal_rtl8373_phy_read(1, 7, 1, &phy_data)) != RT_ERR_OK) + return retVal; + + if(((phy_data >> 2) & 0x1) != 1) + return RT_ERR_PHY_LINK_DOWN; +#endif + if ((retVal = dal_rtl8224_top_regbits_write(RTL8373_MACSEC_REG_RWDH_AE_PORT5_ADDR, RTL8373_MACSEC_REG_RWDH_AE_PORT5_REG_DATA_AE_L_MASK, value & 0xffff)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_regbits_write(RTL8373_MACSEC_REG_RWDH_AE_PORT5_ADDR, RTL8373_MACSEC_REG_RWDH_AE_PORT5_REG_DATA_AE_H_MASK, (value >> 16) & 0xffff)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_regbits_write(RTL8373_MACSEC_REG_ADDR_AE_PORT5_ADDR, RTL8373_MACSEC_REG_ADDR_AE_PORT5_REG_ADDR_AE_MASK, addr)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_REG_CMD_AE_PORT5_ADDR, RTL8373_MACSEC_REG_CMD_AE_PORT5_REG_WR_REQ_AE_OFFSET, 1)) != RT_ERR_OK) + return retVal; + } + else if(port == 2) + { + if ((retVal = dal_rtl8373_phy_read(2, 7, 1, &phy_data)) != RT_ERR_OK) + return retVal; + + if(((phy_data >> 2) & 0x1) != 1) + return RT_ERR_PHY_LINK_DOWN; + + if ((retVal = dal_rtl8224_top_regbits_write(RTL8373_MACSEC_REG_RWDH_AE_PORT6_ADDR, RTL8373_MACSEC_REG_RWDH_AE_PORT6_REG_DATA_AE_L_MASK, value & 0xffff)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_regbits_write(RTL8373_MACSEC_REG_RWDH_AE_PORT6_ADDR, RTL8373_MACSEC_REG_RWDH_AE_PORT6_REG_DATA_AE_H_MASK, (value >> 16) & 0xffff)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_regbits_write(RTL8373_MACSEC_REG_ADDR_AE_PORT6_ADDR, RTL8373_MACSEC_REG_ADDR_AE_PORT6_REG_ADDR_AE_MASK, addr)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_REG_CMD_AE_PORT6_ADDR, RTL8373_MACSEC_REG_CMD_AE_PORT6_REG_WR_REQ_AE_OFFSET, 1)) != RT_ERR_OK) + return retVal; + } + else if(port == 3) + { + if ((retVal = dal_rtl8373_phy_read(3, 7, 1, &phy_data)) != RT_ERR_OK) + return retVal; + + if(((phy_data >> 2) & 0x1) != 1) + return RT_ERR_PHY_LINK_DOWN; + + if ((retVal = dal_rtl8224_top_regbits_write(RTL8373_MACSEC_REG_RWDH_AE_PORT7_ADDR, RTL8373_MACSEC_REG_RWDH_AE_PORT7_REG_DATA_AE_L_MASK, value & 0xffff)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_regbits_write(RTL8373_MACSEC_REG_RWDH_AE_PORT7_ADDR, RTL8373_MACSEC_REG_RWDH_AE_PORT7_REG_DATA_AE_H_MASK, (value >> 16) & 0xffff)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_regbits_write(RTL8373_MACSEC_REG_ADDR_AE_PORT7_ADDR, RTL8373_MACSEC_REG_ADDR_AE_PORT7_REG_ADDR_AE_MASK, addr)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_REG_CMD_AE_PORT7_ADDR, RTL8373_MACSEC_REG_CMD_AE_PORT7_REG_WR_REQ_AE_OFFSET, 1)) != RT_ERR_OK) + return retVal; + } + else if(port == 4) + { + if ((retVal = dal_rtl8373_phy_read(4, 7, 1, &phy_data)) != RT_ERR_OK) + return retVal; + + if(((phy_data >> 2) & 0x1) != 1) + return RT_ERR_PHY_LINK_DOWN; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_MACSEC_REG_ADDR_AE_PORT4_ADDR, RTL8373_MACSEC_REG_ADDR_AE_PORT4_REG_ADDR_AE_MASK, addr)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_MACSEC_REG_RWDH_AE_PORT4_ADDR, RTL8373_MACSEC_REG_RWDH_AE_PORT4_REG_DATA_AE_L_MASK, value & 0xffff)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_MACSEC_REG_RWDH_AE_PORT4_ADDR, RTL8373_MACSEC_REG_RWDH_AE_PORT4_REG_DATA_AE_H_MASK, (value >> 16) & 0xffff)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_REG_CMD_AE_PORT4_ADDR, RTL8373_MACSEC_REG_CMD_AE_PORT4_REG_WR_REQ_AE_OFFSET, 1)) != RT_ERR_OK) + return retVal; + } + else if(port == 5) + { + if ((retVal = dal_rtl8373_phy_read(5, 7, 1, &phy_data)) != RT_ERR_OK) + return retVal; + + if(((phy_data >> 2) & 0x1) != 1) + return RT_ERR_PHY_LINK_DOWN; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_MACSEC_REG_RWDH_AE_PORT5_ADDR, RTL8373_MACSEC_REG_RWDH_AE_PORT5_REG_DATA_AE_L_MASK, value & 0xffff)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_MACSEC_REG_RWDH_AE_PORT5_ADDR, RTL8373_MACSEC_REG_RWDH_AE_PORT5_REG_DATA_AE_H_MASK, (value >> 16) & 0xffff)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_MACSEC_REG_ADDR_AE_PORT5_ADDR, RTL8373_MACSEC_REG_ADDR_AE_PORT5_REG_ADDR_AE_MASK, addr)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_REG_CMD_AE_PORT5_ADDR, RTL8373_MACSEC_REG_CMD_AE_PORT5_REG_WR_REQ_AE_OFFSET, 1)) != RT_ERR_OK) + return retVal; + } + else if(port == 6) + { + if ((retVal = dal_rtl8373_phy_read(6, 7, 1, &phy_data)) != RT_ERR_OK) + return retVal; + + if(((phy_data >> 2) & 0x1) != 1) + return RT_ERR_PHY_LINK_DOWN; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_MACSEC_REG_RWDH_AE_PORT6_ADDR, RTL8373_MACSEC_REG_RWDH_AE_PORT6_REG_DATA_AE_L_MASK, value & 0xffff)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_MACSEC_REG_RWDH_AE_PORT6_ADDR, RTL8373_MACSEC_REG_RWDH_AE_PORT6_REG_DATA_AE_H_MASK, (value >> 16) & 0xffff)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_MACSEC_REG_ADDR_AE_PORT6_ADDR, RTL8373_MACSEC_REG_ADDR_AE_PORT6_REG_ADDR_AE_MASK, addr)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_REG_CMD_AE_PORT6_ADDR, RTL8373_MACSEC_REG_CMD_AE_PORT6_REG_WR_REQ_AE_OFFSET, 1)) != RT_ERR_OK) + return retVal; + } + else if(port == 7) + { + if ((retVal = dal_rtl8373_phy_read(7, 7, 1, &phy_data)) != RT_ERR_OK) + return retVal; + + if(((phy_data >> 2) & 0x1) != 1) + return RT_ERR_PHY_LINK_DOWN; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_MACSEC_REG_RWDH_AE_PORT7_ADDR, RTL8373_MACSEC_REG_RWDH_AE_PORT7_REG_DATA_AE_L_MASK, value & 0xffff)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_MACSEC_REG_RWDH_AE_PORT7_ADDR, RTL8373_MACSEC_REG_RWDH_AE_PORT7_REG_DATA_AE_H_MASK, (value >> 16) & 0xffff)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_MACSEC_REG_ADDR_AE_PORT7_ADDR, RTL8373_MACSEC_REG_ADDR_AE_PORT7_REG_ADDR_AE_MASK, addr)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_REG_CMD_AE_PORT7_ADDR, RTL8373_MACSEC_REG_CMD_AE_PORT7_REG_WR_REQ_AE_OFFSET, 1)) != RT_ERR_OK) + return retVal; + } + else + return RT_ERR_INPUT; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_macsec_egress_get + * Description: + * get macsec egress rule. + * Input: + * port - port id + * addr - macsec ip core register address + * Output: + * value - data for rule + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will get macsec egress rule:SA match rule, flow control register and transform record. + */ +rtk_api_ret_t dal_rtl8373_macsec_egress_get(rtk_uint32 port, rtk_uint32 addr, rtk_uint32 *value) +{ + rtk_api_ret_t retVal; + rtk_uint32 phy_data,tmp; + + if(port == 0) + { +#if 1 //pending + + if ((retVal = dal_rtl8373_phy_read(0, 7, 1, &phy_data)) != RT_ERR_OK) + return retVal; + + if(((phy_data >> 2) & 0x1) != 1) + return RT_ERR_PHY_LINK_DOWN; +#endif + + if ((retVal = dal_rtl8224_top_regbits_write(RTL8373_MACSEC_REG_ADDR_AE_PORT4_ADDR, RTL8373_MACSEC_REG_ADDR_AE_PORT4_REG_ADDR_AE_MASK, addr)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_REG_CMD_AE_PORT4_ADDR, RTL8373_MACSEC_REG_CMD_AE_PORT4_REG_RD_REQ_AE_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_reg_read(RTL8373_MACSEC_REG_RWDH_AE_PORT4_ADDR, &tmp)) != RT_ERR_OK) + return retVal; + //printk("4\n"); + *value = ((tmp >> 16) & 0xffff) | ((tmp & 0xffff) << 16); + } + else if(port == 1) + { +#if 1 //pending + + if ((retVal = dal_rtl8373_phy_read(1, 7, 1, &phy_data)) != RT_ERR_OK) + return retVal; + + if(((phy_data >> 2) & 0x1) != 1) + return RT_ERR_PHY_LINK_DOWN; +#endif + if ((retVal = dal_rtl8224_top_regbits_write(RTL8373_MACSEC_REG_ADDR_AE_PORT5_ADDR, RTL8373_MACSEC_REG_ADDR_AE_PORT5_REG_ADDR_AE_MASK, addr)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_REG_CMD_AE_PORT5_ADDR, RTL8373_MACSEC_REG_CMD_AE_PORT5_REG_RD_REQ_AE_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_reg_read(RTL8373_MACSEC_REG_RWDH_AE_PORT5_ADDR, &tmp)) != RT_ERR_OK) + return retVal; + + *value = ((tmp >> 16) & 0xffff) | ((tmp & 0xffff) << 16); + } + else if(port == 2) + { + if ((retVal = dal_rtl8373_phy_read(2, 7, 1, &phy_data)) != RT_ERR_OK) + return retVal; + + if(((phy_data >> 2) & 0x1) != 1) + return RT_ERR_PHY_LINK_DOWN; + + if ((retVal = dal_rtl8224_top_regbits_write(RTL8373_MACSEC_REG_ADDR_AE_PORT6_ADDR, RTL8373_MACSEC_REG_ADDR_AE_PORT6_REG_ADDR_AE_MASK, addr)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_REG_CMD_AE_PORT6_ADDR, RTL8373_MACSEC_REG_CMD_AE_PORT6_REG_RD_REQ_AE_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_reg_read(RTL8373_MACSEC_REG_RWDH_AE_PORT6_ADDR, &tmp)) != RT_ERR_OK) + return retVal; + + *value = ((tmp >> 16) & 0xffff) | ((tmp & 0xffff) << 16); + } + else if(port == 3) + { + if ((retVal = dal_rtl8373_phy_read(3, 7, 1, &phy_data)) != RT_ERR_OK) + return retVal; + + if(((phy_data >> 2) & 0x1) != 1) + return RT_ERR_PHY_LINK_DOWN; + + if ((retVal = dal_rtl8224_top_regbits_write(RTL8373_MACSEC_REG_ADDR_AE_PORT7_ADDR, RTL8373_MACSEC_REG_ADDR_AE_PORT7_REG_ADDR_AE_MASK, addr)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_REG_CMD_AE_PORT7_ADDR, RTL8373_MACSEC_REG_CMD_AE_PORT7_REG_RD_REQ_AE_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_reg_read(RTL8373_MACSEC_REG_RWDH_AE_PORT7_ADDR, &tmp)) != RT_ERR_OK) + return retVal; + + *value = ((tmp >> 16) & 0xffff) | ((tmp & 0xffff) << 16); + } + else if(port == 4) + { + if ((retVal = dal_rtl8373_phy_read(4, 7, 1, &phy_data)) != RT_ERR_OK) + return retVal; + + if(((phy_data >> 2) & 0x1) != 1) + return RT_ERR_PHY_LINK_DOWN; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_MACSEC_REG_ADDR_AE_PORT4_ADDR, RTL8373_MACSEC_REG_ADDR_AE_PORT4_REG_ADDR_AE_MASK, addr)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_REG_CMD_AE_PORT4_ADDR, RTL8373_MACSEC_REG_CMD_AE_PORT4_REG_RD_REQ_AE_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_getAsicReg(RTL8373_MACSEC_REG_RWDH_AE_PORT4_ADDR, &tmp)) != RT_ERR_OK) + return retVal; + + *value = ((tmp >> 16) & 0xffff) | ((tmp & 0xffff) << 16); + } + else if(port == 5) + { + if ((retVal = dal_rtl8373_phy_read(5, 7, 1, &phy_data)) != RT_ERR_OK) + return retVal; + + if(((phy_data >> 2) & 0x1) != 1) + return RT_ERR_PHY_LINK_DOWN; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_MACSEC_REG_ADDR_AE_PORT5_ADDR, RTL8373_MACSEC_REG_ADDR_AE_PORT5_REG_ADDR_AE_MASK, addr)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_REG_CMD_AE_PORT5_ADDR, RTL8373_MACSEC_REG_CMD_AE_PORT5_REG_RD_REQ_AE_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_getAsicReg(RTL8373_MACSEC_REG_RWDH_AE_PORT5_ADDR, &tmp)) != RT_ERR_OK) + return retVal; + + *value = ((tmp >> 16) & 0xffff) | ((tmp & 0xffff) << 16); + } + else if(port == 6) + { + if ((retVal = dal_rtl8373_phy_read(6, 7, 1, &phy_data)) != RT_ERR_OK) + return retVal; + + if(((phy_data >> 2) & 0x1) != 1) + return RT_ERR_PHY_LINK_DOWN; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_MACSEC_REG_ADDR_AE_PORT6_ADDR, RTL8373_MACSEC_REG_ADDR_AE_PORT6_REG_ADDR_AE_MASK, addr)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_REG_CMD_AE_PORT6_ADDR, RTL8373_MACSEC_REG_CMD_AE_PORT6_REG_RD_REQ_AE_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_getAsicReg(RTL8373_MACSEC_REG_RWDH_AE_PORT6_ADDR, &tmp)) != RT_ERR_OK) + return retVal; + + *value = ((tmp >> 16) & 0xffff) | ((tmp & 0xffff) << 16); + } + else if(port == 7) + { + if ((retVal = dal_rtl8373_phy_read(7, 7, 1, &phy_data)) != RT_ERR_OK) + return retVal; + + if(((phy_data >> 2) & 0x1) != 1) + return RT_ERR_PHY_LINK_DOWN; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_MACSEC_REG_ADDR_AE_PORT7_ADDR, RTL8373_MACSEC_REG_ADDR_AE_PORT7_REG_ADDR_AE_MASK, addr)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_REG_CMD_AE_PORT7_ADDR, RTL8373_MACSEC_REG_CMD_AE_PORT7_REG_RD_REQ_AE_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_getAsicReg(RTL8373_MACSEC_REG_RWDH_AE_PORT7_ADDR, &tmp)) != RT_ERR_OK) + return retVal; + + *value = ((tmp >> 16) & 0xffff) | ((tmp & 0xffff) << 16); + } + else + return RT_ERR_INPUT; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_macsec_ingress_set + * Description: + * Configure macsec ingress rule. + * Input: + * port - port id + * addr - macsec ip core register address + * value - data for rule + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure macsec ingress rule:SA match rule, flow control register and transform record. + */ +rtk_api_ret_t dal_rtl8373_macsec_ingress_set(rtk_uint32 port, rtk_uint32 addr, rtk_uint32 value) +{ + rtk_api_ret_t retVal; + rtk_uint32 phy_data; + + if(port == 0) + { +#if 1 //pending + + if ((retVal = dal_rtl8373_phy_read(0, 7, 1, &phy_data)) != RT_ERR_OK) + return retVal; + + if(((phy_data >> 2) & 0x1) != 1) + return RT_ERR_PHY_LINK_DOWN; + +#endif + if ((retVal = dal_rtl8224_top_regbits_write(RTL8373_MACSEC_REG_CMD_AE_PORT4_ADDR, RTL8373_MACSEC_REG_CMD_AE_PORT4_REG_DATA_AI_H_MASK, (value >> 16) &0xffff)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_regbits_write(RTL8373_MACSEC_REG_RWDL_AI_PORT4_ADDR, RTL8373_MACSEC_REG_RWDL_AI_PORT4_REG_DATA_AI_L_MASK, value & 0xffff)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_regbits_write(RTL8373_MACSEC_REG_ADDR_AI_PORT4_ADDR, RTL8373_MACSEC_REG_ADDR_AI_PORT4_REG_ADDR_AI_MASK, addr)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_REG_ADDR_AI_PORT4_ADDR, RTL8373_MACSEC_REG_ADDR_AI_PORT4_REG_WR_REQ_AI_OFFSET, 1)) != RT_ERR_OK) + return retVal; + } + else if(port == 1) + { +#if 1 //pending + + if ((retVal = dal_rtl8373_phy_read(1, 7, 1, &phy_data)) != RT_ERR_OK) + return retVal; + + if(((phy_data >> 2) & 0x1) != 1) + return RT_ERR_PHY_LINK_DOWN; +#endif + if ((retVal = dal_rtl8224_top_regbits_write(RTL8373_MACSEC_REG_CMD_AE_PORT5_ADDR, RTL8373_MACSEC_REG_CMD_AE_PORT5_REG_DATA_AI_H_MASK, (value >> 16) &0xffff)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_regbits_write(RTL8373_MACSEC_REG_RWDL_AI_PORT5_ADDR, RTL8373_MACSEC_REG_RWDL_AI_PORT5_REG_DATA_AI_L_MASK, value & 0xffff)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_regbits_write(RTL8373_MACSEC_REG_ADDR_AI_PORT5_ADDR, RTL8373_MACSEC_REG_ADDR_AI_PORT5_REG_ADDR_AI_MASK, addr)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_REG_ADDR_AI_PORT5_ADDR, RTL8373_MACSEC_REG_ADDR_AI_PORT5_REG_WR_REQ_AI_OFFSET, 1)) != RT_ERR_OK) + return retVal; + } + else if(port == 2) + { + if ((retVal = dal_rtl8373_phy_read(2, 7, 1, &phy_data)) != RT_ERR_OK) + return retVal; + + if(((phy_data >> 2) & 0x1) != 1) + return RT_ERR_PHY_LINK_DOWN; + + if ((retVal = dal_rtl8224_top_regbits_write(RTL8373_MACSEC_REG_CMD_AE_PORT6_ADDR, RTL8373_MACSEC_REG_CMD_AE_PORT6_REG_DATA_AI_H_MASK, (value >> 16) &0xffff)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_regbits_write(RTL8373_MACSEC_REG_RWDL_AI_PORT6_ADDR, RTL8373_MACSEC_REG_RWDL_AI_PORT6_REG_DATA_AI_L_MASK, value & 0xffff)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_regbits_write(RTL8373_MACSEC_REG_ADDR_AI_PORT6_ADDR, RTL8373_MACSEC_REG_ADDR_AI_PORT6_REG_ADDR_AI_MASK, addr)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_REG_ADDR_AI_PORT6_ADDR, RTL8373_MACSEC_REG_ADDR_AI_PORT6_REG_WR_REQ_AI_OFFSET, 1)) != RT_ERR_OK) + return retVal; + } + else if(port == 3) + { + if ((retVal = dal_rtl8373_phy_read(3, 7, 1, &phy_data)) != RT_ERR_OK) + return retVal; + + if(((phy_data >> 2) & 0x1) != 1) + return RT_ERR_PHY_LINK_DOWN; + + if ((retVal = dal_rtl8224_top_regbits_write(RTL8373_MACSEC_REG_CMD_AE_PORT7_ADDR, RTL8373_MACSEC_REG_CMD_AE_PORT7_REG_DATA_AI_H_MASK, (value >> 16) &0xffff)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_regbits_write(RTL8373_MACSEC_REG_RWDL_AI_PORT7_ADDR, RTL8373_MACSEC_REG_RWDL_AI_PORT7_REG_DATA_AI_L_MASK, value & 0xffff)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_regbits_write(RTL8373_MACSEC_REG_ADDR_AI_PORT7_ADDR, RTL8373_MACSEC_REG_ADDR_AI_PORT7_REG_ADDR_AI_MASK, addr)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_REG_ADDR_AI_PORT7_ADDR, RTL8373_MACSEC_REG_ADDR_AI_PORT7_REG_WR_REQ_AI_OFFSET, 1)) != RT_ERR_OK) + return retVal; + } + else if(port == 4) + { + if ((retVal = dal_rtl8373_phy_read(4, 7, 1, &phy_data)) != RT_ERR_OK) + return retVal; + + if(((phy_data >> 2) & 0x1) != 1) + return RT_ERR_PHY_LINK_DOWN; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_MACSEC_REG_CMD_AE_PORT4_ADDR, RTL8373_MACSEC_REG_CMD_AE_PORT4_REG_DATA_AI_H_MASK, (value >> 16) &0xffff)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_MACSEC_REG_RWDL_AI_PORT4_ADDR, RTL8373_MACSEC_REG_RWDL_AI_PORT4_REG_DATA_AI_L_MASK, value & 0xffff)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_MACSEC_REG_ADDR_AI_PORT4_ADDR, RTL8373_MACSEC_REG_ADDR_AI_PORT4_REG_ADDR_AI_MASK, addr)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_REG_ADDR_AI_PORT4_ADDR, RTL8373_MACSEC_REG_ADDR_AI_PORT4_REG_WR_REQ_AI_OFFSET, 1)) != RT_ERR_OK) + return retVal; + } + else if(port == 5) + { + if ((retVal = dal_rtl8373_phy_read(5, 7, 1, &phy_data)) != RT_ERR_OK) + return retVal; + + if(((phy_data >> 2) & 0x1) != 1) + return RT_ERR_PHY_LINK_DOWN; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_MACSEC_REG_CMD_AE_PORT5_ADDR, RTL8373_MACSEC_REG_CMD_AE_PORT5_REG_DATA_AI_H_MASK, (value >> 16) &0xffff)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_MACSEC_REG_RWDL_AI_PORT5_ADDR, RTL8373_MACSEC_REG_RWDL_AI_PORT5_REG_DATA_AI_L_MASK, value & 0xffff)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_MACSEC_REG_ADDR_AI_PORT5_ADDR, RTL8373_MACSEC_REG_ADDR_AI_PORT5_REG_ADDR_AI_MASK, addr)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_REG_ADDR_AI_PORT5_ADDR, RTL8373_MACSEC_REG_ADDR_AI_PORT5_REG_WR_REQ_AI_OFFSET, 1)) != RT_ERR_OK) + return retVal; + } + else if(port == 6) + { + if ((retVal = dal_rtl8373_phy_read(6, 7, 1, &phy_data)) != RT_ERR_OK) + return retVal; + + if(((phy_data >> 2) & 0x1) != 1) + return RT_ERR_PHY_LINK_DOWN; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_MACSEC_REG_CMD_AE_PORT6_ADDR, RTL8373_MACSEC_REG_CMD_AE_PORT6_REG_DATA_AI_H_MASK, (value >> 16) &0xffff)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_MACSEC_REG_RWDL_AI_PORT6_ADDR, RTL8373_MACSEC_REG_RWDL_AI_PORT6_REG_DATA_AI_L_MASK, value & 0xffff)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_MACSEC_REG_ADDR_AI_PORT6_ADDR, RTL8373_MACSEC_REG_ADDR_AI_PORT6_REG_ADDR_AI_MASK, addr)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_REG_ADDR_AI_PORT6_ADDR, RTL8373_MACSEC_REG_ADDR_AI_PORT6_REG_WR_REQ_AI_OFFSET, 1)) != RT_ERR_OK) + return retVal; + } + else if(port == 7) + { + if ((retVal = dal_rtl8373_phy_read(7, 7, 1, &phy_data)) != RT_ERR_OK) + return retVal; + + if(((phy_data >> 2) & 0x1) != 1) + return RT_ERR_PHY_LINK_DOWN; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_MACSEC_REG_CMD_AE_PORT7_ADDR, RTL8373_MACSEC_REG_CMD_AE_PORT7_REG_DATA_AI_H_MASK, (value >> 16) &0xffff)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_MACSEC_REG_RWDL_AI_PORT7_ADDR, RTL8373_MACSEC_REG_RWDL_AI_PORT7_REG_DATA_AI_L_MASK, value & 0xffff)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_MACSEC_REG_ADDR_AI_PORT7_ADDR, RTL8373_MACSEC_REG_ADDR_AI_PORT7_REG_ADDR_AI_MASK, addr)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_REG_ADDR_AI_PORT7_ADDR, RTL8373_MACSEC_REG_ADDR_AI_PORT7_REG_WR_REQ_AI_OFFSET, 1)) != RT_ERR_OK) + return retVal; + } + else + return RT_ERR_INPUT; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_macsec_ingress_get + * Description: + * get macsec egress rule. + * Input: + * port - port id + * addr - macsec ip core register address + * Output: + * value - data for rule + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will get macsec ingress rule:SA match rule, flow control register and transform record. + */ +rtk_api_ret_t dal_rtl8373_macsec_ingress_get(rtk_uint32 port, rtk_uint32 addr, rtk_uint32 *value) +{ + rtk_api_ret_t retVal; + rtk_uint32 phy_data; + rtk_uint32 value_H,value_L; + + if(port == 0) + { +#if 1 //pending + + if ((retVal = dal_rtl8373_phy_read(0, 7, 1, &phy_data)) != RT_ERR_OK) + return retVal; + + if(((phy_data >> 2) & 0x1) != 1) + return RT_ERR_PHY_LINK_DOWN; +#endif + if ((retVal = dal_rtl8224_top_regbits_write(RTL8373_MACSEC_REG_ADDR_AI_PORT4_ADDR, RTL8373_MACSEC_REG_ADDR_AI_PORT4_REG_ADDR_AI_MASK, addr)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_REG_ADDR_AI_PORT4_ADDR, RTL8373_MACSEC_REG_ADDR_AI_PORT4_REG_RD_REQ_AI_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_regbits_read(RTL8373_MACSEC_REG_CMD_AE_PORT4_ADDR, RTL8373_MACSEC_REG_CMD_AE_PORT4_REG_DATA_AI_H_MASK, &value_H)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_regbits_read(RTL8373_MACSEC_REG_RWDL_AI_PORT4_ADDR, RTL8373_MACSEC_REG_RWDL_AI_PORT4_REG_DATA_AI_L_MASK, &value_L)) != RT_ERR_OK) + return retVal; + + *value = (value_H << 16) | (value_L & 0xffff); + + } + else if(port == 1) + { +#if 1 //pending + + if ((retVal = dal_rtl8373_phy_read(1, 7, 1, &phy_data)) != RT_ERR_OK) + return retVal; + + if(((phy_data >> 2) & 0x1) != 1) + return RT_ERR_PHY_LINK_DOWN; +#endif + if ((retVal = dal_rtl8224_top_regbits_write(RTL8373_MACSEC_REG_ADDR_AI_PORT5_ADDR, RTL8373_MACSEC_REG_ADDR_AI_PORT5_REG_ADDR_AI_MASK, addr)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_REG_ADDR_AI_PORT5_ADDR, RTL8373_MACSEC_REG_ADDR_AI_PORT5_REG_RD_REQ_AI_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_regbits_read(RTL8373_MACSEC_REG_CMD_AE_PORT5_ADDR, RTL8373_MACSEC_REG_CMD_AE_PORT5_REG_DATA_AI_H_MASK, &value_H)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_regbits_read(RTL8373_MACSEC_REG_RWDL_AI_PORT5_ADDR, RTL8373_MACSEC_REG_RWDL_AI_PORT5_REG_DATA_AI_L_MASK, &value_L)) != RT_ERR_OK) + return retVal; + + *value = (value_H << 16) | (value_L & 0xffff); + } + else if(port == 2) + { + if ((retVal = dal_rtl8373_phy_read(2, 7, 1, &phy_data)) != RT_ERR_OK) + return retVal; + + if(((phy_data >> 2) & 0x1) != 1) + return RT_ERR_PHY_LINK_DOWN; + + if ((retVal = dal_rtl8224_top_regbits_write(RTL8373_MACSEC_REG_ADDR_AI_PORT6_ADDR, RTL8373_MACSEC_REG_ADDR_AI_PORT6_REG_ADDR_AI_MASK, addr)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_REG_ADDR_AI_PORT6_ADDR, RTL8373_MACSEC_REG_ADDR_AI_PORT6_REG_RD_REQ_AI_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_regbits_read(RTL8373_MACSEC_REG_CMD_AE_PORT6_ADDR, RTL8373_MACSEC_REG_CMD_AE_PORT6_REG_DATA_AI_H_MASK, &value_H)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_regbits_read(RTL8373_MACSEC_REG_RWDL_AI_PORT6_ADDR, RTL8373_MACSEC_REG_RWDL_AI_PORT6_REG_DATA_AI_L_MASK, &value_L)) != RT_ERR_OK) + return retVal; + + *value = (value_H << 16) | (value_L & 0xffff); + } + else if(port == 3) + { + if ((retVal = dal_rtl8373_phy_read(3, 7, 1, &phy_data)) != RT_ERR_OK) + return retVal; + + if(((phy_data >> 2) & 0x1) != 1) + return RT_ERR_PHY_LINK_DOWN; + + if ((retVal = dal_rtl8224_top_regbits_write(RTL8373_MACSEC_REG_ADDR_AI_PORT7_ADDR, RTL8373_MACSEC_REG_ADDR_AI_PORT7_REG_ADDR_AI_MASK, addr)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_REG_ADDR_AI_PORT7_ADDR, RTL8373_MACSEC_REG_ADDR_AI_PORT7_REG_RD_REQ_AI_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_regbits_read(RTL8373_MACSEC_REG_CMD_AE_PORT7_ADDR, RTL8373_MACSEC_REG_CMD_AE_PORT7_REG_DATA_AI_H_MASK, &value_H)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_regbits_read(RTL8373_MACSEC_REG_RWDL_AI_PORT7_ADDR, RTL8373_MACSEC_REG_RWDL_AI_PORT7_REG_DATA_AI_L_MASK, &value_L)) != RT_ERR_OK) + return retVal; + + *value = (value_H << 16) | (value_L & 0xffff); + } + else if(port == 4) + { + if ((retVal = dal_rtl8373_phy_read(4, 7, 1, &phy_data)) != RT_ERR_OK) + return retVal; + + if(((phy_data >> 2) & 0x1) != 1) + return RT_ERR_PHY_LINK_DOWN; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_MACSEC_REG_ADDR_AI_PORT4_ADDR, RTL8373_MACSEC_REG_ADDR_AI_PORT4_REG_ADDR_AI_MASK, addr)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_REG_ADDR_AI_PORT4_ADDR, RTL8373_MACSEC_REG_ADDR_AI_PORT4_REG_RD_REQ_AI_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_getAsicRegBits(RTL8373_MACSEC_REG_CMD_AE_PORT4_ADDR, RTL8373_MACSEC_REG_CMD_AE_PORT4_REG_DATA_AI_H_MASK, &value_H)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_getAsicRegBits(RTL8373_MACSEC_REG_RWDL_AI_PORT4_ADDR, RTL8373_MACSEC_REG_RWDL_AI_PORT4_REG_DATA_AI_L_MASK, &value_L)) != RT_ERR_OK) + return retVal; + + *value = (value_H << 16) | (value_L & 0xffff); + + } + else if(port == 5) + { + if ((retVal = dal_rtl8373_phy_read(5, 7, 1, &phy_data)) != RT_ERR_OK) + return retVal; + + if(((phy_data >> 2) & 0x1) != 1) + return RT_ERR_PHY_LINK_DOWN; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_MACSEC_REG_ADDR_AI_PORT5_ADDR, RTL8373_MACSEC_REG_ADDR_AI_PORT5_REG_ADDR_AI_MASK, addr)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_REG_ADDR_AI_PORT5_ADDR, RTL8373_MACSEC_REG_ADDR_AI_PORT5_REG_RD_REQ_AI_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_getAsicRegBits(RTL8373_MACSEC_REG_CMD_AE_PORT5_ADDR, RTL8373_MACSEC_REG_CMD_AE_PORT5_REG_DATA_AI_H_MASK, &value_H)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_getAsicRegBits(RTL8373_MACSEC_REG_RWDL_AI_PORT5_ADDR, RTL8373_MACSEC_REG_RWDL_AI_PORT5_REG_DATA_AI_L_MASK, &value_L)) != RT_ERR_OK) + return retVal; + + *value = (value_H << 16) | (value_L & 0xffff); + } + else if(port == 6) + { + if ((retVal = dal_rtl8373_phy_read(6, 7, 1, &phy_data)) != RT_ERR_OK) + return retVal; + + if(((phy_data >> 2) & 0x1) != 1) + return RT_ERR_PHY_LINK_DOWN; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_MACSEC_REG_ADDR_AI_PORT6_ADDR, RTL8373_MACSEC_REG_ADDR_AI_PORT6_REG_ADDR_AI_MASK, addr)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_REG_ADDR_AI_PORT6_ADDR, RTL8373_MACSEC_REG_ADDR_AI_PORT6_REG_RD_REQ_AI_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_getAsicRegBits(RTL8373_MACSEC_REG_CMD_AE_PORT6_ADDR, RTL8373_MACSEC_REG_CMD_AE_PORT6_REG_DATA_AI_H_MASK, &value_H)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_getAsicRegBits(RTL8373_MACSEC_REG_RWDL_AI_PORT6_ADDR, RTL8373_MACSEC_REG_RWDL_AI_PORT6_REG_DATA_AI_L_MASK, &value_L)) != RT_ERR_OK) + return retVal; + + *value = (value_H << 16) | (value_L & 0xffff); + } + else if(port == 7) + { + if ((retVal = dal_rtl8373_phy_read(7, 7, 1, &phy_data)) != RT_ERR_OK) + return retVal; + + if(((phy_data >> 2) & 0x1) != 1) + return RT_ERR_PHY_LINK_DOWN; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_MACSEC_REG_ADDR_AI_PORT7_ADDR, RTL8373_MACSEC_REG_ADDR_AI_PORT7_REG_ADDR_AI_MASK, addr)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_REG_ADDR_AI_PORT7_ADDR, RTL8373_MACSEC_REG_ADDR_AI_PORT7_REG_RD_REQ_AI_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_getAsicRegBits(RTL8373_MACSEC_REG_CMD_AE_PORT7_ADDR, RTL8373_MACSEC_REG_CMD_AE_PORT7_REG_DATA_AI_H_MASK, &value_H)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_getAsicRegBits(RTL8373_MACSEC_REG_RWDL_AI_PORT7_ADDR, RTL8373_MACSEC_REG_RWDL_AI_PORT7_REG_DATA_AI_L_MASK, &value_L)) != RT_ERR_OK) + return retVal; + + *value = (value_H << 16) | (value_L & 0xffff); + } + else + return RT_ERR_INPUT; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_macsec_rxgating_set + * Description: + * Configure macsec rx gating value + * Input: + * port - port id + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure macsec rx gating value,before set the packet flow path called this API. + */ +rtk_api_ret_t dal_rtl8373_macsec_rxgating_set(rtk_uint32 port) +{ + rtk_api_ret_t retVal; + rtk_uint32 tmp_value,tmp_gvalue; + rtk_uint32 pollcnt; + + if(port == 0) + { + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_REG_GLB_SET1_PORT4_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT4_RX_GATING_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + for(pollcnt = 0; pollcnt < 0xffff; pollcnt++) + { + if ((retVal = dal_rtl8224_top_regbit_read(RTL8373_MACSEC_REG_GLB_MASK_PORT4_ADDR, RTL8373_MACSEC_REG_GLB_MASK_PORT4_RX_XGMASK_OFFSET, &tmp_value)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_regbit_read(RTL8373_MACSEC_REG_GLB_MASK_PORT4_ADDR, RTL8373_MACSEC_REG_GLB_MASK_PORT4_RXDV_GMASK_OFFSET, &tmp_gvalue)) != RT_ERR_OK) + return retVal; + + if((tmp_value == 1) && (tmp_gvalue == 1)) + break; + } + if(pollcnt == RTL8373_MACSEC_POLLCNT) + return RT_ERR_BUSYWAIT_TIMEOUT; + } + else if(port == 1) + { + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_REG_GLB_SET1_PORT5_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT5_RX_GATING_OFFSET, 1)) != RT_ERR_OK) + return retVal; + for(pollcnt = 0; pollcnt < RTL8373_MACSEC_POLLCNT; pollcnt++) + { + if ((retVal = dal_rtl8224_top_regbit_read(RTL8373_MACSEC_REG_GLB_MASK_PORT5_ADDR, RTL8373_MACSEC_REG_GLB_MASK_PORT5_RX_XGMASK_OFFSET, &tmp_value)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_regbit_read(RTL8373_MACSEC_REG_GLB_MASK_PORT5_ADDR, RTL8373_MACSEC_REG_GLB_MASK_PORT5_RXDV_GMASK_OFFSET, &tmp_gvalue)) != RT_ERR_OK) + return retVal; + + if((tmp_value == 1) && (tmp_gvalue == 1)) + break; + } + + if(pollcnt == RTL8373_MACSEC_POLLCNT) + return RT_ERR_BUSYWAIT_TIMEOUT; + } + else if(port == 2) + { + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_REG_GLB_SET1_PORT6_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT6_RX_GATING_OFFSET, 1)) != RT_ERR_OK) + return retVal; + for(pollcnt = 0; pollcnt < RTL8373_MACSEC_POLLCNT; pollcnt++) + { + if ((retVal = dal_rtl8224_top_regbit_read(RTL8373_MACSEC_REG_GLB_MASK_PORT6_ADDR, RTL8373_MACSEC_REG_GLB_MASK_PORT6_RX_XGMASK_OFFSET, &tmp_value)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_regbit_read(RTL8373_MACSEC_REG_GLB_MASK_PORT6_ADDR, RTL8373_MACSEC_REG_GLB_MASK_PORT6_RXDV_GMASK_OFFSET, &tmp_gvalue)) != RT_ERR_OK) + return retVal; + + if((tmp_value == 1) && (tmp_gvalue == 1)) + break; + } + + if(pollcnt == RTL8373_MACSEC_POLLCNT) + return RT_ERR_BUSYWAIT_TIMEOUT; + } + else if(port == 3) + { + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_REG_GLB_SET1_PORT7_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT7_RX_GATING_OFFSET, 1)) != RT_ERR_OK) + return retVal; + for(pollcnt = 0; pollcnt < RTL8373_MACSEC_POLLCNT; pollcnt++) + { + if ((retVal = dal_rtl8224_top_regbit_read(RTL8373_MACSEC_REG_GLB_MASK_PORT7_ADDR, RTL8373_MACSEC_REG_GLB_MASK_PORT7_RX_XGMASK_OFFSET, &tmp_value)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_regbit_read(RTL8373_MACSEC_REG_GLB_MASK_PORT7_ADDR, RTL8373_MACSEC_REG_GLB_MASK_PORT7_RXDV_GMASK_OFFSET, &tmp_gvalue)) != RT_ERR_OK) + return retVal; + + if((tmp_value == 1) && (tmp_gvalue == 1)) + break; + } + + if(pollcnt == RTL8373_MACSEC_POLLCNT) + return RT_ERR_BUSYWAIT_TIMEOUT; + } + else if(port == 4) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_REG_GLB_SET1_PORT4_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT4_RX_GATING_OFFSET, 1)) != RT_ERR_OK) + return retVal; + for(pollcnt = 0; pollcnt < RTL8373_MACSEC_POLLCNT; pollcnt++) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_MACSEC_REG_GLB_MASK_PORT4_ADDR, RTL8373_MACSEC_REG_GLB_MASK_PORT4_RX_XGMASK_OFFSET, &tmp_value)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_getAsicRegBit(RTL8373_MACSEC_REG_GLB_MASK_PORT4_ADDR, RTL8373_MACSEC_REG_GLB_MASK_PORT4_RXDV_GMASK_OFFSET, &tmp_gvalue)) != RT_ERR_OK) + return retVal; + + if((tmp_value == 1) && (tmp_gvalue == 1)) + break; + } + + if(pollcnt == RTL8373_MACSEC_POLLCNT) + return RT_ERR_BUSYWAIT_TIMEOUT; + } + else if(port == 5) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_REG_GLB_SET1_PORT5_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT5_RX_GATING_OFFSET, 1)) != RT_ERR_OK) + return retVal; + for(pollcnt = 0; pollcnt < RTL8373_MACSEC_POLLCNT; pollcnt++) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_MACSEC_REG_GLB_MASK_PORT5_ADDR, RTL8373_MACSEC_REG_GLB_MASK_PORT5_RX_XGMASK_OFFSET, &tmp_value)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_getAsicRegBit(RTL8373_MACSEC_REG_GLB_MASK_PORT5_ADDR, RTL8373_MACSEC_REG_GLB_MASK_PORT5_RXDV_GMASK_OFFSET, &tmp_gvalue)) != RT_ERR_OK) + return retVal; + + if((tmp_value == 1) && (tmp_gvalue == 1)) + break; + } + + if(pollcnt == RTL8373_MACSEC_POLLCNT) + return RT_ERR_BUSYWAIT_TIMEOUT; + } + else if(port == 6) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_REG_GLB_SET1_PORT6_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT6_RX_GATING_OFFSET, 1)) != RT_ERR_OK) + return retVal; + for(pollcnt = 0; pollcnt < RTL8373_MACSEC_POLLCNT; pollcnt++) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_MACSEC_REG_GLB_MASK_PORT6_ADDR, RTL8373_MACSEC_REG_GLB_MASK_PORT6_RX_XGMASK_OFFSET, &tmp_value)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_getAsicRegBit(RTL8373_MACSEC_REG_GLB_MASK_PORT6_ADDR, RTL8373_MACSEC_REG_GLB_MASK_PORT6_RXDV_GMASK_OFFSET, &tmp_gvalue)) != RT_ERR_OK) + return retVal; + + if((tmp_value == 1) && (tmp_gvalue == 1)) + break; + } + + if(pollcnt == RTL8373_MACSEC_POLLCNT) + return RT_ERR_BUSYWAIT_TIMEOUT; + } + else if(port == 7) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_REG_GLB_SET1_PORT7_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT7_RX_GATING_OFFSET, 1)) != RT_ERR_OK) + return retVal; + for(pollcnt = 0; pollcnt < RTL8373_MACSEC_POLLCNT; pollcnt++) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_MACSEC_REG_GLB_MASK_PORT7_ADDR, RTL8373_MACSEC_REG_GLB_MASK_PORT7_RX_XGMASK_OFFSET, &tmp_value)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_getAsicRegBit(RTL8373_MACSEC_REG_GLB_MASK_PORT7_ADDR, RTL8373_MACSEC_REG_GLB_MASK_PORT7_RXDV_GMASK_OFFSET, &tmp_gvalue)) != RT_ERR_OK) + return retVal; + + if((tmp_value == 1) && (tmp_gvalue == 1)) + break; + } + + if(pollcnt == RTL8373_MACSEC_POLLCNT) + return RT_ERR_BUSYWAIT_TIMEOUT; + } + else + return RT_ERR_INPUT; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_macsec_rxgating_cancel + * Description: + * Configure macsec rx gating value + * Input: + * port - port id + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure macsec rx gating value, called after packet flow path changed. + */ +rtk_api_ret_t dal_rtl8373_macsec_rxgating_cancel(rtk_uint32 port) +{ + rtk_api_ret_t retVal; + rtk_uint32 tmp_value,tmp_gvalue; + rtk_uint32 pollcnt; + + if(port == 0) + { + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_REG_GLB_SET1_PORT4_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT4_RX_GATING_OFFSET, 0)) != RT_ERR_OK) + return retVal; + for(pollcnt = 0; pollcnt < RTL8373_MACSEC_POLLCNT; pollcnt++) + { + if ((retVal = dal_rtl8224_top_regbit_read(RTL8373_MACSEC_REG_GLB_MASK_PORT4_ADDR, RTL8373_MACSEC_REG_GLB_MASK_PORT4_RX_XGMASK_OFFSET, &tmp_value)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_regbit_read(RTL8373_MACSEC_REG_GLB_MASK_PORT4_ADDR, RTL8373_MACSEC_REG_GLB_MASK_PORT4_RXDV_GMASK_OFFSET, &tmp_gvalue)) != RT_ERR_OK) + return retVal; + + if((tmp_value == 0) && (tmp_gvalue == 0)) + break; + } + + if(pollcnt == RTL8373_MACSEC_POLLCNT) + return RT_ERR_BUSYWAIT_TIMEOUT; + } + else if(port == 1) + { + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_REG_GLB_SET1_PORT5_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT5_RX_GATING_OFFSET, 0)) != RT_ERR_OK) + return retVal; + for(pollcnt = 0; pollcnt < RTL8373_MACSEC_POLLCNT; pollcnt++) + { + if ((retVal = dal_rtl8224_top_regbit_read(RTL8373_MACSEC_REG_GLB_MASK_PORT5_ADDR, RTL8373_MACSEC_REG_GLB_MASK_PORT5_RX_XGMASK_OFFSET, &tmp_value)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_regbit_read(RTL8373_MACSEC_REG_GLB_MASK_PORT5_ADDR, RTL8373_MACSEC_REG_GLB_MASK_PORT5_RXDV_GMASK_OFFSET, &tmp_gvalue)) != RT_ERR_OK) + return retVal; + + if((tmp_value == 0) && (tmp_gvalue == 0)) + break; + } + + if(pollcnt == RTL8373_MACSEC_POLLCNT) + return RT_ERR_BUSYWAIT_TIMEOUT; + } + else if(port == 2) + { + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_REG_GLB_SET1_PORT6_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT6_RX_GATING_OFFSET, 0)) != RT_ERR_OK) + return retVal; + for(pollcnt = 0; pollcnt < RTL8373_MACSEC_POLLCNT; pollcnt++) + { + if ((retVal = dal_rtl8224_top_regbit_read(RTL8373_MACSEC_REG_GLB_MASK_PORT6_ADDR, RTL8373_MACSEC_REG_GLB_MASK_PORT6_RX_XGMASK_OFFSET, &tmp_value)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_regbit_read(RTL8373_MACSEC_REG_GLB_MASK_PORT6_ADDR, RTL8373_MACSEC_REG_GLB_MASK_PORT6_RXDV_GMASK_OFFSET, &tmp_gvalue)) != RT_ERR_OK) + return retVal; + + if((tmp_value == 0) && (tmp_gvalue == 0)) + break; + } + + if(pollcnt == RTL8373_MACSEC_POLLCNT) + return RT_ERR_BUSYWAIT_TIMEOUT; + } + else if(port == 3) + { + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_REG_GLB_SET1_PORT7_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT7_RX_GATING_OFFSET, 0)) != RT_ERR_OK) + return retVal; + for(pollcnt = 0; pollcnt < RTL8373_MACSEC_POLLCNT; pollcnt++) + { + if ((retVal = dal_rtl8224_top_regbit_read(RTL8373_MACSEC_REG_GLB_MASK_PORT7_ADDR, RTL8373_MACSEC_REG_GLB_MASK_PORT7_RX_XGMASK_OFFSET, &tmp_value)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_regbit_read(RTL8373_MACSEC_REG_GLB_MASK_PORT7_ADDR, RTL8373_MACSEC_REG_GLB_MASK_PORT7_RXDV_GMASK_OFFSET, &tmp_gvalue)) != RT_ERR_OK) + return retVal; + + if((tmp_value == 0) && (tmp_gvalue == 0)) + break; + } + + if(pollcnt == RTL8373_MACSEC_POLLCNT) + return RT_ERR_BUSYWAIT_TIMEOUT; + } + else if(port == 4) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_REG_GLB_SET1_PORT4_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT4_RX_GATING_OFFSET, 0)) != RT_ERR_OK) + return retVal; + for(pollcnt = 0; pollcnt < RTL8373_MACSEC_POLLCNT; pollcnt++) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_MACSEC_REG_GLB_MASK_PORT4_ADDR, RTL8373_MACSEC_REG_GLB_MASK_PORT4_RX_XGMASK_OFFSET, &tmp_value)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_getAsicRegBit(RTL8373_MACSEC_REG_GLB_MASK_PORT4_ADDR, RTL8373_MACSEC_REG_GLB_MASK_PORT4_RXDV_GMASK_OFFSET, &tmp_gvalue)) != RT_ERR_OK) + return retVal; + + if((tmp_value == 0) && (tmp_gvalue == 0)) + break; + } + + if(pollcnt == RTL8373_MACSEC_POLLCNT) + return RT_ERR_BUSYWAIT_TIMEOUT; + } + else if(port == 5) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_REG_GLB_SET1_PORT5_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT5_RX_GATING_OFFSET, 0)) != RT_ERR_OK) + return retVal; + for(pollcnt = 0; pollcnt < RTL8373_MACSEC_POLLCNT; pollcnt++) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_MACSEC_REG_GLB_MASK_PORT5_ADDR, RTL8373_MACSEC_REG_GLB_MASK_PORT5_RX_XGMASK_OFFSET, &tmp_value)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_getAsicRegBit(RTL8373_MACSEC_REG_GLB_MASK_PORT5_ADDR, RTL8373_MACSEC_REG_GLB_MASK_PORT5_RXDV_GMASK_OFFSET, &tmp_gvalue)) != RT_ERR_OK) + return retVal; + + if((tmp_value == 0) && (tmp_gvalue == 0)) + break; + } + + if(pollcnt == RTL8373_MACSEC_POLLCNT) + return RT_ERR_BUSYWAIT_TIMEOUT; + } + else if(port == 6) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_REG_GLB_SET1_PORT6_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT6_RX_GATING_OFFSET, 0)) != RT_ERR_OK) + return retVal; + for(pollcnt = 0; pollcnt < RTL8373_MACSEC_POLLCNT; pollcnt++) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_MACSEC_REG_GLB_MASK_PORT6_ADDR, RTL8373_MACSEC_REG_GLB_MASK_PORT6_RX_XGMASK_OFFSET, &tmp_value)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_getAsicRegBit(RTL8373_MACSEC_REG_GLB_MASK_PORT6_ADDR, RTL8373_MACSEC_REG_GLB_MASK_PORT6_RXDV_GMASK_OFFSET, &tmp_gvalue)) != RT_ERR_OK) + return retVal; + + if((tmp_value == 0) && (tmp_gvalue == 0)) + break; + } + + if(pollcnt == RTL8373_MACSEC_POLLCNT) + return RT_ERR_BUSYWAIT_TIMEOUT; + } + else if(port == 7) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_REG_GLB_SET1_PORT7_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT7_RX_GATING_OFFSET, 0)) != RT_ERR_OK) + return retVal; + for(pollcnt = 0; pollcnt < RTL8373_MACSEC_POLLCNT; pollcnt++) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_MACSEC_REG_GLB_MASK_PORT7_ADDR, RTL8373_MACSEC_REG_GLB_MASK_PORT7_RX_XGMASK_OFFSET, &tmp_value)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_getAsicRegBit(RTL8373_MACSEC_REG_GLB_MASK_PORT7_ADDR, RTL8373_MACSEC_REG_GLB_MASK_PORT7_RXDV_GMASK_OFFSET, &tmp_gvalue)) != RT_ERR_OK) + return retVal; + + if((tmp_value == 0) && (tmp_gvalue == 0)) + break; + } + + if(pollcnt == RTL8373_MACSEC_POLLCNT) + return RT_ERR_BUSYWAIT_TIMEOUT; + } + else + return RT_ERR_INPUT; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_macsec_txgating_set + * Description: + * Configure macsec tx gating value + * Input: + * port - port id + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure macsec tx gating value, before set the packet flow path called this API. + */ +rtk_api_ret_t dal_rtl8373_macsec_txgating_set(rtk_uint32 port) +{ + rtk_api_ret_t retVal; + rtk_uint32 tmp_value,tmp_gvalue; + rtk_uint32 pollcnt; + + if(port == 0) + { + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_REG_GLB_SET1_PORT4_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT4_TX_GATING_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + for(pollcnt = 0; pollcnt < RTL8373_MACSEC_POLLCNT; pollcnt++) + { + if ((retVal = dal_rtl8224_top_regbit_read(RTL8373_MACSEC_REG_GLB_MASK_PORT4_ADDR, RTL8373_MACSEC_REG_GLB_MASK_PORT4_TX_XGMASK_OFFSET, &tmp_value)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_regbit_read(RTL8373_MACSEC_REG_GLB_MASK_PORT4_ADDR, RTL8373_MACSEC_REG_GLB_MASK_PORT4_TXEN_GMASK_OFFSET, &tmp_gvalue)) != RT_ERR_OK) + return retVal; + + if((tmp_value == 1) && (tmp_gvalue == 1)) + break; + } + if(pollcnt == RTL8373_MACSEC_POLLCNT) + return RT_ERR_BUSYWAIT_TIMEOUT; + } + else if(port == 1) + { + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_REG_GLB_SET1_PORT5_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT5_TX_GATING_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + for(pollcnt = 0; pollcnt < RTL8373_MACSEC_POLLCNT; pollcnt++) + { + if ((retVal = dal_rtl8224_top_regbit_read(RTL8373_MACSEC_REG_GLB_MASK_PORT5_ADDR, RTL8373_MACSEC_REG_GLB_MASK_PORT5_TX_XGMASK_OFFSET, &tmp_value)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_regbit_read(RTL8373_MACSEC_REG_GLB_MASK_PORT5_ADDR, RTL8373_MACSEC_REG_GLB_MASK_PORT5_TXEN_GMASK_OFFSET, &tmp_gvalue)) != RT_ERR_OK) + return retVal; + + if((tmp_value == 1) && (tmp_gvalue == 1)) + break; + } + + if(pollcnt == RTL8373_MACSEC_POLLCNT) + return RT_ERR_BUSYWAIT_TIMEOUT; + } + else if(port == 2) + { + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_REG_GLB_SET1_PORT6_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT6_TX_GATING_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + for(pollcnt = 0; pollcnt < RTL8373_MACSEC_POLLCNT; pollcnt++) + { + if ((retVal = dal_rtl8224_top_regbit_read(RTL8373_MACSEC_REG_GLB_MASK_PORT6_ADDR, RTL8373_MACSEC_REG_GLB_MASK_PORT6_TX_XGMASK_OFFSET, &tmp_value)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_regbit_read(RTL8373_MACSEC_REG_GLB_MASK_PORT6_ADDR, RTL8373_MACSEC_REG_GLB_MASK_PORT6_TXEN_GMASK_OFFSET, &tmp_gvalue)) != RT_ERR_OK) + return retVal; + + if((tmp_value == 1) && (tmp_gvalue == 1)) + break; + } + + if(pollcnt == RTL8373_MACSEC_POLLCNT) + return RT_ERR_BUSYWAIT_TIMEOUT; + } + else if(port == 3) + { + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_REG_GLB_SET1_PORT7_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT7_TX_GATING_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + for(pollcnt = 0; pollcnt < RTL8373_MACSEC_POLLCNT; pollcnt++) + { + if ((retVal = dal_rtl8224_top_regbit_read(RTL8373_MACSEC_REG_GLB_MASK_PORT7_ADDR, RTL8373_MACSEC_REG_GLB_MASK_PORT7_TX_XGMASK_OFFSET, &tmp_value)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_regbit_read(RTL8373_MACSEC_REG_GLB_MASK_PORT7_ADDR, RTL8373_MACSEC_REG_GLB_MASK_PORT7_TXEN_GMASK_OFFSET, &tmp_gvalue)) != RT_ERR_OK) + return retVal; + + if((tmp_value == 1) && (tmp_gvalue == 1)) + break; + } + + if(pollcnt == RTL8373_MACSEC_POLLCNT) + return RT_ERR_BUSYWAIT_TIMEOUT; + } + else if(port == 4) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_REG_GLB_SET1_PORT4_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT4_TX_GATING_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + for(pollcnt = 0; pollcnt < RTL8373_MACSEC_POLLCNT; pollcnt++) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_MACSEC_REG_GLB_MASK_PORT4_ADDR, RTL8373_MACSEC_REG_GLB_MASK_PORT4_TX_XGMASK_OFFSET, &tmp_value)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_getAsicRegBit(RTL8373_MACSEC_REG_GLB_MASK_PORT4_ADDR, RTL8373_MACSEC_REG_GLB_MASK_PORT4_TXEN_GMASK_OFFSET, &tmp_gvalue)) != RT_ERR_OK) + return retVal; + + if((tmp_value == 1) && (tmp_gvalue == 1)) + break; + } + + if(pollcnt == RTL8373_MACSEC_POLLCNT) + return RT_ERR_BUSYWAIT_TIMEOUT; + } + else if(port == 5) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_REG_GLB_SET1_PORT5_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT5_TX_GATING_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + for(pollcnt = 0; pollcnt < RTL8373_MACSEC_POLLCNT; pollcnt++) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_MACSEC_REG_GLB_MASK_PORT5_ADDR, RTL8373_MACSEC_REG_GLB_MASK_PORT5_TX_XGMASK_OFFSET, &tmp_value)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_getAsicRegBit(RTL8373_MACSEC_REG_GLB_MASK_PORT5_ADDR, RTL8373_MACSEC_REG_GLB_MASK_PORT5_TXEN_GMASK_OFFSET, &tmp_gvalue)) != RT_ERR_OK) + return retVal; + + if((tmp_value == 1) && (tmp_gvalue == 1)) + break; + } + + if(pollcnt == RTL8373_MACSEC_POLLCNT) + return RT_ERR_BUSYWAIT_TIMEOUT; + } + else if(port == 6) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_REG_GLB_SET1_PORT6_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT6_TX_GATING_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + for(pollcnt = 0; pollcnt < RTL8373_MACSEC_POLLCNT; pollcnt++) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_MACSEC_REG_GLB_MASK_PORT6_ADDR, RTL8373_MACSEC_REG_GLB_MASK_PORT6_TX_XGMASK_OFFSET, &tmp_value)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_getAsicRegBit(RTL8373_MACSEC_REG_GLB_MASK_PORT6_ADDR, RTL8373_MACSEC_REG_GLB_MASK_PORT6_TXEN_GMASK_OFFSET, &tmp_gvalue)) != RT_ERR_OK) + return retVal; + + if((tmp_value == 1) && (tmp_gvalue == 1)) + break; + } + + if(pollcnt == RTL8373_MACSEC_POLLCNT) + return RT_ERR_BUSYWAIT_TIMEOUT; + } + else if(port == 7) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_REG_GLB_SET1_PORT7_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT7_TX_GATING_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + for(pollcnt = 0; pollcnt < RTL8373_MACSEC_POLLCNT; pollcnt++) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_MACSEC_REG_GLB_MASK_PORT7_ADDR, RTL8373_MACSEC_REG_GLB_MASK_PORT7_TX_XGMASK_OFFSET, &tmp_value)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_getAsicRegBit(RTL8373_MACSEC_REG_GLB_MASK_PORT7_ADDR, RTL8373_MACSEC_REG_GLB_MASK_PORT7_TXEN_GMASK_OFFSET, &tmp_gvalue)) != RT_ERR_OK) + return retVal; + + if((tmp_value == 1) && (tmp_gvalue == 1)) + break; + } + + if(pollcnt == RTL8373_MACSEC_POLLCNT) + return RT_ERR_BUSYWAIT_TIMEOUT; + } + else + return RT_ERR_INPUT; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_macsec_txgating_cancel + * Description: + * Configure macsec tx gating value + * Input: + * port - port id + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure macsec tx gating value, called after packet flow path changed.. + */ +rtk_api_ret_t dal_rtl8373_macsec_txgating_cancel(rtk_uint32 port) +{ + rtk_api_ret_t retVal; + rtk_uint32 tmp_value,tmp_gvalue; + rtk_uint32 pollcnt; + + if(port == 0) + { + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_REG_GLB_SET1_PORT4_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT4_TX_GATING_OFFSET, 0)) != RT_ERR_OK) + return retVal; + + for(pollcnt = 0; pollcnt < RTL8373_MACSEC_POLLCNT; pollcnt++) + { + if ((retVal = dal_rtl8224_top_regbit_read(RTL8373_MACSEC_REG_GLB_MASK_PORT4_ADDR, RTL8373_MACSEC_REG_GLB_MASK_PORT4_TX_XGMASK_OFFSET, &tmp_value)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_regbit_read(RTL8373_MACSEC_REG_GLB_MASK_PORT4_ADDR, RTL8373_MACSEC_REG_GLB_MASK_PORT4_TXEN_GMASK_OFFSET, &tmp_gvalue)) != RT_ERR_OK) + return retVal; + + if((tmp_value == 0) && (tmp_gvalue == 0)) + break; + } + + if(pollcnt == RTL8373_MACSEC_POLLCNT) + return RT_ERR_BUSYWAIT_TIMEOUT; + } + else if(port == 1) + { + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_REG_GLB_SET1_PORT5_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT5_TX_GATING_OFFSET, 0)) != RT_ERR_OK) + return retVal; + + for(pollcnt = 0; pollcnt < RTL8373_MACSEC_POLLCNT; pollcnt++) + { + if ((retVal = dal_rtl8224_top_regbit_read(RTL8373_MACSEC_REG_GLB_MASK_PORT5_ADDR, RTL8373_MACSEC_REG_GLB_MASK_PORT5_TX_XGMASK_OFFSET, &tmp_value)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_regbit_read(RTL8373_MACSEC_REG_GLB_MASK_PORT5_ADDR, RTL8373_MACSEC_REG_GLB_MASK_PORT5_TXEN_GMASK_OFFSET, &tmp_gvalue)) != RT_ERR_OK) + return retVal; + + if((tmp_value == 0) && (tmp_gvalue == 0)) + break; + } + + if(pollcnt == RTL8373_MACSEC_POLLCNT) + return RT_ERR_BUSYWAIT_TIMEOUT; + } + else if(port == 2) + { + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_REG_GLB_SET1_PORT6_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT6_TX_GATING_OFFSET, 0)) != RT_ERR_OK) + return retVal; + + for(pollcnt = 0; pollcnt < RTL8373_MACSEC_POLLCNT; pollcnt++) + { + if ((retVal = dal_rtl8224_top_regbit_read(RTL8373_MACSEC_REG_GLB_MASK_PORT6_ADDR, RTL8373_MACSEC_REG_GLB_MASK_PORT6_TX_XGMASK_OFFSET, &tmp_value)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_regbit_read(RTL8373_MACSEC_REG_GLB_MASK_PORT6_ADDR, RTL8373_MACSEC_REG_GLB_MASK_PORT6_TXEN_GMASK_OFFSET, &tmp_gvalue)) != RT_ERR_OK) + return retVal; + + if((tmp_value == 0) && (tmp_gvalue == 0)) + break; + } + + if(pollcnt == RTL8373_MACSEC_POLLCNT) + return RT_ERR_BUSYWAIT_TIMEOUT; + } + else if(port == 3) + { + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_REG_GLB_SET1_PORT7_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT7_TX_GATING_OFFSET, 0)) != RT_ERR_OK) + return retVal; + + for(pollcnt = 0; pollcnt < RTL8373_MACSEC_POLLCNT; pollcnt++) + { + if ((retVal = dal_rtl8224_top_regbit_read(RTL8373_MACSEC_REG_GLB_MASK_PORT7_ADDR, RTL8373_MACSEC_REG_GLB_MASK_PORT7_TX_XGMASK_OFFSET, &tmp_value)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_regbit_read(RTL8373_MACSEC_REG_GLB_MASK_PORT7_ADDR, RTL8373_MACSEC_REG_GLB_MASK_PORT7_TXEN_GMASK_OFFSET, &tmp_gvalue)) != RT_ERR_OK) + return retVal; + + if((tmp_value == 0) && (tmp_gvalue == 0)) + break; + } + + if(pollcnt == RTL8373_MACSEC_POLLCNT) + return RT_ERR_BUSYWAIT_TIMEOUT; + } + else if(port == 4) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_REG_GLB_SET1_PORT4_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT4_TX_GATING_OFFSET, 0)) != RT_ERR_OK) + return retVal; + + for(pollcnt = 0; pollcnt < RTL8373_MACSEC_POLLCNT; pollcnt++) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_MACSEC_REG_GLB_MASK_PORT4_ADDR, RTL8373_MACSEC_REG_GLB_MASK_PORT4_TX_XGMASK_OFFSET, &tmp_value)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_getAsicRegBit(RTL8373_MACSEC_REG_GLB_MASK_PORT4_ADDR, RTL8373_MACSEC_REG_GLB_MASK_PORT4_TXEN_GMASK_OFFSET, &tmp_gvalue)) != RT_ERR_OK) + return retVal; + + if((tmp_value == 0) && (tmp_gvalue == 0)) + break; + } + + if(pollcnt == RTL8373_MACSEC_POLLCNT) + return RT_ERR_BUSYWAIT_TIMEOUT; + } + else if(port == 5) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_REG_GLB_SET1_PORT5_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT5_TX_GATING_OFFSET, 0)) != RT_ERR_OK) + return retVal; + + for(pollcnt = 0; pollcnt < RTL8373_MACSEC_POLLCNT; pollcnt++) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_MACSEC_REG_GLB_MASK_PORT5_ADDR, RTL8373_MACSEC_REG_GLB_MASK_PORT5_TX_XGMASK_OFFSET, &tmp_value)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_getAsicRegBit(RTL8373_MACSEC_REG_GLB_MASK_PORT5_ADDR, RTL8373_MACSEC_REG_GLB_MASK_PORT5_TXEN_GMASK_OFFSET, &tmp_gvalue)) != RT_ERR_OK) + return retVal; + + if((tmp_value == 0) && (tmp_gvalue == 0)) + break; + } + + if(pollcnt == RTL8373_MACSEC_POLLCNT) + return RT_ERR_BUSYWAIT_TIMEOUT; + } + else if(port == 6) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_REG_GLB_SET1_PORT6_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT6_TX_GATING_OFFSET, 0)) != RT_ERR_OK) + return retVal; + + for(pollcnt = 0; pollcnt < RTL8373_MACSEC_POLLCNT; pollcnt++) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_MACSEC_REG_GLB_MASK_PORT6_ADDR, RTL8373_MACSEC_REG_GLB_MASK_PORT6_TX_XGMASK_OFFSET, &tmp_value)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_getAsicRegBit(RTL8373_MACSEC_REG_GLB_MASK_PORT6_ADDR, RTL8373_MACSEC_REG_GLB_MASK_PORT6_TXEN_GMASK_OFFSET, &tmp_gvalue)) != RT_ERR_OK) + return retVal; + + if((tmp_value == 0) && (tmp_gvalue == 0)) + break; + } + + if(pollcnt == RTL8373_MACSEC_POLLCNT) + return RT_ERR_BUSYWAIT_TIMEOUT; + } + else if(port == 7) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_REG_GLB_SET1_PORT7_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT7_TX_GATING_OFFSET, 0)) != RT_ERR_OK) + return retVal; + + for(pollcnt = 0; pollcnt < RTL8373_MACSEC_POLLCNT; pollcnt++) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_MACSEC_REG_GLB_MASK_PORT7_ADDR, RTL8373_MACSEC_REG_GLB_MASK_PORT7_TX_XGMASK_OFFSET, &tmp_value)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_getAsicRegBit(RTL8373_MACSEC_REG_GLB_MASK_PORT7_ADDR, RTL8373_MACSEC_REG_GLB_MASK_PORT7_TXEN_GMASK_OFFSET, &tmp_gvalue)) != RT_ERR_OK) + return retVal; + + if((tmp_value == 0) && (tmp_gvalue == 0)) + break; + } + + if(pollcnt == RTL8373_MACSEC_POLLCNT) + return RT_ERR_BUSYWAIT_TIMEOUT; + } + else + return RT_ERR_INPUT; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_macsec_rxIPbypass_set + * Description: + * Configure macsec bypass in MACsec IP function. + * Input: + * port - port id + * enable - enable ip bypass + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure macsec bypass in MACsec IP function. + */ +rtk_api_ret_t dal_rtl8373_macsec_rxIPbypass_set(rtk_uint32 port, rtk_uint32 enable) +{ + rtk_api_ret_t retVal; + + if(port == 0) + { + dal_rtl8373_macsec_rxgating_set(port); + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_REG_GLB_SET1_PORT4_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT4_RX_IPBYPASS_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + dal_rtl8373_macsec_rxgating_cancel(port); + } + else if(port == 1) + { + dal_rtl8373_macsec_rxgating_set(port); + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_REG_GLB_SET1_PORT5_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT5_RX_IPBYPASS_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + dal_rtl8373_macsec_rxgating_cancel(port); + } + else if(port == 2) + { + dal_rtl8373_macsec_rxgating_set(port); + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_REG_GLB_SET1_PORT6_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT6_RX_IPBYPASS_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + dal_rtl8373_macsec_rxgating_cancel(port); + } + else if(port == 3) + { + dal_rtl8373_macsec_rxgating_set(port); + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_REG_GLB_SET1_PORT7_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT7_RX_IPBYPASS_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + dal_rtl8373_macsec_rxgating_cancel(port); + } + else if(port == 4) + { + dal_rtl8373_macsec_rxgating_set(port); + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_REG_GLB_SET1_PORT4_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT4_RX_IPBYPASS_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + dal_rtl8373_macsec_rxgating_cancel(port); + } + else if(port == 5) + { + dal_rtl8373_macsec_rxgating_set(port); + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_REG_GLB_SET1_PORT5_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT5_RX_IPBYPASS_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + dal_rtl8373_macsec_rxgating_cancel(port); + } + else if(port == 6) + { + dal_rtl8373_macsec_rxgating_set(port); + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_REG_GLB_SET1_PORT6_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT6_RX_IPBYPASS_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + dal_rtl8373_macsec_rxgating_cancel(port); + } + else if(port == 7) + { + dal_rtl8373_macsec_rxgating_set(port); + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_REG_GLB_SET1_PORT7_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT7_RX_IPBYPASS_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + dal_rtl8373_macsec_rxgating_cancel(port); + } + else + return RT_ERR_INPUT; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_macsec_rxIPbypass_get + * Description: + * get macsec bypass in MACsec IP function status. + * Input: + * port - port id + * Output: + * enable - enable ip bypass + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will get macsec bypass in MACsec IP function status. + */ +rtk_api_ret_t dal_rtl8373_macsec_rxIPbypass_get(rtk_uint32 port, rtk_uint32 *enable) +{ + rtk_api_ret_t retVal; + + if(port == 0) + { + if ((retVal = dal_rtl8224_top_regbit_read(RTL8373_MACSEC_REG_GLB_SET1_PORT4_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT4_RX_IPBYPASS_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + } + else if(port == 1) + { + if ((retVal = dal_rtl8224_top_regbit_read(RTL8373_MACSEC_REG_GLB_SET1_PORT5_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT5_RX_IPBYPASS_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + } + else if(port == 2) + { + if ((retVal = dal_rtl8224_top_regbit_read(RTL8373_MACSEC_REG_GLB_SET1_PORT6_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT6_RX_IPBYPASS_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + } + else if(port == 3) + { + if ((retVal = dal_rtl8224_top_regbit_read(RTL8373_MACSEC_REG_GLB_SET1_PORT7_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT7_RX_IPBYPASS_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + } + else if(port == 4) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_MACSEC_REG_GLB_SET1_PORT4_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT4_RX_IPBYPASS_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + } + else if(port == 5) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_MACSEC_REG_GLB_SET1_PORT5_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT5_RX_IPBYPASS_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + } + else if(port == 6) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_MACSEC_REG_GLB_SET1_PORT6_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT6_RX_IPBYPASS_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + } + else if(port == 7) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_MACSEC_REG_GLB_SET1_PORT7_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT7_RX_IPBYPASS_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + } + else + return RT_ERR_INPUT; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_macsec_txIPbypass_set + * Description: + * Configure macsec bypass in MACsec IP function. + * Input: + * port - port id + * enable - enable ip bypass + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure macsec bypass in MACsec IP function. + */ +rtk_api_ret_t dal_rtl8373_macsec_txIPbypass_set(rtk_uint32 port, rtk_uint32 enable) +{ + rtk_api_ret_t retVal; + + if(port == 0) + { + dal_rtl8373_macsec_txgating_set(port); + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_REG_GLB_SET1_PORT4_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT4_TX_IPBYPASS_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + dal_rtl8373_macsec_txgating_cancel(port); + } + else if(port == 1) + { + dal_rtl8373_macsec_txgating_set(port); + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_REG_GLB_SET1_PORT5_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT5_TX_IPBYPASS_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + dal_rtl8373_macsec_txgating_cancel(port); + } + else if(port == 2) + { + dal_rtl8373_macsec_txgating_set(port); + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_REG_GLB_SET1_PORT6_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT6_TX_IPBYPASS_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + dal_rtl8373_macsec_txgating_cancel(port); + } + else if(port == 3) + { + dal_rtl8373_macsec_txgating_set(port); + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_REG_GLB_SET1_PORT7_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT7_TX_IPBYPASS_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + dal_rtl8373_macsec_txgating_cancel(port); + } + else if(port == 4) + { + dal_rtl8373_macsec_txgating_set(port); + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_REG_GLB_SET1_PORT4_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT4_TX_IPBYPASS_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + dal_rtl8373_macsec_txgating_cancel(port); + } + else if(port == 5) + { + dal_rtl8373_macsec_txgating_set(port); + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_REG_GLB_SET1_PORT5_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT5_TX_IPBYPASS_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + dal_rtl8373_macsec_txgating_cancel(port); + } + else if(port == 6) + { + dal_rtl8373_macsec_txgating_set(port); + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_REG_GLB_SET1_PORT6_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT6_TX_IPBYPASS_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + dal_rtl8373_macsec_txgating_cancel(port); + } + else if(port == 7) + { + dal_rtl8373_macsec_txgating_set(port); + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_REG_GLB_SET1_PORT7_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT7_TX_IPBYPASS_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + dal_rtl8373_macsec_txgating_cancel(port); + } + else + return RT_ERR_INPUT; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_macsec_txIPbypass_get + * Description: + * get macsec bypass MACsec IP function status. + * Input: + * port - port id + * Output: + * enable - enable ip bypass + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will get macsec bypass MACsec IP function status. + */ +rtk_api_ret_t dal_rtl8373_macsec_txIPbypass_get(rtk_uint32 port, rtk_uint32 *enable) +{ + rtk_api_ret_t retVal; + + if(port == 0) + { + if ((retVal = dal_rtl8224_top_regbit_read(RTL8373_MACSEC_REG_GLB_SET1_PORT4_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT4_TX_IPBYPASS_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + } + else if(port == 1) + { + if ((retVal = dal_rtl8224_top_regbit_read(RTL8373_MACSEC_REG_GLB_SET1_PORT5_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT5_TX_IPBYPASS_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + } + else if(port == 2) + { + if ((retVal = dal_rtl8224_top_regbit_read(RTL8373_MACSEC_REG_GLB_SET1_PORT6_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT6_TX_IPBYPASS_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + } + else if(port == 3) + { + if ((retVal = dal_rtl8224_top_regbit_read(RTL8373_MACSEC_REG_GLB_SET1_PORT7_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT7_TX_IPBYPASS_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + } + else if(port == 4) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_MACSEC_REG_GLB_SET1_PORT4_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT4_TX_IPBYPASS_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + } + else if(port == 5) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_MACSEC_REG_GLB_SET1_PORT5_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT5_TX_IPBYPASS_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + } + else if(port == 6) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_MACSEC_REG_GLB_SET1_PORT6_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT6_TX_IPBYPASS_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + } + else if(port == 7) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_MACSEC_REG_GLB_SET1_PORT7_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT7_TX_IPBYPASS_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + } + else + return RT_ERR_INPUT; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_macsec_rxIPbypass_set + * Description: + * Configure macsec bypass MACsec IP function. + * Input: + * port - port id + * enable - enable ip bypass + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure macsec bypass MACsec IP function. + */ +rtk_api_ret_t dal_rtl8373_macsec_rxbypass_set(rtk_uint32 port, rtk_uint32 enable) +{ + rtk_api_ret_t retVal; + + if(port == 0) + { + dal_rtl8373_macsec_rxgating_set(port); + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_REG_GLB_SET1_PORT4_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT4_RX_MACSECBYPASS_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + dal_rtl8373_macsec_rxgating_cancel(port); + } + else if(port == 1) + { + dal_rtl8373_macsec_rxgating_set(port); + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_REG_GLB_SET1_PORT5_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT5_RX_MACSECBYPASS_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + dal_rtl8373_macsec_rxgating_cancel(port); + } + else if(port == 2) + { + dal_rtl8373_macsec_rxgating_set(port); + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_REG_GLB_SET1_PORT6_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT6_RX_MACSECBYPASS_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + dal_rtl8373_macsec_rxgating_cancel(port); + } + else if(port == 3) + { + dal_rtl8373_macsec_rxgating_set(port); + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_REG_GLB_SET1_PORT7_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT7_RX_MACSECBYPASS_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + dal_rtl8373_macsec_rxgating_cancel(port); + } + else if(port == 4) + { + dal_rtl8373_macsec_rxgating_set(port); + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_REG_GLB_SET1_PORT4_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT4_RX_MACSECBYPASS_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + dal_rtl8373_macsec_rxgating_cancel(port); + } + else if(port == 5) + { + dal_rtl8373_macsec_rxgating_set(port); + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_REG_GLB_SET1_PORT5_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT5_RX_MACSECBYPASS_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + dal_rtl8373_macsec_rxgating_cancel(port); + } + else if(port == 6) + { + dal_rtl8373_macsec_rxgating_set(port); + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_REG_GLB_SET1_PORT6_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT6_RX_MACSECBYPASS_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + dal_rtl8373_macsec_rxgating_cancel(port); + } + else if(port == 7) + { + dal_rtl8373_macsec_rxgating_set(port); + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_REG_GLB_SET1_PORT7_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT7_RX_MACSECBYPASS_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + dal_rtl8373_macsec_rxgating_cancel(port); + } + else + return RT_ERR_INPUT; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_macsec_rxbypass_get + * Description: + * get macsec bypass MACsec IP function status. + * Input: + * port - port id + * Output: + * enable - enable ip bypass + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will get macsec bypass MACsec IP function status. + */ +rtk_api_ret_t dal_rtl8373_macsec_rxbypass_get(rtk_uint32 port, rtk_uint32 *enable) +{ + rtk_api_ret_t retVal; + + if(port == 0) + { + if ((retVal = dal_rtl8224_top_regbit_read(RTL8373_MACSEC_REG_GLB_SET1_PORT4_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT4_RX_MACSECBYPASS_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + } + else if(port == 1) + { + if ((retVal = dal_rtl8224_top_regbit_read(RTL8373_MACSEC_REG_GLB_SET1_PORT5_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT5_RX_MACSECBYPASS_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + } + else if(port == 2) + { + if ((retVal = dal_rtl8224_top_regbit_read(RTL8373_MACSEC_REG_GLB_SET1_PORT6_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT6_RX_MACSECBYPASS_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + } + else if(port == 3) + { + if ((retVal = dal_rtl8224_top_regbit_read(RTL8373_MACSEC_REG_GLB_SET1_PORT7_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT7_RX_MACSECBYPASS_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + } + else if(port == 4) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_MACSEC_REG_GLB_SET1_PORT4_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT4_RX_MACSECBYPASS_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + } + else if(port == 5) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_MACSEC_REG_GLB_SET1_PORT5_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT5_RX_MACSECBYPASS_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + } + else if(port == 6) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_MACSEC_REG_GLB_SET1_PORT6_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT6_RX_MACSECBYPASS_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + } + else if(port == 7) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_MACSEC_REG_GLB_SET1_PORT7_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT7_RX_MACSECBYPASS_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + } + else + return RT_ERR_INPUT; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_macsec_txbypass_set + * Description: + * Configure macsec bypass MACsec IP function. + * Input: + * port - port id + * enable - enable ip bypass + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure macsec bypass MACsec IP function. + */ +rtk_api_ret_t dal_rtl8373_macsec_txbypass_set(rtk_uint32 port, rtk_uint32 enable) +{ + rtk_api_ret_t retVal; + + if(port == 0) + { + dal_rtl8373_macsec_txgating_set(port); + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_REG_GLB_SET1_PORT4_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT4_TX_MACSECBYPASS_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + dal_rtl8373_macsec_txgating_cancel(port); + } + else if(port == 1) + { + dal_rtl8373_macsec_txgating_set(port); + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_REG_GLB_SET1_PORT5_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT5_TX_MACSECBYPASS_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + dal_rtl8373_macsec_txgating_cancel(port); + } + else if(port == 2) + { + dal_rtl8373_macsec_txgating_set(port); + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_REG_GLB_SET1_PORT6_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT6_TX_MACSECBYPASS_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + dal_rtl8373_macsec_txgating_cancel(port); + } + else if(port == 3) + { + dal_rtl8373_macsec_txgating_set(port); + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_REG_GLB_SET1_PORT7_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT7_TX_MACSECBYPASS_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + dal_rtl8373_macsec_txgating_cancel(port); + } + else if(port == 4) + { + dal_rtl8373_macsec_txgating_set(port); + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_REG_GLB_SET1_PORT4_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT4_TX_MACSECBYPASS_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + dal_rtl8373_macsec_txgating_cancel(port); + } + else if(port == 5) + { + dal_rtl8373_macsec_txgating_set(port); + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_REG_GLB_SET1_PORT5_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT5_TX_MACSECBYPASS_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + dal_rtl8373_macsec_txgating_cancel(port); + } + else if(port == 6) + { + dal_rtl8373_macsec_txgating_set(port); + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_REG_GLB_SET1_PORT6_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT6_TX_MACSECBYPASS_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + dal_rtl8373_macsec_txgating_cancel(port); + } + else if(port == 7) + { + dal_rtl8373_macsec_txgating_set(port); + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_REG_GLB_SET1_PORT7_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT7_TX_MACSECBYPASS_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + dal_rtl8373_macsec_txgating_cancel(port); + } + else + return RT_ERR_INPUT; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_macsec_txbypass_get + * Description: + * get macsec bypass MACsec IP function status. + * Input: + * port - port id + * Output: + * enable - enable ip bypass + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will get macsec bypass MACsec IP function status. + */ +rtk_api_ret_t dal_rtl8373_macsec_txbypass_get(rtk_uint32 port, rtk_uint32 *enable) +{ + rtk_api_ret_t retVal; + + if(port == 0) + { + if ((retVal = dal_rtl8224_top_regbit_read(RTL8373_MACSEC_REG_GLB_SET1_PORT4_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT4_TX_MACSECBYPASS_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + } + else if(port == 1) + { + if ((retVal = dal_rtl8224_top_regbit_read(RTL8373_MACSEC_REG_GLB_SET1_PORT5_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT5_TX_MACSECBYPASS_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + } + else if(port == 2) + { + if ((retVal = dal_rtl8224_top_regbit_read(RTL8373_MACSEC_REG_GLB_SET1_PORT6_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT6_TX_MACSECBYPASS_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + } + else if(port == 3) + { + if ((retVal = dal_rtl8224_top_regbit_read(RTL8373_MACSEC_REG_GLB_SET1_PORT7_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT7_TX_MACSECBYPASS_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + } + else if(port == 4) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_MACSEC_REG_GLB_SET1_PORT4_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT4_TX_MACSECBYPASS_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + } + else if(port == 4) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_MACSEC_REG_GLB_SET1_PORT4_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT4_TX_MACSECBYPASS_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + } + else if(port == 5) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_MACSEC_REG_GLB_SET1_PORT5_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT5_TX_MACSECBYPASS_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + } + else if(port == 6) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_MACSEC_REG_GLB_SET1_PORT6_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT6_TX_MACSECBYPASS_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + } + else if(port == 7) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_MACSEC_REG_GLB_SET1_PORT7_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT7_TX_MACSECBYPASS_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + } + else + return RT_ERR_INPUT; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_wrapper_int_control_set + * Description: + * Configure MACsec interrupt. + * Input: + * port - port id + * type - interrupt type + * enable - enable interrupt + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure MACsec interrupt. + * The interrupt trigger status is shown in the following: + * - INT_TYPE_TX_IPE_GLB + * - INT_TYPE_TX_IPESECFAIL + * - INT_TYPE_TX_IPELOCK + * - INT_TYPE_TX_IPELOCK_XG + * - INT_TYPE_RX_IPI_GLB + * - INT_TYPE_RX_IPISECFAIL + * - INT_TYPE_RX_IPILOCK + * - INT_TYPE_RX_IPILOCK_XG + */ +rtk_api_ret_t dal_rtl8373_wrapper_int_control_set(rtk_uint32 port, rtk_macsec_int_type_t type, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + rtk_uint32 tmp_value; + + if(port == 0) + { + if ((retVal = dal_rtl8224_top_reg_read(RTL8373_MACSEC_REG_GLB_IMR_PORT4_ADDR, &tmp_value)) != RT_ERR_OK) + return retVal; + + if(enable == ENABLED) + { + tmp_value |=(1 << type); + + if ((retVal = dal_rtl8224_top_reg_write(RTL8373_MACSEC_REG_GLB_IMR_PORT4_ADDR, tmp_value)) != RT_ERR_OK) + return retVal; + } + else if(enable == DISABLED) + { + tmp_value &= ~(1 << type); + + if ((retVal = dal_rtl8224_top_reg_write(RTL8373_MACSEC_REG_GLB_IMR_PORT4_ADDR, tmp_value)) != RT_ERR_OK) + return retVal; + } + } + else if(port == 1) + { + if ((retVal = dal_rtl8224_top_reg_read(RTL8373_MACSEC_REG_GLB_IMR_PORT5_ADDR, &tmp_value)) != RT_ERR_OK) + return retVal; + + if(enable == ENABLED) + { + tmp_value |=(1 << type); + + if ((retVal = dal_rtl8224_top_reg_write(RTL8373_MACSEC_REG_GLB_IMR_PORT5_ADDR, tmp_value)) != RT_ERR_OK) + return retVal; + } + else if(enable == DISABLED) + { + tmp_value &= ~(1 << type); + + if ((retVal = dal_rtl8224_top_reg_write(RTL8373_MACSEC_REG_GLB_IMR_PORT5_ADDR, tmp_value)) != RT_ERR_OK) + return retVal; + } + } + else if(port == 2) + { + if ((retVal = dal_rtl8224_top_reg_read(RTL8373_MACSEC_REG_GLB_IMR_PORT6_ADDR, &tmp_value)) != RT_ERR_OK) + return retVal; + + if(enable == ENABLED) + { + tmp_value |=(1 << type); + + if ((retVal = dal_rtl8224_top_reg_write(RTL8373_MACSEC_REG_GLB_IMR_PORT6_ADDR, tmp_value)) != RT_ERR_OK) + return retVal; + } + else if(enable == DISABLED) + { + tmp_value &= ~(1 << type); + + if ((retVal = dal_rtl8224_top_reg_write(RTL8373_MACSEC_REG_GLB_IMR_PORT6_ADDR, tmp_value)) != RT_ERR_OK) + return retVal; + } + } + else if(port == 3) + { + if ((retVal = dal_rtl8224_top_reg_read(RTL8373_MACSEC_REG_GLB_IMR_PORT7_ADDR, &tmp_value)) != RT_ERR_OK) + return retVal; + + if(enable == ENABLED) + { + tmp_value |=(1 << type); + + if ((retVal = dal_rtl8224_top_reg_write(RTL8373_MACSEC_REG_GLB_IMR_PORT7_ADDR, tmp_value)) != RT_ERR_OK) + return retVal; + } + else if(enable == DISABLED) + { + tmp_value &= ~(1 << type); + + if ((retVal = dal_rtl8224_top_reg_write(RTL8373_MACSEC_REG_GLB_IMR_PORT7_ADDR, tmp_value)) != RT_ERR_OK) + return retVal; + } + } + else if(port == 4) + { + if ((retVal = rtl8373_getAsicReg(RTL8373_MACSEC_REG_GLB_IMR_PORT4_ADDR, &tmp_value)) != RT_ERR_OK) + return retVal; + + if(enable == ENABLED) + { + tmp_value |=(1 << type); + + if ((retVal = rtl8373_setAsicReg(RTL8373_MACSEC_REG_GLB_IMR_PORT4_ADDR, tmp_value)) != RT_ERR_OK) + return retVal; + } + else if(enable == DISABLED) + { + tmp_value &= ~(1 << type); + + if ((retVal = rtl8373_setAsicReg(RTL8373_MACSEC_REG_GLB_IMR_PORT4_ADDR, tmp_value)) != RT_ERR_OK) + return retVal; + } + } + else if(port == 5) + { + if ((retVal = rtl8373_getAsicReg(RTL8373_MACSEC_REG_GLB_IMR_PORT5_ADDR, &tmp_value)) != RT_ERR_OK) + return retVal; + + if(enable == ENABLED) + { + tmp_value |=(1 << type); + + if ((retVal = rtl8373_setAsicReg(RTL8373_MACSEC_REG_GLB_IMR_PORT5_ADDR, tmp_value)) != RT_ERR_OK) + return retVal; + } + else if(enable == DISABLED) + { + tmp_value &= ~(1 << type); + + if ((retVal = rtl8373_setAsicReg(RTL8373_MACSEC_REG_GLB_IMR_PORT5_ADDR, tmp_value)) != RT_ERR_OK) + return retVal; + } + } + else if(port == 6) + { + if ((retVal = rtl8373_getAsicReg(RTL8373_MACSEC_REG_GLB_IMR_PORT6_ADDR, &tmp_value)) != RT_ERR_OK) + return retVal; + + if(enable == ENABLED) + { + tmp_value |=(1 << type); + + if ((retVal = rtl8373_setAsicReg(RTL8373_MACSEC_REG_GLB_IMR_PORT6_ADDR, tmp_value)) != RT_ERR_OK) + return retVal; + } + else if(enable == DISABLED) + { + tmp_value &= ~(1 << type); + + if ((retVal = rtl8373_setAsicReg(RTL8373_MACSEC_REG_GLB_IMR_PORT6_ADDR, tmp_value)) != RT_ERR_OK) + return retVal; + } + } + else if(port == 7) + { + if ((retVal = rtl8373_getAsicReg(RTL8373_MACSEC_REG_GLB_IMR_PORT7_ADDR, &tmp_value)) != RT_ERR_OK) + return retVal; + + if(enable == ENABLED) + { + tmp_value |=(1 << type); + + if ((retVal = rtl8373_setAsicReg(RTL8373_MACSEC_REG_GLB_IMR_PORT7_ADDR, tmp_value)) != RT_ERR_OK) + return retVal; + } + else if(enable == DISABLED) + { + tmp_value &= ~(1 << type); + + if ((retVal = rtl8373_setAsicReg(RTL8373_MACSEC_REG_GLB_IMR_PORT7_ADDR, tmp_value)) != RT_ERR_OK) + return retVal; + } + } + else + return RT_ERR_INPUT; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_wrapper_int_control_get + * Description: + * gonfigure MACsec interrupt. + * Input: + * port - port id + * type - interrupt type + * Output: + * pEnable - enable interrupt + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will get MACsec interrupt. + * The interrupt trigger status is shown in the following: + * - INT_TYPE_TX_IPE_GLB + * - INT_TYPE_TX_IPESECFAIL + * - INT_TYPE_TX_IPELOCK + * - INT_TYPE_TX_IPELOCK_XG + * - INT_TYPE_RX_IPI_GLB + * - INT_TYPE_RX_IPISECFAIL + * - INT_TYPE_RX_IPILOCK + * - INT_TYPE_RX_IPILOCK_XG + */ +rtk_api_ret_t dal_rtl8373_wrapper_int_control_get(rtk_uint32 port, rtk_macsec_int_type_t type, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + rtk_uint32 tmp_value; + + if(port == 0) + { + if ((retVal = dal_rtl8224_top_reg_read(RTL8373_MACSEC_REG_GLB_IMR_PORT4_ADDR, &tmp_value)) != RT_ERR_OK) + return retVal; + + if(0 == (tmp_value & (1 << type))) + { + *pEnable = DISABLED; + } + else if(1 == (tmp_value & (1 << type))) + { + *pEnable = ENABLED; + } + } + else if(port == 1) + { + if ((retVal = dal_rtl8224_top_reg_read(RTL8373_MACSEC_REG_GLB_IMR_PORT5_ADDR, &tmp_value)) != RT_ERR_OK) + return retVal; + + if(0 == (tmp_value & (1 << type))) + { + *pEnable = DISABLED; + } + else if(1 == (tmp_value & (1 << type))) + { + *pEnable = ENABLED; + } + } + else if(port == 2) + { + if ((retVal = dal_rtl8224_top_reg_read(RTL8373_MACSEC_REG_GLB_IMR_PORT6_ADDR, &tmp_value)) != RT_ERR_OK) + return retVal; + + if(0 == (tmp_value & (1 << type))) + { + *pEnable = DISABLED; + } + else if(1 == (tmp_value & (1 << type))) + { + *pEnable = ENABLED; + } + } + else if(port == 3) + { + if ((retVal = dal_rtl8224_top_reg_read(RTL8373_MACSEC_REG_GLB_IMR_PORT7_ADDR, &tmp_value)) != RT_ERR_OK) + return retVal; + + if(0 == (tmp_value & (1 << type))) + { + *pEnable = DISABLED; + } + else if(1 == (tmp_value & (1 << type))) + { + *pEnable = ENABLED; + } + } + else if(port == 4) + { + if ((retVal = rtl8373_getAsicReg(RTL8373_MACSEC_REG_GLB_IMR_PORT4_ADDR, &tmp_value)) != RT_ERR_OK) + return retVal; + + if(0 == (tmp_value & (1 << type))) + { + *pEnable = DISABLED; + } + else if(1 == (tmp_value & (1 << type))) + { + *pEnable = ENABLED; + } + } + else if(port == 5) + { + if ((retVal = rtl8373_getAsicReg(RTL8373_MACSEC_REG_GLB_IMR_PORT5_ADDR, &tmp_value)) != RT_ERR_OK) + return retVal; + + if(0 == (tmp_value & (1 << type))) + { + *pEnable = DISABLED; + } + else if(1 == (tmp_value & (1 << type))) + { + *pEnable = ENABLED; + } + } + else if(port == 6) + { + if ((retVal = rtl8373_getAsicReg(RTL8373_MACSEC_REG_GLB_IMR_PORT6_ADDR, &tmp_value)) != RT_ERR_OK) + return retVal; + + if(0 == (tmp_value & (1 << type))) + { + *pEnable = DISABLED; + } + else if(1 == (tmp_value & (1 << type))) + { + *pEnable = ENABLED; + } + } + else if(port == 7) + { + if ((retVal = rtl8373_getAsicReg(RTL8373_MACSEC_REG_GLB_IMR_PORT7_ADDR, &tmp_value)) != RT_ERR_OK) + return retVal; + + if(0 == (tmp_value & (1 << type))) + { + *pEnable = DISABLED; + } + else if(1 == (tmp_value & (1 << type))) + { + *pEnable = ENABLED; + } + } + else + return RT_ERR_INPUT; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_wrapper_int_status_set + * Description: + * Configure MACsec interrupt status. + * Input: + * port - port id + * statusMask - interrupt status mask + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will clean MACsec interrupt status when interrupt happened. + * The interrupt trigger status is shown in the following: + * - INT_TYPE_TX_IPE_GLB [bit[0]] + * - INT_TYPE_TX_IPESECFAIL [bit[1]] + * - INT_TYPE_TX_IPELOCK [bit[2]] + * - INT_TYPE_TX_IPELOCK_XG [bit[3]] + * - INT_TYPE_RX_IPI_GLB [bit[8]] + * - INT_TYPE_RX_IPISECFAIL [bit[9]] + * - INT_TYPE_RX_IPILOCK [bit[10]] + * - INT_TYPE_RX_IPILOCK_XG [bit[11]] + */ +rtk_api_ret_t dal_rtl8373_wrapper_int_status_set(rtk_uint32 port, rtk_uint32 statusMask) +{ + rtk_api_ret_t retVal; + + if(port == 0) + { + if ((retVal = dal_rtl8224_top_reg_write(RTL8373_MACSEC_REG_GLB_ISR_PORT4_ADDR, statusMask)) != RT_ERR_OK) + return retVal; + } + else if(port == 1) + { + if ((retVal = dal_rtl8224_top_reg_write(RTL8373_MACSEC_REG_GLB_ISR_PORT5_ADDR, statusMask)) != RT_ERR_OK) + return retVal; + } + else if(port == 2) + { + if ((retVal = dal_rtl8224_top_reg_write(RTL8373_MACSEC_REG_GLB_ISR_PORT6_ADDR, statusMask)) != RT_ERR_OK) + return retVal; + } + else if(port == 3) + { + if ((retVal = dal_rtl8224_top_reg_write(RTL8373_MACSEC_REG_GLB_ISR_PORT7_ADDR, statusMask)) != RT_ERR_OK) + return retVal; + } + else if(port == 4) + { + if ((retVal = rtl8373_setAsicReg(RTL8373_MACSEC_REG_GLB_ISR_PORT4_ADDR, statusMask)) != RT_ERR_OK) + return retVal; + } + else if(port == 5) + { + if ((retVal = rtl8373_setAsicReg(RTL8373_MACSEC_REG_GLB_ISR_PORT5_ADDR, statusMask)) != RT_ERR_OK) + return retVal; + } + else if(port == 6) + { + if ((retVal = rtl8373_setAsicReg(RTL8373_MACSEC_REG_GLB_ISR_PORT6_ADDR, statusMask)) != RT_ERR_OK) + return retVal; + } + else if(port == 7) + { + if ((retVal = rtl8373_setAsicReg(RTL8373_MACSEC_REG_GLB_ISR_PORT7_ADDR, statusMask)) != RT_ERR_OK) + return retVal; + } + else + return RT_ERR_INPUT; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_wrapper_int_status_get + * Description: + * Configure MACsec interrupt status. + * Input: + * port - port id + + * Output: + * pStatusMask - interrupt status mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will clean MACsec interrupt status when interrupt happened. + * The interrupt trigger status is shown in the following: + * - INT_TYPE_TX_IPE_GLB [bit[0]] + * - INT_TYPE_TX_IPESECFAIL [bit[1]] + * - INT_TYPE_TX_IPELOCK [bit[2]] + * - INT_TYPE_TX_IPELOCK_XG [bit[3]] + * - INT_TYPE_RX_IPI_GLB [bit[8]] + * - INT_TYPE_RX_IPISECFAIL [bit[9]] + * - INT_TYPE_RX_IPILOCK [bit[10]] + * - INT_TYPE_RX_IPILOCK_XG [bit[11]] + */ +rtk_api_ret_t dal_rtl8373_wrapper_int_status_get(rtk_uint32 port, rtk_uint32 *pStatusMask) +{ + rtk_api_ret_t retVal; + rtk_uint32 tmp_value; + + if(port == 0) + { + if ((retVal = dal_rtl8224_top_reg_read(RTL8373_MACSEC_REG_GLB_ISR_PORT4_ADDR, &tmp_value)) != RT_ERR_OK) + return retVal; + } + else if(port == 1) + { + if ((retVal = dal_rtl8224_top_reg_read(RTL8373_MACSEC_REG_GLB_ISR_PORT5_ADDR, &tmp_value)) != RT_ERR_OK) + return retVal; + } + else if(port == 2) + { + if ((retVal = dal_rtl8224_top_reg_read(RTL8373_MACSEC_REG_GLB_ISR_PORT6_ADDR, &tmp_value)) != RT_ERR_OK) + return retVal; + } + else if(port == 3) + { + if ((retVal = dal_rtl8224_top_reg_read(RTL8373_MACSEC_REG_GLB_ISR_PORT7_ADDR, &tmp_value)) != RT_ERR_OK) + return retVal; + } + else if(port == 4) + { + if ((retVal = rtl8373_getAsicReg(RTL8373_MACSEC_REG_GLB_ISR_PORT4_ADDR, &tmp_value)) != RT_ERR_OK) + return retVal; + } + else if(port == 5) + { + if ((retVal = rtl8373_getAsicReg(RTL8373_MACSEC_REG_GLB_ISR_PORT5_ADDR, &tmp_value)) != RT_ERR_OK) + return retVal; + } + else if(port == 6) + { + if ((retVal = rtl8373_getAsicReg(RTL8373_MACSEC_REG_GLB_ISR_PORT6_ADDR, &tmp_value)) != RT_ERR_OK) + return retVal; + } + else if(port == 7) + { + if ((retVal = rtl8373_getAsicReg(RTL8373_MACSEC_REG_GLB_ISR_PORT7_ADDR, &tmp_value)) != RT_ERR_OK) + return retVal; + } + else + return RT_ERR_INPUT; + + *pStatusMask = tmp_value & 0xf0f; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_wrapper_mib_reset + * Description: + * Configure wrapper mib reset. + * Input: + * port - port id + * reset - reset value + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure wrapper mib reset. + */ +rtk_api_ret_t dal_rtl8373_wrapper_mib_reset(rtk_uint32 port, rtk_uint32 reset) +{ + rtk_api_ret_t retVal; + + if(port == 0) + { + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_REG_GLB_SET1_PORT4_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT4_MIBCNT_SWRST_N_OFFSET, reset?0:1)) != RT_ERR_OK) + return retVal; + } + else if(port == 1) + { + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_REG_GLB_SET1_PORT5_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT5_MIBCNT_SWRST_N_OFFSET, reset?0:1)) != RT_ERR_OK) + return retVal; + } + else if(port == 2) + { + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_REG_GLB_SET1_PORT6_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT6_MIBCNT_SWRST_N_OFFSET, reset?0:1)) != RT_ERR_OK) + return retVal; + } + else if(port == 3) + { + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_REG_GLB_SET1_PORT7_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT7_MIBCNT_SWRST_N_OFFSET, reset?0:1)) != RT_ERR_OK) + return retVal; + } + else if(port == 4) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_REG_GLB_SET1_PORT4_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT4_MIBCNT_SWRST_N_OFFSET, reset?0:1)) != RT_ERR_OK) + return retVal; + } + else if(port == 5) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_REG_GLB_SET1_PORT5_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT5_MIBCNT_SWRST_N_OFFSET, reset?0:1)) != RT_ERR_OK) + return retVal; + } + else if(port == 6) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_REG_GLB_SET1_PORT6_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT6_MIBCNT_SWRST_N_OFFSET, reset?0:1)) != RT_ERR_OK) + return retVal; + } + else if(port == 7) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_REG_GLB_SET1_PORT7_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT7_MIBCNT_SWRST_N_OFFSET, reset?0:1)) != RT_ERR_OK) + return retVal; + } + else + return RT_ERR_INPUT; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_wrapper_mib_counter + * Description: + * get wrapper mib counters. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will get wrapper mib counters. + */ +rtk_api_ret_t dal_rtl8373_wrapper_mib_counter(rtk_uint32 port, RTL8373_WRAPPER_MIBCOUNTER mibIdx, rtk_uint64* pCounter) +{ + rtk_api_ret_t retVal; + rtk_uint32 tmp_value_L; + rtk_uint32 tmp_value_H; + rtk_uint64 tmp; + + if(port == 0) + { + if((mibIdx == TXSYS_OK) || (mibIdx == TXLINE_OK) || (mibIdx == TXLINE_OK) || (mibIdx == TXLINE_OK)) + { + if ((retVal = dal_rtl8224_top_reg_read(RTL8373_MACSEC_TXSYSCRCERR_CNT_PORT4_ADDR + mibIdx * 0x4, &tmp_value_L)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_reg_read(RTL8373_MACSEC_TXSYSCRCERR_CNT_PORT4_ADDR + (mibIdx + 1) * 0x4, &tmp_value_H)) != RT_ERR_OK) + return retVal; + + tmp = tmp_value_H; + *pCounter = (tmp << 32) | tmp_value_L; + + } + else + { + if ((retVal = dal_rtl8224_top_reg_read(RTL8373_MACSEC_TXSYSCRCERR_CNT_PORT4_ADDR + mibIdx * 0x4, (rtk_uint32 *)pCounter)) != RT_ERR_OK) + return retVal; + } + } + else if(port == 1) + { + if((mibIdx == TXSYS_OK) || (mibIdx == TXLINE_OK) || (mibIdx == TXLINE_OK) || (mibIdx == TXLINE_OK)) + { + if ((retVal = dal_rtl8224_top_reg_read(RTL8373_MACSEC_TXSYSCRCERR_CNT_PORT5_ADDR + mibIdx * 0x4, &tmp_value_L)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_reg_read(RTL8373_MACSEC_TXSYSCRCERR_CNT_PORT5_ADDR + (mibIdx + 1) * 0x4, &tmp_value_H)) != RT_ERR_OK) + return retVal; + + tmp = tmp_value_H; + *pCounter = (tmp << 32) | tmp_value_L; + } + else + { + if ((retVal = dal_rtl8224_top_reg_read(RTL8373_MACSEC_TXSYSCRCERR_CNT_PORT5_ADDR + mibIdx * 0x4, (rtk_uint32 *)pCounter)) != RT_ERR_OK) + return retVal; + } + } + else if(port == 2) + { + if((mibIdx == TXSYS_OK) || (mibIdx == TXLINE_OK) || (mibIdx == TXLINE_OK) || (mibIdx == TXLINE_OK)) + { + if ((retVal = dal_rtl8224_top_reg_read(RTL8373_MACSEC_TXSYSCRCERR_CNT_PORT6_ADDR + mibIdx * 0x4, &tmp_value_L)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_reg_read(RTL8373_MACSEC_TXSYSCRCERR_CNT_PORT6_ADDR + (mibIdx + 1) * 0x4, &tmp_value_H)) != RT_ERR_OK) + return retVal; + + tmp = tmp_value_H; + *pCounter = (tmp << 32) | tmp_value_L; + } + else + { + if ((retVal = dal_rtl8224_top_reg_read(RTL8373_MACSEC_TXSYSCRCERR_CNT_PORT6_ADDR + mibIdx * 0x4, (rtk_uint32 *)pCounter)) != RT_ERR_OK) + return retVal; + } + } + else if(port == 3) + { + if((mibIdx == TXSYS_OK) || (mibIdx == TXLINE_OK) || (mibIdx == TXLINE_OK) || (mibIdx == TXLINE_OK)) + { + if ((retVal = dal_rtl8224_top_reg_read(RTL8373_MACSEC_TXSYSCRCERR_CNT_PORT7_ADDR + mibIdx * 0x4, &tmp_value_L)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8224_top_reg_read(RTL8373_MACSEC_TXSYSCRCERR_CNT_PORT7_ADDR + (mibIdx + 1) * 0x4, &tmp_value_H)) != RT_ERR_OK) + return retVal; + + tmp = tmp_value_H; + *pCounter = (tmp << 32) | tmp_value_L; + } + else + { + if ((retVal = dal_rtl8224_top_reg_read(RTL8373_MACSEC_TXSYSCRCERR_CNT_PORT7_ADDR + mibIdx * 0x4, (rtk_uint32 *)pCounter)) != RT_ERR_OK) + return retVal; + } + } + else if(port == 4) + { + if((mibIdx == TXSYS_OK) || (mibIdx == TXLINE_OK) || (mibIdx == TXLINE_OK) || (mibIdx == TXLINE_OK)) + { + if ((retVal = rtl8373_getAsicReg(RTL8373_MACSEC_TXSYSCRCERR_CNT_PORT4_ADDR + mibIdx * 0x4, &tmp_value_L)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_getAsicReg(RTL8373_MACSEC_TXSYSCRCERR_CNT_PORT4_ADDR + (mibIdx + 1) * 0x4, &tmp_value_H)) != RT_ERR_OK) + return retVal; + + tmp = tmp_value_H; + *pCounter = (tmp << 32) | tmp_value_L; + + } + else + { + if ((retVal = rtl8373_getAsicReg(RTL8373_MACSEC_TXSYSCRCERR_CNT_PORT4_ADDR + mibIdx * 0x4, (rtk_uint32 *)pCounter)) != RT_ERR_OK) + return retVal; + } + } + else if(port == 5) + { + if((mibIdx == TXSYS_OK) || (mibIdx == TXLINE_OK) || (mibIdx == TXLINE_OK) || (mibIdx == TXLINE_OK)) + { + if ((retVal = rtl8373_getAsicReg(RTL8373_MACSEC_TXSYSCRCERR_CNT_PORT5_ADDR + mibIdx * 0x4, &tmp_value_L)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_getAsicReg(RTL8373_MACSEC_TXSYSCRCERR_CNT_PORT5_ADDR + (mibIdx + 1) * 0x4, &tmp_value_H)) != RT_ERR_OK) + return retVal; + + tmp = tmp_value_H; + *pCounter = (tmp << 32) | tmp_value_L; + } + else + { + if ((retVal = rtl8373_getAsicReg(RTL8373_MACSEC_TXSYSCRCERR_CNT_PORT5_ADDR + mibIdx * 0x4, (rtk_uint32 *)pCounter)) != RT_ERR_OK) + return retVal; + } + } + else if(port == 6) + { + if((mibIdx == TXSYS_OK) || (mibIdx == TXLINE_OK) || (mibIdx == TXLINE_OK) || (mibIdx == TXLINE_OK)) + { + if ((retVal = rtl8373_getAsicReg(RTL8373_MACSEC_TXSYSCRCERR_CNT_PORT6_ADDR + mibIdx * 0x4, &tmp_value_L)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_getAsicReg(RTL8373_MACSEC_TXSYSCRCERR_CNT_PORT6_ADDR + (mibIdx + 1) * 0x4, &tmp_value_H)) != RT_ERR_OK) + return retVal; + + tmp = tmp_value_H; + *pCounter = (tmp << 32) | tmp_value_L; + } + else + { + if ((retVal = rtl8373_getAsicReg(RTL8373_MACSEC_TXSYSCRCERR_CNT_PORT6_ADDR + mibIdx * 0x4, (rtk_uint32 *)pCounter)) != RT_ERR_OK) + return retVal; + } + } + else if(port == 7) + { + if((mibIdx == TXSYS_OK) || (mibIdx == TXLINE_OK) || (mibIdx == TXLINE_OK) || (mibIdx == TXLINE_OK)) + { + if ((retVal = rtl8373_getAsicReg(RTL8373_MACSEC_TXSYSCRCERR_CNT_PORT7_ADDR + mibIdx * 0x4, &tmp_value_L)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_getAsicReg(RTL8373_MACSEC_TXSYSCRCERR_CNT_PORT7_ADDR + (mibIdx + 1) * 0x4, &tmp_value_H)) != RT_ERR_OK) + return retVal; + + tmp = tmp_value_H; + *pCounter = (tmp << 32) | tmp_value_L; + } + else + { + if ((retVal = rtl8373_getAsicReg(RTL8373_MACSEC_TXSYSCRCERR_CNT_PORT7_ADDR + mibIdx * 0x4, (rtk_uint32 *)pCounter)) != RT_ERR_OK) + return retVal; + } + } + else + return RT_ERR_INPUT; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_macsec_ipg_len_set + * Description: + * mac mode MACsec ipg length set. + * Input: + * port - port number + * length - ipg length + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will set mac mode MACsec ipg length. + */ +rtk_api_ret_t dal_rtl8373_macsec_ipg_len_set(rtk_uint32 port, rtk_uint32 length) +{ + rtk_api_ret_t retVal; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_MAC_MACSEC_IPG_CFG_ADDR(port), RTL8373_MAC_MACSEC_IPG_CFG_MACSEC_IPG_LENGTH_MASK, length)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_macsec_ipg_len_get + * Description: + * mac mode MACsec ipg length get. + * Input: + * port - port number + * Output: + * plength - ipg length + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will get mac mode MACsec ipg length. + */ +rtk_api_ret_t dal_rtl8373_macsec_ipg_len_get(rtk_uint32 port, rtk_uint32 *plength) +{ + rtk_api_ret_t retVal; + rtk_uint32 length = 0; + + if ((retVal = rtl8373_getAsicRegBits(RTL8373_MAC_MACSEC_IPG_CFG_ADDR(port), RTL8373_MAC_MACSEC_IPG_CFG_MACSEC_IPG_LENGTH_MASK, &length)) != RT_ERR_OK) + return retVal; + + *plength = length; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_macsec_ipg_mode_set + * Description: + * mac mode MACsec ipg mode set. + * Input: + * port - port number + * mode - ipg config mode + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will set mac mode MACsec ipg mode. + * mode[1:0]: + 0: don't insert ipg for macsec + 1: insert ipg for macsec according to macsec feedback signal + 2: insert ipg for masec according to ethertype & cfg_macsec_ipg_length + 3: always insert ipg for macsec, length according to cfg_macsec_ipg_length + */ +rtk_api_ret_t dal_rtl8373_macsec_ipg_mode_set(rtk_uint32 port, rtk_uint32 mode) +{ + rtk_api_ret_t retVal; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_MAC_MACSEC_IPG_CFG_ADDR(port), RTL8373_MAC_MACSEC_IPG_CFG_MACSEC_IPG_MODE_MASK, mode)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_macsec_ipg_mode_get + * Description: + * mac mode MACsec ipg mode get. + * Input: + * port - port number + * Output: + * pmode - ipg config mode + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will get mac mode MACsec ipg mode. + * mode[1:0]: + 0: don't insert ipg for macsec + 1: insert ipg for macsec according to macsec feedback signal + 2: insert ipg for masec according to ethertype & cfg_macsec_ipg_length + 3: always insert ipg for macsec, length according to cfg_macsec_ipg_length + */ +rtk_api_ret_t dal_rtl8373_macsec_ipg_mode_get(rtk_uint32 port, rtk_uint32 *pmode) +{ + rtk_api_ret_t retVal; + rtk_uint32 mode = 0; + + if ((retVal = rtl8373_getAsicRegBits(RTL8373_MAC_MACSEC_IPG_CFG_ADDR(port), RTL8373_MAC_MACSEC_IPG_CFG_MACSEC_IPG_MODE_MASK, &mode)) != RT_ERR_OK) + return retVal; + + *pmode = mode; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_macsec_eth_set + * Description: + * mac mode MACsec eth set. + * Input: + * port - port number + * entry - entry number(0-7) + * ethertype - ether type value + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will set mac mode MACsec eth. + */ +rtk_api_ret_t dal_rtl8373_macsec_eth_set(rtk_uint32 port, rtk_uint32 entry, rtk_uint32 ethertype) +{ + rtk_api_ret_t retVal; + + switch(entry) + { + case 0: + if ((retVal = rtl8373_setAsicRegBits(RTL8373_MAC_MACSEC_ETH_1_0_ADDR(port), RTL8373_MAC_MACSEC_ETH_1_0_MACSEC_ETH_0_MASK, ethertype)) != RT_ERR_OK) + return retVal; + break; + case 1: + if ((retVal = rtl8373_setAsicRegBits(RTL8373_MAC_MACSEC_ETH_1_0_ADDR(port), RTL8373_MAC_MACSEC_ETH_1_0_MACSEC_ETH_1_MASK, ethertype)) != RT_ERR_OK) + return retVal; + break; + case 2: + if ((retVal = rtl8373_setAsicRegBits(RTL8373_MAC_MACSEC_ETH_3_2_ADDR(port), RTL8373_MAC_MACSEC_ETH_3_2_MACSEC_ETH_2_MASK, ethertype)) != RT_ERR_OK) + return retVal; + break; + case 3: + if ((retVal = rtl8373_setAsicRegBits(RTL8373_MAC_MACSEC_ETH_3_2_ADDR(port), RTL8373_MAC_MACSEC_ETH_3_2_MACSEC_ETH_3_MASK, ethertype)) != RT_ERR_OK) + return retVal; + break; + case 4: + if ((retVal = rtl8373_setAsicRegBits(RTL8373_MAC_MACSEC_ETH_5_4_ADDR(port), RTL8373_MAC_MACSEC_ETH_5_4_MACSEC_ETH_4_MASK, ethertype)) != RT_ERR_OK) + return retVal; + break; + case 5: + if ((retVal = rtl8373_setAsicRegBits(RTL8373_MAC_MACSEC_ETH_5_4_ADDR(port), RTL8373_MAC_MACSEC_ETH_5_4_MACSEC_ETH_5_MASK, ethertype)) != RT_ERR_OK) + return retVal; + break; + case 6: + if ((retVal = rtl8373_setAsicRegBits(RTL8373_MAC_MACSEC_ETH_7_6_ADDR(port), RTL8373_MAC_MACSEC_ETH_7_6_MACSEC_ETH_6_MASK, ethertype)) != RT_ERR_OK) + return retVal; + break; + case 7: + if ((retVal = rtl8373_setAsicRegBits(RTL8373_MAC_MACSEC_ETH_7_6_ADDR(port), RTL8373_MAC_MACSEC_ETH_7_6_MACSEC_ETH_7_MASK, ethertype)) != RT_ERR_OK) + return retVal; + break; + default: + return RT_ERR_INPUT; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_macsec_eth_get + * Description: + * mac mode MACsec eth get. + * Input: + * port - port number + * entry - entry number(0-7) + * Output: + * pethertype - ether type value + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will get mac mode MACsec eth. + */ +rtk_api_ret_t dal_rtl8373_macsec_eth_get(rtk_uint32 port, rtk_uint32 entry, rtk_uint32 *pethertype) +{ + rtk_api_ret_t retVal; + rtk_uint32 ethertype = 0; + + switch(entry) + { + case 0: + if ((retVal = rtl8373_getAsicRegBits(RTL8373_MAC_MACSEC_ETH_1_0_ADDR(port), RTL8373_MAC_MACSEC_ETH_1_0_MACSEC_ETH_0_MASK, ðertype)) != RT_ERR_OK) + return retVal; + break; + case 1: + if ((retVal = rtl8373_getAsicRegBits(RTL8373_MAC_MACSEC_ETH_1_0_ADDR(port), RTL8373_MAC_MACSEC_ETH_1_0_MACSEC_ETH_1_MASK, ðertype)) != RT_ERR_OK) + return retVal; + break; + case 2: + if ((retVal = rtl8373_getAsicRegBits(RTL8373_MAC_MACSEC_ETH_3_2_ADDR(port), RTL8373_MAC_MACSEC_ETH_3_2_MACSEC_ETH_2_MASK, ðertype)) != RT_ERR_OK) + return retVal; + break; + case 3: + if ((retVal = rtl8373_getAsicRegBits(RTL8373_MAC_MACSEC_ETH_3_2_ADDR(port), RTL8373_MAC_MACSEC_ETH_3_2_MACSEC_ETH_3_MASK, ðertype)) != RT_ERR_OK) + return retVal; + break; + case 4: + if ((retVal = rtl8373_getAsicRegBits(RTL8373_MAC_MACSEC_ETH_5_4_ADDR(port), RTL8373_MAC_MACSEC_ETH_5_4_MACSEC_ETH_4_MASK, ðertype)) != RT_ERR_OK) + return retVal; + break; + case 5: + if ((retVal = rtl8373_getAsicRegBits(RTL8373_MAC_MACSEC_ETH_5_4_ADDR(port), RTL8373_MAC_MACSEC_ETH_5_4_MACSEC_ETH_5_MASK, ðertype)) != RT_ERR_OK) + return retVal; + break; + case 6: + if ((retVal = rtl8373_getAsicRegBits(RTL8373_MAC_MACSEC_ETH_7_6_ADDR(port), RTL8373_MAC_MACSEC_ETH_7_6_MACSEC_ETH_6_MASK, ðertype)) != RT_ERR_OK) + return retVal; + break; + case 7: + if ((retVal = rtl8373_getAsicRegBits(RTL8373_MAC_MACSEC_ETH_7_6_ADDR(port), RTL8373_MAC_MACSEC_ETH_7_6_MACSEC_ETH_7_MASK, ðertype)) != RT_ERR_OK) + return retVal; + break; + default: + return RT_ERR_INPUT; + } + + *pethertype = ethertype; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_macsec_init + * Description: + * Initialize MACsec information. + * Input: + * port_mask - port mask, bit[4:7] + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will initialize MACsec information. + */ +rtk_api_ret_t dal_rtl8373_macsec_init(rtk_uint32 port_mask) +{ + rtk_api_ret_t retVal; + rtk_uint32 phy_data; + rtk_uint32 tmp_value; + rtk_uint32 index = 0; + rtk_uint32 port; + + dal_rtl8373_mdc_en(ENABLED); + + for(port = 0; port < 8; port++) + { + if(port_mask & (1 << port)) + { + /* check phy if link up*/ + if ((retVal = dal_rtl8373_phy_read(port, 7, 1, &phy_data)) != RT_ERR_OK) + return retVal; + + if(((phy_data >> 2) & 0x1) != 1) + return RT_ERR_PHY_LINK_DOWN; + + /* enable macsec egress enable and ingress enable */ + if((retVal = dal_rtl8373_macsec_enable_set(port, ENABLED, ENABLED)) != RT_ERR_OK) + return retVal; + + if((retVal = dal_rtl8373_macsec_egress_get(port, RTL8373_MACSEC_EIP160_VERSION, &tmp_value)) != RT_ERR_OK) + return retVal; + + dal_rtl8373_macsec_rxIPbypass_set(port, DISABLED); + dal_rtl8373_macsec_txIPbypass_set(port, DISABLED); + dal_rtl8373_macsec_rxbypass_set(port, DISABLED); + dal_rtl8373_macsec_txbypass_set(port, DISABLED); + + + if(port == 0) + { + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_REG_GLB_SET1_PORT4_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT4_TX_SWRST_EN_OFFSET, 1)) != RT_ERR_OK) + return retVal; + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_REG_GLB_SET1_PORT4_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT4_RX_SWRST_EN_OFFSET, 1)) != RT_ERR_OK) + return retVal; + } + else if(port == 1) + { + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_REG_GLB_SET1_PORT5_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT5_TX_SWRST_EN_OFFSET, 1)) != RT_ERR_OK) + return retVal; + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_REG_GLB_SET1_PORT5_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT5_RX_SWRST_EN_OFFSET, 1)) != RT_ERR_OK) + return retVal; + } + else if(port == 2) + { + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_REG_GLB_SET1_PORT6_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT6_TX_SWRST_EN_OFFSET, 1)) != RT_ERR_OK) + return retVal; + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_REG_GLB_SET1_PORT6_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT6_RX_SWRST_EN_OFFSET, 1)) != RT_ERR_OK) + return retVal; + } + else if(port == 3) + { + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_REG_GLB_SET1_PORT7_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT7_TX_SWRST_EN_OFFSET, 1)) != RT_ERR_OK) + return retVal; + if ((retVal = dal_rtl8224_top_regbit_write(RTL8373_MACSEC_REG_GLB_SET1_PORT7_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT7_RX_SWRST_EN_OFFSET, 1)) != RT_ERR_OK) + return retVal; + } + else if(port == 4) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_REG_GLB_SET1_PORT4_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT4_TX_SWRST_EN_OFFSET, 1)) != RT_ERR_OK) + return retVal; + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_REG_GLB_SET1_PORT4_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT4_RX_SWRST_EN_OFFSET, 1)) != RT_ERR_OK) + return retVal; + } + else if(port == 5) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_REG_GLB_SET1_PORT5_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT5_TX_SWRST_EN_OFFSET, 1)) != RT_ERR_OK) + return retVal; + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_REG_GLB_SET1_PORT5_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT5_RX_SWRST_EN_OFFSET, 1)) != RT_ERR_OK) + return retVal; + } + else if(port == 6) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_REG_GLB_SET1_PORT6_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT6_TX_SWRST_EN_OFFSET, 1)) != RT_ERR_OK) + return retVal; + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_REG_GLB_SET1_PORT6_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT6_RX_SWRST_EN_OFFSET, 1)) != RT_ERR_OK) + return retVal; + } + else if(port == 7) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_REG_GLB_SET1_PORT7_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT7_TX_SWRST_EN_OFFSET, 1)) != RT_ERR_OK) + return retVal; + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MACSEC_REG_GLB_SET1_PORT7_ADDR, RTL8373_MACSEC_REG_GLB_SET1_PORT7_RX_SWRST_EN_OFFSET, 1)) != RT_ERR_OK) + return retVal; + } + else + return RT_ERR_PORT_ID; + + /* check egress and ingress version*/ + if((tmp_value & 0xffff) != 0x5fa0) + return RT_ERR_MACSEC_EGRESS_DEVICE; + + if((retVal = dal_rtl8373_macsec_ingress_get(port, RTL8373_MACSEC_EIP160_VERSION, &tmp_value)) != RT_ERR_OK) + return retVal; + + if((tmp_value & 0xffff) != 0x5fa0) + return RT_ERR_MACSEC_INGRESS_DEVICE; + + /* initial egress and ingress transform records*/ + for(index = 0; index < 16; index++) + { + if((retVal = dal_rtl8373_macsec_egress_set(port, RTL8373_MACSEC_TR_CTRL_E_64(index), 0)) != RT_ERR_OK) + return retVal; + + if((retVal = dal_rtl8373_macsec_egress_set(port, RTL8373_MACSEC_TR_ID_E_64(index), 0)) != RT_ERR_OK) + return retVal; + + if((retVal = dal_rtl8373_macsec_egress_set(port, RTL8373_MACSEC_TR_Key0_E_64(index), 0)) != RT_ERR_OK) + return retVal; + + if((retVal = dal_rtl8373_macsec_egress_set(port, RTL8373_MACSEC_TR_Key1_E_64(index), 0)) != RT_ERR_OK) + return retVal; + + if((retVal = dal_rtl8373_macsec_egress_set(port, RTL8373_MACSEC_TR_Key2_E_64(index), 0)) != RT_ERR_OK) + return retVal; + + if((retVal = dal_rtl8373_macsec_egress_set(port, RTL8373_MACSEC_TR_Key3_E_64(index), 0)) != RT_ERR_OK) + return retVal; + + if((retVal = dal_rtl8373_macsec_egress_set(port, RTL8373_MACSEC_TR_Hkey0_Key4_E_64(index), 0)) != RT_ERR_OK) + return retVal; + + if((retVal = dal_rtl8373_macsec_egress_set(port, RTL8373_MACSEC_TR_Hkey1_Key5_E_64(index), 0)) != RT_ERR_OK) + return retVal; + + if((retVal = dal_rtl8373_macsec_egress_set(port, RTL8373_MACSEC_TR_Hkey2_Key6_E_64(index), 0)) != RT_ERR_OK) + return retVal; + + if((retVal = dal_rtl8373_macsec_egress_set(port, RTL8373_MACSEC_TR_Hkey3_Key7_E_64(index), 0)) != RT_ERR_OK) + return retVal; + + if((retVal = dal_rtl8373_macsec_egress_set(port, RTL8373_MACSEC_TR_Seq0_Hkey0_E_64(index), 0)) != RT_ERR_OK) + return retVal; + + if((retVal = dal_rtl8373_macsec_egress_set(port, RTL8373_MACSEC_TR_Seq1_Hkey1_E_64(index), 0)) != RT_ERR_OK) + return retVal; + + if((retVal = dal_rtl8373_macsec_egress_set(port, RTL8373_MACSEC_TR_Zero_Hkey2_E_64(index), 0)) != RT_ERR_OK) + return retVal; + + if((retVal = dal_rtl8373_macsec_egress_set(port, RTL8373_MACSEC_TR_IS0_Hkey3_E_64(index), 0)) != RT_ERR_OK) + return retVal; + + if((retVal = dal_rtl8373_macsec_egress_set(port, RTL8373_MACSEC_TR_IS1_Seq0_E_64(index), 0)) != RT_ERR_OK) + return retVal; + + if((retVal = dal_rtl8373_macsec_egress_set(port, RTL8373_MACSEC_TR_IS2_Seq1_E_64(index), 0)) != RT_ERR_OK) + return retVal; + + if((retVal = dal_rtl8373_macsec_egress_set(port, RTL8373_MACSEC_TR_IV0_Zero_E_64(index), 0)) != RT_ERR_OK) + return retVal; + + if((retVal = dal_rtl8373_macsec_egress_set(port, RTL8373_MACSEC_TR_IV1_IS0_E_64(index), 0)) != RT_ERR_OK) + return retVal; + + if((retVal = dal_rtl8373_macsec_egress_set(port, RTL8373_MACSEC_TR_Zero_IS1_E_64(index), 0)) != RT_ERR_OK) + return retVal; + + if((retVal = dal_rtl8373_macsec_egress_set(port, RTL8373_MACSEC_TR_SAupd_IS2_E_64(index), 0)) != RT_ERR_OK) + return retVal; + + if((retVal = dal_rtl8373_macsec_egress_set(port, RTL8373_MACSEC_TR_Zero_IV0_E_64(index), 0)) != RT_ERR_OK) + return retVal; + + if((retVal = dal_rtl8373_macsec_egress_set(port, RTL8373_MACSEC_TR_Zero_IV1_E_64(index), 0)) != RT_ERR_OK) + return retVal; + + if((retVal = dal_rtl8373_macsec_egress_set(port, RTL8373_MACSEC_TR_Zero_SAupd_E_64(index), 0)) != RT_ERR_OK) + return retVal; + + if((retVal = dal_rtl8373_macsec_ingress_set(port, RTL8373_MACSEC_TR_CTRL_I_64(index), 0)) != RT_ERR_OK) + return retVal; + + if((retVal = dal_rtl8373_macsec_ingress_set(port, RTL8373_MACSEC_TR_ID_I_64(index), 0)) != RT_ERR_OK) + return retVal; + + if((retVal = dal_rtl8373_macsec_ingress_set(port, RTL8373_MACSEC_TR_Key0_I_64(index), 0)) != RT_ERR_OK) + return retVal; + + if((retVal = dal_rtl8373_macsec_ingress_set(port, RTL8373_MACSEC_TR_Key1_I_64(index), 0)) != RT_ERR_OK) + return retVal; + + if((retVal = dal_rtl8373_macsec_ingress_set(port, RTL8373_MACSEC_TR_Key2_I_64(index), 0)) != RT_ERR_OK) + return retVal; + + if((retVal = dal_rtl8373_macsec_ingress_set(port, RTL8373_MACSEC_TR_Key3_I_64(index), 0)) != RT_ERR_OK) + return retVal; + + if((retVal = dal_rtl8373_macsec_ingress_set(port, RTL8373_MACSEC_TR_Hkey0_Key4_I_64(index), 0)) != RT_ERR_OK) + return retVal; + + if((retVal = dal_rtl8373_macsec_ingress_set(port, RTL8373_MACSEC_TR_Hkey1_Key5_I_64(index), 0)) != RT_ERR_OK) + return retVal; + + if((retVal = dal_rtl8373_macsec_ingress_set(port, RTL8373_MACSEC_TR_Hkey2_Key6_I_64(index), 0)) != RT_ERR_OK) + return retVal; + + if((retVal = dal_rtl8373_macsec_ingress_set(port, RTL8373_MACSEC_TR_Hkey3_Key7_I_64(index), 0)) != RT_ERR_OK) + return retVal; + + if((retVal = dal_rtl8373_macsec_ingress_set(port, RTL8373_MACSEC_TR_Seq0_Hkey0_I_64(index), 0)) != RT_ERR_OK) + return retVal; + + if((retVal = dal_rtl8373_macsec_ingress_set(port, RTL8373_MACSEC_TR_Seq1_Hkey1_I_64(index), 0)) != RT_ERR_OK) + return retVal; + + if((retVal = dal_rtl8373_macsec_ingress_set(port, RTL8373_MACSEC_TR_Mask_Hkey2_I_64(index), 0)) != RT_ERR_OK) + return retVal; + + if((retVal = dal_rtl8373_macsec_ingress_set(port, RTL8373_MACSEC_TR_IV0_Hkey3_I_64(index), 0)) != RT_ERR_OK) + return retVal; + + if((retVal = dal_rtl8373_macsec_ingress_set(port, RTL8373_MACSEC_TR_IV1_Seq0_I_64(index), 0)) != RT_ERR_OK) + return retVal; + + if((retVal = dal_rtl8373_macsec_ingress_set(port, RTL8373_MACSEC_TR_IV2_Seq1_I_64(index), 0)) != RT_ERR_OK) + return retVal; + + if((retVal = dal_rtl8373_macsec_ingress_set(port, RTL8373_MACSEC_TR_Zero_Mask_I_64(index), 0)) != RT_ERR_OK) + return retVal; + + if((retVal = dal_rtl8373_macsec_ingress_set(port, RTL8373_MACSEC_TR_Zero_IV0_I_64(index), 0)) != RT_ERR_OK) + return retVal; + + if((retVal = dal_rtl8373_macsec_ingress_set(port, RTL8373_MACSEC_TR_Zero_IV1_I_64(index), 0)) != RT_ERR_OK) + return retVal; + + if((retVal = dal_rtl8373_macsec_ingress_set(port, RTL8373_MACSEC_TR_Zero_IV2_I_64(index), 0)) != RT_ERR_OK) + return retVal; + + //initial SA match rule and flow index + if((retVal = dal_rtl8373_macsec_ingress_set(port, RTL8373_MACSEC_SAM_SA_LO(index), 0)) != RT_ERR_OK) + return retVal; + + if((retVal = dal_rtl8373_macsec_ingress_set(port, RTL8373_MACSEC_SAM_SA_HI(index), 0)) != RT_ERR_OK) + return retVal; + + if((retVal = dal_rtl8373_macsec_ingress_set(port, RTL8373_MACSEC_SAM_DA_LO(index), 0)) != RT_ERR_OK) + return retVal; + + if((retVal = dal_rtl8373_macsec_ingress_set(port, RTL8373_MACSEC_SAM_DA_HI(index), 0)) != RT_ERR_OK) + return retVal; + + if((retVal = dal_rtl8373_macsec_ingress_set(port, RTL8373_MACSEC_SAM_MISC(index), 0)) != RT_ERR_OK) + return retVal; + + if((retVal = dal_rtl8373_macsec_ingress_set(port, RTL8373_MACSEC_SAM_SCI_LO(index), 0)) != RT_ERR_OK) + return retVal; + + if((retVal = dal_rtl8373_macsec_ingress_set(port, RTL8373_MACSEC_SAM_SCI_HI(index), 0)) != RT_ERR_OK) + return retVal; + + if((retVal = dal_rtl8373_macsec_ingress_set(port, RTL8373_MACSEC_SAM_MASK(index), 0)) != RT_ERR_OK) + return retVal; + + if((retVal = dal_rtl8373_macsec_ingress_set(port, RTL8373_MACSEC_SAM_EXT(index), 0)) != RT_ERR_OK) + return retVal; + + if((retVal = dal_rtl8373_macsec_ingress_set(port, RTL8373_MACSEC_SAM_FLOW_CTRL(index), 0)) != RT_ERR_OK) + return retVal; + } + + /* configure egress and ingress context size*/ + if((retVal = dal_rtl8373_macsec_egress_set(port, RTL8373_MACSEC_EIP62_CONTEXT_CTRL, 0xe5880218)) != RT_ERR_OK) + return retVal; + + if((retVal = dal_rtl8373_macsec_ingress_set(port, RTL8373_MACSEC_EIP62_CONTEXT_CTRL, 0xe5880214)) != RT_ERR_OK) + return retVal; + + /* configure context update control*/ + if((retVal = dal_rtl8373_macsec_egress_set(port, RTL8373_MACSEC_EIP62_CONTEXT_UPD_CTRL, 0x0003)) != RT_ERR_OK) + return retVal; + + if((retVal = dal_rtl8373_macsec_ingress_set(port, RTL8373_MACSEC_EIP62_CONTEXT_UPD_CTRL, 0x0003)) != RT_ERR_OK) + return retVal; + + /* configure MACsec fix latency and xform size*/ + if((retVal = dal_rtl8373_macsec_egress_set(port, RTL8373_MACSEC_MISC_CONTROL, 0x02000030)) != RT_ERR_OK) + return retVal; + + if((retVal = dal_rtl8373_macsec_ingress_set(port, RTL8373_MACSEC_MISC_CONTROL, 0x01000833)) != RT_ERR_OK) + return retVal; + } + + } + + return RT_ERR_OK; + +} + + diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_macsec.h b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_macsec.h new file mode 100755 index 00000000..d2b4bd55 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_macsec.h @@ -0,0 +1,706 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8371c switch high-level API + * + * Feature : The file includes QoS module high-layer API defination + * + */ + +#ifndef __DAL_RTL8373_MACSEC_H__ +#define __DAL_RTL8373_MACSEC_H__ + +#include "macsec.h" + +/* Function Name: + * dal_rtl8373_macsec_enable_set + * Description: + * Configure macsec enable. + * Input: + * port - port id + * ingress_en - ingress enable + * egress_en - egress enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure macsec enable. + */ +extern rtk_api_ret_t dal_rtl8373_macsec_enable_set(rtk_uint32 port, rtk_uint32 ingress_en, rtk_uint32 egress_en); + +/* Function Name: + * dal_rtl8373_macsec_enable_get + * Description: + * get macsec enable status. + * Input: + * port - port id + * Output: + * ingress_en - ingress enable + * egress_en - egress enable + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will get macsec enable status. + */ +extern rtk_api_ret_t dal_rtl8373_macsec_enable_get(rtk_uint32 port, rtk_uint32 *ingress_en, rtk_uint32 *egress_en); + +/* Function Name: + * dal_rtl8373_macsec_reset + * Description: + * reset macsec ip. + * Input: + * port - port id + * ingress_rst - ingress reset + * egress_rst - egress reset + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will reset macsec. + */ +extern rtk_api_ret_t dal_rtl8373_macsec_reset(rtk_uint32 port, rtk_uint32 ingress_rst, rtk_uint32 egress_rst); + +/* Function Name: + * dal_rtl8373_macsec_egress_set + * Description: + * Configure macsec egress rule. + * Input: + * port - port id + * addr - macsec ip core register address + * value - data for rule + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure macsec egress rule:SA match rule, flow control register and transform record. + */ +extern rtk_api_ret_t dal_rtl8373_macsec_egress_set(rtk_uint32 port, rtk_uint32 addr, rtk_uint32 value); + +/* Function Name: + * dal_rtl8373_macsec_egress_get + * Description: + * get macsec egress rule. + * Input: + * port - port id + * addr - macsec ip core register address + * Output: + * value - data for rule + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will get macsec egress rule:SA match rule, flow control register and transform record. + */ +extern rtk_api_ret_t dal_rtl8373_macsec_egress_get(rtk_uint32 port, rtk_uint32 addr, rtk_uint32 *value); + +/* Function Name: + * dal_rtl8373_macsec_ingress_set + * Description: + * Configure macsec ingress rule. + * Input: + * port - port id + * addr - macsec ip core register address + * value - data for rule + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure macsec ingress rule:SA match rule, flow control register and transform record. + */ +extern rtk_api_ret_t dal_rtl8373_macsec_ingress_set(rtk_uint32 port, rtk_uint32 addr, rtk_uint32 value); + +/* Function Name: + * dal_rtl8373_macsec_ingress_get + * Description: + * get macsec egress rule. + * Input: + * port - port id + * addr - macsec ip core register address + * Output: + * value - data for rule + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will get macsec ingress rule:SA match rule, flow control register and transform record. + */ +extern rtk_api_ret_t dal_rtl8373_macsec_ingress_get(rtk_uint32 port, rtk_uint32 addr, rtk_uint32 *value); + +/* Function Name: + * dal_rtl8373_macsec_rxgating_set + * Description: + * Configure macsec rx gating value + * Input: + * port - port id + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure macsec rx gating value,before set the packet flow path called this API. + */ +extern rtk_api_ret_t dal_rtl8373_macsec_rxgating_set(rtk_uint32 port); + +/* Function Name: + * dal_rtl8373_macsec_rxgating_cancel + * Description: + * Configure macsec rx gating value + * Input: + * port - port id + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure macsec rx gating value, called after packet flow path changed. + */ +extern rtk_api_ret_t dal_rtl8373_macsec_rxgating_cancel(rtk_uint32 port); + +/* Function Name: + * dal_rtl8373_macsec_txgating_set + * Description: + * Configure macsec tx gating value + * Input: + * port - port id + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure macsec tx gating value, before set the packet flow path called this API. + */ +extern rtk_api_ret_t dal_rtl8373_macsec_txgating_set(rtk_uint32 port); + +/* Function Name: + * dal_rtl8373_macsec_txgating_cancel + * Description: + * Configure macsec tx gating value + * Input: + * port - port id + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure macsec tx gating value, called after packet flow path changed.. + */ +extern rtk_api_ret_t dal_rtl8373_macsec_txgating_cancel(rtk_uint32 port); + +/* Function Name: + * dal_rtl8373_macsec_rxIPbypass_set + * Description: + * Configure macsec bypass MACsec IP function. + * Input: + * port - port id + * enable - enable ip bypass + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure macsec bypass MACsec IP function. + */ +extern rtk_api_ret_t dal_rtl8373_macsec_rxIPbypass_set(rtk_uint32 port, rtk_uint32 enable); + +/* Function Name: + * dal_rtl8373_macsec_rxIPbypass_get + * Description: + * get macsec bypass MACsec IP function status. + * Input: + * port - port id + * Output: + * enable - enable ip bypass + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will get macsec bypass MACsec IP function status. + */ +extern rtk_api_ret_t dal_rtl8373_macsec_rxIPbypass_get(rtk_uint32 port, rtk_uint32 *enable); + +/* Function Name: + * dal_rtl8373_macsec_txIPbypass_set + * Description: + * Configure macsec bypass MACsec IP function. + * Input: + * port - port id + * enable - enable ip bypass + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure macsec bypass MACsec IP function. + */ +extern rtk_api_ret_t dal_rtl8373_macsec_txIPbypass_set(rtk_uint32 port, rtk_uint32 enable); + +/* Function Name: + * dal_rtl8373_macsec_txIPbypass_get + * Description: + * get macsec bypass MACsec IP function status. + * Input: + * port - port id + * Output: + * enable - enable ip bypass + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will get macsec bypass MACsec IP function status. + */ +extern rtk_api_ret_t dal_rtl8373_macsec_txIPbypass_get(rtk_uint32 port, rtk_uint32 *enable); + +/* Function Name: + * dal_rtl8373_macsec_rxIPbypass_set + * Description: + * Configure macsec bypass in MACsec IP function. + * Input: + * port - port id + * enable - enable ip bypass + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure macsec bypass in MACsec IP function. + */ +extern rtk_api_ret_t dal_rtl8373_macsec_rxbypass_set(rtk_uint32 port, rtk_uint32 enable); + +/* Function Name: + * dal_rtl8373_macsec_rxbypass_get + * Description: + * get macsec bypass in MACsec IP function status. + * Input: + * port - port id + * Output: + * enable - enable ip bypass + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will get macsec bypass in MACsec IP function status. + */ +extern rtk_api_ret_t dal_rtl8373_macsec_rxbypass_get(rtk_uint32 port, rtk_uint32 *enable); + +/* Function Name: + * dal_rtl8373_macsec_txbypass_set + * Description: + * Configure macsec bypass in MACsec IP function. + * Input: + * port - port id + * enable - enable ip bypass + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure macsec bypass in MACsec IP function. + */ +extern rtk_api_ret_t dal_rtl8373_macsec_txbypass_set(rtk_uint32 port, rtk_uint32 enable); + +/* Function Name: + * dal_rtl8373_macsec_txbypass_get + * Description: + * get macsec bypass in MACsec IP function status. + * Input: + * port - port id + * Output: + * enable - enable ip bypass + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will get macsec bypass in MACsec IP function status. + */ +extern rtk_api_ret_t dal_rtl8373_macsec_txbypass_get(rtk_uint32 port, rtk_uint32 *enable); + +/* Function Name: + * dal_rtl8373_wrapper_int_control_set + * Description: + * Configure MACsec interrupt. + * Input: + * port - port id + * type - interrupt type + * enable - enable interrupt + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure MACsec interrupt. + * The interrupt trigger status is shown in the following: + * - INT_TYPE_TX_IPE_GLB + * - INT_TYPE_TX_IPESECFAIL + * - INT_TYPE_TX_IPELOCK + * - INT_TYPE_TX_IPELOCK_XG + * - INT_TYPE_RX_IPI_GLB + * - INT_TYPE_RX_IPISECFAIL + * - INT_TYPE_RX_IPILOCK + * - INT_TYPE_RX_IPILOCK_XG + */ +extern rtk_api_ret_t dal_rtl8373_wrapper_int_control_set(rtk_uint32 port, rtk_macsec_int_type_t type, rtk_enable_t enable); + +/* Function Name: + * dal_rtl8373_wrapper_int_control_get + * Description: + * gonfigure MACsec interrupt. + * Input: + * port - port id + * type - interrupt type + * Output: + * pEnable - enable interrupt + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will get MACsec interrupt. + * The interrupt trigger status is shown in the following: + * - INT_TYPE_TX_IPE_GLB + * - INT_TYPE_TX_IPESECFAIL + * - INT_TYPE_TX_IPELOCK + * - INT_TYPE_TX_IPELOCK_XG + * - INT_TYPE_RX_IPI_GLB + * - INT_TYPE_RX_IPISECFAIL + * - INT_TYPE_RX_IPILOCK + * - INT_TYPE_RX_IPILOCK_XG + */ +extern rtk_api_ret_t dal_rtl8373_wrapper_int_control_get(rtk_uint32 port, rtk_macsec_int_type_t type, rtk_enable_t *pEnable); + +/* Function Name: + * dal_rtl8373_wrapper_int_status_set + * Description: + * Configure MACsec interrupt status. + * Input: + * port - port id + * statusMask - interrupt status mask + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will clean MACsec interrupt status when interrupt happened. + * The interrupt trigger status is shown in the following: + * - INT_TYPE_TX_IPE_GLB [bit[0]] + * - INT_TYPE_TX_IPESECFAIL [bit[1]] + * - INT_TYPE_TX_IPELOCK [bit[2]] + * - INT_TYPE_TX_IPELOCK_XG [bit[3]] + * - INT_TYPE_RX_IPI_GLB [bit[8]] + * - INT_TYPE_RX_IPISECFAIL [bit[9]] + * - INT_TYPE_RX_IPILOCK [bit[10]] + * - INT_TYPE_RX_IPILOCK_XG [bit[11]] + */ +extern rtk_api_ret_t dal_rtl8373_wrapper_int_status_set(rtk_uint32 port, rtk_uint32 statusMask); + +/* Function Name: + * dal_rtl8373_wrapper_int_status_get + * Description: + * Configure MACsec interrupt status. + * Input: + * port - port id + + * Output: + * pStatusMask - interrupt status mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will clean MACsec interrupt status when interrupt happened. + * The interrupt trigger status is shown in the following: + * - INT_TYPE_TX_IPE_GLB [bit[0]] + * - INT_TYPE_TX_IPESECFAIL [bit[1]] + * - INT_TYPE_TX_IPELOCK [bit[2]] + * - INT_TYPE_TX_IPELOCK_XG [bit[3]] + * - INT_TYPE_RX_IPI_GLB [bit[8]] + * - INT_TYPE_RX_IPISECFAIL [bit[9]] + * - INT_TYPE_RX_IPILOCK [bit[10]] + * - INT_TYPE_RX_IPILOCK_XG [bit[11]] + */ +extern rtk_api_ret_t dal_rtl8373_wrapper_int_status_get(rtk_uint32 port, rtk_uint32 *pStatusMask); + +/* Function Name: + * dal_rtl8373_wrapper_mib_reset + * Description: + * Configure wrapper mib reset. + * Input: + * port - port id + * reset - reset value + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure wrapper mib reset. + */ +extern rtk_api_ret_t dal_rtl8373_wrapper_mib_reset(rtk_uint32 port, rtk_uint32 reset); + +/* Function Name: + * dal_rtl8373_wrapper_mib_counter + * Description: + * get wrapper mib counters. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will get wrapper mib counters. + */ +extern rtk_api_ret_t dal_rtl8373_wrapper_mib_counter(rtk_uint32 port, RTL8373_WRAPPER_MIBCOUNTER mibIdx, rtk_uint64* pCounter); + +/* Function Name: + * dal_rtl8373_macsec_ipg_len_set + * Description: + * mac mode MACsec ipg length set. + * Input: + * port - port number + * length - ipg length + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will set mac mode MACsec ipg length. + */ +extern rtk_api_ret_t dal_rtl8373_macsec_ipg_len_set(rtk_uint32 port, rtk_uint32 length); + +/* Function Name: + * dal_rtl8373_macsec_ipg_len_get + * Description: + * mac mode MACsec ipg length get. + * Input: + * port - port number + * Output: + * plength - ipg length + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will get mac mode MACsec ipg length. + */ +extern rtk_api_ret_t dal_rtl8373_macsec_ipg_len_get(rtk_uint32 port, rtk_uint32 *plength); + +/* Function Name: + * dal_rtl8373_macsec_ipg_mode_set + * Description: + * mac mode MACsec ipg mode set. + * Input: + * port - port number + * mode - ipg config mode + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will set mac mode MACsec ipg mode. + * mode[1:0]: + 0: don't insert ipg for macsec + 1: insert ipg for macsec according to macsec feedback signal + 2: insert ipg for masec according to ethertype & cfg_macsec_ipg_length + 3: always insert ipg for macsec, length according to cfg_macsec_ipg_length + */ +extern rtk_api_ret_t dal_rtl8373_macsec_ipg_mode_set(rtk_uint32 port, rtk_uint32 mode); + +/* Function Name: + * dal_rtl8373_macsec_ipg_mode_get + * Description: + * mac mode MACsec ipg mode get. + * Input: + * port - port number + * Output: + * pmode - ipg config mode + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will get mac mode MACsec ipg mode. + * mode[1:0]: + 0: don't insert ipg for macsec + 1: insert ipg for macsec according to macsec feedback signal + 2: insert ipg for masec according to ethertype & cfg_macsec_ipg_length + 3: always insert ipg for macsec, length according to cfg_macsec_ipg_length + */ +extern rtk_api_ret_t dal_rtl8373_macsec_ipg_mode_get(rtk_uint32 port, rtk_uint32 *pmode); + +/* Function Name: + * dal_rtl8373_macsec_eth_set + * Description: + * mac mode MACsec eth set. + * Input: + * port - port number + * entry - entry number(0-7) + * ethertype - ether type value + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will set mac mode MACsec eth. + */ +extern rtk_api_ret_t dal_rtl8373_macsec_eth_set(rtk_uint32 port, rtk_uint32 entry, rtk_uint32 ethertype); + +/* Function Name: + * dal_rtl8373_macsec_eth_get + * Description: + * mac mode MACsec eth get. + * Input: + * port - port number + * entry - entry number(0-7) + * Output: + * pethertype - ether type value + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will get mac mode MACsec eth. + */ +extern rtk_api_ret_t dal_rtl8373_macsec_eth_get(rtk_uint32 port, rtk_uint32 entry, rtk_uint32 *pethertype); + +/* Function Name: + * dal_rtl8373_macsec_init + * Description: + * Initialize MACsec information. + * Input: + * port_mask - port mask, bit[4:7] + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will initialize MACsec information. + */ +extern rtk_api_ret_t dal_rtl8373_macsec_init(rtk_uint32 port_mask); + + +#endif + + diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_macsec_ip_reg.h b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_macsec_ip_reg.h new file mode 100755 index 00000000..f29fa002 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_macsec_ip_reg.h @@ -0,0 +1,235 @@ +/* + * ## Please DO NOT edit this file!! ## + * This file is auto-generated from the register source files. + * Any modifications to this file will be LOST when it is re-generated. + * + * ---------------------------------------------------------------- + * (C) Copyright 2009-2016 Realtek Semiconductor Corp. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * ---------------------------------------------------------------- + * Purpose: chip register definition and structure of RTL8373 + * + * ---------------------------------------------------------------- + */ + +#ifndef __RTL8373_MACSEC_REG_DEFINITION_H__ +#define __RTL8373_MACSEC_REG_DEFINITION_H__ + +/* follow variable index value from 0 to 15*/ +/* 128bit & 256 bit egress register (32 bit packet number)*/ +#define RTL8373_MACSEC_TR_CTRL_E(index) (0x0 + index * 0x60) +#define RTL8373_MACSEC_TR_ID_E(index) (0x4 + index * 0x60) +#define RTL8373_MACSEC_TR_Key0_E(index) (0x8 + index * 0x60) +#define RTL8373_MACSEC_TR_Key1_E(index) (0xc + index * 0x60) +#define RTL8373_MACSEC_TR_Key2_E(index) (0x10 + index * 0x60) +#define RTL8373_MACSEC_TR_Key3_E(index) (0x14 + index * 0x60) +#define RTL8373_MACSEC_TR_Hkey0_Key4_E(index) (0x18 + index * 0x60) +#define RTL8373_MACSEC_TR_Hkey1_Key5_E(index) (0x1c + index * 0x60) +#define RTL8373_MACSEC_TR_Hkey2_Key6_E(index) (0x20 + index * 0x60) +#define RTL8373_MACSEC_TR_Hkey3_Key7_E(index) (0x24 + index * 0x60) +#define RTL8373_MACSEC_TR_Seq_Hkey0_E(index) (0x28 + index * 0x60) +#define RTL8373_MACSEC_TR_IV0_Hkey1_E(index) (0x2c + index * 0x60) +#define RTL8373_MACSEC_TR_IV1_Hkey2_E(index) (0x30 + index * 0x60) +#define RTL8373_MACSEC_TR_Zero_Hkey3_E(index) (0x34 + index * 0x60) +#define RTL8373_MACSEC_TR_Zero_Seq_E(index) (0x38 + index * 0x60) +#define RTL8373_MACSEC_TR_SAupd_IV0_E(index) (0x3c + index * 0x60) +#define RTL8373_MACSEC_TR_Zero_IV1_E(index) (0x40 + index * 0x60) +#define RTL8373_MACSEC_TR_Zero_SAupd_E(index) (0x4c + index * 0x60) + +/* 128bit & 256 bit ingress(explict or implict) register (32 bit packet number)*/ +#define RTL8373_MACSEC_TR_CTRL_I(index) (0x0 + index * 0x50) +#define RTL8373_MACSEC_TR_ID_I(index) (0x4 + index * 0x50) +#define RTL8373_MACSEC_TR_Key0_I(index) (0x8 + index * 0x50) +#define RTL8373_MACSEC_TR_Key1_I(index) (0xc + index * 0x50) +#define RTL8373_MACSEC_TR_Key2_I(index) (0x10 + index * 0x50) +#define RTL8373_MACSEC_TR_Key3_I(index) (0x14 + index * 0x50) +#define RTL8373_MACSEC_TR_Hkey0_Key4_I(index) (0x18 + index * 0x50) +#define RTL8373_MACSEC_TR_Hkey1_Key5_I(index) (0x1c + index * 0x50) +#define RTL8373_MACSEC_TR_Hkey2_Key6_I(index) (0x20 + index * 0x50) +#define RTL8373_MACSEC_TR_Hkey3_Key7_I(index) (0x24 + index * 0x50) +#define RTL8373_MACSEC_TR_Seq_Hkey0_I(index) (0x28 + index * 0x50) +#define RTL8373_MACSEC_TR_Mask_Hkey1_I(index) (0x2c + index * 0x50) +#define RTL8373_MACSEC_TR_Zero_IV0_Hkey2_I(index) (0x30 + index * 0x50) +#define RTL8373_MACSEC_TR_Zero_IV1_Hkey3_I(index) (0x34 + index * 0x50) +#define RTL8373_MACSEC_TR_Zero_Seq_I(index) (0x38 + index * 0x50) +#define RTL8373_MACSEC_TR_Zero_Mask_I(index) (0x3c + index * 0x50) +#define RTL8373_MACSEC_TR_Zero_Zero_IV0_I(index) (0x40 + index * 0x50) +#define RTL8373_MACSEC_TR_Zero_Zero_IV1_I(index) (0x44 + index * 0x50) + +/* 128bit & 256 bit egress register (64 bit packet number)*/ +#define RTL8373_MACSEC_TR_CTRL_E_64(index) (0x0 + index * 0x60) +#define RTL8373_MACSEC_TR_ID_E_64(index) (0x4 + index * 0x60) +#define RTL8373_MACSEC_TR_Key0_E_64(index) (0x8 + index * 0x60) +#define RTL8373_MACSEC_TR_Key1_E_64(index) (0xc + index * 0x60) +#define RTL8373_MACSEC_TR_Key2_E_64(index) (0x10 + index * 0x60) +#define RTL8373_MACSEC_TR_Key3_E_64(index) (0x14 + index * 0x60) +#define RTL8373_MACSEC_TR_Hkey0_Key4_E_64(index) (0x18 + index * 0x60) +#define RTL8373_MACSEC_TR_Hkey1_Key5_E_64(index) (0x1c + index * 0x60) +#define RTL8373_MACSEC_TR_Hkey2_Key6_E_64(index) (0x20 + index * 0x60) +#define RTL8373_MACSEC_TR_Hkey3_Key7_E_64(index) (0x24 + index * 0x60) +#define RTL8373_MACSEC_TR_Seq0_Hkey0_E_64(index) (0x28 + index * 0x60) +#define RTL8373_MACSEC_TR_Seq1_Hkey1_E_64(index) (0x2c + index * 0x60) +#define RTL8373_MACSEC_TR_Zero_Hkey2_E_64(index) (0x30 + index * 0x60) +#define RTL8373_MACSEC_TR_IS0_Hkey3_E_64(index) (0x34 + index * 0x60) +#define RTL8373_MACSEC_TR_IS1_Seq0_E_64(index) (0x38 + index * 0x60) +#define RTL8373_MACSEC_TR_IS2_Seq1_E_64(index) (0x3c + index * 0x60) +#define RTL8373_MACSEC_TR_IV0_Zero_E_64(index) (0x40 + index * 0x60) +#define RTL8373_MACSEC_TR_IV1_IS0_E_64(index) (0x44 + index * 0x60) +#define RTL8373_MACSEC_TR_Zero_IS1_E_64(index) (0x48 + index * 0x60) +#define RTL8373_MACSEC_TR_SAupd_IS2_E_64(index) (0x4c + index * 0x60) +#define RTL8373_MACSEC_TR_Zero_IV0_E_64(index) (0x50 + index * 0x60) +#define RTL8373_MACSEC_TR_Zero_IV1_E_64(index) (0x54 + index * 0x60) +#define RTL8373_MACSEC_TR_Zero_SAupd_E_64(index) (0x5c + index * 0x60) + +/* 128bit & 256 bit ingress register (64 bit packet number)*/ +#define RTL8373_MACSEC_TR_CTRL_I_64(index) (0x0 + index * 0x50) +#define RTL8373_MACSEC_TR_ID_I_64(index) (0x4 + index * 0x50) +#define RTL8373_MACSEC_TR_Key0_I_64(index) (0x8 + index * 0x50) +#define RTL8373_MACSEC_TR_Key1_I_64(index) (0xc + index * 0x50) +#define RTL8373_MACSEC_TR_Key2_I_64(index) (0x10 + index * 0x50) +#define RTL8373_MACSEC_TR_Key3_I_64(index) (0x14 + index * 0x50) +#define RTL8373_MACSEC_TR_Hkey0_Key4_I_64(index) (0x18 + index * 0x50) +#define RTL8373_MACSEC_TR_Hkey1_Key5_I_64(index) (0x1c + index * 0x50) +#define RTL8373_MACSEC_TR_Hkey2_Key6_I_64(index) (0x20 + index * 0x50) +#define RTL8373_MACSEC_TR_Hkey3_Key7_I_64(index) (0x24 + index * 0x50) +#define RTL8373_MACSEC_TR_Seq0_Hkey0_I_64(index) (0x28 + index * 0x50) +#define RTL8373_MACSEC_TR_Seq1_Hkey1_I_64(index) (0x2c + index * 0x50) +#define RTL8373_MACSEC_TR_Mask_Hkey2_I_64(index) (0x30 + index * 0x50) +#define RTL8373_MACSEC_TR_IV0_Hkey3_I_64(index) (0x34 + index * 0x50) +#define RTL8373_MACSEC_TR_IV1_Seq0_I_64(index) (0x38 + index * 0x50) +#define RTL8373_MACSEC_TR_IV2_Seq1_I_64(index) (0x3c + index * 0x50) +#define RTL8373_MACSEC_TR_Zero_Mask_I_64(index) (0x40 + index * 0x50) +#define RTL8373_MACSEC_TR_Zero_IV0_I_64(index) (0x44 + index * 0x50) +#define RTL8373_MACSEC_TR_Zero_IV1_I_64(index) (0x48 + index * 0x50) +#define RTL8373_MACSEC_TR_Zero_IV2_I_64(index) (0x4c + index * 0x50) + +/* SA match rule register*/ +#define RTL8373_MACSEC_SAM_SA_LO(index) (0x4000 + index * 0x40) +#define RTL8373_MACSEC_SAM_SA_HI(index) (0x4004 + index * 0x40) +#define RTL8373_MACSEC_SAM_DA_LO(index) (0x4008 + index * 0x40) +#define RTL8373_MACSEC_SAM_DA_HI(index) (0x400c + index * 0x40) +#define RTL8373_MACSEC_SAM_MISC(index) (0x4010 + index * 0x40) +#define RTL8373_MACSEC_SAM_SCI_LO(index) (0x4014 + index * 0x40) +#define RTL8373_MACSEC_SAM_SCI_HI(index) (0x4018 + index * 0x40) +#define RTL8373_MACSEC_SAM_MASK(index) (0x401c + index * 0x40) +#define RTL8373_MACSEC_SAM_EXT(index) (0x4020 + index * 0x40) + +/*SA match entry enable control register*/ +#define RTL8373_MACSEC_SAM_ENTRY_ENABLE (0x6000) +#define RTL8373_MACSEC_SAM_ENTRY_TOGGLE (0x6040) +#define RTL8373_MACSEC_SAM_ENTRY_SET (0x6080) +#define RTL8373_MACSEC_SAM_ENTRY_CLEAR (0x60c0) +#define RTL8373_MACSEC_SAM_ENTRY_ENBALE_CTRL (0x6100) +#define RTL8373_MACSEC_SAM_IN_FLIGHT (0x6104) + +/* Flow control words register for MACsec/bypass/drop*/ +#define RTL8373_MACSEC_SAM_FLOW_CTRL(index) (0x7000 + index * 0x4) + +/* Control packet classifier register*/ +/* the variable index value from 0 to 9*/ +#define RTL8373_MACSEC_CP_MAC_DA(index) (0x7800 + index * 0x8) +#define RTL8373_MACSEC_CP_MAC_DA_ET(index) (0x7804 + index * 0x8) +#define RTL8373_MACSEC_CP_MAC_ET(index) (0x7850 + index * 0x4) +#define RTL8373_MACSEC_CP_MAC_DA_START_LO (0x7880) +#define RTL8373_MACSEC_CP_MAC_DA_START_HI (0x7884) +#define RTL8373_MACSEC_CP_MAC_DA_END_LO (0x7888) +#define RTL8373_MACSEC_CP_MAC_DA_END_HI (0x788c) +#define RTL8373_MACSEC_CP_MAC_DA_44_BITS_LO (0x7890) +#define RTL8373_MACSEC_CP_MAC_DA_44_BITS_HI (0x7894) +#define RTL8373_MACSEC_CP_MAC_DA_48_BITS_LO (0x7898) +#define RTL8373_MACSEC_CP_MAC_DA_48_BITS_HI (0x789c) +#define RTL8373_MACSEC_CP_MATCH_MODE (0x78f8) +#define RTL8373_MACSEC_CP_MATCH_ENABLE (0x78fc) + +/* Vlan parser algorithm register*/ +#define RTL8373_MACSEC_SAM_CP_TAG (0x7900) +#define RTL8373_MACSEC_SAM_PP_TAGS (0x7904) +#define RTL8373_MACSEC_SAM_PP_TAGS2 (0x7908) +#define RTL8373_MACSEC_SAM_CP_TAG2 (0x790c) + +/* No-match classifier control*/ +#define RTL8373_MACSEC_NM_PARAMS (0x7940) + +/* Non-match flows register*/ +#define RTL8373_MACSEC_NM_FLOW_NCP (0x7944) +#define RTL8373_MACSEC_NM_FLOW_CP (0x7948) + +/* Explicit non-match flow*/ +#define RTL8373_MACSEC_NM_FLOW_EXPL (0x794c) + +/* Miscellaneous control*/ +#define RTL8373_MACSEC_MISC_CONTROL (0x797c) + +/* Crypt-authenticate mode control*/ +#define RTL8373_MACSEC_CRYPT_AUTH_CTRL (0x7984) + +/* Threshold for 32-bit packet numbert*/ +#define RTL8373_MACSEC_SEQ_NUM_THRESHOLD (0xf420) + +/* Threshold for 32-bit packet numbert*/ +#define RTL8373_MACSEC_SEQ_NUM_THRESHOLD64_LO (0xf424) +#define RTL8373_MACSEC_SEQ_NUM_THRESHOLD64_HI (0xf424) + +/* MACsec egress or ingress mode register*/ +#define RTL8373_MACSEC_EIP160_CONFIG2 (0xfff4) + +/* MACsec version register*/ +#define RTL8373_MACSEC_EIP160_VERSION (0xfffc) + +/* MACsec context update control register*/ +#define RTL8373_MACSEC_EIP62_CONTEXT_UPD_CTRL (0xf430) + +/* MACsec context control register*/ +#define RTL8373_MACSEC_EIP62_CONTEXT_CTRL (0xf408) + +/* MACsec statistics counter ingress register*/ +#define RTL8373_MACSEC_STA_INOCTETSDEP(index) (0x8000 + index * 0x80) +#define RTL8373_MACSEC_STA_INPKTSUNCHECK(index) (0x8010 + index * 0x80) +#define RTL8373_MACSEC_STA_INPKTSDELAY(index) (0x8018 + index * 0x80) +#define RTL8373_MACSEC_STA_INPKTSLATE(index) (0x8020 + index * 0x80) +#define RTL8373_MACSEC_STA_INPKTSOK(index) (0x8028 + index * 0x80) +#define RTL8373_MACSEC_STA_INPKTSINVALID(index) (0x8030 + index * 0x80) +#define RTL8373_MACSEC_STA_INPKTSNOTVALID(index) (0x8038 + index * 0x80) +#define RTL8373_MACSEC_STA_INPKTSNOTUSINGSA(index) (0x8040 + index * 0x80) +#define RTL8373_MACSEC_STA_INPKTSUNUSEDSA(index) (0x8048 + index * 0x80) +#define RTL8373_MACSEC_STA_INPKTSUNTAGHIT(index) (0x8050 + index * 0x80) + +#define RTL8373_MACSEC_STA_TRANSFORMERRORPKTS_IN (0xc400) +#define RTL8373_MACSEC_STA_INPKTSCTRL (0xc408) +#define RTL8373_MACSEC_STA_INPKTSNOTAG (0xc410) +#define RTL8373_MACSEC_STA_INPKTSUNTAG (0xc418) +#define RTL8373_MACSEC_STA_INPKTSTAG (0xc420) +#define RTL8373_MACSEC_STA_INPKTSBADTAG (0xc428) +#define RTL8373_MACSEC_STA_INPKTSUNTAGMISS (0xc430) +#define RTL8373_MACSEC_STA_INPKTSNOSCI (0xc438) +#define RTL8373_MACSEC_STA_INPKTSUNKNOWNSCI (0xc440) +#define RTL8373_MACSEC_STA_INCONSISTCHECKCTRLNOTPASS (0xc448) +#define RTL8373_MACSEC_STA_INCONSISTCHECKUNCTRLNOTPASS (0xc450) +#define RTL8373_MACSEC_STA_INCONSISTCHECKCTRLPASS (0xc458) +#define RTL8373_MACSEC_STA_INCONSISTCHECKUNCTRLPASS (0xc460) +#define RTL8373_MACSEC_STA_INOVERSIZEPKTS (0xc468) + +/* MACsec statistics counter egress register*/ +#define RTL8373_MACSEC_STA_OUTOCTETSENP(index) (0x8000 + index * 0x80) +#define RTL8373_MACSEC_STA_OUTPKTSENP(index) (0x8010 + index * 0x80) +#define RTL8373_MACSEC_STA_OUTPKTTOOLONG(index) (0x8018 + index * 0x80) + +#define RTL8373_MACSEC_STA_TRANSFORMERRORPKTS_EG (0xc400) +#define RTL8373_MACSEC_STA_OUTPKTSCTRL (0xc408) +#define RTL8373_MACSEC_STA_OUTPKTSUNKNOWNSA (0xc410) +#define RTL8373_MACSEC_STA_OUTPKTSUNTAG (0xc418) +#define RTL8373_MACSEC_STA_OUTOVERSIZEPKTS (0xc420) + + +#endif + + + + diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_mapper.c b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_mapper.c new file mode 100755 index 00000000..b70a7185 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_mapper.c @@ -0,0 +1,758 @@ + +/* + * Copyright (C) 2012 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + */ + +/* + * Include Files + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#if 0 +#include +#include +#include +#include +#include +#include +#endif +/* + * Symbol Definition + */ + +/* + * Data Declaration + */ +static dal_mapper_t dal_rtl8373_mapper = +{ + /* Switch */ + .switch_init = dal_rtl8373_switch_init, + //.switch_portMaxPktLen_set = dal_rtl8373_portMaxLen_set, + //.switch_portMaxPktLen_get = dal_rtl8373_portMaxLen_get, + //.switch_maxPktLenCfg_set = dal_rtl8373_switch_maxPktLenCfg_set, + //.switch_maxPktLenCfg_get = dal_rtl8373_switch_maxPktLenCfg_get, + .switch_greenEthernet_set = NULL, //dal_rtl8373_switch_greenEthernet_set, + .switch_greenEthernet_get = NULL, //dal_rtl8373_switch_greenEthernet_get, + + .fMdrv_miim_mmd_read = dal_rtl8373_phy_read, + .fMdrv_miim_mmd_write = dal_rtl8373_phy_write, + .fMdrv_miim_mmd_readbits = dal_rtl8373_phy_readBits, + .fMdrv_miim_mmd_writebits = dal_rtl8373_phy_writeBits, + /* cpu */ + .cpuTag_externalCpuPort_set = dal_rtl8373_cpuTag_externalCpuPort_set, + .cpuTag_externalCpuPort_get = dal_rtl8373_cpuTag_externalCpuPort_get, + .cpuTag_tpid_set = dal_rtl8373_cpuTag_tpid_set, + .cpuTag_tpid_get = dal_rtl8373_cpuTag_tpid_get, + .cpuTag_enable_set = dal_rtl8373_cpuTag_enable_set, + .cpuTag_enable_get = dal_rtl8373_cpuTag_enable_get, + .cpuTag_insertMode_set = dal_rtl8373_cpuTag_insertMode_set, + .cpuTag_insertMode_get = dal_rtl8373_cpuTag_insertMode_get, + .cpuTag_awarePort_set = dal_rtl8373_cpuTag_awarePort_set, + .cpuTag_awarePort_get = dal_rtl8373_cpuTag_awarePort_get, + .cpuTag_priRemap_set = dal_rtl8373_cpuTag_priRemap_set, + .cpuTag_priRemap_get = dal_rtl8373_cpuTag_priRemap_get, + + /* acl */ + .filter_igrAcl_init = dal_rtl8373_igrAcl_init, + .filter_igrAcl_field_add = dal_rtl8373_igrAcl_field_add, + .filter_igrAcl_cfg_add = dal_rtl8373_igrAcl_cfg_add, + .filter_igrAcl_cfg_del = dal_rtl8373_igrAcl_cfg_del, + .filter_igrAcl_cfg_delAll = dal_rtl8373_igrAcl_cfg_delAll, + .filter_igrAcl_cfg_get = dal_rtl8373_igrAcl_cfg_get, + .filter_igrAcl_unmatchAction_set = dal_rtl8373_igrAcl_unmatchAction_set, + .filter_igrAcl_unmatchAction_get = dal_rtl8373_igrAcl_unmatchAction_get, + .filter_igrAcl_state_set = dal_rtl8373_igrAcl_state_set, + .filter_igrAcl_state_get = dal_rtl8373_igrAcl_state_get, + .filter_igrAcl_template_set = dal_rtl8373_igrAcl_template_set, + .filter_igrAcl_template_get = dal_rtl8373_igrAcl_template_get, + .filter_igrAcl_field_sel_set = dal_rtl8373_igrAcl_fieldSel_set, + .filter_igrAcl_field_sel_get = dal_rtl8373_igrAcl_fieldSel_get, + .filter_iprange_set = dal_rtl8373_igrAcl_ipRange_set, + .filter_iprange_get = dal_rtl8373_igrAcl_ipRange_get, + .filter_vidrange_set = dal_rtl8373_igrAcl_vidRange_set, + .filter_vidrange_get = dal_rtl8373_igrAcl_vidRange_get, + .filter_portrange_set = dal_rtl8373_igrAcl_portRange_set, + .filter_portrange_get = dal_rtl8373_igrAcl_portRange_get, + .filter_igrAcl_gpioPolarity_set = dal_rtl8373_igrAcl_gpioPolarity_set, + .filter_igrAcl_gpioPolarity_get = dal_rtl8373_igrAcl_gpioPolarity_get, + .filter_igrAcl_gpioEn_set = dal_rtl8373_igrAcl_gpioEn_set, + .filter_igrAcl_gpioEn_get = dal_rtl8373_igrAcl_gpioEn_get, + .filter_igrAcl_tbl_rst = dal_rtl8373_igrAcl_table_rst, + + /* mirror */ + .mirror_set_en = dal_rtl8373_mirror_set_en, + .mirror_setStatus_get = dal_rtl8373_mirror_setStatus_get, + .mirror_entry_set = dal_rtl8373_mirror_entry_set, + .mirror_entry_get = dal_rtl8373_mirror_entry_get, + .mirror_portIso_set = dal_rtl8373_mirror_portIso_set, + .mirror_portIso_get = dal_rtl8373_mirror_portIso_get, + .mirror_vlanLeaky_set = dal_rtl8373_mirror_vlanLeaky_set, + .mirror_vlanLeaky_get = dal_rtl8373_mirror_vlanLeaky_get, + .mirror_isolationLeaky_set = dal_rtl8373_mirror_isolationLeaky_set, + .mirror_isolationLeaky_get = dal_rtl8373_mirror_isolationLeaky_get, + .mirror_keep_set = dal_rtl8373_mirror_keep_set, + .mirror_keep_get = dal_rtl8373_mirror_keep_get, + .mirror_override_set = dal_rtl8373_mirror_override_set, + .mirror_override_get = dal_rtl8373_mirror_override_get, + .mirror_sampleRate_set = dal_rtl8373_mirror_sampeRate_set, + .mirror_sampleRate_get = dal_rtl8373_mirror_sampeRate_get, + .mirror_pktCnt_get = dal_rtl8373_mirror_pktCnt_get, + .mirror_samplePktCnt_get = dal_rtl8373_mirror_samplePktCnt_get, + .rspan_rxTag_en = dal_rtl8373_rspan_rxTag_en, + .rspan_rxTagEnSts_get = dal_rtl8373_rspan_rxTagEnSts_get, + .rspan_tagCtxt_set = dal_rtl8373_rspan_tagContext_set, + .rspan_tagCtxt_get = dal_rtl8373_rspan_tagContext_get, + .rspan_tagAdd_set = dal_rtl8373_rspan_tagAdd_set, + .rspan_tagAdd_get = dal_rtl8373_rspan_tagAdd_get, + .rspan_tagRemove_set = dal_rtl8373_rspan_tagRemove_set, + .rspan_tagRemove_get = dal_rtl8373_rspan_tagRemove_get, + + .port_isolation_set = dal_rtl8373_port_isolation_set, + .port_isolation_get = dal_rtl8373_port_isolation_get, + + + /* Storm */ + .rate_stormControlMeterIdx_set = dal_rtl8373_rate_stormControlMeterIdx_set, + .rate_stormControlMeterIdx_get = dal_rtl8373_rate_stormControlMeterIdx_get, + .rate_stormControlPortEnable_set = dal_rtl8373_rate_stormControlPortEnable_set, + .rate_stormControlPortEnable_get = dal_rtl8373_rate_stormControlPortEnable_get, + .storm_bypass_set = dal_rtl8373_storm_bypass_set, + .storm_bypass_get = dal_rtl8373_storm_bypass_get, + .rate_stormControlExtPortmask_set = dal_rtl8373_rate_stormControlExtPortmask_set, + .rate_stormControlExtPortmask_get = dal_rtl8373_rate_stormControlExtPortmask_get, + .rate_stormControlExtEnable_set = dal_rtl8373_rate_stormControlExtEnable_set, + .rate_stormControlExtEnable_get = dal_rtl8373_rate_stormControlExtEnable_get, + .rate_stormControlExtMeterIdx_set = dal_rtl8373_rate_stormControlExtMeterIdx_set, + .rate_stormControlExtMeterIdx_get = dal_rtl8373_rate_stormControlExtMeterIdx_get, + + /* Rate */ + .rate_shareMeter_set = dal_rtl8373_rate_shareMeter_set, + .rate_shareMeter_get = dal_rtl8373_rate_shareMeter_get, + .rate_shareMeterBucket_set = dal_rtl8373_rate_shareMeterBucket_set, + .rate_shareMeterBucket_get = dal_rtl8373_rate_shareMeterBucket_get, + .rate_shareMeterExceedStatus_set = dal_rtl8373_rate_shareMeterExceedStatus_set, + .rate_shareMeterExceedStatus_get = dal_rtl8373_rate_shareMeterExceedStatus_get, + .rate_shareMeterICPUExceedStatus_set = dal_rtl8373_rate_shareMeterICPUExceedStatus_set, + .rate_shareMeterICPUExceedStatus_get = dal_rtl8373_rate_shareMeterICPUExceedStatus_get, + /*QoS*/ + .qos_init = dal_rtl8373_qos_init, + .qos_priSel_set = dal_rtl8373_qos_priSel_set, + .qos_priSel_get = dal_rtl8373_qos_priSel_get, + .qos_1pPriRemap_set = dal_rtl8373_qos_1pPriRemap_set, + .qos_1pPriRemap_get = dal_rtl8373_qos_1pPriRemap_get, + .qos_1pRemarkSrcSel_set = dal_rtl8373_qos_1pRemarkSrcSel_set, + .qos_1pRemarkSrcSel_get = dal_rtl8373_qos_1pRemarkSrcSel_get, + .qos_dscpPriRemap_set = dal_rtl8373_qos_dscpPriRemap_set, + .qos_dscpPriRemap_get = dal_rtl8373_qos_dscpPriRemap_get, + .qos_rspanpriRemap_set = dal_rtl8373_qos_RspanPriRemap_set, + .qos_rspanpriRemap_get = dal_rtl8373_qos_RspanPriRemap_get, + .qos_portPri_set = dal_rtl8373_qos_portPri_set, + .qos_portPri_get = dal_rtl8373_qos_portPri_get, + .qos_priMap_set = dal_rtl8373_qos_priMap_set, + .qos_priMap_get = dal_rtl8373_qos_priMap_get, + .qos_schedulingQueue_set = dal_rtl8373_qos_schedulingQueue_set, + .qos_schedulingQueue_get = dal_rtl8373_qos_schedulingQueue_get, + .qos_1pRemarkEnable_set = dal_rtl8373_qos_1pRemarkEnable_set, + .qos_1pRemarkEnable_get = dal_rtl8373_qos_1pRemarkEnable_get, + .qos_1pRemark_set = dal_rtl8373_qos_1pRemark_set, + .qos_1pRemark_get = dal_rtl8373_qos_1pRemark_get, + .qos_dscpRemarkEnable_set = dal_rtl8373_qos_dscpRemarkEnable_set, + .qos_dscpRemarkEnable_get = dal_rtl8373_qos_dscpRemarkEnable_get, + .qos_intpri2dscpRemark_set = dal_rtl8373_qos_intpri2dscp_Remark_set, + .qos_intpri2dscpRemark_get = dal_rtl8373_qos_intpri2dscp_Remark_get, + .qos_dscp2dscpRemark_set = dal_rtl8373_qos_dscp2dscp_Remark_set, + .qos_dscp2dscpRemark_get = dal_rtl8373_qos_dscp2dscp_Remark_get, + .qos_dscpRemarkSrcSel_set = dal_rtl8373_qos_dscpRemarkSrcSel_set, + .qos_dscpRemarkSrcSel_get = dal_rtl8373_qos_dscpRemarkSrcSel_get, + .qos_portPriSelIndex_set = dal_rtl8373_qos_portPriSelIndex_set, + .qos_portPriSelIndex_get = dal_rtl8373_qos_portPriSelIndex_get, + .qos_schedulingType_set = dal_rtl8373_qos_schedulingType_set, + .qos_schedulingType_get = dal_rtl8373_qos_schedulingType_get, + + /*VLAN*/ + .vlan_init = dal_rtl8373_vlan_init, + .vlan_set = dal_rtl8373_vlan_set, + .vlan_get = dal_rtl8373_vlan_get, + .vlan_egrFilterEnable_set = dal_rtl8373_vlan_egrFilterEnable_set, + .vlan_egrFilterEnable_get = dal_rtl8373_vlan_egrFilterEnable_get, + .vlan_portPvid_set = dal_rtl8373_vlan_portPvid_set, + .vlan_portPvid_get = dal_rtl8373_vlan_portPvid_get, + .vlan_portIgrFilterEnable_set = dal_rtl8373_vlan_portIgrFilterEnable_set, + .vlan_portIgrFilterEnable_get = dal_rtl8373_vlan_portIgrFilterEnable_get, + .vlan_portAcceptFrameType_set = dal_rtl8373_vlan_portAcceptFrameType_set, + .vlan_portAcceptFrameType_get = dal_rtl8373_vlan_portAcceptFrameType_get, + .vlan_tagMode_set = dal_rtl8373_vlan_tagMode_set, + .vlan_tagMode_get = dal_rtl8373_vlan_tagMode_get, + .vlan_transparent_set = dal_rtl8373_vlan_portTransparent_set, + .vlan_transparent_get = dal_rtl8373_vlan_portTransparent_get, + .vlan_keep_set = dal_rtl8373_vlan_keep_set, + .vlan_keep_get = dal_rtl8373_vlan_keep_get, + .vlan_stg_set = dal_rtl8373_vlan_stg_set, + .vlan_stg_get = dal_rtl8373_vlan_stg_get, + .vlan_portFid_set = dal_rtl8373_vlan_portFid_set, + .vlan_portFid_get = dal_rtl8373_vlan_portFid_get, + .vlan_reservedVidAction_set = dal_rtl8373_vlan_reservedVidAction_set, + .vlan_reservedVidAction_get = dal_rtl8373_vlan_reservedVidAction_get, + .vlan_realKeepRemarkEnable_set = dal_rtl8373_vlan_realKeepRemarkEnable_set, + .vlan_realKeepRemarkEnable_get = dal_rtl8373_vlan_realKeepRemarkEnable_get, + .vlan_disL2Learn_entry_set = dal_rtl8373_vlan_disL2Learn_entry_set, + .vlan_disL2Learn_entry_get = dal_rtl8373_vlan_disL2Learn_entry_get, + .vlan_reset = dal_rtl8373_vlan_reset, + + /*dot1x*/ + .dot1x_unauthPacketOper_set = dal_rtl8373_dot1x_unauthPacketOper_set, + .dot1x_unauthPacketOper_get = dal_rtl8373_dot1x_unauthPacketOper_get, + //.dot1x_eapolFrame2CpuEnable_set = dal_rtl8373_dot1x_eapolFrame2CpuEnable_set, + //.dot1x_eapolFrame2CpuEnable_get = dal_rtl8373_dot1x_eapolFrame2CpuEnable_get, + .dot1x_trap2CPU_Sel_set = dal_rtl8373_dot1x_trap2CPU_Sel_set, + .dot1x_trap2CPU_Sel_get = dal_rtl8373_dot1x_trap2CPU_Sel_get, + .dot1x_trap_priority_set = dal_rtl8373_dot1x_trap_priority_set, + .dot1x_trap_priority_get = dal_rtl8373_dot1x_trap_priority_get, + .dot1x_portBasedEnable_set = dal_rtl8373_dot1x_portBasedEnable_set, + .dot1x_portBasedEnable_get = dal_rtl8373_dot1x_portBasedEnable_get, + .dot1x_portBasedAuthStatus_set = dal_rtl8373_dot1x_portBasedAuthStatus_set, + .dot1x_portBasedAuthStatus_get = dal_rtl8373_dot1x_portBasedAuthStatus_get, + .dot1x_portBasedDirection_set = dal_rtl8373_dot1x_portBasedDirection_set, + .dot1x_portBasedDirection_get = dal_rtl8373_dot1x_portBasedDirection_get, + .dot1x_macBasedEnable_set = dal_rtl8373_dot1x_macBasedEnable_set, + .dot1x_macBasedEnable_get = dal_rtl8373_dot1x_macBasedEnable_get, + .dot1x_macBasedAuthMac_add = dal_rtl8373_dot1x_macBasedAuthMac_add, + .dot1x_macBasedAuthMac_del = dal_rtl8373_dot1x_macBasedAuthMac_del, + .dot1x_macBasedDirection_set = dal_rtl8373_dot1x_macBasedDirection_set, + .dot1x_macBasedDirection_get = dal_rtl8373_dot1x_macBasedDirection_get, + .dot1x_guestVlan_set = dal_rtl8373_dot1x_guestVlan_set, + .dot1x_guestVlan_get = dal_rtl8373_dot1x_guestVlan_get, + .dot1x_guestVlan2Auth_set = dal_rtl8373_dot1x_guestVlan2Auth_set, + .dot1x_guestVlan2Auth_get = dal_rtl8373_dot1x_guestVlan2Auth_get, + + /*MACsec*/ + .macsec_enable_set = dal_rtl8373_macsec_enable_set, + .macsec_enable_get = dal_rtl8373_macsec_enable_get, + .macsec_egress_set = dal_rtl8373_macsec_egress_set, + .macsec_egress_get = dal_rtl8373_macsec_egress_get, + .macsec_ingress_set = dal_rtl8373_macsec_ingress_set, + .macsec_ingress_get = dal_rtl8373_macsec_ingress_get, + .macsec_rxgating_set = dal_rtl8373_macsec_rxgating_set, + .macsec_rxgating_cancel = dal_rtl8373_macsec_rxgating_cancel, + .macsec_txgating_set = dal_rtl8373_macsec_txgating_set, + .macsec_txgating_cancel = dal_rtl8373_macsec_txgating_cancel, + .macsec_rxIPbypass_set = dal_rtl8373_macsec_rxIPbypass_set, + .macsec_rxIPbypass_get = dal_rtl8373_macsec_rxIPbypass_get, + .macsec_txIPbypass_set = dal_rtl8373_macsec_txIPbypass_set, + .macsec_txIPbypass_get = dal_rtl8373_macsec_txIPbypass_get, + .macsec_rxbypass_set = dal_rtl8373_macsec_rxbypass_set, + .macsec_rxbypass_get = dal_rtl8373_macsec_rxbypass_get, + .macsec_txbypass_set = dal_rtl8373_macsec_txbypass_set, + .macsec_txbypass_get = dal_rtl8373_macsec_txbypass_get, + .wrapper_int_control_set = dal_rtl8373_wrapper_int_control_set, + .wrapper_int_control_get = dal_rtl8373_wrapper_int_control_get, + .wrapper_int_status_set = dal_rtl8373_wrapper_int_status_set, + .wrapper_int_status_get = dal_rtl8373_wrapper_int_status_get, + .wrapper_mib_reset = dal_rtl8373_wrapper_mib_reset, + .wrapper_mib_counter = dal_rtl8373_wrapper_mib_counter, + .macsec_ipg_len_set = dal_rtl8373_macsec_ipg_len_set, + .macsec_ipg_len_get = dal_rtl8373_macsec_ipg_len_get, + .macsec_ipg_mode_set = dal_rtl8373_macsec_ipg_mode_set, + .macsec_ipg_mode_get = dal_rtl8373_macsec_ipg_mode_get, + .macsec_eth_set = dal_rtl8373_macsec_eth_set, + .macsec_eth_get = dal_rtl8373_macsec_eth_get, + .macsec_init = dal_rtl8373_macsec_init, + + /*SVLAN*/ + .svlan_init = dal_rtl8373_svlanInit, + .svlan_servicePort_add = dal_rtl8373_svlanServicePort_add, + .svlan_servicePort_get = dal_rtl8373_svlanServicePort_get, + .svlan_servicePort_del = dal_rtl8373_svlanServicePort_del, + .svlan_tpidEntry_set = dal_rtl8373_svlanTpid_set, + .svlan_tpidEntry_get = dal_rtl8373_svlanTpid_get, + .svlan_priorityRef_set = dal_rtl8373_svlanPriRef_set, + .svlan_priorityRef_get = dal_rtl8373_svlanPriRef_get, + // .svlan_memberPortEntry_set = dal_rtl8373_svlanMbrrPortEntry_set, + // .svlan_memberPortEntry_get = dal_rtl8373_svlanmemberPortEntry_get, + //.svlan_memberPortEntry_adv_set = NULL, + //.svlan_memberPortEntry_adv_get = NULL, + .svlan_defaultSvlan_set = dal_rtl8373_svlanDfltSvlan_set, + .svlan_defaultSvlan_get = dal_rtl8373_svlanDfltSvlan_get, + .svlan_c2s_add = dal_rtl8373_svlanC2S_add, + .svlan_c2s_del = dal_rtl8373_svlanC2S_del, + .svlan_c2s_get = dal_rtl8373_svlanC2S_get, + .svlan_untag_action_set = dal_rtl8373_svlanUntagAction_set, + .svlan_untag_action_get = dal_rtl8373_svlanUntagAction_get, + .svlan_trapPri_set = dal_rtl8373_svlanTrapPri_set, + .svlan_trapPri_get = dal_rtl8373_svlanTrapPri_get, + .svlan_unassign_action_set = dal_rtl8373_svlanUnassignAction_set, + .svlan_unassign_action_get = dal_rtl8373_svlanUnassignAction_get, + .svlan_trapCpuMsk_set = dal_rtl8373_svlanTrapCpumsk_set, + .svlan_trapCpuMsk_get = dal_rtl8373_svlanTrapCpumsk_get, + + /*NIC*/ + .nic_rst_set = dal_rtl8373_nic_rst_set, + .nic_txStopAddr_set = dal_rtl8373_nic_txStopAddr_set, + .nic_txStopAddr_get = dal_rtl8373_nic_txStopAddr_get, + .nic_rxStopAddr_set = dal_rtl8373_nic_rxStopAddr_set, + .nic_rxStopAddr_get = dal_rtl8373_nic_rxStopAddr_get, + .nic_swRxCurPktAddr_get = dal_rtl8373_nic_swRxCurPktAddr_get, + .nic_rxReceivedPktLen_get = dal_rtl8373_nic_rxReceivedPktLen_get, + .nic_txAvailSpace_get = dal_rtl8373_nic_txAvailSpace_get, + .nic_moduleEn_set = dal_rtl8373_nic_moduleEn_set, + .nic_moduleEn_get = dal_rtl8373_nic_moduleEn_get, + .nic_rxEn_set = dal_rtl8373_nic_rxEn_set, + .nic_rxEn_get = dal_rtl8373_nic_rxEn_get, + .nic_txEn_set = dal_rtl8373_nic_txEn_set, + .nic_txEn_get = dal_rtl8373_nic_txEn_get, + .nic_rxRemoveCrc_set = dal_rtl8373_nic_rxRemoveCrc_set, + .nic_rxRemoveCrc_get = dal_rtl8373_nic_rxRemoveCrc_get, + .nic_rxPaddingEn_set = dal_rtl8373_nic_rxPaddingEn_set, + .nic_rxPaddingEn_get = dal_rtl8373_nic_rxPaddingEn_get, + .nic_rxFreeSpaceThd_set = dal_rtl8373_nic_rxFreeSpaceThd_set, + .nic_rxFreeSpaceThd_get = dal_rtl8373_nic_rxFreeSpaceThd_get, + .nic_rxCrcErrEn_set = dal_rtl8373_nic_rxCrcErrEn_set, + .nic_rxCrcErrEn_get = dal_rtl8373_nic_rxCrcErrEn_get, + .nic_rxL3CrcErrEn_set = dal_rtl8373_nic_rxL3CrcErrEn_set, + .nic_rxL3CrcErrEn_get = dal_rtl8373_nic_rxL3CrcErrEn_get, + .nic_rxL4CrcErrEn_set = dal_rtl8373_nic_rxL4CrcErrEn_set, + .nic_rxL4CrcErrEn_get = dal_rtl8373_nic_rxL4CrcErrEn_get, + .nic_rxArpEn_set = dal_rtl8373_nic_rxArpEn_set, + .nic_rxArpEn_get = dal_rtl8373_nic_rxArpEn_get, + .nic_rxAllPktEn_set = dal_rtl8373_nic_rxAllPktEn_set, + .nic_rxAllPktEn_get = dal_rtl8373_nic_rxAllPktEn_get, + .nic_rxPhyPktSel_set = dal_rtl8373_nic_rxPhyPktSel_set, + .nic_rxPhyPktSel_get = dal_rtl8373_nic_rxPhyPktSel_get, + .nic_rxMultiPktEn_set = dal_rtl8373_nic_rxMultiPktEn_set, + .nic_rxMultiPktEn_get = dal_rtl8373_nic_rxMultiPktEn_get, + .nic_rxBcPktEn_set = dal_rtl8373_nic_rxBcPktEn_set, + .nic_rxBcPktEn_get = dal_rtl8373_nic_rxBcPktEn_get, + .nic_mcHashFltrEn_set = dal_rtl8373_nic_mcHashFltrEn_set, + .nic_mcHashFltrEn_get = dal_rtl8373_nic_mcHashFltrEn_get, + .nic_phyPktHashFltrEn_set = dal_rtl8373_nic_phyPktHashFltrEn_set, + .nic_phyPktHashFltrEn_get = dal_rtl8373_nic_phyPktHashFltrEn_get, + .nic_mcHashTblVal_set = dal_rtl8373_nic_mcHashTblVal_set, + .nic_mcHashTblVal_get = dal_rtl8373_nic_mcHashTblVal_get, + .nic_phyPktHashTblVal_set = dal_rtl8373_nic_phyPktHashTblVal_set, + .nic_phyPktHashTblVal_get = dal_rtl8373_nic_phyPktHashTblVal_get, + .nic_rxMTU_set = dal_rtl8373_nic_rxMTU_set, + .nic_rxMTU_get = dal_rtl8373_nic_rxMTU_get, + .nic_loopbackEn_set = dal_rtl8373_nic_loopbackEn_set, + .nic_loopbackEn_get = dal_rtl8373_nic_loopbackEn_get, + .nic_interruptEn_set = dal_rtl8373_nic_interruptEn_set, + .nic_interruptEn_get = dal_rtl8373_nic_interruptEn_get, + .nic_interruptStatus_get = dal_rtl8373_nic_interruptStatus_get, + .nic_interruptStatus_clear = dal_rtl8373_nic_interruptStatus_clear, + + /* IGMP */ + .igmp_init = dal_rtl8373_igmp_init, + .igmp_state_set = dal_rtl8373_igmp_state_set, + .igmp_state_get = dal_rtl8373_igmp_state_get, + .igmp_static_router_port_set = dal_rtl8373_igmp_static_router_port_set, + .igmp_static_router_port_get = dal_rtl8373_igmp_static_router_port_get, + .igmp_protocol_set = dal_rtl8373_igmp_protocol_set, + .igmp_protocol_get = dal_rtl8373_igmp_protocol_get, + .igmp_fastLeave_set = dal_rtl8373_igmp_fastLeave_set, + .igmp_fastLeave_get = dal_rtl8373_igmp_fastLeave_get, + .igmp_maxGroup_set = dal_rtl8373_igmp_maxGroup_set, + .igmp_maxGroup_get = dal_rtl8373_igmp_maxGroup_get, + .igmp_currentGroup_get = dal_rtl8373_igmp_currentGroup_get, + .igmp_tableFullAction_set = dal_rtl8373_igmp_tableFullAction_set, + .igmp_tableFullAction_get = dal_rtl8373_igmp_tableFullAction_get, + .igmp_checksumErrorAction_set = dal_rtl8373_igmp_checksumErrorAction_set, + .igmp_checksumErrorAction_get = dal_rtl8373_igmp_checksumErrorAction_get, + .igmp_leaveTimer_set = dal_rtl8373_igmp_leaveTimer_set, + .igmp_leaveTimer_get = dal_rtl8373_igmp_leaveTimer_get, + .igmp_queryInterval_set = dal_rtl8373_igmp_queryInterval_set, + .igmp_queryInterval_get = dal_rtl8373_igmp_queryInterval_get, + .igmp_robustness_set = dal_rtl8373_igmp_robustness_set, + .igmp_robustness_get = dal_rtl8373_igmp_robustness_get, + .igmp_dynamicRouterPortAllow_set = dal_rtl8373_igmp_dynamicRouterPortAllow_set, + .igmp_dynamicRouterPortAllow_get = dal_rtl8373_igmp_dynamicRouterPortAllow_get, + .igmp_dynamicRouterPort_get = dal_rtl8373_igmp_dynamicRouterPort_get, + .igmp_suppressionEnable_set = dal_rtl8373_igmp_suppressionEnable_set, + .igmp_suppressionEnable_get = dal_rtl8373_igmp_suppressionEnable_get, + .igmp_portRxPktEnable_set = dal_rtl8373_igmp_portRxPktEnable_set, + .igmp_portRxPktEnable_get = dal_rtl8373_igmp_portRxPktEnable_get, + .igmp_groupInfo_get = dal_rtl8373_igmp_groupInfo_get, + .igmp_ReportLeaveFwdAction_set = dal_rtl8373_igmp_ReportLeaveFwdAction_set, + .igmp_ReportLeaveFwdAction_get = dal_rtl8373_igmp_ReportLeaveFwdAction_get, + .igmp_dropLeaveZeroEnable_set = dal_rtl8373_igmp_dropLeaveZeroEnable_set, + .igmp_dropLeaveZeroEnable_get = dal_rtl8373_igmp_dropLeaveZeroEnable_get, + .igmp_bypassGroupRange_set = dal_rtl8373_igmp_bypassGroupRange_set, + .igmp_bypassGroupRange_get = dal_rtl8373_igmp_bypassGroupRange_get, +#if 1 + /*RLDP*/ + .rldp_config_set = dal_rtl8373_rldp_config_set, + .rldp_config_get = dal_rtl8373_rldp_config_get, + .rldp_portConfig_set = dal_rtl8373_rldp_portConfig_set, + .rldp_portConfig_get = dal_rtl8373_rldp_portConfig_get, + .rldp_status_get = NULL, + .rldp_portStatus_get = dal_rtl8373_rldp_portStatus_get, + .rldp_portStatus_set = NULL, + .rldp_portLoopPair_get = dal_rtl8373_rldp_portLoopPair_get, +#endif + +#if 1 + /*trunk*/ + .trunk_port_set = dal_rtl8373_trunk_port_set, + .trunk_port_get = dal_rtl8373_trunk_port_get, + .trunk_distributionAlgorithm_set = dal_rtl8373_trunk_distributionAlgorithm_set, + .trunk_distributionAlgorithm_get = dal_rtl8373_trunk_distributionAlgorithm_get, + .trunk_trafficSeparate_set = dal_rtl8373_trunk_trafficSeparate_set, + .trunk_trafficSeparate_get = dal_rtl8373_trunk_trafficSeparate_get, + .trunk_mode_set = NULL, + .trunk_mode_get = NULL, + .trunk_trafficPause_set = dal_rtl8373_trunk_trafficPause_set, + .trunk_trafficPause_get = dal_rtl8373_trunk_trafficPause_get, + .trunk_hashMappingTable_set = NULL, + .trunk_hashMappingTable_get = NULL, + .trunk_portQueueEmpty_get = dal_rtl8373_trunk_portQueueEmpty_get, +#endif + + /* l2 */ + .l2_init = dal_rtl8373_l2_init, + .l2_addr_add = dal_rtl8373_l2_addr_add, + .l2_addr_get = dal_rtl8373_l2_addr_get, + .l2_addr_next_get = dal_rtl8373_l2_addr_next_get, + .l2_addr_del = dal_rtl8373_l2_addr_del, + .l2_mcastAddr_add = dal_rtl8373_l2_mcastAddr_add, + .l2_mcastAddr_get = dal_rtl8373_l2_mcastAddr_get, + .l2_mcastAddr_next_get = dal_rtl8373_l2_mcastAddr_next_get, + .l2_mcastAddr_del = dal_rtl8373_l2_mcastAddr_del, + .l2_ipMcastAddr_add = dal_rtl8373_l2_ipMcastAddr_add, + .l2_ipMcastAddr_get = dal_rtl8373_l2_ipMcastAddr_get, + .l2_ipMcastAddr_next_get = dal_rtl8373_l2_ipMcastAddr_next_get, + .l2_ipMcastAddr_del = dal_rtl8373_l2_ipMcastAddr_del, + .l2_ucastAddr_flush = NULL, + .l2_table_clear = dal_rtl8373_l2_table_clear, + .l2_table_clearStatus_get = dal_rtl8373_l2_table_clearStatus_get, + .l2_flushLinkDownPortAddrEnable_set = dal_rtl8373_l2_flushLinkDownPortAddrEnable_set, + .l2_flushLinkDownPortAddrEnable_get = dal_rtl8373_l2_flushLinkDownPortAddrEnable_get, + .l2_agingEnable_set = dal_rtl8373_l2_agingEnable_set, + .l2_agingEnable_get = dal_rtl8373_l2_agingEnable_get, + .l2_limitLearningCnt_set = dal_rtl8373_l2_limitLearningCnt_set, + .l2_limitLearningCnt_get = dal_rtl8373_l2_limitLearningCnt_get, + .l2_limitSystemLearningCnt_set = dal_rtl8373_l2_limitSystemLearningCnt_set, + .l2_limitSystemLearningCnt_get = dal_rtl8373_l2_limitSystemLearningCnt_get, + .l2_limitLearningCntAction_set = dal_rtl8373_l2_limitLearningCntAction_set, + .l2_limitLearningCntAction_get = dal_rtl8373_l2_limitLearningCntAction_get, + .l2_limitSystemLearningCntAction_set = dal_rtl8373_l2_limitSystemLearningCntAction_set, + .l2_limitSystemLearningCntAction_get = dal_rtl8373_l2_limitSystemLearningCntAction_get, + .l2_limitSystemLearningCntPortMask_set = dal_rtl8373_l2_limitSystemLearningCntPortMask_set, + .l2_limitSystemLearningCntPortMask_get = dal_rtl8373_l2_limitSystemLearningCntPortMask_get, + .l2_learningCnt_get = dal_rtl8373_l2_learningCnt_get, + .l2_floodPortMask_set = dal_rtl8373_l2_floodPortMsk_set, + .l2_floodPortMask_get = dal_rtl8373_l2_floodPortMsk_get, + .l2_localPktPermit_set = dal_rtl8373_srcPortPermit_set, + .l2_localPktPermit_get = dal_rtl8373_srcPortPermit_get, + .l2_aging_set = dal_rtl8373_l2_ageout_timer_set, + .l2_aging_get = dal_rtl8373_l2_ageout_timer_get, + .l2_ipMcastAddrLookup_set = dal_rtl8373_l2_ipMcastAddrLookup_set, + .l2_ipMcastAddrLookup_get = dal_rtl8373_l2_ipMcastAddrLookup_get, + .l2_ipMcastForwardRouterPort_set = NULL, + .l2_ipMcastForwardRouterPort_get = NULL, + .l2_ipMcastGroupEntry_add = dal_rtl8373_l2_ipMcastGroupEntry_add, + .l2_ipMcastGroupEntry_del = dal_rtl8373_l2_ipMcastGroupEntry_del, + .l2_ipMcastGroupEntry_get = dal_rtl8373_l2_ipMcastGroupEntry_get, + .l2_entry_get = dal_rtl8373_l2_entry_get, + .l2_lookupHitIsolationAction_set = dal_rtl8373_l2_lookupHitIsolationAction_set, + .l2_lookupHitIsolationAction_get = dal_rtl8373_l2_lookupHitIsolationAction_get, + .l2_unknownUnicastPktAction_set = dal_rtl8373_l2_unknUc_action_set, + .l2_unknownUnicastPktAction_get = dal_rtl8373_l2_unknUc_action_get, + .l2_unknownMulticastPktAction_set = dal_rtl8373_l2_unknMc_action_set, + .l2_unknownMulticastPktAction_get = dal_rtl8373_l2_unknMc_action_get, + .l2_unknownV4McPktAction_set = dal_rtl8373_l2_unknV4Mc_action_set, + .l2_unknownV4McPktAction_get = dal_rtl8373_l2_unknV4Mc_action_get, + .l2_unknownV6McPktAction_set = dal_rtl8373_l2_unknV6Mc_action_set, + .l2_unknownV6McPktAction_get = dal_rtl8373_l2_unknV6Mc_action_get, + + /*GPIO*/ + .gpio_muxSel_set = dal_rtl8373_gpio_muxSel_set, + .gpio_muxSel_get = dal_rtl8373_gpio_muxSel_get, + .gpio_groupVal_write = dal_rtl8373_gpio_groupVal_write, + .gpio_groupVal_read = dal_rtl8373_gpio_groupVal_read, + .gpio_pinVal_write = dal_rtl8373_gpio_pinVal_write, + .gpio_pinVal_read = dal_rtl8373_gpio_pinVal_read, + .gpio_pinDir_set = dal_rtl8373_gpio_pinDir_set, + .gpio_pinDir_get = dal_rtl8373_gpio_pinDir_get, + .gpio_groupDir_get = dal_rtl8373_gpio_groupDir_get, + + /*I2C*/ + .i2c_init = dal_rtl8373_i2c_init, + .i2c_readMode_set = dal_rtl8373_i2c_readMode_set, + .i2c_readMode_get = dal_rtl8373_i2c_readMode_get, + .i2c_gpioPinGroup_set = dal_rtl8373_i2c_gpioPinGroup_set, + .i2c_gpioPinGroup_get = dal_rtl8373_i2c_gpioPinGroup_get, + .i2c_data_read = dal_rtl8373_i2c_data_read, + .i2c_data_write = dal_rtl8373_i2c_data_write, + + /*Rate : ingress BW & egress queue BW*/ + .rate_igrBwCtrlPortEn_set = dal_rtl8373_rate_igrBwCtrlPortEn_set, + .rate_igrBwCtrlPortEn_get = dal_rtl8373_rate_igrBwCtrlPortEn_get, + .rate_igrBwCtrlRate_set = dal_rtl8373_rate_igrBwCtrlRate_set, + .rate_igrBwCtrlRate_get = dal_rtl8373_rate_igrBwCtrlRate_get, + .rate_igrBwCtrlIfg_set = dal_rtl8373_rate_igrBwCtrlIfg_set, + .rate_igrBwCtrlIfg_get = dal_rtl8373_rate_igrBwCtrlIfg_get, + .rate_igrBwCtrlCongestSts_get = dal_rtl8373_rate_igrBwCtrlCongestSts_get, + .rate_egrBandwidthCtrlRate_set = dal_rtl8373_rate_egrBwCtrlRate_set, + .rate_egrBandwidthCtrlRate_get = dal_rtl8373_rate_egrBwCtrlRate_get, + .rate_egrQueueBwCtrlEnable_set = dal_rtl8373_rate_egrQueueMaxBwEn_set, + .rate_egrQueueBwCtrlEnable_get = dal_rtl8373_rate_egrQueueMaxBwEn_get, + .rate_egrQueueBwCtrlRate_set = dal_rtl8373_rate_egrQueueMaxBwRate_set, + .rate_egrQueueBwCtrlRate_get = dal_rtl8373_rate_egrQueueMaxBwRate_get, + + + /* eee */ + .eee_init = dal_rtl8373_eee_init, + .eee_macForceSpeedEn_set = dal_rtl8373_eee_macForceSpeedEn_set, + .eee_macForceSpeedEn_get = dal_rtl8373_eee_macForceSpeedEn_get, + .eee_macForceAllSpeedEn_get = dal_rtl8373_eee_macForceAllSpeedEn_get, + .eee_portTxRxEn_set = dal_rtl8373_eee_portTxRxEn_set, + .eee_portTxRxEn_get = dal_rtl8373_eee_portTxRxEn_get, + + /* interrupt */ + .int_enable = dal_rtl8373_IE_set, + .int_polarity_set = dal_rtl8373_intMode_set, + .int_polarity_get = dal_rtl8373_intMode_get, + .int_control_set = dal_rtl8373_portIntIMR_set, + .int_control_get = dal_rtl8373_portIntIMR_get, + .int_miscIMR_set = dal_rtl8373_miscIMR_set, + .int_miscIMR_get = dal_rtl8373_miscIMR_get, + .int_miscISR_clear = dal_rtl8373_miscISR_clear, + .int_miscISR_get = dal_rtl8373_miscISR_get, + /* mib */ + .stat_global_reset = dal_rtl8373_globalMib_rst, + .stat_port_reset = dal_rtl8373_portMib_rst, + .stat_port_get = dal_rtl8373_portMib_read, + .stat_lengthMode_set = dal_rtl8373_mibLength_set, + .stat_lengthMode_get = dal_rtl8373_mibLength_get, + + /*RMA*/ + + .rma_set = dal_rtl8373_asicRma_set, + .rma_get = dal_rtl8373_asicRma_get, + + /*LED*/ + .led_blinkRate_set = dal_rtl8373_led_blinkRate_set, + .led_blinkRate_get = dal_rtl8373_led_blinkRate_get, + .led_groupConfig_set = dal_rtl8373_led_config_set, + .led_portSelConfig_set = dal_rtl8373_portLedConfig_set, + .led_portSelConfig_get = dal_rtl8373_portLedConfig_get, + + + /*port*/ + .port_macForceLink_set = dal_rtl8373_portFrcAbility_set, + .port_macForceLink_get = dal_rtl8373_portFrcAbility_get, + .port_macStatus_get = dal_rtl8373_portStatus_get, + .port_macLocalLoopbackEnable_set = dal_rtl8373_portLoopbackEn_set, + .port_macLocalLoopbackEnable_get = dal_rtl8373_portLoopbackEn_get, + .port_backpressureEnable_set = dal_rtl8373_portBackpressureEn_set, + .port_backpressureEnable_get = dal_rtl8373_portBackpressureEn_get, + .port_rtct_init = dal_rtl8373_rtct_init, + .port_rtct_start = dal_rtl8373_rtct_start, + .port_rtctResult_get = dal_rtl8373_rtct_status_get, + .port_sdsMode_set = dal_rtl8373_sdsMode_set, + .port_sdsMode_get = dal_rtl8373_sdsMode_get, + +#if 0 + + /*leaky*/ + .leaky_vlan_set = dal_rtl8373_leaky_vlan_set, + .leaky_vlan_get = dal_rtl8373_leaky_vlan_get, + .leaky_portIsolation_set = dal_rtl8373_leaky_portIsolation_set, + .leaky_portIsolation_get = dal_rtl8373_leaky_portIsolation_get, + + /* led */ + .led_enable_set = dal_rtl8373_led_enable_set, + .led_enable_get = dal_rtl8373_led_enable_get, + .led_operation_set = dal_rtl8373_led_operation_set, + .led_operation_get = dal_rtl8373_led_operation_get, + .led_modeForce_set = dal_rtl8373_led_modeForce_set, + .led_modeForce_get = dal_rtl8373_led_modeForce_get, + .led_blinkRate_set = dal_rtl8373_led_blinkRate_set, + .led_blinkRate_get = dal_rtl8373_led_blinkRate_get, + .led_groupConfig_set = dal_rtl8373_led_groupConfig_set, + .led_groupConfig_get = dal_rtl8373_led_groupConfig_get, + .led_groupAbility_set = dal_rtl8373_led_groupAbility_set, + .led_groupAbility_get = dal_rtl8373_led_groupAbility_get, + .led_serialMode_set = dal_rtl8373_led_serialMode_set, + .led_serialMode_get = dal_rtl8373_led_serialMode_get, + .led_OutputEnable_set = dal_rtl8373_led_OutputEnable_set, + .led_OutputEnable_get = dal_rtl8373_led_OutputEnable_get, + .led_serialModePortmask_set = NULL, + .led_serialModePortmask_get = NULL, + + /* oam */ + .oam_init = NULL, + .oam_state_set = NULL, + .oam_state_get = NULL, + .oam_parserAction_set = NULL, + .oam_parserAction_get = NULL, + .oam_multiplexerAction_set = NULL, + .oam_multiplexerAction_get = NULL, + + /* stat */ + .stat_global_reset = dal_rtl8373_stat_global_reset, + .stat_port_reset = dal_rtl8373_stat_port_reset, + .stat_queueManage_reset = dal_rtl8373_stat_queueManage_reset, + .stat_global_get = dal_rtl8373_stat_global_get, + .stat_global_getAll = dal_rtl8373_stat_global_getAll, + .stat_port_get = dal_rtl8373_stat_port_get, + .stat_port_getAll = dal_rtl8373_stat_port_getAll, + .stat_logging_counterCfg_set = dal_rtl8373_stat_logging_counterCfg_set, + .stat_logging_counterCfg_get = dal_rtl8373_stat_logging_counterCfg_get, + .stat_logging_counter_reset = dal_rtl8373_stat_logging_counter_reset, + .stat_logging_counter_get = dal_rtl8373_stat_logging_counter_get, + .stat_lengthMode_set = dal_rtl8373_stat_lengthMode_set, + .stat_lengthMode_get = dal_rtl8373_stat_lengthMode_get, + + + /* interrupt */ + .int_polarity_set = dal_rtl8373_int_polarity_set, + .int_polarity_get = dal_rtl8373_int_polarity_get, + .int_control_set = dal_rtl8373_int_control_set, + .int_control_get = dal_rtl8373_int_control_get, + .int_status_set = dal_rtl8373_int_status_set, + .int_status_get = dal_rtl8373_int_status_get, + .int_advanceInfo_get = dal_rtl8373_int_advanceInfo_get, + + /* port */ + .port_phyAutoNegoAbility_set = dal_rtl8373_port_phyAutoNegoAbility_set, + .port_phyAutoNegoAbility_get = dal_rtl8373_port_phyAutoNegoAbility_get, + .port_phyForceModeAbility_set = dal_rtl8373_port_phyForceModeAbility_set, + .port_phyForceModeAbility_get = dal_rtl8373_port_phyForceModeAbility_get, + .port_phyStatus_get = dal_rtl8373_port_phyStatus_get, + + .port_macForceLinkExt_set = dal_rtl8373_port_macForceLinkExt_set, + .port_macForceLinkExt_get = dal_rtl8373_port_macForceLinkExt_get, + + + .port_phyReg_set = dal_rtl8373_port_phyReg_set, + .port_phyReg_get = dal_rtl8373_port_phyReg_get, + + .port_adminEnable_set = dal_rtl8373_port_adminEnable_set, + .port_adminEnable_get = dal_rtl8373_port_adminEnable_get + .port_rgmiiDelayExt_set = dal_rtl8373_port_rgmiiDelayExt_set, + .port_rgmiiDelayExt_get = dal_rtl8373_port_rgmiiDelayExt_get, + .port_phyEnableAll_set = dal_rtl8373_port_phyEnableAll_set, + .port_phyEnableAll_get = dal_rtl8373_port_phyEnableAll_get, + .port_efid_set = NULL, + .port_efid_get = NULL, + .port_phyComboPortMedia_set = dal_rtl8373_port_phyComboPortMedia_set, + .port_phyComboPortMedia_get = dal_rtl8373_port_phyComboPortMedia_get, + .port_rtctEnable_set = NULL, + .port_rtctDisable_set = NULL, + .port_rtctResult_get = NULL, + .port_sds_reset = NULL, + .port_sgmiiLinkStatus_get = dal_rtl8373_port_sgmiiLinkStatus_get, + .port_sgmiiNway_set = dal_rtl8373_port_sgmiiNway_set, + .port_sgmiiNway_get = dal_rtl8373_port_sgmiiNway_get, + .port_fiberAbilityExt_set = NULL, + .port_fiberAbilityExt_get = NULL, + +#endif + .port_autoDos_set = dal_rtl8373_asicDos_set, + .port_autoDos_get = dal_rtl8373_asicDos_get, + + /*PTP*/ + .time_init = dal_rtl8373_ptp_init, + .time_portPtpbypassptpEn_get = dal_rtl8373_bypassptpEn_get, + .time_portPtpbypassptpEn_set = dal_rtl8373_bypassptpEn_set, + .time_portPtpEnable_get = NULL, + .time_portPtpEnable_set = NULL, + .time_portPtpOper_triger =dal_rtl8373_ptp_Oper_triger, + .time_portRefTime_get=dal_rtl8373_ptp_refTime_get, + .time_portRefTime_set=dal_rtl8373_ptp_refTime_set, + .time_portRefTimeAdjust_set = dal_rtl8373_ptp_refTimeAdjust_set, + .time_portPtpVlanTpid_get = dal_rtl8373_ptp_tpid_get, + .time_portPtpVlanTpid_set = dal_rtl8373_ptp_tpid_set, + .time_portPtpOper_get = dal_rtl8373_ptp_Oper_get, + .time_portPtpOper_set = dal_rtl8373_ptp_Oper_set, + .time_portPtpLatchTime_get = dal_rtl8373_ptp_LatchTime_get, + .time_portPtpRefTimeFreqCfg_get = dal_rtl8373_ptp_RefTimeFreqCfg_get, + .time_portPtpRefTimeFreqCfg_set = dal_rtl8373_ptp_RefTimeFreqCfg_set, + .time_portPtpClkSrcCtrl_set = dal_rtl8373_ptp_ClkSrcCtrl_set, + .time_portPtpClkSrcCtrl_get = dal_rtl8373_ptp_ClkSrcCtrl_get, + + .time_portPtpTxTimestampFifo_get = dal_rtl8373_ptp_TxTimestampFifo_get , + .time_portPtp1PPSOutput_get = dal_rtl8373_ptp_1PPSOutput_get, + .time_portPtp1PPSOutput_set = dal_rtl8373_ptp_1PPSOutput_set, + .time_portPtpClockOutput_get = dal_rtl8373_ptp_ClockOutput_get, + .time_portPtpClockOutput_set = dal_rtl8373_ptp_ClockOutput_set, + .time_portPtpToddelay_set =dal_rtl8373_ptp_toddelay_set, + .time_portPtpToddelay_get =dal_rtl8373_ptp_toddelay_get, + .time_portPtpPortctrl_get = dal_rtl8373_ptp_portctrl_get, + .time_portPtpPortctrl_set = dal_rtl8373_ptp_portctrl_set, + .ptp_intControl_set = dal_rtl8373_ptp_intControl_set, + .ptp_intControl_get = dal_rtl8373_ptp_intControl_get, + .ptp_portTrap_set = dal_rtl8373_ptp_portTrap_set, + .ptp_portTrap_get = dal_rtl8373_ptp_portTrap_get, + .ptp_intStatus_get = dal_rtl8373_ptp_intStatus_get, + + + +}; + +/* + * Macro Declaration + */ + +/* + * Function Declaration + */ + + +/* Module Name : */ + +/* Function Name: + * dal_rtl8373_mapper_get + * Description: + * Get DAL mapper function + * Input: + * None + * Output: + * None + * Return: + * dal_mapper_t * - mapper pointer + * Note: + */ +dal_mapper_t *dal_rtl8373_mapper_get(void) +{ + + return &dal_rtl8373_mapper; +} /* end of dal_rtl8373_mapper_get */ + diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_mapper.h b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_mapper.h new file mode 100755 index 00000000..4f8d12fd --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_mapper.h @@ -0,0 +1,54 @@ + +/* + * Copyright(c) Realtek Semiconductor Corporation, 2011 + * All rights reserved. + * + * Purpose : Enterprise Switch RTK API mapper table + * + * Feature : + * + */ + +#ifndef __DAL_RTL8373_MAPPER_H__ +#define __DAL_RTL8373_MAPPER_H__ + +/* + * Include Files + */ +#include +#include +#include + + +/* + * Symbol Definition + */ + +/* + * Data Declaration + */ + +/* + * Macro Declaration + */ + +/* + * Function Declaration + */ + + +/* Function Name: + * dal_rtl8373_mapper_get + * Description: + * Get DAL mapper function + * Input: + * None + * Output: + * None + * Return: + * dal_mapper_t * - mapper pointer + * Note: + */ +extern dal_mapper_t *dal_rtl8373_mapper_get(void); + +#endif /* __DAL_RTL8373_MAPPER_H__ */ diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_mib.c b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_mib.c new file mode 100755 index 00000000..f189b470 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_mib.c @@ -0,0 +1,251 @@ +/* + * Copyright (C) 2012 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision: $ + * $Date: $ + * + * Purpose : Declaration of MIB + * + * Feature : The file have include the following module and sub-modules + * 1) MIB reset , get + * + */ + + +/* + * Include Files + */ +#include +#include +#include +#include + + +/* Function Name: + * dal_rtl8373_globalMib_rst + * Description: + * global mib reset + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t dal_rtl8373_globalMib_rst(void) +{ + ret_t retVal; + + retVal = rtl8373_setAsicRegBit(RTL8373_STAT_RST_ADDR, RTL8373_STAT_RST_RST_GLB_MIB_OFFSET,1); + + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_portMib_rst + * Description: + * port mib reset + * Input: + * port: the port to reset mib + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t dal_rtl8373_portMib_rst(rtk_uint32 port) +{ + ret_t retVal; + rtk_uint32 tmp; + + tmp = (1 << 4)| port; + + retVal = rtl8373_setAsicReg(RTL8373_STAT_PORT_RST_ADDR, tmp); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_dbgMib_rst + * Description: + * debug mib reset + * Input: + * port: the port to reset mib + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t dal_rtl8373_dbgMib_rst(rtk_uint32 port) +{ + ret_t retVal; + + retVal = rtl8373_setAsicRegBit(RTL8373_DEBUG_MIB_RST_ADDR(port), RTL8373_DEBUG_MIB_RST_WRAP_MIB_RST_OFFSET(port), 1); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + + + +/* Function Name: + * dal_rtl8373_dbgMib_rst + * Description: + * debug mib reset + * Input: + * port: the port to reset mib + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t dal_rtl8373_portMib_read(rtk_uint32 portid, rtk_stat_port_type_t mibid, rtk_uint64 * pMibCounter) +{ + ret_t retVal; + rtk_uint32 tmp, wait, mibReqIdx = 0; + rtk_uint32 dataH, dataL; + + mibReqIdx = mibid/2; + tmp = 1 | ((portid & 0xf) << 1) | ((mibReqIdx & 0x3f) << 5); + //printk("regvalue 0x%x ", tmp); + retVal = rtl8373_setAsicReg(RTL8373_INDIRECT_ACCESS_CTRL_ADDR, tmp); + if(retVal != RT_ERR_OK) + return retVal; + + wait = 0; + retVal = rtl8373_getAsicRegBit(RTL8373_INDIRECT_ACCESS_CTRL_ADDR, RTL8373_INDIRECT_ACCESS_CTRL_ACC_CMD_OFFSET, &tmp); + if(retVal != RT_ERR_OK) + return retVal; + + while(tmp & 1) + { + wait++; + if(wait > 100) + return RT_ERR_FAILED; + + retVal = rtl8373_getAsicRegBit(RTL8373_INDIRECT_ACCESS_CTRL_ADDR, RTL8373_INDIRECT_ACCESS_CTRL_ACC_CMD_OFFSET, &tmp); + if(retVal != RT_ERR_OK) + return retVal; + } + + retVal = rtl8373_getAsicReg(RTL8373_INDIRECT_ACCESS_CNT_L_ADDR, &dataL); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8373_getAsicReg(RTL8373_INDIRECT_ACCESS_CNT_H_ADDR, &dataH); + if(retVal != RT_ERR_OK) + return retVal; + //printk("dataH 0x%x, dataL: 0x%x ", dataH, dataL); + if((mibid < 16) || ((mibid >91) && (mibid < 96)) || ((mibid >97) && (mibid < 102))) + *pMibCounter = ((rtk_uint64)dataL << 32) | dataH; + else if((mibid < 92) || ((mibid > 95) && (mibid < 98)) || ((mibid > 101) && (mibid < 104))) + { + if(mibid % 2) + *pMibCounter = dataH; + else + *pMibCounter = dataL; + } + + return RT_ERR_OK; +} + + + +/* Function Name: + * dal_rtl8373_mibLength_set + * Description: + * Set mib counter length include tag or not + * Input: + * txMode: tx include tag or not; rxMode: rx include tag or not + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t dal_rtl8373_mibLength_set(rtk_stat_lengthMode_t txMode, rtk_stat_lengthMode_t rxMode) +{ + ret_t retVal; + + retVal = rtl8373_setAsicRegBit(RTL8373_STAT_CTRL_ADDR, RTL8373_STAT_CTRL_TX_CNT_TAG_OFFSET,txMode); + + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8373_setAsicRegBit(RTL8373_STAT_CTRL_ADDR, RTL8373_STAT_CTRL_RX_CNT_TAG_OFFSET,rxMode); + + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_mibLength_get + * Description: + * Get mib counter length include tag or not + * Input: + * txMode: tx include tag or not; rxMode: rx include tag or not + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t dal_rtl8373_mibLength_get(rtk_stat_lengthMode_t* pTxMode, rtk_stat_lengthMode_t* pRxMode) +{ + ret_t retVal; + + retVal = rtl8373_getAsicRegBit(RTL8373_STAT_CTRL_ADDR, RTL8373_STAT_CTRL_TX_CNT_TAG_OFFSET,pTxMode); + + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8373_getAsicRegBit(RTL8373_STAT_CTRL_ADDR, RTL8373_STAT_CTRL_RX_CNT_TAG_OFFSET,pRxMode); + + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + + + + + + + diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_mib.h b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_mib.h new file mode 100755 index 00000000..6c0677dd --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_mib.h @@ -0,0 +1,119 @@ +#ifndef __DAL_RTL8373_MIB_H__ +#define __DAL_RTL8373_MIB_H__ + +#include + + + + +#define RTL8373_PORT_MIB_NUMBER 104 + + +/* Function Name: + * dal_rtl8373_globalMib_rst + * Description: + * global mib reset + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +extern ret_t dal_rtl8373_globalMib_rst(void); + + +/* Function Name: + * dal_rtl8373_portMib_rst + * Description: + * port mib reset + * Input: + * port: the port to reset mib + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +extern ret_t dal_rtl8373_portMib_rst(rtk_uint32 port); + + +/* Function Name: + * dal_rtl8373_dbgMib_rst + * Description: + * debug mib reset + * Input: + * port: the port to reset mib + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +extern ret_t dal_rtl8373_dbgMib_rst(rtk_uint32 port); + + + + +/* Function Name: + * dal_rtl8373_dbgMib_rst + * Description: + * debug mib reset + * Input: + * port: the port to reset mib + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +extern ret_t dal_rtl8373_portMib_read(rtk_uint32 portid, rtk_stat_port_type_t mibid, rtk_uint64 * pMibCounter); + + +/* Function Name: + * dal_rtl8373_mibLength_set + * Description: + * Set mib counter length include tag or not + * Input: + * txMode: tx include tag or not; rxMode: rx include tag or not + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +extern ret_t dal_rtl8373_mibLength_set(rtk_stat_lengthMode_t txMode, rtk_stat_lengthMode_t rxMode); + + +/* Function Name: + * dal_rtl8373_mibLength_get + * Description: + * Get mib counter length include tag or not + * Input: + * txMode: tx include tag or not; rxMode: rx include tag or not + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +extern ret_t dal_rtl8373_mibLength_get(rtk_stat_lengthMode_t* pTxMode, rtk_stat_lengthMode_t* pRxMode); + + + + +#endif + diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_mirror.c b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_mirror.c new file mode 100755 index 00000000..bb248708 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_mirror.c @@ -0,0 +1,994 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8373 + * Feature : Here is a list of all functions and variables in Mirror module. + * + */ + +#include +#include +#include +#include + +/* Function Name: + * dal_rtl8373_mirror_set_en + * Description: + * enable/disable port mirror function. + * Input: + * enable - + * Output: + * None + * Return: + * RT_ERR_OK - OK + * Note: + * The API is to enable/disable mirror function + */ +rtk_api_ret_t dal_rtl8373_mirror_set_en(rtk_enable_t enable) +{ + rtk_api_ret_t retVal = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(enable > RTK_ENABLE_END) + return RT_ERR_INPUT; + + retVal = rtl8373_setAsicRegBit(RTL8373_MIR_SET_CTRL_ADDR, RTL8373_MIR_SET_CTRL_MIR_EN_OFFSET, (rtk_uint32)enable); + if( retVal != RT_ERR_OK ) + return retVal; + + return RT_ERR_OK ; +} + +/* Function Name: + * dal_rtl8373_mirror_setStatus_get + * Description: + * get port mirror function state. + * Input: + * enable - + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_NULL_POINTER - + * Note: + * The API is to get mirror function state + */ +rtk_api_ret_t dal_rtl8373_mirror_setStatus_get(rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal = 0; + rtk_uint32 regData = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pEnable) + return RT_ERR_NULL_POINTER; + + retVal = rtl8373_getAsicRegBit(RTL8373_MIR_SET_CTRL_ADDR, RTL8373_MIR_SET_CTRL_MIR_EN_OFFSET, ®Data); + if( retVal != RT_ERR_OK ) + return retVal; + *pEnable = (rtk_enable_t)regData; + + return RT_ERR_OK ; +} + +/* Function Name: + * dal_rtl8373_mirror_portBased_set + * Description: + * Set port mirror function. + * Input: + * mirroring_port - Monitor port. + * pMirrored_rx_portmask - Rx mirror port mask. + * pMirrored_tx_portmask - Tx mirror port mask. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * RT_ERR_PORT_MASK - Invalid portmask. + * Note: + * The API is to set mirror function of source port and mirror port. + * The mirror port can only be set to one port and the TX and RX mirror ports + * should be identical. + */ +rtk_api_ret_t dal_rtl8373_mirror_entry_set(rtk_port_mir_set_t *pMirSet) +{ + rtk_api_ret_t retVal = 0; + rtk_uint16 tmp = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pMirSet) + return RT_ERR_NULL_POINTER; + + if( (pMirSet->rx_tx_sel) >= MIRROR_DIR_END ) + return RT_ERR_INPUT; + + /* Check port valid */ + RTK_CHK_PORTMASK_VALID(&pMirSet->tx_pmsk); + RTK_CHK_PORTMASK_VALID(&pMirSet->rx_pmsk); + RTK_CHK_PORT_VALID(pMirSet->mtp_port); + + /*Check mirrored port not include mtp port*/ + tmp = 1<<(pMirSet->mtp_port); + + if( (tmp & pMirSet->rx_pmsk.bits[0]) || (tmp & pMirSet->tx_pmsk.bits[0]) ) + return RT_ERR_INPUT; + + retVal = rtl8373_setAsicRegBits(RTL8373_MIR_SET_CTRL_ADDR, RTL8373_MIR_SET_CTRL_MTP_PORT_MASK, pMirSet->mtp_port); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8373_setAsicRegBits(RTL8373_MIR_SET_PMSK_ADDR, RTL8373_MIR_SET_PMSK_RX_PMSK_MASK, pMirSet->rx_pmsk.bits[0]); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8373_setAsicRegBits(RTL8373_MIR_SET_PMSK_ADDR, RTL8373_MIR_SET_PMSK_TX_PMSK_MASK, pMirSet->tx_pmsk.bits[0]); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8373_setAsicRegBit(RTL8373_MIR_SET_CTRL_ADDR, RTL8373_MIR_SET_CTRL_MIR_RX_TX_SEL_OFFSET, (rtk_uint32)pMirSet->rx_tx_sel); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_mirror_portBased_get + * Description: + * Get port mirror function. + * Input: + * None + * Output: + * pMirroring_port - Monitor port. + * pMirrored_rx_portmask - Rx mirror port mask. + * pMirrored_tx_portmask - Tx mirror port mask. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API is to get mirror function of source port and mirror port. + */ +rtk_api_ret_t dal_rtl8373_mirror_entry_get(rtk_port_mir_set_t *pMirSet) +{ + rtk_api_ret_t retVal = 0; + rtk_uint32 txRxSel = 0; + rtk_uint32 regData = 0; + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pMirSet) + return RT_ERR_NULL_POINTER; + /* Get source portmask */ + if((retVal = rtl8373_getAsicRegBits(RTL8373_MIR_SET_PMSK_ADDR, RTL8373_MIR_SET_PMSK_TX_PMSK_MASK , ®Data)) != RT_ERR_OK) + return retVal; + pMirSet->tx_pmsk.bits[0] = regData; + + if((retVal = rtl8373_getAsicRegBits(RTL8373_MIR_SET_PMSK_ADDR, RTL8373_MIR_SET_PMSK_RX_PMSK_MASK, ®Data)) != RT_ERR_OK) + return retVal; + pMirSet->rx_pmsk.bits[0] = regData; + + if((retVal = rtl8373_getAsicRegBit(RTL8373_MIR_SET_CTRL_ADDR, RTL8373_MIR_SET_CTRL_MIR_RX_TX_SEL_OFFSET, &txRxSel)) != RT_ERR_OK) + return retVal; + + /* Get monitor(destination) port */ + if((retVal = rtl8373_getAsicRegBits(RTL8373_MIR_SET_CTRL_ADDR, RTL8373_MIR_SET_CTRL_MTP_PORT_MASK, ®Data)) != RT_ERR_OK) + return retVal; + + pMirSet->mtp_port = regData; + + pMirSet->rx_tx_sel = (rtk_mirror_direction_t)(txRxSel) ; + return RT_ERR_OK; + +} + +/* Function Name: + * dal_rtl8373_mirror_portIso_set + * Description: + * Set mirror port isolation. + * Input: + * enable |Mirror isolation status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid enable input + * Note: + * The API is to set mirror isolation function that prevent normal forwarding packets to miror port. + */ +rtk_api_ret_t dal_rtl8373_mirror_portIso_set(rtk_enable_t enable) +{ + rtk_api_ret_t retVal = 0; + rtk_uint32 isoEn = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (enable >= RTK_ENABLE_END) + return RT_ERR_ENABLE; + + isoEn = (enable == ENABLED) ? 1 : 0; + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MIR_SET_CTRL_ADDR, RTL8373_MIR_SET_CTRL_MIR_ISO_OFFSET, isoEn)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_mirror_portIso_get + * Description: + * Get mirror port isolation. + * Input: + * None + * Output: + * pEnable |Mirror isolation status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API is to get mirror isolation status. + */ +rtk_api_ret_t dal_rtl8373_mirror_portIso_get(rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal = 0; + rtk_uint32 isoEn = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pEnable) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8373_getAsicRegBit(RTL8373_MIR_SET_CTRL_ADDR, RTL8373_MIR_SET_CTRL_MIR_ISO_OFFSET, &isoEn)) != RT_ERR_OK) + return retVal; + + *pEnable = (isoEn == 1) ? ENABLED : DISABLED; + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_mirror_vlanLeaky_set + * Description: + * Set mirror VLAN leaky. + * Input: + * txenable -TX leaky enable. + * rxenable - RX leaky enable. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid enable input + * Note: + * The API is to set mirror VLAN leaky function forwarding packets to miror port. + */ +rtk_api_ret_t dal_rtl8373_mirror_vlanLeaky_set(rtk_enable_t txenable, rtk_enable_t rxenable) +{ + rtk_api_ret_t retVal = 0; + rtk_uint32 txEn = 0, rxEn = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if ((txenable >= RTK_ENABLE_END) ||(rxenable >= RTK_ENABLE_END)) + return RT_ERR_ENABLE; + + txEn = (txenable == ENABLED) ? 1 : 0; + rxEn = (rxenable == ENABLED) ? 1 : 0; + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MIR_CTRL_ADDR, RTL8373_MIR_CTRL_MIR_TX_VLAN_LKY_OFFSET, txEn)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MIR_CTRL_ADDR, RTL8373_MIR_CTRL_MIR_RX_VLAN_LKY_OFFSET, rxEn)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_mirror_vlanLeaky_get + * Description: + * Get mirror VLAN leaky. + * Input: + * None + * Output: + * pTxenable - TX leaky enable. + * pRxenable - RX leaky enable. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API is to get mirror VLAN leaky status. + */ +rtk_api_ret_t dal_rtl8373_mirror_vlanLeaky_get(rtk_enable_t *pTxenable, rtk_enable_t *pRxenable) +{ + rtk_api_ret_t retVal = 0; + rtk_uint32 txEn = 0, rxEn = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if( (NULL == pTxenable) || (NULL == pRxenable) ) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8373_getAsicRegBit(RTL8373_MIR_CTRL_ADDR, RTL8373_MIR_CTRL_MIR_TX_VLAN_LKY_OFFSET, &txEn)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_getAsicRegBit(RTL8373_MIR_CTRL_ADDR, RTL8373_MIR_CTRL_MIR_RX_VLAN_LKY_OFFSET, &rxEn)) != RT_ERR_OK) + return retVal; + + *pTxenable = (txEn == 1) ? ENABLED : DISABLED; + *pRxenable = (rxEn == 1) ? ENABLED : DISABLED; + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_mirror_isolationLeaky_set + * Description: + * Set mirror Isolation leaky. + * Input: + * txenable -TX leaky enable. + * rxenable - RX leaky enable. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid enable input + * Note: + * The API is to set mirror PORT ISOLATION leaky function forwarding packets to miror port. + */ +rtk_api_ret_t dal_rtl8373_mirror_isolationLeaky_set(rtk_enable_t txenable, rtk_enable_t rxenable) +{ + rtk_api_ret_t retVal = 0; + rtk_uint32 txEn = 0, rxEn = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if ((txenable >= RTK_ENABLE_END) ||(rxenable >= RTK_ENABLE_END)) + return RT_ERR_ENABLE; + + txEn = (txenable == ENABLED) ? 1 : 0; + rxEn = (rxenable == ENABLED) ? 1 : 0; + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MIR_CTRL_ADDR, RTL8373_MIR_CTRL_MIR_TX_ISOLATE_LKY_OFFSET, txEn)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MIR_CTRL_ADDR, RTL8373_MIR_CTRL_MIR_RX_ISOLATE_LKY_OFFSET, rxEn)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_mirror_isolationLeaky_get + * Description: + * Get mirror isolation leaky. + * Input: + * None + * Output: + * pTxenable - TX leaky enable. + * pRxenable - RX leaky enable. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API is to get mirror isolation leaky status. + */ +rtk_api_ret_t dal_rtl8373_mirror_isolationLeaky_get(rtk_enable_t *pTxenable, rtk_enable_t *pRxenable) +{ + rtk_api_ret_t retVal = 0; + rtk_uint32 txEn = 0, rxEn = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if( (NULL == pTxenable) || (NULL == pRxenable) ) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8373_getAsicRegBit(RTL8373_MIR_CTRL_ADDR, RTL8373_MIR_CTRL_MIR_TX_ISOLATE_LKY_OFFSET, &txEn)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_getAsicRegBit(RTL8373_MIR_CTRL_ADDR, RTL8373_MIR_CTRL_MIR_RX_ISOLATE_LKY_OFFSET, &rxEn)) != RT_ERR_OK) + return retVal; + + *pTxenable = (txEn == 1) ? ENABLED : DISABLED; + *pRxenable = (rxEn == 1) ? ENABLED : DISABLED; + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_mirror_keep_set + * Description: + * Set mirror packet format keep. + * Input: + * mode - -mirror keep mode. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid enable input + * Note: + * The API is to set -mirror keep mode. + * The mirror keep mode is as following: + * - MIRROR_FOLLOW_VLAN + * - MIRROR_KEEP_ORIGINAL + * - MIRROR_KEEP_END + */ +rtk_api_ret_t dal_rtl8373_mirror_keep_set(rtk_mirror_keep_t mode) +{ + rtk_api_ret_t retVal = 0; + rtk_uint32 keepMode = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (mode >= MIRROR_KEEP_END) + return RT_ERR_ENABLE; + + keepMode = (mode == MIRROR_FOLLOW_VLAN) ? 0 : 1; + if ((retVal = rtl8373_setAsicRegBit(RTL8373_MIR_CTRL_ADDR, RTL8373_MIR_CTRL_MIR_REALKEEP_EN_OFFSET, keepMode)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_mirror_keep_get + * Description: + * Get mirror packet format keep. + * Input: + * None + * Output: + * pMode -mirror keep mode. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API is to get mirror keep mode. + * The mirror keep mode is as following: + * - MIRROR_FOLLOW_VLAN + * - MIRROR_KEEP_ORIGINAL + * - MIRROR_KEEP_END + */ +rtk_api_ret_t dal_rtl8373_mirror_keep_get(rtk_mirror_keep_t *pMode) +{ + rtk_api_ret_t retVal = 0; + rtk_uint32 keepMode = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pMode) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8373_getAsicRegBit(RTL8373_MIR_CTRL_ADDR, RTL8373_MIR_CTRL_MIR_REALKEEP_EN_OFFSET, &keepMode)) != RT_ERR_OK) + return retVal; + + *pMode = (keepMode == 0) ? MIRROR_FOLLOW_VLAN : MIRROR_KEEP_ORIGINAL; + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_mirror_override_set + * Description: + * Set port mirror override function. + * Input: + * rxMirror - 1: output mirrored packet, 0: output normal forward packet + * txMirror - 1: output mirrored packet, 0: output normal forward packet + * aclMirror - 1: output mirrored packet, 0: output normal forward packet + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API is to set mirror override function. + * This function control the output format when a port output + * normal forward & mirrored packet at the same time. + */ +rtk_api_ret_t dal_rtl8373_mirror_override_set(rtk_enable_t rxMirror, rtk_enable_t txMirror, rtk_enable_t aclMirror) +{ + rtk_api_ret_t retVal = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if( (rxMirror >= RTK_ENABLE_END) || (txMirror >= RTK_ENABLE_END) || (aclMirror >= RTK_ENABLE_END)) + return RT_ERR_NULL_POINTER; + + if((retVal = rtl8373_setAsicRegBit(RTL8373_MIR_CTRL_ADDR, RTL8373_MIR_CTRL_MIRROR_RX_OVERRIDE_EN_OFFSET, (rxMirror == ENABLED) ? 1 : 0)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8373_setAsicRegBit(RTL8373_MIR_CTRL_ADDR, RTL8373_MIR_CTRL_MIRROR_TX_OVERRIDE_EN_OFFSET, (txMirror == ENABLED) ? 1 : 0)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8373_setAsicRegBit(RTL8373_MIR_CTRL_ADDR, RTL8373_MIR_CTRL_MIRROR_ACL_OVERRIDE_EN_OFFSET, (aclMirror == ENABLED) ? 1 : 0)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_mirror_override_get + * Description: + * Get port mirror override function. + * Input: + * None + * Output: + * pRxMirror - 1: output mirrored packet, 0: output normal forward packet + * pTxMirror - 1: output mirrored packet, 0: output normal forward packet + * pAclMirror - 1: output mirrored packet, 0: output normal forward packet + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Null Pointer + * Note: + * The API is to Get mirror override function. + * This function control the output format when a port output + * normal forward & mirrored packet at the same time. + */ +rtk_api_ret_t dal_rtl8373_mirror_override_get(rtk_enable_t *pRxMirror, rtk_enable_t *pTxMirror, rtk_enable_t *pAclMirror) +{ + rtk_api_ret_t retVal = 0; + rtk_uint32 txEn = 0, rxEn = 0, aclEn = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if( (pRxMirror == NULL) || (pTxMirror == NULL) || (pAclMirror == NULL)) + return RT_ERR_NULL_POINTER; + + if((retVal = rtl8373_getAsicRegBit(RTL8373_MIR_CTRL_ADDR, RTL8373_MIR_CTRL_MIRROR_RX_OVERRIDE_EN_OFFSET, &rxEn)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8373_getAsicRegBit(RTL8373_MIR_CTRL_ADDR, RTL8373_MIR_CTRL_MIRROR_TX_OVERRIDE_EN_OFFSET, &txEn)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8373_getAsicRegBit(RTL8373_MIR_CTRL_ADDR, RTL8373_MIR_CTRL_MIRROR_ACL_OVERRIDE_EN_OFFSET, &aclEn)) != RT_ERR_OK) + return retVal; + + *pRxMirror = (rxEn == 1) ? ENABLED : DISABLED; + *pTxMirror = (txEn == 1) ? ENABLED : DISABLED; + *pAclMirror = (aclEn == 1) ? ENABLED : DISABLED; + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_mirror_sampeRate_set + * Description: + * set port mirror sample rate. + * Input: + * rateVal - + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Null Pointer + * Note: + * The API is to Set mirror sample rate. + */ +rtk_api_ret_t dal_rtl8373_mirror_sampeRate_set(rtk_uint32 rateVal) +{ + rtk_api_ret_t retVal = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(rateVal > MIR_SAMPLE_RATE_MAX) + return RT_ERR_INPUT; + + if((retVal = rtl8373_setAsicRegBits(RTL8373_MIR_SAMPLE_CRTL_ADDR, RTL8373_MIR_SAMPLE_CRTL_RATE_MASK, rateVal) != RT_ERR_OK)) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_mirror_sampeRate_get + * Description: + * get port mirror sample rate. + * Input: + * None - + * Output: + * pRateVal - sample rate value + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Null Pointer + * Note: + * The API is to Set mirror sample rate. + */ +rtk_api_ret_t dal_rtl8373_mirror_sampeRate_get(rtk_uint32 *pRateVal) +{ + rtk_api_ret_t retVal = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if( pRateVal == NULL) + return RT_ERR_NULL_POINTER; + + if((retVal = rtl8373_getAsicRegBits(RTL8373_MIR_SAMPLE_CRTL_ADDR, RTL8373_MIR_SAMPLE_CRTL_RATE_MASK, pRateVal) != RT_ERR_OK)) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_mirror_samplePktCnt_get + * Description: + * get Total counter for mirror condition satisfied packets + * Input: + * None - + * Output: + * pCntr -Total counter for mirror condition satisfied packets + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Null Pointer + * Note: + * The API is to get Total counter for mirror condition satisfied packets + */ +rtk_api_ret_t dal_rtl8373_mirror_pktCnt_get(rtk_uint32 *pCntr) +{ + rtk_api_ret_t retVal = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if( pCntr == NULL) + return RT_ERR_NULL_POINTER; + + if((retVal = rtl8373_getAsicRegBits(RTL8373_MIR_MATCHED_ADDR, RTL8373_MIR_MATCHED_PKT_CNT_MASK, pCntr) != RT_ERR_OK)) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_mirror_samplePktCnt_get + * Description: + * get Total sample counter for traffic mirror + * Input: + * None - + * Output: + * pCntr - Total sample counter for traffic mirror + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Null Pointer + * Note: + * The API is to get Total sample counter for traffic mirror + */ +rtk_api_ret_t dal_rtl8373_mirror_samplePktCnt_get(rtk_uint32 *pCntr) +{ + rtk_api_ret_t retVal = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if( pCntr == NULL) + return RT_ERR_NULL_POINTER; + + if((retVal = rtl8373_getAsicRegBits(RTL8373_MIR_MATCHED_ADDR, RTL8373_MIR_MATCHED_SAMPLE_PKT_CNT_MASK, pCntr) != RT_ERR_OK)) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_rspan_rxTag_en + * Description: + * set rspan rx tag parser function enable/disable. + * Input: + * enable + * Output: + * None - . + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + */ +rtk_api_ret_t dal_rtl8373_rspan_rxTag_en(rtk_enable_t enable) +{ + rtk_api_ret_t retVal = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(enable > RTK_ENABLE_END) + return RT_ERR_INPUT; + + retVal = rtl8373_setAsicRegBit(RTL8373_MIR_RSPAN_CTRL_ADDR, RTL8373_MIR_RSPAN_CTRL_RX_TAG_EN_OFFSET, (rtk_uint32)enable); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_rspan_rxTagEnStatus_get + * Description: + * get rspan rx tag enable/disable status. + * Input: + * None + * Output: + * pEnable - + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + */ +rtk_api_ret_t dal_rtl8373_rspan_rxTagEnSts_get(rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal = 0; + rtk_uint32 regData = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pEnable) + return RT_ERR_NULL_POINTER; + + retVal = rtl8373_getAsicRegBit(RTL8373_MIR_RSPAN_CTRL_ADDR, RTL8373_MIR_RSPAN_CTRL_RX_TAG_EN_OFFSET, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + *pEnable = (rtk_enable_t )regData; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_rspan_tagContext_set + * Description: + * set rspan tag context:TPID PRI CFI VID . + * Input: + * pRspanTag - rspan tag context:TPID PRI CFI VID . + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + */ +rtk_api_ret_t dal_rtl8373_rspan_tagContext_set(rtk_rspan_tag_t *pRspanTag) +{ + rtk_api_ret_t retVal = 0; + rtk_uint32 regData = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pRspanTag) + return RT_ERR_NULL_POINTER; + + if (pRspanTag->tpid > RTK_MAX_NUM_OF_PROTO_TYPE) + return RT_ERR_INPUT; + + if (pRspanTag->vid > RTL8373_VIDMAX) + return RT_ERR_VLAN_VID; + + if (pRspanTag->pri > RTL8373_PRIMAX) + return RT_ERR_VLAN_PRIORITY; + + if (pRspanTag->cfi > RTK_ENABLE_END) + return RT_ERR_INPUT; + + regData = ((pRspanTag->tpid & 0xFFFF)<< RTL8373_MIR_RSPAN_TAG_CTRL_TPID_OFFSET) | \ + ((pRspanTag->pri & 0x7) << RTL8373_MIR_RSPAN_TAG_CTRL_PRI_OFFSET) | \ + ((pRspanTag->cfi & 0x1) << RTL8373_MIR_RSPAN_TAG_CTRL_CFI_OFFSET) | (pRspanTag->vid & 0xFFF); + + retVal = rtl8373_setAsicReg(RTL8373_MIR_RSPAN_TAG_CTRL_ADDR, regData); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; + } + +/* Function Name: + * dal_rtl8373_rspan_tagContext_get + * Description: + * get rspan tag context:TPID PRI CFI VID . + * Input: + * None + * Output: + * pRspanTag - rspan tag context:TPID PRI CFI VID . + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + */ +rtk_api_ret_t dal_rtl8373_rspan_tagContext_get(rtk_rspan_tag_t *pRspanTag) +{ + rtk_api_ret_t retVal = 0; + rtk_uint32 regData = 0; + + retVal = rtl8373_getAsicReg(RTL8373_MIR_RSPAN_TAG_CTRL_ADDR, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + pRspanTag->tpid = (regData >> RTL8373_MIR_RSPAN_TAG_CTRL_TPID_OFFSET) & RTK_MAX_NUM_OF_PROTO_TYPE ; + pRspanTag->pri = (regData >> RTL8373_MIR_RSPAN_TAG_CTRL_PRI_OFFSET) & RTL8373_PRIMAX ; + pRspanTag->cfi = (regData >> RTL8373_MIR_RSPAN_TAG_CTRL_CFI_OFFSET) & 0x1 ; + pRspanTag->vid = (regData >> RTL8373_MIR_RSPAN_TAG_CTRL_VID_OFFSET) & RTL8373_VIDMAX ; + + return RT_ERR_OK; +} + +/* +* Function Name: +* dal_rtl8373_rspan_tagAdd_set +* Description: +* enable port add rspan tag function +*Input: +* pmsk: port mask that tx pkt want add rspan tag +*Output: +* None +*Return: +* RT_ERR_OK - OK +* RT_ERR_FAILED - Failed +*Note: None +*/ +rtk_api_ret_t dal_rtl8373_rspan_tagAdd_set(rtk_portmask_t pmsk) +{ + rtk_api_ret_t retVal = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + RTK_CHK_PORTMASK_VALID(&pmsk); + + retVal = rtl8373_setAsicRegBits(RTL8373_MIR_RSPAN_TX_PORT_CTRL_ADDR, RTL8373_MIR_RSPAN_TX_PORT_CTRL_TAG_ADD_MASK, pmsk.bits[0]); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* +* Function Name: +* dal_rtl8373_rspan_tagAdd_get +* Description: +* enable port add rspan tag function +*Input: +* None +*Output: +* pPmskSts: per port add rspan tag status +*Return: +* RT_ERR_OK - OK +* RT_ERR_FAILED - Failed +*Note: None +*/ +rtk_api_ret_t dal_rtl8373_rspan_tagAdd_get(rtk_portmask_t *pPmskSts) +{ + rtk_api_ret_t retVal = 0; + rtk_uint32 regData = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pPmskSts) + return RT_ERR_NULL_POINTER; + + retVal = rtl8373_getAsicRegBits(RTL8373_MIR_RSPAN_TX_PORT_CTRL_ADDR, RTL8373_MIR_RSPAN_TX_PORT_CTRL_TAG_ADD_MASK, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + pPmskSts->bits[0] = regData; + + return RT_ERR_OK; +} + +/* +* Function Name: +* dal_rtl8373_rspan_tagRemove_set +* Description: +* set mtp port remove rspan tag function +*Input: +* enable: mtp port remove rspan tag function enable/disable +*Output: +* None +*Return: +* RT_ERR_OK - OK +* RT_ERR_FAILED - Failed +*Note: None +*/ +rtk_api_ret_t dal_rtl8373_rspan_tagRemove_set(rtk_enable_t enable) +{ + rtk_api_ret_t retVal = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(enable > RTK_ENABLE_END) + return RT_ERR_INPUT; + + retVal = rtl8373_setAsicRegBit(RTL8373_MIR_RSPAN_RX_ACT_ADDR, RTL8373_MIR_RSPAN_RX_ACT_TAG_RM_OFFSET, enable); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* +* Function Name: +* dal_rtl8373_rspan_tagRemove_get +* Description: +* get mtp port remove rspan tag status +*Input: +* None +*Output: +* pEnable - +*Return: +* RT_ERR_OK - OK +* RT_ERR_FAILED - Failed +*Note: None +*/ +rtk_api_ret_t dal_rtl8373_rspan_tagRemove_get(rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal = 0; + rtk_uint32 regData = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pEnable) + return RT_ERR_NULL_POINTER; + + retVal = rtl8373_getAsicRegBit(RTL8373_MIR_RSPAN_RX_ACT_ADDR, RTL8373_MIR_RSPAN_RX_ACT_TAG_RM_OFFSET, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + *pEnable = (rtk_enable_t )regData; + + return RT_ERR_OK; +} + diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_mirror.h b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_mirror.h new file mode 100755 index 00000000..3475bf93 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_mirror.h @@ -0,0 +1,499 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8373 switch high-level API + * + * Feature : The file includes Mirror module high-layer API defination + * + */ + +#ifndef __DAL_RTL8373_MIRROR_H__ +#define __DAL_RTL8373_MIRROR_H__ + +#include + +#define MIR_SAMPLE_RATE_MAX (0xFFFF) + +/* Function Name: + * dal_rtl8373_mirror_set_en + * Description: + * enable/disable port mirror function. + * Input: + * enable - + * Output: + * None + * Return: + * RT_ERR_OK - OK + * Note: + * The API is to enable/disable mirror function + */ +extern rtk_api_ret_t dal_rtl8373_mirror_set_en(rtk_enable_t enable); +/* Function Name: + * dal_rtl8373_mirror_setStatus_get + * Description: + * get port mirror function state. + * Input: + * enable - + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_NULL_POINTER - + * Note: + * The API is to get mirror function state + */ +extern rtk_api_ret_t dal_rtl8373_mirror_setStatus_get(rtk_enable_t *pEnable); + +/* Function Name: + * dal_rtl8373_mirror_portBased_set + * Description: + * Set port mirror function. + * Input: + * pMirSet - Mirror set related parameter:MTP port number, tx mirrored port, rx mirrored port, mirror direction. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * RT_ERR_PORT_MASK - Invalid portmask. + * Note: + * The API is to set mirror function of source port and mirror port. + * The mirror port can only be set to one port and the TX and RX mirror ports + * should be identical. + */ +extern rtk_api_ret_t dal_rtl8373_mirror_entry_set(rtk_port_mir_set_t *pMirSet); + +/* Function Name: + * dal_rtl8373_mirror_portBased_get + * Description: + * Get port mirror function. + * Input: + * None + * Output: + * pMirSet - Mirror set related parameter:MTP port number, tx mirrored port, rx mirrored port, mirror direction. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API is to get mirror function of source port and mirror port. + */ +extern rtk_api_ret_t dal_rtl8373_mirror_entry_get(rtk_port_mir_set_t *pMirSet); + +/* Function Name: + * dal_rtl8373_mirror_portIso_set + * Description: + * Set mirror port isolation. + * Input: + * enable |Mirror isolation status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid enable input + * Note: + * The API is to set mirror isolation function that prevent normal forwarding packets to miror port. + */ +extern rtk_api_ret_t dal_rtl8373_mirror_portIso_set(rtk_enable_t enable); + +/* Function Name: + * dal_rtl8373_mirror_portIso_get + * Description: + * Get mirror port isolation. + * Input: + * None + * Output: + * pEnable |Mirror isolation status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API is to get mirror isolation status. + */ +extern rtk_api_ret_t dal_rtl8373_mirror_portIso_get(rtk_enable_t *pEnable); + +/* Function Name: + * dal_rtl8373_mirror_vlanLeaky_set + * Description: + * Set mirror VLAN leaky. + * Input: + * txenable -TX leaky enable. + * rxenable - RX leaky enable. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid enable input + * Note: + * The API is to set mirror VLAN leaky function forwarding packets to miror port. + */ +extern rtk_api_ret_t dal_rtl8373_mirror_vlanLeaky_set(rtk_enable_t txenable, rtk_enable_t rxenable); + + +/* Function Name: + * dal_rtl8373_mirror_vlanLeaky_get + * Description: + * Get mirror VLAN leaky. + * Input: + * None + * Output: + * pTxenable - TX leaky enable. + * pRxenable - RX leaky enable. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API is to get mirror VLAN leaky status. + */ +extern rtk_api_ret_t dal_rtl8373_mirror_vlanLeaky_get(rtk_enable_t *pTxenable, rtk_enable_t *pRxenable); + +/* Function Name: + * dal_rtl8373_mirror_isolationLeaky_set + * Description: + * Set mirror Isolation leaky. + * Input: + * txenable -TX leaky enable. + * rxenable - RX leaky enable. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid enable input + * Note: + * The API is to set mirror VLAN leaky function forwarding packets to miror port. + */ +extern rtk_api_ret_t dal_rtl8373_mirror_isolationLeaky_set(rtk_enable_t txenable, rtk_enable_t rxenable); + +/* Function Name: + * dal_rtl8373_mirror_isolationLeaky_get + * Description: + * Get mirror isolation leaky. + * Input: + * None + * Output: + * pTxenable - TX leaky enable. + * pRxenable - RX leaky enable. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API is to get mirror isolation leaky status. + */ +extern rtk_api_ret_t dal_rtl8373_mirror_isolationLeaky_get(rtk_enable_t *pTxenable, rtk_enable_t *pRxenable); + +/* Function Name: + * dal_rtl8373_mirror_keep_set + * Description: + * Set mirror packet format keep. + * Input: + * mode - -mirror keep mode. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid enable input + * Note: + * The API is to set -mirror keep mode. + * The mirror keep mode is as following: + * - MIRROR_FOLLOW_VLAN + * - MIRROR_KEEP_ORIGINAL + * - MIRROR_KEEP_END + */ +extern rtk_api_ret_t dal_rtl8373_mirror_keep_set(rtk_mirror_keep_t mode); + + +/* Function Name: + * dal_rtl8373_mirror_keep_get + * Description: + * Get mirror packet format keep. + * Input: + * None + * Output: + * pMode -mirror keep mode. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API is to get mirror keep mode. + * The mirror keep mode is as following: + * - MIRROR_FOLLOW_VLAN + * - MIRROR_KEEP_ORIGINAL + * - MIRROR_KEEP_END + */ +extern rtk_api_ret_t dal_rtl8373_mirror_keep_get(rtk_mirror_keep_t *pMode); + +/* Function Name: + * dal_rtl8373_mirror_override_set + * Description: + * Set port mirror override function. + * Input: + * rxMirror - 1: output mirrored packet, 0: output normal forward packet + * txMirror - 1: output mirrored packet, 0: output normal forward packet + * aclMirror - 1: output mirrored packet, 0: output normal forward packet + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API is to set mirror override function. + * This function control the output format when a port output + * normal forward & mirrored packet at the same time. + */ +extern rtk_api_ret_t dal_rtl8373_mirror_override_set(rtk_enable_t rxMirror, rtk_enable_t txMirror, rtk_enable_t aclMirror); + +/* Function Name: + * dal_rtl8373_mirror_override_get + * Description: + * Get port mirror override function. + * Input: + * None + * Output: + * pRxMirror - 1: output mirrored packet, 0: output normal forward packet + * pTxMirror - 1: output mirrored packet, 0: output normal forward packet + * pAclMirror - 1: output mirrored packet, 0: output normal forward packet + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Null Pointer + * Note: + * The API is to Get mirror override function. + * This function control the output format when a port output + * normal forward & mirrored packet at the same time. + */ +extern rtk_api_ret_t dal_rtl8373_mirror_override_get(rtk_enable_t *pRxMirror, rtk_enable_t *pTxMirror, rtk_enable_t *pAclMirror); + +/* Function Name: + * dal_rtl8373_mirror_sampeRate_set + * Description: + * set port mirror sample rate. + * Input: + * rateVal - + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Null Pointer + * Note: + * The API is to Set mirror sample rate. + */ +extern rtk_api_ret_t dal_rtl8373_mirror_sampeRate_set(rtk_uint32 rateVal); + +/* Function Name: + * dal_rtl8373_mirror_sampeRate_get + * Description: + * get port mirror sample rate. + * Input: + * None - + * Output: + * pRateVal - sample rate value + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Null Pointer + * Note: + * The API is to Set mirror sample rate. + */ +extern rtk_api_ret_t dal_rtl8373_mirror_sampeRate_get(rtk_uint32 *pRateVal); + +/* Function Name: + * dal_rtl8373_mirror_samplePktCnt_get + * Description: + * get Total counter for mirror condition satisfied packets + * Input: + * None - + * Output: + * pCntr -Total counter for mirror condition satisfied packets + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Null Pointer + * Note: + * The API is to get Total counter for mirror condition satisfied packets + */ +extern rtk_api_ret_t dal_rtl8373_mirror_pktCnt_get(rtk_uint32 *pCntr); + +/* Function Name: + * dal_rtl8373_mirror_samplePktCnt_get + * Description: + * get Total sample counter for traffic mirror + * Input: + * None - + * Output: + * pCntr - Total sample counter for traffic mirror + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Null Pointer + * Note: + * The API is to get Total sample counter for traffic mirror + */ +extern rtk_api_ret_t dal_rtl8373_mirror_samplePktCnt_get(rtk_uint32 *pCntr); + +/* Function Name: + * rtk_rspan_rxTag_en + * Description: + * set rspan rx tag parser function enable/disable. + * Input: + * enable + * Output: + * None - . + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + */ +extern rtk_api_ret_t dal_rtl8373_rspan_rxTag_en(rtk_enable_t enable); + +/* Function Name: + * rtk_rspan_rxTagEnStatus_get + * Description: + * get rspan rx tag enable/disable status. + * Input: + * None + * Output: + * pEnable - + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + */ +extern rtk_api_ret_t dal_rtl8373_rspan_rxTagEnSts_get(rtk_enable_t *pEnable); + +/* Function Name: + * dal_rtl8373_rspan_tagContext_set + * Description: + * set rspan tag context:TPID PRI CFI VID . + * Input: + * pRspanTag - rspan tag context:TPID PRI CFI VID . + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + */ +extern rtk_api_ret_t dal_rtl8373_rspan_tagContext_set(rtk_rspan_tag_t *pRspanTag); + +/* Function Name: + * dal_rtl8373_rspan_tagContext_get + * Description: + * get rspan tag context:TPID PRI CFI VID . + * Input: + * None + * Output: + * pRspanTag - rspan tag context:TPID PRI CFI VID . + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + */ +extern rtk_api_ret_t dal_rtl8373_rspan_tagContext_get(rtk_rspan_tag_t *pRspanTag); +/* +* Function Name: +* dal_rtl8373_rspan_tagAdd_set +* Description: +* enable port add rspan tag function +*Input: +* pmsk: port mask that tx pkt want add rspan tag +*Output: +* None +*Return: +* RT_ERR_OK - OK +* RT_ERR_FAILED - Failed +*Note: None +*/ +extern rtk_api_ret_t dal_rtl8373_rspan_tagAdd_set(rtk_portmask_t pmsk); + +/* +* Function Name: +* dal_rtl8373_rspan_tagAdd_get +* Description: +* enable port add rspan tag function +*Input: +* None +*Output: +* pPmskSts +*Return: +* RT_ERR_OK - OK +* RT_ERR_FAILED - Failed +*Note: None +*/ +extern rtk_api_ret_t dal_rtl8373_rspan_tagAdd_get(rtk_portmask_t *pPmskSts); + +/* +* Function Name: +* dal_rtl8373_rspan_tagRemove_set +* Description: +* set mtp port remove rspan tag function +*Input: +* enable: mtp port remove rspan tag function enable/disable +*Output: +* None +*Return: +* RT_ERR_OK - OK +* RT_ERR_FAILED - Failed +*Note: None +*/ +extern rtk_api_ret_t dal_rtl8373_rspan_tagRemove_set(rtk_enable_t enable); + +/* +* Function Name: +* dal_rtl8373_rspan_tagRemove_get +* Description: +* get mtp port remove rspan tag status +*Input: +* None +*Output: +* pEnable - +*Return: +* RT_ERR_OK - OK +* RT_ERR_FAILED - Failed +*Note: None +*/ +extern rtk_api_ret_t dal_rtl8373_rspan_tagRemove_get(rtk_enable_t *pEnable); + +#endif /* __DAL_RTL8373_MIRROR_H__ */ + diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_nic.c b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_nic.c new file mode 100755 index 00000000..0aaebf8f --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_nic.c @@ -0,0 +1,1461 @@ +/******************************************************************************* +* Copyright (C), 2013, Realtek Semiconductor Corp. +* All Rights Reserved. +* +* This program is the proprietary software of Realtek Semiconductor +* Corporation and/or its licensors, and only be used, duplicated, +* modified or distributed under the authorized license from Realtek. +* +* ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER +* THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. +* +* File Name: +* Author : Cynthia_wang +* Version : +* Date : 2020-9-24 +* Purpose : RTL8373 switch low-level API for RTL8373 +* Feature : Here is a list of all functions and variables in NIC module +* Note: +*******************************************************************************/ + +#include +#include +#include +#include +#include + +/* Function Name: + * dal_rtl8373_nic_rst_set + * Description: + * NIC Reset, Write 1 will reset NIC, all the NIC registers and parameters will set to default. After the reset is finished, this bit will turn to 0. + * Input: + * enabled - + * Output: + * none + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI + * + * Note: + * + */ +ret_t dal_rtl8373_nic_rst_set(void) +{ + RTK_ERR_CHK(rtl8373_setAsicRegBit(RTL8373_RST_GLB_CTRL_0_ADDR, RTL8373_RST_GLB_CTRL_0_SW_NIC_RST_OFFSET, ENABLED)); + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_nic_txStopAddr_set + * Description: + * Set nic buffer total size (txstop boundary) + * Input: + * addr - address + * Output: + * none + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI + * + * Note: + * + */ +ret_t dal_rtl8373_nic_txStopAddr_set(rtk_uint32 addr) +{ + + if (addr > RTK_NIC_TXSTOP_MAX ) + return RT_ERR_ENABLE; + + RTK_ERR_CHK(rtl8373_setAsicRegBits(RTL8373_NIC_BUFFSIZE_CTRL_ADDR, RTL8373_NIC_BUFFSIZE_CTRL_TXSTOP_ADDR_MASK, addr)); + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_nic_txStopAddr_get + * Description: + * Get nic buffer total size (txstop boundary) + * Input: + * none + * Output: + * addr - address + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI + * RT_ERR_NULL_POINTER + * Note: + * + */ +ret_t dal_rtl8373_nic_txStopAddr_get(rtk_uint32 *pAddr) +{ + + if (NULL == pAddr) + return RT_ERR_NULL_POINTER; + + RTK_ERR_CHK(rtl8373_getAsicRegBits(RTL8373_NIC_BUFFSIZE_CTRL_ADDR, RTL8373_NIC_BUFFSIZE_CTRL_TXSTOP_ADDR_MASK, pAddr)); + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_nic_rxStopAddr_set + * Description: + * Set nic rx buffer size + * Input: + * addr - address + * Output: + * none + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI + * + * Note: + * + */ +ret_t dal_rtl8373_nic_rxStopAddr_set(rtk_uint32 addr) +{ + + if (addr > RTK_NIC_TXSTOP_MAX ) + return RT_ERR_INPUT; + + RTK_ERR_CHK(rtl8373_setAsicRegBits(RTL8373_NIC_RXBUFF_CTRL_ADDR, RTL8373_NIC_RXBUFF_CTRL_RXSTOP_ADDR_MASK, addr)); + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_nic_rxStopAddr_get + * Description: + * Set nic rx buffer size + * Input: + * none + * Output: + * addr - address + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI + * RT_ERR_NULL_POINTER + * Note: + * + */ +ret_t dal_rtl8373_nic_rxStopAddr_get(rtk_uint32 *pAddr) +{ + + if (NULL == pAddr) + return RT_ERR_NULL_POINTER; + + RTK_ERR_CHK(rtl8373_getAsicRegBits(RTL8373_NIC_RXBUFF_CTRL_ADDR, RTL8373_NIC_RXBUFF_CTRL_RXSTOP_ADDR_MASK, pAddr)); + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_nic_swRxCurPktAddr_get + * Description: + * Get nic rx buffer received pkt length + * Input: + * none + * Output: + * addr - address + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI + * RT_ERR_NULL_POINTER + * Note: + * + */ +ret_t dal_rtl8373_nic_swRxCurPktAddr_get(rtk_uint32 *pAddr) +{ + + if (NULL == pAddr) + return RT_ERR_NULL_POINTER; + + RTK_ERR_CHK(rtl8373_getAsicReg(RTL8373_NIC_RX_CURR_PKT_ADDR, pAddr)); + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_nic_rxReceivedPktLen_get + * Description: + * Get nic rx buffer received pkt length + * Input: + * none + * Output: + * pLength - + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI + * RT_ERR_NULL_POINTER + * Note: + * + */ +ret_t dal_rtl8373_nic_rxReceivedPktLen_get(rtk_uint32 *pLength) +{ + + if (NULL == pLength) + return RT_ERR_NULL_POINTER; + + RTK_ERR_CHK(rtl8373_getAsicReg(RTL8373_NIC_RX_BUFF_DATA_ADDR, pLength)); + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_nic_txAvailableSpace_get + * Description: + * Get nic tx available free space. + * Input: + * none + * Output: + * addr - address + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI + * RT_ERR_NULL_POINTER + * Note: + * + */ +ret_t dal_rtl8373_nic_txAvailSpace_get(rtk_uint32 *pLength) +{ + + if (NULL == pLength) + return RT_ERR_NULL_POINTER; + + RTK_ERR_CHK(rtl8373_getAsicReg(RTL8373_NIC_TX_BUFF_AVAIL_ADDR, pLength)); + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_nic_moduleEn_set + * Description: + * enable/disable nic mocule. + * Input: + * enabled - enable or disable + * Output: + * none + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI + * + * Note: + * + */ +ret_t dal_rtl8373_nic_moduleEn_set(rtk_enable_t enabled) +{ + if(enabled > RTK_ENABLE_END) + return RT_ERR_ENABLE; + + RTK_ERR_CHK(rtl8373_setAsicRegBit(RTL8373_DW8051_CFG_ADDR, RTL8373_DW8051_CFG_NIC_EN_OFFSET, (enabled ? 1: 0) )); + return RT_ERR_OK; + +} + +/* Function Name: + * dal_rtl8373_nic_moduleEn_get + * Description: + * Get nic mocule status. + * Input: + * none + * Output: + * pEnabled - enable/disable + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI + * + * Note: + * + */ +ret_t dal_rtl8373_nic_moduleEn_get(rtk_enable_t *pEnabled) +{ + rtk_uint32 regData = 0; + + if (NULL == pEnabled) + return RT_ERR_NULL_POINTER; + + RTK_ERR_CHK(rtl8373_getAsicRegBit(RTL8373_DW8051_CFG_ADDR, RTL8373_DW8051_CFG_NIC_EN_OFFSET, ®Data)); + + *pEnabled = (rtk_enable_t)regData; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_nic_rxEn_set + * Description: + * enable nic rx or not. + * Input: + * enabled - enable or disable - + * Output: + * none + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI + * + * Note: + * + */ +ret_t dal_rtl8373_nic_rxEn_set(rtk_enable_t enabled) +{ + if(enabled > RTK_ENABLE_END) + return RT_ERR_ENABLE; + + RTK_ERR_CHK(rtl8373_setAsicRegBit(RTL8373_NIC_RX_CTRL_ADDR, RTL8373_NIC_RX_CTRL_RX_EN_OFFSET, (enabled ? 1: 0) )); + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_nic_rxEn_get + * Description: + * get nic rx status. + * Input: + * none + * Output: + * pEnabled - enable or disable + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI + * + * Note: + * + */ +ret_t dal_rtl8373_nic_rxEn_get(rtk_enable_t *pEnabled) +{ + rtk_uint32 regData = 0; + + if (NULL == pEnabled) + return RT_ERR_NULL_POINTER; + + RTK_ERR_CHK(rtl8373_getAsicRegBit(RTL8373_NIC_RX_CTRL_ADDR, RTL8373_NIC_RX_CTRL_RX_EN_OFFSET, ®Data)); + + *pEnabled = (rtk_enable_t)regData; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_nic_rxRemoveCrc_set + * Description: + * enable rx remove crc or not. + * Input: + * enabled - enable or disable - + * Output: + * none + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI + * + * Note: + * + */ +ret_t dal_rtl8373_nic_rxRemoveCrc_set(rtk_enable_t enabled) +{ + if(enabled > RTK_ENABLE_END) + return RT_ERR_ENABLE; + + RTK_ERR_CHK(rtl8373_setAsicRegBit(RTL8373_NIC_RX_CTRL_ADDR, RTL8373_NIC_RX_CTRL_RMCRC_EN_OFFSET, (enabled ? 1 : 0))); + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_nic_rxRemoveCrc_get + * Description: + * get nic rx remove crc enable or not. + * Input: + * none + * Output: + * pEnabled - enable or disable + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI + * + * Note: + * + */ +ret_t dal_rtl8373_nic_rxRemoveCrc_get(rtk_enable_t *pEnabled) +{ + rtk_uint32 regData = 0; + + if (NULL == pEnabled) + return RT_ERR_NULL_POINTER; + + RTK_ERR_CHK(rtl8373_getAsicRegBit(RTL8373_NIC_RX_CTRL_ADDR, RTL8373_NIC_RX_CTRL_RMCRC_EN_OFFSET, ®Data)); + *pEnabled = (rtk_enable_t)regData; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_nic_rxPaddingEn_set + * Description: + * enable nic rx padding. + * Input: + * enabled - enable or disable - + * Output: + * none + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI + * + * Note: + * + */ +ret_t dal_rtl8373_nic_rxPaddingEn_set(rtk_enable_t enabled) +{ + if(enabled > RTK_ENABLE_END) + return RT_ERR_ENABLE; + + RTK_ERR_CHK(rtl8373_setAsicRegBit(RTL8373_NIC_RX_CTRL_ADDR, RTL8373_NIC_RX_CTRL_RXPAD_OFFSET, (enabled ? 1 : 0))); + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_nic_rxPaddingEn_get + * Description: + * get nic rx padding status. + * Input: + * none - + * Output: + * *pEnabled - enable or disable + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI + * + * Note: + * + */ +ret_t dal_rtl8373_nic_rxPaddingEn_get(rtk_enable_t *pEnabled) +{ + rtk_uint32 regData = 0; + + if (NULL == pEnabled) + return RT_ERR_NULL_POINTER; + + RTK_ERR_CHK(rtl8373_getAsicRegBit(RTL8373_NIC_RX_CTRL_ADDR, RTL8373_NIC_RX_CTRL_RXPAD_OFFSET, ®Data)); + *pEnabled = (rtk_enable_t)regData; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_nic_rxFreeSpaceThd_set + * Description: + * set nic rx buffer free space threshlod + * Input: + * val - free space threshlod value (uint:8Byte) - + * Output: + * none + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI + * + * Note: + * + */ +ret_t dal_rtl8373_nic_rxFreeSpaceThd_set(rtk_uint32 val) +{ + if(val > RTK_RXFST_WIDTH) + return RT_ERR_RANGE; + + RTK_ERR_CHK(rtl8373_setAsicRegBits(RTL8373_NIC_RX_CTRL_ADDR, RTL8373_NIC_RX_CTRL_RXFST_MASK, val)); + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_nic_rxFreeSpaceThd_get + * Description: + * Get nic rx buffer free space threshlod + * Input: + * none - + * Output: + * *pval - free space threshlod value (uint:8Byte) + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI + * + * Note: + * + */ +ret_t dal_rtl8373_nic_rxFreeSpaceThd_get(rtk_nic_RxMTU_t *pVal) +{ + rtk_uint32 regData = 0; + + if (NULL == pVal) + return RT_ERR_NULL_POINTER; + + RTK_ERR_CHK(rtl8373_getAsicRegBits(RTL8373_NIC_RX_CTRL_ADDR, RTL8373_NIC_RX_CTRL_RXFST_MASK, ®Data)); + + *pVal = (rtk_nic_RxMTU_t)regData; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_nic_rxCrcErrEn_set + * Description: + * To set rx crc error pkt recieve or drop. + * Input: + * enabled - enable or disable - + * Output: + * none + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI + * + * Note: + * + */ +ret_t dal_rtl8373_nic_rxCrcErrEn_set(rtk_enable_t enabled) +{ + if(enabled > RTK_ENABLE_END) + return RT_ERR_ENABLE; + + RTK_ERR_CHK(rtl8373_setAsicRegBit(RTL8373_NIC_RX_CTRL_ADDR, RTL8373_NIC_RX_CTRL_RCRCEPE_OFFSET, (enabled ? 1 : 0))); + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_nic_rxCrcErrEn_get + * Description: + * Get rx crc error pkt recieved or be drop. + * Input: + * none - + * Output: + * *pEnabled - enable recieve or not + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI + * + * Note: + * + */ +ret_t dal_rtl8373_nic_rxCrcErrEn_get(rtk_enable_t *pEnabled) +{ + rtk_uint32 regData = 0; + + if (NULL == pEnabled) + return RT_ERR_NULL_POINTER; + + RTK_ERR_CHK(rtl8373_getAsicRegBit(RTL8373_NIC_RX_CTRL_ADDR, RTL8373_NIC_RX_CTRL_RCRCEPE_OFFSET, ®Data)); + *pEnabled = (rtk_enable_t)regData; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_nic_rxL3CrcErrEn_set + * Description: + * enable rx l3 crc error pkt recieved or not. + * Input: + * enabled - enable or disable - + * Output: + * none + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI + * + * Note: + * + */ +ret_t dal_rtl8373_nic_rxL3CrcErrEn_set(rtk_enable_t enabled) +{ + if(enabled > RTK_ENABLE_END) + return RT_ERR_ENABLE; + + RTK_ERR_CHK(rtl8373_setAsicRegBit(RTL8373_NIC_RX_CTRL_ADDR, RTL8373_NIC_RX_CTRL_RL3CEPE_OFFSET, (enabled ? 1 : 0))); + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_nic_rxL3CrcErrEn_get + * Description: + * Get rx l3 crc error pkt recieved or be drop. + * Input: + * none - + * Output: + * *pEnabled - enable recieve or not + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI + * + * Note: + * + */ +ret_t dal_rtl8373_nic_rxL3CrcErrEn_get(rtk_enable_t *pEnabled) +{ + rtk_uint32 regData = 0; + + if (NULL == pEnabled) + return RT_ERR_NULL_POINTER; + + RTK_ERR_CHK(rtl8373_getAsicRegBit(RTL8373_NIC_RX_CTRL_ADDR, RTL8373_NIC_RX_CTRL_RL3CEPE_OFFSET, ®Data)); + *pEnabled = (rtk_enable_t)regData; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_nic_rxL4CrcErrEn_set + * Description: + * enable rx l4 crc error pkt recieved or not. + * Input: + * enabled - enable or disable - + * Output: + * none + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI + * + * Note: + * + */ +ret_t dal_rtl8373_nic_rxL4CrcErrEn_set(rtk_enable_t enabled) +{ + if(enabled > RTK_ENABLE_END) + return RT_ERR_ENABLE; + + RTK_ERR_CHK(rtl8373_setAsicRegBit(RTL8373_NIC_RX_CTRL_ADDR, RTL8373_NIC_RX_CTRL_RL4CEPE_OFFSET, (enabled ? 1 : 0))); + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_nic_rxL4CrcErrEn_get + * Description: + * Get rx l4 crc error pkt recieved or be drop. + * Input: + * none - + * Output: + * *pEnabled - enable recieve or not + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI + * + * Note: + * + */ +ret_t dal_rtl8373_nic_rxL4CrcErrEn_get(rtk_enable_t *pEnabled) +{ + rtk_uint32 regData = 0; + + if (NULL == pEnabled) + return RT_ERR_NULL_POINTER; + + RTK_ERR_CHK(rtl8373_getAsicRegBit(RTL8373_NIC_RX_CTRL_ADDR, RTL8373_NIC_RX_CTRL_RL4CEPE_OFFSET, ®Data)); + *pEnabled = (rtk_enable_t)regData; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_nic_rxArpEn_set + * Description: + * enable ARP pkt pass or not. + * Input: + * enabled - enable or disable - + * Output: + * none + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI + * + * Note: + * + */ +ret_t dal_rtl8373_nic_rxArpEn_set(rtk_enable_t enabled) +{ + if(enabled > RTK_ENABLE_END) + return RT_ERR_ENABLE; + + RTK_ERR_CHK(rtl8373_setAsicRegBit(RTL8373_NIC_RX_CTRL_ADDR, RTL8373_NIC_RX_CTRL_ARPPE_OFFSET, (enabled ? 1 : 0))); + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_nic_rxArpEn_get + * Description: + * Get ARP pkt pass or not config. + * Input: + * none - + * Output: + * *pEnabled - enable or disable + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI + * + * Note: + * + */ +ret_t dal_rtl8373_nic_rxArpEn_get(rtk_enable_t *pEnabled) +{ + rtk_uint32 regData = 0; + + if (NULL == pEnabled) + return RT_ERR_NULL_POINTER; + + RTK_ERR_CHK(rtl8373_getAsicRegBit(RTL8373_NIC_RX_CTRL_ADDR, RTL8373_NIC_RX_CTRL_ARPPE_OFFSET, ®Data)); + *pEnabled = (rtk_enable_t)regData; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_nic_rxAllPktEn_set + * Description: + * enable nic rx all pkt or not. + * Input: + * enabled - enable or disable - + * Output: + * none + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI + * + * Note: + * + */ +ret_t dal_rtl8373_nic_rxAllPktEn_set(rtk_enable_t enabled) +{ + if(enabled > RTK_ENABLE_END) + return RT_ERR_ENABLE; + + RTK_ERR_CHK(rtl8373_setAsicRegBit(RTL8373_NIC_RX_CTRL_ADDR, RTL8373_NIC_RX_CTRL_RXAPE_OFFSET, (enabled ? 1 : 0))); + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_nic_rxAllPktEn_get + * Description: + * get nic rx all pkt or not config. + * Input: + * none - + * Output: + * *pEnabled - enable or disable + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI + * + * Note: + * + */ +ret_t dal_rtl8373_nic_rxAllPktEn_get(rtk_enable_t *pEnabled) +{ + rtk_uint32 regData = 0; + + if (NULL == pEnabled) + return RT_ERR_NULL_POINTER; + + RTK_ERR_CHK(rtl8373_getAsicRegBit(RTL8373_NIC_RX_CTRL_ADDR, RTL8373_NIC_RX_CTRL_RXAPE_OFFSET, ®Data)); + *pEnabled = (rtk_enable_t)regData; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_nic_rxPhyPktSel_set + * Description: + * enable nic Receive Physical Address Packet Select or not. + * Input: + * enabled - enable or disable - + * Output: + * none + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI + * + * Note: + * + */ +ret_t dal_rtl8373_nic_rxPhyPktSel_set(rtk_nic_rxpps_t behavior) +{ + if(behavior >= NIC_RX_PPS_END) + return RT_ERR_RANGE; + + RTK_ERR_CHK(rtl8373_setAsicRegBits(RTL8373_NIC_RX_CTRL_ADDR, RTL8373_NIC_RX_CTRL_RXPPS_MASK, behavior)); + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_nic_rxPhyPktSel_get + * Description: + * Get nic Receive Physical Address Packet Select or not config. + * Input: + * none - + * Output: + * *pBehavior - enable or disable + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI + * + * Note: + * + */ +ret_t dal_rtl8373_nic_rxPhyPktSel_get(rtk_nic_rxpps_t *pBehavior) +{ + rtk_uint32 regData = 0; + + if (NULL == pBehavior) + return RT_ERR_NULL_POINTER; + + RTK_ERR_CHK(rtl8373_getAsicRegBits(RTL8373_NIC_RX_CTRL_ADDR, RTL8373_NIC_RX_CTRL_RXPPS_MASK, ®Data)); + *pBehavior = (rtk_nic_rxpps_t)regData; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_nic_rxMultiPktEn_set + * Description: + * enable nic Receive multicast packet or not. + * Input: + * enabled - enable or disable - + * Output: + * none + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI + * + * Note: + * + */ +ret_t dal_rtl8373_nic_rxMultiPktEn_set(rtk_enable_t enabled) +{ + if(enabled > RTK_ENABLE_END) + return RT_ERR_ENABLE; + + RTK_ERR_CHK(rtl8373_setAsicRegBit(RTL8373_NIC_RX_CTRL_ADDR, RTL8373_NIC_RX_CTRL_RXMPE_OFFSET, (enabled ? 1 : 0))); + + return RT_ERR_OK; +} + +ret_t dal_rtl8373_nic_rxMultiPktEn_get(rtk_enable_t *pEnabled) +{ + rtk_uint32 regData = 0; + + if (NULL == pEnabled) + return RT_ERR_NULL_POINTER; + + RTK_ERR_CHK(rtl8373_getAsicRegBit(RTL8373_NIC_RX_CTRL_ADDR, RTL8373_NIC_RX_CTRL_RXMPE_OFFSET, ®Data)); + *pEnabled = (rtk_enable_t)regData; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_nic_rxBcPktEn_set + * Description: + * enable nic Receive broadcast packet or not. + * Input: + * enabled - enable or disable - + * Output: + * none + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI + * + * Note: + * + */ +ret_t dal_rtl8373_nic_rxBcPktEn_set(rtk_enable_t enabled) +{ + if(enabled > RTK_ENABLE_END) + return RT_ERR_ENABLE; + + RTK_ERR_CHK(rtl8373_setAsicRegBit(RTL8373_NIC_RX_CTRL_ADDR, RTL8373_NIC_RX_CTRL_RXBPE_OFFSET, (enabled ? 1 : 0))); + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_nic_rxBcPktEn_get + * Description: + * Get nic Receive broadcast packet config. + * Input: + * none - + * Output: + * *pEnabled - enable or disable + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI + * + * Note: + * + */ +ret_t dal_rtl8373_nic_rxBcPktEn_get(rtk_enable_t *pEnabled) +{ + rtk_uint32 regData = 0; + + if (NULL == pEnabled) + return RT_ERR_NULL_POINTER; + + RTK_ERR_CHK(rtl8373_getAsicRegBit(RTL8373_NIC_RX_CTRL_ADDR, RTL8373_NIC_RX_CTRL_RXBPE_OFFSET, ®Data)); + *pEnabled = (rtk_enable_t)regData; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_nic_MultiHashFltrEn_set + * Description: + * enable nic Received Multicast Packets Hash Filtering or not. + * Input: + * enabled - enable or disable - + * Output: + * none + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI + * + * Note: + * + */ +ret_t dal_rtl8373_nic_mcHashFltrEn_set(rtk_enable_t enabled) +{ + if(enabled > RTK_ENABLE_END) + return RT_ERR_ENABLE; + + RTK_ERR_CHK(rtl8373_setAsicRegBit(RTL8373_NIC_RX_CTRL_ADDR, RTL8373_NIC_RX_CTRL_HFMPE_OFFSET, (enabled ? 1 : 0))); + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_nic_MultiHashFltrEn_get + * Description: + * get nic Received Multicast Packets Hash Filtering config. + * Input: + * none - + * Output: + * *pEnabled - enable or disable + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI + * + * Note: + * + */ +ret_t dal_rtl8373_nic_mcHashFltrEn_get(rtk_enable_t *pEnabled) +{ + rtk_uint32 regData = 0; + + if (NULL == pEnabled) + return RT_ERR_NULL_POINTER; + + RTK_ERR_CHK(rtl8373_getAsicRegBit(RTL8373_NIC_RX_CTRL_ADDR, RTL8373_NIC_RX_CTRL_HFMPE_OFFSET, ®Data)); + *pEnabled = (rtk_enable_t)regData; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_nic_PhyPktHashFltrEn_set + * Description: + * enable nic Received unicast Packets Hash Filtering or not. + * Input: + * enabled - enable or disable - + * Output: + * none + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI + * + * Note: + * + */ +ret_t dal_rtl8373_nic_phyPktHashFltrEn_set(rtk_enable_t enabled) +{ + if(enabled > RTK_ENABLE_END) + return RT_ERR_ENABLE; + + RTK_ERR_CHK(rtl8373_setAsicRegBit(RTL8373_NIC_RX_CTRL_ADDR, RTL8373_NIC_RX_CTRL_HFPPE_OFFSET, (enabled ? 1 : 0))); + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_nic_phyPktHashFltrEn_get + * Description: + * Get nic Received unicast Packets Hash Filtering config. + * Input: + * none - + * Output: + * *pEnabled - enable or disable + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI + * + * Note: + * + */ +ret_t dal_rtl8373_nic_phyPktHashFltrEn_get(rtk_enable_t *pEnabled) +{ + rtk_uint32 regData = 0; + + if (NULL == pEnabled) + return RT_ERR_NULL_POINTER; + + RTK_ERR_CHK(rtl8373_getAsicRegBit(RTL8373_NIC_RX_CTRL_ADDR, RTL8373_NIC_RX_CTRL_HFPPE_OFFSET, ®Data)); + *pEnabled = (rtk_enable_t)regData; + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_nic_phyPktHashTblVal_set + * Description: + * Set unicast Packets Hash table. + * Input: + * type - high 32 bits value / low 32 bits value + * val - value - + * Output: + * none + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI + * + * Note: + * + */ +ret_t dal_rtl8373_nic_phyPktHashTblVal_set(rtk_nic_hashValType_t type, rtk_uint32 val) +{ + rtk_uint32 regAddr = 0; + + if(type > NIC_HASH_VAL_HIGH_WORD) + return RT_ERR_INPUT; + + regAddr = RTL8373_NIC_UC_HASH_TBL_ADDR(0) + (type << 2) ; + RTK_ERR_CHK(rtl8373_setAsicReg(regAddr, val)); + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_nic_phyPktHashTblVal_get + * Description: + * Get unicast Packets Hash table. + * Input: + * type - high 32 bits value / low 32 bits value + * Output: + * *pVal - value + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI + * + * Note: + * + */ +ret_t dal_rtl8373_nic_phyPktHashTblVal_get(rtk_nic_hashValType_t type, rtk_uint32 *pVal) +{ + rtk_uint32 regAddr = 0; + + if(type > NIC_HASH_VAL_HIGH_WORD) + return RT_ERR_INPUT; + if (NULL == pVal) + return RT_ERR_NULL_POINTER; + + regAddr = RTL8373_NIC_UC_HASH_TBL_ADDR(0) + (type << 2) ; + RTK_ERR_CHK(rtl8373_getAsicReg(regAddr, pVal)); + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_nic_multiPktHashTblVal_set + * Description: + * Set multicast Packets Hash table. + * Input: + * type - high 32 bits value / low 32 bits value + * val - value - + * Output: + * none + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI + * + * Note: + * + */ +ret_t dal_rtl8373_nic_mcHashTblVal_set(rtk_nic_hashValType_t type, rtk_uint32 val) +{ + rtk_uint32 regAddr = 0; + + if(type > NIC_HASH_VAL_HIGH_WORD) + return RT_ERR_INPUT; + + regAddr = RTL8373_NIC_MC_HASH_TBL_ADDR(0) + (type << 2) ; + RTK_ERR_CHK(rtl8373_setAsicReg(regAddr, val)); + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_nic_mcHashTblVal_get + * Description: + * Get multicast Packets Hash table. + * Input: + * type - high 32 bits value / low 32 bits value + * Output: + * *pVal - value + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI + * + * Note: + * + */ +ret_t dal_rtl8373_nic_mcHashTblVal_get(rtk_nic_hashValType_t type, rtk_uint32 *pVal) +{ + rtk_uint32 regAddr = 0; + + if(type > NIC_HASH_VAL_HIGH_WORD) + return RT_ERR_INPUT; + if (NULL == pVal) + return RT_ERR_NULL_POINTER; + + regAddr = RTL8373_NIC_MC_HASH_TBL_ADDR(0) + (type << 2) ; + RTK_ERR_CHK(rtl8373_getAsicReg(regAddr, pVal)); + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_nic_rxMTU_set + * Description: + * set nic RXMTU. + * Input: + * length - max length nic could recieved - + * Output: + * none + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI + * + * Note: + * + */ +ret_t dal_rtl8373_nic_rxMTU_set(rtk_nic_RxMTU_t lenIdx) +{ + if(lenIdx > NIC_RX_MTU_END) + return RT_ERR_RANGE; + + RTK_ERR_CHK(rtl8373_setAsicRegBits(RTL8373_NIC_RX_CTRL_ADDR, RTL8373_NIC_RX_CTRL_RXMTU_MASK, lenIdx)); + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_nic_rxMTU_get + * Description: + * Get nic RXMTU. + * Input: + * none - + * Output: + * *pLenIdx - max length nic could recieved + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI + * + * Note: + * + */ +ret_t dal_rtl8373_nic_rxMTU_get(rtk_nic_RxMTU_t *pLenIdx) +{ + rtk_uint32 regData = 0; + + if (NULL == pLenIdx) + return RT_ERR_NULL_POINTER; + + RTK_ERR_CHK(rtl8373_getAsicRegBits(RTL8373_NIC_RX_CTRL_ADDR, RTL8373_NIC_RX_CTRL_RXMTU_MASK, ®Data)); + + *pLenIdx = (rtk_nic_RxMTU_t)regData; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_nic_txEn_set + * Description: + * enable nic tx ablity. + * Input: + * enabled - enable or disable - + * Output: + * none + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI + * + * Note: + * + */ +ret_t dal_rtl8373_nic_txEn_set(rtk_enable_t enabled) +{ + if(enabled > RTK_ENABLE_END) + return RT_ERR_ENABLE; + + RTK_ERR_CHK(rtl8373_setAsicRegBit(RTL8373_NIC_TX_CTRL_ADDR, RTL8373_NIC_TX_CTRL_TX_EN_OFFSET, (enabled ? 1 : 0 ))); + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_nic_txEn_get + * Description: + * Get nic tx ablity. + * Input: + * none - + * Output: + * *pEnabled - enable or disable + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI + * + * Note: + * + */ +ret_t dal_rtl8373_nic_txEn_get(rtk_enable_t *pEnabled) +{ + rtk_uint32 regData = 0; + + if (NULL == pEnabled) + return RT_ERR_NULL_POINTER; + + RTK_ERR_CHK(rtl8373_getAsicRegBit(RTL8373_NIC_TX_CTRL_ADDR, RTL8373_NIC_TX_CTRL_TX_EN_OFFSET, ®Data)); + *pEnabled = (rtk_enable_t)regData; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_nic_LoopbackEn_set + * Description: + * enable nic loopback ablity. + * Input: + * enabled - enable or disable - + * Output: + * none + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI + * + * Note: + * + */ +ret_t dal_rtl8373_nic_loopbackEn_set(rtk_enable_t enabled) +{ + if(enabled > RTK_ENABLE_END) + return RT_ERR_ENABLE; + + RTK_ERR_CHK(rtl8373_setAsicRegBit(RTL8373_NIC_TX_CTRL_ADDR, RTL8373_NIC_TX_CTRL_LOOPBACK_EN_OFFSET, (enabled ? 1 : 0 ))); + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_nic_LoopbackEn_get + * Description: + * Get nic loopback ablity. + * Input: + * none - + * Output: + * *pEnabled - enable or disable + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI + * + * Note: + * + */ +ret_t dal_rtl8373_nic_loopbackEn_get(rtk_enable_t *pEnabled) +{ + rtk_uint32 regData = 0; + + if (NULL == pEnabled) + return RT_ERR_NULL_POINTER; + + RTK_ERR_CHK(rtl8373_getAsicRegBit(RTL8373_NIC_TX_CTRL_ADDR, RTL8373_NIC_TX_CTRL_LOOPBACK_EN_OFFSET, ®Data)); + *pEnabled = (rtk_enable_t)regData; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_nic_interruptEn_set + * Description: + * enable nix rx pkt interrupt and nic tx error interrupt. + * Input: + * rxie - enable or disable nic rx pkt interrupt - + * txee - enable or disable nic tx error interrupt + * Output: + * none + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI + * + * Note: + * + */ +ret_t dal_rtl8373_nic_interruptEn_set(rtk_enable_t rxie, rtk_enable_t txee) +{ + rtk_uint32 mask = 0; + if((rxie > RTK_ENABLE_END) || (txee > RTK_ENABLE_END)) + return RT_ERR_ENABLE; + + mask = (rxie ? 1 : 0 ) << RTL8373_NIC_INT_MSK_RXIE_OFFSET; + mask |= (txee ? 1 : 0 ); + RTK_ERR_CHK(rtl8373_setAsicReg(RTL8373_NIC_INT_MSK_ADDR, mask)); + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_nic_interruptEn_get + * Description: + * Get nix rx pkt interrupt and nic tx error interrupt config . + * Input: + * none + * Output: + * *pRxie - nic rx pkt interrupt config:enable or disable - + * *pTxee - nic tx error interrupt config:enable or disable + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI + * + * Note: + * + */ +ret_t dal_rtl8373_nic_interruptEn_get(rtk_enable_t *pRxie, rtk_enable_t *pTxee) +{ + rtk_uint32 regData = 0; + + if ((NULL == pRxie) || (NULL == pTxee)) + return RT_ERR_NULL_POINTER; + + RTK_ERR_CHK(rtl8373_getAsicReg(RTL8373_NIC_INT_MSK_ADDR, ®Data)); + *pRxie = (rtk_enable_t)((regData >> RTL8373_NIC_INT_MSK_RXIE_OFFSET) & 1); + *pTxee = (rtk_enable_t)(regData & 1); + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_nic_interruptStatus_get + * Description: + * get nix rx pkt interrupt and nic tx error interrupt status . + * Input: + * none + * Output: + * *pRxis - nic rx pkt interrupt occured or not - + * *pTxes - nic tx error interrupt occured or not + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI + * + * Note: + * + */ +ret_t dal_rtl8373_nic_interruptStatus_get(rtk_uint32 *pRxis, rtk_uint32 *pTxes) +{ + rtk_uint32 regData = 0; + if (NULL == pRxis) + return RT_ERR_NULL_POINTER; + if (NULL == pTxes) + return RT_ERR_NULL_POINTER; + + RTK_ERR_CHK(rtl8373_getAsicReg(RTL8373_NIC_INT_STS_ADDR, ®Data)); + + *pRxis = (regData >> RTL8373_NIC_INT_STS_RXIS_OFFSET) & 1; + *pTxes = (regData & 1); + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_nic_interruptStatus_clear + * Description: + * clear nix rx pkt interrupt status and nic tx error interrupt status . + * Input: + * rxis - clear nic rx pkt interrupt status - + * txes - clear or disable nic tx error interrupt status + * Output: + * none + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI + * + * Note: + * + */ +ret_t dal_rtl8373_nic_interruptStatus_clear(rtk_uint32 rxis, rtk_uint32 txes) +{ + rtk_uint32 regData = 0; + if (rxis > 1) + return RT_ERR_INPUT; + if (txes > 1) + return RT_ERR_INPUT; + + regData = (rxis << RTL8373_NIC_INT_STS_RXIS_OFFSET) |txes; + RTK_ERR_CHK(rtl8373_setAsicReg(RTL8373_NIC_INT_STS_ADDR, regData)); + + return RT_ERR_OK; +} + diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_nic.h b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_nic.h new file mode 100755 index 00000000..14801ec1 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_nic.h @@ -0,0 +1,367 @@ +/******************************************************************************* +* Copyright (C), 2013, Realtek Semiconductor Corp. +* All Rights Reserved. +* +* This program is the proprietary software of Realtek Semiconductor +* Corporation and/or its licensors, and only be used, duplicated, +* modified or distributed under the authorized license from Realtek. +* +* ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER +* THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. +* +* File Name: +* Author : Cynthia_wang +* Version : +* Date : 2020-9-24 +* Purpose : RTL8373 switch low-level API for RTL8373 +* Feature : Here is a list of all functions and variables in NIC module +* Note: +*******************************************************************************/ + +#ifndef __DAL_RTL8373_NIC_H__ +#define __DAL_RTL8373_NIC_H__ + +#include + + +#define RXSTOP_NIC 0x1FF //it's 8 byte alignment. So the actual size is the number * 8 +#define TXSTOP_NIC 0x3FF + +/* Sometimes, cpu will append ITAG|OTAG|CPU in reply packet, + * This offset is the length of unused buffer space before received packet buffer. + * So that when the cpu appends ITAG|OTAG|CPU, the contents in the packet buffer + * don't need to move afterwards. + */ +#define CPU_TAG_LEN 8 +#define OTAG_LEN 4 +#define ITAG_LEN 4 +#define MEMCPY_RESERVE 1 // because Rx & Tx share the same buffer, to avoid copy same memory, 1 byte is reserved. +#define HEADER_EXTENSION_SIZE (ITAG_LEN + OTAG_LEN + CPU_TAG_LEN + MEMCPY_RESERVE) +#define MAX_PKT_PAYLOAD_LEN 1514 +#define FCS_LEN (12) + +#define MAX_PKT_LEN (MAX_PKT_PAYLOAD_LEN + FCS_LEN + OTAG_LEN + ITAG_LEN + CPU_TAG_LEN) +#define MIN_PKT_LEN (60 + CPU_TAG_LEN) + +#define PKT_BUFFER_SIZE (MAX_PKT_PAYLOAD_LEN + FCS_LEN + HEADER_EXTENSION_SIZE) + + +#define NIC_RXSTAT_RRCPCSER_OFFSET 26 +#define NIC_RXSTAT_RRCPCSER_MASK (0x1UL << NIC_RXSTAT_RRCPCSER_OFFSET) +#define NIC_RXSTAT_PRI_OFFSET 24 +#define NIC_RXSTAT_PRI_MASK (0x3UL << NIC_RXSTAT_PRI_OFFSET) +#define NIC_RXSTAT_CPUTAG_OFFSET 23 +#define NIC_RXSTAT_CPUTAG_MASK (0x1UL << NIC_RXSTAT_CPUTAG_OFFSET) +#define NIC_RXSTAT_FRAG_OFFSET 22 +#define NIC_RXSTAT_FRAG_MASK (0x1UL << NIC_RXSTAT_FRAG_OFFSET) +#define NIC_RXSTAT_PPPOE_OFFSET 22 +#define NIC_RXSTAT_PPPOE_MASK (0x1UL << NIC_RXSTAT_PPPOE_OFFSET) +#define NIC_RXSTAT_L34FMT_OFFSET 16 +#define NIC_RXSTAT_L34FMT_MASK (0xFUL << NIC_RXSTAT_L34FMT_OFFSET) +#define NIC_RXSTAT_ITAG_OFFSET 15 +#define NIC_RXSTAT_ITAG_MASK (0x1UL << NIC_RXSTAT_ITAG_OFFSET) +#define NIC_RXSTAT_OTAG_OFFSET 14 +#define NIC_RXSTAT_OTAG_MASK (0x1UL << NIC_RXSTAT_OTAG_OFFSET) +#define NIC_RXSTAT_L2FMT_OFFSET 12 +#define NIC_RXSTAT_L2FMT_MASK (0x3UL << NIC_RXSTAT_L2FMT_OFFSET) +#define NIC_RXSTAT_L4CSER_OFFSET 11 +#define NIC_RXSTAT_L4CSER_MASK (0x1UL << NIC_RXSTAT_L4CSER_OFFSET) +#define NIC_RXSTAT_L3CSER_OFFSET 10 +#define NIC_RXSTAT_L3CSER_MASK (0x1UL << NIC_RXSTAT_L3CSER_OFFSET) +#define NIC_RXSTAT_CRCER_OFFSET 9 +#define NIC_RXSTAT_CRCER_MASK (0x1UL << NIC_RXSTAT_CRCER_OFFSET) +#define NIC_RXSTAT_OVERSIZE_OFFSET 8 +#define NIC_RXSTAT_OVERSIZE_MASK (0x1UL << NIC_RXSTAT_OVERSIZE_OFFSET) +#define NIC_RXSTAT_PKTSN_OFFSET 0 +#define NIC_RXSTAT_PKTSN_MASK (0xFF << NIC_RXSTAT_PKTSN_OFFSET) + + +#define NIC_TXSTAT_RRCPSRE_OFFSET 11 +#define NIC_TXSTAT_RRCPSRE_MASK (0x1 << NIC_TXSTAT_RRCPSRE_OFFSET) +#define NIC_TXSTAT_L4CSRE_OFFSET 10 +#define NIC_TXSTAT_L4CSRE_MASK (0x1 << NIC_TXSTAT_L4CSRE_OFFSET) +#define NIC_TXSTAT_L3CSRE_OFFSET 9 +#define NIC_TXSTAT_L3CSRE_MASK (0x1 << NIC_TXSTAT_L3CSRE_OFFSET) +#define NIC_TXSTAT_CRCRE_OFFSET 8 +#define NIC_TXSTAT_CRCRE_MASK (0x1 << NIC_TXSTAT_CRCRE_OFFSET) +#define NIC_TXSTAT_PKTSN_OFFSET 0 +#define NIC_TXSTAT_PKTSN_MASK (0xFF << NIC_TXSTAT_PKTSN_OFFSET) + +#define L34FMT_UNKNOWN 0 +#define L34FMT_ARP 1 +#define L34FMT_ICMP 2 +#define L34FMT_IGMP 3 +#define L34FMT_TCP 4 +#define L34FMT_UDP 5 +#define L34FMT_IPV4 6 +#define L34FMT_ICMPV6 7 +#define L34FMT_TCPV6 8 +#define L34FMT_UDPV6 9 +#define L34FMT_IPV6 10 + +/* NIC initilization symbolic constant */ +#define SYS_IP0 192 +#define SYS_IP1 168 +#define SYS_IP2 0 +#define SYS_IP3 1 + +#define SYS_GATEWAY0 192 +#define SYS_GATEWAY1 168 +#define SYS_GATEWAY2 0 +#define SYS_GATEWAY3 254 +#define DEFAULT_GATEWAY SYS_GATEWAY0, SYS_GATEWAY1, SYS_GATEWAY2, SYS_GATEWAY3 + +#define SYS_NETMASK0 255 +#define SYS_NETMASK1 255 +#define SYS_NETMASK2 255 +#define SYS_NETMASK3 0 + +/*Memory Controller Reg*/ +#define CPU_REGBASE_ADDR 0x7F00 +#define CPU_CRSTR_ADDR (CPU_REGBASE_ADDR+0) +#define CPU_CMDTR_ADDR (CPU_REGBASE_ADDR+4) +#define CPU_DMAR_ADDR (CPU_REGBASE_ADDR+8) +#define CPU_SMAR_ADDR (CPU_REGBASE_ADDR+0xC) +#define CPU_DLR_ADDR (CPU_REGBASE_ADDR+0x10) +#define CPU_FPNUMR_ADDR (CPU_REGBASE_ADDR+0x14) +#define CPU_8051FRQ_ADDR (CPU_REGBASE_ADDR+0x18) +#define CPU_IMCR_ADDR (CPU_REGBASE_ADDR+0x1C) +#define CPU_IMDR0_ADDR (CPU_REGBASE_ADDR+0x20) +#define CPU_IMDR1_ADDR (CPU_REGBASE_ADDR+0x24) +#define CPU_SRAAR_ADDR (CPU_REGBASE_ADDR+0x28) +#define CPU_SRADR_ADDR (CPU_REGBASE_ADDR+0x2C) +#define CPU_SRACR_ADDR (CPU_REGBASE_ADDR+0x30) +#define CPU_ECS2R_ADDR (CPU_REGBASE_ADDR+0x40) + +/*NIC Reg*/ +#define NIC_REGBASE_ADDR 0x7F50 +#define NIC_GCR_ADDR (NIC_REGBASE_ADDR + 0) +#define NIC_TXSTOPR_ADDR (NIC_REGBASE_ADDR + 4) +#define NIC_RXSTOPR_ADDR (NIC_REGBASE_ADDR + 8) +#define NIC_RXRDLR_ADDR (NIC_REGBASE_ADDR + 0xC) +#define NIC_TXAFSR_ADDR (NIC_REGBASE_ADDR + 0x10) +#define NIC_RXCMDR_ADDR (NIC_REGBASE_ADDR + 0x14) +#define NIC_TXCMDR_ADDR (NIC_REGBASE_ADDR + 0x18) +#define NIC_ISR_ADDR (NIC_REGBASE_ADDR + 0x1C) +#define NIC_IMR_ADDR (NIC_REGBASE_ADDR + 0x20) +#define NIC_RXCTLR_ADDR (NIC_REGBASE_ADDR + 0x24) +#define NIC_TXCTLR_ADDR (NIC_REGBASE_ADDR + 0x28) +#define NIC_CRXCPR_ADDR (NIC_REGBASE_ADDR + 0x2C) +#define NIC_CTXCPR_ADDR (NIC_REGBASE_ADDR + 0x30) +#define NIC_MHR0_ADDR (NIC_REGBASE_ADDR + 0x34) +#define NIC_MHR1_ADDR (NIC_REGBASE_ADDR + 0x38) +#define NIC_MHR2_ADDR (NIC_REGBASE_ADDR + 0x3C) +#define NIC_MHR3_ADDR (NIC_REGBASE_ADDR + 0x40) +#define NIC_MHR4_ADDR (NIC_REGBASE_ADDR + 0x44) +#define NIC_MHR5_ADDR (NIC_REGBASE_ADDR + 0x48) +#define NIC_MHR6_ADDR (NIC_REGBASE_ADDR + 0x4C) +#define NIC_MHR7_ADDR (NIC_REGBASE_ADDR + 0x50) +#define NIC_PAHR0_ADDR (NIC_REGBASE_ADDR + 0x54) +#define NIC_PAHR1_ADDR (NIC_REGBASE_ADDR + 0x58) +#define NIC_PAHR2_ADDR (NIC_REGBASE_ADDR + 0x5C) +#define NIC_PAHR3_ADDR (NIC_REGBASE_ADDR + 0x60) +#define NIC_PAHR4_ADDR (NIC_REGBASE_ADDR + 0x64) +#define NIC_PAHR5_ADDR (NIC_REGBASE_ADDR + 0x68) +#define NIC_PAHR6_ADDR (NIC_REGBASE_ADDR + 0x6C) +#define NIC_PAHR7_ADDR (NIC_REGBASE_ADDR + 0x70) +#define NIC_SRXCURPKTR_ADDR (NIC_REGBASE_ADDR + 0x74) +#define NIC_STXCURPKTR_ADDR (NIC_REGBASE_ADDR + 0x78) +#define NIC_STXPktLENR_ADDR (NIC_REGBASE_ADDR + 0x7C) +#define NIC_STXCURUNITR_ADDR (NIC_REGBASE_ADDR + 0x80) + +#define CPU_CMDTR_CMDSTATUS_OFFSET 6 +#define CPU_CMDTR_CMDSTATUS_MASK (1 << CPU_CMDTR_CMDSTATUS_OFFSET) +#define CPU_CMDTR_CMPRESULT_OFFSET 5 +#define CPU_CMDTR_CMPRESULT_MASK (1 << CPU_CMDTR_CMPRESULT_OFFSET) +#define CPU_CMDTR_FMODE_OFFSET 4 +#define CPU_CMDTR_FMODE_MASK (1 << CPU_CMDTR_FMODE_OFFSET) +#define CPU_CMDTR_CMDTYPE_OFFSET 0 +#define CPU_CMDTR_CMDTYPE_MASK (0xF << CPU_CMDTR_FMODE_OFFSET) + +#define CPU_SRACR_TRIGGER_OFFSET 1 +#define CPU_SRACR_TRIGGER_MASK (1 << CPU_SRACR_TRIGGER_OFFSET) +#define CPU_SRACR_TYPE_OFFSET 1 +#define CPU_SRACR_TYPE_MASK (1 << CPU_SRACR_TYPE_OFFSET) +#define CPU_SRACR_TYPE_READ 0 +#define CPU_SRACR_TYPE_WRITE 1 + +#define PORT_ALL_MASK 0x1FFFFFF + + +/* Rx Status Word for NIC */ +typedef struct rx_stat_s +{ + rtk_uint8 rrcpcse; /* 1: rrcp checksum error; 0: no error*/ + rtk_uint8 rxPri; /* Rx packet priority */ + rtk_uint8 cputag; /* If the cpu tag exist or not*/ + rtk_uint8 fragment; /* The packet has fragment or not. 0: has no fragment; 1: has fragment */ + rtk_uint8 pppoe; /* Packet has PPPoE header. 0: is; 1: not */ + rtk_uint8 l34fmt; /* layer 3/4 format */ + rtk_uint8 iTagExist; + rtk_uint8 oTagExist; + rtk_uint8 l2fmt; /* layer 2 format */ + rtk_uint8 L4cse; /* ICMP/IGMP/TCP/UDP checksum error . 0: correct ; 1: error*/ + rtk_uint8 L3cse; /* IP Checksum Error. 0: correct ; 1: error*/ + rtk_uint8 crce; /* CRC Error. 0: correct ; 1: error*/ + rtk_uint8 oversize; + rtk_uint8 rxPktSn; /* Rx Packet Sequence Number */ + rtk_uint16 length; +}rx_stat_t; + +/* Tx Control Word for NIC*/ + +/* Rx CPU tag */ +typedef struct rx_cpuTag_s +{ + rtk_uint16 etherType; + rtk_uint8 protocol; + rtk_uint8 pri; + rtk_uint8 sphy; + rtk_uint16 vid; + rtk_uint8 pppoe; + rtk_uint8 l34fmt; + rtk_uint8 iTagExist; + rtk_uint8 oTagExist; + rtk_uint8 l2fmt; + rtk_uint8 aclOTagOp; + rtk_uint8 aclITagOp; + rtk_uint8 rsnValid; + rtk_uint8 reason; +}rx_cpuTag_t; + +/* Tx CPU tag */ +typedef struct tx_cpuTag_s +{ + rtk_uint16 etherType; + rtk_uint8 protocol; + rtk_uint8 dslrn; /*Disable SMAC learning*/ + rtk_uint8 pri; /*assigned priority*/ + rtk_uint8 normk; /*When NORMK is 0, the packet will be remarked based on assigned priority¡¢Tx port priority copy¡¢swap and remarking setting. Otherwise£¬priority¡¢DEI and DSCP would not be remarked by ALE*/ + rtk_uint8 aspri; /*If ASPRI is 1, MCU8051 provides the priority (maybe include DEI and DSCP if exist) directly. If ASPRI is 0, the priority¡¢DEI and DSCP is decided by ASIC lookup process.*/ + rtk_uint32 dmp; /*Destination Port Mask*/ +}tx_cpuTag_t; + +/* ITag & OTag Information */ +typedef struct vlan_tag_s +{ + rtk_uint16 etherType; + rtk_uint16 tag; +}vlan_tag_t; + +/* Packet information needed when receiving packets */ +typedef struct rx_pktInfo_s +{ + rx_stat_t rx_stat; + rtk_uint8 da[6]; + rtk_uint8 sa[6]; + rx_cpuTag_t cpu_tag; + vlan_tag_t otag; + vlan_tag_t itag; + rtk_uint8* data_buf; // packet buffer + rtk_uint16 buf_len; // length when used for protocol stack + //uint16 proto_start; // offset used when parsering the packet +}rx_pktInfo_t; + +typedef struct pktBuf_s { + rtk_uint16 size; + rtk_uint8 *frame_info; + rtk_uint8 *pkt_cputag; + rtk_uint8 *pkt_vlantag; + rtk_uint8 *pkt_head; + rtk_uint8 *l2; + rtk_uint8 *l3; + rtk_uint8 *l4; + rtk_uint8 l2fmt; /* Layer 2 Format */ + rtk_uint8 l3fmt; /* Layer 3 Format */ + rtk_uint8 l4fmt; /* Layer 4 Format */ + + rtk_uint8 spa; /* Rx port */ + + rtk_uint8 tx_chksum_mode; /* Check sum config for NIC tx function */ + rtk_uint8 tx_dport_mode; /* Tx packet mode. please reference to tx_pkt_mode_t */ + rtk_uint32 tx_dst_pmsk; + rtk_uint8 inner_tag_mode; /* InnerTagMode of TX pkt */ + rtk_uint8 outer_tag_mode; /* InnerTagMode of TX pkt */ + rtk_uint32 inner_tag; /* Inner tag of rx pkt / Inner tag of tx pkt */ + rtk_uint32 outer_tag; /* Outer tag of rx pkt / Outer tag of tx pkt */ +} pktBuf_t; + +extern ret_t dal_rtl8373_nic_rst_set(void); + +extern ret_t dal_rtl8373_nic_txStopAddr_set(rtk_uint32 addr); +extern ret_t dal_rtl8373_nic_txStopAddr_get(rtk_uint32 *pAddr); + +extern ret_t dal_rtl8373_nic_rxStopAddr_set(rtk_uint32 addr); +extern ret_t dal_rtl8373_nic_rxStopAddr_get(rtk_uint32 *pAddr); + +extern ret_t dal_rtl8373_nic_moduleEn_set(rtk_enable_t enabled); +extern ret_t dal_rtl8373_nic_moduleEn_get(rtk_enable_t *pEnabled); + +extern ret_t dal_rtl8373_nic_rxEn_set(rtk_enable_t enabled); +extern ret_t dal_rtl8373_nic_rxEn_get(rtk_enable_t *pEnabled); + +extern ret_t dal_rtl8373_nic_rxRemoveCrc_set(rtk_enable_t enabled); +extern ret_t dal_rtl8373_nic_rxRemoveCrc_get(rtk_enable_t *pEnabled); + +extern ret_t dal_rtl8373_nic_rxPaddingEn_set(rtk_enable_t enabled); +extern ret_t dal_rtl8373_nic_rxPaddingEn_get(rtk_enable_t *pEnabled); + +extern ret_t dal_rtl8373_nic_rxFreeSpaceThd_set(rtk_uint32 val); +extern ret_t dal_rtl8373_nic_rxFreeSpaceThd_get(rtk_nic_RxMTU_t *pVal); + +extern ret_t dal_rtl8373_nic_rxCrcErrEn_set(rtk_enable_t enabled); +extern ret_t dal_rtl8373_nic_rxCrcErrEn_get(rtk_enable_t *pEnabled); + +extern ret_t dal_rtl8373_nic_rxL3CrcErrEn_set(rtk_enable_t enabled); +extern ret_t dal_rtl8373_nic_rxL3CrcErrEn_get(rtk_enable_t *pEnabled); + +extern ret_t dal_rtl8373_nic_rxL4CrcErrEn_set(rtk_enable_t enabled); +extern ret_t dal_rtl8373_nic_rxL4CrcErrEn_get(rtk_enable_t *pEnabled); + +extern ret_t dal_rtl8373_nic_rxArpEn_set(rtk_enable_t enabled); +extern ret_t dal_rtl8373_nic_rxArpEn_get(rtk_enable_t *pEnabled); + +extern ret_t dal_rtl8373_nic_rxAllPktEn_set(rtk_enable_t enabled); +extern ret_t dal_rtl8373_nic_rxAllPktEn_get(rtk_enable_t *pEnabled); + +extern ret_t dal_rtl8373_nic_rxPhyPktSel_set(rtk_nic_rxpps_t behavior); +extern ret_t dal_rtl8373_nic_rxPhyPktSel_get(rtk_nic_rxpps_t *pBehavior); + +extern ret_t dal_rtl8373_nic_rxMultiPktEn_set(rtk_enable_t enabled); +extern ret_t dal_rtl8373_nic_rxMultiPktEn_get(rtk_enable_t *pEnabled); + +extern ret_t dal_rtl8373_nic_rxBcPktEn_set(rtk_enable_t enabled); +extern ret_t dal_rtl8373_nic_rxBcPktEn_get(rtk_enable_t *pEnabled); + +extern ret_t dal_rtl8373_nic_mcHashFltrEn_set(rtk_enable_t enabled); +extern ret_t dal_rtl8373_nic_mcHashFltrEn_get(rtk_enable_t *pEnabled); + +extern ret_t dal_rtl8373_nic_phyPktHashFltrEn_set(rtk_enable_t enabled); +extern ret_t dal_rtl8373_nic_phyPktHashFltrEn_get(rtk_enable_t *pEnabled); + +extern ret_t dal_rtl8373_nic_phyPktHashTblVal_set(rtk_nic_hashValType_t type, rtk_uint32 val); +extern ret_t dal_rtl8373_nic_phyPktHashTblVal_get(rtk_nic_hashValType_t type, rtk_uint32 *pVal); + +extern ret_t dal_rtl8373_nic_mcHashTblVal_set(rtk_nic_hashValType_t type, rtk_uint32 val); +extern ret_t dal_rtl8373_nic_mcHashTblVal_get(rtk_nic_hashValType_t type, rtk_uint32 *pVal); + +extern ret_t dal_rtl8373_nic_rxMTU_set(rtk_nic_RxMTU_t lenIdx); +extern ret_t dal_rtl8373_nic_rxMTU_get(rtk_nic_RxMTU_t *pLenIdx); + +extern ret_t dal_rtl8373_nic_txEn_set(rtk_enable_t enabled); +extern ret_t dal_rtl8373_nic_txEn_get(rtk_enable_t *pEnabled); + +extern ret_t dal_rtl8373_nic_loopbackEn_set(rtk_enable_t enabled); +extern ret_t dal_rtl8373_nic_loopbackEn_get(rtk_enable_t *pEnabled); + +extern ret_t dal_rtl8373_nic_interruptEn_set(rtk_enable_t rxie, rtk_enable_t txee); +extern ret_t dal_rtl8373_nic_interruptEn_get(rtk_enable_t *pRxie, rtk_enable_t *pTxee); + +extern ret_t dal_rtl8373_nic_interruptStatus_get(rtk_uint32 *pRxis, rtk_uint32 *pTxes); +extern ret_t dal_rtl8373_nic_interruptStatus_clear(rtk_uint32 rxis, rtk_uint32 txes); + +extern ret_t dal_rtl8373_nic_swRxCurPktAddr_get(rtk_uint32 *pAddr); +extern ret_t dal_rtl8373_nic_rxReceivedPktLen_get(rtk_uint32 *pLength); +extern ret_t dal_rtl8373_nic_txAvailSpace_get(rtk_uint32 *pLength); + +#endif /* __DAL_RTL8373_NIC_H__ */ diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_parser.c b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_parser.c new file mode 100755 index 00000000..6749e932 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_parser.c @@ -0,0 +1,189 @@ +/* + * Copyright (C) 2012 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision: $ + * $Date: $ + * + * Purpose : Declaration of Parser + * + * Feature : The file have include the following module and sub-modules + * 1) HSB, HSA get + * + */ + + +/* + * Include Files + */ +#include +#include +#include +#include + +/* Function Name: + * dal_rtl8373_ignrOUI_set + * Description: + * Get ignore OUI + * Input: + * None + * Output: + * pEnabled - ignore OUI enable/disable + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RMA_ADDR - Invalid RMA address index + * Note: + * None + */ +ret_t dal_rtl8373_ignrOUI_set(rtk_uint32 enabled) +{ + ret_t retVal; + + retVal = rtl8373_setAsicRegBit(RTL8373_PARSER_CTRL_ADDR, RTL8373_PARSER_CTRL_RFC1042_OUI_IGNORE_OFFSET,enabled); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + + +/* Function Name: + * dal_rtl8373_ignrOUI_get + * Description: + * Get ignore OUI + * Input: + * None + * Output: + * pEnabled - ignore OUI enable/disable + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RMA_ADDR - Invalid RMA address index + * Note: + * None + */ +ret_t dal_rtl8373_ignrOUI_get(rtk_uint32 *pEnabled) +{ + ret_t retVal; + + retVal = rtl8373_getAsicRegBit(RTL8373_PARSER_CTRL_ADDR, RTL8373_PARSER_CTRL_RFC1042_OUI_IGNORE_OFFSET,pEnabled); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; + +} + + + +/* Function Name: + * dal_rtl8373_rxReason_get + * Description: + * Get ignore OUI + * Input: + * None + * Output: + * pReason - rx drop reason + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RMA_ADDR - Invalid RMA address index + * Note: + * None + */ +ret_t dal_rtl8373_rxReason_get(rtk_uint32 port, rtk_uint32 *pReason) +{ + ret_t retVal; + + retVal = rtl8373_getAsicRegBits(RTL8373_PARSER_DROP_REASON_ADDR(port), RTL8373_PARSER_DROP_REASON_REASON_MASK,pReason); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; + +} + + + +/* Function Name: + * dal_rtl8373_fieldSelector_set + * Description: + * Get field selector setting + * Input: + * None + * Output: + * index - 0~15 + * format 0 ~ 7 + * offset 0 ~ 172 + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RMA_ADDR - Invalid RMA address index + * Note: + * None + */ +ret_t dal_rtl8373_fieldSelector_set(rtk_uint32 index, rtk_uint32 format, rtk_uint32 offset) +{ + ret_t retVal; + + retVal = rtl8373_setAsicRegBits(RTL8373_PARSER_FIELD_SELTOR_CTRL_ADDR(index), RTL8373_PARSER_FIELD_SELTOR_CTRL_FMT_MASK,format); + if(retVal != RT_ERR_OK) + return retVal; + + + retVal = rtl8373_setAsicRegBits(RTL8373_PARSER_FIELD_SELTOR_CTRL_ADDR(index), RTL8373_PARSER_FIELD_SELTOR_CTRL_OFFSET_MASK,offset); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_fieldSelector_get + * Description: + * Get field selector setting + * Input: + * None + * Output: + * index - 0~15 + * pFormat 0 ~ 7 + * pOffset 0 ~ 172 + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RMA_ADDR - Invalid RMA address index + * Note: + * None + */ +ret_t dal_rtl8373_fieldSelector_get(rtk_uint32 index, rtk_uint32 *pFormat, rtk_uint32 *pOffset) +{ + ret_t retVal; + + retVal = rtl8373_getAsicRegBits(RTL8373_PARSER_FIELD_SELTOR_CTRL_ADDR(index), RTL8373_PARSER_FIELD_SELTOR_CTRL_FMT_MASK,pFormat); + if(retVal != RT_ERR_OK) + return retVal; + + + retVal = rtl8373_getAsicRegBits(RTL8373_PARSER_FIELD_SELTOR_CTRL_ADDR(index), RTL8373_PARSER_FIELD_SELTOR_CTRL_OFFSET_MASK,pOffset); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + + + + + + diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_parser.h b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_parser.h new file mode 100755 index 00000000..71b0ddba --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_parser.h @@ -0,0 +1,104 @@ +#ifndef __DAL_RTL8373_PARSER_H__ +#define __DAL_RTL8373_PARSER_H__ + + +/* Function Name: + * dal_rtl8373_ignrOUI_set + * Description: + * Get ignore OUI + * Input: + * None + * Output: + * pEnabled - ignore OUI enable/disable + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RMA_ADDR - Invalid RMA address index + * Note: + * None + */ +extern ret_t dal_rtl8373_ignrOUI_set(rtk_uint32 enabled); + + + +/* Function Name: + * dal_rtl8373_ignrOUI_get + * Description: + * Get ignore OUI + * Input: + * None + * Output: + * pEnabled - ignore OUI enable/disable + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RMA_ADDR - Invalid RMA address index + * Note: + * None + */ +extern ret_t dal_rtl8373_ignrOUI_get(rtk_uint32 *pEnabled); + + + +/* Function Name: + * dal_rtl8373_rxReason_get + * Description: + * Get ignore OUI + * Input: + * None + * Output: + * pReason - rx drop reason + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RMA_ADDR - Invalid RMA address index + * Note: + * None + */ +extern ret_t dal_rtl8373_rxReason_get(rtk_uint32 port, rtk_uint32 *pReason); + + + +/* Function Name: + * dal_rtl8373_fieldSelector_set + * Description: + * Get field selector setting + * Input: + * None + * Output: + * index - 0~15 + * format 0 ~ 7 + * offset 0 ~ 172 + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RMA_ADDR - Invalid RMA address index + * Note: + * None + */ +extern ret_t dal_rtl8373_fieldSelector_set(rtk_uint32 index, rtk_uint32 format, rtk_uint32 offset); + + +/* Function Name: + * dal_rtl8373_fieldSelector_get + * Description: + * Get field selector setting + * Input: + * None + * Output: + * index - 0~15 + * pFormat 0 ~ 7 + * pOffset 0 ~ 172 + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RMA_ADDR - Invalid RMA address index + * Note: + * None + */ +extern ret_t dal_rtl8373_fieldSelector_get(rtk_uint32 index, rtk_uint32 *pFormat, rtk_uint32 *pOffset); + + + +#endif + diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_port.c b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_port.c new file mode 100755 index 00000000..ec4a30e7 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_port.c @@ -0,0 +1,1596 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8373 + * Feature : Here is a list of all functions and variables in port module. + * + */ + +#include +#include +#include +#include +#include +#include +#include + +rtk_uint32 PORT3_PHYAD=0; +#ifdef GE550V2_RTL8372_RTL8251B +rtk_uint32 PORT8_PHYAD=2; +#else +rtk_uint32 PORT8_PHYAD=0; +#endif +rtk_uint16 rtl8373_rtct_patch[][2]= +{ + {0x81A3,0x2E}, + {0x81A4,0xE0}, + {0x81A5,0x2E}, + {0x81A6,0xE0}, + {0x81A8,0x1D}, + {0x81A9,0x00}, + {0x81AF,0x2D}, + {0x81B0,0x05}, + {0x81B2,0x09}, + {0x81B3,0x1F}, + {0x81BC,0x1D}, + {0x81BD,0x00}, + {0x81BE,0x00}, + {0x81BF,0xEA}, + {0x81C0,0x03}, + {0x81C1,0xCA}, + {0x81C2,0x1D}, + {0x81C3,0x00}, + {0x81C4,0x00}, + {0x81C5,0x3B}, + {0x81C6,0x00}, + {0x81C7,0x1A}, + {0x81C8,0x00}, + {0x81C9,0x54}, + {0x81CA,0xFF}, + {0x81CB,0xD5}, + {0x81CC,0x07}, + {0x81CD,0xFA}, + {0x81CE,0xFF}, + {0x81CF,0x14}, + {0x81D0,0x00}, + {0x81D1,0x74}, + {0x81D2,0xFF}, + {0x81D3,0xDB}, + {0x81D4,0x09}, + {0x81D5,0xF0}, + {0x81D6,0xFF}, + {0x81D7,0x97}, + {0x81D8,0xFF}, + {0x81D9,0xC2}, + {0x81DA,0x00}, + {0x81DB,0x28}, + {0x81DC,0xF1}, + {0x81DD,0xA0}, + {0x81DE,0x00}, + {0x81DF,0x94}, + {0x81E0,0x00}, + {0x81E1,0x76}, + {0x81E2,0xFF}, + {0x81E3,0xB8}, + {0x81E4,0xEA}, + {0x81E5,0xDD}, + {0x81E6,0x01}, + {0x81E7,0x6B}, + {0x81E8,0xFF}, + {0x81E9,0xAA}, + {0x81EA,0x00}, + {0x81EB,0x06}, + {0x81EC,0x05}, + {0x81ED,0x0A}, + {0x81EE,0xFF}, + {0x81EF,0x9D}, + {0x81F0,0x00}, + {0x81F1,0x10}, + {0x81F2,0x00}, + {0x81F3,0x05}, + {0x81F4,0x01}, + {0x81F5,0xE0}, + {0x81F6,0x00}, + {0x81F7,0x00}, + {0x81F8,0x00}, + {0x81F9,0x00}, + {0x81FA,0x00}, + {0x81FB,0x00}, +}; + + + + + + +static ret_t _rtl8373_portlink_get(rtk_uint32 port, rtk_uint32* link) +{ + rtk_uint32 regData = 0; + ret_t retVal; + + retVal = rtl8373_getAsicReg(RTL8373_MAC_LINK_STS_ADDR, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8373_getAsicReg(RTL8373_MAC_LINK_STS_ADDR, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + *link = (regData >> port) & 1; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_portFrcAblitiy_set + * Description: + * Set port force ability + * Input: + * port - 0 ~ 9 + * ability - link, speed, duplex, rxpause, txpause + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ + +ret_t dal_rtl8373_portFrcAbility_set(rtk_uint32 port, rtk_port_ability_t* ability) +{ + rtk_uint32 regData = 0; + rtk_uint32 tmp = 0; + ret_t retVal; + if((ability->forcemode>=RTK_ENABLE_END)||(ability->link>=PORT_LINKSTATUS_END)||(ability->duplex>=PORT_DUPLEX_END)|| + (ability->speed >=PORT_SPEED_END)||(ability->txpause>=RTK_ENABLE_END)||(ability->rxpause>=RTK_ENABLE_END)|| + (ability->smi_force_fc>=RTK_ENABLE_END)||(ability->media>=PORT_MEDIA_END)) + return RT_ERR_INPUT; + + /*if port now is link up, force linkdown first, then set other ability*/ + _rtl8373_portlink_get(port, &tmp); + if(tmp == 1) + { + retVal = rtl8373_setAsicRegBit(RTL8373_MAC_FORCE_MODE_CTRL0_ADDR(port), RTL8373_MAC_FORCE_MODE_CTRL0_FORCE_LINK_EN_OFFSET, 0); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8373_setAsicRegBit(RTL8373_MAC_FORCE_MODE_CTRL0_ADDR(port), RTL8373_MAC_FORCE_MODE_CTRL0_MAC_FORCE_EN_OFFSET, 1); + if(retVal != RT_ERR_OK) + return retVal; + } + + regData = ability->forcemode & 1; + regData |= (ability->link << 1); + regData |= (ability->duplex << 2); + regData |= ((ability->speed & 0xf) << 3); + regData |= (ability->txpause << 7); + regData |= (ability->rxpause << 8); + regData |= (ability->smi_force_fc << 9); + regData |= (ability->media << 10); + + return rtl8373_setAsicRegBits(RTL8373_MAC_FORCE_MODE_CTRL0_ADDR(port), 0x7ff, regData); +} + + +/* Function Name: + * dal_rtl8373_portFrcAblitiy_get + * Description: + * Get port force ability + * Input: + * port - 0 ~ 9 + * ability - link, speed, duplex, rxpause, txpause + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ + +ret_t dal_rtl8373_portFrcAbility_get(rtk_uint32 port, rtk_port_ability_t* ability) +{ + rtk_uint32 regData = 0; + ret_t retVal; + + retVal = rtl8373_getAsicRegBits(RTL8373_MAC_FORCE_MODE_CTRL0_ADDR(port), 0x7ff, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + ability->forcemode = regData & 1; + ability->link = (regData >> 1) & 1; + ability->duplex = (regData >> 2) & 1; + ability->speed = (regData >> 3) & 0xf; + ability->txpause = (regData >> 7) & 1; + ability->rxpause = (regData >> 8) & 1; + ability->smi_force_fc = (regData >> 9) & 1; + ability->media = (regData >> 10) & 1; + + return RT_ERR_OK; +} + + + +/* Function Name: + * dal_rtl8373_portStatus_get + * Description: + * Get port status + * Input: + * port - 0 ~ 9 + * ability - link, speed, duplex, rxpause, txpause + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ + +ret_t dal_rtl8373_portStatus_get(rtk_uint32 port, rtk_port_status_t* status) +{ + rtk_uint32 regData = 0; + ret_t retVal; + /*link status*/ + retVal = rtl8373_getAsicReg(RTL8373_MAC_LINK_STS_ADDR, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8373_getAsicReg(RTL8373_MAC_LINK_STS_ADDR, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + status->link = (regData >> port) & 1; + + /*speed status*/ + retVal = rtl8373_getAsicRegBits(RTL8373_MAC_LINK_SPD_STS_ADDR(port), RTL8373_MAC_LINK_SPD_STS_SPD_STS_9_0_MASK(port), ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + status->speed= regData; + + /*duplex status*/ + retVal = rtl8373_getAsicReg(RTL8373_MAC_LINK_DUP_STS_ADDR, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + status->duplex= (regData >> port) & 1; + + /*tx pause status*/ + retVal = rtl8373_getAsicReg(RTL8373_MAC_TX_PAUSE_STS_ADDR, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + status->txpause= (regData >> port) & 1; + + /*rx pause status*/ + retVal = rtl8373_getAsicReg(RTL8373_MAC_TX_PAUSE_STS_ADDR, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + status->rxpause= (regData >> port) & 1; + + /*media status*/ + retVal = rtl8373_getAsicReg(RTL8373_MAC_LINK_MEDIA_STS_ADDR, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + status->media= (regData >> port) & 1; + + /*eee status*/ + retVal = rtl8373_getAsicReg(RTL8373_MAC_EEE_ABLTY_ADDR, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + status->eee= (regData >> port) & 1; + + /*master status*/ + retVal = rtl8373_getAsicReg(RTL8373_MAC_MSTR_SLV_STS_ADDR, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + status->master= (regData >> port) & 1; + + /*master slave nway*/ + retVal = rtl8373_getAsicReg(RTL8373_MAC_MSTR_SLV_FAULT_STS_ADDR, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + status->master_slave= (regData >> port) & 1; + + + return RT_ERR_OK; + +} + + +/* Function Name: + * dal_rtl8373_portMaxLen_set + * Description: + * Set port rx max length + * Input: + * port - 0 ~ 9 + * type - 0 FE:10M,100M, 1 giga:1G, 2.5G, 5G, 10G + * len - max length + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ + +ret_t dal_rtl8373_portMaxLen_set(rtk_uint32 port, rtk_uint32 type, rtk_uint32 len) +{ + ret_t retVal; + + + if(type == 0) + { + retVal = rtl8373_setAsicRegBits(RTL8373_MAC_L2_PORT_MAX_LEN_CTRL_ADDR(port), RTL8373_MAC_L2_PORT_MAX_LEN_CTRL_MAX_LEN_100M_10M_SEL_MASK, len); + if(retVal != RT_ERR_OK) + return retVal; + } + else if(type == 1) + { + retVal = rtl8373_setAsicRegBits(RTL8373_MAC_L2_PORT_MAX_LEN_CTRL_ADDR(port), RTL8373_MAC_L2_PORT_MAX_LEN_CTRL_MAX_LEN_1G_2P5G_5G_10G_SEL_MASK, len); + if(retVal != RT_ERR_OK) + return retVal; + } + else + return RT_ERR_INPUT; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_portMaxLen_get + * Description: + * Get port rx max length + * Input: + * port - 0 ~ 9 + * type - 0 FE:10M,100M, 1 giga:1G, 2.5G, 5G, 10G + * pLen - max length + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ + +ret_t dal_rtl8373_portMaxLen_get(rtk_uint32 port, rtk_uint32 type, rtk_uint32* pLen) +{ + ret_t retVal; + + + if(type == 0) + { + retVal = rtl8373_getAsicRegBits(RTL8373_MAC_L2_PORT_MAX_LEN_CTRL_ADDR(port), RTL8373_MAC_L2_PORT_MAX_LEN_CTRL_MAX_LEN_100M_10M_SEL_MASK, pLen); + if(retVal != RT_ERR_OK) + return retVal; + } + else if(type == 1) + { + retVal = rtl8373_getAsicRegBits(RTL8373_MAC_L2_PORT_MAX_LEN_CTRL_ADDR(port), RTL8373_MAC_L2_PORT_MAX_LEN_CTRL_MAX_LEN_1G_2P5G_5G_10G_SEL_MASK, pLen); + if(retVal != RT_ERR_OK) + return retVal; + } + else + return RT_ERR_INPUT; + + return RT_ERR_OK; +} + + + + +/* Function Name: + * dal_rtl8373_portMaxLenIncTag_set + * Description: + * Set port rx max length include tag length: cputag ctag, stag + * Input: + * port - 0 ~ 9 + * enaleb - 1: include tag length, 0: not include tag length + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ + +ret_t dal_rtl8373_portMaxLenIncTag_set(rtk_uint32 port, rtk_uint32 enable) +{ + + + return rtl8373_setAsicRegBit(RTL8373_MAC_L2_PORT_MAX_LEN_CTRL_ADDR(port), RTL8373_MAC_L2_PORT_MAX_LEN_CTRL_MAX_LEN_TAG_INC_OFFSET, enable); + +} + + +/* Function Name: + * dal_rtl8373_portMaxLenIncTag_get + * Description: + * Get port rx max length include tag length: cputag ctag, stag + * Input: + * port - 0 ~ 9 + * enaleb - 1: include tag length, 0: not include tag length + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ + +ret_t dal_rtl8373_portMaxLenIncTag_get(rtk_uint32 port, rtk_uint32* pEnable) +{ + + return rtl8373_getAsicRegBit(RTL8373_MAC_L2_PORT_MAX_LEN_CTRL_ADDR(port), RTL8373_MAC_L2_PORT_MAX_LEN_CTRL_MAX_LEN_TAG_INC_OFFSET, pEnable); + +} + + +/* Function Name: + * dal_rtl8373_portLoopbackEn_set + * Description: + * Set port mac tx loopback to rx + * Input: + * port - 0 ~ 9 + * enable - 0 disable loopback, 1 enable loopback + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ + +ret_t dal_rtl8373_portLoopbackEn_set(rtk_uint32 port, rtk_enable_t enable) +{ + ret_t retVal; + + + retVal = rtl8373_setAsicRegBit(RTL8373_MAC_L2_PORT_CTRL_ADDR(port), RTL8373_MAC_L2_PORT_CTRL_CFG_PORT_L_LPBK_OFFSET, enable); + if(retVal != RT_ERR_OK) + return retVal; + + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_portLoopbackEn_get + * Description: + * Get port mac tx loopback to rx + * Input: + * port - 0 ~ 9 + * pEnable - 0 disable loopback, 1 enable loopback + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ + +ret_t dal_rtl8373_portLoopbackEn_get(rtk_uint32 port, rtk_enable_t * pEnable) +{ + ret_t retVal; + + + retVal = rtl8373_getAsicRegBit(RTL8373_MAC_L2_PORT_CTRL_ADDR(port), RTL8373_MAC_L2_PORT_CTRL_CFG_PORT_L_LPBK_OFFSET, pEnable); + if(retVal != RT_ERR_OK) + return retVal; + + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_portBackpressureEn_set + * Description: + * Set port half back pressure enable + * Input: + * port - 0 ~ 9 + * enable - 0 disable backpressure, 1 enable backpressure + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ + +ret_t dal_rtl8373_portBackpressureEn_set(rtk_uint32 port, rtk_enable_t enable) +{ + ret_t retVal; + + + retVal = rtl8373_setAsicRegBit(RTL8373_MAC_PORT_CTRL_ADDR(port), RTL8373_MAC_PORT_CTRL_BKPRES_EN_OFFSET, enable); + if(retVal != RT_ERR_OK) + return retVal; + + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_portBackpressureEn_get + * Description: + * Get port half back pressure enable + * Input: + * port - 0 ~ 9 + * pEnable - 0 disable backpressure, 1 enable backpressure + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ + +ret_t dal_rtl8373_portBackpressureEn_get(rtk_uint32 port, rtk_enable_t * pEnable) +{ + ret_t retVal; + + + retVal = rtl8373_getAsicRegBit(RTL8373_MAC_PORT_CTRL_ADDR(port), RTL8373_MAC_PORT_CTRL_BKPRES_EN_OFFSET, pEnable); + if(retVal != RT_ERR_OK) + return retVal; + + + return RT_ERR_OK; +} + + + + +/* Function Name: + * dal_rtl8373_port_extphyid_set + * Description: + * Set smi address ,SMI Address, default value equals to port number + * Input: + * sdsid - 0,1 + * phyid - get from phy strap pin + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ + +ret_t dal_rtl8373_port_extphyid_set(rtk_uint32 sdsid, rtk_uint32 phyid) +{ + ret_t retVal; + + RTK_CHK_INIT_STATE(); + if(sdsid == SERDES_ID0) + { + retVal =rtl8373_setAsicRegBits(RTL8373_SMI_MAC_TYPE_CTRL_ADDR, RTL8373_SMI_MAC_TYPE_CTRL_MAC_PORT3_TYPE_MASK, 1); + if(retVal != RT_ERR_OK) + return retVal; + retVal = rtl8373_setAsicRegBits(RTL8373_SMI_PORT0_5_ADDR_CTRL_ADDR, RTL8373_SMI_PORT0_5_ADDR_CTRL_PORT3_ADDR_MASK, phyid); + if(retVal != RT_ERR_OK) + return retVal; + PORT3_PHYAD=phyid; + } + else if(sdsid == SERDES_ID1) + { + retVal =rtl8373_setAsicRegBits(RTL8373_SMI_MAC_TYPE_CTRL_ADDR, RTL8373_SMI_MAC_TYPE_CTRL_MAC_PORT8_TYPE_MASK, 1); + if(retVal != RT_ERR_OK) + return retVal; + retVal = rtl8373_setAsicRegBits(RTL8373_SMI_PORT6_9_ADDR_CTRL_ADDR, RTL8373_SMI_PORT6_9_ADDR_CTRL_PORT8_ADDR_MASK, phyid); + if(retVal != RT_ERR_OK) + return retVal; + PORT8_PHYAD=phyid; + } + else + return RT_ERR_INPUT; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_port_extphyid_get + * Description: + * Get smi address ,SMI Address, default value equals to port number + * Input: + * sdsid - 0,1 + * phyid - get smi address + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ + +ret_t dal_rtl8373_port_extphyid_get(rtk_uint32 sdsid, rtk_uint32 *phyid) +{ + ret_t retVal; + + if(phyid == NULL) + return RT_ERR_INPUT; + + if(sdsid == SERDES_ID0) + { + + retVal = rtl8373_getAsicRegBits(RTL8373_SMI_PORT0_5_ADDR_CTRL_ADDR, RTL8373_SMI_PORT0_5_ADDR_CTRL_PORT3_ADDR_MASK, phyid); + if(retVal != RT_ERR_OK) + return retVal; + + } + else if(sdsid == SERDES_ID1) + { + + retVal = rtl8373_getAsicRegBits(RTL8373_SMI_PORT6_9_ADDR_CTRL_ADDR, RTL8373_SMI_PORT6_9_ADDR_CTRL_PORT8_ADDR_MASK, phyid); + if(retVal != RT_ERR_OK) + return retVal; + } + else + return RT_ERR_INPUT; + + return RT_ERR_OK; +} +/* Function Name: + * dal_rtl8373_port_sdsNway_set + * Description: + * Configure serdes port Nway state + * Input: + * sdsId - serdes ID + * sdsMode - serdes mode + * enable - 1:enable nway, 0:disable nway + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API configure SERDES port Nway state + */ +rtk_api_ret_t dal_rtl8373_port_sdsNway_set(rtk_uint32 sdsId, rtk_sds_mode_t sdsMode, rtk_enable_t enable) +{ + switch(sdsMode) + { + case SERDES_100FX: + case SERDES_10GR: + break; + case SERDES_1000BASEX: + case SERDES_2500BASEX: + case SERDES_SG: + case SERDES_HSG: + if(enable) + { + dal_rtl8373_sds_regbits_write(sdsId, 0, 2, 0x3<<8, 0x3); + dal_rtl8373_sds_regbits_write(sdsId, 0, 4, 0x1<<2, 0x1); + } + else + { + dal_rtl8373_sds_regbits_write(sdsId, 0, 2, 0x3<<8, 0x1); + dal_rtl8373_sds_regbits_write(sdsId, 0, 4, 0x1<<2, 0x1); + } + break; + case SERDES_10GUSXG: + case SERDES_10GQXG: + if(enable) + { + dal_rtl8373_sds_regbits_write(sdsId, 7, 17, 0xf<<0, 0xf); + } + else + { + + dal_rtl8373_sds_regbits_write(sdsId, 7, 17, 0xf<<0, 0x0); + } + break; + default: + return RT_ERR_INPUT; + break; + } + return RT_ERR_OK; +} +/* Function Name: + * dal_rtl8373_port_sdsNway_get + * Description: + * Get serdes Nway + * Input: + * sdsid - serdes ID + * pState - Nway state + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API configure serdes port Nway state + */ +rtk_api_ret_t dal_rtl8373_port_sdsNway_get(rtk_uint32 sdsId, rtk_sds_mode_t sdsMode, rtk_enable_t *pState) +{ + rtk_uint32 regData; + + switch(sdsMode) + { + case SERDES_100FX: + case SERDES_10GR: + break; + case SERDES_1000BASEX: + case SERDES_2500BASEX: + case SERDES_SG: + case SERDES_HSG: + dal_rtl8373_sds_regbits_read(sdsId, 0, 2, 0x1<<8, ®Data); + if(regData == 1) + *pState = ENABLED; + else if(regData == 0) + *pState = DISABLED; + else + return RT_ERR_FAILED; + + break; + case SERDES_10GUSXG: + case SERDES_10GQXG: + dal_rtl8373_sds_regbits_read(sdsId, 7, 17, 0xf<<0, ®Data); + if(regData == 0xf) + *pState = ENABLED; + else if(regData == 0) + *pState = DISABLED; + else + return RT_ERR_FAILED; + break; + default: + return RT_ERR_INPUT; + break; + } + return RT_ERR_OK; +} +/* Function Name: + * dal_rtl8373_sdsMode_set + * Description: + * Set sds mode + * Input: + * sdsid - 0 ~ 1 + * mode - + * SERDES_10GQXG, + * SERDES_10GUSXG, + * SERDES_10GR, + * SERDES_HSG, + * SERDES_2500BASEX, + * SERDES_SG, + * SERDES_1000BASEX, + * SERDES_100FX, + * SERDES_OFF, + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_NOT_ALLOWED - mode is not support + * Note: + * None + */ + +rtk_api_ret_t dal_rtl8373_sdsMode_set(rtk_uint32 sdsid, rtk_sds_mode_t mode) +{ + ret_t retVal; + rtk_uint32 regdata, chiptype; + + RTK_CHK_INIT_STATE(); + + if((retVal = rtl8373_getAsicReg(0x4, ®data)) != RT_ERR_OK) + return retVal; + + regdata = regdata >> 8; + + if(regdata == 0x837300) + { + if((sdsid == 0) && (mode != SERDES_10GQXG) && (mode != SERDES_OFF)) + return RT_ERR_NOT_ALLOWED; + chiptype = CHIP_RTL8373_MODE; + } + else if (regdata == 0x837200) + chiptype = CHIP_RTL8372_MODE; + else if (regdata == 0x822400) + { + chiptype = CHIP_RTL8224_MODE; + } + else if (regdata == 0x837370) + { + chiptype = CHIP_RTL8373N_MODE; + } + else if (regdata == 0x837270) + { + chiptype = CHIP_RTL8372N_MODE; + } + else if (regdata == 0x822470) + { + chiptype = CHIP_RTL8224N_MODE; + } + else if (regdata == 0x8366A8) + { + chiptype = CHIP_RTL8366U_MODE; + } + else + return RT_ERR_CHIP_NOT_FOUND; + + if(sdsid==SERDES_ID0) + { + if (mode == SERDES_8221B) + { + rtl8373_setAsicRegBit(RTL8373_SDS_MODE_SEL_ADDR, RTL8373_SDS_MODE_SEL_CFG_MAC3_8221B_OFFSET, ENABLED); + rtl8373_setAsicRegBits(RTL8373_SMI_PORT0_5_ADDR_CTRL_ADDR, RTL8373_SMI_PORT0_5_ADDR_CTRL_PORT3_ADDR_MASK, PORT3_PHYAD); + rtl8373_setAsicRegBit(RTL8373_SMI_PORT_POLLING_SEL_ADDR, RTL8373_SMI_PORT_POLLING_SEL_SMI_POLLING_SEL3_OFFSET, ENABLED); // RTL8372 set port3 polling internal resolution reg + cfg_rl6637_sds_mode(UTP_PORT3, 1); + SDS_MODE_SET_SW(chiptype, sdsid, SERDES_SG); + SDS_MODE_SET_SW(chiptype, sdsid, SERDES_HSG); + //rtl8373_setAsicRegBits(RTL8373_SDS_MODE_SEL_ADDR,RTL8373_SDS_MODE_SEL_SDS0_MODE_SEL_MASK,0x1F); + + } + else + { + + rtl8373_setAsicRegBit(RTL8373_SDS_MODE_SEL_ADDR, RTL8373_SDS_MODE_SEL_CFG_MAC3_8221B_OFFSET, DISABLED); + rtl8373_setAsicRegBits(RTL8373_SDS_MODE_SEL_ADDR,RTL8373_SDS_MODE_SEL_SDS0_MODE_SEL_MASK,0x1F); + delay_loop(100); + SDS_MODE_SET_SW(chiptype, sdsid, mode); + } + } + if(sdsid==SERDES_ID1) + { + if (mode == SERDES_8221B) + { + rtl8373_setAsicRegBit(RTL8373_SDS_MODE_SEL_ADDR, RTL8373_SDS_MODE_SEL_CFG_MAC8_8221B_OFFSET, ENABLED); + rtl8373_setAsicRegBits(RTL8373_SMI_PORT6_9_ADDR_CTRL_ADDR, RTL8373_SMI_PORT6_9_ADDR_CTRL_PORT8_ADDR_MASK, PORT8_PHYAD); + cfg_rl6637_sds_mode(UTP_PORT8, 1); + SDS_MODE_SET_SW(chiptype, sdsid, SERDES_SG); + SDS_MODE_SET_SW(chiptype, sdsid, SERDES_HSG); + //rtl8373_setAsicRegBits(RTL8373_SDS_MODE_SEL_ADDR,RTL8373_SDS_MODE_SEL_SDS1_MODE_SEL_MASK,0x1F); + rtl8373_setAsicRegBit(RTL8373_SMI_PORT_POLLING_SEL_ADDR, RTL8373_SMI_PORT_POLLING_SEL_SMI_POLLING_SEL8_OFFSET, ENABLED); // RTL8372 set port8 polling internal resolution reg + } + else + { + + rtl8373_setAsicRegBit(RTL8373_SDS_MODE_SEL_ADDR, RTL8373_SDS_MODE_SEL_CFG_MAC8_8221B_OFFSET, DISABLED); + rtl8373_setAsicRegBits(RTL8373_SDS_MODE_SEL_ADDR,RTL8373_SDS_MODE_SEL_SDS1_MODE_SEL_MASK,0x1F); + delay_loop(100); + SDS_MODE_SET_SW(chiptype, sdsid, mode); + } + } + + delay_loop(50); + if((mode == SERDES_10GQXG)||(mode == SERDES_10GR) || (mode == SERDES_10GUSXG)) + fw_reset_flow_tgr(sdsid); + else + fw_reset_flow_tgx(sdsid); + + delay_loop(50); + + return RT_ERR_OK; + +} + + + +/* Function Name: + * dal_rtl8373_sdsMode_get + * Description: + * Get sds mode + * Input: + * sdsid - 0 ~ 1 + * pMode - + * SERDES_10GQXG, + * SERDES_10GUSXG, + * SERDES_10GR, + * SERDES_HSG, + * SERDES_2500BASEX, + * SERDES_SG, + * SERDES_1000BASEX, + * SERDES_100FX, + * SERDES_OFF, + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_NOT_ALLOWED - mode is not support + * Note: + * None + */ + +rtk_api_ret_t dal_rtl8373_sdsMode_get(rtk_uint32 sdsid, rtk_sds_mode_t * pMode) +{ + rtk_uint32 regdata, subtype; + + if(sdsid == 0) + { + rtl8373_getAsicRegBits(RTL8373_SDS_MODE_SEL_ADDR, RTL8373_SDS_MODE_SEL_SDS0_MODE_SEL_MASK,®data); + rtl8373_getAsicRegBits(RTL8373_SDS_MODE_SEL_ADDR, RTL8373_SDS_MODE_SEL_SDS0_USX_SUB_MODE_MASK,&subtype); + } + else if(sdsid == 1) + { + rtl8373_getAsicRegBits(RTL8373_SDS_MODE_SEL_ADDR, RTL8373_SDS_MODE_SEL_SDS1_MODE_SEL_MASK,®data); + rtl8373_getAsicRegBits(RTL8373_SDS_MODE_SEL_ADDR, RTL8373_SDS_MODE_SEL_SDS1_USX_SUB_MODE_MASK,&subtype); + } + else + return RT_ERR_INPUT; + + if(regdata == 0xD) + { + /*USXG*/ + if(subtype == 0) + *pMode = SERDES_10GUSXG; + else if (subtype == 2) + *pMode = SERDES_10GQXG; + else + return RT_ERR_FAILED; + + } + else if (regdata == 0x1A) + *pMode = SERDES_10GR; + else if (regdata == 0x12) + *pMode = SERDES_HSG; + else if (regdata == 0x16) + *pMode = SERDES_2500BASEX; + else if (regdata == 0x2) + *pMode = SERDES_SG; + else if (regdata == 0x4) + *pMode = SERDES_1000BASEX; + else if (regdata == 0x5) + *pMode = SERDES_100FX; + else if (regdata == 0x1F) + *pMode = SERDES_OFF; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_rtct_init + * Description: + * Init RTCT + * Input: + * None. + * Output: + * None. + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Invalid port mask + * Note: + * RTCT test takes 4.8 seconds at most. + */ + +ret_t dal_rtl8373_rtct_init(void) +{ + rtk_uint32 phyid, len, regaddr, regdata, i; + rtk_uint32 rg_dll_one_ch_en, pn_rate, rg_biquad_coef_sel, enlongpn, rg_rtct_hpf_coef_sel, reg_pnrate; + + + for(phyid = 4; phyid < 8; phyid++) + { + dal_rtl8373_phy_regbits_write(1<channelABusy = channalA & 1; + pResult->channelAMisOpen = (channalA >> 1) & 1; + pResult->channelAMisShort = (channalA >> 2) & 1; + pResult->channelAOpen = (channalA >> 3) & 1; + pResult->channelAShort = (channalA >> 4) & 1; + pResult->channelANormal = (channalA >> 5) & 1; + pResult->channelADone = (channalA >> 6) & 1; + pResult->channelAInterShort = (channalA >> 7) & 1; + + pResult->channelBBusy = channalB & 1; + pResult->channelBMisOpen = (channalB >> 1) & 1; + pResult->channelBMisShort = (channalB >> 2) & 1; + pResult->channelBOpen = (channalB >> 3) & 1; + pResult->channelBShort = (channalB >> 4) & 1; + pResult->channelBNormal = (channalB >> 5) & 1; + pResult->channelBDone = (channalB >> 6) & 1; + pResult->channelBInterShort = (channalB >> 7) & 1; + + pResult->channelCBusy = channalC & 1; + pResult->channelCMisOpen = (channalC >> 1) & 1; + pResult->channelCMisShort = (channalC >> 2) & 1; + pResult->channelCOpen = (channalC >> 3) & 1; + pResult->channelCShort = (channalC >> 4) & 1; + pResult->channelCNormal = (channalC >> 5) & 1; + pResult->channelCDone = (channalC >> 6) & 1; + pResult->channelCInterShort = (channalC >> 7) & 1; + + pResult->channelDBusy = channalD & 1; + pResult->channelDMisOpen = (channalD >> 1) & 1; + pResult->channelDMisShort = (channalD >> 2) & 1; + pResult->channelDOpen = (channalD >> 3) & 1; + pResult->channelDShort = (channalD >> 4) & 1; + pResult->channelDNormal = (channalD >> 5) & 1; + pResult->channelDDone = (channalD >> 6) & 1; + pResult->channelDInterShort = (channalD >> 7) & 1; + + return RT_ERR_OK; + +} + + +/* Function Name: + * dal_rtl8373_iol_fix_pattern + * Description: + * Set IOL fix pattern. + * Input: + * port - port id 0 - 8 + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will enbale MDC function. + */ + +rtk_api_ret_t dal_rtl8373_iol_fix_pattern(rtk_uint32 port) +{ + rtk_uint32 phymask; + rtk_api_ret_t retVal; + + phymask = 1 << port; + + if ((retVal = dal_rtl8373_phy_write(phymask, 31, 0xc804, 0x0015)) != RT_ERR_OK) + return retVal; + + + if ((retVal = dal_rtl8373_phy_write(phymask, 31, 0xc800, 0xFF21)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_iol_random_pattern + * Description: + * Set IOL ramdom pattern. + * Input: + * port - port id 0 - 8 + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will enbale MDC function. + */ + +rtk_api_ret_t dal_rtl8373_iol_random_pattern(rtk_uint32 port) +{ + rtk_uint32 phymask; + rtk_api_ret_t retVal; + + phymask = 1 << port; + + if ((retVal = dal_rtl8373_phy_write(phymask, 31, 0xc804, 0x0115)) != RT_ERR_OK) + return retVal; + + + if ((retVal = dal_rtl8373_phy_write(phymask, 31, 0xc800, 0x5A21)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + + +/* Function Name: + * dal_rtl8373_iol_10M_mode + * Description: + * Set IOL 10M mode. + * Input: + * port - port id 0 - 8 + * mode - 0:mdi 1:mdix + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will enbale MDC function. + */ + +rtk_api_ret_t dal_rtl8373_iol_10M_mode(rtk_uint32 port, rtk_uint32 mode) +{ + rtk_uint32 phymask; + rtk_api_ret_t retVal; + + phymask = 1 << port; + + if ((retVal = dal_rtl8373_phy_write(phymask, 1, 0, 0)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8373_phy_regbits_write(phymask, 7, 0, 1 << 12, 0)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8373_phy_regbits_write(phymask, 31, 0xA412, 7 << 13, 0)) != RT_ERR_OK) + return retVal; + + if(mode == IOL_MODE_MDI) + { + if ((retVal = dal_rtl8373_phy_write(phymask, 31, 0xA430, 0x239A)) != RT_ERR_OK) + return retVal; + } + else if(mode == IOL_MODE_MDIX) + { + if ((retVal = dal_rtl8373_phy_write(phymask, 31, 0xA430, 0x229A)) != RT_ERR_OK) + return retVal; + } + else + return RT_ERR_INPUT; + + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_iol_100M_mode + * Description: + * Set IOL 100M mode. + * Input: + * port - port id 0 - 8 + * mode - 0:mdi 1:mdix + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will enbale MDC function. + */ + +rtk_api_ret_t dal_rtl8373_iol_100M_mode(rtk_uint32 port, rtk_uint32 mode) +{ + rtk_uint32 phymask; + rtk_api_ret_t retVal; + + phymask = 1 << port; + + if ((retVal = dal_rtl8373_phy_write(phymask, 1, 0, 0x2000)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8373_phy_write(phymask, 7, 0, 0x2000)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8373_phy_write(phymask, 31, 0xA412, 0x0200)) != RT_ERR_OK) + return retVal; + + if(mode == IOL_MODE_MDI) + { + if ((retVal = dal_rtl8373_phy_write(phymask, 31, 0xA430, 0x239A)) != RT_ERR_OK) + return retVal; + } + else if(mode == IOL_MODE_MDIX) + { + if ((retVal = dal_rtl8373_phy_write(phymask, 31, 0xA430, 0x229A)) != RT_ERR_OK) + return retVal; + } + else + return RT_ERR_INPUT; + + + return RT_ERR_OK; +} + + + +/* Function Name: + * dal_rtl8373_iol_giga_mode + * Description: + * Set IOL Giga mode. + * Input: + * port - port id 0 - 8 + * mode - 1 - 4 + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will enbale MDC function. + */ + +rtk_api_ret_t dal_rtl8373_iol_giga_mode(rtk_uint32 port, rtk_uint32 mode) +{ + rtk_uint32 phymask; + rtk_api_ret_t retVal; + + phymask = 1 << port; + + if ((retVal = dal_rtl8373_phy_write(phymask, 1, 0, 0xA058)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8373_phy_write(phymask, 7, 0, 0x3000)) != RT_ERR_OK) + return retVal; + + + if(mode == 1) + { + if ((retVal = dal_rtl8373_phy_write(phymask, 31, 0xA412, 0x3040)) != RT_ERR_OK) + return retVal; + } + else if(mode == 2) + { + if ((retVal = dal_rtl8373_phy_write(phymask, 31, 0xA412, 0x5040)) != RT_ERR_OK) + return retVal; + } + else if(mode == 3) + { + if ((retVal = dal_rtl8373_phy_write(phymask, 31, 0xA412, 0x7040)) != RT_ERR_OK) + return retVal; + } + else if(mode == 4) + { + if ((retVal = dal_rtl8373_phy_write(phymask, 31, 0xA412, 0x9040)) != RT_ERR_OK) + return retVal; + } + else + return RT_ERR_INPUT; + + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_iol_2p5G_mode2 + * Description: + * Set IOL 2.5G mode2. + * Input: + * port - port id 0 - 8 + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will enbale MDC function. + */ + +rtk_api_ret_t dal_rtl8373_iol_2p5G_mode2(rtk_uint32 port) +{ + rtk_uint32 phymask; + rtk_api_ret_t retVal; + + phymask = 1 << port; + + if ((retVal = dal_rtl8373_phy_write(phymask, 1, 0x84, 0x4400)) != RT_ERR_OK) + return retVal; + + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_iol_2p5G_mode3 + * Description: + * Set IOL 2.5G mode3. + * Input: + * port - port id 0 - 8 + * lp + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will enbale MDC function. + */ + +rtk_api_ret_t dal_rtl8373_iol_2p5G_mode3(rtk_uint32 port, rtk_uint32 lp) +{ + rtk_uint32 phymask, lpmask; + rtk_api_ret_t retVal; + + phymask = 1 << port; + lpmask = 1 << lp; + + if ((retVal = dal_rtl8373_phy_write(phymask, 1, 0x84, 0x6400)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8373_phy_write(lpmask, 1, 0x84, 0x2400)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_iol_2p5G_mode4 + * Description: + * Set IOL 2.5G mode4. + * Input: + * port - port id 0 - 8 + * tone - 1-5 + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will enbale MDC function. + */ + +rtk_api_ret_t dal_rtl8373_iol_2p5G_mode4(rtk_uint32 port, rtk_uint32 tone) +{ + rtk_uint32 phymask; + rtk_api_ret_t retVal; + + phymask = 1 << port; + + if(tone == 1) + { + if ((retVal = dal_rtl8373_phy_write(phymask, 1, 0x84, 0x8400)) != RT_ERR_OK) + return retVal; + } + else if(tone == 2) + { + if ((retVal = dal_rtl8373_phy_write(phymask, 1, 0x84, 0x8800)) != RT_ERR_OK) + return retVal; + } + else if(tone == 3) + { + if ((retVal = dal_rtl8373_phy_write(phymask, 1, 0x84, 0x9000)) != RT_ERR_OK) + return retVal; + } + else if(tone == 4) + { + if ((retVal = dal_rtl8373_phy_write(phymask, 1, 0x84, 0x9400)) != RT_ERR_OK) + return retVal; + } + else if(tone == 5) + { + if ((retVal = dal_rtl8373_phy_write(phymask, 1, 0x84, 0x9800)) != RT_ERR_OK) + return retVal; + } + else + return RT_ERR_INPUT; + + + return RT_ERR_OK; +} + + + +/* Function Name: + * dal_rtl8373_iol_2p5G_mode5 + * Description: + * Set IOL 2.5G mode5. + * Input: + * port - port id 0 - 8 + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will enbale MDC function. + */ + +rtk_api_ret_t dal_rtl8373_iol_2p5G_mode5(rtk_uint32 port) +{ + rtk_uint32 phymask; + rtk_api_ret_t retVal; + + phymask = 1 << port; + + if ((retVal = dal_rtl8373_phy_write(phymask, 1, 0x84, 0xA400)) != RT_ERR_OK) + return retVal; + + + return RT_ERR_OK; +} + + + +/* Function Name: + * dal_rtl8373_iol_2p5G_mode6 + * Description: + * Set IOL 2.5G mode6. + * Input: + * port - port id 0 - 8 + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will enbale MDC function. + */ + +rtk_api_ret_t dal_rtl8373_iol_2p5G_mode6(rtk_uint32 port) +{ + rtk_uint32 phymask; + rtk_api_ret_t retVal; + + phymask = 1 << port; + + if ((retVal = dal_rtl8373_phy_write(phymask, 31, 0xA412, 0x0200)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8373_phy_write(phymask, 7, 0x0, 0x3000)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8373_phy_write(phymask, 1, 0x0, 0x2058)) != RT_ERR_OK) + return retVal; + + if ((retVal = dal_rtl8373_phy_write(phymask, 1, 0x84, 0xC400)) != RT_ERR_OK) + return retVal; + + + return RT_ERR_OK; +} + + + + diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_port.h b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_port.h new file mode 100755 index 00000000..63dbb3e1 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_port.h @@ -0,0 +1,629 @@ +#ifndef __DAL_RTL8373_PORT_H__ +#define __DAL_RTL8373_PORT_H__ + + +#include +#include + + + +typedef enum rtk_iol_mode_e +{ + IOL_MODE_MDI = 0, + IOL_MODE_MDIX, + IOL_MODE_END, + +} rtk_iol_mode_t; + + + + +/* Function Name: + * dal_rtl8373_portFrcAblitiy_set + * Description: + * Set port force ability + * Input: + * port - 0 ~ 9 + * ability - link, speed, duplex, rxpause, txpause + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ + +extern ret_t dal_rtl8373_portFrcAbility_set(rtk_uint32 port, rtk_port_ability_t* ability); + + +/* Function Name: + * dal_rtl8373_portFrcAblitiy_get + * Description: + * Get port force ability + * Input: + * port - 0 ~ 9 + * ability - link, speed, duplex, rxpause, txpause + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ + +extern ret_t dal_rtl8373_portFrcAbility_get(rtk_uint32 port, rtk_port_ability_t* ability); + + + +/* Function Name: + * dal_rtl8373_portStatus_get + * Description: + * Get port status + * Input: + * port - 0 ~ 9 + * ability - link, speed, duplex, rxpause, txpause + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ + +extern ret_t dal_rtl8373_portStatus_get(rtk_uint32 port, rtk_port_status_t* status); + +/* Function Name: + * dal_rtl8373_portMaxLen_set + * Description: + * Set port rx max length + * Input: + * port - 0 ~ 9 + * type - 0 FE:10M,100M, 1 giga:1G, 2.5G, 5G, 10G + * len - max length + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ + +extern ret_t dal_rtl8373_portMaxLen_set(rtk_uint32 port, rtk_uint32 type, rtk_uint32 len); + + +/* Function Name: + * dal_rtl8373_portMaxLen_get + * Description: + * Get port rx max length + * Input: + * port - 0 ~ 9 + * type - 0 FE:10M,100M, 1 giga:1G, 2.5G, 5G, 10G + * pLen - max length + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ + +extern ret_t dal_rtl8373_portMaxLen_get(rtk_uint32 port, rtk_uint32 type, rtk_uint32* pLen); + + + + +/* Function Name: + * dal_rtl8373_portMaxLenIncTag_set + * Description: + * Set port rx max length include tag length: cputag ctag, stag + * Input: + * port - 0 ~ 9 + * enaleb - 1: include tag length, 0: not include tag length + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ + +extern ret_t dal_rtl8373_portMaxLenIncTag_set(rtk_uint32 port, rtk_uint32 enable); + + +/* Function Name: + * dal_rtl8373_portMaxLenIncTag_get + * Description: + * Get port rx max length include tag length: cputag ctag, stag + * Input: + * port - 0 ~ 9 + * enaleb - 1: include tag length, 0: not include tag length + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ + +extern ret_t dal_rtl8373_portMaxLenIncTag_get(rtk_uint32 port, rtk_uint32* pEnable); + + +/* Function Name: + * dal_rtl8373_portLoopbackEn_set + * Description: + * Set port mac tx loopback to rx + * Input: + * port - 0 ~ 9 + * enable - 0 disable loopback, 1 enable loopback + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ + +extern ret_t dal_rtl8373_portLoopbackEn_set(rtk_uint32 port, rtk_enable_t enable); + + +/* Function Name: + * dal_rtl8373_portLoopbackEn_get + * Description: + * Get port mac tx loopback to rx + * Input: + * port - 0 ~ 9 + * pEnable - 0 disable loopback, 1 enable loopback + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ + +extern ret_t dal_rtl8373_portLoopbackEn_get(rtk_uint32 port, rtk_enable_t * pEnable); + + +/* Function Name: + * dal_rtl8373_portBackpressureEn_set + * Description: + * Set port half back pressure enable + * Input: + * port - 0 ~ 9 + * enable - 0 disable backpressure, 1 enable backpressure + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ + +extern ret_t dal_rtl8373_portBackpressureEn_set(rtk_uint32 port, rtk_enable_t enable); + + +/* Function Name: + * dal_rtl8373_portBackpressureEn_get + * Description: + * Get port half back pressure enable + * Input: + * port - 0 ~ 9 + * pEnable - 0 disable backpressure, 1 enable backpressure + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ + +extern ret_t dal_rtl8373_portBackpressureEn_get(rtk_uint32 port, rtk_enable_t * pEnable); + + + +/* Function Name: + * dal_rtl8373_rtct_start + * Description: + * Set RTCT start + * Input: + * portmask - Port mask of RTCT enabled (4 - 7) + * Output: + * None. + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Invalid port mask + * Note: + * RTCT test takes 4.8 seconds at most. + */ +extern ret_t dal_rtl8373_rtct_start(rtk_uint32 phymask); + + +/* Function Name: + * dal_rtl8373_rtct_status_get + * Description: + * Get RTCT result + * Input: + * phyid - Port id of RTCT result (4 - 7) + * pResult - result of RTCT + * Output: + * None. + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * RTCT test takes 4.8 seconds at most. + */ +extern ret_t dal_rtl8373_rtct_status_get(rtk_uint32 phyid, rtk_rtct_result_t * pResult); + + +/* Function Name: + * dal_rtl8373_iol_fix_pattern + * Description: + * Set IOL fix pattern. + * Input: + * port - port id 0 - 8 + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will enbale MDC function. + */ + +extern rtk_api_ret_t dal_rtl8373_iol_fix_pattern(rtk_uint32 port); + + +/* Function Name: + * dal_rtl8373_iol_random_pattern + * Description: + * Set IOL ramdom pattern. + * Input: + * port - port id 0 - 8 + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will enbale MDC function. + */ + +extern rtk_api_ret_t dal_rtl8373_iol_random_pattern(rtk_uint32 port); + + + +/* Function Name: + * dal_rtl8373_iol_10M_mode + * Description: + * Set IOL 10M mode. + * Input: + * port - port id 0 - 8 + * mode - 0:mdi 1:mdix + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will enbale MDC function. + */ + +extern rtk_api_ret_t dal_rtl8373_iol_10M_mode(rtk_uint32 port, rtk_uint32 mode); + + +/* Function Name: + * dal_rtl8373_iol_100M_mode + * Description: + * Set IOL 100M mode. + * Input: + * port - port id 0 - 8 + * mode - 0:mdi 1:mdix + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will enbale MDC function. + */ + +extern rtk_api_ret_t dal_rtl8373_iol_100M_mode(rtk_uint32 port, rtk_uint32 mode); + + + +/* Function Name: + * dal_rtl8373_iol_giga_mode + * Description: + * Set IOL Giga mode. + * Input: + * port - port id 0 - 8 + * mode - 1 - 4 + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will enbale MDC function. + */ + +extern rtk_api_ret_t dal_rtl8373_iol_giga_mode(rtk_uint32 port, rtk_uint32 mode); + + +/* Function Name: + * dal_rtl8373_iol_2p5G_mode2 + * Description: + * Set IOL 2.5G mode2. + * Input: + * port - port id 0 - 8 + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will enbale MDC function. + */ + +extern rtk_api_ret_t dal_rtl8373_iol_2p5G_mode2(rtk_uint32 port); + + +/* Function Name: + * dal_rtl8373_iol_2p5G_mode3 + * Description: + * Set IOL 2.5G mode3. + * Input: + * port - port id 0 - 8 + * lp + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will enbale MDC function. + */ + +extern rtk_api_ret_t dal_rtl8373_iol_2p5G_mode3(rtk_uint32 port, rtk_uint32 lp); + + +/* Function Name: + * dal_rtl8373_iol_2p5G_mode4 + * Description: + * Set IOL 2.5G mode4. + * Input: + * port - port id 0 - 8 + * tone - 1-5 + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will enbale MDC function. + */ + +extern rtk_api_ret_t dal_rtl8373_iol_2p5G_mode4(rtk_uint32 port, rtk_uint32 tone); + + + +/* Function Name: + * dal_rtl8373_iol_2p5G_mode5 + * Description: + * Set IOL 2.5G mode5. + * Input: + * port - port id 0 - 8 + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will enbale MDC function. + */ + +extern rtk_api_ret_t dal_rtl8373_iol_2p5G_mode5(rtk_uint32 port); + + + +/* Function Name: + * dal_rtl8373_iol_2p5G_mode6 + * Description: + * Set IOL 2.5G mode6. + * Input: + * port - port id 0 - 8 + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will enbale MDC function. + */ + +extern rtk_api_ret_t dal_rtl8373_iol_2p5G_mode6(rtk_uint32 port); + + +/* Function Name: + * dal_rtl8373_port_extphyid_set + * Description: + * Set smi address ,SMI Address, default value equals to port number + * Input: + * sdsid - 0,1 + * phyid - get from phy strap pin + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ + +extern ret_t dal_rtl8373_port_extphyid_set(rtk_uint32 sdsid, rtk_uint32 phyid); + +/* Function Name: + * dal_rtl8373_port_extphyid_get + * Description: + * Get smi address ,SMI Address, default value equals to port number + * Input: + * sdsid - 0,1 + * phyid - get smi address + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ + +extern ret_t dal_rtl8373_port_extphyid_get(rtk_uint32 sdsid, rtk_uint32 *phyid); +/* Function Name: + * dal_rtl8373_sdsMode_set + * Description: + * Set sds mode + * Input: + * sdsid - 0 ~ 1 + * mode - + * SERDES_10GQXG, + * SERDES_10GUSXG, + * SERDES_10GR, + * SERDES_HSG, + * SERDES_2500BASEX, + * SERDES_SG, + * SERDES_1000BASEX, + * SERDES_100FX, + * SERDES_OFF, + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_NOT_ALLOWED - mode is not support + * Note: + * None + */ + +extern rtk_api_ret_t dal_rtl8373_sdsMode_set(rtk_uint32 sdsid, rtk_sds_mode_t mode); + +/* Function Name: + * dal_rtl8373_sdsMode_get + * Description: + * Get sds mode + * Input: + * sdsid - 0 ~ 1 + * pMode - + * SERDES_10GQXG, + * SERDES_10GUSXG, + * SERDES_10GR, + * SERDES_HSG, + * SERDES_2500BASEX, + * SERDES_SG, + * SERDES_1000BASEX, + * SERDES_100FX, + * SERDES_OFF, + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_NOT_ALLOWED - mode is not support + * Note: + * None + */ + +extern rtk_api_ret_t dal_rtl8373_sdsMode_get(rtk_uint32 sdsid, rtk_sds_mode_t * pMode); + +/* Function Name: + * dal_rtl8373_port_sdsNway_set + * Description: + * Configure serdes port Nway state + * Input: + * sdsId - serdes ID + * sdsMode - serdes mode + * enable - 1:enable nway, 0:disable nway + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API configure SERDES port Nway state + */ +extern rtk_api_ret_t dal_rtl8373_port_sdsNway_set(rtk_uint32 sdsId, rtk_sds_mode_t sdsMode, rtk_enable_t enable); + +/* Function Name: + * dal_rtl8373_port_sdsNway_get + * Description: + * Get serdes Nway + * Input: + * sdsid - serdes ID + * pState - Nway state + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API configure serdes port Nway state + */ +extern rtk_api_ret_t dal_rtl8373_port_sdsNway_get(rtk_uint32 sdsId, rtk_sds_mode_t sdsMode, rtk_enable_t *pState); + +/* Function Name: + * dal_rtl8373_rtct_init + * Description: + * Init RTCT + * Input: + * None. + * Output: + * None. + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Invalid port mask + * Note: + * RTCT test takes 4.8 seconds at most. + */ + +extern ret_t dal_rtl8373_rtct_init(void); + + + +#endif + diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_ptp.c b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_ptp.c new file mode 100755 index 00000000..6ab47d44 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_ptp.c @@ -0,0 +1,1922 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision: 39583 $ + * $Date: 2013-05-20 16:59:23 +0800 (星期一, 20 五月 2013) $ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8367C + * Feature : Here is a list of all functions and variables in time module. + * + */ + +#include +#include +#include +#include +#include +#include +//#include + +static rtk_uint32 ptp_internal_portmask = 0x01f8; +static rtk_port_t l2ptp_port[RTK_SWITCH_PORT_NUM]={0xff,0xff,0xff,4,0,1,2,3,5}; +/* Function Name: + * rtk_switch_port_L2Ptpport_get + * Description: + * Get ptp port ID + * Input: + * logicalPort - logical port ID + * Output: + * None + * Return: + * ptp port ID + * Note: + * + */ +rtk_uint32 rtk_switch_port_L2Ptpport_get(rtk_port_t logicalPort) +{ + + if(logicalPort >= RTK_SWITCH_PORT_NUM) + return UNDEFINE_PHY_PORT; + + return (l2ptp_port[logicalPort]); +} +/* Function Name: + * rtl8373_getAsicEavInterruptMask + * Description: + * Get PTP interrupt enable mask + * Input: + * pImrMsk - Interrupt mask + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + */ +static ret_t rtl8373_getAsicisrMask(rtk_uint32 *pIsrMsk) +{ + rtk_uint32 pps_1,tod_done,txtime_empty; + + if (pIsrMsk==NULL) + return RT_ERR_INPUT; + + rtl8373_getAsicRegBit(RTL8373_PTP_MIB_INTR_ADDR, RTL8373_PTP_MIB_INTR_RD_ISR_PPS_I_OFFSET, &pps_1); + rtl8373_getAsicRegBit(RTL8373_TOD_INTR_ADDR, RTL8373_TOD_INTR_ISR_TOD_OFFSET, &tod_done); + rtl8373_getAsicRegBit(RTL8373_PTP_MIB_INTR_ADDR, RTL8373_PTP_MIB_INTR_RD_ISR_PTP_OFFSET, &txtime_empty); + + *pIsrMsk=(pps_1<eth_en); + if(retVal != RT_ERR_OK) + return retVal; + retVal =rtl8373_setAsicRegBit(RTL8373_RMA_PORT_PTP_UDP_CTRL_ADDR(port),RTL8373_RMA_PORT_PTP_UDP_CTRL_UDP_P0_ACT_OFFSET(port) , trapctrl->udp_en); + if(retVal != RT_ERR_OK) + return retVal; + retVal =rtl8373_setAsicRegBit(RTL8373_RMA_PORT_PTP_DELAY_CARE_CTRL_ADDR(port),RTL8373_RMA_PORT_PTP_DELAY_CARE_CTRL_P0_PTP_DELAY_CARE_OFFSET(port) ,trapctrl->ptp_delay_en); + if(retVal != RT_ERR_OK) + return retVal; + retVal =rtl8373_setAsicRegBit(RTL8373_RMA_PORT_PTP_PDELAY_CARE_CTRL_ADDR(port),RTL8373_RMA_PORT_PTP_PDELAY_CARE_CTRL_P0_PTP_PDELAY_CARE_OFFSET(port),trapctrl->ptp_pdelay_en); + if(retVal != RT_ERR_OK) + return retVal; + retVal =rtl8373_setAsicRegBit(RTL8373_RMA_PORT_PTP_ASM_CARE_CTRL_ADDR(port),RTL8373_RMA_PORT_PTP_ASM_CARE_CTRL_P0_PTP_ASM_CARE_OFFSET(port) ,trapctrl->ptp_pasm_en); + if(retVal != RT_ERR_OK) + return retVal; + + return retVal; +} +/* Function Name: + * rtl8373_getAsicEavTrap + * Description: + * Set PTPtrap enable mask + * Input: + * none + * Output: + * enabled + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + + */ +static ret_t rtl8373_getAsicEavTrap(rtk_uint32 port, rtk_ptp_porttrap_ctrl_t *trapctrl) +{ + ret_t retVal; + + retVal =rtl8373_getAsicRegBit(RTL8373_RMA_PORT_PTP_ETH2_CTRL_ADDR(port),RTL8373_RMA_PORT_PTP_ETH2_CTRL_ETH2_P0_ACT_OFFSET(port), &(trapctrl->eth_en)); + if(retVal != RT_ERR_OK) + return retVal; + retVal =rtl8373_getAsicRegBit(RTL8373_RMA_PORT_PTP_UDP_CTRL_ADDR(port),RTL8373_RMA_PORT_PTP_UDP_CTRL_UDP_P0_ACT_OFFSET(port) , &(trapctrl->udp_en)); + if(retVal != RT_ERR_OK) + return retVal; + retVal =rtl8373_getAsicRegBit(RTL8373_RMA_PORT_PTP_DELAY_CARE_CTRL_ADDR(port),RTL8373_RMA_PORT_PTP_DELAY_CARE_CTRL_P0_PTP_DELAY_CARE_OFFSET(port) ,&(trapctrl->ptp_delay_en)); + if(retVal != RT_ERR_OK) + return retVal; + retVal =rtl8373_getAsicRegBit(RTL8373_RMA_PORT_PTP_PDELAY_CARE_CTRL_ADDR(port),RTL8373_RMA_PORT_PTP_PDELAY_CARE_CTRL_P0_PTP_PDELAY_CARE_OFFSET(port),&(trapctrl->ptp_pdelay_en)); + if(retVal != RT_ERR_OK) + return retVal; + retVal =rtl8373_getAsicRegBit(RTL8373_RMA_PORT_PTP_ASM_CARE_CTRL_ADDR(port),RTL8373_RMA_PORT_PTP_ASM_CARE_CTRL_P0_PTP_ASM_CARE_OFFSET(port) ,&(trapctrl->ptp_pasm_en)); + if(retVal != RT_ERR_OK) + return retVal; + return RT_ERR_OK; +} +/* Function Name: + * rtl8373_ptp_execbyreg + * Description: + * PTP function exec by register. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API is used to initialize PTP status. + */ +static ret_t rtl8373_ptp_execbyreg(void) +{ + ret_t retVal=0; + rtk_uint32 busyFlag, count; + + if((retVal = rtl8373_setAsicRegBit(RTL8373_PTP_TIME_CRTL_ADDR,RTL8373_PTP_TIME_CRTL_PTP_TIME_EXEC_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + count = 0; + do { + if((retVal = rtl8373_getAsicRegBit(RTL8373_PTP_TIME_CRTL_ADDR, RTL8373_PTP_TIME_CRTL_PTP_TIME_EXEC_OFFSET, &busyFlag)) != RT_ERR_OK) + return retVal; + count++; + } while ((busyFlag != 0)&&(count<20)); + + if (busyFlag != 0) + return RT_ERR_BUSYWAIT_TIMEOUT; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_ptp_init + * Description: + * PTP function initialization. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API is used to initialize PTP status. + */ +ret_t dal_rtl8373_ptp_internalport(rtk_portmask_t portmask) +{ + ptp_internal_portmask=portmask.bits[0]; + return RT_ERR_OK; +} +/* Function Name: + * dal_rtl8373_ptp_init + * Description: + * PTP function initialization. + * Input: + * ptpinternalpmask port range 3~8 + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API is used to initialize PTP status. + */ +ret_t dal_rtl8373_ptp_init( rtk_portmask_t ptpinternalpmask) +{ + + rtk_port_t port; + rtk_uint32 freq=0x10000000;//internal clock + + /* Check initialization state */ + dal_rtl8373_ptp_internalport(ptpinternalpmask); + + for(port=UTP_PORT0;port= VLAN_TYPE_END) || (idx > 4)) + return RT_ERR_INPUT; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(type == OUTER_VLAN) + { + if((retVal = rtl8373_setAsicReg(RTL8373_PTP_OTAG_CONFIG0_ADDR+(4<= VLAN_TYPE_END) || (idx > 4)) + return RT_ERR_INPUT; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(type == OUTER_VLAN) + { + if((retVal = rtl8373_getAsicReg(RTL8373_PTP_OTAG_CONFIG0_ADDR+(4<> 4; + switch (oper) + { + case 0: + pOperCfg->oper = TIME_OPER_START; + break; + case 1: + pOperCfg->oper = TIME_OPER_LATCH; + break; + case 2: + pOperCfg->oper = TIME_OPER_STOP; + break; + case 3: + pOperCfg->oper = TIME_OPER_CMD_EXEC; + break; + case 4: + pOperCfg->oper = TIME_OPER_FREQ_APPLY; + break; + default: + return RT_ERR_FAILED; + } + + pOperCfg->rise_tri = (reg_val & RTL8373_PTP_TIME_OP_CTRL_CFG_GPI_RISE_TRIG_MASK) >> 3; + pOperCfg->fall_tri = (reg_val & RTL8373_PTP_TIME_OP_CTRL_CFG_GPI_FALL_TRIG_MASK) >> 2; + + + /*to be added phy*/ + + return ret; +} +/* Function Name: + * dal_rtl8373_ptp_Oper_triger + * Description: + * Set the PTP time operation triger. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None + */ +ret_t dal_rtl8373_ptp_Oper_triger() +{ + rtk_int32 ret; + rtk_time_opertriger_t opt; + rtk_uint32 retVal; + + if((ret = rtl8373_setAsicRegBit(RTL8373_TOD_UART_SETTING_ADDR, RTL8373_TOD_UART_SETTING_TIMER_GPIO_OE_OFFSET,ENABLED)) != RT_ERR_OK) + return ret; + if((ret = rtl8373_getAsicRegBits(RTL8373_PTP_TIME_OP_CTRL_ADDR, + RTL8373_PTP_TIME_OP_CTRL_CFG_GPI_RISE_TRIG_MASK|RTL8373_PTP_TIME_OP_CTRL_CFG_GPI_FALL_TRIG_MASK,&opt)) != RT_ERR_OK) + return ret; + + switch(opt) + { + case TIME_RISE_TRI: + if((ret = rtl8373_setAsicRegBit(RTL8373_TOD_UART_SETTING_ADDR, RTL8373_TOD_UART_SETTING_TIMER_GPO_OFFSET,DISABLED)) != RT_ERR_OK) + return ret; + if((ret = rtl8373_setAsicRegBit(RTL8373_TOD_UART_SETTING_ADDR, RTL8373_TOD_UART_SETTING_TIMER_GPO_OFFSET,ENABLED)) != RT_ERR_OK) + return ret; + break; + case TIME_FALL_TRI: + if((ret = rtl8373_setAsicRegBit(RTL8373_TOD_UART_SETTING_ADDR, RTL8373_TOD_UART_SETTING_TIMER_GPO_OFFSET,ENABLED)) != RT_ERR_OK) + return ret; + if((ret = rtl8373_setAsicRegBit(RTL8373_TOD_UART_SETTING_ADDR, RTL8373_TOD_UART_SETTING_TIMER_GPO_OFFSET,DISABLED)) != RT_ERR_OK) + return ret; + break; + case TIME_BOTH_TRI: + if((ret = rtl8373_getAsicRegBit(RTL8373_TOD_UART_SETTING_ADDR, RTL8373_TOD_UART_SETTING_TIMER_GPO_OFFSET,&retVal)) != RT_ERR_OK) + return ret; + retVal=((retVal+1)&1); + if((ret = rtl8373_setAsicRegBit(RTL8373_TOD_UART_SETTING_ADDR, RTL8373_TOD_UART_SETTING_TIMER_GPO_OFFSET,retVal)) != RT_ERR_OK) + return ret; + break; + + default: + return RT_ERR_INPUT; + } + + + return RT_ERR_OK; +} +/* Function Name: + * dal_rtl8373_ptp_Oper_set + * Description: + * Set the PTP time operation configuration of specific port. + * Input: + * port - port ID + * pOperCfg - pointer to PTP time operation configuraton + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None + */ +ret_t dal_rtl8373_ptp_Oper_set( rtk_time_operCfg_t pOperCfg) +{ + rtk_int32 ret ; + rtk_uint32 reg_val = 0; + + + switch (pOperCfg.oper) + { + case TIME_OPER_START: + reg_val = 0 << 4; + break; + case TIME_OPER_LATCH: + reg_val = 1 << 4; + break; + case TIME_OPER_STOP: + reg_val = 2 << 4; + break; + case TIME_OPER_CMD_EXEC: + reg_val = 3 << 4; + break; + case TIME_OPER_FREQ_APPLY: + reg_val = 4 << 4; + break; + default: + return RT_ERR_FAILED; + } + reg_val |= (pOperCfg.rise_tri == ENABLED) ? (RTL8373_PTP_TIME_OP_CTRL_CFG_GPI_RISE_TRIG_MASK) : (0); + reg_val |= (pOperCfg.fall_tri == ENABLED) ? (RTL8373_PTP_TIME_OP_CTRL_CFG_GPI_FALL_TRIG_MASK) : (0); + if((ret = rtl8373_setAsicReg(RTL8373_PTP_TIME_OP_CTRL_ADDR, reg_val)) != RT_ERR_OK) + return ret; + + if(pOperCfg.tri_apply) + { + return dal_rtl8373_ptp_Oper_triger(); + } + + /*to be added phy*/ + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_ptp_LatchTime_get + * Description: + * Get the PTP latched time of specific port by hardware. + * Input: + * Output: + * pLatchTime - pointer to PTP time operation configuraton + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None + */ +ret_t dal_rtl8373_ptp_LatchTime_get( rtk_time_timeStamp_t *pLatchTime) +{ + rtk_int32 ret = RT_ERR_OK; + rtk_uint32 sec_l = 0; + rtk_uint32 sec_m = 0; + rtk_uint32 sec_h = 0; + rtk_uint32 nsec_l = 0; + rtk_uint32 nsec_h = 0; + + + if((ret = rtl8373_getAsicReg(RTL8373_PTP_TIME_SEC_RD2_ADDR, &sec_h)) != RT_ERR_OK) + return ret; + if((ret = rtl8373_getAsicReg(RTL8373_PTP_TIME_SEC_RD1_ADDR, &sec_m)) != RT_ERR_OK) + return ret; + if((ret = rtl8373_getAsicReg(RTL8373_PTP_TIME_SEC_RD0_ADDR, &sec_l)) != RT_ERR_OK) + return ret; + if((ret = rtl8373_getAsicReg(RTL8373_PTP_TIME_NSEC_RD1_ADDR, &nsec_h)) != RT_ERR_OK) + return ret; + if((ret = rtl8373_getAsicReg(RTL8373_PTP_TIME_NSEC_RD0_ADDR, &nsec_l)) != RT_ERR_OK) + return ret; + + pLatchTime->sec = ((rtk_uint64)sec_h << 32) | ((rtk_uint64)sec_m << 16) | ((rtk_uint64)sec_l & 0xFFFF); + pLatchTime->nsec = (((nsec_h & 0x3FFF) << 16) | (nsec_l & 0xFFFF)); + + /*to be added phy*/ + + return RT_ERR_OK; +} + + + +/* Function Name: + * dal_rtl8373_ptp_refTime_set + * Description: + * Set the reference time of the specified device. + * Input: + * apply + * timeStamp - reference timestamp value + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT - invalid input parameter + * Applicable: + * Note: + * None + */ +ret_t dal_rtl8373_ptp_refTime_set(rtk_time_timeStamp_t timeStamp, rtk_enable_t apply) +{ + ret_t retVal; + rtk_uint32 sec_h, sec_m,sec_l, nsec8_h, nsec8_l; + rtk_uint32 nano_second_8; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + + if (timeStamp.nsec > RTK_MAX_NUM_OF_NANO_SECOND) + return RT_ERR_INPUT; + + /* adjust Timer for PHYs */ + // retVal = phy_ptpRefTime_set(timeStamp); + + sec_h = (timeStamp.sec>>32)& 0xFFFF; + sec_m = (timeStamp.sec >>16)& 0xFFFF; + sec_l = timeStamp.sec & 0xFFFF; + // nano_second_8 = timeStamp.nsec >> 3; + + nano_second_8 = timeStamp.nsec ; + nsec8_h = (nano_second_8 >>16) & 0x3FFF; + nsec8_l = nano_second_8 &0xFFFF; + + if((retVal = rtl8373_setAsicReg(RTL8373_PTP_TIME_NSEC1_ADDR, nsec8_h)) != RT_ERR_OK) + return retVal; + if((retVal = rtl8373_setAsicReg(RTL8373_PTP_TIME_NSEC0_ADDR, nsec8_l)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8373_setAsicReg(RTL8373_PTP_TIME_SEC2_ADDR, sec_h)) != RT_ERR_OK) + return retVal; + if((retVal = rtl8373_setAsicReg(RTL8373_PTP_TIME_SEC1_ADDR, sec_m)) != RT_ERR_OK) + return retVal; + if((retVal = rtl8373_setAsicReg(RTL8373_PTP_TIME_SEC0_ADDR, sec_l)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8373_setAsicRegBits(RTL8373_PTP_TIME_CRTL_ADDR,RTL8373_PTP_TIME_CRTL_PTP_TIME_CMD_MASK, PTP_TIME_WRITE)) != RT_ERR_OK) + return retVal; + if((retVal = rtl8373_setAsicRegBits(RTL8373_PTP_TIME_NSEC1_ADDR,RTL8373_PTP_TIME_NSEC1_CFG_TOD_VALID_MASK,ENABLED)) != RT_ERR_OK) + return retVal; + if (apply != DISABLED) + { + if((retVal =rtl8373_ptp_execbyreg()) != RT_ERR_OK) + return retVal;; + } + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_ptp_refTime_get + * Description: + * Get the reference time of the specified device by software. + * Input: + * Output: + * pTimeStamp - pointer buffer of the reference time + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Applicable: + * 8371 + * Note: + * None + */ +ret_t dal_rtl8373_ptp_refTime_get(rtk_time_timeStamp_t *pTimeStamp) +{ + ret_t retVal; + rtk_uint32 sec_h, sec_m,sec_l; + rtk_uint32 nsec8_h, nsec8_l; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(pTimeStamp == NULL) + { + return RT_ERR_INPUT; + } + + if((retVal = rtl8373_setAsicRegBits(RTL8373_PTP_TIME_CRTL_ADDR,RTL8373_PTP_TIME_CRTL_PTP_TIME_CMD_MASK, PTP_TIME_READ)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8373_setAsicRegBit(RTL8373_PTP_TIME_CRTL_ADDR,RTL8373_PTP_TIME_CRTL_PTP_TIME_EXEC_OFFSET, 1)) != RT_ERR_OK) + return retVal; + + if((retVal =rtl8373_ptp_execbyreg()) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8373_getAsicReg(RTL8373_PTP_TIME_SEC_RD2_ADDR, &sec_h)) != RT_ERR_OK) + return retVal; + if((retVal = rtl8373_getAsicReg(RTL8373_PTP_TIME_SEC_RD1_ADDR, &sec_m)) != RT_ERR_OK) + return retVal; + if((retVal = rtl8373_getAsicReg(RTL8373_PTP_TIME_SEC_RD0_ADDR, &sec_l)) != RT_ERR_OK) + return retVal; + if((retVal = rtl8373_getAsicReg(RTL8373_PTP_TIME_NSEC_RD1_ADDR, &nsec8_h)) != RT_ERR_OK) + return retVal; + if((retVal = rtl8373_getAsicReg(RTL8373_PTP_TIME_NSEC_RD0_ADDR, &nsec8_l)) != RT_ERR_OK) + return retVal; + + pTimeStamp->sec= ((rtk_uint64)sec_h<<32) | ((rtk_uint64)sec_m<<16) |(rtk_uint64)sec_l; + // nano_second_8 = (nsec8_h<<16) | nsec8_l; + // pTimeStamp->nsec= nano_second_8<<3; + + pTimeStamp->nsec= (nsec8_h<<16) | nsec8_l; + +/*to be added*/ + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_ptp_refTimeAdjust_set + * Description: + * Adjust the reference time. + * Input: + * sign - significant + * timeStamp - reference timestamp value + * apply + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Note: + * sign=0 for positive adjustment, sign=1 for negative adjustment. + */ + ret_t dal_rtl8373_ptp_refTimeAdjust_set( rtk_ptp_sys_adjust_t sign, rtk_time_timeStamp_t timeStamp, rtk_enable_t apply) +{ + ret_t retVal=0; + rtk_uint32 sec_h, sec_m,sec_l, nsec8_h, nsec8_l,nsec; + rtk_uint64 sec; + + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (timeStamp.nsec > DAL_RTL8373_MAX_NUM_OF_NANO_SECOND) + return RT_ERR_INPUT; + + if (sign >= SYS_ADJUST_END) + return RT_ERR_INPUT; + + if (sign == SYS_ADJUST_MINUS) + { + sec = timeStamp.sec; + nsec= timeStamp.nsec; + } + else + { + /* adjust Timer of PHY */ + sec = 0 - (timeStamp.sec + 1); + nsec = 1000000000 - timeStamp.nsec; + } + + sec_h = (rtk_uint32)(sec >>32)& 0xFFFF; + sec_m = (rtk_uint32)(sec >>16)& 0xFFFF; + sec_l = sec & 0xFFFF; + nsec8_h = (nsec >>16) & 0xFFFF; + nsec8_l = nsec &0xFFFF; + + if((retVal = rtl8373_setAsicReg(RTL8373_PTP_TIME_SEC2_ADDR, sec_h)) != RT_ERR_OK) + return retVal; + if((retVal = rtl8373_setAsicReg(RTL8373_PTP_TIME_SEC1_ADDR, sec_m)) != RT_ERR_OK) + return retVal; + if((retVal = rtl8373_setAsicReg(RTL8373_PTP_TIME_SEC0_ADDR, sec_l)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8373_setAsicReg(RTL8373_PTP_TIME_NSEC1_ADDR, nsec8_h)) != RT_ERR_OK) + return retVal; + if((retVal = rtl8373_setAsicReg(RTL8373_PTP_TIME_NSEC0_ADDR, nsec8_l)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8373_setAsicRegBits(RTL8373_PTP_TIME_CRTL_ADDR,RTL8373_PTP_TIME_CRTL_PTP_TIME_CMD_MASK, PTP_TIME_ADJUST)) != RT_ERR_OK) + return retVal; + if (apply != DISABLED) + { + if((retVal =rtl8373_ptp_execbyreg()) != RT_ERR_OK) + return retVal; + } + + return RT_ERR_OK; + +} + +/* Function Name: + * dal_rtl8373_ptp_TxTimestampFifo_get + * Description: + * Get the top entry from PTP Tx timstamp FIFO on the dedicated port from the specified device. + * Input: + * Output: + * pTimeEntry - pointer buffer of TIME timestamp entry + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None + */ +ret_t dal_rtl8373_ptp_TxTimestampFifo_get(rtk_time_txTimeEntry_t *pTimeEntry) +{ + ret_t retVal = RT_ERR_OK; + rtk_uint32 reg_val = 0; + rtk_uint32 sec_l = 0; + rtk_uint32 sec_m = 0; + rtk_uint32 sec_h = 0; + rtk_uint32 regData,count,busyFlag; + + if((retVal = rtl8373_getAsicReg(RTL8373_PTP_TX_TIMESTAMP_RD0_ADDR,®_val)) != RT_ERR_OK) + return retVal; + + pTimeEntry->valid = (reg_val & RTL8373_PTP_TX_TIMESTAMP_RD0_RD_TX_TIMESTAMP_VALID_MASK)? 1:0; + pTimeEntry->port = (reg_val & RTL8373_PTP_TX_TIMESTAMP_RD0_RD_PORT_ID_MASK) >> 8; + pTimeEntry->msg_type = (reg_val & RTL8373_PTP_TX_TIMESTAMP_RD0_RD_MSG_TYPE_MASK) >> 6; + pTimeEntry->seqId = (reg_val & RTL8373_PTP_TX_TIMESTAMP_RD0_RD_SEQ_ID_H_MASK) << 10; + + if((retVal = rtl8373_getAsicReg(RTL8373_PTP_TX_TIMESTAMP_RD1_ADDR,®_val)) != RT_ERR_OK) + return retVal; + + pTimeEntry->seqId |= (reg_val & RTL8373_PTP_TX_TIMESTAMP_RD1_RD_SEQ_ID_L_MASK) >> 6; + pTimeEntry->txTime.sec = (reg_val & RTL8373_PTP_TX_TIMESTAMP_RD1_RD_TX_TIMESTAMP_SEC_H_MASK) << 2; + + if((retVal = rtl8373_getAsicReg(RTL8373_PTP_TX_TIMESTAMP_RD2_ADDR,®_val)) != RT_ERR_OK) + return retVal; + + pTimeEntry->txTime.sec |= (reg_val & RTL8373_PTP_TX_TIMESTAMP_RD2_RD_TX_TIMESTAMP_SEC_L_MASK) >> 14; + pTimeEntry->txTime.nsec = (reg_val & RTL8373_PTP_TX_TIMESTAMP_RD2_RD_TX_TIMESTAMP_NSEC_H_MASK) << 16; + + if((retVal = rtl8373_getAsicReg(RTL8373_PTP_TX_TIMESTAMP_RD3_ADDR,®_val)) != RT_ERR_OK) + return retVal; + + pTimeEntry->txTime.nsec |= (reg_val & RTL8373_PTP_TX_TIMESTAMP_RD3_RD_TX_TIMESTAMP_NSEC_L_MASK); + + // rtl8373_getAsicEavSysTime(&Sec,&NanoSec);/* 8 bits sec is not overflow yet */ + + regData = (PTP_TIME_READ<=pTimeEntry->txTime.sec) + { + pTimeEntry->txTime.sec |= ((rtk_uint64)sec_h << 32) | ((rtk_uint64)sec_m << 16) | ((rtk_uint64)sec_l & 0xFF00); + } + else + { + pTimeEntry->txTime.sec |= ((rtk_uint64)sec_h << 32) | ((rtk_uint64)sec_m << 16) | ((rtk_uint64)sec_l & 0xFF00); + pTimeEntry->txTime.sec -= 0x100; + } + + + /*to be added phy*/ + + return RT_ERR_OK; +} + + + + + +/* Function Name: + * dal_rtl8373_ptp_1PPSOutput_get + * Description: + * Get 1 PPS output configuration of the specified port. + * Input: + * Output: + * pPulseWidth - pointer to 1 PPS pulse width, unit: 10 ms + * pEnable - pointer to 1 PPS output enable status + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None + */ +ret_t dal_rtl8373_ptp_1PPSOutput_get( rtk_uint32 *pPulseWidth, rtk_enable_t *pEnable) +{ + ret_t ret = RT_ERR_OK; + rtk_uint32 reg_val = 0; + + ret=rtl8373_getAsicReg(RTL8373_PTP_PPS_CTRL_ADDR,®_val); + if(ret!=RT_ERR_OK) + return ret; + + if (reg_val & RTL8373_PTP_PPS_CTRL_CFG_PPS_EN_MASK) + *pEnable = ENABLED; + else + *pEnable = DISABLED; + + *pPulseWidth = reg_val & RTL8373_PTP_PPS_CTRL_CFG_PPS_WIDTH_MASK; + + /*to be added phy*/ + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_ptp_1PPSOutput_set + * Description: + * Set 1 PPS output configuration of the specified port. + * Input: + * pulseWidth - pointer to 1 PPS pulse width, unit: 10 ms + * enable - enable 1 PPS output + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * Note: + * None + */ +ret_t dal_rtl8373_ptp_1PPSOutput_set( rtk_uint32 pulseWidth, rtk_enable_t enable) +{ + ret_t ret = RT_ERR_OK; + rtk_uint32 reg_val = 0; + + if (pulseWidth > RTL8373_MAX_PPS_WIDTH) + return RT_ERR_OUT_OF_RANGE; + + reg_val = (enable << RTL8373_PTP_PPS_CTRL_CFG_PPS_EN_OFFSET) | (pulseWidth); + ret=rtl8373_setAsicReg(RTL8373_PTP_PPS_CTRL_ADDR,reg_val); + if(ret!=RT_ERR_OK) + return ret; + /*to be added*/ + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_ptp_ClockOutput_get + * Description: + * Get clock output configuration of the specified port. + * Input: + * pClkOutput -pClkOutput + * Output: + * pClkOutput - pointer to clock output configuration + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None + */ +ret_t dal_rtl8373_ptp_ClockOutput_get( rtk_time_clkOutput_t *pClkOutput) +{ + ret_t ret = RT_ERR_OK; + rtk_uint32 reg_val = 0; + rtk_uint32 sec_l = 0; + rtk_uint32 sec_m = 0; + rtk_uint32 sec_h = 0; + rtk_uint32 nsec_l = 0; + rtk_uint32 nsec_h = 0; + + ret=rtl8373_getAsicReg(RTL8373_PTP_CLKOUT_SEC0_ADDR, &sec_l); + if(ret!=RT_ERR_OK) + return ret; + ret=rtl8373_getAsicReg(RTL8373_PTP_CLKOUT_SEC1_ADDR, &sec_m); + if(ret!=RT_ERR_OK) + return ret; + ret=rtl8373_getAsicReg(RTL8373_PTP_CLKOUT_SEC2_ADDR, &sec_h); + if(ret!=RT_ERR_OK) + return ret; + ret=rtl8373_getAsicReg(RTL8373_PTP_CLKOUT_NSEC0_ADDR, &nsec_l); + if(ret!=RT_ERR_OK) + return ret; + ret=rtl8373_getAsicReg(RTL8373_PTP_CLKOUT_NSEC1_ADDR, &nsec_h); + if(ret!=RT_ERR_OK) + return ret; + pClkOutput->startTime.sec = ((rtk_uint64)sec_h << 32) | ((rtk_uint64)sec_m << 16) | ((rtk_uint64)sec_l & 0xFFFF); + pClkOutput->startTime.nsec = (((nsec_h & 0x3FFF) << 16) | (nsec_l & 0xFFFF)); + + ret=rtl8373_getAsicReg(RTL8373_PTP_CLKOUT_CTRL_ADDR, ®_val); + if(ret!=RT_ERR_OK) + return ret; + if (reg_val & RTL8373_PTP_CLKOUT_CTRL_CFG_PULSE_MODE_MASK) + pClkOutput->mode = PTP_CLK_OUT_PULSE; + else + pClkOutput->mode = PTP_CLK_OUT_REPEAT; + + if (reg_val & RTL8373_PTP_CLKOUT_CTRL_CFG_CLKOUT_EN_MASK) + pClkOutput->enable = ENABLED; + else + pClkOutput->enable = DISABLED; + + if (reg_val & RTL8373_PTP_CLKOUT_CTRL_RD_CLKOUT_RUN_MASK) + pClkOutput->runing = TRUE; + else + pClkOutput->runing = FALSE; + + ret=rtl8373_getAsicReg(RTL8373_PTP_CLKOUT_HALF_PERD_NS_L_ADDR, &nsec_l); + if(ret!=RT_ERR_OK) + return ret; + ret=rtl8373_getAsicReg(RTL8373_PTP_CLKOUT_HALF_PERD_NS_H_ADDR, &nsec_h); + if(ret!=RT_ERR_OK) + return ret; + pClkOutput->halfPeriodNsec = (((nsec_h & 0x3FFF) << 16) | (nsec_l & 0xFFFF)); + + /*to be added phy*/ + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_ptp_ClockOutput_set + * Description: + * Set 1 PPS output configuration of the specified port. + * Input: +* type - phy or mac + * pClkOutput - pointer to clock output configuration + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * Note: + * None + */ +ret_t dal_rtl8373_ptp_ClockOutput_set( rtk_time_clkOutput_t pClkOutput) +{ + ret_t ret = RT_ERR_OK; + rtk_uint32 reg_val = 0; + rtk_uint32 sec_l = 0; + rtk_uint32 sec_m = 0; + rtk_uint32 sec_h = 0; + rtk_uint32 nsec_l = 0; + rtk_uint32 nsec_h = 0; + + /* adjust Timer of PHY */ + sec_l = (pClkOutput.startTime.sec) & 0xFFFF; + sec_m = ((pClkOutput.startTime.sec) >> 16) & 0xFFFF; + sec_h = ((pClkOutput.startTime.sec) >> 32) & 0xFFFF; + /* convert nsec to 8nsec */ + nsec_l = pClkOutput.startTime.nsec & 0xFFFF; + nsec_h = pClkOutput.startTime.nsec >> 16; + + ret=rtl8373_setAsicReg(RTL8373_PTP_CLKOUT_SEC0_ADDR, sec_l); + if(ret!=RT_ERR_OK) + return ret; + ret=rtl8373_setAsicReg(RTL8373_PTP_CLKOUT_SEC1_ADDR, sec_m); + if(ret!=RT_ERR_OK) + return ret; + ret=rtl8373_setAsicReg(RTL8373_PTP_CLKOUT_SEC2_ADDR, sec_h); + if(ret!=RT_ERR_OK) + return ret; + ret=rtl8373_setAsicReg(RTL8373_PTP_CLKOUT_NSEC0_ADDR, nsec_l); + if(ret!=RT_ERR_OK) + return ret; + ret=rtl8373_setAsicReg(RTL8373_PTP_CLKOUT_NSEC1_ADDR, nsec_h); + if(ret!=RT_ERR_OK) + return ret; + + nsec_l = pClkOutput.halfPeriodNsec & 0xFFFF; + nsec_h = pClkOutput.halfPeriodNsec >> 16; + + ret=rtl8373_setAsicReg(RTL8373_PTP_CLKOUT_HALF_PERD_NS_L_ADDR, nsec_l); + if(ret!=RT_ERR_OK) + return ret; + ret=rtl8373_setAsicReg(RTL8373_PTP_CLKOUT_HALF_PERD_NS_H_ADDR, nsec_h); + if(ret!=RT_ERR_OK) + return ret; + + reg_val = (pClkOutput.mode << RTL8373_PTP_CLKOUT_CTRL_CFG_PULSE_MODE_OFFSET) | (pClkOutput.enable << RTL8373_PTP_CLKOUT_CTRL_CFG_CLKOUT_EN_OFFSET); + + ret=rtl8373_setAsicReg(RTL8373_PTP_CLKOUT_CTRL_ADDR, reg_val); + if(ret!=RT_ERR_OK) + return ret; + + return RT_ERR_OK; + +} + +/* Function Name: + * dal_rtl8373_ptp_portctrl_set + * Description: + * Get enable status for PTP transparent clock of the specified port. + * Input: + * port - port id + * portcfg -port role/udp_en/eth_en/always_ts + * Output: + * + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None + */ +ret_t dal_rtl8373_ptp_portctrl_set( rtk_port_t port, rtk_ptp_port_ctrl_t portcfg) +{ + ret_t retVal = RT_ERR_OK; + rtk_uint32 link_delay_l,link_delay_h; + + if ((1<>10) & 0xFFFF; + + if((retVal = rtl8373_setAsicRegBits(RTL8373_P0_LINK_DELAY_H_ADDR(rtk_switch_port_L2Ptpport_get(port)), RTL8373_P0_LINK_DELAY_H_P0_CFG_LINK_DELAY_H_MASK,link_delay_h)) != RT_ERR_OK) + return retVal; + if((retVal = rtl8373_setAsicRegBits(RTL8373_P0_PORT_CTRL_ADDR(rtk_switch_port_L2Ptpport_get(port)), RTL8373_P0_PORT_CTRL_P0_CFG_LINK_DELAY_L_MASK,link_delay_l)) != RT_ERR_OK) + return retVal; + } + else + { + /*to be added*/ + } + return retVal; +} + + +/* Function Name: + * dal_rtl8373_ptp_TransEnable_get + * Description: + * Get enable status for PTP transparent clock of the specified port. + * Input: + * port - port id + * Output: + * portcfg -port role/udp_en/eth_en/always_ts + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None + */ +ret_t dal_rtl8373_ptp_portctrl_get( rtk_port_t port, rtk_ptp_port_ctrl_t *pportcfg) +{ + ret_t retVal = RT_ERR_OK; + rtk_uint32 link_delay_l=0; + rtk_uint32 link_delay_h=0; + rtk_uint32 portrole = 0; + rtk_uint32 udp_en = 0; + rtk_uint32 eth_en = 0; + rtk_uint32 always_ts_en = 0; + + if(pportcfg==NULL) + return RT_ERR_INPUT; + + if ((1<always_ts_en=always_ts_en; + pportcfg->eth_en=eth_en; + pportcfg->udp_en=udp_en; + pportcfg->link_delay=link_delay_l|(link_delay_h<<10); + pportcfg->portrole=portrole; + } + else + { + /*to be added*/ + } + return retVal; +} + + + +/* Function Name: + * dal_rtl8373_ptp_TransEnable_set + * Description: + * Set TX/RX timer value compensation.. + * Input: + * port - port id + * TxImbal - TX timer value compensation + * RxImbal - RX timer value compensation + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * Note: + * unit: 1 ns + */ +ret_t dal_rtl8373_ptp_TxImbal_set(rtk_port_t port, rtk_uint32 TxImbal,rtk_uint32 RxImbal) +{ + ret_t ret = RT_ERR_OK; + + if ((1<sec = ((rtk_uint64)sec_h << 32) | ((rtk_uint64)sec_m << 16) | ((rtk_uint64)sec_l & 0xFFFF); + pLatchTime->nsec = (((nsec_h & 0x3FFF) << 16) | (nsec_l & 0xFFFF)); + + + return ret; +} +/* Function Name: + * dal_rtl8373_ptp_RefTimeFreqCfg_set + * Description: + * Set the frequency of reference time of PHY of the specified port. + * Input: + * freq - reference time frequency + * apply + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * Note: + * The frequency configuration decides the reference time tick frequency. + * The default value is 0x10000000. + * If it is configured to 0x8000000, the tick frequency would be half of default. + * If it is configured to 0x20000000, the tick frequency would be one and half times of default. + */ +ret_t dal_rtl8373_ptp_RefTimeFreqCfg_set(rtk_uint32 freq, rtk_enable_t apply) +{ + ret_t ret; + rtk_int32 retVal; + rtk_uint32 busyFlag, count; + + if((ret = rtl8373_setAsicRegBits(RTL8373_PTP_TIME_FREQ0_ADDR,RTL8373_PTP_TIME_FREQ0_CFG_PTP_TIME_FREQ0_MASK, freq&0xffff)) != RT_ERR_OK) + return ret; + + if((ret = rtl8373_setAsicRegBits(RTL8373_PTP_TIME_FREQ1_ADDR,RTL8373_PTP_TIME_FREQ1_CFG_PTP_TIME_FREQ1_MASK, (freq>>16)&0xffff)) != RT_ERR_OK) + return ret; + + if((ret = rtl8373_setAsicRegBits(RTL8373_PTP_APPLY_FREQ_ADDR,RTL8373_PTP_APPLY_FREQ_APPLY_FREQ_MASK, apply)) != RT_ERR_OK) + return ret; + + + count = 0; + do { + if((retVal = rtl8373_getAsicRegBit(RTL8373_PTP_APPLY_FREQ_ADDR, RTL8373_PTP_APPLY_FREQ_APPLY_FREQ_OFFSET, &busyFlag)) != RT_ERR_OK) + return retVal; + count++; + } while ((busyFlag != 0)&&(count<5)); + + + if (busyFlag != 0) + return RT_ERR_BUSYWAIT_TIMEOUT; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_ptp_RefTimeFreqCfg_get + * Description: + * Set ptp_RefTimeFreqCfg_get. + * Input: + * None + * Output: + * cfgFreq + * curFreq + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * Note: + */ +ret_t dal_rtl8373_ptp_RefTimeFreqCfg_get(rtk_uint32 *cfgFreq,rtk_uint32 *curFreq) +{ + rtk_uint32 freqtmp; + + + rtl8373_getAsicRegBits(RTL8373_PTP_TIME_FREQ0_ADDR,RTL8373_PTP_TIME_FREQ0_CFG_PTP_TIME_FREQ0_MASK, cfgFreq); + rtl8373_getAsicRegBits(RTL8373_PTP_TIME_FREQ1_ADDR,RTL8373_PTP_TIME_FREQ1_CFG_PTP_TIME_FREQ1_MASK, &freqtmp); + *cfgFreq|=(freqtmp<<16); + + rtl8373_getAsicRegBits(RTL8373_PTP_CUR_TIME_FREQ0_ADDR,RTL8373_PTP_CUR_TIME_FREQ0_CUR_PTP_TIME_FREQ0_MASK, curFreq); + rtl8373_getAsicRegBits(RTL8373_PTP_CUR_TIME_FREQ1_ADDR,RTL8373_PTP_CUR_TIME_FREQ1_CUR_PTP_TIME_FREQ1_MASK, &freqtmp); + *curFreq|=(freqtmp<<16); + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_ptp_ClkSrcCtrl_set + * Description: + * Set PTP time Clock source selection + * Input: + * clksrc + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * 0: internal clock (Internal PLL, 1GMHz) + * 1: external clock, refer to cfg_ext_clk_src) + */ +ret_t dal_rtl8373_ptp_ClkSrcCtrl_set(rtk_enable_t clksrc) +{ + ret_t retVal=RT_ERR_OK; + if (clksrc>1) + return RT_ERR_INPUT; + + retVal=rtl8373_setAsicRegBit(RTL8373_PTP_CLK_SRC_CTRL_ADDR, RTL8373_PTP_CLK_SRC_CTRL_CFG_CLK_SRC_OFFSET, clksrc); + return retVal; +} + +/* Function Name: + * dal_rtl8373_ptp_ClkSrcCtrl_get + * Description: + * Get PTP time Clock source selection + * Input: + * clksrc + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * 0: internal clock (Internal PLL, 1GMHz) + * 1: external clock, refer to cfg_ext_clk_src) + */ +ret_t dal_rtl8373_ptp_ClkSrcCtrl_get(rtk_enable_t *clksrc) +{ + ret_t retVal=RT_ERR_OK; + if (clksrc == NULL) + return RT_ERR_INPUT; + + retVal=rtl8373_getAsicRegBit(RTL8373_PTP_CLK_SRC_CTRL_ADDR, RTL8373_PTP_CLK_SRC_CTRL_CFG_CLK_SRC_OFFSET, clksrc); + return retVal; +} +/* Function Name: + * dal_rtl8373_ptp_intControl_set + * Description: + * Set PTP interrupt trigger status configuration. + * Input: + * type - Interrupt type. + * enable - Interrupt status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * The API can set PTP interrupt status configuration. + * The interrupt trigger status is shown in the following: + * PTP_INT_TYPE_1PPS = 0, + * PTP_INT_TYPE_TOD_DONE, + * PTP_INT_TYPE_TXTIME_EMPTY + */ +ret_t dal_rtl8373_ptp_intControl_set(rtk_ptp_intType_t type, rtk_enable_t enable) +{ + ret_t retVal; + rtk_uint32 mask; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (type>=PTP_INT_TYPE_END) + return RT_ERR_INPUT; + + if ((retVal = rtl8373_getAsicEavInterruptMask(&mask)) != RT_ERR_OK) + return retVal; + + if (ENABLED == enable) + mask|=(1< +#include +#include +#include + +#include + +/* Function Name: + * dal_rtl8373_qos_init + * Description: + * Configure Qos default settings. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will initialize related Qos setting. + */ +rtk_api_ret_t dal_rtl8373_qos_init(void) +{ + CONST_T rtk_uint16 g_prioritytToQid[8]= {0, 1,2,3,4,5,6,7}; + CONST_T rtk_uint32 g_priorityDecision[6] = {0x01, 0x10,0x04,0x02,0x08,0x20}; + CONST_T rtk_uint32 g_prioritytRemap[8] = {0,1,2,3,4,5,6,7}; + + rtk_api_ret_t retVal; + rtk_uint32 priority; + rtk_uint32 priDec; + rtk_uint32 priIdx; + rtk_uint32 port; + rtk_uint32 dscp; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /*Set Priority to Qid per port*/ + for (port = 0; port < RTL8373_PORTNO; port++) + { + for(priority = 0; priority <=RTK_PRIMAX; priority++) + { + if ((retVal = rtl8373_setAsicRegBits(RTL8373_QID_TO_PRI_ADDR(port), 0x7 << (priority * 4), g_prioritytToQid[priority])) != RT_ERR_OK) + return retVal; + } + } + + /*Priority Decision Order*/ + for(priIdx = 0; priIdx < RTL8373_PRIIDX_END; priIdx++) + { + for (priDec = 0;priDec < RTL8373_PRIDEC_END;priDec++) + { + if ((retVal = rtl8373_setAsicRegBits(RTL8373_PRI_WEIGHT_ADDR(priIdx), 0x1f << (priDec * 5), g_priorityDecision[priDec])) != RT_ERR_OK) + return retVal; + } + } + + /*Set per port weight select*/ + for(port = 0; port < RTL8373_PORTNO; port++) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_PORT_WEIGHT_SEL_ADDR (port),RTL8373_PORT_WEIGHT_SEL_WEIGHT_SEL_OFFSET(port), 0)) != RT_ERR_OK) + return retVal; + } + + /*Set Port-based Priority to 0*/ + RTK_SCAN_ALL_PHY_PORTMASK(port) + { + if ((retVal = rtl8373_setAsicRegBits(RTL8373_PORT_PRI_ADDR (port),RTL8373_PORT_PRI_PORT_BASE_PRI_MASK(port), 0)) != RT_ERR_OK) + return retVal; + } + + RTK_SCAN_ALL_PHY_PORTMASK(port) + { + /*Disable 1p Remarking*/ + if ((retVal = rtl8373_setAsicRegBit(RTL8373_RMK_PORT_CTRL_ADDR(port), RTL8373_RMK_PORT_CTRL_IPRI_RMK_EN_OFFSET, DISABLED)) != RT_ERR_OK) + return retVal; + /*Disable DSCP Remarking*/ + if ((retVal = rtl8373_setAsicRegBit(RTL8373_RMK_PORT_CTRL_ADDR(port), RTL8373_RMK_PORT_CTRL_DSCP_RMK_EN_OFFSET, DISABLED)) != RT_ERR_OK) + return retVal; + } + + /*Set 1p & DSCP Priority Remapping & Remarking*/ + for (priority = 0; priority <= RTK_PRIMAX; priority++) + { + if ((retVal = rtl8373_setAsicRegBits(RTL8373_DOT1Q_PRI_REMAP_ADDR, 0x7<< (priority * 4), g_prioritytRemap[priority])) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_setAsicRegBit(RTL8373_RMK_CTRL_ADDR ,RTL8373_RMK_CTRL_IPRI_RMK_SRC_OFFSET, 0))!= RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_setAsicRegBit(RTL8373_RMK_CTRL_ADDR,RTL8373_RMK_CTRL_DSCP_RMK_SRC_OFFSET, 0)) != RT_ERR_OK) + return retVal; + + /*set RSPAN Priority Remapping*/ + if ((retVal = rtl8373_setAsicRegBits(RTL8373_RSPAN_PRI_REMAP_ADDR, 0x7<< (priority * 4), g_prioritytRemap[priority])) != RT_ERR_OK) + return retVal; + } + + /*Set DSCP Priority*/ + for (dscp = 0; dscp <= 63; dscp++) + { + if ((retVal = rtl8373_setAsicRegBits(RTL8373_PRI_SEL_REMAP_DSCP_ADDR(dscp),RTL8373_PRI_SEL_REMAP_DSCP_INTPRI_DSCP_MASK(dscp), 0)) != RT_ERR_OK) + return retVal; + } + + /* Finetune B/T value */ + // if((retVal = rtl8373_setAsicReg(0x1722, 0x1158)) != RT_ERR_OK) + // return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_qos_priSel_set + * Description: + * Configure the priority order among different priority mechanism. + * Input: + * index - Priority decision table index (0~1) + * pPriDec - Priority assign for port, dscp, 802.1p, svlan, acl based priority decision. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_SEL_PRI_SOURCE - Invalid priority decision source parameter. + * Note: + * ASIC will follow user priority setting of mechanisms to select mapped queue priority for receiving frame. + * If two priority mechanisms are the same, the ASIC will chose the highest priority from mechanisms to + * assign queue priority to receiving frame. + * The priority sources are: + * - RTL8373_PRIDEC_PORT + * - RTL8373_PRIDEC_ACL + * - RTL8373_PRIDEC_DSCP + * - RTL8373_PRIDEC_1Q + * - RTL8373_PRIDEC_SVLAN + */ +rtk_api_ret_t dal_rtl8373_qos_priSel_set(rtk_qos_priDecTbl_t index, rtk_priority_select_t *pPriDec) +{ + rtk_api_ret_t retVal; + rtk_uint32 port_pow; + rtk_uint32 dot1q_pow; + rtk_uint32 dscp_pow; + rtk_uint32 acl_pow; + rtk_uint32 svlan_pow; + rtk_uint32 i; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (index < 0 || index >= PRIDECTBL_END) + return RT_ERR_ENTRY_INDEX; + + if (pPriDec->port_pri >= 5 || pPriDec->dot1q_pri >= 5 || pPriDec->acl_pri >= 5 || pPriDec->dscp_pri >= 5 || + pPriDec->svlan_pri >= 5) + return RT_ERR_QOS_SEL_PRI_SOURCE; + + port_pow = 1; + for (i = pPriDec->port_pri; i > 0; i--) + port_pow = (port_pow)*2; + + dot1q_pow = 1; + for (i = pPriDec->dot1q_pri; i > 0; i--) + dot1q_pow = (dot1q_pow)*2; + + acl_pow = 1; + for (i = pPriDec->acl_pri; i > 0; i--) + acl_pow = (acl_pow)*2; + + dscp_pow = 1; + for (i = pPriDec->dscp_pri; i > 0; i--) + dscp_pow = (dscp_pow)*2; + + svlan_pow = 1; + for (i = pPriDec->svlan_pri; i > 0; i--) + svlan_pow = (svlan_pow)*2; + + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_PRI_WEIGHT_ADDR(index), RTL8373_PRI_WEIGHT_PORT_WEIGHT_MASK, port_pow)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_PRI_WEIGHT_ADDR(index), RTL8373_PRI_WEIGHT_DOT1Q_WEIGHT_MASK, dot1q_pow)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_PRI_WEIGHT_ADDR(index), RTL8373_PRI_WEIGHT_DSCP_WEIGHT_MASK, dscp_pow)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_PRI_WEIGHT_ADDR(index), RTL8373_PRI_WEIGHT_ACL_WEIGHT_MASK, acl_pow)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_PRI_WEIGHT_ADDR(index), RTL8373_PRI_WEIGHT_SVLAN_WEIGHT_MASK, svlan_pow)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_qos_priSel_get + * Description: + * Get the priority order configuration among different priority mechanism. + * Input: + * index - Priority decision table index (0~1) + * Output: + * pPriDec - Priority assign for port, dscp, 802.1p, svlan, acl based priority decision . + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * ASIC will follow user priority setting of mechanisms to select mapped queue priority for receiving frame. + * If two priority mechanisms are the same, the ASIC will chose the highest priority from mechanisms to + * assign queue priority to receiving frame. + * The priority sources are: + * - RTL8373_PRIDEC_PORT + * - RTL8373_PRIDEC_ACL + * - RTL8373_PRIDEC_DSCP + * - RTL8373_PRIDEC_1Q + * - RTL8373_PRIDEC_SVLAN + */ +rtk_api_ret_t dal_rtl8373_qos_priSel_get(rtk_qos_priDecTbl_t index, rtk_priority_select_t *pPriDec) +{ + + rtk_api_ret_t retVal; + rtk_int32 i; + rtk_uint32 port_pow; + rtk_uint32 dot1q_pow; + rtk_uint32 dscp_pow; + rtk_uint32 acl_pow; + rtk_uint32 svlan_pow; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (index < 0 || index >= PRIDECTBL_END) + return RT_ERR_ENTRY_INDEX; + + memset(pPriDec, 0x00, sizeof(rtk_priority_select_t)); + + if ((retVal = rtl8373_getAsicRegBits(RTL8373_PRI_WEIGHT_ADDR(index), RTL8373_PRI_WEIGHT_PORT_WEIGHT_MASK, &port_pow)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_getAsicRegBits(RTL8373_PRI_WEIGHT_ADDR(index), RTL8373_PRI_WEIGHT_DOT1Q_WEIGHT_MASK, &dot1q_pow)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_getAsicRegBits(RTL8373_PRI_WEIGHT_ADDR(index), RTL8373_PRI_WEIGHT_DSCP_WEIGHT_MASK, &dscp_pow)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_getAsicRegBits(RTL8373_PRI_WEIGHT_ADDR(index), RTL8373_PRI_WEIGHT_ACL_WEIGHT_MASK, &acl_pow)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_getAsicRegBits(RTL8373_PRI_WEIGHT_ADDR(index), RTL8373_PRI_WEIGHT_SVLAN_WEIGHT_MASK, &svlan_pow)) != RT_ERR_OK) + return retVal; + + for (i = 31; i >= 0; i--) + { + if (port_pow & (1 << i)) + { + pPriDec->port_pri = i; + break; + } + } + + for (i = 31; i >= 0; i--) + { + if (dot1q_pow & (1 << i)) + { + pPriDec->dot1q_pri = i; + break; + } + } + + for (i = 31; i >= 0; i--) + { + if (acl_pow & (1 << i)) + { + pPriDec->acl_pri = i; + break; + } + } + + for (i = 31; i >= 0; i--) + { + if (dscp_pow & (1 << i)) + { + pPriDec->dscp_pri = i; + break; + } + } + + for (i = 31; i >= 0; i--) + { + if (svlan_pow & (1 << i)) + { + pPriDec->svlan_pri = i; + break; + } + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_qos_1pPriRemap_set + * Description: + * Configure 1Q priorities mapping to internal absolute priority. + * Input: + * dot1p_pri - 802.1p priority value. + * int_pri - internal priority value. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_VLAN_PRIORITY - Invalid 1p priority. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * Priority of 802.1Q assignment for internal asic priority, and it is used for queue usage and packet scheduling. + */ +rtk_api_ret_t dal_rtl8373_qos_1pPriRemap_set(rtk_pri_t dot1p_pri, rtk_pri_t int_pri) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (dot1p_pri > RTL8373_PRIMAX || int_pri > RTL8373_PRIMAX) + return RT_ERR_VLAN_PRIORITY; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_DOT1Q_PRI_REMAP_ADDR, 0x7<< (dot1p_pri * 4), int_pri)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_qos_1pPriRemap_get + * Description: + * Get 1Q priorities mapping to internal absolute priority. + * Input: + * dot1p_pri - 802.1p priority value . + * Output: + * pInt_pri - internal priority value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_VLAN_PRIORITY - Invalid priority. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * Priority of 802.1Q assigment for internal asic priority, and it is uesed for queue usage and packet scheduling. + */ +rtk_api_ret_t dal_rtl8373_qos_1pPriRemap_get(rtk_pri_t dot1p_pri, rtk_pri_t *pInt_pri) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (dot1p_pri > RTL8373_PRIMAX) + return RT_ERR_QOS_INT_PRIORITY; + + if ((retVal = rtl8373_getAsicRegBits(RTL8373_DOT1Q_PRI_REMAP_ADDR, 0x7<< (dot1p_pri * 4), pInt_pri)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_qos_dscpPriRemap_set + * Description: + * Map dscp value to internal priority. + * Input: + * dscp - Dscp value of receiving frame + * int_pri - internal priority value . + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_QOS_DSCP_VALUE - Invalid DSCP value. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * The Differentiated Service Code Point is a selector for router's per-hop behaviors. As a selector, there is no implication that a numerically + * greater DSCP implies a better network service. As can be seen, the DSCP totally overlaps the old precedence field of TOS. So if values of + * DSCP are carefully chosen then backward compatibility can be achieved. + */ +rtk_api_ret_t dal_rtl8373_qos_dscpPriRemap_set(rtk_dscp_t dscp, rtk_pri_t int_pri) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (int_pri > RTL8373_PRIMAX ) + return RT_ERR_QOS_INT_PRIORITY; + + if (dscp > RTL8373_DSCPMAX) + return RT_ERR_QOS_DSCP_VALUE; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_PRI_SEL_REMAP_DSCP_ADDR(dscp), RTL8373_PRI_SEL_REMAP_DSCP_INTPRI_DSCP_MASK(dscp),int_pri)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_qos_dscpPriRemap_get + * Description: + * Get dscp value to internal priority. + * Input: + * dscp - Dscp value of receiving frame + * Output: + * pInt_pri - internal priority value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_DSCP_VALUE - Invalid DSCP value. + * Note: + * The Differentiated Service Code Point is a selector for router's per-hop behaviors. As a selector, there is no implication that a numerically + * greater DSCP implies a better network service. As can be seen, the DSCP totally overlaps the old precedence field of TOS. So if values of + * DSCP are carefully chosen then backward compatibility can be achieved. + */ +rtk_api_ret_t dal_rtl8373_qos_dscpPriRemap_get(rtk_dscp_t dscp, rtk_pri_t *pInt_pri) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (dscp > RTL8373_DSCPMAX) + return RT_ERR_QOS_DSCP_VALUE; + + if ((retVal = rtl8373_getAsicRegBits(RTL8373_PRI_SEL_REMAP_DSCP_ADDR(dscp),RTL8373_PRI_SEL_REMAP_DSCP_INTPRI_DSCP_MASK(dscp), pInt_pri)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_qos_RspanPriRemap_set + * Description: + * Configure RSPAN priorities mapping to internal absolute priority. + * Input: + * rspan_pri - rspan priority value. + * int_pri - internal priority value. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_VLAN_PRIORITY - Invalid 1p priority. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * Priority of RSPAN assignment for internal asic priority, and it is used for queue usage and packet scheduling. + */ +rtk_api_ret_t dal_rtl8373_qos_RspanPriRemap_set(rtk_pri_t rspan_pri, rtk_pri_t int_pri) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (rspan_pri > RTL8373_PRIMAX || int_pri > RTL8373_PRIMAX) + return RT_ERR_VLAN_PRIORITY; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_RSPAN_PRI_REMAP_ADDR, 0x7<< (rspan_pri * 4), int_pri)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_qos_RspanPriRemap_get + * Description: + * Get RSPAN priorities mapping to internal absolute priority. + * Input: + * rspan_pri - rspan priority value. + * Output: + * pInt_pri - internal priority value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_VLAN_PRIORITY - Invalid priority. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * Priority of RSPAN assigment for internal asic priority, and it is uesed for queue usage and packet scheduling. + */ +rtk_api_ret_t dal_rtl8373_qos_RspanPriRemap_get(rtk_pri_t rspan_pri, rtk_pri_t *pInt_pri) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (rspan_pri > RTL8373_PRIMAX) + return RT_ERR_QOS_INT_PRIORITY; + + if ((retVal = rtl8373_getAsicRegBits(RTL8373_RSPAN_PRI_REMAP_ADDR, 0x7<< (rspan_pri * 4), pInt_pri)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_qos_portPri_set + * Description: + * Configure priority usage to each port. + * Input: + * port - Port id. + * int_pri - internal priority value. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_QOS_SEL_PORT_PRI - Invalid port priority. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * The API can set priority of port assignments for queue usage and packet scheduling. + */ +rtk_api_ret_t dal_rtl8373_qos_portPri_set(rtk_port_t port, rtk_pri_t int_pri) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if (int_pri > RTL8373_PRIMAX ) + return RT_ERR_QOS_INT_PRIORITY; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_PORT_PRI_ADDR (port), RTL8373_PORT_PRI_PORT_BASE_PRI_MASK(port),int_pri)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_PORT_PRI_DUP_ADDR (port), RTL8373_PORT_PRI_DUP_PORT_BASE_PRI_DUP_MASK(port),int_pri)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_qos_portPri_get + * Description: + * Get priority usage to each port. + * Input: + * port - Port id. + * Output: + * pInt_pri - internal priority value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get priority of port assignments for queue usage and packet scheduling. + */ +rtk_api_ret_t dal_rtl8373_qos_portPri_get(rtk_port_t port, rtk_pri_t *pInt_pri) +{ + rtk_api_ret_t retVal; + rtk_pri_t encap_pri; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if ((retVal = rtl8373_getAsicRegBits(RTL8373_PORT_PRI_ADDR (port), RTL8373_PORT_PRI_PORT_BASE_PRI_MASK(port), pInt_pri)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_getAsicRegBits(RTL8373_PORT_PRI_DUP_ADDR (port), RTL8373_PORT_PRI_DUP_PORT_BASE_PRI_DUP_MASK(port), &encap_pri)) != RT_ERR_OK) + return retVal; + + if(*pInt_pri != encap_pri) + return RT_ERR_FAILED; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_qos_priMap_set + * Description: + * Set output queue number for each port. + * Input: + * port - Port ID. + * pPri2qid - Priority mapping to queue ID. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_QUEUE_ID - Invalid queue id. + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * ASIC supports priority mapping to queue with different internal available queue IDs. + */ +rtk_api_ret_t dal_rtl8373_qos_priMap_set(rtk_port_t port, rtk_qos_pri2queue_t *pPri2qid) +{ + rtk_api_ret_t retVal; + rtk_uint32 pri; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + for (pri = 0; pri <= RTK_PRIMAX; pri++) + { + if (pPri2qid->pri2queue[pri] > RTK_QIDMAX) + return RT_ERR_QUEUE_ID; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_QID_TO_PRI_ADDR(port), 0x7 << (pri * 4), pPri2qid->pri2queue[pri])) != RT_ERR_OK) + return retVal; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_qos_priMap_get + * Description: + * Get priority to queue ID mapping table parameters. + * Input: + * port - Port ID. + * Output: + * pPri2qid - Priority mapping to queue ID. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_QUEUE_NUM - Invalid queue number. + * Note: + * The API can return the mapping queue id of the specified priority. + */ +rtk_api_ret_t dal_rtl8373_qos_priMap_get(rtk_port_t port, rtk_qos_pri2queue_t *pPri2qid) +{ + rtk_api_ret_t retVal; + rtk_uint32 pri; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + for (pri = 0; pri <= RTK_PRIMAX; pri++) + { + if ((retVal = rtl8373_getAsicRegBits(RTL8373_QID_TO_PRI_ADDR(port), 0x7 << (pri * 4), &pPri2qid->pri2queue[pri])) != RT_ERR_OK) + return retVal; + } + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_qos_schedulingQueue_set + * Description: + * Set weight and type of queues in dedicated port. + * Input: + * port - Port id. + * pQweights - The array of weights for WRR/WFQ queue (0 for STRICT_PRIORITY queue). + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_QOS_QUEUE_WEIGHT - Invalid queue weight. + * Note: + * The API can set weight and type, strict priority or weight fair queue (WFQ) for + * dedicated port for using queues. If queue id is not included in queue usage, + * then its type and weight setting in dummy for setting. There are priorities + * as queue id in strict queues. It means strict queue id 5 carrying higher priority + * than strict queue id 4. The WFQ queue weight is from 1 to 127, and weight 0 is + * for strict priority queue type. + */ +rtk_api_ret_t dal_rtl8373_qos_schedulingQueue_set(rtk_port_t port, rtk_qos_queue_weights_t *pQweights) +{ + rtk_api_ret_t retVal; + rtk_uint32 qid; + //rtk_uint32 phy_port; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + for (qid = 0; qid < RTL8373_QUEUENO; qid ++) + { + + if (pQweights->weights[qid] > QOS_WEIGHT_MAX) + return RT_ERR_QOS_QUEUE_WEIGHT; + + //phy_port = rtk_switch_port_L2P_get(port); + + if (0 == pQweights->weights[qid]) + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_SCHED_PORT_Q_CTRL_SET_ADDR(port,qid), RTL8373_SCHED_PORT_Q_CTRL_SET_STRICT_EN_OFFSET,RTL8373_QTYPE_STRICT)) != RT_ERR_OK) + return retVal; + } + else + { + if ((retVal = rtl8373_setAsicRegBit(RTL8373_SCHED_PORT_Q_CTRL_SET_ADDR(port,qid), RTL8373_SCHED_PORT_Q_CTRL_SET_STRICT_EN_OFFSET,RTL8373_QTYPE_WFQ)) != RT_ERR_OK) + return retVal; + if ((retVal = rtl8373_setAsicRegBits(RTL8373_SCHED_PORT_Q_CTRL_SET_ADDR(port,qid), RTL8373_SCHED_PORT_Q_CTRL_SET_WEIGHT_MASK,pQweights->weights[qid])) != RT_ERR_OK) + return retVal; + } + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_qos_schedulingQueue_get + * Description: + * Get weight and type of queues in dedicated port. + * Input: + * port - Port id. + * Output: + * pQweights - The array of weights for WRR/WFQ queue (0 for STRICT_PRIORITY queue). + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get weight and type, strict priority or weight fair queue (WFQ) for dedicated port for using queues. + * The WFQ queue weight is from 1 to 127, and weight 0 is for strict priority queue type. + */ +rtk_api_ret_t dal_rtl8373_qos_schedulingQueue_get(rtk_port_t port, rtk_qos_queue_weights_t *pQweights) +{ + rtk_api_ret_t retVal; + rtk_uint32 qid,qtype,qweight; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + //phy_port = rtk_switch_port_L2P_get(port); + + for (qid = 0; qid < RTL8373_QUEUENO; qid++) + { + if ((retVal = rtl8373_getAsicRegBit(RTL8373_SCHED_PORT_Q_CTRL_SET_ADDR(port,qid), RTL8373_SCHED_PORT_Q_CTRL_SET_STRICT_EN_OFFSET,&qtype)) != RT_ERR_OK) + return retVal; + + if (RTL8373_QTYPE_STRICT == qtype) + { + pQweights->weights[qid] = 0; + } + else + { + if ((retVal = rtl8373_getAsicRegBits(RTL8373_SCHED_PORT_Q_CTRL_SET_ADDR(port,qid), RTL8373_SCHED_PORT_Q_CTRL_SET_WEIGHT_MASK, &qweight)) != RT_ERR_OK) + return retVal; + pQweights->weights[qid] = qweight; + } + } + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_qos_1pRemarkEnable_set + * Description: + * Set 1p Remarking state + * Input: + * port - Port id. + * enable - State of per-port 1p Remarking + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable parameter. + * Note: + * The API can enable or disable 802.1p remarking ability for whole system. + * The status of 802.1p remark: + * - DISABLED + * - ENABLED + */ +rtk_api_ret_t dal_rtl8373_qos_1pRemarkEnable_set(rtk_port_t port, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if (enable >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if ((retVal = rtl8373_setAsicRegBit(RTL8373_RMK_PORT_CTRL_ADDR(port), RTL8373_RMK_PORT_CTRL_IPRI_RMK_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_qos_1pRemarkEnable_get + * Description: + * Get 802.1p remarking ability. + * Input: + * port - Port id. + * Output: + * pEnable - Status of 802.1p remark. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get 802.1p remarking ability. + * The status of 802.1p remark: + * - DISABLED + * - ENABLED + */ +rtk_api_ret_t dal_rtl8373_qos_1pRemarkEnable_get(rtk_port_t port, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if ((retVal = rtl8373_getAsicRegBit(RTL8373_RMK_PORT_CTRL_ADDR(port), RTL8373_RMK_PORT_CTRL_IPRI_RMK_EN_OFFSET, pEnable)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_qos_1pRemark_set + * Description: + * Set 802.1p remarking parameter. + * Input: + * int_pri - Internal priority value. + * dot1p_pri - 802.1p priority value. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_VLAN_PRIORITY - Invalid 1p priority. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * The API can set 802.1p parameters source priority and new priority. + */ +rtk_api_ret_t dal_rtl8373_qos_1pRemark_set(rtk_pri_t int_pri, rtk_pri_t dot1p_pri) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (int_pri > RTL8373_PRIMAX ) + return RT_ERR_QOS_INT_PRIORITY; + + if (dot1p_pri > RTL8373_PRIMAX) + return RT_ERR_VLAN_PRIORITY; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_RMK_INTPRI2IPRI_CTRL_ADDR,0x7<<(int_pri * 4), dot1p_pri)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_qos_1pRemark_get + * Description: + * Get 802.1p remarking parameter. + * Input: + * int_pri - Internal priority value. + * Output: + * pDot1p_pri - 802.1p priority value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * The API can get 802.1p remarking parameters. It would return new priority of ingress priority. + */ +rtk_api_ret_t dal_rtl8373_qos_1pRemark_get(rtk_pri_t int_pri, rtk_pri_t *pDot1p_pri) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (int_pri > RTL8373_PRIMAX ) + return RT_ERR_QOS_INT_PRIORITY; + + if ((retVal = rtl8373_getAsicRegBits(RTL8373_RMK_INTPRI2IPRI_CTRL_ADDR,0x7<<(int_pri * 4), pDot1p_pri)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_qos_1pRemarkSrcSel_set + * Description: + * Set remarking source of 802.1p remarking. + * Input: + * type - remarking source + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + + * Note: + * The API can configure 802.1p remark functionality to map original 802.1p value or internal + * priority to TX DSCP value. + */ +rtk_api_ret_t dal_rtl8373_qos_1pRemarkSrcSel_set(rtk_qos_1pRmkSrc_t type) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (type >= DOT1P_RMK_SRC_END ) + return RT_ERR_QOS_INT_PRIORITY; + + if ((retVal = rtl8373_setAsicRegBit(RTL8373_RMK_CTRL_ADDR ,RTL8373_RMK_CTRL_IPRI_RMK_SRC_OFFSET, type)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_qos_1pRemarkSrcSel_get + * Description: + * Get remarking source of 802.1p remarking. + * Input: + * none + * Output: + * pType - remarking source + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * RT_ERR_NULL_POINTER - input parameter may be null pointer + + * Note: + * None + */ +rtk_api_ret_t dal_rtl8373_qos_1pRemarkSrcSel_get(rtk_qos_1pRmkSrc_t *pType) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if ((retVal = rtl8373_getAsicRegBit(RTL8373_RMK_CTRL_ADDR ,RTL8373_RMK_CTRL_IPRI_RMK_SRC_OFFSET, pType)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_qos_dscpRemarkEnable_set + * Description: + * Set DSCP remarking ability. + * Input: + * port - Port id. + * enable - status of DSCP remark. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * RT_ERR_ENABLE - Invalid enable parameter. + * Note: + * The API can enable or disable DSCP remarking ability for whole system. + * The status of DSCP remark: + * - DISABLED + * - ENABLED + */ +rtk_api_ret_t dal_rtl8373_qos_dscpRemarkEnable_set(rtk_port_t port, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if (enable >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if ((retVal = rtl8373_setAsicRegBit(RTL8373_RMK_PORT_CTRL_ADDR(port), RTL8373_RMK_PORT_CTRL_DSCP_RMK_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_qos_dscpRemarkEnable_get + * Description: + * Get DSCP remarking ability. + * Input: + * port - Port id. + * Output: + * pEnable - status of DSCP remarking. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get DSCP remarking ability. + * The status of DSCP remark: + * - DISABLED + * - ENABLED + */ +rtk_api_ret_t dal_rtl8373_qos_dscpRemarkEnable_get(rtk_port_t port, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if ((retVal = rtl8373_getAsicRegBit(RTL8373_RMK_PORT_CTRL_ADDR(port), RTL8373_RMK_PORT_CTRL_DSCP_RMK_EN_OFFSET, pEnable)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_qos_intpri2dscp_Remark_set + * Description: + * Set DSCP remarking parameter. + * Input: + * int_pri - Internal priority value. + * dscp - remark DSCP value. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * RT_ERR_QOS_DSCP_VALUE - Invalid DSCP value. + * Note: + * The API can set internal priority to DSCP value. + */ +rtk_api_ret_t dal_rtl8373_qos_intpri2dscp_Remark_set(rtk_pri_t int_pri, rtk_dscp_t dscp) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (int_pri > RTK_PRIMAX ) + return RT_ERR_QOS_INT_PRIORITY; + + if (dscp > RTK_DSCPMAX) + return RT_ERR_QOS_DSCP_VALUE; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_RMK_INTPRI2DSCP_CTRL_ADDR(int_pri), RTL8373_RMK_INTPRI2DSCP_CTRL_DSCP_MASK(int_pri), dscp)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_qos_intpri2dscp_Remark_get + * Description: + * Get DSCP remarking parameter. + * Input: + * int_pri - Internal priority value. + * Output: + * pDscp - remark DSCP value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * The API can get DSCP parameters. It would return DSCP value for mapping priority. + */ +rtk_api_ret_t dal_rtl8373_qos_intpri2dscp_Remark_get(rtk_pri_t int_pri, rtk_dscp_t *pDscp) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (int_pri > RTK_PRIMAX ) + return RT_ERR_QOS_INT_PRIORITY; + + if ((retVal = rtl8373_getAsicRegBits(RTL8373_RMK_INTPRI2DSCP_CTRL_ADDR(int_pri), RTL8373_RMK_INTPRI2DSCP_CTRL_DSCP_MASK(int_pri), pDscp)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_qos_dscp2dscp_Remark_set + * Description: + * Set original DSCP remarking parameter. + * Input: + * ori_dscp - original dscp value. + * RmkDscp - remark DSCP value. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * RT_ERR_QOS_DSCP_VALUE - Invalid DSCP value. + * Note: + * The API can set original DSCP value to dscp value. + */ +rtk_api_ret_t dal_rtl8373_qos_dscp2dscp_Remark_set(rtk_pri_t ori_dscp, rtk_dscp_t RmkDscp) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (ori_dscp > RTK_DSCPMAX ) + return RT_ERR_QOS_DSCP_VALUE; + + if (RmkDscp > RTK_DSCPMAX) + return RT_ERR_QOS_DSCP_VALUE; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_RMK_DSCP2DSCP_CTRL_ADDR(ori_dscp), RTL8373_RMK_DSCP2DSCP_CTRL_DSCP_MASK(ori_dscp), RmkDscp)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_qos_dscp2dscp_Remark_get + * Description: + * Get DSCP remarking parameter. + * Input: + * int_pri - Internal priority value. + * Output: + * pRmkDscp - remark DSCP value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * The API can get DSCP parameters. It would return DSCP value for mapping priority. + */ +rtk_api_ret_t dal_rtl8373_qos_dscp2dscp_Remark_get(rtk_pri_t ori_dscp, rtk_dscp_t *pRmkDscp) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (ori_dscp > RTK_DSCPMAX ) + return RT_ERR_QOS_DSCP_VALUE; + + if ((retVal = rtl8373_getAsicRegBits(RTL8373_RMK_DSCP2DSCP_CTRL_ADDR(ori_dscp), RTL8373_RMK_DSCP2DSCP_CTRL_DSCP_MASK(ori_dscp), pRmkDscp)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_qos_dscpRemarkSrcSel_set + * Description: + * Set remarking source of DSCP remarking. + * Input: + * type - remarking source + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + + * Note: + * The API can configure DSCP remark functionality to map original DSCP value or internal + * priority to TX DSCP value. + */ +rtk_api_ret_t dal_rtl8373_qos_dscpRemarkSrcSel_set(rtk_qos_dscpRmkSrc_t type) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (type >= DSCP_RMK_SRC_END ) + return RT_ERR_QOS_INT_PRIORITY; + + if (type == DSCP_RMK_SRC_INT_PRI ) + return RT_ERR_QOS_INT_PRIORITY; + + switch (type) + { + case DSCP_RMK_SRC_DSCP: + regData = 1; + break; + case DSCP_RMK_SRC_USER_PRI: + regData = 0; + break; + default: + return RT_ERR_QOS_INT_PRIORITY; + } + + if ((retVal = rtl8373_setAsicRegBit(RTL8373_RMK_CTRL_ADDR,RTL8373_RMK_CTRL_DSCP_RMK_SRC_OFFSET, regData)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_qos_dscpRemarkSrcSel_get + * Description: + * Get remarking source of DSCP remarking. + * Input: + * none + * Output: + * pType - remarking source + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * RT_ERR_NULL_POINTER - input parameter may be null pointer + + * Note: + * None + */ +rtk_api_ret_t dal_rtl8373_qos_dscpRemarkSrcSel_get(rtk_qos_dscpRmkSrc_t *pType) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if ((retVal = rtl8373_getAsicRegBit(RTL8373_RMK_CTRL_ADDR,RTL8373_RMK_CTRL_DSCP_RMK_SRC_OFFSET, ®Data)) != RT_ERR_OK) + return retVal; + + switch (regData) + { + case 0: + *pType = DSCP_RMK_SRC_USER_PRI; + break; + case 1: + *pType = DSCP_RMK_SRC_DSCP; + break; + default: + return RT_ERR_FAILED; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_qos_schedulingType_set + * Description: + * Set scheduling type. + * Input: + * port - port id + * type - scheduling type + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + + * Note: + * The API can configure QoS scheduling type. + */ +rtk_api_ret_t dal_rtl8373_qos_schedulingType_set(rtk_port_t port, rtk_qos_scheduling_type_t type) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (type >= SCHEDULING_TYPE_END ) + return RT_ERR_QOS_SCHE_TYPE; + + if ((retVal = rtl8373_setAsicRegBit(RTL8373_SCHED_PORT_ALGO_CTRL_ADDR(port), RTL8373_SCHED_PORT_ALGO_CTRL_SCHED_TYPE_OFFSET(port), type)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_qos_schedulingType_get + * Description: + * Get type of scheduling. + * Input: + * port - port id + * Output: + * pType - scheduling type + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_NULL_POINTER - input parameter may be null pointer + + * Note: + * The API can get QoS scheduling type + */ +rtk_api_ret_t dal_rtl8373_qos_schedulingType_get(rtk_port_t port, rtk_qos_scheduling_type_t *pType) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if ((retVal = rtl8373_getAsicRegBit(RTL8373_SCHED_PORT_ALGO_CTRL_ADDR(port), RTL8373_SCHED_PORT_ALGO_CTRL_SCHED_TYPE_OFFSET(port), pType)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_qos_portPriSelIndex_set + * Description: + * Configure priority decision index to each port. + * Input: + * port - Port id. + * index - priority decision index. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENTRY_INDEX - Invalid entry index. + * Note: + * The API can set priority of port assignments for queue usage and packet scheduling. + */ +rtk_api_ret_t dal_rtl8373_qos_portPriSelIndex_set(rtk_port_t port, rtk_qos_priDecTbl_t index) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if (index >= PRIDECTBL_END ) + return RT_ERR_ENTRY_INDEX; + + if ((retVal = rtl8373_setAsicRegBit(RTL8373_PORT_WEIGHT_SEL_ADDR (port), RTL8373_PORT_WEIGHT_SEL_WEIGHT_SEL_OFFSET(port), index)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_qos_portPriSelIndex_get + * Description: + * Get priority decision index from each port. + * Input: + * port - Port id. + * Output: + * pIndex - priority decision index. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get priority of port assignments for queue usage and packet scheduling. + */ +rtk_api_ret_t dal_rtl8373_qos_portPriSelIndex_get(rtk_port_t port, rtk_qos_priDecTbl_t *pIndex) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if ((retVal = rtl8373_getAsicRegBit(RTL8373_PORT_WEIGHT_SEL_ADDR (port), RTL8373_PORT_WEIGHT_SEL_WEIGHT_SEL_OFFSET(port), pIndex)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_qos.h b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_qos.h new file mode 100755 index 00000000..f3680fd6 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_qos.h @@ -0,0 +1,721 @@ + /* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8371c switch high-level API + * + * Feature : The file includes QoS module high-layer API defination + * + */ + +#ifndef __DAL_RTL8373_QOS_H__ +#define __DAL_RTL8373_QOS_H__ + +#include + +#define RTL8373_QTYPE_STRICT 1 +#define RTL8373_QTYPE_WFQ 0 +#define RTL8373_QTYPE_SRR 1 + +#define RTL8373_PRIDEC_END 5 +#define RTL8373_PRIIDX_END 2 + + + +/* Function Name: + * dal_rtl8373_qos_init + * Description: + * Configure Qos default settings. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will initialize related Qos setting. + */ +extern rtk_api_ret_t dal_rtl8373_qos_init(void); + +/* Function Name: + * dal_rtl8373_qos_priSel_set + * Description: + * Configure the priority order among different priority mechanism. + * Input: + * index - Priority decision table index (0~1) + * pPriDec - Priority assign for port, dscp, 802.1p, svlan, acl based priority decision. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_SEL_PRI_SOURCE - Invalid priority decision source parameter. + * Note: + * ASIC will follow user priority setting of mechanisms to select mapped queue priority for receiving frame. + * If two priority mechanisms are the same, the ASIC will chose the highest priority from mechanisms to + * assign queue priority to receiving frame. + * The priority sources are: + * - RTL8373_PRIDEC_PORT + * - RTL8373_PRIDEC_ACL + * - RTL8373_PRIDEC_DSCP + * - RTL8373_PRIDEC_1Q + * - RTL8373_PRIDEC_SVLAN + */ +extern rtk_api_ret_t dal_rtl8373_qos_priSel_set(rtk_qos_priDecTbl_t index, rtk_priority_select_t *pPriDec); + + +/* Function Name: + * dal_rtl8373_qos_priSel_get + * Description: + * Get the priority order configuration among different priority mechanism. + * Input: + * index - Priority decision table index (0~1) + * Output: + * pPriDec - Priority assign for port, dscp, 802.1p, svlan, acl based priority decision . + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * ASIC will follow user priority setting of mechanisms to select mapped queue priority for receiving frame. + * If two priority mechanisms are the same, the ASIC will chose the highest priority from mechanisms to + * assign queue priority to receiving frame. + * The priority sources are: + * - RTL8373_PRIDEC_PORT + * - RTL8373_PRIDEC_ACL + * - RTL8373_PRIDEC_DSCP + * - RTL8373_PRIDEC_1Q + * - RTL8373_PRIDEC_SVLAN + */ +extern rtk_api_ret_t dal_rtl8373_qos_priSel_get(rtk_qos_priDecTbl_t index, rtk_priority_select_t *pPriDec); + +/* Function Name: + * dal_rtl8373_qos_1pPriRemap_set + * Description: + * Configure 1Q priorities mapping to internal absolute priority. + * Input: + * dot1p_pri - 802.1p priority value. + * int_pri - internal priority value. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_VLAN_PRIORITY - Invalid 1p priority. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * Priority of 802.1Q assignment for internal asic priority, and it is used for queue usage and packet scheduling. + */ +extern rtk_api_ret_t dal_rtl8373_qos_1pPriRemap_set(rtk_pri_t dot1p_pri, rtk_pri_t int_pri); + +/* Function Name: + * dal_rtl8373_qos_1pPriRemap_get + * Description: + * Get 1Q priorities mapping to internal absolute priority. + * Input: + * dot1p_pri - 802.1p priority value . + * Output: + * pInt_pri - internal priority value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_VLAN_PRIORITY - Invalid priority. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * Priority of 802.1Q assigment for internal asic priority, and it is uesed for queue usage and packet scheduling. + */ +extern rtk_api_ret_t dal_rtl8373_qos_1pPriRemap_get(rtk_pri_t dot1p_pri, rtk_pri_t *pInt_pri); + +/* Function Name: + * dal_rtl8373_qos_dscpPriRemap_set + * Description: + * Map dscp value to internal priority. + * Input: + * dscp - Dscp value of receiving frame + * int_pri - internal priority value . + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_QOS_DSCP_VALUE - Invalid DSCP value. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * The Differentiated Service Code Point is a selector for router's per-hop behaviors. As a selector, there is no implication that a numerically + * greater DSCP implies a better network service. As can be seen, the DSCP totally overlaps the old precedence field of TOS. So if values of + * DSCP are carefully chosen then backward compatibility can be achieved. + */ +extern rtk_api_ret_t dal_rtl8373_qos_dscpPriRemap_set(rtk_dscp_t dscp, rtk_pri_t int_pri); + +/* Function Name: + * dal_rtl8373_qos_dscpPriRemap_get + * Description: + * Get dscp value to internal priority. + * Input: + * dscp - Dscp value of receiving frame + * Output: + * pInt_pri - internal priority value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_DSCP_VALUE - Invalid DSCP value. + * Note: + * The Differentiated Service Code Point is a selector for router's per-hop behaviors. As a selector, there is no implication that a numerically + * greater DSCP implies a better network service. As can be seen, the DSCP totally overlaps the old precedence field of TOS. So if values of + * DSCP are carefully chosen then backward compatibility can be achieved. + */ +extern rtk_api_ret_t dal_rtl8373_qos_dscpPriRemap_get(rtk_dscp_t dscp, rtk_pri_t *pInt_pri); + +/* Function Name: + * dal_rtl8373_qos_RspanPriRemap_set + * Description: + * Configure RSPAN priorities mapping to internal absolute priority. + * Input: + * rspan_pri - rspan priority value. + * int_pri - internal priority value. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_VLAN_PRIORITY - Invalid 1p priority. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * Priority of RSPAN assignment for internal asic priority, and it is used for queue usage and packet scheduling. + */ +extern rtk_api_ret_t dal_rtl8373_qos_RspanPriRemap_set(rtk_pri_t rspan_pri, rtk_pri_t int_pri); + +/* Function Name: + * dal_rtl8373_qos_RspanPriRemap_get + * Description: + * Get RSPAN priorities mapping to internal absolute priority. + * Input: + * rspan_pri - rspan priority value. + * Output: + * pInt_pri - internal priority value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_VLAN_PRIORITY - Invalid priority. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * Priority of RSPAN assigment for internal asic priority, and it is uesed for queue usage and packet scheduling. + */ +extern rtk_api_ret_t dal_rtl8373_qos_RspanPriRemap_get(rtk_pri_t rspan_pri, rtk_pri_t *pInt_pri); + +/* Function Name: + * dal_rtl8373_qos_portPri_set + * Description: + * Configure priority usage to each port. + * Input: + * port - Port id. + * int_pri - internal priority value. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_QOS_SEL_PORT_PRI - Invalid port priority. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * The API can set priority of port assignments for queue usage and packet scheduling. + */ +extern rtk_api_ret_t dal_rtl8373_qos_portPri_set(rtk_port_t port, rtk_pri_t int_pri); + +/* Function Name: + * dal_rtl8373_qos_portPri_get + * Description: + * Get priority usage to each port. + * Input: + * port - Port id. + * Output: + * pInt_pri - internal priority value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get priority of port assignments for queue usage and packet scheduling. + */ +extern rtk_api_ret_t dal_rtl8373_qos_portPri_get(rtk_port_t port, rtk_pri_t *pInt_pri) ; + +/* Function Name: + * dal_rtl8373_qos_priMap_set + * Description: + * Set output queue number for each port. + * Input: + * port - Port ID. + * pPri2qid - Priority mapping to queue ID. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_QUEUE_ID - Invalid queue id. + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * ASIC supports priority mapping to queue with different internal available queue IDs. + */ +extern rtk_api_ret_t dal_rtl8373_qos_priMap_set(rtk_port_t port, rtk_qos_pri2queue_t *pPri2qid); + +/* Function Name: + * dal_rtl8373_qos_priMap_get + * Description: + * Get priority to queue ID mapping table parameters. + * Input: + * port - Port ID. + * Output: + * pPri2qid - Priority mapping to queue ID. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_QUEUE_NUM - Invalid queue number. + * Note: + * The API can return the mapping queue id of the specified priority. + */ +extern rtk_api_ret_t dal_rtl8373_qos_priMap_get(rtk_port_t port, rtk_qos_pri2queue_t *pPri2qid); + +/* Function Name: + * dal_rtl8373_qos_schedulingQueue_set + * Description: + * Set weight and type of queues in dedicated port. + * Input: + * port - Port id. + * pQweights - The array of weights for WRR/WFQ queue (0 for STRICT_PRIORITY queue). + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_QOS_QUEUE_WEIGHT - Invalid queue weight. + * Note: + * The API can set weight and type, strict priority or weight fair queue (WFQ) for + * dedicated port for using queues. If queue id is not included in queue usage, + * then its type and weight setting in dummy for setting. There are priorities + * as queue id in strict queues. It means strict queue id 5 carrying higher priority + * than strict queue id 4. The WFQ queue weight is from 1 to 128, and weight 0 is + * for strict priority queue type. + */ +extern rtk_api_ret_t dal_rtl8373_qos_schedulingQueue_set(rtk_port_t port, rtk_qos_queue_weights_t *pQweights); + +/* Function Name: + * dal_rtl8373_qos_schedulingQueue_get + * Description: + * Get weight and type of queues in dedicated port. + * Input: + * port - Port id. + * Output: + * pQweights - The array of weights for WRR/WFQ queue (0 for STRICT_PRIORITY queue). + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get weight and type, strict priority or weight fair queue (WFQ) for dedicated port for using queues. + * The WFQ queue weight is from 1 to 128, and weight 0 is for strict priority queue type. + */ +extern rtk_api_ret_t dal_rtl8373_qos_schedulingQueue_get(rtk_port_t port, rtk_qos_queue_weights_t *pQweights); + +/* Function Name: + * dal_rtl8373_qos_1pRemarkEnable_set + * Description: + * Set 1p Remarking state + * Input: + * port - Port id. + * enable - State of per-port 1p Remarking + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable parameter. + * Note: + * The API can enable or disable 802.1p remarking ability for whole system. + * The status of 802.1p remark: + * - DISABLED + * - ENABLED + */ +extern rtk_api_ret_t dal_rtl8373_qos_1pRemarkEnable_set(rtk_port_t port, rtk_enable_t enable); + +/* Function Name: + * dal_rtl8373_qos_1pRemarkEnable_get + * Description: + * Get 802.1p remarking ability. + * Input: + * port - Port id. + * Output: + * pEnable - Status of 802.1p remark. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get 802.1p remarking ability. + * The status of 802.1p remark: + * - DISABLED + * - ENABLED + */ +extern rtk_api_ret_t dal_rtl8373_qos_1pRemarkEnable_get(rtk_port_t port, rtk_enable_t *pEnable); + +/* Function Name: + * dal_rtl8373_qos_1pRemark_set + * Description: + * Set 802.1p remarking parameter. + * Input: + * int_pri - Internal priority value. + * dot1p_pri - 802.1p priority value. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_VLAN_PRIORITY - Invalid 1p priority. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * The API can set 802.1p parameters source priority and new priority. + */ +extern rtk_api_ret_t dal_rtl8373_qos_1pRemark_set(rtk_pri_t int_pri, rtk_pri_t dot1p_pri); + +/* Function Name: + * dal_rtl8373_qos_1pRemark_get + * Description: + * Get 802.1p remarking parameter. + * Input: + * int_pri - Internal priority value. + * Output: + * pDot1p_pri - 802.1p priority value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * The API can get 802.1p remarking parameters. It would return new priority of ingress priority. + */ +extern rtk_api_ret_t dal_rtl8373_qos_1pRemark_get(rtk_pri_t int_pri, rtk_pri_t *pDot1p_pri); + +/* Function Name: + * dal_rtl8373_qos_1pRemarkSrcSel_set + * Description: + * Set remarking source of 802.1p remarking. + * Input: + * type - remarking source + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + + * Note: + * The API can configure 802.1p remark functionality to map original 802.1p value or internal + * priority to TX DSCP value. + */ +extern rtk_api_ret_t dal_rtl8373_qos_1pRemarkSrcSel_set(rtk_qos_1pRmkSrc_t type); + +/* Function Name: + * dal_rtl8373_qos_1pRemarkSrcSel_get + * Description: + * Get remarking source of 802.1p remarking. + * Input: + * none + * Output: + * pType - remarking source + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * RT_ERR_NULL_POINTER - input parameter may be null pointer + + * Note: + * None + */ +extern rtk_api_ret_t dal_rtl8373_qos_1pRemarkSrcSel_get(rtk_qos_1pRmkSrc_t *pType); + +/* Function Name: + * dal_rtl8373_qos_dscpRemarkEnable_set + * Description: + * Set DSCP remarking ability. + * Input: + * port - Port id. + * enable - status of DSCP remark. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * RT_ERR_ENABLE - Invalid enable parameter. + * Note: + * The API can enable or disable DSCP remarking ability for whole system. + * The status of DSCP remark: + * - DISABLED + * - ENABLED + */ +extern rtk_api_ret_t dal_rtl8373_qos_dscpRemarkEnable_set(rtk_port_t port, rtk_enable_t enable); + +/* Function Name: + * dal_rtl8373_qos_dscpRemarkEnable_get + * Description: + * Get DSCP remarking ability. + * Input: + * port - Port id. + * Output: + * pEnable - status of DSCP remarking. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get DSCP remarking ability. + * The status of DSCP remark: + * - DISABLED + * - ENABLED + */ +extern rtk_api_ret_t dal_rtl8373_qos_dscpRemarkEnable_get(rtk_port_t port, rtk_enable_t *pEnable); + +/* Function Name: + * dal_rtl8373_qos_intpri2dscp_Remark_set + * Description: + * Set DSCP remarking parameter. + * Input: + * int_pri - Internal priority value. + * dscp - remark DSCP value. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * RT_ERR_QOS_DSCP_VALUE - Invalid DSCP value. + * Note: + * The API can set internal priority to DSCP value. + */ +extern rtk_api_ret_t dal_rtl8373_qos_intpri2dscp_Remark_set(rtk_pri_t int_pri, rtk_dscp_t dscp); + +/* Function Name: + * dal_rtl8373_qos_intpri2dscp_Remark_get + * Description: + * Get DSCP remarking parameter. + * Input: + * int_pri - Internal priority value. + * Output: + * pDscp - remark DSCP value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * The API can get DSCP parameters. It would return DSCP value for mapping priority. + */ +extern rtk_api_ret_t dal_rtl8373_qos_intpri2dscp_Remark_get(rtk_pri_t int_pri, rtk_dscp_t *pDscp); + +/* Function Name: + * dal_rtl8373_qos_dscp2dscp_Remark_set + * Description: + * Set original DSCP remarking parameter. + * Input: + * ori_dscp - original dscp value. + * RmkDscp - remark DSCP value. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * RT_ERR_QOS_DSCP_VALUE - Invalid DSCP value. + * Note: + * The API can set original DSCP value to dscp value. + */ +extern rtk_api_ret_t dal_rtl8373_qos_dscp2dscp_Remark_set(rtk_pri_t ori_dscp, rtk_dscp_t RmkDscp); + +/* Function Name: + * dal_rtl8373_qos_dscp2dscp_Remark_get + * Description: + * Get DSCP remarking parameter. + * Input: + * int_pri - Internal priority value. + * Output: + * pRmkDscp - remark DSCP value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * The API can get DSCP parameters. It would return DSCP value for mapping priority. + */ +extern rtk_api_ret_t dal_rtl8373_qos_dscp2dscp_Remark_get(rtk_pri_t ori_dscp, rtk_dscp_t *pRmkDscp); + +/* Function Name: + * dal_rtl8373_qos_dscpRemarkSrcSel_set + * Description: + * Set remarking source of DSCP remarking. + * Input: + * type - remarking source + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + + * Note: + * The API can configure DSCP remark functionality to map original DSCP value or internal + * priority to TX DSCP value. + */ +extern rtk_api_ret_t dal_rtl8373_qos_dscpRemarkSrcSel_set(rtk_qos_dscpRmkSrc_t type); + +/* Function Name: + * dal_rtl8373_qos_dscpRemarkSrcSel_get + * Description: + * Get remarking source of DSCP remarking. + * Input: + * none + * Output: + * pType - remarking source + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * RT_ERR_NULL_POINTER - input parameter may be null pointer + + * Note: + * None + */ +extern rtk_api_ret_t dal_rtl8373_qos_dscpRemarkSrcSel_get(rtk_qos_dscpRmkSrc_t *pType); + +/* Function Name: + * dal_rtl8373_qos_schedulingType_set + * Description: + * Set scheduling type. + * Input: + * port - port id + * type - scheduling type + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + + * Note: + * The API can configure QoS scheduling type. + */ +extern rtk_api_ret_t dal_rtl8373_qos_schedulingType_set(rtk_port_t port, rtk_qos_scheduling_type_t type); + +/* Function Name: + * dal_rtl8373_qos_schedulingType_get + * Description: + * Get type of scheduling. + * Input: + * port - port id + * Output: + * pType - scheduling type + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_NULL_POINTER - input parameter may be null pointer + + * Note: + * The API can get QoS scheduling type + */ +extern rtk_api_ret_t dal_rtl8373_qos_schedulingType_get(rtk_port_t port, rtk_qos_scheduling_type_t *pType); + +/* Function Name: + * dal_rtl8373_qos_portPriSelIndex_set + * Description: + * Configure priority decision index to each port. + * Input: + * port - Port id. + * index - priority decision index. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENTRY_INDEX - Invalid entry index. + * Note: + * The API can set priority of port assignments for queue usage and packet scheduling. + */ +extern rtk_api_ret_t dal_rtl8373_qos_portPriSelIndex_set(rtk_port_t port, rtk_qos_priDecTbl_t index); + +/* Function Name: + * dal_rtl8373_qos_portPriSelIndex_get + * Description: + * Get priority decision index from each port. + * Input: + * port - Port id. + * Output: + * pIndex - priority decision index. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get priority of port assignments for queue usage and packet scheduling. + */ +extern rtk_api_ret_t dal_rtl8373_qos_portPriSelIndex_get(rtk_port_t port, rtk_qos_priDecTbl_t *pIndex); + +#endif /* __DAL_rtl8373_QOS_H__*/ + diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_rate.c b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_rate.c new file mode 100755 index 00000000..ce1d33b1 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_rate.c @@ -0,0 +1,647 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8373 + * Feature : Here is a list of all functions and variables in ingress bandwitdh control and egress queue bandwidth control module. + * + */ + +#include +#include +#include +#include +#include + +#include + + +/* Function Name: + * dal_rtl8373_rate_igrBwCtrlPortEn_set + * Description: + * Enable or disable port ingress bandwidth control + * Input: + * port - Port id + * bwEn - enable ingress bandwidth control or not + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid IFG parameter. + * RT_ERR_INBW_RATE - Invalid ingress rate parameter. + * Note: + * + */ +rtk_api_ret_t dal_rtl8373_rate_igrBwCtrlPortEn_set(rtk_port_t port, rtk_enable_t bwEn) +{ + rtk_uint32 retVal = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + if(port > INBW_CTRL_MAX_PORT_ID) + return RT_ERR_INBW_PORT_ID; + + if(bwEn >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if((retVal = rtl8373_setAsicRegBit(RTL8373_IGBW_PORT_CTRL_ADDR(port), RTL8373_IGBW_PORT_CTRL_BW_EN_OFFSET, bwEn)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; + +} + +/* Function Name: + * dal_rtl8373_rate_igrBwCtrlPortEn_get + * Description: + * Enable or disable port ingress bandwidth control + * Input: + * port - Port id + * + * Output: + * pBwEn - Port ingress bandwidth control state + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid IFG parameter. + * RT_ERR_INBW_RATE - Invalid ingress rate parameter. + * Note: + * + */ +rtk_api_ret_t dal_rtl8373_rate_igrBwCtrlPortEn_get(rtk_port_t port, rtk_enable_t *pBwEn) +{ + rtk_uint32 retVal = 0, regVal = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + if(port > INBW_CTRL_MAX_PORT_ID) + return RT_ERR_INBW_PORT_ID; + + if(pBwEn == NULL) + return RT_ERR_NULL_POINTER; + + if((retVal = rtl8373_getAsicRegBit(RTL8373_IGBW_PORT_CTRL_ADDR(port), RTL8373_IGBW_PORT_CTRL_BW_EN_OFFSET, ®Val)) != RT_ERR_OK) + return retVal; + *pBwEn = (rtk_enable_t)regVal; + + return RT_ERR_OK; + +} + +/* Function Name: + * dal_rtl8373_rate_igrBwCtrlRate_set + * Description: + * Set port ingress bandwidth control rate and FC config + * Input: + * port - Port id + * rate - Rate of share meter(uint: kpbs) + * fcEn - enable flow control or not, ENABLE:use flow control DISABLE:drop + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid IFG parameter. + * RT_ERR_INBW_RATE - Invalid ingress rate parameter. + * Note: + * The rate unit is 16 kbps and the range is from 16k to 10G. The granularity of rate is 16 kbps. + * The ifg_include parameter is used for rate calculation with/without inter-frame-gap and preamble. + */ +rtk_api_ret_t dal_rtl8373_rate_igrBwCtrlRate_set(rtk_port_t port, rtk_rate_t rate, rtk_enable_t fcEn) +{ + rtk_uint32 retVal = 0, regData = 0; + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if (port > INBW_CTRL_MAX_PORT_ID) + return RT_ERR_INBW_PORT_ID; + + if (fcEn >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if (rate > INBW_CTRL_RATE_MAX) + return RT_ERR_INBW_RATE; + + regData = (rate >> 4); + if ((retVal = rtl8373_setAsicRegBits(RTL8373_IGBW_PORT_CTRL_ADDR(port), RTL8373_IGBW_PORT_CTRL_RATE_MASK, regData)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_setAsicRegBit(RTL8373_IGBW_PORT_FC_CTRL_ADDR(port), RTL8373_IGBW_PORT_FC_CTRL_EN_OFFSET(port), fcEn)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_rate_igrBwCtrlRate_get + * Description: + * Get port ingress bandwidth control rate and FC config + * Input: + * port - Port id + * + * Output: + * pRate - Rate of share meter(uint: kpbs) + * pFcEn - enable flow control or not, ENABLE:use flow control DISABLE:drop + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid IFG parameter. + * RT_ERR_INBW_RATE - Invalid ingress rate parameter. + * Note: + * The rate unit is 16 kbps and the range is from 16k to 10G. The granularity of rate is 16 kbps. + * The ifg_include parameter is used for rate calculation with/without inter-frame-gap and preamble. + */ +rtk_api_ret_t dal_rtl8373_rate_igrBwCtrlRate_get(rtk_port_t port, rtk_rate_t *pRate, rtk_enable_t *pFcEn) +{ + rtk_uint32 retVal = 0, regData = 0; + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + if(port > INBW_CTRL_MAX_PORT_ID) + return RT_ERR_INBW_PORT_ID; + + if((pRate == NULL) || (pFcEn == NULL)) + return RT_ERR_NULL_POINTER; + + if((retVal = rtl8373_getAsicRegBits(RTL8373_IGBW_PORT_CTRL_ADDR(port), RTL8373_IGBW_PORT_CTRL_RATE_MASK, ®Data)) != RT_ERR_OK) + return retVal; + *pRate = (regData << 4); + + if((retVal = rtl8373_getAsicRegBit(RTL8373_IGBW_PORT_FC_CTRL_ADDR(port), RTL8373_IGBW_PORT_FC_CTRL_EN_OFFSET(port), ®Data)) != RT_ERR_OK) + return retVal; + *pFcEn = (rtk_enable_t)regData; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_rate_igrBwCtrlIfg_set + * Description: + * Set ingress bandwidth control include Preamble and IFG or not + * Input: + * ifgInclude - include or not, ENABLE:include DISABLE:exclude + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid IFG parameter. + * RT_ERR_INBW_RATE - Invalid ingress rate parameter. + * Note: + * + */ +rtk_api_ret_t dal_rtl8373_rate_igrBwCtrlIfg_set(rtk_enable_t ifgInclude) +{ + rtk_uint32 retVal = 0; + + if(ifgInclude >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if((retVal = rtl8373_setAsicRegBit(RTL8373_IGBW_CTRL_ADDR, RTL8373_IGBW_CTRL_INC_IFG_OFFSET, ifgInclude)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_rate_igrBwCtrlIfg_get + * Description: + * Get ingress bandwidth control include 8B Preamble and 12B IFG or not + * Input: + * None + * Output: + * ifgInclude - include or not, ENABLE:include DISABLE:exclude + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid IFG parameter. + * RT_ERR_INBW_RATE - Invalid ingress rate parameter. + * Note: + * + */ +rtk_api_ret_t dal_rtl8373_rate_igrBwCtrlIfg_get(rtk_enable_t *pIfgInclude) +{ + rtk_uint32 retVal = 0, regVal = 0; + + if(pIfgInclude == NULL) + return RT_ERR_INPUT; + + if((retVal = rtl8373_getAsicRegBit(RTL8373_IGBW_CTRL_ADDR, RTL8373_IGBW_CTRL_INC_IFG_OFFSET, ®Val)) != RT_ERR_OK) + return retVal; + *pIfgInclude = (rtk_enable_t)regVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_rate_igrBwCtrlCongestSts_get + * Description: + * Get port_n ingress bandwidth exceed leaky bucket high-on or not + * Input: + * port - port Idx + * Output: + * pCongestSts - Indicate ingress bandwidth exceed Pn_IGR_LB_ HIGH _ON for port n. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid IFG parameter. + * RT_ERR_INBW_RATE - Invalid ingress rate parameter. + * Note: + * + */ +rtk_api_ret_t dal_rtl8373_rate_igrBwCtrlCongestSts_get(rtk_port_t port, rtk_rate_igrBwCongestSts_t *pCongestSts) +{ + rtk_uint32 retVal = 0, regVal = 0; + + if(pCongestSts == NULL) + return RT_ERR_INPUT; + + if((retVal = rtl8373_getAsicRegBit(RTL8373_IGBW_PORT_CNGST_FLAG_ADDR(port), RTL8373_IGBW_PORT_CNGST_FLAG_FLAG_OFFSET(port), ®Val)) != RT_ERR_OK) + return retVal; + *pCongestSts = (rtk_rate_igrBwCongestSts_t)regVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_rate_egrBwCtrlPortEn_set + * Description: + * Enable or disable port egress bandwidth control + * Input: + * port - Port id + * bwEn - enable egress bandwidth control or not + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid IFG parameter. + * RT_ERR_INBW_RATE - Invalid ingress rate parameter. + * Note: + * + */ +rtk_api_ret_t dal_rtl8373_rate_egrBwCtrlPortEn_set(rtk_port_t port, rtk_enable_t bwEn) +{ + rtk_uint32 retVal = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + if(port > EBW_CTRL_MAX_PORT_ID) + return RT_ERR_QOS_EBW_PORT_ID; + + if(bwEn >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if((retVal = rtl8373_setAsicRegBit(RTL8373_EGBW_PORT_CTRL_ADDR(port), RTL8373_EGBW_PORT_CTRL_EN_OFFSET, bwEn)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; + +} + +/* Function Name: + * dal_rtl8373_rate_egrBwCtrlPortEn_get + * Description: + * Enable or disable port egress bandwidth control + * Input: + * port - Port id + * + * Output: + * pBwEn - Port egress bandwidth control state + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid IFG parameter. + * RT_ERR_INBW_RATE - Invalid ingress rate parameter. + * Note: + * + */ +rtk_api_ret_t dal_rtl8373_rate_egrBwCtrlPortEn_get(rtk_port_t port, rtk_enable_t *pBwEn) +{ + rtk_uint32 retVal = 0, regVal = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + if(port > EBW_CTRL_MAX_PORT_ID) + return RT_ERR_QOS_EBW_PORT_ID; + + if(pBwEn == NULL) + return RT_ERR_NULL_POINTER; + + if((retVal = rtl8373_getAsicRegBit(RTL8373_EGBW_PORT_CTRL_ADDR(port), RTL8373_EGBW_PORT_CTRL_EN_OFFSET, ®Val)) != RT_ERR_OK) + return retVal; + *pBwEn = (rtk_enable_t)regVal; + + return RT_ERR_OK; + +} + + +/* Function Name: + * dal_rtl8373_rate_egrBwCtrlRate_set + * Description: + * Set port egress bandwidth control rate and IPG config + * Input: + * port - Port id + * rate - Rate of share meter(uint: kpbs) + * ipg - include ipg or not, ENABLE:include DISABLE:exclude + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid IFG parameter. + * RT_ERR_INBW_RATE - Invalid ingress rate parameter. + * Note: + * The rate unit is 16 kbps and the range is from 16k to 10G. The granularity of rate is 16 kbps. + * The ifg_include parameter is used for rate calculation with/without inter-frame-gap and preamble. + */ +rtk_api_ret_t dal_rtl8373_rate_egrBwCtrlRate_set(rtk_port_t port, rtk_rate_t rate, rtk_enable_t ipg) +{ + rtk_uint32 retVal = 0, regData = 0; + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + if(port > EBW_CTRL_MAX_PORT_ID) + return RT_ERR_QOS_EBW_PORT_ID; + + if(ipg >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + + if(rate > EBW_CTRL_RATE_MAX) + return RT_ERR_QOS_EBW_RATE; + + regData = (rate >> 4); + if((retVal = rtl8373_setAsicRegBits(RTL8373_EGBW_PORT_CTRL_ADDR(port), RTL8373_EGBW_PORT_CTRL_RATE_MASK, regData)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8373_setAsicRegBit(RTL8373_EGBW_CTRL_ADDR, RTL8373_EGBW_CTRL_INC_IFG_OFFSET, ipg)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_rate_egrBwCtrlRate_get + * Description: + * Get port egress bandwidth control rate and IPG config + * Input: + * port - Port id + * + * Output: + * pRate - Rate of share meter(uint: kpbs) + * pIpg - include ipg or not, ENABLE:include DISABLE:exclude + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid IFG parameter. + * RT_ERR_INBW_RATE - Invalid ingress rate parameter. + * Note: + * The rate unit is 16 kbps and the range is from 16k to 10G. The granularity of rate is 16 kbps. + * The ifg_include parameter is used for rate calculation with/without inter-frame-gap and preamble. + */ +rtk_api_ret_t dal_rtl8373_rate_egrBwCtrlRate_get(rtk_port_t port, rtk_rate_t *pRate, rtk_enable_t *pIpg) +{ + rtk_uint32 retVal = 0, regData = 0; + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + if(port > EBW_CTRL_MAX_PORT_ID) + return RT_ERR_QOS_EBW_PORT_ID; + + if((pRate == NULL) || (pIpg == NULL)) + return RT_ERR_NULL_POINTER; + + if((retVal = rtl8373_getAsicRegBits(RTL8373_EGBW_PORT_CTRL_ADDR(port), RTL8373_EGBW_PORT_CTRL_RATE_MASK, ®Data)) != RT_ERR_OK) + return retVal; + *pRate = (regData << 4); + + if((retVal = rtl8373_getAsicRegBit(RTL8373_EGBW_CTRL_ADDR, RTL8373_EGBW_CTRL_INC_IFG_OFFSET, ®Data)) != RT_ERR_OK) + return retVal; + *pIpg = (rtk_enable_t)regData; + + return RT_ERR_OK; +} + + + +/* Function Name: + * dal_rtl8373_rate_egrQueueMaxBwEn_set + * Description: + * Set port egress queue max bandwidth enable + * Input: + * port - Port id + * qid - Queue ID + * enable - 1:enable, 0:disable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid IFG parameter. + * RT_ERR_INBW_RATE - Invalid ingress rate parameter. + * Note: + */ +rtk_api_ret_t dal_rtl8373_rate_egrQueueMaxBwEn_set(rtk_port_t port, rtk_qid_t qid, rtk_enable_t enable) +{ + rtk_uint32 retVal = 0; + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + if(port > EBW_CTRL_MAX_PORT_ID) + return RT_ERR_QOS_EBW_PORT_ID; + + if(enable >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + + if((retVal = rtl8373_setAsicRegBit(RTL8373_EGBW_PORT_Q_MAX_LB_CTRL_SET_ADDR(port, qid), RTL8373_EGBW_PORT_Q_MAX_LB_CTRL_SET_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_rate_egrQueueMaxBwEn_gget + * Description: + * Get port egress queue max bandwidth enable + * Input: + * port - Port id + * qid - Queue ID + * pEnable - 1:enable, 0:disable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid IFG parameter. + * RT_ERR_INBW_RATE - Invalid ingress rate parameter. + * Note: + */ +rtk_api_ret_t dal_rtl8373_rate_egrQueueMaxBwEn_get(rtk_port_t port, rtk_qid_t qid, rtk_enable_t * pEnable) +{ + rtk_uint32 retVal = 0; + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + if(port > EBW_CTRL_MAX_PORT_ID) + return RT_ERR_QOS_EBW_PORT_ID; + + + if((retVal = rtl8373_getAsicRegBit(RTL8373_EGBW_PORT_Q_MAX_LB_CTRL_SET_ADDR(port, qid), RTL8373_EGBW_PORT_Q_MAX_LB_CTRL_SET_EN_OFFSET, pEnable)) != RT_ERR_OK) + return retVal; + + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_rate_egrQueueMaxBwRate_set + * Description: + * Set port egress queue max bandwidth rate + * Input: + * port - Port id + * qid - Queue ID + * rate - Rate of share meter(uint: kpbs) + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid IFG parameter. + * RT_ERR_INBW_RATE - Invalid ingress rate parameter. + * Note: + */ +rtk_api_ret_t dal_rtl8373_rate_egrQueueMaxBwRate_set(rtk_port_t port, rtk_qid_t qid, rtk_rate_t rate) +{ + rtk_uint32 retVal = 0; + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + if(port > EBW_CTRL_MAX_PORT_ID) + return RT_ERR_QOS_EBW_PORT_ID; + + if(rate >= EBW_CTRL_RATE_MAX) + return RT_ERR_INPUT; + + + if((retVal = rtl8373_setAsicRegBits(RTL8373_EGBW_PORT_Q_MAX_LB_CTRL_SET_ADDR(port, qid), RTL8373_EGBW_PORT_Q_MAX_LB_CTRL_SET_RATE_MASK, rate)) != RT_ERR_OK) + return retVal; + + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_rate_egrQueueMaxBwRate_get + * Description: + * Get port egress queue max bandwidth rate + * Input: + * port - Port id + * qid - Queue ID + * rate - Rate of share meter(uint: kpbs) + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid IFG parameter. + * RT_ERR_INBW_RATE - Invalid ingress rate parameter. + * Note: + */ +rtk_api_ret_t dal_rtl8373_rate_egrQueueMaxBwRate_get(rtk_port_t port, rtk_qid_t qid, rtk_rate_t * pRate) +{ + rtk_uint32 retVal = 0; + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + if(port > EBW_CTRL_MAX_PORT_ID) + return RT_ERR_QOS_EBW_PORT_ID; + + if(pRate == NULL) + return RT_ERR_NULL_POINTER; + + + if((retVal = rtl8373_getAsicRegBits(RTL8373_EGBW_PORT_Q_MAX_LB_CTRL_SET_ADDR(port, qid), RTL8373_EGBW_PORT_Q_MAX_LB_CTRL_SET_RATE_MASK, pRate)) != RT_ERR_OK) + return retVal; + + + return RT_ERR_OK; +} + + + + diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_rate.h b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_rate.h new file mode 100755 index 00000000..bad4084f --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_rate.h @@ -0,0 +1,355 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8373 switch high-level API + * + * Feature : The file includes Rate module high-layer API defination + * + */ + +#ifndef __DAL_RTL8373_RATE_H__ +#define __DAL_RTL8373_RATE_H__ +#include + +/* Function Name: + * dal_rtl8373_rate_igrBwCtrlPortEn_set + * Description: + * Enable or disable port ingress bandwidth control + * Input: + * port - Port id + * bwEn - enable ingress bandwidth control or not + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid IFG parameter. + * RT_ERR_INBW_RATE - Invalid ingress rate parameter. + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8373_rate_igrBwCtrlPortEn_set(rtk_port_t port, rtk_enable_t bwEn); + +/* Function Name: + * dal_rtl8373_rate_igrBwCtrlPortEn_get + * Description: + * Enable or disable port ingress bandwidth control + * Input: + * port - Port id + * + * Output: + * pBwEn - Port ingress bandwidth control state + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid IFG parameter. + * RT_ERR_INBW_RATE - Invalid ingress rate parameter. + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8373_rate_igrBwCtrlPortEn_get(rtk_port_t port, rtk_enable_t *pBwEn); + +/* Function Name: + * dal_rtl8373_rate_igrBwCtrlRate_set + * Description: + * Set port ingress bandwidth control rate and FC config + * Input: + * port - Port id + * rate - Rate of share meter(uint: kpbs) + * fcEn - enable flow control or not, ENABLE:use flow control DISABLE:drop + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid IFG parameter. + * RT_ERR_INBW_RATE - Invalid ingress rate parameter. + * Note: + * The rate unit is 16 kbps and the range is from 16k to 10G. The granularity of rate is 16 kbps. + * The ifg_include parameter is used for rate calculation with/without inter-frame-gap and preamble. + */ +extern rtk_api_ret_t dal_rtl8373_rate_igrBwCtrlRate_set(rtk_port_t port, rtk_rate_t rate, rtk_enable_t fcEn); + +/* Function Name: + * dal_rtl8373_rate_igrBwCtrlRate_get + * Description: + * Get port ingress bandwidth control rate and FC config + * Input: + * port - Port id + * + * Output: + * pRate - Rate of share meter(uint: kpbs) + * pFcEn - enable flow control or not, ENABLE:use flow control DISABLE:drop + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid IFG parameter. + * RT_ERR_INBW_RATE - Invalid ingress rate parameter. + * Note: + * The rate unit is 16 kbps and the range is from 16k to 10G. The granularity of rate is 16 kbps. + * The ifg_include parameter is used for rate calculation with/without inter-frame-gap and preamble. + */ +extern rtk_api_ret_t dal_rtl8373_rate_igrBwCtrlRate_get(rtk_port_t port, rtk_rate_t *pRate, rtk_enable_t *pFcEn); + +/* Function Name: + * dal_rtl8373_rate_igrBwCtrlIfg_set + * Description: + * Set ingress bandwidth control include Preamble and IFG or not + * Input: + * ifgInclude - include or not, ENABLE:include DISABLE:exclude + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid IFG parameter. + * RT_ERR_INBW_RATE - Invalid ingress rate parameter. + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8373_rate_igrBwCtrlIfg_set(rtk_enable_t ifgInclude); + +/* Function Name: + * dal_rtl8373_rate_igrBwCtrlIfg_get + * Description: + * Get ingress bandwidth control include 8B Preamble and 12B IFG or not + * Input: + * None + * Output: + * ifgInclude - include or not, ENABLE:include DISABLE:exclude + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid IFG parameter. + * RT_ERR_INBW_RATE - Invalid ingress rate parameter. + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8373_rate_igrBwCtrlIfg_get(rtk_enable_t *pIfgInclude); + +/* Function Name: + * dal_rtl8373_rate_igrBwCtrlCongestSts_get + * Description: + * Get port_n ingress bandwidth exceed leaky bucket high-on or not + * Input: + * port - port Idx + * Output: + * pCongestSts - Indicate ingress bandwidth exceed Pn_IGR_LB_ HIGH _ON for port n. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid IFG parameter. + * RT_ERR_INBW_RATE - Invalid ingress rate parameter. + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8373_rate_igrBwCtrlCongestSts_get(rtk_port_t port, rtk_rate_igrBwCongestSts_t *pCongestSts); + + +/* Function Name: + * dal_rtl8373_rate_egrBwCtrlPortEn_set + * Description: + * Enable or disable port egress bandwidth control + * Input: + * port - Port id + * bwEn - enable egress bandwidth control or not + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid IFG parameter. + * RT_ERR_INBW_RATE - Invalid ingress rate parameter. + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8373_rate_egrBwCtrlPortEn_set(rtk_port_t port, rtk_enable_t bwEn); + +/* Function Name: + * dal_rtl8373_rate_egrBwCtrlPortEn_get + * Description: + * Enable or disable port egress bandwidth control + * Input: + * port - Port id + * + * Output: + * pBwEn - Port egress bandwidth control state + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid IFG parameter. + * RT_ERR_INBW_RATE - Invalid ingress rate parameter. + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8373_rate_egrBwCtrlPortEn_get(rtk_port_t port, rtk_enable_t *pBwEn); + + +/* Function Name: + * dal_rtl8373_rate_egrBwCtrlRate_set + * Description: + * Set port egress bandwidth control rate and IPG config + * Input: + * port - Port id + * rate - Rate of share meter(uint: kpbs) + * ipg - include ipg or not, ENABLE:include DISABLE:exclude + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid IFG parameter. + * RT_ERR_INBW_RATE - Invalid ingress rate parameter. + * Note: + * The rate unit is 16 kbps and the range is from 16k to 10G. The granularity of rate is 16 kbps. + * The ifg_include parameter is used for rate calculation with/without inter-frame-gap and preamble. + */ +extern rtk_api_ret_t dal_rtl8373_rate_egrBwCtrlRate_set(rtk_port_t port, rtk_rate_t rate, rtk_enable_t ipg); + +/* Function Name: + * dal_rtl8373_rate_egrBwCtrlRate_get + * Description: + * Get port egress bandwidth control rate and IPG config + * Input: + * port - Port id + * + * Output: + * pRate - Rate of share meter(uint: kpbs) + * pIpg - include ipg or not, ENABLE:include DISABLE:exclude + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid IFG parameter. + * RT_ERR_INBW_RATE - Invalid ingress rate parameter. + * Note: + * The rate unit is 16 kbps and the range is from 16k to 10G. The granularity of rate is 16 kbps. + * The ifg_include parameter is used for rate calculation with/without inter-frame-gap and preamble. + */ +extern rtk_api_ret_t dal_rtl8373_rate_egrBwCtrlRate_get(rtk_port_t port, rtk_rate_t *pRate, rtk_enable_t *pIpg); + + + +/* Function Name: + * dal_rtl8373_rate_egrQueueMaxBwEn_set + * Description: + * Set port egress queue max bandwidth enable + * Input: + * port - Port id + * qid - Queue ID + * enable - 1:enable, 0:disable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid IFG parameter. + * RT_ERR_INBW_RATE - Invalid ingress rate parameter. + * Note: + */ +extern rtk_api_ret_t dal_rtl8373_rate_egrQueueMaxBwEn_set(rtk_port_t port, rtk_qid_t qid, rtk_enable_t enable); + + +/* Function Name: + * dal_rtl8373_rate_egrQueueMaxBwEn_gget + * Description: + * Get port egress queue max bandwidth enable + * Input: + * port - Port id + * qid - Queue ID + * pEnable - 1:enable, 0:disable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid IFG parameter. + * RT_ERR_INBW_RATE - Invalid ingress rate parameter. + * Note: + */ +extern rtk_api_ret_t dal_rtl8373_rate_egrQueueMaxBwEn_get(rtk_port_t port, rtk_qid_t qid, rtk_enable_t * pEnable); + + +/* Function Name: + * dal_rtl8373_rate_egrQueueMaxBwRate_set + * Description: + * Set port egress queue max bandwidth rate + * Input: + * port - Port id + * qid - Queue ID + * rate - Rate of share meter(uint: kpbs) + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid IFG parameter. + * RT_ERR_INBW_RATE - Invalid ingress rate parameter. + * Note: + */ +extern rtk_api_ret_t dal_rtl8373_rate_egrQueueMaxBwRate_set(rtk_port_t port, rtk_qid_t qid, rtk_rate_t rate); + + +/* Function Name: + * dal_rtl8373_rate_egrQueueMaxBwRate_get + * Description: + * Get port egress queue max bandwidth rate + * Input: + * port - Port id + * qid - Queue ID + * rate - Rate of share meter(uint: kpbs) + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid IFG parameter. + * RT_ERR_INBW_RATE - Invalid ingress rate parameter. + * Note: + */ +extern rtk_api_ret_t dal_rtl8373_rate_egrQueueMaxBwRate_get(rtk_port_t port, rtk_qid_t qid, rtk_rate_t * pRate); + + + + + + + + +#endif /* __DAL_RTL8373_RATE_H__ */ + + diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_rma.c b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_rma.c new file mode 100755 index 00000000..1af880d4 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_rma.c @@ -0,0 +1,533 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8373 + * Feature : Here is a list of all functions and variables in RMA module. + * + */ + +#include +#include +#include +#include +#include + + +/* Function Name: + * dal_rtl8373_asicRma_set + * Description: + * Set reserved multicast address for CPU trapping + * Input: + * index - reserved multicast LSB byte, 0x00~0x2F is available value + * pRmacfg - type of RMA for trapping frame type setting + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RMA_ADDR - Invalid RMA address index + * Note: + * None + */ +ret_t dal_rtl8373_asicRma_set(rtk_uint32 index, rtk_rmaParam_t* pRmacfg) +{ + ret_t retVal; + + if(index > RTL8373_RMAMAX) + return RT_ERR_RMA_ADDR; + + if( (index >= 0x4 && index <= 0x7) || (index >= 0x9 && index <= 0x0C) || (0x0F == index)) + index = 0x04; + else if(index == 0x8) + index = 0x5; + else if(index == 0xD) + index = 0x6; + else if(index == 0xE) + index = 0x7; + else if(index == 0x10) + index = 0x8; + else if(index == 0x11) + index = 0x9; + else if(index == 0x12) + index = 0xA; + else if((index >= 0x13 && index <= 0x17) || (0x19 == index) || (index >= 0x1B && index <= 0x1f)) + index = 0xB; + else if(index == 0x18) + index = 0xC; + else if(index == 0x1A) + index = 0xD; + else if(index == 0x20) + index = 0xE; + else if(index == 0x21) + index = 0xF; + else if(index >= 0x22 && index <= 0x2F) + index = 0x10; + + retVal = rtl8373_setAsicRegBits(RTL8373_RMA_OP_CTRL_00_ADDR+index*4, RTL8373_RMA_OP_CTRL_00_RMA_ACT_00_MASK, pRmacfg->operation); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8373_setAsicRegBit(RTL8373_RMA_OP_CTRL_00_ADDR+index*4, RTL8373_RMA_OP_CTRL_00_DIS_STORM_CTRL_00_OFFSET, pRmacfg->discard_storm_filter); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8373_setAsicRegBit(RTL8373_RMA_OP_CTRL_00_ADDR+index*4, RTL8373_RMA_OP_CTRL_00_CKEEP_00_OFFSET, pRmacfg->keep_format); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8373_setAsicRegBit(RTL8373_RMA_OP_CTRL_00_ADDR+index*4, RTL8373_RMA_OP_CTRL_00_VLAN_LEAKY_00_OFFSET, pRmacfg->vlan_leaky); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8373_setAsicRegBit(RTL8373_RMA_OP_CTRL_00_ADDR+index*4, RTL8373_RMA_OP_CTRL_00_PISO_LEAKY_00_OFFSET, pRmacfg->portiso_leaky); + if(retVal != RT_ERR_OK) + return retVal; + + return rtl8373_setAsicRegBits(RTL8373_RMA_CFG_ADDR, RTL8373_RMA_CFG_RMA_TRAP_PRI_MASK, pRmacfg->trap_priority); +} + + +/* Function Name: + * dal_rtl8373_asicRma_get + * Description: + * Get reserved multicast address for CPU trapping + * Input: + * index - reserved multicast LSB byte, 0x00~0x2F is available value + * rmacfg - type of RMA for trapping frame type setting + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RMA_ADDR - Invalid RMA address index + * Note: + * None + */ +ret_t dal_rtl8373_asicRma_get(rtk_uint32 index, rtk_rmaParam_t* pRmacfg) +{ + ret_t retVal; + + + if( (index >= 0x4 && index <= 0x7) || (index >= 0x9 && index <= 0x0C) || (0x0F == index)) + index = 0x04; + else if(index == 0x8) + index = 0x5; + else if(index == 0xD) + index = 0x6; + else if(index == 0xE) + index = 0x7; + else if(index == 0x10) + index = 0x8; + else if(index == 0x11) + index = 0x9; + else if(index == 0x12) + index = 0xA; + else if((index >= 0x13 && index <= 0x17) || (0x19 == index) || (index >= 0x1B && index <= 0x1f)) + index = 0xB; + else if(index == 0x18) + index = 0xC; + else if(index == 0x1A) + index = 0xD; + else if(index == 0x20) + index = 0xE; + else if(index == 0x21) + index = 0xF; + else if(index >= 0x22 && index <= 0x2F) + index = 0x10; + + + retVal = rtl8373_getAsicRegBits(RTL8373_RMA_OP_CTRL_00_ADDR+index*4, RTL8373_RMA_OP_CTRL_00_RMA_ACT_00_MASK, &pRmacfg->operation); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8373_getAsicRegBit(RTL8373_RMA_OP_CTRL_00_ADDR+index*4, RTL8373_RMA_OP_CTRL_00_DIS_STORM_CTRL_00_OFFSET, &pRmacfg->discard_storm_filter); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8373_getAsicRegBit(RTL8373_RMA_OP_CTRL_00_ADDR+index*4, RTL8373_RMA_OP_CTRL_00_CKEEP_00_OFFSET, &pRmacfg->keep_format); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8373_getAsicRegBit(RTL8373_RMA_OP_CTRL_00_ADDR+index*4, RTL8373_RMA_OP_CTRL_00_VLAN_LEAKY_00_OFFSET, &pRmacfg->vlan_leaky); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8373_getAsicRegBit(RTL8373_RMA_OP_CTRL_00_ADDR+index*4, RTL8373_RMA_OP_CTRL_00_PISO_LEAKY_00_OFFSET, &pRmacfg->portiso_leaky); + if(retVal != RT_ERR_OK) + return retVal; + + + retVal = rtl8373_getAsicRegBits(RTL8373_RMA_CFG_ADDR, RTL8373_RMA_CFG_RMA_TRAP_PRI_MASK, &pRmacfg->trap_priority); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_asicRmaCdp_set + * Description: + * Set CDP(Cisco Discovery Protocol) for CPU trapping + * Input: + * pRmacfg - type of RMA for trapping frame type setting + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RMA_ADDR - Invalid RMA address index + * Note: + * None + */ +ret_t dal_rtl8373_asicRmaCdp_set(rtk_rmaParam_t* pRmacfg) +{ + ret_t retVal; + + if(pRmacfg->operation >= RMAOP_END) + return RT_ERR_RMA_ACTION; + + if(pRmacfg->trap_priority > RTL8373_PRIMAX) + return RT_ERR_QOS_INT_PRIORITY; + + retVal = rtl8373_setAsicRegBits(RTL8373_RMA_OP_CTRL_CDP_ADDR, RTL8373_RMA_OP_CTRL_CDP_RMA_ACT_CDP_MASK, pRmacfg->operation); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8373_setAsicRegBit(RTL8373_RMA_OP_CTRL_CDP_ADDR, RTL8373_RMA_OP_CTRL_CDP_DIS_STORM_CTRL_CDP_OFFSET, pRmacfg->discard_storm_filter); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8373_setAsicRegBit(RTL8373_RMA_OP_CTRL_CDP_ADDR, RTL8373_RMA_OP_CTRL_CDP_CKEEP_CDP_OFFSET, pRmacfg->keep_format); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8373_setAsicRegBit(RTL8373_RMA_OP_CTRL_CDP_ADDR, RTL8373_RMA_OP_CTRL_CDP_VLAN_LEAKY_CDP_OFFSET, pRmacfg->vlan_leaky); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8373_setAsicRegBit(RTL8373_RMA_OP_CTRL_CDP_ADDR, RTL8373_RMA_OP_CTRL_CDP_PISO_LEAKY_CDP_OFFSET, pRmacfg->portiso_leaky); + if(retVal != RT_ERR_OK) + return retVal; + + return rtl8373_setAsicRegBits(RTL8373_RMA_CFG_ADDR, RTL8373_RMA_CFG_RMA_TRAP_PRI_MASK, pRmacfg->trap_priority); +} + +/* Function Name: + * dal_rtl8373_asicRmaCdp_get + * Description: + * Get CDP(Cisco Discovery Protocol) for CPU trapping + * Input: + * None + * Output: + * pRmacfg - type of RMA for trapping frame type setting + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RMA_ADDR - Invalid RMA address index + * Note: + * None + */ +ret_t dal_rtl8373_asicRmaCdp_get(rtk_rmaParam_t* pRmacfg) +{ + ret_t retVal; + + retVal = rtl8373_getAsicRegBits(RTL8373_RMA_OP_CTRL_CDP_ADDR, RTL8373_RMA_OP_CTRL_CDP_RMA_ACT_CDP_MASK, &pRmacfg->operation); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8373_getAsicRegBit(RTL8373_RMA_OP_CTRL_CDP_ADDR, RTL8373_RMA_OP_CTRL_CDP_DIS_STORM_CTRL_CDP_OFFSET, &pRmacfg->discard_storm_filter); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8373_getAsicRegBit(RTL8373_RMA_OP_CTRL_CDP_ADDR, RTL8373_RMA_OP_CTRL_CDP_CKEEP_CDP_OFFSET, &pRmacfg->keep_format); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8373_getAsicRegBit(RTL8373_RMA_OP_CTRL_CDP_ADDR, RTL8373_RMA_OP_CTRL_CDP_VLAN_LEAKY_CDP_OFFSET, &pRmacfg->vlan_leaky); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8373_getAsicRegBit(RTL8373_RMA_OP_CTRL_CDP_ADDR, RTL8373_RMA_OP_CTRL_CDP_PISO_LEAKY_CDP_OFFSET, &pRmacfg->portiso_leaky); + if(retVal != RT_ERR_OK) + return retVal; + + + retVal = rtl8373_getAsicRegBits(RTL8373_RMA_CFG_ADDR, RTL8373_RMA_CFG_RMA_TRAP_PRI_MASK, &pRmacfg->trap_priority); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; + +} + + +/* Function Name: + * dal_rtl8373_asicRmaCsstp_set + * Description: + * Set CSSTP(Cisco Shared Spanning Tree Protocol) for CPU trapping + * Input: + * pRmacfg - type of RMA for trapping frame type setting + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RMA_ADDR - Invalid RMA address index + * Note: + * None + */ +ret_t dal_rtl8373_asicRmaCsstp_set(rtk_rmaParam_t* pRmacfg) +{ + ret_t retVal; + + if(pRmacfg->operation >= RMAOP_END) + return RT_ERR_RMA_ACTION; + + if(pRmacfg->trap_priority > RTL8373_PRIMAX) + return RT_ERR_QOS_INT_PRIORITY; + + retVal = rtl8373_setAsicRegBits(RTL8373_RMA_OP_CTRL_CSSTP_ADDR, RTL8373_RMA_OP_CTRL_CSSTP_RMA_ACT_CSSTP_MASK, pRmacfg->operation); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8373_setAsicRegBit(RTL8373_RMA_OP_CTRL_CSSTP_ADDR, RTL8373_RMA_OP_CTRL_CSSTP_DIS_STORM_CTRL_CSSTP_OFFSET, pRmacfg->discard_storm_filter); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8373_setAsicRegBit(RTL8373_RMA_OP_CTRL_CSSTP_ADDR, RTL8373_RMA_OP_CTRL_CSSTP_CKEEP_CSSTP_OFFSET, pRmacfg->keep_format); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8373_setAsicRegBit(RTL8373_RMA_OP_CTRL_CSSTP_ADDR, RTL8373_RMA_OP_CTRL_CSSTP_VLAN_LEAKY_CSSTP_OFFSET, pRmacfg->vlan_leaky); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8373_setAsicRegBit(RTL8373_RMA_OP_CTRL_CSSTP_ADDR, RTL8373_RMA_OP_CTRL_CSSTP_PISO_LEAKY_CSSTP_OFFSET, pRmacfg->portiso_leaky); + if(retVal != RT_ERR_OK) + return retVal; + + return rtl8373_setAsicRegBits(RTL8373_RMA_CFG_ADDR, RTL8373_RMA_CFG_RMA_TRAP_PRI_MASK, pRmacfg->trap_priority); +} + + +/* Function Name: + * dal_rtl8373_asicRmaCsstp_get + * Description: + * Get CSSTP(Cisco Shared Spanning Tree Protocol) for CPU trapping + * Input: + * None + * Output: + * pRmacfg - type of RMA for trapping frame type setting + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RMA_ADDR - Invalid RMA address index + * Note: + * None + */ +ret_t dal_rtl8373_asicRmaCsstp_get(rtk_rmaParam_t* pRmacfg) +{ + ret_t retVal; + + retVal = rtl8373_getAsicRegBits(RTL8373_RMA_OP_CTRL_CSSTP_ADDR, RTL8373_RMA_OP_CTRL_CSSTP_RMA_ACT_CSSTP_MASK, &pRmacfg->operation); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8373_getAsicRegBit(RTL8373_RMA_OP_CTRL_CSSTP_ADDR, RTL8373_RMA_OP_CTRL_CSSTP_DIS_STORM_CTRL_CSSTP_OFFSET, &pRmacfg->discard_storm_filter); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8373_getAsicRegBit(RTL8373_RMA_OP_CTRL_CSSTP_ADDR, RTL8373_RMA_OP_CTRL_CSSTP_CKEEP_CSSTP_OFFSET, &pRmacfg->keep_format); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8373_getAsicRegBit(RTL8373_RMA_OP_CTRL_CSSTP_ADDR, RTL8373_RMA_OP_CTRL_CSSTP_VLAN_LEAKY_CSSTP_OFFSET, &pRmacfg->vlan_leaky); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8373_getAsicRegBit(RTL8373_RMA_OP_CTRL_CSSTP_ADDR, RTL8373_RMA_OP_CTRL_CSSTP_PISO_LEAKY_CSSTP_OFFSET, &pRmacfg->portiso_leaky); + if(retVal != RT_ERR_OK) + return retVal; + + + retVal = rtl8373_getAsicRegBits(RTL8373_RMA_CFG_ADDR, RTL8373_RMA_CFG_RMA_TRAP_PRI_MASK, &pRmacfg->trap_priority); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + + +/* Function Name: + * dal_rtl8373_asicRmaLldp_set + * Description: + * Set LLDP for CPU trapping + * Input: + * pRmacfg - type of RMA for trapping frame type setting + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RMA_ADDR - Invalid RMA address index + * Note: + * None + */ +ret_t dal_rtl8373_asicRmaLldp_set(rtk_uint32 enabled, rtk_rmaParam_t* pRmacfg) +{ + ret_t retVal; + + if(enabled > 1) + return RT_ERR_ENABLE; + + if(pRmacfg->operation >= RMAOP_END) + return RT_ERR_RMA_ACTION; + + if(pRmacfg->trap_priority > RTL8373_PRIMAX) + return RT_ERR_QOS_INT_PRIORITY; + + retVal = rtl8373_setAsicRegBit(RTL8373_RMA_CFG_ADDR, RTL8373_RMA_CFG_LLDP_EN_OFFSET,enabled); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8373_setAsicRegBits(RTL8373_RMA_OP_CTRL_LLDP_ADDR, RTL8373_RMA_OP_CTRL_LLDP_RMA_ACT_LLDP_MASK, pRmacfg->operation); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8373_setAsicRegBit(RTL8373_RMA_OP_CTRL_LLDP_ADDR, RTL8373_RMA_OP_CTRL_LLDP_DIS_STORM_CTRL_LLDP_OFFSET, pRmacfg->discard_storm_filter); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8373_setAsicRegBit(RTL8373_RMA_OP_CTRL_LLDP_ADDR, RTL8373_RMA_OP_CTRL_LLDP_CKEEP_LLDP_OFFSET, pRmacfg->keep_format); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8373_setAsicRegBit(RTL8373_RMA_OP_CTRL_LLDP_ADDR, RTL8373_RMA_OP_CTRL_LLDP_VLAN_LEAKY_LLDP_OFFSET, pRmacfg->vlan_leaky); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8373_setAsicRegBit(RTL8373_RMA_OP_CTRL_LLDP_ADDR, RTL8373_RMA_OP_CTRL_LLDP_PISO_LEAKY_LLDP_OFFSET, pRmacfg->portiso_leaky); + if(retVal != RT_ERR_OK) + return retVal; + + return rtl8373_setAsicRegBits(RTL8373_RMA_CFG_ADDR, RTL8373_RMA_CFG_RMA_TRAP_PRI_MASK, pRmacfg->trap_priority); +} + + +/* Function Name: + * dal_rtl8373_asicRmaLldp_get + * Description: + * Get LLDP for CPU trapping + * Input: + * None + * Output: + * pRmacfg - type of RMA for trapping frame type setting + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RMA_ADDR - Invalid RMA address index + * Note: + * None + */ +ret_t dal_rtl8373_asicRmaLldp_get(rtk_uint32 *pEnabled, rtk_rmaParam_t* pRmacfg) +{ + ret_t retVal; + + retVal = rtl8373_getAsicRegBit(RTL8373_RMA_CFG_ADDR, RTL8373_RMA_CFG_LLDP_EN_OFFSET,pEnabled); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8373_getAsicRegBits(RTL8373_RMA_OP_CTRL_LLDP_ADDR, RTL8373_RMA_OP_CTRL_LLDP_RMA_ACT_LLDP_MASK, &pRmacfg->operation); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8373_getAsicRegBit(RTL8373_RMA_OP_CTRL_LLDP_ADDR, RTL8373_RMA_OP_CTRL_LLDP_DIS_STORM_CTRL_LLDP_OFFSET, &pRmacfg->discard_storm_filter); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8373_getAsicRegBit(RTL8373_RMA_OP_CTRL_LLDP_ADDR, RTL8373_RMA_OP_CTRL_LLDP_CKEEP_LLDP_OFFSET, &pRmacfg->keep_format); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8373_getAsicRegBit(RTL8373_RMA_OP_CTRL_LLDP_ADDR, RTL8373_RMA_OP_CTRL_LLDP_VLAN_LEAKY_LLDP_OFFSET, &pRmacfg->vlan_leaky); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8373_getAsicRegBit(RTL8373_RMA_OP_CTRL_LLDP_ADDR, RTL8373_RMA_OP_CTRL_LLDP_PISO_LEAKY_LLDP_OFFSET, &pRmacfg->portiso_leaky); + if(retVal != RT_ERR_OK) + return retVal; + + + retVal = rtl8373_getAsicRegBits(RTL8373_RMA_CFG_ADDR, RTL8373_RMA_CFG_RMA_TRAP_PRI_MASK, &pRmacfg->trap_priority); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_asicRmaTrapPri_set + * Description: + * Set RMA function trap priority + * Input: + * pri - trap priority for all RMA + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RMA_ADDR - Invalid RMA address index + * Note: + * None + */ + +ret_t dal_rtl8373_asicRmaTrapPri_set(rtk_uint32 pri) +{ + ret_t retVal; + retVal = rtl8373_setAsicRegBits(RTL8373_RMA_CFG_ADDR, RTL8373_RMA_CFG_RMA_TRAP_PRI_MASK, pri); + + return retVal; +} + + +/* Function Name: + * dal_rtl8373_asicRmaTrapPri_get + * Description: + * Set RMA function trap priority + * Input: + * pri - trap priority for all RMA + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RMA_ADDR - Invalid RMA address index + * Note: + * None + */ + +ret_t dal_rtl8373_asicRmaTrapPri_get(rtk_uint32 * pri) +{ + ret_t retVal; + retVal = rtl8373_getAsicRegBits(RTL8373_RMA_CFG_ADDR, RTL8373_RMA_CFG_RMA_TRAP_PRI_MASK, pri); + + return retVal; +} + + + + diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_rma.h b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_rma.h new file mode 100755 index 00000000..6025df47 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_rma.h @@ -0,0 +1,206 @@ +#ifndef __DAL_RTL8373_RMA_H__ +#define __DAL_RTL8373_RMA_H__ + +#include + + +#define RTL8373_RMAMAX 0x2F + + + + +/* Function Name: + * dal_rtl8373_asicRma_set + * Description: + * Set reserved multicast address for CPU trapping + * Input: + * index - reserved multicast LSB byte, 0x00~0x2F is available value + * pRmacfg - type of RMA for trapping frame type setting + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RMA_ADDR - Invalid RMA address index + * Note: + * None + */ +extern ret_t dal_rtl8373_asicRma_set(rtk_uint32 index, rtk_rmaParam_t* pRmacfg); + + + +/* Function Name: + * dal_rtl8373_asicRma_get + * Description: + * Get reserved multicast address for CPU trapping + * Input: + * index - reserved multicast LSB byte, 0x00~0x2F is available value + * rmacfg - type of RMA for trapping frame type setting + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RMA_ADDR - Invalid RMA address index + * Note: + * None + */ +extern ret_t dal_rtl8373_asicRma_get(rtk_uint32 index, rtk_rmaParam_t* pRmacfg); + + + +/* Function Name: + * dal_rtl8373_asicRmaCdp_set + * Description: + * Set CDP(Cisco Discovery Protocol) for CPU trapping + * Input: + * pRmacfg - type of RMA for trapping frame type setting + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RMA_ADDR - Invalid RMA address index + * Note: + * None + */ +extern ret_t dal_rtl8373_asicRmaCdp_set(rtk_rmaParam_t* pRmacfg); + + +/* Function Name: + * dal_rtl8373_asicRmaCdp_get + * Description: + * Get CDP(Cisco Discovery Protocol) for CPU trapping + * Input: + * None + * Output: + * pRmacfg - type of RMA for trapping frame type setting + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RMA_ADDR - Invalid RMA address index + * Note: + * None + */ +extern ret_t dal_rtl8373_asicRmaCdp_get(rtk_rmaParam_t* pRmacfg); + + + +/* Function Name: + * dal_rtl8373_asicRmaCsstp_set + * Description: + * Set CSSTP(Cisco Shared Spanning Tree Protocol) for CPU trapping + * Input: + * pRmacfg - type of RMA for trapping frame type setting + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RMA_ADDR - Invalid RMA address index + * Note: + * None + */ +extern ret_t dal_rtl8373_asicRmaCsstp_set(rtk_rmaParam_t* pRmacfg); + + + +/* Function Name: + * dal_rtl8373_asicRmaCsstp_get + * Description: + * Get CSSTP(Cisco Shared Spanning Tree Protocol) for CPU trapping + * Input: + * None + * Output: + * pRmacfg - type of RMA for trapping frame type setting + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RMA_ADDR - Invalid RMA address index + * Note: + * None + */ +extern ret_t dal_rtl8373_asicRmaCsstp_get(rtk_rmaParam_t* pRmacfg); + + + + +/* Function Name: + * dal_rtl8373_asicRmaLldp_set + * Description: + * Set LLDP for CPU trapping + * Input: + * pRmacfg - type of RMA for trapping frame type setting + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RMA_ADDR - Invalid RMA address index + * Note: + * None + */ +extern ret_t dal_rtl8373_asicRmaLldp_set(rtk_uint32 enabled, rtk_rmaParam_t* pRmacfg); + + + +/* Function Name: + * dal_rtl8373_asicRmaLldp_get + * Description: + * Get LLDP for CPU trapping + * Input: + * None + * Output: + * pRmacfg - type of RMA for trapping frame type setting + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RMA_ADDR - Invalid RMA address index + * Note: + * None + */ +extern ret_t dal_rtl8373_asicRmaLldp_get(rtk_uint32 *pEnabled, rtk_rmaParam_t* pRmacfg); + + + +/* Function Name: + * dal_rtl8373_asicRmaTrapPri_set + * Description: + * Set RMA function trap priority + * Input: + * pri - trap priority for all RMA + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RMA_ADDR - Invalid RMA address index + * Note: + * None + */ + +extern ret_t dal_rtl8373_asicRmaTrapPri_set(rtk_uint32 pri); + + +/* Function Name: + * dal_rtl8373_asicRmaTrapPri_get + * Description: + * Set RMA function trap priority + * Input: + * pri - trap priority for all RMA + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RMA_ADDR - Invalid RMA address index + * Note: + * None + */ + +extern ret_t dal_rtl8373_asicRmaTrapPri_get(rtk_uint32 * pri); + + + +#endif + diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_rtkpp.c b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_rtkpp.c new file mode 100755 index 00000000..4769eb65 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_rtkpp.c @@ -0,0 +1,581 @@ +/* + * Copyright (C) 2012 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision: $ + * $Date: $ + * + * Purpose : Declaration of RLDP and RLPP API + * + * Feature : The file have include the following module and sub-modules + * 1) RLDP and RLPP configuration and status + * + */ + + +/* + * Include Files + */ +#include +#include +#include +#include + + +/* Function Name: + * dal_rtl8373_rldp_config_set + * Description: + * Set RLDP module configuration + * Input: + * pConfig - configuration structure of RLDP + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT + * RT_ERR_NULL_POINTER + * Note: + * None + */ +rtk_api_ret_t dal_rtl8373_rldp_config_set(rtk_rldp_config_t *pConfig) +{ + rtk_api_ret_t retVal; + rtk_uint32 *magic; + rtk_uint32 regData; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (pConfig->rldp_enable >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if (pConfig->trigger_mode >= RTK_RLDP_TRIGGER_END) + return RT_ERR_INPUT; + + if (pConfig->compare_type >= RTK_RLDP_CMPTYPE_END) + return RT_ERR_INPUT; + + if (pConfig->num_check >= RTK_RLDP_NUM_MAX) + return RT_ERR_INPUT; + + if (pConfig->interval_check >= RTK_RLDP_INTERVAL_MAX) + return RT_ERR_INPUT; + + if (pConfig->num_loop >= RTK_RLDP_NUM_MAX) + return RT_ERR_INPUT; + + if (pConfig->interval_loop >= RTK_RLDP_INTERVAL_MAX) + return RT_ERR_INPUT; + + + if ((retVal = rtl8373_setAsicRegBit(RTL8373_RLDP_RLPP_CTRL_ADDR, RTL8373_RLDP_RLPP_CTRL_RLDP_EN_OFFSET, pConfig->rldp_enable))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_setAsicRegBit(RTL8373_RLDP_RLPP_CTRL_ADDR, RTL8373_RLDP_RLPP_CTRL_RLDP_MODE_OFFSET, pConfig->trigger_mode))!=RT_ERR_OK) + return retVal; + + + magic = (rtk_uint32*)&pConfig->magic; + regData = *magic; + if ((retVal = rtl8373_setAsicReg(RTL8373_MAGIC_NUM0_ADDR, regData))!=RT_ERR_OK) + return retVal; + + magic++; + regData = *magic & 0xffff; + if ((retVal = rtl8373_setAsicReg(RTL8373_MAGIC_NUM1_ADDR, regData))!=RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8373_setAsicRegBit(RTL8373_RLDP_RLPP_CTRL_ADDR, RTL8373_RLDP_RLPP_CTRL_COMP_ID_OFFSET, pConfig->compare_type))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_RETRY_CTRL_ADDR, RTL8373_RETRY_CTRL_RETRY_CHK_MASK, pConfig->num_check))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_PERIOD_CTRL_ADDR, RTL8373_PERIOD_CTRL_PERIOD_CHK_MASK, pConfig->interval_check))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_RETRY_CTRL_ADDR, RTL8373_RETRY_CTRL_RETRY_LOOP_MASK, pConfig->num_loop))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_PERIOD_CTRL_ADDR, RTL8373_PERIOD_CTRL_PERIOD_LOOP_MASK, pConfig->interval_loop))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + + +/* Function Name: + * dal_rtl8373_rldp_config_get + * Description: + * Get RLDP module configuration + * Input: + * None + * Output: + * pConfig - configuration structure of RLDP + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT + * RT_ERR_NULL_POINTER + * Note: + * None + */ +rtk_api_ret_t dal_rtl8373_rldp_config_get(rtk_rldp_config_t *pConfig) +{ + rtk_api_ret_t retVal; + rtk_uint32 *magic; + rtk_uint32 regData; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if ((retVal = rtl8373_getAsicRegBit(RTL8373_RLDP_RLPP_CTRL_ADDR, RTL8373_RLDP_RLPP_CTRL_RLDP_EN_OFFSET, &pConfig->rldp_enable))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_getAsicRegBit(RTL8373_RLDP_RLPP_CTRL_ADDR, RTL8373_RLDP_RLPP_CTRL_RLDP_MODE_OFFSET, &pConfig->trigger_mode))!=RT_ERR_OK) + return retVal; + + magic = (rtk_uint32*)&pConfig->magic; + retVal = rtl8373_getAsicReg(RTL8373_MAGIC_NUM0_ADDR, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + *magic = regData; + magic++; + + retVal = rtl8373_getAsicReg(RTL8373_MAGIC_NUM1_ADDR, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + *magic = regData; + + if ((retVal = rtl8373_getAsicRegBit(RTL8373_RLDP_RLPP_CTRL_ADDR, RTL8373_RLDP_RLPP_CTRL_COMP_ID_OFFSET, &pConfig->compare_type))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_getAsicRegBits(RTL8373_RETRY_CTRL_ADDR, RTL8373_RETRY_CTRL_RETRY_CHK_MASK, &pConfig->num_check))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_getAsicRegBits(RTL8373_PERIOD_CTRL_ADDR, RTL8373_PERIOD_CTRL_PERIOD_CHK_MASK, &pConfig->interval_check))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_getAsicRegBits(RTL8373_RETRY_CTRL_ADDR, RTL8373_RETRY_CTRL_RETRY_LOOP_MASK, &pConfig->num_loop))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_getAsicRegBits(RTL8373_PERIOD_CTRL_ADDR, RTL8373_PERIOD_CTRL_PERIOD_LOOP_MASK, &pConfig->interval_loop))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_rldp_portConfig_set + * Description: + * Set per port RLDP module configuration + * Input: + * port - port number to be configured + * pPortConfig - per port configuration structure of RLDP + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT + * RT_ERR_NULL_POINTER + * Note: + * None + */ +rtk_api_ret_t dal_rtl8373_rldp_portConfig_set(rtk_port_t port, rtk_rldp_portConfig_t *pPortConfig) +{ + rtk_api_ret_t retVal; + rtk_uint32 portmask; + rtk_uint32 phy_port; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if (pPortConfig->tx_enable>= RTK_ENABLE_END) + return RT_ERR_INPUT; + + phy_port = rtk_switch_port_L2P_get(port); + + if ((retVal = rtl8373_getAsicRegBits(RTL8373_RLDP_TX_PMSK_ADDR, RTL8373_RLDP_TX_PMSK_PMSK_MASK, &portmask))!=RT_ERR_OK) + return retVal; + + if (pPortConfig->tx_enable) + { + portmask |=(1<tx_enable = ENABLED; + } + else + { + pPortConfig->tx_enable = DISABLED; + } + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_rldp_randomNum_get + * Description: + * Get RLDP random number + * Output: + * pRandom - the pointer to random number + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT + * RT_ERR_NULL_POINTER + * Note: + * None + */ +rtk_api_ret_t dal_rtl8373_rldp_randomNum_get(rtk_mac_t * pRandom) +{ + rtk_api_ret_t retVal; + rtk_uint32 * tmp; + rtk_uint32 regData; + + + tmp = (rtk_uint32*)pRandom; + retVal = rtl8373_getAsicReg(RTL8373_RAND_NUM0_ADDR, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + *tmp = regData; + tmp++; + + retVal = rtl8373_getAsicReg(RTL8373_RAND_NUM1_ADDR, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + *tmp = regData; + + return RT_ERR_OK; +} + + + + +/* Function Name: + * dal_rtl8373_rldp_portStatus_get + * Description: + * Get RLDP module status + * Input: + * port - port number to be get + * Output: + * pPortStatus - per port status structure of RLDP + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT + * RT_ERR_NULL_POINTER + * Note: + * None + */ +rtk_api_ret_t dal_rtl8373_rldp_portStatus_get(rtk_port_t port, rtk_rldp_portStatus_t *pPortStatus) +{ + rtk_api_ret_t retVal; + rtk_uint32 status; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if ((retVal = rtl8373_getAsicRegBit(RTL8373_LOOP_STATE_ADDR(port), RTL8373_LOOP_STATE_LOOP_PMSK_OFFSET(port), &status))!=RT_ERR_OK) + return retVal; + + if (status & 1) + { + pPortStatus->loop_status = RTK_RLDP_LOOPSTS_LOOPING; + } + else + { + pPortStatus->loop_status = RTK_RLDP_LOOPSTS_NONE; + } + + if ((retVal = rtl8373_getAsicRegBit(RTL8373_LOOPED_STATE_ADDR(port), RTL8373_LOOPED_STATE_LOOPED_PMSK_OFFSET(port), &status))!=RT_ERR_OK) + return retVal; + + if (status & 1) + { + pPortStatus->loop_enter = RTK_RLDP_LOOPSTS_LOOPING; + } + else + { + pPortStatus->loop_enter = RTK_RLDP_LOOPSTS_NONE; + } + + if ((retVal = rtl8373_getAsicRegBit(RTL8373_LEAVE_LOOP_STATE_ADDR(port), RTL8373_LEAVE_LOOP_STATE_LEAVE_LOOP_PMSK_OFFSET(port), &status))!=RT_ERR_OK) + return retVal; + + if (status & 1) + { + pPortStatus->loop_leave = RTK_RLDP_LOOPSTS_LOOPING; + } + else + { + pPortStatus->loop_leave = RTK_RLDP_LOOPSTS_NONE; + } + + return RT_ERR_OK; +} + + + + +/* Function Name: + * dal_rtl8373_rldp_portLoopPair_get + * Description: + * Get RLDP port loop pairs + * Input: + * port - port number to be get + * Output: + * pPortmask - per port related loop ports + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT + * RT_ERR_NULL_POINTER + * Note: + * None + */ +rtk_api_ret_t dal_rtl8373_rldp_portLoopPair_get(rtk_port_t port, rtk_portmask_t *pPortmask) +{ + rtk_api_ret_t retVal; + rtk_uint32 pmsk; + //rtk_uint32 phy_port; + rtk_uint32 loopedPair; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + //phy_port = rtk_switch_port_L2P_get(port); + + if ((retVal = rtl8373_getAsicRegBits(RTL8373_LOOPPAIR_ADDR(port), RTL8373_LOOPPAIR_LOOP_PAIR_MASK(port), &loopedPair))!=RT_ERR_OK) + return retVal; + + if(loopedPair == 0) + pmsk = 0; + else + pmsk = 1 << (loopedPair - 1); + if ((retVal = rtk_switch_portmask_P2L_get(pmsk, pPortmask)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_rldp_genRandom + * Description: + * set asic gen random number + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * Note: + * None + */ +rtk_api_ret_t dal_rtl8373_rldp_genRandom(void) +{ + rtk_api_ret_t retVal; + + + + if ((retVal = rtl8373_setAsicRegBit(RTL8373_RLDP_RLPP_CTRL_ADDR, RTL8373_RLDP_RLPP_CTRL_GEN_RANDOM_OFFSET, 1))!=RT_ERR_OK) + return retVal; + + + return RT_ERR_OK; +} + + + +/* Function Name: + * dal_rtl8373_rlpp_config_set + * Description: + * Set trap RLPP pkt to 8051 + * Input: + * enable - enable trap + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT + * RT_ERR_NULL_POINTER + * Note: + * None + */ +rtk_api_ret_t dal_rtl8373_rlpp_trap_set(rtk_uint32 enable) +{ + rtk_api_ret_t retVal; + + + if ((retVal = rtl8373_setAsicRegBit(RTL8373_RLDP_RLPP_CTRL_ADDR, RTL8373_RLDP_RLPP_CTRL_RLPP_TRAP_OFFSET, enable))!=RT_ERR_OK) + return retVal; + + + return RT_ERR_OK; +} + + + +/* Function Name: + * dal_rtl8373_rlpp_config_get + * Description: + * Get trap RLPP pkt to 8051 + * Input: + * pEnable - enable trap + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT + * RT_ERR_NULL_POINTER + * Note: + * None + */ +rtk_api_ret_t dal_rtl8373_rlpp_trap_get(rtk_uint32* pEnable) +{ + rtk_api_ret_t retVal; + + + if ((retVal = rtl8373_getAsicRegBit(RTL8373_RLDP_RLPP_CTRL_ADDR, RTL8373_RLDP_RLPP_CTRL_RLPP_TRAP_OFFSET, pEnable))!=RT_ERR_OK) + return retVal; + + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_rrcp_config_set + * Description: + * Set trap RRCP status + * Input: + * status - 0b00:fwd, 0b01:trap to 8051, 0b10: trap external cpu + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT + * RT_ERR_NULL_POINTER + * Note: + * None + */ +rtk_api_ret_t dal_rtl8373_rrcp_trap_set(rtk_uint32 status) +{ + rtk_api_ret_t retVal; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_RRCP_CTRL_ADDR, RTL8373_RRCP_CTRL_RRCP_TRAP_MASK, status))!=RT_ERR_OK) + return retVal; + + + return RT_ERR_OK; +} + + + +/* Function Name: + * dal_rtl8373_rrcp_config_get + * Description: + * Get trap RRCP status + * Input: + * pStatus - 0b00:fwd, 0b01:trap to 8051, 0b10: trap external cpu + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT + * RT_ERR_NULL_POINTER + * Note: + * None + */ +rtk_api_ret_t dal_rtl8373_rrcp_trap_get(rtk_uint32* pStatus) +{ + rtk_api_ret_t retVal; + + if ((retVal = rtl8373_getAsicRegBits(RTL8373_RRCP_CTRL_ADDR, RTL8373_RRCP_CTRL_RRCP_TRAP_MASK, pStatus))!=RT_ERR_OK) + return retVal; + + + return RT_ERR_OK; +} + + + + + + diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_rtkpp.h b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_rtkpp.h new file mode 100755 index 00000000..6bc869e1 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_rtkpp.h @@ -0,0 +1,225 @@ +#ifndef __DAL_RTL8373_RTKPP_H__ +#define __DAL_RTL8373_RTKPP_H__ + + +#include "rldp.h" + + + +/* Function Name: + * dal_rtl8373_rldp_config_set + * Description: + * Set RLDP module configuration + * Input: + * pConfig - configuration structure of RLDP + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT + * RT_ERR_NULL_POINTER + * Note: + * None + */ +extern rtk_api_ret_t dal_rtl8373_rldp_config_set(rtk_rldp_config_t *pConfig); + +/* Function Name: + * dal_rtl8373_rldp_config_get + * Description: + * Get RLDP module configuration + * Input: + * None + * Output: + * pConfig - configuration structure of RLDP + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT + * RT_ERR_NULL_POINTER + * Note: + * None + */ +extern rtk_api_ret_t dal_rtl8373_rldp_config_get(rtk_rldp_config_t *pConfig); + + + +/* Function Name: + * dal_rtl8373_rldp_portConfig_set + * Description: + * Set per port RLDP module configuration + * Input: + * port - port number to be configured + * pPortConfig - per port configuration structure of RLDP + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT + * RT_ERR_NULL_POINTER + * Note: + * None + */ +extern rtk_api_ret_t dal_rtl8373_rldp_portConfig_set(rtk_port_t port, rtk_rldp_portConfig_t *pPortConfig); + +/* Function Name: + * dal_rtl8373_rldp_portConfig_get + * Description: + * Get per port RLDP module configuration + * Input: + * port - port number to be get + * Output: + * pPortConfig - per port configuration structure of RLDP + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT + * RT_ERR_NULL_POINTER + * Note: + * None + */ +extern rtk_api_ret_t dal_rtl8373_rldp_portConfig_get(rtk_port_t port, rtk_rldp_portConfig_t *pPortConfig); + +/* Function Name: + * dal_rtl8373_rldp_portStatus_get + * Description: + * Get RLDP module status + * Input: + * port - port number to be get + * Output: + * pPortStatus - per port status structure of RLDP + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT + * RT_ERR_NULL_POINTER + * Note: + * None + */ +extern rtk_api_ret_t dal_rtl8373_rldp_portStatus_get(rtk_port_t port, rtk_rldp_portStatus_t *pPortStatus); + + +/* Function Name: + * dal_rtl8373_rldp_portLoopPair_get + * Description: + * Get RLDP port loop pairs + * Input: + * port - port number to be get + * Output: + * pPortmask - per port related loop ports + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT + * RT_ERR_NULL_POINTER + * Note: + * None + */ +extern rtk_api_ret_t dal_rtl8373_rldp_portLoopPair_get(rtk_port_t port, rtk_portmask_t *pPortmask); + +/* Function Name: + * dal_rtl8373_rldp_genRandom + * Description: + * set asic gen random number + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * Note: + * None + */ +extern rtk_api_ret_t dal_rtl8373_rldp_genRandom(void); + + +/* Function Name: + * dal_rtl8373_rlpp_config_set + * Description: + * Set trap RLPP pkt to 8051 + * Input: + * enable - enable trap + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT + * RT_ERR_NULL_POINTER + * Note: + * None + */ +extern rtk_api_ret_t dal_rtl8373_rlpp_trap_set(rtk_uint32 enable); + +/* Function Name: + * dal_rtl8373_rlpp_config_get + * Description: + * Get trap RLPP pkt to 8051 + * Input: + * pEnable - enable trap + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT + * RT_ERR_NULL_POINTER + * Note: + * None + */ +extern rtk_api_ret_t dal_rtl8373_rlpp_trap_get(rtk_uint32* pEnable); + +/* Function Name: + * dal_rtl8373_rrcp_config_set + * Description: + * Set trap RRCP status + * Input: + * status - 0b00:fwd, 0b01:trap to 8051, 0b10: trap external cpu + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT + * RT_ERR_NULL_POINTER + * Note: + * None + */ +extern rtk_api_ret_t dal_rtl8373_rrcp_trap_set(rtk_uint32 status); + + +/* Function Name: + * dal_rtl8373_rrcp_config_get + * Description: + * Get trap RRCP status + * Input: + * pStatus - 0b00:fwd, 0b01:trap to 8051, 0b10: trap external cpu + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT + * RT_ERR_NULL_POINTER + * Note: + * None + */ +extern rtk_api_ret_t dal_rtl8373_rrcp_trap_get(rtk_uint32* pStatus); + + +/* Function Name: + * dal_rtl8373_rldp_randomNum_get + * Description: + * Get RLDP random number + * Output: + * pRandom - the pointer to random number + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT + * RT_ERR_NULL_POINTER + * Note: + * None + */ +extern rtk_api_ret_t dal_rtl8373_rldp_randomNum_get(rtk_mac_t * pRandom); + + +#endif \ No newline at end of file diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_sharemeter.c b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_sharemeter.c new file mode 100755 index 00000000..5b56f7f7 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_sharemeter.c @@ -0,0 +1,785 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8373 + * Feature : Here is a list of all functions and variables in ShareMeter module. + * + */ + +#include +#include +#include +#include +#include + +#include +#if 0 +#define RTL8373_SCHEDULE_PORT_APR_METER_REG(port, queue) (RTL8373_REG_SCHEDULE_PORT0_APR_METER_CTRL0 + (port << 2) + (queue / 5)) +#define RTL8373_SCHEDULE_PORT_APR_METER_MASK(queue) (RTL8373_SCHEDULE_PORT0_APR_METER_CTRL0_QUEUE0_APR_METER_MASK << (3 * (queue % 5))) + +#define RTL8373_MAX_NUM_OF_QUEUE (8) +#endif + +/* Function Name: + * dal_rtl8373_rate_shareMeter_set + * Description: + * Set meter configuration + * Input: + * index - shared meter index(0 - 63) + * type - shared meter type + * rate - rate of share meter + * ifg_include - include IFG or not, ENABLE:include DISABLE:exclude + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_METER_ID - Invalid meter + * RT_ERR_RATE - Invalid rate + * RT_ERR_INPUT - Invalid input parameters + * Note: + * The API can set shared meter rate and ifg include for each meter. + * The rate unit is 1 kbps and the range is from 0 to 0x989680 if type is METER_TYPE_KBPS and + * the granularity of rate is 1 kbps. + * The rate unit is packets per second and the range is 0 ~ 0xE310B8 if type is METER_TYPE_PPS. + * The ifg_include parameter is used + * for rate calculation with/without inter-frame-gap and preamble. + */ +rtk_api_ret_t dal_rtl8373_rate_shareMeter_set(rtk_meter_id_t index, rtk_meter_type_t type, rtk_rate_t rate, rtk_enable_t ifg_include) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (index > RTL8373_METERMAX) + return RT_ERR_FILTER_METER_ID; + + if (type >= METER_TYPE_END) + return RT_ERR_INPUT; + + if (ifg_include >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + switch (type) + { + case METER_TYPE_KBPS: + if (rate > RTL8373_QOS_RATE_INPUT_MAX_HSG) + return RT_ERR_RATE ; + + if((retVal = rtl8373_setAsicReg(RTL8373_SHARED_METER_RATE_CTRL_ADDR(index), rate)) != RT_ERR_OK) + return retVal; + + break; + case METER_TYPE_PPS: + if (rate > RTL8373_QOS_PPS_INPUT_MAX) + return RT_ERR_RATE ; + + if((retVal = rtl8373_setAsicReg(RTL8373_SHARED_METER_RATE_CTRL_ADDR(index), rate)) != RT_ERR_OK) + return retVal; + + break; + default: + return RT_ERR_INPUT; + } + + /*Set IFG */ + if((retVal = rtl8373_setAsicRegBit(RTL8373_SHARED_METER_IPG_CTRL_ADDR(index), RTL8373_SHARED_METER_IPG_CTRL_IPG_CNTR_OFFSET(index), ifg_include)) != RT_ERR_OK) + return retVal; + + /* Set Type */ + if ((retVal = rtl8373_setAsicRegBit(RTL8373_SHARED_METER_MODE_ADDR(index), RTL8373_SHARED_METER_MODE_LB_MODE_OFFSET(index), (rtk_uint32)type)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_rate_shareMeter_get + * Description: + * Get meter configuration + * Input: + * index - shared meter index(0 - 63) + * Output: + * pType - Meter Type + * pRate - pointer of rate of share meter + * pIfg_include - include IFG or not, ENABLE:include DISABLE:exclude + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_METER_ID - Invalid meter + * Note: + * + */ +rtk_api_ret_t dal_rtl8373_rate_shareMeter_get(rtk_meter_id_t index, rtk_meter_type_t *pType, rtk_rate_t *pRate, rtk_enable_t *pIfg_include) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (index > RTL8373_METERMAX) + return RT_ERR_FILTER_METER_ID; + + if(NULL == pType) + return RT_ERR_NULL_POINTER; + + if(NULL == pRate) + return RT_ERR_NULL_POINTER; + + if(NULL == pIfg_include) + return RT_ERR_NULL_POINTER; + + /* 19-bits Rate */ + if((retVal = rtl8373_getAsicReg(RTL8373_SHARED_METER_RATE_CTRL_ADDR(index), pRate)) != RT_ERR_OK) + return retVal; + + /* IFG */ + if((retVal = rtl8373_getAsicRegBit(RTL8373_SHARED_METER_IPG_CTRL_ADDR(index), RTL8373_SHARED_METER_IPG_CTRL_IPG_CNTR_OFFSET(index), pIfg_include)) != RT_ERR_OK) + return retVal; + + *pIfg_include = (regData == 1) ? ENABLED : DISABLED; + + /* Type */ + if ((retVal = rtl8373_getAsicRegBit(RTL8373_SHARED_METER_MODE_ADDR(index), RTL8373_SHARED_METER_MODE_LB_MODE_OFFSET(index), ®Data)) != RT_ERR_OK) + return retVal; + + *pType = (regData == 0) ? METER_TYPE_KBPS : METER_TYPE_PPS; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_rate_shareMeterBucket_set + * Description: + * Set meter Bucket Size + * Input: + * index - shared meter index(0 - 63) + * bucket_size - Bucket Size + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_INPUT - Error Input + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_METER_ID - Invalid meter + * Note: + * The API can set shared meter bucket size. + */ +rtk_api_ret_t dal_rtl8373_rate_shareMeterBucket_set(rtk_meter_id_t index, rtk_uint32 bucket_size) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (index > RTL8373_METERMAX) + return RT_ERR_FILTER_METER_ID; + + if(bucket_size > RTL8373_METERBUCKETSIZEMAX) + return RT_ERR_INPUT; + + if ((retVal = rtl8373_setAsicReg(RTL8373_SHARED_METER_BURST_CTRL_ADDR(index), bucket_size)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_rate_shareMeterBucket_get + * Description: + * Get meter Bucket Size + * Input: + * index - shared meter index(0 - 63) + * Output: + * pBucket_size - Bucket Size + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_METER_ID - Invalid meter + * Note: + * The API can get shared meter bucket size. + */ +rtk_api_ret_t dal_rtl8373_rate_shareMeterBucket_get(rtk_meter_id_t index, rtk_uint32 *pBucket_size) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (index > RTL8373_METERMAX) + return RT_ERR_FILTER_METER_ID; + + if(NULL == pBucket_size) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8373_getAsicReg(RTL8373_SHARED_METER_BURST_CTRL_ADDR(index), pBucket_size)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_rate_shareMeterExceedStatus_set + * Description: + * Clear shared meter status + * Input: + * index - share meter index (0 - 63) + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_METER_ID - Invalid meter + * Note: + * None + */ +ret_t dal_rtl8373_rate_shareMeterExceedStatus_set(rtk_uint32 index) +{ + if(index > RTL8373_METERMAX) + return RT_ERR_FILTER_METER_ID; + + return rtl8373_setAsicRegBit(RTL8373_SHARED_METER_EXCEED_ADDR(index), RTL8373_SHARED_METER_EXCEED_LB_EXCEED_OFFSET(index), 1); + +} + +/* Function Name: + * dal_rtl8373_rate_shareMeterExceedStatus_get + * Description: + * Get shared meter status + * Input: + * index - share meter index (0-63) + * pStatus - 0: rate doesn't exceed 1: rate exceeds + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_METER_ID - Invalid meter + * Note: + * If rate is over rate*16Kbps of a meter, the state bit of this meter is set to 1. + */ +ret_t dal_rtl8373_rate_shareMeterExceedStatus_get(rtk_uint32 index, rtk_uint32* pStatus) +{ + if(index > RTL8373_METERMAX) + return RT_ERR_FILTER_METER_ID; + + return rtl8373_getAsicRegBit(RTL8373_SHARED_METER_EXCEED_ADDR(index), RTL8373_SHARED_METER_EXCEED_LB_EXCEED_OFFSET(index), pStatus); +} + +/* Function Name: + * dal_rtl8373_rate_shareMeterICPUExceedStatus_set + * Description: + * Clear shared meter ICPU status + * Input: + * index - meter index (0 - 63) + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_METER_ID - Invalid meter + * Note: + * None + */ +ret_t dal_rtl8373_rate_shareMeterICPUExceedStatus_set(rtk_uint32 index) +{ + if(index > RTL8373_METERMAX) + return RT_ERR_FILTER_METER_ID; + + return rtl8373_setAsicRegBit(RTL8373_SHARED_METER_EXCEED_ICPU_ADDR(index), RTL8373_SHARED_METER_EXCEED_ICPU_LB_EXCEED_ICPU_OFFSET(index), 1); + +} + +/* Function Name: + * dal_rtl8373_rate_shareMeterICPUExceedStatus_get + * Description: + * Get shared meter ICPU exceed status + * Input: + * index - meter index (0 - 63) + * pStatus - 0: rate doesn't exceed 1: rate exceeds + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_METER_ID - Invalid meter + * Note: + * If rate is over rate*16Kbps of a meter, the state bit of this meter is set to 1. + */ +ret_t dal_rtl8373_rate_shareMeterICPUExceedStatus_get(rtk_uint32 index, rtk_uint32* pStatus) +{ + if(index > RTL8373_METERMAX) + return RT_ERR_FILTER_METER_ID; + + return rtl8373_getAsicRegBit(RTL8373_SHARED_METER_EXCEED_ICPU_ADDR(index), RTL8373_SHARED_METER_EXCEED_ICPU_LB_EXCEED_ICPU_OFFSET(index), pStatus); +} + +#if 0 +/* Function Name: + * dal_rtl8373_rate_igrBandwidthCtrlRate_set + * Description: + * Set port ingress bandwidth control + * Input: + * port - Port id + * rate - Rate of share meter + * ifg_include - include IFG or not, ENABLE:include DISABLE:exclude + * fc_enable - enable flow control or not, ENABLE:use flow control DISABLE:drop + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid IFG parameter. + * RT_ERR_INBW_RATE - Invalid ingress rate parameter. + * Note: + * The rate unit is 1 kbps and the range is from 8k to 1048568k. The granularity of rate is 8 kbps. + * The ifg_include parameter is used for rate calculation with/without inter-frame-gap and preamble. + */ +rtk_api_ret_t dal_rtl8373_rate_igrBandwidthCtrlRate_set(rtk_port_t port, rtk_rate_t rate, rtk_enable_t ifg_include, rtk_enable_t fc_enable) +{ + rtk_api_ret_t retVal; + rtk_uint32 regAddr, regData; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if(ifg_include >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if(fc_enable >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if(rtk_switch_isHsgPort(port) == RT_ERR_OK) + { + if (rate > rtl8373_QOS_RATE_INPUT_MAX_HSG) + return RT_ERR_QOS_EBW_RATE ; + } + else + { + if (rate > rtl8373_QOS_RATE_INPUT_MAX) + return RT_ERR_QOS_EBW_RATE ; + } + + regAddr = rtl8373_REG_INGRESSBW_PORT0_RATE_CTRL0 + (rtk_switch_port_L2P_get(port) * 0x20); + regData = (rate >> 3) & 0xFFFF; + if((retVal = rtl8373_setAsicReg(regAddr, regData)) != RT_ERR_OK) + return retVal; + + regAddr += 1; + regData = ((rate >> 3) & 0x70000) >> 16; + if((retVal = rtl8373_setAsicRegBits(regAddr, rtl8373_INGRESSBW_PORT0_RATE_CTRL1_INGRESSBW_RATE16_MASK, regData)) != RT_ERR_OK) + return retVal; + + regAddr = rtl8373_REG_PORT0_MISC_CFG + (rtk_switch_port_L2P_get(port) * 0x20); + if((retVal = rtl8373_setAsicRegBit(regAddr, rtl8373_PORT0_MISC_CFG_INGRESSBW_IFG_OFFSET, (ifg_include == ENABLED) ? 1 : 0)) != RT_ERR_OK) + return retVal; + + regAddr = rtl8373_REG_PORT0_MISC_CFG + (rtk_switch_port_L2P_get(port) * 0x20); + if((retVal = rtl8373_setAsicRegBit(regAddr, rtl8373_PORT0_MISC_CFG_INGRESSBW_FLOWCTRL_OFFSET, (fc_enable == ENABLED) ? 1 : 0)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_rate_igrBandwidthCtrlRate_get + * Description: + * Get port ingress bandwidth control + * Input: + * port - Port id + * Output: + * pRate - Rate of share meter + * pIfg_include - Rate's calculation including IFG, ENABLE:include DISABLE:exclude + * pFc_enable - enable flow control or not, ENABLE:use flow control DISABLE:drop + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The rate unit is 1 kbps and the range is from 8k to 1048568k. The granularity of rate is 8 kbps. + * The ifg_include parameter is used for rate calculation with/without inter-frame-gap and preamble. + */ +rtk_api_ret_t dal_rtl8373_rate_igrBandwidthCtrlRate_get(rtk_port_t port, rtk_rate_t *pRate, rtk_enable_t *pIfg_include, rtk_enable_t *pFc_enable) +{ + rtk_api_ret_t retVal; + rtk_uint32 regAddr, regData; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if(NULL == pIfg_include) + return RT_ERR_NULL_POINTER; + + if(NULL == pFc_enable) + return RT_ERR_NULL_POINTER; + + regAddr = rtl8373_REG_INGRESSBW_PORT0_RATE_CTRL0 + (rtk_switch_port_L2P_get(port) * 0x20); + if((retVal = rtl8373_getAsicReg(regAddr, ®Data)) != RT_ERR_OK) + return retVal; + + *pRate = regData; + + regAddr += 1; + if((retVal = rtl8373_getAsicRegBits(regAddr, rtl8373_INGRESSBW_PORT0_RATE_CTRL1_INGRESSBW_RATE16_MASK, ®Data)) != RT_ERR_OK) + return retVal; + + *pRate |= (regData << 16); + *pRate = (*pRate << 3); + + regAddr = rtl8373_REG_PORT0_MISC_CFG + (rtk_switch_port_L2P_get(port) * 0x20); + if((retVal = rtl8373_getAsicRegBit(regAddr, rtl8373_PORT0_MISC_CFG_INGRESSBW_IFG_OFFSET, ®Data)) != RT_ERR_OK) + return retVal; + + *pIfg_include = (regData == 1) ? ENABLED : DISABLED; + + regAddr = rtl8373_REG_PORT0_MISC_CFG + (rtk_switch_port_L2P_get(port) * 0x20); + if((retVal = rtl8373_getAsicRegBit(regAddr, rtl8373_PORT0_MISC_CFG_INGRESSBW_FLOWCTRL_OFFSET, ®Data)) != RT_ERR_OK) + return retVal; + + *pFc_enable = (regData == 1) ? ENABLED : DISABLED; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_rate_egrBandwidthCtrlRate_set + * Description: + * Set port egress bandwidth control + * Input: + * port - Port id + * rate - Rate of egress bandwidth + * ifg_include - include IFG or not, ENABLE:include DISABLE:exclude + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_QOS_EBW_RATE - Invalid egress bandwidth/rate + * Note: + * The rate unit is 1 kbps and the range is from 8k to 1048568k. The granularity of rate is 8 kbps. + * The ifg_include parameter is used for rate calculation with/without inter-frame-gap and preamble. + */ +rtk_api_ret_t dal_rtl8373_rate_egrBandwidthCtrlRate_set( rtk_port_t port, rtk_rate_t rate, rtk_enable_t ifg_include) +{ + rtk_api_ret_t retVal; + rtk_uint32 regAddr, regData; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if(rtk_switch_isHsgPort(port) == RT_ERR_OK) + { + if (rate > rtl8373_QOS_RATE_INPUT_MAX_HSG) + return RT_ERR_QOS_EBW_RATE ; + } + else + { + if (rate > rtl8373_QOS_RATE_INPUT_MAX) + return RT_ERR_QOS_EBW_RATE ; + } + + if (ifg_include >= RTK_ENABLE_END) + return RT_ERR_ENABLE; + + regAddr = rtl8373_REG_PORT0_EGRESSBW_CTRL0 + (rtk_switch_port_L2P_get(port) * 2); + regData = (rate >> 3) & 0xFFFF; + + if((retVal = rtl8373_setAsicReg(regAddr, regData)) != RT_ERR_OK) + return retVal; + + if(rtk_switch_isHsgPort(port) == RT_ERR_OK) + { + regAddr = rtl8373_REG_PORT0_EGRESSBW_CTRL1 + (rtk_switch_port_L2P_get(port) * 2); + regData = ((rate >> 3) & 0x70000) >> 16; + + if((retVal = rtl8373_setAsicRegBits(regAddr, rtl8373_PORT6_EGRESSBW_CTRL1_MASK, regData)) != RT_ERR_OK) + return retVal; + } + else + { + regAddr = rtl8373_REG_PORT0_EGRESSBW_CTRL1 + (rtk_switch_port_L2P_get(port) * 2); + regData = ((rate >> 3) & 0x10000) >> 16; + + if((retVal = rtl8373_setAsicRegBits(regAddr, rtl8373_PORT0_EGRESSBW_CTRL1_MASK, regData)) != RT_ERR_OK) + return retVal; + } + + if((retVal = rtl8373_setAsicRegBit(rtl8373_REG_SCHEDULE_WFQ_CTRL, rtl8373_SCHEDULE_WFQ_CTRL_OFFSET, (ifg_include == ENABLED) ? 1 : 0)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_rate_egrBandwidthCtrlRate_get + * Description: + * Get port egress bandwidth control + * Input: + * port - Port id + * Output: + * pRate - Rate of egress bandwidth + * pIfg_include - Rate's calculation including IFG, ENABLE:include DISABLE:exclude + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The rate unit is 1 kbps and the range is from 8k to 1048568k. The granularity of rate is 8 kbps. + * The ifg_include parameter is used for rate calculation with/without inter-frame-gap and preamble. + */ +rtk_api_ret_t dal_rtl8373_rate_egrBandwidthCtrlRate_get(rtk_port_t port, rtk_rate_t *pRate, rtk_enable_t *pIfg_include) +{ + rtk_api_ret_t retVal; + rtk_uint32 regAddr, regData, regData2; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if(NULL == pRate) + return RT_ERR_NULL_POINTER; + + if(NULL == pIfg_include) + return RT_ERR_NULL_POINTER; + + regAddr = rtl8373_REG_PORT0_EGRESSBW_CTRL0 + (rtk_switch_port_L2P_get(port) * 2); + if((retVal = rtl8373_getAsicReg(regAddr, ®Data)) != RT_ERR_OK) + return retVal; + + regAddr = rtl8373_REG_PORT0_EGRESSBW_CTRL1 + (rtk_switch_port_L2P_get(port) * 2); + retVal = rtl8373_getAsicRegBits(regAddr, rtl8373_PORT6_EGRESSBW_CTRL1_MASK, ®Data2); + if(retVal != RT_ERR_OK) + return retVal; + + *pRate = ((regData | (regData2 << 16)) << 3); + + if((retVal = rtl8373_getAsicRegBit(rtl8373_REG_SCHEDULE_WFQ_CTRL, rtl8373_SCHEDULE_WFQ_CTRL_OFFSET, ®Data)) != RT_ERR_OK) + return retVal; + + *pIfg_include = (regData == 1) ? ENABLED : DISABLED; + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_rate_egrQueueBwCtrlEnable_get + * Description: + * Get enable status of egress bandwidth control on specified queue. + * Input: + * unit - unit id + * port - port id + * queue - queue id + * Output: + * pEnable - Pointer to enable status of egress queue bandwidth control + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_QUEUE_ID - invalid queue id + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None + */ +rtk_api_ret_t dal_rtl8373_rate_egrQueueBwCtrlEnable_get(rtk_port_t port, rtk_qid_t queue, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + rtk_uint32 aprEnable; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + /*for whole port function, the queue value should be 0xFF*/ + if (queue != RTK_WHOLE_SYSTEM) + return RT_ERR_QUEUE_ID; + + if(NULL == pEnable) + return RT_ERR_NULL_POINTER; + + if((retVal = rtl8373_getAsicRegBit(rtl8373_REG_SCHEDULE_APR_CTRL0, rtk_switch_port_L2P_get(port), &aprEnable)) != RT_ERR_OK) + return retVal; + + *pEnable = (aprEnable == 1) ? ENABLED : DISABLED; + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_rate_egrQueueBwCtrlEnable_set + * Description: + * Set enable status of egress bandwidth control on specified queue. + * Input: + * port - port id + * queue - queue id + * enable - enable status of egress queue bandwidth control + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_QUEUE_ID - invalid queue id + * RT_ERR_INPUT - invalid input parameter + * Note: + * None + */ +rtk_api_ret_t dal_rtl8373_rate_egrQueueBwCtrlEnable_set(rtk_port_t port, rtk_qid_t queue, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + /*for whole port function, the queue value should be 0xFF*/ + if (queue != RTK_WHOLE_SYSTEM) + return RT_ERR_QUEUE_ID; + + if (enable>=RTK_ENABLE_END) + return RT_ERR_INPUT; + + if((retVal = rtl8373_setAsicRegBit(rtl8373_REG_SCHEDULE_APR_CTRL0, rtk_switch_port_L2P_get(port), (enable == ENABLED) ? 1 : 0)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_rate_egrQueueBwCtrlRate_get + * Description: + * Get rate of egress bandwidth control on specified queue. + * Input: + * port - port id + * queue - queue id + * pIndex - shared meter index + * Output: + * pRate - pointer to rate of egress queue bandwidth control + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_QUEUE_ID - invalid queue id + * RT_ERR_FILTER_METER_ID - Invalid meter id + * Note: + * The actual rate control is set in shared meters. + * The unit of granularity is 8Kbps. + */ +rtk_api_ret_t dal_rtl8373_rate_egrQueueBwCtrlRate_get(rtk_port_t port, rtk_qid_t queue, rtk_meter_id_t *pIndex) +{ + rtk_api_ret_t retVal; + rtk_uint32 apridx; + rtk_uint32 phy_port; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if (queue >= rtl8373_MAX_NUM_OF_QUEUE) + return RT_ERR_QUEUE_ID; + + if(NULL == pIndex) + return RT_ERR_NULL_POINTER; + + phy_port = rtk_switch_port_L2P_get(port); + if((retVal = rtl8373_getAsicRegBits(rtl8373_SCHEDULE_PORT_APR_METER_REG(phy_port, queue), rtl8373_SCHEDULE_PORT_APR_METER_MASK(phy_port), &apridx)) != RT_ERR_OK) + return retVal; + + *pIndex = apridx + ((rtk_switch_port_L2P_get(port) % 4) * 8); + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_rate_egrQueueBwCtrlRate_set + * Description: + * Set rate of egress bandwidth control on specified queue. + * Input: + * port - port id + * queue - queue id + * index - shared meter index + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_QUEUE_ID - invalid queue id + * RT_ERR_FILTER_METER_ID - Invalid meter id + * Note: + * The actual rate control is set in shared meters. + * The unit of granularity is 8Kbps. + */ +rtk_api_ret_t dal_rtl8373_rate_egrQueueBwCtrlRate_set(rtk_port_t port, rtk_qid_t queue, rtk_meter_id_t index) +{ + rtk_api_ret_t retVal; + rtk_uint32 offset_idx; + rtk_uint32 phy_port; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if (queue >= rtl8373_MAX_NUM_OF_QUEUE) + return RT_ERR_QUEUE_ID; + + if (index > RTK_MAX_METER_ID) + return RT_ERR_FILTER_METER_ID; + + phy_port = rtk_switch_port_L2P_get(port); + if (index < ((phy_port % 4) * 8) || index > (7 + ((phy_port % 4) * 8))) + return RT_ERR_FILTER_METER_ID; + + offset_idx = index - ((phy_port % 4) * 8); + + if ((retVal = rtl8373_setAsicRegBits(rtl8373_SCHEDULE_PORT_APR_METER_REG(phy_port, queue), rtl8373_SCHEDULE_PORT_APR_METER_MASK(queue), offset_idx))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +#endif + + + diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_sharemeter.h b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_sharemeter.h new file mode 100755 index 00000000..2a009553 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_sharemeter.h @@ -0,0 +1,369 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8367/RTL8367D switch high-level API + * + * Feature : The file includes rate module high-layer API defination + * + */ + +#ifndef __DAL_RTL8373_SHAREDMETER_H__ +#define __DAL_RTL8373_SHAREDMETER_H__ + +/* + * Include Files + */ +#include + +/* + * Data Type Declaration + */ +//#define RTL8373_METERBUCKETSIZEMAX 0xFFFFFFF + +/* Function Name: + * dal_rtl8373_rate_shareMeter_set + * Description: + * Set meter configuration + * Input: + * index - shared meter index(0 - 63) + * type - shared meter type + * rate - rate of share meter + * ifg_include - include IFG or not, ENABLE:include DISABLE:exclude + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_METER_ID - Invalid meter + * RT_ERR_RATE - Invalid rate + * RT_ERR_INPUT - Invalid input parameters + * Note: + * The API can set shared meter rate and ifg include for each meter. + * The rate unit is 16 kbps and the range is from 0 to 0x98968 if type is METER_TYPE_KBPS and + * the granularity of rate is 16 kbps. + * The rate unit is packets per second and the range is 0 ~ 0xFFFFF if type is METER_TYPE_PPS. + * The ifg_include parameter is used + * for rate calculation with/without inter-frame-gap and preamble. + */ +extern rtk_api_ret_t dal_rtl8373_rate_shareMeter_set(rtk_meter_id_t index, rtk_meter_type_t type, rtk_rate_t rate, rtk_enable_t ifg_include); + +/* Function Name: + * dal_rtl8373_rate_shareMeter_get + * Description: + * Get meter configuration + * Input: + * index - shared meter index(0 - 63) + * Output: + * pType - Meter Type + * pRate - pointer of rate of share meter + * pIfg_include - include IFG or not, ENABLE:include DISABLE:exclude + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_METER_ID - Invalid meter + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8373_rate_shareMeter_get(rtk_meter_id_t index, rtk_meter_type_t *pType, rtk_rate_t *pRate, rtk_enable_t *pIfg_include); + +/* Function Name: + * dal_rtl8373_rate_shareMeterBucket_set + * Description: + * Set meter Bucket Size + * Input: + * index - shared meter index(0 - 63) + * bucket_size - Bucket Size + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_INPUT - Error Input + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_METER_ID - Invalid meter + * Note: + * The API can set shared meter bucket size. + */ +extern rtk_api_ret_t dal_rtl8373_rate_shareMeterBucket_set(rtk_meter_id_t index, rtk_uint32 bucket_size); + +/* Function Name: + * dal_rtl8373_rate_shareMeterBucket_get + * Description: + * Get meter Bucket Size + * Input: + * index - shared meter index(0 - 63) + * Output: + * pBucket_size - Bucket Size + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_METER_ID - Invalid meter + * Note: + * The API can get shared meter bucket size. + */ +extern rtk_api_ret_t dal_rtl8373_rate_shareMeterBucket_get(rtk_meter_id_t index, rtk_uint32 *pBucket_size); + +/* Function Name: + * dal_rtl8373_rate_shareMeterExceedStatus_set + * Description: + * Clear shared meter status + * Input: + * index - share meter index (0 - 63) + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_METER_ID - Invalid meter + * Note: + * None + */ +extern ret_t dal_rtl8373_rate_shareMeterExceedStatus_set(rtk_uint32 index); + +/* Function Name: + * dal_rtl8373_rate_shareMeterExceedStatus_get + * Description: + * Get shared meter status + * Input: + * index - share meter index (0-63) + * pStatus - 0: rate doesn't exceed 1: rate exceeds + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_METER_ID - Invalid meter + * Note: + * If rate is over rate*16Kbps of a meter, the state bit of this meter is set to 1. + */ +extern ret_t dal_rtl8373_rate_shareMeterExceedStatus_get(rtk_uint32 index, rtk_uint32* pStatus); + +/* Function Name: + * dal_rtl8373_rate_shareMeterICPUExceedStatus_set + * Description: + * Clear shared meter ICPU status + * Input: + * index - share meter index (0 - 63) + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_METER_ID - Invalid meter + * Note: + * None + */ +extern ret_t dal_rtl8373_rate_shareMeterICPUExceedStatus_set(rtk_uint32 index); + +/* Function Name: + * dal_rtl8373_rate_shareMeterICPUExceedStatus_get + * Description: + * Get shared meter ICPU exceed status + * Input: + * index - share meter index (0 - 63) + * pStatus - 0: rate doesn't exceed 1: rate exceeds + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_METER_ID - Invalid meter + * Note: + * If rate is over rate*16Kbps of a meter, the state bit of this meter is set to 1. + */ +extern ret_t dal_rtl8373_rate_shareMeterICPUExceedStatus_get(rtk_uint32 index, rtk_uint32* pStatus); + +#if 0 +/* Function Name: + * dal_rtl8367d_rate_igrBandwidthCtrlRate_set + * Description: + * Set port ingress bandwidth control + * Input: + * port - Port id + * rate - Rate of share meter + * ifg_include - include IFG or not, ENABLE:include DISABLE:exclude + * fc_enable - enable flow control or not, ENABLE:use flow control DISABLE:drop + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid IFG parameter. + * RT_ERR_INBW_RATE - Invalid ingress rate parameter. + * Note: + * The rate unit is 1 kbps and the range is from 8k to 1048568k. The granularity of rate is 8 kbps. + * The ifg_include parameter is used for rate calculation with/without inter-frame-gap and preamble. + */ +extern rtk_api_ret_t dal_rtl8367d_rate_igrBandwidthCtrlRate_set( rtk_port_t port, rtk_rate_t rate, rtk_enable_t ifg_include, rtk_enable_t fc_enable); + +/* Function Name: + * dal_rtl8367d_rate_igrBandwidthCtrlRate_get + * Description: + * Get port ingress bandwidth control + * Input: + * port - Port id + * Output: + * pRate - Rate of share meter + * pIfg_include - Rate's calculation including IFG, ENABLE:include DISABLE:exclude + * pFc_enable - enable flow control or not, ENABLE:use flow control DISABLE:drop + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The rate unit is 1 kbps and the range is from 8k to 1048568k. The granularity of rate is 8 kbps. + * The ifg_include parameter is used for rate calculation with/without inter-frame-gap and preamble. + */ +extern rtk_api_ret_t dal_rtl8367d_rate_igrBandwidthCtrlRate_get(rtk_port_t port, rtk_rate_t *pRate, rtk_enable_t *pIfg_include, rtk_enable_t *pFc_enable); + +/* Function Name: + * dal_rtl8367d_rate_egrBandwidthCtrlRate_set + * Description: + * Set port egress bandwidth control + * Input: + * port - Port id + * rate - Rate of egress bandwidth + * ifg_include - include IFG or not, ENABLE:include DISABLE:exclude + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_QOS_EBW_RATE - Invalid egress bandwidth/rate + * Note: + * The rate unit is 1 kbps and the range is from 8k to 1048568k. The granularity of rate is 8 kbps. + * The ifg_include parameter is used for rate calculation with/without inter-frame-gap and preamble. + */ +extern rtk_api_ret_t dal_rtl8367d_rate_egrBandwidthCtrlRate_set(rtk_port_t port, rtk_rate_t rate, rtk_enable_t ifg_includ); + +/* Function Name: + * dal_rtl8367d_rate_egrBandwidthCtrlRate_get + * Description: + * Get port egress bandwidth control + * Input: + * port - Port id + * Output: + * pRate - Rate of egress bandwidth + * pIfg_include - Rate's calculation including IFG, ENABLE:include DISABLE:exclude + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The rate unit is 1 kbps and the range is from 8k to 1048568k. The granularity of rate is 8 kbps. + * The ifg_include parameter is used for rate calculation with/without inter-frame-gap and preamble. + */ +extern rtk_api_ret_t dal_rtl8367d_rate_egrBandwidthCtrlRate_get(rtk_port_t port, rtk_rate_t *pRate, rtk_enable_t *pIfg_include); + +/* Function Name: + * dal_rtl8367d_rate_egrQueueBwCtrlEnable_set + * Description: + * Set enable status of egress bandwidth control on specified queue. + * Input: + * port - port id + * queue - queue id + * enable - enable status of egress queue bandwidth control + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_QUEUE_ID - invalid queue id + * RT_ERR_INPUT - invalid input parameter + * Note: + * None + */ +extern rtk_api_ret_t dal_rtl8367d_rate_egrQueueBwCtrlEnable_set(rtk_port_t port, rtk_qid_t queue, rtk_enable_t enable); + +/* Function Name: + * dal_rtl8367d_rate_egrQueueBwCtrlRate_get + * Description: + * Get rate of egress bandwidth control on specified queue. + * Input: + * port - port id + * queue - queue id + * pIndex - shared meter index + * Output: + * pRate - pointer to rate of egress queue bandwidth control + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_QUEUE_ID - invalid queue id + * RT_ERR_FILTER_METER_ID - Invalid meter id + * Note: + * None. + */ +extern rtk_api_ret_t dal_rtl8367d_rate_egrQueueBwCtrlEnable_get(rtk_port_t port, rtk_qid_t queue, rtk_enable_t *pEnable); + +/* Function Name: + * dal_rtl8367d_rate_egrQueueBwCtrlRate_set + * Description: + * Set rate of egress bandwidth control on specified queue. + * Input: + * port - port id + * queue - queue id + * index - shared meter index + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_QUEUE_ID - invalid queue id + * RT_ERR_FILTER_METER_ID - Invalid meter id + * Note: + * The actual rate control is set in shared meters. + * The unit of granularity is 8Kbps. + */ +extern rtk_api_ret_t dal_rtl8367d_rate_egrQueueBwCtrlRate_set(rtk_port_t port, rtk_qid_t queue, rtk_meter_id_t index); + +/* Function Name: + * dal_rtl8367d_rate_egrQueueBwCtrlRate_get + * Description: + * Get rate of egress bandwidth control on specified queue. + * Input: + * port - port id + * queue - queue id + * pIndex - shared meter index + * Output: + * pRate - pointer to rate of egress queue bandwidth control + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_QUEUE_ID - invalid queue id + * RT_ERR_FILTER_METER_ID - Invalid meter id + * Note: + * The actual rate control is set in shared meters. + * The unit of granularity is 8Kbps. + */ +extern rtk_api_ret_t dal_rtl8367d_rate_egrQueueBwCtrlRate_get(rtk_port_t port, rtk_qid_t queue, rtk_meter_id_t *pIndex); +#endif + +#endif /* __DAL_RTL8371B_SHAREDMETER_H__ */ + + + + diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_storm.c b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_storm.c new file mode 100755 index 00000000..b4b6888c --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_storm.c @@ -0,0 +1,816 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8373 + * Feature : Here is a list of all functions and variables in Storm module. + * + */ + +#include +#include +#include +#include + +#include +#include +#include + + +/* Function Name: + * dal_rtl8373_rate_stormControlMeterIdx_set + * Description: + * Set the storm control meter index. + * Input: + * port - port id + * storm_type - storm group type + * index - storm control meter index. + * Output: + * None. + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - Invalid port id + * RT_ERR_FILTER_METER_ID - Invalid meter + * Note: + * + */ +rtk_api_ret_t dal_rtl8373_rate_stormControlMeterIdx_set(rtk_port_t port, rtk_rate_storm_group_t stormType, rtk_uint32 index) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if (stormType >= STORM_GROUP_END) + return RT_ERR_SFC_UNKNOWN_GROUP; + + if (index > RTL8373_METERMAX) + return RT_ERR_FILTER_METER_ID; + + switch (stormType) + { + case STORM_GROUP_UNKNOWN_UNICAST: + if((retVal = rtl8373_setAsicRegBits(RTL8373_RX_STORM_UNUCAST_METER_ADDR(port), RTL8373_RX_STORM_UNUCAST_METER_RX_STROM_UNUCAST_MIDX_MASK(port), index)) != RT_ERR_OK) + return retVal; + break; + case STORM_GROUP_UNKNOWN_MULTICAST: + if((retVal = rtl8373_setAsicRegBits(RTL8373_RX_STORM_UNMCAST_METER_ADDR(port), RTL8373_RX_STORM_UNMCAST_METER_RX_STROM_UNMCAST_MIDX_MASK(port), index)) != RT_ERR_OK) + return retVal; + break; + case STORM_GROUP_MULTICAST: + if((retVal = rtl8373_setAsicRegBits(RTL8373_RX_STORM_MCAST_METER_ADDR(port), RTL8373_RX_STORM_MCAST_METER_RX_STROM_MCAST_MIDX_MASK(port), index)) != RT_ERR_OK) + return retVal; + break; + case STORM_GROUP_BROADCAST: + if((retVal = rtl8373_setAsicRegBits(RTL8373_RX_STORM_BCAST_METER_ADDR(port), RTL8373_RX_STORM_BCAST_METER_RX_STROM_BCAST_MIDX_MASK(port), index)) != RT_ERR_OK) + return retVal; + break; + default: + break; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_rate_stormControlMeterIdx_get + * Description: + * Get the storm control meter index. + * Input: + * port - port id + * storm_type - storm group type + * Output: + * pIndex - storm control meter index. + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - Invalid port id + * RT_ERR_FILTER_METER_ID - Invalid meter + * Note: + * + */ +rtk_api_ret_t dal_rtl8373_rate_stormControlMeterIdx_get(rtk_port_t port, rtk_rate_storm_group_t stormType, rtk_uint32 *pIndex) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if (stormType >= STORM_GROUP_END) + return RT_ERR_SFC_UNKNOWN_GROUP; + + if (NULL == pIndex ) + return RT_ERR_NULL_POINTER; + + + switch (stormType) + { + case STORM_GROUP_UNKNOWN_UNICAST: + if((retVal = rtl8373_getAsicRegBits(RTL8373_RX_STORM_UNUCAST_METER_ADDR(port), RTL8373_RX_STORM_UNUCAST_METER_RX_STROM_UNUCAST_MIDX_MASK(port), pIndex)) != RT_ERR_OK) + return retVal; + break; + case STORM_GROUP_UNKNOWN_MULTICAST: + if((retVal = rtl8373_getAsicRegBits(RTL8373_RX_STORM_UNMCAST_METER_ADDR(port), RTL8373_RX_STORM_UNMCAST_METER_RX_STROM_UNMCAST_MIDX_MASK(port), pIndex)) != RT_ERR_OK) + return retVal; + break; + case STORM_GROUP_MULTICAST: + if((retVal = rtl8373_getAsicRegBits(RTL8373_RX_STORM_MCAST_METER_ADDR(port), RTL8373_RX_STORM_MCAST_METER_RX_STROM_MCAST_MIDX_MASK(port), pIndex)) != RT_ERR_OK) + return retVal; + break; + case STORM_GROUP_BROADCAST: + if((retVal = rtl8373_getAsicRegBits(RTL8373_RX_STORM_BCAST_METER_ADDR(port), RTL8373_RX_STORM_BCAST_METER_RX_STROM_BCAST_MIDX_MASK(port), pIndex)) != RT_ERR_OK) + return retVal; + break; + default: + break; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_rate_stormControlPortEnable_set + * Description: + * Set enable status of storm control on specified port. + * Input: + * port - port id + * stormType - storm group type + * enable - enable status of storm control + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +rtk_api_ret_t dal_rtl8373_rate_stormControlPortEnable_set(rtk_port_t port, rtk_rate_storm_group_t stormType, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if (stormType >= STORM_GROUP_END) + return RT_ERR_SFC_UNKNOWN_GROUP; + + if (enable >= RTK_ENABLE_END) + return RT_ERR_ENABLE; + + switch (stormType) + { + case STORM_GROUP_UNKNOWN_UNICAST: + if ((retVal = rtl8373_setAsicRegBit(RTL8373_RX_STORM_UNUCAST_CTRL_ADDR(port), RTL8373_RX_STORM_UNUCAST_CTRL_RX_STROM_UNUCAST_EN_OFFSET(port), enable)) != RT_ERR_OK) + return retVal; + break; + case STORM_GROUP_UNKNOWN_MULTICAST: + if ((retVal = rtl8373_setAsicRegBit(RTL8373_RX_STORM_UNMCAST_CTRL_ADDR(port), RTL8373_RX_STORM_UNMCAST_CTRL_RX_STROM_UNMCAST_EN_OFFSET(port), enable)) != RT_ERR_OK) + return retVal; + break; + case STORM_GROUP_MULTICAST: + if ((retVal = rtl8373_setAsicRegBit(RTL8373_RX_STORM_MCAST_CTRL_ADDR(port), RTL8373_RX_STORM_MCAST_CTRL_RX_STROM_MCAST_EN_OFFSET(port), enable)) != RT_ERR_OK) + return retVal; + break; + case STORM_GROUP_BROADCAST: + if ((retVal = rtl8373_setAsicRegBit(RTL8373_RX_STORM_BCAST_CTRL_ADDR(port), RTL8373_RX_STORM_BCAST_CTRL_RX_STROM_BCAST_EN_OFFSET(port), enable)) != RT_ERR_OK) + return retVal; + break; + default: + break; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_rate_stormControlPortEnable_set + * Description: + * Set enable status of storm control on specified port. + * Input: + * port - port id + * stormType - storm group type + * Output: + * pEnable - enable status of storm control + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +rtk_api_ret_t dal_rtl8373_rate_stormControlPortEnable_get(rtk_port_t port, rtk_rate_storm_group_t stormType, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if (stormType >= STORM_GROUP_END) + return RT_ERR_SFC_UNKNOWN_GROUP; + + if (NULL == pEnable) + return RT_ERR_ENABLE; + + switch (stormType) + { + case STORM_GROUP_UNKNOWN_UNICAST: + if ((retVal = rtl8373_getAsicRegBit(RTL8373_RX_STORM_UNUCAST_CTRL_ADDR(port), RTL8373_RX_STORM_UNUCAST_CTRL_RX_STROM_UNUCAST_EN_OFFSET(port), ®Data)) != RT_ERR_OK) + return retVal; + break; + case STORM_GROUP_UNKNOWN_MULTICAST: + if ((retVal = rtl8373_getAsicRegBit(RTL8373_RX_STORM_UNMCAST_CTRL_ADDR(port), RTL8373_RX_STORM_UNMCAST_CTRL_RX_STROM_UNMCAST_EN_OFFSET(port), ®Data)) != RT_ERR_OK) + return retVal; + break; + case STORM_GROUP_MULTICAST: + if ((retVal = rtl8373_getAsicRegBit(RTL8373_RX_STORM_MCAST_CTRL_ADDR(port), RTL8373_RX_STORM_MCAST_CTRL_RX_STROM_MCAST_EN_OFFSET(port), ®Data)) != RT_ERR_OK) + return retVal; + break; + case STORM_GROUP_BROADCAST: + if ((retVal = rtl8373_getAsicRegBit(RTL8373_RX_STORM_BCAST_CTRL_ADDR(port), RTL8373_RX_STORM_BCAST_CTRL_RX_STROM_BCAST_EN_OFFSET(port), ®Data)) != RT_ERR_OK) + return retVal; + break; + default: + break; + } + + *pEnable = (regData == 1) ? ENABLED : DISABLED; + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_rate_stormControlExtPortmask_set + * Description: + * Set externsion storm control port mask + * Input: + * Portmask - port mask + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +rtk_api_ret_t dal_rtl8373_rate_stormControlExtPortmask_set(rtk_uint32 portmask) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if( portmask > RTL8373_PORTMASK) + return RT_ERR_PORT_MASK; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_CFG_STORM_EXT_ADDR, RTL8373_CFG_STORM_EXT_STORM_EXT_EN_PORTMASK_MASK, portmask)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_rate_stormControlExtPortmask_get + * Description: + * Set externsion storm control port mask + * Input: + * None + * Output: + * pPortmask - port mask + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +rtk_api_ret_t dal_rtl8373_rate_stormControlExtPortmask_get(rtk_uint32 *pPortmask) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pPortmask) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8373_getAsicRegBits(RTL8373_CFG_STORM_EXT_ADDR, RTL8373_CFG_STORM_EXT_STORM_EXT_EN_PORTMASK_MASK, pPortmask)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_rate_stormControlExtEnable_set + * Description: + * Set externsion storm control state + * Input: + * stormType - storm group type + * enable - externsion storm control state + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +rtk_api_ret_t dal_rtl8373_rate_stormControlExtEnable_set(rtk_rate_storm_group_t stormType, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (stormType >= STORM_GROUP_END) + return RT_ERR_SFC_UNKNOWN_GROUP; + + if (enable >= RTK_ENABLE_END) + return RT_ERR_ENABLE; + + switch (stormType) + { + case STORM_GROUP_UNKNOWN_UNICAST: + if ((retVal = rtl8373_setAsicRegBit(RTL8373_CFG_STORM_EXT_ADDR, RTL8373_CFG_STORM_EXT_STORM_UNKNOWN_UCAST_EXT_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + break; + case STORM_GROUP_UNKNOWN_MULTICAST: + if ((retVal = rtl8373_setAsicRegBit(RTL8373_CFG_STORM_EXT_ADDR, RTL8373_CFG_STORM_EXT_STORM_UNKNOWN_MCAST_EXT_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + break; + case STORM_GROUP_MULTICAST: + if ((retVal = rtl8373_setAsicRegBit(RTL8373_CFG_STORM_EXT_ADDR, RTL8373_CFG_STORM_EXT_STORM_MCAST_EXT_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + break; + case STORM_GROUP_BROADCAST: + if ((retVal = rtl8373_setAsicRegBit(RTL8373_CFG_STORM_EXT_ADDR, RTL8373_CFG_STORM_EXT_STORM_BCAST_EXT_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + break; + default: + break; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_rate_stormControlExtEnable_get + * Description: + * Get externsion storm control state + * Input: + * stormType - storm group type + * Output: + * pEnable - externsion storm control state + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +rtk_api_ret_t dal_rtl8373_rate_stormControlExtEnable_get(rtk_rate_storm_group_t stormType, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + //rtk_uint32 regData; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (stormType >= STORM_GROUP_END) + return RT_ERR_SFC_UNKNOWN_GROUP; + + if (NULL == pEnable) + return RT_ERR_NULL_POINTER; + + switch (stormType) + { + case STORM_GROUP_UNKNOWN_UNICAST: + if ((retVal = rtl8373_getAsicRegBit(RTL8373_CFG_STORM_EXT_ADDR, RTL8373_CFG_STORM_EXT_STORM_UNKNOWN_UCAST_EXT_EN_OFFSET, pEnable)) != RT_ERR_OK) + return retVal; + break; + case STORM_GROUP_UNKNOWN_MULTICAST: + if ((retVal = rtl8373_getAsicRegBit(RTL8373_CFG_STORM_EXT_ADDR, RTL8373_CFG_STORM_EXT_STORM_UNKNOWN_MCAST_EXT_EN_OFFSET, pEnable)) != RT_ERR_OK) + return retVal; + break; + case STORM_GROUP_MULTICAST: + if ((retVal = rtl8373_getAsicRegBit(RTL8373_CFG_STORM_EXT_ADDR, RTL8373_CFG_STORM_EXT_STORM_MCAST_EXT_EN_OFFSET, pEnable)) != RT_ERR_OK) + return retVal; + break; + case STORM_GROUP_BROADCAST: + if ((retVal = rtl8373_getAsicRegBit(RTL8373_CFG_STORM_EXT_ADDR, RTL8373_CFG_STORM_EXT_STORM_BCAST_EXT_EN_OFFSET, pEnable)) != RT_ERR_OK) + return retVal; + break; + default: + break; + } + + //*pEnable = (regData == 1) ? ENABLED : DISABLED; + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_rate_stormControlExtMeterIdx_set + * Description: + * Set externsion storm control meter index + * Input: + * stormType - storm group type + * index - externsion storm control state + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +rtk_api_ret_t dal_rtl8373_rate_stormControlExtMeterIdx_set(rtk_rate_storm_group_t stormType, rtk_uint32 index) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (stormType >= STORM_GROUP_END) + return RT_ERR_SFC_UNKNOWN_GROUP; + + if (index > RTL8373_METERMAX) + return RT_ERR_FILTER_METER_ID; + + switch (stormType) + { + case STORM_GROUP_UNKNOWN_UNICAST: + if ((retVal = rtl8373_setAsicRegBits(RTL8373_STORM_EXT_MTRIDX_CFG_ADDR, RTL8373_STORM_EXT_MTRIDX_CFG_STORM_UNKNOWN_UCAST_EXT_METERID_MASK, index))!=RT_ERR_OK) + return retVal; + break; + case STORM_GROUP_UNKNOWN_MULTICAST: + if ((retVal = rtl8373_setAsicRegBits(RTL8373_STORM_EXT_MTRIDX_CFG_ADDR, RTL8373_STORM_EXT_MTRIDX_CFG_STORM_UNKNOWN_MCAST_EXT_METERID_MASK, index))!=RT_ERR_OK) + return retVal; + break; + case STORM_GROUP_MULTICAST: + if ((retVal = rtl8373_setAsicRegBits(RTL8373_STORM_EXT_MTRIDX_CFG_ADDR, RTL8373_STORM_EXT_MTRIDX_CFG_STORM_MCAST_EXT_METERID_MASK, index))!=RT_ERR_OK) + return retVal; + break; + case STORM_GROUP_BROADCAST: + if ((retVal = rtl8373_setAsicRegBits(RTL8373_STORM_EXT_MTRIDX_CFG_ADDR, RTL8373_STORM_EXT_MTRIDX_CFG_STORM_BCAST_EXT_METERID_MASK, index))!=RT_ERR_OK) + return retVal; + break; + default: + break; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_rate_stormControlExtMeterIdx_get + * Description: + * Get externsion storm control meter index + * Input: + * stormType - storm group type + * Output: + * pIndex - externsion storm control state + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +rtk_api_ret_t dal_rtl8373_rate_stormControlExtMeterIdx_get(rtk_rate_storm_group_t stormType, rtk_uint32 *pIndex) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (stormType >= STORM_GROUP_END) + return RT_ERR_SFC_UNKNOWN_GROUP; + + if(NULL == pIndex) + return RT_ERR_NULL_POINTER; + + switch (stormType) + { + case STORM_GROUP_UNKNOWN_UNICAST: + if ((retVal = rtl8373_getAsicRegBits(RTL8373_STORM_EXT_MTRIDX_CFG_ADDR, RTL8373_STORM_EXT_MTRIDX_CFG_STORM_UNKNOWN_UCAST_EXT_METERID_MASK, pIndex))!=RT_ERR_OK) + return retVal; + break; + case STORM_GROUP_UNKNOWN_MULTICAST: + if ((retVal = rtl8373_getAsicRegBits(RTL8373_STORM_EXT_MTRIDX_CFG_ADDR, RTL8373_STORM_EXT_MTRIDX_CFG_STORM_UNKNOWN_MCAST_EXT_METERID_MASK, pIndex))!=RT_ERR_OK) + return retVal; + break; + case STORM_GROUP_MULTICAST: + if ((retVal = rtl8373_getAsicRegBits(RTL8373_STORM_EXT_MTRIDX_CFG_ADDR, RTL8373_STORM_EXT_MTRIDX_CFG_STORM_MCAST_EXT_METERID_MASK, pIndex))!=RT_ERR_OK) + return retVal; + break; + case STORM_GROUP_BROADCAST: + if ((retVal = rtl8373_getAsicRegBits(RTL8373_STORM_EXT_MTRIDX_CFG_ADDR, RTL8373_STORM_EXT_MTRIDX_CFG_STORM_BCAST_EXT_METERID_MASK, pIndex))!=RT_ERR_OK) + return retVal; + break; + default: + break; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_storm_bypass_set + * Description: + * Set bypass storm filter control configuration. + * Input: + * type - Bypass storm filter control type. + * enable - Bypass status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_ENABLE - Invalid IFG parameter + * Note: + * + * This API can set per-port bypass stomr filter control frame type including RMA and igmp. + * The bypass frame type is as following: + * - BYPASS_BRG_GROUP, + * - BYPASS_FD_PAUSE, + * - BYPASS_SP_MCAST, + * - BYPASS_1X_PAE, + * - BYPASS_UNDEF_BRG_04, + * - BYPASS_UNDEF_BRG_05, + * - BYPASS_UNDEF_BRG_06, + * - BYPASS_UNDEF_BRG_07, + * - BYPASS_PROVIDER_BRIDGE_GROUP_ADDRESS, + * - BYPASS_UNDEF_BRG_09, + * - BYPASS_UNDEF_BRG_0A, + * - BYPASS_UNDEF_BRG_0B, + * - BYPASS_UNDEF_BRG_0C, + * - BYPASS_PROVIDER_BRIDGE_GVRP_ADDRESS, + * - BYPASS_8021AB, + * - BYPASS_UNDEF_BRG_0F, + * - BYPASS_BRG_MNGEMENT, + * - BYPASS_UNDEFINED_11, + * - BYPASS_UNDEFINED_12, + * - BYPASS_UNDEFINED_13, + * - BYPASS_UNDEFINED_14, + * - BYPASS_UNDEFINED_15, + * - BYPASS_UNDEFINED_16, + * - BYPASS_UNDEFINED_17, + * - BYPASS_UNDEFINED_18, + * - BYPASS_UNDEFINED_19, + * - BYPASS_UNDEFINED_1A, + * - BYPASS_UNDEFINED_1B, + * - BYPASS_UNDEFINED_1C, + * - BYPASS_UNDEFINED_1D, + * - BYPASS_UNDEFINED_1E, + * - BYPASS_UNDEFINED_1F, + * - BYPASS_GMRP, + * - BYPASS_GVRP, + * - BYPASS_UNDEF_GARP_22, + * - BYPASS_UNDEF_GARP_23, + * - BYPASS_UNDEF_GARP_24, + * - BYPASS_UNDEF_GARP_25, + * - BYPASS_UNDEF_GARP_26, + * - BYPASS_UNDEF_GARP_27, + * - BYPASS_UNDEF_GARP_28, + * - BYPASS_UNDEF_GARP_29, + * - BYPASS_UNDEF_GARP_2A, + * - BYPASS_UNDEF_GARP_2B, + * - BYPASS_UNDEF_GARP_2C, + * - BYPASS_UNDEF_GARP_2D, + * - BYPASS_UNDEF_GARP_2E, + * - BYPASS_UNDEF_GARP_2F, + * - BYPASS_IGMP. + * - BYPASS_CDP. + * - BYPASS_CSSTP. + * - BYPASS_LLDP. + */ +rtk_api_ret_t dal_rtl8373_storm_bypass_set(rtk_storm_bypass_t type, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + rtk_rmaParam_t rmacfg; + rtk_uint32 tmp; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (type >= BYPASS_END) + return RT_ERR_INPUT; + + if (enable >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if (type >= 0 && type <= BYPASS_UNDEF_GARP_2F) + { + if ((retVal = dal_rtl8373_asicRma_get(type, &rmacfg)) != RT_ERR_OK) + return retVal; + + rmacfg.discard_storm_filter = enable; + + if ((retVal = dal_rtl8373_asicRma_set(type, &rmacfg)) != RT_ERR_OK) + return retVal; + } + else if(type == BYPASS_IGMP) + { + if ((retVal = dal_rtl8373_setAsicIGMPBypassStormCTRL(enable)) != RT_ERR_OK) + return retVal; + } + else if (type == BYPASS_CDP) + { + if ((retVal = dal_rtl8373_asicRmaCdp_get(&rmacfg)) != RT_ERR_OK) + return retVal; + + rmacfg.discard_storm_filter = enable; + + if ((retVal = dal_rtl8373_asicRmaCdp_set(&rmacfg)) != RT_ERR_OK) + return retVal; + } + else if (type == BYPASS_CSSTP) + { + if ((retVal = dal_rtl8373_asicRmaCsstp_get(&rmacfg)) != RT_ERR_OK) + return retVal; + + rmacfg.discard_storm_filter = enable; + + if ((retVal = dal_rtl8373_asicRmaCsstp_set(&rmacfg)) != RT_ERR_OK) + return retVal; + } + else if (type == BYPASS_LLDP) + { + if ((retVal = dal_rtl8373_asicRmaLldp_get(&tmp, &rmacfg)) != RT_ERR_OK) + return retVal; + + rmacfg.discard_storm_filter = enable; + + if ((retVal = dal_rtl8373_asicRmaLldp_set(tmp, &rmacfg)) != RT_ERR_OK) + return retVal; + } + else + return RT_ERR_INPUT; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8367c_storm_bypass_get + * Description: + * Get bypass storm filter control configuration. + * Input: + * type - Bypass storm filter control type. + * Output: + * pEnable - Bypass status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can get per-port bypass stomr filter control frame type including RMA and igmp. + * The bypass frame type is as following: + * - BYPASS_BRG_GROUP, + * - BYPASS_FD_PAUSE, + * - BYPASS_SP_MCAST, + * - BYPASS_1X_PAE, + * - BYPASS_UNDEF_BRG_04, + * - BYPASS_UNDEF_BRG_05, + * - BYPASS_UNDEF_BRG_06, + * - BYPASS_UNDEF_BRG_07, + * - BYPASS_PROVIDER_BRIDGE_GROUP_ADDRESS, + * - BYPASS_UNDEF_BRG_09, + * - BYPASS_UNDEF_BRG_0A, + * - BYPASS_UNDEF_BRG_0B, + * - BYPASS_UNDEF_BRG_0C, + * - BYPASS_PROVIDER_BRIDGE_GVRP_ADDRESS, + * - BYPASS_8021AB, + * - BYPASS_UNDEF_BRG_0F, + * - BYPASS_BRG_MNGEMENT, + * - BYPASS_UNDEFINED_11, + * - BYPASS_UNDEFINED_12, + * - BYPASS_UNDEFINED_13, + * - BYPASS_UNDEFINED_14, + * - BYPASS_UNDEFINED_15, + * - BYPASS_UNDEFINED_16, + * - BYPASS_UNDEFINED_17, + * - BYPASS_UNDEFINED_18, + * - BYPASS_UNDEFINED_19, + * - BYPASS_UNDEFINED_1A, + * - BYPASS_UNDEFINED_1B, + * - BYPASS_UNDEFINED_1C, + * - BYPASS_UNDEFINED_1D, + * - BYPASS_UNDEFINED_1E, + * - BYPASS_UNDEFINED_1F, + * - BYPASS_GMRP, + * - BYPASS_GVRP, + * - BYPASS_UNDEF_GARP_22, + * - BYPASS_UNDEF_GARP_23, + * - BYPASS_UNDEF_GARP_24, + * - BYPASS_UNDEF_GARP_25, + * - BYPASS_UNDEF_GARP_26, + * - BYPASS_UNDEF_GARP_27, + * - BYPASS_UNDEF_GARP_28, + * - BYPASS_UNDEF_GARP_29, + * - BYPASS_UNDEF_GARP_2A, + * - BYPASS_UNDEF_GARP_2B, + * - BYPASS_UNDEF_GARP_2C, + * - BYPASS_UNDEF_GARP_2D, + * - BYPASS_UNDEF_GARP_2E, + * - BYPASS_UNDEF_GARP_2F, + * - BYPASS_IGMP. + * - BYPASS_CDP. + * - BYPASS_CSSTP. + * - BYPASS_LLDP. + */ +rtk_api_ret_t dal_rtl8373_storm_bypass_get(rtk_storm_bypass_t type, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + rtk_rmaParam_t rmacfg; + rtk_uint32 tmp; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (type >= BYPASS_END) + return RT_ERR_INPUT; + + if(NULL == pEnable) + return RT_ERR_NULL_POINTER; + + if (type >= 0 && type <= BYPASS_UNDEF_GARP_2F) + { + if ((retVal = dal_rtl8373_asicRma_get(type, &rmacfg)) != RT_ERR_OK) + return retVal; + + *pEnable = rmacfg.discard_storm_filter; + } + else if(type == BYPASS_IGMP) + { + if ((retVal = dal_rtl8373_getAsicIGMPBypassStormCTRL(pEnable)) != RT_ERR_OK) + return retVal; + } + else if (type == BYPASS_CDP) + { + if ((retVal = dal_rtl8373_asicRmaCdp_get(&rmacfg)) != RT_ERR_OK) + return retVal; + + *pEnable = rmacfg.discard_storm_filter; + } + else if (type == BYPASS_CSSTP) + { + if ((retVal = dal_rtl8373_asicRmaCsstp_get(&rmacfg)) != RT_ERR_OK) + return retVal; + + *pEnable = rmacfg.discard_storm_filter; + } + else if (type == BYPASS_LLDP) + { + if ((retVal = dal_rtl8373_asicRmaLldp_get(&tmp,&rmacfg)) != RT_ERR_OK) + return retVal; + + *pEnable = rmacfg.discard_storm_filter; + } + else + return RT_ERR_INPUT; + + return RT_ERR_OK; +} + + + + diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_storm.h b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_storm.h new file mode 100755 index 00000000..2cb9b0f7 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_storm.h @@ -0,0 +1,355 @@ + /* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8373 switch high-level API + * + * Feature : The file includes Storm module high-layer API defination + * + */ + +#ifndef __DAL_RTL8373_STORM_H__ +#define __DAL_RTL8373_STORM_H__ + +#include + +/* Function Name: + * dal_rtl8373_rate_stormControlMeterIdx_set + * Description: + * Set the storm control meter index. + * Input: + * port - port id + * storm_type - storm group type + * index - storm control meter index. + * Output: + * None. + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - Invalid port id + * RT_ERR_FILTER_METER_ID - Invalid meter + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8373_rate_stormControlMeterIdx_set(rtk_port_t port, rtk_rate_storm_group_t stormType, rtk_uint32 index); + +/* Function Name: + * dal_rtl8373_rate_stormControlMeterIdx_get + * Description: + * Get the storm control meter index. + * Input: + * port - port id + * storm_type - storm group type + * Output: + * pIndex - storm control meter index. + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - Invalid port id + * RT_ERR_FILTER_METER_ID - Invalid meter + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8373_rate_stormControlMeterIdx_get(rtk_port_t port, rtk_rate_storm_group_t stormType, rtk_uint32 *pIndex); + +/* Function Name: + * dal_rtl8373_rate_stormControlPortEnable_set + * Description: + * Set enable status of storm control on specified port. + * Input: + * port - port id + * stormType - storm group type + * enable - enable status of storm control + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8373_rate_stormControlPortEnable_set(rtk_port_t port, rtk_rate_storm_group_t stormType, rtk_enable_t enable); + +/* Function Name: + * dal_rtl8373_rate_stormControlPortEnable_set + * Description: + * Set enable status of storm control on specified port. + * Input: + * port - port id + * stormType - storm group type + * Output: + * pEnable - enable status of storm control + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8373_rate_stormControlPortEnable_get(rtk_port_t port, rtk_rate_storm_group_t stormType, rtk_enable_t *pEnable); + +/* Function Name: + * dal_rtl8367d_storm_bypass_set + * Description: + * Set bypass storm filter control configuration. + * Input: + * type - Bypass storm filter control type. + * enable - Bypass status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_ENABLE - Invalid IFG parameter + * Note: + * + * This API can set per-port bypass stomr filter control frame type including RMA and igmp. + * The bypass frame type is as following: + * - BYPASS_BRG_GROUP, + * - BYPASS_FD_PAUSE, + * - BYPASS_SP_MCAST, + * - BYPASS_1X_PAE, + * - BYPASS_UNDEF_BRG_04, + * - BYPASS_UNDEF_BRG_05, + * - BYPASS_UNDEF_BRG_06, + * - BYPASS_UNDEF_BRG_07, + * - BYPASS_PROVIDER_BRIDGE_GROUP_ADDRESS, + * - BYPASS_UNDEF_BRG_09, + * - BYPASS_UNDEF_BRG_0A, + * - BYPASS_UNDEF_BRG_0B, + * - BYPASS_UNDEF_BRG_0C, + * - BYPASS_PROVIDER_BRIDGE_GVRP_ADDRESS, + * - BYPASS_8021AB, + * - BYPASS_UNDEF_BRG_0F, + * - BYPASS_BRG_MNGEMENT, + * - BYPASS_UNDEFINED_11, + * - BYPASS_UNDEFINED_12, + * - BYPASS_UNDEFINED_13, + * - BYPASS_UNDEFINED_14, + * - BYPASS_UNDEFINED_15, + * - BYPASS_UNDEFINED_16, + * - BYPASS_UNDEFINED_17, + * - BYPASS_UNDEFINED_18, + * - BYPASS_UNDEFINED_19, + * - BYPASS_UNDEFINED_1A, + * - BYPASS_UNDEFINED_1B, + * - BYPASS_UNDEFINED_1C, + * - BYPASS_UNDEFINED_1D, + * - BYPASS_UNDEFINED_1E, + * - BYPASS_UNDEFINED_1F, + * - BYPASS_GMRP, + * - BYPASS_GVRP, + * - BYPASS_UNDEF_GARP_22, + * - BYPASS_UNDEF_GARP_23, + * - BYPASS_UNDEF_GARP_24, + * - BYPASS_UNDEF_GARP_25, + * - BYPASS_UNDEF_GARP_26, + * - BYPASS_UNDEF_GARP_27, + * - BYPASS_UNDEF_GARP_28, + * - BYPASS_UNDEF_GARP_29, + * - BYPASS_UNDEF_GARP_2A, + * - BYPASS_UNDEF_GARP_2B, + * - BYPASS_UNDEF_GARP_2C, + * - BYPASS_UNDEF_GARP_2D, + * - BYPASS_UNDEF_GARP_2E, + * - BYPASS_UNDEF_GARP_2F, + * - BYPASS_IGMP. + */ +extern rtk_api_ret_t dal_rtl8373_storm_bypass_set(rtk_storm_bypass_t type, rtk_enable_t enable); + +/* Function Name: + * dal_rtl8367d_storm_bypass_get + * Description: + * Get bypass storm filter control configuration. + * Input: + * type - Bypass storm filter control type. + * Output: + * pEnable - Bypass status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can get per-port bypass stomr filter control frame type including RMA and igmp. + * The bypass frame type is as following: + * - BYPASS_BRG_GROUP, + * - BYPASS_FD_PAUSE, + * - BYPASS_SP_MCAST, + * - BYPASS_1X_PAE, + * - BYPASS_UNDEF_BRG_04, + * - BYPASS_UNDEF_BRG_05, + * - BYPASS_UNDEF_BRG_06, + * - BYPASS_UNDEF_BRG_07, + * - BYPASS_PROVIDER_BRIDGE_GROUP_ADDRESS, + * - BYPASS_UNDEF_BRG_09, + * - BYPASS_UNDEF_BRG_0A, + * - BYPASS_UNDEF_BRG_0B, + * - BYPASS_UNDEF_BRG_0C, + * - BYPASS_PROVIDER_BRIDGE_GVRP_ADDRESS, + * - BYPASS_8021AB, + * - BYPASS_UNDEF_BRG_0F, + * - BYPASS_BRG_MNGEMENT, + * - BYPASS_UNDEFINED_11, + * - BYPASS_UNDEFINED_12, + * - BYPASS_UNDEFINED_13, + * - BYPASS_UNDEFINED_14, + * - BYPASS_UNDEFINED_15, + * - BYPASS_UNDEFINED_16, + * - BYPASS_UNDEFINED_17, + * - BYPASS_UNDEFINED_18, + * - BYPASS_UNDEFINED_19, + * - BYPASS_UNDEFINED_1A, + * - BYPASS_UNDEFINED_1B, + * - BYPASS_UNDEFINED_1C, + * - BYPASS_UNDEFINED_1D, + * - BYPASS_UNDEFINED_1E, + * - BYPASS_UNDEFINED_1F, + * - BYPASS_GMRP, + * - BYPASS_GVRP, + * - BYPASS_UNDEF_GARP_22, + * - BYPASS_UNDEF_GARP_23, + * - BYPASS_UNDEF_GARP_24, + * - BYPASS_UNDEF_GARP_25, + * - BYPASS_UNDEF_GARP_26, + * - BYPASS_UNDEF_GARP_27, + * - BYPASS_UNDEF_GARP_28, + * - BYPASS_UNDEF_GARP_29, + * - BYPASS_UNDEF_GARP_2A, + * - BYPASS_UNDEF_GARP_2B, + * - BYPASS_UNDEF_GARP_2C, + * - BYPASS_UNDEF_GARP_2D, + * - BYPASS_UNDEF_GARP_2E, + * - BYPASS_UNDEF_GARP_2F, + * - BYPASS_IGMP. + */ +extern rtk_api_ret_t dal_rtl8373_storm_bypass_get(rtk_storm_bypass_t type, rtk_enable_t *pEnable); + +/* Function Name: + * dal_rtl8373_rate_stormControlExtPortmask_set + * Description: + * Set externsion storm control port mask + * Input: + * Portmask - port mask + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8373_rate_stormControlExtPortmask_set(rtk_uint32 portmask); + +/* Function Name: + * dal_rtl8373_rate_stormControlExtPortmask_get + * Description: + * Set externsion storm control port mask + * Input: + * None + * Output: + * pPortmask - port mask + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8373_rate_stormControlExtPortmask_get(rtk_uint32 *pPortmask); + +/* Function Name: + * dal_rtl8373_rate_stormControlExtEnable_set + * Description: + * Set externsion storm control state + * Input: + * stormType - storm group type + * enable - externsion storm control state + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8373_rate_stormControlExtEnable_set(rtk_rate_storm_group_t stormType, rtk_enable_t enable); + +/* Function Name: + * dal_rtl8373_rate_stormControlExtEnable_get + * Description: + * Get externsion storm control state + * Input: + * stormType - storm group type + * Output: + * pEnable - externsion storm control state + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8373_rate_stormControlExtEnable_get(rtk_rate_storm_group_t stormType, rtk_enable_t *pEnable); + +/* Function Name: + * dal_rtl8373_rate_stormControlExtMeterIdx_set + * Description: + * Set externsion storm control meter index + * Input: + * stormType - storm group type + * index - externsion storm control state + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8373_rate_stormControlExtMeterIdx_set(rtk_rate_storm_group_t stormType, rtk_uint32 index); + +/* Function Name: + * dal_rtl8373_rate_stormControlExtMeterIdx_get + * Description: + * Get externsion storm control meter index + * Input: + * stormType - storm group type + * Output: + * pIndex - externsion storm control state + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8373_rate_stormControlExtMeterIdx_get(rtk_rate_storm_group_t stormType, rtk_uint32 *pIndex); + + + +#endif /* __DAL_RTL8367D_STORM_H__ */ + diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_stp.c b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_stp.c new file mode 100755 index 00000000..57e3ff2a --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_stp.c @@ -0,0 +1,95 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8373 + * Feature : Here is a list of all functions and variables in RMA module. + * + */ + +#include +#include +#include +#include +#include + + +/* Function Name: + * dal_rtl8373_asicMstpPortStatus_set + * Description: + * Set MSTP port status + * Input: + * fid - mstp index + * port - + * statys - 0 disable 1 blocking 2 learning 3 forwarding + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t dal_rtl8373_asicMstpPortStatus_set(rtk_uint32 fid, rtk_uint32 port, rtk_uint32 status) +{ + ret_t retVal; + + if(fid > RTL8373_FIDMAX) + return RT_ERR_INPUT; + + + retVal = rtl8373_setAsicRegBits(RTL8373_MSPT_STATE_ADDR(fid), 0x3<<(port*2), status); + if(retVal != RT_ERR_OK) + return retVal; + + return retVal; +} + + +/* Function Name: + * dal_rtl8373_asicMstpPortStatus_get + * Description: + * Get MSTP port status + * Input: + * fid - mstp index + * port - + * *pStatys - 0 disable 1 blocking 2 learning 3 forwarding + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +ret_t dal_rtl8373_asicMstpPortStatus_get(rtk_uint32 fid, rtk_uint32 port, rtk_uint32* pStatus) +{ + ret_t retVal; + + if(fid > RTL8373_FIDMAX) + return RT_ERR_INPUT; + + + retVal = rtl8373_getAsicRegBits(RTL8373_MSPT_STATE_ADDR(fid), 0x3<<(port*2), pStatus); + if(retVal != RT_ERR_OK) + return retVal; + + return retVal; +} + + + + + + + diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_stp.h b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_stp.h new file mode 100755 index 00000000..d0076fb9 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_stp.h @@ -0,0 +1,59 @@ +#ifndef __DAL_RTL8373_STP_H__ +#define __DAL_RTL8373_STP_H__ + +#include +#include +#include +#include + +enum RTL8373_MSTP_STATE +{ + MSTP_DISABLE = 0, + MSTP_BLOCKING, + MSTP_LEARNING, + MSTP_FORWARDING, + MSTP_END +}; + +/* Function Name: + * dal_rtl8373_asicMstpPortStatus_set + * Description: + * Set MSTP port status + * Input: + * fid - mstp index + * port - + * statys - 0 disable 1 blocking 2 learning 3 forwarding + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +extern ret_t dal_rtl8373_asicMstpPortStatus_set(rtk_uint32 fid, rtk_uint32 port, rtk_uint32 status); + + + +/* Function Name: + * dal_rtl8373_asicMstpPortStatus_get + * Description: + * Get MSTP port status + * Input: + * fid - mstp index + * port - + * *pStatys - 0 disable 1 blocking 2 learning 3 forwarding + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +extern ret_t dal_rtl8373_asicMstpPortStatus_get(rtk_uint32 fid, rtk_uint32 port, rtk_uint32* pStatus); + + + +#endif + diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_svlan.c b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_svlan.c new file mode 100755 index 00000000..a812bb1e --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_svlan.c @@ -0,0 +1,1084 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8373 + * Feature : Here is a list of all functions and variables in SVLAN module. + * + */ + +#include +#include +//#include +#include +#include +#include +#include + + +/* Function Name: + * dal_rtl8373_svlanInit + * Description: + * Initialize SVLAN Configuration + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * Ether type of S-tag in 802.1ad is 0x88a8 and there are existed ether type 0x9100 and 0x9200 for Q-in-Q SLAN design. + * User can set mathced ether type as service provider supported protocol. + */ +rtk_api_ret_t dal_rtl8373_svlanInit(void) +{ + rtk_uint32 idx = 0; + rtk_api_ret_t retVal = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + /*default use C-priority*/ + if ((retVal = dal_rtl8373_svlanPriRef_set(REF_CTAG_PRI)) != RT_ERR_OK) + return retVal; + + /*Drop SVLAN untag frame*/ + if ((retVal = dal_rtl8373_svlanUntagAction_set(UNTAG_DROP, 0)) != RT_ERR_OK) + return retVal; + /*Set TPID to 0x88a8*/ + if ((retVal = dal_rtl8373_svlanTpid_set(0x88a8)) != RT_ERR_OK) + return retVal; + /*Clean Uplink Port Mask to none*/ + if ((retVal = rtl8373_setAsicReg(RTL8373_VS_UPLINK_PORT_ADDR,0)) != RT_ERR_OK) + return retVal; + /*Clean C2S Configuration*/ + for (idx = 0; idx <= RTL8373_C2SIDXMAX; idx++) + { + if ((retVal = rtl8373_setAsicReg(RTL8373_VLAN_C2S_ENTRY_ADDR(idx)+4, 0)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_setAsicReg(RTL8373_VLAN_C2S_ENTRY_ADDR(idx), 0)) != RT_ERR_OK) + return retVal; + } + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_svlanServicePort_add + * Description: + * Add one service port in the specified device + * Input: + * port - Port id. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API is setting which port is connected to provider switch. All frames receiving from this port must + * contain accept SVID in S-tag field. + */ +rtk_api_ret_t dal_rtl8373_svlanServicePort_add(rtk_port_t port) +{ + rtk_api_ret_t retVal = 0; + rtk_uint32 pmsk = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* check port valid */ + RTK_CHK_PORT_VALID(port); + + if ((retVal = rtl8373_getAsicReg(RTL8373_VS_UPLINK_PORT_ADDR, &pmsk)) != RT_ERR_OK) + return retVal; + + pmsk = pmsk | (1<RTK_MAX_NUM_OF_PROTO_TYPE) + return RT_ERR_INPUT; + + if ((retVal = rtl8373_setAsicReg(RTL8373_VS_GLB_CTRL_ADDR, svlanTpid)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_svlanTpid_get + * Description: + * Get accepted S-VLAN ether type setting. + * Input: + * None + * Output: + * pSvlanTpid - Ether type of S-tag frame parsing in uplink ports. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API is setting which port is connected to provider switch. All frames receiving from this port must + * contain accept SVID in S-tag field. + */ +rtk_api_ret_t dal_rtl8373_svlanTpid_get(rtk_uint32 *pSvlanTpid) +{ + rtk_api_ret_t retVal = 0; + rtk_uint32 regVal = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pSvlanTpid) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8373_getAsicReg(RTL8373_VS_GLB_CTRL_ADDR, ®Val)) != RT_ERR_OK) + return retVal; + + *pSvlanTpid = (regVal & RTK_MAX_NUM_OF_PROTO_TYPE); + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_svlanPriRef_set + * Description: + * Set S-VLAN upstream priority reference setting. + * Input: + * ref - reference selection parameter. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * Note: + * The API can set the upstream SVLAN tag priority reference source. The related priority + * sources are as following: + * - REF_INTERNAL_PRI, + * - REF_CTAG_PRI, + * - REF_SVLAN_PRI, + * - REF_PB_PRI. + */ +rtk_api_ret_t dal_rtl8373_svlanPriRef_set(rtk_svlan_pri_ref_t ref) +{ + rtk_api_ret_t retVal = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (ref >= REF_PRI_END) + return RT_ERR_INPUT; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_VS_CTRL_ADDR, RTL8373_VS_CTRL_SPRISEL_MASK, ref)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_svlanPriRef_get + * Description: + * Get S-VLAN upstream priority reference setting. + * Input: + * None + * Output: + * pRef - reference selection parameter. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can get the upstream SVLAN tag priority reference source. The related priority + * sources are as following: + * - REF_INTERNAL_PRI, + * - REF_CTAG_PRI, + * - REF_SVLAN_PRI, + * - REF_PB_PRI + */ +rtk_api_ret_t dal_rtl8373_svlanPriRef_get(rtk_svlan_pri_ref_t *pRef) +{ + rtk_api_ret_t retVal = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pRef) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8373_getAsicRegBits(RTL8373_VS_CTRL_ADDR, RTL8373_VS_CTRL_SPRISEL_MASK, pRef)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_svlanmemberPortEntry_set + * Description: + * Configure system SVLAN member content + * Input: + * svid - SVLAN id + * psvlan_cfg - SVLAN member configuration + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_PORT_MASK - Invalid portmask. + * RT_ERR_SVLAN_TABLE_FULL - SVLAN configuration is full. + * Note: + * The API can set system 64 accepted s-tag frame format. Only 64 SVID S-tag frame will be accpeted + * to receiving from uplink ports. Other SVID S-tag frame or S-untagged frame will be droped by default setup. + * - rtk_svlan_memberCfg_t->svid is SVID of SVLAN member configuration. + * - rtk_svlan_memberCfg_t->memberport is member port mask of SVLAN member configuration. + * - rtk_svlan_memberCfg_t->fid is filtering database of SVLAN member configuration. + * - rtk_svlan_memberCfg_t->priority is priority of SVLAN member configuration. + */ +rtk_api_ret_t dal_rtl8373_svlanMbrPortEntry_set(rtk_vlan_t svid, rtk_svlan_memberCfg_t *pSvlan_cfg) +{ + rtk_api_ret_t retVal = 0; + rtk_uint32 phyMbrPmask, phyUntagPmask; + dal_rtl8373_user_vlan4kentry vlan4kEntry; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pSvlan_cfg) + return RT_ERR_NULL_POINTER; + + if(svid > RTL8373_VIDMAX) + return RT_ERR_SVLAN_VID; + + RTK_CHK_PORTMASK_VALID(&pSvlan_cfg->memberport); + + RTK_CHK_PORTMASK_VALID(&pSvlan_cfg->untagport); + + if (pSvlan_cfg->fid > RTL8373_FIDMAX) + return RT_ERR_L2_FID; + + if (pSvlan_cfg->chk_ivl_svl> ENABLED) + return RT_ERR_INPUT; + + if (pSvlan_cfg->ivl_svl> ENABLED) + return RT_ERR_INPUT; + + if (pSvlan_cfg->fiden !=0) + return RT_ERR_CHIP_NOT_SUPPORTED; + + if (pSvlan_cfg->priority != 0) + return RT_ERR_CHIP_NOT_SUPPORTED; + + if (pSvlan_cfg->efiden != 0) + return RT_ERR_CHIP_NOT_SUPPORTED; + + if (pSvlan_cfg->efid != 0) + return RT_ERR_CHIP_NOT_SUPPORTED; + + /* Get physical port mask */ + if(rtk_switch_portmask_L2P_get(&(pSvlan_cfg->memberport), &phyMbrPmask) != RT_ERR_OK) + return RT_ERR_FAILED; + if(rtk_switch_portmask_L2P_get(&(pSvlan_cfg->untagport), &phyUntagPmask) != RT_ERR_OK) + return RT_ERR_FAILED; + + memset(&vlan4kEntry, 0, sizeof(dal_rtl8373_user_vlan4kentry)); + vlan4kEntry.vid = svid; + if ((retVal = _dal_rtl8373_getAsicVlan4kEntry(&vlan4kEntry)) != RT_ERR_OK) + return retVal; + + vlan4kEntry.vid = svid; + vlan4kEntry.mbr = phyMbrPmask; + vlan4kEntry.untag = phyUntagPmask; + vlan4kEntry.svlan_chk_ivl_svl = pSvlan_cfg->chk_ivl_svl; + vlan4kEntry.ivl_svl = pSvlan_cfg->ivl_svl; + vlan4kEntry.fid_msti = pSvlan_cfg->fid; + + if ((retVal = _dal_rtl8373_setAsicVlan4kEntry(&vlan4kEntry)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_svlanmemberPortEntry_get + * Description: + * Get SVLAN member Configure. + * Input: + * svid - SVLAN id + * Output: + * pSvlan_cfg - SVLAN member configuration + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get system 64 accepted s-tag frame format. Only 64 SVID S-tag frame will be accpeted + * to receiving from uplink ports. Other SVID S-tag frame or S-untagged frame will be droped. + */ +rtk_api_ret_t dal_rtl8373_svlanMbrPortEntry_get(rtk_vlan_t svid, rtk_svlan_memberCfg_t *pSvlan_cfg) +{ + rtk_api_ret_t retVal = 0; + dal_rtl8373_user_vlan4kentry vlan4kEntry; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pSvlan_cfg) + return RT_ERR_NULL_POINTER; + + if (svid > RTL8373_VIDMAX) + return RT_ERR_SVLAN_VID; + + memset(&vlan4kEntry, 0, sizeof(dal_rtl8373_user_vlan4kentry)); + vlan4kEntry.vid = svid; + if ((retVal = _dal_rtl8373_getAsicVlan4kEntry(&vlan4kEntry)) != RT_ERR_OK) + return retVal; + + memset(pSvlan_cfg, 0, sizeof(rtk_svlan_memberCfg_t)); + pSvlan_cfg->svid = vlan4kEntry.vid; + if(rtk_switch_portmask_P2L_get(vlan4kEntry.mbr,&(pSvlan_cfg->memberport)) != RT_ERR_OK) + return RT_ERR_FAILED; + if(rtk_switch_portmask_P2L_get(vlan4kEntry.untag,&(pSvlan_cfg->untagport)) != RT_ERR_OK) + return RT_ERR_FAILED; + pSvlan_cfg->chk_ivl_svl = vlan4kEntry.svlan_chk_ivl_svl; + pSvlan_cfg->ivl_svl = vlan4kEntry.ivl_svl; + pSvlan_cfg->fid = vlan4kEntry.fid_msti; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_svlanDftSvlan_set + * Description: + * Configure default egress SVLAN. + * Input: + * port - Source port + * svid - SVLAN id + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found. + * Note: + * The API can set port n S-tag format index while receiving frame from port n + * is transmit through uplink port with s-tag field + */ +rtk_api_ret_t dal_rtl8373_svlanDfltSvlan_set(rtk_port_t port, rtk_vlan_t svid) +{ + rtk_api_ret_t retVal = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check port Valid */ + RTK_CHK_PORT_VALID(port); + + /* svid must be 0~4095 */ + if (svid > RTL8373_VIDMAX) + return RT_ERR_SVLAN_VID; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_VS_PORT_DFLT_SVID_ADDR(port), RTL8373_VS_PORT_DFLT_SVID_PORT_DFLT_SVID_MASK(port) , svid)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_svlanDfltSvlan_get + * Description: + * Get the configure default egress SVLAN. + * Input: + * port - Source port + * Output: + * pSvid - SVLAN VID + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get port n S-tag format index while receiving frame from port n + * is transmit through uplink port with s-tag field + */ +rtk_api_ret_t dal_rtl8373_svlanDfltSvlan_get(rtk_port_t port, rtk_vlan_t *pSvid) +{ + rtk_api_ret_t retVal = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pSvid) + return RT_ERR_NULL_POINTER; + + /* Check port Valid */ + RTK_CHK_PORT_VALID(port); + + if ((retVal = rtl8373_getAsicRegBits(RTL8373_VS_PORT_DFLT_SVID_ADDR(port), RTL8373_VS_PORT_DFLT_SVID_PORT_DFLT_SVID_MASK(port), pSvid)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_svlanC2S_add + * Description: + * Configure SVLAN C2S table + * Input: + * vid - VLAN ID + * srcPort - Ingress Port + * svid - SVLAN VID + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port ID. + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can set system C2S configuration. ASIC will check upstream's VID and assign related + * SVID to mathed packet. There are 128 SVLAN C2S configurations. + */ +rtk_api_ret_t dal_rtl8373_svlanC2S_add(rtk_vlan_t vid, rtk_port_t srcPort, rtk_vlan_t svid) +{ + rtk_api_ret_t retVal = 0, i = 0; + rtk_uint32 empty_idx = 0; + rtk_port_t phyPort; + rtk_uint16 doneFlag = 0; + rtk_uint32 idx_svid = 0, idx_pmsk = 0, idx_cvid = 0; + + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + + if (vid > RTL8373_VIDMAX) + return RT_ERR_VLAN_VID; + + if (svid > RTL8373_VIDMAX) + return RT_ERR_SVLAN_VID; + + /* Check port Valid */ + RTK_CHK_PORT_VALID(srcPort); + + phyPort = rtk_switch_port_L2P_get(srcPort); + empty_idx = 0xFFFF; + doneFlag = FALSE; + + for (i = RTL8373_C2SIDXMAX; i>=0; i--) + { + if ((retVal = rtl8373_getAsicRegBits(RTL8373_VLAN_C2S_ENTRY_ADDR(i) , RTL8373_VLAN_C2S_ENTRY_SVID_ASSIGN_MASK, &idx_svid)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_getAsicRegBits(RTL8373_VLAN_C2S_ENTRY_ADDR(i) + 4, RTK_MAX_PORT_MASK, &idx_pmsk)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_getAsicRegBits(RTL8373_VLAN_C2S_ENTRY_ADDR(i) + 4, (0xFFF << RTK_MAX_NUM_OF_PORT), &idx_cvid)) != RT_ERR_OK) + return retVal; + + + if (idx_cvid == vid) + { + /* Check Src_port */ + if(idx_pmsk & (1 << phyPort)) + { + /* Check SVIDX */ + if(idx_svid == svid) + { + /* All the same, do nothing */ + } + else + { + /* New svidx, remove src_port and find a new slot to add a new enrty */ + idx_pmsk = idx_pmsk & ~(1 << phyPort); + if(idx_pmsk == 0) + idx_svid = 0; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_VLAN_C2S_ENTRY_ADDR(i) , RTL8373_VLAN_C2S_ENTRY_SVID_ASSIGN_MASK, idx_svid)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_VLAN_C2S_ENTRY_ADDR(i) + 4, RTK_MAX_PORT_MASK, idx_pmsk)) != RT_ERR_OK) + return retVal; + } + } + else + { + if(idx_svid == svid && doneFlag == FALSE) + { + idx_pmsk = idx_pmsk | (1 << phyPort); + if ((retVal = rtl8373_setAsicRegBits(RTL8373_VLAN_C2S_ENTRY_ADDR(i) + 4, RTK_MAX_PORT_MASK, idx_pmsk)) != RT_ERR_OK) + return retVal; + + doneFlag = TRUE; + } + } + } + else if (idx_svid==0&&idx_pmsk==0) + { + empty_idx = i; + } + } + + if (0xFFFF != empty_idx && doneFlag ==FALSE) + { + if ((retVal = rtl8373_setAsicRegBits(RTL8373_VLAN_C2S_ENTRY_ADDR(empty_idx) , RTL8373_VLAN_C2S_ENTRY_SVID_ASSIGN_MASK, svid)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_VLAN_C2S_ENTRY_ADDR(empty_idx) + 4, RTK_MAX_PORT_MASK, (1< RTL8373_VIDMAX) + return RT_ERR_VLAN_VID; + + /* Check port Valid */ + RTK_CHK_PORT_VALID(srcPort); + phyPort = rtk_switch_port_L2P_get(srcPort); + + for (i = 0; i <= RTL8373_C2SIDXMAX; i++) + { + if ((retVal = rtl8373_getAsicRegBits(RTL8373_VLAN_C2S_ENTRY_ADDR(i) , RTL8373_VLAN_C2S_ENTRY_SVID_ASSIGN_MASK, &idx_svid)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_getAsicRegBits(RTL8373_VLAN_C2S_ENTRY_ADDR(i) + 4, RTK_MAX_PORT_MASK, &idx_pmsk)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_getAsicRegBits(RTL8373_VLAN_C2S_ENTRY_ADDR(i) + 4, (0xFFF << RTK_MAX_NUM_OF_PORT), &idx_cvid)) != RT_ERR_OK) + return retVal; + + if (idx_cvid == vid) + { + if(idx_pmsk & (1 << phyPort)) + { + idx_pmsk = idx_pmsk & ~(1 << phyPort); + if(idx_pmsk == 0) + { + idx_cvid = 0; + idx_svid = 0; + } + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_VLAN_C2S_ENTRY_ADDR(i) , RTL8373_VLAN_C2S_ENTRY_SVID_ASSIGN_MASK, idx_svid)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_VLAN_C2S_ENTRY_ADDR(i) + 4, RTK_MAX_PORT_MASK, idx_pmsk)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_VLAN_C2S_ENTRY_ADDR(i) + 4, (0xFFF << RTK_MAX_NUM_OF_PORT), idx_cvid)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; + } + } + } + + return RT_ERR_OUT_OF_RANGE; +} + +/* Function Name: + * dal_rtl8373_svlanC2S_get + * Description: + * Get configure SVLAN C2S table + * Input: + * vid - VLAN ID + * srcPort - Ingress Port + * Output: + * pSvid - SVLAN ID + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port ID. + * RT_ERR_OUT_OF_RANGE - input out of range. + * Note: + * The API can get system C2S configuration. There are 128 SVLAN C2S configurations. + */ +rtk_api_ret_t dal_rtl8373_svlanC2S_get(rtk_vlan_t vid, rtk_port_t srcPort, rtk_vlan_t *pSvid) +{ + rtk_api_ret_t retVal = 0; + rtk_uint32 i = 0; + rtk_uint32 idx_svid, idx_pmsk, idx_cvid; + rtk_port_t phyPort; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pSvid) + return RT_ERR_NULL_POINTER; + + if (vid > RTL8373_VIDMAX) + return RT_ERR_VLAN_VID; + + /* Check port Valid */ + RTK_CHK_PORT_VALID(srcPort); + phyPort = rtk_switch_port_L2P_get(srcPort); + + for (i = 0; i <= RTL8373_C2SIDXMAX; i++) + { + if ((retVal = rtl8373_getAsicRegBits(RTL8373_VLAN_C2S_ENTRY_ADDR(i) , RTL8373_VLAN_C2S_ENTRY_SVID_ASSIGN_MASK, &idx_svid)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_getAsicRegBits(RTL8373_VLAN_C2S_ENTRY_ADDR(i) + 4, RTK_MAX_PORT_MASK, &idx_pmsk)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_getAsicRegBits(RTL8373_VLAN_C2S_ENTRY_ADDR(i) + 4, (0xFFF << RTK_MAX_NUM_OF_PORT), &idx_cvid)) != RT_ERR_OK) + return retVal; + + if (idx_cvid == vid) + { + if(idx_pmsk & (1 << phyPort)) + { + *pSvid = idx_svid; + return RT_ERR_OK; + } + } + } + + return RT_ERR_OUT_OF_RANGE; +} + +/* Function Name: + * dal_rtl8373_svlanUntagAction_set + * Description: + * Configure Action of downstream Un-Stag packet + * Input: + * action - Action for UnStag + * svid - The SVID assigned to UnStag packet + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found. + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can configure action of downstream Un-Stag packet. A SVID assigned + * to the un-stag is also supported by this API. The parameter of svid is + * only referenced when the action is set to UNTAG_ASSIGN + */ +rtk_api_ret_t dal_rtl8373_svlanUntagAction_set(rtk_svlan_untag_action_t action, rtk_vlan_t svid) +{ + rtk_api_ret_t retVal = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (action >= UNTAG_END) + return RT_ERR_OUT_OF_RANGE; + + if(action == UNTAG_ASSIGN) + { + if (svid > RTL8373_VIDMAX) + return RT_ERR_SVLAN_VID; + } + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_VS_CTRL_ADDR, RTL8373_VS_CTRL_UNTAG_MASK, action)) != RT_ERR_OK) + return retVal; + + if(action == UNTAG_ASSIGN) + { + if ((retVal = rtl8373_setAsicRegBits(RTL8373_VS_UNTAG_SVID_ADDR, RTL8373_VS_UNTAG_SVID_UNTAG_SVID_MASK, svid)) != RT_ERR_OK) + return retVal; + } + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_svlanUntagAction_get + * Description: + * Get Action of downstream Un-Stag packet + * Input: + * None + * Output: + * pAction - Action for UnStag + * pSvid - The SVID assigned to UnStag packet + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found. + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can Get action of downstream Un-Stag packet. A SVID assigned + * to the un-stag is also retrieved by this API. The parameter pSvid is + * only refernced when the action is UNTAG_ASSIGN + */ +rtk_api_ret_t dal_rtl8373_svlanUntagAction_get(rtk_svlan_untag_action_t *pAction, rtk_vlan_t *pSvid) +{ + rtk_api_ret_t retVal = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pAction || NULL == pSvid) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8373_getAsicRegBits(RTL8373_VS_CTRL_ADDR, RTL8373_VS_CTRL_UNTAG_MASK, pAction)) != RT_ERR_OK) + return retVal; + + if(*pAction == UNTAG_ASSIGN) + { + if ((retVal = rtl8373_getAsicRegBits(RTL8373_VS_UNTAG_SVID_ADDR, RTL8373_VS_UNTAG_SVID_UNTAG_SVID_MASK, pSvid)) != RT_ERR_OK) + return retVal; + } + + return RT_ERR_OK; +} + + + +/* Function Name: + * dal_rtl8373_svlanUnassignAction_set + * Description: + * Configure Action of upstream without svid assign action + * Input: + * action - Action for Un-assign + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can configure action of upstream Un-assign svid packet. If action is not + * trap to CPU, the port-based SVID sure be assign as system need + */ +rtk_api_ret_t dal_rtl8373_svlanUnassignAction_set(rtk_svlan_unassign_action_t action) +{ + rtk_api_ret_t retVal = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (action >= UNASSIGN_END) + return RT_ERR_OUT_OF_RANGE; + + retVal = rtl8373_setAsicRegBit(RTL8373_VS_CTRL_ADDR, RTL8373_VS_CTRL_UIFSEG_OFFSET, action); + + return retVal; +} + +/* Function Name: + * dal_rtl8373_svlanUnassignAction_get + * Description: + * Get action of upstream without svid assignment + * Input: + * None + * Output: + * pAction - Action for Un-assign + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * Note: + * None + */ +rtk_api_ret_t dal_rtl8373_svlanUnassignAction_get(rtk_svlan_unassign_action_t *pAction) +{ + rtk_api_ret_t retVal = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pAction) + return RT_ERR_NULL_POINTER; + + retVal = rtl8373_getAsicRegBit(RTL8373_VS_CTRL_ADDR, RTL8373_VS_CTRL_UIFSEG_OFFSET, pAction); + + return retVal; +} + +/* Function Name: + * dal_rtl8373_svlanTrapPri_set + * Description: + * Set svlan trap priority + * Input: + * priority - priority for trap packets + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_QOS_INT_PRIORITY + * Note: + * None + */ +rtk_api_ret_t dal_rtl8373_svlanTrapPri_set(rtk_pri_t priority) +{ + rtk_api_ret_t retVal = 0; + + RTK_CHK_INIT_STATE(); + + if(priority > RTL8373_PRIMAX) + return RT_ERR_OUT_OF_RANGE; + + retVal = rtl8373_setAsicRegBits(RTL8373_SVLAN_TRAP_CTRL_ADDR, RTL8373_SVLAN_TRAP_CTRL_PRI_MASK, priority); + + return retVal; +} + +/* Function Name: + * dal_rtl8373_svlanTrapPri_get + * Description: + * Get svlan trap priority + * Input: + * None + * Output: + * pPriority - priority for trap packets + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None + */ +rtk_api_ret_t dal_rtl8373_svlanTrapPri_get(rtk_pri_t *pPriority) +{ + rtk_api_ret_t retVal = 0; + + RTK_CHK_INIT_STATE(); + + if(NULL == pPriority) + return RT_ERR_NULL_POINTER; + + retVal = rtl8373_getAsicRegBits(RTL8373_SVLAN_TRAP_CTRL_ADDR, RTL8373_SVLAN_TRAP_CTRL_PRI_MASK, pPriority); + + return retVal; +} /* end of rtk_svlan_trapPri_get */ + +/* Function Name: + * dal_rtl8373_svlanTrapCpumsk_set + * Description: + * Set svlan trap cpu mask + * Input: + * mask - cpu mask; bit0: internal cpu; bit1: external cpu + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_QOS_INT_PRIORITY + * Note: + * None + */ +rtk_api_ret_t dal_rtl8373_svlanTrapCpumsk_set(rtk_pri_t mask) +{ + rtk_api_ret_t retVal = 0; + + RTK_CHK_INIT_STATE(); + + if(mask > RTL8373_PRIMAX) + return RT_ERR_OUT_OF_RANGE; + + retVal = rtl8373_setAsicRegBits(RTL8373_SVLAN_TRAP_CTRL_ADDR, RTL8373_SVLAN_TRAP_CTRL_CPU_PMSK_MASK, mask); + + return retVal; +} + +/* Function Name: + * dal_rtl8373_svlanTrapCpumsk_get + * Description: + * Get svlan trap cpu mask + * Input: + * None + * Output: + * pMask - traped cpu mask + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None + */ +rtk_api_ret_t dal_rtl8373_svlanTrapCpumsk_get(rtk_pri_t *pMask) +{ + rtk_api_ret_t retVal = 0; + + RTK_CHK_INIT_STATE(); + + if(NULL == pMask) + return RT_ERR_NULL_POINTER; + + retVal = rtl8373_getAsicRegBits(RTL8373_SVLAN_TRAP_CTRL_ADDR, RTL8373_SVLAN_TRAP_CTRL_CPU_PMSK_MASK, pMask); + + return retVal; +} + diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_svlan.h b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_svlan.h new file mode 100755 index 00000000..e94c0f22 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_svlan.h @@ -0,0 +1,490 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose :RTL8373 switch high-level API + * + * Feature : The file includes SVLAN module high-layer API defination + * + */ + +#ifndef __DAL_RTL8373_SVLAN_H__ +#define __DAL_RTL8373_SVLAN_H__ + +#include +#include +#include + + +/* Function Name: + * dal_rtl8373_svlanInit + * Description: + * Initialize SVLAN Configuration + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * Ether type of S-tag in 802.1ad is 0x88a8 and there are existed ether type 0x9100 and 0x9200 for Q-in-Q SLAN design. + * User can set mathced ether type as service provider supported protocol. + */ +extern rtk_api_ret_t dal_rtl8373_svlanInit(void); + +/* Function Name: + * dal_rtl8373_svlanServicePort_add + * Description: + * Add one service port in the specified device + * Input: + * port - Port id. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API is setting which port is connected to provider switch. All frames receiving from this port must + * contain accept SVID in S-tag field. + */ +extern rtk_api_ret_t dal_rtl8373_svlanServicePort_add(rtk_port_t port); + +/* Function Name: + * dal_rtl8373_svlanServicePort_get + * Description: + * Get service ports in the specified device. + * Input: + * None + * Output: + * pSvlanPmsk - pointer buffer of svlan ports. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API is setting which port is connected to provider switch. All frames receiving from this port must + * contain accept SVID in S-tag field. + */ +extern rtk_api_ret_t dal_rtl8373_svlanServicePort_get(rtk_portmask_t *pSvlanPmsk); + +/* Function Name: + * dal_rtl8373_svlanservicePort_del + * Description: + * Delete one service port in the specified device + * Input: + * port - Port id. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API is removing SVLAN service port in the specified device. + */ +extern rtk_api_ret_t dal_rtl8373_svlanServicePort_del(rtk_port_t port); + +/* Function Name: + * dal_rtl8373_svlanTpid_set + * Description: + * Configure accepted S-VLAN ether type. + * Input: + * svlanTpid - Ether type of S-tag frame parsing in uplink ports. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * Note: + * Ether type of S-tag in 802.1ad is 0x88a8 and there are existed ether type 0x9100 and 0x9200 for Q-in-Q SLAN design. + * User can set mathced ether type as service provider supported protocol. + */ +extern rtk_api_ret_t dal_rtl8373_svlanTpid_set(rtk_uint32 svlanTpid); + +/* Function Name: + * dal_rtl8373_svlanTpid_get + * Description: + * Get accepted S-VLAN ether type setting. + * Input: + * None + * Output: + * pSvlanTpid - Ether type of S-tag frame parsing in uplink ports. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API is setting which port is connected to provider switch. All frames receiving from this port must + * contain accept SVID in S-tag field. + */ +extern rtk_api_ret_t dal_rtl8373_svlanTpid_get(rtk_uint32 *pSvlanTpid); + +/* Function Name: + * dal_rtl8373_svlanPriRef_set + * Description: + * Set S-VLAN upstream priority reference setting. + * Input: + * ref - reference selection parameter. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * Note: + * The API can set the upstream SVLAN tag priority reference source. The related priority + * sources are as following: + * - REF_INTERNAL_PRI, + * - REF_CTAG_PRI, + * - REF_SVLAN_PRI, + * - REF_PB_PRI. + */ +extern rtk_api_ret_t dal_rtl8373_svlanPriRef_set(rtk_svlan_pri_ref_t ref); + +/* Function Name: + * dal_rtl8373_svlanPriRef_get + * Description: + * Get S-VLAN upstream priority reference setting. + * Input: + * None + * Output: + * pRef - reference selection parameter. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can get the upstream SVLAN tag priority reference source. The related priority + * sources are as following: + * - REF_INTERNAL_PRI, + * - REF_CTAG_PRI, + * - REF_SVLAN_PRI, + * - REF_PB_PRI + */ +extern rtk_api_ret_t dal_rtl8373_svlanPriRef_get(rtk_svlan_pri_ref_t *pRef); + +/* Function Name: + * dal_rtl8373_svlanmemberPortEntry_set + * Description: + * Configure system SVLAN member content + * Input: + * svid - SVLAN id + * psvlan_cfg - SVLAN member configuration + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_PORT_MASK - Invalid portmask. + * RT_ERR_SVLAN_TABLE_FULL - SVLAN configuration is full. + * Note: + * The API can set system 64 accepted s-tag frame format. Only 64 SVID S-tag frame will be accpeted + * to receiving from uplink ports. Other SVID S-tag frame or S-untagged frame will be droped by default setup. + * - rtk_svlan_memberCfg_t->svid is SVID of SVLAN member configuration. + * - rtk_svlan_memberCfg_t->memberport is member port mask of SVLAN member configuration. + * - rtk_svlan_memberCfg_t->fid is filtering database of SVLAN member configuration. + * - rtk_svlan_memberCfg_t->priority is priority of SVLAN member configuration. + */ +extern rtk_api_ret_t dal_rtl8373_svlanMbrPortEntry_set(rtk_vlan_t svid, rtk_svlan_memberCfg_t *pSvlan_cfg); + +/* Function Name: + * dal_rtl8373_svlanmemberPortEntry_get + * Description: + * Get SVLAN member Configure. + * Input: + * svid - SVLAN id + * Output: + * pSvlan_cfg - SVLAN member configuration + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get system 64 accepted s-tag frame format. Only 64 SVID S-tag frame will be accpeted + * to receiving from uplink ports. Other SVID S-tag frame or S-untagged frame will be droped. + */ +extern rtk_api_ret_t dal_rtl8373_svlanMbrPortEntry_get(rtk_vlan_t svid, rtk_svlan_memberCfg_t *pSvlan_cfg); + +/* Function Name: + * dal_rtl8373_svlanDftSvlan_set + * Description: + * Configure default egress SVLAN. + * Input: + * port - Source port + * svid - SVLAN id + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found. + * Note: + * The API can set port n S-tag format index while receiving frame from port n + * is transmit through uplink port with s-tag field + */ +extern rtk_api_ret_t dal_rtl8373_svlanDfltSvlan_set(rtk_port_t port, rtk_vlan_t svid); + +/* Function Name: + * dal_rtl8373_svlanDfltSvlan_get + * Description: + * Get the configure default egress SVLAN. + * Input: + * port - Source port + * Output: + * pSvid - SVLAN VID + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get port n S-tag format index while receiving frame from port n + * is transmit through uplink port with s-tag field + */ +extern rtk_api_ret_t dal_rtl8373_svlanDfltSvlan_get(rtk_port_t port, rtk_vlan_t *pSvid); + +/* Function Name: + * dal_rtl8373_svlanC2S_add + * Description: + * Configure SVLAN C2S table + * Input: + * vid - VLAN ID + * srcPort - Ingress Port + * svid - SVLAN VID + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port ID. + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can set system C2S configuration. ASIC will check upstream's VID and assign related + * SVID to mathed packet. There are 128 SVLAN C2S configurations. + */ +extern rtk_api_ret_t dal_rtl8373_svlanC2S_add(rtk_vlan_t vid, rtk_port_t srcPort, rtk_vlan_t svid); + +/* Function Name: + * dal_rtl8373_svlanC2S_del + * Description: + * Delete one C2S entry + * Input: + * vid - VLAN ID + * srcPort - Ingress Port + * svid - SVLAN VID + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_VLAN_VID - Invalid VID parameter. + * RT_ERR_PORT_ID - Invalid port ID. + * RT_ERR_OUT_OF_RANGE - input out of range. + * Note: + * The API can delete system C2S configuration. There are 128 SVLAN C2S configurations. + */ +extern rtk_api_ret_t dal_rtl8373_svlanC2S_del(rtk_vlan_t vid, rtk_port_t srcPort); + +/* Function Name: + * dal_rtl8373_svlanC2S_get + * Description: + * Get configure SVLAN C2S table + * Input: + * vid - VLAN ID + * srcPort - Ingress Port + * Output: + * pSvid - SVLAN ID + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port ID. + * RT_ERR_OUT_OF_RANGE - input out of range. + * Note: + * The API can get system C2S configuration. There are 128 SVLAN C2S configurations. + */ +extern rtk_api_ret_t dal_rtl8373_svlanC2S_get(rtk_vlan_t vid, rtk_port_t srcPort, rtk_vlan_t *pSvid); + +/* Function Name: + * dal_rtl8373_svlanUntagAction_set + * Description: + * Configure Action of downstream Un-Stag packet + * Input: + * action - Action for UnStag + * svid - The SVID assigned to UnStag packet + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found. + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can configure action of downstream Un-Stag packet. A SVID assigned + * to the un-stag is also supported by this API. The parameter of svid is + * only referenced when the action is set to UNTAG_ASSIGN + */ +extern rtk_api_ret_t dal_rtl8373_svlanUntagAction_set(rtk_svlan_untag_action_t action, rtk_vlan_t svid); + +/* Function Name: + * dal_rtl8373_svlanUntagAction_get + * Description: + * Get Action of downstream Un-Stag packet + * Input: + * None + * Output: + * pAction - Action for UnStag + * pSvid - The SVID assigned to UnStag packet + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found. + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can Get action of downstream Un-Stag packet. A SVID assigned + * to the un-stag is also retrieved by this API. The parameter pSvid is + * only refernced when the action is UNTAG_ASSIGN + */ +extern rtk_api_ret_t dal_rtl8373_svlanUntagAction_get(rtk_svlan_untag_action_t *pAction, rtk_vlan_t *pSvid); + +/* Function Name: + * dal_rtl8373_svlanUnassignAction_set + * Description: + * Configure Action of upstream without svid assign action + * Input: + * action - Action for Un-assign + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can configure action of upstream Un-assign svid packet. If action is not + * trap to CPU, the port-based SVID sure be assign as system need + */ +extern rtk_api_ret_t dal_rtl8373_svlanUnassignAction_set(rtk_svlan_unassign_action_t action); + +/* Function Name: + * dal_rtl8373_svlanUnassignAction_get + * Description: + * Get action of upstream without svid assignment + * Input: + * None + * Output: + * pAction - Action for Un-assign + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * Note: + * None + */ +extern rtk_api_ret_t dal_rtl8373_svlanUnassignAction_get(rtk_svlan_unassign_action_t *pAction); + +/* Function Name: + * dal_rtl8373_svlanTrapPri_set + * Description: + * Set svlan trap priority + * Input: + * priority - priority for trap packets + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_QOS_INT_PRIORITY + * Note: + * None + */ +extern rtk_api_ret_t dal_rtl8373_svlanTrapPri_set(rtk_pri_t priority); + +/* Function Name: + * dal_rtl8373_svlanTrapPri_get + * Description: + * Get svlan trap priority + * Input: + * None + * Output: + * pPriority - priority for trap packets + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None + */ +extern rtk_api_ret_t dal_rtl8373_svlanTrapPri_get(rtk_pri_t *pPriority); + +/* Function Name: + * dal_rtl8373_svlanTrapCpumsk_set + * Description: + * Set svlan trap cpu mask + * Input: + * mask - cpu mask; bit0: internal cpu; bit1: external cpu + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_QOS_INT_PRIORITY + * Note: + * None + */ +extern rtk_api_ret_t dal_rtl8373_svlanTrapCpumsk_set(rtk_pri_t mask); + +/* Function Name: + * dal_rtl8373_svlanTrapCpumsk_get + * Description: + * Get svlan trap cpu mask + * Input: + * None + * Output: + * pMask - traped cpu mask + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None + */ +extern rtk_api_ret_t dal_rtl8373_svlanTrapCpumsk_get(rtk_pri_t *pMask); + + +#endif /* __DAL_RTL8373_SVLAN_H__ */ diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_switch.c b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_switch.c new file mode 100755 index 00000000..cd4b7583 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_switch.c @@ -0,0 +1,3116 @@ + /* + * Copyright (C) 2012 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : Definition of Switch Global API + * + * Feature : The file have include the following module and sub-modules + * (1) Switch parameter settings + * + */ + + + /* + * Include Files + */ +#include +#include +#include +#include +#include +/* +#include "ssdk_plat.h" + +#include "chip.h" +#include "sw.h" +#include "fal_port_ctrl.h" +#include "hsl_api.h" +#include "hsl.h" +#include "hsl_phy.h" +#include "ssdk_plat.h" +#include "qca808x_phy.h" +#include "eee.h" + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +*/ + + /* + * Symbol Definition + */ +#ifndef ENABLE +#define ENABLE 1 +#endif + +#ifndef DISABLE +#define DISABLE 0 +#endif + +#define PHY_PATCH 1 +#define SDS_FIBER_FC_EN (1) +#define SDS_NWAY_EN (1) + + + + /* + * Data Declaration + */ + rtk_uint32 currentVersion, FWVersion; + rtk_uint32 Ver8373_72 = 0xf; + rtk_uint32 Ver8224 = 0xf; + rtk_uint32 Ver8366U = 0xf; + rtk_uint32 Ver8372N = 0xf; + rtk_uint32 Ver8373N = 0xf; + rtk_uint32 Ver8224N = 0xf; + + chip_mode_type_t CHIP_TYPE; + + + rtk_uint16 an_10p3125g_chipa[][3] ={ + {0x21 ,0x10, 0x4480}, {0x21, 0x13 ,0x0400}, {0x21, 0x18, 0x6d02}, {0x21 ,0x1b,0x424e} , + {0x21, 0x1d, 0x0002}, {0x36, 0x1c ,0x1390} ,{0x2e ,0x4 ,0x0080} ,{0x2e ,0x6 ,0x0408} , + {0x2e, 0x7, 0x020d}, {0x2e, 0x9 ,0x0601}, {0x2e ,0xb, 0x222c}, {0x2e, 0xc, 0x9217} , + {0x2e ,0x16, 0x0743}, {0x2e, 0x1d ,0xabb0} + }; + + rtk_uint16 an_10p3125g_chipb[][3] ={ + {0x21 ,0x10, 0x4480}, {0x21, 0x13 ,0x0400}, {0x21, 0x18, 0x6d02}, {0x21 ,0x1b,0x424e} , + {0x21, 0x1d, 0x0002}, {0x36, 0x1c ,0x1390} ,{0x36 ,0x14 ,0x003f} ,{0x36 ,0x10,0x0200} , + {0x2e, 0x4, 0x0080}, {0x2e, 0x6 ,0x0408}, {0x2e ,0x7, 0x020d}, {0x2e, 0x9, 0x0601} , + {0x2e ,0xb, 0x222c}, {0x2e, 0x0c ,0xa217}, {0x2e, 0x0d, 0xfe40},{0x2e, 0x15, 0xf5c1}, + {0x2e, 0x16, 0x0443}, {0x2e, 0x1d, 0xabb0} + }; + + + + rtk_uint16 an_3p125g_chipa[][3]= { + {0x21, 0x10, 0x6480}, {0x21, 0x13 ,0x400 }, {0x21, 0x18 ,0x6d02}, {0x21 ,0x1b ,0x424e}, + {0x21 ,0x1d ,0x2 } ,{0x36 ,0x1c ,0x1390}, {0x28, 0x4 ,0x0080}, {0x28, 0x9 ,0x601 }, + {0x28 ,0xb , 0x232c} ,{0x28, 0xc, 0x9217} ,{0x28 ,0xf, 0x5b50}, {0x28, 0x16, 0x443 }, + {0x28, 0x1d, 0xabb0} + }; + + rtk_uint16 an_3p125g_chipb[][3]= { + {0x21, 0x10, 0x6480}, {0x21, 0x13 ,0x400 }, {0x21, 0x18 ,0x6d02}, {0x21 ,0x1b ,0x424e}, + {0x21 ,0x1d ,0x2 }, {0x36 ,0x1c ,0x1390}, {0x36, 0x14, 0x003F}, {0x36, 0x10, 0x0200}, + {0x28, 0x4 ,0x0080}, {0x28, 0x7, 0x1201}, {0x28, 0x9 ,0x601 }, {0x28 ,0xb , 0x232c} , + {0x28, 0xc, 0x9217}, {0x28 ,0xf, 0x5b50}, {0x28, 0x15, 0xe7f1}, {0x28, 0x16, 0x443 }, + {0x28, 0x1d, 0xabb0} + }; + + rtk_uint16 an_1p25g_chipa[][3]= { + {0x21, 0x10, 0x6480}, {0x21 ,0x13 ,0x0400}, {0x21 ,0x18 ,0x6d02}, {0x21, 0x1b ,0x424e}, + {0x21, 0x1d, 0x0002}, {0x36 ,0x1c, 0x1390} ,{0x36, 0x14, 0x003F}, {0x36, 0x10, 0x0300}, + {0x24 ,0x04 ,0x0080}, {0x24, 0x7, 0x1201}, {0x24 ,0x09, 0x0601}, {0x24 ,0x0b, 0x232c}, + {0x24, 0x0c ,0x9217}, {0x24 ,0x0f ,0x5B50} ,{0x24, 0x15, 0xe7c1}, {0x24 ,0x16, 0x0443}, + {0x24, 0x1d ,0xabb0} + }; + + rtk_uint16 an_1p25g_chipb[][3]= { + {0x21, 0x10, 0x6480}, {0x21, 0x13, 0x0400}, {0x21, 0x18, 0x6d02}, + {0x21, 0x1b, 0x424e}, {0x21, 0x1d, 0x0002}, {0x36, 0x1c, 0x1390}, {0x36, 0x14, 0x003F}, + {0x36, 0x10, 0x0300}, {0x24, 0x04, 0x0080}, {0x24, 0x07, 0x1201}, {0x24, 0x09, 0x0601}, + {0x24, 0x0b, 0x232c}, {0x24, 0x0c, 0x9217}, {0x24, 0x0f, 0x5b50}, {0x24, 0x15, 0xe7C1}, + {0x24, 0x16, 0x0443}, {0x24, 0x1d, 0xabb0} +}; + + rtk_uint16 an_125m_chipa[][3]= { + {0x21, 0x10, 0x6480}, {0x21, 0x13, 0x0400}, {0x21, 0x18, 0x6d02}, {0x21, 0x1b, 0x424e}, + {0x21, 0x1d, 0x0002}, {0x36, 0x1c, 0x1390}, {0x26, 0x04, 0x0080}, {0x26, 0x09, 0x0601}, + {0x26, 0x0b, 0x232c}, {0x26, 0x0c, 0x9217}, {0x26, 0x0f, 0x5B50}, {0x26, 0x16, 0x0443}, + {0x26, 0x1d, 0xabb0} + }; + + rtk_uint16 an_125m_chipb[][3]= { + {0x21, 0x10, 0x6480}, {0x21, 0x13, 0x0400}, {0x21, 0x18, 0x6d02}, + {0x21, 0x1b, 0x424e}, {0x21, 0x1d, 0x0002}, {0x36, 0x1c, 0x1390}, {0x36, 0x14, 0x003F}, + {0x36, 0x10, 0x0300}, {0x26, 0x04, 0x0080}, {0x26, 0x07, 0x1201}, {0x26, 0x09, 0x0601}, + {0x26, 0x0b, 0x232c}, {0x26, 0x0c, 0x9217}, {0x26, 0x0f, 0x5b50}, {0x26, 0x15, 0xe7C1}, + {0x26, 0x16, 0x0443}, {0x26, 0x1d, 0xabb0} + + }; + + + + rtk_uint16 dig_patch_mac[][3]= { + {6 , 18 ,0x5078}, {7, 6 ,0x9401}, {7 , 8 , 0x9401}, {7 ,10 ,0x9401}, + {7 , 12 ,0x9401}, {31 ,11 ,0x0003}, {6, 3, 0xc45c}, {6, 31, 0x2100} + }; + rtk_uint16 dig_patch_phy[][3]= { + {6, 18 ,0x5078}, {6, 3, 0xc45c}, {6, 30, 0x000C}, {6, 31, 0x2100} + }; + + + rtk_uint16 patch_list[][2]= + { + {0xC202, 0xC1} , + {0xC203, 0x01}, + {0xC204, 0xFF} , + {0xC205, 0x02}, + {0xC206, 0x6A}, + {0xC207, 0x02} , + {0xC208, 0xD9} , + {0xC209, 0x03} , + {0xC20A, 0x5C} , + {0xC20B, 0x03} , + {0xC20C, 0xF6}, + {0xC20D, 0x04} , + {0xC20E, 0x88}, + {0xC20F, 0x05} , + {0xC210, 0x40}, + {0xC211, 0x06} , + {0xC212, 0x3D}, + {0xC213, 0x07} , + {0xC214, 0x24}, + {0xC215, 0x08} , + {0xC216, 0x2B}, + {0xC217, 0x09} , + {0xC218, 0x84}, + {0xC219, 0x0B} , + {0xC21A, 0x41}, + {0xC21B, 0x0C} , + {0xC21C, 0x44}, + {0xC21D, 0x0E} , + {0xC21E, 0x00}, + {0xC21F, 0xF6} , + {0xC220, 0xF6}, + {0xC221, 0xF5}, + {0xC222, 0xF3}, + {0xC223, 0xF3}, + {0xC224, 0xEF}, + {0xC225, 0xEB}, + {0xC226, 0xE7}, + {0xC227, 0xE4}, + {0xC228, 0xE2}, + {0xC229, 0xDF}, + {0xC22A, 0xDD}, + {0xC22B, 0xDB}, + {0xC22C, 0xDA}, + {0xC22D, 0xD9}, + {0xC270, 0x18}, + {0xC271, 0x19}, + {0xC272, 0x1C}, + {0xC273, 0x1E}, + {0xC274, 0x20}, + {0xC275, 0x21}, + {0xC276, 0x22}, + {0xC277, 0x23}, + {0xC278, 0x23}, + {0xC279, 0x24}, + {0xC27A, 0x25}, + {0xC27B, 0x25}, + {0xC27C, 0x26}, + {0xC27D, 0x26}, + {0xC27E, 0x26}, + {0xC27F, 0x4A}, + {0xC280, 0x4A}, + {0xC281, 0x4A}, + {0xC282, 0x4D}, + {0xC283, 0x4D}, + {0xC284, 0x50}, + {0xC285, 0x55}, + {0xC286, 0x52}, + {0xC287, 0x52}, + {0xC288, 0x52}, + {0xC289, 0x52}, + {0xC28A, 0x52}, + {0xC28B, 0x51}, + {0xC28C, 0x52}, + {0xC28D, 0x52}, + {0xC201, 0x01}, + {0xC22E, 0xD7}, + {0xC26F, 0x18}, + {0xC28E, 0x52}, + }; + + rtk_uint16 alg_tune_giga_220411_patch[][2]= + { + {0x80b5,0x98}, + {0x80b6, 0xc3} , + {0x80b7 ,0xf6} , + {0x80b8 ,0x04}, + {0x80b9 ,0xd2}, + {0x80ba, 0x06}, + {0x80bb ,0xfa}, + {0x80bc ,0xbc}, + {0x80bd ,0x66}, + {0x80be ,0x19} , + {0x80bf ,0x2f} , + + {0x80c9, 0xc0} , + {0x80ca ,0xbb}, + {0x80cb ,0xf6} , + {0x80cc ,0x04}, + {0x80cd ,0x9e} , + {0x80ce ,0x06} , + {0x80cf ,0xfa}, + {0x80d0, 0xc4}, + {0x80d1 ,0x63}, + {0x80d2 ,0x19}, + {0x80d3 ,0x2f} , + {0x80c0, 0x0c}, + {0x80d4 ,0x0c} + }; + + rtk_uint16 alg_tune_fnet_6818_220628_patch[][2]= + { + {0x80a1 ,0x48}, + {0x80a2 ,0x9c}, + {0x80a3 ,0xb6}, + {0x80a4 ,0x03}, + {0x80a5 ,0xda} , + {0x80a6 ,0x0a}, + {0x80a7 ,0xea}, + {0x80a8 ,0xa6}, + {0x80a9, 0xe3}, + {0x80aa ,0x1f}, + {0x80ab ,0x3b}, + {0x80ac ,0x1e} + }; + + + + /* + * Function Declaration + */ + + + + void delay_loop(rtk_uint32 loop) + { + rtk_uint32 i, j; + + for (i = 0; i < loop; ++i) + for (j = 0; j < 40; j++) + ; + } + + + void Pin_Reset_8224_via_8373(void) + { + //******************** Begin to Reset RTL8224 by RTL8373_GPIO36 *************************** + rtl8373_setAsicRegBit(RTL8373_GPIO_OUT1_ADDR, 4, 0); + rtl8373_setAsicRegBit(RTL8373_GPIO_OE1_ADDR, 4, 1); + + delay_loop(100); + rtl8373_setAsicRegBit(RTL8373_GPIO_OUT1_ADDR, 4, 1); + delay_loop(500); + } + + + void uc1_sram_write_8b(rtk_uint32 port,rtk_uint32 addr,rtk_uint32 val) + { + + dal_rtl8373_phy_regbits_write(1<>7)&1); + NSQ=((REG_31_21>>6)&1); + + //#切debug port 看SIG_OK + writesdsreg_8224_via_8373_setbits(0,sds,0x21,0,5,5,1);//#RX_Test_EN + writesdsreg_8224_via_8373_setbits(0,sds,0x21,0x1b,10,7,9);//#reg0_debug_sel + writesdsreg_8224_via_8373(0,sds,0x1f,2,0x4A);//#切debug port + + + if(NSQ==1 || RXIDLE==0) + { + //#NSQ=1或RXIDLE=0åŽï¼Œè‹¥æ— SYNC_OK则 Rx reset + REG_5_0=readsdsreg_8224_via_8373(0,sds,0x5,0); + SYNC_OK=(REG_5_0&1); + if(SYNC_OK==0) + { + //puts "NSQ=1或RXIDLE=0åŽï¼Œè‹¥æ— SYNC_OK则 Rx reset!" + writesdsreg_8224_via_8373_setbits(0,sds,0x20,0,5,4,0x3);//FRC_RX_EN_VAL[5] FRC_RX_EN_ON[4] + writesdsreg_8224_via_8373_setbits(0,sds,0x20,0,5,4,0x1);//FRC_RX_EN_VAL[5] FRC_RX_EN_ON[4] + writesdsreg_8224_via_8373_setbits(0,sds,0x20,0,5,4,0x3);//FRC_RX_EN_VAL[5] FRC_RX_EN_ON[4] + } + else + { + LINK_OK = ((REG_5_0>>12)&1); + HI_BER = ((REG_5_0>>1)&1); + // puts "LINK_OK = $LINK_OK, HI_BER = $HI_BER;" + if((LINK_OK==0) || (HI_BER==1)) + { + writesdsreg_8224_via_8373_setbits(0,sds,0x20,0,5,4,0x3);//FRC_RX_EN_VAL[5] FRC_RX_EN_ON[4] + writesdsreg_8224_via_8373_setbits(0,sds,0x20,0,5,4,0x1);//FRC_RX_EN_VAL[5] FRC_RX_EN_ON[4] + writesdsreg_8224_via_8373_setbits(0,sds,0x20,0,5,4,0x3);//FRC_RX_EN_VAL[5] FRC_RX_EN_ON[4] + } + } + } + } + + */ + + rtk_api_ret_t fw_reset_flow_tgr_8224(rtk_uint32 sdsid) + { + rtk_uint32 REG_31_21,RXIDLE,NSQ,SYNC_OK,REG_5_0,LINK_OK,HI_BER; + ret_t retVal; + + //#切debug port 看SIG_OK + + retVal = dal_rtl8224_sds_regbits_write(sdsid, 0x21, 0, (1<<2), 1);//#RX_Test_EN + if(retVal != RT_ERR_OK) + return retVal; + + retVal = dal_rtl8224_sds_regbits_write(sdsid, 0x36, 0x05, (0xf<<11), 8);//##reg0_debug_sel + if(retVal != RT_ERR_OK) + return retVal; + + retVal = dal_rtl8224_sds_reg_write(sdsid, 0x1f, 0x2, 0x1f);//切debug port + if(retVal != RT_ERR_OK) + return retVal; + + retVal = dal_rtl8224_sds_reg_read(sdsid, 0x1f, 0x15, ®_31_21); + if(retVal != RT_ERR_OK) + return retVal; + + RXIDLE = ((REG_31_21 >> 7)&1); + NSQ = ((REG_31_21 >> 6)&1); + if(NSQ==1 || RXIDLE==0) + { + //#NSQ=1或RXIDLE=0åŽï¼Œè‹¥æ— SYNC_OK则 Rx reset + retVal = dal_rtl8224_sds_reg_read(sdsid, 0x5, 0x0, ®_5_0); + if(retVal != RT_ERR_OK) + return retVal; + + SYNC_OK=(REG_5_0&1); + if(SYNC_OK==0) + { + retVal = dal_rtl8224_sds_regbits_write(sdsid, 0x20, 0, (0x3<<4), 3);//FRC_RX_EN_VAL[5] FRC_RX_EN_ON[4] + if(retVal != RT_ERR_OK) + return retVal; + delay_loop(100); + retVal = dal_rtl8224_sds_regbits_write(sdsid, 0x20, 0, (0x3<<4), 1);//FRC_RX_EN_VAL[5] FRC_RX_EN_ON[4] + if(retVal != RT_ERR_OK) + return retVal; + delay_loop(100); + retVal = dal_rtl8224_sds_regbits_write(sdsid, 0x20, 0, (0x3<<4), 3);//FRC_RX_EN_VAL[5] FRC_RX_EN_ON[4] + if(retVal != RT_ERR_OK) + return retVal; + delay_loop(100); + + } + else + { + LINK_OK = ((REG_5_0>>12)&1); + HI_BER = ((REG_5_0>>1)&1); + if((LINK_OK==0) || (HI_BER==1)) + { + + retVal = dal_rtl8224_sds_regbits_write(sdsid, 0x20, 0, (0x3<<4), 3);//FRC_RX_EN_VAL[5] FRC_RX_EN_ON[4] + if(retVal != RT_ERR_OK) + return retVal; + delay_loop(100); + retVal = dal_rtl8224_sds_regbits_write(sdsid, 0x20, 0, (0x3<<4), 1);//FRC_RX_EN_VAL[5] FRC_RX_EN_ON[4] + if(retVal != RT_ERR_OK) + return retVal; + delay_loop(100); + retVal = dal_rtl8224_sds_regbits_write(sdsid, 0x20, 0, (0x3<<4), 3);//FRC_RX_EN_VAL[5] FRC_RX_EN_ON[4] + if(retVal != RT_ERR_OK) + return retVal; + delay_loop(100); + } + } + } + + return RT_ERR_OK; + } + + + rtk_api_ret_t fw_reset_flow_tgr(rtk_uint32 sdsid) + { + rtk_uint32 REG_31_21,RXIDLE,NSQ,SYNC_OK,REG_5_0,LINK_OK,HI_BER,test; + ret_t retVal; + + //#切debug port 看SIG_OK + retVal = dal_rtl8373_sds_regbits_write(sdsid, 0x21, 0, (1<<2), 1);//#RX_Test_EN + if(retVal != RT_ERR_OK) + return retVal; + + retVal = dal_rtl8373_sds_regbits_write(sdsid, 0x36, 0x5, (0xf<<11), 8);//##reg0_debug_sel + if(retVal != RT_ERR_OK) + return retVal; + + retVal = dal_rtl8373_sds_reg_write(sdsid, 0x1f, 0x2, 0x1f);//切debug port + if(retVal != RT_ERR_OK) + return retVal; + + /*REG_31_21=rtl8371b_sds_reg_get(sds,0x1F,0x15);*/ + retVal = dal_rtl8373_sds_reg_read(sdsid, 0x1f, 0x15, ®_31_21); + if(retVal != RT_ERR_OK) + return retVal; + + RXIDLE = ((REG_31_21 >> 7)&1); + NSQ = ((REG_31_21 >> 6)&1); + if(NSQ==1 || RXIDLE==0) + { + //#NSQ=1或RXIDLE=0åŽï¼Œè‹¥æ— SYNC_OK则 Rx reset + retVal = dal_rtl8373_sds_reg_read(sdsid, 0x5, 0x0, ®_5_0); + if(retVal != RT_ERR_OK) + return retVal; + + SYNC_OK=(REG_5_0&1); + if(SYNC_OK==0) + { + retVal = dal_rtl8373_sds_regbits_write(sdsid, 0x20, 0, (0x3<<4), 3);//FRC_RX_EN_VAL[5] FRC_RX_EN_ON[4] + if(retVal != RT_ERR_OK) + return retVal; + delay_loop(100); + retVal = dal_rtl8373_sds_regbits_write(sdsid, 0x20, 0, (0x3<<4), 1);//FRC_RX_EN_VAL[5] FRC_RX_EN_ON[4] + if(retVal != RT_ERR_OK) + return retVal; + delay_loop(100); + retVal = dal_rtl8373_sds_regbits_write(sdsid, 0x20, 0, (0x3<<4), 3);//FRC_RX_EN_VAL[5] FRC_RX_EN_ON[4] + if(retVal != RT_ERR_OK) + return retVal; + delay_loop(100); + retVal = dal_rtl8373_sds_regbits_write(sdsid, 0x20, 0, (0x3<<4), 0);//FRC_RX_EN_VAL[5] FRC_RX_EN_ON[4] + if(retVal != RT_ERR_OK) + return retVal; + delay_loop(100); + retVal = dal_rtl8373_sds_reg_read(sdsid, 0x5, 0, &test); + if(retVal != RT_ERR_OK) + return retVal; + + } + else + { + retVal = dal_rtl8373_sds_reg_read(sdsid, 0x5, 0, ®_5_0); + if(retVal != RT_ERR_OK) + return retVal; + + LINK_OK = ((REG_5_0>>12)&1); + HI_BER = ((REG_5_0>>1)&1); + // puts "LINK_OK = $LINK_OK, HI_BER = $HI_BER;" + if((LINK_OK==0) || (HI_BER==1)) + { + retVal = dal_rtl8373_sds_regbits_write(sdsid, 0x20, 0, (0x3<<4), 3);//FRC_RX_EN_VAL[5] FRC_RX_EN_ON[4] + if(retVal != RT_ERR_OK) + return retVal; + delay_loop(100); + retVal = dal_rtl8373_sds_regbits_write(sdsid, 0x20, 0, (0x3<<4), 1);//FRC_RX_EN_VAL[5] FRC_RX_EN_ON[4] + if(retVal != RT_ERR_OK) + return retVal; + delay_loop(100); + retVal = dal_rtl8373_sds_regbits_write(sdsid, 0x20, 0, (0x3<<4), 3);//FRC_RX_EN_VAL[5] FRC_RX_EN_ON[4] + if(retVal != RT_ERR_OK) + return retVal; + delay_loop(100); + retVal = dal_rtl8373_sds_regbits_write(sdsid, 0x20, 0, (0x3<<4), 0);//FRC_RX_EN_VAL[5] FRC_RX_EN_ON[4] + if(retVal != RT_ERR_OK) + return retVal; + } + } + } + + return RT_ERR_OK; + } + + + void afe_patch_6818_220325(void) + { + if(CHIP_TYPE == CHIP_RTL8373_MODE ) + { + //setPhyMaskRegBits(1<<1|1<<5,31,0xbf84,2,0,7); + //setPhyMaskRegBits(1<<1|1<<5,31,0xbf8c,10,6,0); + dal_rtl8373_phy_regbits_write(1<<1|1<<5, 31, 0xbf84, 0x7, 7); + dal_rtl8373_phy_regbits_write(1<<1|1<<5, 31, 0xbf8c, 0x1f<<6, 0); + } + else if(CHIP_TYPE == CHIP_RTL8372_MODE ) + { + //setPhyMaskRegBits(1<<5,31,0xbf84,2,0,7); + //setPhyMaskRegBits(1<<5,31,0xbf8c,10,6,0); + dal_rtl8373_phy_regbits_write(1<<5, 31, 0xbf84, 0x7, 7); + dal_rtl8373_phy_regbits_write(1<<5, 31, 0xbf8c, 0x1f<<6, 0); + } + } + + + void alg_tune_fnet_6818_220628(rtk_uint32 phymask) + { + rtk_uint16 port,i,data_ram_addr,data_ram_val,len; + + len = sizeof(alg_tune_fnet_6818_220628_patch)/4; + + for(port=0;port<8;port++) + { + if((1<>8)&1); + SYNC_OK=(REG_1_29&1); + LINK_OK=((REG_1_29>>4)&1); + if(SIG_OK==1) + { + if(SYNC_OK==0) + { + + dal_rtl8373_sds_regbits_write(sds, 0, 0, 1<<1, 1); + delay_loop(100); + dal_rtl8373_sds_regbits_write(sds, 0, 0, 1<<1, 0); + delay_loop(100); + dal_rtl8373_sds_regbits_write(sds, 0, 0, 1<<1, 1); + } + else + { + if(LINK_OK==0) + { + dal_rtl8373_sds_regbits_write(sds, 0, 0, 1<<1, 1); + delay_loop(100); + dal_rtl8373_sds_regbits_write(sds, 0, 0, 1<<1, 0); + delay_loop(100); + dal_rtl8373_sds_regbits_write(sds, 0, 0, 1<<1, 1); + + } + } + } + } + + rtk_api_ret_t rtl8373_8224_init(void) + { + rtk_uint32 i; + + + //******************** End to Reset RTL8224 by RTL8373_GPIO36 *************************** + Pin_Reset_8224_via_8373(); + //******************** Begin to Initial RTL8373 MDC/MDIO ******************************** + // puts "MDC/MDIO pad initial" + + rtl8373_setAsicRegBits(RTL8373_SMI_MAC_TYPE_CTRL_ADDR, RTL8373_SMI_MAC_TYPE_CTRL_MAC_PORT3_TYPE_MASK, 1);//MAC_PORT3_TYPE=0 port type: RTL8373 default set port0-7 polling 10G/2.5GPHY + rtl8373_setAsicRegBits(RTL8373_SMI_PORT_POLLING_SEL_ADDR, 0xff, 0xff); // RTL8373 set port0-8 polling internal resolution reg + rtl8373_setAsicRegBits(RTL8373_SMI_CTRL_ADDR, 0x7000, 7);//enable SMI0/1/2 MDC clock output, default is 0 + //******************** End to Initial RTL8373 MDC/MDIO ******************************** + +//>50ms + delay_loop(5000000); + + get_version_8373(); + get_version_8224(); + PRINT("8373_8224 init, 8373 ver is %d, 8224 ver is %d\n", Ver8373_72, Ver8224); + + delay_loop(100); + + + rtl8373_setAsicRegBits(RTL8373_SDS_MODE_SEL_ADDR, RTL8373_SDS_MODE_SEL_SDS0_USX_SUB_MODE_MASK, 2);//SDS0_USX_SUB_MODE = 0x2, default is 0x2 10G-QXGMII + rtl8373_setAsicRegBits(RTL8373_SDS_MODE_SEL_ADDR, RTL8373_SDS_MODE_SEL_SDS0_MODE_SEL_MASK, 0xD);//SDS0_MODE_SEL = 0xD + dal_rtl8373_sds_regbits_write(0, 6, 1, 0x4, 1); + delay_loop(20); + dal_rtl8373_sds_regbits_write(0, 6, 1, 0x4, 0); + + + rtl8373_setAsicRegBits(RTL8373_SDS_MODE_SEL_ADDR, RTL8373_SDS_MODE_SEL_SDS0_MODE_SEL_MASK, 0x1F);//SDS0_MODE_SEL = 0x1F + delay_loop(100); + + + rtl8373_setAsicRegBit(RTL8373_SDS_MODE_SEL_ADDR, RTL8373_SDS_MODE_SEL_CFG_MAC3_8221B_OFFSET, 0); + rtl8373_setAsicRegBit(RTL8373_SDS_MODE_SEL_ADDR, RTL8373_SDS_MODE_SEL_CFG_MAC8_8221B_OFFSET, 0); + + SDS_MODE_SET_SW(CHIP_RTL8373_MODE,0,SERDES_10GQXG); + SDS_MODE_SET_SW(CHIP_RTL8224_MODE,0,SERDES_10GQXG); + + delay_loop(50); + fw_reset_flow_tgr_8224(0); + + delay_loop(50); + + fw_reset_flow_tgr(0); + + + rtl8373_setAsicRegBits(RTL8373_CFG_PHY_MDI_REVERSE_ADDR, 0xf, 0xc); + dal_rtl8224_top_regbits_write(RTL8373_CFG_PHY_MDI_REVERSE_ADDR, 0xf, 0xc); + dal_rtl8373_phy_write(0xff, 31, 0xa610, 0x2858); + + + //## ---------------------------Patch MAC-------------------------- + // #set MAC_L2_GLOBAL_CTRL0 0x5FD4 + rtl8373_setAsicRegBit(RTL8373_MAC_L2_GLOBAL_CTRL0_ADDR,RTL8373_MAC_L2_GLOBAL_CTRL0_FWD_INVLD_MAC_CTRL_EN_OFFSET,1); + rtl8373_setAsicRegBit(RTL8373_MAC_L2_GLOBAL_CTRL0_ADDR,RTL8373_MAC_L2_GLOBAL_CTRL0_FWD_UNKN_OPCODE_EN_OFFSET,1); + + + // #BYP_TX_CRC=1 + for(i=0;i<9;i++) + { + rtl8373_setAsicRegBit(RTL8373_MAC_L2_PORT_CTRL_ADDR(i),RTL8373_MAC_L2_PORT_CTRL_RX_CHK_CRC_EN_OFFSET,1); + rtl8373_setAsicRegBit(RTL8373_MAC_L2_PORT_CTRL_ADDR(i),RTL8373_MAC_L2_PORT_CTRL_CLOCK_SWITCH_OFFSET,1); + } + + rtl8373_setAsicRegBit(RTL8373_RS_LAYER_CONFIG_ADDR,RTL8373_RS_LAYER_CONFIG_RS_LINK_FAULT_INDI_OFF_OFFSET,1); + + + for(i=0; i<10; i++) + { + rtl8373_setAsicReg(RTL8373_FC_PORT_ACT_CTRL_ADDR(i), 0x1050); + } + + //## ---------------------------Init END-------------------------- + + rtl8373_setAsicRegBit(RTL8373_DW8051_CFG_ADDR,RTL8373_DW8051_CFG_DW8051_READY_OFFSET,ENABLE); + + delay_loop(50); + +#if PHY_PATCH + if(Ver8224 == 1) //chipB + { + RL6818B_pwr_on_patch_phy_v006(0xf); + RL6818B_pwr_on_patch_phy_v006_rls_lockmain(0xf); + } + else if(Ver8224 == 2) //chipC + { + RL6818C_pwr_on_patch_phy_v004(0xf); + RL6818C_pwr_on_patch_phy_v004_rls_lockmain(0xf); + } + + if(Ver8373_72== 1) //chipB + { + RL6818B_pwr_on_patch_phy_v006(0xf0); + RL6818B_pwr_on_patch_phy_v006_rls_lockmain(0xf0); + } + else if(Ver8373_72 == 2) //chipC + { + RL6818C_pwr_on_patch_phy_v004(0xf0); + RL6818C_pwr_on_patch_phy_v004_rls_lockmain(0xf0); + } +#endif + + dal_rtl8373_phy_write(0xff, 31, 0xa610, 0x2058); + rtl8373_setAsicRegBits(RTL8373_SMI_GLB_CTRL_ADDR,RTL8373_SMI_GLB_CTRL_SMI_POLLING_MASK_MASK,0x1ff); + rtl8373_setAsicRegBits(RTL8373_SMI_MAC_TYPE_CTRL_ADDR, RTL8373_SMI_MAC_TYPE_CTRL_MAC_PORT8_TYPE_MASK, 0); + + return RT_ERR_OK; + +} + + + + + rtk_api_ret_t rtl8372_init() + { + rtk_uint32 i; + //******************** Begin to Initial RTL8373 MDC/MDIO ******************************** + // puts "MDC/MDIO pad initial" + + rtl8373_setAsicRegBits(RTL8373_SMI_PORT_POLLING_SEL_ADDR, 0xf0, 0xf); // RTL8372 set port4-7 polling internal resolution reg + rtl8373_setAsicRegBits(RTL8373_SMI_CTRL_ADDR, 0x7000, 7);//enable SMI0/1/2 MDC clock output, default is 0 + //******************** End to Initial RTL8373 MDC/MDIO ******************************** + + get_version_8373(); + PRINT("8372 init, 8372 ver is %d\n", Ver8373_72); + + delay_loop(100); + + rtl8373_setAsicRegBit(RTL8373_SDS_MODE_SEL_ADDR, RTL8373_SDS_MODE_SEL_CFG_MAC3_8221B_OFFSET, 0); + rtl8373_setAsicRegBit(RTL8373_SDS_MODE_SEL_ADDR, RTL8373_SDS_MODE_SEL_CFG_MAC3_8221B_OFFSET, 0); + // ## tgr reset flow + delay_loop(50); + + //******************** Begin to Initial RTL8372 PHY configuration *************************** + + + //#MDI reverse configuration for Demo Tap UP RJ45, RTL8372 + rtl8373_setAsicRegBits(RTL8373_CFG_PHY_MDI_REVERSE_ADDR, 0xf, 0xc); + + // puts "Power down PHY 4~7" + dal_rtl8373_phy_write(0xf0, 31, 0xa610, 0x2858); + +// ## ---------------------------Patch MAC-------------------------- + + rtl8373_setAsicRegBit(RTL8373_MAC_L2_GLOBAL_CTRL0_ADDR,RTL8373_MAC_L2_GLOBAL_CTRL0_FWD_INVLD_MAC_CTRL_EN_OFFSET,1); + rtl8373_setAsicRegBit(RTL8373_MAC_L2_GLOBAL_CTRL0_ADDR,RTL8373_MAC_L2_GLOBAL_CTRL0_FWD_UNKN_OPCODE_EN_OFFSET,1); + + // #BYP_TX_CRC=1 + for(i=3;i<9;i++) + { + rtl8373_setAsicRegBit(RTL8373_MAC_L2_PORT_CTRL_ADDR(i),RTL8373_MAC_L2_PORT_CTRL_RX_CHK_CRC_EN_OFFSET,1); + rtl8373_setAsicRegBit(RTL8373_MAC_L2_PORT_CTRL_ADDR(i),RTL8373_MAC_L2_PORT_CTRL_CLOCK_SWITCH_OFFSET,1); + } + + rtl8373_setAsicRegBit(RTL8373_RS_LAYER_CONFIG_ADDR,RTL8373_RS_LAYER_CONFIG_RS_LINK_FAULT_INDI_OFF_OFFSET,1); + + for(i=0; i<10; i++) + { + rtl8373_setAsicReg(RTL8373_FC_PORT_ACT_CTRL_ADDR(i), 0x1050); + } + +//## ---------------------------Init END-------------------------- + rtl8373_setAsicRegBit(RTL8373_DW8051_CFG_ADDR,RTL8373_DW8051_CFG_DW8051_READY_OFFSET,ENABLE); + + delay_loop(200); + +#if PHY_PATCH + if(Ver8373_72 == 1) + { + RL6818B_pwr_on_patch_phy_v006(0xf0); + RL6818B_pwr_on_patch_phy_v006_rls_lockmain(0xf0); + } + else if(Ver8373_72 == 2) + { + RL6818C_pwr_on_patch_phy_v004(0xf0); + RL6818C_pwr_on_patch_phy_v004_rls_lockmain(0xf0); + } +#endif + + dal_rtl8373_phy_write(0xf0, 31, 0xa610, 0x2058); + rtl8373_setAsicRegBits(RTL8373_SMI_GLB_CTRL_ADDR,RTL8373_SMI_GLB_CTRL_SMI_POLLING_MASK_MASK,0x1f8); + rtl8373_setAsicRegBits(RTL8373_SMI_MAC_TYPE_CTRL_ADDR, RTL8373_SMI_MAC_TYPE_CTRL_MAC_PORT3_TYPE_MASK, 0); + rtl8373_setAsicRegBits(RTL8373_SMI_MAC_TYPE_CTRL_ADDR, RTL8373_SMI_MAC_TYPE_CTRL_MAC_PORT8_TYPE_MASK, 0); + + return RT_ERR_OK; + +} + + + rtk_api_ret_t rtl8366u_init(void) + { + rtk_uint32 i = 0; + rtk_uint32 chip_mode = 0; + + rtl8373_getAsicRegBits(RTL8373_BOND_INFO_ADDR, 3, &chip_mode ); + + if(chip_mode !=2) + { + return RT_ERR_CHIP_NOT_SUPPORTED; //chip mode error + } + + get_version_8366u(); + + //******************** Begin to Initial RTL8373 MDC/MDIO ******************************** + // puts "MDC/MDIO pad initial" + rtl8373_setAsicRegBits(RTL8373_SMI_MAC_TYPE_CTRL_ADDR, RTL8373_SMI_MAC_TYPE_CTRL_MAC_PORT8_TYPE_MASK, 0); //#MAC_PORT8_TYPE=0 port type: sds_ablty + rtl8373_setAsicRegBits(RTL8373_SMI_MAC_TYPE_CTRL_ADDR, RTL8373_SMI_MAC_TYPE_CTRL_MAC_PORT3_TYPE_MASK, 0); //#MAC_PORT3_TYPE=0 port type: sds_ablty + rtl8373_setAsicRegBits(RTL8373_SMI_PORT_POLLING_SEL_ADDR, 0xf0, 0xf);//#RTL8372/RTL8372N/RTL8366U set port4-7 polling internal resolution reg + rtl8373_setAsicRegBits(RTL8373_SMI_CTRL_ADDR, 0x7000, 7); //enable SMI0/1/2 MDC clock output, default is 0 + delay_loop(1); + + + dal_rtl8373_sds_regbits_write(1, 0x2e, 0x13, 0x30, 0x1); //10G sds CMU off + dal_rtl8373_phy_writeBits(0xc0, 7, 32, 1<<7, 0); + //******************** End to Initial RTL8373 MDC/MDIO ******************************** + + //## ---------------------------Init LED-------------------------- + //led_8366U_cfg(); + + + //## ---------------------------Init SDS-------------------------- + + dal_rtl8373_sds_regbits_write(0, 0, 0, 0x200, 1); //#SDS0RX PN swap + dal_rtl8373_sds_regbits_write(1, 0, 0, 0x200, 1); //#SDS1RX PN swap + + dal_rtl8373_sds_regbits_write(0, 6, 2, 0x2000, 1); + dal_rtl8373_sds_regbits_write(1, 6, 2, 0x2000, 1); + + + // ## tgr reset flow + delay_loop(5); + fw_reset_flow_tgr(1); //8366U SDS1 execute reset flow + delay_loop(5); + fw_reset_flow_tgr(0); + + //## ---------------------------Patch PHY-------------------------- + + //##MDI reverse configuration for Demo Tap UP RJ45, RTL8366U/RTL8373N/RTL8372N + rtl8373_setAsicRegBits(RTL8373_CFG_PHY_MDI_REVERSE_ADDR, 0xF, 0xC); + rtl8373_setAsicRegBits(RTL8373_CFG_PHY_TX_POLARITY_SWAP_ADDR, 0xFFFF, 0x596A); //#TX_POLARITY_SWAP + + // puts "Power down PHY 4~7" + dal_rtl8373_phy_write(0xF0, 31, 0xa610, 0x2858); + + //## ---------------------------Patch MAC-------------------------- + rtl8373_setAsicRegBits(RTL8373_MAC_L2_GLOBAL_CTRL0_ADDR, 0x180000, 3);//#cfg_FWD_INVLD_MAC_CTRL_EN,cfg_FWD_UNKN_OPCODE_EN + + // set MAC_L2_PORT_CTRL_ADDR 0x1238; 0x1238+$port*0x100 + for(i=3;i<9;i++) + { + rtl8373_setAsicRegBits(RTL8373_MAC_L2_PORT_CTRL_ADDR(i),0x10,1); //#RX_CHK_CRC_EN=1 + rtl8373_setAsicRegBits(RTL8373_MAC_L2_PORT_CTRL_ADDR(i),0x100,1); //#CLOCK_SWITCH=1; Ϊ½â¾öijélinkdownʱÒòclockãµô¶øÎÞ·¨drain outµÄÎÊÌâ + } + + //#RS_LINK_FAULT_INDI_OFF=1 disable link fault flag, resolve port4-port7 linkdown dsc expand issue + + rtl8373_setAsicRegBits(RTL8373_RS_LAYER_CONFIG_ADDR, 0x20, 1); + + // + for(i=0; i<10; i++) + { + rtl8373_setAsicReg(RTL8373_FC_PORT_ACT_CTRL_ADDR(i), 0x1050); + } + //## ---------------------------Init END-------------------------- + rtl8373_setAsicRegBits(RTL8373_DW8051_CFG_ADDR, RTL8373_DW8051_CFG_DW8051_READY_MASK, ENABLE); + delay_loop(100); + +#if PHY_PATCH + if (Ver8366U == 2) + { + RL6818C_pwr_on_patch_phy_v004(0xf0); + RL6818C_pwr_on_patch_phy_v004_rls_lockmain(0xf0); + } + +#endif + + // puts "Power up PHY 4~7" + dal_rtl8373_phy_write(0xF0 ,31,0xa610,0x2058); + //RTL8372/RTL8372N/RTL8366U set polling mask 0x1f8, port 3/8 from serdes need config bit8=1 + rtl8373_setAsicRegBits(RTL8373_SMI_GLB_CTRL_ADDR , 0x1FF000,0x1f8); + + delay_loop(50); + + return RT_ERR_OK; +} + +rtk_api_ret_t rtl8372n_init(void) +{ + rtk_uint32 i = 0; + rtk_uint32 chip_mode = 0; + + rtl8373_getAsicRegBits(RTL8373_BOND_INFO_ADDR, 3, &chip_mode ); + + if(chip_mode !=2) + { + return RT_ERR_CHIP_NOT_SUPPORTED; //chip mode error + } + + get_version_8373(); + + //******************** Begin to Initial RTL8373 MDC/MDIO ******************************** + // puts "MDC/MDIO pad initial" + rtl8373_setAsicRegBits(RTL8373_SMI_MAC_TYPE_CTRL_ADDR, RTL8373_SMI_MAC_TYPE_CTRL_MAC_PORT8_TYPE_MASK, 0); //#MAC_PORT8_TYPE=0 port type: sds_ablty + rtl8373_setAsicRegBits(RTL8373_SMI_MAC_TYPE_CTRL_ADDR, RTL8373_SMI_MAC_TYPE_CTRL_MAC_PORT3_TYPE_MASK, 0); //#MAC_PORT3_TYPE=0 port type: sds_ablty + rtl8373_setAsicRegBits(RTL8373_SMI_PORT_POLLING_SEL_ADDR, 0xf0, 0xf);//#RTL8372/RTL8372N/RTL8366U set port4-7 polling internal resolution reg + rtl8373_setAsicRegBits(RTL8373_SMI_CTRL_ADDR, 0x7000, 7); //enable SMI0/1/2 MDC clock output, default is 0 + delay_loop(1); + //******************** End to Initial RTL8373 MDC/MDIO ******************************** + + //## ---------------------------Init LED-------------------------- + //led_8372n_cfg(); + + + + //## ---------------------------Init SDS-------------------------- + + dal_rtl8373_sds_regbits_write(0, 0, 0, 0x200, 1); //#SDS0RX PN swap + dal_rtl8373_sds_regbits_write(1, 0, 0, 0x200, 1); //#SDS1RX PN swap + + dal_rtl8373_sds_regbits_write(0, 6, 2, 0x2000, 1); + dal_rtl8373_sds_regbits_write(1, 6, 2, 0x2000, 1); + + + // ## tgr reset flow + delay_loop(5); + fw_reset_flow_tgr(1); //8366U SDS1 execute reset flow + delay_loop(5); + fw_reset_flow_tgr(0); + + //## ---------------------------Patch PHY-------------------------- + + //##MDI reverse configuration for Demo Tap UP RJ45, RTL8366U/RTL8373N/RTL8372N + rtl8373_setAsicRegBits(RTL8373_CFG_PHY_MDI_REVERSE_ADDR, 0xF, 0xC); + rtl8373_setAsicRegBits(RTL8373_CFG_PHY_TX_POLARITY_SWAP_ADDR, 0xFFFF, 0x596A); //#TX_POLARITY_SWAP + + // puts "Power down PHY 4~7" + dal_rtl8373_phy_write(0xF0, 31, 0xa610, 0x2858); + + //## ---------------------------Patch MAC-------------------------- + rtl8373_setAsicRegBits(RTL8373_MAC_L2_GLOBAL_CTRL0_ADDR, 0x180000, 3);//#cfg_FWD_INVLD_MAC_CTRL_EN,cfg_FWD_UNKN_OPCODE_EN + + // set MAC_L2_PORT_CTRL_ADDR 0x1238; 0x1238+$port*0x100 + for(i=3;i<9;i++) + { + rtl8373_setAsicRegBits(RTL8373_MAC_L2_PORT_CTRL_ADDR(i),0x10,1); //#RX_CHK_CRC_EN=1 + rtl8373_setAsicRegBits(RTL8373_MAC_L2_PORT_CTRL_ADDR(i),0x100,1); //#CLOCK_SWITCH=1; Ϊ½â¾öijélinkdownʱÒòclockãµô¶øÎÞ·¨drain outµÄÎÊÌâ + } + + //#RS_LINK_FAULT_INDI_OFF=1 disable link fault flag, resolve port4-port7 linkdown dsc expand issue + + rtl8373_setAsicRegBits(RTL8373_RS_LAYER_CONFIG_ADDR, 0x20, 1); + + // + for(i=0; i<10; i++) + { + rtl8373_setAsicReg(RTL8373_FC_PORT_ACT_CTRL_ADDR(i), 0x1050); + } + //## ---------------------------Init END-------------------------- + rtl8373_setAsicRegBits(RTL8373_DW8051_CFG_ADDR, RTL8373_DW8051_CFG_DW8051_READY_MASK, ENABLE); + delay_loop(100); + +#if PHY_PATCH + if (Ver8373_72 == 2) + { + RL6818C_pwr_on_patch_phy_v004(0xf0); + RL6818C_pwr_on_patch_phy_v004_rls_lockmain(0xf0); + } + +#endif + + // puts "Power up PHY 4~7" + dal_rtl8373_phy_write(0xF0 ,31,0xa610,0x2058); + //RTL8372/RTL8372N/RTL8366U set polling mask 0x1f8, port 3/8 from serdes need config bit8=1 + rtl8373_setAsicRegBits(RTL8373_SMI_GLB_CTRL_ADDR , 0x1FF000,0x1f8); + + delay_loop(50); + + return RT_ERR_OK; + +} + + + void Pin_Reset_8224N_via_8373N(void) + { + //******************** Begin to Reset RTL8224N by RTL8373N_GPIO30 *************************** + rtl8373_setAsicRegBit(RTL8373_GPIO_OUT0_ADDR, 30, 0); //#GPIO_OUT0.bit30=0 for GPIO30 + rtl8373_setAsicRegBit(RTL8373_IO_MUX_SEL_2_ADDR, 3, 0); //#GPIO30 Function + + rtl8373_setAsicRegBit(RTL8373_GPIO_OE0_ADDR, 30, 1); //#GPIO_OE0.bit30=1 for enable GPIO30 output + // after 11 + delay_loop(100); + rtl8373_setAsicRegBit(RTL8373_GPIO_OUT0_ADDR, 30, 1); //#GPIO_OUT0.bit30=1 for GPIO30=1 to set RTL8224N nRESET pin high + delay_loop(500); + } + +rtk_api_ret_t rtl8373N_8224N_init(void) +{ + rtk_uint32 chip_mode = 0; + rtk_uint32 i; + rtk_uint32 phymask = 0xff; + + rtl8373_getAsicRegBits(RTL8373_BOND_INFO_ADDR, 3, &chip_mode); + + if(chip_mode != 0x3) + { + return RT_ERR_CHIP_NOT_SUPPORTED; //chip mode error + } + + + Pin_Reset_8224N_via_8373N(); + //******************** Begin to Initial RTL8373 MDC/MDIO ******************************** + // puts "MDC/MDIO pad initial" + rtl8373_setAsicRegBits(RTL8373_SMI_MAC_TYPE_CTRL_ADDR, RTL8373_SMI_MAC_TYPE_CTRL_MAC_PORT3_TYPE_MASK, 1); //MAC_PORT3_TYPE=0 port type: RTL8373 default set port0-7 polling 10G/2.5GPHY + rtl8373_setAsicRegBits(RTL8373_SMI_PORT_POLLING_SEL_ADDR, 0xFF, 0xFF);//#RTL8372/RTL8372N/RTL8366U set port4-7 polling internal resolution reg + rtl8373_setAsicRegBits(RTL8373_SMI_CTRL_ADDR, 0X7000, 7); //enable SMI0/1/2 MDC clock output, default is 0 + + //******************** End to Initial RTL8373 MDC/MDIO ******************************** + //>50ms + delay_loop(5000000); + + get_version_8373(); + get_version_8224(); + PRINT("8373N_8224N init, 8373N ver is %d, 8224N ver is %d\n", Ver8373N, Ver8224N); + + delay_loop(100); + //## ---------------------------Init LED-------------------------- + //led_8373N_cfg(); + //## ---------------------------Init SDS-------------------------- + rtl8373_setAsicRegBits(RTL8373_SDS_MODE_SEL_ADDR, RTL8373_SDS_MODE_SEL_SDS0_USX_SUB_MODE_MASK, 2);//SDS0_USX_SUB_MODE = 0x2, default is 0x2 10G-QXGMII + rtl8373_setAsicRegBits(RTL8373_SDS_MODE_SEL_ADDR, RTL8373_SDS_MODE_SEL_SDS0_MODE_SEL_MASK, 0xD);//SDS0_MODE_SEL = 0xD + + dal_rtl8373_sds_regbits_write(0, 6, 1, 0x4, 1);//#serdes0 AFE loopback + delay_loop(20); + + dal_rtl8373_sds_regbits_write(0, 6, 1, 0x4, 0);//#关闭loopback + rtl8373_setAsicRegBits(RTL8373_SDS_MODE_SEL_ADDR, RTL8373_SDS_MODE_SEL_SDS0_MODE_SEL_MASK, 0x1F);//SDS0_MODE_SEL = 0x1F + delay_loop(100); + + dal_rtl8373_sds_regbits_write(0, 6, 2, 0x2000, 1); //##S0RX PN swap for 64B/66B + dal_rtl8373_sds_regbits_write(1, 6, 2, 0x2000, 1); //S1RX PN swap for 64B/66B + + dal_rtl8373_sds_regbits_write(1, 0, 0, 0x200, 1); //#S1RX PN swap for 8B/10B + + dal_rtl8224_sds_regbits_write(0, 6, 2, 0x2000, 1); //##S0RX PN swap for 64B/66B + + SDS_MODE_SET_SW(CHIP_RTL8373N_MODE, 0, SERDES_10GQXG); + + + //## ---------------------------Init 8224 SDS-------------------------- + SDS_MODE_SET_SW(CHIP_RTL8224N_MODE, 0, SERDES_10GQXG); + delay_loop(50); + fw_reset_flow_tgr_8224(0); + + delay_loop(50); + fw_reset_flow_tgr(1); + + delay_loop(50); + fw_reset_flow_tgr(0); + + + //## ---------------------------Patch PHY-------------------------- + + //##MDI reverse configuration for Demo Tap UP RJ45, RTL8366U/RTL8373N/RTL8372N + rtl8373_setAsicRegBits(RTL8373_CFG_PHY_MDI_REVERSE_ADDR, 0xf, 0xc); + rtl8373_setAsicRegBits(RTL8373_CFG_PHY_TX_POLARITY_SWAP_ADDR, 0xffff, 0x596A); //#TX_POLARITY_SWAP + + dal_rtl8224_top_regbits_write(RTL8373_CFG_PHY_MDI_REVERSE_ADDR, 0xf, 0xc); + dal_rtl8224_top_regbits_write(RTL8373_CFG_PHY_TX_POLARITY_SWAP_ADDR, 0xffff, 0x596A); + + // puts "Power down PHY 0~7" + dal_rtl8373_phy_write(phymask, 31, 0xa610, 0x2858); + + //## ---------------------------Patch MAC-------------------------- + rtl8373_setAsicRegBit(RTL8373_MAC_L2_GLOBAL_CTRL0_ADDR, RTL8373_MAC_L2_GLOBAL_CTRL0_FWD_INVLD_MAC_CTRL_EN_OFFSET, 1); //#cfg_FWD_INVLD_MAC_CTRL_EN, + rtl8373_setAsicRegBit(RTL8373_MAC_L2_GLOBAL_CTRL0_ADDR, RTL8373_MAC_L2_GLOBAL_CTRL0_FWD_UNKN_OPCODE_EN_OFFSET, 1); //cfg_FWD_UNKN_OPCODE_EN + + + for(i=0; i<8; i++) + { + rtl8373_setAsicRegBit(RTL8373_MAC_L2_PORT_CTRL_ADDR(i),RTL8373_MAC_L2_PORT_CTRL_RX_CHK_CRC_EN_OFFSET,1); //#RX_CHK_CRC_EN=1 + rtl8373_setAsicRegBit(RTL8373_MAC_L2_PORT_CTRL_ADDR(i),RTL8373_MAC_L2_PORT_CTRL_CLOCK_SWITCH_OFFSET,1); //#CLOCK_SWITCH=1; + } + + rtl8373_setAsicRegBit(RTL8373_RS_LAYER_CONFIG_ADDR, RTL8373_RS_LAYER_CONFIG_RS_LINK_FAULT_INDI_OFF_OFFSET, 1); + + for(i=0; i<10; i++) + { + rtl8373_setAsicReg(RTL8373_FC_PORT_ACT_CTRL_ADDR(i), 0x1050); + } + //## ---------------------------Init END-------------------------- + + rtl8373_setAsicRegBit(RTL8373_DW8051_CFG_ADDR, RTL8373_DW8051_CFG_DW8051_READY_OFFSET, ENABLE); + delay_loop(50); + +#if PHY_PATCH + + if (Ver8224N == 1) //chip B + { + RL6818B_pwr_on_patch_phy_v006(0xf); + RL6818B_pwr_on_patch_phy_v006_rls_lockmain(0xf); + } + else if(Ver8224N == 2) //chip C + { + RL6818C_pwr_on_patch_phy_v004(0xf); + RL6818C_pwr_on_patch_phy_v004_rls_lockmain(0xf); + } + + if (Ver8373N == 1) + { + RL6818B_pwr_on_patch_phy_v006(0xf0); + RL6818B_pwr_on_patch_phy_v006_rls_lockmain(0xf0); + } + else if(Ver8373N == 2) + { + RL6818C_pwr_on_patch_phy_v004(0xf0); + RL6818C_pwr_on_patch_phy_v004_rls_lockmain(0xf0); + } +#endif + + // puts "Power up PHY 0~7" + dal_rtl8373_phy_write(phymask, 31, 0xa610, 0x2058); + rtl8373_setAsicRegBits(RTL8373_SMI_GLB_CTRL_ADDR, RTL8373_SMI_GLB_CTRL_SMI_POLLING_MASK_MASK, 0x1ff); + + delay_loop(50); + + return RT_ERR_OK; + +} + + + /* Function Name: + * dal_rtl8373_switch_init + * Description: + * Set chip to default configuration enviroment + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set chip registers to default configuration for different release chip model. + */ + rtk_api_ret_t dal_rtl8373_switch_init() + { + ret_t retVal; + rtk_uint32 regdata; + + if((retVal = rtl8373_getAsicReg(0x4, ®data)) != RT_ERR_OK) + return retVal; + + regdata = regdata >> 8; + PRINT("regdata = 0x%x", regdata); + + if (regdata == 0x837300) + { + CHIP_TYPE = CHIP_RTL8373_MODE; + + return rtl8373_8224_init(); + } + else if (regdata == 0x837200) + { + CHIP_TYPE = CHIP_RTL8372_MODE; + return rtl8372_init(); + } + else if (regdata == 0x822400) + { + CHIP_TYPE = CHIP_RTL8224_MODE; + } + else if (regdata == 0x837370) + { + CHIP_TYPE = CHIP_RTL8373N_MODE; + + return rtl8373N_8224N_init(); + + } + else if (regdata == 0x837270) + { + CHIP_TYPE = CHIP_RTL8372N_MODE; + + return rtl8372n_init(); + } + else if (regdata == 0x822470) + { + CHIP_TYPE = CHIP_RTL8224N_MODE; + + } + else if (regdata == 0x8366A8) + { + CHIP_TYPE = CHIP_RTL8366U_MODE; + + return rtl8366u_init(); + } + else + return RT_ERR_CHIP_NOT_FOUND; + + return RT_ERR_OK; + } + + diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_switch.h b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_switch.h new file mode 100755 index 00000000..ac6914cf --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_switch.h @@ -0,0 +1,320 @@ + +/* + * Copyright (C) 2012 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : Definition of Switch Global API + * + * Feature : The file have include the following module and sub-modules + * (1) Switch parameter settings + * + */ + +#ifndef __DAL_RTL8373_SWITCH_H__ +#define __DAL_RTL8373_SWITCH_H__ + +/* + * Include Files + */ +#include +#include + + +typedef enum chip_mode_type_e +{ + CHIP_RTL8373_MODE, + CHIP_RTL8372_MODE, + CHIP_RTL8224_MODE, + CHIP_RTL8221B_MODE, + CHIP_RTL8373N_MODE, + CHIP_RTL8372N_MODE, + CHIP_RTL8224N_MODE, + CHIP_RTL8366U_MODE, + CHIP_MODE_END +}chip_mode_type_t; +/* + * Symbol Definition + */ + + + +typedef enum rtl8373_sds_id_e +{ + SERDES_ID0=0, + SERDES_ID1=1, + SERDES_IDEND +}rtl8373_sds_id_t; +void delay_loop(rtk_uint32 loop); + + +void Pin_Reset_8224_via_8373(void); + + +void uc1_sram_write_8b(rtk_uint32 port,rtk_uint32 addr,rtk_uint32 val); + +rtk_uint32 uc1_sram_read_8b(rtk_uint32 port,rtk_uint32 addr); + +void uc2_sram_write_8b(rtk_uint32 port,rtk_uint32 addr,rtk_uint32 val); + +rtk_uint32 uc2_sram_read_8b(rtk_uint32 port,rtk_uint32 addr); + +void data_ram_write_8b (rtk_uint32 port, rtk_uint32 addr,rtk_uint32 val); + +void n0_patch_RL6818B_220912 (rtk_uint32 phymask); + +void n2_tp3_patch_6818B_220812 (rtk_uint32 phymask); + + +void uc2_patch_6818B_220627 (rtk_uint32 phymask); + +void uc_patch_6818B_20221211(rtk_uint32 phymask); + +void rtct_para_6818B_221211(rtk_uint32 phymask); + +void n2_patch_6818C_221026 (rtk_uint32 phymask); + +void uc_patch_6818C_221117 (rtk_uint32 phymask); + +void data_ram_patch_6818C_221026(rtk_uint32 phymask); + +void RTCT_para_6818C_221118(rtk_uint32 phymask); + +void data_ram_patch_6818B_220714(rtk_uint32 phymask); + +void alg_tune_2p5G_6818B_220701 (rtk_uint32 phymask); + + +void alg_tune_giga_6818B_220617(rtk_uint32 phymask); + + +void afe_patch_6818B_220607(rtk_uint32 phymask); + +void rtct_para_6818B_220713(rtk_uint16 phymask); + + +rtk_api_ret_t SDS_MODE_SET_SW(rtk_uint32 CHIP_MODE, rtk_uint32 SDS_INDX ,rtk_uint32 SDS_MODE); + + +void get_version_8373(void); + +void get_version_8224(void); + +void get_version_8366u(void); + + +void afe_patch_6818_220325(void); + +void afe_patch_6818C_220607(rtk_uint16 phymask); + +void RL6818C_pwr_on_patch_phy_v004_rls_lockmain(rtk_uint32 phymask); + +void RL6818C_pwr_on_patch_phy_v004(rtk_uint32 phymask); + + + + +void alg_tune_fnet_6818_220628(rtk_uint32 phymask); + +void n0_patch_RL6818B_221012 (rtk_uint32 phymask); + +void uc_patch_6818B_20220927(rtk_uint32 phymask); + +void RL6818B_pwr_on_patch_phy_v006_rls_lockmain(rtk_uint32 phymask); + +void RL6818B_pwr_on_patch_phy_v006(rtk_uint32 phymask); + +void n0_patch_RL6818C_230424 (rtk_uint32 phymask); + +void n2_patch_6818C_230410 (rtk_uint32 phymask); + +void uc_patch_6818C_221012 (rtk_uint32 phymask); + + +void RL6818B_pwr_on_patch_phy_v004a_rls_lockmain(rtk_uint32 phymask); + + +void RL6818B_pwr_on_patch_phy_v004a(rtk_uint32 phymask); + +void cfg_rl6637_sds_mode(rtk_uint32 phyId,rtk_uint32 sds_mode); + + +void fw_reset_flow_tgx(rtk_uint32 sds); + +rtk_api_ret_t rtl8373_8224_init(void); +rtk_api_ret_t rtl8372_init(void); +rtk_api_ret_t rtl8372n_init(void); +rtk_api_ret_t rtl8366u_init(void); +rtk_api_ret_t rtl8373N_8224N_init(void); +void Pin_Reset_8224N_via_8373N(void); + + +/* + * Data Declaration + */ + +/* + * Function Declaration + */ + +/* Module Name : Switch */ +/* Sub-module Name: Switch parameter settings */ + +/* Function Name: + * dal_rtl8373_switch_init + * Description: + * Initialize switch module of the specified device. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * Note: + * Module must be initialized before using all of APIs in this module + */ +extern rtk_api_ret_t +dal_rtl8373_switch_init(void); + +/* Module Name : Switch */ +/* Sub-module Name: Switch parameter settings */ +/* Function Name: + * dal_rtl8373_switch_portMaxPktLen_set + * Description: + * Set Max packet length + * Input: + * port - Port ID + * speed - Speed + * cfgId - Configuration ID + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + */ +extern rtk_api_ret_t +dal_rtl8373_switch_portMaxPktLen_set(rtk_port_t port, rtk_switch_maxPktLen_linkSpeed_t speed, rtk_uint32 cfgId); + +/* Function Name: + * dal_rtl8373_switch_portMaxPktLen_get + * Description: + * Get Max packet length + * Input: + * port - Port ID + * speed - Speed + * Output: + * pCfgId - Configuration ID + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + */ +extern rtk_api_ret_t +dal_rtl8373_switch_portMaxPktLen_get(rtk_port_t port, rtk_switch_maxPktLen_linkSpeed_t speed, rtk_uint32 *pCfgId); + +/* Function Name: + * dal_rtl8373_switch_maxPktLenCfg_set + * Description: + * Set Max packet length configuration + * Input: + * cfgId - Configuration ID + * pktLen - Max packet length + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + */ +extern rtk_api_ret_t +dal_rtl8373_switch_maxPktLenCfg_set(rtk_uint32 cfgId, rtk_uint32 pktLen); + +/* Function Name: + * dal_rtl8373_switch_maxPktLenCfg_get + * Description: + * Get Max packet length configuration + * Input: + * cfgId - Configuration ID + * pPktLen - Max packet length + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + */ +extern rtk_api_ret_t +dal_rtl8373_switch_maxPktLenCfg_get(rtk_uint32 cfgId, rtk_uint32 *pPktLen); + +/* Function Name: + * dal_rtl8373_switch_greenEthernet_set + * Description: + * Set all Ports Green Ethernet state. + * Input: + * enable - Green Ethernet state. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * This API can set all Ports Green Ethernet state. + * The configuration is as following: + * - DISABLE + * - ENABLE + */ +extern rtk_api_ret_t +dal_rtl8373_switch_greenEthernet_set(rtk_enable_t enable); + +/* Function Name: + * dal_rtl8373_switch_greenEthernet_get + * Description: + * Get all Ports Green Ethernet state. + * Input: + * None + * Output: + * pEnable - Green Ethernet state. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API can get Green Ethernet state. + */ +extern rtk_api_ret_t +dal_rtl8373_switch_greenEthernet_get(rtk_enable_t *pEnable); + + +extern void fiber_fc_en (rtk_uint32 SDS_INDX ,rtk_uint32 SDS_MODE, rtk_uint32 fc_en); + +extern void sds_nway_set (rtk_uint32 SDS_INDX ,rtk_uint32 SDS_MODE, rtk_uint32 an_en); + +extern rtk_api_ret_t serdes_patch (rtk_uint32 CHIP_MODE, rtk_uint32 SDS_INDX ,rtk_uint32 SDS_MODE); + +extern rtk_api_ret_t fw_reset_flow_tgr(rtk_uint32 sdsid); + +extern void fw_reset_flow_tgx(rtk_uint32 sds); + +extern rtk_api_ret_t SDS_MODE_SET_SW(rtk_uint32 CHIP_MODE, rtk_uint32 SDS_INDX ,rtk_uint32 SDS_MODE); + +extern rtk_api_ret_t fw_reset_flow_tgr_8224(rtk_uint32 sdsid); + +#endif /* __DAL_RTL8373_SWITCH_H__ */ diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_trunk.c b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_trunk.c new file mode 100755 index 00000000..839e0991 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_trunk.c @@ -0,0 +1,396 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8373 + * Feature : Here is a list of all functions and variables in TRUNK module. + * + */ + +#include +#include +#include +#include +#include + + + +/* Function Name: + * dal_rtl8373_trunk_port_set + * Description: + * Set trunking group available port mask + * Input: + * trk_gid - trunk group id + * pTrunk_member_portmask - Logic trunking member port mask + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_LA_TRUNK_ID - Invalid trunking group + * RT_ERR_PORT_MASK - Invalid portmask. + * Note: + * The API can set port trunking group port mask. Each port trunking group has max 4 ports. + * If enabled port mask has less than 2 ports available setting, then this trunking group function is disabled. + */ +rtk_api_ret_t dal_rtl8373_trunk_port_set(rtk_trunk_group_t trk_gid, rtk_portmask_t *pTrunk_member_portmask) +{ + rtk_api_ret_t retVal; + rtk_uint32 pmsk; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Trunk Group Valid */ + RTK_CHK_TRUNK_GROUP_VALID(trk_gid); + + if(NULL == pTrunk_member_portmask) + return RT_ERR_NULL_POINTER; + + RTK_CHK_PORTMASK_VALID(pTrunk_member_portmask); + + if((retVal = rtk_switch_portmask_L2P_get(pTrunk_member_portmask, &pmsk)) != RT_ERR_OK) + return retVal; + + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_TRK_MBR_CTRL_ADDR(trk_gid), RTL8373_TRK_MBR_CTRL_TRK_PMSK_MASK, pmsk)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + + +/* Function Name: + * dal_rtl8373_trunk_port_get + * Description: + * Get trunking group available port mask + * Input: + * trk_gid - trunk group id + * Output: + * pTrunk_member_portmask - Logic trunking member port mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_LA_TRUNK_ID - Invalid trunking group + * Note: + * The API can get 2 port trunking group. + */ +rtk_api_ret_t dal_rtl8373_trunk_port_get(rtk_trunk_group_t trk_gid, rtk_portmask_t *pTrunk_member_portmask) +{ + rtk_api_ret_t retVal; + rtk_uint32 pmsk; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Trunk Group Valid */ + RTK_CHK_TRUNK_GROUP_VALID(trk_gid); + + if ((retVal = rtl8373_getAsicRegBits(RTL8373_TRK_MBR_CTRL_ADDR(trk_gid), RTL8373_TRK_MBR_CTRL_TRK_PMSK_MASK, &pmsk)) != RT_ERR_OK) + return retVal; + + + if((retVal = rtk_switch_portmask_P2L_get(pmsk, pTrunk_member_portmask)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_trunk_distributionAlgorithm_set + * Description: + * Set port trunking hash select sources + * Input: + * trk_gid - trunk group id + * algo_bitmask - Bitmask of the distribution algorithm + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_LA_TRUNK_ID - Invalid trunking group + * RT_ERR_LA_HASHMASK - Hash algorithm selection error. + * RT_ERR_PORT_MASK - Invalid portmask. + * Note: + * The API can set port trunking hash algorithm sources. + * 7 bits mask for link aggregation group0 hash parameter selection {DIP, SIP, DMAC, SMAC, SPA} + * - 0b0000001: SPA + * - 0b0000010: SMAC + * - 0b0000100: DMAC + * - 0b0001000: SIP + * - 0b0010000: DIP + * - 0b0100000: TCP/UDP Source Port + * - 0b1000000: TCP/UDP Destination Port + * Example: + * - 0b0000011: SMAC & SPA + * - Note that it could be an arbitrary combination or independent set + */ +rtk_api_ret_t dal_rtl8373_trunk_distributionAlgorithm_set(rtk_trunk_group_t trk_gid, rtk_uint32 algo_bitmask) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Trunk Group Valid */ + RTK_CHK_TRUNK_GROUP_VALID(trk_gid); + + if (algo_bitmask >= 128) + return RT_ERR_LA_HASHMASK; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_TRK_HASH_CTRL_ADDR(trk_gid), RTL8373_TRK_HASH_CTRL_HASH_MSK_MASK, algo_bitmask)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_trunk_distributionAlgorithm_get + * Description: + * Get port trunking hash select sources + * Input: + * trk_gid - trunk group id + * Output: + * pAlgo_bitmask - Bitmask of the distribution algorithm + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_LA_TRUNK_ID - Invalid trunking group + * Note: + * The API can get port trunking hash algorithm sources. + */ +rtk_api_ret_t dal_rtl8373_trunk_distributionAlgorithm_get(rtk_trunk_group_t trk_gid, rtk_uint32 *pAlgo_bitmask) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Trunk Group Valid */ + RTK_CHK_TRUNK_GROUP_VALID(trk_gid); + + if(NULL == pAlgo_bitmask) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8373_getAsicRegBits(RTL8373_TRK_HASH_CTRL_ADDR(trk_gid), RTL8373_TRK_HASH_CTRL_HASH_MSK_MASK, pAlgo_bitmask)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + + +/* Function Name: + * dal_rtl8373_trunk_trafficSeparate_set + * Description: + * Set the traffic separation setting of a trunk group from the specified device. + * Input: + * trk_gid - trunk group id + * separateType - traffic separation setting + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_LA_TRUNK_ID - invalid trunk ID + * RT_ERR_LA_HASHMASK - invalid hash mask + * Note: + * SEPARATE_NONE: disable traffic separation + * SEPARATE_FLOOD: trunk MSB link up port is dedicated to TX flooding (L2 lookup miss) traffic + */ +rtk_api_ret_t dal_rtl8373_trunk_trafficSeparate_set(rtk_trunk_group_t trk_gid, rtk_trunk_separateType_t separateType) +{ + rtk_api_ret_t retVal; + rtk_uint32 enabled; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(trk_gid >= TRUNK_GROUP_END) + return RT_ERR_INPUT; + + if(separateType >= SEPARATE_END) + return RT_ERR_INPUT; + + enabled = (separateType == SEPARATE_FLOOD) ? ENABLED : DISABLED; + + if ((retVal = rtl8373_setAsicRegBit(RTL8373_TRK_CTRL_ADDR, RTL8373_TRK_CTRL_TRUNK_FLD_OFFSET, enabled)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_trunk_trafficSeparate_get + * Description: + * Get the traffic separation setting of a trunk group from the specified device. + * Input: + * trk_gid - trunk group id + * Output: + * pSeparateType - pointer separated traffic type + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_LA_TRUNK_ID - invalid trunk ID + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * SEPARATE_NONE: disable traffic separation + * SEPARATE_FLOOD: trunk MSB link up port is dedicated to TX flooding (L2 lookup miss) traffic + */ +rtk_api_ret_t dal_rtl8373_trunk_trafficSeparate_get(rtk_trunk_group_t trk_gid, rtk_trunk_separateType_t *pSeparateType) +{ + rtk_api_ret_t retVal; + rtk_uint32 enabled; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(trk_gid >= TRUNK_GROUP_END) + return RT_ERR_INPUT; + + if(NULL == pSeparateType) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8373_getAsicRegBit(RTL8373_TRK_CTRL_ADDR, RTL8373_TRK_CTRL_TRUNK_FLD_OFFSET, &enabled)) != RT_ERR_OK) + return retVal; + + *pSeparateType = (enabled == ENABLED) ? SEPARATE_FLOOD : SEPARATE_NONE; + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_trunk_trafficPause_set + * Description: + * Set the traffic pause setting of a trunk group. + * Input: + * trk_gid - trunk group id + * enable - traffic pause state + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_LA_TRUNK_ID - invalid trunk ID + * Note: + * None. + */ +rtk_api_ret_t dal_rtl8373_trunk_trafficPause_set(rtk_trunk_group_t trk_gid, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Trunk Group Valid */ + RTK_CHK_TRUNK_GROUP_VALID(trk_gid); + + if(enable >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if((retVal = rtl8373_setAsicRegBit(RTL8373_TRK_FLOW_CTRL_ADDR(trk_gid), RTL8373_TRK_FLOW_CTRL_TRK_FLCTRL_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_trunk_trafficPause_get + * Description: + * Get the traffic pause setting of a trunk group. + * Input: + * trk_gid - trunk group id + * Output: + * pEnable - pointer of traffic pause state. + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_LA_TRUNK_ID - invalid trunk ID + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None. + */ +rtk_api_ret_t dal_rtl8373_trunk_trafficPause_get(rtk_trunk_group_t trk_gid, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Trunk Group Valid */ + RTK_CHK_TRUNK_GROUP_VALID(trk_gid); + + if(NULL == pEnable) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8373_getAsicRegBit(RTL8373_TRK_FLOW_CTRL_ADDR(trk_gid), RTL8373_TRK_FLOW_CTRL_TRK_FLCTRL_EN_OFFSET, pEnable)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_trunk_portQueueEmpty_get + * Description: + * Get the port mask which all queues are empty. + * Input: + * None. + * Output: + * pEmpty_portmask - pointer empty port mask + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None. + */ +rtk_api_ret_t dal_rtl8373_trunk_portQueueEmpty_get(rtk_portmask_t *pEmpty_portmask) +{ + rtk_api_ret_t retVal; + rtk_uint32 pmask; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pEmpty_portmask) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8373_getAsicReg(RTL8373_TRK_QUEUE_EMPTY_ADDR, &pmask)) != RT_ERR_OK) + return retVal; + + if ((retVal = rtk_switch_portmask_P2L_get(pmask, pEmpty_portmask)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + + + + + + + + diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_trunk.h b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_trunk.h new file mode 100755 index 00000000..8689520a --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_trunk.h @@ -0,0 +1,196 @@ +#ifndef __DAL_RTL8373_TRUNK_H__ +#define __DAL_RTL8373_TRUNK_H__ + +#include "trunk.h" + + +/* Function Name: + * dal_rtl8373_trunk_port_set + * Description: + * Set trunking group available port mask + * Input: + * trk_gid - trunk group id + * pTrunk_member_portmask - Logic trunking member port mask + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_LA_TRUNK_ID - Invalid trunking group + * RT_ERR_PORT_MASK - Invalid portmask. + * Note: + * The API can set port trunking group port mask. Each port trunking group has max 4 ports. + * If enabled port mask has less than 2 ports available setting, then this trunking group function is disabled. + */ +extern rtk_api_ret_t dal_rtl8373_trunk_port_set(rtk_trunk_group_t trk_gid, rtk_portmask_t *pTrunk_member_portmask); + + + +/* Function Name: + * dal_rtl8373_trunk_port_get + * Description: + * Get trunking group available port mask + * Input: + * trk_gid - trunk group id + * Output: + * pTrunk_member_portmask - Logic trunking member port mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_LA_TRUNK_ID - Invalid trunking group + * Note: + * The API can get 2 port trunking group. + */ +extern rtk_api_ret_t dal_rtl8373_trunk_port_get(rtk_trunk_group_t trk_gid, rtk_portmask_t *pTrunk_member_portmask); + + +/* Function Name: + * dal_rtl8373_trunk_distributionAlgorithm_set + * Description: + * Set port trunking hash select sources + * Input: + * trk_gid - trunk group id + * algo_bitmask - Bitmask of the distribution algorithm + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_LA_TRUNK_ID - Invalid trunking group + * RT_ERR_LA_HASHMASK - Hash algorithm selection error. + * RT_ERR_PORT_MASK - Invalid portmask. + * Note: + * The API can set port trunking hash algorithm sources. + * 7 bits mask for link aggregation group0 hash parameter selection {DIP, SIP, DMAC, SMAC, SPA} + * - 0b0000001: SPA + * - 0b0000010: SMAC + * - 0b0000100: DMAC + * - 0b0001000: SIP + * - 0b0010000: DIP + * - 0b0100000: TCP/UDP Source Port + * - 0b1000000: TCP/UDP Destination Port + * Example: + * - 0b0000011: SMAC & SPA + * - Note that it could be an arbitrary combination or independent set + */ +extern rtk_api_ret_t dal_rtl8373_trunk_distributionAlgorithm_set(rtk_trunk_group_t trk_gid, rtk_uint32 algo_bitmask); + + +/* Function Name: + * dal_rtl8373_trunk_distributionAlgorithm_get + * Description: + * Get port trunking hash select sources + * Input: + * trk_gid - trunk group id + * Output: + * pAlgo_bitmask - Bitmask of the distribution algorithm + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_LA_TRUNK_ID - Invalid trunking group + * Note: + * The API can get port trunking hash algorithm sources. + */ +extern rtk_api_ret_t dal_rtl8373_trunk_distributionAlgorithm_get(rtk_trunk_group_t trk_gid, rtk_uint32 *pAlgo_bitmask); + + +/* Function Name: + * dal_rtl8373_trunk_trafficSeparate_set + * Description: + * Set the traffic separation setting of a trunk group from the specified device. + * Input: + * trk_gid - trunk group id + * separateType - traffic separation setting + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_LA_TRUNK_ID - invalid trunk ID + * RT_ERR_LA_HASHMASK - invalid hash mask + * Note: + * SEPARATE_NONE: disable traffic separation + * SEPARATE_FLOOD: trunk MSB link up port is dedicated to TX flooding (L2 lookup miss) traffic + */ +extern rtk_api_ret_t dal_rtl8373_trunk_trafficSeparate_set(rtk_trunk_group_t trk_gid, rtk_trunk_separateType_t separateType); + +/* Function Name: + * dal_rtl8373_trunk_trafficSeparate_get + * Description: + * Get the traffic separation setting of a trunk group from the specified device. + * Input: + * trk_gid - trunk group id + * Output: + * pSeparateType - pointer separated traffic type + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_LA_TRUNK_ID - invalid trunk ID + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * SEPARATE_NONE: disable traffic separation + * SEPARATE_FLOOD: trunk MSB link up port is dedicated to TX flooding (L2 lookup miss) traffic + */ +extern rtk_api_ret_t dal_rtl8373_trunk_trafficSeparate_get(rtk_trunk_group_t trk_gid, rtk_trunk_separateType_t *pSeparateType); + + +/* Function Name: + * dal_rtl8373_trunk_portQueueEmpty_get + * Description: + * Get the port mask which all queues are empty. + * Input: + * None. + * Output: + * pEmpty_portmask - pointer empty port mask + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None. + */ +extern rtk_api_ret_t dal_rtl8373_trunk_portQueueEmpty_get(rtk_portmask_t *pEmpty_portmask); + +/* Function Name: + * dal_rtl8373_trunk_trafficPause_set + * Description: + * Set the traffic pause setting of a trunk group. + * Input: + * trk_gid - trunk group id + * enable - traffic pause state + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_LA_TRUNK_ID - invalid trunk ID + * Note: + * None. + */ +extern rtk_api_ret_t dal_rtl8373_trunk_trafficPause_set(rtk_trunk_group_t trk_gid, rtk_enable_t enable); + +/* Function Name: + * dal_rtl8373_trunk_trafficPause_get + * Description: + * Get the traffic pause setting of a trunk group. + * Input: + * trk_gid - trunk group id + * Output: + * pEnable - pointer of traffic pause state. + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_LA_TRUNK_ID - invalid trunk ID + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None. + */ +extern rtk_api_ret_t dal_rtl8373_trunk_trafficPause_get(rtk_trunk_group_t trk_gid, rtk_enable_t *pEnable); + +#endif \ No newline at end of file diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_vlan.c b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_vlan.c new file mode 100755 index 00000000..58ce229d --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_vlan.c @@ -0,0 +1,1424 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8373 + * Feature : Here is a list of all functions and variables in VLAN module. + * + */ + +#include +#include +#include +#include +#include + + +#if defined(CONFIG_RTL8373_ASICDRV_TEST) +dal_rtl8373_user_vlan4kentry Rtl8371cVirtualVlanTable[RTL8373_VIDMAX + 1]; +#endif + +static void _dal_rtl8373_Vlan4kStUser2Smi(dal_rtl8373_user_vlan4kentry *pUserVlan4kEntry, rtk_uint32 *pSmiVlan4kEntry) +{ + rtk_uint32 regValue = 0; + regValue |= (pUserVlan4kEntry->mbr & 0x3FF); + regValue |= (pUserVlan4kEntry->untag & 0x3FF) << 10; + regValue |= (pUserVlan4kEntry->fid_msti & 0xF) << 20; + regValue |= (pUserVlan4kEntry->svlan_chk_ivl_svl & 0x1) << 24; + regValue |= (pUserVlan4kEntry->ivl_svl & 0x1) << 25; + + *pSmiVlan4kEntry = regValue; +} + +static void _dal_rtl8373_Vlan4kStSmi2User(rtk_uint32 smiVlan4kEntry, dal_rtl8373_user_vlan4kentry *pUserVlan4kEntry) +{ + pUserVlan4kEntry->mbr = (rtk_uint16) (smiVlan4kEntry& 0x3FF); + pUserVlan4kEntry->untag = (rtk_uint16) ((smiVlan4kEntry >> 10) & 0x3FF); + pUserVlan4kEntry->fid_msti = (rtk_uint16) ((smiVlan4kEntry >> 20) & 0xF); + pUserVlan4kEntry->svlan_chk_ivl_svl = (rtk_uint16) ((smiVlan4kEntry >> 24) & 0x1) ; + pUserVlan4kEntry->ivl_svl = (rtk_uint16) ((smiVlan4kEntry >> 25) & 0x1) ; +} + +ret_t _dal_rtl8373_setAsicVlan4kEntry(dal_rtl8373_user_vlan4kentry *pVlan4kEntry ) +{ + rtk_uint32 vlanEntryVal = 0; + rtk_uint32 retVal = 0; + rtk_uint32 regData = 0; + + if(pVlan4kEntry->vid > RTL8373_VIDMAX) + return RT_ERR_VLAN_VID; + + if(pVlan4kEntry->mbr > RTL8373_PORTMASK) + return RT_ERR_PORT_MASK; + + if(pVlan4kEntry->untag > RTL8373_PORTMASK) + return RT_ERR_PORT_MASK; + + if(pVlan4kEntry->fid_msti > RTL8373_FIDMAX) + return RT_ERR_L2_FID; + + if(pVlan4kEntry->ivl_svl> RTK_ENABLE_END) + return RT_ERR_INPUT; + + if(pVlan4kEntry->svlan_chk_ivl_svl> RTK_ENABLE_END) + return RT_ERR_INPUT; + + /* Prepare Data */ + _dal_rtl8373_Vlan4kStUser2Smi(pVlan4kEntry, &vlanEntryVal); + + retVal = rtl8373_setAsicReg(RTL8373_ITA_WRITE_DATA0_ADDR (0), vlanEntryVal); + if(retVal != RT_ERR_OK) + return retVal; + + /*write control word*/ + regData = (pVlan4kEntry->vid) << RTL8373_ITA_CTRL0_TBL_ADDR_OFFSET; + regData |= (TB_TARGET_CVLAN << RTL8373_ITA_CTRL0_TLB_TYPE_OFFSET); + regData |= (TB_OP_WRITE << RTL8373_ITA_CTRL0_TLB_ACT_OFFSET); + regData |= (TB_EXECUTE << RTL8373_ITA_CTRL0_TLB_EXECUTE_OFFSET); + #if 0 + /* Write Address (VLAN_ID) */ + regData = pVlan4kEntry->vid; + regAddr = RTL8373_ITA_CTRL0_ADDR; + retVal = rtl8373_setAsicRegBits(regAddr,RTL8373_ITA_CTRL0_TBL_ADDR_OFFSET, regData); + if(retVal != RT_ERR_OK) + return retVal; + + /* Write Command */ + /* Write ACS_CMD register */ + retVal = rtl8373_setAsicRegBit(regAddr, RTL8373_ITA_CTRL0_TLB_ACT_OFFSET, TB_OP_WRITE); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8373_setAsicRegBits(regAddr, RTL8373_ITA_CTRL0_TLB_TYPE_MASK, TB_TARGET_CVLAN); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8373_setAsicRegBit(regAddr, RTL8373_ITA_CTRL0_TLB_EXECUTE_OFFSET , TB_EXECUTE); + if(retVal != RT_ERR_OK) + return retVal; +#endif + retVal = rtl8373_setAsicReg(RTL8373_ITA_CTRL0_ADDR, regData); + if(retVal != RT_ERR_OK) + return retVal; + + + /*wait access finished */ + do{ + retVal = rtl8373_getAsicReg(RTL8373_ITA_CTRL0_ADDR, ®Data); + if(retVal != RT_ERR_OK) + return retVal; + }while(regData & 0x1); + +#if defined(CONFIG_RTL8373_ASICDRV_TEST) + memcpy(&Rtl8367dVirtualVlanTable[pVlan4kEntry->vid], pVlan4kEntry, sizeof(dal_rtl8373_user_vlan4kentry)); +#endif + + return RT_ERR_OK; +} + + +ret_t _dal_rtl8373_getAsicVlan4kEntry(dal_rtl8373_user_vlan4kentry *pVlan4kEntry ) +{ + rtk_uint32 retVal = 0; + rtk_uint32 regData = 0; + rtk_uint32 regAddr = 0; + rtk_uint32 busyCounter = 0; + + if(pVlan4kEntry->vid > RTL8373_VIDMAX) + return RT_ERR_VLAN_VID; + + /* Polling status */ + busyCounter = RTL8373_VLAN_BUSY_CHECK_NO; + regAddr = RTL8373_ITA_CTRL0_ADDR; + do{ + retVal = rtl8373_getAsicRegBit(regAddr, RTL8373_ITA_CTRL0_TLB_EXECUTE_OFFSET , ®Data); + if(retVal != RT_ERR_OK) + return retVal; + busyCounter --; + if(busyCounter == 0) + return RT_ERR_BUSYWAIT_TIMEOUT; + + }while(regData); + + /* Write Address (VLAN_ID) */ + regAddr = RTL8373_ITA_CTRL0_ADDR; + regData = pVlan4kEntry->vid; + retVal = rtl8373_setAsicRegBits(regAddr, RTL8373_ITA_CTRL0_TBL_ADDR_MASK, regData); + if(retVal != RT_ERR_OK) + return retVal; + + /* Read Command */ + /* Write ACS_CMD register */ + retVal = rtl8373_setAsicRegBit(regAddr, RTL8373_ITA_CTRL0_TLB_ACT_OFFSET, TB_OP_READ); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8373_setAsicRegBits(regAddr, RTL8373_ITA_CTRL0_TLB_TYPE_MASK, TB_TARGET_CVLAN); + if(retVal != RT_ERR_OK) + return retVal; + + retVal = rtl8373_setAsicRegBit(regAddr, RTL8373_ITA_CTRL0_TLB_EXECUTE_OFFSET , TB_EXECUTE); + if(retVal != RT_ERR_OK) + return retVal; + + /*wait access finished */ + busyCounter = RTL8373_VLAN_BUSY_CHECK_NO; + do{ + retVal = rtl8373_getAsicRegBit(regAddr, RTL8373_ITA_CTRL0_TLB_EXECUTE_OFFSET , ®Data); + if(retVal != RT_ERR_OK) + return retVal; + busyCounter --; + if(busyCounter == 0) + return RT_ERR_BUSYWAIT_TIMEOUT; + }while(regData); + + /* Read VLAN data from register */ + retVal = rtl8373_getAsicReg(RTL8373_ITA_READ_DATA0_ADDR(0) , ®Data); + if(retVal != RT_ERR_OK) + return retVal; + + _dal_rtl8373_Vlan4kStSmi2User(regData, pVlan4kEntry); + + +#if defined(CONFIG_RTL8373_ASICDRV_TEST) + memcpy(pVlan4kEntry, &Rtl8367dVirtualVlanTable[pVlan4kEntry->vid], sizeof(dal_rtl8373_user_vlan4kentry)); +#endif + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_vlan_init + * Description: + * Initialize VLAN. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * VLAN is disabled by default. User has to call this API to enable VLAN before + * using it. And It will set a default VLAN(vid 1) including all ports and set + * all ports PVID to the default VLAN. + */ +rtk_api_ret_t dal_rtl8373_vlan_init(void) +{ + rtk_api_ret_t retVal = 0; + rtk_uint32 idx = 0; + dal_rtl8373_user_vlan4kentry vlan4K; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Set a default VLAN with vid 1 to 4K table for all ports */ + memset(&vlan4K, 0, sizeof(dal_rtl8373_user_vlan4kentry)); + vlan4K.vid = 1; + vlan4K.mbr = RTK_PHY_PORTMASK_ALL; + vlan4K.untag = RTK_PHY_PORTMASK_ALL; + vlan4K.fid_msti = 0; + if ((retVal = _dal_rtl8373_setAsicVlan4kEntry(&vlan4K)) != RT_ERR_OK) + return retVal; + + /* Set all ports PVID to default VLAN and tag-mode to original */ + RTK_SCAN_ALL_LOG_PORT(idx) + { + if ((retVal = dal_rtl8373_vlan_portPvid_set(idx, 1)) != RT_ERR_OK) + return retVal; + if ((retVal = dal_rtl8373_vlan_tagMode_set(idx, VLAN_EGRESS_TAG_MODE_ORIGINAL)) != RT_ERR_OK) + return retVal; + } + + /* Enable Ingress filter */ + for(idx = 0; idx < RTK_MAX_NUM_OF_PORT; idx++) + { + if ((retVal = dal_rtl8373_vlan_portIgrFilterEnable_set(idx, ENABLED)) != RT_ERR_OK) + return retVal; + } + + /* enable VLAN egress filter */ + if ((retVal = dal_rtl8373_vlan_egrFilterEnable_set(ENABLED)) != RT_ERR_OK) + return retVal; + + /*invalid all L2 disable learning table*/ + if((retVal = rtl8373_setAsicReg(RTL8373_VLAN_L2_LRN_DIS_ADDR(0),0)) != RT_ERR_OK) + return retVal; + if((retVal = rtl8373_setAsicReg(RTL8373_VLAN_L2_LRN_DIS_ADDR(1),0)) != RT_ERR_OK) + return retVal; + + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_vlan_set + * Description: + * Set a VLAN entry. + * Input: + * vid - VLAN ID to configure. + * pVlanCfg - VLAN Configuration + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_L2_FID - Invalid FID. + * RT_ERR_VLAN_PORT_MBR_EXIST - Invalid member port mask. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * Note: + * + */ +rtk_api_ret_t dal_rtl8373_vlan_set(rtk_vlan_t vid, rtk_vlan_entry_t *pVlanCfg) +{ + rtk_api_ret_t retVal = 0; + dal_rtl8373_user_vlan4kentry vlan4K; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* vid must be 0~4095 */ + if (vid > RTL8373_VIDMAX) + return RT_ERR_VLAN_VID; + + /* Null pointer check */ + if(NULL == pVlanCfg) + return RT_ERR_NULL_POINTER; + + memset(&vlan4K, 0, sizeof(dal_rtl8373_user_vlan4kentry)); + + /* Check port mask valid */ + RTK_CHK_PORTMASK_VALID(&pVlanCfg->mbr); + + /* Check untag port mask valid */ + RTK_CHK_PORTMASK_VALID(&pVlanCfg->untag); + + /* fid must be 0~15 */ + if(pVlanCfg->fid_msti > RTL8373_FIDMAX) + return RT_ERR_L2_FID; + + /* svlan_chk_svl_ivl*/ + if(pVlanCfg->svlan_chk_ivl_svl > 1) + return RT_ERR_INPUT; + + /*svl_ivl*/ + if(pVlanCfg->ivl_svl > 1) + return RT_ERR_INPUT; + + + + /* update 4K table */ + memset(&vlan4K, 0, sizeof(dal_rtl8373_user_vlan4kentry)); + vlan4K.vid = vid; + + vlan4K.mbr = (pVlanCfg->mbr.bits[0]) & RTK_MAX_PORT_MASK; + vlan4K.untag = (pVlanCfg->untag.bits[0]) & RTK_MAX_PORT_MASK; + + vlan4K.svlan_chk_ivl_svl = pVlanCfg->svlan_chk_ivl_svl; + vlan4K.ivl_svl = pVlanCfg->ivl_svl; + vlan4K.fid_msti = pVlanCfg->fid_msti; + + if ((retVal = _dal_rtl8373_setAsicVlan4kEntry(&vlan4K)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_vlan_get + * Description: + * Get a VLAN entry. + * Input: + * vid - VLAN ID to configure. + * Output: + * pVlanCfg - VLAN Configuration + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * Note: + * + */ +rtk_api_ret_t dal_rtl8373_vlan_get(rtk_vlan_t vid, rtk_vlan_entry_t *pVlanCfg) +{ + rtk_api_ret_t retVal = 0; + dal_rtl8373_user_vlan4kentry vlan4K; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* vid must be 0~8191 */ + if (vid > RTL8373_VIDMAX) + return RT_ERR_VLAN_VID; + + /* Null pointer check */ + if(NULL == pVlanCfg) + return RT_ERR_NULL_POINTER; + + memset(&vlan4K, 0, sizeof(dal_rtl8373_user_vlan4kentry)); + vlan4K.vid = vid; + + if ((retVal = _dal_rtl8373_getAsicVlan4kEntry(&vlan4K)) != RT_ERR_OK) + return retVal; + + pVlanCfg->mbr.bits[0] = vlan4K.mbr; + pVlanCfg->untag.bits[0] = vlan4K.untag; + pVlanCfg->svlan_chk_ivl_svl = vlan4K.svlan_chk_ivl_svl; + pVlanCfg->ivl_svl = vlan4K.ivl_svl; + pVlanCfg->fid_msti = vlan4K.fid_msti; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_vlan_egrFilterEnable_set + * Description: + * Set VLAN egress filter. + * Input: + * egrFilter - Egress filtering + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid input parameters. + * Note: + * + */ +rtk_api_ret_t dal_rtl8373_vlan_egrFilterEnable_set(rtk_enable_t egrFilter) +{ + rtk_api_ret_t retVal = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(egrFilter >= RTK_ENABLE_END) + return RT_ERR_ENABLE; + + /* enable VLAN */ + if ((retVal = rtl8373_setAsicRegBit(RTL8373_VLAN_CTRL_ADDR, RTL8373_VLAN_CTRL_CVLAN_FILTER_OFFSET, egrFilter)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_vlan_egrFilterEnable_get + * Description: + * Get VLAN egress filter. + * Input: + * pEgrFilter - Egress filtering + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - NULL Pointer. + * Note: + * + */ +rtk_api_ret_t dal_rtl8373_vlan_egrFilterEnable_get(rtk_enable_t *pEgrFilter) +{ + rtk_api_ret_t retVal = 0; + rtk_uint32 state = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pEgrFilter) + return RT_ERR_NULL_POINTER; + + /* enable VLAN */ + if ((retVal = rtl8373_getAsicRegBit(RTL8373_VLAN_CTRL_ADDR, RTL8373_VLAN_CTRL_CVLAN_FILTER_OFFSET, &state)) != RT_ERR_OK) + return retVal; + + *pEgrFilter = (rtk_enable_t)state; + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_vlan_portPvid_set + * Description: + * Set port to specified VLAN ID(PVID). + * Input: + * port - Port id. + * pvid - Specified VLAN ID. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_VLAN_PRIORITY - Invalid priority. + * RT_ERR_VLAN_ENTRY_NOT_FOUND - VLAN entry not found. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * Note: + * The API is used for Port-based VLAN. The untagged frame received from the + * port will be classified to the specified VLAN and assigned to the specified priority. + */ +rtk_api_ret_t dal_rtl8373_vlan_portPvid_set(rtk_port_t port, rtk_vlan_t pvid) +{ + rtk_api_ret_t retVal = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + /* vid must be 0~8191 */ + if (pvid > RTL8373_VIDMAX) + return RT_ERR_VLAN_VID; + + /* priority */ + + retVal = rtl8373_setAsicRegBits(RTL8373_VLAN_PORT_PB_VLAN_ADDR(port), RTL8373_VLAN_PORT_PB_VLAN_PVID_MASK(port), pvid); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_vlan_portPvid_get + * Description: + * Get VLAN ID(PVID) on specified port. + * Input: + * port - Port id. + * Output: + * pPvid - Specified VLAN ID. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get the PVID and 802.1p priority for the PVID of Port-based VLAN. + */ +rtk_api_ret_t dal_rtl8373_vlan_portPvid_get(rtk_port_t port, rtk_vlan_t *pPvid) +{ + rtk_api_ret_t retVal = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if(NULL == pPvid) + return RT_ERR_NULL_POINTER; + + retVal = rtl8373_getAsicRegBits(RTL8373_VLAN_PORT_PB_VLAN_ADDR(port), RTL8373_VLAN_PORT_PB_VLAN_PVID_MASK(port), pPvid); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_vlan_portIgrFilterEnable_set + * Description: + * Set VLAN ingress for each port. + * Input: + * port - Port id. + * igrFilter - VLAN ingress function enable status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * RT_ERR_ENABLE - Invalid enable input + * Note: + * The status of vlan ingress filter is as following: + * - DISABLED + * - ENABLED + * While VLAN function is enabled, ASIC will decide VLAN ID for each received frame and get belonged member + * ports from VLAN table. If received port is not belonged to VLAN member ports, ASIC will drop received frame if VLAN ingress function is enabled. + */ +rtk_api_ret_t dal_rtl8373_vlan_portIgrFilterEnable_set(rtk_port_t port, rtk_enable_t igrFilter) +{ + rtk_api_ret_t retVal = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if (igrFilter >= RTK_ENABLE_END) + return RT_ERR_ENABLE; + + if ((retVal = rtl8373_setAsicRegBit(RTL8373_VLAN_PORT_IGR_FLTR_ADDR(port), RTL8373_VLAN_PORT_IGR_FLTR_IGR_FLTR_ACT_OFFSET(port), (rtk_uint32)igrFilter)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_vlan_portIgrFilterEnable_get + * Description: + * Get VLAN Ingress Filter + * Input: + * port - Port id. + * Output: + * pIgrFilter - VLAN ingress function enable status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can Get the VLAN ingress filter status. + * The status of vlan ingress filter is as following: + * - DISABLED + * - ENABLED + */ +rtk_api_ret_t dal_rtl8373_vlan_portIgrFilterEnable_get(rtk_port_t port, rtk_enable_t *pIgrFilter) +{ + rtk_api_ret_t retVal = 0; + rtk_uint32 regData = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if(NULL == pIgrFilter) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8373_getAsicRegBit(RTL8373_VLAN_PORT_IGR_FLTR_ADDR(port), RTL8373_VLAN_PORT_IGR_FLTR_IGR_FLTR_ACT_OFFSET(port), ®Data)) != RT_ERR_OK) + return retVal; + + *pIgrFilter = (rtk_enable_t)regData; + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_vlan_portAcceptFrameType_set + * Description: + * Set VLAN accept_frame_type + * Input: + * port - Port id. + * acceptFrameType - accept frame type + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_VLAN_ACCEPT_FRAME_TYPE - Invalid frame type. + * Note: + * The API is used for checking 802.1Q tagged frames. + * The accept frame type as following: + * - ACCEPT_FRAME_TYPE_ALL + * - ACCEPT_FRAME_TYPE_TAG_ONLY + * - ACCEPT_FRAME_TYPE_UNTAG_ONLY + */ +rtk_api_ret_t dal_rtl8373_vlan_portAcceptFrameType_set(rtk_port_t port, rtk_vlan_acceptFrameType_t acceptFrameType) +{ + rtk_api_ret_t retVal = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if (acceptFrameType >= ACCEPT_FRAME_TYPE_END) + return RT_ERR_VLAN_ACCEPT_FRAME_TYPE; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_VLAN_PORT_AFT_ADDR(port), RTL8373_VLAN_PORT_AFT_CTAG_ACCEPT_TYPE_MASK(port), acceptFrameType)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_vlan_portAcceptFrameType_get + * Description: + * Get VLAN accept_frame_type + * Input: + * port - Port id. + * Output: + * pAcceptFrameType - accept frame type + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can Get the VLAN ingress filter. + * The accept frame type as following: + * - ACCEPT_FRAME_TYPE_ALL + * - ACCEPT_FRAME_TYPE_TAG_ONLY + * - ACCEPT_FRAME_TYPE_UNTAG_ONLY + */ +rtk_api_ret_t dal_rtl8373_vlan_portAcceptFrameType_get(rtk_port_t port, rtk_vlan_acceptFrameType_t *pAcceptFrameType) +{ + rtk_api_ret_t retVal = 0; + rtk_uint32 regData = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if(NULL == pAcceptFrameType) + return RT_ERR_NULL_POINTER; + + if((retVal = rtl8373_getAsicRegBits( RTL8373_VLAN_PORT_AFT_ADDR(port), RTL8373_VLAN_PORT_AFT_CTAG_ACCEPT_TYPE_MASK(port) , ®Data)) != RT_ERR_OK) + return retVal; + + *pAcceptFrameType = (rtk_vlan_acceptFrameType_t)regData; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_vlan_tagMode_set + * Description: + * Set CVLAN egress tag mode + * Input: + * port - Port id. + * tagMode - The egress tag mode. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * The API can set Egress tag mode. There are 4 mode for egress tag: + * - VLAN_EGRESS_TAG_MODE_ORIGINAL, + * - VLAN_EGRESS_TAG_MODE_KEEP_FORMAT, + * - VLAN_EGRESS_TAG_MODE_PRI. + * - VLAN_EGRESS_TAG_MODE_REAL_KEEP, + */ +rtk_api_ret_t dal_rtl8373_vlan_tagMode_set(rtk_port_t port, rtk_vlan_egressTagMode_t tagMode) +{ + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if (tagMode >= VLAN_EGRESS_TAG_MODE_END) + return RT_ERR_PORT_ID; + + return rtl8373_setAsicRegBits(RTL8373_VLAN_PORT_EGR_TAG_ADDR(port), RTL8373_VLAN_PORT_EGR_TAG_MODE_MASK(port), tagMode); + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_vlan_tagMode_get + * Description: + * Get CVLAN egress tag mode + * Input: + * port - Port id. + * Output: + * pTagMode - The egress tag mode. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get Egress tag mode. There are 4 mode for egress tag: + * - VLAN_EGRESS_TAG_MODE_ORIGINAL, + * - VLAN_EGRESS_TAG_MODE_KEEP_FORMAT, + * - VLAN_EGRESS_TAG_MODE_PRI. + * - VLAN_EGRESS_TAG_MODE_REAL_KEEP, + */ +rtk_api_ret_t dal_rtl8373_vlan_tagMode_get(rtk_port_t port, rtk_vlan_egressTagMode_t *pTagMode) +{ + rtk_uint32 mode = 0; + rtk_api_ret_t retVal = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + RTK_CHK_PORT_VALID(port); + + if(NULL == pTagMode) + return RT_ERR_NULL_POINTER; + + retVal = rtl8373_getAsicRegBits(RTL8373_VLAN_PORT_EGR_TAG_ADDR(port), RTL8373_VLAN_PORT_EGR_TAG_MODE_MASK(port), &mode); + if(retVal != RT_ERR_OK) + return retVal; + + *pTagMode = (rtk_vlan_egressTagMode_t)mode; + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_vlan_portTransparent_set + * Description: + * Set VLAN transparent mode + * Input: + * egrPort - Egress Port id. + * pIgrPmsk - Ingress Port Mask. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * None. + */ +rtk_api_ret_t dal_rtl8373_vlan_portTransparent_set(rtk_port_t egrPort, rtk_portmask_t *pIgrPmsk) +{ + rtk_api_ret_t retVal = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + if(egrPort > RTL8373_PORTIDMAX) + return RT_ERR_PORT_ID; + + if(NULL == pIgrPmsk) + return RT_ERR_NULL_POINTER; + + if(pIgrPmsk->bits[0] > RTL8373_PORTMASK) + return RT_ERR_PORT_MASK; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_VLAN_PORT_EGR_TRANS_ADDR(egrPort), RTL8373_VLAN_PORT_EGR_TRANS_PMSK_MASK(egrPort), pIgrPmsk->bits[0])) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_vlan_portTransparent_get + * Description: + * Get VLAN transparent mode + * Input: + * egrPort - Egress Port id. + * Output: + * pIgrPmsk - Ingress Port Mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * None. + */ +rtk_api_ret_t dal_rtl8373_vlan_portTransparent_get(rtk_port_t egrPort, rtk_portmask_t *pIgrPmsk) +{ + rtk_api_ret_t retVal = 0; + rtk_uint32 pmask = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + if(egrPort > RTL8373_PORTIDMAX) + return RT_ERR_PORT_ID; + + if(NULL == pIgrPmsk) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8373_getAsicRegBits(RTL8373_VLAN_PORT_EGR_TRANS_ADDR(egrPort), RTL8373_VLAN_PORT_EGR_TRANS_PMSK_MASK(egrPort),&pmask)) != RT_ERR_OK) + return retVal; + + pIgrPmsk->bits[0] = pmask; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_vlan_keep_set + * Description: + * Set VLAN egress keep mode + * Input: + * egrPort - Egress Port id. + * pIgrPmsk - Ingress Port Mask. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * None. + */ +rtk_api_ret_t dal_rtl8373_vlan_keep_set(rtk_port_t egrPort, rtk_portmask_t *pIgrPmsk) +{ + rtk_api_ret_t retVal = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + if(egrPort > RTL8373_PORTIDMAX) + return RT_ERR_PORT_ID; + + if(NULL == pIgrPmsk) + return RT_ERR_NULL_POINTER; + + if(pIgrPmsk->bits[0] > RTL8373_PORTMASK) + return RT_ERR_PORT_MASK; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_VLAN_PORT_EGR_KEEP_ADDR(egrPort), RTL8373_VLAN_PORT_EGR_KEEP_PMSK_MASK(egrPort), pIgrPmsk->bits[0])) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_vlan_keep_get + * Description: + * Get VLAN egress keep mode + * Input: + * egrPort - Egress Port id. + * Output: + * pIgrPmsk - Ingress Port Mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * None. + */ +rtk_api_ret_t dal_rtl8373_vlan_keep_get(rtk_port_t egrPort, rtk_portmask_t *pIgrPmsk) +{ + rtk_api_ret_t retVal = 0; + rtk_uint32 pmask = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + if(egrPort > RTL8373_PORTIDMAX) + return RT_ERR_PORT_ID; + + if(NULL == pIgrPmsk) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8373_getAsicRegBits(RTL8373_VLAN_PORT_EGR_KEEP_ADDR(egrPort), RTL8373_VLAN_PORT_EGR_KEEP_PMSK_MASK(egrPort),&pmask)) != RT_ERR_OK) + return retVal; + + pIgrPmsk->bits[0] = pmask; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_vlan_stg_set + * Description: + * Set spanning tree group instance of the vlan to the specified device + * Input: + * vid - Specified VLAN ID. + * stg - spanning tree group instance. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_MSTI - Invalid msti parameter + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * Note: + * The API can set spanning tree group instance of the vlan to the specified device. + */ +rtk_api_ret_t dal_rtl8373_vlan_stg_set(rtk_vlan_t vid, rtk_stp_msti_id_t stg) +{ + rtk_api_ret_t retVal = 0; + dal_rtl8373_user_vlan4kentry vlan4K; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* vid must be 0~4095 */ + if (vid > RTL8373_VIDMAX) + return RT_ERR_VLAN_VID; + + /* stg must be 0~3 */ + if (stg > RTL8373_MSTIMAX) + return RT_ERR_MSTI; + + memset(&vlan4K, 0, sizeof(dal_rtl8373_user_vlan4kentry)); + + /* update 4K table */ + vlan4K.vid = vid; + if ((retVal = _dal_rtl8373_getAsicVlan4kEntry(&vlan4K)) != RT_ERR_OK) + return retVal; + + vlan4K.fid_msti= stg; + if ((retVal = _dal_rtl8373_setAsicVlan4kEntry(&vlan4K)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_vlan_stg_get + * Description: + * Get spanning tree group instance of the vlan to the specified device + * Input: + * vid - Specified VLAN ID. + * Output: + * pStg - spanning tree group instance. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * Note: + * The API can get spanning tree group instance of the vlan to the specified device. + */ +rtk_api_ret_t dal_rtl8373_vlan_stg_get(rtk_vlan_t vid, rtk_stp_msti_id_t *pStg) +{ + rtk_api_ret_t retVal = 0; + dal_rtl8373_user_vlan4kentry vlan4K; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* vid must be 0~4095 */ + if (vid > RTL8373_VIDMAX) + return RT_ERR_VLAN_VID; + + if(NULL == pStg) + return RT_ERR_NULL_POINTER; + + memset(&vlan4K, 0, sizeof(dal_rtl8373_user_vlan4kentry)); + + /* update 4K table */ + vlan4K.vid = vid; + if ((retVal = _dal_rtl8373_getAsicVlan4kEntry(&vlan4K)) != RT_ERR_OK) + return retVal; + + *pStg = vlan4K.fid_msti; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_vlan_portFid_set + * Description: + * Set port-based filtering database + * Input: + * port - Port id. + * enable - ebable port-based FID + * fid - Specified filtering database. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_FID - Invalid fid. + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API can set port-based filtering database. If the function is enabled, all input + * packets will be assigned to the port-based fid regardless vlan tag. + */ +rtk_api_ret_t dal_rtl8373_vlan_portFid_set(rtk_port_t port, rtk_enable_t enable, rtk_fid_t fid) +{ + rtk_api_ret_t retVal = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + if(port > RTL8373_PORTIDMAX) + return RT_ERR_PORT_ID; + + if (enable>=RTK_ENABLE_END) + return RT_ERR_ENABLE; + + /* fid must be 0~3 */ + if (fid > RTL8373_FIDMAX) + return RT_ERR_L2_FID; + + if ((retVal = rtl8373_setAsicRegBit(RTL8373_PORT_BASED_FID_EN_ADDR, port, enable))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_PORT_BASED_FID_ADDR(port), RTL8373_PORT_BASED_FID_FID_MASK(port) , fid))!=RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_vlan_portFid_get + * Description: + * Get port-based filtering database + * Input: + * port - Port id. + * Output: + * pEnable - ebable port-based FID + * pFid - Specified filtering database. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API can get port-based filtering database status. If the function is enabled, all input + * packets will be assigned to the port-based fid regardless vlan tag. + */ +rtk_api_ret_t dal_rtl8373_vlan_portFid_get(rtk_port_t port, rtk_enable_t *pEnable, rtk_fid_t *pFid) +{ + rtk_api_ret_t retVal = 0; + rtk_uint32 enable = 0 ; + rtk_uint32 fid = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + /* Check Port Valid */ + if(port > RTL8373_PORTIDMAX) + return RT_ERR_PORT_ID; + + if(NULL == pEnable) + return RT_ERR_NULL_POINTER; + + if(NULL == pFid) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8373_getAsicRegBit(RTL8373_PORT_BASED_FID_EN_ADDR, port, &enable))!=RT_ERR_OK) + return retVal; + + if ((retVal = rtl8373_getAsicRegBits(RTL8373_PORT_BASED_FID_ADDR(port), RTL8373_PORT_BASED_FID_FID_MASK(port) , &fid))!=RT_ERR_OK) + return retVal; + + *pEnable = (rtk_enable_t) (enable); + *pFid = (rtk_fid_t)fid; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_vlan_reservedVidAction_set + * Description: + * Set Action of VLAN ID = 0 & 4095 tagged packet + * Input: + * actVid0 - Action for VID 0. + * actVid4095 - Action for VID 4095. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + * + */ +rtk_api_ret_t dal_rtl8373_vlan_reservedVidAction_set(rtk_vlan_resVidAction_t actVid0, rtk_vlan_resVidAction_t actVid4095) +{ + rtk_api_ret_t retVal = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(actVid0 >= RSV_VID_ACTION_END) + return RT_ERR_INPUT; + + if(actVid4095 >= RSV_VID_ACTION_END) + return RT_ERR_INPUT; + + if((retVal = rtl8373_setAsicRegBit(RTL8373_VLAN_CTRL_ADDR, RTL8373_VLAN_CTRL_VID0_TYPE_OFFSET, actVid0)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8373_setAsicRegBit(RTL8373_VLAN_CTRL_ADDR, RTL8373_VLAN_CTRL_VID4095_TYPE_OFFSET, actVid4095)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_vlan_reservedVidAction_get + * Description: + * Get Action of VLAN ID = 0 & 4095 tagged packet + * Input: + * pAction_vid0 - Action for VID 0. + * pAction_vid4095 - Action for VID 4095. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - NULL Pointer + * Note: + * + */ +rtk_api_ret_t dal_rtl8373_vlan_reservedVidAction_get(rtk_vlan_resVidAction_t *pActVid0, rtk_vlan_resVidAction_t *pActVid4095) +{ + rtk_api_ret_t retVal = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(pActVid0 == NULL) + return RT_ERR_NULL_POINTER; + + if(pActVid4095 == NULL) + return RT_ERR_NULL_POINTER; + + if((retVal = rtl8373_getAsicRegBit(RTL8373_VLAN_CTRL_ADDR, RTL8373_VLAN_CTRL_VID0_TYPE_OFFSET, (rtk_uint32 *)pActVid0)) != RT_ERR_OK) + return retVal; + + if((retVal = rtl8373_getAsicRegBit(RTL8373_VLAN_CTRL_ADDR, RTL8373_VLAN_CTRL_VID4095_TYPE_OFFSET, (rtk_uint32 *)pActVid4095)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_vlan_realKeepRemarkEnable_set + * Description: + * Set Real keep 1p remarking feature + * Input: + * enabled - State of 1p remarking at real keep packet + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + * + */ +rtk_api_ret_t dal_rtl8373_vlan_realKeepRemarkEnable_set(rtk_enable_t enabled) +{ + rtk_api_ret_t retVal = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(enabled >= RTK_ENABLE_END) + return RT_ERR_INPUT; + + if((retVal = rtl8373_setAsicRegBit(RTL8373_VLAN_TAG_PRI_CFG_ADDR, RTL8373_VLAN_TAG_PRI_CFG_RMK1P_BYPASS_REALKEEP_OFFSET, enabled)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * dal_rtl8373_vlan_realKeepRemarkEnable_get + * Description: + * Get Real keep 1p remarking feature + * Input: + * None. + * Output: + * pEnabled - State of 1p remarking at real keep packet + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + * + */ +rtk_api_ret_t dal_rtl8373_vlan_realKeepRemarkEnable_get(rtk_enable_t *pEnabled) +{ + rtk_api_ret_t retVal = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(NULL == pEnabled) + return RT_ERR_NULL_POINTER; + + if((retVal = rtl8373_getAsicRegBit(RTL8373_VLAN_TAG_PRI_CFG_ADDR, RTL8373_VLAN_TAG_PRI_CFG_RMK1P_BYPASS_REALKEEP_OFFSET, (rtk_uint32 *)pEnabled)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/******************************************************************************* +* Function Name: dal_rtl8373_vlan_disL2Learn_entry_set +* +* Description: +* config a L2 disable learning entry which based on vlan id +*Input: +* index: entry index +* pDisL2LearnCfg: L2 disable learning database +*Output: +* None +*Return: +* RT_ERR_OK - OK +* RT_ERR_FAILED - Failed +* RT_ERR_ENTRY_INDEX - error entry +* RT_ERR_ENABLE - error action +* RT_ERR_NULL_POINTER - NULL Pointer +* RT_ERR_VLAN_VID - Invalid VID parameter. + +*Note: None +*******************************************************************************/ +rtk_api_ret_t dal_rtl8373_vlan_disL2Learn_entry_set(rtk_vlan_disL2_learn_t *pDisL2LearnCfg) +{ + rtk_api_ret_t retVal = 0; + rtk_uint8 available = 0xFF, same = 0xFF, i=0; + rtk_uint32 vid = 0, index = 0, regData = 0; + rtk_vlan_disL2_learn_t tempData; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + if(NULL ==pDisL2LearnCfg) + return RT_ERR_NULL_POINTER; + + if (pDisL2LearnCfg->vid > RTL8373_VIDMAX) + return RT_ERR_INPUT; + + if ((pDisL2LearnCfg->act > 1) ||(pDisL2LearnCfg->valid > 1) ) + return RT_ERR_INPUT; + + vid = pDisL2LearnCfg->vid; + for(i=0; i<2; i++) + { + if((retVal = rtl8373_getAsicReg(RTL8373_VLAN_L2_LRN_DIS_ADDR(i),®Data)) != RT_ERR_OK) + return retVal; + + tempData.valid = (regData & RTL8373_VLAN_L2_LRN_DIS_VALID_MASK) >> RTL8373_VLAN_L2_LRN_DIS_VALID_OFFSET; + tempData.vid = (regData & RTL8373_VLAN_L2_LRN_DIS_VID_MASK) >> RTL8373_VLAN_L2_LRN_DIS_VID_OFFSET; + tempData.act = (regData & RTL8373_VLAN_L2_LRN_DIS_ACT_MASK) >> RTL8373_VLAN_L2_LRN_DIS_ACT_OFFSET; + + if(tempData.valid == 0) + available = i; + if(tempData.vid == vid) + same = i; + } + if( (available == 0xFF) && (same == 0xFF) ) + return RT_ERR_TBL_FULL; + else if( (available == 0xFF) && (same != 0xFF) ) + index = same; + else if( (available != 0xFF) && (same == 0xFF) ) + index = available; + else + index = same; + + regData =(pDisL2LearnCfg->act << RTL8373_VLAN_L2_LRN_DIS_ACT_OFFSET) |(pDisL2LearnCfg->vid << RTL8373_VLAN_L2_LRN_DIS_VID_OFFSET); + regData |= pDisL2LearnCfg->valid ; + + /* set entry*/ + if((retVal = rtl8373_setAsicReg(RTL8373_VLAN_L2_LRN_DIS_ADDR(index),regData)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/******************************************************************************* +* Function Name: dal_rtl8373_vlan_disL2Learn_entry_get +* +* Description: +* get vlan based disable L2 entry data +*Input: +* index: entry index +* +*Output: +* pDisL2LearnCfg: L2 disable learning database +*Return: +* RT_ERR_OK - OK +* RT_ERR_FAILED - Failed +* RT_ERR_ENTRY_INDEX - error entry +* RT_ERR_ENABLE - error action +* RT_ERR_NULL_POINTER - NULL Pointer +* RT_ERR_VLAN_VID - Invalid VID parameter. + +*Note: None +*******************************************************************************/ +rtk_api_ret_t dal_rtl8373_vlan_disL2Learn_entry_get(rtk_uint32 index, rtk_vlan_disL2_learn_t *pDisL2LearnCfg) +{ + rtk_api_ret_t retVal = 0; + rtk_uint32 regData = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + if( index > RTL8373_DISABLE_L2_LEARN_MAX) + return RT_ERR_INPUT; + if(NULL ==pDisL2LearnCfg) + return RT_ERR_NULL_POINTER; + + + if((retVal = rtl8373_getAsicReg(RTL8373_VLAN_L2_LRN_DIS_ADDR(index),®Data)) != RT_ERR_OK) + return retVal; + + pDisL2LearnCfg->valid = (regData & RTL8373_VLAN_L2_LRN_DIS_VALID_MASK) >> RTL8373_VLAN_L2_LRN_DIS_VALID_OFFSET; + pDisL2LearnCfg->vid = (regData & RTL8373_VLAN_L2_LRN_DIS_VID_MASK) >> RTL8373_VLAN_L2_LRN_DIS_VID_OFFSET; + pDisL2LearnCfg->act = (regData & RTL8373_VLAN_L2_LRN_DIS_ACT_MASK) >> RTL8373_VLAN_L2_LRN_DIS_ACT_OFFSET; + + return RT_ERR_OK; +} +/* Function Name: + * dal_rtl8373_vlan_reset + * Description: + * Reset VLAN + * Input: + * None. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + * + */ +rtk_api_ret_t dal_rtl8373_vlan_reset(void) +{ + rtk_api_ret_t retVal = 0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if((retVal = rtl8373_setAsicRegBit(RTL8373_VLAN_CTRL_ADDR, RTL8373_VLAN_CTRL_TABLE_RST_OFFSET, ENABLED)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + + diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_vlan.h b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_vlan.h new file mode 100755 index 00000000..32684159 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_vlan.h @@ -0,0 +1,616 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8373 switch high-level API + * + * Feature : The file includes Trap module high-layer VLAN defination + * + */ + +#ifndef __DAL_RTL8373_VLAN_H__ +#define __DAL_RTL8373_VLAN_H__ + +#include + +typedef struct USER_VLANTABLE{ + + rtk_uint16 vid; + rtk_uint16 mbr; + rtk_uint16 untag; + rtk_uint16 fid_msti; + rtk_uint16 svlan_chk_ivl_svl; + rtk_uint16 ivl_svl; + +}dal_rtl8373_user_vlan4kentry; + +extern ret_t _dal_rtl8373_setAsicVlan4kEntry(dal_rtl8373_user_vlan4kentry *pVlan4kEntry); +extern ret_t _dal_rtl8373_getAsicVlan4kEntry(dal_rtl8373_user_vlan4kentry *pVlan4kEntry); + +/* Function Name: + * dal_rtl8373_vlan_init + * Description: + * Initialize VLAN. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * VLAN is disabled by default. User has to call this API to enable VLAN before + * using it. And It will set a default VLAN(vid 1) including all ports and set + * all ports PVID to the default VLAN. + */ +extern rtk_api_ret_t dal_rtl8373_vlan_init(void); + +/* Function Name: + * dal_rtl8373_vlan_set + * Description: + * Set a VLAN entry. + * Input: + * vid - VLAN ID to configure. + * pVlanCfg - VLAN Configuration + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_L2_FID - Invalid FID. + * RT_ERR_VLAN_PORT_MBR_EXIST - Invalid member port mask. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8373_vlan_set(rtk_vlan_t vid, rtk_vlan_entry_t *pVlanCfg); + +/* Function Name: + * dal_rtl8373_vlan_get + * Description: + * Get a VLAN entry. + * Input: + * vid - VLAN ID to configure. + * Output: + * pVlanCfg - VLAN Configuration + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8373_vlan_get(rtk_vlan_t vid, rtk_vlan_entry_t *pVlanCfg); + +/* Function Name: + * dal_rtl8373_vlan_egrFilterEnable_set + * Description: + * Set VLAN egress filter. + * Input: + * egrFilter - Egress filtering + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid input parameters. + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8373_vlan_egrFilterEnable_set(rtk_enable_t egrFilter); + +/* Function Name: + * dal_rtl8373_vlan_egrFilterEnable_get + * Description: + * Get VLAN egress filter. + * Input: + * pEgrFilter - Egress filtering + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - NULL Pointer. + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8373_vlan_egrFilterEnable_get(rtk_enable_t *pEgrFilter); + +/* Function Name: + * dal_rtl8373_vlan_portPvid_set + * Description: + * Set port to specified VLAN ID(PVID). + * Input: + * port - Port id. + * pvid - Specified VLAN ID. + * priority - 802.1p priority for the PVID. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_VLAN_PRIORITY - Invalid priority. + * RT_ERR_VLAN_ENTRY_NOT_FOUND - VLAN entry not found. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * Note: + * The API is used for Port-based VLAN. The untagged frame received from the + * port will be classified to the specified VLAN and assigned to the specified priority. + */ +extern rtk_api_ret_t dal_rtl8373_vlan_portPvid_set(rtk_port_t port, rtk_vlan_t pvid); + +/* Function Name: + * dal_rtl8373_vlan_portPvid_get + * Description: + * Get VLAN ID(PVID) on specified port. + * Input: + * port - Port id. + * Output: + * pPvid - Specified VLAN ID. + * pPriority - 802.1p priority for the PVID. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get the PVID and 802.1p priority for the PVID of Port-based VLAN. + */ +extern rtk_api_ret_t dal_rtl8373_vlan_portPvid_get(rtk_port_t port, rtk_vlan_t *pPvid); + +/* Function Name: + * dal_rtl8373_vlan_portIgrFilterEnable_set + * Description: + * Set VLAN ingress for each port. + * Input: + * port - Port id. + * igrFilter - VLAN ingress function enable status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * RT_ERR_ENABLE - Invalid enable input + * Note: + * The status of vlan ingress filter is as following: + * - DISABLED + * - ENABLED + * While VLAN function is enabled, ASIC will decide VLAN ID for each received frame and get belonged member + * ports from VLAN table. If received port is not belonged to VLAN member ports, ASIC will drop received frame if VLAN ingress function is enabled. + */ +extern rtk_api_ret_t dal_rtl8373_vlan_portIgrFilterEnable_set(rtk_port_t port, rtk_enable_t igrFilter); + +/* Function Name: + * dal_rtl8373_vlan_portIgrFilterEnable_get + * Description: + * Get VLAN Ingress Filter + * Input: + * port - Port id. + * Output: + * pIgrFilter - VLAN ingress function enable status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can Get the VLAN ingress filter status. + * The status of vlan ingress filter is as following: + * - DISABLED + * - ENABLED + */ +extern rtk_api_ret_t dal_rtl8373_vlan_portIgrFilterEnable_get(rtk_port_t port, rtk_enable_t *pIgrFilter); + +/* Function Name: + * dal_rtl8373_vlan_portAcceptFrameType_set + * Description: + * Set VLAN accept_frame_type + * Input: + * port - Port id. + * acceptFrameType - accept frame type + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_VLAN_ACCEPT_FRAME_TYPE - Invalid frame type. + * Note: + * The API is used for checking 802.1Q tagged frames. + * The accept frame type as following: + * - ACCEPT_FRAME_TYPE_ALL + * - ACCEPT_FRAME_TYPE_TAG_ONLY + * - ACCEPT_FRAME_TYPE_UNTAG_ONLY + */ +extern rtk_api_ret_t dal_rtl8373_vlan_portAcceptFrameType_set(rtk_port_t port, rtk_vlan_acceptFrameType_t acceptFrameType); + +/* Function Name: + * dal_rtl8373_vlan_portAcceptFrameType_get + * Description: + * Get VLAN accept_frame_type + * Input: + * port - Port id. + * Output: + * pAcceptFrameType - accept frame type + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can Get the VLAN ingress filter. + * The accept frame type as following: + * - ACCEPT_FRAME_TYPE_ALL + * - ACCEPT_FRAME_TYPE_TAG_ONLY + * - ACCEPT_FRAME_TYPE_UNTAG_ONLY + */ +extern rtk_api_ret_t dal_rtl8373_vlan_portAcceptFrameType_get(rtk_port_t port, rtk_vlan_acceptFrameType_t *pAcceptFrameType); + +/* Function Name: + * dal_rtl8373_vlan_tagMode_set + * Description: + * Set CVLAN egress tag mode + * Input: + * port - Port id. + * tagMode - The egress tag mode. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * The API can set Egress tag mode. There are 4 mode for egress tag: + * - VLAN_EGRESS_TAG_MODE_ORIGINAL, + * - VLAN_EGRESS_TAG_MODE_KEEP_FORMAT, + * - VLAN_EGRESS_TAG_MODE_PRI. + * - VLAN_EGRESS_TAG_MODE_REAL_KEEP, + */ +extern rtk_api_ret_t dal_rtl8373_vlan_tagMode_set(rtk_port_t port, rtk_vlan_egressTagMode_t tagMode); + +/* Function Name: + * dal_rtl8373_vlan_tagMode_get + * Description: + * Get CVLAN egress tag mode + * Input: + * port - Port id. + * Output: + * pTagMode - The egress tag mode. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get Egress tag mode. There are 4 mode for egress tag: + * - VLAN_EGRESS_TAG_MODE_ORIGINAL, + * - VLAN_EGRESS_TAG_MODE_KEEP_FORMAT, + * - VLAN_EGRESS_TAG_MODE_PRI. + * - VLAN_EGRESS_TAG_MODE_REAL_KEEP, + */ +extern rtk_api_ret_t dal_rtl8373_vlan_tagMode_get(rtk_port_t port, rtk_vlan_egressTagMode_t *pTagMode); + +/* Function Name: + * dal_rtl8373_vlan_transparent_set + * Description: + * Set VLAN transparent mode + * Input: + * egrPort - Egress Port id. + * pIgrPmsk - Ingress Port Mask. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * None. + */ +extern rtk_api_ret_t dal_rtl8373_vlan_portTransparent_set(rtk_port_t egrPort, rtk_portmask_t *pIgrPmsk); + +/* Function Name: + * dal_rtl8373_vlan_transparent_get + * Description: + * Get VLAN transparent mode + * Input: + * egrPort - Egress Port id. + * Output: + * pIgrPmsk - Ingress Port Mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * None. + */ +extern rtk_api_ret_t dal_rtl8373_vlan_portTransparent_get(rtk_port_t egrPort, rtk_portmask_t *pIgrPmsk); + +/* Function Name: + * dal_rtl8373_vlan_keep_set + * Description: + * Set VLAN egress keep mode + * Input: + * egrPort - Egress Port id. + * pIgrPmsk - Ingress Port Mask. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * None. + */ +extern rtk_api_ret_t dal_rtl8373_vlan_keep_set(rtk_port_t egrPort, rtk_portmask_t *pIgrPmsk); + +/* Function Name: + * dal_rtl8373_vlan_keep_get + * Description: + * Get VLAN egress keep mode + * Input: + * egr_port - Egress Port id. + * Output: + * pIgr_pmask - Ingress Port Mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * None. + */ +extern rtk_api_ret_t dal_rtl8373_vlan_keep_get(rtk_port_t egrPort, rtk_portmask_t *pIgrPmsk); + +/* Function Name: + * dal_rtl8373_vlan_stg_set + * Description: + * Set spanning tree group instance of the vlan to the specified device + * Input: + * vid - Specified VLAN ID. + * stg - spanning tree group instance. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_MSTI - Invalid msti parameter + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * Note: + * The API can set spanning tree group instance of the vlan to the specified device. + */ +extern rtk_api_ret_t dal_rtl8373_vlan_stg_set(rtk_vlan_t vid, rtk_stp_msti_id_t stg); + +/* Function Name: + * dal_rtl8373_vlan_stg_get + * Description: + * Get spanning tree group instance of the vlan to the specified device + * Input: + * vid - Specified VLAN ID. + * Output: + * pStg - spanning tree group instance. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * Note: + * The API can get spanning tree group instance of the vlan to the specified device. + */ +extern rtk_api_ret_t dal_rtl8373_vlan_stg_get(rtk_vlan_t vid, rtk_stp_msti_id_t *pStg); + +/* Function Name: + * dal_rtl8373_vlan_portFid_set + * Description: + * Set port-based filtering database + * Input: + * port - Port id. + * enable - ebable port-based FID + * fid - Specified filtering database. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_FID - Invalid fid. + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API can set port-based filtering database. If the function is enabled, all input + * packets will be assigned to the port-based fid regardless vlan tag. + */ +extern rtk_api_ret_t dal_rtl8373_vlan_portFid_set(rtk_port_t port, rtk_enable_t enable, rtk_fid_t fid); + +/* Function Name: + * dal_rtl8373_vlan_portFid_get + * Description: + * Get port-based filtering database + * Input: + * port - Port id. + * Output: + * pEnable - ebable port-based FID + * pFid - Specified filtering database. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API can get port-based filtering database status. If the function is enabled, all input + * packets will be assigned to the port-based fid regardless vlan tag. + */ +extern rtk_api_ret_t dal_rtl8373_vlan_portFid_get(rtk_port_t port, rtk_enable_t *pEnable, rtk_fid_t *pFid); + +/* Function Name: + * dal_rtl8373_vlan_reservedVidAction_set + * Description: + * Set Action of VLAN ID = 0 & 4095 tagged packet + * Input: + * actVid0 - Action for VID 0. + * actVid4095 - Action for VID 4095. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8373_vlan_reservedVidAction_set(rtk_vlan_resVidAction_t actVid0, rtk_vlan_resVidAction_t actVid4095); + +/* Function Name: + * dal_rtl8373_vlan_reservedVidAction_get + * Description: + * Get Action of VLAN ID = 0 & 4095 tagged packet + * Input: + * pActVid0 - Action for VID 0. + * pActVid4095 - Action for VID 4095. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - NULL Pointer + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8373_vlan_reservedVidAction_get(rtk_vlan_resVidAction_t *pActVid0, rtk_vlan_resVidAction_t *pActVid4095); + +/* Function Name: + * dal_rtl8373_vlan_realKeepRemarkEnable_set + * Description: + * Set Real keep 1p remarking feature + * Input: + * enabled - State of 1p remarking at real keep packet + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8373_vlan_realKeepRemarkEnable_set(rtk_enable_t enabled); + +/* Function Name: + * dal_rtl8373_vlan_realKeepRemarkEnable_get + * Description: + * Get Real keep 1p remarking feature + * Input: + * None. + * Output: + * pEnabled - State of 1p remarking at real keep packet + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8373_vlan_realKeepRemarkEnable_get(rtk_enable_t *pEnabled); + +/******************************************************************************* +* Function Name: dal_rtl8373_vlan_disL2Learn_entry_set +* +* Description: +* config a L2 disable learning entry which based on vlan id +*Input: +* index: entry index +* pDisL2LearnCfg: L2 disable learning database +*Output: +* None +*Return: +* RT_ERR_OK - OK +* RT_ERR_FAILED - Failed +* RT_ERR_ENTRY_INDEX - error entry +* RT_ERR_ENABLE - error action +* RT_ERR_NULL_POINTER - NULL Pointer +* RT_ERR_VLAN_VID - Invalid VID parameter. + +*Note: None +*******************************************************************************/ +extern rtk_api_ret_t dal_rtl8373_vlan_disL2Learn_entry_set(rtk_vlan_disL2_learn_t *pDisL2LearnCfg); + +/******************************************************************************* +* Function Name: dal_rtl8373_vlan_disL2Learn_entry_get +* +* Description: +* get vlan based disable L2 entry data +*Input: +* index: entry index +* +*Output: +* pDisL2LearnCfg: L2 disable learning database +*Return: +* RT_ERR_OK - OK +* RT_ERR_FAILED - Failed +* RT_ERR_ENTRY_INDEX - error entry +* RT_ERR_ENABLE - error action +* RT_ERR_NULL_POINTER - NULL Pointer +* RT_ERR_VLAN_VID - Invalid VID parameter. + +*Note: None +*******************************************************************************/ +extern rtk_api_ret_t dal_rtl8373_vlan_disL2Learn_entry_get(rtk_uint32 index, rtk_vlan_disL2_learn_t *pDisL2LearnCfg); + +/* Function Name: + * dal_rtl8373_vlan_reset + * Description: + * Reset VLAN + * Input: + * None. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + * + */ +extern rtk_api_ret_t dal_rtl8373_vlan_reset(void); + +#endif /* __DAL_RTL8373_VLAN_H__ */ diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_wol.c b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_wol.c new file mode 100755 index 00000000..d7434114 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_wol.c @@ -0,0 +1,220 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8373 + * Feature : Here is a list of all functions and variables in TRUNK module. + * + */ + +#include +#include +#include +#include +#include + + + +/* Function Name: + * dal_rtl8373_wolState_set + * Description: + * Set wol function enable + * Input: + * enable : 1 enable wol; 0: disable wol + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ +rtk_api_ret_t dal_rtl8373_wolState_set(rtk_uint32 enable) +{ + rtk_api_ret_t retVal; + + if ((retVal = rtl8373_setAsicRegBit(RTL8373_WOL_CTRL_ADDR, RTL8373_WOL_CTRL_WOL_EN_OFFSET, enable)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_wolState_get + * Description: + * Set wol function enable + * Input: + * pEnable : 1 enable wol; 0: disable wol + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ +rtk_api_ret_t dal_rtl8373_wolState_get(rtk_uint32* pEnable) +{ + rtk_api_ret_t retVal; + + if ((retVal = rtl8373_getAsicRegBit(RTL8373_WOL_CTRL_ADDR, RTL8373_WOL_CTRL_WOL_EN_OFFSET, pEnable)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + +#if 0 + +/* Function Name: + * dal_rtl8373_wolPortmsk_set + * Description: + * Set wol port mask + * Input: + * portmask: port mask + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ +rtk_api_ret_t dal_rtl8373_wolPortmsk_set(rtk_uint32 portmask) +{ + rtk_api_ret_t retVal; + + if ((retVal = rtl8373_setAsicRegBits(RTL8373_WOL_CTRL_ADDR, RTL8373_WOL_CTRL_WOL_PMSK_MASK, portmask)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +#endif + + +/* Function Name: + * dal_rtl8373_wolPortmsk_get + * Description: + * Set wol port mask + * Input: + * pMask: port mask + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ +rtk_api_ret_t dal_rtl8373_wolPortmsk_get(rtk_uint32* pMask) +{ + rtk_api_ret_t retVal; + + if ((retVal = rtl8373_getAsicRegBits(RTL8373_WOL_CTRL_ADDR, RTL8373_WOL_CTRL_WOL_PMSK_MASK, pMask)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + + + + +/* Function Name: + * dal_rtl8373_wolMac_set + * Description: + * Set wol port mask + * Input: + * pMac: wol mac address + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ +rtk_api_ret_t dal_rtl8373_wolMac_set(rtk_mac_t *pMac) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + + if(pMac == NULL) + return RT_ERR_NULL_POINTER; + + regData = (pMac->octet[2] << 24) | (pMac->octet[3] << 16) | (pMac->octet[4] << 8) | pMac->octet[5]; + if ((retVal = rtl8373_setAsicReg(RTL8373_WOL_MAC0_ADDR, regData)) != RT_ERR_OK) + return retVal; + + + regData = (pMac->octet[0] << 8) | pMac->octet[1]; + if ((retVal = rtl8373_setAsicReg(RTL8373_WOL_MAC1_ADDR, regData)) != RT_ERR_OK) + return retVal; + + + return RT_ERR_OK; +} + + +/* Function Name: + * dal_rtl8373_wolMac_get + * Description: + * Set wol port mask + * Input: + * pMac: wol mac address + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ +rtk_api_ret_t dal_rtl8373_wolMac_get(rtk_mac_t *pMac) +{ + rtk_api_ret_t retVal; + rtk_uint32 regData; + + if(pMac == NULL) + return RT_ERR_NULL_POINTER; + + if ((retVal = rtl8373_getAsicReg(RTL8373_WOL_MAC0_ADDR, ®Data)) != RT_ERR_OK) + return retVal; + pMac->octet[2] = (regData >> 24) & 0xff; + pMac->octet[3] = (regData >> 16) & 0xff; + pMac->octet[4] = (regData >> 8) & 0xff; + pMac->octet[5] = regData & 0xff; + + + if ((retVal = rtl8373_getAsicReg(RTL8373_WOL_MAC1_ADDR, ®Data)) != RT_ERR_OK) + return retVal; + + pMac->octet[0] = (regData >> 8) & 0xff; + pMac->octet[1] = regData & 0xff; + + + return RT_ERR_OK; +} + + + + + + diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_wol.h b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_wol.h new file mode 100755 index 00000000..b59dc526 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/dal_rtl8373_wol.h @@ -0,0 +1,120 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8373 + * Feature : Here is a list of all functions and variables in TRUNK module. + * + */ + +#include +#include +#include +#include + + + +/* Function Name: + * dal_rtl8373_wolState_set + * Description: + * Set wol function enable + * Input: + * enable : 1 enable wol; 0: disable wol + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ +extern rtk_api_ret_t dal_rtl8373_wolState_set(rtk_uint32 enable); + + +/* Function Name: + * dal_rtl8373_wolState_sget + * Description: + * Set wol function enable + * Input: + * pEnable : 1 enable wol; 0: disable wol + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ +extern rtk_api_ret_t dal_rtl8373_wolState_get(rtk_uint32* pEnable); + + +/* Function Name: + * dal_rtl8373_wolPortmsk_get + * Description: + * Set wol port mask + * Input: + * pMask: port mask + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ +extern rtk_api_ret_t dal_rtl8373_wolPortmsk_get(rtk_uint32* pMask); + + + + +/* Function Name: + * dal_rtl8373_wolMac_set + * Description: + * Set wol port mask + * Input: + * pMac: wol mac address + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ +extern rtk_api_ret_t dal_rtl8373_wolMac_set(rtk_mac_t *pMac); + + +/* Function Name: + * dal_rtl8373_wolMac_get + * Description: + * Set wol port mask + * Input: + * pMac: wol mac address + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ +extern rtk_api_ret_t dal_rtl8373_wolMac_get(rtk_mac_t *pMac); + + + + diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/rtl8373_asicdrv.c b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/rtl8373_asicdrv.c new file mode 100755 index 00000000..934d8dfc --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/rtl8373_asicdrv.c @@ -0,0 +1,644 @@ +/* + * Copyright (C) 2019 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTL8373 switch high-level API for RTL8373 + * Feature : + * + */ + +#include + +#if defined(RTK_X86_ASICDRV) +#include +#else +#include +#endif + +/*for driver verify testing only*/ +#ifdef CONFIG_RTL8373_ASICDRV_TEST +#define CLE_VIRTUAL_REG_SIZE 0x10000 +rtk_uint16 CleVirtualReg[CLE_VIRTUAL_REG_SIZE]; +#endif + +#if defined(CONFIG_RTL865X_CLE) || defined (RTK_X86_CLE) +rtk_uint32 cleDebuggingDisplay; +#endif + +#ifdef EMBEDDED_SUPPORT +extern void setReg(rtk_uint16, rtk_uint16); +extern rtk_uint16 getReg(rtk_uint16); +#endif + +/* Function Name: + * rtl8373_setAsicRegBit + * Description: + * Set a bit value of a specified register + * Input: + * reg - register's address + * offset - offset location + * value - value to set. It can be value 0 or 1. + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter + * Note: + * Set a bit of a specified register to 1 or 0. + */ +ret_t rtl8373_setAsicRegBit(rtk_uint32 reg, rtk_uint32 offset, rtk_uint32 value) +{ + +#if defined(RTK_X86_ASICDRV) + rtk_uint32 regData; + ret_t retVal; + + if(offset >= RTL8373_REGBITLENGTH) + return RT_ERR_INPUT; + + retVal = Access_Read(reg, 4, ®Data); + if(TRUE != retVal) + return RT_ERR_SMI; + + if(0x8367B == cleDebuggingDisplay) + PRINT("R[0x%4.4x]=0x%4.4x\n", reg, regData); + + if(value) + regData = regData | (1 << offset); + else + regData = regData & (~(1 << offset)); + + retVal = Access_Write(reg,4, regData); + if(TRUE != retVal) + return RT_ERR_SMI; + + if(0x8367B == cleDebuggingDisplay) + PRINT("W[0x%4.4x]=0x%4.4x\n", reg, regData); + + +#elif defined(CONFIG_RTL8373_ASICDRV_TEST) + + if(offset >= RTL8373_REGBITLENGTH) + return RT_ERR_INPUT; + + else if(reg >= CLE_VIRTUAL_REG_SIZE) + return RT_ERR_OUT_OF_RANGE; + + if(value) + { + CleVirtualReg[reg] = CleVirtualReg[reg] | (1 << offset); + } + else + { + CleVirtualReg[reg] = CleVirtualReg[reg] & (~(1 << offset)); + } + + if(0x8367B == cleDebuggingDisplay) + PRINT("W[0x%8.8x]=0x%8.8x\n", reg, CleVirtualReg[reg]); + +#elif defined(EMBEDDED_SUPPORT) + rtk_uint16 tmp; + + if(reg > RTL8373_REGDATAMAX || value > 1) + return RT_ERR_INPUT; + + tmp = getReg(reg); + tmp &= (1 << offset); + tmp |= (value << offset); + setReg(reg, tmp); + +#else + rtk_uint32 regData; + ret_t retVal; + + + if(offset >= RTL8373_REGBITLENGTH) + return RT_ERR_INPUT; + + retVal = rtl8373_smi_read(reg, ®Data); + if(retVal != RT_ERR_OK) + return RT_ERR_SMI; + + #ifdef CONFIG_RTL865X_CLE + if(0x8367B == cleDebuggingDisplay) + PRINT("R[0x%8.8x]=0x%8.8x\n", reg, regData); + #endif + if(value) + regData = regData | (1 << offset); + else + regData = regData & (~(1 << offset)); + + retVal = rtl8373_smi_write(reg, regData); + if(retVal != RT_ERR_OK) + return RT_ERR_SMI; + + #ifdef CONFIG_RTL865X_CLE + if(0x8367B == cleDebuggingDisplay) + PRINT("W[0x%8.8x]=0x%8.8x\n", reg, regData); + #endif + +#endif + return RT_ERR_OK; +} +/* Function Name: + * rtl8373_getAsicRegBit + * Description: + * Get a bit value of a specified register + * Input: + * reg - register's address + * offset - bit location + * value - value to get. + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter + * Note: + * None + */ +ret_t rtl8373_getAsicRegBit(rtk_uint32 reg, rtk_uint32 offset, rtk_uint32 *pValue) +{ + +#if defined(RTK_X86_ASICDRV) + + rtk_uint32 regData; + ret_t retVal; + + if(offset >= RTL8373_REGBITLENGTH) + return RT_ERR_INPUT; + + retVal = Access_Read(reg, 4, ®Data); + if(TRUE != retVal) + return RT_ERR_SMI; + + //*pValue = (regData & (0x1 << offset)) >> offset; + *pValue = ((regData >> offset ) & 0x1); + if(0x8367B == cleDebuggingDisplay) + PRINT("R[0x%8.8x]=0x%8.8x\n", reg, regData); + +#elif defined(CONFIG_RTL8373_ASICDRV_TEST) + + if(bit >= RTL8373_REGBITLENGTH) + return RT_ERR_INPUT; + + if(reg >= CLE_VIRTUAL_REG_SIZE) + return RT_ERR_OUT_OF_RANGE; + + *pValue = (CleVirtualReg[reg] & (0x1 << offset)) >> offset; + + if(0x8367B == cleDebuggingDisplay) + PRINT("R[0x%8.8x]=0x%8.8x\n", reg, CleVirtualReg[reg]); + +#elif defined(EMBEDDED_SUPPORT) + rtk_uint16 tmp; + + if(reg > RTL8373_REGDATAMAX ) + return RT_ERR_INPUT; + + tmp = getReg(reg); + tmp = tmp >> offset; + tmp &= 1; + *pValue = tmp; +#else + rtk_uint32 regData; + ret_t retVal; + + retVal = rtl8373_smi_read(reg, ®Data); + if(retVal != RT_ERR_OK) + return RT_ERR_SMI; + + #ifdef CONFIG_RTL865X_CLE + if(0x8367B == cleDebuggingDisplay) + PRINT("R[0x%8.8x]=0x%8.8x\n", reg, regData); + #endif + + *pValue = (regData & (0x1 << offset)) >> offset; + +#endif + return RT_ERR_OK; +} +/* Function Name: + * rtl8373_setAsicRegBits + * Description: + * Set bits value of a specified register + * Input: + * reg - register's address + * bits - bits mask for setting + * value - bits value for setting + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter + * Note: + * Set bits of a specified register to value. Both bits and value are be treated as bit-mask + */ +ret_t rtl8373_setAsicRegBits(rtk_uint32 reg, rtk_uint32 bitsMask, rtk_uint32 value) +{ + +#if defined(RTK_X86_ASICDRV) + + rtk_uint32 regData; + ret_t retVal; + rtk_uint32 bitsShift; + rtk_uint32 valueShifted; + + if( !bitsMask ) + return RT_ERR_INPUT; + + bitsShift = 0; + while(!(bitsMask & (1 << bitsShift))) + { + bitsShift++; + if(bitsShift >= RTL8373_REGBITLENGTH) + return RT_ERR_INPUT; + } + + valueShifted = value << bitsShift; + if(valueShifted > RTL8373_REGDATAMAX) + return RT_ERR_INPUT; + + retVal = Access_Read(reg, 4, ®Data); + if(TRUE != retVal) + return RT_ERR_SMI; + + if(0x8367B == cleDebuggingDisplay) + PRINT("R[0x%4.4x]=0x%4.4x\n", reg, regData); + + regData = regData & (~bitsMask); + regData = regData | (valueShifted & bitsMask); + + retVal = Access_Write(reg,4, regData); + if(TRUE != retVal) + return RT_ERR_SMI; + + if(0x8367B == cleDebuggingDisplay) + PRINT("W[0x%4.4x]=0x%4.4x\n", reg, regData); + +#elif defined(CONFIG_RTL8373_ASICDRV_TEST) + rtk_uint32 regData; + rtk_uint32 bitsShift; + rtk_uint32 valueShifted; + + if(!bitsMask ) + return RT_ERR_INPUT; + + bitsShift = 0; + while(!(bitsMask & (1 << bitsShift))) + { + bitsShift++; + if(bitsShift >= RTL8373_REGBITLENGTH) + return RT_ERR_INPUT; + } + valueShifted = value << bitsShift; + + if(valueShifted > RTL8373_REGDATAMAX) + return RT_ERR_INPUT; + + if(reg >= CLE_VIRTUAL_REG_SIZE) + return RT_ERR_OUT_OF_RANGE; + + regData = CleVirtualReg[reg] & (~bitsMask); + regData = regData | (valueShifted & bitsMask); + + CleVirtualReg[reg] = regData; + + if(0x8367B == cleDebuggingDisplay) + PRINT("W[0x%4.4x]=0x%4.4x\n", reg, regData); + +#elif defined(EMBEDDED_SUPPORT) + rtk_uint32 regData; + rtk_uint32 bitsShift; + rtk_uint32 valueShifted; + + if(reg > RTL8373_REGDATAMAX ) + return RT_ERR_INPUT; + + if(bitsMask >= (1 << RTL8373_REGBITLENGTH) ) + return RT_ERR_INPUT; + + bitsShift = 0; + while(!(bitsMask & (1 << bitsShift))) + { + bitsShift++; + if(bitsShift >= RTL8373_REGBITLENGTH) + return RT_ERR_INPUT; + } + + valueShifted = value << bitsShift; + if(valueShifted > RTL8373_REGDATAMAX) + return RT_ERR_INPUT; + + regData = getReg(reg); + regData = regData & (~bitsMask); + regData = regData | (valueShifted & bitsMask); + + setReg(reg, regData); + +#else + rtk_uint32 regData; + ret_t retVal; + rtk_uint32 bitsShift; + rtk_uint32 valueShifted; + + if( !bitsMask ) + return RT_ERR_INPUT; + + bitsShift = 0; + while(!(bitsMask & (1 << bitsShift))) + { + bitsShift++; + if(bitsShift >= RTL8373_REGBITLENGTH) + return RT_ERR_INPUT; + } + valueShifted = value << bitsShift; + + if(valueShifted > RTL8373_REGDATAMAX) + return RT_ERR_INPUT; + + retVal = rtl8373_smi_read(reg, ®Data); + if(retVal != RT_ERR_OK) + return RT_ERR_SMI; + #ifdef CONFIG_RTL865X_CLE + if(0x8367B == cleDebuggingDisplay) + PRINT("R[0x%4.4x]=0x%4.4x\n", reg, regData); + #endif + + regData = regData & (~bitsMask); + regData = regData | (valueShifted & bitsMask); + + retVal = rtl8373_smi_write(reg, regData); + if(retVal != RT_ERR_OK) + return RT_ERR_SMI; + #ifdef CONFIG_RTL865X_CLE + if(0x8367B == cleDebuggingDisplay) + PRINT("W[0x%4.4x]=0x%4.4x\n", reg, regData); + #endif +#endif + return RT_ERR_OK; +} +/* Function Name: + * rtl8373_getAsicRegBits + * Description: + * Get bits value of a specified register + * Input: + * reg - register's address + * bits - bits mask for setting + * value - bits value for setting + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter + * Note: + * None + */ +ret_t rtl8373_getAsicRegBits(rtk_uint32 reg, rtk_uint32 bitsMask, rtk_uint32 *pValue) +{ + +#if defined(RTK_X86_ASICDRV) + + rtk_uint32 regData; + ret_t retVal; + rtk_uint32 bitsShift; + + if( !bitsMask ) + return RT_ERR_INPUT; + + bitsShift = 0; + while(!(bitsMask & (1 << bitsShift))) + { + bitsShift++; + if(bitsShift >= RTL8373_REGBITLENGTH) + return RT_ERR_INPUT; + } + + retVal = Access_Read(reg, 4, ®Data); + if(TRUE != retVal) + return RT_ERR_SMI; + + *pValue = (regData & bitsMask) >> bitsShift; + + if(0x8367B == cleDebuggingDisplay) + PRINT("R[0x%4.4x]=0x%4.4x\n", reg, regData); + +#elif defined(CONFIG_RTL8373_ASICDRV_TEST) + rtk_uint32 bitsShift; + + if( !bitsMask ) + return RT_ERR_INPUT; + + bitsShift = 0; + while(!(bitsMask & (1 << bitsShift))) + { + bitsShift++; + if(bitsShift >= RTL8373_REGBITLENGTH) + return RT_ERR_INPUT; + } + + if(reg >= CLE_VIRTUAL_REG_SIZE) + return RT_ERR_OUT_OF_RANGE; + + *pValue = (CleVirtualReg[reg] & bitsMask) >> bitsShift; + + if(0x8367B == cleDebuggingDisplay) + PRINT("R[0x%4.4x]=0x%4.4x\n", reg, CleVirtualReg[reg]); + +#elif defined(EMBEDDED_SUPPORT) + rtk_uint32 regData; + rtk_uint32 bitsShift; + + if(reg > RTL8373_REGDATAMAX ) + return RT_ERR_INPUT; + + if(bitsMask >= (1UL << RTL8373_REGBITLENGTH) ) + return RT_ERR_INPUT; + + bitsShift = 0; + while(!(bitsMask & (1UL << bitsShift))) + { + bitsShift++; + if(bitsShift >= RTL8373_REGBITLENGTH) + return RT_ERR_INPUT; + } + + regData = getReg(reg); + *value = (regData & bitsMask) >> bitsShift; + +#else + rtk_uint32 regData; + ret_t retVal; + rtk_uint32 bitsShift; + + if( !bitsMask ) + return RT_ERR_INPUT; + + bitsShift = 0; + while(!(bitsMask & (1 << bitsShift))) + { + bitsShift++; + if(bitsShift >= RTL8373_REGBITLENGTH) + return RT_ERR_INPUT; + } + + retVal = rtl8373_smi_read(reg, ®Data); + if(retVal != RT_ERR_OK) return RT_ERR_SMI; + + *pValue = (regData & bitsMask) >> bitsShift; + #ifdef CONFIG_RTL865X_CLE + if(0x8367B == cleDebuggingDisplay) + PRINT("R[0x%4.4x]=0x%4.4x\n",reg, regData); + #endif + +#endif + return RT_ERR_OK; +} +/* Function Name: + * rtl8373_setAsicReg + * Description: + * Set content of asic register + * Input: + * reg - register's address + * value - Value setting to register + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * The value will be set to ASIC mapping address only and it is always return RT_ERR_OK while setting un-mapping address registers + */ +ret_t rtl8373_setAsicReg(rtk_uint32 reg, rtk_uint32 value) +{ +#if defined(RTK_X86_ASICDRV)/*RTK-CNSD2-NickWu-20061222: for x86 compile*/ + + ret_t retVal; + + retVal = Access_Write(reg,4,value); + if(TRUE != retVal) + return RT_ERR_SMI; + + if(0x8367B == cleDebuggingDisplay) + PRINT("W[0x%8.8x]=0x%8.8x\n",reg,value); + +#elif defined(CONFIG_RTL8373_ASICDRV_TEST) + #if 0 + /*MIBs emulating*/ + if(reg == RTL8373_REG_MIB_ADDRESS) + { + CleVirtualReg[RTL8373_REG_MIB_COUNTER0] = 0x1; + CleVirtualReg[RTL8373_REG_MIB_COUNTER0+1] = 0x2; + CleVirtualReg[RTL8373_REG_MIB_COUNTER0+2] = 0x3; + CleVirtualReg[RTL8373_REG_MIB_COUNTER0+3] = 0x4; + } + #endif + if(reg >= CLE_VIRTUAL_REG_SIZE) + return RT_ERR_OUT_OF_RANGE; + + CleVirtualReg[reg] = value; + + if(0x8367B == cleDebuggingDisplay) + PRINT("W[0x%8.8x]=0x%8.8x\n",reg,CleVirtualReg[reg]); + +#elif defined(EMBEDDED_SUPPORT) + if(reg > RTL8373_REGDATAMAX || value > RTL8373_REGDATAMAX ) + return RT_ERR_INPUT; + + setReg(reg, value); + +#else + ret_t retVal; + + retVal = rtl8373_smi_write(reg, value); + if(retVal != RT_ERR_OK) + return RT_ERR_SMI; + #ifdef CONFIG_RTL865X_CLE + if(0x8367B == cleDebuggingDisplay) + PRINT("W[0x%4.4x]=0x%4.4x\n",reg,value); + #endif + +#endif + + return RT_ERR_OK; +} +/* Function Name: + * rtl8373_getAsicReg + * Description: + * Get content of asic register + * Input: + * reg - register's address + * value - Value setting to register + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * Value 0x0000 will be returned for ASIC un-mapping address + */ +ret_t rtl8373_getAsicReg(rtk_uint32 reg, rtk_uint32 *pValue) +{ + +#if defined(RTK_X86_ASICDRV) + + rtk_uint32 regData; + ret_t retVal; + + retVal = Access_Read(reg, 4, ®Data); + + if(TRUE != retVal) + return RT_ERR_SMI; + + *pValue = regData; + + if(0x8367B == cleDebuggingDisplay) + PRINT("R[0x%4.4x]=0x%4.4x\n", reg, regData); + +#elif defined(CONFIG_RTL8373_ASICDRV_TEST) + if(reg >= CLE_VIRTUAL_REG_SIZE) + return RT_ERR_OUT_OF_RANGE; + + *pValue = CleVirtualReg[reg]; + + if(0x8367B == cleDebuggingDisplay) + PRINT("R[0x%8.8x]=0x%8.8x\n", reg, CleVirtualReg[reg]); + +#elif defined(EMBEDDED_SUPPORT) + if(reg > RTL8373_REGDATAMAX ) + return RT_ERR_INPUT; + + *value = getReg(reg); + +#else + rtk_uint32 regData; + ret_t retVal; + + retVal = rtl8373_smi_read(reg, ®Data); + if(retVal != RT_ERR_OK) + return RT_ERR_SMI; + + *pValue = regData; + #ifdef CONFIG_RTL865X_CLE + if(0x8367B == cleDebuggingDisplay) + PRINT("R[0x%8.8x]=0x%8.8x\n", reg, regData); + #endif + +#endif + + return RT_ERR_OK; +} + diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/rtl8373_asicdrv.h b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/rtl8373_asicdrv.h new file mode 100755 index 00000000..2f3217e9 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/rtl8373_asicdrv.h @@ -0,0 +1,139 @@ +#ifndef _RTL8373_ASICDRV_H_ +#define _RTL8373_ASICDRV_H_ + +#include +#include +#include + +#define RTL8373_REGBITLENGTH (32) +#define RTL8373_REGDATAMAX (0xFFFFFFFF) +#define RTL8373_REG_ADDR_STEP (4) +#define RTL8373_PHYBITLENGTH (16) +#define RTL8373_PHYDATAMAX (0xFFFF) + +#define RTL8373_QOS_RATE_INPUT_MAX (0x1FFFF * 8) +#define RTL8373_QOS_RATE_INPUT_MAX_HSG (0x989680) +#define RTL8373_QOS_PPS_INPUT_MAX (0xE310B8) + +#define RTL8373_PORTNO (10) +#define RTL8373_PORTIDMAX (RTL8373_PORTNO-1) +#define RTL8373_PMSKMAX ((1<<(RTL8373_PORTNO))-1) +#define RTL8373_PORTMASK (0x3FF) + +#define RTL8373_PRIMAX (7) +#define RTL8373_DSCPMAX (63) + +#define RTL8373_VIDMAX (0xFFF) +#define RTL8373_FIDMAX (15) +#define RTL8373_MSTIMAX (15) + +#define RTL8373_VLAN_4KTABLE_LEN (1) +#define RTL8373_VLAN_BUSY_CHECK_NO (10) + +#define RTL8373_C2SIDXMAX (127) + +#define RTL8373_SVIDXNO (0x1000) +#define RTL8373_SVIDXMAX (RTL8373_SVIDXNO-1) + +#define RTL8373_LOGGINGNO (64) +#define RTL8373_LOGGINGMAX (RTL8373_LOGGINGNO-1) + +#define RTL8373_QUEUENO (8) +#define RTL8373_QIDMAX (RTL8373_QUEUENO-1) + +#define RTL8373_GPIO_PIN_NUM (64) +#define RTL8373_GPIO_MAX_PIN_NUM (GPIO_PIN_NUM -1) + + +#define RTL8373_METERNO (64) +#define RTL8373_METERMAX (RTL8373_METERNO-1) +#define RTL8373_METERBUCKETSIZEMAX (0xFFFFFFF) + +#define RTL8373_PHY_BUSY_CHECK_COUNTER (1000) +#define RTL8373_MACSEC_POLLCNT (1000) + +#define RTL8373_QOS_GRANULARTY_MAX (0x7FFFF) +#define RTL8373_QOS_GRANULARTY_LSB_MASK (0xFFFF) +#define RTL8373_QOS_GRANULARTY_LSB_OFFSET (0) +#define RTL8373_QOS_GRANULARTY_MSB_MASK (0x70000) +#define RTL8373_QOS_GRANULARTY_MSB_OFFSET (16) + +#define RTL8373_QOS_GRANULARTY_UNIT_KBPS (8) + +#define RTL8373_QOS_RATE_INPUT_MAX (0x1FFFF * 8) +#define RTL8373_QOS_RATE_INPUT_MAX_HSG (0x989680) +#define RTL8373_QOS_RATE_INPUT_MIN (8) +#define RTL8373_QOS_PPS_INPUT_MAX (0xE310B8) +#define RTL8373_QOS_PPS_INPUT_MIN 1 + +#define RTL8373_QUEUE_MASK (0xFF) + +#define RTL8373_DISABLE_L2_LEARN_NO (2) +#define RTL8373_DISABLE_L2_LEARN_MAX (RTL8373_DISABLE_L2_LEARN_NO -1) + + +/* the above macro is generated by genDotH */ +#define RTL8370UG_VALID_REG_NO (5000) + +/*======================================================================= + * Enum + *========================================================================*/ +enum RTL8370UG_TABLE_ACCESS_EXECUTE +{ + TB_NOT_EXECUTE = 0, + TB_EXECUTE, +}; + + +enum RTL8370UG_TABLE_ACCESS_OP +{ + TB_OP_READ = 0, + TB_OP_WRITE +}; + +enum RTL8370UG_TABLE_ACCESS_TARGET +{ + TB_TARGET_ACLRULE = 1, + TB_TARGET_ACLACT, + TB_TARGET_CVLAN, + TB_TARGET_L2, + TB_TARGET_IGMP_GROUP, + TB_TARGET_HSA, + TB_TARGET_HSB +}; + +/* the above macro is generated by genDotH */ +#define RTL8373_VALID_REG_NO 5000 + +/*======================================================================= + * Enum + *========================================================================*/ + + +#define RTL8373_TABLE_ACCESS_REG_DATA(op, target) ((op << 3) | target) + +/*======================================================================= + * Structures + *========================================================================*/ + + +#ifdef __cplusplus +extern "C" { +#endif +extern ret_t rtl8373_setAsicRegBit(rtk_uint32 reg, rtk_uint32 bit, rtk_uint32 value); +extern ret_t rtl8373_getAsicRegBit(rtk_uint32 reg, rtk_uint32 bit, rtk_uint32 *pValue); + +extern ret_t rtl8373_setAsicRegBits(rtk_uint32 reg, rtk_uint32 bits, rtk_uint32 value); +extern ret_t rtl8373_getAsicRegBits(rtk_uint32 reg, rtk_uint32 bits, rtk_uint32 *pValue); + +extern ret_t rtl8373_setAsicReg(rtk_uint32 reg, rtk_uint32 value); +extern ret_t rtl8373_getAsicReg(rtk_uint32 reg, rtk_uint32 *pValue); + +#ifdef __cplusplus +} +#endif + + + +#endif /*#ifndef _RTL8373_ASICDRV_H_*/ + diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/rtl8373_regField_list.c b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/rtl8373_regField_list.c new file mode 100755 index 00000000..5cadc7bd --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/rtl8373_regField_list.c @@ -0,0 +1,32001 @@ +/* + * ## Please DO NOT edit this file!! ## + * This file is auto-generated from the register source files. + * Any modifications to this file will be LOST when it is re-generated. + * + * ---------------------------------------------------------------- + * (C) Copyright 2009-2016 Realtek Semiconductor Corp. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * ---------------------------------------------------------------- + * Purpose: chip register definition and structure of RTL8373 + * + * ---------------------------------------------------------------- + */ + +#include "rtl8373_reg_definition.h" +#include "rtl8373_reg_struct.h" + +/* Module: Chip Information */ +rtk_regField_t MODEL_NAME_INFO_FIELDS[] = +{ + { /* name */ RTL_IDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ MODEL_CHAR_1STf, + /* lsp */ 11, + /* len */ 5 + }, + { /* name */ MODEL_CHAR_2NDf, + /* lsp */ 6, + /* len */ 5 + }, + { /* name */ TEST_CUTf, + /* lsp */ 4, + /* len */ 2 + }, + { /* name */ RTL_VIDf, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t CHIP_MODE_INFO_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ DEV_PRESENTf, + /* lsp */ 14, + /* len */ 2 + }, + { /* name */ RESERVEDf, + /* lsp */ 0, + /* len */ 14 + }, +}; + +rtk_regField_t CHIP_INFO_FIELDS[] = +{ + { /* name */ RL_VIDf, + /* lsp */ 28, + /* len */ 4 + }, + { /* name */ MCIDf, + /* lsp */ 24, + /* len */ 4 + }, + { /* name */ BO_CHIP_MODE_ROf, + /* lsp */ 20, + /* len */ 4 + }, + { /* name */ CHIP_INFO_ENf, + /* lsp */ 16, + /* len */ 4 + }, + { /* name */ RL_IDf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t CHIP_UUID_REG_FIELDS[] = +{ + { /* name */ CHIP_UUIDf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t CHIP_LOT_NO_REG0_FIELDS[] = +{ + { /* name */ CHIP_LOT_NO_REG0f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t CHIP_LOT_NO_REG1_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ CHIP_LOT_NO_CRCf, + /* lsp */ 8, + /* len */ 8 + }, + { /* name */ CHIP_LOT_NO_REG1f, + /* lsp */ 0, + /* len */ 8 + }, +}; + +rtk_regField_t SMI_MMD_SP_FIELDS[] = +{ + { /* name */ SMI_MMD_SPf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t CFG_DMY_CHIP_INFO_1_FIELDS[] = +{ + { /* name */ CFG_DMY_1f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +/* Module: Reset */ +rtk_regField_t RST_GLB_CTRL_0_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 20 + }, + { /* name */ CFG_EN_8051f, + /* lsp */ 11, + /* len */ 1 + }, + { /* name */ GPHY_ENf, + /* lsp */ 7, + /* len */ 4 + }, + { /* name */ SDS_REG_RSTf, + /* lsp */ 6, + /* len */ 1 + }, + { /* name */ SW_RSTf, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ DW8051_RSTf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ SW_SERDES_RSTf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ SW_NIC_RSTf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ SW_Q_RSTf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ SW_CHIP_RSTf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t RST_GLB_DBG_0_FIELDS[] = +{ + { /* name */ DBGO_RST_0f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t RST_GLB_DBG_1_FIELDS[] = +{ + { /* name */ DBGO_RST_1f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +/* Module: BIST & BISR */ +rtk_regField_t MAC_BIST_MODE_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 8, + /* len */ 24 + }, + { /* name */ BIST_MODE_TXFIFO_PG03f, + /* lsp */ 7, + /* len */ 1 + }, + { /* name */ BIST_MODE_RXFIFO_PG03f, + /* lsp */ 6, + /* len */ 1 + }, + { /* name */ BIST_MODE_TXFIFO_PG02f, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ BIST_MODE_RXFIFO_PG02f, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ BIST_MODE_TXFIFO_PG01f, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ BIST_MODE_RXFIFO_PG01f, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ BIST_MODE_TXFIFO_PG00f, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ BIST_MODE_RXFIFO_PG00f, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t MAC_DRF_BIST_MODE_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 8, + /* len */ 24 + }, + { /* name */ DRF_BIST_MODE_TXFIFO_PG03f, + /* lsp */ 7, + /* len */ 1 + }, + { /* name */ DRF_BIST_MODE_RXFIFO_PG03f, + /* lsp */ 6, + /* len */ 1 + }, + { /* name */ DRF_BIST_MODE_TXFIFO_PG02f, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ DRF_BIST_MODE_RXFIFO_PG02f, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ DRF_BIST_MODE_TXFIFO_PG01f, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ DRF_BIST_MODE_RXFIFO_PG01f, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ DRF_BIST_MODE_TXFIFO_PG00f, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ DRF_BIST_MODE_RXFIFO_PG00f, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t MAC_BIST_RSTN_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 8, + /* len */ 24 + }, + { /* name */ BIST_RSTN_TXFIFO_PG03f, + /* lsp */ 7, + /* len */ 1 + }, + { /* name */ BIST_RSTN_RXFIFO_PG03f, + /* lsp */ 6, + /* len */ 1 + }, + { /* name */ BIST_RSTN_TXFIFO_PG02f, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ BIST_RSTN_RXFIFO_PG02f, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ BIST_RSTN_TXFIFO_PG01f, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ BIST_RSTN_RXFIFO_PG01f, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ BIST_RSTN_TXFIFO_PG00f, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ BIST_RSTN_RXFIFO_PG00f, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t MAC_BIST_LOOP_MODE_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 8, + /* len */ 24 + }, + { /* name */ BIST_LOOP_MODE_TXFIFO_PG03f, + /* lsp */ 7, + /* len */ 1 + }, + { /* name */ BIST_LOOP_MODE_RXFIFO_PG03f, + /* lsp */ 6, + /* len */ 1 + }, + { /* name */ BIST_LOOP_MODE_TXFIFO_PG02f, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ BIST_LOOP_MODE_RXFIFO_PG02f, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ BIST_LOOP_MODE_TXFIFO_PG01f, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ BIST_LOOP_MODE_RXFIFO_PG01f, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ BIST_LOOP_MODE_TXFIFO_PG00f, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ BIST_LOOP_MODE_RXFIFO_PG00f, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t MAC_BIST_DYN_READ_EN_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 8, + /* len */ 24 + }, + { /* name */ BIST_DYN_READ_EN_TXFIFO_PG03f, + /* lsp */ 7, + /* len */ 1 + }, + { /* name */ BIST_DYN_READ_EN_RXFIFO_PG03f, + /* lsp */ 6, + /* len */ 1 + }, + { /* name */ BIST_DYN_READ_EN_TXFIFO_PG02f, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ BIST_DYN_READ_EN_RXFIFO_PG02f, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ BIST_DYN_READ_EN_TXFIFO_PG01f, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ BIST_DYN_READ_EN_RXFIFO_PG01f, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ BIST_DYN_READ_EN_TXFIFO_PG00f, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ BIST_DYN_READ_EN_RXFIFO_PG00f, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t MAC_DRF_TEST_RESUME_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 8, + /* len */ 24 + }, + { /* name */ DRF_TEST_RESUME_TXFIFO_PG03f, + /* lsp */ 7, + /* len */ 1 + }, + { /* name */ DRF_TEST_RESUME_RXFIFO_PG03f, + /* lsp */ 6, + /* len */ 1 + }, + { /* name */ DRF_TEST_RESUME_TXFIFO_PG02f, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ DRF_TEST_RESUME_RXFIFO_PG02f, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ DRF_TEST_RESUME_TXFIFO_PG01f, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ DRF_TEST_RESUME_RXFIFO_PG01f, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ DRF_TEST_RESUME_TXFIFO_PG00f, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ DRF_TEST_RESUME_RXFIFO_PG00f, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t MAC_DRF_START_PAUSE_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 8, + /* len */ 24 + }, + { /* name */ DRF_START_PAUSE_TXFIFO_PG03f, + /* lsp */ 7, + /* len */ 1 + }, + { /* name */ DRF_START_PAUSE_RXFIFO_PG03f, + /* lsp */ 6, + /* len */ 1 + }, + { /* name */ DRF_START_PAUSE_TXFIFO_PG02f, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ DRF_START_PAUSE_RXFIFO_PG02f, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ DRF_START_PAUSE_TXFIFO_PG01f, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ DRF_START_PAUSE_RXFIFO_PG01f, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ DRF_START_PAUSE_TXFIFO_PG00f, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ DRF_START_PAUSE_RXFIFO_PG00f, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t MAC_MBIST_DONE_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 8, + /* len */ 24 + }, + { /* name */ BIST_DONE_TXFIFO_PG03f, + /* lsp */ 7, + /* len */ 1 + }, + { /* name */ BIST_DONE_RXFIFO_PG03f, + /* lsp */ 6, + /* len */ 1 + }, + { /* name */ BIST_DONE_TXFIFO_PG02f, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ BIST_DONE_RXFIFO_PG02f, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ BIST_DONE_TXFIFO_PG01f, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ BIST_DONE_RXFIFO_PG01f, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ BIST_DONE_TXFIFO_PG00f, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ BIST_DONE_RXFIFO_PG00f, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t MAC_MBIST_DRF_DONE_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 8, + /* len */ 24 + }, + { /* name */ BIST_DRF_DONE_TXFIFO_PG03f, + /* lsp */ 7, + /* len */ 1 + }, + { /* name */ BIST_DRF_DONE_RXFIFO_PG03f, + /* lsp */ 6, + /* len */ 1 + }, + { /* name */ BIST_DRF_DONE_TXFIFO_PG02f, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ BIST_DRF_DONE_RXFIFO_PG02f, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ BIST_DRF_DONE_TXFIFO_PG01f, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ BIST_DRF_DONE_RXFIFO_PG01f, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ BIST_DRF_DONE_TXFIFO_PG00f, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ BIST_DRF_DONE_RXFIFO_PG00f, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t MAC_MBIST_FAIL_PG00_PG01_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 26, + /* len */ 6 + }, + { /* name */ BIST_FAIL_TXFIFO_PG01f, + /* lsp */ 22, + /* len */ 4 + }, + { /* name */ BIST_FAIL_RXFIFO_PG01f, + /* lsp */ 14, + /* len */ 8 + }, + { /* name */ BIST_FAIL_TXFIFO_PG00f, + /* lsp */ 8, + /* len */ 6 + }, + { /* name */ BIST_FAIL_RXFIFO_PG00f, + /* lsp */ 0, + /* len */ 8 + }, +}; + +rtk_regField_t MAC_MBIST_FAIL_PG02_PG03_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 15, + /* len */ 17 + }, + { /* name */ BIST_FAIL_TXFIFO_PG03f, + /* lsp */ 14, + /* len */ 1 + }, + { /* name */ BIST_FAIL_RXFIFO_PG03f, + /* lsp */ 12, + /* len */ 2 + }, + { /* name */ BIST_FAIL_TXFIFO_PG02f, + /* lsp */ 6, + /* len */ 6 + }, + { /* name */ BIST_FAIL_RXFIFO_PG02f, + /* lsp */ 0, + /* len */ 6 + }, +}; + +rtk_regField_t MAC_MBIST_DRF_FAIL_PG00_PG01_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 26, + /* len */ 6 + }, + { /* name */ BIST_DRF_FAIL_TXFIFO_PG01f, + /* lsp */ 22, + /* len */ 4 + }, + { /* name */ BIST_DRF_FAIL_RXFIFO_PG01f, + /* lsp */ 14, + /* len */ 8 + }, + { /* name */ BIST_DRF_FAIL_TXFIFO_PG00f, + /* lsp */ 8, + /* len */ 6 + }, + { /* name */ BIST_DRF_FAIL_RXFIFO_PG00f, + /* lsp */ 0, + /* len */ 8 + }, +}; + +rtk_regField_t MAC_MBIST_DRF_FAIL_PG02_PG03_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 15, + /* len */ 17 + }, + { /* name */ BIST_DRF_FAIL_TXFIFO_PG03f, + /* lsp */ 14, + /* len */ 1 + }, + { /* name */ BIST_DRF_FAIL_RXFIFO_PG03f, + /* lsp */ 12, + /* len */ 2 + }, + { /* name */ BIST_DRF_FAIL_TXFIFO_PG02f, + /* lsp */ 6, + /* len */ 6 + }, + { /* name */ BIST_DRF_FAIL_RXFIFO_PG02f, + /* lsp */ 0, + /* len */ 6 + }, +}; + +rtk_regField_t MAC_RXFIFO_LS_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 24, + /* len */ 8 + }, + { /* name */ CFG_RXFIFO_LS_PG03f, + /* lsp */ 22, + /* len */ 2 + }, + { /* name */ CFG_RXFIFO_LS_PG02f, + /* lsp */ 16, + /* len */ 6 + }, + { /* name */ CFG_RXFIFO_LS_PG01f, + /* lsp */ 8, + /* len */ 8 + }, + { /* name */ CFG_RXFIFO_LS_PG00f, + /* lsp */ 0, + /* len */ 8 + }, +}; + +rtk_regField_t MAC_RXFIFO_RMEA_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 24, + /* len */ 8 + }, + { /* name */ CFG_RXFIFO_RMEA_PG03f, + /* lsp */ 22, + /* len */ 2 + }, + { /* name */ CFG_RXFIFO_RMEA_PG02f, + /* lsp */ 16, + /* len */ 6 + }, + { /* name */ CFG_RXFIFO_RMEA_PG01f, + /* lsp */ 8, + /* len */ 8 + }, + { /* name */ CFG_RXFIFO_RMEA_PG00f, + /* lsp */ 0, + /* len */ 8 + }, +}; + +rtk_regField_t MAC_RXFIFO_RMA_PG00_FIELDS[] = +{ + { /* name */ CFG_RXFIFO_RMA_7_PG00f, + /* lsp */ 28, + /* len */ 4 + }, + { /* name */ CFG_RXFIFO_RMA_6_PG00f, + /* lsp */ 24, + /* len */ 4 + }, + { /* name */ CFG_RXFIFO_RMA_5_PG00f, + /* lsp */ 20, + /* len */ 4 + }, + { /* name */ CFG_RXFIFO_RMA_4_PG00f, + /* lsp */ 16, + /* len */ 4 + }, + { /* name */ CFG_RXFIFO_RMA_3_PG00f, + /* lsp */ 12, + /* len */ 4 + }, + { /* name */ CFG_RXFIFO_RMA_2_PG00f, + /* lsp */ 8, + /* len */ 4 + }, + { /* name */ CFG_RXFIFO_RMA_1_PG00f, + /* lsp */ 4, + /* len */ 4 + }, + { /* name */ CFG_RXFIFO_RMA_0_PG00f, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t MAC_RXFIFO_RMA_PG01_FIELDS[] = +{ + { /* name */ CFG_RXFIFO_RMA_7_PG01f, + /* lsp */ 28, + /* len */ 4 + }, + { /* name */ CFG_RXFIFO_RMA_6_PG01f, + /* lsp */ 24, + /* len */ 4 + }, + { /* name */ CFG_RXFIFO_RMA_5_PG01f, + /* lsp */ 20, + /* len */ 4 + }, + { /* name */ CFG_RXFIFO_RMA_4_PG01f, + /* lsp */ 16, + /* len */ 4 + }, + { /* name */ CFG_RXFIFO_RMA_3_PG01f, + /* lsp */ 12, + /* len */ 4 + }, + { /* name */ CFG_RXFIFO_RMA_2_PG01f, + /* lsp */ 8, + /* len */ 4 + }, + { /* name */ CFG_RXFIFO_RMA_1_PG01f, + /* lsp */ 4, + /* len */ 4 + }, + { /* name */ CFG_RXFIFO_RMA_0_PG01f, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t MAC_RXFIFO_RMA_PG02_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 24, + /* len */ 8 + }, + { /* name */ CFG_RXFIFO_RMA_5_PG02f, + /* lsp */ 20, + /* len */ 4 + }, + { /* name */ CFG_RXFIFO_RMA_4_PG02f, + /* lsp */ 16, + /* len */ 4 + }, + { /* name */ CFG_RXFIFO_RMA_3_PG02f, + /* lsp */ 12, + /* len */ 4 + }, + { /* name */ CFG_RXFIFO_RMA_2_PG02f, + /* lsp */ 8, + /* len */ 4 + }, + { /* name */ CFG_RXFIFO_RMA_1_PG02f, + /* lsp */ 4, + /* len */ 4 + }, + { /* name */ CFG_RXFIFO_RMA_0_PG02f, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t MAC_RXFIFO_RMA_PG03_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 8, + /* len */ 24 + }, + { /* name */ CFG_RXFIFO_RMA_1_PG03f, + /* lsp */ 4, + /* len */ 4 + }, + { /* name */ CFG_RXFIFO_RMA_0_PG03f, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t MAC_RXFIFO_RMEB_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 24, + /* len */ 8 + }, + { /* name */ CFG_RXFIFO_RMEB_PG03f, + /* lsp */ 22, + /* len */ 2 + }, + { /* name */ CFG_RXFIFO_RMEB_PG02f, + /* lsp */ 16, + /* len */ 6 + }, + { /* name */ CFG_RXFIFO_RMEB_PG01f, + /* lsp */ 8, + /* len */ 8 + }, + { /* name */ CFG_RXFIFO_RMEB_PG00f, + /* lsp */ 0, + /* len */ 8 + }, +}; + +rtk_regField_t MAC_RXFIFO_RMB_PG00_FIELDS[] = +{ + { /* name */ CFG_RXFIFO_RMB_7_PG00f, + /* lsp */ 28, + /* len */ 4 + }, + { /* name */ CFG_RXFIFO_RMB_6_PG00f, + /* lsp */ 24, + /* len */ 4 + }, + { /* name */ CFG_RXFIFO_RMB_5_PG00f, + /* lsp */ 20, + /* len */ 4 + }, + { /* name */ CFG_RXFIFO_RMB_4_PG00f, + /* lsp */ 16, + /* len */ 4 + }, + { /* name */ CFG_RXFIFO_RMB_3_PG00f, + /* lsp */ 12, + /* len */ 4 + }, + { /* name */ CFG_RXFIFO_RMB_2_PG00f, + /* lsp */ 8, + /* len */ 4 + }, + { /* name */ CFG_RXFIFO_RMB_1_PG00f, + /* lsp */ 4, + /* len */ 4 + }, + { /* name */ CFG_RXFIFO_RMB_0_PG00f, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t MAC_RXFIFO_RMB_PG01_FIELDS[] = +{ + { /* name */ CFG_RXFIFO_RMB_7_PG01f, + /* lsp */ 28, + /* len */ 4 + }, + { /* name */ CFG_RXFIFO_RMB_6_PG01f, + /* lsp */ 24, + /* len */ 4 + }, + { /* name */ CFG_RXFIFO_RMB_5_PG01f, + /* lsp */ 20, + /* len */ 4 + }, + { /* name */ CFG_RXFIFO_RMB_4_PG01f, + /* lsp */ 16, + /* len */ 4 + }, + { /* name */ CFG_RXFIFO_RMB_3_PG01f, + /* lsp */ 12, + /* len */ 4 + }, + { /* name */ CFG_RXFIFO_RMB_2_PG01f, + /* lsp */ 8, + /* len */ 4 + }, + { /* name */ CFG_RXFIFO_RMB_1_PG01f, + /* lsp */ 4, + /* len */ 4 + }, + { /* name */ CFG_RXFIFO_RMB_0_PG01f, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t MAC_RXFIFO_RMB_PG02_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 24, + /* len */ 8 + }, + { /* name */ CFG_RXFIFO_RMB_5_PG02f, + /* lsp */ 20, + /* len */ 4 + }, + { /* name */ CFG_RXFIFO_RMB_4_PG02f, + /* lsp */ 16, + /* len */ 4 + }, + { /* name */ CFG_RXFIFO_RMB_3_PG02f, + /* lsp */ 12, + /* len */ 4 + }, + { /* name */ CFG_RXFIFO_RMB_2_PG02f, + /* lsp */ 8, + /* len */ 4 + }, + { /* name */ CFG_RXFIFO_RMB_1_PG02f, + /* lsp */ 4, + /* len */ 4 + }, + { /* name */ CFG_RXFIFO_RMB_0_PG02f, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t MAC_RXFIFO_RMB_PG03_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 8, + /* len */ 24 + }, + { /* name */ CFG_RXFIFO_RMB_1_PG03f, + /* lsp */ 4, + /* len */ 4 + }, + { /* name */ CFG_RXFIFO_RMB_0_PG03f, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t MAC_TXFIFO_LS_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 17, + /* len */ 15 + }, + { /* name */ CFG_TXFIFO_LS_PG03f, + /* lsp */ 16, + /* len */ 1 + }, + { /* name */ CFG_TXFIFO_LS_PG02f, + /* lsp */ 10, + /* len */ 6 + }, + { /* name */ CFG_TXFIFO_LS_PG01f, + /* lsp */ 6, + /* len */ 4 + }, + { /* name */ CFG_TXFIFO_LS_PG00f, + /* lsp */ 0, + /* len */ 6 + }, +}; + +rtk_regField_t MAC_TXFIFO_RMEA_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 17, + /* len */ 15 + }, + { /* name */ CFG_TXFIFO_RMEA_PG03f, + /* lsp */ 16, + /* len */ 1 + }, + { /* name */ CFG_TXFIFO_RMEA_PG02f, + /* lsp */ 10, + /* len */ 6 + }, + { /* name */ CFG_TXFIFO_RMEA_PG01f, + /* lsp */ 6, + /* len */ 4 + }, + { /* name */ CFG_TXFIFO_RMEA_PG00f, + /* lsp */ 0, + /* len */ 6 + }, +}; + +rtk_regField_t MAC_TXFIFO_RMA_PG00_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 24, + /* len */ 8 + }, + { /* name */ CFG_TXFIFO_RMA_5_PG00f, + /* lsp */ 20, + /* len */ 4 + }, + { /* name */ CFG_TXFIFO_RMA_4_PG00f, + /* lsp */ 16, + /* len */ 4 + }, + { /* name */ CFG_TXFIFO_RMA_3_PG00f, + /* lsp */ 12, + /* len */ 4 + }, + { /* name */ CFG_TXFIFO_RMA_2_PG00f, + /* lsp */ 8, + /* len */ 4 + }, + { /* name */ CFG_TXFIFO_RMA_1_PG00f, + /* lsp */ 4, + /* len */ 4 + }, + { /* name */ CFG_TXFIFO_RMA_0_PG00f, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t MAC_TXFIFO_RMA_PG01_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ CFG_TXFIFO_RMA_3_PG01f, + /* lsp */ 12, + /* len */ 4 + }, + { /* name */ CFG_TXFIFO_RMA_2_PG01f, + /* lsp */ 8, + /* len */ 4 + }, + { /* name */ CFG_TXFIFO_RMA_1_PG01f, + /* lsp */ 4, + /* len */ 4 + }, + { /* name */ CFG_TXFIFO_RMA_0_PG01f, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t MAC_TXFIFO_RMA_PG02_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 24, + /* len */ 8 + }, + { /* name */ CFG_TXFIFO_RMA_5_PG02f, + /* lsp */ 20, + /* len */ 4 + }, + { /* name */ CFG_TXFIFO_RMA_4_PG02f, + /* lsp */ 16, + /* len */ 4 + }, + { /* name */ CFG_TXFIFO_RMA_3_PG02f, + /* lsp */ 12, + /* len */ 4 + }, + { /* name */ CFG_TXFIFO_RMA_2_PG02f, + /* lsp */ 8, + /* len */ 4 + }, + { /* name */ CFG_TXFIFO_RMA_1_PG02f, + /* lsp */ 4, + /* len */ 4 + }, + { /* name */ CFG_TXFIFO_RMA_0_PG02f, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t MAC_TXFIFO_RMA_PG03_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 28 + }, + { /* name */ CFG_TXFIFO_RMA_0_PG03f, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t MAC_TXFIFO_RMEB_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 17, + /* len */ 15 + }, + { /* name */ CFG_TXFIFO_RMEB_PG03f, + /* lsp */ 16, + /* len */ 1 + }, + { /* name */ CFG_TXFIFO_RMEB_PG02f, + /* lsp */ 10, + /* len */ 6 + }, + { /* name */ CFG_TXFIFO_RMEB_PG01f, + /* lsp */ 6, + /* len */ 4 + }, + { /* name */ CFG_TXFIFO_RMEB_PG00f, + /* lsp */ 0, + /* len */ 6 + }, +}; + +rtk_regField_t MAC_TXFIFO_RMB_PG00_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 24, + /* len */ 8 + }, + { /* name */ CFG_TXFIFO_RMB_5_PG00f, + /* lsp */ 20, + /* len */ 4 + }, + { /* name */ CFG_TXFIFO_RMB_4_PG00f, + /* lsp */ 16, + /* len */ 4 + }, + { /* name */ CFG_TXFIFO_RMB_3_PG00f, + /* lsp */ 12, + /* len */ 4 + }, + { /* name */ CFG_TXFIFO_RMB_2_PG00f, + /* lsp */ 8, + /* len */ 4 + }, + { /* name */ CFG_TXFIFO_RMB_1_PG00f, + /* lsp */ 4, + /* len */ 4 + }, + { /* name */ CFG_TXFIFO_RMB_0_PG00f, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t MAC_TXFIFO_RMB_PG01_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ CFG_TXFIFO_RMB_3_PG01f, + /* lsp */ 12, + /* len */ 4 + }, + { /* name */ CFG_TXFIFO_RMB_2_PG01f, + /* lsp */ 8, + /* len */ 4 + }, + { /* name */ CFG_TXFIFO_RMB_1_PG01f, + /* lsp */ 4, + /* len */ 4 + }, + { /* name */ CFG_TXFIFO_RMB_0_PG01f, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t MAC_TXFIFO_RMB_PG02_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 24, + /* len */ 8 + }, + { /* name */ CFG_TXFIFO_RMB_5_PG02f, + /* lsp */ 20, + /* len */ 4 + }, + { /* name */ CFG_TXFIFO_RMB_4_PG02f, + /* lsp */ 16, + /* len */ 4 + }, + { /* name */ CFG_TXFIFO_RMB_3_PG02f, + /* lsp */ 12, + /* len */ 4 + }, + { /* name */ CFG_TXFIFO_RMB_2_PG02f, + /* lsp */ 8, + /* len */ 4 + }, + { /* name */ CFG_TXFIFO_RMB_1_PG02f, + /* lsp */ 4, + /* len */ 4 + }, + { /* name */ CFG_TXFIFO_RMB_0_PG02f, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t MAC_TXFIFO_RMB_PG03_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 28 + }, + { /* name */ CFG_TXFIFO_RMB_0_PG03f, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t CHIP_ALL_RESULT_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 28 + }, + { /* name */ ALL_BIST_DONEf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ ALL_DRF_BIST_DONEf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ ANY_BIST_FAILf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ ANY_DRF_BIST_FAILf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t CHIP_BISR_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 2, + /* len */ 30 + }, + { /* name */ CFG_BISR_SERIALf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ CFG_BISR_MODEf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t GLB_MBISD_DATA_FIELDS[] = +{ + { /* name */ BISD_DATA_OUTf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t GLB_MBISD_CFG_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 8, + /* len */ 24 + }, + { /* name */ BISD_DATA_SELf, + /* lsp */ 5, + /* len */ 3 + }, + { /* name */ BISD_CLK_SELf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ BISD_CLK_ENf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ BIST_DIAG_MODEf, + /* lsp */ 0, + /* len */ 3 + }, +}; + +rtk_regField_t INGR_BIST_CTRL0_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 7, + /* len */ 25 + }, + { /* name */ CFG_CBUF_BIST_MODEf, + /* lsp */ 6, + /* len */ 1 + }, + { /* name */ CFG_PKB_BIST_MODE_2_0f, + /* lsp */ 3, + /* len */ 3 + }, + { /* name */ CFG_RSC_FIFO_BIST_MODEf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ CFG_DROP_FIFO_BIST_MODEf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ CFG_LL_BIST_MODEf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t INGR_BIST_CTRL1_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 7, + /* len */ 25 + }, + { /* name */ CFG_CBUF_DRF_BIST_MODEf, + /* lsp */ 6, + /* len */ 1 + }, + { /* name */ CFG_PKB_DRF_BIST_MODE_2_0f, + /* lsp */ 3, + /* len */ 3 + }, + { /* name */ CFG_RSC_FIFO_DRF_BIST_MODEf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ CFG_DROP_FIFO_DRF_BIST_MODEf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ CFG_LL_DRF_BIST_MODEf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t INGR_BIST_CTRL2_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 7, + /* len */ 25 + }, + { /* name */ CFG_CBUF_DRF_TEST_RESUMEf, + /* lsp */ 6, + /* len */ 1 + }, + { /* name */ CFG_PKB_DRF_BIST_TEST_RESUME_2_0f, + /* lsp */ 3, + /* len */ 3 + }, + { /* name */ CFG_RSC_FIFO_DRF_TEST_RESUMEf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ CFG_DROP_FIFO_DRF_TEST_RESUMEf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ CFG_LL_DRF_TEST_RESUMEf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t INGR_BIST_CTRL3_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 7, + /* len */ 25 + }, + { /* name */ CFG_CBUF_DRF_BIST_DYN_RD_ENf, + /* lsp */ 6, + /* len */ 1 + }, + { /* name */ CFG_PKB_DRF_BIST_DYN_RD_EN_2_0f, + /* lsp */ 3, + /* len */ 3 + }, + { /* name */ CFG_RSC_FIFO_DRF_BIST_DYN_RD_ENf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ CFG_DROP_FIFO_DRF_BIST_DYN_RD_ENf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ CFG_LL_DRF_BIST_DYN_RD_ENf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t INGR_BIST_CTRL4_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 7, + /* len */ 25 + }, + { /* name */ CFG_CBUF_BIST_LOOP_MODEf, + /* lsp */ 6, + /* len */ 1 + }, + { /* name */ CFG_PKB_BIST_LOOP_MODE_2_0f, + /* lsp */ 3, + /* len */ 3 + }, + { /* name */ CFG_RSC_FIFO_BIST_LOOP_MODEf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ CFG_DROP_FIFO_BIST_LOOP_MODEf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ CFG_LL_BIST_LOOP_MODEf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t INGR_BIST_CTRL5_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 28, + /* len */ 4 + }, + { /* name */ CFG_CBUF_BIST_GRP_ENf, + /* lsp */ 18, + /* len */ 10 + }, + { /* name */ CFG_PKB_BIST_GRP_EN_2_0f, + /* lsp */ 0, + /* len */ 18 + }, +}; + +rtk_regField_t INGR_BIST_CTRL6_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 7, + /* len */ 25 + }, + { /* name */ CFG_CBUF_BIST_RSTBf, + /* lsp */ 6, + /* len */ 1 + }, + { /* name */ CFG_PKB_BIST_RSTB_2_0f, + /* lsp */ 3, + /* len */ 3 + }, + { /* name */ CFG_RSC_FIFO_BIST_RSTBf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ CFG_DROP_FIFO_BIST_RSTBf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ CFG_LL_BIST_RSTBf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t INGR_BIST_RSLT0_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 7, + /* len */ 25 + }, + { /* name */ CBUF_DRF_START_PAUSEf, + /* lsp */ 6, + /* len */ 1 + }, + { /* name */ PKB_DRF_START_PAUSE_2_0f, + /* lsp */ 3, + /* len */ 3 + }, + { /* name */ RSC_FIFO_DRF_START_PAUSEf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ DROP_FIFO_DRF_START_PAUSEf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ LL_DRF_START_PAUSEf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t INGR_BIST_RSLT1_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 7, + /* len */ 25 + }, + { /* name */ CBUF_BIST_DONEf, + /* lsp */ 6, + /* len */ 1 + }, + { /* name */ PKB_BIST_DONE_2_0f, + /* lsp */ 3, + /* len */ 3 + }, + { /* name */ RSC_FIFO_BIST_DONEf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ DROP_FIFO_BIST_DONEf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ LL_BIST_DONEf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t INGR_BIST_RSLT2_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 7, + /* len */ 25 + }, + { /* name */ CBUF_DRF_BIST_DONEf, + /* lsp */ 6, + /* len */ 1 + }, + { /* name */ PKB_DRF_BIST_DONE_2_0f, + /* lsp */ 3, + /* len */ 3 + }, + { /* name */ RSC_FIFO_DRF_BIST_DONEf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ DROP_FIFO_DRF_BIST_DONEf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ LL_DRF_BIST_DONEf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t INGR_BIST_RSLT3_FIELDS[] = +{ + { /* name */ CBUF_BIST_FAILf, + /* lsp */ 22, + /* len */ 10 + }, + { /* name */ PKB_BIST_FAIL_2_0f, + /* lsp */ 4, + /* len */ 18 + }, + { /* name */ RSC_FIFO_BIST_FAILf, + /* lsp */ 2, + /* len */ 2 + }, + { /* name */ DROP_FIFO_BIST_FAILf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ LL_BIST_FAILf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t INGR_BIST_RSLT4_FIELDS[] = +{ + { /* name */ CBUF_DRF_BIST_FAILf, + /* lsp */ 22, + /* len */ 10 + }, + { /* name */ PKB_DRF_BIST_FAIL_2_0f, + /* lsp */ 4, + /* len */ 18 + }, + { /* name */ RSC_FIFO_DRF_BIST_FAILf, + /* lsp */ 2, + /* len */ 2 + }, + { /* name */ DROP_FIFO_DRF_BIST_FAILf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ LL_DRF_BIST_FAILf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t INGR_SRAM_CTRL_0_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 28, + /* len */ 4 + }, + { /* name */ CFG_CBUF_SRAM_RMEf, + /* lsp */ 27, + /* len */ 1 + }, + { /* name */ CFG_CBUF_SRAM_RMf, + /* lsp */ 23, + /* len */ 4 + }, + { /* name */ CFG_CUBF_SRAM_LSf, + /* lsp */ 22, + /* len */ 1 + }, + { /* name */ CFG_CBUF_BIST_TEST1f, + /* lsp */ 21, + /* len */ 1 + }, + { /* name */ CFG_PKB_SRAM_RME_2_0f, + /* lsp */ 18, + /* len */ 3 + }, + { /* name */ CFG_PKB_SRAM_RM_2_0f, + /* lsp */ 6, + /* len */ 12 + }, + { /* name */ CFG_PKB_SRAM_LS_2_0f, + /* lsp */ 3, + /* len */ 3 + }, + { /* name */ CFG_PKB_BIST_TEST1_2_0f, + /* lsp */ 0, + /* len */ 3 + }, +}; + +rtk_regField_t INGR_SRAM_CTRL_1_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 21, + /* len */ 11 + }, + { /* name */ CFG_RSC_FIFO_SRAM_RMEf, + /* lsp */ 20, + /* len */ 1 + }, + { /* name */ CFG_RSC_FIFO_SRAM_RMf, + /* lsp */ 16, + /* len */ 4 + }, + { /* name */ CFG_RSC_FIFO_SRAM_LSf, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ CFG_RSC_FIFO_BIST_TEST1f, + /* lsp */ 14, + /* len */ 1 + }, + { /* name */ CFG_DROP_FIFO_SRAM_RMEf, + /* lsp */ 13, + /* len */ 1 + }, + { /* name */ CFG_DROP_FIFO_SRAM_RMf, + /* lsp */ 9, + /* len */ 4 + }, + { /* name */ CFG_DROP_FIFO_SRAM_LSf, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ CFG_DROP_FIFO_BIST_TEST1f, + /* lsp */ 7, + /* len */ 1 + }, + { /* name */ CFG_LL_SRAM_RMEf, + /* lsp */ 6, + /* len */ 1 + }, + { /* name */ CFG_LL_SRAM_RMf, + /* lsp */ 2, + /* len */ 4 + }, + { /* name */ CFG_LL_SRAM_LSf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ CFG_LL_BIST_TEST1f, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t INGR_BISR_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 2, + /* len */ 30 + }, + { /* name */ PKB_SECOND_RUN_ENf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ PKB_HOLD_REMAPf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t INGR_BISR_RSLT0_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 27, + /* len */ 5 + }, + { /* name */ BYPASS_PG_VLD_2_0f, + /* lsp */ 24, + /* len */ 3 + }, + { /* name */ BYPASS_PG_AD1_11_0f, + /* lsp */ 12, + /* len */ 12 + }, + { /* name */ BYPASS_PG_AD0_11_0f, + /* lsp */ 0, + /* len */ 12 + }, +}; + +rtk_regField_t INGR_BISR_RSLT1_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ BYPASS_PG_AD2_11_0f, + /* lsp */ 4, + /* len */ 12 + }, + { /* name */ PKB_BISR_FAILf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ PKB_BISR_DONEf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ PKB_DRF_BISR_FAILf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ PKB_DRF_BISR_DONEf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t INGR_BISR_RSLT2_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 13, + /* len */ 19 + }, + { /* name */ CFG_BYPASS_PG_AD2_11_0f, + /* lsp */ 1, + /* len */ 12 + }, + { /* name */ CFG_FAIL_AD_ENf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t INGR_BISR_RSLT3_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 27, + /* len */ 5 + }, + { /* name */ CFG_BYPASS_PG_VLD_2_0f, + /* lsp */ 24, + /* len */ 3 + }, + { /* name */ CFG_BYPASS_PG_AD1_11_0f, + /* lsp */ 12, + /* len */ 12 + }, + { /* name */ CFG_BYPASS_PG_AD0_11_0f, + /* lsp */ 0, + /* len */ 12 + }, +}; + +rtk_regField_t EGR_BIST_CTRL0_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 20, + /* len */ 12 + }, + { /* name */ BHSA_TEST_RESUMEf, + /* lsp */ 19, + /* len */ 1 + }, + { /* name */ DPC_DRF_TEST_RESUMEf, + /* lsp */ 18, + /* len */ 1 + }, + { /* name */ TXQ_DRF_TEST_RESUME_1_0f, + /* lsp */ 16, + /* len */ 2 + }, + { /* name */ RESERVEDf, + /* lsp */ 3, + /* len */ 13 + }, + { /* name */ BHSA_BIST_RSTBf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ DPC_BIST_RSTBf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ TXQ_BIST_RSTBf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t EGR_BIST_CTRL1_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 20, + /* len */ 12 + }, + { /* name */ BHSA_DRF_BIST_MODEf, + /* lsp */ 19, + /* len */ 1 + }, + { /* name */ DPC_DRF_BIST_MODEf, + /* lsp */ 18, + /* len */ 1 + }, + { /* name */ TXQ_DRF_BIST_MODE_1_0f, + /* lsp */ 16, + /* len */ 2 + }, + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 12 + }, + { /* name */ BHSA_BIST_MODEf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ DPC_BIST_MODEf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ TXQ_BIST_MODE_1_0f, + /* lsp */ 0, + /* len */ 2 + }, +}; + +rtk_regField_t EGR_BIST_CTRL2_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 20, + /* len */ 12 + }, + { /* name */ HSA_LSf, + /* lsp */ 19, + /* len */ 1 + }, + { /* name */ DPC_LSf, + /* lsp */ 18, + /* len */ 1 + }, + { /* name */ TXQ_LSf, + /* lsp */ 16, + /* len */ 2 + }, + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 12 + }, + { /* name */ HSA_TEST1f, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ DPC_TEST1f, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ TXQ_TEST1f, + /* lsp */ 0, + /* len */ 2 + }, +}; + +rtk_regField_t EGR_SRAM_CTRL3_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 19, + /* len */ 13 + }, + { /* name */ BHSA_SRAM_RMEf, + /* lsp */ 18, + /* len */ 1 + }, + { /* name */ DPC_SRAM_RMEf, + /* lsp */ 17, + /* len */ 1 + }, + { /* name */ TXQ_SRAM_RMEf, + /* lsp */ 16, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 4 + }, + { /* name */ BHSA_SRAM_RM_3_0f, + /* lsp */ 8, + /* len */ 4 + }, + { /* name */ DPC_SRAM_RM_3_0f, + /* lsp */ 4, + /* len */ 4 + }, + { /* name */ TXQ_SRAM_RM_3_0f, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t EGR_BIST_CTRL4_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 20, + /* len */ 12 + }, + { /* name */ HSA_BIST_LOOPf, + /* lsp */ 19, + /* len */ 1 + }, + { /* name */ DPC_BIST_LOOPf, + /* lsp */ 18, + /* len */ 1 + }, + { /* name */ TXQ_BIST_LOOP_1_0f, + /* lsp */ 16, + /* len */ 2 + }, + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 12 + }, + { /* name */ HSA_DYN_READf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ DPC_DYN_READf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ TXQ_DYN_READ_1_0f, + /* lsp */ 0, + /* len */ 2 + }, +}; + +rtk_regField_t EGR_BIST_CTRL5_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 20 + }, + { /* name */ HSA_BIST_GRP_ENf, + /* lsp */ 10, + /* len */ 2 + }, + { /* name */ TXQ_BIST_GRP_ENf, + /* lsp */ 0, + /* len */ 10 + }, +}; + +rtk_regField_t EGR_BIST_RSLT0_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 20, + /* len */ 12 + }, + { /* name */ BHSA_DRF_BIST_DONEf, + /* lsp */ 19, + /* len */ 1 + }, + { /* name */ DPC_DRF_BIST_DONEf, + /* lsp */ 18, + /* len */ 1 + }, + { /* name */ TXQ_DRF_BIST_DONE_1_0f, + /* lsp */ 16, + /* len */ 2 + }, + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 12 + }, + { /* name */ BHSA_BIST_DONEf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ DPC_BIST_DONEf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ TXQ_BIST_DONE_1_0f, + /* lsp */ 0, + /* len */ 2 + }, +}; + +rtk_regField_t EGR_BIST_RSLT1_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 29, + /* len */ 3 + }, + { /* name */ BHSA_DRF_BIST_FAILf, + /* lsp */ 27, + /* len */ 2 + }, + { /* name */ DPC_DRF_BIST_FAILf, + /* lsp */ 26, + /* len */ 1 + }, + { /* name */ TXQ_DRF_BIST_FAIL_9_0f, + /* lsp */ 16, + /* len */ 10 + }, + { /* name */ RESERVEDf, + /* lsp */ 13, + /* len */ 3 + }, + { /* name */ BHSA_BIST_FAILf, + /* lsp */ 11, + /* len */ 2 + }, + { /* name */ DPC_BIST_FAILf, + /* lsp */ 10, + /* len */ 1 + }, + { /* name */ TXQ_BIST_FAIL_9_0f, + /* lsp */ 0, + /* len */ 10 + }, +}; + +rtk_regField_t EGR_BIST_RSLT2_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 28 + }, + { /* name */ BHSA_DRF_START_PAUSEf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ DPC_DRF_START_PAUSEf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ TXQ_DRF_START_PAUSE_1_0f, + /* lsp */ 0, + /* len */ 2 + }, +}; + +rtk_regField_t NIC_BIST_CTRL0_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 3, + /* len */ 29 + }, + { /* name */ DW8051_ERAM_BIST_GRP_ENf, + /* lsp */ 0, + /* len */ 3 + }, +}; + +rtk_regField_t NIC_BIST_CTRL1_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 20, + /* len */ 12 + }, + { /* name */ DW8051_ERAM_BIST_LOOP_MODEf, + /* lsp */ 19, + /* len */ 1 + }, + { /* name */ DW8051_IRAM_BIST_LOOP_MODEf, + /* lsp */ 18, + /* len */ 1 + }, + { /* name */ DW8051_IROM_BIST_LOOP_MODEf, + /* lsp */ 17, + /* len */ 1 + }, + { /* name */ NIC_BIST_LOOP_MODEf, + /* lsp */ 16, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 12 + }, + { /* name */ DW8051_ERAM_DYN_READ_ENf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ DW8051_IRAM_DYN_READ_ENf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ DW8051_IROM_DYN_READ_ENf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ NIC_DYN_READ_ENf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t NIC_BIST_CTRL2_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 30, + /* len */ 2 + }, + { /* name */ DW8051_ERAM_RM_2f, + /* lsp */ 26, + /* len */ 4 + }, + { /* name */ DW8051_ERAM_RM_1f, + /* lsp */ 22, + /* len */ 4 + }, + { /* name */ DW8051_ERAM_RM_0f, + /* lsp */ 18, + /* len */ 4 + }, + { /* name */ DW8051_IRAM_RMf, + /* lsp */ 14, + /* len */ 4 + }, + { /* name */ DW8051_IROM_RMf, + /* lsp */ 10, + /* len */ 4 + }, + { /* name */ NIC_RMf, + /* lsp */ 6, + /* len */ 4 + }, + { /* name */ DW8051_ERAM_RMEf, + /* lsp */ 3, + /* len */ 3 + }, + { /* name */ DW8051_IRAM_RMEf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ DW8051_IROM_RMEf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ NIC_RMEf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t NIC_BIST_CTRL3_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 22, + /* len */ 10 + }, + { /* name */ DW8051_ERAM_LSf, + /* lsp */ 19, + /* len */ 3 + }, + { /* name */ DW8051_IRAM_LSf, + /* lsp */ 18, + /* len */ 1 + }, + { /* name */ DW8051_IROM_LSf, + /* lsp */ 17, + /* len */ 1 + }, + { /* name */ NIC_LSf, + /* lsp */ 16, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 6, + /* len */ 10 + }, + { /* name */ DW8051_ERAM_TEST1f, + /* lsp */ 3, + /* len */ 3 + }, + { /* name */ DW8051_IRAM_TEST1f, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ DW8051_IROM_TEST1f, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ NIC_TEST1f, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t NIC_BIST_CTRL4_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 20, + /* len */ 12 + }, + { /* name */ DW8051_ERAM_DRF_TEST_RESUMEf, + /* lsp */ 19, + /* len */ 1 + }, + { /* name */ DW8051_IRAM_DRF_TEST_RESUMEf, + /* lsp */ 18, + /* len */ 1 + }, + { /* name */ DW8051_IROM_DRF_TEST_RESUMEf, + /* lsp */ 17, + /* len */ 1 + }, + { /* name */ NIC_DRF_TEST_RESUMEf, + /* lsp */ 16, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 12 + }, + { /* name */ DW8051_ERAM_BIST_RSTNf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ DW8051_IRAM_BIST_RSTNf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ DW8051_IROM_BIST_RSTNf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ NIC_BIST_RSTNf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t NIC_BIST_CTRL5_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 20, + /* len */ 12 + }, + { /* name */ DW8051_DRF_ERAM_BIST_MODEf, + /* lsp */ 19, + /* len */ 1 + }, + { /* name */ DW8051_DRF_IRAM_BIST_MODEf, + /* lsp */ 18, + /* len */ 1 + }, + { /* name */ DW8051_DRF_IROM_BIST_MODEf, + /* lsp */ 17, + /* len */ 1 + }, + { /* name */ NIC_DRF_BIST_MODEf, + /* lsp */ 16, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 12 + }, + { /* name */ DW8051_ERAM_BIST_MODEf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ DW8051_IRAM_BIST_MODEf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ DW8051_IROM_BIST_MODEf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ NIC_BIST_MODEf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t NIC_BIST_RSLT0_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 28 + }, + { /* name */ DW8051_ERAM_DRF_START_PAUSEf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ DW8051_IRAM_DRF_START_PAUSEf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ DW8051_IROM_DRF_START_PAUSEf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ NIC_DRF_START_PAUSEf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t NIC_BIST_RSLT1_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 22, + /* len */ 10 + }, + { /* name */ DW8051_ERAM_DRF_BIST_FAILf, + /* lsp */ 19, + /* len */ 3 + }, + { /* name */ DW8051_IRAM_DRF_BIST_FAILf, + /* lsp */ 18, + /* len */ 1 + }, + { /* name */ DW8051_IROM_DRF_BIST_FAILf, + /* lsp */ 17, + /* len */ 1 + }, + { /* name */ NIC_DRF_BIST_FAILf, + /* lsp */ 16, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 6, + /* len */ 10 + }, + { /* name */ DW8051_ERAM_BIST_FAILf, + /* lsp */ 3, + /* len */ 3 + }, + { /* name */ DW8051_IRAM_BIST_FAILf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ DW8051_IROM_BIST_FAILf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ NIC_BIST_FAILf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t NIC_BIST_RSLT2_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 20, + /* len */ 12 + }, + { /* name */ DW8051_ERAM_DRF_BIST_DONEf, + /* lsp */ 19, + /* len */ 1 + }, + { /* name */ DW8051_IRAM_DRF_BIST_DONEf, + /* lsp */ 18, + /* len */ 1 + }, + { /* name */ DW8051_IROM_DRF_BIST_DONEf, + /* lsp */ 17, + /* len */ 1 + }, + { /* name */ NIC_DRF_BIST_DONEf, + /* lsp */ 16, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 12 + }, + { /* name */ DW8051_ERAM_BIST_DONEf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ DW8051_IRAM_BIST_DONEf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ DW8051_IROM_BIST_DONEf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ NIC_BIST_DONEf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t SPI_BIST_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 13, + /* len */ 19 + }, + { /* name */ SPI_LSf, + /* lsp */ 12, + /* len */ 1 + }, + { /* name */ SPI_RMf, + /* lsp */ 8, + /* len */ 4 + }, + { /* name */ SPI_RMEf, + /* lsp */ 7, + /* len */ 1 + }, + { /* name */ SPI_TEST1f, + /* lsp */ 6, + /* len */ 1 + }, + { /* name */ SPI_BIST_LOOP_MODEf, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ SPI_DYN_READ_ENf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ SPI_DRF_TEST_RESUMEf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ SPI_DRF_BIST_MODEf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ SPI_BIST_MODEf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ SPI_BIST_RSTNf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t SPI_BIST_RSLT_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 5, + /* len */ 27 + }, + { /* name */ SPI_DRF_BIST_FAILf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ SPI_BIST_FAILf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ SPI_DRF_BIST_DONEf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ SPI_BIST_DONEf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ SPI_DRF_START_PAUSEf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t ALE_MEM_CFG_0_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 14, + /* len */ 18 + }, + { /* name */ ACT_LSf, + /* lsp */ 13, + /* len */ 1 + }, + { /* name */ ACT_TEST1f, + /* lsp */ 12, + /* len */ 1 + }, + { /* name */ ACT_DVSf, + /* lsp */ 8, + /* len */ 4 + }, + { /* name */ ACT_DVSEf, + /* lsp */ 7, + /* len */ 1 + }, + { /* name */ CVLAN_LSf, + /* lsp */ 6, + /* len */ 1 + }, + { /* name */ CVLAN_TEST1f, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ CVLAN_DVSf, + /* lsp */ 1, + /* len */ 4 + }, + { /* name */ CVLAN_DVSEf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t ALE_MEM_CFG_1_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 28, + /* len */ 4 + }, + { /* name */ L2_LSf, + /* lsp */ 24, + /* len */ 4 + }, + { /* name */ L2_TEST1f, + /* lsp */ 20, + /* len */ 4 + }, + { /* name */ L2_DVS_3f, + /* lsp */ 16, + /* len */ 4 + }, + { /* name */ L2_DVS_2f, + /* lsp */ 12, + /* len */ 4 + }, + { /* name */ L2_DVS_1f, + /* lsp */ 8, + /* len */ 4 + }, + { /* name */ L2_DVS_0f, + /* lsp */ 4, + /* len */ 4 + }, + { /* name */ L2_DVSEf, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t ALE_CAM_CFG_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 27, + /* len */ 5 + }, + { /* name */ BCAM_UDSf, + /* lsp */ 25, + /* len */ 2 + }, + { /* name */ BCAM_MDSf, + /* lsp */ 22, + /* len */ 3 + }, + { /* name */ BCAM_RDSf, + /* lsp */ 18, + /* len */ 4 + }, + { /* name */ TCAM_UDS_Hf, + /* lsp */ 16, + /* len */ 2 + }, + { /* name */ TCAM_MDS_Hf, + /* lsp */ 13, + /* len */ 3 + }, + { /* name */ TCAM_RDS_Hf, + /* lsp */ 9, + /* len */ 4 + }, + { /* name */ TCAM_UDS_Lf, + /* lsp */ 7, + /* len */ 2 + }, + { /* name */ TCAM_MDS_Lf, + /* lsp */ 4, + /* len */ 3 + }, + { /* name */ TCAM_RDS_Lf, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t ALE_BIST_LOOP_EN_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 6, + /* len */ 26 + }, + { /* name */ L2_BIST_LOOP_ENf, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ TCAM_BIST_LOOP_EN_Hf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ TCAM_BIST_LOOP_EN_Lf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ BCAM_BIST_LOOP_ENf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ ACT_BIST_LOOP_ENf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ CVLAN_BIST_LOOP_ENf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t ALE_BIST_DYN_READ_EN_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 6, + /* len */ 26 + }, + { /* name */ L2_BIST_DYN_READ_ENf, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ TCAM_BIST_DYN_READ_EN_Hf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ TCAM_BIST_DYN_READ_EN_Lf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ BCAM_BIST_DYN_READ_ENf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ ACT_BIST_DYN_READ_ENf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ CVLAN_BIST_DYN_READ_ENf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t ALE_BIST_GRP_EN_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 9, + /* len */ 23 + }, + { /* name */ L2_BIST_GRP_ENf, + /* lsp */ 5, + /* len */ 4 + }, + { /* name */ TCAM_BIST_GRP_EN_Hf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ TCAM_BIST_GRP_EN_Lf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ BCAM_BIST_GRP_ENf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ ACT_BIST_GRP_ENf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ CVLAN_BIST_GRP_ENf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t ALE_BIST_RSTN_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 6, + /* len */ 26 + }, + { /* name */ L2_BIST_RSTNf, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ TCAM_BIST_RSTN_Hf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ TCAM_BIST_RSTN_Lf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ BCAM_BIST_RSTNf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ ACT_BIST_RSTNf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ CVLAN_BIST_RSTNf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t ALE_BIST_MODE_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 6, + /* len */ 26 + }, + { /* name */ L2_BIST_MODEf, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ TCAM_BIST_MODE_Hf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ TCAM_BIST_MODE_Lf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ BCAM_BIST_MODEf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ ACT_BIST_MODEf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ CVLAN_BIST_MODEf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t ALE_BIST_DONE_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 6, + /* len */ 26 + }, + { /* name */ L2_BIST_DONEf, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ TCAM_BIST_DONE_Hf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ TCAM_BIST_DONE_Lf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ BCAM_BIST_DONEf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ ACT_BIST_DONEf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ CVLAN_BIST_DONEf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t ALE_BIST_FAIL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 9, + /* len */ 23 + }, + { /* name */ L2_BIST_FAILf, + /* lsp */ 5, + /* len */ 4 + }, + { /* name */ TCAM_BIST_FAIL_Hf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ TCAM_BIST_FAIL_Lf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ BCAM_BIST_FAILf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ ACT_BIST_FAILf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ CVLAN_BIST_FAILf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t ALE_DRF_MODE_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 6, + /* len */ 26 + }, + { /* name */ L2_DRF_MODEf, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ TCAM_DRF_MODE_Hf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ TCAM_DRF_MODE_Lf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ BCAM_DRF_MODEf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ ACT_DRF_MODEf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ CVLAN_DRF_MODEf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t ALE_DRF_PAUSE_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 6, + /* len */ 26 + }, + { /* name */ L2_DRF_PAUSEf, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ TCAM_DRF_PAUSE_Hf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ TCAM_DRF_PAUSE_Lf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ BCAM_DRF_PAUSEf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ ACT_DRF_PAUSEf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ CVLAN_DRF_PAUSEf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t ALE_DRF_RESUME_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 6, + /* len */ 26 + }, + { /* name */ L2_DRF_RESUMEf, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ TCAM_DRF_RESUME_Hf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ TCAM_DRF_RESUME_Lf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ BCAM_DRF_RESUMEf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ ACT_DRF_RESUMEf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ CVLAN_DRF_RESUMEf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t ALE_DRF_DONE_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 9, + /* len */ 23 + }, + { /* name */ L2_DRF_DONEf, + /* lsp */ 5, + /* len */ 4 + }, + { /* name */ TCAM_DRF_DONE_Hf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ TCAM_DRF_DONE_Lf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ BCAM_DRF_DONEf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ ACT_DRF_DONEf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ CVLAN_DRF_DONEf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t ALE_DRF_FAIL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 9, + /* len */ 23 + }, + { /* name */ L2_DRF_FAILf, + /* lsp */ 5, + /* len */ 4 + }, + { /* name */ TCAM_DRF_FAIL_Hf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ TCAM_DRF_FAIL_Lf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ BCAM_DRF_FAILf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ ACT_DRF_FAILf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ CVLAN_DRF_FAILf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t PAR_MEM_CFG_0_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 13, + /* len */ 19 + }, + { /* name */ PTR_LSf, + /* lsp */ 12, + /* len */ 1 + }, + { /* name */ PTR_TEST1Af, + /* lsp */ 11, + /* len */ 1 + }, + { /* name */ PTR_TEST1Bf, + /* lsp */ 10, + /* len */ 1 + }, + { /* name */ PTR_RMAf, + /* lsp */ 6, + /* len */ 4 + }, + { /* name */ PTR_RMBf, + /* lsp */ 2, + /* len */ 4 + }, + { /* name */ PTR_RMEAf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ PTR_RMEBf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t PAR_MEM_CFG_1_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 24, + /* len */ 8 + }, + { /* name */ HSB_RMBf, + /* lsp */ 0, + /* len */ 24 + }, +}; + +rtk_regField_t PAR_MEM_CFG_2_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 24, + /* len */ 8 + }, + { /* name */ HSB_RMAf, + /* lsp */ 0, + /* len */ 24 + }, +}; + +rtk_regField_t PAR_MEM_CFG_3_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 30, + /* len */ 2 + }, + { /* name */ HSB_LSf, + /* lsp */ 24, + /* len */ 6 + }, + { /* name */ HSB_TEST1Af, + /* lsp */ 18, + /* len */ 6 + }, + { /* name */ HSB_TEST1Bf, + /* lsp */ 12, + /* len */ 6 + }, + { /* name */ HSB_RMEAf, + /* lsp */ 6, + /* len */ 6 + }, + { /* name */ HSB_RMEBf, + /* lsp */ 0, + /* len */ 6 + }, +}; + +rtk_regField_t PAR_BIST_RESET_RESUME_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 18, + /* len */ 14 + }, + { /* name */ HSB_DRF_TEST_RESUMEf, + /* lsp */ 17, + /* len */ 1 + }, + { /* name */ PTR_DRF_TEST_RESUMEf, + /* lsp */ 16, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 2, + /* len */ 14 + }, + { /* name */ HSB_BIST_RSTNf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ PTR_BIST_RSTNf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t PAR_BIST_MODE_DRFMODE_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 18, + /* len */ 14 + }, + { /* name */ HSB_DRF_MODEf, + /* lsp */ 17, + /* len */ 1 + }, + { /* name */ PTR_DRF_MODEf, + /* lsp */ 16, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 2, + /* len */ 14 + }, + { /* name */ HSB_BIST_MODEf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ PTR_BIST_MODEf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t PAR_BIST_VDDR_LOOP_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 18, + /* len */ 14 + }, + { /* name */ HSB_BIST_LOOP_MODEf, + /* lsp */ 17, + /* len */ 1 + }, + { /* name */ PTR_BIST_LOOP_MODEf, + /* lsp */ 16, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 2, + /* len */ 14 + }, + { /* name */ HSB_DYN_READ_ENf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ PTR_DYN_READ_ENf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t PAR_BIST_START_PAUSE_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 2, + /* len */ 30 + }, + { /* name */ HSB_DRF_START_PAUSEf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ PTR_DRF_START_PAUSEf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t PAR_BIST_DONE_DRFDONE_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 18, + /* len */ 14 + }, + { /* name */ HSB_DRF_DONEf, + /* lsp */ 17, + /* len */ 1 + }, + { /* name */ PTR_DRF_DONEf, + /* lsp */ 16, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 2, + /* len */ 14 + }, + { /* name */ HSB_BIST_DONEf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ PTR_BIST_DONEf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t PAR_BIST_FAIL_DRFFAIL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 23, + /* len */ 9 + }, + { /* name */ HSB_DRF_FAILf, + /* lsp */ 17, + /* len */ 6 + }, + { /* name */ PTR_DRF_FAILf, + /* lsp */ 16, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 7, + /* len */ 9 + }, + { /* name */ HSB_BIST_FAILf, + /* lsp */ 1, + /* len */ 6 + }, + { /* name */ PTR_BIST_FAILf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t PAR_BIST_CTRL_0_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 2, + /* len */ 30 + }, + { /* name */ HSB_BIST_ENf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ PTR_BIST_ENf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t MBIST_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 13, + /* len */ 19 + }, + { /* name */ MIB_LS_MODEf, + /* lsp */ 12, + /* len */ 1 + }, + { /* name */ MIB_MB_RMf, + /* lsp */ 8, + /* len */ 4 + }, + { /* name */ MIB_MB_RMEf, + /* lsp */ 7, + /* len */ 1 + }, + { /* name */ MIB_TEST1f, + /* lsp */ 6, + /* len */ 1 + }, + { /* name */ MIB_LOOP_MODEf, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ MIB_DYN_READ_ENf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ MIB_RESUMEf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ MIB_DRF_MODEf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ MIB_MODEf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ MIB_RSTNf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t MBIST_RSLT_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 5, + /* len */ 27 + }, + { /* name */ MIB_DRF_FAILf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ MIB_FAILf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ MIB_DRF_DONEf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ MIB_DONEf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ MIB_DRF_PAUSEf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +/* Module: HW_MISC */ +rtk_regField_t BOND_INFO_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 20 + }, + { /* name */ BOND_INFO_ROf, + /* lsp */ 0, + /* len */ 12 + }, +}; + +rtk_regField_t STRAP_INFO_0_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 18, + /* len */ 14 + }, + { /* name */ STRAP_INFO_ROf, + /* lsp */ 0, + /* len */ 18 + }, +}; + +rtk_regField_t IO_DRVING_0_FIELDS[] = +{ + { /* name */ IO_DRVING_0f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t IO_DRVING_1_FIELDS[] = +{ + { /* name */ IO_DRVING_1f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t IO_DRVING_2_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 19, + /* len */ 13 + }, + { /* name */ IO_DRVING_2f, + /* lsp */ 0, + /* len */ 19 + }, +}; + +rtk_regField_t IO_SLEW_0_FIELDS[] = +{ + { /* name */ IO_SLEW_0f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t IO_SLEW_1_FIELDS[] = +{ + { /* name */ IO_SLEW_1f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t IO_SLEW_2_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 19, + /* len */ 13 + }, + { /* name */ IO_SLEW_2f, + /* lsp */ 0, + /* len */ 19 + }, +}; + +rtk_regField_t IO_SMT_EN_0_FIELDS[] = +{ + { /* name */ IO_SMT_EN_0f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t IO_SMT_EN_1_FIELDS[] = +{ + { /* name */ IO_SMT_EN_1f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t IO_SMT_EN_2_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 19, + /* len */ 13 + }, + { /* name */ IO_SMT_EN_2f, + /* lsp */ 0, + /* len */ 19 + }, +}; + +rtk_regField_t IO_MUX_SEL_0_FIELDS[] = +{ + { /* name */ FLASH_FORCE_CTR_ENf, + /* lsp */ 31, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 30, + /* len */ 1 + }, + { /* name */ GLB_RLDP_LED_ENf, + /* lsp */ 29, + /* len */ 1 + }, + { /* name */ SYS_LED_ENf, + /* lsp */ 28, + /* len */ 1 + }, + { /* name */ GPIO_LED27_SELf, + /* lsp */ 27, + /* len */ 1 + }, + { /* name */ GPIO_LED26_SELf, + /* lsp */ 26, + /* len */ 1 + }, + { /* name */ GPIO_LED25_SELf, + /* lsp */ 25, + /* len */ 1 + }, + { /* name */ GPIO_LED24_SELf, + /* lsp */ 24, + /* len */ 1 + }, + { /* name */ GPIO_LED23_SELf, + /* lsp */ 23, + /* len */ 1 + }, + { /* name */ GPIO_LED22_SELf, + /* lsp */ 22, + /* len */ 1 + }, + { /* name */ GPIO_LED21_SELf, + /* lsp */ 21, + /* len */ 1 + }, + { /* name */ GPIO_LED20_SELf, + /* lsp */ 20, + /* len */ 1 + }, + { /* name */ GPIO_LED19_SELf, + /* lsp */ 19, + /* len */ 1 + }, + { /* name */ GPIO_LED18_SELf, + /* lsp */ 18, + /* len */ 1 + }, + { /* name */ GPIO_LED17_SELf, + /* lsp */ 17, + /* len */ 1 + }, + { /* name */ GPIO_LED16_SELf, + /* lsp */ 16, + /* len */ 1 + }, + { /* name */ GPIO_LED15_SELf, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ GPIO_LED14_SELf, + /* lsp */ 14, + /* len */ 1 + }, + { /* name */ GPIO_LED13_SELf, + /* lsp */ 13, + /* len */ 1 + }, + { /* name */ GPIO_LED12_SELf, + /* lsp */ 12, + /* len */ 1 + }, + { /* name */ GPIO_LED11_SELf, + /* lsp */ 11, + /* len */ 1 + }, + { /* name */ GPIO_LED10_SELf, + /* lsp */ 10, + /* len */ 1 + }, + { /* name */ GPIO_LED9_SELf, + /* lsp */ 9, + /* len */ 1 + }, + { /* name */ GPIO_LED8_SELf, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ GPIO_LED7_SELf, + /* lsp */ 7, + /* len */ 1 + }, + { /* name */ GPIO_LED6_SELf, + /* lsp */ 6, + /* len */ 1 + }, + { /* name */ GPIO_LED5_SELf, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ GPIO_LED4_SELf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ GPIO_LED3_SELf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ GPIO_LED2_SELf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ GPIO_LED1_SELf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ GPIO_LED0_SELf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t IO_MUX_SEL_1_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 31, + /* len */ 1 + }, + { /* name */ GPIO_PWM_OUT_SELf, + /* lsp */ 30, + /* len */ 1 + }, + { /* name */ GPIO_SDA4_SELf, + /* lsp */ 29, + /* len */ 1 + }, + { /* name */ SYNCELOCK1_SELf, + /* lsp */ 28, + /* len */ 1 + }, + { /* name */ SYNCELOCK0_SELf, + /* lsp */ 27, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 25, + /* len */ 2 + }, + { /* name */ PTP_PPS_IN_SELf, + /* lsp */ 24, + /* len */ 1 + }, + { /* name */ PTP_TOD_IN_SELf, + /* lsp */ 23, + /* len */ 1 + }, + { /* name */ PTP_PPS_OUT_SELf, + /* lsp */ 22, + /* len */ 1 + }, + { /* name */ PTP_TOD_OUT_SELf, + /* lsp */ 21, + /* len */ 1 + }, + { /* name */ PTP_CLK_OUT_SELf, + /* lsp */ 20, + /* len */ 1 + }, + { /* name */ PTP_CLK125M_IN_SELf, + /* lsp */ 19, + /* len */ 1 + }, + { /* name */ PAD_MSDA2_SEL_1f, + /* lsp */ 18, + /* len */ 1 + }, + { /* name */ PAD_MSDA2_SEL_0f, + /* lsp */ 17, + /* len */ 1 + }, + { /* name */ PAD_MSCK2_SEL_1f, + /* lsp */ 16, + /* len */ 1 + }, + { /* name */ PAD_MSCK2_SEL_0f, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ PAD_MSDA1_SEL_1f, + /* lsp */ 14, + /* len */ 1 + }, + { /* name */ PAD_MSDA1_SEL_0f, + /* lsp */ 13, + /* len */ 1 + }, + { /* name */ PAD_MSCK1_SEL_1f, + /* lsp */ 12, + /* len */ 1 + }, + { /* name */ PAD_MSCK1_SEL_0f, + /* lsp */ 11, + /* len */ 1 + }, + { /* name */ PAD_MSDA0_SEL_1f, + /* lsp */ 10, + /* len */ 1 + }, + { /* name */ PAD_MSDA0_SEL_0f, + /* lsp */ 9, + /* len */ 1 + }, + { /* name */ PAD_MSCK0_SEL_1f, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ PAD_MSCK0_SEL_0f, + /* lsp */ 7, + /* len */ 1 + }, + { /* name */ GPIO_MDX1_SEL_1f, + /* lsp */ 6, + /* len */ 1 + }, + { /* name */ GPIO_MDX1_SEL_0f, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ GPIO_MDIO0_SELf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ GPIO_MDC0_SELf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ GPIO_INT_SELf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ PAD_UART0_SEL_1f, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ PAD_UART0_SEL_0f, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t IO_MUX_SEL_2_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 28 + }, + { /* name */ ACL_BIT3_ENf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ ACL_BIT2_ENf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ ACL_BIT1_ENf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ ACL_BIT0_ENf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t IO_MUX_SEL_3_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 1, + /* len */ 31 + }, + { /* name */ IO_BISD_ENf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t DBG_MODE_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 3, + /* len */ 29 + }, + { /* name */ DBG_SHIFTf, + /* lsp */ 0, + /* len */ 3 + }, +}; + +rtk_regField_t DBG_PAD_CTRL_FIELDS[] = +{ + { /* name */ DBG_PAD_CTRLf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t DBG_CTRL_ADR0_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ DBG_ADR0f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t DBG_CTRL_ADR1_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ DBG_ADR1f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t DBG_CTRL_ADR2_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ DBG_ADR2f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t DBG_CTRL_ADR3_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ DBG_ADR3f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t DBG_CTRL_SEL0_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 7, + /* len */ 25 + }, + { /* name */ DBG_SHIFT_SEL0f, + /* lsp */ 4, + /* len */ 3 + }, + { /* name */ DBG_BIT_SEL0f, + /* lsp */ 2, + /* len */ 2 + }, + { /* name */ DBG_BLK_SEL0f, + /* lsp */ 0, + /* len */ 2 + }, +}; + +rtk_regField_t DBG_CTRL_SEL1_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 7, + /* len */ 25 + }, + { /* name */ DBG_SHIFT_SEL1f, + /* lsp */ 4, + /* len */ 3 + }, + { /* name */ DBG_BIT_SEL1f, + /* lsp */ 2, + /* len */ 2 + }, + { /* name */ DBG_BLK_SEL1f, + /* lsp */ 0, + /* len */ 2 + }, +}; + +rtk_regField_t DBG_CTRL_SEL2_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 7, + /* len */ 25 + }, + { /* name */ DBG_SHIFT_SEL2f, + /* lsp */ 4, + /* len */ 3 + }, + { /* name */ DBG_BIT_SEL2f, + /* lsp */ 2, + /* len */ 2 + }, + { /* name */ DBG_BLK_SEL2f, + /* lsp */ 0, + /* len */ 2 + }, +}; + +rtk_regField_t DBG_CTRL_SEL3_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 7, + /* len */ 25 + }, + { /* name */ DBG_SHIFT_SEL3f, + /* lsp */ 4, + /* len */ 3 + }, + { /* name */ DBG_BIT_SEL3f, + /* lsp */ 2, + /* len */ 2 + }, + { /* name */ DBG_BLK_SEL3f, + /* lsp */ 0, + /* len */ 2 + }, +}; + +rtk_regField_t DBG_CTRL_VAL_FIELDS[] = +{ + { /* name */ DBG_OUTf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t FORCE_PU_PD_EN_0_FIELDS[] = +{ + { /* name */ FORCE_PU_PD_EN_0f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t FORCE_PU_PD_EN_1_FIELDS[] = +{ + { /* name */ FORCE_PU_PD_EN_1f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t FORCE_PU_0_FIELDS[] = +{ + { /* name */ FORCE_PU_0f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t FORCE_PU_1_FIELDS[] = +{ + { /* name */ FORCE_PU_1f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t FORCE_PD_0_FIELDS[] = +{ + { /* name */ FORCE_PD_0f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t FORCE_PD_1_FIELDS[] = +{ + { /* name */ FORCE_PD_1f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t CFG_PAD_MDIO0_DRV_MODE_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 1, + /* len */ 31 + }, + { /* name */ CFG_MDIO_DRV_PADf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t VOLT_PROB_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 30, + /* len */ 2 + }, + { /* name */ LOW_VOLT_CH_FLAGf, + /* lsp */ 22, + /* len */ 8 + }, + { /* name */ VOLT_CMP_ENf, + /* lsp */ 21, + /* len */ 1 + }, + { /* name */ VOLT_THRf, + /* lsp */ 11, + /* len */ 10 + }, + { /* name */ VOLT_PROB_PAD_OUT_ENf, + /* lsp */ 10, + /* len */ 1 + }, + { /* name */ VOLT_PROB_SELf, + /* lsp */ 6, + /* len */ 4 + }, + { /* name */ VOLT_PROB_RECORDf, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ POW_SAR_ENf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ SAR_REFf, + /* lsp */ 1, + /* len */ 3 + }, + { /* name */ SAR_REG_WTf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t VOLT_PROB_RESULT0_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 10, + /* len */ 22 + }, + { /* name */ DOUT_CURRENTf, + /* lsp */ 0, + /* len */ 10 + }, +}; + +rtk_regField_t VOLT_PROB_RESULT1_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 26, + /* len */ 6 + }, + { /* name */ VOLT_PROB_MAXf, + /* lsp */ 16, + /* len */ 10 + }, + { /* name */ RESERVEDf, + /* lsp */ 10, + /* len */ 6 + }, + { /* name */ VOLT_PROB_MINf, + /* lsp */ 0, + /* len */ 10 + }, +}; + +rtk_regField_t CFG_XTAL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 9, + /* len */ 23 + }, + { /* name */ REG_CKREFBUF_CML_I_SDSf, + /* lsp */ 6, + /* len */ 3 + }, + { /* name */ REG_CKREFBUF_CML_I_APHYf, + /* lsp */ 3, + /* len */ 3 + }, + { /* name */ REG_CKREFBUF_ENf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ REG_CMU_TEST_EN_XTALf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ REG_PIN_SEL_25M_TEST_ENf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +/* Module: Wrapper_PHY */ +rtk_regField_t CFG_EEE_FLG_DLY_FIELDS[] = +{ + { /* name */ SDS2PHY_EEE_FLG_DLY3f, + /* lsp */ 28, + /* len */ 4 + }, + { /* name */ PHY2SDS_EEE_FLG_DLY3f, + /* lsp */ 24, + /* len */ 4 + }, + { /* name */ SDS2PHY_EEE_FLG_DLY2f, + /* lsp */ 20, + /* len */ 4 + }, + { /* name */ PHY2SDS_EEE_FLG_DLY2f, + /* lsp */ 16, + /* len */ 4 + }, + { /* name */ SDS2PHY_EEE_FLG_DLY1f, + /* lsp */ 12, + /* len */ 4 + }, + { /* name */ PHY2SDS_EEE_FLG_DLY1f, + /* lsp */ 8, + /* len */ 4 + }, + { /* name */ SDS2PHY_EEE_FLG_DLY0f, + /* lsp */ 4, + /* len */ 4 + }, + { /* name */ PHY2SDS_EEE_FLG_DLY0f, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t CFG_PHY_MDI_REVERSE_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 8, + /* len */ 24 + }, + { /* name */ P3_PHY_R_FRCf, + /* lsp */ 7, + /* len */ 1 + }, + { /* name */ P2_PHY_R_FRCf, + /* lsp */ 6, + /* len */ 1 + }, + { /* name */ P1_PHY_R_FRCf, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ P0_PHY_R_FRCf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ P3_MDI_REVERSEf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ P2_MDI_REVERSEf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ P1_MDI_REVERSEf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ P0_MDI_REVERSEf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t CFG_PHY_TX_POLARITY_SWAP_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ P3_TX_POLARITY_SWAPf, + /* lsp */ 12, + /* len */ 4 + }, + { /* name */ P2_TX_POLARITY_SWAPf, + /* lsp */ 8, + /* len */ 4 + }, + { /* name */ P1_TX_POLARITY_SWAPf, + /* lsp */ 4, + /* len */ 4 + }, + { /* name */ P0_TX_POLARITY_SWAPf, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t CFG_PHY_OCP_TIMEOUT_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 20 + }, + { /* name */ PHY_OCP_TOFf, + /* lsp */ 8, + /* len */ 4 + }, + { /* name */ PHY_OCP_TOf, + /* lsp */ 0, + /* len */ 8 + }, +}; + +rtk_regField_t CFG_PHY_PCSXF_1_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 13, + /* len */ 19 + }, + { /* name */ PCSXF_RXFIFO_ERR_FLAGf, + /* lsp */ 9, + /* len */ 4 + }, + { /* name */ PCSXF_RST_RXFIFOf, + /* lsp */ 5, + /* len */ 4 + }, + { /* name */ PCSXF_MCFGf, + /* lsp */ 1, + /* len */ 4 + }, + { /* name */ COL_10Mf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t CFG_PHY_PCSXF_2_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 13, + /* len */ 19 + }, + { /* name */ PCSXF_MIIRX_IPGf, + /* lsp */ 8, + /* len */ 5 + }, + { /* name */ PCSXF_STOP_TXCf, + /* lsp */ 4, + /* len */ 4 + }, + { /* name */ PCSXF_STOP_RXCf, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t CFG_PHY_G2XG_IPG_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 8, + /* len */ 24 + }, + { /* name */ G2XG_GTX_MIN_IPGf, + /* lsp */ 4, + /* len */ 4 + }, + { /* name */ G2XG_GRX_MIN_IPGf, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t CFG_PHY_G2XG_FIFO_THR_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 14, + /* len */ 18 + }, + { /* name */ CFG_LDN_CLR_FIFO_RXf, + /* lsp */ 13, + /* len */ 1 + }, + { /* name */ CFG_LDN_CLR_FIFO_TXf, + /* lsp */ 12, + /* len */ 1 + }, + { /* name */ CFG_MDY_XG_EEE_LPI_TXf, + /* lsp */ 11, + /* len */ 1 + }, + { /* name */ CFG_MDY_G_EEE_LPI_RXf, + /* lsp */ 10, + /* len */ 1 + }, + { /* name */ G2XG_TX_RDFIFO_THRf, + /* lsp */ 4, + /* len */ 6 + }, + { /* name */ G2XG_RX_RDFIFO_THRf, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t CFG_PHY_G2XG_AUTORST_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ G2XG_EN_AUTO_RSTf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t CFG_PHY_G2XG_MISC_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ G2XG_EN_ECODEf, + /* lsp */ 12, + /* len */ 4 + }, + { /* name */ G2XG_BYPASS_BCHf, + /* lsp */ 8, + /* len */ 4 + }, + { /* name */ G2XG_EN_G_LPIf, + /* lsp */ 4, + /* len */ 4 + }, + { /* name */ G2XG_EN_XG_LPIf, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t CFG_PHY_G2XG_MODULE_RST_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 14, + /* len */ 18 + }, + { /* name */ CFG_G_EEE_LPI_RX_DLY_ENf, + /* lsp */ 13, + /* len */ 1 + }, + { /* name */ CFG_XG_EEE_LPI_TX_DLY_ENf, + /* lsp */ 12, + /* len */ 1 + }, + { /* name */ CFG_G_EEE_LPI_RX_SHIFTf, + /* lsp */ 8, + /* len */ 4 + }, + { /* name */ CFG_XG_EEE_LPI_TX_SHIFTf, + /* lsp */ 4, + /* len */ 4 + }, + { /* name */ G2XG_MODULE_RSTf, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t P0_PHY_G2XG_BCH_ERR_FLAG_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ P0_G2XG_BCH_ERR_FLAGf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t P1_PHY_G2XG_BCH_ERR_FLAG_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ P1_G2XG_BCH_ERR_FLAGf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t P2_PHY_G2XG_BCH_ERR_FLAG_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ P2_G2XG_BCH_ERR_FLAGf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t P3_PHY_G2XG_BCH_ERR_FLAG_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ P3_G2XG_BCH_ERR_FLAGf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t CFG_PHY_MISC_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 24, + /* len */ 8 + }, + { /* name */ WRAP_PHY_DBGf, + /* lsp */ 16, + /* len */ 8 + }, + { /* name */ DCO_CLK_SRCf, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ PHY_MISC_FAULT_ONf, + /* lsp */ 14, + /* len */ 1 + }, + { /* name */ UNIDIR_ENf, + /* lsp */ 13, + /* len */ 1 + }, + { /* name */ QHSGMII_EEE_ENf, + /* lsp */ 12, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 11, + /* len */ 1 + }, + { /* name */ STRP_DIS_POR_DBG_8224f, + /* lsp */ 10, + /* len */ 1 + }, + { /* name */ CFG_BYP_SDS_LDNf, + /* lsp */ 9, + /* len */ 1 + }, + { /* name */ CFG_BYP_PHY_LDNf, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ CFG_312P5_CLK_SELf, + /* lsp */ 4, + /* len */ 4 + }, + { /* name */ MDI_BRD_MSKf, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t PHY_LINK_FAULT_STS_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 20 + }, + { /* name */ P3_LINK_FAULT_STSf, + /* lsp */ 9, + /* len */ 3 + }, + { /* name */ P2_LINK_FAULT_STSf, + /* lsp */ 6, + /* len */ 3 + }, + { /* name */ P1_LINK_FAULT_STSf, + /* lsp */ 3, + /* len */ 3 + }, + { /* name */ P0_LINK_FAULT_STSf, + /* lsp */ 0, + /* len */ 3 + }, +}; + +rtk_regField_t CFG_PHY_BRD_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 14, + /* len */ 18 + }, + { /* name */ PHY_BASE_ADRf, + /* lsp */ 9, + /* len */ 5 + }, + { /* name */ PHY_BRD_MODEf, + /* lsp */ 5, + /* len */ 4 + }, + { /* name */ PHY_BRD_ADRf, + /* lsp */ 0, + /* len */ 5 + }, +}; + +rtk_regField_t CFG_PHY_INI_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 20, + /* len */ 12 + }, + { /* name */ PHY_INI_POWER_DOWNf, + /* lsp */ 16, + /* len */ 4 + }, + { /* name */ RESERVEDf, + /* lsp */ 3, + /* len */ 13 + }, + { /* name */ BYPS_CHK_INIf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ PHY_INI_DISGIGAf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ PHY_INI_EEE_ENf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t CFG_PHY_POLL_CMD1_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 14, + /* len */ 18 + }, + { /* name */ PHY_SDET_SELf, + /* lsp */ 12, + /* len */ 2 + }, + { /* name */ CMD_WRMSK_ENf, + /* lsp */ 8, + /* len */ 4 + }, + { /* name */ CMD_WR_ENf, + /* lsp */ 4, + /* len */ 4 + }, + { /* name */ CMD_RD_ENf, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t CFG_PHY_POLL_CMD2_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 13, + /* len */ 19 + }, + { /* name */ CMD_PRDf, + /* lsp */ 8, + /* len */ 5 + }, + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 4 + }, + { /* name */ HOTCMD_PRD_ENf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ HOTCMD_ENf, + /* lsp */ 0, + /* len */ 3 + }, +}; + +rtk_regField_t CFG_PHY_HOTCMD1_ADR_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ HOTCMD1_ADRf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t CFG_PHY_HOTCMD1_DAT_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ HOTCMD1_DATf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t P0_XG2XG_IPG_DBG_INFO_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ CFG_P0_DBG_INFO_OFFf, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ CFG_P0_CUR_IPGf, + /* lsp */ 10, + /* len */ 5 + }, + { /* name */ CFG_P0_MAX_IPGf, + /* lsp */ 5, + /* len */ 5 + }, + { /* name */ CFG_P0_MIN_IPGf, + /* lsp */ 0, + /* len */ 5 + }, +}; + +rtk_regField_t P0_XG2XG_PRMB_DBG_INFO_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 20 + }, + { /* name */ CFG_P0_CUR_PRMBf, + /* lsp */ 8, + /* len */ 4 + }, + { /* name */ CFG_P0_MAX_PRMBf, + /* lsp */ 4, + /* len */ 4 + }, + { /* name */ CFG_P0_MIN_PRMBf, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t P0_XG2XG_THR_DBG_INFO_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 20 + }, + { /* name */ CFG_P0_CUR_THRf, + /* lsp */ 6, + /* len */ 6 + }, + { /* name */ CFG_P0_MAX_THRf, + /* lsp */ 0, + /* len */ 6 + }, +}; + +rtk_regField_t CFG_PHY_POLL_ADR0_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ CMD0_ADRf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t CFG_PHY_POLL_ADR1_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ CMD1_ADRf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t CFG_PHY_POLL_ADR2_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ CMD2_ADRf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t CFG_PHY_POLL_ADR3_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ CMD3_ADRf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t CFG_PHY_POLL_INV0_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ CMD0_INVf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t CFG_PHY_POLL_INV1_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ CMD1_INVf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t CFG_PHY_POLL_INV2_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ CMD2_INVf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t CFG_PHY_POLL_INV3_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ CMD3_INVf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t CFG_PHY_POLL_WD0_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ CMD0_WDATf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t CFG_PHY_POLL_WD1_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ CMD1_WDATf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t CFG_PHY_POLL_WD2_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ CMD2_WDATf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t CFG_PHY_POLL_WD3_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ CMD3_WDATf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t PHY_SDET_STATUS_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 28 + }, + { /* name */ P3_SDET_STSf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ P2_SDET_STSf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ P1_SDET_STSf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ P0_SDET_STSf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t P0_PHY_POLL_CMD0_RDAT_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ P0_CMD0_RDATf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t P0_PHY_POLL_CMD1_RDAT_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ P0_CMD1_RDATf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t P0_PHY_POLL_CMD2_RDAT_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ P0_CMD2_RDATf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t P0_PHY_POLL_CMD3_RDAT_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ P0_CMD3_RDATf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t P1_PHY_POLL_CMD0_RDAT_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ P1_CMD0_RDATf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t P1_PHY_POLL_CMD1_RDAT_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ P1_CMD1_RDATf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t P1_PHY_POLL_CMD2_RDAT_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ P1_CMD2_RDATf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t P1_PHY_POLL_CMD3_RDAT_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ P1_CMD3_RDATf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t P2_PHY_POLL_CMD0_RDAT_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ P2_CMD0_RDATf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t P2_PHY_POLL_CMD1_RDAT_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ P2_CMD1_RDATf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t P2_PHY_POLL_CMD2_RDAT_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ P2_CMD2_RDATf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t P2_PHY_POLL_CMD3_RDAT_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ P2_CMD3_RDATf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t P3_PHY_POLL_CMD0_RDAT_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ P3_CMD0_RDATf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t P3_PHY_POLL_CMD1_RDAT_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ P3_CMD1_RDATf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t P3_PHY_POLL_CMD2_RDAT_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ P3_CMD2_RDATf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t P3_PHY_POLL_CMD3_RDAT_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ P3_CMD3_RDATf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t PHY_ABLTY_RESOLUTION_FRC_MODE_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 28 + }, + { /* name */ PHY_ABLTY_RESOLUTION_FRC_MODEf, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t P0_PHY_ABLTY_RESOLUTION_FORCE_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ P0_PHY_ABLTY_RESOLUTION_FRC_VALUEf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t P1_PHY_ABLTY_RESOLUTION_FORCE_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ P1_PHY_ABLTY_RESOLUTION_FRC_VALUEf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t P2_PHY_ABLTY_RESOLUTION_FORCE_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ P2_PHY_ABLTY_RESOLUTION_FRC_VALUEf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t P3_PHY_ABLTY_RESOLUTION_FORCE_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ P3_PHY_ABLTY_RESOLUTION_FRC_VALUEf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t POWCTRL_ADR_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ GETPOWCTRL_ADRf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t POWCTRL1_BIT_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ GETPOWCTRL1_BITf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t POWCTRL0_BIT_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ GETPOWCTRL0_BITf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t RS_LAYER_CONFIG_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 8, + /* len */ 24 + }, + { /* name */ RS_BYPASSf, + /* lsp */ 7, + /* len */ 1 + }, + { /* name */ RS_FB_ONf, + /* lsp */ 6, + /* len */ 1 + }, + { /* name */ RS_LINK_FAULT_INDI_OFFf, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ RS_SEQ_CONVf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ RS_PASS_FAULT2MACf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ RS_LINK_FAULT_LOCAL_OFFf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ RS_LINK_FAULT_REMOTE_OFFf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ RS_LINK_FAULT_LINT_OFFf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t PHY0_RD_PCS_ABILITY_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ P0_RD_PCS_ABILITYf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t PHY1_RD_PCS_ABILITY_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ P1_RD_PCS_ABILITYf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t PHY2_RD_PCS_ABILITY_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ P2_RD_PCS_ABILITYf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t PHY3_RD_PCS_ABILITY_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ P3_RD_PCS_ABILITYf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t CFG_PHY_XG2G_G_MISC_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ P3_IPG_DIFFf, + /* lsp */ 14, + /* len */ 2 + }, + { /* name */ P3_BYPASS_SMOOTHf, + /* lsp */ 13, + /* len */ 1 + }, + { /* name */ P3_RST_LATCH_MIN_IPGf, + /* lsp */ 12, + /* len */ 1 + }, + { /* name */ P2_IPG_DIFFf, + /* lsp */ 10, + /* len */ 2 + }, + { /* name */ P2_BYPASS_SMOOTHf, + /* lsp */ 9, + /* len */ 1 + }, + { /* name */ P2_RST_LATCH_MIN_IPGf, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ P1_IPG_DIFFf, + /* lsp */ 6, + /* len */ 2 + }, + { /* name */ P1_BYPASS_SMOOTHf, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ P1_RST_LATCH_MIN_IPGf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ P0_IPG_DIFFf, + /* lsp */ 2, + /* len */ 2 + }, + { /* name */ P0_BYPASS_SMOOTHf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ P0_RST_LATCH_MIN_IPGf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t P1_XG2XG_IPG_DBG_INFO_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ CFG_P1_DBG_INFO_OFFf, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ CFG_P1_CUR_IPGf, + /* lsp */ 10, + /* len */ 5 + }, + { /* name */ CFG_P1_MAX_IPGf, + /* lsp */ 5, + /* len */ 5 + }, + { /* name */ CFG_P1_MIN_IPGf, + /* lsp */ 0, + /* len */ 5 + }, +}; + +rtk_regField_t P1_XG2XG_PRMB_DBG_INFO_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 20 + }, + { /* name */ CFG_P1_CUR_PRMBf, + /* lsp */ 8, + /* len */ 4 + }, + { /* name */ CFG_P1_MAX_PRMBf, + /* lsp */ 4, + /* len */ 4 + }, + { /* name */ CFG_P1_MIN_PRMBf, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t P1_XG2XG_THR_DBG_INFO_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 20 + }, + { /* name */ CFG_P1_CUR_THRf, + /* lsp */ 6, + /* len */ 6 + }, + { /* name */ CFG_P1_MAX_THRf, + /* lsp */ 0, + /* len */ 6 + }, +}; + +rtk_regField_t RANDOM_UPD_PERIOD_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RSUPD_PERIODf, + /* lsp */ 8, + /* len */ 8 + }, + { /* name */ RRUPD_PERIODf, + /* lsp */ 0, + /* len */ 8 + }, +}; + +rtk_regField_t RANDOM_UPD_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TMTENBITf, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ TMLSB_2_0f, + /* lsp */ 12, + /* len */ 3 + }, + { /* name */ RR_SEL_MTHDf, + /* lsp */ 11, + /* len */ 1 + }, + { /* name */ RRSTEP_4_0f, + /* lsp */ 6, + /* len */ 5 + }, + { /* name */ RRRND_SRC_SELf, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ RRUPD_ONCEf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ RRUPD_ENf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ RSRND_SRC_SELf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ RSUPD_ONCEf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ RSUPD_ENf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t RG_RDM_SEED_SRC_ADDR_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RDM_SEED_REGADDRf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t RING_RATE_REGADDR_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RING_RATE_REGADDRf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t RING_RATE_SEL_MASK_L_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RATE_MASK_15_0f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t RING_RATE_SEL_MASK_H_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RATE_MASK_31_16f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t RING_RATE_FRC_VALUE_H_FIELDS[] = +{ + { /* name */ RR_FRC_MODEf, + /* lsp */ 31, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 10, + /* len */ 21 + }, + { /* name */ RR_FRC_VAL_19_10f, + /* lsp */ 0, + /* len */ 10 + }, +}; + +rtk_regField_t RING_RATE_FRC_VALUE_L_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 10, + /* len */ 22 + }, + { /* name */ RR_FRC_VAL_9_0f, + /* lsp */ 0, + /* len */ 10 + }, +}; + +rtk_regField_t LFSR_INIT_SEED_FRC_VALUE_FIELDS[] = +{ + { /* name */ RS_FRC_MODEf, + /* lsp */ 31, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 10, + /* len */ 21 + }, + { /* name */ RS_FRC_VAL_9_0f, + /* lsp */ 0, + /* len */ 10 + }, +}; + +rtk_regField_t RING_RATE_RD_VALUE_H_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 10, + /* len */ 22 + }, + { /* name */ RR_RD_VAL_19_10f, + /* lsp */ 0, + /* len */ 10 + }, +}; + +rtk_regField_t RING_RATE_RD_VALUE_L_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 10, + /* len */ 22 + }, + { /* name */ RR_RD_VAL_9_0f, + /* lsp */ 0, + /* len */ 10 + }, +}; + +rtk_regField_t LFSR_INIT_SEED_RD_VALUE_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 10, + /* len */ 22 + }, + { /* name */ RS_RD_VAL_9_0f, + /* lsp */ 0, + /* len */ 10 + }, +}; + +rtk_regField_t P0_G2XG_CFG_CLR_ERR_FLAG_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ P0_G2XG_CFG_CLR_ERR_FLAGf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t P1_G2XG_CFG_CLR_ERR_FLAG_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ P1_G2XG_CFG_CLR_ERR_FLAGf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t P2_G2XG_CFG_CLR_ERR_FLAG_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ P2_G2XG_CFG_CLR_ERR_FLAGf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t P3_G2XG_CFG_CLR_ERR_FLAG_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ P3_G2XG_CFG_CLR_ERR_FLAGf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t G2XG_FIFO_CLR_CFG_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ P3_LDN_CLR_G2XG_FIFO_RXf, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ P2_LDN_CLR_G2XG_FIFO_RXf, + /* lsp */ 14, + /* len */ 1 + }, + { /* name */ P1_LDN_CLR_G2XG_FIFO_RXf, + /* lsp */ 13, + /* len */ 1 + }, + { /* name */ P0_LDN_CLR_G2XG_FIFO_RXf, + /* lsp */ 12, + /* len */ 1 + }, + { /* name */ P3_CLR_G2XG_FIFO_RXf, + /* lsp */ 11, + /* len */ 1 + }, + { /* name */ P2_CLR_G2XG_FIFO_RXf, + /* lsp */ 10, + /* len */ 1 + }, + { /* name */ P1_CLR_G2XG_FIFO_RXf, + /* lsp */ 9, + /* len */ 1 + }, + { /* name */ P0_CLR_G2XG_FIFO_RXf, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ P3_LDN_CLR_G2XG_FIFO_TXf, + /* lsp */ 7, + /* len */ 1 + }, + { /* name */ P2_LDN_CLR_G2XG_FIFO_TXf, + /* lsp */ 6, + /* len */ 1 + }, + { /* name */ P1_LDN_CLR_G2XG_FIFO_TXf, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ P0_LDN_CLR_G2XG_FIFO_TXf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ P3_CLR_G2XG_FIFO_TXf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ P2_CLR_G2XG_FIFO_TXf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ P1_CLR_G2XG_FIFO_TXf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ P0_CLR_G2XG_FIFO_TXf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t P2_XG2XG_IPG_DBG_INFO_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ CFG_P2_DBG_INFO_OFFf, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ CFG_P2_CUR_IPGf, + /* lsp */ 10, + /* len */ 5 + }, + { /* name */ CFG_P2_MAX_IPGf, + /* lsp */ 5, + /* len */ 5 + }, + { /* name */ CFG_P2_MIN_IPGf, + /* lsp */ 0, + /* len */ 5 + }, +}; + +rtk_regField_t P2_XG2XG_PRMB_DBG_INFO_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 20 + }, + { /* name */ CFG_P2_CUR_PRMBf, + /* lsp */ 8, + /* len */ 4 + }, + { /* name */ CFG_P2_MAX_PRMBf, + /* lsp */ 4, + /* len */ 4 + }, + { /* name */ CFG_P2_MIN_PRMBf, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t P2_XG2XG_THR_DBG_INFO_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 20 + }, + { /* name */ CFG_P2_CUR_THRf, + /* lsp */ 6, + /* len */ 6 + }, + { /* name */ CFG_P2_MAX_THRf, + /* lsp */ 0, + /* len */ 6 + }, +}; + +rtk_regField_t G2G_WATER_LEVEL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ CFG_G2G_WATER_LEVEL_X2Yf, + /* lsp */ 13, + /* len */ 3 + }, + { /* name */ CFG_G2G_WATER_LEVEL_Y2Xf, + /* lsp */ 10, + /* len */ 3 + }, + { /* name */ CFG_G2G_WATER_LEVEL_FDf, + /* lsp */ 7, + /* len */ 3 + }, + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 3 + }, + { /* name */ CGF_G2G_LPBKf, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t G2G_MISC_CFG_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ CLR_G2G_FIFOf, + /* lsp */ 12, + /* len */ 4 + }, + { /* name */ CFG_CLR_FIFO_OVTHRf, + /* lsp */ 11, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 10, + /* len */ 1 + }, + { /* name */ CFG_G2G_DIS_AUTO_RST_FIFOf, + /* lsp */ 9, + /* len */ 1 + }, + { /* name */ CFG_G2G_AFO_IPGCOMPf, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ CFG_G2G_AFE_IPG_CNTf, + /* lsp */ 4, + /* len */ 4 + }, + { /* name */ CFG_G2G_BGPTR_CHKf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ CFG_G2G_EDPTR_CHKf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ G2G_CLR_ERR_CNT_X2Yf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ G2G_CLR_ERR_CNT_Y2Xf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t G2G_ERR_CNT_01_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ G2G_0_ERR_CNT_X2Yf, + /* lsp */ 12, + /* len */ 4 + }, + { /* name */ G2G_0_ERR_CNT_Y2Xf, + /* lsp */ 8, + /* len */ 4 + }, + { /* name */ G2G_1_ERR_CNT_X2Yf, + /* lsp */ 4, + /* len */ 4 + }, + { /* name */ G2G_1_ERR_CNT_Y2Xf, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t G2G_ERR_CNT_23_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ G2G_2_ERR_CNT_X2Yf, + /* lsp */ 12, + /* len */ 4 + }, + { /* name */ G2G_2_ERR_CNT_Y2Xf, + /* lsp */ 8, + /* len */ 4 + }, + { /* name */ G2G_3_ERR_CNT_X2Yf, + /* lsp */ 4, + /* len */ 4 + }, + { /* name */ G2G_3_ERR_CNT_Y2Xf, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t XG2XG_WATER_LEVEL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 13, + /* len */ 19 + }, + { /* name */ CFG_WATER_LEVEL_Hf, + /* lsp */ 7, + /* len */ 6 + }, + { /* name */ CFG_WATER_LEVEL_Lf, + /* lsp */ 1, + /* len */ 6 + }, + { /* name */ CFG_EEE_DELETEf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t XG2XG_MISC_CFG_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ CFG_FIFO_START_FBf, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ CFG_FIFO_START_SEQf, + /* lsp */ 14, + /* len */ 1 + }, + { /* name */ CFG_XG2XG_FAULT_ONf, + /* lsp */ 13, + /* len */ 1 + }, + { /* name */ CFG_REC_LINK_INTRf, + /* lsp */ 12, + /* len */ 1 + }, + { /* name */ CFG_SEQ_RSV_ONf, + /* lsp */ 11, + /* len */ 1 + }, + { /* name */ CFG_ERROR_ONf, + /* lsp */ 10, + /* len */ 1 + }, + { /* name */ CFG_STK_PORT_P0f, + /* lsp */ 9, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ CFG_LDN_CLR_FIFO_FRC_VALf, + /* lsp */ 4, + /* len */ 4 + }, + { /* name */ CFG_LDN_CLR_FIFO_FRC_ONf, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t XG2XG_ERR_STATUS_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ XG2XG_OVRUN_Xf, + /* lsp */ 12, + /* len */ 4 + }, + { /* name */ XG2XG_UDRUN_Xf, + /* lsp */ 8, + /* len */ 4 + }, + { /* name */ XG2XG_OVRUN_Yf, + /* lsp */ 4, + /* len */ 4 + }, + { /* name */ XG2XG_UDRUN_Yf, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t EEE_LPI_DLY_CYCLE_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 14, + /* len */ 18 + }, + { /* name */ CFG_WATER_LEVEL_STf, + /* lsp */ 8, + /* len */ 6 + }, + { /* name */ TX_LPI_DLY_CYCLEf, + /* lsp */ 4, + /* len */ 4 + }, + { /* name */ RX_LPI_DLY_CYCLEf, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t PREAMBLE_RECOVERY_CRTL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 6, + /* len */ 26 + }, + { /* name */ CFG_PRMB_6BYTE_MODEf, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ CFG_PRMB_RCVY_ENf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ PRMB_RCVY_OVTHR_MONf, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t G2G_FIFO_CLR_CFG_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ P3_LDN_CLR_G2G_FIFO_RXf, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ P2_LDN_CLR_G2G_FIFO_RXf, + /* lsp */ 14, + /* len */ 1 + }, + { /* name */ P1_LDN_CLR_G2G_FIFO_RXf, + /* lsp */ 13, + /* len */ 1 + }, + { /* name */ P0_LDN_CLR_G2G_FIFO_RXf, + /* lsp */ 12, + /* len */ 1 + }, + { /* name */ P3_CLR_G2G_FIFO_RXf, + /* lsp */ 11, + /* len */ 1 + }, + { /* name */ P2_CLR_G2G_FIFO_RXf, + /* lsp */ 10, + /* len */ 1 + }, + { /* name */ P1_CLR_G2G_FIFO_RXf, + /* lsp */ 9, + /* len */ 1 + }, + { /* name */ P0_CLR_G2G_FIFO_RXf, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ P3_LDN_CLR_G2G_FIFO_TXf, + /* lsp */ 7, + /* len */ 1 + }, + { /* name */ P2_LDN_CLR_G2G_FIFO_TXf, + /* lsp */ 6, + /* len */ 1 + }, + { /* name */ P1_LDN_CLR_G2G_FIFO_TXf, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ P0_LDN_CLR_G2G_FIFO_TXf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ P3_CLR_G2G_FIFO_TXf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ P2_CLR_G2G_FIFO_TXf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ P1_CLR_G2G_FIFO_TXf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ P0_CLR_G2G_FIFO_TXf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t XG2XG_FIFO_CLR_CFG_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ P3_LDN_CLR_XG2XG_FIFO_RXf, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ P2_LDN_CLR_XG2XG_FIFO_RXf, + /* lsp */ 14, + /* len */ 1 + }, + { /* name */ P1_LDN_CLR_XG2XG_FIFO_RXf, + /* lsp */ 13, + /* len */ 1 + }, + { /* name */ P0_LDN_CLR_XG2XG_FIFO_RXf, + /* lsp */ 12, + /* len */ 1 + }, + { /* name */ P3_CLR_XG2XG_FIFO_RXf, + /* lsp */ 11, + /* len */ 1 + }, + { /* name */ P2_CLR_XG2XG_FIFO_RXf, + /* lsp */ 10, + /* len */ 1 + }, + { /* name */ P1_CLR_XG2XG_FIFO_RXf, + /* lsp */ 9, + /* len */ 1 + }, + { /* name */ P0_CLR_XG2XG_FIFO_RXf, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ P3_LDN_CLR_XG2XG_FIFO_TXf, + /* lsp */ 7, + /* len */ 1 + }, + { /* name */ P2_LDN_CLR_XG2XG_FIFO_TXf, + /* lsp */ 6, + /* len */ 1 + }, + { /* name */ P1_LDN_CLR_XG2XG_FIFO_TXf, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ P0_LDN_CLR_XG2XG_FIFO_TXf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ P3_CLR_XG2XG_FIFO_TXf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ P2_CLR_XG2XG_FIFO_TXf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ P1_CLR_XG2XG_FIFO_TXf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ P0_CLR_XG2XG_FIFO_TXf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t P3_XG2XG_IPG_DBG_INFO_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ CFG_P3_DBG_INFO_OFFf, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ CFG_P3_CUR_IPGf, + /* lsp */ 10, + /* len */ 5 + }, + { /* name */ CFG_P3_MAX_IPGf, + /* lsp */ 5, + /* len */ 5 + }, + { /* name */ CFG_P3_MIN_IPGf, + /* lsp */ 0, + /* len */ 5 + }, +}; + +rtk_regField_t P3_XG2XG_PRMB_DBG_INFO_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 20 + }, + { /* name */ CFG_P3_CUR_PRMBf, + /* lsp */ 8, + /* len */ 4 + }, + { /* name */ CFG_P3_MAX_PRMBf, + /* lsp */ 4, + /* len */ 4 + }, + { /* name */ CFG_P3_MIN_PRMBf, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t P3_XG2XG_THR_DBG_INFO_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 20 + }, + { /* name */ CFG_P3_CUR_THRf, + /* lsp */ 6, + /* len */ 6 + }, + { /* name */ CFG_P3_MAX_THRf, + /* lsp */ 0, + /* len */ 6 + }, +}; + +rtk_regField_t SYNCE_CTRL_0_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 30, + /* len */ 2 + }, + { /* name */ REG_EN_LOCK_SEL_MANUAL1f, + /* lsp */ 29, + /* len */ 1 + }, + { /* name */ CFG_LOCK_SEL1f, + /* lsp */ 28, + /* len */ 1 + }, + { /* name */ REG_SYNC_LOCK_OUT_SEL1f, + /* lsp */ 26, + /* len */ 2 + }, + { /* name */ REG_EN_SYNC_OUT_MANUAL1f, + /* lsp */ 25, + /* len */ 1 + }, + { /* name */ REG_EN_ICG_MANUAL1f, + /* lsp */ 24, + /* len */ 1 + }, + { /* name */ TRAIN_SRC1f, + /* lsp */ 23, + /* len */ 1 + }, + { /* name */ REG_PHY_SEL1f, + /* lsp */ 21, + /* len */ 2 + }, + { /* name */ CFG_SYNC_OUT_SEL1f, + /* lsp */ 20, + /* len */ 1 + }, + { /* name */ CFG_EN_ICG_SEL1f, + /* lsp */ 19, + /* len */ 1 + }, + { /* name */ CFG_IDLE_MODE1f, + /* lsp */ 18, + /* len */ 1 + }, + { /* name */ CFG_IDLE_OUT_SEL1f, + /* lsp */ 17, + /* len */ 1 + }, + { /* name */ REG_DIVIDER_SEL1f, + /* lsp */ 16, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 14, + /* len */ 2 + }, + { /* name */ REG_EN_LOCK_SEL_MANUAL0f, + /* lsp */ 13, + /* len */ 1 + }, + { /* name */ CFG_LOCK_SEL0f, + /* lsp */ 12, + /* len */ 1 + }, + { /* name */ REG_SYNC_LOCK_OUT_SEL0f, + /* lsp */ 10, + /* len */ 2 + }, + { /* name */ REG_EN_SYNC_OUT_MANUAL0f, + /* lsp */ 9, + /* len */ 1 + }, + { /* name */ REG_EN_ICG_MANUAL0f, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ TRAIN_SRC0f, + /* lsp */ 7, + /* len */ 1 + }, + { /* name */ REG_PHY_SEL0f, + /* lsp */ 5, + /* len */ 2 + }, + { /* name */ CFG_SYNC_OUT_SEL0f, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ CFG_EN_ICG_SEL0f, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ CFG_IDLE_MODE0f, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ CFG_IDLE_OUT_SEL0f, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ REG_DIVIDER_SEL0f, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t SYNCE_CTRL_1_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 28, + /* len */ 4 + }, + { /* name */ CFG_CKR_SEL3f, + /* lsp */ 27, + /* len */ 1 + }, + { /* name */ CFG_CKR_SEL2f, + /* lsp */ 26, + /* len */ 1 + }, + { /* name */ CFG_CKR_SEL1f, + /* lsp */ 25, + /* len */ 1 + }, + { /* name */ CFG_CKR_SEL0f, + /* lsp */ 24, + /* len */ 1 + }, + { /* name */ CFG_CLK_CH_SEL3f, + /* lsp */ 22, + /* len */ 2 + }, + { /* name */ CFG_CLK_CH_SEL2f, + /* lsp */ 20, + /* len */ 2 + }, + { /* name */ CFG_CLK_CH_SEL1f, + /* lsp */ 18, + /* len */ 2 + }, + { /* name */ CFG_CLK_CH_SEL0f, + /* lsp */ 16, + /* len */ 2 + }, + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 4 + }, + { /* name */ SYNCE_EN1f, + /* lsp */ 11, + /* len */ 1 + }, + { /* name */ SYNCE_EN0f, + /* lsp */ 10, + /* len */ 1 + }, + { /* name */ REG_EN_CKR_SEL_MANUAL3f, + /* lsp */ 9, + /* len */ 1 + }, + { /* name */ REG_EN_CKR_SEL_MANUAL2f, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ REG_EN_CKR_SEL_MANUAL1f, + /* lsp */ 7, + /* len */ 1 + }, + { /* name */ REG_EN_CKR_SEL_MANUAL0f, + /* lsp */ 6, + /* len */ 1 + }, + { /* name */ REG_EN_CH_SEL_MANUAL3f, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ REG_EN_CH_SEL_MANUAL2f, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ REG_EN_CH_SEL_MANUAL1f, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ REG_EN_CH_SEL_MANUAL0f, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ EN_SYNCE_LOCK1f, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ EN_SYNCE_LOCK0f, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t SYNCE_DUMMY1_FIELDS[] = +{ + { /* name */ SYNCE_DUMMY1f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t SYNCE_DUMMY2_FIELDS[] = +{ + { /* name */ SYNCE_DUMMY2f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t SYNCE_DUMMY3_FIELDS[] = +{ + { /* name */ SYNCE_DUMMY3f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t SYNCE_DUMMY4_FIELDS[] = +{ + { /* name */ SYNCE_DUMMY4f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t SYNCE_DUMMY5_FIELDS[] = +{ + { /* name */ SYNCE_DUMMY5f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t PKTGEN_GLOBAL_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ PKGN_TX_DONEf, + /* lsp */ 12, + /* len */ 4 + }, + { /* name */ PKG3_TX_SELf, + /* lsp */ 10, + /* len */ 2 + }, + { /* name */ PKG2_TX_SELf, + /* lsp */ 8, + /* len */ 2 + }, + { /* name */ PKG1_TX_SELf, + /* lsp */ 6, + /* len */ 2 + }, + { /* name */ PKG0_TX_SELf, + /* lsp */ 4, + /* len */ 2 + }, + { /* name */ PKGN_TX_CMDf, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t PKTGEN_PAYLOAD_IND_ACCESS_CTRL_FIELDS[] = +{ + { /* name */ SRAM_ACCCESS_CMDf, + /* lsp */ 31, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 24, + /* len */ 7 + }, + { /* name */ SRAM_ADDRESSf, + /* lsp */ 16, + /* len */ 8 + }, + { /* name */ STREAM_PAYLOAD_ACCCESS_TRIGGERf, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 8, + /* len */ 7 + }, + { /* name */ STREAM_PAYLOAD_SRAM_DATAf, + /* lsp */ 0, + /* len */ 8 + }, +}; + +rtk_regField_t PKTGEN_G2XG_FIFO_CTRL_FIELDS[] = +{ + { /* name */ PKTGEN_DUMMY0f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ PKG3_TX_CLK_SELf, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ PKG2_TX_CLK_SELf, + /* lsp */ 14, + /* len */ 1 + }, + { /* name */ PKG1_TX_CLK_SELf, + /* lsp */ 13, + /* len */ 1 + }, + { /* name */ PKG0_TX_CLK_SELf, + /* lsp */ 12, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 10, + /* len */ 2 + }, + { /* name */ PKG_G2XG_GTX_MIN_IPGf, + /* lsp */ 6, + /* len */ 4 + }, + { /* name */ PKG_G2XG_TX_RDFIFO_THRf, + /* lsp */ 0, + /* len */ 6 + }, +}; + +rtk_regField_t PKTGEN0_CTRL0_FIELDS[] = +{ + { /* name */ IBG_LENf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t PKTGEN0_CTRL1_FIELDS[] = +{ + { /* name */ BURST_CNTf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t PKTGEN0_CTRL2_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ BURST_SIZEf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t PKTGEN0_CTRL3_FIELDS[] = +{ + { /* name */ STREAM_LEN_MODf, + /* lsp */ 30, + /* len */ 2 + }, + { /* name */ STREAM_LEN_RNG_STARTf, + /* lsp */ 16, + /* len */ 14 + }, + { /* name */ RESERVEDf, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ STREAM_ETHERTYPE_MODf, + /* lsp */ 14, + /* len */ 1 + }, + { /* name */ STREAM_LEN_RNG_ENDf, + /* lsp */ 0, + /* len */ 14 + }, +}; + +rtk_regField_t PKTGEN0_CTRL4_FIELDS[] = +{ + { /* name */ STREAM_ETHERTYPEf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 12 + }, + { /* name */ STREAM_PAYLOAD_MODf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ STREAM_PAYLOAD_MASKf, + /* lsp */ 0, + /* len */ 3 + }, +}; + +rtk_regField_t PKTGEN0_CTRL5_FIELDS[] = +{ + { /* name */ STREAM_FIX_DMAC_Lf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t PKTGEN0_CTRL6_FIELDS[] = +{ + { /* name */ STREAM_FIX_DMAC_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ STREAM_FIX_SMAC_Hf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t PKTGEN0_CTRL7_FIELDS[] = +{ + { /* name */ STREAM_FIX_SMAC_Lf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t PKTGEN1_CTRL0_FIELDS[] = +{ + { /* name */ IBG_LENf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t PKTGEN1_CTRL1_FIELDS[] = +{ + { /* name */ BURST_CNTf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t PKTGEN1_CTRL2_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ BURST_SIZEf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t PKTGEN1_CTRL3_FIELDS[] = +{ + { /* name */ STREAM_LEN_MODf, + /* lsp */ 30, + /* len */ 2 + }, + { /* name */ STREAM_LEN_RNG_STARTf, + /* lsp */ 16, + /* len */ 14 + }, + { /* name */ RESERVEDf, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ STREAM_ETHERTYPE_MODf, + /* lsp */ 14, + /* len */ 1 + }, + { /* name */ STREAM_LEN_RNG_ENDf, + /* lsp */ 0, + /* len */ 14 + }, +}; + +rtk_regField_t PKTGEN1_CTRL4_FIELDS[] = +{ + { /* name */ STREAM_ETHERTYPEf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 12 + }, + { /* name */ STREAM_PAYLOAD_MODf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ STREAM_PAYLOAD_MASKf, + /* lsp */ 0, + /* len */ 3 + }, +}; + +rtk_regField_t PKTGEN1_CTRL5_FIELDS[] = +{ + { /* name */ STREAM_FIX_DMAC_Lf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t PKTGEN1_CTRL6_FIELDS[] = +{ + { /* name */ STREAM_FIX_DMAC_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ STREAM_FIX_SMAC_Hf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t PKTGEN1_CTRL7_FIELDS[] = +{ + { /* name */ STREAM_FIX_SMAC_Lf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t PKTGEN2_CTRL0_FIELDS[] = +{ + { /* name */ IBG_LENf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t PKTGEN2_CTRL1_FIELDS[] = +{ + { /* name */ BURST_CNTf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t PKTGEN2_CTRL2_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ BURST_SIZEf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t PKTGEN2_CTRL3_FIELDS[] = +{ + { /* name */ STREAM_LEN_MODf, + /* lsp */ 30, + /* len */ 2 + }, + { /* name */ STREAM_LEN_RNG_STARTf, + /* lsp */ 16, + /* len */ 14 + }, + { /* name */ RESERVEDf, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ STREAM_ETHERTYPE_MODf, + /* lsp */ 14, + /* len */ 1 + }, + { /* name */ STREAM_LEN_RNG_ENDf, + /* lsp */ 0, + /* len */ 14 + }, +}; + +rtk_regField_t PKTGEN2_CTRL4_FIELDS[] = +{ + { /* name */ STREAM_ETHERTYPEf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 12 + }, + { /* name */ STREAM_PAYLOAD_MODf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ STREAM_PAYLOAD_MASKf, + /* lsp */ 0, + /* len */ 3 + }, +}; + +rtk_regField_t PKTGEN2_CTRL5_FIELDS[] = +{ + { /* name */ STREAM_FIX_DMAC_Lf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t PKTGEN2_CTRL6_FIELDS[] = +{ + { /* name */ STREAM_FIX_DMAC_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ STREAM_FIX_SMAC_Hf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t PKTGEN2_CTRL7_FIELDS[] = +{ + { /* name */ STREAM_FIX_SMAC_Lf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t PKTGEN3_CTRL0_FIELDS[] = +{ + { /* name */ IBG_LENf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t PKTGEN3_CTRL1_FIELDS[] = +{ + { /* name */ BURST_CNTf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t PKTGEN3_CTRL2_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ BURST_SIZEf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t PKTGEN3_CTRL3_FIELDS[] = +{ + { /* name */ STREAM_LEN_MODf, + /* lsp */ 30, + /* len */ 2 + }, + { /* name */ STREAM_LEN_RNG_STARTf, + /* lsp */ 16, + /* len */ 14 + }, + { /* name */ RESERVEDf, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ STREAM_ETHERTYPE_MODf, + /* lsp */ 14, + /* len */ 1 + }, + { /* name */ STREAM_LEN_RNG_ENDf, + /* lsp */ 0, + /* len */ 14 + }, +}; + +rtk_regField_t PKTGEN3_CTRL4_FIELDS[] = +{ + { /* name */ STREAM_ETHERTYPEf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 12 + }, + { /* name */ STREAM_PAYLOAD_MODf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ STREAM_PAYLOAD_MASKf, + /* lsp */ 0, + /* len */ 3 + }, +}; + +rtk_regField_t PKTGEN3_CTRL5_FIELDS[] = +{ + { /* name */ STREAM_FIX_DMAC_Lf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t PKTGEN3_CTRL6_FIELDS[] = +{ + { /* name */ STREAM_FIX_DMAC_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ STREAM_FIX_SMAC_Hf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t PKTGEN3_CTRL7_FIELDS[] = +{ + { /* name */ STREAM_FIX_SMAC_Lf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t PKTGEN0_CTRL15_FIELDS[] = +{ + { /* name */ BURST_CNT_DBGf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t PKTGEN1_CTRL15_FIELDS[] = +{ + { /* name */ BURST_CNT_DBGf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t PKTGEN2_CTRL15_FIELDS[] = +{ + { /* name */ BURST_CNT_DBGf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t PKTGEN3_CTRL15_FIELDS[] = +{ + { /* name */ BURST_CNT_DBGf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t PHY_MODEL_ID_REV_CTRL_FIELDS[] = +{ + { /* name */ CFG_PHY_OUI_BIT19_BIT24f, + /* lsp */ 26, + /* len */ 6 + }, + { /* name */ CFG_PHY_MODEL_NOf, + /* lsp */ 20, + /* len */ 6 + }, + { /* name */ CFG_PHY_REVISION_NUMf, + /* lsp */ 16, + /* len */ 4 + }, + { /* name */ CFG_PHY_OUI_BIT3_BIT18f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +/* Module: SDS */ +rtk_regField_t SDS_MODE_SEL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 23, + /* len */ 9 + }, + { /* name */ CFG_MAC8_8221Bf, + /* lsp */ 22, + /* len */ 1 + }, + { /* name */ CFG_MAC3_8221Bf, + /* lsp */ 21, + /* len */ 1 + }, + { /* name */ SDS1_USX_SUB_MODEf, + /* lsp */ 16, + /* len */ 5 + }, + { /* name */ RESERVEDf, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ SDS0_USX_SUB_MODEf, + /* lsp */ 10, + /* len */ 5 + }, + { /* name */ SDS1_MODE_SELf, + /* lsp */ 5, + /* len */ 5 + }, + { /* name */ SDS0_MODE_SELf, + /* lsp */ 0, + /* len */ 5 + }, +}; + +rtk_regField_t SDS_INDACS_CMD_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ SDS_CMDf, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ SDS_RWOPf, + /* lsp */ 14, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 2 + }, + { /* name */ SDS_REGADf, + /* lsp */ 7, + /* len */ 5 + }, + { /* name */ SDS_PAGEf, + /* lsp */ 1, + /* len */ 6 + }, + { /* name */ SDS_INDEXf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t SDS_INDACS_RD_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ SDS_RDf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t SDS_INDACS_WD_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ SDS_WDf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t SDS0_STATUS_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 15, + /* len */ 17 + }, + { /* name */ LINK_FAULT_SDS1_TGXR0_CH0f, + /* lsp */ 12, + /* len */ 3 + }, + { /* name */ LINK_FAULT_SDS0_TGXR0_CH3f, + /* lsp */ 9, + /* len */ 3 + }, + { /* name */ LINK_FAULT_SDS0_TGXR0_CH2f, + /* lsp */ 6, + /* len */ 3 + }, + { /* name */ LINK_FAULT_SDS0_TGXR0_CH1f, + /* lsp */ 3, + /* len */ 3 + }, + { /* name */ LINK_FAULT_SDS0_TGXR0_CH0f, + /* lsp */ 0, + /* len */ 3 + }, +}; + +rtk_regField_t SDS0_CH0_RO_ABLTY_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 17, + /* len */ 15 + }, + { /* name */ SDS0_CH0_RO_ABLTYf, + /* lsp */ 0, + /* len */ 17 + }, +}; + +rtk_regField_t SDS0_CH1_RO_ABLTY_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 17, + /* len */ 15 + }, + { /* name */ SDS0_CH1_RO_ABLTYf, + /* lsp */ 0, + /* len */ 17 + }, +}; + +rtk_regField_t SDS0_CH2_RO_ABLTY_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 17, + /* len */ 15 + }, + { /* name */ SDS0_CH2_RO_ABLTYf, + /* lsp */ 0, + /* len */ 17 + }, +}; + +rtk_regField_t SDS0_CH3_3_RO_ABLTY_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 17, + /* len */ 15 + }, + { /* name */ SDS0_CH3_RO_ABLTYf, + /* lsp */ 0, + /* len */ 17 + }, +}; + +rtk_regField_t SDS1_CH0_RO_ABLTY_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 17, + /* len */ 15 + }, + { /* name */ SDS1_CH0_RO_ABLTYf, + /* lsp */ 0, + /* len */ 17 + }, +}; + +rtk_regField_t SDS0_1_MODE_RO_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 26, + /* len */ 6 + }, + { /* name */ SDS1_SUB_MODE_ROf, + /* lsp */ 21, + /* len */ 5 + }, + { /* name */ SDS1_MODE_ROf, + /* lsp */ 16, + /* len */ 5 + }, + { /* name */ RESERVEDf, + /* lsp */ 10, + /* len */ 6 + }, + { /* name */ SDS0_SUB_MODE_ROf, + /* lsp */ 5, + /* len */ 5 + }, + { /* name */ SDS0_MODE_ROf, + /* lsp */ 0, + /* len */ 5 + }, +}; + +rtk_regField_t CFG_DMY_SDS_0_FIELDS[] = +{ + { /* name */ CFG_DMY_0f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t CFG_DMY_SDS_1_FIELDS[] = +{ + { /* name */ CFG_DMY_1f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t SDS_OUI_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 24, + /* len */ 8 + }, + { /* name */ SDS_RTK_OUIf, + /* lsp */ 0, + /* len */ 24 + }, +}; + +rtk_regField_t SDS_VERSION_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 10, + /* len */ 22 + }, + { /* name */ SDS_MODEL_NOf, + /* lsp */ 4, + /* len */ 6 + }, + { /* name */ SDS_REVISION_NOf, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t SDS_OUI_TGR_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 24, + /* len */ 8 + }, + { /* name */ SDS_RTK_OUI_TGRf, + /* lsp */ 0, + /* len */ 24 + }, +}; + +rtk_regField_t SDS_VERSION_TGR_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 10, + /* len */ 22 + }, + { /* name */ SDS_MODEL_NO_TGRf, + /* lsp */ 4, + /* len */ 6 + }, + { /* name */ SDS_REVISION_NO_TGRf, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t SDS_INTF_CTRL1_FIELDS[] = +{ + { /* name */ SDS01_SDS_FRC_LDf, + /* lsp */ 31, + /* len */ 1 + }, + { /* name */ SDS01_SILENT_EN_INIf, + /* lsp */ 30, + /* len */ 1 + }, + { /* name */ SDS01_PDOWN_EN_INIf, + /* lsp */ 29, + /* len */ 1 + }, + { /* name */ SDS01_AUTONEG_EN_INIf, + /* lsp */ 28, + /* len */ 1 + }, + { /* name */ SDS01_AUTODET_EN_INIf, + /* lsp */ 27, + /* len */ 1 + }, + { /* name */ SDS01_SDS_RX_DISABLEf, + /* lsp */ 26, + /* len */ 1 + }, + { /* name */ SDS01_SDS_TX_DISABLEf, + /* lsp */ 25, + /* len */ 1 + }, + { /* name */ SDS01_FRC_REG4_FIB100f, + /* lsp */ 24, + /* len */ 1 + }, + { /* name */ SDS01_FRC_REG4_ENf, + /* lsp */ 23, + /* len */ 1 + }, + { /* name */ SDS01_CMD_STOP_GLI_CLKf, + /* lsp */ 15, + /* len */ 8 + }, + { /* name */ SDS01_STS_UPD_TXf, + /* lsp */ 7, + /* len */ 8 + }, + { /* name */ LOAD_SYS_PARf, + /* lsp */ 6, + /* len */ 1 + }, + { /* name */ PDOWN_EN_INI_TGRf, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ CFG_FB_ONf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ INTP_SRC_TGR0f, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ CFG_UNIDIR_EN_TGXR0f, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ TGR_ECC_ENf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ SDf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t SDS_INTF_CTRL2_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RSTR_ORI_AUTO_DET_SGf, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ AUTO_DET_SG3_UPD_ENf, + /* lsp */ 14, + /* len */ 1 + }, + { /* name */ AUTO_DET_SG2_UPD_ENf, + /* lsp */ 13, + /* len */ 1 + }, + { /* name */ AUTO_DET_SG1_UPD_ENf, + /* lsp */ 12, + /* len */ 1 + }, + { /* name */ AUTO_DET_SG0_UPD_ENf, + /* lsp */ 11, + /* len */ 1 + }, + { /* name */ CFG_SDSREG_BCST_ONf, + /* lsp */ 10, + /* len */ 1 + }, + { /* name */ CFG_SDS_BCST_IDXf, + /* lsp */ 5, + /* len */ 5 + }, + { /* name */ SDS01_LPI_GMII_SELf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ SDS01_SDS_PHY_MODEf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ SDS01_UNIDIR_TX_ABLEf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ SDS01_PAUSE_INIf, + /* lsp */ 0, + /* len */ 2 + }, +}; + +rtk_regField_t SDS_INTF_OUT1_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ SDS01_SDS_LINK_OK_SUMf, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ SDS01_FIB_ISOf, + /* lsp */ 14, + /* len */ 1 + }, + { /* name */ SDS01_FIB100_SDETf, + /* lsp */ 13, + /* len */ 1 + }, + { /* name */ SDS01_FIB100_DETf, + /* lsp */ 12, + /* len */ 1 + }, + { /* name */ SDS01_SDS_SDET_OUTf, + /* lsp */ 11, + /* len */ 1 + }, + { /* name */ RX_SYM_ERR_TGXR0f, + /* lsp */ 10, + /* len */ 1 + }, + { /* name */ RXIDLE_Df, + /* lsp */ 9, + /* len */ 1 + }, + { /* name */ SDS01_SDS_RX_SYM_ERR_ALLf, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ SDS01_SDS_LINK_OKf, + /* lsp */ 4, + /* len */ 4 + }, + { /* name */ SDS01_STS_UPD_RXf, + /* lsp */ 0, + /* len */ 4 + }, +}; + +/* Module: LED */ +rtk_regField_t LED_GLB_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 24, + /* len */ 8 + }, + { /* name */ BLINK_TIME_SELf, + /* lsp */ 21, + /* len */ 3 + }, + { /* name */ RESERVEDf, + /* lsp */ 19, + /* len */ 2 + }, + { /* name */ LED_LOAD_ENf, + /* lsp */ 18, + /* len */ 1 + }, + { /* name */ SYS_LED_MODEf, + /* lsp */ 16, + /* len */ 2 + }, + { /* name */ SYS_LED_ENf, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ FIB_UNIDIR_LED_ENf, + /* lsp */ 14, + /* len */ 1 + }, + { /* name */ POB_ENf, + /* lsp */ 13, + /* len */ 1 + }, + { /* name */ STP2_PWR_ON_LEDf, + /* lsp */ 9, + /* len */ 4 + }, + { /* name */ STP1_PWR_ON_LEDf, + /* lsp */ 5, + /* len */ 4 + }, + { /* name */ PWR_ON_BLINK_SELf, + /* lsp */ 3, + /* len */ 2 + }, + { /* name */ RESERVEDf, + /* lsp */ 0, + /* len */ 3 + }, +}; + +rtk_regField_t LED3_0_SET3_2_CTRL1_FIELDS[] = +{ + { /* name */ SET3_LED3_SEL1f, + /* lsp */ 28, + /* len */ 4 + }, + { /* name */ SET3_LED2_SEL1f, + /* lsp */ 24, + /* len */ 4 + }, + { /* name */ SET3_LED1_SEL1f, + /* lsp */ 20, + /* len */ 4 + }, + { /* name */ SET3_LED0_SEL1f, + /* lsp */ 16, + /* len */ 4 + }, + { /* name */ SET2_LED3_SEL1f, + /* lsp */ 12, + /* len */ 4 + }, + { /* name */ SET2_LED2_SEL1f, + /* lsp */ 8, + /* len */ 4 + }, + { /* name */ SET2_LED1_SEL1f, + /* lsp */ 4, + /* len */ 4 + }, + { /* name */ SET2_LED0_SEL1f, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t LED3_0_SET1_0_CTRL1_FIELDS[] = +{ + { /* name */ SET1_LED3_SEL1f, + /* lsp */ 28, + /* len */ 4 + }, + { /* name */ SET1_LED2_SEL1f, + /* lsp */ 24, + /* len */ 4 + }, + { /* name */ SET1_LED1_SEL1f, + /* lsp */ 20, + /* len */ 4 + }, + { /* name */ SET1_LED0_SEL1f, + /* lsp */ 16, + /* len */ 4 + }, + { /* name */ SET0_LED3_SEL1f, + /* lsp */ 12, + /* len */ 4 + }, + { /* name */ SET0_LED2_SEL1f, + /* lsp */ 8, + /* len */ 4 + }, + { /* name */ SET0_LED1_SEL1f, + /* lsp */ 4, + /* len */ 4 + }, + { /* name */ SET0_LED0_SEL1f, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t LED3_2_SET3_CTRL0_FIELDS[] = +{ + { /* name */ SET3_LED3_SEL0f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ SET3_LED2_SEL0f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t LED1_0_SET3_CTRL0_FIELDS[] = +{ + { /* name */ SET3_LED1_SEL0f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ SET3_LED0_SEL0f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t LED3_2_SET2_CTRL0_FIELDS[] = +{ + { /* name */ SET2_LED3_SEL0f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ SET2_LED2_SEL0f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t LED1_0_SET2_CTRL0_FIELDS[] = +{ + { /* name */ SET2_LED1_SEL0f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ SET2_LED0_SEL0f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t LED3_2_SET1_CTRL0_FIELDS[] = +{ + { /* name */ SET1_LED3_SEL0f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ SET1_LED2_SEL0f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t LED1_0_SET1_CTRL0_FIELDS[] = +{ + { /* name */ SET1_LED1_SEL0f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ SET1_LED0_SEL0f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t LED3_2_SET0_CTRL0_FIELDS[] = +{ + { /* name */ SET0_LED3_SEL0f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ SET0_LED2_SEL0f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t LED1_0_SET0_CTRL0_FIELDS[] = +{ + { /* name */ SET0_LED1_SEL0f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ SET0_LED0_SEL0f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t LED_PORT_SET_SEL_CTRL_FIELDS[] = +{ + { /* name */ LED_SET_PSELf, + /* lsp */ 0, + /* len */ 2 + }, +}; + +rtk_regField_t SW_LED_LOAD_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 1, + /* len */ 31 + }, + { /* name */ SW_LED_LOADf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t LED_PORT_SW_EN_CTRL_FIELDS[] = +{ + { /* name */ SW_CTRL_LED_ENf, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t LED_PORT_SW_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 20 + }, + { /* name */ SW_LED3_MODEf, + /* lsp */ 9, + /* len */ 3 + }, + { /* name */ SW_LED2_MODEf, + /* lsp */ 6, + /* len */ 3 + }, + { /* name */ SW_LED1_MODEf, + /* lsp */ 3, + /* len */ 3 + }, + { /* name */ SW_LED0_MODEf, + /* lsp */ 0, + /* len */ 3 + }, +}; + +rtk_regField_t LED_LOAD_LV1_10G_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 24, + /* len */ 8 + }, + { /* name */ LV1_THR_10Gf, + /* lsp */ 0, + /* len */ 24 + }, +}; + +rtk_regField_t LED_LOAD_LV2_10G_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 24, + /* len */ 8 + }, + { /* name */ LV2_THR_10Gf, + /* lsp */ 0, + /* len */ 24 + }, +}; + +rtk_regField_t LED_LOAD_LV3_10G_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 24, + /* len */ 8 + }, + { /* name */ LV3_THR_10Gf, + /* lsp */ 0, + /* len */ 24 + }, +}; + +rtk_regField_t LED_LOAD_LV1_5G_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 24, + /* len */ 8 + }, + { /* name */ LV1_THR_5Gf, + /* lsp */ 0, + /* len */ 24 + }, +}; + +rtk_regField_t LED_LOAD_LV2_5G_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 24, + /* len */ 8 + }, + { /* name */ LV2_THR_5Gf, + /* lsp */ 0, + /* len */ 24 + }, +}; + +rtk_regField_t LED_LOAD_LV3_5G_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 24, + /* len */ 8 + }, + { /* name */ LV3_THR_5Gf, + /* lsp */ 0, + /* len */ 24 + }, +}; + +rtk_regField_t LED_LOAD_LV1_2P5G_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 24, + /* len */ 8 + }, + { /* name */ LV1_THR_2P5Gf, + /* lsp */ 0, + /* len */ 24 + }, +}; + +rtk_regField_t LED_LOAD_LV2_2P5G_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 24, + /* len */ 8 + }, + { /* name */ LV2_THR_2P5Gf, + /* lsp */ 0, + /* len */ 24 + }, +}; + +rtk_regField_t LED_LOAD_LV3_2P5G_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 24, + /* len */ 8 + }, + { /* name */ LV3_THR_2P5Gf, + /* lsp */ 0, + /* len */ 24 + }, +}; + +rtk_regField_t LED_LOAD_LV1_1G_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 24, + /* len */ 8 + }, + { /* name */ LV1_THR_1Gf, + /* lsp */ 0, + /* len */ 24 + }, +}; + +rtk_regField_t LED_LOAD_LV2_1G_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 24, + /* len */ 8 + }, + { /* name */ LV2_THR_1Gf, + /* lsp */ 0, + /* len */ 24 + }, +}; + +rtk_regField_t LED_LOAD_LV3_1G_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 24, + /* len */ 8 + }, + { /* name */ LV3_THR_1Gf, + /* lsp */ 0, + /* len */ 24 + }, +}; + +rtk_regField_t LED_LOAD_LV1_500M_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 24, + /* len */ 8 + }, + { /* name */ LV1_THR_500Mf, + /* lsp */ 0, + /* len */ 24 + }, +}; + +rtk_regField_t LED_LOAD_LV2_500M_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 24, + /* len */ 8 + }, + { /* name */ LV2_THR_500Mf, + /* lsp */ 0, + /* len */ 24 + }, +}; + +rtk_regField_t LED_LOAD_LV3_500M_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 24, + /* len */ 8 + }, + { /* name */ LV3_THR_500Mf, + /* lsp */ 0, + /* len */ 24 + }, +}; + +rtk_regField_t LED_LOAD_LV1_100M_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 20, + /* len */ 12 + }, + { /* name */ LV1_THR_100Mf, + /* lsp */ 0, + /* len */ 20 + }, +}; + +rtk_regField_t LED_LOAD_LV2_100M_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 20, + /* len */ 12 + }, + { /* name */ LV2_THR_100Mf, + /* lsp */ 0, + /* len */ 20 + }, +}; + +rtk_regField_t LED_LOAD_LV3_100M_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 20, + /* len */ 12 + }, + { /* name */ LV3_THR_100Mf, + /* lsp */ 0, + /* len */ 20 + }, +}; + +rtk_regField_t LED_LOAD_LV1_10M_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 17, + /* len */ 15 + }, + { /* name */ LV1_THR_10Mf, + /* lsp */ 0, + /* len */ 17 + }, +}; + +rtk_regField_t LED_LOAD_LV2_10M_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 17, + /* len */ 15 + }, + { /* name */ LV2_THR_10Mf, + /* lsp */ 0, + /* len */ 17 + }, +}; + +rtk_regField_t LED_LOAD_LV3_10M_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 17, + /* len */ 15 + }, + { /* name */ LV3_THR_10Mf, + /* lsp */ 0, + /* len */ 17 + }, +}; + +rtk_regField_t LED_P_LOAD_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 30, + /* len */ 2 + }, + { /* name */ DV_SPEEDUP_LEDf, + /* lsp */ 29, + /* len */ 1 + }, + { /* name */ P_LOAD_CNTR_IDXf, + /* lsp */ 24, + /* len */ 5 + }, + { /* name */ P_LOAD_CNTRf, + /* lsp */ 0, + /* len */ 24 + }, +}; + +rtk_regField_t LED_GLB_ACTIVE_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 30, + /* len */ 2 + }, + { /* name */ CFG_PAD_LED29_ACTIVE_LOWf, + /* lsp */ 29, + /* len */ 1 + }, + { /* name */ CFG_PAD_LED28_ACTIVE_LOWf, + /* lsp */ 28, + /* len */ 1 + }, + { /* name */ CFG_PAD_LED27_ACTIVE_LOWf, + /* lsp */ 27, + /* len */ 1 + }, + { /* name */ CFG_PAD_LED26_ACTIVE_LOWf, + /* lsp */ 26, + /* len */ 1 + }, + { /* name */ CFG_PAD_LED25_ACTIVE_LOWf, + /* lsp */ 25, + /* len */ 1 + }, + { /* name */ CFG_PAD_LED24_ACTIVE_LOWf, + /* lsp */ 24, + /* len */ 1 + }, + { /* name */ CFG_PAD_LED23_ACTIVE_LOWf, + /* lsp */ 23, + /* len */ 1 + }, + { /* name */ CFG_PAD_LED22_ACTIVE_LOWf, + /* lsp */ 22, + /* len */ 1 + }, + { /* name */ CFG_PAD_LED21_ACTIVE_LOWf, + /* lsp */ 21, + /* len */ 1 + }, + { /* name */ CFG_PAD_LED20_ACTIVE_LOWf, + /* lsp */ 20, + /* len */ 1 + }, + { /* name */ CFG_PAD_LED19_ACTIVE_LOWf, + /* lsp */ 19, + /* len */ 1 + }, + { /* name */ CFG_PAD_LED18_ACTIVE_LOWf, + /* lsp */ 18, + /* len */ 1 + }, + { /* name */ CFG_PAD_LED17_ACTIVE_LOWf, + /* lsp */ 17, + /* len */ 1 + }, + { /* name */ CFG_PAD_LED16_ACTIVE_LOWf, + /* lsp */ 16, + /* len */ 1 + }, + { /* name */ CFG_PAD_LED15_ACTIVE_LOWf, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ CFG_PAD_LED14_ACTIVE_LOWf, + /* lsp */ 14, + /* len */ 1 + }, + { /* name */ CFG_PAD_LED13_ACTIVE_LOWf, + /* lsp */ 13, + /* len */ 1 + }, + { /* name */ CFG_PAD_LED12_ACTIVE_LOWf, + /* lsp */ 12, + /* len */ 1 + }, + { /* name */ CFG_PAD_LED11_ACTIVE_LOWf, + /* lsp */ 11, + /* len */ 1 + }, + { /* name */ CFG_PAD_LED10_ACTIVE_LOWf, + /* lsp */ 10, + /* len */ 1 + }, + { /* name */ CFG_PAD_LED9_ACTIVE_LOWf, + /* lsp */ 9, + /* len */ 1 + }, + { /* name */ CFG_PAD_LED8_ACTIVE_LOWf, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ CFG_PAD_LED7_ACTIVE_LOWf, + /* lsp */ 7, + /* len */ 1 + }, + { /* name */ CFG_PAD_LED6_ACTIVE_LOWf, + /* lsp */ 6, + /* len */ 1 + }, + { /* name */ CFG_PAD_LED5_ACTIVE_LOWf, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ CFG_PAD_LED4_ACTIVE_LOWf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ CFG_PAD_LED3_ACTIVE_LOWf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ CFG_PAD_LED2_ACTIVE_LOWf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ CFG_PAD_LED1_ACTIVE_LOWf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ CFG_PAD_LED0_ACTIVE_LOWf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t LED_GLB_IO_EN_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 31, + /* len */ 1 + }, + { /* name */ LED_PAD_ENf, + /* lsp */ 30, + /* len */ 1 + }, + { /* name */ CFG_PARA_LED29_IO_ENf, + /* lsp */ 29, + /* len */ 1 + }, + { /* name */ CFG_PARA_LED28_IO_ENf, + /* lsp */ 28, + /* len */ 1 + }, + { /* name */ CFG_PARA_LED27_IO_ENf, + /* lsp */ 27, + /* len */ 1 + }, + { /* name */ CFG_PARA_LED26_IO_ENf, + /* lsp */ 26, + /* len */ 1 + }, + { /* name */ CFG_PARA_LED25_IO_ENf, + /* lsp */ 25, + /* len */ 1 + }, + { /* name */ CFG_PARA_LED24_IO_ENf, + /* lsp */ 24, + /* len */ 1 + }, + { /* name */ CFG_PARA_LED23_IO_ENf, + /* lsp */ 23, + /* len */ 1 + }, + { /* name */ CFG_PARA_LED22_IO_ENf, + /* lsp */ 22, + /* len */ 1 + }, + { /* name */ CFG_PARA_LED21_IO_ENf, + /* lsp */ 21, + /* len */ 1 + }, + { /* name */ CFG_PARA_LED20_IO_ENf, + /* lsp */ 20, + /* len */ 1 + }, + { /* name */ CFG_PARA_LED19_IO_ENf, + /* lsp */ 19, + /* len */ 1 + }, + { /* name */ CFG_PARA_LED18_IO_ENf, + /* lsp */ 18, + /* len */ 1 + }, + { /* name */ CFG_PARA_LED17_IO_ENf, + /* lsp */ 17, + /* len */ 1 + }, + { /* name */ CFG_PARA_LED16_IO_ENf, + /* lsp */ 16, + /* len */ 1 + }, + { /* name */ CFG_PARA_LED15_IO_ENf, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ CFG_PARA_LED14_IO_ENf, + /* lsp */ 14, + /* len */ 1 + }, + { /* name */ CFG_PARA_LED13_IO_ENf, + /* lsp */ 13, + /* len */ 1 + }, + { /* name */ CFG_PARA_LED12_IO_ENf, + /* lsp */ 12, + /* len */ 1 + }, + { /* name */ CFG_PARA_LED11_IO_ENf, + /* lsp */ 11, + /* len */ 1 + }, + { /* name */ CFG_PARA_LED10_IO_ENf, + /* lsp */ 10, + /* len */ 1 + }, + { /* name */ CFG_PARA_LED9_IO_ENf, + /* lsp */ 9, + /* len */ 1 + }, + { /* name */ CFG_PARA_LED8_IO_ENf, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ CFG_PARA_LED7_IO_ENf, + /* lsp */ 7, + /* len */ 1 + }, + { /* name */ CFG_PARA_LED6_IO_ENf, + /* lsp */ 6, + /* len */ 1 + }, + { /* name */ CFG_PARA_LED5_IO_ENf, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ CFG_PARA_LED4_IO_ENf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ CFG_PARA_LED3_IO_ENf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ CFG_PARA_LED2_IO_ENf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ CFG_PARA_LED1_IO_ENf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ CFG_PARA_LED0_IO_ENf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t LED_GLB_MUX_1_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 30, + /* len */ 2 + }, + { /* name */ CFG_PAD_LED4_MUXf, + /* lsp */ 24, + /* len */ 6 + }, + { /* name */ CFG_PAD_LED3_MUXf, + /* lsp */ 18, + /* len */ 6 + }, + { /* name */ CFG_PAD_LED2_MUXf, + /* lsp */ 12, + /* len */ 6 + }, + { /* name */ CFG_PAD_LED1_MUXf, + /* lsp */ 6, + /* len */ 6 + }, + { /* name */ CFG_PAD_LED0_MUXf, + /* lsp */ 0, + /* len */ 6 + }, +}; + +rtk_regField_t LED_GLB_MUX_2_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 30, + /* len */ 2 + }, + { /* name */ CFG_PAD_LED9_MUXf, + /* lsp */ 24, + /* len */ 6 + }, + { /* name */ CFG_PAD_LED8_MUXf, + /* lsp */ 18, + /* len */ 6 + }, + { /* name */ CFG_PAD_LED7_MUXf, + /* lsp */ 12, + /* len */ 6 + }, + { /* name */ CFG_PAD_LED6_MUXf, + /* lsp */ 6, + /* len */ 6 + }, + { /* name */ CFG_PAD_LED5_MUXf, + /* lsp */ 0, + /* len */ 6 + }, +}; + +rtk_regField_t LED_GLB_MUX_3_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 30, + /* len */ 2 + }, + { /* name */ CFG_PAD_LED14_MUXf, + /* lsp */ 24, + /* len */ 6 + }, + { /* name */ CFG_PAD_LED13_MUXf, + /* lsp */ 18, + /* len */ 6 + }, + { /* name */ CFG_PAD_LED12_MUXf, + /* lsp */ 12, + /* len */ 6 + }, + { /* name */ CFG_PAD_LED11_MUXf, + /* lsp */ 6, + /* len */ 6 + }, + { /* name */ CFG_PAD_LED10_MUXf, + /* lsp */ 0, + /* len */ 6 + }, +}; + +rtk_regField_t LED_GLB_MUX_4_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 30, + /* len */ 2 + }, + { /* name */ CFG_PAD_LED19_MUXf, + /* lsp */ 24, + /* len */ 6 + }, + { /* name */ CFG_PAD_LED18_MUXf, + /* lsp */ 18, + /* len */ 6 + }, + { /* name */ CFG_PAD_LED17_MUXf, + /* lsp */ 12, + /* len */ 6 + }, + { /* name */ CFG_PAD_LED16_MUXf, + /* lsp */ 6, + /* len */ 6 + }, + { /* name */ CFG_PAD_LED15_MUXf, + /* lsp */ 0, + /* len */ 6 + }, +}; + +rtk_regField_t LED_GLB_MUX_5_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 30, + /* len */ 2 + }, + { /* name */ CFG_PAD_LED24_MUXf, + /* lsp */ 24, + /* len */ 6 + }, + { /* name */ CFG_PAD_LED23_MUXf, + /* lsp */ 18, + /* len */ 6 + }, + { /* name */ CFG_PAD_LED22_MUXf, + /* lsp */ 12, + /* len */ 6 + }, + { /* name */ CFG_PAD_LED21_MUXf, + /* lsp */ 6, + /* len */ 6 + }, + { /* name */ CFG_PAD_LED20_MUXf, + /* lsp */ 0, + /* len */ 6 + }, +}; + +rtk_regField_t LED_GLB_MUX_6_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 18, + /* len */ 14 + }, + { /* name */ CFG_PAD_LED27_MUXf, + /* lsp */ 12, + /* len */ 6 + }, + { /* name */ CFG_PAD_LED26_MUXf, + /* lsp */ 6, + /* len */ 6 + }, + { /* name */ CFG_PAD_LED25_MUXf, + /* lsp */ 0, + /* len */ 6 + }, +}; + +rtk_regField_t LED_RLDP_CTRL_1_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 5, + /* len */ 27 + }, + { /* name */ LOOP_DETECT_RATEf, + /* lsp */ 2, + /* len */ 3 + }, + { /* name */ RLDP_LED_ENABLEf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ GLB_RLDP_LED_ENABLEf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t LED_RLDP_CTRL_2_FIELDS[] = +{ + { /* name */ P7_LED3_0_RLDP_MASKf, + /* lsp */ 28, + /* len */ 4 + }, + { /* name */ P6_LED3_0_RLDP_MASKf, + /* lsp */ 24, + /* len */ 4 + }, + { /* name */ P5_LED3_0_RLDP_MASKf, + /* lsp */ 20, + /* len */ 4 + }, + { /* name */ P4_LED3_0_RLDP_MASKf, + /* lsp */ 16, + /* len */ 4 + }, + { /* name */ P3_LED3_0_RLDP_MASKf, + /* lsp */ 12, + /* len */ 4 + }, + { /* name */ P2_LED3_0_RLDP_MASKf, + /* lsp */ 8, + /* len */ 4 + }, + { /* name */ P1_LED3_0_RLDP_MASKf, + /* lsp */ 4, + /* len */ 4 + }, + { /* name */ P0_LED3_0_RLDP_MASKf, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t LED_RLDP_CTRL_3_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 28 + }, + { /* name */ P8_LED3_0_RLDP_MASKf, + /* lsp */ 0, + /* len */ 4 + }, +}; + +/* Module: Smart Packet Generator */ +rtk_regField_t SPG_GLB_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 3, + /* len */ 29 + }, + { /* name */ GRP_TX_CMDf, + /* lsp */ 1, + /* len */ 2 + }, + { /* name */ SPG_MODEf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t PKB_ACC_DEBUG_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 1, + /* len */ 31 + }, + { /* name */ DBG_ACC_PKB_ENf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t SPG_PORT_TX_GRP_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 9, + /* len */ 23 + }, + { /* name */ GRP_TX_PORTf, + /* lsp */ 0, + /* len */ 9 + }, +}; + +rtk_regField_t SPG_GLOBAL_STS_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 9, + /* len */ 23 + }, + { /* name */ TX_DONE_PORTf, + /* lsp */ 0, + /* len */ 9 + }, +}; + +rtk_regField_t SPG_PORT_IBG_CTRL0_FIELDS[] = +{ + { /* name */ IBG_LENf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t SPG_PORT_IBG_CTRL1_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ IBG_SIZEf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t SPG_PORT_IPG_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 20, + /* len */ 12 + }, + { /* name */ IPG_LENf, + /* lsp */ 0, + /* len */ 20 + }, +}; + +rtk_regField_t SPG_PORT_PKT_CNT_H_FIELDS[] = +{ + { /* name */ PKT_CNT_HIGHf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t SPG_PORT_PKT_CNT_L_FIELDS[] = +{ + { /* name */ PKT_CNT_LOWf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t SPG_PORT_PKT_CNT_DBG_H_FIELDS[] = +{ + { /* name */ PKT_CNT_DBG_HIGHf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t SPG_PORT_PKT_CNT_DBG_L_FIELDS[] = +{ + { /* name */ PKT_CNT_DBG_LOWf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t SPG_PORT_STREAM0_CTRL0_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 14, + /* len */ 18 + }, + { /* name */ BAD_CRC_EN_0f, + /* lsp */ 13, + /* len */ 1 + }, + { /* name */ STREAM_DA_MOD_0f, + /* lsp */ 11, + /* len */ 2 + }, + { /* name */ STREAM_SA_MOD_0f, + /* lsp */ 9, + /* len */ 2 + }, + { /* name */ STREAM_LEN_TYPE_0f, + /* lsp */ 7, + /* len */ 2 + }, + { /* name */ STREAM_CONTENT_OFFSET_0f, + /* lsp */ 2, + /* len */ 5 + }, + { /* name */ STREAM_CONTENT_MOD_0f, + /* lsp */ 0, + /* len */ 2 + }, +}; + +rtk_regField_t SPG_PORT_STREAM0_CTRL1_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 30, + /* len */ 2 + }, + { /* name */ STREAM_LEN_RNG_START_0f, + /* lsp */ 16, + /* len */ 14 + }, + { /* name */ RESERVEDf, + /* lsp */ 14, + /* len */ 2 + }, + { /* name */ STREAM_LEN_RNG_END_0f, + /* lsp */ 0, + /* len */ 14 + }, +}; + +rtk_regField_t SPG_PORT_STREAM0_CTRL2_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 31, + /* len */ 1 + }, + { /* name */ STREAM_DA_ADD_CNT_0f, + /* lsp */ 16, + /* len */ 15 + }, + { /* name */ RESERVEDf, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ STREAM_SA_ADD_CNT_0f, + /* lsp */ 0, + /* len */ 15 + }, +}; + +rtk_regField_t SPG_PORT_STREAM0_CTRL3_FIELDS[] = +{ + { /* name */ STREAM_REPEAT_CONTENT_0f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t SPG_PB_ACCESS_CTRL0_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 6, + /* len */ 26 + }, + { /* name */ PB_INDEXf, + /* lsp */ 0, + /* len */ 6 + }, +}; + +rtk_regField_t SPG_PB_ACCESS_CTRL1_FIELDS[] = +{ + { /* name */ ACCESS_DATAf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t SPG_PB_ACCESS_CTRL2_FIELDS[] = +{ + { /* name */ PB_TRIGf, + /* lsp */ 31, + /* len */ 1 + }, + { /* name */ PB_TYPEf, + /* lsp */ 30, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 14 + }, + { /* name */ PB_CELL_INDEXf, + /* lsp */ 8, + /* len */ 8 + }, + { /* name */ PB_BYTE_INDEXf, + /* lsp */ 0, + /* len */ 8 + }, +}; + +rtk_regField_t SPG_PORT_INDEX_CTRL0_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 20 + }, + { /* name */ PORTN_INDEXf, + /* lsp */ 0, + /* len */ 12 + }, +}; + +rtk_regField_t SPG_GLOBAL_INDEX_CTRL0_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 20 + }, + { /* name */ PKT_INDEXf, + /* lsp */ 0, + /* len */ 12 + }, +}; + +rtk_regField_t SPG_PREAMBLE_LENGTH_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 28 + }, + { /* name */ SPG_PREAMBLE_LENGTHf, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t SPG_PREAMBLE_CONTENT_CTRL2_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ SPG_PREAMBLE_CONTENT2f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t SPG_PREAMBLE_CONTENT_CTRL1_FIELDS[] = +{ + { /* name */ SPG_PREAMBLE_CONTENT1f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t SPG_PREAMBLE_CONTENT_CTRL0_FIELDS[] = +{ + { /* name */ SPG_PREAMBLE_CONTENT0f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +/* Module: Interface */ +rtk_regField_t I2C_SLV_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 7, + /* len */ 25 + }, + { /* name */ CFG_SDA_DLYf, + /* lsp */ 1, + /* len */ 6 + }, + { /* name */ I2C_DATA_ENDIAN_SELf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t MAC_SLV_TIMEOUT_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 30, + /* len */ 2 + }, + { /* name */ I2C_TIMEOUT_SETf, + /* lsp */ 16, + /* len */ 14 + }, + { /* name */ I2C_TIMEOUT_FLAGf, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ SPI_TIMEOUT_SETf, + /* lsp */ 1, + /* len */ 14 + }, + { /* name */ SPI_TIMEOUT_FLAGf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t MAC_IF_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 28 + }, + { /* name */ DW8051_INDIRECT_EE_ENf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ SPI_SO_REFf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ REG_IF_SELf, + /* lsp */ 0, + /* len */ 2 + }, +}; + +rtk_regField_t SLV_MDX_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 7, + /* len */ 25 + }, + { /* name */ CFG_PRMB_SUPPf, + /* lsp */ 6, + /* len */ 1 + }, + { /* name */ CFG_SHORT_PRMBf, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ CFG_TA_CHK_ENf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ CFG_SLV_EDGE_SELf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ CFG_SLV_MDIO_DLYf, + /* lsp */ 1, + /* len */ 2 + }, + { /* name */ STRP_EN_SLV_MDC_DEGf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t I2C_MST_IF_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 18, + /* len */ 14 + }, + { /* name */ CFG_DATA_HOLD_TIME_1f, + /* lsp */ 17, + /* len */ 1 + }, + { /* name */ CFG_SCK_I_DLY_1f, + /* lsp */ 13, + /* len */ 4 + }, + { /* name */ CFG_WAIT_SCK_MODE_1f, + /* lsp */ 11, + /* len */ 2 + }, + { /* name */ I2C_OPEN_DRN_SCK_1f, + /* lsp */ 6, + /* len */ 5 + }, + { /* name */ I2C_OPEN_DRN_SDA_1f, + /* lsp */ 0, + /* len */ 6 + }, +}; + +rtk_regField_t I2C_MST1_CTRL1_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 23, + /* len */ 9 + }, + { /* name */ READ_MODEf, + /* lsp */ 22, + /* len */ 1 + }, + { /* name */ MEM_ADDR_WIDTHf, + /* lsp */ 20, + /* len */ 2 + }, + { /* name */ DATA_WIDTHf, + /* lsp */ 16, + /* len */ 4 + }, + { /* name */ SCL_OUT_SELf, + /* lsp */ 13, + /* len */ 3 + }, + { /* name */ SDA_OUT_SELf, + /* lsp */ 10, + /* len */ 3 + }, + { /* name */ DEV_ADDRf, + /* lsp */ 3, + /* len */ 7 + }, + { /* name */ RWOPf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ I2C_FAILf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ I2C_TRIGf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t I2C_MST1_CTRL2_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 19, + /* len */ 13 + }, + { /* name */ MST_CODEf, + /* lsp */ 16, + /* len */ 3 + }, + { /* name */ I2C_MST_CODEf, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ I2C_RESETf, + /* lsp */ 14, + /* len */ 1 + }, + { /* name */ CHK_ACK_DLYf, + /* lsp */ 10, + /* len */ 4 + }, + { /* name */ DRV_ACK_DLYf, + /* lsp */ 6, + /* len */ 4 + }, + { /* name */ BYTE_TO_BYTE_DLYf, + /* lsp */ 4, + /* len */ 2 + }, + { /* name */ TBUF_DELAYf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ SCL_FREQf, + /* lsp */ 0, + /* len */ 2 + }, +}; + +rtk_regField_t I2C_MST1_MEMADDR_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 24, + /* len */ 8 + }, + { /* name */ MEM_ADDRf, + /* lsp */ 0, + /* len */ 24 + }, +}; + +rtk_regField_t I2C_MST1_DATA_CTRL_FIELDS[] = +{ + { /* name */ DATAf, + /* lsp */ 0, + /* len */ 8 + }, +}; + +rtk_regField_t SPI_CTRL0_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 21, + /* len */ 11 + }, + { /* name */ SPI_OUT_SELf, + /* lsp */ 20, + /* len */ 1 + }, + { /* name */ SPI_RX_DLYf, + /* lsp */ 17, + /* len */ 3 + }, + { /* name */ SPI_CLK_DLYf, + /* lsp */ 14, + /* len */ 3 + }, + { /* name */ SPI_TX_DLYf, + /* lsp */ 11, + /* len */ 3 + }, + { /* name */ SPI_CLK_DIVf, + /* lsp */ 8, + /* len */ 3 + }, + { /* name */ SPI_CPHAf, + /* lsp */ 7, + /* len */ 1 + }, + { /* name */ SPI_CPOLf, + /* lsp */ 6, + /* len */ 1 + }, + { /* name */ SPI_TSLCHf, + /* lsp */ 3, + /* len */ 3 + }, + { /* name */ SPI_TCHSHf, + /* lsp */ 0, + /* len */ 3 + }, +}; + +rtk_regField_t SPI_CTRL1_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 23, + /* len */ 9 + }, + { /* name */ ADDR_WIDTHf, + /* lsp */ 20, + /* len */ 3 + }, + { /* name */ DATA_WIDTHf, + /* lsp */ 11, + /* len */ 9 + }, + { /* name */ BYPASS_DATA_BYTEf, + /* lsp */ 10, + /* len */ 1 + }, + { /* name */ SPI_CMD_TYPEf, + /* lsp */ 9, + /* len */ 1 + }, + { /* name */ SPI_CMDf, + /* lsp */ 1, + /* len */ 8 + }, + { /* name */ SPI_TRIGf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t SPI_DATA_FIELDS[] = +{ + { /* name */ SPI_DATAf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t SPI_ADDR_FIELDS[] = +{ + { /* name */ SPI_ADDRf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t GPIO_OUT0_FIELDS[] = +{ + { /* name */ GPIO_OUT_31_0f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t GPIO_OUT1_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 31, + /* len */ 1 + }, + { /* name */ GPIO_OUT_62_32f, + /* lsp */ 0, + /* len */ 31 + }, +}; + +rtk_regField_t GPIO_IN0_FIELDS[] = +{ + { /* name */ GPIO_IN_31_0f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t GPIO_IN1_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 31, + /* len */ 1 + }, + { /* name */ GPIO_IN_62_32f, + /* lsp */ 0, + /* len */ 31 + }, +}; + +rtk_regField_t GPIO_OE0_FIELDS[] = +{ + { /* name */ GPIO_OE_31_0f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t GPIO_OE1_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 31, + /* len */ 1 + }, + { /* name */ GPIO_OE_62_32f, + /* lsp */ 0, + /* len */ 31 + }, +}; + +rtk_regField_t GPIO_IMODE_54_52_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 6, + /* len */ 26 + }, + { /* name */ IMODE_GPIO_54f, + /* lsp */ 4, + /* len */ 2 + }, + { /* name */ IMODE_GPIO_53f, + /* lsp */ 2, + /* len */ 2 + }, + { /* name */ IMODE_GPIO_52f, + /* lsp */ 0, + /* len */ 2 + }, +}; + +rtk_regField_t INI_MODE_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 2, + /* len */ 30 + }, + { /* name */ INI_MODEf, + /* lsp */ 0, + /* len */ 2 + }, +}; + +rtk_regField_t PWM_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 20 + }, + { /* name */ PWM_OEf, + /* lsp */ 11, + /* len */ 1 + }, + { /* name */ PWM_DUTY_RATIOf, + /* lsp */ 3, + /* len */ 8 + }, + { /* name */ PWM_CLK_SELf, + /* lsp */ 0, + /* len */ 3 + }, +}; + +rtk_regField_t REGIF_TIMEOUT_INFO_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 20, + /* len */ 12 + }, + { /* name */ REGIF_TIME_OUTf, + /* lsp */ 19, + /* len */ 1 + }, + { /* name */ REGIF_AC_SOURf, + /* lsp */ 16, + /* len */ 3 + }, + { /* name */ REGIF_AC_ADDRf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +/* Module: TM */ +rtk_regField_t TM0_CTRL0_FIELDS[] = +{ + { /* name */ DUMY_TM0_CTRL0f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t TM0_CTRL1_FIELDS[] = +{ + { /* name */ DUMY_TM0_CTRL1f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t TM0_CTRL2_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 3, + /* len */ 29 + }, + { /* name */ REG_EN_LATCHf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 0, + /* len */ 2 + }, +}; + +rtk_regField_t TM0_CTRL3_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 20, + /* len */ 12 + }, + { /* name */ TM_HIGHCMP_ENf, + /* lsp */ 19, + /* len */ 1 + }, + { /* name */ TM_HIGH_THRf, + /* lsp */ 10, + /* len */ 9 + }, + { /* name */ TM_LOWCMP_ENf, + /* lsp */ 9, + /* len */ 1 + }, + { /* name */ TM_LOW_THRf, + /* lsp */ 0, + /* len */ 9 + }, +}; + +rtk_regField_t TM0_RESULT0_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 19, + /* len */ 13 + }, + { /* name */ TM_OUT_2_0f, + /* lsp */ 16, + /* len */ 3 + }, + { /* name */ TM_OUT_18_3f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t TM0_RESULT1_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 22, + /* len */ 10 + }, + { /* name */ TM_ADC_OUTf, + /* lsp */ 0, + /* len */ 22 + }, +}; + +rtk_regField_t TM0_RESULT2_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 20, + /* len */ 12 + }, + { /* name */ EN_TM_MAXf, + /* lsp */ 19, + /* len */ 1 + }, + { /* name */ TM_MAX_2_0f, + /* lsp */ 16, + /* len */ 3 + }, + { /* name */ TM_MAX_18_3f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t TM0_RESULT3_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 20, + /* len */ 12 + }, + { /* name */ EN_TM_MINf, + /* lsp */ 19, + /* len */ 1 + }, + { /* name */ TM_MIN_2_0f, + /* lsp */ 16, + /* len */ 3 + }, + { /* name */ TM_MIN_18_3f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t TM0_RESULT4_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 19, + /* len */ 13 + }, + { /* name */ TEMP_OUT_POWERON_2_0f, + /* lsp */ 16, + /* len */ 3 + }, + { /* name */ TEMP_OUT_POWERON_18_3f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t TM1_CTRL0_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 29, + /* len */ 3 + }, + { /* name */ REG_Af, + /* lsp */ 0, + /* len */ 29 + }, +}; + +rtk_regField_t TM1_CTRL1_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 22, + /* len */ 10 + }, + { /* name */ REG_Bf, + /* lsp */ 0, + /* len */ 22 + }, +}; + +rtk_regField_t TM1_CTRL2_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 15, + /* len */ 17 + }, + { /* name */ RSTB_TMf, + /* lsp */ 14, + /* len */ 1 + }, + { /* name */ REG_CHOPFREQSELf, + /* lsp */ 10, + /* len */ 4 + }, + { /* name */ REG_OSRf, + /* lsp */ 7, + /* len */ 3 + }, + { /* name */ REG_HOLD_ENf, + /* lsp */ 6, + /* len */ 1 + }, + { /* name */ REG_HOLD_DLYf, + /* lsp */ 4, + /* len */ 2 + }, + { /* name */ REG_CHOPENf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ REG_EN_LATCHf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ REG_BIASDEM_ENf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ REG_ADCCKSELf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t TM1_CTRL3_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 20, + /* len */ 12 + }, + { /* name */ TM_HIGHCMP_ENf, + /* lsp */ 19, + /* len */ 1 + }, + { /* name */ TM_HIGH_THRf, + /* lsp */ 10, + /* len */ 9 + }, + { /* name */ TM_LOWCMP_ENf, + /* lsp */ 9, + /* len */ 1 + }, + { /* name */ TM_LOW_THRf, + /* lsp */ 0, + /* len */ 9 + }, +}; + +rtk_regField_t TM1_RESULT0_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 19, + /* len */ 13 + }, + { /* name */ TM_OUT_2_0f, + /* lsp */ 16, + /* len */ 3 + }, + { /* name */ TM_OUT_18_3f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t TM1_RESULT1_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 22, + /* len */ 10 + }, + { /* name */ TM_ADC_OUTf, + /* lsp */ 0, + /* len */ 22 + }, +}; + +rtk_regField_t TM1_RESULT2_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 20, + /* len */ 12 + }, + { /* name */ EN_TM_MAXf, + /* lsp */ 19, + /* len */ 1 + }, + { /* name */ TM_MAX_2_0f, + /* lsp */ 16, + /* len */ 3 + }, + { /* name */ TM_MAX_18_3f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t TM1_RESULT3_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 20, + /* len */ 12 + }, + { /* name */ EN_TM_MINf, + /* lsp */ 19, + /* len */ 1 + }, + { /* name */ TM_MIN_2_0f, + /* lsp */ 16, + /* len */ 3 + }, + { /* name */ TM_MIN_18_3f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t TM1_RESULT4_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 19, + /* len */ 13 + }, + { /* name */ TEMP_OUT_POWERON_2_0f, + /* lsp */ 16, + /* len */ 3 + }, + { /* name */ TEMP_OUT_POWERON_18_3f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +/* Module: EFUSE&EEPROM */ +rtk_regField_t EFUSE_ACCESS_EN_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ EFUSE_ACCESS_ENf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t EFUSE_AUTOLOAD_CTRL_FIELDS[] = +{ + { /* name */ EFUSE_AUTOLOAD_TIMERf, + /* lsp */ 12, + /* len */ 20 + }, + { /* name */ EFUSE_AUTOLOAD_CNTf, + /* lsp */ 1, + /* len */ 11 + }, + { /* name */ EFUSE_RE_AUTOLOADf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t EFUSE_ACCESS_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ EFUSE_MODEf, + /* lsp */ 12, + /* len */ 4 + }, + { /* name */ EFUSE_CMDf, + /* lsp */ 11, + /* len */ 1 + }, + { /* name */ EFUSE_ADDRf, + /* lsp */ 0, + /* len */ 11 + }, +}; + +rtk_regField_t EFUSE_WDATA_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 8, + /* len */ 24 + }, + { /* name */ EFUSE_WDATAf, + /* lsp */ 0, + /* len */ 8 + }, +}; + +rtk_regField_t EFUSE_RDATA_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 8, + /* len */ 24 + }, + { /* name */ EFUSE_RDATAf, + /* lsp */ 0, + /* len */ 8 + }, +}; + +rtk_regField_t EFUSE_CP_MISC_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 3, + /* len */ 29 + }, + { /* name */ EFUSE_CP_CHKf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ EFUSE_REPAIR_CHKf, + /* lsp */ 0, + /* len */ 2 + }, +}; + +rtk_regField_t EFUSE_MARGIN_RD_CFG_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 28, + /* len */ 4 + }, + { /* name */ EFUSE_MARGIN_RD_ERR_CNTf, + /* lsp */ 16, + /* len */ 12 + }, + { /* name */ RESERVEDf, + /* lsp */ 11, + /* len */ 5 + }, + { /* name */ EFUSE_MARGIN_RD_END_ADRf, + /* lsp */ 0, + /* len */ 11 + }, +}; + +rtk_regField_t EFUSE_MARGIN_RD_ERR_1_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 24, + /* len */ 8 + }, + { /* name */ EFUSE_MARGIN_RD_ERR_DAT1f, + /* lsp */ 16, + /* len */ 8 + }, + { /* name */ RESERVEDf, + /* lsp */ 11, + /* len */ 5 + }, + { /* name */ EFUSE_MARGIN_RD_ERR_ADR1f, + /* lsp */ 0, + /* len */ 11 + }, +}; + +rtk_regField_t EFUSE_MARGIN_RD_ERR_2_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 24, + /* len */ 8 + }, + { /* name */ EFUSE_MARGIN_RD_ERR_DAT2f, + /* lsp */ 16, + /* len */ 8 + }, + { /* name */ RESERVEDf, + /* lsp */ 11, + /* len */ 5 + }, + { /* name */ EFUSE_MARGIN_RD_ERR_ADR2f, + /* lsp */ 0, + /* len */ 11 + }, +}; + +rtk_regField_t EFUSE_FREQ_SEL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 1, + /* len */ 31 + }, + { /* name */ EFUSE_FREQ_SELf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t EFUSE_MASS_OPERATION_CFG_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 28, + /* len */ 4 + }, + { /* name */ EFUSE_COMP_ERR_CNTf, + /* lsp */ 16, + /* len */ 12 + }, + { /* name */ RESERVEDf, + /* lsp */ 11, + /* len */ 5 + }, + { /* name */ EFUSE_MASS_OP_END_ADRf, + /* lsp */ 0, + /* len */ 11 + }, +}; + +rtk_regField_t EFUSE_MASS_COMP_ERR_1_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 24, + /* len */ 8 + }, + { /* name */ EFUSE_MASS_COMP_ERR_DAT1f, + /* lsp */ 16, + /* len */ 8 + }, + { /* name */ RESERVEDf, + /* lsp */ 11, + /* len */ 5 + }, + { /* name */ EFUSE_MASS_COMP_ERR_ADR1f, + /* lsp */ 0, + /* len */ 11 + }, +}; + +rtk_regField_t EFUSE_MASS_COMP_ERR_2_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 24, + /* len */ 8 + }, + { /* name */ EFUSE_MASS_COMP_ERR_DAT2f, + /* lsp */ 16, + /* len */ 8 + }, + { /* name */ RESERVEDf, + /* lsp */ 11, + /* len */ 5 + }, + { /* name */ EFUSE_MASS_COMP_ERR_ADR2f, + /* lsp */ 0, + /* len */ 11 + }, +}; + +rtk_regField_t EFUSE_MASS_DATA_REG_FIELDS[] = +{ + { /* name */ EFUSE_MASS_DATAf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t MAC_EEPROM_DOWN_LOAD_FREQ_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 2, + /* len */ 30 + }, + { /* name */ SCK_FREQ_SELf, + /* lsp */ 0, + /* len */ 2 + }, +}; + +rtk_regField_t MAC_EEPROM_DOWN_LOAD_STS_FIELDS[] = +{ + { /* name */ EEPROM_AUTO_LOAD_LENf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RESERVEDf, + /* lsp */ 3, + /* len */ 13 + }, + { /* name */ EEPROM_VALID_FAILf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ EEPROM_COMPLf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ NOEEPROMf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t EEPROM_VER_INFO_FIELDS[] = +{ + { /* name */ EEPROM_CODE_VERf, + /* lsp */ 24, + /* len */ 8 + }, + { /* name */ EEPROM_CODE_DATE_2f, + /* lsp */ 16, + /* len */ 8 + }, + { /* name */ EEPROM_CODE_DATE_1f, + /* lsp */ 8, + /* len */ 8 + }, + { /* name */ EEPROM_CODE_DATE_0f, + /* lsp */ 0, + /* len */ 8 + }, +}; + +rtk_regField_t EEPROM_AUTOLOAD_TIMER_FIELDS[] = +{ + { /* name */ EEPROM_AUTOLOAD_TIMERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t MAC_EEPROM_ADDR_LEN_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 1, + /* len */ 31 + }, + { /* name */ EEPROM_ADDR_LENf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +/* Module: Interrupt */ +rtk_regField_t IMR_INT_PORT_LINK_STS_CHG_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 10, + /* len */ 22 + }, + { /* name */ IMR_INT_PORT_LINK_STS_CHG_10_0f, + /* lsp */ 0, + /* len */ 10 + }, +}; + +rtk_regField_t IMR_INT_GPHY_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 28 + }, + { /* name */ IMR_INT_GPHY_3_0f, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t IMR_INT_LEARNOVER_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 10, + /* len */ 22 + }, + { /* name */ IMR_INT_LEARN_OVER_PORT_9_0f, + /* lsp */ 0, + /* len */ 10 + }, +}; + +rtk_regField_t IMR_INT_RLFD_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 9, + /* len */ 23 + }, + { /* name */ IMR_INT_RLFD_PORT_8_0f, + /* lsp */ 0, + /* len */ 9 + }, +}; + +rtk_regField_t IMR_INT_WOL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 13, + /* len */ 19 + }, + { /* name */ IMR_INT_PHYWOL_PORT_3_0f, + /* lsp */ 9, + /* len */ 4 + }, + { /* name */ IMR_INT_WOL_PORT_8_0f, + /* lsp */ 0, + /* len */ 9 + }, +}; + +rtk_regField_t IMR_INT_SERDES_LINK_FAULT_P_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 5, + /* len */ 27 + }, + { /* name */ IMR_INT_SERDES_LINK_FAULT_PORTf, + /* lsp */ 0, + /* len */ 5 + }, +}; + +rtk_regField_t IMR_INT_SDS_UPD_PHYSTS0_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 5, + /* len */ 27 + }, + { /* name */ IMR_INT_SDS_UPD_PHYSTSf, + /* lsp */ 0, + /* len */ 5 + }, +}; + +rtk_regField_t IMR_INT_GPIO_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 3, + /* len */ 29 + }, + { /* name */ IMR_INT_GPIOf, + /* lsp */ 0, + /* len */ 3 + }, +}; + +rtk_regField_t IMR_INT_MISC_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 25, + /* len */ 7 + }, + { /* name */ IMR_EXT_CPUIDE_EXTf, + /* lsp */ 24, + /* len */ 1 + }, + { /* name */ IMR_EXT_CPUIDE_ENRf, + /* lsp */ 23, + /* len */ 1 + }, + { /* name */ IMR_INT_MACSECWRP_3_0f, + /* lsp */ 19, + /* len */ 4 + }, + { /* name */ IMR_INT_PTP1588f, + /* lsp */ 18, + /* len */ 1 + }, + { /* name */ IMR_INT_ROUT_PBUFf, + /* lsp */ 17, + /* len */ 1 + }, + { /* name */ IMR_INT_METER_EXCEEDf, + /* lsp */ 16, + /* len */ 1 + }, + { /* name */ IMR_INT_LOOP_DETECTIONf, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 14, + /* len */ 1 + }, + { /* name */ IMR_INT_ACLf, + /* lsp */ 13, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 1 + }, + { /* name */ IMR_INT_AUTO_RECf, + /* lsp */ 11, + /* len */ 1 + }, + { /* name */ IMR_INT_SAMOVEf, + /* lsp */ 10, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 9, + /* len */ 1 + }, + { /* name */ IMR_INT_SERDES_RX_SYM_ERR_1_0f, + /* lsp */ 7, + /* len */ 2 + }, + { /* name */ IMR_INT_SMI_CHECK_REG_4_0f, + /* lsp */ 2, + /* len */ 5 + }, + { /* name */ IMR_INT_TM_LOWf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ IMR_INT_TM_HIGHf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t IMR_EXT_PORT_LINK_STS_CHG_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 10, + /* len */ 22 + }, + { /* name */ IMR_EXT_PORT_LINK_STS_CHG_10_0f, + /* lsp */ 0, + /* len */ 10 + }, +}; + +rtk_regField_t IMR_EXT_GPHY_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 28 + }, + { /* name */ IMR_EXT_GPHY_3_0f, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t IMR_EXT_LEARNOVER_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 10, + /* len */ 22 + }, + { /* name */ IMR_EXT_LEARN_OVER_PORT_9_0f, + /* lsp */ 0, + /* len */ 10 + }, +}; + +rtk_regField_t IMR_EXT_RLFD_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 9, + /* len */ 23 + }, + { /* name */ IMR_EXT_RLFD_PORT_8_0f, + /* lsp */ 0, + /* len */ 9 + }, +}; + +rtk_regField_t IMR_EXT_WOL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 13, + /* len */ 19 + }, + { /* name */ IMR_EXT_PHYWOL_PORT_3_0f, + /* lsp */ 9, + /* len */ 4 + }, + { /* name */ IMR_EXT_WOL_PORT_8_0f, + /* lsp */ 0, + /* len */ 9 + }, +}; + +rtk_regField_t IMR_EXT_SERDES_LINK_FAULT_P_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 5, + /* len */ 27 + }, + { /* name */ IMR_EXT_SERDES_LINK_FAULT_PORTf, + /* lsp */ 0, + /* len */ 5 + }, +}; + +rtk_regField_t IMR_EXT_SDS_UPD_PHYSTS0_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 5, + /* len */ 27 + }, + { /* name */ IMR_EXT_SDS_UPD_PHYSTSf, + /* lsp */ 0, + /* len */ 5 + }, +}; + +rtk_regField_t IMR_EXT_GPIO_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 3, + /* len */ 29 + }, + { /* name */ IMR_EXT_GPIOf, + /* lsp */ 0, + /* len */ 3 + }, +}; + +rtk_regField_t IMR_EXT_MISC_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 23, + /* len */ 9 + }, + { /* name */ IMR_EXT_MACSECWRP_3_0f, + /* lsp */ 19, + /* len */ 4 + }, + { /* name */ IMR_EXT_PTP1588f, + /* lsp */ 18, + /* len */ 1 + }, + { /* name */ IMR_EXT_ROUT_PBUFf, + /* lsp */ 17, + /* len */ 1 + }, + { /* name */ IMR_EXT_METER_EXCEEDf, + /* lsp */ 16, + /* len */ 1 + }, + { /* name */ IMR_EXT_LOOP_DETECTIONf, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ IMR_EXT_8051f, + /* lsp */ 14, + /* len */ 1 + }, + { /* name */ IMR_EXT_ACLf, + /* lsp */ 13, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 1 + }, + { /* name */ IMR_EXT_AUTO_RECf, + /* lsp */ 11, + /* len */ 1 + }, + { /* name */ IMR_EXT_SAMOVEf, + /* lsp */ 10, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 9, + /* len */ 1 + }, + { /* name */ IMR_EXT_SERDES_RX_SYM_ERR_1_0f, + /* lsp */ 7, + /* len */ 2 + }, + { /* name */ IMR_EXT_SMI_CHECK_REG_4_0f, + /* lsp */ 2, + /* len */ 5 + }, + { /* name */ IMR_EXT_TM_LOWf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ IMR_EXT_TM_HIGHf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t ISR_INT_GLB_FIELDS[] = +{ + { /* name */ ISR_INT_GLB_LINK_CHGf, + /* lsp */ 31, + /* len */ 1 + }, + { /* name */ ISR_INT_GLB_LEARN_OVERf, + /* lsp */ 30, + /* len */ 1 + }, + { /* name */ ISR_INT_GLB_GPHYf, + /* lsp */ 29, + /* len */ 1 + }, + { /* name */ ISR_INT_GLB_RLFDf, + /* lsp */ 28, + /* len */ 1 + }, + { /* name */ ISR_INT_GLB_WOLf, + /* lsp */ 27, + /* len */ 1 + }, + { /* name */ ISR_INT_GLB_SERDES_LINK_FAULT_Pf, + /* lsp */ 26, + /* len */ 1 + }, + { /* name */ ISR_INT_GLB_SDS_UPD_PHYSTSf, + /* lsp */ 25, + /* len */ 1 + }, + { /* name */ ISR_INT_GLB_ROUT_PBUFf, + /* lsp */ 24, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 17, + /* len */ 7 + }, + { /* name */ ISR_INT_GLB_PHYWOLf, + /* lsp */ 16, + /* len */ 1 + }, + { /* name */ ISR_INT_GLB_MACSECWRPf, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ ISR_INT_GLB_PTP1588f, + /* lsp */ 14, + /* len */ 1 + }, + { /* name */ ISR_INT_GLB_METER_EXCEEDf, + /* lsp */ 13, + /* len */ 1 + }, + { /* name */ ISR_INT_GLB_LOOP_DETECTIONf, + /* lsp */ 12, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 11, + /* len */ 1 + }, + { /* name */ ISR_INT_GLB_ACLf, + /* lsp */ 10, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 9, + /* len */ 1 + }, + { /* name */ ISR_INT_GLB_AUTO_RECf, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ ISR_INT_GLB_SAMOVEf, + /* lsp */ 7, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 6, + /* len */ 1 + }, + { /* name */ ISR_INT_GLB_GPIOf, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ ISR_INT_GLB_SDS_RX_SYM_ERRf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ ISR_INT_GLB_SMI_CHECKf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ ISR_INT_GLB_TERMAL_DETECTf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t ISR_EXT_GLB_FIELDS[] = +{ + { /* name */ ISR_EXT_GLB_LINK_CHGf, + /* lsp */ 31, + /* len */ 1 + }, + { /* name */ ISR_EXT_GLB_LEARN_OVERf, + /* lsp */ 30, + /* len */ 1 + }, + { /* name */ ISR_EXT_GLB_GPHYf, + /* lsp */ 29, + /* len */ 1 + }, + { /* name */ ISR_EXT_GLB_RLFDf, + /* lsp */ 28, + /* len */ 1 + }, + { /* name */ ISR_EXT_GLB_WOLf, + /* lsp */ 27, + /* len */ 1 + }, + { /* name */ ISR_EXT_GLB_SERDES_LINK_FAULT_Pf, + /* lsp */ 26, + /* len */ 1 + }, + { /* name */ ISR_EXT_GLB_SDS_UPD_PHYSTSf, + /* lsp */ 25, + /* len */ 1 + }, + { /* name */ ISR_EXT_GLB_ROUT_PBUFf, + /* lsp */ 24, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 19, + /* len */ 5 + }, + { /* name */ ISR_EXT_GLB_CPUIDE_EXTf, + /* lsp */ 18, + /* len */ 1 + }, + { /* name */ ISR_EXT_GLB_CPUIDE_ENRf, + /* lsp */ 17, + /* len */ 1 + }, + { /* name */ ISR_EXT_GLB_PHYWOLf, + /* lsp */ 16, + /* len */ 1 + }, + { /* name */ ISR_EXT_GLB_MACSECWRPf, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ ISR_EXT_GLB_PTP1588f, + /* lsp */ 14, + /* len */ 1 + }, + { /* name */ ISR_EXT_GLB_METER_EXCEEDf, + /* lsp */ 13, + /* len */ 1 + }, + { /* name */ ISR_EXT_GLB_LOOP_DETECTIONf, + /* lsp */ 12, + /* len */ 1 + }, + { /* name */ ISR_EXT_GLB_8051f, + /* lsp */ 11, + /* len */ 1 + }, + { /* name */ ISR_EXT_GLB_ACLf, + /* lsp */ 10, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 9, + /* len */ 1 + }, + { /* name */ ISR_EXT_GLB_AUTO_RECf, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ ISR_EXT_GLB_SAMOVEf, + /* lsp */ 7, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 6, + /* len */ 1 + }, + { /* name */ ISR_EXT_GLB_GPIOf, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ ISR_EXT_GLB_SDS_RX_SYM_ERRf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ ISR_EXT_GLB_SMI_CHECKf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ ISR_EXT_GLB_TERMAL_DETECTf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t ISR_SW_INT_MODE_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 8, + /* len */ 24 + }, + { /* name */ INTP_OUT_SDS_CTRLf, + /* lsp */ 7, + /* len */ 1 + }, + { /* name */ SWITCH_IEf, + /* lsp */ 6, + /* len */ 1 + }, + { /* name */ SW_INT_PULSE_INTERVALf, + /* lsp */ 3, + /* len */ 3 + }, + { /* name */ SW_INT_MODEf, + /* lsp */ 1, + /* len */ 2 + }, + { /* name */ SW_INT_ODf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t ISR_INT_PORT_LINK_STS_CHG_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 10, + /* len */ 22 + }, + { /* name */ ISR_INT_PORT_LINK_STS_CHG_9_0f, + /* lsp */ 0, + /* len */ 10 + }, +}; + +rtk_regField_t ISR_INT_GPHY_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 28 + }, + { /* name */ ISR_INT_GPHYf, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t ISR_INT_LEARNOVER_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 10, + /* len */ 22 + }, + { /* name */ ISR_INT_LEARN_OVER_PORT_9_0f, + /* lsp */ 0, + /* len */ 10 + }, +}; + +rtk_regField_t ISR_INT_TM_RLFD_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 9, + /* len */ 23 + }, + { /* name */ ISR_INT_RLFD_PORT_8_0f, + /* lsp */ 0, + /* len */ 9 + }, +}; + +rtk_regField_t ISR_INT_WOL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 13, + /* len */ 19 + }, + { /* name */ ISR_INT_PHYWOL_PORT_3_0f, + /* lsp */ 9, + /* len */ 4 + }, + { /* name */ ISR_INT_WOL_PORT_8_0f, + /* lsp */ 0, + /* len */ 9 + }, +}; + +rtk_regField_t ISR_INT_SERDES_LINK_FAULT_P_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 5, + /* len */ 27 + }, + { /* name */ ISR_INT_SERDES_LINK_FAULT_PORTf, + /* lsp */ 0, + /* len */ 5 + }, +}; + +rtk_regField_t ISR_INT_SDS_UPD_PHYSTS0_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 5, + /* len */ 27 + }, + { /* name */ ISR_INT_SDS_UPD_PHYSTSf, + /* lsp */ 0, + /* len */ 5 + }, +}; + +rtk_regField_t ISR_INT_GPIO_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 3, + /* len */ 29 + }, + { /* name */ ISR_INT_GPIOf, + /* lsp */ 0, + /* len */ 3 + }, +}; + +rtk_regField_t ISR_INT_MISC_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 23, + /* len */ 9 + }, + { /* name */ ISR_INT_MACSECWRP_3_0f, + /* lsp */ 19, + /* len */ 4 + }, + { /* name */ ISR_INT_PTP1588f, + /* lsp */ 18, + /* len */ 1 + }, + { /* name */ ISR_INT_ROUT_PBUFf, + /* lsp */ 17, + /* len */ 1 + }, + { /* name */ ISR_INT_METER_EXCEEDf, + /* lsp */ 16, + /* len */ 1 + }, + { /* name */ ISR_INT_LOOP_DETECTIONf, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 14, + /* len */ 1 + }, + { /* name */ ISR_INT_ACLf, + /* lsp */ 13, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 1 + }, + { /* name */ ISR_INT_AUTO_RECf, + /* lsp */ 11, + /* len */ 1 + }, + { /* name */ ISR_INT_SAMOVEf, + /* lsp */ 10, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 9, + /* len */ 1 + }, + { /* name */ ISR_INT_SERDES_RX_SYM_ERR_1_0f, + /* lsp */ 7, + /* len */ 2 + }, + { /* name */ ISR_INT_SMI_CHECK_REG_4_0f, + /* lsp */ 2, + /* len */ 5 + }, + { /* name */ ISR_INT_TM_LOWf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ ISR_INT_TM_HIGHf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t ISR_EXT_PORT_LINK_STS_CHG_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 10, + /* len */ 22 + }, + { /* name */ ISR_EXT_PORT_LINK_STS_CHG_9_0f, + /* lsp */ 0, + /* len */ 10 + }, +}; + +rtk_regField_t ISR_EXT_GPHY_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 28 + }, + { /* name */ ISR_EXT_GPHYf, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t ISR_EXT_LEARNOVER_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 10, + /* len */ 22 + }, + { /* name */ ISR_EXT_LEARN_OVER_PORT_9_0f, + /* lsp */ 0, + /* len */ 10 + }, +}; + +rtk_regField_t ISR_EXT_TM_RLFD_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 9, + /* len */ 23 + }, + { /* name */ ISR_EXT_RLFD_PORT_8_0f, + /* lsp */ 0, + /* len */ 9 + }, +}; + +rtk_regField_t ISR_EXT_WOL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 13, + /* len */ 19 + }, + { /* name */ ISR_EXT_PHYWOL_PORT_3_0f, + /* lsp */ 9, + /* len */ 4 + }, + { /* name */ ISR_EXT_WOL_PORT_8_0f, + /* lsp */ 0, + /* len */ 9 + }, +}; + +rtk_regField_t ISR_EXT_SERDES_LINK_FAULT_P_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 5, + /* len */ 27 + }, + { /* name */ ISR_EXT_SERDES_LINK_FAULT_PORTf, + /* lsp */ 0, + /* len */ 5 + }, +}; + +rtk_regField_t ISR_EXT_SDS_UPD_PHYSTS0_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 5, + /* len */ 27 + }, + { /* name */ ISR_EXT_SDS_UPD_PHYSTSf, + /* lsp */ 0, + /* len */ 5 + }, +}; + +rtk_regField_t ISR_EXT_GPIO_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 3, + /* len */ 29 + }, + { /* name */ ISR_EXT_GPIOf, + /* lsp */ 0, + /* len */ 3 + }, +}; + +rtk_regField_t ISR_EXT_MISC_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 23, + /* len */ 9 + }, + { /* name */ ISR_EXT_MACSECWRP_3_0f, + /* lsp */ 19, + /* len */ 4 + }, + { /* name */ ISR_EXT_PTP1588f, + /* lsp */ 18, + /* len */ 1 + }, + { /* name */ ISR_EXT_ROUT_PBUFf, + /* lsp */ 17, + /* len */ 1 + }, + { /* name */ ISR_EXT_METER_EXCEEDf, + /* lsp */ 16, + /* len */ 1 + }, + { /* name */ ISR_EXT_LOOP_DETECTIONf, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ ISR_EXT_8051f, + /* lsp */ 14, + /* len */ 1 + }, + { /* name */ ISR_EXT_ACLf, + /* lsp */ 13, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 1 + }, + { /* name */ ISR_EXT_AUTO_RECf, + /* lsp */ 11, + /* len */ 1 + }, + { /* name */ ISR_EXT_SAMOVEf, + /* lsp */ 10, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 9, + /* len */ 1 + }, + { /* name */ ISR_EXT_SERDES_RX_SYM_ERR_1_0f, + /* lsp */ 7, + /* len */ 2 + }, + { /* name */ ISR_EXT_SMI_CHECK_REG_4_0f, + /* lsp */ 2, + /* len */ 5 + }, + { /* name */ ISR_EXT_TM_LOWf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ ISR_EXT_TM_HIGHf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +/* Module: MIB Control */ +rtk_regField_t STAT_RST_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 2, + /* len */ 30 + }, + { /* name */ RST_MIB_VALf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ RST_GLB_MIBf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t STAT_PORT_RST_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 5, + /* len */ 27 + }, + { /* name */ RST_PORT_FLAGf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ RST_PORT_MIBf, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t STAT_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 2, + /* len */ 30 + }, + { /* name */ TX_CNT_TAGf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ RX_CNT_TAGf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t STAT_CNT_SET1_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 28, + /* len */ 4 + }, + { /* name */ CNT_SET1_LEN_MAXf, + /* lsp */ 14, + /* len */ 14 + }, + { /* name */ CNT_SET1_LEN_MINf, + /* lsp */ 0, + /* len */ 14 + }, +}; + +rtk_regField_t STAT_CNT_SET0_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 28, + /* len */ 4 + }, + { /* name */ CNT_SET0_LEN_MAXf, + /* lsp */ 14, + /* len */ 14 + }, + { /* name */ CNT_SET0_LEN_MINf, + /* lsp */ 0, + /* len */ 14 + }, +}; + +rtk_regField_t PHY_MIB_GLOBAL_CONFIG_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 20 + }, + { /* name */ START_MIBf, + /* lsp */ 11, + /* len */ 1 + }, + { /* name */ EN_LATCHf, + /* lsp */ 10, + /* len */ 1 + }, + { /* name */ MIB_RESET_VALUEf, + /* lsp */ 9, + /* len */ 1 + }, + { /* name */ MIB_GLOBAL_RESETf, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ MIB_PORTN_RESETf, + /* lsp */ 0, + /* len */ 8 + }, +}; + +rtk_regField_t DEBUG_MIB_RST_FIELDS[] = +{ + { /* name */ WRAP_MIB_RSTf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t INDIRECT_ACCESS_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 11, + /* len */ 21 + }, + { /* name */ MIB_IDf, + /* lsp */ 5, + /* len */ 6 + }, + { /* name */ PORT_IDf, + /* lsp */ 1, + /* len */ 4 + }, + { /* name */ ACC_CMDf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t INDIRECT_ACCESS_CNT_L_FIELDS[] = +{ + { /* name */ MIB_COUNTER_Lf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t INDIRECT_ACCESS_CNT_H_FIELDS[] = +{ + { /* name */ MIB_COUNTER_Hf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +/* Module: MIB Counter */ +rtk_regField_t PHY0_RX_MIB_CNTR0_FIELDS[] = +{ + { /* name */ PHY0_RX_TOTAL_PKTS_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ PHY0_RX_TOTAL_PKTS_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t PHY0_RX_MIB_CNTR1_FIELDS[] = +{ + { /* name */ PHY0_RX_GOOD_OCTETS_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ PHY0_RX_GOOD_OCTETS_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t PHY0_RX_MIB_CNTR2_FIELDS[] = +{ + { /* name */ PHY0_RX_GOOD_PKTS_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ PHY0_RX_GOOD_PKTS_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t PHY0_RX_MIB_CNTR3_FIELDS[] = +{ + { /* name */ PHY0_RX_CRC_ERRORSf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ PHY0_RX_SYMBOL_ERRORSf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t PHY0_TX_MIB_CNTR0_FIELDS[] = +{ + { /* name */ PHY0_TX_TOTAL_PKTS_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ PHY0_TX_TOTAL_PKTS_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t PHY0_TX_MIB_CNTR1_FIELDS[] = +{ + { /* name */ PHY0_TX_GOOD_OCTETS_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ PHY0_TX_GOOD_OCTETS_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t PHY0_TX_MIB_CNTR2_FIELDS[] = +{ + { /* name */ PHY0_TX_GOOD_PKTS_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ PHY0_TX_GOOD_PKTS_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t PHY0_TX_MIB_CNTR3_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ PHY0_TX_CRC_ERRORSf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t PHY1_RX_MIB_CNTR0_FIELDS[] = +{ + { /* name */ PHY1_RX_TOTAL_PKTS_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ PHY1_RX_TOTAL_PKTS_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t PHY1_RX_MIB_CNTR1_FIELDS[] = +{ + { /* name */ PHY1_RX_GOOD_OCTETS_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ PHY1_RX_GOOD_OCTETS_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t PHY1_RX_MIB_CNTR2_FIELDS[] = +{ + { /* name */ PHY1_RX_GOOD_PKTS_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ PHY1_RX_GOOD_PKTS_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t PHY1_RX_MIB_CNTR3_FIELDS[] = +{ + { /* name */ PHY1_RX_CRC_ERRORSf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ PHY1_RX_SYMBOL_ERRORSf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t PHY1_TX_MIB_CNTR0_FIELDS[] = +{ + { /* name */ PHY1_TX_TOTAL_PKTS_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ PHY1_TX_TOTAL_PKTS_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t PHY1_TX_MIB_CNTR1_FIELDS[] = +{ + { /* name */ PHY1_TX_GOOD_OCTETS_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ PHY1_TX_GOOD_OCTETS_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t PHY1_TX_MIB_CNTR2_FIELDS[] = +{ + { /* name */ PHY1_TX_GOOD_PKTS_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ PHY1_TX_GOOD_PKTS_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t PHY1_TX_MIB_CNTR3_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ PHY1_TX_CRC_ERRORSf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t PHY2_RX_MIB_CNTR0_FIELDS[] = +{ + { /* name */ PHY2_RX_TOTAL_PKTS_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ PHY2_RX_TOTAL_PKTS_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t PHY2_RX_MIB_CNTR1_FIELDS[] = +{ + { /* name */ PHY2_RX_GOOD_OCTETS_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ PHY2_RX_GOOD_OCTETS_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t PHY2_RX_MIB_CNTR2_FIELDS[] = +{ + { /* name */ PHY2_RX_GOOD_PKTS_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ PHY2_RX_GOOD_PKTS_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t PHY2_RX_MIB_CNTR3_FIELDS[] = +{ + { /* name */ PHY2_RX_CRC_ERRORSf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ PHY2_RX_SYMBOL_ERRORSf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t PHY2_TX_MIB_CNTR0_FIELDS[] = +{ + { /* name */ PHY2_TX_TOTAL_PKTS_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ PHY2_TX_TOTAL_PKTS_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t PHY2_TX_MIB_CNTR1_FIELDS[] = +{ + { /* name */ PHY2_TX_GOOD_OCTETS_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ PHY2_TX_GOOD_OCTETS_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t PHY2_TX_MIB_CNTR2_FIELDS[] = +{ + { /* name */ PHY2_TX_GOOD_PKTS_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ PHY2_TX_GOOD_PKTS_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t PHY2_TX_MIB_CNTR3_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ PHY2_TX_CRC_ERRORSf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t PHY3_RX_MIB_CNTR0_FIELDS[] = +{ + { /* name */ PHY3_RX_TOTAL_PKTS_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ PHY3_RX_TOTAL_PKTS_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t PHY3_RX_MIB_CNTR1_FIELDS[] = +{ + { /* name */ PHY3_RX_GOOD_OCTETS_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ PHY3_RX_GOOD_OCTETS_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t PHY3_RX_MIB_CNTR2_FIELDS[] = +{ + { /* name */ PHY3_RX_GOOD_PKTS_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ PHY3_RX_GOOD_PKTS_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t PHY3_RX_MIB_CNTR3_FIELDS[] = +{ + { /* name */ PHY3_RX_CRC_ERRORSf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ PHY3_RX_SYMBOL_ERRORSf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t PHY3_TX_MIB_CNTR0_FIELDS[] = +{ + { /* name */ PHY3_TX_TOTAL_PKTS_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ PHY3_TX_TOTAL_PKTS_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t PHY3_TX_MIB_CNTR1_FIELDS[] = +{ + { /* name */ PHY3_TX_GOOD_OCTETS_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ PHY3_TX_GOOD_OCTETS_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t PHY3_TX_MIB_CNTR2_FIELDS[] = +{ + { /* name */ PHY3_TX_GOOD_PKTS_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ PHY3_TX_GOOD_PKTS_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t PHY3_TX_MIB_CNTR3_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ PHY3_TX_CRC_ERRORSf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t SDS_CH0_RX_MIB_CNTR0_FIELDS[] = +{ + { /* name */ SDS_CH0_RX_TOTAL_PKTS_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ SDS_CH0_RX_TOTAL_PKTS_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t SDS_CH0_RX_MIB_CNTR1_FIELDS[] = +{ + { /* name */ SDS_CH0_RX_GOOD_OCTETS_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ SDS_CH0_RX_GOOD_OCTETS_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t SDS_CH0_RX_MIB_CNTR2_FIELDS[] = +{ + { /* name */ SDS_CH0_RX_GOOD_PKTS_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ SDS_CH0_RX_GOOD_PKTS_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t SDS_CH0_RX_MIB_CNTR3_FIELDS[] = +{ + { /* name */ SDS_CH0_RX_CRC_ERRORSf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ SDS_CH0_RX_SYMBOL_ERRORSf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t SDS_CH0_TX_MIB_CNTR0_FIELDS[] = +{ + { /* name */ SDS_CH0_TX_TOTAL_PKTS_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ SDS_CH0_TX_TOTAL_PKTS_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t SDS_CH0_TX_MIB_CNTR1_FIELDS[] = +{ + { /* name */ SDS_CH0_TX_GOOD_OCTETS_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ SDS_CH0_TX_GOOD_OCTETS_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t SDS_CH0_TX_MIB_CNTR2_FIELDS[] = +{ + { /* name */ SDS_CH0_TX_GOOD_PKTS_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ SDS_CH0_TX_GOOD_PKTS_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t SDS_CH0_TX_MIB_CNTR3_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ SDS_CH0_TX_CRC_ERRORSf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t SDS_CH1_RX_MIB_CNTR0_FIELDS[] = +{ + { /* name */ SDS_CH1_RX_TOTAL_PKTS_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ SDS_CH1_RX_TOTAL_PKTS_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t SDS_CH1_RX_MIB_CNTR1_FIELDS[] = +{ + { /* name */ SDS_CH1_RX_GOOD_OCTETS_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ SDS_CH1_RX_GOOD_OCTETS_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t SDS_CH1_RX_MIB_CNTR2_FIELDS[] = +{ + { /* name */ SDS_CH1_RX_GOOD_PKTS_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ SDS_CH1_RX_GOOD_PKTS_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t SDS_CH1_RX_MIB_CNTR3_FIELDS[] = +{ + { /* name */ SDS_CH1_RX_CRC_ERRORSf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ SDS_CH1_RX_SYMBOL_ERRORSf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t SDS_CH1_TX_MIB_CNTR0_FIELDS[] = +{ + { /* name */ SDS_CH1_TX_TOTAL_PKTS_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ SDS_CH1_TX_TOTAL_PKTS_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t SDS_CH1_TX_MIB_CNTR1_FIELDS[] = +{ + { /* name */ SDS_CH1_TX_GOOD_OCTETS_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ SDS_CH1_TX_GOOD_OCTETS_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t SDS_CH1_TX_MIB_CNTR2_FIELDS[] = +{ + { /* name */ SDS_CH1_TX_GOOD_PKTS_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ SDS_CH1_TX_GOOD_PKTS_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t SDS_CH1_TX_MIB_CNTR3_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ SDS_CH1_TX_CRC_ERRORSf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t SDS_CH2_RX_MIB_CNTR0_FIELDS[] = +{ + { /* name */ SDS_CH2_RX_TOTAL_PKTS_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ SDS_CH2_RX_TOTAL_PKTS_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t SDS_CH2_RX_MIB_CNTR1_FIELDS[] = +{ + { /* name */ SDS_CH2_RX_GOOD_OCTETS_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ SDS_CH2_RX_GOOD_OCTETS_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t SDS_CH2_RX_MIB_CNTR2_FIELDS[] = +{ + { /* name */ SDS_CH2_RX_GOOD_PKTS_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ SDS_CH2_RX_GOOD_PKTS_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t SDS_CH2_RX_MIB_CNTR3_FIELDS[] = +{ + { /* name */ SDS_CH2_RX_CRC_ERRORSf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ SDS_CH2_RX_SYMBOL_ERRORSf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t SDS_CH2_TX_MIB_CNTR0_FIELDS[] = +{ + { /* name */ SDS_CH2_TX_TOTAL_PKTS_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ SDS_CH2_TX_TOTAL_PKTS_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t SDS_CH2_TX_MIB_CNTR1_FIELDS[] = +{ + { /* name */ SDS_CH2_TX_GOOD_OCTETS_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ SDS_CH2_TX_GOOD_OCTETS_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t SDS_CH2_TX_MIB_CNTR2_FIELDS[] = +{ + { /* name */ SDS_CH2_TX_GOOD_PKTS_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ SDS_CH2_TX_GOOD_PKTS_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t SDS_CH2_TX_MIB_CNTR3_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ SDS_CH2_TX_CRC_ERRORSf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t SDS_CH3_RX_MIB_CNTR0_FIELDS[] = +{ + { /* name */ SDS_CH3_RX_TOTAL_PKTS_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ SDS_CH3_RX_TOTAL_PKTS_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t SDS_CH3_RX_MIB_CNTR1_FIELDS[] = +{ + { /* name */ SDS_CH3_RX_GOOD_OCTETS_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ SDS_CH3_RX_GOOD_OCTETS_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t SDS_CH3_RX_MIB_CNTR2_FIELDS[] = +{ + { /* name */ SDS_CH3_RX_GOOD_PKTS_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ SDS_CH3_RX_GOOD_PKTS_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t SDS_CH3_RX_MIB_CNTR3_FIELDS[] = +{ + { /* name */ SDS_CH3_RX_CRC_ERRORSf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ SDS_CH3_RX_SYMBOL_ERRORSf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t SDS_CH3_TX_MIB_CNTR0_FIELDS[] = +{ + { /* name */ SDS_CH3_TX_TOTAL_PKTS_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ SDS_CH3_TX_TOTAL_PKTS_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t SDS_CH3_TX_MIB_CNTR1_FIELDS[] = +{ + { /* name */ SDS_CH3_TX_GOOD_OCTETS_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ SDS_CH3_TX_GOOD_OCTETS_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t SDS_CH3_TX_MIB_CNTR2_FIELDS[] = +{ + { /* name */ SDS_CH3_TX_GOOD_PKTS_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ SDS_CH3_TX_GOOD_PKTS_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t SDS_CH3_TX_MIB_CNTR3_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ SDS_CH3_TX_CRC_ERRORSf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t DMY_REG0_MIB_DATA_FIELDS[] = +{ + { /* name */ DUMMYf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t DMY_REG1_MIB_DATA_FIELDS[] = +{ + { /* name */ DUMMYf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t DMY_REG2_MIB_DATA_FIELDS[] = +{ + { /* name */ DUMMYf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t DMY_REG3_MIB_DATA_FIELDS[] = +{ + { /* name */ DUMMYf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +/* Module: MAC Control */ +rtk_regField_t MAC_L2_PORT_TX_MAX_LEN_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 28, + /* len */ 4 + }, + { /* name */ MAX_LEN_TX_1G_2P5G_5G_10G_SELf, + /* lsp */ 14, + /* len */ 14 + }, + { /* name */ MAX_LEN_TX_100M_10M_SELf, + /* lsp */ 0, + /* len */ 14 + }, +}; + +rtk_regField_t SMI_BYPASS_ABLTY_LOCK_CTRL_FIELDS[] = +{ + { /* name */ BYPASS_ABLTY_LOCKf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t LINK_DOWN_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 27, + /* len */ 5 + }, + { /* name */ LINK_DOWN_TIME_EN2f, + /* lsp */ 26, + /* len */ 1 + }, + { /* name */ LINK_DOWN_TIME2f, + /* lsp */ 18, + /* len */ 8 + }, + { /* name */ LINK_DOWN_TIME_EN1f, + /* lsp */ 17, + /* len */ 1 + }, + { /* name */ LINK_DOWN_TIME1f, + /* lsp */ 9, + /* len */ 8 + }, + { /* name */ LINK_DOWN_TIME_EN0f, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ LINK_DOWN_TIME0f, + /* lsp */ 0, + /* len */ 8 + }, +}; + +rtk_regField_t MAC_GLB_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 14, + /* len */ 18 + }, + { /* name */ MAC_48PASS1_DROP_ENf, + /* lsp */ 13, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 11, + /* len */ 1 + }, + { /* name */ DEFER_PKT_CONT_SELf, + /* lsp */ 10, + /* len */ 1 + }, + { /* name */ MAX_RETX_SELf, + /* lsp */ 9, + /* len */ 1 + }, + { /* name */ LATE_COLI_DROP_ENf, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ IOL_MAX_RETRY_ENf, + /* lsp */ 7, + /* len */ 1 + }, + { /* name */ BKOFF_SPDUPf, + /* lsp */ 6, + /* len */ 1 + }, + { /* name */ BKOFF_SELf, + /* lsp */ 4, + /* len */ 2 + }, + { /* name */ HALF_48PASS1_ENf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ BKPRES_MTHD_SELf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ DEFER_IPG_SELf, + /* lsp */ 0, + /* len */ 2 + }, +}; + +rtk_regField_t MAC_PORT_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 7, + /* len */ 25 + }, + { /* name */ ORIGINAL_CRSf, + /* lsp */ 6, + /* len */ 1 + }, + { /* name */ ORIGINAL_COLf, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ PRECOLLAT_SELf, + /* lsp */ 3, + /* len */ 2 + }, + { /* name */ LATE_COLI_THRf, + /* lsp */ 1, + /* len */ 2 + }, + { /* name */ BKPRES_ENf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t HALF_CHG_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 14, + /* len */ 18 + }, + { /* name */ HALF_TO_FULL_PAUSEf, + /* lsp */ 13, + /* len */ 1 + }, + { /* name */ REF_RX_CONGESTf, + /* lsp */ 12, + /* len */ 1 + }, + { /* name */ CHG_DUP_THRf, + /* lsp */ 7, + /* len */ 5 + }, + { /* name */ FULL_DET_ENf, + /* lsp */ 6, + /* len */ 1 + }, + { /* name */ MAC_CHG_DUPf, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ COL_CUR_CNTf, + /* lsp */ 0, + /* len */ 5 + }, +}; + +rtk_regField_t SMI_GLB_CTRL2_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 3, + /* len */ 29 + }, + { /* name */ PHY_FORCE_PAUSE_ABLTY_SELf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ PHY_FORCE_TX_PAUSE_ABLTYf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ PHY_FORCE_RX_PAUSE_ABLTYf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t SMI_GLB_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 22, + /* len */ 10 + }, + { /* name */ SMI_GLB_RSTf, + /* lsp */ 21, + /* len */ 1 + }, + { /* name */ SMI_POLLING_MASKf, + /* lsp */ 12, + /* len */ 9 + }, + { /* name */ SMI2_FREQ_SELf, + /* lsp */ 10, + /* len */ 2 + }, + { /* name */ SMI1_FREQ_SELf, + /* lsp */ 8, + /* len */ 2 + }, + { /* name */ SMI0_FREQ_SELf, + /* lsp */ 6, + /* len */ 2 + }, + { /* name */ SMI2_PREAMBLE_SELf, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ SMI1_PREAMBLE_SELf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ SMI0_PREAMBLE_SELf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ SMI2_BROADCAST_SET_ENf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ SMI1_BROADCAST_SET_ENf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ SMI0_BROADCAST_SET_ENf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t SMI_MAC_TYPE_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 18, + /* len */ 14 + }, + { /* name */ MAC_PORT8_TYPEf, + /* lsp */ 16, + /* len */ 2 + }, + { /* name */ MAC_PORT7_TYPEf, + /* lsp */ 14, + /* len */ 2 + }, + { /* name */ MAC_PORT6_TYPEf, + /* lsp */ 12, + /* len */ 2 + }, + { /* name */ MAC_PORT5_TYPEf, + /* lsp */ 10, + /* len */ 2 + }, + { /* name */ MAC_PORT4_TYPEf, + /* lsp */ 8, + /* len */ 2 + }, + { /* name */ MAC_PORT3_TYPEf, + /* lsp */ 6, + /* len */ 2 + }, + { /* name */ MAC_PORT2_TYPEf, + /* lsp */ 4, + /* len */ 2 + }, + { /* name */ MAC_PORT1_TYPEf, + /* lsp */ 2, + /* len */ 2 + }, + { /* name */ MAC_PORT0_TYPEf, + /* lsp */ 0, + /* len */ 2 + }, +}; + +rtk_regField_t SMI_PORT_POLLING_SEL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 9, + /* len */ 23 + }, + { /* name */ SMI_POLLING_SEL8f, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ SMI_POLLING_SEL7f, + /* lsp */ 7, + /* len */ 1 + }, + { /* name */ SMI_POLLING_SEL6f, + /* lsp */ 6, + /* len */ 1 + }, + { /* name */ SMI_POLLING_SEL5f, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ SMI_POLLING_SEL4f, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ SMI_POLLING_SEL3f, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ SMI_POLLING_SEL2f, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ SMI_POLLING_SEL1f, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ SMI_POLLING_SEL0f, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t SMI_MDIO_FREE_CNT_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 13, + /* len */ 19 + }, + { /* name */ MDIO_FREE_CNT_SELf, + /* lsp */ 1, + /* len */ 12 + }, + { /* name */ MDIO_FREE_CNT_ENf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t SMI_PRVTE_POLLING_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 18, + /* len */ 14 + }, + { /* name */ SMI_PRVTE1_POLLING8_0f, + /* lsp */ 9, + /* len */ 9 + }, + { /* name */ SMI_PRVTE_POLLING8_0f, + /* lsp */ 0, + /* len */ 9 + }, +}; + +rtk_regField_t SMI_10GPHY_POLLING_SEL_0_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 21, + /* len */ 11 + }, + { /* name */ INTDEV0_POLLING_10GPHYf, + /* lsp */ 16, + /* len */ 5 + }, + { /* name */ INTREG0_POLLING_10GPHYf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MAC_FORCE_MODE_CTRL0_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 20 + }, + { /* name */ FORCE_BYP_LINKf, + /* lsp */ 11, + /* len */ 1 + }, + { /* name */ MEDIA_SELf, + /* lsp */ 10, + /* len */ 1 + }, + { /* name */ SMI_FORCE_FC_ENf, + /* lsp */ 9, + /* len */ 1 + }, + { /* name */ RX_PAUSE_ENf, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ TX_PAUSE_ENf, + /* lsp */ 7, + /* len */ 1 + }, + { /* name */ SPD_SELf, + /* lsp */ 3, + /* len */ 4 + }, + { /* name */ DUP_SELf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ FORCE_LINK_ENf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ MAC_FORCE_ENf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t MAC_FORCE_MODE_CTRL1_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 9, + /* len */ 23 + }, + { /* name */ EEE_10G_ENf, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ EEE_10GLITE_ENf, + /* lsp */ 7, + /* len */ 1 + }, + { /* name */ EEE_5G_ENf, + /* lsp */ 6, + /* len */ 1 + }, + { /* name */ EEE_5GLITE_ENf, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ EEE_2P5G_ENf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ EEE_2P5GLITE_ENf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ EEE_GIGA_ENf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ EEE_500M_ENf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ EEE_100M_ENf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t SMI_REG_CHK1_CTRL1_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 23, + /* len */ 9 + }, + { /* name */ CHK1_MODE_10Gf, + /* lsp */ 21, + /* len */ 2 + }, + { /* name */ CHECK1_MMD_REGf, + /* lsp */ 5, + /* len */ 16 + }, + { /* name */ CHECK1_MMD_DEVADf, + /* lsp */ 0, + /* len */ 5 + }, +}; + +rtk_regField_t SMI_REG_CHK1_PMSK_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 9, + /* len */ 23 + }, + { /* name */ CHK1_PMSKf, + /* lsp */ 0, + /* len */ 9 + }, +}; + +rtk_regField_t SMI_REG_CHK1_DATA_10G_FIELDS[] = +{ + { /* name */ CHK1_DMSK_10Gf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ CHK1_DATA_10Gf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t SMI_REG_CHK1_RESULT_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 9, + /* len */ 23 + }, + { /* name */ CHK1_RESULTf, + /* lsp */ 0, + /* len */ 9 + }, +}; + +rtk_regField_t SMI_REG_CHK2_CTRL1_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 23, + /* len */ 9 + }, + { /* name */ CHK2_MODE_10Gf, + /* lsp */ 21, + /* len */ 2 + }, + { /* name */ CHECK2_MMD_REGf, + /* lsp */ 5, + /* len */ 16 + }, + { /* name */ CHECK2_MMD_DEVADf, + /* lsp */ 0, + /* len */ 5 + }, +}; + +rtk_regField_t SMI_REG_CHK2_PMSK_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 9, + /* len */ 23 + }, + { /* name */ CHK2_PMSKf, + /* lsp */ 0, + /* len */ 9 + }, +}; + +rtk_regField_t SMI_REG_CHK2_DATA_10G_FIELDS[] = +{ + { /* name */ CHK2_DMSK_10Gf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ CHK2_DATA_10Gf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t SMI_REG_CHK2_RESULT_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 9, + /* len */ 23 + }, + { /* name */ CHK2_RESULTf, + /* lsp */ 0, + /* len */ 9 + }, +}; + +rtk_regField_t SMI_REG_CHK3_CTRL1_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 23, + /* len */ 9 + }, + { /* name */ CHK3_MODE_10Gf, + /* lsp */ 21, + /* len */ 2 + }, + { /* name */ CHECK3_MMD_REGf, + /* lsp */ 5, + /* len */ 16 + }, + { /* name */ CHECK3_MMD_DEVADf, + /* lsp */ 0, + /* len */ 5 + }, +}; + +rtk_regField_t SMI_REG_CHK3_PMSK_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 9, + /* len */ 23 + }, + { /* name */ CHK3_PMSKf, + /* lsp */ 0, + /* len */ 9 + }, +}; + +rtk_regField_t SMI_REG_CHK3_DATA_10G_FIELDS[] = +{ + { /* name */ CHK3_DMSK_10Gf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ CHK3_DATA_10Gf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t SMI_REG_CHK3_RESULT_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 9, + /* len */ 23 + }, + { /* name */ CHK3_RESULTf, + /* lsp */ 0, + /* len */ 9 + }, +}; + +rtk_regField_t SMI_REG_CHK4_CTRL1_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 23, + /* len */ 9 + }, + { /* name */ CHK4_MODE_10Gf, + /* lsp */ 21, + /* len */ 2 + }, + { /* name */ CHECK4_MMD_REGf, + /* lsp */ 5, + /* len */ 16 + }, + { /* name */ CHECK4_MMD_DEVADf, + /* lsp */ 0, + /* len */ 5 + }, +}; + +rtk_regField_t SMI_REG_CHK4_PMSK_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 9, + /* len */ 23 + }, + { /* name */ CHK4_PMSKf, + /* lsp */ 0, + /* len */ 9 + }, +}; + +rtk_regField_t SMI_REG_CHK4_DATA_10G_FIELDS[] = +{ + { /* name */ CHK4_DMSK_10Gf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ CHK4_DATA_10Gf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t SMI_REG_CHK4_RESULT_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 9, + /* len */ 23 + }, + { /* name */ CHK4_RESULTf, + /* lsp */ 0, + /* len */ 9 + }, +}; + +rtk_regField_t SMI_REG_CHK5_CTRL1_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 23, + /* len */ 9 + }, + { /* name */ CHK5_MODE_10Gf, + /* lsp */ 21, + /* len */ 2 + }, + { /* name */ CHECK5_MMD_REGf, + /* lsp */ 5, + /* len */ 16 + }, + { /* name */ CHECK5_MMD_DEVADf, + /* lsp */ 0, + /* len */ 5 + }, +}; + +rtk_regField_t SMI_REG_CHK5_PMSK_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 9, + /* len */ 23 + }, + { /* name */ CHK5_PMSKf, + /* lsp */ 0, + /* len */ 9 + }, +}; + +rtk_regField_t SMI_REG_CHK5_DATA_10G_FIELDS[] = +{ + { /* name */ CHK5_DMSK_10Gf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ CHK5_DATA_10Gf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t SMI_REG_CHK5_RESULT_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 9, + /* len */ 23 + }, + { /* name */ CHK5_RESULTf, + /* lsp */ 0, + /* len */ 9 + }, +}; + +rtk_regField_t LINK_DELAY_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 25, + /* len */ 7 + }, + { /* name */ TX_IDLE_TMRf, + /* lsp */ 17, + /* len */ 8 + }, + { /* name */ DOWN2UP_DLY_ENf, + /* lsp */ 8, + /* len */ 9 + }, + { /* name */ LNKDN_FRC_DISf, + /* lsp */ 7, + /* len */ 1 + }, + { /* name */ LINKUP_DELAY_10G_5Gf, + /* lsp */ 5, + /* len */ 2 + }, + { /* name */ LINKUP_DELAY_2P5G_1000M_100Mf, + /* lsp */ 3, + /* len */ 2 + }, + { /* name */ LINKUP_DELAY_10Mf, + /* lsp */ 0, + /* len */ 3 + }, +}; + +rtk_regField_t MAC_LINK_STS_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 26, + /* len */ 6 + }, + { /* name */ MAC_LINK_STS_9_0f, + /* lsp */ 16, + /* len */ 10 + }, + { /* name */ RESERVEDf, + /* lsp */ 10, + /* len */ 6 + }, + { /* name */ LINK_STS_9_0f, + /* lsp */ 0, + /* len */ 10 + }, +}; + +rtk_regField_t MAC_LINK_MEDIA_STS_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 10, + /* len */ 22 + }, + { /* name */ MEDIA_STS_9_0f, + /* lsp */ 0, + /* len */ 10 + }, +}; + +rtk_regField_t MAC_LINK_SPD_STS_FIELDS[] = +{ + { /* name */ SPD_STS_9_0f, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t MAC_LINK_DUP_STS_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 10, + /* len */ 22 + }, + { /* name */ DUP_STS_9_0f, + /* lsp */ 0, + /* len */ 10 + }, +}; + +rtk_regField_t MAC_TX_PAUSE_STS_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 10, + /* len */ 22 + }, + { /* name */ TX_PAUSE_STS_9_0f, + /* lsp */ 0, + /* len */ 10 + }, +}; + +rtk_regField_t MAC_RX_PAUSE_STS_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 10, + /* len */ 22 + }, + { /* name */ RX_PAUSE_STS_9_0f, + /* lsp */ 0, + /* len */ 10 + }, +}; + +rtk_regField_t MAC_EEE_ABLTY_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 10, + /* len */ 22 + }, + { /* name */ EEE_ABLTY_9_0f, + /* lsp */ 0, + /* len */ 10 + }, +}; + +rtk_regField_t MAC_MSTR_SLV_STS_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 9, + /* len */ 23 + }, + { /* name */ MSTR_SLV_STS_8_0f, + /* lsp */ 0, + /* len */ 9 + }, +}; + +rtk_regField_t MAC_MSTR_SLV_FAULT_STS_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 9, + /* len */ 23 + }, + { /* name */ MSTR_SLV_FAULT_STS_8_0f, + /* lsp */ 0, + /* len */ 9 + }, +}; + +rtk_regField_t PHY_LINK_STS_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 9, + /* len */ 23 + }, + { /* name */ LINK_STS_8_0f, + /* lsp */ 0, + /* len */ 9 + }, +}; + +rtk_regField_t PHY_LINK_MEDIA_STS_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 9, + /* len */ 23 + }, + { /* name */ MEDIA_STS_8_0f, + /* lsp */ 0, + /* len */ 9 + }, +}; + +rtk_regField_t PHY_LINK_SPD_STS_FIELDS[] = +{ + { /* name */ SPD_STS_8_0f, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t PHY_LINK_DUP_STS_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 9, + /* len */ 23 + }, + { /* name */ DUP_STS_8_0f, + /* lsp */ 0, + /* len */ 9 + }, +}; + +rtk_regField_t PHY_TX_PAUSE_STS_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 9, + /* len */ 23 + }, + { /* name */ TX_PAUSE_STS_8_0f, + /* lsp */ 0, + /* len */ 9 + }, +}; + +rtk_regField_t PHY_RX_PAUSE_STS_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 9, + /* len */ 23 + }, + { /* name */ RX_PAUSE_STS_8_0f, + /* lsp */ 0, + /* len */ 9 + }, +}; + +rtk_regField_t PHY_EEE_ABLTY_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 9, + /* len */ 23 + }, + { /* name */ EEE_ABLTY_8_0f, + /* lsp */ 0, + /* len */ 9 + }, +}; + +rtk_regField_t PHY_MSTR_SLV_STS_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 9, + /* len */ 23 + }, + { /* name */ MSTR_SLV_STS_8_0f, + /* lsp */ 0, + /* len */ 9 + }, +}; + +rtk_regField_t PHY_MSTR_SLV_FAULT_STS_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 9, + /* len */ 23 + }, + { /* name */ MSTR_SLV_FAULT_STS_8_0f, + /* lsp */ 0, + /* len */ 9 + }, +}; + +rtk_regField_t SMI_ACCESS_PHY_CTRL_0_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 10, + /* len */ 22 + }, + { /* name */ PHY_BRDCASTf, + /* lsp */ 9, + /* len */ 1 + }, + { /* name */ PHY_MASKf, + /* lsp */ 0, + /* len */ 9 + }, +}; + +rtk_regField_t SMI_ACCESS_PHY_CTRL_1_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 27, + /* len */ 5 + }, + { /* name */ FAILf, + /* lsp */ 24, + /* len */ 3 + }, + { /* name */ MMD_DEVAD_4_0f, + /* lsp */ 19, + /* len */ 5 + }, + { /* name */ MMD_REG_15_0f, + /* lsp */ 3, + /* len */ 16 + }, + { /* name */ RWOPf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ TYPEf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ CMDf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t SMI_ACCESS_PHY_CTRL_2_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ DATA_15_0f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t SMI_ACCESS_PHY_CTRL_3_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ INDATA_15_0f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t SMI_ACCESS_PHY_CTRL_4_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 22, + /* len */ 10 + }, + { /* name */ REG_ADDR_4_0f, + /* lsp */ 17, + /* len */ 5 + }, + { /* name */ PARK_PAGE_4_0f, + /* lsp */ 12, + /* len */ 5 + }, + { /* name */ MAIN_PAGE_11_0f, + /* lsp */ 0, + /* len */ 12 + }, +}; + +rtk_regField_t SMI_PORT0_5_ADDR_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 30, + /* len */ 2 + }, + { /* name */ PORT5_ADDRf, + /* lsp */ 25, + /* len */ 5 + }, + { /* name */ PORT4_ADDRf, + /* lsp */ 20, + /* len */ 5 + }, + { /* name */ PORT3_ADDRf, + /* lsp */ 15, + /* len */ 5 + }, + { /* name */ PORT2_ADDRf, + /* lsp */ 10, + /* len */ 5 + }, + { /* name */ PORT1_ADDRf, + /* lsp */ 5, + /* len */ 5 + }, + { /* name */ PORT0_ADDRf, + /* lsp */ 0, + /* len */ 5 + }, +}; + +rtk_regField_t SMI_PORT6_9_ADDR_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 15, + /* len */ 17 + }, + { /* name */ PORT8_ADDRf, + /* lsp */ 10, + /* len */ 5 + }, + { /* name */ PORT7_ADDRf, + /* lsp */ 5, + /* len */ 5 + }, + { /* name */ PORT6_ADDRf, + /* lsp */ 0, + /* len */ 5 + }, +}; + +rtk_regField_t SMI_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 15, + /* len */ 17 + }, + { /* name */ SMI2_MDC_ENf, + /* lsp */ 14, + /* len */ 1 + }, + { /* name */ SMI1_MDC_ENf, + /* lsp */ 13, + /* len */ 1 + }, + { /* name */ SMI0_MDC_ENf, + /* lsp */ 12, + /* len */ 1 + }, + { /* name */ SMI2_DLY_CFGf, + /* lsp */ 8, + /* len */ 4 + }, + { /* name */ SMI1_DLY_CFGf, + /* lsp */ 4, + /* len */ 4 + }, + { /* name */ SMI0_DLY_CFGf, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t RLFD_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 11, + /* len */ 21 + }, + { /* name */ RLFD_SELf, + /* lsp */ 10, + /* len */ 1 + }, + { /* name */ RLFD_ENf, + /* lsp */ 9, + /* len */ 1 + }, + { /* name */ RLFD_STSf, + /* lsp */ 0, + /* len */ 9 + }, +}; + +rtk_regField_t RLFD_10G_ADDR_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 25, + /* len */ 7 + }, + { /* name */ RLFD_DEV_2P5G_10GPHYf, + /* lsp */ 20, + /* len */ 5 + }, + { /* name */ RLFD_REG_2P5G_10GPHYf, + /* lsp */ 4, + /* len */ 16 + }, + { /* name */ RLFD_BIT_2P5G_10GPHYf, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t UNI_DIR_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 13, + /* len */ 19 + }, + { /* name */ UNIDIR_WIN_DLYf, + /* lsp */ 11, + /* len */ 2 + }, + { /* name */ FIB_UNIDIR_ONLY_CPUTX_ENf, + /* lsp */ 10, + /* len */ 1 + }, + { /* name */ FIB_UNIDIR_ENf, + /* lsp */ 0, + /* len */ 10 + }, +}; + +rtk_regField_t SMI_10GPHY_POLLING_SEL_1_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 21, + /* len */ 11 + }, + { /* name */ INTDEV1_POLLING_10GPHYf, + /* lsp */ 16, + /* len */ 5 + }, + { /* name */ INTREG1_POLLING_10GPHYf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t SMI_10GPHY_POLLING_REG0_CFG_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 25, + /* len */ 7 + }, + { /* name */ REG0_BIT_2P5G_10GPHYf, + /* lsp */ 21, + /* len */ 4 + }, + { /* name */ REG0_DEV_2P5G_10GPHYf, + /* lsp */ 16, + /* len */ 5 + }, + { /* name */ REG0_REG_2P5G_10GPHYf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t SMI_10GPHY_POLLING_REG9_CFG_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 25, + /* len */ 7 + }, + { /* name */ REG9_BIT_2P5G_10GPHYf, + /* lsp */ 21, + /* len */ 4 + }, + { /* name */ REG9_DEV_2P5G_10GPHYf, + /* lsp */ 16, + /* len */ 5 + }, + { /* name */ REG9_REG_2P5G_10GPHYf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t SMI_10GPHY_POLLING_REG10_CFG_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 25, + /* len */ 7 + }, + { /* name */ REG10_BIT_2P5G_10GPHYf, + /* lsp */ 21, + /* len */ 4 + }, + { /* name */ REG10_DEV_2P5G_10GPHYf, + /* lsp */ 16, + /* len */ 5 + }, + { /* name */ REG10_REG_2P5G_10GPHYf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MAC_CTRL_1_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 24, + /* len */ 8 + }, + { /* name */ MAC_SPD_ABLTY2f, + /* lsp */ 16, + /* len */ 8 + }, + { /* name */ MAC_SPD_ABLTY1f, + /* lsp */ 8, + /* len */ 8 + }, + { /* name */ MAC_SPD_ABLTY0f, + /* lsp */ 0, + /* len */ 8 + }, +}; + +rtk_regField_t MAC_CTRL_2_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 10, + /* len */ 22 + }, + { /* name */ MAC_SPD_ABLTY_BYPf, + /* lsp */ 0, + /* len */ 10 + }, +}; + +rtk_regField_t MAC8_RTL8226B_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 10, + /* len */ 22 + }, + { /* name */ MAC3_SDS0_MODEf, + /* lsp */ 5, + /* len */ 5 + }, + { /* name */ MAC8_SDS1_MODEf, + /* lsp */ 0, + /* len */ 5 + }, +}; + +rtk_regField_t TX_RX_IDLE_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 27, + /* len */ 5 + }, + { /* name */ WAIT_FOR_TX_IDLEf, + /* lsp */ 18, + /* len */ 9 + }, + { /* name */ WAIT_FOR_RX_IDLEf, + /* lsp */ 9, + /* len */ 9 + }, + { /* name */ REF_RX_IDLEf, + /* lsp */ 0, + /* len */ 9 + }, +}; + +rtk_regField_t IDLE_DLY_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TX_IDLE_TIMERf, + /* lsp */ 8, + /* len */ 8 + }, + { /* name */ RX_IDLE_TIMERf, + /* lsp */ 0, + /* len */ 8 + }, +}; + +rtk_regField_t MAC_IPG_COMPS_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 3, + /* len */ 29 + }, + { /* name */ IPG_COMPS_ENf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ IPG_COMPS_SELf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ IPG_4N_BYTE_COMPS_ENf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t MAC_L2_GLOBAL_CTRL0_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 22, + /* len */ 10 + }, + { /* name */ FWD_PAUSE_ENf, + /* lsp */ 21, + /* len */ 1 + }, + { /* name */ FWD_INVLD_MAC_CTRL_ENf, + /* lsp */ 20, + /* len */ 1 + }, + { /* name */ FWD_UNKN_OPCODE_ENf, + /* lsp */ 19, + /* len */ 1 + }, + { /* name */ LIMIT_PAUSE_ENf, + /* lsp */ 17, + /* len */ 2 + }, + { /* name */ CRC_CPU_RC_ENf, + /* lsp */ 15, + /* len */ 2 + }, + { /* name */ FWD_PFC_ENf, + /* lsp */ 14, + /* len */ 1 + }, + { /* name */ LIMIT_PFC_ENf, + /* lsp */ 12, + /* len */ 2 + }, + { /* name */ IOL_LEN_ERR_ENf, + /* lsp */ 11, + /* len */ 1 + }, + { /* name */ IOL_MAX_LEN_ENf, + /* lsp */ 10, + /* len */ 1 + }, + { /* name */ LIMIT_IPG_CFG_1G_2P5Gf, + /* lsp */ 5, + /* len */ 5 + }, + { /* name */ LIMIT_IPG_CFG_10M_100Mf, + /* lsp */ 0, + /* len */ 5 + }, +}; + +rtk_regField_t MAC_L2_GLOBAL_CTRL1_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ LINKINTRP_TX_EN_8_0f, + /* lsp */ 7, + /* len */ 9 + }, + { /* name */ CFG_RX_RXDV_CNTf, + /* lsp */ 0, + /* len */ 7 + }, +}; + +rtk_regField_t MAC_L2_PORT_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 20 + }, + { /* name */ PER_PORT_RSTBf, + /* lsp */ 11, + /* len */ 1 + }, + { /* name */ PER_PORT_RX_RSTBf, + /* lsp */ 10, + /* len */ 1 + }, + { /* name */ PER_PORT_TX_RSTBf, + /* lsp */ 9, + /* len */ 1 + }, + { /* name */ CLOCK_SWITCHf, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ CFG_PORT_L_LPBKf, + /* lsp */ 7, + /* len */ 1 + }, + { /* name */ ALWAYS_TX_CRC_RC_ENf, + /* lsp */ 6, + /* len */ 1 + }, + { /* name */ PADDING_UND_SIZE_ENf, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ RX_CHK_CRC_ENf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ PASS_ALL_MODE_ENf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ BYP_TX_CRCf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ TX_ENf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ RX_ENf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t MAC_MACSEC_IPG_CFG_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 9, + /* len */ 23 + }, + { /* name */ MACSEC_IPG_LENGTHf, + /* lsp */ 2, + /* len */ 7 + }, + { /* name */ MACSEC_IPG_MODEf, + /* lsp */ 0, + /* len */ 2 + }, +}; + +rtk_regField_t MAC_MACSEC_ETH_1_0_FIELDS[] = +{ + { /* name */ MACSEC_ETH_1f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ MACSEC_ETH_0f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MAC_MACSEC_ETH_3_2_FIELDS[] = +{ + { /* name */ MACSEC_ETH_3f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ MACSEC_ETH_2f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MAC_MACSEC_ETH_5_4_FIELDS[] = +{ + { /* name */ MACSEC_ETH_5f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ MACSEC_ETH_4f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MAC_MACSEC_ETH_7_6_FIELDS[] = +{ + { /* name */ MACSEC_ETH_7f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ MACSEC_ETH_6f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MAC_L2_PADDING_SEL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 8, + /* len */ 24 + }, + { /* name */ PADDING_SELf, + /* lsp */ 0, + /* len */ 8 + }, +}; + +rtk_regField_t MAC_L2_ADDR_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 48, + /* len */ 16 + }, + { /* name */ SW_MAC_ADDR_47_32f, + /* lsp */ 32, + /* len */ 16 + }, + { /* name */ SW_MAC_ADDR_31_0f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t MAC_L2_PORT_MAX_LEN_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 29, + /* len */ 3 + }, + { /* name */ MAX_LEN_TAG_INCf, + /* lsp */ 28, + /* len */ 1 + }, + { /* name */ MAX_LEN_1G_2P5G_5G_10G_SELf, + /* lsp */ 14, + /* len */ 14 + }, + { /* name */ MAX_LEN_100M_10M_SELf, + /* lsp */ 0, + /* len */ 14 + }, +}; + +rtk_regField_t MAC_L2_TGPORT_PRMB_DBG0_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 31, + /* len */ 1 + }, + { /* name */ CFG_PRMB_6BYTE_MODEf, + /* lsp */ 30, + /* len */ 1 + }, + { /* name */ CFG_PRMB_RCVY_ENf, + /* lsp */ 29, + /* len */ 1 + }, + { /* name */ CFG_PN_FRAG_FLTf, + /* lsp */ 28, + /* len */ 1 + }, + { /* name */ CFG_PN_CUR_PRMBf, + /* lsp */ 24, + /* len */ 4 + }, + { /* name */ CFG_PN_MAX_PRMBf, + /* lsp */ 20, + /* len */ 4 + }, + { /* name */ CFG_PN_MIN_PRMBf, + /* lsp */ 16, + /* len */ 4 + }, + { /* name */ CFG_PN_DBG_INFO_OFFf, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ CFG_PN_CUR_IPGf, + /* lsp */ 10, + /* len */ 5 + }, + { /* name */ CFG_PN_MAX_IPGf, + /* lsp */ 5, + /* len */ 5 + }, + { /* name */ CFG_PN_MIN_IPGf, + /* lsp */ 0, + /* len */ 5 + }, +}; + +rtk_regField_t MAC_L2_TGPORT_PRMB_DBG1_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 15, + /* len */ 17 + }, + { /* name */ TG_SFD_FB_DIS_TXf, + /* lsp */ 14, + /* len */ 1 + }, + { /* name */ TG_SFD_FB_DIS_RXf, + /* lsp */ 13, + /* len */ 1 + }, + { /* name */ PRMB_RCVY_OVTHR_MONf, + /* lsp */ 12, + /* len */ 1 + }, + { /* name */ CFG_PN_CUR_THRf, + /* lsp */ 6, + /* len */ 6 + }, + { /* name */ CFG_PN_MAX_THRf, + /* lsp */ 0, + /* len */ 6 + }, +}; + +rtk_regField_t PHY_CFG_8224_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 6, + /* len */ 26 + }, + { /* name */ SMI_DGL_EN_8224f, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ BASE_PHY_ADDR_8224f, + /* lsp */ 0, + /* len */ 5 + }, +}; + +rtk_regField_t MDX_CTRL_8224_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 9, + /* len */ 23 + }, + { /* name */ SLV_CLK_EDGE_SELf, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ CFG_PRMB_SUPP_8224f, + /* lsp */ 7, + /* len */ 1 + }, + { /* name */ CFG_TA_CHK_EN_8224f, + /* lsp */ 6, + /* len */ 1 + }, + { /* name */ CFG_MULTI_GPHY_MDIO_DLY_8224f, + /* lsp */ 4, + /* len */ 2 + }, + { /* name */ CFG_TOP_MDIO_DLY_8224f, + /* lsp */ 2, + /* len */ 2 + }, + { /* name */ CFG_MULTI_GPHY_MDC_DEGLITCH_EN_8224f, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ CFG_TOP_MDC_DEGLITCH_EN_8224f, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t INT_PHY_OCP_INDR_ACC_CTRL_0_FIELDS[] = +{ + { /* name */ INT_PHY_OCP_INDACC_ADDRf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RESERVEDf, + /* lsp */ 9, + /* len */ 7 + }, + { /* name */ INT_PHY_OCP_INDACC_PHYADRf, + /* lsp */ 4, + /* len */ 5 + }, + { /* name */ RESERVEDf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ INT_PHY_OCP_INDACC_FAILf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ INT_PHY_OCP_INDACC_RWf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ INT_PHY_OCP_INDACC_CMDf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t INT_PHY_OCP_INDR_ACC_CTRL_1_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ INT_PHY_OCP_INDACC_RDDATAf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t INT_PHY_OCP_INDR_ACC_CTRL_2_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ INT_PHY_OCP_INDACC_WRDATAf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MAC_PFC_FORCE_FC_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 6, + /* len */ 26 + }, + { /* name */ MAC3_PFC_FRC_FC_ENf, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ MAC3_PFC_FRC_FC_RXf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ MAC3_PFC_FRC_FC_TXf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ MAC8_PFC_FRC_FC_ENf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ MAC8_PFC_FRC_FC_RXf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ MAC8_PFC_FRC_FC_TXf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t MAC_TXFIFO_FULTH_CTRL_0_FIELDS[] = +{ + { /* name */ MAC0_TXFIFO_THR_CTRLf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ MAC1_TXFIFO_THR_CTRLf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MAC_TXFIFO_FULTH_CTRL_1_FIELDS[] = +{ + { /* name */ MAC2_TXFIFO_THR_CTRLf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ MAC3_TXFIFO_THR_CTRL_1Gf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MAC_TXFIFO_FULTH_CTRL_2_FIELDS[] = +{ + { /* name */ MAC3_TXFIFO_THR_CTRL_TGf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ MAC4_TXFIFO_THR_CTRLf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MAC_TXFIFO_FULTH_CTRL_3_FIELDS[] = +{ + { /* name */ MAC5_TXFIFO_THR_CTRLf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ MAC6_TXFIFO_THR_CTRLf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MAC_TXFIFO_FULTH_CTRL_4_FIELDS[] = +{ + { /* name */ MAC7_TXFIFO_THR_CTRLf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ MAC8_TXFIFO_THR_CTRL_TGf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MAC_TXFIFO_FULTH_CTRL_5_FIELDS[] = +{ + { /* name */ MAC8_TXFIFO_THR_CTRL_1Gf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ MAC9_TXFIFO_THR_CTRLf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_REG_GLB_SET1_PORT4_FIELDS[] = +{ + { /* name */ RX_GATINGf, + /* lsp */ 31, + /* len */ 1 + }, + { /* name */ TX_GATINGf, + /* lsp */ 30, + /* len */ 1 + }, + { /* name */ DBG_ENf, + /* lsp */ 29, + /* len */ 1 + }, + { /* name */ DBG_SELf, + /* lsp */ 24, + /* len */ 5 + }, + { /* name */ DBG_SPD_SELf, + /* lsp */ 23, + /* len */ 1 + }, + { /* name */ RX_G_IOSAMEPMBf, + /* lsp */ 22, + /* len */ 1 + }, + { /* name */ TX_G_IOSAMEPMBf, + /* lsp */ 21, + /* len */ 1 + }, + { /* name */ MIBCNT_MODEf, + /* lsp */ 20, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 19, + /* len */ 1 + }, + { /* name */ RX_XGDIC_ENf, + /* lsp */ 18, + /* len */ 1 + }, + { /* name */ TX_XGDIC_ENf, + /* lsp */ 17, + /* len */ 1 + }, + { /* name */ MIBCNT_SWRST_Nf, + /* lsp */ 16, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ PTPBYPASS_ENf, + /* lsp */ 14, + /* len */ 1 + }, + { /* name */ SYSLPBK_ENf, + /* lsp */ 13, + /* len */ 1 + }, + { /* name */ PHY2MAC_ENf, + /* lsp */ 12, + /* len */ 1 + }, + { /* name */ RX_IPRST_Nf, + /* lsp */ 11, + /* len */ 1 + }, + { /* name */ RX_IPBYPASS_ENf, + /* lsp */ 10, + /* len */ 1 + }, + { /* name */ RX_MACSECBYPASS_ENf, + /* lsp */ 9, + /* len */ 1 + }, + { /* name */ RX_SWRST_ENf, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 6, + /* len */ 2 + }, + { /* name */ LINELPBK_ENf, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ MAC2PHY_ENf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ TX_IPRST_Nf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ TX_IPBYPASS_ENf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ TX_MACSECBYPASS_ENf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ TX_SWRST_ENf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t MACSEC_REG_GLB_IMR_PORT4_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 20 + }, + { /* name */ RX_IPILOCK_XG_IMRf, + /* lsp */ 11, + /* len */ 1 + }, + { /* name */ RX_IPILOCK_IMRf, + /* lsp */ 10, + /* len */ 1 + }, + { /* name */ RX_IPISECFAIL_IMRf, + /* lsp */ 9, + /* len */ 1 + }, + { /* name */ RX_IPI_GLB_IMRf, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 4 + }, + { /* name */ TX_IPELOCK_XG_IMRf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ TX_IPELOCK_IMRf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ TX_IPESECFAIL_IMRf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ TX_IPE_GLB_IMRf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t MACSEC_REG_GLB_ISR_PORT4_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 20 + }, + { /* name */ RX_IPILOCK_XG_ISRf, + /* lsp */ 11, + /* len */ 1 + }, + { /* name */ RX_IPILOCK_ISRf, + /* lsp */ 10, + /* len */ 1 + }, + { /* name */ RX_IPISECFAIL_ISRf, + /* lsp */ 9, + /* len */ 1 + }, + { /* name */ RX_IPI_GLB_ISRf, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 4 + }, + { /* name */ TX_IPELOCK_XG_ISRf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ TX_IPELOCK_ISRf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ TX_IPESECFAIL_ISRf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ TX_IPE_GLB_ISRf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t UNUSED_000C_PORT4_FIELDS[] = +{ + { /* name */ UNUSED_000C_PORT4f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t MACSEC_PM_CTRL_PORT4_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 2, + /* len */ 30 + }, + { /* name */ MACSEC_RX_ICG_ENf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ MACSEC_TX_ICG_ENf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t MACSEC_REG_GLB_MASK_PORT4_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 30, + /* len */ 2 + }, + { /* name */ RX_MTUf, + /* lsp */ 24, + /* len */ 6 + }, + { /* name */ RESERVEDf, + /* lsp */ 22, + /* len */ 2 + }, + { /* name */ TX_MTUf, + /* lsp */ 16, + /* len */ 6 + }, + { /* name */ RESERVEDf, + /* lsp */ 13, + /* len */ 3 + }, + { /* name */ RX_XGMASKf, + /* lsp */ 12, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 9, + /* len */ 3 + }, + { /* name */ RXDV_GMASKf, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 5, + /* len */ 3 + }, + { /* name */ TX_XGMASKf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 1, + /* len */ 3 + }, + { /* name */ TXEN_GMASKf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t MACSEC_REG_GLB_SET4_PORT4_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 31, + /* len */ 1 + }, + { /* name */ TXMSKDELAY_VALf, + /* lsp */ 16, + /* len */ 15 + }, + { /* name */ RESERVEDf, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ RXMSKDELAY_VALf, + /* lsp */ 0, + /* len */ 15 + }, +}; + +rtk_regField_t MACSEC_REG_IP_PROBE_PORT4_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ PROBE_SEL_AEf, + /* lsp */ 8, + /* len */ 8 + }, + { /* name */ PROBE_SEL_AIf, + /* lsp */ 0, + /* len */ 8 + }, +}; + +rtk_regField_t UNUSED_0020_PORT4_FIELDS[] = +{ + { /* name */ UNUSED_0020_PORT4f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0024_PORT4_FIELDS[] = +{ + { /* name */ UNUSED_0024_PORT4f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t MACSEC_MBIST_SA_CTRL_PORT4_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 30, + /* len */ 2 + }, + { /* name */ BIST_MODE_MACSEC_SA_AEf, + /* lsp */ 29, + /* len */ 1 + }, + { /* name */ DRF_BIST_MODE_MACSEC_SA_AEf, + /* lsp */ 28, + /* len */ 1 + }, + { /* name */ BIST_RSTN_MACSEC_SA_AEf, + /* lsp */ 27, + /* len */ 1 + }, + { /* name */ BIST_LOOP_MODE_MACSEC_SA_AEf, + /* lsp */ 26, + /* len */ 1 + }, + { /* name */ DYN_READ_EN_MACSEC_SA_AEf, + /* lsp */ 25, + /* len */ 1 + }, + { /* name */ DRF_TESS_RESUME_MACSEC_SA_AEf, + /* lsp */ 24, + /* len */ 1 + }, + { /* name */ BIST_MODE_MACSEC_SA_AIf, + /* lsp */ 23, + /* len */ 1 + }, + { /* name */ DRF_BIST_MODE_MACSEC_SA_AIf, + /* lsp */ 22, + /* len */ 1 + }, + { /* name */ BIST_RSTN_MACSEC_SA_AIf, + /* lsp */ 21, + /* len */ 1 + }, + { /* name */ BIST_LOOP_MODE_MACSEC_SA_AIf, + /* lsp */ 20, + /* len */ 1 + }, + { /* name */ DYN_READ_EN_MACSEC_SA_AIf, + /* lsp */ 19, + /* len */ 1 + }, + { /* name */ DRF_TESS_RESUME_MACSEC_SA_AIf, + /* lsp */ 18, + /* len */ 1 + }, + { /* name */ MACSEC_SA_AE_ICG_ENf, + /* lsp */ 17, + /* len */ 1 + }, + { /* name */ MACSEC_SA_AI_ICG_ENf, + /* lsp */ 16, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_MBIST_STAT_CTRL_PORT4_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 28, + /* len */ 4 + }, + { /* name */ DRF_START_PAUSE_MACSEC_SA_AEf, + /* lsp */ 27, + /* len */ 1 + }, + { /* name */ BIST_DONE_MACSEC_SA_AEf, + /* lsp */ 26, + /* len */ 1 + }, + { /* name */ DRF_BIST_DONE_MACSEC_SA_AEf, + /* lsp */ 25, + /* len */ 1 + }, + { /* name */ DRF_START_PAUSE_MACSEC_SA_AIf, + /* lsp */ 24, + /* len */ 1 + }, + { /* name */ BIST_DONE_MACSEC_SA_AIf, + /* lsp */ 23, + /* len */ 1 + }, + { /* name */ DRF_BIST_DONE_MACSEC_SA_AIf, + /* lsp */ 22, + /* len */ 1 + }, + { /* name */ DRF_START_PAUSE_MACSEC_STAT_AEf, + /* lsp */ 21, + /* len */ 1 + }, + { /* name */ BIST_DONE_MACSEC_STAT_AEf, + /* lsp */ 20, + /* len */ 1 + }, + { /* name */ DRF_BIST_DONE_MACSEC_STAT_AEf, + /* lsp */ 19, + /* len */ 1 + }, + { /* name */ DRF_START_PAUSE_MACSEC_STAT_AIf, + /* lsp */ 18, + /* len */ 1 + }, + { /* name */ BIST_DONE_MACSEC_STAT_AIf, + /* lsp */ 17, + /* len */ 1 + }, + { /* name */ DRF_BIST_DONE_MACSEC_STAT_AIf, + /* lsp */ 16, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 14, + /* len */ 2 + }, + { /* name */ BIST_MODE_MACSEC_STAT_AEf, + /* lsp */ 13, + /* len */ 1 + }, + { /* name */ DRF_BIST_MODE_MACSEC_STAT_AEf, + /* lsp */ 12, + /* len */ 1 + }, + { /* name */ BIST_RSTN_MACSEC_STAT_AEf, + /* lsp */ 11, + /* len */ 1 + }, + { /* name */ BIST_LOOP_MODE_MACSEC_STAT_AEf, + /* lsp */ 10, + /* len */ 1 + }, + { /* name */ DYN_READ_EN_MACSEC_STAT_AEf, + /* lsp */ 9, + /* len */ 1 + }, + { /* name */ DRF_TESS_RESUME_MACSEC_STAT_AEf, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ BIST_MODE_MACSEC_STAT_AIf, + /* lsp */ 7, + /* len */ 1 + }, + { /* name */ DRF_BIST_MODE_MACSEC_STAT_AIf, + /* lsp */ 6, + /* len */ 1 + }, + { /* name */ BIST_RSTN_MACSEC_STAT_AIf, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ BIST_LOOP_MODE_MACSEC_STAT_AIf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ DYN_READ_EN_MACSEC_STAT_AIf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ DRF_TESS_RESUME_MACSEC_STAT_AIf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ MACSEC_STAT_AE_ICG_ENf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ MACSEC_STAT_AI_ICG_ENf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t MACSEC_MBIST_SA_AE_TEST_PORT4_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 28, + /* len */ 4 + }, + { /* name */ MACSEC_SA_AI_DVSEf, + /* lsp */ 27, + /* len */ 1 + }, + { /* name */ MACSEC_SA_AI_DVSf, + /* lsp */ 23, + /* len */ 4 + }, + { /* name */ MACSEC_SA_AI_LSf, + /* lsp */ 22, + /* len */ 1 + }, + { /* name */ MACSEC_SA_AI_DSf, + /* lsp */ 21, + /* len */ 1 + }, + { /* name */ MACSEC_SA_AI_SDf, + /* lsp */ 20, + /* len */ 1 + }, + { /* name */ MACSEC_SA_AI3_TEST1f, + /* lsp */ 19, + /* len */ 1 + }, + { /* name */ MACSEC_SA_AI2_TEST1f, + /* lsp */ 18, + /* len */ 1 + }, + { /* name */ MACSEC_SA_AI1_TEST1f, + /* lsp */ 17, + /* len */ 1 + }, + { /* name */ MACSEC_SA_AI0_TEST1f, + /* lsp */ 16, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 4 + }, + { /* name */ MACSEC_SA_AE_DVSEf, + /* lsp */ 11, + /* len */ 1 + }, + { /* name */ MACSEC_SA_AE_DVSf, + /* lsp */ 7, + /* len */ 4 + }, + { /* name */ MACSEC_SA_AE_LSf, + /* lsp */ 6, + /* len */ 1 + }, + { /* name */ MACSEC_SA_AE_DSf, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ MACSEC_SA_AE_SDf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ MACSEC_SA_AE3_TEST1f, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ MACSEC_SA_AE2_TEST1f, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ MACSEC_SA_AE1_TEST1f, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ MACSEC_SA_AE0_TEST1f, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t MACSEC_MBIST_STAT_AE_TEST_PORT4_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 26, + /* len */ 6 + }, + { /* name */ MACSEC_STAT_AI_DVSEf, + /* lsp */ 25, + /* len */ 1 + }, + { /* name */ MACSEC_STAT_AI_DVSf, + /* lsp */ 21, + /* len */ 4 + }, + { /* name */ MACSEC_STAT_AI_LSf, + /* lsp */ 20, + /* len */ 1 + }, + { /* name */ MACSEC_STAT_AI_DSf, + /* lsp */ 19, + /* len */ 1 + }, + { /* name */ MACSEC_STAT_AI_SDf, + /* lsp */ 18, + /* len */ 1 + }, + { /* name */ MACSEC_STAT_AI_TEST1f, + /* lsp */ 17, + /* len */ 1 + }, + { /* name */ MACSEC_STAT_AI_TESTRWMf, + /* lsp */ 16, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 10, + /* len */ 6 + }, + { /* name */ MACSEC_STAT_AE_DVSEf, + /* lsp */ 9, + /* len */ 1 + }, + { /* name */ MACSEC_STAT_AE_DVSf, + /* lsp */ 5, + /* len */ 4 + }, + { /* name */ MACSEC_STAT_AE_LSf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ MACSEC_STAT_AE_DSf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ MACSEC_STAT_AE_SDf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ MACSEC_STAT_AE_TEST1f, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ MACSEC_STAT_AE_TESTRWMf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t MACSEC_MBIST_SA_FAIL_PORT4_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 20, + /* len */ 12 + }, + { /* name */ BIST_FAIL_MACSEC_STAT_AEf, + /* lsp */ 19, + /* len */ 1 + }, + { /* name */ DRF_BIST_FAIL_MACSEC_STAT_AEf, + /* lsp */ 18, + /* len */ 1 + }, + { /* name */ BIST_FAIL_MACSEC_STAT_AIf, + /* lsp */ 17, + /* len */ 1 + }, + { /* name */ DRF_BIST_FAIL_MACSEC_STAT_AIf, + /* lsp */ 16, + /* len */ 1 + }, + { /* name */ BIST_FAIL_MACSEC_SA_AE3f, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ DRF_BIST_FAIL_MACSEC_SA_AE3f, + /* lsp */ 14, + /* len */ 1 + }, + { /* name */ BIST_FAIL_MACSEC_SA_AE2f, + /* lsp */ 13, + /* len */ 1 + }, + { /* name */ DRF_BIST_FAIL_MACSEC_SA_AE2f, + /* lsp */ 12, + /* len */ 1 + }, + { /* name */ BIST_FAIL_MACSEC_SA_AE1f, + /* lsp */ 11, + /* len */ 1 + }, + { /* name */ DRF_BIST_FAIL_MACSEC_SA_AE1f, + /* lsp */ 10, + /* len */ 1 + }, + { /* name */ BIST_FAIL_MACSEC_SA_AE0f, + /* lsp */ 9, + /* len */ 1 + }, + { /* name */ DRF_BIST_FAIL_MACSEC_SA_AE0f, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ BIST_FAIL_MACSEC_SA_AI3f, + /* lsp */ 7, + /* len */ 1 + }, + { /* name */ DRF_BIST_FAIL_MACSEC_SA_AI3f, + /* lsp */ 6, + /* len */ 1 + }, + { /* name */ BIST_FAIL_MACSEC_SA_AI2f, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ DRF_BIST_FAIL_MACSEC_SA_AI2f, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ BIST_FAIL_MACSEC_SA_AI1f, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ DRF_BIST_FAIL_MACSEC_SA_AI1f, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ BIST_FAIL_MACSEC_SA_AI0f, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ DRF_BIST_FAIL_MACSEC_SA_AI0f, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t MACSEC_XGLBK_FIFO_DBG_PORT4_FIELDS[] = +{ + { /* name */ CFG_WATER_LEVEL_STf, + /* lsp */ 28, + /* len */ 4 + }, + { /* name */ CFG_WATER_LEVEL_Hf, + /* lsp */ 24, + /* len */ 4 + }, + { /* name */ CFG_WATER_LEVEL_Lf, + /* lsp */ 20, + /* len */ 4 + }, + { /* name */ CFG_FAULT_ONf, + /* lsp */ 19, + /* len */ 1 + }, + { /* name */ CFG_ERROR_ONf, + /* lsp */ 18, + /* len */ 1 + }, + { /* name */ CFG_SEQ_RSV_ONf, + /* lsp */ 17, + /* len */ 1 + }, + { /* name */ CFG_CLR_FIFO_OVTHRf, + /* lsp */ 16, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 5, + /* len */ 11 + }, + { /* name */ XGLBK_FIFO_DBG_ENf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ XGLBK_FIFO_DBG_SELf, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t MACSEC_REG_RWDH_AE_PORT4_FIELDS[] = +{ + { /* name */ REG_DATA_AE_Lf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ REG_DATA_AE_Hf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_REG_ADDR_AE_PORT4_FIELDS[] = +{ + { /* name */ REG_ADDR_AEf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RESERVEDf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_REG_CMD_AE_PORT4_FIELDS[] = +{ + { /* name */ REG_DATA_AI_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RESERVEDf, + /* lsp */ 5, + /* len */ 11 + }, + { /* name */ REG_RD_REQ_AEf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 1, + /* len */ 3 + }, + { /* name */ REG_WR_REQ_AEf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t MACSEC_REG_RWDL_AI_PORT4_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ REG_DATA_AI_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_REG_ADDR_AI_PORT4_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 21, + /* len */ 11 + }, + { /* name */ REG_RD_REQ_AIf, + /* lsp */ 20, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 17, + /* len */ 3 + }, + { /* name */ REG_WR_REQ_AIf, + /* lsp */ 16, + /* len */ 1 + }, + { /* name */ REG_ADDR_AIf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_REG_RWD_PTP_PORT4_FIELDS[] = +{ + { /* name */ REG_ADDR_PTPf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ REG_DATA_PTPf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_REG_CMD_PTP_PORT4_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 5, + /* len */ 27 + }, + { /* name */ REG_RD_REQ_PTPf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 1, + /* len */ 3 + }, + { /* name */ REG_WR_REQ_PTPf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t UNUSED_005C_PORT4_FIELDS[] = +{ + { /* name */ UNUSED_005C_PORT4f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0060_PORT4_FIELDS[] = +{ + { /* name */ UNUSED_0060_PORT4f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0064_PORT4_FIELDS[] = +{ + { /* name */ UNUSED_0064_PORT4f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0068_PORT4_FIELDS[] = +{ + { /* name */ UNUSED_0068_PORT4f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_006C_PORT4_FIELDS[] = +{ + { /* name */ UNUSED_006C_PORT4f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0070_PORT4_FIELDS[] = +{ + { /* name */ UNUSED_0070_PORT4f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0074_PORT4_FIELDS[] = +{ + { /* name */ UNUSED_0074_PORT4f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t RESERVED_0078_PORT4_FIELDS[] = +{ + { /* name */ RESERVED_0078_PORT4f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t RESERVED_007C_PORT4_FIELDS[] = +{ + { /* name */ RESERVED_007C_PORT4f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t MACSEC_TXSYSCRCERR_CNT_PORT4_FIELDS[] = +{ + { /* name */ TXSYS_CRCERR_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TXSYS_CRCERR_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_TXSYSPKTERR_CNT_PORT4_FIELDS[] = +{ + { /* name */ TXSYS_PKTERR_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TXSYS_PKTERR_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_TXSYSOK_CNT_0_PORT4_FIELDS[] = +{ + { /* name */ TXSYS_OK_CNT_1f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TXSYS_OK_CNT_0f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_TXSYSOK_CNT_2_PORT4_FIELDS[] = +{ + { /* name */ TXSYS_OK_CNT_3f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TXSYS_OK_CNT_2f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_TXSYSGERR_CNT_PORT4_FIELDS[] = +{ + { /* name */ TXSYS_GERR_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TXSYS_GERR_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_TXSYSGLPIERR_CNT_PORT4_FIELDS[] = +{ + { /* name */ TXSYS_GLPIERR_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TXSYS_GLPIERR_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_TXSYS_DBG_PORT4_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 20, + /* len */ 12 + }, + { /* name */ TXSYS_XG2IP_FSMf, + /* lsp */ 16, + /* len */ 4 + }, + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 12 + }, + { /* name */ TXSYS_WRP2IP_FSMf, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t MACSEC_TX_RX_CNT_INCR_PORT4_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 28, + /* len */ 4 + }, + { /* name */ RXSYS_UNDERRUN_CNT_INCRf, + /* lsp */ 27, + /* len */ 1 + }, + { /* name */ RXSYS_DROP_CNT_INCRf, + /* lsp */ 26, + /* len */ 1 + }, + { /* name */ RXSYS_PKTERR_CNT_INCRf, + /* lsp */ 25, + /* len */ 1 + }, + { /* name */ RXSYS_CRCERR_CNT_INCRf, + /* lsp */ 24, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 19, + /* len */ 5 + }, + { /* name */ RXLINE_OVERFLOW_CNT_INCRf, + /* lsp */ 18, + /* len */ 1 + }, + { /* name */ RXLINE_PKTERR_CNT_INCRf, + /* lsp */ 17, + /* len */ 1 + }, + { /* name */ RXLINE_CRCERR_CNT_INCRf, + /* lsp */ 16, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 4 + }, + { /* name */ TXLINE_UNDERRUN_CNT_INCRf, + /* lsp */ 11, + /* len */ 1 + }, + { /* name */ TXLINE_DROP_CNT_INCRf, + /* lsp */ 10, + /* len */ 1 + }, + { /* name */ TXLINE_PKTERR_CNT_INCRf, + /* lsp */ 9, + /* len */ 1 + }, + { /* name */ TXLINE_CRCERR_CNT_INCRf, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 3, + /* len */ 5 + }, + { /* name */ TXSYS_OVERFLOW_CNT_INCRf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ TXSYS_PKTERR_CNT_INCRf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ TXSYS_CRCERR_CNT_INCRf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t MACSEC_TXLINECRCERR_CNT_PORT4_FIELDS[] = +{ + { /* name */ TXLINE_CRCERR_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TXLINE_CRCERR_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_TXLINEPKTERR_CNT_PORT4_FIELDS[] = +{ + { /* name */ TXLINE_PKTERR_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TXLINE_PKTERR_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_TXLINEOK_CNT_0_PORT4_FIELDS[] = +{ + { /* name */ TXLINE_OK_CNT_1f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TXLINE_OK_CNT_0f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_TXLINEOK_CNT_2_PORT4_FIELDS[] = +{ + { /* name */ TXLINE_OK_CNT_3f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TXLINE_OK_CNT_2f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_TXLINEDROP_CNT_PORT4_FIELDS[] = +{ + { /* name */ TXLINE_DROP_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TXLINE_DROP_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_TXLINESRT_CNT_PORT4_FIELDS[] = +{ + { /* name */ TXLINE_SRTPKT_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TXLINE_SRTPKT_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_TXLINEGERR_CNT_PORT4_FIELDS[] = +{ + { /* name */ TXLINE_GERR_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TXLINE_GERR_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_TXLINE_DBG_PORT4_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 21, + /* len */ 11 + }, + { /* name */ TXLINE_IP2XG_FSMf, + /* lsp */ 16, + /* len */ 5 + }, + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 12 + }, + { /* name */ TXLINE_IP2WRP_FSMf, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t MACSEC_RXLINECRCERR_CNT_PORT4_FIELDS[] = +{ + { /* name */ RXLINE_CRCERR_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXLINE_CRCERR_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXLINEPKTERR_CNT_PORT4_FIELDS[] = +{ + { /* name */ RXLINE_PKTERR_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXLINE_PKTERR_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXLINEOK_CNT_0_PORT4_FIELDS[] = +{ + { /* name */ RXLINE_OK_CNT_1f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXLINE_OK_CNT_0f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXLINEOK_CNT_2_PORT4_FIELDS[] = +{ + { /* name */ RXLINE_OK_CNT_3f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXLINE_OK_CNT_2f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXLINESRT_CNT_PORT4_FIELDS[] = +{ + { /* name */ RXLINE_SHORTPKT_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXLINE_SHORTPKT_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXLINEGERR_CNT_PORT4_FIELDS[] = +{ + { /* name */ RXLINE_GERR_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXLINE_GERR_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXLINEGLPIERR_CNT_PORT4_FIELDS[] = +{ + { /* name */ RXLINE_GLPIERR_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXLINE_GLPIERR_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXLINE_DBG_PORT4_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 20, + /* len */ 12 + }, + { /* name */ RXLINE_XG2IP_FSMf, + /* lsp */ 16, + /* len */ 4 + }, + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 12 + }, + { /* name */ RXLINE_WRP2IP_FSMf, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t MACSEC_RXSYSCRCERR_CNT_PORT4_FIELDS[] = +{ + { /* name */ RXSYS_CRCERR_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXSYS_CRCERR_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXSYSPKTERR_CNT_PORT4_FIELDS[] = +{ + { /* name */ RXSYS_PKTERR_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXSYS_PKTERR_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXSYSOK_CNT_0_PORT4_FIELDS[] = +{ + { /* name */ RXSYS_OK_CNT_1f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXSYS_OK_CNT_0f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXSYSOK_CNT_2_PORT4_FIELDS[] = +{ + { /* name */ RXSYS_OK_CNT_3f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXSYS_OK_CNT_2f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXSYSDROP_CNT_PORT4_FIELDS[] = +{ + { /* name */ RXSYS_DROP_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXSYS_DROP_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXSYSSRT_CNT_PORT4_FIELDS[] = +{ + { /* name */ RXSYS_DECRYPTSRT_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXSYS_DECRYPTSRT_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXSYSGERR_CNT_PORT4_FIELDS[] = +{ + { /* name */ RXSYS_GERR_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXSYS_GERR_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXSYS_DBG_PORT4_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 21, + /* len */ 11 + }, + { /* name */ RXSYS_IP2XG_FSMf, + /* lsp */ 16, + /* len */ 5 + }, + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 12 + }, + { /* name */ RXSYS_IP2WRP_FSMf, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t MACSEC_TXSYS_CFG1_PORT4_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 21, + /* len */ 11 + }, + { /* name */ TXSYS_XGMINIFGf, + /* lsp */ 16, + /* len */ 5 + }, + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 4 + }, + { /* name */ TXSYS_MINIFGf, + /* lsp */ 8, + /* len */ 4 + }, + { /* name */ RESERVEDf, + /* lsp */ 3, + /* len */ 5 + }, + { /* name */ TXSYS_PMBNUMf, + /* lsp */ 0, + /* len */ 3 + }, +}; + +rtk_regField_t MACSEC_TXSYS_PTPCFG_PORT4_FIELDS[] = +{ + { /* name */ TXSYS_OUTERVLAN1f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RESERVEDf, + /* lsp */ 14, + /* len */ 2 + }, + { /* name */ PTP_UDP_ENf, + /* lsp */ 13, + /* len */ 1 + }, + { /* name */ PTP_ETH_ENf, + /* lsp */ 12, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 9, + /* len */ 3 + }, + { /* name */ TXSYS_PTPCRYPT_ENf, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 6, + /* len */ 2 + }, + { /* name */ TXSYS_FLOWIDf, + /* lsp */ 0, + /* len */ 6 + }, +}; + +rtk_regField_t MACSEC_TXSYS_OUTERVLAN2_PORT4_FIELDS[] = +{ + { /* name */ TXSYS_OUTERVLAN3f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TXSYS_OUTERVLAN2f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_TXSYS_OUTERVLAN4_PORT4_FIELDS[] = +{ + { /* name */ TXSYS_INNERVLAN1f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TXSYS_OUTERVLAN4f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_TXSYS_INNERVLAN2_PORT4_FIELDS[] = +{ + { /* name */ TXSYS_INNERVLAN3f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TXSYS_INNERVLAN2f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_TXSYS_INNERVLAN4_PORT4_FIELDS[] = +{ + { /* name */ TXSYS_INNERVLAN5f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TXSYS_INNERVLAN4f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_TXSYS_INNERVLAN6_PORT4_FIELDS[] = +{ + { /* name */ TXSYS_INNERVLAN7f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TXSYS_INNERVLAN6f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t UNUSED_011C_PORT4_FIELDS[] = +{ + { /* name */ UNUSED_011C_PORT4f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0120_PORT4_FIELDS[] = +{ + { /* name */ UNUSED_0120_PORT4f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0124_PORT4_FIELDS[] = +{ + { /* name */ UNUSED_0124_PORT4f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0128_PORT4_FIELDS[] = +{ + { /* name */ UNUSED_0128_PORT4f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_012C_PORT4_FIELDS[] = +{ + { /* name */ UNUSED_012C_PORT4f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0130_PORT4_FIELDS[] = +{ + { /* name */ UNUSED_0130_PORT4f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0134_PORT4_FIELDS[] = +{ + { /* name */ UNUSED_0134_PORT4f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0138_PORT4_FIELDS[] = +{ + { /* name */ UNUSED_0138_PORT4f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_013C_PORT4_FIELDS[] = +{ + { /* name */ UNUSED_013C_PORT4f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t MACSEC_TXLINE_CFG1_PORT4_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 24, + /* len */ 8 + }, + { /* name */ TXLINE_WAIT_Tf, + /* lsp */ 16, + /* len */ 8 + }, + { /* name */ TXLINE_MINIFGf, + /* lsp */ 8, + /* len */ 8 + }, + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 4 + }, + { /* name */ TXLINE_PMBNUMf, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t MACSEC_TXLINE_CFG3_PORT4_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 24, + /* len */ 8 + }, + { /* name */ TXLINE_FIFO_TSHDf, + /* lsp */ 16, + /* len */ 8 + }, + { /* name */ RESERVEDf, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ TXLINE_PAD_VLAN_ENf, + /* lsp */ 14, + /* len */ 1 + }, + { /* name */ TXLINE_PAD_MACSEC_ENf, + /* lsp */ 13, + /* len */ 1 + }, + { /* name */ TXLINE_PAD_ENf, + /* lsp */ 12, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 9, + /* len */ 3 + }, + { /* name */ TXLINE_PKTERR_INVRSCRC_ENf, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 6, + /* len */ 2 + }, + { /* name */ TXLINE_GMIIER_INVRSCRC_ENf, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ TXLINE_CRCERR_INVRSCRC_ENf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 1, + /* len */ 3 + }, + { /* name */ TXLINE_CLASSDROP_ENf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t MACSEC_TXLINE_CFG5_PORT4_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 20, + /* len */ 12 + }, + { /* name */ TXLINE_AVG_IPGf, + /* lsp */ 16, + /* len */ 4 + }, + { /* name */ RESERVEDf, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ TXLIEN_LPIEXIT_Tf, + /* lsp */ 0, + /* len */ 15 + }, +}; + +rtk_regField_t UNUSED_014C_PORT4_FIELDS[] = +{ + { /* name */ UNUSED_014C_PORT4f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0150_PORT4_FIELDS[] = +{ + { /* name */ UNUSED_0150_PORT4f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0154_PORT4_FIELDS[] = +{ + { /* name */ UNUSED_0154_PORT4f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0158_PORT4_FIELDS[] = +{ + { /* name */ UNUSED_0158_PORT4f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_015C_PORT4_FIELDS[] = +{ + { /* name */ UNUSED_015C_PORT4f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0160_PORT4_FIELDS[] = +{ + { /* name */ UNUSED_0160_PORT4f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0164_PORT4_FIELDS[] = +{ + { /* name */ UNUSED_0164_PORT4f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0168_PORT4_FIELDS[] = +{ + { /* name */ UNUSED_0168_PORT4f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_016C_PORT4_FIELDS[] = +{ + { /* name */ UNUSED_016C_PORT4f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0170_PORT4_FIELDS[] = +{ + { /* name */ UNUSED_0170_PORT4f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0174_PORT4_FIELDS[] = +{ + { /* name */ UNUSED_0174_PORT4f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0178_PORT4_FIELDS[] = +{ + { /* name */ UNUSED_0178_PORT4f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_017C_PORT4_FIELDS[] = +{ + { /* name */ UNUSED_017C_PORT4f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t MACSEC_RXLINE_CFG1_PORT4_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 21, + /* len */ 11 + }, + { /* name */ RXLINE_XGMINIFGf, + /* lsp */ 16, + /* len */ 5 + }, + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 4 + }, + { /* name */ RXLINE_MINIPGf, + /* lsp */ 8, + /* len */ 4 + }, + { /* name */ RESERVEDf, + /* lsp */ 3, + /* len */ 5 + }, + { /* name */ RXLINE_PMBNUMf, + /* lsp */ 0, + /* len */ 3 + }, +}; + +rtk_regField_t UNUSED_0184_PORT4_FIELDS[] = +{ + { /* name */ UNUSED_0184_PORT4f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0188_PORT4_FIELDS[] = +{ + { /* name */ UNUSED_0188_PORT4f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_018C_PORT4_FIELDS[] = +{ + { /* name */ UNUSED_018C_PORT4f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0190_PORT4_FIELDS[] = +{ + { /* name */ UNUSED_0190_PORT4f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0194_PORT4_FIELDS[] = +{ + { /* name */ UNUSED_0194_PORT4f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0198_PORT4_FIELDS[] = +{ + { /* name */ UNUSED_0198_PORT4f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_019C_PORT4_FIELDS[] = +{ + { /* name */ UNUSED_019C_PORT4f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_01A0_PORT4_FIELDS[] = +{ + { /* name */ UNUSED_01A0_PORT4f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_01A4_PORT4_FIELDS[] = +{ + { /* name */ UNUSED_01A4_PORT4f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_01A8_PORT4_FIELDS[] = +{ + { /* name */ UNUSED_01A8_PORT4f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_01AC_PORT4_FIELDS[] = +{ + { /* name */ UNUSED_01AC_PORT4f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_01B0_PORT4_FIELDS[] = +{ + { /* name */ UNUSED_01B0_PORT4f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_01B4_PORT4_FIELDS[] = +{ + { /* name */ UNUSED_01B4_PORT4f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_01B8_PORT4_FIELDS[] = +{ + { /* name */ UNUSED_01B8_PORT4f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_01BC_PORT4_FIELDS[] = +{ + { /* name */ UNUSED_01BC_PORT4f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t MACSEC_RXSYS_CFG1_PORT4_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 24, + /* len */ 8 + }, + { /* name */ RXSYS_WAIT_Tf, + /* lsp */ 16, + /* len */ 8 + }, + { /* name */ RXSYS_MINIPGf, + /* lsp */ 8, + /* len */ 8 + }, + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 4 + }, + { /* name */ RXSYS_PMBNUMf, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t MACSEC_RXSYS_CFG3_PORT4_FIELDS[] = +{ + { /* name */ RXSYS_OUTERVLAN1f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RESERVEDf, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ RXSYS_PAD_VLAN_ENf, + /* lsp */ 14, + /* len */ 1 + }, + { /* name */ RXSYS_PAD_LINESRT_ENf, + /* lsp */ 13, + /* len */ 1 + }, + { /* name */ RXSYS_PAD_DECRYPTSRT_ENf, + /* lsp */ 12, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 9, + /* len */ 3 + }, + { /* name */ RXSYS_PKTERR_INVRSCRC_ENf, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 6, + /* len */ 2 + }, + { /* name */ RXSYS_GMIIER_INVRSCRC_ENf, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ RXSYS_CRCERR_INVRSCRC_ENf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 1, + /* len */ 3 + }, + { /* name */ RXSYS_CLASSDROP_ENf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t MACSEC_RXSYS_OUTERVLAN2_PORT4_FIELDS[] = +{ + { /* name */ RXSYS_OUTERVLAN3f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXSYS_OUTERVLAN2f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXSYS_OUTERVLAN4_PORT4_FIELDS[] = +{ + { /* name */ RXSYS_INNERVLAN1f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXSYS_OUTERVLAN4f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXSYS_INNERVLAN2_PORT4_FIELDS[] = +{ + { /* name */ RXSYS_INNERVLAN3f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXSYS_INNERVLAN2f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXSYS_INNERVLAN4_PORT4_FIELDS[] = +{ + { /* name */ RXSYS_INNERVLAN5f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXSYS_INNERVLAN4f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXSYS_INNERVLAN6_PORT4_FIELDS[] = +{ + { /* name */ RXSYS_INNERVLAN7f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXSYS_INNERVLAN6f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXSYS_CFG4_PORT4_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 31, + /* len */ 1 + }, + { /* name */ RXSYS_LPIEXIT_Tf, + /* lsp */ 16, + /* len */ 15 + }, + { /* name */ RXSYS_FIFO_FTUNEf, + /* lsp */ 8, + /* len */ 8 + }, + { /* name */ RXSYS_FIFO_TSHDf, + /* lsp */ 0, + /* len */ 8 + }, +}; + +rtk_regField_t MACSEC_RXSYS_CFG6_PORT4_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 28 + }, + { /* name */ RXSYS_AVG_IPGf, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t MACSEC_REG_GLB_SET1_PORT5_FIELDS[] = +{ + { /* name */ RX_GATINGf, + /* lsp */ 31, + /* len */ 1 + }, + { /* name */ TX_GATINGf, + /* lsp */ 30, + /* len */ 1 + }, + { /* name */ DBG_ENf, + /* lsp */ 29, + /* len */ 1 + }, + { /* name */ DBG_SELf, + /* lsp */ 24, + /* len */ 5 + }, + { /* name */ DBG_SPD_SELf, + /* lsp */ 23, + /* len */ 1 + }, + { /* name */ RX_G_IOSAMEPMBf, + /* lsp */ 22, + /* len */ 1 + }, + { /* name */ TX_G_IOSAMEPMBf, + /* lsp */ 21, + /* len */ 1 + }, + { /* name */ MIBCNT_MODEf, + /* lsp */ 20, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 19, + /* len */ 1 + }, + { /* name */ RX_XGDIC_ENf, + /* lsp */ 18, + /* len */ 1 + }, + { /* name */ TX_XGDIC_ENf, + /* lsp */ 17, + /* len */ 1 + }, + { /* name */ MIBCNT_SWRST_Nf, + /* lsp */ 16, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ PTPBYPASS_ENf, + /* lsp */ 14, + /* len */ 1 + }, + { /* name */ SYSLPBK_ENf, + /* lsp */ 13, + /* len */ 1 + }, + { /* name */ PHY2MAC_ENf, + /* lsp */ 12, + /* len */ 1 + }, + { /* name */ RX_IPRST_Nf, + /* lsp */ 11, + /* len */ 1 + }, + { /* name */ RX_IPBYPASS_ENf, + /* lsp */ 10, + /* len */ 1 + }, + { /* name */ RX_MACSECBYPASS_ENf, + /* lsp */ 9, + /* len */ 1 + }, + { /* name */ RX_SWRST_ENf, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 6, + /* len */ 2 + }, + { /* name */ LINELPBK_ENf, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ MAC2PHY_ENf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ TX_IPRST_Nf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ TX_IPBYPASS_ENf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ TX_MACSECBYPASS_ENf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ TX_SWRST_ENf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t MACSEC_REG_GLB_IMR_PORT5_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 20 + }, + { /* name */ RX_IPILOCK_XG_IMRf, + /* lsp */ 11, + /* len */ 1 + }, + { /* name */ RX_IPILOCK_IMRf, + /* lsp */ 10, + /* len */ 1 + }, + { /* name */ RX_IPISECFAIL_IMRf, + /* lsp */ 9, + /* len */ 1 + }, + { /* name */ RX_IPI_GLB_IMRf, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 4 + }, + { /* name */ TX_IPELOCK_XG_IMRf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ TX_IPELOCK_IMRf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ TX_IPESECFAIL_IMRf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ TX_IPE_GLB_IMRf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t MACSEC_REG_GLB_ISR_PORT5_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 20 + }, + { /* name */ RX_IPILOCK_XG_ISRf, + /* lsp */ 11, + /* len */ 1 + }, + { /* name */ RX_IPILOCK_ISRf, + /* lsp */ 10, + /* len */ 1 + }, + { /* name */ RX_IPISECFAIL_ISRf, + /* lsp */ 9, + /* len */ 1 + }, + { /* name */ RX_IPI_GLB_ISRf, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 4 + }, + { /* name */ TX_IPELOCK_XG_ISRf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ TX_IPELOCK_ISRf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ TX_IPESECFAIL_ISRf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ TX_IPE_GLB_ISRf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t UNUSED_000C_PORT5_FIELDS[] = +{ + { /* name */ UNUSED_000C_PORT5f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t MACSEC_PM_CTRL_PORT5_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 2, + /* len */ 30 + }, + { /* name */ MACSEC_RX_ICG_ENf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ MACSEC_TX_ICG_ENf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t MACSEC_REG_GLB_MASK_PORT5_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 30, + /* len */ 2 + }, + { /* name */ RX_MTUf, + /* lsp */ 24, + /* len */ 6 + }, + { /* name */ RESERVEDf, + /* lsp */ 22, + /* len */ 2 + }, + { /* name */ TX_MTUf, + /* lsp */ 16, + /* len */ 6 + }, + { /* name */ RESERVEDf, + /* lsp */ 13, + /* len */ 3 + }, + { /* name */ RX_XGMASKf, + /* lsp */ 12, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 9, + /* len */ 3 + }, + { /* name */ RXDV_GMASKf, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 5, + /* len */ 3 + }, + { /* name */ TX_XGMASKf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 1, + /* len */ 3 + }, + { /* name */ TXEN_GMASKf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t MACSEC_REG_GLB_SET4_PORT5_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 31, + /* len */ 1 + }, + { /* name */ TXMSKDELAY_VALf, + /* lsp */ 16, + /* len */ 15 + }, + { /* name */ RESERVEDf, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ RXMSKDELAY_VALf, + /* lsp */ 0, + /* len */ 15 + }, +}; + +rtk_regField_t MACSEC_REG_IP_PROBE_PORT5_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ PROBE_SEL_AEf, + /* lsp */ 8, + /* len */ 8 + }, + { /* name */ PROBE_SEL_AIf, + /* lsp */ 0, + /* len */ 8 + }, +}; + +rtk_regField_t UNUSED_0020_PORT5_FIELDS[] = +{ + { /* name */ UNUSED_0020_PORT5f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0024_PORT5_FIELDS[] = +{ + { /* name */ UNUSED_0024_PORT5f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t MACSEC_MBIST_SA_CTRL_PORT5_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 30, + /* len */ 2 + }, + { /* name */ BIST_MODE_MACSEC_SA_AEf, + /* lsp */ 29, + /* len */ 1 + }, + { /* name */ DRF_BIST_MODE_MACSEC_SA_AEf, + /* lsp */ 28, + /* len */ 1 + }, + { /* name */ BIST_RSTN_MACSEC_SA_AEf, + /* lsp */ 27, + /* len */ 1 + }, + { /* name */ BIST_LOOP_MODE_MACSEC_SA_AEf, + /* lsp */ 26, + /* len */ 1 + }, + { /* name */ DYN_READ_EN_MACSEC_SA_AEf, + /* lsp */ 25, + /* len */ 1 + }, + { /* name */ DRF_TESS_RESUME_MACSEC_SA_AEf, + /* lsp */ 24, + /* len */ 1 + }, + { /* name */ BIST_MODE_MACSEC_SA_AIf, + /* lsp */ 23, + /* len */ 1 + }, + { /* name */ DRF_BIST_MODE_MACSEC_SA_AIf, + /* lsp */ 22, + /* len */ 1 + }, + { /* name */ BIST_RSTN_MACSEC_SA_AIf, + /* lsp */ 21, + /* len */ 1 + }, + { /* name */ BIST_LOOP_MODE_MACSEC_SA_AIf, + /* lsp */ 20, + /* len */ 1 + }, + { /* name */ DYN_READ_EN_MACSEC_SA_AIf, + /* lsp */ 19, + /* len */ 1 + }, + { /* name */ DRF_TESS_RESUME_MACSEC_SA_AIf, + /* lsp */ 18, + /* len */ 1 + }, + { /* name */ MACSEC_SA_AE_ICG_ENf, + /* lsp */ 17, + /* len */ 1 + }, + { /* name */ MACSEC_SA_AI_ICG_ENf, + /* lsp */ 16, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_MBIST_STAT_CTRL_PORT5_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 28, + /* len */ 4 + }, + { /* name */ DRF_START_PAUSE_MACSEC_SA_AEf, + /* lsp */ 27, + /* len */ 1 + }, + { /* name */ BIST_DONE_MACSEC_SA_AEf, + /* lsp */ 26, + /* len */ 1 + }, + { /* name */ DRF_BIST_DONE_MACSEC_SA_AEf, + /* lsp */ 25, + /* len */ 1 + }, + { /* name */ DRF_START_PAUSE_MACSEC_SA_AIf, + /* lsp */ 24, + /* len */ 1 + }, + { /* name */ BIST_DONE_MACSEC_SA_AIf, + /* lsp */ 23, + /* len */ 1 + }, + { /* name */ DRF_BIST_DONE_MACSEC_SA_AIf, + /* lsp */ 22, + /* len */ 1 + }, + { /* name */ DRF_START_PAUSE_MACSEC_STAT_AEf, + /* lsp */ 21, + /* len */ 1 + }, + { /* name */ BIST_DONE_MACSEC_STAT_AEf, + /* lsp */ 20, + /* len */ 1 + }, + { /* name */ DRF_BIST_DONE_MACSEC_STAT_AEf, + /* lsp */ 19, + /* len */ 1 + }, + { /* name */ DRF_START_PAUSE_MACSEC_STAT_AIf, + /* lsp */ 18, + /* len */ 1 + }, + { /* name */ BIST_DONE_MACSEC_STAT_AIf, + /* lsp */ 17, + /* len */ 1 + }, + { /* name */ DRF_BIST_DONE_MACSEC_STAT_AIf, + /* lsp */ 16, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 14, + /* len */ 2 + }, + { /* name */ BIST_MODE_MACSEC_STAT_AEf, + /* lsp */ 13, + /* len */ 1 + }, + { /* name */ DRF_BIST_MODE_MACSEC_STAT_AEf, + /* lsp */ 12, + /* len */ 1 + }, + { /* name */ BIST_RSTN_MACSEC_STAT_AEf, + /* lsp */ 11, + /* len */ 1 + }, + { /* name */ BIST_LOOP_MODE_MACSEC_STAT_AEf, + /* lsp */ 10, + /* len */ 1 + }, + { /* name */ DYN_READ_EN_MACSEC_STAT_AEf, + /* lsp */ 9, + /* len */ 1 + }, + { /* name */ DRF_TESS_RESUME_MACSEC_STAT_AEf, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ BIST_MODE_MACSEC_STAT_AIf, + /* lsp */ 7, + /* len */ 1 + }, + { /* name */ DRF_BIST_MODE_MACSEC_STAT_AIf, + /* lsp */ 6, + /* len */ 1 + }, + { /* name */ BIST_RSTN_MACSEC_STAT_AIf, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ BIST_LOOP_MODE_MACSEC_STAT_AIf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ DYN_READ_EN_MACSEC_STAT_AIf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ DRF_TESS_RESUME_MACSEC_STAT_AIf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ MACSEC_STAT_AE_ICG_ENf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ MACSEC_STAT_AI_ICG_ENf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t MACSEC_MBIST_SA_AE_TEST_PORT5_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 28, + /* len */ 4 + }, + { /* name */ MACSEC_SA_AI_DVSEf, + /* lsp */ 27, + /* len */ 1 + }, + { /* name */ MACSEC_SA_AI_DVSf, + /* lsp */ 23, + /* len */ 4 + }, + { /* name */ MACSEC_SA_AI_LSf, + /* lsp */ 22, + /* len */ 1 + }, + { /* name */ MACSEC_SA_AI_DSf, + /* lsp */ 21, + /* len */ 1 + }, + { /* name */ MACSEC_SA_AI_SDf, + /* lsp */ 20, + /* len */ 1 + }, + { /* name */ MACSEC_SA_AI3_TEST1f, + /* lsp */ 19, + /* len */ 1 + }, + { /* name */ MACSEC_SA_AI2_TEST1f, + /* lsp */ 18, + /* len */ 1 + }, + { /* name */ MACSEC_SA_AI1_TEST1f, + /* lsp */ 17, + /* len */ 1 + }, + { /* name */ MACSEC_SA_AI0_TEST1f, + /* lsp */ 16, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 4 + }, + { /* name */ MACSEC_SA_AE_DVSEf, + /* lsp */ 11, + /* len */ 1 + }, + { /* name */ MACSEC_SA_AE_DVSf, + /* lsp */ 7, + /* len */ 4 + }, + { /* name */ MACSEC_SA_AE_LSf, + /* lsp */ 6, + /* len */ 1 + }, + { /* name */ MACSEC_SA_AE_DSf, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ MACSEC_SA_AE_SDf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ MACSEC_SA_AE3_TEST1f, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ MACSEC_SA_AE2_TEST1f, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ MACSEC_SA_AE1_TEST1f, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ MACSEC_SA_AE0_TEST1f, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t MACSEC_MBIST_STAT_AE_TEST_PORT5_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 26, + /* len */ 6 + }, + { /* name */ MACSEC_STAT_AI_DVSEf, + /* lsp */ 25, + /* len */ 1 + }, + { /* name */ MACSEC_STAT_AI_DVSf, + /* lsp */ 21, + /* len */ 4 + }, + { /* name */ MACSEC_STAT_AI_LSf, + /* lsp */ 20, + /* len */ 1 + }, + { /* name */ MACSEC_STAT_AI_DSf, + /* lsp */ 19, + /* len */ 1 + }, + { /* name */ MACSEC_STAT_AI_SDf, + /* lsp */ 18, + /* len */ 1 + }, + { /* name */ MACSEC_STAT_AI_TEST1f, + /* lsp */ 17, + /* len */ 1 + }, + { /* name */ MACSEC_STAT_AI_TESTRWMf, + /* lsp */ 16, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 10, + /* len */ 6 + }, + { /* name */ MACSEC_STAT_AE_DVSEf, + /* lsp */ 9, + /* len */ 1 + }, + { /* name */ MACSEC_STAT_AE_DVSf, + /* lsp */ 5, + /* len */ 4 + }, + { /* name */ MACSEC_STAT_AE_LSf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ MACSEC_STAT_AE_DSf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ MACSEC_STAT_AE_SDf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ MACSEC_STAT_AE_TEST1f, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ MACSEC_STAT_AE_TESTRWMf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t MACSEC_MBIST_SA_FAIL_PORT5_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 20, + /* len */ 12 + }, + { /* name */ BIST_FAIL_MACSEC_STAT_AEf, + /* lsp */ 19, + /* len */ 1 + }, + { /* name */ DRF_BIST_FAIL_MACSEC_STAT_AEf, + /* lsp */ 18, + /* len */ 1 + }, + { /* name */ BIST_FAIL_MACSEC_STAT_AIf, + /* lsp */ 17, + /* len */ 1 + }, + { /* name */ DRF_BIST_FAIL_MACSEC_STAT_AIf, + /* lsp */ 16, + /* len */ 1 + }, + { /* name */ BIST_FAIL_MACSEC_SA_AE3f, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ DRF_BIST_FAIL_MACSEC_SA_AE3f, + /* lsp */ 14, + /* len */ 1 + }, + { /* name */ BIST_FAIL_MACSEC_SA_AE2f, + /* lsp */ 13, + /* len */ 1 + }, + { /* name */ DRF_BIST_FAIL_MACSEC_SA_AE2f, + /* lsp */ 12, + /* len */ 1 + }, + { /* name */ BIST_FAIL_MACSEC_SA_AE1f, + /* lsp */ 11, + /* len */ 1 + }, + { /* name */ DRF_BIST_FAIL_MACSEC_SA_AE1f, + /* lsp */ 10, + /* len */ 1 + }, + { /* name */ BIST_FAIL_MACSEC_SA_AE0f, + /* lsp */ 9, + /* len */ 1 + }, + { /* name */ DRF_BIST_FAIL_MACSEC_SA_AE0f, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ BIST_FAIL_MACSEC_SA_AI3f, + /* lsp */ 7, + /* len */ 1 + }, + { /* name */ DRF_BIST_FAIL_MACSEC_SA_AI3f, + /* lsp */ 6, + /* len */ 1 + }, + { /* name */ BIST_FAIL_MACSEC_SA_AI2f, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ DRF_BIST_FAIL_MACSEC_SA_AI2f, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ BIST_FAIL_MACSEC_SA_AI1f, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ DRF_BIST_FAIL_MACSEC_SA_AI1f, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ BIST_FAIL_MACSEC_SA_AI0f, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ DRF_BIST_FAIL_MACSEC_SA_AI0f, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t MACSEC_XGLBK_FIFO_DBG_PORT5_FIELDS[] = +{ + { /* name */ CFG_WATER_LEVEL_STf, + /* lsp */ 28, + /* len */ 4 + }, + { /* name */ CFG_WATER_LEVEL_Hf, + /* lsp */ 24, + /* len */ 4 + }, + { /* name */ CFG_WATER_LEVEL_Lf, + /* lsp */ 20, + /* len */ 4 + }, + { /* name */ CFG_FAULT_ONf, + /* lsp */ 19, + /* len */ 1 + }, + { /* name */ CFG_ERROR_ONf, + /* lsp */ 18, + /* len */ 1 + }, + { /* name */ CFG_SEQ_RSV_ONf, + /* lsp */ 17, + /* len */ 1 + }, + { /* name */ CFG_CLR_FIFO_OVTHRf, + /* lsp */ 16, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 5, + /* len */ 11 + }, + { /* name */ XGLBK_FIFO_DBG_ENf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ XGLBK_FIFO_DBG_SELf, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t MACSEC_REG_RWDH_AE_PORT5_FIELDS[] = +{ + { /* name */ REG_DATA_AE_Lf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ REG_DATA_AE_Hf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_REG_ADDR_AE_PORT5_FIELDS[] = +{ + { /* name */ REG_ADDR_AEf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RESERVEDf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_REG_CMD_AE_PORT5_FIELDS[] = +{ + { /* name */ REG_DATA_AI_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RESERVEDf, + /* lsp */ 5, + /* len */ 11 + }, + { /* name */ REG_RD_REQ_AEf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 1, + /* len */ 3 + }, + { /* name */ REG_WR_REQ_AEf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t MACSEC_REG_RWDL_AI_PORT5_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ REG_DATA_AI_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_REG_ADDR_AI_PORT5_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 21, + /* len */ 11 + }, + { /* name */ REG_RD_REQ_AIf, + /* lsp */ 20, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 17, + /* len */ 3 + }, + { /* name */ REG_WR_REQ_AIf, + /* lsp */ 16, + /* len */ 1 + }, + { /* name */ REG_ADDR_AIf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_REG_RWD_PTP_PORT5_FIELDS[] = +{ + { /* name */ REG_ADDR_PTPf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ REG_DATA_PTPf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_REG_CMD_PTP_PORT5_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 5, + /* len */ 27 + }, + { /* name */ REG_RD_REQ_PTPf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 1, + /* len */ 3 + }, + { /* name */ REG_WR_REQ_PTPf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t UNUSED_005C_PORT5_FIELDS[] = +{ + { /* name */ UNUSED_005C_PORT5f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0060_PORT5_FIELDS[] = +{ + { /* name */ UNUSED_0060_PORT5f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0064_PORT5_FIELDS[] = +{ + { /* name */ UNUSED_0064_PORT5f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0068_PORT5_FIELDS[] = +{ + { /* name */ UNUSED_0068_PORT5f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_006C_PORT5_FIELDS[] = +{ + { /* name */ UNUSED_006C_PORT5f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0070_PORT5_FIELDS[] = +{ + { /* name */ UNUSED_0070_PORT5f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0074_PORT5_FIELDS[] = +{ + { /* name */ UNUSED_0074_PORT5f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t RESERVED_0078_PORT5_FIELDS[] = +{ + { /* name */ RESERVED_0078_PORT5f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t RESERVED_007C_PORT5_FIELDS[] = +{ + { /* name */ RESERVED_007C_PORT5f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t MACSEC_TXSYSCRCERR_CNT_PORT5_FIELDS[] = +{ + { /* name */ TXSYS_CRCERR_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TXSYS_CRCERR_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_TXSYSPKTERR_CNT_PORT5_FIELDS[] = +{ + { /* name */ TXSYS_PKTERR_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TXSYS_PKTERR_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_TXSYSOK_CNT_0_PORT5_FIELDS[] = +{ + { /* name */ TXSYS_OK_CNT_1f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TXSYS_OK_CNT_0f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_TXSYSOK_CNT_2_PORT5_FIELDS[] = +{ + { /* name */ TXSYS_OK_CNT_3f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TXSYS_OK_CNT_2f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_TXSYSGERR_CNT_PORT5_FIELDS[] = +{ + { /* name */ TXSYS_GERR_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TXSYS_GERR_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_TXSYSGLPIERR_CNT_PORT5_FIELDS[] = +{ + { /* name */ TXSYS_GLPIERR_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TXSYS_GLPIERR_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_TXSYS_DBG_PORT5_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 20, + /* len */ 12 + }, + { /* name */ TXSYS_XG2IP_FSMf, + /* lsp */ 16, + /* len */ 4 + }, + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 12 + }, + { /* name */ TXSYS_WRP2IP_FSMf, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t MACSEC_TX_RX_CNT_INCR_PORT5_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 28, + /* len */ 4 + }, + { /* name */ RXSYS_UNDERRUN_CNT_INCRf, + /* lsp */ 27, + /* len */ 1 + }, + { /* name */ RXSYS_DROP_CNT_INCRf, + /* lsp */ 26, + /* len */ 1 + }, + { /* name */ RXSYS_PKTERR_CNT_INCRf, + /* lsp */ 25, + /* len */ 1 + }, + { /* name */ RXSYS_CRCERR_CNT_INCRf, + /* lsp */ 24, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 19, + /* len */ 5 + }, + { /* name */ RXLINE_OVERFLOW_CNT_INCRf, + /* lsp */ 18, + /* len */ 1 + }, + { /* name */ RXLINE_PKTERR_CNT_INCRf, + /* lsp */ 17, + /* len */ 1 + }, + { /* name */ RXLINE_CRCERR_CNT_INCRf, + /* lsp */ 16, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 4 + }, + { /* name */ TXLINE_UNDERRUN_CNT_INCRf, + /* lsp */ 11, + /* len */ 1 + }, + { /* name */ TXLINE_DROP_CNT_INCRf, + /* lsp */ 10, + /* len */ 1 + }, + { /* name */ TXLINE_PKTERR_CNT_INCRf, + /* lsp */ 9, + /* len */ 1 + }, + { /* name */ TXLINE_CRCERR_CNT_INCRf, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 3, + /* len */ 5 + }, + { /* name */ TXSYS_OVERFLOW_CNT_INCRf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ TXSYS_PKTERR_CNT_INCRf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ TXSYS_CRCERR_CNT_INCRf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t MACSEC_TXLINECRCERR_CNT_PORT5_FIELDS[] = +{ + { /* name */ TXLINE_CRCERR_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TXLINE_CRCERR_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_TXLINEPKTERR_CNT_PORT5_FIELDS[] = +{ + { /* name */ TXLINE_PKTERR_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TXLINE_PKTERR_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_TXLINEOK_CNT_0_PORT5_FIELDS[] = +{ + { /* name */ TXLINE_OK_CNT_1f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TXLINE_OK_CNT_0f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_TXLINEOK_CNT_2_PORT5_FIELDS[] = +{ + { /* name */ TXLINE_OK_CNT_3f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TXLINE_OK_CNT_2f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_TXLINEDROP_CNT_PORT5_FIELDS[] = +{ + { /* name */ TXLINE_DROP_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TXLINE_DROP_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_TXLINESRT_CNT_PORT5_FIELDS[] = +{ + { /* name */ TXLINE_SRTPKT_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TXLINE_SRTPKT_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_TXLINEGERR_CNT_PORT5_FIELDS[] = +{ + { /* name */ TXLINE_GERR_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TXLINE_GERR_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_TXLINE_DBG_PORT5_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 21, + /* len */ 11 + }, + { /* name */ TXLINE_IP2XG_FSMf, + /* lsp */ 16, + /* len */ 5 + }, + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 12 + }, + { /* name */ TXLINE_IP2WRP_FSMf, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t MACSEC_RXLINECRCERR_CNT_PORT5_FIELDS[] = +{ + { /* name */ RXLINE_CRCERR_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXLINE_CRCERR_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXLINEPKTERR_CNT_PORT5_FIELDS[] = +{ + { /* name */ RXLINE_PKTERR_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXLINE_PKTERR_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXLINEOK_CNT_0_PORT5_FIELDS[] = +{ + { /* name */ RXLINE_OK_CNT_1f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXLINE_OK_CNT_0f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXLINEOK_CNT_2_PORT5_FIELDS[] = +{ + { /* name */ RXLINE_OK_CNT_3f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXLINE_OK_CNT_2f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXLINESRT_CNT_PORT5_FIELDS[] = +{ + { /* name */ RXLINE_SHORTPKT_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXLINE_SHORTPKT_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXLINEGERR_CNT_PORT5_FIELDS[] = +{ + { /* name */ RXLINE_GERR_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXLINE_GERR_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXLINEGLPIERR_CNT_PORT5_FIELDS[] = +{ + { /* name */ RXLINE_GLPIERR_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXLINE_GLPIERR_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXLINE_DBG_PORT5_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 20, + /* len */ 12 + }, + { /* name */ RXLINE_XG2IP_FSMf, + /* lsp */ 16, + /* len */ 4 + }, + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 12 + }, + { /* name */ RXLINE_WRP2IP_FSMf, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t MACSEC_RXSYSCRCERR_CNT_PORT5_FIELDS[] = +{ + { /* name */ RXSYS_CRCERR_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXSYS_CRCERR_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXSYSPKTERR_CNT_PORT5_FIELDS[] = +{ + { /* name */ RXSYS_PKTERR_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXSYS_PKTERR_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXSYSOK_CNT_0_PORT5_FIELDS[] = +{ + { /* name */ RXSYS_OK_CNT_1f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXSYS_OK_CNT_0f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXSYSOK_CNT_2_PORT5_FIELDS[] = +{ + { /* name */ RXSYS_OK_CNT_3f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXSYS_OK_CNT_2f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXSYSDROP_CNT_PORT5_FIELDS[] = +{ + { /* name */ RXSYS_DROP_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXSYS_DROP_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXSYSSRT_CNT_PORT5_FIELDS[] = +{ + { /* name */ RXSYS_DECRYPTSRT_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXSYS_DECRYPTSRT_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXSYSGERR_CNT_PORT5_FIELDS[] = +{ + { /* name */ RXSYS_GERR_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXSYS_GERR_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXSYS_DBG_PORT5_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 21, + /* len */ 11 + }, + { /* name */ RXSYS_IP2XG_FSMf, + /* lsp */ 16, + /* len */ 5 + }, + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 12 + }, + { /* name */ RXSYS_IP2WRP_FSMf, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t MACSEC_TXSYS_CFG1_PORT5_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 21, + /* len */ 11 + }, + { /* name */ TXSYS_XGMINIFGf, + /* lsp */ 16, + /* len */ 5 + }, + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 4 + }, + { /* name */ TXSYS_MINIFGf, + /* lsp */ 8, + /* len */ 4 + }, + { /* name */ RESERVEDf, + /* lsp */ 3, + /* len */ 5 + }, + { /* name */ TXSYS_PMBNUMf, + /* lsp */ 0, + /* len */ 3 + }, +}; + +rtk_regField_t MACSEC_TXSYS_PTPCFG_PORT5_FIELDS[] = +{ + { /* name */ TXSYS_OUTERVLAN1f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RESERVEDf, + /* lsp */ 14, + /* len */ 2 + }, + { /* name */ PTP_UDP_ENf, + /* lsp */ 13, + /* len */ 1 + }, + { /* name */ PTP_ETH_ENf, + /* lsp */ 12, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 9, + /* len */ 3 + }, + { /* name */ TXSYS_PTPCRYPT_ENf, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 6, + /* len */ 2 + }, + { /* name */ TXSYS_FLOWIDf, + /* lsp */ 0, + /* len */ 6 + }, +}; + +rtk_regField_t MACSEC_TXSYS_OUTERVLAN2_PORT5_FIELDS[] = +{ + { /* name */ TXSYS_OUTERVLAN3f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TXSYS_OUTERVLAN2f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_TXSYS_OUTERVLAN4_PORT5_FIELDS[] = +{ + { /* name */ TXSYS_INNERVLAN1f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TXSYS_OUTERVLAN4f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_TXSYS_INNERVLAN2_PORT5_FIELDS[] = +{ + { /* name */ TXSYS_INNERVLAN3f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TXSYS_INNERVLAN2f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_TXSYS_INNERVLAN4_PORT5_FIELDS[] = +{ + { /* name */ TXSYS_INNERVLAN5f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TXSYS_INNERVLAN4f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_TXSYS_INNERVLAN6_PORT5_FIELDS[] = +{ + { /* name */ TXSYS_INNERVLAN7f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TXSYS_INNERVLAN6f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t UNUSED_011C_PORT5_FIELDS[] = +{ + { /* name */ UNUSED_011C_PORT5f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0120_PORT5_FIELDS[] = +{ + { /* name */ UNUSED_0120_PORT5f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0124_PORT5_FIELDS[] = +{ + { /* name */ UNUSED_0124_PORT5f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0128_PORT5_FIELDS[] = +{ + { /* name */ UNUSED_0128_PORT5f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_012C_PORT5_FIELDS[] = +{ + { /* name */ UNUSED_012C_PORT5f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0130_PORT5_FIELDS[] = +{ + { /* name */ UNUSED_0130_PORT5f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0134_PORT5_FIELDS[] = +{ + { /* name */ UNUSED_0134_PORT5f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0138_PORT5_FIELDS[] = +{ + { /* name */ UNUSED_0138_PORT5f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_013C_PORT5_FIELDS[] = +{ + { /* name */ UNUSED_013C_PORT5f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t MACSEC_TXLINE_CFG1_PORT5_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 24, + /* len */ 8 + }, + { /* name */ TXLINE_WAIT_Tf, + /* lsp */ 16, + /* len */ 8 + }, + { /* name */ TXLINE_MINIFGf, + /* lsp */ 8, + /* len */ 8 + }, + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 4 + }, + { /* name */ TXLINE_PMBNUMf, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t MACSEC_TXLINE_CFG3_PORT5_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 24, + /* len */ 8 + }, + { /* name */ TXLINE_FIFO_TSHDf, + /* lsp */ 16, + /* len */ 8 + }, + { /* name */ RESERVEDf, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ TXLINE_PAD_VLAN_ENf, + /* lsp */ 14, + /* len */ 1 + }, + { /* name */ TXLINE_PAD_MACSEC_ENf, + /* lsp */ 13, + /* len */ 1 + }, + { /* name */ TXLINE_PAD_ENf, + /* lsp */ 12, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 9, + /* len */ 3 + }, + { /* name */ TXLINE_PKTERR_INVRSCRC_ENf, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 6, + /* len */ 2 + }, + { /* name */ TXLINE_GMIIER_INVRSCRC_ENf, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ TXLINE_CRCERR_INVRSCRC_ENf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 1, + /* len */ 3 + }, + { /* name */ TXLINE_CLASSDROP_ENf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t MACSEC_TXLINE_CFG5_PORT5_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 20, + /* len */ 12 + }, + { /* name */ TXLINE_AVG_IPGf, + /* lsp */ 16, + /* len */ 4 + }, + { /* name */ RESERVEDf, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ TXLIEN_LPIEXIT_Tf, + /* lsp */ 0, + /* len */ 15 + }, +}; + +rtk_regField_t UNUSED_014C_PORT5_FIELDS[] = +{ + { /* name */ UNUSED_014C_PORT5f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0150_PORT5_FIELDS[] = +{ + { /* name */ UNUSED_0150_PORT5f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0154_PORT5_FIELDS[] = +{ + { /* name */ UNUSED_0154_PORT5f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0158_PORT5_FIELDS[] = +{ + { /* name */ UNUSED_0158_PORT5f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_015C_PORT5_FIELDS[] = +{ + { /* name */ UNUSED_015C_PORT5f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0160_PORT5_FIELDS[] = +{ + { /* name */ UNUSED_0160_PORT5f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0164_PORT5_FIELDS[] = +{ + { /* name */ UNUSED_0164_PORT5f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0168_PORT5_FIELDS[] = +{ + { /* name */ UNUSED_0168_PORT5f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_016C_PORT5_FIELDS[] = +{ + { /* name */ UNUSED_016C_PORT5f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0170_PORT5_FIELDS[] = +{ + { /* name */ UNUSED_0170_PORT5f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0174_PORT5_FIELDS[] = +{ + { /* name */ UNUSED_0174_PORT5f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0178_PORT5_FIELDS[] = +{ + { /* name */ UNUSED_0178_PORT5f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_017C_PORT5_FIELDS[] = +{ + { /* name */ UNUSED_017C_PORT5f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t MACSEC_RXLINE_CFG1_PORT5_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 21, + /* len */ 11 + }, + { /* name */ RXLINE_XGMINIFGf, + /* lsp */ 16, + /* len */ 5 + }, + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 4 + }, + { /* name */ RXLINE_MINIPGf, + /* lsp */ 8, + /* len */ 4 + }, + { /* name */ RESERVEDf, + /* lsp */ 3, + /* len */ 5 + }, + { /* name */ RXLINE_PMBNUMf, + /* lsp */ 0, + /* len */ 3 + }, +}; + +rtk_regField_t UNUSED_0184_PORT5_FIELDS[] = +{ + { /* name */ UNUSED_0184_PORT5f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0188_PORT5_FIELDS[] = +{ + { /* name */ UNUSED_0188_PORT5f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_018C_PORT5_FIELDS[] = +{ + { /* name */ UNUSED_018C_PORT5f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0190_PORT5_FIELDS[] = +{ + { /* name */ UNUSED_0190_PORT5f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0194_PORT5_FIELDS[] = +{ + { /* name */ UNUSED_0194_PORT5f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0198_PORT5_FIELDS[] = +{ + { /* name */ UNUSED_0198_PORT5f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_019C_PORT5_FIELDS[] = +{ + { /* name */ UNUSED_019C_PORT5f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_01A0_PORT5_FIELDS[] = +{ + { /* name */ UNUSED_01A0_PORT5f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_01A4_PORT5_FIELDS[] = +{ + { /* name */ UNUSED_01A4_PORT5f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_01A8_PORT5_FIELDS[] = +{ + { /* name */ UNUSED_01A8_PORT5f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_01AC_PORT5_FIELDS[] = +{ + { /* name */ UNUSED_01AC_PORT5f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_01B0_PORT5_FIELDS[] = +{ + { /* name */ UNUSED_01B0_PORT5f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_01B4_PORT5_FIELDS[] = +{ + { /* name */ UNUSED_01B4_PORT5f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_01B8_PORT5_FIELDS[] = +{ + { /* name */ UNUSED_01B8_PORT5f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_01BC_PORT5_FIELDS[] = +{ + { /* name */ UNUSED_01BC_PORT5f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t MACSEC_RXSYS_CFG1_PORT5_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 24, + /* len */ 8 + }, + { /* name */ RXSYS_WAIT_Tf, + /* lsp */ 16, + /* len */ 8 + }, + { /* name */ RXSYS_MINIPGf, + /* lsp */ 8, + /* len */ 8 + }, + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 4 + }, + { /* name */ RXSYS_PMBNUMf, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t MACSEC_RXSYS_CFG3_PORT5_FIELDS[] = +{ + { /* name */ RXSYS_OUTERVLAN1f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RESERVEDf, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ RXSYS_PAD_VLAN_ENf, + /* lsp */ 14, + /* len */ 1 + }, + { /* name */ RXSYS_PAD_LINESRT_ENf, + /* lsp */ 13, + /* len */ 1 + }, + { /* name */ RXSYS_PAD_DECRYPTSRT_ENf, + /* lsp */ 12, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 9, + /* len */ 3 + }, + { /* name */ RXSYS_PKTERR_INVRSCRC_ENf, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 6, + /* len */ 2 + }, + { /* name */ RXSYS_GMIIER_INVRSCRC_ENf, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ RXSYS_CRCERR_INVRSCRC_ENf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 1, + /* len */ 3 + }, + { /* name */ RXSYS_CLASSDROP_ENf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t MACSEC_RXSYS_OUTERVLAN2_PORT5_FIELDS[] = +{ + { /* name */ RXSYS_OUTERVLAN3f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXSYS_OUTERVLAN2f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXSYS_OUTERVLAN4_PORT5_FIELDS[] = +{ + { /* name */ RXSYS_INNERVLAN1f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXSYS_OUTERVLAN4f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXSYS_INNERVLAN2_PORT5_FIELDS[] = +{ + { /* name */ RXSYS_INNERVLAN3f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXSYS_INNERVLAN2f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXSYS_INNERVLAN4_PORT5_FIELDS[] = +{ + { /* name */ RXSYS_INNERVLAN5f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXSYS_INNERVLAN4f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXSYS_INNERVLAN6_PORT5_FIELDS[] = +{ + { /* name */ RXSYS_INNERVLAN7f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXSYS_INNERVLAN6f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXSYS_CFG4_PORT5_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 31, + /* len */ 1 + }, + { /* name */ RXSYS_LPIEXIT_Tf, + /* lsp */ 16, + /* len */ 15 + }, + { /* name */ RXSYS_FIFO_FTUNEf, + /* lsp */ 8, + /* len */ 8 + }, + { /* name */ RXSYS_FIFO_TSHDf, + /* lsp */ 0, + /* len */ 8 + }, +}; + +rtk_regField_t MACSEC_RXSYS_CFG6_PORT5_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 28 + }, + { /* name */ RXSYS_AVG_IPGf, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t MACSEC_REG_GLB_SET1_PORT6_FIELDS[] = +{ + { /* name */ RX_GATINGf, + /* lsp */ 31, + /* len */ 1 + }, + { /* name */ TX_GATINGf, + /* lsp */ 30, + /* len */ 1 + }, + { /* name */ DBG_ENf, + /* lsp */ 29, + /* len */ 1 + }, + { /* name */ DBG_SELf, + /* lsp */ 24, + /* len */ 5 + }, + { /* name */ DBG_SPD_SELf, + /* lsp */ 23, + /* len */ 1 + }, + { /* name */ RX_G_IOSAMEPMBf, + /* lsp */ 22, + /* len */ 1 + }, + { /* name */ TX_G_IOSAMEPMBf, + /* lsp */ 21, + /* len */ 1 + }, + { /* name */ MIBCNT_MODEf, + /* lsp */ 20, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 19, + /* len */ 1 + }, + { /* name */ RX_XGDIC_ENf, + /* lsp */ 18, + /* len */ 1 + }, + { /* name */ TX_XGDIC_ENf, + /* lsp */ 17, + /* len */ 1 + }, + { /* name */ MIBCNT_SWRST_Nf, + /* lsp */ 16, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ PTPBYPASS_ENf, + /* lsp */ 14, + /* len */ 1 + }, + { /* name */ SYSLPBK_ENf, + /* lsp */ 13, + /* len */ 1 + }, + { /* name */ PHY2MAC_ENf, + /* lsp */ 12, + /* len */ 1 + }, + { /* name */ RX_IPRST_Nf, + /* lsp */ 11, + /* len */ 1 + }, + { /* name */ RX_IPBYPASS_ENf, + /* lsp */ 10, + /* len */ 1 + }, + { /* name */ RX_MACSECBYPASS_ENf, + /* lsp */ 9, + /* len */ 1 + }, + { /* name */ RX_SWRST_ENf, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 6, + /* len */ 2 + }, + { /* name */ LINELPBK_ENf, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ MAC2PHY_ENf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ TX_IPRST_Nf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ TX_IPBYPASS_ENf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ TX_MACSECBYPASS_ENf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ TX_SWRST_ENf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t MACSEC_REG_GLB_IMR_PORT6_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 20 + }, + { /* name */ RX_IPILOCK_XG_IMRf, + /* lsp */ 11, + /* len */ 1 + }, + { /* name */ RX_IPILOCK_IMRf, + /* lsp */ 10, + /* len */ 1 + }, + { /* name */ RX_IPISECFAIL_IMRf, + /* lsp */ 9, + /* len */ 1 + }, + { /* name */ RX_IPI_GLB_IMRf, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 4 + }, + { /* name */ TX_IPELOCK_XG_IMRf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ TX_IPELOCK_IMRf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ TX_IPESECFAIL_IMRf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ TX_IPE_GLB_IMRf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t MACSEC_REG_GLB_ISR_PORT6_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 20 + }, + { /* name */ RX_IPILOCK_XG_ISRf, + /* lsp */ 11, + /* len */ 1 + }, + { /* name */ RX_IPILOCK_ISRf, + /* lsp */ 10, + /* len */ 1 + }, + { /* name */ RX_IPISECFAIL_ISRf, + /* lsp */ 9, + /* len */ 1 + }, + { /* name */ RX_IPI_GLB_ISRf, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 4 + }, + { /* name */ TX_IPELOCK_XG_ISRf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ TX_IPELOCK_ISRf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ TX_IPESECFAIL_ISRf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ TX_IPE_GLB_ISRf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t UNUSED_000C_PORT6_FIELDS[] = +{ + { /* name */ UNUSED_000C_PORT6f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t MACSEC_PM_CTRL_PORT6_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 2, + /* len */ 30 + }, + { /* name */ MACSEC_RX_ICG_ENf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ MACSEC_TX_ICG_ENf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t MACSEC_REG_GLB_MASK_PORT6_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 30, + /* len */ 2 + }, + { /* name */ RX_MTUf, + /* lsp */ 24, + /* len */ 6 + }, + { /* name */ RESERVEDf, + /* lsp */ 22, + /* len */ 2 + }, + { /* name */ TX_MTUf, + /* lsp */ 16, + /* len */ 6 + }, + { /* name */ RESERVEDf, + /* lsp */ 13, + /* len */ 3 + }, + { /* name */ RX_XGMASKf, + /* lsp */ 12, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 9, + /* len */ 3 + }, + { /* name */ RXDV_GMASKf, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 5, + /* len */ 3 + }, + { /* name */ TX_XGMASKf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 1, + /* len */ 3 + }, + { /* name */ TXEN_GMASKf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t MACSEC_REG_GLB_SET4_PORT6_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 31, + /* len */ 1 + }, + { /* name */ TXMSKDELAY_VALf, + /* lsp */ 16, + /* len */ 15 + }, + { /* name */ RESERVEDf, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ RXMSKDELAY_VALf, + /* lsp */ 0, + /* len */ 15 + }, +}; + +rtk_regField_t MACSEC_REG_IP_PROBE_PORT6_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ PROBE_SEL_AEf, + /* lsp */ 8, + /* len */ 8 + }, + { /* name */ PROBE_SEL_AIf, + /* lsp */ 0, + /* len */ 8 + }, +}; + +rtk_regField_t UNUSED_0020_PORT6_FIELDS[] = +{ + { /* name */ UNUSED_0020_PORT6f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0024_PORT6_FIELDS[] = +{ + { /* name */ UNUSED_0024_PORT6f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t MACSEC_MBIST_SA_CTRL_PORT6_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 30, + /* len */ 2 + }, + { /* name */ BIST_MODE_MACSEC_SA_AEf, + /* lsp */ 29, + /* len */ 1 + }, + { /* name */ DRF_BIST_MODE_MACSEC_SA_AEf, + /* lsp */ 28, + /* len */ 1 + }, + { /* name */ BIST_RSTN_MACSEC_SA_AEf, + /* lsp */ 27, + /* len */ 1 + }, + { /* name */ BIST_LOOP_MODE_MACSEC_SA_AEf, + /* lsp */ 26, + /* len */ 1 + }, + { /* name */ DYN_READ_EN_MACSEC_SA_AEf, + /* lsp */ 25, + /* len */ 1 + }, + { /* name */ DRF_TESS_RESUME_MACSEC_SA_AEf, + /* lsp */ 24, + /* len */ 1 + }, + { /* name */ BIST_MODE_MACSEC_SA_AIf, + /* lsp */ 23, + /* len */ 1 + }, + { /* name */ DRF_BIST_MODE_MACSEC_SA_AIf, + /* lsp */ 22, + /* len */ 1 + }, + { /* name */ BIST_RSTN_MACSEC_SA_AIf, + /* lsp */ 21, + /* len */ 1 + }, + { /* name */ BIST_LOOP_MODE_MACSEC_SA_AIf, + /* lsp */ 20, + /* len */ 1 + }, + { /* name */ DYN_READ_EN_MACSEC_SA_AIf, + /* lsp */ 19, + /* len */ 1 + }, + { /* name */ DRF_TESS_RESUME_MACSEC_SA_AIf, + /* lsp */ 18, + /* len */ 1 + }, + { /* name */ MACSEC_SA_AE_ICG_ENf, + /* lsp */ 17, + /* len */ 1 + }, + { /* name */ MACSEC_SA_AI_ICG_ENf, + /* lsp */ 16, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_MBIST_STAT_CTRL_PORT6_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 28, + /* len */ 4 + }, + { /* name */ DRF_START_PAUSE_MACSEC_SA_AEf, + /* lsp */ 27, + /* len */ 1 + }, + { /* name */ BIST_DONE_MACSEC_SA_AEf, + /* lsp */ 26, + /* len */ 1 + }, + { /* name */ DRF_BIST_DONE_MACSEC_SA_AEf, + /* lsp */ 25, + /* len */ 1 + }, + { /* name */ DRF_START_PAUSE_MACSEC_SA_AIf, + /* lsp */ 24, + /* len */ 1 + }, + { /* name */ BIST_DONE_MACSEC_SA_AIf, + /* lsp */ 23, + /* len */ 1 + }, + { /* name */ DRF_BIST_DONE_MACSEC_SA_AIf, + /* lsp */ 22, + /* len */ 1 + }, + { /* name */ DRF_START_PAUSE_MACSEC_STAT_AEf, + /* lsp */ 21, + /* len */ 1 + }, + { /* name */ BIST_DONE_MACSEC_STAT_AEf, + /* lsp */ 20, + /* len */ 1 + }, + { /* name */ DRF_BIST_DONE_MACSEC_STAT_AEf, + /* lsp */ 19, + /* len */ 1 + }, + { /* name */ DRF_START_PAUSE_MACSEC_STAT_AIf, + /* lsp */ 18, + /* len */ 1 + }, + { /* name */ BIST_DONE_MACSEC_STAT_AIf, + /* lsp */ 17, + /* len */ 1 + }, + { /* name */ DRF_BIST_DONE_MACSEC_STAT_AIf, + /* lsp */ 16, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 14, + /* len */ 2 + }, + { /* name */ BIST_MODE_MACSEC_STAT_AEf, + /* lsp */ 13, + /* len */ 1 + }, + { /* name */ DRF_BIST_MODE_MACSEC_STAT_AEf, + /* lsp */ 12, + /* len */ 1 + }, + { /* name */ BIST_RSTN_MACSEC_STAT_AEf, + /* lsp */ 11, + /* len */ 1 + }, + { /* name */ BIST_LOOP_MODE_MACSEC_STAT_AEf, + /* lsp */ 10, + /* len */ 1 + }, + { /* name */ DYN_READ_EN_MACSEC_STAT_AEf, + /* lsp */ 9, + /* len */ 1 + }, + { /* name */ DRF_TESS_RESUME_MACSEC_STAT_AEf, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ BIST_MODE_MACSEC_STAT_AIf, + /* lsp */ 7, + /* len */ 1 + }, + { /* name */ DRF_BIST_MODE_MACSEC_STAT_AIf, + /* lsp */ 6, + /* len */ 1 + }, + { /* name */ BIST_RSTN_MACSEC_STAT_AIf, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ BIST_LOOP_MODE_MACSEC_STAT_AIf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ DYN_READ_EN_MACSEC_STAT_AIf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ DRF_TESS_RESUME_MACSEC_STAT_AIf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ MACSEC_STAT_AE_ICG_ENf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ MACSEC_STAT_AI_ICG_ENf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t MACSEC_MBIST_SA_AE_TEST_PORT6_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 28, + /* len */ 4 + }, + { /* name */ MACSEC_SA_AI_DVSEf, + /* lsp */ 27, + /* len */ 1 + }, + { /* name */ MACSEC_SA_AI_DVSf, + /* lsp */ 23, + /* len */ 4 + }, + { /* name */ MACSEC_SA_AI_LSf, + /* lsp */ 22, + /* len */ 1 + }, + { /* name */ MACSEC_SA_AI_DSf, + /* lsp */ 21, + /* len */ 1 + }, + { /* name */ MACSEC_SA_AI_SDf, + /* lsp */ 20, + /* len */ 1 + }, + { /* name */ MACSEC_SA_AI3_TEST1f, + /* lsp */ 19, + /* len */ 1 + }, + { /* name */ MACSEC_SA_AI2_TEST1f, + /* lsp */ 18, + /* len */ 1 + }, + { /* name */ MACSEC_SA_AI1_TEST1f, + /* lsp */ 17, + /* len */ 1 + }, + { /* name */ MACSEC_SA_AI0_TEST1f, + /* lsp */ 16, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 4 + }, + { /* name */ MACSEC_SA_AE_DVSEf, + /* lsp */ 11, + /* len */ 1 + }, + { /* name */ MACSEC_SA_AE_DVSf, + /* lsp */ 7, + /* len */ 4 + }, + { /* name */ MACSEC_SA_AE_LSf, + /* lsp */ 6, + /* len */ 1 + }, + { /* name */ MACSEC_SA_AE_DSf, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ MACSEC_SA_AE_SDf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ MACSEC_SA_AE3_TEST1f, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ MACSEC_SA_AE2_TEST1f, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ MACSEC_SA_AE1_TEST1f, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ MACSEC_SA_AE0_TEST1f, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t MACSEC_MBIST_STAT_AE_TEST_PORT6_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 26, + /* len */ 6 + }, + { /* name */ MACSEC_STAT_AI_DVSEf, + /* lsp */ 25, + /* len */ 1 + }, + { /* name */ MACSEC_STAT_AI_DVSf, + /* lsp */ 21, + /* len */ 4 + }, + { /* name */ MACSEC_STAT_AI_LSf, + /* lsp */ 20, + /* len */ 1 + }, + { /* name */ MACSEC_STAT_AI_DSf, + /* lsp */ 19, + /* len */ 1 + }, + { /* name */ MACSEC_STAT_AI_SDf, + /* lsp */ 18, + /* len */ 1 + }, + { /* name */ MACSEC_STAT_AI_TEST1f, + /* lsp */ 17, + /* len */ 1 + }, + { /* name */ MACSEC_STAT_AI_TESTRWMf, + /* lsp */ 16, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 10, + /* len */ 6 + }, + { /* name */ MACSEC_STAT_AE_DVSEf, + /* lsp */ 9, + /* len */ 1 + }, + { /* name */ MACSEC_STAT_AE_DVSf, + /* lsp */ 5, + /* len */ 4 + }, + { /* name */ MACSEC_STAT_AE_LSf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ MACSEC_STAT_AE_DSf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ MACSEC_STAT_AE_SDf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ MACSEC_STAT_AE_TEST1f, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ MACSEC_STAT_AE_TESTRWMf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t MACSEC_MBIST_SA_FAIL_PORT6_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 20, + /* len */ 12 + }, + { /* name */ BIST_FAIL_MACSEC_STAT_AEf, + /* lsp */ 19, + /* len */ 1 + }, + { /* name */ DRF_BIST_FAIL_MACSEC_STAT_AEf, + /* lsp */ 18, + /* len */ 1 + }, + { /* name */ BIST_FAIL_MACSEC_STAT_AIf, + /* lsp */ 17, + /* len */ 1 + }, + { /* name */ DRF_BIST_FAIL_MACSEC_STAT_AIf, + /* lsp */ 16, + /* len */ 1 + }, + { /* name */ BIST_FAIL_MACSEC_SA_AE3f, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ DRF_BIST_FAIL_MACSEC_SA_AE3f, + /* lsp */ 14, + /* len */ 1 + }, + { /* name */ BIST_FAIL_MACSEC_SA_AE2f, + /* lsp */ 13, + /* len */ 1 + }, + { /* name */ DRF_BIST_FAIL_MACSEC_SA_AE2f, + /* lsp */ 12, + /* len */ 1 + }, + { /* name */ BIST_FAIL_MACSEC_SA_AE1f, + /* lsp */ 11, + /* len */ 1 + }, + { /* name */ DRF_BIST_FAIL_MACSEC_SA_AE1f, + /* lsp */ 10, + /* len */ 1 + }, + { /* name */ BIST_FAIL_MACSEC_SA_AE0f, + /* lsp */ 9, + /* len */ 1 + }, + { /* name */ DRF_BIST_FAIL_MACSEC_SA_AE0f, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ BIST_FAIL_MACSEC_SA_AI3f, + /* lsp */ 7, + /* len */ 1 + }, + { /* name */ DRF_BIST_FAIL_MACSEC_SA_AI3f, + /* lsp */ 6, + /* len */ 1 + }, + { /* name */ BIST_FAIL_MACSEC_SA_AI2f, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ DRF_BIST_FAIL_MACSEC_SA_AI2f, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ BIST_FAIL_MACSEC_SA_AI1f, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ DRF_BIST_FAIL_MACSEC_SA_AI1f, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ BIST_FAIL_MACSEC_SA_AI0f, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ DRF_BIST_FAIL_MACSEC_SA_AI0f, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t MACSEC_XGLBK_FIFO_DBG_PORT6_FIELDS[] = +{ + { /* name */ CFG_WATER_LEVEL_STf, + /* lsp */ 28, + /* len */ 4 + }, + { /* name */ CFG_WATER_LEVEL_Hf, + /* lsp */ 24, + /* len */ 4 + }, + { /* name */ CFG_WATER_LEVEL_Lf, + /* lsp */ 20, + /* len */ 4 + }, + { /* name */ CFG_FAULT_ONf, + /* lsp */ 19, + /* len */ 1 + }, + { /* name */ CFG_ERROR_ONf, + /* lsp */ 18, + /* len */ 1 + }, + { /* name */ CFG_SEQ_RSV_ONf, + /* lsp */ 17, + /* len */ 1 + }, + { /* name */ CFG_CLR_FIFO_OVTHRf, + /* lsp */ 16, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 5, + /* len */ 11 + }, + { /* name */ XGLBK_FIFO_DBG_ENf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ XGLBK_FIFO_DBG_SELf, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t MACSEC_REG_RWDH_AE_PORT6_FIELDS[] = +{ + { /* name */ REG_DATA_AE_Lf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ REG_DATA_AE_Hf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_REG_ADDR_AE_PORT6_FIELDS[] = +{ + { /* name */ REG_ADDR_AEf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RESERVEDf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_REG_CMD_AE_PORT6_FIELDS[] = +{ + { /* name */ REG_DATA_AI_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RESERVEDf, + /* lsp */ 5, + /* len */ 11 + }, + { /* name */ REG_RD_REQ_AEf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 1, + /* len */ 3 + }, + { /* name */ REG_WR_REQ_AEf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t MACSEC_REG_RWDL_AI_PORT6_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ REG_DATA_AI_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_REG_ADDR_AI_PORT6_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 21, + /* len */ 11 + }, + { /* name */ REG_RD_REQ_AIf, + /* lsp */ 20, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 17, + /* len */ 3 + }, + { /* name */ REG_WR_REQ_AIf, + /* lsp */ 16, + /* len */ 1 + }, + { /* name */ REG_ADDR_AIf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_REG_RWD_PTP_PORT6_FIELDS[] = +{ + { /* name */ REG_ADDR_PTPf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ REG_DATA_PTPf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_REG_CMD_PTP_PORT6_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 5, + /* len */ 27 + }, + { /* name */ REG_RD_REQ_PTPf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 1, + /* len */ 3 + }, + { /* name */ REG_WR_REQ_PTPf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t UNUSED_005C_PORT6_FIELDS[] = +{ + { /* name */ UNUSED_005C_PORT6f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0060_PORT6_FIELDS[] = +{ + { /* name */ UNUSED_0060_PORT6f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0064_PORT6_FIELDS[] = +{ + { /* name */ UNUSED_0064_PORT6f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0068_PORT6_FIELDS[] = +{ + { /* name */ UNUSED_0068_PORT6f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_006C_PORT6_FIELDS[] = +{ + { /* name */ UNUSED_006C_PORT6f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0070_PORT6_FIELDS[] = +{ + { /* name */ UNUSED_0070_PORT6f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0074_PORT6_FIELDS[] = +{ + { /* name */ UNUSED_0074_PORT6f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t RESERVED_0078_PORT6_FIELDS[] = +{ + { /* name */ RESERVED_0078_PORT6f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t RESERVED_007C_PORT6_FIELDS[] = +{ + { /* name */ RESERVED_007C_PORT6f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t MACSEC_TXSYSCRCERR_CNT_PORT6_FIELDS[] = +{ + { /* name */ TXSYS_CRCERR_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TXSYS_CRCERR_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_TXSYSPKTERR_CNT_PORT6_FIELDS[] = +{ + { /* name */ TXSYS_PKTERR_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TXSYS_PKTERR_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_TXSYSOK_CNT_0_PORT6_FIELDS[] = +{ + { /* name */ TXSYS_OK_CNT_1f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TXSYS_OK_CNT_0f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_TXSYSOK_CNT_2_PORT6_FIELDS[] = +{ + { /* name */ TXSYS_OK_CNT_3f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TXSYS_OK_CNT_2f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_TXSYSGERR_CNT_PORT6_FIELDS[] = +{ + { /* name */ TXSYS_GERR_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TXSYS_GERR_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_TXSYSGLPIERR_CNT_PORT6_FIELDS[] = +{ + { /* name */ TXSYS_GLPIERR_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TXSYS_GLPIERR_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_TXSYS_DBG_PORT6_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 20, + /* len */ 12 + }, + { /* name */ TXSYS_XG2IP_FSMf, + /* lsp */ 16, + /* len */ 4 + }, + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 12 + }, + { /* name */ TXSYS_WRP2IP_FSMf, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t MACSEC_TX_RX_CNT_INCR_PORT6_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 28, + /* len */ 4 + }, + { /* name */ RXSYS_UNDERRUN_CNT_INCRf, + /* lsp */ 27, + /* len */ 1 + }, + { /* name */ RXSYS_DROP_CNT_INCRf, + /* lsp */ 26, + /* len */ 1 + }, + { /* name */ RXSYS_PKTERR_CNT_INCRf, + /* lsp */ 25, + /* len */ 1 + }, + { /* name */ RXSYS_CRCERR_CNT_INCRf, + /* lsp */ 24, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 19, + /* len */ 5 + }, + { /* name */ RXLINE_OVERFLOW_CNT_INCRf, + /* lsp */ 18, + /* len */ 1 + }, + { /* name */ RXLINE_PKTERR_CNT_INCRf, + /* lsp */ 17, + /* len */ 1 + }, + { /* name */ RXLINE_CRCERR_CNT_INCRf, + /* lsp */ 16, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 4 + }, + { /* name */ TXLINE_UNDERRUN_CNT_INCRf, + /* lsp */ 11, + /* len */ 1 + }, + { /* name */ TXLINE_DROP_CNT_INCRf, + /* lsp */ 10, + /* len */ 1 + }, + { /* name */ TXLINE_PKTERR_CNT_INCRf, + /* lsp */ 9, + /* len */ 1 + }, + { /* name */ TXLINE_CRCERR_CNT_INCRf, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 3, + /* len */ 5 + }, + { /* name */ TXSYS_OVERFLOW_CNT_INCRf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ TXSYS_PKTERR_CNT_INCRf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ TXSYS_CRCERR_CNT_INCRf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t MACSEC_TXLINECRCERR_CNT_PORT6_FIELDS[] = +{ + { /* name */ TXLINE_CRCERR_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TXLINE_CRCERR_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_TXLINEPKTERR_CNT_PORT6_FIELDS[] = +{ + { /* name */ TXLINE_PKTERR_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TXLINE_PKTERR_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_TXLINEOK_CNT_0_PORT6_FIELDS[] = +{ + { /* name */ TXLINE_OK_CNT_1f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TXLINE_OK_CNT_0f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_TXLINEOK_CNT_2_PORT6_FIELDS[] = +{ + { /* name */ TXLINE_OK_CNT_3f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TXLINE_OK_CNT_2f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_TXLINEDROP_CNT_PORT6_FIELDS[] = +{ + { /* name */ TXLINE_DROP_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TXLINE_DROP_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_TXLINESRT_CNT_PORT6_FIELDS[] = +{ + { /* name */ TXLINE_SRTPKT_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TXLINE_SRTPKT_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_TXLINEGERR_CNT_PORT6_FIELDS[] = +{ + { /* name */ TXLINE_GERR_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TXLINE_GERR_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_TXLINE_DBG_PORT6_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 21, + /* len */ 11 + }, + { /* name */ TXLINE_IP2XG_FSMf, + /* lsp */ 16, + /* len */ 5 + }, + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 12 + }, + { /* name */ TXLINE_IP2WRP_FSMf, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t MACSEC_RXLINECRCERR_CNT_PORT6_FIELDS[] = +{ + { /* name */ RXLINE_CRCERR_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXLINE_CRCERR_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXLINEPKTERR_CNT_PORT6_FIELDS[] = +{ + { /* name */ RXLINE_PKTERR_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXLINE_PKTERR_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXLINEOK_CNT_0_PORT6_FIELDS[] = +{ + { /* name */ RXLINE_OK_CNT_1f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXLINE_OK_CNT_0f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXLINEOK_CNT_2_PORT6_FIELDS[] = +{ + { /* name */ RXLINE_OK_CNT_3f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXLINE_OK_CNT_2f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXLINESRT_CNT_PORT6_FIELDS[] = +{ + { /* name */ RXLINE_SHORTPKT_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXLINE_SHORTPKT_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXLINEGERR_CNT_PORT6_FIELDS[] = +{ + { /* name */ RXLINE_GERR_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXLINE_GERR_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXLINEGLPIERR_CNT_PORT6_FIELDS[] = +{ + { /* name */ RXLINE_GLPIERR_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXLINE_GLPIERR_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXLINE_DBG_PORT6_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 20, + /* len */ 12 + }, + { /* name */ RXLINE_XG2IP_FSMf, + /* lsp */ 16, + /* len */ 4 + }, + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 12 + }, + { /* name */ RXLINE_WRP2IP_FSMf, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t MACSEC_RXSYSCRCERR_CNT_PORT6_FIELDS[] = +{ + { /* name */ RXSYS_CRCERR_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXSYS_CRCERR_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXSYSPKTERR_CNT_PORT6_FIELDS[] = +{ + { /* name */ RXSYS_PKTERR_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXSYS_PKTERR_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXSYSOK_CNT_0_PORT6_FIELDS[] = +{ + { /* name */ RXSYS_OK_CNT_1f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXSYS_OK_CNT_0f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXSYSOK_CNT_2_PORT6_FIELDS[] = +{ + { /* name */ RXSYS_OK_CNT_3f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXSYS_OK_CNT_2f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXSYSDROP_CNT_PORT6_FIELDS[] = +{ + { /* name */ RXSYS_DROP_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXSYS_DROP_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXSYSSRT_CNT_PORT6_FIELDS[] = +{ + { /* name */ RXSYS_DECRYPTSRT_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXSYS_DECRYPTSRT_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXSYSGERR_CNT_PORT6_FIELDS[] = +{ + { /* name */ RXSYS_GERR_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXSYS_GERR_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXSYS_DBG_PORT6_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 21, + /* len */ 11 + }, + { /* name */ RXSYS_IP2XG_FSMf, + /* lsp */ 16, + /* len */ 5 + }, + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 12 + }, + { /* name */ RXSYS_IP2WRP_FSMf, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t MACSEC_TXSYS_CFG1_PORT6_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 21, + /* len */ 11 + }, + { /* name */ TXSYS_XGMINIFGf, + /* lsp */ 16, + /* len */ 5 + }, + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 4 + }, + { /* name */ TXSYS_MINIFGf, + /* lsp */ 8, + /* len */ 4 + }, + { /* name */ RESERVEDf, + /* lsp */ 3, + /* len */ 5 + }, + { /* name */ TXSYS_PMBNUMf, + /* lsp */ 0, + /* len */ 3 + }, +}; + +rtk_regField_t MACSEC_TXSYS_PTPCFG_PORT6_FIELDS[] = +{ + { /* name */ TXSYS_OUTERVLAN1f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RESERVEDf, + /* lsp */ 14, + /* len */ 2 + }, + { /* name */ PTP_UDP_ENf, + /* lsp */ 13, + /* len */ 1 + }, + { /* name */ PTP_ETH_ENf, + /* lsp */ 12, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 9, + /* len */ 3 + }, + { /* name */ TXSYS_PTPCRYPT_ENf, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 6, + /* len */ 2 + }, + { /* name */ TXSYS_FLOWIDf, + /* lsp */ 0, + /* len */ 6 + }, +}; + +rtk_regField_t MACSEC_TXSYS_OUTERVLAN2_PORT6_FIELDS[] = +{ + { /* name */ TXSYS_OUTERVLAN3f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TXSYS_OUTERVLAN2f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_TXSYS_OUTERVLAN4_PORT6_FIELDS[] = +{ + { /* name */ TXSYS_INNERVLAN1f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TXSYS_OUTERVLAN4f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_TXSYS_INNERVLAN2_PORT6_FIELDS[] = +{ + { /* name */ TXSYS_INNERVLAN3f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TXSYS_INNERVLAN2f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_TXSYS_INNERVLAN4_PORT6_FIELDS[] = +{ + { /* name */ TXSYS_INNERVLAN5f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TXSYS_INNERVLAN4f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_TXSYS_INNERVLAN6_PORT6_FIELDS[] = +{ + { /* name */ TXSYS_INNERVLAN7f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TXSYS_INNERVLAN6f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t UNUSED_011C_PORT6_FIELDS[] = +{ + { /* name */ UNUSED_011C_PORT6f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0120_PORT6_FIELDS[] = +{ + { /* name */ UNUSED_0120_PORT6f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0124_PORT6_FIELDS[] = +{ + { /* name */ UNUSED_0124_PORT6f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0128_PORT6_FIELDS[] = +{ + { /* name */ UNUSED_0128_PORT6f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_012C_PORT6_FIELDS[] = +{ + { /* name */ UNUSED_012C_PORT6f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0130_PORT6_FIELDS[] = +{ + { /* name */ UNUSED_0130_PORT6f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0134_PORT6_FIELDS[] = +{ + { /* name */ UNUSED_0134_PORT6f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0138_PORT6_FIELDS[] = +{ + { /* name */ UNUSED_0138_PORT6f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_013C_PORT6_FIELDS[] = +{ + { /* name */ UNUSED_013C_PORT6f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t MACSEC_TXLINE_CFG1_PORT6_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 24, + /* len */ 8 + }, + { /* name */ TXLINE_WAIT_Tf, + /* lsp */ 16, + /* len */ 8 + }, + { /* name */ TXLINE_MINIFGf, + /* lsp */ 8, + /* len */ 8 + }, + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 4 + }, + { /* name */ TXLINE_PMBNUMf, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t MACSEC_TXLINE_CFG3_PORT6_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 24, + /* len */ 8 + }, + { /* name */ TXLINE_FIFO_TSHDf, + /* lsp */ 16, + /* len */ 8 + }, + { /* name */ RESERVEDf, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ TXLINE_PAD_VLAN_ENf, + /* lsp */ 14, + /* len */ 1 + }, + { /* name */ TXLINE_PAD_MACSEC_ENf, + /* lsp */ 13, + /* len */ 1 + }, + { /* name */ TXLINE_PAD_ENf, + /* lsp */ 12, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 9, + /* len */ 3 + }, + { /* name */ TXLINE_PKTERR_INVRSCRC_ENf, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 6, + /* len */ 2 + }, + { /* name */ TXLINE_GMIIER_INVRSCRC_ENf, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ TXLINE_CRCERR_INVRSCRC_ENf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 1, + /* len */ 3 + }, + { /* name */ TXLINE_CLASSDROP_ENf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t MACSEC_TXLINE_CFG5_PORT6_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 20, + /* len */ 12 + }, + { /* name */ TXLINE_AVG_IPGf, + /* lsp */ 16, + /* len */ 4 + }, + { /* name */ RESERVEDf, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ TXLIEN_LPIEXIT_Tf, + /* lsp */ 0, + /* len */ 15 + }, +}; + +rtk_regField_t UNUSED_014C_PORT6_FIELDS[] = +{ + { /* name */ UNUSED_014C_PORT6f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0150_PORT6_FIELDS[] = +{ + { /* name */ UNUSED_0150_PORT6f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0154_PORT6_FIELDS[] = +{ + { /* name */ UNUSED_0154_PORT6f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0158_PORT6_FIELDS[] = +{ + { /* name */ UNUSED_0158_PORT6f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_015C_PORT6_FIELDS[] = +{ + { /* name */ UNUSED_015C_PORT6f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0160_PORT6_FIELDS[] = +{ + { /* name */ UNUSED_0160_PORT6f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0164_PORT6_FIELDS[] = +{ + { /* name */ UNUSED_0164_PORT6f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0168_PORT6_FIELDS[] = +{ + { /* name */ UNUSED_0168_PORT6f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_016C_PORT6_FIELDS[] = +{ + { /* name */ UNUSED_016C_PORT6f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0170_PORT6_FIELDS[] = +{ + { /* name */ UNUSED_0170_PORT6f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0174_PORT6_FIELDS[] = +{ + { /* name */ UNUSED_0174_PORT6f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0178_PORT6_FIELDS[] = +{ + { /* name */ UNUSED_0178_PORT6f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_017C_PORT6_FIELDS[] = +{ + { /* name */ UNUSED_017C_PORT6f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t MACSEC_RXLINE_CFG1_PORT6_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 21, + /* len */ 11 + }, + { /* name */ RXLINE_XGMINIFGf, + /* lsp */ 16, + /* len */ 5 + }, + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 4 + }, + { /* name */ RXLINE_MINIPGf, + /* lsp */ 8, + /* len */ 4 + }, + { /* name */ RESERVEDf, + /* lsp */ 3, + /* len */ 5 + }, + { /* name */ RXLINE_PMBNUMf, + /* lsp */ 0, + /* len */ 3 + }, +}; + +rtk_regField_t UNUSED_0184_PORT6_FIELDS[] = +{ + { /* name */ UNUSED_0184_PORT6f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0188_PORT6_FIELDS[] = +{ + { /* name */ UNUSED_0188_PORT6f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_018C_PORT6_FIELDS[] = +{ + { /* name */ UNUSED_018C_PORT6f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0190_PORT6_FIELDS[] = +{ + { /* name */ UNUSED_0190_PORT6f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0194_PORT6_FIELDS[] = +{ + { /* name */ UNUSED_0194_PORT6f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0198_PORT6_FIELDS[] = +{ + { /* name */ UNUSED_0198_PORT6f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_019C_PORT6_FIELDS[] = +{ + { /* name */ UNUSED_019C_PORT6f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_01A0_PORT6_FIELDS[] = +{ + { /* name */ UNUSED_01A0_PORT6f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_01A4_PORT6_FIELDS[] = +{ + { /* name */ UNUSED_01A4_PORT6f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_01A8_PORT6_FIELDS[] = +{ + { /* name */ UNUSED_01A8_PORT6f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_01AC_PORT6_FIELDS[] = +{ + { /* name */ UNUSED_01AC_PORT6f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_01B0_PORT6_FIELDS[] = +{ + { /* name */ UNUSED_01B0_PORT6f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_01B4_PORT6_FIELDS[] = +{ + { /* name */ UNUSED_01B4_PORT6f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_01B8_PORT6_FIELDS[] = +{ + { /* name */ UNUSED_01B8_PORT6f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_01BC_PORT6_FIELDS[] = +{ + { /* name */ UNUSED_01BC_PORT6f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t MACSEC_RXSYS_CFG1_PORT6_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 24, + /* len */ 8 + }, + { /* name */ RXSYS_WAIT_Tf, + /* lsp */ 16, + /* len */ 8 + }, + { /* name */ RXSYS_MINIPGf, + /* lsp */ 8, + /* len */ 8 + }, + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 4 + }, + { /* name */ RXSYS_PMBNUMf, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t MACSEC_RXSYS_CFG3_PORT6_FIELDS[] = +{ + { /* name */ RXSYS_OUTERVLAN1f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RESERVEDf, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ RXSYS_PAD_VLAN_ENf, + /* lsp */ 14, + /* len */ 1 + }, + { /* name */ RXSYS_PAD_LINESRT_ENf, + /* lsp */ 13, + /* len */ 1 + }, + { /* name */ RXSYS_PAD_DECRYPTSRT_ENf, + /* lsp */ 12, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 9, + /* len */ 3 + }, + { /* name */ RXSYS_PKTERR_INVRSCRC_ENf, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 6, + /* len */ 2 + }, + { /* name */ RXSYS_GMIIER_INVRSCRC_ENf, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ RXSYS_CRCERR_INVRSCRC_ENf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 1, + /* len */ 3 + }, + { /* name */ RXSYS_CLASSDROP_ENf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t MACSEC_RXSYS_OUTERVLAN2_PORT6_FIELDS[] = +{ + { /* name */ RXSYS_OUTERVLAN3f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXSYS_OUTERVLAN2f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXSYS_OUTERVLAN4_PORT6_FIELDS[] = +{ + { /* name */ RXSYS_INNERVLAN1f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXSYS_OUTERVLAN4f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXSYS_INNERVLAN2_PORT6_FIELDS[] = +{ + { /* name */ RXSYS_INNERVLAN3f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXSYS_INNERVLAN2f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXSYS_INNERVLAN4_PORT6_FIELDS[] = +{ + { /* name */ RXSYS_INNERVLAN5f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXSYS_INNERVLAN4f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXSYS_INNERVLAN6_PORT6_FIELDS[] = +{ + { /* name */ RXSYS_INNERVLAN7f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXSYS_INNERVLAN6f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXSYS_CFG4_PORT6_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 31, + /* len */ 1 + }, + { /* name */ RXSYS_LPIEXIT_Tf, + /* lsp */ 16, + /* len */ 15 + }, + { /* name */ RXSYS_FIFO_FTUNEf, + /* lsp */ 8, + /* len */ 8 + }, + { /* name */ RXSYS_FIFO_TSHDf, + /* lsp */ 0, + /* len */ 8 + }, +}; + +rtk_regField_t MACSEC_RXSYS_CFG6_PORT6_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 28 + }, + { /* name */ RXSYS_AVG_IPGf, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t MACSEC_REG_GLB_SET1_PORT7_FIELDS[] = +{ + { /* name */ RX_GATINGf, + /* lsp */ 31, + /* len */ 1 + }, + { /* name */ TX_GATINGf, + /* lsp */ 30, + /* len */ 1 + }, + { /* name */ DBG_ENf, + /* lsp */ 29, + /* len */ 1 + }, + { /* name */ DBG_SELf, + /* lsp */ 24, + /* len */ 5 + }, + { /* name */ DBG_SPD_SELf, + /* lsp */ 23, + /* len */ 1 + }, + { /* name */ RX_G_IOSAMEPMBf, + /* lsp */ 22, + /* len */ 1 + }, + { /* name */ TX_G_IOSAMEPMBf, + /* lsp */ 21, + /* len */ 1 + }, + { /* name */ MIBCNT_MODEf, + /* lsp */ 20, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 19, + /* len */ 1 + }, + { /* name */ RX_XGDIC_ENf, + /* lsp */ 18, + /* len */ 1 + }, + { /* name */ TX_XGDIC_ENf, + /* lsp */ 17, + /* len */ 1 + }, + { /* name */ MIBCNT_SWRST_Nf, + /* lsp */ 16, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ PTPBYPASS_ENf, + /* lsp */ 14, + /* len */ 1 + }, + { /* name */ SYSLPBK_ENf, + /* lsp */ 13, + /* len */ 1 + }, + { /* name */ PHY2MAC_ENf, + /* lsp */ 12, + /* len */ 1 + }, + { /* name */ RX_IPRST_Nf, + /* lsp */ 11, + /* len */ 1 + }, + { /* name */ RX_IPBYPASS_ENf, + /* lsp */ 10, + /* len */ 1 + }, + { /* name */ RX_MACSECBYPASS_ENf, + /* lsp */ 9, + /* len */ 1 + }, + { /* name */ RX_SWRST_ENf, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 6, + /* len */ 2 + }, + { /* name */ LINELPBK_ENf, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ MAC2PHY_ENf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ TX_IPRST_Nf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ TX_IPBYPASS_ENf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ TX_MACSECBYPASS_ENf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ TX_SWRST_ENf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t MACSEC_REG_GLB_IMR_PORT7_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 20 + }, + { /* name */ RX_IPILOCK_XG_IMRf, + /* lsp */ 11, + /* len */ 1 + }, + { /* name */ RX_IPILOCK_IMRf, + /* lsp */ 10, + /* len */ 1 + }, + { /* name */ RX_IPISECFAIL_IMRf, + /* lsp */ 9, + /* len */ 1 + }, + { /* name */ RX_IPI_GLB_IMRf, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 4 + }, + { /* name */ TX_IPELOCK_XG_IMRf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ TX_IPELOCK_IMRf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ TX_IPESECFAIL_IMRf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ TX_IPE_GLB_IMRf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t MACSEC_REG_GLB_ISR_PORT7_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 20 + }, + { /* name */ RX_IPILOCK_XG_ISRf, + /* lsp */ 11, + /* len */ 1 + }, + { /* name */ RX_IPILOCK_ISRf, + /* lsp */ 10, + /* len */ 1 + }, + { /* name */ RX_IPISECFAIL_ISRf, + /* lsp */ 9, + /* len */ 1 + }, + { /* name */ RX_IPI_GLB_ISRf, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 4 + }, + { /* name */ TX_IPELOCK_XG_ISRf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ TX_IPELOCK_ISRf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ TX_IPESECFAIL_ISRf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ TX_IPE_GLB_ISRf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t UNUSED_000C_PORT7_FIELDS[] = +{ + { /* name */ UNUSED_000C_PORT7f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t MACSEC_PM_CTRL_PORT7_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 2, + /* len */ 30 + }, + { /* name */ MACSEC_RX_ICG_ENf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ MACSEC_TX_ICG_ENf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t MACSEC_REG_GLB_MASK_PORT7_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 30, + /* len */ 2 + }, + { /* name */ RX_MTUf, + /* lsp */ 24, + /* len */ 6 + }, + { /* name */ RESERVEDf, + /* lsp */ 22, + /* len */ 2 + }, + { /* name */ TX_MTUf, + /* lsp */ 16, + /* len */ 6 + }, + { /* name */ RESERVEDf, + /* lsp */ 13, + /* len */ 3 + }, + { /* name */ RX_XGMASKf, + /* lsp */ 12, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 9, + /* len */ 3 + }, + { /* name */ RXDV_GMASKf, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 5, + /* len */ 3 + }, + { /* name */ TX_XGMASKf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 1, + /* len */ 3 + }, + { /* name */ TXEN_GMASKf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t MACSEC_REG_GLB_SET4_PORT7_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 31, + /* len */ 1 + }, + { /* name */ TXMSKDELAY_VALf, + /* lsp */ 16, + /* len */ 15 + }, + { /* name */ RESERVEDf, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ RXMSKDELAY_VALf, + /* lsp */ 0, + /* len */ 15 + }, +}; + +rtk_regField_t MACSEC_REG_IP_PROBE_PORT7_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ PROBE_SEL_AEf, + /* lsp */ 8, + /* len */ 8 + }, + { /* name */ PROBE_SEL_AIf, + /* lsp */ 0, + /* len */ 8 + }, +}; + +rtk_regField_t UNUSED_0020_PORT7_FIELDS[] = +{ + { /* name */ UNUSED_0020_PORT7f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0024_PORT7_FIELDS[] = +{ + { /* name */ UNUSED_0024_PORT7f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t MACSEC_MBIST_SA_CTRL_PORT7_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 30, + /* len */ 2 + }, + { /* name */ BIST_MODE_MACSEC_SA_AEf, + /* lsp */ 29, + /* len */ 1 + }, + { /* name */ DRF_BIST_MODE_MACSEC_SA_AEf, + /* lsp */ 28, + /* len */ 1 + }, + { /* name */ BIST_RSTN_MACSEC_SA_AEf, + /* lsp */ 27, + /* len */ 1 + }, + { /* name */ BIST_LOOP_MODE_MACSEC_SA_AEf, + /* lsp */ 26, + /* len */ 1 + }, + { /* name */ DYN_READ_EN_MACSEC_SA_AEf, + /* lsp */ 25, + /* len */ 1 + }, + { /* name */ DRF_TESS_RESUME_MACSEC_SA_AEf, + /* lsp */ 24, + /* len */ 1 + }, + { /* name */ BIST_MODE_MACSEC_SA_AIf, + /* lsp */ 23, + /* len */ 1 + }, + { /* name */ DRF_BIST_MODE_MACSEC_SA_AIf, + /* lsp */ 22, + /* len */ 1 + }, + { /* name */ BIST_RSTN_MACSEC_SA_AIf, + /* lsp */ 21, + /* len */ 1 + }, + { /* name */ BIST_LOOP_MODE_MACSEC_SA_AIf, + /* lsp */ 20, + /* len */ 1 + }, + { /* name */ DYN_READ_EN_MACSEC_SA_AIf, + /* lsp */ 19, + /* len */ 1 + }, + { /* name */ DRF_TESS_RESUME_MACSEC_SA_AIf, + /* lsp */ 18, + /* len */ 1 + }, + { /* name */ MACSEC_SA_AE_ICG_ENf, + /* lsp */ 17, + /* len */ 1 + }, + { /* name */ MACSEC_SA_AI_ICG_ENf, + /* lsp */ 16, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_MBIST_STAT_CTRL_PORT7_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 28, + /* len */ 4 + }, + { /* name */ DRF_START_PAUSE_MACSEC_SA_AEf, + /* lsp */ 27, + /* len */ 1 + }, + { /* name */ BIST_DONE_MACSEC_SA_AEf, + /* lsp */ 26, + /* len */ 1 + }, + { /* name */ DRF_BIST_DONE_MACSEC_SA_AEf, + /* lsp */ 25, + /* len */ 1 + }, + { /* name */ DRF_START_PAUSE_MACSEC_SA_AIf, + /* lsp */ 24, + /* len */ 1 + }, + { /* name */ BIST_DONE_MACSEC_SA_AIf, + /* lsp */ 23, + /* len */ 1 + }, + { /* name */ DRF_BIST_DONE_MACSEC_SA_AIf, + /* lsp */ 22, + /* len */ 1 + }, + { /* name */ DRF_START_PAUSE_MACSEC_STAT_AEf, + /* lsp */ 21, + /* len */ 1 + }, + { /* name */ BIST_DONE_MACSEC_STAT_AEf, + /* lsp */ 20, + /* len */ 1 + }, + { /* name */ DRF_BIST_DONE_MACSEC_STAT_AEf, + /* lsp */ 19, + /* len */ 1 + }, + { /* name */ DRF_START_PAUSE_MACSEC_STAT_AIf, + /* lsp */ 18, + /* len */ 1 + }, + { /* name */ BIST_DONE_MACSEC_STAT_AIf, + /* lsp */ 17, + /* len */ 1 + }, + { /* name */ DRF_BIST_DONE_MACSEC_STAT_AIf, + /* lsp */ 16, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 14, + /* len */ 2 + }, + { /* name */ BIST_MODE_MACSEC_STAT_AEf, + /* lsp */ 13, + /* len */ 1 + }, + { /* name */ DRF_BIST_MODE_MACSEC_STAT_AEf, + /* lsp */ 12, + /* len */ 1 + }, + { /* name */ BIST_RSTN_MACSEC_STAT_AEf, + /* lsp */ 11, + /* len */ 1 + }, + { /* name */ BIST_LOOP_MODE_MACSEC_STAT_AEf, + /* lsp */ 10, + /* len */ 1 + }, + { /* name */ DYN_READ_EN_MACSEC_STAT_AEf, + /* lsp */ 9, + /* len */ 1 + }, + { /* name */ DRF_TESS_RESUME_MACSEC_STAT_AEf, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ BIST_MODE_MACSEC_STAT_AIf, + /* lsp */ 7, + /* len */ 1 + }, + { /* name */ DRF_BIST_MODE_MACSEC_STAT_AIf, + /* lsp */ 6, + /* len */ 1 + }, + { /* name */ BIST_RSTN_MACSEC_STAT_AIf, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ BIST_LOOP_MODE_MACSEC_STAT_AIf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ DYN_READ_EN_MACSEC_STAT_AIf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ DRF_TESS_RESUME_MACSEC_STAT_AIf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ MACSEC_STAT_AE_ICG_ENf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ MACSEC_STAT_AI_ICG_ENf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t MACSEC_MBIST_SA_AE_TEST_PORT7_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 28, + /* len */ 4 + }, + { /* name */ MACSEC_SA_AI_DVSEf, + /* lsp */ 27, + /* len */ 1 + }, + { /* name */ MACSEC_SA_AI_DVSf, + /* lsp */ 23, + /* len */ 4 + }, + { /* name */ MACSEC_SA_AI_LSf, + /* lsp */ 22, + /* len */ 1 + }, + { /* name */ MACSEC_SA_AI_DSf, + /* lsp */ 21, + /* len */ 1 + }, + { /* name */ MACSEC_SA_AI_SDf, + /* lsp */ 20, + /* len */ 1 + }, + { /* name */ MACSEC_SA_AI3_TEST1f, + /* lsp */ 19, + /* len */ 1 + }, + { /* name */ MACSEC_SA_AI2_TEST1f, + /* lsp */ 18, + /* len */ 1 + }, + { /* name */ MACSEC_SA_AI1_TEST1f, + /* lsp */ 17, + /* len */ 1 + }, + { /* name */ MACSEC_SA_AI0_TEST1f, + /* lsp */ 16, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 4 + }, + { /* name */ MACSEC_SA_AE_DVSEf, + /* lsp */ 11, + /* len */ 1 + }, + { /* name */ MACSEC_SA_AE_DVSf, + /* lsp */ 7, + /* len */ 4 + }, + { /* name */ MACSEC_SA_AE_LSf, + /* lsp */ 6, + /* len */ 1 + }, + { /* name */ MACSEC_SA_AE_DSf, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ MACSEC_SA_AE_SDf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ MACSEC_SA_AE3_TEST1f, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ MACSEC_SA_AE2_TEST1f, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ MACSEC_SA_AE1_TEST1f, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ MACSEC_SA_AE0_TEST1f, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t MACSEC_MBIST_STAT_AE_TEST_PORT7_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 26, + /* len */ 6 + }, + { /* name */ MACSEC_STAT_AI_DVSEf, + /* lsp */ 25, + /* len */ 1 + }, + { /* name */ MACSEC_STAT_AI_DVSf, + /* lsp */ 21, + /* len */ 4 + }, + { /* name */ MACSEC_STAT_AI_LSf, + /* lsp */ 20, + /* len */ 1 + }, + { /* name */ MACSEC_STAT_AI_DSf, + /* lsp */ 19, + /* len */ 1 + }, + { /* name */ MACSEC_STAT_AI_SDf, + /* lsp */ 18, + /* len */ 1 + }, + { /* name */ MACSEC_STAT_AI_TEST1f, + /* lsp */ 17, + /* len */ 1 + }, + { /* name */ MACSEC_STAT_AI_TESTRWMf, + /* lsp */ 16, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 10, + /* len */ 6 + }, + { /* name */ MACSEC_STAT_AE_DVSEf, + /* lsp */ 9, + /* len */ 1 + }, + { /* name */ MACSEC_STAT_AE_DVSf, + /* lsp */ 5, + /* len */ 4 + }, + { /* name */ MACSEC_STAT_AE_LSf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ MACSEC_STAT_AE_DSf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ MACSEC_STAT_AE_SDf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ MACSEC_STAT_AE_TEST1f, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ MACSEC_STAT_AE_TESTRWMf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t MACSEC_MBIST_SA_FAIL_PORT7_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 20, + /* len */ 12 + }, + { /* name */ BIST_FAIL_MACSEC_STAT_AEf, + /* lsp */ 19, + /* len */ 1 + }, + { /* name */ DRF_BIST_FAIL_MACSEC_STAT_AEf, + /* lsp */ 18, + /* len */ 1 + }, + { /* name */ BIST_FAIL_MACSEC_STAT_AIf, + /* lsp */ 17, + /* len */ 1 + }, + { /* name */ DRF_BIST_FAIL_MACSEC_STAT_AIf, + /* lsp */ 16, + /* len */ 1 + }, + { /* name */ BIST_FAIL_MACSEC_SA_AE3f, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ DRF_BIST_FAIL_MACSEC_SA_AE3f, + /* lsp */ 14, + /* len */ 1 + }, + { /* name */ BIST_FAIL_MACSEC_SA_AE2f, + /* lsp */ 13, + /* len */ 1 + }, + { /* name */ DRF_BIST_FAIL_MACSEC_SA_AE2f, + /* lsp */ 12, + /* len */ 1 + }, + { /* name */ BIST_FAIL_MACSEC_SA_AE1f, + /* lsp */ 11, + /* len */ 1 + }, + { /* name */ DRF_BIST_FAIL_MACSEC_SA_AE1f, + /* lsp */ 10, + /* len */ 1 + }, + { /* name */ BIST_FAIL_MACSEC_SA_AE0f, + /* lsp */ 9, + /* len */ 1 + }, + { /* name */ DRF_BIST_FAIL_MACSEC_SA_AE0f, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ BIST_FAIL_MACSEC_SA_AI3f, + /* lsp */ 7, + /* len */ 1 + }, + { /* name */ DRF_BIST_FAIL_MACSEC_SA_AI3f, + /* lsp */ 6, + /* len */ 1 + }, + { /* name */ BIST_FAIL_MACSEC_SA_AI2f, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ DRF_BIST_FAIL_MACSEC_SA_AI2f, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ BIST_FAIL_MACSEC_SA_AI1f, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ DRF_BIST_FAIL_MACSEC_SA_AI1f, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ BIST_FAIL_MACSEC_SA_AI0f, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ DRF_BIST_FAIL_MACSEC_SA_AI0f, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t MACSEC_XGLBK_FIFO_DBG_PORT7_FIELDS[] = +{ + { /* name */ CFG_WATER_LEVEL_STf, + /* lsp */ 28, + /* len */ 4 + }, + { /* name */ CFG_WATER_LEVEL_Hf, + /* lsp */ 24, + /* len */ 4 + }, + { /* name */ CFG_WATER_LEVEL_Lf, + /* lsp */ 20, + /* len */ 4 + }, + { /* name */ CFG_FAULT_ONf, + /* lsp */ 19, + /* len */ 1 + }, + { /* name */ CFG_ERROR_ONf, + /* lsp */ 18, + /* len */ 1 + }, + { /* name */ CFG_SEQ_RSV_ONf, + /* lsp */ 17, + /* len */ 1 + }, + { /* name */ CFG_CLR_FIFO_OVTHRf, + /* lsp */ 16, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 5, + /* len */ 11 + }, + { /* name */ XGLBK_FIFO_DBG_ENf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ XGLBK_FIFO_DBG_SELf, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t MACSEC_REG_RWDH_AE_PORT7_FIELDS[] = +{ + { /* name */ REG_DATA_AE_Lf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ REG_DATA_AE_Hf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_REG_ADDR_AE_PORT7_FIELDS[] = +{ + { /* name */ REG_ADDR_AEf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RESERVEDf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_REG_CMD_AE_PORT7_FIELDS[] = +{ + { /* name */ REG_DATA_AI_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RESERVEDf, + /* lsp */ 5, + /* len */ 11 + }, + { /* name */ REG_RD_REQ_AEf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 1, + /* len */ 3 + }, + { /* name */ REG_WR_REQ_AEf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t MACSEC_REG_RWDL_AI_PORT7_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ REG_DATA_AI_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_REG_ADDR_AI_PORT7_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 21, + /* len */ 11 + }, + { /* name */ REG_RD_REQ_AIf, + /* lsp */ 20, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 17, + /* len */ 3 + }, + { /* name */ REG_WR_REQ_AIf, + /* lsp */ 16, + /* len */ 1 + }, + { /* name */ REG_ADDR_AIf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_REG_RWD_PTP_PORT7_FIELDS[] = +{ + { /* name */ REG_ADDR_PTPf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ REG_DATA_PTPf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_REG_CMD_PTP_PORT7_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 5, + /* len */ 27 + }, + { /* name */ REG_RD_REQ_PTPf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 1, + /* len */ 3 + }, + { /* name */ REG_WR_REQ_PTPf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t UNUSED_005C_PORT7_FIELDS[] = +{ + { /* name */ UNUSED_005C_PORT7f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0060_PORT7_FIELDS[] = +{ + { /* name */ UNUSED_0060_PORT7f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0064_PORT7_FIELDS[] = +{ + { /* name */ UNUSED_0064_PORT7f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0068_PORT7_FIELDS[] = +{ + { /* name */ UNUSED_0068_PORT7f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_006C_PORT7_FIELDS[] = +{ + { /* name */ UNUSED_006C_PORT7f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0070_PORT7_FIELDS[] = +{ + { /* name */ UNUSED_0070_PORT7f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0074_PORT7_FIELDS[] = +{ + { /* name */ UNUSED_0074_PORT7f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t RESERVED_0078_PORT7_FIELDS[] = +{ + { /* name */ RESERVED_0078_PORT7f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t RESERVED_007C_PORT7_FIELDS[] = +{ + { /* name */ RESERVED_007C_PORT7f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t MACSEC_TXSYSCRCERR_CNT_PORT7_FIELDS[] = +{ + { /* name */ TXSYS_CRCERR_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TXSYS_CRCERR_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_TXSYSPKTERR_CNT_PORT7_FIELDS[] = +{ + { /* name */ TXSYS_PKTERR_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TXSYS_PKTERR_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_TXSYSOK_CNT_0_PORT7_FIELDS[] = +{ + { /* name */ TXSYS_OK_CNT_1f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TXSYS_OK_CNT_0f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_TXSYSOK_CNT_2_PORT7_FIELDS[] = +{ + { /* name */ TXSYS_OK_CNT_3f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TXSYS_OK_CNT_2f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_TXSYSGERR_CNT_PORT7_FIELDS[] = +{ + { /* name */ TXSYS_GERR_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TXSYS_GERR_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_TXSYSGLPIERR_CNT_PORT7_FIELDS[] = +{ + { /* name */ TXSYS_GLPIERR_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TXSYS_GLPIERR_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_TXSYS_DBG_PORT7_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 20, + /* len */ 12 + }, + { /* name */ TXSYS_XG2IP_FSMf, + /* lsp */ 16, + /* len */ 4 + }, + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 12 + }, + { /* name */ TXSYS_WRP2IP_FSMf, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t MACSEC_TX_RX_CNT_INCR_PORT7_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 28, + /* len */ 4 + }, + { /* name */ RXSYS_UNDERRUN_CNT_INCRf, + /* lsp */ 27, + /* len */ 1 + }, + { /* name */ RXSYS_DROP_CNT_INCRf, + /* lsp */ 26, + /* len */ 1 + }, + { /* name */ RXSYS_PKTERR_CNT_INCRf, + /* lsp */ 25, + /* len */ 1 + }, + { /* name */ RXSYS_CRCERR_CNT_INCRf, + /* lsp */ 24, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 19, + /* len */ 5 + }, + { /* name */ RXLINE_OVERFLOW_CNT_INCRf, + /* lsp */ 18, + /* len */ 1 + }, + { /* name */ RXLINE_PKTERR_CNT_INCRf, + /* lsp */ 17, + /* len */ 1 + }, + { /* name */ RXLINE_CRCERR_CNT_INCRf, + /* lsp */ 16, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 4 + }, + { /* name */ TXLINE_UNDERRUN_CNT_INCRf, + /* lsp */ 11, + /* len */ 1 + }, + { /* name */ TXLINE_DROP_CNT_INCRf, + /* lsp */ 10, + /* len */ 1 + }, + { /* name */ TXLINE_PKTERR_CNT_INCRf, + /* lsp */ 9, + /* len */ 1 + }, + { /* name */ TXLINE_CRCERR_CNT_INCRf, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 3, + /* len */ 5 + }, + { /* name */ TXSYS_OVERFLOW_CNT_INCRf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ TXSYS_PKTERR_CNT_INCRf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ TXSYS_CRCERR_CNT_INCRf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t MACSEC_TXLINECRCERR_CNT_PORT7_FIELDS[] = +{ + { /* name */ TXLINE_CRCERR_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TXLINE_CRCERR_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_TXLINEPKTERR_CNT_PORT7_FIELDS[] = +{ + { /* name */ TXLINE_PKTERR_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TXLINE_PKTERR_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_TXLINEOK_CNT_0_PORT7_FIELDS[] = +{ + { /* name */ TXLINE_OK_CNT_1f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TXLINE_OK_CNT_0f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_TXLINEOK_CNT_2_PORT7_FIELDS[] = +{ + { /* name */ TXLINE_OK_CNT_3f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TXLINE_OK_CNT_2f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_TXLINEDROP_CNT_PORT7_FIELDS[] = +{ + { /* name */ TXLINE_DROP_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TXLINE_DROP_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_TXLINESRT_CNT_PORT7_FIELDS[] = +{ + { /* name */ TXLINE_SRTPKT_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TXLINE_SRTPKT_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_TXLINEGERR_CNT_PORT7_FIELDS[] = +{ + { /* name */ TXLINE_GERR_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TXLINE_GERR_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_TXLINE_DBG_PORT7_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 21, + /* len */ 11 + }, + { /* name */ TXLINE_IP2XG_FSMf, + /* lsp */ 16, + /* len */ 5 + }, + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 12 + }, + { /* name */ TXLINE_IP2WRP_FSMf, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t MACSEC_RXLINECRCERR_CNT_PORT7_FIELDS[] = +{ + { /* name */ RXLINE_CRCERR_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXLINE_CRCERR_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXLINEPKTERR_CNT_PORT7_FIELDS[] = +{ + { /* name */ RXLINE_PKTERR_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXLINE_PKTERR_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXLINEOK_CNT_0_PORT7_FIELDS[] = +{ + { /* name */ RXLINE_OK_CNT_1f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXLINE_OK_CNT_0f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXLINEOK_CNT_2_PORT7_FIELDS[] = +{ + { /* name */ RXLINE_OK_CNT_3f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXLINE_OK_CNT_2f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXLINESRT_CNT_PORT7_FIELDS[] = +{ + { /* name */ RXLINE_SHORTPKT_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXLINE_SHORTPKT_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXLINEGERR_CNT_PORT7_FIELDS[] = +{ + { /* name */ RXLINE_GERR_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXLINE_GERR_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXLINEGLPIERR_CNT_PORT7_FIELDS[] = +{ + { /* name */ RXLINE_GLPIERR_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXLINE_GLPIERR_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXLINE_DBG_PORT7_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 20, + /* len */ 12 + }, + { /* name */ RXLINE_XG2IP_FSMf, + /* lsp */ 16, + /* len */ 4 + }, + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 12 + }, + { /* name */ RXLINE_WRP2IP_FSMf, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t MACSEC_RXSYSCRCERR_CNT_PORT7_FIELDS[] = +{ + { /* name */ RXSYS_CRCERR_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXSYS_CRCERR_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXSYSPKTERR_CNT_PORT7_FIELDS[] = +{ + { /* name */ RXSYS_PKTERR_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXSYS_PKTERR_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXSYSOK_CNT_0_PORT7_FIELDS[] = +{ + { /* name */ RXSYS_OK_CNT_1f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXSYS_OK_CNT_0f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXSYSOK_CNT_2_PORT7_FIELDS[] = +{ + { /* name */ RXSYS_OK_CNT_3f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXSYS_OK_CNT_2f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXSYSDROP_CNT_PORT7_FIELDS[] = +{ + { /* name */ RXSYS_DROP_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXSYS_DROP_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXSYSSRT_CNT_PORT7_FIELDS[] = +{ + { /* name */ RXSYS_DECRYPTSRT_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXSYS_DECRYPTSRT_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXSYSGERR_CNT_PORT7_FIELDS[] = +{ + { /* name */ RXSYS_GERR_CNT_Hf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXSYS_GERR_CNT_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXSYS_DBG_PORT7_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 21, + /* len */ 11 + }, + { /* name */ RXSYS_IP2XG_FSMf, + /* lsp */ 16, + /* len */ 5 + }, + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 12 + }, + { /* name */ RXSYS_IP2WRP_FSMf, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t MACSEC_TXSYS_CFG1_PORT7_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 21, + /* len */ 11 + }, + { /* name */ TXSYS_XGMINIFGf, + /* lsp */ 16, + /* len */ 5 + }, + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 4 + }, + { /* name */ TXSYS_MINIFGf, + /* lsp */ 8, + /* len */ 4 + }, + { /* name */ RESERVEDf, + /* lsp */ 3, + /* len */ 5 + }, + { /* name */ TXSYS_PMBNUMf, + /* lsp */ 0, + /* len */ 3 + }, +}; + +rtk_regField_t MACSEC_TXSYS_PTPCFG_PORT7_FIELDS[] = +{ + { /* name */ TXSYS_OUTERVLAN1f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RESERVEDf, + /* lsp */ 14, + /* len */ 2 + }, + { /* name */ PTP_UDP_ENf, + /* lsp */ 13, + /* len */ 1 + }, + { /* name */ PTP_ETH_ENf, + /* lsp */ 12, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 9, + /* len */ 3 + }, + { /* name */ TXSYS_PTPCRYPT_ENf, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 6, + /* len */ 2 + }, + { /* name */ TXSYS_FLOWIDf, + /* lsp */ 0, + /* len */ 6 + }, +}; + +rtk_regField_t MACSEC_TXSYS_OUTERVLAN2_PORT7_FIELDS[] = +{ + { /* name */ TXSYS_OUTERVLAN3f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TXSYS_OUTERVLAN2f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_TXSYS_OUTERVLAN4_PORT7_FIELDS[] = +{ + { /* name */ TXSYS_INNERVLAN1f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TXSYS_OUTERVLAN4f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_TXSYS_INNERVLAN2_PORT7_FIELDS[] = +{ + { /* name */ TXSYS_INNERVLAN3f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TXSYS_INNERVLAN2f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_TXSYS_INNERVLAN4_PORT7_FIELDS[] = +{ + { /* name */ TXSYS_INNERVLAN5f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TXSYS_INNERVLAN4f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_TXSYS_INNERVLAN6_PORT7_FIELDS[] = +{ + { /* name */ TXSYS_INNERVLAN7f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TXSYS_INNERVLAN6f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t UNUSED_011C_PORT7_FIELDS[] = +{ + { /* name */ UNUSED_011C_PORT7f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0120_PORT7_FIELDS[] = +{ + { /* name */ UNUSED_0120_PORT7f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0124_PORT7_FIELDS[] = +{ + { /* name */ UNUSED_0124_PORT7f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0128_PORT7_FIELDS[] = +{ + { /* name */ UNUSED_0128_PORT7f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_012C_PORT7_FIELDS[] = +{ + { /* name */ UNUSED_012C_PORT7f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0130_PORT7_FIELDS[] = +{ + { /* name */ UNUSED_0130_PORT7f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0134_PORT7_FIELDS[] = +{ + { /* name */ UNUSED_0134_PORT7f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0138_PORT7_FIELDS[] = +{ + { /* name */ UNUSED_0138_PORT7f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_013C_PORT7_FIELDS[] = +{ + { /* name */ UNUSED_013C_PORT7f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t MACSEC_TXLINE_CFG1_PORT7_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 24, + /* len */ 8 + }, + { /* name */ TXLINE_WAIT_Tf, + /* lsp */ 16, + /* len */ 8 + }, + { /* name */ TXLINE_MINIFGf, + /* lsp */ 8, + /* len */ 8 + }, + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 4 + }, + { /* name */ TXLINE_PMBNUMf, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t MACSEC_TXLINE_CFG3_PORT7_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 24, + /* len */ 8 + }, + { /* name */ TXLINE_FIFO_TSHDf, + /* lsp */ 16, + /* len */ 8 + }, + { /* name */ RESERVEDf, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ TXLINE_PAD_VLAN_ENf, + /* lsp */ 14, + /* len */ 1 + }, + { /* name */ TXLINE_PAD_MACSEC_ENf, + /* lsp */ 13, + /* len */ 1 + }, + { /* name */ TXLINE_PAD_ENf, + /* lsp */ 12, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 9, + /* len */ 3 + }, + { /* name */ TXLINE_PKTERR_INVRSCRC_ENf, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 6, + /* len */ 2 + }, + { /* name */ TXLINE_GMIIER_INVRSCRC_ENf, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ TXLINE_CRCERR_INVRSCRC_ENf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 1, + /* len */ 3 + }, + { /* name */ TXLINE_CLASSDROP_ENf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t MACSEC_TXLINE_CFG5_PORT7_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 20, + /* len */ 12 + }, + { /* name */ TXLINE_AVG_IPGf, + /* lsp */ 16, + /* len */ 4 + }, + { /* name */ RESERVEDf, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ TXLIEN_LPIEXIT_Tf, + /* lsp */ 0, + /* len */ 15 + }, +}; + +rtk_regField_t UNUSED_014C_PORT7_FIELDS[] = +{ + { /* name */ UNUSED_014C_PORT7f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0150_PORT7_FIELDS[] = +{ + { /* name */ UNUSED_0150_PORT7f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0154_PORT7_FIELDS[] = +{ + { /* name */ UNUSED_0154_PORT7f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0158_PORT7_FIELDS[] = +{ + { /* name */ UNUSED_0158_PORT7f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_015C_PORT7_FIELDS[] = +{ + { /* name */ UNUSED_015C_PORT7f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0160_PORT7_FIELDS[] = +{ + { /* name */ UNUSED_0160_PORT7f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0164_PORT7_FIELDS[] = +{ + { /* name */ UNUSED_0164_PORT7f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0168_PORT7_FIELDS[] = +{ + { /* name */ UNUSED_0168_PORT7f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_016C_PORT7_FIELDS[] = +{ + { /* name */ UNUSED_016C_PORT7f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0170_PORT7_FIELDS[] = +{ + { /* name */ UNUSED_0170_PORT7f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0174_PORT7_FIELDS[] = +{ + { /* name */ UNUSED_0174_PORT7f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0178_PORT7_FIELDS[] = +{ + { /* name */ UNUSED_0178_PORT7f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_017C_PORT7_FIELDS[] = +{ + { /* name */ UNUSED_017C_PORT7f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t MACSEC_RXLINE_CFG1_PORT7_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 21, + /* len */ 11 + }, + { /* name */ RXLINE_XGMINIFGf, + /* lsp */ 16, + /* len */ 5 + }, + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 4 + }, + { /* name */ RXLINE_MINIPGf, + /* lsp */ 8, + /* len */ 4 + }, + { /* name */ RESERVEDf, + /* lsp */ 3, + /* len */ 5 + }, + { /* name */ RXLINE_PMBNUMf, + /* lsp */ 0, + /* len */ 3 + }, +}; + +rtk_regField_t UNUSED_0184_PORT7_FIELDS[] = +{ + { /* name */ UNUSED_0184_PORT7f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0188_PORT7_FIELDS[] = +{ + { /* name */ UNUSED_0188_PORT7f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_018C_PORT7_FIELDS[] = +{ + { /* name */ UNUSED_018C_PORT7f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0190_PORT7_FIELDS[] = +{ + { /* name */ UNUSED_0190_PORT7f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0194_PORT7_FIELDS[] = +{ + { /* name */ UNUSED_0194_PORT7f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_0198_PORT7_FIELDS[] = +{ + { /* name */ UNUSED_0198_PORT7f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_019C_PORT7_FIELDS[] = +{ + { /* name */ UNUSED_019C_PORT7f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_01A0_PORT7_FIELDS[] = +{ + { /* name */ UNUSED_01A0_PORT7f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_01A4_PORT7_FIELDS[] = +{ + { /* name */ UNUSED_01A4_PORT7f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_01A8_PORT7_FIELDS[] = +{ + { /* name */ UNUSED_01A8_PORT7f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_01AC_PORT7_FIELDS[] = +{ + { /* name */ UNUSED_01AC_PORT7f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_01B0_PORT7_FIELDS[] = +{ + { /* name */ UNUSED_01B0_PORT7f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_01B4_PORT7_FIELDS[] = +{ + { /* name */ UNUSED_01B4_PORT7f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_01B8_PORT7_FIELDS[] = +{ + { /* name */ UNUSED_01B8_PORT7f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t UNUSED_01BC_PORT7_FIELDS[] = +{ + { /* name */ UNUSED_01BC_PORT7f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t MACSEC_RXSYS_CFG1_PORT7_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 24, + /* len */ 8 + }, + { /* name */ RXSYS_WAIT_Tf, + /* lsp */ 16, + /* len */ 8 + }, + { /* name */ RXSYS_MINIPGf, + /* lsp */ 8, + /* len */ 8 + }, + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 4 + }, + { /* name */ RXSYS_PMBNUMf, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t MACSEC_RXSYS_CFG3_PORT7_FIELDS[] = +{ + { /* name */ RXSYS_OUTERVLAN1f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RESERVEDf, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ RXSYS_PAD_VLAN_ENf, + /* lsp */ 14, + /* len */ 1 + }, + { /* name */ RXSYS_PAD_LINESRT_ENf, + /* lsp */ 13, + /* len */ 1 + }, + { /* name */ RXSYS_PAD_DECRYPTSRT_ENf, + /* lsp */ 12, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 9, + /* len */ 3 + }, + { /* name */ RXSYS_PKTERR_INVRSCRC_ENf, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 6, + /* len */ 2 + }, + { /* name */ RXSYS_GMIIER_INVRSCRC_ENf, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ RXSYS_CRCERR_INVRSCRC_ENf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 1, + /* len */ 3 + }, + { /* name */ RXSYS_CLASSDROP_ENf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t MACSEC_RXSYS_OUTERVLAN2_PORT7_FIELDS[] = +{ + { /* name */ RXSYS_OUTERVLAN3f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXSYS_OUTERVLAN2f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXSYS_OUTERVLAN4_PORT7_FIELDS[] = +{ + { /* name */ RXSYS_INNERVLAN1f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXSYS_OUTERVLAN4f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXSYS_INNERVLAN2_PORT7_FIELDS[] = +{ + { /* name */ RXSYS_INNERVLAN3f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXSYS_INNERVLAN2f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXSYS_INNERVLAN4_PORT7_FIELDS[] = +{ + { /* name */ RXSYS_INNERVLAN5f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXSYS_INNERVLAN4f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXSYS_INNERVLAN6_PORT7_FIELDS[] = +{ + { /* name */ RXSYS_INNERVLAN7f, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RXSYS_INNERVLAN6f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MACSEC_RXSYS_CFG4_PORT7_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 31, + /* len */ 1 + }, + { /* name */ RXSYS_LPIEXIT_Tf, + /* lsp */ 16, + /* len */ 15 + }, + { /* name */ RXSYS_FIFO_FTUNEf, + /* lsp */ 8, + /* len */ 8 + }, + { /* name */ RXSYS_FIFO_TSHDf, + /* lsp */ 0, + /* len */ 8 + }, +}; + +rtk_regField_t MACSEC_RXSYS_CFG6_PORT7_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 28 + }, + { /* name */ RXSYS_AVG_IPGf, + /* lsp */ 0, + /* len */ 4 + }, +}; + +/* Module: Power Saving */ +rtk_regField_t GATING_CLOCK0_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ LNKDN_CLK_GATE_FLAGf, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ ALLPORT_MASKf, + /* lsp */ 5, + /* len */ 10 + }, + { /* name */ LINKDOWN_TO_UPSf, + /* lsp */ 0, + /* len */ 5 + }, +}; + +rtk_regField_t GATING_CLOCK1_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 13, + /* len */ 19 + }, + { /* name */ SLOW_DOWN_PLL_ENf, + /* lsp */ 12, + /* len */ 1 + }, + { /* name */ SLOW_CLK_TG1_RATEf, + /* lsp */ 8, + /* len */ 4 + }, + { /* name */ RESERVEDf, + /* lsp */ 7, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 6, + /* len */ 1 + }, + { /* name */ MAC_GATCLK_ENf, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ ALE_GATCLK_ENf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ PKT_ENCAP_GATCLK_ENf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ PKT_PRS_GATCLK_ENf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ EGR_CTRL_GATCLK_ENf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ IGR_CTRL_GATCLK_ENf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t EEE_TX_Q_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 20, + /* len */ 12 + }, + { /* name */ LOW_Q_THRf, + /* lsp */ 8, + /* len */ 12 + }, + { /* name */ HIGH_Qf, + /* lsp */ 0, + /* len */ 8 + }, +}; + +rtk_regField_t EEE_TX_MINIFG_CTRL0_FIELDS[] = +{ + { /* name */ TX_LPI_MINIPG_GELITEf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TX_LPI_MINIPG_FEf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t EEE_TX_MINIFG_CTRL1_FIELDS[] = +{ + { /* name */ TX_LPI_MINIPG_2P5GLITEf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TX_LPI_MINIPG_GEf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t EEE_TX_MINIFG_CTRL2_FIELDS[] = +{ + { /* name */ TX_LPI_MINIPG_5GLITEf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TX_LPI_MINIPG_2P5Gf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t EEE_TX_MINIFG_CTRL3_FIELDS[] = +{ + { /* name */ TX_LPI_MINIPG_10GLITEf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TX_LPI_MINIPG_5Gf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t EEE_TX_MINIFG_CTRL4_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TX_LPI_MINIPG_10Gf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t EEE_TX_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 20 + }, + { /* name */ MULTIWAKE_PORTSf, + /* lsp */ 10, + /* len */ 2 + }, + { /* name */ MULTIWAKE_INTLVf, + /* lsp */ 8, + /* len */ 2 + }, + { /* name */ MULTIWAKE_TIME_UNITf, + /* lsp */ 6, + /* len */ 2 + }, + { /* name */ MULTIWAKE_ENf, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ LINK_UP_DELAYf, + /* lsp */ 3, + /* len */ 2 + }, + { /* name */ EN_FC_EFCTf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ REF_RXLPIf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ TX_WAKE_SELf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t EEE_TX_TIMER_100M_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 20, + /* len */ 12 + }, + { /* name */ LOW_Q_TX_DELAY_FEf, + /* lsp */ 8, + /* len */ 12 + }, + { /* name */ TX_WAKE_TIMER_FEf, + /* lsp */ 0, + /* len */ 8 + }, +}; + +rtk_regField_t EEE_TX_TIMER_GELITE_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 28, + /* len */ 4 + }, + { /* name */ LOW_Q_TX_DELAY_GELITEf, + /* lsp */ 16, + /* len */ 12 + }, + { /* name */ TX_PAUSE_WAKE_TIMER_GELITEf, + /* lsp */ 8, + /* len */ 8 + }, + { /* name */ TX_WAKE_TIMER_GELITEf, + /* lsp */ 0, + /* len */ 8 + }, +}; + +rtk_regField_t EEE_TX_TIMER_GIGA_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 28, + /* len */ 4 + }, + { /* name */ LOW_Q_TX_DELAY_GEf, + /* lsp */ 16, + /* len */ 12 + }, + { /* name */ TX_PAUSE_WAKE_TIMER_GEf, + /* lsp */ 8, + /* len */ 8 + }, + { /* name */ TX_WAKE_TIMER_GEf, + /* lsp */ 0, + /* len */ 8 + }, +}; + +rtk_regField_t EEE_TX_TIMER_2P5GLITE_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 20, + /* len */ 12 + }, + { /* name */ LOW_Q_TX_DELAY_2P5GLITEf, + /* lsp */ 8, + /* len */ 12 + }, + { /* name */ TX_WAKE_TIMER_2P5GLITEf, + /* lsp */ 0, + /* len */ 8 + }, +}; + +rtk_regField_t EEE_TX_TIMER_2P5G_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 20, + /* len */ 12 + }, + { /* name */ LOW_Q_TX_DELAY_2P5Gf, + /* lsp */ 8, + /* len */ 12 + }, + { /* name */ TX_WAKE_TIMER_2P5Gf, + /* lsp */ 0, + /* len */ 8 + }, +}; + +rtk_regField_t EEE_TX_TIMER_5GLITE_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 20, + /* len */ 12 + }, + { /* name */ LOW_Q_TX_DELAY_5GLITEf, + /* lsp */ 8, + /* len */ 12 + }, + { /* name */ TX_WAKE_TIMER_5GLITEf, + /* lsp */ 0, + /* len */ 8 + }, +}; + +rtk_regField_t EEE_TX_TIMER_5G_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 20, + /* len */ 12 + }, + { /* name */ LOW_Q_TX_DELAY_5Gf, + /* lsp */ 8, + /* len */ 12 + }, + { /* name */ TX_WAKE_TIMER_5Gf, + /* lsp */ 0, + /* len */ 8 + }, +}; + +rtk_regField_t EEE_TX_TIMER_10GLITE_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 20, + /* len */ 12 + }, + { /* name */ LOW_Q_TX_DELAY_10GLITEf, + /* lsp */ 8, + /* len */ 12 + }, + { /* name */ TX_WAKE_TIMER_10GLITEf, + /* lsp */ 0, + /* len */ 8 + }, +}; + +rtk_regField_t EEE_TX_TIMER_10G_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 20, + /* len */ 12 + }, + { /* name */ LOW_Q_TX_DELAY_10Gf, + /* lsp */ 8, + /* len */ 12 + }, + { /* name */ TX_WAKE_TIMER_10Gf, + /* lsp */ 0, + /* len */ 8 + }, +}; + +rtk_regField_t EEE_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 28 + }, + { /* name */ EEE_RX_STSf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ EEE_TX_STSf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ EEE_PORT_TX_ENf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ EEE_PORT_RX_ENf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t EEE_RX_GELITE_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 9, + /* len */ 23 + }, + { /* name */ WAIT_RX_INACTIVE_GELITEf, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ WAIT_RX_INACTIVE_TIMER_GELITEf, + /* lsp */ 0, + /* len */ 8 + }, +}; + +rtk_regField_t EEE_RX_GE_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 9, + /* len */ 23 + }, + { /* name */ WAIT_RX_INACTIVE_GEf, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ WAIT_RX_INACTIVE_TIMER_GEf, + /* lsp */ 0, + /* len */ 8 + }, +}; + +rtk_regField_t LPI_OPTION_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 2, + /* len */ 30 + }, + { /* name */ MAC8_LPI_OPTIONf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ MAC3_LPI_OPTIONf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +/* Module: RA */ +rtk_regField_t RA_FIFO_FUL_THR0_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 22, + /* len */ 10 + }, + { /* name */ RXFIFO_FULL_THf, + /* lsp */ 11, + /* len */ 11 + }, + { /* name */ TXFIFO_FULL_THf, + /* lsp */ 0, + /* len */ 11 + }, +}; + +rtk_regField_t RA_FIFO_EMPTY_THR0_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 11, + /* len */ 21 + }, + { /* name */ FIFO_EMPTY_THf, + /* lsp */ 0, + /* len */ 11 + }, +}; + +rtk_regField_t RA_TX_STATUS0_FIELDS[] = +{ + { /* name */ H2E_TX_STATUSf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t RA_RX_STATUS0_FIELDS[] = +{ + { /* name */ H2E_RX_STATUSf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t RA_HSG_IFG0_FIELDS[] = +{ + { /* name */ HSG_XGMI_RX_IFGf, + /* lsp */ 24, + /* len */ 8 + }, + { /* name */ HSG_XGMI_TX_IFGf, + /* lsp */ 16, + /* len */ 8 + }, + { /* name */ HSG_GMI_RX_IFGf, + /* lsp */ 8, + /* len */ 8 + }, + { /* name */ HSG_GMI_TX_IFGf, + /* lsp */ 0, + /* len */ 8 + }, +}; + +rtk_regField_t RA_MACSEC_ETH0_FIELDS[] = +{ + { /* name */ MACSEC_ETHf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t RA_MACSEC_VLAN0_FIELDS[] = +{ + { /* name */ MACSEC_VLANf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t RA_MACSEC_IFG_CTRL0_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 28 + }, + { /* name */ RG_H2E_MACSEC_IFG_ENf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ MACSEC_IFG_SELf, + /* lsp */ 0, + /* len */ 3 + }, +}; + +rtk_regField_t RA_PAUSE_CTRL0_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 51, + /* len */ 13 + }, + { /* name */ RG_PAUSE_ACCEPT_MAC_SAf, + /* lsp */ 50, + /* len */ 1 + }, + { /* name */ RG_SDS_PAUSE_DECT_ENf, + /* lsp */ 49, + /* len */ 1 + }, + { /* name */ RG_ETH_PAUSE_DECT_ENf, + /* lsp */ 48, + /* len */ 1 + }, + { /* name */ RG_H2E_MAC_SA_Hf, + /* lsp */ 32, + /* len */ 16 + }, + { /* name */ RG_H2E_MAC_SA_Lf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t RA_GLB_CTRL0_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 5, + /* len */ 27 + }, + { /* name */ RG_PRMB_NUMf, + /* lsp */ 2, + /* len */ 3 + }, + { /* name */ RG_H2E_ENABLEf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ RG_H2E_BYPASS_MODEf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t RA_PADDING_CTRL0_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 3, + /* len */ 29 + }, + { /* name */ RG_H2E_PADDING_VLANf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ RG_H2E_PADDING_MACSECf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ RG_H2E_PADDING_ENf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t RA_SLOT_TIME0_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ SLOT_TIMEf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t RA_SOFT_RST0_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 1, + /* len */ 31 + }, + { /* name */ RSTf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t RA_FIFO_FUL_THR1_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 22, + /* len */ 10 + }, + { /* name */ RXFIFO_FULL_THf, + /* lsp */ 11, + /* len */ 11 + }, + { /* name */ TXFIFO_FULL_THf, + /* lsp */ 0, + /* len */ 11 + }, +}; + +rtk_regField_t RA_FIFO_EMPTY_THR1_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 11, + /* len */ 21 + }, + { /* name */ FIFO_EMPTY_THf, + /* lsp */ 0, + /* len */ 11 + }, +}; + +rtk_regField_t RA_TX_STATUS1_FIELDS[] = +{ + { /* name */ H2E_TX_STATUSf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t RA_RX_STATUS1_FIELDS[] = +{ + { /* name */ H2E_RX_STATUSf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t RA_HSG_IFG1_FIELDS[] = +{ + { /* name */ HSG_XGMI_RX_IFGf, + /* lsp */ 24, + /* len */ 8 + }, + { /* name */ HSG_XGMI_TX_IFGf, + /* lsp */ 16, + /* len */ 8 + }, + { /* name */ HSG_GMI_RX_IFGf, + /* lsp */ 8, + /* len */ 8 + }, + { /* name */ HSG_GMI_TX_IFGf, + /* lsp */ 0, + /* len */ 8 + }, +}; + +rtk_regField_t RA_MACSEC_ETH1_FIELDS[] = +{ + { /* name */ MACSEC_ETHf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t RA_MACSEC_VLAN1_FIELDS[] = +{ + { /* name */ MACSEC_VLANf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t RA_MACSEC_IFG_CTRL1_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 28 + }, + { /* name */ RG_H2E_MACSEC_IFG_ENf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ MACSEC_IFG_SELf, + /* lsp */ 0, + /* len */ 3 + }, +}; + +rtk_regField_t RA_PAUSE_CTRL1_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 51, + /* len */ 13 + }, + { /* name */ RG_PAUSE_ACCEPT_MAC_SAf, + /* lsp */ 50, + /* len */ 1 + }, + { /* name */ RG_SDS_PAUSE_DECT_ENf, + /* lsp */ 49, + /* len */ 1 + }, + { /* name */ RG_ETH_PAUSE_DECT_ENf, + /* lsp */ 48, + /* len */ 1 + }, + { /* name */ RG_H2E_MAC_SA_Hf, + /* lsp */ 32, + /* len */ 16 + }, + { /* name */ RG_H2E_MAC_SA_Lf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t RA_GLB_CTRL1_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 5, + /* len */ 27 + }, + { /* name */ RG_PRMB_NUMf, + /* lsp */ 2, + /* len */ 3 + }, + { /* name */ RG_H2E_ENABLEf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ RG_H2E_BYPASS_MODEf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t RA_PADDING_CTRL1_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 3, + /* len */ 29 + }, + { /* name */ RG_H2E_PADDING_VLANf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ RG_H2E_PADDING_MACSECf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ RG_H2E_PADDING_ENf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t RA_SLOT_TIME1_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ SLOT_TIMEf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t RA_SOFT_RST1_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 1, + /* len */ 31 + }, + { /* name */ RSTf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t RA_FIFO_FUL_THR2_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 22, + /* len */ 10 + }, + { /* name */ RXFIFO_FULL_THf, + /* lsp */ 11, + /* len */ 11 + }, + { /* name */ TXFIFO_FULL_THf, + /* lsp */ 0, + /* len */ 11 + }, +}; + +rtk_regField_t RA_FIFO_EMPTY_THR2_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 11, + /* len */ 21 + }, + { /* name */ FIFO_EMPTY_THf, + /* lsp */ 0, + /* len */ 11 + }, +}; + +rtk_regField_t RA_TX_STATUS2_FIELDS[] = +{ + { /* name */ H2E_TX_STATUSf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t RA_RX_STATUS2_FIELDS[] = +{ + { /* name */ H2E_RX_STATUSf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t RA_HSG_IFG2_FIELDS[] = +{ + { /* name */ HSG_XGMI_RX_IFGf, + /* lsp */ 24, + /* len */ 8 + }, + { /* name */ HSG_XGMI_TX_IFGf, + /* lsp */ 16, + /* len */ 8 + }, + { /* name */ HSG_GMI_RX_IFGf, + /* lsp */ 8, + /* len */ 8 + }, + { /* name */ HSG_GMI_TX_IFGf, + /* lsp */ 0, + /* len */ 8 + }, +}; + +rtk_regField_t RA_MACSEC_ETH2_FIELDS[] = +{ + { /* name */ MACSEC_ETHf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t RA_MACSEC_VLAN2_FIELDS[] = +{ + { /* name */ MACSEC_VLANf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t RA_MACSEC_IFG_CTRL2_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 28 + }, + { /* name */ RG_H2E_MACSEC_IFG_ENf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ MACSEC_IFG_SELf, + /* lsp */ 0, + /* len */ 3 + }, +}; + +rtk_regField_t RA_PAUSE_CTRL2_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 51, + /* len */ 13 + }, + { /* name */ RG_PAUSE_ACCEPT_MAC_SAf, + /* lsp */ 50, + /* len */ 1 + }, + { /* name */ RG_SDS_PAUSE_DECT_ENf, + /* lsp */ 49, + /* len */ 1 + }, + { /* name */ RG_ETH_PAUSE_DECT_ENf, + /* lsp */ 48, + /* len */ 1 + }, + { /* name */ RG_H2E_MAC_SA_Hf, + /* lsp */ 32, + /* len */ 16 + }, + { /* name */ RG_H2E_MAC_SA_Lf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t RA_GLB_CTRL2_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 5, + /* len */ 27 + }, + { /* name */ RG_PRMB_NUMf, + /* lsp */ 2, + /* len */ 3 + }, + { /* name */ RG_H2E_ENABLEf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ RG_H2E_BYPASS_MODEf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t RA_PADDING_CTRL2_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 3, + /* len */ 29 + }, + { /* name */ RG_H2E_PADDING_VLANf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ RG_H2E_PADDING_MACSECf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ RG_H2E_PADDING_ENf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t RA_SLOT_TIME2_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ SLOT_TIMEf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t RA_SOFT_RST2_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 1, + /* len */ 31 + }, + { /* name */ RSTf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t RA_FIFO_FUL_THR3_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 22, + /* len */ 10 + }, + { /* name */ RXFIFO_FULL_THf, + /* lsp */ 11, + /* len */ 11 + }, + { /* name */ TXFIFO_FULL_THf, + /* lsp */ 0, + /* len */ 11 + }, +}; + +rtk_regField_t RA_FIFO_EMPTY_THR3_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 11, + /* len */ 21 + }, + { /* name */ FIFO_EMPTY_THf, + /* lsp */ 0, + /* len */ 11 + }, +}; + +rtk_regField_t RA_TX_STATUS3_FIELDS[] = +{ + { /* name */ H2E_TX_STATUSf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t RA_RX_STATUS3_FIELDS[] = +{ + { /* name */ H2E_RX_STATUSf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t RA_HSG_IFG3_FIELDS[] = +{ + { /* name */ HSG_XGMI_RX_IFGf, + /* lsp */ 24, + /* len */ 8 + }, + { /* name */ HSG_XGMI_TX_IFGf, + /* lsp */ 16, + /* len */ 8 + }, + { /* name */ HSG_GMI_RX_IFGf, + /* lsp */ 8, + /* len */ 8 + }, + { /* name */ HSG_GMI_TX_IFGf, + /* lsp */ 0, + /* len */ 8 + }, +}; + +rtk_regField_t RA_MACSEC_ETH3_FIELDS[] = +{ + { /* name */ MACSEC_ETHf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t RA_MACSEC_VLAN3_FIELDS[] = +{ + { /* name */ MACSEC_VLANf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t RA_MACSEC_IFG_CTRL3_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 28 + }, + { /* name */ RG_H2E_MACSEC_IFG_ENf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ MACSEC_IFG_SELf, + /* lsp */ 0, + /* len */ 3 + }, +}; + +rtk_regField_t RA_PAUSE_CTRL3_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 51, + /* len */ 13 + }, + { /* name */ RG_PAUSE_ACCEPT_MAC_SAf, + /* lsp */ 50, + /* len */ 1 + }, + { /* name */ RG_SDS_PAUSE_DECT_ENf, + /* lsp */ 49, + /* len */ 1 + }, + { /* name */ RG_ETH_PAUSE_DECT_ENf, + /* lsp */ 48, + /* len */ 1 + }, + { /* name */ RG_H2E_MAC_SA_Hf, + /* lsp */ 32, + /* len */ 16 + }, + { /* name */ RG_H2E_MAC_SA_Lf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t RA_GLB_CTRL3_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 5, + /* len */ 27 + }, + { /* name */ RG_PRMB_NUMf, + /* lsp */ 2, + /* len */ 3 + }, + { /* name */ RG_H2E_ENABLEf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ RG_H2E_BYPASS_MODEf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t RA_PADDING_CTRL3_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 3, + /* len */ 29 + }, + { /* name */ RG_H2E_PADDING_VLANf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ RG_H2E_PADDING_MACSECf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ RG_H2E_PADDING_ENf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t RA_SLOT_TIME3_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ SLOT_TIMEf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t RA_SOFT_RST3_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 1, + /* len */ 31 + }, + { /* name */ RSTf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +/* Module: NIC */ +rtk_regField_t NIC_BUFFSIZE_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 11, + /* len */ 21 + }, + { /* name */ TXSTOP_ADDRf, + /* lsp */ 0, + /* len */ 11 + }, +}; + +rtk_regField_t NIC_RXBUFF_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 11, + /* len */ 21 + }, + { /* name */ RXSTOP_ADDRf, + /* lsp */ 0, + /* len */ 11 + }, +}; + +rtk_regField_t NIC_RXCMD_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 1, + /* len */ 31 + }, + { /* name */ FLAGf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t NIC_TXCMD_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 1, + /* len */ 31 + }, + { /* name */ FLAGf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t NIC_INT_STS_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 2, + /* len */ 30 + }, + { /* name */ RXISf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ TXESf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t NIC_INT_MSK_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 2, + /* len */ 30 + }, + { /* name */ RXIEf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ TXEEf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t NIC_RX_CTRL_FIELDS[] = +{ + { /* name */ RXFSTf, + /* lsp */ 24, + /* len */ 8 + }, + { /* name */ RESERVEDf, + /* lsp */ 19, + /* len */ 5 + }, + { /* name */ RXPADf, + /* lsp */ 18, + /* len */ 1 + }, + { /* name */ RXMTUf, + /* lsp */ 16, + /* len */ 2 + }, + { /* name */ HFMPEf, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ HFPPEf, + /* lsp */ 14, + /* len */ 1 + }, + { /* name */ RXAPEf, + /* lsp */ 13, + /* len */ 1 + }, + { /* name */ ARPPEf, + /* lsp */ 12, + /* len */ 1 + }, + { /* name */ RXBPEf, + /* lsp */ 11, + /* len */ 1 + }, + { /* name */ RXMPEf, + /* lsp */ 10, + /* len */ 1 + }, + { /* name */ RXPPSf, + /* lsp */ 8, + /* len */ 2 + }, + { /* name */ RESERVEDf, + /* lsp */ 5, + /* len */ 3 + }, + { /* name */ RL4CEPEf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ RL3CEPEf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ RCRCEPEf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ RMCRC_ENf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ RX_ENf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t NIC_TX_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 2, + /* len */ 30 + }, + { /* name */ LOOPBACK_ENf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ TX_ENf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t NIC_MC_HASH_TBL_FIELDS[] = +{ + { /* name */ HF_VALf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t NIC_UC_HASH_TBL_FIELDS[] = +{ + { /* name */ HF_VALf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t NIC_RX_BUFF_DATA_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 14, + /* len */ 18 + }, + { /* name */ LENf, + /* lsp */ 0, + /* len */ 14 + }, +}; + +rtk_regField_t NIC_RX_CURR_PKT_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 11, + /* len */ 21 + }, + { /* name */ ADDRf, + /* lsp */ 0, + /* len */ 11 + }, +}; + +rtk_regField_t CPU_RX_CURR_PKT_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 11, + /* len */ 21 + }, + { /* name */ ADDRf, + /* lsp */ 0, + /* len */ 11 + }, +}; + +rtk_regField_t NIC_TX_BUFF_AVAIL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 11, + /* len */ 21 + }, + { /* name */ FREE_SPACEf, + /* lsp */ 0, + /* len */ 11 + }, +}; + +rtk_regField_t NIC_TX_CURR_PKT_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 11, + /* len */ 21 + }, + { /* name */ ADDRf, + /* lsp */ 0, + /* len */ 11 + }, +}; + +rtk_regField_t NIC_TX_CURR_UNIT_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 11, + /* len */ 21 + }, + { /* name */ ADDRf, + /* lsp */ 0, + /* len */ 11 + }, +}; + +rtk_regField_t NIC_TX_PKT_INFO_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 14, + /* len */ 18 + }, + { /* name */ LENf, + /* lsp */ 0, + /* len */ 14 + }, +}; + +rtk_regField_t CPU_TX_CURR_PKT_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 11, + /* len */ 21 + }, + { /* name */ ADDRf, + /* lsp */ 0, + /* len */ 11 + }, +}; + +rtk_regField_t DMY_REG0_NIC_FIELDS[] = +{ + { /* name */ DUMMY_REG0_NICf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t DMY_REG1_NIC_FIELDS[] = +{ + { /* name */ DUMMY_REG1_NICf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +/* Module: Cpu Tag */ +rtk_regField_t CPU_TAG_TPID_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TPIDf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t CPU_TAG_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 20 + }, + { /* name */ EXT_CPUTAG_INSERTMODf, + /* lsp */ 10, + /* len */ 2 + }, + { /* name */ INT_CPUTAG_INSERTMODf, + /* lsp */ 8, + /* len */ 2 + }, + { /* name */ RESERVEDf, + /* lsp */ 2, + /* len */ 6 + }, + { /* name */ EXT_CPUTAG_ENf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ INT_CPUTAG_ENf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t EXT_CPU_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 28 + }, + { /* name */ PORTf, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t CPU_TAG_AWARE_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 10, + /* len */ 22 + }, + { /* name */ PMSKf, + /* lsp */ 0, + /* len */ 10 + }, +}; + +/* Module: Table Access */ +rtk_regField_t ITA_CTRL0_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 29, + /* len */ 3 + }, + { /* name */ TBL_ADDRf, + /* lsp */ 16, + /* len */ 13 + }, + { /* name */ RESERVEDf, + /* lsp */ 11, + /* len */ 5 + }, + { /* name */ TLB_TYPEf, + /* lsp */ 8, + /* len */ 3 + }, + { /* name */ RESERVEDf, + /* lsp */ 2, + /* len */ 6 + }, + { /* name */ TLB_ACTf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ TLB_EXECUTEf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t ITA_L2_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 23, + /* len */ 9 + }, + { /* name */ PORT_NUMf, + /* lsp */ 19, + /* len */ 4 + }, + { /* name */ ENTRY_CLRf, + /* lsp */ 18, + /* len */ 1 + }, + { /* name */ READ_MTHDf, + /* lsp */ 14, + /* len */ 4 + }, + { /* name */ TBL_TYPEf, + /* lsp */ 13, + /* len */ 1 + }, + { /* name */ ACT_STSf, + /* lsp */ 12, + /* len */ 1 + }, + { /* name */ TBL_ADDRf, + /* lsp */ 0, + /* len */ 12 + }, +}; + +rtk_regField_t ITA_HSAB_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 17, + /* len */ 15 + }, + { /* name */ LATCH_ALWAYSf, + /* lsp */ 16, + /* len */ 1 + }, + { /* name */ LATCH_FIRSTf, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ SPA_ENf, + /* lsp */ 14, + /* len */ 1 + }, + { /* name */ FORWARD_ENf, + /* lsp */ 13, + /* len */ 1 + }, + { /* name */ REASON_ENf, + /* lsp */ 12, + /* len */ 1 + }, + { /* name */ SPAf, + /* lsp */ 8, + /* len */ 4 + }, + { /* name */ FORWARDf, + /* lsp */ 6, + /* len */ 2 + }, + { /* name */ REASONf, + /* lsp */ 0, + /* len */ 6 + }, +}; + +rtk_regField_t ITA_WRITE_DATA0_FIELDS[] = +{ + { /* name */ WRITE_DATAf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t ITA_READ_DATA0_FIELDS[] = +{ + { /* name */ READ_DATAf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t TEST_MODE_ALE_HSA_MULTI_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 13, + /* len */ 19 + }, + { /* name */ CNTf, + /* lsp */ 2, + /* len */ 11 + }, + { /* name */ CNT_RSTf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ ENf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t TBL_ACCESS_HSA_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 14, + /* len */ 18 + }, + { /* name */ EXECf, + /* lsp */ 13, + /* len */ 1 + }, + { /* name */ CMDf, + /* lsp */ 12, + /* len */ 1 + }, + { /* name */ TBLf, + /* lsp */ 11, + /* len */ 1 + }, + { /* name */ ADDRf, + /* lsp */ 0, + /* len */ 11 + }, +}; + +rtk_regField_t TBL_ACCESS_HSA_DATA_FIELDS[] = +{ + { /* name */ DATAf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +/* Module: 8051 */ +rtk_regField_t DW8051_CFG_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 13, + /* len */ 19 + }, + { /* name */ NIC_ENf, + /* lsp */ 12, + /* len */ 1 + }, + { /* name */ CPUIDL_EXTf, + /* lsp */ 11, + /* len */ 1 + }, + { /* name */ CPUIDL_ENRf, + /* lsp */ 10, + /* len */ 1 + }, + { /* name */ VIAROM_WRITE_ENf, + /* lsp */ 9, + /* len */ 1 + }, + { /* name */ SPIF_CK2f, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ RRCP_MDOEf, + /* lsp */ 7, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 6, + /* len */ 1 + }, + { /* name */ DW8051_RATEf, + /* lsp */ 4, + /* len */ 2 + }, + { /* name */ IROM_MSBf, + /* lsp */ 2, + /* len */ 2 + }, + { /* name */ ACS_IROM_ENABLEf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ DW8051_READYf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t DW8051_IROM_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 8, + /* len */ 24 + }, + { /* name */ IROM_DATAf, + /* lsp */ 0, + /* len */ 8 + }, +}; + +/* Module: 802.1Q VLAN */ +rtk_regField_t VLAN_PORT_AFT_FIELDS[] = +{ + { /* name */ CTAG_ACCEPT_TYPEf, + /* lsp */ 0, + /* len */ 2 + }, +}; + +rtk_regField_t VLAN_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 28 + }, + { /* name */ TABLE_RSTf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ CVLAN_FILTERf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ VID4095_TYPEf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ VID0_TYPEf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t VLAN_PORT_IGR_FLTR_FIELDS[] = +{ + { /* name */ IGR_FLTR_ACTf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t VLAN_PORT_PB_VLAN_FIELDS[] = +{ + { /* name */ PVIDf, + /* lsp */ 0, + /* len */ 12 + }, +}; + +rtk_regField_t VLAN_PORT_EGR_TRANS_FIELDS[] = +{ + { /* name */ PMSKf, + /* lsp */ 0, + /* len */ 10 + }, +}; + +rtk_regField_t VLAN_PORT_EGR_KEEP_FIELDS[] = +{ + { /* name */ PMSKf, + /* lsp */ 0, + /* len */ 10 + }, +}; + +rtk_regField_t VLAN_PORT_EGR_TAG_FIELDS[] = +{ + { /* name */ MODEf, + /* lsp */ 0, + /* len */ 2 + }, +}; + +rtk_regField_t VLAN_L2_LRN_DIS_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 14, + /* len */ 18 + }, + { /* name */ ACTf, + /* lsp */ 13, + /* len */ 1 + }, + { /* name */ VIDf, + /* lsp */ 1, + /* len */ 12 + }, + { /* name */ VALIDf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t PORT_BASED_FID_EN_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 10, + /* len */ 22 + }, + { /* name */ PMSKf, + /* lsp */ 0, + /* len */ 10 + }, +}; + +rtk_regField_t PORT_BASED_FID_FIELDS[] = +{ + { /* name */ FIDf, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t VLAN_TAG_PRI_CFG_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 1, + /* len */ 31 + }, + { /* name */ RMK1P_BYPASS_REALKEEPf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +/* Module: 802.1D SVLAN */ +rtk_regField_t VS_GLB_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ VS_TPIDf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t VS_UPLINK_PORT_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 10, + /* len */ 22 + }, + { /* name */ MSKf, + /* lsp */ 0, + /* len */ 10 + }, +}; + +rtk_regField_t VS_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 5, + /* len */ 27 + }, + { /* name */ SPRISELf, + /* lsp */ 3, + /* len */ 2 + }, + { /* name */ UIFSEGf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ UNTAGf, + /* lsp */ 0, + /* len */ 2 + }, +}; + +rtk_regField_t VS_UNTAG_SVID_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 20 + }, + { /* name */ UNTAG_SVIDf, + /* lsp */ 0, + /* len */ 12 + }, +}; + +rtk_regField_t VS_PORT_DFLT_SVID_FIELDS[] = +{ + { /* name */ PORT_DFLT_SVIDf, + /* lsp */ 0, + /* len */ 12 + }, +}; + +rtk_regField_t SVLAN_TRAP_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 18, + /* len */ 14 + }, + { /* name */ CPU_PMSKf, + /* lsp */ 16, + /* len */ 2 + }, + { /* name */ RESERVEDf, + /* lsp */ 3, + /* len */ 13 + }, + { /* name */ PRIf, + /* lsp */ 0, + /* len */ 3 + }, +}; + +/* Module: C2S Table */ +rtk_regField_t VLAN_C2S_ENTRY_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 44, + /* len */ 20 + }, + { /* name */ SVID_ASSIGNf, + /* lsp */ 32, + /* len */ 12 + }, + { /* name */ RESERVEDf, + /* lsp */ 22, + /* len */ 10 + }, + { /* name */ CVIDf, + /* lsp */ 10, + /* len */ 12 + }, + { /* name */ PMSK_ENf, + /* lsp */ 0, + /* len */ 10 + }, +}; + +/* Module: RMA */ +rtk_regField_t RMA_OP_CTRL_00_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 6, + /* len */ 26 + }, + { /* name */ RMA_ACT_00f, + /* lsp */ 4, + /* len */ 2 + }, + { /* name */ DIS_STORM_CTRL_00f, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ CKEEP_00f, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ VLAN_LEAKY_00f, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ PISO_LEAKY_00f, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t RMA_OP_CTRL_01_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 6, + /* len */ 26 + }, + { /* name */ RMA_ACT_01f, + /* lsp */ 4, + /* len */ 2 + }, + { /* name */ DIS_STORM_CTRL_01f, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ CKEEP_01f, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ VLAN_LEAKY_01f, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ PISO_LEAKY_01f, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t RMA_OP_CTRL_02_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 6, + /* len */ 26 + }, + { /* name */ RMA_ACT_02f, + /* lsp */ 4, + /* len */ 2 + }, + { /* name */ DIS_STORM_CTRL_02f, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ CKEEP_02f, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ VLAN_LEAKY_02f, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ PISO_LEAKY_02f, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t RMA_OP_CTRL_03_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 6, + /* len */ 26 + }, + { /* name */ RMA_ACT_03f, + /* lsp */ 4, + /* len */ 2 + }, + { /* name */ DIS_STORM_CTRL_03f, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ CKEEP_03f, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ VLAN_LEAKY_03f, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ PISO_LEAKY_03f, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t RMA_OP_CTRL_04_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 6, + /* len */ 26 + }, + { /* name */ RMA_ACT_04f, + /* lsp */ 4, + /* len */ 2 + }, + { /* name */ DIS_STORM_CTRL_04f, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ CKEEP_04f, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ VLAN_LEAKY_04f, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ PISO_LEAKY_04f, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t RMA_OP_CTRL_08_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 6, + /* len */ 26 + }, + { /* name */ RMA_ACT_08f, + /* lsp */ 4, + /* len */ 2 + }, + { /* name */ DIS_STORM_CTRL_08f, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ CKEEP_08f, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ VLAN_LEAKY_08f, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ PISO_LEAKY_08f, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t RMA_OP_CTRL_0D_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 6, + /* len */ 26 + }, + { /* name */ RMA_ACT_0Df, + /* lsp */ 4, + /* len */ 2 + }, + { /* name */ DIS_STORM_CTRL_0Df, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ CKEEP_0Df, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ VLAN_LEAKY_0Df, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ PISO_LEAKY_0Df, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t RMA_OP_CTRL_0E_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 6, + /* len */ 26 + }, + { /* name */ RMA_ACT_0Ef, + /* lsp */ 4, + /* len */ 2 + }, + { /* name */ DIS_STORM_CTRL_0Ef, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ CKEEP_0Ef, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ VLAN_LEAKY_0Ef, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ PISO_LEAKY_0Ef, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t RMA_OP_CTRL_10_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 6, + /* len */ 26 + }, + { /* name */ RMA_ACT_10f, + /* lsp */ 4, + /* len */ 2 + }, + { /* name */ DIS_STORM_CTRL_10f, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ CKEEP_10f, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ VLAN_LEAKY_10f, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ PISO_LEAKY_10f, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t RMA_OP_CTRL_11_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 6, + /* len */ 26 + }, + { /* name */ RMA_ACT_11f, + /* lsp */ 4, + /* len */ 2 + }, + { /* name */ DIS_STORM_CTRL_11f, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ CKEEP_11f, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ VLAN_LEAKY_11f, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ PISO_LEAKY_11f, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t RMA_OP_CTRL_12_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 6, + /* len */ 26 + }, + { /* name */ RMA_ACT_12f, + /* lsp */ 4, + /* len */ 2 + }, + { /* name */ DIS_STORM_CTRL_12f, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ CKEEP_12f, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ VLAN_LEAKY_12f, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ PISO_LEAKY_12f, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t RMA_OP_CTRL_13_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 6, + /* len */ 26 + }, + { /* name */ RMA_ACT_13f, + /* lsp */ 4, + /* len */ 2 + }, + { /* name */ DIS_STORM_CTRL_13f, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ CKEEP_13f, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ VLAN_LEAKY_13f, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ PISO_LEAKY_13f, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t RMA_OP_CTRL_18_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 6, + /* len */ 26 + }, + { /* name */ RMA_ACT_18f, + /* lsp */ 4, + /* len */ 2 + }, + { /* name */ DIS_STORM_CTRL_18f, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ CKEEP_18f, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ VLAN_LEAKY_18f, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ PISO_LEAKY_18f, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t RMA_OP_CTRL_1A_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 6, + /* len */ 26 + }, + { /* name */ RMA_ACT_1Af, + /* lsp */ 4, + /* len */ 2 + }, + { /* name */ DIS_STORM_CTRL_1Af, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ CKEEP_1Af, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ VLAN_LEAKY_1Af, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ PISO_LEAKY_1Af, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t RMA_OP_CTRL_20_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 6, + /* len */ 26 + }, + { /* name */ RMA_ACT_20f, + /* lsp */ 4, + /* len */ 2 + }, + { /* name */ DIS_STORM_CTRL_20f, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ CKEEP_20f, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ VLAN_LEAKY_20f, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ PISO_LEAKY_20f, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t RMA_OP_CTRL_21_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 6, + /* len */ 26 + }, + { /* name */ RMA_ACT_21f, + /* lsp */ 4, + /* len */ 2 + }, + { /* name */ DIS_STORM_CTRL_21f, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ CKEEP_21f, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ VLAN_LEAKY_21f, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ PISO_LEAKY_21f, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t RMA_OP_CTRL_22_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 6, + /* len */ 26 + }, + { /* name */ RMA_ACT_22f, + /* lsp */ 4, + /* len */ 2 + }, + { /* name */ DIS_STORM_CTRL_22f, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ CKEEP_22f, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ VLAN_LEAKY_22f, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ PISO_LEAKY_22f, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t RMA_OP_CTRL_CDP_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 6, + /* len */ 26 + }, + { /* name */ RMA_ACT_CDPf, + /* lsp */ 4, + /* len */ 2 + }, + { /* name */ DIS_STORM_CTRL_CDPf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ CKEEP_CDPf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ VLAN_LEAKY_CDPf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ PISO_LEAKY_CDPf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t RMA_OP_CTRL_CSSTP_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 6, + /* len */ 26 + }, + { /* name */ RMA_ACT_CSSTPf, + /* lsp */ 4, + /* len */ 2 + }, + { /* name */ DIS_STORM_CTRL_CSSTPf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ CKEEP_CSSTPf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ VLAN_LEAKY_CSSTPf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ PISO_LEAKY_CSSTPf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t RMA_OP_CTRL_LLDP_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 6, + /* len */ 26 + }, + { /* name */ RMA_ACT_LLDPf, + /* lsp */ 4, + /* len */ 2 + }, + { /* name */ DIS_STORM_CTRL_LLDPf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ CKEEP_LLDPf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ VLAN_LEAKY_LLDPf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ PISO_LEAKY_LLDPf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t RMA_CFG_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 28 + }, + { /* name */ LLDP_ENf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ RMA_TRAP_PRIf, + /* lsp */ 0, + /* len */ 3 + }, +}; + +rtk_regField_t RMA_PORT_PTP_ETH2_CTRL_FIELDS[] = +{ + { /* name */ ETH2_P0_ACTf, + /* lsp */ 0, + /* len */ 2 + }, +}; + +rtk_regField_t RMA_PORT_PTP_UDP_CTRL_FIELDS[] = +{ + { /* name */ UDP_P0_ACTf, + /* lsp */ 0, + /* len */ 2 + }, +}; + +rtk_regField_t RMA_PORT_PTP_DELAY_CARE_CTRL_FIELDS[] = +{ + { /* name */ P0_PTP_DELAY_CAREf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t RMA_PORT_PTP_PDELAY_CARE_CTRL_FIELDS[] = +{ + { /* name */ P0_PTP_PDELAY_CAREf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t RMA_PORT_PTP_ASM_CARE_CTRL_FIELDS[] = +{ + { /* name */ P0_PTP_ASM_CAREf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t RMA_PTP_TRAP_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 18, + /* len */ 14 + }, + { /* name */ CPU_PMSKf, + /* lsp */ 16, + /* len */ 2 + }, + { /* name */ RESERVEDf, + /* lsp */ 3, + /* len */ 13 + }, + { /* name */ PRIf, + /* lsp */ 0, + /* len */ 3 + }, +}; + +/* Module: Link Aggregation */ +rtk_regField_t TRK_MBR_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 10, + /* len */ 22 + }, + { /* name */ TRK_PMSKf, + /* lsp */ 0, + /* len */ 10 + }, +}; + +rtk_regField_t TRK_HASH_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 7, + /* len */ 25 + }, + { /* name */ HASH_MSKf, + /* lsp */ 0, + /* len */ 7 + }, +}; + +rtk_regField_t TRK_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 2, + /* len */ 30 + }, + { /* name */ TRUNK_FLDf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t TRK_FLOW_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 1, + /* len */ 31 + }, + { /* name */ TRK_FLCTRL_ENf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t TRK_QUEUE_EMPTY_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 10, + /* len */ 22 + }, + { /* name */ QEMPTYf, + /* lsp */ 0, + /* len */ 10 + }, +}; + +/* Module: Spanning Tree */ +rtk_regField_t MSPT_STATE_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 20, + /* len */ 12 + }, + { /* name */ PORT9_STATEf, + /* lsp */ 18, + /* len */ 2 + }, + { /* name */ PORT8_STATEf, + /* lsp */ 16, + /* len */ 2 + }, + { /* name */ PORT7_STATEf, + /* lsp */ 14, + /* len */ 2 + }, + { /* name */ PORT6_STATEf, + /* lsp */ 12, + /* len */ 2 + }, + { /* name */ PORT5_STATEf, + /* lsp */ 10, + /* len */ 2 + }, + { /* name */ PORT4_STATEf, + /* lsp */ 8, + /* len */ 2 + }, + { /* name */ PORT3_STATEf, + /* lsp */ 6, + /* len */ 2 + }, + { /* name */ PORT2_STATEf, + /* lsp */ 4, + /* len */ 2 + }, + { /* name */ PORT1_STATEf, + /* lsp */ 2, + /* len */ 2 + }, + { /* name */ PORT0_STATEf, + /* lsp */ 0, + /* len */ 2 + }, +}; + +/* Module: MAC Forwarding Control */ +rtk_regField_t L2_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 17, + /* len */ 15 + }, + { /* name */ CPU_PMSKf, + /* lsp */ 15, + /* len */ 2 + }, + { /* name */ MUL_TRAP_PRIf, + /* lsp */ 12, + /* len */ 3 + }, + { /* name */ TRAP_PRIf, + /* lsp */ 9, + /* len */ 3 + }, + { /* name */ CFG_LOOKUP_HIT_ISO_ACTf, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ HASH_FULL_ACTf, + /* lsp */ 6, + /* len */ 2 + }, + { /* name */ LUTCAM_DISABLEf, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ LINKDOWN_AGEOUTf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ LUT_IPMC_HASHf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ AGE_TIMERf, + /* lsp */ 0, + /* len */ 3 + }, +}; + +rtk_regField_t L2_AGE_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ AGE_UNITf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t L2_PORT_AGE_CTRL_FIELDS[] = +{ + { /* name */ DIS_AGEf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t L2_NEWSA_CTRL_FIELDS[] = +{ + { /* name */ NEW_SAf, + /* lsp */ 0, + /* len */ 2 + }, +}; + +rtk_regField_t L2_UNMATCH_SA_CTRL_FIELDS[] = +{ + { /* name */ UNMATCH_SAf, + /* lsp */ 0, + /* len */ 2 + }, +}; + +rtk_regField_t L2_SA_MOVING_FORBID_FIELDS[] = +{ + { /* name */ FORBIDf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t L2_UNKN_UC_FLD_PMSK_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 10, + /* len */ 22 + }, + { /* name */ PORTMASKf, + /* lsp */ 0, + /* len */ 10 + }, +}; + +rtk_regField_t L2_UNKN_MC_FLD_PMSK_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 10, + /* len */ 22 + }, + { /* name */ PORTMASKf, + /* lsp */ 0, + /* len */ 10 + }, +}; + +rtk_regField_t IPV4_UNKN_MC_FLD_PMSK_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 10, + /* len */ 22 + }, + { /* name */ PORTMASKf, + /* lsp */ 0, + /* len */ 10 + }, +}; + +rtk_regField_t IPV6_UNKN_MC_FLD_PMSK_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 10, + /* len */ 22 + }, + { /* name */ PORTMASKf, + /* lsp */ 0, + /* len */ 10 + }, +}; + +rtk_regField_t L2_BC_FLD_PMSK_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 10, + /* len */ 22 + }, + { /* name */ PORTMASKf, + /* lsp */ 0, + /* len */ 10 + }, +}; + +rtk_regField_t L2_PORT_UC_LM_ACT_FIELDS[] = +{ + { /* name */ ACTf, + /* lsp */ 0, + /* len */ 2 + }, +}; + +rtk_regField_t L2_PORT_MC_LM_ACT_FIELDS[] = +{ + { /* name */ ACTf, + /* lsp */ 0, + /* len */ 2 + }, +}; + +rtk_regField_t IPV4_PORT_MC_LM_ACT_FIELDS[] = +{ + { /* name */ ACTf, + /* lsp */ 0, + /* len */ 2 + }, +}; + +rtk_regField_t IPV6_PORT_MC_LM_ACT_FIELDS[] = +{ + { /* name */ ACTf, + /* lsp */ 0, + /* len */ 2 + }, +}; + +rtk_regField_t L2_LRN_CONSTRT_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 26, + /* len */ 6 + }, + { /* name */ PORT_MASKf, + /* lsp */ 16, + /* len */ 10 + }, + { /* name */ RESERVEDf, + /* lsp */ 13, + /* len */ 3 + }, + { /* name */ CONSTRT_NUMf, + /* lsp */ 0, + /* len */ 13 + }, +}; + +rtk_regField_t L2_LRN_CONSTRT_CNT_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 13, + /* len */ 19 + }, + { /* name */ LRN_CNTf, + /* lsp */ 0, + /* len */ 13 + }, +}; + +rtk_regField_t L2_LRN_CONSTRT_ACT_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 2, + /* len */ 30 + }, + { /* name */ LRN_ACTf, + /* lsp */ 0, + /* len */ 2 + }, +}; + +rtk_regField_t L2_LRN_PORT_CONSTRT_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 13, + /* len */ 19 + }, + { /* name */ CONSTRT_NUMf, + /* lsp */ 0, + /* len */ 13 + }, +}; + +rtk_regField_t L2_LRN_PORT_CONSTRT_CNT_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 13, + /* len */ 19 + }, + { /* name */ LRN_CNTf, + /* lsp */ 0, + /* len */ 13 + }, +}; + +rtk_regField_t L2_LRN_PORT_CONSTRT_ACT_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 2, + /* len */ 30 + }, + { /* name */ LRN_ACTf, + /* lsp */ 0, + /* len */ 2 + }, +}; + +rtk_regField_t L2_TBL_FLUSH_CMD_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 18, + /* len */ 14 + }, + { /* name */ FLUSH_BUSYf, + /* lsp */ 17, + /* len */ 1 + }, + { /* name */ FLUSH_ACTf, + /* lsp */ 16, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 10, + /* len */ 6 + }, + { /* name */ FLUSH_PMSKf, + /* lsp */ 0, + /* len */ 10 + }, +}; + +rtk_regField_t L2_TBL_FLUSH_ALL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 1, + /* len */ 31 + }, + { /* name */ FLUSH_ALLf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t L2_TBL_FLUSH_MODE_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 3, + /* len */ 29 + }, + { /* name */ FLUSH_TYPEf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ FLUSH_MODEf, + /* lsp */ 0, + /* len */ 2 + }, +}; + +rtk_regField_t L2_TBL_FLUSH_XID_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 20, + /* len */ 12 + }, + { /* name */ FLUSH_FIDf, + /* lsp */ 16, + /* len */ 4 + }, + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 4 + }, + { /* name */ FLUSH_VIDf, + /* lsp */ 0, + /* len */ 12 + }, +}; + +rtk_regField_t SOURCE_PORT_PERMIT_FIELDS[] = +{ + { /* name */ SRC_PERMIT_ENf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t IPMC_GROUP_DIP_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 28, + /* len */ 4 + }, + { /* name */ DIPf, + /* lsp */ 0, + /* len */ 28 + }, +}; + +rtk_regField_t IPMC_GROUP_PMSK_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 10, + /* len */ 22 + }, + { /* name */ PMSKf, + /* lsp */ 0, + /* len */ 10 + }, +}; + +rtk_regField_t IPMC_GROUP_VALID_FIELDS[] = +{ + { /* name */ VALIDf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t IPMUL_NO_VLAN_EGRESS_FIELDS[] = +{ + { /* name */ IPMUL_VLAN_LEAKYf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t IPMUL_NO_PORTISO_FIELDS[] = +{ + { /* name */ IPMUL_PORTISO_LEAKYf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t L2_FORCE_MODE_FIELDS[] = +{ + { /* name */ FORCE_CTRLf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t L2_FORCE_DPM_PORT_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 10, + /* len */ 22 + }, + { /* name */ FORCE_PORT_MASKf, + /* lsp */ 0, + /* len */ 10 + }, +}; + +/* Module: IGMP & MLD */ +rtk_regField_t IGMP_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 26, + /* len */ 6 + }, + { /* name */ IGMP_MLD_IP6_BYPASSf, + /* lsp */ 25, + /* len */ 1 + }, + { /* name */ IGMP_MLD_IP4_BYPASS_239_255_255f, + /* lsp */ 24, + /* len */ 1 + }, + { /* name */ IGMP_MLD_IP4_BYPASS_224_0_1f, + /* lsp */ 23, + /* len */ 1 + }, + { /* name */ IGMP_MLD_IP4_BYPASS_224_0_0f, + /* lsp */ 22, + /* len */ 1 + }, + { /* name */ DROP_LEAVE_ZEROf, + /* lsp */ 21, + /* len */ 1 + }, + { /* name */ TABLE_FULL_OPf, + /* lsp */ 19, + /* len */ 2 + }, + { /* name */ IGMP_MLD_PORTISO_LKYf, + /* lsp */ 18, + /* len */ 1 + }, + { /* name */ IGMP_MLD_VLAN_LKYf, + /* lsp */ 17, + /* len */ 1 + }, + { /* name */ IGMP_MLD_DISC_STORM_FLTRf, + /* lsp */ 16, + /* len */ 1 + }, + { /* name */ REPORT_LEAVE_FWDf, + /* lsp */ 14, + /* len */ 2 + }, + { /* name */ REPORT_FWDf, + /* lsp */ 13, + /* len */ 1 + }, + { /* name */ ROBUSTNESS_VARf, + /* lsp */ 10, + /* len */ 3 + }, + { /* name */ LEAVE_SUPPRESSIONf, + /* lsp */ 9, + /* len */ 1 + }, + { /* name */ REPORT_SUPPRESSIONf, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ LEAVE_TIMERf, + /* lsp */ 5, + /* len */ 3 + }, + { /* name */ FAST_LEAVE_ENf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ CKS_ERR_OPf, + /* lsp */ 2, + /* len */ 2 + }, + { /* name */ RESERVEDf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ IGMP_MLD_ENf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t IGMP_QUERY_INTVL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ VALUEf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t IGMP_DYN_ROUTER_INFO_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ ROUTER_PORT_FORBID_2f, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ PORT2_IDf, + /* lsp */ 11, + /* len */ 4 + }, + { /* name */ TIMER2f, + /* lsp */ 8, + /* len */ 3 + }, + { /* name */ ROUTER_PORT_FORBID_1f, + /* lsp */ 7, + /* len */ 1 + }, + { /* name */ PORT1_IDf, + /* lsp */ 3, + /* len */ 4 + }, + { /* name */ TIMER1f, + /* lsp */ 0, + /* len */ 3 + }, +}; + +rtk_regField_t IGMP_ROUTER_PORT_CRTL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 26, + /* len */ 6 + }, + { /* name */ ALLOW_DYN_ROTR_PMSKf, + /* lsp */ 16, + /* len */ 10 + }, + { /* name */ RESERVEDf, + /* lsp */ 10, + /* len */ 6 + }, + { /* name */ STIC_PMSKf, + /* lsp */ 0, + /* len */ 10 + }, +}; + +rtk_regField_t IGMP_PORT_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 24, + /* len */ 8 + }, + { /* name */ MAX_GROUP_NUMf, + /* lsp */ 16, + /* len */ 8 + }, + { /* name */ RESERVEDf, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ ALLOW_QUERYf, + /* lsp */ 14, + /* len */ 1 + }, + { /* name */ ALLOW_REPORTf, + /* lsp */ 13, + /* len */ 1 + }, + { /* name */ ALLOW_LEAVEf, + /* lsp */ 12, + /* len */ 1 + }, + { /* name */ ALLOW_MRPf, + /* lsp */ 11, + /* len */ 1 + }, + { /* name */ ALLOW_MC_DATAf, + /* lsp */ 10, + /* len */ 1 + }, + { /* name */ MLDV2_OPf, + /* lsp */ 8, + /* len */ 2 + }, + { /* name */ MLDV1_OPf, + /* lsp */ 6, + /* len */ 2 + }, + { /* name */ IGMPV3_OPf, + /* lsp */ 4, + /* len */ 2 + }, + { /* name */ IGMPV2_OPf, + /* lsp */ 2, + /* len */ 2 + }, + { /* name */ IGMPV1_OPf, + /* lsp */ 0, + /* len */ 2 + }, +}; + +rtk_regField_t PORT_CURR_GROUP_FIELDS[] = +{ + { /* name */ NUMf, + /* lsp */ 0, + /* len */ 8 + }, +}; + +rtk_regField_t IGMP_TBL_USAGE_FIELDS[] = +{ + { /* name */ LIST_BITf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t IGMP_TRAP_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 18, + /* len */ 14 + }, + { /* name */ CPU_PMSKf, + /* lsp */ 16, + /* len */ 2 + }, + { /* name */ RESERVEDf, + /* lsp */ 3, + /* len */ 13 + }, + { /* name */ PRIf, + /* lsp */ 0, + /* len */ 3 + }, +}; + +/* Module: Port Isolation */ +rtk_regField_t PORT_ISO_PORT_PMSK_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 10, + /* len */ 22 + }, + { /* name */ PMSKf, + /* lsp */ 0, + /* len */ 10 + }, +}; + +/* Module: Port Mirror */ +rtk_regField_t MIR_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 8, + /* len */ 24 + }, + { /* name */ MIR_REALKEEP_ENf, + /* lsp */ 7, + /* len */ 1 + }, + { /* name */ MIR_RX_ISOLATE_LKYf, + /* lsp */ 6, + /* len */ 1 + }, + { /* name */ MIR_TX_ISOLATE_LKYf, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ MIR_RX_VLAN_LKYf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ MIR_TX_VLAN_LKYf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ MIRROR_ACL_OVERRIDE_ENf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ MIRROR_TX_OVERRIDE_ENf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ MIRROR_RX_OVERRIDE_ENf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t MIR_SET_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 7, + /* len */ 25 + }, + { /* name */ MIR_ISOf, + /* lsp */ 6, + /* len */ 1 + }, + { /* name */ MIR_RX_TX_SELf, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ MTP_PORTf, + /* lsp */ 1, + /* len */ 4 + }, + { /* name */ MIR_ENf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t MIR_SET_PMSK_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 26, + /* len */ 6 + }, + { /* name */ RX_PMSKf, + /* lsp */ 16, + /* len */ 10 + }, + { /* name */ RESERVEDf, + /* lsp */ 10, + /* len */ 6 + }, + { /* name */ TX_PMSKf, + /* lsp */ 0, + /* len */ 10 + }, +}; + +rtk_regField_t MIR_SAMPLE_CRTL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RATEf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MIR_MATCHED_FIELDS[] = +{ + { /* name */ PKT_CNTf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ SAMPLE_PKT_CNTf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +/* Module: RSPAN */ +rtk_regField_t MIR_RSPAN_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 1, + /* len */ 31 + }, + { /* name */ RX_TAG_ENf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t MIR_RSPAN_TAG_CTRL_FIELDS[] = +{ + { /* name */ TPIDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ PRIf, + /* lsp */ 13, + /* len */ 3 + }, + { /* name */ CFIf, + /* lsp */ 12, + /* len */ 1 + }, + { /* name */ VIDf, + /* lsp */ 0, + /* len */ 12 + }, +}; + +rtk_regField_t MIR_RSPAN_TX_PORT_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 10, + /* len */ 22 + }, + { /* name */ TAG_ADDf, + /* lsp */ 0, + /* len */ 10 + }, +}; + +rtk_regField_t MIR_RSPAN_RX_ACT_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 1, + /* len */ 31 + }, + { /* name */ TAG_RMf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +/* Module: ACL Module */ +rtk_regField_t ACL_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 1, + /* len */ 31 + }, + { /* name */ TABLE_RSTf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t ACL_GPIO_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 1, + /* len */ 31 + }, + { /* name */ DFLT_PLTYf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t ACL_PORT_EN_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 10, + /* len */ 22 + }, + { /* name */ PMSKf, + /* lsp */ 0, + /* len */ 10 + }, +}; + +rtk_regField_t ACL_PORT_UNMATCH_PERMIT_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 10, + /* len */ 22 + }, + { /* name */ PMSK_ACTf, + /* lsp */ 0, + /* len */ 10 + }, +}; + +rtk_regField_t ACL_TEMPLATE_CTRL_FIELDS[] = +{ + { /* name */ FILED7_TYPEf, + /* lsp */ 56, + /* len */ 8 + }, + { /* name */ FILED6_TYPEf, + /* lsp */ 48, + /* len */ 8 + }, + { /* name */ FILED5_TYPEf, + /* lsp */ 40, + /* len */ 8 + }, + { /* name */ FILED4_TYPEf, + /* lsp */ 32, + /* len */ 8 + }, + { /* name */ FILED3_TYPEf, + /* lsp */ 24, + /* len */ 8 + }, + { /* name */ FILED2_TYPEf, + /* lsp */ 16, + /* len */ 8 + }, + { /* name */ FILED1_TYPEf, + /* lsp */ 8, + /* len */ 8 + }, + { /* name */ FILED0_TYPEf, + /* lsp */ 0, + /* len */ 8 + }, +}; + +rtk_regField_t ACL_ACT_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 9, + /* len */ 23 + }, + { /* name */ NOTf, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ BYPASS_CTRL_BITf, + /* lsp */ 7, + /* len */ 1 + }, + { /* name */ GPIO_CTRL_BITf, + /* lsp */ 6, + /* len */ 1 + }, + { /* name */ FWD_CTRL_BITf, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ POLIC_LOG_CTRL_BITf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ RMK_CTRL_BITf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ PRI_CTRL_BITf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ SVLAN_CTRL_BITf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ CVLAN_CTRL_BITf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t ACL_HIT_INDICATOR_FIELDS[] = +{ + { /* name */ BYPASS_ACT_HITf, + /* lsp */ 63, + /* len */ 1 + }, + { /* name */ BYPASS_RULE_IDXf, + /* lsp */ 56, + /* len */ 7 + }, + { /* name */ GPO_ACT_HITf, + /* lsp */ 55, + /* len */ 1 + }, + { /* name */ GPO_RULE_IDXf, + /* lsp */ 48, + /* len */ 7 + }, + { /* name */ FWD_ACT_HITf, + /* lsp */ 47, + /* len */ 1 + }, + { /* name */ FWD_RULE_IDXf, + /* lsp */ 40, + /* len */ 7 + }, + { /* name */ POLIC_LOG_ACT_HITf, + /* lsp */ 39, + /* len */ 1 + }, + { /* name */ POLIC_LOG_RULE_IDXf, + /* lsp */ 32, + /* len */ 7 + }, + { /* name */ RMK_ACT_HITf, + /* lsp */ 31, + /* len */ 1 + }, + { /* name */ P1_DSCP_RULE_IDXf, + /* lsp */ 24, + /* len */ 7 + }, + { /* name */ PRI_ACT_HITf, + /* lsp */ 23, + /* len */ 1 + }, + { /* name */ PRI_RULE_IDXf, + /* lsp */ 16, + /* len */ 7 + }, + { /* name */ SVLAN_ACT_HITf, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ SVLAN_RULE_IDXf, + /* lsp */ 8, + /* len */ 7 + }, + { /* name */ CVLAN_ACT_HITf, + /* lsp */ 7, + /* len */ 1 + }, + { /* name */ CVLAN_RULE_IDXf, + /* lsp */ 0, + /* len */ 7 + }, +}; + +/* Module: Range Check (port/vlan/ip/L4port) */ +rtk_regField_t RNG_CHK_VID_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 26, + /* len */ 6 + }, + { /* name */ UPPERf, + /* lsp */ 14, + /* len */ 12 + }, + { /* name */ LOWERf, + /* lsp */ 2, + /* len */ 12 + }, + { /* name */ TYPEf, + /* lsp */ 0, + /* len */ 2 + }, +}; + +rtk_regField_t RNG_CHK_IP_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 67, + /* len */ 29 + }, + { /* name */ TYPEf, + /* lsp */ 64, + /* len */ 3 + }, + { /* name */ UPPERf, + /* lsp */ 32, + /* len */ 32 + }, + { /* name */ LOWERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t RNG_CHK_PORT_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 34, + /* len */ 30 + }, + { /* name */ TYPEf, + /* lsp */ 32, + /* len */ 2 + }, + { /* name */ UPPERf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ LOWERf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +/* Module: ACL LOG COUNTER */ +rtk_regField_t ACL_LOG_CNTR_RST_FIELDS[] = +{ + { /* name */ RSTf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t ACL_CNTR_RST_VAL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 1, + /* len */ 31 + }, + { /* name */ VALf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t ACL_LOG_CNTR_TYPE_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TYPEf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t ACL_LOG_CNTR_MODE_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ MODEf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t ACL_LOG_CNTR_DATA_FIELDS[] = +{ + { /* name */ CNTR_VALf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t ACL_LATCH_TRIGGER_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 1, + /* len */ 31 + }, + { /* name */ CMDf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t ACL_LATCH_ADDR_FIELDS[] = +{ + { /* name */ ADDRf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t ACL_LATCH_VAL_L_FIELDS[] = +{ + { /* name */ VAL_Lf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t ACL_LATCH_VAL_H_FIELDS[] = +{ + { /* name */ VAL_Hf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +/* Module: PTP (Precision Time Protocol) */ +rtk_regField_t PTP_TIME_TOD_DELAY_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TOD_DELAYf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t PTP_TIME_OP_DURATION_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 10, + /* len */ 22 + }, + { /* name */ TIME_OP_DURATIONf, + /* lsp */ 0, + /* len */ 10 + }, +}; + +rtk_regField_t PTP_DUMMY_RG02_FIELDS[] = +{ + { /* name */ PTP_DUMMY_RG02f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t PTP_DUMMY_RG03_FIELDS[] = +{ + { /* name */ PTP_DUMMY_RG03f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t PTP_OTAG_CONFIG0_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ OTAG_TPID_0f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t PTP_OTAG_CONFIG1_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ OTAG_TPID_1f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t PTP_OTAG_CONFIG2_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ OTAG_TPID_2f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t PTP_OTAG_CONFIG3_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ OTAG_TPID_3f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t PTP_ITAG_CONFIG0_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ ITAG_TPID_0f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t PTP_DUMMY_RG09_FIELDS[] = +{ + { /* name */ PTP_TIMER_RESERVE_RG09f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t PTP_DUMMY_RG10_FIELDS[] = +{ + { /* name */ PTP_TIMER_RESERVE_RG10f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t PTP_APPLY_FREQ_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 1, + /* len */ 31 + }, + { /* name */ APPLY_FREQf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t PTP_TIME_FREQ0_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ CFG_PTP_TIME_FREQ0f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t PTP_TIME_FREQ1_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ CFG_PTP_TIME_FREQ1f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t PTP_CUR_TIME_FREQ0_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ CUR_PTP_TIME_FREQ0f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t PTP_CUR_TIME_FREQ1_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ CUR_PTP_TIME_FREQ1f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t PTP_TIME_NSEC0_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ CFG_PTP_TIME_NSEC_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t PTP_TIME_NSEC1_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ CFG_TOD_VALIDf, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 14, + /* len */ 1 + }, + { /* name */ CFG_PTP_TIME_NSEC_Hf, + /* lsp */ 0, + /* len */ 14 + }, +}; + +rtk_regField_t PTP_TIME_SEC0_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ CFG_PTP_TIME_SEC_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t PTP_TIME_SEC1_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ CFG_PTP_TIME_SEC_Mf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t PTP_TIME_SEC2_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ CFG_PTP_TIME_SEC_Hf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t PTP_TIME_CRTL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 3, + /* len */ 29 + }, + { /* name */ PTP_TIME_EXECf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ PTP_TIME_CMDf, + /* lsp */ 0, + /* len */ 2 + }, +}; + +rtk_regField_t PTP_TIME_NSEC_RD0_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RD_PTP_TIME_NSEC_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t PTP_TIME_NSEC_RD1_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 14, + /* len */ 18 + }, + { /* name */ RD_PTP_TIME_NSEC_Hf, + /* lsp */ 0, + /* len */ 14 + }, +}; + +rtk_regField_t PTP_TIME_SEC_RD0_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RD_PTP_TIME_SEC_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t PTP_TIME_SEC_RD1_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RD_PTP_TIME_SEC_Mf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t PTP_TIME_SEC_RD2_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RD_PTP_TIME_SEC_Hf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t PTP_CLKOUT_NSEC0_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ CLKOUT_PTP_TIME_NSEC_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t PTP_CLKOUT_NSEC1_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ CLKOUT_PTP_RSVf, + /* lsp */ 14, + /* len */ 2 + }, + { /* name */ CLKOUT_PTP_TIME_NSEC_Hf, + /* lsp */ 0, + /* len */ 14 + }, +}; + +rtk_regField_t PTP_CLKOUT_SEC0_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ CLKOUT_PTP_TIME_SEC_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t PTP_CLKOUT_SEC1_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ CLKOUT_PTP_TIME_SEC_Mf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t PTP_CLKOUT_SEC2_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ CLKOUT_PTP_TIME_SEC_Hf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t PTP_CLKOUT_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ CFG_PULSE_RSVf, + /* lsp */ 3, + /* len */ 13 + }, + { /* name */ CFG_PULSE_MODEf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ CFG_CLKOUT_ENf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ RD_CLKOUT_RUNf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t PTP_CLKOUT_HALF_PERD_NS_L_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ CFG_CLKOUT_HALF_PERIOD_NS_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t PTP_CLKOUT_HALF_PERD_NS_H_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ CFG_CLKOUT_HALF_PERIOD_RSVf, + /* lsp */ 14, + /* len */ 2 + }, + { /* name */ CFG_CLKOUT_HALF_PERIOD_NS_Hf, + /* lsp */ 0, + /* len */ 14 + }, +}; + +rtk_regField_t PTP_TIME_OP_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ CFG_GPI_RSV_15_7f, + /* lsp */ 7, + /* len */ 9 + }, + { /* name */ CFG_GPI_OPf, + /* lsp */ 4, + /* len */ 3 + }, + { /* name */ CFG_GPI_RISE_TRIGf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ CFG_GPI_FALL_TRIGf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ CFG_GPI_RSV_1_0f, + /* lsp */ 0, + /* len */ 2 + }, +}; + +rtk_regField_t PTP_PPS_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ CFG_PPS_RSVf, + /* lsp */ 7, + /* len */ 9 + }, + { /* name */ CFG_PPS_ENf, + /* lsp */ 6, + /* len */ 1 + }, + { /* name */ CFG_PPS_WIDTHf, + /* lsp */ 0, + /* len */ 6 + }, +}; + +rtk_regField_t PTP_TX_TIMESTAMP_RD0_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RD_TX_TIMESTAMP_VALIDf, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 14, + /* len */ 1 + }, + { /* name */ RD_PORT_IDf, + /* lsp */ 8, + /* len */ 6 + }, + { /* name */ RD_MSG_TYPEf, + /* lsp */ 6, + /* len */ 2 + }, + { /* name */ RD_SEQ_ID_Hf, + /* lsp */ 0, + /* len */ 6 + }, +}; + +rtk_regField_t PTP_TX_TIMESTAMP_RD1_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RD_SEQ_ID_Lf, + /* lsp */ 6, + /* len */ 10 + }, + { /* name */ RD_TX_TIMESTAMP_SEC_Hf, + /* lsp */ 0, + /* len */ 6 + }, +}; + +rtk_regField_t PTP_TX_TIMESTAMP_RD2_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RD_TX_TIMESTAMP_SEC_Lf, + /* lsp */ 14, + /* len */ 2 + }, + { /* name */ RD_TX_TIMESTAMP_NSEC_Hf, + /* lsp */ 0, + /* len */ 14 + }, +}; + +rtk_regField_t PTP_TX_TIMESTAMP_RD3_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RD_TX_TIMESTAMP_NSEC_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t PTP_MIB_INTR_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 9, + /* len */ 23 + }, + { /* name */ CFG_MIB_ENf, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 4 + }, + { /* name */ RD_ISR_PPS_If, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ CFG_IMR_PPS_If, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ RD_ISR_PTPf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ CFG_IMR_PTPf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t PTP_GLOBAL_DBG_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ CFG_DBG_SEL_MODEf, + /* lsp */ 8, + /* len */ 8 + }, + { /* name */ CFG_DBG_SEL_PTPf, + /* lsp */ 4, + /* len */ 4 + }, + { /* name */ CFG_DBG_SEL_INSTf, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t PTP_CLK_SRC_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ CFG_CLK_RSVf, + /* lsp */ 1, + /* len */ 15 + }, + { /* name */ CFG_CLK_SRCf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t PTP_CLKOUT_HALF_PERD_FS_L_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ CFG_CLKOUT_HALF_PERIOD_FS_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t PTP_CLKOUT_HALF_PERD_FS_H_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ CFG_CLKOUT_RSVf, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ CFG_CLKOUT_HALF_PERIOD_FS_Hf, + /* lsp */ 0, + /* len */ 15 + }, +}; + +rtk_regField_t PTP_DUMMY_RG46_FIELDS[] = +{ + { /* name */ PTP_TIMER_RESERVE_RG46f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t PTP_DUMMY_RG47_FIELDS[] = +{ + { /* name */ PTP_TIMER_RESERVE_RG47f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t PPS_IN_LATCH_TIME_NSEC_L_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ PPS_LATCH_PTP_TIME_NSEC_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t PPS_IN_LATCH_TIME_NSEC_H_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 14, + /* len */ 18 + }, + { /* name */ PPS_LATCH_PTP_TIME_NSEC_Hf, + /* lsp */ 0, + /* len */ 14 + }, +}; + +rtk_regField_t PPS_IN_LATCH_TIME_SEC_L_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ PPS_LATCH_PTP_TIME_SEC_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t PPS_IN_LATCH_TIME_SEC_M_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ PPS_LATCH_PTP_TIME_SEC_Mf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t PPS_IN_LATCH_TIME_SEC_H_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ PPS_LATCH_PTP_TIME_SEC_Hf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t PTP_DUMMY_RG53_FIELDS[] = +{ + { /* name */ PTP_DUMMY_RG53f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t PTP_DUMMY_RG54_FIELDS[] = +{ + { /* name */ PTP_DUMMY_RG54f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t PTP_DUMMY_RG55_FIELDS[] = +{ + { /* name */ PTP_DUMMY_RG55f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t PTP_DUMMY_RG56_FIELDS[] = +{ + { /* name */ PTP_DUMMY_RG56f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t PTP_DUMMY_RG57_FIELDS[] = +{ + { /* name */ PTP_DUMMY_RG57f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t PTP_DUMMY_RG58_FIELDS[] = +{ + { /* name */ PTP_DUMMY_RG58f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t PTP_DUMMY_RG59_FIELDS[] = +{ + { /* name */ PTP_DUMMY_RG59f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t PTP_DUMMY_RG60_FIELDS[] = +{ + { /* name */ PTP_DUMMY_RG60f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t PTP_DUMMY_RG61_FIELDS[] = +{ + { /* name */ PTP_DUMMY_RG61f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t PTP_TIME_SPEED_UP_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 1, + /* len */ 31 + }, + { /* name */ CFG_DUR_SPDUPf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t PTP_VERSION_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ PTP_VERSIONf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t P0_PORT_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ P0_CFG_LINK_DELAY_Lf, + /* lsp */ 6, + /* len */ 10 + }, + { /* name */ P0_CFG_ALWAYS_TSf, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ P0_PTP_ROLEf, + /* lsp */ 2, + /* len */ 2 + }, + { /* name */ P0_CFG_UDP_ENf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ P0_CFG_ETH_ENf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t P0_LINK_DELAY_H_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ P0_CFG_LINK_DELAY_Hf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t P0_MISC_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ P0_PTP_DUMMYf, + /* lsp */ 1, + /* len */ 15 + }, + { /* name */ P0_CFG_BYPASSf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t P0_TX_IMBAL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 20 + }, + { /* name */ P0_TX_IMBALf, + /* lsp */ 0, + /* len */ 12 + }, +}; + +rtk_regField_t P0_RX_IMBAL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 20 + }, + { /* name */ P0_RX_IMBALf, + /* lsp */ 0, + /* len */ 12 + }, +}; + +rtk_regField_t P0_PTP_PORTID_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 6, + /* len */ 26 + }, + { /* name */ P0_IDf, + /* lsp */ 0, + /* len */ 6 + }, +}; + +rtk_regField_t P0_PTP_DUMMY_RG06_FIELDS[] = +{ + { /* name */ P0_PTP_DUMMY_RG06f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t P0_DBG_PTP_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ P0_DBG_PTPf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t TOD_OUT_DATA_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TOD_DATAf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t TOD_OUT_CTRL0_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TOD_DATA_LENf, + /* lsp */ 8, + /* len */ 8 + }, + { /* name */ DIVISOR_LATCH_VAL_BIT16f, + /* lsp */ 7, + /* len */ 1 + }, + { /* name */ MANUALf, + /* lsp */ 6, + /* len */ 1 + }, + { /* name */ TOD_DELAYf, + /* lsp */ 0, + /* len */ 6 + }, +}; + +rtk_regField_t TOD_OUT_CTRL1_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ DIVISOR_LATCH_VAL_BIT15_0f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t TOD_SARP_GPS_WEEK_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TOD_SARP_GPS_WEEKf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t TOD_SARP_GPS_SEC_L_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TOD_SARP_GPS_SEC_Lf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t TOD_SARP_GPS_SEC_H_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TOD_SARP_GPS_SEC_Hf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t TOD_UART_SETTING_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 15, + /* len */ 17 + }, + { /* name */ DBG_SELf, + /* lsp */ 11, + /* len */ 4 + }, + { /* name */ TIMER_GPIO_OEf, + /* lsp */ 10, + /* len */ 1 + }, + { /* name */ SELF_GPIf, + /* lsp */ 9, + /* len */ 1 + }, + { /* name */ TIMER_GPOf, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ DBG_ENf, + /* lsp */ 7, + /* len */ 1 + }, + { /* name */ PARITYf, + /* lsp */ 5, + /* len */ 2 + }, + { /* name */ STOP_BITf, + /* lsp */ 2, + /* len */ 3 + }, + { /* name */ DATA_BITf, + /* lsp */ 0, + /* len */ 2 + }, +}; + +rtk_regField_t TOD_INTR_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TOD_DUMMYf, + /* lsp */ 2, + /* len */ 14 + }, + { /* name */ ISR_TODf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ IMR_TODf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +/* Module: Storm Control (B/M/UM/DLF) */ +rtk_regField_t RX_STORM_BCAST_CTRL_FIELDS[] = +{ + { /* name */ RX_STROM_BCAST_ENf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t RX_STORM_MCAST_CTRL_FIELDS[] = +{ + { /* name */ RX_STROM_MCAST_ENf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t RX_STORM_UNUCAST_CTRL_FIELDS[] = +{ + { /* name */ RX_STROM_UNUCAST_ENf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t RX_STORM_UNMCAST_CTRL_FIELDS[] = +{ + { /* name */ RX_STROM_UNMCAST_ENf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t RX_STORM_BCAST_METER_FIELDS[] = +{ + { /* name */ RX_STROM_BCAST_MIDXf, + /* lsp */ 0, + /* len */ 6 + }, +}; + +rtk_regField_t RX_STORM_MCAST_METER_FIELDS[] = +{ + { /* name */ RX_STROM_MCAST_MIDXf, + /* lsp */ 0, + /* len */ 6 + }, +}; + +rtk_regField_t RX_STORM_UNUCAST_METER_FIELDS[] = +{ + { /* name */ RX_STROM_UNUCAST_MIDXf, + /* lsp */ 0, + /* len */ 6 + }, +}; + +rtk_regField_t RX_STORM_UNMCAST_METER_FIELDS[] = +{ + { /* name */ RX_STROM_UNMCAST_MIDXf, + /* lsp */ 0, + /* len */ 6 + }, +}; + +rtk_regField_t CFG_STORM_EXT_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 14, + /* len */ 18 + }, + { /* name */ STORM_EXT_EN_PORTMASKf, + /* lsp */ 4, + /* len */ 10 + }, + { /* name */ STORM_UNKNOWN_MCAST_EXT_ENf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ STORM_UNKNOWN_UCAST_EXT_ENf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ STORM_MCAST_EXT_ENf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ STORM_BCAST_EXT_ENf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t STORM_EXT_MTRIDX_CFG_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 30, + /* len */ 2 + }, + { /* name */ STORM_UNKNOWN_MCAST_EXT_METERIDf, + /* lsp */ 24, + /* len */ 6 + }, + { /* name */ RESERVEDf, + /* lsp */ 22, + /* len */ 2 + }, + { /* name */ STORM_UNKNOWN_UCAST_EXT_METERIDf, + /* lsp */ 16, + /* len */ 6 + }, + { /* name */ RESERVEDf, + /* lsp */ 14, + /* len */ 2 + }, + { /* name */ STORM_MCAST_EXT_METERIDf, + /* lsp */ 8, + /* len */ 6 + }, + { /* name */ RESERVEDf, + /* lsp */ 6, + /* len */ 2 + }, + { /* name */ STORM_BCAST_EXT_METERIDf, + /* lsp */ 0, + /* len */ 6 + }, +}; + +/* Module: IngressBW */ +rtk_regField_t IGBW_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 9, + /* len */ 23 + }, + { /* name */ INC_BYPASS_PKTf, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ INC_IFGf, + /* lsp */ 7, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 6, + /* len */ 1 + }, + { /* name */ ADMIT_DHCPf, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ ADMIT_ARPREQf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ ADMIT_RMAf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ ADMIT_BPDUf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ ADMIT_RTKPKTf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ ADMIT_IGMPf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t IGBW_LB_CTRL_FIELDS[] = +{ + { /* name */ TICKf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TKNf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t IGBW_PORT_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 21, + /* len */ 11 + }, + { /* name */ BW_ENf, + /* lsp */ 20, + /* len */ 1 + }, + { /* name */ RATEf, + /* lsp */ 0, + /* len */ 20 + }, +}; + +rtk_regField_t IGBW_PORT_BURST_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 63, + /* len */ 1 + }, + { /* name */ HIGH_ONf, + /* lsp */ 32, + /* len */ 31 + }, + { /* name */ RESERVEDf, + /* lsp */ 31, + /* len */ 1 + }, + { /* name */ HIGH_OFFf, + /* lsp */ 0, + /* len */ 31 + }, +}; + +rtk_regField_t IGBW_PORT_LB_RST_FIELDS[] = +{ + { /* name */ RSTf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t IGBW_PORT_CNGST_FLAG_FIELDS[] = +{ + { /* name */ FLAGf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t IGBW_PORT_FC_CTRL_FIELDS[] = +{ + { /* name */ ENf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t IGBW_PORT_DROP_CTRL_FIELDS[] = +{ + { /* name */ DROP_THRf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +/* Module: Egress Bandwidth Control */ +rtk_regField_t EGBW_ENCAP_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 2, + /* len */ 30 + }, + { /* name */ ASSURED_DIS_ENCAP_FEED_BACKf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t EGBW_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 2, + /* len */ 30 + }, + { /* name */ INC_IFGf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ RATE_MODE_CPUf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t EGBW_LB_CTRL_FIELDS[] = +{ + { /* name */ TKNf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TICKf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t EGBW_PORT_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 53, + /* len */ 11 + }, + { /* name */ ENf, + /* lsp */ 52, + /* len */ 1 + }, + { /* name */ RATEf, + /* lsp */ 32, + /* len */ 20 + }, + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ BURSTf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t EGBW_PORT_LB_RST_FIELDS[] = +{ + { /* name */ RSTf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t EGBW_PORT_Q_MAX_LB_CTRL_SET_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 53, + /* len */ 11 + }, + { /* name */ ENf, + /* lsp */ 52, + /* len */ 1 + }, + { /* name */ RATEf, + /* lsp */ 32, + /* len */ 20 + }, + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ BURSTf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t EGBW_PORT_Q_MAX_LB_RST_SET_FIELDS[] = +{ + { /* name */ RSTf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t EGBW_PORT_Q_ASSURED_FIX_BURST_CTRL_SET_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ BURSTf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t EGBW_PORT_Q_ASSURED_LB_CTRL_SET_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 21, + /* len */ 11 + }, + { /* name */ ENf, + /* lsp */ 20, + /* len */ 1 + }, + { /* name */ RATEf, + /* lsp */ 0, + /* len */ 20 + }, +}; + +rtk_regField_t EGBW_PORT_Q_FIX_LB_CTRL_SET_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 21, + /* len */ 11 + }, + { /* name */ ENf, + /* lsp */ 20, + /* len */ 1 + }, + { /* name */ RATEf, + /* lsp */ 0, + /* len */ 20 + }, +}; + +rtk_regField_t EGBW_PORT_Q_ASSURED_FIX_LB_RST_SET_FIELDS[] = +{ + { /* name */ RSTf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t EGBW_RATE_10M_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 20, + /* len */ 12 + }, + { /* name */ RATEf, + /* lsp */ 0, + /* len */ 20 + }, +}; + +rtk_regField_t EGBW_RATE_100M_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 20, + /* len */ 12 + }, + { /* name */ RATEf, + /* lsp */ 0, + /* len */ 20 + }, +}; + +rtk_regField_t EGBW_RATE_1G_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 20, + /* len */ 12 + }, + { /* name */ RATEf, + /* lsp */ 0, + /* len */ 20 + }, +}; + +rtk_regField_t EGBW_RATE_500M_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 20, + /* len */ 12 + }, + { /* name */ RATEf, + /* lsp */ 0, + /* len */ 20 + }, +}; + +rtk_regField_t EGBW_RATE_10G_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 20, + /* len */ 12 + }, + { /* name */ RATEf, + /* lsp */ 0, + /* len */ 20 + }, +}; + +rtk_regField_t EGBW_RATE_2500M_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 20, + /* len */ 12 + }, + { /* name */ RATEf, + /* lsp */ 0, + /* len */ 20 + }, +}; + +rtk_regField_t EGBW_RATE_1250M_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 20, + /* len */ 12 + }, + { /* name */ RATEf, + /* lsp */ 0, + /* len */ 20 + }, +}; + +rtk_regField_t EGBW_RATE_5G_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 20, + /* len */ 12 + }, + { /* name */ RATEf, + /* lsp */ 0, + /* len */ 20 + }, +}; + +rtk_regField_t DMY_REG0_EGRESS_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 18, + /* len */ 14 + }, + { /* name */ STRIC_WFQ_JUMBO_BUG_FIXf, + /* lsp */ 17, + /* len */ 1 + }, + { /* name */ SPD_UP_REFILLf, + /* lsp */ 16, + /* len */ 1 + }, + { /* name */ AMP_FACTORf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +/* Module: Meter Marker */ +rtk_regField_t SHARED_METER_RATE_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 24, + /* len */ 8 + }, + { /* name */ LB_RATEf, + /* lsp */ 0, + /* len */ 24 + }, +}; + +rtk_regField_t SHARED_METER_BURST_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 28, + /* len */ 4 + }, + { /* name */ LB_BURSTf, + /* lsp */ 0, + /* len */ 28 + }, +}; + +rtk_regField_t SHARED_METER_MODE_FIELDS[] = +{ + { /* name */ LB_MODEf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t SHARED_METER_EXCEED_FIELDS[] = +{ + { /* name */ LB_EXCEEDf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t SHARED_METER_EXCEED_ICPU_FIELDS[] = +{ + { /* name */ LB_EXCEED_ICPUf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t SHARED_METER_IPG_CTRL_FIELDS[] = +{ + { /* name */ IPG_CNTRf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t SHARED_METER_LB_CTRL_FIELDS[] = +{ + { /* name */ TICKf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TKNf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t SHARED_METER_LB_PPS_CTRL_FIELDS[] = +{ + { /* name */ TICKf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ TKNf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +/* Module: FlowControl & Backpressure */ +rtk_regField_t FC_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 28, + /* len */ 4 + }, + { /* name */ JUMBO_FRAME_CNTf, + /* lsp */ 16, + /* len */ 12 + }, + { /* name */ RESERVEDf, + /* lsp */ 2, + /* len */ 14 + }, + { /* name */ PRECISE_DROP_ALL_ENf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ RESERVEDf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t FC_PORT_ACT_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 13, + /* len */ 19 + }, + { /* name */ ACTf, + /* lsp */ 12, + /* len */ 1 + }, + { /* name */ ALLOW_PAGE_CNTf, + /* lsp */ 0, + /* len */ 12 + }, +}; + +rtk_regField_t FC_GLB_SYS_UTIL_THR_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 24, + /* len */ 8 + }, + { /* name */ THR_OFFf, + /* lsp */ 12, + /* len */ 12 + }, + { /* name */ THR_ONf, + /* lsp */ 0, + /* len */ 12 + }, +}; + +rtk_regField_t FC_GLB_DROP_THR_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 28, + /* len */ 4 + }, + { /* name */ PUB_PAGEf, + /* lsp */ 16, + /* len */ 12 + }, + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 4 + }, + { /* name */ DROP_ALLf, + /* lsp */ 0, + /* len */ 12 + }, +}; + +rtk_regField_t FC_GLB_HI_THR_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 28, + /* len */ 4 + }, + { /* name */ ONf, + /* lsp */ 16, + /* len */ 12 + }, + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 4 + }, + { /* name */ OFFf, + /* lsp */ 0, + /* len */ 12 + }, +}; + +rtk_regField_t FC_GLB_LO_THR_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 28, + /* len */ 4 + }, + { /* name */ ONf, + /* lsp */ 16, + /* len */ 12 + }, + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 4 + }, + { /* name */ OFFf, + /* lsp */ 0, + /* len */ 12 + }, +}; + +rtk_regField_t FC_GLB_FCOFF_HI_THR_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 28, + /* len */ 4 + }, + { /* name */ ONf, + /* lsp */ 16, + /* len */ 12 + }, + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 4 + }, + { /* name */ OFFf, + /* lsp */ 0, + /* len */ 12 + }, +}; + +rtk_regField_t FC_GLB_FCOFF_LO_THR_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 28, + /* len */ 4 + }, + { /* name */ ONf, + /* lsp */ 16, + /* len */ 12 + }, + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 4 + }, + { /* name */ OFFf, + /* lsp */ 0, + /* len */ 12 + }, +}; + +rtk_regField_t FC_JUMBO_HI_THR_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 28, + /* len */ 4 + }, + { /* name */ ONf, + /* lsp */ 16, + /* len */ 12 + }, + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 4 + }, + { /* name */ OFFf, + /* lsp */ 0, + /* len */ 12 + }, +}; + +rtk_regField_t FC_JUMBO_LO_THR_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 28, + /* len */ 4 + }, + { /* name */ ONf, + /* lsp */ 16, + /* len */ 12 + }, + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 4 + }, + { /* name */ OFFf, + /* lsp */ 0, + /* len */ 12 + }, +}; + +rtk_regField_t FC_JUMBO_FCOFF_HI_THR_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 28, + /* len */ 4 + }, + { /* name */ ONf, + /* lsp */ 16, + /* len */ 12 + }, + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 4 + }, + { /* name */ OFFf, + /* lsp */ 0, + /* len */ 12 + }, +}; + +rtk_regField_t FC_JUMBO_FCOFF_LO_THR_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 28, + /* len */ 4 + }, + { /* name */ ONf, + /* lsp */ 16, + /* len */ 12 + }, + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 4 + }, + { /* name */ OFFf, + /* lsp */ 0, + /* len */ 12 + }, +}; + +rtk_regField_t FC_JUMBO_THR_ADJUST_FIELDS[] = +{ + { /* name */ ENf, + /* lsp */ 31, + /* len */ 1 + }, + { /* name */ STSf, + /* lsp */ 30, + /* len */ 1 + }, + { /* name */ PKT_LENf, + /* lsp */ 16, + /* len */ 14 + }, + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 4 + }, + { /* name */ SYS_USED_PAGE_THRf, + /* lsp */ 0, + /* len */ 12 + }, +}; + +rtk_regField_t FC_PORT_HI_THR_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 28, + /* len */ 4 + }, + { /* name */ ONf, + /* lsp */ 16, + /* len */ 12 + }, + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 4 + }, + { /* name */ OFFf, + /* lsp */ 0, + /* len */ 12 + }, +}; + +rtk_regField_t FC_PORT_LO_THR_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 28, + /* len */ 4 + }, + { /* name */ ONf, + /* lsp */ 16, + /* len */ 12 + }, + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 4 + }, + { /* name */ OFFf, + /* lsp */ 0, + /* len */ 12 + }, +}; + +rtk_regField_t FC_PORT_FCOFF_HI_THR_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 28, + /* len */ 4 + }, + { /* name */ ONf, + /* lsp */ 16, + /* len */ 12 + }, + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 4 + }, + { /* name */ OFFf, + /* lsp */ 0, + /* len */ 12 + }, +}; + +rtk_regField_t FC_PORT_FCOFF_LO_THR_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 28, + /* len */ 4 + }, + { /* name */ ONf, + /* lsp */ 16, + /* len */ 12 + }, + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 4 + }, + { /* name */ OFFf, + /* lsp */ 0, + /* len */ 12 + }, +}; + +rtk_regField_t FC_PORT_GUAR_THR_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 20 + }, + { /* name */ THRf, + /* lsp */ 0, + /* len */ 12 + }, +}; + +rtk_regField_t FC_PORT_THR_SET_SEL_FIELDS[] = +{ + { /* name */ IDXf, + /* lsp */ 0, + /* len */ 2 + }, +}; + +rtk_regField_t FC_PORT_EGR_DROP_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 2, + /* len */ 30 + }, + { /* name */ REF_RXCNGSTf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ HOL_PRVNT_ENf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t FC_HOL_PRVNT_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 3, + /* len */ 29 + }, + { /* name */ BC_ENf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ L2_MC_ENf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ UNKN_UC_ENf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t FC_PORT_Q_EGR_DROP_CTRL_SET_FIELDS[] = +{ + { /* name */ ENf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t FC_PORT_Q_EGR_FORCE_DROP_CTRL_SET_FIELDS[] = +{ + { /* name */ ENf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t FC_Q_EGR_DROP_THR_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 28, + /* len */ 4 + }, + { /* name */ ONf, + /* lsp */ 16, + /* len */ 12 + }, + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 4 + }, + { /* name */ OFFf, + /* lsp */ 0, + /* len */ 12 + }, +}; + +rtk_regField_t FC_PORT_EGR_DROP_THR_SET_SEL_FIELDS[] = +{ + { /* name */ IDXf, + /* lsp */ 0, + /* len */ 2 + }, +}; + +rtk_regField_t FC_GLB_PAGE_CNT_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 20 + }, + { /* name */ GLB_PAGE_CNTf, + /* lsp */ 0, + /* len */ 12 + }, +}; + +rtk_regField_t FC_PORT_PAGE_CNT_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 20 + }, + { /* name */ P_PAGE_CNT_IGRf, + /* lsp */ 0, + /* len */ 12 + }, +}; + +rtk_regField_t FC_GLB_PAGE_PEAKCNT_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 20 + }, + { /* name */ GLB_PAGE_PEAKCNTf, + /* lsp */ 0, + /* len */ 12 + }, +}; + +rtk_regField_t FC_PORT_CUR_PAGE_CNT_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 20 + }, + { /* name */ P_PAGE_CURCNTf, + /* lsp */ 0, + /* len */ 12 + }, +}; + +rtk_regField_t FC_PORT_PEAK_PAGE_CNT_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 28, + /* len */ 4 + }, + { /* name */ GLB_PAGE_CURCNTf, + /* lsp */ 16, + /* len */ 12 + }, + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 4 + }, + { /* name */ P_PAGE_PEAKCNT_IGRf, + /* lsp */ 0, + /* len */ 12 + }, +}; + +rtk_regField_t FC_PORT_EGR_PAGE_CNT_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 28, + /* len */ 4 + }, + { /* name */ P_PAGE_PEAKCNT_EGRf, + /* lsp */ 16, + /* len */ 12 + }, + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 4 + }, + { /* name */ P_PAGE_CNT_EGRf, + /* lsp */ 0, + /* len */ 12 + }, +}; + +rtk_regField_t FC_PORT_Q_EGR_PAGE_CNT_SET_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 28, + /* len */ 4 + }, + { /* name */ Q_PAGE_PEAKCNTf, + /* lsp */ 16, + /* len */ 12 + }, + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 4 + }, + { /* name */ Q_PAGE_CNTf, + /* lsp */ 0, + /* len */ 12 + }, +}; + +rtk_regField_t FC_PORT_Q_EGR_PKT_CNT_SET_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 28, + /* len */ 4 + }, + { /* name */ Q_PKT_PEAKCNTf, + /* lsp */ 16, + /* len */ 12 + }, + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 4 + }, + { /* name */ Q_PKT_CNTf, + /* lsp */ 0, + /* len */ 12 + }, +}; + +rtk_regField_t FC_PORT_PAGE_CNT_ERROR_FIELDS[] = +{ + { /* name */ FLAGf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t PFC_ENABLE_0_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 25, + /* len */ 7 + }, + { /* name */ PORT_PFC_ENf, + /* lsp */ 24, + /* len */ 1 + }, + { /* name */ PRI_PFC_RX_ENf, + /* lsp */ 16, + /* len */ 8 + }, + { /* name */ PRI_PFC_TX_ENf, + /* lsp */ 8, + /* len */ 8 + }, + { /* name */ PRI_PFC_ENf, + /* lsp */ 0, + /* len */ 8 + }, +}; + +rtk_regField_t PFC_ENABLE_1_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 8, + /* len */ 24 + }, + { /* name */ PG_PFC_ENf, + /* lsp */ 0, + /* len */ 8 + }, +}; + +rtk_regField_t PFC_CTRL_0_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 15, + /* len */ 17 + }, + { /* name */ UNTAG_PRI_SRCf, + /* lsp */ 14, + /* len */ 1 + }, + { /* name */ PFC_PCPSRC_SELf, + /* lsp */ 12, + /* len */ 2 + }, + { /* name */ PFC_PCP_UTAGf, + /* lsp */ 9, + /* len */ 3 + }, + { /* name */ PFC_MODE_SELf, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ PFC_STSPRIf, + /* lsp */ 0, + /* len */ 8 + }, +}; + +rtk_regField_t PFC_ACTDROP_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 13, + /* len */ 19 + }, + { /* name */ PFC_ACTDROP_PG_ENf, + /* lsp */ 12, + /* len */ 1 + }, + { /* name */ PFC_ALLOWPAGE_CNTf, + /* lsp */ 0, + /* len */ 12 + }, +}; + +rtk_regField_t P_PFC_THR_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 28, + /* len */ 4 + }, + { /* name */ ONf, + /* lsp */ 16, + /* len */ 12 + }, + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 4 + }, + { /* name */ OFFf, + /* lsp */ 0, + /* len */ 12 + }, +}; + +rtk_regField_t P_PFCOFF_THR_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 28, + /* len */ 4 + }, + { /* name */ ONf, + /* lsp */ 16, + /* len */ 12 + }, + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 4 + }, + { /* name */ OFFf, + /* lsp */ 0, + /* len */ 12 + }, +}; + +rtk_regField_t PG_HI_THR_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 28, + /* len */ 4 + }, + { /* name */ ONf, + /* lsp */ 16, + /* len */ 12 + }, + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 4 + }, + { /* name */ OFFf, + /* lsp */ 0, + /* len */ 12 + }, +}; + +rtk_regField_t PG_LO_THR_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 28, + /* len */ 4 + }, + { /* name */ ONf, + /* lsp */ 16, + /* len */ 12 + }, + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 4 + }, + { /* name */ OFFf, + /* lsp */ 0, + /* len */ 12 + }, +}; + +rtk_regField_t PG_PFCOFF_HI_THR_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 28, + /* len */ 4 + }, + { /* name */ ONf, + /* lsp */ 16, + /* len */ 12 + }, + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 4 + }, + { /* name */ OFFf, + /* lsp */ 0, + /* len */ 12 + }, +}; + +rtk_regField_t PG_PFCOFF_LO_THR_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 28, + /* len */ 4 + }, + { /* name */ ONf, + /* lsp */ 16, + /* len */ 12 + }, + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 4 + }, + { /* name */ OFFf, + /* lsp */ 0, + /* len */ 12 + }, +}; + +rtk_regField_t PG_GURANTEE_THR_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 28, + /* len */ 4 + }, + { /* name */ PG_PFCON_GURANTEE_THRf, + /* lsp */ 16, + /* len */ 12 + }, + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 4 + }, + { /* name */ PG_PFCOFF_GURANTEE_THRf, + /* lsp */ 0, + /* len */ 12 + }, +}; + +rtk_regField_t PFC_CTRL_1_FIELDS[] = +{ + { /* name */ PFC_PG_FORCE_CNG_ENf, + /* lsp */ 24, + /* len */ 8 + }, + { /* name */ PFC_PG_FORCE_CNG_VALUEf, + /* lsp */ 16, + /* len */ 8 + }, + { /* name */ PFC_PG_ISCNGf, + /* lsp */ 8, + /* len */ 8 + }, + { /* name */ P_PG_REF_PORTf, + /* lsp */ 0, + /* len */ 8 + }, +}; + +rtk_regField_t PFC_CTRL_2_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ PFC_STSPRI_FORCE_ENf, + /* lsp */ 8, + /* len */ 8 + }, + { /* name */ PFC_STSPRI_FORCE_VALUEf, + /* lsp */ 0, + /* len */ 8 + }, +}; + +rtk_regField_t PG_2_PEV_TABLE_FIELDS[] = +{ + { /* name */ PG7_PEV_MAPf, + /* lsp */ 56, + /* len */ 8 + }, + { /* name */ PG6_PEV_MAPf, + /* lsp */ 48, + /* len */ 8 + }, + { /* name */ PG5_PEV_MAPf, + /* lsp */ 40, + /* len */ 8 + }, + { /* name */ PG4_PEV_MAPf, + /* lsp */ 32, + /* len */ 8 + }, + { /* name */ PG3_PEV_MAPf, + /* lsp */ 24, + /* len */ 8 + }, + { /* name */ PG2_PEV_MAPf, + /* lsp */ 16, + /* len */ 8 + }, + { /* name */ PG1_PEV_MAPf, + /* lsp */ 8, + /* len */ 8 + }, + { /* name */ PG0_PEV_MAPf, + /* lsp */ 0, + /* len */ 8 + }, +}; + +rtk_regField_t DPRI_2_PG_TABLE_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 24, + /* len */ 8 + }, + { /* name */ DPRI7_PG_MAPf, + /* lsp */ 21, + /* len */ 3 + }, + { /* name */ DPRI6_PG_MAPf, + /* lsp */ 18, + /* len */ 3 + }, + { /* name */ DPRI5_PG_MAPf, + /* lsp */ 15, + /* len */ 3 + }, + { /* name */ DPRI4_PG_MAPf, + /* lsp */ 12, + /* len */ 3 + }, + { /* name */ DPRI3_PG_MAPf, + /* lsp */ 9, + /* len */ 3 + }, + { /* name */ DPRI2_PG_MAPf, + /* lsp */ 6, + /* len */ 3 + }, + { /* name */ DPRI1_PG_MAPf, + /* lsp */ 3, + /* len */ 3 + }, + { /* name */ DPRI0_PG_MAPf, + /* lsp */ 0, + /* len */ 3 + }, +}; + +rtk_regField_t PCP_2_PG_TABLE_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 24, + /* len */ 8 + }, + { /* name */ PCP7_PG_MAPf, + /* lsp */ 21, + /* len */ 3 + }, + { /* name */ PCP6_PG_MAPf, + /* lsp */ 18, + /* len */ 3 + }, + { /* name */ PCP5_PG_MAPf, + /* lsp */ 15, + /* len */ 3 + }, + { /* name */ PCP4_PG_MAPf, + /* lsp */ 12, + /* len */ 3 + }, + { /* name */ PCP3_PG_MAPf, + /* lsp */ 9, + /* len */ 3 + }, + { /* name */ PCP2_PG_MAPf, + /* lsp */ 6, + /* len */ 3 + }, + { /* name */ PCP1_PG_MAPf, + /* lsp */ 3, + /* len */ 3 + }, + { /* name */ PCP0_PG_MAPf, + /* lsp */ 0, + /* len */ 3 + }, +}; + +rtk_regField_t PEV_2_TXQ_TABLE_FIELDS[] = +{ + { /* name */ PEV7_TXQ_MAPf, + /* lsp */ 56, + /* len */ 8 + }, + { /* name */ PEV6_TXQ_MAPf, + /* lsp */ 48, + /* len */ 8 + }, + { /* name */ PEV5_TXQ_MAPf, + /* lsp */ 40, + /* len */ 8 + }, + { /* name */ PEV4_TXQ_MAPf, + /* lsp */ 32, + /* len */ 8 + }, + { /* name */ PEV3_TXQ_MAPf, + /* lsp */ 24, + /* len */ 8 + }, + { /* name */ PEV2_TXQ_MAPf, + /* lsp */ 16, + /* len */ 8 + }, + { /* name */ PEV1_TXQ_MAPf, + /* lsp */ 8, + /* len */ 8 + }, + { /* name */ PEV0_TXQ_MAPf, + /* lsp */ 0, + /* len */ 8 + }, +}; + +rtk_regField_t PFC_PORT_PG_RX_PAGE_CNT_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 28, + /* len */ 4 + }, + { /* name */ PG_PAGE_PEAKCNTf, + /* lsp */ 16, + /* len */ 12 + }, + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 4 + }, + { /* name */ PG_PAGE_CNTf, + /* lsp */ 0, + /* len */ 12 + }, +}; + +/* Module: Congestion Avoidance */ +rtk_regField_t SC_P_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 28, + /* len */ 4 + }, + { /* name */ DRAIN_OUT_THR_Hf, + /* lsp */ 16, + /* len */ 12 + }, + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 4 + }, + { /* name */ DRAIN_OUT_THRf, + /* lsp */ 0, + /* len */ 12 + }, +}; + +rtk_regField_t SC_P_EN_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 24, + /* len */ 8 + }, + { /* name */ CNGST_TMR_Hf, + /* lsp */ 20, + /* len */ 4 + }, + { /* name */ CNGST_SUST_TMR_LMT_Hf, + /* lsp */ 16, + /* len */ 4 + }, + { /* name */ RESERVEDf, + /* lsp */ 8, + /* len */ 8 + }, + { /* name */ CNGST_TMRf, + /* lsp */ 4, + /* len */ 4 + }, + { /* name */ CNGST_SUST_TMR_LMTf, + /* lsp */ 0, + /* len */ 4 + }, +}; + +/* Module: Ingress Priority Decision */ +rtk_regField_t PORT_PRI_FIELDS[] = +{ + { /* name */ PORT_BASE_PRIf, + /* lsp */ 0, + /* len */ 3 + }, +}; + +rtk_regField_t DOT1Q_PRI_REMAP_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 31, + /* len */ 1 + }, + { /* name */ PRI7f, + /* lsp */ 28, + /* len */ 3 + }, + { /* name */ RESERVEDf, + /* lsp */ 27, + /* len */ 1 + }, + { /* name */ PRI6f, + /* lsp */ 24, + /* len */ 3 + }, + { /* name */ RESERVEDf, + /* lsp */ 23, + /* len */ 1 + }, + { /* name */ PRI5f, + /* lsp */ 20, + /* len */ 3 + }, + { /* name */ RESERVEDf, + /* lsp */ 19, + /* len */ 1 + }, + { /* name */ PRI4f, + /* lsp */ 16, + /* len */ 3 + }, + { /* name */ RESERVEDf, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ PRI3f, + /* lsp */ 12, + /* len */ 3 + }, + { /* name */ RESERVEDf, + /* lsp */ 11, + /* len */ 1 + }, + { /* name */ PRI2f, + /* lsp */ 8, + /* len */ 3 + }, + { /* name */ RESERVEDf, + /* lsp */ 7, + /* len */ 1 + }, + { /* name */ PRI1f, + /* lsp */ 4, + /* len */ 3 + }, + { /* name */ RESERVEDf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ PRI0f, + /* lsp */ 0, + /* len */ 3 + }, +}; + +rtk_regField_t PRI_SEL_REMAP_DSCP_FIELDS[] = +{ + { /* name */ INTPRI_DSCPf, + /* lsp */ 0, + /* len */ 3 + }, +}; + +rtk_regField_t RSPAN_PRI_REMAP_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 31, + /* len */ 1 + }, + { /* name */ PRI7f, + /* lsp */ 28, + /* len */ 3 + }, + { /* name */ RESERVEDf, + /* lsp */ 27, + /* len */ 1 + }, + { /* name */ PRI6f, + /* lsp */ 24, + /* len */ 3 + }, + { /* name */ RESERVEDf, + /* lsp */ 23, + /* len */ 1 + }, + { /* name */ PRI5f, + /* lsp */ 20, + /* len */ 3 + }, + { /* name */ RESERVEDf, + /* lsp */ 19, + /* len */ 1 + }, + { /* name */ PRI4f, + /* lsp */ 16, + /* len */ 3 + }, + { /* name */ RESERVEDf, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ PRI3f, + /* lsp */ 12, + /* len */ 3 + }, + { /* name */ RESERVEDf, + /* lsp */ 11, + /* len */ 1 + }, + { /* name */ PRI2f, + /* lsp */ 8, + /* len */ 3 + }, + { /* name */ RESERVEDf, + /* lsp */ 7, + /* len */ 1 + }, + { /* name */ PRI1f, + /* lsp */ 4, + /* len */ 3 + }, + { /* name */ RESERVEDf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ PRI0f, + /* lsp */ 0, + /* len */ 3 + }, +}; + +rtk_regField_t PRI_WEIGHT_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 25, + /* len */ 7 + }, + { /* name */ SVLAN_WEIGHTf, + /* lsp */ 20, + /* len */ 5 + }, + { /* name */ ACL_WEIGHTf, + /* lsp */ 15, + /* len */ 5 + }, + { /* name */ DSCP_WEIGHTf, + /* lsp */ 10, + /* len */ 5 + }, + { /* name */ PORT_WEIGHTf, + /* lsp */ 5, + /* len */ 5 + }, + { /* name */ DOT1Q_WEIGHTf, + /* lsp */ 0, + /* len */ 5 + }, +}; + +rtk_regField_t PORT_WEIGHT_SEL_FIELDS[] = +{ + { /* name */ WEIGHT_SELf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t QID_TO_PRI_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 31, + /* len */ 1 + }, + { /* name */ PRI7QNUMf, + /* lsp */ 28, + /* len */ 3 + }, + { /* name */ RESERVEDf, + /* lsp */ 27, + /* len */ 1 + }, + { /* name */ PRI6QNUMf, + /* lsp */ 24, + /* len */ 3 + }, + { /* name */ RESERVEDf, + /* lsp */ 23, + /* len */ 1 + }, + { /* name */ PRI5QNUMf, + /* lsp */ 20, + /* len */ 3 + }, + { /* name */ RESERVEDf, + /* lsp */ 19, + /* len */ 1 + }, + { /* name */ PRI4QNUMf, + /* lsp */ 16, + /* len */ 3 + }, + { /* name */ RESERVEDf, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ PRI3QNUMf, + /* lsp */ 12, + /* len */ 3 + }, + { /* name */ RESERVEDf, + /* lsp */ 11, + /* len */ 1 + }, + { /* name */ PRI2QNUMf, + /* lsp */ 8, + /* len */ 3 + }, + { /* name */ RESERVEDf, + /* lsp */ 7, + /* len */ 1 + }, + { /* name */ PRI1QNUMf, + /* lsp */ 4, + /* len */ 3 + }, + { /* name */ RESERVEDf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ PRI0QNUMf, + /* lsp */ 0, + /* len */ 3 + }, +}; + +rtk_regField_t INCPU_PRI_REMAP_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 31, + /* len */ 1 + }, + { /* name */ INTPRI7_TO_VALf, + /* lsp */ 28, + /* len */ 3 + }, + { /* name */ RESERVEDf, + /* lsp */ 27, + /* len */ 1 + }, + { /* name */ INTPRI6_TO_VALf, + /* lsp */ 24, + /* len */ 3 + }, + { /* name */ RESERVEDf, + /* lsp */ 23, + /* len */ 1 + }, + { /* name */ INTPRI5_TO_VALf, + /* lsp */ 20, + /* len */ 3 + }, + { /* name */ RESERVEDf, + /* lsp */ 19, + /* len */ 1 + }, + { /* name */ INTPRI4_TO_VALf, + /* lsp */ 16, + /* len */ 3 + }, + { /* name */ RESERVEDf, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ INTPRI3_TO_VALf, + /* lsp */ 12, + /* len */ 3 + }, + { /* name */ RESERVEDf, + /* lsp */ 11, + /* len */ 1 + }, + { /* name */ INTPRI2_TO_VALf, + /* lsp */ 8, + /* len */ 3 + }, + { /* name */ RESERVEDf, + /* lsp */ 7, + /* len */ 1 + }, + { /* name */ INTPRI1_TO_VALf, + /* lsp */ 4, + /* len */ 3 + }, + { /* name */ RESERVEDf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ INTPRI0_TO_VALf, + /* lsp */ 0, + /* len */ 3 + }, +}; + +rtk_regField_t EXCPU_PRI_REMAP_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 31, + /* len */ 1 + }, + { /* name */ INTPRI7_TO_VALf, + /* lsp */ 28, + /* len */ 3 + }, + { /* name */ RESERVEDf, + /* lsp */ 27, + /* len */ 1 + }, + { /* name */ INTPRI6_TO_VALf, + /* lsp */ 24, + /* len */ 3 + }, + { /* name */ RESERVEDf, + /* lsp */ 23, + /* len */ 1 + }, + { /* name */ INTPRI5_TO_VALf, + /* lsp */ 20, + /* len */ 3 + }, + { /* name */ RESERVEDf, + /* lsp */ 19, + /* len */ 1 + }, + { /* name */ INTPRI4_TO_VALf, + /* lsp */ 16, + /* len */ 3 + }, + { /* name */ RESERVEDf, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ INTPRI3_TO_VALf, + /* lsp */ 12, + /* len */ 3 + }, + { /* name */ RESERVEDf, + /* lsp */ 11, + /* len */ 1 + }, + { /* name */ INTPRI2_TO_VALf, + /* lsp */ 8, + /* len */ 3 + }, + { /* name */ RESERVEDf, + /* lsp */ 7, + /* len */ 1 + }, + { /* name */ INTPRI1_TO_VALf, + /* lsp */ 4, + /* len */ 3 + }, + { /* name */ RESERVEDf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ INTPRI0_TO_VALf, + /* lsp */ 0, + /* len */ 3 + }, +}; + +rtk_regField_t PORT_PRI_DUP_FIELDS[] = +{ + { /* name */ PORT_BASE_PRI_DUPf, + /* lsp */ 0, + /* len */ 3 + }, +}; + +/* Module: Scheduling & Queue Management */ +rtk_regField_t SCHED_PORT_Q_CTRL_SET_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 8, + /* len */ 24 + }, + { /* name */ STRICT_ENf, + /* lsp */ 7, + /* len */ 1 + }, + { /* name */ WEIGHTf, + /* lsp */ 0, + /* len */ 7 + }, +}; + +rtk_regField_t SCHED_PORT_ALGO_CTRL_FIELDS[] = +{ + { /* name */ SCHED_TYPEf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t CFG_TG_URR_SEL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 2, + /* len */ 30 + }, + { /* name */ CFG_TG_URR_SELf, + /* lsp */ 0, + /* len */ 2 + }, +}; + +/* Module: Remarking */ +rtk_regField_t RMK_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 2, + /* len */ 30 + }, + { /* name */ IPRI_RMK_SRCf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ DSCP_RMK_SRCf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t RMK_PORT_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 2, + /* len */ 30 + }, + { /* name */ DSCP_RMK_ENf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ IPRI_RMK_ENf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t RMK_INTPRI2IPRI_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 31, + /* len */ 1 + }, + { /* name */ IPRI7f, + /* lsp */ 28, + /* len */ 3 + }, + { /* name */ RESERVEDf, + /* lsp */ 27, + /* len */ 1 + }, + { /* name */ IPRI6f, + /* lsp */ 24, + /* len */ 3 + }, + { /* name */ RESERVEDf, + /* lsp */ 23, + /* len */ 1 + }, + { /* name */ IPRI5f, + /* lsp */ 20, + /* len */ 3 + }, + { /* name */ RESERVEDf, + /* lsp */ 19, + /* len */ 1 + }, + { /* name */ IPRI4f, + /* lsp */ 16, + /* len */ 3 + }, + { /* name */ RESERVEDf, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ IPRI3f, + /* lsp */ 12, + /* len */ 3 + }, + { /* name */ RESERVEDf, + /* lsp */ 11, + /* len */ 1 + }, + { /* name */ IPRI2f, + /* lsp */ 8, + /* len */ 3 + }, + { /* name */ RESERVEDf, + /* lsp */ 7, + /* len */ 1 + }, + { /* name */ IPRI1f, + /* lsp */ 4, + /* len */ 3 + }, + { /* name */ RESERVEDf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ IPRI0f, + /* lsp */ 0, + /* len */ 3 + }, +}; + +rtk_regField_t RMK_INTPRI2DSCP_CTRL_FIELDS[] = +{ + { /* name */ DSCPf, + /* lsp */ 0, + /* len */ 6 + }, +}; + +rtk_regField_t RMK_DSCP2DSCP_CTRL_FIELDS[] = +{ + { /* name */ DSCPf, + /* lsp */ 0, + /* len */ 6 + }, +}; + +/* Module: 802.1X */ +rtk_regField_t DOT1X_PORT_EN_FIELDS[] = +{ + { /* name */ PORT_ENf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t DOT1X_MAC_EN_FIELDS[] = +{ + { /* name */ MAC_ENf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t DOT1X_PORT_AUTH_FIELDS[] = +{ + { /* name */ PORT_AUTHf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t DOT1X_PORT_DIR_FIELDS[] = +{ + { /* name */ PORT_DIRf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t DOT1X_TRAP_PRIORITY_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 3, + /* len */ 29 + }, + { /* name */ TRAP_PRIf, + /* lsp */ 0, + /* len */ 3 + }, +}; + +rtk_regField_t DOT1X_UNAUTH_ACT_FIELDS[] = +{ + { /* name */ PORT_ACTf, + /* lsp */ 0, + /* len */ 2 + }, +}; + +rtk_regField_t DOT1X_TRAP_CPU_SEL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 2, + /* len */ 30 + }, + { /* name */ TRAP_CPU_SELf, + /* lsp */ 0, + /* len */ 2 + }, +}; + +rtk_regField_t DOT1X_CFG_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 14, + /* len */ 18 + }, + { /* name */ GUSET_OPf, + /* lsp */ 13, + /* len */ 1 + }, + { /* name */ MAC_DIRf, + /* lsp */ 12, + /* len */ 1 + }, + { /* name */ GUEST_VIDf, + /* lsp */ 0, + /* len */ 12 + }, +}; + +/* Module: Attack Prevention */ +rtk_regField_t ATK_PRVNT_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 11, + /* len */ 21 + }, + { /* name */ ICMPFRAGMENTf, + /* lsp */ 10, + /* len */ 1 + }, + { /* name */ TCPFRAGERRf, + /* lsp */ 9, + /* len */ 1 + }, + { /* name */ TCPSHORTHDRf, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ SYN1024f, + /* lsp */ 7, + /* len */ 1 + }, + { /* name */ NULLSCANf, + /* lsp */ 6, + /* len */ 1 + }, + { /* name */ XMASCANf, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ SYNFINSCANf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ BLATf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ LAND_V6f, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ LAND_V4f, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ DAEQSAf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t MIN_TCPHDR_LEN_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 5, + /* len */ 27 + }, + { /* name */ LENf, + /* lsp */ 0, + /* len */ 5 + }, +}; + +/* Module: WOL */ +rtk_regField_t WOL_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 11, + /* len */ 21 + }, + { /* name */ WOL_ENf, + /* lsp */ 10, + /* len */ 1 + }, + { /* name */ WOL_PMSKf, + /* lsp */ 0, + /* len */ 10 + }, +}; + +rtk_regField_t WOL_MAC0_FIELDS[] = +{ + { /* name */ WOL_MAC_0_31f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t WOL_MAC1_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ WOL_MAC_32_47f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t PHY_WOL_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 1, + /* len */ 31 + }, + { /* name */ PHY_WOL_ENf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t PHY_WOL_MAC0_FIELDS[] = +{ + { /* name */ PHY_WOL_MAC_0_31f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t PHY_WOL_MAC1_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ PHY_WOL_MAC_32_47f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +/* Module: Parser */ +rtk_regField_t PARSER_FIELD_SELTOR_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 11, + /* len */ 21 + }, + { /* name */ OFFSETf, + /* lsp */ 3, + /* len */ 8 + }, + { /* name */ FMTf, + /* lsp */ 0, + /* len */ 3 + }, +}; + +rtk_regField_t PARSER_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 1, + /* len */ 31 + }, + { /* name */ RFC1042_OUI_IGNOREf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t PARSER_DROP_REASON_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 4, + /* len */ 28 + }, + { /* name */ REASONf, + /* lsp */ 0, + /* len */ 4 + }, +}; + +/* Module: Parser HSB */ +rtk_regField_t HSB_DATA0_FIELDS[] = +{ + { /* name */ DMAC17_0f, + /* lsp */ 14, + /* len */ 18 + }, + { /* name */ PKE_LENf, + /* lsp */ 0, + /* len */ 14 + }, +}; + +rtk_regField_t HSB_DATA1_FIELDS[] = +{ + { /* name */ SMAC1_0f, + /* lsp */ 30, + /* len */ 2 + }, + { /* name */ DMAC47_18f, + /* lsp */ 0, + /* len */ 30 + }, +}; + +rtk_regField_t HSB_DATA2_FIELDS[] = +{ + { /* name */ SMAC33_2f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t HSB_DATA3_FIELDS[] = +{ + { /* name */ CPUTAG16_0f, + /* lsp */ 15, + /* len */ 17 + }, + { /* name */ CPUTAG_IFf, + /* lsp */ 14, + /* len */ 1 + }, + { /* name */ SMAC47_34f, + /* lsp */ 0, + /* len */ 14 + }, +}; + +rtk_regField_t HSB_DATA4_FIELDS[] = +{ + { /* name */ STAGf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ STAG_IFf, + /* lsp */ 15, + /* len */ 1 + }, + { /* name */ CPUTAG31_17f, + /* lsp */ 0, + /* len */ 15 + }, +}; + +rtk_regField_t HSB_DATA5_FIELDS[] = +{ + { /* name */ ETYPE13_0f, + /* lsp */ 18, + /* len */ 14 + }, + { /* name */ RTAG_IFf, + /* lsp */ 17, + /* len */ 1 + }, + { /* name */ CTAGf, + /* lsp */ 1, + /* len */ 16 + }, + { /* name */ CTAG_IFf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t HSB_DATA6_FIELDS[] = +{ + { /* name */ DIP16_0f, + /* lsp */ 15, + /* len */ 17 + }, + { /* name */ IGMPf, + /* lsp */ 14, + /* len */ 1 + }, + { /* name */ ICMPf, + /* lsp */ 13, + /* len */ 1 + }, + { /* name */ UDPf, + /* lsp */ 12, + /* len */ 1 + }, + { /* name */ TCPf, + /* lsp */ 11, + /* len */ 1 + }, + { /* name */ IPTYPEf, + /* lsp */ 9, + /* len */ 2 + }, + { /* name */ ARPf, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ OAMf, + /* lsp */ 7, + /* len */ 1 + }, + { /* name */ RLPPf, + /* lsp */ 6, + /* len */ 1 + }, + { /* name */ RLDPf, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ RRCPf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ PPPOEf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ SNAPf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ ETYPE15_14f, + /* lsp */ 0, + /* len */ 2 + }, +}; + +rtk_regField_t HSB_DATA7_FIELDS[] = +{ + { /* name */ SIP16_0f, + /* lsp */ 15, + /* len */ 17 + }, + { /* name */ DIP31_17f, + /* lsp */ 0, + /* len */ 15 + }, +}; + +rtk_regField_t HSB_DATA8_FIELDS[] = +{ + { /* name */ L4SPORT0f, + /* lsp */ 31, + /* len */ 1 + }, + { /* name */ L4DPORTf, + /* lsp */ 15, + /* len */ 16 + }, + { /* name */ SIP31_17f, + /* lsp */ 0, + /* len */ 15 + }, +}; + +rtk_regField_t HSB_DATA9_FIELDS[] = +{ + { /* name */ UDV0f, + /* lsp */ 31, + /* len */ 1 + }, + { /* name */ TOSf, + /* lsp */ 15, + /* len */ 16 + }, + { /* name */ L4SPORT15_1f, + /* lsp */ 0, + /* len */ 15 + }, +}; + +rtk_regField_t HSB_DATA10_FIELDS[] = +{ + { /* name */ UDF1_0_0f, + /* lsp */ 31, + /* len */ 1 + }, + { /* name */ UDF0f, + /* lsp */ 15, + /* len */ 16 + }, + { /* name */ UDV15f, + /* lsp */ 14, + /* len */ 1 + }, + { /* name */ UDV14f, + /* lsp */ 13, + /* len */ 1 + }, + { /* name */ UDV13f, + /* lsp */ 12, + /* len */ 1 + }, + { /* name */ UDV12f, + /* lsp */ 11, + /* len */ 1 + }, + { /* name */ UDV11f, + /* lsp */ 10, + /* len */ 1 + }, + { /* name */ UDV10f, + /* lsp */ 9, + /* len */ 1 + }, + { /* name */ UDV9f, + /* lsp */ 8, + /* len */ 1 + }, + { /* name */ UDV8f, + /* lsp */ 7, + /* len */ 1 + }, + { /* name */ UDV7f, + /* lsp */ 6, + /* len */ 1 + }, + { /* name */ UDV6f, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ UDV5f, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ UDV4f, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ UDV3f, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ UDV2f, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ UDV1f, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t HSB_DATA11_FIELDS[] = +{ + { /* name */ UDF3_0_0f, + /* lsp */ 31, + /* len */ 1 + }, + { /* name */ UDF2f, + /* lsp */ 15, + /* len */ 16 + }, + { /* name */ UDF1_15_1f, + /* lsp */ 0, + /* len */ 15 + }, +}; + +rtk_regField_t HSB_DATA12_FIELDS[] = +{ + { /* name */ UDF5_0_0f, + /* lsp */ 31, + /* len */ 1 + }, + { /* name */ UDF4f, + /* lsp */ 15, + /* len */ 16 + }, + { /* name */ UDF3_15_1f, + /* lsp */ 0, + /* len */ 15 + }, +}; + +rtk_regField_t HSB_DATA13_FIELDS[] = +{ + { /* name */ UDF7_0_0f, + /* lsp */ 31, + /* len */ 1 + }, + { /* name */ UDF6f, + /* lsp */ 15, + /* len */ 16 + }, + { /* name */ UDF5_15_1f, + /* lsp */ 0, + /* len */ 15 + }, +}; + +rtk_regField_t HSB_DATA14_FIELDS[] = +{ + { /* name */ UDF9_0_0f, + /* lsp */ 31, + /* len */ 1 + }, + { /* name */ UDF8f, + /* lsp */ 15, + /* len */ 16 + }, + { /* name */ UDF7_15_1f, + /* lsp */ 0, + /* len */ 15 + }, +}; + +rtk_regField_t HSB_DATA15_FIELDS[] = +{ + { /* name */ UDF11_0_0f, + /* lsp */ 31, + /* len */ 1 + }, + { /* name */ UDF10f, + /* lsp */ 15, + /* len */ 16 + }, + { /* name */ UDF9_15_1f, + /* lsp */ 0, + /* len */ 15 + }, +}; + +rtk_regField_t HSB_DATA16_FIELDS[] = +{ + { /* name */ UDF13_0_0f, + /* lsp */ 31, + /* len */ 1 + }, + { /* name */ UDF12f, + /* lsp */ 15, + /* len */ 16 + }, + { /* name */ UDF11_15_1f, + /* lsp */ 0, + /* len */ 15 + }, +}; + +rtk_regField_t HSB_DATA17_FIELDS[] = +{ + { /* name */ UDF15_0_0f, + /* lsp */ 31, + /* len */ 1 + }, + { /* name */ UDF14f, + /* lsp */ 15, + /* len */ 16 + }, + { /* name */ UDF13_15_1f, + /* lsp */ 0, + /* len */ 15 + }, +}; + +rtk_regField_t HSB_DATA18_FIELDS[] = +{ + { /* name */ BDSC6_0f, + /* lsp */ 25, + /* len */ 7 + }, + { /* name */ L3ERRf, + /* lsp */ 24, + /* len */ 1 + }, + { /* name */ ERRPKTf, + /* lsp */ 23, + /* len */ 1 + }, + { /* name */ INGR_ERRf, + /* lsp */ 22, + /* len */ 1 + }, + { /* name */ UDPPTPf, + /* lsp */ 21, + /* len */ 1 + }, + { /* name */ L2PTPf, + /* lsp */ 20, + /* len */ 1 + }, + { /* name */ WOLf, + /* lsp */ 19, + /* len */ 1 + }, + { /* name */ RXPORTf, + /* lsp */ 15, + /* len */ 4 + }, + { /* name */ UDF15_15_1f, + /* lsp */ 0, + /* len */ 15 + }, +}; + +rtk_regField_t HSB_DATA19_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 17, + /* len */ 15 + }, + { /* name */ EDSCf, + /* lsp */ 5, + /* len */ 12 + }, + { /* name */ BDSC11_7f, + /* lsp */ 0, + /* len */ 5 + }, +}; + +rtk_regField_t HSB_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 1, + /* len */ 31 + }, + { /* name */ READHSBf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +/* Module: RLDP & RLPP */ +rtk_regField_t RLDP_RLPP_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 17, + /* len */ 15 + }, + { /* name */ FRC_LOOP_MASKf, + /* lsp */ 7, + /* len */ 10 + }, + { /* name */ RLPP_TRAPf, + /* lsp */ 6, + /* len */ 1 + }, + { /* name */ RLDP_MODEf, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ INDICATORf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ GEN_RANDOMf, + /* lsp */ 3, + /* len */ 1 + }, + { /* name */ COMP_IDf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ RLDP_ICPU_ENf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ RLDP_ENf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t RETRY_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RETRY_LOOPf, + /* lsp */ 8, + /* len */ 8 + }, + { /* name */ RETRY_CHKf, + /* lsp */ 0, + /* len */ 8 + }, +}; + +rtk_regField_t PERIOD_CTRL_FIELDS[] = +{ + { /* name */ PERIOD_LOOPf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ PERIOD_CHKf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t RLDP_TX_PMSK_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 10, + /* len */ 22 + }, + { /* name */ PMSKf, + /* lsp */ 0, + /* len */ 10 + }, +}; + +rtk_regField_t RAND_NUM0_FIELDS[] = +{ + { /* name */ RAN0_31f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t RAND_NUM1_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ RAN32_47f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t MAGIC_NUM0_FIELDS[] = +{ + { /* name */ MGC0_31f, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t MAGIC_NUM1_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ MGC32_47f, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t LOOP_STATE_FIELDS[] = +{ + { /* name */ LOOP_PMSKf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t LOOPED_STATE_FIELDS[] = +{ + { /* name */ LOOPED_PMSKf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t LEAVE_LOOP_STATE_FIELDS[] = +{ + { /* name */ LEAVE_LOOP_PMSKf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t LOOPPAIR_FIELDS[] = +{ + { /* name */ LOOP_PAIRf, + /* lsp */ 0, + /* len */ 4 + }, +}; + +rtk_regField_t RRCP_CTRL_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 2, + /* len */ 30 + }, + { /* name */ RRCP_TRAPf, + /* lsp */ 0, + /* len */ 2 + }, +}; + +/* Module: Auto Recovery */ +rtk_regField_t RXPORT_DSC_STS_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 26, + /* len */ 6 + }, + { /* name */ RXPORT_DSC_STSf, + /* lsp */ 16, + /* len */ 10 + }, + { /* name */ RESERVEDf, + /* lsp */ 10, + /* len */ 6 + }, + { /* name */ RXPORT_DSC_ERRf, + /* lsp */ 0, + /* len */ 10 + }, +}; + +rtk_regField_t SW_Q_RST_THR_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 20 + }, + { /* name */ SW_Q_RST_SYS_THRf, + /* lsp */ 0, + /* len */ 12 + }, +}; + +rtk_regField_t SW_Q_RST_P_THR_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 12, + /* len */ 20 + }, + { /* name */ SW_Q_RST_P_THRf, + /* lsp */ 0, + /* len */ 12 + }, +}; + +rtk_regField_t LD_TX_DSC_STS_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 26, + /* len */ 6 + }, + { /* name */ LD_TX_DSC_STSf, + /* lsp */ 16, + /* len */ 10 + }, + { /* name */ RESERVEDf, + /* lsp */ 10, + /* len */ 6 + }, + { /* name */ LD_TX_DSC_ERRf, + /* lsp */ 0, + /* len */ 10 + }, +}; + +rtk_regField_t TX_DSC_CHK_TMR_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 8, + /* len */ 24 + }, + { /* name */ TX_DSC_CHK_TMRf, + /* lsp */ 0, + /* len */ 8 + }, +}; + +rtk_regField_t RXFIFO_OVERFLOW_STS_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 26, + /* len */ 6 + }, + { /* name */ RXFIFO_OVERFLOW_STSf, + /* lsp */ 16, + /* len */ 10 + }, + { /* name */ RESERVEDf, + /* lsp */ 10, + /* len */ 6 + }, + { /* name */ RXFIFO_OVERFLOW_ERRf, + /* lsp */ 0, + /* len */ 10 + }, +}; + +rtk_regField_t RXFIFO_RDEMPTY_STS_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 26, + /* len */ 6 + }, + { /* name */ RXFIFO_RDEMPTY_STSf, + /* lsp */ 16, + /* len */ 10 + }, + { /* name */ RESERVEDf, + /* lsp */ 10, + /* len */ 6 + }, + { /* name */ RXFIFO_RDEMPTY_ERRf, + /* lsp */ 0, + /* len */ 10 + }, +}; + +rtk_regField_t TXFIFO_OVERFLOW_STS_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 26, + /* len */ 6 + }, + { /* name */ TXFIFO_OVERFLOW_STSf, + /* lsp */ 16, + /* len */ 10 + }, + { /* name */ RESERVEDf, + /* lsp */ 10, + /* len */ 6 + }, + { /* name */ TXFIFO_OVERFLOW_ERRf, + /* lsp */ 0, + /* len */ 10 + }, +}; + +rtk_regField_t TXFIFO_RDEMPTY_STS_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 26, + /* len */ 6 + }, + { /* name */ TXFIFO_RDEMPTY_STSf, + /* lsp */ 16, + /* len */ 10 + }, + { /* name */ RESERVEDf, + /* lsp */ 10, + /* len */ 6 + }, + { /* name */ TXFIFO_RDEMPTY_ERRf, + /* lsp */ 0, + /* len */ 10 + }, +}; + +rtk_regField_t PINGPONG_PLUS_STS_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 26, + /* len */ 6 + }, + { /* name */ PINGPONG_PLUS_STSf, + /* lsp */ 16, + /* len */ 10 + }, + { /* name */ RESERVEDf, + /* lsp */ 10, + /* len */ 6 + }, + { /* name */ PINGPONG_PLUS_ERRf, + /* lsp */ 0, + /* len */ 10 + }, +}; + +rtk_regField_t TOKEN_STS_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 26, + /* len */ 6 + }, + { /* name */ TOKEN_STSf, + /* lsp */ 16, + /* len */ 10 + }, + { /* name */ RESERVEDf, + /* lsp */ 10, + /* len */ 6 + }, + { /* name */ TOKEN_ERRf, + /* lsp */ 0, + /* len */ 10 + }, +}; + +rtk_regField_t SW_Q_RST_CNT_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 16, + /* len */ 16 + }, + { /* name */ SW_Q_RST_ASIC_CNTf, + /* lsp */ 0, + /* len */ 16 + }, +}; + +rtk_regField_t AUTO_RECOVER_SRC_SEL_INGRESS_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 26, + /* len */ 6 + }, + { /* name */ TOKEN_ERR_MSKf, + /* lsp */ 16, + /* len */ 10 + }, + { /* name */ RESERVEDf, + /* lsp */ 11, + /* len */ 5 + }, + { /* name */ RXSYS_DSC_ERR_MSKf, + /* lsp */ 10, + /* len */ 1 + }, + { /* name */ RXPORT_DSC_ERR_MSKf, + /* lsp */ 0, + /* len */ 10 + }, +}; + +rtk_regField_t AUTO_RECOVER_SRC_SEL_EGRESS_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 26, + /* len */ 6 + }, + { /* name */ PINGPONG_PLUS_ERR_MSKf, + /* lsp */ 16, + /* len */ 10 + }, + { /* name */ RESERVEDf, + /* lsp */ 10, + /* len */ 6 + }, + { /* name */ LD_TX_DSC_ERR_MSKf, + /* lsp */ 0, + /* len */ 10 + }, +}; + +rtk_regField_t AUTO_RECOVER_SRC_SEL_MAC_0_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 26, + /* len */ 6 + }, + { /* name */ RXFIFO_RDEMPTY_ERR_MSKf, + /* lsp */ 16, + /* len */ 10 + }, + { /* name */ RESERVEDf, + /* lsp */ 10, + /* len */ 6 + }, + { /* name */ RXFIFO_OVERFLOW_ERR_MSKf, + /* lsp */ 0, + /* len */ 10 + }, +}; + +rtk_regField_t AUTO_RECOVER_SRC_SEL_MAC_1_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 26, + /* len */ 6 + }, + { /* name */ TXFIFO_RDEMPTY_ERR_MSKf, + /* lsp */ 16, + /* len */ 10 + }, + { /* name */ RESERVEDf, + /* lsp */ 10, + /* len */ 6 + }, + { /* name */ TXFIFO_OVERFLOW_ERR_MSKf, + /* lsp */ 0, + /* len */ 10 + }, +}; + +rtk_regField_t TRIG_AUTO_RECOVER_CTRL_INGRESS_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 3, + /* len */ 29 + }, + { /* name */ EN_TOKEN_ERR_TRIGf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ EN_RXPORT_DSC_ERR_TRIGf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ EN_SYS_DSC_ERR_TRIGf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t TRIG_AUTO_RECOVER_CTRL_EGRESS_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 2, + /* len */ 30 + }, + { /* name */ EN_PINGPONG_PLUS_ERR_TRIGf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ EN_LD_TX_DSC_ERR_TRIGf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t TRIG_AUTO_RECOVER_CTRL_MAC_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 1, + /* len */ 31 + }, + { /* name */ EN_FIFO_ERR_TRIGf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t AUTO_RECOVER_EVENT_FLAG_STS_INGRESS_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 3, + /* len */ 29 + }, + { /* name */ GLB_TOKEN_STSf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ GLB_RXPORT_DSC_STSf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ GLB_SYS_DSC_STSf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t AUTO_RECOVER_EVENT_FLAG_STS_EGRESS_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 2, + /* len */ 30 + }, + { /* name */ GLB_PINGPONG_STSf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ GLB_LD_TX_DSC_STSf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t AUTO_RECOVER_EVENT_FLAG_STS_MAC_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 1, + /* len */ 31 + }, + { /* name */ GLB_FIFO_STSf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t AUTO_RECOVER_EVENT_FLAG_ERR_INGRESS_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 3, + /* len */ 29 + }, + { /* name */ GLB_TOKEN_ERRf, + /* lsp */ 2, + /* len */ 1 + }, + { /* name */ GLB_RX_P_DSC_ERRf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ GLB_SYS_DSC_ERRf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t AUTO_RECOVER_EVENT_FLAG_ERR_EGRESS_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 2, + /* len */ 30 + }, + { /* name */ GLB_PINGPONG_ERRf, + /* lsp */ 1, + /* len */ 1 + }, + { /* name */ GLB_LD_TX_DSC_ERRf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t AUTO_RECOVER_EVENT_FLAG_ERR_MAC_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 1, + /* len */ 31 + }, + { /* name */ GLB_FIFO_ERRf, + /* lsp */ 0, + /* len */ 1 + }, +}; + +rtk_regField_t FIFO_FLOW_FLAG_MSK_FIELDS[] = +{ + { /* name */ RESERVEDf, + /* lsp */ 7, + /* len */ 25 + }, + { /* name */ RXFIFO_DGLT_ENf, + /* lsp */ 6, + /* len */ 1 + }, + { /* name */ EGR_P_DGLT_ENf, + /* lsp */ 5, + /* len */ 1 + }, + { /* name */ TXFIFO_DGLT_ENf, + /* lsp */ 4, + /* len */ 1 + }, + { /* name */ FIFO_FLAG_MSKf, + /* lsp */ 0, + /* len */ 4 + }, +}; + +/* Module: ECO */ +rtk_regField_t CHIP_MISC_DUMY_0_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t CHIP_MISC_DUMY_1_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t TM0_CTRL_DUMY_0_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t TM0_CTRL_DUMY_1_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t TM1_CTRL_DUMY_0_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t TM1_CTRL_DUMY_1_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t VOLT_PROB_DUMY_0_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t VOLT_PROB_DUMY_1_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t REG_IF_DUMY_0_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t REG_IF_DUMY_1_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t MIB_0_DUMY_0_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t MIB_0_DUMY_1_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t MIB_1_DUMY_0_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t MIB_1_DUMY_1_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t MIB_2_DUMY_0_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t MIB_2_DUMY_1_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t MIB_3_DUMY_0_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t MIB_3_DUMY_1_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t MIB_4_DUMY_0_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t MIB_4_DUMY_1_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t MIB_5_DUMY_0_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t MIB_5_DUMY_1_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t MIB_6_DUMY_0_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t MIB_6_DUMY_1_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t MIB_7_DUMY_0_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t MIB_7_DUMY_1_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t MIB_8_DUMY_0_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t MIB_8_DUMY_1_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t MIB_9_DUMY_0_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t MIB_9_DUMY_1_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t MIB_10_DUMY_0_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t MIB_10_DUMY_1_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t MIB_11_DUMY_0_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t MIB_11_DUMY_1_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t MIB_12_DUMY_0_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t MIB_12_DUMY_1_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t MIB_13_DUMY_0_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t MIB_13_DUMY_1_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t MIB_14_DUMY_0_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t MIB_14_DUMY_1_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t MIB_15_DUMY_0_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t MIB_15_DUMY_1_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t MIB_16_DUMY_0_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t MIB_16_DUMY_1_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t PHY_INTF_DUMY_0_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t PHY_INTF_DUMY_1_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t PHY_INTF_DUMY_2_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t PHY_INTF_DUMY_3_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t PHY_PKG_DUMY_0_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t PHY_PKG_DUMY_1_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t PHY_MISC_DUMY_0_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t PHY_MISC_DUMY_1_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t RANDOM_SEED_DUMY_0_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t RANDOM_SEED_DUMY_1_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t RANDOM_SEED_DUMY_2_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t RANDOM_SEED_DUMY_3_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t MIB_CTRL_DUMY_0_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t MIB_CTRL_DUMY_1_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t MAC_GLB_DUMY_0_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t MAC_GLB_DUMY_1_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t PER_PORT_MAC_DUMY_0_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t PER_PORT_MAC_DUMY_1_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t PER_PORT_TXQ_REG_10P_DUMY_0_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t PER_PORT_TXQ_REG_10P_DUMY_1_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t EGRESS_CTRL_DUMY_0_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t EGRESS_CTRL_DUMY_1_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t EGRESS_CTRL_DUMY_2_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t EGRESS_CTRL_DUMY_3_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t ACL_DUMY_0_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t ACL_DUMY_1_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t ACL_DUMY_2_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t ACL_DUMY_3_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t INBW_DUMY_0_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t INBW_DUMY_1_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t CVLAN_DUMY_0_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t CVLAN_DUMY_1_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t CVLAN_DUMY_2_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t CVLAN_DUMY_3_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t DPM_DUMY_0_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t DPM_DUMY_1_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t IGMP_DUMY_0_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t IGMP_DUMY_1_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t L2_DUMY_0_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t L2_DUMY_1_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t SVLAN_DUMY_0_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t SVLAN_DUMY_1_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t SVLAN_DUMY_2_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t SVLAN_DUMY_3_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t TABLE_DUMY_0_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t TABLE_DUMY_1_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t MTRPOOL_DUMY_0_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t MTRPOOL_DUMY_1_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t GLB_CTRL_DUMY_0_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t GLB_CTRL_DUMY_1_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t GLB_CTRL_DUMY_2_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t GLB_CTRL_DUMY_3_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t SMI_CTRL_DUMY_0_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t SMI_CTRL_DUMY_1_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t LED_DUMY_0_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t LED_DUMY_1_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t PKT_ENCAP_DUMY_0_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t PKT_ENCAP_DUMY_1_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t PKT_ENCAP_DUMY_2_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t PKT_ENCAP_DUMY_3_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t PKT_PARSER_DUMY_0_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t PKT_PARSER_DUMY_1_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t INGRESS_CTRL_DUMY_0_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t INGRESS_CTRL_DUMY_1_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t INGRESS_CTRL_DUMY_2_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t INGRESS_CTRL_DUMY_3_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t INGRESS_CTRL_2_DUMY_0_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t INGRESS_CTRL_2_DUMY_1_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t INGRESS_CTRL_2_DUMY_2_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t INGRESS_CTRL_2_DUMY_3_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t NIC_DUMY_0_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t NIC_DUMY_1_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t CHIP_BIST_DUMY_0_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t CHIP_BIST_DUMY_1_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t SDS_DUMY_0_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t SDS_DUMY_1_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t IO_DUMY_0_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t IO_DUMY_1_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t EFUSE_CTRL_DUMY_0_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t EFUSE_CTRL_DUMY_1_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t DBG_CTRL_DUMY_0_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t DBG_CTRL_DUMY_1_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t RATE_ADAPTER0_DUMY_0_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t RATE_ADAPTER0_DUMY_1_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t RATE_ADAPTER1_DUMY_0_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t RATE_ADAPTER1_DUMY_1_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t RATE_ADAPTER2_DUMY_0_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t RATE_ADAPTER2_DUMY_1_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t RATE_ADAPTER3_DUMY_0_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + +rtk_regField_t RATE_ADAPTER3_DUMY_1_FIELDS[] = +{ + { /* name */ DUMMY_REGISTERf, + /* lsp */ 0, + /* len */ 32 + }, +}; + diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/rtl8373_regField_list.h b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/rtl8373_regField_list.h new file mode 100755 index 00000000..66ef5130 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/rtl8373_regField_list.h @@ -0,0 +1,1933 @@ +/* + * ## Please DO NOT edit this file!! ## + * This file is auto-generated from the register source files. + * Any modifications to this file will be LOST when it is re-generated. + * + * ---------------------------------------------------------------- + * (C) Copyright 2009-2016 Realtek Semiconductor Corp. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * ---------------------------------------------------------------- + * Purpose: chip register definition and structure of RTL8373 + * + * ---------------------------------------------------------------- + */ + +#ifndef __RTL8373_REGFIELD_LIST_H__ +#define __RTL8373_REGFIELD_LIST_H__ + + +/* Module: Chip Information */ +extern rtk_regField_t MODEL_NAME_INFO_FIELDS[]; +extern rtk_regField_t CHIP_MODE_INFO_FIELDS[]; +extern rtk_regField_t CHIP_INFO_FIELDS[]; +extern rtk_regField_t CHIP_UUID_REG_FIELDS[]; +extern rtk_regField_t CHIP_LOT_NO_REG0_FIELDS[]; +extern rtk_regField_t CHIP_LOT_NO_REG1_FIELDS[]; +extern rtk_regField_t SMI_MMD_SP_FIELDS[]; +extern rtk_regField_t CFG_DMY_CHIP_INFO_1_FIELDS[]; + +/* Module: Reset */ +extern rtk_regField_t RST_GLB_CTRL_0_FIELDS[]; +extern rtk_regField_t RST_GLB_DBG_0_FIELDS[]; +extern rtk_regField_t RST_GLB_DBG_1_FIELDS[]; + +/* Module: BIST & BISR */ +extern rtk_regField_t MAC_BIST_MODE_FIELDS[]; +extern rtk_regField_t MAC_DRF_BIST_MODE_FIELDS[]; +extern rtk_regField_t MAC_BIST_RSTN_FIELDS[]; +extern rtk_regField_t MAC_BIST_LOOP_MODE_FIELDS[]; +extern rtk_regField_t MAC_BIST_DYN_READ_EN_FIELDS[]; +extern rtk_regField_t MAC_DRF_TEST_RESUME_FIELDS[]; +extern rtk_regField_t MAC_DRF_START_PAUSE_FIELDS[]; +extern rtk_regField_t MAC_MBIST_DONE_FIELDS[]; +extern rtk_regField_t MAC_MBIST_DRF_DONE_FIELDS[]; +extern rtk_regField_t MAC_MBIST_FAIL_PG00_PG01_FIELDS[]; +extern rtk_regField_t MAC_MBIST_FAIL_PG02_PG03_FIELDS[]; +extern rtk_regField_t MAC_MBIST_DRF_FAIL_PG00_PG01_FIELDS[]; +extern rtk_regField_t MAC_MBIST_DRF_FAIL_PG02_PG03_FIELDS[]; +extern rtk_regField_t MAC_RXFIFO_LS_FIELDS[]; +extern rtk_regField_t MAC_RXFIFO_RMEA_FIELDS[]; +extern rtk_regField_t MAC_RXFIFO_RMA_PG00_FIELDS[]; +extern rtk_regField_t MAC_RXFIFO_RMA_PG01_FIELDS[]; +extern rtk_regField_t MAC_RXFIFO_RMA_PG02_FIELDS[]; +extern rtk_regField_t MAC_RXFIFO_RMA_PG03_FIELDS[]; +extern rtk_regField_t MAC_RXFIFO_RMEB_FIELDS[]; +extern rtk_regField_t MAC_RXFIFO_RMB_PG00_FIELDS[]; +extern rtk_regField_t MAC_RXFIFO_RMB_PG01_FIELDS[]; +extern rtk_regField_t MAC_RXFIFO_RMB_PG02_FIELDS[]; +extern rtk_regField_t MAC_RXFIFO_RMB_PG03_FIELDS[]; +extern rtk_regField_t MAC_TXFIFO_LS_FIELDS[]; +extern rtk_regField_t MAC_TXFIFO_RMEA_FIELDS[]; +extern rtk_regField_t MAC_TXFIFO_RMA_PG00_FIELDS[]; +extern rtk_regField_t MAC_TXFIFO_RMA_PG01_FIELDS[]; +extern rtk_regField_t MAC_TXFIFO_RMA_PG02_FIELDS[]; +extern rtk_regField_t MAC_TXFIFO_RMA_PG03_FIELDS[]; +extern rtk_regField_t MAC_TXFIFO_RMEB_FIELDS[]; +extern rtk_regField_t MAC_TXFIFO_RMB_PG00_FIELDS[]; +extern rtk_regField_t MAC_TXFIFO_RMB_PG01_FIELDS[]; +extern rtk_regField_t MAC_TXFIFO_RMB_PG02_FIELDS[]; +extern rtk_regField_t MAC_TXFIFO_RMB_PG03_FIELDS[]; +extern rtk_regField_t CHIP_ALL_RESULT_FIELDS[]; +extern rtk_regField_t CHIP_BISR_CTRL_FIELDS[]; +extern rtk_regField_t GLB_MBISD_DATA_FIELDS[]; +extern rtk_regField_t GLB_MBISD_CFG_FIELDS[]; +extern rtk_regField_t INGR_BIST_CTRL0_FIELDS[]; +extern rtk_regField_t INGR_BIST_CTRL1_FIELDS[]; +extern rtk_regField_t INGR_BIST_CTRL2_FIELDS[]; +extern rtk_regField_t INGR_BIST_CTRL3_FIELDS[]; +extern rtk_regField_t INGR_BIST_CTRL4_FIELDS[]; +extern rtk_regField_t INGR_BIST_CTRL5_FIELDS[]; +extern rtk_regField_t INGR_BIST_CTRL6_FIELDS[]; +extern rtk_regField_t INGR_BIST_RSLT0_FIELDS[]; +extern rtk_regField_t INGR_BIST_RSLT1_FIELDS[]; +extern rtk_regField_t INGR_BIST_RSLT2_FIELDS[]; +extern rtk_regField_t INGR_BIST_RSLT3_FIELDS[]; +extern rtk_regField_t INGR_BIST_RSLT4_FIELDS[]; +extern rtk_regField_t INGR_SRAM_CTRL_0_FIELDS[]; +extern rtk_regField_t INGR_SRAM_CTRL_1_FIELDS[]; +extern rtk_regField_t INGR_BISR_CTRL_FIELDS[]; +extern rtk_regField_t INGR_BISR_RSLT0_FIELDS[]; +extern rtk_regField_t INGR_BISR_RSLT1_FIELDS[]; +extern rtk_regField_t INGR_BISR_RSLT2_FIELDS[]; +extern rtk_regField_t INGR_BISR_RSLT3_FIELDS[]; +extern rtk_regField_t EGR_BIST_CTRL0_FIELDS[]; +extern rtk_regField_t EGR_BIST_CTRL1_FIELDS[]; +extern rtk_regField_t EGR_BIST_CTRL2_FIELDS[]; +extern rtk_regField_t EGR_SRAM_CTRL3_FIELDS[]; +extern rtk_regField_t EGR_BIST_CTRL4_FIELDS[]; +extern rtk_regField_t EGR_BIST_CTRL5_FIELDS[]; +extern rtk_regField_t EGR_BIST_RSLT0_FIELDS[]; +extern rtk_regField_t EGR_BIST_RSLT1_FIELDS[]; +extern rtk_regField_t EGR_BIST_RSLT2_FIELDS[]; +extern rtk_regField_t NIC_BIST_CTRL0_FIELDS[]; +extern rtk_regField_t NIC_BIST_CTRL1_FIELDS[]; +extern rtk_regField_t NIC_BIST_CTRL2_FIELDS[]; +extern rtk_regField_t NIC_BIST_CTRL3_FIELDS[]; +extern rtk_regField_t NIC_BIST_CTRL4_FIELDS[]; +extern rtk_regField_t NIC_BIST_CTRL5_FIELDS[]; +extern rtk_regField_t NIC_BIST_RSLT0_FIELDS[]; +extern rtk_regField_t NIC_BIST_RSLT1_FIELDS[]; +extern rtk_regField_t NIC_BIST_RSLT2_FIELDS[]; +extern rtk_regField_t SPI_BIST_CTRL_FIELDS[]; +extern rtk_regField_t SPI_BIST_RSLT_FIELDS[]; +extern rtk_regField_t ALE_MEM_CFG_0_FIELDS[]; +extern rtk_regField_t ALE_MEM_CFG_1_FIELDS[]; +extern rtk_regField_t ALE_CAM_CFG_FIELDS[]; +extern rtk_regField_t ALE_BIST_LOOP_EN_FIELDS[]; +extern rtk_regField_t ALE_BIST_DYN_READ_EN_FIELDS[]; +extern rtk_regField_t ALE_BIST_GRP_EN_FIELDS[]; +extern rtk_regField_t ALE_BIST_RSTN_FIELDS[]; +extern rtk_regField_t ALE_BIST_MODE_FIELDS[]; +extern rtk_regField_t ALE_BIST_DONE_FIELDS[]; +extern rtk_regField_t ALE_BIST_FAIL_FIELDS[]; +extern rtk_regField_t ALE_DRF_MODE_FIELDS[]; +extern rtk_regField_t ALE_DRF_PAUSE_FIELDS[]; +extern rtk_regField_t ALE_DRF_RESUME_FIELDS[]; +extern rtk_regField_t ALE_DRF_DONE_FIELDS[]; +extern rtk_regField_t ALE_DRF_FAIL_FIELDS[]; +extern rtk_regField_t PAR_MEM_CFG_0_FIELDS[]; +extern rtk_regField_t PAR_MEM_CFG_1_FIELDS[]; +extern rtk_regField_t PAR_MEM_CFG_2_FIELDS[]; +extern rtk_regField_t PAR_MEM_CFG_3_FIELDS[]; +extern rtk_regField_t PAR_BIST_RESET_RESUME_FIELDS[]; +extern rtk_regField_t PAR_BIST_MODE_DRFMODE_FIELDS[]; +extern rtk_regField_t PAR_BIST_VDDR_LOOP_FIELDS[]; +extern rtk_regField_t PAR_BIST_START_PAUSE_FIELDS[]; +extern rtk_regField_t PAR_BIST_DONE_DRFDONE_FIELDS[]; +extern rtk_regField_t PAR_BIST_FAIL_DRFFAIL_FIELDS[]; +extern rtk_regField_t PAR_BIST_CTRL_0_FIELDS[]; +extern rtk_regField_t MBIST_CTRL_FIELDS[]; +extern rtk_regField_t MBIST_RSLT_FIELDS[]; + +/* Module: HW_MISC */ +extern rtk_regField_t BOND_INFO_FIELDS[]; +extern rtk_regField_t STRAP_INFO_0_FIELDS[]; +extern rtk_regField_t IO_DRVING_0_FIELDS[]; +extern rtk_regField_t IO_DRVING_1_FIELDS[]; +extern rtk_regField_t IO_DRVING_2_FIELDS[]; +extern rtk_regField_t IO_SLEW_0_FIELDS[]; +extern rtk_regField_t IO_SLEW_1_FIELDS[]; +extern rtk_regField_t IO_SLEW_2_FIELDS[]; +extern rtk_regField_t IO_SMT_EN_0_FIELDS[]; +extern rtk_regField_t IO_SMT_EN_1_FIELDS[]; +extern rtk_regField_t IO_SMT_EN_2_FIELDS[]; +extern rtk_regField_t IO_MUX_SEL_0_FIELDS[]; +extern rtk_regField_t IO_MUX_SEL_1_FIELDS[]; +extern rtk_regField_t IO_MUX_SEL_2_FIELDS[]; +extern rtk_regField_t IO_MUX_SEL_3_FIELDS[]; +extern rtk_regField_t DBG_MODE_FIELDS[]; +extern rtk_regField_t DBG_PAD_CTRL_FIELDS[]; +extern rtk_regField_t DBG_CTRL_ADR0_FIELDS[]; +extern rtk_regField_t DBG_CTRL_ADR1_FIELDS[]; +extern rtk_regField_t DBG_CTRL_ADR2_FIELDS[]; +extern rtk_regField_t DBG_CTRL_ADR3_FIELDS[]; +extern rtk_regField_t DBG_CTRL_SEL0_FIELDS[]; +extern rtk_regField_t DBG_CTRL_SEL1_FIELDS[]; +extern rtk_regField_t DBG_CTRL_SEL2_FIELDS[]; +extern rtk_regField_t DBG_CTRL_SEL3_FIELDS[]; +extern rtk_regField_t DBG_CTRL_VAL_FIELDS[]; +extern rtk_regField_t FORCE_PU_PD_EN_0_FIELDS[]; +extern rtk_regField_t FORCE_PU_PD_EN_1_FIELDS[]; +extern rtk_regField_t FORCE_PU_0_FIELDS[]; +extern rtk_regField_t FORCE_PU_1_FIELDS[]; +extern rtk_regField_t FORCE_PD_0_FIELDS[]; +extern rtk_regField_t FORCE_PD_1_FIELDS[]; +extern rtk_regField_t CFG_PAD_MDIO0_DRV_MODE_FIELDS[]; +extern rtk_regField_t VOLT_PROB_CTRL_FIELDS[]; +extern rtk_regField_t VOLT_PROB_RESULT0_FIELDS[]; +extern rtk_regField_t VOLT_PROB_RESULT1_FIELDS[]; +extern rtk_regField_t CFG_XTAL_FIELDS[]; + +/* Module: Wrapper_PHY */ +extern rtk_regField_t CFG_EEE_FLG_DLY_FIELDS[]; +extern rtk_regField_t CFG_PHY_MDI_REVERSE_FIELDS[]; +extern rtk_regField_t CFG_PHY_TX_POLARITY_SWAP_FIELDS[]; +extern rtk_regField_t CFG_PHY_OCP_TIMEOUT_FIELDS[]; +extern rtk_regField_t CFG_PHY_PCSXF_1_FIELDS[]; +extern rtk_regField_t CFG_PHY_PCSXF_2_FIELDS[]; +extern rtk_regField_t CFG_PHY_G2XG_IPG_FIELDS[]; +extern rtk_regField_t CFG_PHY_G2XG_FIFO_THR_FIELDS[]; +extern rtk_regField_t CFG_PHY_G2XG_AUTORST_FIELDS[]; +extern rtk_regField_t CFG_PHY_G2XG_MISC_FIELDS[]; +extern rtk_regField_t CFG_PHY_G2XG_MODULE_RST_FIELDS[]; +extern rtk_regField_t P0_PHY_G2XG_BCH_ERR_FLAG_FIELDS[]; +extern rtk_regField_t P1_PHY_G2XG_BCH_ERR_FLAG_FIELDS[]; +extern rtk_regField_t P2_PHY_G2XG_BCH_ERR_FLAG_FIELDS[]; +extern rtk_regField_t P3_PHY_G2XG_BCH_ERR_FLAG_FIELDS[]; +extern rtk_regField_t CFG_PHY_MISC_FIELDS[]; +extern rtk_regField_t PHY_LINK_FAULT_STS_FIELDS[]; +extern rtk_regField_t CFG_PHY_BRD_FIELDS[]; +extern rtk_regField_t CFG_PHY_INI_FIELDS[]; +extern rtk_regField_t CFG_PHY_POLL_CMD1_FIELDS[]; +extern rtk_regField_t CFG_PHY_POLL_CMD2_FIELDS[]; +extern rtk_regField_t CFG_PHY_HOTCMD1_ADR_FIELDS[]; +extern rtk_regField_t CFG_PHY_HOTCMD1_DAT_FIELDS[]; +extern rtk_regField_t P0_XG2XG_IPG_DBG_INFO_FIELDS[]; +extern rtk_regField_t P0_XG2XG_PRMB_DBG_INFO_FIELDS[]; +extern rtk_regField_t P0_XG2XG_THR_DBG_INFO_FIELDS[]; +extern rtk_regField_t CFG_PHY_POLL_ADR0_FIELDS[]; +extern rtk_regField_t CFG_PHY_POLL_ADR1_FIELDS[]; +extern rtk_regField_t CFG_PHY_POLL_ADR2_FIELDS[]; +extern rtk_regField_t CFG_PHY_POLL_ADR3_FIELDS[]; +extern rtk_regField_t CFG_PHY_POLL_INV0_FIELDS[]; +extern rtk_regField_t CFG_PHY_POLL_INV1_FIELDS[]; +extern rtk_regField_t CFG_PHY_POLL_INV2_FIELDS[]; +extern rtk_regField_t CFG_PHY_POLL_INV3_FIELDS[]; +extern rtk_regField_t CFG_PHY_POLL_WD0_FIELDS[]; +extern rtk_regField_t CFG_PHY_POLL_WD1_FIELDS[]; +extern rtk_regField_t CFG_PHY_POLL_WD2_FIELDS[]; +extern rtk_regField_t CFG_PHY_POLL_WD3_FIELDS[]; +extern rtk_regField_t PHY_SDET_STATUS_FIELDS[]; +extern rtk_regField_t P0_PHY_POLL_CMD0_RDAT_FIELDS[]; +extern rtk_regField_t P0_PHY_POLL_CMD1_RDAT_FIELDS[]; +extern rtk_regField_t P0_PHY_POLL_CMD2_RDAT_FIELDS[]; +extern rtk_regField_t P0_PHY_POLL_CMD3_RDAT_FIELDS[]; +extern rtk_regField_t P1_PHY_POLL_CMD0_RDAT_FIELDS[]; +extern rtk_regField_t P1_PHY_POLL_CMD1_RDAT_FIELDS[]; +extern rtk_regField_t P1_PHY_POLL_CMD2_RDAT_FIELDS[]; +extern rtk_regField_t P1_PHY_POLL_CMD3_RDAT_FIELDS[]; +extern rtk_regField_t P2_PHY_POLL_CMD0_RDAT_FIELDS[]; +extern rtk_regField_t P2_PHY_POLL_CMD1_RDAT_FIELDS[]; +extern rtk_regField_t P2_PHY_POLL_CMD2_RDAT_FIELDS[]; +extern rtk_regField_t P2_PHY_POLL_CMD3_RDAT_FIELDS[]; +extern rtk_regField_t P3_PHY_POLL_CMD0_RDAT_FIELDS[]; +extern rtk_regField_t P3_PHY_POLL_CMD1_RDAT_FIELDS[]; +extern rtk_regField_t P3_PHY_POLL_CMD2_RDAT_FIELDS[]; +extern rtk_regField_t P3_PHY_POLL_CMD3_RDAT_FIELDS[]; +extern rtk_regField_t PHY_ABLTY_RESOLUTION_FRC_MODE_FIELDS[]; +extern rtk_regField_t P0_PHY_ABLTY_RESOLUTION_FORCE_FIELDS[]; +extern rtk_regField_t P1_PHY_ABLTY_RESOLUTION_FORCE_FIELDS[]; +extern rtk_regField_t P2_PHY_ABLTY_RESOLUTION_FORCE_FIELDS[]; +extern rtk_regField_t P3_PHY_ABLTY_RESOLUTION_FORCE_FIELDS[]; +extern rtk_regField_t POWCTRL_ADR_FIELDS[]; +extern rtk_regField_t POWCTRL1_BIT_FIELDS[]; +extern rtk_regField_t POWCTRL0_BIT_FIELDS[]; +extern rtk_regField_t RS_LAYER_CONFIG_FIELDS[]; +extern rtk_regField_t PHY0_RD_PCS_ABILITY_FIELDS[]; +extern rtk_regField_t PHY1_RD_PCS_ABILITY_FIELDS[]; +extern rtk_regField_t PHY2_RD_PCS_ABILITY_FIELDS[]; +extern rtk_regField_t PHY3_RD_PCS_ABILITY_FIELDS[]; +extern rtk_regField_t CFG_PHY_XG2G_G_MISC_FIELDS[]; +extern rtk_regField_t P1_XG2XG_IPG_DBG_INFO_FIELDS[]; +extern rtk_regField_t P1_XG2XG_PRMB_DBG_INFO_FIELDS[]; +extern rtk_regField_t P1_XG2XG_THR_DBG_INFO_FIELDS[]; +extern rtk_regField_t RANDOM_UPD_PERIOD_FIELDS[]; +extern rtk_regField_t RANDOM_UPD_CTRL_FIELDS[]; +extern rtk_regField_t RG_RDM_SEED_SRC_ADDR_FIELDS[]; +extern rtk_regField_t RING_RATE_REGADDR_FIELDS[]; +extern rtk_regField_t RING_RATE_SEL_MASK_L_FIELDS[]; +extern rtk_regField_t RING_RATE_SEL_MASK_H_FIELDS[]; +extern rtk_regField_t RING_RATE_FRC_VALUE_H_FIELDS[]; +extern rtk_regField_t RING_RATE_FRC_VALUE_L_FIELDS[]; +extern rtk_regField_t LFSR_INIT_SEED_FRC_VALUE_FIELDS[]; +extern rtk_regField_t RING_RATE_RD_VALUE_H_FIELDS[]; +extern rtk_regField_t RING_RATE_RD_VALUE_L_FIELDS[]; +extern rtk_regField_t LFSR_INIT_SEED_RD_VALUE_FIELDS[]; +extern rtk_regField_t P0_G2XG_CFG_CLR_ERR_FLAG_FIELDS[]; +extern rtk_regField_t P1_G2XG_CFG_CLR_ERR_FLAG_FIELDS[]; +extern rtk_regField_t P2_G2XG_CFG_CLR_ERR_FLAG_FIELDS[]; +extern rtk_regField_t P3_G2XG_CFG_CLR_ERR_FLAG_FIELDS[]; +extern rtk_regField_t G2XG_FIFO_CLR_CFG_FIELDS[]; +extern rtk_regField_t P2_XG2XG_IPG_DBG_INFO_FIELDS[]; +extern rtk_regField_t P2_XG2XG_PRMB_DBG_INFO_FIELDS[]; +extern rtk_regField_t P2_XG2XG_THR_DBG_INFO_FIELDS[]; +extern rtk_regField_t G2G_WATER_LEVEL_FIELDS[]; +extern rtk_regField_t G2G_MISC_CFG_FIELDS[]; +extern rtk_regField_t G2G_ERR_CNT_01_FIELDS[]; +extern rtk_regField_t G2G_ERR_CNT_23_FIELDS[]; +extern rtk_regField_t XG2XG_WATER_LEVEL_FIELDS[]; +extern rtk_regField_t XG2XG_MISC_CFG_FIELDS[]; +extern rtk_regField_t XG2XG_ERR_STATUS_FIELDS[]; +extern rtk_regField_t EEE_LPI_DLY_CYCLE_FIELDS[]; +extern rtk_regField_t PREAMBLE_RECOVERY_CRTL_FIELDS[]; +extern rtk_regField_t G2G_FIFO_CLR_CFG_FIELDS[]; +extern rtk_regField_t XG2XG_FIFO_CLR_CFG_FIELDS[]; +extern rtk_regField_t P3_XG2XG_IPG_DBG_INFO_FIELDS[]; +extern rtk_regField_t P3_XG2XG_PRMB_DBG_INFO_FIELDS[]; +extern rtk_regField_t P3_XG2XG_THR_DBG_INFO_FIELDS[]; +extern rtk_regField_t SYNCE_CTRL_0_FIELDS[]; +extern rtk_regField_t SYNCE_CTRL_1_FIELDS[]; +extern rtk_regField_t SYNCE_DUMMY1_FIELDS[]; +extern rtk_regField_t SYNCE_DUMMY2_FIELDS[]; +extern rtk_regField_t SYNCE_DUMMY3_FIELDS[]; +extern rtk_regField_t SYNCE_DUMMY4_FIELDS[]; +extern rtk_regField_t SYNCE_DUMMY5_FIELDS[]; +extern rtk_regField_t PKTGEN_GLOBAL_CTRL_FIELDS[]; +extern rtk_regField_t PKTGEN_PAYLOAD_IND_ACCESS_CTRL_FIELDS[]; +extern rtk_regField_t PKTGEN_G2XG_FIFO_CTRL_FIELDS[]; +extern rtk_regField_t PKTGEN0_CTRL0_FIELDS[]; +extern rtk_regField_t PKTGEN0_CTRL1_FIELDS[]; +extern rtk_regField_t PKTGEN0_CTRL2_FIELDS[]; +extern rtk_regField_t PKTGEN0_CTRL3_FIELDS[]; +extern rtk_regField_t PKTGEN0_CTRL4_FIELDS[]; +extern rtk_regField_t PKTGEN0_CTRL5_FIELDS[]; +extern rtk_regField_t PKTGEN0_CTRL6_FIELDS[]; +extern rtk_regField_t PKTGEN0_CTRL7_FIELDS[]; +extern rtk_regField_t PKTGEN1_CTRL0_FIELDS[]; +extern rtk_regField_t PKTGEN1_CTRL1_FIELDS[]; +extern rtk_regField_t PKTGEN1_CTRL2_FIELDS[]; +extern rtk_regField_t PKTGEN1_CTRL3_FIELDS[]; +extern rtk_regField_t PKTGEN1_CTRL4_FIELDS[]; +extern rtk_regField_t PKTGEN1_CTRL5_FIELDS[]; +extern rtk_regField_t PKTGEN1_CTRL6_FIELDS[]; +extern rtk_regField_t PKTGEN1_CTRL7_FIELDS[]; +extern rtk_regField_t PKTGEN2_CTRL0_FIELDS[]; +extern rtk_regField_t PKTGEN2_CTRL1_FIELDS[]; +extern rtk_regField_t PKTGEN2_CTRL2_FIELDS[]; +extern rtk_regField_t PKTGEN2_CTRL3_FIELDS[]; +extern rtk_regField_t PKTGEN2_CTRL4_FIELDS[]; +extern rtk_regField_t PKTGEN2_CTRL5_FIELDS[]; +extern rtk_regField_t PKTGEN2_CTRL6_FIELDS[]; +extern rtk_regField_t PKTGEN2_CTRL7_FIELDS[]; +extern rtk_regField_t PKTGEN3_CTRL0_FIELDS[]; +extern rtk_regField_t PKTGEN3_CTRL1_FIELDS[]; +extern rtk_regField_t PKTGEN3_CTRL2_FIELDS[]; +extern rtk_regField_t PKTGEN3_CTRL3_FIELDS[]; +extern rtk_regField_t PKTGEN3_CTRL4_FIELDS[]; +extern rtk_regField_t PKTGEN3_CTRL5_FIELDS[]; +extern rtk_regField_t PKTGEN3_CTRL6_FIELDS[]; +extern rtk_regField_t PKTGEN3_CTRL7_FIELDS[]; +extern rtk_regField_t PKTGEN0_CTRL15_FIELDS[]; +extern rtk_regField_t PKTGEN1_CTRL15_FIELDS[]; +extern rtk_regField_t PKTGEN2_CTRL15_FIELDS[]; +extern rtk_regField_t PKTGEN3_CTRL15_FIELDS[]; +extern rtk_regField_t PHY_MODEL_ID_REV_CTRL_FIELDS[]; + +/* Module: SDS */ +extern rtk_regField_t SDS_MODE_SEL_FIELDS[]; +extern rtk_regField_t SDS_INDACS_CMD_FIELDS[]; +extern rtk_regField_t SDS_INDACS_RD_FIELDS[]; +extern rtk_regField_t SDS_INDACS_WD_FIELDS[]; +extern rtk_regField_t SDS0_STATUS_FIELDS[]; +extern rtk_regField_t SDS0_CH0_RO_ABLTY_FIELDS[]; +extern rtk_regField_t SDS0_CH1_RO_ABLTY_FIELDS[]; +extern rtk_regField_t SDS0_CH2_RO_ABLTY_FIELDS[]; +extern rtk_regField_t SDS0_CH3_3_RO_ABLTY_FIELDS[]; +extern rtk_regField_t SDS1_CH0_RO_ABLTY_FIELDS[]; +extern rtk_regField_t SDS0_1_MODE_RO_FIELDS[]; +extern rtk_regField_t CFG_DMY_SDS_0_FIELDS[]; +extern rtk_regField_t CFG_DMY_SDS_1_FIELDS[]; +extern rtk_regField_t SDS_OUI_FIELDS[]; +extern rtk_regField_t SDS_VERSION_FIELDS[]; +extern rtk_regField_t SDS_OUI_TGR_FIELDS[]; +extern rtk_regField_t SDS_VERSION_TGR_FIELDS[]; +extern rtk_regField_t SDS_INTF_CTRL1_FIELDS[]; +extern rtk_regField_t SDS_INTF_CTRL2_FIELDS[]; +extern rtk_regField_t SDS_INTF_OUT1_FIELDS[]; + +/* Module: LED */ +extern rtk_regField_t LED_GLB_CTRL_FIELDS[]; +extern rtk_regField_t LED3_0_SET3_2_CTRL1_FIELDS[]; +extern rtk_regField_t LED3_0_SET1_0_CTRL1_FIELDS[]; +extern rtk_regField_t LED3_2_SET3_CTRL0_FIELDS[]; +extern rtk_regField_t LED1_0_SET3_CTRL0_FIELDS[]; +extern rtk_regField_t LED3_2_SET2_CTRL0_FIELDS[]; +extern rtk_regField_t LED1_0_SET2_CTRL0_FIELDS[]; +extern rtk_regField_t LED3_2_SET1_CTRL0_FIELDS[]; +extern rtk_regField_t LED1_0_SET1_CTRL0_FIELDS[]; +extern rtk_regField_t LED3_2_SET0_CTRL0_FIELDS[]; +extern rtk_regField_t LED1_0_SET0_CTRL0_FIELDS[]; +extern rtk_regField_t LED_PORT_SET_SEL_CTRL_FIELDS[]; +extern rtk_regField_t SW_LED_LOAD_FIELDS[]; +extern rtk_regField_t LED_PORT_SW_EN_CTRL_FIELDS[]; +extern rtk_regField_t LED_PORT_SW_CTRL_FIELDS[]; +extern rtk_regField_t LED_LOAD_LV1_10G_FIELDS[]; +extern rtk_regField_t LED_LOAD_LV2_10G_FIELDS[]; +extern rtk_regField_t LED_LOAD_LV3_10G_FIELDS[]; +extern rtk_regField_t LED_LOAD_LV1_5G_FIELDS[]; +extern rtk_regField_t LED_LOAD_LV2_5G_FIELDS[]; +extern rtk_regField_t LED_LOAD_LV3_5G_FIELDS[]; +extern rtk_regField_t LED_LOAD_LV1_2P5G_FIELDS[]; +extern rtk_regField_t LED_LOAD_LV2_2P5G_FIELDS[]; +extern rtk_regField_t LED_LOAD_LV3_2P5G_FIELDS[]; +extern rtk_regField_t LED_LOAD_LV1_1G_FIELDS[]; +extern rtk_regField_t LED_LOAD_LV2_1G_FIELDS[]; +extern rtk_regField_t LED_LOAD_LV3_1G_FIELDS[]; +extern rtk_regField_t LED_LOAD_LV1_500M_FIELDS[]; +extern rtk_regField_t LED_LOAD_LV2_500M_FIELDS[]; +extern rtk_regField_t LED_LOAD_LV3_500M_FIELDS[]; +extern rtk_regField_t LED_LOAD_LV1_100M_FIELDS[]; +extern rtk_regField_t LED_LOAD_LV2_100M_FIELDS[]; +extern rtk_regField_t LED_LOAD_LV3_100M_FIELDS[]; +extern rtk_regField_t LED_LOAD_LV1_10M_FIELDS[]; +extern rtk_regField_t LED_LOAD_LV2_10M_FIELDS[]; +extern rtk_regField_t LED_LOAD_LV3_10M_FIELDS[]; +extern rtk_regField_t LED_P_LOAD_CTRL_FIELDS[]; +extern rtk_regField_t LED_GLB_ACTIVE_FIELDS[]; +extern rtk_regField_t LED_GLB_IO_EN_FIELDS[]; +extern rtk_regField_t LED_GLB_MUX_1_FIELDS[]; +extern rtk_regField_t LED_GLB_MUX_2_FIELDS[]; +extern rtk_regField_t LED_GLB_MUX_3_FIELDS[]; +extern rtk_regField_t LED_GLB_MUX_4_FIELDS[]; +extern rtk_regField_t LED_GLB_MUX_5_FIELDS[]; +extern rtk_regField_t LED_GLB_MUX_6_FIELDS[]; +extern rtk_regField_t LED_RLDP_CTRL_1_FIELDS[]; +extern rtk_regField_t LED_RLDP_CTRL_2_FIELDS[]; +extern rtk_regField_t LED_RLDP_CTRL_3_FIELDS[]; + +/* Module: Smart Packet Generator */ +extern rtk_regField_t SPG_GLB_CTRL_FIELDS[]; +extern rtk_regField_t PKB_ACC_DEBUG_CTRL_FIELDS[]; +extern rtk_regField_t SPG_PORT_TX_GRP_CTRL_FIELDS[]; +extern rtk_regField_t SPG_GLOBAL_STS_FIELDS[]; +extern rtk_regField_t SPG_PORT_IBG_CTRL0_FIELDS[]; +extern rtk_regField_t SPG_PORT_IBG_CTRL1_FIELDS[]; +extern rtk_regField_t SPG_PORT_IPG_CTRL_FIELDS[]; +extern rtk_regField_t SPG_PORT_PKT_CNT_H_FIELDS[]; +extern rtk_regField_t SPG_PORT_PKT_CNT_L_FIELDS[]; +extern rtk_regField_t SPG_PORT_PKT_CNT_DBG_H_FIELDS[]; +extern rtk_regField_t SPG_PORT_PKT_CNT_DBG_L_FIELDS[]; +extern rtk_regField_t SPG_PORT_STREAM0_CTRL0_FIELDS[]; +extern rtk_regField_t SPG_PORT_STREAM0_CTRL1_FIELDS[]; +extern rtk_regField_t SPG_PORT_STREAM0_CTRL2_FIELDS[]; +extern rtk_regField_t SPG_PORT_STREAM0_CTRL3_FIELDS[]; +extern rtk_regField_t SPG_PB_ACCESS_CTRL0_FIELDS[]; +extern rtk_regField_t SPG_PB_ACCESS_CTRL1_FIELDS[]; +extern rtk_regField_t SPG_PB_ACCESS_CTRL2_FIELDS[]; +extern rtk_regField_t SPG_PORT_INDEX_CTRL0_FIELDS[]; +extern rtk_regField_t SPG_GLOBAL_INDEX_CTRL0_FIELDS[]; +extern rtk_regField_t SPG_PREAMBLE_LENGTH_CTRL_FIELDS[]; +extern rtk_regField_t SPG_PREAMBLE_CONTENT_CTRL2_FIELDS[]; +extern rtk_regField_t SPG_PREAMBLE_CONTENT_CTRL1_FIELDS[]; +extern rtk_regField_t SPG_PREAMBLE_CONTENT_CTRL0_FIELDS[]; + +/* Module: Interface */ +extern rtk_regField_t I2C_SLV_CTRL_FIELDS[]; +extern rtk_regField_t MAC_SLV_TIMEOUT_FIELDS[]; +extern rtk_regField_t MAC_IF_CTRL_FIELDS[]; +extern rtk_regField_t SLV_MDX_CTRL_FIELDS[]; +extern rtk_regField_t I2C_MST_IF_CTRL_FIELDS[]; +extern rtk_regField_t I2C_MST1_CTRL1_FIELDS[]; +extern rtk_regField_t I2C_MST1_CTRL2_FIELDS[]; +extern rtk_regField_t I2C_MST1_MEMADDR_CTRL_FIELDS[]; +extern rtk_regField_t I2C_MST1_DATA_CTRL_FIELDS[]; +extern rtk_regField_t SPI_CTRL0_FIELDS[]; +extern rtk_regField_t SPI_CTRL1_FIELDS[]; +extern rtk_regField_t SPI_DATA_FIELDS[]; +extern rtk_regField_t SPI_ADDR_FIELDS[]; +extern rtk_regField_t GPIO_OUT0_FIELDS[]; +extern rtk_regField_t GPIO_OUT1_FIELDS[]; +extern rtk_regField_t GPIO_IN0_FIELDS[]; +extern rtk_regField_t GPIO_IN1_FIELDS[]; +extern rtk_regField_t GPIO_OE0_FIELDS[]; +extern rtk_regField_t GPIO_OE1_FIELDS[]; +extern rtk_regField_t GPIO_IMODE_54_52_FIELDS[]; +extern rtk_regField_t INI_MODE_FIELDS[]; +extern rtk_regField_t PWM_CTRL_FIELDS[]; +extern rtk_regField_t REGIF_TIMEOUT_INFO_FIELDS[]; + +/* Module: TM */ +extern rtk_regField_t TM0_CTRL0_FIELDS[]; +extern rtk_regField_t TM0_CTRL1_FIELDS[]; +extern rtk_regField_t TM0_CTRL2_FIELDS[]; +extern rtk_regField_t TM0_CTRL3_FIELDS[]; +extern rtk_regField_t TM0_RESULT0_FIELDS[]; +extern rtk_regField_t TM0_RESULT1_FIELDS[]; +extern rtk_regField_t TM0_RESULT2_FIELDS[]; +extern rtk_regField_t TM0_RESULT3_FIELDS[]; +extern rtk_regField_t TM0_RESULT4_FIELDS[]; +extern rtk_regField_t TM1_CTRL0_FIELDS[]; +extern rtk_regField_t TM1_CTRL1_FIELDS[]; +extern rtk_regField_t TM1_CTRL2_FIELDS[]; +extern rtk_regField_t TM1_CTRL3_FIELDS[]; +extern rtk_regField_t TM1_RESULT0_FIELDS[]; +extern rtk_regField_t TM1_RESULT1_FIELDS[]; +extern rtk_regField_t TM1_RESULT2_FIELDS[]; +extern rtk_regField_t TM1_RESULT3_FIELDS[]; +extern rtk_regField_t TM1_RESULT4_FIELDS[]; + +/* Module: EFUSE&EEPROM */ +extern rtk_regField_t EFUSE_ACCESS_EN_FIELDS[]; +extern rtk_regField_t EFUSE_AUTOLOAD_CTRL_FIELDS[]; +extern rtk_regField_t EFUSE_ACCESS_CTRL_FIELDS[]; +extern rtk_regField_t EFUSE_WDATA_CTRL_FIELDS[]; +extern rtk_regField_t EFUSE_RDATA_CTRL_FIELDS[]; +extern rtk_regField_t EFUSE_CP_MISC_FIELDS[]; +extern rtk_regField_t EFUSE_MARGIN_RD_CFG_FIELDS[]; +extern rtk_regField_t EFUSE_MARGIN_RD_ERR_1_FIELDS[]; +extern rtk_regField_t EFUSE_MARGIN_RD_ERR_2_FIELDS[]; +extern rtk_regField_t EFUSE_FREQ_SEL_FIELDS[]; +extern rtk_regField_t EFUSE_MASS_OPERATION_CFG_FIELDS[]; +extern rtk_regField_t EFUSE_MASS_COMP_ERR_1_FIELDS[]; +extern rtk_regField_t EFUSE_MASS_COMP_ERR_2_FIELDS[]; +extern rtk_regField_t EFUSE_MASS_DATA_REG_FIELDS[]; +extern rtk_regField_t MAC_EEPROM_DOWN_LOAD_FREQ_FIELDS[]; +extern rtk_regField_t MAC_EEPROM_DOWN_LOAD_STS_FIELDS[]; +extern rtk_regField_t EEPROM_VER_INFO_FIELDS[]; +extern rtk_regField_t EEPROM_AUTOLOAD_TIMER_FIELDS[]; +extern rtk_regField_t MAC_EEPROM_ADDR_LEN_FIELDS[]; + +/* Module: Interrupt */ +extern rtk_regField_t IMR_INT_PORT_LINK_STS_CHG_FIELDS[]; +extern rtk_regField_t IMR_INT_GPHY_FIELDS[]; +extern rtk_regField_t IMR_INT_LEARNOVER_FIELDS[]; +extern rtk_regField_t IMR_INT_RLFD_FIELDS[]; +extern rtk_regField_t IMR_INT_WOL_FIELDS[]; +extern rtk_regField_t IMR_INT_SERDES_LINK_FAULT_P_FIELDS[]; +extern rtk_regField_t IMR_INT_SDS_UPD_PHYSTS0_FIELDS[]; +extern rtk_regField_t IMR_INT_GPIO_FIELDS[]; +extern rtk_regField_t IMR_INT_MISC_FIELDS[]; +extern rtk_regField_t IMR_EXT_PORT_LINK_STS_CHG_FIELDS[]; +extern rtk_regField_t IMR_EXT_GPHY_FIELDS[]; +extern rtk_regField_t IMR_EXT_LEARNOVER_FIELDS[]; +extern rtk_regField_t IMR_EXT_RLFD_FIELDS[]; +extern rtk_regField_t IMR_EXT_WOL_FIELDS[]; +extern rtk_regField_t IMR_EXT_SERDES_LINK_FAULT_P_FIELDS[]; +extern rtk_regField_t IMR_EXT_SDS_UPD_PHYSTS0_FIELDS[]; +extern rtk_regField_t IMR_EXT_GPIO_FIELDS[]; +extern rtk_regField_t IMR_EXT_MISC_FIELDS[]; +extern rtk_regField_t ISR_INT_GLB_FIELDS[]; +extern rtk_regField_t ISR_EXT_GLB_FIELDS[]; +extern rtk_regField_t ISR_SW_INT_MODE_FIELDS[]; +extern rtk_regField_t ISR_INT_PORT_LINK_STS_CHG_FIELDS[]; +extern rtk_regField_t ISR_INT_GPHY_FIELDS[]; +extern rtk_regField_t ISR_INT_LEARNOVER_FIELDS[]; +extern rtk_regField_t ISR_INT_TM_RLFD_FIELDS[]; +extern rtk_regField_t ISR_INT_WOL_FIELDS[]; +extern rtk_regField_t ISR_INT_SERDES_LINK_FAULT_P_FIELDS[]; +extern rtk_regField_t ISR_INT_SDS_UPD_PHYSTS0_FIELDS[]; +extern rtk_regField_t ISR_INT_GPIO_FIELDS[]; +extern rtk_regField_t ISR_INT_MISC_FIELDS[]; +extern rtk_regField_t ISR_EXT_PORT_LINK_STS_CHG_FIELDS[]; +extern rtk_regField_t ISR_EXT_GPHY_FIELDS[]; +extern rtk_regField_t ISR_EXT_LEARNOVER_FIELDS[]; +extern rtk_regField_t ISR_EXT_TM_RLFD_FIELDS[]; +extern rtk_regField_t ISR_EXT_WOL_FIELDS[]; +extern rtk_regField_t ISR_EXT_SERDES_LINK_FAULT_P_FIELDS[]; +extern rtk_regField_t ISR_EXT_SDS_UPD_PHYSTS0_FIELDS[]; +extern rtk_regField_t ISR_EXT_GPIO_FIELDS[]; +extern rtk_regField_t ISR_EXT_MISC_FIELDS[]; + +/* Module: MIB Control */ +extern rtk_regField_t STAT_RST_FIELDS[]; +extern rtk_regField_t STAT_PORT_RST_FIELDS[]; +extern rtk_regField_t STAT_CTRL_FIELDS[]; +extern rtk_regField_t STAT_CNT_SET1_CTRL_FIELDS[]; +extern rtk_regField_t STAT_CNT_SET0_CTRL_FIELDS[]; +extern rtk_regField_t PHY_MIB_GLOBAL_CONFIG_FIELDS[]; +extern rtk_regField_t DEBUG_MIB_RST_FIELDS[]; +extern rtk_regField_t INDIRECT_ACCESS_CTRL_FIELDS[]; +extern rtk_regField_t INDIRECT_ACCESS_CNT_L_FIELDS[]; +extern rtk_regField_t INDIRECT_ACCESS_CNT_H_FIELDS[]; + +/* Module: MIB Counter */ +extern rtk_regField_t PHY0_RX_MIB_CNTR0_FIELDS[]; +extern rtk_regField_t PHY0_RX_MIB_CNTR1_FIELDS[]; +extern rtk_regField_t PHY0_RX_MIB_CNTR2_FIELDS[]; +extern rtk_regField_t PHY0_RX_MIB_CNTR3_FIELDS[]; +extern rtk_regField_t PHY0_TX_MIB_CNTR0_FIELDS[]; +extern rtk_regField_t PHY0_TX_MIB_CNTR1_FIELDS[]; +extern rtk_regField_t PHY0_TX_MIB_CNTR2_FIELDS[]; +extern rtk_regField_t PHY0_TX_MIB_CNTR3_FIELDS[]; +extern rtk_regField_t PHY1_RX_MIB_CNTR0_FIELDS[]; +extern rtk_regField_t PHY1_RX_MIB_CNTR1_FIELDS[]; +extern rtk_regField_t PHY1_RX_MIB_CNTR2_FIELDS[]; +extern rtk_regField_t PHY1_RX_MIB_CNTR3_FIELDS[]; +extern rtk_regField_t PHY1_TX_MIB_CNTR0_FIELDS[]; +extern rtk_regField_t PHY1_TX_MIB_CNTR1_FIELDS[]; +extern rtk_regField_t PHY1_TX_MIB_CNTR2_FIELDS[]; +extern rtk_regField_t PHY1_TX_MIB_CNTR3_FIELDS[]; +extern rtk_regField_t PHY2_RX_MIB_CNTR0_FIELDS[]; +extern rtk_regField_t PHY2_RX_MIB_CNTR1_FIELDS[]; +extern rtk_regField_t PHY2_RX_MIB_CNTR2_FIELDS[]; +extern rtk_regField_t PHY2_RX_MIB_CNTR3_FIELDS[]; +extern rtk_regField_t PHY2_TX_MIB_CNTR0_FIELDS[]; +extern rtk_regField_t PHY2_TX_MIB_CNTR1_FIELDS[]; +extern rtk_regField_t PHY2_TX_MIB_CNTR2_FIELDS[]; +extern rtk_regField_t PHY2_TX_MIB_CNTR3_FIELDS[]; +extern rtk_regField_t PHY3_RX_MIB_CNTR0_FIELDS[]; +extern rtk_regField_t PHY3_RX_MIB_CNTR1_FIELDS[]; +extern rtk_regField_t PHY3_RX_MIB_CNTR2_FIELDS[]; +extern rtk_regField_t PHY3_RX_MIB_CNTR3_FIELDS[]; +extern rtk_regField_t PHY3_TX_MIB_CNTR0_FIELDS[]; +extern rtk_regField_t PHY3_TX_MIB_CNTR1_FIELDS[]; +extern rtk_regField_t PHY3_TX_MIB_CNTR2_FIELDS[]; +extern rtk_regField_t PHY3_TX_MIB_CNTR3_FIELDS[]; +extern rtk_regField_t SDS_CH0_RX_MIB_CNTR0_FIELDS[]; +extern rtk_regField_t SDS_CH0_RX_MIB_CNTR1_FIELDS[]; +extern rtk_regField_t SDS_CH0_RX_MIB_CNTR2_FIELDS[]; +extern rtk_regField_t SDS_CH0_RX_MIB_CNTR3_FIELDS[]; +extern rtk_regField_t SDS_CH0_TX_MIB_CNTR0_FIELDS[]; +extern rtk_regField_t SDS_CH0_TX_MIB_CNTR1_FIELDS[]; +extern rtk_regField_t SDS_CH0_TX_MIB_CNTR2_FIELDS[]; +extern rtk_regField_t SDS_CH0_TX_MIB_CNTR3_FIELDS[]; +extern rtk_regField_t SDS_CH1_RX_MIB_CNTR0_FIELDS[]; +extern rtk_regField_t SDS_CH1_RX_MIB_CNTR1_FIELDS[]; +extern rtk_regField_t SDS_CH1_RX_MIB_CNTR2_FIELDS[]; +extern rtk_regField_t SDS_CH1_RX_MIB_CNTR3_FIELDS[]; +extern rtk_regField_t SDS_CH1_TX_MIB_CNTR0_FIELDS[]; +extern rtk_regField_t SDS_CH1_TX_MIB_CNTR1_FIELDS[]; +extern rtk_regField_t SDS_CH1_TX_MIB_CNTR2_FIELDS[]; +extern rtk_regField_t SDS_CH1_TX_MIB_CNTR3_FIELDS[]; +extern rtk_regField_t SDS_CH2_RX_MIB_CNTR0_FIELDS[]; +extern rtk_regField_t SDS_CH2_RX_MIB_CNTR1_FIELDS[]; +extern rtk_regField_t SDS_CH2_RX_MIB_CNTR2_FIELDS[]; +extern rtk_regField_t SDS_CH2_RX_MIB_CNTR3_FIELDS[]; +extern rtk_regField_t SDS_CH2_TX_MIB_CNTR0_FIELDS[]; +extern rtk_regField_t SDS_CH2_TX_MIB_CNTR1_FIELDS[]; +extern rtk_regField_t SDS_CH2_TX_MIB_CNTR2_FIELDS[]; +extern rtk_regField_t SDS_CH2_TX_MIB_CNTR3_FIELDS[]; +extern rtk_regField_t SDS_CH3_RX_MIB_CNTR0_FIELDS[]; +extern rtk_regField_t SDS_CH3_RX_MIB_CNTR1_FIELDS[]; +extern rtk_regField_t SDS_CH3_RX_MIB_CNTR2_FIELDS[]; +extern rtk_regField_t SDS_CH3_RX_MIB_CNTR3_FIELDS[]; +extern rtk_regField_t SDS_CH3_TX_MIB_CNTR0_FIELDS[]; +extern rtk_regField_t SDS_CH3_TX_MIB_CNTR1_FIELDS[]; +extern rtk_regField_t SDS_CH3_TX_MIB_CNTR2_FIELDS[]; +extern rtk_regField_t SDS_CH3_TX_MIB_CNTR3_FIELDS[]; +extern rtk_regField_t DMY_REG0_MIB_DATA_FIELDS[]; +extern rtk_regField_t DMY_REG1_MIB_DATA_FIELDS[]; +extern rtk_regField_t DMY_REG2_MIB_DATA_FIELDS[]; +extern rtk_regField_t DMY_REG3_MIB_DATA_FIELDS[]; + +/* Module: MAC Control */ +extern rtk_regField_t MAC_L2_PORT_TX_MAX_LEN_CTRL_FIELDS[]; +extern rtk_regField_t SMI_BYPASS_ABLTY_LOCK_CTRL_FIELDS[]; +extern rtk_regField_t LINK_DOWN_CTRL_FIELDS[]; +extern rtk_regField_t MAC_GLB_CTRL_FIELDS[]; +extern rtk_regField_t MAC_PORT_CTRL_FIELDS[]; +extern rtk_regField_t HALF_CHG_CTRL_FIELDS[]; +extern rtk_regField_t SMI_GLB_CTRL2_FIELDS[]; +extern rtk_regField_t SMI_GLB_CTRL_FIELDS[]; +extern rtk_regField_t SMI_MAC_TYPE_CTRL_FIELDS[]; +extern rtk_regField_t SMI_PORT_POLLING_SEL_FIELDS[]; +extern rtk_regField_t SMI_MDIO_FREE_CNT_CTRL_FIELDS[]; +extern rtk_regField_t SMI_PRVTE_POLLING_CTRL_FIELDS[]; +extern rtk_regField_t SMI_10GPHY_POLLING_SEL_0_FIELDS[]; +extern rtk_regField_t MAC_FORCE_MODE_CTRL0_FIELDS[]; +extern rtk_regField_t MAC_FORCE_MODE_CTRL1_FIELDS[]; +extern rtk_regField_t SMI_REG_CHK1_CTRL1_FIELDS[]; +extern rtk_regField_t SMI_REG_CHK1_PMSK_FIELDS[]; +extern rtk_regField_t SMI_REG_CHK1_DATA_10G_FIELDS[]; +extern rtk_regField_t SMI_REG_CHK1_RESULT_FIELDS[]; +extern rtk_regField_t SMI_REG_CHK2_CTRL1_FIELDS[]; +extern rtk_regField_t SMI_REG_CHK2_PMSK_FIELDS[]; +extern rtk_regField_t SMI_REG_CHK2_DATA_10G_FIELDS[]; +extern rtk_regField_t SMI_REG_CHK2_RESULT_FIELDS[]; +extern rtk_regField_t SMI_REG_CHK3_CTRL1_FIELDS[]; +extern rtk_regField_t SMI_REG_CHK3_PMSK_FIELDS[]; +extern rtk_regField_t SMI_REG_CHK3_DATA_10G_FIELDS[]; +extern rtk_regField_t SMI_REG_CHK3_RESULT_FIELDS[]; +extern rtk_regField_t SMI_REG_CHK4_CTRL1_FIELDS[]; +extern rtk_regField_t SMI_REG_CHK4_PMSK_FIELDS[]; +extern rtk_regField_t SMI_REG_CHK4_DATA_10G_FIELDS[]; +extern rtk_regField_t SMI_REG_CHK4_RESULT_FIELDS[]; +extern rtk_regField_t SMI_REG_CHK5_CTRL1_FIELDS[]; +extern rtk_regField_t SMI_REG_CHK5_PMSK_FIELDS[]; +extern rtk_regField_t SMI_REG_CHK5_DATA_10G_FIELDS[]; +extern rtk_regField_t SMI_REG_CHK5_RESULT_FIELDS[]; +extern rtk_regField_t LINK_DELAY_CTRL_FIELDS[]; +extern rtk_regField_t MAC_LINK_STS_FIELDS[]; +extern rtk_regField_t MAC_LINK_MEDIA_STS_FIELDS[]; +extern rtk_regField_t MAC_LINK_SPD_STS_FIELDS[]; +extern rtk_regField_t MAC_LINK_DUP_STS_FIELDS[]; +extern rtk_regField_t MAC_TX_PAUSE_STS_FIELDS[]; +extern rtk_regField_t MAC_RX_PAUSE_STS_FIELDS[]; +extern rtk_regField_t MAC_EEE_ABLTY_FIELDS[]; +extern rtk_regField_t MAC_MSTR_SLV_STS_FIELDS[]; +extern rtk_regField_t MAC_MSTR_SLV_FAULT_STS_FIELDS[]; +extern rtk_regField_t PHY_LINK_STS_FIELDS[]; +extern rtk_regField_t PHY_LINK_MEDIA_STS_FIELDS[]; +extern rtk_regField_t PHY_LINK_SPD_STS_FIELDS[]; +extern rtk_regField_t PHY_LINK_DUP_STS_FIELDS[]; +extern rtk_regField_t PHY_TX_PAUSE_STS_FIELDS[]; +extern rtk_regField_t PHY_RX_PAUSE_STS_FIELDS[]; +extern rtk_regField_t PHY_EEE_ABLTY_FIELDS[]; +extern rtk_regField_t PHY_MSTR_SLV_STS_FIELDS[]; +extern rtk_regField_t PHY_MSTR_SLV_FAULT_STS_FIELDS[]; +extern rtk_regField_t SMI_ACCESS_PHY_CTRL_0_FIELDS[]; +extern rtk_regField_t SMI_ACCESS_PHY_CTRL_1_FIELDS[]; +extern rtk_regField_t SMI_ACCESS_PHY_CTRL_2_FIELDS[]; +extern rtk_regField_t SMI_ACCESS_PHY_CTRL_3_FIELDS[]; +extern rtk_regField_t SMI_ACCESS_PHY_CTRL_4_FIELDS[]; +extern rtk_regField_t SMI_PORT0_5_ADDR_CTRL_FIELDS[]; +extern rtk_regField_t SMI_PORT6_9_ADDR_CTRL_FIELDS[]; +extern rtk_regField_t SMI_CTRL_FIELDS[]; +extern rtk_regField_t RLFD_CTRL_FIELDS[]; +extern rtk_regField_t RLFD_10G_ADDR_FIELDS[]; +extern rtk_regField_t UNI_DIR_CTRL_FIELDS[]; +extern rtk_regField_t SMI_10GPHY_POLLING_SEL_1_FIELDS[]; +extern rtk_regField_t SMI_10GPHY_POLLING_REG0_CFG_FIELDS[]; +extern rtk_regField_t SMI_10GPHY_POLLING_REG9_CFG_FIELDS[]; +extern rtk_regField_t SMI_10GPHY_POLLING_REG10_CFG_FIELDS[]; +extern rtk_regField_t MAC_CTRL_1_FIELDS[]; +extern rtk_regField_t MAC_CTRL_2_FIELDS[]; +extern rtk_regField_t MAC8_RTL8226B_CTRL_FIELDS[]; +extern rtk_regField_t TX_RX_IDLE_FIELDS[]; +extern rtk_regField_t IDLE_DLY_CTRL_FIELDS[]; +extern rtk_regField_t MAC_IPG_COMPS_CTRL_FIELDS[]; +extern rtk_regField_t MAC_L2_GLOBAL_CTRL0_FIELDS[]; +extern rtk_regField_t MAC_L2_GLOBAL_CTRL1_FIELDS[]; +extern rtk_regField_t MAC_L2_PORT_CTRL_FIELDS[]; +extern rtk_regField_t MAC_MACSEC_IPG_CFG_FIELDS[]; +extern rtk_regField_t MAC_MACSEC_ETH_1_0_FIELDS[]; +extern rtk_regField_t MAC_MACSEC_ETH_3_2_FIELDS[]; +extern rtk_regField_t MAC_MACSEC_ETH_5_4_FIELDS[]; +extern rtk_regField_t MAC_MACSEC_ETH_7_6_FIELDS[]; +extern rtk_regField_t MAC_L2_PADDING_SEL_FIELDS[]; +extern rtk_regField_t MAC_L2_ADDR_CTRL_FIELDS[]; +extern rtk_regField_t MAC_L2_PORT_MAX_LEN_CTRL_FIELDS[]; +extern rtk_regField_t MAC_L2_TGPORT_PRMB_DBG0_FIELDS[]; +extern rtk_regField_t MAC_L2_TGPORT_PRMB_DBG1_FIELDS[]; +extern rtk_regField_t PHY_CFG_8224_FIELDS[]; +extern rtk_regField_t MDX_CTRL_8224_FIELDS[]; +extern rtk_regField_t INT_PHY_OCP_INDR_ACC_CTRL_0_FIELDS[]; +extern rtk_regField_t INT_PHY_OCP_INDR_ACC_CTRL_1_FIELDS[]; +extern rtk_regField_t INT_PHY_OCP_INDR_ACC_CTRL_2_FIELDS[]; +extern rtk_regField_t MAC_PFC_FORCE_FC_FIELDS[]; +extern rtk_regField_t MAC_TXFIFO_FULTH_CTRL_0_FIELDS[]; +extern rtk_regField_t MAC_TXFIFO_FULTH_CTRL_1_FIELDS[]; +extern rtk_regField_t MAC_TXFIFO_FULTH_CTRL_2_FIELDS[]; +extern rtk_regField_t MAC_TXFIFO_FULTH_CTRL_3_FIELDS[]; +extern rtk_regField_t MAC_TXFIFO_FULTH_CTRL_4_FIELDS[]; +extern rtk_regField_t MAC_TXFIFO_FULTH_CTRL_5_FIELDS[]; +extern rtk_regField_t MACSEC_REG_GLB_SET1_PORT4_FIELDS[]; +extern rtk_regField_t MACSEC_REG_GLB_IMR_PORT4_FIELDS[]; +extern rtk_regField_t MACSEC_REG_GLB_ISR_PORT4_FIELDS[]; +extern rtk_regField_t UNUSED_000C_PORT4_FIELDS[]; +extern rtk_regField_t MACSEC_PM_CTRL_PORT4_FIELDS[]; +extern rtk_regField_t MACSEC_REG_GLB_MASK_PORT4_FIELDS[]; +extern rtk_regField_t MACSEC_REG_GLB_SET4_PORT4_FIELDS[]; +extern rtk_regField_t MACSEC_REG_IP_PROBE_PORT4_FIELDS[]; +extern rtk_regField_t UNUSED_0020_PORT4_FIELDS[]; +extern rtk_regField_t UNUSED_0024_PORT4_FIELDS[]; +extern rtk_regField_t MACSEC_MBIST_SA_CTRL_PORT4_FIELDS[]; +extern rtk_regField_t MACSEC_MBIST_STAT_CTRL_PORT4_FIELDS[]; +extern rtk_regField_t MACSEC_MBIST_SA_AE_TEST_PORT4_FIELDS[]; +extern rtk_regField_t MACSEC_MBIST_STAT_AE_TEST_PORT4_FIELDS[]; +extern rtk_regField_t MACSEC_MBIST_SA_FAIL_PORT4_FIELDS[]; +extern rtk_regField_t MACSEC_XGLBK_FIFO_DBG_PORT4_FIELDS[]; +extern rtk_regField_t MACSEC_REG_RWDH_AE_PORT4_FIELDS[]; +extern rtk_regField_t MACSEC_REG_ADDR_AE_PORT4_FIELDS[]; +extern rtk_regField_t MACSEC_REG_CMD_AE_PORT4_FIELDS[]; +extern rtk_regField_t MACSEC_REG_RWDL_AI_PORT4_FIELDS[]; +extern rtk_regField_t MACSEC_REG_ADDR_AI_PORT4_FIELDS[]; +extern rtk_regField_t MACSEC_REG_RWD_PTP_PORT4_FIELDS[]; +extern rtk_regField_t MACSEC_REG_CMD_PTP_PORT4_FIELDS[]; +extern rtk_regField_t UNUSED_005C_PORT4_FIELDS[]; +extern rtk_regField_t UNUSED_0060_PORT4_FIELDS[]; +extern rtk_regField_t UNUSED_0064_PORT4_FIELDS[]; +extern rtk_regField_t UNUSED_0068_PORT4_FIELDS[]; +extern rtk_regField_t UNUSED_006C_PORT4_FIELDS[]; +extern rtk_regField_t UNUSED_0070_PORT4_FIELDS[]; +extern rtk_regField_t UNUSED_0074_PORT4_FIELDS[]; +extern rtk_regField_t RESERVED_0078_PORT4_FIELDS[]; +extern rtk_regField_t RESERVED_007C_PORT4_FIELDS[]; +extern rtk_regField_t MACSEC_TXSYSCRCERR_CNT_PORT4_FIELDS[]; +extern rtk_regField_t MACSEC_TXSYSPKTERR_CNT_PORT4_FIELDS[]; +extern rtk_regField_t MACSEC_TXSYSOK_CNT_0_PORT4_FIELDS[]; +extern rtk_regField_t MACSEC_TXSYSOK_CNT_2_PORT4_FIELDS[]; +extern rtk_regField_t MACSEC_TXSYSGERR_CNT_PORT4_FIELDS[]; +extern rtk_regField_t MACSEC_TXSYSGLPIERR_CNT_PORT4_FIELDS[]; +extern rtk_regField_t MACSEC_TXSYS_DBG_PORT4_FIELDS[]; +extern rtk_regField_t MACSEC_TX_RX_CNT_INCR_PORT4_FIELDS[]; +extern rtk_regField_t MACSEC_TXLINECRCERR_CNT_PORT4_FIELDS[]; +extern rtk_regField_t MACSEC_TXLINEPKTERR_CNT_PORT4_FIELDS[]; +extern rtk_regField_t MACSEC_TXLINEOK_CNT_0_PORT4_FIELDS[]; +extern rtk_regField_t MACSEC_TXLINEOK_CNT_2_PORT4_FIELDS[]; +extern rtk_regField_t MACSEC_TXLINEDROP_CNT_PORT4_FIELDS[]; +extern rtk_regField_t MACSEC_TXLINESRT_CNT_PORT4_FIELDS[]; +extern rtk_regField_t MACSEC_TXLINEGERR_CNT_PORT4_FIELDS[]; +extern rtk_regField_t MACSEC_TXLINE_DBG_PORT4_FIELDS[]; +extern rtk_regField_t MACSEC_RXLINECRCERR_CNT_PORT4_FIELDS[]; +extern rtk_regField_t MACSEC_RXLINEPKTERR_CNT_PORT4_FIELDS[]; +extern rtk_regField_t MACSEC_RXLINEOK_CNT_0_PORT4_FIELDS[]; +extern rtk_regField_t MACSEC_RXLINEOK_CNT_2_PORT4_FIELDS[]; +extern rtk_regField_t MACSEC_RXLINESRT_CNT_PORT4_FIELDS[]; +extern rtk_regField_t MACSEC_RXLINEGERR_CNT_PORT4_FIELDS[]; +extern rtk_regField_t MACSEC_RXLINEGLPIERR_CNT_PORT4_FIELDS[]; +extern rtk_regField_t MACSEC_RXLINE_DBG_PORT4_FIELDS[]; +extern rtk_regField_t MACSEC_RXSYSCRCERR_CNT_PORT4_FIELDS[]; +extern rtk_regField_t MACSEC_RXSYSPKTERR_CNT_PORT4_FIELDS[]; +extern rtk_regField_t MACSEC_RXSYSOK_CNT_0_PORT4_FIELDS[]; +extern rtk_regField_t MACSEC_RXSYSOK_CNT_2_PORT4_FIELDS[]; +extern rtk_regField_t MACSEC_RXSYSDROP_CNT_PORT4_FIELDS[]; +extern rtk_regField_t MACSEC_RXSYSSRT_CNT_PORT4_FIELDS[]; +extern rtk_regField_t MACSEC_RXSYSGERR_CNT_PORT4_FIELDS[]; +extern rtk_regField_t MACSEC_RXSYS_DBG_PORT4_FIELDS[]; +extern rtk_regField_t MACSEC_TXSYS_CFG1_PORT4_FIELDS[]; +extern rtk_regField_t MACSEC_TXSYS_PTPCFG_PORT4_FIELDS[]; +extern rtk_regField_t MACSEC_TXSYS_OUTERVLAN2_PORT4_FIELDS[]; +extern rtk_regField_t MACSEC_TXSYS_OUTERVLAN4_PORT4_FIELDS[]; +extern rtk_regField_t MACSEC_TXSYS_INNERVLAN2_PORT4_FIELDS[]; +extern rtk_regField_t MACSEC_TXSYS_INNERVLAN4_PORT4_FIELDS[]; +extern rtk_regField_t MACSEC_TXSYS_INNERVLAN6_PORT4_FIELDS[]; +extern rtk_regField_t UNUSED_011C_PORT4_FIELDS[]; +extern rtk_regField_t UNUSED_0120_PORT4_FIELDS[]; +extern rtk_regField_t UNUSED_0124_PORT4_FIELDS[]; +extern rtk_regField_t UNUSED_0128_PORT4_FIELDS[]; +extern rtk_regField_t UNUSED_012C_PORT4_FIELDS[]; +extern rtk_regField_t UNUSED_0130_PORT4_FIELDS[]; +extern rtk_regField_t UNUSED_0134_PORT4_FIELDS[]; +extern rtk_regField_t UNUSED_0138_PORT4_FIELDS[]; +extern rtk_regField_t UNUSED_013C_PORT4_FIELDS[]; +extern rtk_regField_t MACSEC_TXLINE_CFG1_PORT4_FIELDS[]; +extern rtk_regField_t MACSEC_TXLINE_CFG3_PORT4_FIELDS[]; +extern rtk_regField_t MACSEC_TXLINE_CFG5_PORT4_FIELDS[]; +extern rtk_regField_t UNUSED_014C_PORT4_FIELDS[]; +extern rtk_regField_t UNUSED_0150_PORT4_FIELDS[]; +extern rtk_regField_t UNUSED_0154_PORT4_FIELDS[]; +extern rtk_regField_t UNUSED_0158_PORT4_FIELDS[]; +extern rtk_regField_t UNUSED_015C_PORT4_FIELDS[]; +extern rtk_regField_t UNUSED_0160_PORT4_FIELDS[]; +extern rtk_regField_t UNUSED_0164_PORT4_FIELDS[]; +extern rtk_regField_t UNUSED_0168_PORT4_FIELDS[]; +extern rtk_regField_t UNUSED_016C_PORT4_FIELDS[]; +extern rtk_regField_t UNUSED_0170_PORT4_FIELDS[]; +extern rtk_regField_t UNUSED_0174_PORT4_FIELDS[]; +extern rtk_regField_t UNUSED_0178_PORT4_FIELDS[]; +extern rtk_regField_t UNUSED_017C_PORT4_FIELDS[]; +extern rtk_regField_t MACSEC_RXLINE_CFG1_PORT4_FIELDS[]; +extern rtk_regField_t UNUSED_0184_PORT4_FIELDS[]; +extern rtk_regField_t UNUSED_0188_PORT4_FIELDS[]; +extern rtk_regField_t UNUSED_018C_PORT4_FIELDS[]; +extern rtk_regField_t UNUSED_0190_PORT4_FIELDS[]; +extern rtk_regField_t UNUSED_0194_PORT4_FIELDS[]; +extern rtk_regField_t UNUSED_0198_PORT4_FIELDS[]; +extern rtk_regField_t UNUSED_019C_PORT4_FIELDS[]; +extern rtk_regField_t UNUSED_01A0_PORT4_FIELDS[]; +extern rtk_regField_t UNUSED_01A4_PORT4_FIELDS[]; +extern rtk_regField_t UNUSED_01A8_PORT4_FIELDS[]; +extern rtk_regField_t UNUSED_01AC_PORT4_FIELDS[]; +extern rtk_regField_t UNUSED_01B0_PORT4_FIELDS[]; +extern rtk_regField_t UNUSED_01B4_PORT4_FIELDS[]; +extern rtk_regField_t UNUSED_01B8_PORT4_FIELDS[]; +extern rtk_regField_t UNUSED_01BC_PORT4_FIELDS[]; +extern rtk_regField_t MACSEC_RXSYS_CFG1_PORT4_FIELDS[]; +extern rtk_regField_t MACSEC_RXSYS_CFG3_PORT4_FIELDS[]; +extern rtk_regField_t MACSEC_RXSYS_OUTERVLAN2_PORT4_FIELDS[]; +extern rtk_regField_t MACSEC_RXSYS_OUTERVLAN4_PORT4_FIELDS[]; +extern rtk_regField_t MACSEC_RXSYS_INNERVLAN2_PORT4_FIELDS[]; +extern rtk_regField_t MACSEC_RXSYS_INNERVLAN4_PORT4_FIELDS[]; +extern rtk_regField_t MACSEC_RXSYS_INNERVLAN6_PORT4_FIELDS[]; +extern rtk_regField_t MACSEC_RXSYS_CFG4_PORT4_FIELDS[]; +extern rtk_regField_t MACSEC_RXSYS_CFG6_PORT4_FIELDS[]; +extern rtk_regField_t MACSEC_REG_GLB_SET1_PORT5_FIELDS[]; +extern rtk_regField_t MACSEC_REG_GLB_IMR_PORT5_FIELDS[]; +extern rtk_regField_t MACSEC_REG_GLB_ISR_PORT5_FIELDS[]; +extern rtk_regField_t UNUSED_000C_PORT5_FIELDS[]; +extern rtk_regField_t MACSEC_PM_CTRL_PORT5_FIELDS[]; +extern rtk_regField_t MACSEC_REG_GLB_MASK_PORT5_FIELDS[]; +extern rtk_regField_t MACSEC_REG_GLB_SET4_PORT5_FIELDS[]; +extern rtk_regField_t MACSEC_REG_IP_PROBE_PORT5_FIELDS[]; +extern rtk_regField_t UNUSED_0020_PORT5_FIELDS[]; +extern rtk_regField_t UNUSED_0024_PORT5_FIELDS[]; +extern rtk_regField_t MACSEC_MBIST_SA_CTRL_PORT5_FIELDS[]; +extern rtk_regField_t MACSEC_MBIST_STAT_CTRL_PORT5_FIELDS[]; +extern rtk_regField_t MACSEC_MBIST_SA_AE_TEST_PORT5_FIELDS[]; +extern rtk_regField_t MACSEC_MBIST_STAT_AE_TEST_PORT5_FIELDS[]; +extern rtk_regField_t MACSEC_MBIST_SA_FAIL_PORT5_FIELDS[]; +extern rtk_regField_t MACSEC_XGLBK_FIFO_DBG_PORT5_FIELDS[]; +extern rtk_regField_t MACSEC_REG_RWDH_AE_PORT5_FIELDS[]; +extern rtk_regField_t MACSEC_REG_ADDR_AE_PORT5_FIELDS[]; +extern rtk_regField_t MACSEC_REG_CMD_AE_PORT5_FIELDS[]; +extern rtk_regField_t MACSEC_REG_RWDL_AI_PORT5_FIELDS[]; +extern rtk_regField_t MACSEC_REG_ADDR_AI_PORT5_FIELDS[]; +extern rtk_regField_t MACSEC_REG_RWD_PTP_PORT5_FIELDS[]; +extern rtk_regField_t MACSEC_REG_CMD_PTP_PORT5_FIELDS[]; +extern rtk_regField_t UNUSED_005C_PORT5_FIELDS[]; +extern rtk_regField_t UNUSED_0060_PORT5_FIELDS[]; +extern rtk_regField_t UNUSED_0064_PORT5_FIELDS[]; +extern rtk_regField_t UNUSED_0068_PORT5_FIELDS[]; +extern rtk_regField_t UNUSED_006C_PORT5_FIELDS[]; +extern rtk_regField_t UNUSED_0070_PORT5_FIELDS[]; +extern rtk_regField_t UNUSED_0074_PORT5_FIELDS[]; +extern rtk_regField_t RESERVED_0078_PORT5_FIELDS[]; +extern rtk_regField_t RESERVED_007C_PORT5_FIELDS[]; +extern rtk_regField_t MACSEC_TXSYSCRCERR_CNT_PORT5_FIELDS[]; +extern rtk_regField_t MACSEC_TXSYSPKTERR_CNT_PORT5_FIELDS[]; +extern rtk_regField_t MACSEC_TXSYSOK_CNT_0_PORT5_FIELDS[]; +extern rtk_regField_t MACSEC_TXSYSOK_CNT_2_PORT5_FIELDS[]; +extern rtk_regField_t MACSEC_TXSYSGERR_CNT_PORT5_FIELDS[]; +extern rtk_regField_t MACSEC_TXSYSGLPIERR_CNT_PORT5_FIELDS[]; +extern rtk_regField_t MACSEC_TXSYS_DBG_PORT5_FIELDS[]; +extern rtk_regField_t MACSEC_TX_RX_CNT_INCR_PORT5_FIELDS[]; +extern rtk_regField_t MACSEC_TXLINECRCERR_CNT_PORT5_FIELDS[]; +extern rtk_regField_t MACSEC_TXLINEPKTERR_CNT_PORT5_FIELDS[]; +extern rtk_regField_t MACSEC_TXLINEOK_CNT_0_PORT5_FIELDS[]; +extern rtk_regField_t MACSEC_TXLINEOK_CNT_2_PORT5_FIELDS[]; +extern rtk_regField_t MACSEC_TXLINEDROP_CNT_PORT5_FIELDS[]; +extern rtk_regField_t MACSEC_TXLINESRT_CNT_PORT5_FIELDS[]; +extern rtk_regField_t MACSEC_TXLINEGERR_CNT_PORT5_FIELDS[]; +extern rtk_regField_t MACSEC_TXLINE_DBG_PORT5_FIELDS[]; +extern rtk_regField_t MACSEC_RXLINECRCERR_CNT_PORT5_FIELDS[]; +extern rtk_regField_t MACSEC_RXLINEPKTERR_CNT_PORT5_FIELDS[]; +extern rtk_regField_t MACSEC_RXLINEOK_CNT_0_PORT5_FIELDS[]; +extern rtk_regField_t MACSEC_RXLINEOK_CNT_2_PORT5_FIELDS[]; +extern rtk_regField_t MACSEC_RXLINESRT_CNT_PORT5_FIELDS[]; +extern rtk_regField_t MACSEC_RXLINEGERR_CNT_PORT5_FIELDS[]; +extern rtk_regField_t MACSEC_RXLINEGLPIERR_CNT_PORT5_FIELDS[]; +extern rtk_regField_t MACSEC_RXLINE_DBG_PORT5_FIELDS[]; +extern rtk_regField_t MACSEC_RXSYSCRCERR_CNT_PORT5_FIELDS[]; +extern rtk_regField_t MACSEC_RXSYSPKTERR_CNT_PORT5_FIELDS[]; +extern rtk_regField_t MACSEC_RXSYSOK_CNT_0_PORT5_FIELDS[]; +extern rtk_regField_t MACSEC_RXSYSOK_CNT_2_PORT5_FIELDS[]; +extern rtk_regField_t MACSEC_RXSYSDROP_CNT_PORT5_FIELDS[]; +extern rtk_regField_t MACSEC_RXSYSSRT_CNT_PORT5_FIELDS[]; +extern rtk_regField_t MACSEC_RXSYSGERR_CNT_PORT5_FIELDS[]; +extern rtk_regField_t MACSEC_RXSYS_DBG_PORT5_FIELDS[]; +extern rtk_regField_t MACSEC_TXSYS_CFG1_PORT5_FIELDS[]; +extern rtk_regField_t MACSEC_TXSYS_PTPCFG_PORT5_FIELDS[]; +extern rtk_regField_t MACSEC_TXSYS_OUTERVLAN2_PORT5_FIELDS[]; +extern rtk_regField_t MACSEC_TXSYS_OUTERVLAN4_PORT5_FIELDS[]; +extern rtk_regField_t MACSEC_TXSYS_INNERVLAN2_PORT5_FIELDS[]; +extern rtk_regField_t MACSEC_TXSYS_INNERVLAN4_PORT5_FIELDS[]; +extern rtk_regField_t MACSEC_TXSYS_INNERVLAN6_PORT5_FIELDS[]; +extern rtk_regField_t UNUSED_011C_PORT5_FIELDS[]; +extern rtk_regField_t UNUSED_0120_PORT5_FIELDS[]; +extern rtk_regField_t UNUSED_0124_PORT5_FIELDS[]; +extern rtk_regField_t UNUSED_0128_PORT5_FIELDS[]; +extern rtk_regField_t UNUSED_012C_PORT5_FIELDS[]; +extern rtk_regField_t UNUSED_0130_PORT5_FIELDS[]; +extern rtk_regField_t UNUSED_0134_PORT5_FIELDS[]; +extern rtk_regField_t UNUSED_0138_PORT5_FIELDS[]; +extern rtk_regField_t UNUSED_013C_PORT5_FIELDS[]; +extern rtk_regField_t MACSEC_TXLINE_CFG1_PORT5_FIELDS[]; +extern rtk_regField_t MACSEC_TXLINE_CFG3_PORT5_FIELDS[]; +extern rtk_regField_t MACSEC_TXLINE_CFG5_PORT5_FIELDS[]; +extern rtk_regField_t UNUSED_014C_PORT5_FIELDS[]; +extern rtk_regField_t UNUSED_0150_PORT5_FIELDS[]; +extern rtk_regField_t UNUSED_0154_PORT5_FIELDS[]; +extern rtk_regField_t UNUSED_0158_PORT5_FIELDS[]; +extern rtk_regField_t UNUSED_015C_PORT5_FIELDS[]; +extern rtk_regField_t UNUSED_0160_PORT5_FIELDS[]; +extern rtk_regField_t UNUSED_0164_PORT5_FIELDS[]; +extern rtk_regField_t UNUSED_0168_PORT5_FIELDS[]; +extern rtk_regField_t UNUSED_016C_PORT5_FIELDS[]; +extern rtk_regField_t UNUSED_0170_PORT5_FIELDS[]; +extern rtk_regField_t UNUSED_0174_PORT5_FIELDS[]; +extern rtk_regField_t UNUSED_0178_PORT5_FIELDS[]; +extern rtk_regField_t UNUSED_017C_PORT5_FIELDS[]; +extern rtk_regField_t MACSEC_RXLINE_CFG1_PORT5_FIELDS[]; +extern rtk_regField_t UNUSED_0184_PORT5_FIELDS[]; +extern rtk_regField_t UNUSED_0188_PORT5_FIELDS[]; +extern rtk_regField_t UNUSED_018C_PORT5_FIELDS[]; +extern rtk_regField_t UNUSED_0190_PORT5_FIELDS[]; +extern rtk_regField_t UNUSED_0194_PORT5_FIELDS[]; +extern rtk_regField_t UNUSED_0198_PORT5_FIELDS[]; +extern rtk_regField_t UNUSED_019C_PORT5_FIELDS[]; +extern rtk_regField_t UNUSED_01A0_PORT5_FIELDS[]; +extern rtk_regField_t UNUSED_01A4_PORT5_FIELDS[]; +extern rtk_regField_t UNUSED_01A8_PORT5_FIELDS[]; +extern rtk_regField_t UNUSED_01AC_PORT5_FIELDS[]; +extern rtk_regField_t UNUSED_01B0_PORT5_FIELDS[]; +extern rtk_regField_t UNUSED_01B4_PORT5_FIELDS[]; +extern rtk_regField_t UNUSED_01B8_PORT5_FIELDS[]; +extern rtk_regField_t UNUSED_01BC_PORT5_FIELDS[]; +extern rtk_regField_t MACSEC_RXSYS_CFG1_PORT5_FIELDS[]; +extern rtk_regField_t MACSEC_RXSYS_CFG3_PORT5_FIELDS[]; +extern rtk_regField_t MACSEC_RXSYS_OUTERVLAN2_PORT5_FIELDS[]; +extern rtk_regField_t MACSEC_RXSYS_OUTERVLAN4_PORT5_FIELDS[]; +extern rtk_regField_t MACSEC_RXSYS_INNERVLAN2_PORT5_FIELDS[]; +extern rtk_regField_t MACSEC_RXSYS_INNERVLAN4_PORT5_FIELDS[]; +extern rtk_regField_t MACSEC_RXSYS_INNERVLAN6_PORT5_FIELDS[]; +extern rtk_regField_t MACSEC_RXSYS_CFG4_PORT5_FIELDS[]; +extern rtk_regField_t MACSEC_RXSYS_CFG6_PORT5_FIELDS[]; +extern rtk_regField_t MACSEC_REG_GLB_SET1_PORT6_FIELDS[]; +extern rtk_regField_t MACSEC_REG_GLB_IMR_PORT6_FIELDS[]; +extern rtk_regField_t MACSEC_REG_GLB_ISR_PORT6_FIELDS[]; +extern rtk_regField_t UNUSED_000C_PORT6_FIELDS[]; +extern rtk_regField_t MACSEC_PM_CTRL_PORT6_FIELDS[]; +extern rtk_regField_t MACSEC_REG_GLB_MASK_PORT6_FIELDS[]; +extern rtk_regField_t MACSEC_REG_GLB_SET4_PORT6_FIELDS[]; +extern rtk_regField_t MACSEC_REG_IP_PROBE_PORT6_FIELDS[]; +extern rtk_regField_t UNUSED_0020_PORT6_FIELDS[]; +extern rtk_regField_t UNUSED_0024_PORT6_FIELDS[]; +extern rtk_regField_t MACSEC_MBIST_SA_CTRL_PORT6_FIELDS[]; +extern rtk_regField_t MACSEC_MBIST_STAT_CTRL_PORT6_FIELDS[]; +extern rtk_regField_t MACSEC_MBIST_SA_AE_TEST_PORT6_FIELDS[]; +extern rtk_regField_t MACSEC_MBIST_STAT_AE_TEST_PORT6_FIELDS[]; +extern rtk_regField_t MACSEC_MBIST_SA_FAIL_PORT6_FIELDS[]; +extern rtk_regField_t MACSEC_XGLBK_FIFO_DBG_PORT6_FIELDS[]; +extern rtk_regField_t MACSEC_REG_RWDH_AE_PORT6_FIELDS[]; +extern rtk_regField_t MACSEC_REG_ADDR_AE_PORT6_FIELDS[]; +extern rtk_regField_t MACSEC_REG_CMD_AE_PORT6_FIELDS[]; +extern rtk_regField_t MACSEC_REG_RWDL_AI_PORT6_FIELDS[]; +extern rtk_regField_t MACSEC_REG_ADDR_AI_PORT6_FIELDS[]; +extern rtk_regField_t MACSEC_REG_RWD_PTP_PORT6_FIELDS[]; +extern rtk_regField_t MACSEC_REG_CMD_PTP_PORT6_FIELDS[]; +extern rtk_regField_t UNUSED_005C_PORT6_FIELDS[]; +extern rtk_regField_t UNUSED_0060_PORT6_FIELDS[]; +extern rtk_regField_t UNUSED_0064_PORT6_FIELDS[]; +extern rtk_regField_t UNUSED_0068_PORT6_FIELDS[]; +extern rtk_regField_t UNUSED_006C_PORT6_FIELDS[]; +extern rtk_regField_t UNUSED_0070_PORT6_FIELDS[]; +extern rtk_regField_t UNUSED_0074_PORT6_FIELDS[]; +extern rtk_regField_t RESERVED_0078_PORT6_FIELDS[]; +extern rtk_regField_t RESERVED_007C_PORT6_FIELDS[]; +extern rtk_regField_t MACSEC_TXSYSCRCERR_CNT_PORT6_FIELDS[]; +extern rtk_regField_t MACSEC_TXSYSPKTERR_CNT_PORT6_FIELDS[]; +extern rtk_regField_t MACSEC_TXSYSOK_CNT_0_PORT6_FIELDS[]; +extern rtk_regField_t MACSEC_TXSYSOK_CNT_2_PORT6_FIELDS[]; +extern rtk_regField_t MACSEC_TXSYSGERR_CNT_PORT6_FIELDS[]; +extern rtk_regField_t MACSEC_TXSYSGLPIERR_CNT_PORT6_FIELDS[]; +extern rtk_regField_t MACSEC_TXSYS_DBG_PORT6_FIELDS[]; +extern rtk_regField_t MACSEC_TX_RX_CNT_INCR_PORT6_FIELDS[]; +extern rtk_regField_t MACSEC_TXLINECRCERR_CNT_PORT6_FIELDS[]; +extern rtk_regField_t MACSEC_TXLINEPKTERR_CNT_PORT6_FIELDS[]; +extern rtk_regField_t MACSEC_TXLINEOK_CNT_0_PORT6_FIELDS[]; +extern rtk_regField_t MACSEC_TXLINEOK_CNT_2_PORT6_FIELDS[]; +extern rtk_regField_t MACSEC_TXLINEDROP_CNT_PORT6_FIELDS[]; +extern rtk_regField_t MACSEC_TXLINESRT_CNT_PORT6_FIELDS[]; +extern rtk_regField_t MACSEC_TXLINEGERR_CNT_PORT6_FIELDS[]; +extern rtk_regField_t MACSEC_TXLINE_DBG_PORT6_FIELDS[]; +extern rtk_regField_t MACSEC_RXLINECRCERR_CNT_PORT6_FIELDS[]; +extern rtk_regField_t MACSEC_RXLINEPKTERR_CNT_PORT6_FIELDS[]; +extern rtk_regField_t MACSEC_RXLINEOK_CNT_0_PORT6_FIELDS[]; +extern rtk_regField_t MACSEC_RXLINEOK_CNT_2_PORT6_FIELDS[]; +extern rtk_regField_t MACSEC_RXLINESRT_CNT_PORT6_FIELDS[]; +extern rtk_regField_t MACSEC_RXLINEGERR_CNT_PORT6_FIELDS[]; +extern rtk_regField_t MACSEC_RXLINEGLPIERR_CNT_PORT6_FIELDS[]; +extern rtk_regField_t MACSEC_RXLINE_DBG_PORT6_FIELDS[]; +extern rtk_regField_t MACSEC_RXSYSCRCERR_CNT_PORT6_FIELDS[]; +extern rtk_regField_t MACSEC_RXSYSPKTERR_CNT_PORT6_FIELDS[]; +extern rtk_regField_t MACSEC_RXSYSOK_CNT_0_PORT6_FIELDS[]; +extern rtk_regField_t MACSEC_RXSYSOK_CNT_2_PORT6_FIELDS[]; +extern rtk_regField_t MACSEC_RXSYSDROP_CNT_PORT6_FIELDS[]; +extern rtk_regField_t MACSEC_RXSYSSRT_CNT_PORT6_FIELDS[]; +extern rtk_regField_t MACSEC_RXSYSGERR_CNT_PORT6_FIELDS[]; +extern rtk_regField_t MACSEC_RXSYS_DBG_PORT6_FIELDS[]; +extern rtk_regField_t MACSEC_TXSYS_CFG1_PORT6_FIELDS[]; +extern rtk_regField_t MACSEC_TXSYS_PTPCFG_PORT6_FIELDS[]; +extern rtk_regField_t MACSEC_TXSYS_OUTERVLAN2_PORT6_FIELDS[]; +extern rtk_regField_t MACSEC_TXSYS_OUTERVLAN4_PORT6_FIELDS[]; +extern rtk_regField_t MACSEC_TXSYS_INNERVLAN2_PORT6_FIELDS[]; +extern rtk_regField_t MACSEC_TXSYS_INNERVLAN4_PORT6_FIELDS[]; +extern rtk_regField_t MACSEC_TXSYS_INNERVLAN6_PORT6_FIELDS[]; +extern rtk_regField_t UNUSED_011C_PORT6_FIELDS[]; +extern rtk_regField_t UNUSED_0120_PORT6_FIELDS[]; +extern rtk_regField_t UNUSED_0124_PORT6_FIELDS[]; +extern rtk_regField_t UNUSED_0128_PORT6_FIELDS[]; +extern rtk_regField_t UNUSED_012C_PORT6_FIELDS[]; +extern rtk_regField_t UNUSED_0130_PORT6_FIELDS[]; +extern rtk_regField_t UNUSED_0134_PORT6_FIELDS[]; +extern rtk_regField_t UNUSED_0138_PORT6_FIELDS[]; +extern rtk_regField_t UNUSED_013C_PORT6_FIELDS[]; +extern rtk_regField_t MACSEC_TXLINE_CFG1_PORT6_FIELDS[]; +extern rtk_regField_t MACSEC_TXLINE_CFG3_PORT6_FIELDS[]; +extern rtk_regField_t MACSEC_TXLINE_CFG5_PORT6_FIELDS[]; +extern rtk_regField_t UNUSED_014C_PORT6_FIELDS[]; +extern rtk_regField_t UNUSED_0150_PORT6_FIELDS[]; +extern rtk_regField_t UNUSED_0154_PORT6_FIELDS[]; +extern rtk_regField_t UNUSED_0158_PORT6_FIELDS[]; +extern rtk_regField_t UNUSED_015C_PORT6_FIELDS[]; +extern rtk_regField_t UNUSED_0160_PORT6_FIELDS[]; +extern rtk_regField_t UNUSED_0164_PORT6_FIELDS[]; +extern rtk_regField_t UNUSED_0168_PORT6_FIELDS[]; +extern rtk_regField_t UNUSED_016C_PORT6_FIELDS[]; +extern rtk_regField_t UNUSED_0170_PORT6_FIELDS[]; +extern rtk_regField_t UNUSED_0174_PORT6_FIELDS[]; +extern rtk_regField_t UNUSED_0178_PORT6_FIELDS[]; +extern rtk_regField_t UNUSED_017C_PORT6_FIELDS[]; +extern rtk_regField_t MACSEC_RXLINE_CFG1_PORT6_FIELDS[]; +extern rtk_regField_t UNUSED_0184_PORT6_FIELDS[]; +extern rtk_regField_t UNUSED_0188_PORT6_FIELDS[]; +extern rtk_regField_t UNUSED_018C_PORT6_FIELDS[]; +extern rtk_regField_t UNUSED_0190_PORT6_FIELDS[]; +extern rtk_regField_t UNUSED_0194_PORT6_FIELDS[]; +extern rtk_regField_t UNUSED_0198_PORT6_FIELDS[]; +extern rtk_regField_t UNUSED_019C_PORT6_FIELDS[]; +extern rtk_regField_t UNUSED_01A0_PORT6_FIELDS[]; +extern rtk_regField_t UNUSED_01A4_PORT6_FIELDS[]; +extern rtk_regField_t UNUSED_01A8_PORT6_FIELDS[]; +extern rtk_regField_t UNUSED_01AC_PORT6_FIELDS[]; +extern rtk_regField_t UNUSED_01B0_PORT6_FIELDS[]; +extern rtk_regField_t UNUSED_01B4_PORT6_FIELDS[]; +extern rtk_regField_t UNUSED_01B8_PORT6_FIELDS[]; +extern rtk_regField_t UNUSED_01BC_PORT6_FIELDS[]; +extern rtk_regField_t MACSEC_RXSYS_CFG1_PORT6_FIELDS[]; +extern rtk_regField_t MACSEC_RXSYS_CFG3_PORT6_FIELDS[]; +extern rtk_regField_t MACSEC_RXSYS_OUTERVLAN2_PORT6_FIELDS[]; +extern rtk_regField_t MACSEC_RXSYS_OUTERVLAN4_PORT6_FIELDS[]; +extern rtk_regField_t MACSEC_RXSYS_INNERVLAN2_PORT6_FIELDS[]; +extern rtk_regField_t MACSEC_RXSYS_INNERVLAN4_PORT6_FIELDS[]; +extern rtk_regField_t MACSEC_RXSYS_INNERVLAN6_PORT6_FIELDS[]; +extern rtk_regField_t MACSEC_RXSYS_CFG4_PORT6_FIELDS[]; +extern rtk_regField_t MACSEC_RXSYS_CFG6_PORT6_FIELDS[]; +extern rtk_regField_t MACSEC_REG_GLB_SET1_PORT7_FIELDS[]; +extern rtk_regField_t MACSEC_REG_GLB_IMR_PORT7_FIELDS[]; +extern rtk_regField_t MACSEC_REG_GLB_ISR_PORT7_FIELDS[]; +extern rtk_regField_t UNUSED_000C_PORT7_FIELDS[]; +extern rtk_regField_t MACSEC_PM_CTRL_PORT7_FIELDS[]; +extern rtk_regField_t MACSEC_REG_GLB_MASK_PORT7_FIELDS[]; +extern rtk_regField_t MACSEC_REG_GLB_SET4_PORT7_FIELDS[]; +extern rtk_regField_t MACSEC_REG_IP_PROBE_PORT7_FIELDS[]; +extern rtk_regField_t UNUSED_0020_PORT7_FIELDS[]; +extern rtk_regField_t UNUSED_0024_PORT7_FIELDS[]; +extern rtk_regField_t MACSEC_MBIST_SA_CTRL_PORT7_FIELDS[]; +extern rtk_regField_t MACSEC_MBIST_STAT_CTRL_PORT7_FIELDS[]; +extern rtk_regField_t MACSEC_MBIST_SA_AE_TEST_PORT7_FIELDS[]; +extern rtk_regField_t MACSEC_MBIST_STAT_AE_TEST_PORT7_FIELDS[]; +extern rtk_regField_t MACSEC_MBIST_SA_FAIL_PORT7_FIELDS[]; +extern rtk_regField_t MACSEC_XGLBK_FIFO_DBG_PORT7_FIELDS[]; +extern rtk_regField_t MACSEC_REG_RWDH_AE_PORT7_FIELDS[]; +extern rtk_regField_t MACSEC_REG_ADDR_AE_PORT7_FIELDS[]; +extern rtk_regField_t MACSEC_REG_CMD_AE_PORT7_FIELDS[]; +extern rtk_regField_t MACSEC_REG_RWDL_AI_PORT7_FIELDS[]; +extern rtk_regField_t MACSEC_REG_ADDR_AI_PORT7_FIELDS[]; +extern rtk_regField_t MACSEC_REG_RWD_PTP_PORT7_FIELDS[]; +extern rtk_regField_t MACSEC_REG_CMD_PTP_PORT7_FIELDS[]; +extern rtk_regField_t UNUSED_005C_PORT7_FIELDS[]; +extern rtk_regField_t UNUSED_0060_PORT7_FIELDS[]; +extern rtk_regField_t UNUSED_0064_PORT7_FIELDS[]; +extern rtk_regField_t UNUSED_0068_PORT7_FIELDS[]; +extern rtk_regField_t UNUSED_006C_PORT7_FIELDS[]; +extern rtk_regField_t UNUSED_0070_PORT7_FIELDS[]; +extern rtk_regField_t UNUSED_0074_PORT7_FIELDS[]; +extern rtk_regField_t RESERVED_0078_PORT7_FIELDS[]; +extern rtk_regField_t RESERVED_007C_PORT7_FIELDS[]; +extern rtk_regField_t MACSEC_TXSYSCRCERR_CNT_PORT7_FIELDS[]; +extern rtk_regField_t MACSEC_TXSYSPKTERR_CNT_PORT7_FIELDS[]; +extern rtk_regField_t MACSEC_TXSYSOK_CNT_0_PORT7_FIELDS[]; +extern rtk_regField_t MACSEC_TXSYSOK_CNT_2_PORT7_FIELDS[]; +extern rtk_regField_t MACSEC_TXSYSGERR_CNT_PORT7_FIELDS[]; +extern rtk_regField_t MACSEC_TXSYSGLPIERR_CNT_PORT7_FIELDS[]; +extern rtk_regField_t MACSEC_TXSYS_DBG_PORT7_FIELDS[]; +extern rtk_regField_t MACSEC_TX_RX_CNT_INCR_PORT7_FIELDS[]; +extern rtk_regField_t MACSEC_TXLINECRCERR_CNT_PORT7_FIELDS[]; +extern rtk_regField_t MACSEC_TXLINEPKTERR_CNT_PORT7_FIELDS[]; +extern rtk_regField_t MACSEC_TXLINEOK_CNT_0_PORT7_FIELDS[]; +extern rtk_regField_t MACSEC_TXLINEOK_CNT_2_PORT7_FIELDS[]; +extern rtk_regField_t MACSEC_TXLINEDROP_CNT_PORT7_FIELDS[]; +extern rtk_regField_t MACSEC_TXLINESRT_CNT_PORT7_FIELDS[]; +extern rtk_regField_t MACSEC_TXLINEGERR_CNT_PORT7_FIELDS[]; +extern rtk_regField_t MACSEC_TXLINE_DBG_PORT7_FIELDS[]; +extern rtk_regField_t MACSEC_RXLINECRCERR_CNT_PORT7_FIELDS[]; +extern rtk_regField_t MACSEC_RXLINEPKTERR_CNT_PORT7_FIELDS[]; +extern rtk_regField_t MACSEC_RXLINEOK_CNT_0_PORT7_FIELDS[]; +extern rtk_regField_t MACSEC_RXLINEOK_CNT_2_PORT7_FIELDS[]; +extern rtk_regField_t MACSEC_RXLINESRT_CNT_PORT7_FIELDS[]; +extern rtk_regField_t MACSEC_RXLINEGERR_CNT_PORT7_FIELDS[]; +extern rtk_regField_t MACSEC_RXLINEGLPIERR_CNT_PORT7_FIELDS[]; +extern rtk_regField_t MACSEC_RXLINE_DBG_PORT7_FIELDS[]; +extern rtk_regField_t MACSEC_RXSYSCRCERR_CNT_PORT7_FIELDS[]; +extern rtk_regField_t MACSEC_RXSYSPKTERR_CNT_PORT7_FIELDS[]; +extern rtk_regField_t MACSEC_RXSYSOK_CNT_0_PORT7_FIELDS[]; +extern rtk_regField_t MACSEC_RXSYSOK_CNT_2_PORT7_FIELDS[]; +extern rtk_regField_t MACSEC_RXSYSDROP_CNT_PORT7_FIELDS[]; +extern rtk_regField_t MACSEC_RXSYSSRT_CNT_PORT7_FIELDS[]; +extern rtk_regField_t MACSEC_RXSYSGERR_CNT_PORT7_FIELDS[]; +extern rtk_regField_t MACSEC_RXSYS_DBG_PORT7_FIELDS[]; +extern rtk_regField_t MACSEC_TXSYS_CFG1_PORT7_FIELDS[]; +extern rtk_regField_t MACSEC_TXSYS_PTPCFG_PORT7_FIELDS[]; +extern rtk_regField_t MACSEC_TXSYS_OUTERVLAN2_PORT7_FIELDS[]; +extern rtk_regField_t MACSEC_TXSYS_OUTERVLAN4_PORT7_FIELDS[]; +extern rtk_regField_t MACSEC_TXSYS_INNERVLAN2_PORT7_FIELDS[]; +extern rtk_regField_t MACSEC_TXSYS_INNERVLAN4_PORT7_FIELDS[]; +extern rtk_regField_t MACSEC_TXSYS_INNERVLAN6_PORT7_FIELDS[]; +extern rtk_regField_t UNUSED_011C_PORT7_FIELDS[]; +extern rtk_regField_t UNUSED_0120_PORT7_FIELDS[]; +extern rtk_regField_t UNUSED_0124_PORT7_FIELDS[]; +extern rtk_regField_t UNUSED_0128_PORT7_FIELDS[]; +extern rtk_regField_t UNUSED_012C_PORT7_FIELDS[]; +extern rtk_regField_t UNUSED_0130_PORT7_FIELDS[]; +extern rtk_regField_t UNUSED_0134_PORT7_FIELDS[]; +extern rtk_regField_t UNUSED_0138_PORT7_FIELDS[]; +extern rtk_regField_t UNUSED_013C_PORT7_FIELDS[]; +extern rtk_regField_t MACSEC_TXLINE_CFG1_PORT7_FIELDS[]; +extern rtk_regField_t MACSEC_TXLINE_CFG3_PORT7_FIELDS[]; +extern rtk_regField_t MACSEC_TXLINE_CFG5_PORT7_FIELDS[]; +extern rtk_regField_t UNUSED_014C_PORT7_FIELDS[]; +extern rtk_regField_t UNUSED_0150_PORT7_FIELDS[]; +extern rtk_regField_t UNUSED_0154_PORT7_FIELDS[]; +extern rtk_regField_t UNUSED_0158_PORT7_FIELDS[]; +extern rtk_regField_t UNUSED_015C_PORT7_FIELDS[]; +extern rtk_regField_t UNUSED_0160_PORT7_FIELDS[]; +extern rtk_regField_t UNUSED_0164_PORT7_FIELDS[]; +extern rtk_regField_t UNUSED_0168_PORT7_FIELDS[]; +extern rtk_regField_t UNUSED_016C_PORT7_FIELDS[]; +extern rtk_regField_t UNUSED_0170_PORT7_FIELDS[]; +extern rtk_regField_t UNUSED_0174_PORT7_FIELDS[]; +extern rtk_regField_t UNUSED_0178_PORT7_FIELDS[]; +extern rtk_regField_t UNUSED_017C_PORT7_FIELDS[]; +extern rtk_regField_t MACSEC_RXLINE_CFG1_PORT7_FIELDS[]; +extern rtk_regField_t UNUSED_0184_PORT7_FIELDS[]; +extern rtk_regField_t UNUSED_0188_PORT7_FIELDS[]; +extern rtk_regField_t UNUSED_018C_PORT7_FIELDS[]; +extern rtk_regField_t UNUSED_0190_PORT7_FIELDS[]; +extern rtk_regField_t UNUSED_0194_PORT7_FIELDS[]; +extern rtk_regField_t UNUSED_0198_PORT7_FIELDS[]; +extern rtk_regField_t UNUSED_019C_PORT7_FIELDS[]; +extern rtk_regField_t UNUSED_01A0_PORT7_FIELDS[]; +extern rtk_regField_t UNUSED_01A4_PORT7_FIELDS[]; +extern rtk_regField_t UNUSED_01A8_PORT7_FIELDS[]; +extern rtk_regField_t UNUSED_01AC_PORT7_FIELDS[]; +extern rtk_regField_t UNUSED_01B0_PORT7_FIELDS[]; +extern rtk_regField_t UNUSED_01B4_PORT7_FIELDS[]; +extern rtk_regField_t UNUSED_01B8_PORT7_FIELDS[]; +extern rtk_regField_t UNUSED_01BC_PORT7_FIELDS[]; +extern rtk_regField_t MACSEC_RXSYS_CFG1_PORT7_FIELDS[]; +extern rtk_regField_t MACSEC_RXSYS_CFG3_PORT7_FIELDS[]; +extern rtk_regField_t MACSEC_RXSYS_OUTERVLAN2_PORT7_FIELDS[]; +extern rtk_regField_t MACSEC_RXSYS_OUTERVLAN4_PORT7_FIELDS[]; +extern rtk_regField_t MACSEC_RXSYS_INNERVLAN2_PORT7_FIELDS[]; +extern rtk_regField_t MACSEC_RXSYS_INNERVLAN4_PORT7_FIELDS[]; +extern rtk_regField_t MACSEC_RXSYS_INNERVLAN6_PORT7_FIELDS[]; +extern rtk_regField_t MACSEC_RXSYS_CFG4_PORT7_FIELDS[]; +extern rtk_regField_t MACSEC_RXSYS_CFG6_PORT7_FIELDS[]; + +/* Module: Power Saving */ +extern rtk_regField_t GATING_CLOCK0_FIELDS[]; +extern rtk_regField_t GATING_CLOCK1_FIELDS[]; +extern rtk_regField_t EEE_TX_Q_CTRL_FIELDS[]; +extern rtk_regField_t EEE_TX_MINIFG_CTRL0_FIELDS[]; +extern rtk_regField_t EEE_TX_MINIFG_CTRL1_FIELDS[]; +extern rtk_regField_t EEE_TX_MINIFG_CTRL2_FIELDS[]; +extern rtk_regField_t EEE_TX_MINIFG_CTRL3_FIELDS[]; +extern rtk_regField_t EEE_TX_MINIFG_CTRL4_FIELDS[]; +extern rtk_regField_t EEE_TX_CTRL_FIELDS[]; +extern rtk_regField_t EEE_TX_TIMER_100M_CTRL_FIELDS[]; +extern rtk_regField_t EEE_TX_TIMER_GELITE_CTRL_FIELDS[]; +extern rtk_regField_t EEE_TX_TIMER_GIGA_CTRL_FIELDS[]; +extern rtk_regField_t EEE_TX_TIMER_2P5GLITE_CTRL_FIELDS[]; +extern rtk_regField_t EEE_TX_TIMER_2P5G_CTRL_FIELDS[]; +extern rtk_regField_t EEE_TX_TIMER_5GLITE_CTRL_FIELDS[]; +extern rtk_regField_t EEE_TX_TIMER_5G_CTRL_FIELDS[]; +extern rtk_regField_t EEE_TX_TIMER_10GLITE_CTRL_FIELDS[]; +extern rtk_regField_t EEE_TX_TIMER_10G_CTRL_FIELDS[]; +extern rtk_regField_t EEE_CTRL_FIELDS[]; +extern rtk_regField_t EEE_RX_GELITE_CTRL_FIELDS[]; +extern rtk_regField_t EEE_RX_GE_CTRL_FIELDS[]; +extern rtk_regField_t LPI_OPTION_FIELDS[]; + +/* Module: RA */ +extern rtk_regField_t RA_FIFO_FUL_THR0_FIELDS[]; +extern rtk_regField_t RA_FIFO_EMPTY_THR0_FIELDS[]; +extern rtk_regField_t RA_TX_STATUS0_FIELDS[]; +extern rtk_regField_t RA_RX_STATUS0_FIELDS[]; +extern rtk_regField_t RA_HSG_IFG0_FIELDS[]; +extern rtk_regField_t RA_MACSEC_ETH0_FIELDS[]; +extern rtk_regField_t RA_MACSEC_VLAN0_FIELDS[]; +extern rtk_regField_t RA_MACSEC_IFG_CTRL0_FIELDS[]; +extern rtk_regField_t RA_PAUSE_CTRL0_FIELDS[]; +extern rtk_regField_t RA_GLB_CTRL0_FIELDS[]; +extern rtk_regField_t RA_PADDING_CTRL0_FIELDS[]; +extern rtk_regField_t RA_SLOT_TIME0_FIELDS[]; +extern rtk_regField_t RA_SOFT_RST0_FIELDS[]; +extern rtk_regField_t RA_FIFO_FUL_THR1_FIELDS[]; +extern rtk_regField_t RA_FIFO_EMPTY_THR1_FIELDS[]; +extern rtk_regField_t RA_TX_STATUS1_FIELDS[]; +extern rtk_regField_t RA_RX_STATUS1_FIELDS[]; +extern rtk_regField_t RA_HSG_IFG1_FIELDS[]; +extern rtk_regField_t RA_MACSEC_ETH1_FIELDS[]; +extern rtk_regField_t RA_MACSEC_VLAN1_FIELDS[]; +extern rtk_regField_t RA_MACSEC_IFG_CTRL1_FIELDS[]; +extern rtk_regField_t RA_PAUSE_CTRL1_FIELDS[]; +extern rtk_regField_t RA_GLB_CTRL1_FIELDS[]; +extern rtk_regField_t RA_PADDING_CTRL1_FIELDS[]; +extern rtk_regField_t RA_SLOT_TIME1_FIELDS[]; +extern rtk_regField_t RA_SOFT_RST1_FIELDS[]; +extern rtk_regField_t RA_FIFO_FUL_THR2_FIELDS[]; +extern rtk_regField_t RA_FIFO_EMPTY_THR2_FIELDS[]; +extern rtk_regField_t RA_TX_STATUS2_FIELDS[]; +extern rtk_regField_t RA_RX_STATUS2_FIELDS[]; +extern rtk_regField_t RA_HSG_IFG2_FIELDS[]; +extern rtk_regField_t RA_MACSEC_ETH2_FIELDS[]; +extern rtk_regField_t RA_MACSEC_VLAN2_FIELDS[]; +extern rtk_regField_t RA_MACSEC_IFG_CTRL2_FIELDS[]; +extern rtk_regField_t RA_PAUSE_CTRL2_FIELDS[]; +extern rtk_regField_t RA_GLB_CTRL2_FIELDS[]; +extern rtk_regField_t RA_PADDING_CTRL2_FIELDS[]; +extern rtk_regField_t RA_SLOT_TIME2_FIELDS[]; +extern rtk_regField_t RA_SOFT_RST2_FIELDS[]; +extern rtk_regField_t RA_FIFO_FUL_THR3_FIELDS[]; +extern rtk_regField_t RA_FIFO_EMPTY_THR3_FIELDS[]; +extern rtk_regField_t RA_TX_STATUS3_FIELDS[]; +extern rtk_regField_t RA_RX_STATUS3_FIELDS[]; +extern rtk_regField_t RA_HSG_IFG3_FIELDS[]; +extern rtk_regField_t RA_MACSEC_ETH3_FIELDS[]; +extern rtk_regField_t RA_MACSEC_VLAN3_FIELDS[]; +extern rtk_regField_t RA_MACSEC_IFG_CTRL3_FIELDS[]; +extern rtk_regField_t RA_PAUSE_CTRL3_FIELDS[]; +extern rtk_regField_t RA_GLB_CTRL3_FIELDS[]; +extern rtk_regField_t RA_PADDING_CTRL3_FIELDS[]; +extern rtk_regField_t RA_SLOT_TIME3_FIELDS[]; +extern rtk_regField_t RA_SOFT_RST3_FIELDS[]; + +/* Module: NIC */ +extern rtk_regField_t NIC_BUFFSIZE_CTRL_FIELDS[]; +extern rtk_regField_t NIC_RXBUFF_CTRL_FIELDS[]; +extern rtk_regField_t NIC_RXCMD_FIELDS[]; +extern rtk_regField_t NIC_TXCMD_FIELDS[]; +extern rtk_regField_t NIC_INT_STS_FIELDS[]; +extern rtk_regField_t NIC_INT_MSK_FIELDS[]; +extern rtk_regField_t NIC_RX_CTRL_FIELDS[]; +extern rtk_regField_t NIC_TX_CTRL_FIELDS[]; +extern rtk_regField_t NIC_MC_HASH_TBL_FIELDS[]; +extern rtk_regField_t NIC_UC_HASH_TBL_FIELDS[]; +extern rtk_regField_t NIC_RX_BUFF_DATA_FIELDS[]; +extern rtk_regField_t NIC_RX_CURR_PKT_FIELDS[]; +extern rtk_regField_t CPU_RX_CURR_PKT_FIELDS[]; +extern rtk_regField_t NIC_TX_BUFF_AVAIL_FIELDS[]; +extern rtk_regField_t NIC_TX_CURR_PKT_FIELDS[]; +extern rtk_regField_t NIC_TX_CURR_UNIT_FIELDS[]; +extern rtk_regField_t NIC_TX_PKT_INFO_FIELDS[]; +extern rtk_regField_t CPU_TX_CURR_PKT_FIELDS[]; +extern rtk_regField_t DMY_REG0_NIC_FIELDS[]; +extern rtk_regField_t DMY_REG1_NIC_FIELDS[]; + +/* Module: Cpu Tag */ +extern rtk_regField_t CPU_TAG_TPID_CTRL_FIELDS[]; +extern rtk_regField_t CPU_TAG_CTRL_FIELDS[]; +extern rtk_regField_t EXT_CPU_CTRL_FIELDS[]; +extern rtk_regField_t CPU_TAG_AWARE_CTRL_FIELDS[]; + +/* Module: Table Access */ +extern rtk_regField_t ITA_CTRL0_FIELDS[]; +extern rtk_regField_t ITA_L2_CTRL_FIELDS[]; +extern rtk_regField_t ITA_HSAB_CTRL_FIELDS[]; +extern rtk_regField_t ITA_WRITE_DATA0_FIELDS[]; +extern rtk_regField_t ITA_READ_DATA0_FIELDS[]; +extern rtk_regField_t TEST_MODE_ALE_HSA_MULTI_CTRL_FIELDS[]; +extern rtk_regField_t TBL_ACCESS_HSA_CTRL_FIELDS[]; +extern rtk_regField_t TBL_ACCESS_HSA_DATA_FIELDS[]; + +/* Module: 8051 */ +extern rtk_regField_t DW8051_CFG_FIELDS[]; +extern rtk_regField_t DW8051_IROM_FIELDS[]; + +/* Module: 802.1Q VLAN */ +extern rtk_regField_t VLAN_PORT_AFT_FIELDS[]; +extern rtk_regField_t VLAN_CTRL_FIELDS[]; +extern rtk_regField_t VLAN_PORT_IGR_FLTR_FIELDS[]; +extern rtk_regField_t VLAN_PORT_PB_VLAN_FIELDS[]; +extern rtk_regField_t VLAN_PORT_EGR_TRANS_FIELDS[]; +extern rtk_regField_t VLAN_PORT_EGR_KEEP_FIELDS[]; +extern rtk_regField_t VLAN_PORT_EGR_TAG_FIELDS[]; +extern rtk_regField_t VLAN_L2_LRN_DIS_FIELDS[]; +extern rtk_regField_t PORT_BASED_FID_EN_FIELDS[]; +extern rtk_regField_t PORT_BASED_FID_FIELDS[]; +extern rtk_regField_t VLAN_TAG_PRI_CFG_FIELDS[]; + +/* Module: 802.1D SVLAN */ +extern rtk_regField_t VS_GLB_CTRL_FIELDS[]; +extern rtk_regField_t VS_UPLINK_PORT_FIELDS[]; +extern rtk_regField_t VS_CTRL_FIELDS[]; +extern rtk_regField_t VS_UNTAG_SVID_FIELDS[]; +extern rtk_regField_t VS_PORT_DFLT_SVID_FIELDS[]; +extern rtk_regField_t SVLAN_TRAP_CTRL_FIELDS[]; + +/* Module: C2S Table */ +extern rtk_regField_t VLAN_C2S_ENTRY_FIELDS[]; + +/* Module: RMA */ +extern rtk_regField_t RMA_OP_CTRL_00_FIELDS[]; +extern rtk_regField_t RMA_OP_CTRL_01_FIELDS[]; +extern rtk_regField_t RMA_OP_CTRL_02_FIELDS[]; +extern rtk_regField_t RMA_OP_CTRL_03_FIELDS[]; +extern rtk_regField_t RMA_OP_CTRL_04_FIELDS[]; +extern rtk_regField_t RMA_OP_CTRL_08_FIELDS[]; +extern rtk_regField_t RMA_OP_CTRL_0D_FIELDS[]; +extern rtk_regField_t RMA_OP_CTRL_0E_FIELDS[]; +extern rtk_regField_t RMA_OP_CTRL_10_FIELDS[]; +extern rtk_regField_t RMA_OP_CTRL_11_FIELDS[]; +extern rtk_regField_t RMA_OP_CTRL_12_FIELDS[]; +extern rtk_regField_t RMA_OP_CTRL_13_FIELDS[]; +extern rtk_regField_t RMA_OP_CTRL_18_FIELDS[]; +extern rtk_regField_t RMA_OP_CTRL_1A_FIELDS[]; +extern rtk_regField_t RMA_OP_CTRL_20_FIELDS[]; +extern rtk_regField_t RMA_OP_CTRL_21_FIELDS[]; +extern rtk_regField_t RMA_OP_CTRL_22_FIELDS[]; +extern rtk_regField_t RMA_OP_CTRL_CDP_FIELDS[]; +extern rtk_regField_t RMA_OP_CTRL_CSSTP_FIELDS[]; +extern rtk_regField_t RMA_OP_CTRL_LLDP_FIELDS[]; +extern rtk_regField_t RMA_CFG_FIELDS[]; +extern rtk_regField_t RMA_PORT_PTP_ETH2_CTRL_FIELDS[]; +extern rtk_regField_t RMA_PORT_PTP_UDP_CTRL_FIELDS[]; +extern rtk_regField_t RMA_PORT_PTP_DELAY_CARE_CTRL_FIELDS[]; +extern rtk_regField_t RMA_PORT_PTP_PDELAY_CARE_CTRL_FIELDS[]; +extern rtk_regField_t RMA_PORT_PTP_ASM_CARE_CTRL_FIELDS[]; +extern rtk_regField_t RMA_PTP_TRAP_CTRL_FIELDS[]; + +/* Module: Link Aggregation */ +extern rtk_regField_t TRK_MBR_CTRL_FIELDS[]; +extern rtk_regField_t TRK_HASH_CTRL_FIELDS[]; +extern rtk_regField_t TRK_CTRL_FIELDS[]; +extern rtk_regField_t TRK_FLOW_CTRL_FIELDS[]; +extern rtk_regField_t TRK_QUEUE_EMPTY_FIELDS[]; + +/* Module: Spanning Tree */ +extern rtk_regField_t MSPT_STATE_FIELDS[]; + +/* Module: MAC Forwarding Control */ +extern rtk_regField_t L2_CTRL_FIELDS[]; +extern rtk_regField_t L2_AGE_CTRL_FIELDS[]; +extern rtk_regField_t L2_PORT_AGE_CTRL_FIELDS[]; +extern rtk_regField_t L2_NEWSA_CTRL_FIELDS[]; +extern rtk_regField_t L2_UNMATCH_SA_CTRL_FIELDS[]; +extern rtk_regField_t L2_SA_MOVING_FORBID_FIELDS[]; +extern rtk_regField_t L2_UNKN_UC_FLD_PMSK_FIELDS[]; +extern rtk_regField_t L2_UNKN_MC_FLD_PMSK_FIELDS[]; +extern rtk_regField_t IPV4_UNKN_MC_FLD_PMSK_FIELDS[]; +extern rtk_regField_t IPV6_UNKN_MC_FLD_PMSK_FIELDS[]; +extern rtk_regField_t L2_BC_FLD_PMSK_FIELDS[]; +extern rtk_regField_t L2_PORT_UC_LM_ACT_FIELDS[]; +extern rtk_regField_t L2_PORT_MC_LM_ACT_FIELDS[]; +extern rtk_regField_t IPV4_PORT_MC_LM_ACT_FIELDS[]; +extern rtk_regField_t IPV6_PORT_MC_LM_ACT_FIELDS[]; +extern rtk_regField_t L2_LRN_CONSTRT_CTRL_FIELDS[]; +extern rtk_regField_t L2_LRN_CONSTRT_CNT_FIELDS[]; +extern rtk_regField_t L2_LRN_CONSTRT_ACT_FIELDS[]; +extern rtk_regField_t L2_LRN_PORT_CONSTRT_CTRL_FIELDS[]; +extern rtk_regField_t L2_LRN_PORT_CONSTRT_CNT_FIELDS[]; +extern rtk_regField_t L2_LRN_PORT_CONSTRT_ACT_FIELDS[]; +extern rtk_regField_t L2_TBL_FLUSH_CMD_FIELDS[]; +extern rtk_regField_t L2_TBL_FLUSH_ALL_FIELDS[]; +extern rtk_regField_t L2_TBL_FLUSH_MODE_FIELDS[]; +extern rtk_regField_t L2_TBL_FLUSH_XID_FIELDS[]; +extern rtk_regField_t SOURCE_PORT_PERMIT_FIELDS[]; +extern rtk_regField_t IPMC_GROUP_DIP_FIELDS[]; +extern rtk_regField_t IPMC_GROUP_PMSK_FIELDS[]; +extern rtk_regField_t IPMC_GROUP_VALID_FIELDS[]; +extern rtk_regField_t IPMUL_NO_VLAN_EGRESS_FIELDS[]; +extern rtk_regField_t IPMUL_NO_PORTISO_FIELDS[]; +extern rtk_regField_t L2_FORCE_MODE_FIELDS[]; +extern rtk_regField_t L2_FORCE_DPM_PORT_FIELDS[]; + +/* Module: IGMP & MLD */ +extern rtk_regField_t IGMP_CTRL_FIELDS[]; +extern rtk_regField_t IGMP_QUERY_INTVL_FIELDS[]; +extern rtk_regField_t IGMP_DYN_ROUTER_INFO_FIELDS[]; +extern rtk_regField_t IGMP_ROUTER_PORT_CRTL_FIELDS[]; +extern rtk_regField_t IGMP_PORT_CTRL_FIELDS[]; +extern rtk_regField_t PORT_CURR_GROUP_FIELDS[]; +extern rtk_regField_t IGMP_TBL_USAGE_FIELDS[]; +extern rtk_regField_t IGMP_TRAP_CTRL_FIELDS[]; + +/* Module: Port Isolation */ +extern rtk_regField_t PORT_ISO_PORT_PMSK_FIELDS[]; + +/* Module: Port Mirror */ +extern rtk_regField_t MIR_CTRL_FIELDS[]; +extern rtk_regField_t MIR_SET_CTRL_FIELDS[]; +extern rtk_regField_t MIR_SET_PMSK_FIELDS[]; +extern rtk_regField_t MIR_SAMPLE_CRTL_FIELDS[]; +extern rtk_regField_t MIR_MATCHED_FIELDS[]; + +/* Module: RSPAN */ +extern rtk_regField_t MIR_RSPAN_CTRL_FIELDS[]; +extern rtk_regField_t MIR_RSPAN_TAG_CTRL_FIELDS[]; +extern rtk_regField_t MIR_RSPAN_TX_PORT_CTRL_FIELDS[]; +extern rtk_regField_t MIR_RSPAN_RX_ACT_FIELDS[]; + +/* Module: ACL Module */ +extern rtk_regField_t ACL_CTRL_FIELDS[]; +extern rtk_regField_t ACL_GPIO_CTRL_FIELDS[]; +extern rtk_regField_t ACL_PORT_EN_FIELDS[]; +extern rtk_regField_t ACL_PORT_UNMATCH_PERMIT_FIELDS[]; +extern rtk_regField_t ACL_TEMPLATE_CTRL_FIELDS[]; +extern rtk_regField_t ACL_ACT_CTRL_FIELDS[]; +extern rtk_regField_t ACL_HIT_INDICATOR_FIELDS[]; + +/* Module: Range Check (port/vlan/ip/L4port) */ +extern rtk_regField_t RNG_CHK_VID_FIELDS[]; +extern rtk_regField_t RNG_CHK_IP_FIELDS[]; +extern rtk_regField_t RNG_CHK_PORT_FIELDS[]; + +/* Module: ACL LOG COUNTER */ +extern rtk_regField_t ACL_LOG_CNTR_RST_FIELDS[]; +extern rtk_regField_t ACL_CNTR_RST_VAL_FIELDS[]; +extern rtk_regField_t ACL_LOG_CNTR_TYPE_FIELDS[]; +extern rtk_regField_t ACL_LOG_CNTR_MODE_FIELDS[]; +extern rtk_regField_t ACL_LOG_CNTR_DATA_FIELDS[]; +extern rtk_regField_t ACL_LATCH_TRIGGER_FIELDS[]; +extern rtk_regField_t ACL_LATCH_ADDR_FIELDS[]; +extern rtk_regField_t ACL_LATCH_VAL_L_FIELDS[]; +extern rtk_regField_t ACL_LATCH_VAL_H_FIELDS[]; + +/* Module: PTP (Precision Time Protocol) */ +extern rtk_regField_t PTP_TIME_TOD_DELAY_FIELDS[]; +extern rtk_regField_t PTP_TIME_OP_DURATION_FIELDS[]; +extern rtk_regField_t PTP_DUMMY_RG02_FIELDS[]; +extern rtk_regField_t PTP_DUMMY_RG03_FIELDS[]; +extern rtk_regField_t PTP_OTAG_CONFIG0_FIELDS[]; +extern rtk_regField_t PTP_OTAG_CONFIG1_FIELDS[]; +extern rtk_regField_t PTP_OTAG_CONFIG2_FIELDS[]; +extern rtk_regField_t PTP_OTAG_CONFIG3_FIELDS[]; +extern rtk_regField_t PTP_ITAG_CONFIG0_FIELDS[]; +extern rtk_regField_t PTP_DUMMY_RG09_FIELDS[]; +extern rtk_regField_t PTP_DUMMY_RG10_FIELDS[]; +extern rtk_regField_t PTP_APPLY_FREQ_FIELDS[]; +extern rtk_regField_t PTP_TIME_FREQ0_FIELDS[]; +extern rtk_regField_t PTP_TIME_FREQ1_FIELDS[]; +extern rtk_regField_t PTP_CUR_TIME_FREQ0_FIELDS[]; +extern rtk_regField_t PTP_CUR_TIME_FREQ1_FIELDS[]; +extern rtk_regField_t PTP_TIME_NSEC0_FIELDS[]; +extern rtk_regField_t PTP_TIME_NSEC1_FIELDS[]; +extern rtk_regField_t PTP_TIME_SEC0_FIELDS[]; +extern rtk_regField_t PTP_TIME_SEC1_FIELDS[]; +extern rtk_regField_t PTP_TIME_SEC2_FIELDS[]; +extern rtk_regField_t PTP_TIME_CRTL_FIELDS[]; +extern rtk_regField_t PTP_TIME_NSEC_RD0_FIELDS[]; +extern rtk_regField_t PTP_TIME_NSEC_RD1_FIELDS[]; +extern rtk_regField_t PTP_TIME_SEC_RD0_FIELDS[]; +extern rtk_regField_t PTP_TIME_SEC_RD1_FIELDS[]; +extern rtk_regField_t PTP_TIME_SEC_RD2_FIELDS[]; +extern rtk_regField_t PTP_CLKOUT_NSEC0_FIELDS[]; +extern rtk_regField_t PTP_CLKOUT_NSEC1_FIELDS[]; +extern rtk_regField_t PTP_CLKOUT_SEC0_FIELDS[]; +extern rtk_regField_t PTP_CLKOUT_SEC1_FIELDS[]; +extern rtk_regField_t PTP_CLKOUT_SEC2_FIELDS[]; +extern rtk_regField_t PTP_CLKOUT_CTRL_FIELDS[]; +extern rtk_regField_t PTP_CLKOUT_HALF_PERD_NS_L_FIELDS[]; +extern rtk_regField_t PTP_CLKOUT_HALF_PERD_NS_H_FIELDS[]; +extern rtk_regField_t PTP_TIME_OP_CTRL_FIELDS[]; +extern rtk_regField_t PTP_PPS_CTRL_FIELDS[]; +extern rtk_regField_t PTP_TX_TIMESTAMP_RD0_FIELDS[]; +extern rtk_regField_t PTP_TX_TIMESTAMP_RD1_FIELDS[]; +extern rtk_regField_t PTP_TX_TIMESTAMP_RD2_FIELDS[]; +extern rtk_regField_t PTP_TX_TIMESTAMP_RD3_FIELDS[]; +extern rtk_regField_t PTP_MIB_INTR_FIELDS[]; +extern rtk_regField_t PTP_GLOBAL_DBG_FIELDS[]; +extern rtk_regField_t PTP_CLK_SRC_CTRL_FIELDS[]; +extern rtk_regField_t PTP_CLKOUT_HALF_PERD_FS_L_FIELDS[]; +extern rtk_regField_t PTP_CLKOUT_HALF_PERD_FS_H_FIELDS[]; +extern rtk_regField_t PTP_DUMMY_RG46_FIELDS[]; +extern rtk_regField_t PTP_DUMMY_RG47_FIELDS[]; +extern rtk_regField_t PPS_IN_LATCH_TIME_NSEC_L_FIELDS[]; +extern rtk_regField_t PPS_IN_LATCH_TIME_NSEC_H_FIELDS[]; +extern rtk_regField_t PPS_IN_LATCH_TIME_SEC_L_FIELDS[]; +extern rtk_regField_t PPS_IN_LATCH_TIME_SEC_M_FIELDS[]; +extern rtk_regField_t PPS_IN_LATCH_TIME_SEC_H_FIELDS[]; +extern rtk_regField_t PTP_DUMMY_RG53_FIELDS[]; +extern rtk_regField_t PTP_DUMMY_RG54_FIELDS[]; +extern rtk_regField_t PTP_DUMMY_RG55_FIELDS[]; +extern rtk_regField_t PTP_DUMMY_RG56_FIELDS[]; +extern rtk_regField_t PTP_DUMMY_RG57_FIELDS[]; +extern rtk_regField_t PTP_DUMMY_RG58_FIELDS[]; +extern rtk_regField_t PTP_DUMMY_RG59_FIELDS[]; +extern rtk_regField_t PTP_DUMMY_RG60_FIELDS[]; +extern rtk_regField_t PTP_DUMMY_RG61_FIELDS[]; +extern rtk_regField_t PTP_TIME_SPEED_UP_FIELDS[]; +extern rtk_regField_t PTP_VERSION_FIELDS[]; +extern rtk_regField_t P0_PORT_CTRL_FIELDS[]; +extern rtk_regField_t P0_LINK_DELAY_H_FIELDS[]; +extern rtk_regField_t P0_MISC_CTRL_FIELDS[]; +extern rtk_regField_t P0_TX_IMBAL_FIELDS[]; +extern rtk_regField_t P0_RX_IMBAL_FIELDS[]; +extern rtk_regField_t P0_PTP_PORTID_FIELDS[]; +extern rtk_regField_t P0_PTP_DUMMY_RG06_FIELDS[]; +extern rtk_regField_t P0_DBG_PTP_CTRL_FIELDS[]; +extern rtk_regField_t TOD_OUT_DATA_CTRL_FIELDS[]; +extern rtk_regField_t TOD_OUT_CTRL0_FIELDS[]; +extern rtk_regField_t TOD_OUT_CTRL1_FIELDS[]; +extern rtk_regField_t TOD_SARP_GPS_WEEK_FIELDS[]; +extern rtk_regField_t TOD_SARP_GPS_SEC_L_FIELDS[]; +extern rtk_regField_t TOD_SARP_GPS_SEC_H_FIELDS[]; +extern rtk_regField_t TOD_UART_SETTING_FIELDS[]; +extern rtk_regField_t TOD_INTR_FIELDS[]; + +/* Module: Storm Control (B/M/UM/DLF) */ +extern rtk_regField_t RX_STORM_BCAST_CTRL_FIELDS[]; +extern rtk_regField_t RX_STORM_MCAST_CTRL_FIELDS[]; +extern rtk_regField_t RX_STORM_UNUCAST_CTRL_FIELDS[]; +extern rtk_regField_t RX_STORM_UNMCAST_CTRL_FIELDS[]; +extern rtk_regField_t RX_STORM_BCAST_METER_FIELDS[]; +extern rtk_regField_t RX_STORM_MCAST_METER_FIELDS[]; +extern rtk_regField_t RX_STORM_UNUCAST_METER_FIELDS[]; +extern rtk_regField_t RX_STORM_UNMCAST_METER_FIELDS[]; +extern rtk_regField_t CFG_STORM_EXT_FIELDS[]; +extern rtk_regField_t STORM_EXT_MTRIDX_CFG_FIELDS[]; + +/* Module: IngressBW */ +extern rtk_regField_t IGBW_CTRL_FIELDS[]; +extern rtk_regField_t IGBW_LB_CTRL_FIELDS[]; +extern rtk_regField_t IGBW_PORT_CTRL_FIELDS[]; +extern rtk_regField_t IGBW_PORT_BURST_CTRL_FIELDS[]; +extern rtk_regField_t IGBW_PORT_LB_RST_FIELDS[]; +extern rtk_regField_t IGBW_PORT_CNGST_FLAG_FIELDS[]; +extern rtk_regField_t IGBW_PORT_FC_CTRL_FIELDS[]; +extern rtk_regField_t IGBW_PORT_DROP_CTRL_FIELDS[]; + +/* Module: Egress Bandwidth Control */ +extern rtk_regField_t EGBW_ENCAP_CTRL_FIELDS[]; +extern rtk_regField_t EGBW_CTRL_FIELDS[]; +extern rtk_regField_t EGBW_LB_CTRL_FIELDS[]; +extern rtk_regField_t EGBW_PORT_CTRL_FIELDS[]; +extern rtk_regField_t EGBW_PORT_LB_RST_FIELDS[]; +extern rtk_regField_t EGBW_PORT_Q_MAX_LB_CTRL_SET_FIELDS[]; +extern rtk_regField_t EGBW_PORT_Q_MAX_LB_RST_SET_FIELDS[]; +extern rtk_regField_t EGBW_PORT_Q_ASSURED_FIX_BURST_CTRL_SET_FIELDS[]; +extern rtk_regField_t EGBW_PORT_Q_ASSURED_LB_CTRL_SET_FIELDS[]; +extern rtk_regField_t EGBW_PORT_Q_FIX_LB_CTRL_SET_FIELDS[]; +extern rtk_regField_t EGBW_PORT_Q_ASSURED_FIX_LB_RST_SET_FIELDS[]; +extern rtk_regField_t EGBW_RATE_10M_CTRL_FIELDS[]; +extern rtk_regField_t EGBW_RATE_100M_CTRL_FIELDS[]; +extern rtk_regField_t EGBW_RATE_1G_CTRL_FIELDS[]; +extern rtk_regField_t EGBW_RATE_500M_CTRL_FIELDS[]; +extern rtk_regField_t EGBW_RATE_10G_CTRL_FIELDS[]; +extern rtk_regField_t EGBW_RATE_2500M_CTRL_FIELDS[]; +extern rtk_regField_t EGBW_RATE_1250M_CTRL_FIELDS[]; +extern rtk_regField_t EGBW_RATE_5G_CTRL_FIELDS[]; +extern rtk_regField_t DMY_REG0_EGRESS_CTRL_FIELDS[]; + +/* Module: Meter Marker */ +extern rtk_regField_t SHARED_METER_RATE_CTRL_FIELDS[]; +extern rtk_regField_t SHARED_METER_BURST_CTRL_FIELDS[]; +extern rtk_regField_t SHARED_METER_MODE_FIELDS[]; +extern rtk_regField_t SHARED_METER_EXCEED_FIELDS[]; +extern rtk_regField_t SHARED_METER_EXCEED_ICPU_FIELDS[]; +extern rtk_regField_t SHARED_METER_IPG_CTRL_FIELDS[]; +extern rtk_regField_t SHARED_METER_LB_CTRL_FIELDS[]; +extern rtk_regField_t SHARED_METER_LB_PPS_CTRL_FIELDS[]; + +/* Module: FlowControl & Backpressure */ +extern rtk_regField_t FC_CTRL_FIELDS[]; +extern rtk_regField_t FC_PORT_ACT_CTRL_FIELDS[]; +extern rtk_regField_t FC_GLB_SYS_UTIL_THR_FIELDS[]; +extern rtk_regField_t FC_GLB_DROP_THR_FIELDS[]; +extern rtk_regField_t FC_GLB_HI_THR_FIELDS[]; +extern rtk_regField_t FC_GLB_LO_THR_FIELDS[]; +extern rtk_regField_t FC_GLB_FCOFF_HI_THR_FIELDS[]; +extern rtk_regField_t FC_GLB_FCOFF_LO_THR_FIELDS[]; +extern rtk_regField_t FC_JUMBO_HI_THR_FIELDS[]; +extern rtk_regField_t FC_JUMBO_LO_THR_FIELDS[]; +extern rtk_regField_t FC_JUMBO_FCOFF_HI_THR_FIELDS[]; +extern rtk_regField_t FC_JUMBO_FCOFF_LO_THR_FIELDS[]; +extern rtk_regField_t FC_JUMBO_THR_ADJUST_FIELDS[]; +extern rtk_regField_t FC_PORT_HI_THR_FIELDS[]; +extern rtk_regField_t FC_PORT_LO_THR_FIELDS[]; +extern rtk_regField_t FC_PORT_FCOFF_HI_THR_FIELDS[]; +extern rtk_regField_t FC_PORT_FCOFF_LO_THR_FIELDS[]; +extern rtk_regField_t FC_PORT_GUAR_THR_FIELDS[]; +extern rtk_regField_t FC_PORT_THR_SET_SEL_FIELDS[]; +extern rtk_regField_t FC_PORT_EGR_DROP_CTRL_FIELDS[]; +extern rtk_regField_t FC_HOL_PRVNT_CTRL_FIELDS[]; +extern rtk_regField_t FC_PORT_Q_EGR_DROP_CTRL_SET_FIELDS[]; +extern rtk_regField_t FC_PORT_Q_EGR_FORCE_DROP_CTRL_SET_FIELDS[]; +extern rtk_regField_t FC_Q_EGR_DROP_THR_FIELDS[]; +extern rtk_regField_t FC_PORT_EGR_DROP_THR_SET_SEL_FIELDS[]; +extern rtk_regField_t FC_GLB_PAGE_CNT_FIELDS[]; +extern rtk_regField_t FC_PORT_PAGE_CNT_FIELDS[]; +extern rtk_regField_t FC_GLB_PAGE_PEAKCNT_FIELDS[]; +extern rtk_regField_t FC_PORT_CUR_PAGE_CNT_FIELDS[]; +extern rtk_regField_t FC_PORT_PEAK_PAGE_CNT_FIELDS[]; +extern rtk_regField_t FC_PORT_EGR_PAGE_CNT_FIELDS[]; +extern rtk_regField_t FC_PORT_Q_EGR_PAGE_CNT_SET_FIELDS[]; +extern rtk_regField_t FC_PORT_Q_EGR_PKT_CNT_SET_FIELDS[]; +extern rtk_regField_t FC_PORT_PAGE_CNT_ERROR_FIELDS[]; +extern rtk_regField_t PFC_ENABLE_0_FIELDS[]; +extern rtk_regField_t PFC_ENABLE_1_FIELDS[]; +extern rtk_regField_t PFC_CTRL_0_FIELDS[]; +extern rtk_regField_t PFC_ACTDROP_CTRL_FIELDS[]; +extern rtk_regField_t P_PFC_THR_FIELDS[]; +extern rtk_regField_t P_PFCOFF_THR_FIELDS[]; +extern rtk_regField_t PG_HI_THR_FIELDS[]; +extern rtk_regField_t PG_LO_THR_FIELDS[]; +extern rtk_regField_t PG_PFCOFF_HI_THR_FIELDS[]; +extern rtk_regField_t PG_PFCOFF_LO_THR_FIELDS[]; +extern rtk_regField_t PG_GURANTEE_THR_FIELDS[]; +extern rtk_regField_t PFC_CTRL_1_FIELDS[]; +extern rtk_regField_t PFC_CTRL_2_FIELDS[]; +extern rtk_regField_t PG_2_PEV_TABLE_FIELDS[]; +extern rtk_regField_t DPRI_2_PG_TABLE_FIELDS[]; +extern rtk_regField_t PCP_2_PG_TABLE_FIELDS[]; +extern rtk_regField_t PEV_2_TXQ_TABLE_FIELDS[]; +extern rtk_regField_t PFC_PORT_PG_RX_PAGE_CNT_FIELDS[]; + +/* Module: Congestion Avoidance */ +extern rtk_regField_t SC_P_CTRL_FIELDS[]; +extern rtk_regField_t SC_P_EN_FIELDS[]; + +/* Module: Ingress Priority Decision */ +extern rtk_regField_t PORT_PRI_FIELDS[]; +extern rtk_regField_t DOT1Q_PRI_REMAP_FIELDS[]; +extern rtk_regField_t PRI_SEL_REMAP_DSCP_FIELDS[]; +extern rtk_regField_t RSPAN_PRI_REMAP_FIELDS[]; +extern rtk_regField_t PRI_WEIGHT_FIELDS[]; +extern rtk_regField_t PORT_WEIGHT_SEL_FIELDS[]; +extern rtk_regField_t QID_TO_PRI_FIELDS[]; +extern rtk_regField_t INCPU_PRI_REMAP_FIELDS[]; +extern rtk_regField_t EXCPU_PRI_REMAP_FIELDS[]; +extern rtk_regField_t PORT_PRI_DUP_FIELDS[]; + +/* Module: Scheduling & Queue Management */ +extern rtk_regField_t SCHED_PORT_Q_CTRL_SET_FIELDS[]; +extern rtk_regField_t SCHED_PORT_ALGO_CTRL_FIELDS[]; +extern rtk_regField_t CFG_TG_URR_SEL_FIELDS[]; + +/* Module: Remarking */ +extern rtk_regField_t RMK_CTRL_FIELDS[]; +extern rtk_regField_t RMK_PORT_CTRL_FIELDS[]; +extern rtk_regField_t RMK_INTPRI2IPRI_CTRL_FIELDS[]; +extern rtk_regField_t RMK_INTPRI2DSCP_CTRL_FIELDS[]; +extern rtk_regField_t RMK_DSCP2DSCP_CTRL_FIELDS[]; + +/* Module: 802.1X */ +extern rtk_regField_t DOT1X_PORT_EN_FIELDS[]; +extern rtk_regField_t DOT1X_MAC_EN_FIELDS[]; +extern rtk_regField_t DOT1X_PORT_AUTH_FIELDS[]; +extern rtk_regField_t DOT1X_PORT_DIR_FIELDS[]; +extern rtk_regField_t DOT1X_TRAP_PRIORITY_FIELDS[]; +extern rtk_regField_t DOT1X_UNAUTH_ACT_FIELDS[]; +extern rtk_regField_t DOT1X_TRAP_CPU_SEL_FIELDS[]; +extern rtk_regField_t DOT1X_CFG_FIELDS[]; + +/* Module: Attack Prevention */ +extern rtk_regField_t ATK_PRVNT_CTRL_FIELDS[]; +extern rtk_regField_t MIN_TCPHDR_LEN_FIELDS[]; + +/* Module: WOL */ +extern rtk_regField_t WOL_CTRL_FIELDS[]; +extern rtk_regField_t WOL_MAC0_FIELDS[]; +extern rtk_regField_t WOL_MAC1_FIELDS[]; +extern rtk_regField_t PHY_WOL_CTRL_FIELDS[]; +extern rtk_regField_t PHY_WOL_MAC0_FIELDS[]; +extern rtk_regField_t PHY_WOL_MAC1_FIELDS[]; + +/* Module: Parser */ +extern rtk_regField_t PARSER_FIELD_SELTOR_CTRL_FIELDS[]; +extern rtk_regField_t PARSER_CTRL_FIELDS[]; +extern rtk_regField_t PARSER_DROP_REASON_FIELDS[]; + +/* Module: Parser HSB */ +extern rtk_regField_t HSB_DATA0_FIELDS[]; +extern rtk_regField_t HSB_DATA1_FIELDS[]; +extern rtk_regField_t HSB_DATA2_FIELDS[]; +extern rtk_regField_t HSB_DATA3_FIELDS[]; +extern rtk_regField_t HSB_DATA4_FIELDS[]; +extern rtk_regField_t HSB_DATA5_FIELDS[]; +extern rtk_regField_t HSB_DATA6_FIELDS[]; +extern rtk_regField_t HSB_DATA7_FIELDS[]; +extern rtk_regField_t HSB_DATA8_FIELDS[]; +extern rtk_regField_t HSB_DATA9_FIELDS[]; +extern rtk_regField_t HSB_DATA10_FIELDS[]; +extern rtk_regField_t HSB_DATA11_FIELDS[]; +extern rtk_regField_t HSB_DATA12_FIELDS[]; +extern rtk_regField_t HSB_DATA13_FIELDS[]; +extern rtk_regField_t HSB_DATA14_FIELDS[]; +extern rtk_regField_t HSB_DATA15_FIELDS[]; +extern rtk_regField_t HSB_DATA16_FIELDS[]; +extern rtk_regField_t HSB_DATA17_FIELDS[]; +extern rtk_regField_t HSB_DATA18_FIELDS[]; +extern rtk_regField_t HSB_DATA19_FIELDS[]; +extern rtk_regField_t HSB_CTRL_FIELDS[]; + +/* Module: RLDP & RLPP */ +extern rtk_regField_t RLDP_RLPP_CTRL_FIELDS[]; +extern rtk_regField_t RETRY_CTRL_FIELDS[]; +extern rtk_regField_t PERIOD_CTRL_FIELDS[]; +extern rtk_regField_t RLDP_TX_PMSK_FIELDS[]; +extern rtk_regField_t RAND_NUM0_FIELDS[]; +extern rtk_regField_t RAND_NUM1_FIELDS[]; +extern rtk_regField_t MAGIC_NUM0_FIELDS[]; +extern rtk_regField_t MAGIC_NUM1_FIELDS[]; +extern rtk_regField_t LOOP_STATE_FIELDS[]; +extern rtk_regField_t LOOPED_STATE_FIELDS[]; +extern rtk_regField_t LEAVE_LOOP_STATE_FIELDS[]; +extern rtk_regField_t LOOPPAIR_FIELDS[]; +extern rtk_regField_t RRCP_CTRL_FIELDS[]; + +/* Module: Auto Recovery */ +extern rtk_regField_t RXPORT_DSC_STS_FIELDS[]; +extern rtk_regField_t SW_Q_RST_THR_FIELDS[]; +extern rtk_regField_t SW_Q_RST_P_THR_FIELDS[]; +extern rtk_regField_t LD_TX_DSC_STS_FIELDS[]; +extern rtk_regField_t TX_DSC_CHK_TMR_FIELDS[]; +extern rtk_regField_t RXFIFO_OVERFLOW_STS_FIELDS[]; +extern rtk_regField_t RXFIFO_RDEMPTY_STS_FIELDS[]; +extern rtk_regField_t TXFIFO_OVERFLOW_STS_FIELDS[]; +extern rtk_regField_t TXFIFO_RDEMPTY_STS_FIELDS[]; +extern rtk_regField_t PINGPONG_PLUS_STS_FIELDS[]; +extern rtk_regField_t TOKEN_STS_FIELDS[]; +extern rtk_regField_t SW_Q_RST_CNT_FIELDS[]; +extern rtk_regField_t AUTO_RECOVER_SRC_SEL_INGRESS_FIELDS[]; +extern rtk_regField_t AUTO_RECOVER_SRC_SEL_EGRESS_FIELDS[]; +extern rtk_regField_t AUTO_RECOVER_SRC_SEL_MAC_0_FIELDS[]; +extern rtk_regField_t AUTO_RECOVER_SRC_SEL_MAC_1_FIELDS[]; +extern rtk_regField_t TRIG_AUTO_RECOVER_CTRL_INGRESS_FIELDS[]; +extern rtk_regField_t TRIG_AUTO_RECOVER_CTRL_EGRESS_FIELDS[]; +extern rtk_regField_t TRIG_AUTO_RECOVER_CTRL_MAC_FIELDS[]; +extern rtk_regField_t AUTO_RECOVER_EVENT_FLAG_STS_INGRESS_FIELDS[]; +extern rtk_regField_t AUTO_RECOVER_EVENT_FLAG_STS_EGRESS_FIELDS[]; +extern rtk_regField_t AUTO_RECOVER_EVENT_FLAG_STS_MAC_FIELDS[]; +extern rtk_regField_t AUTO_RECOVER_EVENT_FLAG_ERR_INGRESS_FIELDS[]; +extern rtk_regField_t AUTO_RECOVER_EVENT_FLAG_ERR_EGRESS_FIELDS[]; +extern rtk_regField_t AUTO_RECOVER_EVENT_FLAG_ERR_MAC_FIELDS[]; +extern rtk_regField_t FIFO_FLOW_FLAG_MSK_FIELDS[]; + +/* Module: ECO */ +extern rtk_regField_t CHIP_MISC_DUMY_0_FIELDS[]; +extern rtk_regField_t CHIP_MISC_DUMY_1_FIELDS[]; +extern rtk_regField_t TM0_CTRL_DUMY_0_FIELDS[]; +extern rtk_regField_t TM0_CTRL_DUMY_1_FIELDS[]; +extern rtk_regField_t TM1_CTRL_DUMY_0_FIELDS[]; +extern rtk_regField_t TM1_CTRL_DUMY_1_FIELDS[]; +extern rtk_regField_t VOLT_PROB_DUMY_0_FIELDS[]; +extern rtk_regField_t VOLT_PROB_DUMY_1_FIELDS[]; +extern rtk_regField_t REG_IF_DUMY_0_FIELDS[]; +extern rtk_regField_t REG_IF_DUMY_1_FIELDS[]; +extern rtk_regField_t MIB_0_DUMY_0_FIELDS[]; +extern rtk_regField_t MIB_0_DUMY_1_FIELDS[]; +extern rtk_regField_t MIB_1_DUMY_0_FIELDS[]; +extern rtk_regField_t MIB_1_DUMY_1_FIELDS[]; +extern rtk_regField_t MIB_2_DUMY_0_FIELDS[]; +extern rtk_regField_t MIB_2_DUMY_1_FIELDS[]; +extern rtk_regField_t MIB_3_DUMY_0_FIELDS[]; +extern rtk_regField_t MIB_3_DUMY_1_FIELDS[]; +extern rtk_regField_t MIB_4_DUMY_0_FIELDS[]; +extern rtk_regField_t MIB_4_DUMY_1_FIELDS[]; +extern rtk_regField_t MIB_5_DUMY_0_FIELDS[]; +extern rtk_regField_t MIB_5_DUMY_1_FIELDS[]; +extern rtk_regField_t MIB_6_DUMY_0_FIELDS[]; +extern rtk_regField_t MIB_6_DUMY_1_FIELDS[]; +extern rtk_regField_t MIB_7_DUMY_0_FIELDS[]; +extern rtk_regField_t MIB_7_DUMY_1_FIELDS[]; +extern rtk_regField_t MIB_8_DUMY_0_FIELDS[]; +extern rtk_regField_t MIB_8_DUMY_1_FIELDS[]; +extern rtk_regField_t MIB_9_DUMY_0_FIELDS[]; +extern rtk_regField_t MIB_9_DUMY_1_FIELDS[]; +extern rtk_regField_t MIB_10_DUMY_0_FIELDS[]; +extern rtk_regField_t MIB_10_DUMY_1_FIELDS[]; +extern rtk_regField_t MIB_11_DUMY_0_FIELDS[]; +extern rtk_regField_t MIB_11_DUMY_1_FIELDS[]; +extern rtk_regField_t MIB_12_DUMY_0_FIELDS[]; +extern rtk_regField_t MIB_12_DUMY_1_FIELDS[]; +extern rtk_regField_t MIB_13_DUMY_0_FIELDS[]; +extern rtk_regField_t MIB_13_DUMY_1_FIELDS[]; +extern rtk_regField_t MIB_14_DUMY_0_FIELDS[]; +extern rtk_regField_t MIB_14_DUMY_1_FIELDS[]; +extern rtk_regField_t MIB_15_DUMY_0_FIELDS[]; +extern rtk_regField_t MIB_15_DUMY_1_FIELDS[]; +extern rtk_regField_t MIB_16_DUMY_0_FIELDS[]; +extern rtk_regField_t MIB_16_DUMY_1_FIELDS[]; +extern rtk_regField_t PHY_INTF_DUMY_0_FIELDS[]; +extern rtk_regField_t PHY_INTF_DUMY_1_FIELDS[]; +extern rtk_regField_t PHY_INTF_DUMY_2_FIELDS[]; +extern rtk_regField_t PHY_INTF_DUMY_3_FIELDS[]; +extern rtk_regField_t PHY_PKG_DUMY_0_FIELDS[]; +extern rtk_regField_t PHY_PKG_DUMY_1_FIELDS[]; +extern rtk_regField_t PHY_MISC_DUMY_0_FIELDS[]; +extern rtk_regField_t PHY_MISC_DUMY_1_FIELDS[]; +extern rtk_regField_t RANDOM_SEED_DUMY_0_FIELDS[]; +extern rtk_regField_t RANDOM_SEED_DUMY_1_FIELDS[]; +extern rtk_regField_t RANDOM_SEED_DUMY_2_FIELDS[]; +extern rtk_regField_t RANDOM_SEED_DUMY_3_FIELDS[]; +extern rtk_regField_t MIB_CTRL_DUMY_0_FIELDS[]; +extern rtk_regField_t MIB_CTRL_DUMY_1_FIELDS[]; +extern rtk_regField_t MAC_GLB_DUMY_0_FIELDS[]; +extern rtk_regField_t MAC_GLB_DUMY_1_FIELDS[]; +extern rtk_regField_t PER_PORT_MAC_DUMY_0_FIELDS[]; +extern rtk_regField_t PER_PORT_MAC_DUMY_1_FIELDS[]; +extern rtk_regField_t PER_PORT_TXQ_REG_10P_DUMY_0_FIELDS[]; +extern rtk_regField_t PER_PORT_TXQ_REG_10P_DUMY_1_FIELDS[]; +extern rtk_regField_t EGRESS_CTRL_DUMY_0_FIELDS[]; +extern rtk_regField_t EGRESS_CTRL_DUMY_1_FIELDS[]; +extern rtk_regField_t EGRESS_CTRL_DUMY_2_FIELDS[]; +extern rtk_regField_t EGRESS_CTRL_DUMY_3_FIELDS[]; +extern rtk_regField_t ACL_DUMY_0_FIELDS[]; +extern rtk_regField_t ACL_DUMY_1_FIELDS[]; +extern rtk_regField_t ACL_DUMY_2_FIELDS[]; +extern rtk_regField_t ACL_DUMY_3_FIELDS[]; +extern rtk_regField_t INBW_DUMY_0_FIELDS[]; +extern rtk_regField_t INBW_DUMY_1_FIELDS[]; +extern rtk_regField_t CVLAN_DUMY_0_FIELDS[]; +extern rtk_regField_t CVLAN_DUMY_1_FIELDS[]; +extern rtk_regField_t CVLAN_DUMY_2_FIELDS[]; +extern rtk_regField_t CVLAN_DUMY_3_FIELDS[]; +extern rtk_regField_t DPM_DUMY_0_FIELDS[]; +extern rtk_regField_t DPM_DUMY_1_FIELDS[]; +extern rtk_regField_t IGMP_DUMY_0_FIELDS[]; +extern rtk_regField_t IGMP_DUMY_1_FIELDS[]; +extern rtk_regField_t L2_DUMY_0_FIELDS[]; +extern rtk_regField_t L2_DUMY_1_FIELDS[]; +extern rtk_regField_t SVLAN_DUMY_0_FIELDS[]; +extern rtk_regField_t SVLAN_DUMY_1_FIELDS[]; +extern rtk_regField_t SVLAN_DUMY_2_FIELDS[]; +extern rtk_regField_t SVLAN_DUMY_3_FIELDS[]; +extern rtk_regField_t TABLE_DUMY_0_FIELDS[]; +extern rtk_regField_t TABLE_DUMY_1_FIELDS[]; +extern rtk_regField_t MTRPOOL_DUMY_0_FIELDS[]; +extern rtk_regField_t MTRPOOL_DUMY_1_FIELDS[]; +extern rtk_regField_t GLB_CTRL_DUMY_0_FIELDS[]; +extern rtk_regField_t GLB_CTRL_DUMY_1_FIELDS[]; +extern rtk_regField_t GLB_CTRL_DUMY_2_FIELDS[]; +extern rtk_regField_t GLB_CTRL_DUMY_3_FIELDS[]; +extern rtk_regField_t SMI_CTRL_DUMY_0_FIELDS[]; +extern rtk_regField_t SMI_CTRL_DUMY_1_FIELDS[]; +extern rtk_regField_t LED_DUMY_0_FIELDS[]; +extern rtk_regField_t LED_DUMY_1_FIELDS[]; +extern rtk_regField_t PKT_ENCAP_DUMY_0_FIELDS[]; +extern rtk_regField_t PKT_ENCAP_DUMY_1_FIELDS[]; +extern rtk_regField_t PKT_ENCAP_DUMY_2_FIELDS[]; +extern rtk_regField_t PKT_ENCAP_DUMY_3_FIELDS[]; +extern rtk_regField_t PKT_PARSER_DUMY_0_FIELDS[]; +extern rtk_regField_t PKT_PARSER_DUMY_1_FIELDS[]; +extern rtk_regField_t INGRESS_CTRL_DUMY_0_FIELDS[]; +extern rtk_regField_t INGRESS_CTRL_DUMY_1_FIELDS[]; +extern rtk_regField_t INGRESS_CTRL_DUMY_2_FIELDS[]; +extern rtk_regField_t INGRESS_CTRL_DUMY_3_FIELDS[]; +extern rtk_regField_t INGRESS_CTRL_2_DUMY_0_FIELDS[]; +extern rtk_regField_t INGRESS_CTRL_2_DUMY_1_FIELDS[]; +extern rtk_regField_t INGRESS_CTRL_2_DUMY_2_FIELDS[]; +extern rtk_regField_t INGRESS_CTRL_2_DUMY_3_FIELDS[]; +extern rtk_regField_t NIC_DUMY_0_FIELDS[]; +extern rtk_regField_t NIC_DUMY_1_FIELDS[]; +extern rtk_regField_t CHIP_BIST_DUMY_0_FIELDS[]; +extern rtk_regField_t CHIP_BIST_DUMY_1_FIELDS[]; +extern rtk_regField_t SDS_DUMY_0_FIELDS[]; +extern rtk_regField_t SDS_DUMY_1_FIELDS[]; +extern rtk_regField_t IO_DUMY_0_FIELDS[]; +extern rtk_regField_t IO_DUMY_1_FIELDS[]; +extern rtk_regField_t EFUSE_CTRL_DUMY_0_FIELDS[]; +extern rtk_regField_t EFUSE_CTRL_DUMY_1_FIELDS[]; +extern rtk_regField_t DBG_CTRL_DUMY_0_FIELDS[]; +extern rtk_regField_t DBG_CTRL_DUMY_1_FIELDS[]; +extern rtk_regField_t RATE_ADAPTER0_DUMY_0_FIELDS[]; +extern rtk_regField_t RATE_ADAPTER0_DUMY_1_FIELDS[]; +extern rtk_regField_t RATE_ADAPTER1_DUMY_0_FIELDS[]; +extern rtk_regField_t RATE_ADAPTER1_DUMY_1_FIELDS[]; +extern rtk_regField_t RATE_ADAPTER2_DUMY_0_FIELDS[]; +extern rtk_regField_t RATE_ADAPTER2_DUMY_1_FIELDS[]; +extern rtk_regField_t RATE_ADAPTER3_DUMY_0_FIELDS[]; +extern rtk_regField_t RATE_ADAPTER3_DUMY_1_FIELDS[]; + +#endif /* __RTL8373_REGFIELD_LIST_H__ */ + diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/rtl8373_reg_definition.h b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/rtl8373_reg_definition.h new file mode 100755 index 00000000..cd8f00ac --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/rtl8373_reg_definition.h @@ -0,0 +1,13500 @@ +/* + * ## Please DO NOT edit this file!! ## + * This file is auto-generated from the register source files. + * Any modifications to this file will be LOST when it is re-generated. + * + * ---------------------------------------------------------------- + * (C) Copyright 2009-2016 Realtek Semiconductor Corp. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * ---------------------------------------------------------------- + * Purpose: chip register definition and structure of RTL8373 + * + * ---------------------------------------------------------------- + */ + +#ifndef __RTL8373_REG_DEFINITION_H__ +#define __RTL8373_REG_DEFINITION_H__ + +/* + * Feature: Chip Information + */ +#define RTL8373_MODEL_NAME_INFO_ADDR (0x4) + #define RTL8373_MODEL_NAME_INFO_RTL_ID_OFFSET (16) + #define RTL8373_MODEL_NAME_INFO_RTL_ID_MASK (0xFFFF << RTL8373_MODEL_NAME_INFO_RTL_ID_OFFSET) + #define RTL8373_MODEL_NAME_INFO_MODEL_CHAR_1ST_OFFSET (11) + #define RTL8373_MODEL_NAME_INFO_MODEL_CHAR_1ST_MASK (0x1F << RTL8373_MODEL_NAME_INFO_MODEL_CHAR_1ST_OFFSET) + #define RTL8373_MODEL_NAME_INFO_MODEL_CHAR_2ND_OFFSET (6) + #define RTL8373_MODEL_NAME_INFO_MODEL_CHAR_2ND_MASK (0x1F << RTL8373_MODEL_NAME_INFO_MODEL_CHAR_2ND_OFFSET) + #define RTL8373_MODEL_NAME_INFO_TEST_CUT_OFFSET (4) + #define RTL8373_MODEL_NAME_INFO_TEST_CUT_MASK (0x3 << RTL8373_MODEL_NAME_INFO_TEST_CUT_OFFSET) + #define RTL8373_MODEL_NAME_INFO_RTL_VID_OFFSET (0) + #define RTL8373_MODEL_NAME_INFO_RTL_VID_MASK (0xF << RTL8373_MODEL_NAME_INFO_RTL_VID_OFFSET) + +#define RTL8373_CHIP_MODE_INFO_ADDR (0x8) + #define RTL8373_CHIP_MODE_INFO_DEV_PRESENT_OFFSET (14) + #define RTL8373_CHIP_MODE_INFO_DEV_PRESENT_MASK (0x3 << RTL8373_CHIP_MODE_INFO_DEV_PRESENT_OFFSET) + +#define RTL8373_CHIP_INFO_ADDR (0xC) + #define RTL8373_CHIP_INFO_RL_VID_OFFSET (28) + #define RTL8373_CHIP_INFO_RL_VID_MASK (0xF << RTL8373_CHIP_INFO_RL_VID_OFFSET) + #define RTL8373_CHIP_INFO_MCID_OFFSET (24) + #define RTL8373_CHIP_INFO_MCID_MASK (0xF << RTL8373_CHIP_INFO_MCID_OFFSET) + #define RTL8373_CHIP_INFO_BO_CHIP_MODE_RO_OFFSET (20) + #define RTL8373_CHIP_INFO_BO_CHIP_MODE_RO_MASK (0xF << RTL8373_CHIP_INFO_BO_CHIP_MODE_RO_OFFSET) + #define RTL8373_CHIP_INFO_CHIP_INFO_EN_OFFSET (16) + #define RTL8373_CHIP_INFO_CHIP_INFO_EN_MASK (0xF << RTL8373_CHIP_INFO_CHIP_INFO_EN_OFFSET) + #define RTL8373_CHIP_INFO_RL_ID_OFFSET (0) + #define RTL8373_CHIP_INFO_RL_ID_MASK (0xFFFF << RTL8373_CHIP_INFO_RL_ID_OFFSET) + +#define RTL8373_CHIP_UUID_REG_ADDR (0x10) + #define RTL8373_CHIP_UUID_REG_CHIP_UUID_OFFSET (0) + #define RTL8373_CHIP_UUID_REG_CHIP_UUID_MASK (0xFFFFFFFF << RTL8373_CHIP_UUID_REG_CHIP_UUID_OFFSET) + +#define RTL8373_CHIP_LOT_NO_REG0_ADDR (0x14) + #define RTL8373_CHIP_LOT_NO_REG0_CHIP_LOT_NO_REG0_OFFSET (0) + #define RTL8373_CHIP_LOT_NO_REG0_CHIP_LOT_NO_REG0_MASK (0xFFFFFFFF << RTL8373_CHIP_LOT_NO_REG0_CHIP_LOT_NO_REG0_OFFSET) + +#define RTL8373_CHIP_LOT_NO_REG1_ADDR (0x18) + #define RTL8373_CHIP_LOT_NO_REG1_CHIP_LOT_NO_CRC_OFFSET (8) + #define RTL8373_CHIP_LOT_NO_REG1_CHIP_LOT_NO_CRC_MASK (0xFF << RTL8373_CHIP_LOT_NO_REG1_CHIP_LOT_NO_CRC_OFFSET) + #define RTL8373_CHIP_LOT_NO_REG1_CHIP_LOT_NO_REG1_OFFSET (0) + #define RTL8373_CHIP_LOT_NO_REG1_CHIP_LOT_NO_REG1_MASK (0xFF << RTL8373_CHIP_LOT_NO_REG1_CHIP_LOT_NO_REG1_OFFSET) + +#define RTL8373_SMI_MMD_SP_ADDR (0x1C) + #define RTL8373_SMI_MMD_SP_SMI_MMD_SP_OFFSET (0) + #define RTL8373_SMI_MMD_SP_SMI_MMD_SP_MASK (0xFFFFFFFF << RTL8373_SMI_MMD_SP_SMI_MMD_SP_OFFSET) + +#define RTL8373_CFG_DMY_CHIP_INFO_1_ADDR (0x20) + #define RTL8373_CFG_DMY_CHIP_INFO_1_CFG_DMY_1_OFFSET (0) + #define RTL8373_CFG_DMY_CHIP_INFO_1_CFG_DMY_1_MASK (0xFFFFFFFF << RTL8373_CFG_DMY_CHIP_INFO_1_CFG_DMY_1_OFFSET) + +/* + * Feature: Reset + */ +#define RTL8373_RST_GLB_CTRL_0_ADDR (0x24) + #define RTL8373_RST_GLB_CTRL_0_CFG_EN_8051_OFFSET (11) + #define RTL8373_RST_GLB_CTRL_0_CFG_EN_8051_MASK (0x1 << RTL8373_RST_GLB_CTRL_0_CFG_EN_8051_OFFSET) + #define RTL8373_RST_GLB_CTRL_0_GPHY_EN_OFFSET (7) + #define RTL8373_RST_GLB_CTRL_0_GPHY_EN_MASK (0xF << RTL8373_RST_GLB_CTRL_0_GPHY_EN_OFFSET) + #define RTL8373_RST_GLB_CTRL_0_SDS_REG_RST_OFFSET (6) + #define RTL8373_RST_GLB_CTRL_0_SDS_REG_RST_MASK (0x1 << RTL8373_RST_GLB_CTRL_0_SDS_REG_RST_OFFSET) + #define RTL8373_RST_GLB_CTRL_0_SW_RST_OFFSET (5) + #define RTL8373_RST_GLB_CTRL_0_SW_RST_MASK (0x1 << RTL8373_RST_GLB_CTRL_0_SW_RST_OFFSET) + #define RTL8373_RST_GLB_CTRL_0_DW8051_RST_OFFSET (4) + #define RTL8373_RST_GLB_CTRL_0_DW8051_RST_MASK (0x1 << RTL8373_RST_GLB_CTRL_0_DW8051_RST_OFFSET) + #define RTL8373_RST_GLB_CTRL_0_SW_SERDES_RST_OFFSET (3) + #define RTL8373_RST_GLB_CTRL_0_SW_SERDES_RST_MASK (0x1 << RTL8373_RST_GLB_CTRL_0_SW_SERDES_RST_OFFSET) + #define RTL8373_RST_GLB_CTRL_0_SW_NIC_RST_OFFSET (2) + #define RTL8373_RST_GLB_CTRL_0_SW_NIC_RST_MASK (0x1 << RTL8373_RST_GLB_CTRL_0_SW_NIC_RST_OFFSET) + #define RTL8373_RST_GLB_CTRL_0_SW_Q_RST_OFFSET (1) + #define RTL8373_RST_GLB_CTRL_0_SW_Q_RST_MASK (0x1 << RTL8373_RST_GLB_CTRL_0_SW_Q_RST_OFFSET) + #define RTL8373_RST_GLB_CTRL_0_SW_CHIP_RST_OFFSET (0) + #define RTL8373_RST_GLB_CTRL_0_SW_CHIP_RST_MASK (0x1 << RTL8373_RST_GLB_CTRL_0_SW_CHIP_RST_OFFSET) + +#define RTL8373_RST_GLB_DBG_0_ADDR (0x28) + #define RTL8373_RST_GLB_DBG_0_DBGO_RST_0_OFFSET (0) + #define RTL8373_RST_GLB_DBG_0_DBGO_RST_0_MASK (0xFFFFFFFF << RTL8373_RST_GLB_DBG_0_DBGO_RST_0_OFFSET) + +#define RTL8373_RST_GLB_DBG_1_ADDR (0x2C) + #define RTL8373_RST_GLB_DBG_1_DBGO_RST_1_OFFSET (0) + #define RTL8373_RST_GLB_DBG_1_DBGO_RST_1_MASK (0xFFFFFFFF << RTL8373_RST_GLB_DBG_1_DBGO_RST_1_OFFSET) + +/* + * Feature: BIST & BISR + */ +#define RTL8373_MAC_BIST_MODE_ADDR (0xF90) + #define RTL8373_MAC_BIST_MODE_BIST_MODE_TXFIFO_PG03_OFFSET (7) + #define RTL8373_MAC_BIST_MODE_BIST_MODE_TXFIFO_PG03_MASK (0x1 << RTL8373_MAC_BIST_MODE_BIST_MODE_TXFIFO_PG03_OFFSET) + #define RTL8373_MAC_BIST_MODE_BIST_MODE_RXFIFO_PG03_OFFSET (6) + #define RTL8373_MAC_BIST_MODE_BIST_MODE_RXFIFO_PG03_MASK (0x1 << RTL8373_MAC_BIST_MODE_BIST_MODE_RXFIFO_PG03_OFFSET) + #define RTL8373_MAC_BIST_MODE_BIST_MODE_TXFIFO_PG02_OFFSET (5) + #define RTL8373_MAC_BIST_MODE_BIST_MODE_TXFIFO_PG02_MASK (0x1 << RTL8373_MAC_BIST_MODE_BIST_MODE_TXFIFO_PG02_OFFSET) + #define RTL8373_MAC_BIST_MODE_BIST_MODE_RXFIFO_PG02_OFFSET (4) + #define RTL8373_MAC_BIST_MODE_BIST_MODE_RXFIFO_PG02_MASK (0x1 << RTL8373_MAC_BIST_MODE_BIST_MODE_RXFIFO_PG02_OFFSET) + #define RTL8373_MAC_BIST_MODE_BIST_MODE_TXFIFO_PG01_OFFSET (3) + #define RTL8373_MAC_BIST_MODE_BIST_MODE_TXFIFO_PG01_MASK (0x1 << RTL8373_MAC_BIST_MODE_BIST_MODE_TXFIFO_PG01_OFFSET) + #define RTL8373_MAC_BIST_MODE_BIST_MODE_RXFIFO_PG01_OFFSET (2) + #define RTL8373_MAC_BIST_MODE_BIST_MODE_RXFIFO_PG01_MASK (0x1 << RTL8373_MAC_BIST_MODE_BIST_MODE_RXFIFO_PG01_OFFSET) + #define RTL8373_MAC_BIST_MODE_BIST_MODE_TXFIFO_PG00_OFFSET (1) + #define RTL8373_MAC_BIST_MODE_BIST_MODE_TXFIFO_PG00_MASK (0x1 << RTL8373_MAC_BIST_MODE_BIST_MODE_TXFIFO_PG00_OFFSET) + #define RTL8373_MAC_BIST_MODE_BIST_MODE_RXFIFO_PG00_OFFSET (0) + #define RTL8373_MAC_BIST_MODE_BIST_MODE_RXFIFO_PG00_MASK (0x1 << RTL8373_MAC_BIST_MODE_BIST_MODE_RXFIFO_PG00_OFFSET) + +#define RTL8373_MAC_DRF_BIST_MODE_ADDR (0xF94) + #define RTL8373_MAC_DRF_BIST_MODE_DRF_BIST_MODE_TXFIFO_PG03_OFFSET (7) + #define RTL8373_MAC_DRF_BIST_MODE_DRF_BIST_MODE_TXFIFO_PG03_MASK (0x1 << RTL8373_MAC_DRF_BIST_MODE_DRF_BIST_MODE_TXFIFO_PG03_OFFSET) + #define RTL8373_MAC_DRF_BIST_MODE_DRF_BIST_MODE_RXFIFO_PG03_OFFSET (6) + #define RTL8373_MAC_DRF_BIST_MODE_DRF_BIST_MODE_RXFIFO_PG03_MASK (0x1 << RTL8373_MAC_DRF_BIST_MODE_DRF_BIST_MODE_RXFIFO_PG03_OFFSET) + #define RTL8373_MAC_DRF_BIST_MODE_DRF_BIST_MODE_TXFIFO_PG02_OFFSET (5) + #define RTL8373_MAC_DRF_BIST_MODE_DRF_BIST_MODE_TXFIFO_PG02_MASK (0x1 << RTL8373_MAC_DRF_BIST_MODE_DRF_BIST_MODE_TXFIFO_PG02_OFFSET) + #define RTL8373_MAC_DRF_BIST_MODE_DRF_BIST_MODE_RXFIFO_PG02_OFFSET (4) + #define RTL8373_MAC_DRF_BIST_MODE_DRF_BIST_MODE_RXFIFO_PG02_MASK (0x1 << RTL8373_MAC_DRF_BIST_MODE_DRF_BIST_MODE_RXFIFO_PG02_OFFSET) + #define RTL8373_MAC_DRF_BIST_MODE_DRF_BIST_MODE_TXFIFO_PG01_OFFSET (3) + #define RTL8373_MAC_DRF_BIST_MODE_DRF_BIST_MODE_TXFIFO_PG01_MASK (0x1 << RTL8373_MAC_DRF_BIST_MODE_DRF_BIST_MODE_TXFIFO_PG01_OFFSET) + #define RTL8373_MAC_DRF_BIST_MODE_DRF_BIST_MODE_RXFIFO_PG01_OFFSET (2) + #define RTL8373_MAC_DRF_BIST_MODE_DRF_BIST_MODE_RXFIFO_PG01_MASK (0x1 << RTL8373_MAC_DRF_BIST_MODE_DRF_BIST_MODE_RXFIFO_PG01_OFFSET) + #define RTL8373_MAC_DRF_BIST_MODE_DRF_BIST_MODE_TXFIFO_PG00_OFFSET (1) + #define RTL8373_MAC_DRF_BIST_MODE_DRF_BIST_MODE_TXFIFO_PG00_MASK (0x1 << RTL8373_MAC_DRF_BIST_MODE_DRF_BIST_MODE_TXFIFO_PG00_OFFSET) + #define RTL8373_MAC_DRF_BIST_MODE_DRF_BIST_MODE_RXFIFO_PG00_OFFSET (0) + #define RTL8373_MAC_DRF_BIST_MODE_DRF_BIST_MODE_RXFIFO_PG00_MASK (0x1 << RTL8373_MAC_DRF_BIST_MODE_DRF_BIST_MODE_RXFIFO_PG00_OFFSET) + +#define RTL8373_MAC_BIST_RSTN_ADDR (0xF98) + #define RTL8373_MAC_BIST_RSTN_BIST_RSTN_TXFIFO_PG03_OFFSET (7) + #define RTL8373_MAC_BIST_RSTN_BIST_RSTN_TXFIFO_PG03_MASK (0x1 << RTL8373_MAC_BIST_RSTN_BIST_RSTN_TXFIFO_PG03_OFFSET) + #define RTL8373_MAC_BIST_RSTN_BIST_RSTN_RXFIFO_PG03_OFFSET (6) + #define RTL8373_MAC_BIST_RSTN_BIST_RSTN_RXFIFO_PG03_MASK (0x1 << RTL8373_MAC_BIST_RSTN_BIST_RSTN_RXFIFO_PG03_OFFSET) + #define RTL8373_MAC_BIST_RSTN_BIST_RSTN_TXFIFO_PG02_OFFSET (5) + #define RTL8373_MAC_BIST_RSTN_BIST_RSTN_TXFIFO_PG02_MASK (0x1 << RTL8373_MAC_BIST_RSTN_BIST_RSTN_TXFIFO_PG02_OFFSET) + #define RTL8373_MAC_BIST_RSTN_BIST_RSTN_RXFIFO_PG02_OFFSET (4) + #define RTL8373_MAC_BIST_RSTN_BIST_RSTN_RXFIFO_PG02_MASK (0x1 << RTL8373_MAC_BIST_RSTN_BIST_RSTN_RXFIFO_PG02_OFFSET) + #define RTL8373_MAC_BIST_RSTN_BIST_RSTN_TXFIFO_PG01_OFFSET (3) + #define RTL8373_MAC_BIST_RSTN_BIST_RSTN_TXFIFO_PG01_MASK (0x1 << RTL8373_MAC_BIST_RSTN_BIST_RSTN_TXFIFO_PG01_OFFSET) + #define RTL8373_MAC_BIST_RSTN_BIST_RSTN_RXFIFO_PG01_OFFSET (2) + #define RTL8373_MAC_BIST_RSTN_BIST_RSTN_RXFIFO_PG01_MASK (0x1 << RTL8373_MAC_BIST_RSTN_BIST_RSTN_RXFIFO_PG01_OFFSET) + #define RTL8373_MAC_BIST_RSTN_BIST_RSTN_TXFIFO_PG00_OFFSET (1) + #define RTL8373_MAC_BIST_RSTN_BIST_RSTN_TXFIFO_PG00_MASK (0x1 << RTL8373_MAC_BIST_RSTN_BIST_RSTN_TXFIFO_PG00_OFFSET) + #define RTL8373_MAC_BIST_RSTN_BIST_RSTN_RXFIFO_PG00_OFFSET (0) + #define RTL8373_MAC_BIST_RSTN_BIST_RSTN_RXFIFO_PG00_MASK (0x1 << RTL8373_MAC_BIST_RSTN_BIST_RSTN_RXFIFO_PG00_OFFSET) + +#define RTL8373_MAC_BIST_LOOP_MODE_ADDR (0xF9C) + #define RTL8373_MAC_BIST_LOOP_MODE_BIST_LOOP_MODE_TXFIFO_PG03_OFFSET (7) + #define RTL8373_MAC_BIST_LOOP_MODE_BIST_LOOP_MODE_TXFIFO_PG03_MASK (0x1 << RTL8373_MAC_BIST_LOOP_MODE_BIST_LOOP_MODE_TXFIFO_PG03_OFFSET) + #define RTL8373_MAC_BIST_LOOP_MODE_BIST_LOOP_MODE_RXFIFO_PG03_OFFSET (6) + #define RTL8373_MAC_BIST_LOOP_MODE_BIST_LOOP_MODE_RXFIFO_PG03_MASK (0x1 << RTL8373_MAC_BIST_LOOP_MODE_BIST_LOOP_MODE_RXFIFO_PG03_OFFSET) + #define RTL8373_MAC_BIST_LOOP_MODE_BIST_LOOP_MODE_TXFIFO_PG02_OFFSET (5) + #define RTL8373_MAC_BIST_LOOP_MODE_BIST_LOOP_MODE_TXFIFO_PG02_MASK (0x1 << RTL8373_MAC_BIST_LOOP_MODE_BIST_LOOP_MODE_TXFIFO_PG02_OFFSET) + #define RTL8373_MAC_BIST_LOOP_MODE_BIST_LOOP_MODE_RXFIFO_PG02_OFFSET (4) + #define RTL8373_MAC_BIST_LOOP_MODE_BIST_LOOP_MODE_RXFIFO_PG02_MASK (0x1 << RTL8373_MAC_BIST_LOOP_MODE_BIST_LOOP_MODE_RXFIFO_PG02_OFFSET) + #define RTL8373_MAC_BIST_LOOP_MODE_BIST_LOOP_MODE_TXFIFO_PG01_OFFSET (3) + #define RTL8373_MAC_BIST_LOOP_MODE_BIST_LOOP_MODE_TXFIFO_PG01_MASK (0x1 << RTL8373_MAC_BIST_LOOP_MODE_BIST_LOOP_MODE_TXFIFO_PG01_OFFSET) + #define RTL8373_MAC_BIST_LOOP_MODE_BIST_LOOP_MODE_RXFIFO_PG01_OFFSET (2) + #define RTL8373_MAC_BIST_LOOP_MODE_BIST_LOOP_MODE_RXFIFO_PG01_MASK (0x1 << RTL8373_MAC_BIST_LOOP_MODE_BIST_LOOP_MODE_RXFIFO_PG01_OFFSET) + #define RTL8373_MAC_BIST_LOOP_MODE_BIST_LOOP_MODE_TXFIFO_PG00_OFFSET (1) + #define RTL8373_MAC_BIST_LOOP_MODE_BIST_LOOP_MODE_TXFIFO_PG00_MASK (0x1 << RTL8373_MAC_BIST_LOOP_MODE_BIST_LOOP_MODE_TXFIFO_PG00_OFFSET) + #define RTL8373_MAC_BIST_LOOP_MODE_BIST_LOOP_MODE_RXFIFO_PG00_OFFSET (0) + #define RTL8373_MAC_BIST_LOOP_MODE_BIST_LOOP_MODE_RXFIFO_PG00_MASK (0x1 << RTL8373_MAC_BIST_LOOP_MODE_BIST_LOOP_MODE_RXFIFO_PG00_OFFSET) + +#define RTL8373_MAC_BIST_DYN_READ_EN_ADDR (0xFA0) + #define RTL8373_MAC_BIST_DYN_READ_EN_BIST_DYN_READ_EN_TXFIFO_PG03_OFFSET (7) + #define RTL8373_MAC_BIST_DYN_READ_EN_BIST_DYN_READ_EN_TXFIFO_PG03_MASK (0x1 << RTL8373_MAC_BIST_DYN_READ_EN_BIST_DYN_READ_EN_TXFIFO_PG03_OFFSET) + #define RTL8373_MAC_BIST_DYN_READ_EN_BIST_DYN_READ_EN_RXFIFO_PG03_OFFSET (6) + #define RTL8373_MAC_BIST_DYN_READ_EN_BIST_DYN_READ_EN_RXFIFO_PG03_MASK (0x1 << RTL8373_MAC_BIST_DYN_READ_EN_BIST_DYN_READ_EN_RXFIFO_PG03_OFFSET) + #define RTL8373_MAC_BIST_DYN_READ_EN_BIST_DYN_READ_EN_TXFIFO_PG02_OFFSET (5) + #define RTL8373_MAC_BIST_DYN_READ_EN_BIST_DYN_READ_EN_TXFIFO_PG02_MASK (0x1 << RTL8373_MAC_BIST_DYN_READ_EN_BIST_DYN_READ_EN_TXFIFO_PG02_OFFSET) + #define RTL8373_MAC_BIST_DYN_READ_EN_BIST_DYN_READ_EN_RXFIFO_PG02_OFFSET (4) + #define RTL8373_MAC_BIST_DYN_READ_EN_BIST_DYN_READ_EN_RXFIFO_PG02_MASK (0x1 << RTL8373_MAC_BIST_DYN_READ_EN_BIST_DYN_READ_EN_RXFIFO_PG02_OFFSET) + #define RTL8373_MAC_BIST_DYN_READ_EN_BIST_DYN_READ_EN_TXFIFO_PG01_OFFSET (3) + #define RTL8373_MAC_BIST_DYN_READ_EN_BIST_DYN_READ_EN_TXFIFO_PG01_MASK (0x1 << RTL8373_MAC_BIST_DYN_READ_EN_BIST_DYN_READ_EN_TXFIFO_PG01_OFFSET) + #define RTL8373_MAC_BIST_DYN_READ_EN_BIST_DYN_READ_EN_RXFIFO_PG01_OFFSET (2) + #define RTL8373_MAC_BIST_DYN_READ_EN_BIST_DYN_READ_EN_RXFIFO_PG01_MASK (0x1 << RTL8373_MAC_BIST_DYN_READ_EN_BIST_DYN_READ_EN_RXFIFO_PG01_OFFSET) + #define RTL8373_MAC_BIST_DYN_READ_EN_BIST_DYN_READ_EN_TXFIFO_PG00_OFFSET (1) + #define RTL8373_MAC_BIST_DYN_READ_EN_BIST_DYN_READ_EN_TXFIFO_PG00_MASK (0x1 << RTL8373_MAC_BIST_DYN_READ_EN_BIST_DYN_READ_EN_TXFIFO_PG00_OFFSET) + #define RTL8373_MAC_BIST_DYN_READ_EN_BIST_DYN_READ_EN_RXFIFO_PG00_OFFSET (0) + #define RTL8373_MAC_BIST_DYN_READ_EN_BIST_DYN_READ_EN_RXFIFO_PG00_MASK (0x1 << RTL8373_MAC_BIST_DYN_READ_EN_BIST_DYN_READ_EN_RXFIFO_PG00_OFFSET) + +#define RTL8373_MAC_DRF_TEST_RESUME_ADDR (0xFA4) + #define RTL8373_MAC_DRF_TEST_RESUME_DRF_TEST_RESUME_TXFIFO_PG03_OFFSET (7) + #define RTL8373_MAC_DRF_TEST_RESUME_DRF_TEST_RESUME_TXFIFO_PG03_MASK (0x1 << RTL8373_MAC_DRF_TEST_RESUME_DRF_TEST_RESUME_TXFIFO_PG03_OFFSET) + #define RTL8373_MAC_DRF_TEST_RESUME_DRF_TEST_RESUME_RXFIFO_PG03_OFFSET (6) + #define RTL8373_MAC_DRF_TEST_RESUME_DRF_TEST_RESUME_RXFIFO_PG03_MASK (0x1 << RTL8373_MAC_DRF_TEST_RESUME_DRF_TEST_RESUME_RXFIFO_PG03_OFFSET) + #define RTL8373_MAC_DRF_TEST_RESUME_DRF_TEST_RESUME_TXFIFO_PG02_OFFSET (5) + #define RTL8373_MAC_DRF_TEST_RESUME_DRF_TEST_RESUME_TXFIFO_PG02_MASK (0x1 << RTL8373_MAC_DRF_TEST_RESUME_DRF_TEST_RESUME_TXFIFO_PG02_OFFSET) + #define RTL8373_MAC_DRF_TEST_RESUME_DRF_TEST_RESUME_RXFIFO_PG02_OFFSET (4) + #define RTL8373_MAC_DRF_TEST_RESUME_DRF_TEST_RESUME_RXFIFO_PG02_MASK (0x1 << RTL8373_MAC_DRF_TEST_RESUME_DRF_TEST_RESUME_RXFIFO_PG02_OFFSET) + #define RTL8373_MAC_DRF_TEST_RESUME_DRF_TEST_RESUME_TXFIFO_PG01_OFFSET (3) + #define RTL8373_MAC_DRF_TEST_RESUME_DRF_TEST_RESUME_TXFIFO_PG01_MASK (0x1 << RTL8373_MAC_DRF_TEST_RESUME_DRF_TEST_RESUME_TXFIFO_PG01_OFFSET) + #define RTL8373_MAC_DRF_TEST_RESUME_DRF_TEST_RESUME_RXFIFO_PG01_OFFSET (2) + #define RTL8373_MAC_DRF_TEST_RESUME_DRF_TEST_RESUME_RXFIFO_PG01_MASK (0x1 << RTL8373_MAC_DRF_TEST_RESUME_DRF_TEST_RESUME_RXFIFO_PG01_OFFSET) + #define RTL8373_MAC_DRF_TEST_RESUME_DRF_TEST_RESUME_TXFIFO_PG00_OFFSET (1) + #define RTL8373_MAC_DRF_TEST_RESUME_DRF_TEST_RESUME_TXFIFO_PG00_MASK (0x1 << RTL8373_MAC_DRF_TEST_RESUME_DRF_TEST_RESUME_TXFIFO_PG00_OFFSET) + #define RTL8373_MAC_DRF_TEST_RESUME_DRF_TEST_RESUME_RXFIFO_PG00_OFFSET (0) + #define RTL8373_MAC_DRF_TEST_RESUME_DRF_TEST_RESUME_RXFIFO_PG00_MASK (0x1 << RTL8373_MAC_DRF_TEST_RESUME_DRF_TEST_RESUME_RXFIFO_PG00_OFFSET) + +#define RTL8373_MAC_DRF_START_PAUSE_ADDR (0xFA8) + #define RTL8373_MAC_DRF_START_PAUSE_DRF_START_PAUSE_TXFIFO_PG03_OFFSET (7) + #define RTL8373_MAC_DRF_START_PAUSE_DRF_START_PAUSE_TXFIFO_PG03_MASK (0x1 << RTL8373_MAC_DRF_START_PAUSE_DRF_START_PAUSE_TXFIFO_PG03_OFFSET) + #define RTL8373_MAC_DRF_START_PAUSE_DRF_START_PAUSE_RXFIFO_PG03_OFFSET (6) + #define RTL8373_MAC_DRF_START_PAUSE_DRF_START_PAUSE_RXFIFO_PG03_MASK (0x1 << RTL8373_MAC_DRF_START_PAUSE_DRF_START_PAUSE_RXFIFO_PG03_OFFSET) + #define RTL8373_MAC_DRF_START_PAUSE_DRF_START_PAUSE_TXFIFO_PG02_OFFSET (5) + #define RTL8373_MAC_DRF_START_PAUSE_DRF_START_PAUSE_TXFIFO_PG02_MASK (0x1 << RTL8373_MAC_DRF_START_PAUSE_DRF_START_PAUSE_TXFIFO_PG02_OFFSET) + #define RTL8373_MAC_DRF_START_PAUSE_DRF_START_PAUSE_RXFIFO_PG02_OFFSET (4) + #define RTL8373_MAC_DRF_START_PAUSE_DRF_START_PAUSE_RXFIFO_PG02_MASK (0x1 << RTL8373_MAC_DRF_START_PAUSE_DRF_START_PAUSE_RXFIFO_PG02_OFFSET) + #define RTL8373_MAC_DRF_START_PAUSE_DRF_START_PAUSE_TXFIFO_PG01_OFFSET (3) + #define RTL8373_MAC_DRF_START_PAUSE_DRF_START_PAUSE_TXFIFO_PG01_MASK (0x1 << RTL8373_MAC_DRF_START_PAUSE_DRF_START_PAUSE_TXFIFO_PG01_OFFSET) + #define RTL8373_MAC_DRF_START_PAUSE_DRF_START_PAUSE_RXFIFO_PG01_OFFSET (2) + #define RTL8373_MAC_DRF_START_PAUSE_DRF_START_PAUSE_RXFIFO_PG01_MASK (0x1 << RTL8373_MAC_DRF_START_PAUSE_DRF_START_PAUSE_RXFIFO_PG01_OFFSET) + #define RTL8373_MAC_DRF_START_PAUSE_DRF_START_PAUSE_TXFIFO_PG00_OFFSET (1) + #define RTL8373_MAC_DRF_START_PAUSE_DRF_START_PAUSE_TXFIFO_PG00_MASK (0x1 << RTL8373_MAC_DRF_START_PAUSE_DRF_START_PAUSE_TXFIFO_PG00_OFFSET) + #define RTL8373_MAC_DRF_START_PAUSE_DRF_START_PAUSE_RXFIFO_PG00_OFFSET (0) + #define RTL8373_MAC_DRF_START_PAUSE_DRF_START_PAUSE_RXFIFO_PG00_MASK (0x1 << RTL8373_MAC_DRF_START_PAUSE_DRF_START_PAUSE_RXFIFO_PG00_OFFSET) + +#define RTL8373_MAC_MBIST_DONE_ADDR (0xFAC) + #define RTL8373_MAC_MBIST_DONE_BIST_DONE_TXFIFO_PG03_OFFSET (7) + #define RTL8373_MAC_MBIST_DONE_BIST_DONE_TXFIFO_PG03_MASK (0x1 << RTL8373_MAC_MBIST_DONE_BIST_DONE_TXFIFO_PG03_OFFSET) + #define RTL8373_MAC_MBIST_DONE_BIST_DONE_RXFIFO_PG03_OFFSET (6) + #define RTL8373_MAC_MBIST_DONE_BIST_DONE_RXFIFO_PG03_MASK (0x1 << RTL8373_MAC_MBIST_DONE_BIST_DONE_RXFIFO_PG03_OFFSET) + #define RTL8373_MAC_MBIST_DONE_BIST_DONE_TXFIFO_PG02_OFFSET (5) + #define RTL8373_MAC_MBIST_DONE_BIST_DONE_TXFIFO_PG02_MASK (0x1 << RTL8373_MAC_MBIST_DONE_BIST_DONE_TXFIFO_PG02_OFFSET) + #define RTL8373_MAC_MBIST_DONE_BIST_DONE_RXFIFO_PG02_OFFSET (4) + #define RTL8373_MAC_MBIST_DONE_BIST_DONE_RXFIFO_PG02_MASK (0x1 << RTL8373_MAC_MBIST_DONE_BIST_DONE_RXFIFO_PG02_OFFSET) + #define RTL8373_MAC_MBIST_DONE_BIST_DONE_TXFIFO_PG01_OFFSET (3) + #define RTL8373_MAC_MBIST_DONE_BIST_DONE_TXFIFO_PG01_MASK (0x1 << RTL8373_MAC_MBIST_DONE_BIST_DONE_TXFIFO_PG01_OFFSET) + #define RTL8373_MAC_MBIST_DONE_BIST_DONE_RXFIFO_PG01_OFFSET (2) + #define RTL8373_MAC_MBIST_DONE_BIST_DONE_RXFIFO_PG01_MASK (0x1 << RTL8373_MAC_MBIST_DONE_BIST_DONE_RXFIFO_PG01_OFFSET) + #define RTL8373_MAC_MBIST_DONE_BIST_DONE_TXFIFO_PG00_OFFSET (1) + #define RTL8373_MAC_MBIST_DONE_BIST_DONE_TXFIFO_PG00_MASK (0x1 << RTL8373_MAC_MBIST_DONE_BIST_DONE_TXFIFO_PG00_OFFSET) + #define RTL8373_MAC_MBIST_DONE_BIST_DONE_RXFIFO_PG00_OFFSET (0) + #define RTL8373_MAC_MBIST_DONE_BIST_DONE_RXFIFO_PG00_MASK (0x1 << RTL8373_MAC_MBIST_DONE_BIST_DONE_RXFIFO_PG00_OFFSET) + +#define RTL8373_MAC_MBIST_DRF_DONE_ADDR (0xFB0) + #define RTL8373_MAC_MBIST_DRF_DONE_BIST_DRF_DONE_TXFIFO_PG03_OFFSET (7) + #define RTL8373_MAC_MBIST_DRF_DONE_BIST_DRF_DONE_TXFIFO_PG03_MASK (0x1 << RTL8373_MAC_MBIST_DRF_DONE_BIST_DRF_DONE_TXFIFO_PG03_OFFSET) + #define RTL8373_MAC_MBIST_DRF_DONE_BIST_DRF_DONE_RXFIFO_PG03_OFFSET (6) + #define RTL8373_MAC_MBIST_DRF_DONE_BIST_DRF_DONE_RXFIFO_PG03_MASK (0x1 << RTL8373_MAC_MBIST_DRF_DONE_BIST_DRF_DONE_RXFIFO_PG03_OFFSET) + #define RTL8373_MAC_MBIST_DRF_DONE_BIST_DRF_DONE_TXFIFO_PG02_OFFSET (5) + #define RTL8373_MAC_MBIST_DRF_DONE_BIST_DRF_DONE_TXFIFO_PG02_MASK (0x1 << RTL8373_MAC_MBIST_DRF_DONE_BIST_DRF_DONE_TXFIFO_PG02_OFFSET) + #define RTL8373_MAC_MBIST_DRF_DONE_BIST_DRF_DONE_RXFIFO_PG02_OFFSET (4) + #define RTL8373_MAC_MBIST_DRF_DONE_BIST_DRF_DONE_RXFIFO_PG02_MASK (0x1 << RTL8373_MAC_MBIST_DRF_DONE_BIST_DRF_DONE_RXFIFO_PG02_OFFSET) + #define RTL8373_MAC_MBIST_DRF_DONE_BIST_DRF_DONE_TXFIFO_PG01_OFFSET (3) + #define RTL8373_MAC_MBIST_DRF_DONE_BIST_DRF_DONE_TXFIFO_PG01_MASK (0x1 << RTL8373_MAC_MBIST_DRF_DONE_BIST_DRF_DONE_TXFIFO_PG01_OFFSET) + #define RTL8373_MAC_MBIST_DRF_DONE_BIST_DRF_DONE_RXFIFO_PG01_OFFSET (2) + #define RTL8373_MAC_MBIST_DRF_DONE_BIST_DRF_DONE_RXFIFO_PG01_MASK (0x1 << RTL8373_MAC_MBIST_DRF_DONE_BIST_DRF_DONE_RXFIFO_PG01_OFFSET) + #define RTL8373_MAC_MBIST_DRF_DONE_BIST_DRF_DONE_TXFIFO_PG00_OFFSET (1) + #define RTL8373_MAC_MBIST_DRF_DONE_BIST_DRF_DONE_TXFIFO_PG00_MASK (0x1 << RTL8373_MAC_MBIST_DRF_DONE_BIST_DRF_DONE_TXFIFO_PG00_OFFSET) + #define RTL8373_MAC_MBIST_DRF_DONE_BIST_DRF_DONE_RXFIFO_PG00_OFFSET (0) + #define RTL8373_MAC_MBIST_DRF_DONE_BIST_DRF_DONE_RXFIFO_PG00_MASK (0x1 << RTL8373_MAC_MBIST_DRF_DONE_BIST_DRF_DONE_RXFIFO_PG00_OFFSET) + +#define RTL8373_MAC_MBIST_FAIL_PG00_PG01_ADDR (0xFB4) + #define RTL8373_MAC_MBIST_FAIL_PG00_PG01_BIST_FAIL_TXFIFO_PG01_OFFSET (22) + #define RTL8373_MAC_MBIST_FAIL_PG00_PG01_BIST_FAIL_TXFIFO_PG01_MASK (0xF << RTL8373_MAC_MBIST_FAIL_PG00_PG01_BIST_FAIL_TXFIFO_PG01_OFFSET) + #define RTL8373_MAC_MBIST_FAIL_PG00_PG01_BIST_FAIL_RXFIFO_PG01_OFFSET (14) + #define RTL8373_MAC_MBIST_FAIL_PG00_PG01_BIST_FAIL_RXFIFO_PG01_MASK (0xFF << RTL8373_MAC_MBIST_FAIL_PG00_PG01_BIST_FAIL_RXFIFO_PG01_OFFSET) + #define RTL8373_MAC_MBIST_FAIL_PG00_PG01_BIST_FAIL_TXFIFO_PG00_OFFSET (8) + #define RTL8373_MAC_MBIST_FAIL_PG00_PG01_BIST_FAIL_TXFIFO_PG00_MASK (0x3F << RTL8373_MAC_MBIST_FAIL_PG00_PG01_BIST_FAIL_TXFIFO_PG00_OFFSET) + #define RTL8373_MAC_MBIST_FAIL_PG00_PG01_BIST_FAIL_RXFIFO_PG00_OFFSET (0) + #define RTL8373_MAC_MBIST_FAIL_PG00_PG01_BIST_FAIL_RXFIFO_PG00_MASK (0xFF << RTL8373_MAC_MBIST_FAIL_PG00_PG01_BIST_FAIL_RXFIFO_PG00_OFFSET) + +#define RTL8373_MAC_MBIST_FAIL_PG02_PG03_ADDR (0xFB8) + #define RTL8373_MAC_MBIST_FAIL_PG02_PG03_BIST_FAIL_TXFIFO_PG03_OFFSET (14) + #define RTL8373_MAC_MBIST_FAIL_PG02_PG03_BIST_FAIL_TXFIFO_PG03_MASK (0x1 << RTL8373_MAC_MBIST_FAIL_PG02_PG03_BIST_FAIL_TXFIFO_PG03_OFFSET) + #define RTL8373_MAC_MBIST_FAIL_PG02_PG03_BIST_FAIL_RXFIFO_PG03_OFFSET (12) + #define RTL8373_MAC_MBIST_FAIL_PG02_PG03_BIST_FAIL_RXFIFO_PG03_MASK (0x3 << RTL8373_MAC_MBIST_FAIL_PG02_PG03_BIST_FAIL_RXFIFO_PG03_OFFSET) + #define RTL8373_MAC_MBIST_FAIL_PG02_PG03_BIST_FAIL_TXFIFO_PG02_OFFSET (6) + #define RTL8373_MAC_MBIST_FAIL_PG02_PG03_BIST_FAIL_TXFIFO_PG02_MASK (0x3F << RTL8373_MAC_MBIST_FAIL_PG02_PG03_BIST_FAIL_TXFIFO_PG02_OFFSET) + #define RTL8373_MAC_MBIST_FAIL_PG02_PG03_BIST_FAIL_RXFIFO_PG02_OFFSET (0) + #define RTL8373_MAC_MBIST_FAIL_PG02_PG03_BIST_FAIL_RXFIFO_PG02_MASK (0x3F << RTL8373_MAC_MBIST_FAIL_PG02_PG03_BIST_FAIL_RXFIFO_PG02_OFFSET) + +#define RTL8373_MAC_MBIST_DRF_FAIL_PG00_PG01_ADDR (0xFBC) + #define RTL8373_MAC_MBIST_DRF_FAIL_PG00_PG01_BIST_DRF_FAIL_TXFIFO_PG01_OFFSET (22) + #define RTL8373_MAC_MBIST_DRF_FAIL_PG00_PG01_BIST_DRF_FAIL_TXFIFO_PG01_MASK (0xF << RTL8373_MAC_MBIST_DRF_FAIL_PG00_PG01_BIST_DRF_FAIL_TXFIFO_PG01_OFFSET) + #define RTL8373_MAC_MBIST_DRF_FAIL_PG00_PG01_BIST_DRF_FAIL_RXFIFO_PG01_OFFSET (14) + #define RTL8373_MAC_MBIST_DRF_FAIL_PG00_PG01_BIST_DRF_FAIL_RXFIFO_PG01_MASK (0xFF << RTL8373_MAC_MBIST_DRF_FAIL_PG00_PG01_BIST_DRF_FAIL_RXFIFO_PG01_OFFSET) + #define RTL8373_MAC_MBIST_DRF_FAIL_PG00_PG01_BIST_DRF_FAIL_TXFIFO_PG00_OFFSET (8) + #define RTL8373_MAC_MBIST_DRF_FAIL_PG00_PG01_BIST_DRF_FAIL_TXFIFO_PG00_MASK (0x3F << RTL8373_MAC_MBIST_DRF_FAIL_PG00_PG01_BIST_DRF_FAIL_TXFIFO_PG00_OFFSET) + #define RTL8373_MAC_MBIST_DRF_FAIL_PG00_PG01_BIST_DRF_FAIL_RXFIFO_PG00_OFFSET (0) + #define RTL8373_MAC_MBIST_DRF_FAIL_PG00_PG01_BIST_DRF_FAIL_RXFIFO_PG00_MASK (0xFF << RTL8373_MAC_MBIST_DRF_FAIL_PG00_PG01_BIST_DRF_FAIL_RXFIFO_PG00_OFFSET) + +#define RTL8373_MAC_MBIST_DRF_FAIL_PG02_PG03_ADDR (0xFC0) + #define RTL8373_MAC_MBIST_DRF_FAIL_PG02_PG03_BIST_DRF_FAIL_TXFIFO_PG03_OFFSET (14) + #define RTL8373_MAC_MBIST_DRF_FAIL_PG02_PG03_BIST_DRF_FAIL_TXFIFO_PG03_MASK (0x1 << RTL8373_MAC_MBIST_DRF_FAIL_PG02_PG03_BIST_DRF_FAIL_TXFIFO_PG03_OFFSET) + #define RTL8373_MAC_MBIST_DRF_FAIL_PG02_PG03_BIST_DRF_FAIL_RXFIFO_PG03_OFFSET (12) + #define RTL8373_MAC_MBIST_DRF_FAIL_PG02_PG03_BIST_DRF_FAIL_RXFIFO_PG03_MASK (0x3 << RTL8373_MAC_MBIST_DRF_FAIL_PG02_PG03_BIST_DRF_FAIL_RXFIFO_PG03_OFFSET) + #define RTL8373_MAC_MBIST_DRF_FAIL_PG02_PG03_BIST_DRF_FAIL_TXFIFO_PG02_OFFSET (6) + #define RTL8373_MAC_MBIST_DRF_FAIL_PG02_PG03_BIST_DRF_FAIL_TXFIFO_PG02_MASK (0x3F << RTL8373_MAC_MBIST_DRF_FAIL_PG02_PG03_BIST_DRF_FAIL_TXFIFO_PG02_OFFSET) + #define RTL8373_MAC_MBIST_DRF_FAIL_PG02_PG03_BIST_DRF_FAIL_RXFIFO_PG02_OFFSET (0) + #define RTL8373_MAC_MBIST_DRF_FAIL_PG02_PG03_BIST_DRF_FAIL_RXFIFO_PG02_MASK (0x3F << RTL8373_MAC_MBIST_DRF_FAIL_PG02_PG03_BIST_DRF_FAIL_RXFIFO_PG02_OFFSET) + +#define RTL8373_MAC_RXFIFO_LS_ADDR (0xFC4) + #define RTL8373_MAC_RXFIFO_LS_CFG_RXFIFO_LS_PG03_OFFSET (22) + #define RTL8373_MAC_RXFIFO_LS_CFG_RXFIFO_LS_PG03_MASK (0x3 << RTL8373_MAC_RXFIFO_LS_CFG_RXFIFO_LS_PG03_OFFSET) + #define RTL8373_MAC_RXFIFO_LS_CFG_RXFIFO_LS_PG02_OFFSET (16) + #define RTL8373_MAC_RXFIFO_LS_CFG_RXFIFO_LS_PG02_MASK (0x3F << RTL8373_MAC_RXFIFO_LS_CFG_RXFIFO_LS_PG02_OFFSET) + #define RTL8373_MAC_RXFIFO_LS_CFG_RXFIFO_LS_PG01_OFFSET (8) + #define RTL8373_MAC_RXFIFO_LS_CFG_RXFIFO_LS_PG01_MASK (0xFF << RTL8373_MAC_RXFIFO_LS_CFG_RXFIFO_LS_PG01_OFFSET) + #define RTL8373_MAC_RXFIFO_LS_CFG_RXFIFO_LS_PG00_OFFSET (0) + #define RTL8373_MAC_RXFIFO_LS_CFG_RXFIFO_LS_PG00_MASK (0xFF << RTL8373_MAC_RXFIFO_LS_CFG_RXFIFO_LS_PG00_OFFSET) + +#define RTL8373_MAC_RXFIFO_RMEA_ADDR (0xFC8) + #define RTL8373_MAC_RXFIFO_RMEA_CFG_RXFIFO_RMEA_PG03_OFFSET (22) + #define RTL8373_MAC_RXFIFO_RMEA_CFG_RXFIFO_RMEA_PG03_MASK (0x3 << RTL8373_MAC_RXFIFO_RMEA_CFG_RXFIFO_RMEA_PG03_OFFSET) + #define RTL8373_MAC_RXFIFO_RMEA_CFG_RXFIFO_RMEA_PG02_OFFSET (16) + #define RTL8373_MAC_RXFIFO_RMEA_CFG_RXFIFO_RMEA_PG02_MASK (0x3F << RTL8373_MAC_RXFIFO_RMEA_CFG_RXFIFO_RMEA_PG02_OFFSET) + #define RTL8373_MAC_RXFIFO_RMEA_CFG_RXFIFO_RMEA_PG01_OFFSET (8) + #define RTL8373_MAC_RXFIFO_RMEA_CFG_RXFIFO_RMEA_PG01_MASK (0xFF << RTL8373_MAC_RXFIFO_RMEA_CFG_RXFIFO_RMEA_PG01_OFFSET) + #define RTL8373_MAC_RXFIFO_RMEA_CFG_RXFIFO_RMEA_PG00_OFFSET (0) + #define RTL8373_MAC_RXFIFO_RMEA_CFG_RXFIFO_RMEA_PG00_MASK (0xFF << RTL8373_MAC_RXFIFO_RMEA_CFG_RXFIFO_RMEA_PG00_OFFSET) + +#define RTL8373_MAC_RXFIFO_RMA_PG00_ADDR (0xFCC) + #define RTL8373_MAC_RXFIFO_RMA_PG00_CFG_RXFIFO_RMA_7_PG00_OFFSET (28) + #define RTL8373_MAC_RXFIFO_RMA_PG00_CFG_RXFIFO_RMA_7_PG00_MASK (0xF << RTL8373_MAC_RXFIFO_RMA_PG00_CFG_RXFIFO_RMA_7_PG00_OFFSET) + #define RTL8373_MAC_RXFIFO_RMA_PG00_CFG_RXFIFO_RMA_6_PG00_OFFSET (24) + #define RTL8373_MAC_RXFIFO_RMA_PG00_CFG_RXFIFO_RMA_6_PG00_MASK (0xF << RTL8373_MAC_RXFIFO_RMA_PG00_CFG_RXFIFO_RMA_6_PG00_OFFSET) + #define RTL8373_MAC_RXFIFO_RMA_PG00_CFG_RXFIFO_RMA_5_PG00_OFFSET (20) + #define RTL8373_MAC_RXFIFO_RMA_PG00_CFG_RXFIFO_RMA_5_PG00_MASK (0xF << RTL8373_MAC_RXFIFO_RMA_PG00_CFG_RXFIFO_RMA_5_PG00_OFFSET) + #define RTL8373_MAC_RXFIFO_RMA_PG00_CFG_RXFIFO_RMA_4_PG00_OFFSET (16) + #define RTL8373_MAC_RXFIFO_RMA_PG00_CFG_RXFIFO_RMA_4_PG00_MASK (0xF << RTL8373_MAC_RXFIFO_RMA_PG00_CFG_RXFIFO_RMA_4_PG00_OFFSET) + #define RTL8373_MAC_RXFIFO_RMA_PG00_CFG_RXFIFO_RMA_3_PG00_OFFSET (12) + #define RTL8373_MAC_RXFIFO_RMA_PG00_CFG_RXFIFO_RMA_3_PG00_MASK (0xF << RTL8373_MAC_RXFIFO_RMA_PG00_CFG_RXFIFO_RMA_3_PG00_OFFSET) + #define RTL8373_MAC_RXFIFO_RMA_PG00_CFG_RXFIFO_RMA_2_PG00_OFFSET (8) + #define RTL8373_MAC_RXFIFO_RMA_PG00_CFG_RXFIFO_RMA_2_PG00_MASK (0xF << RTL8373_MAC_RXFIFO_RMA_PG00_CFG_RXFIFO_RMA_2_PG00_OFFSET) + #define RTL8373_MAC_RXFIFO_RMA_PG00_CFG_RXFIFO_RMA_1_PG00_OFFSET (4) + #define RTL8373_MAC_RXFIFO_RMA_PG00_CFG_RXFIFO_RMA_1_PG00_MASK (0xF << RTL8373_MAC_RXFIFO_RMA_PG00_CFG_RXFIFO_RMA_1_PG00_OFFSET) + #define RTL8373_MAC_RXFIFO_RMA_PG00_CFG_RXFIFO_RMA_0_PG00_OFFSET (0) + #define RTL8373_MAC_RXFIFO_RMA_PG00_CFG_RXFIFO_RMA_0_PG00_MASK (0xF << RTL8373_MAC_RXFIFO_RMA_PG00_CFG_RXFIFO_RMA_0_PG00_OFFSET) + +#define RTL8373_MAC_RXFIFO_RMA_PG01_ADDR (0xFD0) + #define RTL8373_MAC_RXFIFO_RMA_PG01_CFG_RXFIFO_RMA_7_PG01_OFFSET (28) + #define RTL8373_MAC_RXFIFO_RMA_PG01_CFG_RXFIFO_RMA_7_PG01_MASK (0xF << RTL8373_MAC_RXFIFO_RMA_PG01_CFG_RXFIFO_RMA_7_PG01_OFFSET) + #define RTL8373_MAC_RXFIFO_RMA_PG01_CFG_RXFIFO_RMA_6_PG01_OFFSET (24) + #define RTL8373_MAC_RXFIFO_RMA_PG01_CFG_RXFIFO_RMA_6_PG01_MASK (0xF << RTL8373_MAC_RXFIFO_RMA_PG01_CFG_RXFIFO_RMA_6_PG01_OFFSET) + #define RTL8373_MAC_RXFIFO_RMA_PG01_CFG_RXFIFO_RMA_5_PG01_OFFSET (20) + #define RTL8373_MAC_RXFIFO_RMA_PG01_CFG_RXFIFO_RMA_5_PG01_MASK (0xF << RTL8373_MAC_RXFIFO_RMA_PG01_CFG_RXFIFO_RMA_5_PG01_OFFSET) + #define RTL8373_MAC_RXFIFO_RMA_PG01_CFG_RXFIFO_RMA_4_PG01_OFFSET (16) + #define RTL8373_MAC_RXFIFO_RMA_PG01_CFG_RXFIFO_RMA_4_PG01_MASK (0xF << RTL8373_MAC_RXFIFO_RMA_PG01_CFG_RXFIFO_RMA_4_PG01_OFFSET) + #define RTL8373_MAC_RXFIFO_RMA_PG01_CFG_RXFIFO_RMA_3_PG01_OFFSET (12) + #define RTL8373_MAC_RXFIFO_RMA_PG01_CFG_RXFIFO_RMA_3_PG01_MASK (0xF << RTL8373_MAC_RXFIFO_RMA_PG01_CFG_RXFIFO_RMA_3_PG01_OFFSET) + #define RTL8373_MAC_RXFIFO_RMA_PG01_CFG_RXFIFO_RMA_2_PG01_OFFSET (8) + #define RTL8373_MAC_RXFIFO_RMA_PG01_CFG_RXFIFO_RMA_2_PG01_MASK (0xF << RTL8373_MAC_RXFIFO_RMA_PG01_CFG_RXFIFO_RMA_2_PG01_OFFSET) + #define RTL8373_MAC_RXFIFO_RMA_PG01_CFG_RXFIFO_RMA_1_PG01_OFFSET (4) + #define RTL8373_MAC_RXFIFO_RMA_PG01_CFG_RXFIFO_RMA_1_PG01_MASK (0xF << RTL8373_MAC_RXFIFO_RMA_PG01_CFG_RXFIFO_RMA_1_PG01_OFFSET) + #define RTL8373_MAC_RXFIFO_RMA_PG01_CFG_RXFIFO_RMA_0_PG01_OFFSET (0) + #define RTL8373_MAC_RXFIFO_RMA_PG01_CFG_RXFIFO_RMA_0_PG01_MASK (0xF << RTL8373_MAC_RXFIFO_RMA_PG01_CFG_RXFIFO_RMA_0_PG01_OFFSET) + +#define RTL8373_MAC_RXFIFO_RMA_PG02_ADDR (0xFD4) + #define RTL8373_MAC_RXFIFO_RMA_PG02_CFG_RXFIFO_RMA_5_PG02_OFFSET (20) + #define RTL8373_MAC_RXFIFO_RMA_PG02_CFG_RXFIFO_RMA_5_PG02_MASK (0xF << RTL8373_MAC_RXFIFO_RMA_PG02_CFG_RXFIFO_RMA_5_PG02_OFFSET) + #define RTL8373_MAC_RXFIFO_RMA_PG02_CFG_RXFIFO_RMA_4_PG02_OFFSET (16) + #define RTL8373_MAC_RXFIFO_RMA_PG02_CFG_RXFIFO_RMA_4_PG02_MASK (0xF << RTL8373_MAC_RXFIFO_RMA_PG02_CFG_RXFIFO_RMA_4_PG02_OFFSET) + #define RTL8373_MAC_RXFIFO_RMA_PG02_CFG_RXFIFO_RMA_3_PG02_OFFSET (12) + #define RTL8373_MAC_RXFIFO_RMA_PG02_CFG_RXFIFO_RMA_3_PG02_MASK (0xF << RTL8373_MAC_RXFIFO_RMA_PG02_CFG_RXFIFO_RMA_3_PG02_OFFSET) + #define RTL8373_MAC_RXFIFO_RMA_PG02_CFG_RXFIFO_RMA_2_PG02_OFFSET (8) + #define RTL8373_MAC_RXFIFO_RMA_PG02_CFG_RXFIFO_RMA_2_PG02_MASK (0xF << RTL8373_MAC_RXFIFO_RMA_PG02_CFG_RXFIFO_RMA_2_PG02_OFFSET) + #define RTL8373_MAC_RXFIFO_RMA_PG02_CFG_RXFIFO_RMA_1_PG02_OFFSET (4) + #define RTL8373_MAC_RXFIFO_RMA_PG02_CFG_RXFIFO_RMA_1_PG02_MASK (0xF << RTL8373_MAC_RXFIFO_RMA_PG02_CFG_RXFIFO_RMA_1_PG02_OFFSET) + #define RTL8373_MAC_RXFIFO_RMA_PG02_CFG_RXFIFO_RMA_0_PG02_OFFSET (0) + #define RTL8373_MAC_RXFIFO_RMA_PG02_CFG_RXFIFO_RMA_0_PG02_MASK (0xF << RTL8373_MAC_RXFIFO_RMA_PG02_CFG_RXFIFO_RMA_0_PG02_OFFSET) + +#define RTL8373_MAC_RXFIFO_RMA_PG03_ADDR (0xFD8) + #define RTL8373_MAC_RXFIFO_RMA_PG03_CFG_RXFIFO_RMA_1_PG03_OFFSET (4) + #define RTL8373_MAC_RXFIFO_RMA_PG03_CFG_RXFIFO_RMA_1_PG03_MASK (0xF << RTL8373_MAC_RXFIFO_RMA_PG03_CFG_RXFIFO_RMA_1_PG03_OFFSET) + #define RTL8373_MAC_RXFIFO_RMA_PG03_CFG_RXFIFO_RMA_0_PG03_OFFSET (0) + #define RTL8373_MAC_RXFIFO_RMA_PG03_CFG_RXFIFO_RMA_0_PG03_MASK (0xF << RTL8373_MAC_RXFIFO_RMA_PG03_CFG_RXFIFO_RMA_0_PG03_OFFSET) + +#define RTL8373_MAC_RXFIFO_RMEB_ADDR (0xFDC) + #define RTL8373_MAC_RXFIFO_RMEB_CFG_RXFIFO_RMEB_PG03_OFFSET (22) + #define RTL8373_MAC_RXFIFO_RMEB_CFG_RXFIFO_RMEB_PG03_MASK (0x3 << RTL8373_MAC_RXFIFO_RMEB_CFG_RXFIFO_RMEB_PG03_OFFSET) + #define RTL8373_MAC_RXFIFO_RMEB_CFG_RXFIFO_RMEB_PG02_OFFSET (16) + #define RTL8373_MAC_RXFIFO_RMEB_CFG_RXFIFO_RMEB_PG02_MASK (0x3F << RTL8373_MAC_RXFIFO_RMEB_CFG_RXFIFO_RMEB_PG02_OFFSET) + #define RTL8373_MAC_RXFIFO_RMEB_CFG_RXFIFO_RMEB_PG01_OFFSET (8) + #define RTL8373_MAC_RXFIFO_RMEB_CFG_RXFIFO_RMEB_PG01_MASK (0xFF << RTL8373_MAC_RXFIFO_RMEB_CFG_RXFIFO_RMEB_PG01_OFFSET) + #define RTL8373_MAC_RXFIFO_RMEB_CFG_RXFIFO_RMEB_PG00_OFFSET (0) + #define RTL8373_MAC_RXFIFO_RMEB_CFG_RXFIFO_RMEB_PG00_MASK (0xFF << RTL8373_MAC_RXFIFO_RMEB_CFG_RXFIFO_RMEB_PG00_OFFSET) + +#define RTL8373_MAC_RXFIFO_RMB_PG00_ADDR (0xFE0) + #define RTL8373_MAC_RXFIFO_RMB_PG00_CFG_RXFIFO_RMB_7_PG00_OFFSET (28) + #define RTL8373_MAC_RXFIFO_RMB_PG00_CFG_RXFIFO_RMB_7_PG00_MASK (0xF << RTL8373_MAC_RXFIFO_RMB_PG00_CFG_RXFIFO_RMB_7_PG00_OFFSET) + #define RTL8373_MAC_RXFIFO_RMB_PG00_CFG_RXFIFO_RMB_6_PG00_OFFSET (24) + #define RTL8373_MAC_RXFIFO_RMB_PG00_CFG_RXFIFO_RMB_6_PG00_MASK (0xF << RTL8373_MAC_RXFIFO_RMB_PG00_CFG_RXFIFO_RMB_6_PG00_OFFSET) + #define RTL8373_MAC_RXFIFO_RMB_PG00_CFG_RXFIFO_RMB_5_PG00_OFFSET (20) + #define RTL8373_MAC_RXFIFO_RMB_PG00_CFG_RXFIFO_RMB_5_PG00_MASK (0xF << RTL8373_MAC_RXFIFO_RMB_PG00_CFG_RXFIFO_RMB_5_PG00_OFFSET) + #define RTL8373_MAC_RXFIFO_RMB_PG00_CFG_RXFIFO_RMB_4_PG00_OFFSET (16) + #define RTL8373_MAC_RXFIFO_RMB_PG00_CFG_RXFIFO_RMB_4_PG00_MASK (0xF << RTL8373_MAC_RXFIFO_RMB_PG00_CFG_RXFIFO_RMB_4_PG00_OFFSET) + #define RTL8373_MAC_RXFIFO_RMB_PG00_CFG_RXFIFO_RMB_3_PG00_OFFSET (12) + #define RTL8373_MAC_RXFIFO_RMB_PG00_CFG_RXFIFO_RMB_3_PG00_MASK (0xF << RTL8373_MAC_RXFIFO_RMB_PG00_CFG_RXFIFO_RMB_3_PG00_OFFSET) + #define RTL8373_MAC_RXFIFO_RMB_PG00_CFG_RXFIFO_RMB_2_PG00_OFFSET (8) + #define RTL8373_MAC_RXFIFO_RMB_PG00_CFG_RXFIFO_RMB_2_PG00_MASK (0xF << RTL8373_MAC_RXFIFO_RMB_PG00_CFG_RXFIFO_RMB_2_PG00_OFFSET) + #define RTL8373_MAC_RXFIFO_RMB_PG00_CFG_RXFIFO_RMB_1_PG00_OFFSET (4) + #define RTL8373_MAC_RXFIFO_RMB_PG00_CFG_RXFIFO_RMB_1_PG00_MASK (0xF << RTL8373_MAC_RXFIFO_RMB_PG00_CFG_RXFIFO_RMB_1_PG00_OFFSET) + #define RTL8373_MAC_RXFIFO_RMB_PG00_CFG_RXFIFO_RMB_0_PG00_OFFSET (0) + #define RTL8373_MAC_RXFIFO_RMB_PG00_CFG_RXFIFO_RMB_0_PG00_MASK (0xF << RTL8373_MAC_RXFIFO_RMB_PG00_CFG_RXFIFO_RMB_0_PG00_OFFSET) + +#define RTL8373_MAC_RXFIFO_RMB_PG01_ADDR (0xFE4) + #define RTL8373_MAC_RXFIFO_RMB_PG01_CFG_RXFIFO_RMB_7_PG01_OFFSET (28) + #define RTL8373_MAC_RXFIFO_RMB_PG01_CFG_RXFIFO_RMB_7_PG01_MASK (0xF << RTL8373_MAC_RXFIFO_RMB_PG01_CFG_RXFIFO_RMB_7_PG01_OFFSET) + #define RTL8373_MAC_RXFIFO_RMB_PG01_CFG_RXFIFO_RMB_6_PG01_OFFSET (24) + #define RTL8373_MAC_RXFIFO_RMB_PG01_CFG_RXFIFO_RMB_6_PG01_MASK (0xF << RTL8373_MAC_RXFIFO_RMB_PG01_CFG_RXFIFO_RMB_6_PG01_OFFSET) + #define RTL8373_MAC_RXFIFO_RMB_PG01_CFG_RXFIFO_RMB_5_PG01_OFFSET (20) + #define RTL8373_MAC_RXFIFO_RMB_PG01_CFG_RXFIFO_RMB_5_PG01_MASK (0xF << RTL8373_MAC_RXFIFO_RMB_PG01_CFG_RXFIFO_RMB_5_PG01_OFFSET) + #define RTL8373_MAC_RXFIFO_RMB_PG01_CFG_RXFIFO_RMB_4_PG01_OFFSET (16) + #define RTL8373_MAC_RXFIFO_RMB_PG01_CFG_RXFIFO_RMB_4_PG01_MASK (0xF << RTL8373_MAC_RXFIFO_RMB_PG01_CFG_RXFIFO_RMB_4_PG01_OFFSET) + #define RTL8373_MAC_RXFIFO_RMB_PG01_CFG_RXFIFO_RMB_3_PG01_OFFSET (12) + #define RTL8373_MAC_RXFIFO_RMB_PG01_CFG_RXFIFO_RMB_3_PG01_MASK (0xF << RTL8373_MAC_RXFIFO_RMB_PG01_CFG_RXFIFO_RMB_3_PG01_OFFSET) + #define RTL8373_MAC_RXFIFO_RMB_PG01_CFG_RXFIFO_RMB_2_PG01_OFFSET (8) + #define RTL8373_MAC_RXFIFO_RMB_PG01_CFG_RXFIFO_RMB_2_PG01_MASK (0xF << RTL8373_MAC_RXFIFO_RMB_PG01_CFG_RXFIFO_RMB_2_PG01_OFFSET) + #define RTL8373_MAC_RXFIFO_RMB_PG01_CFG_RXFIFO_RMB_1_PG01_OFFSET (4) + #define RTL8373_MAC_RXFIFO_RMB_PG01_CFG_RXFIFO_RMB_1_PG01_MASK (0xF << RTL8373_MAC_RXFIFO_RMB_PG01_CFG_RXFIFO_RMB_1_PG01_OFFSET) + #define RTL8373_MAC_RXFIFO_RMB_PG01_CFG_RXFIFO_RMB_0_PG01_OFFSET (0) + #define RTL8373_MAC_RXFIFO_RMB_PG01_CFG_RXFIFO_RMB_0_PG01_MASK (0xF << RTL8373_MAC_RXFIFO_RMB_PG01_CFG_RXFIFO_RMB_0_PG01_OFFSET) + +#define RTL8373_MAC_RXFIFO_RMB_PG02_ADDR (0xFE8) + #define RTL8373_MAC_RXFIFO_RMB_PG02_CFG_RXFIFO_RMB_5_PG02_OFFSET (20) + #define RTL8373_MAC_RXFIFO_RMB_PG02_CFG_RXFIFO_RMB_5_PG02_MASK (0xF << RTL8373_MAC_RXFIFO_RMB_PG02_CFG_RXFIFO_RMB_5_PG02_OFFSET) + #define RTL8373_MAC_RXFIFO_RMB_PG02_CFG_RXFIFO_RMB_4_PG02_OFFSET (16) + #define RTL8373_MAC_RXFIFO_RMB_PG02_CFG_RXFIFO_RMB_4_PG02_MASK (0xF << RTL8373_MAC_RXFIFO_RMB_PG02_CFG_RXFIFO_RMB_4_PG02_OFFSET) + #define RTL8373_MAC_RXFIFO_RMB_PG02_CFG_RXFIFO_RMB_3_PG02_OFFSET (12) + #define RTL8373_MAC_RXFIFO_RMB_PG02_CFG_RXFIFO_RMB_3_PG02_MASK (0xF << RTL8373_MAC_RXFIFO_RMB_PG02_CFG_RXFIFO_RMB_3_PG02_OFFSET) + #define RTL8373_MAC_RXFIFO_RMB_PG02_CFG_RXFIFO_RMB_2_PG02_OFFSET (8) + #define RTL8373_MAC_RXFIFO_RMB_PG02_CFG_RXFIFO_RMB_2_PG02_MASK (0xF << RTL8373_MAC_RXFIFO_RMB_PG02_CFG_RXFIFO_RMB_2_PG02_OFFSET) + #define RTL8373_MAC_RXFIFO_RMB_PG02_CFG_RXFIFO_RMB_1_PG02_OFFSET (4) + #define RTL8373_MAC_RXFIFO_RMB_PG02_CFG_RXFIFO_RMB_1_PG02_MASK (0xF << RTL8373_MAC_RXFIFO_RMB_PG02_CFG_RXFIFO_RMB_1_PG02_OFFSET) + #define RTL8373_MAC_RXFIFO_RMB_PG02_CFG_RXFIFO_RMB_0_PG02_OFFSET (0) + #define RTL8373_MAC_RXFIFO_RMB_PG02_CFG_RXFIFO_RMB_0_PG02_MASK (0xF << RTL8373_MAC_RXFIFO_RMB_PG02_CFG_RXFIFO_RMB_0_PG02_OFFSET) + +#define RTL8373_MAC_RXFIFO_RMB_PG03_ADDR (0xFEC) + #define RTL8373_MAC_RXFIFO_RMB_PG03_CFG_RXFIFO_RMB_1_PG03_OFFSET (4) + #define RTL8373_MAC_RXFIFO_RMB_PG03_CFG_RXFIFO_RMB_1_PG03_MASK (0xF << RTL8373_MAC_RXFIFO_RMB_PG03_CFG_RXFIFO_RMB_1_PG03_OFFSET) + #define RTL8373_MAC_RXFIFO_RMB_PG03_CFG_RXFIFO_RMB_0_PG03_OFFSET (0) + #define RTL8373_MAC_RXFIFO_RMB_PG03_CFG_RXFIFO_RMB_0_PG03_MASK (0xF << RTL8373_MAC_RXFIFO_RMB_PG03_CFG_RXFIFO_RMB_0_PG03_OFFSET) + +#define RTL8373_MAC_TXFIFO_LS_ADDR (0xFF0) + #define RTL8373_MAC_TXFIFO_LS_CFG_TXFIFO_LS_PG03_OFFSET (16) + #define RTL8373_MAC_TXFIFO_LS_CFG_TXFIFO_LS_PG03_MASK (0x1 << RTL8373_MAC_TXFIFO_LS_CFG_TXFIFO_LS_PG03_OFFSET) + #define RTL8373_MAC_TXFIFO_LS_CFG_TXFIFO_LS_PG02_OFFSET (10) + #define RTL8373_MAC_TXFIFO_LS_CFG_TXFIFO_LS_PG02_MASK (0x3F << RTL8373_MAC_TXFIFO_LS_CFG_TXFIFO_LS_PG02_OFFSET) + #define RTL8373_MAC_TXFIFO_LS_CFG_TXFIFO_LS_PG01_OFFSET (6) + #define RTL8373_MAC_TXFIFO_LS_CFG_TXFIFO_LS_PG01_MASK (0xF << RTL8373_MAC_TXFIFO_LS_CFG_TXFIFO_LS_PG01_OFFSET) + #define RTL8373_MAC_TXFIFO_LS_CFG_TXFIFO_LS_PG00_OFFSET (0) + #define RTL8373_MAC_TXFIFO_LS_CFG_TXFIFO_LS_PG00_MASK (0x3F << RTL8373_MAC_TXFIFO_LS_CFG_TXFIFO_LS_PG00_OFFSET) + +#define RTL8373_MAC_TXFIFO_RMEA_ADDR (0xFF4) + #define RTL8373_MAC_TXFIFO_RMEA_CFG_TXFIFO_RMEA_PG03_OFFSET (16) + #define RTL8373_MAC_TXFIFO_RMEA_CFG_TXFIFO_RMEA_PG03_MASK (0x1 << RTL8373_MAC_TXFIFO_RMEA_CFG_TXFIFO_RMEA_PG03_OFFSET) + #define RTL8373_MAC_TXFIFO_RMEA_CFG_TXFIFO_RMEA_PG02_OFFSET (10) + #define RTL8373_MAC_TXFIFO_RMEA_CFG_TXFIFO_RMEA_PG02_MASK (0x3F << RTL8373_MAC_TXFIFO_RMEA_CFG_TXFIFO_RMEA_PG02_OFFSET) + #define RTL8373_MAC_TXFIFO_RMEA_CFG_TXFIFO_RMEA_PG01_OFFSET (6) + #define RTL8373_MAC_TXFIFO_RMEA_CFG_TXFIFO_RMEA_PG01_MASK (0xF << RTL8373_MAC_TXFIFO_RMEA_CFG_TXFIFO_RMEA_PG01_OFFSET) + #define RTL8373_MAC_TXFIFO_RMEA_CFG_TXFIFO_RMEA_PG00_OFFSET (0) + #define RTL8373_MAC_TXFIFO_RMEA_CFG_TXFIFO_RMEA_PG00_MASK (0x3F << RTL8373_MAC_TXFIFO_RMEA_CFG_TXFIFO_RMEA_PG00_OFFSET) + +#define RTL8373_MAC_TXFIFO_RMA_PG00_ADDR (0xFF8) + #define RTL8373_MAC_TXFIFO_RMA_PG00_CFG_TXFIFO_RMA_5_PG00_OFFSET (20) + #define RTL8373_MAC_TXFIFO_RMA_PG00_CFG_TXFIFO_RMA_5_PG00_MASK (0xF << RTL8373_MAC_TXFIFO_RMA_PG00_CFG_TXFIFO_RMA_5_PG00_OFFSET) + #define RTL8373_MAC_TXFIFO_RMA_PG00_CFG_TXFIFO_RMA_4_PG00_OFFSET (16) + #define RTL8373_MAC_TXFIFO_RMA_PG00_CFG_TXFIFO_RMA_4_PG00_MASK (0xF << RTL8373_MAC_TXFIFO_RMA_PG00_CFG_TXFIFO_RMA_4_PG00_OFFSET) + #define RTL8373_MAC_TXFIFO_RMA_PG00_CFG_TXFIFO_RMA_3_PG00_OFFSET (12) + #define RTL8373_MAC_TXFIFO_RMA_PG00_CFG_TXFIFO_RMA_3_PG00_MASK (0xF << RTL8373_MAC_TXFIFO_RMA_PG00_CFG_TXFIFO_RMA_3_PG00_OFFSET) + #define RTL8373_MAC_TXFIFO_RMA_PG00_CFG_TXFIFO_RMA_2_PG00_OFFSET (8) + #define RTL8373_MAC_TXFIFO_RMA_PG00_CFG_TXFIFO_RMA_2_PG00_MASK (0xF << RTL8373_MAC_TXFIFO_RMA_PG00_CFG_TXFIFO_RMA_2_PG00_OFFSET) + #define RTL8373_MAC_TXFIFO_RMA_PG00_CFG_TXFIFO_RMA_1_PG00_OFFSET (4) + #define RTL8373_MAC_TXFIFO_RMA_PG00_CFG_TXFIFO_RMA_1_PG00_MASK (0xF << RTL8373_MAC_TXFIFO_RMA_PG00_CFG_TXFIFO_RMA_1_PG00_OFFSET) + #define RTL8373_MAC_TXFIFO_RMA_PG00_CFG_TXFIFO_RMA_0_PG00_OFFSET (0) + #define RTL8373_MAC_TXFIFO_RMA_PG00_CFG_TXFIFO_RMA_0_PG00_MASK (0xF << RTL8373_MAC_TXFIFO_RMA_PG00_CFG_TXFIFO_RMA_0_PG00_OFFSET) + +#define RTL8373_MAC_TXFIFO_RMA_PG01_ADDR (0xFFC) + #define RTL8373_MAC_TXFIFO_RMA_PG01_CFG_TXFIFO_RMA_3_PG01_OFFSET (12) + #define RTL8373_MAC_TXFIFO_RMA_PG01_CFG_TXFIFO_RMA_3_PG01_MASK (0xF << RTL8373_MAC_TXFIFO_RMA_PG01_CFG_TXFIFO_RMA_3_PG01_OFFSET) + #define RTL8373_MAC_TXFIFO_RMA_PG01_CFG_TXFIFO_RMA_2_PG01_OFFSET (8) + #define RTL8373_MAC_TXFIFO_RMA_PG01_CFG_TXFIFO_RMA_2_PG01_MASK (0xF << RTL8373_MAC_TXFIFO_RMA_PG01_CFG_TXFIFO_RMA_2_PG01_OFFSET) + #define RTL8373_MAC_TXFIFO_RMA_PG01_CFG_TXFIFO_RMA_1_PG01_OFFSET (4) + #define RTL8373_MAC_TXFIFO_RMA_PG01_CFG_TXFIFO_RMA_1_PG01_MASK (0xF << RTL8373_MAC_TXFIFO_RMA_PG01_CFG_TXFIFO_RMA_1_PG01_OFFSET) + #define RTL8373_MAC_TXFIFO_RMA_PG01_CFG_TXFIFO_RMA_0_PG01_OFFSET (0) + #define RTL8373_MAC_TXFIFO_RMA_PG01_CFG_TXFIFO_RMA_0_PG01_MASK (0xF << RTL8373_MAC_TXFIFO_RMA_PG01_CFG_TXFIFO_RMA_0_PG01_OFFSET) + +#define RTL8373_MAC_TXFIFO_RMA_PG02_ADDR (0x1000) + #define RTL8373_MAC_TXFIFO_RMA_PG02_CFG_TXFIFO_RMA_5_PG02_OFFSET (20) + #define RTL8373_MAC_TXFIFO_RMA_PG02_CFG_TXFIFO_RMA_5_PG02_MASK (0xF << RTL8373_MAC_TXFIFO_RMA_PG02_CFG_TXFIFO_RMA_5_PG02_OFFSET) + #define RTL8373_MAC_TXFIFO_RMA_PG02_CFG_TXFIFO_RMA_4_PG02_OFFSET (16) + #define RTL8373_MAC_TXFIFO_RMA_PG02_CFG_TXFIFO_RMA_4_PG02_MASK (0xF << RTL8373_MAC_TXFIFO_RMA_PG02_CFG_TXFIFO_RMA_4_PG02_OFFSET) + #define RTL8373_MAC_TXFIFO_RMA_PG02_CFG_TXFIFO_RMA_3_PG02_OFFSET (12) + #define RTL8373_MAC_TXFIFO_RMA_PG02_CFG_TXFIFO_RMA_3_PG02_MASK (0xF << RTL8373_MAC_TXFIFO_RMA_PG02_CFG_TXFIFO_RMA_3_PG02_OFFSET) + #define RTL8373_MAC_TXFIFO_RMA_PG02_CFG_TXFIFO_RMA_2_PG02_OFFSET (8) + #define RTL8373_MAC_TXFIFO_RMA_PG02_CFG_TXFIFO_RMA_2_PG02_MASK (0xF << RTL8373_MAC_TXFIFO_RMA_PG02_CFG_TXFIFO_RMA_2_PG02_OFFSET) + #define RTL8373_MAC_TXFIFO_RMA_PG02_CFG_TXFIFO_RMA_1_PG02_OFFSET (4) + #define RTL8373_MAC_TXFIFO_RMA_PG02_CFG_TXFIFO_RMA_1_PG02_MASK (0xF << RTL8373_MAC_TXFIFO_RMA_PG02_CFG_TXFIFO_RMA_1_PG02_OFFSET) + #define RTL8373_MAC_TXFIFO_RMA_PG02_CFG_TXFIFO_RMA_0_PG02_OFFSET (0) + #define RTL8373_MAC_TXFIFO_RMA_PG02_CFG_TXFIFO_RMA_0_PG02_MASK (0xF << RTL8373_MAC_TXFIFO_RMA_PG02_CFG_TXFIFO_RMA_0_PG02_OFFSET) + +#define RTL8373_MAC_TXFIFO_RMA_PG03_ADDR (0x1004) + #define RTL8373_MAC_TXFIFO_RMA_PG03_CFG_TXFIFO_RMA_0_PG03_OFFSET (0) + #define RTL8373_MAC_TXFIFO_RMA_PG03_CFG_TXFIFO_RMA_0_PG03_MASK (0xF << RTL8373_MAC_TXFIFO_RMA_PG03_CFG_TXFIFO_RMA_0_PG03_OFFSET) + +#define RTL8373_MAC_TXFIFO_RMEB_ADDR (0x1008) + #define RTL8373_MAC_TXFIFO_RMEB_CFG_TXFIFO_RMEB_PG03_OFFSET (16) + #define RTL8373_MAC_TXFIFO_RMEB_CFG_TXFIFO_RMEB_PG03_MASK (0x1 << RTL8373_MAC_TXFIFO_RMEB_CFG_TXFIFO_RMEB_PG03_OFFSET) + #define RTL8373_MAC_TXFIFO_RMEB_CFG_TXFIFO_RMEB_PG02_OFFSET (10) + #define RTL8373_MAC_TXFIFO_RMEB_CFG_TXFIFO_RMEB_PG02_MASK (0x3F << RTL8373_MAC_TXFIFO_RMEB_CFG_TXFIFO_RMEB_PG02_OFFSET) + #define RTL8373_MAC_TXFIFO_RMEB_CFG_TXFIFO_RMEB_PG01_OFFSET (6) + #define RTL8373_MAC_TXFIFO_RMEB_CFG_TXFIFO_RMEB_PG01_MASK (0xF << RTL8373_MAC_TXFIFO_RMEB_CFG_TXFIFO_RMEB_PG01_OFFSET) + #define RTL8373_MAC_TXFIFO_RMEB_CFG_TXFIFO_RMEB_PG00_OFFSET (0) + #define RTL8373_MAC_TXFIFO_RMEB_CFG_TXFIFO_RMEB_PG00_MASK (0x3F << RTL8373_MAC_TXFIFO_RMEB_CFG_TXFIFO_RMEB_PG00_OFFSET) + +#define RTL8373_MAC_TXFIFO_RMB_PG00_ADDR (0x100C) + #define RTL8373_MAC_TXFIFO_RMB_PG00_CFG_TXFIFO_RMB_5_PG00_OFFSET (20) + #define RTL8373_MAC_TXFIFO_RMB_PG00_CFG_TXFIFO_RMB_5_PG00_MASK (0xF << RTL8373_MAC_TXFIFO_RMB_PG00_CFG_TXFIFO_RMB_5_PG00_OFFSET) + #define RTL8373_MAC_TXFIFO_RMB_PG00_CFG_TXFIFO_RMB_4_PG00_OFFSET (16) + #define RTL8373_MAC_TXFIFO_RMB_PG00_CFG_TXFIFO_RMB_4_PG00_MASK (0xF << RTL8373_MAC_TXFIFO_RMB_PG00_CFG_TXFIFO_RMB_4_PG00_OFFSET) + #define RTL8373_MAC_TXFIFO_RMB_PG00_CFG_TXFIFO_RMB_3_PG00_OFFSET (12) + #define RTL8373_MAC_TXFIFO_RMB_PG00_CFG_TXFIFO_RMB_3_PG00_MASK (0xF << RTL8373_MAC_TXFIFO_RMB_PG00_CFG_TXFIFO_RMB_3_PG00_OFFSET) + #define RTL8373_MAC_TXFIFO_RMB_PG00_CFG_TXFIFO_RMB_2_PG00_OFFSET (8) + #define RTL8373_MAC_TXFIFO_RMB_PG00_CFG_TXFIFO_RMB_2_PG00_MASK (0xF << RTL8373_MAC_TXFIFO_RMB_PG00_CFG_TXFIFO_RMB_2_PG00_OFFSET) + #define RTL8373_MAC_TXFIFO_RMB_PG00_CFG_TXFIFO_RMB_1_PG00_OFFSET (4) + #define RTL8373_MAC_TXFIFO_RMB_PG00_CFG_TXFIFO_RMB_1_PG00_MASK (0xF << RTL8373_MAC_TXFIFO_RMB_PG00_CFG_TXFIFO_RMB_1_PG00_OFFSET) + #define RTL8373_MAC_TXFIFO_RMB_PG00_CFG_TXFIFO_RMB_0_PG00_OFFSET (0) + #define RTL8373_MAC_TXFIFO_RMB_PG00_CFG_TXFIFO_RMB_0_PG00_MASK (0xF << RTL8373_MAC_TXFIFO_RMB_PG00_CFG_TXFIFO_RMB_0_PG00_OFFSET) + +#define RTL8373_MAC_TXFIFO_RMB_PG01_ADDR (0x1010) + #define RTL8373_MAC_TXFIFO_RMB_PG01_CFG_TXFIFO_RMB_3_PG01_OFFSET (12) + #define RTL8373_MAC_TXFIFO_RMB_PG01_CFG_TXFIFO_RMB_3_PG01_MASK (0xF << RTL8373_MAC_TXFIFO_RMB_PG01_CFG_TXFIFO_RMB_3_PG01_OFFSET) + #define RTL8373_MAC_TXFIFO_RMB_PG01_CFG_TXFIFO_RMB_2_PG01_OFFSET (8) + #define RTL8373_MAC_TXFIFO_RMB_PG01_CFG_TXFIFO_RMB_2_PG01_MASK (0xF << RTL8373_MAC_TXFIFO_RMB_PG01_CFG_TXFIFO_RMB_2_PG01_OFFSET) + #define RTL8373_MAC_TXFIFO_RMB_PG01_CFG_TXFIFO_RMB_1_PG01_OFFSET (4) + #define RTL8373_MAC_TXFIFO_RMB_PG01_CFG_TXFIFO_RMB_1_PG01_MASK (0xF << RTL8373_MAC_TXFIFO_RMB_PG01_CFG_TXFIFO_RMB_1_PG01_OFFSET) + #define RTL8373_MAC_TXFIFO_RMB_PG01_CFG_TXFIFO_RMB_0_PG01_OFFSET (0) + #define RTL8373_MAC_TXFIFO_RMB_PG01_CFG_TXFIFO_RMB_0_PG01_MASK (0xF << RTL8373_MAC_TXFIFO_RMB_PG01_CFG_TXFIFO_RMB_0_PG01_OFFSET) + +#define RTL8373_MAC_TXFIFO_RMB_PG02_ADDR (0x1014) + #define RTL8373_MAC_TXFIFO_RMB_PG02_CFG_TXFIFO_RMB_5_PG02_OFFSET (20) + #define RTL8373_MAC_TXFIFO_RMB_PG02_CFG_TXFIFO_RMB_5_PG02_MASK (0xF << RTL8373_MAC_TXFIFO_RMB_PG02_CFG_TXFIFO_RMB_5_PG02_OFFSET) + #define RTL8373_MAC_TXFIFO_RMB_PG02_CFG_TXFIFO_RMB_4_PG02_OFFSET (16) + #define RTL8373_MAC_TXFIFO_RMB_PG02_CFG_TXFIFO_RMB_4_PG02_MASK (0xF << RTL8373_MAC_TXFIFO_RMB_PG02_CFG_TXFIFO_RMB_4_PG02_OFFSET) + #define RTL8373_MAC_TXFIFO_RMB_PG02_CFG_TXFIFO_RMB_3_PG02_OFFSET (12) + #define RTL8373_MAC_TXFIFO_RMB_PG02_CFG_TXFIFO_RMB_3_PG02_MASK (0xF << RTL8373_MAC_TXFIFO_RMB_PG02_CFG_TXFIFO_RMB_3_PG02_OFFSET) + #define RTL8373_MAC_TXFIFO_RMB_PG02_CFG_TXFIFO_RMB_2_PG02_OFFSET (8) + #define RTL8373_MAC_TXFIFO_RMB_PG02_CFG_TXFIFO_RMB_2_PG02_MASK (0xF << RTL8373_MAC_TXFIFO_RMB_PG02_CFG_TXFIFO_RMB_2_PG02_OFFSET) + #define RTL8373_MAC_TXFIFO_RMB_PG02_CFG_TXFIFO_RMB_1_PG02_OFFSET (4) + #define RTL8373_MAC_TXFIFO_RMB_PG02_CFG_TXFIFO_RMB_1_PG02_MASK (0xF << RTL8373_MAC_TXFIFO_RMB_PG02_CFG_TXFIFO_RMB_1_PG02_OFFSET) + #define RTL8373_MAC_TXFIFO_RMB_PG02_CFG_TXFIFO_RMB_0_PG02_OFFSET (0) + #define RTL8373_MAC_TXFIFO_RMB_PG02_CFG_TXFIFO_RMB_0_PG02_MASK (0xF << RTL8373_MAC_TXFIFO_RMB_PG02_CFG_TXFIFO_RMB_0_PG02_OFFSET) + +#define RTL8373_MAC_TXFIFO_RMB_PG03_ADDR (0x1018) + #define RTL8373_MAC_TXFIFO_RMB_PG03_CFG_TXFIFO_RMB_0_PG03_OFFSET (0) + #define RTL8373_MAC_TXFIFO_RMB_PG03_CFG_TXFIFO_RMB_0_PG03_MASK (0xF << RTL8373_MAC_TXFIFO_RMB_PG03_CFG_TXFIFO_RMB_0_PG03_OFFSET) + +#define RTL8373_CHIP_ALL_RESULT_ADDR (0x7A20) + #define RTL8373_CHIP_ALL_RESULT_ALL_BIST_DONE_OFFSET (3) + #define RTL8373_CHIP_ALL_RESULT_ALL_BIST_DONE_MASK (0x1 << RTL8373_CHIP_ALL_RESULT_ALL_BIST_DONE_OFFSET) + #define RTL8373_CHIP_ALL_RESULT_ALL_DRF_BIST_DONE_OFFSET (2) + #define RTL8373_CHIP_ALL_RESULT_ALL_DRF_BIST_DONE_MASK (0x1 << RTL8373_CHIP_ALL_RESULT_ALL_DRF_BIST_DONE_OFFSET) + #define RTL8373_CHIP_ALL_RESULT_ANY_BIST_FAIL_OFFSET (1) + #define RTL8373_CHIP_ALL_RESULT_ANY_BIST_FAIL_MASK (0x1 << RTL8373_CHIP_ALL_RESULT_ANY_BIST_FAIL_OFFSET) + #define RTL8373_CHIP_ALL_RESULT_ANY_DRF_BIST_FAIL_OFFSET (0) + #define RTL8373_CHIP_ALL_RESULT_ANY_DRF_BIST_FAIL_MASK (0x1 << RTL8373_CHIP_ALL_RESULT_ANY_DRF_BIST_FAIL_OFFSET) + +#define RTL8373_CHIP_BISR_CTRL_ADDR (0x7A24) + #define RTL8373_CHIP_BISR_CTRL_CFG_BISR_SERIAL_OFFSET (1) + #define RTL8373_CHIP_BISR_CTRL_CFG_BISR_SERIAL_MASK (0x1 << RTL8373_CHIP_BISR_CTRL_CFG_BISR_SERIAL_OFFSET) + #define RTL8373_CHIP_BISR_CTRL_CFG_BISR_MODE_OFFSET (0) + #define RTL8373_CHIP_BISR_CTRL_CFG_BISR_MODE_MASK (0x1 << RTL8373_CHIP_BISR_CTRL_CFG_BISR_MODE_OFFSET) + +#define RTL8373_GLB_MBISD_DATA_ADDR (0x7A28) + #define RTL8373_GLB_MBISD_DATA_BISD_DATA_OUT_OFFSET (0) + #define RTL8373_GLB_MBISD_DATA_BISD_DATA_OUT_MASK (0xFFFFFFFF << RTL8373_GLB_MBISD_DATA_BISD_DATA_OUT_OFFSET) + +#define RTL8373_GLB_MBISD_CFG_ADDR (0x7A2C) + #define RTL8373_GLB_MBISD_CFG_BISD_DATA_SEL_OFFSET (5) + #define RTL8373_GLB_MBISD_CFG_BISD_DATA_SEL_MASK (0x7 << RTL8373_GLB_MBISD_CFG_BISD_DATA_SEL_OFFSET) + #define RTL8373_GLB_MBISD_CFG_BISD_CLK_SEL_OFFSET (4) + #define RTL8373_GLB_MBISD_CFG_BISD_CLK_SEL_MASK (0x1 << RTL8373_GLB_MBISD_CFG_BISD_CLK_SEL_OFFSET) + #define RTL8373_GLB_MBISD_CFG_BISD_CLK_EN_OFFSET (3) + #define RTL8373_GLB_MBISD_CFG_BISD_CLK_EN_MASK (0x1 << RTL8373_GLB_MBISD_CFG_BISD_CLK_EN_OFFSET) + #define RTL8373_GLB_MBISD_CFG_BIST_DIAG_MODE_OFFSET (0) + #define RTL8373_GLB_MBISD_CFG_BIST_DIAG_MODE_MASK (0x7 << RTL8373_GLB_MBISD_CFG_BIST_DIAG_MODE_OFFSET) + +#define RTL8373_INGR_BIST_CTRL0_ADDR (0x7520) + #define RTL8373_INGR_BIST_CTRL0_CFG_CBUF_BIST_MODE_OFFSET (6) + #define RTL8373_INGR_BIST_CTRL0_CFG_CBUF_BIST_MODE_MASK (0x1 << RTL8373_INGR_BIST_CTRL0_CFG_CBUF_BIST_MODE_OFFSET) + #define RTL8373_INGR_BIST_CTRL0_CFG_PKB_BIST_MODE_2_0_OFFSET (3) + #define RTL8373_INGR_BIST_CTRL0_CFG_PKB_BIST_MODE_2_0_MASK (0x7 << RTL8373_INGR_BIST_CTRL0_CFG_PKB_BIST_MODE_2_0_OFFSET) + #define RTL8373_INGR_BIST_CTRL0_CFG_RSC_FIFO_BIST_MODE_OFFSET (2) + #define RTL8373_INGR_BIST_CTRL0_CFG_RSC_FIFO_BIST_MODE_MASK (0x1 << RTL8373_INGR_BIST_CTRL0_CFG_RSC_FIFO_BIST_MODE_OFFSET) + #define RTL8373_INGR_BIST_CTRL0_CFG_DROP_FIFO_BIST_MODE_OFFSET (1) + #define RTL8373_INGR_BIST_CTRL0_CFG_DROP_FIFO_BIST_MODE_MASK (0x1 << RTL8373_INGR_BIST_CTRL0_CFG_DROP_FIFO_BIST_MODE_OFFSET) + #define RTL8373_INGR_BIST_CTRL0_CFG_LL_BIST_MODE_OFFSET (0) + #define RTL8373_INGR_BIST_CTRL0_CFG_LL_BIST_MODE_MASK (0x1 << RTL8373_INGR_BIST_CTRL0_CFG_LL_BIST_MODE_OFFSET) + +#define RTL8373_INGR_BIST_CTRL1_ADDR (0x7524) + #define RTL8373_INGR_BIST_CTRL1_CFG_CBUF_DRF_BIST_MODE_OFFSET (6) + #define RTL8373_INGR_BIST_CTRL1_CFG_CBUF_DRF_BIST_MODE_MASK (0x1 << RTL8373_INGR_BIST_CTRL1_CFG_CBUF_DRF_BIST_MODE_OFFSET) + #define RTL8373_INGR_BIST_CTRL1_CFG_PKB_DRF_BIST_MODE_2_0_OFFSET (3) + #define RTL8373_INGR_BIST_CTRL1_CFG_PKB_DRF_BIST_MODE_2_0_MASK (0x7 << RTL8373_INGR_BIST_CTRL1_CFG_PKB_DRF_BIST_MODE_2_0_OFFSET) + #define RTL8373_INGR_BIST_CTRL1_CFG_RSC_FIFO_DRF_BIST_MODE_OFFSET (2) + #define RTL8373_INGR_BIST_CTRL1_CFG_RSC_FIFO_DRF_BIST_MODE_MASK (0x1 << RTL8373_INGR_BIST_CTRL1_CFG_RSC_FIFO_DRF_BIST_MODE_OFFSET) + #define RTL8373_INGR_BIST_CTRL1_CFG_DROP_FIFO_DRF_BIST_MODE_OFFSET (1) + #define RTL8373_INGR_BIST_CTRL1_CFG_DROP_FIFO_DRF_BIST_MODE_MASK (0x1 << RTL8373_INGR_BIST_CTRL1_CFG_DROP_FIFO_DRF_BIST_MODE_OFFSET) + #define RTL8373_INGR_BIST_CTRL1_CFG_LL_DRF_BIST_MODE_OFFSET (0) + #define RTL8373_INGR_BIST_CTRL1_CFG_LL_DRF_BIST_MODE_MASK (0x1 << RTL8373_INGR_BIST_CTRL1_CFG_LL_DRF_BIST_MODE_OFFSET) + +#define RTL8373_INGR_BIST_CTRL2_ADDR (0x7528) + #define RTL8373_INGR_BIST_CTRL2_CFG_CBUF_DRF_TEST_RESUME_OFFSET (6) + #define RTL8373_INGR_BIST_CTRL2_CFG_CBUF_DRF_TEST_RESUME_MASK (0x1 << RTL8373_INGR_BIST_CTRL2_CFG_CBUF_DRF_TEST_RESUME_OFFSET) + #define RTL8373_INGR_BIST_CTRL2_CFG_PKB_DRF_BIST_TEST_RESUME_2_0_OFFSET (3) + #define RTL8373_INGR_BIST_CTRL2_CFG_PKB_DRF_BIST_TEST_RESUME_2_0_MASK (0x7 << RTL8373_INGR_BIST_CTRL2_CFG_PKB_DRF_BIST_TEST_RESUME_2_0_OFFSET) + #define RTL8373_INGR_BIST_CTRL2_CFG_RSC_FIFO_DRF_TEST_RESUME_OFFSET (2) + #define RTL8373_INGR_BIST_CTRL2_CFG_RSC_FIFO_DRF_TEST_RESUME_MASK (0x1 << RTL8373_INGR_BIST_CTRL2_CFG_RSC_FIFO_DRF_TEST_RESUME_OFFSET) + #define RTL8373_INGR_BIST_CTRL2_CFG_DROP_FIFO_DRF_TEST_RESUME_OFFSET (1) + #define RTL8373_INGR_BIST_CTRL2_CFG_DROP_FIFO_DRF_TEST_RESUME_MASK (0x1 << RTL8373_INGR_BIST_CTRL2_CFG_DROP_FIFO_DRF_TEST_RESUME_OFFSET) + #define RTL8373_INGR_BIST_CTRL2_CFG_LL_DRF_TEST_RESUME_OFFSET (0) + #define RTL8373_INGR_BIST_CTRL2_CFG_LL_DRF_TEST_RESUME_MASK (0x1 << RTL8373_INGR_BIST_CTRL2_CFG_LL_DRF_TEST_RESUME_OFFSET) + +#define RTL8373_INGR_BIST_CTRL3_ADDR (0x752C) + #define RTL8373_INGR_BIST_CTRL3_CFG_CBUF_DRF_BIST_DYN_RD_EN_OFFSET (6) + #define RTL8373_INGR_BIST_CTRL3_CFG_CBUF_DRF_BIST_DYN_RD_EN_MASK (0x1 << RTL8373_INGR_BIST_CTRL3_CFG_CBUF_DRF_BIST_DYN_RD_EN_OFFSET) + #define RTL8373_INGR_BIST_CTRL3_CFG_PKB_DRF_BIST_DYN_RD_EN_2_0_OFFSET (3) + #define RTL8373_INGR_BIST_CTRL3_CFG_PKB_DRF_BIST_DYN_RD_EN_2_0_MASK (0x7 << RTL8373_INGR_BIST_CTRL3_CFG_PKB_DRF_BIST_DYN_RD_EN_2_0_OFFSET) + #define RTL8373_INGR_BIST_CTRL3_CFG_RSC_FIFO_DRF_BIST_DYN_RD_EN_OFFSET (2) + #define RTL8373_INGR_BIST_CTRL3_CFG_RSC_FIFO_DRF_BIST_DYN_RD_EN_MASK (0x1 << RTL8373_INGR_BIST_CTRL3_CFG_RSC_FIFO_DRF_BIST_DYN_RD_EN_OFFSET) + #define RTL8373_INGR_BIST_CTRL3_CFG_DROP_FIFO_DRF_BIST_DYN_RD_EN_OFFSET (1) + #define RTL8373_INGR_BIST_CTRL3_CFG_DROP_FIFO_DRF_BIST_DYN_RD_EN_MASK (0x1 << RTL8373_INGR_BIST_CTRL3_CFG_DROP_FIFO_DRF_BIST_DYN_RD_EN_OFFSET) + #define RTL8373_INGR_BIST_CTRL3_CFG_LL_DRF_BIST_DYN_RD_EN_OFFSET (0) + #define RTL8373_INGR_BIST_CTRL3_CFG_LL_DRF_BIST_DYN_RD_EN_MASK (0x1 << RTL8373_INGR_BIST_CTRL3_CFG_LL_DRF_BIST_DYN_RD_EN_OFFSET) + +#define RTL8373_INGR_BIST_CTRL4_ADDR (0x7530) + #define RTL8373_INGR_BIST_CTRL4_CFG_CBUF_BIST_LOOP_MODE_OFFSET (6) + #define RTL8373_INGR_BIST_CTRL4_CFG_CBUF_BIST_LOOP_MODE_MASK (0x1 << RTL8373_INGR_BIST_CTRL4_CFG_CBUF_BIST_LOOP_MODE_OFFSET) + #define RTL8373_INGR_BIST_CTRL4_CFG_PKB_BIST_LOOP_MODE_2_0_OFFSET (3) + #define RTL8373_INGR_BIST_CTRL4_CFG_PKB_BIST_LOOP_MODE_2_0_MASK (0x7 << RTL8373_INGR_BIST_CTRL4_CFG_PKB_BIST_LOOP_MODE_2_0_OFFSET) + #define RTL8373_INGR_BIST_CTRL4_CFG_RSC_FIFO_BIST_LOOP_MODE_OFFSET (2) + #define RTL8373_INGR_BIST_CTRL4_CFG_RSC_FIFO_BIST_LOOP_MODE_MASK (0x1 << RTL8373_INGR_BIST_CTRL4_CFG_RSC_FIFO_BIST_LOOP_MODE_OFFSET) + #define RTL8373_INGR_BIST_CTRL4_CFG_DROP_FIFO_BIST_LOOP_MODE_OFFSET (1) + #define RTL8373_INGR_BIST_CTRL4_CFG_DROP_FIFO_BIST_LOOP_MODE_MASK (0x1 << RTL8373_INGR_BIST_CTRL4_CFG_DROP_FIFO_BIST_LOOP_MODE_OFFSET) + #define RTL8373_INGR_BIST_CTRL4_CFG_LL_BIST_LOOP_MODE_OFFSET (0) + #define RTL8373_INGR_BIST_CTRL4_CFG_LL_BIST_LOOP_MODE_MASK (0x1 << RTL8373_INGR_BIST_CTRL4_CFG_LL_BIST_LOOP_MODE_OFFSET) + +#define RTL8373_INGR_BIST_CTRL5_ADDR (0x7534) + #define RTL8373_INGR_BIST_CTRL5_CFG_CBUF_BIST_GRP_EN_OFFSET (18) + #define RTL8373_INGR_BIST_CTRL5_CFG_CBUF_BIST_GRP_EN_MASK (0x3FF << RTL8373_INGR_BIST_CTRL5_CFG_CBUF_BIST_GRP_EN_OFFSET) + #define RTL8373_INGR_BIST_CTRL5_CFG_PKB_BIST_GRP_EN_2_0_OFFSET (0) + #define RTL8373_INGR_BIST_CTRL5_CFG_PKB_BIST_GRP_EN_2_0_MASK (0x3FFFF << RTL8373_INGR_BIST_CTRL5_CFG_PKB_BIST_GRP_EN_2_0_OFFSET) + +#define RTL8373_INGR_BIST_CTRL6_ADDR (0x7538) + #define RTL8373_INGR_BIST_CTRL6_CFG_CBUF_BIST_RSTB_OFFSET (6) + #define RTL8373_INGR_BIST_CTRL6_CFG_CBUF_BIST_RSTB_MASK (0x1 << RTL8373_INGR_BIST_CTRL6_CFG_CBUF_BIST_RSTB_OFFSET) + #define RTL8373_INGR_BIST_CTRL6_CFG_PKB_BIST_RSTB_2_0_OFFSET (3) + #define RTL8373_INGR_BIST_CTRL6_CFG_PKB_BIST_RSTB_2_0_MASK (0x7 << RTL8373_INGR_BIST_CTRL6_CFG_PKB_BIST_RSTB_2_0_OFFSET) + #define RTL8373_INGR_BIST_CTRL6_CFG_RSC_FIFO_BIST_RSTB_OFFSET (2) + #define RTL8373_INGR_BIST_CTRL6_CFG_RSC_FIFO_BIST_RSTB_MASK (0x1 << RTL8373_INGR_BIST_CTRL6_CFG_RSC_FIFO_BIST_RSTB_OFFSET) + #define RTL8373_INGR_BIST_CTRL6_CFG_DROP_FIFO_BIST_RSTB_OFFSET (1) + #define RTL8373_INGR_BIST_CTRL6_CFG_DROP_FIFO_BIST_RSTB_MASK (0x1 << RTL8373_INGR_BIST_CTRL6_CFG_DROP_FIFO_BIST_RSTB_OFFSET) + #define RTL8373_INGR_BIST_CTRL6_CFG_LL_BIST_RSTB_OFFSET (0) + #define RTL8373_INGR_BIST_CTRL6_CFG_LL_BIST_RSTB_MASK (0x1 << RTL8373_INGR_BIST_CTRL6_CFG_LL_BIST_RSTB_OFFSET) + +#define RTL8373_INGR_BIST_RSLT0_ADDR (0x753C) + #define RTL8373_INGR_BIST_RSLT0_CBUF_DRF_START_PAUSE_OFFSET (6) + #define RTL8373_INGR_BIST_RSLT0_CBUF_DRF_START_PAUSE_MASK (0x1 << RTL8373_INGR_BIST_RSLT0_CBUF_DRF_START_PAUSE_OFFSET) + #define RTL8373_INGR_BIST_RSLT0_PKB_DRF_START_PAUSE_2_0_OFFSET (3) + #define RTL8373_INGR_BIST_RSLT0_PKB_DRF_START_PAUSE_2_0_MASK (0x7 << RTL8373_INGR_BIST_RSLT0_PKB_DRF_START_PAUSE_2_0_OFFSET) + #define RTL8373_INGR_BIST_RSLT0_RSC_FIFO_DRF_START_PAUSE_OFFSET (2) + #define RTL8373_INGR_BIST_RSLT0_RSC_FIFO_DRF_START_PAUSE_MASK (0x1 << RTL8373_INGR_BIST_RSLT0_RSC_FIFO_DRF_START_PAUSE_OFFSET) + #define RTL8373_INGR_BIST_RSLT0_DROP_FIFO_DRF_START_PAUSE_OFFSET (1) + #define RTL8373_INGR_BIST_RSLT0_DROP_FIFO_DRF_START_PAUSE_MASK (0x1 << RTL8373_INGR_BIST_RSLT0_DROP_FIFO_DRF_START_PAUSE_OFFSET) + #define RTL8373_INGR_BIST_RSLT0_LL_DRF_START_PAUSE_OFFSET (0) + #define RTL8373_INGR_BIST_RSLT0_LL_DRF_START_PAUSE_MASK (0x1 << RTL8373_INGR_BIST_RSLT0_LL_DRF_START_PAUSE_OFFSET) + +#define RTL8373_INGR_BIST_RSLT1_ADDR (0x7540) + #define RTL8373_INGR_BIST_RSLT1_CBUF_BIST_DONE_OFFSET (6) + #define RTL8373_INGR_BIST_RSLT1_CBUF_BIST_DONE_MASK (0x1 << RTL8373_INGR_BIST_RSLT1_CBUF_BIST_DONE_OFFSET) + #define RTL8373_INGR_BIST_RSLT1_PKB_BIST_DONE_2_0_OFFSET (3) + #define RTL8373_INGR_BIST_RSLT1_PKB_BIST_DONE_2_0_MASK (0x7 << RTL8373_INGR_BIST_RSLT1_PKB_BIST_DONE_2_0_OFFSET) + #define RTL8373_INGR_BIST_RSLT1_RSC_FIFO_BIST_DONE_OFFSET (2) + #define RTL8373_INGR_BIST_RSLT1_RSC_FIFO_BIST_DONE_MASK (0x1 << RTL8373_INGR_BIST_RSLT1_RSC_FIFO_BIST_DONE_OFFSET) + #define RTL8373_INGR_BIST_RSLT1_DROP_FIFO_BIST_DONE_OFFSET (1) + #define RTL8373_INGR_BIST_RSLT1_DROP_FIFO_BIST_DONE_MASK (0x1 << RTL8373_INGR_BIST_RSLT1_DROP_FIFO_BIST_DONE_OFFSET) + #define RTL8373_INGR_BIST_RSLT1_LL_BIST_DONE_OFFSET (0) + #define RTL8373_INGR_BIST_RSLT1_LL_BIST_DONE_MASK (0x1 << RTL8373_INGR_BIST_RSLT1_LL_BIST_DONE_OFFSET) + +#define RTL8373_INGR_BIST_RSLT2_ADDR (0x7544) + #define RTL8373_INGR_BIST_RSLT2_CBUF_DRF_BIST_DONE_OFFSET (6) + #define RTL8373_INGR_BIST_RSLT2_CBUF_DRF_BIST_DONE_MASK (0x1 << RTL8373_INGR_BIST_RSLT2_CBUF_DRF_BIST_DONE_OFFSET) + #define RTL8373_INGR_BIST_RSLT2_PKB_DRF_BIST_DONE_2_0_OFFSET (3) + #define RTL8373_INGR_BIST_RSLT2_PKB_DRF_BIST_DONE_2_0_MASK (0x7 << RTL8373_INGR_BIST_RSLT2_PKB_DRF_BIST_DONE_2_0_OFFSET) + #define RTL8373_INGR_BIST_RSLT2_RSC_FIFO_DRF_BIST_DONE_OFFSET (2) + #define RTL8373_INGR_BIST_RSLT2_RSC_FIFO_DRF_BIST_DONE_MASK (0x1 << RTL8373_INGR_BIST_RSLT2_RSC_FIFO_DRF_BIST_DONE_OFFSET) + #define RTL8373_INGR_BIST_RSLT2_DROP_FIFO_DRF_BIST_DONE_OFFSET (1) + #define RTL8373_INGR_BIST_RSLT2_DROP_FIFO_DRF_BIST_DONE_MASK (0x1 << RTL8373_INGR_BIST_RSLT2_DROP_FIFO_DRF_BIST_DONE_OFFSET) + #define RTL8373_INGR_BIST_RSLT2_LL_DRF_BIST_DONE_OFFSET (0) + #define RTL8373_INGR_BIST_RSLT2_LL_DRF_BIST_DONE_MASK (0x1 << RTL8373_INGR_BIST_RSLT2_LL_DRF_BIST_DONE_OFFSET) + +#define RTL8373_INGR_BIST_RSLT3_ADDR (0x7548) + #define RTL8373_INGR_BIST_RSLT3_CBUF_BIST_FAIL_OFFSET (22) + #define RTL8373_INGR_BIST_RSLT3_CBUF_BIST_FAIL_MASK (0x3FF << RTL8373_INGR_BIST_RSLT3_CBUF_BIST_FAIL_OFFSET) + #define RTL8373_INGR_BIST_RSLT3_PKB_BIST_FAIL_2_0_OFFSET (4) + #define RTL8373_INGR_BIST_RSLT3_PKB_BIST_FAIL_2_0_MASK (0x3FFFF << RTL8373_INGR_BIST_RSLT3_PKB_BIST_FAIL_2_0_OFFSET) + #define RTL8373_INGR_BIST_RSLT3_RSC_FIFO_BIST_FAIL_OFFSET (2) + #define RTL8373_INGR_BIST_RSLT3_RSC_FIFO_BIST_FAIL_MASK (0x3 << RTL8373_INGR_BIST_RSLT3_RSC_FIFO_BIST_FAIL_OFFSET) + #define RTL8373_INGR_BIST_RSLT3_DROP_FIFO_BIST_FAIL_OFFSET (1) + #define RTL8373_INGR_BIST_RSLT3_DROP_FIFO_BIST_FAIL_MASK (0x1 << RTL8373_INGR_BIST_RSLT3_DROP_FIFO_BIST_FAIL_OFFSET) + #define RTL8373_INGR_BIST_RSLT3_LL_BIST_FAIL_OFFSET (0) + #define RTL8373_INGR_BIST_RSLT3_LL_BIST_FAIL_MASK (0x1 << RTL8373_INGR_BIST_RSLT3_LL_BIST_FAIL_OFFSET) + +#define RTL8373_INGR_BIST_RSLT4_ADDR (0x754C) + #define RTL8373_INGR_BIST_RSLT4_CBUF_DRF_BIST_FAIL_OFFSET (22) + #define RTL8373_INGR_BIST_RSLT4_CBUF_DRF_BIST_FAIL_MASK (0x3FF << RTL8373_INGR_BIST_RSLT4_CBUF_DRF_BIST_FAIL_OFFSET) + #define RTL8373_INGR_BIST_RSLT4_PKB_DRF_BIST_FAIL_2_0_OFFSET (4) + #define RTL8373_INGR_BIST_RSLT4_PKB_DRF_BIST_FAIL_2_0_MASK (0x3FFFF << RTL8373_INGR_BIST_RSLT4_PKB_DRF_BIST_FAIL_2_0_OFFSET) + #define RTL8373_INGR_BIST_RSLT4_RSC_FIFO_DRF_BIST_FAIL_OFFSET (2) + #define RTL8373_INGR_BIST_RSLT4_RSC_FIFO_DRF_BIST_FAIL_MASK (0x3 << RTL8373_INGR_BIST_RSLT4_RSC_FIFO_DRF_BIST_FAIL_OFFSET) + #define RTL8373_INGR_BIST_RSLT4_DROP_FIFO_DRF_BIST_FAIL_OFFSET (1) + #define RTL8373_INGR_BIST_RSLT4_DROP_FIFO_DRF_BIST_FAIL_MASK (0x1 << RTL8373_INGR_BIST_RSLT4_DROP_FIFO_DRF_BIST_FAIL_OFFSET) + #define RTL8373_INGR_BIST_RSLT4_LL_DRF_BIST_FAIL_OFFSET (0) + #define RTL8373_INGR_BIST_RSLT4_LL_DRF_BIST_FAIL_MASK (0x1 << RTL8373_INGR_BIST_RSLT4_LL_DRF_BIST_FAIL_OFFSET) + +#define RTL8373_INGR_SRAM_CTRL_0_ADDR (0x7550) + #define RTL8373_INGR_SRAM_CTRL_0_CFG_CBUF_SRAM_RME_OFFSET (27) + #define RTL8373_INGR_SRAM_CTRL_0_CFG_CBUF_SRAM_RME_MASK (0x1 << RTL8373_INGR_SRAM_CTRL_0_CFG_CBUF_SRAM_RME_OFFSET) + #define RTL8373_INGR_SRAM_CTRL_0_CFG_CBUF_SRAM_RM_OFFSET (23) + #define RTL8373_INGR_SRAM_CTRL_0_CFG_CBUF_SRAM_RM_MASK (0xF << RTL8373_INGR_SRAM_CTRL_0_CFG_CBUF_SRAM_RM_OFFSET) + #define RTL8373_INGR_SRAM_CTRL_0_CFG_CUBF_SRAM_LS_OFFSET (22) + #define RTL8373_INGR_SRAM_CTRL_0_CFG_CUBF_SRAM_LS_MASK (0x1 << RTL8373_INGR_SRAM_CTRL_0_CFG_CUBF_SRAM_LS_OFFSET) + #define RTL8373_INGR_SRAM_CTRL_0_CFG_CBUF_BIST_TEST1_OFFSET (21) + #define RTL8373_INGR_SRAM_CTRL_0_CFG_CBUF_BIST_TEST1_MASK (0x1 << RTL8373_INGR_SRAM_CTRL_0_CFG_CBUF_BIST_TEST1_OFFSET) + #define RTL8373_INGR_SRAM_CTRL_0_CFG_PKB_SRAM_RME_2_0_OFFSET (18) + #define RTL8373_INGR_SRAM_CTRL_0_CFG_PKB_SRAM_RME_2_0_MASK (0x7 << RTL8373_INGR_SRAM_CTRL_0_CFG_PKB_SRAM_RME_2_0_OFFSET) + #define RTL8373_INGR_SRAM_CTRL_0_CFG_PKB_SRAM_RM_2_0_OFFSET (6) + #define RTL8373_INGR_SRAM_CTRL_0_CFG_PKB_SRAM_RM_2_0_MASK (0xFFF << RTL8373_INGR_SRAM_CTRL_0_CFG_PKB_SRAM_RM_2_0_OFFSET) + #define RTL8373_INGR_SRAM_CTRL_0_CFG_PKB_SRAM_LS_2_0_OFFSET (3) + #define RTL8373_INGR_SRAM_CTRL_0_CFG_PKB_SRAM_LS_2_0_MASK (0x7 << RTL8373_INGR_SRAM_CTRL_0_CFG_PKB_SRAM_LS_2_0_OFFSET) + #define RTL8373_INGR_SRAM_CTRL_0_CFG_PKB_BIST_TEST1_2_0_OFFSET (0) + #define RTL8373_INGR_SRAM_CTRL_0_CFG_PKB_BIST_TEST1_2_0_MASK (0x7 << RTL8373_INGR_SRAM_CTRL_0_CFG_PKB_BIST_TEST1_2_0_OFFSET) + +#define RTL8373_INGR_SRAM_CTRL_1_ADDR (0x7554) + #define RTL8373_INGR_SRAM_CTRL_1_CFG_RSC_FIFO_SRAM_RME_OFFSET (20) + #define RTL8373_INGR_SRAM_CTRL_1_CFG_RSC_FIFO_SRAM_RME_MASK (0x1 << RTL8373_INGR_SRAM_CTRL_1_CFG_RSC_FIFO_SRAM_RME_OFFSET) + #define RTL8373_INGR_SRAM_CTRL_1_CFG_RSC_FIFO_SRAM_RM_OFFSET (16) + #define RTL8373_INGR_SRAM_CTRL_1_CFG_RSC_FIFO_SRAM_RM_MASK (0xF << RTL8373_INGR_SRAM_CTRL_1_CFG_RSC_FIFO_SRAM_RM_OFFSET) + #define RTL8373_INGR_SRAM_CTRL_1_CFG_RSC_FIFO_SRAM_LS_OFFSET (15) + #define RTL8373_INGR_SRAM_CTRL_1_CFG_RSC_FIFO_SRAM_LS_MASK (0x1 << RTL8373_INGR_SRAM_CTRL_1_CFG_RSC_FIFO_SRAM_LS_OFFSET) + #define RTL8373_INGR_SRAM_CTRL_1_CFG_RSC_FIFO_BIST_TEST1_OFFSET (14) + #define RTL8373_INGR_SRAM_CTRL_1_CFG_RSC_FIFO_BIST_TEST1_MASK (0x1 << RTL8373_INGR_SRAM_CTRL_1_CFG_RSC_FIFO_BIST_TEST1_OFFSET) + #define RTL8373_INGR_SRAM_CTRL_1_CFG_DROP_FIFO_SRAM_RME_OFFSET (13) + #define RTL8373_INGR_SRAM_CTRL_1_CFG_DROP_FIFO_SRAM_RME_MASK (0x1 << RTL8373_INGR_SRAM_CTRL_1_CFG_DROP_FIFO_SRAM_RME_OFFSET) + #define RTL8373_INGR_SRAM_CTRL_1_CFG_DROP_FIFO_SRAM_RM_OFFSET (9) + #define RTL8373_INGR_SRAM_CTRL_1_CFG_DROP_FIFO_SRAM_RM_MASK (0xF << RTL8373_INGR_SRAM_CTRL_1_CFG_DROP_FIFO_SRAM_RM_OFFSET) + #define RTL8373_INGR_SRAM_CTRL_1_CFG_DROP_FIFO_SRAM_LS_OFFSET (8) + #define RTL8373_INGR_SRAM_CTRL_1_CFG_DROP_FIFO_SRAM_LS_MASK (0x1 << RTL8373_INGR_SRAM_CTRL_1_CFG_DROP_FIFO_SRAM_LS_OFFSET) + #define RTL8373_INGR_SRAM_CTRL_1_CFG_DROP_FIFO_BIST_TEST1_OFFSET (7) + #define RTL8373_INGR_SRAM_CTRL_1_CFG_DROP_FIFO_BIST_TEST1_MASK (0x1 << RTL8373_INGR_SRAM_CTRL_1_CFG_DROP_FIFO_BIST_TEST1_OFFSET) + #define RTL8373_INGR_SRAM_CTRL_1_CFG_LL_SRAM_RME_OFFSET (6) + #define RTL8373_INGR_SRAM_CTRL_1_CFG_LL_SRAM_RME_MASK (0x1 << RTL8373_INGR_SRAM_CTRL_1_CFG_LL_SRAM_RME_OFFSET) + #define RTL8373_INGR_SRAM_CTRL_1_CFG_LL_SRAM_RM_OFFSET (2) + #define RTL8373_INGR_SRAM_CTRL_1_CFG_LL_SRAM_RM_MASK (0xF << RTL8373_INGR_SRAM_CTRL_1_CFG_LL_SRAM_RM_OFFSET) + #define RTL8373_INGR_SRAM_CTRL_1_CFG_LL_SRAM_LS_OFFSET (1) + #define RTL8373_INGR_SRAM_CTRL_1_CFG_LL_SRAM_LS_MASK (0x1 << RTL8373_INGR_SRAM_CTRL_1_CFG_LL_SRAM_LS_OFFSET) + #define RTL8373_INGR_SRAM_CTRL_1_CFG_LL_BIST_TEST1_OFFSET (0) + #define RTL8373_INGR_SRAM_CTRL_1_CFG_LL_BIST_TEST1_MASK (0x1 << RTL8373_INGR_SRAM_CTRL_1_CFG_LL_BIST_TEST1_OFFSET) + +#define RTL8373_INGR_BISR_CTRL_ADDR (0x7558) + #define RTL8373_INGR_BISR_CTRL_PKB_SECOND_RUN_EN_OFFSET (1) + #define RTL8373_INGR_BISR_CTRL_PKB_SECOND_RUN_EN_MASK (0x1 << RTL8373_INGR_BISR_CTRL_PKB_SECOND_RUN_EN_OFFSET) + #define RTL8373_INGR_BISR_CTRL_PKB_HOLD_REMAP_OFFSET (0) + #define RTL8373_INGR_BISR_CTRL_PKB_HOLD_REMAP_MASK (0x1 << RTL8373_INGR_BISR_CTRL_PKB_HOLD_REMAP_OFFSET) + +#define RTL8373_INGR_BISR_RSLT0_ADDR (0x755C) + #define RTL8373_INGR_BISR_RSLT0_BYPASS_PG_VLD_2_0_OFFSET (24) + #define RTL8373_INGR_BISR_RSLT0_BYPASS_PG_VLD_2_0_MASK (0x7 << RTL8373_INGR_BISR_RSLT0_BYPASS_PG_VLD_2_0_OFFSET) + #define RTL8373_INGR_BISR_RSLT0_BYPASS_PG_AD1_11_0_OFFSET (12) + #define RTL8373_INGR_BISR_RSLT0_BYPASS_PG_AD1_11_0_MASK (0xFFF << RTL8373_INGR_BISR_RSLT0_BYPASS_PG_AD1_11_0_OFFSET) + #define RTL8373_INGR_BISR_RSLT0_BYPASS_PG_AD0_11_0_OFFSET (0) + #define RTL8373_INGR_BISR_RSLT0_BYPASS_PG_AD0_11_0_MASK (0xFFF << RTL8373_INGR_BISR_RSLT0_BYPASS_PG_AD0_11_0_OFFSET) + +#define RTL8373_INGR_BISR_RSLT1_ADDR (0x7560) + #define RTL8373_INGR_BISR_RSLT1_BYPASS_PG_AD2_11_0_OFFSET (4) + #define RTL8373_INGR_BISR_RSLT1_BYPASS_PG_AD2_11_0_MASK (0xFFF << RTL8373_INGR_BISR_RSLT1_BYPASS_PG_AD2_11_0_OFFSET) + #define RTL8373_INGR_BISR_RSLT1_PKB_BISR_FAIL_OFFSET (3) + #define RTL8373_INGR_BISR_RSLT1_PKB_BISR_FAIL_MASK (0x1 << RTL8373_INGR_BISR_RSLT1_PKB_BISR_FAIL_OFFSET) + #define RTL8373_INGR_BISR_RSLT1_PKB_BISR_DONE_OFFSET (2) + #define RTL8373_INGR_BISR_RSLT1_PKB_BISR_DONE_MASK (0x1 << RTL8373_INGR_BISR_RSLT1_PKB_BISR_DONE_OFFSET) + #define RTL8373_INGR_BISR_RSLT1_PKB_DRF_BISR_FAIL_OFFSET (1) + #define RTL8373_INGR_BISR_RSLT1_PKB_DRF_BISR_FAIL_MASK (0x1 << RTL8373_INGR_BISR_RSLT1_PKB_DRF_BISR_FAIL_OFFSET) + #define RTL8373_INGR_BISR_RSLT1_PKB_DRF_BISR_DONE_OFFSET (0) + #define RTL8373_INGR_BISR_RSLT1_PKB_DRF_BISR_DONE_MASK (0x1 << RTL8373_INGR_BISR_RSLT1_PKB_DRF_BISR_DONE_OFFSET) + +#define RTL8373_INGR_BISR_RSLT2_ADDR (0x7564) + #define RTL8373_INGR_BISR_RSLT2_CFG_BYPASS_PG_AD2_11_0_OFFSET (1) + #define RTL8373_INGR_BISR_RSLT2_CFG_BYPASS_PG_AD2_11_0_MASK (0xFFF << RTL8373_INGR_BISR_RSLT2_CFG_BYPASS_PG_AD2_11_0_OFFSET) + #define RTL8373_INGR_BISR_RSLT2_CFG_FAIL_AD_EN_OFFSET (0) + #define RTL8373_INGR_BISR_RSLT2_CFG_FAIL_AD_EN_MASK (0x1 << RTL8373_INGR_BISR_RSLT2_CFG_FAIL_AD_EN_OFFSET) + +#define RTL8373_INGR_BISR_RSLT3_ADDR (0x7568) + #define RTL8373_INGR_BISR_RSLT3_CFG_BYPASS_PG_VLD_2_0_OFFSET (24) + #define RTL8373_INGR_BISR_RSLT3_CFG_BYPASS_PG_VLD_2_0_MASK (0x7 << RTL8373_INGR_BISR_RSLT3_CFG_BYPASS_PG_VLD_2_0_OFFSET) + #define RTL8373_INGR_BISR_RSLT3_CFG_BYPASS_PG_AD1_11_0_OFFSET (12) + #define RTL8373_INGR_BISR_RSLT3_CFG_BYPASS_PG_AD1_11_0_MASK (0xFFF << RTL8373_INGR_BISR_RSLT3_CFG_BYPASS_PG_AD1_11_0_OFFSET) + #define RTL8373_INGR_BISR_RSLT3_CFG_BYPASS_PG_AD0_11_0_OFFSET (0) + #define RTL8373_INGR_BISR_RSLT3_CFG_BYPASS_PG_AD0_11_0_MASK (0xFFF << RTL8373_INGR_BISR_RSLT3_CFG_BYPASS_PG_AD0_11_0_OFFSET) + +#define RTL8373_EGR_BIST_CTRL0_ADDR (0x4410) + #define RTL8373_EGR_BIST_CTRL0_BHSA_TEST_RESUME_OFFSET (19) + #define RTL8373_EGR_BIST_CTRL0_BHSA_TEST_RESUME_MASK (0x1 << RTL8373_EGR_BIST_CTRL0_BHSA_TEST_RESUME_OFFSET) + #define RTL8373_EGR_BIST_CTRL0_DPC_DRF_TEST_RESUME_OFFSET (18) + #define RTL8373_EGR_BIST_CTRL0_DPC_DRF_TEST_RESUME_MASK (0x1 << RTL8373_EGR_BIST_CTRL0_DPC_DRF_TEST_RESUME_OFFSET) + #define RTL8373_EGR_BIST_CTRL0_TXQ_DRF_TEST_RESUME_1_0_OFFSET (16) + #define RTL8373_EGR_BIST_CTRL0_TXQ_DRF_TEST_RESUME_1_0_MASK (0x3 << RTL8373_EGR_BIST_CTRL0_TXQ_DRF_TEST_RESUME_1_0_OFFSET) + #define RTL8373_EGR_BIST_CTRL0_BHSA_BIST_RSTB_OFFSET (2) + #define RTL8373_EGR_BIST_CTRL0_BHSA_BIST_RSTB_MASK (0x1 << RTL8373_EGR_BIST_CTRL0_BHSA_BIST_RSTB_OFFSET) + #define RTL8373_EGR_BIST_CTRL0_DPC_BIST_RSTB_OFFSET (1) + #define RTL8373_EGR_BIST_CTRL0_DPC_BIST_RSTB_MASK (0x1 << RTL8373_EGR_BIST_CTRL0_DPC_BIST_RSTB_OFFSET) + #define RTL8373_EGR_BIST_CTRL0_TXQ_BIST_RSTB_OFFSET (0) + #define RTL8373_EGR_BIST_CTRL0_TXQ_BIST_RSTB_MASK (0x1 << RTL8373_EGR_BIST_CTRL0_TXQ_BIST_RSTB_OFFSET) + +#define RTL8373_EGR_BIST_CTRL1_ADDR (0x4414) + #define RTL8373_EGR_BIST_CTRL1_BHSA_DRF_BIST_MODE_OFFSET (19) + #define RTL8373_EGR_BIST_CTRL1_BHSA_DRF_BIST_MODE_MASK (0x1 << RTL8373_EGR_BIST_CTRL1_BHSA_DRF_BIST_MODE_OFFSET) + #define RTL8373_EGR_BIST_CTRL1_DPC_DRF_BIST_MODE_OFFSET (18) + #define RTL8373_EGR_BIST_CTRL1_DPC_DRF_BIST_MODE_MASK (0x1 << RTL8373_EGR_BIST_CTRL1_DPC_DRF_BIST_MODE_OFFSET) + #define RTL8373_EGR_BIST_CTRL1_TXQ_DRF_BIST_MODE_1_0_OFFSET (16) + #define RTL8373_EGR_BIST_CTRL1_TXQ_DRF_BIST_MODE_1_0_MASK (0x3 << RTL8373_EGR_BIST_CTRL1_TXQ_DRF_BIST_MODE_1_0_OFFSET) + #define RTL8373_EGR_BIST_CTRL1_BHSA_BIST_MODE_OFFSET (3) + #define RTL8373_EGR_BIST_CTRL1_BHSA_BIST_MODE_MASK (0x1 << RTL8373_EGR_BIST_CTRL1_BHSA_BIST_MODE_OFFSET) + #define RTL8373_EGR_BIST_CTRL1_DPC_BIST_MODE_OFFSET (2) + #define RTL8373_EGR_BIST_CTRL1_DPC_BIST_MODE_MASK (0x1 << RTL8373_EGR_BIST_CTRL1_DPC_BIST_MODE_OFFSET) + #define RTL8373_EGR_BIST_CTRL1_TXQ_BIST_MODE_1_0_OFFSET (0) + #define RTL8373_EGR_BIST_CTRL1_TXQ_BIST_MODE_1_0_MASK (0x3 << RTL8373_EGR_BIST_CTRL1_TXQ_BIST_MODE_1_0_OFFSET) + +#define RTL8373_EGR_BIST_CTRL2_ADDR (0x4418) + #define RTL8373_EGR_BIST_CTRL2_HSA_LS_OFFSET (19) + #define RTL8373_EGR_BIST_CTRL2_HSA_LS_MASK (0x1 << RTL8373_EGR_BIST_CTRL2_HSA_LS_OFFSET) + #define RTL8373_EGR_BIST_CTRL2_DPC_LS_OFFSET (18) + #define RTL8373_EGR_BIST_CTRL2_DPC_LS_MASK (0x1 << RTL8373_EGR_BIST_CTRL2_DPC_LS_OFFSET) + #define RTL8373_EGR_BIST_CTRL2_TXQ_LS_OFFSET (16) + #define RTL8373_EGR_BIST_CTRL2_TXQ_LS_MASK (0x3 << RTL8373_EGR_BIST_CTRL2_TXQ_LS_OFFSET) + #define RTL8373_EGR_BIST_CTRL2_HSA_TEST1_OFFSET (3) + #define RTL8373_EGR_BIST_CTRL2_HSA_TEST1_MASK (0x1 << RTL8373_EGR_BIST_CTRL2_HSA_TEST1_OFFSET) + #define RTL8373_EGR_BIST_CTRL2_DPC_TEST1_OFFSET (2) + #define RTL8373_EGR_BIST_CTRL2_DPC_TEST1_MASK (0x1 << RTL8373_EGR_BIST_CTRL2_DPC_TEST1_OFFSET) + #define RTL8373_EGR_BIST_CTRL2_TXQ_TEST1_OFFSET (0) + #define RTL8373_EGR_BIST_CTRL2_TXQ_TEST1_MASK (0x3 << RTL8373_EGR_BIST_CTRL2_TXQ_TEST1_OFFSET) + +#define RTL8373_EGR_SRAM_CTRL3_ADDR (0x441C) + #define RTL8373_EGR_SRAM_CTRL3_BHSA_SRAM_RME_OFFSET (18) + #define RTL8373_EGR_SRAM_CTRL3_BHSA_SRAM_RME_MASK (0x1 << RTL8373_EGR_SRAM_CTRL3_BHSA_SRAM_RME_OFFSET) + #define RTL8373_EGR_SRAM_CTRL3_DPC_SRAM_RME_OFFSET (17) + #define RTL8373_EGR_SRAM_CTRL3_DPC_SRAM_RME_MASK (0x1 << RTL8373_EGR_SRAM_CTRL3_DPC_SRAM_RME_OFFSET) + #define RTL8373_EGR_SRAM_CTRL3_TXQ_SRAM_RME_OFFSET (16) + #define RTL8373_EGR_SRAM_CTRL3_TXQ_SRAM_RME_MASK (0x1 << RTL8373_EGR_SRAM_CTRL3_TXQ_SRAM_RME_OFFSET) + #define RTL8373_EGR_SRAM_CTRL3_BHSA_SRAM_RM_3_0_OFFSET (8) + #define RTL8373_EGR_SRAM_CTRL3_BHSA_SRAM_RM_3_0_MASK (0xF << RTL8373_EGR_SRAM_CTRL3_BHSA_SRAM_RM_3_0_OFFSET) + #define RTL8373_EGR_SRAM_CTRL3_DPC_SRAM_RM_3_0_OFFSET (4) + #define RTL8373_EGR_SRAM_CTRL3_DPC_SRAM_RM_3_0_MASK (0xF << RTL8373_EGR_SRAM_CTRL3_DPC_SRAM_RM_3_0_OFFSET) + #define RTL8373_EGR_SRAM_CTRL3_TXQ_SRAM_RM_3_0_OFFSET (0) + #define RTL8373_EGR_SRAM_CTRL3_TXQ_SRAM_RM_3_0_MASK (0xF << RTL8373_EGR_SRAM_CTRL3_TXQ_SRAM_RM_3_0_OFFSET) + +#define RTL8373_EGR_BIST_CTRL4_ADDR (0x4420) + #define RTL8373_EGR_BIST_CTRL4_HSA_BIST_LOOP_OFFSET (19) + #define RTL8373_EGR_BIST_CTRL4_HSA_BIST_LOOP_MASK (0x1 << RTL8373_EGR_BIST_CTRL4_HSA_BIST_LOOP_OFFSET) + #define RTL8373_EGR_BIST_CTRL4_DPC_BIST_LOOP_OFFSET (18) + #define RTL8373_EGR_BIST_CTRL4_DPC_BIST_LOOP_MASK (0x1 << RTL8373_EGR_BIST_CTRL4_DPC_BIST_LOOP_OFFSET) + #define RTL8373_EGR_BIST_CTRL4_TXQ_BIST_LOOP_1_0_OFFSET (16) + #define RTL8373_EGR_BIST_CTRL4_TXQ_BIST_LOOP_1_0_MASK (0x3 << RTL8373_EGR_BIST_CTRL4_TXQ_BIST_LOOP_1_0_OFFSET) + #define RTL8373_EGR_BIST_CTRL4_HSA_DYN_READ_OFFSET (3) + #define RTL8373_EGR_BIST_CTRL4_HSA_DYN_READ_MASK (0x1 << RTL8373_EGR_BIST_CTRL4_HSA_DYN_READ_OFFSET) + #define RTL8373_EGR_BIST_CTRL4_DPC_DYN_READ_OFFSET (2) + #define RTL8373_EGR_BIST_CTRL4_DPC_DYN_READ_MASK (0x1 << RTL8373_EGR_BIST_CTRL4_DPC_DYN_READ_OFFSET) + #define RTL8373_EGR_BIST_CTRL4_TXQ_DYN_READ_1_0_OFFSET (0) + #define RTL8373_EGR_BIST_CTRL4_TXQ_DYN_READ_1_0_MASK (0x3 << RTL8373_EGR_BIST_CTRL4_TXQ_DYN_READ_1_0_OFFSET) + +#define RTL8373_EGR_BIST_CTRL5_ADDR (0x4424) + #define RTL8373_EGR_BIST_CTRL5_HSA_BIST_GRP_EN_OFFSET (10) + #define RTL8373_EGR_BIST_CTRL5_HSA_BIST_GRP_EN_MASK (0x3 << RTL8373_EGR_BIST_CTRL5_HSA_BIST_GRP_EN_OFFSET) + #define RTL8373_EGR_BIST_CTRL5_TXQ_BIST_GRP_EN_OFFSET (0) + #define RTL8373_EGR_BIST_CTRL5_TXQ_BIST_GRP_EN_MASK (0x3FF << RTL8373_EGR_BIST_CTRL5_TXQ_BIST_GRP_EN_OFFSET) + +#define RTL8373_EGR_BIST_RSLT0_ADDR (0x4428) + #define RTL8373_EGR_BIST_RSLT0_BHSA_DRF_BIST_DONE_OFFSET (19) + #define RTL8373_EGR_BIST_RSLT0_BHSA_DRF_BIST_DONE_MASK (0x1 << RTL8373_EGR_BIST_RSLT0_BHSA_DRF_BIST_DONE_OFFSET) + #define RTL8373_EGR_BIST_RSLT0_DPC_DRF_BIST_DONE_OFFSET (18) + #define RTL8373_EGR_BIST_RSLT0_DPC_DRF_BIST_DONE_MASK (0x1 << RTL8373_EGR_BIST_RSLT0_DPC_DRF_BIST_DONE_OFFSET) + #define RTL8373_EGR_BIST_RSLT0_TXQ_DRF_BIST_DONE_1_0_OFFSET (16) + #define RTL8373_EGR_BIST_RSLT0_TXQ_DRF_BIST_DONE_1_0_MASK (0x3 << RTL8373_EGR_BIST_RSLT0_TXQ_DRF_BIST_DONE_1_0_OFFSET) + #define RTL8373_EGR_BIST_RSLT0_BHSA_BIST_DONE_OFFSET (3) + #define RTL8373_EGR_BIST_RSLT0_BHSA_BIST_DONE_MASK (0x1 << RTL8373_EGR_BIST_RSLT0_BHSA_BIST_DONE_OFFSET) + #define RTL8373_EGR_BIST_RSLT0_DPC_BIST_DONE_OFFSET (2) + #define RTL8373_EGR_BIST_RSLT0_DPC_BIST_DONE_MASK (0x1 << RTL8373_EGR_BIST_RSLT0_DPC_BIST_DONE_OFFSET) + #define RTL8373_EGR_BIST_RSLT0_TXQ_BIST_DONE_1_0_OFFSET (0) + #define RTL8373_EGR_BIST_RSLT0_TXQ_BIST_DONE_1_0_MASK (0x3 << RTL8373_EGR_BIST_RSLT0_TXQ_BIST_DONE_1_0_OFFSET) + +#define RTL8373_EGR_BIST_RSLT1_ADDR (0x442C) + #define RTL8373_EGR_BIST_RSLT1_BHSA_DRF_BIST_FAIL_OFFSET (27) + #define RTL8373_EGR_BIST_RSLT1_BHSA_DRF_BIST_FAIL_MASK (0x3 << RTL8373_EGR_BIST_RSLT1_BHSA_DRF_BIST_FAIL_OFFSET) + #define RTL8373_EGR_BIST_RSLT1_DPC_DRF_BIST_FAIL_OFFSET (26) + #define RTL8373_EGR_BIST_RSLT1_DPC_DRF_BIST_FAIL_MASK (0x1 << RTL8373_EGR_BIST_RSLT1_DPC_DRF_BIST_FAIL_OFFSET) + #define RTL8373_EGR_BIST_RSLT1_TXQ_DRF_BIST_FAIL_9_0_OFFSET (16) + #define RTL8373_EGR_BIST_RSLT1_TXQ_DRF_BIST_FAIL_9_0_MASK (0x3FF << RTL8373_EGR_BIST_RSLT1_TXQ_DRF_BIST_FAIL_9_0_OFFSET) + #define RTL8373_EGR_BIST_RSLT1_BHSA_BIST_FAIL_OFFSET (11) + #define RTL8373_EGR_BIST_RSLT1_BHSA_BIST_FAIL_MASK (0x3 << RTL8373_EGR_BIST_RSLT1_BHSA_BIST_FAIL_OFFSET) + #define RTL8373_EGR_BIST_RSLT1_DPC_BIST_FAIL_OFFSET (10) + #define RTL8373_EGR_BIST_RSLT1_DPC_BIST_FAIL_MASK (0x1 << RTL8373_EGR_BIST_RSLT1_DPC_BIST_FAIL_OFFSET) + #define RTL8373_EGR_BIST_RSLT1_TXQ_BIST_FAIL_9_0_OFFSET (0) + #define RTL8373_EGR_BIST_RSLT1_TXQ_BIST_FAIL_9_0_MASK (0x3FF << RTL8373_EGR_BIST_RSLT1_TXQ_BIST_FAIL_9_0_OFFSET) + +#define RTL8373_EGR_BIST_RSLT2_ADDR (0x4430) + #define RTL8373_EGR_BIST_RSLT2_BHSA_DRF_START_PAUSE_OFFSET (3) + #define RTL8373_EGR_BIST_RSLT2_BHSA_DRF_START_PAUSE_MASK (0x1 << RTL8373_EGR_BIST_RSLT2_BHSA_DRF_START_PAUSE_OFFSET) + #define RTL8373_EGR_BIST_RSLT2_DPC_DRF_START_PAUSE_OFFSET (2) + #define RTL8373_EGR_BIST_RSLT2_DPC_DRF_START_PAUSE_MASK (0x1 << RTL8373_EGR_BIST_RSLT2_DPC_DRF_START_PAUSE_OFFSET) + #define RTL8373_EGR_BIST_RSLT2_TXQ_DRF_START_PAUSE_1_0_OFFSET (0) + #define RTL8373_EGR_BIST_RSLT2_TXQ_DRF_START_PAUSE_1_0_MASK (0x3 << RTL8373_EGR_BIST_RSLT2_TXQ_DRF_START_PAUSE_1_0_OFFSET) + +#define RTL8373_NIC_BIST_CTRL0_ADDR (0x7820) + #define RTL8373_NIC_BIST_CTRL0_DW8051_ERAM_BIST_GRP_EN_OFFSET (0) + #define RTL8373_NIC_BIST_CTRL0_DW8051_ERAM_BIST_GRP_EN_MASK (0x7 << RTL8373_NIC_BIST_CTRL0_DW8051_ERAM_BIST_GRP_EN_OFFSET) + +#define RTL8373_NIC_BIST_CTRL1_ADDR (0x7824) + #define RTL8373_NIC_BIST_CTRL1_DW8051_ERAM_BIST_LOOP_MODE_OFFSET (19) + #define RTL8373_NIC_BIST_CTRL1_DW8051_ERAM_BIST_LOOP_MODE_MASK (0x1 << RTL8373_NIC_BIST_CTRL1_DW8051_ERAM_BIST_LOOP_MODE_OFFSET) + #define RTL8373_NIC_BIST_CTRL1_DW8051_IRAM_BIST_LOOP_MODE_OFFSET (18) + #define RTL8373_NIC_BIST_CTRL1_DW8051_IRAM_BIST_LOOP_MODE_MASK (0x1 << RTL8373_NIC_BIST_CTRL1_DW8051_IRAM_BIST_LOOP_MODE_OFFSET) + #define RTL8373_NIC_BIST_CTRL1_DW8051_IROM_BIST_LOOP_MODE_OFFSET (17) + #define RTL8373_NIC_BIST_CTRL1_DW8051_IROM_BIST_LOOP_MODE_MASK (0x1 << RTL8373_NIC_BIST_CTRL1_DW8051_IROM_BIST_LOOP_MODE_OFFSET) + #define RTL8373_NIC_BIST_CTRL1_NIC_BIST_LOOP_MODE_OFFSET (16) + #define RTL8373_NIC_BIST_CTRL1_NIC_BIST_LOOP_MODE_MASK (0x1 << RTL8373_NIC_BIST_CTRL1_NIC_BIST_LOOP_MODE_OFFSET) + #define RTL8373_NIC_BIST_CTRL1_DW8051_ERAM_DYN_READ_EN_OFFSET (3) + #define RTL8373_NIC_BIST_CTRL1_DW8051_ERAM_DYN_READ_EN_MASK (0x1 << RTL8373_NIC_BIST_CTRL1_DW8051_ERAM_DYN_READ_EN_OFFSET) + #define RTL8373_NIC_BIST_CTRL1_DW8051_IRAM_DYN_READ_EN_OFFSET (2) + #define RTL8373_NIC_BIST_CTRL1_DW8051_IRAM_DYN_READ_EN_MASK (0x1 << RTL8373_NIC_BIST_CTRL1_DW8051_IRAM_DYN_READ_EN_OFFSET) + #define RTL8373_NIC_BIST_CTRL1_DW8051_IROM_DYN_READ_EN_OFFSET (1) + #define RTL8373_NIC_BIST_CTRL1_DW8051_IROM_DYN_READ_EN_MASK (0x1 << RTL8373_NIC_BIST_CTRL1_DW8051_IROM_DYN_READ_EN_OFFSET) + #define RTL8373_NIC_BIST_CTRL1_NIC_DYN_READ_EN_OFFSET (0) + #define RTL8373_NIC_BIST_CTRL1_NIC_DYN_READ_EN_MASK (0x1 << RTL8373_NIC_BIST_CTRL1_NIC_DYN_READ_EN_OFFSET) + +#define RTL8373_NIC_BIST_CTRL2_ADDR (0x7828) + #define RTL8373_NIC_BIST_CTRL2_DW8051_ERAM_RM_2_OFFSET (26) + #define RTL8373_NIC_BIST_CTRL2_DW8051_ERAM_RM_2_MASK (0xF << RTL8373_NIC_BIST_CTRL2_DW8051_ERAM_RM_2_OFFSET) + #define RTL8373_NIC_BIST_CTRL2_DW8051_ERAM_RM_1_OFFSET (22) + #define RTL8373_NIC_BIST_CTRL2_DW8051_ERAM_RM_1_MASK (0xF << RTL8373_NIC_BIST_CTRL2_DW8051_ERAM_RM_1_OFFSET) + #define RTL8373_NIC_BIST_CTRL2_DW8051_ERAM_RM_0_OFFSET (18) + #define RTL8373_NIC_BIST_CTRL2_DW8051_ERAM_RM_0_MASK (0xF << RTL8373_NIC_BIST_CTRL2_DW8051_ERAM_RM_0_OFFSET) + #define RTL8373_NIC_BIST_CTRL2_DW8051_IRAM_RM_OFFSET (14) + #define RTL8373_NIC_BIST_CTRL2_DW8051_IRAM_RM_MASK (0xF << RTL8373_NIC_BIST_CTRL2_DW8051_IRAM_RM_OFFSET) + #define RTL8373_NIC_BIST_CTRL2_DW8051_IROM_RM_OFFSET (10) + #define RTL8373_NIC_BIST_CTRL2_DW8051_IROM_RM_MASK (0xF << RTL8373_NIC_BIST_CTRL2_DW8051_IROM_RM_OFFSET) + #define RTL8373_NIC_BIST_CTRL2_NIC_RM_OFFSET (6) + #define RTL8373_NIC_BIST_CTRL2_NIC_RM_MASK (0xF << RTL8373_NIC_BIST_CTRL2_NIC_RM_OFFSET) + #define RTL8373_NIC_BIST_CTRL2_DW8051_ERAM_RME_OFFSET (3) + #define RTL8373_NIC_BIST_CTRL2_DW8051_ERAM_RME_MASK (0x7 << RTL8373_NIC_BIST_CTRL2_DW8051_ERAM_RME_OFFSET) + #define RTL8373_NIC_BIST_CTRL2_DW8051_IRAM_RME_OFFSET (2) + #define RTL8373_NIC_BIST_CTRL2_DW8051_IRAM_RME_MASK (0x1 << RTL8373_NIC_BIST_CTRL2_DW8051_IRAM_RME_OFFSET) + #define RTL8373_NIC_BIST_CTRL2_DW8051_IROM_RME_OFFSET (1) + #define RTL8373_NIC_BIST_CTRL2_DW8051_IROM_RME_MASK (0x1 << RTL8373_NIC_BIST_CTRL2_DW8051_IROM_RME_OFFSET) + #define RTL8373_NIC_BIST_CTRL2_NIC_RME_OFFSET (0) + #define RTL8373_NIC_BIST_CTRL2_NIC_RME_MASK (0x1 << RTL8373_NIC_BIST_CTRL2_NIC_RME_OFFSET) + +#define RTL8373_NIC_BIST_CTRL3_ADDR (0x782C) + #define RTL8373_NIC_BIST_CTRL3_DW8051_ERAM_LS_OFFSET (19) + #define RTL8373_NIC_BIST_CTRL3_DW8051_ERAM_LS_MASK (0x7 << RTL8373_NIC_BIST_CTRL3_DW8051_ERAM_LS_OFFSET) + #define RTL8373_NIC_BIST_CTRL3_DW8051_IRAM_LS_OFFSET (18) + #define RTL8373_NIC_BIST_CTRL3_DW8051_IRAM_LS_MASK (0x1 << RTL8373_NIC_BIST_CTRL3_DW8051_IRAM_LS_OFFSET) + #define RTL8373_NIC_BIST_CTRL3_DW8051_IROM_LS_OFFSET (17) + #define RTL8373_NIC_BIST_CTRL3_DW8051_IROM_LS_MASK (0x1 << RTL8373_NIC_BIST_CTRL3_DW8051_IROM_LS_OFFSET) + #define RTL8373_NIC_BIST_CTRL3_NIC_LS_OFFSET (16) + #define RTL8373_NIC_BIST_CTRL3_NIC_LS_MASK (0x1 << RTL8373_NIC_BIST_CTRL3_NIC_LS_OFFSET) + #define RTL8373_NIC_BIST_CTRL3_DW8051_ERAM_TEST1_OFFSET (3) + #define RTL8373_NIC_BIST_CTRL3_DW8051_ERAM_TEST1_MASK (0x7 << RTL8373_NIC_BIST_CTRL3_DW8051_ERAM_TEST1_OFFSET) + #define RTL8373_NIC_BIST_CTRL3_DW8051_IRAM_TEST1_OFFSET (2) + #define RTL8373_NIC_BIST_CTRL3_DW8051_IRAM_TEST1_MASK (0x1 << RTL8373_NIC_BIST_CTRL3_DW8051_IRAM_TEST1_OFFSET) + #define RTL8373_NIC_BIST_CTRL3_DW8051_IROM_TEST1_OFFSET (1) + #define RTL8373_NIC_BIST_CTRL3_DW8051_IROM_TEST1_MASK (0x1 << RTL8373_NIC_BIST_CTRL3_DW8051_IROM_TEST1_OFFSET) + #define RTL8373_NIC_BIST_CTRL3_NIC_TEST1_OFFSET (0) + #define RTL8373_NIC_BIST_CTRL3_NIC_TEST1_MASK (0x1 << RTL8373_NIC_BIST_CTRL3_NIC_TEST1_OFFSET) + +#define RTL8373_NIC_BIST_CTRL4_ADDR (0x7830) + #define RTL8373_NIC_BIST_CTRL4_DW8051_ERAM_DRF_TEST_RESUME_OFFSET (19) + #define RTL8373_NIC_BIST_CTRL4_DW8051_ERAM_DRF_TEST_RESUME_MASK (0x1 << RTL8373_NIC_BIST_CTRL4_DW8051_ERAM_DRF_TEST_RESUME_OFFSET) + #define RTL8373_NIC_BIST_CTRL4_DW8051_IRAM_DRF_TEST_RESUME_OFFSET (18) + #define RTL8373_NIC_BIST_CTRL4_DW8051_IRAM_DRF_TEST_RESUME_MASK (0x1 << RTL8373_NIC_BIST_CTRL4_DW8051_IRAM_DRF_TEST_RESUME_OFFSET) + #define RTL8373_NIC_BIST_CTRL4_DW8051_IROM_DRF_TEST_RESUME_OFFSET (17) + #define RTL8373_NIC_BIST_CTRL4_DW8051_IROM_DRF_TEST_RESUME_MASK (0x1 << RTL8373_NIC_BIST_CTRL4_DW8051_IROM_DRF_TEST_RESUME_OFFSET) + #define RTL8373_NIC_BIST_CTRL4_NIC_DRF_TEST_RESUME_OFFSET (16) + #define RTL8373_NIC_BIST_CTRL4_NIC_DRF_TEST_RESUME_MASK (0x1 << RTL8373_NIC_BIST_CTRL4_NIC_DRF_TEST_RESUME_OFFSET) + #define RTL8373_NIC_BIST_CTRL4_DW8051_ERAM_BIST_RSTN_OFFSET (3) + #define RTL8373_NIC_BIST_CTRL4_DW8051_ERAM_BIST_RSTN_MASK (0x1 << RTL8373_NIC_BIST_CTRL4_DW8051_ERAM_BIST_RSTN_OFFSET) + #define RTL8373_NIC_BIST_CTRL4_DW8051_IRAM_BIST_RSTN_OFFSET (2) + #define RTL8373_NIC_BIST_CTRL4_DW8051_IRAM_BIST_RSTN_MASK (0x1 << RTL8373_NIC_BIST_CTRL4_DW8051_IRAM_BIST_RSTN_OFFSET) + #define RTL8373_NIC_BIST_CTRL4_DW8051_IROM_BIST_RSTN_OFFSET (1) + #define RTL8373_NIC_BIST_CTRL4_DW8051_IROM_BIST_RSTN_MASK (0x1 << RTL8373_NIC_BIST_CTRL4_DW8051_IROM_BIST_RSTN_OFFSET) + #define RTL8373_NIC_BIST_CTRL4_NIC_BIST_RSTN_OFFSET (0) + #define RTL8373_NIC_BIST_CTRL4_NIC_BIST_RSTN_MASK (0x1 << RTL8373_NIC_BIST_CTRL4_NIC_BIST_RSTN_OFFSET) + +#define RTL8373_NIC_BIST_CTRL5_ADDR (0x7834) + #define RTL8373_NIC_BIST_CTRL5_DW8051_DRF_ERAM_BIST_MODE_OFFSET (19) + #define RTL8373_NIC_BIST_CTRL5_DW8051_DRF_ERAM_BIST_MODE_MASK (0x1 << RTL8373_NIC_BIST_CTRL5_DW8051_DRF_ERAM_BIST_MODE_OFFSET) + #define RTL8373_NIC_BIST_CTRL5_DW8051_DRF_IRAM_BIST_MODE_OFFSET (18) + #define RTL8373_NIC_BIST_CTRL5_DW8051_DRF_IRAM_BIST_MODE_MASK (0x1 << RTL8373_NIC_BIST_CTRL5_DW8051_DRF_IRAM_BIST_MODE_OFFSET) + #define RTL8373_NIC_BIST_CTRL5_DW8051_DRF_IROM_BIST_MODE_OFFSET (17) + #define RTL8373_NIC_BIST_CTRL5_DW8051_DRF_IROM_BIST_MODE_MASK (0x1 << RTL8373_NIC_BIST_CTRL5_DW8051_DRF_IROM_BIST_MODE_OFFSET) + #define RTL8373_NIC_BIST_CTRL5_NIC_DRF_BIST_MODE_OFFSET (16) + #define RTL8373_NIC_BIST_CTRL5_NIC_DRF_BIST_MODE_MASK (0x1 << RTL8373_NIC_BIST_CTRL5_NIC_DRF_BIST_MODE_OFFSET) + #define RTL8373_NIC_BIST_CTRL5_DW8051_ERAM_BIST_MODE_OFFSET (3) + #define RTL8373_NIC_BIST_CTRL5_DW8051_ERAM_BIST_MODE_MASK (0x1 << RTL8373_NIC_BIST_CTRL5_DW8051_ERAM_BIST_MODE_OFFSET) + #define RTL8373_NIC_BIST_CTRL5_DW8051_IRAM_BIST_MODE_OFFSET (2) + #define RTL8373_NIC_BIST_CTRL5_DW8051_IRAM_BIST_MODE_MASK (0x1 << RTL8373_NIC_BIST_CTRL5_DW8051_IRAM_BIST_MODE_OFFSET) + #define RTL8373_NIC_BIST_CTRL5_DW8051_IROM_BIST_MODE_OFFSET (1) + #define RTL8373_NIC_BIST_CTRL5_DW8051_IROM_BIST_MODE_MASK (0x1 << RTL8373_NIC_BIST_CTRL5_DW8051_IROM_BIST_MODE_OFFSET) + #define RTL8373_NIC_BIST_CTRL5_NIC_BIST_MODE_OFFSET (0) + #define RTL8373_NIC_BIST_CTRL5_NIC_BIST_MODE_MASK (0x1 << RTL8373_NIC_BIST_CTRL5_NIC_BIST_MODE_OFFSET) + +#define RTL8373_NIC_BIST_RSLT0_ADDR (0x7838) + #define RTL8373_NIC_BIST_RSLT0_DW8051_ERAM_DRF_START_PAUSE_OFFSET (3) + #define RTL8373_NIC_BIST_RSLT0_DW8051_ERAM_DRF_START_PAUSE_MASK (0x1 << RTL8373_NIC_BIST_RSLT0_DW8051_ERAM_DRF_START_PAUSE_OFFSET) + #define RTL8373_NIC_BIST_RSLT0_DW8051_IRAM_DRF_START_PAUSE_OFFSET (2) + #define RTL8373_NIC_BIST_RSLT0_DW8051_IRAM_DRF_START_PAUSE_MASK (0x1 << RTL8373_NIC_BIST_RSLT0_DW8051_IRAM_DRF_START_PAUSE_OFFSET) + #define RTL8373_NIC_BIST_RSLT0_DW8051_IROM_DRF_START_PAUSE_OFFSET (1) + #define RTL8373_NIC_BIST_RSLT0_DW8051_IROM_DRF_START_PAUSE_MASK (0x1 << RTL8373_NIC_BIST_RSLT0_DW8051_IROM_DRF_START_PAUSE_OFFSET) + #define RTL8373_NIC_BIST_RSLT0_NIC_DRF_START_PAUSE_OFFSET (0) + #define RTL8373_NIC_BIST_RSLT0_NIC_DRF_START_PAUSE_MASK (0x1 << RTL8373_NIC_BIST_RSLT0_NIC_DRF_START_PAUSE_OFFSET) + +#define RTL8373_NIC_BIST_RSLT1_ADDR (0x783C) + #define RTL8373_NIC_BIST_RSLT1_DW8051_ERAM_DRF_BIST_FAIL_OFFSET (19) + #define RTL8373_NIC_BIST_RSLT1_DW8051_ERAM_DRF_BIST_FAIL_MASK (0x7 << RTL8373_NIC_BIST_RSLT1_DW8051_ERAM_DRF_BIST_FAIL_OFFSET) + #define RTL8373_NIC_BIST_RSLT1_DW8051_IRAM_DRF_BIST_FAIL_OFFSET (18) + #define RTL8373_NIC_BIST_RSLT1_DW8051_IRAM_DRF_BIST_FAIL_MASK (0x1 << RTL8373_NIC_BIST_RSLT1_DW8051_IRAM_DRF_BIST_FAIL_OFFSET) + #define RTL8373_NIC_BIST_RSLT1_DW8051_IROM_DRF_BIST_FAIL_OFFSET (17) + #define RTL8373_NIC_BIST_RSLT1_DW8051_IROM_DRF_BIST_FAIL_MASK (0x1 << RTL8373_NIC_BIST_RSLT1_DW8051_IROM_DRF_BIST_FAIL_OFFSET) + #define RTL8373_NIC_BIST_RSLT1_NIC_DRF_BIST_FAIL_OFFSET (16) + #define RTL8373_NIC_BIST_RSLT1_NIC_DRF_BIST_FAIL_MASK (0x1 << RTL8373_NIC_BIST_RSLT1_NIC_DRF_BIST_FAIL_OFFSET) + #define RTL8373_NIC_BIST_RSLT1_DW8051_ERAM_BIST_FAIL_OFFSET (3) + #define RTL8373_NIC_BIST_RSLT1_DW8051_ERAM_BIST_FAIL_MASK (0x7 << RTL8373_NIC_BIST_RSLT1_DW8051_ERAM_BIST_FAIL_OFFSET) + #define RTL8373_NIC_BIST_RSLT1_DW8051_IRAM_BIST_FAIL_OFFSET (2) + #define RTL8373_NIC_BIST_RSLT1_DW8051_IRAM_BIST_FAIL_MASK (0x1 << RTL8373_NIC_BIST_RSLT1_DW8051_IRAM_BIST_FAIL_OFFSET) + #define RTL8373_NIC_BIST_RSLT1_DW8051_IROM_BIST_FAIL_OFFSET (1) + #define RTL8373_NIC_BIST_RSLT1_DW8051_IROM_BIST_FAIL_MASK (0x1 << RTL8373_NIC_BIST_RSLT1_DW8051_IROM_BIST_FAIL_OFFSET) + #define RTL8373_NIC_BIST_RSLT1_NIC_BIST_FAIL_OFFSET (0) + #define RTL8373_NIC_BIST_RSLT1_NIC_BIST_FAIL_MASK (0x1 << RTL8373_NIC_BIST_RSLT1_NIC_BIST_FAIL_OFFSET) + +#define RTL8373_NIC_BIST_RSLT2_ADDR (0x7840) + #define RTL8373_NIC_BIST_RSLT2_DW8051_ERAM_DRF_BIST_DONE_OFFSET (19) + #define RTL8373_NIC_BIST_RSLT2_DW8051_ERAM_DRF_BIST_DONE_MASK (0x1 << RTL8373_NIC_BIST_RSLT2_DW8051_ERAM_DRF_BIST_DONE_OFFSET) + #define RTL8373_NIC_BIST_RSLT2_DW8051_IRAM_DRF_BIST_DONE_OFFSET (18) + #define RTL8373_NIC_BIST_RSLT2_DW8051_IRAM_DRF_BIST_DONE_MASK (0x1 << RTL8373_NIC_BIST_RSLT2_DW8051_IRAM_DRF_BIST_DONE_OFFSET) + #define RTL8373_NIC_BIST_RSLT2_DW8051_IROM_DRF_BIST_DONE_OFFSET (17) + #define RTL8373_NIC_BIST_RSLT2_DW8051_IROM_DRF_BIST_DONE_MASK (0x1 << RTL8373_NIC_BIST_RSLT2_DW8051_IROM_DRF_BIST_DONE_OFFSET) + #define RTL8373_NIC_BIST_RSLT2_NIC_DRF_BIST_DONE_OFFSET (16) + #define RTL8373_NIC_BIST_RSLT2_NIC_DRF_BIST_DONE_MASK (0x1 << RTL8373_NIC_BIST_RSLT2_NIC_DRF_BIST_DONE_OFFSET) + #define RTL8373_NIC_BIST_RSLT2_DW8051_ERAM_BIST_DONE_OFFSET (3) + #define RTL8373_NIC_BIST_RSLT2_DW8051_ERAM_BIST_DONE_MASK (0x1 << RTL8373_NIC_BIST_RSLT2_DW8051_ERAM_BIST_DONE_OFFSET) + #define RTL8373_NIC_BIST_RSLT2_DW8051_IRAM_BIST_DONE_OFFSET (2) + #define RTL8373_NIC_BIST_RSLT2_DW8051_IRAM_BIST_DONE_MASK (0x1 << RTL8373_NIC_BIST_RSLT2_DW8051_IRAM_BIST_DONE_OFFSET) + #define RTL8373_NIC_BIST_RSLT2_DW8051_IROM_BIST_DONE_OFFSET (1) + #define RTL8373_NIC_BIST_RSLT2_DW8051_IROM_BIST_DONE_MASK (0x1 << RTL8373_NIC_BIST_RSLT2_DW8051_IROM_BIST_DONE_OFFSET) + #define RTL8373_NIC_BIST_RSLT2_NIC_BIST_DONE_OFFSET (0) + #define RTL8373_NIC_BIST_RSLT2_NIC_BIST_DONE_MASK (0x1 << RTL8373_NIC_BIST_RSLT2_NIC_BIST_DONE_OFFSET) + +#define RTL8373_SPI_BIST_CTRL_ADDR (0x3F0) + #define RTL8373_SPI_BIST_CTRL_SPI_LS_OFFSET (12) + #define RTL8373_SPI_BIST_CTRL_SPI_LS_MASK (0x1 << RTL8373_SPI_BIST_CTRL_SPI_LS_OFFSET) + #define RTL8373_SPI_BIST_CTRL_SPI_RM_OFFSET (8) + #define RTL8373_SPI_BIST_CTRL_SPI_RM_MASK (0xF << RTL8373_SPI_BIST_CTRL_SPI_RM_OFFSET) + #define RTL8373_SPI_BIST_CTRL_SPI_RME_OFFSET (7) + #define RTL8373_SPI_BIST_CTRL_SPI_RME_MASK (0x1 << RTL8373_SPI_BIST_CTRL_SPI_RME_OFFSET) + #define RTL8373_SPI_BIST_CTRL_SPI_TEST1_OFFSET (6) + #define RTL8373_SPI_BIST_CTRL_SPI_TEST1_MASK (0x1 << RTL8373_SPI_BIST_CTRL_SPI_TEST1_OFFSET) + #define RTL8373_SPI_BIST_CTRL_SPI_BIST_LOOP_MODE_OFFSET (5) + #define RTL8373_SPI_BIST_CTRL_SPI_BIST_LOOP_MODE_MASK (0x1 << RTL8373_SPI_BIST_CTRL_SPI_BIST_LOOP_MODE_OFFSET) + #define RTL8373_SPI_BIST_CTRL_SPI_DYN_READ_EN_OFFSET (4) + #define RTL8373_SPI_BIST_CTRL_SPI_DYN_READ_EN_MASK (0x1 << RTL8373_SPI_BIST_CTRL_SPI_DYN_READ_EN_OFFSET) + #define RTL8373_SPI_BIST_CTRL_SPI_DRF_TEST_RESUME_OFFSET (3) + #define RTL8373_SPI_BIST_CTRL_SPI_DRF_TEST_RESUME_MASK (0x1 << RTL8373_SPI_BIST_CTRL_SPI_DRF_TEST_RESUME_OFFSET) + #define RTL8373_SPI_BIST_CTRL_SPI_DRF_BIST_MODE_OFFSET (2) + #define RTL8373_SPI_BIST_CTRL_SPI_DRF_BIST_MODE_MASK (0x1 << RTL8373_SPI_BIST_CTRL_SPI_DRF_BIST_MODE_OFFSET) + #define RTL8373_SPI_BIST_CTRL_SPI_BIST_MODE_OFFSET (1) + #define RTL8373_SPI_BIST_CTRL_SPI_BIST_MODE_MASK (0x1 << RTL8373_SPI_BIST_CTRL_SPI_BIST_MODE_OFFSET) + #define RTL8373_SPI_BIST_CTRL_SPI_BIST_RSTN_OFFSET (0) + #define RTL8373_SPI_BIST_CTRL_SPI_BIST_RSTN_MASK (0x1 << RTL8373_SPI_BIST_CTRL_SPI_BIST_RSTN_OFFSET) + +#define RTL8373_SPI_BIST_RSLT_ADDR (0x3F4) + #define RTL8373_SPI_BIST_RSLT_SPI_DRF_BIST_FAIL_OFFSET (4) + #define RTL8373_SPI_BIST_RSLT_SPI_DRF_BIST_FAIL_MASK (0x1 << RTL8373_SPI_BIST_RSLT_SPI_DRF_BIST_FAIL_OFFSET) + #define RTL8373_SPI_BIST_RSLT_SPI_BIST_FAIL_OFFSET (3) + #define RTL8373_SPI_BIST_RSLT_SPI_BIST_FAIL_MASK (0x1 << RTL8373_SPI_BIST_RSLT_SPI_BIST_FAIL_OFFSET) + #define RTL8373_SPI_BIST_RSLT_SPI_DRF_BIST_DONE_OFFSET (2) + #define RTL8373_SPI_BIST_RSLT_SPI_DRF_BIST_DONE_MASK (0x1 << RTL8373_SPI_BIST_RSLT_SPI_DRF_BIST_DONE_OFFSET) + #define RTL8373_SPI_BIST_RSLT_SPI_BIST_DONE_OFFSET (1) + #define RTL8373_SPI_BIST_RSLT_SPI_BIST_DONE_MASK (0x1 << RTL8373_SPI_BIST_RSLT_SPI_BIST_DONE_OFFSET) + #define RTL8373_SPI_BIST_RSLT_SPI_DRF_START_PAUSE_OFFSET (0) + #define RTL8373_SPI_BIST_RSLT_SPI_DRF_START_PAUSE_MASK (0x1 << RTL8373_SPI_BIST_RSLT_SPI_DRF_START_PAUSE_OFFSET) + +#define RTL8373_ALE_MEM_CFG_0_ADDR (0x5C70) + #define RTL8373_ALE_MEM_CFG_0_ACT_LS_OFFSET (13) + #define RTL8373_ALE_MEM_CFG_0_ACT_LS_MASK (0x1 << RTL8373_ALE_MEM_CFG_0_ACT_LS_OFFSET) + #define RTL8373_ALE_MEM_CFG_0_ACT_TEST1_OFFSET (12) + #define RTL8373_ALE_MEM_CFG_0_ACT_TEST1_MASK (0x1 << RTL8373_ALE_MEM_CFG_0_ACT_TEST1_OFFSET) + #define RTL8373_ALE_MEM_CFG_0_ACT_DVS_OFFSET (8) + #define RTL8373_ALE_MEM_CFG_0_ACT_DVS_MASK (0xF << RTL8373_ALE_MEM_CFG_0_ACT_DVS_OFFSET) + #define RTL8373_ALE_MEM_CFG_0_ACT_DVSE_OFFSET (7) + #define RTL8373_ALE_MEM_CFG_0_ACT_DVSE_MASK (0x1 << RTL8373_ALE_MEM_CFG_0_ACT_DVSE_OFFSET) + #define RTL8373_ALE_MEM_CFG_0_CVLAN_LS_OFFSET (6) + #define RTL8373_ALE_MEM_CFG_0_CVLAN_LS_MASK (0x1 << RTL8373_ALE_MEM_CFG_0_CVLAN_LS_OFFSET) + #define RTL8373_ALE_MEM_CFG_0_CVLAN_TEST1_OFFSET (5) + #define RTL8373_ALE_MEM_CFG_0_CVLAN_TEST1_MASK (0x1 << RTL8373_ALE_MEM_CFG_0_CVLAN_TEST1_OFFSET) + #define RTL8373_ALE_MEM_CFG_0_CVLAN_DVS_OFFSET (1) + #define RTL8373_ALE_MEM_CFG_0_CVLAN_DVS_MASK (0xF << RTL8373_ALE_MEM_CFG_0_CVLAN_DVS_OFFSET) + #define RTL8373_ALE_MEM_CFG_0_CVLAN_DVSE_OFFSET (0) + #define RTL8373_ALE_MEM_CFG_0_CVLAN_DVSE_MASK (0x1 << RTL8373_ALE_MEM_CFG_0_CVLAN_DVSE_OFFSET) + +#define RTL8373_ALE_MEM_CFG_1_ADDR (0x5C74) + #define RTL8373_ALE_MEM_CFG_1_L2_LS_OFFSET (24) + #define RTL8373_ALE_MEM_CFG_1_L2_LS_MASK (0xF << RTL8373_ALE_MEM_CFG_1_L2_LS_OFFSET) + #define RTL8373_ALE_MEM_CFG_1_L2_TEST1_OFFSET (20) + #define RTL8373_ALE_MEM_CFG_1_L2_TEST1_MASK (0xF << RTL8373_ALE_MEM_CFG_1_L2_TEST1_OFFSET) + #define RTL8373_ALE_MEM_CFG_1_L2_DVS_3_OFFSET (16) + #define RTL8373_ALE_MEM_CFG_1_L2_DVS_3_MASK (0xF << RTL8373_ALE_MEM_CFG_1_L2_DVS_3_OFFSET) + #define RTL8373_ALE_MEM_CFG_1_L2_DVS_2_OFFSET (12) + #define RTL8373_ALE_MEM_CFG_1_L2_DVS_2_MASK (0xF << RTL8373_ALE_MEM_CFG_1_L2_DVS_2_OFFSET) + #define RTL8373_ALE_MEM_CFG_1_L2_DVS_1_OFFSET (8) + #define RTL8373_ALE_MEM_CFG_1_L2_DVS_1_MASK (0xF << RTL8373_ALE_MEM_CFG_1_L2_DVS_1_OFFSET) + #define RTL8373_ALE_MEM_CFG_1_L2_DVS_0_OFFSET (4) + #define RTL8373_ALE_MEM_CFG_1_L2_DVS_0_MASK (0xF << RTL8373_ALE_MEM_CFG_1_L2_DVS_0_OFFSET) + #define RTL8373_ALE_MEM_CFG_1_L2_DVSE_OFFSET (0) + #define RTL8373_ALE_MEM_CFG_1_L2_DVSE_MASK (0xF << RTL8373_ALE_MEM_CFG_1_L2_DVSE_OFFSET) + +#define RTL8373_ALE_CAM_CFG_ADDR (0x5C78) + #define RTL8373_ALE_CAM_CFG_BCAM_UDS_OFFSET (25) + #define RTL8373_ALE_CAM_CFG_BCAM_UDS_MASK (0x3 << RTL8373_ALE_CAM_CFG_BCAM_UDS_OFFSET) + #define RTL8373_ALE_CAM_CFG_BCAM_MDS_OFFSET (22) + #define RTL8373_ALE_CAM_CFG_BCAM_MDS_MASK (0x7 << RTL8373_ALE_CAM_CFG_BCAM_MDS_OFFSET) + #define RTL8373_ALE_CAM_CFG_BCAM_RDS_OFFSET (18) + #define RTL8373_ALE_CAM_CFG_BCAM_RDS_MASK (0xF << RTL8373_ALE_CAM_CFG_BCAM_RDS_OFFSET) + #define RTL8373_ALE_CAM_CFG_TCAM_UDS_H_OFFSET (16) + #define RTL8373_ALE_CAM_CFG_TCAM_UDS_H_MASK (0x3 << RTL8373_ALE_CAM_CFG_TCAM_UDS_H_OFFSET) + #define RTL8373_ALE_CAM_CFG_TCAM_MDS_H_OFFSET (13) + #define RTL8373_ALE_CAM_CFG_TCAM_MDS_H_MASK (0x7 << RTL8373_ALE_CAM_CFG_TCAM_MDS_H_OFFSET) + #define RTL8373_ALE_CAM_CFG_TCAM_RDS_H_OFFSET (9) + #define RTL8373_ALE_CAM_CFG_TCAM_RDS_H_MASK (0xF << RTL8373_ALE_CAM_CFG_TCAM_RDS_H_OFFSET) + #define RTL8373_ALE_CAM_CFG_TCAM_UDS_L_OFFSET (7) + #define RTL8373_ALE_CAM_CFG_TCAM_UDS_L_MASK (0x3 << RTL8373_ALE_CAM_CFG_TCAM_UDS_L_OFFSET) + #define RTL8373_ALE_CAM_CFG_TCAM_MDS_L_OFFSET (4) + #define RTL8373_ALE_CAM_CFG_TCAM_MDS_L_MASK (0x7 << RTL8373_ALE_CAM_CFG_TCAM_MDS_L_OFFSET) + #define RTL8373_ALE_CAM_CFG_TCAM_RDS_L_OFFSET (0) + #define RTL8373_ALE_CAM_CFG_TCAM_RDS_L_MASK (0xF << RTL8373_ALE_CAM_CFG_TCAM_RDS_L_OFFSET) + +#define RTL8373_ALE_BIST_LOOP_EN_ADDR (0x5C7C) + #define RTL8373_ALE_BIST_LOOP_EN_L2_BIST_LOOP_EN_OFFSET (5) + #define RTL8373_ALE_BIST_LOOP_EN_L2_BIST_LOOP_EN_MASK (0x1 << RTL8373_ALE_BIST_LOOP_EN_L2_BIST_LOOP_EN_OFFSET) + #define RTL8373_ALE_BIST_LOOP_EN_TCAM_BIST_LOOP_EN_H_OFFSET (4) + #define RTL8373_ALE_BIST_LOOP_EN_TCAM_BIST_LOOP_EN_H_MASK (0x1 << RTL8373_ALE_BIST_LOOP_EN_TCAM_BIST_LOOP_EN_H_OFFSET) + #define RTL8373_ALE_BIST_LOOP_EN_TCAM_BIST_LOOP_EN_L_OFFSET (3) + #define RTL8373_ALE_BIST_LOOP_EN_TCAM_BIST_LOOP_EN_L_MASK (0x1 << RTL8373_ALE_BIST_LOOP_EN_TCAM_BIST_LOOP_EN_L_OFFSET) + #define RTL8373_ALE_BIST_LOOP_EN_BCAM_BIST_LOOP_EN_OFFSET (2) + #define RTL8373_ALE_BIST_LOOP_EN_BCAM_BIST_LOOP_EN_MASK (0x1 << RTL8373_ALE_BIST_LOOP_EN_BCAM_BIST_LOOP_EN_OFFSET) + #define RTL8373_ALE_BIST_LOOP_EN_ACT_BIST_LOOP_EN_OFFSET (1) + #define RTL8373_ALE_BIST_LOOP_EN_ACT_BIST_LOOP_EN_MASK (0x1 << RTL8373_ALE_BIST_LOOP_EN_ACT_BIST_LOOP_EN_OFFSET) + #define RTL8373_ALE_BIST_LOOP_EN_CVLAN_BIST_LOOP_EN_OFFSET (0) + #define RTL8373_ALE_BIST_LOOP_EN_CVLAN_BIST_LOOP_EN_MASK (0x1 << RTL8373_ALE_BIST_LOOP_EN_CVLAN_BIST_LOOP_EN_OFFSET) + +#define RTL8373_ALE_BIST_DYN_READ_EN_ADDR (0x5C80) + #define RTL8373_ALE_BIST_DYN_READ_EN_L2_BIST_DYN_READ_EN_OFFSET (5) + #define RTL8373_ALE_BIST_DYN_READ_EN_L2_BIST_DYN_READ_EN_MASK (0x1 << RTL8373_ALE_BIST_DYN_READ_EN_L2_BIST_DYN_READ_EN_OFFSET) + #define RTL8373_ALE_BIST_DYN_READ_EN_TCAM_BIST_DYN_READ_EN_H_OFFSET (4) + #define RTL8373_ALE_BIST_DYN_READ_EN_TCAM_BIST_DYN_READ_EN_H_MASK (0x1 << RTL8373_ALE_BIST_DYN_READ_EN_TCAM_BIST_DYN_READ_EN_H_OFFSET) + #define RTL8373_ALE_BIST_DYN_READ_EN_TCAM_BIST_DYN_READ_EN_L_OFFSET (3) + #define RTL8373_ALE_BIST_DYN_READ_EN_TCAM_BIST_DYN_READ_EN_L_MASK (0x1 << RTL8373_ALE_BIST_DYN_READ_EN_TCAM_BIST_DYN_READ_EN_L_OFFSET) + #define RTL8373_ALE_BIST_DYN_READ_EN_BCAM_BIST_DYN_READ_EN_OFFSET (2) + #define RTL8373_ALE_BIST_DYN_READ_EN_BCAM_BIST_DYN_READ_EN_MASK (0x1 << RTL8373_ALE_BIST_DYN_READ_EN_BCAM_BIST_DYN_READ_EN_OFFSET) + #define RTL8373_ALE_BIST_DYN_READ_EN_ACT_BIST_DYN_READ_EN_OFFSET (1) + #define RTL8373_ALE_BIST_DYN_READ_EN_ACT_BIST_DYN_READ_EN_MASK (0x1 << RTL8373_ALE_BIST_DYN_READ_EN_ACT_BIST_DYN_READ_EN_OFFSET) + #define RTL8373_ALE_BIST_DYN_READ_EN_CVLAN_BIST_DYN_READ_EN_OFFSET (0) + #define RTL8373_ALE_BIST_DYN_READ_EN_CVLAN_BIST_DYN_READ_EN_MASK (0x1 << RTL8373_ALE_BIST_DYN_READ_EN_CVLAN_BIST_DYN_READ_EN_OFFSET) + +#define RTL8373_ALE_BIST_GRP_EN_ADDR (0x5C84) + #define RTL8373_ALE_BIST_GRP_EN_L2_BIST_GRP_EN_OFFSET (5) + #define RTL8373_ALE_BIST_GRP_EN_L2_BIST_GRP_EN_MASK (0xF << RTL8373_ALE_BIST_GRP_EN_L2_BIST_GRP_EN_OFFSET) + #define RTL8373_ALE_BIST_GRP_EN_TCAM_BIST_GRP_EN_H_OFFSET (4) + #define RTL8373_ALE_BIST_GRP_EN_TCAM_BIST_GRP_EN_H_MASK (0x1 << RTL8373_ALE_BIST_GRP_EN_TCAM_BIST_GRP_EN_H_OFFSET) + #define RTL8373_ALE_BIST_GRP_EN_TCAM_BIST_GRP_EN_L_OFFSET (3) + #define RTL8373_ALE_BIST_GRP_EN_TCAM_BIST_GRP_EN_L_MASK (0x1 << RTL8373_ALE_BIST_GRP_EN_TCAM_BIST_GRP_EN_L_OFFSET) + #define RTL8373_ALE_BIST_GRP_EN_BCAM_BIST_GRP_EN_OFFSET (2) + #define RTL8373_ALE_BIST_GRP_EN_BCAM_BIST_GRP_EN_MASK (0x1 << RTL8373_ALE_BIST_GRP_EN_BCAM_BIST_GRP_EN_OFFSET) + #define RTL8373_ALE_BIST_GRP_EN_ACT_BIST_GRP_EN_OFFSET (1) + #define RTL8373_ALE_BIST_GRP_EN_ACT_BIST_GRP_EN_MASK (0x1 << RTL8373_ALE_BIST_GRP_EN_ACT_BIST_GRP_EN_OFFSET) + #define RTL8373_ALE_BIST_GRP_EN_CVLAN_BIST_GRP_EN_OFFSET (0) + #define RTL8373_ALE_BIST_GRP_EN_CVLAN_BIST_GRP_EN_MASK (0x1 << RTL8373_ALE_BIST_GRP_EN_CVLAN_BIST_GRP_EN_OFFSET) + +#define RTL8373_ALE_BIST_RSTN_ADDR (0x5C88) + #define RTL8373_ALE_BIST_RSTN_L2_BIST_RSTN_OFFSET (5) + #define RTL8373_ALE_BIST_RSTN_L2_BIST_RSTN_MASK (0x1 << RTL8373_ALE_BIST_RSTN_L2_BIST_RSTN_OFFSET) + #define RTL8373_ALE_BIST_RSTN_TCAM_BIST_RSTN_H_OFFSET (4) + #define RTL8373_ALE_BIST_RSTN_TCAM_BIST_RSTN_H_MASK (0x1 << RTL8373_ALE_BIST_RSTN_TCAM_BIST_RSTN_H_OFFSET) + #define RTL8373_ALE_BIST_RSTN_TCAM_BIST_RSTN_L_OFFSET (3) + #define RTL8373_ALE_BIST_RSTN_TCAM_BIST_RSTN_L_MASK (0x1 << RTL8373_ALE_BIST_RSTN_TCAM_BIST_RSTN_L_OFFSET) + #define RTL8373_ALE_BIST_RSTN_BCAM_BIST_RSTN_OFFSET (2) + #define RTL8373_ALE_BIST_RSTN_BCAM_BIST_RSTN_MASK (0x1 << RTL8373_ALE_BIST_RSTN_BCAM_BIST_RSTN_OFFSET) + #define RTL8373_ALE_BIST_RSTN_ACT_BIST_RSTN_OFFSET (1) + #define RTL8373_ALE_BIST_RSTN_ACT_BIST_RSTN_MASK (0x1 << RTL8373_ALE_BIST_RSTN_ACT_BIST_RSTN_OFFSET) + #define RTL8373_ALE_BIST_RSTN_CVLAN_BIST_RSTN_OFFSET (0) + #define RTL8373_ALE_BIST_RSTN_CVLAN_BIST_RSTN_MASK (0x1 << RTL8373_ALE_BIST_RSTN_CVLAN_BIST_RSTN_OFFSET) + +#define RTL8373_ALE_BIST_MODE_ADDR (0x5C8C) + #define RTL8373_ALE_BIST_MODE_L2_BIST_MODE_OFFSET (5) + #define RTL8373_ALE_BIST_MODE_L2_BIST_MODE_MASK (0x1 << RTL8373_ALE_BIST_MODE_L2_BIST_MODE_OFFSET) + #define RTL8373_ALE_BIST_MODE_TCAM_BIST_MODE_H_OFFSET (4) + #define RTL8373_ALE_BIST_MODE_TCAM_BIST_MODE_H_MASK (0x1 << RTL8373_ALE_BIST_MODE_TCAM_BIST_MODE_H_OFFSET) + #define RTL8373_ALE_BIST_MODE_TCAM_BIST_MODE_L_OFFSET (3) + #define RTL8373_ALE_BIST_MODE_TCAM_BIST_MODE_L_MASK (0x1 << RTL8373_ALE_BIST_MODE_TCAM_BIST_MODE_L_OFFSET) + #define RTL8373_ALE_BIST_MODE_BCAM_BIST_MODE_OFFSET (2) + #define RTL8373_ALE_BIST_MODE_BCAM_BIST_MODE_MASK (0x1 << RTL8373_ALE_BIST_MODE_BCAM_BIST_MODE_OFFSET) + #define RTL8373_ALE_BIST_MODE_ACT_BIST_MODE_OFFSET (1) + #define RTL8373_ALE_BIST_MODE_ACT_BIST_MODE_MASK (0x1 << RTL8373_ALE_BIST_MODE_ACT_BIST_MODE_OFFSET) + #define RTL8373_ALE_BIST_MODE_CVLAN_BIST_MODE_OFFSET (0) + #define RTL8373_ALE_BIST_MODE_CVLAN_BIST_MODE_MASK (0x1 << RTL8373_ALE_BIST_MODE_CVLAN_BIST_MODE_OFFSET) + +#define RTL8373_ALE_BIST_DONE_ADDR (0x5C90) + #define RTL8373_ALE_BIST_DONE_L2_BIST_DONE_OFFSET (5) + #define RTL8373_ALE_BIST_DONE_L2_BIST_DONE_MASK (0x1 << RTL8373_ALE_BIST_DONE_L2_BIST_DONE_OFFSET) + #define RTL8373_ALE_BIST_DONE_TCAM_BIST_DONE_H_OFFSET (4) + #define RTL8373_ALE_BIST_DONE_TCAM_BIST_DONE_H_MASK (0x1 << RTL8373_ALE_BIST_DONE_TCAM_BIST_DONE_H_OFFSET) + #define RTL8373_ALE_BIST_DONE_TCAM_BIST_DONE_L_OFFSET (3) + #define RTL8373_ALE_BIST_DONE_TCAM_BIST_DONE_L_MASK (0x1 << RTL8373_ALE_BIST_DONE_TCAM_BIST_DONE_L_OFFSET) + #define RTL8373_ALE_BIST_DONE_BCAM_BIST_DONE_OFFSET (2) + #define RTL8373_ALE_BIST_DONE_BCAM_BIST_DONE_MASK (0x1 << RTL8373_ALE_BIST_DONE_BCAM_BIST_DONE_OFFSET) + #define RTL8373_ALE_BIST_DONE_ACT_BIST_DONE_OFFSET (1) + #define RTL8373_ALE_BIST_DONE_ACT_BIST_DONE_MASK (0x1 << RTL8373_ALE_BIST_DONE_ACT_BIST_DONE_OFFSET) + #define RTL8373_ALE_BIST_DONE_CVLAN_BIST_DONE_OFFSET (0) + #define RTL8373_ALE_BIST_DONE_CVLAN_BIST_DONE_MASK (0x1 << RTL8373_ALE_BIST_DONE_CVLAN_BIST_DONE_OFFSET) + +#define RTL8373_ALE_BIST_FAIL_ADDR (0x5C94) + #define RTL8373_ALE_BIST_FAIL_L2_BIST_FAIL_OFFSET (5) + #define RTL8373_ALE_BIST_FAIL_L2_BIST_FAIL_MASK (0xF << RTL8373_ALE_BIST_FAIL_L2_BIST_FAIL_OFFSET) + #define RTL8373_ALE_BIST_FAIL_TCAM_BIST_FAIL_H_OFFSET (4) + #define RTL8373_ALE_BIST_FAIL_TCAM_BIST_FAIL_H_MASK (0x1 << RTL8373_ALE_BIST_FAIL_TCAM_BIST_FAIL_H_OFFSET) + #define RTL8373_ALE_BIST_FAIL_TCAM_BIST_FAIL_L_OFFSET (3) + #define RTL8373_ALE_BIST_FAIL_TCAM_BIST_FAIL_L_MASK (0x1 << RTL8373_ALE_BIST_FAIL_TCAM_BIST_FAIL_L_OFFSET) + #define RTL8373_ALE_BIST_FAIL_BCAM_BIST_FAIL_OFFSET (2) + #define RTL8373_ALE_BIST_FAIL_BCAM_BIST_FAIL_MASK (0x1 << RTL8373_ALE_BIST_FAIL_BCAM_BIST_FAIL_OFFSET) + #define RTL8373_ALE_BIST_FAIL_ACT_BIST_FAIL_OFFSET (1) + #define RTL8373_ALE_BIST_FAIL_ACT_BIST_FAIL_MASK (0x1 << RTL8373_ALE_BIST_FAIL_ACT_BIST_FAIL_OFFSET) + #define RTL8373_ALE_BIST_FAIL_CVLAN_BIST_FAIL_OFFSET (0) + #define RTL8373_ALE_BIST_FAIL_CVLAN_BIST_FAIL_MASK (0x1 << RTL8373_ALE_BIST_FAIL_CVLAN_BIST_FAIL_OFFSET) + +#define RTL8373_ALE_DRF_MODE_ADDR (0x5C98) + #define RTL8373_ALE_DRF_MODE_L2_DRF_MODE_OFFSET (5) + #define RTL8373_ALE_DRF_MODE_L2_DRF_MODE_MASK (0x1 << RTL8373_ALE_DRF_MODE_L2_DRF_MODE_OFFSET) + #define RTL8373_ALE_DRF_MODE_TCAM_DRF_MODE_H_OFFSET (4) + #define RTL8373_ALE_DRF_MODE_TCAM_DRF_MODE_H_MASK (0x1 << RTL8373_ALE_DRF_MODE_TCAM_DRF_MODE_H_OFFSET) + #define RTL8373_ALE_DRF_MODE_TCAM_DRF_MODE_L_OFFSET (3) + #define RTL8373_ALE_DRF_MODE_TCAM_DRF_MODE_L_MASK (0x1 << RTL8373_ALE_DRF_MODE_TCAM_DRF_MODE_L_OFFSET) + #define RTL8373_ALE_DRF_MODE_BCAM_DRF_MODE_OFFSET (2) + #define RTL8373_ALE_DRF_MODE_BCAM_DRF_MODE_MASK (0x1 << RTL8373_ALE_DRF_MODE_BCAM_DRF_MODE_OFFSET) + #define RTL8373_ALE_DRF_MODE_ACT_DRF_MODE_OFFSET (1) + #define RTL8373_ALE_DRF_MODE_ACT_DRF_MODE_MASK (0x1 << RTL8373_ALE_DRF_MODE_ACT_DRF_MODE_OFFSET) + #define RTL8373_ALE_DRF_MODE_CVLAN_DRF_MODE_OFFSET (0) + #define RTL8373_ALE_DRF_MODE_CVLAN_DRF_MODE_MASK (0x1 << RTL8373_ALE_DRF_MODE_CVLAN_DRF_MODE_OFFSET) + +#define RTL8373_ALE_DRF_PAUSE_ADDR (0x5C9C) + #define RTL8373_ALE_DRF_PAUSE_L2_DRF_PAUSE_OFFSET (5) + #define RTL8373_ALE_DRF_PAUSE_L2_DRF_PAUSE_MASK (0x1 << RTL8373_ALE_DRF_PAUSE_L2_DRF_PAUSE_OFFSET) + #define RTL8373_ALE_DRF_PAUSE_TCAM_DRF_PAUSE_H_OFFSET (4) + #define RTL8373_ALE_DRF_PAUSE_TCAM_DRF_PAUSE_H_MASK (0x1 << RTL8373_ALE_DRF_PAUSE_TCAM_DRF_PAUSE_H_OFFSET) + #define RTL8373_ALE_DRF_PAUSE_TCAM_DRF_PAUSE_L_OFFSET (3) + #define RTL8373_ALE_DRF_PAUSE_TCAM_DRF_PAUSE_L_MASK (0x1 << RTL8373_ALE_DRF_PAUSE_TCAM_DRF_PAUSE_L_OFFSET) + #define RTL8373_ALE_DRF_PAUSE_BCAM_DRF_PAUSE_OFFSET (2) + #define RTL8373_ALE_DRF_PAUSE_BCAM_DRF_PAUSE_MASK (0x1 << RTL8373_ALE_DRF_PAUSE_BCAM_DRF_PAUSE_OFFSET) + #define RTL8373_ALE_DRF_PAUSE_ACT_DRF_PAUSE_OFFSET (1) + #define RTL8373_ALE_DRF_PAUSE_ACT_DRF_PAUSE_MASK (0x1 << RTL8373_ALE_DRF_PAUSE_ACT_DRF_PAUSE_OFFSET) + #define RTL8373_ALE_DRF_PAUSE_CVLAN_DRF_PAUSE_OFFSET (0) + #define RTL8373_ALE_DRF_PAUSE_CVLAN_DRF_PAUSE_MASK (0x1 << RTL8373_ALE_DRF_PAUSE_CVLAN_DRF_PAUSE_OFFSET) + +#define RTL8373_ALE_DRF_RESUME_ADDR (0x5CA0) + #define RTL8373_ALE_DRF_RESUME_L2_DRF_RESUME_OFFSET (5) + #define RTL8373_ALE_DRF_RESUME_L2_DRF_RESUME_MASK (0x1 << RTL8373_ALE_DRF_RESUME_L2_DRF_RESUME_OFFSET) + #define RTL8373_ALE_DRF_RESUME_TCAM_DRF_RESUME_H_OFFSET (4) + #define RTL8373_ALE_DRF_RESUME_TCAM_DRF_RESUME_H_MASK (0x1 << RTL8373_ALE_DRF_RESUME_TCAM_DRF_RESUME_H_OFFSET) + #define RTL8373_ALE_DRF_RESUME_TCAM_DRF_RESUME_L_OFFSET (3) + #define RTL8373_ALE_DRF_RESUME_TCAM_DRF_RESUME_L_MASK (0x1 << RTL8373_ALE_DRF_RESUME_TCAM_DRF_RESUME_L_OFFSET) + #define RTL8373_ALE_DRF_RESUME_BCAM_DRF_RESUME_OFFSET (2) + #define RTL8373_ALE_DRF_RESUME_BCAM_DRF_RESUME_MASK (0x1 << RTL8373_ALE_DRF_RESUME_BCAM_DRF_RESUME_OFFSET) + #define RTL8373_ALE_DRF_RESUME_ACT_DRF_RESUME_OFFSET (1) + #define RTL8373_ALE_DRF_RESUME_ACT_DRF_RESUME_MASK (0x1 << RTL8373_ALE_DRF_RESUME_ACT_DRF_RESUME_OFFSET) + #define RTL8373_ALE_DRF_RESUME_CVLAN_DRF_RESUME_OFFSET (0) + #define RTL8373_ALE_DRF_RESUME_CVLAN_DRF_RESUME_MASK (0x1 << RTL8373_ALE_DRF_RESUME_CVLAN_DRF_RESUME_OFFSET) + +#define RTL8373_ALE_DRF_DONE_ADDR (0x5CA4) + #define RTL8373_ALE_DRF_DONE_L2_DRF_DONE_OFFSET (5) + #define RTL8373_ALE_DRF_DONE_L2_DRF_DONE_MASK (0xF << RTL8373_ALE_DRF_DONE_L2_DRF_DONE_OFFSET) + #define RTL8373_ALE_DRF_DONE_TCAM_DRF_DONE_H_OFFSET (4) + #define RTL8373_ALE_DRF_DONE_TCAM_DRF_DONE_H_MASK (0x1 << RTL8373_ALE_DRF_DONE_TCAM_DRF_DONE_H_OFFSET) + #define RTL8373_ALE_DRF_DONE_TCAM_DRF_DONE_L_OFFSET (3) + #define RTL8373_ALE_DRF_DONE_TCAM_DRF_DONE_L_MASK (0x1 << RTL8373_ALE_DRF_DONE_TCAM_DRF_DONE_L_OFFSET) + #define RTL8373_ALE_DRF_DONE_BCAM_DRF_DONE_OFFSET (2) + #define RTL8373_ALE_DRF_DONE_BCAM_DRF_DONE_MASK (0x1 << RTL8373_ALE_DRF_DONE_BCAM_DRF_DONE_OFFSET) + #define RTL8373_ALE_DRF_DONE_ACT_DRF_DONE_OFFSET (1) + #define RTL8373_ALE_DRF_DONE_ACT_DRF_DONE_MASK (0x1 << RTL8373_ALE_DRF_DONE_ACT_DRF_DONE_OFFSET) + #define RTL8373_ALE_DRF_DONE_CVLAN_DRF_DONE_OFFSET (0) + #define RTL8373_ALE_DRF_DONE_CVLAN_DRF_DONE_MASK (0x1 << RTL8373_ALE_DRF_DONE_CVLAN_DRF_DONE_OFFSET) + +#define RTL8373_ALE_DRF_FAIL_ADDR (0x5CA8) + #define RTL8373_ALE_DRF_FAIL_L2_DRF_FAIL_OFFSET (5) + #define RTL8373_ALE_DRF_FAIL_L2_DRF_FAIL_MASK (0xF << RTL8373_ALE_DRF_FAIL_L2_DRF_FAIL_OFFSET) + #define RTL8373_ALE_DRF_FAIL_TCAM_DRF_FAIL_H_OFFSET (4) + #define RTL8373_ALE_DRF_FAIL_TCAM_DRF_FAIL_H_MASK (0x1 << RTL8373_ALE_DRF_FAIL_TCAM_DRF_FAIL_H_OFFSET) + #define RTL8373_ALE_DRF_FAIL_TCAM_DRF_FAIL_L_OFFSET (3) + #define RTL8373_ALE_DRF_FAIL_TCAM_DRF_FAIL_L_MASK (0x1 << RTL8373_ALE_DRF_FAIL_TCAM_DRF_FAIL_L_OFFSET) + #define RTL8373_ALE_DRF_FAIL_BCAM_DRF_FAIL_OFFSET (2) + #define RTL8373_ALE_DRF_FAIL_BCAM_DRF_FAIL_MASK (0x1 << RTL8373_ALE_DRF_FAIL_BCAM_DRF_FAIL_OFFSET) + #define RTL8373_ALE_DRF_FAIL_ACT_DRF_FAIL_OFFSET (1) + #define RTL8373_ALE_DRF_FAIL_ACT_DRF_FAIL_MASK (0x1 << RTL8373_ALE_DRF_FAIL_ACT_DRF_FAIL_OFFSET) + #define RTL8373_ALE_DRF_FAIL_CVLAN_DRF_FAIL_OFFSET (0) + #define RTL8373_ALE_DRF_FAIL_CVLAN_DRF_FAIL_MASK (0x1 << RTL8373_ALE_DRF_FAIL_CVLAN_DRF_FAIL_OFFSET) + +#define RTL8373_PAR_MEM_CFG_0_ADDR (0x6F20) + #define RTL8373_PAR_MEM_CFG_0_PTR_LS_OFFSET (12) + #define RTL8373_PAR_MEM_CFG_0_PTR_LS_MASK (0x1 << RTL8373_PAR_MEM_CFG_0_PTR_LS_OFFSET) + #define RTL8373_PAR_MEM_CFG_0_PTR_TEST1A_OFFSET (11) + #define RTL8373_PAR_MEM_CFG_0_PTR_TEST1A_MASK (0x1 << RTL8373_PAR_MEM_CFG_0_PTR_TEST1A_OFFSET) + #define RTL8373_PAR_MEM_CFG_0_PTR_TEST1B_OFFSET (10) + #define RTL8373_PAR_MEM_CFG_0_PTR_TEST1B_MASK (0x1 << RTL8373_PAR_MEM_CFG_0_PTR_TEST1B_OFFSET) + #define RTL8373_PAR_MEM_CFG_0_PTR_RMA_OFFSET (6) + #define RTL8373_PAR_MEM_CFG_0_PTR_RMA_MASK (0xF << RTL8373_PAR_MEM_CFG_0_PTR_RMA_OFFSET) + #define RTL8373_PAR_MEM_CFG_0_PTR_RMB_OFFSET (2) + #define RTL8373_PAR_MEM_CFG_0_PTR_RMB_MASK (0xF << RTL8373_PAR_MEM_CFG_0_PTR_RMB_OFFSET) + #define RTL8373_PAR_MEM_CFG_0_PTR_RMEA_OFFSET (1) + #define RTL8373_PAR_MEM_CFG_0_PTR_RMEA_MASK (0x1 << RTL8373_PAR_MEM_CFG_0_PTR_RMEA_OFFSET) + #define RTL8373_PAR_MEM_CFG_0_PTR_RMEB_OFFSET (0) + #define RTL8373_PAR_MEM_CFG_0_PTR_RMEB_MASK (0x1 << RTL8373_PAR_MEM_CFG_0_PTR_RMEB_OFFSET) + +#define RTL8373_PAR_MEM_CFG_1_ADDR (0x6F24) + #define RTL8373_PAR_MEM_CFG_1_HSB_RMB_OFFSET (0) + #define RTL8373_PAR_MEM_CFG_1_HSB_RMB_MASK (0xFFFFFF << RTL8373_PAR_MEM_CFG_1_HSB_RMB_OFFSET) + +#define RTL8373_PAR_MEM_CFG_2_ADDR (0x6F28) + #define RTL8373_PAR_MEM_CFG_2_HSB_RMA_OFFSET (0) + #define RTL8373_PAR_MEM_CFG_2_HSB_RMA_MASK (0xFFFFFF << RTL8373_PAR_MEM_CFG_2_HSB_RMA_OFFSET) + +#define RTL8373_PAR_MEM_CFG_3_ADDR (0x6F2C) + #define RTL8373_PAR_MEM_CFG_3_HSB_LS_OFFSET (24) + #define RTL8373_PAR_MEM_CFG_3_HSB_LS_MASK (0x3F << RTL8373_PAR_MEM_CFG_3_HSB_LS_OFFSET) + #define RTL8373_PAR_MEM_CFG_3_HSB_TEST1A_OFFSET (18) + #define RTL8373_PAR_MEM_CFG_3_HSB_TEST1A_MASK (0x3F << RTL8373_PAR_MEM_CFG_3_HSB_TEST1A_OFFSET) + #define RTL8373_PAR_MEM_CFG_3_HSB_TEST1B_OFFSET (12) + #define RTL8373_PAR_MEM_CFG_3_HSB_TEST1B_MASK (0x3F << RTL8373_PAR_MEM_CFG_3_HSB_TEST1B_OFFSET) + #define RTL8373_PAR_MEM_CFG_3_HSB_RMEA_OFFSET (6) + #define RTL8373_PAR_MEM_CFG_3_HSB_RMEA_MASK (0x3F << RTL8373_PAR_MEM_CFG_3_HSB_RMEA_OFFSET) + #define RTL8373_PAR_MEM_CFG_3_HSB_RMEB_OFFSET (0) + #define RTL8373_PAR_MEM_CFG_3_HSB_RMEB_MASK (0x3F << RTL8373_PAR_MEM_CFG_3_HSB_RMEB_OFFSET) + +#define RTL8373_PAR_BIST_RESET_RESUME_ADDR (0x6F30) + #define RTL8373_PAR_BIST_RESET_RESUME_HSB_DRF_TEST_RESUME_OFFSET (17) + #define RTL8373_PAR_BIST_RESET_RESUME_HSB_DRF_TEST_RESUME_MASK (0x1 << RTL8373_PAR_BIST_RESET_RESUME_HSB_DRF_TEST_RESUME_OFFSET) + #define RTL8373_PAR_BIST_RESET_RESUME_PTR_DRF_TEST_RESUME_OFFSET (16) + #define RTL8373_PAR_BIST_RESET_RESUME_PTR_DRF_TEST_RESUME_MASK (0x1 << RTL8373_PAR_BIST_RESET_RESUME_PTR_DRF_TEST_RESUME_OFFSET) + #define RTL8373_PAR_BIST_RESET_RESUME_HSB_BIST_RSTN_OFFSET (1) + #define RTL8373_PAR_BIST_RESET_RESUME_HSB_BIST_RSTN_MASK (0x1 << RTL8373_PAR_BIST_RESET_RESUME_HSB_BIST_RSTN_OFFSET) + #define RTL8373_PAR_BIST_RESET_RESUME_PTR_BIST_RSTN_OFFSET (0) + #define RTL8373_PAR_BIST_RESET_RESUME_PTR_BIST_RSTN_MASK (0x1 << RTL8373_PAR_BIST_RESET_RESUME_PTR_BIST_RSTN_OFFSET) + +#define RTL8373_PAR_BIST_MODE_DRFMODE_ADDR (0x6F34) + #define RTL8373_PAR_BIST_MODE_DRFMODE_HSB_DRF_MODE_OFFSET (17) + #define RTL8373_PAR_BIST_MODE_DRFMODE_HSB_DRF_MODE_MASK (0x1 << RTL8373_PAR_BIST_MODE_DRFMODE_HSB_DRF_MODE_OFFSET) + #define RTL8373_PAR_BIST_MODE_DRFMODE_PTR_DRF_MODE_OFFSET (16) + #define RTL8373_PAR_BIST_MODE_DRFMODE_PTR_DRF_MODE_MASK (0x1 << RTL8373_PAR_BIST_MODE_DRFMODE_PTR_DRF_MODE_OFFSET) + #define RTL8373_PAR_BIST_MODE_DRFMODE_HSB_BIST_MODE_OFFSET (1) + #define RTL8373_PAR_BIST_MODE_DRFMODE_HSB_BIST_MODE_MASK (0x1 << RTL8373_PAR_BIST_MODE_DRFMODE_HSB_BIST_MODE_OFFSET) + #define RTL8373_PAR_BIST_MODE_DRFMODE_PTR_BIST_MODE_OFFSET (0) + #define RTL8373_PAR_BIST_MODE_DRFMODE_PTR_BIST_MODE_MASK (0x1 << RTL8373_PAR_BIST_MODE_DRFMODE_PTR_BIST_MODE_OFFSET) + +#define RTL8373_PAR_BIST_VDDR_LOOP_ADDR (0x6F38) + #define RTL8373_PAR_BIST_VDDR_LOOP_HSB_BIST_LOOP_MODE_OFFSET (17) + #define RTL8373_PAR_BIST_VDDR_LOOP_HSB_BIST_LOOP_MODE_MASK (0x1 << RTL8373_PAR_BIST_VDDR_LOOP_HSB_BIST_LOOP_MODE_OFFSET) + #define RTL8373_PAR_BIST_VDDR_LOOP_PTR_BIST_LOOP_MODE_OFFSET (16) + #define RTL8373_PAR_BIST_VDDR_LOOP_PTR_BIST_LOOP_MODE_MASK (0x1 << RTL8373_PAR_BIST_VDDR_LOOP_PTR_BIST_LOOP_MODE_OFFSET) + #define RTL8373_PAR_BIST_VDDR_LOOP_HSB_DYN_READ_EN_OFFSET (1) + #define RTL8373_PAR_BIST_VDDR_LOOP_HSB_DYN_READ_EN_MASK (0x1 << RTL8373_PAR_BIST_VDDR_LOOP_HSB_DYN_READ_EN_OFFSET) + #define RTL8373_PAR_BIST_VDDR_LOOP_PTR_DYN_READ_EN_OFFSET (0) + #define RTL8373_PAR_BIST_VDDR_LOOP_PTR_DYN_READ_EN_MASK (0x1 << RTL8373_PAR_BIST_VDDR_LOOP_PTR_DYN_READ_EN_OFFSET) + +#define RTL8373_PAR_BIST_START_PAUSE_ADDR (0x6F3C) + #define RTL8373_PAR_BIST_START_PAUSE_HSB_DRF_START_PAUSE_OFFSET (1) + #define RTL8373_PAR_BIST_START_PAUSE_HSB_DRF_START_PAUSE_MASK (0x1 << RTL8373_PAR_BIST_START_PAUSE_HSB_DRF_START_PAUSE_OFFSET) + #define RTL8373_PAR_BIST_START_PAUSE_PTR_DRF_START_PAUSE_OFFSET (0) + #define RTL8373_PAR_BIST_START_PAUSE_PTR_DRF_START_PAUSE_MASK (0x1 << RTL8373_PAR_BIST_START_PAUSE_PTR_DRF_START_PAUSE_OFFSET) + +#define RTL8373_PAR_BIST_DONE_DRFDONE_ADDR (0x6F40) + #define RTL8373_PAR_BIST_DONE_DRFDONE_HSB_DRF_DONE_OFFSET (17) + #define RTL8373_PAR_BIST_DONE_DRFDONE_HSB_DRF_DONE_MASK (0x1 << RTL8373_PAR_BIST_DONE_DRFDONE_HSB_DRF_DONE_OFFSET) + #define RTL8373_PAR_BIST_DONE_DRFDONE_PTR_DRF_DONE_OFFSET (16) + #define RTL8373_PAR_BIST_DONE_DRFDONE_PTR_DRF_DONE_MASK (0x1 << RTL8373_PAR_BIST_DONE_DRFDONE_PTR_DRF_DONE_OFFSET) + #define RTL8373_PAR_BIST_DONE_DRFDONE_HSB_BIST_DONE_OFFSET (1) + #define RTL8373_PAR_BIST_DONE_DRFDONE_HSB_BIST_DONE_MASK (0x1 << RTL8373_PAR_BIST_DONE_DRFDONE_HSB_BIST_DONE_OFFSET) + #define RTL8373_PAR_BIST_DONE_DRFDONE_PTR_BIST_DONE_OFFSET (0) + #define RTL8373_PAR_BIST_DONE_DRFDONE_PTR_BIST_DONE_MASK (0x1 << RTL8373_PAR_BIST_DONE_DRFDONE_PTR_BIST_DONE_OFFSET) + +#define RTL8373_PAR_BIST_FAIL_DRFFAIL_ADDR (0x6F44) + #define RTL8373_PAR_BIST_FAIL_DRFFAIL_HSB_DRF_FAIL_OFFSET (17) + #define RTL8373_PAR_BIST_FAIL_DRFFAIL_HSB_DRF_FAIL_MASK (0x3F << RTL8373_PAR_BIST_FAIL_DRFFAIL_HSB_DRF_FAIL_OFFSET) + #define RTL8373_PAR_BIST_FAIL_DRFFAIL_PTR_DRF_FAIL_OFFSET (16) + #define RTL8373_PAR_BIST_FAIL_DRFFAIL_PTR_DRF_FAIL_MASK (0x1 << RTL8373_PAR_BIST_FAIL_DRFFAIL_PTR_DRF_FAIL_OFFSET) + #define RTL8373_PAR_BIST_FAIL_DRFFAIL_HSB_BIST_FAIL_OFFSET (1) + #define RTL8373_PAR_BIST_FAIL_DRFFAIL_HSB_BIST_FAIL_MASK (0x3F << RTL8373_PAR_BIST_FAIL_DRFFAIL_HSB_BIST_FAIL_OFFSET) + #define RTL8373_PAR_BIST_FAIL_DRFFAIL_PTR_BIST_FAIL_OFFSET (0) + #define RTL8373_PAR_BIST_FAIL_DRFFAIL_PTR_BIST_FAIL_MASK (0x1 << RTL8373_PAR_BIST_FAIL_DRFFAIL_PTR_BIST_FAIL_OFFSET) + +#define RTL8373_PAR_BIST_CTRL_0_ADDR (0x6F48) + #define RTL8373_PAR_BIST_CTRL_0_HSB_BIST_EN_OFFSET (1) + #define RTL8373_PAR_BIST_CTRL_0_HSB_BIST_EN_MASK (0x1 << RTL8373_PAR_BIST_CTRL_0_HSB_BIST_EN_OFFSET) + #define RTL8373_PAR_BIST_CTRL_0_PTR_BIST_EN_OFFSET (0) + #define RTL8373_PAR_BIST_CTRL_0_PTR_BIST_EN_MASK (0x1 << RTL8373_PAR_BIST_CTRL_0_PTR_BIST_EN_OFFSET) + +#define RTL8373_MBIST_CTRL_ADDR (0xF40) + #define RTL8373_MBIST_CTRL_MIB_LS_MODE_OFFSET (12) + #define RTL8373_MBIST_CTRL_MIB_LS_MODE_MASK (0x1 << RTL8373_MBIST_CTRL_MIB_LS_MODE_OFFSET) + #define RTL8373_MBIST_CTRL_MIB_MB_RM_OFFSET (8) + #define RTL8373_MBIST_CTRL_MIB_MB_RM_MASK (0xF << RTL8373_MBIST_CTRL_MIB_MB_RM_OFFSET) + #define RTL8373_MBIST_CTRL_MIB_MB_RME_OFFSET (7) + #define RTL8373_MBIST_CTRL_MIB_MB_RME_MASK (0x1 << RTL8373_MBIST_CTRL_MIB_MB_RME_OFFSET) + #define RTL8373_MBIST_CTRL_MIB_TEST1_OFFSET (6) + #define RTL8373_MBIST_CTRL_MIB_TEST1_MASK (0x1 << RTL8373_MBIST_CTRL_MIB_TEST1_OFFSET) + #define RTL8373_MBIST_CTRL_MIB_LOOP_MODE_OFFSET (5) + #define RTL8373_MBIST_CTRL_MIB_LOOP_MODE_MASK (0x1 << RTL8373_MBIST_CTRL_MIB_LOOP_MODE_OFFSET) + #define RTL8373_MBIST_CTRL_MIB_DYN_READ_EN_OFFSET (4) + #define RTL8373_MBIST_CTRL_MIB_DYN_READ_EN_MASK (0x1 << RTL8373_MBIST_CTRL_MIB_DYN_READ_EN_OFFSET) + #define RTL8373_MBIST_CTRL_MIB_RESUME_OFFSET (3) + #define RTL8373_MBIST_CTRL_MIB_RESUME_MASK (0x1 << RTL8373_MBIST_CTRL_MIB_RESUME_OFFSET) + #define RTL8373_MBIST_CTRL_MIB_DRF_MODE_OFFSET (2) + #define RTL8373_MBIST_CTRL_MIB_DRF_MODE_MASK (0x1 << RTL8373_MBIST_CTRL_MIB_DRF_MODE_OFFSET) + #define RTL8373_MBIST_CTRL_MIB_MODE_OFFSET (1) + #define RTL8373_MBIST_CTRL_MIB_MODE_MASK (0x1 << RTL8373_MBIST_CTRL_MIB_MODE_OFFSET) + #define RTL8373_MBIST_CTRL_MIB_RSTN_OFFSET (0) + #define RTL8373_MBIST_CTRL_MIB_RSTN_MASK (0x1 << RTL8373_MBIST_CTRL_MIB_RSTN_OFFSET) + +#define RTL8373_MBIST_RSLT_ADDR (0xF44) + #define RTL8373_MBIST_RSLT_MIB_DRF_FAIL_OFFSET (4) + #define RTL8373_MBIST_RSLT_MIB_DRF_FAIL_MASK (0x1 << RTL8373_MBIST_RSLT_MIB_DRF_FAIL_OFFSET) + #define RTL8373_MBIST_RSLT_MIB_FAIL_OFFSET (3) + #define RTL8373_MBIST_RSLT_MIB_FAIL_MASK (0x1 << RTL8373_MBIST_RSLT_MIB_FAIL_OFFSET) + #define RTL8373_MBIST_RSLT_MIB_DRF_DONE_OFFSET (2) + #define RTL8373_MBIST_RSLT_MIB_DRF_DONE_MASK (0x1 << RTL8373_MBIST_RSLT_MIB_DRF_DONE_OFFSET) + #define RTL8373_MBIST_RSLT_MIB_DONE_OFFSET (1) + #define RTL8373_MBIST_RSLT_MIB_DONE_MASK (0x1 << RTL8373_MBIST_RSLT_MIB_DONE_OFFSET) + #define RTL8373_MBIST_RSLT_MIB_DRF_PAUSE_OFFSET (0) + #define RTL8373_MBIST_RSLT_MIB_DRF_PAUSE_MASK (0x1 << RTL8373_MBIST_RSLT_MIB_DRF_PAUSE_OFFSET) + +/* + * Feature: HW_MISC + */ +#define RTL8373_BOND_INFO_ADDR (0x7F60) + #define RTL8373_BOND_INFO_BOND_INFO_RO_OFFSET (0) + #define RTL8373_BOND_INFO_BOND_INFO_RO_MASK (0xFFF << RTL8373_BOND_INFO_BOND_INFO_RO_OFFSET) + +#define RTL8373_STRAP_INFO_0_ADDR (0x7F64) + #define RTL8373_STRAP_INFO_0_STRAP_INFO_RO_OFFSET (0) + #define RTL8373_STRAP_INFO_0_STRAP_INFO_RO_MASK (0x3FFFF << RTL8373_STRAP_INFO_0_STRAP_INFO_RO_OFFSET) + +#define RTL8373_IO_DRVING_0_ADDR (0x7F68) + #define RTL8373_IO_DRVING_0_IO_DRVING_0_OFFSET (0) + #define RTL8373_IO_DRVING_0_IO_DRVING_0_MASK (0xFFFFFFFF << RTL8373_IO_DRVING_0_IO_DRVING_0_OFFSET) + +#define RTL8373_IO_DRVING_1_ADDR (0x7F6C) + #define RTL8373_IO_DRVING_1_IO_DRVING_1_OFFSET (0) + #define RTL8373_IO_DRVING_1_IO_DRVING_1_MASK (0xFFFFFFFF << RTL8373_IO_DRVING_1_IO_DRVING_1_OFFSET) + +#define RTL8373_IO_DRVING_2_ADDR (0x7F70) + #define RTL8373_IO_DRVING_2_IO_DRVING_2_OFFSET (0) + #define RTL8373_IO_DRVING_2_IO_DRVING_2_MASK (0x7FFFF << RTL8373_IO_DRVING_2_IO_DRVING_2_OFFSET) + +#define RTL8373_IO_SLEW_0_ADDR (0x7F74) + #define RTL8373_IO_SLEW_0_IO_SLEW_0_OFFSET (0) + #define RTL8373_IO_SLEW_0_IO_SLEW_0_MASK (0xFFFFFFFF << RTL8373_IO_SLEW_0_IO_SLEW_0_OFFSET) + +#define RTL8373_IO_SLEW_1_ADDR (0x7F78) + #define RTL8373_IO_SLEW_1_IO_SLEW_1_OFFSET (0) + #define RTL8373_IO_SLEW_1_IO_SLEW_1_MASK (0xFFFFFFFF << RTL8373_IO_SLEW_1_IO_SLEW_1_OFFSET) + +#define RTL8373_IO_SLEW_2_ADDR (0x7F7C) + #define RTL8373_IO_SLEW_2_IO_SLEW_2_OFFSET (0) + #define RTL8373_IO_SLEW_2_IO_SLEW_2_MASK (0x7FFFF << RTL8373_IO_SLEW_2_IO_SLEW_2_OFFSET) + +#define RTL8373_IO_SMT_EN_0_ADDR (0x7F80) + #define RTL8373_IO_SMT_EN_0_IO_SMT_EN_0_OFFSET (0) + #define RTL8373_IO_SMT_EN_0_IO_SMT_EN_0_MASK (0xFFFFFFFF << RTL8373_IO_SMT_EN_0_IO_SMT_EN_0_OFFSET) + +#define RTL8373_IO_SMT_EN_1_ADDR (0x7F84) + #define RTL8373_IO_SMT_EN_1_IO_SMT_EN_1_OFFSET (0) + #define RTL8373_IO_SMT_EN_1_IO_SMT_EN_1_MASK (0xFFFFFFFF << RTL8373_IO_SMT_EN_1_IO_SMT_EN_1_OFFSET) + +#define RTL8373_IO_SMT_EN_2_ADDR (0x7F88) + #define RTL8373_IO_SMT_EN_2_IO_SMT_EN_2_OFFSET (0) + #define RTL8373_IO_SMT_EN_2_IO_SMT_EN_2_MASK (0x7FFFF << RTL8373_IO_SMT_EN_2_IO_SMT_EN_2_OFFSET) + +#define RTL8373_IO_MUX_SEL_0_ADDR (0x7F8C) + #define RTL8373_IO_MUX_SEL_0_FLASH_FORCE_CTR_EN_OFFSET (31) + #define RTL8373_IO_MUX_SEL_0_FLASH_FORCE_CTR_EN_MASK (0x1 << RTL8373_IO_MUX_SEL_0_FLASH_FORCE_CTR_EN_OFFSET) + #define RTL8373_IO_MUX_SEL_0_GLB_RLDP_LED_EN_OFFSET (29) + #define RTL8373_IO_MUX_SEL_0_GLB_RLDP_LED_EN_MASK (0x1 << RTL8373_IO_MUX_SEL_0_GLB_RLDP_LED_EN_OFFSET) + #define RTL8373_IO_MUX_SEL_0_SYS_LED_EN_OFFSET (28) + #define RTL8373_IO_MUX_SEL_0_SYS_LED_EN_MASK (0x1 << RTL8373_IO_MUX_SEL_0_SYS_LED_EN_OFFSET) + #define RTL8373_IO_MUX_SEL_0_GPIO_LED27_SEL_OFFSET (27) + #define RTL8373_IO_MUX_SEL_0_GPIO_LED27_SEL_MASK (0x1 << RTL8373_IO_MUX_SEL_0_GPIO_LED27_SEL_OFFSET) + #define RTL8373_IO_MUX_SEL_0_GPIO_LED26_SEL_OFFSET (26) + #define RTL8373_IO_MUX_SEL_0_GPIO_LED26_SEL_MASK (0x1 << RTL8373_IO_MUX_SEL_0_GPIO_LED26_SEL_OFFSET) + #define RTL8373_IO_MUX_SEL_0_GPIO_LED25_SEL_OFFSET (25) + #define RTL8373_IO_MUX_SEL_0_GPIO_LED25_SEL_MASK (0x1 << RTL8373_IO_MUX_SEL_0_GPIO_LED25_SEL_OFFSET) + #define RTL8373_IO_MUX_SEL_0_GPIO_LED24_SEL_OFFSET (24) + #define RTL8373_IO_MUX_SEL_0_GPIO_LED24_SEL_MASK (0x1 << RTL8373_IO_MUX_SEL_0_GPIO_LED24_SEL_OFFSET) + #define RTL8373_IO_MUX_SEL_0_GPIO_LED23_SEL_OFFSET (23) + #define RTL8373_IO_MUX_SEL_0_GPIO_LED23_SEL_MASK (0x1 << RTL8373_IO_MUX_SEL_0_GPIO_LED23_SEL_OFFSET) + #define RTL8373_IO_MUX_SEL_0_GPIO_LED22_SEL_OFFSET (22) + #define RTL8373_IO_MUX_SEL_0_GPIO_LED22_SEL_MASK (0x1 << RTL8373_IO_MUX_SEL_0_GPIO_LED22_SEL_OFFSET) + #define RTL8373_IO_MUX_SEL_0_GPIO_LED21_SEL_OFFSET (21) + #define RTL8373_IO_MUX_SEL_0_GPIO_LED21_SEL_MASK (0x1 << RTL8373_IO_MUX_SEL_0_GPIO_LED21_SEL_OFFSET) + #define RTL8373_IO_MUX_SEL_0_GPIO_LED20_SEL_OFFSET (20) + #define RTL8373_IO_MUX_SEL_0_GPIO_LED20_SEL_MASK (0x1 << RTL8373_IO_MUX_SEL_0_GPIO_LED20_SEL_OFFSET) + #define RTL8373_IO_MUX_SEL_0_GPIO_LED19_SEL_OFFSET (19) + #define RTL8373_IO_MUX_SEL_0_GPIO_LED19_SEL_MASK (0x1 << RTL8373_IO_MUX_SEL_0_GPIO_LED19_SEL_OFFSET) + #define RTL8373_IO_MUX_SEL_0_GPIO_LED18_SEL_OFFSET (18) + #define RTL8373_IO_MUX_SEL_0_GPIO_LED18_SEL_MASK (0x1 << RTL8373_IO_MUX_SEL_0_GPIO_LED18_SEL_OFFSET) + #define RTL8373_IO_MUX_SEL_0_GPIO_LED17_SEL_OFFSET (17) + #define RTL8373_IO_MUX_SEL_0_GPIO_LED17_SEL_MASK (0x1 << RTL8373_IO_MUX_SEL_0_GPIO_LED17_SEL_OFFSET) + #define RTL8373_IO_MUX_SEL_0_GPIO_LED16_SEL_OFFSET (16) + #define RTL8373_IO_MUX_SEL_0_GPIO_LED16_SEL_MASK (0x1 << RTL8373_IO_MUX_SEL_0_GPIO_LED16_SEL_OFFSET) + #define RTL8373_IO_MUX_SEL_0_GPIO_LED15_SEL_OFFSET (15) + #define RTL8373_IO_MUX_SEL_0_GPIO_LED15_SEL_MASK (0x1 << RTL8373_IO_MUX_SEL_0_GPIO_LED15_SEL_OFFSET) + #define RTL8373_IO_MUX_SEL_0_GPIO_LED14_SEL_OFFSET (14) + #define RTL8373_IO_MUX_SEL_0_GPIO_LED14_SEL_MASK (0x1 << RTL8373_IO_MUX_SEL_0_GPIO_LED14_SEL_OFFSET) + #define RTL8373_IO_MUX_SEL_0_GPIO_LED13_SEL_OFFSET (13) + #define RTL8373_IO_MUX_SEL_0_GPIO_LED13_SEL_MASK (0x1 << RTL8373_IO_MUX_SEL_0_GPIO_LED13_SEL_OFFSET) + #define RTL8373_IO_MUX_SEL_0_GPIO_LED12_SEL_OFFSET (12) + #define RTL8373_IO_MUX_SEL_0_GPIO_LED12_SEL_MASK (0x1 << RTL8373_IO_MUX_SEL_0_GPIO_LED12_SEL_OFFSET) + #define RTL8373_IO_MUX_SEL_0_GPIO_LED11_SEL_OFFSET (11) + #define RTL8373_IO_MUX_SEL_0_GPIO_LED11_SEL_MASK (0x1 << RTL8373_IO_MUX_SEL_0_GPIO_LED11_SEL_OFFSET) + #define RTL8373_IO_MUX_SEL_0_GPIO_LED10_SEL_OFFSET (10) + #define RTL8373_IO_MUX_SEL_0_GPIO_LED10_SEL_MASK (0x1 << RTL8373_IO_MUX_SEL_0_GPIO_LED10_SEL_OFFSET) + #define RTL8373_IO_MUX_SEL_0_GPIO_LED9_SEL_OFFSET (9) + #define RTL8373_IO_MUX_SEL_0_GPIO_LED9_SEL_MASK (0x1 << RTL8373_IO_MUX_SEL_0_GPIO_LED9_SEL_OFFSET) + #define RTL8373_IO_MUX_SEL_0_GPIO_LED8_SEL_OFFSET (8) + #define RTL8373_IO_MUX_SEL_0_GPIO_LED8_SEL_MASK (0x1 << RTL8373_IO_MUX_SEL_0_GPIO_LED8_SEL_OFFSET) + #define RTL8373_IO_MUX_SEL_0_GPIO_LED7_SEL_OFFSET (7) + #define RTL8373_IO_MUX_SEL_0_GPIO_LED7_SEL_MASK (0x1 << RTL8373_IO_MUX_SEL_0_GPIO_LED7_SEL_OFFSET) + #define RTL8373_IO_MUX_SEL_0_GPIO_LED6_SEL_OFFSET (6) + #define RTL8373_IO_MUX_SEL_0_GPIO_LED6_SEL_MASK (0x1 << RTL8373_IO_MUX_SEL_0_GPIO_LED6_SEL_OFFSET) + #define RTL8373_IO_MUX_SEL_0_GPIO_LED5_SEL_OFFSET (5) + #define RTL8373_IO_MUX_SEL_0_GPIO_LED5_SEL_MASK (0x1 << RTL8373_IO_MUX_SEL_0_GPIO_LED5_SEL_OFFSET) + #define RTL8373_IO_MUX_SEL_0_GPIO_LED4_SEL_OFFSET (4) + #define RTL8373_IO_MUX_SEL_0_GPIO_LED4_SEL_MASK (0x1 << RTL8373_IO_MUX_SEL_0_GPIO_LED4_SEL_OFFSET) + #define RTL8373_IO_MUX_SEL_0_GPIO_LED3_SEL_OFFSET (3) + #define RTL8373_IO_MUX_SEL_0_GPIO_LED3_SEL_MASK (0x1 << RTL8373_IO_MUX_SEL_0_GPIO_LED3_SEL_OFFSET) + #define RTL8373_IO_MUX_SEL_0_GPIO_LED2_SEL_OFFSET (2) + #define RTL8373_IO_MUX_SEL_0_GPIO_LED2_SEL_MASK (0x1 << RTL8373_IO_MUX_SEL_0_GPIO_LED2_SEL_OFFSET) + #define RTL8373_IO_MUX_SEL_0_GPIO_LED1_SEL_OFFSET (1) + #define RTL8373_IO_MUX_SEL_0_GPIO_LED1_SEL_MASK (0x1 << RTL8373_IO_MUX_SEL_0_GPIO_LED1_SEL_OFFSET) + #define RTL8373_IO_MUX_SEL_0_GPIO_LED0_SEL_OFFSET (0) + #define RTL8373_IO_MUX_SEL_0_GPIO_LED0_SEL_MASK (0x1 << RTL8373_IO_MUX_SEL_0_GPIO_LED0_SEL_OFFSET) + +#define RTL8373_IO_MUX_SEL_1_ADDR (0x7F90) + #define RTL8373_IO_MUX_SEL_1_GPIO_PWM_OUT_SEL_OFFSET (30) + #define RTL8373_IO_MUX_SEL_1_GPIO_PWM_OUT_SEL_MASK (0x1 << RTL8373_IO_MUX_SEL_1_GPIO_PWM_OUT_SEL_OFFSET) + #define RTL8373_IO_MUX_SEL_1_GPIO_SDA4_SEL_OFFSET (29) + #define RTL8373_IO_MUX_SEL_1_GPIO_SDA4_SEL_MASK (0x1 << RTL8373_IO_MUX_SEL_1_GPIO_SDA4_SEL_OFFSET) + #define RTL8373_IO_MUX_SEL_1_SYNCELOCK1_SEL_OFFSET (28) + #define RTL8373_IO_MUX_SEL_1_SYNCELOCK1_SEL_MASK (0x1 << RTL8373_IO_MUX_SEL_1_SYNCELOCK1_SEL_OFFSET) + #define RTL8373_IO_MUX_SEL_1_SYNCELOCK0_SEL_OFFSET (27) + #define RTL8373_IO_MUX_SEL_1_SYNCELOCK0_SEL_MASK (0x1 << RTL8373_IO_MUX_SEL_1_SYNCELOCK0_SEL_OFFSET) + #define RTL8373_IO_MUX_SEL_1_PTP_PPS_IN_SEL_OFFSET (24) + #define RTL8373_IO_MUX_SEL_1_PTP_PPS_IN_SEL_MASK (0x1 << RTL8373_IO_MUX_SEL_1_PTP_PPS_IN_SEL_OFFSET) + #define RTL8373_IO_MUX_SEL_1_PTP_TOD_IN_SEL_OFFSET (23) + #define RTL8373_IO_MUX_SEL_1_PTP_TOD_IN_SEL_MASK (0x1 << RTL8373_IO_MUX_SEL_1_PTP_TOD_IN_SEL_OFFSET) + #define RTL8373_IO_MUX_SEL_1_PTP_PPS_OUT_SEL_OFFSET (22) + #define RTL8373_IO_MUX_SEL_1_PTP_PPS_OUT_SEL_MASK (0x1 << RTL8373_IO_MUX_SEL_1_PTP_PPS_OUT_SEL_OFFSET) + #define RTL8373_IO_MUX_SEL_1_PTP_TOD_OUT_SEL_OFFSET (21) + #define RTL8373_IO_MUX_SEL_1_PTP_TOD_OUT_SEL_MASK (0x1 << RTL8373_IO_MUX_SEL_1_PTP_TOD_OUT_SEL_OFFSET) + #define RTL8373_IO_MUX_SEL_1_PTP_CLK_OUT_SEL_OFFSET (20) + #define RTL8373_IO_MUX_SEL_1_PTP_CLK_OUT_SEL_MASK (0x1 << RTL8373_IO_MUX_SEL_1_PTP_CLK_OUT_SEL_OFFSET) + #define RTL8373_IO_MUX_SEL_1_PTP_CLK125M_IN_SEL_OFFSET (19) + #define RTL8373_IO_MUX_SEL_1_PTP_CLK125M_IN_SEL_MASK (0x1 << RTL8373_IO_MUX_SEL_1_PTP_CLK125M_IN_SEL_OFFSET) + #define RTL8373_IO_MUX_SEL_1_PAD_MSDA2_SEL_1_OFFSET (18) + #define RTL8373_IO_MUX_SEL_1_PAD_MSDA2_SEL_1_MASK (0x1 << RTL8373_IO_MUX_SEL_1_PAD_MSDA2_SEL_1_OFFSET) + #define RTL8373_IO_MUX_SEL_1_PAD_MSDA2_SEL_0_OFFSET (17) + #define RTL8373_IO_MUX_SEL_1_PAD_MSDA2_SEL_0_MASK (0x1 << RTL8373_IO_MUX_SEL_1_PAD_MSDA2_SEL_0_OFFSET) + #define RTL8373_IO_MUX_SEL_1_PAD_MSCK2_SEL_1_OFFSET (16) + #define RTL8373_IO_MUX_SEL_1_PAD_MSCK2_SEL_1_MASK (0x1 << RTL8373_IO_MUX_SEL_1_PAD_MSCK2_SEL_1_OFFSET) + #define RTL8373_IO_MUX_SEL_1_PAD_MSCK2_SEL_0_OFFSET (15) + #define RTL8373_IO_MUX_SEL_1_PAD_MSCK2_SEL_0_MASK (0x1 << RTL8373_IO_MUX_SEL_1_PAD_MSCK2_SEL_0_OFFSET) + #define RTL8373_IO_MUX_SEL_1_PAD_MSDA1_SEL_1_OFFSET (14) + #define RTL8373_IO_MUX_SEL_1_PAD_MSDA1_SEL_1_MASK (0x1 << RTL8373_IO_MUX_SEL_1_PAD_MSDA1_SEL_1_OFFSET) + #define RTL8373_IO_MUX_SEL_1_PAD_MSDA1_SEL_0_OFFSET (13) + #define RTL8373_IO_MUX_SEL_1_PAD_MSDA1_SEL_0_MASK (0x1 << RTL8373_IO_MUX_SEL_1_PAD_MSDA1_SEL_0_OFFSET) + #define RTL8373_IO_MUX_SEL_1_PAD_MSCK1_SEL_1_OFFSET (12) + #define RTL8373_IO_MUX_SEL_1_PAD_MSCK1_SEL_1_MASK (0x1 << RTL8373_IO_MUX_SEL_1_PAD_MSCK1_SEL_1_OFFSET) + #define RTL8373_IO_MUX_SEL_1_PAD_MSCK1_SEL_0_OFFSET (11) + #define RTL8373_IO_MUX_SEL_1_PAD_MSCK1_SEL_0_MASK (0x1 << RTL8373_IO_MUX_SEL_1_PAD_MSCK1_SEL_0_OFFSET) + #define RTL8373_IO_MUX_SEL_1_PAD_MSDA0_SEL_1_OFFSET (10) + #define RTL8373_IO_MUX_SEL_1_PAD_MSDA0_SEL_1_MASK (0x1 << RTL8373_IO_MUX_SEL_1_PAD_MSDA0_SEL_1_OFFSET) + #define RTL8373_IO_MUX_SEL_1_PAD_MSDA0_SEL_0_OFFSET (9) + #define RTL8373_IO_MUX_SEL_1_PAD_MSDA0_SEL_0_MASK (0x1 << RTL8373_IO_MUX_SEL_1_PAD_MSDA0_SEL_0_OFFSET) + #define RTL8373_IO_MUX_SEL_1_PAD_MSCK0_SEL_1_OFFSET (8) + #define RTL8373_IO_MUX_SEL_1_PAD_MSCK0_SEL_1_MASK (0x1 << RTL8373_IO_MUX_SEL_1_PAD_MSCK0_SEL_1_OFFSET) + #define RTL8373_IO_MUX_SEL_1_PAD_MSCK0_SEL_0_OFFSET (7) + #define RTL8373_IO_MUX_SEL_1_PAD_MSCK0_SEL_0_MASK (0x1 << RTL8373_IO_MUX_SEL_1_PAD_MSCK0_SEL_0_OFFSET) + #define RTL8373_IO_MUX_SEL_1_GPIO_MDX1_SEL_1_OFFSET (6) + #define RTL8373_IO_MUX_SEL_1_GPIO_MDX1_SEL_1_MASK (0x1 << RTL8373_IO_MUX_SEL_1_GPIO_MDX1_SEL_1_OFFSET) + #define RTL8373_IO_MUX_SEL_1_GPIO_MDX1_SEL_0_OFFSET (5) + #define RTL8373_IO_MUX_SEL_1_GPIO_MDX1_SEL_0_MASK (0x1 << RTL8373_IO_MUX_SEL_1_GPIO_MDX1_SEL_0_OFFSET) + #define RTL8373_IO_MUX_SEL_1_GPIO_MDIO0_SEL_OFFSET (4) + #define RTL8373_IO_MUX_SEL_1_GPIO_MDIO0_SEL_MASK (0x1 << RTL8373_IO_MUX_SEL_1_GPIO_MDIO0_SEL_OFFSET) + #define RTL8373_IO_MUX_SEL_1_GPIO_MDC0_SEL_OFFSET (3) + #define RTL8373_IO_MUX_SEL_1_GPIO_MDC0_SEL_MASK (0x1 << RTL8373_IO_MUX_SEL_1_GPIO_MDC0_SEL_OFFSET) + #define RTL8373_IO_MUX_SEL_1_GPIO_INT_SEL_OFFSET (2) + #define RTL8373_IO_MUX_SEL_1_GPIO_INT_SEL_MASK (0x1 << RTL8373_IO_MUX_SEL_1_GPIO_INT_SEL_OFFSET) + #define RTL8373_IO_MUX_SEL_1_PAD_UART0_SEL_1_OFFSET (1) + #define RTL8373_IO_MUX_SEL_1_PAD_UART0_SEL_1_MASK (0x1 << RTL8373_IO_MUX_SEL_1_PAD_UART0_SEL_1_OFFSET) + #define RTL8373_IO_MUX_SEL_1_PAD_UART0_SEL_0_OFFSET (0) + #define RTL8373_IO_MUX_SEL_1_PAD_UART0_SEL_0_MASK (0x1 << RTL8373_IO_MUX_SEL_1_PAD_UART0_SEL_0_OFFSET) + +#define RTL8373_IO_MUX_SEL_2_ADDR (0x7F94) + #define RTL8373_IO_MUX_SEL_2_ACL_BIT3_EN_OFFSET (3) + #define RTL8373_IO_MUX_SEL_2_ACL_BIT3_EN_MASK (0x1 << RTL8373_IO_MUX_SEL_2_ACL_BIT3_EN_OFFSET) + #define RTL8373_IO_MUX_SEL_2_ACL_BIT2_EN_OFFSET (2) + #define RTL8373_IO_MUX_SEL_2_ACL_BIT2_EN_MASK (0x1 << RTL8373_IO_MUX_SEL_2_ACL_BIT2_EN_OFFSET) + #define RTL8373_IO_MUX_SEL_2_ACL_BIT1_EN_OFFSET (1) + #define RTL8373_IO_MUX_SEL_2_ACL_BIT1_EN_MASK (0x1 << RTL8373_IO_MUX_SEL_2_ACL_BIT1_EN_OFFSET) + #define RTL8373_IO_MUX_SEL_2_ACL_BIT0_EN_OFFSET (0) + #define RTL8373_IO_MUX_SEL_2_ACL_BIT0_EN_MASK (0x1 << RTL8373_IO_MUX_SEL_2_ACL_BIT0_EN_OFFSET) + +#define RTL8373_IO_MUX_SEL_3_ADDR (0x7F98) + #define RTL8373_IO_MUX_SEL_3_IO_BISD_EN_OFFSET (0) + #define RTL8373_IO_MUX_SEL_3_IO_BISD_EN_MASK (0x1 << RTL8373_IO_MUX_SEL_3_IO_BISD_EN_OFFSET) + +#define RTL8373_DBG_MODE_ADDR (0x30) + #define RTL8373_DBG_MODE_DBG_SHIFT_OFFSET (0) + #define RTL8373_DBG_MODE_DBG_SHIFT_MASK (0x7 << RTL8373_DBG_MODE_DBG_SHIFT_OFFSET) + +#define RTL8373_DBG_PAD_CTRL_ADDR (0x34) + #define RTL8373_DBG_PAD_CTRL_DBG_PAD_CTRL_OFFSET (0) + #define RTL8373_DBG_PAD_CTRL_DBG_PAD_CTRL_MASK (0xFFFFFFFF << RTL8373_DBG_PAD_CTRL_DBG_PAD_CTRL_OFFSET) + +#define RTL8373_DBG_CTRL_ADR0_ADDR (0xC0B0) + #define RTL8373_DBG_CTRL_ADR0_DBG_ADR0_OFFSET (0) + #define RTL8373_DBG_CTRL_ADR0_DBG_ADR0_MASK (0xFFFF << RTL8373_DBG_CTRL_ADR0_DBG_ADR0_OFFSET) + +#define RTL8373_DBG_CTRL_ADR1_ADDR (0xC0B4) + #define RTL8373_DBG_CTRL_ADR1_DBG_ADR1_OFFSET (0) + #define RTL8373_DBG_CTRL_ADR1_DBG_ADR1_MASK (0xFFFF << RTL8373_DBG_CTRL_ADR1_DBG_ADR1_OFFSET) + +#define RTL8373_DBG_CTRL_ADR2_ADDR (0xC0B8) + #define RTL8373_DBG_CTRL_ADR2_DBG_ADR2_OFFSET (0) + #define RTL8373_DBG_CTRL_ADR2_DBG_ADR2_MASK (0xFFFF << RTL8373_DBG_CTRL_ADR2_DBG_ADR2_OFFSET) + +#define RTL8373_DBG_CTRL_ADR3_ADDR (0xC0BC) + #define RTL8373_DBG_CTRL_ADR3_DBG_ADR3_OFFSET (0) + #define RTL8373_DBG_CTRL_ADR3_DBG_ADR3_MASK (0xFFFF << RTL8373_DBG_CTRL_ADR3_DBG_ADR3_OFFSET) + +#define RTL8373_DBG_CTRL_SEL0_ADDR (0xC0C0) + #define RTL8373_DBG_CTRL_SEL0_DBG_SHIFT_SEL0_OFFSET (4) + #define RTL8373_DBG_CTRL_SEL0_DBG_SHIFT_SEL0_MASK (0x7 << RTL8373_DBG_CTRL_SEL0_DBG_SHIFT_SEL0_OFFSET) + #define RTL8373_DBG_CTRL_SEL0_DBG_BIT_SEL0_OFFSET (2) + #define RTL8373_DBG_CTRL_SEL0_DBG_BIT_SEL0_MASK (0x3 << RTL8373_DBG_CTRL_SEL0_DBG_BIT_SEL0_OFFSET) + #define RTL8373_DBG_CTRL_SEL0_DBG_BLK_SEL0_OFFSET (0) + #define RTL8373_DBG_CTRL_SEL0_DBG_BLK_SEL0_MASK (0x3 << RTL8373_DBG_CTRL_SEL0_DBG_BLK_SEL0_OFFSET) + +#define RTL8373_DBG_CTRL_SEL1_ADDR (0xC0C4) + #define RTL8373_DBG_CTRL_SEL1_DBG_SHIFT_SEL1_OFFSET (4) + #define RTL8373_DBG_CTRL_SEL1_DBG_SHIFT_SEL1_MASK (0x7 << RTL8373_DBG_CTRL_SEL1_DBG_SHIFT_SEL1_OFFSET) + #define RTL8373_DBG_CTRL_SEL1_DBG_BIT_SEL1_OFFSET (2) + #define RTL8373_DBG_CTRL_SEL1_DBG_BIT_SEL1_MASK (0x3 << RTL8373_DBG_CTRL_SEL1_DBG_BIT_SEL1_OFFSET) + #define RTL8373_DBG_CTRL_SEL1_DBG_BLK_SEL1_OFFSET (0) + #define RTL8373_DBG_CTRL_SEL1_DBG_BLK_SEL1_MASK (0x3 << RTL8373_DBG_CTRL_SEL1_DBG_BLK_SEL1_OFFSET) + +#define RTL8373_DBG_CTRL_SEL2_ADDR (0xC0C8) + #define RTL8373_DBG_CTRL_SEL2_DBG_SHIFT_SEL2_OFFSET (4) + #define RTL8373_DBG_CTRL_SEL2_DBG_SHIFT_SEL2_MASK (0x7 << RTL8373_DBG_CTRL_SEL2_DBG_SHIFT_SEL2_OFFSET) + #define RTL8373_DBG_CTRL_SEL2_DBG_BIT_SEL2_OFFSET (2) + #define RTL8373_DBG_CTRL_SEL2_DBG_BIT_SEL2_MASK (0x3 << RTL8373_DBG_CTRL_SEL2_DBG_BIT_SEL2_OFFSET) + #define RTL8373_DBG_CTRL_SEL2_DBG_BLK_SEL2_OFFSET (0) + #define RTL8373_DBG_CTRL_SEL2_DBG_BLK_SEL2_MASK (0x3 << RTL8373_DBG_CTRL_SEL2_DBG_BLK_SEL2_OFFSET) + +#define RTL8373_DBG_CTRL_SEL3_ADDR (0xC0CC) + #define RTL8373_DBG_CTRL_SEL3_DBG_SHIFT_SEL3_OFFSET (4) + #define RTL8373_DBG_CTRL_SEL3_DBG_SHIFT_SEL3_MASK (0x7 << RTL8373_DBG_CTRL_SEL3_DBG_SHIFT_SEL3_OFFSET) + #define RTL8373_DBG_CTRL_SEL3_DBG_BIT_SEL3_OFFSET (2) + #define RTL8373_DBG_CTRL_SEL3_DBG_BIT_SEL3_MASK (0x3 << RTL8373_DBG_CTRL_SEL3_DBG_BIT_SEL3_OFFSET) + #define RTL8373_DBG_CTRL_SEL3_DBG_BLK_SEL3_OFFSET (0) + #define RTL8373_DBG_CTRL_SEL3_DBG_BLK_SEL3_MASK (0x3 << RTL8373_DBG_CTRL_SEL3_DBG_BLK_SEL3_OFFSET) + +#define RTL8373_DBG_CTRL_VAL_ADDR (0xC0D0) + #define RTL8373_DBG_CTRL_VAL_DBG_OUT_OFFSET (0) + #define RTL8373_DBG_CTRL_VAL_DBG_OUT_MASK (0xFFFFFFFF << RTL8373_DBG_CTRL_VAL_DBG_OUT_OFFSET) + +#define RTL8373_FORCE_PU_PD_EN_0_ADDR (0x7F9C) + #define RTL8373_FORCE_PU_PD_EN_0_FORCE_PU_PD_EN_0_OFFSET (0) + #define RTL8373_FORCE_PU_PD_EN_0_FORCE_PU_PD_EN_0_MASK (0xFFFFFFFF << RTL8373_FORCE_PU_PD_EN_0_FORCE_PU_PD_EN_0_OFFSET) + +#define RTL8373_FORCE_PU_PD_EN_1_ADDR (0x7FA0) + #define RTL8373_FORCE_PU_PD_EN_1_FORCE_PU_PD_EN_1_OFFSET (0) + #define RTL8373_FORCE_PU_PD_EN_1_FORCE_PU_PD_EN_1_MASK (0xFFFFFFFF << RTL8373_FORCE_PU_PD_EN_1_FORCE_PU_PD_EN_1_OFFSET) + +#define RTL8373_FORCE_PU_0_ADDR (0x7FA4) + #define RTL8373_FORCE_PU_0_FORCE_PU_0_OFFSET (0) + #define RTL8373_FORCE_PU_0_FORCE_PU_0_MASK (0xFFFFFFFF << RTL8373_FORCE_PU_0_FORCE_PU_0_OFFSET) + +#define RTL8373_FORCE_PU_1_ADDR (0x7FA8) + #define RTL8373_FORCE_PU_1_FORCE_PU_1_OFFSET (0) + #define RTL8373_FORCE_PU_1_FORCE_PU_1_MASK (0xFFFFFFFF << RTL8373_FORCE_PU_1_FORCE_PU_1_OFFSET) + +#define RTL8373_FORCE_PD_0_ADDR (0x7FAC) + #define RTL8373_FORCE_PD_0_FORCE_PD_0_OFFSET (0) + #define RTL8373_FORCE_PD_0_FORCE_PD_0_MASK (0xFFFFFFFF << RTL8373_FORCE_PD_0_FORCE_PD_0_OFFSET) + +#define RTL8373_FORCE_PD_1_ADDR (0x7FB0) + #define RTL8373_FORCE_PD_1_FORCE_PD_1_OFFSET (0) + #define RTL8373_FORCE_PD_1_FORCE_PD_1_MASK (0xFFFFFFFF << RTL8373_FORCE_PD_1_FORCE_PD_1_OFFSET) + +#define RTL8373_CFG_PAD_MDIO0_DRV_MODE_ADDR (0x7FB4) + #define RTL8373_CFG_PAD_MDIO0_DRV_MODE_CFG_MDIO_DRV_PAD_OFFSET (0) + #define RTL8373_CFG_PAD_MDIO0_DRV_MODE_CFG_MDIO_DRV_PAD_MASK (0x1 << RTL8373_CFG_PAD_MDIO0_DRV_MODE_CFG_MDIO_DRV_PAD_OFFSET) + +#define RTL8373_VOLT_PROB_CTRL_ADDR (0x390) + #define RTL8373_VOLT_PROB_CTRL_LOW_VOLT_CH_FLAG_OFFSET (22) + #define RTL8373_VOLT_PROB_CTRL_LOW_VOLT_CH_FLAG_MASK (0xFF << RTL8373_VOLT_PROB_CTRL_LOW_VOLT_CH_FLAG_OFFSET) + #define RTL8373_VOLT_PROB_CTRL_VOLT_CMP_EN_OFFSET (21) + #define RTL8373_VOLT_PROB_CTRL_VOLT_CMP_EN_MASK (0x1 << RTL8373_VOLT_PROB_CTRL_VOLT_CMP_EN_OFFSET) + #define RTL8373_VOLT_PROB_CTRL_VOLT_THR_OFFSET (11) + #define RTL8373_VOLT_PROB_CTRL_VOLT_THR_MASK (0x3FF << RTL8373_VOLT_PROB_CTRL_VOLT_THR_OFFSET) + #define RTL8373_VOLT_PROB_CTRL_VOLT_PROB_PAD_OUT_EN_OFFSET (10) + #define RTL8373_VOLT_PROB_CTRL_VOLT_PROB_PAD_OUT_EN_MASK (0x1 << RTL8373_VOLT_PROB_CTRL_VOLT_PROB_PAD_OUT_EN_OFFSET) + #define RTL8373_VOLT_PROB_CTRL_VOLT_PROB_SEL_OFFSET (6) + #define RTL8373_VOLT_PROB_CTRL_VOLT_PROB_SEL_MASK (0xF << RTL8373_VOLT_PROB_CTRL_VOLT_PROB_SEL_OFFSET) + #define RTL8373_VOLT_PROB_CTRL_VOLT_PROB_RECORD_OFFSET (5) + #define RTL8373_VOLT_PROB_CTRL_VOLT_PROB_RECORD_MASK (0x1 << RTL8373_VOLT_PROB_CTRL_VOLT_PROB_RECORD_OFFSET) + #define RTL8373_VOLT_PROB_CTRL_POW_SAR_EN_OFFSET (4) + #define RTL8373_VOLT_PROB_CTRL_POW_SAR_EN_MASK (0x1 << RTL8373_VOLT_PROB_CTRL_POW_SAR_EN_OFFSET) + #define RTL8373_VOLT_PROB_CTRL_SAR_REF_OFFSET (1) + #define RTL8373_VOLT_PROB_CTRL_SAR_REF_MASK (0x7 << RTL8373_VOLT_PROB_CTRL_SAR_REF_OFFSET) + #define RTL8373_VOLT_PROB_CTRL_SAR_REG_WT_OFFSET (0) + #define RTL8373_VOLT_PROB_CTRL_SAR_REG_WT_MASK (0x1 << RTL8373_VOLT_PROB_CTRL_SAR_REG_WT_OFFSET) + +#define RTL8373_VOLT_PROB_RESULT0_ADDR (0x394) + #define RTL8373_VOLT_PROB_RESULT0_DOUT_CURRENT_OFFSET (0) + #define RTL8373_VOLT_PROB_RESULT0_DOUT_CURRENT_MASK (0x3FF << RTL8373_VOLT_PROB_RESULT0_DOUT_CURRENT_OFFSET) + +#define RTL8373_VOLT_PROB_RESULT1_ADDR (0x398) + #define RTL8373_VOLT_PROB_RESULT1_VOLT_PROB_MAX_OFFSET (16) + #define RTL8373_VOLT_PROB_RESULT1_VOLT_PROB_MAX_MASK (0x3FF << RTL8373_VOLT_PROB_RESULT1_VOLT_PROB_MAX_OFFSET) + #define RTL8373_VOLT_PROB_RESULT1_VOLT_PROB_MIN_OFFSET (0) + #define RTL8373_VOLT_PROB_RESULT1_VOLT_PROB_MIN_MASK (0x3FF << RTL8373_VOLT_PROB_RESULT1_VOLT_PROB_MIN_OFFSET) + +#define RTL8373_CFG_XTAL_ADDR (0x38) + #define RTL8373_CFG_XTAL_REG_CKREFBUF_CML_I_SDS_OFFSET (6) + #define RTL8373_CFG_XTAL_REG_CKREFBUF_CML_I_SDS_MASK (0x7 << RTL8373_CFG_XTAL_REG_CKREFBUF_CML_I_SDS_OFFSET) + #define RTL8373_CFG_XTAL_REG_CKREFBUF_CML_I_APHY_OFFSET (3) + #define RTL8373_CFG_XTAL_REG_CKREFBUF_CML_I_APHY_MASK (0x7 << RTL8373_CFG_XTAL_REG_CKREFBUF_CML_I_APHY_OFFSET) + #define RTL8373_CFG_XTAL_REG_CKREFBUF_EN_OFFSET (2) + #define RTL8373_CFG_XTAL_REG_CKREFBUF_EN_MASK (0x1 << RTL8373_CFG_XTAL_REG_CKREFBUF_EN_OFFSET) + #define RTL8373_CFG_XTAL_REG_CMU_TEST_EN_XTAL_OFFSET (1) + #define RTL8373_CFG_XTAL_REG_CMU_TEST_EN_XTAL_MASK (0x1 << RTL8373_CFG_XTAL_REG_CMU_TEST_EN_XTAL_OFFSET) + #define RTL8373_CFG_XTAL_REG_PIN_SEL_25M_TEST_EN_OFFSET (0) + #define RTL8373_CFG_XTAL_REG_PIN_SEL_25M_TEST_EN_MASK (0x1 << RTL8373_CFG_XTAL_REG_PIN_SEL_25M_TEST_EN_OFFSET) + +/* + * Feature: Wrapper_PHY + */ +#define RTL8373_CFG_EEE_FLG_DLY_ADDR (0x910) + #define RTL8373_CFG_EEE_FLG_DLY_SDS2PHY_EEE_FLG_DLY3_OFFSET (28) + #define RTL8373_CFG_EEE_FLG_DLY_SDS2PHY_EEE_FLG_DLY3_MASK (0xF << RTL8373_CFG_EEE_FLG_DLY_SDS2PHY_EEE_FLG_DLY3_OFFSET) + #define RTL8373_CFG_EEE_FLG_DLY_PHY2SDS_EEE_FLG_DLY3_OFFSET (24) + #define RTL8373_CFG_EEE_FLG_DLY_PHY2SDS_EEE_FLG_DLY3_MASK (0xF << RTL8373_CFG_EEE_FLG_DLY_PHY2SDS_EEE_FLG_DLY3_OFFSET) + #define RTL8373_CFG_EEE_FLG_DLY_SDS2PHY_EEE_FLG_DLY2_OFFSET (20) + #define RTL8373_CFG_EEE_FLG_DLY_SDS2PHY_EEE_FLG_DLY2_MASK (0xF << RTL8373_CFG_EEE_FLG_DLY_SDS2PHY_EEE_FLG_DLY2_OFFSET) + #define RTL8373_CFG_EEE_FLG_DLY_PHY2SDS_EEE_FLG_DLY2_OFFSET (16) + #define RTL8373_CFG_EEE_FLG_DLY_PHY2SDS_EEE_FLG_DLY2_MASK (0xF << RTL8373_CFG_EEE_FLG_DLY_PHY2SDS_EEE_FLG_DLY2_OFFSET) + #define RTL8373_CFG_EEE_FLG_DLY_SDS2PHY_EEE_FLG_DLY1_OFFSET (12) + #define RTL8373_CFG_EEE_FLG_DLY_SDS2PHY_EEE_FLG_DLY1_MASK (0xF << RTL8373_CFG_EEE_FLG_DLY_SDS2PHY_EEE_FLG_DLY1_OFFSET) + #define RTL8373_CFG_EEE_FLG_DLY_PHY2SDS_EEE_FLG_DLY1_OFFSET (8) + #define RTL8373_CFG_EEE_FLG_DLY_PHY2SDS_EEE_FLG_DLY1_MASK (0xF << RTL8373_CFG_EEE_FLG_DLY_PHY2SDS_EEE_FLG_DLY1_OFFSET) + #define RTL8373_CFG_EEE_FLG_DLY_SDS2PHY_EEE_FLG_DLY0_OFFSET (4) + #define RTL8373_CFG_EEE_FLG_DLY_SDS2PHY_EEE_FLG_DLY0_MASK (0xF << RTL8373_CFG_EEE_FLG_DLY_SDS2PHY_EEE_FLG_DLY0_OFFSET) + #define RTL8373_CFG_EEE_FLG_DLY_PHY2SDS_EEE_FLG_DLY0_OFFSET (0) + #define RTL8373_CFG_EEE_FLG_DLY_PHY2SDS_EEE_FLG_DLY0_MASK (0xF << RTL8373_CFG_EEE_FLG_DLY_PHY2SDS_EEE_FLG_DLY0_OFFSET) + +#define RTL8373_CFG_PHY_MDI_REVERSE_ADDR (0xA90) + #define RTL8373_CFG_PHY_MDI_REVERSE_P3_PHY_R_FRC_OFFSET (7) + #define RTL8373_CFG_PHY_MDI_REVERSE_P3_PHY_R_FRC_MASK (0x1 << RTL8373_CFG_PHY_MDI_REVERSE_P3_PHY_R_FRC_OFFSET) + #define RTL8373_CFG_PHY_MDI_REVERSE_P2_PHY_R_FRC_OFFSET (6) + #define RTL8373_CFG_PHY_MDI_REVERSE_P2_PHY_R_FRC_MASK (0x1 << RTL8373_CFG_PHY_MDI_REVERSE_P2_PHY_R_FRC_OFFSET) + #define RTL8373_CFG_PHY_MDI_REVERSE_P1_PHY_R_FRC_OFFSET (5) + #define RTL8373_CFG_PHY_MDI_REVERSE_P1_PHY_R_FRC_MASK (0x1 << RTL8373_CFG_PHY_MDI_REVERSE_P1_PHY_R_FRC_OFFSET) + #define RTL8373_CFG_PHY_MDI_REVERSE_P0_PHY_R_FRC_OFFSET (4) + #define RTL8373_CFG_PHY_MDI_REVERSE_P0_PHY_R_FRC_MASK (0x1 << RTL8373_CFG_PHY_MDI_REVERSE_P0_PHY_R_FRC_OFFSET) + #define RTL8373_CFG_PHY_MDI_REVERSE_P3_MDI_REVERSE_OFFSET (3) + #define RTL8373_CFG_PHY_MDI_REVERSE_P3_MDI_REVERSE_MASK (0x1 << RTL8373_CFG_PHY_MDI_REVERSE_P3_MDI_REVERSE_OFFSET) + #define RTL8373_CFG_PHY_MDI_REVERSE_P2_MDI_REVERSE_OFFSET (2) + #define RTL8373_CFG_PHY_MDI_REVERSE_P2_MDI_REVERSE_MASK (0x1 << RTL8373_CFG_PHY_MDI_REVERSE_P2_MDI_REVERSE_OFFSET) + #define RTL8373_CFG_PHY_MDI_REVERSE_P1_MDI_REVERSE_OFFSET (1) + #define RTL8373_CFG_PHY_MDI_REVERSE_P1_MDI_REVERSE_MASK (0x1 << RTL8373_CFG_PHY_MDI_REVERSE_P1_MDI_REVERSE_OFFSET) + #define RTL8373_CFG_PHY_MDI_REVERSE_P0_MDI_REVERSE_OFFSET (0) + #define RTL8373_CFG_PHY_MDI_REVERSE_P0_MDI_REVERSE_MASK (0x1 << RTL8373_CFG_PHY_MDI_REVERSE_P0_MDI_REVERSE_OFFSET) + +#define RTL8373_CFG_PHY_TX_POLARITY_SWAP_ADDR (0xA94) + #define RTL8373_CFG_PHY_TX_POLARITY_SWAP_P3_TX_POLARITY_SWAP_OFFSET (12) + #define RTL8373_CFG_PHY_TX_POLARITY_SWAP_P3_TX_POLARITY_SWAP_MASK (0xF << RTL8373_CFG_PHY_TX_POLARITY_SWAP_P3_TX_POLARITY_SWAP_OFFSET) + #define RTL8373_CFG_PHY_TX_POLARITY_SWAP_P2_TX_POLARITY_SWAP_OFFSET (8) + #define RTL8373_CFG_PHY_TX_POLARITY_SWAP_P2_TX_POLARITY_SWAP_MASK (0xF << RTL8373_CFG_PHY_TX_POLARITY_SWAP_P2_TX_POLARITY_SWAP_OFFSET) + #define RTL8373_CFG_PHY_TX_POLARITY_SWAP_P1_TX_POLARITY_SWAP_OFFSET (4) + #define RTL8373_CFG_PHY_TX_POLARITY_SWAP_P1_TX_POLARITY_SWAP_MASK (0xF << RTL8373_CFG_PHY_TX_POLARITY_SWAP_P1_TX_POLARITY_SWAP_OFFSET) + #define RTL8373_CFG_PHY_TX_POLARITY_SWAP_P0_TX_POLARITY_SWAP_OFFSET (0) + #define RTL8373_CFG_PHY_TX_POLARITY_SWAP_P0_TX_POLARITY_SWAP_MASK (0xF << RTL8373_CFG_PHY_TX_POLARITY_SWAP_P0_TX_POLARITY_SWAP_OFFSET) + +#define RTL8373_CFG_PHY_OCP_TIMEOUT_ADDR (0xA98) + #define RTL8373_CFG_PHY_OCP_TIMEOUT_PHY_OCP_TOF_OFFSET (8) + #define RTL8373_CFG_PHY_OCP_TIMEOUT_PHY_OCP_TOF_MASK (0xF << RTL8373_CFG_PHY_OCP_TIMEOUT_PHY_OCP_TOF_OFFSET) + #define RTL8373_CFG_PHY_OCP_TIMEOUT_PHY_OCP_TO_OFFSET (0) + #define RTL8373_CFG_PHY_OCP_TIMEOUT_PHY_OCP_TO_MASK (0xFF << RTL8373_CFG_PHY_OCP_TIMEOUT_PHY_OCP_TO_OFFSET) + +#define RTL8373_CFG_PHY_PCSXF_1_ADDR (0xA9C) + #define RTL8373_CFG_PHY_PCSXF_1_PCSXF_RXFIFO_ERR_FLAG_OFFSET (9) + #define RTL8373_CFG_PHY_PCSXF_1_PCSXF_RXFIFO_ERR_FLAG_MASK (0xF << RTL8373_CFG_PHY_PCSXF_1_PCSXF_RXFIFO_ERR_FLAG_OFFSET) + #define RTL8373_CFG_PHY_PCSXF_1_PCSXF_RST_RXFIFO_OFFSET (5) + #define RTL8373_CFG_PHY_PCSXF_1_PCSXF_RST_RXFIFO_MASK (0xF << RTL8373_CFG_PHY_PCSXF_1_PCSXF_RST_RXFIFO_OFFSET) + #define RTL8373_CFG_PHY_PCSXF_1_PCSXF_MCFG_OFFSET (1) + #define RTL8373_CFG_PHY_PCSXF_1_PCSXF_MCFG_MASK (0xF << RTL8373_CFG_PHY_PCSXF_1_PCSXF_MCFG_OFFSET) + #define RTL8373_CFG_PHY_PCSXF_1_COL_10M_OFFSET (0) + #define RTL8373_CFG_PHY_PCSXF_1_COL_10M_MASK (0x1 << RTL8373_CFG_PHY_PCSXF_1_COL_10M_OFFSET) + +#define RTL8373_CFG_PHY_PCSXF_2_ADDR (0xAA0) + #define RTL8373_CFG_PHY_PCSXF_2_PCSXF_MIIRX_IPG_OFFSET (8) + #define RTL8373_CFG_PHY_PCSXF_2_PCSXF_MIIRX_IPG_MASK (0x1F << RTL8373_CFG_PHY_PCSXF_2_PCSXF_MIIRX_IPG_OFFSET) + #define RTL8373_CFG_PHY_PCSXF_2_PCSXF_STOP_TXC_OFFSET (4) + #define RTL8373_CFG_PHY_PCSXF_2_PCSXF_STOP_TXC_MASK (0xF << RTL8373_CFG_PHY_PCSXF_2_PCSXF_STOP_TXC_OFFSET) + #define RTL8373_CFG_PHY_PCSXF_2_PCSXF_STOP_RXC_OFFSET (0) + #define RTL8373_CFG_PHY_PCSXF_2_PCSXF_STOP_RXC_MASK (0xF << RTL8373_CFG_PHY_PCSXF_2_PCSXF_STOP_RXC_OFFSET) + +#define RTL8373_CFG_PHY_G2XG_IPG_ADDR (0xAA4) + #define RTL8373_CFG_PHY_G2XG_IPG_G2XG_GTX_MIN_IPG_OFFSET (4) + #define RTL8373_CFG_PHY_G2XG_IPG_G2XG_GTX_MIN_IPG_MASK (0xF << RTL8373_CFG_PHY_G2XG_IPG_G2XG_GTX_MIN_IPG_OFFSET) + #define RTL8373_CFG_PHY_G2XG_IPG_G2XG_GRX_MIN_IPG_OFFSET (0) + #define RTL8373_CFG_PHY_G2XG_IPG_G2XG_GRX_MIN_IPG_MASK (0xF << RTL8373_CFG_PHY_G2XG_IPG_G2XG_GRX_MIN_IPG_OFFSET) + +#define RTL8373_CFG_PHY_G2XG_FIFO_THR_ADDR (0xAA8) + #define RTL8373_CFG_PHY_G2XG_FIFO_THR_CFG_LDN_CLR_FIFO_RX_OFFSET (13) + #define RTL8373_CFG_PHY_G2XG_FIFO_THR_CFG_LDN_CLR_FIFO_RX_MASK (0x1 << RTL8373_CFG_PHY_G2XG_FIFO_THR_CFG_LDN_CLR_FIFO_RX_OFFSET) + #define RTL8373_CFG_PHY_G2XG_FIFO_THR_CFG_LDN_CLR_FIFO_TX_OFFSET (12) + #define RTL8373_CFG_PHY_G2XG_FIFO_THR_CFG_LDN_CLR_FIFO_TX_MASK (0x1 << RTL8373_CFG_PHY_G2XG_FIFO_THR_CFG_LDN_CLR_FIFO_TX_OFFSET) + #define RTL8373_CFG_PHY_G2XG_FIFO_THR_CFG_MDY_XG_EEE_LPI_TX_OFFSET (11) + #define RTL8373_CFG_PHY_G2XG_FIFO_THR_CFG_MDY_XG_EEE_LPI_TX_MASK (0x1 << RTL8373_CFG_PHY_G2XG_FIFO_THR_CFG_MDY_XG_EEE_LPI_TX_OFFSET) + #define RTL8373_CFG_PHY_G2XG_FIFO_THR_CFG_MDY_G_EEE_LPI_RX_OFFSET (10) + #define RTL8373_CFG_PHY_G2XG_FIFO_THR_CFG_MDY_G_EEE_LPI_RX_MASK (0x1 << RTL8373_CFG_PHY_G2XG_FIFO_THR_CFG_MDY_G_EEE_LPI_RX_OFFSET) + #define RTL8373_CFG_PHY_G2XG_FIFO_THR_G2XG_TX_RDFIFO_THR_OFFSET (4) + #define RTL8373_CFG_PHY_G2XG_FIFO_THR_G2XG_TX_RDFIFO_THR_MASK (0x3F << RTL8373_CFG_PHY_G2XG_FIFO_THR_G2XG_TX_RDFIFO_THR_OFFSET) + #define RTL8373_CFG_PHY_G2XG_FIFO_THR_G2XG_RX_RDFIFO_THR_OFFSET (0) + #define RTL8373_CFG_PHY_G2XG_FIFO_THR_G2XG_RX_RDFIFO_THR_MASK (0xF << RTL8373_CFG_PHY_G2XG_FIFO_THR_G2XG_RX_RDFIFO_THR_OFFSET) + +#define RTL8373_CFG_PHY_G2XG_AUTORST_ADDR (0xAAC) + #define RTL8373_CFG_PHY_G2XG_AUTORST_G2XG_EN_AUTO_RST_OFFSET (0) + #define RTL8373_CFG_PHY_G2XG_AUTORST_G2XG_EN_AUTO_RST_MASK (0xFFFF << RTL8373_CFG_PHY_G2XG_AUTORST_G2XG_EN_AUTO_RST_OFFSET) + +#define RTL8373_CFG_PHY_G2XG_MISC_ADDR (0xAB0) + #define RTL8373_CFG_PHY_G2XG_MISC_G2XG_EN_ECODE_OFFSET (12) + #define RTL8373_CFG_PHY_G2XG_MISC_G2XG_EN_ECODE_MASK (0xF << RTL8373_CFG_PHY_G2XG_MISC_G2XG_EN_ECODE_OFFSET) + #define RTL8373_CFG_PHY_G2XG_MISC_G2XG_BYPASS_BCH_OFFSET (8) + #define RTL8373_CFG_PHY_G2XG_MISC_G2XG_BYPASS_BCH_MASK (0xF << RTL8373_CFG_PHY_G2XG_MISC_G2XG_BYPASS_BCH_OFFSET) + #define RTL8373_CFG_PHY_G2XG_MISC_G2XG_EN_G_LPI_OFFSET (4) + #define RTL8373_CFG_PHY_G2XG_MISC_G2XG_EN_G_LPI_MASK (0xF << RTL8373_CFG_PHY_G2XG_MISC_G2XG_EN_G_LPI_OFFSET) + #define RTL8373_CFG_PHY_G2XG_MISC_G2XG_EN_XG_LPI_OFFSET (0) + #define RTL8373_CFG_PHY_G2XG_MISC_G2XG_EN_XG_LPI_MASK (0xF << RTL8373_CFG_PHY_G2XG_MISC_G2XG_EN_XG_LPI_OFFSET) + +#define RTL8373_CFG_PHY_G2XG_MODULE_RST_ADDR (0xAB4) + #define RTL8373_CFG_PHY_G2XG_MODULE_RST_CFG_G_EEE_LPI_RX_DLY_EN_OFFSET (13) + #define RTL8373_CFG_PHY_G2XG_MODULE_RST_CFG_G_EEE_LPI_RX_DLY_EN_MASK (0x1 << RTL8373_CFG_PHY_G2XG_MODULE_RST_CFG_G_EEE_LPI_RX_DLY_EN_OFFSET) + #define RTL8373_CFG_PHY_G2XG_MODULE_RST_CFG_XG_EEE_LPI_TX_DLY_EN_OFFSET (12) + #define RTL8373_CFG_PHY_G2XG_MODULE_RST_CFG_XG_EEE_LPI_TX_DLY_EN_MASK (0x1 << RTL8373_CFG_PHY_G2XG_MODULE_RST_CFG_XG_EEE_LPI_TX_DLY_EN_OFFSET) + #define RTL8373_CFG_PHY_G2XG_MODULE_RST_CFG_G_EEE_LPI_RX_SHIFT_OFFSET (8) + #define RTL8373_CFG_PHY_G2XG_MODULE_RST_CFG_G_EEE_LPI_RX_SHIFT_MASK (0xF << RTL8373_CFG_PHY_G2XG_MODULE_RST_CFG_G_EEE_LPI_RX_SHIFT_OFFSET) + #define RTL8373_CFG_PHY_G2XG_MODULE_RST_CFG_XG_EEE_LPI_TX_SHIFT_OFFSET (4) + #define RTL8373_CFG_PHY_G2XG_MODULE_RST_CFG_XG_EEE_LPI_TX_SHIFT_MASK (0xF << RTL8373_CFG_PHY_G2XG_MODULE_RST_CFG_XG_EEE_LPI_TX_SHIFT_OFFSET) + #define RTL8373_CFG_PHY_G2XG_MODULE_RST_G2XG_MODULE_RST_OFFSET (0) + #define RTL8373_CFG_PHY_G2XG_MODULE_RST_G2XG_MODULE_RST_MASK (0xF << RTL8373_CFG_PHY_G2XG_MODULE_RST_G2XG_MODULE_RST_OFFSET) + +#define RTL8373_P0_PHY_G2XG_BCH_ERR_FLAG_ADDR (0xAB8) + #define RTL8373_P0_PHY_G2XG_BCH_ERR_FLAG_P0_G2XG_BCH_ERR_FLAG_OFFSET (0) + #define RTL8373_P0_PHY_G2XG_BCH_ERR_FLAG_P0_G2XG_BCH_ERR_FLAG_MASK (0xFFFF << RTL8373_P0_PHY_G2XG_BCH_ERR_FLAG_P0_G2XG_BCH_ERR_FLAG_OFFSET) + +#define RTL8373_P1_PHY_G2XG_BCH_ERR_FLAG_ADDR (0xABC) + #define RTL8373_P1_PHY_G2XG_BCH_ERR_FLAG_P1_G2XG_BCH_ERR_FLAG_OFFSET (0) + #define RTL8373_P1_PHY_G2XG_BCH_ERR_FLAG_P1_G2XG_BCH_ERR_FLAG_MASK (0xFFFF << RTL8373_P1_PHY_G2XG_BCH_ERR_FLAG_P1_G2XG_BCH_ERR_FLAG_OFFSET) + +#define RTL8373_P2_PHY_G2XG_BCH_ERR_FLAG_ADDR (0xAC0) + #define RTL8373_P2_PHY_G2XG_BCH_ERR_FLAG_P2_G2XG_BCH_ERR_FLAG_OFFSET (0) + #define RTL8373_P2_PHY_G2XG_BCH_ERR_FLAG_P2_G2XG_BCH_ERR_FLAG_MASK (0xFFFF << RTL8373_P2_PHY_G2XG_BCH_ERR_FLAG_P2_G2XG_BCH_ERR_FLAG_OFFSET) + +#define RTL8373_P3_PHY_G2XG_BCH_ERR_FLAG_ADDR (0xAC4) + #define RTL8373_P3_PHY_G2XG_BCH_ERR_FLAG_P3_G2XG_BCH_ERR_FLAG_OFFSET (0) + #define RTL8373_P3_PHY_G2XG_BCH_ERR_FLAG_P3_G2XG_BCH_ERR_FLAG_MASK (0xFFFF << RTL8373_P3_PHY_G2XG_BCH_ERR_FLAG_P3_G2XG_BCH_ERR_FLAG_OFFSET) + +#define RTL8373_CFG_PHY_MISC_ADDR (0xAC8) + #define RTL8373_CFG_PHY_MISC_WRAP_PHY_DBG_OFFSET (16) + #define RTL8373_CFG_PHY_MISC_WRAP_PHY_DBG_MASK (0xFF << RTL8373_CFG_PHY_MISC_WRAP_PHY_DBG_OFFSET) + #define RTL8373_CFG_PHY_MISC_DCO_CLK_SRC_OFFSET (15) + #define RTL8373_CFG_PHY_MISC_DCO_CLK_SRC_MASK (0x1 << RTL8373_CFG_PHY_MISC_DCO_CLK_SRC_OFFSET) + #define RTL8373_CFG_PHY_MISC_PHY_MISC_FAULT_ON_OFFSET (14) + #define RTL8373_CFG_PHY_MISC_PHY_MISC_FAULT_ON_MASK (0x1 << RTL8373_CFG_PHY_MISC_PHY_MISC_FAULT_ON_OFFSET) + #define RTL8373_CFG_PHY_MISC_UNIDIR_EN_OFFSET (13) + #define RTL8373_CFG_PHY_MISC_UNIDIR_EN_MASK (0x1 << RTL8373_CFG_PHY_MISC_UNIDIR_EN_OFFSET) + #define RTL8373_CFG_PHY_MISC_QHSGMII_EEE_EN_OFFSET (12) + #define RTL8373_CFG_PHY_MISC_QHSGMII_EEE_EN_MASK (0x1 << RTL8373_CFG_PHY_MISC_QHSGMII_EEE_EN_OFFSET) + #define RTL8373_CFG_PHY_MISC_STRP_DIS_POR_DBG_8224_OFFSET (10) + #define RTL8373_CFG_PHY_MISC_STRP_DIS_POR_DBG_8224_MASK (0x1 << RTL8373_CFG_PHY_MISC_STRP_DIS_POR_DBG_8224_OFFSET) + #define RTL8373_CFG_PHY_MISC_CFG_BYP_SDS_LDN_OFFSET (9) + #define RTL8373_CFG_PHY_MISC_CFG_BYP_SDS_LDN_MASK (0x1 << RTL8373_CFG_PHY_MISC_CFG_BYP_SDS_LDN_OFFSET) + #define RTL8373_CFG_PHY_MISC_CFG_BYP_PHY_LDN_OFFSET (8) + #define RTL8373_CFG_PHY_MISC_CFG_BYP_PHY_LDN_MASK (0x1 << RTL8373_CFG_PHY_MISC_CFG_BYP_PHY_LDN_OFFSET) + #define RTL8373_CFG_PHY_MISC_CFG_312P5_CLK_SEL_OFFSET (4) + #define RTL8373_CFG_PHY_MISC_CFG_312P5_CLK_SEL_MASK (0xF << RTL8373_CFG_PHY_MISC_CFG_312P5_CLK_SEL_OFFSET) + #define RTL8373_CFG_PHY_MISC_MDI_BRD_MSK_OFFSET (0) + #define RTL8373_CFG_PHY_MISC_MDI_BRD_MSK_MASK (0xF << RTL8373_CFG_PHY_MISC_MDI_BRD_MSK_OFFSET) + +#define RTL8373_PHY_LINK_FAULT_STS_ADDR (0xACC) + #define RTL8373_PHY_LINK_FAULT_STS_P3_LINK_FAULT_STS_OFFSET (9) + #define RTL8373_PHY_LINK_FAULT_STS_P3_LINK_FAULT_STS_MASK (0x7 << RTL8373_PHY_LINK_FAULT_STS_P3_LINK_FAULT_STS_OFFSET) + #define RTL8373_PHY_LINK_FAULT_STS_P2_LINK_FAULT_STS_OFFSET (6) + #define RTL8373_PHY_LINK_FAULT_STS_P2_LINK_FAULT_STS_MASK (0x7 << RTL8373_PHY_LINK_FAULT_STS_P2_LINK_FAULT_STS_OFFSET) + #define RTL8373_PHY_LINK_FAULT_STS_P1_LINK_FAULT_STS_OFFSET (3) + #define RTL8373_PHY_LINK_FAULT_STS_P1_LINK_FAULT_STS_MASK (0x7 << RTL8373_PHY_LINK_FAULT_STS_P1_LINK_FAULT_STS_OFFSET) + #define RTL8373_PHY_LINK_FAULT_STS_P0_LINK_FAULT_STS_OFFSET (0) + #define RTL8373_PHY_LINK_FAULT_STS_P0_LINK_FAULT_STS_MASK (0x7 << RTL8373_PHY_LINK_FAULT_STS_P0_LINK_FAULT_STS_OFFSET) + +#define RTL8373_CFG_PHY_BRD_ADDR (0xAD0) + #define RTL8373_CFG_PHY_BRD_PHY_BASE_ADR_OFFSET (9) + #define RTL8373_CFG_PHY_BRD_PHY_BASE_ADR_MASK (0x1F << RTL8373_CFG_PHY_BRD_PHY_BASE_ADR_OFFSET) + #define RTL8373_CFG_PHY_BRD_PHY_BRD_MODE_OFFSET (5) + #define RTL8373_CFG_PHY_BRD_PHY_BRD_MODE_MASK (0xF << RTL8373_CFG_PHY_BRD_PHY_BRD_MODE_OFFSET) + #define RTL8373_CFG_PHY_BRD_PHY_BRD_ADR_OFFSET (0) + #define RTL8373_CFG_PHY_BRD_PHY_BRD_ADR_MASK (0x1F << RTL8373_CFG_PHY_BRD_PHY_BRD_ADR_OFFSET) + +#define RTL8373_CFG_PHY_INI_ADDR (0xAD4) + #define RTL8373_CFG_PHY_INI_PHY_INI_POWER_DOWN_OFFSET (16) + #define RTL8373_CFG_PHY_INI_PHY_INI_POWER_DOWN_MASK (0xF << RTL8373_CFG_PHY_INI_PHY_INI_POWER_DOWN_OFFSET) + #define RTL8373_CFG_PHY_INI_BYPS_CHK_INI_OFFSET (2) + #define RTL8373_CFG_PHY_INI_BYPS_CHK_INI_MASK (0x1 << RTL8373_CFG_PHY_INI_BYPS_CHK_INI_OFFSET) + #define RTL8373_CFG_PHY_INI_PHY_INI_DISGIGA_OFFSET (1) + #define RTL8373_CFG_PHY_INI_PHY_INI_DISGIGA_MASK (0x1 << RTL8373_CFG_PHY_INI_PHY_INI_DISGIGA_OFFSET) + #define RTL8373_CFG_PHY_INI_PHY_INI_EEE_EN_OFFSET (0) + #define RTL8373_CFG_PHY_INI_PHY_INI_EEE_EN_MASK (0x1 << RTL8373_CFG_PHY_INI_PHY_INI_EEE_EN_OFFSET) + +#define RTL8373_CFG_PHY_POLL_CMD1_ADDR (0xAD8) + #define RTL8373_CFG_PHY_POLL_CMD1_PHY_SDET_SEL_OFFSET (12) + #define RTL8373_CFG_PHY_POLL_CMD1_PHY_SDET_SEL_MASK (0x3 << RTL8373_CFG_PHY_POLL_CMD1_PHY_SDET_SEL_OFFSET) + #define RTL8373_CFG_PHY_POLL_CMD1_CMD_WRMSK_EN_OFFSET (8) + #define RTL8373_CFG_PHY_POLL_CMD1_CMD_WRMSK_EN_MASK (0xF << RTL8373_CFG_PHY_POLL_CMD1_CMD_WRMSK_EN_OFFSET) + #define RTL8373_CFG_PHY_POLL_CMD1_CMD_WR_EN_OFFSET (4) + #define RTL8373_CFG_PHY_POLL_CMD1_CMD_WR_EN_MASK (0xF << RTL8373_CFG_PHY_POLL_CMD1_CMD_WR_EN_OFFSET) + #define RTL8373_CFG_PHY_POLL_CMD1_CMD_RD_EN_OFFSET (0) + #define RTL8373_CFG_PHY_POLL_CMD1_CMD_RD_EN_MASK (0xF << RTL8373_CFG_PHY_POLL_CMD1_CMD_RD_EN_OFFSET) + +#define RTL8373_CFG_PHY_POLL_CMD2_ADDR (0xADC) + #define RTL8373_CFG_PHY_POLL_CMD2_CMD_PRD_OFFSET (8) + #define RTL8373_CFG_PHY_POLL_CMD2_CMD_PRD_MASK (0x1F << RTL8373_CFG_PHY_POLL_CMD2_CMD_PRD_OFFSET) + #define RTL8373_CFG_PHY_POLL_CMD2_HOTCMD_PRD_EN_OFFSET (3) + #define RTL8373_CFG_PHY_POLL_CMD2_HOTCMD_PRD_EN_MASK (0x1 << RTL8373_CFG_PHY_POLL_CMD2_HOTCMD_PRD_EN_OFFSET) + #define RTL8373_CFG_PHY_POLL_CMD2_HOTCMD_EN_OFFSET (0) + #define RTL8373_CFG_PHY_POLL_CMD2_HOTCMD_EN_MASK (0x7 << RTL8373_CFG_PHY_POLL_CMD2_HOTCMD_EN_OFFSET) + +#define RTL8373_CFG_PHY_HOTCMD1_ADR_ADDR (0xAE0) + #define RTL8373_CFG_PHY_HOTCMD1_ADR_HOTCMD1_ADR_OFFSET (0) + #define RTL8373_CFG_PHY_HOTCMD1_ADR_HOTCMD1_ADR_MASK (0xFFFF << RTL8373_CFG_PHY_HOTCMD1_ADR_HOTCMD1_ADR_OFFSET) + +#define RTL8373_CFG_PHY_HOTCMD1_DAT_ADDR (0xAE4) + #define RTL8373_CFG_PHY_HOTCMD1_DAT_HOTCMD1_DAT_OFFSET (0) + #define RTL8373_CFG_PHY_HOTCMD1_DAT_HOTCMD1_DAT_MASK (0xFFFF << RTL8373_CFG_PHY_HOTCMD1_DAT_HOTCMD1_DAT_OFFSET) + +#define RTL8373_P0_XG2XG_IPG_DBG_INFO_ADDR (0x914) + #define RTL8373_P0_XG2XG_IPG_DBG_INFO_CFG_P0_DBG_INFO_OFF_OFFSET (15) + #define RTL8373_P0_XG2XG_IPG_DBG_INFO_CFG_P0_DBG_INFO_OFF_MASK (0x1 << RTL8373_P0_XG2XG_IPG_DBG_INFO_CFG_P0_DBG_INFO_OFF_OFFSET) + #define RTL8373_P0_XG2XG_IPG_DBG_INFO_CFG_P0_CUR_IPG_OFFSET (10) + #define RTL8373_P0_XG2XG_IPG_DBG_INFO_CFG_P0_CUR_IPG_MASK (0x1F << RTL8373_P0_XG2XG_IPG_DBG_INFO_CFG_P0_CUR_IPG_OFFSET) + #define RTL8373_P0_XG2XG_IPG_DBG_INFO_CFG_P0_MAX_IPG_OFFSET (5) + #define RTL8373_P0_XG2XG_IPG_DBG_INFO_CFG_P0_MAX_IPG_MASK (0x1F << RTL8373_P0_XG2XG_IPG_DBG_INFO_CFG_P0_MAX_IPG_OFFSET) + #define RTL8373_P0_XG2XG_IPG_DBG_INFO_CFG_P0_MIN_IPG_OFFSET (0) + #define RTL8373_P0_XG2XG_IPG_DBG_INFO_CFG_P0_MIN_IPG_MASK (0x1F << RTL8373_P0_XG2XG_IPG_DBG_INFO_CFG_P0_MIN_IPG_OFFSET) + +#define RTL8373_P0_XG2XG_PRMB_DBG_INFO_ADDR (0x918) + #define RTL8373_P0_XG2XG_PRMB_DBG_INFO_CFG_P0_CUR_PRMB_OFFSET (8) + #define RTL8373_P0_XG2XG_PRMB_DBG_INFO_CFG_P0_CUR_PRMB_MASK (0xF << RTL8373_P0_XG2XG_PRMB_DBG_INFO_CFG_P0_CUR_PRMB_OFFSET) + #define RTL8373_P0_XG2XG_PRMB_DBG_INFO_CFG_P0_MAX_PRMB_OFFSET (4) + #define RTL8373_P0_XG2XG_PRMB_DBG_INFO_CFG_P0_MAX_PRMB_MASK (0xF << RTL8373_P0_XG2XG_PRMB_DBG_INFO_CFG_P0_MAX_PRMB_OFFSET) + #define RTL8373_P0_XG2XG_PRMB_DBG_INFO_CFG_P0_MIN_PRMB_OFFSET (0) + #define RTL8373_P0_XG2XG_PRMB_DBG_INFO_CFG_P0_MIN_PRMB_MASK (0xF << RTL8373_P0_XG2XG_PRMB_DBG_INFO_CFG_P0_MIN_PRMB_OFFSET) + +#define RTL8373_P0_XG2XG_THR_DBG_INFO_ADDR (0x91C) + #define RTL8373_P0_XG2XG_THR_DBG_INFO_CFG_P0_CUR_THR_OFFSET (6) + #define RTL8373_P0_XG2XG_THR_DBG_INFO_CFG_P0_CUR_THR_MASK (0x3F << RTL8373_P0_XG2XG_THR_DBG_INFO_CFG_P0_CUR_THR_OFFSET) + #define RTL8373_P0_XG2XG_THR_DBG_INFO_CFG_P0_MAX_THR_OFFSET (0) + #define RTL8373_P0_XG2XG_THR_DBG_INFO_CFG_P0_MAX_THR_MASK (0x3F << RTL8373_P0_XG2XG_THR_DBG_INFO_CFG_P0_MAX_THR_OFFSET) + +#define RTL8373_CFG_PHY_POLL_ADR0_ADDR (0xAE8) + #define RTL8373_CFG_PHY_POLL_ADR0_CMD0_ADR_OFFSET (0) + #define RTL8373_CFG_PHY_POLL_ADR0_CMD0_ADR_MASK (0xFFFF << RTL8373_CFG_PHY_POLL_ADR0_CMD0_ADR_OFFSET) + +#define RTL8373_CFG_PHY_POLL_ADR1_ADDR (0xAEC) + #define RTL8373_CFG_PHY_POLL_ADR1_CMD1_ADR_OFFSET (0) + #define RTL8373_CFG_PHY_POLL_ADR1_CMD1_ADR_MASK (0xFFFF << RTL8373_CFG_PHY_POLL_ADR1_CMD1_ADR_OFFSET) + +#define RTL8373_CFG_PHY_POLL_ADR2_ADDR (0xAF0) + #define RTL8373_CFG_PHY_POLL_ADR2_CMD2_ADR_OFFSET (0) + #define RTL8373_CFG_PHY_POLL_ADR2_CMD2_ADR_MASK (0xFFFF << RTL8373_CFG_PHY_POLL_ADR2_CMD2_ADR_OFFSET) + +#define RTL8373_CFG_PHY_POLL_ADR3_ADDR (0xAF4) + #define RTL8373_CFG_PHY_POLL_ADR3_CMD3_ADR_OFFSET (0) + #define RTL8373_CFG_PHY_POLL_ADR3_CMD3_ADR_MASK (0xFFFF << RTL8373_CFG_PHY_POLL_ADR3_CMD3_ADR_OFFSET) + +#define RTL8373_CFG_PHY_POLL_INV0_ADDR (0xAF8) + #define RTL8373_CFG_PHY_POLL_INV0_CMD0_INV_OFFSET (0) + #define RTL8373_CFG_PHY_POLL_INV0_CMD0_INV_MASK (0xFFFF << RTL8373_CFG_PHY_POLL_INV0_CMD0_INV_OFFSET) + +#define RTL8373_CFG_PHY_POLL_INV1_ADDR (0xAFC) + #define RTL8373_CFG_PHY_POLL_INV1_CMD1_INV_OFFSET (0) + #define RTL8373_CFG_PHY_POLL_INV1_CMD1_INV_MASK (0xFFFF << RTL8373_CFG_PHY_POLL_INV1_CMD1_INV_OFFSET) + +#define RTL8373_CFG_PHY_POLL_INV2_ADDR (0xB00) + #define RTL8373_CFG_PHY_POLL_INV2_CMD2_INV_OFFSET (0) + #define RTL8373_CFG_PHY_POLL_INV2_CMD2_INV_MASK (0xFFFF << RTL8373_CFG_PHY_POLL_INV2_CMD2_INV_OFFSET) + +#define RTL8373_CFG_PHY_POLL_INV3_ADDR (0xB04) + #define RTL8373_CFG_PHY_POLL_INV3_CMD3_INV_OFFSET (0) + #define RTL8373_CFG_PHY_POLL_INV3_CMD3_INV_MASK (0xFFFF << RTL8373_CFG_PHY_POLL_INV3_CMD3_INV_OFFSET) + +#define RTL8373_CFG_PHY_POLL_WD0_ADDR (0xB08) + #define RTL8373_CFG_PHY_POLL_WD0_CMD0_WDAT_OFFSET (0) + #define RTL8373_CFG_PHY_POLL_WD0_CMD0_WDAT_MASK (0xFFFF << RTL8373_CFG_PHY_POLL_WD0_CMD0_WDAT_OFFSET) + +#define RTL8373_CFG_PHY_POLL_WD1_ADDR (0xB0C) + #define RTL8373_CFG_PHY_POLL_WD1_CMD1_WDAT_OFFSET (0) + #define RTL8373_CFG_PHY_POLL_WD1_CMD1_WDAT_MASK (0xFFFF << RTL8373_CFG_PHY_POLL_WD1_CMD1_WDAT_OFFSET) + +#define RTL8373_CFG_PHY_POLL_WD2_ADDR (0xB10) + #define RTL8373_CFG_PHY_POLL_WD2_CMD2_WDAT_OFFSET (0) + #define RTL8373_CFG_PHY_POLL_WD2_CMD2_WDAT_MASK (0xFFFF << RTL8373_CFG_PHY_POLL_WD2_CMD2_WDAT_OFFSET) + +#define RTL8373_CFG_PHY_POLL_WD3_ADDR (0xB14) + #define RTL8373_CFG_PHY_POLL_WD3_CMD3_WDAT_OFFSET (0) + #define RTL8373_CFG_PHY_POLL_WD3_CMD3_WDAT_MASK (0xFFFF << RTL8373_CFG_PHY_POLL_WD3_CMD3_WDAT_OFFSET) + +#define RTL8373_PHY_SDET_STATUS_ADDR (0xB18) + #define RTL8373_PHY_SDET_STATUS_P3_SDET_STS_OFFSET (3) + #define RTL8373_PHY_SDET_STATUS_P3_SDET_STS_MASK (0x1 << RTL8373_PHY_SDET_STATUS_P3_SDET_STS_OFFSET) + #define RTL8373_PHY_SDET_STATUS_P2_SDET_STS_OFFSET (2) + #define RTL8373_PHY_SDET_STATUS_P2_SDET_STS_MASK (0x1 << RTL8373_PHY_SDET_STATUS_P2_SDET_STS_OFFSET) + #define RTL8373_PHY_SDET_STATUS_P1_SDET_STS_OFFSET (1) + #define RTL8373_PHY_SDET_STATUS_P1_SDET_STS_MASK (0x1 << RTL8373_PHY_SDET_STATUS_P1_SDET_STS_OFFSET) + #define RTL8373_PHY_SDET_STATUS_P0_SDET_STS_OFFSET (0) + #define RTL8373_PHY_SDET_STATUS_P0_SDET_STS_MASK (0x1 << RTL8373_PHY_SDET_STATUS_P0_SDET_STS_OFFSET) + +#define RTL8373_P0_PHY_POLL_CMD0_RDAT_ADDR (0xB1C) + #define RTL8373_P0_PHY_POLL_CMD0_RDAT_P0_CMD0_RDAT_OFFSET (0) + #define RTL8373_P0_PHY_POLL_CMD0_RDAT_P0_CMD0_RDAT_MASK (0xFFFF << RTL8373_P0_PHY_POLL_CMD0_RDAT_P0_CMD0_RDAT_OFFSET) + +#define RTL8373_P0_PHY_POLL_CMD1_RDAT_ADDR (0xB20) + #define RTL8373_P0_PHY_POLL_CMD1_RDAT_P0_CMD1_RDAT_OFFSET (0) + #define RTL8373_P0_PHY_POLL_CMD1_RDAT_P0_CMD1_RDAT_MASK (0xFFFF << RTL8373_P0_PHY_POLL_CMD1_RDAT_P0_CMD1_RDAT_OFFSET) + +#define RTL8373_P0_PHY_POLL_CMD2_RDAT_ADDR (0xB24) + #define RTL8373_P0_PHY_POLL_CMD2_RDAT_P0_CMD2_RDAT_OFFSET (0) + #define RTL8373_P0_PHY_POLL_CMD2_RDAT_P0_CMD2_RDAT_MASK (0xFFFF << RTL8373_P0_PHY_POLL_CMD2_RDAT_P0_CMD2_RDAT_OFFSET) + +#define RTL8373_P0_PHY_POLL_CMD3_RDAT_ADDR (0xB28) + #define RTL8373_P0_PHY_POLL_CMD3_RDAT_P0_CMD3_RDAT_OFFSET (0) + #define RTL8373_P0_PHY_POLL_CMD3_RDAT_P0_CMD3_RDAT_MASK (0xFFFF << RTL8373_P0_PHY_POLL_CMD3_RDAT_P0_CMD3_RDAT_OFFSET) + +#define RTL8373_P1_PHY_POLL_CMD0_RDAT_ADDR (0xB2C) + #define RTL8373_P1_PHY_POLL_CMD0_RDAT_P1_CMD0_RDAT_OFFSET (0) + #define RTL8373_P1_PHY_POLL_CMD0_RDAT_P1_CMD0_RDAT_MASK (0xFFFF << RTL8373_P1_PHY_POLL_CMD0_RDAT_P1_CMD0_RDAT_OFFSET) + +#define RTL8373_P1_PHY_POLL_CMD1_RDAT_ADDR (0xB30) + #define RTL8373_P1_PHY_POLL_CMD1_RDAT_P1_CMD1_RDAT_OFFSET (0) + #define RTL8373_P1_PHY_POLL_CMD1_RDAT_P1_CMD1_RDAT_MASK (0xFFFF << RTL8373_P1_PHY_POLL_CMD1_RDAT_P1_CMD1_RDAT_OFFSET) + +#define RTL8373_P1_PHY_POLL_CMD2_RDAT_ADDR (0xB34) + #define RTL8373_P1_PHY_POLL_CMD2_RDAT_P1_CMD2_RDAT_OFFSET (0) + #define RTL8373_P1_PHY_POLL_CMD2_RDAT_P1_CMD2_RDAT_MASK (0xFFFF << RTL8373_P1_PHY_POLL_CMD2_RDAT_P1_CMD2_RDAT_OFFSET) + +#define RTL8373_P1_PHY_POLL_CMD3_RDAT_ADDR (0xB38) + #define RTL8373_P1_PHY_POLL_CMD3_RDAT_P1_CMD3_RDAT_OFFSET (0) + #define RTL8373_P1_PHY_POLL_CMD3_RDAT_P1_CMD3_RDAT_MASK (0xFFFF << RTL8373_P1_PHY_POLL_CMD3_RDAT_P1_CMD3_RDAT_OFFSET) + +#define RTL8373_P2_PHY_POLL_CMD0_RDAT_ADDR (0xB3C) + #define RTL8373_P2_PHY_POLL_CMD0_RDAT_P2_CMD0_RDAT_OFFSET (0) + #define RTL8373_P2_PHY_POLL_CMD0_RDAT_P2_CMD0_RDAT_MASK (0xFFFF << RTL8373_P2_PHY_POLL_CMD0_RDAT_P2_CMD0_RDAT_OFFSET) + +#define RTL8373_P2_PHY_POLL_CMD1_RDAT_ADDR (0xB40) + #define RTL8373_P2_PHY_POLL_CMD1_RDAT_P2_CMD1_RDAT_OFFSET (0) + #define RTL8373_P2_PHY_POLL_CMD1_RDAT_P2_CMD1_RDAT_MASK (0xFFFF << RTL8373_P2_PHY_POLL_CMD1_RDAT_P2_CMD1_RDAT_OFFSET) + +#define RTL8373_P2_PHY_POLL_CMD2_RDAT_ADDR (0xB44) + #define RTL8373_P2_PHY_POLL_CMD2_RDAT_P2_CMD2_RDAT_OFFSET (0) + #define RTL8373_P2_PHY_POLL_CMD2_RDAT_P2_CMD2_RDAT_MASK (0xFFFF << RTL8373_P2_PHY_POLL_CMD2_RDAT_P2_CMD2_RDAT_OFFSET) + +#define RTL8373_P2_PHY_POLL_CMD3_RDAT_ADDR (0xB48) + #define RTL8373_P2_PHY_POLL_CMD3_RDAT_P2_CMD3_RDAT_OFFSET (0) + #define RTL8373_P2_PHY_POLL_CMD3_RDAT_P2_CMD3_RDAT_MASK (0xFFFF << RTL8373_P2_PHY_POLL_CMD3_RDAT_P2_CMD3_RDAT_OFFSET) + +#define RTL8373_P3_PHY_POLL_CMD0_RDAT_ADDR (0xB4C) + #define RTL8373_P3_PHY_POLL_CMD0_RDAT_P3_CMD0_RDAT_OFFSET (0) + #define RTL8373_P3_PHY_POLL_CMD0_RDAT_P3_CMD0_RDAT_MASK (0xFFFF << RTL8373_P3_PHY_POLL_CMD0_RDAT_P3_CMD0_RDAT_OFFSET) + +#define RTL8373_P3_PHY_POLL_CMD1_RDAT_ADDR (0xB50) + #define RTL8373_P3_PHY_POLL_CMD1_RDAT_P3_CMD1_RDAT_OFFSET (0) + #define RTL8373_P3_PHY_POLL_CMD1_RDAT_P3_CMD1_RDAT_MASK (0xFFFF << RTL8373_P3_PHY_POLL_CMD1_RDAT_P3_CMD1_RDAT_OFFSET) + +#define RTL8373_P3_PHY_POLL_CMD2_RDAT_ADDR (0xB54) + #define RTL8373_P3_PHY_POLL_CMD2_RDAT_P3_CMD2_RDAT_OFFSET (0) + #define RTL8373_P3_PHY_POLL_CMD2_RDAT_P3_CMD2_RDAT_MASK (0xFFFF << RTL8373_P3_PHY_POLL_CMD2_RDAT_P3_CMD2_RDAT_OFFSET) + +#define RTL8373_P3_PHY_POLL_CMD3_RDAT_ADDR (0xB58) + #define RTL8373_P3_PHY_POLL_CMD3_RDAT_P3_CMD3_RDAT_OFFSET (0) + #define RTL8373_P3_PHY_POLL_CMD3_RDAT_P3_CMD3_RDAT_MASK (0xFFFF << RTL8373_P3_PHY_POLL_CMD3_RDAT_P3_CMD3_RDAT_OFFSET) + +#define RTL8373_PHY_ABLTY_RESOLUTION_FRC_MODE_ADDR (0xB5C) + #define RTL8373_PHY_ABLTY_RESOLUTION_FRC_MODE_PHY_ABLTY_RESOLUTION_FRC_MODE_OFFSET (0) + #define RTL8373_PHY_ABLTY_RESOLUTION_FRC_MODE_PHY_ABLTY_RESOLUTION_FRC_MODE_MASK (0xF << RTL8373_PHY_ABLTY_RESOLUTION_FRC_MODE_PHY_ABLTY_RESOLUTION_FRC_MODE_OFFSET) + +#define RTL8373_P0_PHY_ABLTY_RESOLUTION_FORCE_ADDR (0xB60) + #define RTL8373_P0_PHY_ABLTY_RESOLUTION_FORCE_P0_PHY_ABLTY_RESOLUTION_FRC_VALUE_OFFSET (0) + #define RTL8373_P0_PHY_ABLTY_RESOLUTION_FORCE_P0_PHY_ABLTY_RESOLUTION_FRC_VALUE_MASK (0xFFFF << RTL8373_P0_PHY_ABLTY_RESOLUTION_FORCE_P0_PHY_ABLTY_RESOLUTION_FRC_VALUE_OFFSET) + +#define RTL8373_P1_PHY_ABLTY_RESOLUTION_FORCE_ADDR (0xB64) + #define RTL8373_P1_PHY_ABLTY_RESOLUTION_FORCE_P1_PHY_ABLTY_RESOLUTION_FRC_VALUE_OFFSET (0) + #define RTL8373_P1_PHY_ABLTY_RESOLUTION_FORCE_P1_PHY_ABLTY_RESOLUTION_FRC_VALUE_MASK (0xFFFF << RTL8373_P1_PHY_ABLTY_RESOLUTION_FORCE_P1_PHY_ABLTY_RESOLUTION_FRC_VALUE_OFFSET) + +#define RTL8373_P2_PHY_ABLTY_RESOLUTION_FORCE_ADDR (0xB68) + #define RTL8373_P2_PHY_ABLTY_RESOLUTION_FORCE_P2_PHY_ABLTY_RESOLUTION_FRC_VALUE_OFFSET (0) + #define RTL8373_P2_PHY_ABLTY_RESOLUTION_FORCE_P2_PHY_ABLTY_RESOLUTION_FRC_VALUE_MASK (0xFFFF << RTL8373_P2_PHY_ABLTY_RESOLUTION_FORCE_P2_PHY_ABLTY_RESOLUTION_FRC_VALUE_OFFSET) + +#define RTL8373_P3_PHY_ABLTY_RESOLUTION_FORCE_ADDR (0xB6C) + #define RTL8373_P3_PHY_ABLTY_RESOLUTION_FORCE_P3_PHY_ABLTY_RESOLUTION_FRC_VALUE_OFFSET (0) + #define RTL8373_P3_PHY_ABLTY_RESOLUTION_FORCE_P3_PHY_ABLTY_RESOLUTION_FRC_VALUE_MASK (0xFFFF << RTL8373_P3_PHY_ABLTY_RESOLUTION_FORCE_P3_PHY_ABLTY_RESOLUTION_FRC_VALUE_OFFSET) + +#define RTL8373_POWCTRL_ADR_ADDR (0xB70) + #define RTL8373_POWCTRL_ADR_GETPOWCTRL_ADR_OFFSET (0) + #define RTL8373_POWCTRL_ADR_GETPOWCTRL_ADR_MASK (0xFFFF << RTL8373_POWCTRL_ADR_GETPOWCTRL_ADR_OFFSET) + +#define RTL8373_POWCTRL1_BIT_ADDR (0xB74) + #define RTL8373_POWCTRL1_BIT_GETPOWCTRL1_BIT_OFFSET (0) + #define RTL8373_POWCTRL1_BIT_GETPOWCTRL1_BIT_MASK (0xFFFF << RTL8373_POWCTRL1_BIT_GETPOWCTRL1_BIT_OFFSET) + +#define RTL8373_POWCTRL0_BIT_ADDR (0xB78) + #define RTL8373_POWCTRL0_BIT_GETPOWCTRL0_BIT_OFFSET (0) + #define RTL8373_POWCTRL0_BIT_GETPOWCTRL0_BIT_MASK (0xFFFF << RTL8373_POWCTRL0_BIT_GETPOWCTRL0_BIT_OFFSET) + +#define RTL8373_RS_LAYER_CONFIG_ADDR (0xB7C) + #define RTL8373_RS_LAYER_CONFIG_RS_BYPASS_OFFSET (7) + #define RTL8373_RS_LAYER_CONFIG_RS_BYPASS_MASK (0x1 << RTL8373_RS_LAYER_CONFIG_RS_BYPASS_OFFSET) + #define RTL8373_RS_LAYER_CONFIG_RS_FB_ON_OFFSET (6) + #define RTL8373_RS_LAYER_CONFIG_RS_FB_ON_MASK (0x1 << RTL8373_RS_LAYER_CONFIG_RS_FB_ON_OFFSET) + #define RTL8373_RS_LAYER_CONFIG_RS_LINK_FAULT_INDI_OFF_OFFSET (5) + #define RTL8373_RS_LAYER_CONFIG_RS_LINK_FAULT_INDI_OFF_MASK (0x1 << RTL8373_RS_LAYER_CONFIG_RS_LINK_FAULT_INDI_OFF_OFFSET) + #define RTL8373_RS_LAYER_CONFIG_RS_SEQ_CONV_OFFSET (4) + #define RTL8373_RS_LAYER_CONFIG_RS_SEQ_CONV_MASK (0x1 << RTL8373_RS_LAYER_CONFIG_RS_SEQ_CONV_OFFSET) + #define RTL8373_RS_LAYER_CONFIG_RS_PASS_FAULT2MAC_OFFSET (3) + #define RTL8373_RS_LAYER_CONFIG_RS_PASS_FAULT2MAC_MASK (0x1 << RTL8373_RS_LAYER_CONFIG_RS_PASS_FAULT2MAC_OFFSET) + #define RTL8373_RS_LAYER_CONFIG_RS_LINK_FAULT_LOCAL_OFF_OFFSET (2) + #define RTL8373_RS_LAYER_CONFIG_RS_LINK_FAULT_LOCAL_OFF_MASK (0x1 << RTL8373_RS_LAYER_CONFIG_RS_LINK_FAULT_LOCAL_OFF_OFFSET) + #define RTL8373_RS_LAYER_CONFIG_RS_LINK_FAULT_REMOTE_OFF_OFFSET (1) + #define RTL8373_RS_LAYER_CONFIG_RS_LINK_FAULT_REMOTE_OFF_MASK (0x1 << RTL8373_RS_LAYER_CONFIG_RS_LINK_FAULT_REMOTE_OFF_OFFSET) + #define RTL8373_RS_LAYER_CONFIG_RS_LINK_FAULT_LINT_OFF_OFFSET (0) + #define RTL8373_RS_LAYER_CONFIG_RS_LINK_FAULT_LINT_OFF_MASK (0x1 << RTL8373_RS_LAYER_CONFIG_RS_LINK_FAULT_LINT_OFF_OFFSET) + +#define RTL8373_PHY0_RD_PCS_ABILITY_ADDR (0xB80) + #define RTL8373_PHY0_RD_PCS_ABILITY_P0_RD_PCS_ABILITY_OFFSET (0) + #define RTL8373_PHY0_RD_PCS_ABILITY_P0_RD_PCS_ABILITY_MASK (0xFFFF << RTL8373_PHY0_RD_PCS_ABILITY_P0_RD_PCS_ABILITY_OFFSET) + +#define RTL8373_PHY1_RD_PCS_ABILITY_ADDR (0xB84) + #define RTL8373_PHY1_RD_PCS_ABILITY_P1_RD_PCS_ABILITY_OFFSET (0) + #define RTL8373_PHY1_RD_PCS_ABILITY_P1_RD_PCS_ABILITY_MASK (0xFFFF << RTL8373_PHY1_RD_PCS_ABILITY_P1_RD_PCS_ABILITY_OFFSET) + +#define RTL8373_PHY2_RD_PCS_ABILITY_ADDR (0xB88) + #define RTL8373_PHY2_RD_PCS_ABILITY_P2_RD_PCS_ABILITY_OFFSET (0) + #define RTL8373_PHY2_RD_PCS_ABILITY_P2_RD_PCS_ABILITY_MASK (0xFFFF << RTL8373_PHY2_RD_PCS_ABILITY_P2_RD_PCS_ABILITY_OFFSET) + +#define RTL8373_PHY3_RD_PCS_ABILITY_ADDR (0xB8C) + #define RTL8373_PHY3_RD_PCS_ABILITY_P3_RD_PCS_ABILITY_OFFSET (0) + #define RTL8373_PHY3_RD_PCS_ABILITY_P3_RD_PCS_ABILITY_MASK (0xFFFF << RTL8373_PHY3_RD_PCS_ABILITY_P3_RD_PCS_ABILITY_OFFSET) + +#define RTL8373_CFG_PHY_XG2G_G_MISC_ADDR (0xB90) + #define RTL8373_CFG_PHY_XG2G_G_MISC_P3_IPG_DIFF_OFFSET (14) + #define RTL8373_CFG_PHY_XG2G_G_MISC_P3_IPG_DIFF_MASK (0x3 << RTL8373_CFG_PHY_XG2G_G_MISC_P3_IPG_DIFF_OFFSET) + #define RTL8373_CFG_PHY_XG2G_G_MISC_P3_BYPASS_SMOOTH_OFFSET (13) + #define RTL8373_CFG_PHY_XG2G_G_MISC_P3_BYPASS_SMOOTH_MASK (0x1 << RTL8373_CFG_PHY_XG2G_G_MISC_P3_BYPASS_SMOOTH_OFFSET) + #define RTL8373_CFG_PHY_XG2G_G_MISC_P3_RST_LATCH_MIN_IPG_OFFSET (12) + #define RTL8373_CFG_PHY_XG2G_G_MISC_P3_RST_LATCH_MIN_IPG_MASK (0x1 << RTL8373_CFG_PHY_XG2G_G_MISC_P3_RST_LATCH_MIN_IPG_OFFSET) + #define RTL8373_CFG_PHY_XG2G_G_MISC_P2_IPG_DIFF_OFFSET (10) + #define RTL8373_CFG_PHY_XG2G_G_MISC_P2_IPG_DIFF_MASK (0x3 << RTL8373_CFG_PHY_XG2G_G_MISC_P2_IPG_DIFF_OFFSET) + #define RTL8373_CFG_PHY_XG2G_G_MISC_P2_BYPASS_SMOOTH_OFFSET (9) + #define RTL8373_CFG_PHY_XG2G_G_MISC_P2_BYPASS_SMOOTH_MASK (0x1 << RTL8373_CFG_PHY_XG2G_G_MISC_P2_BYPASS_SMOOTH_OFFSET) + #define RTL8373_CFG_PHY_XG2G_G_MISC_P2_RST_LATCH_MIN_IPG_OFFSET (8) + #define RTL8373_CFG_PHY_XG2G_G_MISC_P2_RST_LATCH_MIN_IPG_MASK (0x1 << RTL8373_CFG_PHY_XG2G_G_MISC_P2_RST_LATCH_MIN_IPG_OFFSET) + #define RTL8373_CFG_PHY_XG2G_G_MISC_P1_IPG_DIFF_OFFSET (6) + #define RTL8373_CFG_PHY_XG2G_G_MISC_P1_IPG_DIFF_MASK (0x3 << RTL8373_CFG_PHY_XG2G_G_MISC_P1_IPG_DIFF_OFFSET) + #define RTL8373_CFG_PHY_XG2G_G_MISC_P1_BYPASS_SMOOTH_OFFSET (5) + #define RTL8373_CFG_PHY_XG2G_G_MISC_P1_BYPASS_SMOOTH_MASK (0x1 << RTL8373_CFG_PHY_XG2G_G_MISC_P1_BYPASS_SMOOTH_OFFSET) + #define RTL8373_CFG_PHY_XG2G_G_MISC_P1_RST_LATCH_MIN_IPG_OFFSET (4) + #define RTL8373_CFG_PHY_XG2G_G_MISC_P1_RST_LATCH_MIN_IPG_MASK (0x1 << RTL8373_CFG_PHY_XG2G_G_MISC_P1_RST_LATCH_MIN_IPG_OFFSET) + #define RTL8373_CFG_PHY_XG2G_G_MISC_P0_IPG_DIFF_OFFSET (2) + #define RTL8373_CFG_PHY_XG2G_G_MISC_P0_IPG_DIFF_MASK (0x3 << RTL8373_CFG_PHY_XG2G_G_MISC_P0_IPG_DIFF_OFFSET) + #define RTL8373_CFG_PHY_XG2G_G_MISC_P0_BYPASS_SMOOTH_OFFSET (1) + #define RTL8373_CFG_PHY_XG2G_G_MISC_P0_BYPASS_SMOOTH_MASK (0x1 << RTL8373_CFG_PHY_XG2G_G_MISC_P0_BYPASS_SMOOTH_OFFSET) + #define RTL8373_CFG_PHY_XG2G_G_MISC_P0_RST_LATCH_MIN_IPG_OFFSET (0) + #define RTL8373_CFG_PHY_XG2G_G_MISC_P0_RST_LATCH_MIN_IPG_MASK (0x1 << RTL8373_CFG_PHY_XG2G_G_MISC_P0_RST_LATCH_MIN_IPG_OFFSET) + +#define RTL8373_P1_XG2XG_IPG_DBG_INFO_ADDR (0x920) + #define RTL8373_P1_XG2XG_IPG_DBG_INFO_CFG_P1_DBG_INFO_OFF_OFFSET (15) + #define RTL8373_P1_XG2XG_IPG_DBG_INFO_CFG_P1_DBG_INFO_OFF_MASK (0x1 << RTL8373_P1_XG2XG_IPG_DBG_INFO_CFG_P1_DBG_INFO_OFF_OFFSET) + #define RTL8373_P1_XG2XG_IPG_DBG_INFO_CFG_P1_CUR_IPG_OFFSET (10) + #define RTL8373_P1_XG2XG_IPG_DBG_INFO_CFG_P1_CUR_IPG_MASK (0x1F << RTL8373_P1_XG2XG_IPG_DBG_INFO_CFG_P1_CUR_IPG_OFFSET) + #define RTL8373_P1_XG2XG_IPG_DBG_INFO_CFG_P1_MAX_IPG_OFFSET (5) + #define RTL8373_P1_XG2XG_IPG_DBG_INFO_CFG_P1_MAX_IPG_MASK (0x1F << RTL8373_P1_XG2XG_IPG_DBG_INFO_CFG_P1_MAX_IPG_OFFSET) + #define RTL8373_P1_XG2XG_IPG_DBG_INFO_CFG_P1_MIN_IPG_OFFSET (0) + #define RTL8373_P1_XG2XG_IPG_DBG_INFO_CFG_P1_MIN_IPG_MASK (0x1F << RTL8373_P1_XG2XG_IPG_DBG_INFO_CFG_P1_MIN_IPG_OFFSET) + +#define RTL8373_P1_XG2XG_PRMB_DBG_INFO_ADDR (0x924) + #define RTL8373_P1_XG2XG_PRMB_DBG_INFO_CFG_P1_CUR_PRMB_OFFSET (8) + #define RTL8373_P1_XG2XG_PRMB_DBG_INFO_CFG_P1_CUR_PRMB_MASK (0xF << RTL8373_P1_XG2XG_PRMB_DBG_INFO_CFG_P1_CUR_PRMB_OFFSET) + #define RTL8373_P1_XG2XG_PRMB_DBG_INFO_CFG_P1_MAX_PRMB_OFFSET (4) + #define RTL8373_P1_XG2XG_PRMB_DBG_INFO_CFG_P1_MAX_PRMB_MASK (0xF << RTL8373_P1_XG2XG_PRMB_DBG_INFO_CFG_P1_MAX_PRMB_OFFSET) + #define RTL8373_P1_XG2XG_PRMB_DBG_INFO_CFG_P1_MIN_PRMB_OFFSET (0) + #define RTL8373_P1_XG2XG_PRMB_DBG_INFO_CFG_P1_MIN_PRMB_MASK (0xF << RTL8373_P1_XG2XG_PRMB_DBG_INFO_CFG_P1_MIN_PRMB_OFFSET) + +#define RTL8373_P1_XG2XG_THR_DBG_INFO_ADDR (0x928) + #define RTL8373_P1_XG2XG_THR_DBG_INFO_CFG_P1_CUR_THR_OFFSET (6) + #define RTL8373_P1_XG2XG_THR_DBG_INFO_CFG_P1_CUR_THR_MASK (0x3F << RTL8373_P1_XG2XG_THR_DBG_INFO_CFG_P1_CUR_THR_OFFSET) + #define RTL8373_P1_XG2XG_THR_DBG_INFO_CFG_P1_MAX_THR_OFFSET (0) + #define RTL8373_P1_XG2XG_THR_DBG_INFO_CFG_P1_MAX_THR_MASK (0x3F << RTL8373_P1_XG2XG_THR_DBG_INFO_CFG_P1_MAX_THR_OFFSET) + +#define RTL8373_RANDOM_UPD_PERIOD_ADDR (0xE90) + #define RTL8373_RANDOM_UPD_PERIOD_RSUPD_PERIOD_OFFSET (8) + #define RTL8373_RANDOM_UPD_PERIOD_RSUPD_PERIOD_MASK (0xFF << RTL8373_RANDOM_UPD_PERIOD_RSUPD_PERIOD_OFFSET) + #define RTL8373_RANDOM_UPD_PERIOD_RRUPD_PERIOD_OFFSET (0) + #define RTL8373_RANDOM_UPD_PERIOD_RRUPD_PERIOD_MASK (0xFF << RTL8373_RANDOM_UPD_PERIOD_RRUPD_PERIOD_OFFSET) + +#define RTL8373_RANDOM_UPD_CTRL_ADDR (0xE94) + #define RTL8373_RANDOM_UPD_CTRL_TMTENBIT_OFFSET (15) + #define RTL8373_RANDOM_UPD_CTRL_TMTENBIT_MASK (0x1 << RTL8373_RANDOM_UPD_CTRL_TMTENBIT_OFFSET) + #define RTL8373_RANDOM_UPD_CTRL_TMLSB_2_0_OFFSET (12) + #define RTL8373_RANDOM_UPD_CTRL_TMLSB_2_0_MASK (0x7 << RTL8373_RANDOM_UPD_CTRL_TMLSB_2_0_OFFSET) + #define RTL8373_RANDOM_UPD_CTRL_RR_SEL_MTHD_OFFSET (11) + #define RTL8373_RANDOM_UPD_CTRL_RR_SEL_MTHD_MASK (0x1 << RTL8373_RANDOM_UPD_CTRL_RR_SEL_MTHD_OFFSET) + #define RTL8373_RANDOM_UPD_CTRL_RRSTEP_4_0_OFFSET (6) + #define RTL8373_RANDOM_UPD_CTRL_RRSTEP_4_0_MASK (0x1F << RTL8373_RANDOM_UPD_CTRL_RRSTEP_4_0_OFFSET) + #define RTL8373_RANDOM_UPD_CTRL_RRRND_SRC_SEL_OFFSET (5) + #define RTL8373_RANDOM_UPD_CTRL_RRRND_SRC_SEL_MASK (0x1 << RTL8373_RANDOM_UPD_CTRL_RRRND_SRC_SEL_OFFSET) + #define RTL8373_RANDOM_UPD_CTRL_RRUPD_ONCE_OFFSET (4) + #define RTL8373_RANDOM_UPD_CTRL_RRUPD_ONCE_MASK (0x1 << RTL8373_RANDOM_UPD_CTRL_RRUPD_ONCE_OFFSET) + #define RTL8373_RANDOM_UPD_CTRL_RRUPD_EN_OFFSET (3) + #define RTL8373_RANDOM_UPD_CTRL_RRUPD_EN_MASK (0x1 << RTL8373_RANDOM_UPD_CTRL_RRUPD_EN_OFFSET) + #define RTL8373_RANDOM_UPD_CTRL_RSRND_SRC_SEL_OFFSET (2) + #define RTL8373_RANDOM_UPD_CTRL_RSRND_SRC_SEL_MASK (0x1 << RTL8373_RANDOM_UPD_CTRL_RSRND_SRC_SEL_OFFSET) + #define RTL8373_RANDOM_UPD_CTRL_RSUPD_ONCE_OFFSET (1) + #define RTL8373_RANDOM_UPD_CTRL_RSUPD_ONCE_MASK (0x1 << RTL8373_RANDOM_UPD_CTRL_RSUPD_ONCE_OFFSET) + #define RTL8373_RANDOM_UPD_CTRL_RSUPD_EN_OFFSET (0) + #define RTL8373_RANDOM_UPD_CTRL_RSUPD_EN_MASK (0x1 << RTL8373_RANDOM_UPD_CTRL_RSUPD_EN_OFFSET) + +#define RTL8373_RG_RDM_SEED_SRC_ADDR_ADDR (0xE98) + #define RTL8373_RG_RDM_SEED_SRC_ADDR_RDM_SEED_REGADDR_OFFSET (0) + #define RTL8373_RG_RDM_SEED_SRC_ADDR_RDM_SEED_REGADDR_MASK (0xFFFF << RTL8373_RG_RDM_SEED_SRC_ADDR_RDM_SEED_REGADDR_OFFSET) + +#define RTL8373_RING_RATE_REGADDR_ADDR (0xE9C) + #define RTL8373_RING_RATE_REGADDR_RING_RATE_REGADDR_OFFSET (0) + #define RTL8373_RING_RATE_REGADDR_RING_RATE_REGADDR_MASK (0xFFFF << RTL8373_RING_RATE_REGADDR_RING_RATE_REGADDR_OFFSET) + +#define RTL8373_RING_RATE_SEL_MASK_L_ADDR (0xEA0) + #define RTL8373_RING_RATE_SEL_MASK_L_RATE_MASK_15_0_OFFSET (0) + #define RTL8373_RING_RATE_SEL_MASK_L_RATE_MASK_15_0_MASK (0xFFFF << RTL8373_RING_RATE_SEL_MASK_L_RATE_MASK_15_0_OFFSET) + +#define RTL8373_RING_RATE_SEL_MASK_H_ADDR (0xEA4) + #define RTL8373_RING_RATE_SEL_MASK_H_RATE_MASK_31_16_OFFSET (0) + #define RTL8373_RING_RATE_SEL_MASK_H_RATE_MASK_31_16_MASK (0xFFFF << RTL8373_RING_RATE_SEL_MASK_H_RATE_MASK_31_16_OFFSET) + +#define RTL8373_RING_RATE_FRC_VALUE_H_ADDR (0xEA8) + #define RTL8373_RING_RATE_FRC_VALUE_H_RR_FRC_MODE_OFFSET (31) + #define RTL8373_RING_RATE_FRC_VALUE_H_RR_FRC_MODE_MASK (0x1 << RTL8373_RING_RATE_FRC_VALUE_H_RR_FRC_MODE_OFFSET) + #define RTL8373_RING_RATE_FRC_VALUE_H_RR_FRC_VAL_19_10_OFFSET (0) + #define RTL8373_RING_RATE_FRC_VALUE_H_RR_FRC_VAL_19_10_MASK (0x3FF << RTL8373_RING_RATE_FRC_VALUE_H_RR_FRC_VAL_19_10_OFFSET) + +#define RTL8373_RING_RATE_FRC_VALUE_L_ADDR (0xEAC) + #define RTL8373_RING_RATE_FRC_VALUE_L_RR_FRC_VAL_9_0_OFFSET (0) + #define RTL8373_RING_RATE_FRC_VALUE_L_RR_FRC_VAL_9_0_MASK (0x3FF << RTL8373_RING_RATE_FRC_VALUE_L_RR_FRC_VAL_9_0_OFFSET) + +#define RTL8373_LFSR_INIT_SEED_FRC_VALUE_ADDR (0xEB0) + #define RTL8373_LFSR_INIT_SEED_FRC_VALUE_RS_FRC_MODE_OFFSET (31) + #define RTL8373_LFSR_INIT_SEED_FRC_VALUE_RS_FRC_MODE_MASK (0x1 << RTL8373_LFSR_INIT_SEED_FRC_VALUE_RS_FRC_MODE_OFFSET) + #define RTL8373_LFSR_INIT_SEED_FRC_VALUE_RS_FRC_VAL_9_0_OFFSET (0) + #define RTL8373_LFSR_INIT_SEED_FRC_VALUE_RS_FRC_VAL_9_0_MASK (0x3FF << RTL8373_LFSR_INIT_SEED_FRC_VALUE_RS_FRC_VAL_9_0_OFFSET) + +#define RTL8373_RING_RATE_RD_VALUE_H_ADDR (0xEB4) + #define RTL8373_RING_RATE_RD_VALUE_H_RR_RD_VAL_19_10_OFFSET (0) + #define RTL8373_RING_RATE_RD_VALUE_H_RR_RD_VAL_19_10_MASK (0x3FF << RTL8373_RING_RATE_RD_VALUE_H_RR_RD_VAL_19_10_OFFSET) + +#define RTL8373_RING_RATE_RD_VALUE_L_ADDR (0xEB8) + #define RTL8373_RING_RATE_RD_VALUE_L_RR_RD_VAL_9_0_OFFSET (0) + #define RTL8373_RING_RATE_RD_VALUE_L_RR_RD_VAL_9_0_MASK (0x3FF << RTL8373_RING_RATE_RD_VALUE_L_RR_RD_VAL_9_0_OFFSET) + +#define RTL8373_LFSR_INIT_SEED_RD_VALUE_ADDR (0xEBC) + #define RTL8373_LFSR_INIT_SEED_RD_VALUE_RS_RD_VAL_9_0_OFFSET (0) + #define RTL8373_LFSR_INIT_SEED_RD_VALUE_RS_RD_VAL_9_0_MASK (0x3FF << RTL8373_LFSR_INIT_SEED_RD_VALUE_RS_RD_VAL_9_0_OFFSET) + +#define RTL8373_P0_G2XG_CFG_CLR_ERR_FLAG_ADDR (0xB94) + #define RTL8373_P0_G2XG_CFG_CLR_ERR_FLAG_P0_G2XG_CFG_CLR_ERR_FLAG_OFFSET (0) + #define RTL8373_P0_G2XG_CFG_CLR_ERR_FLAG_P0_G2XG_CFG_CLR_ERR_FLAG_MASK (0xFFFF << RTL8373_P0_G2XG_CFG_CLR_ERR_FLAG_P0_G2XG_CFG_CLR_ERR_FLAG_OFFSET) + +#define RTL8373_P1_G2XG_CFG_CLR_ERR_FLAG_ADDR (0xB98) + #define RTL8373_P1_G2XG_CFG_CLR_ERR_FLAG_P1_G2XG_CFG_CLR_ERR_FLAG_OFFSET (0) + #define RTL8373_P1_G2XG_CFG_CLR_ERR_FLAG_P1_G2XG_CFG_CLR_ERR_FLAG_MASK (0xFFFF << RTL8373_P1_G2XG_CFG_CLR_ERR_FLAG_P1_G2XG_CFG_CLR_ERR_FLAG_OFFSET) + +#define RTL8373_P2_G2XG_CFG_CLR_ERR_FLAG_ADDR (0xB9C) + #define RTL8373_P2_G2XG_CFG_CLR_ERR_FLAG_P2_G2XG_CFG_CLR_ERR_FLAG_OFFSET (0) + #define RTL8373_P2_G2XG_CFG_CLR_ERR_FLAG_P2_G2XG_CFG_CLR_ERR_FLAG_MASK (0xFFFF << RTL8373_P2_G2XG_CFG_CLR_ERR_FLAG_P2_G2XG_CFG_CLR_ERR_FLAG_OFFSET) + +#define RTL8373_P3_G2XG_CFG_CLR_ERR_FLAG_ADDR (0xBA0) + #define RTL8373_P3_G2XG_CFG_CLR_ERR_FLAG_P3_G2XG_CFG_CLR_ERR_FLAG_OFFSET (0) + #define RTL8373_P3_G2XG_CFG_CLR_ERR_FLAG_P3_G2XG_CFG_CLR_ERR_FLAG_MASK (0xFFFF << RTL8373_P3_G2XG_CFG_CLR_ERR_FLAG_P3_G2XG_CFG_CLR_ERR_FLAG_OFFSET) + +#define RTL8373_G2XG_FIFO_CLR_CFG_ADDR (0xBA4) + #define RTL8373_G2XG_FIFO_CLR_CFG_P3_LDN_CLR_G2XG_FIFO_RX_OFFSET (15) + #define RTL8373_G2XG_FIFO_CLR_CFG_P3_LDN_CLR_G2XG_FIFO_RX_MASK (0x1 << RTL8373_G2XG_FIFO_CLR_CFG_P3_LDN_CLR_G2XG_FIFO_RX_OFFSET) + #define RTL8373_G2XG_FIFO_CLR_CFG_P2_LDN_CLR_G2XG_FIFO_RX_OFFSET (14) + #define RTL8373_G2XG_FIFO_CLR_CFG_P2_LDN_CLR_G2XG_FIFO_RX_MASK (0x1 << RTL8373_G2XG_FIFO_CLR_CFG_P2_LDN_CLR_G2XG_FIFO_RX_OFFSET) + #define RTL8373_G2XG_FIFO_CLR_CFG_P1_LDN_CLR_G2XG_FIFO_RX_OFFSET (13) + #define RTL8373_G2XG_FIFO_CLR_CFG_P1_LDN_CLR_G2XG_FIFO_RX_MASK (0x1 << RTL8373_G2XG_FIFO_CLR_CFG_P1_LDN_CLR_G2XG_FIFO_RX_OFFSET) + #define RTL8373_G2XG_FIFO_CLR_CFG_P0_LDN_CLR_G2XG_FIFO_RX_OFFSET (12) + #define RTL8373_G2XG_FIFO_CLR_CFG_P0_LDN_CLR_G2XG_FIFO_RX_MASK (0x1 << RTL8373_G2XG_FIFO_CLR_CFG_P0_LDN_CLR_G2XG_FIFO_RX_OFFSET) + #define RTL8373_G2XG_FIFO_CLR_CFG_P3_CLR_G2XG_FIFO_RX_OFFSET (11) + #define RTL8373_G2XG_FIFO_CLR_CFG_P3_CLR_G2XG_FIFO_RX_MASK (0x1 << RTL8373_G2XG_FIFO_CLR_CFG_P3_CLR_G2XG_FIFO_RX_OFFSET) + #define RTL8373_G2XG_FIFO_CLR_CFG_P2_CLR_G2XG_FIFO_RX_OFFSET (10) + #define RTL8373_G2XG_FIFO_CLR_CFG_P2_CLR_G2XG_FIFO_RX_MASK (0x1 << RTL8373_G2XG_FIFO_CLR_CFG_P2_CLR_G2XG_FIFO_RX_OFFSET) + #define RTL8373_G2XG_FIFO_CLR_CFG_P1_CLR_G2XG_FIFO_RX_OFFSET (9) + #define RTL8373_G2XG_FIFO_CLR_CFG_P1_CLR_G2XG_FIFO_RX_MASK (0x1 << RTL8373_G2XG_FIFO_CLR_CFG_P1_CLR_G2XG_FIFO_RX_OFFSET) + #define RTL8373_G2XG_FIFO_CLR_CFG_P0_CLR_G2XG_FIFO_RX_OFFSET (8) + #define RTL8373_G2XG_FIFO_CLR_CFG_P0_CLR_G2XG_FIFO_RX_MASK (0x1 << RTL8373_G2XG_FIFO_CLR_CFG_P0_CLR_G2XG_FIFO_RX_OFFSET) + #define RTL8373_G2XG_FIFO_CLR_CFG_P3_LDN_CLR_G2XG_FIFO_TX_OFFSET (7) + #define RTL8373_G2XG_FIFO_CLR_CFG_P3_LDN_CLR_G2XG_FIFO_TX_MASK (0x1 << RTL8373_G2XG_FIFO_CLR_CFG_P3_LDN_CLR_G2XG_FIFO_TX_OFFSET) + #define RTL8373_G2XG_FIFO_CLR_CFG_P2_LDN_CLR_G2XG_FIFO_TX_OFFSET (6) + #define RTL8373_G2XG_FIFO_CLR_CFG_P2_LDN_CLR_G2XG_FIFO_TX_MASK (0x1 << RTL8373_G2XG_FIFO_CLR_CFG_P2_LDN_CLR_G2XG_FIFO_TX_OFFSET) + #define RTL8373_G2XG_FIFO_CLR_CFG_P1_LDN_CLR_G2XG_FIFO_TX_OFFSET (5) + #define RTL8373_G2XG_FIFO_CLR_CFG_P1_LDN_CLR_G2XG_FIFO_TX_MASK (0x1 << RTL8373_G2XG_FIFO_CLR_CFG_P1_LDN_CLR_G2XG_FIFO_TX_OFFSET) + #define RTL8373_G2XG_FIFO_CLR_CFG_P0_LDN_CLR_G2XG_FIFO_TX_OFFSET (4) + #define RTL8373_G2XG_FIFO_CLR_CFG_P0_LDN_CLR_G2XG_FIFO_TX_MASK (0x1 << RTL8373_G2XG_FIFO_CLR_CFG_P0_LDN_CLR_G2XG_FIFO_TX_OFFSET) + #define RTL8373_G2XG_FIFO_CLR_CFG_P3_CLR_G2XG_FIFO_TX_OFFSET (3) + #define RTL8373_G2XG_FIFO_CLR_CFG_P3_CLR_G2XG_FIFO_TX_MASK (0x1 << RTL8373_G2XG_FIFO_CLR_CFG_P3_CLR_G2XG_FIFO_TX_OFFSET) + #define RTL8373_G2XG_FIFO_CLR_CFG_P2_CLR_G2XG_FIFO_TX_OFFSET (2) + #define RTL8373_G2XG_FIFO_CLR_CFG_P2_CLR_G2XG_FIFO_TX_MASK (0x1 << RTL8373_G2XG_FIFO_CLR_CFG_P2_CLR_G2XG_FIFO_TX_OFFSET) + #define RTL8373_G2XG_FIFO_CLR_CFG_P1_CLR_G2XG_FIFO_TX_OFFSET (1) + #define RTL8373_G2XG_FIFO_CLR_CFG_P1_CLR_G2XG_FIFO_TX_MASK (0x1 << RTL8373_G2XG_FIFO_CLR_CFG_P1_CLR_G2XG_FIFO_TX_OFFSET) + #define RTL8373_G2XG_FIFO_CLR_CFG_P0_CLR_G2XG_FIFO_TX_OFFSET (0) + #define RTL8373_G2XG_FIFO_CLR_CFG_P0_CLR_G2XG_FIFO_TX_MASK (0x1 << RTL8373_G2XG_FIFO_CLR_CFG_P0_CLR_G2XG_FIFO_TX_OFFSET) + +#define RTL8373_P2_XG2XG_IPG_DBG_INFO_ADDR (0x92C) + #define RTL8373_P2_XG2XG_IPG_DBG_INFO_CFG_P2_DBG_INFO_OFF_OFFSET (15) + #define RTL8373_P2_XG2XG_IPG_DBG_INFO_CFG_P2_DBG_INFO_OFF_MASK (0x1 << RTL8373_P2_XG2XG_IPG_DBG_INFO_CFG_P2_DBG_INFO_OFF_OFFSET) + #define RTL8373_P2_XG2XG_IPG_DBG_INFO_CFG_P2_CUR_IPG_OFFSET (10) + #define RTL8373_P2_XG2XG_IPG_DBG_INFO_CFG_P2_CUR_IPG_MASK (0x1F << RTL8373_P2_XG2XG_IPG_DBG_INFO_CFG_P2_CUR_IPG_OFFSET) + #define RTL8373_P2_XG2XG_IPG_DBG_INFO_CFG_P2_MAX_IPG_OFFSET (5) + #define RTL8373_P2_XG2XG_IPG_DBG_INFO_CFG_P2_MAX_IPG_MASK (0x1F << RTL8373_P2_XG2XG_IPG_DBG_INFO_CFG_P2_MAX_IPG_OFFSET) + #define RTL8373_P2_XG2XG_IPG_DBG_INFO_CFG_P2_MIN_IPG_OFFSET (0) + #define RTL8373_P2_XG2XG_IPG_DBG_INFO_CFG_P2_MIN_IPG_MASK (0x1F << RTL8373_P2_XG2XG_IPG_DBG_INFO_CFG_P2_MIN_IPG_OFFSET) + +#define RTL8373_P2_XG2XG_PRMB_DBG_INFO_ADDR (0x930) + #define RTL8373_P2_XG2XG_PRMB_DBG_INFO_CFG_P2_CUR_PRMB_OFFSET (8) + #define RTL8373_P2_XG2XG_PRMB_DBG_INFO_CFG_P2_CUR_PRMB_MASK (0xF << RTL8373_P2_XG2XG_PRMB_DBG_INFO_CFG_P2_CUR_PRMB_OFFSET) + #define RTL8373_P2_XG2XG_PRMB_DBG_INFO_CFG_P2_MAX_PRMB_OFFSET (4) + #define RTL8373_P2_XG2XG_PRMB_DBG_INFO_CFG_P2_MAX_PRMB_MASK (0xF << RTL8373_P2_XG2XG_PRMB_DBG_INFO_CFG_P2_MAX_PRMB_OFFSET) + #define RTL8373_P2_XG2XG_PRMB_DBG_INFO_CFG_P2_MIN_PRMB_OFFSET (0) + #define RTL8373_P2_XG2XG_PRMB_DBG_INFO_CFG_P2_MIN_PRMB_MASK (0xF << RTL8373_P2_XG2XG_PRMB_DBG_INFO_CFG_P2_MIN_PRMB_OFFSET) + +#define RTL8373_P2_XG2XG_THR_DBG_INFO_ADDR (0x934) + #define RTL8373_P2_XG2XG_THR_DBG_INFO_CFG_P2_CUR_THR_OFFSET (6) + #define RTL8373_P2_XG2XG_THR_DBG_INFO_CFG_P2_CUR_THR_MASK (0x3F << RTL8373_P2_XG2XG_THR_DBG_INFO_CFG_P2_CUR_THR_OFFSET) + #define RTL8373_P2_XG2XG_THR_DBG_INFO_CFG_P2_MAX_THR_OFFSET (0) + #define RTL8373_P2_XG2XG_THR_DBG_INFO_CFG_P2_MAX_THR_MASK (0x3F << RTL8373_P2_XG2XG_THR_DBG_INFO_CFG_P2_MAX_THR_OFFSET) + +#define RTL8373_G2G_WATER_LEVEL_ADDR (0x938) + #define RTL8373_G2G_WATER_LEVEL_CFG_G2G_WATER_LEVEL_X2Y_OFFSET (13) + #define RTL8373_G2G_WATER_LEVEL_CFG_G2G_WATER_LEVEL_X2Y_MASK (0x7 << RTL8373_G2G_WATER_LEVEL_CFG_G2G_WATER_LEVEL_X2Y_OFFSET) + #define RTL8373_G2G_WATER_LEVEL_CFG_G2G_WATER_LEVEL_Y2X_OFFSET (10) + #define RTL8373_G2G_WATER_LEVEL_CFG_G2G_WATER_LEVEL_Y2X_MASK (0x7 << RTL8373_G2G_WATER_LEVEL_CFG_G2G_WATER_LEVEL_Y2X_OFFSET) + #define RTL8373_G2G_WATER_LEVEL_CFG_G2G_WATER_LEVEL_FD_OFFSET (7) + #define RTL8373_G2G_WATER_LEVEL_CFG_G2G_WATER_LEVEL_FD_MASK (0x7 << RTL8373_G2G_WATER_LEVEL_CFG_G2G_WATER_LEVEL_FD_OFFSET) + #define RTL8373_G2G_WATER_LEVEL_CGF_G2G_LPBK_OFFSET (0) + #define RTL8373_G2G_WATER_LEVEL_CGF_G2G_LPBK_MASK (0xF << RTL8373_G2G_WATER_LEVEL_CGF_G2G_LPBK_OFFSET) + +#define RTL8373_G2G_MISC_CFG_ADDR (0x93C) + #define RTL8373_G2G_MISC_CFG_CLR_G2G_FIFO_OFFSET (12) + #define RTL8373_G2G_MISC_CFG_CLR_G2G_FIFO_MASK (0xF << RTL8373_G2G_MISC_CFG_CLR_G2G_FIFO_OFFSET) + #define RTL8373_G2G_MISC_CFG_CFG_CLR_FIFO_OVTHR_OFFSET (11) + #define RTL8373_G2G_MISC_CFG_CFG_CLR_FIFO_OVTHR_MASK (0x1 << RTL8373_G2G_MISC_CFG_CFG_CLR_FIFO_OVTHR_OFFSET) + #define RTL8373_G2G_MISC_CFG_CFG_G2G_DIS_AUTO_RST_FIFO_OFFSET (9) + #define RTL8373_G2G_MISC_CFG_CFG_G2G_DIS_AUTO_RST_FIFO_MASK (0x1 << RTL8373_G2G_MISC_CFG_CFG_G2G_DIS_AUTO_RST_FIFO_OFFSET) + #define RTL8373_G2G_MISC_CFG_CFG_G2G_AFO_IPGCOMP_OFFSET (8) + #define RTL8373_G2G_MISC_CFG_CFG_G2G_AFO_IPGCOMP_MASK (0x1 << RTL8373_G2G_MISC_CFG_CFG_G2G_AFO_IPGCOMP_OFFSET) + #define RTL8373_G2G_MISC_CFG_CFG_G2G_AFE_IPG_CNT_OFFSET (4) + #define RTL8373_G2G_MISC_CFG_CFG_G2G_AFE_IPG_CNT_MASK (0xF << RTL8373_G2G_MISC_CFG_CFG_G2G_AFE_IPG_CNT_OFFSET) + #define RTL8373_G2G_MISC_CFG_CFG_G2G_BGPTR_CHK_OFFSET (3) + #define RTL8373_G2G_MISC_CFG_CFG_G2G_BGPTR_CHK_MASK (0x1 << RTL8373_G2G_MISC_CFG_CFG_G2G_BGPTR_CHK_OFFSET) + #define RTL8373_G2G_MISC_CFG_CFG_G2G_EDPTR_CHK_OFFSET (2) + #define RTL8373_G2G_MISC_CFG_CFG_G2G_EDPTR_CHK_MASK (0x1 << RTL8373_G2G_MISC_CFG_CFG_G2G_EDPTR_CHK_OFFSET) + #define RTL8373_G2G_MISC_CFG_G2G_CLR_ERR_CNT_X2Y_OFFSET (1) + #define RTL8373_G2G_MISC_CFG_G2G_CLR_ERR_CNT_X2Y_MASK (0x1 << RTL8373_G2G_MISC_CFG_G2G_CLR_ERR_CNT_X2Y_OFFSET) + #define RTL8373_G2G_MISC_CFG_G2G_CLR_ERR_CNT_Y2X_OFFSET (0) + #define RTL8373_G2G_MISC_CFG_G2G_CLR_ERR_CNT_Y2X_MASK (0x1 << RTL8373_G2G_MISC_CFG_G2G_CLR_ERR_CNT_Y2X_OFFSET) + +#define RTL8373_G2G_ERR_CNT_01_ADDR (0x940) + #define RTL8373_G2G_ERR_CNT_01_G2G_0_ERR_CNT_X2Y_OFFSET (12) + #define RTL8373_G2G_ERR_CNT_01_G2G_0_ERR_CNT_X2Y_MASK (0xF << RTL8373_G2G_ERR_CNT_01_G2G_0_ERR_CNT_X2Y_OFFSET) + #define RTL8373_G2G_ERR_CNT_01_G2G_0_ERR_CNT_Y2X_OFFSET (8) + #define RTL8373_G2G_ERR_CNT_01_G2G_0_ERR_CNT_Y2X_MASK (0xF << RTL8373_G2G_ERR_CNT_01_G2G_0_ERR_CNT_Y2X_OFFSET) + #define RTL8373_G2G_ERR_CNT_01_G2G_1_ERR_CNT_X2Y_OFFSET (4) + #define RTL8373_G2G_ERR_CNT_01_G2G_1_ERR_CNT_X2Y_MASK (0xF << RTL8373_G2G_ERR_CNT_01_G2G_1_ERR_CNT_X2Y_OFFSET) + #define RTL8373_G2G_ERR_CNT_01_G2G_1_ERR_CNT_Y2X_OFFSET (0) + #define RTL8373_G2G_ERR_CNT_01_G2G_1_ERR_CNT_Y2X_MASK (0xF << RTL8373_G2G_ERR_CNT_01_G2G_1_ERR_CNT_Y2X_OFFSET) + +#define RTL8373_G2G_ERR_CNT_23_ADDR (0x944) + #define RTL8373_G2G_ERR_CNT_23_G2G_2_ERR_CNT_X2Y_OFFSET (12) + #define RTL8373_G2G_ERR_CNT_23_G2G_2_ERR_CNT_X2Y_MASK (0xF << RTL8373_G2G_ERR_CNT_23_G2G_2_ERR_CNT_X2Y_OFFSET) + #define RTL8373_G2G_ERR_CNT_23_G2G_2_ERR_CNT_Y2X_OFFSET (8) + #define RTL8373_G2G_ERR_CNT_23_G2G_2_ERR_CNT_Y2X_MASK (0xF << RTL8373_G2G_ERR_CNT_23_G2G_2_ERR_CNT_Y2X_OFFSET) + #define RTL8373_G2G_ERR_CNT_23_G2G_3_ERR_CNT_X2Y_OFFSET (4) + #define RTL8373_G2G_ERR_CNT_23_G2G_3_ERR_CNT_X2Y_MASK (0xF << RTL8373_G2G_ERR_CNT_23_G2G_3_ERR_CNT_X2Y_OFFSET) + #define RTL8373_G2G_ERR_CNT_23_G2G_3_ERR_CNT_Y2X_OFFSET (0) + #define RTL8373_G2G_ERR_CNT_23_G2G_3_ERR_CNT_Y2X_MASK (0xF << RTL8373_G2G_ERR_CNT_23_G2G_3_ERR_CNT_Y2X_OFFSET) + +#define RTL8373_XG2XG_WATER_LEVEL_ADDR (0x948) + #define RTL8373_XG2XG_WATER_LEVEL_CFG_WATER_LEVEL_H_OFFSET (7) + #define RTL8373_XG2XG_WATER_LEVEL_CFG_WATER_LEVEL_H_MASK (0x3F << RTL8373_XG2XG_WATER_LEVEL_CFG_WATER_LEVEL_H_OFFSET) + #define RTL8373_XG2XG_WATER_LEVEL_CFG_WATER_LEVEL_L_OFFSET (1) + #define RTL8373_XG2XG_WATER_LEVEL_CFG_WATER_LEVEL_L_MASK (0x3F << RTL8373_XG2XG_WATER_LEVEL_CFG_WATER_LEVEL_L_OFFSET) + #define RTL8373_XG2XG_WATER_LEVEL_CFG_EEE_DELETE_OFFSET (0) + #define RTL8373_XG2XG_WATER_LEVEL_CFG_EEE_DELETE_MASK (0x1 << RTL8373_XG2XG_WATER_LEVEL_CFG_EEE_DELETE_OFFSET) + +#define RTL8373_XG2XG_MISC_CFG_ADDR (0x94C) + #define RTL8373_XG2XG_MISC_CFG_CFG_FIFO_START_FB_OFFSET (15) + #define RTL8373_XG2XG_MISC_CFG_CFG_FIFO_START_FB_MASK (0x1 << RTL8373_XG2XG_MISC_CFG_CFG_FIFO_START_FB_OFFSET) + #define RTL8373_XG2XG_MISC_CFG_CFG_FIFO_START_SEQ_OFFSET (14) + #define RTL8373_XG2XG_MISC_CFG_CFG_FIFO_START_SEQ_MASK (0x1 << RTL8373_XG2XG_MISC_CFG_CFG_FIFO_START_SEQ_OFFSET) + #define RTL8373_XG2XG_MISC_CFG_CFG_XG2XG_FAULT_ON_OFFSET (13) + #define RTL8373_XG2XG_MISC_CFG_CFG_XG2XG_FAULT_ON_MASK (0x1 << RTL8373_XG2XG_MISC_CFG_CFG_XG2XG_FAULT_ON_OFFSET) + #define RTL8373_XG2XG_MISC_CFG_CFG_REC_LINK_INTR_OFFSET (12) + #define RTL8373_XG2XG_MISC_CFG_CFG_REC_LINK_INTR_MASK (0x1 << RTL8373_XG2XG_MISC_CFG_CFG_REC_LINK_INTR_OFFSET) + #define RTL8373_XG2XG_MISC_CFG_CFG_SEQ_RSV_ON_OFFSET (11) + #define RTL8373_XG2XG_MISC_CFG_CFG_SEQ_RSV_ON_MASK (0x1 << RTL8373_XG2XG_MISC_CFG_CFG_SEQ_RSV_ON_OFFSET) + #define RTL8373_XG2XG_MISC_CFG_CFG_ERROR_ON_OFFSET (10) + #define RTL8373_XG2XG_MISC_CFG_CFG_ERROR_ON_MASK (0x1 << RTL8373_XG2XG_MISC_CFG_CFG_ERROR_ON_OFFSET) + #define RTL8373_XG2XG_MISC_CFG_CFG_STK_PORT_P0_OFFSET (9) + #define RTL8373_XG2XG_MISC_CFG_CFG_STK_PORT_P0_MASK (0x1 << RTL8373_XG2XG_MISC_CFG_CFG_STK_PORT_P0_OFFSET) + #define RTL8373_XG2XG_MISC_CFG_CFG_LDN_CLR_FIFO_FRC_VAL_OFFSET (4) + #define RTL8373_XG2XG_MISC_CFG_CFG_LDN_CLR_FIFO_FRC_VAL_MASK (0xF << RTL8373_XG2XG_MISC_CFG_CFG_LDN_CLR_FIFO_FRC_VAL_OFFSET) + #define RTL8373_XG2XG_MISC_CFG_CFG_LDN_CLR_FIFO_FRC_ON_OFFSET (0) + #define RTL8373_XG2XG_MISC_CFG_CFG_LDN_CLR_FIFO_FRC_ON_MASK (0xF << RTL8373_XG2XG_MISC_CFG_CFG_LDN_CLR_FIFO_FRC_ON_OFFSET) + +#define RTL8373_XG2XG_ERR_STATUS_ADDR (0x950) + #define RTL8373_XG2XG_ERR_STATUS_XG2XG_OVRUN_X_OFFSET (12) + #define RTL8373_XG2XG_ERR_STATUS_XG2XG_OVRUN_X_MASK (0xF << RTL8373_XG2XG_ERR_STATUS_XG2XG_OVRUN_X_OFFSET) + #define RTL8373_XG2XG_ERR_STATUS_XG2XG_UDRUN_X_OFFSET (8) + #define RTL8373_XG2XG_ERR_STATUS_XG2XG_UDRUN_X_MASK (0xF << RTL8373_XG2XG_ERR_STATUS_XG2XG_UDRUN_X_OFFSET) + #define RTL8373_XG2XG_ERR_STATUS_XG2XG_OVRUN_Y_OFFSET (4) + #define RTL8373_XG2XG_ERR_STATUS_XG2XG_OVRUN_Y_MASK (0xF << RTL8373_XG2XG_ERR_STATUS_XG2XG_OVRUN_Y_OFFSET) + #define RTL8373_XG2XG_ERR_STATUS_XG2XG_UDRUN_Y_OFFSET (0) + #define RTL8373_XG2XG_ERR_STATUS_XG2XG_UDRUN_Y_MASK (0xF << RTL8373_XG2XG_ERR_STATUS_XG2XG_UDRUN_Y_OFFSET) + +#define RTL8373_EEE_LPI_DLY_CYCLE_ADDR (0x954) + #define RTL8373_EEE_LPI_DLY_CYCLE_CFG_WATER_LEVEL_ST_OFFSET (8) + #define RTL8373_EEE_LPI_DLY_CYCLE_CFG_WATER_LEVEL_ST_MASK (0x3F << RTL8373_EEE_LPI_DLY_CYCLE_CFG_WATER_LEVEL_ST_OFFSET) + #define RTL8373_EEE_LPI_DLY_CYCLE_TX_LPI_DLY_CYCLE_OFFSET (4) + #define RTL8373_EEE_LPI_DLY_CYCLE_TX_LPI_DLY_CYCLE_MASK (0xF << RTL8373_EEE_LPI_DLY_CYCLE_TX_LPI_DLY_CYCLE_OFFSET) + #define RTL8373_EEE_LPI_DLY_CYCLE_RX_LPI_DLY_CYCLE_OFFSET (0) + #define RTL8373_EEE_LPI_DLY_CYCLE_RX_LPI_DLY_CYCLE_MASK (0xF << RTL8373_EEE_LPI_DLY_CYCLE_RX_LPI_DLY_CYCLE_OFFSET) + +#define RTL8373_PREAMBLE_RECOVERY_CRTL_ADDR (0x958) + #define RTL8373_PREAMBLE_RECOVERY_CRTL_CFG_PRMB_6BYTE_MODE_OFFSET (5) + #define RTL8373_PREAMBLE_RECOVERY_CRTL_CFG_PRMB_6BYTE_MODE_MASK (0x1 << RTL8373_PREAMBLE_RECOVERY_CRTL_CFG_PRMB_6BYTE_MODE_OFFSET) + #define RTL8373_PREAMBLE_RECOVERY_CRTL_CFG_PRMB_RCVY_EN_OFFSET (4) + #define RTL8373_PREAMBLE_RECOVERY_CRTL_CFG_PRMB_RCVY_EN_MASK (0x1 << RTL8373_PREAMBLE_RECOVERY_CRTL_CFG_PRMB_RCVY_EN_OFFSET) + #define RTL8373_PREAMBLE_RECOVERY_CRTL_PRMB_RCVY_OVTHR_MON_OFFSET (0) + #define RTL8373_PREAMBLE_RECOVERY_CRTL_PRMB_RCVY_OVTHR_MON_MASK (0xF << RTL8373_PREAMBLE_RECOVERY_CRTL_PRMB_RCVY_OVTHR_MON_OFFSET) + +#define RTL8373_G2G_FIFO_CLR_CFG_ADDR (0x95C) + #define RTL8373_G2G_FIFO_CLR_CFG_P3_LDN_CLR_G2G_FIFO_RX_OFFSET (15) + #define RTL8373_G2G_FIFO_CLR_CFG_P3_LDN_CLR_G2G_FIFO_RX_MASK (0x1 << RTL8373_G2G_FIFO_CLR_CFG_P3_LDN_CLR_G2G_FIFO_RX_OFFSET) + #define RTL8373_G2G_FIFO_CLR_CFG_P2_LDN_CLR_G2G_FIFO_RX_OFFSET (14) + #define RTL8373_G2G_FIFO_CLR_CFG_P2_LDN_CLR_G2G_FIFO_RX_MASK (0x1 << RTL8373_G2G_FIFO_CLR_CFG_P2_LDN_CLR_G2G_FIFO_RX_OFFSET) + #define RTL8373_G2G_FIFO_CLR_CFG_P1_LDN_CLR_G2G_FIFO_RX_OFFSET (13) + #define RTL8373_G2G_FIFO_CLR_CFG_P1_LDN_CLR_G2G_FIFO_RX_MASK (0x1 << RTL8373_G2G_FIFO_CLR_CFG_P1_LDN_CLR_G2G_FIFO_RX_OFFSET) + #define RTL8373_G2G_FIFO_CLR_CFG_P0_LDN_CLR_G2G_FIFO_RX_OFFSET (12) + #define RTL8373_G2G_FIFO_CLR_CFG_P0_LDN_CLR_G2G_FIFO_RX_MASK (0x1 << RTL8373_G2G_FIFO_CLR_CFG_P0_LDN_CLR_G2G_FIFO_RX_OFFSET) + #define RTL8373_G2G_FIFO_CLR_CFG_P3_CLR_G2G_FIFO_RX_OFFSET (11) + #define RTL8373_G2G_FIFO_CLR_CFG_P3_CLR_G2G_FIFO_RX_MASK (0x1 << RTL8373_G2G_FIFO_CLR_CFG_P3_CLR_G2G_FIFO_RX_OFFSET) + #define RTL8373_G2G_FIFO_CLR_CFG_P2_CLR_G2G_FIFO_RX_OFFSET (10) + #define RTL8373_G2G_FIFO_CLR_CFG_P2_CLR_G2G_FIFO_RX_MASK (0x1 << RTL8373_G2G_FIFO_CLR_CFG_P2_CLR_G2G_FIFO_RX_OFFSET) + #define RTL8373_G2G_FIFO_CLR_CFG_P1_CLR_G2G_FIFO_RX_OFFSET (9) + #define RTL8373_G2G_FIFO_CLR_CFG_P1_CLR_G2G_FIFO_RX_MASK (0x1 << RTL8373_G2G_FIFO_CLR_CFG_P1_CLR_G2G_FIFO_RX_OFFSET) + #define RTL8373_G2G_FIFO_CLR_CFG_P0_CLR_G2G_FIFO_RX_OFFSET (8) + #define RTL8373_G2G_FIFO_CLR_CFG_P0_CLR_G2G_FIFO_RX_MASK (0x1 << RTL8373_G2G_FIFO_CLR_CFG_P0_CLR_G2G_FIFO_RX_OFFSET) + #define RTL8373_G2G_FIFO_CLR_CFG_P3_LDN_CLR_G2G_FIFO_TX_OFFSET (7) + #define RTL8373_G2G_FIFO_CLR_CFG_P3_LDN_CLR_G2G_FIFO_TX_MASK (0x1 << RTL8373_G2G_FIFO_CLR_CFG_P3_LDN_CLR_G2G_FIFO_TX_OFFSET) + #define RTL8373_G2G_FIFO_CLR_CFG_P2_LDN_CLR_G2G_FIFO_TX_OFFSET (6) + #define RTL8373_G2G_FIFO_CLR_CFG_P2_LDN_CLR_G2G_FIFO_TX_MASK (0x1 << RTL8373_G2G_FIFO_CLR_CFG_P2_LDN_CLR_G2G_FIFO_TX_OFFSET) + #define RTL8373_G2G_FIFO_CLR_CFG_P1_LDN_CLR_G2G_FIFO_TX_OFFSET (5) + #define RTL8373_G2G_FIFO_CLR_CFG_P1_LDN_CLR_G2G_FIFO_TX_MASK (0x1 << RTL8373_G2G_FIFO_CLR_CFG_P1_LDN_CLR_G2G_FIFO_TX_OFFSET) + #define RTL8373_G2G_FIFO_CLR_CFG_P0_LDN_CLR_G2G_FIFO_TX_OFFSET (4) + #define RTL8373_G2G_FIFO_CLR_CFG_P0_LDN_CLR_G2G_FIFO_TX_MASK (0x1 << RTL8373_G2G_FIFO_CLR_CFG_P0_LDN_CLR_G2G_FIFO_TX_OFFSET) + #define RTL8373_G2G_FIFO_CLR_CFG_P3_CLR_G2G_FIFO_TX_OFFSET (3) + #define RTL8373_G2G_FIFO_CLR_CFG_P3_CLR_G2G_FIFO_TX_MASK (0x1 << RTL8373_G2G_FIFO_CLR_CFG_P3_CLR_G2G_FIFO_TX_OFFSET) + #define RTL8373_G2G_FIFO_CLR_CFG_P2_CLR_G2G_FIFO_TX_OFFSET (2) + #define RTL8373_G2G_FIFO_CLR_CFG_P2_CLR_G2G_FIFO_TX_MASK (0x1 << RTL8373_G2G_FIFO_CLR_CFG_P2_CLR_G2G_FIFO_TX_OFFSET) + #define RTL8373_G2G_FIFO_CLR_CFG_P1_CLR_G2G_FIFO_TX_OFFSET (1) + #define RTL8373_G2G_FIFO_CLR_CFG_P1_CLR_G2G_FIFO_TX_MASK (0x1 << RTL8373_G2G_FIFO_CLR_CFG_P1_CLR_G2G_FIFO_TX_OFFSET) + #define RTL8373_G2G_FIFO_CLR_CFG_P0_CLR_G2G_FIFO_TX_OFFSET (0) + #define RTL8373_G2G_FIFO_CLR_CFG_P0_CLR_G2G_FIFO_TX_MASK (0x1 << RTL8373_G2G_FIFO_CLR_CFG_P0_CLR_G2G_FIFO_TX_OFFSET) + +#define RTL8373_XG2XG_FIFO_CLR_CFG_ADDR (0x960) + #define RTL8373_XG2XG_FIFO_CLR_CFG_P3_LDN_CLR_XG2XG_FIFO_RX_OFFSET (15) + #define RTL8373_XG2XG_FIFO_CLR_CFG_P3_LDN_CLR_XG2XG_FIFO_RX_MASK (0x1 << RTL8373_XG2XG_FIFO_CLR_CFG_P3_LDN_CLR_XG2XG_FIFO_RX_OFFSET) + #define RTL8373_XG2XG_FIFO_CLR_CFG_P2_LDN_CLR_XG2XG_FIFO_RX_OFFSET (14) + #define RTL8373_XG2XG_FIFO_CLR_CFG_P2_LDN_CLR_XG2XG_FIFO_RX_MASK (0x1 << RTL8373_XG2XG_FIFO_CLR_CFG_P2_LDN_CLR_XG2XG_FIFO_RX_OFFSET) + #define RTL8373_XG2XG_FIFO_CLR_CFG_P1_LDN_CLR_XG2XG_FIFO_RX_OFFSET (13) + #define RTL8373_XG2XG_FIFO_CLR_CFG_P1_LDN_CLR_XG2XG_FIFO_RX_MASK (0x1 << RTL8373_XG2XG_FIFO_CLR_CFG_P1_LDN_CLR_XG2XG_FIFO_RX_OFFSET) + #define RTL8373_XG2XG_FIFO_CLR_CFG_P0_LDN_CLR_XG2XG_FIFO_RX_OFFSET (12) + #define RTL8373_XG2XG_FIFO_CLR_CFG_P0_LDN_CLR_XG2XG_FIFO_RX_MASK (0x1 << RTL8373_XG2XG_FIFO_CLR_CFG_P0_LDN_CLR_XG2XG_FIFO_RX_OFFSET) + #define RTL8373_XG2XG_FIFO_CLR_CFG_P3_CLR_XG2XG_FIFO_RX_OFFSET (11) + #define RTL8373_XG2XG_FIFO_CLR_CFG_P3_CLR_XG2XG_FIFO_RX_MASK (0x1 << RTL8373_XG2XG_FIFO_CLR_CFG_P3_CLR_XG2XG_FIFO_RX_OFFSET) + #define RTL8373_XG2XG_FIFO_CLR_CFG_P2_CLR_XG2XG_FIFO_RX_OFFSET (10) + #define RTL8373_XG2XG_FIFO_CLR_CFG_P2_CLR_XG2XG_FIFO_RX_MASK (0x1 << RTL8373_XG2XG_FIFO_CLR_CFG_P2_CLR_XG2XG_FIFO_RX_OFFSET) + #define RTL8373_XG2XG_FIFO_CLR_CFG_P1_CLR_XG2XG_FIFO_RX_OFFSET (9) + #define RTL8373_XG2XG_FIFO_CLR_CFG_P1_CLR_XG2XG_FIFO_RX_MASK (0x1 << RTL8373_XG2XG_FIFO_CLR_CFG_P1_CLR_XG2XG_FIFO_RX_OFFSET) + #define RTL8373_XG2XG_FIFO_CLR_CFG_P0_CLR_XG2XG_FIFO_RX_OFFSET (8) + #define RTL8373_XG2XG_FIFO_CLR_CFG_P0_CLR_XG2XG_FIFO_RX_MASK (0x1 << RTL8373_XG2XG_FIFO_CLR_CFG_P0_CLR_XG2XG_FIFO_RX_OFFSET) + #define RTL8373_XG2XG_FIFO_CLR_CFG_P3_LDN_CLR_XG2XG_FIFO_TX_OFFSET (7) + #define RTL8373_XG2XG_FIFO_CLR_CFG_P3_LDN_CLR_XG2XG_FIFO_TX_MASK (0x1 << RTL8373_XG2XG_FIFO_CLR_CFG_P3_LDN_CLR_XG2XG_FIFO_TX_OFFSET) + #define RTL8373_XG2XG_FIFO_CLR_CFG_P2_LDN_CLR_XG2XG_FIFO_TX_OFFSET (6) + #define RTL8373_XG2XG_FIFO_CLR_CFG_P2_LDN_CLR_XG2XG_FIFO_TX_MASK (0x1 << RTL8373_XG2XG_FIFO_CLR_CFG_P2_LDN_CLR_XG2XG_FIFO_TX_OFFSET) + #define RTL8373_XG2XG_FIFO_CLR_CFG_P1_LDN_CLR_XG2XG_FIFO_TX_OFFSET (5) + #define RTL8373_XG2XG_FIFO_CLR_CFG_P1_LDN_CLR_XG2XG_FIFO_TX_MASK (0x1 << RTL8373_XG2XG_FIFO_CLR_CFG_P1_LDN_CLR_XG2XG_FIFO_TX_OFFSET) + #define RTL8373_XG2XG_FIFO_CLR_CFG_P0_LDN_CLR_XG2XG_FIFO_TX_OFFSET (4) + #define RTL8373_XG2XG_FIFO_CLR_CFG_P0_LDN_CLR_XG2XG_FIFO_TX_MASK (0x1 << RTL8373_XG2XG_FIFO_CLR_CFG_P0_LDN_CLR_XG2XG_FIFO_TX_OFFSET) + #define RTL8373_XG2XG_FIFO_CLR_CFG_P3_CLR_XG2XG_FIFO_TX_OFFSET (3) + #define RTL8373_XG2XG_FIFO_CLR_CFG_P3_CLR_XG2XG_FIFO_TX_MASK (0x1 << RTL8373_XG2XG_FIFO_CLR_CFG_P3_CLR_XG2XG_FIFO_TX_OFFSET) + #define RTL8373_XG2XG_FIFO_CLR_CFG_P2_CLR_XG2XG_FIFO_TX_OFFSET (2) + #define RTL8373_XG2XG_FIFO_CLR_CFG_P2_CLR_XG2XG_FIFO_TX_MASK (0x1 << RTL8373_XG2XG_FIFO_CLR_CFG_P2_CLR_XG2XG_FIFO_TX_OFFSET) + #define RTL8373_XG2XG_FIFO_CLR_CFG_P1_CLR_XG2XG_FIFO_TX_OFFSET (1) + #define RTL8373_XG2XG_FIFO_CLR_CFG_P1_CLR_XG2XG_FIFO_TX_MASK (0x1 << RTL8373_XG2XG_FIFO_CLR_CFG_P1_CLR_XG2XG_FIFO_TX_OFFSET) + #define RTL8373_XG2XG_FIFO_CLR_CFG_P0_CLR_XG2XG_FIFO_TX_OFFSET (0) + #define RTL8373_XG2XG_FIFO_CLR_CFG_P0_CLR_XG2XG_FIFO_TX_MASK (0x1 << RTL8373_XG2XG_FIFO_CLR_CFG_P0_CLR_XG2XG_FIFO_TX_OFFSET) + +#define RTL8373_P3_XG2XG_IPG_DBG_INFO_ADDR (0x964) + #define RTL8373_P3_XG2XG_IPG_DBG_INFO_CFG_P3_DBG_INFO_OFF_OFFSET (15) + #define RTL8373_P3_XG2XG_IPG_DBG_INFO_CFG_P3_DBG_INFO_OFF_MASK (0x1 << RTL8373_P3_XG2XG_IPG_DBG_INFO_CFG_P3_DBG_INFO_OFF_OFFSET) + #define RTL8373_P3_XG2XG_IPG_DBG_INFO_CFG_P3_CUR_IPG_OFFSET (10) + #define RTL8373_P3_XG2XG_IPG_DBG_INFO_CFG_P3_CUR_IPG_MASK (0x1F << RTL8373_P3_XG2XG_IPG_DBG_INFO_CFG_P3_CUR_IPG_OFFSET) + #define RTL8373_P3_XG2XG_IPG_DBG_INFO_CFG_P3_MAX_IPG_OFFSET (5) + #define RTL8373_P3_XG2XG_IPG_DBG_INFO_CFG_P3_MAX_IPG_MASK (0x1F << RTL8373_P3_XG2XG_IPG_DBG_INFO_CFG_P3_MAX_IPG_OFFSET) + #define RTL8373_P3_XG2XG_IPG_DBG_INFO_CFG_P3_MIN_IPG_OFFSET (0) + #define RTL8373_P3_XG2XG_IPG_DBG_INFO_CFG_P3_MIN_IPG_MASK (0x1F << RTL8373_P3_XG2XG_IPG_DBG_INFO_CFG_P3_MIN_IPG_OFFSET) + +#define RTL8373_P3_XG2XG_PRMB_DBG_INFO_ADDR (0x968) + #define RTL8373_P3_XG2XG_PRMB_DBG_INFO_CFG_P3_CUR_PRMB_OFFSET (8) + #define RTL8373_P3_XG2XG_PRMB_DBG_INFO_CFG_P3_CUR_PRMB_MASK (0xF << RTL8373_P3_XG2XG_PRMB_DBG_INFO_CFG_P3_CUR_PRMB_OFFSET) + #define RTL8373_P3_XG2XG_PRMB_DBG_INFO_CFG_P3_MAX_PRMB_OFFSET (4) + #define RTL8373_P3_XG2XG_PRMB_DBG_INFO_CFG_P3_MAX_PRMB_MASK (0xF << RTL8373_P3_XG2XG_PRMB_DBG_INFO_CFG_P3_MAX_PRMB_OFFSET) + #define RTL8373_P3_XG2XG_PRMB_DBG_INFO_CFG_P3_MIN_PRMB_OFFSET (0) + #define RTL8373_P3_XG2XG_PRMB_DBG_INFO_CFG_P3_MIN_PRMB_MASK (0xF << RTL8373_P3_XG2XG_PRMB_DBG_INFO_CFG_P3_MIN_PRMB_OFFSET) + +#define RTL8373_P3_XG2XG_THR_DBG_INFO_ADDR (0x96C) + #define RTL8373_P3_XG2XG_THR_DBG_INFO_CFG_P3_CUR_THR_OFFSET (6) + #define RTL8373_P3_XG2XG_THR_DBG_INFO_CFG_P3_CUR_THR_MASK (0x3F << RTL8373_P3_XG2XG_THR_DBG_INFO_CFG_P3_CUR_THR_OFFSET) + #define RTL8373_P3_XG2XG_THR_DBG_INFO_CFG_P3_MAX_THR_OFFSET (0) + #define RTL8373_P3_XG2XG_THR_DBG_INFO_CFG_P3_MAX_THR_MASK (0x3F << RTL8373_P3_XG2XG_THR_DBG_INFO_CFG_P3_MAX_THR_OFFSET) + +#define RTL8373_SYNCE_CTRL_0_ADDR (0xBA8) + #define RTL8373_SYNCE_CTRL_0_REG_EN_LOCK_SEL_MANUAL1_OFFSET (29) + #define RTL8373_SYNCE_CTRL_0_REG_EN_LOCK_SEL_MANUAL1_MASK (0x1 << RTL8373_SYNCE_CTRL_0_REG_EN_LOCK_SEL_MANUAL1_OFFSET) + #define RTL8373_SYNCE_CTRL_0_CFG_LOCK_SEL1_OFFSET (28) + #define RTL8373_SYNCE_CTRL_0_CFG_LOCK_SEL1_MASK (0x1 << RTL8373_SYNCE_CTRL_0_CFG_LOCK_SEL1_OFFSET) + #define RTL8373_SYNCE_CTRL_0_REG_SYNC_LOCK_OUT_SEL1_OFFSET (26) + #define RTL8373_SYNCE_CTRL_0_REG_SYNC_LOCK_OUT_SEL1_MASK (0x3 << RTL8373_SYNCE_CTRL_0_REG_SYNC_LOCK_OUT_SEL1_OFFSET) + #define RTL8373_SYNCE_CTRL_0_REG_EN_SYNC_OUT_MANUAL1_OFFSET (25) + #define RTL8373_SYNCE_CTRL_0_REG_EN_SYNC_OUT_MANUAL1_MASK (0x1 << RTL8373_SYNCE_CTRL_0_REG_EN_SYNC_OUT_MANUAL1_OFFSET) + #define RTL8373_SYNCE_CTRL_0_REG_EN_ICG_MANUAL1_OFFSET (24) + #define RTL8373_SYNCE_CTRL_0_REG_EN_ICG_MANUAL1_MASK (0x1 << RTL8373_SYNCE_CTRL_0_REG_EN_ICG_MANUAL1_OFFSET) + #define RTL8373_SYNCE_CTRL_0_TRAIN_SRC1_OFFSET (23) + #define RTL8373_SYNCE_CTRL_0_TRAIN_SRC1_MASK (0x1 << RTL8373_SYNCE_CTRL_0_TRAIN_SRC1_OFFSET) + #define RTL8373_SYNCE_CTRL_0_REG_PHY_SEL1_OFFSET (21) + #define RTL8373_SYNCE_CTRL_0_REG_PHY_SEL1_MASK (0x3 << RTL8373_SYNCE_CTRL_0_REG_PHY_SEL1_OFFSET) + #define RTL8373_SYNCE_CTRL_0_CFG_SYNC_OUT_SEL1_OFFSET (20) + #define RTL8373_SYNCE_CTRL_0_CFG_SYNC_OUT_SEL1_MASK (0x1 << RTL8373_SYNCE_CTRL_0_CFG_SYNC_OUT_SEL1_OFFSET) + #define RTL8373_SYNCE_CTRL_0_CFG_EN_ICG_SEL1_OFFSET (19) + #define RTL8373_SYNCE_CTRL_0_CFG_EN_ICG_SEL1_MASK (0x1 << RTL8373_SYNCE_CTRL_0_CFG_EN_ICG_SEL1_OFFSET) + #define RTL8373_SYNCE_CTRL_0_CFG_IDLE_MODE1_OFFSET (18) + #define RTL8373_SYNCE_CTRL_0_CFG_IDLE_MODE1_MASK (0x1 << RTL8373_SYNCE_CTRL_0_CFG_IDLE_MODE1_OFFSET) + #define RTL8373_SYNCE_CTRL_0_CFG_IDLE_OUT_SEL1_OFFSET (17) + #define RTL8373_SYNCE_CTRL_0_CFG_IDLE_OUT_SEL1_MASK (0x1 << RTL8373_SYNCE_CTRL_0_CFG_IDLE_OUT_SEL1_OFFSET) + #define RTL8373_SYNCE_CTRL_0_REG_DIVIDER_SEL1_OFFSET (16) + #define RTL8373_SYNCE_CTRL_0_REG_DIVIDER_SEL1_MASK (0x1 << RTL8373_SYNCE_CTRL_0_REG_DIVIDER_SEL1_OFFSET) + #define RTL8373_SYNCE_CTRL_0_REG_EN_LOCK_SEL_MANUAL0_OFFSET (13) + #define RTL8373_SYNCE_CTRL_0_REG_EN_LOCK_SEL_MANUAL0_MASK (0x1 << RTL8373_SYNCE_CTRL_0_REG_EN_LOCK_SEL_MANUAL0_OFFSET) + #define RTL8373_SYNCE_CTRL_0_CFG_LOCK_SEL0_OFFSET (12) + #define RTL8373_SYNCE_CTRL_0_CFG_LOCK_SEL0_MASK (0x1 << RTL8373_SYNCE_CTRL_0_CFG_LOCK_SEL0_OFFSET) + #define RTL8373_SYNCE_CTRL_0_REG_SYNC_LOCK_OUT_SEL0_OFFSET (10) + #define RTL8373_SYNCE_CTRL_0_REG_SYNC_LOCK_OUT_SEL0_MASK (0x3 << RTL8373_SYNCE_CTRL_0_REG_SYNC_LOCK_OUT_SEL0_OFFSET) + #define RTL8373_SYNCE_CTRL_0_REG_EN_SYNC_OUT_MANUAL0_OFFSET (9) + #define RTL8373_SYNCE_CTRL_0_REG_EN_SYNC_OUT_MANUAL0_MASK (0x1 << RTL8373_SYNCE_CTRL_0_REG_EN_SYNC_OUT_MANUAL0_OFFSET) + #define RTL8373_SYNCE_CTRL_0_REG_EN_ICG_MANUAL0_OFFSET (8) + #define RTL8373_SYNCE_CTRL_0_REG_EN_ICG_MANUAL0_MASK (0x1 << RTL8373_SYNCE_CTRL_0_REG_EN_ICG_MANUAL0_OFFSET) + #define RTL8373_SYNCE_CTRL_0_TRAIN_SRC0_OFFSET (7) + #define RTL8373_SYNCE_CTRL_0_TRAIN_SRC0_MASK (0x1 << RTL8373_SYNCE_CTRL_0_TRAIN_SRC0_OFFSET) + #define RTL8373_SYNCE_CTRL_0_REG_PHY_SEL0_OFFSET (5) + #define RTL8373_SYNCE_CTRL_0_REG_PHY_SEL0_MASK (0x3 << RTL8373_SYNCE_CTRL_0_REG_PHY_SEL0_OFFSET) + #define RTL8373_SYNCE_CTRL_0_CFG_SYNC_OUT_SEL0_OFFSET (4) + #define RTL8373_SYNCE_CTRL_0_CFG_SYNC_OUT_SEL0_MASK (0x1 << RTL8373_SYNCE_CTRL_0_CFG_SYNC_OUT_SEL0_OFFSET) + #define RTL8373_SYNCE_CTRL_0_CFG_EN_ICG_SEL0_OFFSET (3) + #define RTL8373_SYNCE_CTRL_0_CFG_EN_ICG_SEL0_MASK (0x1 << RTL8373_SYNCE_CTRL_0_CFG_EN_ICG_SEL0_OFFSET) + #define RTL8373_SYNCE_CTRL_0_CFG_IDLE_MODE0_OFFSET (2) + #define RTL8373_SYNCE_CTRL_0_CFG_IDLE_MODE0_MASK (0x1 << RTL8373_SYNCE_CTRL_0_CFG_IDLE_MODE0_OFFSET) + #define RTL8373_SYNCE_CTRL_0_CFG_IDLE_OUT_SEL0_OFFSET (1) + #define RTL8373_SYNCE_CTRL_0_CFG_IDLE_OUT_SEL0_MASK (0x1 << RTL8373_SYNCE_CTRL_0_CFG_IDLE_OUT_SEL0_OFFSET) + #define RTL8373_SYNCE_CTRL_0_REG_DIVIDER_SEL0_OFFSET (0) + #define RTL8373_SYNCE_CTRL_0_REG_DIVIDER_SEL0_MASK (0x1 << RTL8373_SYNCE_CTRL_0_REG_DIVIDER_SEL0_OFFSET) + +#define RTL8373_SYNCE_CTRL_1_ADDR (0xBAC) + #define RTL8373_SYNCE_CTRL_1_CFG_CKR_SEL3_OFFSET (27) + #define RTL8373_SYNCE_CTRL_1_CFG_CKR_SEL3_MASK (0x1 << RTL8373_SYNCE_CTRL_1_CFG_CKR_SEL3_OFFSET) + #define RTL8373_SYNCE_CTRL_1_CFG_CKR_SEL2_OFFSET (26) + #define RTL8373_SYNCE_CTRL_1_CFG_CKR_SEL2_MASK (0x1 << RTL8373_SYNCE_CTRL_1_CFG_CKR_SEL2_OFFSET) + #define RTL8373_SYNCE_CTRL_1_CFG_CKR_SEL1_OFFSET (25) + #define RTL8373_SYNCE_CTRL_1_CFG_CKR_SEL1_MASK (0x1 << RTL8373_SYNCE_CTRL_1_CFG_CKR_SEL1_OFFSET) + #define RTL8373_SYNCE_CTRL_1_CFG_CKR_SEL0_OFFSET (24) + #define RTL8373_SYNCE_CTRL_1_CFG_CKR_SEL0_MASK (0x1 << RTL8373_SYNCE_CTRL_1_CFG_CKR_SEL0_OFFSET) + #define RTL8373_SYNCE_CTRL_1_CFG_CLK_CH_SEL3_OFFSET (22) + #define RTL8373_SYNCE_CTRL_1_CFG_CLK_CH_SEL3_MASK (0x3 << RTL8373_SYNCE_CTRL_1_CFG_CLK_CH_SEL3_OFFSET) + #define RTL8373_SYNCE_CTRL_1_CFG_CLK_CH_SEL2_OFFSET (20) + #define RTL8373_SYNCE_CTRL_1_CFG_CLK_CH_SEL2_MASK (0x3 << RTL8373_SYNCE_CTRL_1_CFG_CLK_CH_SEL2_OFFSET) + #define RTL8373_SYNCE_CTRL_1_CFG_CLK_CH_SEL1_OFFSET (18) + #define RTL8373_SYNCE_CTRL_1_CFG_CLK_CH_SEL1_MASK (0x3 << RTL8373_SYNCE_CTRL_1_CFG_CLK_CH_SEL1_OFFSET) + #define RTL8373_SYNCE_CTRL_1_CFG_CLK_CH_SEL0_OFFSET (16) + #define RTL8373_SYNCE_CTRL_1_CFG_CLK_CH_SEL0_MASK (0x3 << RTL8373_SYNCE_CTRL_1_CFG_CLK_CH_SEL0_OFFSET) + #define RTL8373_SYNCE_CTRL_1_SYNCE_EN1_OFFSET (11) + #define RTL8373_SYNCE_CTRL_1_SYNCE_EN1_MASK (0x1 << RTL8373_SYNCE_CTRL_1_SYNCE_EN1_OFFSET) + #define RTL8373_SYNCE_CTRL_1_SYNCE_EN0_OFFSET (10) + #define RTL8373_SYNCE_CTRL_1_SYNCE_EN0_MASK (0x1 << RTL8373_SYNCE_CTRL_1_SYNCE_EN0_OFFSET) + #define RTL8373_SYNCE_CTRL_1_REG_EN_CKR_SEL_MANUAL3_OFFSET (9) + #define RTL8373_SYNCE_CTRL_1_REG_EN_CKR_SEL_MANUAL3_MASK (0x1 << RTL8373_SYNCE_CTRL_1_REG_EN_CKR_SEL_MANUAL3_OFFSET) + #define RTL8373_SYNCE_CTRL_1_REG_EN_CKR_SEL_MANUAL2_OFFSET (8) + #define RTL8373_SYNCE_CTRL_1_REG_EN_CKR_SEL_MANUAL2_MASK (0x1 << RTL8373_SYNCE_CTRL_1_REG_EN_CKR_SEL_MANUAL2_OFFSET) + #define RTL8373_SYNCE_CTRL_1_REG_EN_CKR_SEL_MANUAL1_OFFSET (7) + #define RTL8373_SYNCE_CTRL_1_REG_EN_CKR_SEL_MANUAL1_MASK (0x1 << RTL8373_SYNCE_CTRL_1_REG_EN_CKR_SEL_MANUAL1_OFFSET) + #define RTL8373_SYNCE_CTRL_1_REG_EN_CKR_SEL_MANUAL0_OFFSET (6) + #define RTL8373_SYNCE_CTRL_1_REG_EN_CKR_SEL_MANUAL0_MASK (0x1 << RTL8373_SYNCE_CTRL_1_REG_EN_CKR_SEL_MANUAL0_OFFSET) + #define RTL8373_SYNCE_CTRL_1_REG_EN_CH_SEL_MANUAL3_OFFSET (5) + #define RTL8373_SYNCE_CTRL_1_REG_EN_CH_SEL_MANUAL3_MASK (0x1 << RTL8373_SYNCE_CTRL_1_REG_EN_CH_SEL_MANUAL3_OFFSET) + #define RTL8373_SYNCE_CTRL_1_REG_EN_CH_SEL_MANUAL2_OFFSET (4) + #define RTL8373_SYNCE_CTRL_1_REG_EN_CH_SEL_MANUAL2_MASK (0x1 << RTL8373_SYNCE_CTRL_1_REG_EN_CH_SEL_MANUAL2_OFFSET) + #define RTL8373_SYNCE_CTRL_1_REG_EN_CH_SEL_MANUAL1_OFFSET (3) + #define RTL8373_SYNCE_CTRL_1_REG_EN_CH_SEL_MANUAL1_MASK (0x1 << RTL8373_SYNCE_CTRL_1_REG_EN_CH_SEL_MANUAL1_OFFSET) + #define RTL8373_SYNCE_CTRL_1_REG_EN_CH_SEL_MANUAL0_OFFSET (2) + #define RTL8373_SYNCE_CTRL_1_REG_EN_CH_SEL_MANUAL0_MASK (0x1 << RTL8373_SYNCE_CTRL_1_REG_EN_CH_SEL_MANUAL0_OFFSET) + #define RTL8373_SYNCE_CTRL_1_EN_SYNCE_LOCK1_OFFSET (1) + #define RTL8373_SYNCE_CTRL_1_EN_SYNCE_LOCK1_MASK (0x1 << RTL8373_SYNCE_CTRL_1_EN_SYNCE_LOCK1_OFFSET) + #define RTL8373_SYNCE_CTRL_1_EN_SYNCE_LOCK0_OFFSET (0) + #define RTL8373_SYNCE_CTRL_1_EN_SYNCE_LOCK0_MASK (0x1 << RTL8373_SYNCE_CTRL_1_EN_SYNCE_LOCK0_OFFSET) + +#define RTL8373_SYNCE_DUMMY1_ADDR (0xBB0) + #define RTL8373_SYNCE_DUMMY1_SYNCE_DUMMY1_OFFSET (0) + #define RTL8373_SYNCE_DUMMY1_SYNCE_DUMMY1_MASK (0xFFFFFFFF << RTL8373_SYNCE_DUMMY1_SYNCE_DUMMY1_OFFSET) + +#define RTL8373_SYNCE_DUMMY2_ADDR (0xBB4) + #define RTL8373_SYNCE_DUMMY2_SYNCE_DUMMY2_OFFSET (0) + #define RTL8373_SYNCE_DUMMY2_SYNCE_DUMMY2_MASK (0xFFFFFFFF << RTL8373_SYNCE_DUMMY2_SYNCE_DUMMY2_OFFSET) + +#define RTL8373_SYNCE_DUMMY3_ADDR (0xBB8) + #define RTL8373_SYNCE_DUMMY3_SYNCE_DUMMY3_OFFSET (0) + #define RTL8373_SYNCE_DUMMY3_SYNCE_DUMMY3_MASK (0xFFFFFFFF << RTL8373_SYNCE_DUMMY3_SYNCE_DUMMY3_OFFSET) + +#define RTL8373_SYNCE_DUMMY4_ADDR (0xBBC) + #define RTL8373_SYNCE_DUMMY4_SYNCE_DUMMY4_OFFSET (0) + #define RTL8373_SYNCE_DUMMY4_SYNCE_DUMMY4_MASK (0xFFFFFFFF << RTL8373_SYNCE_DUMMY4_SYNCE_DUMMY4_OFFSET) + +#define RTL8373_SYNCE_DUMMY5_ADDR (0xBC0) + #define RTL8373_SYNCE_DUMMY5_SYNCE_DUMMY5_OFFSET (0) + #define RTL8373_SYNCE_DUMMY5_SYNCE_DUMMY5_MASK (0xFFFFFFFF << RTL8373_SYNCE_DUMMY5_SYNCE_DUMMY5_OFFSET) + +#define RTL8373_PKTGEN_GLOBAL_CTRL_ADDR (0x990) + #define RTL8373_PKTGEN_GLOBAL_CTRL_PKGN_TX_DONE_OFFSET (12) + #define RTL8373_PKTGEN_GLOBAL_CTRL_PKGN_TX_DONE_MASK (0xF << RTL8373_PKTGEN_GLOBAL_CTRL_PKGN_TX_DONE_OFFSET) + #define RTL8373_PKTGEN_GLOBAL_CTRL_PKG3_TX_SEL_OFFSET (10) + #define RTL8373_PKTGEN_GLOBAL_CTRL_PKG3_TX_SEL_MASK (0x3 << RTL8373_PKTGEN_GLOBAL_CTRL_PKG3_TX_SEL_OFFSET) + #define RTL8373_PKTGEN_GLOBAL_CTRL_PKG2_TX_SEL_OFFSET (8) + #define RTL8373_PKTGEN_GLOBAL_CTRL_PKG2_TX_SEL_MASK (0x3 << RTL8373_PKTGEN_GLOBAL_CTRL_PKG2_TX_SEL_OFFSET) + #define RTL8373_PKTGEN_GLOBAL_CTRL_PKG1_TX_SEL_OFFSET (6) + #define RTL8373_PKTGEN_GLOBAL_CTRL_PKG1_TX_SEL_MASK (0x3 << RTL8373_PKTGEN_GLOBAL_CTRL_PKG1_TX_SEL_OFFSET) + #define RTL8373_PKTGEN_GLOBAL_CTRL_PKG0_TX_SEL_OFFSET (4) + #define RTL8373_PKTGEN_GLOBAL_CTRL_PKG0_TX_SEL_MASK (0x3 << RTL8373_PKTGEN_GLOBAL_CTRL_PKG0_TX_SEL_OFFSET) + #define RTL8373_PKTGEN_GLOBAL_CTRL_PKGN_TX_CMD_OFFSET (0) + #define RTL8373_PKTGEN_GLOBAL_CTRL_PKGN_TX_CMD_MASK (0xF << RTL8373_PKTGEN_GLOBAL_CTRL_PKGN_TX_CMD_OFFSET) + +#define RTL8373_PKTGEN_PAYLOAD_IND_ACCESS_CTRL_ADDR (0x994) + #define RTL8373_PKTGEN_PAYLOAD_IND_ACCESS_CTRL_SRAM_ACCCESS_CMD_OFFSET (31) + #define RTL8373_PKTGEN_PAYLOAD_IND_ACCESS_CTRL_SRAM_ACCCESS_CMD_MASK (0x1 << RTL8373_PKTGEN_PAYLOAD_IND_ACCESS_CTRL_SRAM_ACCCESS_CMD_OFFSET) + #define RTL8373_PKTGEN_PAYLOAD_IND_ACCESS_CTRL_SRAM_ADDRESS_OFFSET (16) + #define RTL8373_PKTGEN_PAYLOAD_IND_ACCESS_CTRL_SRAM_ADDRESS_MASK (0xFF << RTL8373_PKTGEN_PAYLOAD_IND_ACCESS_CTRL_SRAM_ADDRESS_OFFSET) + #define RTL8373_PKTGEN_PAYLOAD_IND_ACCESS_CTRL_STREAM_PAYLOAD_ACCCESS_TRIGGER_OFFSET (15) + #define RTL8373_PKTGEN_PAYLOAD_IND_ACCESS_CTRL_STREAM_PAYLOAD_ACCCESS_TRIGGER_MASK (0x1 << RTL8373_PKTGEN_PAYLOAD_IND_ACCESS_CTRL_STREAM_PAYLOAD_ACCCESS_TRIGGER_OFFSET) + #define RTL8373_PKTGEN_PAYLOAD_IND_ACCESS_CTRL_STREAM_PAYLOAD_SRAM_DATA_OFFSET (0) + #define RTL8373_PKTGEN_PAYLOAD_IND_ACCESS_CTRL_STREAM_PAYLOAD_SRAM_DATA_MASK (0xFF << RTL8373_PKTGEN_PAYLOAD_IND_ACCESS_CTRL_STREAM_PAYLOAD_SRAM_DATA_OFFSET) + +#define RTL8373_PKTGEN_G2XG_FIFO_CTRL_ADDR (0x998) + #define RTL8373_PKTGEN_G2XG_FIFO_CTRL_PKTGEN_DUMMY0_OFFSET (16) + #define RTL8373_PKTGEN_G2XG_FIFO_CTRL_PKTGEN_DUMMY0_MASK (0xFFFF << RTL8373_PKTGEN_G2XG_FIFO_CTRL_PKTGEN_DUMMY0_OFFSET) + #define RTL8373_PKTGEN_G2XG_FIFO_CTRL_PKG3_TX_CLK_SEL_OFFSET (15) + #define RTL8373_PKTGEN_G2XG_FIFO_CTRL_PKG3_TX_CLK_SEL_MASK (0x1 << RTL8373_PKTGEN_G2XG_FIFO_CTRL_PKG3_TX_CLK_SEL_OFFSET) + #define RTL8373_PKTGEN_G2XG_FIFO_CTRL_PKG2_TX_CLK_SEL_OFFSET (14) + #define RTL8373_PKTGEN_G2XG_FIFO_CTRL_PKG2_TX_CLK_SEL_MASK (0x1 << RTL8373_PKTGEN_G2XG_FIFO_CTRL_PKG2_TX_CLK_SEL_OFFSET) + #define RTL8373_PKTGEN_G2XG_FIFO_CTRL_PKG1_TX_CLK_SEL_OFFSET (13) + #define RTL8373_PKTGEN_G2XG_FIFO_CTRL_PKG1_TX_CLK_SEL_MASK (0x1 << RTL8373_PKTGEN_G2XG_FIFO_CTRL_PKG1_TX_CLK_SEL_OFFSET) + #define RTL8373_PKTGEN_G2XG_FIFO_CTRL_PKG0_TX_CLK_SEL_OFFSET (12) + #define RTL8373_PKTGEN_G2XG_FIFO_CTRL_PKG0_TX_CLK_SEL_MASK (0x1 << RTL8373_PKTGEN_G2XG_FIFO_CTRL_PKG0_TX_CLK_SEL_OFFSET) + #define RTL8373_PKTGEN_G2XG_FIFO_CTRL_PKG_G2XG_GTX_MIN_IPG_OFFSET (6) + #define RTL8373_PKTGEN_G2XG_FIFO_CTRL_PKG_G2XG_GTX_MIN_IPG_MASK (0xF << RTL8373_PKTGEN_G2XG_FIFO_CTRL_PKG_G2XG_GTX_MIN_IPG_OFFSET) + #define RTL8373_PKTGEN_G2XG_FIFO_CTRL_PKG_G2XG_TX_RDFIFO_THR_OFFSET (0) + #define RTL8373_PKTGEN_G2XG_FIFO_CTRL_PKG_G2XG_TX_RDFIFO_THR_MASK (0x3F << RTL8373_PKTGEN_G2XG_FIFO_CTRL_PKG_G2XG_TX_RDFIFO_THR_OFFSET) + +#define RTL8373_PKTGEN0_CTRL0_ADDR (0x99C) + #define RTL8373_PKTGEN0_CTRL0_IBG_LEN_OFFSET (0) + #define RTL8373_PKTGEN0_CTRL0_IBG_LEN_MASK (0xFFFFFFFF << RTL8373_PKTGEN0_CTRL0_IBG_LEN_OFFSET) + +#define RTL8373_PKTGEN0_CTRL1_ADDR (0x9A0) + #define RTL8373_PKTGEN0_CTRL1_BURST_CNT_OFFSET (0) + #define RTL8373_PKTGEN0_CTRL1_BURST_CNT_MASK (0xFFFFFFFF << RTL8373_PKTGEN0_CTRL1_BURST_CNT_OFFSET) + +#define RTL8373_PKTGEN0_CTRL2_ADDR (0x9A4) + #define RTL8373_PKTGEN0_CTRL2_BURST_SIZE_OFFSET (0) + #define RTL8373_PKTGEN0_CTRL2_BURST_SIZE_MASK (0xFFFF << RTL8373_PKTGEN0_CTRL2_BURST_SIZE_OFFSET) + +#define RTL8373_PKTGEN0_CTRL3_ADDR (0x9A8) + #define RTL8373_PKTGEN0_CTRL3_STREAM_LEN_MOD_OFFSET (30) + #define RTL8373_PKTGEN0_CTRL3_STREAM_LEN_MOD_MASK (0x3 << RTL8373_PKTGEN0_CTRL3_STREAM_LEN_MOD_OFFSET) + #define RTL8373_PKTGEN0_CTRL3_STREAM_LEN_RNG_START_OFFSET (16) + #define RTL8373_PKTGEN0_CTRL3_STREAM_LEN_RNG_START_MASK (0x3FFF << RTL8373_PKTGEN0_CTRL3_STREAM_LEN_RNG_START_OFFSET) + #define RTL8373_PKTGEN0_CTRL3_STREAM_ETHERTYPE_MOD_OFFSET (14) + #define RTL8373_PKTGEN0_CTRL3_STREAM_ETHERTYPE_MOD_MASK (0x1 << RTL8373_PKTGEN0_CTRL3_STREAM_ETHERTYPE_MOD_OFFSET) + #define RTL8373_PKTGEN0_CTRL3_STREAM_LEN_RNG_END_OFFSET (0) + #define RTL8373_PKTGEN0_CTRL3_STREAM_LEN_RNG_END_MASK (0x3FFF << RTL8373_PKTGEN0_CTRL3_STREAM_LEN_RNG_END_OFFSET) + +#define RTL8373_PKTGEN0_CTRL4_ADDR (0x9AC) + #define RTL8373_PKTGEN0_CTRL4_STREAM_ETHERTYPE_OFFSET (16) + #define RTL8373_PKTGEN0_CTRL4_STREAM_ETHERTYPE_MASK (0xFFFF << RTL8373_PKTGEN0_CTRL4_STREAM_ETHERTYPE_OFFSET) + #define RTL8373_PKTGEN0_CTRL4_STREAM_PAYLOAD_MOD_OFFSET (3) + #define RTL8373_PKTGEN0_CTRL4_STREAM_PAYLOAD_MOD_MASK (0x1 << RTL8373_PKTGEN0_CTRL4_STREAM_PAYLOAD_MOD_OFFSET) + #define RTL8373_PKTGEN0_CTRL4_STREAM_PAYLOAD_MASK_OFFSET (0) + #define RTL8373_PKTGEN0_CTRL4_STREAM_PAYLOAD_MASK_MASK (0x7 << RTL8373_PKTGEN0_CTRL4_STREAM_PAYLOAD_MASK_OFFSET) + +#define RTL8373_PKTGEN0_CTRL5_ADDR (0x9B0) + #define RTL8373_PKTGEN0_CTRL5_STREAM_FIX_DMAC_L_OFFSET (0) + #define RTL8373_PKTGEN0_CTRL5_STREAM_FIX_DMAC_L_MASK (0xFFFFFFFF << RTL8373_PKTGEN0_CTRL5_STREAM_FIX_DMAC_L_OFFSET) + +#define RTL8373_PKTGEN0_CTRL6_ADDR (0x9B4) + #define RTL8373_PKTGEN0_CTRL6_STREAM_FIX_DMAC_H_OFFSET (16) + #define RTL8373_PKTGEN0_CTRL6_STREAM_FIX_DMAC_H_MASK (0xFFFF << RTL8373_PKTGEN0_CTRL6_STREAM_FIX_DMAC_H_OFFSET) + #define RTL8373_PKTGEN0_CTRL6_STREAM_FIX_SMAC_H_OFFSET (0) + #define RTL8373_PKTGEN0_CTRL6_STREAM_FIX_SMAC_H_MASK (0xFFFF << RTL8373_PKTGEN0_CTRL6_STREAM_FIX_SMAC_H_OFFSET) + +#define RTL8373_PKTGEN0_CTRL7_ADDR (0x9B8) + #define RTL8373_PKTGEN0_CTRL7_STREAM_FIX_SMAC_L_OFFSET (0) + #define RTL8373_PKTGEN0_CTRL7_STREAM_FIX_SMAC_L_MASK (0xFFFFFFFF << RTL8373_PKTGEN0_CTRL7_STREAM_FIX_SMAC_L_OFFSET) + +#define RTL8373_PKTGEN1_CTRL0_ADDR (0x9BC) + #define RTL8373_PKTGEN1_CTRL0_IBG_LEN_OFFSET (0) + #define RTL8373_PKTGEN1_CTRL0_IBG_LEN_MASK (0xFFFFFFFF << RTL8373_PKTGEN1_CTRL0_IBG_LEN_OFFSET) + +#define RTL8373_PKTGEN1_CTRL1_ADDR (0x9C0) + #define RTL8373_PKTGEN1_CTRL1_BURST_CNT_OFFSET (0) + #define RTL8373_PKTGEN1_CTRL1_BURST_CNT_MASK (0xFFFFFFFF << RTL8373_PKTGEN1_CTRL1_BURST_CNT_OFFSET) + +#define RTL8373_PKTGEN1_CTRL2_ADDR (0x9C4) + #define RTL8373_PKTGEN1_CTRL2_BURST_SIZE_OFFSET (0) + #define RTL8373_PKTGEN1_CTRL2_BURST_SIZE_MASK (0xFFFF << RTL8373_PKTGEN1_CTRL2_BURST_SIZE_OFFSET) + +#define RTL8373_PKTGEN1_CTRL3_ADDR (0x9C8) + #define RTL8373_PKTGEN1_CTRL3_STREAM_LEN_MOD_OFFSET (30) + #define RTL8373_PKTGEN1_CTRL3_STREAM_LEN_MOD_MASK (0x3 << RTL8373_PKTGEN1_CTRL3_STREAM_LEN_MOD_OFFSET) + #define RTL8373_PKTGEN1_CTRL3_STREAM_LEN_RNG_START_OFFSET (16) + #define RTL8373_PKTGEN1_CTRL3_STREAM_LEN_RNG_START_MASK (0x3FFF << RTL8373_PKTGEN1_CTRL3_STREAM_LEN_RNG_START_OFFSET) + #define RTL8373_PKTGEN1_CTRL3_STREAM_ETHERTYPE_MOD_OFFSET (14) + #define RTL8373_PKTGEN1_CTRL3_STREAM_ETHERTYPE_MOD_MASK (0x1 << RTL8373_PKTGEN1_CTRL3_STREAM_ETHERTYPE_MOD_OFFSET) + #define RTL8373_PKTGEN1_CTRL3_STREAM_LEN_RNG_END_OFFSET (0) + #define RTL8373_PKTGEN1_CTRL3_STREAM_LEN_RNG_END_MASK (0x3FFF << RTL8373_PKTGEN1_CTRL3_STREAM_LEN_RNG_END_OFFSET) + +#define RTL8373_PKTGEN1_CTRL4_ADDR (0x9CC) + #define RTL8373_PKTGEN1_CTRL4_STREAM_ETHERTYPE_OFFSET (16) + #define RTL8373_PKTGEN1_CTRL4_STREAM_ETHERTYPE_MASK (0xFFFF << RTL8373_PKTGEN1_CTRL4_STREAM_ETHERTYPE_OFFSET) + #define RTL8373_PKTGEN1_CTRL4_STREAM_PAYLOAD_MOD_OFFSET (3) + #define RTL8373_PKTGEN1_CTRL4_STREAM_PAYLOAD_MOD_MASK (0x1 << RTL8373_PKTGEN1_CTRL4_STREAM_PAYLOAD_MOD_OFFSET) + #define RTL8373_PKTGEN1_CTRL4_STREAM_PAYLOAD_MASK_OFFSET (0) + #define RTL8373_PKTGEN1_CTRL4_STREAM_PAYLOAD_MASK_MASK (0x7 << RTL8373_PKTGEN1_CTRL4_STREAM_PAYLOAD_MASK_OFFSET) + +#define RTL8373_PKTGEN1_CTRL5_ADDR (0x9D0) + #define RTL8373_PKTGEN1_CTRL5_STREAM_FIX_DMAC_L_OFFSET (0) + #define RTL8373_PKTGEN1_CTRL5_STREAM_FIX_DMAC_L_MASK (0xFFFFFFFF << RTL8373_PKTGEN1_CTRL5_STREAM_FIX_DMAC_L_OFFSET) + +#define RTL8373_PKTGEN1_CTRL6_ADDR (0x9D4) + #define RTL8373_PKTGEN1_CTRL6_STREAM_FIX_DMAC_H_OFFSET (16) + #define RTL8373_PKTGEN1_CTRL6_STREAM_FIX_DMAC_H_MASK (0xFFFF << RTL8373_PKTGEN1_CTRL6_STREAM_FIX_DMAC_H_OFFSET) + #define RTL8373_PKTGEN1_CTRL6_STREAM_FIX_SMAC_H_OFFSET (0) + #define RTL8373_PKTGEN1_CTRL6_STREAM_FIX_SMAC_H_MASK (0xFFFF << RTL8373_PKTGEN1_CTRL6_STREAM_FIX_SMAC_H_OFFSET) + +#define RTL8373_PKTGEN1_CTRL7_ADDR (0x9D8) + #define RTL8373_PKTGEN1_CTRL7_STREAM_FIX_SMAC_L_OFFSET (0) + #define RTL8373_PKTGEN1_CTRL7_STREAM_FIX_SMAC_L_MASK (0xFFFFFFFF << RTL8373_PKTGEN1_CTRL7_STREAM_FIX_SMAC_L_OFFSET) + +#define RTL8373_PKTGEN2_CTRL0_ADDR (0x9DC) + #define RTL8373_PKTGEN2_CTRL0_IBG_LEN_OFFSET (0) + #define RTL8373_PKTGEN2_CTRL0_IBG_LEN_MASK (0xFFFFFFFF << RTL8373_PKTGEN2_CTRL0_IBG_LEN_OFFSET) + +#define RTL8373_PKTGEN2_CTRL1_ADDR (0x9E0) + #define RTL8373_PKTGEN2_CTRL1_BURST_CNT_OFFSET (0) + #define RTL8373_PKTGEN2_CTRL1_BURST_CNT_MASK (0xFFFFFFFF << RTL8373_PKTGEN2_CTRL1_BURST_CNT_OFFSET) + +#define RTL8373_PKTGEN2_CTRL2_ADDR (0x9E4) + #define RTL8373_PKTGEN2_CTRL2_BURST_SIZE_OFFSET (0) + #define RTL8373_PKTGEN2_CTRL2_BURST_SIZE_MASK (0xFFFF << RTL8373_PKTGEN2_CTRL2_BURST_SIZE_OFFSET) + +#define RTL8373_PKTGEN2_CTRL3_ADDR (0x9E8) + #define RTL8373_PKTGEN2_CTRL3_STREAM_LEN_MOD_OFFSET (30) + #define RTL8373_PKTGEN2_CTRL3_STREAM_LEN_MOD_MASK (0x3 << RTL8373_PKTGEN2_CTRL3_STREAM_LEN_MOD_OFFSET) + #define RTL8373_PKTGEN2_CTRL3_STREAM_LEN_RNG_START_OFFSET (16) + #define RTL8373_PKTGEN2_CTRL3_STREAM_LEN_RNG_START_MASK (0x3FFF << RTL8373_PKTGEN2_CTRL3_STREAM_LEN_RNG_START_OFFSET) + #define RTL8373_PKTGEN2_CTRL3_STREAM_ETHERTYPE_MOD_OFFSET (14) + #define RTL8373_PKTGEN2_CTRL3_STREAM_ETHERTYPE_MOD_MASK (0x1 << RTL8373_PKTGEN2_CTRL3_STREAM_ETHERTYPE_MOD_OFFSET) + #define RTL8373_PKTGEN2_CTRL3_STREAM_LEN_RNG_END_OFFSET (0) + #define RTL8373_PKTGEN2_CTRL3_STREAM_LEN_RNG_END_MASK (0x3FFF << RTL8373_PKTGEN2_CTRL3_STREAM_LEN_RNG_END_OFFSET) + +#define RTL8373_PKTGEN2_CTRL4_ADDR (0x9EC) + #define RTL8373_PKTGEN2_CTRL4_STREAM_ETHERTYPE_OFFSET (16) + #define RTL8373_PKTGEN2_CTRL4_STREAM_ETHERTYPE_MASK (0xFFFF << RTL8373_PKTGEN2_CTRL4_STREAM_ETHERTYPE_OFFSET) + #define RTL8373_PKTGEN2_CTRL4_STREAM_PAYLOAD_MOD_OFFSET (3) + #define RTL8373_PKTGEN2_CTRL4_STREAM_PAYLOAD_MOD_MASK (0x1 << RTL8373_PKTGEN2_CTRL4_STREAM_PAYLOAD_MOD_OFFSET) + #define RTL8373_PKTGEN2_CTRL4_STREAM_PAYLOAD_MASK_OFFSET (0) + #define RTL8373_PKTGEN2_CTRL4_STREAM_PAYLOAD_MASK_MASK (0x7 << RTL8373_PKTGEN2_CTRL4_STREAM_PAYLOAD_MASK_OFFSET) + +#define RTL8373_PKTGEN2_CTRL5_ADDR (0x9F0) + #define RTL8373_PKTGEN2_CTRL5_STREAM_FIX_DMAC_L_OFFSET (0) + #define RTL8373_PKTGEN2_CTRL5_STREAM_FIX_DMAC_L_MASK (0xFFFFFFFF << RTL8373_PKTGEN2_CTRL5_STREAM_FIX_DMAC_L_OFFSET) + +#define RTL8373_PKTGEN2_CTRL6_ADDR (0x9F4) + #define RTL8373_PKTGEN2_CTRL6_STREAM_FIX_DMAC_H_OFFSET (16) + #define RTL8373_PKTGEN2_CTRL6_STREAM_FIX_DMAC_H_MASK (0xFFFF << RTL8373_PKTGEN2_CTRL6_STREAM_FIX_DMAC_H_OFFSET) + #define RTL8373_PKTGEN2_CTRL6_STREAM_FIX_SMAC_H_OFFSET (0) + #define RTL8373_PKTGEN2_CTRL6_STREAM_FIX_SMAC_H_MASK (0xFFFF << RTL8373_PKTGEN2_CTRL6_STREAM_FIX_SMAC_H_OFFSET) + +#define RTL8373_PKTGEN2_CTRL7_ADDR (0x9F8) + #define RTL8373_PKTGEN2_CTRL7_STREAM_FIX_SMAC_L_OFFSET (0) + #define RTL8373_PKTGEN2_CTRL7_STREAM_FIX_SMAC_L_MASK (0xFFFFFFFF << RTL8373_PKTGEN2_CTRL7_STREAM_FIX_SMAC_L_OFFSET) + +#define RTL8373_PKTGEN3_CTRL0_ADDR (0x9FC) + #define RTL8373_PKTGEN3_CTRL0_IBG_LEN_OFFSET (0) + #define RTL8373_PKTGEN3_CTRL0_IBG_LEN_MASK (0xFFFFFFFF << RTL8373_PKTGEN3_CTRL0_IBG_LEN_OFFSET) + +#define RTL8373_PKTGEN3_CTRL1_ADDR (0xA00) + #define RTL8373_PKTGEN3_CTRL1_BURST_CNT_OFFSET (0) + #define RTL8373_PKTGEN3_CTRL1_BURST_CNT_MASK (0xFFFFFFFF << RTL8373_PKTGEN3_CTRL1_BURST_CNT_OFFSET) + +#define RTL8373_PKTGEN3_CTRL2_ADDR (0xA04) + #define RTL8373_PKTGEN3_CTRL2_BURST_SIZE_OFFSET (0) + #define RTL8373_PKTGEN3_CTRL2_BURST_SIZE_MASK (0xFFFF << RTL8373_PKTGEN3_CTRL2_BURST_SIZE_OFFSET) + +#define RTL8373_PKTGEN3_CTRL3_ADDR (0xA08) + #define RTL8373_PKTGEN3_CTRL3_STREAM_LEN_MOD_OFFSET (30) + #define RTL8373_PKTGEN3_CTRL3_STREAM_LEN_MOD_MASK (0x3 << RTL8373_PKTGEN3_CTRL3_STREAM_LEN_MOD_OFFSET) + #define RTL8373_PKTGEN3_CTRL3_STREAM_LEN_RNG_START_OFFSET (16) + #define RTL8373_PKTGEN3_CTRL3_STREAM_LEN_RNG_START_MASK (0x3FFF << RTL8373_PKTGEN3_CTRL3_STREAM_LEN_RNG_START_OFFSET) + #define RTL8373_PKTGEN3_CTRL3_STREAM_ETHERTYPE_MOD_OFFSET (14) + #define RTL8373_PKTGEN3_CTRL3_STREAM_ETHERTYPE_MOD_MASK (0x1 << RTL8373_PKTGEN3_CTRL3_STREAM_ETHERTYPE_MOD_OFFSET) + #define RTL8373_PKTGEN3_CTRL3_STREAM_LEN_RNG_END_OFFSET (0) + #define RTL8373_PKTGEN3_CTRL3_STREAM_LEN_RNG_END_MASK (0x3FFF << RTL8373_PKTGEN3_CTRL3_STREAM_LEN_RNG_END_OFFSET) + +#define RTL8373_PKTGEN3_CTRL4_ADDR (0xA0C) + #define RTL8373_PKTGEN3_CTRL4_STREAM_ETHERTYPE_OFFSET (16) + #define RTL8373_PKTGEN3_CTRL4_STREAM_ETHERTYPE_MASK (0xFFFF << RTL8373_PKTGEN3_CTRL4_STREAM_ETHERTYPE_OFFSET) + #define RTL8373_PKTGEN3_CTRL4_STREAM_PAYLOAD_MOD_OFFSET (3) + #define RTL8373_PKTGEN3_CTRL4_STREAM_PAYLOAD_MOD_MASK (0x1 << RTL8373_PKTGEN3_CTRL4_STREAM_PAYLOAD_MOD_OFFSET) + #define RTL8373_PKTGEN3_CTRL4_STREAM_PAYLOAD_MASK_OFFSET (0) + #define RTL8373_PKTGEN3_CTRL4_STREAM_PAYLOAD_MASK_MASK (0x7 << RTL8373_PKTGEN3_CTRL4_STREAM_PAYLOAD_MASK_OFFSET) + +#define RTL8373_PKTGEN3_CTRL5_ADDR (0xA10) + #define RTL8373_PKTGEN3_CTRL5_STREAM_FIX_DMAC_L_OFFSET (0) + #define RTL8373_PKTGEN3_CTRL5_STREAM_FIX_DMAC_L_MASK (0xFFFFFFFF << RTL8373_PKTGEN3_CTRL5_STREAM_FIX_DMAC_L_OFFSET) + +#define RTL8373_PKTGEN3_CTRL6_ADDR (0xA14) + #define RTL8373_PKTGEN3_CTRL6_STREAM_FIX_DMAC_H_OFFSET (16) + #define RTL8373_PKTGEN3_CTRL6_STREAM_FIX_DMAC_H_MASK (0xFFFF << RTL8373_PKTGEN3_CTRL6_STREAM_FIX_DMAC_H_OFFSET) + #define RTL8373_PKTGEN3_CTRL6_STREAM_FIX_SMAC_H_OFFSET (0) + #define RTL8373_PKTGEN3_CTRL6_STREAM_FIX_SMAC_H_MASK (0xFFFF << RTL8373_PKTGEN3_CTRL6_STREAM_FIX_SMAC_H_OFFSET) + +#define RTL8373_PKTGEN3_CTRL7_ADDR (0xA18) + #define RTL8373_PKTGEN3_CTRL7_STREAM_FIX_SMAC_L_OFFSET (0) + #define RTL8373_PKTGEN3_CTRL7_STREAM_FIX_SMAC_L_MASK (0xFFFFFFFF << RTL8373_PKTGEN3_CTRL7_STREAM_FIX_SMAC_L_OFFSET) + +#define RTL8373_PKTGEN0_CTRL15_ADDR (0xA1C) + #define RTL8373_PKTGEN0_CTRL15_BURST_CNT_DBG_OFFSET (0) + #define RTL8373_PKTGEN0_CTRL15_BURST_CNT_DBG_MASK (0xFFFFFFFF << RTL8373_PKTGEN0_CTRL15_BURST_CNT_DBG_OFFSET) + +#define RTL8373_PKTGEN1_CTRL15_ADDR (0xA20) + #define RTL8373_PKTGEN1_CTRL15_BURST_CNT_DBG_OFFSET (0) + #define RTL8373_PKTGEN1_CTRL15_BURST_CNT_DBG_MASK (0xFFFFFFFF << RTL8373_PKTGEN1_CTRL15_BURST_CNT_DBG_OFFSET) + +#define RTL8373_PKTGEN2_CTRL15_ADDR (0xA24) + #define RTL8373_PKTGEN2_CTRL15_BURST_CNT_DBG_OFFSET (0) + #define RTL8373_PKTGEN2_CTRL15_BURST_CNT_DBG_MASK (0xFFFFFFFF << RTL8373_PKTGEN2_CTRL15_BURST_CNT_DBG_OFFSET) + +#define RTL8373_PKTGEN3_CTRL15_ADDR (0xA28) + #define RTL8373_PKTGEN3_CTRL15_BURST_CNT_DBG_OFFSET (0) + #define RTL8373_PKTGEN3_CTRL15_BURST_CNT_DBG_MASK (0xFFFFFFFF << RTL8373_PKTGEN3_CTRL15_BURST_CNT_DBG_OFFSET) + +#define RTL8373_PHY_MODEL_ID_REV_CTRL_ADDR (0xBC4) + #define RTL8373_PHY_MODEL_ID_REV_CTRL_CFG_PHY_OUI_BIT19_BIT24_OFFSET (26) + #define RTL8373_PHY_MODEL_ID_REV_CTRL_CFG_PHY_OUI_BIT19_BIT24_MASK (0x3F << RTL8373_PHY_MODEL_ID_REV_CTRL_CFG_PHY_OUI_BIT19_BIT24_OFFSET) + #define RTL8373_PHY_MODEL_ID_REV_CTRL_CFG_PHY_MODEL_NO_OFFSET (20) + #define RTL8373_PHY_MODEL_ID_REV_CTRL_CFG_PHY_MODEL_NO_MASK (0x3F << RTL8373_PHY_MODEL_ID_REV_CTRL_CFG_PHY_MODEL_NO_OFFSET) + #define RTL8373_PHY_MODEL_ID_REV_CTRL_CFG_PHY_REVISION_NUM_OFFSET (16) + #define RTL8373_PHY_MODEL_ID_REV_CTRL_CFG_PHY_REVISION_NUM_MASK (0xF << RTL8373_PHY_MODEL_ID_REV_CTRL_CFG_PHY_REVISION_NUM_OFFSET) + #define RTL8373_PHY_MODEL_ID_REV_CTRL_CFG_PHY_OUI_BIT3_BIT18_OFFSET (0) + #define RTL8373_PHY_MODEL_ID_REV_CTRL_CFG_PHY_OUI_BIT3_BIT18_MASK (0xFFFF << RTL8373_PHY_MODEL_ID_REV_CTRL_CFG_PHY_OUI_BIT3_BIT18_OFFSET) + +/* + * Feature: SDS + */ +#define RTL8373_SDS_MODE_SEL_ADDR (0x7B20) + #define RTL8373_SDS_MODE_SEL_CFG_MAC8_8221B_OFFSET (22) + #define RTL8373_SDS_MODE_SEL_CFG_MAC8_8221B_MASK (0x1 << RTL8373_SDS_MODE_SEL_CFG_MAC8_8221B_OFFSET) + #define RTL8373_SDS_MODE_SEL_CFG_MAC3_8221B_OFFSET (21) + #define RTL8373_SDS_MODE_SEL_CFG_MAC3_8221B_MASK (0x1 << RTL8373_SDS_MODE_SEL_CFG_MAC3_8221B_OFFSET) + #define RTL8373_SDS_MODE_SEL_SDS1_USX_SUB_MODE_OFFSET (16) + #define RTL8373_SDS_MODE_SEL_SDS1_USX_SUB_MODE_MASK (0x1F << RTL8373_SDS_MODE_SEL_SDS1_USX_SUB_MODE_OFFSET) + #define RTL8373_SDS_MODE_SEL_SDS0_USX_SUB_MODE_OFFSET (10) + #define RTL8373_SDS_MODE_SEL_SDS0_USX_SUB_MODE_MASK (0x1F << RTL8373_SDS_MODE_SEL_SDS0_USX_SUB_MODE_OFFSET) + #define RTL8373_SDS_MODE_SEL_SDS1_MODE_SEL_OFFSET (5) + #define RTL8373_SDS_MODE_SEL_SDS1_MODE_SEL_MASK (0x1F << RTL8373_SDS_MODE_SEL_SDS1_MODE_SEL_OFFSET) + #define RTL8373_SDS_MODE_SEL_SDS0_MODE_SEL_OFFSET (0) + #define RTL8373_SDS_MODE_SEL_SDS0_MODE_SEL_MASK (0x1F << RTL8373_SDS_MODE_SEL_SDS0_MODE_SEL_OFFSET) + +#define RTL8373_SDS_INDACS_CMD_ADDR (0x3F8) + #define RTL8373_SDS_INDACS_CMD_SDS_CMD_OFFSET (15) + #define RTL8373_SDS_INDACS_CMD_SDS_CMD_MASK (0x1 << RTL8373_SDS_INDACS_CMD_SDS_CMD_OFFSET) + #define RTL8373_SDS_INDACS_CMD_SDS_RWOP_OFFSET (14) + #define RTL8373_SDS_INDACS_CMD_SDS_RWOP_MASK (0x1 << RTL8373_SDS_INDACS_CMD_SDS_RWOP_OFFSET) + #define RTL8373_SDS_INDACS_CMD_SDS_REGAD_OFFSET (7) + #define RTL8373_SDS_INDACS_CMD_SDS_REGAD_MASK (0x1F << RTL8373_SDS_INDACS_CMD_SDS_REGAD_OFFSET) + #define RTL8373_SDS_INDACS_CMD_SDS_PAGE_OFFSET (1) + #define RTL8373_SDS_INDACS_CMD_SDS_PAGE_MASK (0x3F << RTL8373_SDS_INDACS_CMD_SDS_PAGE_OFFSET) + #define RTL8373_SDS_INDACS_CMD_SDS_INDEX_OFFSET (0) + #define RTL8373_SDS_INDACS_CMD_SDS_INDEX_MASK (0x1 << RTL8373_SDS_INDACS_CMD_SDS_INDEX_OFFSET) + +#define RTL8373_SDS_INDACS_RD_ADDR (0x3FC) + #define RTL8373_SDS_INDACS_RD_SDS_RD_OFFSET (0) + #define RTL8373_SDS_INDACS_RD_SDS_RD_MASK (0xFFFF << RTL8373_SDS_INDACS_RD_SDS_RD_OFFSET) + +#define RTL8373_SDS_INDACS_WD_ADDR (0x400) + #define RTL8373_SDS_INDACS_WD_SDS_WD_OFFSET (0) + #define RTL8373_SDS_INDACS_WD_SDS_WD_MASK (0xFFFF << RTL8373_SDS_INDACS_WD_SDS_WD_OFFSET) + +#define RTL8373_SDS0_STATUS_ADDR (0x7B24) + #define RTL8373_SDS0_STATUS_LINK_FAULT_SDS1_TGXR0_CH0_OFFSET (12) + #define RTL8373_SDS0_STATUS_LINK_FAULT_SDS1_TGXR0_CH0_MASK (0x7 << RTL8373_SDS0_STATUS_LINK_FAULT_SDS1_TGXR0_CH0_OFFSET) + #define RTL8373_SDS0_STATUS_LINK_FAULT_SDS0_TGXR0_CH3_OFFSET (9) + #define RTL8373_SDS0_STATUS_LINK_FAULT_SDS0_TGXR0_CH3_MASK (0x7 << RTL8373_SDS0_STATUS_LINK_FAULT_SDS0_TGXR0_CH3_OFFSET) + #define RTL8373_SDS0_STATUS_LINK_FAULT_SDS0_TGXR0_CH2_OFFSET (6) + #define RTL8373_SDS0_STATUS_LINK_FAULT_SDS0_TGXR0_CH2_MASK (0x7 << RTL8373_SDS0_STATUS_LINK_FAULT_SDS0_TGXR0_CH2_OFFSET) + #define RTL8373_SDS0_STATUS_LINK_FAULT_SDS0_TGXR0_CH1_OFFSET (3) + #define RTL8373_SDS0_STATUS_LINK_FAULT_SDS0_TGXR0_CH1_MASK (0x7 << RTL8373_SDS0_STATUS_LINK_FAULT_SDS0_TGXR0_CH1_OFFSET) + #define RTL8373_SDS0_STATUS_LINK_FAULT_SDS0_TGXR0_CH0_OFFSET (0) + #define RTL8373_SDS0_STATUS_LINK_FAULT_SDS0_TGXR0_CH0_MASK (0x7 << RTL8373_SDS0_STATUS_LINK_FAULT_SDS0_TGXR0_CH0_OFFSET) + +#define RTL8373_SDS0_CH0_RO_ABLTY_ADDR (0x7B28) + #define RTL8373_SDS0_CH0_RO_ABLTY_SDS0_CH0_RO_ABLTY_OFFSET (0) + #define RTL8373_SDS0_CH0_RO_ABLTY_SDS0_CH0_RO_ABLTY_MASK (0x1FFFF << RTL8373_SDS0_CH0_RO_ABLTY_SDS0_CH0_RO_ABLTY_OFFSET) + +#define RTL8373_SDS0_CH1_RO_ABLTY_ADDR (0x7B2C) + #define RTL8373_SDS0_CH1_RO_ABLTY_SDS0_CH1_RO_ABLTY_OFFSET (0) + #define RTL8373_SDS0_CH1_RO_ABLTY_SDS0_CH1_RO_ABLTY_MASK (0x1FFFF << RTL8373_SDS0_CH1_RO_ABLTY_SDS0_CH1_RO_ABLTY_OFFSET) + +#define RTL8373_SDS0_CH2_RO_ABLTY_ADDR (0x7B30) + #define RTL8373_SDS0_CH2_RO_ABLTY_SDS0_CH2_RO_ABLTY_OFFSET (0) + #define RTL8373_SDS0_CH2_RO_ABLTY_SDS0_CH2_RO_ABLTY_MASK (0x1FFFF << RTL8373_SDS0_CH2_RO_ABLTY_SDS0_CH2_RO_ABLTY_OFFSET) + +#define RTL8373_SDS0_CH3_3_RO_ABLTY_ADDR (0x7B34) + #define RTL8373_SDS0_CH3_3_RO_ABLTY_SDS0_CH3_RO_ABLTY_OFFSET (0) + #define RTL8373_SDS0_CH3_3_RO_ABLTY_SDS0_CH3_RO_ABLTY_MASK (0x1FFFF << RTL8373_SDS0_CH3_3_RO_ABLTY_SDS0_CH3_RO_ABLTY_OFFSET) + +#define RTL8373_SDS1_CH0_RO_ABLTY_ADDR (0x7B38) + #define RTL8373_SDS1_CH0_RO_ABLTY_SDS1_CH0_RO_ABLTY_OFFSET (0) + #define RTL8373_SDS1_CH0_RO_ABLTY_SDS1_CH0_RO_ABLTY_MASK (0x1FFFF << RTL8373_SDS1_CH0_RO_ABLTY_SDS1_CH0_RO_ABLTY_OFFSET) + +#define RTL8373_SDS0_1_MODE_RO_ADDR (0x7B3C) + #define RTL8373_SDS0_1_MODE_RO_SDS1_SUB_MODE_RO_OFFSET (21) + #define RTL8373_SDS0_1_MODE_RO_SDS1_SUB_MODE_RO_MASK (0x1F << RTL8373_SDS0_1_MODE_RO_SDS1_SUB_MODE_RO_OFFSET) + #define RTL8373_SDS0_1_MODE_RO_SDS1_MODE_RO_OFFSET (16) + #define RTL8373_SDS0_1_MODE_RO_SDS1_MODE_RO_MASK (0x1F << RTL8373_SDS0_1_MODE_RO_SDS1_MODE_RO_OFFSET) + #define RTL8373_SDS0_1_MODE_RO_SDS0_SUB_MODE_RO_OFFSET (5) + #define RTL8373_SDS0_1_MODE_RO_SDS0_SUB_MODE_RO_MASK (0x1F << RTL8373_SDS0_1_MODE_RO_SDS0_SUB_MODE_RO_OFFSET) + #define RTL8373_SDS0_1_MODE_RO_SDS0_MODE_RO_OFFSET (0) + #define RTL8373_SDS0_1_MODE_RO_SDS0_MODE_RO_MASK (0x1F << RTL8373_SDS0_1_MODE_RO_SDS0_MODE_RO_OFFSET) + +#define RTL8373_CFG_DMY_SDS_0_ADDR (0x7B40) + #define RTL8373_CFG_DMY_SDS_0_CFG_DMY_0_OFFSET (0) + #define RTL8373_CFG_DMY_SDS_0_CFG_DMY_0_MASK (0xFFFFFFFF << RTL8373_CFG_DMY_SDS_0_CFG_DMY_0_OFFSET) + +#define RTL8373_CFG_DMY_SDS_1_ADDR (0x7B44) + #define RTL8373_CFG_DMY_SDS_1_CFG_DMY_1_OFFSET (0) + #define RTL8373_CFG_DMY_SDS_1_CFG_DMY_1_MASK (0xFFFFFFFF << RTL8373_CFG_DMY_SDS_1_CFG_DMY_1_OFFSET) + +#define RTL8373_SDS_OUI_ADDR (0x7B48) + #define RTL8373_SDS_OUI_SDS_RTK_OUI_OFFSET (0) + #define RTL8373_SDS_OUI_SDS_RTK_OUI_MASK (0xFFFFFF << RTL8373_SDS_OUI_SDS_RTK_OUI_OFFSET) + +#define RTL8373_SDS_VERSION_ADDR (0x7B4C) + #define RTL8373_SDS_VERSION_SDS_MODEL_NO_OFFSET (4) + #define RTL8373_SDS_VERSION_SDS_MODEL_NO_MASK (0x3F << RTL8373_SDS_VERSION_SDS_MODEL_NO_OFFSET) + #define RTL8373_SDS_VERSION_SDS_REVISION_NO_OFFSET (0) + #define RTL8373_SDS_VERSION_SDS_REVISION_NO_MASK (0xF << RTL8373_SDS_VERSION_SDS_REVISION_NO_OFFSET) + +#define RTL8373_SDS_OUI_TGR_ADDR (0x7B50) + #define RTL8373_SDS_OUI_TGR_SDS_RTK_OUI_TGR_OFFSET (0) + #define RTL8373_SDS_OUI_TGR_SDS_RTK_OUI_TGR_MASK (0xFFFFFF << RTL8373_SDS_OUI_TGR_SDS_RTK_OUI_TGR_OFFSET) + +#define RTL8373_SDS_VERSION_TGR_ADDR (0x7B54) + #define RTL8373_SDS_VERSION_TGR_SDS_MODEL_NO_TGR_OFFSET (4) + #define RTL8373_SDS_VERSION_TGR_SDS_MODEL_NO_TGR_MASK (0x3F << RTL8373_SDS_VERSION_TGR_SDS_MODEL_NO_TGR_OFFSET) + #define RTL8373_SDS_VERSION_TGR_SDS_REVISION_NO_TGR_OFFSET (0) + #define RTL8373_SDS_VERSION_TGR_SDS_REVISION_NO_TGR_MASK (0xF << RTL8373_SDS_VERSION_TGR_SDS_REVISION_NO_TGR_OFFSET) + +#define RTL8373_SDS_INTF_CTRL1_ADDR(port) (0x7B58 + (((port) << 2))) /* port: 0-1 */ + #define RTL8373_SDS_INTF_CTRL1_SDS01_SDS_FRC_LD_OFFSET (31) + #define RTL8373_SDS_INTF_CTRL1_SDS01_SDS_FRC_LD_MASK (0x1 << RTL8373_SDS_INTF_CTRL1_SDS01_SDS_FRC_LD_OFFSET) + #define RTL8373_SDS_INTF_CTRL1_SDS01_SILENT_EN_INI_OFFSET (30) + #define RTL8373_SDS_INTF_CTRL1_SDS01_SILENT_EN_INI_MASK (0x1 << RTL8373_SDS_INTF_CTRL1_SDS01_SILENT_EN_INI_OFFSET) + #define RTL8373_SDS_INTF_CTRL1_SDS01_PDOWN_EN_INI_OFFSET (29) + #define RTL8373_SDS_INTF_CTRL1_SDS01_PDOWN_EN_INI_MASK (0x1 << RTL8373_SDS_INTF_CTRL1_SDS01_PDOWN_EN_INI_OFFSET) + #define RTL8373_SDS_INTF_CTRL1_SDS01_AUTONEG_EN_INI_OFFSET (28) + #define RTL8373_SDS_INTF_CTRL1_SDS01_AUTONEG_EN_INI_MASK (0x1 << RTL8373_SDS_INTF_CTRL1_SDS01_AUTONEG_EN_INI_OFFSET) + #define RTL8373_SDS_INTF_CTRL1_SDS01_AUTODET_EN_INI_OFFSET (27) + #define RTL8373_SDS_INTF_CTRL1_SDS01_AUTODET_EN_INI_MASK (0x1 << RTL8373_SDS_INTF_CTRL1_SDS01_AUTODET_EN_INI_OFFSET) + #define RTL8373_SDS_INTF_CTRL1_SDS01_SDS_RX_DISABLE_OFFSET (26) + #define RTL8373_SDS_INTF_CTRL1_SDS01_SDS_RX_DISABLE_MASK (0x1 << RTL8373_SDS_INTF_CTRL1_SDS01_SDS_RX_DISABLE_OFFSET) + #define RTL8373_SDS_INTF_CTRL1_SDS01_SDS_TX_DISABLE_OFFSET (25) + #define RTL8373_SDS_INTF_CTRL1_SDS01_SDS_TX_DISABLE_MASK (0x1 << RTL8373_SDS_INTF_CTRL1_SDS01_SDS_TX_DISABLE_OFFSET) + #define RTL8373_SDS_INTF_CTRL1_SDS01_FRC_REG4_FIB100_OFFSET (24) + #define RTL8373_SDS_INTF_CTRL1_SDS01_FRC_REG4_FIB100_MASK (0x1 << RTL8373_SDS_INTF_CTRL1_SDS01_FRC_REG4_FIB100_OFFSET) + #define RTL8373_SDS_INTF_CTRL1_SDS01_FRC_REG4_EN_OFFSET (23) + #define RTL8373_SDS_INTF_CTRL1_SDS01_FRC_REG4_EN_MASK (0x1 << RTL8373_SDS_INTF_CTRL1_SDS01_FRC_REG4_EN_OFFSET) + #define RTL8373_SDS_INTF_CTRL1_SDS01_CMD_STOP_GLI_CLK_OFFSET (15) + #define RTL8373_SDS_INTF_CTRL1_SDS01_CMD_STOP_GLI_CLK_MASK (0xFF << RTL8373_SDS_INTF_CTRL1_SDS01_CMD_STOP_GLI_CLK_OFFSET) + #define RTL8373_SDS_INTF_CTRL1_SDS01_STS_UPD_TX_OFFSET (7) + #define RTL8373_SDS_INTF_CTRL1_SDS01_STS_UPD_TX_MASK (0xFF << RTL8373_SDS_INTF_CTRL1_SDS01_STS_UPD_TX_OFFSET) + #define RTL8373_SDS_INTF_CTRL1_LOAD_SYS_PAR_OFFSET (6) + #define RTL8373_SDS_INTF_CTRL1_LOAD_SYS_PAR_MASK (0x1 << RTL8373_SDS_INTF_CTRL1_LOAD_SYS_PAR_OFFSET) + #define RTL8373_SDS_INTF_CTRL1_PDOWN_EN_INI_TGR_OFFSET (5) + #define RTL8373_SDS_INTF_CTRL1_PDOWN_EN_INI_TGR_MASK (0x1 << RTL8373_SDS_INTF_CTRL1_PDOWN_EN_INI_TGR_OFFSET) + #define RTL8373_SDS_INTF_CTRL1_CFG_FB_ON_OFFSET (4) + #define RTL8373_SDS_INTF_CTRL1_CFG_FB_ON_MASK (0x1 << RTL8373_SDS_INTF_CTRL1_CFG_FB_ON_OFFSET) + #define RTL8373_SDS_INTF_CTRL1_INTP_SRC_TGR0_OFFSET (3) + #define RTL8373_SDS_INTF_CTRL1_INTP_SRC_TGR0_MASK (0x1 << RTL8373_SDS_INTF_CTRL1_INTP_SRC_TGR0_OFFSET) + #define RTL8373_SDS_INTF_CTRL1_CFG_UNIDIR_EN_TGXR0_OFFSET (2) + #define RTL8373_SDS_INTF_CTRL1_CFG_UNIDIR_EN_TGXR0_MASK (0x1 << RTL8373_SDS_INTF_CTRL1_CFG_UNIDIR_EN_TGXR0_OFFSET) + #define RTL8373_SDS_INTF_CTRL1_TGR_ECC_EN_OFFSET (1) + #define RTL8373_SDS_INTF_CTRL1_TGR_ECC_EN_MASK (0x1 << RTL8373_SDS_INTF_CTRL1_TGR_ECC_EN_OFFSET) + #define RTL8373_SDS_INTF_CTRL1_SD_OFFSET (0) + #define RTL8373_SDS_INTF_CTRL1_SD_MASK (0x1 << RTL8373_SDS_INTF_CTRL1_SD_OFFSET) + +#define RTL8373_SDS_INTF_CTRL2_ADDR(port) (0x7B60 + (((port) << 2))) /* port: 0-1 */ + #define RTL8373_SDS_INTF_CTRL2_RSTR_ORI_AUTO_DET_SG_OFFSET (15) + #define RTL8373_SDS_INTF_CTRL2_RSTR_ORI_AUTO_DET_SG_MASK (0x1 << RTL8373_SDS_INTF_CTRL2_RSTR_ORI_AUTO_DET_SG_OFFSET) + #define RTL8373_SDS_INTF_CTRL2_AUTO_DET_SG3_UPD_EN_OFFSET (14) + #define RTL8373_SDS_INTF_CTRL2_AUTO_DET_SG3_UPD_EN_MASK (0x1 << RTL8373_SDS_INTF_CTRL2_AUTO_DET_SG3_UPD_EN_OFFSET) + #define RTL8373_SDS_INTF_CTRL2_AUTO_DET_SG2_UPD_EN_OFFSET (13) + #define RTL8373_SDS_INTF_CTRL2_AUTO_DET_SG2_UPD_EN_MASK (0x1 << RTL8373_SDS_INTF_CTRL2_AUTO_DET_SG2_UPD_EN_OFFSET) + #define RTL8373_SDS_INTF_CTRL2_AUTO_DET_SG1_UPD_EN_OFFSET (12) + #define RTL8373_SDS_INTF_CTRL2_AUTO_DET_SG1_UPD_EN_MASK (0x1 << RTL8373_SDS_INTF_CTRL2_AUTO_DET_SG1_UPD_EN_OFFSET) + #define RTL8373_SDS_INTF_CTRL2_AUTO_DET_SG0_UPD_EN_OFFSET (11) + #define RTL8373_SDS_INTF_CTRL2_AUTO_DET_SG0_UPD_EN_MASK (0x1 << RTL8373_SDS_INTF_CTRL2_AUTO_DET_SG0_UPD_EN_OFFSET) + #define RTL8373_SDS_INTF_CTRL2_CFG_SDSREG_BCST_ON_OFFSET (10) + #define RTL8373_SDS_INTF_CTRL2_CFG_SDSREG_BCST_ON_MASK (0x1 << RTL8373_SDS_INTF_CTRL2_CFG_SDSREG_BCST_ON_OFFSET) + #define RTL8373_SDS_INTF_CTRL2_CFG_SDS_BCST_IDX_OFFSET (5) + #define RTL8373_SDS_INTF_CTRL2_CFG_SDS_BCST_IDX_MASK (0x1F << RTL8373_SDS_INTF_CTRL2_CFG_SDS_BCST_IDX_OFFSET) + #define RTL8373_SDS_INTF_CTRL2_SDS01_LPI_GMII_SEL_OFFSET (4) + #define RTL8373_SDS_INTF_CTRL2_SDS01_LPI_GMII_SEL_MASK (0x1 << RTL8373_SDS_INTF_CTRL2_SDS01_LPI_GMII_SEL_OFFSET) + #define RTL8373_SDS_INTF_CTRL2_SDS01_SDS_PHY_MODE_OFFSET (3) + #define RTL8373_SDS_INTF_CTRL2_SDS01_SDS_PHY_MODE_MASK (0x1 << RTL8373_SDS_INTF_CTRL2_SDS01_SDS_PHY_MODE_OFFSET) + #define RTL8373_SDS_INTF_CTRL2_SDS01_UNIDIR_TX_ABLE_OFFSET (2) + #define RTL8373_SDS_INTF_CTRL2_SDS01_UNIDIR_TX_ABLE_MASK (0x1 << RTL8373_SDS_INTF_CTRL2_SDS01_UNIDIR_TX_ABLE_OFFSET) + #define RTL8373_SDS_INTF_CTRL2_SDS01_PAUSE_INI_OFFSET (0) + #define RTL8373_SDS_INTF_CTRL2_SDS01_PAUSE_INI_MASK (0x3 << RTL8373_SDS_INTF_CTRL2_SDS01_PAUSE_INI_OFFSET) + +#define RTL8373_SDS_INTF_OUT1_ADDR(port) (0x7B68 + (((port) << 2))) /* port: 0-1 */ + #define RTL8373_SDS_INTF_OUT1_SDS01_SDS_LINK_OK_SUM_OFFSET (15) + #define RTL8373_SDS_INTF_OUT1_SDS01_SDS_LINK_OK_SUM_MASK (0x1 << RTL8373_SDS_INTF_OUT1_SDS01_SDS_LINK_OK_SUM_OFFSET) + #define RTL8373_SDS_INTF_OUT1_SDS01_FIB_ISO_OFFSET (14) + #define RTL8373_SDS_INTF_OUT1_SDS01_FIB_ISO_MASK (0x1 << RTL8373_SDS_INTF_OUT1_SDS01_FIB_ISO_OFFSET) + #define RTL8373_SDS_INTF_OUT1_SDS01_FIB100_SDET_OFFSET (13) + #define RTL8373_SDS_INTF_OUT1_SDS01_FIB100_SDET_MASK (0x1 << RTL8373_SDS_INTF_OUT1_SDS01_FIB100_SDET_OFFSET) + #define RTL8373_SDS_INTF_OUT1_SDS01_FIB100_DET_OFFSET (12) + #define RTL8373_SDS_INTF_OUT1_SDS01_FIB100_DET_MASK (0x1 << RTL8373_SDS_INTF_OUT1_SDS01_FIB100_DET_OFFSET) + #define RTL8373_SDS_INTF_OUT1_SDS01_SDS_SDET_OUT_OFFSET (11) + #define RTL8373_SDS_INTF_OUT1_SDS01_SDS_SDET_OUT_MASK (0x1 << RTL8373_SDS_INTF_OUT1_SDS01_SDS_SDET_OUT_OFFSET) + #define RTL8373_SDS_INTF_OUT1_RX_SYM_ERR_TGXR0_OFFSET (10) + #define RTL8373_SDS_INTF_OUT1_RX_SYM_ERR_TGXR0_MASK (0x1 << RTL8373_SDS_INTF_OUT1_RX_SYM_ERR_TGXR0_OFFSET) + #define RTL8373_SDS_INTF_OUT1_RXIDLE_D_OFFSET (9) + #define RTL8373_SDS_INTF_OUT1_RXIDLE_D_MASK (0x1 << RTL8373_SDS_INTF_OUT1_RXIDLE_D_OFFSET) + #define RTL8373_SDS_INTF_OUT1_SDS01_SDS_RX_SYM_ERR_ALL_OFFSET (8) + #define RTL8373_SDS_INTF_OUT1_SDS01_SDS_RX_SYM_ERR_ALL_MASK (0x1 << RTL8373_SDS_INTF_OUT1_SDS01_SDS_RX_SYM_ERR_ALL_OFFSET) + #define RTL8373_SDS_INTF_OUT1_SDS01_SDS_LINK_OK_OFFSET (4) + #define RTL8373_SDS_INTF_OUT1_SDS01_SDS_LINK_OK_MASK (0xF << RTL8373_SDS_INTF_OUT1_SDS01_SDS_LINK_OK_OFFSET) + #define RTL8373_SDS_INTF_OUT1_SDS01_STS_UPD_RX_OFFSET (0) + #define RTL8373_SDS_INTF_OUT1_SDS01_STS_UPD_RX_MASK (0xF << RTL8373_SDS_INTF_OUT1_SDS01_STS_UPD_RX_OFFSET) + +/* + * Feature: LED + */ +#define RTL8373_LED_GLB_CTRL_ADDR (0x6520) + #define RTL8373_LED_GLB_CTRL_BLINK_TIME_SEL_OFFSET (21) + #define RTL8373_LED_GLB_CTRL_BLINK_TIME_SEL_MASK (0x7 << RTL8373_LED_GLB_CTRL_BLINK_TIME_SEL_OFFSET) + #define RTL8373_LED_GLB_CTRL_LED_LOAD_EN_OFFSET (18) + #define RTL8373_LED_GLB_CTRL_LED_LOAD_EN_MASK (0x1 << RTL8373_LED_GLB_CTRL_LED_LOAD_EN_OFFSET) + #define RTL8373_LED_GLB_CTRL_SYS_LED_MODE_OFFSET (16) + #define RTL8373_LED_GLB_CTRL_SYS_LED_MODE_MASK (0x3 << RTL8373_LED_GLB_CTRL_SYS_LED_MODE_OFFSET) + #define RTL8373_LED_GLB_CTRL_SYS_LED_EN_OFFSET (15) + #define RTL8373_LED_GLB_CTRL_SYS_LED_EN_MASK (0x1 << RTL8373_LED_GLB_CTRL_SYS_LED_EN_OFFSET) + #define RTL8373_LED_GLB_CTRL_FIB_UNIDIR_LED_EN_OFFSET (14) + #define RTL8373_LED_GLB_CTRL_FIB_UNIDIR_LED_EN_MASK (0x1 << RTL8373_LED_GLB_CTRL_FIB_UNIDIR_LED_EN_OFFSET) + #define RTL8373_LED_GLB_CTRL_POB_EN_OFFSET (13) + #define RTL8373_LED_GLB_CTRL_POB_EN_MASK (0x1 << RTL8373_LED_GLB_CTRL_POB_EN_OFFSET) + #define RTL8373_LED_GLB_CTRL_STP2_PWR_ON_LED_OFFSET (9) + #define RTL8373_LED_GLB_CTRL_STP2_PWR_ON_LED_MASK (0xF << RTL8373_LED_GLB_CTRL_STP2_PWR_ON_LED_OFFSET) + #define RTL8373_LED_GLB_CTRL_STP1_PWR_ON_LED_OFFSET (5) + #define RTL8373_LED_GLB_CTRL_STP1_PWR_ON_LED_MASK (0xF << RTL8373_LED_GLB_CTRL_STP1_PWR_ON_LED_OFFSET) + #define RTL8373_LED_GLB_CTRL_PWR_ON_BLINK_SEL_OFFSET (3) + #define RTL8373_LED_GLB_CTRL_PWR_ON_BLINK_SEL_MASK (0x3 << RTL8373_LED_GLB_CTRL_PWR_ON_BLINK_SEL_OFFSET) + +#define RTL8373_LED3_0_SET3_2_CTRL1_ADDR (0x6524) + #define RTL8373_LED3_0_SET3_2_CTRL1_SET3_LED3_SEL1_OFFSET (28) + #define RTL8373_LED3_0_SET3_2_CTRL1_SET3_LED3_SEL1_MASK (0xF << RTL8373_LED3_0_SET3_2_CTRL1_SET3_LED3_SEL1_OFFSET) + #define RTL8373_LED3_0_SET3_2_CTRL1_SET3_LED2_SEL1_OFFSET (24) + #define RTL8373_LED3_0_SET3_2_CTRL1_SET3_LED2_SEL1_MASK (0xF << RTL8373_LED3_0_SET3_2_CTRL1_SET3_LED2_SEL1_OFFSET) + #define RTL8373_LED3_0_SET3_2_CTRL1_SET3_LED1_SEL1_OFFSET (20) + #define RTL8373_LED3_0_SET3_2_CTRL1_SET3_LED1_SEL1_MASK (0xF << RTL8373_LED3_0_SET3_2_CTRL1_SET3_LED1_SEL1_OFFSET) + #define RTL8373_LED3_0_SET3_2_CTRL1_SET3_LED0_SEL1_OFFSET (16) + #define RTL8373_LED3_0_SET3_2_CTRL1_SET3_LED0_SEL1_MASK (0xF << RTL8373_LED3_0_SET3_2_CTRL1_SET3_LED0_SEL1_OFFSET) + #define RTL8373_LED3_0_SET3_2_CTRL1_SET2_LED3_SEL1_OFFSET (12) + #define RTL8373_LED3_0_SET3_2_CTRL1_SET2_LED3_SEL1_MASK (0xF << RTL8373_LED3_0_SET3_2_CTRL1_SET2_LED3_SEL1_OFFSET) + #define RTL8373_LED3_0_SET3_2_CTRL1_SET2_LED2_SEL1_OFFSET (8) + #define RTL8373_LED3_0_SET3_2_CTRL1_SET2_LED2_SEL1_MASK (0xF << RTL8373_LED3_0_SET3_2_CTRL1_SET2_LED2_SEL1_OFFSET) + #define RTL8373_LED3_0_SET3_2_CTRL1_SET2_LED1_SEL1_OFFSET (4) + #define RTL8373_LED3_0_SET3_2_CTRL1_SET2_LED1_SEL1_MASK (0xF << RTL8373_LED3_0_SET3_2_CTRL1_SET2_LED1_SEL1_OFFSET) + #define RTL8373_LED3_0_SET3_2_CTRL1_SET2_LED0_SEL1_OFFSET (0) + #define RTL8373_LED3_0_SET3_2_CTRL1_SET2_LED0_SEL1_MASK (0xF << RTL8373_LED3_0_SET3_2_CTRL1_SET2_LED0_SEL1_OFFSET) + +#define RTL8373_LED3_0_SET1_0_CTRL1_ADDR (0x6528) + #define RTL8373_LED3_0_SET1_0_CTRL1_SET1_LED3_SEL1_OFFSET (28) + #define RTL8373_LED3_0_SET1_0_CTRL1_SET1_LED3_SEL1_MASK (0xF << RTL8373_LED3_0_SET1_0_CTRL1_SET1_LED3_SEL1_OFFSET) + #define RTL8373_LED3_0_SET1_0_CTRL1_SET1_LED2_SEL1_OFFSET (24) + #define RTL8373_LED3_0_SET1_0_CTRL1_SET1_LED2_SEL1_MASK (0xF << RTL8373_LED3_0_SET1_0_CTRL1_SET1_LED2_SEL1_OFFSET) + #define RTL8373_LED3_0_SET1_0_CTRL1_SET1_LED1_SEL1_OFFSET (20) + #define RTL8373_LED3_0_SET1_0_CTRL1_SET1_LED1_SEL1_MASK (0xF << RTL8373_LED3_0_SET1_0_CTRL1_SET1_LED1_SEL1_OFFSET) + #define RTL8373_LED3_0_SET1_0_CTRL1_SET1_LED0_SEL1_OFFSET (16) + #define RTL8373_LED3_0_SET1_0_CTRL1_SET1_LED0_SEL1_MASK (0xF << RTL8373_LED3_0_SET1_0_CTRL1_SET1_LED0_SEL1_OFFSET) + #define RTL8373_LED3_0_SET1_0_CTRL1_SET0_LED3_SEL1_OFFSET (12) + #define RTL8373_LED3_0_SET1_0_CTRL1_SET0_LED3_SEL1_MASK (0xF << RTL8373_LED3_0_SET1_0_CTRL1_SET0_LED3_SEL1_OFFSET) + #define RTL8373_LED3_0_SET1_0_CTRL1_SET0_LED2_SEL1_OFFSET (8) + #define RTL8373_LED3_0_SET1_0_CTRL1_SET0_LED2_SEL1_MASK (0xF << RTL8373_LED3_0_SET1_0_CTRL1_SET0_LED2_SEL1_OFFSET) + #define RTL8373_LED3_0_SET1_0_CTRL1_SET0_LED1_SEL1_OFFSET (4) + #define RTL8373_LED3_0_SET1_0_CTRL1_SET0_LED1_SEL1_MASK (0xF << RTL8373_LED3_0_SET1_0_CTRL1_SET0_LED1_SEL1_OFFSET) + #define RTL8373_LED3_0_SET1_0_CTRL1_SET0_LED0_SEL1_OFFSET (0) + #define RTL8373_LED3_0_SET1_0_CTRL1_SET0_LED0_SEL1_MASK (0xF << RTL8373_LED3_0_SET1_0_CTRL1_SET0_LED0_SEL1_OFFSET) + +#define RTL8373_LED3_2_SET3_CTRL0_ADDR (0x652C) + #define RTL8373_LED3_2_SET3_CTRL0_SET3_LED3_SEL0_OFFSET (16) + #define RTL8373_LED3_2_SET3_CTRL0_SET3_LED3_SEL0_MASK (0xFFFF << RTL8373_LED3_2_SET3_CTRL0_SET3_LED3_SEL0_OFFSET) + #define RTL8373_LED3_2_SET3_CTRL0_SET3_LED2_SEL0_OFFSET (0) + #define RTL8373_LED3_2_SET3_CTRL0_SET3_LED2_SEL0_MASK (0xFFFF << RTL8373_LED3_2_SET3_CTRL0_SET3_LED2_SEL0_OFFSET) + +#define RTL8373_LED1_0_SET3_CTRL0_ADDR (0x6530) + #define RTL8373_LED1_0_SET3_CTRL0_SET3_LED1_SEL0_OFFSET (16) + #define RTL8373_LED1_0_SET3_CTRL0_SET3_LED1_SEL0_MASK (0xFFFF << RTL8373_LED1_0_SET3_CTRL0_SET3_LED1_SEL0_OFFSET) + #define RTL8373_LED1_0_SET3_CTRL0_SET3_LED0_SEL0_OFFSET (0) + #define RTL8373_LED1_0_SET3_CTRL0_SET3_LED0_SEL0_MASK (0xFFFF << RTL8373_LED1_0_SET3_CTRL0_SET3_LED0_SEL0_OFFSET) + +#define RTL8373_LED3_2_SET2_CTRL0_ADDR (0x6534) + #define RTL8373_LED3_2_SET2_CTRL0_SET2_LED3_SEL0_OFFSET (16) + #define RTL8373_LED3_2_SET2_CTRL0_SET2_LED3_SEL0_MASK (0xFFFF << RTL8373_LED3_2_SET2_CTRL0_SET2_LED3_SEL0_OFFSET) + #define RTL8373_LED3_2_SET2_CTRL0_SET2_LED2_SEL0_OFFSET (0) + #define RTL8373_LED3_2_SET2_CTRL0_SET2_LED2_SEL0_MASK (0xFFFF << RTL8373_LED3_2_SET2_CTRL0_SET2_LED2_SEL0_OFFSET) + +#define RTL8373_LED1_0_SET2_CTRL0_ADDR (0x6538) + #define RTL8373_LED1_0_SET2_CTRL0_SET2_LED1_SEL0_OFFSET (16) + #define RTL8373_LED1_0_SET2_CTRL0_SET2_LED1_SEL0_MASK (0xFFFF << RTL8373_LED1_0_SET2_CTRL0_SET2_LED1_SEL0_OFFSET) + #define RTL8373_LED1_0_SET2_CTRL0_SET2_LED0_SEL0_OFFSET (0) + #define RTL8373_LED1_0_SET2_CTRL0_SET2_LED0_SEL0_MASK (0xFFFF << RTL8373_LED1_0_SET2_CTRL0_SET2_LED0_SEL0_OFFSET) + +#define RTL8373_LED3_2_SET1_CTRL0_ADDR (0x653C) + #define RTL8373_LED3_2_SET1_CTRL0_SET1_LED3_SEL0_OFFSET (16) + #define RTL8373_LED3_2_SET1_CTRL0_SET1_LED3_SEL0_MASK (0xFFFF << RTL8373_LED3_2_SET1_CTRL0_SET1_LED3_SEL0_OFFSET) + #define RTL8373_LED3_2_SET1_CTRL0_SET1_LED2_SEL0_OFFSET (0) + #define RTL8373_LED3_2_SET1_CTRL0_SET1_LED2_SEL0_MASK (0xFFFF << RTL8373_LED3_2_SET1_CTRL0_SET1_LED2_SEL0_OFFSET) + +#define RTL8373_LED1_0_SET1_CTRL0_ADDR (0x6540) + #define RTL8373_LED1_0_SET1_CTRL0_SET1_LED1_SEL0_OFFSET (16) + #define RTL8373_LED1_0_SET1_CTRL0_SET1_LED1_SEL0_MASK (0xFFFF << RTL8373_LED1_0_SET1_CTRL0_SET1_LED1_SEL0_OFFSET) + #define RTL8373_LED1_0_SET1_CTRL0_SET1_LED0_SEL0_OFFSET (0) + #define RTL8373_LED1_0_SET1_CTRL0_SET1_LED0_SEL0_MASK (0xFFFF << RTL8373_LED1_0_SET1_CTRL0_SET1_LED0_SEL0_OFFSET) + +#define RTL8373_LED3_2_SET0_CTRL0_ADDR (0x6544) + #define RTL8373_LED3_2_SET0_CTRL0_SET0_LED3_SEL0_OFFSET (16) + #define RTL8373_LED3_2_SET0_CTRL0_SET0_LED3_SEL0_MASK (0xFFFF << RTL8373_LED3_2_SET0_CTRL0_SET0_LED3_SEL0_OFFSET) + #define RTL8373_LED3_2_SET0_CTRL0_SET0_LED2_SEL0_OFFSET (0) + #define RTL8373_LED3_2_SET0_CTRL0_SET0_LED2_SEL0_MASK (0xFFFF << RTL8373_LED3_2_SET0_CTRL0_SET0_LED2_SEL0_OFFSET) + +#define RTL8373_LED1_0_SET0_CTRL0_ADDR (0x6548) + #define RTL8373_LED1_0_SET0_CTRL0_SET0_LED1_SEL0_OFFSET (16) + #define RTL8373_LED1_0_SET0_CTRL0_SET0_LED1_SEL0_MASK (0xFFFF << RTL8373_LED1_0_SET0_CTRL0_SET0_LED1_SEL0_OFFSET) + #define RTL8373_LED1_0_SET0_CTRL0_SET0_LED0_SEL0_OFFSET (0) + #define RTL8373_LED1_0_SET0_CTRL0_SET0_LED0_SEL0_MASK (0xFFFF << RTL8373_LED1_0_SET0_CTRL0_SET0_LED0_SEL0_OFFSET) + +#define RTL8373_LED_PORT_SET_SEL_CTRL_ADDR(port) (0x654C + (((port / 9) << 2))) /* port: 0-8 */ + #define RTL8373_LED_PORT_SET_SEL_CTRL_LED_SET_PSEL_OFFSET(port) ((port % 0x9) << 1) + #define RTL8373_LED_PORT_SET_SEL_CTRL_LED_SET_PSEL_MASK(port) (0x3 << RTL8373_LED_PORT_SET_SEL_CTRL_LED_SET_PSEL_OFFSET(port)) + +#define RTL8373_SW_LED_LOAD_ADDR (0x6550) + #define RTL8373_SW_LED_LOAD_SW_LED_LOAD_OFFSET (0) + #define RTL8373_SW_LED_LOAD_SW_LED_LOAD_MASK (0x1 << RTL8373_SW_LED_LOAD_SW_LED_LOAD_OFFSET) + +#define RTL8373_LED_PORT_SW_EN_CTRL_ADDR(port) (0x6554 + (((port >> 3) << 2))) /* port: 0-8 */ + #define RTL8373_LED_PORT_SW_EN_CTRL_SW_CTRL_LED_EN_OFFSET(port) ((port & 0x7) << 2) + #define RTL8373_LED_PORT_SW_EN_CTRL_SW_CTRL_LED_EN_MASK(port) (0xF << RTL8373_LED_PORT_SW_EN_CTRL_SW_CTRL_LED_EN_OFFSET(port)) + +#define RTL8373_LED_PORT_SW_CTRL_ADDR(port) (0x655C + (((port) << 2))) /* port: 0-8 */ + #define RTL8373_LED_PORT_SW_CTRL_SW_LED3_MODE_OFFSET (9) + #define RTL8373_LED_PORT_SW_CTRL_SW_LED3_MODE_MASK (0x7 << RTL8373_LED_PORT_SW_CTRL_SW_LED3_MODE_OFFSET) + #define RTL8373_LED_PORT_SW_CTRL_SW_LED2_MODE_OFFSET (6) + #define RTL8373_LED_PORT_SW_CTRL_SW_LED2_MODE_MASK (0x7 << RTL8373_LED_PORT_SW_CTRL_SW_LED2_MODE_OFFSET) + #define RTL8373_LED_PORT_SW_CTRL_SW_LED1_MODE_OFFSET (3) + #define RTL8373_LED_PORT_SW_CTRL_SW_LED1_MODE_MASK (0x7 << RTL8373_LED_PORT_SW_CTRL_SW_LED1_MODE_OFFSET) + #define RTL8373_LED_PORT_SW_CTRL_SW_LED0_MODE_OFFSET (0) + #define RTL8373_LED_PORT_SW_CTRL_SW_LED0_MODE_MASK (0x7 << RTL8373_LED_PORT_SW_CTRL_SW_LED0_MODE_OFFSET) + +#define RTL8373_LED_LOAD_LV1_10G_ADDR (0x6580) + #define RTL8373_LED_LOAD_LV1_10G_LV1_THR_10G_OFFSET (0) + #define RTL8373_LED_LOAD_LV1_10G_LV1_THR_10G_MASK (0xFFFFFF << RTL8373_LED_LOAD_LV1_10G_LV1_THR_10G_OFFSET) + +#define RTL8373_LED_LOAD_LV2_10G_ADDR (0x6584) + #define RTL8373_LED_LOAD_LV2_10G_LV2_THR_10G_OFFSET (0) + #define RTL8373_LED_LOAD_LV2_10G_LV2_THR_10G_MASK (0xFFFFFF << RTL8373_LED_LOAD_LV2_10G_LV2_THR_10G_OFFSET) + +#define RTL8373_LED_LOAD_LV3_10G_ADDR (0x6588) + #define RTL8373_LED_LOAD_LV3_10G_LV3_THR_10G_OFFSET (0) + #define RTL8373_LED_LOAD_LV3_10G_LV3_THR_10G_MASK (0xFFFFFF << RTL8373_LED_LOAD_LV3_10G_LV3_THR_10G_OFFSET) + +#define RTL8373_LED_LOAD_LV1_5G_ADDR (0x658C) + #define RTL8373_LED_LOAD_LV1_5G_LV1_THR_5G_OFFSET (0) + #define RTL8373_LED_LOAD_LV1_5G_LV1_THR_5G_MASK (0xFFFFFF << RTL8373_LED_LOAD_LV1_5G_LV1_THR_5G_OFFSET) + +#define RTL8373_LED_LOAD_LV2_5G_ADDR (0x6590) + #define RTL8373_LED_LOAD_LV2_5G_LV2_THR_5G_OFFSET (0) + #define RTL8373_LED_LOAD_LV2_5G_LV2_THR_5G_MASK (0xFFFFFF << RTL8373_LED_LOAD_LV2_5G_LV2_THR_5G_OFFSET) + +#define RTL8373_LED_LOAD_LV3_5G_ADDR (0x6594) + #define RTL8373_LED_LOAD_LV3_5G_LV3_THR_5G_OFFSET (0) + #define RTL8373_LED_LOAD_LV3_5G_LV3_THR_5G_MASK (0xFFFFFF << RTL8373_LED_LOAD_LV3_5G_LV3_THR_5G_OFFSET) + +#define RTL8373_LED_LOAD_LV1_2P5G_ADDR (0x6598) + #define RTL8373_LED_LOAD_LV1_2P5G_LV1_THR_2P5G_OFFSET (0) + #define RTL8373_LED_LOAD_LV1_2P5G_LV1_THR_2P5G_MASK (0xFFFFFF << RTL8373_LED_LOAD_LV1_2P5G_LV1_THR_2P5G_OFFSET) + +#define RTL8373_LED_LOAD_LV2_2P5G_ADDR (0x659C) + #define RTL8373_LED_LOAD_LV2_2P5G_LV2_THR_2P5G_OFFSET (0) + #define RTL8373_LED_LOAD_LV2_2P5G_LV2_THR_2P5G_MASK (0xFFFFFF << RTL8373_LED_LOAD_LV2_2P5G_LV2_THR_2P5G_OFFSET) + +#define RTL8373_LED_LOAD_LV3_2P5G_ADDR (0x65A0) + #define RTL8373_LED_LOAD_LV3_2P5G_LV3_THR_2P5G_OFFSET (0) + #define RTL8373_LED_LOAD_LV3_2P5G_LV3_THR_2P5G_MASK (0xFFFFFF << RTL8373_LED_LOAD_LV3_2P5G_LV3_THR_2P5G_OFFSET) + +#define RTL8373_LED_LOAD_LV1_1G_ADDR (0x65A4) + #define RTL8373_LED_LOAD_LV1_1G_LV1_THR_1G_OFFSET (0) + #define RTL8373_LED_LOAD_LV1_1G_LV1_THR_1G_MASK (0xFFFFFF << RTL8373_LED_LOAD_LV1_1G_LV1_THR_1G_OFFSET) + +#define RTL8373_LED_LOAD_LV2_1G_ADDR (0x65A8) + #define RTL8373_LED_LOAD_LV2_1G_LV2_THR_1G_OFFSET (0) + #define RTL8373_LED_LOAD_LV2_1G_LV2_THR_1G_MASK (0xFFFFFF << RTL8373_LED_LOAD_LV2_1G_LV2_THR_1G_OFFSET) + +#define RTL8373_LED_LOAD_LV3_1G_ADDR (0x65AC) + #define RTL8373_LED_LOAD_LV3_1G_LV3_THR_1G_OFFSET (0) + #define RTL8373_LED_LOAD_LV3_1G_LV3_THR_1G_MASK (0xFFFFFF << RTL8373_LED_LOAD_LV3_1G_LV3_THR_1G_OFFSET) + +#define RTL8373_LED_LOAD_LV1_500M_ADDR (0x65B0) + #define RTL8373_LED_LOAD_LV1_500M_LV1_THR_500M_OFFSET (0) + #define RTL8373_LED_LOAD_LV1_500M_LV1_THR_500M_MASK (0xFFFFFF << RTL8373_LED_LOAD_LV1_500M_LV1_THR_500M_OFFSET) + +#define RTL8373_LED_LOAD_LV2_500M_ADDR (0x65B4) + #define RTL8373_LED_LOAD_LV2_500M_LV2_THR_500M_OFFSET (0) + #define RTL8373_LED_LOAD_LV2_500M_LV2_THR_500M_MASK (0xFFFFFF << RTL8373_LED_LOAD_LV2_500M_LV2_THR_500M_OFFSET) + +#define RTL8373_LED_LOAD_LV3_500M_ADDR (0x65B8) + #define RTL8373_LED_LOAD_LV3_500M_LV3_THR_500M_OFFSET (0) + #define RTL8373_LED_LOAD_LV3_500M_LV3_THR_500M_MASK (0xFFFFFF << RTL8373_LED_LOAD_LV3_500M_LV3_THR_500M_OFFSET) + +#define RTL8373_LED_LOAD_LV1_100M_ADDR (0x65BC) + #define RTL8373_LED_LOAD_LV1_100M_LV1_THR_100M_OFFSET (0) + #define RTL8373_LED_LOAD_LV1_100M_LV1_THR_100M_MASK (0xFFFFF << RTL8373_LED_LOAD_LV1_100M_LV1_THR_100M_OFFSET) + +#define RTL8373_LED_LOAD_LV2_100M_ADDR (0x65C0) + #define RTL8373_LED_LOAD_LV2_100M_LV2_THR_100M_OFFSET (0) + #define RTL8373_LED_LOAD_LV2_100M_LV2_THR_100M_MASK (0xFFFFF << RTL8373_LED_LOAD_LV2_100M_LV2_THR_100M_OFFSET) + +#define RTL8373_LED_LOAD_LV3_100M_ADDR (0x65C4) + #define RTL8373_LED_LOAD_LV3_100M_LV3_THR_100M_OFFSET (0) + #define RTL8373_LED_LOAD_LV3_100M_LV3_THR_100M_MASK (0xFFFFF << RTL8373_LED_LOAD_LV3_100M_LV3_THR_100M_OFFSET) + +#define RTL8373_LED_LOAD_LV1_10M_ADDR (0x65C8) + #define RTL8373_LED_LOAD_LV1_10M_LV1_THR_10M_OFFSET (0) + #define RTL8373_LED_LOAD_LV1_10M_LV1_THR_10M_MASK (0x1FFFF << RTL8373_LED_LOAD_LV1_10M_LV1_THR_10M_OFFSET) + +#define RTL8373_LED_LOAD_LV2_10M_ADDR (0x65CC) + #define RTL8373_LED_LOAD_LV2_10M_LV2_THR_10M_OFFSET (0) + #define RTL8373_LED_LOAD_LV2_10M_LV2_THR_10M_MASK (0x1FFFF << RTL8373_LED_LOAD_LV2_10M_LV2_THR_10M_OFFSET) + +#define RTL8373_LED_LOAD_LV3_10M_ADDR (0x65D0) + #define RTL8373_LED_LOAD_LV3_10M_LV3_THR_10M_OFFSET (0) + #define RTL8373_LED_LOAD_LV3_10M_LV3_THR_10M_MASK (0x1FFFF << RTL8373_LED_LOAD_LV3_10M_LV3_THR_10M_OFFSET) + +#define RTL8373_LED_P_LOAD_CTRL_ADDR (0x65D4) + #define RTL8373_LED_P_LOAD_CTRL_DV_SPEEDUP_LED_OFFSET (29) + #define RTL8373_LED_P_LOAD_CTRL_DV_SPEEDUP_LED_MASK (0x1 << RTL8373_LED_P_LOAD_CTRL_DV_SPEEDUP_LED_OFFSET) + #define RTL8373_LED_P_LOAD_CTRL_P_LOAD_CNTR_IDX_OFFSET (24) + #define RTL8373_LED_P_LOAD_CTRL_P_LOAD_CNTR_IDX_MASK (0x1F << RTL8373_LED_P_LOAD_CTRL_P_LOAD_CNTR_IDX_OFFSET) + #define RTL8373_LED_P_LOAD_CTRL_P_LOAD_CNTR_OFFSET (0) + #define RTL8373_LED_P_LOAD_CTRL_P_LOAD_CNTR_MASK (0xFFFFFF << RTL8373_LED_P_LOAD_CTRL_P_LOAD_CNTR_OFFSET) + +#define RTL8373_LED_GLB_ACTIVE_ADDR (0x65D8) + #define RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED29_ACTIVE_LOW_OFFSET (29) + #define RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED29_ACTIVE_LOW_MASK (0x1 << RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED29_ACTIVE_LOW_OFFSET) + #define RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED28_ACTIVE_LOW_OFFSET (28) + #define RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED28_ACTIVE_LOW_MASK (0x1 << RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED28_ACTIVE_LOW_OFFSET) + #define RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED27_ACTIVE_LOW_OFFSET (27) + #define RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED27_ACTIVE_LOW_MASK (0x1 << RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED27_ACTIVE_LOW_OFFSET) + #define RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED26_ACTIVE_LOW_OFFSET (26) + #define RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED26_ACTIVE_LOW_MASK (0x1 << RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED26_ACTIVE_LOW_OFFSET) + #define RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED25_ACTIVE_LOW_OFFSET (25) + #define RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED25_ACTIVE_LOW_MASK (0x1 << RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED25_ACTIVE_LOW_OFFSET) + #define RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED24_ACTIVE_LOW_OFFSET (24) + #define RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED24_ACTIVE_LOW_MASK (0x1 << RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED24_ACTIVE_LOW_OFFSET) + #define RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED23_ACTIVE_LOW_OFFSET (23) + #define RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED23_ACTIVE_LOW_MASK (0x1 << RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED23_ACTIVE_LOW_OFFSET) + #define RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED22_ACTIVE_LOW_OFFSET (22) + #define RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED22_ACTIVE_LOW_MASK (0x1 << RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED22_ACTIVE_LOW_OFFSET) + #define RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED21_ACTIVE_LOW_OFFSET (21) + #define RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED21_ACTIVE_LOW_MASK (0x1 << RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED21_ACTIVE_LOW_OFFSET) + #define RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED20_ACTIVE_LOW_OFFSET (20) + #define RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED20_ACTIVE_LOW_MASK (0x1 << RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED20_ACTIVE_LOW_OFFSET) + #define RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED19_ACTIVE_LOW_OFFSET (19) + #define RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED19_ACTIVE_LOW_MASK (0x1 << RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED19_ACTIVE_LOW_OFFSET) + #define RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED18_ACTIVE_LOW_OFFSET (18) + #define RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED18_ACTIVE_LOW_MASK (0x1 << RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED18_ACTIVE_LOW_OFFSET) + #define RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED17_ACTIVE_LOW_OFFSET (17) + #define RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED17_ACTIVE_LOW_MASK (0x1 << RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED17_ACTIVE_LOW_OFFSET) + #define RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED16_ACTIVE_LOW_OFFSET (16) + #define RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED16_ACTIVE_LOW_MASK (0x1 << RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED16_ACTIVE_LOW_OFFSET) + #define RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED15_ACTIVE_LOW_OFFSET (15) + #define RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED15_ACTIVE_LOW_MASK (0x1 << RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED15_ACTIVE_LOW_OFFSET) + #define RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED14_ACTIVE_LOW_OFFSET (14) + #define RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED14_ACTIVE_LOW_MASK (0x1 << RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED14_ACTIVE_LOW_OFFSET) + #define RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED13_ACTIVE_LOW_OFFSET (13) + #define RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED13_ACTIVE_LOW_MASK (0x1 << RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED13_ACTIVE_LOW_OFFSET) + #define RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED12_ACTIVE_LOW_OFFSET (12) + #define RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED12_ACTIVE_LOW_MASK (0x1 << RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED12_ACTIVE_LOW_OFFSET) + #define RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED11_ACTIVE_LOW_OFFSET (11) + #define RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED11_ACTIVE_LOW_MASK (0x1 << RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED11_ACTIVE_LOW_OFFSET) + #define RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED10_ACTIVE_LOW_OFFSET (10) + #define RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED10_ACTIVE_LOW_MASK (0x1 << RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED10_ACTIVE_LOW_OFFSET) + #define RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED9_ACTIVE_LOW_OFFSET (9) + #define RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED9_ACTIVE_LOW_MASK (0x1 << RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED9_ACTIVE_LOW_OFFSET) + #define RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED8_ACTIVE_LOW_OFFSET (8) + #define RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED8_ACTIVE_LOW_MASK (0x1 << RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED8_ACTIVE_LOW_OFFSET) + #define RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED7_ACTIVE_LOW_OFFSET (7) + #define RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED7_ACTIVE_LOW_MASK (0x1 << RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED7_ACTIVE_LOW_OFFSET) + #define RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED6_ACTIVE_LOW_OFFSET (6) + #define RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED6_ACTIVE_LOW_MASK (0x1 << RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED6_ACTIVE_LOW_OFFSET) + #define RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED5_ACTIVE_LOW_OFFSET (5) + #define RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED5_ACTIVE_LOW_MASK (0x1 << RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED5_ACTIVE_LOW_OFFSET) + #define RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED4_ACTIVE_LOW_OFFSET (4) + #define RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED4_ACTIVE_LOW_MASK (0x1 << RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED4_ACTIVE_LOW_OFFSET) + #define RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED3_ACTIVE_LOW_OFFSET (3) + #define RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED3_ACTIVE_LOW_MASK (0x1 << RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED3_ACTIVE_LOW_OFFSET) + #define RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED2_ACTIVE_LOW_OFFSET (2) + #define RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED2_ACTIVE_LOW_MASK (0x1 << RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED2_ACTIVE_LOW_OFFSET) + #define RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED1_ACTIVE_LOW_OFFSET (1) + #define RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED1_ACTIVE_LOW_MASK (0x1 << RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED1_ACTIVE_LOW_OFFSET) + #define RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED0_ACTIVE_LOW_OFFSET (0) + #define RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED0_ACTIVE_LOW_MASK (0x1 << RTL8373_LED_GLB_ACTIVE_CFG_PAD_LED0_ACTIVE_LOW_OFFSET) + +#define RTL8373_LED_GLB_IO_EN_ADDR (0x65DC) + #define RTL8373_LED_GLB_IO_EN_LED_PAD_EN_OFFSET (30) + #define RTL8373_LED_GLB_IO_EN_LED_PAD_EN_MASK (0x1 << RTL8373_LED_GLB_IO_EN_LED_PAD_EN_OFFSET) + #define RTL8373_LED_GLB_IO_EN_CFG_PARA_LED29_IO_EN_OFFSET (29) + #define RTL8373_LED_GLB_IO_EN_CFG_PARA_LED29_IO_EN_MASK (0x1 << RTL8373_LED_GLB_IO_EN_CFG_PARA_LED29_IO_EN_OFFSET) + #define RTL8373_LED_GLB_IO_EN_CFG_PARA_LED28_IO_EN_OFFSET (28) + #define RTL8373_LED_GLB_IO_EN_CFG_PARA_LED28_IO_EN_MASK (0x1 << RTL8373_LED_GLB_IO_EN_CFG_PARA_LED28_IO_EN_OFFSET) + #define RTL8373_LED_GLB_IO_EN_CFG_PARA_LED27_IO_EN_OFFSET (27) + #define RTL8373_LED_GLB_IO_EN_CFG_PARA_LED27_IO_EN_MASK (0x1 << RTL8373_LED_GLB_IO_EN_CFG_PARA_LED27_IO_EN_OFFSET) + #define RTL8373_LED_GLB_IO_EN_CFG_PARA_LED26_IO_EN_OFFSET (26) + #define RTL8373_LED_GLB_IO_EN_CFG_PARA_LED26_IO_EN_MASK (0x1 << RTL8373_LED_GLB_IO_EN_CFG_PARA_LED26_IO_EN_OFFSET) + #define RTL8373_LED_GLB_IO_EN_CFG_PARA_LED25_IO_EN_OFFSET (25) + #define RTL8373_LED_GLB_IO_EN_CFG_PARA_LED25_IO_EN_MASK (0x1 << RTL8373_LED_GLB_IO_EN_CFG_PARA_LED25_IO_EN_OFFSET) + #define RTL8373_LED_GLB_IO_EN_CFG_PARA_LED24_IO_EN_OFFSET (24) + #define RTL8373_LED_GLB_IO_EN_CFG_PARA_LED24_IO_EN_MASK (0x1 << RTL8373_LED_GLB_IO_EN_CFG_PARA_LED24_IO_EN_OFFSET) + #define RTL8373_LED_GLB_IO_EN_CFG_PARA_LED23_IO_EN_OFFSET (23) + #define RTL8373_LED_GLB_IO_EN_CFG_PARA_LED23_IO_EN_MASK (0x1 << RTL8373_LED_GLB_IO_EN_CFG_PARA_LED23_IO_EN_OFFSET) + #define RTL8373_LED_GLB_IO_EN_CFG_PARA_LED22_IO_EN_OFFSET (22) + #define RTL8373_LED_GLB_IO_EN_CFG_PARA_LED22_IO_EN_MASK (0x1 << RTL8373_LED_GLB_IO_EN_CFG_PARA_LED22_IO_EN_OFFSET) + #define RTL8373_LED_GLB_IO_EN_CFG_PARA_LED21_IO_EN_OFFSET (21) + #define RTL8373_LED_GLB_IO_EN_CFG_PARA_LED21_IO_EN_MASK (0x1 << RTL8373_LED_GLB_IO_EN_CFG_PARA_LED21_IO_EN_OFFSET) + #define RTL8373_LED_GLB_IO_EN_CFG_PARA_LED20_IO_EN_OFFSET (20) + #define RTL8373_LED_GLB_IO_EN_CFG_PARA_LED20_IO_EN_MASK (0x1 << RTL8373_LED_GLB_IO_EN_CFG_PARA_LED20_IO_EN_OFFSET) + #define RTL8373_LED_GLB_IO_EN_CFG_PARA_LED19_IO_EN_OFFSET (19) + #define RTL8373_LED_GLB_IO_EN_CFG_PARA_LED19_IO_EN_MASK (0x1 << RTL8373_LED_GLB_IO_EN_CFG_PARA_LED19_IO_EN_OFFSET) + #define RTL8373_LED_GLB_IO_EN_CFG_PARA_LED18_IO_EN_OFFSET (18) + #define RTL8373_LED_GLB_IO_EN_CFG_PARA_LED18_IO_EN_MASK (0x1 << RTL8373_LED_GLB_IO_EN_CFG_PARA_LED18_IO_EN_OFFSET) + #define RTL8373_LED_GLB_IO_EN_CFG_PARA_LED17_IO_EN_OFFSET (17) + #define RTL8373_LED_GLB_IO_EN_CFG_PARA_LED17_IO_EN_MASK (0x1 << RTL8373_LED_GLB_IO_EN_CFG_PARA_LED17_IO_EN_OFFSET) + #define RTL8373_LED_GLB_IO_EN_CFG_PARA_LED16_IO_EN_OFFSET (16) + #define RTL8373_LED_GLB_IO_EN_CFG_PARA_LED16_IO_EN_MASK (0x1 << RTL8373_LED_GLB_IO_EN_CFG_PARA_LED16_IO_EN_OFFSET) + #define RTL8373_LED_GLB_IO_EN_CFG_PARA_LED15_IO_EN_OFFSET (15) + #define RTL8373_LED_GLB_IO_EN_CFG_PARA_LED15_IO_EN_MASK (0x1 << RTL8373_LED_GLB_IO_EN_CFG_PARA_LED15_IO_EN_OFFSET) + #define RTL8373_LED_GLB_IO_EN_CFG_PARA_LED14_IO_EN_OFFSET (14) + #define RTL8373_LED_GLB_IO_EN_CFG_PARA_LED14_IO_EN_MASK (0x1 << RTL8373_LED_GLB_IO_EN_CFG_PARA_LED14_IO_EN_OFFSET) + #define RTL8373_LED_GLB_IO_EN_CFG_PARA_LED13_IO_EN_OFFSET (13) + #define RTL8373_LED_GLB_IO_EN_CFG_PARA_LED13_IO_EN_MASK (0x1 << RTL8373_LED_GLB_IO_EN_CFG_PARA_LED13_IO_EN_OFFSET) + #define RTL8373_LED_GLB_IO_EN_CFG_PARA_LED12_IO_EN_OFFSET (12) + #define RTL8373_LED_GLB_IO_EN_CFG_PARA_LED12_IO_EN_MASK (0x1 << RTL8373_LED_GLB_IO_EN_CFG_PARA_LED12_IO_EN_OFFSET) + #define RTL8373_LED_GLB_IO_EN_CFG_PARA_LED11_IO_EN_OFFSET (11) + #define RTL8373_LED_GLB_IO_EN_CFG_PARA_LED11_IO_EN_MASK (0x1 << RTL8373_LED_GLB_IO_EN_CFG_PARA_LED11_IO_EN_OFFSET) + #define RTL8373_LED_GLB_IO_EN_CFG_PARA_LED10_IO_EN_OFFSET (10) + #define RTL8373_LED_GLB_IO_EN_CFG_PARA_LED10_IO_EN_MASK (0x1 << RTL8373_LED_GLB_IO_EN_CFG_PARA_LED10_IO_EN_OFFSET) + #define RTL8373_LED_GLB_IO_EN_CFG_PARA_LED9_IO_EN_OFFSET (9) + #define RTL8373_LED_GLB_IO_EN_CFG_PARA_LED9_IO_EN_MASK (0x1 << RTL8373_LED_GLB_IO_EN_CFG_PARA_LED9_IO_EN_OFFSET) + #define RTL8373_LED_GLB_IO_EN_CFG_PARA_LED8_IO_EN_OFFSET (8) + #define RTL8373_LED_GLB_IO_EN_CFG_PARA_LED8_IO_EN_MASK (0x1 << RTL8373_LED_GLB_IO_EN_CFG_PARA_LED8_IO_EN_OFFSET) + #define RTL8373_LED_GLB_IO_EN_CFG_PARA_LED7_IO_EN_OFFSET (7) + #define RTL8373_LED_GLB_IO_EN_CFG_PARA_LED7_IO_EN_MASK (0x1 << RTL8373_LED_GLB_IO_EN_CFG_PARA_LED7_IO_EN_OFFSET) + #define RTL8373_LED_GLB_IO_EN_CFG_PARA_LED6_IO_EN_OFFSET (6) + #define RTL8373_LED_GLB_IO_EN_CFG_PARA_LED6_IO_EN_MASK (0x1 << RTL8373_LED_GLB_IO_EN_CFG_PARA_LED6_IO_EN_OFFSET) + #define RTL8373_LED_GLB_IO_EN_CFG_PARA_LED5_IO_EN_OFFSET (5) + #define RTL8373_LED_GLB_IO_EN_CFG_PARA_LED5_IO_EN_MASK (0x1 << RTL8373_LED_GLB_IO_EN_CFG_PARA_LED5_IO_EN_OFFSET) + #define RTL8373_LED_GLB_IO_EN_CFG_PARA_LED4_IO_EN_OFFSET (4) + #define RTL8373_LED_GLB_IO_EN_CFG_PARA_LED4_IO_EN_MASK (0x1 << RTL8373_LED_GLB_IO_EN_CFG_PARA_LED4_IO_EN_OFFSET) + #define RTL8373_LED_GLB_IO_EN_CFG_PARA_LED3_IO_EN_OFFSET (3) + #define RTL8373_LED_GLB_IO_EN_CFG_PARA_LED3_IO_EN_MASK (0x1 << RTL8373_LED_GLB_IO_EN_CFG_PARA_LED3_IO_EN_OFFSET) + #define RTL8373_LED_GLB_IO_EN_CFG_PARA_LED2_IO_EN_OFFSET (2) + #define RTL8373_LED_GLB_IO_EN_CFG_PARA_LED2_IO_EN_MASK (0x1 << RTL8373_LED_GLB_IO_EN_CFG_PARA_LED2_IO_EN_OFFSET) + #define RTL8373_LED_GLB_IO_EN_CFG_PARA_LED1_IO_EN_OFFSET (1) + #define RTL8373_LED_GLB_IO_EN_CFG_PARA_LED1_IO_EN_MASK (0x1 << RTL8373_LED_GLB_IO_EN_CFG_PARA_LED1_IO_EN_OFFSET) + #define RTL8373_LED_GLB_IO_EN_CFG_PARA_LED0_IO_EN_OFFSET (0) + #define RTL8373_LED_GLB_IO_EN_CFG_PARA_LED0_IO_EN_MASK (0x1 << RTL8373_LED_GLB_IO_EN_CFG_PARA_LED0_IO_EN_OFFSET) + +#define RTL8373_LED_GLB_MUX_1_ADDR (0x65E0) + #define RTL8373_LED_GLB_MUX_1_CFG_PAD_LED4_MUX_OFFSET (24) + #define RTL8373_LED_GLB_MUX_1_CFG_PAD_LED4_MUX_MASK (0x3F << RTL8373_LED_GLB_MUX_1_CFG_PAD_LED4_MUX_OFFSET) + #define RTL8373_LED_GLB_MUX_1_CFG_PAD_LED3_MUX_OFFSET (18) + #define RTL8373_LED_GLB_MUX_1_CFG_PAD_LED3_MUX_MASK (0x3F << RTL8373_LED_GLB_MUX_1_CFG_PAD_LED3_MUX_OFFSET) + #define RTL8373_LED_GLB_MUX_1_CFG_PAD_LED2_MUX_OFFSET (12) + #define RTL8373_LED_GLB_MUX_1_CFG_PAD_LED2_MUX_MASK (0x3F << RTL8373_LED_GLB_MUX_1_CFG_PAD_LED2_MUX_OFFSET) + #define RTL8373_LED_GLB_MUX_1_CFG_PAD_LED1_MUX_OFFSET (6) + #define RTL8373_LED_GLB_MUX_1_CFG_PAD_LED1_MUX_MASK (0x3F << RTL8373_LED_GLB_MUX_1_CFG_PAD_LED1_MUX_OFFSET) + #define RTL8373_LED_GLB_MUX_1_CFG_PAD_LED0_MUX_OFFSET (0) + #define RTL8373_LED_GLB_MUX_1_CFG_PAD_LED0_MUX_MASK (0x3F << RTL8373_LED_GLB_MUX_1_CFG_PAD_LED0_MUX_OFFSET) + +#define RTL8373_LED_GLB_MUX_2_ADDR (0x65E4) + #define RTL8373_LED_GLB_MUX_2_CFG_PAD_LED9_MUX_OFFSET (24) + #define RTL8373_LED_GLB_MUX_2_CFG_PAD_LED9_MUX_MASK (0x3F << RTL8373_LED_GLB_MUX_2_CFG_PAD_LED9_MUX_OFFSET) + #define RTL8373_LED_GLB_MUX_2_CFG_PAD_LED8_MUX_OFFSET (18) + #define RTL8373_LED_GLB_MUX_2_CFG_PAD_LED8_MUX_MASK (0x3F << RTL8373_LED_GLB_MUX_2_CFG_PAD_LED8_MUX_OFFSET) + #define RTL8373_LED_GLB_MUX_2_CFG_PAD_LED7_MUX_OFFSET (12) + #define RTL8373_LED_GLB_MUX_2_CFG_PAD_LED7_MUX_MASK (0x3F << RTL8373_LED_GLB_MUX_2_CFG_PAD_LED7_MUX_OFFSET) + #define RTL8373_LED_GLB_MUX_2_CFG_PAD_LED6_MUX_OFFSET (6) + #define RTL8373_LED_GLB_MUX_2_CFG_PAD_LED6_MUX_MASK (0x3F << RTL8373_LED_GLB_MUX_2_CFG_PAD_LED6_MUX_OFFSET) + #define RTL8373_LED_GLB_MUX_2_CFG_PAD_LED5_MUX_OFFSET (0) + #define RTL8373_LED_GLB_MUX_2_CFG_PAD_LED5_MUX_MASK (0x3F << RTL8373_LED_GLB_MUX_2_CFG_PAD_LED5_MUX_OFFSET) + +#define RTL8373_LED_GLB_MUX_3_ADDR (0x65E8) + #define RTL8373_LED_GLB_MUX_3_CFG_PAD_LED14_MUX_OFFSET (24) + #define RTL8373_LED_GLB_MUX_3_CFG_PAD_LED14_MUX_MASK (0x3F << RTL8373_LED_GLB_MUX_3_CFG_PAD_LED14_MUX_OFFSET) + #define RTL8373_LED_GLB_MUX_3_CFG_PAD_LED13_MUX_OFFSET (18) + #define RTL8373_LED_GLB_MUX_3_CFG_PAD_LED13_MUX_MASK (0x3F << RTL8373_LED_GLB_MUX_3_CFG_PAD_LED13_MUX_OFFSET) + #define RTL8373_LED_GLB_MUX_3_CFG_PAD_LED12_MUX_OFFSET (12) + #define RTL8373_LED_GLB_MUX_3_CFG_PAD_LED12_MUX_MASK (0x3F << RTL8373_LED_GLB_MUX_3_CFG_PAD_LED12_MUX_OFFSET) + #define RTL8373_LED_GLB_MUX_3_CFG_PAD_LED11_MUX_OFFSET (6) + #define RTL8373_LED_GLB_MUX_3_CFG_PAD_LED11_MUX_MASK (0x3F << RTL8373_LED_GLB_MUX_3_CFG_PAD_LED11_MUX_OFFSET) + #define RTL8373_LED_GLB_MUX_3_CFG_PAD_LED10_MUX_OFFSET (0) + #define RTL8373_LED_GLB_MUX_3_CFG_PAD_LED10_MUX_MASK (0x3F << RTL8373_LED_GLB_MUX_3_CFG_PAD_LED10_MUX_OFFSET) + +#define RTL8373_LED_GLB_MUX_4_ADDR (0x65EC) + #define RTL8373_LED_GLB_MUX_4_CFG_PAD_LED19_MUX_OFFSET (24) + #define RTL8373_LED_GLB_MUX_4_CFG_PAD_LED19_MUX_MASK (0x3F << RTL8373_LED_GLB_MUX_4_CFG_PAD_LED19_MUX_OFFSET) + #define RTL8373_LED_GLB_MUX_4_CFG_PAD_LED18_MUX_OFFSET (18) + #define RTL8373_LED_GLB_MUX_4_CFG_PAD_LED18_MUX_MASK (0x3F << RTL8373_LED_GLB_MUX_4_CFG_PAD_LED18_MUX_OFFSET) + #define RTL8373_LED_GLB_MUX_4_CFG_PAD_LED17_MUX_OFFSET (12) + #define RTL8373_LED_GLB_MUX_4_CFG_PAD_LED17_MUX_MASK (0x3F << RTL8373_LED_GLB_MUX_4_CFG_PAD_LED17_MUX_OFFSET) + #define RTL8373_LED_GLB_MUX_4_CFG_PAD_LED16_MUX_OFFSET (6) + #define RTL8373_LED_GLB_MUX_4_CFG_PAD_LED16_MUX_MASK (0x3F << RTL8373_LED_GLB_MUX_4_CFG_PAD_LED16_MUX_OFFSET) + #define RTL8373_LED_GLB_MUX_4_CFG_PAD_LED15_MUX_OFFSET (0) + #define RTL8373_LED_GLB_MUX_4_CFG_PAD_LED15_MUX_MASK (0x3F << RTL8373_LED_GLB_MUX_4_CFG_PAD_LED15_MUX_OFFSET) + +#define RTL8373_LED_GLB_MUX_5_ADDR (0x65F0) + #define RTL8373_LED_GLB_MUX_5_CFG_PAD_LED24_MUX_OFFSET (24) + #define RTL8373_LED_GLB_MUX_5_CFG_PAD_LED24_MUX_MASK (0x3F << RTL8373_LED_GLB_MUX_5_CFG_PAD_LED24_MUX_OFFSET) + #define RTL8373_LED_GLB_MUX_5_CFG_PAD_LED23_MUX_OFFSET (18) + #define RTL8373_LED_GLB_MUX_5_CFG_PAD_LED23_MUX_MASK (0x3F << RTL8373_LED_GLB_MUX_5_CFG_PAD_LED23_MUX_OFFSET) + #define RTL8373_LED_GLB_MUX_5_CFG_PAD_LED22_MUX_OFFSET (12) + #define RTL8373_LED_GLB_MUX_5_CFG_PAD_LED22_MUX_MASK (0x3F << RTL8373_LED_GLB_MUX_5_CFG_PAD_LED22_MUX_OFFSET) + #define RTL8373_LED_GLB_MUX_5_CFG_PAD_LED21_MUX_OFFSET (6) + #define RTL8373_LED_GLB_MUX_5_CFG_PAD_LED21_MUX_MASK (0x3F << RTL8373_LED_GLB_MUX_5_CFG_PAD_LED21_MUX_OFFSET) + #define RTL8373_LED_GLB_MUX_5_CFG_PAD_LED20_MUX_OFFSET (0) + #define RTL8373_LED_GLB_MUX_5_CFG_PAD_LED20_MUX_MASK (0x3F << RTL8373_LED_GLB_MUX_5_CFG_PAD_LED20_MUX_OFFSET) + +#define RTL8373_LED_GLB_MUX_6_ADDR (0x65F4) + #define RTL8373_LED_GLB_MUX_6_CFG_PAD_LED27_MUX_OFFSET (12) + #define RTL8373_LED_GLB_MUX_6_CFG_PAD_LED27_MUX_MASK (0x3F << RTL8373_LED_GLB_MUX_6_CFG_PAD_LED27_MUX_OFFSET) + #define RTL8373_LED_GLB_MUX_6_CFG_PAD_LED26_MUX_OFFSET (6) + #define RTL8373_LED_GLB_MUX_6_CFG_PAD_LED26_MUX_MASK (0x3F << RTL8373_LED_GLB_MUX_6_CFG_PAD_LED26_MUX_OFFSET) + #define RTL8373_LED_GLB_MUX_6_CFG_PAD_LED25_MUX_OFFSET (0) + #define RTL8373_LED_GLB_MUX_6_CFG_PAD_LED25_MUX_MASK (0x3F << RTL8373_LED_GLB_MUX_6_CFG_PAD_LED25_MUX_OFFSET) + +#define RTL8373_LED_RLDP_CTRL_1_ADDR (0x65F8) + #define RTL8373_LED_RLDP_CTRL_1_LOOP_DETECT_RATE_OFFSET (2) + #define RTL8373_LED_RLDP_CTRL_1_LOOP_DETECT_RATE_MASK (0x7 << RTL8373_LED_RLDP_CTRL_1_LOOP_DETECT_RATE_OFFSET) + #define RTL8373_LED_RLDP_CTRL_1_RLDP_LED_ENABLE_OFFSET (1) + #define RTL8373_LED_RLDP_CTRL_1_RLDP_LED_ENABLE_MASK (0x1 << RTL8373_LED_RLDP_CTRL_1_RLDP_LED_ENABLE_OFFSET) + #define RTL8373_LED_RLDP_CTRL_1_GLB_RLDP_LED_ENABLE_OFFSET (0) + #define RTL8373_LED_RLDP_CTRL_1_GLB_RLDP_LED_ENABLE_MASK (0x1 << RTL8373_LED_RLDP_CTRL_1_GLB_RLDP_LED_ENABLE_OFFSET) + +#define RTL8373_LED_RLDP_CTRL_2_ADDR (0x65FC) + #define RTL8373_LED_RLDP_CTRL_2_P7_LED3_0_RLDP_MASK_OFFSET (28) + #define RTL8373_LED_RLDP_CTRL_2_P7_LED3_0_RLDP_MASK_MASK (0xF << RTL8373_LED_RLDP_CTRL_2_P7_LED3_0_RLDP_MASK_OFFSET) + #define RTL8373_LED_RLDP_CTRL_2_P6_LED3_0_RLDP_MASK_OFFSET (24) + #define RTL8373_LED_RLDP_CTRL_2_P6_LED3_0_RLDP_MASK_MASK (0xF << RTL8373_LED_RLDP_CTRL_2_P6_LED3_0_RLDP_MASK_OFFSET) + #define RTL8373_LED_RLDP_CTRL_2_P5_LED3_0_RLDP_MASK_OFFSET (20) + #define RTL8373_LED_RLDP_CTRL_2_P5_LED3_0_RLDP_MASK_MASK (0xF << RTL8373_LED_RLDP_CTRL_2_P5_LED3_0_RLDP_MASK_OFFSET) + #define RTL8373_LED_RLDP_CTRL_2_P4_LED3_0_RLDP_MASK_OFFSET (16) + #define RTL8373_LED_RLDP_CTRL_2_P4_LED3_0_RLDP_MASK_MASK (0xF << RTL8373_LED_RLDP_CTRL_2_P4_LED3_0_RLDP_MASK_OFFSET) + #define RTL8373_LED_RLDP_CTRL_2_P3_LED3_0_RLDP_MASK_OFFSET (12) + #define RTL8373_LED_RLDP_CTRL_2_P3_LED3_0_RLDP_MASK_MASK (0xF << RTL8373_LED_RLDP_CTRL_2_P3_LED3_0_RLDP_MASK_OFFSET) + #define RTL8373_LED_RLDP_CTRL_2_P2_LED3_0_RLDP_MASK_OFFSET (8) + #define RTL8373_LED_RLDP_CTRL_2_P2_LED3_0_RLDP_MASK_MASK (0xF << RTL8373_LED_RLDP_CTRL_2_P2_LED3_0_RLDP_MASK_OFFSET) + #define RTL8373_LED_RLDP_CTRL_2_P1_LED3_0_RLDP_MASK_OFFSET (4) + #define RTL8373_LED_RLDP_CTRL_2_P1_LED3_0_RLDP_MASK_MASK (0xF << RTL8373_LED_RLDP_CTRL_2_P1_LED3_0_RLDP_MASK_OFFSET) + #define RTL8373_LED_RLDP_CTRL_2_P0_LED3_0_RLDP_MASK_OFFSET (0) + #define RTL8373_LED_RLDP_CTRL_2_P0_LED3_0_RLDP_MASK_MASK (0xF << RTL8373_LED_RLDP_CTRL_2_P0_LED3_0_RLDP_MASK_OFFSET) + +#define RTL8373_LED_RLDP_CTRL_3_ADDR (0x6600) + #define RTL8373_LED_RLDP_CTRL_3_P8_LED3_0_RLDP_MASK_OFFSET (0) + #define RTL8373_LED_RLDP_CTRL_3_P8_LED3_0_RLDP_MASK_MASK (0xF << RTL8373_LED_RLDP_CTRL_3_P8_LED3_0_RLDP_MASK_OFFSET) + +/* + * Feature: Smart Packet Generator + */ +#define RTL8373_SPG_GLB_CTRL_ADDR (0x4434) + #define RTL8373_SPG_GLB_CTRL_GRP_TX_CMD_OFFSET (1) + #define RTL8373_SPG_GLB_CTRL_GRP_TX_CMD_MASK (0x3 << RTL8373_SPG_GLB_CTRL_GRP_TX_CMD_OFFSET) + #define RTL8373_SPG_GLB_CTRL_SPG_MODE_OFFSET (0) + #define RTL8373_SPG_GLB_CTRL_SPG_MODE_MASK (0x1 << RTL8373_SPG_GLB_CTRL_SPG_MODE_OFFSET) + +#define RTL8373_PKB_ACC_DEBUG_CTRL_ADDR (0x756C) + #define RTL8373_PKB_ACC_DEBUG_CTRL_DBG_ACC_PKB_EN_OFFSET (0) + #define RTL8373_PKB_ACC_DEBUG_CTRL_DBG_ACC_PKB_EN_MASK (0x1 << RTL8373_PKB_ACC_DEBUG_CTRL_DBG_ACC_PKB_EN_OFFSET) + +#define RTL8373_SPG_PORT_TX_GRP_CTRL_ADDR (0x4438) + #define RTL8373_SPG_PORT_TX_GRP_CTRL_GRP_TX_PORT_OFFSET (0) + #define RTL8373_SPG_PORT_TX_GRP_CTRL_GRP_TX_PORT_MASK (0x1FF << RTL8373_SPG_PORT_TX_GRP_CTRL_GRP_TX_PORT_OFFSET) + +#define RTL8373_SPG_GLOBAL_STS_ADDR (0x443C) + #define RTL8373_SPG_GLOBAL_STS_TX_DONE_PORT_OFFSET (0) + #define RTL8373_SPG_GLOBAL_STS_TX_DONE_PORT_MASK (0x1FF << RTL8373_SPG_GLOBAL_STS_TX_DONE_PORT_OFFSET) + +#define RTL8373_SPG_PORT_IBG_CTRL0_ADDR(port) (0x1210 + (((port) << 8))) /* port: 0-9 */ + #define RTL8373_SPG_PORT_IBG_CTRL0_IBG_LEN_OFFSET (0) + #define RTL8373_SPG_PORT_IBG_CTRL0_IBG_LEN_MASK (0xFFFFFFFF << RTL8373_SPG_PORT_IBG_CTRL0_IBG_LEN_OFFSET) + +#define RTL8373_SPG_PORT_IBG_CTRL1_ADDR(port) (0x1214 + (((port) << 8))) /* port: 0-9 */ + #define RTL8373_SPG_PORT_IBG_CTRL1_IBG_SIZE_OFFSET (0) + #define RTL8373_SPG_PORT_IBG_CTRL1_IBG_SIZE_MASK (0xFFFF << RTL8373_SPG_PORT_IBG_CTRL1_IBG_SIZE_OFFSET) + +#define RTL8373_SPG_PORT_IPG_CTRL_ADDR(port) (0x1218 + (((port) << 8))) /* port: 0-9 */ + #define RTL8373_SPG_PORT_IPG_CTRL_IPG_LEN_OFFSET (0) + #define RTL8373_SPG_PORT_IPG_CTRL_IPG_LEN_MASK (0xFFFFF << RTL8373_SPG_PORT_IPG_CTRL_IPG_LEN_OFFSET) + +#define RTL8373_SPG_PORT_PKT_CNT_H_ADDR(port) (0x1C10 + (((port) << 10))) /* port: 0-9 */ + #define RTL8373_SPG_PORT_PKT_CNT_H_PKT_CNT_HIGH_OFFSET (0) + #define RTL8373_SPG_PORT_PKT_CNT_H_PKT_CNT_HIGH_MASK (0xFFFFFFFF << RTL8373_SPG_PORT_PKT_CNT_H_PKT_CNT_HIGH_OFFSET) + +#define RTL8373_SPG_PORT_PKT_CNT_L_ADDR(port) (0x1C14 + (((port) << 10))) /* port: 0-9 */ + #define RTL8373_SPG_PORT_PKT_CNT_L_PKT_CNT_LOW_OFFSET (0) + #define RTL8373_SPG_PORT_PKT_CNT_L_PKT_CNT_LOW_MASK (0xFFFFFFFF << RTL8373_SPG_PORT_PKT_CNT_L_PKT_CNT_LOW_OFFSET) + +#define RTL8373_SPG_PORT_PKT_CNT_DBG_H_ADDR(port) (0x1C18 + (((port) << 10))) /* port: 0-9 */ + #define RTL8373_SPG_PORT_PKT_CNT_DBG_H_PKT_CNT_DBG_HIGH_OFFSET (0) + #define RTL8373_SPG_PORT_PKT_CNT_DBG_H_PKT_CNT_DBG_HIGH_MASK (0xFFFFFFFF << RTL8373_SPG_PORT_PKT_CNT_DBG_H_PKT_CNT_DBG_HIGH_OFFSET) + +#define RTL8373_SPG_PORT_PKT_CNT_DBG_L_ADDR(port) (0x1C1C + (((port) << 10))) /* port: 0-9 */ + #define RTL8373_SPG_PORT_PKT_CNT_DBG_L_PKT_CNT_DBG_LOW_OFFSET (0) + #define RTL8373_SPG_PORT_PKT_CNT_DBG_L_PKT_CNT_DBG_LOW_MASK (0xFFFFFFFF << RTL8373_SPG_PORT_PKT_CNT_DBG_L_PKT_CNT_DBG_LOW_OFFSET) + +#define RTL8373_SPG_PORT_STREAM0_CTRL0_ADDR(port) (0x1C20 + (((port) << 10))) /* port: 0-9 */ + #define RTL8373_SPG_PORT_STREAM0_CTRL0_BAD_CRC_EN_0_OFFSET (13) + #define RTL8373_SPG_PORT_STREAM0_CTRL0_BAD_CRC_EN_0_MASK (0x1 << RTL8373_SPG_PORT_STREAM0_CTRL0_BAD_CRC_EN_0_OFFSET) + #define RTL8373_SPG_PORT_STREAM0_CTRL0_STREAM_DA_MOD_0_OFFSET (11) + #define RTL8373_SPG_PORT_STREAM0_CTRL0_STREAM_DA_MOD_0_MASK (0x3 << RTL8373_SPG_PORT_STREAM0_CTRL0_STREAM_DA_MOD_0_OFFSET) + #define RTL8373_SPG_PORT_STREAM0_CTRL0_STREAM_SA_MOD_0_OFFSET (9) + #define RTL8373_SPG_PORT_STREAM0_CTRL0_STREAM_SA_MOD_0_MASK (0x3 << RTL8373_SPG_PORT_STREAM0_CTRL0_STREAM_SA_MOD_0_OFFSET) + #define RTL8373_SPG_PORT_STREAM0_CTRL0_STREAM_LEN_TYPE_0_OFFSET (7) + #define RTL8373_SPG_PORT_STREAM0_CTRL0_STREAM_LEN_TYPE_0_MASK (0x3 << RTL8373_SPG_PORT_STREAM0_CTRL0_STREAM_LEN_TYPE_0_OFFSET) + #define RTL8373_SPG_PORT_STREAM0_CTRL0_STREAM_CONTENT_OFFSET_0_OFFSET (2) + #define RTL8373_SPG_PORT_STREAM0_CTRL0_STREAM_CONTENT_OFFSET_0_MASK (0x1F << RTL8373_SPG_PORT_STREAM0_CTRL0_STREAM_CONTENT_OFFSET_0_OFFSET) + #define RTL8373_SPG_PORT_STREAM0_CTRL0_STREAM_CONTENT_MOD_0_OFFSET (0) + #define RTL8373_SPG_PORT_STREAM0_CTRL0_STREAM_CONTENT_MOD_0_MASK (0x3 << RTL8373_SPG_PORT_STREAM0_CTRL0_STREAM_CONTENT_MOD_0_OFFSET) + +#define RTL8373_SPG_PORT_STREAM0_CTRL1_ADDR(port) (0x1C24 + (((port) << 10))) /* port: 0-9 */ + #define RTL8373_SPG_PORT_STREAM0_CTRL1_STREAM_LEN_RNG_START_0_OFFSET (16) + #define RTL8373_SPG_PORT_STREAM0_CTRL1_STREAM_LEN_RNG_START_0_MASK (0x3FFF << RTL8373_SPG_PORT_STREAM0_CTRL1_STREAM_LEN_RNG_START_0_OFFSET) + #define RTL8373_SPG_PORT_STREAM0_CTRL1_STREAM_LEN_RNG_END_0_OFFSET (0) + #define RTL8373_SPG_PORT_STREAM0_CTRL1_STREAM_LEN_RNG_END_0_MASK (0x3FFF << RTL8373_SPG_PORT_STREAM0_CTRL1_STREAM_LEN_RNG_END_0_OFFSET) + +#define RTL8373_SPG_PORT_STREAM0_CTRL2_ADDR(port) (0x1C28 + (((port) << 10))) /* port: 0-9 */ + #define RTL8373_SPG_PORT_STREAM0_CTRL2_STREAM_DA_ADD_CNT_0_OFFSET (16) + #define RTL8373_SPG_PORT_STREAM0_CTRL2_STREAM_DA_ADD_CNT_0_MASK (0x7FFF << RTL8373_SPG_PORT_STREAM0_CTRL2_STREAM_DA_ADD_CNT_0_OFFSET) + #define RTL8373_SPG_PORT_STREAM0_CTRL2_STREAM_SA_ADD_CNT_0_OFFSET (0) + #define RTL8373_SPG_PORT_STREAM0_CTRL2_STREAM_SA_ADD_CNT_0_MASK (0x7FFF << RTL8373_SPG_PORT_STREAM0_CTRL2_STREAM_SA_ADD_CNT_0_OFFSET) + +#define RTL8373_SPG_PORT_STREAM0_CTRL3_ADDR(port) (0x1C2C + (((port) << 10))) /* port: 0-9 */ + #define RTL8373_SPG_PORT_STREAM0_CTRL3_STREAM_REPEAT_CONTENT_0_OFFSET (0) + #define RTL8373_SPG_PORT_STREAM0_CTRL3_STREAM_REPEAT_CONTENT_0_MASK (0xFFFFFFFF << RTL8373_SPG_PORT_STREAM0_CTRL3_STREAM_REPEAT_CONTENT_0_OFFSET) + +#define RTL8373_SPG_PB_ACCESS_CTRL0_ADDR (0x7570) + #define RTL8373_SPG_PB_ACCESS_CTRL0_PB_INDEX_OFFSET (0) + #define RTL8373_SPG_PB_ACCESS_CTRL0_PB_INDEX_MASK (0x3F << RTL8373_SPG_PB_ACCESS_CTRL0_PB_INDEX_OFFSET) + +#define RTL8373_SPG_PB_ACCESS_CTRL1_ADDR (0x7574) + #define RTL8373_SPG_PB_ACCESS_CTRL1_ACCESS_DATA_OFFSET (0) + #define RTL8373_SPG_PB_ACCESS_CTRL1_ACCESS_DATA_MASK (0xFFFFFFFF << RTL8373_SPG_PB_ACCESS_CTRL1_ACCESS_DATA_OFFSET) + +#define RTL8373_SPG_PB_ACCESS_CTRL2_ADDR (0x7578) + #define RTL8373_SPG_PB_ACCESS_CTRL2_PB_TRIG_OFFSET (31) + #define RTL8373_SPG_PB_ACCESS_CTRL2_PB_TRIG_MASK (0x1 << RTL8373_SPG_PB_ACCESS_CTRL2_PB_TRIG_OFFSET) + #define RTL8373_SPG_PB_ACCESS_CTRL2_PB_TYPE_OFFSET (30) + #define RTL8373_SPG_PB_ACCESS_CTRL2_PB_TYPE_MASK (0x1 << RTL8373_SPG_PB_ACCESS_CTRL2_PB_TYPE_OFFSET) + #define RTL8373_SPG_PB_ACCESS_CTRL2_PB_CELL_INDEX_OFFSET (8) + #define RTL8373_SPG_PB_ACCESS_CTRL2_PB_CELL_INDEX_MASK (0xFF << RTL8373_SPG_PB_ACCESS_CTRL2_PB_CELL_INDEX_OFFSET) + #define RTL8373_SPG_PB_ACCESS_CTRL2_PB_BYTE_INDEX_OFFSET (0) + #define RTL8373_SPG_PB_ACCESS_CTRL2_PB_BYTE_INDEX_MASK (0xFF << RTL8373_SPG_PB_ACCESS_CTRL2_PB_BYTE_INDEX_OFFSET) + +#define RTL8373_SPG_PORT_INDEX_CTRL0_ADDR(port) (0x1C30 + (((port) << 10))) /* port: 0-9 */ + #define RTL8373_SPG_PORT_INDEX_CTRL0_PORTN_INDEX_OFFSET (0) + #define RTL8373_SPG_PORT_INDEX_CTRL0_PORTN_INDEX_MASK (0xFFF << RTL8373_SPG_PORT_INDEX_CTRL0_PORTN_INDEX_OFFSET) + +#define RTL8373_SPG_GLOBAL_INDEX_CTRL0_ADDR(port) (0x757C + (((port) << 2))) /* port: 0-9 */ + #define RTL8373_SPG_GLOBAL_INDEX_CTRL0_PKT_INDEX_OFFSET (0) + #define RTL8373_SPG_GLOBAL_INDEX_CTRL0_PKT_INDEX_MASK (0xFFF << RTL8373_SPG_GLOBAL_INDEX_CTRL0_PKT_INDEX_OFFSET) + +#define RTL8373_SPG_PREAMBLE_LENGTH_CTRL_ADDR(port) (0x121C + (((port) << 8))) /* port: 0-9 */ + #define RTL8373_SPG_PREAMBLE_LENGTH_CTRL_SPG_PREAMBLE_LENGTH_OFFSET (0) + #define RTL8373_SPG_PREAMBLE_LENGTH_CTRL_SPG_PREAMBLE_LENGTH_MASK (0xF << RTL8373_SPG_PREAMBLE_LENGTH_CTRL_SPG_PREAMBLE_LENGTH_OFFSET) + +#define RTL8373_SPG_PREAMBLE_CONTENT_CTRL2_ADDR(port) (0x1220 + (((port) << 8))) /* port: 0-9 */ + #define RTL8373_SPG_PREAMBLE_CONTENT_CTRL2_SPG_PREAMBLE_CONTENT2_OFFSET (0) + #define RTL8373_SPG_PREAMBLE_CONTENT_CTRL2_SPG_PREAMBLE_CONTENT2_MASK (0xFFFF << RTL8373_SPG_PREAMBLE_CONTENT_CTRL2_SPG_PREAMBLE_CONTENT2_OFFSET) + +#define RTL8373_SPG_PREAMBLE_CONTENT_CTRL1_ADDR(port) (0x1224 + (((port) << 8))) /* port: 0-9 */ + #define RTL8373_SPG_PREAMBLE_CONTENT_CTRL1_SPG_PREAMBLE_CONTENT1_OFFSET (0) + #define RTL8373_SPG_PREAMBLE_CONTENT_CTRL1_SPG_PREAMBLE_CONTENT1_MASK (0xFFFFFFFF << RTL8373_SPG_PREAMBLE_CONTENT_CTRL1_SPG_PREAMBLE_CONTENT1_OFFSET) + +#define RTL8373_SPG_PREAMBLE_CONTENT_CTRL0_ADDR(port) (0x1228 + (((port) << 8))) /* port: 0-9 */ + #define RTL8373_SPG_PREAMBLE_CONTENT_CTRL0_SPG_PREAMBLE_CONTENT0_OFFSET (0) + #define RTL8373_SPG_PREAMBLE_CONTENT_CTRL0_SPG_PREAMBLE_CONTENT0_MASK (0xFFFFFFFF << RTL8373_SPG_PREAMBLE_CONTENT_CTRL0_SPG_PREAMBLE_CONTENT0_OFFSET) + +/* + * Feature: Interface + */ +#define RTL8373_I2C_SLV_CTRL_ADDR (0x404) + #define RTL8373_I2C_SLV_CTRL_CFG_SDA_DLY_OFFSET (1) + #define RTL8373_I2C_SLV_CTRL_CFG_SDA_DLY_MASK (0x3F << RTL8373_I2C_SLV_CTRL_CFG_SDA_DLY_OFFSET) + #define RTL8373_I2C_SLV_CTRL_I2C_DATA_ENDIAN_SEL_OFFSET (0) + #define RTL8373_I2C_SLV_CTRL_I2C_DATA_ENDIAN_SEL_MASK (0x1 << RTL8373_I2C_SLV_CTRL_I2C_DATA_ENDIAN_SEL_OFFSET) + +#define RTL8373_MAC_SLV_TIMEOUT_ADDR (0x408) + #define RTL8373_MAC_SLV_TIMEOUT_I2C_TIMEOUT_SET_OFFSET (16) + #define RTL8373_MAC_SLV_TIMEOUT_I2C_TIMEOUT_SET_MASK (0x3FFF << RTL8373_MAC_SLV_TIMEOUT_I2C_TIMEOUT_SET_OFFSET) + #define RTL8373_MAC_SLV_TIMEOUT_I2C_TIMEOUT_FLAG_OFFSET (15) + #define RTL8373_MAC_SLV_TIMEOUT_I2C_TIMEOUT_FLAG_MASK (0x1 << RTL8373_MAC_SLV_TIMEOUT_I2C_TIMEOUT_FLAG_OFFSET) + #define RTL8373_MAC_SLV_TIMEOUT_SPI_TIMEOUT_SET_OFFSET (1) + #define RTL8373_MAC_SLV_TIMEOUT_SPI_TIMEOUT_SET_MASK (0x3FFF << RTL8373_MAC_SLV_TIMEOUT_SPI_TIMEOUT_SET_OFFSET) + #define RTL8373_MAC_SLV_TIMEOUT_SPI_TIMEOUT_FLAG_OFFSET (0) + #define RTL8373_MAC_SLV_TIMEOUT_SPI_TIMEOUT_FLAG_MASK (0x1 << RTL8373_MAC_SLV_TIMEOUT_SPI_TIMEOUT_FLAG_OFFSET) + +#define RTL8373_MAC_IF_CTRL_ADDR (0x40C) + #define RTL8373_MAC_IF_CTRL_DW8051_INDIRECT_EE_EN_OFFSET (3) + #define RTL8373_MAC_IF_CTRL_DW8051_INDIRECT_EE_EN_MASK (0x1 << RTL8373_MAC_IF_CTRL_DW8051_INDIRECT_EE_EN_OFFSET) + #define RTL8373_MAC_IF_CTRL_SPI_SO_REF_OFFSET (2) + #define RTL8373_MAC_IF_CTRL_SPI_SO_REF_MASK (0x1 << RTL8373_MAC_IF_CTRL_SPI_SO_REF_OFFSET) + #define RTL8373_MAC_IF_CTRL_REG_IF_SEL_OFFSET (0) + #define RTL8373_MAC_IF_CTRL_REG_IF_SEL_MASK (0x3 << RTL8373_MAC_IF_CTRL_REG_IF_SEL_OFFSET) + +#define RTL8373_SLV_MDX_CTRL_ADDR (0x410) + #define RTL8373_SLV_MDX_CTRL_CFG_PRMB_SUPP_OFFSET (6) + #define RTL8373_SLV_MDX_CTRL_CFG_PRMB_SUPP_MASK (0x1 << RTL8373_SLV_MDX_CTRL_CFG_PRMB_SUPP_OFFSET) + #define RTL8373_SLV_MDX_CTRL_CFG_SHORT_PRMB_OFFSET (5) + #define RTL8373_SLV_MDX_CTRL_CFG_SHORT_PRMB_MASK (0x1 << RTL8373_SLV_MDX_CTRL_CFG_SHORT_PRMB_OFFSET) + #define RTL8373_SLV_MDX_CTRL_CFG_TA_CHK_EN_OFFSET (4) + #define RTL8373_SLV_MDX_CTRL_CFG_TA_CHK_EN_MASK (0x1 << RTL8373_SLV_MDX_CTRL_CFG_TA_CHK_EN_OFFSET) + #define RTL8373_SLV_MDX_CTRL_CFG_SLV_EDGE_SEL_OFFSET (3) + #define RTL8373_SLV_MDX_CTRL_CFG_SLV_EDGE_SEL_MASK (0x1 << RTL8373_SLV_MDX_CTRL_CFG_SLV_EDGE_SEL_OFFSET) + #define RTL8373_SLV_MDX_CTRL_CFG_SLV_MDIO_DLY_OFFSET (1) + #define RTL8373_SLV_MDX_CTRL_CFG_SLV_MDIO_DLY_MASK (0x3 << RTL8373_SLV_MDX_CTRL_CFG_SLV_MDIO_DLY_OFFSET) + #define RTL8373_SLV_MDX_CTRL_STRP_EN_SLV_MDC_DEG_OFFSET (0) + #define RTL8373_SLV_MDX_CTRL_STRP_EN_SLV_MDC_DEG_MASK (0x1 << RTL8373_SLV_MDX_CTRL_STRP_EN_SLV_MDC_DEG_OFFSET) + +#define RTL8373_I2C_MST_IF_CTRL_ADDR (0x414) + #define RTL8373_I2C_MST_IF_CTRL_CFG_DATA_HOLD_TIME_1_OFFSET (17) + #define RTL8373_I2C_MST_IF_CTRL_CFG_DATA_HOLD_TIME_1_MASK (0x1 << RTL8373_I2C_MST_IF_CTRL_CFG_DATA_HOLD_TIME_1_OFFSET) + #define RTL8373_I2C_MST_IF_CTRL_CFG_SCK_I_DLY_1_OFFSET (13) + #define RTL8373_I2C_MST_IF_CTRL_CFG_SCK_I_DLY_1_MASK (0xF << RTL8373_I2C_MST_IF_CTRL_CFG_SCK_I_DLY_1_OFFSET) + #define RTL8373_I2C_MST_IF_CTRL_CFG_WAIT_SCK_MODE_1_OFFSET (11) + #define RTL8373_I2C_MST_IF_CTRL_CFG_WAIT_SCK_MODE_1_MASK (0x3 << RTL8373_I2C_MST_IF_CTRL_CFG_WAIT_SCK_MODE_1_OFFSET) + #define RTL8373_I2C_MST_IF_CTRL_I2C_OPEN_DRN_SCK_1_OFFSET (6) + #define RTL8373_I2C_MST_IF_CTRL_I2C_OPEN_DRN_SCK_1_MASK (0x1F << RTL8373_I2C_MST_IF_CTRL_I2C_OPEN_DRN_SCK_1_OFFSET) + #define RTL8373_I2C_MST_IF_CTRL_I2C_OPEN_DRN_SDA_1_OFFSET (0) + #define RTL8373_I2C_MST_IF_CTRL_I2C_OPEN_DRN_SDA_1_MASK (0x3F << RTL8373_I2C_MST_IF_CTRL_I2C_OPEN_DRN_SDA_1_OFFSET) + +#define RTL8373_I2C_MST1_CTRL1_ADDR (0x418) + #define RTL8373_I2C_MST1_CTRL1_READ_MODE_OFFSET (22) + #define RTL8373_I2C_MST1_CTRL1_READ_MODE_MASK (0x1 << RTL8373_I2C_MST1_CTRL1_READ_MODE_OFFSET) + #define RTL8373_I2C_MST1_CTRL1_MEM_ADDR_WIDTH_OFFSET (20) + #define RTL8373_I2C_MST1_CTRL1_MEM_ADDR_WIDTH_MASK (0x3 << RTL8373_I2C_MST1_CTRL1_MEM_ADDR_WIDTH_OFFSET) + #define RTL8373_I2C_MST1_CTRL1_DATA_WIDTH_OFFSET (16) + #define RTL8373_I2C_MST1_CTRL1_DATA_WIDTH_MASK (0xF << RTL8373_I2C_MST1_CTRL1_DATA_WIDTH_OFFSET) + #define RTL8373_I2C_MST1_CTRL1_SCL_OUT_SEL_OFFSET (13) + #define RTL8373_I2C_MST1_CTRL1_SCL_OUT_SEL_MASK (0x7 << RTL8373_I2C_MST1_CTRL1_SCL_OUT_SEL_OFFSET) + #define RTL8373_I2C_MST1_CTRL1_SDA_OUT_SEL_OFFSET (10) + #define RTL8373_I2C_MST1_CTRL1_SDA_OUT_SEL_MASK (0x7 << RTL8373_I2C_MST1_CTRL1_SDA_OUT_SEL_OFFSET) + #define RTL8373_I2C_MST1_CTRL1_DEV_ADDR_OFFSET (3) + #define RTL8373_I2C_MST1_CTRL1_DEV_ADDR_MASK (0x7F << RTL8373_I2C_MST1_CTRL1_DEV_ADDR_OFFSET) + #define RTL8373_I2C_MST1_CTRL1_RWOP_OFFSET (2) + #define RTL8373_I2C_MST1_CTRL1_RWOP_MASK (0x1 << RTL8373_I2C_MST1_CTRL1_RWOP_OFFSET) + #define RTL8373_I2C_MST1_CTRL1_I2C_FAIL_OFFSET (1) + #define RTL8373_I2C_MST1_CTRL1_I2C_FAIL_MASK (0x1 << RTL8373_I2C_MST1_CTRL1_I2C_FAIL_OFFSET) + #define RTL8373_I2C_MST1_CTRL1_I2C_TRIG_OFFSET (0) + #define RTL8373_I2C_MST1_CTRL1_I2C_TRIG_MASK (0x1 << RTL8373_I2C_MST1_CTRL1_I2C_TRIG_OFFSET) + +#define RTL8373_I2C_MST1_CTRL2_ADDR (0x41C) + #define RTL8373_I2C_MST1_CTRL2_MST_CODE_OFFSET (16) + #define RTL8373_I2C_MST1_CTRL2_MST_CODE_MASK (0x7 << RTL8373_I2C_MST1_CTRL2_MST_CODE_OFFSET) + #define RTL8373_I2C_MST1_CTRL2_I2C_MST_CODE_OFFSET (15) + #define RTL8373_I2C_MST1_CTRL2_I2C_MST_CODE_MASK (0x1 << RTL8373_I2C_MST1_CTRL2_I2C_MST_CODE_OFFSET) + #define RTL8373_I2C_MST1_CTRL2_I2C_RESET_OFFSET (14) + #define RTL8373_I2C_MST1_CTRL2_I2C_RESET_MASK (0x1 << RTL8373_I2C_MST1_CTRL2_I2C_RESET_OFFSET) + #define RTL8373_I2C_MST1_CTRL2_CHK_ACK_DLY_OFFSET (10) + #define RTL8373_I2C_MST1_CTRL2_CHK_ACK_DLY_MASK (0xF << RTL8373_I2C_MST1_CTRL2_CHK_ACK_DLY_OFFSET) + #define RTL8373_I2C_MST1_CTRL2_DRV_ACK_DLY_OFFSET (6) + #define RTL8373_I2C_MST1_CTRL2_DRV_ACK_DLY_MASK (0xF << RTL8373_I2C_MST1_CTRL2_DRV_ACK_DLY_OFFSET) + #define RTL8373_I2C_MST1_CTRL2_BYTE_TO_BYTE_DLY_OFFSET (4) + #define RTL8373_I2C_MST1_CTRL2_BYTE_TO_BYTE_DLY_MASK (0x3 << RTL8373_I2C_MST1_CTRL2_BYTE_TO_BYTE_DLY_OFFSET) + #define RTL8373_I2C_MST1_CTRL2_TBUF_DELAY_OFFSET (3) + #define RTL8373_I2C_MST1_CTRL2_TBUF_DELAY_MASK (0x1 << RTL8373_I2C_MST1_CTRL2_TBUF_DELAY_OFFSET) + #define RTL8373_I2C_MST1_CTRL2_SCL_FREQ_OFFSET (0) + #define RTL8373_I2C_MST1_CTRL2_SCL_FREQ_MASK (0x3 << RTL8373_I2C_MST1_CTRL2_SCL_FREQ_OFFSET) + +#define RTL8373_I2C_MST1_MEMADDR_CTRL_ADDR (0x420) + #define RTL8373_I2C_MST1_MEMADDR_CTRL_MEM_ADDR_OFFSET (0) + #define RTL8373_I2C_MST1_MEMADDR_CTRL_MEM_ADDR_MASK (0xFFFFFF << RTL8373_I2C_MST1_MEMADDR_CTRL_MEM_ADDR_OFFSET) + +#define RTL8373_I2C_MST1_DATA_CTRL_ADDR(index) (0x424 + (((index >> 2) << 2))) /* index: 0-15 */ + #define RTL8373_I2C_MST1_DATA_CTRL_DATA_OFFSET(index) ((index & 0x3) << 3) + #define RTL8373_I2C_MST1_DATA_CTRL_DATA_MASK(index) (0xFF << RTL8373_I2C_MST1_DATA_CTRL_DATA_OFFSET(index)) + +#define RTL8373_SPI_CTRL0_ADDR (0x434) + #define RTL8373_SPI_CTRL0_SPI_OUT_SEL_OFFSET (20) + #define RTL8373_SPI_CTRL0_SPI_OUT_SEL_MASK (0x1 << RTL8373_SPI_CTRL0_SPI_OUT_SEL_OFFSET) + #define RTL8373_SPI_CTRL0_SPI_RX_DLY_OFFSET (17) + #define RTL8373_SPI_CTRL0_SPI_RX_DLY_MASK (0x7 << RTL8373_SPI_CTRL0_SPI_RX_DLY_OFFSET) + #define RTL8373_SPI_CTRL0_SPI_CLK_DLY_OFFSET (14) + #define RTL8373_SPI_CTRL0_SPI_CLK_DLY_MASK (0x7 << RTL8373_SPI_CTRL0_SPI_CLK_DLY_OFFSET) + #define RTL8373_SPI_CTRL0_SPI_TX_DLY_OFFSET (11) + #define RTL8373_SPI_CTRL0_SPI_TX_DLY_MASK (0x7 << RTL8373_SPI_CTRL0_SPI_TX_DLY_OFFSET) + #define RTL8373_SPI_CTRL0_SPI_CLK_DIV_OFFSET (8) + #define RTL8373_SPI_CTRL0_SPI_CLK_DIV_MASK (0x7 << RTL8373_SPI_CTRL0_SPI_CLK_DIV_OFFSET) + #define RTL8373_SPI_CTRL0_SPI_CPHA_OFFSET (7) + #define RTL8373_SPI_CTRL0_SPI_CPHA_MASK (0x1 << RTL8373_SPI_CTRL0_SPI_CPHA_OFFSET) + #define RTL8373_SPI_CTRL0_SPI_CPOL_OFFSET (6) + #define RTL8373_SPI_CTRL0_SPI_CPOL_MASK (0x1 << RTL8373_SPI_CTRL0_SPI_CPOL_OFFSET) + #define RTL8373_SPI_CTRL0_SPI_TSLCH_OFFSET (3) + #define RTL8373_SPI_CTRL0_SPI_TSLCH_MASK (0x7 << RTL8373_SPI_CTRL0_SPI_TSLCH_OFFSET) + #define RTL8373_SPI_CTRL0_SPI_TCHSH_OFFSET (0) + #define RTL8373_SPI_CTRL0_SPI_TCHSH_MASK (0x7 << RTL8373_SPI_CTRL0_SPI_TCHSH_OFFSET) + +#define RTL8373_SPI_CTRL1_ADDR (0x438) + #define RTL8373_SPI_CTRL1_ADDR_WIDTH_OFFSET (20) + #define RTL8373_SPI_CTRL1_ADDR_WIDTH_MASK (0x7 << RTL8373_SPI_CTRL1_ADDR_WIDTH_OFFSET) + #define RTL8373_SPI_CTRL1_DATA_WIDTH_OFFSET (11) + #define RTL8373_SPI_CTRL1_DATA_WIDTH_MASK (0x1FF << RTL8373_SPI_CTRL1_DATA_WIDTH_OFFSET) + #define RTL8373_SPI_CTRL1_BYPASS_DATA_BYTE_OFFSET (10) + #define RTL8373_SPI_CTRL1_BYPASS_DATA_BYTE_MASK (0x1 << RTL8373_SPI_CTRL1_BYPASS_DATA_BYTE_OFFSET) + #define RTL8373_SPI_CTRL1_SPI_CMD_TYPE_OFFSET (9) + #define RTL8373_SPI_CTRL1_SPI_CMD_TYPE_MASK (0x1 << RTL8373_SPI_CTRL1_SPI_CMD_TYPE_OFFSET) + #define RTL8373_SPI_CTRL1_SPI_CMD_OFFSET (1) + #define RTL8373_SPI_CTRL1_SPI_CMD_MASK (0xFF << RTL8373_SPI_CTRL1_SPI_CMD_OFFSET) + #define RTL8373_SPI_CTRL1_SPI_TRIG_OFFSET (0) + #define RTL8373_SPI_CTRL1_SPI_TRIG_MASK (0x1 << RTL8373_SPI_CTRL1_SPI_TRIG_OFFSET) + +#define RTL8373_SPI_DATA_ADDR(index) (0x4F0 + (((index) << 2))) /* index: 0-127 */ + #define RTL8373_SPI_DATA_SPI_DATA_OFFSET (0) + #define RTL8373_SPI_DATA_SPI_DATA_MASK (0xFFFFFFFF << RTL8373_SPI_DATA_SPI_DATA_OFFSET) + +#define RTL8373_SPI_ADDR_ADDR (0x43C) + #define RTL8373_SPI_ADDR_SPI_ADDR_OFFSET (0) + #define RTL8373_SPI_ADDR_SPI_ADDR_MASK (0xFFFFFFFF << RTL8373_SPI_ADDR_SPI_ADDR_OFFSET) + +#define RTL8373_GPIO_OUT0_ADDR (0x3C) + #define RTL8373_GPIO_OUT0_GPIO_OUT_31_0_OFFSET (0) + #define RTL8373_GPIO_OUT0_GPIO_OUT_31_0_MASK (0xFFFFFFFF << RTL8373_GPIO_OUT0_GPIO_OUT_31_0_OFFSET) + +#define RTL8373_GPIO_OUT1_ADDR (0x40) + #define RTL8373_GPIO_OUT1_GPIO_OUT_62_32_OFFSET (0) + #define RTL8373_GPIO_OUT1_GPIO_OUT_62_32_MASK (0x7FFFFFFF << RTL8373_GPIO_OUT1_GPIO_OUT_62_32_OFFSET) + +#define RTL8373_GPIO_IN0_ADDR (0x44) + #define RTL8373_GPIO_IN0_GPIO_IN_31_0_OFFSET (0) + #define RTL8373_GPIO_IN0_GPIO_IN_31_0_MASK (0xFFFFFFFF << RTL8373_GPIO_IN0_GPIO_IN_31_0_OFFSET) + +#define RTL8373_GPIO_IN1_ADDR (0x48) + #define RTL8373_GPIO_IN1_GPIO_IN_62_32_OFFSET (0) + #define RTL8373_GPIO_IN1_GPIO_IN_62_32_MASK (0x7FFFFFFF << RTL8373_GPIO_IN1_GPIO_IN_62_32_OFFSET) + +#define RTL8373_GPIO_OE0_ADDR (0x4C) + #define RTL8373_GPIO_OE0_GPIO_OE_31_0_OFFSET (0) + #define RTL8373_GPIO_OE0_GPIO_OE_31_0_MASK (0xFFFFFFFF << RTL8373_GPIO_OE0_GPIO_OE_31_0_OFFSET) + +#define RTL8373_GPIO_OE1_ADDR (0x50) + #define RTL8373_GPIO_OE1_GPIO_OE_62_32_OFFSET (0) + #define RTL8373_GPIO_OE1_GPIO_OE_62_32_MASK (0x7FFFFFFF << RTL8373_GPIO_OE1_GPIO_OE_62_32_OFFSET) + +#define RTL8373_GPIO_IMODE_54_52_ADDR (0x54) + #define RTL8373_GPIO_IMODE_54_52_IMODE_GPIO_54_OFFSET (4) + #define RTL8373_GPIO_IMODE_54_52_IMODE_GPIO_54_MASK (0x3 << RTL8373_GPIO_IMODE_54_52_IMODE_GPIO_54_OFFSET) + #define RTL8373_GPIO_IMODE_54_52_IMODE_GPIO_53_OFFSET (2) + #define RTL8373_GPIO_IMODE_54_52_IMODE_GPIO_53_MASK (0x3 << RTL8373_GPIO_IMODE_54_52_IMODE_GPIO_53_OFFSET) + #define RTL8373_GPIO_IMODE_54_52_IMODE_GPIO_52_OFFSET (0) + #define RTL8373_GPIO_IMODE_54_52_IMODE_GPIO_52_MASK (0x3 << RTL8373_GPIO_IMODE_54_52_IMODE_GPIO_52_OFFSET) + +#define RTL8373_INI_MODE_ADDR (0x58) + #define RTL8373_INI_MODE_INI_MODE_OFFSET (0) + #define RTL8373_INI_MODE_INI_MODE_MASK (0x3 << RTL8373_INI_MODE_INI_MODE_OFFSET) + +#define RTL8373_PWM_CTRL_ADDR (0x5C) + #define RTL8373_PWM_CTRL_PWM_OE_OFFSET (11) + #define RTL8373_PWM_CTRL_PWM_OE_MASK (0x1 << RTL8373_PWM_CTRL_PWM_OE_OFFSET) + #define RTL8373_PWM_CTRL_PWM_DUTY_RATIO_OFFSET (3) + #define RTL8373_PWM_CTRL_PWM_DUTY_RATIO_MASK (0xFF << RTL8373_PWM_CTRL_PWM_DUTY_RATIO_OFFSET) + #define RTL8373_PWM_CTRL_PWM_CLK_SEL_OFFSET (0) + #define RTL8373_PWM_CTRL_PWM_CLK_SEL_MASK (0x7 << RTL8373_PWM_CTRL_PWM_CLK_SEL_OFFSET) + +#define RTL8373_REGIF_TIMEOUT_INFO_ADDR (0x440) + #define RTL8373_REGIF_TIMEOUT_INFO_REGIF_TIME_OUT_OFFSET (19) + #define RTL8373_REGIF_TIMEOUT_INFO_REGIF_TIME_OUT_MASK (0x1 << RTL8373_REGIF_TIMEOUT_INFO_REGIF_TIME_OUT_OFFSET) + #define RTL8373_REGIF_TIMEOUT_INFO_REGIF_AC_SOUR_OFFSET (16) + #define RTL8373_REGIF_TIMEOUT_INFO_REGIF_AC_SOUR_MASK (0x7 << RTL8373_REGIF_TIMEOUT_INFO_REGIF_AC_SOUR_OFFSET) + #define RTL8373_REGIF_TIMEOUT_INFO_REGIF_AC_ADDR_OFFSET (0) + #define RTL8373_REGIF_TIMEOUT_INFO_REGIF_AC_ADDR_MASK (0xFFFF << RTL8373_REGIF_TIMEOUT_INFO_REGIF_AC_ADDR_OFFSET) + +/* + * Feature: TM + */ +#define RTL8373_TM0_CTRL0_ADDR (0x2D0) + #define RTL8373_TM0_CTRL0_DUMY_TM0_CTRL0_OFFSET (0) + #define RTL8373_TM0_CTRL0_DUMY_TM0_CTRL0_MASK (0xFFFFFFFF << RTL8373_TM0_CTRL0_DUMY_TM0_CTRL0_OFFSET) + +#define RTL8373_TM0_CTRL1_ADDR (0x2D4) + #define RTL8373_TM0_CTRL1_DUMY_TM0_CTRL1_OFFSET (0) + #define RTL8373_TM0_CTRL1_DUMY_TM0_CTRL1_MASK (0xFFFFFFFF << RTL8373_TM0_CTRL1_DUMY_TM0_CTRL1_OFFSET) + +#define RTL8373_TM0_CTRL2_ADDR (0x2D8) + #define RTL8373_TM0_CTRL2_REG_EN_LATCH_OFFSET (2) + #define RTL8373_TM0_CTRL2_REG_EN_LATCH_MASK (0x1 << RTL8373_TM0_CTRL2_REG_EN_LATCH_OFFSET) + +#define RTL8373_TM0_CTRL3_ADDR (0x2DC) + #define RTL8373_TM0_CTRL3_TM_HIGHCMP_EN_OFFSET (19) + #define RTL8373_TM0_CTRL3_TM_HIGHCMP_EN_MASK (0x1 << RTL8373_TM0_CTRL3_TM_HIGHCMP_EN_OFFSET) + #define RTL8373_TM0_CTRL3_TM_HIGH_THR_OFFSET (10) + #define RTL8373_TM0_CTRL3_TM_HIGH_THR_MASK (0x1FF << RTL8373_TM0_CTRL3_TM_HIGH_THR_OFFSET) + #define RTL8373_TM0_CTRL3_TM_LOWCMP_EN_OFFSET (9) + #define RTL8373_TM0_CTRL3_TM_LOWCMP_EN_MASK (0x1 << RTL8373_TM0_CTRL3_TM_LOWCMP_EN_OFFSET) + #define RTL8373_TM0_CTRL3_TM_LOW_THR_OFFSET (0) + #define RTL8373_TM0_CTRL3_TM_LOW_THR_MASK (0x1FF << RTL8373_TM0_CTRL3_TM_LOW_THR_OFFSET) + +#define RTL8373_TM0_RESULT0_ADDR (0x2E0) + #define RTL8373_TM0_RESULT0_TM_OUT_2_0_OFFSET (16) + #define RTL8373_TM0_RESULT0_TM_OUT_2_0_MASK (0x7 << RTL8373_TM0_RESULT0_TM_OUT_2_0_OFFSET) + #define RTL8373_TM0_RESULT0_TM_OUT_18_3_OFFSET (0) + #define RTL8373_TM0_RESULT0_TM_OUT_18_3_MASK (0xFFFF << RTL8373_TM0_RESULT0_TM_OUT_18_3_OFFSET) + +#define RTL8373_TM0_RESULT1_ADDR (0x2E4) + #define RTL8373_TM0_RESULT1_TM_ADC_OUT_OFFSET (0) + #define RTL8373_TM0_RESULT1_TM_ADC_OUT_MASK (0x3FFFFF << RTL8373_TM0_RESULT1_TM_ADC_OUT_OFFSET) + +#define RTL8373_TM0_RESULT2_ADDR (0x2E8) + #define RTL8373_TM0_RESULT2_EN_TM_MAX_OFFSET (19) + #define RTL8373_TM0_RESULT2_EN_TM_MAX_MASK (0x1 << RTL8373_TM0_RESULT2_EN_TM_MAX_OFFSET) + #define RTL8373_TM0_RESULT2_TM_MAX_2_0_OFFSET (16) + #define RTL8373_TM0_RESULT2_TM_MAX_2_0_MASK (0x7 << RTL8373_TM0_RESULT2_TM_MAX_2_0_OFFSET) + #define RTL8373_TM0_RESULT2_TM_MAX_18_3_OFFSET (0) + #define RTL8373_TM0_RESULT2_TM_MAX_18_3_MASK (0xFFFF << RTL8373_TM0_RESULT2_TM_MAX_18_3_OFFSET) + +#define RTL8373_TM0_RESULT3_ADDR (0x2EC) + #define RTL8373_TM0_RESULT3_EN_TM_MIN_OFFSET (19) + #define RTL8373_TM0_RESULT3_EN_TM_MIN_MASK (0x1 << RTL8373_TM0_RESULT3_EN_TM_MIN_OFFSET) + #define RTL8373_TM0_RESULT3_TM_MIN_2_0_OFFSET (16) + #define RTL8373_TM0_RESULT3_TM_MIN_2_0_MASK (0x7 << RTL8373_TM0_RESULT3_TM_MIN_2_0_OFFSET) + #define RTL8373_TM0_RESULT3_TM_MIN_18_3_OFFSET (0) + #define RTL8373_TM0_RESULT3_TM_MIN_18_3_MASK (0xFFFF << RTL8373_TM0_RESULT3_TM_MIN_18_3_OFFSET) + +#define RTL8373_TM0_RESULT4_ADDR (0x2F0) + #define RTL8373_TM0_RESULT4_TEMP_OUT_POWERON_2_0_OFFSET (16) + #define RTL8373_TM0_RESULT4_TEMP_OUT_POWERON_2_0_MASK (0x7 << RTL8373_TM0_RESULT4_TEMP_OUT_POWERON_2_0_OFFSET) + #define RTL8373_TM0_RESULT4_TEMP_OUT_POWERON_18_3_OFFSET (0) + #define RTL8373_TM0_RESULT4_TEMP_OUT_POWERON_18_3_MASK (0xFFFF << RTL8373_TM0_RESULT4_TEMP_OUT_POWERON_18_3_OFFSET) + +#define RTL8373_TM1_CTRL0_ADDR (0x330) + #define RTL8373_TM1_CTRL0_REG_A_OFFSET (0) + #define RTL8373_TM1_CTRL0_REG_A_MASK (0x1FFFFFFF << RTL8373_TM1_CTRL0_REG_A_OFFSET) + +#define RTL8373_TM1_CTRL1_ADDR (0x334) + #define RTL8373_TM1_CTRL1_REG_B_OFFSET (0) + #define RTL8373_TM1_CTRL1_REG_B_MASK (0x3FFFFF << RTL8373_TM1_CTRL1_REG_B_OFFSET) + +#define RTL8373_TM1_CTRL2_ADDR (0x338) + #define RTL8373_TM1_CTRL2_RSTB_TM_OFFSET (14) + #define RTL8373_TM1_CTRL2_RSTB_TM_MASK (0x1 << RTL8373_TM1_CTRL2_RSTB_TM_OFFSET) + #define RTL8373_TM1_CTRL2_REG_CHOPFREQSEL_OFFSET (10) + #define RTL8373_TM1_CTRL2_REG_CHOPFREQSEL_MASK (0xF << RTL8373_TM1_CTRL2_REG_CHOPFREQSEL_OFFSET) + #define RTL8373_TM1_CTRL2_REG_OSR_OFFSET (7) + #define RTL8373_TM1_CTRL2_REG_OSR_MASK (0x7 << RTL8373_TM1_CTRL2_REG_OSR_OFFSET) + #define RTL8373_TM1_CTRL2_REG_HOLD_EN_OFFSET (6) + #define RTL8373_TM1_CTRL2_REG_HOLD_EN_MASK (0x1 << RTL8373_TM1_CTRL2_REG_HOLD_EN_OFFSET) + #define RTL8373_TM1_CTRL2_REG_HOLD_DLY_OFFSET (4) + #define RTL8373_TM1_CTRL2_REG_HOLD_DLY_MASK (0x3 << RTL8373_TM1_CTRL2_REG_HOLD_DLY_OFFSET) + #define RTL8373_TM1_CTRL2_REG_CHOPEN_OFFSET (3) + #define RTL8373_TM1_CTRL2_REG_CHOPEN_MASK (0x1 << RTL8373_TM1_CTRL2_REG_CHOPEN_OFFSET) + #define RTL8373_TM1_CTRL2_REG_EN_LATCH_OFFSET (2) + #define RTL8373_TM1_CTRL2_REG_EN_LATCH_MASK (0x1 << RTL8373_TM1_CTRL2_REG_EN_LATCH_OFFSET) + #define RTL8373_TM1_CTRL2_REG_BIASDEM_EN_OFFSET (1) + #define RTL8373_TM1_CTRL2_REG_BIASDEM_EN_MASK (0x1 << RTL8373_TM1_CTRL2_REG_BIASDEM_EN_OFFSET) + #define RTL8373_TM1_CTRL2_REG_ADCCKSEL_OFFSET (0) + #define RTL8373_TM1_CTRL2_REG_ADCCKSEL_MASK (0x1 << RTL8373_TM1_CTRL2_REG_ADCCKSEL_OFFSET) + +#define RTL8373_TM1_CTRL3_ADDR (0x33C) + #define RTL8373_TM1_CTRL3_TM_HIGHCMP_EN_OFFSET (19) + #define RTL8373_TM1_CTRL3_TM_HIGHCMP_EN_MASK (0x1 << RTL8373_TM1_CTRL3_TM_HIGHCMP_EN_OFFSET) + #define RTL8373_TM1_CTRL3_TM_HIGH_THR_OFFSET (10) + #define RTL8373_TM1_CTRL3_TM_HIGH_THR_MASK (0x1FF << RTL8373_TM1_CTRL3_TM_HIGH_THR_OFFSET) + #define RTL8373_TM1_CTRL3_TM_LOWCMP_EN_OFFSET (9) + #define RTL8373_TM1_CTRL3_TM_LOWCMP_EN_MASK (0x1 << RTL8373_TM1_CTRL3_TM_LOWCMP_EN_OFFSET) + #define RTL8373_TM1_CTRL3_TM_LOW_THR_OFFSET (0) + #define RTL8373_TM1_CTRL3_TM_LOW_THR_MASK (0x1FF << RTL8373_TM1_CTRL3_TM_LOW_THR_OFFSET) + +#define RTL8373_TM1_RESULT0_ADDR (0x340) + #define RTL8373_TM1_RESULT0_TM_OUT_2_0_OFFSET (16) + #define RTL8373_TM1_RESULT0_TM_OUT_2_0_MASK (0x7 << RTL8373_TM1_RESULT0_TM_OUT_2_0_OFFSET) + #define RTL8373_TM1_RESULT0_TM_OUT_18_3_OFFSET (0) + #define RTL8373_TM1_RESULT0_TM_OUT_18_3_MASK (0xFFFF << RTL8373_TM1_RESULT0_TM_OUT_18_3_OFFSET) + +#define RTL8373_TM1_RESULT1_ADDR (0x344) + #define RTL8373_TM1_RESULT1_TM_ADC_OUT_OFFSET (0) + #define RTL8373_TM1_RESULT1_TM_ADC_OUT_MASK (0x3FFFFF << RTL8373_TM1_RESULT1_TM_ADC_OUT_OFFSET) + +#define RTL8373_TM1_RESULT2_ADDR (0x348) + #define RTL8373_TM1_RESULT2_EN_TM_MAX_OFFSET (19) + #define RTL8373_TM1_RESULT2_EN_TM_MAX_MASK (0x1 << RTL8373_TM1_RESULT2_EN_TM_MAX_OFFSET) + #define RTL8373_TM1_RESULT2_TM_MAX_2_0_OFFSET (16) + #define RTL8373_TM1_RESULT2_TM_MAX_2_0_MASK (0x7 << RTL8373_TM1_RESULT2_TM_MAX_2_0_OFFSET) + #define RTL8373_TM1_RESULT2_TM_MAX_18_3_OFFSET (0) + #define RTL8373_TM1_RESULT2_TM_MAX_18_3_MASK (0xFFFF << RTL8373_TM1_RESULT2_TM_MAX_18_3_OFFSET) + +#define RTL8373_TM1_RESULT3_ADDR (0x34C) + #define RTL8373_TM1_RESULT3_EN_TM_MIN_OFFSET (19) + #define RTL8373_TM1_RESULT3_EN_TM_MIN_MASK (0x1 << RTL8373_TM1_RESULT3_EN_TM_MIN_OFFSET) + #define RTL8373_TM1_RESULT3_TM_MIN_2_0_OFFSET (16) + #define RTL8373_TM1_RESULT3_TM_MIN_2_0_MASK (0x7 << RTL8373_TM1_RESULT3_TM_MIN_2_0_OFFSET) + #define RTL8373_TM1_RESULT3_TM_MIN_18_3_OFFSET (0) + #define RTL8373_TM1_RESULT3_TM_MIN_18_3_MASK (0xFFFF << RTL8373_TM1_RESULT3_TM_MIN_18_3_OFFSET) + +#define RTL8373_TM1_RESULT4_ADDR (0x350) + #define RTL8373_TM1_RESULT4_TEMP_OUT_POWERON_2_0_OFFSET (16) + #define RTL8373_TM1_RESULT4_TEMP_OUT_POWERON_2_0_MASK (0x7 << RTL8373_TM1_RESULT4_TEMP_OUT_POWERON_2_0_OFFSET) + #define RTL8373_TM1_RESULT4_TEMP_OUT_POWERON_18_3_OFFSET (0) + #define RTL8373_TM1_RESULT4_TEMP_OUT_POWERON_18_3_MASK (0xFFFF << RTL8373_TM1_RESULT4_TEMP_OUT_POWERON_18_3_OFFSET) + +/* + * Feature: EFUSE&EEPROM + */ +#define RTL8373_EFUSE_ACCESS_EN_ADDR (0x7FE0) + #define RTL8373_EFUSE_ACCESS_EN_EFUSE_ACCESS_EN_OFFSET (0) + #define RTL8373_EFUSE_ACCESS_EN_EFUSE_ACCESS_EN_MASK (0xFFFF << RTL8373_EFUSE_ACCESS_EN_EFUSE_ACCESS_EN_OFFSET) + +#define RTL8373_EFUSE_AUTOLOAD_CTRL_ADDR (0x7FE4) + #define RTL8373_EFUSE_AUTOLOAD_CTRL_EFUSE_AUTOLOAD_TIMER_OFFSET (12) + #define RTL8373_EFUSE_AUTOLOAD_CTRL_EFUSE_AUTOLOAD_TIMER_MASK (0xFFFFF << RTL8373_EFUSE_AUTOLOAD_CTRL_EFUSE_AUTOLOAD_TIMER_OFFSET) + #define RTL8373_EFUSE_AUTOLOAD_CTRL_EFUSE_AUTOLOAD_CNT_OFFSET (1) + #define RTL8373_EFUSE_AUTOLOAD_CTRL_EFUSE_AUTOLOAD_CNT_MASK (0x7FF << RTL8373_EFUSE_AUTOLOAD_CTRL_EFUSE_AUTOLOAD_CNT_OFFSET) + #define RTL8373_EFUSE_AUTOLOAD_CTRL_EFUSE_RE_AUTOLOAD_OFFSET (0) + #define RTL8373_EFUSE_AUTOLOAD_CTRL_EFUSE_RE_AUTOLOAD_MASK (0x1 << RTL8373_EFUSE_AUTOLOAD_CTRL_EFUSE_RE_AUTOLOAD_OFFSET) + +#define RTL8373_EFUSE_ACCESS_CTRL_ADDR (0x7FE8) + #define RTL8373_EFUSE_ACCESS_CTRL_EFUSE_MODE_OFFSET (12) + #define RTL8373_EFUSE_ACCESS_CTRL_EFUSE_MODE_MASK (0xF << RTL8373_EFUSE_ACCESS_CTRL_EFUSE_MODE_OFFSET) + #define RTL8373_EFUSE_ACCESS_CTRL_EFUSE_CMD_OFFSET (11) + #define RTL8373_EFUSE_ACCESS_CTRL_EFUSE_CMD_MASK (0x1 << RTL8373_EFUSE_ACCESS_CTRL_EFUSE_CMD_OFFSET) + #define RTL8373_EFUSE_ACCESS_CTRL_EFUSE_ADDR_OFFSET (0) + #define RTL8373_EFUSE_ACCESS_CTRL_EFUSE_ADDR_MASK (0x7FF << RTL8373_EFUSE_ACCESS_CTRL_EFUSE_ADDR_OFFSET) + +#define RTL8373_EFUSE_WDATA_CTRL_ADDR (0x7FEC) + #define RTL8373_EFUSE_WDATA_CTRL_EFUSE_WDATA_OFFSET (0) + #define RTL8373_EFUSE_WDATA_CTRL_EFUSE_WDATA_MASK (0xFF << RTL8373_EFUSE_WDATA_CTRL_EFUSE_WDATA_OFFSET) + +#define RTL8373_EFUSE_RDATA_CTRL_ADDR (0x7FF0) + #define RTL8373_EFUSE_RDATA_CTRL_EFUSE_RDATA_OFFSET (0) + #define RTL8373_EFUSE_RDATA_CTRL_EFUSE_RDATA_MASK (0xFF << RTL8373_EFUSE_RDATA_CTRL_EFUSE_RDATA_OFFSET) + +#define RTL8373_EFUSE_CP_MISC_ADDR (0x7FF4) + #define RTL8373_EFUSE_CP_MISC_EFUSE_CP_CHK_OFFSET (2) + #define RTL8373_EFUSE_CP_MISC_EFUSE_CP_CHK_MASK (0x1 << RTL8373_EFUSE_CP_MISC_EFUSE_CP_CHK_OFFSET) + #define RTL8373_EFUSE_CP_MISC_EFUSE_REPAIR_CHK_OFFSET (0) + #define RTL8373_EFUSE_CP_MISC_EFUSE_REPAIR_CHK_MASK (0x3 << RTL8373_EFUSE_CP_MISC_EFUSE_REPAIR_CHK_OFFSET) + +#define RTL8373_EFUSE_MARGIN_RD_CFG_ADDR (0x7FF8) + #define RTL8373_EFUSE_MARGIN_RD_CFG_EFUSE_MARGIN_RD_ERR_CNT_OFFSET (16) + #define RTL8373_EFUSE_MARGIN_RD_CFG_EFUSE_MARGIN_RD_ERR_CNT_MASK (0xFFF << RTL8373_EFUSE_MARGIN_RD_CFG_EFUSE_MARGIN_RD_ERR_CNT_OFFSET) + #define RTL8373_EFUSE_MARGIN_RD_CFG_EFUSE_MARGIN_RD_END_ADR_OFFSET (0) + #define RTL8373_EFUSE_MARGIN_RD_CFG_EFUSE_MARGIN_RD_END_ADR_MASK (0x7FF << RTL8373_EFUSE_MARGIN_RD_CFG_EFUSE_MARGIN_RD_END_ADR_OFFSET) + +#define RTL8373_EFUSE_MARGIN_RD_ERR_1_ADDR (0x7FFC) + #define RTL8373_EFUSE_MARGIN_RD_ERR_1_EFUSE_MARGIN_RD_ERR_DAT1_OFFSET (16) + #define RTL8373_EFUSE_MARGIN_RD_ERR_1_EFUSE_MARGIN_RD_ERR_DAT1_MASK (0xFF << RTL8373_EFUSE_MARGIN_RD_ERR_1_EFUSE_MARGIN_RD_ERR_DAT1_OFFSET) + #define RTL8373_EFUSE_MARGIN_RD_ERR_1_EFUSE_MARGIN_RD_ERR_ADR1_OFFSET (0) + #define RTL8373_EFUSE_MARGIN_RD_ERR_1_EFUSE_MARGIN_RD_ERR_ADR1_MASK (0x7FF << RTL8373_EFUSE_MARGIN_RD_ERR_1_EFUSE_MARGIN_RD_ERR_ADR1_OFFSET) + +#define RTL8373_EFUSE_MARGIN_RD_ERR_2_ADDR (0x8000) + #define RTL8373_EFUSE_MARGIN_RD_ERR_2_EFUSE_MARGIN_RD_ERR_DAT2_OFFSET (16) + #define RTL8373_EFUSE_MARGIN_RD_ERR_2_EFUSE_MARGIN_RD_ERR_DAT2_MASK (0xFF << RTL8373_EFUSE_MARGIN_RD_ERR_2_EFUSE_MARGIN_RD_ERR_DAT2_OFFSET) + #define RTL8373_EFUSE_MARGIN_RD_ERR_2_EFUSE_MARGIN_RD_ERR_ADR2_OFFSET (0) + #define RTL8373_EFUSE_MARGIN_RD_ERR_2_EFUSE_MARGIN_RD_ERR_ADR2_MASK (0x7FF << RTL8373_EFUSE_MARGIN_RD_ERR_2_EFUSE_MARGIN_RD_ERR_ADR2_OFFSET) + +#define RTL8373_EFUSE_FREQ_SEL_ADDR (0x8004) + #define RTL8373_EFUSE_FREQ_SEL_EFUSE_FREQ_SEL_OFFSET (0) + #define RTL8373_EFUSE_FREQ_SEL_EFUSE_FREQ_SEL_MASK (0x1 << RTL8373_EFUSE_FREQ_SEL_EFUSE_FREQ_SEL_OFFSET) + +#define RTL8373_EFUSE_MASS_OPERATION_CFG_ADDR (0x8008) + #define RTL8373_EFUSE_MASS_OPERATION_CFG_EFUSE_COMP_ERR_CNT_OFFSET (16) + #define RTL8373_EFUSE_MASS_OPERATION_CFG_EFUSE_COMP_ERR_CNT_MASK (0xFFF << RTL8373_EFUSE_MASS_OPERATION_CFG_EFUSE_COMP_ERR_CNT_OFFSET) + #define RTL8373_EFUSE_MASS_OPERATION_CFG_EFUSE_MASS_OP_END_ADR_OFFSET (0) + #define RTL8373_EFUSE_MASS_OPERATION_CFG_EFUSE_MASS_OP_END_ADR_MASK (0x7FF << RTL8373_EFUSE_MASS_OPERATION_CFG_EFUSE_MASS_OP_END_ADR_OFFSET) + +#define RTL8373_EFUSE_MASS_COMP_ERR_1_ADDR (0x800C) + #define RTL8373_EFUSE_MASS_COMP_ERR_1_EFUSE_MASS_COMP_ERR_DAT1_OFFSET (16) + #define RTL8373_EFUSE_MASS_COMP_ERR_1_EFUSE_MASS_COMP_ERR_DAT1_MASK (0xFF << RTL8373_EFUSE_MASS_COMP_ERR_1_EFUSE_MASS_COMP_ERR_DAT1_OFFSET) + #define RTL8373_EFUSE_MASS_COMP_ERR_1_EFUSE_MASS_COMP_ERR_ADR1_OFFSET (0) + #define RTL8373_EFUSE_MASS_COMP_ERR_1_EFUSE_MASS_COMP_ERR_ADR1_MASK (0x7FF << RTL8373_EFUSE_MASS_COMP_ERR_1_EFUSE_MASS_COMP_ERR_ADR1_OFFSET) + +#define RTL8373_EFUSE_MASS_COMP_ERR_2_ADDR (0x8010) + #define RTL8373_EFUSE_MASS_COMP_ERR_2_EFUSE_MASS_COMP_ERR_DAT2_OFFSET (16) + #define RTL8373_EFUSE_MASS_COMP_ERR_2_EFUSE_MASS_COMP_ERR_DAT2_MASK (0xFF << RTL8373_EFUSE_MASS_COMP_ERR_2_EFUSE_MASS_COMP_ERR_DAT2_OFFSET) + #define RTL8373_EFUSE_MASS_COMP_ERR_2_EFUSE_MASS_COMP_ERR_ADR2_OFFSET (0) + #define RTL8373_EFUSE_MASS_COMP_ERR_2_EFUSE_MASS_COMP_ERR_ADR2_MASK (0x7FF << RTL8373_EFUSE_MASS_COMP_ERR_2_EFUSE_MASS_COMP_ERR_ADR2_OFFSET) + +#define RTL8373_EFUSE_MASS_DATA_REG_ADDR(index) (0x8014 + (((index) << 2))) /* index: 0-31 */ + #define RTL8373_EFUSE_MASS_DATA_REG_EFUSE_MASS_DATA_OFFSET (0) + #define RTL8373_EFUSE_MASS_DATA_REG_EFUSE_MASS_DATA_MASK (0xFFFFFFFF << RTL8373_EFUSE_MASS_DATA_REG_EFUSE_MASS_DATA_OFFSET) + +#define RTL8373_MAC_EEPROM_DOWN_LOAD_FREQ_ADDR (0x5F20) + #define RTL8373_MAC_EEPROM_DOWN_LOAD_FREQ_SCK_FREQ_SEL_OFFSET (0) + #define RTL8373_MAC_EEPROM_DOWN_LOAD_FREQ_SCK_FREQ_SEL_MASK (0x3 << RTL8373_MAC_EEPROM_DOWN_LOAD_FREQ_SCK_FREQ_SEL_OFFSET) + +#define RTL8373_MAC_EEPROM_DOWN_LOAD_STS_ADDR (0x5F24) + #define RTL8373_MAC_EEPROM_DOWN_LOAD_STS_EEPROM_AUTO_LOAD_LEN_OFFSET (16) + #define RTL8373_MAC_EEPROM_DOWN_LOAD_STS_EEPROM_AUTO_LOAD_LEN_MASK (0xFFFF << RTL8373_MAC_EEPROM_DOWN_LOAD_STS_EEPROM_AUTO_LOAD_LEN_OFFSET) + #define RTL8373_MAC_EEPROM_DOWN_LOAD_STS_EEPROM_VALID_FAIL_OFFSET (2) + #define RTL8373_MAC_EEPROM_DOWN_LOAD_STS_EEPROM_VALID_FAIL_MASK (0x1 << RTL8373_MAC_EEPROM_DOWN_LOAD_STS_EEPROM_VALID_FAIL_OFFSET) + #define RTL8373_MAC_EEPROM_DOWN_LOAD_STS_EEPROM_COMPL_OFFSET (1) + #define RTL8373_MAC_EEPROM_DOWN_LOAD_STS_EEPROM_COMPL_MASK (0x1 << RTL8373_MAC_EEPROM_DOWN_LOAD_STS_EEPROM_COMPL_OFFSET) + #define RTL8373_MAC_EEPROM_DOWN_LOAD_STS_NOEEPROM_OFFSET (0) + #define RTL8373_MAC_EEPROM_DOWN_LOAD_STS_NOEEPROM_MASK (0x1 << RTL8373_MAC_EEPROM_DOWN_LOAD_STS_NOEEPROM_OFFSET) + +#define RTL8373_EEPROM_VER_INFO_ADDR (0x5F28) + #define RTL8373_EEPROM_VER_INFO_EEPROM_CODE_VER_OFFSET (24) + #define RTL8373_EEPROM_VER_INFO_EEPROM_CODE_VER_MASK (0xFF << RTL8373_EEPROM_VER_INFO_EEPROM_CODE_VER_OFFSET) + #define RTL8373_EEPROM_VER_INFO_EEPROM_CODE_DATE_2_OFFSET (16) + #define RTL8373_EEPROM_VER_INFO_EEPROM_CODE_DATE_2_MASK (0xFF << RTL8373_EEPROM_VER_INFO_EEPROM_CODE_DATE_2_OFFSET) + #define RTL8373_EEPROM_VER_INFO_EEPROM_CODE_DATE_1_OFFSET (8) + #define RTL8373_EEPROM_VER_INFO_EEPROM_CODE_DATE_1_MASK (0xFF << RTL8373_EEPROM_VER_INFO_EEPROM_CODE_DATE_1_OFFSET) + #define RTL8373_EEPROM_VER_INFO_EEPROM_CODE_DATE_0_OFFSET (0) + #define RTL8373_EEPROM_VER_INFO_EEPROM_CODE_DATE_0_MASK (0xFF << RTL8373_EEPROM_VER_INFO_EEPROM_CODE_DATE_0_OFFSET) + +#define RTL8373_EEPROM_AUTOLOAD_TIMER_ADDR (0x5F2C) + #define RTL8373_EEPROM_AUTOLOAD_TIMER_EEPROM_AUTOLOAD_TIMER_OFFSET (0) + #define RTL8373_EEPROM_AUTOLOAD_TIMER_EEPROM_AUTOLOAD_TIMER_MASK (0xFFFFFFFF << RTL8373_EEPROM_AUTOLOAD_TIMER_EEPROM_AUTOLOAD_TIMER_OFFSET) + +#define RTL8373_MAC_EEPROM_ADDR_LEN_ADDR (0x5F30) + #define RTL8373_MAC_EEPROM_ADDR_LEN_EEPROM_ADDR_LEN_OFFSET (0) + #define RTL8373_MAC_EEPROM_ADDR_LEN_EEPROM_ADDR_LEN_MASK (0x1 << RTL8373_MAC_EEPROM_ADDR_LEN_EEPROM_ADDR_LEN_OFFSET) + +/* + * Feature: Interrupt + */ +#define RTL8373_IMR_INT_PORT_LINK_STS_CHG_ADDR (0x5F34) + #define RTL8373_IMR_INT_PORT_LINK_STS_CHG_IMR_INT_PORT_LINK_STS_CHG_10_0_OFFSET (0) + #define RTL8373_IMR_INT_PORT_LINK_STS_CHG_IMR_INT_PORT_LINK_STS_CHG_10_0_MASK (0x3FF << RTL8373_IMR_INT_PORT_LINK_STS_CHG_IMR_INT_PORT_LINK_STS_CHG_10_0_OFFSET) + +#define RTL8373_IMR_INT_GPHY_ADDR (0x5F38) + #define RTL8373_IMR_INT_GPHY_IMR_INT_GPHY_3_0_OFFSET (0) + #define RTL8373_IMR_INT_GPHY_IMR_INT_GPHY_3_0_MASK (0xF << RTL8373_IMR_INT_GPHY_IMR_INT_GPHY_3_0_OFFSET) + +#define RTL8373_IMR_INT_LEARNOVER_ADDR (0x5F3C) + #define RTL8373_IMR_INT_LEARNOVER_IMR_INT_LEARN_OVER_PORT_9_0_OFFSET (0) + #define RTL8373_IMR_INT_LEARNOVER_IMR_INT_LEARN_OVER_PORT_9_0_MASK (0x3FF << RTL8373_IMR_INT_LEARNOVER_IMR_INT_LEARN_OVER_PORT_9_0_OFFSET) + +#define RTL8373_IMR_INT_RLFD_ADDR (0x5F40) + #define RTL8373_IMR_INT_RLFD_IMR_INT_RLFD_PORT_8_0_OFFSET (0) + #define RTL8373_IMR_INT_RLFD_IMR_INT_RLFD_PORT_8_0_MASK (0x1FF << RTL8373_IMR_INT_RLFD_IMR_INT_RLFD_PORT_8_0_OFFSET) + +#define RTL8373_IMR_INT_WOL_ADDR (0x5F44) + #define RTL8373_IMR_INT_WOL_IMR_INT_PHYWOL_PORT_3_0_OFFSET (9) + #define RTL8373_IMR_INT_WOL_IMR_INT_PHYWOL_PORT_3_0_MASK (0xF << RTL8373_IMR_INT_WOL_IMR_INT_PHYWOL_PORT_3_0_OFFSET) + #define RTL8373_IMR_INT_WOL_IMR_INT_WOL_PORT_8_0_OFFSET (0) + #define RTL8373_IMR_INT_WOL_IMR_INT_WOL_PORT_8_0_MASK (0x1FF << RTL8373_IMR_INT_WOL_IMR_INT_WOL_PORT_8_0_OFFSET) + +#define RTL8373_IMR_INT_SERDES_LINK_FAULT_P_ADDR (0x5F48) + #define RTL8373_IMR_INT_SERDES_LINK_FAULT_P_IMR_INT_SERDES_LINK_FAULT_PORT_OFFSET (0) + #define RTL8373_IMR_INT_SERDES_LINK_FAULT_P_IMR_INT_SERDES_LINK_FAULT_PORT_MASK (0x1F << RTL8373_IMR_INT_SERDES_LINK_FAULT_P_IMR_INT_SERDES_LINK_FAULT_PORT_OFFSET) + +#define RTL8373_IMR_INT_SDS_UPD_PHYSTS0_ADDR (0x5F4C) + #define RTL8373_IMR_INT_SDS_UPD_PHYSTS0_IMR_INT_SDS_UPD_PHYSTS_OFFSET (0) + #define RTL8373_IMR_INT_SDS_UPD_PHYSTS0_IMR_INT_SDS_UPD_PHYSTS_MASK (0x1F << RTL8373_IMR_INT_SDS_UPD_PHYSTS0_IMR_INT_SDS_UPD_PHYSTS_OFFSET) + +#define RTL8373_IMR_INT_GPIO_ADDR (0x5F50) + #define RTL8373_IMR_INT_GPIO_IMR_INT_GPIO_OFFSET (0) + #define RTL8373_IMR_INT_GPIO_IMR_INT_GPIO_MASK (0x7 << RTL8373_IMR_INT_GPIO_IMR_INT_GPIO_OFFSET) + +#define RTL8373_IMR_INT_MISC_ADDR (0x5F54) + #define RTL8373_IMR_INT_MISC_IMR_EXT_CPUIDE_EXT_OFFSET (24) + #define RTL8373_IMR_INT_MISC_IMR_EXT_CPUIDE_EXT_MASK (0x1 << RTL8373_IMR_INT_MISC_IMR_EXT_CPUIDE_EXT_OFFSET) + #define RTL8373_IMR_INT_MISC_IMR_EXT_CPUIDE_ENR_OFFSET (23) + #define RTL8373_IMR_INT_MISC_IMR_EXT_CPUIDE_ENR_MASK (0x1 << RTL8373_IMR_INT_MISC_IMR_EXT_CPUIDE_ENR_OFFSET) + #define RTL8373_IMR_INT_MISC_IMR_INT_MACSECWRP_3_0_OFFSET (19) + #define RTL8373_IMR_INT_MISC_IMR_INT_MACSECWRP_3_0_MASK (0xF << RTL8373_IMR_INT_MISC_IMR_INT_MACSECWRP_3_0_OFFSET) + #define RTL8373_IMR_INT_MISC_IMR_INT_PTP1588_OFFSET (18) + #define RTL8373_IMR_INT_MISC_IMR_INT_PTP1588_MASK (0x1 << RTL8373_IMR_INT_MISC_IMR_INT_PTP1588_OFFSET) + #define RTL8373_IMR_INT_MISC_IMR_INT_ROUT_PBUF_OFFSET (17) + #define RTL8373_IMR_INT_MISC_IMR_INT_ROUT_PBUF_MASK (0x1 << RTL8373_IMR_INT_MISC_IMR_INT_ROUT_PBUF_OFFSET) + #define RTL8373_IMR_INT_MISC_IMR_INT_METER_EXCEED_OFFSET (16) + #define RTL8373_IMR_INT_MISC_IMR_INT_METER_EXCEED_MASK (0x1 << RTL8373_IMR_INT_MISC_IMR_INT_METER_EXCEED_OFFSET) + #define RTL8373_IMR_INT_MISC_IMR_INT_LOOP_DETECTION_OFFSET (15) + #define RTL8373_IMR_INT_MISC_IMR_INT_LOOP_DETECTION_MASK (0x1 << RTL8373_IMR_INT_MISC_IMR_INT_LOOP_DETECTION_OFFSET) + #define RTL8373_IMR_INT_MISC_IMR_INT_ACL_OFFSET (13) + #define RTL8373_IMR_INT_MISC_IMR_INT_ACL_MASK (0x1 << RTL8373_IMR_INT_MISC_IMR_INT_ACL_OFFSET) + #define RTL8373_IMR_INT_MISC_IMR_INT_AUTO_REC_OFFSET (11) + #define RTL8373_IMR_INT_MISC_IMR_INT_AUTO_REC_MASK (0x1 << RTL8373_IMR_INT_MISC_IMR_INT_AUTO_REC_OFFSET) + #define RTL8373_IMR_INT_MISC_IMR_INT_SAMOVE_OFFSET (10) + #define RTL8373_IMR_INT_MISC_IMR_INT_SAMOVE_MASK (0x1 << RTL8373_IMR_INT_MISC_IMR_INT_SAMOVE_OFFSET) + #define RTL8373_IMR_INT_MISC_IMR_INT_SERDES_RX_SYM_ERR_1_0_OFFSET (7) + #define RTL8373_IMR_INT_MISC_IMR_INT_SERDES_RX_SYM_ERR_1_0_MASK (0x3 << RTL8373_IMR_INT_MISC_IMR_INT_SERDES_RX_SYM_ERR_1_0_OFFSET) + #define RTL8373_IMR_INT_MISC_IMR_INT_SMI_CHECK_REG_4_0_OFFSET (2) + #define RTL8373_IMR_INT_MISC_IMR_INT_SMI_CHECK_REG_4_0_MASK (0x1F << RTL8373_IMR_INT_MISC_IMR_INT_SMI_CHECK_REG_4_0_OFFSET) + #define RTL8373_IMR_INT_MISC_IMR_INT_TM_LOW_OFFSET (1) + #define RTL8373_IMR_INT_MISC_IMR_INT_TM_LOW_MASK (0x1 << RTL8373_IMR_INT_MISC_IMR_INT_TM_LOW_OFFSET) + #define RTL8373_IMR_INT_MISC_IMR_INT_TM_HIGH_OFFSET (0) + #define RTL8373_IMR_INT_MISC_IMR_INT_TM_HIGH_MASK (0x1 << RTL8373_IMR_INT_MISC_IMR_INT_TM_HIGH_OFFSET) + +#define RTL8373_IMR_EXT_PORT_LINK_STS_CHG_ADDR (0x5F58) + #define RTL8373_IMR_EXT_PORT_LINK_STS_CHG_IMR_EXT_PORT_LINK_STS_CHG_10_0_OFFSET (0) + #define RTL8373_IMR_EXT_PORT_LINK_STS_CHG_IMR_EXT_PORT_LINK_STS_CHG_10_0_MASK (0x3FF << RTL8373_IMR_EXT_PORT_LINK_STS_CHG_IMR_EXT_PORT_LINK_STS_CHG_10_0_OFFSET) + +#define RTL8373_IMR_EXT_GPHY_ADDR (0x5F5C) + #define RTL8373_IMR_EXT_GPHY_IMR_EXT_GPHY_3_0_OFFSET (0) + #define RTL8373_IMR_EXT_GPHY_IMR_EXT_GPHY_3_0_MASK (0xF << RTL8373_IMR_EXT_GPHY_IMR_EXT_GPHY_3_0_OFFSET) + +#define RTL8373_IMR_EXT_LEARNOVER_ADDR (0x5F60) + #define RTL8373_IMR_EXT_LEARNOVER_IMR_EXT_LEARN_OVER_PORT_9_0_OFFSET (0) + #define RTL8373_IMR_EXT_LEARNOVER_IMR_EXT_LEARN_OVER_PORT_9_0_MASK (0x3FF << RTL8373_IMR_EXT_LEARNOVER_IMR_EXT_LEARN_OVER_PORT_9_0_OFFSET) + +#define RTL8373_IMR_EXT_RLFD_ADDR (0x5F64) + #define RTL8373_IMR_EXT_RLFD_IMR_EXT_RLFD_PORT_8_0_OFFSET (0) + #define RTL8373_IMR_EXT_RLFD_IMR_EXT_RLFD_PORT_8_0_MASK (0x1FF << RTL8373_IMR_EXT_RLFD_IMR_EXT_RLFD_PORT_8_0_OFFSET) + +#define RTL8373_IMR_EXT_WOL_ADDR (0x5F68) + #define RTL8373_IMR_EXT_WOL_IMR_EXT_PHYWOL_PORT_3_0_OFFSET (9) + #define RTL8373_IMR_EXT_WOL_IMR_EXT_PHYWOL_PORT_3_0_MASK (0xF << RTL8373_IMR_EXT_WOL_IMR_EXT_PHYWOL_PORT_3_0_OFFSET) + #define RTL8373_IMR_EXT_WOL_IMR_EXT_WOL_PORT_8_0_OFFSET (0) + #define RTL8373_IMR_EXT_WOL_IMR_EXT_WOL_PORT_8_0_MASK (0x1FF << RTL8373_IMR_EXT_WOL_IMR_EXT_WOL_PORT_8_0_OFFSET) + +#define RTL8373_IMR_EXT_SERDES_LINK_FAULT_P_ADDR (0x5F6C) + #define RTL8373_IMR_EXT_SERDES_LINK_FAULT_P_IMR_EXT_SERDES_LINK_FAULT_PORT_OFFSET (0) + #define RTL8373_IMR_EXT_SERDES_LINK_FAULT_P_IMR_EXT_SERDES_LINK_FAULT_PORT_MASK (0x1F << RTL8373_IMR_EXT_SERDES_LINK_FAULT_P_IMR_EXT_SERDES_LINK_FAULT_PORT_OFFSET) + +#define RTL8373_IMR_EXT_SDS_UPD_PHYSTS0_ADDR (0x5F70) + #define RTL8373_IMR_EXT_SDS_UPD_PHYSTS0_IMR_EXT_SDS_UPD_PHYSTS_OFFSET (0) + #define RTL8373_IMR_EXT_SDS_UPD_PHYSTS0_IMR_EXT_SDS_UPD_PHYSTS_MASK (0x1F << RTL8373_IMR_EXT_SDS_UPD_PHYSTS0_IMR_EXT_SDS_UPD_PHYSTS_OFFSET) + +#define RTL8373_IMR_EXT_GPIO_ADDR (0x5F74) + #define RTL8373_IMR_EXT_GPIO_IMR_EXT_GPIO_OFFSET (0) + #define RTL8373_IMR_EXT_GPIO_IMR_EXT_GPIO_MASK (0x7 << RTL8373_IMR_EXT_GPIO_IMR_EXT_GPIO_OFFSET) + +#define RTL8373_IMR_EXT_MISC_ADDR (0x5F78) + #define RTL8373_IMR_EXT_MISC_IMR_EXT_MACSECWRP_3_0_OFFSET (19) + #define RTL8373_IMR_EXT_MISC_IMR_EXT_MACSECWRP_3_0_MASK (0xF << RTL8373_IMR_EXT_MISC_IMR_EXT_MACSECWRP_3_0_OFFSET) + #define RTL8373_IMR_EXT_MISC_IMR_EXT_PTP1588_OFFSET (18) + #define RTL8373_IMR_EXT_MISC_IMR_EXT_PTP1588_MASK (0x1 << RTL8373_IMR_EXT_MISC_IMR_EXT_PTP1588_OFFSET) + #define RTL8373_IMR_EXT_MISC_IMR_EXT_ROUT_PBUF_OFFSET (17) + #define RTL8373_IMR_EXT_MISC_IMR_EXT_ROUT_PBUF_MASK (0x1 << RTL8373_IMR_EXT_MISC_IMR_EXT_ROUT_PBUF_OFFSET) + #define RTL8373_IMR_EXT_MISC_IMR_EXT_METER_EXCEED_OFFSET (16) + #define RTL8373_IMR_EXT_MISC_IMR_EXT_METER_EXCEED_MASK (0x1 << RTL8373_IMR_EXT_MISC_IMR_EXT_METER_EXCEED_OFFSET) + #define RTL8373_IMR_EXT_MISC_IMR_EXT_LOOP_DETECTION_OFFSET (15) + #define RTL8373_IMR_EXT_MISC_IMR_EXT_LOOP_DETECTION_MASK (0x1 << RTL8373_IMR_EXT_MISC_IMR_EXT_LOOP_DETECTION_OFFSET) + #define RTL8373_IMR_EXT_MISC_IMR_EXT_8051_OFFSET (14) + #define RTL8373_IMR_EXT_MISC_IMR_EXT_8051_MASK (0x1 << RTL8373_IMR_EXT_MISC_IMR_EXT_8051_OFFSET) + #define RTL8373_IMR_EXT_MISC_IMR_EXT_ACL_OFFSET (13) + #define RTL8373_IMR_EXT_MISC_IMR_EXT_ACL_MASK (0x1 << RTL8373_IMR_EXT_MISC_IMR_EXT_ACL_OFFSET) + #define RTL8373_IMR_EXT_MISC_IMR_EXT_AUTO_REC_OFFSET (11) + #define RTL8373_IMR_EXT_MISC_IMR_EXT_AUTO_REC_MASK (0x1 << RTL8373_IMR_EXT_MISC_IMR_EXT_AUTO_REC_OFFSET) + #define RTL8373_IMR_EXT_MISC_IMR_EXT_SAMOVE_OFFSET (10) + #define RTL8373_IMR_EXT_MISC_IMR_EXT_SAMOVE_MASK (0x1 << RTL8373_IMR_EXT_MISC_IMR_EXT_SAMOVE_OFFSET) + #define RTL8373_IMR_EXT_MISC_IMR_EXT_SERDES_RX_SYM_ERR_1_0_OFFSET (7) + #define RTL8373_IMR_EXT_MISC_IMR_EXT_SERDES_RX_SYM_ERR_1_0_MASK (0x3 << RTL8373_IMR_EXT_MISC_IMR_EXT_SERDES_RX_SYM_ERR_1_0_OFFSET) + #define RTL8373_IMR_EXT_MISC_IMR_EXT_SMI_CHECK_REG_4_0_OFFSET (2) + #define RTL8373_IMR_EXT_MISC_IMR_EXT_SMI_CHECK_REG_4_0_MASK (0x1F << RTL8373_IMR_EXT_MISC_IMR_EXT_SMI_CHECK_REG_4_0_OFFSET) + #define RTL8373_IMR_EXT_MISC_IMR_EXT_TM_LOW_OFFSET (1) + #define RTL8373_IMR_EXT_MISC_IMR_EXT_TM_LOW_MASK (0x1 << RTL8373_IMR_EXT_MISC_IMR_EXT_TM_LOW_OFFSET) + #define RTL8373_IMR_EXT_MISC_IMR_EXT_TM_HIGH_OFFSET (0) + #define RTL8373_IMR_EXT_MISC_IMR_EXT_TM_HIGH_MASK (0x1 << RTL8373_IMR_EXT_MISC_IMR_EXT_TM_HIGH_OFFSET) + +#define RTL8373_ISR_INT_GLB_ADDR (0x5F7C) + #define RTL8373_ISR_INT_GLB_ISR_INT_GLB_LINK_CHG_OFFSET (31) + #define RTL8373_ISR_INT_GLB_ISR_INT_GLB_LINK_CHG_MASK (0x1 << RTL8373_ISR_INT_GLB_ISR_INT_GLB_LINK_CHG_OFFSET) + #define RTL8373_ISR_INT_GLB_ISR_INT_GLB_LEARN_OVER_OFFSET (30) + #define RTL8373_ISR_INT_GLB_ISR_INT_GLB_LEARN_OVER_MASK (0x1 << RTL8373_ISR_INT_GLB_ISR_INT_GLB_LEARN_OVER_OFFSET) + #define RTL8373_ISR_INT_GLB_ISR_INT_GLB_GPHY_OFFSET (29) + #define RTL8373_ISR_INT_GLB_ISR_INT_GLB_GPHY_MASK (0x1 << RTL8373_ISR_INT_GLB_ISR_INT_GLB_GPHY_OFFSET) + #define RTL8373_ISR_INT_GLB_ISR_INT_GLB_RLFD_OFFSET (28) + #define RTL8373_ISR_INT_GLB_ISR_INT_GLB_RLFD_MASK (0x1 << RTL8373_ISR_INT_GLB_ISR_INT_GLB_RLFD_OFFSET) + #define RTL8373_ISR_INT_GLB_ISR_INT_GLB_WOL_OFFSET (27) + #define RTL8373_ISR_INT_GLB_ISR_INT_GLB_WOL_MASK (0x1 << RTL8373_ISR_INT_GLB_ISR_INT_GLB_WOL_OFFSET) + #define RTL8373_ISR_INT_GLB_ISR_INT_GLB_SERDES_LINK_FAULT_P_OFFSET (26) + #define RTL8373_ISR_INT_GLB_ISR_INT_GLB_SERDES_LINK_FAULT_P_MASK (0x1 << RTL8373_ISR_INT_GLB_ISR_INT_GLB_SERDES_LINK_FAULT_P_OFFSET) + #define RTL8373_ISR_INT_GLB_ISR_INT_GLB_SDS_UPD_PHYSTS_OFFSET (25) + #define RTL8373_ISR_INT_GLB_ISR_INT_GLB_SDS_UPD_PHYSTS_MASK (0x1 << RTL8373_ISR_INT_GLB_ISR_INT_GLB_SDS_UPD_PHYSTS_OFFSET) + #define RTL8373_ISR_INT_GLB_ISR_INT_GLB_ROUT_PBUF_OFFSET (24) + #define RTL8373_ISR_INT_GLB_ISR_INT_GLB_ROUT_PBUF_MASK (0x1 << RTL8373_ISR_INT_GLB_ISR_INT_GLB_ROUT_PBUF_OFFSET) + #define RTL8373_ISR_INT_GLB_ISR_INT_GLB_PHYWOL_OFFSET (16) + #define RTL8373_ISR_INT_GLB_ISR_INT_GLB_PHYWOL_MASK (0x1 << RTL8373_ISR_INT_GLB_ISR_INT_GLB_PHYWOL_OFFSET) + #define RTL8373_ISR_INT_GLB_ISR_INT_GLB_MACSECWRP_OFFSET (15) + #define RTL8373_ISR_INT_GLB_ISR_INT_GLB_MACSECWRP_MASK (0x1 << RTL8373_ISR_INT_GLB_ISR_INT_GLB_MACSECWRP_OFFSET) + #define RTL8373_ISR_INT_GLB_ISR_INT_GLB_PTP1588_OFFSET (14) + #define RTL8373_ISR_INT_GLB_ISR_INT_GLB_PTP1588_MASK (0x1 << RTL8373_ISR_INT_GLB_ISR_INT_GLB_PTP1588_OFFSET) + #define RTL8373_ISR_INT_GLB_ISR_INT_GLB_METER_EXCEED_OFFSET (13) + #define RTL8373_ISR_INT_GLB_ISR_INT_GLB_METER_EXCEED_MASK (0x1 << RTL8373_ISR_INT_GLB_ISR_INT_GLB_METER_EXCEED_OFFSET) + #define RTL8373_ISR_INT_GLB_ISR_INT_GLB_LOOP_DETECTION_OFFSET (12) + #define RTL8373_ISR_INT_GLB_ISR_INT_GLB_LOOP_DETECTION_MASK (0x1 << RTL8373_ISR_INT_GLB_ISR_INT_GLB_LOOP_DETECTION_OFFSET) + #define RTL8373_ISR_INT_GLB_ISR_INT_GLB_ACL_OFFSET (10) + #define RTL8373_ISR_INT_GLB_ISR_INT_GLB_ACL_MASK (0x1 << RTL8373_ISR_INT_GLB_ISR_INT_GLB_ACL_OFFSET) + #define RTL8373_ISR_INT_GLB_ISR_INT_GLB_AUTO_REC_OFFSET (8) + #define RTL8373_ISR_INT_GLB_ISR_INT_GLB_AUTO_REC_MASK (0x1 << RTL8373_ISR_INT_GLB_ISR_INT_GLB_AUTO_REC_OFFSET) + #define RTL8373_ISR_INT_GLB_ISR_INT_GLB_SAMOVE_OFFSET (7) + #define RTL8373_ISR_INT_GLB_ISR_INT_GLB_SAMOVE_MASK (0x1 << RTL8373_ISR_INT_GLB_ISR_INT_GLB_SAMOVE_OFFSET) + #define RTL8373_ISR_INT_GLB_ISR_INT_GLB_GPIO_OFFSET (5) + #define RTL8373_ISR_INT_GLB_ISR_INT_GLB_GPIO_MASK (0x1 << RTL8373_ISR_INT_GLB_ISR_INT_GLB_GPIO_OFFSET) + #define RTL8373_ISR_INT_GLB_ISR_INT_GLB_SDS_RX_SYM_ERR_OFFSET (4) + #define RTL8373_ISR_INT_GLB_ISR_INT_GLB_SDS_RX_SYM_ERR_MASK (0x1 << RTL8373_ISR_INT_GLB_ISR_INT_GLB_SDS_RX_SYM_ERR_OFFSET) + #define RTL8373_ISR_INT_GLB_ISR_INT_GLB_SMI_CHECK_OFFSET (2) + #define RTL8373_ISR_INT_GLB_ISR_INT_GLB_SMI_CHECK_MASK (0x1 << RTL8373_ISR_INT_GLB_ISR_INT_GLB_SMI_CHECK_OFFSET) + #define RTL8373_ISR_INT_GLB_ISR_INT_GLB_TERMAL_DETECT_OFFSET (0) + #define RTL8373_ISR_INT_GLB_ISR_INT_GLB_TERMAL_DETECT_MASK (0x1 << RTL8373_ISR_INT_GLB_ISR_INT_GLB_TERMAL_DETECT_OFFSET) + +#define RTL8373_ISR_EXT_GLB_ADDR (0x5F80) + #define RTL8373_ISR_EXT_GLB_ISR_EXT_GLB_LINK_CHG_OFFSET (31) + #define RTL8373_ISR_EXT_GLB_ISR_EXT_GLB_LINK_CHG_MASK (0x1 << RTL8373_ISR_EXT_GLB_ISR_EXT_GLB_LINK_CHG_OFFSET) + #define RTL8373_ISR_EXT_GLB_ISR_EXT_GLB_LEARN_OVER_OFFSET (30) + #define RTL8373_ISR_EXT_GLB_ISR_EXT_GLB_LEARN_OVER_MASK (0x1 << RTL8373_ISR_EXT_GLB_ISR_EXT_GLB_LEARN_OVER_OFFSET) + #define RTL8373_ISR_EXT_GLB_ISR_EXT_GLB_GPHY_OFFSET (29) + #define RTL8373_ISR_EXT_GLB_ISR_EXT_GLB_GPHY_MASK (0x1 << RTL8373_ISR_EXT_GLB_ISR_EXT_GLB_GPHY_OFFSET) + #define RTL8373_ISR_EXT_GLB_ISR_EXT_GLB_RLFD_OFFSET (28) + #define RTL8373_ISR_EXT_GLB_ISR_EXT_GLB_RLFD_MASK (0x1 << RTL8373_ISR_EXT_GLB_ISR_EXT_GLB_RLFD_OFFSET) + #define RTL8373_ISR_EXT_GLB_ISR_EXT_GLB_WOL_OFFSET (27) + #define RTL8373_ISR_EXT_GLB_ISR_EXT_GLB_WOL_MASK (0x1 << RTL8373_ISR_EXT_GLB_ISR_EXT_GLB_WOL_OFFSET) + #define RTL8373_ISR_EXT_GLB_ISR_EXT_GLB_SERDES_LINK_FAULT_P_OFFSET (26) + #define RTL8373_ISR_EXT_GLB_ISR_EXT_GLB_SERDES_LINK_FAULT_P_MASK (0x1 << RTL8373_ISR_EXT_GLB_ISR_EXT_GLB_SERDES_LINK_FAULT_P_OFFSET) + #define RTL8373_ISR_EXT_GLB_ISR_EXT_GLB_SDS_UPD_PHYSTS_OFFSET (25) + #define RTL8373_ISR_EXT_GLB_ISR_EXT_GLB_SDS_UPD_PHYSTS_MASK (0x1 << RTL8373_ISR_EXT_GLB_ISR_EXT_GLB_SDS_UPD_PHYSTS_OFFSET) + #define RTL8373_ISR_EXT_GLB_ISR_EXT_GLB_ROUT_PBUF_OFFSET (24) + #define RTL8373_ISR_EXT_GLB_ISR_EXT_GLB_ROUT_PBUF_MASK (0x1 << RTL8373_ISR_EXT_GLB_ISR_EXT_GLB_ROUT_PBUF_OFFSET) + #define RTL8373_ISR_EXT_GLB_ISR_EXT_GLB_CPUIDE_EXT_OFFSET (18) + #define RTL8373_ISR_EXT_GLB_ISR_EXT_GLB_CPUIDE_EXT_MASK (0x1 << RTL8373_ISR_EXT_GLB_ISR_EXT_GLB_CPUIDE_EXT_OFFSET) + #define RTL8373_ISR_EXT_GLB_ISR_EXT_GLB_CPUIDE_ENR_OFFSET (17) + #define RTL8373_ISR_EXT_GLB_ISR_EXT_GLB_CPUIDE_ENR_MASK (0x1 << RTL8373_ISR_EXT_GLB_ISR_EXT_GLB_CPUIDE_ENR_OFFSET) + #define RTL8373_ISR_EXT_GLB_ISR_EXT_GLB_PHYWOL_OFFSET (16) + #define RTL8373_ISR_EXT_GLB_ISR_EXT_GLB_PHYWOL_MASK (0x1 << RTL8373_ISR_EXT_GLB_ISR_EXT_GLB_PHYWOL_OFFSET) + #define RTL8373_ISR_EXT_GLB_ISR_EXT_GLB_MACSECWRP_OFFSET (15) + #define RTL8373_ISR_EXT_GLB_ISR_EXT_GLB_MACSECWRP_MASK (0x1 << RTL8373_ISR_EXT_GLB_ISR_EXT_GLB_MACSECWRP_OFFSET) + #define RTL8373_ISR_EXT_GLB_ISR_EXT_GLB_PTP1588_OFFSET (14) + #define RTL8373_ISR_EXT_GLB_ISR_EXT_GLB_PTP1588_MASK (0x1 << RTL8373_ISR_EXT_GLB_ISR_EXT_GLB_PTP1588_OFFSET) + #define RTL8373_ISR_EXT_GLB_ISR_EXT_GLB_METER_EXCEED_OFFSET (13) + #define RTL8373_ISR_EXT_GLB_ISR_EXT_GLB_METER_EXCEED_MASK (0x1 << RTL8373_ISR_EXT_GLB_ISR_EXT_GLB_METER_EXCEED_OFFSET) + #define RTL8373_ISR_EXT_GLB_ISR_EXT_GLB_LOOP_DETECTION_OFFSET (12) + #define RTL8373_ISR_EXT_GLB_ISR_EXT_GLB_LOOP_DETECTION_MASK (0x1 << RTL8373_ISR_EXT_GLB_ISR_EXT_GLB_LOOP_DETECTION_OFFSET) + #define RTL8373_ISR_EXT_GLB_ISR_EXT_GLB_8051_OFFSET (11) + #define RTL8373_ISR_EXT_GLB_ISR_EXT_GLB_8051_MASK (0x1 << RTL8373_ISR_EXT_GLB_ISR_EXT_GLB_8051_OFFSET) + #define RTL8373_ISR_EXT_GLB_ISR_EXT_GLB_ACL_OFFSET (10) + #define RTL8373_ISR_EXT_GLB_ISR_EXT_GLB_ACL_MASK (0x1 << RTL8373_ISR_EXT_GLB_ISR_EXT_GLB_ACL_OFFSET) + #define RTL8373_ISR_EXT_GLB_ISR_EXT_GLB_AUTO_REC_OFFSET (8) + #define RTL8373_ISR_EXT_GLB_ISR_EXT_GLB_AUTO_REC_MASK (0x1 << RTL8373_ISR_EXT_GLB_ISR_EXT_GLB_AUTO_REC_OFFSET) + #define RTL8373_ISR_EXT_GLB_ISR_EXT_GLB_SAMOVE_OFFSET (7) + #define RTL8373_ISR_EXT_GLB_ISR_EXT_GLB_SAMOVE_MASK (0x1 << RTL8373_ISR_EXT_GLB_ISR_EXT_GLB_SAMOVE_OFFSET) + #define RTL8373_ISR_EXT_GLB_ISR_EXT_GLB_GPIO_OFFSET (5) + #define RTL8373_ISR_EXT_GLB_ISR_EXT_GLB_GPIO_MASK (0x1 << RTL8373_ISR_EXT_GLB_ISR_EXT_GLB_GPIO_OFFSET) + #define RTL8373_ISR_EXT_GLB_ISR_EXT_GLB_SDS_RX_SYM_ERR_OFFSET (4) + #define RTL8373_ISR_EXT_GLB_ISR_EXT_GLB_SDS_RX_SYM_ERR_MASK (0x1 << RTL8373_ISR_EXT_GLB_ISR_EXT_GLB_SDS_RX_SYM_ERR_OFFSET) + #define RTL8373_ISR_EXT_GLB_ISR_EXT_GLB_SMI_CHECK_OFFSET (2) + #define RTL8373_ISR_EXT_GLB_ISR_EXT_GLB_SMI_CHECK_MASK (0x1 << RTL8373_ISR_EXT_GLB_ISR_EXT_GLB_SMI_CHECK_OFFSET) + #define RTL8373_ISR_EXT_GLB_ISR_EXT_GLB_TERMAL_DETECT_OFFSET (0) + #define RTL8373_ISR_EXT_GLB_ISR_EXT_GLB_TERMAL_DETECT_MASK (0x1 << RTL8373_ISR_EXT_GLB_ISR_EXT_GLB_TERMAL_DETECT_OFFSET) + +#define RTL8373_ISR_SW_INT_MODE_ADDR (0x5F84) + #define RTL8373_ISR_SW_INT_MODE_INTP_OUT_SDS_CTRL_OFFSET (7) + #define RTL8373_ISR_SW_INT_MODE_INTP_OUT_SDS_CTRL_MASK (0x1 << RTL8373_ISR_SW_INT_MODE_INTP_OUT_SDS_CTRL_OFFSET) + #define RTL8373_ISR_SW_INT_MODE_SWITCH_IE_OFFSET (6) + #define RTL8373_ISR_SW_INT_MODE_SWITCH_IE_MASK (0x1 << RTL8373_ISR_SW_INT_MODE_SWITCH_IE_OFFSET) + #define RTL8373_ISR_SW_INT_MODE_SW_INT_PULSE_INTERVAL_OFFSET (3) + #define RTL8373_ISR_SW_INT_MODE_SW_INT_PULSE_INTERVAL_MASK (0x7 << RTL8373_ISR_SW_INT_MODE_SW_INT_PULSE_INTERVAL_OFFSET) + #define RTL8373_ISR_SW_INT_MODE_SW_INT_MODE_OFFSET (1) + #define RTL8373_ISR_SW_INT_MODE_SW_INT_MODE_MASK (0x3 << RTL8373_ISR_SW_INT_MODE_SW_INT_MODE_OFFSET) + #define RTL8373_ISR_SW_INT_MODE_SW_INT_OD_OFFSET (0) + #define RTL8373_ISR_SW_INT_MODE_SW_INT_OD_MASK (0x1 << RTL8373_ISR_SW_INT_MODE_SW_INT_OD_OFFSET) + +#define RTL8373_ISR_INT_PORT_LINK_STS_CHG_ADDR (0x5F88) + #define RTL8373_ISR_INT_PORT_LINK_STS_CHG_ISR_INT_PORT_LINK_STS_CHG_9_0_OFFSET (0) + #define RTL8373_ISR_INT_PORT_LINK_STS_CHG_ISR_INT_PORT_LINK_STS_CHG_9_0_MASK (0x3FF << RTL8373_ISR_INT_PORT_LINK_STS_CHG_ISR_INT_PORT_LINK_STS_CHG_9_0_OFFSET) + +#define RTL8373_ISR_INT_GPHY_ADDR (0x5F8C) + #define RTL8373_ISR_INT_GPHY_ISR_INT_GPHY_OFFSET (0) + #define RTL8373_ISR_INT_GPHY_ISR_INT_GPHY_MASK (0xF << RTL8373_ISR_INT_GPHY_ISR_INT_GPHY_OFFSET) + +#define RTL8373_ISR_INT_LEARNOVER_ADDR (0x5F90) + #define RTL8373_ISR_INT_LEARNOVER_ISR_INT_LEARN_OVER_PORT_9_0_OFFSET (0) + #define RTL8373_ISR_INT_LEARNOVER_ISR_INT_LEARN_OVER_PORT_9_0_MASK (0x3FF << RTL8373_ISR_INT_LEARNOVER_ISR_INT_LEARN_OVER_PORT_9_0_OFFSET) + +#define RTL8373_ISR_INT_TM_RLFD_ADDR (0x5F94) + #define RTL8373_ISR_INT_TM_RLFD_ISR_INT_RLFD_PORT_8_0_OFFSET (0) + #define RTL8373_ISR_INT_TM_RLFD_ISR_INT_RLFD_PORT_8_0_MASK (0x1FF << RTL8373_ISR_INT_TM_RLFD_ISR_INT_RLFD_PORT_8_0_OFFSET) + +#define RTL8373_ISR_INT_WOL_ADDR (0x5F98) + #define RTL8373_ISR_INT_WOL_ISR_INT_PHYWOL_PORT_3_0_OFFSET (9) + #define RTL8373_ISR_INT_WOL_ISR_INT_PHYWOL_PORT_3_0_MASK (0xF << RTL8373_ISR_INT_WOL_ISR_INT_PHYWOL_PORT_3_0_OFFSET) + #define RTL8373_ISR_INT_WOL_ISR_INT_WOL_PORT_8_0_OFFSET (0) + #define RTL8373_ISR_INT_WOL_ISR_INT_WOL_PORT_8_0_MASK (0x1FF << RTL8373_ISR_INT_WOL_ISR_INT_WOL_PORT_8_0_OFFSET) + +#define RTL8373_ISR_INT_SERDES_LINK_FAULT_P_ADDR (0x5F9C) + #define RTL8373_ISR_INT_SERDES_LINK_FAULT_P_ISR_INT_SERDES_LINK_FAULT_PORT_OFFSET (0) + #define RTL8373_ISR_INT_SERDES_LINK_FAULT_P_ISR_INT_SERDES_LINK_FAULT_PORT_MASK (0x1F << RTL8373_ISR_INT_SERDES_LINK_FAULT_P_ISR_INT_SERDES_LINK_FAULT_PORT_OFFSET) + +#define RTL8373_ISR_INT_SDS_UPD_PHYSTS0_ADDR (0x5FA0) + #define RTL8373_ISR_INT_SDS_UPD_PHYSTS0_ISR_INT_SDS_UPD_PHYSTS_OFFSET (0) + #define RTL8373_ISR_INT_SDS_UPD_PHYSTS0_ISR_INT_SDS_UPD_PHYSTS_MASK (0x1F << RTL8373_ISR_INT_SDS_UPD_PHYSTS0_ISR_INT_SDS_UPD_PHYSTS_OFFSET) + +#define RTL8373_ISR_INT_GPIO_ADDR (0x5FA4) + #define RTL8373_ISR_INT_GPIO_ISR_INT_GPIO_OFFSET (0) + #define RTL8373_ISR_INT_GPIO_ISR_INT_GPIO_MASK (0x7 << RTL8373_ISR_INT_GPIO_ISR_INT_GPIO_OFFSET) + +#define RTL8373_ISR_INT_MISC_ADDR (0x5FA8) + #define RTL8373_ISR_INT_MISC_ISR_INT_MACSECWRP_3_0_OFFSET (19) + #define RTL8373_ISR_INT_MISC_ISR_INT_MACSECWRP_3_0_MASK (0xF << RTL8373_ISR_INT_MISC_ISR_INT_MACSECWRP_3_0_OFFSET) + #define RTL8373_ISR_INT_MISC_ISR_INT_PTP1588_OFFSET (18) + #define RTL8373_ISR_INT_MISC_ISR_INT_PTP1588_MASK (0x1 << RTL8373_ISR_INT_MISC_ISR_INT_PTP1588_OFFSET) + #define RTL8373_ISR_INT_MISC_ISR_INT_ROUT_PBUF_OFFSET (17) + #define RTL8373_ISR_INT_MISC_ISR_INT_ROUT_PBUF_MASK (0x1 << RTL8373_ISR_INT_MISC_ISR_INT_ROUT_PBUF_OFFSET) + #define RTL8373_ISR_INT_MISC_ISR_INT_METER_EXCEED_OFFSET (16) + #define RTL8373_ISR_INT_MISC_ISR_INT_METER_EXCEED_MASK (0x1 << RTL8373_ISR_INT_MISC_ISR_INT_METER_EXCEED_OFFSET) + #define RTL8373_ISR_INT_MISC_ISR_INT_LOOP_DETECTION_OFFSET (15) + #define RTL8373_ISR_INT_MISC_ISR_INT_LOOP_DETECTION_MASK (0x1 << RTL8373_ISR_INT_MISC_ISR_INT_LOOP_DETECTION_OFFSET) + #define RTL8373_ISR_INT_MISC_ISR_INT_ACL_OFFSET (13) + #define RTL8373_ISR_INT_MISC_ISR_INT_ACL_MASK (0x1 << RTL8373_ISR_INT_MISC_ISR_INT_ACL_OFFSET) + #define RTL8373_ISR_INT_MISC_ISR_INT_AUTO_REC_OFFSET (11) + #define RTL8373_ISR_INT_MISC_ISR_INT_AUTO_REC_MASK (0x1 << RTL8373_ISR_INT_MISC_ISR_INT_AUTO_REC_OFFSET) + #define RTL8373_ISR_INT_MISC_ISR_INT_SAMOVE_OFFSET (10) + #define RTL8373_ISR_INT_MISC_ISR_INT_SAMOVE_MASK (0x1 << RTL8373_ISR_INT_MISC_ISR_INT_SAMOVE_OFFSET) + #define RTL8373_ISR_INT_MISC_ISR_INT_SERDES_RX_SYM_ERR_1_0_OFFSET (7) + #define RTL8373_ISR_INT_MISC_ISR_INT_SERDES_RX_SYM_ERR_1_0_MASK (0x3 << RTL8373_ISR_INT_MISC_ISR_INT_SERDES_RX_SYM_ERR_1_0_OFFSET) + #define RTL8373_ISR_INT_MISC_ISR_INT_SMI_CHECK_REG_4_0_OFFSET (2) + #define RTL8373_ISR_INT_MISC_ISR_INT_SMI_CHECK_REG_4_0_MASK (0x1F << RTL8373_ISR_INT_MISC_ISR_INT_SMI_CHECK_REG_4_0_OFFSET) + #define RTL8373_ISR_INT_MISC_ISR_INT_TM_LOW_OFFSET (1) + #define RTL8373_ISR_INT_MISC_ISR_INT_TM_LOW_MASK (0x1 << RTL8373_ISR_INT_MISC_ISR_INT_TM_LOW_OFFSET) + #define RTL8373_ISR_INT_MISC_ISR_INT_TM_HIGH_OFFSET (0) + #define RTL8373_ISR_INT_MISC_ISR_INT_TM_HIGH_MASK (0x1 << RTL8373_ISR_INT_MISC_ISR_INT_TM_HIGH_OFFSET) + +#define RTL8373_ISR_EXT_PORT_LINK_STS_CHG_ADDR (0x5FAC) + #define RTL8373_ISR_EXT_PORT_LINK_STS_CHG_ISR_EXT_PORT_LINK_STS_CHG_9_0_OFFSET (0) + #define RTL8373_ISR_EXT_PORT_LINK_STS_CHG_ISR_EXT_PORT_LINK_STS_CHG_9_0_MASK (0x3FF << RTL8373_ISR_EXT_PORT_LINK_STS_CHG_ISR_EXT_PORT_LINK_STS_CHG_9_0_OFFSET) + +#define RTL8373_ISR_EXT_GPHY_ADDR (0x5FB0) + #define RTL8373_ISR_EXT_GPHY_ISR_EXT_GPHY_OFFSET (0) + #define RTL8373_ISR_EXT_GPHY_ISR_EXT_GPHY_MASK (0xF << RTL8373_ISR_EXT_GPHY_ISR_EXT_GPHY_OFFSET) + +#define RTL8373_ISR_EXT_LEARNOVER_ADDR (0x5FB4) + #define RTL8373_ISR_EXT_LEARNOVER_ISR_EXT_LEARN_OVER_PORT_9_0_OFFSET (0) + #define RTL8373_ISR_EXT_LEARNOVER_ISR_EXT_LEARN_OVER_PORT_9_0_MASK (0x3FF << RTL8373_ISR_EXT_LEARNOVER_ISR_EXT_LEARN_OVER_PORT_9_0_OFFSET) + +#define RTL8373_ISR_EXT_TM_RLFD_ADDR (0x5FB8) + #define RTL8373_ISR_EXT_TM_RLFD_ISR_EXT_RLFD_PORT_8_0_OFFSET (0) + #define RTL8373_ISR_EXT_TM_RLFD_ISR_EXT_RLFD_PORT_8_0_MASK (0x1FF << RTL8373_ISR_EXT_TM_RLFD_ISR_EXT_RLFD_PORT_8_0_OFFSET) + +#define RTL8373_ISR_EXT_WOL_ADDR (0x5FBC) + #define RTL8373_ISR_EXT_WOL_ISR_EXT_PHYWOL_PORT_3_0_OFFSET (9) + #define RTL8373_ISR_EXT_WOL_ISR_EXT_PHYWOL_PORT_3_0_MASK (0xF << RTL8373_ISR_EXT_WOL_ISR_EXT_PHYWOL_PORT_3_0_OFFSET) + #define RTL8373_ISR_EXT_WOL_ISR_EXT_WOL_PORT_8_0_OFFSET (0) + #define RTL8373_ISR_EXT_WOL_ISR_EXT_WOL_PORT_8_0_MASK (0x1FF << RTL8373_ISR_EXT_WOL_ISR_EXT_WOL_PORT_8_0_OFFSET) + +#define RTL8373_ISR_EXT_SERDES_LINK_FAULT_P_ADDR (0x5FC0) + #define RTL8373_ISR_EXT_SERDES_LINK_FAULT_P_ISR_EXT_SERDES_LINK_FAULT_PORT_OFFSET (0) + #define RTL8373_ISR_EXT_SERDES_LINK_FAULT_P_ISR_EXT_SERDES_LINK_FAULT_PORT_MASK (0x1F << RTL8373_ISR_EXT_SERDES_LINK_FAULT_P_ISR_EXT_SERDES_LINK_FAULT_PORT_OFFSET) + +#define RTL8373_ISR_EXT_SDS_UPD_PHYSTS0_ADDR (0x5FC4) + #define RTL8373_ISR_EXT_SDS_UPD_PHYSTS0_ISR_EXT_SDS_UPD_PHYSTS_OFFSET (0) + #define RTL8373_ISR_EXT_SDS_UPD_PHYSTS0_ISR_EXT_SDS_UPD_PHYSTS_MASK (0x1F << RTL8373_ISR_EXT_SDS_UPD_PHYSTS0_ISR_EXT_SDS_UPD_PHYSTS_OFFSET) + +#define RTL8373_ISR_EXT_GPIO_ADDR (0x5FC8) + #define RTL8373_ISR_EXT_GPIO_ISR_EXT_GPIO_OFFSET (0) + #define RTL8373_ISR_EXT_GPIO_ISR_EXT_GPIO_MASK (0x7 << RTL8373_ISR_EXT_GPIO_ISR_EXT_GPIO_OFFSET) + +#define RTL8373_ISR_EXT_MISC_ADDR (0x5FCC) + #define RTL8373_ISR_EXT_MISC_ISR_EXT_MACSECWRP_3_0_OFFSET (19) + #define RTL8373_ISR_EXT_MISC_ISR_EXT_MACSECWRP_3_0_MASK (0xF << RTL8373_ISR_EXT_MISC_ISR_EXT_MACSECWRP_3_0_OFFSET) + #define RTL8373_ISR_EXT_MISC_ISR_EXT_PTP1588_OFFSET (18) + #define RTL8373_ISR_EXT_MISC_ISR_EXT_PTP1588_MASK (0x1 << RTL8373_ISR_EXT_MISC_ISR_EXT_PTP1588_OFFSET) + #define RTL8373_ISR_EXT_MISC_ISR_EXT_ROUT_PBUF_OFFSET (17) + #define RTL8373_ISR_EXT_MISC_ISR_EXT_ROUT_PBUF_MASK (0x1 << RTL8373_ISR_EXT_MISC_ISR_EXT_ROUT_PBUF_OFFSET) + #define RTL8373_ISR_EXT_MISC_ISR_EXT_METER_EXCEED_OFFSET (16) + #define RTL8373_ISR_EXT_MISC_ISR_EXT_METER_EXCEED_MASK (0x1 << RTL8373_ISR_EXT_MISC_ISR_EXT_METER_EXCEED_OFFSET) + #define RTL8373_ISR_EXT_MISC_ISR_EXT_LOOP_DETECTION_OFFSET (15) + #define RTL8373_ISR_EXT_MISC_ISR_EXT_LOOP_DETECTION_MASK (0x1 << RTL8373_ISR_EXT_MISC_ISR_EXT_LOOP_DETECTION_OFFSET) + #define RTL8373_ISR_EXT_MISC_ISR_EXT_8051_OFFSET (14) + #define RTL8373_ISR_EXT_MISC_ISR_EXT_8051_MASK (0x1 << RTL8373_ISR_EXT_MISC_ISR_EXT_8051_OFFSET) + #define RTL8373_ISR_EXT_MISC_ISR_EXT_ACL_OFFSET (13) + #define RTL8373_ISR_EXT_MISC_ISR_EXT_ACL_MASK (0x1 << RTL8373_ISR_EXT_MISC_ISR_EXT_ACL_OFFSET) + #define RTL8373_ISR_EXT_MISC_ISR_EXT_AUTO_REC_OFFSET (11) + #define RTL8373_ISR_EXT_MISC_ISR_EXT_AUTO_REC_MASK (0x1 << RTL8373_ISR_EXT_MISC_ISR_EXT_AUTO_REC_OFFSET) + #define RTL8373_ISR_EXT_MISC_ISR_EXT_SAMOVE_OFFSET (10) + #define RTL8373_ISR_EXT_MISC_ISR_EXT_SAMOVE_MASK (0x1 << RTL8373_ISR_EXT_MISC_ISR_EXT_SAMOVE_OFFSET) + #define RTL8373_ISR_EXT_MISC_ISR_EXT_SERDES_RX_SYM_ERR_1_0_OFFSET (7) + #define RTL8373_ISR_EXT_MISC_ISR_EXT_SERDES_RX_SYM_ERR_1_0_MASK (0x3 << RTL8373_ISR_EXT_MISC_ISR_EXT_SERDES_RX_SYM_ERR_1_0_OFFSET) + #define RTL8373_ISR_EXT_MISC_ISR_EXT_SMI_CHECK_REG_4_0_OFFSET (2) + #define RTL8373_ISR_EXT_MISC_ISR_EXT_SMI_CHECK_REG_4_0_MASK (0x1F << RTL8373_ISR_EXT_MISC_ISR_EXT_SMI_CHECK_REG_4_0_OFFSET) + #define RTL8373_ISR_EXT_MISC_ISR_EXT_TM_LOW_OFFSET (1) + #define RTL8373_ISR_EXT_MISC_ISR_EXT_TM_LOW_MASK (0x1 << RTL8373_ISR_EXT_MISC_ISR_EXT_TM_LOW_OFFSET) + #define RTL8373_ISR_EXT_MISC_ISR_EXT_TM_HIGH_OFFSET (0) + #define RTL8373_ISR_EXT_MISC_ISR_EXT_TM_HIGH_MASK (0x1 << RTL8373_ISR_EXT_MISC_ISR_EXT_TM_HIGH_OFFSET) + +/* + * Feature: MIB Control + */ +#define RTL8373_STAT_RST_ADDR (0xF48) + #define RTL8373_STAT_RST_RST_MIB_VAL_OFFSET (1) + #define RTL8373_STAT_RST_RST_MIB_VAL_MASK (0x1 << RTL8373_STAT_RST_RST_MIB_VAL_OFFSET) + #define RTL8373_STAT_RST_RST_GLB_MIB_OFFSET (0) + #define RTL8373_STAT_RST_RST_GLB_MIB_MASK (0x1 << RTL8373_STAT_RST_RST_GLB_MIB_OFFSET) + +#define RTL8373_STAT_PORT_RST_ADDR (0xF4C) + #define RTL8373_STAT_PORT_RST_RST_PORT_FLAG_OFFSET (4) + #define RTL8373_STAT_PORT_RST_RST_PORT_FLAG_MASK (0x1 << RTL8373_STAT_PORT_RST_RST_PORT_FLAG_OFFSET) + #define RTL8373_STAT_PORT_RST_RST_PORT_MIB_OFFSET (0) + #define RTL8373_STAT_PORT_RST_RST_PORT_MIB_MASK (0xF << RTL8373_STAT_PORT_RST_RST_PORT_MIB_OFFSET) + +#define RTL8373_STAT_CTRL_ADDR (0xF50) + #define RTL8373_STAT_CTRL_TX_CNT_TAG_OFFSET (1) + #define RTL8373_STAT_CTRL_TX_CNT_TAG_MASK (0x1 << RTL8373_STAT_CTRL_TX_CNT_TAG_OFFSET) + #define RTL8373_STAT_CTRL_RX_CNT_TAG_OFFSET (0) + #define RTL8373_STAT_CTRL_RX_CNT_TAG_MASK (0x1 << RTL8373_STAT_CTRL_RX_CNT_TAG_OFFSET) + +#define RTL8373_STAT_CNT_SET1_CTRL_ADDR (0xF54) + #define RTL8373_STAT_CNT_SET1_CTRL_CNT_SET1_LEN_MAX_OFFSET (14) + #define RTL8373_STAT_CNT_SET1_CTRL_CNT_SET1_LEN_MAX_MASK (0x3FFF << RTL8373_STAT_CNT_SET1_CTRL_CNT_SET1_LEN_MAX_OFFSET) + #define RTL8373_STAT_CNT_SET1_CTRL_CNT_SET1_LEN_MIN_OFFSET (0) + #define RTL8373_STAT_CNT_SET1_CTRL_CNT_SET1_LEN_MIN_MASK (0x3FFF << RTL8373_STAT_CNT_SET1_CTRL_CNT_SET1_LEN_MIN_OFFSET) + +#define RTL8373_STAT_CNT_SET0_CTRL_ADDR (0xF58) + #define RTL8373_STAT_CNT_SET0_CTRL_CNT_SET0_LEN_MAX_OFFSET (14) + #define RTL8373_STAT_CNT_SET0_CTRL_CNT_SET0_LEN_MAX_MASK (0x3FFF << RTL8373_STAT_CNT_SET0_CTRL_CNT_SET0_LEN_MAX_OFFSET) + #define RTL8373_STAT_CNT_SET0_CTRL_CNT_SET0_LEN_MIN_OFFSET (0) + #define RTL8373_STAT_CNT_SET0_CTRL_CNT_SET0_LEN_MIN_MASK (0x3FFF << RTL8373_STAT_CNT_SET0_CTRL_CNT_SET0_LEN_MIN_OFFSET) + +#define RTL8373_PHY_MIB_GLOBAL_CONFIG_ADDR (0x6F0) + #define RTL8373_PHY_MIB_GLOBAL_CONFIG_START_MIB_OFFSET (11) + #define RTL8373_PHY_MIB_GLOBAL_CONFIG_START_MIB_MASK (0x1 << RTL8373_PHY_MIB_GLOBAL_CONFIG_START_MIB_OFFSET) + #define RTL8373_PHY_MIB_GLOBAL_CONFIG_EN_LATCH_OFFSET (10) + #define RTL8373_PHY_MIB_GLOBAL_CONFIG_EN_LATCH_MASK (0x1 << RTL8373_PHY_MIB_GLOBAL_CONFIG_EN_LATCH_OFFSET) + #define RTL8373_PHY_MIB_GLOBAL_CONFIG_MIB_RESET_VALUE_OFFSET (9) + #define RTL8373_PHY_MIB_GLOBAL_CONFIG_MIB_RESET_VALUE_MASK (0x1 << RTL8373_PHY_MIB_GLOBAL_CONFIG_MIB_RESET_VALUE_OFFSET) + #define RTL8373_PHY_MIB_GLOBAL_CONFIG_MIB_GLOBAL_RESET_OFFSET (8) + #define RTL8373_PHY_MIB_GLOBAL_CONFIG_MIB_GLOBAL_RESET_MASK (0x1 << RTL8373_PHY_MIB_GLOBAL_CONFIG_MIB_GLOBAL_RESET_OFFSET) + #define RTL8373_PHY_MIB_GLOBAL_CONFIG_MIB_PORTN_RESET_OFFSET (0) + #define RTL8373_PHY_MIB_GLOBAL_CONFIG_MIB_PORTN_RESET_MASK (0xFF << RTL8373_PHY_MIB_GLOBAL_CONFIG_MIB_PORTN_RESET_OFFSET) + +#define RTL8373_DEBUG_MIB_RST_ADDR(port) (0xF5C + (((port / 10) << 2))) /* port: 0-9 */ + #define RTL8373_DEBUG_MIB_RST_WRAP_MIB_RST_OFFSET(port) (port % 0xA) + #define RTL8373_DEBUG_MIB_RST_WRAP_MIB_RST_MASK(port) (0x1 << RTL8373_DEBUG_MIB_RST_WRAP_MIB_RST_OFFSET(port)) + +#define RTL8373_INDIRECT_ACCESS_CTRL_ADDR (0xF60) + #define RTL8373_INDIRECT_ACCESS_CTRL_MIB_ID_OFFSET (5) + #define RTL8373_INDIRECT_ACCESS_CTRL_MIB_ID_MASK (0x3F << RTL8373_INDIRECT_ACCESS_CTRL_MIB_ID_OFFSET) + #define RTL8373_INDIRECT_ACCESS_CTRL_PORT_ID_OFFSET (1) + #define RTL8373_INDIRECT_ACCESS_CTRL_PORT_ID_MASK (0xF << RTL8373_INDIRECT_ACCESS_CTRL_PORT_ID_OFFSET) + #define RTL8373_INDIRECT_ACCESS_CTRL_ACC_CMD_OFFSET (0) + #define RTL8373_INDIRECT_ACCESS_CTRL_ACC_CMD_MASK (0x1 << RTL8373_INDIRECT_ACCESS_CTRL_ACC_CMD_OFFSET) + +#define RTL8373_INDIRECT_ACCESS_CNT_L_ADDR (0xF64) + #define RTL8373_INDIRECT_ACCESS_CNT_L_MIB_COUNTER_L_OFFSET (0) + #define RTL8373_INDIRECT_ACCESS_CNT_L_MIB_COUNTER_L_MASK (0xFFFFFFFF << RTL8373_INDIRECT_ACCESS_CNT_L_MIB_COUNTER_L_OFFSET) + +#define RTL8373_INDIRECT_ACCESS_CNT_H_ADDR (0xF68) + #define RTL8373_INDIRECT_ACCESS_CNT_H_MIB_COUNTER_H_OFFSET (0) + #define RTL8373_INDIRECT_ACCESS_CNT_H_MIB_COUNTER_H_MASK (0xFFFFFFFF << RTL8373_INDIRECT_ACCESS_CNT_H_MIB_COUNTER_H_OFFSET) + +/* + * Feature: MIB Counter + */ +#define RTL8373_PHY0_RX_MIB_CNTR0_ADDR (0x710) + #define RTL8373_PHY0_RX_MIB_CNTR0_PHY0_RX_TOTAL_PKTS_H_OFFSET (16) + #define RTL8373_PHY0_RX_MIB_CNTR0_PHY0_RX_TOTAL_PKTS_H_MASK (0xFFFF << RTL8373_PHY0_RX_MIB_CNTR0_PHY0_RX_TOTAL_PKTS_H_OFFSET) + #define RTL8373_PHY0_RX_MIB_CNTR0_PHY0_RX_TOTAL_PKTS_L_OFFSET (0) + #define RTL8373_PHY0_RX_MIB_CNTR0_PHY0_RX_TOTAL_PKTS_L_MASK (0xFFFF << RTL8373_PHY0_RX_MIB_CNTR0_PHY0_RX_TOTAL_PKTS_L_OFFSET) + +#define RTL8373_PHY0_RX_MIB_CNTR1_ADDR (0x714) + #define RTL8373_PHY0_RX_MIB_CNTR1_PHY0_RX_GOOD_OCTETS_H_OFFSET (16) + #define RTL8373_PHY0_RX_MIB_CNTR1_PHY0_RX_GOOD_OCTETS_H_MASK (0xFFFF << RTL8373_PHY0_RX_MIB_CNTR1_PHY0_RX_GOOD_OCTETS_H_OFFSET) + #define RTL8373_PHY0_RX_MIB_CNTR1_PHY0_RX_GOOD_OCTETS_L_OFFSET (0) + #define RTL8373_PHY0_RX_MIB_CNTR1_PHY0_RX_GOOD_OCTETS_L_MASK (0xFFFF << RTL8373_PHY0_RX_MIB_CNTR1_PHY0_RX_GOOD_OCTETS_L_OFFSET) + +#define RTL8373_PHY0_RX_MIB_CNTR2_ADDR (0x718) + #define RTL8373_PHY0_RX_MIB_CNTR2_PHY0_RX_GOOD_PKTS_H_OFFSET (16) + #define RTL8373_PHY0_RX_MIB_CNTR2_PHY0_RX_GOOD_PKTS_H_MASK (0xFFFF << RTL8373_PHY0_RX_MIB_CNTR2_PHY0_RX_GOOD_PKTS_H_OFFSET) + #define RTL8373_PHY0_RX_MIB_CNTR2_PHY0_RX_GOOD_PKTS_L_OFFSET (0) + #define RTL8373_PHY0_RX_MIB_CNTR2_PHY0_RX_GOOD_PKTS_L_MASK (0xFFFF << RTL8373_PHY0_RX_MIB_CNTR2_PHY0_RX_GOOD_PKTS_L_OFFSET) + +#define RTL8373_PHY0_RX_MIB_CNTR3_ADDR (0x71C) + #define RTL8373_PHY0_RX_MIB_CNTR3_PHY0_RX_CRC_ERRORS_OFFSET (16) + #define RTL8373_PHY0_RX_MIB_CNTR3_PHY0_RX_CRC_ERRORS_MASK (0xFFFF << RTL8373_PHY0_RX_MIB_CNTR3_PHY0_RX_CRC_ERRORS_OFFSET) + #define RTL8373_PHY0_RX_MIB_CNTR3_PHY0_RX_SYMBOL_ERRORS_OFFSET (0) + #define RTL8373_PHY0_RX_MIB_CNTR3_PHY0_RX_SYMBOL_ERRORS_MASK (0xFFFF << RTL8373_PHY0_RX_MIB_CNTR3_PHY0_RX_SYMBOL_ERRORS_OFFSET) + +#define RTL8373_PHY0_TX_MIB_CNTR0_ADDR (0x730) + #define RTL8373_PHY0_TX_MIB_CNTR0_PHY0_TX_TOTAL_PKTS_H_OFFSET (16) + #define RTL8373_PHY0_TX_MIB_CNTR0_PHY0_TX_TOTAL_PKTS_H_MASK (0xFFFF << RTL8373_PHY0_TX_MIB_CNTR0_PHY0_TX_TOTAL_PKTS_H_OFFSET) + #define RTL8373_PHY0_TX_MIB_CNTR0_PHY0_TX_TOTAL_PKTS_L_OFFSET (0) + #define RTL8373_PHY0_TX_MIB_CNTR0_PHY0_TX_TOTAL_PKTS_L_MASK (0xFFFF << RTL8373_PHY0_TX_MIB_CNTR0_PHY0_TX_TOTAL_PKTS_L_OFFSET) + +#define RTL8373_PHY0_TX_MIB_CNTR1_ADDR (0x734) + #define RTL8373_PHY0_TX_MIB_CNTR1_PHY0_TX_GOOD_OCTETS_H_OFFSET (16) + #define RTL8373_PHY0_TX_MIB_CNTR1_PHY0_TX_GOOD_OCTETS_H_MASK (0xFFFF << RTL8373_PHY0_TX_MIB_CNTR1_PHY0_TX_GOOD_OCTETS_H_OFFSET) + #define RTL8373_PHY0_TX_MIB_CNTR1_PHY0_TX_GOOD_OCTETS_L_OFFSET (0) + #define RTL8373_PHY0_TX_MIB_CNTR1_PHY0_TX_GOOD_OCTETS_L_MASK (0xFFFF << RTL8373_PHY0_TX_MIB_CNTR1_PHY0_TX_GOOD_OCTETS_L_OFFSET) + +#define RTL8373_PHY0_TX_MIB_CNTR2_ADDR (0x738) + #define RTL8373_PHY0_TX_MIB_CNTR2_PHY0_TX_GOOD_PKTS_H_OFFSET (16) + #define RTL8373_PHY0_TX_MIB_CNTR2_PHY0_TX_GOOD_PKTS_H_MASK (0xFFFF << RTL8373_PHY0_TX_MIB_CNTR2_PHY0_TX_GOOD_PKTS_H_OFFSET) + #define RTL8373_PHY0_TX_MIB_CNTR2_PHY0_TX_GOOD_PKTS_L_OFFSET (0) + #define RTL8373_PHY0_TX_MIB_CNTR2_PHY0_TX_GOOD_PKTS_L_MASK (0xFFFF << RTL8373_PHY0_TX_MIB_CNTR2_PHY0_TX_GOOD_PKTS_L_OFFSET) + +#define RTL8373_PHY0_TX_MIB_CNTR3_ADDR (0x73C) + #define RTL8373_PHY0_TX_MIB_CNTR3_PHY0_TX_CRC_ERRORS_OFFSET (0) + #define RTL8373_PHY0_TX_MIB_CNTR3_PHY0_TX_CRC_ERRORS_MASK (0xFFFF << RTL8373_PHY0_TX_MIB_CNTR3_PHY0_TX_CRC_ERRORS_OFFSET) + +#define RTL8373_PHY1_RX_MIB_CNTR0_ADDR (0x750) + #define RTL8373_PHY1_RX_MIB_CNTR0_PHY1_RX_TOTAL_PKTS_H_OFFSET (16) + #define RTL8373_PHY1_RX_MIB_CNTR0_PHY1_RX_TOTAL_PKTS_H_MASK (0xFFFF << RTL8373_PHY1_RX_MIB_CNTR0_PHY1_RX_TOTAL_PKTS_H_OFFSET) + #define RTL8373_PHY1_RX_MIB_CNTR0_PHY1_RX_TOTAL_PKTS_L_OFFSET (0) + #define RTL8373_PHY1_RX_MIB_CNTR0_PHY1_RX_TOTAL_PKTS_L_MASK (0xFFFF << RTL8373_PHY1_RX_MIB_CNTR0_PHY1_RX_TOTAL_PKTS_L_OFFSET) + +#define RTL8373_PHY1_RX_MIB_CNTR1_ADDR (0x754) + #define RTL8373_PHY1_RX_MIB_CNTR1_PHY1_RX_GOOD_OCTETS_H_OFFSET (16) + #define RTL8373_PHY1_RX_MIB_CNTR1_PHY1_RX_GOOD_OCTETS_H_MASK (0xFFFF << RTL8373_PHY1_RX_MIB_CNTR1_PHY1_RX_GOOD_OCTETS_H_OFFSET) + #define RTL8373_PHY1_RX_MIB_CNTR1_PHY1_RX_GOOD_OCTETS_L_OFFSET (0) + #define RTL8373_PHY1_RX_MIB_CNTR1_PHY1_RX_GOOD_OCTETS_L_MASK (0xFFFF << RTL8373_PHY1_RX_MIB_CNTR1_PHY1_RX_GOOD_OCTETS_L_OFFSET) + +#define RTL8373_PHY1_RX_MIB_CNTR2_ADDR (0x758) + #define RTL8373_PHY1_RX_MIB_CNTR2_PHY1_RX_GOOD_PKTS_H_OFFSET (16) + #define RTL8373_PHY1_RX_MIB_CNTR2_PHY1_RX_GOOD_PKTS_H_MASK (0xFFFF << RTL8373_PHY1_RX_MIB_CNTR2_PHY1_RX_GOOD_PKTS_H_OFFSET) + #define RTL8373_PHY1_RX_MIB_CNTR2_PHY1_RX_GOOD_PKTS_L_OFFSET (0) + #define RTL8373_PHY1_RX_MIB_CNTR2_PHY1_RX_GOOD_PKTS_L_MASK (0xFFFF << RTL8373_PHY1_RX_MIB_CNTR2_PHY1_RX_GOOD_PKTS_L_OFFSET) + +#define RTL8373_PHY1_RX_MIB_CNTR3_ADDR (0x75C) + #define RTL8373_PHY1_RX_MIB_CNTR3_PHY1_RX_CRC_ERRORS_OFFSET (16) + #define RTL8373_PHY1_RX_MIB_CNTR3_PHY1_RX_CRC_ERRORS_MASK (0xFFFF << RTL8373_PHY1_RX_MIB_CNTR3_PHY1_RX_CRC_ERRORS_OFFSET) + #define RTL8373_PHY1_RX_MIB_CNTR3_PHY1_RX_SYMBOL_ERRORS_OFFSET (0) + #define RTL8373_PHY1_RX_MIB_CNTR3_PHY1_RX_SYMBOL_ERRORS_MASK (0xFFFF << RTL8373_PHY1_RX_MIB_CNTR3_PHY1_RX_SYMBOL_ERRORS_OFFSET) + +#define RTL8373_PHY1_TX_MIB_CNTR0_ADDR (0x770) + #define RTL8373_PHY1_TX_MIB_CNTR0_PHY1_TX_TOTAL_PKTS_H_OFFSET (16) + #define RTL8373_PHY1_TX_MIB_CNTR0_PHY1_TX_TOTAL_PKTS_H_MASK (0xFFFF << RTL8373_PHY1_TX_MIB_CNTR0_PHY1_TX_TOTAL_PKTS_H_OFFSET) + #define RTL8373_PHY1_TX_MIB_CNTR0_PHY1_TX_TOTAL_PKTS_L_OFFSET (0) + #define RTL8373_PHY1_TX_MIB_CNTR0_PHY1_TX_TOTAL_PKTS_L_MASK (0xFFFF << RTL8373_PHY1_TX_MIB_CNTR0_PHY1_TX_TOTAL_PKTS_L_OFFSET) + +#define RTL8373_PHY1_TX_MIB_CNTR1_ADDR (0x774) + #define RTL8373_PHY1_TX_MIB_CNTR1_PHY1_TX_GOOD_OCTETS_H_OFFSET (16) + #define RTL8373_PHY1_TX_MIB_CNTR1_PHY1_TX_GOOD_OCTETS_H_MASK (0xFFFF << RTL8373_PHY1_TX_MIB_CNTR1_PHY1_TX_GOOD_OCTETS_H_OFFSET) + #define RTL8373_PHY1_TX_MIB_CNTR1_PHY1_TX_GOOD_OCTETS_L_OFFSET (0) + #define RTL8373_PHY1_TX_MIB_CNTR1_PHY1_TX_GOOD_OCTETS_L_MASK (0xFFFF << RTL8373_PHY1_TX_MIB_CNTR1_PHY1_TX_GOOD_OCTETS_L_OFFSET) + +#define RTL8373_PHY1_TX_MIB_CNTR2_ADDR (0x778) + #define RTL8373_PHY1_TX_MIB_CNTR2_PHY1_TX_GOOD_PKTS_H_OFFSET (16) + #define RTL8373_PHY1_TX_MIB_CNTR2_PHY1_TX_GOOD_PKTS_H_MASK (0xFFFF << RTL8373_PHY1_TX_MIB_CNTR2_PHY1_TX_GOOD_PKTS_H_OFFSET) + #define RTL8373_PHY1_TX_MIB_CNTR2_PHY1_TX_GOOD_PKTS_L_OFFSET (0) + #define RTL8373_PHY1_TX_MIB_CNTR2_PHY1_TX_GOOD_PKTS_L_MASK (0xFFFF << RTL8373_PHY1_TX_MIB_CNTR2_PHY1_TX_GOOD_PKTS_L_OFFSET) + +#define RTL8373_PHY1_TX_MIB_CNTR3_ADDR (0x77C) + #define RTL8373_PHY1_TX_MIB_CNTR3_PHY1_TX_CRC_ERRORS_OFFSET (0) + #define RTL8373_PHY1_TX_MIB_CNTR3_PHY1_TX_CRC_ERRORS_MASK (0xFFFF << RTL8373_PHY1_TX_MIB_CNTR3_PHY1_TX_CRC_ERRORS_OFFSET) + +#define RTL8373_PHY2_RX_MIB_CNTR0_ADDR (0x790) + #define RTL8373_PHY2_RX_MIB_CNTR0_PHY2_RX_TOTAL_PKTS_H_OFFSET (16) + #define RTL8373_PHY2_RX_MIB_CNTR0_PHY2_RX_TOTAL_PKTS_H_MASK (0xFFFF << RTL8373_PHY2_RX_MIB_CNTR0_PHY2_RX_TOTAL_PKTS_H_OFFSET) + #define RTL8373_PHY2_RX_MIB_CNTR0_PHY2_RX_TOTAL_PKTS_L_OFFSET (0) + #define RTL8373_PHY2_RX_MIB_CNTR0_PHY2_RX_TOTAL_PKTS_L_MASK (0xFFFF << RTL8373_PHY2_RX_MIB_CNTR0_PHY2_RX_TOTAL_PKTS_L_OFFSET) + +#define RTL8373_PHY2_RX_MIB_CNTR1_ADDR (0x794) + #define RTL8373_PHY2_RX_MIB_CNTR1_PHY2_RX_GOOD_OCTETS_H_OFFSET (16) + #define RTL8373_PHY2_RX_MIB_CNTR1_PHY2_RX_GOOD_OCTETS_H_MASK (0xFFFF << RTL8373_PHY2_RX_MIB_CNTR1_PHY2_RX_GOOD_OCTETS_H_OFFSET) + #define RTL8373_PHY2_RX_MIB_CNTR1_PHY2_RX_GOOD_OCTETS_L_OFFSET (0) + #define RTL8373_PHY2_RX_MIB_CNTR1_PHY2_RX_GOOD_OCTETS_L_MASK (0xFFFF << RTL8373_PHY2_RX_MIB_CNTR1_PHY2_RX_GOOD_OCTETS_L_OFFSET) + +#define RTL8373_PHY2_RX_MIB_CNTR2_ADDR (0x798) + #define RTL8373_PHY2_RX_MIB_CNTR2_PHY2_RX_GOOD_PKTS_H_OFFSET (16) + #define RTL8373_PHY2_RX_MIB_CNTR2_PHY2_RX_GOOD_PKTS_H_MASK (0xFFFF << RTL8373_PHY2_RX_MIB_CNTR2_PHY2_RX_GOOD_PKTS_H_OFFSET) + #define RTL8373_PHY2_RX_MIB_CNTR2_PHY2_RX_GOOD_PKTS_L_OFFSET (0) + #define RTL8373_PHY2_RX_MIB_CNTR2_PHY2_RX_GOOD_PKTS_L_MASK (0xFFFF << RTL8373_PHY2_RX_MIB_CNTR2_PHY2_RX_GOOD_PKTS_L_OFFSET) + +#define RTL8373_PHY2_RX_MIB_CNTR3_ADDR (0x79C) + #define RTL8373_PHY2_RX_MIB_CNTR3_PHY2_RX_CRC_ERRORS_OFFSET (16) + #define RTL8373_PHY2_RX_MIB_CNTR3_PHY2_RX_CRC_ERRORS_MASK (0xFFFF << RTL8373_PHY2_RX_MIB_CNTR3_PHY2_RX_CRC_ERRORS_OFFSET) + #define RTL8373_PHY2_RX_MIB_CNTR3_PHY2_RX_SYMBOL_ERRORS_OFFSET (0) + #define RTL8373_PHY2_RX_MIB_CNTR3_PHY2_RX_SYMBOL_ERRORS_MASK (0xFFFF << RTL8373_PHY2_RX_MIB_CNTR3_PHY2_RX_SYMBOL_ERRORS_OFFSET) + +#define RTL8373_PHY2_TX_MIB_CNTR0_ADDR (0x7B0) + #define RTL8373_PHY2_TX_MIB_CNTR0_PHY2_TX_TOTAL_PKTS_H_OFFSET (16) + #define RTL8373_PHY2_TX_MIB_CNTR0_PHY2_TX_TOTAL_PKTS_H_MASK (0xFFFF << RTL8373_PHY2_TX_MIB_CNTR0_PHY2_TX_TOTAL_PKTS_H_OFFSET) + #define RTL8373_PHY2_TX_MIB_CNTR0_PHY2_TX_TOTAL_PKTS_L_OFFSET (0) + #define RTL8373_PHY2_TX_MIB_CNTR0_PHY2_TX_TOTAL_PKTS_L_MASK (0xFFFF << RTL8373_PHY2_TX_MIB_CNTR0_PHY2_TX_TOTAL_PKTS_L_OFFSET) + +#define RTL8373_PHY2_TX_MIB_CNTR1_ADDR (0x7B4) + #define RTL8373_PHY2_TX_MIB_CNTR1_PHY2_TX_GOOD_OCTETS_H_OFFSET (16) + #define RTL8373_PHY2_TX_MIB_CNTR1_PHY2_TX_GOOD_OCTETS_H_MASK (0xFFFF << RTL8373_PHY2_TX_MIB_CNTR1_PHY2_TX_GOOD_OCTETS_H_OFFSET) + #define RTL8373_PHY2_TX_MIB_CNTR1_PHY2_TX_GOOD_OCTETS_L_OFFSET (0) + #define RTL8373_PHY2_TX_MIB_CNTR1_PHY2_TX_GOOD_OCTETS_L_MASK (0xFFFF << RTL8373_PHY2_TX_MIB_CNTR1_PHY2_TX_GOOD_OCTETS_L_OFFSET) + +#define RTL8373_PHY2_TX_MIB_CNTR2_ADDR (0x7B8) + #define RTL8373_PHY2_TX_MIB_CNTR2_PHY2_TX_GOOD_PKTS_H_OFFSET (16) + #define RTL8373_PHY2_TX_MIB_CNTR2_PHY2_TX_GOOD_PKTS_H_MASK (0xFFFF << RTL8373_PHY2_TX_MIB_CNTR2_PHY2_TX_GOOD_PKTS_H_OFFSET) + #define RTL8373_PHY2_TX_MIB_CNTR2_PHY2_TX_GOOD_PKTS_L_OFFSET (0) + #define RTL8373_PHY2_TX_MIB_CNTR2_PHY2_TX_GOOD_PKTS_L_MASK (0xFFFF << RTL8373_PHY2_TX_MIB_CNTR2_PHY2_TX_GOOD_PKTS_L_OFFSET) + +#define RTL8373_PHY2_TX_MIB_CNTR3_ADDR (0x7BC) + #define RTL8373_PHY2_TX_MIB_CNTR3_PHY2_TX_CRC_ERRORS_OFFSET (0) + #define RTL8373_PHY2_TX_MIB_CNTR3_PHY2_TX_CRC_ERRORS_MASK (0xFFFF << RTL8373_PHY2_TX_MIB_CNTR3_PHY2_TX_CRC_ERRORS_OFFSET) + +#define RTL8373_PHY3_RX_MIB_CNTR0_ADDR (0x7D0) + #define RTL8373_PHY3_RX_MIB_CNTR0_PHY3_RX_TOTAL_PKTS_H_OFFSET (16) + #define RTL8373_PHY3_RX_MIB_CNTR0_PHY3_RX_TOTAL_PKTS_H_MASK (0xFFFF << RTL8373_PHY3_RX_MIB_CNTR0_PHY3_RX_TOTAL_PKTS_H_OFFSET) + #define RTL8373_PHY3_RX_MIB_CNTR0_PHY3_RX_TOTAL_PKTS_L_OFFSET (0) + #define RTL8373_PHY3_RX_MIB_CNTR0_PHY3_RX_TOTAL_PKTS_L_MASK (0xFFFF << RTL8373_PHY3_RX_MIB_CNTR0_PHY3_RX_TOTAL_PKTS_L_OFFSET) + +#define RTL8373_PHY3_RX_MIB_CNTR1_ADDR (0x7D4) + #define RTL8373_PHY3_RX_MIB_CNTR1_PHY3_RX_GOOD_OCTETS_H_OFFSET (16) + #define RTL8373_PHY3_RX_MIB_CNTR1_PHY3_RX_GOOD_OCTETS_H_MASK (0xFFFF << RTL8373_PHY3_RX_MIB_CNTR1_PHY3_RX_GOOD_OCTETS_H_OFFSET) + #define RTL8373_PHY3_RX_MIB_CNTR1_PHY3_RX_GOOD_OCTETS_L_OFFSET (0) + #define RTL8373_PHY3_RX_MIB_CNTR1_PHY3_RX_GOOD_OCTETS_L_MASK (0xFFFF << RTL8373_PHY3_RX_MIB_CNTR1_PHY3_RX_GOOD_OCTETS_L_OFFSET) + +#define RTL8373_PHY3_RX_MIB_CNTR2_ADDR (0x7D8) + #define RTL8373_PHY3_RX_MIB_CNTR2_PHY3_RX_GOOD_PKTS_H_OFFSET (16) + #define RTL8373_PHY3_RX_MIB_CNTR2_PHY3_RX_GOOD_PKTS_H_MASK (0xFFFF << RTL8373_PHY3_RX_MIB_CNTR2_PHY3_RX_GOOD_PKTS_H_OFFSET) + #define RTL8373_PHY3_RX_MIB_CNTR2_PHY3_RX_GOOD_PKTS_L_OFFSET (0) + #define RTL8373_PHY3_RX_MIB_CNTR2_PHY3_RX_GOOD_PKTS_L_MASK (0xFFFF << RTL8373_PHY3_RX_MIB_CNTR2_PHY3_RX_GOOD_PKTS_L_OFFSET) + +#define RTL8373_PHY3_RX_MIB_CNTR3_ADDR (0x7DC) + #define RTL8373_PHY3_RX_MIB_CNTR3_PHY3_RX_CRC_ERRORS_OFFSET (16) + #define RTL8373_PHY3_RX_MIB_CNTR3_PHY3_RX_CRC_ERRORS_MASK (0xFFFF << RTL8373_PHY3_RX_MIB_CNTR3_PHY3_RX_CRC_ERRORS_OFFSET) + #define RTL8373_PHY3_RX_MIB_CNTR3_PHY3_RX_SYMBOL_ERRORS_OFFSET (0) + #define RTL8373_PHY3_RX_MIB_CNTR3_PHY3_RX_SYMBOL_ERRORS_MASK (0xFFFF << RTL8373_PHY3_RX_MIB_CNTR3_PHY3_RX_SYMBOL_ERRORS_OFFSET) + +#define RTL8373_PHY3_TX_MIB_CNTR0_ADDR (0x7F0) + #define RTL8373_PHY3_TX_MIB_CNTR0_PHY3_TX_TOTAL_PKTS_H_OFFSET (16) + #define RTL8373_PHY3_TX_MIB_CNTR0_PHY3_TX_TOTAL_PKTS_H_MASK (0xFFFF << RTL8373_PHY3_TX_MIB_CNTR0_PHY3_TX_TOTAL_PKTS_H_OFFSET) + #define RTL8373_PHY3_TX_MIB_CNTR0_PHY3_TX_TOTAL_PKTS_L_OFFSET (0) + #define RTL8373_PHY3_TX_MIB_CNTR0_PHY3_TX_TOTAL_PKTS_L_MASK (0xFFFF << RTL8373_PHY3_TX_MIB_CNTR0_PHY3_TX_TOTAL_PKTS_L_OFFSET) + +#define RTL8373_PHY3_TX_MIB_CNTR1_ADDR (0x7F4) + #define RTL8373_PHY3_TX_MIB_CNTR1_PHY3_TX_GOOD_OCTETS_H_OFFSET (16) + #define RTL8373_PHY3_TX_MIB_CNTR1_PHY3_TX_GOOD_OCTETS_H_MASK (0xFFFF << RTL8373_PHY3_TX_MIB_CNTR1_PHY3_TX_GOOD_OCTETS_H_OFFSET) + #define RTL8373_PHY3_TX_MIB_CNTR1_PHY3_TX_GOOD_OCTETS_L_OFFSET (0) + #define RTL8373_PHY3_TX_MIB_CNTR1_PHY3_TX_GOOD_OCTETS_L_MASK (0xFFFF << RTL8373_PHY3_TX_MIB_CNTR1_PHY3_TX_GOOD_OCTETS_L_OFFSET) + +#define RTL8373_PHY3_TX_MIB_CNTR2_ADDR (0x7F8) + #define RTL8373_PHY3_TX_MIB_CNTR2_PHY3_TX_GOOD_PKTS_H_OFFSET (16) + #define RTL8373_PHY3_TX_MIB_CNTR2_PHY3_TX_GOOD_PKTS_H_MASK (0xFFFF << RTL8373_PHY3_TX_MIB_CNTR2_PHY3_TX_GOOD_PKTS_H_OFFSET) + #define RTL8373_PHY3_TX_MIB_CNTR2_PHY3_TX_GOOD_PKTS_L_OFFSET (0) + #define RTL8373_PHY3_TX_MIB_CNTR2_PHY3_TX_GOOD_PKTS_L_MASK (0xFFFF << RTL8373_PHY3_TX_MIB_CNTR2_PHY3_TX_GOOD_PKTS_L_OFFSET) + +#define RTL8373_PHY3_TX_MIB_CNTR3_ADDR (0x7FC) + #define RTL8373_PHY3_TX_MIB_CNTR3_PHY3_TX_CRC_ERRORS_OFFSET (0) + #define RTL8373_PHY3_TX_MIB_CNTR3_PHY3_TX_CRC_ERRORS_MASK (0xFFFF << RTL8373_PHY3_TX_MIB_CNTR3_PHY3_TX_CRC_ERRORS_OFFSET) + +#define RTL8373_SDS_CH0_RX_MIB_CNTR0_ADDR (0x810) + #define RTL8373_SDS_CH0_RX_MIB_CNTR0_SDS_CH0_RX_TOTAL_PKTS_H_OFFSET (16) + #define RTL8373_SDS_CH0_RX_MIB_CNTR0_SDS_CH0_RX_TOTAL_PKTS_H_MASK (0xFFFF << RTL8373_SDS_CH0_RX_MIB_CNTR0_SDS_CH0_RX_TOTAL_PKTS_H_OFFSET) + #define RTL8373_SDS_CH0_RX_MIB_CNTR0_SDS_CH0_RX_TOTAL_PKTS_L_OFFSET (0) + #define RTL8373_SDS_CH0_RX_MIB_CNTR0_SDS_CH0_RX_TOTAL_PKTS_L_MASK (0xFFFF << RTL8373_SDS_CH0_RX_MIB_CNTR0_SDS_CH0_RX_TOTAL_PKTS_L_OFFSET) + +#define RTL8373_SDS_CH0_RX_MIB_CNTR1_ADDR (0x814) + #define RTL8373_SDS_CH0_RX_MIB_CNTR1_SDS_CH0_RX_GOOD_OCTETS_H_OFFSET (16) + #define RTL8373_SDS_CH0_RX_MIB_CNTR1_SDS_CH0_RX_GOOD_OCTETS_H_MASK (0xFFFF << RTL8373_SDS_CH0_RX_MIB_CNTR1_SDS_CH0_RX_GOOD_OCTETS_H_OFFSET) + #define RTL8373_SDS_CH0_RX_MIB_CNTR1_SDS_CH0_RX_GOOD_OCTETS_L_OFFSET (0) + #define RTL8373_SDS_CH0_RX_MIB_CNTR1_SDS_CH0_RX_GOOD_OCTETS_L_MASK (0xFFFF << RTL8373_SDS_CH0_RX_MIB_CNTR1_SDS_CH0_RX_GOOD_OCTETS_L_OFFSET) + +#define RTL8373_SDS_CH0_RX_MIB_CNTR2_ADDR (0x818) + #define RTL8373_SDS_CH0_RX_MIB_CNTR2_SDS_CH0_RX_GOOD_PKTS_H_OFFSET (16) + #define RTL8373_SDS_CH0_RX_MIB_CNTR2_SDS_CH0_RX_GOOD_PKTS_H_MASK (0xFFFF << RTL8373_SDS_CH0_RX_MIB_CNTR2_SDS_CH0_RX_GOOD_PKTS_H_OFFSET) + #define RTL8373_SDS_CH0_RX_MIB_CNTR2_SDS_CH0_RX_GOOD_PKTS_L_OFFSET (0) + #define RTL8373_SDS_CH0_RX_MIB_CNTR2_SDS_CH0_RX_GOOD_PKTS_L_MASK (0xFFFF << RTL8373_SDS_CH0_RX_MIB_CNTR2_SDS_CH0_RX_GOOD_PKTS_L_OFFSET) + +#define RTL8373_SDS_CH0_RX_MIB_CNTR3_ADDR (0x81C) + #define RTL8373_SDS_CH0_RX_MIB_CNTR3_SDS_CH0_RX_CRC_ERRORS_OFFSET (16) + #define RTL8373_SDS_CH0_RX_MIB_CNTR3_SDS_CH0_RX_CRC_ERRORS_MASK (0xFFFF << RTL8373_SDS_CH0_RX_MIB_CNTR3_SDS_CH0_RX_CRC_ERRORS_OFFSET) + #define RTL8373_SDS_CH0_RX_MIB_CNTR3_SDS_CH0_RX_SYMBOL_ERRORS_OFFSET (0) + #define RTL8373_SDS_CH0_RX_MIB_CNTR3_SDS_CH0_RX_SYMBOL_ERRORS_MASK (0xFFFF << RTL8373_SDS_CH0_RX_MIB_CNTR3_SDS_CH0_RX_SYMBOL_ERRORS_OFFSET) + +#define RTL8373_SDS_CH0_TX_MIB_CNTR0_ADDR (0x830) + #define RTL8373_SDS_CH0_TX_MIB_CNTR0_SDS_CH0_TX_TOTAL_PKTS_H_OFFSET (16) + #define RTL8373_SDS_CH0_TX_MIB_CNTR0_SDS_CH0_TX_TOTAL_PKTS_H_MASK (0xFFFF << RTL8373_SDS_CH0_TX_MIB_CNTR0_SDS_CH0_TX_TOTAL_PKTS_H_OFFSET) + #define RTL8373_SDS_CH0_TX_MIB_CNTR0_SDS_CH0_TX_TOTAL_PKTS_L_OFFSET (0) + #define RTL8373_SDS_CH0_TX_MIB_CNTR0_SDS_CH0_TX_TOTAL_PKTS_L_MASK (0xFFFF << RTL8373_SDS_CH0_TX_MIB_CNTR0_SDS_CH0_TX_TOTAL_PKTS_L_OFFSET) + +#define RTL8373_SDS_CH0_TX_MIB_CNTR1_ADDR (0x834) + #define RTL8373_SDS_CH0_TX_MIB_CNTR1_SDS_CH0_TX_GOOD_OCTETS_H_OFFSET (16) + #define RTL8373_SDS_CH0_TX_MIB_CNTR1_SDS_CH0_TX_GOOD_OCTETS_H_MASK (0xFFFF << RTL8373_SDS_CH0_TX_MIB_CNTR1_SDS_CH0_TX_GOOD_OCTETS_H_OFFSET) + #define RTL8373_SDS_CH0_TX_MIB_CNTR1_SDS_CH0_TX_GOOD_OCTETS_L_OFFSET (0) + #define RTL8373_SDS_CH0_TX_MIB_CNTR1_SDS_CH0_TX_GOOD_OCTETS_L_MASK (0xFFFF << RTL8373_SDS_CH0_TX_MIB_CNTR1_SDS_CH0_TX_GOOD_OCTETS_L_OFFSET) + +#define RTL8373_SDS_CH0_TX_MIB_CNTR2_ADDR (0x838) + #define RTL8373_SDS_CH0_TX_MIB_CNTR2_SDS_CH0_TX_GOOD_PKTS_H_OFFSET (16) + #define RTL8373_SDS_CH0_TX_MIB_CNTR2_SDS_CH0_TX_GOOD_PKTS_H_MASK (0xFFFF << RTL8373_SDS_CH0_TX_MIB_CNTR2_SDS_CH0_TX_GOOD_PKTS_H_OFFSET) + #define RTL8373_SDS_CH0_TX_MIB_CNTR2_SDS_CH0_TX_GOOD_PKTS_L_OFFSET (0) + #define RTL8373_SDS_CH0_TX_MIB_CNTR2_SDS_CH0_TX_GOOD_PKTS_L_MASK (0xFFFF << RTL8373_SDS_CH0_TX_MIB_CNTR2_SDS_CH0_TX_GOOD_PKTS_L_OFFSET) + +#define RTL8373_SDS_CH0_TX_MIB_CNTR3_ADDR (0x83C) + #define RTL8373_SDS_CH0_TX_MIB_CNTR3_SDS_CH0_TX_CRC_ERRORS_OFFSET (0) + #define RTL8373_SDS_CH0_TX_MIB_CNTR3_SDS_CH0_TX_CRC_ERRORS_MASK (0xFFFF << RTL8373_SDS_CH0_TX_MIB_CNTR3_SDS_CH0_TX_CRC_ERRORS_OFFSET) + +#define RTL8373_SDS_CH1_RX_MIB_CNTR0_ADDR (0x850) + #define RTL8373_SDS_CH1_RX_MIB_CNTR0_SDS_CH1_RX_TOTAL_PKTS_H_OFFSET (16) + #define RTL8373_SDS_CH1_RX_MIB_CNTR0_SDS_CH1_RX_TOTAL_PKTS_H_MASK (0xFFFF << RTL8373_SDS_CH1_RX_MIB_CNTR0_SDS_CH1_RX_TOTAL_PKTS_H_OFFSET) + #define RTL8373_SDS_CH1_RX_MIB_CNTR0_SDS_CH1_RX_TOTAL_PKTS_L_OFFSET (0) + #define RTL8373_SDS_CH1_RX_MIB_CNTR0_SDS_CH1_RX_TOTAL_PKTS_L_MASK (0xFFFF << RTL8373_SDS_CH1_RX_MIB_CNTR0_SDS_CH1_RX_TOTAL_PKTS_L_OFFSET) + +#define RTL8373_SDS_CH1_RX_MIB_CNTR1_ADDR (0x854) + #define RTL8373_SDS_CH1_RX_MIB_CNTR1_SDS_CH1_RX_GOOD_OCTETS_H_OFFSET (16) + #define RTL8373_SDS_CH1_RX_MIB_CNTR1_SDS_CH1_RX_GOOD_OCTETS_H_MASK (0xFFFF << RTL8373_SDS_CH1_RX_MIB_CNTR1_SDS_CH1_RX_GOOD_OCTETS_H_OFFSET) + #define RTL8373_SDS_CH1_RX_MIB_CNTR1_SDS_CH1_RX_GOOD_OCTETS_L_OFFSET (0) + #define RTL8373_SDS_CH1_RX_MIB_CNTR1_SDS_CH1_RX_GOOD_OCTETS_L_MASK (0xFFFF << RTL8373_SDS_CH1_RX_MIB_CNTR1_SDS_CH1_RX_GOOD_OCTETS_L_OFFSET) + +#define RTL8373_SDS_CH1_RX_MIB_CNTR2_ADDR (0x858) + #define RTL8373_SDS_CH1_RX_MIB_CNTR2_SDS_CH1_RX_GOOD_PKTS_H_OFFSET (16) + #define RTL8373_SDS_CH1_RX_MIB_CNTR2_SDS_CH1_RX_GOOD_PKTS_H_MASK (0xFFFF << RTL8373_SDS_CH1_RX_MIB_CNTR2_SDS_CH1_RX_GOOD_PKTS_H_OFFSET) + #define RTL8373_SDS_CH1_RX_MIB_CNTR2_SDS_CH1_RX_GOOD_PKTS_L_OFFSET (0) + #define RTL8373_SDS_CH1_RX_MIB_CNTR2_SDS_CH1_RX_GOOD_PKTS_L_MASK (0xFFFF << RTL8373_SDS_CH1_RX_MIB_CNTR2_SDS_CH1_RX_GOOD_PKTS_L_OFFSET) + +#define RTL8373_SDS_CH1_RX_MIB_CNTR3_ADDR (0x85C) + #define RTL8373_SDS_CH1_RX_MIB_CNTR3_SDS_CH1_RX_CRC_ERRORS_OFFSET (16) + #define RTL8373_SDS_CH1_RX_MIB_CNTR3_SDS_CH1_RX_CRC_ERRORS_MASK (0xFFFF << RTL8373_SDS_CH1_RX_MIB_CNTR3_SDS_CH1_RX_CRC_ERRORS_OFFSET) + #define RTL8373_SDS_CH1_RX_MIB_CNTR3_SDS_CH1_RX_SYMBOL_ERRORS_OFFSET (0) + #define RTL8373_SDS_CH1_RX_MIB_CNTR3_SDS_CH1_RX_SYMBOL_ERRORS_MASK (0xFFFF << RTL8373_SDS_CH1_RX_MIB_CNTR3_SDS_CH1_RX_SYMBOL_ERRORS_OFFSET) + +#define RTL8373_SDS_CH1_TX_MIB_CNTR0_ADDR (0x870) + #define RTL8373_SDS_CH1_TX_MIB_CNTR0_SDS_CH1_TX_TOTAL_PKTS_H_OFFSET (16) + #define RTL8373_SDS_CH1_TX_MIB_CNTR0_SDS_CH1_TX_TOTAL_PKTS_H_MASK (0xFFFF << RTL8373_SDS_CH1_TX_MIB_CNTR0_SDS_CH1_TX_TOTAL_PKTS_H_OFFSET) + #define RTL8373_SDS_CH1_TX_MIB_CNTR0_SDS_CH1_TX_TOTAL_PKTS_L_OFFSET (0) + #define RTL8373_SDS_CH1_TX_MIB_CNTR0_SDS_CH1_TX_TOTAL_PKTS_L_MASK (0xFFFF << RTL8373_SDS_CH1_TX_MIB_CNTR0_SDS_CH1_TX_TOTAL_PKTS_L_OFFSET) + +#define RTL8373_SDS_CH1_TX_MIB_CNTR1_ADDR (0x874) + #define RTL8373_SDS_CH1_TX_MIB_CNTR1_SDS_CH1_TX_GOOD_OCTETS_H_OFFSET (16) + #define RTL8373_SDS_CH1_TX_MIB_CNTR1_SDS_CH1_TX_GOOD_OCTETS_H_MASK (0xFFFF << RTL8373_SDS_CH1_TX_MIB_CNTR1_SDS_CH1_TX_GOOD_OCTETS_H_OFFSET) + #define RTL8373_SDS_CH1_TX_MIB_CNTR1_SDS_CH1_TX_GOOD_OCTETS_L_OFFSET (0) + #define RTL8373_SDS_CH1_TX_MIB_CNTR1_SDS_CH1_TX_GOOD_OCTETS_L_MASK (0xFFFF << RTL8373_SDS_CH1_TX_MIB_CNTR1_SDS_CH1_TX_GOOD_OCTETS_L_OFFSET) + +#define RTL8373_SDS_CH1_TX_MIB_CNTR2_ADDR (0x878) + #define RTL8373_SDS_CH1_TX_MIB_CNTR2_SDS_CH1_TX_GOOD_PKTS_H_OFFSET (16) + #define RTL8373_SDS_CH1_TX_MIB_CNTR2_SDS_CH1_TX_GOOD_PKTS_H_MASK (0xFFFF << RTL8373_SDS_CH1_TX_MIB_CNTR2_SDS_CH1_TX_GOOD_PKTS_H_OFFSET) + #define RTL8373_SDS_CH1_TX_MIB_CNTR2_SDS_CH1_TX_GOOD_PKTS_L_OFFSET (0) + #define RTL8373_SDS_CH1_TX_MIB_CNTR2_SDS_CH1_TX_GOOD_PKTS_L_MASK (0xFFFF << RTL8373_SDS_CH1_TX_MIB_CNTR2_SDS_CH1_TX_GOOD_PKTS_L_OFFSET) + +#define RTL8373_SDS_CH1_TX_MIB_CNTR3_ADDR (0x87C) + #define RTL8373_SDS_CH1_TX_MIB_CNTR3_SDS_CH1_TX_CRC_ERRORS_OFFSET (0) + #define RTL8373_SDS_CH1_TX_MIB_CNTR3_SDS_CH1_TX_CRC_ERRORS_MASK (0xFFFF << RTL8373_SDS_CH1_TX_MIB_CNTR3_SDS_CH1_TX_CRC_ERRORS_OFFSET) + +#define RTL8373_SDS_CH2_RX_MIB_CNTR0_ADDR (0x890) + #define RTL8373_SDS_CH2_RX_MIB_CNTR0_SDS_CH2_RX_TOTAL_PKTS_H_OFFSET (16) + #define RTL8373_SDS_CH2_RX_MIB_CNTR0_SDS_CH2_RX_TOTAL_PKTS_H_MASK (0xFFFF << RTL8373_SDS_CH2_RX_MIB_CNTR0_SDS_CH2_RX_TOTAL_PKTS_H_OFFSET) + #define RTL8373_SDS_CH2_RX_MIB_CNTR0_SDS_CH2_RX_TOTAL_PKTS_L_OFFSET (0) + #define RTL8373_SDS_CH2_RX_MIB_CNTR0_SDS_CH2_RX_TOTAL_PKTS_L_MASK (0xFFFF << RTL8373_SDS_CH2_RX_MIB_CNTR0_SDS_CH2_RX_TOTAL_PKTS_L_OFFSET) + +#define RTL8373_SDS_CH2_RX_MIB_CNTR1_ADDR (0x894) + #define RTL8373_SDS_CH2_RX_MIB_CNTR1_SDS_CH2_RX_GOOD_OCTETS_H_OFFSET (16) + #define RTL8373_SDS_CH2_RX_MIB_CNTR1_SDS_CH2_RX_GOOD_OCTETS_H_MASK (0xFFFF << RTL8373_SDS_CH2_RX_MIB_CNTR1_SDS_CH2_RX_GOOD_OCTETS_H_OFFSET) + #define RTL8373_SDS_CH2_RX_MIB_CNTR1_SDS_CH2_RX_GOOD_OCTETS_L_OFFSET (0) + #define RTL8373_SDS_CH2_RX_MIB_CNTR1_SDS_CH2_RX_GOOD_OCTETS_L_MASK (0xFFFF << RTL8373_SDS_CH2_RX_MIB_CNTR1_SDS_CH2_RX_GOOD_OCTETS_L_OFFSET) + +#define RTL8373_SDS_CH2_RX_MIB_CNTR2_ADDR (0x898) + #define RTL8373_SDS_CH2_RX_MIB_CNTR2_SDS_CH2_RX_GOOD_PKTS_H_OFFSET (16) + #define RTL8373_SDS_CH2_RX_MIB_CNTR2_SDS_CH2_RX_GOOD_PKTS_H_MASK (0xFFFF << RTL8373_SDS_CH2_RX_MIB_CNTR2_SDS_CH2_RX_GOOD_PKTS_H_OFFSET) + #define RTL8373_SDS_CH2_RX_MIB_CNTR2_SDS_CH2_RX_GOOD_PKTS_L_OFFSET (0) + #define RTL8373_SDS_CH2_RX_MIB_CNTR2_SDS_CH2_RX_GOOD_PKTS_L_MASK (0xFFFF << RTL8373_SDS_CH2_RX_MIB_CNTR2_SDS_CH2_RX_GOOD_PKTS_L_OFFSET) + +#define RTL8373_SDS_CH2_RX_MIB_CNTR3_ADDR (0x89C) + #define RTL8373_SDS_CH2_RX_MIB_CNTR3_SDS_CH2_RX_CRC_ERRORS_OFFSET (16) + #define RTL8373_SDS_CH2_RX_MIB_CNTR3_SDS_CH2_RX_CRC_ERRORS_MASK (0xFFFF << RTL8373_SDS_CH2_RX_MIB_CNTR3_SDS_CH2_RX_CRC_ERRORS_OFFSET) + #define RTL8373_SDS_CH2_RX_MIB_CNTR3_SDS_CH2_RX_SYMBOL_ERRORS_OFFSET (0) + #define RTL8373_SDS_CH2_RX_MIB_CNTR3_SDS_CH2_RX_SYMBOL_ERRORS_MASK (0xFFFF << RTL8373_SDS_CH2_RX_MIB_CNTR3_SDS_CH2_RX_SYMBOL_ERRORS_OFFSET) + +#define RTL8373_SDS_CH2_TX_MIB_CNTR0_ADDR (0x8B0) + #define RTL8373_SDS_CH2_TX_MIB_CNTR0_SDS_CH2_TX_TOTAL_PKTS_H_OFFSET (16) + #define RTL8373_SDS_CH2_TX_MIB_CNTR0_SDS_CH2_TX_TOTAL_PKTS_H_MASK (0xFFFF << RTL8373_SDS_CH2_TX_MIB_CNTR0_SDS_CH2_TX_TOTAL_PKTS_H_OFFSET) + #define RTL8373_SDS_CH2_TX_MIB_CNTR0_SDS_CH2_TX_TOTAL_PKTS_L_OFFSET (0) + #define RTL8373_SDS_CH2_TX_MIB_CNTR0_SDS_CH2_TX_TOTAL_PKTS_L_MASK (0xFFFF << RTL8373_SDS_CH2_TX_MIB_CNTR0_SDS_CH2_TX_TOTAL_PKTS_L_OFFSET) + +#define RTL8373_SDS_CH2_TX_MIB_CNTR1_ADDR (0x8B4) + #define RTL8373_SDS_CH2_TX_MIB_CNTR1_SDS_CH2_TX_GOOD_OCTETS_H_OFFSET (16) + #define RTL8373_SDS_CH2_TX_MIB_CNTR1_SDS_CH2_TX_GOOD_OCTETS_H_MASK (0xFFFF << RTL8373_SDS_CH2_TX_MIB_CNTR1_SDS_CH2_TX_GOOD_OCTETS_H_OFFSET) + #define RTL8373_SDS_CH2_TX_MIB_CNTR1_SDS_CH2_TX_GOOD_OCTETS_L_OFFSET (0) + #define RTL8373_SDS_CH2_TX_MIB_CNTR1_SDS_CH2_TX_GOOD_OCTETS_L_MASK (0xFFFF << RTL8373_SDS_CH2_TX_MIB_CNTR1_SDS_CH2_TX_GOOD_OCTETS_L_OFFSET) + +#define RTL8373_SDS_CH2_TX_MIB_CNTR2_ADDR (0x8B8) + #define RTL8373_SDS_CH2_TX_MIB_CNTR2_SDS_CH2_TX_GOOD_PKTS_H_OFFSET (16) + #define RTL8373_SDS_CH2_TX_MIB_CNTR2_SDS_CH2_TX_GOOD_PKTS_H_MASK (0xFFFF << RTL8373_SDS_CH2_TX_MIB_CNTR2_SDS_CH2_TX_GOOD_PKTS_H_OFFSET) + #define RTL8373_SDS_CH2_TX_MIB_CNTR2_SDS_CH2_TX_GOOD_PKTS_L_OFFSET (0) + #define RTL8373_SDS_CH2_TX_MIB_CNTR2_SDS_CH2_TX_GOOD_PKTS_L_MASK (0xFFFF << RTL8373_SDS_CH2_TX_MIB_CNTR2_SDS_CH2_TX_GOOD_PKTS_L_OFFSET) + +#define RTL8373_SDS_CH2_TX_MIB_CNTR3_ADDR (0x8BC) + #define RTL8373_SDS_CH2_TX_MIB_CNTR3_SDS_CH2_TX_CRC_ERRORS_OFFSET (0) + #define RTL8373_SDS_CH2_TX_MIB_CNTR3_SDS_CH2_TX_CRC_ERRORS_MASK (0xFFFF << RTL8373_SDS_CH2_TX_MIB_CNTR3_SDS_CH2_TX_CRC_ERRORS_OFFSET) + +#define RTL8373_SDS_CH3_RX_MIB_CNTR0_ADDR (0x8D0) + #define RTL8373_SDS_CH3_RX_MIB_CNTR0_SDS_CH3_RX_TOTAL_PKTS_H_OFFSET (16) + #define RTL8373_SDS_CH3_RX_MIB_CNTR0_SDS_CH3_RX_TOTAL_PKTS_H_MASK (0xFFFF << RTL8373_SDS_CH3_RX_MIB_CNTR0_SDS_CH3_RX_TOTAL_PKTS_H_OFFSET) + #define RTL8373_SDS_CH3_RX_MIB_CNTR0_SDS_CH3_RX_TOTAL_PKTS_L_OFFSET (0) + #define RTL8373_SDS_CH3_RX_MIB_CNTR0_SDS_CH3_RX_TOTAL_PKTS_L_MASK (0xFFFF << RTL8373_SDS_CH3_RX_MIB_CNTR0_SDS_CH3_RX_TOTAL_PKTS_L_OFFSET) + +#define RTL8373_SDS_CH3_RX_MIB_CNTR1_ADDR (0x8D4) + #define RTL8373_SDS_CH3_RX_MIB_CNTR1_SDS_CH3_RX_GOOD_OCTETS_H_OFFSET (16) + #define RTL8373_SDS_CH3_RX_MIB_CNTR1_SDS_CH3_RX_GOOD_OCTETS_H_MASK (0xFFFF << RTL8373_SDS_CH3_RX_MIB_CNTR1_SDS_CH3_RX_GOOD_OCTETS_H_OFFSET) + #define RTL8373_SDS_CH3_RX_MIB_CNTR1_SDS_CH3_RX_GOOD_OCTETS_L_OFFSET (0) + #define RTL8373_SDS_CH3_RX_MIB_CNTR1_SDS_CH3_RX_GOOD_OCTETS_L_MASK (0xFFFF << RTL8373_SDS_CH3_RX_MIB_CNTR1_SDS_CH3_RX_GOOD_OCTETS_L_OFFSET) + +#define RTL8373_SDS_CH3_RX_MIB_CNTR2_ADDR (0x8D8) + #define RTL8373_SDS_CH3_RX_MIB_CNTR2_SDS_CH3_RX_GOOD_PKTS_H_OFFSET (16) + #define RTL8373_SDS_CH3_RX_MIB_CNTR2_SDS_CH3_RX_GOOD_PKTS_H_MASK (0xFFFF << RTL8373_SDS_CH3_RX_MIB_CNTR2_SDS_CH3_RX_GOOD_PKTS_H_OFFSET) + #define RTL8373_SDS_CH3_RX_MIB_CNTR2_SDS_CH3_RX_GOOD_PKTS_L_OFFSET (0) + #define RTL8373_SDS_CH3_RX_MIB_CNTR2_SDS_CH3_RX_GOOD_PKTS_L_MASK (0xFFFF << RTL8373_SDS_CH3_RX_MIB_CNTR2_SDS_CH3_RX_GOOD_PKTS_L_OFFSET) + +#define RTL8373_SDS_CH3_RX_MIB_CNTR3_ADDR (0x8DC) + #define RTL8373_SDS_CH3_RX_MIB_CNTR3_SDS_CH3_RX_CRC_ERRORS_OFFSET (16) + #define RTL8373_SDS_CH3_RX_MIB_CNTR3_SDS_CH3_RX_CRC_ERRORS_MASK (0xFFFF << RTL8373_SDS_CH3_RX_MIB_CNTR3_SDS_CH3_RX_CRC_ERRORS_OFFSET) + #define RTL8373_SDS_CH3_RX_MIB_CNTR3_SDS_CH3_RX_SYMBOL_ERRORS_OFFSET (0) + #define RTL8373_SDS_CH3_RX_MIB_CNTR3_SDS_CH3_RX_SYMBOL_ERRORS_MASK (0xFFFF << RTL8373_SDS_CH3_RX_MIB_CNTR3_SDS_CH3_RX_SYMBOL_ERRORS_OFFSET) + +#define RTL8373_SDS_CH3_TX_MIB_CNTR0_ADDR (0x8F0) + #define RTL8373_SDS_CH3_TX_MIB_CNTR0_SDS_CH3_TX_TOTAL_PKTS_H_OFFSET (16) + #define RTL8373_SDS_CH3_TX_MIB_CNTR0_SDS_CH3_TX_TOTAL_PKTS_H_MASK (0xFFFF << RTL8373_SDS_CH3_TX_MIB_CNTR0_SDS_CH3_TX_TOTAL_PKTS_H_OFFSET) + #define RTL8373_SDS_CH3_TX_MIB_CNTR0_SDS_CH3_TX_TOTAL_PKTS_L_OFFSET (0) + #define RTL8373_SDS_CH3_TX_MIB_CNTR0_SDS_CH3_TX_TOTAL_PKTS_L_MASK (0xFFFF << RTL8373_SDS_CH3_TX_MIB_CNTR0_SDS_CH3_TX_TOTAL_PKTS_L_OFFSET) + +#define RTL8373_SDS_CH3_TX_MIB_CNTR1_ADDR (0x8F4) + #define RTL8373_SDS_CH3_TX_MIB_CNTR1_SDS_CH3_TX_GOOD_OCTETS_H_OFFSET (16) + #define RTL8373_SDS_CH3_TX_MIB_CNTR1_SDS_CH3_TX_GOOD_OCTETS_H_MASK (0xFFFF << RTL8373_SDS_CH3_TX_MIB_CNTR1_SDS_CH3_TX_GOOD_OCTETS_H_OFFSET) + #define RTL8373_SDS_CH3_TX_MIB_CNTR1_SDS_CH3_TX_GOOD_OCTETS_L_OFFSET (0) + #define RTL8373_SDS_CH3_TX_MIB_CNTR1_SDS_CH3_TX_GOOD_OCTETS_L_MASK (0xFFFF << RTL8373_SDS_CH3_TX_MIB_CNTR1_SDS_CH3_TX_GOOD_OCTETS_L_OFFSET) + +#define RTL8373_SDS_CH3_TX_MIB_CNTR2_ADDR (0x8F8) + #define RTL8373_SDS_CH3_TX_MIB_CNTR2_SDS_CH3_TX_GOOD_PKTS_H_OFFSET (16) + #define RTL8373_SDS_CH3_TX_MIB_CNTR2_SDS_CH3_TX_GOOD_PKTS_H_MASK (0xFFFF << RTL8373_SDS_CH3_TX_MIB_CNTR2_SDS_CH3_TX_GOOD_PKTS_H_OFFSET) + #define RTL8373_SDS_CH3_TX_MIB_CNTR2_SDS_CH3_TX_GOOD_PKTS_L_OFFSET (0) + #define RTL8373_SDS_CH3_TX_MIB_CNTR2_SDS_CH3_TX_GOOD_PKTS_L_MASK (0xFFFF << RTL8373_SDS_CH3_TX_MIB_CNTR2_SDS_CH3_TX_GOOD_PKTS_L_OFFSET) + +#define RTL8373_SDS_CH3_TX_MIB_CNTR3_ADDR (0x8FC) + #define RTL8373_SDS_CH3_TX_MIB_CNTR3_SDS_CH3_TX_CRC_ERRORS_OFFSET (0) + #define RTL8373_SDS_CH3_TX_MIB_CNTR3_SDS_CH3_TX_CRC_ERRORS_MASK (0xFFFF << RTL8373_SDS_CH3_TX_MIB_CNTR3_SDS_CH3_TX_CRC_ERRORS_OFFSET) + +#define RTL8373_DMY_REG0_MIB_DATA_ADDR (0xF30) + #define RTL8373_DMY_REG0_MIB_DATA_DUMMY_OFFSET (0) + #define RTL8373_DMY_REG0_MIB_DATA_DUMMY_MASK (0xFFFFFFFF << RTL8373_DMY_REG0_MIB_DATA_DUMMY_OFFSET) + +#define RTL8373_DMY_REG1_MIB_DATA_ADDR (0xF34) + #define RTL8373_DMY_REG1_MIB_DATA_DUMMY_OFFSET (0) + #define RTL8373_DMY_REG1_MIB_DATA_DUMMY_MASK (0xFFFFFFFF << RTL8373_DMY_REG1_MIB_DATA_DUMMY_OFFSET) + +#define RTL8373_DMY_REG2_MIB_DATA_ADDR (0xF38) + #define RTL8373_DMY_REG2_MIB_DATA_DUMMY_OFFSET (0) + #define RTL8373_DMY_REG2_MIB_DATA_DUMMY_MASK (0xFFFFFFFF << RTL8373_DMY_REG2_MIB_DATA_DUMMY_OFFSET) + +#define RTL8373_DMY_REG3_MIB_DATA_ADDR (0xF3C) + #define RTL8373_DMY_REG3_MIB_DATA_DUMMY_OFFSET (0) + #define RTL8373_DMY_REG3_MIB_DATA_DUMMY_MASK (0xFFFFFFFF << RTL8373_DMY_REG3_MIB_DATA_DUMMY_OFFSET) + +/* + * Feature: MAC Control + */ +#define RTL8373_MAC_L2_PORT_TX_MAX_LEN_CTRL_ADDR(port) (0x4E90 + (((port) << 2))) /* port: 0-9 */ + #define RTL8373_MAC_L2_PORT_TX_MAX_LEN_CTRL_MAX_LEN_TX_1G_2P5G_5G_10G_SEL_OFFSET (14) + #define RTL8373_MAC_L2_PORT_TX_MAX_LEN_CTRL_MAX_LEN_TX_1G_2P5G_5G_10G_SEL_MASK (0x3FFF << RTL8373_MAC_L2_PORT_TX_MAX_LEN_CTRL_MAX_LEN_TX_1G_2P5G_5G_10G_SEL_OFFSET) + #define RTL8373_MAC_L2_PORT_TX_MAX_LEN_CTRL_MAX_LEN_TX_100M_10M_SEL_OFFSET (0) + #define RTL8373_MAC_L2_PORT_TX_MAX_LEN_CTRL_MAX_LEN_TX_100M_10M_SEL_MASK (0x3FFF << RTL8373_MAC_L2_PORT_TX_MAX_LEN_CTRL_MAX_LEN_TX_100M_10M_SEL_OFFSET) + +#define RTL8373_SMI_BYPASS_ABLTY_LOCK_CTRL_ADDR(port) (0x6320 + (((port / 9) << 2))) /* port: 0-8 */ + #define RTL8373_SMI_BYPASS_ABLTY_LOCK_CTRL_BYPASS_ABLTY_LOCK_OFFSET(port) (port % 0x9) + #define RTL8373_SMI_BYPASS_ABLTY_LOCK_CTRL_BYPASS_ABLTY_LOCK_MASK(port) (0x1 << RTL8373_SMI_BYPASS_ABLTY_LOCK_CTRL_BYPASS_ABLTY_LOCK_OFFSET(port)) + +#define RTL8373_LINK_DOWN_CTRL_ADDR (0x6324) + #define RTL8373_LINK_DOWN_CTRL_LINK_DOWN_TIME_EN2_OFFSET (26) + #define RTL8373_LINK_DOWN_CTRL_LINK_DOWN_TIME_EN2_MASK (0x1 << RTL8373_LINK_DOWN_CTRL_LINK_DOWN_TIME_EN2_OFFSET) + #define RTL8373_LINK_DOWN_CTRL_LINK_DOWN_TIME2_OFFSET (18) + #define RTL8373_LINK_DOWN_CTRL_LINK_DOWN_TIME2_MASK (0xFF << RTL8373_LINK_DOWN_CTRL_LINK_DOWN_TIME2_OFFSET) + #define RTL8373_LINK_DOWN_CTRL_LINK_DOWN_TIME_EN1_OFFSET (17) + #define RTL8373_LINK_DOWN_CTRL_LINK_DOWN_TIME_EN1_MASK (0x1 << RTL8373_LINK_DOWN_CTRL_LINK_DOWN_TIME_EN1_OFFSET) + #define RTL8373_LINK_DOWN_CTRL_LINK_DOWN_TIME1_OFFSET (9) + #define RTL8373_LINK_DOWN_CTRL_LINK_DOWN_TIME1_MASK (0xFF << RTL8373_LINK_DOWN_CTRL_LINK_DOWN_TIME1_OFFSET) + #define RTL8373_LINK_DOWN_CTRL_LINK_DOWN_TIME_EN0_OFFSET (8) + #define RTL8373_LINK_DOWN_CTRL_LINK_DOWN_TIME_EN0_MASK (0x1 << RTL8373_LINK_DOWN_CTRL_LINK_DOWN_TIME_EN0_OFFSET) + #define RTL8373_LINK_DOWN_CTRL_LINK_DOWN_TIME0_OFFSET (0) + #define RTL8373_LINK_DOWN_CTRL_LINK_DOWN_TIME0_MASK (0xFF << RTL8373_LINK_DOWN_CTRL_LINK_DOWN_TIME0_OFFSET) + +#define RTL8373_MAC_GLB_CTRL_ADDR (0x5FD0) + #define RTL8373_MAC_GLB_CTRL_MAC_48PASS1_DROP_EN_OFFSET (13) + #define RTL8373_MAC_GLB_CTRL_MAC_48PASS1_DROP_EN_MASK (0x1 << RTL8373_MAC_GLB_CTRL_MAC_48PASS1_DROP_EN_OFFSET) + #define RTL8373_MAC_GLB_CTRL_DEFER_PKT_CONT_SEL_OFFSET (10) + #define RTL8373_MAC_GLB_CTRL_DEFER_PKT_CONT_SEL_MASK (0x1 << RTL8373_MAC_GLB_CTRL_DEFER_PKT_CONT_SEL_OFFSET) + #define RTL8373_MAC_GLB_CTRL_MAX_RETX_SEL_OFFSET (9) + #define RTL8373_MAC_GLB_CTRL_MAX_RETX_SEL_MASK (0x1 << RTL8373_MAC_GLB_CTRL_MAX_RETX_SEL_OFFSET) + #define RTL8373_MAC_GLB_CTRL_LATE_COLI_DROP_EN_OFFSET (8) + #define RTL8373_MAC_GLB_CTRL_LATE_COLI_DROP_EN_MASK (0x1 << RTL8373_MAC_GLB_CTRL_LATE_COLI_DROP_EN_OFFSET) + #define RTL8373_MAC_GLB_CTRL_IOL_MAX_RETRY_EN_OFFSET (7) + #define RTL8373_MAC_GLB_CTRL_IOL_MAX_RETRY_EN_MASK (0x1 << RTL8373_MAC_GLB_CTRL_IOL_MAX_RETRY_EN_OFFSET) + #define RTL8373_MAC_GLB_CTRL_BKOFF_SPDUP_OFFSET (6) + #define RTL8373_MAC_GLB_CTRL_BKOFF_SPDUP_MASK (0x1 << RTL8373_MAC_GLB_CTRL_BKOFF_SPDUP_OFFSET) + #define RTL8373_MAC_GLB_CTRL_BKOFF_SEL_OFFSET (4) + #define RTL8373_MAC_GLB_CTRL_BKOFF_SEL_MASK (0x3 << RTL8373_MAC_GLB_CTRL_BKOFF_SEL_OFFSET) + #define RTL8373_MAC_GLB_CTRL_HALF_48PASS1_EN_OFFSET (3) + #define RTL8373_MAC_GLB_CTRL_HALF_48PASS1_EN_MASK (0x1 << RTL8373_MAC_GLB_CTRL_HALF_48PASS1_EN_OFFSET) + #define RTL8373_MAC_GLB_CTRL_BKPRES_MTHD_SEL_OFFSET (2) + #define RTL8373_MAC_GLB_CTRL_BKPRES_MTHD_SEL_MASK (0x1 << RTL8373_MAC_GLB_CTRL_BKPRES_MTHD_SEL_OFFSET) + #define RTL8373_MAC_GLB_CTRL_DEFER_IPG_SEL_OFFSET (0) + #define RTL8373_MAC_GLB_CTRL_DEFER_IPG_SEL_MASK (0x3 << RTL8373_MAC_GLB_CTRL_DEFER_IPG_SEL_OFFSET) + +#define RTL8373_MAC_PORT_CTRL_ADDR(port) (0x122C + (((port) << 8))) /* port: 0-9 */ + #define RTL8373_MAC_PORT_CTRL_ORIGINAL_CRS_OFFSET (6) + #define RTL8373_MAC_PORT_CTRL_ORIGINAL_CRS_MASK (0x1 << RTL8373_MAC_PORT_CTRL_ORIGINAL_CRS_OFFSET) + #define RTL8373_MAC_PORT_CTRL_ORIGINAL_COL_OFFSET (5) + #define RTL8373_MAC_PORT_CTRL_ORIGINAL_COL_MASK (0x1 << RTL8373_MAC_PORT_CTRL_ORIGINAL_COL_OFFSET) + #define RTL8373_MAC_PORT_CTRL_PRECOLLAT_SEL_OFFSET (3) + #define RTL8373_MAC_PORT_CTRL_PRECOLLAT_SEL_MASK (0x3 << RTL8373_MAC_PORT_CTRL_PRECOLLAT_SEL_OFFSET) + #define RTL8373_MAC_PORT_CTRL_LATE_COLI_THR_OFFSET (1) + #define RTL8373_MAC_PORT_CTRL_LATE_COLI_THR_MASK (0x3 << RTL8373_MAC_PORT_CTRL_LATE_COLI_THR_OFFSET) + #define RTL8373_MAC_PORT_CTRL_BKPRES_EN_OFFSET (0) + #define RTL8373_MAC_PORT_CTRL_BKPRES_EN_MASK (0x1 << RTL8373_MAC_PORT_CTRL_BKPRES_EN_OFFSET) + +#define RTL8373_HALF_CHG_CTRL_ADDR(port) (0x1230 + (((port) << 8))) /* port: 0-9 */ + #define RTL8373_HALF_CHG_CTRL_HALF_TO_FULL_PAUSE_OFFSET (13) + #define RTL8373_HALF_CHG_CTRL_HALF_TO_FULL_PAUSE_MASK (0x1 << RTL8373_HALF_CHG_CTRL_HALF_TO_FULL_PAUSE_OFFSET) + #define RTL8373_HALF_CHG_CTRL_REF_RX_CONGEST_OFFSET (12) + #define RTL8373_HALF_CHG_CTRL_REF_RX_CONGEST_MASK (0x1 << RTL8373_HALF_CHG_CTRL_REF_RX_CONGEST_OFFSET) + #define RTL8373_HALF_CHG_CTRL_CHG_DUP_THR_OFFSET (7) + #define RTL8373_HALF_CHG_CTRL_CHG_DUP_THR_MASK (0x1F << RTL8373_HALF_CHG_CTRL_CHG_DUP_THR_OFFSET) + #define RTL8373_HALF_CHG_CTRL_FULL_DET_EN_OFFSET (6) + #define RTL8373_HALF_CHG_CTRL_FULL_DET_EN_MASK (0x1 << RTL8373_HALF_CHG_CTRL_FULL_DET_EN_OFFSET) + #define RTL8373_HALF_CHG_CTRL_MAC_CHG_DUP_OFFSET (5) + #define RTL8373_HALF_CHG_CTRL_MAC_CHG_DUP_MASK (0x1 << RTL8373_HALF_CHG_CTRL_MAC_CHG_DUP_OFFSET) + #define RTL8373_HALF_CHG_CTRL_COL_CUR_CNT_OFFSET (0) + #define RTL8373_HALF_CHG_CTRL_COL_CUR_CNT_MASK (0x1F << RTL8373_HALF_CHG_CTRL_COL_CUR_CNT_OFFSET) + +#define RTL8373_SMI_GLB_CTRL2_ADDR (0x6328) + #define RTL8373_SMI_GLB_CTRL2_PHY_FORCE_PAUSE_ABLTY_SEL_OFFSET (2) + #define RTL8373_SMI_GLB_CTRL2_PHY_FORCE_PAUSE_ABLTY_SEL_MASK (0x1 << RTL8373_SMI_GLB_CTRL2_PHY_FORCE_PAUSE_ABLTY_SEL_OFFSET) + #define RTL8373_SMI_GLB_CTRL2_PHY_FORCE_TX_PAUSE_ABLTY_OFFSET (1) + #define RTL8373_SMI_GLB_CTRL2_PHY_FORCE_TX_PAUSE_ABLTY_MASK (0x1 << RTL8373_SMI_GLB_CTRL2_PHY_FORCE_TX_PAUSE_ABLTY_OFFSET) + #define RTL8373_SMI_GLB_CTRL2_PHY_FORCE_RX_PAUSE_ABLTY_OFFSET (0) + #define RTL8373_SMI_GLB_CTRL2_PHY_FORCE_RX_PAUSE_ABLTY_MASK (0x1 << RTL8373_SMI_GLB_CTRL2_PHY_FORCE_RX_PAUSE_ABLTY_OFFSET) + +#define RTL8373_SMI_GLB_CTRL_ADDR (0x632C) + #define RTL8373_SMI_GLB_CTRL_SMI_GLB_RST_OFFSET (21) + #define RTL8373_SMI_GLB_CTRL_SMI_GLB_RST_MASK (0x1 << RTL8373_SMI_GLB_CTRL_SMI_GLB_RST_OFFSET) + #define RTL8373_SMI_GLB_CTRL_SMI_POLLING_MASK_OFFSET (12) + #define RTL8373_SMI_GLB_CTRL_SMI_POLLING_MASK_MASK (0x1FF << RTL8373_SMI_GLB_CTRL_SMI_POLLING_MASK_OFFSET) + #define RTL8373_SMI_GLB_CTRL_SMI2_FREQ_SEL_OFFSET (10) + #define RTL8373_SMI_GLB_CTRL_SMI2_FREQ_SEL_MASK (0x3 << RTL8373_SMI_GLB_CTRL_SMI2_FREQ_SEL_OFFSET) + #define RTL8373_SMI_GLB_CTRL_SMI1_FREQ_SEL_OFFSET (8) + #define RTL8373_SMI_GLB_CTRL_SMI1_FREQ_SEL_MASK (0x3 << RTL8373_SMI_GLB_CTRL_SMI1_FREQ_SEL_OFFSET) + #define RTL8373_SMI_GLB_CTRL_SMI0_FREQ_SEL_OFFSET (6) + #define RTL8373_SMI_GLB_CTRL_SMI0_FREQ_SEL_MASK (0x3 << RTL8373_SMI_GLB_CTRL_SMI0_FREQ_SEL_OFFSET) + #define RTL8373_SMI_GLB_CTRL_SMI2_PREAMBLE_SEL_OFFSET (5) + #define RTL8373_SMI_GLB_CTRL_SMI2_PREAMBLE_SEL_MASK (0x1 << RTL8373_SMI_GLB_CTRL_SMI2_PREAMBLE_SEL_OFFSET) + #define RTL8373_SMI_GLB_CTRL_SMI1_PREAMBLE_SEL_OFFSET (4) + #define RTL8373_SMI_GLB_CTRL_SMI1_PREAMBLE_SEL_MASK (0x1 << RTL8373_SMI_GLB_CTRL_SMI1_PREAMBLE_SEL_OFFSET) + #define RTL8373_SMI_GLB_CTRL_SMI0_PREAMBLE_SEL_OFFSET (3) + #define RTL8373_SMI_GLB_CTRL_SMI0_PREAMBLE_SEL_MASK (0x1 << RTL8373_SMI_GLB_CTRL_SMI0_PREAMBLE_SEL_OFFSET) + #define RTL8373_SMI_GLB_CTRL_SMI2_BROADCAST_SET_EN_OFFSET (2) + #define RTL8373_SMI_GLB_CTRL_SMI2_BROADCAST_SET_EN_MASK (0x1 << RTL8373_SMI_GLB_CTRL_SMI2_BROADCAST_SET_EN_OFFSET) + #define RTL8373_SMI_GLB_CTRL_SMI1_BROADCAST_SET_EN_OFFSET (1) + #define RTL8373_SMI_GLB_CTRL_SMI1_BROADCAST_SET_EN_MASK (0x1 << RTL8373_SMI_GLB_CTRL_SMI1_BROADCAST_SET_EN_OFFSET) + #define RTL8373_SMI_GLB_CTRL_SMI0_BROADCAST_SET_EN_OFFSET (0) + #define RTL8373_SMI_GLB_CTRL_SMI0_BROADCAST_SET_EN_MASK (0x1 << RTL8373_SMI_GLB_CTRL_SMI0_BROADCAST_SET_EN_OFFSET) + +#define RTL8373_SMI_MAC_TYPE_CTRL_ADDR (0x6330) + #define RTL8373_SMI_MAC_TYPE_CTRL_MAC_PORT8_TYPE_OFFSET (16) + #define RTL8373_SMI_MAC_TYPE_CTRL_MAC_PORT8_TYPE_MASK (0x3 << RTL8373_SMI_MAC_TYPE_CTRL_MAC_PORT8_TYPE_OFFSET) + #define RTL8373_SMI_MAC_TYPE_CTRL_MAC_PORT7_TYPE_OFFSET (14) + #define RTL8373_SMI_MAC_TYPE_CTRL_MAC_PORT7_TYPE_MASK (0x3 << RTL8373_SMI_MAC_TYPE_CTRL_MAC_PORT7_TYPE_OFFSET) + #define RTL8373_SMI_MAC_TYPE_CTRL_MAC_PORT6_TYPE_OFFSET (12) + #define RTL8373_SMI_MAC_TYPE_CTRL_MAC_PORT6_TYPE_MASK (0x3 << RTL8373_SMI_MAC_TYPE_CTRL_MAC_PORT6_TYPE_OFFSET) + #define RTL8373_SMI_MAC_TYPE_CTRL_MAC_PORT5_TYPE_OFFSET (10) + #define RTL8373_SMI_MAC_TYPE_CTRL_MAC_PORT5_TYPE_MASK (0x3 << RTL8373_SMI_MAC_TYPE_CTRL_MAC_PORT5_TYPE_OFFSET) + #define RTL8373_SMI_MAC_TYPE_CTRL_MAC_PORT4_TYPE_OFFSET (8) + #define RTL8373_SMI_MAC_TYPE_CTRL_MAC_PORT4_TYPE_MASK (0x3 << RTL8373_SMI_MAC_TYPE_CTRL_MAC_PORT4_TYPE_OFFSET) + #define RTL8373_SMI_MAC_TYPE_CTRL_MAC_PORT3_TYPE_OFFSET (6) + #define RTL8373_SMI_MAC_TYPE_CTRL_MAC_PORT3_TYPE_MASK (0x3 << RTL8373_SMI_MAC_TYPE_CTRL_MAC_PORT3_TYPE_OFFSET) + #define RTL8373_SMI_MAC_TYPE_CTRL_MAC_PORT2_TYPE_OFFSET (4) + #define RTL8373_SMI_MAC_TYPE_CTRL_MAC_PORT2_TYPE_MASK (0x3 << RTL8373_SMI_MAC_TYPE_CTRL_MAC_PORT2_TYPE_OFFSET) + #define RTL8373_SMI_MAC_TYPE_CTRL_MAC_PORT1_TYPE_OFFSET (2) + #define RTL8373_SMI_MAC_TYPE_CTRL_MAC_PORT1_TYPE_MASK (0x3 << RTL8373_SMI_MAC_TYPE_CTRL_MAC_PORT1_TYPE_OFFSET) + #define RTL8373_SMI_MAC_TYPE_CTRL_MAC_PORT0_TYPE_OFFSET (0) + #define RTL8373_SMI_MAC_TYPE_CTRL_MAC_PORT0_TYPE_MASK (0x3 << RTL8373_SMI_MAC_TYPE_CTRL_MAC_PORT0_TYPE_OFFSET) + +#define RTL8373_SMI_PORT_POLLING_SEL_ADDR (0x6334) + #define RTL8373_SMI_PORT_POLLING_SEL_SMI_POLLING_SEL8_OFFSET (8) + #define RTL8373_SMI_PORT_POLLING_SEL_SMI_POLLING_SEL8_MASK (0x1 << RTL8373_SMI_PORT_POLLING_SEL_SMI_POLLING_SEL8_OFFSET) + #define RTL8373_SMI_PORT_POLLING_SEL_SMI_POLLING_SEL7_OFFSET (7) + #define RTL8373_SMI_PORT_POLLING_SEL_SMI_POLLING_SEL7_MASK (0x1 << RTL8373_SMI_PORT_POLLING_SEL_SMI_POLLING_SEL7_OFFSET) + #define RTL8373_SMI_PORT_POLLING_SEL_SMI_POLLING_SEL6_OFFSET (6) + #define RTL8373_SMI_PORT_POLLING_SEL_SMI_POLLING_SEL6_MASK (0x1 << RTL8373_SMI_PORT_POLLING_SEL_SMI_POLLING_SEL6_OFFSET) + #define RTL8373_SMI_PORT_POLLING_SEL_SMI_POLLING_SEL5_OFFSET (5) + #define RTL8373_SMI_PORT_POLLING_SEL_SMI_POLLING_SEL5_MASK (0x1 << RTL8373_SMI_PORT_POLLING_SEL_SMI_POLLING_SEL5_OFFSET) + #define RTL8373_SMI_PORT_POLLING_SEL_SMI_POLLING_SEL4_OFFSET (4) + #define RTL8373_SMI_PORT_POLLING_SEL_SMI_POLLING_SEL4_MASK (0x1 << RTL8373_SMI_PORT_POLLING_SEL_SMI_POLLING_SEL4_OFFSET) + #define RTL8373_SMI_PORT_POLLING_SEL_SMI_POLLING_SEL3_OFFSET (3) + #define RTL8373_SMI_PORT_POLLING_SEL_SMI_POLLING_SEL3_MASK (0x1 << RTL8373_SMI_PORT_POLLING_SEL_SMI_POLLING_SEL3_OFFSET) + #define RTL8373_SMI_PORT_POLLING_SEL_SMI_POLLING_SEL2_OFFSET (2) + #define RTL8373_SMI_PORT_POLLING_SEL_SMI_POLLING_SEL2_MASK (0x1 << RTL8373_SMI_PORT_POLLING_SEL_SMI_POLLING_SEL2_OFFSET) + #define RTL8373_SMI_PORT_POLLING_SEL_SMI_POLLING_SEL1_OFFSET (1) + #define RTL8373_SMI_PORT_POLLING_SEL_SMI_POLLING_SEL1_MASK (0x1 << RTL8373_SMI_PORT_POLLING_SEL_SMI_POLLING_SEL1_OFFSET) + #define RTL8373_SMI_PORT_POLLING_SEL_SMI_POLLING_SEL0_OFFSET (0) + #define RTL8373_SMI_PORT_POLLING_SEL_SMI_POLLING_SEL0_MASK (0x1 << RTL8373_SMI_PORT_POLLING_SEL_SMI_POLLING_SEL0_OFFSET) + +#define RTL8373_SMI_MDIO_FREE_CNT_CTRL_ADDR (0x6338) + #define RTL8373_SMI_MDIO_FREE_CNT_CTRL_MDIO_FREE_CNT_SEL_OFFSET (1) + #define RTL8373_SMI_MDIO_FREE_CNT_CTRL_MDIO_FREE_CNT_SEL_MASK (0xFFF << RTL8373_SMI_MDIO_FREE_CNT_CTRL_MDIO_FREE_CNT_SEL_OFFSET) + #define RTL8373_SMI_MDIO_FREE_CNT_CTRL_MDIO_FREE_CNT_EN_OFFSET (0) + #define RTL8373_SMI_MDIO_FREE_CNT_CTRL_MDIO_FREE_CNT_EN_MASK (0x1 << RTL8373_SMI_MDIO_FREE_CNT_CTRL_MDIO_FREE_CNT_EN_OFFSET) + +#define RTL8373_SMI_PRVTE_POLLING_CTRL_ADDR (0x633C) + #define RTL8373_SMI_PRVTE_POLLING_CTRL_SMI_PRVTE1_POLLING8_0_OFFSET (9) + #define RTL8373_SMI_PRVTE_POLLING_CTRL_SMI_PRVTE1_POLLING8_0_MASK (0x1FF << RTL8373_SMI_PRVTE_POLLING_CTRL_SMI_PRVTE1_POLLING8_0_OFFSET) + #define RTL8373_SMI_PRVTE_POLLING_CTRL_SMI_PRVTE_POLLING8_0_OFFSET (0) + #define RTL8373_SMI_PRVTE_POLLING_CTRL_SMI_PRVTE_POLLING8_0_MASK (0x1FF << RTL8373_SMI_PRVTE_POLLING_CTRL_SMI_PRVTE_POLLING8_0_OFFSET) + +#define RTL8373_SMI_10GPHY_POLLING_SEL_0_ADDR (0x6340) + #define RTL8373_SMI_10GPHY_POLLING_SEL_0_INTDEV0_POLLING_10GPHY_OFFSET (16) + #define RTL8373_SMI_10GPHY_POLLING_SEL_0_INTDEV0_POLLING_10GPHY_MASK (0x1F << RTL8373_SMI_10GPHY_POLLING_SEL_0_INTDEV0_POLLING_10GPHY_OFFSET) + #define RTL8373_SMI_10GPHY_POLLING_SEL_0_INTREG0_POLLING_10GPHY_OFFSET (0) + #define RTL8373_SMI_10GPHY_POLLING_SEL_0_INTREG0_POLLING_10GPHY_MASK (0xFFFF << RTL8373_SMI_10GPHY_POLLING_SEL_0_INTREG0_POLLING_10GPHY_OFFSET) + +#define RTL8373_MAC_FORCE_MODE_CTRL0_ADDR(port) (0x6344 + (((port) << 2))) /* port: 0-9 */ + #define RTL8373_MAC_FORCE_MODE_CTRL0_FORCE_BYP_LINK_OFFSET (11) + #define RTL8373_MAC_FORCE_MODE_CTRL0_FORCE_BYP_LINK_MASK (0x1 << RTL8373_MAC_FORCE_MODE_CTRL0_FORCE_BYP_LINK_OFFSET) + #define RTL8373_MAC_FORCE_MODE_CTRL0_MEDIA_SEL_OFFSET (10) + #define RTL8373_MAC_FORCE_MODE_CTRL0_MEDIA_SEL_MASK (0x1 << RTL8373_MAC_FORCE_MODE_CTRL0_MEDIA_SEL_OFFSET) + #define RTL8373_MAC_FORCE_MODE_CTRL0_SMI_FORCE_FC_EN_OFFSET (9) + #define RTL8373_MAC_FORCE_MODE_CTRL0_SMI_FORCE_FC_EN_MASK (0x1 << RTL8373_MAC_FORCE_MODE_CTRL0_SMI_FORCE_FC_EN_OFFSET) + #define RTL8373_MAC_FORCE_MODE_CTRL0_RX_PAUSE_EN_OFFSET (8) + #define RTL8373_MAC_FORCE_MODE_CTRL0_RX_PAUSE_EN_MASK (0x1 << RTL8373_MAC_FORCE_MODE_CTRL0_RX_PAUSE_EN_OFFSET) + #define RTL8373_MAC_FORCE_MODE_CTRL0_TX_PAUSE_EN_OFFSET (7) + #define RTL8373_MAC_FORCE_MODE_CTRL0_TX_PAUSE_EN_MASK (0x1 << RTL8373_MAC_FORCE_MODE_CTRL0_TX_PAUSE_EN_OFFSET) + #define RTL8373_MAC_FORCE_MODE_CTRL0_SPD_SEL_OFFSET (3) + #define RTL8373_MAC_FORCE_MODE_CTRL0_SPD_SEL_MASK (0xF << RTL8373_MAC_FORCE_MODE_CTRL0_SPD_SEL_OFFSET) + #define RTL8373_MAC_FORCE_MODE_CTRL0_DUP_SEL_OFFSET (2) + #define RTL8373_MAC_FORCE_MODE_CTRL0_DUP_SEL_MASK (0x1 << RTL8373_MAC_FORCE_MODE_CTRL0_DUP_SEL_OFFSET) + #define RTL8373_MAC_FORCE_MODE_CTRL0_FORCE_LINK_EN_OFFSET (1) + #define RTL8373_MAC_FORCE_MODE_CTRL0_FORCE_LINK_EN_MASK (0x1 << RTL8373_MAC_FORCE_MODE_CTRL0_FORCE_LINK_EN_OFFSET) + #define RTL8373_MAC_FORCE_MODE_CTRL0_MAC_FORCE_EN_OFFSET (0) + #define RTL8373_MAC_FORCE_MODE_CTRL0_MAC_FORCE_EN_MASK (0x1 << RTL8373_MAC_FORCE_MODE_CTRL0_MAC_FORCE_EN_OFFSET) + +#define RTL8373_MAC_FORCE_MODE_CTRL1_ADDR(port) (0x636C + (((port) << 2))) /* port: 0-9 */ + #define RTL8373_MAC_FORCE_MODE_CTRL1_EEE_10G_EN_OFFSET (8) + #define RTL8373_MAC_FORCE_MODE_CTRL1_EEE_10G_EN_MASK (0x1 << RTL8373_MAC_FORCE_MODE_CTRL1_EEE_10G_EN_OFFSET) + #define RTL8373_MAC_FORCE_MODE_CTRL1_EEE_10GLITE_EN_OFFSET (7) + #define RTL8373_MAC_FORCE_MODE_CTRL1_EEE_10GLITE_EN_MASK (0x1 << RTL8373_MAC_FORCE_MODE_CTRL1_EEE_10GLITE_EN_OFFSET) + #define RTL8373_MAC_FORCE_MODE_CTRL1_EEE_5G_EN_OFFSET (6) + #define RTL8373_MAC_FORCE_MODE_CTRL1_EEE_5G_EN_MASK (0x1 << RTL8373_MAC_FORCE_MODE_CTRL1_EEE_5G_EN_OFFSET) + #define RTL8373_MAC_FORCE_MODE_CTRL1_EEE_5GLITE_EN_OFFSET (5) + #define RTL8373_MAC_FORCE_MODE_CTRL1_EEE_5GLITE_EN_MASK (0x1 << RTL8373_MAC_FORCE_MODE_CTRL1_EEE_5GLITE_EN_OFFSET) + #define RTL8373_MAC_FORCE_MODE_CTRL1_EEE_2P5G_EN_OFFSET (4) + #define RTL8373_MAC_FORCE_MODE_CTRL1_EEE_2P5G_EN_MASK (0x1 << RTL8373_MAC_FORCE_MODE_CTRL1_EEE_2P5G_EN_OFFSET) + #define RTL8373_MAC_FORCE_MODE_CTRL1_EEE_2P5GLITE_EN_OFFSET (3) + #define RTL8373_MAC_FORCE_MODE_CTRL1_EEE_2P5GLITE_EN_MASK (0x1 << RTL8373_MAC_FORCE_MODE_CTRL1_EEE_2P5GLITE_EN_OFFSET) + #define RTL8373_MAC_FORCE_MODE_CTRL1_EEE_GIGA_EN_OFFSET (2) + #define RTL8373_MAC_FORCE_MODE_CTRL1_EEE_GIGA_EN_MASK (0x1 << RTL8373_MAC_FORCE_MODE_CTRL1_EEE_GIGA_EN_OFFSET) + #define RTL8373_MAC_FORCE_MODE_CTRL1_EEE_500M_EN_OFFSET (1) + #define RTL8373_MAC_FORCE_MODE_CTRL1_EEE_500M_EN_MASK (0x1 << RTL8373_MAC_FORCE_MODE_CTRL1_EEE_500M_EN_OFFSET) + #define RTL8373_MAC_FORCE_MODE_CTRL1_EEE_100M_EN_OFFSET (0) + #define RTL8373_MAC_FORCE_MODE_CTRL1_EEE_100M_EN_MASK (0x1 << RTL8373_MAC_FORCE_MODE_CTRL1_EEE_100M_EN_OFFSET) + +#define RTL8373_SMI_REG_CHK1_CTRL1_ADDR (0x6394) + #define RTL8373_SMI_REG_CHK1_CTRL1_CHK1_MODE_10G_OFFSET (21) + #define RTL8373_SMI_REG_CHK1_CTRL1_CHK1_MODE_10G_MASK (0x3 << RTL8373_SMI_REG_CHK1_CTRL1_CHK1_MODE_10G_OFFSET) + #define RTL8373_SMI_REG_CHK1_CTRL1_CHECK1_MMD_REG_OFFSET (5) + #define RTL8373_SMI_REG_CHK1_CTRL1_CHECK1_MMD_REG_MASK (0xFFFF << RTL8373_SMI_REG_CHK1_CTRL1_CHECK1_MMD_REG_OFFSET) + #define RTL8373_SMI_REG_CHK1_CTRL1_CHECK1_MMD_DEVAD_OFFSET (0) + #define RTL8373_SMI_REG_CHK1_CTRL1_CHECK1_MMD_DEVAD_MASK (0x1F << RTL8373_SMI_REG_CHK1_CTRL1_CHECK1_MMD_DEVAD_OFFSET) + +#define RTL8373_SMI_REG_CHK1_PMSK_ADDR (0x6398) + #define RTL8373_SMI_REG_CHK1_PMSK_CHK1_PMSK_OFFSET (0) + #define RTL8373_SMI_REG_CHK1_PMSK_CHK1_PMSK_MASK (0x1FF << RTL8373_SMI_REG_CHK1_PMSK_CHK1_PMSK_OFFSET) + +#define RTL8373_SMI_REG_CHK1_DATA_10G_ADDR (0x639C) + #define RTL8373_SMI_REG_CHK1_DATA_10G_CHK1_DMSK_10G_OFFSET (16) + #define RTL8373_SMI_REG_CHK1_DATA_10G_CHK1_DMSK_10G_MASK (0xFFFF << RTL8373_SMI_REG_CHK1_DATA_10G_CHK1_DMSK_10G_OFFSET) + #define RTL8373_SMI_REG_CHK1_DATA_10G_CHK1_DATA_10G_OFFSET (0) + #define RTL8373_SMI_REG_CHK1_DATA_10G_CHK1_DATA_10G_MASK (0xFFFF << RTL8373_SMI_REG_CHK1_DATA_10G_CHK1_DATA_10G_OFFSET) + +#define RTL8373_SMI_REG_CHK1_RESULT_ADDR (0x63A0) + #define RTL8373_SMI_REG_CHK1_RESULT_CHK1_RESULT_OFFSET (0) + #define RTL8373_SMI_REG_CHK1_RESULT_CHK1_RESULT_MASK (0x1FF << RTL8373_SMI_REG_CHK1_RESULT_CHK1_RESULT_OFFSET) + +#define RTL8373_SMI_REG_CHK2_CTRL1_ADDR (0x63A4) + #define RTL8373_SMI_REG_CHK2_CTRL1_CHK2_MODE_10G_OFFSET (21) + #define RTL8373_SMI_REG_CHK2_CTRL1_CHK2_MODE_10G_MASK (0x3 << RTL8373_SMI_REG_CHK2_CTRL1_CHK2_MODE_10G_OFFSET) + #define RTL8373_SMI_REG_CHK2_CTRL1_CHECK2_MMD_REG_OFFSET (5) + #define RTL8373_SMI_REG_CHK2_CTRL1_CHECK2_MMD_REG_MASK (0xFFFF << RTL8373_SMI_REG_CHK2_CTRL1_CHECK2_MMD_REG_OFFSET) + #define RTL8373_SMI_REG_CHK2_CTRL1_CHECK2_MMD_DEVAD_OFFSET (0) + #define RTL8373_SMI_REG_CHK2_CTRL1_CHECK2_MMD_DEVAD_MASK (0x1F << RTL8373_SMI_REG_CHK2_CTRL1_CHECK2_MMD_DEVAD_OFFSET) + +#define RTL8373_SMI_REG_CHK2_PMSK_ADDR (0x63A8) + #define RTL8373_SMI_REG_CHK2_PMSK_CHK2_PMSK_OFFSET (0) + #define RTL8373_SMI_REG_CHK2_PMSK_CHK2_PMSK_MASK (0x1FF << RTL8373_SMI_REG_CHK2_PMSK_CHK2_PMSK_OFFSET) + +#define RTL8373_SMI_REG_CHK2_DATA_10G_ADDR (0x63AC) + #define RTL8373_SMI_REG_CHK2_DATA_10G_CHK2_DMSK_10G_OFFSET (16) + #define RTL8373_SMI_REG_CHK2_DATA_10G_CHK2_DMSK_10G_MASK (0xFFFF << RTL8373_SMI_REG_CHK2_DATA_10G_CHK2_DMSK_10G_OFFSET) + #define RTL8373_SMI_REG_CHK2_DATA_10G_CHK2_DATA_10G_OFFSET (0) + #define RTL8373_SMI_REG_CHK2_DATA_10G_CHK2_DATA_10G_MASK (0xFFFF << RTL8373_SMI_REG_CHK2_DATA_10G_CHK2_DATA_10G_OFFSET) + +#define RTL8373_SMI_REG_CHK2_RESULT_ADDR (0x63B0) + #define RTL8373_SMI_REG_CHK2_RESULT_CHK2_RESULT_OFFSET (0) + #define RTL8373_SMI_REG_CHK2_RESULT_CHK2_RESULT_MASK (0x1FF << RTL8373_SMI_REG_CHK2_RESULT_CHK2_RESULT_OFFSET) + +#define RTL8373_SMI_REG_CHK3_CTRL1_ADDR (0x63B4) + #define RTL8373_SMI_REG_CHK3_CTRL1_CHK3_MODE_10G_OFFSET (21) + #define RTL8373_SMI_REG_CHK3_CTRL1_CHK3_MODE_10G_MASK (0x3 << RTL8373_SMI_REG_CHK3_CTRL1_CHK3_MODE_10G_OFFSET) + #define RTL8373_SMI_REG_CHK3_CTRL1_CHECK3_MMD_REG_OFFSET (5) + #define RTL8373_SMI_REG_CHK3_CTRL1_CHECK3_MMD_REG_MASK (0xFFFF << RTL8373_SMI_REG_CHK3_CTRL1_CHECK3_MMD_REG_OFFSET) + #define RTL8373_SMI_REG_CHK3_CTRL1_CHECK3_MMD_DEVAD_OFFSET (0) + #define RTL8373_SMI_REG_CHK3_CTRL1_CHECK3_MMD_DEVAD_MASK (0x1F << RTL8373_SMI_REG_CHK3_CTRL1_CHECK3_MMD_DEVAD_OFFSET) + +#define RTL8373_SMI_REG_CHK3_PMSK_ADDR (0x63B8) + #define RTL8373_SMI_REG_CHK3_PMSK_CHK3_PMSK_OFFSET (0) + #define RTL8373_SMI_REG_CHK3_PMSK_CHK3_PMSK_MASK (0x1FF << RTL8373_SMI_REG_CHK3_PMSK_CHK3_PMSK_OFFSET) + +#define RTL8373_SMI_REG_CHK3_DATA_10G_ADDR (0x63BC) + #define RTL8373_SMI_REG_CHK3_DATA_10G_CHK3_DMSK_10G_OFFSET (16) + #define RTL8373_SMI_REG_CHK3_DATA_10G_CHK3_DMSK_10G_MASK (0xFFFF << RTL8373_SMI_REG_CHK3_DATA_10G_CHK3_DMSK_10G_OFFSET) + #define RTL8373_SMI_REG_CHK3_DATA_10G_CHK3_DATA_10G_OFFSET (0) + #define RTL8373_SMI_REG_CHK3_DATA_10G_CHK3_DATA_10G_MASK (0xFFFF << RTL8373_SMI_REG_CHK3_DATA_10G_CHK3_DATA_10G_OFFSET) + +#define RTL8373_SMI_REG_CHK3_RESULT_ADDR (0x63C0) + #define RTL8373_SMI_REG_CHK3_RESULT_CHK3_RESULT_OFFSET (0) + #define RTL8373_SMI_REG_CHK3_RESULT_CHK3_RESULT_MASK (0x1FF << RTL8373_SMI_REG_CHK3_RESULT_CHK3_RESULT_OFFSET) + +#define RTL8373_SMI_REG_CHK4_CTRL1_ADDR (0x63C4) + #define RTL8373_SMI_REG_CHK4_CTRL1_CHK4_MODE_10G_OFFSET (21) + #define RTL8373_SMI_REG_CHK4_CTRL1_CHK4_MODE_10G_MASK (0x3 << RTL8373_SMI_REG_CHK4_CTRL1_CHK4_MODE_10G_OFFSET) + #define RTL8373_SMI_REG_CHK4_CTRL1_CHECK4_MMD_REG_OFFSET (5) + #define RTL8373_SMI_REG_CHK4_CTRL1_CHECK4_MMD_REG_MASK (0xFFFF << RTL8373_SMI_REG_CHK4_CTRL1_CHECK4_MMD_REG_OFFSET) + #define RTL8373_SMI_REG_CHK4_CTRL1_CHECK4_MMD_DEVAD_OFFSET (0) + #define RTL8373_SMI_REG_CHK4_CTRL1_CHECK4_MMD_DEVAD_MASK (0x1F << RTL8373_SMI_REG_CHK4_CTRL1_CHECK4_MMD_DEVAD_OFFSET) + +#define RTL8373_SMI_REG_CHK4_PMSK_ADDR (0x63C8) + #define RTL8373_SMI_REG_CHK4_PMSK_CHK4_PMSK_OFFSET (0) + #define RTL8373_SMI_REG_CHK4_PMSK_CHK4_PMSK_MASK (0x1FF << RTL8373_SMI_REG_CHK4_PMSK_CHK4_PMSK_OFFSET) + +#define RTL8373_SMI_REG_CHK4_DATA_10G_ADDR (0x63CC) + #define RTL8373_SMI_REG_CHK4_DATA_10G_CHK4_DMSK_10G_OFFSET (16) + #define RTL8373_SMI_REG_CHK4_DATA_10G_CHK4_DMSK_10G_MASK (0xFFFF << RTL8373_SMI_REG_CHK4_DATA_10G_CHK4_DMSK_10G_OFFSET) + #define RTL8373_SMI_REG_CHK4_DATA_10G_CHK4_DATA_10G_OFFSET (0) + #define RTL8373_SMI_REG_CHK4_DATA_10G_CHK4_DATA_10G_MASK (0xFFFF << RTL8373_SMI_REG_CHK4_DATA_10G_CHK4_DATA_10G_OFFSET) + +#define RTL8373_SMI_REG_CHK4_RESULT_ADDR (0x63D0) + #define RTL8373_SMI_REG_CHK4_RESULT_CHK4_RESULT_OFFSET (0) + #define RTL8373_SMI_REG_CHK4_RESULT_CHK4_RESULT_MASK (0x1FF << RTL8373_SMI_REG_CHK4_RESULT_CHK4_RESULT_OFFSET) + +#define RTL8373_SMI_REG_CHK5_CTRL1_ADDR (0x63D4) + #define RTL8373_SMI_REG_CHK5_CTRL1_CHK5_MODE_10G_OFFSET (21) + #define RTL8373_SMI_REG_CHK5_CTRL1_CHK5_MODE_10G_MASK (0x3 << RTL8373_SMI_REG_CHK5_CTRL1_CHK5_MODE_10G_OFFSET) + #define RTL8373_SMI_REG_CHK5_CTRL1_CHECK5_MMD_REG_OFFSET (5) + #define RTL8373_SMI_REG_CHK5_CTRL1_CHECK5_MMD_REG_MASK (0xFFFF << RTL8373_SMI_REG_CHK5_CTRL1_CHECK5_MMD_REG_OFFSET) + #define RTL8373_SMI_REG_CHK5_CTRL1_CHECK5_MMD_DEVAD_OFFSET (0) + #define RTL8373_SMI_REG_CHK5_CTRL1_CHECK5_MMD_DEVAD_MASK (0x1F << RTL8373_SMI_REG_CHK5_CTRL1_CHECK5_MMD_DEVAD_OFFSET) + +#define RTL8373_SMI_REG_CHK5_PMSK_ADDR (0x63D8) + #define RTL8373_SMI_REG_CHK5_PMSK_CHK5_PMSK_OFFSET (0) + #define RTL8373_SMI_REG_CHK5_PMSK_CHK5_PMSK_MASK (0x1FF << RTL8373_SMI_REG_CHK5_PMSK_CHK5_PMSK_OFFSET) + +#define RTL8373_SMI_REG_CHK5_DATA_10G_ADDR (0x63DC) + #define RTL8373_SMI_REG_CHK5_DATA_10G_CHK5_DMSK_10G_OFFSET (16) + #define RTL8373_SMI_REG_CHK5_DATA_10G_CHK5_DMSK_10G_MASK (0xFFFF << RTL8373_SMI_REG_CHK5_DATA_10G_CHK5_DMSK_10G_OFFSET) + #define RTL8373_SMI_REG_CHK5_DATA_10G_CHK5_DATA_10G_OFFSET (0) + #define RTL8373_SMI_REG_CHK5_DATA_10G_CHK5_DATA_10G_MASK (0xFFFF << RTL8373_SMI_REG_CHK5_DATA_10G_CHK5_DATA_10G_OFFSET) + +#define RTL8373_SMI_REG_CHK5_RESULT_ADDR (0x63E0) + #define RTL8373_SMI_REG_CHK5_RESULT_CHK5_RESULT_OFFSET (0) + #define RTL8373_SMI_REG_CHK5_RESULT_CHK5_RESULT_MASK (0x1FF << RTL8373_SMI_REG_CHK5_RESULT_CHK5_RESULT_OFFSET) + +#define RTL8373_LINK_DELAY_CTRL_ADDR (0x63E4) + #define RTL8373_LINK_DELAY_CTRL_TX_IDLE_TMR_OFFSET (17) + #define RTL8373_LINK_DELAY_CTRL_TX_IDLE_TMR_MASK (0xFF << RTL8373_LINK_DELAY_CTRL_TX_IDLE_TMR_OFFSET) + #define RTL8373_LINK_DELAY_CTRL_DOWN2UP_DLY_EN_OFFSET (8) + #define RTL8373_LINK_DELAY_CTRL_DOWN2UP_DLY_EN_MASK (0x1FF << RTL8373_LINK_DELAY_CTRL_DOWN2UP_DLY_EN_OFFSET) + #define RTL8373_LINK_DELAY_CTRL_LNKDN_FRC_DIS_OFFSET (7) + #define RTL8373_LINK_DELAY_CTRL_LNKDN_FRC_DIS_MASK (0x1 << RTL8373_LINK_DELAY_CTRL_LNKDN_FRC_DIS_OFFSET) + #define RTL8373_LINK_DELAY_CTRL_LINKUP_DELAY_10G_5G_OFFSET (5) + #define RTL8373_LINK_DELAY_CTRL_LINKUP_DELAY_10G_5G_MASK (0x3 << RTL8373_LINK_DELAY_CTRL_LINKUP_DELAY_10G_5G_OFFSET) + #define RTL8373_LINK_DELAY_CTRL_LINKUP_DELAY_2P5G_1000M_100M_OFFSET (3) + #define RTL8373_LINK_DELAY_CTRL_LINKUP_DELAY_2P5G_1000M_100M_MASK (0x3 << RTL8373_LINK_DELAY_CTRL_LINKUP_DELAY_2P5G_1000M_100M_OFFSET) + #define RTL8373_LINK_DELAY_CTRL_LINKUP_DELAY_10M_OFFSET (0) + #define RTL8373_LINK_DELAY_CTRL_LINKUP_DELAY_10M_MASK (0x7 << RTL8373_LINK_DELAY_CTRL_LINKUP_DELAY_10M_OFFSET) + +#define RTL8373_MAC_LINK_STS_ADDR (0x63E8) + #define RTL8373_MAC_LINK_STS_MAC_LINK_STS_9_0_OFFSET (16) + #define RTL8373_MAC_LINK_STS_MAC_LINK_STS_9_0_MASK (0x3FF << RTL8373_MAC_LINK_STS_MAC_LINK_STS_9_0_OFFSET) + #define RTL8373_MAC_LINK_STS_LINK_STS_9_0_OFFSET (0) + #define RTL8373_MAC_LINK_STS_LINK_STS_9_0_MASK (0x3FF << RTL8373_MAC_LINK_STS_LINK_STS_9_0_OFFSET) + +#define RTL8373_MAC_LINK_MEDIA_STS_ADDR (0x63EC) + #define RTL8373_MAC_LINK_MEDIA_STS_MEDIA_STS_9_0_OFFSET (0) + #define RTL8373_MAC_LINK_MEDIA_STS_MEDIA_STS_9_0_MASK (0x3FF << RTL8373_MAC_LINK_MEDIA_STS_MEDIA_STS_9_0_OFFSET) + +#define RTL8373_MAC_LINK_SPD_STS_ADDR(port) (0x63F0 + (((port >> 3) << 2))) /* port: 0-9 */ + #define RTL8373_MAC_LINK_SPD_STS_SPD_STS_9_0_OFFSET(port) ((port & 0x7) << 2) + #define RTL8373_MAC_LINK_SPD_STS_SPD_STS_9_0_MASK(port) (0xF << RTL8373_MAC_LINK_SPD_STS_SPD_STS_9_0_OFFSET(port)) + +#define RTL8373_MAC_LINK_DUP_STS_ADDR (0x63F8) + #define RTL8373_MAC_LINK_DUP_STS_DUP_STS_9_0_OFFSET (0) + #define RTL8373_MAC_LINK_DUP_STS_DUP_STS_9_0_MASK (0x3FF << RTL8373_MAC_LINK_DUP_STS_DUP_STS_9_0_OFFSET) + +#define RTL8373_MAC_TX_PAUSE_STS_ADDR (0x63FC) + #define RTL8373_MAC_TX_PAUSE_STS_TX_PAUSE_STS_9_0_OFFSET (0) + #define RTL8373_MAC_TX_PAUSE_STS_TX_PAUSE_STS_9_0_MASK (0x3FF << RTL8373_MAC_TX_PAUSE_STS_TX_PAUSE_STS_9_0_OFFSET) + +#define RTL8373_MAC_RX_PAUSE_STS_ADDR (0x6400) + #define RTL8373_MAC_RX_PAUSE_STS_RX_PAUSE_STS_9_0_OFFSET (0) + #define RTL8373_MAC_RX_PAUSE_STS_RX_PAUSE_STS_9_0_MASK (0x3FF << RTL8373_MAC_RX_PAUSE_STS_RX_PAUSE_STS_9_0_OFFSET) + +#define RTL8373_MAC_EEE_ABLTY_ADDR (0x6404) + #define RTL8373_MAC_EEE_ABLTY_EEE_ABLTY_9_0_OFFSET (0) + #define RTL8373_MAC_EEE_ABLTY_EEE_ABLTY_9_0_MASK (0x3FF << RTL8373_MAC_EEE_ABLTY_EEE_ABLTY_9_0_OFFSET) + +#define RTL8373_MAC_MSTR_SLV_STS_ADDR (0x6408) + #define RTL8373_MAC_MSTR_SLV_STS_MSTR_SLV_STS_8_0_OFFSET (0) + #define RTL8373_MAC_MSTR_SLV_STS_MSTR_SLV_STS_8_0_MASK (0x1FF << RTL8373_MAC_MSTR_SLV_STS_MSTR_SLV_STS_8_0_OFFSET) + +#define RTL8373_MAC_MSTR_SLV_FAULT_STS_ADDR (0x640C) + #define RTL8373_MAC_MSTR_SLV_FAULT_STS_MSTR_SLV_FAULT_STS_8_0_OFFSET (0) + #define RTL8373_MAC_MSTR_SLV_FAULT_STS_MSTR_SLV_FAULT_STS_8_0_MASK (0x1FF << RTL8373_MAC_MSTR_SLV_FAULT_STS_MSTR_SLV_FAULT_STS_8_0_OFFSET) + +#define RTL8373_PHY_LINK_STS_ADDR (0x6410) + #define RTL8373_PHY_LINK_STS_LINK_STS_8_0_OFFSET (0) + #define RTL8373_PHY_LINK_STS_LINK_STS_8_0_MASK (0x1FF << RTL8373_PHY_LINK_STS_LINK_STS_8_0_OFFSET) + +#define RTL8373_PHY_LINK_MEDIA_STS_ADDR (0x6414) + #define RTL8373_PHY_LINK_MEDIA_STS_MEDIA_STS_8_0_OFFSET (0) + #define RTL8373_PHY_LINK_MEDIA_STS_MEDIA_STS_8_0_MASK (0x1FF << RTL8373_PHY_LINK_MEDIA_STS_MEDIA_STS_8_0_OFFSET) + +#define RTL8373_PHY_LINK_SPD_STS_ADDR(port) (0x6418 + (((port >> 3) << 2))) /* port: 0-8 */ + #define RTL8373_PHY_LINK_SPD_STS_SPD_STS_8_0_OFFSET(port) ((port & 0x7) << 2) + #define RTL8373_PHY_LINK_SPD_STS_SPD_STS_8_0_MASK(port) (0xF << RTL8373_PHY_LINK_SPD_STS_SPD_STS_8_0_OFFSET(port)) + +#define RTL8373_PHY_LINK_DUP_STS_ADDR (0x6420) + #define RTL8373_PHY_LINK_DUP_STS_DUP_STS_8_0_OFFSET (0) + #define RTL8373_PHY_LINK_DUP_STS_DUP_STS_8_0_MASK (0x1FF << RTL8373_PHY_LINK_DUP_STS_DUP_STS_8_0_OFFSET) + +#define RTL8373_PHY_TX_PAUSE_STS_ADDR (0x6424) + #define RTL8373_PHY_TX_PAUSE_STS_TX_PAUSE_STS_8_0_OFFSET (0) + #define RTL8373_PHY_TX_PAUSE_STS_TX_PAUSE_STS_8_0_MASK (0x1FF << RTL8373_PHY_TX_PAUSE_STS_TX_PAUSE_STS_8_0_OFFSET) + +#define RTL8373_PHY_RX_PAUSE_STS_ADDR (0x6428) + #define RTL8373_PHY_RX_PAUSE_STS_RX_PAUSE_STS_8_0_OFFSET (0) + #define RTL8373_PHY_RX_PAUSE_STS_RX_PAUSE_STS_8_0_MASK (0x1FF << RTL8373_PHY_RX_PAUSE_STS_RX_PAUSE_STS_8_0_OFFSET) + +#define RTL8373_PHY_EEE_ABLTY_ADDR (0x642C) + #define RTL8373_PHY_EEE_ABLTY_EEE_ABLTY_8_0_OFFSET (0) + #define RTL8373_PHY_EEE_ABLTY_EEE_ABLTY_8_0_MASK (0x1FF << RTL8373_PHY_EEE_ABLTY_EEE_ABLTY_8_0_OFFSET) + +#define RTL8373_PHY_MSTR_SLV_STS_ADDR (0x6430) + #define RTL8373_PHY_MSTR_SLV_STS_MSTR_SLV_STS_8_0_OFFSET (0) + #define RTL8373_PHY_MSTR_SLV_STS_MSTR_SLV_STS_8_0_MASK (0x1FF << RTL8373_PHY_MSTR_SLV_STS_MSTR_SLV_STS_8_0_OFFSET) + +#define RTL8373_PHY_MSTR_SLV_FAULT_STS_ADDR (0x6434) + #define RTL8373_PHY_MSTR_SLV_FAULT_STS_MSTR_SLV_FAULT_STS_8_0_OFFSET (0) + #define RTL8373_PHY_MSTR_SLV_FAULT_STS_MSTR_SLV_FAULT_STS_8_0_MASK (0x1FF << RTL8373_PHY_MSTR_SLV_FAULT_STS_MSTR_SLV_FAULT_STS_8_0_OFFSET) + +#define RTL8373_SMI_ACCESS_PHY_CTRL_0_ADDR (0x6438) + #define RTL8373_SMI_ACCESS_PHY_CTRL_0_PHY_BRDCAST_OFFSET (9) + #define RTL8373_SMI_ACCESS_PHY_CTRL_0_PHY_BRDCAST_MASK (0x1 << RTL8373_SMI_ACCESS_PHY_CTRL_0_PHY_BRDCAST_OFFSET) + #define RTL8373_SMI_ACCESS_PHY_CTRL_0_PHY_MASK_OFFSET (0) + #define RTL8373_SMI_ACCESS_PHY_CTRL_0_PHY_MASK_MASK (0x1FF << RTL8373_SMI_ACCESS_PHY_CTRL_0_PHY_MASK_OFFSET) + +#define RTL8373_SMI_ACCESS_PHY_CTRL_1_ADDR (0x643C) + #define RTL8373_SMI_ACCESS_PHY_CTRL_1_FAIL_OFFSET (24) + #define RTL8373_SMI_ACCESS_PHY_CTRL_1_FAIL_MASK (0x7 << RTL8373_SMI_ACCESS_PHY_CTRL_1_FAIL_OFFSET) + #define RTL8373_SMI_ACCESS_PHY_CTRL_1_MMD_DEVAD_4_0_OFFSET (19) + #define RTL8373_SMI_ACCESS_PHY_CTRL_1_MMD_DEVAD_4_0_MASK (0x1F << RTL8373_SMI_ACCESS_PHY_CTRL_1_MMD_DEVAD_4_0_OFFSET) + #define RTL8373_SMI_ACCESS_PHY_CTRL_1_MMD_REG_15_0_OFFSET (3) + #define RTL8373_SMI_ACCESS_PHY_CTRL_1_MMD_REG_15_0_MASK (0xFFFF << RTL8373_SMI_ACCESS_PHY_CTRL_1_MMD_REG_15_0_OFFSET) + #define RTL8373_SMI_ACCESS_PHY_CTRL_1_RWOP_OFFSET (2) + #define RTL8373_SMI_ACCESS_PHY_CTRL_1_RWOP_MASK (0x1 << RTL8373_SMI_ACCESS_PHY_CTRL_1_RWOP_OFFSET) + #define RTL8373_SMI_ACCESS_PHY_CTRL_1_TYPE_OFFSET (1) + #define RTL8373_SMI_ACCESS_PHY_CTRL_1_TYPE_MASK (0x1 << RTL8373_SMI_ACCESS_PHY_CTRL_1_TYPE_OFFSET) + #define RTL8373_SMI_ACCESS_PHY_CTRL_1_CMD_OFFSET (0) + #define RTL8373_SMI_ACCESS_PHY_CTRL_1_CMD_MASK (0x1 << RTL8373_SMI_ACCESS_PHY_CTRL_1_CMD_OFFSET) + +#define RTL8373_SMI_ACCESS_PHY_CTRL_2_ADDR (0x6440) + #define RTL8373_SMI_ACCESS_PHY_CTRL_2_DATA_15_0_OFFSET (0) + #define RTL8373_SMI_ACCESS_PHY_CTRL_2_DATA_15_0_MASK (0xFFFF << RTL8373_SMI_ACCESS_PHY_CTRL_2_DATA_15_0_OFFSET) + +#define RTL8373_SMI_ACCESS_PHY_CTRL_3_ADDR (0x6444) + #define RTL8373_SMI_ACCESS_PHY_CTRL_3_INDATA_15_0_OFFSET (0) + #define RTL8373_SMI_ACCESS_PHY_CTRL_3_INDATA_15_0_MASK (0xFFFF << RTL8373_SMI_ACCESS_PHY_CTRL_3_INDATA_15_0_OFFSET) + +#define RTL8373_SMI_ACCESS_PHY_CTRL_4_ADDR (0x6448) + #define RTL8373_SMI_ACCESS_PHY_CTRL_4_REG_ADDR_4_0_OFFSET (17) + #define RTL8373_SMI_ACCESS_PHY_CTRL_4_REG_ADDR_4_0_MASK (0x1F << RTL8373_SMI_ACCESS_PHY_CTRL_4_REG_ADDR_4_0_OFFSET) + #define RTL8373_SMI_ACCESS_PHY_CTRL_4_PARK_PAGE_4_0_OFFSET (12) + #define RTL8373_SMI_ACCESS_PHY_CTRL_4_PARK_PAGE_4_0_MASK (0x1F << RTL8373_SMI_ACCESS_PHY_CTRL_4_PARK_PAGE_4_0_OFFSET) + #define RTL8373_SMI_ACCESS_PHY_CTRL_4_MAIN_PAGE_11_0_OFFSET (0) + #define RTL8373_SMI_ACCESS_PHY_CTRL_4_MAIN_PAGE_11_0_MASK (0xFFF << RTL8373_SMI_ACCESS_PHY_CTRL_4_MAIN_PAGE_11_0_OFFSET) + +#define RTL8373_SMI_PORT0_5_ADDR_CTRL_ADDR (0x644C) + #define RTL8373_SMI_PORT0_5_ADDR_CTRL_PORT5_ADDR_OFFSET (25) + #define RTL8373_SMI_PORT0_5_ADDR_CTRL_PORT5_ADDR_MASK (0x1F << RTL8373_SMI_PORT0_5_ADDR_CTRL_PORT5_ADDR_OFFSET) + #define RTL8373_SMI_PORT0_5_ADDR_CTRL_PORT4_ADDR_OFFSET (20) + #define RTL8373_SMI_PORT0_5_ADDR_CTRL_PORT4_ADDR_MASK (0x1F << RTL8373_SMI_PORT0_5_ADDR_CTRL_PORT4_ADDR_OFFSET) + #define RTL8373_SMI_PORT0_5_ADDR_CTRL_PORT3_ADDR_OFFSET (15) + #define RTL8373_SMI_PORT0_5_ADDR_CTRL_PORT3_ADDR_MASK (0x1F << RTL8373_SMI_PORT0_5_ADDR_CTRL_PORT3_ADDR_OFFSET) + #define RTL8373_SMI_PORT0_5_ADDR_CTRL_PORT2_ADDR_OFFSET (10) + #define RTL8373_SMI_PORT0_5_ADDR_CTRL_PORT2_ADDR_MASK (0x1F << RTL8373_SMI_PORT0_5_ADDR_CTRL_PORT2_ADDR_OFFSET) + #define RTL8373_SMI_PORT0_5_ADDR_CTRL_PORT1_ADDR_OFFSET (5) + #define RTL8373_SMI_PORT0_5_ADDR_CTRL_PORT1_ADDR_MASK (0x1F << RTL8373_SMI_PORT0_5_ADDR_CTRL_PORT1_ADDR_OFFSET) + #define RTL8373_SMI_PORT0_5_ADDR_CTRL_PORT0_ADDR_OFFSET (0) + #define RTL8373_SMI_PORT0_5_ADDR_CTRL_PORT0_ADDR_MASK (0x1F << RTL8373_SMI_PORT0_5_ADDR_CTRL_PORT0_ADDR_OFFSET) + +#define RTL8373_SMI_PORT6_9_ADDR_CTRL_ADDR (0x6450) + #define RTL8373_SMI_PORT6_9_ADDR_CTRL_PORT8_ADDR_OFFSET (10) + #define RTL8373_SMI_PORT6_9_ADDR_CTRL_PORT8_ADDR_MASK (0x1F << RTL8373_SMI_PORT6_9_ADDR_CTRL_PORT8_ADDR_OFFSET) + #define RTL8373_SMI_PORT6_9_ADDR_CTRL_PORT7_ADDR_OFFSET (5) + #define RTL8373_SMI_PORT6_9_ADDR_CTRL_PORT7_ADDR_MASK (0x1F << RTL8373_SMI_PORT6_9_ADDR_CTRL_PORT7_ADDR_OFFSET) + #define RTL8373_SMI_PORT6_9_ADDR_CTRL_PORT6_ADDR_OFFSET (0) + #define RTL8373_SMI_PORT6_9_ADDR_CTRL_PORT6_ADDR_MASK (0x1F << RTL8373_SMI_PORT6_9_ADDR_CTRL_PORT6_ADDR_OFFSET) + +#define RTL8373_SMI_CTRL_ADDR (0x6454) + #define RTL8373_SMI_CTRL_SMI2_MDC_EN_OFFSET (14) + #define RTL8373_SMI_CTRL_SMI2_MDC_EN_MASK (0x1 << RTL8373_SMI_CTRL_SMI2_MDC_EN_OFFSET) + #define RTL8373_SMI_CTRL_SMI1_MDC_EN_OFFSET (13) + #define RTL8373_SMI_CTRL_SMI1_MDC_EN_MASK (0x1 << RTL8373_SMI_CTRL_SMI1_MDC_EN_OFFSET) + #define RTL8373_SMI_CTRL_SMI0_MDC_EN_OFFSET (12) + #define RTL8373_SMI_CTRL_SMI0_MDC_EN_MASK (0x1 << RTL8373_SMI_CTRL_SMI0_MDC_EN_OFFSET) + #define RTL8373_SMI_CTRL_SMI2_DLY_CFG_OFFSET (8) + #define RTL8373_SMI_CTRL_SMI2_DLY_CFG_MASK (0xF << RTL8373_SMI_CTRL_SMI2_DLY_CFG_OFFSET) + #define RTL8373_SMI_CTRL_SMI1_DLY_CFG_OFFSET (4) + #define RTL8373_SMI_CTRL_SMI1_DLY_CFG_MASK (0xF << RTL8373_SMI_CTRL_SMI1_DLY_CFG_OFFSET) + #define RTL8373_SMI_CTRL_SMI0_DLY_CFG_OFFSET (0) + #define RTL8373_SMI_CTRL_SMI0_DLY_CFG_MASK (0xF << RTL8373_SMI_CTRL_SMI0_DLY_CFG_OFFSET) + +#define RTL8373_RLFD_CTRL_ADDR (0x6458) + #define RTL8373_RLFD_CTRL_RLFD_SEL_OFFSET (10) + #define RTL8373_RLFD_CTRL_RLFD_SEL_MASK (0x1 << RTL8373_RLFD_CTRL_RLFD_SEL_OFFSET) + #define RTL8373_RLFD_CTRL_RLFD_EN_OFFSET (9) + #define RTL8373_RLFD_CTRL_RLFD_EN_MASK (0x1 << RTL8373_RLFD_CTRL_RLFD_EN_OFFSET) + #define RTL8373_RLFD_CTRL_RLFD_STS_OFFSET (0) + #define RTL8373_RLFD_CTRL_RLFD_STS_MASK (0x1FF << RTL8373_RLFD_CTRL_RLFD_STS_OFFSET) + +#define RTL8373_RLFD_10G_ADDR_ADDR (0x645C) + #define RTL8373_RLFD_10G_ADDR_RLFD_DEV_2P5G_10GPHY_OFFSET (20) + #define RTL8373_RLFD_10G_ADDR_RLFD_DEV_2P5G_10GPHY_MASK (0x1F << RTL8373_RLFD_10G_ADDR_RLFD_DEV_2P5G_10GPHY_OFFSET) + #define RTL8373_RLFD_10G_ADDR_RLFD_REG_2P5G_10GPHY_OFFSET (4) + #define RTL8373_RLFD_10G_ADDR_RLFD_REG_2P5G_10GPHY_MASK (0xFFFF << RTL8373_RLFD_10G_ADDR_RLFD_REG_2P5G_10GPHY_OFFSET) + #define RTL8373_RLFD_10G_ADDR_RLFD_BIT_2P5G_10GPHY_OFFSET (0) + #define RTL8373_RLFD_10G_ADDR_RLFD_BIT_2P5G_10GPHY_MASK (0xF << RTL8373_RLFD_10G_ADDR_RLFD_BIT_2P5G_10GPHY_OFFSET) + +#define RTL8373_UNI_DIR_CTRL_ADDR (0x6460) + #define RTL8373_UNI_DIR_CTRL_UNIDIR_WIN_DLY_OFFSET (11) + #define RTL8373_UNI_DIR_CTRL_UNIDIR_WIN_DLY_MASK (0x3 << RTL8373_UNI_DIR_CTRL_UNIDIR_WIN_DLY_OFFSET) + #define RTL8373_UNI_DIR_CTRL_FIB_UNIDIR_ONLY_CPUTX_EN_OFFSET (10) + #define RTL8373_UNI_DIR_CTRL_FIB_UNIDIR_ONLY_CPUTX_EN_MASK (0x1 << RTL8373_UNI_DIR_CTRL_FIB_UNIDIR_ONLY_CPUTX_EN_OFFSET) + #define RTL8373_UNI_DIR_CTRL_FIB_UNIDIR_EN_OFFSET (0) + #define RTL8373_UNI_DIR_CTRL_FIB_UNIDIR_EN_MASK (0x3FF << RTL8373_UNI_DIR_CTRL_FIB_UNIDIR_EN_OFFSET) + +#define RTL8373_SMI_10GPHY_POLLING_SEL_1_ADDR (0x6464) + #define RTL8373_SMI_10GPHY_POLLING_SEL_1_INTDEV1_POLLING_10GPHY_OFFSET (16) + #define RTL8373_SMI_10GPHY_POLLING_SEL_1_INTDEV1_POLLING_10GPHY_MASK (0x1F << RTL8373_SMI_10GPHY_POLLING_SEL_1_INTDEV1_POLLING_10GPHY_OFFSET) + #define RTL8373_SMI_10GPHY_POLLING_SEL_1_INTREG1_POLLING_10GPHY_OFFSET (0) + #define RTL8373_SMI_10GPHY_POLLING_SEL_1_INTREG1_POLLING_10GPHY_MASK (0xFFFF << RTL8373_SMI_10GPHY_POLLING_SEL_1_INTREG1_POLLING_10GPHY_OFFSET) + +#define RTL8373_SMI_10GPHY_POLLING_REG0_CFG_ADDR(port) (0x6468 + (((port) << 2))) /* port: 0-2 */ + #define RTL8373_SMI_10GPHY_POLLING_REG0_CFG_REG0_BIT_2P5G_10GPHY_OFFSET (21) + #define RTL8373_SMI_10GPHY_POLLING_REG0_CFG_REG0_BIT_2P5G_10GPHY_MASK (0xF << RTL8373_SMI_10GPHY_POLLING_REG0_CFG_REG0_BIT_2P5G_10GPHY_OFFSET) + #define RTL8373_SMI_10GPHY_POLLING_REG0_CFG_REG0_DEV_2P5G_10GPHY_OFFSET (16) + #define RTL8373_SMI_10GPHY_POLLING_REG0_CFG_REG0_DEV_2P5G_10GPHY_MASK (0x1F << RTL8373_SMI_10GPHY_POLLING_REG0_CFG_REG0_DEV_2P5G_10GPHY_OFFSET) + #define RTL8373_SMI_10GPHY_POLLING_REG0_CFG_REG0_REG_2P5G_10GPHY_OFFSET (0) + #define RTL8373_SMI_10GPHY_POLLING_REG0_CFG_REG0_REG_2P5G_10GPHY_MASK (0xFFFF << RTL8373_SMI_10GPHY_POLLING_REG0_CFG_REG0_REG_2P5G_10GPHY_OFFSET) + +#define RTL8373_SMI_10GPHY_POLLING_REG9_CFG_ADDR(port) (0x6474 + (((port) << 2))) /* port: 0-2 */ + #define RTL8373_SMI_10GPHY_POLLING_REG9_CFG_REG9_BIT_2P5G_10GPHY_OFFSET (21) + #define RTL8373_SMI_10GPHY_POLLING_REG9_CFG_REG9_BIT_2P5G_10GPHY_MASK (0xF << RTL8373_SMI_10GPHY_POLLING_REG9_CFG_REG9_BIT_2P5G_10GPHY_OFFSET) + #define RTL8373_SMI_10GPHY_POLLING_REG9_CFG_REG9_DEV_2P5G_10GPHY_OFFSET (16) + #define RTL8373_SMI_10GPHY_POLLING_REG9_CFG_REG9_DEV_2P5G_10GPHY_MASK (0x1F << RTL8373_SMI_10GPHY_POLLING_REG9_CFG_REG9_DEV_2P5G_10GPHY_OFFSET) + #define RTL8373_SMI_10GPHY_POLLING_REG9_CFG_REG9_REG_2P5G_10GPHY_OFFSET (0) + #define RTL8373_SMI_10GPHY_POLLING_REG9_CFG_REG9_REG_2P5G_10GPHY_MASK (0xFFFF << RTL8373_SMI_10GPHY_POLLING_REG9_CFG_REG9_REG_2P5G_10GPHY_OFFSET) + +#define RTL8373_SMI_10GPHY_POLLING_REG10_CFG_ADDR(port) (0x6480 + (((port) << 2))) /* port: 0-2 */ + #define RTL8373_SMI_10GPHY_POLLING_REG10_CFG_REG10_BIT_2P5G_10GPHY_OFFSET (21) + #define RTL8373_SMI_10GPHY_POLLING_REG10_CFG_REG10_BIT_2P5G_10GPHY_MASK (0xF << RTL8373_SMI_10GPHY_POLLING_REG10_CFG_REG10_BIT_2P5G_10GPHY_OFFSET) + #define RTL8373_SMI_10GPHY_POLLING_REG10_CFG_REG10_DEV_2P5G_10GPHY_OFFSET (16) + #define RTL8373_SMI_10GPHY_POLLING_REG10_CFG_REG10_DEV_2P5G_10GPHY_MASK (0x1F << RTL8373_SMI_10GPHY_POLLING_REG10_CFG_REG10_DEV_2P5G_10GPHY_OFFSET) + #define RTL8373_SMI_10GPHY_POLLING_REG10_CFG_REG10_REG_2P5G_10GPHY_OFFSET (0) + #define RTL8373_SMI_10GPHY_POLLING_REG10_CFG_REG10_REG_2P5G_10GPHY_MASK (0xFFFF << RTL8373_SMI_10GPHY_POLLING_REG10_CFG_REG10_REG_2P5G_10GPHY_OFFSET) + +#define RTL8373_MAC_CTRL_1_ADDR (0x648C) + #define RTL8373_MAC_CTRL_1_MAC_SPD_ABLTY2_OFFSET (16) + #define RTL8373_MAC_CTRL_1_MAC_SPD_ABLTY2_MASK (0xFF << RTL8373_MAC_CTRL_1_MAC_SPD_ABLTY2_OFFSET) + #define RTL8373_MAC_CTRL_1_MAC_SPD_ABLTY1_OFFSET (8) + #define RTL8373_MAC_CTRL_1_MAC_SPD_ABLTY1_MASK (0xFF << RTL8373_MAC_CTRL_1_MAC_SPD_ABLTY1_OFFSET) + #define RTL8373_MAC_CTRL_1_MAC_SPD_ABLTY0_OFFSET (0) + #define RTL8373_MAC_CTRL_1_MAC_SPD_ABLTY0_MASK (0xFF << RTL8373_MAC_CTRL_1_MAC_SPD_ABLTY0_OFFSET) + +#define RTL8373_MAC_CTRL_2_ADDR (0x6490) + #define RTL8373_MAC_CTRL_2_MAC_SPD_ABLTY_BYP_OFFSET (0) + #define RTL8373_MAC_CTRL_2_MAC_SPD_ABLTY_BYP_MASK (0x3FF << RTL8373_MAC_CTRL_2_MAC_SPD_ABLTY_BYP_OFFSET) + +#define RTL8373_MAC8_RTL8226B_CTRL_ADDR (0x6494) + #define RTL8373_MAC8_RTL8226B_CTRL_MAC3_SDS0_MODE_OFFSET (5) + #define RTL8373_MAC8_RTL8226B_CTRL_MAC3_SDS0_MODE_MASK (0x1F << RTL8373_MAC8_RTL8226B_CTRL_MAC3_SDS0_MODE_OFFSET) + #define RTL8373_MAC8_RTL8226B_CTRL_MAC8_SDS1_MODE_OFFSET (0) + #define RTL8373_MAC8_RTL8226B_CTRL_MAC8_SDS1_MODE_MASK (0x1F << RTL8373_MAC8_RTL8226B_CTRL_MAC8_SDS1_MODE_OFFSET) + +#define RTL8373_TX_RX_IDLE_ADDR (0x6498) + #define RTL8373_TX_RX_IDLE_WAIT_FOR_TX_IDLE_OFFSET (18) + #define RTL8373_TX_RX_IDLE_WAIT_FOR_TX_IDLE_MASK (0x1FF << RTL8373_TX_RX_IDLE_WAIT_FOR_TX_IDLE_OFFSET) + #define RTL8373_TX_RX_IDLE_WAIT_FOR_RX_IDLE_OFFSET (9) + #define RTL8373_TX_RX_IDLE_WAIT_FOR_RX_IDLE_MASK (0x1FF << RTL8373_TX_RX_IDLE_WAIT_FOR_RX_IDLE_OFFSET) + #define RTL8373_TX_RX_IDLE_REF_RX_IDLE_OFFSET (0) + #define RTL8373_TX_RX_IDLE_REF_RX_IDLE_MASK (0x1FF << RTL8373_TX_RX_IDLE_REF_RX_IDLE_OFFSET) + +#define RTL8373_IDLE_DLY_CTRL_ADDR (0x101C) + #define RTL8373_IDLE_DLY_CTRL_TX_IDLE_TIMER_OFFSET (8) + #define RTL8373_IDLE_DLY_CTRL_TX_IDLE_TIMER_MASK (0xFF << RTL8373_IDLE_DLY_CTRL_TX_IDLE_TIMER_OFFSET) + #define RTL8373_IDLE_DLY_CTRL_RX_IDLE_TIMER_OFFSET (0) + #define RTL8373_IDLE_DLY_CTRL_RX_IDLE_TIMER_MASK (0xFF << RTL8373_IDLE_DLY_CTRL_RX_IDLE_TIMER_OFFSET) + +#define RTL8373_MAC_IPG_COMPS_CTRL_ADDR(port) (0x1234 + (((port) << 8))) /* port: 0-9 */ + #define RTL8373_MAC_IPG_COMPS_CTRL_IPG_COMPS_EN_OFFSET (2) + #define RTL8373_MAC_IPG_COMPS_CTRL_IPG_COMPS_EN_MASK (0x1 << RTL8373_MAC_IPG_COMPS_CTRL_IPG_COMPS_EN_OFFSET) + #define RTL8373_MAC_IPG_COMPS_CTRL_IPG_COMPS_SEL_OFFSET (1) + #define RTL8373_MAC_IPG_COMPS_CTRL_IPG_COMPS_SEL_MASK (0x1 << RTL8373_MAC_IPG_COMPS_CTRL_IPG_COMPS_SEL_OFFSET) + #define RTL8373_MAC_IPG_COMPS_CTRL_IPG_4N_BYTE_COMPS_EN_OFFSET (0) + #define RTL8373_MAC_IPG_COMPS_CTRL_IPG_4N_BYTE_COMPS_EN_MASK (0x1 << RTL8373_MAC_IPG_COMPS_CTRL_IPG_4N_BYTE_COMPS_EN_OFFSET) + +#define RTL8373_MAC_L2_GLOBAL_CTRL0_ADDR (0x5FD4) + #define RTL8373_MAC_L2_GLOBAL_CTRL0_FWD_PAUSE_EN_OFFSET (21) + #define RTL8373_MAC_L2_GLOBAL_CTRL0_FWD_PAUSE_EN_MASK (0x1 << RTL8373_MAC_L2_GLOBAL_CTRL0_FWD_PAUSE_EN_OFFSET) + #define RTL8373_MAC_L2_GLOBAL_CTRL0_FWD_INVLD_MAC_CTRL_EN_OFFSET (20) + #define RTL8373_MAC_L2_GLOBAL_CTRL0_FWD_INVLD_MAC_CTRL_EN_MASK (0x1 << RTL8373_MAC_L2_GLOBAL_CTRL0_FWD_INVLD_MAC_CTRL_EN_OFFSET) + #define RTL8373_MAC_L2_GLOBAL_CTRL0_FWD_UNKN_OPCODE_EN_OFFSET (19) + #define RTL8373_MAC_L2_GLOBAL_CTRL0_FWD_UNKN_OPCODE_EN_MASK (0x1 << RTL8373_MAC_L2_GLOBAL_CTRL0_FWD_UNKN_OPCODE_EN_OFFSET) + #define RTL8373_MAC_L2_GLOBAL_CTRL0_LIMIT_PAUSE_EN_OFFSET (17) + #define RTL8373_MAC_L2_GLOBAL_CTRL0_LIMIT_PAUSE_EN_MASK (0x3 << RTL8373_MAC_L2_GLOBAL_CTRL0_LIMIT_PAUSE_EN_OFFSET) + #define RTL8373_MAC_L2_GLOBAL_CTRL0_CRC_CPU_RC_EN_OFFSET (15) + #define RTL8373_MAC_L2_GLOBAL_CTRL0_CRC_CPU_RC_EN_MASK (0x3 << RTL8373_MAC_L2_GLOBAL_CTRL0_CRC_CPU_RC_EN_OFFSET) + #define RTL8373_MAC_L2_GLOBAL_CTRL0_FWD_PFC_EN_OFFSET (14) + #define RTL8373_MAC_L2_GLOBAL_CTRL0_FWD_PFC_EN_MASK (0x1 << RTL8373_MAC_L2_GLOBAL_CTRL0_FWD_PFC_EN_OFFSET) + #define RTL8373_MAC_L2_GLOBAL_CTRL0_LIMIT_PFC_EN_OFFSET (12) + #define RTL8373_MAC_L2_GLOBAL_CTRL0_LIMIT_PFC_EN_MASK (0x3 << RTL8373_MAC_L2_GLOBAL_CTRL0_LIMIT_PFC_EN_OFFSET) + #define RTL8373_MAC_L2_GLOBAL_CTRL0_IOL_LEN_ERR_EN_OFFSET (11) + #define RTL8373_MAC_L2_GLOBAL_CTRL0_IOL_LEN_ERR_EN_MASK (0x1 << RTL8373_MAC_L2_GLOBAL_CTRL0_IOL_LEN_ERR_EN_OFFSET) + #define RTL8373_MAC_L2_GLOBAL_CTRL0_IOL_MAX_LEN_EN_OFFSET (10) + #define RTL8373_MAC_L2_GLOBAL_CTRL0_IOL_MAX_LEN_EN_MASK (0x1 << RTL8373_MAC_L2_GLOBAL_CTRL0_IOL_MAX_LEN_EN_OFFSET) + #define RTL8373_MAC_L2_GLOBAL_CTRL0_LIMIT_IPG_CFG_1G_2P5G_OFFSET (5) + #define RTL8373_MAC_L2_GLOBAL_CTRL0_LIMIT_IPG_CFG_1G_2P5G_MASK (0x1F << RTL8373_MAC_L2_GLOBAL_CTRL0_LIMIT_IPG_CFG_1G_2P5G_OFFSET) + #define RTL8373_MAC_L2_GLOBAL_CTRL0_LIMIT_IPG_CFG_10M_100M_OFFSET (0) + #define RTL8373_MAC_L2_GLOBAL_CTRL0_LIMIT_IPG_CFG_10M_100M_MASK (0x1F << RTL8373_MAC_L2_GLOBAL_CTRL0_LIMIT_IPG_CFG_10M_100M_OFFSET) + +#define RTL8373_MAC_L2_GLOBAL_CTRL1_ADDR (0x5FD8) + #define RTL8373_MAC_L2_GLOBAL_CTRL1_LINKINTRP_TX_EN_8_0_OFFSET (7) + #define RTL8373_MAC_L2_GLOBAL_CTRL1_LINKINTRP_TX_EN_8_0_MASK (0x1FF << RTL8373_MAC_L2_GLOBAL_CTRL1_LINKINTRP_TX_EN_8_0_OFFSET) + #define RTL8373_MAC_L2_GLOBAL_CTRL1_CFG_RX_RXDV_CNT_OFFSET (0) + #define RTL8373_MAC_L2_GLOBAL_CTRL1_CFG_RX_RXDV_CNT_MASK (0x7F << RTL8373_MAC_L2_GLOBAL_CTRL1_CFG_RX_RXDV_CNT_OFFSET) + +#define RTL8373_MAC_L2_PORT_CTRL_ADDR(port) (0x1238 + (((port) << 8))) /* port: 0-9 */ + #define RTL8373_MAC_L2_PORT_CTRL_PER_PORT_RSTB_OFFSET (11) + #define RTL8373_MAC_L2_PORT_CTRL_PER_PORT_RSTB_MASK (0x1 << RTL8373_MAC_L2_PORT_CTRL_PER_PORT_RSTB_OFFSET) + #define RTL8373_MAC_L2_PORT_CTRL_PER_PORT_RX_RSTB_OFFSET (10) + #define RTL8373_MAC_L2_PORT_CTRL_PER_PORT_RX_RSTB_MASK (0x1 << RTL8373_MAC_L2_PORT_CTRL_PER_PORT_RX_RSTB_OFFSET) + #define RTL8373_MAC_L2_PORT_CTRL_PER_PORT_TX_RSTB_OFFSET (9) + #define RTL8373_MAC_L2_PORT_CTRL_PER_PORT_TX_RSTB_MASK (0x1 << RTL8373_MAC_L2_PORT_CTRL_PER_PORT_TX_RSTB_OFFSET) + #define RTL8373_MAC_L2_PORT_CTRL_CLOCK_SWITCH_OFFSET (8) + #define RTL8373_MAC_L2_PORT_CTRL_CLOCK_SWITCH_MASK (0x1 << RTL8373_MAC_L2_PORT_CTRL_CLOCK_SWITCH_OFFSET) + #define RTL8373_MAC_L2_PORT_CTRL_CFG_PORT_L_LPBK_OFFSET (7) + #define RTL8373_MAC_L2_PORT_CTRL_CFG_PORT_L_LPBK_MASK (0x1 << RTL8373_MAC_L2_PORT_CTRL_CFG_PORT_L_LPBK_OFFSET) + #define RTL8373_MAC_L2_PORT_CTRL_ALWAYS_TX_CRC_RC_EN_OFFSET (6) + #define RTL8373_MAC_L2_PORT_CTRL_ALWAYS_TX_CRC_RC_EN_MASK (0x1 << RTL8373_MAC_L2_PORT_CTRL_ALWAYS_TX_CRC_RC_EN_OFFSET) + #define RTL8373_MAC_L2_PORT_CTRL_PADDING_UND_SIZE_EN_OFFSET (5) + #define RTL8373_MAC_L2_PORT_CTRL_PADDING_UND_SIZE_EN_MASK (0x1 << RTL8373_MAC_L2_PORT_CTRL_PADDING_UND_SIZE_EN_OFFSET) + #define RTL8373_MAC_L2_PORT_CTRL_RX_CHK_CRC_EN_OFFSET (4) + #define RTL8373_MAC_L2_PORT_CTRL_RX_CHK_CRC_EN_MASK (0x1 << RTL8373_MAC_L2_PORT_CTRL_RX_CHK_CRC_EN_OFFSET) + #define RTL8373_MAC_L2_PORT_CTRL_PASS_ALL_MODE_EN_OFFSET (3) + #define RTL8373_MAC_L2_PORT_CTRL_PASS_ALL_MODE_EN_MASK (0x1 << RTL8373_MAC_L2_PORT_CTRL_PASS_ALL_MODE_EN_OFFSET) + #define RTL8373_MAC_L2_PORT_CTRL_BYP_TX_CRC_OFFSET (2) + #define RTL8373_MAC_L2_PORT_CTRL_BYP_TX_CRC_MASK (0x1 << RTL8373_MAC_L2_PORT_CTRL_BYP_TX_CRC_OFFSET) + #define RTL8373_MAC_L2_PORT_CTRL_TX_EN_OFFSET (1) + #define RTL8373_MAC_L2_PORT_CTRL_TX_EN_MASK (0x1 << RTL8373_MAC_L2_PORT_CTRL_TX_EN_OFFSET) + #define RTL8373_MAC_L2_PORT_CTRL_RX_EN_OFFSET (0) + #define RTL8373_MAC_L2_PORT_CTRL_RX_EN_MASK (0x1 << RTL8373_MAC_L2_PORT_CTRL_RX_EN_OFFSET) + +#define RTL8373_MAC_MACSEC_IPG_CFG_ADDR(port) (0x123C + (((port) << 8))) /* port: 0-9 */ + #define RTL8373_MAC_MACSEC_IPG_CFG_MACSEC_IPG_LENGTH_OFFSET (2) + #define RTL8373_MAC_MACSEC_IPG_CFG_MACSEC_IPG_LENGTH_MASK (0x7F << RTL8373_MAC_MACSEC_IPG_CFG_MACSEC_IPG_LENGTH_OFFSET) + #define RTL8373_MAC_MACSEC_IPG_CFG_MACSEC_IPG_MODE_OFFSET (0) + #define RTL8373_MAC_MACSEC_IPG_CFG_MACSEC_IPG_MODE_MASK (0x3 << RTL8373_MAC_MACSEC_IPG_CFG_MACSEC_IPG_MODE_OFFSET) + +#define RTL8373_MAC_MACSEC_ETH_1_0_ADDR(port) (0x1240 + (((port) << 8))) /* port: 0-9 */ + #define RTL8373_MAC_MACSEC_ETH_1_0_MACSEC_ETH_1_OFFSET (16) + #define RTL8373_MAC_MACSEC_ETH_1_0_MACSEC_ETH_1_MASK (0xFFFF << RTL8373_MAC_MACSEC_ETH_1_0_MACSEC_ETH_1_OFFSET) + #define RTL8373_MAC_MACSEC_ETH_1_0_MACSEC_ETH_0_OFFSET (0) + #define RTL8373_MAC_MACSEC_ETH_1_0_MACSEC_ETH_0_MASK (0xFFFF << RTL8373_MAC_MACSEC_ETH_1_0_MACSEC_ETH_0_OFFSET) + +#define RTL8373_MAC_MACSEC_ETH_3_2_ADDR(port) (0x1244 + (((port) << 8))) /* port: 0-9 */ + #define RTL8373_MAC_MACSEC_ETH_3_2_MACSEC_ETH_3_OFFSET (16) + #define RTL8373_MAC_MACSEC_ETH_3_2_MACSEC_ETH_3_MASK (0xFFFF << RTL8373_MAC_MACSEC_ETH_3_2_MACSEC_ETH_3_OFFSET) + #define RTL8373_MAC_MACSEC_ETH_3_2_MACSEC_ETH_2_OFFSET (0) + #define RTL8373_MAC_MACSEC_ETH_3_2_MACSEC_ETH_2_MASK (0xFFFF << RTL8373_MAC_MACSEC_ETH_3_2_MACSEC_ETH_2_OFFSET) + +#define RTL8373_MAC_MACSEC_ETH_5_4_ADDR(port) (0x1248 + (((port) << 8))) /* port: 0-9 */ + #define RTL8373_MAC_MACSEC_ETH_5_4_MACSEC_ETH_5_OFFSET (16) + #define RTL8373_MAC_MACSEC_ETH_5_4_MACSEC_ETH_5_MASK (0xFFFF << RTL8373_MAC_MACSEC_ETH_5_4_MACSEC_ETH_5_OFFSET) + #define RTL8373_MAC_MACSEC_ETH_5_4_MACSEC_ETH_4_OFFSET (0) + #define RTL8373_MAC_MACSEC_ETH_5_4_MACSEC_ETH_4_MASK (0xFFFF << RTL8373_MAC_MACSEC_ETH_5_4_MACSEC_ETH_4_OFFSET) + +#define RTL8373_MAC_MACSEC_ETH_7_6_ADDR(port) (0x124C + (((port) << 8))) /* port: 0-9 */ + #define RTL8373_MAC_MACSEC_ETH_7_6_MACSEC_ETH_7_OFFSET (16) + #define RTL8373_MAC_MACSEC_ETH_7_6_MACSEC_ETH_7_MASK (0xFFFF << RTL8373_MAC_MACSEC_ETH_7_6_MACSEC_ETH_7_OFFSET) + #define RTL8373_MAC_MACSEC_ETH_7_6_MACSEC_ETH_6_OFFSET (0) + #define RTL8373_MAC_MACSEC_ETH_7_6_MACSEC_ETH_6_MASK (0xFFFF << RTL8373_MAC_MACSEC_ETH_7_6_MACSEC_ETH_6_OFFSET) + +#define RTL8373_MAC_L2_PADDING_SEL_ADDR (0x5FDC) + #define RTL8373_MAC_L2_PADDING_SEL_PADDING_SEL_OFFSET (0) + #define RTL8373_MAC_L2_PADDING_SEL_PADDING_SEL_MASK (0xFF << RTL8373_MAC_L2_PADDING_SEL_PADDING_SEL_OFFSET) + +#define RTL8373_MAC_L2_ADDR_CTRL_ADDR (0x5FE0) + #define RTL8373_MAC_L2_ADDR_CTRL_SW_MAC_ADDR_47_32_OFFSET (0) + #define RTL8373_MAC_L2_ADDR_CTRL_SW_MAC_ADDR_47_32_MASK (0xFFFF << RTL8373_MAC_L2_ADDR_CTRL_SW_MAC_ADDR_47_32_OFFSET) + #define RTL8373_MAC_L2_ADDR_CTRL_SW_MAC_ADDR_31_0_OFFSET (32) + #define RTL8373_MAC_L2_ADDR_CTRL_SW_MAC_ADDR_31_0_MASK (0xFFFFFFFF << RTL8373_MAC_L2_ADDR_CTRL_SW_MAC_ADDR_31_0_OFFSET) + +#define RTL8373_MAC_L2_PORT_MAX_LEN_CTRL_ADDR(port) (0x1250 + (((port) << 8))) /* port: 0-9 */ + #define RTL8373_MAC_L2_PORT_MAX_LEN_CTRL_MAX_LEN_TAG_INC_OFFSET (28) + #define RTL8373_MAC_L2_PORT_MAX_LEN_CTRL_MAX_LEN_TAG_INC_MASK (0x1 << RTL8373_MAC_L2_PORT_MAX_LEN_CTRL_MAX_LEN_TAG_INC_OFFSET) + #define RTL8373_MAC_L2_PORT_MAX_LEN_CTRL_MAX_LEN_1G_2P5G_5G_10G_SEL_OFFSET (14) + #define RTL8373_MAC_L2_PORT_MAX_LEN_CTRL_MAX_LEN_1G_2P5G_5G_10G_SEL_MASK (0x3FFF << RTL8373_MAC_L2_PORT_MAX_LEN_CTRL_MAX_LEN_1G_2P5G_5G_10G_SEL_OFFSET) + #define RTL8373_MAC_L2_PORT_MAX_LEN_CTRL_MAX_LEN_100M_10M_SEL_OFFSET (0) + #define RTL8373_MAC_L2_PORT_MAX_LEN_CTRL_MAX_LEN_100M_10M_SEL_MASK (0x3FFF << RTL8373_MAC_L2_PORT_MAX_LEN_CTRL_MAX_LEN_100M_10M_SEL_OFFSET) + +#define RTL8373_MAC_L2_TGPORT_PRMB_DBG0_ADDR(port) (0x1254 + (((port) << 8))) /* port: 0-9 */ + #define RTL8373_MAC_L2_TGPORT_PRMB_DBG0_CFG_PRMB_6BYTE_MODE_OFFSET (30) + #define RTL8373_MAC_L2_TGPORT_PRMB_DBG0_CFG_PRMB_6BYTE_MODE_MASK (0x1 << RTL8373_MAC_L2_TGPORT_PRMB_DBG0_CFG_PRMB_6BYTE_MODE_OFFSET) + #define RTL8373_MAC_L2_TGPORT_PRMB_DBG0_CFG_PRMB_RCVY_EN_OFFSET (29) + #define RTL8373_MAC_L2_TGPORT_PRMB_DBG0_CFG_PRMB_RCVY_EN_MASK (0x1 << RTL8373_MAC_L2_TGPORT_PRMB_DBG0_CFG_PRMB_RCVY_EN_OFFSET) + #define RTL8373_MAC_L2_TGPORT_PRMB_DBG0_CFG_PN_FRAG_FLT_OFFSET (28) + #define RTL8373_MAC_L2_TGPORT_PRMB_DBG0_CFG_PN_FRAG_FLT_MASK (0x1 << RTL8373_MAC_L2_TGPORT_PRMB_DBG0_CFG_PN_FRAG_FLT_OFFSET) + #define RTL8373_MAC_L2_TGPORT_PRMB_DBG0_CFG_PN_CUR_PRMB_OFFSET (24) + #define RTL8373_MAC_L2_TGPORT_PRMB_DBG0_CFG_PN_CUR_PRMB_MASK (0xF << RTL8373_MAC_L2_TGPORT_PRMB_DBG0_CFG_PN_CUR_PRMB_OFFSET) + #define RTL8373_MAC_L2_TGPORT_PRMB_DBG0_CFG_PN_MAX_PRMB_OFFSET (20) + #define RTL8373_MAC_L2_TGPORT_PRMB_DBG0_CFG_PN_MAX_PRMB_MASK (0xF << RTL8373_MAC_L2_TGPORT_PRMB_DBG0_CFG_PN_MAX_PRMB_OFFSET) + #define RTL8373_MAC_L2_TGPORT_PRMB_DBG0_CFG_PN_MIN_PRMB_OFFSET (16) + #define RTL8373_MAC_L2_TGPORT_PRMB_DBG0_CFG_PN_MIN_PRMB_MASK (0xF << RTL8373_MAC_L2_TGPORT_PRMB_DBG0_CFG_PN_MIN_PRMB_OFFSET) + #define RTL8373_MAC_L2_TGPORT_PRMB_DBG0_CFG_PN_DBG_INFO_OFF_OFFSET (15) + #define RTL8373_MAC_L2_TGPORT_PRMB_DBG0_CFG_PN_DBG_INFO_OFF_MASK (0x1 << RTL8373_MAC_L2_TGPORT_PRMB_DBG0_CFG_PN_DBG_INFO_OFF_OFFSET) + #define RTL8373_MAC_L2_TGPORT_PRMB_DBG0_CFG_PN_CUR_IPG_OFFSET (10) + #define RTL8373_MAC_L2_TGPORT_PRMB_DBG0_CFG_PN_CUR_IPG_MASK (0x1F << RTL8373_MAC_L2_TGPORT_PRMB_DBG0_CFG_PN_CUR_IPG_OFFSET) + #define RTL8373_MAC_L2_TGPORT_PRMB_DBG0_CFG_PN_MAX_IPG_OFFSET (5) + #define RTL8373_MAC_L2_TGPORT_PRMB_DBG0_CFG_PN_MAX_IPG_MASK (0x1F << RTL8373_MAC_L2_TGPORT_PRMB_DBG0_CFG_PN_MAX_IPG_OFFSET) + #define RTL8373_MAC_L2_TGPORT_PRMB_DBG0_CFG_PN_MIN_IPG_OFFSET (0) + #define RTL8373_MAC_L2_TGPORT_PRMB_DBG0_CFG_PN_MIN_IPG_MASK (0x1F << RTL8373_MAC_L2_TGPORT_PRMB_DBG0_CFG_PN_MIN_IPG_OFFSET) + +#define RTL8373_MAC_L2_TGPORT_PRMB_DBG1_ADDR(port) (0x1258 + (((port) << 8))) /* port: 0-9 */ + #define RTL8373_MAC_L2_TGPORT_PRMB_DBG1_TG_SFD_FB_DIS_TX_OFFSET (14) + #define RTL8373_MAC_L2_TGPORT_PRMB_DBG1_TG_SFD_FB_DIS_TX_MASK (0x1 << RTL8373_MAC_L2_TGPORT_PRMB_DBG1_TG_SFD_FB_DIS_TX_OFFSET) + #define RTL8373_MAC_L2_TGPORT_PRMB_DBG1_TG_SFD_FB_DIS_RX_OFFSET (13) + #define RTL8373_MAC_L2_TGPORT_PRMB_DBG1_TG_SFD_FB_DIS_RX_MASK (0x1 << RTL8373_MAC_L2_TGPORT_PRMB_DBG1_TG_SFD_FB_DIS_RX_OFFSET) + #define RTL8373_MAC_L2_TGPORT_PRMB_DBG1_PRMB_RCVY_OVTHR_MON_OFFSET (12) + #define RTL8373_MAC_L2_TGPORT_PRMB_DBG1_PRMB_RCVY_OVTHR_MON_MASK (0x1 << RTL8373_MAC_L2_TGPORT_PRMB_DBG1_PRMB_RCVY_OVTHR_MON_OFFSET) + #define RTL8373_MAC_L2_TGPORT_PRMB_DBG1_CFG_PN_CUR_THR_OFFSET (6) + #define RTL8373_MAC_L2_TGPORT_PRMB_DBG1_CFG_PN_CUR_THR_MASK (0x3F << RTL8373_MAC_L2_TGPORT_PRMB_DBG1_CFG_PN_CUR_THR_OFFSET) + #define RTL8373_MAC_L2_TGPORT_PRMB_DBG1_CFG_PN_MAX_THR_OFFSET (0) + #define RTL8373_MAC_L2_TGPORT_PRMB_DBG1_CFG_PN_MAX_THR_MASK (0x3F << RTL8373_MAC_L2_TGPORT_PRMB_DBG1_CFG_PN_MAX_THR_OFFSET) + +#define RTL8373_PHY_CFG_8224_ADDR (0x444) + #define RTL8373_PHY_CFG_8224_SMI_DGL_EN_8224_OFFSET (5) + #define RTL8373_PHY_CFG_8224_SMI_DGL_EN_8224_MASK (0x1 << RTL8373_PHY_CFG_8224_SMI_DGL_EN_8224_OFFSET) + #define RTL8373_PHY_CFG_8224_BASE_PHY_ADDR_8224_OFFSET (0) + #define RTL8373_PHY_CFG_8224_BASE_PHY_ADDR_8224_MASK (0x1F << RTL8373_PHY_CFG_8224_BASE_PHY_ADDR_8224_OFFSET) + +#define RTL8373_MDX_CTRL_8224_ADDR (0x448) + #define RTL8373_MDX_CTRL_8224_SLV_CLK_EDGE_SEL_OFFSET (8) + #define RTL8373_MDX_CTRL_8224_SLV_CLK_EDGE_SEL_MASK (0x1 << RTL8373_MDX_CTRL_8224_SLV_CLK_EDGE_SEL_OFFSET) + #define RTL8373_MDX_CTRL_8224_CFG_PRMB_SUPP_8224_OFFSET (7) + #define RTL8373_MDX_CTRL_8224_CFG_PRMB_SUPP_8224_MASK (0x1 << RTL8373_MDX_CTRL_8224_CFG_PRMB_SUPP_8224_OFFSET) + #define RTL8373_MDX_CTRL_8224_CFG_TA_CHK_EN_8224_OFFSET (6) + #define RTL8373_MDX_CTRL_8224_CFG_TA_CHK_EN_8224_MASK (0x1 << RTL8373_MDX_CTRL_8224_CFG_TA_CHK_EN_8224_OFFSET) + #define RTL8373_MDX_CTRL_8224_CFG_MULTI_GPHY_MDIO_DLY_8224_OFFSET (4) + #define RTL8373_MDX_CTRL_8224_CFG_MULTI_GPHY_MDIO_DLY_8224_MASK (0x3 << RTL8373_MDX_CTRL_8224_CFG_MULTI_GPHY_MDIO_DLY_8224_OFFSET) + #define RTL8373_MDX_CTRL_8224_CFG_TOP_MDIO_DLY_8224_OFFSET (2) + #define RTL8373_MDX_CTRL_8224_CFG_TOP_MDIO_DLY_8224_MASK (0x3 << RTL8373_MDX_CTRL_8224_CFG_TOP_MDIO_DLY_8224_OFFSET) + #define RTL8373_MDX_CTRL_8224_CFG_MULTI_GPHY_MDC_DEGLITCH_EN_8224_OFFSET (1) + #define RTL8373_MDX_CTRL_8224_CFG_MULTI_GPHY_MDC_DEGLITCH_EN_8224_MASK (0x1 << RTL8373_MDX_CTRL_8224_CFG_MULTI_GPHY_MDC_DEGLITCH_EN_8224_OFFSET) + #define RTL8373_MDX_CTRL_8224_CFG_TOP_MDC_DEGLITCH_EN_8224_OFFSET (0) + #define RTL8373_MDX_CTRL_8224_CFG_TOP_MDC_DEGLITCH_EN_8224_MASK (0x1 << RTL8373_MDX_CTRL_8224_CFG_TOP_MDC_DEGLITCH_EN_8224_OFFSET) + +#define RTL8373_INT_PHY_OCP_INDR_ACC_CTRL_0_ADDR (0xBC8) + #define RTL8373_INT_PHY_OCP_INDR_ACC_CTRL_0_INT_PHY_OCP_INDACC_ADDR_OFFSET (16) + #define RTL8373_INT_PHY_OCP_INDR_ACC_CTRL_0_INT_PHY_OCP_INDACC_ADDR_MASK (0xFFFF << RTL8373_INT_PHY_OCP_INDR_ACC_CTRL_0_INT_PHY_OCP_INDACC_ADDR_OFFSET) + #define RTL8373_INT_PHY_OCP_INDR_ACC_CTRL_0_INT_PHY_OCP_INDACC_PHYADR_OFFSET (4) + #define RTL8373_INT_PHY_OCP_INDR_ACC_CTRL_0_INT_PHY_OCP_INDACC_PHYADR_MASK (0x1F << RTL8373_INT_PHY_OCP_INDR_ACC_CTRL_0_INT_PHY_OCP_INDACC_PHYADR_OFFSET) + #define RTL8373_INT_PHY_OCP_INDR_ACC_CTRL_0_INT_PHY_OCP_INDACC_FAIL_OFFSET (2) + #define RTL8373_INT_PHY_OCP_INDR_ACC_CTRL_0_INT_PHY_OCP_INDACC_FAIL_MASK (0x1 << RTL8373_INT_PHY_OCP_INDR_ACC_CTRL_0_INT_PHY_OCP_INDACC_FAIL_OFFSET) + #define RTL8373_INT_PHY_OCP_INDR_ACC_CTRL_0_INT_PHY_OCP_INDACC_RW_OFFSET (1) + #define RTL8373_INT_PHY_OCP_INDR_ACC_CTRL_0_INT_PHY_OCP_INDACC_RW_MASK (0x1 << RTL8373_INT_PHY_OCP_INDR_ACC_CTRL_0_INT_PHY_OCP_INDACC_RW_OFFSET) + #define RTL8373_INT_PHY_OCP_INDR_ACC_CTRL_0_INT_PHY_OCP_INDACC_CMD_OFFSET (0) + #define RTL8373_INT_PHY_OCP_INDR_ACC_CTRL_0_INT_PHY_OCP_INDACC_CMD_MASK (0x1 << RTL8373_INT_PHY_OCP_INDR_ACC_CTRL_0_INT_PHY_OCP_INDACC_CMD_OFFSET) + +#define RTL8373_INT_PHY_OCP_INDR_ACC_CTRL_1_ADDR (0xBCC) + #define RTL8373_INT_PHY_OCP_INDR_ACC_CTRL_1_INT_PHY_OCP_INDACC_RDDATA_OFFSET (0) + #define RTL8373_INT_PHY_OCP_INDR_ACC_CTRL_1_INT_PHY_OCP_INDACC_RDDATA_MASK (0xFFFF << RTL8373_INT_PHY_OCP_INDR_ACC_CTRL_1_INT_PHY_OCP_INDACC_RDDATA_OFFSET) + +#define RTL8373_INT_PHY_OCP_INDR_ACC_CTRL_2_ADDR (0xBD0) + #define RTL8373_INT_PHY_OCP_INDR_ACC_CTRL_2_INT_PHY_OCP_INDACC_WRDATA_OFFSET (0) + #define RTL8373_INT_PHY_OCP_INDR_ACC_CTRL_2_INT_PHY_OCP_INDACC_WRDATA_MASK (0xFFFF << RTL8373_INT_PHY_OCP_INDR_ACC_CTRL_2_INT_PHY_OCP_INDACC_WRDATA_OFFSET) + +#define RTL8373_MAC_PFC_FORCE_FC_ADDR (0x5FE8) + #define RTL8373_MAC_PFC_FORCE_FC_MAC3_PFC_FRC_FC_EN_OFFSET (5) + #define RTL8373_MAC_PFC_FORCE_FC_MAC3_PFC_FRC_FC_EN_MASK (0x1 << RTL8373_MAC_PFC_FORCE_FC_MAC3_PFC_FRC_FC_EN_OFFSET) + #define RTL8373_MAC_PFC_FORCE_FC_MAC3_PFC_FRC_FC_RX_OFFSET (4) + #define RTL8373_MAC_PFC_FORCE_FC_MAC3_PFC_FRC_FC_RX_MASK (0x1 << RTL8373_MAC_PFC_FORCE_FC_MAC3_PFC_FRC_FC_RX_OFFSET) + #define RTL8373_MAC_PFC_FORCE_FC_MAC3_PFC_FRC_FC_TX_OFFSET (3) + #define RTL8373_MAC_PFC_FORCE_FC_MAC3_PFC_FRC_FC_TX_MASK (0x1 << RTL8373_MAC_PFC_FORCE_FC_MAC3_PFC_FRC_FC_TX_OFFSET) + #define RTL8373_MAC_PFC_FORCE_FC_MAC8_PFC_FRC_FC_EN_OFFSET (2) + #define RTL8373_MAC_PFC_FORCE_FC_MAC8_PFC_FRC_FC_EN_MASK (0x1 << RTL8373_MAC_PFC_FORCE_FC_MAC8_PFC_FRC_FC_EN_OFFSET) + #define RTL8373_MAC_PFC_FORCE_FC_MAC8_PFC_FRC_FC_RX_OFFSET (1) + #define RTL8373_MAC_PFC_FORCE_FC_MAC8_PFC_FRC_FC_RX_MASK (0x1 << RTL8373_MAC_PFC_FORCE_FC_MAC8_PFC_FRC_FC_RX_OFFSET) + #define RTL8373_MAC_PFC_FORCE_FC_MAC8_PFC_FRC_FC_TX_OFFSET (0) + #define RTL8373_MAC_PFC_FORCE_FC_MAC8_PFC_FRC_FC_TX_MASK (0x1 << RTL8373_MAC_PFC_FORCE_FC_MAC8_PFC_FRC_FC_TX_OFFSET) + +#define RTL8373_MAC_TXFIFO_FULTH_CTRL_0_ADDR (0x1020) + #define RTL8373_MAC_TXFIFO_FULTH_CTRL_0_MAC0_TXFIFO_THR_CTRL_OFFSET (16) + #define RTL8373_MAC_TXFIFO_FULTH_CTRL_0_MAC0_TXFIFO_THR_CTRL_MASK (0xFFFF << RTL8373_MAC_TXFIFO_FULTH_CTRL_0_MAC0_TXFIFO_THR_CTRL_OFFSET) + #define RTL8373_MAC_TXFIFO_FULTH_CTRL_0_MAC1_TXFIFO_THR_CTRL_OFFSET (0) + #define RTL8373_MAC_TXFIFO_FULTH_CTRL_0_MAC1_TXFIFO_THR_CTRL_MASK (0xFFFF << RTL8373_MAC_TXFIFO_FULTH_CTRL_0_MAC1_TXFIFO_THR_CTRL_OFFSET) + +#define RTL8373_MAC_TXFIFO_FULTH_CTRL_1_ADDR (0x1024) + #define RTL8373_MAC_TXFIFO_FULTH_CTRL_1_MAC2_TXFIFO_THR_CTRL_OFFSET (16) + #define RTL8373_MAC_TXFIFO_FULTH_CTRL_1_MAC2_TXFIFO_THR_CTRL_MASK (0xFFFF << RTL8373_MAC_TXFIFO_FULTH_CTRL_1_MAC2_TXFIFO_THR_CTRL_OFFSET) + #define RTL8373_MAC_TXFIFO_FULTH_CTRL_1_MAC3_TXFIFO_THR_CTRL_1G_OFFSET (0) + #define RTL8373_MAC_TXFIFO_FULTH_CTRL_1_MAC3_TXFIFO_THR_CTRL_1G_MASK (0xFFFF << RTL8373_MAC_TXFIFO_FULTH_CTRL_1_MAC3_TXFIFO_THR_CTRL_1G_OFFSET) + +#define RTL8373_MAC_TXFIFO_FULTH_CTRL_2_ADDR (0x1028) + #define RTL8373_MAC_TXFIFO_FULTH_CTRL_2_MAC3_TXFIFO_THR_CTRL_TG_OFFSET (16) + #define RTL8373_MAC_TXFIFO_FULTH_CTRL_2_MAC3_TXFIFO_THR_CTRL_TG_MASK (0xFFFF << RTL8373_MAC_TXFIFO_FULTH_CTRL_2_MAC3_TXFIFO_THR_CTRL_TG_OFFSET) + #define RTL8373_MAC_TXFIFO_FULTH_CTRL_2_MAC4_TXFIFO_THR_CTRL_OFFSET (0) + #define RTL8373_MAC_TXFIFO_FULTH_CTRL_2_MAC4_TXFIFO_THR_CTRL_MASK (0xFFFF << RTL8373_MAC_TXFIFO_FULTH_CTRL_2_MAC4_TXFIFO_THR_CTRL_OFFSET) + +#define RTL8373_MAC_TXFIFO_FULTH_CTRL_3_ADDR (0x102C) + #define RTL8373_MAC_TXFIFO_FULTH_CTRL_3_MAC5_TXFIFO_THR_CTRL_OFFSET (16) + #define RTL8373_MAC_TXFIFO_FULTH_CTRL_3_MAC5_TXFIFO_THR_CTRL_MASK (0xFFFF << RTL8373_MAC_TXFIFO_FULTH_CTRL_3_MAC5_TXFIFO_THR_CTRL_OFFSET) + #define RTL8373_MAC_TXFIFO_FULTH_CTRL_3_MAC6_TXFIFO_THR_CTRL_OFFSET (0) + #define RTL8373_MAC_TXFIFO_FULTH_CTRL_3_MAC6_TXFIFO_THR_CTRL_MASK (0xFFFF << RTL8373_MAC_TXFIFO_FULTH_CTRL_3_MAC6_TXFIFO_THR_CTRL_OFFSET) + +#define RTL8373_MAC_TXFIFO_FULTH_CTRL_4_ADDR (0x1030) + #define RTL8373_MAC_TXFIFO_FULTH_CTRL_4_MAC7_TXFIFO_THR_CTRL_OFFSET (16) + #define RTL8373_MAC_TXFIFO_FULTH_CTRL_4_MAC7_TXFIFO_THR_CTRL_MASK (0xFFFF << RTL8373_MAC_TXFIFO_FULTH_CTRL_4_MAC7_TXFIFO_THR_CTRL_OFFSET) + #define RTL8373_MAC_TXFIFO_FULTH_CTRL_4_MAC8_TXFIFO_THR_CTRL_TG_OFFSET (0) + #define RTL8373_MAC_TXFIFO_FULTH_CTRL_4_MAC8_TXFIFO_THR_CTRL_TG_MASK (0xFFFF << RTL8373_MAC_TXFIFO_FULTH_CTRL_4_MAC8_TXFIFO_THR_CTRL_TG_OFFSET) + +#define RTL8373_MAC_TXFIFO_FULTH_CTRL_5_ADDR (0x1034) + #define RTL8373_MAC_TXFIFO_FULTH_CTRL_5_MAC8_TXFIFO_THR_CTRL_1G_OFFSET (16) + #define RTL8373_MAC_TXFIFO_FULTH_CTRL_5_MAC8_TXFIFO_THR_CTRL_1G_MASK (0xFFFF << RTL8373_MAC_TXFIFO_FULTH_CTRL_5_MAC8_TXFIFO_THR_CTRL_1G_OFFSET) + #define RTL8373_MAC_TXFIFO_FULTH_CTRL_5_MAC9_TXFIFO_THR_CTRL_OFFSET (0) + #define RTL8373_MAC_TXFIFO_FULTH_CTRL_5_MAC9_TXFIFO_THR_CTRL_MASK (0xFFFF << RTL8373_MAC_TXFIFO_FULTH_CTRL_5_MAC9_TXFIFO_THR_CTRL_OFFSET) + +#define RTL8373_MACSEC_REG_GLB_SET1_PORT4_ADDR (0xC0F0) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT4_RX_GATING_OFFSET (31) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT4_RX_GATING_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT4_RX_GATING_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT4_TX_GATING_OFFSET (30) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT4_TX_GATING_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT4_TX_GATING_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT4_DBG_EN_OFFSET (29) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT4_DBG_EN_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT4_DBG_EN_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT4_DBG_SEL_OFFSET (24) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT4_DBG_SEL_MASK (0x1F << RTL8373_MACSEC_REG_GLB_SET1_PORT4_DBG_SEL_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT4_DBG_SPD_SEL_OFFSET (23) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT4_DBG_SPD_SEL_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT4_DBG_SPD_SEL_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT4_RX_G_IOSAMEPMB_OFFSET (22) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT4_RX_G_IOSAMEPMB_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT4_RX_G_IOSAMEPMB_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT4_TX_G_IOSAMEPMB_OFFSET (21) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT4_TX_G_IOSAMEPMB_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT4_TX_G_IOSAMEPMB_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT4_MIBCNT_MODE_OFFSET (20) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT4_MIBCNT_MODE_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT4_MIBCNT_MODE_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT4_RX_XGDIC_EN_OFFSET (18) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT4_RX_XGDIC_EN_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT4_RX_XGDIC_EN_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT4_TX_XGDIC_EN_OFFSET (17) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT4_TX_XGDIC_EN_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT4_TX_XGDIC_EN_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT4_MIBCNT_SWRST_N_OFFSET (16) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT4_MIBCNT_SWRST_N_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT4_MIBCNT_SWRST_N_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT4_PTPBYPASS_EN_OFFSET (14) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT4_PTPBYPASS_EN_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT4_PTPBYPASS_EN_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT4_SYSLPBK_EN_OFFSET (13) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT4_SYSLPBK_EN_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT4_SYSLPBK_EN_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT4_PHY2MAC_EN_OFFSET (12) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT4_PHY2MAC_EN_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT4_PHY2MAC_EN_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT4_RX_IPRST_N_OFFSET (11) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT4_RX_IPRST_N_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT4_RX_IPRST_N_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT4_RX_IPBYPASS_EN_OFFSET (10) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT4_RX_IPBYPASS_EN_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT4_RX_IPBYPASS_EN_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT4_RX_MACSECBYPASS_EN_OFFSET (9) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT4_RX_MACSECBYPASS_EN_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT4_RX_MACSECBYPASS_EN_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT4_RX_SWRST_EN_OFFSET (8) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT4_RX_SWRST_EN_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT4_RX_SWRST_EN_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT4_LINELPBK_EN_OFFSET (5) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT4_LINELPBK_EN_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT4_LINELPBK_EN_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT4_MAC2PHY_EN_OFFSET (4) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT4_MAC2PHY_EN_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT4_MAC2PHY_EN_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT4_TX_IPRST_N_OFFSET (3) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT4_TX_IPRST_N_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT4_TX_IPRST_N_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT4_TX_IPBYPASS_EN_OFFSET (2) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT4_TX_IPBYPASS_EN_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT4_TX_IPBYPASS_EN_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT4_TX_MACSECBYPASS_EN_OFFSET (1) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT4_TX_MACSECBYPASS_EN_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT4_TX_MACSECBYPASS_EN_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT4_TX_SWRST_EN_OFFSET (0) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT4_TX_SWRST_EN_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT4_TX_SWRST_EN_OFFSET) + +#define RTL8373_MACSEC_REG_GLB_IMR_PORT4_ADDR (0xC0F4) + #define RTL8373_MACSEC_REG_GLB_IMR_PORT4_RX_IPILOCK_XG_IMR_OFFSET (11) + #define RTL8373_MACSEC_REG_GLB_IMR_PORT4_RX_IPILOCK_XG_IMR_MASK (0x1 << RTL8373_MACSEC_REG_GLB_IMR_PORT4_RX_IPILOCK_XG_IMR_OFFSET) + #define RTL8373_MACSEC_REG_GLB_IMR_PORT4_RX_IPILOCK_IMR_OFFSET (10) + #define RTL8373_MACSEC_REG_GLB_IMR_PORT4_RX_IPILOCK_IMR_MASK (0x1 << RTL8373_MACSEC_REG_GLB_IMR_PORT4_RX_IPILOCK_IMR_OFFSET) + #define RTL8373_MACSEC_REG_GLB_IMR_PORT4_RX_IPISECFAIL_IMR_OFFSET (9) + #define RTL8373_MACSEC_REG_GLB_IMR_PORT4_RX_IPISECFAIL_IMR_MASK (0x1 << RTL8373_MACSEC_REG_GLB_IMR_PORT4_RX_IPISECFAIL_IMR_OFFSET) + #define RTL8373_MACSEC_REG_GLB_IMR_PORT4_RX_IPI_GLB_IMR_OFFSET (8) + #define RTL8373_MACSEC_REG_GLB_IMR_PORT4_RX_IPI_GLB_IMR_MASK (0x1 << RTL8373_MACSEC_REG_GLB_IMR_PORT4_RX_IPI_GLB_IMR_OFFSET) + #define RTL8373_MACSEC_REG_GLB_IMR_PORT4_TX_IPELOCK_XG_IMR_OFFSET (3) + #define RTL8373_MACSEC_REG_GLB_IMR_PORT4_TX_IPELOCK_XG_IMR_MASK (0x1 << RTL8373_MACSEC_REG_GLB_IMR_PORT4_TX_IPELOCK_XG_IMR_OFFSET) + #define RTL8373_MACSEC_REG_GLB_IMR_PORT4_TX_IPELOCK_IMR_OFFSET (2) + #define RTL8373_MACSEC_REG_GLB_IMR_PORT4_TX_IPELOCK_IMR_MASK (0x1 << RTL8373_MACSEC_REG_GLB_IMR_PORT4_TX_IPELOCK_IMR_OFFSET) + #define RTL8373_MACSEC_REG_GLB_IMR_PORT4_TX_IPESECFAIL_IMR_OFFSET (1) + #define RTL8373_MACSEC_REG_GLB_IMR_PORT4_TX_IPESECFAIL_IMR_MASK (0x1 << RTL8373_MACSEC_REG_GLB_IMR_PORT4_TX_IPESECFAIL_IMR_OFFSET) + #define RTL8373_MACSEC_REG_GLB_IMR_PORT4_TX_IPE_GLB_IMR_OFFSET (0) + #define RTL8373_MACSEC_REG_GLB_IMR_PORT4_TX_IPE_GLB_IMR_MASK (0x1 << RTL8373_MACSEC_REG_GLB_IMR_PORT4_TX_IPE_GLB_IMR_OFFSET) + +#define RTL8373_MACSEC_REG_GLB_ISR_PORT4_ADDR (0xC0F8) + #define RTL8373_MACSEC_REG_GLB_ISR_PORT4_RX_IPILOCK_XG_ISR_OFFSET (11) + #define RTL8373_MACSEC_REG_GLB_ISR_PORT4_RX_IPILOCK_XG_ISR_MASK (0x1 << RTL8373_MACSEC_REG_GLB_ISR_PORT4_RX_IPILOCK_XG_ISR_OFFSET) + #define RTL8373_MACSEC_REG_GLB_ISR_PORT4_RX_IPILOCK_ISR_OFFSET (10) + #define RTL8373_MACSEC_REG_GLB_ISR_PORT4_RX_IPILOCK_ISR_MASK (0x1 << RTL8373_MACSEC_REG_GLB_ISR_PORT4_RX_IPILOCK_ISR_OFFSET) + #define RTL8373_MACSEC_REG_GLB_ISR_PORT4_RX_IPISECFAIL_ISR_OFFSET (9) + #define RTL8373_MACSEC_REG_GLB_ISR_PORT4_RX_IPISECFAIL_ISR_MASK (0x1 << RTL8373_MACSEC_REG_GLB_ISR_PORT4_RX_IPISECFAIL_ISR_OFFSET) + #define RTL8373_MACSEC_REG_GLB_ISR_PORT4_RX_IPI_GLB_ISR_OFFSET (8) + #define RTL8373_MACSEC_REG_GLB_ISR_PORT4_RX_IPI_GLB_ISR_MASK (0x1 << RTL8373_MACSEC_REG_GLB_ISR_PORT4_RX_IPI_GLB_ISR_OFFSET) + #define RTL8373_MACSEC_REG_GLB_ISR_PORT4_TX_IPELOCK_XG_ISR_OFFSET (3) + #define RTL8373_MACSEC_REG_GLB_ISR_PORT4_TX_IPELOCK_XG_ISR_MASK (0x1 << RTL8373_MACSEC_REG_GLB_ISR_PORT4_TX_IPELOCK_XG_ISR_OFFSET) + #define RTL8373_MACSEC_REG_GLB_ISR_PORT4_TX_IPELOCK_ISR_OFFSET (2) + #define RTL8373_MACSEC_REG_GLB_ISR_PORT4_TX_IPELOCK_ISR_MASK (0x1 << RTL8373_MACSEC_REG_GLB_ISR_PORT4_TX_IPELOCK_ISR_OFFSET) + #define RTL8373_MACSEC_REG_GLB_ISR_PORT4_TX_IPESECFAIL_ISR_OFFSET (1) + #define RTL8373_MACSEC_REG_GLB_ISR_PORT4_TX_IPESECFAIL_ISR_MASK (0x1 << RTL8373_MACSEC_REG_GLB_ISR_PORT4_TX_IPESECFAIL_ISR_OFFSET) + #define RTL8373_MACSEC_REG_GLB_ISR_PORT4_TX_IPE_GLB_ISR_OFFSET (0) + #define RTL8373_MACSEC_REG_GLB_ISR_PORT4_TX_IPE_GLB_ISR_MASK (0x1 << RTL8373_MACSEC_REG_GLB_ISR_PORT4_TX_IPE_GLB_ISR_OFFSET) + +#define RTL8373_UNUSED_000C_PORT4_ADDR (0xC0FC) + #define RTL8373_UNUSED_000C_PORT4_UNUSED_000C_PORT4_OFFSET (0) + #define RTL8373_UNUSED_000C_PORT4_UNUSED_000C_PORT4_MASK (0xFFFFFFFF << RTL8373_UNUSED_000C_PORT4_UNUSED_000C_PORT4_OFFSET) + +#define RTL8373_MACSEC_PM_CTRL_PORT4_ADDR (0xC100) + #define RTL8373_MACSEC_PM_CTRL_PORT4_MACSEC_RX_ICG_EN_OFFSET (1) + #define RTL8373_MACSEC_PM_CTRL_PORT4_MACSEC_RX_ICG_EN_MASK (0x1 << RTL8373_MACSEC_PM_CTRL_PORT4_MACSEC_RX_ICG_EN_OFFSET) + #define RTL8373_MACSEC_PM_CTRL_PORT4_MACSEC_TX_ICG_EN_OFFSET (0) + #define RTL8373_MACSEC_PM_CTRL_PORT4_MACSEC_TX_ICG_EN_MASK (0x1 << RTL8373_MACSEC_PM_CTRL_PORT4_MACSEC_TX_ICG_EN_OFFSET) + +#define RTL8373_MACSEC_REG_GLB_MASK_PORT4_ADDR (0xC104) + #define RTL8373_MACSEC_REG_GLB_MASK_PORT4_RX_MTU_OFFSET (24) + #define RTL8373_MACSEC_REG_GLB_MASK_PORT4_RX_MTU_MASK (0x3F << RTL8373_MACSEC_REG_GLB_MASK_PORT4_RX_MTU_OFFSET) + #define RTL8373_MACSEC_REG_GLB_MASK_PORT4_TX_MTU_OFFSET (16) + #define RTL8373_MACSEC_REG_GLB_MASK_PORT4_TX_MTU_MASK (0x3F << RTL8373_MACSEC_REG_GLB_MASK_PORT4_TX_MTU_OFFSET) + #define RTL8373_MACSEC_REG_GLB_MASK_PORT4_RX_XGMASK_OFFSET (12) + #define RTL8373_MACSEC_REG_GLB_MASK_PORT4_RX_XGMASK_MASK (0x1 << RTL8373_MACSEC_REG_GLB_MASK_PORT4_RX_XGMASK_OFFSET) + #define RTL8373_MACSEC_REG_GLB_MASK_PORT4_RXDV_GMASK_OFFSET (8) + #define RTL8373_MACSEC_REG_GLB_MASK_PORT4_RXDV_GMASK_MASK (0x1 << RTL8373_MACSEC_REG_GLB_MASK_PORT4_RXDV_GMASK_OFFSET) + #define RTL8373_MACSEC_REG_GLB_MASK_PORT4_TX_XGMASK_OFFSET (4) + #define RTL8373_MACSEC_REG_GLB_MASK_PORT4_TX_XGMASK_MASK (0x1 << RTL8373_MACSEC_REG_GLB_MASK_PORT4_TX_XGMASK_OFFSET) + #define RTL8373_MACSEC_REG_GLB_MASK_PORT4_TXEN_GMASK_OFFSET (0) + #define RTL8373_MACSEC_REG_GLB_MASK_PORT4_TXEN_GMASK_MASK (0x1 << RTL8373_MACSEC_REG_GLB_MASK_PORT4_TXEN_GMASK_OFFSET) + +#define RTL8373_MACSEC_REG_GLB_SET4_PORT4_ADDR (0xC108) + #define RTL8373_MACSEC_REG_GLB_SET4_PORT4_TXMSKDELAY_VAL_OFFSET (16) + #define RTL8373_MACSEC_REG_GLB_SET4_PORT4_TXMSKDELAY_VAL_MASK (0x7FFF << RTL8373_MACSEC_REG_GLB_SET4_PORT4_TXMSKDELAY_VAL_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET4_PORT4_RXMSKDELAY_VAL_OFFSET (0) + #define RTL8373_MACSEC_REG_GLB_SET4_PORT4_RXMSKDELAY_VAL_MASK (0x7FFF << RTL8373_MACSEC_REG_GLB_SET4_PORT4_RXMSKDELAY_VAL_OFFSET) + +#define RTL8373_MACSEC_REG_IP_PROBE_PORT4_ADDR (0xC10C) + #define RTL8373_MACSEC_REG_IP_PROBE_PORT4_PROBE_SEL_AE_OFFSET (8) + #define RTL8373_MACSEC_REG_IP_PROBE_PORT4_PROBE_SEL_AE_MASK (0xFF << RTL8373_MACSEC_REG_IP_PROBE_PORT4_PROBE_SEL_AE_OFFSET) + #define RTL8373_MACSEC_REG_IP_PROBE_PORT4_PROBE_SEL_AI_OFFSET (0) + #define RTL8373_MACSEC_REG_IP_PROBE_PORT4_PROBE_SEL_AI_MASK (0xFF << RTL8373_MACSEC_REG_IP_PROBE_PORT4_PROBE_SEL_AI_OFFSET) + +#define RTL8373_UNUSED_0020_PORT4_ADDR (0xC110) + #define RTL8373_UNUSED_0020_PORT4_UNUSED_0020_PORT4_OFFSET (0) + #define RTL8373_UNUSED_0020_PORT4_UNUSED_0020_PORT4_MASK (0xFFFFFFFF << RTL8373_UNUSED_0020_PORT4_UNUSED_0020_PORT4_OFFSET) + +#define RTL8373_UNUSED_0024_PORT4_ADDR (0xC114) + #define RTL8373_UNUSED_0024_PORT4_UNUSED_0024_PORT4_OFFSET (0) + #define RTL8373_UNUSED_0024_PORT4_UNUSED_0024_PORT4_MASK (0xFFFFFFFF << RTL8373_UNUSED_0024_PORT4_UNUSED_0024_PORT4_OFFSET) + +#define RTL8373_MACSEC_MBIST_SA_CTRL_PORT4_ADDR (0xC118) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT4_BIST_MODE_MACSEC_SA_AE_OFFSET (29) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT4_BIST_MODE_MACSEC_SA_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_CTRL_PORT4_BIST_MODE_MACSEC_SA_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT4_DRF_BIST_MODE_MACSEC_SA_AE_OFFSET (28) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT4_DRF_BIST_MODE_MACSEC_SA_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_CTRL_PORT4_DRF_BIST_MODE_MACSEC_SA_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT4_BIST_RSTN_MACSEC_SA_AE_OFFSET (27) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT4_BIST_RSTN_MACSEC_SA_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_CTRL_PORT4_BIST_RSTN_MACSEC_SA_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT4_BIST_LOOP_MODE_MACSEC_SA_AE_OFFSET (26) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT4_BIST_LOOP_MODE_MACSEC_SA_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_CTRL_PORT4_BIST_LOOP_MODE_MACSEC_SA_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT4_DYN_READ_EN_MACSEC_SA_AE_OFFSET (25) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT4_DYN_READ_EN_MACSEC_SA_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_CTRL_PORT4_DYN_READ_EN_MACSEC_SA_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT4_DRF_TESS_RESUME_MACSEC_SA_AE_OFFSET (24) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT4_DRF_TESS_RESUME_MACSEC_SA_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_CTRL_PORT4_DRF_TESS_RESUME_MACSEC_SA_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT4_BIST_MODE_MACSEC_SA_AI_OFFSET (23) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT4_BIST_MODE_MACSEC_SA_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_CTRL_PORT4_BIST_MODE_MACSEC_SA_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT4_DRF_BIST_MODE_MACSEC_SA_AI_OFFSET (22) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT4_DRF_BIST_MODE_MACSEC_SA_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_CTRL_PORT4_DRF_BIST_MODE_MACSEC_SA_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT4_BIST_RSTN_MACSEC_SA_AI_OFFSET (21) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT4_BIST_RSTN_MACSEC_SA_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_CTRL_PORT4_BIST_RSTN_MACSEC_SA_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT4_BIST_LOOP_MODE_MACSEC_SA_AI_OFFSET (20) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT4_BIST_LOOP_MODE_MACSEC_SA_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_CTRL_PORT4_BIST_LOOP_MODE_MACSEC_SA_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT4_DYN_READ_EN_MACSEC_SA_AI_OFFSET (19) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT4_DYN_READ_EN_MACSEC_SA_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_CTRL_PORT4_DYN_READ_EN_MACSEC_SA_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT4_DRF_TESS_RESUME_MACSEC_SA_AI_OFFSET (18) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT4_DRF_TESS_RESUME_MACSEC_SA_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_CTRL_PORT4_DRF_TESS_RESUME_MACSEC_SA_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT4_MACSEC_SA_AE_ICG_EN_OFFSET (17) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT4_MACSEC_SA_AE_ICG_EN_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_CTRL_PORT4_MACSEC_SA_AE_ICG_EN_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT4_MACSEC_SA_AI_ICG_EN_OFFSET (16) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT4_MACSEC_SA_AI_ICG_EN_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_CTRL_PORT4_MACSEC_SA_AI_ICG_EN_OFFSET) + +#define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_ADDR (0xC11C) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_DRF_START_PAUSE_MACSEC_SA_AE_OFFSET (27) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_DRF_START_PAUSE_MACSEC_SA_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_DRF_START_PAUSE_MACSEC_SA_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_BIST_DONE_MACSEC_SA_AE_OFFSET (26) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_BIST_DONE_MACSEC_SA_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_BIST_DONE_MACSEC_SA_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_DRF_BIST_DONE_MACSEC_SA_AE_OFFSET (25) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_DRF_BIST_DONE_MACSEC_SA_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_DRF_BIST_DONE_MACSEC_SA_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_DRF_START_PAUSE_MACSEC_SA_AI_OFFSET (24) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_DRF_START_PAUSE_MACSEC_SA_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_DRF_START_PAUSE_MACSEC_SA_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_BIST_DONE_MACSEC_SA_AI_OFFSET (23) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_BIST_DONE_MACSEC_SA_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_BIST_DONE_MACSEC_SA_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_DRF_BIST_DONE_MACSEC_SA_AI_OFFSET (22) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_DRF_BIST_DONE_MACSEC_SA_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_DRF_BIST_DONE_MACSEC_SA_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_DRF_START_PAUSE_MACSEC_STAT_AE_OFFSET (21) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_DRF_START_PAUSE_MACSEC_STAT_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_DRF_START_PAUSE_MACSEC_STAT_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_BIST_DONE_MACSEC_STAT_AE_OFFSET (20) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_BIST_DONE_MACSEC_STAT_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_BIST_DONE_MACSEC_STAT_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_DRF_BIST_DONE_MACSEC_STAT_AE_OFFSET (19) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_DRF_BIST_DONE_MACSEC_STAT_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_DRF_BIST_DONE_MACSEC_STAT_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_DRF_START_PAUSE_MACSEC_STAT_AI_OFFSET (18) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_DRF_START_PAUSE_MACSEC_STAT_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_DRF_START_PAUSE_MACSEC_STAT_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_BIST_DONE_MACSEC_STAT_AI_OFFSET (17) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_BIST_DONE_MACSEC_STAT_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_BIST_DONE_MACSEC_STAT_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_DRF_BIST_DONE_MACSEC_STAT_AI_OFFSET (16) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_DRF_BIST_DONE_MACSEC_STAT_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_DRF_BIST_DONE_MACSEC_STAT_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_BIST_MODE_MACSEC_STAT_AE_OFFSET (13) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_BIST_MODE_MACSEC_STAT_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_BIST_MODE_MACSEC_STAT_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_DRF_BIST_MODE_MACSEC_STAT_AE_OFFSET (12) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_DRF_BIST_MODE_MACSEC_STAT_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_DRF_BIST_MODE_MACSEC_STAT_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_BIST_RSTN_MACSEC_STAT_AE_OFFSET (11) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_BIST_RSTN_MACSEC_STAT_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_BIST_RSTN_MACSEC_STAT_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_BIST_LOOP_MODE_MACSEC_STAT_AE_OFFSET (10) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_BIST_LOOP_MODE_MACSEC_STAT_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_BIST_LOOP_MODE_MACSEC_STAT_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_DYN_READ_EN_MACSEC_STAT_AE_OFFSET (9) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_DYN_READ_EN_MACSEC_STAT_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_DYN_READ_EN_MACSEC_STAT_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_DRF_TESS_RESUME_MACSEC_STAT_AE_OFFSET (8) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_DRF_TESS_RESUME_MACSEC_STAT_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_DRF_TESS_RESUME_MACSEC_STAT_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_BIST_MODE_MACSEC_STAT_AI_OFFSET (7) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_BIST_MODE_MACSEC_STAT_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_BIST_MODE_MACSEC_STAT_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_DRF_BIST_MODE_MACSEC_STAT_AI_OFFSET (6) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_DRF_BIST_MODE_MACSEC_STAT_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_DRF_BIST_MODE_MACSEC_STAT_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_BIST_RSTN_MACSEC_STAT_AI_OFFSET (5) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_BIST_RSTN_MACSEC_STAT_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_BIST_RSTN_MACSEC_STAT_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_BIST_LOOP_MODE_MACSEC_STAT_AI_OFFSET (4) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_BIST_LOOP_MODE_MACSEC_STAT_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_BIST_LOOP_MODE_MACSEC_STAT_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_DYN_READ_EN_MACSEC_STAT_AI_OFFSET (3) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_DYN_READ_EN_MACSEC_STAT_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_DYN_READ_EN_MACSEC_STAT_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_DRF_TESS_RESUME_MACSEC_STAT_AI_OFFSET (2) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_DRF_TESS_RESUME_MACSEC_STAT_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_DRF_TESS_RESUME_MACSEC_STAT_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_MACSEC_STAT_AE_ICG_EN_OFFSET (1) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_MACSEC_STAT_AE_ICG_EN_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_MACSEC_STAT_AE_ICG_EN_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_MACSEC_STAT_AI_ICG_EN_OFFSET (0) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_MACSEC_STAT_AI_ICG_EN_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT4_MACSEC_STAT_AI_ICG_EN_OFFSET) + +#define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT4_ADDR (0xC120) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT4_MACSEC_SA_AI_DVSE_OFFSET (27) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT4_MACSEC_SA_AI_DVSE_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT4_MACSEC_SA_AI_DVSE_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT4_MACSEC_SA_AI_DVS_OFFSET (23) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT4_MACSEC_SA_AI_DVS_MASK (0xF << RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT4_MACSEC_SA_AI_DVS_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT4_MACSEC_SA_AI_LS_OFFSET (22) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT4_MACSEC_SA_AI_LS_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT4_MACSEC_SA_AI_LS_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT4_MACSEC_SA_AI_DS_OFFSET (21) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT4_MACSEC_SA_AI_DS_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT4_MACSEC_SA_AI_DS_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT4_MACSEC_SA_AI_SD_OFFSET (20) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT4_MACSEC_SA_AI_SD_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT4_MACSEC_SA_AI_SD_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT4_MACSEC_SA_AI3_TEST1_OFFSET (19) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT4_MACSEC_SA_AI3_TEST1_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT4_MACSEC_SA_AI3_TEST1_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT4_MACSEC_SA_AI2_TEST1_OFFSET (18) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT4_MACSEC_SA_AI2_TEST1_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT4_MACSEC_SA_AI2_TEST1_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT4_MACSEC_SA_AI1_TEST1_OFFSET (17) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT4_MACSEC_SA_AI1_TEST1_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT4_MACSEC_SA_AI1_TEST1_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT4_MACSEC_SA_AI0_TEST1_OFFSET (16) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT4_MACSEC_SA_AI0_TEST1_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT4_MACSEC_SA_AI0_TEST1_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT4_MACSEC_SA_AE_DVSE_OFFSET (11) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT4_MACSEC_SA_AE_DVSE_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT4_MACSEC_SA_AE_DVSE_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT4_MACSEC_SA_AE_DVS_OFFSET (7) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT4_MACSEC_SA_AE_DVS_MASK (0xF << RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT4_MACSEC_SA_AE_DVS_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT4_MACSEC_SA_AE_LS_OFFSET (6) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT4_MACSEC_SA_AE_LS_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT4_MACSEC_SA_AE_LS_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT4_MACSEC_SA_AE_DS_OFFSET (5) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT4_MACSEC_SA_AE_DS_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT4_MACSEC_SA_AE_DS_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT4_MACSEC_SA_AE_SD_OFFSET (4) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT4_MACSEC_SA_AE_SD_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT4_MACSEC_SA_AE_SD_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT4_MACSEC_SA_AE3_TEST1_OFFSET (3) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT4_MACSEC_SA_AE3_TEST1_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT4_MACSEC_SA_AE3_TEST1_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT4_MACSEC_SA_AE2_TEST1_OFFSET (2) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT4_MACSEC_SA_AE2_TEST1_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT4_MACSEC_SA_AE2_TEST1_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT4_MACSEC_SA_AE1_TEST1_OFFSET (1) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT4_MACSEC_SA_AE1_TEST1_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT4_MACSEC_SA_AE1_TEST1_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT4_MACSEC_SA_AE0_TEST1_OFFSET (0) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT4_MACSEC_SA_AE0_TEST1_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT4_MACSEC_SA_AE0_TEST1_OFFSET) + +#define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT4_ADDR (0xC124) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT4_MACSEC_STAT_AI_DVSE_OFFSET (25) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT4_MACSEC_STAT_AI_DVSE_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT4_MACSEC_STAT_AI_DVSE_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT4_MACSEC_STAT_AI_DVS_OFFSET (21) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT4_MACSEC_STAT_AI_DVS_MASK (0xF << RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT4_MACSEC_STAT_AI_DVS_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT4_MACSEC_STAT_AI_LS_OFFSET (20) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT4_MACSEC_STAT_AI_LS_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT4_MACSEC_STAT_AI_LS_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT4_MACSEC_STAT_AI_DS_OFFSET (19) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT4_MACSEC_STAT_AI_DS_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT4_MACSEC_STAT_AI_DS_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT4_MACSEC_STAT_AI_SD_OFFSET (18) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT4_MACSEC_STAT_AI_SD_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT4_MACSEC_STAT_AI_SD_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT4_MACSEC_STAT_AI_TEST1_OFFSET (17) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT4_MACSEC_STAT_AI_TEST1_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT4_MACSEC_STAT_AI_TEST1_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT4_MACSEC_STAT_AI_TESTRWM_OFFSET (16) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT4_MACSEC_STAT_AI_TESTRWM_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT4_MACSEC_STAT_AI_TESTRWM_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT4_MACSEC_STAT_AE_DVSE_OFFSET (9) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT4_MACSEC_STAT_AE_DVSE_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT4_MACSEC_STAT_AE_DVSE_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT4_MACSEC_STAT_AE_DVS_OFFSET (5) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT4_MACSEC_STAT_AE_DVS_MASK (0xF << RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT4_MACSEC_STAT_AE_DVS_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT4_MACSEC_STAT_AE_LS_OFFSET (4) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT4_MACSEC_STAT_AE_LS_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT4_MACSEC_STAT_AE_LS_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT4_MACSEC_STAT_AE_DS_OFFSET (3) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT4_MACSEC_STAT_AE_DS_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT4_MACSEC_STAT_AE_DS_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT4_MACSEC_STAT_AE_SD_OFFSET (2) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT4_MACSEC_STAT_AE_SD_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT4_MACSEC_STAT_AE_SD_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT4_MACSEC_STAT_AE_TEST1_OFFSET (1) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT4_MACSEC_STAT_AE_TEST1_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT4_MACSEC_STAT_AE_TEST1_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT4_MACSEC_STAT_AE_TESTRWM_OFFSET (0) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT4_MACSEC_STAT_AE_TESTRWM_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT4_MACSEC_STAT_AE_TESTRWM_OFFSET) + +#define RTL8373_MACSEC_MBIST_SA_FAIL_PORT4_ADDR (0xC128) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT4_BIST_FAIL_MACSEC_STAT_AE_OFFSET (19) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT4_BIST_FAIL_MACSEC_STAT_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT4_BIST_FAIL_MACSEC_STAT_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT4_DRF_BIST_FAIL_MACSEC_STAT_AE_OFFSET (18) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT4_DRF_BIST_FAIL_MACSEC_STAT_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT4_DRF_BIST_FAIL_MACSEC_STAT_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT4_BIST_FAIL_MACSEC_STAT_AI_OFFSET (17) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT4_BIST_FAIL_MACSEC_STAT_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT4_BIST_FAIL_MACSEC_STAT_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT4_DRF_BIST_FAIL_MACSEC_STAT_AI_OFFSET (16) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT4_DRF_BIST_FAIL_MACSEC_STAT_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT4_DRF_BIST_FAIL_MACSEC_STAT_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT4_BIST_FAIL_MACSEC_SA_AE3_OFFSET (15) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT4_BIST_FAIL_MACSEC_SA_AE3_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT4_BIST_FAIL_MACSEC_SA_AE3_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT4_DRF_BIST_FAIL_MACSEC_SA_AE3_OFFSET (14) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT4_DRF_BIST_FAIL_MACSEC_SA_AE3_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT4_DRF_BIST_FAIL_MACSEC_SA_AE3_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT4_BIST_FAIL_MACSEC_SA_AE2_OFFSET (13) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT4_BIST_FAIL_MACSEC_SA_AE2_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT4_BIST_FAIL_MACSEC_SA_AE2_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT4_DRF_BIST_FAIL_MACSEC_SA_AE2_OFFSET (12) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT4_DRF_BIST_FAIL_MACSEC_SA_AE2_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT4_DRF_BIST_FAIL_MACSEC_SA_AE2_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT4_BIST_FAIL_MACSEC_SA_AE1_OFFSET (11) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT4_BIST_FAIL_MACSEC_SA_AE1_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT4_BIST_FAIL_MACSEC_SA_AE1_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT4_DRF_BIST_FAIL_MACSEC_SA_AE1_OFFSET (10) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT4_DRF_BIST_FAIL_MACSEC_SA_AE1_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT4_DRF_BIST_FAIL_MACSEC_SA_AE1_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT4_BIST_FAIL_MACSEC_SA_AE0_OFFSET (9) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT4_BIST_FAIL_MACSEC_SA_AE0_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT4_BIST_FAIL_MACSEC_SA_AE0_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT4_DRF_BIST_FAIL_MACSEC_SA_AE0_OFFSET (8) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT4_DRF_BIST_FAIL_MACSEC_SA_AE0_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT4_DRF_BIST_FAIL_MACSEC_SA_AE0_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT4_BIST_FAIL_MACSEC_SA_AI3_OFFSET (7) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT4_BIST_FAIL_MACSEC_SA_AI3_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT4_BIST_FAIL_MACSEC_SA_AI3_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT4_DRF_BIST_FAIL_MACSEC_SA_AI3_OFFSET (6) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT4_DRF_BIST_FAIL_MACSEC_SA_AI3_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT4_DRF_BIST_FAIL_MACSEC_SA_AI3_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT4_BIST_FAIL_MACSEC_SA_AI2_OFFSET (5) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT4_BIST_FAIL_MACSEC_SA_AI2_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT4_BIST_FAIL_MACSEC_SA_AI2_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT4_DRF_BIST_FAIL_MACSEC_SA_AI2_OFFSET (4) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT4_DRF_BIST_FAIL_MACSEC_SA_AI2_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT4_DRF_BIST_FAIL_MACSEC_SA_AI2_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT4_BIST_FAIL_MACSEC_SA_AI1_OFFSET (3) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT4_BIST_FAIL_MACSEC_SA_AI1_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT4_BIST_FAIL_MACSEC_SA_AI1_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT4_DRF_BIST_FAIL_MACSEC_SA_AI1_OFFSET (2) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT4_DRF_BIST_FAIL_MACSEC_SA_AI1_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT4_DRF_BIST_FAIL_MACSEC_SA_AI1_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT4_BIST_FAIL_MACSEC_SA_AI0_OFFSET (1) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT4_BIST_FAIL_MACSEC_SA_AI0_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT4_BIST_FAIL_MACSEC_SA_AI0_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT4_DRF_BIST_FAIL_MACSEC_SA_AI0_OFFSET (0) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT4_DRF_BIST_FAIL_MACSEC_SA_AI0_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT4_DRF_BIST_FAIL_MACSEC_SA_AI0_OFFSET) + +#define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT4_ADDR (0xC12C) + #define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT4_CFG_WATER_LEVEL_ST_OFFSET (28) + #define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT4_CFG_WATER_LEVEL_ST_MASK (0xF << RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT4_CFG_WATER_LEVEL_ST_OFFSET) + #define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT4_CFG_WATER_LEVEL_H_OFFSET (24) + #define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT4_CFG_WATER_LEVEL_H_MASK (0xF << RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT4_CFG_WATER_LEVEL_H_OFFSET) + #define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT4_CFG_WATER_LEVEL_L_OFFSET (20) + #define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT4_CFG_WATER_LEVEL_L_MASK (0xF << RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT4_CFG_WATER_LEVEL_L_OFFSET) + #define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT4_CFG_FAULT_ON_OFFSET (19) + #define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT4_CFG_FAULT_ON_MASK (0x1 << RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT4_CFG_FAULT_ON_OFFSET) + #define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT4_CFG_ERROR_ON_OFFSET (18) + #define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT4_CFG_ERROR_ON_MASK (0x1 << RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT4_CFG_ERROR_ON_OFFSET) + #define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT4_CFG_SEQ_RSV_ON_OFFSET (17) + #define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT4_CFG_SEQ_RSV_ON_MASK (0x1 << RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT4_CFG_SEQ_RSV_ON_OFFSET) + #define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT4_CFG_CLR_FIFO_OVTHR_OFFSET (16) + #define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT4_CFG_CLR_FIFO_OVTHR_MASK (0x1 << RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT4_CFG_CLR_FIFO_OVTHR_OFFSET) + #define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT4_XGLBK_FIFO_DBG_EN_OFFSET (4) + #define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT4_XGLBK_FIFO_DBG_EN_MASK (0x1 << RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT4_XGLBK_FIFO_DBG_EN_OFFSET) + #define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT4_XGLBK_FIFO_DBG_SEL_OFFSET (0) + #define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT4_XGLBK_FIFO_DBG_SEL_MASK (0xF << RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT4_XGLBK_FIFO_DBG_SEL_OFFSET) + +#define RTL8373_MACSEC_REG_RWDH_AE_PORT4_ADDR (0xC130) + #define RTL8373_MACSEC_REG_RWDH_AE_PORT4_REG_DATA_AE_L_OFFSET (16) + #define RTL8373_MACSEC_REG_RWDH_AE_PORT4_REG_DATA_AE_L_MASK (0xFFFF << RTL8373_MACSEC_REG_RWDH_AE_PORT4_REG_DATA_AE_L_OFFSET) + #define RTL8373_MACSEC_REG_RWDH_AE_PORT4_REG_DATA_AE_H_OFFSET (0) + #define RTL8373_MACSEC_REG_RWDH_AE_PORT4_REG_DATA_AE_H_MASK (0xFFFF << RTL8373_MACSEC_REG_RWDH_AE_PORT4_REG_DATA_AE_H_OFFSET) + +#define RTL8373_MACSEC_REG_ADDR_AE_PORT4_ADDR (0xC134) + #define RTL8373_MACSEC_REG_ADDR_AE_PORT4_REG_ADDR_AE_OFFSET (16) + #define RTL8373_MACSEC_REG_ADDR_AE_PORT4_REG_ADDR_AE_MASK (0xFFFF << RTL8373_MACSEC_REG_ADDR_AE_PORT4_REG_ADDR_AE_OFFSET) + +#define RTL8373_MACSEC_REG_CMD_AE_PORT4_ADDR (0xC138) + #define RTL8373_MACSEC_REG_CMD_AE_PORT4_REG_DATA_AI_H_OFFSET (16) + #define RTL8373_MACSEC_REG_CMD_AE_PORT4_REG_DATA_AI_H_MASK (0xFFFF << RTL8373_MACSEC_REG_CMD_AE_PORT4_REG_DATA_AI_H_OFFSET) + #define RTL8373_MACSEC_REG_CMD_AE_PORT4_REG_RD_REQ_AE_OFFSET (4) + #define RTL8373_MACSEC_REG_CMD_AE_PORT4_REG_RD_REQ_AE_MASK (0x1 << RTL8373_MACSEC_REG_CMD_AE_PORT4_REG_RD_REQ_AE_OFFSET) + #define RTL8373_MACSEC_REG_CMD_AE_PORT4_REG_WR_REQ_AE_OFFSET (0) + #define RTL8373_MACSEC_REG_CMD_AE_PORT4_REG_WR_REQ_AE_MASK (0x1 << RTL8373_MACSEC_REG_CMD_AE_PORT4_REG_WR_REQ_AE_OFFSET) + +#define RTL8373_MACSEC_REG_RWDL_AI_PORT4_ADDR (0xC13C) + #define RTL8373_MACSEC_REG_RWDL_AI_PORT4_REG_DATA_AI_L_OFFSET (0) + #define RTL8373_MACSEC_REG_RWDL_AI_PORT4_REG_DATA_AI_L_MASK (0xFFFF << RTL8373_MACSEC_REG_RWDL_AI_PORT4_REG_DATA_AI_L_OFFSET) + +#define RTL8373_MACSEC_REG_ADDR_AI_PORT4_ADDR (0xC140) + #define RTL8373_MACSEC_REG_ADDR_AI_PORT4_REG_RD_REQ_AI_OFFSET (20) + #define RTL8373_MACSEC_REG_ADDR_AI_PORT4_REG_RD_REQ_AI_MASK (0x1 << RTL8373_MACSEC_REG_ADDR_AI_PORT4_REG_RD_REQ_AI_OFFSET) + #define RTL8373_MACSEC_REG_ADDR_AI_PORT4_REG_WR_REQ_AI_OFFSET (16) + #define RTL8373_MACSEC_REG_ADDR_AI_PORT4_REG_WR_REQ_AI_MASK (0x1 << RTL8373_MACSEC_REG_ADDR_AI_PORT4_REG_WR_REQ_AI_OFFSET) + #define RTL8373_MACSEC_REG_ADDR_AI_PORT4_REG_ADDR_AI_OFFSET (0) + #define RTL8373_MACSEC_REG_ADDR_AI_PORT4_REG_ADDR_AI_MASK (0xFFFF << RTL8373_MACSEC_REG_ADDR_AI_PORT4_REG_ADDR_AI_OFFSET) + +#define RTL8373_MACSEC_REG_RWD_PTP_PORT4_ADDR (0xC144) + #define RTL8373_MACSEC_REG_RWD_PTP_PORT4_REG_ADDR_PTP_OFFSET (16) + #define RTL8373_MACSEC_REG_RWD_PTP_PORT4_REG_ADDR_PTP_MASK (0xFFFF << RTL8373_MACSEC_REG_RWD_PTP_PORT4_REG_ADDR_PTP_OFFSET) + #define RTL8373_MACSEC_REG_RWD_PTP_PORT4_REG_DATA_PTP_OFFSET (0) + #define RTL8373_MACSEC_REG_RWD_PTP_PORT4_REG_DATA_PTP_MASK (0xFFFF << RTL8373_MACSEC_REG_RWD_PTP_PORT4_REG_DATA_PTP_OFFSET) + +#define RTL8373_MACSEC_REG_CMD_PTP_PORT4_ADDR (0xC148) + #define RTL8373_MACSEC_REG_CMD_PTP_PORT4_REG_RD_REQ_PTP_OFFSET (4) + #define RTL8373_MACSEC_REG_CMD_PTP_PORT4_REG_RD_REQ_PTP_MASK (0x1 << RTL8373_MACSEC_REG_CMD_PTP_PORT4_REG_RD_REQ_PTP_OFFSET) + #define RTL8373_MACSEC_REG_CMD_PTP_PORT4_REG_WR_REQ_PTP_OFFSET (0) + #define RTL8373_MACSEC_REG_CMD_PTP_PORT4_REG_WR_REQ_PTP_MASK (0x1 << RTL8373_MACSEC_REG_CMD_PTP_PORT4_REG_WR_REQ_PTP_OFFSET) + +#define RTL8373_UNUSED_005C_PORT4_ADDR (0xC14C) + #define RTL8373_UNUSED_005C_PORT4_UNUSED_005C_PORT4_OFFSET (0) + #define RTL8373_UNUSED_005C_PORT4_UNUSED_005C_PORT4_MASK (0xFFFFFFFF << RTL8373_UNUSED_005C_PORT4_UNUSED_005C_PORT4_OFFSET) + +#define RTL8373_UNUSED_0060_PORT4_ADDR (0xC150) + #define RTL8373_UNUSED_0060_PORT4_UNUSED_0060_PORT4_OFFSET (0) + #define RTL8373_UNUSED_0060_PORT4_UNUSED_0060_PORT4_MASK (0xFFFFFFFF << RTL8373_UNUSED_0060_PORT4_UNUSED_0060_PORT4_OFFSET) + +#define RTL8373_UNUSED_0064_PORT4_ADDR (0xC154) + #define RTL8373_UNUSED_0064_PORT4_UNUSED_0064_PORT4_OFFSET (0) + #define RTL8373_UNUSED_0064_PORT4_UNUSED_0064_PORT4_MASK (0xFFFFFFFF << RTL8373_UNUSED_0064_PORT4_UNUSED_0064_PORT4_OFFSET) + +#define RTL8373_UNUSED_0068_PORT4_ADDR (0xC158) + #define RTL8373_UNUSED_0068_PORT4_UNUSED_0068_PORT4_OFFSET (0) + #define RTL8373_UNUSED_0068_PORT4_UNUSED_0068_PORT4_MASK (0xFFFFFFFF << RTL8373_UNUSED_0068_PORT4_UNUSED_0068_PORT4_OFFSET) + +#define RTL8373_UNUSED_006C_PORT4_ADDR (0xC15C) + #define RTL8373_UNUSED_006C_PORT4_UNUSED_006C_PORT4_OFFSET (0) + #define RTL8373_UNUSED_006C_PORT4_UNUSED_006C_PORT4_MASK (0xFFFFFFFF << RTL8373_UNUSED_006C_PORT4_UNUSED_006C_PORT4_OFFSET) + +#define RTL8373_UNUSED_0070_PORT4_ADDR (0xC160) + #define RTL8373_UNUSED_0070_PORT4_UNUSED_0070_PORT4_OFFSET (0) + #define RTL8373_UNUSED_0070_PORT4_UNUSED_0070_PORT4_MASK (0xFFFFFFFF << RTL8373_UNUSED_0070_PORT4_UNUSED_0070_PORT4_OFFSET) + +#define RTL8373_UNUSED_0074_PORT4_ADDR (0xC164) + #define RTL8373_UNUSED_0074_PORT4_UNUSED_0074_PORT4_OFFSET (0) + #define RTL8373_UNUSED_0074_PORT4_UNUSED_0074_PORT4_MASK (0xFFFFFFFF << RTL8373_UNUSED_0074_PORT4_UNUSED_0074_PORT4_OFFSET) + +#define RTL8373_RESERVED_0078_PORT4_ADDR (0xC168) + #define RTL8373_RESERVED_0078_PORT4_RESERVED_0078_PORT4_OFFSET (0) + #define RTL8373_RESERVED_0078_PORT4_RESERVED_0078_PORT4_MASK (0xFFFFFFFF << RTL8373_RESERVED_0078_PORT4_RESERVED_0078_PORT4_OFFSET) + +#define RTL8373_RESERVED_007C_PORT4_ADDR (0xC16C) + #define RTL8373_RESERVED_007C_PORT4_RESERVED_007C_PORT4_OFFSET (0) + #define RTL8373_RESERVED_007C_PORT4_RESERVED_007C_PORT4_MASK (0xFFFFFFFF << RTL8373_RESERVED_007C_PORT4_RESERVED_007C_PORT4_OFFSET) + +#define RTL8373_MACSEC_TXSYSCRCERR_CNT_PORT4_ADDR (0xC170) + #define RTL8373_MACSEC_TXSYSCRCERR_CNT_PORT4_TXSYS_CRCERR_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_TXSYSCRCERR_CNT_PORT4_TXSYS_CRCERR_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_TXSYSCRCERR_CNT_PORT4_TXSYS_CRCERR_CNT_H_OFFSET) + #define RTL8373_MACSEC_TXSYSCRCERR_CNT_PORT4_TXSYS_CRCERR_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_TXSYSCRCERR_CNT_PORT4_TXSYS_CRCERR_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_TXSYSCRCERR_CNT_PORT4_TXSYS_CRCERR_CNT_L_OFFSET) + +#define RTL8373_MACSEC_TXSYSPKTERR_CNT_PORT4_ADDR (0xC174) + #define RTL8373_MACSEC_TXSYSPKTERR_CNT_PORT4_TXSYS_PKTERR_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_TXSYSPKTERR_CNT_PORT4_TXSYS_PKTERR_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_TXSYSPKTERR_CNT_PORT4_TXSYS_PKTERR_CNT_H_OFFSET) + #define RTL8373_MACSEC_TXSYSPKTERR_CNT_PORT4_TXSYS_PKTERR_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_TXSYSPKTERR_CNT_PORT4_TXSYS_PKTERR_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_TXSYSPKTERR_CNT_PORT4_TXSYS_PKTERR_CNT_L_OFFSET) + +#define RTL8373_MACSEC_TXSYSOK_CNT_0_PORT4_ADDR (0xC178) + #define RTL8373_MACSEC_TXSYSOK_CNT_0_PORT4_TXSYS_OK_CNT_1_OFFSET (16) + #define RTL8373_MACSEC_TXSYSOK_CNT_0_PORT4_TXSYS_OK_CNT_1_MASK (0xFFFF << RTL8373_MACSEC_TXSYSOK_CNT_0_PORT4_TXSYS_OK_CNT_1_OFFSET) + #define RTL8373_MACSEC_TXSYSOK_CNT_0_PORT4_TXSYS_OK_CNT_0_OFFSET (0) + #define RTL8373_MACSEC_TXSYSOK_CNT_0_PORT4_TXSYS_OK_CNT_0_MASK (0xFFFF << RTL8373_MACSEC_TXSYSOK_CNT_0_PORT4_TXSYS_OK_CNT_0_OFFSET) + +#define RTL8373_MACSEC_TXSYSOK_CNT_2_PORT4_ADDR (0xC17C) + #define RTL8373_MACSEC_TXSYSOK_CNT_2_PORT4_TXSYS_OK_CNT_3_OFFSET (16) + #define RTL8373_MACSEC_TXSYSOK_CNT_2_PORT4_TXSYS_OK_CNT_3_MASK (0xFFFF << RTL8373_MACSEC_TXSYSOK_CNT_2_PORT4_TXSYS_OK_CNT_3_OFFSET) + #define RTL8373_MACSEC_TXSYSOK_CNT_2_PORT4_TXSYS_OK_CNT_2_OFFSET (0) + #define RTL8373_MACSEC_TXSYSOK_CNT_2_PORT4_TXSYS_OK_CNT_2_MASK (0xFFFF << RTL8373_MACSEC_TXSYSOK_CNT_2_PORT4_TXSYS_OK_CNT_2_OFFSET) + +#define RTL8373_MACSEC_TXSYSGERR_CNT_PORT4_ADDR (0xC180) + #define RTL8373_MACSEC_TXSYSGERR_CNT_PORT4_TXSYS_GERR_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_TXSYSGERR_CNT_PORT4_TXSYS_GERR_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_TXSYSGERR_CNT_PORT4_TXSYS_GERR_CNT_H_OFFSET) + #define RTL8373_MACSEC_TXSYSGERR_CNT_PORT4_TXSYS_GERR_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_TXSYSGERR_CNT_PORT4_TXSYS_GERR_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_TXSYSGERR_CNT_PORT4_TXSYS_GERR_CNT_L_OFFSET) + +#define RTL8373_MACSEC_TXSYSGLPIERR_CNT_PORT4_ADDR (0xC184) + #define RTL8373_MACSEC_TXSYSGLPIERR_CNT_PORT4_TXSYS_GLPIERR_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_TXSYSGLPIERR_CNT_PORT4_TXSYS_GLPIERR_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_TXSYSGLPIERR_CNT_PORT4_TXSYS_GLPIERR_CNT_H_OFFSET) + #define RTL8373_MACSEC_TXSYSGLPIERR_CNT_PORT4_TXSYS_GLPIERR_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_TXSYSGLPIERR_CNT_PORT4_TXSYS_GLPIERR_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_TXSYSGLPIERR_CNT_PORT4_TXSYS_GLPIERR_CNT_L_OFFSET) + +#define RTL8373_MACSEC_TXSYS_DBG_PORT4_ADDR (0xC188) + #define RTL8373_MACSEC_TXSYS_DBG_PORT4_TXSYS_XG2IP_FSM_OFFSET (16) + #define RTL8373_MACSEC_TXSYS_DBG_PORT4_TXSYS_XG2IP_FSM_MASK (0xF << RTL8373_MACSEC_TXSYS_DBG_PORT4_TXSYS_XG2IP_FSM_OFFSET) + #define RTL8373_MACSEC_TXSYS_DBG_PORT4_TXSYS_WRP2IP_FSM_OFFSET (0) + #define RTL8373_MACSEC_TXSYS_DBG_PORT4_TXSYS_WRP2IP_FSM_MASK (0xF << RTL8373_MACSEC_TXSYS_DBG_PORT4_TXSYS_WRP2IP_FSM_OFFSET) + +#define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT4_ADDR (0xC18C) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT4_RXSYS_UNDERRUN_CNT_INCR_OFFSET (27) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT4_RXSYS_UNDERRUN_CNT_INCR_MASK (0x1 << RTL8373_MACSEC_TX_RX_CNT_INCR_PORT4_RXSYS_UNDERRUN_CNT_INCR_OFFSET) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT4_RXSYS_DROP_CNT_INCR_OFFSET (26) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT4_RXSYS_DROP_CNT_INCR_MASK (0x1 << RTL8373_MACSEC_TX_RX_CNT_INCR_PORT4_RXSYS_DROP_CNT_INCR_OFFSET) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT4_RXSYS_PKTERR_CNT_INCR_OFFSET (25) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT4_RXSYS_PKTERR_CNT_INCR_MASK (0x1 << RTL8373_MACSEC_TX_RX_CNT_INCR_PORT4_RXSYS_PKTERR_CNT_INCR_OFFSET) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT4_RXSYS_CRCERR_CNT_INCR_OFFSET (24) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT4_RXSYS_CRCERR_CNT_INCR_MASK (0x1 << RTL8373_MACSEC_TX_RX_CNT_INCR_PORT4_RXSYS_CRCERR_CNT_INCR_OFFSET) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT4_RXLINE_OVERFLOW_CNT_INCR_OFFSET (18) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT4_RXLINE_OVERFLOW_CNT_INCR_MASK (0x1 << RTL8373_MACSEC_TX_RX_CNT_INCR_PORT4_RXLINE_OVERFLOW_CNT_INCR_OFFSET) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT4_RXLINE_PKTERR_CNT_INCR_OFFSET (17) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT4_RXLINE_PKTERR_CNT_INCR_MASK (0x1 << RTL8373_MACSEC_TX_RX_CNT_INCR_PORT4_RXLINE_PKTERR_CNT_INCR_OFFSET) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT4_RXLINE_CRCERR_CNT_INCR_OFFSET (16) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT4_RXLINE_CRCERR_CNT_INCR_MASK (0x1 << RTL8373_MACSEC_TX_RX_CNT_INCR_PORT4_RXLINE_CRCERR_CNT_INCR_OFFSET) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT4_TXLINE_UNDERRUN_CNT_INCR_OFFSET (11) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT4_TXLINE_UNDERRUN_CNT_INCR_MASK (0x1 << RTL8373_MACSEC_TX_RX_CNT_INCR_PORT4_TXLINE_UNDERRUN_CNT_INCR_OFFSET) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT4_TXLINE_DROP_CNT_INCR_OFFSET (10) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT4_TXLINE_DROP_CNT_INCR_MASK (0x1 << RTL8373_MACSEC_TX_RX_CNT_INCR_PORT4_TXLINE_DROP_CNT_INCR_OFFSET) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT4_TXLINE_PKTERR_CNT_INCR_OFFSET (9) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT4_TXLINE_PKTERR_CNT_INCR_MASK (0x1 << RTL8373_MACSEC_TX_RX_CNT_INCR_PORT4_TXLINE_PKTERR_CNT_INCR_OFFSET) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT4_TXLINE_CRCERR_CNT_INCR_OFFSET (8) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT4_TXLINE_CRCERR_CNT_INCR_MASK (0x1 << RTL8373_MACSEC_TX_RX_CNT_INCR_PORT4_TXLINE_CRCERR_CNT_INCR_OFFSET) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT4_TXSYS_OVERFLOW_CNT_INCR_OFFSET (2) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT4_TXSYS_OVERFLOW_CNT_INCR_MASK (0x1 << RTL8373_MACSEC_TX_RX_CNT_INCR_PORT4_TXSYS_OVERFLOW_CNT_INCR_OFFSET) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT4_TXSYS_PKTERR_CNT_INCR_OFFSET (1) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT4_TXSYS_PKTERR_CNT_INCR_MASK (0x1 << RTL8373_MACSEC_TX_RX_CNT_INCR_PORT4_TXSYS_PKTERR_CNT_INCR_OFFSET) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT4_TXSYS_CRCERR_CNT_INCR_OFFSET (0) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT4_TXSYS_CRCERR_CNT_INCR_MASK (0x1 << RTL8373_MACSEC_TX_RX_CNT_INCR_PORT4_TXSYS_CRCERR_CNT_INCR_OFFSET) + +#define RTL8373_MACSEC_TXLINECRCERR_CNT_PORT4_ADDR (0xC190) + #define RTL8373_MACSEC_TXLINECRCERR_CNT_PORT4_TXLINE_CRCERR_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_TXLINECRCERR_CNT_PORT4_TXLINE_CRCERR_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_TXLINECRCERR_CNT_PORT4_TXLINE_CRCERR_CNT_H_OFFSET) + #define RTL8373_MACSEC_TXLINECRCERR_CNT_PORT4_TXLINE_CRCERR_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_TXLINECRCERR_CNT_PORT4_TXLINE_CRCERR_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_TXLINECRCERR_CNT_PORT4_TXLINE_CRCERR_CNT_L_OFFSET) + +#define RTL8373_MACSEC_TXLINEPKTERR_CNT_PORT4_ADDR (0xC194) + #define RTL8373_MACSEC_TXLINEPKTERR_CNT_PORT4_TXLINE_PKTERR_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_TXLINEPKTERR_CNT_PORT4_TXLINE_PKTERR_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_TXLINEPKTERR_CNT_PORT4_TXLINE_PKTERR_CNT_H_OFFSET) + #define RTL8373_MACSEC_TXLINEPKTERR_CNT_PORT4_TXLINE_PKTERR_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_TXLINEPKTERR_CNT_PORT4_TXLINE_PKTERR_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_TXLINEPKTERR_CNT_PORT4_TXLINE_PKTERR_CNT_L_OFFSET) + +#define RTL8373_MACSEC_TXLINEOK_CNT_0_PORT4_ADDR (0xC198) + #define RTL8373_MACSEC_TXLINEOK_CNT_0_PORT4_TXLINE_OK_CNT_1_OFFSET (16) + #define RTL8373_MACSEC_TXLINEOK_CNT_0_PORT4_TXLINE_OK_CNT_1_MASK (0xFFFF << RTL8373_MACSEC_TXLINEOK_CNT_0_PORT4_TXLINE_OK_CNT_1_OFFSET) + #define RTL8373_MACSEC_TXLINEOK_CNT_0_PORT4_TXLINE_OK_CNT_0_OFFSET (0) + #define RTL8373_MACSEC_TXLINEOK_CNT_0_PORT4_TXLINE_OK_CNT_0_MASK (0xFFFF << RTL8373_MACSEC_TXLINEOK_CNT_0_PORT4_TXLINE_OK_CNT_0_OFFSET) + +#define RTL8373_MACSEC_TXLINEOK_CNT_2_PORT4_ADDR (0xC19C) + #define RTL8373_MACSEC_TXLINEOK_CNT_2_PORT4_TXLINE_OK_CNT_3_OFFSET (16) + #define RTL8373_MACSEC_TXLINEOK_CNT_2_PORT4_TXLINE_OK_CNT_3_MASK (0xFFFF << RTL8373_MACSEC_TXLINEOK_CNT_2_PORT4_TXLINE_OK_CNT_3_OFFSET) + #define RTL8373_MACSEC_TXLINEOK_CNT_2_PORT4_TXLINE_OK_CNT_2_OFFSET (0) + #define RTL8373_MACSEC_TXLINEOK_CNT_2_PORT4_TXLINE_OK_CNT_2_MASK (0xFFFF << RTL8373_MACSEC_TXLINEOK_CNT_2_PORT4_TXLINE_OK_CNT_2_OFFSET) + +#define RTL8373_MACSEC_TXLINEDROP_CNT_PORT4_ADDR (0xC1A0) + #define RTL8373_MACSEC_TXLINEDROP_CNT_PORT4_TXLINE_DROP_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_TXLINEDROP_CNT_PORT4_TXLINE_DROP_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_TXLINEDROP_CNT_PORT4_TXLINE_DROP_CNT_H_OFFSET) + #define RTL8373_MACSEC_TXLINEDROP_CNT_PORT4_TXLINE_DROP_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_TXLINEDROP_CNT_PORT4_TXLINE_DROP_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_TXLINEDROP_CNT_PORT4_TXLINE_DROP_CNT_L_OFFSET) + +#define RTL8373_MACSEC_TXLINESRT_CNT_PORT4_ADDR (0xC1A4) + #define RTL8373_MACSEC_TXLINESRT_CNT_PORT4_TXLINE_SRTPKT_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_TXLINESRT_CNT_PORT4_TXLINE_SRTPKT_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_TXLINESRT_CNT_PORT4_TXLINE_SRTPKT_CNT_H_OFFSET) + #define RTL8373_MACSEC_TXLINESRT_CNT_PORT4_TXLINE_SRTPKT_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_TXLINESRT_CNT_PORT4_TXLINE_SRTPKT_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_TXLINESRT_CNT_PORT4_TXLINE_SRTPKT_CNT_L_OFFSET) + +#define RTL8373_MACSEC_TXLINEGERR_CNT_PORT4_ADDR (0xC1A8) + #define RTL8373_MACSEC_TXLINEGERR_CNT_PORT4_TXLINE_GERR_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_TXLINEGERR_CNT_PORT4_TXLINE_GERR_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_TXLINEGERR_CNT_PORT4_TXLINE_GERR_CNT_H_OFFSET) + #define RTL8373_MACSEC_TXLINEGERR_CNT_PORT4_TXLINE_GERR_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_TXLINEGERR_CNT_PORT4_TXLINE_GERR_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_TXLINEGERR_CNT_PORT4_TXLINE_GERR_CNT_L_OFFSET) + +#define RTL8373_MACSEC_TXLINE_DBG_PORT4_ADDR (0xC1AC) + #define RTL8373_MACSEC_TXLINE_DBG_PORT4_TXLINE_IP2XG_FSM_OFFSET (16) + #define RTL8373_MACSEC_TXLINE_DBG_PORT4_TXLINE_IP2XG_FSM_MASK (0x1F << RTL8373_MACSEC_TXLINE_DBG_PORT4_TXLINE_IP2XG_FSM_OFFSET) + #define RTL8373_MACSEC_TXLINE_DBG_PORT4_TXLINE_IP2WRP_FSM_OFFSET (0) + #define RTL8373_MACSEC_TXLINE_DBG_PORT4_TXLINE_IP2WRP_FSM_MASK (0xF << RTL8373_MACSEC_TXLINE_DBG_PORT4_TXLINE_IP2WRP_FSM_OFFSET) + +#define RTL8373_MACSEC_RXLINECRCERR_CNT_PORT4_ADDR (0xC1B0) + #define RTL8373_MACSEC_RXLINECRCERR_CNT_PORT4_RXLINE_CRCERR_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_RXLINECRCERR_CNT_PORT4_RXLINE_CRCERR_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_RXLINECRCERR_CNT_PORT4_RXLINE_CRCERR_CNT_H_OFFSET) + #define RTL8373_MACSEC_RXLINECRCERR_CNT_PORT4_RXLINE_CRCERR_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_RXLINECRCERR_CNT_PORT4_RXLINE_CRCERR_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_RXLINECRCERR_CNT_PORT4_RXLINE_CRCERR_CNT_L_OFFSET) + +#define RTL8373_MACSEC_RXLINEPKTERR_CNT_PORT4_ADDR (0xC1B4) + #define RTL8373_MACSEC_RXLINEPKTERR_CNT_PORT4_RXLINE_PKTERR_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_RXLINEPKTERR_CNT_PORT4_RXLINE_PKTERR_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_RXLINEPKTERR_CNT_PORT4_RXLINE_PKTERR_CNT_H_OFFSET) + #define RTL8373_MACSEC_RXLINEPKTERR_CNT_PORT4_RXLINE_PKTERR_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_RXLINEPKTERR_CNT_PORT4_RXLINE_PKTERR_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_RXLINEPKTERR_CNT_PORT4_RXLINE_PKTERR_CNT_L_OFFSET) + +#define RTL8373_MACSEC_RXLINEOK_CNT_0_PORT4_ADDR (0xC1B8) + #define RTL8373_MACSEC_RXLINEOK_CNT_0_PORT4_RXLINE_OK_CNT_1_OFFSET (16) + #define RTL8373_MACSEC_RXLINEOK_CNT_0_PORT4_RXLINE_OK_CNT_1_MASK (0xFFFF << RTL8373_MACSEC_RXLINEOK_CNT_0_PORT4_RXLINE_OK_CNT_1_OFFSET) + #define RTL8373_MACSEC_RXLINEOK_CNT_0_PORT4_RXLINE_OK_CNT_0_OFFSET (0) + #define RTL8373_MACSEC_RXLINEOK_CNT_0_PORT4_RXLINE_OK_CNT_0_MASK (0xFFFF << RTL8373_MACSEC_RXLINEOK_CNT_0_PORT4_RXLINE_OK_CNT_0_OFFSET) + +#define RTL8373_MACSEC_RXLINEOK_CNT_2_PORT4_ADDR (0xC1BC) + #define RTL8373_MACSEC_RXLINEOK_CNT_2_PORT4_RXLINE_OK_CNT_3_OFFSET (16) + #define RTL8373_MACSEC_RXLINEOK_CNT_2_PORT4_RXLINE_OK_CNT_3_MASK (0xFFFF << RTL8373_MACSEC_RXLINEOK_CNT_2_PORT4_RXLINE_OK_CNT_3_OFFSET) + #define RTL8373_MACSEC_RXLINEOK_CNT_2_PORT4_RXLINE_OK_CNT_2_OFFSET (0) + #define RTL8373_MACSEC_RXLINEOK_CNT_2_PORT4_RXLINE_OK_CNT_2_MASK (0xFFFF << RTL8373_MACSEC_RXLINEOK_CNT_2_PORT4_RXLINE_OK_CNT_2_OFFSET) + +#define RTL8373_MACSEC_RXLINESRT_CNT_PORT4_ADDR (0xC1C0) + #define RTL8373_MACSEC_RXLINESRT_CNT_PORT4_RXLINE_SHORTPKT_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_RXLINESRT_CNT_PORT4_RXLINE_SHORTPKT_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_RXLINESRT_CNT_PORT4_RXLINE_SHORTPKT_CNT_H_OFFSET) + #define RTL8373_MACSEC_RXLINESRT_CNT_PORT4_RXLINE_SHORTPKT_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_RXLINESRT_CNT_PORT4_RXLINE_SHORTPKT_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_RXLINESRT_CNT_PORT4_RXLINE_SHORTPKT_CNT_L_OFFSET) + +#define RTL8373_MACSEC_RXLINEGERR_CNT_PORT4_ADDR (0xC1C4) + #define RTL8373_MACSEC_RXLINEGERR_CNT_PORT4_RXLINE_GERR_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_RXLINEGERR_CNT_PORT4_RXLINE_GERR_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_RXLINEGERR_CNT_PORT4_RXLINE_GERR_CNT_H_OFFSET) + #define RTL8373_MACSEC_RXLINEGERR_CNT_PORT4_RXLINE_GERR_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_RXLINEGERR_CNT_PORT4_RXLINE_GERR_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_RXLINEGERR_CNT_PORT4_RXLINE_GERR_CNT_L_OFFSET) + +#define RTL8373_MACSEC_RXLINEGLPIERR_CNT_PORT4_ADDR (0xC1C8) + #define RTL8373_MACSEC_RXLINEGLPIERR_CNT_PORT4_RXLINE_GLPIERR_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_RXLINEGLPIERR_CNT_PORT4_RXLINE_GLPIERR_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_RXLINEGLPIERR_CNT_PORT4_RXLINE_GLPIERR_CNT_H_OFFSET) + #define RTL8373_MACSEC_RXLINEGLPIERR_CNT_PORT4_RXLINE_GLPIERR_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_RXLINEGLPIERR_CNT_PORT4_RXLINE_GLPIERR_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_RXLINEGLPIERR_CNT_PORT4_RXLINE_GLPIERR_CNT_L_OFFSET) + +#define RTL8373_MACSEC_RXLINE_DBG_PORT4_ADDR (0xC1CC) + #define RTL8373_MACSEC_RXLINE_DBG_PORT4_RXLINE_XG2IP_FSM_OFFSET (16) + #define RTL8373_MACSEC_RXLINE_DBG_PORT4_RXLINE_XG2IP_FSM_MASK (0xF << RTL8373_MACSEC_RXLINE_DBG_PORT4_RXLINE_XG2IP_FSM_OFFSET) + #define RTL8373_MACSEC_RXLINE_DBG_PORT4_RXLINE_WRP2IP_FSM_OFFSET (0) + #define RTL8373_MACSEC_RXLINE_DBG_PORT4_RXLINE_WRP2IP_FSM_MASK (0xF << RTL8373_MACSEC_RXLINE_DBG_PORT4_RXLINE_WRP2IP_FSM_OFFSET) + +#define RTL8373_MACSEC_RXSYSCRCERR_CNT_PORT4_ADDR (0xC1D0) + #define RTL8373_MACSEC_RXSYSCRCERR_CNT_PORT4_RXSYS_CRCERR_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_RXSYSCRCERR_CNT_PORT4_RXSYS_CRCERR_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_RXSYSCRCERR_CNT_PORT4_RXSYS_CRCERR_CNT_H_OFFSET) + #define RTL8373_MACSEC_RXSYSCRCERR_CNT_PORT4_RXSYS_CRCERR_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_RXSYSCRCERR_CNT_PORT4_RXSYS_CRCERR_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_RXSYSCRCERR_CNT_PORT4_RXSYS_CRCERR_CNT_L_OFFSET) + +#define RTL8373_MACSEC_RXSYSPKTERR_CNT_PORT4_ADDR (0xC1D4) + #define RTL8373_MACSEC_RXSYSPKTERR_CNT_PORT4_RXSYS_PKTERR_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_RXSYSPKTERR_CNT_PORT4_RXSYS_PKTERR_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_RXSYSPKTERR_CNT_PORT4_RXSYS_PKTERR_CNT_H_OFFSET) + #define RTL8373_MACSEC_RXSYSPKTERR_CNT_PORT4_RXSYS_PKTERR_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_RXSYSPKTERR_CNT_PORT4_RXSYS_PKTERR_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_RXSYSPKTERR_CNT_PORT4_RXSYS_PKTERR_CNT_L_OFFSET) + +#define RTL8373_MACSEC_RXSYSOK_CNT_0_PORT4_ADDR (0xC1D8) + #define RTL8373_MACSEC_RXSYSOK_CNT_0_PORT4_RXSYS_OK_CNT_1_OFFSET (16) + #define RTL8373_MACSEC_RXSYSOK_CNT_0_PORT4_RXSYS_OK_CNT_1_MASK (0xFFFF << RTL8373_MACSEC_RXSYSOK_CNT_0_PORT4_RXSYS_OK_CNT_1_OFFSET) + #define RTL8373_MACSEC_RXSYSOK_CNT_0_PORT4_RXSYS_OK_CNT_0_OFFSET (0) + #define RTL8373_MACSEC_RXSYSOK_CNT_0_PORT4_RXSYS_OK_CNT_0_MASK (0xFFFF << RTL8373_MACSEC_RXSYSOK_CNT_0_PORT4_RXSYS_OK_CNT_0_OFFSET) + +#define RTL8373_MACSEC_RXSYSOK_CNT_2_PORT4_ADDR (0xC1DC) + #define RTL8373_MACSEC_RXSYSOK_CNT_2_PORT4_RXSYS_OK_CNT_3_OFFSET (16) + #define RTL8373_MACSEC_RXSYSOK_CNT_2_PORT4_RXSYS_OK_CNT_3_MASK (0xFFFF << RTL8373_MACSEC_RXSYSOK_CNT_2_PORT4_RXSYS_OK_CNT_3_OFFSET) + #define RTL8373_MACSEC_RXSYSOK_CNT_2_PORT4_RXSYS_OK_CNT_2_OFFSET (0) + #define RTL8373_MACSEC_RXSYSOK_CNT_2_PORT4_RXSYS_OK_CNT_2_MASK (0xFFFF << RTL8373_MACSEC_RXSYSOK_CNT_2_PORT4_RXSYS_OK_CNT_2_OFFSET) + +#define RTL8373_MACSEC_RXSYSDROP_CNT_PORT4_ADDR (0xC1E0) + #define RTL8373_MACSEC_RXSYSDROP_CNT_PORT4_RXSYS_DROP_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_RXSYSDROP_CNT_PORT4_RXSYS_DROP_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_RXSYSDROP_CNT_PORT4_RXSYS_DROP_CNT_H_OFFSET) + #define RTL8373_MACSEC_RXSYSDROP_CNT_PORT4_RXSYS_DROP_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_RXSYSDROP_CNT_PORT4_RXSYS_DROP_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_RXSYSDROP_CNT_PORT4_RXSYS_DROP_CNT_L_OFFSET) + +#define RTL8373_MACSEC_RXSYSSRT_CNT_PORT4_ADDR (0xC1E4) + #define RTL8373_MACSEC_RXSYSSRT_CNT_PORT4_RXSYS_DECRYPTSRT_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_RXSYSSRT_CNT_PORT4_RXSYS_DECRYPTSRT_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_RXSYSSRT_CNT_PORT4_RXSYS_DECRYPTSRT_CNT_H_OFFSET) + #define RTL8373_MACSEC_RXSYSSRT_CNT_PORT4_RXSYS_DECRYPTSRT_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_RXSYSSRT_CNT_PORT4_RXSYS_DECRYPTSRT_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_RXSYSSRT_CNT_PORT4_RXSYS_DECRYPTSRT_CNT_L_OFFSET) + +#define RTL8373_MACSEC_RXSYSGERR_CNT_PORT4_ADDR (0xC1E8) + #define RTL8373_MACSEC_RXSYSGERR_CNT_PORT4_RXSYS_GERR_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_RXSYSGERR_CNT_PORT4_RXSYS_GERR_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_RXSYSGERR_CNT_PORT4_RXSYS_GERR_CNT_H_OFFSET) + #define RTL8373_MACSEC_RXSYSGERR_CNT_PORT4_RXSYS_GERR_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_RXSYSGERR_CNT_PORT4_RXSYS_GERR_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_RXSYSGERR_CNT_PORT4_RXSYS_GERR_CNT_L_OFFSET) + +#define RTL8373_MACSEC_RXSYS_DBG_PORT4_ADDR (0xC1EC) + #define RTL8373_MACSEC_RXSYS_DBG_PORT4_RXSYS_IP2XG_FSM_OFFSET (16) + #define RTL8373_MACSEC_RXSYS_DBG_PORT4_RXSYS_IP2XG_FSM_MASK (0x1F << RTL8373_MACSEC_RXSYS_DBG_PORT4_RXSYS_IP2XG_FSM_OFFSET) + #define RTL8373_MACSEC_RXSYS_DBG_PORT4_RXSYS_IP2WRP_FSM_OFFSET (0) + #define RTL8373_MACSEC_RXSYS_DBG_PORT4_RXSYS_IP2WRP_FSM_MASK (0xF << RTL8373_MACSEC_RXSYS_DBG_PORT4_RXSYS_IP2WRP_FSM_OFFSET) + +#define RTL8373_MACSEC_TXSYS_CFG1_PORT4_ADDR (0xC1F0) + #define RTL8373_MACSEC_TXSYS_CFG1_PORT4_TXSYS_XGMINIFG_OFFSET (16) + #define RTL8373_MACSEC_TXSYS_CFG1_PORT4_TXSYS_XGMINIFG_MASK (0x1F << RTL8373_MACSEC_TXSYS_CFG1_PORT4_TXSYS_XGMINIFG_OFFSET) + #define RTL8373_MACSEC_TXSYS_CFG1_PORT4_TXSYS_MINIFG_OFFSET (8) + #define RTL8373_MACSEC_TXSYS_CFG1_PORT4_TXSYS_MINIFG_MASK (0xF << RTL8373_MACSEC_TXSYS_CFG1_PORT4_TXSYS_MINIFG_OFFSET) + #define RTL8373_MACSEC_TXSYS_CFG1_PORT4_TXSYS_PMBNUM_OFFSET (0) + #define RTL8373_MACSEC_TXSYS_CFG1_PORT4_TXSYS_PMBNUM_MASK (0x7 << RTL8373_MACSEC_TXSYS_CFG1_PORT4_TXSYS_PMBNUM_OFFSET) + +#define RTL8373_MACSEC_TXSYS_PTPCFG_PORT4_ADDR (0xC1F4) + #define RTL8373_MACSEC_TXSYS_PTPCFG_PORT4_TXSYS_OUTERVLAN1_OFFSET (16) + #define RTL8373_MACSEC_TXSYS_PTPCFG_PORT4_TXSYS_OUTERVLAN1_MASK (0xFFFF << RTL8373_MACSEC_TXSYS_PTPCFG_PORT4_TXSYS_OUTERVLAN1_OFFSET) + #define RTL8373_MACSEC_TXSYS_PTPCFG_PORT4_PTP_UDP_EN_OFFSET (13) + #define RTL8373_MACSEC_TXSYS_PTPCFG_PORT4_PTP_UDP_EN_MASK (0x1 << RTL8373_MACSEC_TXSYS_PTPCFG_PORT4_PTP_UDP_EN_OFFSET) + #define RTL8373_MACSEC_TXSYS_PTPCFG_PORT4_PTP_ETH_EN_OFFSET (12) + #define RTL8373_MACSEC_TXSYS_PTPCFG_PORT4_PTP_ETH_EN_MASK (0x1 << RTL8373_MACSEC_TXSYS_PTPCFG_PORT4_PTP_ETH_EN_OFFSET) + #define RTL8373_MACSEC_TXSYS_PTPCFG_PORT4_TXSYS_PTPCRYPT_EN_OFFSET (8) + #define RTL8373_MACSEC_TXSYS_PTPCFG_PORT4_TXSYS_PTPCRYPT_EN_MASK (0x1 << RTL8373_MACSEC_TXSYS_PTPCFG_PORT4_TXSYS_PTPCRYPT_EN_OFFSET) + #define RTL8373_MACSEC_TXSYS_PTPCFG_PORT4_TXSYS_FLOWID_OFFSET (0) + #define RTL8373_MACSEC_TXSYS_PTPCFG_PORT4_TXSYS_FLOWID_MASK (0x3F << RTL8373_MACSEC_TXSYS_PTPCFG_PORT4_TXSYS_FLOWID_OFFSET) + +#define RTL8373_MACSEC_TXSYS_OUTERVLAN2_PORT4_ADDR (0xC1F8) + #define RTL8373_MACSEC_TXSYS_OUTERVLAN2_PORT4_TXSYS_OUTERVLAN3_OFFSET (16) + #define RTL8373_MACSEC_TXSYS_OUTERVLAN2_PORT4_TXSYS_OUTERVLAN3_MASK (0xFFFF << RTL8373_MACSEC_TXSYS_OUTERVLAN2_PORT4_TXSYS_OUTERVLAN3_OFFSET) + #define RTL8373_MACSEC_TXSYS_OUTERVLAN2_PORT4_TXSYS_OUTERVLAN2_OFFSET (0) + #define RTL8373_MACSEC_TXSYS_OUTERVLAN2_PORT4_TXSYS_OUTERVLAN2_MASK (0xFFFF << RTL8373_MACSEC_TXSYS_OUTERVLAN2_PORT4_TXSYS_OUTERVLAN2_OFFSET) + +#define RTL8373_MACSEC_TXSYS_OUTERVLAN4_PORT4_ADDR (0xC1FC) + #define RTL8373_MACSEC_TXSYS_OUTERVLAN4_PORT4_TXSYS_INNERVLAN1_OFFSET (16) + #define RTL8373_MACSEC_TXSYS_OUTERVLAN4_PORT4_TXSYS_INNERVLAN1_MASK (0xFFFF << RTL8373_MACSEC_TXSYS_OUTERVLAN4_PORT4_TXSYS_INNERVLAN1_OFFSET) + #define RTL8373_MACSEC_TXSYS_OUTERVLAN4_PORT4_TXSYS_OUTERVLAN4_OFFSET (0) + #define RTL8373_MACSEC_TXSYS_OUTERVLAN4_PORT4_TXSYS_OUTERVLAN4_MASK (0xFFFF << RTL8373_MACSEC_TXSYS_OUTERVLAN4_PORT4_TXSYS_OUTERVLAN4_OFFSET) + +#define RTL8373_MACSEC_TXSYS_INNERVLAN2_PORT4_ADDR (0xC200) + #define RTL8373_MACSEC_TXSYS_INNERVLAN2_PORT4_TXSYS_INNERVLAN3_OFFSET (16) + #define RTL8373_MACSEC_TXSYS_INNERVLAN2_PORT4_TXSYS_INNERVLAN3_MASK (0xFFFF << RTL8373_MACSEC_TXSYS_INNERVLAN2_PORT4_TXSYS_INNERVLAN3_OFFSET) + #define RTL8373_MACSEC_TXSYS_INNERVLAN2_PORT4_TXSYS_INNERVLAN2_OFFSET (0) + #define RTL8373_MACSEC_TXSYS_INNERVLAN2_PORT4_TXSYS_INNERVLAN2_MASK (0xFFFF << RTL8373_MACSEC_TXSYS_INNERVLAN2_PORT4_TXSYS_INNERVLAN2_OFFSET) + +#define RTL8373_MACSEC_TXSYS_INNERVLAN4_PORT4_ADDR (0xC204) + #define RTL8373_MACSEC_TXSYS_INNERVLAN4_PORT4_TXSYS_INNERVLAN5_OFFSET (16) + #define RTL8373_MACSEC_TXSYS_INNERVLAN4_PORT4_TXSYS_INNERVLAN5_MASK (0xFFFF << RTL8373_MACSEC_TXSYS_INNERVLAN4_PORT4_TXSYS_INNERVLAN5_OFFSET) + #define RTL8373_MACSEC_TXSYS_INNERVLAN4_PORT4_TXSYS_INNERVLAN4_OFFSET (0) + #define RTL8373_MACSEC_TXSYS_INNERVLAN4_PORT4_TXSYS_INNERVLAN4_MASK (0xFFFF << RTL8373_MACSEC_TXSYS_INNERVLAN4_PORT4_TXSYS_INNERVLAN4_OFFSET) + +#define RTL8373_MACSEC_TXSYS_INNERVLAN6_PORT4_ADDR (0xC208) + #define RTL8373_MACSEC_TXSYS_INNERVLAN6_PORT4_TXSYS_INNERVLAN7_OFFSET (16) + #define RTL8373_MACSEC_TXSYS_INNERVLAN6_PORT4_TXSYS_INNERVLAN7_MASK (0xFFFF << RTL8373_MACSEC_TXSYS_INNERVLAN6_PORT4_TXSYS_INNERVLAN7_OFFSET) + #define RTL8373_MACSEC_TXSYS_INNERVLAN6_PORT4_TXSYS_INNERVLAN6_OFFSET (0) + #define RTL8373_MACSEC_TXSYS_INNERVLAN6_PORT4_TXSYS_INNERVLAN6_MASK (0xFFFF << RTL8373_MACSEC_TXSYS_INNERVLAN6_PORT4_TXSYS_INNERVLAN6_OFFSET) + +#define RTL8373_UNUSED_011C_PORT4_ADDR (0xC20C) + #define RTL8373_UNUSED_011C_PORT4_UNUSED_011C_PORT4_OFFSET (0) + #define RTL8373_UNUSED_011C_PORT4_UNUSED_011C_PORT4_MASK (0xFFFFFFFF << RTL8373_UNUSED_011C_PORT4_UNUSED_011C_PORT4_OFFSET) + +#define RTL8373_UNUSED_0120_PORT4_ADDR (0xC210) + #define RTL8373_UNUSED_0120_PORT4_UNUSED_0120_PORT4_OFFSET (0) + #define RTL8373_UNUSED_0120_PORT4_UNUSED_0120_PORT4_MASK (0xFFFFFFFF << RTL8373_UNUSED_0120_PORT4_UNUSED_0120_PORT4_OFFSET) + +#define RTL8373_UNUSED_0124_PORT4_ADDR (0xC214) + #define RTL8373_UNUSED_0124_PORT4_UNUSED_0124_PORT4_OFFSET (0) + #define RTL8373_UNUSED_0124_PORT4_UNUSED_0124_PORT4_MASK (0xFFFFFFFF << RTL8373_UNUSED_0124_PORT4_UNUSED_0124_PORT4_OFFSET) + +#define RTL8373_UNUSED_0128_PORT4_ADDR (0xC218) + #define RTL8373_UNUSED_0128_PORT4_UNUSED_0128_PORT4_OFFSET (0) + #define RTL8373_UNUSED_0128_PORT4_UNUSED_0128_PORT4_MASK (0xFFFFFFFF << RTL8373_UNUSED_0128_PORT4_UNUSED_0128_PORT4_OFFSET) + +#define RTL8373_UNUSED_012C_PORT4_ADDR (0xC21C) + #define RTL8373_UNUSED_012C_PORT4_UNUSED_012C_PORT4_OFFSET (0) + #define RTL8373_UNUSED_012C_PORT4_UNUSED_012C_PORT4_MASK (0xFFFFFFFF << RTL8373_UNUSED_012C_PORT4_UNUSED_012C_PORT4_OFFSET) + +#define RTL8373_UNUSED_0130_PORT4_ADDR (0xC220) + #define RTL8373_UNUSED_0130_PORT4_UNUSED_0130_PORT4_OFFSET (0) + #define RTL8373_UNUSED_0130_PORT4_UNUSED_0130_PORT4_MASK (0xFFFFFFFF << RTL8373_UNUSED_0130_PORT4_UNUSED_0130_PORT4_OFFSET) + +#define RTL8373_UNUSED_0134_PORT4_ADDR (0xC224) + #define RTL8373_UNUSED_0134_PORT4_UNUSED_0134_PORT4_OFFSET (0) + #define RTL8373_UNUSED_0134_PORT4_UNUSED_0134_PORT4_MASK (0xFFFFFFFF << RTL8373_UNUSED_0134_PORT4_UNUSED_0134_PORT4_OFFSET) + +#define RTL8373_UNUSED_0138_PORT4_ADDR (0xC228) + #define RTL8373_UNUSED_0138_PORT4_UNUSED_0138_PORT4_OFFSET (0) + #define RTL8373_UNUSED_0138_PORT4_UNUSED_0138_PORT4_MASK (0xFFFFFFFF << RTL8373_UNUSED_0138_PORT4_UNUSED_0138_PORT4_OFFSET) + +#define RTL8373_UNUSED_013C_PORT4_ADDR (0xC22C) + #define RTL8373_UNUSED_013C_PORT4_UNUSED_013C_PORT4_OFFSET (0) + #define RTL8373_UNUSED_013C_PORT4_UNUSED_013C_PORT4_MASK (0xFFFFFFFF << RTL8373_UNUSED_013C_PORT4_UNUSED_013C_PORT4_OFFSET) + +#define RTL8373_MACSEC_TXLINE_CFG1_PORT4_ADDR (0xC230) + #define RTL8373_MACSEC_TXLINE_CFG1_PORT4_TXLINE_WAIT_T_OFFSET (16) + #define RTL8373_MACSEC_TXLINE_CFG1_PORT4_TXLINE_WAIT_T_MASK (0xFF << RTL8373_MACSEC_TXLINE_CFG1_PORT4_TXLINE_WAIT_T_OFFSET) + #define RTL8373_MACSEC_TXLINE_CFG1_PORT4_TXLINE_MINIFG_OFFSET (8) + #define RTL8373_MACSEC_TXLINE_CFG1_PORT4_TXLINE_MINIFG_MASK (0xFF << RTL8373_MACSEC_TXLINE_CFG1_PORT4_TXLINE_MINIFG_OFFSET) + #define RTL8373_MACSEC_TXLINE_CFG1_PORT4_TXLINE_PMBNUM_OFFSET (0) + #define RTL8373_MACSEC_TXLINE_CFG1_PORT4_TXLINE_PMBNUM_MASK (0xF << RTL8373_MACSEC_TXLINE_CFG1_PORT4_TXLINE_PMBNUM_OFFSET) + +#define RTL8373_MACSEC_TXLINE_CFG3_PORT4_ADDR (0xC234) + #define RTL8373_MACSEC_TXLINE_CFG3_PORT4_TXLINE_FIFO_TSHD_OFFSET (16) + #define RTL8373_MACSEC_TXLINE_CFG3_PORT4_TXLINE_FIFO_TSHD_MASK (0xFF << RTL8373_MACSEC_TXLINE_CFG3_PORT4_TXLINE_FIFO_TSHD_OFFSET) + #define RTL8373_MACSEC_TXLINE_CFG3_PORT4_TXLINE_PAD_VLAN_EN_OFFSET (14) + #define RTL8373_MACSEC_TXLINE_CFG3_PORT4_TXLINE_PAD_VLAN_EN_MASK (0x1 << RTL8373_MACSEC_TXLINE_CFG3_PORT4_TXLINE_PAD_VLAN_EN_OFFSET) + #define RTL8373_MACSEC_TXLINE_CFG3_PORT4_TXLINE_PAD_MACSEC_EN_OFFSET (13) + #define RTL8373_MACSEC_TXLINE_CFG3_PORT4_TXLINE_PAD_MACSEC_EN_MASK (0x1 << RTL8373_MACSEC_TXLINE_CFG3_PORT4_TXLINE_PAD_MACSEC_EN_OFFSET) + #define RTL8373_MACSEC_TXLINE_CFG3_PORT4_TXLINE_PAD_EN_OFFSET (12) + #define RTL8373_MACSEC_TXLINE_CFG3_PORT4_TXLINE_PAD_EN_MASK (0x1 << RTL8373_MACSEC_TXLINE_CFG3_PORT4_TXLINE_PAD_EN_OFFSET) + #define RTL8373_MACSEC_TXLINE_CFG3_PORT4_TXLINE_PKTERR_INVRSCRC_EN_OFFSET (8) + #define RTL8373_MACSEC_TXLINE_CFG3_PORT4_TXLINE_PKTERR_INVRSCRC_EN_MASK (0x1 << RTL8373_MACSEC_TXLINE_CFG3_PORT4_TXLINE_PKTERR_INVRSCRC_EN_OFFSET) + #define RTL8373_MACSEC_TXLINE_CFG3_PORT4_TXLINE_GMIIER_INVRSCRC_EN_OFFSET (5) + #define RTL8373_MACSEC_TXLINE_CFG3_PORT4_TXLINE_GMIIER_INVRSCRC_EN_MASK (0x1 << RTL8373_MACSEC_TXLINE_CFG3_PORT4_TXLINE_GMIIER_INVRSCRC_EN_OFFSET) + #define RTL8373_MACSEC_TXLINE_CFG3_PORT4_TXLINE_CRCERR_INVRSCRC_EN_OFFSET (4) + #define RTL8373_MACSEC_TXLINE_CFG3_PORT4_TXLINE_CRCERR_INVRSCRC_EN_MASK (0x1 << RTL8373_MACSEC_TXLINE_CFG3_PORT4_TXLINE_CRCERR_INVRSCRC_EN_OFFSET) + #define RTL8373_MACSEC_TXLINE_CFG3_PORT4_TXLINE_CLASSDROP_EN_OFFSET (0) + #define RTL8373_MACSEC_TXLINE_CFG3_PORT4_TXLINE_CLASSDROP_EN_MASK (0x1 << RTL8373_MACSEC_TXLINE_CFG3_PORT4_TXLINE_CLASSDROP_EN_OFFSET) + +#define RTL8373_MACSEC_TXLINE_CFG5_PORT4_ADDR (0xC238) + #define RTL8373_MACSEC_TXLINE_CFG5_PORT4_TXLINE_AVG_IPG_OFFSET (16) + #define RTL8373_MACSEC_TXLINE_CFG5_PORT4_TXLINE_AVG_IPG_MASK (0xF << RTL8373_MACSEC_TXLINE_CFG5_PORT4_TXLINE_AVG_IPG_OFFSET) + #define RTL8373_MACSEC_TXLINE_CFG5_PORT4_TXLIEN_LPIEXIT_T_OFFSET (0) + #define RTL8373_MACSEC_TXLINE_CFG5_PORT4_TXLIEN_LPIEXIT_T_MASK (0x7FFF << RTL8373_MACSEC_TXLINE_CFG5_PORT4_TXLIEN_LPIEXIT_T_OFFSET) + +#define RTL8373_UNUSED_014C_PORT4_ADDR (0xC23C) + #define RTL8373_UNUSED_014C_PORT4_UNUSED_014C_PORT4_OFFSET (0) + #define RTL8373_UNUSED_014C_PORT4_UNUSED_014C_PORT4_MASK (0xFFFFFFFF << RTL8373_UNUSED_014C_PORT4_UNUSED_014C_PORT4_OFFSET) + +#define RTL8373_UNUSED_0150_PORT4_ADDR (0xC240) + #define RTL8373_UNUSED_0150_PORT4_UNUSED_0150_PORT4_OFFSET (0) + #define RTL8373_UNUSED_0150_PORT4_UNUSED_0150_PORT4_MASK (0xFFFFFFFF << RTL8373_UNUSED_0150_PORT4_UNUSED_0150_PORT4_OFFSET) + +#define RTL8373_UNUSED_0154_PORT4_ADDR (0xC244) + #define RTL8373_UNUSED_0154_PORT4_UNUSED_0154_PORT4_OFFSET (0) + #define RTL8373_UNUSED_0154_PORT4_UNUSED_0154_PORT4_MASK (0xFFFFFFFF << RTL8373_UNUSED_0154_PORT4_UNUSED_0154_PORT4_OFFSET) + +#define RTL8373_UNUSED_0158_PORT4_ADDR (0xC248) + #define RTL8373_UNUSED_0158_PORT4_UNUSED_0158_PORT4_OFFSET (0) + #define RTL8373_UNUSED_0158_PORT4_UNUSED_0158_PORT4_MASK (0xFFFFFFFF << RTL8373_UNUSED_0158_PORT4_UNUSED_0158_PORT4_OFFSET) + +#define RTL8373_UNUSED_015C_PORT4_ADDR (0xC24C) + #define RTL8373_UNUSED_015C_PORT4_UNUSED_015C_PORT4_OFFSET (0) + #define RTL8373_UNUSED_015C_PORT4_UNUSED_015C_PORT4_MASK (0xFFFFFFFF << RTL8373_UNUSED_015C_PORT4_UNUSED_015C_PORT4_OFFSET) + +#define RTL8373_UNUSED_0160_PORT4_ADDR (0xC250) + #define RTL8373_UNUSED_0160_PORT4_UNUSED_0160_PORT4_OFFSET (0) + #define RTL8373_UNUSED_0160_PORT4_UNUSED_0160_PORT4_MASK (0xFFFFFFFF << RTL8373_UNUSED_0160_PORT4_UNUSED_0160_PORT4_OFFSET) + +#define RTL8373_UNUSED_0164_PORT4_ADDR (0xC254) + #define RTL8373_UNUSED_0164_PORT4_UNUSED_0164_PORT4_OFFSET (0) + #define RTL8373_UNUSED_0164_PORT4_UNUSED_0164_PORT4_MASK (0xFFFFFFFF << RTL8373_UNUSED_0164_PORT4_UNUSED_0164_PORT4_OFFSET) + +#define RTL8373_UNUSED_0168_PORT4_ADDR (0xC258) + #define RTL8373_UNUSED_0168_PORT4_UNUSED_0168_PORT4_OFFSET (0) + #define RTL8373_UNUSED_0168_PORT4_UNUSED_0168_PORT4_MASK (0xFFFFFFFF << RTL8373_UNUSED_0168_PORT4_UNUSED_0168_PORT4_OFFSET) + +#define RTL8373_UNUSED_016C_PORT4_ADDR (0xC25C) + #define RTL8373_UNUSED_016C_PORT4_UNUSED_016C_PORT4_OFFSET (0) + #define RTL8373_UNUSED_016C_PORT4_UNUSED_016C_PORT4_MASK (0xFFFFFFFF << RTL8373_UNUSED_016C_PORT4_UNUSED_016C_PORT4_OFFSET) + +#define RTL8373_UNUSED_0170_PORT4_ADDR (0xC260) + #define RTL8373_UNUSED_0170_PORT4_UNUSED_0170_PORT4_OFFSET (0) + #define RTL8373_UNUSED_0170_PORT4_UNUSED_0170_PORT4_MASK (0xFFFFFFFF << RTL8373_UNUSED_0170_PORT4_UNUSED_0170_PORT4_OFFSET) + +#define RTL8373_UNUSED_0174_PORT4_ADDR (0xC264) + #define RTL8373_UNUSED_0174_PORT4_UNUSED_0174_PORT4_OFFSET (0) + #define RTL8373_UNUSED_0174_PORT4_UNUSED_0174_PORT4_MASK (0xFFFFFFFF << RTL8373_UNUSED_0174_PORT4_UNUSED_0174_PORT4_OFFSET) + +#define RTL8373_UNUSED_0178_PORT4_ADDR (0xC268) + #define RTL8373_UNUSED_0178_PORT4_UNUSED_0178_PORT4_OFFSET (0) + #define RTL8373_UNUSED_0178_PORT4_UNUSED_0178_PORT4_MASK (0xFFFFFFFF << RTL8373_UNUSED_0178_PORT4_UNUSED_0178_PORT4_OFFSET) + +#define RTL8373_UNUSED_017C_PORT4_ADDR (0xC26C) + #define RTL8373_UNUSED_017C_PORT4_UNUSED_017C_PORT4_OFFSET (0) + #define RTL8373_UNUSED_017C_PORT4_UNUSED_017C_PORT4_MASK (0xFFFFFFFF << RTL8373_UNUSED_017C_PORT4_UNUSED_017C_PORT4_OFFSET) + +#define RTL8373_MACSEC_RXLINE_CFG1_PORT4_ADDR (0xC270) + #define RTL8373_MACSEC_RXLINE_CFG1_PORT4_RXLINE_XGMINIFG_OFFSET (16) + #define RTL8373_MACSEC_RXLINE_CFG1_PORT4_RXLINE_XGMINIFG_MASK (0x1F << RTL8373_MACSEC_RXLINE_CFG1_PORT4_RXLINE_XGMINIFG_OFFSET) + #define RTL8373_MACSEC_RXLINE_CFG1_PORT4_RXLINE_MINIPG_OFFSET (8) + #define RTL8373_MACSEC_RXLINE_CFG1_PORT4_RXLINE_MINIPG_MASK (0xF << RTL8373_MACSEC_RXLINE_CFG1_PORT4_RXLINE_MINIPG_OFFSET) + #define RTL8373_MACSEC_RXLINE_CFG1_PORT4_RXLINE_PMBNUM_OFFSET (0) + #define RTL8373_MACSEC_RXLINE_CFG1_PORT4_RXLINE_PMBNUM_MASK (0x7 << RTL8373_MACSEC_RXLINE_CFG1_PORT4_RXLINE_PMBNUM_OFFSET) + +#define RTL8373_UNUSED_0184_PORT4_ADDR (0xC274) + #define RTL8373_UNUSED_0184_PORT4_UNUSED_0184_PORT4_OFFSET (0) + #define RTL8373_UNUSED_0184_PORT4_UNUSED_0184_PORT4_MASK (0xFFFFFFFF << RTL8373_UNUSED_0184_PORT4_UNUSED_0184_PORT4_OFFSET) + +#define RTL8373_UNUSED_0188_PORT4_ADDR (0xC278) + #define RTL8373_UNUSED_0188_PORT4_UNUSED_0188_PORT4_OFFSET (0) + #define RTL8373_UNUSED_0188_PORT4_UNUSED_0188_PORT4_MASK (0xFFFFFFFF << RTL8373_UNUSED_0188_PORT4_UNUSED_0188_PORT4_OFFSET) + +#define RTL8373_UNUSED_018C_PORT4_ADDR (0xC27C) + #define RTL8373_UNUSED_018C_PORT4_UNUSED_018C_PORT4_OFFSET (0) + #define RTL8373_UNUSED_018C_PORT4_UNUSED_018C_PORT4_MASK (0xFFFFFFFF << RTL8373_UNUSED_018C_PORT4_UNUSED_018C_PORT4_OFFSET) + +#define RTL8373_UNUSED_0190_PORT4_ADDR (0xC280) + #define RTL8373_UNUSED_0190_PORT4_UNUSED_0190_PORT4_OFFSET (0) + #define RTL8373_UNUSED_0190_PORT4_UNUSED_0190_PORT4_MASK (0xFFFFFFFF << RTL8373_UNUSED_0190_PORT4_UNUSED_0190_PORT4_OFFSET) + +#define RTL8373_UNUSED_0194_PORT4_ADDR (0xC284) + #define RTL8373_UNUSED_0194_PORT4_UNUSED_0194_PORT4_OFFSET (0) + #define RTL8373_UNUSED_0194_PORT4_UNUSED_0194_PORT4_MASK (0xFFFFFFFF << RTL8373_UNUSED_0194_PORT4_UNUSED_0194_PORT4_OFFSET) + +#define RTL8373_UNUSED_0198_PORT4_ADDR (0xC288) + #define RTL8373_UNUSED_0198_PORT4_UNUSED_0198_PORT4_OFFSET (0) + #define RTL8373_UNUSED_0198_PORT4_UNUSED_0198_PORT4_MASK (0xFFFFFFFF << RTL8373_UNUSED_0198_PORT4_UNUSED_0198_PORT4_OFFSET) + +#define RTL8373_UNUSED_019C_PORT4_ADDR (0xC28C) + #define RTL8373_UNUSED_019C_PORT4_UNUSED_019C_PORT4_OFFSET (0) + #define RTL8373_UNUSED_019C_PORT4_UNUSED_019C_PORT4_MASK (0xFFFFFFFF << RTL8373_UNUSED_019C_PORT4_UNUSED_019C_PORT4_OFFSET) + +#define RTL8373_UNUSED_01A0_PORT4_ADDR (0xC290) + #define RTL8373_UNUSED_01A0_PORT4_UNUSED_01A0_PORT4_OFFSET (0) + #define RTL8373_UNUSED_01A0_PORT4_UNUSED_01A0_PORT4_MASK (0xFFFFFFFF << RTL8373_UNUSED_01A0_PORT4_UNUSED_01A0_PORT4_OFFSET) + +#define RTL8373_UNUSED_01A4_PORT4_ADDR (0xC294) + #define RTL8373_UNUSED_01A4_PORT4_UNUSED_01A4_PORT4_OFFSET (0) + #define RTL8373_UNUSED_01A4_PORT4_UNUSED_01A4_PORT4_MASK (0xFFFFFFFF << RTL8373_UNUSED_01A4_PORT4_UNUSED_01A4_PORT4_OFFSET) + +#define RTL8373_UNUSED_01A8_PORT4_ADDR (0xC298) + #define RTL8373_UNUSED_01A8_PORT4_UNUSED_01A8_PORT4_OFFSET (0) + #define RTL8373_UNUSED_01A8_PORT4_UNUSED_01A8_PORT4_MASK (0xFFFFFFFF << RTL8373_UNUSED_01A8_PORT4_UNUSED_01A8_PORT4_OFFSET) + +#define RTL8373_UNUSED_01AC_PORT4_ADDR (0xC29C) + #define RTL8373_UNUSED_01AC_PORT4_UNUSED_01AC_PORT4_OFFSET (0) + #define RTL8373_UNUSED_01AC_PORT4_UNUSED_01AC_PORT4_MASK (0xFFFFFFFF << RTL8373_UNUSED_01AC_PORT4_UNUSED_01AC_PORT4_OFFSET) + +#define RTL8373_UNUSED_01B0_PORT4_ADDR (0xC2A0) + #define RTL8373_UNUSED_01B0_PORT4_UNUSED_01B0_PORT4_OFFSET (0) + #define RTL8373_UNUSED_01B0_PORT4_UNUSED_01B0_PORT4_MASK (0xFFFFFFFF << RTL8373_UNUSED_01B0_PORT4_UNUSED_01B0_PORT4_OFFSET) + +#define RTL8373_UNUSED_01B4_PORT4_ADDR (0xC2A4) + #define RTL8373_UNUSED_01B4_PORT4_UNUSED_01B4_PORT4_OFFSET (0) + #define RTL8373_UNUSED_01B4_PORT4_UNUSED_01B4_PORT4_MASK (0xFFFFFFFF << RTL8373_UNUSED_01B4_PORT4_UNUSED_01B4_PORT4_OFFSET) + +#define RTL8373_UNUSED_01B8_PORT4_ADDR (0xC2A8) + #define RTL8373_UNUSED_01B8_PORT4_UNUSED_01B8_PORT4_OFFSET (0) + #define RTL8373_UNUSED_01B8_PORT4_UNUSED_01B8_PORT4_MASK (0xFFFFFFFF << RTL8373_UNUSED_01B8_PORT4_UNUSED_01B8_PORT4_OFFSET) + +#define RTL8373_UNUSED_01BC_PORT4_ADDR (0xC2AC) + #define RTL8373_UNUSED_01BC_PORT4_UNUSED_01BC_PORT4_OFFSET (0) + #define RTL8373_UNUSED_01BC_PORT4_UNUSED_01BC_PORT4_MASK (0xFFFFFFFF << RTL8373_UNUSED_01BC_PORT4_UNUSED_01BC_PORT4_OFFSET) + +#define RTL8373_MACSEC_RXSYS_CFG1_PORT4_ADDR (0xC2B0) + #define RTL8373_MACSEC_RXSYS_CFG1_PORT4_RXSYS_WAIT_T_OFFSET (16) + #define RTL8373_MACSEC_RXSYS_CFG1_PORT4_RXSYS_WAIT_T_MASK (0xFF << RTL8373_MACSEC_RXSYS_CFG1_PORT4_RXSYS_WAIT_T_OFFSET) + #define RTL8373_MACSEC_RXSYS_CFG1_PORT4_RXSYS_MINIPG_OFFSET (8) + #define RTL8373_MACSEC_RXSYS_CFG1_PORT4_RXSYS_MINIPG_MASK (0xFF << RTL8373_MACSEC_RXSYS_CFG1_PORT4_RXSYS_MINIPG_OFFSET) + #define RTL8373_MACSEC_RXSYS_CFG1_PORT4_RXSYS_PMBNUM_OFFSET (0) + #define RTL8373_MACSEC_RXSYS_CFG1_PORT4_RXSYS_PMBNUM_MASK (0xF << RTL8373_MACSEC_RXSYS_CFG1_PORT4_RXSYS_PMBNUM_OFFSET) + +#define RTL8373_MACSEC_RXSYS_CFG3_PORT4_ADDR (0xC2B4) + #define RTL8373_MACSEC_RXSYS_CFG3_PORT4_RXSYS_OUTERVLAN1_OFFSET (16) + #define RTL8373_MACSEC_RXSYS_CFG3_PORT4_RXSYS_OUTERVLAN1_MASK (0xFFFF << RTL8373_MACSEC_RXSYS_CFG3_PORT4_RXSYS_OUTERVLAN1_OFFSET) + #define RTL8373_MACSEC_RXSYS_CFG3_PORT4_RXSYS_PAD_VLAN_EN_OFFSET (14) + #define RTL8373_MACSEC_RXSYS_CFG3_PORT4_RXSYS_PAD_VLAN_EN_MASK (0x1 << RTL8373_MACSEC_RXSYS_CFG3_PORT4_RXSYS_PAD_VLAN_EN_OFFSET) + #define RTL8373_MACSEC_RXSYS_CFG3_PORT4_RXSYS_PAD_LINESRT_EN_OFFSET (13) + #define RTL8373_MACSEC_RXSYS_CFG3_PORT4_RXSYS_PAD_LINESRT_EN_MASK (0x1 << RTL8373_MACSEC_RXSYS_CFG3_PORT4_RXSYS_PAD_LINESRT_EN_OFFSET) + #define RTL8373_MACSEC_RXSYS_CFG3_PORT4_RXSYS_PAD_DECRYPTSRT_EN_OFFSET (12) + #define RTL8373_MACSEC_RXSYS_CFG3_PORT4_RXSYS_PAD_DECRYPTSRT_EN_MASK (0x1 << RTL8373_MACSEC_RXSYS_CFG3_PORT4_RXSYS_PAD_DECRYPTSRT_EN_OFFSET) + #define RTL8373_MACSEC_RXSYS_CFG3_PORT4_RXSYS_PKTERR_INVRSCRC_EN_OFFSET (8) + #define RTL8373_MACSEC_RXSYS_CFG3_PORT4_RXSYS_PKTERR_INVRSCRC_EN_MASK (0x1 << RTL8373_MACSEC_RXSYS_CFG3_PORT4_RXSYS_PKTERR_INVRSCRC_EN_OFFSET) + #define RTL8373_MACSEC_RXSYS_CFG3_PORT4_RXSYS_GMIIER_INVRSCRC_EN_OFFSET (5) + #define RTL8373_MACSEC_RXSYS_CFG3_PORT4_RXSYS_GMIIER_INVRSCRC_EN_MASK (0x1 << RTL8373_MACSEC_RXSYS_CFG3_PORT4_RXSYS_GMIIER_INVRSCRC_EN_OFFSET) + #define RTL8373_MACSEC_RXSYS_CFG3_PORT4_RXSYS_CRCERR_INVRSCRC_EN_OFFSET (4) + #define RTL8373_MACSEC_RXSYS_CFG3_PORT4_RXSYS_CRCERR_INVRSCRC_EN_MASK (0x1 << RTL8373_MACSEC_RXSYS_CFG3_PORT4_RXSYS_CRCERR_INVRSCRC_EN_OFFSET) + #define RTL8373_MACSEC_RXSYS_CFG3_PORT4_RXSYS_CLASSDROP_EN_OFFSET (0) + #define RTL8373_MACSEC_RXSYS_CFG3_PORT4_RXSYS_CLASSDROP_EN_MASK (0x1 << RTL8373_MACSEC_RXSYS_CFG3_PORT4_RXSYS_CLASSDROP_EN_OFFSET) + +#define RTL8373_MACSEC_RXSYS_OUTERVLAN2_PORT4_ADDR (0xC2B8) + #define RTL8373_MACSEC_RXSYS_OUTERVLAN2_PORT4_RXSYS_OUTERVLAN3_OFFSET (16) + #define RTL8373_MACSEC_RXSYS_OUTERVLAN2_PORT4_RXSYS_OUTERVLAN3_MASK (0xFFFF << RTL8373_MACSEC_RXSYS_OUTERVLAN2_PORT4_RXSYS_OUTERVLAN3_OFFSET) + #define RTL8373_MACSEC_RXSYS_OUTERVLAN2_PORT4_RXSYS_OUTERVLAN2_OFFSET (0) + #define RTL8373_MACSEC_RXSYS_OUTERVLAN2_PORT4_RXSYS_OUTERVLAN2_MASK (0xFFFF << RTL8373_MACSEC_RXSYS_OUTERVLAN2_PORT4_RXSYS_OUTERVLAN2_OFFSET) + +#define RTL8373_MACSEC_RXSYS_OUTERVLAN4_PORT4_ADDR (0xC2BC) + #define RTL8373_MACSEC_RXSYS_OUTERVLAN4_PORT4_RXSYS_INNERVLAN1_OFFSET (16) + #define RTL8373_MACSEC_RXSYS_OUTERVLAN4_PORT4_RXSYS_INNERVLAN1_MASK (0xFFFF << RTL8373_MACSEC_RXSYS_OUTERVLAN4_PORT4_RXSYS_INNERVLAN1_OFFSET) + #define RTL8373_MACSEC_RXSYS_OUTERVLAN4_PORT4_RXSYS_OUTERVLAN4_OFFSET (0) + #define RTL8373_MACSEC_RXSYS_OUTERVLAN4_PORT4_RXSYS_OUTERVLAN4_MASK (0xFFFF << RTL8373_MACSEC_RXSYS_OUTERVLAN4_PORT4_RXSYS_OUTERVLAN4_OFFSET) + +#define RTL8373_MACSEC_RXSYS_INNERVLAN2_PORT4_ADDR (0xC2C0) + #define RTL8373_MACSEC_RXSYS_INNERVLAN2_PORT4_RXSYS_INNERVLAN3_OFFSET (16) + #define RTL8373_MACSEC_RXSYS_INNERVLAN2_PORT4_RXSYS_INNERVLAN3_MASK (0xFFFF << RTL8373_MACSEC_RXSYS_INNERVLAN2_PORT4_RXSYS_INNERVLAN3_OFFSET) + #define RTL8373_MACSEC_RXSYS_INNERVLAN2_PORT4_RXSYS_INNERVLAN2_OFFSET (0) + #define RTL8373_MACSEC_RXSYS_INNERVLAN2_PORT4_RXSYS_INNERVLAN2_MASK (0xFFFF << RTL8373_MACSEC_RXSYS_INNERVLAN2_PORT4_RXSYS_INNERVLAN2_OFFSET) + +#define RTL8373_MACSEC_RXSYS_INNERVLAN4_PORT4_ADDR (0xC2C4) + #define RTL8373_MACSEC_RXSYS_INNERVLAN4_PORT4_RXSYS_INNERVLAN5_OFFSET (16) + #define RTL8373_MACSEC_RXSYS_INNERVLAN4_PORT4_RXSYS_INNERVLAN5_MASK (0xFFFF << RTL8373_MACSEC_RXSYS_INNERVLAN4_PORT4_RXSYS_INNERVLAN5_OFFSET) + #define RTL8373_MACSEC_RXSYS_INNERVLAN4_PORT4_RXSYS_INNERVLAN4_OFFSET (0) + #define RTL8373_MACSEC_RXSYS_INNERVLAN4_PORT4_RXSYS_INNERVLAN4_MASK (0xFFFF << RTL8373_MACSEC_RXSYS_INNERVLAN4_PORT4_RXSYS_INNERVLAN4_OFFSET) + +#define RTL8373_MACSEC_RXSYS_INNERVLAN6_PORT4_ADDR (0xC2C8) + #define RTL8373_MACSEC_RXSYS_INNERVLAN6_PORT4_RXSYS_INNERVLAN7_OFFSET (16) + #define RTL8373_MACSEC_RXSYS_INNERVLAN6_PORT4_RXSYS_INNERVLAN7_MASK (0xFFFF << RTL8373_MACSEC_RXSYS_INNERVLAN6_PORT4_RXSYS_INNERVLAN7_OFFSET) + #define RTL8373_MACSEC_RXSYS_INNERVLAN6_PORT4_RXSYS_INNERVLAN6_OFFSET (0) + #define RTL8373_MACSEC_RXSYS_INNERVLAN6_PORT4_RXSYS_INNERVLAN6_MASK (0xFFFF << RTL8373_MACSEC_RXSYS_INNERVLAN6_PORT4_RXSYS_INNERVLAN6_OFFSET) + +#define RTL8373_MACSEC_RXSYS_CFG4_PORT4_ADDR (0xC2CC) + #define RTL8373_MACSEC_RXSYS_CFG4_PORT4_RXSYS_LPIEXIT_T_OFFSET (16) + #define RTL8373_MACSEC_RXSYS_CFG4_PORT4_RXSYS_LPIEXIT_T_MASK (0x7FFF << RTL8373_MACSEC_RXSYS_CFG4_PORT4_RXSYS_LPIEXIT_T_OFFSET) + #define RTL8373_MACSEC_RXSYS_CFG4_PORT4_RXSYS_FIFO_FTUNE_OFFSET (8) + #define RTL8373_MACSEC_RXSYS_CFG4_PORT4_RXSYS_FIFO_FTUNE_MASK (0xFF << RTL8373_MACSEC_RXSYS_CFG4_PORT4_RXSYS_FIFO_FTUNE_OFFSET) + #define RTL8373_MACSEC_RXSYS_CFG4_PORT4_RXSYS_FIFO_TSHD_OFFSET (0) + #define RTL8373_MACSEC_RXSYS_CFG4_PORT4_RXSYS_FIFO_TSHD_MASK (0xFF << RTL8373_MACSEC_RXSYS_CFG4_PORT4_RXSYS_FIFO_TSHD_OFFSET) + +#define RTL8373_MACSEC_RXSYS_CFG6_PORT4_ADDR (0xC2D0) + #define RTL8373_MACSEC_RXSYS_CFG6_PORT4_RXSYS_AVG_IPG_OFFSET (0) + #define RTL8373_MACSEC_RXSYS_CFG6_PORT4_RXSYS_AVG_IPG_MASK (0xF << RTL8373_MACSEC_RXSYS_CFG6_PORT4_RXSYS_AVG_IPG_OFFSET) + +#define RTL8373_MACSEC_REG_GLB_SET1_PORT5_ADDR (0xC8F0) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT5_RX_GATING_OFFSET (31) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT5_RX_GATING_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT5_RX_GATING_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT5_TX_GATING_OFFSET (30) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT5_TX_GATING_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT5_TX_GATING_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT5_DBG_EN_OFFSET (29) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT5_DBG_EN_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT5_DBG_EN_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT5_DBG_SEL_OFFSET (24) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT5_DBG_SEL_MASK (0x1F << RTL8373_MACSEC_REG_GLB_SET1_PORT5_DBG_SEL_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT5_DBG_SPD_SEL_OFFSET (23) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT5_DBG_SPD_SEL_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT5_DBG_SPD_SEL_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT5_RX_G_IOSAMEPMB_OFFSET (22) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT5_RX_G_IOSAMEPMB_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT5_RX_G_IOSAMEPMB_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT5_TX_G_IOSAMEPMB_OFFSET (21) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT5_TX_G_IOSAMEPMB_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT5_TX_G_IOSAMEPMB_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT5_MIBCNT_MODE_OFFSET (20) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT5_MIBCNT_MODE_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT5_MIBCNT_MODE_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT5_RX_XGDIC_EN_OFFSET (18) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT5_RX_XGDIC_EN_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT5_RX_XGDIC_EN_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT5_TX_XGDIC_EN_OFFSET (17) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT5_TX_XGDIC_EN_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT5_TX_XGDIC_EN_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT5_MIBCNT_SWRST_N_OFFSET (16) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT5_MIBCNT_SWRST_N_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT5_MIBCNT_SWRST_N_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT5_PTPBYPASS_EN_OFFSET (14) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT5_PTPBYPASS_EN_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT5_PTPBYPASS_EN_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT5_SYSLPBK_EN_OFFSET (13) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT5_SYSLPBK_EN_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT5_SYSLPBK_EN_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT5_PHY2MAC_EN_OFFSET (12) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT5_PHY2MAC_EN_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT5_PHY2MAC_EN_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT5_RX_IPRST_N_OFFSET (11) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT5_RX_IPRST_N_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT5_RX_IPRST_N_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT5_RX_IPBYPASS_EN_OFFSET (10) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT5_RX_IPBYPASS_EN_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT5_RX_IPBYPASS_EN_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT5_RX_MACSECBYPASS_EN_OFFSET (9) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT5_RX_MACSECBYPASS_EN_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT5_RX_MACSECBYPASS_EN_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT5_RX_SWRST_EN_OFFSET (8) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT5_RX_SWRST_EN_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT5_RX_SWRST_EN_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT5_LINELPBK_EN_OFFSET (5) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT5_LINELPBK_EN_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT5_LINELPBK_EN_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT5_MAC2PHY_EN_OFFSET (4) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT5_MAC2PHY_EN_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT5_MAC2PHY_EN_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT5_TX_IPRST_N_OFFSET (3) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT5_TX_IPRST_N_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT5_TX_IPRST_N_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT5_TX_IPBYPASS_EN_OFFSET (2) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT5_TX_IPBYPASS_EN_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT5_TX_IPBYPASS_EN_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT5_TX_MACSECBYPASS_EN_OFFSET (1) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT5_TX_MACSECBYPASS_EN_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT5_TX_MACSECBYPASS_EN_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT5_TX_SWRST_EN_OFFSET (0) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT5_TX_SWRST_EN_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT5_TX_SWRST_EN_OFFSET) + +#define RTL8373_MACSEC_REG_GLB_IMR_PORT5_ADDR (0xC8F4) + #define RTL8373_MACSEC_REG_GLB_IMR_PORT5_RX_IPILOCK_XG_IMR_OFFSET (11) + #define RTL8373_MACSEC_REG_GLB_IMR_PORT5_RX_IPILOCK_XG_IMR_MASK (0x1 << RTL8373_MACSEC_REG_GLB_IMR_PORT5_RX_IPILOCK_XG_IMR_OFFSET) + #define RTL8373_MACSEC_REG_GLB_IMR_PORT5_RX_IPILOCK_IMR_OFFSET (10) + #define RTL8373_MACSEC_REG_GLB_IMR_PORT5_RX_IPILOCK_IMR_MASK (0x1 << RTL8373_MACSEC_REG_GLB_IMR_PORT5_RX_IPILOCK_IMR_OFFSET) + #define RTL8373_MACSEC_REG_GLB_IMR_PORT5_RX_IPISECFAIL_IMR_OFFSET (9) + #define RTL8373_MACSEC_REG_GLB_IMR_PORT5_RX_IPISECFAIL_IMR_MASK (0x1 << RTL8373_MACSEC_REG_GLB_IMR_PORT5_RX_IPISECFAIL_IMR_OFFSET) + #define RTL8373_MACSEC_REG_GLB_IMR_PORT5_RX_IPI_GLB_IMR_OFFSET (8) + #define RTL8373_MACSEC_REG_GLB_IMR_PORT5_RX_IPI_GLB_IMR_MASK (0x1 << RTL8373_MACSEC_REG_GLB_IMR_PORT5_RX_IPI_GLB_IMR_OFFSET) + #define RTL8373_MACSEC_REG_GLB_IMR_PORT5_TX_IPELOCK_XG_IMR_OFFSET (3) + #define RTL8373_MACSEC_REG_GLB_IMR_PORT5_TX_IPELOCK_XG_IMR_MASK (0x1 << RTL8373_MACSEC_REG_GLB_IMR_PORT5_TX_IPELOCK_XG_IMR_OFFSET) + #define RTL8373_MACSEC_REG_GLB_IMR_PORT5_TX_IPELOCK_IMR_OFFSET (2) + #define RTL8373_MACSEC_REG_GLB_IMR_PORT5_TX_IPELOCK_IMR_MASK (0x1 << RTL8373_MACSEC_REG_GLB_IMR_PORT5_TX_IPELOCK_IMR_OFFSET) + #define RTL8373_MACSEC_REG_GLB_IMR_PORT5_TX_IPESECFAIL_IMR_OFFSET (1) + #define RTL8373_MACSEC_REG_GLB_IMR_PORT5_TX_IPESECFAIL_IMR_MASK (0x1 << RTL8373_MACSEC_REG_GLB_IMR_PORT5_TX_IPESECFAIL_IMR_OFFSET) + #define RTL8373_MACSEC_REG_GLB_IMR_PORT5_TX_IPE_GLB_IMR_OFFSET (0) + #define RTL8373_MACSEC_REG_GLB_IMR_PORT5_TX_IPE_GLB_IMR_MASK (0x1 << RTL8373_MACSEC_REG_GLB_IMR_PORT5_TX_IPE_GLB_IMR_OFFSET) + +#define RTL8373_MACSEC_REG_GLB_ISR_PORT5_ADDR (0xC8F8) + #define RTL8373_MACSEC_REG_GLB_ISR_PORT5_RX_IPILOCK_XG_ISR_OFFSET (11) + #define RTL8373_MACSEC_REG_GLB_ISR_PORT5_RX_IPILOCK_XG_ISR_MASK (0x1 << RTL8373_MACSEC_REG_GLB_ISR_PORT5_RX_IPILOCK_XG_ISR_OFFSET) + #define RTL8373_MACSEC_REG_GLB_ISR_PORT5_RX_IPILOCK_ISR_OFFSET (10) + #define RTL8373_MACSEC_REG_GLB_ISR_PORT5_RX_IPILOCK_ISR_MASK (0x1 << RTL8373_MACSEC_REG_GLB_ISR_PORT5_RX_IPILOCK_ISR_OFFSET) + #define RTL8373_MACSEC_REG_GLB_ISR_PORT5_RX_IPISECFAIL_ISR_OFFSET (9) + #define RTL8373_MACSEC_REG_GLB_ISR_PORT5_RX_IPISECFAIL_ISR_MASK (0x1 << RTL8373_MACSEC_REG_GLB_ISR_PORT5_RX_IPISECFAIL_ISR_OFFSET) + #define RTL8373_MACSEC_REG_GLB_ISR_PORT5_RX_IPI_GLB_ISR_OFFSET (8) + #define RTL8373_MACSEC_REG_GLB_ISR_PORT5_RX_IPI_GLB_ISR_MASK (0x1 << RTL8373_MACSEC_REG_GLB_ISR_PORT5_RX_IPI_GLB_ISR_OFFSET) + #define RTL8373_MACSEC_REG_GLB_ISR_PORT5_TX_IPELOCK_XG_ISR_OFFSET (3) + #define RTL8373_MACSEC_REG_GLB_ISR_PORT5_TX_IPELOCK_XG_ISR_MASK (0x1 << RTL8373_MACSEC_REG_GLB_ISR_PORT5_TX_IPELOCK_XG_ISR_OFFSET) + #define RTL8373_MACSEC_REG_GLB_ISR_PORT5_TX_IPELOCK_ISR_OFFSET (2) + #define RTL8373_MACSEC_REG_GLB_ISR_PORT5_TX_IPELOCK_ISR_MASK (0x1 << RTL8373_MACSEC_REG_GLB_ISR_PORT5_TX_IPELOCK_ISR_OFFSET) + #define RTL8373_MACSEC_REG_GLB_ISR_PORT5_TX_IPESECFAIL_ISR_OFFSET (1) + #define RTL8373_MACSEC_REG_GLB_ISR_PORT5_TX_IPESECFAIL_ISR_MASK (0x1 << RTL8373_MACSEC_REG_GLB_ISR_PORT5_TX_IPESECFAIL_ISR_OFFSET) + #define RTL8373_MACSEC_REG_GLB_ISR_PORT5_TX_IPE_GLB_ISR_OFFSET (0) + #define RTL8373_MACSEC_REG_GLB_ISR_PORT5_TX_IPE_GLB_ISR_MASK (0x1 << RTL8373_MACSEC_REG_GLB_ISR_PORT5_TX_IPE_GLB_ISR_OFFSET) + +#define RTL8373_UNUSED_000C_PORT5_ADDR (0xC8FC) + #define RTL8373_UNUSED_000C_PORT5_UNUSED_000C_PORT5_OFFSET (0) + #define RTL8373_UNUSED_000C_PORT5_UNUSED_000C_PORT5_MASK (0xFFFFFFFF << RTL8373_UNUSED_000C_PORT5_UNUSED_000C_PORT5_OFFSET) + +#define RTL8373_MACSEC_PM_CTRL_PORT5_ADDR (0xC900) + #define RTL8373_MACSEC_PM_CTRL_PORT5_MACSEC_RX_ICG_EN_OFFSET (1) + #define RTL8373_MACSEC_PM_CTRL_PORT5_MACSEC_RX_ICG_EN_MASK (0x1 << RTL8373_MACSEC_PM_CTRL_PORT5_MACSEC_RX_ICG_EN_OFFSET) + #define RTL8373_MACSEC_PM_CTRL_PORT5_MACSEC_TX_ICG_EN_OFFSET (0) + #define RTL8373_MACSEC_PM_CTRL_PORT5_MACSEC_TX_ICG_EN_MASK (0x1 << RTL8373_MACSEC_PM_CTRL_PORT5_MACSEC_TX_ICG_EN_OFFSET) + +#define RTL8373_MACSEC_REG_GLB_MASK_PORT5_ADDR (0xC904) + #define RTL8373_MACSEC_REG_GLB_MASK_PORT5_RX_MTU_OFFSET (24) + #define RTL8373_MACSEC_REG_GLB_MASK_PORT5_RX_MTU_MASK (0x3F << RTL8373_MACSEC_REG_GLB_MASK_PORT5_RX_MTU_OFFSET) + #define RTL8373_MACSEC_REG_GLB_MASK_PORT5_TX_MTU_OFFSET (16) + #define RTL8373_MACSEC_REG_GLB_MASK_PORT5_TX_MTU_MASK (0x3F << RTL8373_MACSEC_REG_GLB_MASK_PORT5_TX_MTU_OFFSET) + #define RTL8373_MACSEC_REG_GLB_MASK_PORT5_RX_XGMASK_OFFSET (12) + #define RTL8373_MACSEC_REG_GLB_MASK_PORT5_RX_XGMASK_MASK (0x1 << RTL8373_MACSEC_REG_GLB_MASK_PORT5_RX_XGMASK_OFFSET) + #define RTL8373_MACSEC_REG_GLB_MASK_PORT5_RXDV_GMASK_OFFSET (8) + #define RTL8373_MACSEC_REG_GLB_MASK_PORT5_RXDV_GMASK_MASK (0x1 << RTL8373_MACSEC_REG_GLB_MASK_PORT5_RXDV_GMASK_OFFSET) + #define RTL8373_MACSEC_REG_GLB_MASK_PORT5_TX_XGMASK_OFFSET (4) + #define RTL8373_MACSEC_REG_GLB_MASK_PORT5_TX_XGMASK_MASK (0x1 << RTL8373_MACSEC_REG_GLB_MASK_PORT5_TX_XGMASK_OFFSET) + #define RTL8373_MACSEC_REG_GLB_MASK_PORT5_TXEN_GMASK_OFFSET (0) + #define RTL8373_MACSEC_REG_GLB_MASK_PORT5_TXEN_GMASK_MASK (0x1 << RTL8373_MACSEC_REG_GLB_MASK_PORT5_TXEN_GMASK_OFFSET) + +#define RTL8373_MACSEC_REG_GLB_SET4_PORT5_ADDR (0xC908) + #define RTL8373_MACSEC_REG_GLB_SET4_PORT5_TXMSKDELAY_VAL_OFFSET (16) + #define RTL8373_MACSEC_REG_GLB_SET4_PORT5_TXMSKDELAY_VAL_MASK (0x7FFF << RTL8373_MACSEC_REG_GLB_SET4_PORT5_TXMSKDELAY_VAL_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET4_PORT5_RXMSKDELAY_VAL_OFFSET (0) + #define RTL8373_MACSEC_REG_GLB_SET4_PORT5_RXMSKDELAY_VAL_MASK (0x7FFF << RTL8373_MACSEC_REG_GLB_SET4_PORT5_RXMSKDELAY_VAL_OFFSET) + +#define RTL8373_MACSEC_REG_IP_PROBE_PORT5_ADDR (0xC90C) + #define RTL8373_MACSEC_REG_IP_PROBE_PORT5_PROBE_SEL_AE_OFFSET (8) + #define RTL8373_MACSEC_REG_IP_PROBE_PORT5_PROBE_SEL_AE_MASK (0xFF << RTL8373_MACSEC_REG_IP_PROBE_PORT5_PROBE_SEL_AE_OFFSET) + #define RTL8373_MACSEC_REG_IP_PROBE_PORT5_PROBE_SEL_AI_OFFSET (0) + #define RTL8373_MACSEC_REG_IP_PROBE_PORT5_PROBE_SEL_AI_MASK (0xFF << RTL8373_MACSEC_REG_IP_PROBE_PORT5_PROBE_SEL_AI_OFFSET) + +#define RTL8373_UNUSED_0020_PORT5_ADDR (0xC910) + #define RTL8373_UNUSED_0020_PORT5_UNUSED_0020_PORT5_OFFSET (0) + #define RTL8373_UNUSED_0020_PORT5_UNUSED_0020_PORT5_MASK (0xFFFFFFFF << RTL8373_UNUSED_0020_PORT5_UNUSED_0020_PORT5_OFFSET) + +#define RTL8373_UNUSED_0024_PORT5_ADDR (0xC914) + #define RTL8373_UNUSED_0024_PORT5_UNUSED_0024_PORT5_OFFSET (0) + #define RTL8373_UNUSED_0024_PORT5_UNUSED_0024_PORT5_MASK (0xFFFFFFFF << RTL8373_UNUSED_0024_PORT5_UNUSED_0024_PORT5_OFFSET) + +#define RTL8373_MACSEC_MBIST_SA_CTRL_PORT5_ADDR (0xC918) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT5_BIST_MODE_MACSEC_SA_AE_OFFSET (29) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT5_BIST_MODE_MACSEC_SA_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_CTRL_PORT5_BIST_MODE_MACSEC_SA_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT5_DRF_BIST_MODE_MACSEC_SA_AE_OFFSET (28) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT5_DRF_BIST_MODE_MACSEC_SA_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_CTRL_PORT5_DRF_BIST_MODE_MACSEC_SA_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT5_BIST_RSTN_MACSEC_SA_AE_OFFSET (27) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT5_BIST_RSTN_MACSEC_SA_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_CTRL_PORT5_BIST_RSTN_MACSEC_SA_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT5_BIST_LOOP_MODE_MACSEC_SA_AE_OFFSET (26) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT5_BIST_LOOP_MODE_MACSEC_SA_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_CTRL_PORT5_BIST_LOOP_MODE_MACSEC_SA_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT5_DYN_READ_EN_MACSEC_SA_AE_OFFSET (25) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT5_DYN_READ_EN_MACSEC_SA_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_CTRL_PORT5_DYN_READ_EN_MACSEC_SA_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT5_DRF_TESS_RESUME_MACSEC_SA_AE_OFFSET (24) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT5_DRF_TESS_RESUME_MACSEC_SA_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_CTRL_PORT5_DRF_TESS_RESUME_MACSEC_SA_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT5_BIST_MODE_MACSEC_SA_AI_OFFSET (23) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT5_BIST_MODE_MACSEC_SA_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_CTRL_PORT5_BIST_MODE_MACSEC_SA_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT5_DRF_BIST_MODE_MACSEC_SA_AI_OFFSET (22) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT5_DRF_BIST_MODE_MACSEC_SA_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_CTRL_PORT5_DRF_BIST_MODE_MACSEC_SA_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT5_BIST_RSTN_MACSEC_SA_AI_OFFSET (21) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT5_BIST_RSTN_MACSEC_SA_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_CTRL_PORT5_BIST_RSTN_MACSEC_SA_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT5_BIST_LOOP_MODE_MACSEC_SA_AI_OFFSET (20) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT5_BIST_LOOP_MODE_MACSEC_SA_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_CTRL_PORT5_BIST_LOOP_MODE_MACSEC_SA_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT5_DYN_READ_EN_MACSEC_SA_AI_OFFSET (19) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT5_DYN_READ_EN_MACSEC_SA_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_CTRL_PORT5_DYN_READ_EN_MACSEC_SA_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT5_DRF_TESS_RESUME_MACSEC_SA_AI_OFFSET (18) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT5_DRF_TESS_RESUME_MACSEC_SA_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_CTRL_PORT5_DRF_TESS_RESUME_MACSEC_SA_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT5_MACSEC_SA_AE_ICG_EN_OFFSET (17) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT5_MACSEC_SA_AE_ICG_EN_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_CTRL_PORT5_MACSEC_SA_AE_ICG_EN_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT5_MACSEC_SA_AI_ICG_EN_OFFSET (16) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT5_MACSEC_SA_AI_ICG_EN_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_CTRL_PORT5_MACSEC_SA_AI_ICG_EN_OFFSET) + +#define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_ADDR (0xC91C) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_DRF_START_PAUSE_MACSEC_SA_AE_OFFSET (27) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_DRF_START_PAUSE_MACSEC_SA_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_DRF_START_PAUSE_MACSEC_SA_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_BIST_DONE_MACSEC_SA_AE_OFFSET (26) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_BIST_DONE_MACSEC_SA_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_BIST_DONE_MACSEC_SA_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_DRF_BIST_DONE_MACSEC_SA_AE_OFFSET (25) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_DRF_BIST_DONE_MACSEC_SA_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_DRF_BIST_DONE_MACSEC_SA_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_DRF_START_PAUSE_MACSEC_SA_AI_OFFSET (24) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_DRF_START_PAUSE_MACSEC_SA_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_DRF_START_PAUSE_MACSEC_SA_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_BIST_DONE_MACSEC_SA_AI_OFFSET (23) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_BIST_DONE_MACSEC_SA_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_BIST_DONE_MACSEC_SA_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_DRF_BIST_DONE_MACSEC_SA_AI_OFFSET (22) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_DRF_BIST_DONE_MACSEC_SA_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_DRF_BIST_DONE_MACSEC_SA_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_DRF_START_PAUSE_MACSEC_STAT_AE_OFFSET (21) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_DRF_START_PAUSE_MACSEC_STAT_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_DRF_START_PAUSE_MACSEC_STAT_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_BIST_DONE_MACSEC_STAT_AE_OFFSET (20) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_BIST_DONE_MACSEC_STAT_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_BIST_DONE_MACSEC_STAT_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_DRF_BIST_DONE_MACSEC_STAT_AE_OFFSET (19) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_DRF_BIST_DONE_MACSEC_STAT_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_DRF_BIST_DONE_MACSEC_STAT_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_DRF_START_PAUSE_MACSEC_STAT_AI_OFFSET (18) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_DRF_START_PAUSE_MACSEC_STAT_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_DRF_START_PAUSE_MACSEC_STAT_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_BIST_DONE_MACSEC_STAT_AI_OFFSET (17) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_BIST_DONE_MACSEC_STAT_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_BIST_DONE_MACSEC_STAT_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_DRF_BIST_DONE_MACSEC_STAT_AI_OFFSET (16) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_DRF_BIST_DONE_MACSEC_STAT_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_DRF_BIST_DONE_MACSEC_STAT_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_BIST_MODE_MACSEC_STAT_AE_OFFSET (13) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_BIST_MODE_MACSEC_STAT_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_BIST_MODE_MACSEC_STAT_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_DRF_BIST_MODE_MACSEC_STAT_AE_OFFSET (12) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_DRF_BIST_MODE_MACSEC_STAT_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_DRF_BIST_MODE_MACSEC_STAT_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_BIST_RSTN_MACSEC_STAT_AE_OFFSET (11) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_BIST_RSTN_MACSEC_STAT_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_BIST_RSTN_MACSEC_STAT_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_BIST_LOOP_MODE_MACSEC_STAT_AE_OFFSET (10) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_BIST_LOOP_MODE_MACSEC_STAT_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_BIST_LOOP_MODE_MACSEC_STAT_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_DYN_READ_EN_MACSEC_STAT_AE_OFFSET (9) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_DYN_READ_EN_MACSEC_STAT_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_DYN_READ_EN_MACSEC_STAT_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_DRF_TESS_RESUME_MACSEC_STAT_AE_OFFSET (8) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_DRF_TESS_RESUME_MACSEC_STAT_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_DRF_TESS_RESUME_MACSEC_STAT_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_BIST_MODE_MACSEC_STAT_AI_OFFSET (7) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_BIST_MODE_MACSEC_STAT_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_BIST_MODE_MACSEC_STAT_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_DRF_BIST_MODE_MACSEC_STAT_AI_OFFSET (6) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_DRF_BIST_MODE_MACSEC_STAT_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_DRF_BIST_MODE_MACSEC_STAT_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_BIST_RSTN_MACSEC_STAT_AI_OFFSET (5) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_BIST_RSTN_MACSEC_STAT_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_BIST_RSTN_MACSEC_STAT_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_BIST_LOOP_MODE_MACSEC_STAT_AI_OFFSET (4) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_BIST_LOOP_MODE_MACSEC_STAT_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_BIST_LOOP_MODE_MACSEC_STAT_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_DYN_READ_EN_MACSEC_STAT_AI_OFFSET (3) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_DYN_READ_EN_MACSEC_STAT_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_DYN_READ_EN_MACSEC_STAT_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_DRF_TESS_RESUME_MACSEC_STAT_AI_OFFSET (2) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_DRF_TESS_RESUME_MACSEC_STAT_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_DRF_TESS_RESUME_MACSEC_STAT_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_MACSEC_STAT_AE_ICG_EN_OFFSET (1) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_MACSEC_STAT_AE_ICG_EN_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_MACSEC_STAT_AE_ICG_EN_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_MACSEC_STAT_AI_ICG_EN_OFFSET (0) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_MACSEC_STAT_AI_ICG_EN_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT5_MACSEC_STAT_AI_ICG_EN_OFFSET) + +#define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT5_ADDR (0xC920) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT5_MACSEC_SA_AI_DVSE_OFFSET (27) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT5_MACSEC_SA_AI_DVSE_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT5_MACSEC_SA_AI_DVSE_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT5_MACSEC_SA_AI_DVS_OFFSET (23) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT5_MACSEC_SA_AI_DVS_MASK (0xF << RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT5_MACSEC_SA_AI_DVS_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT5_MACSEC_SA_AI_LS_OFFSET (22) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT5_MACSEC_SA_AI_LS_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT5_MACSEC_SA_AI_LS_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT5_MACSEC_SA_AI_DS_OFFSET (21) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT5_MACSEC_SA_AI_DS_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT5_MACSEC_SA_AI_DS_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT5_MACSEC_SA_AI_SD_OFFSET (20) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT5_MACSEC_SA_AI_SD_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT5_MACSEC_SA_AI_SD_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT5_MACSEC_SA_AI3_TEST1_OFFSET (19) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT5_MACSEC_SA_AI3_TEST1_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT5_MACSEC_SA_AI3_TEST1_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT5_MACSEC_SA_AI2_TEST1_OFFSET (18) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT5_MACSEC_SA_AI2_TEST1_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT5_MACSEC_SA_AI2_TEST1_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT5_MACSEC_SA_AI1_TEST1_OFFSET (17) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT5_MACSEC_SA_AI1_TEST1_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT5_MACSEC_SA_AI1_TEST1_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT5_MACSEC_SA_AI0_TEST1_OFFSET (16) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT5_MACSEC_SA_AI0_TEST1_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT5_MACSEC_SA_AI0_TEST1_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT5_MACSEC_SA_AE_DVSE_OFFSET (11) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT5_MACSEC_SA_AE_DVSE_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT5_MACSEC_SA_AE_DVSE_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT5_MACSEC_SA_AE_DVS_OFFSET (7) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT5_MACSEC_SA_AE_DVS_MASK (0xF << RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT5_MACSEC_SA_AE_DVS_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT5_MACSEC_SA_AE_LS_OFFSET (6) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT5_MACSEC_SA_AE_LS_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT5_MACSEC_SA_AE_LS_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT5_MACSEC_SA_AE_DS_OFFSET (5) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT5_MACSEC_SA_AE_DS_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT5_MACSEC_SA_AE_DS_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT5_MACSEC_SA_AE_SD_OFFSET (4) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT5_MACSEC_SA_AE_SD_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT5_MACSEC_SA_AE_SD_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT5_MACSEC_SA_AE3_TEST1_OFFSET (3) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT5_MACSEC_SA_AE3_TEST1_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT5_MACSEC_SA_AE3_TEST1_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT5_MACSEC_SA_AE2_TEST1_OFFSET (2) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT5_MACSEC_SA_AE2_TEST1_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT5_MACSEC_SA_AE2_TEST1_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT5_MACSEC_SA_AE1_TEST1_OFFSET (1) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT5_MACSEC_SA_AE1_TEST1_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT5_MACSEC_SA_AE1_TEST1_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT5_MACSEC_SA_AE0_TEST1_OFFSET (0) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT5_MACSEC_SA_AE0_TEST1_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT5_MACSEC_SA_AE0_TEST1_OFFSET) + +#define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT5_ADDR (0xC924) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT5_MACSEC_STAT_AI_DVSE_OFFSET (25) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT5_MACSEC_STAT_AI_DVSE_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT5_MACSEC_STAT_AI_DVSE_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT5_MACSEC_STAT_AI_DVS_OFFSET (21) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT5_MACSEC_STAT_AI_DVS_MASK (0xF << RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT5_MACSEC_STAT_AI_DVS_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT5_MACSEC_STAT_AI_LS_OFFSET (20) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT5_MACSEC_STAT_AI_LS_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT5_MACSEC_STAT_AI_LS_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT5_MACSEC_STAT_AI_DS_OFFSET (19) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT5_MACSEC_STAT_AI_DS_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT5_MACSEC_STAT_AI_DS_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT5_MACSEC_STAT_AI_SD_OFFSET (18) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT5_MACSEC_STAT_AI_SD_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT5_MACSEC_STAT_AI_SD_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT5_MACSEC_STAT_AI_TEST1_OFFSET (17) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT5_MACSEC_STAT_AI_TEST1_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT5_MACSEC_STAT_AI_TEST1_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT5_MACSEC_STAT_AI_TESTRWM_OFFSET (16) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT5_MACSEC_STAT_AI_TESTRWM_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT5_MACSEC_STAT_AI_TESTRWM_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT5_MACSEC_STAT_AE_DVSE_OFFSET (9) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT5_MACSEC_STAT_AE_DVSE_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT5_MACSEC_STAT_AE_DVSE_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT5_MACSEC_STAT_AE_DVS_OFFSET (5) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT5_MACSEC_STAT_AE_DVS_MASK (0xF << RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT5_MACSEC_STAT_AE_DVS_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT5_MACSEC_STAT_AE_LS_OFFSET (4) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT5_MACSEC_STAT_AE_LS_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT5_MACSEC_STAT_AE_LS_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT5_MACSEC_STAT_AE_DS_OFFSET (3) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT5_MACSEC_STAT_AE_DS_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT5_MACSEC_STAT_AE_DS_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT5_MACSEC_STAT_AE_SD_OFFSET (2) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT5_MACSEC_STAT_AE_SD_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT5_MACSEC_STAT_AE_SD_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT5_MACSEC_STAT_AE_TEST1_OFFSET (1) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT5_MACSEC_STAT_AE_TEST1_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT5_MACSEC_STAT_AE_TEST1_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT5_MACSEC_STAT_AE_TESTRWM_OFFSET (0) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT5_MACSEC_STAT_AE_TESTRWM_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT5_MACSEC_STAT_AE_TESTRWM_OFFSET) + +#define RTL8373_MACSEC_MBIST_SA_FAIL_PORT5_ADDR (0xC928) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT5_BIST_FAIL_MACSEC_STAT_AE_OFFSET (19) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT5_BIST_FAIL_MACSEC_STAT_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT5_BIST_FAIL_MACSEC_STAT_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT5_DRF_BIST_FAIL_MACSEC_STAT_AE_OFFSET (18) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT5_DRF_BIST_FAIL_MACSEC_STAT_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT5_DRF_BIST_FAIL_MACSEC_STAT_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT5_BIST_FAIL_MACSEC_STAT_AI_OFFSET (17) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT5_BIST_FAIL_MACSEC_STAT_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT5_BIST_FAIL_MACSEC_STAT_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT5_DRF_BIST_FAIL_MACSEC_STAT_AI_OFFSET (16) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT5_DRF_BIST_FAIL_MACSEC_STAT_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT5_DRF_BIST_FAIL_MACSEC_STAT_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT5_BIST_FAIL_MACSEC_SA_AE3_OFFSET (15) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT5_BIST_FAIL_MACSEC_SA_AE3_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT5_BIST_FAIL_MACSEC_SA_AE3_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT5_DRF_BIST_FAIL_MACSEC_SA_AE3_OFFSET (14) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT5_DRF_BIST_FAIL_MACSEC_SA_AE3_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT5_DRF_BIST_FAIL_MACSEC_SA_AE3_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT5_BIST_FAIL_MACSEC_SA_AE2_OFFSET (13) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT5_BIST_FAIL_MACSEC_SA_AE2_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT5_BIST_FAIL_MACSEC_SA_AE2_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT5_DRF_BIST_FAIL_MACSEC_SA_AE2_OFFSET (12) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT5_DRF_BIST_FAIL_MACSEC_SA_AE2_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT5_DRF_BIST_FAIL_MACSEC_SA_AE2_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT5_BIST_FAIL_MACSEC_SA_AE1_OFFSET (11) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT5_BIST_FAIL_MACSEC_SA_AE1_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT5_BIST_FAIL_MACSEC_SA_AE1_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT5_DRF_BIST_FAIL_MACSEC_SA_AE1_OFFSET (10) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT5_DRF_BIST_FAIL_MACSEC_SA_AE1_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT5_DRF_BIST_FAIL_MACSEC_SA_AE1_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT5_BIST_FAIL_MACSEC_SA_AE0_OFFSET (9) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT5_BIST_FAIL_MACSEC_SA_AE0_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT5_BIST_FAIL_MACSEC_SA_AE0_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT5_DRF_BIST_FAIL_MACSEC_SA_AE0_OFFSET (8) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT5_DRF_BIST_FAIL_MACSEC_SA_AE0_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT5_DRF_BIST_FAIL_MACSEC_SA_AE0_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT5_BIST_FAIL_MACSEC_SA_AI3_OFFSET (7) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT5_BIST_FAIL_MACSEC_SA_AI3_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT5_BIST_FAIL_MACSEC_SA_AI3_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT5_DRF_BIST_FAIL_MACSEC_SA_AI3_OFFSET (6) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT5_DRF_BIST_FAIL_MACSEC_SA_AI3_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT5_DRF_BIST_FAIL_MACSEC_SA_AI3_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT5_BIST_FAIL_MACSEC_SA_AI2_OFFSET (5) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT5_BIST_FAIL_MACSEC_SA_AI2_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT5_BIST_FAIL_MACSEC_SA_AI2_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT5_DRF_BIST_FAIL_MACSEC_SA_AI2_OFFSET (4) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT5_DRF_BIST_FAIL_MACSEC_SA_AI2_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT5_DRF_BIST_FAIL_MACSEC_SA_AI2_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT5_BIST_FAIL_MACSEC_SA_AI1_OFFSET (3) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT5_BIST_FAIL_MACSEC_SA_AI1_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT5_BIST_FAIL_MACSEC_SA_AI1_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT5_DRF_BIST_FAIL_MACSEC_SA_AI1_OFFSET (2) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT5_DRF_BIST_FAIL_MACSEC_SA_AI1_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT5_DRF_BIST_FAIL_MACSEC_SA_AI1_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT5_BIST_FAIL_MACSEC_SA_AI0_OFFSET (1) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT5_BIST_FAIL_MACSEC_SA_AI0_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT5_BIST_FAIL_MACSEC_SA_AI0_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT5_DRF_BIST_FAIL_MACSEC_SA_AI0_OFFSET (0) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT5_DRF_BIST_FAIL_MACSEC_SA_AI0_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT5_DRF_BIST_FAIL_MACSEC_SA_AI0_OFFSET) + +#define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT5_ADDR (0xC92C) + #define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT5_CFG_WATER_LEVEL_ST_OFFSET (28) + #define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT5_CFG_WATER_LEVEL_ST_MASK (0xF << RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT5_CFG_WATER_LEVEL_ST_OFFSET) + #define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT5_CFG_WATER_LEVEL_H_OFFSET (24) + #define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT5_CFG_WATER_LEVEL_H_MASK (0xF << RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT5_CFG_WATER_LEVEL_H_OFFSET) + #define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT5_CFG_WATER_LEVEL_L_OFFSET (20) + #define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT5_CFG_WATER_LEVEL_L_MASK (0xF << RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT5_CFG_WATER_LEVEL_L_OFFSET) + #define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT5_CFG_FAULT_ON_OFFSET (19) + #define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT5_CFG_FAULT_ON_MASK (0x1 << RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT5_CFG_FAULT_ON_OFFSET) + #define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT5_CFG_ERROR_ON_OFFSET (18) + #define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT5_CFG_ERROR_ON_MASK (0x1 << RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT5_CFG_ERROR_ON_OFFSET) + #define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT5_CFG_SEQ_RSV_ON_OFFSET (17) + #define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT5_CFG_SEQ_RSV_ON_MASK (0x1 << RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT5_CFG_SEQ_RSV_ON_OFFSET) + #define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT5_CFG_CLR_FIFO_OVTHR_OFFSET (16) + #define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT5_CFG_CLR_FIFO_OVTHR_MASK (0x1 << RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT5_CFG_CLR_FIFO_OVTHR_OFFSET) + #define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT5_XGLBK_FIFO_DBG_EN_OFFSET (4) + #define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT5_XGLBK_FIFO_DBG_EN_MASK (0x1 << RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT5_XGLBK_FIFO_DBG_EN_OFFSET) + #define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT5_XGLBK_FIFO_DBG_SEL_OFFSET (0) + #define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT5_XGLBK_FIFO_DBG_SEL_MASK (0xF << RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT5_XGLBK_FIFO_DBG_SEL_OFFSET) + +#define RTL8373_MACSEC_REG_RWDH_AE_PORT5_ADDR (0xC930) + #define RTL8373_MACSEC_REG_RWDH_AE_PORT5_REG_DATA_AE_L_OFFSET (16) + #define RTL8373_MACSEC_REG_RWDH_AE_PORT5_REG_DATA_AE_L_MASK (0xFFFF << RTL8373_MACSEC_REG_RWDH_AE_PORT5_REG_DATA_AE_L_OFFSET) + #define RTL8373_MACSEC_REG_RWDH_AE_PORT5_REG_DATA_AE_H_OFFSET (0) + #define RTL8373_MACSEC_REG_RWDH_AE_PORT5_REG_DATA_AE_H_MASK (0xFFFF << RTL8373_MACSEC_REG_RWDH_AE_PORT5_REG_DATA_AE_H_OFFSET) + +#define RTL8373_MACSEC_REG_ADDR_AE_PORT5_ADDR (0xC934) + #define RTL8373_MACSEC_REG_ADDR_AE_PORT5_REG_ADDR_AE_OFFSET (16) + #define RTL8373_MACSEC_REG_ADDR_AE_PORT5_REG_ADDR_AE_MASK (0xFFFF << RTL8373_MACSEC_REG_ADDR_AE_PORT5_REG_ADDR_AE_OFFSET) + +#define RTL8373_MACSEC_REG_CMD_AE_PORT5_ADDR (0xC938) + #define RTL8373_MACSEC_REG_CMD_AE_PORT5_REG_DATA_AI_H_OFFSET (16) + #define RTL8373_MACSEC_REG_CMD_AE_PORT5_REG_DATA_AI_H_MASK (0xFFFF << RTL8373_MACSEC_REG_CMD_AE_PORT5_REG_DATA_AI_H_OFFSET) + #define RTL8373_MACSEC_REG_CMD_AE_PORT5_REG_RD_REQ_AE_OFFSET (4) + #define RTL8373_MACSEC_REG_CMD_AE_PORT5_REG_RD_REQ_AE_MASK (0x1 << RTL8373_MACSEC_REG_CMD_AE_PORT5_REG_RD_REQ_AE_OFFSET) + #define RTL8373_MACSEC_REG_CMD_AE_PORT5_REG_WR_REQ_AE_OFFSET (0) + #define RTL8373_MACSEC_REG_CMD_AE_PORT5_REG_WR_REQ_AE_MASK (0x1 << RTL8373_MACSEC_REG_CMD_AE_PORT5_REG_WR_REQ_AE_OFFSET) + +#define RTL8373_MACSEC_REG_RWDL_AI_PORT5_ADDR (0xC93C) + #define RTL8373_MACSEC_REG_RWDL_AI_PORT5_REG_DATA_AI_L_OFFSET (0) + #define RTL8373_MACSEC_REG_RWDL_AI_PORT5_REG_DATA_AI_L_MASK (0xFFFF << RTL8373_MACSEC_REG_RWDL_AI_PORT5_REG_DATA_AI_L_OFFSET) + +#define RTL8373_MACSEC_REG_ADDR_AI_PORT5_ADDR (0xC940) + #define RTL8373_MACSEC_REG_ADDR_AI_PORT5_REG_RD_REQ_AI_OFFSET (20) + #define RTL8373_MACSEC_REG_ADDR_AI_PORT5_REG_RD_REQ_AI_MASK (0x1 << RTL8373_MACSEC_REG_ADDR_AI_PORT5_REG_RD_REQ_AI_OFFSET) + #define RTL8373_MACSEC_REG_ADDR_AI_PORT5_REG_WR_REQ_AI_OFFSET (16) + #define RTL8373_MACSEC_REG_ADDR_AI_PORT5_REG_WR_REQ_AI_MASK (0x1 << RTL8373_MACSEC_REG_ADDR_AI_PORT5_REG_WR_REQ_AI_OFFSET) + #define RTL8373_MACSEC_REG_ADDR_AI_PORT5_REG_ADDR_AI_OFFSET (0) + #define RTL8373_MACSEC_REG_ADDR_AI_PORT5_REG_ADDR_AI_MASK (0xFFFF << RTL8373_MACSEC_REG_ADDR_AI_PORT5_REG_ADDR_AI_OFFSET) + +#define RTL8373_MACSEC_REG_RWD_PTP_PORT5_ADDR (0xC944) + #define RTL8373_MACSEC_REG_RWD_PTP_PORT5_REG_ADDR_PTP_OFFSET (16) + #define RTL8373_MACSEC_REG_RWD_PTP_PORT5_REG_ADDR_PTP_MASK (0xFFFF << RTL8373_MACSEC_REG_RWD_PTP_PORT5_REG_ADDR_PTP_OFFSET) + #define RTL8373_MACSEC_REG_RWD_PTP_PORT5_REG_DATA_PTP_OFFSET (0) + #define RTL8373_MACSEC_REG_RWD_PTP_PORT5_REG_DATA_PTP_MASK (0xFFFF << RTL8373_MACSEC_REG_RWD_PTP_PORT5_REG_DATA_PTP_OFFSET) + +#define RTL8373_MACSEC_REG_CMD_PTP_PORT5_ADDR (0xC948) + #define RTL8373_MACSEC_REG_CMD_PTP_PORT5_REG_RD_REQ_PTP_OFFSET (4) + #define RTL8373_MACSEC_REG_CMD_PTP_PORT5_REG_RD_REQ_PTP_MASK (0x1 << RTL8373_MACSEC_REG_CMD_PTP_PORT5_REG_RD_REQ_PTP_OFFSET) + #define RTL8373_MACSEC_REG_CMD_PTP_PORT5_REG_WR_REQ_PTP_OFFSET (0) + #define RTL8373_MACSEC_REG_CMD_PTP_PORT5_REG_WR_REQ_PTP_MASK (0x1 << RTL8373_MACSEC_REG_CMD_PTP_PORT5_REG_WR_REQ_PTP_OFFSET) + +#define RTL8373_UNUSED_005C_PORT5_ADDR (0xC94C) + #define RTL8373_UNUSED_005C_PORT5_UNUSED_005C_PORT5_OFFSET (0) + #define RTL8373_UNUSED_005C_PORT5_UNUSED_005C_PORT5_MASK (0xFFFFFFFF << RTL8373_UNUSED_005C_PORT5_UNUSED_005C_PORT5_OFFSET) + +#define RTL8373_UNUSED_0060_PORT5_ADDR (0xC950) + #define RTL8373_UNUSED_0060_PORT5_UNUSED_0060_PORT5_OFFSET (0) + #define RTL8373_UNUSED_0060_PORT5_UNUSED_0060_PORT5_MASK (0xFFFFFFFF << RTL8373_UNUSED_0060_PORT5_UNUSED_0060_PORT5_OFFSET) + +#define RTL8373_UNUSED_0064_PORT5_ADDR (0xC954) + #define RTL8373_UNUSED_0064_PORT5_UNUSED_0064_PORT5_OFFSET (0) + #define RTL8373_UNUSED_0064_PORT5_UNUSED_0064_PORT5_MASK (0xFFFFFFFF << RTL8373_UNUSED_0064_PORT5_UNUSED_0064_PORT5_OFFSET) + +#define RTL8373_UNUSED_0068_PORT5_ADDR (0xC958) + #define RTL8373_UNUSED_0068_PORT5_UNUSED_0068_PORT5_OFFSET (0) + #define RTL8373_UNUSED_0068_PORT5_UNUSED_0068_PORT5_MASK (0xFFFFFFFF << RTL8373_UNUSED_0068_PORT5_UNUSED_0068_PORT5_OFFSET) + +#define RTL8373_UNUSED_006C_PORT5_ADDR (0xC95C) + #define RTL8373_UNUSED_006C_PORT5_UNUSED_006C_PORT5_OFFSET (0) + #define RTL8373_UNUSED_006C_PORT5_UNUSED_006C_PORT5_MASK (0xFFFFFFFF << RTL8373_UNUSED_006C_PORT5_UNUSED_006C_PORT5_OFFSET) + +#define RTL8373_UNUSED_0070_PORT5_ADDR (0xC960) + #define RTL8373_UNUSED_0070_PORT5_UNUSED_0070_PORT5_OFFSET (0) + #define RTL8373_UNUSED_0070_PORT5_UNUSED_0070_PORT5_MASK (0xFFFFFFFF << RTL8373_UNUSED_0070_PORT5_UNUSED_0070_PORT5_OFFSET) + +#define RTL8373_UNUSED_0074_PORT5_ADDR (0xC964) + #define RTL8373_UNUSED_0074_PORT5_UNUSED_0074_PORT5_OFFSET (0) + #define RTL8373_UNUSED_0074_PORT5_UNUSED_0074_PORT5_MASK (0xFFFFFFFF << RTL8373_UNUSED_0074_PORT5_UNUSED_0074_PORT5_OFFSET) + +#define RTL8373_RESERVED_0078_PORT5_ADDR (0xC968) + #define RTL8373_RESERVED_0078_PORT5_RESERVED_0078_PORT5_OFFSET (0) + #define RTL8373_RESERVED_0078_PORT5_RESERVED_0078_PORT5_MASK (0xFFFFFFFF << RTL8373_RESERVED_0078_PORT5_RESERVED_0078_PORT5_OFFSET) + +#define RTL8373_RESERVED_007C_PORT5_ADDR (0xC96C) + #define RTL8373_RESERVED_007C_PORT5_RESERVED_007C_PORT5_OFFSET (0) + #define RTL8373_RESERVED_007C_PORT5_RESERVED_007C_PORT5_MASK (0xFFFFFFFF << RTL8373_RESERVED_007C_PORT5_RESERVED_007C_PORT5_OFFSET) + +#define RTL8373_MACSEC_TXSYSCRCERR_CNT_PORT5_ADDR (0xC970) + #define RTL8373_MACSEC_TXSYSCRCERR_CNT_PORT5_TXSYS_CRCERR_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_TXSYSCRCERR_CNT_PORT5_TXSYS_CRCERR_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_TXSYSCRCERR_CNT_PORT5_TXSYS_CRCERR_CNT_H_OFFSET) + #define RTL8373_MACSEC_TXSYSCRCERR_CNT_PORT5_TXSYS_CRCERR_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_TXSYSCRCERR_CNT_PORT5_TXSYS_CRCERR_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_TXSYSCRCERR_CNT_PORT5_TXSYS_CRCERR_CNT_L_OFFSET) + +#define RTL8373_MACSEC_TXSYSPKTERR_CNT_PORT5_ADDR (0xC974) + #define RTL8373_MACSEC_TXSYSPKTERR_CNT_PORT5_TXSYS_PKTERR_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_TXSYSPKTERR_CNT_PORT5_TXSYS_PKTERR_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_TXSYSPKTERR_CNT_PORT5_TXSYS_PKTERR_CNT_H_OFFSET) + #define RTL8373_MACSEC_TXSYSPKTERR_CNT_PORT5_TXSYS_PKTERR_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_TXSYSPKTERR_CNT_PORT5_TXSYS_PKTERR_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_TXSYSPKTERR_CNT_PORT5_TXSYS_PKTERR_CNT_L_OFFSET) + +#define RTL8373_MACSEC_TXSYSOK_CNT_0_PORT5_ADDR (0xC978) + #define RTL8373_MACSEC_TXSYSOK_CNT_0_PORT5_TXSYS_OK_CNT_1_OFFSET (16) + #define RTL8373_MACSEC_TXSYSOK_CNT_0_PORT5_TXSYS_OK_CNT_1_MASK (0xFFFF << RTL8373_MACSEC_TXSYSOK_CNT_0_PORT5_TXSYS_OK_CNT_1_OFFSET) + #define RTL8373_MACSEC_TXSYSOK_CNT_0_PORT5_TXSYS_OK_CNT_0_OFFSET (0) + #define RTL8373_MACSEC_TXSYSOK_CNT_0_PORT5_TXSYS_OK_CNT_0_MASK (0xFFFF << RTL8373_MACSEC_TXSYSOK_CNT_0_PORT5_TXSYS_OK_CNT_0_OFFSET) + +#define RTL8373_MACSEC_TXSYSOK_CNT_2_PORT5_ADDR (0xC97C) + #define RTL8373_MACSEC_TXSYSOK_CNT_2_PORT5_TXSYS_OK_CNT_3_OFFSET (16) + #define RTL8373_MACSEC_TXSYSOK_CNT_2_PORT5_TXSYS_OK_CNT_3_MASK (0xFFFF << RTL8373_MACSEC_TXSYSOK_CNT_2_PORT5_TXSYS_OK_CNT_3_OFFSET) + #define RTL8373_MACSEC_TXSYSOK_CNT_2_PORT5_TXSYS_OK_CNT_2_OFFSET (0) + #define RTL8373_MACSEC_TXSYSOK_CNT_2_PORT5_TXSYS_OK_CNT_2_MASK (0xFFFF << RTL8373_MACSEC_TXSYSOK_CNT_2_PORT5_TXSYS_OK_CNT_2_OFFSET) + +#define RTL8373_MACSEC_TXSYSGERR_CNT_PORT5_ADDR (0xC980) + #define RTL8373_MACSEC_TXSYSGERR_CNT_PORT5_TXSYS_GERR_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_TXSYSGERR_CNT_PORT5_TXSYS_GERR_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_TXSYSGERR_CNT_PORT5_TXSYS_GERR_CNT_H_OFFSET) + #define RTL8373_MACSEC_TXSYSGERR_CNT_PORT5_TXSYS_GERR_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_TXSYSGERR_CNT_PORT5_TXSYS_GERR_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_TXSYSGERR_CNT_PORT5_TXSYS_GERR_CNT_L_OFFSET) + +#define RTL8373_MACSEC_TXSYSGLPIERR_CNT_PORT5_ADDR (0xC984) + #define RTL8373_MACSEC_TXSYSGLPIERR_CNT_PORT5_TXSYS_GLPIERR_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_TXSYSGLPIERR_CNT_PORT5_TXSYS_GLPIERR_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_TXSYSGLPIERR_CNT_PORT5_TXSYS_GLPIERR_CNT_H_OFFSET) + #define RTL8373_MACSEC_TXSYSGLPIERR_CNT_PORT5_TXSYS_GLPIERR_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_TXSYSGLPIERR_CNT_PORT5_TXSYS_GLPIERR_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_TXSYSGLPIERR_CNT_PORT5_TXSYS_GLPIERR_CNT_L_OFFSET) + +#define RTL8373_MACSEC_TXSYS_DBG_PORT5_ADDR (0xC988) + #define RTL8373_MACSEC_TXSYS_DBG_PORT5_TXSYS_XG2IP_FSM_OFFSET (16) + #define RTL8373_MACSEC_TXSYS_DBG_PORT5_TXSYS_XG2IP_FSM_MASK (0xF << RTL8373_MACSEC_TXSYS_DBG_PORT5_TXSYS_XG2IP_FSM_OFFSET) + #define RTL8373_MACSEC_TXSYS_DBG_PORT5_TXSYS_WRP2IP_FSM_OFFSET (0) + #define RTL8373_MACSEC_TXSYS_DBG_PORT5_TXSYS_WRP2IP_FSM_MASK (0xF << RTL8373_MACSEC_TXSYS_DBG_PORT5_TXSYS_WRP2IP_FSM_OFFSET) + +#define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT5_ADDR (0xC98C) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT5_RXSYS_UNDERRUN_CNT_INCR_OFFSET (27) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT5_RXSYS_UNDERRUN_CNT_INCR_MASK (0x1 << RTL8373_MACSEC_TX_RX_CNT_INCR_PORT5_RXSYS_UNDERRUN_CNT_INCR_OFFSET) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT5_RXSYS_DROP_CNT_INCR_OFFSET (26) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT5_RXSYS_DROP_CNT_INCR_MASK (0x1 << RTL8373_MACSEC_TX_RX_CNT_INCR_PORT5_RXSYS_DROP_CNT_INCR_OFFSET) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT5_RXSYS_PKTERR_CNT_INCR_OFFSET (25) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT5_RXSYS_PKTERR_CNT_INCR_MASK (0x1 << RTL8373_MACSEC_TX_RX_CNT_INCR_PORT5_RXSYS_PKTERR_CNT_INCR_OFFSET) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT5_RXSYS_CRCERR_CNT_INCR_OFFSET (24) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT5_RXSYS_CRCERR_CNT_INCR_MASK (0x1 << RTL8373_MACSEC_TX_RX_CNT_INCR_PORT5_RXSYS_CRCERR_CNT_INCR_OFFSET) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT5_RXLINE_OVERFLOW_CNT_INCR_OFFSET (18) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT5_RXLINE_OVERFLOW_CNT_INCR_MASK (0x1 << RTL8373_MACSEC_TX_RX_CNT_INCR_PORT5_RXLINE_OVERFLOW_CNT_INCR_OFFSET) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT5_RXLINE_PKTERR_CNT_INCR_OFFSET (17) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT5_RXLINE_PKTERR_CNT_INCR_MASK (0x1 << RTL8373_MACSEC_TX_RX_CNT_INCR_PORT5_RXLINE_PKTERR_CNT_INCR_OFFSET) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT5_RXLINE_CRCERR_CNT_INCR_OFFSET (16) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT5_RXLINE_CRCERR_CNT_INCR_MASK (0x1 << RTL8373_MACSEC_TX_RX_CNT_INCR_PORT5_RXLINE_CRCERR_CNT_INCR_OFFSET) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT5_TXLINE_UNDERRUN_CNT_INCR_OFFSET (11) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT5_TXLINE_UNDERRUN_CNT_INCR_MASK (0x1 << RTL8373_MACSEC_TX_RX_CNT_INCR_PORT5_TXLINE_UNDERRUN_CNT_INCR_OFFSET) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT5_TXLINE_DROP_CNT_INCR_OFFSET (10) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT5_TXLINE_DROP_CNT_INCR_MASK (0x1 << RTL8373_MACSEC_TX_RX_CNT_INCR_PORT5_TXLINE_DROP_CNT_INCR_OFFSET) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT5_TXLINE_PKTERR_CNT_INCR_OFFSET (9) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT5_TXLINE_PKTERR_CNT_INCR_MASK (0x1 << RTL8373_MACSEC_TX_RX_CNT_INCR_PORT5_TXLINE_PKTERR_CNT_INCR_OFFSET) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT5_TXLINE_CRCERR_CNT_INCR_OFFSET (8) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT5_TXLINE_CRCERR_CNT_INCR_MASK (0x1 << RTL8373_MACSEC_TX_RX_CNT_INCR_PORT5_TXLINE_CRCERR_CNT_INCR_OFFSET) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT5_TXSYS_OVERFLOW_CNT_INCR_OFFSET (2) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT5_TXSYS_OVERFLOW_CNT_INCR_MASK (0x1 << RTL8373_MACSEC_TX_RX_CNT_INCR_PORT5_TXSYS_OVERFLOW_CNT_INCR_OFFSET) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT5_TXSYS_PKTERR_CNT_INCR_OFFSET (1) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT5_TXSYS_PKTERR_CNT_INCR_MASK (0x1 << RTL8373_MACSEC_TX_RX_CNT_INCR_PORT5_TXSYS_PKTERR_CNT_INCR_OFFSET) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT5_TXSYS_CRCERR_CNT_INCR_OFFSET (0) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT5_TXSYS_CRCERR_CNT_INCR_MASK (0x1 << RTL8373_MACSEC_TX_RX_CNT_INCR_PORT5_TXSYS_CRCERR_CNT_INCR_OFFSET) + +#define RTL8373_MACSEC_TXLINECRCERR_CNT_PORT5_ADDR (0xC990) + #define RTL8373_MACSEC_TXLINECRCERR_CNT_PORT5_TXLINE_CRCERR_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_TXLINECRCERR_CNT_PORT5_TXLINE_CRCERR_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_TXLINECRCERR_CNT_PORT5_TXLINE_CRCERR_CNT_H_OFFSET) + #define RTL8373_MACSEC_TXLINECRCERR_CNT_PORT5_TXLINE_CRCERR_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_TXLINECRCERR_CNT_PORT5_TXLINE_CRCERR_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_TXLINECRCERR_CNT_PORT5_TXLINE_CRCERR_CNT_L_OFFSET) + +#define RTL8373_MACSEC_TXLINEPKTERR_CNT_PORT5_ADDR (0xC994) + #define RTL8373_MACSEC_TXLINEPKTERR_CNT_PORT5_TXLINE_PKTERR_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_TXLINEPKTERR_CNT_PORT5_TXLINE_PKTERR_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_TXLINEPKTERR_CNT_PORT5_TXLINE_PKTERR_CNT_H_OFFSET) + #define RTL8373_MACSEC_TXLINEPKTERR_CNT_PORT5_TXLINE_PKTERR_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_TXLINEPKTERR_CNT_PORT5_TXLINE_PKTERR_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_TXLINEPKTERR_CNT_PORT5_TXLINE_PKTERR_CNT_L_OFFSET) + +#define RTL8373_MACSEC_TXLINEOK_CNT_0_PORT5_ADDR (0xC998) + #define RTL8373_MACSEC_TXLINEOK_CNT_0_PORT5_TXLINE_OK_CNT_1_OFFSET (16) + #define RTL8373_MACSEC_TXLINEOK_CNT_0_PORT5_TXLINE_OK_CNT_1_MASK (0xFFFF << RTL8373_MACSEC_TXLINEOK_CNT_0_PORT5_TXLINE_OK_CNT_1_OFFSET) + #define RTL8373_MACSEC_TXLINEOK_CNT_0_PORT5_TXLINE_OK_CNT_0_OFFSET (0) + #define RTL8373_MACSEC_TXLINEOK_CNT_0_PORT5_TXLINE_OK_CNT_0_MASK (0xFFFF << RTL8373_MACSEC_TXLINEOK_CNT_0_PORT5_TXLINE_OK_CNT_0_OFFSET) + +#define RTL8373_MACSEC_TXLINEOK_CNT_2_PORT5_ADDR (0xC99C) + #define RTL8373_MACSEC_TXLINEOK_CNT_2_PORT5_TXLINE_OK_CNT_3_OFFSET (16) + #define RTL8373_MACSEC_TXLINEOK_CNT_2_PORT5_TXLINE_OK_CNT_3_MASK (0xFFFF << RTL8373_MACSEC_TXLINEOK_CNT_2_PORT5_TXLINE_OK_CNT_3_OFFSET) + #define RTL8373_MACSEC_TXLINEOK_CNT_2_PORT5_TXLINE_OK_CNT_2_OFFSET (0) + #define RTL8373_MACSEC_TXLINEOK_CNT_2_PORT5_TXLINE_OK_CNT_2_MASK (0xFFFF << RTL8373_MACSEC_TXLINEOK_CNT_2_PORT5_TXLINE_OK_CNT_2_OFFSET) + +#define RTL8373_MACSEC_TXLINEDROP_CNT_PORT5_ADDR (0xC9A0) + #define RTL8373_MACSEC_TXLINEDROP_CNT_PORT5_TXLINE_DROP_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_TXLINEDROP_CNT_PORT5_TXLINE_DROP_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_TXLINEDROP_CNT_PORT5_TXLINE_DROP_CNT_H_OFFSET) + #define RTL8373_MACSEC_TXLINEDROP_CNT_PORT5_TXLINE_DROP_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_TXLINEDROP_CNT_PORT5_TXLINE_DROP_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_TXLINEDROP_CNT_PORT5_TXLINE_DROP_CNT_L_OFFSET) + +#define RTL8373_MACSEC_TXLINESRT_CNT_PORT5_ADDR (0xC9A4) + #define RTL8373_MACSEC_TXLINESRT_CNT_PORT5_TXLINE_SRTPKT_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_TXLINESRT_CNT_PORT5_TXLINE_SRTPKT_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_TXLINESRT_CNT_PORT5_TXLINE_SRTPKT_CNT_H_OFFSET) + #define RTL8373_MACSEC_TXLINESRT_CNT_PORT5_TXLINE_SRTPKT_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_TXLINESRT_CNT_PORT5_TXLINE_SRTPKT_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_TXLINESRT_CNT_PORT5_TXLINE_SRTPKT_CNT_L_OFFSET) + +#define RTL8373_MACSEC_TXLINEGERR_CNT_PORT5_ADDR (0xC9A8) + #define RTL8373_MACSEC_TXLINEGERR_CNT_PORT5_TXLINE_GERR_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_TXLINEGERR_CNT_PORT5_TXLINE_GERR_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_TXLINEGERR_CNT_PORT5_TXLINE_GERR_CNT_H_OFFSET) + #define RTL8373_MACSEC_TXLINEGERR_CNT_PORT5_TXLINE_GERR_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_TXLINEGERR_CNT_PORT5_TXLINE_GERR_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_TXLINEGERR_CNT_PORT5_TXLINE_GERR_CNT_L_OFFSET) + +#define RTL8373_MACSEC_TXLINE_DBG_PORT5_ADDR (0xC9AC) + #define RTL8373_MACSEC_TXLINE_DBG_PORT5_TXLINE_IP2XG_FSM_OFFSET (16) + #define RTL8373_MACSEC_TXLINE_DBG_PORT5_TXLINE_IP2XG_FSM_MASK (0x1F << RTL8373_MACSEC_TXLINE_DBG_PORT5_TXLINE_IP2XG_FSM_OFFSET) + #define RTL8373_MACSEC_TXLINE_DBG_PORT5_TXLINE_IP2WRP_FSM_OFFSET (0) + #define RTL8373_MACSEC_TXLINE_DBG_PORT5_TXLINE_IP2WRP_FSM_MASK (0xF << RTL8373_MACSEC_TXLINE_DBG_PORT5_TXLINE_IP2WRP_FSM_OFFSET) + +#define RTL8373_MACSEC_RXLINECRCERR_CNT_PORT5_ADDR (0xC9B0) + #define RTL8373_MACSEC_RXLINECRCERR_CNT_PORT5_RXLINE_CRCERR_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_RXLINECRCERR_CNT_PORT5_RXLINE_CRCERR_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_RXLINECRCERR_CNT_PORT5_RXLINE_CRCERR_CNT_H_OFFSET) + #define RTL8373_MACSEC_RXLINECRCERR_CNT_PORT5_RXLINE_CRCERR_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_RXLINECRCERR_CNT_PORT5_RXLINE_CRCERR_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_RXLINECRCERR_CNT_PORT5_RXLINE_CRCERR_CNT_L_OFFSET) + +#define RTL8373_MACSEC_RXLINEPKTERR_CNT_PORT5_ADDR (0xC9B4) + #define RTL8373_MACSEC_RXLINEPKTERR_CNT_PORT5_RXLINE_PKTERR_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_RXLINEPKTERR_CNT_PORT5_RXLINE_PKTERR_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_RXLINEPKTERR_CNT_PORT5_RXLINE_PKTERR_CNT_H_OFFSET) + #define RTL8373_MACSEC_RXLINEPKTERR_CNT_PORT5_RXLINE_PKTERR_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_RXLINEPKTERR_CNT_PORT5_RXLINE_PKTERR_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_RXLINEPKTERR_CNT_PORT5_RXLINE_PKTERR_CNT_L_OFFSET) + +#define RTL8373_MACSEC_RXLINEOK_CNT_0_PORT5_ADDR (0xC9B8) + #define RTL8373_MACSEC_RXLINEOK_CNT_0_PORT5_RXLINE_OK_CNT_1_OFFSET (16) + #define RTL8373_MACSEC_RXLINEOK_CNT_0_PORT5_RXLINE_OK_CNT_1_MASK (0xFFFF << RTL8373_MACSEC_RXLINEOK_CNT_0_PORT5_RXLINE_OK_CNT_1_OFFSET) + #define RTL8373_MACSEC_RXLINEOK_CNT_0_PORT5_RXLINE_OK_CNT_0_OFFSET (0) + #define RTL8373_MACSEC_RXLINEOK_CNT_0_PORT5_RXLINE_OK_CNT_0_MASK (0xFFFF << RTL8373_MACSEC_RXLINEOK_CNT_0_PORT5_RXLINE_OK_CNT_0_OFFSET) + +#define RTL8373_MACSEC_RXLINEOK_CNT_2_PORT5_ADDR (0xC9BC) + #define RTL8373_MACSEC_RXLINEOK_CNT_2_PORT5_RXLINE_OK_CNT_3_OFFSET (16) + #define RTL8373_MACSEC_RXLINEOK_CNT_2_PORT5_RXLINE_OK_CNT_3_MASK (0xFFFF << RTL8373_MACSEC_RXLINEOK_CNT_2_PORT5_RXLINE_OK_CNT_3_OFFSET) + #define RTL8373_MACSEC_RXLINEOK_CNT_2_PORT5_RXLINE_OK_CNT_2_OFFSET (0) + #define RTL8373_MACSEC_RXLINEOK_CNT_2_PORT5_RXLINE_OK_CNT_2_MASK (0xFFFF << RTL8373_MACSEC_RXLINEOK_CNT_2_PORT5_RXLINE_OK_CNT_2_OFFSET) + +#define RTL8373_MACSEC_RXLINESRT_CNT_PORT5_ADDR (0xC9C0) + #define RTL8373_MACSEC_RXLINESRT_CNT_PORT5_RXLINE_SHORTPKT_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_RXLINESRT_CNT_PORT5_RXLINE_SHORTPKT_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_RXLINESRT_CNT_PORT5_RXLINE_SHORTPKT_CNT_H_OFFSET) + #define RTL8373_MACSEC_RXLINESRT_CNT_PORT5_RXLINE_SHORTPKT_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_RXLINESRT_CNT_PORT5_RXLINE_SHORTPKT_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_RXLINESRT_CNT_PORT5_RXLINE_SHORTPKT_CNT_L_OFFSET) + +#define RTL8373_MACSEC_RXLINEGERR_CNT_PORT5_ADDR (0xC9C4) + #define RTL8373_MACSEC_RXLINEGERR_CNT_PORT5_RXLINE_GERR_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_RXLINEGERR_CNT_PORT5_RXLINE_GERR_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_RXLINEGERR_CNT_PORT5_RXLINE_GERR_CNT_H_OFFSET) + #define RTL8373_MACSEC_RXLINEGERR_CNT_PORT5_RXLINE_GERR_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_RXLINEGERR_CNT_PORT5_RXLINE_GERR_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_RXLINEGERR_CNT_PORT5_RXLINE_GERR_CNT_L_OFFSET) + +#define RTL8373_MACSEC_RXLINEGLPIERR_CNT_PORT5_ADDR (0xC9C8) + #define RTL8373_MACSEC_RXLINEGLPIERR_CNT_PORT5_RXLINE_GLPIERR_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_RXLINEGLPIERR_CNT_PORT5_RXLINE_GLPIERR_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_RXLINEGLPIERR_CNT_PORT5_RXLINE_GLPIERR_CNT_H_OFFSET) + #define RTL8373_MACSEC_RXLINEGLPIERR_CNT_PORT5_RXLINE_GLPIERR_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_RXLINEGLPIERR_CNT_PORT5_RXLINE_GLPIERR_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_RXLINEGLPIERR_CNT_PORT5_RXLINE_GLPIERR_CNT_L_OFFSET) + +#define RTL8373_MACSEC_RXLINE_DBG_PORT5_ADDR (0xC9CC) + #define RTL8373_MACSEC_RXLINE_DBG_PORT5_RXLINE_XG2IP_FSM_OFFSET (16) + #define RTL8373_MACSEC_RXLINE_DBG_PORT5_RXLINE_XG2IP_FSM_MASK (0xF << RTL8373_MACSEC_RXLINE_DBG_PORT5_RXLINE_XG2IP_FSM_OFFSET) + #define RTL8373_MACSEC_RXLINE_DBG_PORT5_RXLINE_WRP2IP_FSM_OFFSET (0) + #define RTL8373_MACSEC_RXLINE_DBG_PORT5_RXLINE_WRP2IP_FSM_MASK (0xF << RTL8373_MACSEC_RXLINE_DBG_PORT5_RXLINE_WRP2IP_FSM_OFFSET) + +#define RTL8373_MACSEC_RXSYSCRCERR_CNT_PORT5_ADDR (0xC9D0) + #define RTL8373_MACSEC_RXSYSCRCERR_CNT_PORT5_RXSYS_CRCERR_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_RXSYSCRCERR_CNT_PORT5_RXSYS_CRCERR_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_RXSYSCRCERR_CNT_PORT5_RXSYS_CRCERR_CNT_H_OFFSET) + #define RTL8373_MACSEC_RXSYSCRCERR_CNT_PORT5_RXSYS_CRCERR_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_RXSYSCRCERR_CNT_PORT5_RXSYS_CRCERR_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_RXSYSCRCERR_CNT_PORT5_RXSYS_CRCERR_CNT_L_OFFSET) + +#define RTL8373_MACSEC_RXSYSPKTERR_CNT_PORT5_ADDR (0xC9D4) + #define RTL8373_MACSEC_RXSYSPKTERR_CNT_PORT5_RXSYS_PKTERR_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_RXSYSPKTERR_CNT_PORT5_RXSYS_PKTERR_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_RXSYSPKTERR_CNT_PORT5_RXSYS_PKTERR_CNT_H_OFFSET) + #define RTL8373_MACSEC_RXSYSPKTERR_CNT_PORT5_RXSYS_PKTERR_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_RXSYSPKTERR_CNT_PORT5_RXSYS_PKTERR_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_RXSYSPKTERR_CNT_PORT5_RXSYS_PKTERR_CNT_L_OFFSET) + +#define RTL8373_MACSEC_RXSYSOK_CNT_0_PORT5_ADDR (0xC9D8) + #define RTL8373_MACSEC_RXSYSOK_CNT_0_PORT5_RXSYS_OK_CNT_1_OFFSET (16) + #define RTL8373_MACSEC_RXSYSOK_CNT_0_PORT5_RXSYS_OK_CNT_1_MASK (0xFFFF << RTL8373_MACSEC_RXSYSOK_CNT_0_PORT5_RXSYS_OK_CNT_1_OFFSET) + #define RTL8373_MACSEC_RXSYSOK_CNT_0_PORT5_RXSYS_OK_CNT_0_OFFSET (0) + #define RTL8373_MACSEC_RXSYSOK_CNT_0_PORT5_RXSYS_OK_CNT_0_MASK (0xFFFF << RTL8373_MACSEC_RXSYSOK_CNT_0_PORT5_RXSYS_OK_CNT_0_OFFSET) + +#define RTL8373_MACSEC_RXSYSOK_CNT_2_PORT5_ADDR (0xC9DC) + #define RTL8373_MACSEC_RXSYSOK_CNT_2_PORT5_RXSYS_OK_CNT_3_OFFSET (16) + #define RTL8373_MACSEC_RXSYSOK_CNT_2_PORT5_RXSYS_OK_CNT_3_MASK (0xFFFF << RTL8373_MACSEC_RXSYSOK_CNT_2_PORT5_RXSYS_OK_CNT_3_OFFSET) + #define RTL8373_MACSEC_RXSYSOK_CNT_2_PORT5_RXSYS_OK_CNT_2_OFFSET (0) + #define RTL8373_MACSEC_RXSYSOK_CNT_2_PORT5_RXSYS_OK_CNT_2_MASK (0xFFFF << RTL8373_MACSEC_RXSYSOK_CNT_2_PORT5_RXSYS_OK_CNT_2_OFFSET) + +#define RTL8373_MACSEC_RXSYSDROP_CNT_PORT5_ADDR (0xC9E0) + #define RTL8373_MACSEC_RXSYSDROP_CNT_PORT5_RXSYS_DROP_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_RXSYSDROP_CNT_PORT5_RXSYS_DROP_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_RXSYSDROP_CNT_PORT5_RXSYS_DROP_CNT_H_OFFSET) + #define RTL8373_MACSEC_RXSYSDROP_CNT_PORT5_RXSYS_DROP_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_RXSYSDROP_CNT_PORT5_RXSYS_DROP_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_RXSYSDROP_CNT_PORT5_RXSYS_DROP_CNT_L_OFFSET) + +#define RTL8373_MACSEC_RXSYSSRT_CNT_PORT5_ADDR (0xC9E4) + #define RTL8373_MACSEC_RXSYSSRT_CNT_PORT5_RXSYS_DECRYPTSRT_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_RXSYSSRT_CNT_PORT5_RXSYS_DECRYPTSRT_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_RXSYSSRT_CNT_PORT5_RXSYS_DECRYPTSRT_CNT_H_OFFSET) + #define RTL8373_MACSEC_RXSYSSRT_CNT_PORT5_RXSYS_DECRYPTSRT_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_RXSYSSRT_CNT_PORT5_RXSYS_DECRYPTSRT_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_RXSYSSRT_CNT_PORT5_RXSYS_DECRYPTSRT_CNT_L_OFFSET) + +#define RTL8373_MACSEC_RXSYSGERR_CNT_PORT5_ADDR (0xC9E8) + #define RTL8373_MACSEC_RXSYSGERR_CNT_PORT5_RXSYS_GERR_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_RXSYSGERR_CNT_PORT5_RXSYS_GERR_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_RXSYSGERR_CNT_PORT5_RXSYS_GERR_CNT_H_OFFSET) + #define RTL8373_MACSEC_RXSYSGERR_CNT_PORT5_RXSYS_GERR_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_RXSYSGERR_CNT_PORT5_RXSYS_GERR_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_RXSYSGERR_CNT_PORT5_RXSYS_GERR_CNT_L_OFFSET) + +#define RTL8373_MACSEC_RXSYS_DBG_PORT5_ADDR (0xC9EC) + #define RTL8373_MACSEC_RXSYS_DBG_PORT5_RXSYS_IP2XG_FSM_OFFSET (16) + #define RTL8373_MACSEC_RXSYS_DBG_PORT5_RXSYS_IP2XG_FSM_MASK (0x1F << RTL8373_MACSEC_RXSYS_DBG_PORT5_RXSYS_IP2XG_FSM_OFFSET) + #define RTL8373_MACSEC_RXSYS_DBG_PORT5_RXSYS_IP2WRP_FSM_OFFSET (0) + #define RTL8373_MACSEC_RXSYS_DBG_PORT5_RXSYS_IP2WRP_FSM_MASK (0xF << RTL8373_MACSEC_RXSYS_DBG_PORT5_RXSYS_IP2WRP_FSM_OFFSET) + +#define RTL8373_MACSEC_TXSYS_CFG1_PORT5_ADDR (0xC9F0) + #define RTL8373_MACSEC_TXSYS_CFG1_PORT5_TXSYS_XGMINIFG_OFFSET (16) + #define RTL8373_MACSEC_TXSYS_CFG1_PORT5_TXSYS_XGMINIFG_MASK (0x1F << RTL8373_MACSEC_TXSYS_CFG1_PORT5_TXSYS_XGMINIFG_OFFSET) + #define RTL8373_MACSEC_TXSYS_CFG1_PORT5_TXSYS_MINIFG_OFFSET (8) + #define RTL8373_MACSEC_TXSYS_CFG1_PORT5_TXSYS_MINIFG_MASK (0xF << RTL8373_MACSEC_TXSYS_CFG1_PORT5_TXSYS_MINIFG_OFFSET) + #define RTL8373_MACSEC_TXSYS_CFG1_PORT5_TXSYS_PMBNUM_OFFSET (0) + #define RTL8373_MACSEC_TXSYS_CFG1_PORT5_TXSYS_PMBNUM_MASK (0x7 << RTL8373_MACSEC_TXSYS_CFG1_PORT5_TXSYS_PMBNUM_OFFSET) + +#define RTL8373_MACSEC_TXSYS_PTPCFG_PORT5_ADDR (0xC9F4) + #define RTL8373_MACSEC_TXSYS_PTPCFG_PORT5_TXSYS_OUTERVLAN1_OFFSET (16) + #define RTL8373_MACSEC_TXSYS_PTPCFG_PORT5_TXSYS_OUTERVLAN1_MASK (0xFFFF << RTL8373_MACSEC_TXSYS_PTPCFG_PORT5_TXSYS_OUTERVLAN1_OFFSET) + #define RTL8373_MACSEC_TXSYS_PTPCFG_PORT5_PTP_UDP_EN_OFFSET (13) + #define RTL8373_MACSEC_TXSYS_PTPCFG_PORT5_PTP_UDP_EN_MASK (0x1 << RTL8373_MACSEC_TXSYS_PTPCFG_PORT5_PTP_UDP_EN_OFFSET) + #define RTL8373_MACSEC_TXSYS_PTPCFG_PORT5_PTP_ETH_EN_OFFSET (12) + #define RTL8373_MACSEC_TXSYS_PTPCFG_PORT5_PTP_ETH_EN_MASK (0x1 << RTL8373_MACSEC_TXSYS_PTPCFG_PORT5_PTP_ETH_EN_OFFSET) + #define RTL8373_MACSEC_TXSYS_PTPCFG_PORT5_TXSYS_PTPCRYPT_EN_OFFSET (8) + #define RTL8373_MACSEC_TXSYS_PTPCFG_PORT5_TXSYS_PTPCRYPT_EN_MASK (0x1 << RTL8373_MACSEC_TXSYS_PTPCFG_PORT5_TXSYS_PTPCRYPT_EN_OFFSET) + #define RTL8373_MACSEC_TXSYS_PTPCFG_PORT5_TXSYS_FLOWID_OFFSET (0) + #define RTL8373_MACSEC_TXSYS_PTPCFG_PORT5_TXSYS_FLOWID_MASK (0x3F << RTL8373_MACSEC_TXSYS_PTPCFG_PORT5_TXSYS_FLOWID_OFFSET) + +#define RTL8373_MACSEC_TXSYS_OUTERVLAN2_PORT5_ADDR (0xC9F8) + #define RTL8373_MACSEC_TXSYS_OUTERVLAN2_PORT5_TXSYS_OUTERVLAN3_OFFSET (16) + #define RTL8373_MACSEC_TXSYS_OUTERVLAN2_PORT5_TXSYS_OUTERVLAN3_MASK (0xFFFF << RTL8373_MACSEC_TXSYS_OUTERVLAN2_PORT5_TXSYS_OUTERVLAN3_OFFSET) + #define RTL8373_MACSEC_TXSYS_OUTERVLAN2_PORT5_TXSYS_OUTERVLAN2_OFFSET (0) + #define RTL8373_MACSEC_TXSYS_OUTERVLAN2_PORT5_TXSYS_OUTERVLAN2_MASK (0xFFFF << RTL8373_MACSEC_TXSYS_OUTERVLAN2_PORT5_TXSYS_OUTERVLAN2_OFFSET) + +#define RTL8373_MACSEC_TXSYS_OUTERVLAN4_PORT5_ADDR (0xC9FC) + #define RTL8373_MACSEC_TXSYS_OUTERVLAN4_PORT5_TXSYS_INNERVLAN1_OFFSET (16) + #define RTL8373_MACSEC_TXSYS_OUTERVLAN4_PORT5_TXSYS_INNERVLAN1_MASK (0xFFFF << RTL8373_MACSEC_TXSYS_OUTERVLAN4_PORT5_TXSYS_INNERVLAN1_OFFSET) + #define RTL8373_MACSEC_TXSYS_OUTERVLAN4_PORT5_TXSYS_OUTERVLAN4_OFFSET (0) + #define RTL8373_MACSEC_TXSYS_OUTERVLAN4_PORT5_TXSYS_OUTERVLAN4_MASK (0xFFFF << RTL8373_MACSEC_TXSYS_OUTERVLAN4_PORT5_TXSYS_OUTERVLAN4_OFFSET) + +#define RTL8373_MACSEC_TXSYS_INNERVLAN2_PORT5_ADDR (0xCA00) + #define RTL8373_MACSEC_TXSYS_INNERVLAN2_PORT5_TXSYS_INNERVLAN3_OFFSET (16) + #define RTL8373_MACSEC_TXSYS_INNERVLAN2_PORT5_TXSYS_INNERVLAN3_MASK (0xFFFF << RTL8373_MACSEC_TXSYS_INNERVLAN2_PORT5_TXSYS_INNERVLAN3_OFFSET) + #define RTL8373_MACSEC_TXSYS_INNERVLAN2_PORT5_TXSYS_INNERVLAN2_OFFSET (0) + #define RTL8373_MACSEC_TXSYS_INNERVLAN2_PORT5_TXSYS_INNERVLAN2_MASK (0xFFFF << RTL8373_MACSEC_TXSYS_INNERVLAN2_PORT5_TXSYS_INNERVLAN2_OFFSET) + +#define RTL8373_MACSEC_TXSYS_INNERVLAN4_PORT5_ADDR (0xCA04) + #define RTL8373_MACSEC_TXSYS_INNERVLAN4_PORT5_TXSYS_INNERVLAN5_OFFSET (16) + #define RTL8373_MACSEC_TXSYS_INNERVLAN4_PORT5_TXSYS_INNERVLAN5_MASK (0xFFFF << RTL8373_MACSEC_TXSYS_INNERVLAN4_PORT5_TXSYS_INNERVLAN5_OFFSET) + #define RTL8373_MACSEC_TXSYS_INNERVLAN4_PORT5_TXSYS_INNERVLAN4_OFFSET (0) + #define RTL8373_MACSEC_TXSYS_INNERVLAN4_PORT5_TXSYS_INNERVLAN4_MASK (0xFFFF << RTL8373_MACSEC_TXSYS_INNERVLAN4_PORT5_TXSYS_INNERVLAN4_OFFSET) + +#define RTL8373_MACSEC_TXSYS_INNERVLAN6_PORT5_ADDR (0xCA08) + #define RTL8373_MACSEC_TXSYS_INNERVLAN6_PORT5_TXSYS_INNERVLAN7_OFFSET (16) + #define RTL8373_MACSEC_TXSYS_INNERVLAN6_PORT5_TXSYS_INNERVLAN7_MASK (0xFFFF << RTL8373_MACSEC_TXSYS_INNERVLAN6_PORT5_TXSYS_INNERVLAN7_OFFSET) + #define RTL8373_MACSEC_TXSYS_INNERVLAN6_PORT5_TXSYS_INNERVLAN6_OFFSET (0) + #define RTL8373_MACSEC_TXSYS_INNERVLAN6_PORT5_TXSYS_INNERVLAN6_MASK (0xFFFF << RTL8373_MACSEC_TXSYS_INNERVLAN6_PORT5_TXSYS_INNERVLAN6_OFFSET) + +#define RTL8373_UNUSED_011C_PORT5_ADDR (0xCA0C) + #define RTL8373_UNUSED_011C_PORT5_UNUSED_011C_PORT5_OFFSET (0) + #define RTL8373_UNUSED_011C_PORT5_UNUSED_011C_PORT5_MASK (0xFFFFFFFF << RTL8373_UNUSED_011C_PORT5_UNUSED_011C_PORT5_OFFSET) + +#define RTL8373_UNUSED_0120_PORT5_ADDR (0xCA10) + #define RTL8373_UNUSED_0120_PORT5_UNUSED_0120_PORT5_OFFSET (0) + #define RTL8373_UNUSED_0120_PORT5_UNUSED_0120_PORT5_MASK (0xFFFFFFFF << RTL8373_UNUSED_0120_PORT5_UNUSED_0120_PORT5_OFFSET) + +#define RTL8373_UNUSED_0124_PORT5_ADDR (0xCA14) + #define RTL8373_UNUSED_0124_PORT5_UNUSED_0124_PORT5_OFFSET (0) + #define RTL8373_UNUSED_0124_PORT5_UNUSED_0124_PORT5_MASK (0xFFFFFFFF << RTL8373_UNUSED_0124_PORT5_UNUSED_0124_PORT5_OFFSET) + +#define RTL8373_UNUSED_0128_PORT5_ADDR (0xCA18) + #define RTL8373_UNUSED_0128_PORT5_UNUSED_0128_PORT5_OFFSET (0) + #define RTL8373_UNUSED_0128_PORT5_UNUSED_0128_PORT5_MASK (0xFFFFFFFF << RTL8373_UNUSED_0128_PORT5_UNUSED_0128_PORT5_OFFSET) + +#define RTL8373_UNUSED_012C_PORT5_ADDR (0xCA1C) + #define RTL8373_UNUSED_012C_PORT5_UNUSED_012C_PORT5_OFFSET (0) + #define RTL8373_UNUSED_012C_PORT5_UNUSED_012C_PORT5_MASK (0xFFFFFFFF << RTL8373_UNUSED_012C_PORT5_UNUSED_012C_PORT5_OFFSET) + +#define RTL8373_UNUSED_0130_PORT5_ADDR (0xCA20) + #define RTL8373_UNUSED_0130_PORT5_UNUSED_0130_PORT5_OFFSET (0) + #define RTL8373_UNUSED_0130_PORT5_UNUSED_0130_PORT5_MASK (0xFFFFFFFF << RTL8373_UNUSED_0130_PORT5_UNUSED_0130_PORT5_OFFSET) + +#define RTL8373_UNUSED_0134_PORT5_ADDR (0xCA24) + #define RTL8373_UNUSED_0134_PORT5_UNUSED_0134_PORT5_OFFSET (0) + #define RTL8373_UNUSED_0134_PORT5_UNUSED_0134_PORT5_MASK (0xFFFFFFFF << RTL8373_UNUSED_0134_PORT5_UNUSED_0134_PORT5_OFFSET) + +#define RTL8373_UNUSED_0138_PORT5_ADDR (0xCA28) + #define RTL8373_UNUSED_0138_PORT5_UNUSED_0138_PORT5_OFFSET (0) + #define RTL8373_UNUSED_0138_PORT5_UNUSED_0138_PORT5_MASK (0xFFFFFFFF << RTL8373_UNUSED_0138_PORT5_UNUSED_0138_PORT5_OFFSET) + +#define RTL8373_UNUSED_013C_PORT5_ADDR (0xCA2C) + #define RTL8373_UNUSED_013C_PORT5_UNUSED_013C_PORT5_OFFSET (0) + #define RTL8373_UNUSED_013C_PORT5_UNUSED_013C_PORT5_MASK (0xFFFFFFFF << RTL8373_UNUSED_013C_PORT5_UNUSED_013C_PORT5_OFFSET) + +#define RTL8373_MACSEC_TXLINE_CFG1_PORT5_ADDR (0xCA30) + #define RTL8373_MACSEC_TXLINE_CFG1_PORT5_TXLINE_WAIT_T_OFFSET (16) + #define RTL8373_MACSEC_TXLINE_CFG1_PORT5_TXLINE_WAIT_T_MASK (0xFF << RTL8373_MACSEC_TXLINE_CFG1_PORT5_TXLINE_WAIT_T_OFFSET) + #define RTL8373_MACSEC_TXLINE_CFG1_PORT5_TXLINE_MINIFG_OFFSET (8) + #define RTL8373_MACSEC_TXLINE_CFG1_PORT5_TXLINE_MINIFG_MASK (0xFF << RTL8373_MACSEC_TXLINE_CFG1_PORT5_TXLINE_MINIFG_OFFSET) + #define RTL8373_MACSEC_TXLINE_CFG1_PORT5_TXLINE_PMBNUM_OFFSET (0) + #define RTL8373_MACSEC_TXLINE_CFG1_PORT5_TXLINE_PMBNUM_MASK (0xF << RTL8373_MACSEC_TXLINE_CFG1_PORT5_TXLINE_PMBNUM_OFFSET) + +#define RTL8373_MACSEC_TXLINE_CFG3_PORT5_ADDR (0xCA34) + #define RTL8373_MACSEC_TXLINE_CFG3_PORT5_TXLINE_FIFO_TSHD_OFFSET (16) + #define RTL8373_MACSEC_TXLINE_CFG3_PORT5_TXLINE_FIFO_TSHD_MASK (0xFF << RTL8373_MACSEC_TXLINE_CFG3_PORT5_TXLINE_FIFO_TSHD_OFFSET) + #define RTL8373_MACSEC_TXLINE_CFG3_PORT5_TXLINE_PAD_VLAN_EN_OFFSET (14) + #define RTL8373_MACSEC_TXLINE_CFG3_PORT5_TXLINE_PAD_VLAN_EN_MASK (0x1 << RTL8373_MACSEC_TXLINE_CFG3_PORT5_TXLINE_PAD_VLAN_EN_OFFSET) + #define RTL8373_MACSEC_TXLINE_CFG3_PORT5_TXLINE_PAD_MACSEC_EN_OFFSET (13) + #define RTL8373_MACSEC_TXLINE_CFG3_PORT5_TXLINE_PAD_MACSEC_EN_MASK (0x1 << RTL8373_MACSEC_TXLINE_CFG3_PORT5_TXLINE_PAD_MACSEC_EN_OFFSET) + #define RTL8373_MACSEC_TXLINE_CFG3_PORT5_TXLINE_PAD_EN_OFFSET (12) + #define RTL8373_MACSEC_TXLINE_CFG3_PORT5_TXLINE_PAD_EN_MASK (0x1 << RTL8373_MACSEC_TXLINE_CFG3_PORT5_TXLINE_PAD_EN_OFFSET) + #define RTL8373_MACSEC_TXLINE_CFG3_PORT5_TXLINE_PKTERR_INVRSCRC_EN_OFFSET (8) + #define RTL8373_MACSEC_TXLINE_CFG3_PORT5_TXLINE_PKTERR_INVRSCRC_EN_MASK (0x1 << RTL8373_MACSEC_TXLINE_CFG3_PORT5_TXLINE_PKTERR_INVRSCRC_EN_OFFSET) + #define RTL8373_MACSEC_TXLINE_CFG3_PORT5_TXLINE_GMIIER_INVRSCRC_EN_OFFSET (5) + #define RTL8373_MACSEC_TXLINE_CFG3_PORT5_TXLINE_GMIIER_INVRSCRC_EN_MASK (0x1 << RTL8373_MACSEC_TXLINE_CFG3_PORT5_TXLINE_GMIIER_INVRSCRC_EN_OFFSET) + #define RTL8373_MACSEC_TXLINE_CFG3_PORT5_TXLINE_CRCERR_INVRSCRC_EN_OFFSET (4) + #define RTL8373_MACSEC_TXLINE_CFG3_PORT5_TXLINE_CRCERR_INVRSCRC_EN_MASK (0x1 << RTL8373_MACSEC_TXLINE_CFG3_PORT5_TXLINE_CRCERR_INVRSCRC_EN_OFFSET) + #define RTL8373_MACSEC_TXLINE_CFG3_PORT5_TXLINE_CLASSDROP_EN_OFFSET (0) + #define RTL8373_MACSEC_TXLINE_CFG3_PORT5_TXLINE_CLASSDROP_EN_MASK (0x1 << RTL8373_MACSEC_TXLINE_CFG3_PORT5_TXLINE_CLASSDROP_EN_OFFSET) + +#define RTL8373_MACSEC_TXLINE_CFG5_PORT5_ADDR (0xCA38) + #define RTL8373_MACSEC_TXLINE_CFG5_PORT5_TXLINE_AVG_IPG_OFFSET (16) + #define RTL8373_MACSEC_TXLINE_CFG5_PORT5_TXLINE_AVG_IPG_MASK (0xF << RTL8373_MACSEC_TXLINE_CFG5_PORT5_TXLINE_AVG_IPG_OFFSET) + #define RTL8373_MACSEC_TXLINE_CFG5_PORT5_TXLIEN_LPIEXIT_T_OFFSET (0) + #define RTL8373_MACSEC_TXLINE_CFG5_PORT5_TXLIEN_LPIEXIT_T_MASK (0x7FFF << RTL8373_MACSEC_TXLINE_CFG5_PORT5_TXLIEN_LPIEXIT_T_OFFSET) + +#define RTL8373_UNUSED_014C_PORT5_ADDR (0xCA3C) + #define RTL8373_UNUSED_014C_PORT5_UNUSED_014C_PORT5_OFFSET (0) + #define RTL8373_UNUSED_014C_PORT5_UNUSED_014C_PORT5_MASK (0xFFFFFFFF << RTL8373_UNUSED_014C_PORT5_UNUSED_014C_PORT5_OFFSET) + +#define RTL8373_UNUSED_0150_PORT5_ADDR (0xCA40) + #define RTL8373_UNUSED_0150_PORT5_UNUSED_0150_PORT5_OFFSET (0) + #define RTL8373_UNUSED_0150_PORT5_UNUSED_0150_PORT5_MASK (0xFFFFFFFF << RTL8373_UNUSED_0150_PORT5_UNUSED_0150_PORT5_OFFSET) + +#define RTL8373_UNUSED_0154_PORT5_ADDR (0xCA44) + #define RTL8373_UNUSED_0154_PORT5_UNUSED_0154_PORT5_OFFSET (0) + #define RTL8373_UNUSED_0154_PORT5_UNUSED_0154_PORT5_MASK (0xFFFFFFFF << RTL8373_UNUSED_0154_PORT5_UNUSED_0154_PORT5_OFFSET) + +#define RTL8373_UNUSED_0158_PORT5_ADDR (0xCA48) + #define RTL8373_UNUSED_0158_PORT5_UNUSED_0158_PORT5_OFFSET (0) + #define RTL8373_UNUSED_0158_PORT5_UNUSED_0158_PORT5_MASK (0xFFFFFFFF << RTL8373_UNUSED_0158_PORT5_UNUSED_0158_PORT5_OFFSET) + +#define RTL8373_UNUSED_015C_PORT5_ADDR (0xCA4C) + #define RTL8373_UNUSED_015C_PORT5_UNUSED_015C_PORT5_OFFSET (0) + #define RTL8373_UNUSED_015C_PORT5_UNUSED_015C_PORT5_MASK (0xFFFFFFFF << RTL8373_UNUSED_015C_PORT5_UNUSED_015C_PORT5_OFFSET) + +#define RTL8373_UNUSED_0160_PORT5_ADDR (0xCA50) + #define RTL8373_UNUSED_0160_PORT5_UNUSED_0160_PORT5_OFFSET (0) + #define RTL8373_UNUSED_0160_PORT5_UNUSED_0160_PORT5_MASK (0xFFFFFFFF << RTL8373_UNUSED_0160_PORT5_UNUSED_0160_PORT5_OFFSET) + +#define RTL8373_UNUSED_0164_PORT5_ADDR (0xCA54) + #define RTL8373_UNUSED_0164_PORT5_UNUSED_0164_PORT5_OFFSET (0) + #define RTL8373_UNUSED_0164_PORT5_UNUSED_0164_PORT5_MASK (0xFFFFFFFF << RTL8373_UNUSED_0164_PORT5_UNUSED_0164_PORT5_OFFSET) + +#define RTL8373_UNUSED_0168_PORT5_ADDR (0xCA58) + #define RTL8373_UNUSED_0168_PORT5_UNUSED_0168_PORT5_OFFSET (0) + #define RTL8373_UNUSED_0168_PORT5_UNUSED_0168_PORT5_MASK (0xFFFFFFFF << RTL8373_UNUSED_0168_PORT5_UNUSED_0168_PORT5_OFFSET) + +#define RTL8373_UNUSED_016C_PORT5_ADDR (0xCA5C) + #define RTL8373_UNUSED_016C_PORT5_UNUSED_016C_PORT5_OFFSET (0) + #define RTL8373_UNUSED_016C_PORT5_UNUSED_016C_PORT5_MASK (0xFFFFFFFF << RTL8373_UNUSED_016C_PORT5_UNUSED_016C_PORT5_OFFSET) + +#define RTL8373_UNUSED_0170_PORT5_ADDR (0xCA60) + #define RTL8373_UNUSED_0170_PORT5_UNUSED_0170_PORT5_OFFSET (0) + #define RTL8373_UNUSED_0170_PORT5_UNUSED_0170_PORT5_MASK (0xFFFFFFFF << RTL8373_UNUSED_0170_PORT5_UNUSED_0170_PORT5_OFFSET) + +#define RTL8373_UNUSED_0174_PORT5_ADDR (0xCA64) + #define RTL8373_UNUSED_0174_PORT5_UNUSED_0174_PORT5_OFFSET (0) + #define RTL8373_UNUSED_0174_PORT5_UNUSED_0174_PORT5_MASK (0xFFFFFFFF << RTL8373_UNUSED_0174_PORT5_UNUSED_0174_PORT5_OFFSET) + +#define RTL8373_UNUSED_0178_PORT5_ADDR (0xCA68) + #define RTL8373_UNUSED_0178_PORT5_UNUSED_0178_PORT5_OFFSET (0) + #define RTL8373_UNUSED_0178_PORT5_UNUSED_0178_PORT5_MASK (0xFFFFFFFF << RTL8373_UNUSED_0178_PORT5_UNUSED_0178_PORT5_OFFSET) + +#define RTL8373_UNUSED_017C_PORT5_ADDR (0xCA6C) + #define RTL8373_UNUSED_017C_PORT5_UNUSED_017C_PORT5_OFFSET (0) + #define RTL8373_UNUSED_017C_PORT5_UNUSED_017C_PORT5_MASK (0xFFFFFFFF << RTL8373_UNUSED_017C_PORT5_UNUSED_017C_PORT5_OFFSET) + +#define RTL8373_MACSEC_RXLINE_CFG1_PORT5_ADDR (0xCA70) + #define RTL8373_MACSEC_RXLINE_CFG1_PORT5_RXLINE_XGMINIFG_OFFSET (16) + #define RTL8373_MACSEC_RXLINE_CFG1_PORT5_RXLINE_XGMINIFG_MASK (0x1F << RTL8373_MACSEC_RXLINE_CFG1_PORT5_RXLINE_XGMINIFG_OFFSET) + #define RTL8373_MACSEC_RXLINE_CFG1_PORT5_RXLINE_MINIPG_OFFSET (8) + #define RTL8373_MACSEC_RXLINE_CFG1_PORT5_RXLINE_MINIPG_MASK (0xF << RTL8373_MACSEC_RXLINE_CFG1_PORT5_RXLINE_MINIPG_OFFSET) + #define RTL8373_MACSEC_RXLINE_CFG1_PORT5_RXLINE_PMBNUM_OFFSET (0) + #define RTL8373_MACSEC_RXLINE_CFG1_PORT5_RXLINE_PMBNUM_MASK (0x7 << RTL8373_MACSEC_RXLINE_CFG1_PORT5_RXLINE_PMBNUM_OFFSET) + +#define RTL8373_UNUSED_0184_PORT5_ADDR (0xCA74) + #define RTL8373_UNUSED_0184_PORT5_UNUSED_0184_PORT5_OFFSET (0) + #define RTL8373_UNUSED_0184_PORT5_UNUSED_0184_PORT5_MASK (0xFFFFFFFF << RTL8373_UNUSED_0184_PORT5_UNUSED_0184_PORT5_OFFSET) + +#define RTL8373_UNUSED_0188_PORT5_ADDR (0xCA78) + #define RTL8373_UNUSED_0188_PORT5_UNUSED_0188_PORT5_OFFSET (0) + #define RTL8373_UNUSED_0188_PORT5_UNUSED_0188_PORT5_MASK (0xFFFFFFFF << RTL8373_UNUSED_0188_PORT5_UNUSED_0188_PORT5_OFFSET) + +#define RTL8373_UNUSED_018C_PORT5_ADDR (0xCA7C) + #define RTL8373_UNUSED_018C_PORT5_UNUSED_018C_PORT5_OFFSET (0) + #define RTL8373_UNUSED_018C_PORT5_UNUSED_018C_PORT5_MASK (0xFFFFFFFF << RTL8373_UNUSED_018C_PORT5_UNUSED_018C_PORT5_OFFSET) + +#define RTL8373_UNUSED_0190_PORT5_ADDR (0xCA80) + #define RTL8373_UNUSED_0190_PORT5_UNUSED_0190_PORT5_OFFSET (0) + #define RTL8373_UNUSED_0190_PORT5_UNUSED_0190_PORT5_MASK (0xFFFFFFFF << RTL8373_UNUSED_0190_PORT5_UNUSED_0190_PORT5_OFFSET) + +#define RTL8373_UNUSED_0194_PORT5_ADDR (0xCA84) + #define RTL8373_UNUSED_0194_PORT5_UNUSED_0194_PORT5_OFFSET (0) + #define RTL8373_UNUSED_0194_PORT5_UNUSED_0194_PORT5_MASK (0xFFFFFFFF << RTL8373_UNUSED_0194_PORT5_UNUSED_0194_PORT5_OFFSET) + +#define RTL8373_UNUSED_0198_PORT5_ADDR (0xCA88) + #define RTL8373_UNUSED_0198_PORT5_UNUSED_0198_PORT5_OFFSET (0) + #define RTL8373_UNUSED_0198_PORT5_UNUSED_0198_PORT5_MASK (0xFFFFFFFF << RTL8373_UNUSED_0198_PORT5_UNUSED_0198_PORT5_OFFSET) + +#define RTL8373_UNUSED_019C_PORT5_ADDR (0xCA8C) + #define RTL8373_UNUSED_019C_PORT5_UNUSED_019C_PORT5_OFFSET (0) + #define RTL8373_UNUSED_019C_PORT5_UNUSED_019C_PORT5_MASK (0xFFFFFFFF << RTL8373_UNUSED_019C_PORT5_UNUSED_019C_PORT5_OFFSET) + +#define RTL8373_UNUSED_01A0_PORT5_ADDR (0xCA90) + #define RTL8373_UNUSED_01A0_PORT5_UNUSED_01A0_PORT5_OFFSET (0) + #define RTL8373_UNUSED_01A0_PORT5_UNUSED_01A0_PORT5_MASK (0xFFFFFFFF << RTL8373_UNUSED_01A0_PORT5_UNUSED_01A0_PORT5_OFFSET) + +#define RTL8373_UNUSED_01A4_PORT5_ADDR (0xCA94) + #define RTL8373_UNUSED_01A4_PORT5_UNUSED_01A4_PORT5_OFFSET (0) + #define RTL8373_UNUSED_01A4_PORT5_UNUSED_01A4_PORT5_MASK (0xFFFFFFFF << RTL8373_UNUSED_01A4_PORT5_UNUSED_01A4_PORT5_OFFSET) + +#define RTL8373_UNUSED_01A8_PORT5_ADDR (0xCA98) + #define RTL8373_UNUSED_01A8_PORT5_UNUSED_01A8_PORT5_OFFSET (0) + #define RTL8373_UNUSED_01A8_PORT5_UNUSED_01A8_PORT5_MASK (0xFFFFFFFF << RTL8373_UNUSED_01A8_PORT5_UNUSED_01A8_PORT5_OFFSET) + +#define RTL8373_UNUSED_01AC_PORT5_ADDR (0xCA9C) + #define RTL8373_UNUSED_01AC_PORT5_UNUSED_01AC_PORT5_OFFSET (0) + #define RTL8373_UNUSED_01AC_PORT5_UNUSED_01AC_PORT5_MASK (0xFFFFFFFF << RTL8373_UNUSED_01AC_PORT5_UNUSED_01AC_PORT5_OFFSET) + +#define RTL8373_UNUSED_01B0_PORT5_ADDR (0xCAA0) + #define RTL8373_UNUSED_01B0_PORT5_UNUSED_01B0_PORT5_OFFSET (0) + #define RTL8373_UNUSED_01B0_PORT5_UNUSED_01B0_PORT5_MASK (0xFFFFFFFF << RTL8373_UNUSED_01B0_PORT5_UNUSED_01B0_PORT5_OFFSET) + +#define RTL8373_UNUSED_01B4_PORT5_ADDR (0xCAA4) + #define RTL8373_UNUSED_01B4_PORT5_UNUSED_01B4_PORT5_OFFSET (0) + #define RTL8373_UNUSED_01B4_PORT5_UNUSED_01B4_PORT5_MASK (0xFFFFFFFF << RTL8373_UNUSED_01B4_PORT5_UNUSED_01B4_PORT5_OFFSET) + +#define RTL8373_UNUSED_01B8_PORT5_ADDR (0xCAA8) + #define RTL8373_UNUSED_01B8_PORT5_UNUSED_01B8_PORT5_OFFSET (0) + #define RTL8373_UNUSED_01B8_PORT5_UNUSED_01B8_PORT5_MASK (0xFFFFFFFF << RTL8373_UNUSED_01B8_PORT5_UNUSED_01B8_PORT5_OFFSET) + +#define RTL8373_UNUSED_01BC_PORT5_ADDR (0xCAAC) + #define RTL8373_UNUSED_01BC_PORT5_UNUSED_01BC_PORT5_OFFSET (0) + #define RTL8373_UNUSED_01BC_PORT5_UNUSED_01BC_PORT5_MASK (0xFFFFFFFF << RTL8373_UNUSED_01BC_PORT5_UNUSED_01BC_PORT5_OFFSET) + +#define RTL8373_MACSEC_RXSYS_CFG1_PORT5_ADDR (0xCAB0) + #define RTL8373_MACSEC_RXSYS_CFG1_PORT5_RXSYS_WAIT_T_OFFSET (16) + #define RTL8373_MACSEC_RXSYS_CFG1_PORT5_RXSYS_WAIT_T_MASK (0xFF << RTL8373_MACSEC_RXSYS_CFG1_PORT5_RXSYS_WAIT_T_OFFSET) + #define RTL8373_MACSEC_RXSYS_CFG1_PORT5_RXSYS_MINIPG_OFFSET (8) + #define RTL8373_MACSEC_RXSYS_CFG1_PORT5_RXSYS_MINIPG_MASK (0xFF << RTL8373_MACSEC_RXSYS_CFG1_PORT5_RXSYS_MINIPG_OFFSET) + #define RTL8373_MACSEC_RXSYS_CFG1_PORT5_RXSYS_PMBNUM_OFFSET (0) + #define RTL8373_MACSEC_RXSYS_CFG1_PORT5_RXSYS_PMBNUM_MASK (0xF << RTL8373_MACSEC_RXSYS_CFG1_PORT5_RXSYS_PMBNUM_OFFSET) + +#define RTL8373_MACSEC_RXSYS_CFG3_PORT5_ADDR (0xCAB4) + #define RTL8373_MACSEC_RXSYS_CFG3_PORT5_RXSYS_OUTERVLAN1_OFFSET (16) + #define RTL8373_MACSEC_RXSYS_CFG3_PORT5_RXSYS_OUTERVLAN1_MASK (0xFFFF << RTL8373_MACSEC_RXSYS_CFG3_PORT5_RXSYS_OUTERVLAN1_OFFSET) + #define RTL8373_MACSEC_RXSYS_CFG3_PORT5_RXSYS_PAD_VLAN_EN_OFFSET (14) + #define RTL8373_MACSEC_RXSYS_CFG3_PORT5_RXSYS_PAD_VLAN_EN_MASK (0x1 << RTL8373_MACSEC_RXSYS_CFG3_PORT5_RXSYS_PAD_VLAN_EN_OFFSET) + #define RTL8373_MACSEC_RXSYS_CFG3_PORT5_RXSYS_PAD_LINESRT_EN_OFFSET (13) + #define RTL8373_MACSEC_RXSYS_CFG3_PORT5_RXSYS_PAD_LINESRT_EN_MASK (0x1 << RTL8373_MACSEC_RXSYS_CFG3_PORT5_RXSYS_PAD_LINESRT_EN_OFFSET) + #define RTL8373_MACSEC_RXSYS_CFG3_PORT5_RXSYS_PAD_DECRYPTSRT_EN_OFFSET (12) + #define RTL8373_MACSEC_RXSYS_CFG3_PORT5_RXSYS_PAD_DECRYPTSRT_EN_MASK (0x1 << RTL8373_MACSEC_RXSYS_CFG3_PORT5_RXSYS_PAD_DECRYPTSRT_EN_OFFSET) + #define RTL8373_MACSEC_RXSYS_CFG3_PORT5_RXSYS_PKTERR_INVRSCRC_EN_OFFSET (8) + #define RTL8373_MACSEC_RXSYS_CFG3_PORT5_RXSYS_PKTERR_INVRSCRC_EN_MASK (0x1 << RTL8373_MACSEC_RXSYS_CFG3_PORT5_RXSYS_PKTERR_INVRSCRC_EN_OFFSET) + #define RTL8373_MACSEC_RXSYS_CFG3_PORT5_RXSYS_GMIIER_INVRSCRC_EN_OFFSET (5) + #define RTL8373_MACSEC_RXSYS_CFG3_PORT5_RXSYS_GMIIER_INVRSCRC_EN_MASK (0x1 << RTL8373_MACSEC_RXSYS_CFG3_PORT5_RXSYS_GMIIER_INVRSCRC_EN_OFFSET) + #define RTL8373_MACSEC_RXSYS_CFG3_PORT5_RXSYS_CRCERR_INVRSCRC_EN_OFFSET (4) + #define RTL8373_MACSEC_RXSYS_CFG3_PORT5_RXSYS_CRCERR_INVRSCRC_EN_MASK (0x1 << RTL8373_MACSEC_RXSYS_CFG3_PORT5_RXSYS_CRCERR_INVRSCRC_EN_OFFSET) + #define RTL8373_MACSEC_RXSYS_CFG3_PORT5_RXSYS_CLASSDROP_EN_OFFSET (0) + #define RTL8373_MACSEC_RXSYS_CFG3_PORT5_RXSYS_CLASSDROP_EN_MASK (0x1 << RTL8373_MACSEC_RXSYS_CFG3_PORT5_RXSYS_CLASSDROP_EN_OFFSET) + +#define RTL8373_MACSEC_RXSYS_OUTERVLAN2_PORT5_ADDR (0xCAB8) + #define RTL8373_MACSEC_RXSYS_OUTERVLAN2_PORT5_RXSYS_OUTERVLAN3_OFFSET (16) + #define RTL8373_MACSEC_RXSYS_OUTERVLAN2_PORT5_RXSYS_OUTERVLAN3_MASK (0xFFFF << RTL8373_MACSEC_RXSYS_OUTERVLAN2_PORT5_RXSYS_OUTERVLAN3_OFFSET) + #define RTL8373_MACSEC_RXSYS_OUTERVLAN2_PORT5_RXSYS_OUTERVLAN2_OFFSET (0) + #define RTL8373_MACSEC_RXSYS_OUTERVLAN2_PORT5_RXSYS_OUTERVLAN2_MASK (0xFFFF << RTL8373_MACSEC_RXSYS_OUTERVLAN2_PORT5_RXSYS_OUTERVLAN2_OFFSET) + +#define RTL8373_MACSEC_RXSYS_OUTERVLAN4_PORT5_ADDR (0xCABC) + #define RTL8373_MACSEC_RXSYS_OUTERVLAN4_PORT5_RXSYS_INNERVLAN1_OFFSET (16) + #define RTL8373_MACSEC_RXSYS_OUTERVLAN4_PORT5_RXSYS_INNERVLAN1_MASK (0xFFFF << RTL8373_MACSEC_RXSYS_OUTERVLAN4_PORT5_RXSYS_INNERVLAN1_OFFSET) + #define RTL8373_MACSEC_RXSYS_OUTERVLAN4_PORT5_RXSYS_OUTERVLAN4_OFFSET (0) + #define RTL8373_MACSEC_RXSYS_OUTERVLAN4_PORT5_RXSYS_OUTERVLAN4_MASK (0xFFFF << RTL8373_MACSEC_RXSYS_OUTERVLAN4_PORT5_RXSYS_OUTERVLAN4_OFFSET) + +#define RTL8373_MACSEC_RXSYS_INNERVLAN2_PORT5_ADDR (0xCAC0) + #define RTL8373_MACSEC_RXSYS_INNERVLAN2_PORT5_RXSYS_INNERVLAN3_OFFSET (16) + #define RTL8373_MACSEC_RXSYS_INNERVLAN2_PORT5_RXSYS_INNERVLAN3_MASK (0xFFFF << RTL8373_MACSEC_RXSYS_INNERVLAN2_PORT5_RXSYS_INNERVLAN3_OFFSET) + #define RTL8373_MACSEC_RXSYS_INNERVLAN2_PORT5_RXSYS_INNERVLAN2_OFFSET (0) + #define RTL8373_MACSEC_RXSYS_INNERVLAN2_PORT5_RXSYS_INNERVLAN2_MASK (0xFFFF << RTL8373_MACSEC_RXSYS_INNERVLAN2_PORT5_RXSYS_INNERVLAN2_OFFSET) + +#define RTL8373_MACSEC_RXSYS_INNERVLAN4_PORT5_ADDR (0xCAC4) + #define RTL8373_MACSEC_RXSYS_INNERVLAN4_PORT5_RXSYS_INNERVLAN5_OFFSET (16) + #define RTL8373_MACSEC_RXSYS_INNERVLAN4_PORT5_RXSYS_INNERVLAN5_MASK (0xFFFF << RTL8373_MACSEC_RXSYS_INNERVLAN4_PORT5_RXSYS_INNERVLAN5_OFFSET) + #define RTL8373_MACSEC_RXSYS_INNERVLAN4_PORT5_RXSYS_INNERVLAN4_OFFSET (0) + #define RTL8373_MACSEC_RXSYS_INNERVLAN4_PORT5_RXSYS_INNERVLAN4_MASK (0xFFFF << RTL8373_MACSEC_RXSYS_INNERVLAN4_PORT5_RXSYS_INNERVLAN4_OFFSET) + +#define RTL8373_MACSEC_RXSYS_INNERVLAN6_PORT5_ADDR (0xCAC8) + #define RTL8373_MACSEC_RXSYS_INNERVLAN6_PORT5_RXSYS_INNERVLAN7_OFFSET (16) + #define RTL8373_MACSEC_RXSYS_INNERVLAN6_PORT5_RXSYS_INNERVLAN7_MASK (0xFFFF << RTL8373_MACSEC_RXSYS_INNERVLAN6_PORT5_RXSYS_INNERVLAN7_OFFSET) + #define RTL8373_MACSEC_RXSYS_INNERVLAN6_PORT5_RXSYS_INNERVLAN6_OFFSET (0) + #define RTL8373_MACSEC_RXSYS_INNERVLAN6_PORT5_RXSYS_INNERVLAN6_MASK (0xFFFF << RTL8373_MACSEC_RXSYS_INNERVLAN6_PORT5_RXSYS_INNERVLAN6_OFFSET) + +#define RTL8373_MACSEC_RXSYS_CFG4_PORT5_ADDR (0xCACC) + #define RTL8373_MACSEC_RXSYS_CFG4_PORT5_RXSYS_LPIEXIT_T_OFFSET (16) + #define RTL8373_MACSEC_RXSYS_CFG4_PORT5_RXSYS_LPIEXIT_T_MASK (0x7FFF << RTL8373_MACSEC_RXSYS_CFG4_PORT5_RXSYS_LPIEXIT_T_OFFSET) + #define RTL8373_MACSEC_RXSYS_CFG4_PORT5_RXSYS_FIFO_FTUNE_OFFSET (8) + #define RTL8373_MACSEC_RXSYS_CFG4_PORT5_RXSYS_FIFO_FTUNE_MASK (0xFF << RTL8373_MACSEC_RXSYS_CFG4_PORT5_RXSYS_FIFO_FTUNE_OFFSET) + #define RTL8373_MACSEC_RXSYS_CFG4_PORT5_RXSYS_FIFO_TSHD_OFFSET (0) + #define RTL8373_MACSEC_RXSYS_CFG4_PORT5_RXSYS_FIFO_TSHD_MASK (0xFF << RTL8373_MACSEC_RXSYS_CFG4_PORT5_RXSYS_FIFO_TSHD_OFFSET) + +#define RTL8373_MACSEC_RXSYS_CFG6_PORT5_ADDR (0xCAD0) + #define RTL8373_MACSEC_RXSYS_CFG6_PORT5_RXSYS_AVG_IPG_OFFSET (0) + #define RTL8373_MACSEC_RXSYS_CFG6_PORT5_RXSYS_AVG_IPG_MASK (0xF << RTL8373_MACSEC_RXSYS_CFG6_PORT5_RXSYS_AVG_IPG_OFFSET) + +#define RTL8373_MACSEC_REG_GLB_SET1_PORT6_ADDR (0xD0F0) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT6_RX_GATING_OFFSET (31) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT6_RX_GATING_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT6_RX_GATING_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT6_TX_GATING_OFFSET (30) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT6_TX_GATING_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT6_TX_GATING_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT6_DBG_EN_OFFSET (29) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT6_DBG_EN_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT6_DBG_EN_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT6_DBG_SEL_OFFSET (24) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT6_DBG_SEL_MASK (0x1F << RTL8373_MACSEC_REG_GLB_SET1_PORT6_DBG_SEL_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT6_DBG_SPD_SEL_OFFSET (23) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT6_DBG_SPD_SEL_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT6_DBG_SPD_SEL_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT6_RX_G_IOSAMEPMB_OFFSET (22) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT6_RX_G_IOSAMEPMB_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT6_RX_G_IOSAMEPMB_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT6_TX_G_IOSAMEPMB_OFFSET (21) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT6_TX_G_IOSAMEPMB_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT6_TX_G_IOSAMEPMB_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT6_MIBCNT_MODE_OFFSET (20) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT6_MIBCNT_MODE_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT6_MIBCNT_MODE_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT6_RX_XGDIC_EN_OFFSET (18) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT6_RX_XGDIC_EN_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT6_RX_XGDIC_EN_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT6_TX_XGDIC_EN_OFFSET (17) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT6_TX_XGDIC_EN_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT6_TX_XGDIC_EN_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT6_MIBCNT_SWRST_N_OFFSET (16) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT6_MIBCNT_SWRST_N_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT6_MIBCNT_SWRST_N_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT6_PTPBYPASS_EN_OFFSET (14) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT6_PTPBYPASS_EN_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT6_PTPBYPASS_EN_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT6_SYSLPBK_EN_OFFSET (13) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT6_SYSLPBK_EN_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT6_SYSLPBK_EN_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT6_PHY2MAC_EN_OFFSET (12) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT6_PHY2MAC_EN_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT6_PHY2MAC_EN_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT6_RX_IPRST_N_OFFSET (11) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT6_RX_IPRST_N_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT6_RX_IPRST_N_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT6_RX_IPBYPASS_EN_OFFSET (10) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT6_RX_IPBYPASS_EN_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT6_RX_IPBYPASS_EN_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT6_RX_MACSECBYPASS_EN_OFFSET (9) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT6_RX_MACSECBYPASS_EN_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT6_RX_MACSECBYPASS_EN_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT6_RX_SWRST_EN_OFFSET (8) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT6_RX_SWRST_EN_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT6_RX_SWRST_EN_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT6_LINELPBK_EN_OFFSET (5) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT6_LINELPBK_EN_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT6_LINELPBK_EN_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT6_MAC2PHY_EN_OFFSET (4) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT6_MAC2PHY_EN_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT6_MAC2PHY_EN_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT6_TX_IPRST_N_OFFSET (3) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT6_TX_IPRST_N_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT6_TX_IPRST_N_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT6_TX_IPBYPASS_EN_OFFSET (2) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT6_TX_IPBYPASS_EN_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT6_TX_IPBYPASS_EN_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT6_TX_MACSECBYPASS_EN_OFFSET (1) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT6_TX_MACSECBYPASS_EN_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT6_TX_MACSECBYPASS_EN_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT6_TX_SWRST_EN_OFFSET (0) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT6_TX_SWRST_EN_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT6_TX_SWRST_EN_OFFSET) + +#define RTL8373_MACSEC_REG_GLB_IMR_PORT6_ADDR (0xD0F4) + #define RTL8373_MACSEC_REG_GLB_IMR_PORT6_RX_IPILOCK_XG_IMR_OFFSET (11) + #define RTL8373_MACSEC_REG_GLB_IMR_PORT6_RX_IPILOCK_XG_IMR_MASK (0x1 << RTL8373_MACSEC_REG_GLB_IMR_PORT6_RX_IPILOCK_XG_IMR_OFFSET) + #define RTL8373_MACSEC_REG_GLB_IMR_PORT6_RX_IPILOCK_IMR_OFFSET (10) + #define RTL8373_MACSEC_REG_GLB_IMR_PORT6_RX_IPILOCK_IMR_MASK (0x1 << RTL8373_MACSEC_REG_GLB_IMR_PORT6_RX_IPILOCK_IMR_OFFSET) + #define RTL8373_MACSEC_REG_GLB_IMR_PORT6_RX_IPISECFAIL_IMR_OFFSET (9) + #define RTL8373_MACSEC_REG_GLB_IMR_PORT6_RX_IPISECFAIL_IMR_MASK (0x1 << RTL8373_MACSEC_REG_GLB_IMR_PORT6_RX_IPISECFAIL_IMR_OFFSET) + #define RTL8373_MACSEC_REG_GLB_IMR_PORT6_RX_IPI_GLB_IMR_OFFSET (8) + #define RTL8373_MACSEC_REG_GLB_IMR_PORT6_RX_IPI_GLB_IMR_MASK (0x1 << RTL8373_MACSEC_REG_GLB_IMR_PORT6_RX_IPI_GLB_IMR_OFFSET) + #define RTL8373_MACSEC_REG_GLB_IMR_PORT6_TX_IPELOCK_XG_IMR_OFFSET (3) + #define RTL8373_MACSEC_REG_GLB_IMR_PORT6_TX_IPELOCK_XG_IMR_MASK (0x1 << RTL8373_MACSEC_REG_GLB_IMR_PORT6_TX_IPELOCK_XG_IMR_OFFSET) + #define RTL8373_MACSEC_REG_GLB_IMR_PORT6_TX_IPELOCK_IMR_OFFSET (2) + #define RTL8373_MACSEC_REG_GLB_IMR_PORT6_TX_IPELOCK_IMR_MASK (0x1 << RTL8373_MACSEC_REG_GLB_IMR_PORT6_TX_IPELOCK_IMR_OFFSET) + #define RTL8373_MACSEC_REG_GLB_IMR_PORT6_TX_IPESECFAIL_IMR_OFFSET (1) + #define RTL8373_MACSEC_REG_GLB_IMR_PORT6_TX_IPESECFAIL_IMR_MASK (0x1 << RTL8373_MACSEC_REG_GLB_IMR_PORT6_TX_IPESECFAIL_IMR_OFFSET) + #define RTL8373_MACSEC_REG_GLB_IMR_PORT6_TX_IPE_GLB_IMR_OFFSET (0) + #define RTL8373_MACSEC_REG_GLB_IMR_PORT6_TX_IPE_GLB_IMR_MASK (0x1 << RTL8373_MACSEC_REG_GLB_IMR_PORT6_TX_IPE_GLB_IMR_OFFSET) + +#define RTL8373_MACSEC_REG_GLB_ISR_PORT6_ADDR (0xD0F8) + #define RTL8373_MACSEC_REG_GLB_ISR_PORT6_RX_IPILOCK_XG_ISR_OFFSET (11) + #define RTL8373_MACSEC_REG_GLB_ISR_PORT6_RX_IPILOCK_XG_ISR_MASK (0x1 << RTL8373_MACSEC_REG_GLB_ISR_PORT6_RX_IPILOCK_XG_ISR_OFFSET) + #define RTL8373_MACSEC_REG_GLB_ISR_PORT6_RX_IPILOCK_ISR_OFFSET (10) + #define RTL8373_MACSEC_REG_GLB_ISR_PORT6_RX_IPILOCK_ISR_MASK (0x1 << RTL8373_MACSEC_REG_GLB_ISR_PORT6_RX_IPILOCK_ISR_OFFSET) + #define RTL8373_MACSEC_REG_GLB_ISR_PORT6_RX_IPISECFAIL_ISR_OFFSET (9) + #define RTL8373_MACSEC_REG_GLB_ISR_PORT6_RX_IPISECFAIL_ISR_MASK (0x1 << RTL8373_MACSEC_REG_GLB_ISR_PORT6_RX_IPISECFAIL_ISR_OFFSET) + #define RTL8373_MACSEC_REG_GLB_ISR_PORT6_RX_IPI_GLB_ISR_OFFSET (8) + #define RTL8373_MACSEC_REG_GLB_ISR_PORT6_RX_IPI_GLB_ISR_MASK (0x1 << RTL8373_MACSEC_REG_GLB_ISR_PORT6_RX_IPI_GLB_ISR_OFFSET) + #define RTL8373_MACSEC_REG_GLB_ISR_PORT6_TX_IPELOCK_XG_ISR_OFFSET (3) + #define RTL8373_MACSEC_REG_GLB_ISR_PORT6_TX_IPELOCK_XG_ISR_MASK (0x1 << RTL8373_MACSEC_REG_GLB_ISR_PORT6_TX_IPELOCK_XG_ISR_OFFSET) + #define RTL8373_MACSEC_REG_GLB_ISR_PORT6_TX_IPELOCK_ISR_OFFSET (2) + #define RTL8373_MACSEC_REG_GLB_ISR_PORT6_TX_IPELOCK_ISR_MASK (0x1 << RTL8373_MACSEC_REG_GLB_ISR_PORT6_TX_IPELOCK_ISR_OFFSET) + #define RTL8373_MACSEC_REG_GLB_ISR_PORT6_TX_IPESECFAIL_ISR_OFFSET (1) + #define RTL8373_MACSEC_REG_GLB_ISR_PORT6_TX_IPESECFAIL_ISR_MASK (0x1 << RTL8373_MACSEC_REG_GLB_ISR_PORT6_TX_IPESECFAIL_ISR_OFFSET) + #define RTL8373_MACSEC_REG_GLB_ISR_PORT6_TX_IPE_GLB_ISR_OFFSET (0) + #define RTL8373_MACSEC_REG_GLB_ISR_PORT6_TX_IPE_GLB_ISR_MASK (0x1 << RTL8373_MACSEC_REG_GLB_ISR_PORT6_TX_IPE_GLB_ISR_OFFSET) + +#define RTL8373_UNUSED_000C_PORT6_ADDR (0xD0FC) + #define RTL8373_UNUSED_000C_PORT6_UNUSED_000C_PORT6_OFFSET (0) + #define RTL8373_UNUSED_000C_PORT6_UNUSED_000C_PORT6_MASK (0xFFFFFFFF << RTL8373_UNUSED_000C_PORT6_UNUSED_000C_PORT6_OFFSET) + +#define RTL8373_MACSEC_PM_CTRL_PORT6_ADDR (0xD100) + #define RTL8373_MACSEC_PM_CTRL_PORT6_MACSEC_RX_ICG_EN_OFFSET (1) + #define RTL8373_MACSEC_PM_CTRL_PORT6_MACSEC_RX_ICG_EN_MASK (0x1 << RTL8373_MACSEC_PM_CTRL_PORT6_MACSEC_RX_ICG_EN_OFFSET) + #define RTL8373_MACSEC_PM_CTRL_PORT6_MACSEC_TX_ICG_EN_OFFSET (0) + #define RTL8373_MACSEC_PM_CTRL_PORT6_MACSEC_TX_ICG_EN_MASK (0x1 << RTL8373_MACSEC_PM_CTRL_PORT6_MACSEC_TX_ICG_EN_OFFSET) + +#define RTL8373_MACSEC_REG_GLB_MASK_PORT6_ADDR (0xD104) + #define RTL8373_MACSEC_REG_GLB_MASK_PORT6_RX_MTU_OFFSET (24) + #define RTL8373_MACSEC_REG_GLB_MASK_PORT6_RX_MTU_MASK (0x3F << RTL8373_MACSEC_REG_GLB_MASK_PORT6_RX_MTU_OFFSET) + #define RTL8373_MACSEC_REG_GLB_MASK_PORT6_TX_MTU_OFFSET (16) + #define RTL8373_MACSEC_REG_GLB_MASK_PORT6_TX_MTU_MASK (0x3F << RTL8373_MACSEC_REG_GLB_MASK_PORT6_TX_MTU_OFFSET) + #define RTL8373_MACSEC_REG_GLB_MASK_PORT6_RX_XGMASK_OFFSET (12) + #define RTL8373_MACSEC_REG_GLB_MASK_PORT6_RX_XGMASK_MASK (0x1 << RTL8373_MACSEC_REG_GLB_MASK_PORT6_RX_XGMASK_OFFSET) + #define RTL8373_MACSEC_REG_GLB_MASK_PORT6_RXDV_GMASK_OFFSET (8) + #define RTL8373_MACSEC_REG_GLB_MASK_PORT6_RXDV_GMASK_MASK (0x1 << RTL8373_MACSEC_REG_GLB_MASK_PORT6_RXDV_GMASK_OFFSET) + #define RTL8373_MACSEC_REG_GLB_MASK_PORT6_TX_XGMASK_OFFSET (4) + #define RTL8373_MACSEC_REG_GLB_MASK_PORT6_TX_XGMASK_MASK (0x1 << RTL8373_MACSEC_REG_GLB_MASK_PORT6_TX_XGMASK_OFFSET) + #define RTL8373_MACSEC_REG_GLB_MASK_PORT6_TXEN_GMASK_OFFSET (0) + #define RTL8373_MACSEC_REG_GLB_MASK_PORT6_TXEN_GMASK_MASK (0x1 << RTL8373_MACSEC_REG_GLB_MASK_PORT6_TXEN_GMASK_OFFSET) + +#define RTL8373_MACSEC_REG_GLB_SET4_PORT6_ADDR (0xD108) + #define RTL8373_MACSEC_REG_GLB_SET4_PORT6_TXMSKDELAY_VAL_OFFSET (16) + #define RTL8373_MACSEC_REG_GLB_SET4_PORT6_TXMSKDELAY_VAL_MASK (0x7FFF << RTL8373_MACSEC_REG_GLB_SET4_PORT6_TXMSKDELAY_VAL_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET4_PORT6_RXMSKDELAY_VAL_OFFSET (0) + #define RTL8373_MACSEC_REG_GLB_SET4_PORT6_RXMSKDELAY_VAL_MASK (0x7FFF << RTL8373_MACSEC_REG_GLB_SET4_PORT6_RXMSKDELAY_VAL_OFFSET) + +#define RTL8373_MACSEC_REG_IP_PROBE_PORT6_ADDR (0xD10C) + #define RTL8373_MACSEC_REG_IP_PROBE_PORT6_PROBE_SEL_AE_OFFSET (8) + #define RTL8373_MACSEC_REG_IP_PROBE_PORT6_PROBE_SEL_AE_MASK (0xFF << RTL8373_MACSEC_REG_IP_PROBE_PORT6_PROBE_SEL_AE_OFFSET) + #define RTL8373_MACSEC_REG_IP_PROBE_PORT6_PROBE_SEL_AI_OFFSET (0) + #define RTL8373_MACSEC_REG_IP_PROBE_PORT6_PROBE_SEL_AI_MASK (0xFF << RTL8373_MACSEC_REG_IP_PROBE_PORT6_PROBE_SEL_AI_OFFSET) + +#define RTL8373_UNUSED_0020_PORT6_ADDR (0xD110) + #define RTL8373_UNUSED_0020_PORT6_UNUSED_0020_PORT6_OFFSET (0) + #define RTL8373_UNUSED_0020_PORT6_UNUSED_0020_PORT6_MASK (0xFFFFFFFF << RTL8373_UNUSED_0020_PORT6_UNUSED_0020_PORT6_OFFSET) + +#define RTL8373_UNUSED_0024_PORT6_ADDR (0xD114) + #define RTL8373_UNUSED_0024_PORT6_UNUSED_0024_PORT6_OFFSET (0) + #define RTL8373_UNUSED_0024_PORT6_UNUSED_0024_PORT6_MASK (0xFFFFFFFF << RTL8373_UNUSED_0024_PORT6_UNUSED_0024_PORT6_OFFSET) + +#define RTL8373_MACSEC_MBIST_SA_CTRL_PORT6_ADDR (0xD118) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT6_BIST_MODE_MACSEC_SA_AE_OFFSET (29) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT6_BIST_MODE_MACSEC_SA_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_CTRL_PORT6_BIST_MODE_MACSEC_SA_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT6_DRF_BIST_MODE_MACSEC_SA_AE_OFFSET (28) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT6_DRF_BIST_MODE_MACSEC_SA_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_CTRL_PORT6_DRF_BIST_MODE_MACSEC_SA_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT6_BIST_RSTN_MACSEC_SA_AE_OFFSET (27) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT6_BIST_RSTN_MACSEC_SA_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_CTRL_PORT6_BIST_RSTN_MACSEC_SA_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT6_BIST_LOOP_MODE_MACSEC_SA_AE_OFFSET (26) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT6_BIST_LOOP_MODE_MACSEC_SA_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_CTRL_PORT6_BIST_LOOP_MODE_MACSEC_SA_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT6_DYN_READ_EN_MACSEC_SA_AE_OFFSET (25) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT6_DYN_READ_EN_MACSEC_SA_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_CTRL_PORT6_DYN_READ_EN_MACSEC_SA_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT6_DRF_TESS_RESUME_MACSEC_SA_AE_OFFSET (24) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT6_DRF_TESS_RESUME_MACSEC_SA_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_CTRL_PORT6_DRF_TESS_RESUME_MACSEC_SA_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT6_BIST_MODE_MACSEC_SA_AI_OFFSET (23) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT6_BIST_MODE_MACSEC_SA_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_CTRL_PORT6_BIST_MODE_MACSEC_SA_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT6_DRF_BIST_MODE_MACSEC_SA_AI_OFFSET (22) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT6_DRF_BIST_MODE_MACSEC_SA_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_CTRL_PORT6_DRF_BIST_MODE_MACSEC_SA_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT6_BIST_RSTN_MACSEC_SA_AI_OFFSET (21) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT6_BIST_RSTN_MACSEC_SA_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_CTRL_PORT6_BIST_RSTN_MACSEC_SA_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT6_BIST_LOOP_MODE_MACSEC_SA_AI_OFFSET (20) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT6_BIST_LOOP_MODE_MACSEC_SA_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_CTRL_PORT6_BIST_LOOP_MODE_MACSEC_SA_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT6_DYN_READ_EN_MACSEC_SA_AI_OFFSET (19) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT6_DYN_READ_EN_MACSEC_SA_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_CTRL_PORT6_DYN_READ_EN_MACSEC_SA_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT6_DRF_TESS_RESUME_MACSEC_SA_AI_OFFSET (18) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT6_DRF_TESS_RESUME_MACSEC_SA_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_CTRL_PORT6_DRF_TESS_RESUME_MACSEC_SA_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT6_MACSEC_SA_AE_ICG_EN_OFFSET (17) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT6_MACSEC_SA_AE_ICG_EN_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_CTRL_PORT6_MACSEC_SA_AE_ICG_EN_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT6_MACSEC_SA_AI_ICG_EN_OFFSET (16) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT6_MACSEC_SA_AI_ICG_EN_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_CTRL_PORT6_MACSEC_SA_AI_ICG_EN_OFFSET) + +#define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_ADDR (0xD11C) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_DRF_START_PAUSE_MACSEC_SA_AE_OFFSET (27) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_DRF_START_PAUSE_MACSEC_SA_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_DRF_START_PAUSE_MACSEC_SA_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_BIST_DONE_MACSEC_SA_AE_OFFSET (26) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_BIST_DONE_MACSEC_SA_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_BIST_DONE_MACSEC_SA_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_DRF_BIST_DONE_MACSEC_SA_AE_OFFSET (25) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_DRF_BIST_DONE_MACSEC_SA_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_DRF_BIST_DONE_MACSEC_SA_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_DRF_START_PAUSE_MACSEC_SA_AI_OFFSET (24) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_DRF_START_PAUSE_MACSEC_SA_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_DRF_START_PAUSE_MACSEC_SA_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_BIST_DONE_MACSEC_SA_AI_OFFSET (23) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_BIST_DONE_MACSEC_SA_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_BIST_DONE_MACSEC_SA_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_DRF_BIST_DONE_MACSEC_SA_AI_OFFSET (22) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_DRF_BIST_DONE_MACSEC_SA_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_DRF_BIST_DONE_MACSEC_SA_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_DRF_START_PAUSE_MACSEC_STAT_AE_OFFSET (21) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_DRF_START_PAUSE_MACSEC_STAT_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_DRF_START_PAUSE_MACSEC_STAT_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_BIST_DONE_MACSEC_STAT_AE_OFFSET (20) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_BIST_DONE_MACSEC_STAT_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_BIST_DONE_MACSEC_STAT_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_DRF_BIST_DONE_MACSEC_STAT_AE_OFFSET (19) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_DRF_BIST_DONE_MACSEC_STAT_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_DRF_BIST_DONE_MACSEC_STAT_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_DRF_START_PAUSE_MACSEC_STAT_AI_OFFSET (18) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_DRF_START_PAUSE_MACSEC_STAT_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_DRF_START_PAUSE_MACSEC_STAT_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_BIST_DONE_MACSEC_STAT_AI_OFFSET (17) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_BIST_DONE_MACSEC_STAT_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_BIST_DONE_MACSEC_STAT_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_DRF_BIST_DONE_MACSEC_STAT_AI_OFFSET (16) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_DRF_BIST_DONE_MACSEC_STAT_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_DRF_BIST_DONE_MACSEC_STAT_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_BIST_MODE_MACSEC_STAT_AE_OFFSET (13) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_BIST_MODE_MACSEC_STAT_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_BIST_MODE_MACSEC_STAT_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_DRF_BIST_MODE_MACSEC_STAT_AE_OFFSET (12) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_DRF_BIST_MODE_MACSEC_STAT_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_DRF_BIST_MODE_MACSEC_STAT_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_BIST_RSTN_MACSEC_STAT_AE_OFFSET (11) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_BIST_RSTN_MACSEC_STAT_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_BIST_RSTN_MACSEC_STAT_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_BIST_LOOP_MODE_MACSEC_STAT_AE_OFFSET (10) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_BIST_LOOP_MODE_MACSEC_STAT_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_BIST_LOOP_MODE_MACSEC_STAT_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_DYN_READ_EN_MACSEC_STAT_AE_OFFSET (9) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_DYN_READ_EN_MACSEC_STAT_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_DYN_READ_EN_MACSEC_STAT_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_DRF_TESS_RESUME_MACSEC_STAT_AE_OFFSET (8) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_DRF_TESS_RESUME_MACSEC_STAT_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_DRF_TESS_RESUME_MACSEC_STAT_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_BIST_MODE_MACSEC_STAT_AI_OFFSET (7) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_BIST_MODE_MACSEC_STAT_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_BIST_MODE_MACSEC_STAT_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_DRF_BIST_MODE_MACSEC_STAT_AI_OFFSET (6) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_DRF_BIST_MODE_MACSEC_STAT_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_DRF_BIST_MODE_MACSEC_STAT_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_BIST_RSTN_MACSEC_STAT_AI_OFFSET (5) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_BIST_RSTN_MACSEC_STAT_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_BIST_RSTN_MACSEC_STAT_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_BIST_LOOP_MODE_MACSEC_STAT_AI_OFFSET (4) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_BIST_LOOP_MODE_MACSEC_STAT_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_BIST_LOOP_MODE_MACSEC_STAT_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_DYN_READ_EN_MACSEC_STAT_AI_OFFSET (3) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_DYN_READ_EN_MACSEC_STAT_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_DYN_READ_EN_MACSEC_STAT_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_DRF_TESS_RESUME_MACSEC_STAT_AI_OFFSET (2) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_DRF_TESS_RESUME_MACSEC_STAT_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_DRF_TESS_RESUME_MACSEC_STAT_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_MACSEC_STAT_AE_ICG_EN_OFFSET (1) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_MACSEC_STAT_AE_ICG_EN_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_MACSEC_STAT_AE_ICG_EN_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_MACSEC_STAT_AI_ICG_EN_OFFSET (0) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_MACSEC_STAT_AI_ICG_EN_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT6_MACSEC_STAT_AI_ICG_EN_OFFSET) + +#define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT6_ADDR (0xD120) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT6_MACSEC_SA_AI_DVSE_OFFSET (27) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT6_MACSEC_SA_AI_DVSE_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT6_MACSEC_SA_AI_DVSE_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT6_MACSEC_SA_AI_DVS_OFFSET (23) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT6_MACSEC_SA_AI_DVS_MASK (0xF << RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT6_MACSEC_SA_AI_DVS_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT6_MACSEC_SA_AI_LS_OFFSET (22) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT6_MACSEC_SA_AI_LS_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT6_MACSEC_SA_AI_LS_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT6_MACSEC_SA_AI_DS_OFFSET (21) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT6_MACSEC_SA_AI_DS_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT6_MACSEC_SA_AI_DS_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT6_MACSEC_SA_AI_SD_OFFSET (20) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT6_MACSEC_SA_AI_SD_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT6_MACSEC_SA_AI_SD_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT6_MACSEC_SA_AI3_TEST1_OFFSET (19) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT6_MACSEC_SA_AI3_TEST1_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT6_MACSEC_SA_AI3_TEST1_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT6_MACSEC_SA_AI2_TEST1_OFFSET (18) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT6_MACSEC_SA_AI2_TEST1_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT6_MACSEC_SA_AI2_TEST1_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT6_MACSEC_SA_AI1_TEST1_OFFSET (17) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT6_MACSEC_SA_AI1_TEST1_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT6_MACSEC_SA_AI1_TEST1_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT6_MACSEC_SA_AI0_TEST1_OFFSET (16) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT6_MACSEC_SA_AI0_TEST1_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT6_MACSEC_SA_AI0_TEST1_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT6_MACSEC_SA_AE_DVSE_OFFSET (11) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT6_MACSEC_SA_AE_DVSE_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT6_MACSEC_SA_AE_DVSE_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT6_MACSEC_SA_AE_DVS_OFFSET (7) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT6_MACSEC_SA_AE_DVS_MASK (0xF << RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT6_MACSEC_SA_AE_DVS_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT6_MACSEC_SA_AE_LS_OFFSET (6) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT6_MACSEC_SA_AE_LS_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT6_MACSEC_SA_AE_LS_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT6_MACSEC_SA_AE_DS_OFFSET (5) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT6_MACSEC_SA_AE_DS_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT6_MACSEC_SA_AE_DS_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT6_MACSEC_SA_AE_SD_OFFSET (4) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT6_MACSEC_SA_AE_SD_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT6_MACSEC_SA_AE_SD_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT6_MACSEC_SA_AE3_TEST1_OFFSET (3) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT6_MACSEC_SA_AE3_TEST1_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT6_MACSEC_SA_AE3_TEST1_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT6_MACSEC_SA_AE2_TEST1_OFFSET (2) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT6_MACSEC_SA_AE2_TEST1_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT6_MACSEC_SA_AE2_TEST1_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT6_MACSEC_SA_AE1_TEST1_OFFSET (1) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT6_MACSEC_SA_AE1_TEST1_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT6_MACSEC_SA_AE1_TEST1_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT6_MACSEC_SA_AE0_TEST1_OFFSET (0) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT6_MACSEC_SA_AE0_TEST1_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT6_MACSEC_SA_AE0_TEST1_OFFSET) + +#define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT6_ADDR (0xD124) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT6_MACSEC_STAT_AI_DVSE_OFFSET (25) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT6_MACSEC_STAT_AI_DVSE_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT6_MACSEC_STAT_AI_DVSE_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT6_MACSEC_STAT_AI_DVS_OFFSET (21) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT6_MACSEC_STAT_AI_DVS_MASK (0xF << RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT6_MACSEC_STAT_AI_DVS_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT6_MACSEC_STAT_AI_LS_OFFSET (20) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT6_MACSEC_STAT_AI_LS_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT6_MACSEC_STAT_AI_LS_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT6_MACSEC_STAT_AI_DS_OFFSET (19) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT6_MACSEC_STAT_AI_DS_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT6_MACSEC_STAT_AI_DS_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT6_MACSEC_STAT_AI_SD_OFFSET (18) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT6_MACSEC_STAT_AI_SD_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT6_MACSEC_STAT_AI_SD_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT6_MACSEC_STAT_AI_TEST1_OFFSET (17) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT6_MACSEC_STAT_AI_TEST1_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT6_MACSEC_STAT_AI_TEST1_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT6_MACSEC_STAT_AI_TESTRWM_OFFSET (16) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT6_MACSEC_STAT_AI_TESTRWM_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT6_MACSEC_STAT_AI_TESTRWM_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT6_MACSEC_STAT_AE_DVSE_OFFSET (9) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT6_MACSEC_STAT_AE_DVSE_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT6_MACSEC_STAT_AE_DVSE_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT6_MACSEC_STAT_AE_DVS_OFFSET (5) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT6_MACSEC_STAT_AE_DVS_MASK (0xF << RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT6_MACSEC_STAT_AE_DVS_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT6_MACSEC_STAT_AE_LS_OFFSET (4) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT6_MACSEC_STAT_AE_LS_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT6_MACSEC_STAT_AE_LS_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT6_MACSEC_STAT_AE_DS_OFFSET (3) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT6_MACSEC_STAT_AE_DS_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT6_MACSEC_STAT_AE_DS_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT6_MACSEC_STAT_AE_SD_OFFSET (2) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT6_MACSEC_STAT_AE_SD_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT6_MACSEC_STAT_AE_SD_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT6_MACSEC_STAT_AE_TEST1_OFFSET (1) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT6_MACSEC_STAT_AE_TEST1_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT6_MACSEC_STAT_AE_TEST1_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT6_MACSEC_STAT_AE_TESTRWM_OFFSET (0) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT6_MACSEC_STAT_AE_TESTRWM_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT6_MACSEC_STAT_AE_TESTRWM_OFFSET) + +#define RTL8373_MACSEC_MBIST_SA_FAIL_PORT6_ADDR (0xD128) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT6_BIST_FAIL_MACSEC_STAT_AE_OFFSET (19) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT6_BIST_FAIL_MACSEC_STAT_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT6_BIST_FAIL_MACSEC_STAT_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT6_DRF_BIST_FAIL_MACSEC_STAT_AE_OFFSET (18) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT6_DRF_BIST_FAIL_MACSEC_STAT_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT6_DRF_BIST_FAIL_MACSEC_STAT_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT6_BIST_FAIL_MACSEC_STAT_AI_OFFSET (17) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT6_BIST_FAIL_MACSEC_STAT_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT6_BIST_FAIL_MACSEC_STAT_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT6_DRF_BIST_FAIL_MACSEC_STAT_AI_OFFSET (16) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT6_DRF_BIST_FAIL_MACSEC_STAT_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT6_DRF_BIST_FAIL_MACSEC_STAT_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT6_BIST_FAIL_MACSEC_SA_AE3_OFFSET (15) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT6_BIST_FAIL_MACSEC_SA_AE3_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT6_BIST_FAIL_MACSEC_SA_AE3_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT6_DRF_BIST_FAIL_MACSEC_SA_AE3_OFFSET (14) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT6_DRF_BIST_FAIL_MACSEC_SA_AE3_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT6_DRF_BIST_FAIL_MACSEC_SA_AE3_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT6_BIST_FAIL_MACSEC_SA_AE2_OFFSET (13) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT6_BIST_FAIL_MACSEC_SA_AE2_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT6_BIST_FAIL_MACSEC_SA_AE2_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT6_DRF_BIST_FAIL_MACSEC_SA_AE2_OFFSET (12) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT6_DRF_BIST_FAIL_MACSEC_SA_AE2_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT6_DRF_BIST_FAIL_MACSEC_SA_AE2_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT6_BIST_FAIL_MACSEC_SA_AE1_OFFSET (11) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT6_BIST_FAIL_MACSEC_SA_AE1_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT6_BIST_FAIL_MACSEC_SA_AE1_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT6_DRF_BIST_FAIL_MACSEC_SA_AE1_OFFSET (10) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT6_DRF_BIST_FAIL_MACSEC_SA_AE1_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT6_DRF_BIST_FAIL_MACSEC_SA_AE1_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT6_BIST_FAIL_MACSEC_SA_AE0_OFFSET (9) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT6_BIST_FAIL_MACSEC_SA_AE0_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT6_BIST_FAIL_MACSEC_SA_AE0_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT6_DRF_BIST_FAIL_MACSEC_SA_AE0_OFFSET (8) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT6_DRF_BIST_FAIL_MACSEC_SA_AE0_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT6_DRF_BIST_FAIL_MACSEC_SA_AE0_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT6_BIST_FAIL_MACSEC_SA_AI3_OFFSET (7) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT6_BIST_FAIL_MACSEC_SA_AI3_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT6_BIST_FAIL_MACSEC_SA_AI3_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT6_DRF_BIST_FAIL_MACSEC_SA_AI3_OFFSET (6) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT6_DRF_BIST_FAIL_MACSEC_SA_AI3_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT6_DRF_BIST_FAIL_MACSEC_SA_AI3_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT6_BIST_FAIL_MACSEC_SA_AI2_OFFSET (5) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT6_BIST_FAIL_MACSEC_SA_AI2_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT6_BIST_FAIL_MACSEC_SA_AI2_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT6_DRF_BIST_FAIL_MACSEC_SA_AI2_OFFSET (4) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT6_DRF_BIST_FAIL_MACSEC_SA_AI2_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT6_DRF_BIST_FAIL_MACSEC_SA_AI2_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT6_BIST_FAIL_MACSEC_SA_AI1_OFFSET (3) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT6_BIST_FAIL_MACSEC_SA_AI1_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT6_BIST_FAIL_MACSEC_SA_AI1_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT6_DRF_BIST_FAIL_MACSEC_SA_AI1_OFFSET (2) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT6_DRF_BIST_FAIL_MACSEC_SA_AI1_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT6_DRF_BIST_FAIL_MACSEC_SA_AI1_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT6_BIST_FAIL_MACSEC_SA_AI0_OFFSET (1) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT6_BIST_FAIL_MACSEC_SA_AI0_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT6_BIST_FAIL_MACSEC_SA_AI0_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT6_DRF_BIST_FAIL_MACSEC_SA_AI0_OFFSET (0) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT6_DRF_BIST_FAIL_MACSEC_SA_AI0_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT6_DRF_BIST_FAIL_MACSEC_SA_AI0_OFFSET) + +#define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT6_ADDR (0xD12C) + #define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT6_CFG_WATER_LEVEL_ST_OFFSET (28) + #define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT6_CFG_WATER_LEVEL_ST_MASK (0xF << RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT6_CFG_WATER_LEVEL_ST_OFFSET) + #define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT6_CFG_WATER_LEVEL_H_OFFSET (24) + #define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT6_CFG_WATER_LEVEL_H_MASK (0xF << RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT6_CFG_WATER_LEVEL_H_OFFSET) + #define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT6_CFG_WATER_LEVEL_L_OFFSET (20) + #define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT6_CFG_WATER_LEVEL_L_MASK (0xF << RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT6_CFG_WATER_LEVEL_L_OFFSET) + #define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT6_CFG_FAULT_ON_OFFSET (19) + #define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT6_CFG_FAULT_ON_MASK (0x1 << RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT6_CFG_FAULT_ON_OFFSET) + #define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT6_CFG_ERROR_ON_OFFSET (18) + #define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT6_CFG_ERROR_ON_MASK (0x1 << RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT6_CFG_ERROR_ON_OFFSET) + #define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT6_CFG_SEQ_RSV_ON_OFFSET (17) + #define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT6_CFG_SEQ_RSV_ON_MASK (0x1 << RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT6_CFG_SEQ_RSV_ON_OFFSET) + #define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT6_CFG_CLR_FIFO_OVTHR_OFFSET (16) + #define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT6_CFG_CLR_FIFO_OVTHR_MASK (0x1 << RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT6_CFG_CLR_FIFO_OVTHR_OFFSET) + #define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT6_XGLBK_FIFO_DBG_EN_OFFSET (4) + #define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT6_XGLBK_FIFO_DBG_EN_MASK (0x1 << RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT6_XGLBK_FIFO_DBG_EN_OFFSET) + #define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT6_XGLBK_FIFO_DBG_SEL_OFFSET (0) + #define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT6_XGLBK_FIFO_DBG_SEL_MASK (0xF << RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT6_XGLBK_FIFO_DBG_SEL_OFFSET) + +#define RTL8373_MACSEC_REG_RWDH_AE_PORT6_ADDR (0xD130) + #define RTL8373_MACSEC_REG_RWDH_AE_PORT6_REG_DATA_AE_L_OFFSET (16) + #define RTL8373_MACSEC_REG_RWDH_AE_PORT6_REG_DATA_AE_L_MASK (0xFFFF << RTL8373_MACSEC_REG_RWDH_AE_PORT6_REG_DATA_AE_L_OFFSET) + #define RTL8373_MACSEC_REG_RWDH_AE_PORT6_REG_DATA_AE_H_OFFSET (0) + #define RTL8373_MACSEC_REG_RWDH_AE_PORT6_REG_DATA_AE_H_MASK (0xFFFF << RTL8373_MACSEC_REG_RWDH_AE_PORT6_REG_DATA_AE_H_OFFSET) + +#define RTL8373_MACSEC_REG_ADDR_AE_PORT6_ADDR (0xD134) + #define RTL8373_MACSEC_REG_ADDR_AE_PORT6_REG_ADDR_AE_OFFSET (16) + #define RTL8373_MACSEC_REG_ADDR_AE_PORT6_REG_ADDR_AE_MASK (0xFFFF << RTL8373_MACSEC_REG_ADDR_AE_PORT6_REG_ADDR_AE_OFFSET) + +#define RTL8373_MACSEC_REG_CMD_AE_PORT6_ADDR (0xD138) + #define RTL8373_MACSEC_REG_CMD_AE_PORT6_REG_DATA_AI_H_OFFSET (16) + #define RTL8373_MACSEC_REG_CMD_AE_PORT6_REG_DATA_AI_H_MASK (0xFFFF << RTL8373_MACSEC_REG_CMD_AE_PORT6_REG_DATA_AI_H_OFFSET) + #define RTL8373_MACSEC_REG_CMD_AE_PORT6_REG_RD_REQ_AE_OFFSET (4) + #define RTL8373_MACSEC_REG_CMD_AE_PORT6_REG_RD_REQ_AE_MASK (0x1 << RTL8373_MACSEC_REG_CMD_AE_PORT6_REG_RD_REQ_AE_OFFSET) + #define RTL8373_MACSEC_REG_CMD_AE_PORT6_REG_WR_REQ_AE_OFFSET (0) + #define RTL8373_MACSEC_REG_CMD_AE_PORT6_REG_WR_REQ_AE_MASK (0x1 << RTL8373_MACSEC_REG_CMD_AE_PORT6_REG_WR_REQ_AE_OFFSET) + +#define RTL8373_MACSEC_REG_RWDL_AI_PORT6_ADDR (0xD13C) + #define RTL8373_MACSEC_REG_RWDL_AI_PORT6_REG_DATA_AI_L_OFFSET (0) + #define RTL8373_MACSEC_REG_RWDL_AI_PORT6_REG_DATA_AI_L_MASK (0xFFFF << RTL8373_MACSEC_REG_RWDL_AI_PORT6_REG_DATA_AI_L_OFFSET) + +#define RTL8373_MACSEC_REG_ADDR_AI_PORT6_ADDR (0xD140) + #define RTL8373_MACSEC_REG_ADDR_AI_PORT6_REG_RD_REQ_AI_OFFSET (20) + #define RTL8373_MACSEC_REG_ADDR_AI_PORT6_REG_RD_REQ_AI_MASK (0x1 << RTL8373_MACSEC_REG_ADDR_AI_PORT6_REG_RD_REQ_AI_OFFSET) + #define RTL8373_MACSEC_REG_ADDR_AI_PORT6_REG_WR_REQ_AI_OFFSET (16) + #define RTL8373_MACSEC_REG_ADDR_AI_PORT6_REG_WR_REQ_AI_MASK (0x1 << RTL8373_MACSEC_REG_ADDR_AI_PORT6_REG_WR_REQ_AI_OFFSET) + #define RTL8373_MACSEC_REG_ADDR_AI_PORT6_REG_ADDR_AI_OFFSET (0) + #define RTL8373_MACSEC_REG_ADDR_AI_PORT6_REG_ADDR_AI_MASK (0xFFFF << RTL8373_MACSEC_REG_ADDR_AI_PORT6_REG_ADDR_AI_OFFSET) + +#define RTL8373_MACSEC_REG_RWD_PTP_PORT6_ADDR (0xD144) + #define RTL8373_MACSEC_REG_RWD_PTP_PORT6_REG_ADDR_PTP_OFFSET (16) + #define RTL8373_MACSEC_REG_RWD_PTP_PORT6_REG_ADDR_PTP_MASK (0xFFFF << RTL8373_MACSEC_REG_RWD_PTP_PORT6_REG_ADDR_PTP_OFFSET) + #define RTL8373_MACSEC_REG_RWD_PTP_PORT6_REG_DATA_PTP_OFFSET (0) + #define RTL8373_MACSEC_REG_RWD_PTP_PORT6_REG_DATA_PTP_MASK (0xFFFF << RTL8373_MACSEC_REG_RWD_PTP_PORT6_REG_DATA_PTP_OFFSET) + +#define RTL8373_MACSEC_REG_CMD_PTP_PORT6_ADDR (0xD148) + #define RTL8373_MACSEC_REG_CMD_PTP_PORT6_REG_RD_REQ_PTP_OFFSET (4) + #define RTL8373_MACSEC_REG_CMD_PTP_PORT6_REG_RD_REQ_PTP_MASK (0x1 << RTL8373_MACSEC_REG_CMD_PTP_PORT6_REG_RD_REQ_PTP_OFFSET) + #define RTL8373_MACSEC_REG_CMD_PTP_PORT6_REG_WR_REQ_PTP_OFFSET (0) + #define RTL8373_MACSEC_REG_CMD_PTP_PORT6_REG_WR_REQ_PTP_MASK (0x1 << RTL8373_MACSEC_REG_CMD_PTP_PORT6_REG_WR_REQ_PTP_OFFSET) + +#define RTL8373_UNUSED_005C_PORT6_ADDR (0xD14C) + #define RTL8373_UNUSED_005C_PORT6_UNUSED_005C_PORT6_OFFSET (0) + #define RTL8373_UNUSED_005C_PORT6_UNUSED_005C_PORT6_MASK (0xFFFFFFFF << RTL8373_UNUSED_005C_PORT6_UNUSED_005C_PORT6_OFFSET) + +#define RTL8373_UNUSED_0060_PORT6_ADDR (0xD150) + #define RTL8373_UNUSED_0060_PORT6_UNUSED_0060_PORT6_OFFSET (0) + #define RTL8373_UNUSED_0060_PORT6_UNUSED_0060_PORT6_MASK (0xFFFFFFFF << RTL8373_UNUSED_0060_PORT6_UNUSED_0060_PORT6_OFFSET) + +#define RTL8373_UNUSED_0064_PORT6_ADDR (0xD154) + #define RTL8373_UNUSED_0064_PORT6_UNUSED_0064_PORT6_OFFSET (0) + #define RTL8373_UNUSED_0064_PORT6_UNUSED_0064_PORT6_MASK (0xFFFFFFFF << RTL8373_UNUSED_0064_PORT6_UNUSED_0064_PORT6_OFFSET) + +#define RTL8373_UNUSED_0068_PORT6_ADDR (0xD158) + #define RTL8373_UNUSED_0068_PORT6_UNUSED_0068_PORT6_OFFSET (0) + #define RTL8373_UNUSED_0068_PORT6_UNUSED_0068_PORT6_MASK (0xFFFFFFFF << RTL8373_UNUSED_0068_PORT6_UNUSED_0068_PORT6_OFFSET) + +#define RTL8373_UNUSED_006C_PORT6_ADDR (0xD15C) + #define RTL8373_UNUSED_006C_PORT6_UNUSED_006C_PORT6_OFFSET (0) + #define RTL8373_UNUSED_006C_PORT6_UNUSED_006C_PORT6_MASK (0xFFFFFFFF << RTL8373_UNUSED_006C_PORT6_UNUSED_006C_PORT6_OFFSET) + +#define RTL8373_UNUSED_0070_PORT6_ADDR (0xD160) + #define RTL8373_UNUSED_0070_PORT6_UNUSED_0070_PORT6_OFFSET (0) + #define RTL8373_UNUSED_0070_PORT6_UNUSED_0070_PORT6_MASK (0xFFFFFFFF << RTL8373_UNUSED_0070_PORT6_UNUSED_0070_PORT6_OFFSET) + +#define RTL8373_UNUSED_0074_PORT6_ADDR (0xD164) + #define RTL8373_UNUSED_0074_PORT6_UNUSED_0074_PORT6_OFFSET (0) + #define RTL8373_UNUSED_0074_PORT6_UNUSED_0074_PORT6_MASK (0xFFFFFFFF << RTL8373_UNUSED_0074_PORT6_UNUSED_0074_PORT6_OFFSET) + +#define RTL8373_RESERVED_0078_PORT6_ADDR (0xD168) + #define RTL8373_RESERVED_0078_PORT6_RESERVED_0078_PORT6_OFFSET (0) + #define RTL8373_RESERVED_0078_PORT6_RESERVED_0078_PORT6_MASK (0xFFFFFFFF << RTL8373_RESERVED_0078_PORT6_RESERVED_0078_PORT6_OFFSET) + +#define RTL8373_RESERVED_007C_PORT6_ADDR (0xD16C) + #define RTL8373_RESERVED_007C_PORT6_RESERVED_007C_PORT6_OFFSET (0) + #define RTL8373_RESERVED_007C_PORT6_RESERVED_007C_PORT6_MASK (0xFFFFFFFF << RTL8373_RESERVED_007C_PORT6_RESERVED_007C_PORT6_OFFSET) + +#define RTL8373_MACSEC_TXSYSCRCERR_CNT_PORT6_ADDR (0xD170) + #define RTL8373_MACSEC_TXSYSCRCERR_CNT_PORT6_TXSYS_CRCERR_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_TXSYSCRCERR_CNT_PORT6_TXSYS_CRCERR_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_TXSYSCRCERR_CNT_PORT6_TXSYS_CRCERR_CNT_H_OFFSET) + #define RTL8373_MACSEC_TXSYSCRCERR_CNT_PORT6_TXSYS_CRCERR_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_TXSYSCRCERR_CNT_PORT6_TXSYS_CRCERR_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_TXSYSCRCERR_CNT_PORT6_TXSYS_CRCERR_CNT_L_OFFSET) + +#define RTL8373_MACSEC_TXSYSPKTERR_CNT_PORT6_ADDR (0xD174) + #define RTL8373_MACSEC_TXSYSPKTERR_CNT_PORT6_TXSYS_PKTERR_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_TXSYSPKTERR_CNT_PORT6_TXSYS_PKTERR_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_TXSYSPKTERR_CNT_PORT6_TXSYS_PKTERR_CNT_H_OFFSET) + #define RTL8373_MACSEC_TXSYSPKTERR_CNT_PORT6_TXSYS_PKTERR_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_TXSYSPKTERR_CNT_PORT6_TXSYS_PKTERR_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_TXSYSPKTERR_CNT_PORT6_TXSYS_PKTERR_CNT_L_OFFSET) + +#define RTL8373_MACSEC_TXSYSOK_CNT_0_PORT6_ADDR (0xD178) + #define RTL8373_MACSEC_TXSYSOK_CNT_0_PORT6_TXSYS_OK_CNT_1_OFFSET (16) + #define RTL8373_MACSEC_TXSYSOK_CNT_0_PORT6_TXSYS_OK_CNT_1_MASK (0xFFFF << RTL8373_MACSEC_TXSYSOK_CNT_0_PORT6_TXSYS_OK_CNT_1_OFFSET) + #define RTL8373_MACSEC_TXSYSOK_CNT_0_PORT6_TXSYS_OK_CNT_0_OFFSET (0) + #define RTL8373_MACSEC_TXSYSOK_CNT_0_PORT6_TXSYS_OK_CNT_0_MASK (0xFFFF << RTL8373_MACSEC_TXSYSOK_CNT_0_PORT6_TXSYS_OK_CNT_0_OFFSET) + +#define RTL8373_MACSEC_TXSYSOK_CNT_2_PORT6_ADDR (0xD17C) + #define RTL8373_MACSEC_TXSYSOK_CNT_2_PORT6_TXSYS_OK_CNT_3_OFFSET (16) + #define RTL8373_MACSEC_TXSYSOK_CNT_2_PORT6_TXSYS_OK_CNT_3_MASK (0xFFFF << RTL8373_MACSEC_TXSYSOK_CNT_2_PORT6_TXSYS_OK_CNT_3_OFFSET) + #define RTL8373_MACSEC_TXSYSOK_CNT_2_PORT6_TXSYS_OK_CNT_2_OFFSET (0) + #define RTL8373_MACSEC_TXSYSOK_CNT_2_PORT6_TXSYS_OK_CNT_2_MASK (0xFFFF << RTL8373_MACSEC_TXSYSOK_CNT_2_PORT6_TXSYS_OK_CNT_2_OFFSET) + +#define RTL8373_MACSEC_TXSYSGERR_CNT_PORT6_ADDR (0xD180) + #define RTL8373_MACSEC_TXSYSGERR_CNT_PORT6_TXSYS_GERR_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_TXSYSGERR_CNT_PORT6_TXSYS_GERR_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_TXSYSGERR_CNT_PORT6_TXSYS_GERR_CNT_H_OFFSET) + #define RTL8373_MACSEC_TXSYSGERR_CNT_PORT6_TXSYS_GERR_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_TXSYSGERR_CNT_PORT6_TXSYS_GERR_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_TXSYSGERR_CNT_PORT6_TXSYS_GERR_CNT_L_OFFSET) + +#define RTL8373_MACSEC_TXSYSGLPIERR_CNT_PORT6_ADDR (0xD184) + #define RTL8373_MACSEC_TXSYSGLPIERR_CNT_PORT6_TXSYS_GLPIERR_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_TXSYSGLPIERR_CNT_PORT6_TXSYS_GLPIERR_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_TXSYSGLPIERR_CNT_PORT6_TXSYS_GLPIERR_CNT_H_OFFSET) + #define RTL8373_MACSEC_TXSYSGLPIERR_CNT_PORT6_TXSYS_GLPIERR_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_TXSYSGLPIERR_CNT_PORT6_TXSYS_GLPIERR_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_TXSYSGLPIERR_CNT_PORT6_TXSYS_GLPIERR_CNT_L_OFFSET) + +#define RTL8373_MACSEC_TXSYS_DBG_PORT6_ADDR (0xD188) + #define RTL8373_MACSEC_TXSYS_DBG_PORT6_TXSYS_XG2IP_FSM_OFFSET (16) + #define RTL8373_MACSEC_TXSYS_DBG_PORT6_TXSYS_XG2IP_FSM_MASK (0xF << RTL8373_MACSEC_TXSYS_DBG_PORT6_TXSYS_XG2IP_FSM_OFFSET) + #define RTL8373_MACSEC_TXSYS_DBG_PORT6_TXSYS_WRP2IP_FSM_OFFSET (0) + #define RTL8373_MACSEC_TXSYS_DBG_PORT6_TXSYS_WRP2IP_FSM_MASK (0xF << RTL8373_MACSEC_TXSYS_DBG_PORT6_TXSYS_WRP2IP_FSM_OFFSET) + +#define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT6_ADDR (0xD18C) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT6_RXSYS_UNDERRUN_CNT_INCR_OFFSET (27) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT6_RXSYS_UNDERRUN_CNT_INCR_MASK (0x1 << RTL8373_MACSEC_TX_RX_CNT_INCR_PORT6_RXSYS_UNDERRUN_CNT_INCR_OFFSET) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT6_RXSYS_DROP_CNT_INCR_OFFSET (26) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT6_RXSYS_DROP_CNT_INCR_MASK (0x1 << RTL8373_MACSEC_TX_RX_CNT_INCR_PORT6_RXSYS_DROP_CNT_INCR_OFFSET) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT6_RXSYS_PKTERR_CNT_INCR_OFFSET (25) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT6_RXSYS_PKTERR_CNT_INCR_MASK (0x1 << RTL8373_MACSEC_TX_RX_CNT_INCR_PORT6_RXSYS_PKTERR_CNT_INCR_OFFSET) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT6_RXSYS_CRCERR_CNT_INCR_OFFSET (24) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT6_RXSYS_CRCERR_CNT_INCR_MASK (0x1 << RTL8373_MACSEC_TX_RX_CNT_INCR_PORT6_RXSYS_CRCERR_CNT_INCR_OFFSET) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT6_RXLINE_OVERFLOW_CNT_INCR_OFFSET (18) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT6_RXLINE_OVERFLOW_CNT_INCR_MASK (0x1 << RTL8373_MACSEC_TX_RX_CNT_INCR_PORT6_RXLINE_OVERFLOW_CNT_INCR_OFFSET) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT6_RXLINE_PKTERR_CNT_INCR_OFFSET (17) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT6_RXLINE_PKTERR_CNT_INCR_MASK (0x1 << RTL8373_MACSEC_TX_RX_CNT_INCR_PORT6_RXLINE_PKTERR_CNT_INCR_OFFSET) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT6_RXLINE_CRCERR_CNT_INCR_OFFSET (16) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT6_RXLINE_CRCERR_CNT_INCR_MASK (0x1 << RTL8373_MACSEC_TX_RX_CNT_INCR_PORT6_RXLINE_CRCERR_CNT_INCR_OFFSET) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT6_TXLINE_UNDERRUN_CNT_INCR_OFFSET (11) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT6_TXLINE_UNDERRUN_CNT_INCR_MASK (0x1 << RTL8373_MACSEC_TX_RX_CNT_INCR_PORT6_TXLINE_UNDERRUN_CNT_INCR_OFFSET) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT6_TXLINE_DROP_CNT_INCR_OFFSET (10) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT6_TXLINE_DROP_CNT_INCR_MASK (0x1 << RTL8373_MACSEC_TX_RX_CNT_INCR_PORT6_TXLINE_DROP_CNT_INCR_OFFSET) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT6_TXLINE_PKTERR_CNT_INCR_OFFSET (9) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT6_TXLINE_PKTERR_CNT_INCR_MASK (0x1 << RTL8373_MACSEC_TX_RX_CNT_INCR_PORT6_TXLINE_PKTERR_CNT_INCR_OFFSET) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT6_TXLINE_CRCERR_CNT_INCR_OFFSET (8) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT6_TXLINE_CRCERR_CNT_INCR_MASK (0x1 << RTL8373_MACSEC_TX_RX_CNT_INCR_PORT6_TXLINE_CRCERR_CNT_INCR_OFFSET) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT6_TXSYS_OVERFLOW_CNT_INCR_OFFSET (2) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT6_TXSYS_OVERFLOW_CNT_INCR_MASK (0x1 << RTL8373_MACSEC_TX_RX_CNT_INCR_PORT6_TXSYS_OVERFLOW_CNT_INCR_OFFSET) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT6_TXSYS_PKTERR_CNT_INCR_OFFSET (1) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT6_TXSYS_PKTERR_CNT_INCR_MASK (0x1 << RTL8373_MACSEC_TX_RX_CNT_INCR_PORT6_TXSYS_PKTERR_CNT_INCR_OFFSET) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT6_TXSYS_CRCERR_CNT_INCR_OFFSET (0) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT6_TXSYS_CRCERR_CNT_INCR_MASK (0x1 << RTL8373_MACSEC_TX_RX_CNT_INCR_PORT6_TXSYS_CRCERR_CNT_INCR_OFFSET) + +#define RTL8373_MACSEC_TXLINECRCERR_CNT_PORT6_ADDR (0xD190) + #define RTL8373_MACSEC_TXLINECRCERR_CNT_PORT6_TXLINE_CRCERR_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_TXLINECRCERR_CNT_PORT6_TXLINE_CRCERR_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_TXLINECRCERR_CNT_PORT6_TXLINE_CRCERR_CNT_H_OFFSET) + #define RTL8373_MACSEC_TXLINECRCERR_CNT_PORT6_TXLINE_CRCERR_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_TXLINECRCERR_CNT_PORT6_TXLINE_CRCERR_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_TXLINECRCERR_CNT_PORT6_TXLINE_CRCERR_CNT_L_OFFSET) + +#define RTL8373_MACSEC_TXLINEPKTERR_CNT_PORT6_ADDR (0xD194) + #define RTL8373_MACSEC_TXLINEPKTERR_CNT_PORT6_TXLINE_PKTERR_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_TXLINEPKTERR_CNT_PORT6_TXLINE_PKTERR_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_TXLINEPKTERR_CNT_PORT6_TXLINE_PKTERR_CNT_H_OFFSET) + #define RTL8373_MACSEC_TXLINEPKTERR_CNT_PORT6_TXLINE_PKTERR_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_TXLINEPKTERR_CNT_PORT6_TXLINE_PKTERR_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_TXLINEPKTERR_CNT_PORT6_TXLINE_PKTERR_CNT_L_OFFSET) + +#define RTL8373_MACSEC_TXLINEOK_CNT_0_PORT6_ADDR (0xD198) + #define RTL8373_MACSEC_TXLINEOK_CNT_0_PORT6_TXLINE_OK_CNT_1_OFFSET (16) + #define RTL8373_MACSEC_TXLINEOK_CNT_0_PORT6_TXLINE_OK_CNT_1_MASK (0xFFFF << RTL8373_MACSEC_TXLINEOK_CNT_0_PORT6_TXLINE_OK_CNT_1_OFFSET) + #define RTL8373_MACSEC_TXLINEOK_CNT_0_PORT6_TXLINE_OK_CNT_0_OFFSET (0) + #define RTL8373_MACSEC_TXLINEOK_CNT_0_PORT6_TXLINE_OK_CNT_0_MASK (0xFFFF << RTL8373_MACSEC_TXLINEOK_CNT_0_PORT6_TXLINE_OK_CNT_0_OFFSET) + +#define RTL8373_MACSEC_TXLINEOK_CNT_2_PORT6_ADDR (0xD19C) + #define RTL8373_MACSEC_TXLINEOK_CNT_2_PORT6_TXLINE_OK_CNT_3_OFFSET (16) + #define RTL8373_MACSEC_TXLINEOK_CNT_2_PORT6_TXLINE_OK_CNT_3_MASK (0xFFFF << RTL8373_MACSEC_TXLINEOK_CNT_2_PORT6_TXLINE_OK_CNT_3_OFFSET) + #define RTL8373_MACSEC_TXLINEOK_CNT_2_PORT6_TXLINE_OK_CNT_2_OFFSET (0) + #define RTL8373_MACSEC_TXLINEOK_CNT_2_PORT6_TXLINE_OK_CNT_2_MASK (0xFFFF << RTL8373_MACSEC_TXLINEOK_CNT_2_PORT6_TXLINE_OK_CNT_2_OFFSET) + +#define RTL8373_MACSEC_TXLINEDROP_CNT_PORT6_ADDR (0xD1A0) + #define RTL8373_MACSEC_TXLINEDROP_CNT_PORT6_TXLINE_DROP_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_TXLINEDROP_CNT_PORT6_TXLINE_DROP_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_TXLINEDROP_CNT_PORT6_TXLINE_DROP_CNT_H_OFFSET) + #define RTL8373_MACSEC_TXLINEDROP_CNT_PORT6_TXLINE_DROP_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_TXLINEDROP_CNT_PORT6_TXLINE_DROP_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_TXLINEDROP_CNT_PORT6_TXLINE_DROP_CNT_L_OFFSET) + +#define RTL8373_MACSEC_TXLINESRT_CNT_PORT6_ADDR (0xD1A4) + #define RTL8373_MACSEC_TXLINESRT_CNT_PORT6_TXLINE_SRTPKT_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_TXLINESRT_CNT_PORT6_TXLINE_SRTPKT_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_TXLINESRT_CNT_PORT6_TXLINE_SRTPKT_CNT_H_OFFSET) + #define RTL8373_MACSEC_TXLINESRT_CNT_PORT6_TXLINE_SRTPKT_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_TXLINESRT_CNT_PORT6_TXLINE_SRTPKT_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_TXLINESRT_CNT_PORT6_TXLINE_SRTPKT_CNT_L_OFFSET) + +#define RTL8373_MACSEC_TXLINEGERR_CNT_PORT6_ADDR (0xD1A8) + #define RTL8373_MACSEC_TXLINEGERR_CNT_PORT6_TXLINE_GERR_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_TXLINEGERR_CNT_PORT6_TXLINE_GERR_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_TXLINEGERR_CNT_PORT6_TXLINE_GERR_CNT_H_OFFSET) + #define RTL8373_MACSEC_TXLINEGERR_CNT_PORT6_TXLINE_GERR_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_TXLINEGERR_CNT_PORT6_TXLINE_GERR_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_TXLINEGERR_CNT_PORT6_TXLINE_GERR_CNT_L_OFFSET) + +#define RTL8373_MACSEC_TXLINE_DBG_PORT6_ADDR (0xD1AC) + #define RTL8373_MACSEC_TXLINE_DBG_PORT6_TXLINE_IP2XG_FSM_OFFSET (16) + #define RTL8373_MACSEC_TXLINE_DBG_PORT6_TXLINE_IP2XG_FSM_MASK (0x1F << RTL8373_MACSEC_TXLINE_DBG_PORT6_TXLINE_IP2XG_FSM_OFFSET) + #define RTL8373_MACSEC_TXLINE_DBG_PORT6_TXLINE_IP2WRP_FSM_OFFSET (0) + #define RTL8373_MACSEC_TXLINE_DBG_PORT6_TXLINE_IP2WRP_FSM_MASK (0xF << RTL8373_MACSEC_TXLINE_DBG_PORT6_TXLINE_IP2WRP_FSM_OFFSET) + +#define RTL8373_MACSEC_RXLINECRCERR_CNT_PORT6_ADDR (0xD1B0) + #define RTL8373_MACSEC_RXLINECRCERR_CNT_PORT6_RXLINE_CRCERR_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_RXLINECRCERR_CNT_PORT6_RXLINE_CRCERR_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_RXLINECRCERR_CNT_PORT6_RXLINE_CRCERR_CNT_H_OFFSET) + #define RTL8373_MACSEC_RXLINECRCERR_CNT_PORT6_RXLINE_CRCERR_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_RXLINECRCERR_CNT_PORT6_RXLINE_CRCERR_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_RXLINECRCERR_CNT_PORT6_RXLINE_CRCERR_CNT_L_OFFSET) + +#define RTL8373_MACSEC_RXLINEPKTERR_CNT_PORT6_ADDR (0xD1B4) + #define RTL8373_MACSEC_RXLINEPKTERR_CNT_PORT6_RXLINE_PKTERR_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_RXLINEPKTERR_CNT_PORT6_RXLINE_PKTERR_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_RXLINEPKTERR_CNT_PORT6_RXLINE_PKTERR_CNT_H_OFFSET) + #define RTL8373_MACSEC_RXLINEPKTERR_CNT_PORT6_RXLINE_PKTERR_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_RXLINEPKTERR_CNT_PORT6_RXLINE_PKTERR_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_RXLINEPKTERR_CNT_PORT6_RXLINE_PKTERR_CNT_L_OFFSET) + +#define RTL8373_MACSEC_RXLINEOK_CNT_0_PORT6_ADDR (0xD1B8) + #define RTL8373_MACSEC_RXLINEOK_CNT_0_PORT6_RXLINE_OK_CNT_1_OFFSET (16) + #define RTL8373_MACSEC_RXLINEOK_CNT_0_PORT6_RXLINE_OK_CNT_1_MASK (0xFFFF << RTL8373_MACSEC_RXLINEOK_CNT_0_PORT6_RXLINE_OK_CNT_1_OFFSET) + #define RTL8373_MACSEC_RXLINEOK_CNT_0_PORT6_RXLINE_OK_CNT_0_OFFSET (0) + #define RTL8373_MACSEC_RXLINEOK_CNT_0_PORT6_RXLINE_OK_CNT_0_MASK (0xFFFF << RTL8373_MACSEC_RXLINEOK_CNT_0_PORT6_RXLINE_OK_CNT_0_OFFSET) + +#define RTL8373_MACSEC_RXLINEOK_CNT_2_PORT6_ADDR (0xD1BC) + #define RTL8373_MACSEC_RXLINEOK_CNT_2_PORT6_RXLINE_OK_CNT_3_OFFSET (16) + #define RTL8373_MACSEC_RXLINEOK_CNT_2_PORT6_RXLINE_OK_CNT_3_MASK (0xFFFF << RTL8373_MACSEC_RXLINEOK_CNT_2_PORT6_RXLINE_OK_CNT_3_OFFSET) + #define RTL8373_MACSEC_RXLINEOK_CNT_2_PORT6_RXLINE_OK_CNT_2_OFFSET (0) + #define RTL8373_MACSEC_RXLINEOK_CNT_2_PORT6_RXLINE_OK_CNT_2_MASK (0xFFFF << RTL8373_MACSEC_RXLINEOK_CNT_2_PORT6_RXLINE_OK_CNT_2_OFFSET) + +#define RTL8373_MACSEC_RXLINESRT_CNT_PORT6_ADDR (0xD1C0) + #define RTL8373_MACSEC_RXLINESRT_CNT_PORT6_RXLINE_SHORTPKT_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_RXLINESRT_CNT_PORT6_RXLINE_SHORTPKT_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_RXLINESRT_CNT_PORT6_RXLINE_SHORTPKT_CNT_H_OFFSET) + #define RTL8373_MACSEC_RXLINESRT_CNT_PORT6_RXLINE_SHORTPKT_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_RXLINESRT_CNT_PORT6_RXLINE_SHORTPKT_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_RXLINESRT_CNT_PORT6_RXLINE_SHORTPKT_CNT_L_OFFSET) + +#define RTL8373_MACSEC_RXLINEGERR_CNT_PORT6_ADDR (0xD1C4) + #define RTL8373_MACSEC_RXLINEGERR_CNT_PORT6_RXLINE_GERR_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_RXLINEGERR_CNT_PORT6_RXLINE_GERR_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_RXLINEGERR_CNT_PORT6_RXLINE_GERR_CNT_H_OFFSET) + #define RTL8373_MACSEC_RXLINEGERR_CNT_PORT6_RXLINE_GERR_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_RXLINEGERR_CNT_PORT6_RXLINE_GERR_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_RXLINEGERR_CNT_PORT6_RXLINE_GERR_CNT_L_OFFSET) + +#define RTL8373_MACSEC_RXLINEGLPIERR_CNT_PORT6_ADDR (0xD1C8) + #define RTL8373_MACSEC_RXLINEGLPIERR_CNT_PORT6_RXLINE_GLPIERR_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_RXLINEGLPIERR_CNT_PORT6_RXLINE_GLPIERR_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_RXLINEGLPIERR_CNT_PORT6_RXLINE_GLPIERR_CNT_H_OFFSET) + #define RTL8373_MACSEC_RXLINEGLPIERR_CNT_PORT6_RXLINE_GLPIERR_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_RXLINEGLPIERR_CNT_PORT6_RXLINE_GLPIERR_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_RXLINEGLPIERR_CNT_PORT6_RXLINE_GLPIERR_CNT_L_OFFSET) + +#define RTL8373_MACSEC_RXLINE_DBG_PORT6_ADDR (0xD1CC) + #define RTL8373_MACSEC_RXLINE_DBG_PORT6_RXLINE_XG2IP_FSM_OFFSET (16) + #define RTL8373_MACSEC_RXLINE_DBG_PORT6_RXLINE_XG2IP_FSM_MASK (0xF << RTL8373_MACSEC_RXLINE_DBG_PORT6_RXLINE_XG2IP_FSM_OFFSET) + #define RTL8373_MACSEC_RXLINE_DBG_PORT6_RXLINE_WRP2IP_FSM_OFFSET (0) + #define RTL8373_MACSEC_RXLINE_DBG_PORT6_RXLINE_WRP2IP_FSM_MASK (0xF << RTL8373_MACSEC_RXLINE_DBG_PORT6_RXLINE_WRP2IP_FSM_OFFSET) + +#define RTL8373_MACSEC_RXSYSCRCERR_CNT_PORT6_ADDR (0xD1D0) + #define RTL8373_MACSEC_RXSYSCRCERR_CNT_PORT6_RXSYS_CRCERR_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_RXSYSCRCERR_CNT_PORT6_RXSYS_CRCERR_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_RXSYSCRCERR_CNT_PORT6_RXSYS_CRCERR_CNT_H_OFFSET) + #define RTL8373_MACSEC_RXSYSCRCERR_CNT_PORT6_RXSYS_CRCERR_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_RXSYSCRCERR_CNT_PORT6_RXSYS_CRCERR_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_RXSYSCRCERR_CNT_PORT6_RXSYS_CRCERR_CNT_L_OFFSET) + +#define RTL8373_MACSEC_RXSYSPKTERR_CNT_PORT6_ADDR (0xD1D4) + #define RTL8373_MACSEC_RXSYSPKTERR_CNT_PORT6_RXSYS_PKTERR_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_RXSYSPKTERR_CNT_PORT6_RXSYS_PKTERR_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_RXSYSPKTERR_CNT_PORT6_RXSYS_PKTERR_CNT_H_OFFSET) + #define RTL8373_MACSEC_RXSYSPKTERR_CNT_PORT6_RXSYS_PKTERR_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_RXSYSPKTERR_CNT_PORT6_RXSYS_PKTERR_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_RXSYSPKTERR_CNT_PORT6_RXSYS_PKTERR_CNT_L_OFFSET) + +#define RTL8373_MACSEC_RXSYSOK_CNT_0_PORT6_ADDR (0xD1D8) + #define RTL8373_MACSEC_RXSYSOK_CNT_0_PORT6_RXSYS_OK_CNT_1_OFFSET (16) + #define RTL8373_MACSEC_RXSYSOK_CNT_0_PORT6_RXSYS_OK_CNT_1_MASK (0xFFFF << RTL8373_MACSEC_RXSYSOK_CNT_0_PORT6_RXSYS_OK_CNT_1_OFFSET) + #define RTL8373_MACSEC_RXSYSOK_CNT_0_PORT6_RXSYS_OK_CNT_0_OFFSET (0) + #define RTL8373_MACSEC_RXSYSOK_CNT_0_PORT6_RXSYS_OK_CNT_0_MASK (0xFFFF << RTL8373_MACSEC_RXSYSOK_CNT_0_PORT6_RXSYS_OK_CNT_0_OFFSET) + +#define RTL8373_MACSEC_RXSYSOK_CNT_2_PORT6_ADDR (0xD1DC) + #define RTL8373_MACSEC_RXSYSOK_CNT_2_PORT6_RXSYS_OK_CNT_3_OFFSET (16) + #define RTL8373_MACSEC_RXSYSOK_CNT_2_PORT6_RXSYS_OK_CNT_3_MASK (0xFFFF << RTL8373_MACSEC_RXSYSOK_CNT_2_PORT6_RXSYS_OK_CNT_3_OFFSET) + #define RTL8373_MACSEC_RXSYSOK_CNT_2_PORT6_RXSYS_OK_CNT_2_OFFSET (0) + #define RTL8373_MACSEC_RXSYSOK_CNT_2_PORT6_RXSYS_OK_CNT_2_MASK (0xFFFF << RTL8373_MACSEC_RXSYSOK_CNT_2_PORT6_RXSYS_OK_CNT_2_OFFSET) + +#define RTL8373_MACSEC_RXSYSDROP_CNT_PORT6_ADDR (0xD1E0) + #define RTL8373_MACSEC_RXSYSDROP_CNT_PORT6_RXSYS_DROP_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_RXSYSDROP_CNT_PORT6_RXSYS_DROP_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_RXSYSDROP_CNT_PORT6_RXSYS_DROP_CNT_H_OFFSET) + #define RTL8373_MACSEC_RXSYSDROP_CNT_PORT6_RXSYS_DROP_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_RXSYSDROP_CNT_PORT6_RXSYS_DROP_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_RXSYSDROP_CNT_PORT6_RXSYS_DROP_CNT_L_OFFSET) + +#define RTL8373_MACSEC_RXSYSSRT_CNT_PORT6_ADDR (0xD1E4) + #define RTL8373_MACSEC_RXSYSSRT_CNT_PORT6_RXSYS_DECRYPTSRT_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_RXSYSSRT_CNT_PORT6_RXSYS_DECRYPTSRT_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_RXSYSSRT_CNT_PORT6_RXSYS_DECRYPTSRT_CNT_H_OFFSET) + #define RTL8373_MACSEC_RXSYSSRT_CNT_PORT6_RXSYS_DECRYPTSRT_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_RXSYSSRT_CNT_PORT6_RXSYS_DECRYPTSRT_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_RXSYSSRT_CNT_PORT6_RXSYS_DECRYPTSRT_CNT_L_OFFSET) + +#define RTL8373_MACSEC_RXSYSGERR_CNT_PORT6_ADDR (0xD1E8) + #define RTL8373_MACSEC_RXSYSGERR_CNT_PORT6_RXSYS_GERR_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_RXSYSGERR_CNT_PORT6_RXSYS_GERR_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_RXSYSGERR_CNT_PORT6_RXSYS_GERR_CNT_H_OFFSET) + #define RTL8373_MACSEC_RXSYSGERR_CNT_PORT6_RXSYS_GERR_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_RXSYSGERR_CNT_PORT6_RXSYS_GERR_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_RXSYSGERR_CNT_PORT6_RXSYS_GERR_CNT_L_OFFSET) + +#define RTL8373_MACSEC_RXSYS_DBG_PORT6_ADDR (0xD1EC) + #define RTL8373_MACSEC_RXSYS_DBG_PORT6_RXSYS_IP2XG_FSM_OFFSET (16) + #define RTL8373_MACSEC_RXSYS_DBG_PORT6_RXSYS_IP2XG_FSM_MASK (0x1F << RTL8373_MACSEC_RXSYS_DBG_PORT6_RXSYS_IP2XG_FSM_OFFSET) + #define RTL8373_MACSEC_RXSYS_DBG_PORT6_RXSYS_IP2WRP_FSM_OFFSET (0) + #define RTL8373_MACSEC_RXSYS_DBG_PORT6_RXSYS_IP2WRP_FSM_MASK (0xF << RTL8373_MACSEC_RXSYS_DBG_PORT6_RXSYS_IP2WRP_FSM_OFFSET) + +#define RTL8373_MACSEC_TXSYS_CFG1_PORT6_ADDR (0xD1F0) + #define RTL8373_MACSEC_TXSYS_CFG1_PORT6_TXSYS_XGMINIFG_OFFSET (16) + #define RTL8373_MACSEC_TXSYS_CFG1_PORT6_TXSYS_XGMINIFG_MASK (0x1F << RTL8373_MACSEC_TXSYS_CFG1_PORT6_TXSYS_XGMINIFG_OFFSET) + #define RTL8373_MACSEC_TXSYS_CFG1_PORT6_TXSYS_MINIFG_OFFSET (8) + #define RTL8373_MACSEC_TXSYS_CFG1_PORT6_TXSYS_MINIFG_MASK (0xF << RTL8373_MACSEC_TXSYS_CFG1_PORT6_TXSYS_MINIFG_OFFSET) + #define RTL8373_MACSEC_TXSYS_CFG1_PORT6_TXSYS_PMBNUM_OFFSET (0) + #define RTL8373_MACSEC_TXSYS_CFG1_PORT6_TXSYS_PMBNUM_MASK (0x7 << RTL8373_MACSEC_TXSYS_CFG1_PORT6_TXSYS_PMBNUM_OFFSET) + +#define RTL8373_MACSEC_TXSYS_PTPCFG_PORT6_ADDR (0xD1F4) + #define RTL8373_MACSEC_TXSYS_PTPCFG_PORT6_TXSYS_OUTERVLAN1_OFFSET (16) + #define RTL8373_MACSEC_TXSYS_PTPCFG_PORT6_TXSYS_OUTERVLAN1_MASK (0xFFFF << RTL8373_MACSEC_TXSYS_PTPCFG_PORT6_TXSYS_OUTERVLAN1_OFFSET) + #define RTL8373_MACSEC_TXSYS_PTPCFG_PORT6_PTP_UDP_EN_OFFSET (13) + #define RTL8373_MACSEC_TXSYS_PTPCFG_PORT6_PTP_UDP_EN_MASK (0x1 << RTL8373_MACSEC_TXSYS_PTPCFG_PORT6_PTP_UDP_EN_OFFSET) + #define RTL8373_MACSEC_TXSYS_PTPCFG_PORT6_PTP_ETH_EN_OFFSET (12) + #define RTL8373_MACSEC_TXSYS_PTPCFG_PORT6_PTP_ETH_EN_MASK (0x1 << RTL8373_MACSEC_TXSYS_PTPCFG_PORT6_PTP_ETH_EN_OFFSET) + #define RTL8373_MACSEC_TXSYS_PTPCFG_PORT6_TXSYS_PTPCRYPT_EN_OFFSET (8) + #define RTL8373_MACSEC_TXSYS_PTPCFG_PORT6_TXSYS_PTPCRYPT_EN_MASK (0x1 << RTL8373_MACSEC_TXSYS_PTPCFG_PORT6_TXSYS_PTPCRYPT_EN_OFFSET) + #define RTL8373_MACSEC_TXSYS_PTPCFG_PORT6_TXSYS_FLOWID_OFFSET (0) + #define RTL8373_MACSEC_TXSYS_PTPCFG_PORT6_TXSYS_FLOWID_MASK (0x3F << RTL8373_MACSEC_TXSYS_PTPCFG_PORT6_TXSYS_FLOWID_OFFSET) + +#define RTL8373_MACSEC_TXSYS_OUTERVLAN2_PORT6_ADDR (0xD1F8) + #define RTL8373_MACSEC_TXSYS_OUTERVLAN2_PORT6_TXSYS_OUTERVLAN3_OFFSET (16) + #define RTL8373_MACSEC_TXSYS_OUTERVLAN2_PORT6_TXSYS_OUTERVLAN3_MASK (0xFFFF << RTL8373_MACSEC_TXSYS_OUTERVLAN2_PORT6_TXSYS_OUTERVLAN3_OFFSET) + #define RTL8373_MACSEC_TXSYS_OUTERVLAN2_PORT6_TXSYS_OUTERVLAN2_OFFSET (0) + #define RTL8373_MACSEC_TXSYS_OUTERVLAN2_PORT6_TXSYS_OUTERVLAN2_MASK (0xFFFF << RTL8373_MACSEC_TXSYS_OUTERVLAN2_PORT6_TXSYS_OUTERVLAN2_OFFSET) + +#define RTL8373_MACSEC_TXSYS_OUTERVLAN4_PORT6_ADDR (0xD1FC) + #define RTL8373_MACSEC_TXSYS_OUTERVLAN4_PORT6_TXSYS_INNERVLAN1_OFFSET (16) + #define RTL8373_MACSEC_TXSYS_OUTERVLAN4_PORT6_TXSYS_INNERVLAN1_MASK (0xFFFF << RTL8373_MACSEC_TXSYS_OUTERVLAN4_PORT6_TXSYS_INNERVLAN1_OFFSET) + #define RTL8373_MACSEC_TXSYS_OUTERVLAN4_PORT6_TXSYS_OUTERVLAN4_OFFSET (0) + #define RTL8373_MACSEC_TXSYS_OUTERVLAN4_PORT6_TXSYS_OUTERVLAN4_MASK (0xFFFF << RTL8373_MACSEC_TXSYS_OUTERVLAN4_PORT6_TXSYS_OUTERVLAN4_OFFSET) + +#define RTL8373_MACSEC_TXSYS_INNERVLAN2_PORT6_ADDR (0xD200) + #define RTL8373_MACSEC_TXSYS_INNERVLAN2_PORT6_TXSYS_INNERVLAN3_OFFSET (16) + #define RTL8373_MACSEC_TXSYS_INNERVLAN2_PORT6_TXSYS_INNERVLAN3_MASK (0xFFFF << RTL8373_MACSEC_TXSYS_INNERVLAN2_PORT6_TXSYS_INNERVLAN3_OFFSET) + #define RTL8373_MACSEC_TXSYS_INNERVLAN2_PORT6_TXSYS_INNERVLAN2_OFFSET (0) + #define RTL8373_MACSEC_TXSYS_INNERVLAN2_PORT6_TXSYS_INNERVLAN2_MASK (0xFFFF << RTL8373_MACSEC_TXSYS_INNERVLAN2_PORT6_TXSYS_INNERVLAN2_OFFSET) + +#define RTL8373_MACSEC_TXSYS_INNERVLAN4_PORT6_ADDR (0xD204) + #define RTL8373_MACSEC_TXSYS_INNERVLAN4_PORT6_TXSYS_INNERVLAN5_OFFSET (16) + #define RTL8373_MACSEC_TXSYS_INNERVLAN4_PORT6_TXSYS_INNERVLAN5_MASK (0xFFFF << RTL8373_MACSEC_TXSYS_INNERVLAN4_PORT6_TXSYS_INNERVLAN5_OFFSET) + #define RTL8373_MACSEC_TXSYS_INNERVLAN4_PORT6_TXSYS_INNERVLAN4_OFFSET (0) + #define RTL8373_MACSEC_TXSYS_INNERVLAN4_PORT6_TXSYS_INNERVLAN4_MASK (0xFFFF << RTL8373_MACSEC_TXSYS_INNERVLAN4_PORT6_TXSYS_INNERVLAN4_OFFSET) + +#define RTL8373_MACSEC_TXSYS_INNERVLAN6_PORT6_ADDR (0xD208) + #define RTL8373_MACSEC_TXSYS_INNERVLAN6_PORT6_TXSYS_INNERVLAN7_OFFSET (16) + #define RTL8373_MACSEC_TXSYS_INNERVLAN6_PORT6_TXSYS_INNERVLAN7_MASK (0xFFFF << RTL8373_MACSEC_TXSYS_INNERVLAN6_PORT6_TXSYS_INNERVLAN7_OFFSET) + #define RTL8373_MACSEC_TXSYS_INNERVLAN6_PORT6_TXSYS_INNERVLAN6_OFFSET (0) + #define RTL8373_MACSEC_TXSYS_INNERVLAN6_PORT6_TXSYS_INNERVLAN6_MASK (0xFFFF << RTL8373_MACSEC_TXSYS_INNERVLAN6_PORT6_TXSYS_INNERVLAN6_OFFSET) + +#define RTL8373_UNUSED_011C_PORT6_ADDR (0xD20C) + #define RTL8373_UNUSED_011C_PORT6_UNUSED_011C_PORT6_OFFSET (0) + #define RTL8373_UNUSED_011C_PORT6_UNUSED_011C_PORT6_MASK (0xFFFFFFFF << RTL8373_UNUSED_011C_PORT6_UNUSED_011C_PORT6_OFFSET) + +#define RTL8373_UNUSED_0120_PORT6_ADDR (0xD210) + #define RTL8373_UNUSED_0120_PORT6_UNUSED_0120_PORT6_OFFSET (0) + #define RTL8373_UNUSED_0120_PORT6_UNUSED_0120_PORT6_MASK (0xFFFFFFFF << RTL8373_UNUSED_0120_PORT6_UNUSED_0120_PORT6_OFFSET) + +#define RTL8373_UNUSED_0124_PORT6_ADDR (0xD214) + #define RTL8373_UNUSED_0124_PORT6_UNUSED_0124_PORT6_OFFSET (0) + #define RTL8373_UNUSED_0124_PORT6_UNUSED_0124_PORT6_MASK (0xFFFFFFFF << RTL8373_UNUSED_0124_PORT6_UNUSED_0124_PORT6_OFFSET) + +#define RTL8373_UNUSED_0128_PORT6_ADDR (0xD218) + #define RTL8373_UNUSED_0128_PORT6_UNUSED_0128_PORT6_OFFSET (0) + #define RTL8373_UNUSED_0128_PORT6_UNUSED_0128_PORT6_MASK (0xFFFFFFFF << RTL8373_UNUSED_0128_PORT6_UNUSED_0128_PORT6_OFFSET) + +#define RTL8373_UNUSED_012C_PORT6_ADDR (0xD21C) + #define RTL8373_UNUSED_012C_PORT6_UNUSED_012C_PORT6_OFFSET (0) + #define RTL8373_UNUSED_012C_PORT6_UNUSED_012C_PORT6_MASK (0xFFFFFFFF << RTL8373_UNUSED_012C_PORT6_UNUSED_012C_PORT6_OFFSET) + +#define RTL8373_UNUSED_0130_PORT6_ADDR (0xD220) + #define RTL8373_UNUSED_0130_PORT6_UNUSED_0130_PORT6_OFFSET (0) + #define RTL8373_UNUSED_0130_PORT6_UNUSED_0130_PORT6_MASK (0xFFFFFFFF << RTL8373_UNUSED_0130_PORT6_UNUSED_0130_PORT6_OFFSET) + +#define RTL8373_UNUSED_0134_PORT6_ADDR (0xD224) + #define RTL8373_UNUSED_0134_PORT6_UNUSED_0134_PORT6_OFFSET (0) + #define RTL8373_UNUSED_0134_PORT6_UNUSED_0134_PORT6_MASK (0xFFFFFFFF << RTL8373_UNUSED_0134_PORT6_UNUSED_0134_PORT6_OFFSET) + +#define RTL8373_UNUSED_0138_PORT6_ADDR (0xD228) + #define RTL8373_UNUSED_0138_PORT6_UNUSED_0138_PORT6_OFFSET (0) + #define RTL8373_UNUSED_0138_PORT6_UNUSED_0138_PORT6_MASK (0xFFFFFFFF << RTL8373_UNUSED_0138_PORT6_UNUSED_0138_PORT6_OFFSET) + +#define RTL8373_UNUSED_013C_PORT6_ADDR (0xD22C) + #define RTL8373_UNUSED_013C_PORT6_UNUSED_013C_PORT6_OFFSET (0) + #define RTL8373_UNUSED_013C_PORT6_UNUSED_013C_PORT6_MASK (0xFFFFFFFF << RTL8373_UNUSED_013C_PORT6_UNUSED_013C_PORT6_OFFSET) + +#define RTL8373_MACSEC_TXLINE_CFG1_PORT6_ADDR (0xD230) + #define RTL8373_MACSEC_TXLINE_CFG1_PORT6_TXLINE_WAIT_T_OFFSET (16) + #define RTL8373_MACSEC_TXLINE_CFG1_PORT6_TXLINE_WAIT_T_MASK (0xFF << RTL8373_MACSEC_TXLINE_CFG1_PORT6_TXLINE_WAIT_T_OFFSET) + #define RTL8373_MACSEC_TXLINE_CFG1_PORT6_TXLINE_MINIFG_OFFSET (8) + #define RTL8373_MACSEC_TXLINE_CFG1_PORT6_TXLINE_MINIFG_MASK (0xFF << RTL8373_MACSEC_TXLINE_CFG1_PORT6_TXLINE_MINIFG_OFFSET) + #define RTL8373_MACSEC_TXLINE_CFG1_PORT6_TXLINE_PMBNUM_OFFSET (0) + #define RTL8373_MACSEC_TXLINE_CFG1_PORT6_TXLINE_PMBNUM_MASK (0xF << RTL8373_MACSEC_TXLINE_CFG1_PORT6_TXLINE_PMBNUM_OFFSET) + +#define RTL8373_MACSEC_TXLINE_CFG3_PORT6_ADDR (0xD234) + #define RTL8373_MACSEC_TXLINE_CFG3_PORT6_TXLINE_FIFO_TSHD_OFFSET (16) + #define RTL8373_MACSEC_TXLINE_CFG3_PORT6_TXLINE_FIFO_TSHD_MASK (0xFF << RTL8373_MACSEC_TXLINE_CFG3_PORT6_TXLINE_FIFO_TSHD_OFFSET) + #define RTL8373_MACSEC_TXLINE_CFG3_PORT6_TXLINE_PAD_VLAN_EN_OFFSET (14) + #define RTL8373_MACSEC_TXLINE_CFG3_PORT6_TXLINE_PAD_VLAN_EN_MASK (0x1 << RTL8373_MACSEC_TXLINE_CFG3_PORT6_TXLINE_PAD_VLAN_EN_OFFSET) + #define RTL8373_MACSEC_TXLINE_CFG3_PORT6_TXLINE_PAD_MACSEC_EN_OFFSET (13) + #define RTL8373_MACSEC_TXLINE_CFG3_PORT6_TXLINE_PAD_MACSEC_EN_MASK (0x1 << RTL8373_MACSEC_TXLINE_CFG3_PORT6_TXLINE_PAD_MACSEC_EN_OFFSET) + #define RTL8373_MACSEC_TXLINE_CFG3_PORT6_TXLINE_PAD_EN_OFFSET (12) + #define RTL8373_MACSEC_TXLINE_CFG3_PORT6_TXLINE_PAD_EN_MASK (0x1 << RTL8373_MACSEC_TXLINE_CFG3_PORT6_TXLINE_PAD_EN_OFFSET) + #define RTL8373_MACSEC_TXLINE_CFG3_PORT6_TXLINE_PKTERR_INVRSCRC_EN_OFFSET (8) + #define RTL8373_MACSEC_TXLINE_CFG3_PORT6_TXLINE_PKTERR_INVRSCRC_EN_MASK (0x1 << RTL8373_MACSEC_TXLINE_CFG3_PORT6_TXLINE_PKTERR_INVRSCRC_EN_OFFSET) + #define RTL8373_MACSEC_TXLINE_CFG3_PORT6_TXLINE_GMIIER_INVRSCRC_EN_OFFSET (5) + #define RTL8373_MACSEC_TXLINE_CFG3_PORT6_TXLINE_GMIIER_INVRSCRC_EN_MASK (0x1 << RTL8373_MACSEC_TXLINE_CFG3_PORT6_TXLINE_GMIIER_INVRSCRC_EN_OFFSET) + #define RTL8373_MACSEC_TXLINE_CFG3_PORT6_TXLINE_CRCERR_INVRSCRC_EN_OFFSET (4) + #define RTL8373_MACSEC_TXLINE_CFG3_PORT6_TXLINE_CRCERR_INVRSCRC_EN_MASK (0x1 << RTL8373_MACSEC_TXLINE_CFG3_PORT6_TXLINE_CRCERR_INVRSCRC_EN_OFFSET) + #define RTL8373_MACSEC_TXLINE_CFG3_PORT6_TXLINE_CLASSDROP_EN_OFFSET (0) + #define RTL8373_MACSEC_TXLINE_CFG3_PORT6_TXLINE_CLASSDROP_EN_MASK (0x1 << RTL8373_MACSEC_TXLINE_CFG3_PORT6_TXLINE_CLASSDROP_EN_OFFSET) + +#define RTL8373_MACSEC_TXLINE_CFG5_PORT6_ADDR (0xD238) + #define RTL8373_MACSEC_TXLINE_CFG5_PORT6_TXLINE_AVG_IPG_OFFSET (16) + #define RTL8373_MACSEC_TXLINE_CFG5_PORT6_TXLINE_AVG_IPG_MASK (0xF << RTL8373_MACSEC_TXLINE_CFG5_PORT6_TXLINE_AVG_IPG_OFFSET) + #define RTL8373_MACSEC_TXLINE_CFG5_PORT6_TXLIEN_LPIEXIT_T_OFFSET (0) + #define RTL8373_MACSEC_TXLINE_CFG5_PORT6_TXLIEN_LPIEXIT_T_MASK (0x7FFF << RTL8373_MACSEC_TXLINE_CFG5_PORT6_TXLIEN_LPIEXIT_T_OFFSET) + +#define RTL8373_UNUSED_014C_PORT6_ADDR (0xD23C) + #define RTL8373_UNUSED_014C_PORT6_UNUSED_014C_PORT6_OFFSET (0) + #define RTL8373_UNUSED_014C_PORT6_UNUSED_014C_PORT6_MASK (0xFFFFFFFF << RTL8373_UNUSED_014C_PORT6_UNUSED_014C_PORT6_OFFSET) + +#define RTL8373_UNUSED_0150_PORT6_ADDR (0xD240) + #define RTL8373_UNUSED_0150_PORT6_UNUSED_0150_PORT6_OFFSET (0) + #define RTL8373_UNUSED_0150_PORT6_UNUSED_0150_PORT6_MASK (0xFFFFFFFF << RTL8373_UNUSED_0150_PORT6_UNUSED_0150_PORT6_OFFSET) + +#define RTL8373_UNUSED_0154_PORT6_ADDR (0xD244) + #define RTL8373_UNUSED_0154_PORT6_UNUSED_0154_PORT6_OFFSET (0) + #define RTL8373_UNUSED_0154_PORT6_UNUSED_0154_PORT6_MASK (0xFFFFFFFF << RTL8373_UNUSED_0154_PORT6_UNUSED_0154_PORT6_OFFSET) + +#define RTL8373_UNUSED_0158_PORT6_ADDR (0xD248) + #define RTL8373_UNUSED_0158_PORT6_UNUSED_0158_PORT6_OFFSET (0) + #define RTL8373_UNUSED_0158_PORT6_UNUSED_0158_PORT6_MASK (0xFFFFFFFF << RTL8373_UNUSED_0158_PORT6_UNUSED_0158_PORT6_OFFSET) + +#define RTL8373_UNUSED_015C_PORT6_ADDR (0xD24C) + #define RTL8373_UNUSED_015C_PORT6_UNUSED_015C_PORT6_OFFSET (0) + #define RTL8373_UNUSED_015C_PORT6_UNUSED_015C_PORT6_MASK (0xFFFFFFFF << RTL8373_UNUSED_015C_PORT6_UNUSED_015C_PORT6_OFFSET) + +#define RTL8373_UNUSED_0160_PORT6_ADDR (0xD250) + #define RTL8373_UNUSED_0160_PORT6_UNUSED_0160_PORT6_OFFSET (0) + #define RTL8373_UNUSED_0160_PORT6_UNUSED_0160_PORT6_MASK (0xFFFFFFFF << RTL8373_UNUSED_0160_PORT6_UNUSED_0160_PORT6_OFFSET) + +#define RTL8373_UNUSED_0164_PORT6_ADDR (0xD254) + #define RTL8373_UNUSED_0164_PORT6_UNUSED_0164_PORT6_OFFSET (0) + #define RTL8373_UNUSED_0164_PORT6_UNUSED_0164_PORT6_MASK (0xFFFFFFFF << RTL8373_UNUSED_0164_PORT6_UNUSED_0164_PORT6_OFFSET) + +#define RTL8373_UNUSED_0168_PORT6_ADDR (0xD258) + #define RTL8373_UNUSED_0168_PORT6_UNUSED_0168_PORT6_OFFSET (0) + #define RTL8373_UNUSED_0168_PORT6_UNUSED_0168_PORT6_MASK (0xFFFFFFFF << RTL8373_UNUSED_0168_PORT6_UNUSED_0168_PORT6_OFFSET) + +#define RTL8373_UNUSED_016C_PORT6_ADDR (0xD25C) + #define RTL8373_UNUSED_016C_PORT6_UNUSED_016C_PORT6_OFFSET (0) + #define RTL8373_UNUSED_016C_PORT6_UNUSED_016C_PORT6_MASK (0xFFFFFFFF << RTL8373_UNUSED_016C_PORT6_UNUSED_016C_PORT6_OFFSET) + +#define RTL8373_UNUSED_0170_PORT6_ADDR (0xD260) + #define RTL8373_UNUSED_0170_PORT6_UNUSED_0170_PORT6_OFFSET (0) + #define RTL8373_UNUSED_0170_PORT6_UNUSED_0170_PORT6_MASK (0xFFFFFFFF << RTL8373_UNUSED_0170_PORT6_UNUSED_0170_PORT6_OFFSET) + +#define RTL8373_UNUSED_0174_PORT6_ADDR (0xD264) + #define RTL8373_UNUSED_0174_PORT6_UNUSED_0174_PORT6_OFFSET (0) + #define RTL8373_UNUSED_0174_PORT6_UNUSED_0174_PORT6_MASK (0xFFFFFFFF << RTL8373_UNUSED_0174_PORT6_UNUSED_0174_PORT6_OFFSET) + +#define RTL8373_UNUSED_0178_PORT6_ADDR (0xD268) + #define RTL8373_UNUSED_0178_PORT6_UNUSED_0178_PORT6_OFFSET (0) + #define RTL8373_UNUSED_0178_PORT6_UNUSED_0178_PORT6_MASK (0xFFFFFFFF << RTL8373_UNUSED_0178_PORT6_UNUSED_0178_PORT6_OFFSET) + +#define RTL8373_UNUSED_017C_PORT6_ADDR (0xD26C) + #define RTL8373_UNUSED_017C_PORT6_UNUSED_017C_PORT6_OFFSET (0) + #define RTL8373_UNUSED_017C_PORT6_UNUSED_017C_PORT6_MASK (0xFFFFFFFF << RTL8373_UNUSED_017C_PORT6_UNUSED_017C_PORT6_OFFSET) + +#define RTL8373_MACSEC_RXLINE_CFG1_PORT6_ADDR (0xD270) + #define RTL8373_MACSEC_RXLINE_CFG1_PORT6_RXLINE_XGMINIFG_OFFSET (16) + #define RTL8373_MACSEC_RXLINE_CFG1_PORT6_RXLINE_XGMINIFG_MASK (0x1F << RTL8373_MACSEC_RXLINE_CFG1_PORT6_RXLINE_XGMINIFG_OFFSET) + #define RTL8373_MACSEC_RXLINE_CFG1_PORT6_RXLINE_MINIPG_OFFSET (8) + #define RTL8373_MACSEC_RXLINE_CFG1_PORT6_RXLINE_MINIPG_MASK (0xF << RTL8373_MACSEC_RXLINE_CFG1_PORT6_RXLINE_MINIPG_OFFSET) + #define RTL8373_MACSEC_RXLINE_CFG1_PORT6_RXLINE_PMBNUM_OFFSET (0) + #define RTL8373_MACSEC_RXLINE_CFG1_PORT6_RXLINE_PMBNUM_MASK (0x7 << RTL8373_MACSEC_RXLINE_CFG1_PORT6_RXLINE_PMBNUM_OFFSET) + +#define RTL8373_UNUSED_0184_PORT6_ADDR (0xD274) + #define RTL8373_UNUSED_0184_PORT6_UNUSED_0184_PORT6_OFFSET (0) + #define RTL8373_UNUSED_0184_PORT6_UNUSED_0184_PORT6_MASK (0xFFFFFFFF << RTL8373_UNUSED_0184_PORT6_UNUSED_0184_PORT6_OFFSET) + +#define RTL8373_UNUSED_0188_PORT6_ADDR (0xD278) + #define RTL8373_UNUSED_0188_PORT6_UNUSED_0188_PORT6_OFFSET (0) + #define RTL8373_UNUSED_0188_PORT6_UNUSED_0188_PORT6_MASK (0xFFFFFFFF << RTL8373_UNUSED_0188_PORT6_UNUSED_0188_PORT6_OFFSET) + +#define RTL8373_UNUSED_018C_PORT6_ADDR (0xD27C) + #define RTL8373_UNUSED_018C_PORT6_UNUSED_018C_PORT6_OFFSET (0) + #define RTL8373_UNUSED_018C_PORT6_UNUSED_018C_PORT6_MASK (0xFFFFFFFF << RTL8373_UNUSED_018C_PORT6_UNUSED_018C_PORT6_OFFSET) + +#define RTL8373_UNUSED_0190_PORT6_ADDR (0xD280) + #define RTL8373_UNUSED_0190_PORT6_UNUSED_0190_PORT6_OFFSET (0) + #define RTL8373_UNUSED_0190_PORT6_UNUSED_0190_PORT6_MASK (0xFFFFFFFF << RTL8373_UNUSED_0190_PORT6_UNUSED_0190_PORT6_OFFSET) + +#define RTL8373_UNUSED_0194_PORT6_ADDR (0xD284) + #define RTL8373_UNUSED_0194_PORT6_UNUSED_0194_PORT6_OFFSET (0) + #define RTL8373_UNUSED_0194_PORT6_UNUSED_0194_PORT6_MASK (0xFFFFFFFF << RTL8373_UNUSED_0194_PORT6_UNUSED_0194_PORT6_OFFSET) + +#define RTL8373_UNUSED_0198_PORT6_ADDR (0xD288) + #define RTL8373_UNUSED_0198_PORT6_UNUSED_0198_PORT6_OFFSET (0) + #define RTL8373_UNUSED_0198_PORT6_UNUSED_0198_PORT6_MASK (0xFFFFFFFF << RTL8373_UNUSED_0198_PORT6_UNUSED_0198_PORT6_OFFSET) + +#define RTL8373_UNUSED_019C_PORT6_ADDR (0xD28C) + #define RTL8373_UNUSED_019C_PORT6_UNUSED_019C_PORT6_OFFSET (0) + #define RTL8373_UNUSED_019C_PORT6_UNUSED_019C_PORT6_MASK (0xFFFFFFFF << RTL8373_UNUSED_019C_PORT6_UNUSED_019C_PORT6_OFFSET) + +#define RTL8373_UNUSED_01A0_PORT6_ADDR (0xD290) + #define RTL8373_UNUSED_01A0_PORT6_UNUSED_01A0_PORT6_OFFSET (0) + #define RTL8373_UNUSED_01A0_PORT6_UNUSED_01A0_PORT6_MASK (0xFFFFFFFF << RTL8373_UNUSED_01A0_PORT6_UNUSED_01A0_PORT6_OFFSET) + +#define RTL8373_UNUSED_01A4_PORT6_ADDR (0xD294) + #define RTL8373_UNUSED_01A4_PORT6_UNUSED_01A4_PORT6_OFFSET (0) + #define RTL8373_UNUSED_01A4_PORT6_UNUSED_01A4_PORT6_MASK (0xFFFFFFFF << RTL8373_UNUSED_01A4_PORT6_UNUSED_01A4_PORT6_OFFSET) + +#define RTL8373_UNUSED_01A8_PORT6_ADDR (0xD298) + #define RTL8373_UNUSED_01A8_PORT6_UNUSED_01A8_PORT6_OFFSET (0) + #define RTL8373_UNUSED_01A8_PORT6_UNUSED_01A8_PORT6_MASK (0xFFFFFFFF << RTL8373_UNUSED_01A8_PORT6_UNUSED_01A8_PORT6_OFFSET) + +#define RTL8373_UNUSED_01AC_PORT6_ADDR (0xD29C) + #define RTL8373_UNUSED_01AC_PORT6_UNUSED_01AC_PORT6_OFFSET (0) + #define RTL8373_UNUSED_01AC_PORT6_UNUSED_01AC_PORT6_MASK (0xFFFFFFFF << RTL8373_UNUSED_01AC_PORT6_UNUSED_01AC_PORT6_OFFSET) + +#define RTL8373_UNUSED_01B0_PORT6_ADDR (0xD2A0) + #define RTL8373_UNUSED_01B0_PORT6_UNUSED_01B0_PORT6_OFFSET (0) + #define RTL8373_UNUSED_01B0_PORT6_UNUSED_01B0_PORT6_MASK (0xFFFFFFFF << RTL8373_UNUSED_01B0_PORT6_UNUSED_01B0_PORT6_OFFSET) + +#define RTL8373_UNUSED_01B4_PORT6_ADDR (0xD2A4) + #define RTL8373_UNUSED_01B4_PORT6_UNUSED_01B4_PORT6_OFFSET (0) + #define RTL8373_UNUSED_01B4_PORT6_UNUSED_01B4_PORT6_MASK (0xFFFFFFFF << RTL8373_UNUSED_01B4_PORT6_UNUSED_01B4_PORT6_OFFSET) + +#define RTL8373_UNUSED_01B8_PORT6_ADDR (0xD2A8) + #define RTL8373_UNUSED_01B8_PORT6_UNUSED_01B8_PORT6_OFFSET (0) + #define RTL8373_UNUSED_01B8_PORT6_UNUSED_01B8_PORT6_MASK (0xFFFFFFFF << RTL8373_UNUSED_01B8_PORT6_UNUSED_01B8_PORT6_OFFSET) + +#define RTL8373_UNUSED_01BC_PORT6_ADDR (0xD2AC) + #define RTL8373_UNUSED_01BC_PORT6_UNUSED_01BC_PORT6_OFFSET (0) + #define RTL8373_UNUSED_01BC_PORT6_UNUSED_01BC_PORT6_MASK (0xFFFFFFFF << RTL8373_UNUSED_01BC_PORT6_UNUSED_01BC_PORT6_OFFSET) + +#define RTL8373_MACSEC_RXSYS_CFG1_PORT6_ADDR (0xD2B0) + #define RTL8373_MACSEC_RXSYS_CFG1_PORT6_RXSYS_WAIT_T_OFFSET (16) + #define RTL8373_MACSEC_RXSYS_CFG1_PORT6_RXSYS_WAIT_T_MASK (0xFF << RTL8373_MACSEC_RXSYS_CFG1_PORT6_RXSYS_WAIT_T_OFFSET) + #define RTL8373_MACSEC_RXSYS_CFG1_PORT6_RXSYS_MINIPG_OFFSET (8) + #define RTL8373_MACSEC_RXSYS_CFG1_PORT6_RXSYS_MINIPG_MASK (0xFF << RTL8373_MACSEC_RXSYS_CFG1_PORT6_RXSYS_MINIPG_OFFSET) + #define RTL8373_MACSEC_RXSYS_CFG1_PORT6_RXSYS_PMBNUM_OFFSET (0) + #define RTL8373_MACSEC_RXSYS_CFG1_PORT6_RXSYS_PMBNUM_MASK (0xF << RTL8373_MACSEC_RXSYS_CFG1_PORT6_RXSYS_PMBNUM_OFFSET) + +#define RTL8373_MACSEC_RXSYS_CFG3_PORT6_ADDR (0xD2B4) + #define RTL8373_MACSEC_RXSYS_CFG3_PORT6_RXSYS_OUTERVLAN1_OFFSET (16) + #define RTL8373_MACSEC_RXSYS_CFG3_PORT6_RXSYS_OUTERVLAN1_MASK (0xFFFF << RTL8373_MACSEC_RXSYS_CFG3_PORT6_RXSYS_OUTERVLAN1_OFFSET) + #define RTL8373_MACSEC_RXSYS_CFG3_PORT6_RXSYS_PAD_VLAN_EN_OFFSET (14) + #define RTL8373_MACSEC_RXSYS_CFG3_PORT6_RXSYS_PAD_VLAN_EN_MASK (0x1 << RTL8373_MACSEC_RXSYS_CFG3_PORT6_RXSYS_PAD_VLAN_EN_OFFSET) + #define RTL8373_MACSEC_RXSYS_CFG3_PORT6_RXSYS_PAD_LINESRT_EN_OFFSET (13) + #define RTL8373_MACSEC_RXSYS_CFG3_PORT6_RXSYS_PAD_LINESRT_EN_MASK (0x1 << RTL8373_MACSEC_RXSYS_CFG3_PORT6_RXSYS_PAD_LINESRT_EN_OFFSET) + #define RTL8373_MACSEC_RXSYS_CFG3_PORT6_RXSYS_PAD_DECRYPTSRT_EN_OFFSET (12) + #define RTL8373_MACSEC_RXSYS_CFG3_PORT6_RXSYS_PAD_DECRYPTSRT_EN_MASK (0x1 << RTL8373_MACSEC_RXSYS_CFG3_PORT6_RXSYS_PAD_DECRYPTSRT_EN_OFFSET) + #define RTL8373_MACSEC_RXSYS_CFG3_PORT6_RXSYS_PKTERR_INVRSCRC_EN_OFFSET (8) + #define RTL8373_MACSEC_RXSYS_CFG3_PORT6_RXSYS_PKTERR_INVRSCRC_EN_MASK (0x1 << RTL8373_MACSEC_RXSYS_CFG3_PORT6_RXSYS_PKTERR_INVRSCRC_EN_OFFSET) + #define RTL8373_MACSEC_RXSYS_CFG3_PORT6_RXSYS_GMIIER_INVRSCRC_EN_OFFSET (5) + #define RTL8373_MACSEC_RXSYS_CFG3_PORT6_RXSYS_GMIIER_INVRSCRC_EN_MASK (0x1 << RTL8373_MACSEC_RXSYS_CFG3_PORT6_RXSYS_GMIIER_INVRSCRC_EN_OFFSET) + #define RTL8373_MACSEC_RXSYS_CFG3_PORT6_RXSYS_CRCERR_INVRSCRC_EN_OFFSET (4) + #define RTL8373_MACSEC_RXSYS_CFG3_PORT6_RXSYS_CRCERR_INVRSCRC_EN_MASK (0x1 << RTL8373_MACSEC_RXSYS_CFG3_PORT6_RXSYS_CRCERR_INVRSCRC_EN_OFFSET) + #define RTL8373_MACSEC_RXSYS_CFG3_PORT6_RXSYS_CLASSDROP_EN_OFFSET (0) + #define RTL8373_MACSEC_RXSYS_CFG3_PORT6_RXSYS_CLASSDROP_EN_MASK (0x1 << RTL8373_MACSEC_RXSYS_CFG3_PORT6_RXSYS_CLASSDROP_EN_OFFSET) + +#define RTL8373_MACSEC_RXSYS_OUTERVLAN2_PORT6_ADDR (0xD2B8) + #define RTL8373_MACSEC_RXSYS_OUTERVLAN2_PORT6_RXSYS_OUTERVLAN3_OFFSET (16) + #define RTL8373_MACSEC_RXSYS_OUTERVLAN2_PORT6_RXSYS_OUTERVLAN3_MASK (0xFFFF << RTL8373_MACSEC_RXSYS_OUTERVLAN2_PORT6_RXSYS_OUTERVLAN3_OFFSET) + #define RTL8373_MACSEC_RXSYS_OUTERVLAN2_PORT6_RXSYS_OUTERVLAN2_OFFSET (0) + #define RTL8373_MACSEC_RXSYS_OUTERVLAN2_PORT6_RXSYS_OUTERVLAN2_MASK (0xFFFF << RTL8373_MACSEC_RXSYS_OUTERVLAN2_PORT6_RXSYS_OUTERVLAN2_OFFSET) + +#define RTL8373_MACSEC_RXSYS_OUTERVLAN4_PORT6_ADDR (0xD2BC) + #define RTL8373_MACSEC_RXSYS_OUTERVLAN4_PORT6_RXSYS_INNERVLAN1_OFFSET (16) + #define RTL8373_MACSEC_RXSYS_OUTERVLAN4_PORT6_RXSYS_INNERVLAN1_MASK (0xFFFF << RTL8373_MACSEC_RXSYS_OUTERVLAN4_PORT6_RXSYS_INNERVLAN1_OFFSET) + #define RTL8373_MACSEC_RXSYS_OUTERVLAN4_PORT6_RXSYS_OUTERVLAN4_OFFSET (0) + #define RTL8373_MACSEC_RXSYS_OUTERVLAN4_PORT6_RXSYS_OUTERVLAN4_MASK (0xFFFF << RTL8373_MACSEC_RXSYS_OUTERVLAN4_PORT6_RXSYS_OUTERVLAN4_OFFSET) + +#define RTL8373_MACSEC_RXSYS_INNERVLAN2_PORT6_ADDR (0xD2C0) + #define RTL8373_MACSEC_RXSYS_INNERVLAN2_PORT6_RXSYS_INNERVLAN3_OFFSET (16) + #define RTL8373_MACSEC_RXSYS_INNERVLAN2_PORT6_RXSYS_INNERVLAN3_MASK (0xFFFF << RTL8373_MACSEC_RXSYS_INNERVLAN2_PORT6_RXSYS_INNERVLAN3_OFFSET) + #define RTL8373_MACSEC_RXSYS_INNERVLAN2_PORT6_RXSYS_INNERVLAN2_OFFSET (0) + #define RTL8373_MACSEC_RXSYS_INNERVLAN2_PORT6_RXSYS_INNERVLAN2_MASK (0xFFFF << RTL8373_MACSEC_RXSYS_INNERVLAN2_PORT6_RXSYS_INNERVLAN2_OFFSET) + +#define RTL8373_MACSEC_RXSYS_INNERVLAN4_PORT6_ADDR (0xD2C4) + #define RTL8373_MACSEC_RXSYS_INNERVLAN4_PORT6_RXSYS_INNERVLAN5_OFFSET (16) + #define RTL8373_MACSEC_RXSYS_INNERVLAN4_PORT6_RXSYS_INNERVLAN5_MASK (0xFFFF << RTL8373_MACSEC_RXSYS_INNERVLAN4_PORT6_RXSYS_INNERVLAN5_OFFSET) + #define RTL8373_MACSEC_RXSYS_INNERVLAN4_PORT6_RXSYS_INNERVLAN4_OFFSET (0) + #define RTL8373_MACSEC_RXSYS_INNERVLAN4_PORT6_RXSYS_INNERVLAN4_MASK (0xFFFF << RTL8373_MACSEC_RXSYS_INNERVLAN4_PORT6_RXSYS_INNERVLAN4_OFFSET) + +#define RTL8373_MACSEC_RXSYS_INNERVLAN6_PORT6_ADDR (0xD2C8) + #define RTL8373_MACSEC_RXSYS_INNERVLAN6_PORT6_RXSYS_INNERVLAN7_OFFSET (16) + #define RTL8373_MACSEC_RXSYS_INNERVLAN6_PORT6_RXSYS_INNERVLAN7_MASK (0xFFFF << RTL8373_MACSEC_RXSYS_INNERVLAN6_PORT6_RXSYS_INNERVLAN7_OFFSET) + #define RTL8373_MACSEC_RXSYS_INNERVLAN6_PORT6_RXSYS_INNERVLAN6_OFFSET (0) + #define RTL8373_MACSEC_RXSYS_INNERVLAN6_PORT6_RXSYS_INNERVLAN6_MASK (0xFFFF << RTL8373_MACSEC_RXSYS_INNERVLAN6_PORT6_RXSYS_INNERVLAN6_OFFSET) + +#define RTL8373_MACSEC_RXSYS_CFG4_PORT6_ADDR (0xD2CC) + #define RTL8373_MACSEC_RXSYS_CFG4_PORT6_RXSYS_LPIEXIT_T_OFFSET (16) + #define RTL8373_MACSEC_RXSYS_CFG4_PORT6_RXSYS_LPIEXIT_T_MASK (0x7FFF << RTL8373_MACSEC_RXSYS_CFG4_PORT6_RXSYS_LPIEXIT_T_OFFSET) + #define RTL8373_MACSEC_RXSYS_CFG4_PORT6_RXSYS_FIFO_FTUNE_OFFSET (8) + #define RTL8373_MACSEC_RXSYS_CFG4_PORT6_RXSYS_FIFO_FTUNE_MASK (0xFF << RTL8373_MACSEC_RXSYS_CFG4_PORT6_RXSYS_FIFO_FTUNE_OFFSET) + #define RTL8373_MACSEC_RXSYS_CFG4_PORT6_RXSYS_FIFO_TSHD_OFFSET (0) + #define RTL8373_MACSEC_RXSYS_CFG4_PORT6_RXSYS_FIFO_TSHD_MASK (0xFF << RTL8373_MACSEC_RXSYS_CFG4_PORT6_RXSYS_FIFO_TSHD_OFFSET) + +#define RTL8373_MACSEC_RXSYS_CFG6_PORT6_ADDR (0xD2D0) + #define RTL8373_MACSEC_RXSYS_CFG6_PORT6_RXSYS_AVG_IPG_OFFSET (0) + #define RTL8373_MACSEC_RXSYS_CFG6_PORT6_RXSYS_AVG_IPG_MASK (0xF << RTL8373_MACSEC_RXSYS_CFG6_PORT6_RXSYS_AVG_IPG_OFFSET) + +#define RTL8373_MACSEC_REG_GLB_SET1_PORT7_ADDR (0xD8F0) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT7_RX_GATING_OFFSET (31) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT7_RX_GATING_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT7_RX_GATING_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT7_TX_GATING_OFFSET (30) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT7_TX_GATING_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT7_TX_GATING_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT7_DBG_EN_OFFSET (29) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT7_DBG_EN_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT7_DBG_EN_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT7_DBG_SEL_OFFSET (24) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT7_DBG_SEL_MASK (0x1F << RTL8373_MACSEC_REG_GLB_SET1_PORT7_DBG_SEL_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT7_DBG_SPD_SEL_OFFSET (23) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT7_DBG_SPD_SEL_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT7_DBG_SPD_SEL_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT7_RX_G_IOSAMEPMB_OFFSET (22) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT7_RX_G_IOSAMEPMB_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT7_RX_G_IOSAMEPMB_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT7_TX_G_IOSAMEPMB_OFFSET (21) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT7_TX_G_IOSAMEPMB_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT7_TX_G_IOSAMEPMB_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT7_MIBCNT_MODE_OFFSET (20) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT7_MIBCNT_MODE_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT7_MIBCNT_MODE_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT7_RX_XGDIC_EN_OFFSET (18) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT7_RX_XGDIC_EN_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT7_RX_XGDIC_EN_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT7_TX_XGDIC_EN_OFFSET (17) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT7_TX_XGDIC_EN_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT7_TX_XGDIC_EN_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT7_MIBCNT_SWRST_N_OFFSET (16) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT7_MIBCNT_SWRST_N_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT7_MIBCNT_SWRST_N_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT7_PTPBYPASS_EN_OFFSET (14) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT7_PTPBYPASS_EN_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT7_PTPBYPASS_EN_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT7_SYSLPBK_EN_OFFSET (13) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT7_SYSLPBK_EN_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT7_SYSLPBK_EN_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT7_PHY2MAC_EN_OFFSET (12) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT7_PHY2MAC_EN_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT7_PHY2MAC_EN_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT7_RX_IPRST_N_OFFSET (11) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT7_RX_IPRST_N_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT7_RX_IPRST_N_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT7_RX_IPBYPASS_EN_OFFSET (10) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT7_RX_IPBYPASS_EN_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT7_RX_IPBYPASS_EN_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT7_RX_MACSECBYPASS_EN_OFFSET (9) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT7_RX_MACSECBYPASS_EN_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT7_RX_MACSECBYPASS_EN_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT7_RX_SWRST_EN_OFFSET (8) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT7_RX_SWRST_EN_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT7_RX_SWRST_EN_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT7_LINELPBK_EN_OFFSET (5) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT7_LINELPBK_EN_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT7_LINELPBK_EN_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT7_MAC2PHY_EN_OFFSET (4) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT7_MAC2PHY_EN_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT7_MAC2PHY_EN_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT7_TX_IPRST_N_OFFSET (3) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT7_TX_IPRST_N_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT7_TX_IPRST_N_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT7_TX_IPBYPASS_EN_OFFSET (2) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT7_TX_IPBYPASS_EN_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT7_TX_IPBYPASS_EN_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT7_TX_MACSECBYPASS_EN_OFFSET (1) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT7_TX_MACSECBYPASS_EN_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT7_TX_MACSECBYPASS_EN_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT7_TX_SWRST_EN_OFFSET (0) + #define RTL8373_MACSEC_REG_GLB_SET1_PORT7_TX_SWRST_EN_MASK (0x1 << RTL8373_MACSEC_REG_GLB_SET1_PORT7_TX_SWRST_EN_OFFSET) + +#define RTL8373_MACSEC_REG_GLB_IMR_PORT7_ADDR (0xD8F4) + #define RTL8373_MACSEC_REG_GLB_IMR_PORT7_RX_IPILOCK_XG_IMR_OFFSET (11) + #define RTL8373_MACSEC_REG_GLB_IMR_PORT7_RX_IPILOCK_XG_IMR_MASK (0x1 << RTL8373_MACSEC_REG_GLB_IMR_PORT7_RX_IPILOCK_XG_IMR_OFFSET) + #define RTL8373_MACSEC_REG_GLB_IMR_PORT7_RX_IPILOCK_IMR_OFFSET (10) + #define RTL8373_MACSEC_REG_GLB_IMR_PORT7_RX_IPILOCK_IMR_MASK (0x1 << RTL8373_MACSEC_REG_GLB_IMR_PORT7_RX_IPILOCK_IMR_OFFSET) + #define RTL8373_MACSEC_REG_GLB_IMR_PORT7_RX_IPISECFAIL_IMR_OFFSET (9) + #define RTL8373_MACSEC_REG_GLB_IMR_PORT7_RX_IPISECFAIL_IMR_MASK (0x1 << RTL8373_MACSEC_REG_GLB_IMR_PORT7_RX_IPISECFAIL_IMR_OFFSET) + #define RTL8373_MACSEC_REG_GLB_IMR_PORT7_RX_IPI_GLB_IMR_OFFSET (8) + #define RTL8373_MACSEC_REG_GLB_IMR_PORT7_RX_IPI_GLB_IMR_MASK (0x1 << RTL8373_MACSEC_REG_GLB_IMR_PORT7_RX_IPI_GLB_IMR_OFFSET) + #define RTL8373_MACSEC_REG_GLB_IMR_PORT7_TX_IPELOCK_XG_IMR_OFFSET (3) + #define RTL8373_MACSEC_REG_GLB_IMR_PORT7_TX_IPELOCK_XG_IMR_MASK (0x1 << RTL8373_MACSEC_REG_GLB_IMR_PORT7_TX_IPELOCK_XG_IMR_OFFSET) + #define RTL8373_MACSEC_REG_GLB_IMR_PORT7_TX_IPELOCK_IMR_OFFSET (2) + #define RTL8373_MACSEC_REG_GLB_IMR_PORT7_TX_IPELOCK_IMR_MASK (0x1 << RTL8373_MACSEC_REG_GLB_IMR_PORT7_TX_IPELOCK_IMR_OFFSET) + #define RTL8373_MACSEC_REG_GLB_IMR_PORT7_TX_IPESECFAIL_IMR_OFFSET (1) + #define RTL8373_MACSEC_REG_GLB_IMR_PORT7_TX_IPESECFAIL_IMR_MASK (0x1 << RTL8373_MACSEC_REG_GLB_IMR_PORT7_TX_IPESECFAIL_IMR_OFFSET) + #define RTL8373_MACSEC_REG_GLB_IMR_PORT7_TX_IPE_GLB_IMR_OFFSET (0) + #define RTL8373_MACSEC_REG_GLB_IMR_PORT7_TX_IPE_GLB_IMR_MASK (0x1 << RTL8373_MACSEC_REG_GLB_IMR_PORT7_TX_IPE_GLB_IMR_OFFSET) + +#define RTL8373_MACSEC_REG_GLB_ISR_PORT7_ADDR (0xD8F8) + #define RTL8373_MACSEC_REG_GLB_ISR_PORT7_RX_IPILOCK_XG_ISR_OFFSET (11) + #define RTL8373_MACSEC_REG_GLB_ISR_PORT7_RX_IPILOCK_XG_ISR_MASK (0x1 << RTL8373_MACSEC_REG_GLB_ISR_PORT7_RX_IPILOCK_XG_ISR_OFFSET) + #define RTL8373_MACSEC_REG_GLB_ISR_PORT7_RX_IPILOCK_ISR_OFFSET (10) + #define RTL8373_MACSEC_REG_GLB_ISR_PORT7_RX_IPILOCK_ISR_MASK (0x1 << RTL8373_MACSEC_REG_GLB_ISR_PORT7_RX_IPILOCK_ISR_OFFSET) + #define RTL8373_MACSEC_REG_GLB_ISR_PORT7_RX_IPISECFAIL_ISR_OFFSET (9) + #define RTL8373_MACSEC_REG_GLB_ISR_PORT7_RX_IPISECFAIL_ISR_MASK (0x1 << RTL8373_MACSEC_REG_GLB_ISR_PORT7_RX_IPISECFAIL_ISR_OFFSET) + #define RTL8373_MACSEC_REG_GLB_ISR_PORT7_RX_IPI_GLB_ISR_OFFSET (8) + #define RTL8373_MACSEC_REG_GLB_ISR_PORT7_RX_IPI_GLB_ISR_MASK (0x1 << RTL8373_MACSEC_REG_GLB_ISR_PORT7_RX_IPI_GLB_ISR_OFFSET) + #define RTL8373_MACSEC_REG_GLB_ISR_PORT7_TX_IPELOCK_XG_ISR_OFFSET (3) + #define RTL8373_MACSEC_REG_GLB_ISR_PORT7_TX_IPELOCK_XG_ISR_MASK (0x1 << RTL8373_MACSEC_REG_GLB_ISR_PORT7_TX_IPELOCK_XG_ISR_OFFSET) + #define RTL8373_MACSEC_REG_GLB_ISR_PORT7_TX_IPELOCK_ISR_OFFSET (2) + #define RTL8373_MACSEC_REG_GLB_ISR_PORT7_TX_IPELOCK_ISR_MASK (0x1 << RTL8373_MACSEC_REG_GLB_ISR_PORT7_TX_IPELOCK_ISR_OFFSET) + #define RTL8373_MACSEC_REG_GLB_ISR_PORT7_TX_IPESECFAIL_ISR_OFFSET (1) + #define RTL8373_MACSEC_REG_GLB_ISR_PORT7_TX_IPESECFAIL_ISR_MASK (0x1 << RTL8373_MACSEC_REG_GLB_ISR_PORT7_TX_IPESECFAIL_ISR_OFFSET) + #define RTL8373_MACSEC_REG_GLB_ISR_PORT7_TX_IPE_GLB_ISR_OFFSET (0) + #define RTL8373_MACSEC_REG_GLB_ISR_PORT7_TX_IPE_GLB_ISR_MASK (0x1 << RTL8373_MACSEC_REG_GLB_ISR_PORT7_TX_IPE_GLB_ISR_OFFSET) + +#define RTL8373_UNUSED_000C_PORT7_ADDR (0xD8FC) + #define RTL8373_UNUSED_000C_PORT7_UNUSED_000C_PORT7_OFFSET (0) + #define RTL8373_UNUSED_000C_PORT7_UNUSED_000C_PORT7_MASK (0xFFFFFFFF << RTL8373_UNUSED_000C_PORT7_UNUSED_000C_PORT7_OFFSET) + +#define RTL8373_MACSEC_PM_CTRL_PORT7_ADDR (0xD900) + #define RTL8373_MACSEC_PM_CTRL_PORT7_MACSEC_RX_ICG_EN_OFFSET (1) + #define RTL8373_MACSEC_PM_CTRL_PORT7_MACSEC_RX_ICG_EN_MASK (0x1 << RTL8373_MACSEC_PM_CTRL_PORT7_MACSEC_RX_ICG_EN_OFFSET) + #define RTL8373_MACSEC_PM_CTRL_PORT7_MACSEC_TX_ICG_EN_OFFSET (0) + #define RTL8373_MACSEC_PM_CTRL_PORT7_MACSEC_TX_ICG_EN_MASK (0x1 << RTL8373_MACSEC_PM_CTRL_PORT7_MACSEC_TX_ICG_EN_OFFSET) + +#define RTL8373_MACSEC_REG_GLB_MASK_PORT7_ADDR (0xD904) + #define RTL8373_MACSEC_REG_GLB_MASK_PORT7_RX_MTU_OFFSET (24) + #define RTL8373_MACSEC_REG_GLB_MASK_PORT7_RX_MTU_MASK (0x3F << RTL8373_MACSEC_REG_GLB_MASK_PORT7_RX_MTU_OFFSET) + #define RTL8373_MACSEC_REG_GLB_MASK_PORT7_TX_MTU_OFFSET (16) + #define RTL8373_MACSEC_REG_GLB_MASK_PORT7_TX_MTU_MASK (0x3F << RTL8373_MACSEC_REG_GLB_MASK_PORT7_TX_MTU_OFFSET) + #define RTL8373_MACSEC_REG_GLB_MASK_PORT7_RX_XGMASK_OFFSET (12) + #define RTL8373_MACSEC_REG_GLB_MASK_PORT7_RX_XGMASK_MASK (0x1 << RTL8373_MACSEC_REG_GLB_MASK_PORT7_RX_XGMASK_OFFSET) + #define RTL8373_MACSEC_REG_GLB_MASK_PORT7_RXDV_GMASK_OFFSET (8) + #define RTL8373_MACSEC_REG_GLB_MASK_PORT7_RXDV_GMASK_MASK (0x1 << RTL8373_MACSEC_REG_GLB_MASK_PORT7_RXDV_GMASK_OFFSET) + #define RTL8373_MACSEC_REG_GLB_MASK_PORT7_TX_XGMASK_OFFSET (4) + #define RTL8373_MACSEC_REG_GLB_MASK_PORT7_TX_XGMASK_MASK (0x1 << RTL8373_MACSEC_REG_GLB_MASK_PORT7_TX_XGMASK_OFFSET) + #define RTL8373_MACSEC_REG_GLB_MASK_PORT7_TXEN_GMASK_OFFSET (0) + #define RTL8373_MACSEC_REG_GLB_MASK_PORT7_TXEN_GMASK_MASK (0x1 << RTL8373_MACSEC_REG_GLB_MASK_PORT7_TXEN_GMASK_OFFSET) + +#define RTL8373_MACSEC_REG_GLB_SET4_PORT7_ADDR (0xD908) + #define RTL8373_MACSEC_REG_GLB_SET4_PORT7_TXMSKDELAY_VAL_OFFSET (16) + #define RTL8373_MACSEC_REG_GLB_SET4_PORT7_TXMSKDELAY_VAL_MASK (0x7FFF << RTL8373_MACSEC_REG_GLB_SET4_PORT7_TXMSKDELAY_VAL_OFFSET) + #define RTL8373_MACSEC_REG_GLB_SET4_PORT7_RXMSKDELAY_VAL_OFFSET (0) + #define RTL8373_MACSEC_REG_GLB_SET4_PORT7_RXMSKDELAY_VAL_MASK (0x7FFF << RTL8373_MACSEC_REG_GLB_SET4_PORT7_RXMSKDELAY_VAL_OFFSET) + +#define RTL8373_MACSEC_REG_IP_PROBE_PORT7_ADDR (0xD90C) + #define RTL8373_MACSEC_REG_IP_PROBE_PORT7_PROBE_SEL_AE_OFFSET (8) + #define RTL8373_MACSEC_REG_IP_PROBE_PORT7_PROBE_SEL_AE_MASK (0xFF << RTL8373_MACSEC_REG_IP_PROBE_PORT7_PROBE_SEL_AE_OFFSET) + #define RTL8373_MACSEC_REG_IP_PROBE_PORT7_PROBE_SEL_AI_OFFSET (0) + #define RTL8373_MACSEC_REG_IP_PROBE_PORT7_PROBE_SEL_AI_MASK (0xFF << RTL8373_MACSEC_REG_IP_PROBE_PORT7_PROBE_SEL_AI_OFFSET) + +#define RTL8373_UNUSED_0020_PORT7_ADDR (0xD910) + #define RTL8373_UNUSED_0020_PORT7_UNUSED_0020_PORT7_OFFSET (0) + #define RTL8373_UNUSED_0020_PORT7_UNUSED_0020_PORT7_MASK (0xFFFFFFFF << RTL8373_UNUSED_0020_PORT7_UNUSED_0020_PORT7_OFFSET) + +#define RTL8373_UNUSED_0024_PORT7_ADDR (0xD914) + #define RTL8373_UNUSED_0024_PORT7_UNUSED_0024_PORT7_OFFSET (0) + #define RTL8373_UNUSED_0024_PORT7_UNUSED_0024_PORT7_MASK (0xFFFFFFFF << RTL8373_UNUSED_0024_PORT7_UNUSED_0024_PORT7_OFFSET) + +#define RTL8373_MACSEC_MBIST_SA_CTRL_PORT7_ADDR (0xD918) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT7_BIST_MODE_MACSEC_SA_AE_OFFSET (29) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT7_BIST_MODE_MACSEC_SA_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_CTRL_PORT7_BIST_MODE_MACSEC_SA_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT7_DRF_BIST_MODE_MACSEC_SA_AE_OFFSET (28) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT7_DRF_BIST_MODE_MACSEC_SA_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_CTRL_PORT7_DRF_BIST_MODE_MACSEC_SA_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT7_BIST_RSTN_MACSEC_SA_AE_OFFSET (27) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT7_BIST_RSTN_MACSEC_SA_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_CTRL_PORT7_BIST_RSTN_MACSEC_SA_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT7_BIST_LOOP_MODE_MACSEC_SA_AE_OFFSET (26) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT7_BIST_LOOP_MODE_MACSEC_SA_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_CTRL_PORT7_BIST_LOOP_MODE_MACSEC_SA_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT7_DYN_READ_EN_MACSEC_SA_AE_OFFSET (25) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT7_DYN_READ_EN_MACSEC_SA_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_CTRL_PORT7_DYN_READ_EN_MACSEC_SA_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT7_DRF_TESS_RESUME_MACSEC_SA_AE_OFFSET (24) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT7_DRF_TESS_RESUME_MACSEC_SA_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_CTRL_PORT7_DRF_TESS_RESUME_MACSEC_SA_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT7_BIST_MODE_MACSEC_SA_AI_OFFSET (23) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT7_BIST_MODE_MACSEC_SA_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_CTRL_PORT7_BIST_MODE_MACSEC_SA_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT7_DRF_BIST_MODE_MACSEC_SA_AI_OFFSET (22) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT7_DRF_BIST_MODE_MACSEC_SA_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_CTRL_PORT7_DRF_BIST_MODE_MACSEC_SA_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT7_BIST_RSTN_MACSEC_SA_AI_OFFSET (21) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT7_BIST_RSTN_MACSEC_SA_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_CTRL_PORT7_BIST_RSTN_MACSEC_SA_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT7_BIST_LOOP_MODE_MACSEC_SA_AI_OFFSET (20) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT7_BIST_LOOP_MODE_MACSEC_SA_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_CTRL_PORT7_BIST_LOOP_MODE_MACSEC_SA_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT7_DYN_READ_EN_MACSEC_SA_AI_OFFSET (19) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT7_DYN_READ_EN_MACSEC_SA_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_CTRL_PORT7_DYN_READ_EN_MACSEC_SA_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT7_DRF_TESS_RESUME_MACSEC_SA_AI_OFFSET (18) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT7_DRF_TESS_RESUME_MACSEC_SA_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_CTRL_PORT7_DRF_TESS_RESUME_MACSEC_SA_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT7_MACSEC_SA_AE_ICG_EN_OFFSET (17) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT7_MACSEC_SA_AE_ICG_EN_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_CTRL_PORT7_MACSEC_SA_AE_ICG_EN_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT7_MACSEC_SA_AI_ICG_EN_OFFSET (16) + #define RTL8373_MACSEC_MBIST_SA_CTRL_PORT7_MACSEC_SA_AI_ICG_EN_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_CTRL_PORT7_MACSEC_SA_AI_ICG_EN_OFFSET) + +#define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_ADDR (0xD91C) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_DRF_START_PAUSE_MACSEC_SA_AE_OFFSET (27) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_DRF_START_PAUSE_MACSEC_SA_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_DRF_START_PAUSE_MACSEC_SA_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_BIST_DONE_MACSEC_SA_AE_OFFSET (26) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_BIST_DONE_MACSEC_SA_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_BIST_DONE_MACSEC_SA_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_DRF_BIST_DONE_MACSEC_SA_AE_OFFSET (25) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_DRF_BIST_DONE_MACSEC_SA_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_DRF_BIST_DONE_MACSEC_SA_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_DRF_START_PAUSE_MACSEC_SA_AI_OFFSET (24) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_DRF_START_PAUSE_MACSEC_SA_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_DRF_START_PAUSE_MACSEC_SA_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_BIST_DONE_MACSEC_SA_AI_OFFSET (23) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_BIST_DONE_MACSEC_SA_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_BIST_DONE_MACSEC_SA_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_DRF_BIST_DONE_MACSEC_SA_AI_OFFSET (22) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_DRF_BIST_DONE_MACSEC_SA_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_DRF_BIST_DONE_MACSEC_SA_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_DRF_START_PAUSE_MACSEC_STAT_AE_OFFSET (21) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_DRF_START_PAUSE_MACSEC_STAT_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_DRF_START_PAUSE_MACSEC_STAT_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_BIST_DONE_MACSEC_STAT_AE_OFFSET (20) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_BIST_DONE_MACSEC_STAT_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_BIST_DONE_MACSEC_STAT_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_DRF_BIST_DONE_MACSEC_STAT_AE_OFFSET (19) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_DRF_BIST_DONE_MACSEC_STAT_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_DRF_BIST_DONE_MACSEC_STAT_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_DRF_START_PAUSE_MACSEC_STAT_AI_OFFSET (18) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_DRF_START_PAUSE_MACSEC_STAT_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_DRF_START_PAUSE_MACSEC_STAT_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_BIST_DONE_MACSEC_STAT_AI_OFFSET (17) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_BIST_DONE_MACSEC_STAT_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_BIST_DONE_MACSEC_STAT_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_DRF_BIST_DONE_MACSEC_STAT_AI_OFFSET (16) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_DRF_BIST_DONE_MACSEC_STAT_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_DRF_BIST_DONE_MACSEC_STAT_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_BIST_MODE_MACSEC_STAT_AE_OFFSET (13) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_BIST_MODE_MACSEC_STAT_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_BIST_MODE_MACSEC_STAT_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_DRF_BIST_MODE_MACSEC_STAT_AE_OFFSET (12) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_DRF_BIST_MODE_MACSEC_STAT_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_DRF_BIST_MODE_MACSEC_STAT_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_BIST_RSTN_MACSEC_STAT_AE_OFFSET (11) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_BIST_RSTN_MACSEC_STAT_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_BIST_RSTN_MACSEC_STAT_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_BIST_LOOP_MODE_MACSEC_STAT_AE_OFFSET (10) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_BIST_LOOP_MODE_MACSEC_STAT_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_BIST_LOOP_MODE_MACSEC_STAT_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_DYN_READ_EN_MACSEC_STAT_AE_OFFSET (9) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_DYN_READ_EN_MACSEC_STAT_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_DYN_READ_EN_MACSEC_STAT_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_DRF_TESS_RESUME_MACSEC_STAT_AE_OFFSET (8) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_DRF_TESS_RESUME_MACSEC_STAT_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_DRF_TESS_RESUME_MACSEC_STAT_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_BIST_MODE_MACSEC_STAT_AI_OFFSET (7) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_BIST_MODE_MACSEC_STAT_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_BIST_MODE_MACSEC_STAT_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_DRF_BIST_MODE_MACSEC_STAT_AI_OFFSET (6) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_DRF_BIST_MODE_MACSEC_STAT_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_DRF_BIST_MODE_MACSEC_STAT_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_BIST_RSTN_MACSEC_STAT_AI_OFFSET (5) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_BIST_RSTN_MACSEC_STAT_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_BIST_RSTN_MACSEC_STAT_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_BIST_LOOP_MODE_MACSEC_STAT_AI_OFFSET (4) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_BIST_LOOP_MODE_MACSEC_STAT_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_BIST_LOOP_MODE_MACSEC_STAT_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_DYN_READ_EN_MACSEC_STAT_AI_OFFSET (3) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_DYN_READ_EN_MACSEC_STAT_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_DYN_READ_EN_MACSEC_STAT_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_DRF_TESS_RESUME_MACSEC_STAT_AI_OFFSET (2) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_DRF_TESS_RESUME_MACSEC_STAT_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_DRF_TESS_RESUME_MACSEC_STAT_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_MACSEC_STAT_AE_ICG_EN_OFFSET (1) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_MACSEC_STAT_AE_ICG_EN_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_MACSEC_STAT_AE_ICG_EN_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_MACSEC_STAT_AI_ICG_EN_OFFSET (0) + #define RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_MACSEC_STAT_AI_ICG_EN_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_CTRL_PORT7_MACSEC_STAT_AI_ICG_EN_OFFSET) + +#define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT7_ADDR (0xD920) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT7_MACSEC_SA_AI_DVSE_OFFSET (27) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT7_MACSEC_SA_AI_DVSE_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT7_MACSEC_SA_AI_DVSE_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT7_MACSEC_SA_AI_DVS_OFFSET (23) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT7_MACSEC_SA_AI_DVS_MASK (0xF << RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT7_MACSEC_SA_AI_DVS_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT7_MACSEC_SA_AI_LS_OFFSET (22) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT7_MACSEC_SA_AI_LS_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT7_MACSEC_SA_AI_LS_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT7_MACSEC_SA_AI_DS_OFFSET (21) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT7_MACSEC_SA_AI_DS_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT7_MACSEC_SA_AI_DS_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT7_MACSEC_SA_AI_SD_OFFSET (20) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT7_MACSEC_SA_AI_SD_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT7_MACSEC_SA_AI_SD_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT7_MACSEC_SA_AI3_TEST1_OFFSET (19) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT7_MACSEC_SA_AI3_TEST1_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT7_MACSEC_SA_AI3_TEST1_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT7_MACSEC_SA_AI2_TEST1_OFFSET (18) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT7_MACSEC_SA_AI2_TEST1_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT7_MACSEC_SA_AI2_TEST1_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT7_MACSEC_SA_AI1_TEST1_OFFSET (17) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT7_MACSEC_SA_AI1_TEST1_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT7_MACSEC_SA_AI1_TEST1_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT7_MACSEC_SA_AI0_TEST1_OFFSET (16) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT7_MACSEC_SA_AI0_TEST1_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT7_MACSEC_SA_AI0_TEST1_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT7_MACSEC_SA_AE_DVSE_OFFSET (11) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT7_MACSEC_SA_AE_DVSE_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT7_MACSEC_SA_AE_DVSE_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT7_MACSEC_SA_AE_DVS_OFFSET (7) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT7_MACSEC_SA_AE_DVS_MASK (0xF << RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT7_MACSEC_SA_AE_DVS_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT7_MACSEC_SA_AE_LS_OFFSET (6) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT7_MACSEC_SA_AE_LS_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT7_MACSEC_SA_AE_LS_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT7_MACSEC_SA_AE_DS_OFFSET (5) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT7_MACSEC_SA_AE_DS_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT7_MACSEC_SA_AE_DS_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT7_MACSEC_SA_AE_SD_OFFSET (4) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT7_MACSEC_SA_AE_SD_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT7_MACSEC_SA_AE_SD_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT7_MACSEC_SA_AE3_TEST1_OFFSET (3) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT7_MACSEC_SA_AE3_TEST1_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT7_MACSEC_SA_AE3_TEST1_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT7_MACSEC_SA_AE2_TEST1_OFFSET (2) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT7_MACSEC_SA_AE2_TEST1_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT7_MACSEC_SA_AE2_TEST1_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT7_MACSEC_SA_AE1_TEST1_OFFSET (1) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT7_MACSEC_SA_AE1_TEST1_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT7_MACSEC_SA_AE1_TEST1_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT7_MACSEC_SA_AE0_TEST1_OFFSET (0) + #define RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT7_MACSEC_SA_AE0_TEST1_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_AE_TEST_PORT7_MACSEC_SA_AE0_TEST1_OFFSET) + +#define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT7_ADDR (0xD924) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT7_MACSEC_STAT_AI_DVSE_OFFSET (25) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT7_MACSEC_STAT_AI_DVSE_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT7_MACSEC_STAT_AI_DVSE_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT7_MACSEC_STAT_AI_DVS_OFFSET (21) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT7_MACSEC_STAT_AI_DVS_MASK (0xF << RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT7_MACSEC_STAT_AI_DVS_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT7_MACSEC_STAT_AI_LS_OFFSET (20) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT7_MACSEC_STAT_AI_LS_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT7_MACSEC_STAT_AI_LS_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT7_MACSEC_STAT_AI_DS_OFFSET (19) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT7_MACSEC_STAT_AI_DS_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT7_MACSEC_STAT_AI_DS_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT7_MACSEC_STAT_AI_SD_OFFSET (18) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT7_MACSEC_STAT_AI_SD_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT7_MACSEC_STAT_AI_SD_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT7_MACSEC_STAT_AI_TEST1_OFFSET (17) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT7_MACSEC_STAT_AI_TEST1_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT7_MACSEC_STAT_AI_TEST1_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT7_MACSEC_STAT_AI_TESTRWM_OFFSET (16) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT7_MACSEC_STAT_AI_TESTRWM_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT7_MACSEC_STAT_AI_TESTRWM_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT7_MACSEC_STAT_AE_DVSE_OFFSET (9) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT7_MACSEC_STAT_AE_DVSE_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT7_MACSEC_STAT_AE_DVSE_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT7_MACSEC_STAT_AE_DVS_OFFSET (5) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT7_MACSEC_STAT_AE_DVS_MASK (0xF << RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT7_MACSEC_STAT_AE_DVS_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT7_MACSEC_STAT_AE_LS_OFFSET (4) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT7_MACSEC_STAT_AE_LS_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT7_MACSEC_STAT_AE_LS_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT7_MACSEC_STAT_AE_DS_OFFSET (3) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT7_MACSEC_STAT_AE_DS_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT7_MACSEC_STAT_AE_DS_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT7_MACSEC_STAT_AE_SD_OFFSET (2) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT7_MACSEC_STAT_AE_SD_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT7_MACSEC_STAT_AE_SD_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT7_MACSEC_STAT_AE_TEST1_OFFSET (1) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT7_MACSEC_STAT_AE_TEST1_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT7_MACSEC_STAT_AE_TEST1_OFFSET) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT7_MACSEC_STAT_AE_TESTRWM_OFFSET (0) + #define RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT7_MACSEC_STAT_AE_TESTRWM_MASK (0x1 << RTL8373_MACSEC_MBIST_STAT_AE_TEST_PORT7_MACSEC_STAT_AE_TESTRWM_OFFSET) + +#define RTL8373_MACSEC_MBIST_SA_FAIL_PORT7_ADDR (0xD928) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT7_BIST_FAIL_MACSEC_STAT_AE_OFFSET (19) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT7_BIST_FAIL_MACSEC_STAT_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT7_BIST_FAIL_MACSEC_STAT_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT7_DRF_BIST_FAIL_MACSEC_STAT_AE_OFFSET (18) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT7_DRF_BIST_FAIL_MACSEC_STAT_AE_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT7_DRF_BIST_FAIL_MACSEC_STAT_AE_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT7_BIST_FAIL_MACSEC_STAT_AI_OFFSET (17) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT7_BIST_FAIL_MACSEC_STAT_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT7_BIST_FAIL_MACSEC_STAT_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT7_DRF_BIST_FAIL_MACSEC_STAT_AI_OFFSET (16) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT7_DRF_BIST_FAIL_MACSEC_STAT_AI_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT7_DRF_BIST_FAIL_MACSEC_STAT_AI_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT7_BIST_FAIL_MACSEC_SA_AE3_OFFSET (15) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT7_BIST_FAIL_MACSEC_SA_AE3_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT7_BIST_FAIL_MACSEC_SA_AE3_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT7_DRF_BIST_FAIL_MACSEC_SA_AE3_OFFSET (14) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT7_DRF_BIST_FAIL_MACSEC_SA_AE3_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT7_DRF_BIST_FAIL_MACSEC_SA_AE3_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT7_BIST_FAIL_MACSEC_SA_AE2_OFFSET (13) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT7_BIST_FAIL_MACSEC_SA_AE2_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT7_BIST_FAIL_MACSEC_SA_AE2_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT7_DRF_BIST_FAIL_MACSEC_SA_AE2_OFFSET (12) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT7_DRF_BIST_FAIL_MACSEC_SA_AE2_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT7_DRF_BIST_FAIL_MACSEC_SA_AE2_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT7_BIST_FAIL_MACSEC_SA_AE1_OFFSET (11) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT7_BIST_FAIL_MACSEC_SA_AE1_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT7_BIST_FAIL_MACSEC_SA_AE1_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT7_DRF_BIST_FAIL_MACSEC_SA_AE1_OFFSET (10) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT7_DRF_BIST_FAIL_MACSEC_SA_AE1_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT7_DRF_BIST_FAIL_MACSEC_SA_AE1_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT7_BIST_FAIL_MACSEC_SA_AE0_OFFSET (9) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT7_BIST_FAIL_MACSEC_SA_AE0_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT7_BIST_FAIL_MACSEC_SA_AE0_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT7_DRF_BIST_FAIL_MACSEC_SA_AE0_OFFSET (8) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT7_DRF_BIST_FAIL_MACSEC_SA_AE0_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT7_DRF_BIST_FAIL_MACSEC_SA_AE0_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT7_BIST_FAIL_MACSEC_SA_AI3_OFFSET (7) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT7_BIST_FAIL_MACSEC_SA_AI3_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT7_BIST_FAIL_MACSEC_SA_AI3_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT7_DRF_BIST_FAIL_MACSEC_SA_AI3_OFFSET (6) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT7_DRF_BIST_FAIL_MACSEC_SA_AI3_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT7_DRF_BIST_FAIL_MACSEC_SA_AI3_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT7_BIST_FAIL_MACSEC_SA_AI2_OFFSET (5) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT7_BIST_FAIL_MACSEC_SA_AI2_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT7_BIST_FAIL_MACSEC_SA_AI2_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT7_DRF_BIST_FAIL_MACSEC_SA_AI2_OFFSET (4) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT7_DRF_BIST_FAIL_MACSEC_SA_AI2_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT7_DRF_BIST_FAIL_MACSEC_SA_AI2_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT7_BIST_FAIL_MACSEC_SA_AI1_OFFSET (3) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT7_BIST_FAIL_MACSEC_SA_AI1_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT7_BIST_FAIL_MACSEC_SA_AI1_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT7_DRF_BIST_FAIL_MACSEC_SA_AI1_OFFSET (2) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT7_DRF_BIST_FAIL_MACSEC_SA_AI1_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT7_DRF_BIST_FAIL_MACSEC_SA_AI1_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT7_BIST_FAIL_MACSEC_SA_AI0_OFFSET (1) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT7_BIST_FAIL_MACSEC_SA_AI0_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT7_BIST_FAIL_MACSEC_SA_AI0_OFFSET) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT7_DRF_BIST_FAIL_MACSEC_SA_AI0_OFFSET (0) + #define RTL8373_MACSEC_MBIST_SA_FAIL_PORT7_DRF_BIST_FAIL_MACSEC_SA_AI0_MASK (0x1 << RTL8373_MACSEC_MBIST_SA_FAIL_PORT7_DRF_BIST_FAIL_MACSEC_SA_AI0_OFFSET) + +#define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT7_ADDR (0xD92C) + #define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT7_CFG_WATER_LEVEL_ST_OFFSET (28) + #define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT7_CFG_WATER_LEVEL_ST_MASK (0xF << RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT7_CFG_WATER_LEVEL_ST_OFFSET) + #define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT7_CFG_WATER_LEVEL_H_OFFSET (24) + #define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT7_CFG_WATER_LEVEL_H_MASK (0xF << RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT7_CFG_WATER_LEVEL_H_OFFSET) + #define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT7_CFG_WATER_LEVEL_L_OFFSET (20) + #define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT7_CFG_WATER_LEVEL_L_MASK (0xF << RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT7_CFG_WATER_LEVEL_L_OFFSET) + #define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT7_CFG_FAULT_ON_OFFSET (19) + #define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT7_CFG_FAULT_ON_MASK (0x1 << RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT7_CFG_FAULT_ON_OFFSET) + #define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT7_CFG_ERROR_ON_OFFSET (18) + #define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT7_CFG_ERROR_ON_MASK (0x1 << RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT7_CFG_ERROR_ON_OFFSET) + #define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT7_CFG_SEQ_RSV_ON_OFFSET (17) + #define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT7_CFG_SEQ_RSV_ON_MASK (0x1 << RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT7_CFG_SEQ_RSV_ON_OFFSET) + #define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT7_CFG_CLR_FIFO_OVTHR_OFFSET (16) + #define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT7_CFG_CLR_FIFO_OVTHR_MASK (0x1 << RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT7_CFG_CLR_FIFO_OVTHR_OFFSET) + #define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT7_XGLBK_FIFO_DBG_EN_OFFSET (4) + #define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT7_XGLBK_FIFO_DBG_EN_MASK (0x1 << RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT7_XGLBK_FIFO_DBG_EN_OFFSET) + #define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT7_XGLBK_FIFO_DBG_SEL_OFFSET (0) + #define RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT7_XGLBK_FIFO_DBG_SEL_MASK (0xF << RTL8373_MACSEC_XGLBK_FIFO_DBG_PORT7_XGLBK_FIFO_DBG_SEL_OFFSET) + +#define RTL8373_MACSEC_REG_RWDH_AE_PORT7_ADDR (0xD930) + #define RTL8373_MACSEC_REG_RWDH_AE_PORT7_REG_DATA_AE_L_OFFSET (16) + #define RTL8373_MACSEC_REG_RWDH_AE_PORT7_REG_DATA_AE_L_MASK (0xFFFF << RTL8373_MACSEC_REG_RWDH_AE_PORT7_REG_DATA_AE_L_OFFSET) + #define RTL8373_MACSEC_REG_RWDH_AE_PORT7_REG_DATA_AE_H_OFFSET (0) + #define RTL8373_MACSEC_REG_RWDH_AE_PORT7_REG_DATA_AE_H_MASK (0xFFFF << RTL8373_MACSEC_REG_RWDH_AE_PORT7_REG_DATA_AE_H_OFFSET) + +#define RTL8373_MACSEC_REG_ADDR_AE_PORT7_ADDR (0xD934) + #define RTL8373_MACSEC_REG_ADDR_AE_PORT7_REG_ADDR_AE_OFFSET (16) + #define RTL8373_MACSEC_REG_ADDR_AE_PORT7_REG_ADDR_AE_MASK (0xFFFF << RTL8373_MACSEC_REG_ADDR_AE_PORT7_REG_ADDR_AE_OFFSET) + +#define RTL8373_MACSEC_REG_CMD_AE_PORT7_ADDR (0xD938) + #define RTL8373_MACSEC_REG_CMD_AE_PORT7_REG_DATA_AI_H_OFFSET (16) + #define RTL8373_MACSEC_REG_CMD_AE_PORT7_REG_DATA_AI_H_MASK (0xFFFF << RTL8373_MACSEC_REG_CMD_AE_PORT7_REG_DATA_AI_H_OFFSET) + #define RTL8373_MACSEC_REG_CMD_AE_PORT7_REG_RD_REQ_AE_OFFSET (4) + #define RTL8373_MACSEC_REG_CMD_AE_PORT7_REG_RD_REQ_AE_MASK (0x1 << RTL8373_MACSEC_REG_CMD_AE_PORT7_REG_RD_REQ_AE_OFFSET) + #define RTL8373_MACSEC_REG_CMD_AE_PORT7_REG_WR_REQ_AE_OFFSET (0) + #define RTL8373_MACSEC_REG_CMD_AE_PORT7_REG_WR_REQ_AE_MASK (0x1 << RTL8373_MACSEC_REG_CMD_AE_PORT7_REG_WR_REQ_AE_OFFSET) + +#define RTL8373_MACSEC_REG_RWDL_AI_PORT7_ADDR (0xD93C) + #define RTL8373_MACSEC_REG_RWDL_AI_PORT7_REG_DATA_AI_L_OFFSET (0) + #define RTL8373_MACSEC_REG_RWDL_AI_PORT7_REG_DATA_AI_L_MASK (0xFFFF << RTL8373_MACSEC_REG_RWDL_AI_PORT7_REG_DATA_AI_L_OFFSET) + +#define RTL8373_MACSEC_REG_ADDR_AI_PORT7_ADDR (0xD940) + #define RTL8373_MACSEC_REG_ADDR_AI_PORT7_REG_RD_REQ_AI_OFFSET (20) + #define RTL8373_MACSEC_REG_ADDR_AI_PORT7_REG_RD_REQ_AI_MASK (0x1 << RTL8373_MACSEC_REG_ADDR_AI_PORT7_REG_RD_REQ_AI_OFFSET) + #define RTL8373_MACSEC_REG_ADDR_AI_PORT7_REG_WR_REQ_AI_OFFSET (16) + #define RTL8373_MACSEC_REG_ADDR_AI_PORT7_REG_WR_REQ_AI_MASK (0x1 << RTL8373_MACSEC_REG_ADDR_AI_PORT7_REG_WR_REQ_AI_OFFSET) + #define RTL8373_MACSEC_REG_ADDR_AI_PORT7_REG_ADDR_AI_OFFSET (0) + #define RTL8373_MACSEC_REG_ADDR_AI_PORT7_REG_ADDR_AI_MASK (0xFFFF << RTL8373_MACSEC_REG_ADDR_AI_PORT7_REG_ADDR_AI_OFFSET) + +#define RTL8373_MACSEC_REG_RWD_PTP_PORT7_ADDR (0xD944) + #define RTL8373_MACSEC_REG_RWD_PTP_PORT7_REG_ADDR_PTP_OFFSET (16) + #define RTL8373_MACSEC_REG_RWD_PTP_PORT7_REG_ADDR_PTP_MASK (0xFFFF << RTL8373_MACSEC_REG_RWD_PTP_PORT7_REG_ADDR_PTP_OFFSET) + #define RTL8373_MACSEC_REG_RWD_PTP_PORT7_REG_DATA_PTP_OFFSET (0) + #define RTL8373_MACSEC_REG_RWD_PTP_PORT7_REG_DATA_PTP_MASK (0xFFFF << RTL8373_MACSEC_REG_RWD_PTP_PORT7_REG_DATA_PTP_OFFSET) + +#define RTL8373_MACSEC_REG_CMD_PTP_PORT7_ADDR (0xD948) + #define RTL8373_MACSEC_REG_CMD_PTP_PORT7_REG_RD_REQ_PTP_OFFSET (4) + #define RTL8373_MACSEC_REG_CMD_PTP_PORT7_REG_RD_REQ_PTP_MASK (0x1 << RTL8373_MACSEC_REG_CMD_PTP_PORT7_REG_RD_REQ_PTP_OFFSET) + #define RTL8373_MACSEC_REG_CMD_PTP_PORT7_REG_WR_REQ_PTP_OFFSET (0) + #define RTL8373_MACSEC_REG_CMD_PTP_PORT7_REG_WR_REQ_PTP_MASK (0x1 << RTL8373_MACSEC_REG_CMD_PTP_PORT7_REG_WR_REQ_PTP_OFFSET) + +#define RTL8373_UNUSED_005C_PORT7_ADDR (0xD94C) + #define RTL8373_UNUSED_005C_PORT7_UNUSED_005C_PORT7_OFFSET (0) + #define RTL8373_UNUSED_005C_PORT7_UNUSED_005C_PORT7_MASK (0xFFFFFFFF << RTL8373_UNUSED_005C_PORT7_UNUSED_005C_PORT7_OFFSET) + +#define RTL8373_UNUSED_0060_PORT7_ADDR (0xD950) + #define RTL8373_UNUSED_0060_PORT7_UNUSED_0060_PORT7_OFFSET (0) + #define RTL8373_UNUSED_0060_PORT7_UNUSED_0060_PORT7_MASK (0xFFFFFFFF << RTL8373_UNUSED_0060_PORT7_UNUSED_0060_PORT7_OFFSET) + +#define RTL8373_UNUSED_0064_PORT7_ADDR (0xD954) + #define RTL8373_UNUSED_0064_PORT7_UNUSED_0064_PORT7_OFFSET (0) + #define RTL8373_UNUSED_0064_PORT7_UNUSED_0064_PORT7_MASK (0xFFFFFFFF << RTL8373_UNUSED_0064_PORT7_UNUSED_0064_PORT7_OFFSET) + +#define RTL8373_UNUSED_0068_PORT7_ADDR (0xD958) + #define RTL8373_UNUSED_0068_PORT7_UNUSED_0068_PORT7_OFFSET (0) + #define RTL8373_UNUSED_0068_PORT7_UNUSED_0068_PORT7_MASK (0xFFFFFFFF << RTL8373_UNUSED_0068_PORT7_UNUSED_0068_PORT7_OFFSET) + +#define RTL8373_UNUSED_006C_PORT7_ADDR (0xD95C) + #define RTL8373_UNUSED_006C_PORT7_UNUSED_006C_PORT7_OFFSET (0) + #define RTL8373_UNUSED_006C_PORT7_UNUSED_006C_PORT7_MASK (0xFFFFFFFF << RTL8373_UNUSED_006C_PORT7_UNUSED_006C_PORT7_OFFSET) + +#define RTL8373_UNUSED_0070_PORT7_ADDR (0xD960) + #define RTL8373_UNUSED_0070_PORT7_UNUSED_0070_PORT7_OFFSET (0) + #define RTL8373_UNUSED_0070_PORT7_UNUSED_0070_PORT7_MASK (0xFFFFFFFF << RTL8373_UNUSED_0070_PORT7_UNUSED_0070_PORT7_OFFSET) + +#define RTL8373_UNUSED_0074_PORT7_ADDR (0xD964) + #define RTL8373_UNUSED_0074_PORT7_UNUSED_0074_PORT7_OFFSET (0) + #define RTL8373_UNUSED_0074_PORT7_UNUSED_0074_PORT7_MASK (0xFFFFFFFF << RTL8373_UNUSED_0074_PORT7_UNUSED_0074_PORT7_OFFSET) + +#define RTL8373_RESERVED_0078_PORT7_ADDR (0xD968) + #define RTL8373_RESERVED_0078_PORT7_RESERVED_0078_PORT7_OFFSET (0) + #define RTL8373_RESERVED_0078_PORT7_RESERVED_0078_PORT7_MASK (0xFFFFFFFF << RTL8373_RESERVED_0078_PORT7_RESERVED_0078_PORT7_OFFSET) + +#define RTL8373_RESERVED_007C_PORT7_ADDR (0xD96C) + #define RTL8373_RESERVED_007C_PORT7_RESERVED_007C_PORT7_OFFSET (0) + #define RTL8373_RESERVED_007C_PORT7_RESERVED_007C_PORT7_MASK (0xFFFFFFFF << RTL8373_RESERVED_007C_PORT7_RESERVED_007C_PORT7_OFFSET) + +#define RTL8373_MACSEC_TXSYSCRCERR_CNT_PORT7_ADDR (0xD970) + #define RTL8373_MACSEC_TXSYSCRCERR_CNT_PORT7_TXSYS_CRCERR_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_TXSYSCRCERR_CNT_PORT7_TXSYS_CRCERR_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_TXSYSCRCERR_CNT_PORT7_TXSYS_CRCERR_CNT_H_OFFSET) + #define RTL8373_MACSEC_TXSYSCRCERR_CNT_PORT7_TXSYS_CRCERR_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_TXSYSCRCERR_CNT_PORT7_TXSYS_CRCERR_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_TXSYSCRCERR_CNT_PORT7_TXSYS_CRCERR_CNT_L_OFFSET) + +#define RTL8373_MACSEC_TXSYSPKTERR_CNT_PORT7_ADDR (0xD974) + #define RTL8373_MACSEC_TXSYSPKTERR_CNT_PORT7_TXSYS_PKTERR_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_TXSYSPKTERR_CNT_PORT7_TXSYS_PKTERR_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_TXSYSPKTERR_CNT_PORT7_TXSYS_PKTERR_CNT_H_OFFSET) + #define RTL8373_MACSEC_TXSYSPKTERR_CNT_PORT7_TXSYS_PKTERR_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_TXSYSPKTERR_CNT_PORT7_TXSYS_PKTERR_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_TXSYSPKTERR_CNT_PORT7_TXSYS_PKTERR_CNT_L_OFFSET) + +#define RTL8373_MACSEC_TXSYSOK_CNT_0_PORT7_ADDR (0xD978) + #define RTL8373_MACSEC_TXSYSOK_CNT_0_PORT7_TXSYS_OK_CNT_1_OFFSET (16) + #define RTL8373_MACSEC_TXSYSOK_CNT_0_PORT7_TXSYS_OK_CNT_1_MASK (0xFFFF << RTL8373_MACSEC_TXSYSOK_CNT_0_PORT7_TXSYS_OK_CNT_1_OFFSET) + #define RTL8373_MACSEC_TXSYSOK_CNT_0_PORT7_TXSYS_OK_CNT_0_OFFSET (0) + #define RTL8373_MACSEC_TXSYSOK_CNT_0_PORT7_TXSYS_OK_CNT_0_MASK (0xFFFF << RTL8373_MACSEC_TXSYSOK_CNT_0_PORT7_TXSYS_OK_CNT_0_OFFSET) + +#define RTL8373_MACSEC_TXSYSOK_CNT_2_PORT7_ADDR (0xD97C) + #define RTL8373_MACSEC_TXSYSOK_CNT_2_PORT7_TXSYS_OK_CNT_3_OFFSET (16) + #define RTL8373_MACSEC_TXSYSOK_CNT_2_PORT7_TXSYS_OK_CNT_3_MASK (0xFFFF << RTL8373_MACSEC_TXSYSOK_CNT_2_PORT7_TXSYS_OK_CNT_3_OFFSET) + #define RTL8373_MACSEC_TXSYSOK_CNT_2_PORT7_TXSYS_OK_CNT_2_OFFSET (0) + #define RTL8373_MACSEC_TXSYSOK_CNT_2_PORT7_TXSYS_OK_CNT_2_MASK (0xFFFF << RTL8373_MACSEC_TXSYSOK_CNT_2_PORT7_TXSYS_OK_CNT_2_OFFSET) + +#define RTL8373_MACSEC_TXSYSGERR_CNT_PORT7_ADDR (0xD980) + #define RTL8373_MACSEC_TXSYSGERR_CNT_PORT7_TXSYS_GERR_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_TXSYSGERR_CNT_PORT7_TXSYS_GERR_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_TXSYSGERR_CNT_PORT7_TXSYS_GERR_CNT_H_OFFSET) + #define RTL8373_MACSEC_TXSYSGERR_CNT_PORT7_TXSYS_GERR_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_TXSYSGERR_CNT_PORT7_TXSYS_GERR_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_TXSYSGERR_CNT_PORT7_TXSYS_GERR_CNT_L_OFFSET) + +#define RTL8373_MACSEC_TXSYSGLPIERR_CNT_PORT7_ADDR (0xD984) + #define RTL8373_MACSEC_TXSYSGLPIERR_CNT_PORT7_TXSYS_GLPIERR_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_TXSYSGLPIERR_CNT_PORT7_TXSYS_GLPIERR_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_TXSYSGLPIERR_CNT_PORT7_TXSYS_GLPIERR_CNT_H_OFFSET) + #define RTL8373_MACSEC_TXSYSGLPIERR_CNT_PORT7_TXSYS_GLPIERR_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_TXSYSGLPIERR_CNT_PORT7_TXSYS_GLPIERR_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_TXSYSGLPIERR_CNT_PORT7_TXSYS_GLPIERR_CNT_L_OFFSET) + +#define RTL8373_MACSEC_TXSYS_DBG_PORT7_ADDR (0xD988) + #define RTL8373_MACSEC_TXSYS_DBG_PORT7_TXSYS_XG2IP_FSM_OFFSET (16) + #define RTL8373_MACSEC_TXSYS_DBG_PORT7_TXSYS_XG2IP_FSM_MASK (0xF << RTL8373_MACSEC_TXSYS_DBG_PORT7_TXSYS_XG2IP_FSM_OFFSET) + #define RTL8373_MACSEC_TXSYS_DBG_PORT7_TXSYS_WRP2IP_FSM_OFFSET (0) + #define RTL8373_MACSEC_TXSYS_DBG_PORT7_TXSYS_WRP2IP_FSM_MASK (0xF << RTL8373_MACSEC_TXSYS_DBG_PORT7_TXSYS_WRP2IP_FSM_OFFSET) + +#define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT7_ADDR (0xD98C) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT7_RXSYS_UNDERRUN_CNT_INCR_OFFSET (27) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT7_RXSYS_UNDERRUN_CNT_INCR_MASK (0x1 << RTL8373_MACSEC_TX_RX_CNT_INCR_PORT7_RXSYS_UNDERRUN_CNT_INCR_OFFSET) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT7_RXSYS_DROP_CNT_INCR_OFFSET (26) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT7_RXSYS_DROP_CNT_INCR_MASK (0x1 << RTL8373_MACSEC_TX_RX_CNT_INCR_PORT7_RXSYS_DROP_CNT_INCR_OFFSET) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT7_RXSYS_PKTERR_CNT_INCR_OFFSET (25) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT7_RXSYS_PKTERR_CNT_INCR_MASK (0x1 << RTL8373_MACSEC_TX_RX_CNT_INCR_PORT7_RXSYS_PKTERR_CNT_INCR_OFFSET) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT7_RXSYS_CRCERR_CNT_INCR_OFFSET (24) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT7_RXSYS_CRCERR_CNT_INCR_MASK (0x1 << RTL8373_MACSEC_TX_RX_CNT_INCR_PORT7_RXSYS_CRCERR_CNT_INCR_OFFSET) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT7_RXLINE_OVERFLOW_CNT_INCR_OFFSET (18) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT7_RXLINE_OVERFLOW_CNT_INCR_MASK (0x1 << RTL8373_MACSEC_TX_RX_CNT_INCR_PORT7_RXLINE_OVERFLOW_CNT_INCR_OFFSET) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT7_RXLINE_PKTERR_CNT_INCR_OFFSET (17) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT7_RXLINE_PKTERR_CNT_INCR_MASK (0x1 << RTL8373_MACSEC_TX_RX_CNT_INCR_PORT7_RXLINE_PKTERR_CNT_INCR_OFFSET) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT7_RXLINE_CRCERR_CNT_INCR_OFFSET (16) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT7_RXLINE_CRCERR_CNT_INCR_MASK (0x1 << RTL8373_MACSEC_TX_RX_CNT_INCR_PORT7_RXLINE_CRCERR_CNT_INCR_OFFSET) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT7_TXLINE_UNDERRUN_CNT_INCR_OFFSET (11) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT7_TXLINE_UNDERRUN_CNT_INCR_MASK (0x1 << RTL8373_MACSEC_TX_RX_CNT_INCR_PORT7_TXLINE_UNDERRUN_CNT_INCR_OFFSET) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT7_TXLINE_DROP_CNT_INCR_OFFSET (10) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT7_TXLINE_DROP_CNT_INCR_MASK (0x1 << RTL8373_MACSEC_TX_RX_CNT_INCR_PORT7_TXLINE_DROP_CNT_INCR_OFFSET) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT7_TXLINE_PKTERR_CNT_INCR_OFFSET (9) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT7_TXLINE_PKTERR_CNT_INCR_MASK (0x1 << RTL8373_MACSEC_TX_RX_CNT_INCR_PORT7_TXLINE_PKTERR_CNT_INCR_OFFSET) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT7_TXLINE_CRCERR_CNT_INCR_OFFSET (8) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT7_TXLINE_CRCERR_CNT_INCR_MASK (0x1 << RTL8373_MACSEC_TX_RX_CNT_INCR_PORT7_TXLINE_CRCERR_CNT_INCR_OFFSET) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT7_TXSYS_OVERFLOW_CNT_INCR_OFFSET (2) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT7_TXSYS_OVERFLOW_CNT_INCR_MASK (0x1 << RTL8373_MACSEC_TX_RX_CNT_INCR_PORT7_TXSYS_OVERFLOW_CNT_INCR_OFFSET) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT7_TXSYS_PKTERR_CNT_INCR_OFFSET (1) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT7_TXSYS_PKTERR_CNT_INCR_MASK (0x1 << RTL8373_MACSEC_TX_RX_CNT_INCR_PORT7_TXSYS_PKTERR_CNT_INCR_OFFSET) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT7_TXSYS_CRCERR_CNT_INCR_OFFSET (0) + #define RTL8373_MACSEC_TX_RX_CNT_INCR_PORT7_TXSYS_CRCERR_CNT_INCR_MASK (0x1 << RTL8373_MACSEC_TX_RX_CNT_INCR_PORT7_TXSYS_CRCERR_CNT_INCR_OFFSET) + +#define RTL8373_MACSEC_TXLINECRCERR_CNT_PORT7_ADDR (0xD990) + #define RTL8373_MACSEC_TXLINECRCERR_CNT_PORT7_TXLINE_CRCERR_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_TXLINECRCERR_CNT_PORT7_TXLINE_CRCERR_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_TXLINECRCERR_CNT_PORT7_TXLINE_CRCERR_CNT_H_OFFSET) + #define RTL8373_MACSEC_TXLINECRCERR_CNT_PORT7_TXLINE_CRCERR_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_TXLINECRCERR_CNT_PORT7_TXLINE_CRCERR_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_TXLINECRCERR_CNT_PORT7_TXLINE_CRCERR_CNT_L_OFFSET) + +#define RTL8373_MACSEC_TXLINEPKTERR_CNT_PORT7_ADDR (0xD994) + #define RTL8373_MACSEC_TXLINEPKTERR_CNT_PORT7_TXLINE_PKTERR_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_TXLINEPKTERR_CNT_PORT7_TXLINE_PKTERR_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_TXLINEPKTERR_CNT_PORT7_TXLINE_PKTERR_CNT_H_OFFSET) + #define RTL8373_MACSEC_TXLINEPKTERR_CNT_PORT7_TXLINE_PKTERR_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_TXLINEPKTERR_CNT_PORT7_TXLINE_PKTERR_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_TXLINEPKTERR_CNT_PORT7_TXLINE_PKTERR_CNT_L_OFFSET) + +#define RTL8373_MACSEC_TXLINEOK_CNT_0_PORT7_ADDR (0xD998) + #define RTL8373_MACSEC_TXLINEOK_CNT_0_PORT7_TXLINE_OK_CNT_1_OFFSET (16) + #define RTL8373_MACSEC_TXLINEOK_CNT_0_PORT7_TXLINE_OK_CNT_1_MASK (0xFFFF << RTL8373_MACSEC_TXLINEOK_CNT_0_PORT7_TXLINE_OK_CNT_1_OFFSET) + #define RTL8373_MACSEC_TXLINEOK_CNT_0_PORT7_TXLINE_OK_CNT_0_OFFSET (0) + #define RTL8373_MACSEC_TXLINEOK_CNT_0_PORT7_TXLINE_OK_CNT_0_MASK (0xFFFF << RTL8373_MACSEC_TXLINEOK_CNT_0_PORT7_TXLINE_OK_CNT_0_OFFSET) + +#define RTL8373_MACSEC_TXLINEOK_CNT_2_PORT7_ADDR (0xD99C) + #define RTL8373_MACSEC_TXLINEOK_CNT_2_PORT7_TXLINE_OK_CNT_3_OFFSET (16) + #define RTL8373_MACSEC_TXLINEOK_CNT_2_PORT7_TXLINE_OK_CNT_3_MASK (0xFFFF << RTL8373_MACSEC_TXLINEOK_CNT_2_PORT7_TXLINE_OK_CNT_3_OFFSET) + #define RTL8373_MACSEC_TXLINEOK_CNT_2_PORT7_TXLINE_OK_CNT_2_OFFSET (0) + #define RTL8373_MACSEC_TXLINEOK_CNT_2_PORT7_TXLINE_OK_CNT_2_MASK (0xFFFF << RTL8373_MACSEC_TXLINEOK_CNT_2_PORT7_TXLINE_OK_CNT_2_OFFSET) + +#define RTL8373_MACSEC_TXLINEDROP_CNT_PORT7_ADDR (0xD9A0) + #define RTL8373_MACSEC_TXLINEDROP_CNT_PORT7_TXLINE_DROP_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_TXLINEDROP_CNT_PORT7_TXLINE_DROP_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_TXLINEDROP_CNT_PORT7_TXLINE_DROP_CNT_H_OFFSET) + #define RTL8373_MACSEC_TXLINEDROP_CNT_PORT7_TXLINE_DROP_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_TXLINEDROP_CNT_PORT7_TXLINE_DROP_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_TXLINEDROP_CNT_PORT7_TXLINE_DROP_CNT_L_OFFSET) + +#define RTL8373_MACSEC_TXLINESRT_CNT_PORT7_ADDR (0xD9A4) + #define RTL8373_MACSEC_TXLINESRT_CNT_PORT7_TXLINE_SRTPKT_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_TXLINESRT_CNT_PORT7_TXLINE_SRTPKT_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_TXLINESRT_CNT_PORT7_TXLINE_SRTPKT_CNT_H_OFFSET) + #define RTL8373_MACSEC_TXLINESRT_CNT_PORT7_TXLINE_SRTPKT_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_TXLINESRT_CNT_PORT7_TXLINE_SRTPKT_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_TXLINESRT_CNT_PORT7_TXLINE_SRTPKT_CNT_L_OFFSET) + +#define RTL8373_MACSEC_TXLINEGERR_CNT_PORT7_ADDR (0xD9A8) + #define RTL8373_MACSEC_TXLINEGERR_CNT_PORT7_TXLINE_GERR_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_TXLINEGERR_CNT_PORT7_TXLINE_GERR_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_TXLINEGERR_CNT_PORT7_TXLINE_GERR_CNT_H_OFFSET) + #define RTL8373_MACSEC_TXLINEGERR_CNT_PORT7_TXLINE_GERR_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_TXLINEGERR_CNT_PORT7_TXLINE_GERR_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_TXLINEGERR_CNT_PORT7_TXLINE_GERR_CNT_L_OFFSET) + +#define RTL8373_MACSEC_TXLINE_DBG_PORT7_ADDR (0xD9AC) + #define RTL8373_MACSEC_TXLINE_DBG_PORT7_TXLINE_IP2XG_FSM_OFFSET (16) + #define RTL8373_MACSEC_TXLINE_DBG_PORT7_TXLINE_IP2XG_FSM_MASK (0x1F << RTL8373_MACSEC_TXLINE_DBG_PORT7_TXLINE_IP2XG_FSM_OFFSET) + #define RTL8373_MACSEC_TXLINE_DBG_PORT7_TXLINE_IP2WRP_FSM_OFFSET (0) + #define RTL8373_MACSEC_TXLINE_DBG_PORT7_TXLINE_IP2WRP_FSM_MASK (0xF << RTL8373_MACSEC_TXLINE_DBG_PORT7_TXLINE_IP2WRP_FSM_OFFSET) + +#define RTL8373_MACSEC_RXLINECRCERR_CNT_PORT7_ADDR (0xD9B0) + #define RTL8373_MACSEC_RXLINECRCERR_CNT_PORT7_RXLINE_CRCERR_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_RXLINECRCERR_CNT_PORT7_RXLINE_CRCERR_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_RXLINECRCERR_CNT_PORT7_RXLINE_CRCERR_CNT_H_OFFSET) + #define RTL8373_MACSEC_RXLINECRCERR_CNT_PORT7_RXLINE_CRCERR_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_RXLINECRCERR_CNT_PORT7_RXLINE_CRCERR_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_RXLINECRCERR_CNT_PORT7_RXLINE_CRCERR_CNT_L_OFFSET) + +#define RTL8373_MACSEC_RXLINEPKTERR_CNT_PORT7_ADDR (0xD9B4) + #define RTL8373_MACSEC_RXLINEPKTERR_CNT_PORT7_RXLINE_PKTERR_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_RXLINEPKTERR_CNT_PORT7_RXLINE_PKTERR_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_RXLINEPKTERR_CNT_PORT7_RXLINE_PKTERR_CNT_H_OFFSET) + #define RTL8373_MACSEC_RXLINEPKTERR_CNT_PORT7_RXLINE_PKTERR_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_RXLINEPKTERR_CNT_PORT7_RXLINE_PKTERR_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_RXLINEPKTERR_CNT_PORT7_RXLINE_PKTERR_CNT_L_OFFSET) + +#define RTL8373_MACSEC_RXLINEOK_CNT_0_PORT7_ADDR (0xD9B8) + #define RTL8373_MACSEC_RXLINEOK_CNT_0_PORT7_RXLINE_OK_CNT_1_OFFSET (16) + #define RTL8373_MACSEC_RXLINEOK_CNT_0_PORT7_RXLINE_OK_CNT_1_MASK (0xFFFF << RTL8373_MACSEC_RXLINEOK_CNT_0_PORT7_RXLINE_OK_CNT_1_OFFSET) + #define RTL8373_MACSEC_RXLINEOK_CNT_0_PORT7_RXLINE_OK_CNT_0_OFFSET (0) + #define RTL8373_MACSEC_RXLINEOK_CNT_0_PORT7_RXLINE_OK_CNT_0_MASK (0xFFFF << RTL8373_MACSEC_RXLINEOK_CNT_0_PORT7_RXLINE_OK_CNT_0_OFFSET) + +#define RTL8373_MACSEC_RXLINEOK_CNT_2_PORT7_ADDR (0xD9BC) + #define RTL8373_MACSEC_RXLINEOK_CNT_2_PORT7_RXLINE_OK_CNT_3_OFFSET (16) + #define RTL8373_MACSEC_RXLINEOK_CNT_2_PORT7_RXLINE_OK_CNT_3_MASK (0xFFFF << RTL8373_MACSEC_RXLINEOK_CNT_2_PORT7_RXLINE_OK_CNT_3_OFFSET) + #define RTL8373_MACSEC_RXLINEOK_CNT_2_PORT7_RXLINE_OK_CNT_2_OFFSET (0) + #define RTL8373_MACSEC_RXLINEOK_CNT_2_PORT7_RXLINE_OK_CNT_2_MASK (0xFFFF << RTL8373_MACSEC_RXLINEOK_CNT_2_PORT7_RXLINE_OK_CNT_2_OFFSET) + +#define RTL8373_MACSEC_RXLINESRT_CNT_PORT7_ADDR (0xD9C0) + #define RTL8373_MACSEC_RXLINESRT_CNT_PORT7_RXLINE_SHORTPKT_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_RXLINESRT_CNT_PORT7_RXLINE_SHORTPKT_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_RXLINESRT_CNT_PORT7_RXLINE_SHORTPKT_CNT_H_OFFSET) + #define RTL8373_MACSEC_RXLINESRT_CNT_PORT7_RXLINE_SHORTPKT_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_RXLINESRT_CNT_PORT7_RXLINE_SHORTPKT_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_RXLINESRT_CNT_PORT7_RXLINE_SHORTPKT_CNT_L_OFFSET) + +#define RTL8373_MACSEC_RXLINEGERR_CNT_PORT7_ADDR (0xD9C4) + #define RTL8373_MACSEC_RXLINEGERR_CNT_PORT7_RXLINE_GERR_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_RXLINEGERR_CNT_PORT7_RXLINE_GERR_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_RXLINEGERR_CNT_PORT7_RXLINE_GERR_CNT_H_OFFSET) + #define RTL8373_MACSEC_RXLINEGERR_CNT_PORT7_RXLINE_GERR_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_RXLINEGERR_CNT_PORT7_RXLINE_GERR_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_RXLINEGERR_CNT_PORT7_RXLINE_GERR_CNT_L_OFFSET) + +#define RTL8373_MACSEC_RXLINEGLPIERR_CNT_PORT7_ADDR (0xD9C8) + #define RTL8373_MACSEC_RXLINEGLPIERR_CNT_PORT7_RXLINE_GLPIERR_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_RXLINEGLPIERR_CNT_PORT7_RXLINE_GLPIERR_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_RXLINEGLPIERR_CNT_PORT7_RXLINE_GLPIERR_CNT_H_OFFSET) + #define RTL8373_MACSEC_RXLINEGLPIERR_CNT_PORT7_RXLINE_GLPIERR_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_RXLINEGLPIERR_CNT_PORT7_RXLINE_GLPIERR_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_RXLINEGLPIERR_CNT_PORT7_RXLINE_GLPIERR_CNT_L_OFFSET) + +#define RTL8373_MACSEC_RXLINE_DBG_PORT7_ADDR (0xD9CC) + #define RTL8373_MACSEC_RXLINE_DBG_PORT7_RXLINE_XG2IP_FSM_OFFSET (16) + #define RTL8373_MACSEC_RXLINE_DBG_PORT7_RXLINE_XG2IP_FSM_MASK (0xF << RTL8373_MACSEC_RXLINE_DBG_PORT7_RXLINE_XG2IP_FSM_OFFSET) + #define RTL8373_MACSEC_RXLINE_DBG_PORT7_RXLINE_WRP2IP_FSM_OFFSET (0) + #define RTL8373_MACSEC_RXLINE_DBG_PORT7_RXLINE_WRP2IP_FSM_MASK (0xF << RTL8373_MACSEC_RXLINE_DBG_PORT7_RXLINE_WRP2IP_FSM_OFFSET) + +#define RTL8373_MACSEC_RXSYSCRCERR_CNT_PORT7_ADDR (0xD9D0) + #define RTL8373_MACSEC_RXSYSCRCERR_CNT_PORT7_RXSYS_CRCERR_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_RXSYSCRCERR_CNT_PORT7_RXSYS_CRCERR_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_RXSYSCRCERR_CNT_PORT7_RXSYS_CRCERR_CNT_H_OFFSET) + #define RTL8373_MACSEC_RXSYSCRCERR_CNT_PORT7_RXSYS_CRCERR_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_RXSYSCRCERR_CNT_PORT7_RXSYS_CRCERR_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_RXSYSCRCERR_CNT_PORT7_RXSYS_CRCERR_CNT_L_OFFSET) + +#define RTL8373_MACSEC_RXSYSPKTERR_CNT_PORT7_ADDR (0xD9D4) + #define RTL8373_MACSEC_RXSYSPKTERR_CNT_PORT7_RXSYS_PKTERR_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_RXSYSPKTERR_CNT_PORT7_RXSYS_PKTERR_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_RXSYSPKTERR_CNT_PORT7_RXSYS_PKTERR_CNT_H_OFFSET) + #define RTL8373_MACSEC_RXSYSPKTERR_CNT_PORT7_RXSYS_PKTERR_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_RXSYSPKTERR_CNT_PORT7_RXSYS_PKTERR_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_RXSYSPKTERR_CNT_PORT7_RXSYS_PKTERR_CNT_L_OFFSET) + +#define RTL8373_MACSEC_RXSYSOK_CNT_0_PORT7_ADDR (0xD9D8) + #define RTL8373_MACSEC_RXSYSOK_CNT_0_PORT7_RXSYS_OK_CNT_1_OFFSET (16) + #define RTL8373_MACSEC_RXSYSOK_CNT_0_PORT7_RXSYS_OK_CNT_1_MASK (0xFFFF << RTL8373_MACSEC_RXSYSOK_CNT_0_PORT7_RXSYS_OK_CNT_1_OFFSET) + #define RTL8373_MACSEC_RXSYSOK_CNT_0_PORT7_RXSYS_OK_CNT_0_OFFSET (0) + #define RTL8373_MACSEC_RXSYSOK_CNT_0_PORT7_RXSYS_OK_CNT_0_MASK (0xFFFF << RTL8373_MACSEC_RXSYSOK_CNT_0_PORT7_RXSYS_OK_CNT_0_OFFSET) + +#define RTL8373_MACSEC_RXSYSOK_CNT_2_PORT7_ADDR (0xD9DC) + #define RTL8373_MACSEC_RXSYSOK_CNT_2_PORT7_RXSYS_OK_CNT_3_OFFSET (16) + #define RTL8373_MACSEC_RXSYSOK_CNT_2_PORT7_RXSYS_OK_CNT_3_MASK (0xFFFF << RTL8373_MACSEC_RXSYSOK_CNT_2_PORT7_RXSYS_OK_CNT_3_OFFSET) + #define RTL8373_MACSEC_RXSYSOK_CNT_2_PORT7_RXSYS_OK_CNT_2_OFFSET (0) + #define RTL8373_MACSEC_RXSYSOK_CNT_2_PORT7_RXSYS_OK_CNT_2_MASK (0xFFFF << RTL8373_MACSEC_RXSYSOK_CNT_2_PORT7_RXSYS_OK_CNT_2_OFFSET) + +#define RTL8373_MACSEC_RXSYSDROP_CNT_PORT7_ADDR (0xD9E0) + #define RTL8373_MACSEC_RXSYSDROP_CNT_PORT7_RXSYS_DROP_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_RXSYSDROP_CNT_PORT7_RXSYS_DROP_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_RXSYSDROP_CNT_PORT7_RXSYS_DROP_CNT_H_OFFSET) + #define RTL8373_MACSEC_RXSYSDROP_CNT_PORT7_RXSYS_DROP_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_RXSYSDROP_CNT_PORT7_RXSYS_DROP_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_RXSYSDROP_CNT_PORT7_RXSYS_DROP_CNT_L_OFFSET) + +#define RTL8373_MACSEC_RXSYSSRT_CNT_PORT7_ADDR (0xD9E4) + #define RTL8373_MACSEC_RXSYSSRT_CNT_PORT7_RXSYS_DECRYPTSRT_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_RXSYSSRT_CNT_PORT7_RXSYS_DECRYPTSRT_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_RXSYSSRT_CNT_PORT7_RXSYS_DECRYPTSRT_CNT_H_OFFSET) + #define RTL8373_MACSEC_RXSYSSRT_CNT_PORT7_RXSYS_DECRYPTSRT_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_RXSYSSRT_CNT_PORT7_RXSYS_DECRYPTSRT_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_RXSYSSRT_CNT_PORT7_RXSYS_DECRYPTSRT_CNT_L_OFFSET) + +#define RTL8373_MACSEC_RXSYSGERR_CNT_PORT7_ADDR (0xD9E8) + #define RTL8373_MACSEC_RXSYSGERR_CNT_PORT7_RXSYS_GERR_CNT_H_OFFSET (16) + #define RTL8373_MACSEC_RXSYSGERR_CNT_PORT7_RXSYS_GERR_CNT_H_MASK (0xFFFF << RTL8373_MACSEC_RXSYSGERR_CNT_PORT7_RXSYS_GERR_CNT_H_OFFSET) + #define RTL8373_MACSEC_RXSYSGERR_CNT_PORT7_RXSYS_GERR_CNT_L_OFFSET (0) + #define RTL8373_MACSEC_RXSYSGERR_CNT_PORT7_RXSYS_GERR_CNT_L_MASK (0xFFFF << RTL8373_MACSEC_RXSYSGERR_CNT_PORT7_RXSYS_GERR_CNT_L_OFFSET) + +#define RTL8373_MACSEC_RXSYS_DBG_PORT7_ADDR (0xD9EC) + #define RTL8373_MACSEC_RXSYS_DBG_PORT7_RXSYS_IP2XG_FSM_OFFSET (16) + #define RTL8373_MACSEC_RXSYS_DBG_PORT7_RXSYS_IP2XG_FSM_MASK (0x1F << RTL8373_MACSEC_RXSYS_DBG_PORT7_RXSYS_IP2XG_FSM_OFFSET) + #define RTL8373_MACSEC_RXSYS_DBG_PORT7_RXSYS_IP2WRP_FSM_OFFSET (0) + #define RTL8373_MACSEC_RXSYS_DBG_PORT7_RXSYS_IP2WRP_FSM_MASK (0xF << RTL8373_MACSEC_RXSYS_DBG_PORT7_RXSYS_IP2WRP_FSM_OFFSET) + +#define RTL8373_MACSEC_TXSYS_CFG1_PORT7_ADDR (0xD9F0) + #define RTL8373_MACSEC_TXSYS_CFG1_PORT7_TXSYS_XGMINIFG_OFFSET (16) + #define RTL8373_MACSEC_TXSYS_CFG1_PORT7_TXSYS_XGMINIFG_MASK (0x1F << RTL8373_MACSEC_TXSYS_CFG1_PORT7_TXSYS_XGMINIFG_OFFSET) + #define RTL8373_MACSEC_TXSYS_CFG1_PORT7_TXSYS_MINIFG_OFFSET (8) + #define RTL8373_MACSEC_TXSYS_CFG1_PORT7_TXSYS_MINIFG_MASK (0xF << RTL8373_MACSEC_TXSYS_CFG1_PORT7_TXSYS_MINIFG_OFFSET) + #define RTL8373_MACSEC_TXSYS_CFG1_PORT7_TXSYS_PMBNUM_OFFSET (0) + #define RTL8373_MACSEC_TXSYS_CFG1_PORT7_TXSYS_PMBNUM_MASK (0x7 << RTL8373_MACSEC_TXSYS_CFG1_PORT7_TXSYS_PMBNUM_OFFSET) + +#define RTL8373_MACSEC_TXSYS_PTPCFG_PORT7_ADDR (0xD9F4) + #define RTL8373_MACSEC_TXSYS_PTPCFG_PORT7_TXSYS_OUTERVLAN1_OFFSET (16) + #define RTL8373_MACSEC_TXSYS_PTPCFG_PORT7_TXSYS_OUTERVLAN1_MASK (0xFFFF << RTL8373_MACSEC_TXSYS_PTPCFG_PORT7_TXSYS_OUTERVLAN1_OFFSET) + #define RTL8373_MACSEC_TXSYS_PTPCFG_PORT7_PTP_UDP_EN_OFFSET (13) + #define RTL8373_MACSEC_TXSYS_PTPCFG_PORT7_PTP_UDP_EN_MASK (0x1 << RTL8373_MACSEC_TXSYS_PTPCFG_PORT7_PTP_UDP_EN_OFFSET) + #define RTL8373_MACSEC_TXSYS_PTPCFG_PORT7_PTP_ETH_EN_OFFSET (12) + #define RTL8373_MACSEC_TXSYS_PTPCFG_PORT7_PTP_ETH_EN_MASK (0x1 << RTL8373_MACSEC_TXSYS_PTPCFG_PORT7_PTP_ETH_EN_OFFSET) + #define RTL8373_MACSEC_TXSYS_PTPCFG_PORT7_TXSYS_PTPCRYPT_EN_OFFSET (8) + #define RTL8373_MACSEC_TXSYS_PTPCFG_PORT7_TXSYS_PTPCRYPT_EN_MASK (0x1 << RTL8373_MACSEC_TXSYS_PTPCFG_PORT7_TXSYS_PTPCRYPT_EN_OFFSET) + #define RTL8373_MACSEC_TXSYS_PTPCFG_PORT7_TXSYS_FLOWID_OFFSET (0) + #define RTL8373_MACSEC_TXSYS_PTPCFG_PORT7_TXSYS_FLOWID_MASK (0x3F << RTL8373_MACSEC_TXSYS_PTPCFG_PORT7_TXSYS_FLOWID_OFFSET) + +#define RTL8373_MACSEC_TXSYS_OUTERVLAN2_PORT7_ADDR (0xD9F8) + #define RTL8373_MACSEC_TXSYS_OUTERVLAN2_PORT7_TXSYS_OUTERVLAN3_OFFSET (16) + #define RTL8373_MACSEC_TXSYS_OUTERVLAN2_PORT7_TXSYS_OUTERVLAN3_MASK (0xFFFF << RTL8373_MACSEC_TXSYS_OUTERVLAN2_PORT7_TXSYS_OUTERVLAN3_OFFSET) + #define RTL8373_MACSEC_TXSYS_OUTERVLAN2_PORT7_TXSYS_OUTERVLAN2_OFFSET (0) + #define RTL8373_MACSEC_TXSYS_OUTERVLAN2_PORT7_TXSYS_OUTERVLAN2_MASK (0xFFFF << RTL8373_MACSEC_TXSYS_OUTERVLAN2_PORT7_TXSYS_OUTERVLAN2_OFFSET) + +#define RTL8373_MACSEC_TXSYS_OUTERVLAN4_PORT7_ADDR (0xD9FC) + #define RTL8373_MACSEC_TXSYS_OUTERVLAN4_PORT7_TXSYS_INNERVLAN1_OFFSET (16) + #define RTL8373_MACSEC_TXSYS_OUTERVLAN4_PORT7_TXSYS_INNERVLAN1_MASK (0xFFFF << RTL8373_MACSEC_TXSYS_OUTERVLAN4_PORT7_TXSYS_INNERVLAN1_OFFSET) + #define RTL8373_MACSEC_TXSYS_OUTERVLAN4_PORT7_TXSYS_OUTERVLAN4_OFFSET (0) + #define RTL8373_MACSEC_TXSYS_OUTERVLAN4_PORT7_TXSYS_OUTERVLAN4_MASK (0xFFFF << RTL8373_MACSEC_TXSYS_OUTERVLAN4_PORT7_TXSYS_OUTERVLAN4_OFFSET) + +#define RTL8373_MACSEC_TXSYS_INNERVLAN2_PORT7_ADDR (0xDA00) + #define RTL8373_MACSEC_TXSYS_INNERVLAN2_PORT7_TXSYS_INNERVLAN3_OFFSET (16) + #define RTL8373_MACSEC_TXSYS_INNERVLAN2_PORT7_TXSYS_INNERVLAN3_MASK (0xFFFF << RTL8373_MACSEC_TXSYS_INNERVLAN2_PORT7_TXSYS_INNERVLAN3_OFFSET) + #define RTL8373_MACSEC_TXSYS_INNERVLAN2_PORT7_TXSYS_INNERVLAN2_OFFSET (0) + #define RTL8373_MACSEC_TXSYS_INNERVLAN2_PORT7_TXSYS_INNERVLAN2_MASK (0xFFFF << RTL8373_MACSEC_TXSYS_INNERVLAN2_PORT7_TXSYS_INNERVLAN2_OFFSET) + +#define RTL8373_MACSEC_TXSYS_INNERVLAN4_PORT7_ADDR (0xDA04) + #define RTL8373_MACSEC_TXSYS_INNERVLAN4_PORT7_TXSYS_INNERVLAN5_OFFSET (16) + #define RTL8373_MACSEC_TXSYS_INNERVLAN4_PORT7_TXSYS_INNERVLAN5_MASK (0xFFFF << RTL8373_MACSEC_TXSYS_INNERVLAN4_PORT7_TXSYS_INNERVLAN5_OFFSET) + #define RTL8373_MACSEC_TXSYS_INNERVLAN4_PORT7_TXSYS_INNERVLAN4_OFFSET (0) + #define RTL8373_MACSEC_TXSYS_INNERVLAN4_PORT7_TXSYS_INNERVLAN4_MASK (0xFFFF << RTL8373_MACSEC_TXSYS_INNERVLAN4_PORT7_TXSYS_INNERVLAN4_OFFSET) + +#define RTL8373_MACSEC_TXSYS_INNERVLAN6_PORT7_ADDR (0xDA08) + #define RTL8373_MACSEC_TXSYS_INNERVLAN6_PORT7_TXSYS_INNERVLAN7_OFFSET (16) + #define RTL8373_MACSEC_TXSYS_INNERVLAN6_PORT7_TXSYS_INNERVLAN7_MASK (0xFFFF << RTL8373_MACSEC_TXSYS_INNERVLAN6_PORT7_TXSYS_INNERVLAN7_OFFSET) + #define RTL8373_MACSEC_TXSYS_INNERVLAN6_PORT7_TXSYS_INNERVLAN6_OFFSET (0) + #define RTL8373_MACSEC_TXSYS_INNERVLAN6_PORT7_TXSYS_INNERVLAN6_MASK (0xFFFF << RTL8373_MACSEC_TXSYS_INNERVLAN6_PORT7_TXSYS_INNERVLAN6_OFFSET) + +#define RTL8373_UNUSED_011C_PORT7_ADDR (0xDA0C) + #define RTL8373_UNUSED_011C_PORT7_UNUSED_011C_PORT7_OFFSET (0) + #define RTL8373_UNUSED_011C_PORT7_UNUSED_011C_PORT7_MASK (0xFFFFFFFF << RTL8373_UNUSED_011C_PORT7_UNUSED_011C_PORT7_OFFSET) + +#define RTL8373_UNUSED_0120_PORT7_ADDR (0xDA10) + #define RTL8373_UNUSED_0120_PORT7_UNUSED_0120_PORT7_OFFSET (0) + #define RTL8373_UNUSED_0120_PORT7_UNUSED_0120_PORT7_MASK (0xFFFFFFFF << RTL8373_UNUSED_0120_PORT7_UNUSED_0120_PORT7_OFFSET) + +#define RTL8373_UNUSED_0124_PORT7_ADDR (0xDA14) + #define RTL8373_UNUSED_0124_PORT7_UNUSED_0124_PORT7_OFFSET (0) + #define RTL8373_UNUSED_0124_PORT7_UNUSED_0124_PORT7_MASK (0xFFFFFFFF << RTL8373_UNUSED_0124_PORT7_UNUSED_0124_PORT7_OFFSET) + +#define RTL8373_UNUSED_0128_PORT7_ADDR (0xDA18) + #define RTL8373_UNUSED_0128_PORT7_UNUSED_0128_PORT7_OFFSET (0) + #define RTL8373_UNUSED_0128_PORT7_UNUSED_0128_PORT7_MASK (0xFFFFFFFF << RTL8373_UNUSED_0128_PORT7_UNUSED_0128_PORT7_OFFSET) + +#define RTL8373_UNUSED_012C_PORT7_ADDR (0xDA1C) + #define RTL8373_UNUSED_012C_PORT7_UNUSED_012C_PORT7_OFFSET (0) + #define RTL8373_UNUSED_012C_PORT7_UNUSED_012C_PORT7_MASK (0xFFFFFFFF << RTL8373_UNUSED_012C_PORT7_UNUSED_012C_PORT7_OFFSET) + +#define RTL8373_UNUSED_0130_PORT7_ADDR (0xDA20) + #define RTL8373_UNUSED_0130_PORT7_UNUSED_0130_PORT7_OFFSET (0) + #define RTL8373_UNUSED_0130_PORT7_UNUSED_0130_PORT7_MASK (0xFFFFFFFF << RTL8373_UNUSED_0130_PORT7_UNUSED_0130_PORT7_OFFSET) + +#define RTL8373_UNUSED_0134_PORT7_ADDR (0xDA24) + #define RTL8373_UNUSED_0134_PORT7_UNUSED_0134_PORT7_OFFSET (0) + #define RTL8373_UNUSED_0134_PORT7_UNUSED_0134_PORT7_MASK (0xFFFFFFFF << RTL8373_UNUSED_0134_PORT7_UNUSED_0134_PORT7_OFFSET) + +#define RTL8373_UNUSED_0138_PORT7_ADDR (0xDA28) + #define RTL8373_UNUSED_0138_PORT7_UNUSED_0138_PORT7_OFFSET (0) + #define RTL8373_UNUSED_0138_PORT7_UNUSED_0138_PORT7_MASK (0xFFFFFFFF << RTL8373_UNUSED_0138_PORT7_UNUSED_0138_PORT7_OFFSET) + +#define RTL8373_UNUSED_013C_PORT7_ADDR (0xDA2C) + #define RTL8373_UNUSED_013C_PORT7_UNUSED_013C_PORT7_OFFSET (0) + #define RTL8373_UNUSED_013C_PORT7_UNUSED_013C_PORT7_MASK (0xFFFFFFFF << RTL8373_UNUSED_013C_PORT7_UNUSED_013C_PORT7_OFFSET) + +#define RTL8373_MACSEC_TXLINE_CFG1_PORT7_ADDR (0xDA30) + #define RTL8373_MACSEC_TXLINE_CFG1_PORT7_TXLINE_WAIT_T_OFFSET (16) + #define RTL8373_MACSEC_TXLINE_CFG1_PORT7_TXLINE_WAIT_T_MASK (0xFF << RTL8373_MACSEC_TXLINE_CFG1_PORT7_TXLINE_WAIT_T_OFFSET) + #define RTL8373_MACSEC_TXLINE_CFG1_PORT7_TXLINE_MINIFG_OFFSET (8) + #define RTL8373_MACSEC_TXLINE_CFG1_PORT7_TXLINE_MINIFG_MASK (0xFF << RTL8373_MACSEC_TXLINE_CFG1_PORT7_TXLINE_MINIFG_OFFSET) + #define RTL8373_MACSEC_TXLINE_CFG1_PORT7_TXLINE_PMBNUM_OFFSET (0) + #define RTL8373_MACSEC_TXLINE_CFG1_PORT7_TXLINE_PMBNUM_MASK (0xF << RTL8373_MACSEC_TXLINE_CFG1_PORT7_TXLINE_PMBNUM_OFFSET) + +#define RTL8373_MACSEC_TXLINE_CFG3_PORT7_ADDR (0xDA34) + #define RTL8373_MACSEC_TXLINE_CFG3_PORT7_TXLINE_FIFO_TSHD_OFFSET (16) + #define RTL8373_MACSEC_TXLINE_CFG3_PORT7_TXLINE_FIFO_TSHD_MASK (0xFF << RTL8373_MACSEC_TXLINE_CFG3_PORT7_TXLINE_FIFO_TSHD_OFFSET) + #define RTL8373_MACSEC_TXLINE_CFG3_PORT7_TXLINE_PAD_VLAN_EN_OFFSET (14) + #define RTL8373_MACSEC_TXLINE_CFG3_PORT7_TXLINE_PAD_VLAN_EN_MASK (0x1 << RTL8373_MACSEC_TXLINE_CFG3_PORT7_TXLINE_PAD_VLAN_EN_OFFSET) + #define RTL8373_MACSEC_TXLINE_CFG3_PORT7_TXLINE_PAD_MACSEC_EN_OFFSET (13) + #define RTL8373_MACSEC_TXLINE_CFG3_PORT7_TXLINE_PAD_MACSEC_EN_MASK (0x1 << RTL8373_MACSEC_TXLINE_CFG3_PORT7_TXLINE_PAD_MACSEC_EN_OFFSET) + #define RTL8373_MACSEC_TXLINE_CFG3_PORT7_TXLINE_PAD_EN_OFFSET (12) + #define RTL8373_MACSEC_TXLINE_CFG3_PORT7_TXLINE_PAD_EN_MASK (0x1 << RTL8373_MACSEC_TXLINE_CFG3_PORT7_TXLINE_PAD_EN_OFFSET) + #define RTL8373_MACSEC_TXLINE_CFG3_PORT7_TXLINE_PKTERR_INVRSCRC_EN_OFFSET (8) + #define RTL8373_MACSEC_TXLINE_CFG3_PORT7_TXLINE_PKTERR_INVRSCRC_EN_MASK (0x1 << RTL8373_MACSEC_TXLINE_CFG3_PORT7_TXLINE_PKTERR_INVRSCRC_EN_OFFSET) + #define RTL8373_MACSEC_TXLINE_CFG3_PORT7_TXLINE_GMIIER_INVRSCRC_EN_OFFSET (5) + #define RTL8373_MACSEC_TXLINE_CFG3_PORT7_TXLINE_GMIIER_INVRSCRC_EN_MASK (0x1 << RTL8373_MACSEC_TXLINE_CFG3_PORT7_TXLINE_GMIIER_INVRSCRC_EN_OFFSET) + #define RTL8373_MACSEC_TXLINE_CFG3_PORT7_TXLINE_CRCERR_INVRSCRC_EN_OFFSET (4) + #define RTL8373_MACSEC_TXLINE_CFG3_PORT7_TXLINE_CRCERR_INVRSCRC_EN_MASK (0x1 << RTL8373_MACSEC_TXLINE_CFG3_PORT7_TXLINE_CRCERR_INVRSCRC_EN_OFFSET) + #define RTL8373_MACSEC_TXLINE_CFG3_PORT7_TXLINE_CLASSDROP_EN_OFFSET (0) + #define RTL8373_MACSEC_TXLINE_CFG3_PORT7_TXLINE_CLASSDROP_EN_MASK (0x1 << RTL8373_MACSEC_TXLINE_CFG3_PORT7_TXLINE_CLASSDROP_EN_OFFSET) + +#define RTL8373_MACSEC_TXLINE_CFG5_PORT7_ADDR (0xDA38) + #define RTL8373_MACSEC_TXLINE_CFG5_PORT7_TXLINE_AVG_IPG_OFFSET (16) + #define RTL8373_MACSEC_TXLINE_CFG5_PORT7_TXLINE_AVG_IPG_MASK (0xF << RTL8373_MACSEC_TXLINE_CFG5_PORT7_TXLINE_AVG_IPG_OFFSET) + #define RTL8373_MACSEC_TXLINE_CFG5_PORT7_TXLIEN_LPIEXIT_T_OFFSET (0) + #define RTL8373_MACSEC_TXLINE_CFG5_PORT7_TXLIEN_LPIEXIT_T_MASK (0x7FFF << RTL8373_MACSEC_TXLINE_CFG5_PORT7_TXLIEN_LPIEXIT_T_OFFSET) + +#define RTL8373_UNUSED_014C_PORT7_ADDR (0xDA3C) + #define RTL8373_UNUSED_014C_PORT7_UNUSED_014C_PORT7_OFFSET (0) + #define RTL8373_UNUSED_014C_PORT7_UNUSED_014C_PORT7_MASK (0xFFFFFFFF << RTL8373_UNUSED_014C_PORT7_UNUSED_014C_PORT7_OFFSET) + +#define RTL8373_UNUSED_0150_PORT7_ADDR (0xDA40) + #define RTL8373_UNUSED_0150_PORT7_UNUSED_0150_PORT7_OFFSET (0) + #define RTL8373_UNUSED_0150_PORT7_UNUSED_0150_PORT7_MASK (0xFFFFFFFF << RTL8373_UNUSED_0150_PORT7_UNUSED_0150_PORT7_OFFSET) + +#define RTL8373_UNUSED_0154_PORT7_ADDR (0xDA44) + #define RTL8373_UNUSED_0154_PORT7_UNUSED_0154_PORT7_OFFSET (0) + #define RTL8373_UNUSED_0154_PORT7_UNUSED_0154_PORT7_MASK (0xFFFFFFFF << RTL8373_UNUSED_0154_PORT7_UNUSED_0154_PORT7_OFFSET) + +#define RTL8373_UNUSED_0158_PORT7_ADDR (0xDA48) + #define RTL8373_UNUSED_0158_PORT7_UNUSED_0158_PORT7_OFFSET (0) + #define RTL8373_UNUSED_0158_PORT7_UNUSED_0158_PORT7_MASK (0xFFFFFFFF << RTL8373_UNUSED_0158_PORT7_UNUSED_0158_PORT7_OFFSET) + +#define RTL8373_UNUSED_015C_PORT7_ADDR (0xDA4C) + #define RTL8373_UNUSED_015C_PORT7_UNUSED_015C_PORT7_OFFSET (0) + #define RTL8373_UNUSED_015C_PORT7_UNUSED_015C_PORT7_MASK (0xFFFFFFFF << RTL8373_UNUSED_015C_PORT7_UNUSED_015C_PORT7_OFFSET) + +#define RTL8373_UNUSED_0160_PORT7_ADDR (0xDA50) + #define RTL8373_UNUSED_0160_PORT7_UNUSED_0160_PORT7_OFFSET (0) + #define RTL8373_UNUSED_0160_PORT7_UNUSED_0160_PORT7_MASK (0xFFFFFFFF << RTL8373_UNUSED_0160_PORT7_UNUSED_0160_PORT7_OFFSET) + +#define RTL8373_UNUSED_0164_PORT7_ADDR (0xDA54) + #define RTL8373_UNUSED_0164_PORT7_UNUSED_0164_PORT7_OFFSET (0) + #define RTL8373_UNUSED_0164_PORT7_UNUSED_0164_PORT7_MASK (0xFFFFFFFF << RTL8373_UNUSED_0164_PORT7_UNUSED_0164_PORT7_OFFSET) + +#define RTL8373_UNUSED_0168_PORT7_ADDR (0xDA58) + #define RTL8373_UNUSED_0168_PORT7_UNUSED_0168_PORT7_OFFSET (0) + #define RTL8373_UNUSED_0168_PORT7_UNUSED_0168_PORT7_MASK (0xFFFFFFFF << RTL8373_UNUSED_0168_PORT7_UNUSED_0168_PORT7_OFFSET) + +#define RTL8373_UNUSED_016C_PORT7_ADDR (0xDA5C) + #define RTL8373_UNUSED_016C_PORT7_UNUSED_016C_PORT7_OFFSET (0) + #define RTL8373_UNUSED_016C_PORT7_UNUSED_016C_PORT7_MASK (0xFFFFFFFF << RTL8373_UNUSED_016C_PORT7_UNUSED_016C_PORT7_OFFSET) + +#define RTL8373_UNUSED_0170_PORT7_ADDR (0xDA60) + #define RTL8373_UNUSED_0170_PORT7_UNUSED_0170_PORT7_OFFSET (0) + #define RTL8373_UNUSED_0170_PORT7_UNUSED_0170_PORT7_MASK (0xFFFFFFFF << RTL8373_UNUSED_0170_PORT7_UNUSED_0170_PORT7_OFFSET) + +#define RTL8373_UNUSED_0174_PORT7_ADDR (0xDA64) + #define RTL8373_UNUSED_0174_PORT7_UNUSED_0174_PORT7_OFFSET (0) + #define RTL8373_UNUSED_0174_PORT7_UNUSED_0174_PORT7_MASK (0xFFFFFFFF << RTL8373_UNUSED_0174_PORT7_UNUSED_0174_PORT7_OFFSET) + +#define RTL8373_UNUSED_0178_PORT7_ADDR (0xDA68) + #define RTL8373_UNUSED_0178_PORT7_UNUSED_0178_PORT7_OFFSET (0) + #define RTL8373_UNUSED_0178_PORT7_UNUSED_0178_PORT7_MASK (0xFFFFFFFF << RTL8373_UNUSED_0178_PORT7_UNUSED_0178_PORT7_OFFSET) + +#define RTL8373_UNUSED_017C_PORT7_ADDR (0xDA6C) + #define RTL8373_UNUSED_017C_PORT7_UNUSED_017C_PORT7_OFFSET (0) + #define RTL8373_UNUSED_017C_PORT7_UNUSED_017C_PORT7_MASK (0xFFFFFFFF << RTL8373_UNUSED_017C_PORT7_UNUSED_017C_PORT7_OFFSET) + +#define RTL8373_MACSEC_RXLINE_CFG1_PORT7_ADDR (0xDA70) + #define RTL8373_MACSEC_RXLINE_CFG1_PORT7_RXLINE_XGMINIFG_OFFSET (16) + #define RTL8373_MACSEC_RXLINE_CFG1_PORT7_RXLINE_XGMINIFG_MASK (0x1F << RTL8373_MACSEC_RXLINE_CFG1_PORT7_RXLINE_XGMINIFG_OFFSET) + #define RTL8373_MACSEC_RXLINE_CFG1_PORT7_RXLINE_MINIPG_OFFSET (8) + #define RTL8373_MACSEC_RXLINE_CFG1_PORT7_RXLINE_MINIPG_MASK (0xF << RTL8373_MACSEC_RXLINE_CFG1_PORT7_RXLINE_MINIPG_OFFSET) + #define RTL8373_MACSEC_RXLINE_CFG1_PORT7_RXLINE_PMBNUM_OFFSET (0) + #define RTL8373_MACSEC_RXLINE_CFG1_PORT7_RXLINE_PMBNUM_MASK (0x7 << RTL8373_MACSEC_RXLINE_CFG1_PORT7_RXLINE_PMBNUM_OFFSET) + +#define RTL8373_UNUSED_0184_PORT7_ADDR (0xDA74) + #define RTL8373_UNUSED_0184_PORT7_UNUSED_0184_PORT7_OFFSET (0) + #define RTL8373_UNUSED_0184_PORT7_UNUSED_0184_PORT7_MASK (0xFFFFFFFF << RTL8373_UNUSED_0184_PORT7_UNUSED_0184_PORT7_OFFSET) + +#define RTL8373_UNUSED_0188_PORT7_ADDR (0xDA78) + #define RTL8373_UNUSED_0188_PORT7_UNUSED_0188_PORT7_OFFSET (0) + #define RTL8373_UNUSED_0188_PORT7_UNUSED_0188_PORT7_MASK (0xFFFFFFFF << RTL8373_UNUSED_0188_PORT7_UNUSED_0188_PORT7_OFFSET) + +#define RTL8373_UNUSED_018C_PORT7_ADDR (0xDA7C) + #define RTL8373_UNUSED_018C_PORT7_UNUSED_018C_PORT7_OFFSET (0) + #define RTL8373_UNUSED_018C_PORT7_UNUSED_018C_PORT7_MASK (0xFFFFFFFF << RTL8373_UNUSED_018C_PORT7_UNUSED_018C_PORT7_OFFSET) + +#define RTL8373_UNUSED_0190_PORT7_ADDR (0xDA80) + #define RTL8373_UNUSED_0190_PORT7_UNUSED_0190_PORT7_OFFSET (0) + #define RTL8373_UNUSED_0190_PORT7_UNUSED_0190_PORT7_MASK (0xFFFFFFFF << RTL8373_UNUSED_0190_PORT7_UNUSED_0190_PORT7_OFFSET) + +#define RTL8373_UNUSED_0194_PORT7_ADDR (0xDA84) + #define RTL8373_UNUSED_0194_PORT7_UNUSED_0194_PORT7_OFFSET (0) + #define RTL8373_UNUSED_0194_PORT7_UNUSED_0194_PORT7_MASK (0xFFFFFFFF << RTL8373_UNUSED_0194_PORT7_UNUSED_0194_PORT7_OFFSET) + +#define RTL8373_UNUSED_0198_PORT7_ADDR (0xDA88) + #define RTL8373_UNUSED_0198_PORT7_UNUSED_0198_PORT7_OFFSET (0) + #define RTL8373_UNUSED_0198_PORT7_UNUSED_0198_PORT7_MASK (0xFFFFFFFF << RTL8373_UNUSED_0198_PORT7_UNUSED_0198_PORT7_OFFSET) + +#define RTL8373_UNUSED_019C_PORT7_ADDR (0xDA8C) + #define RTL8373_UNUSED_019C_PORT7_UNUSED_019C_PORT7_OFFSET (0) + #define RTL8373_UNUSED_019C_PORT7_UNUSED_019C_PORT7_MASK (0xFFFFFFFF << RTL8373_UNUSED_019C_PORT7_UNUSED_019C_PORT7_OFFSET) + +#define RTL8373_UNUSED_01A0_PORT7_ADDR (0xDA90) + #define RTL8373_UNUSED_01A0_PORT7_UNUSED_01A0_PORT7_OFFSET (0) + #define RTL8373_UNUSED_01A0_PORT7_UNUSED_01A0_PORT7_MASK (0xFFFFFFFF << RTL8373_UNUSED_01A0_PORT7_UNUSED_01A0_PORT7_OFFSET) + +#define RTL8373_UNUSED_01A4_PORT7_ADDR (0xDA94) + #define RTL8373_UNUSED_01A4_PORT7_UNUSED_01A4_PORT7_OFFSET (0) + #define RTL8373_UNUSED_01A4_PORT7_UNUSED_01A4_PORT7_MASK (0xFFFFFFFF << RTL8373_UNUSED_01A4_PORT7_UNUSED_01A4_PORT7_OFFSET) + +#define RTL8373_UNUSED_01A8_PORT7_ADDR (0xDA98) + #define RTL8373_UNUSED_01A8_PORT7_UNUSED_01A8_PORT7_OFFSET (0) + #define RTL8373_UNUSED_01A8_PORT7_UNUSED_01A8_PORT7_MASK (0xFFFFFFFF << RTL8373_UNUSED_01A8_PORT7_UNUSED_01A8_PORT7_OFFSET) + +#define RTL8373_UNUSED_01AC_PORT7_ADDR (0xDA9C) + #define RTL8373_UNUSED_01AC_PORT7_UNUSED_01AC_PORT7_OFFSET (0) + #define RTL8373_UNUSED_01AC_PORT7_UNUSED_01AC_PORT7_MASK (0xFFFFFFFF << RTL8373_UNUSED_01AC_PORT7_UNUSED_01AC_PORT7_OFFSET) + +#define RTL8373_UNUSED_01B0_PORT7_ADDR (0xDAA0) + #define RTL8373_UNUSED_01B0_PORT7_UNUSED_01B0_PORT7_OFFSET (0) + #define RTL8373_UNUSED_01B0_PORT7_UNUSED_01B0_PORT7_MASK (0xFFFFFFFF << RTL8373_UNUSED_01B0_PORT7_UNUSED_01B0_PORT7_OFFSET) + +#define RTL8373_UNUSED_01B4_PORT7_ADDR (0xDAA4) + #define RTL8373_UNUSED_01B4_PORT7_UNUSED_01B4_PORT7_OFFSET (0) + #define RTL8373_UNUSED_01B4_PORT7_UNUSED_01B4_PORT7_MASK (0xFFFFFFFF << RTL8373_UNUSED_01B4_PORT7_UNUSED_01B4_PORT7_OFFSET) + +#define RTL8373_UNUSED_01B8_PORT7_ADDR (0xDAA8) + #define RTL8373_UNUSED_01B8_PORT7_UNUSED_01B8_PORT7_OFFSET (0) + #define RTL8373_UNUSED_01B8_PORT7_UNUSED_01B8_PORT7_MASK (0xFFFFFFFF << RTL8373_UNUSED_01B8_PORT7_UNUSED_01B8_PORT7_OFFSET) + +#define RTL8373_UNUSED_01BC_PORT7_ADDR (0xDAAC) + #define RTL8373_UNUSED_01BC_PORT7_UNUSED_01BC_PORT7_OFFSET (0) + #define RTL8373_UNUSED_01BC_PORT7_UNUSED_01BC_PORT7_MASK (0xFFFFFFFF << RTL8373_UNUSED_01BC_PORT7_UNUSED_01BC_PORT7_OFFSET) + +#define RTL8373_MACSEC_RXSYS_CFG1_PORT7_ADDR (0xDAB0) + #define RTL8373_MACSEC_RXSYS_CFG1_PORT7_RXSYS_WAIT_T_OFFSET (16) + #define RTL8373_MACSEC_RXSYS_CFG1_PORT7_RXSYS_WAIT_T_MASK (0xFF << RTL8373_MACSEC_RXSYS_CFG1_PORT7_RXSYS_WAIT_T_OFFSET) + #define RTL8373_MACSEC_RXSYS_CFG1_PORT7_RXSYS_MINIPG_OFFSET (8) + #define RTL8373_MACSEC_RXSYS_CFG1_PORT7_RXSYS_MINIPG_MASK (0xFF << RTL8373_MACSEC_RXSYS_CFG1_PORT7_RXSYS_MINIPG_OFFSET) + #define RTL8373_MACSEC_RXSYS_CFG1_PORT7_RXSYS_PMBNUM_OFFSET (0) + #define RTL8373_MACSEC_RXSYS_CFG1_PORT7_RXSYS_PMBNUM_MASK (0xF << RTL8373_MACSEC_RXSYS_CFG1_PORT7_RXSYS_PMBNUM_OFFSET) + +#define RTL8373_MACSEC_RXSYS_CFG3_PORT7_ADDR (0xDAB4) + #define RTL8373_MACSEC_RXSYS_CFG3_PORT7_RXSYS_OUTERVLAN1_OFFSET (16) + #define RTL8373_MACSEC_RXSYS_CFG3_PORT7_RXSYS_OUTERVLAN1_MASK (0xFFFF << RTL8373_MACSEC_RXSYS_CFG3_PORT7_RXSYS_OUTERVLAN1_OFFSET) + #define RTL8373_MACSEC_RXSYS_CFG3_PORT7_RXSYS_PAD_VLAN_EN_OFFSET (14) + #define RTL8373_MACSEC_RXSYS_CFG3_PORT7_RXSYS_PAD_VLAN_EN_MASK (0x1 << RTL8373_MACSEC_RXSYS_CFG3_PORT7_RXSYS_PAD_VLAN_EN_OFFSET) + #define RTL8373_MACSEC_RXSYS_CFG3_PORT7_RXSYS_PAD_LINESRT_EN_OFFSET (13) + #define RTL8373_MACSEC_RXSYS_CFG3_PORT7_RXSYS_PAD_LINESRT_EN_MASK (0x1 << RTL8373_MACSEC_RXSYS_CFG3_PORT7_RXSYS_PAD_LINESRT_EN_OFFSET) + #define RTL8373_MACSEC_RXSYS_CFG3_PORT7_RXSYS_PAD_DECRYPTSRT_EN_OFFSET (12) + #define RTL8373_MACSEC_RXSYS_CFG3_PORT7_RXSYS_PAD_DECRYPTSRT_EN_MASK (0x1 << RTL8373_MACSEC_RXSYS_CFG3_PORT7_RXSYS_PAD_DECRYPTSRT_EN_OFFSET) + #define RTL8373_MACSEC_RXSYS_CFG3_PORT7_RXSYS_PKTERR_INVRSCRC_EN_OFFSET (8) + #define RTL8373_MACSEC_RXSYS_CFG3_PORT7_RXSYS_PKTERR_INVRSCRC_EN_MASK (0x1 << RTL8373_MACSEC_RXSYS_CFG3_PORT7_RXSYS_PKTERR_INVRSCRC_EN_OFFSET) + #define RTL8373_MACSEC_RXSYS_CFG3_PORT7_RXSYS_GMIIER_INVRSCRC_EN_OFFSET (5) + #define RTL8373_MACSEC_RXSYS_CFG3_PORT7_RXSYS_GMIIER_INVRSCRC_EN_MASK (0x1 << RTL8373_MACSEC_RXSYS_CFG3_PORT7_RXSYS_GMIIER_INVRSCRC_EN_OFFSET) + #define RTL8373_MACSEC_RXSYS_CFG3_PORT7_RXSYS_CRCERR_INVRSCRC_EN_OFFSET (4) + #define RTL8373_MACSEC_RXSYS_CFG3_PORT7_RXSYS_CRCERR_INVRSCRC_EN_MASK (0x1 << RTL8373_MACSEC_RXSYS_CFG3_PORT7_RXSYS_CRCERR_INVRSCRC_EN_OFFSET) + #define RTL8373_MACSEC_RXSYS_CFG3_PORT7_RXSYS_CLASSDROP_EN_OFFSET (0) + #define RTL8373_MACSEC_RXSYS_CFG3_PORT7_RXSYS_CLASSDROP_EN_MASK (0x1 << RTL8373_MACSEC_RXSYS_CFG3_PORT7_RXSYS_CLASSDROP_EN_OFFSET) + +#define RTL8373_MACSEC_RXSYS_OUTERVLAN2_PORT7_ADDR (0xDAB8) + #define RTL8373_MACSEC_RXSYS_OUTERVLAN2_PORT7_RXSYS_OUTERVLAN3_OFFSET (16) + #define RTL8373_MACSEC_RXSYS_OUTERVLAN2_PORT7_RXSYS_OUTERVLAN3_MASK (0xFFFF << RTL8373_MACSEC_RXSYS_OUTERVLAN2_PORT7_RXSYS_OUTERVLAN3_OFFSET) + #define RTL8373_MACSEC_RXSYS_OUTERVLAN2_PORT7_RXSYS_OUTERVLAN2_OFFSET (0) + #define RTL8373_MACSEC_RXSYS_OUTERVLAN2_PORT7_RXSYS_OUTERVLAN2_MASK (0xFFFF << RTL8373_MACSEC_RXSYS_OUTERVLAN2_PORT7_RXSYS_OUTERVLAN2_OFFSET) + +#define RTL8373_MACSEC_RXSYS_OUTERVLAN4_PORT7_ADDR (0xDABC) + #define RTL8373_MACSEC_RXSYS_OUTERVLAN4_PORT7_RXSYS_INNERVLAN1_OFFSET (16) + #define RTL8373_MACSEC_RXSYS_OUTERVLAN4_PORT7_RXSYS_INNERVLAN1_MASK (0xFFFF << RTL8373_MACSEC_RXSYS_OUTERVLAN4_PORT7_RXSYS_INNERVLAN1_OFFSET) + #define RTL8373_MACSEC_RXSYS_OUTERVLAN4_PORT7_RXSYS_OUTERVLAN4_OFFSET (0) + #define RTL8373_MACSEC_RXSYS_OUTERVLAN4_PORT7_RXSYS_OUTERVLAN4_MASK (0xFFFF << RTL8373_MACSEC_RXSYS_OUTERVLAN4_PORT7_RXSYS_OUTERVLAN4_OFFSET) + +#define RTL8373_MACSEC_RXSYS_INNERVLAN2_PORT7_ADDR (0xDAC0) + #define RTL8373_MACSEC_RXSYS_INNERVLAN2_PORT7_RXSYS_INNERVLAN3_OFFSET (16) + #define RTL8373_MACSEC_RXSYS_INNERVLAN2_PORT7_RXSYS_INNERVLAN3_MASK (0xFFFF << RTL8373_MACSEC_RXSYS_INNERVLAN2_PORT7_RXSYS_INNERVLAN3_OFFSET) + #define RTL8373_MACSEC_RXSYS_INNERVLAN2_PORT7_RXSYS_INNERVLAN2_OFFSET (0) + #define RTL8373_MACSEC_RXSYS_INNERVLAN2_PORT7_RXSYS_INNERVLAN2_MASK (0xFFFF << RTL8373_MACSEC_RXSYS_INNERVLAN2_PORT7_RXSYS_INNERVLAN2_OFFSET) + +#define RTL8373_MACSEC_RXSYS_INNERVLAN4_PORT7_ADDR (0xDAC4) + #define RTL8373_MACSEC_RXSYS_INNERVLAN4_PORT7_RXSYS_INNERVLAN5_OFFSET (16) + #define RTL8373_MACSEC_RXSYS_INNERVLAN4_PORT7_RXSYS_INNERVLAN5_MASK (0xFFFF << RTL8373_MACSEC_RXSYS_INNERVLAN4_PORT7_RXSYS_INNERVLAN5_OFFSET) + #define RTL8373_MACSEC_RXSYS_INNERVLAN4_PORT7_RXSYS_INNERVLAN4_OFFSET (0) + #define RTL8373_MACSEC_RXSYS_INNERVLAN4_PORT7_RXSYS_INNERVLAN4_MASK (0xFFFF << RTL8373_MACSEC_RXSYS_INNERVLAN4_PORT7_RXSYS_INNERVLAN4_OFFSET) + +#define RTL8373_MACSEC_RXSYS_INNERVLAN6_PORT7_ADDR (0xDAC8) + #define RTL8373_MACSEC_RXSYS_INNERVLAN6_PORT7_RXSYS_INNERVLAN7_OFFSET (16) + #define RTL8373_MACSEC_RXSYS_INNERVLAN6_PORT7_RXSYS_INNERVLAN7_MASK (0xFFFF << RTL8373_MACSEC_RXSYS_INNERVLAN6_PORT7_RXSYS_INNERVLAN7_OFFSET) + #define RTL8373_MACSEC_RXSYS_INNERVLAN6_PORT7_RXSYS_INNERVLAN6_OFFSET (0) + #define RTL8373_MACSEC_RXSYS_INNERVLAN6_PORT7_RXSYS_INNERVLAN6_MASK (0xFFFF << RTL8373_MACSEC_RXSYS_INNERVLAN6_PORT7_RXSYS_INNERVLAN6_OFFSET) + +#define RTL8373_MACSEC_RXSYS_CFG4_PORT7_ADDR (0xDACC) + #define RTL8373_MACSEC_RXSYS_CFG4_PORT7_RXSYS_LPIEXIT_T_OFFSET (16) + #define RTL8373_MACSEC_RXSYS_CFG4_PORT7_RXSYS_LPIEXIT_T_MASK (0x7FFF << RTL8373_MACSEC_RXSYS_CFG4_PORT7_RXSYS_LPIEXIT_T_OFFSET) + #define RTL8373_MACSEC_RXSYS_CFG4_PORT7_RXSYS_FIFO_FTUNE_OFFSET (8) + #define RTL8373_MACSEC_RXSYS_CFG4_PORT7_RXSYS_FIFO_FTUNE_MASK (0xFF << RTL8373_MACSEC_RXSYS_CFG4_PORT7_RXSYS_FIFO_FTUNE_OFFSET) + #define RTL8373_MACSEC_RXSYS_CFG4_PORT7_RXSYS_FIFO_TSHD_OFFSET (0) + #define RTL8373_MACSEC_RXSYS_CFG4_PORT7_RXSYS_FIFO_TSHD_MASK (0xFF << RTL8373_MACSEC_RXSYS_CFG4_PORT7_RXSYS_FIFO_TSHD_OFFSET) + +#define RTL8373_MACSEC_RXSYS_CFG6_PORT7_ADDR (0xDAD0) + #define RTL8373_MACSEC_RXSYS_CFG6_PORT7_RXSYS_AVG_IPG_OFFSET (0) + #define RTL8373_MACSEC_RXSYS_CFG6_PORT7_RXSYS_AVG_IPG_MASK (0xF << RTL8373_MACSEC_RXSYS_CFG6_PORT7_RXSYS_AVG_IPG_OFFSET) + +/* + * Feature: Power Saving + */ +#define RTL8373_GATING_CLOCK0_ADDR (0x5FEC) + #define RTL8373_GATING_CLOCK0_LNKDN_CLK_GATE_FLAG_OFFSET (15) + #define RTL8373_GATING_CLOCK0_LNKDN_CLK_GATE_FLAG_MASK (0x1 << RTL8373_GATING_CLOCK0_LNKDN_CLK_GATE_FLAG_OFFSET) + #define RTL8373_GATING_CLOCK0_ALLPORT_MASK_OFFSET (5) + #define RTL8373_GATING_CLOCK0_ALLPORT_MASK_MASK (0x3FF << RTL8373_GATING_CLOCK0_ALLPORT_MASK_OFFSET) + #define RTL8373_GATING_CLOCK0_LINKDOWN_TO_UPS_OFFSET (0) + #define RTL8373_GATING_CLOCK0_LINKDOWN_TO_UPS_MASK (0x1F << RTL8373_GATING_CLOCK0_LINKDOWN_TO_UPS_OFFSET) + +#define RTL8373_GATING_CLOCK1_ADDR (0x5FF0) + #define RTL8373_GATING_CLOCK1_SLOW_DOWN_PLL_EN_OFFSET (12) + #define RTL8373_GATING_CLOCK1_SLOW_DOWN_PLL_EN_MASK (0x1 << RTL8373_GATING_CLOCK1_SLOW_DOWN_PLL_EN_OFFSET) + #define RTL8373_GATING_CLOCK1_SLOW_CLK_TG1_RATE_OFFSET (8) + #define RTL8373_GATING_CLOCK1_SLOW_CLK_TG1_RATE_MASK (0xF << RTL8373_GATING_CLOCK1_SLOW_CLK_TG1_RATE_OFFSET) + #define RTL8373_GATING_CLOCK1_MAC_GATCLK_EN_OFFSET (5) + #define RTL8373_GATING_CLOCK1_MAC_GATCLK_EN_MASK (0x1 << RTL8373_GATING_CLOCK1_MAC_GATCLK_EN_OFFSET) + #define RTL8373_GATING_CLOCK1_ALE_GATCLK_EN_OFFSET (4) + #define RTL8373_GATING_CLOCK1_ALE_GATCLK_EN_MASK (0x1 << RTL8373_GATING_CLOCK1_ALE_GATCLK_EN_OFFSET) + #define RTL8373_GATING_CLOCK1_PKT_ENCAP_GATCLK_EN_OFFSET (3) + #define RTL8373_GATING_CLOCK1_PKT_ENCAP_GATCLK_EN_MASK (0x1 << RTL8373_GATING_CLOCK1_PKT_ENCAP_GATCLK_EN_OFFSET) + #define RTL8373_GATING_CLOCK1_PKT_PRS_GATCLK_EN_OFFSET (2) + #define RTL8373_GATING_CLOCK1_PKT_PRS_GATCLK_EN_MASK (0x1 << RTL8373_GATING_CLOCK1_PKT_PRS_GATCLK_EN_OFFSET) + #define RTL8373_GATING_CLOCK1_EGR_CTRL_GATCLK_EN_OFFSET (1) + #define RTL8373_GATING_CLOCK1_EGR_CTRL_GATCLK_EN_MASK (0x1 << RTL8373_GATING_CLOCK1_EGR_CTRL_GATCLK_EN_OFFSET) + #define RTL8373_GATING_CLOCK1_IGR_CTRL_GATCLK_EN_OFFSET (0) + #define RTL8373_GATING_CLOCK1_IGR_CTRL_GATCLK_EN_MASK (0x1 << RTL8373_GATING_CLOCK1_IGR_CTRL_GATCLK_EN_OFFSET) + +#define RTL8373_EEE_TX_Q_CTRL_ADDR (0x4440) + #define RTL8373_EEE_TX_Q_CTRL_LOW_Q_THR_OFFSET (8) + #define RTL8373_EEE_TX_Q_CTRL_LOW_Q_THR_MASK (0xFFF << RTL8373_EEE_TX_Q_CTRL_LOW_Q_THR_OFFSET) + #define RTL8373_EEE_TX_Q_CTRL_HIGH_Q_OFFSET (0) + #define RTL8373_EEE_TX_Q_CTRL_HIGH_Q_MASK (0xFF << RTL8373_EEE_TX_Q_CTRL_HIGH_Q_OFFSET) + +#define RTL8373_EEE_TX_MINIFG_CTRL0_ADDR (0x5FF4) + #define RTL8373_EEE_TX_MINIFG_CTRL0_TX_LPI_MINIPG_GELITE_OFFSET (16) + #define RTL8373_EEE_TX_MINIFG_CTRL0_TX_LPI_MINIPG_GELITE_MASK (0xFFFF << RTL8373_EEE_TX_MINIFG_CTRL0_TX_LPI_MINIPG_GELITE_OFFSET) + #define RTL8373_EEE_TX_MINIFG_CTRL0_TX_LPI_MINIPG_FE_OFFSET (0) + #define RTL8373_EEE_TX_MINIFG_CTRL0_TX_LPI_MINIPG_FE_MASK (0xFFFF << RTL8373_EEE_TX_MINIFG_CTRL0_TX_LPI_MINIPG_FE_OFFSET) + +#define RTL8373_EEE_TX_MINIFG_CTRL1_ADDR (0x5FF8) + #define RTL8373_EEE_TX_MINIFG_CTRL1_TX_LPI_MINIPG_2P5GLITE_OFFSET (16) + #define RTL8373_EEE_TX_MINIFG_CTRL1_TX_LPI_MINIPG_2P5GLITE_MASK (0xFFFF << RTL8373_EEE_TX_MINIFG_CTRL1_TX_LPI_MINIPG_2P5GLITE_OFFSET) + #define RTL8373_EEE_TX_MINIFG_CTRL1_TX_LPI_MINIPG_GE_OFFSET (0) + #define RTL8373_EEE_TX_MINIFG_CTRL1_TX_LPI_MINIPG_GE_MASK (0xFFFF << RTL8373_EEE_TX_MINIFG_CTRL1_TX_LPI_MINIPG_GE_OFFSET) + +#define RTL8373_EEE_TX_MINIFG_CTRL2_ADDR (0x5FFC) + #define RTL8373_EEE_TX_MINIFG_CTRL2_TX_LPI_MINIPG_5GLITE_OFFSET (16) + #define RTL8373_EEE_TX_MINIFG_CTRL2_TX_LPI_MINIPG_5GLITE_MASK (0xFFFF << RTL8373_EEE_TX_MINIFG_CTRL2_TX_LPI_MINIPG_5GLITE_OFFSET) + #define RTL8373_EEE_TX_MINIFG_CTRL2_TX_LPI_MINIPG_2P5G_OFFSET (0) + #define RTL8373_EEE_TX_MINIFG_CTRL2_TX_LPI_MINIPG_2P5G_MASK (0xFFFF << RTL8373_EEE_TX_MINIFG_CTRL2_TX_LPI_MINIPG_2P5G_OFFSET) + +#define RTL8373_EEE_TX_MINIFG_CTRL3_ADDR (0x6000) + #define RTL8373_EEE_TX_MINIFG_CTRL3_TX_LPI_MINIPG_10GLITE_OFFSET (16) + #define RTL8373_EEE_TX_MINIFG_CTRL3_TX_LPI_MINIPG_10GLITE_MASK (0xFFFF << RTL8373_EEE_TX_MINIFG_CTRL3_TX_LPI_MINIPG_10GLITE_OFFSET) + #define RTL8373_EEE_TX_MINIFG_CTRL3_TX_LPI_MINIPG_5G_OFFSET (0) + #define RTL8373_EEE_TX_MINIFG_CTRL3_TX_LPI_MINIPG_5G_MASK (0xFFFF << RTL8373_EEE_TX_MINIFG_CTRL3_TX_LPI_MINIPG_5G_OFFSET) + +#define RTL8373_EEE_TX_MINIFG_CTRL4_ADDR (0x6004) + #define RTL8373_EEE_TX_MINIFG_CTRL4_TX_LPI_MINIPG_10G_OFFSET (0) + #define RTL8373_EEE_TX_MINIFG_CTRL4_TX_LPI_MINIPG_10G_MASK (0xFFFF << RTL8373_EEE_TX_MINIFG_CTRL4_TX_LPI_MINIPG_10G_OFFSET) + +#define RTL8373_EEE_TX_CTRL_ADDR (0x6008) + #define RTL8373_EEE_TX_CTRL_MULTIWAKE_PORTS_OFFSET (10) + #define RTL8373_EEE_TX_CTRL_MULTIWAKE_PORTS_MASK (0x3 << RTL8373_EEE_TX_CTRL_MULTIWAKE_PORTS_OFFSET) + #define RTL8373_EEE_TX_CTRL_MULTIWAKE_INTLV_OFFSET (8) + #define RTL8373_EEE_TX_CTRL_MULTIWAKE_INTLV_MASK (0x3 << RTL8373_EEE_TX_CTRL_MULTIWAKE_INTLV_OFFSET) + #define RTL8373_EEE_TX_CTRL_MULTIWAKE_TIME_UNIT_OFFSET (6) + #define RTL8373_EEE_TX_CTRL_MULTIWAKE_TIME_UNIT_MASK (0x3 << RTL8373_EEE_TX_CTRL_MULTIWAKE_TIME_UNIT_OFFSET) + #define RTL8373_EEE_TX_CTRL_MULTIWAKE_EN_OFFSET (5) + #define RTL8373_EEE_TX_CTRL_MULTIWAKE_EN_MASK (0x1 << RTL8373_EEE_TX_CTRL_MULTIWAKE_EN_OFFSET) + #define RTL8373_EEE_TX_CTRL_LINK_UP_DELAY_OFFSET (3) + #define RTL8373_EEE_TX_CTRL_LINK_UP_DELAY_MASK (0x3 << RTL8373_EEE_TX_CTRL_LINK_UP_DELAY_OFFSET) + #define RTL8373_EEE_TX_CTRL_EN_FC_EFCT_OFFSET (2) + #define RTL8373_EEE_TX_CTRL_EN_FC_EFCT_MASK (0x1 << RTL8373_EEE_TX_CTRL_EN_FC_EFCT_OFFSET) + #define RTL8373_EEE_TX_CTRL_REF_RXLPI_OFFSET (1) + #define RTL8373_EEE_TX_CTRL_REF_RXLPI_MASK (0x1 << RTL8373_EEE_TX_CTRL_REF_RXLPI_OFFSET) + #define RTL8373_EEE_TX_CTRL_TX_WAKE_SEL_OFFSET (0) + #define RTL8373_EEE_TX_CTRL_TX_WAKE_SEL_MASK (0x1 << RTL8373_EEE_TX_CTRL_TX_WAKE_SEL_OFFSET) + +#define RTL8373_EEE_TX_TIMER_100M_CTRL_ADDR (0x600C) + #define RTL8373_EEE_TX_TIMER_100M_CTRL_LOW_Q_TX_DELAY_FE_OFFSET (8) + #define RTL8373_EEE_TX_TIMER_100M_CTRL_LOW_Q_TX_DELAY_FE_MASK (0xFFF << RTL8373_EEE_TX_TIMER_100M_CTRL_LOW_Q_TX_DELAY_FE_OFFSET) + #define RTL8373_EEE_TX_TIMER_100M_CTRL_TX_WAKE_TIMER_FE_OFFSET (0) + #define RTL8373_EEE_TX_TIMER_100M_CTRL_TX_WAKE_TIMER_FE_MASK (0xFF << RTL8373_EEE_TX_TIMER_100M_CTRL_TX_WAKE_TIMER_FE_OFFSET) + +#define RTL8373_EEE_TX_TIMER_GELITE_CTRL_ADDR (0x6010) + #define RTL8373_EEE_TX_TIMER_GELITE_CTRL_LOW_Q_TX_DELAY_GELITE_OFFSET (16) + #define RTL8373_EEE_TX_TIMER_GELITE_CTRL_LOW_Q_TX_DELAY_GELITE_MASK (0xFFF << RTL8373_EEE_TX_TIMER_GELITE_CTRL_LOW_Q_TX_DELAY_GELITE_OFFSET) + #define RTL8373_EEE_TX_TIMER_GELITE_CTRL_TX_PAUSE_WAKE_TIMER_GELITE_OFFSET (8) + #define RTL8373_EEE_TX_TIMER_GELITE_CTRL_TX_PAUSE_WAKE_TIMER_GELITE_MASK (0xFF << RTL8373_EEE_TX_TIMER_GELITE_CTRL_TX_PAUSE_WAKE_TIMER_GELITE_OFFSET) + #define RTL8373_EEE_TX_TIMER_GELITE_CTRL_TX_WAKE_TIMER_GELITE_OFFSET (0) + #define RTL8373_EEE_TX_TIMER_GELITE_CTRL_TX_WAKE_TIMER_GELITE_MASK (0xFF << RTL8373_EEE_TX_TIMER_GELITE_CTRL_TX_WAKE_TIMER_GELITE_OFFSET) + +#define RTL8373_EEE_TX_TIMER_GIGA_CTRL_ADDR (0x6014) + #define RTL8373_EEE_TX_TIMER_GIGA_CTRL_LOW_Q_TX_DELAY_GE_OFFSET (16) + #define RTL8373_EEE_TX_TIMER_GIGA_CTRL_LOW_Q_TX_DELAY_GE_MASK (0xFFF << RTL8373_EEE_TX_TIMER_GIGA_CTRL_LOW_Q_TX_DELAY_GE_OFFSET) + #define RTL8373_EEE_TX_TIMER_GIGA_CTRL_TX_PAUSE_WAKE_TIMER_GE_OFFSET (8) + #define RTL8373_EEE_TX_TIMER_GIGA_CTRL_TX_PAUSE_WAKE_TIMER_GE_MASK (0xFF << RTL8373_EEE_TX_TIMER_GIGA_CTRL_TX_PAUSE_WAKE_TIMER_GE_OFFSET) + #define RTL8373_EEE_TX_TIMER_GIGA_CTRL_TX_WAKE_TIMER_GE_OFFSET (0) + #define RTL8373_EEE_TX_TIMER_GIGA_CTRL_TX_WAKE_TIMER_GE_MASK (0xFF << RTL8373_EEE_TX_TIMER_GIGA_CTRL_TX_WAKE_TIMER_GE_OFFSET) + +#define RTL8373_EEE_TX_TIMER_2P5GLITE_CTRL_ADDR (0x6018) + #define RTL8373_EEE_TX_TIMER_2P5GLITE_CTRL_LOW_Q_TX_DELAY_2P5GLITE_OFFSET (8) + #define RTL8373_EEE_TX_TIMER_2P5GLITE_CTRL_LOW_Q_TX_DELAY_2P5GLITE_MASK (0xFFF << RTL8373_EEE_TX_TIMER_2P5GLITE_CTRL_LOW_Q_TX_DELAY_2P5GLITE_OFFSET) + #define RTL8373_EEE_TX_TIMER_2P5GLITE_CTRL_TX_WAKE_TIMER_2P5GLITE_OFFSET (0) + #define RTL8373_EEE_TX_TIMER_2P5GLITE_CTRL_TX_WAKE_TIMER_2P5GLITE_MASK (0xFF << RTL8373_EEE_TX_TIMER_2P5GLITE_CTRL_TX_WAKE_TIMER_2P5GLITE_OFFSET) + +#define RTL8373_EEE_TX_TIMER_2P5G_CTRL_ADDR (0x601C) + #define RTL8373_EEE_TX_TIMER_2P5G_CTRL_LOW_Q_TX_DELAY_2P5G_OFFSET (8) + #define RTL8373_EEE_TX_TIMER_2P5G_CTRL_LOW_Q_TX_DELAY_2P5G_MASK (0xFFF << RTL8373_EEE_TX_TIMER_2P5G_CTRL_LOW_Q_TX_DELAY_2P5G_OFFSET) + #define RTL8373_EEE_TX_TIMER_2P5G_CTRL_TX_WAKE_TIMER_2P5G_OFFSET (0) + #define RTL8373_EEE_TX_TIMER_2P5G_CTRL_TX_WAKE_TIMER_2P5G_MASK (0xFF << RTL8373_EEE_TX_TIMER_2P5G_CTRL_TX_WAKE_TIMER_2P5G_OFFSET) + +#define RTL8373_EEE_TX_TIMER_5GLITE_CTRL_ADDR (0x6020) + #define RTL8373_EEE_TX_TIMER_5GLITE_CTRL_LOW_Q_TX_DELAY_5GLITE_OFFSET (8) + #define RTL8373_EEE_TX_TIMER_5GLITE_CTRL_LOW_Q_TX_DELAY_5GLITE_MASK (0xFFF << RTL8373_EEE_TX_TIMER_5GLITE_CTRL_LOW_Q_TX_DELAY_5GLITE_OFFSET) + #define RTL8373_EEE_TX_TIMER_5GLITE_CTRL_TX_WAKE_TIMER_5GLITE_OFFSET (0) + #define RTL8373_EEE_TX_TIMER_5GLITE_CTRL_TX_WAKE_TIMER_5GLITE_MASK (0xFF << RTL8373_EEE_TX_TIMER_5GLITE_CTRL_TX_WAKE_TIMER_5GLITE_OFFSET) + +#define RTL8373_EEE_TX_TIMER_5G_CTRL_ADDR (0x6024) + #define RTL8373_EEE_TX_TIMER_5G_CTRL_LOW_Q_TX_DELAY_5G_OFFSET (8) + #define RTL8373_EEE_TX_TIMER_5G_CTRL_LOW_Q_TX_DELAY_5G_MASK (0xFFF << RTL8373_EEE_TX_TIMER_5G_CTRL_LOW_Q_TX_DELAY_5G_OFFSET) + #define RTL8373_EEE_TX_TIMER_5G_CTRL_TX_WAKE_TIMER_5G_OFFSET (0) + #define RTL8373_EEE_TX_TIMER_5G_CTRL_TX_WAKE_TIMER_5G_MASK (0xFF << RTL8373_EEE_TX_TIMER_5G_CTRL_TX_WAKE_TIMER_5G_OFFSET) + +#define RTL8373_EEE_TX_TIMER_10GLITE_CTRL_ADDR (0x6028) + #define RTL8373_EEE_TX_TIMER_10GLITE_CTRL_LOW_Q_TX_DELAY_10GLITE_OFFSET (8) + #define RTL8373_EEE_TX_TIMER_10GLITE_CTRL_LOW_Q_TX_DELAY_10GLITE_MASK (0xFFF << RTL8373_EEE_TX_TIMER_10GLITE_CTRL_LOW_Q_TX_DELAY_10GLITE_OFFSET) + #define RTL8373_EEE_TX_TIMER_10GLITE_CTRL_TX_WAKE_TIMER_10GLITE_OFFSET (0) + #define RTL8373_EEE_TX_TIMER_10GLITE_CTRL_TX_WAKE_TIMER_10GLITE_MASK (0xFF << RTL8373_EEE_TX_TIMER_10GLITE_CTRL_TX_WAKE_TIMER_10GLITE_OFFSET) + +#define RTL8373_EEE_TX_TIMER_10G_CTRL_ADDR (0x602C) + #define RTL8373_EEE_TX_TIMER_10G_CTRL_LOW_Q_TX_DELAY_10G_OFFSET (8) + #define RTL8373_EEE_TX_TIMER_10G_CTRL_LOW_Q_TX_DELAY_10G_MASK (0xFFF << RTL8373_EEE_TX_TIMER_10G_CTRL_LOW_Q_TX_DELAY_10G_OFFSET) + #define RTL8373_EEE_TX_TIMER_10G_CTRL_TX_WAKE_TIMER_10G_OFFSET (0) + #define RTL8373_EEE_TX_TIMER_10G_CTRL_TX_WAKE_TIMER_10G_MASK (0xFF << RTL8373_EEE_TX_TIMER_10G_CTRL_TX_WAKE_TIMER_10G_OFFSET) + +#define RTL8373_EEE_CTRL_ADDR(port) (0x125C + (((port) << 8))) /* port: 0-9 */ + #define RTL8373_EEE_CTRL_EEE_RX_STS_OFFSET (3) + #define RTL8373_EEE_CTRL_EEE_RX_STS_MASK (0x1 << RTL8373_EEE_CTRL_EEE_RX_STS_OFFSET) + #define RTL8373_EEE_CTRL_EEE_TX_STS_OFFSET (2) + #define RTL8373_EEE_CTRL_EEE_TX_STS_MASK (0x1 << RTL8373_EEE_CTRL_EEE_TX_STS_OFFSET) + #define RTL8373_EEE_CTRL_EEE_PORT_TX_EN_OFFSET (1) + #define RTL8373_EEE_CTRL_EEE_PORT_TX_EN_MASK (0x1 << RTL8373_EEE_CTRL_EEE_PORT_TX_EN_OFFSET) + #define RTL8373_EEE_CTRL_EEE_PORT_RX_EN_OFFSET (0) + #define RTL8373_EEE_CTRL_EEE_PORT_RX_EN_MASK (0x1 << RTL8373_EEE_CTRL_EEE_PORT_RX_EN_OFFSET) + +#define RTL8373_EEE_RX_GELITE_CTRL_ADDR (0x6030) + #define RTL8373_EEE_RX_GELITE_CTRL_WAIT_RX_INACTIVE_GELITE_OFFSET (8) + #define RTL8373_EEE_RX_GELITE_CTRL_WAIT_RX_INACTIVE_GELITE_MASK (0x1 << RTL8373_EEE_RX_GELITE_CTRL_WAIT_RX_INACTIVE_GELITE_OFFSET) + #define RTL8373_EEE_RX_GELITE_CTRL_WAIT_RX_INACTIVE_TIMER_GELITE_OFFSET (0) + #define RTL8373_EEE_RX_GELITE_CTRL_WAIT_RX_INACTIVE_TIMER_GELITE_MASK (0xFF << RTL8373_EEE_RX_GELITE_CTRL_WAIT_RX_INACTIVE_TIMER_GELITE_OFFSET) + +#define RTL8373_EEE_RX_GE_CTRL_ADDR (0x6034) + #define RTL8373_EEE_RX_GE_CTRL_WAIT_RX_INACTIVE_GE_OFFSET (8) + #define RTL8373_EEE_RX_GE_CTRL_WAIT_RX_INACTIVE_GE_MASK (0x1 << RTL8373_EEE_RX_GE_CTRL_WAIT_RX_INACTIVE_GE_OFFSET) + #define RTL8373_EEE_RX_GE_CTRL_WAIT_RX_INACTIVE_TIMER_GE_OFFSET (0) + #define RTL8373_EEE_RX_GE_CTRL_WAIT_RX_INACTIVE_TIMER_GE_MASK (0xFF << RTL8373_EEE_RX_GE_CTRL_WAIT_RX_INACTIVE_TIMER_GE_OFFSET) + +#define RTL8373_LPI_OPTION_ADDR (0x1038) + #define RTL8373_LPI_OPTION_MAC8_LPI_OPTION_OFFSET (1) + #define RTL8373_LPI_OPTION_MAC8_LPI_OPTION_MASK (0x1 << RTL8373_LPI_OPTION_MAC8_LPI_OPTION_OFFSET) + #define RTL8373_LPI_OPTION_MAC3_LPI_OPTION_OFFSET (0) + #define RTL8373_LPI_OPTION_MAC3_LPI_OPTION_MASK (0x1 << RTL8373_LPI_OPTION_MAC3_LPI_OPTION_OFFSET) + +/* + * Feature: RA + */ +#define RTL8373_RA_FIFO_FUL_THR0_ADDR (0xE0F0) + #define RTL8373_RA_FIFO_FUL_THR0_RXFIFO_FULL_TH_OFFSET (11) + #define RTL8373_RA_FIFO_FUL_THR0_RXFIFO_FULL_TH_MASK (0x7FF << RTL8373_RA_FIFO_FUL_THR0_RXFIFO_FULL_TH_OFFSET) + #define RTL8373_RA_FIFO_FUL_THR0_TXFIFO_FULL_TH_OFFSET (0) + #define RTL8373_RA_FIFO_FUL_THR0_TXFIFO_FULL_TH_MASK (0x7FF << RTL8373_RA_FIFO_FUL_THR0_TXFIFO_FULL_TH_OFFSET) + +#define RTL8373_RA_FIFO_EMPTY_THR0_ADDR (0xE0F4) + #define RTL8373_RA_FIFO_EMPTY_THR0_FIFO_EMPTY_TH_OFFSET (0) + #define RTL8373_RA_FIFO_EMPTY_THR0_FIFO_EMPTY_TH_MASK (0x7FF << RTL8373_RA_FIFO_EMPTY_THR0_FIFO_EMPTY_TH_OFFSET) + +#define RTL8373_RA_TX_STATUS0_ADDR (0xE0F8) + #define RTL8373_RA_TX_STATUS0_H2E_TX_STATUS_OFFSET (0) + #define RTL8373_RA_TX_STATUS0_H2E_TX_STATUS_MASK (0xFFFFFFFF << RTL8373_RA_TX_STATUS0_H2E_TX_STATUS_OFFSET) + +#define RTL8373_RA_RX_STATUS0_ADDR (0xE0FC) + #define RTL8373_RA_RX_STATUS0_H2E_RX_STATUS_OFFSET (0) + #define RTL8373_RA_RX_STATUS0_H2E_RX_STATUS_MASK (0xFFFFFFFF << RTL8373_RA_RX_STATUS0_H2E_RX_STATUS_OFFSET) + +#define RTL8373_RA_HSG_IFG0_ADDR (0xE100) + #define RTL8373_RA_HSG_IFG0_HSG_XGMI_RX_IFG_OFFSET (24) + #define RTL8373_RA_HSG_IFG0_HSG_XGMI_RX_IFG_MASK (0xFF << RTL8373_RA_HSG_IFG0_HSG_XGMI_RX_IFG_OFFSET) + #define RTL8373_RA_HSG_IFG0_HSG_XGMI_TX_IFG_OFFSET (16) + #define RTL8373_RA_HSG_IFG0_HSG_XGMI_TX_IFG_MASK (0xFF << RTL8373_RA_HSG_IFG0_HSG_XGMI_TX_IFG_OFFSET) + #define RTL8373_RA_HSG_IFG0_HSG_GMI_RX_IFG_OFFSET (8) + #define RTL8373_RA_HSG_IFG0_HSG_GMI_RX_IFG_MASK (0xFF << RTL8373_RA_HSG_IFG0_HSG_GMI_RX_IFG_OFFSET) + #define RTL8373_RA_HSG_IFG0_HSG_GMI_TX_IFG_OFFSET (0) + #define RTL8373_RA_HSG_IFG0_HSG_GMI_TX_IFG_MASK (0xFF << RTL8373_RA_HSG_IFG0_HSG_GMI_TX_IFG_OFFSET) + +#define RTL8373_RA_MACSEC_ETH0_ADDR(index) (0xE104 + (((index >> 1) << 2))) /* index: 0-7 */ + #define RTL8373_RA_MACSEC_ETH0_MACSEC_ETH_OFFSET(index) ((index & 0x1) << 4) + #define RTL8373_RA_MACSEC_ETH0_MACSEC_ETH_MASK(index) (0xFFFF << RTL8373_RA_MACSEC_ETH0_MACSEC_ETH_OFFSET(index)) + +#define RTL8373_RA_MACSEC_VLAN0_ADDR(index) (0xE114 + (((index >> 1) << 2))) /* index: 0-10 */ + #define RTL8373_RA_MACSEC_VLAN0_MACSEC_VLAN_OFFSET(index) ((index & 0x1) << 4) + #define RTL8373_RA_MACSEC_VLAN0_MACSEC_VLAN_MASK(index) (0xFFFF << RTL8373_RA_MACSEC_VLAN0_MACSEC_VLAN_OFFSET(index)) + +#define RTL8373_RA_MACSEC_IFG_CTRL0_ADDR (0xE12C) + #define RTL8373_RA_MACSEC_IFG_CTRL0_RG_H2E_MACSEC_IFG_EN_OFFSET (3) + #define RTL8373_RA_MACSEC_IFG_CTRL0_RG_H2E_MACSEC_IFG_EN_MASK (0x1 << RTL8373_RA_MACSEC_IFG_CTRL0_RG_H2E_MACSEC_IFG_EN_OFFSET) + #define RTL8373_RA_MACSEC_IFG_CTRL0_MACSEC_IFG_SEL_OFFSET (0) + #define RTL8373_RA_MACSEC_IFG_CTRL0_MACSEC_IFG_SEL_MASK (0x7 << RTL8373_RA_MACSEC_IFG_CTRL0_MACSEC_IFG_SEL_OFFSET) + +#define RTL8373_RA_PAUSE_CTRL0_ADDR (0xE130) + #define RTL8373_RA_PAUSE_CTRL0_RG_PAUSE_ACCEPT_MAC_SA_OFFSET (18) + #define RTL8373_RA_PAUSE_CTRL0_RG_PAUSE_ACCEPT_MAC_SA_MASK (0x1 << RTL8373_RA_PAUSE_CTRL0_RG_PAUSE_ACCEPT_MAC_SA_OFFSET) + #define RTL8373_RA_PAUSE_CTRL0_RG_SDS_PAUSE_DECT_EN_OFFSET (17) + #define RTL8373_RA_PAUSE_CTRL0_RG_SDS_PAUSE_DECT_EN_MASK (0x1 << RTL8373_RA_PAUSE_CTRL0_RG_SDS_PAUSE_DECT_EN_OFFSET) + #define RTL8373_RA_PAUSE_CTRL0_RG_ETH_PAUSE_DECT_EN_OFFSET (16) + #define RTL8373_RA_PAUSE_CTRL0_RG_ETH_PAUSE_DECT_EN_MASK (0x1 << RTL8373_RA_PAUSE_CTRL0_RG_ETH_PAUSE_DECT_EN_OFFSET) + #define RTL8373_RA_PAUSE_CTRL0_RG_H2E_MAC_SA_H_OFFSET (0) + #define RTL8373_RA_PAUSE_CTRL0_RG_H2E_MAC_SA_H_MASK (0xFFFF << RTL8373_RA_PAUSE_CTRL0_RG_H2E_MAC_SA_H_OFFSET) + #define RTL8373_RA_PAUSE_CTRL0_RG_H2E_MAC_SA_L_OFFSET (32) + #define RTL8373_RA_PAUSE_CTRL0_RG_H2E_MAC_SA_L_MASK (0xFFFFFFFF << RTL8373_RA_PAUSE_CTRL0_RG_H2E_MAC_SA_L_OFFSET) + +#define RTL8373_RA_GLB_CTRL0_ADDR (0xE138) + #define RTL8373_RA_GLB_CTRL0_RG_PRMB_NUM_OFFSET (2) + #define RTL8373_RA_GLB_CTRL0_RG_PRMB_NUM_MASK (0x7 << RTL8373_RA_GLB_CTRL0_RG_PRMB_NUM_OFFSET) + #define RTL8373_RA_GLB_CTRL0_RG_H2E_ENABLE_OFFSET (1) + #define RTL8373_RA_GLB_CTRL0_RG_H2E_ENABLE_MASK (0x1 << RTL8373_RA_GLB_CTRL0_RG_H2E_ENABLE_OFFSET) + #define RTL8373_RA_GLB_CTRL0_RG_H2E_BYPASS_MODE_OFFSET (0) + #define RTL8373_RA_GLB_CTRL0_RG_H2E_BYPASS_MODE_MASK (0x1 << RTL8373_RA_GLB_CTRL0_RG_H2E_BYPASS_MODE_OFFSET) + +#define RTL8373_RA_PADDING_CTRL0_ADDR (0xE13C) + #define RTL8373_RA_PADDING_CTRL0_RG_H2E_PADDING_VLAN_OFFSET (2) + #define RTL8373_RA_PADDING_CTRL0_RG_H2E_PADDING_VLAN_MASK (0x1 << RTL8373_RA_PADDING_CTRL0_RG_H2E_PADDING_VLAN_OFFSET) + #define RTL8373_RA_PADDING_CTRL0_RG_H2E_PADDING_MACSEC_OFFSET (1) + #define RTL8373_RA_PADDING_CTRL0_RG_H2E_PADDING_MACSEC_MASK (0x1 << RTL8373_RA_PADDING_CTRL0_RG_H2E_PADDING_MACSEC_OFFSET) + #define RTL8373_RA_PADDING_CTRL0_RG_H2E_PADDING_EN_OFFSET (0) + #define RTL8373_RA_PADDING_CTRL0_RG_H2E_PADDING_EN_MASK (0x1 << RTL8373_RA_PADDING_CTRL0_RG_H2E_PADDING_EN_OFFSET) + +#define RTL8373_RA_SLOT_TIME0_ADDR (0xE140) + #define RTL8373_RA_SLOT_TIME0_SLOT_TIME_OFFSET (0) + #define RTL8373_RA_SLOT_TIME0_SLOT_TIME_MASK (0xFFFF << RTL8373_RA_SLOT_TIME0_SLOT_TIME_OFFSET) + +#define RTL8373_RA_SOFT_RST0_ADDR (0xE144) + #define RTL8373_RA_SOFT_RST0_RST_OFFSET (0) + #define RTL8373_RA_SOFT_RST0_RST_MASK (0x1 << RTL8373_RA_SOFT_RST0_RST_OFFSET) + +#define RTL8373_RA_FIFO_FUL_THR1_ADDR (0xE2F0) + #define RTL8373_RA_FIFO_FUL_THR1_RXFIFO_FULL_TH_OFFSET (11) + #define RTL8373_RA_FIFO_FUL_THR1_RXFIFO_FULL_TH_MASK (0x7FF << RTL8373_RA_FIFO_FUL_THR1_RXFIFO_FULL_TH_OFFSET) + #define RTL8373_RA_FIFO_FUL_THR1_TXFIFO_FULL_TH_OFFSET (0) + #define RTL8373_RA_FIFO_FUL_THR1_TXFIFO_FULL_TH_MASK (0x7FF << RTL8373_RA_FIFO_FUL_THR1_TXFIFO_FULL_TH_OFFSET) + +#define RTL8373_RA_FIFO_EMPTY_THR1_ADDR (0xE2F4) + #define RTL8373_RA_FIFO_EMPTY_THR1_FIFO_EMPTY_TH_OFFSET (0) + #define RTL8373_RA_FIFO_EMPTY_THR1_FIFO_EMPTY_TH_MASK (0x7FF << RTL8373_RA_FIFO_EMPTY_THR1_FIFO_EMPTY_TH_OFFSET) + +#define RTL8373_RA_TX_STATUS1_ADDR (0xE2F8) + #define RTL8373_RA_TX_STATUS1_H2E_TX_STATUS_OFFSET (0) + #define RTL8373_RA_TX_STATUS1_H2E_TX_STATUS_MASK (0xFFFFFFFF << RTL8373_RA_TX_STATUS1_H2E_TX_STATUS_OFFSET) + +#define RTL8373_RA_RX_STATUS1_ADDR (0xE2FC) + #define RTL8373_RA_RX_STATUS1_H2E_RX_STATUS_OFFSET (0) + #define RTL8373_RA_RX_STATUS1_H2E_RX_STATUS_MASK (0xFFFFFFFF << RTL8373_RA_RX_STATUS1_H2E_RX_STATUS_OFFSET) + +#define RTL8373_RA_HSG_IFG1_ADDR (0xE300) + #define RTL8373_RA_HSG_IFG1_HSG_XGMI_RX_IFG_OFFSET (24) + #define RTL8373_RA_HSG_IFG1_HSG_XGMI_RX_IFG_MASK (0xFF << RTL8373_RA_HSG_IFG1_HSG_XGMI_RX_IFG_OFFSET) + #define RTL8373_RA_HSG_IFG1_HSG_XGMI_TX_IFG_OFFSET (16) + #define RTL8373_RA_HSG_IFG1_HSG_XGMI_TX_IFG_MASK (0xFF << RTL8373_RA_HSG_IFG1_HSG_XGMI_TX_IFG_OFFSET) + #define RTL8373_RA_HSG_IFG1_HSG_GMI_RX_IFG_OFFSET (8) + #define RTL8373_RA_HSG_IFG1_HSG_GMI_RX_IFG_MASK (0xFF << RTL8373_RA_HSG_IFG1_HSG_GMI_RX_IFG_OFFSET) + #define RTL8373_RA_HSG_IFG1_HSG_GMI_TX_IFG_OFFSET (0) + #define RTL8373_RA_HSG_IFG1_HSG_GMI_TX_IFG_MASK (0xFF << RTL8373_RA_HSG_IFG1_HSG_GMI_TX_IFG_OFFSET) + +#define RTL8373_RA_MACSEC_ETH1_ADDR(index) (0xE304 + (((index >> 1) << 2))) /* index: 0-7 */ + #define RTL8373_RA_MACSEC_ETH1_MACSEC_ETH_OFFSET(index) ((index & 0x1) << 4) + #define RTL8373_RA_MACSEC_ETH1_MACSEC_ETH_MASK(index) (0xFFFF << RTL8373_RA_MACSEC_ETH1_MACSEC_ETH_OFFSET(index)) + +#define RTL8373_RA_MACSEC_VLAN1_ADDR(index) (0xE314 + (((index >> 1) << 2))) /* index: 0-10 */ + #define RTL8373_RA_MACSEC_VLAN1_MACSEC_VLAN_OFFSET(index) ((index & 0x1) << 4) + #define RTL8373_RA_MACSEC_VLAN1_MACSEC_VLAN_MASK(index) (0xFFFF << RTL8373_RA_MACSEC_VLAN1_MACSEC_VLAN_OFFSET(index)) + +#define RTL8373_RA_MACSEC_IFG_CTRL1_ADDR (0xE32C) + #define RTL8373_RA_MACSEC_IFG_CTRL1_RG_H2E_MACSEC_IFG_EN_OFFSET (3) + #define RTL8373_RA_MACSEC_IFG_CTRL1_RG_H2E_MACSEC_IFG_EN_MASK (0x1 << RTL8373_RA_MACSEC_IFG_CTRL1_RG_H2E_MACSEC_IFG_EN_OFFSET) + #define RTL8373_RA_MACSEC_IFG_CTRL1_MACSEC_IFG_SEL_OFFSET (0) + #define RTL8373_RA_MACSEC_IFG_CTRL1_MACSEC_IFG_SEL_MASK (0x7 << RTL8373_RA_MACSEC_IFG_CTRL1_MACSEC_IFG_SEL_OFFSET) + +#define RTL8373_RA_PAUSE_CTRL1_ADDR (0xE330) + #define RTL8373_RA_PAUSE_CTRL1_RG_PAUSE_ACCEPT_MAC_SA_OFFSET (18) + #define RTL8373_RA_PAUSE_CTRL1_RG_PAUSE_ACCEPT_MAC_SA_MASK (0x1 << RTL8373_RA_PAUSE_CTRL1_RG_PAUSE_ACCEPT_MAC_SA_OFFSET) + #define RTL8373_RA_PAUSE_CTRL1_RG_SDS_PAUSE_DECT_EN_OFFSET (17) + #define RTL8373_RA_PAUSE_CTRL1_RG_SDS_PAUSE_DECT_EN_MASK (0x1 << RTL8373_RA_PAUSE_CTRL1_RG_SDS_PAUSE_DECT_EN_OFFSET) + #define RTL8373_RA_PAUSE_CTRL1_RG_ETH_PAUSE_DECT_EN_OFFSET (16) + #define RTL8373_RA_PAUSE_CTRL1_RG_ETH_PAUSE_DECT_EN_MASK (0x1 << RTL8373_RA_PAUSE_CTRL1_RG_ETH_PAUSE_DECT_EN_OFFSET) + #define RTL8373_RA_PAUSE_CTRL1_RG_H2E_MAC_SA_H_OFFSET (0) + #define RTL8373_RA_PAUSE_CTRL1_RG_H2E_MAC_SA_H_MASK (0xFFFF << RTL8373_RA_PAUSE_CTRL1_RG_H2E_MAC_SA_H_OFFSET) + #define RTL8373_RA_PAUSE_CTRL1_RG_H2E_MAC_SA_L_OFFSET (32) + #define RTL8373_RA_PAUSE_CTRL1_RG_H2E_MAC_SA_L_MASK (0xFFFFFFFF << RTL8373_RA_PAUSE_CTRL1_RG_H2E_MAC_SA_L_OFFSET) + +#define RTL8373_RA_GLB_CTRL1_ADDR (0xE338) + #define RTL8373_RA_GLB_CTRL1_RG_PRMB_NUM_OFFSET (2) + #define RTL8373_RA_GLB_CTRL1_RG_PRMB_NUM_MASK (0x7 << RTL8373_RA_GLB_CTRL1_RG_PRMB_NUM_OFFSET) + #define RTL8373_RA_GLB_CTRL1_RG_H2E_ENABLE_OFFSET (1) + #define RTL8373_RA_GLB_CTRL1_RG_H2E_ENABLE_MASK (0x1 << RTL8373_RA_GLB_CTRL1_RG_H2E_ENABLE_OFFSET) + #define RTL8373_RA_GLB_CTRL1_RG_H2E_BYPASS_MODE_OFFSET (0) + #define RTL8373_RA_GLB_CTRL1_RG_H2E_BYPASS_MODE_MASK (0x1 << RTL8373_RA_GLB_CTRL1_RG_H2E_BYPASS_MODE_OFFSET) + +#define RTL8373_RA_PADDING_CTRL1_ADDR (0xE33C) + #define RTL8373_RA_PADDING_CTRL1_RG_H2E_PADDING_VLAN_OFFSET (2) + #define RTL8373_RA_PADDING_CTRL1_RG_H2E_PADDING_VLAN_MASK (0x1 << RTL8373_RA_PADDING_CTRL1_RG_H2E_PADDING_VLAN_OFFSET) + #define RTL8373_RA_PADDING_CTRL1_RG_H2E_PADDING_MACSEC_OFFSET (1) + #define RTL8373_RA_PADDING_CTRL1_RG_H2E_PADDING_MACSEC_MASK (0x1 << RTL8373_RA_PADDING_CTRL1_RG_H2E_PADDING_MACSEC_OFFSET) + #define RTL8373_RA_PADDING_CTRL1_RG_H2E_PADDING_EN_OFFSET (0) + #define RTL8373_RA_PADDING_CTRL1_RG_H2E_PADDING_EN_MASK (0x1 << RTL8373_RA_PADDING_CTRL1_RG_H2E_PADDING_EN_OFFSET) + +#define RTL8373_RA_SLOT_TIME1_ADDR (0xE340) + #define RTL8373_RA_SLOT_TIME1_SLOT_TIME_OFFSET (0) + #define RTL8373_RA_SLOT_TIME1_SLOT_TIME_MASK (0xFFFF << RTL8373_RA_SLOT_TIME1_SLOT_TIME_OFFSET) + +#define RTL8373_RA_SOFT_RST1_ADDR (0xE344) + #define RTL8373_RA_SOFT_RST1_RST_OFFSET (0) + #define RTL8373_RA_SOFT_RST1_RST_MASK (0x1 << RTL8373_RA_SOFT_RST1_RST_OFFSET) + +#define RTL8373_RA_FIFO_FUL_THR2_ADDR (0xE4F0) + #define RTL8373_RA_FIFO_FUL_THR2_RXFIFO_FULL_TH_OFFSET (11) + #define RTL8373_RA_FIFO_FUL_THR2_RXFIFO_FULL_TH_MASK (0x7FF << RTL8373_RA_FIFO_FUL_THR2_RXFIFO_FULL_TH_OFFSET) + #define RTL8373_RA_FIFO_FUL_THR2_TXFIFO_FULL_TH_OFFSET (0) + #define RTL8373_RA_FIFO_FUL_THR2_TXFIFO_FULL_TH_MASK (0x7FF << RTL8373_RA_FIFO_FUL_THR2_TXFIFO_FULL_TH_OFFSET) + +#define RTL8373_RA_FIFO_EMPTY_THR2_ADDR (0xE4F4) + #define RTL8373_RA_FIFO_EMPTY_THR2_FIFO_EMPTY_TH_OFFSET (0) + #define RTL8373_RA_FIFO_EMPTY_THR2_FIFO_EMPTY_TH_MASK (0x7FF << RTL8373_RA_FIFO_EMPTY_THR2_FIFO_EMPTY_TH_OFFSET) + +#define RTL8373_RA_TX_STATUS2_ADDR (0xE4F8) + #define RTL8373_RA_TX_STATUS2_H2E_TX_STATUS_OFFSET (0) + #define RTL8373_RA_TX_STATUS2_H2E_TX_STATUS_MASK (0xFFFFFFFF << RTL8373_RA_TX_STATUS2_H2E_TX_STATUS_OFFSET) + +#define RTL8373_RA_RX_STATUS2_ADDR (0xE4FC) + #define RTL8373_RA_RX_STATUS2_H2E_RX_STATUS_OFFSET (0) + #define RTL8373_RA_RX_STATUS2_H2E_RX_STATUS_MASK (0xFFFFFFFF << RTL8373_RA_RX_STATUS2_H2E_RX_STATUS_OFFSET) + +#define RTL8373_RA_HSG_IFG2_ADDR (0xE500) + #define RTL8373_RA_HSG_IFG2_HSG_XGMI_RX_IFG_OFFSET (24) + #define RTL8373_RA_HSG_IFG2_HSG_XGMI_RX_IFG_MASK (0xFF << RTL8373_RA_HSG_IFG2_HSG_XGMI_RX_IFG_OFFSET) + #define RTL8373_RA_HSG_IFG2_HSG_XGMI_TX_IFG_OFFSET (16) + #define RTL8373_RA_HSG_IFG2_HSG_XGMI_TX_IFG_MASK (0xFF << RTL8373_RA_HSG_IFG2_HSG_XGMI_TX_IFG_OFFSET) + #define RTL8373_RA_HSG_IFG2_HSG_GMI_RX_IFG_OFFSET (8) + #define RTL8373_RA_HSG_IFG2_HSG_GMI_RX_IFG_MASK (0xFF << RTL8373_RA_HSG_IFG2_HSG_GMI_RX_IFG_OFFSET) + #define RTL8373_RA_HSG_IFG2_HSG_GMI_TX_IFG_OFFSET (0) + #define RTL8373_RA_HSG_IFG2_HSG_GMI_TX_IFG_MASK (0xFF << RTL8373_RA_HSG_IFG2_HSG_GMI_TX_IFG_OFFSET) + +#define RTL8373_RA_MACSEC_ETH2_ADDR(index) (0xE504 + (((index >> 1) << 2))) /* index: 0-7 */ + #define RTL8373_RA_MACSEC_ETH2_MACSEC_ETH_OFFSET(index) ((index & 0x1) << 4) + #define RTL8373_RA_MACSEC_ETH2_MACSEC_ETH_MASK(index) (0xFFFF << RTL8373_RA_MACSEC_ETH2_MACSEC_ETH_OFFSET(index)) + +#define RTL8373_RA_MACSEC_VLAN2_ADDR(index) (0xE514 + (((index >> 1) << 2))) /* index: 0-10 */ + #define RTL8373_RA_MACSEC_VLAN2_MACSEC_VLAN_OFFSET(index) ((index & 0x1) << 4) + #define RTL8373_RA_MACSEC_VLAN2_MACSEC_VLAN_MASK(index) (0xFFFF << RTL8373_RA_MACSEC_VLAN2_MACSEC_VLAN_OFFSET(index)) + +#define RTL8373_RA_MACSEC_IFG_CTRL2_ADDR (0xE52C) + #define RTL8373_RA_MACSEC_IFG_CTRL2_RG_H2E_MACSEC_IFG_EN_OFFSET (3) + #define RTL8373_RA_MACSEC_IFG_CTRL2_RG_H2E_MACSEC_IFG_EN_MASK (0x1 << RTL8373_RA_MACSEC_IFG_CTRL2_RG_H2E_MACSEC_IFG_EN_OFFSET) + #define RTL8373_RA_MACSEC_IFG_CTRL2_MACSEC_IFG_SEL_OFFSET (0) + #define RTL8373_RA_MACSEC_IFG_CTRL2_MACSEC_IFG_SEL_MASK (0x7 << RTL8373_RA_MACSEC_IFG_CTRL2_MACSEC_IFG_SEL_OFFSET) + +#define RTL8373_RA_PAUSE_CTRL2_ADDR (0xE530) + #define RTL8373_RA_PAUSE_CTRL2_RG_PAUSE_ACCEPT_MAC_SA_OFFSET (18) + #define RTL8373_RA_PAUSE_CTRL2_RG_PAUSE_ACCEPT_MAC_SA_MASK (0x1 << RTL8373_RA_PAUSE_CTRL2_RG_PAUSE_ACCEPT_MAC_SA_OFFSET) + #define RTL8373_RA_PAUSE_CTRL2_RG_SDS_PAUSE_DECT_EN_OFFSET (17) + #define RTL8373_RA_PAUSE_CTRL2_RG_SDS_PAUSE_DECT_EN_MASK (0x1 << RTL8373_RA_PAUSE_CTRL2_RG_SDS_PAUSE_DECT_EN_OFFSET) + #define RTL8373_RA_PAUSE_CTRL2_RG_ETH_PAUSE_DECT_EN_OFFSET (16) + #define RTL8373_RA_PAUSE_CTRL2_RG_ETH_PAUSE_DECT_EN_MASK (0x1 << RTL8373_RA_PAUSE_CTRL2_RG_ETH_PAUSE_DECT_EN_OFFSET) + #define RTL8373_RA_PAUSE_CTRL2_RG_H2E_MAC_SA_H_OFFSET (0) + #define RTL8373_RA_PAUSE_CTRL2_RG_H2E_MAC_SA_H_MASK (0xFFFF << RTL8373_RA_PAUSE_CTRL2_RG_H2E_MAC_SA_H_OFFSET) + #define RTL8373_RA_PAUSE_CTRL2_RG_H2E_MAC_SA_L_OFFSET (32) + #define RTL8373_RA_PAUSE_CTRL2_RG_H2E_MAC_SA_L_MASK (0xFFFFFFFF << RTL8373_RA_PAUSE_CTRL2_RG_H2E_MAC_SA_L_OFFSET) + +#define RTL8373_RA_GLB_CTRL2_ADDR (0xE538) + #define RTL8373_RA_GLB_CTRL2_RG_PRMB_NUM_OFFSET (2) + #define RTL8373_RA_GLB_CTRL2_RG_PRMB_NUM_MASK (0x7 << RTL8373_RA_GLB_CTRL2_RG_PRMB_NUM_OFFSET) + #define RTL8373_RA_GLB_CTRL2_RG_H2E_ENABLE_OFFSET (1) + #define RTL8373_RA_GLB_CTRL2_RG_H2E_ENABLE_MASK (0x1 << RTL8373_RA_GLB_CTRL2_RG_H2E_ENABLE_OFFSET) + #define RTL8373_RA_GLB_CTRL2_RG_H2E_BYPASS_MODE_OFFSET (0) + #define RTL8373_RA_GLB_CTRL2_RG_H2E_BYPASS_MODE_MASK (0x1 << RTL8373_RA_GLB_CTRL2_RG_H2E_BYPASS_MODE_OFFSET) + +#define RTL8373_RA_PADDING_CTRL2_ADDR (0xE53C) + #define RTL8373_RA_PADDING_CTRL2_RG_H2E_PADDING_VLAN_OFFSET (2) + #define RTL8373_RA_PADDING_CTRL2_RG_H2E_PADDING_VLAN_MASK (0x1 << RTL8373_RA_PADDING_CTRL2_RG_H2E_PADDING_VLAN_OFFSET) + #define RTL8373_RA_PADDING_CTRL2_RG_H2E_PADDING_MACSEC_OFFSET (1) + #define RTL8373_RA_PADDING_CTRL2_RG_H2E_PADDING_MACSEC_MASK (0x1 << RTL8373_RA_PADDING_CTRL2_RG_H2E_PADDING_MACSEC_OFFSET) + #define RTL8373_RA_PADDING_CTRL2_RG_H2E_PADDING_EN_OFFSET (0) + #define RTL8373_RA_PADDING_CTRL2_RG_H2E_PADDING_EN_MASK (0x1 << RTL8373_RA_PADDING_CTRL2_RG_H2E_PADDING_EN_OFFSET) + +#define RTL8373_RA_SLOT_TIME2_ADDR (0xE540) + #define RTL8373_RA_SLOT_TIME2_SLOT_TIME_OFFSET (0) + #define RTL8373_RA_SLOT_TIME2_SLOT_TIME_MASK (0xFFFF << RTL8373_RA_SLOT_TIME2_SLOT_TIME_OFFSET) + +#define RTL8373_RA_SOFT_RST2_ADDR (0xE544) + #define RTL8373_RA_SOFT_RST2_RST_OFFSET (0) + #define RTL8373_RA_SOFT_RST2_RST_MASK (0x1 << RTL8373_RA_SOFT_RST2_RST_OFFSET) + +#define RTL8373_RA_FIFO_FUL_THR3_ADDR (0xE6F0) + #define RTL8373_RA_FIFO_FUL_THR3_RXFIFO_FULL_TH_OFFSET (11) + #define RTL8373_RA_FIFO_FUL_THR3_RXFIFO_FULL_TH_MASK (0x7FF << RTL8373_RA_FIFO_FUL_THR3_RXFIFO_FULL_TH_OFFSET) + #define RTL8373_RA_FIFO_FUL_THR3_TXFIFO_FULL_TH_OFFSET (0) + #define RTL8373_RA_FIFO_FUL_THR3_TXFIFO_FULL_TH_MASK (0x7FF << RTL8373_RA_FIFO_FUL_THR3_TXFIFO_FULL_TH_OFFSET) + +#define RTL8373_RA_FIFO_EMPTY_THR3_ADDR (0xE6F4) + #define RTL8373_RA_FIFO_EMPTY_THR3_FIFO_EMPTY_TH_OFFSET (0) + #define RTL8373_RA_FIFO_EMPTY_THR3_FIFO_EMPTY_TH_MASK (0x7FF << RTL8373_RA_FIFO_EMPTY_THR3_FIFO_EMPTY_TH_OFFSET) + +#define RTL8373_RA_TX_STATUS3_ADDR (0xE6F8) + #define RTL8373_RA_TX_STATUS3_H2E_TX_STATUS_OFFSET (0) + #define RTL8373_RA_TX_STATUS3_H2E_TX_STATUS_MASK (0xFFFFFFFF << RTL8373_RA_TX_STATUS3_H2E_TX_STATUS_OFFSET) + +#define RTL8373_RA_RX_STATUS3_ADDR (0xE6FC) + #define RTL8373_RA_RX_STATUS3_H2E_RX_STATUS_OFFSET (0) + #define RTL8373_RA_RX_STATUS3_H2E_RX_STATUS_MASK (0xFFFFFFFF << RTL8373_RA_RX_STATUS3_H2E_RX_STATUS_OFFSET) + +#define RTL8373_RA_HSG_IFG3_ADDR (0xE700) + #define RTL8373_RA_HSG_IFG3_HSG_XGMI_RX_IFG_OFFSET (24) + #define RTL8373_RA_HSG_IFG3_HSG_XGMI_RX_IFG_MASK (0xFF << RTL8373_RA_HSG_IFG3_HSG_XGMI_RX_IFG_OFFSET) + #define RTL8373_RA_HSG_IFG3_HSG_XGMI_TX_IFG_OFFSET (16) + #define RTL8373_RA_HSG_IFG3_HSG_XGMI_TX_IFG_MASK (0xFF << RTL8373_RA_HSG_IFG3_HSG_XGMI_TX_IFG_OFFSET) + #define RTL8373_RA_HSG_IFG3_HSG_GMI_RX_IFG_OFFSET (8) + #define RTL8373_RA_HSG_IFG3_HSG_GMI_RX_IFG_MASK (0xFF << RTL8373_RA_HSG_IFG3_HSG_GMI_RX_IFG_OFFSET) + #define RTL8373_RA_HSG_IFG3_HSG_GMI_TX_IFG_OFFSET (0) + #define RTL8373_RA_HSG_IFG3_HSG_GMI_TX_IFG_MASK (0xFF << RTL8373_RA_HSG_IFG3_HSG_GMI_TX_IFG_OFFSET) + +#define RTL8373_RA_MACSEC_ETH3_ADDR(index) (0xE704 + (((index >> 1) << 2))) /* index: 0-7 */ + #define RTL8373_RA_MACSEC_ETH3_MACSEC_ETH_OFFSET(index) ((index & 0x1) << 4) + #define RTL8373_RA_MACSEC_ETH3_MACSEC_ETH_MASK(index) (0xFFFF << RTL8373_RA_MACSEC_ETH3_MACSEC_ETH_OFFSET(index)) + +#define RTL8373_RA_MACSEC_VLAN3_ADDR(index) (0xE714 + (((index >> 1) << 2))) /* index: 0-10 */ + #define RTL8373_RA_MACSEC_VLAN3_MACSEC_VLAN_OFFSET(index) ((index & 0x1) << 4) + #define RTL8373_RA_MACSEC_VLAN3_MACSEC_VLAN_MASK(index) (0xFFFF << RTL8373_RA_MACSEC_VLAN3_MACSEC_VLAN_OFFSET(index)) + +#define RTL8373_RA_MACSEC_IFG_CTRL3_ADDR (0xE72C) + #define RTL8373_RA_MACSEC_IFG_CTRL3_RG_H2E_MACSEC_IFG_EN_OFFSET (3) + #define RTL8373_RA_MACSEC_IFG_CTRL3_RG_H2E_MACSEC_IFG_EN_MASK (0x1 << RTL8373_RA_MACSEC_IFG_CTRL3_RG_H2E_MACSEC_IFG_EN_OFFSET) + #define RTL8373_RA_MACSEC_IFG_CTRL3_MACSEC_IFG_SEL_OFFSET (0) + #define RTL8373_RA_MACSEC_IFG_CTRL3_MACSEC_IFG_SEL_MASK (0x7 << RTL8373_RA_MACSEC_IFG_CTRL3_MACSEC_IFG_SEL_OFFSET) + +#define RTL8373_RA_PAUSE_CTRL3_ADDR (0xE730) + #define RTL8373_RA_PAUSE_CTRL3_RG_PAUSE_ACCEPT_MAC_SA_OFFSET (18) + #define RTL8373_RA_PAUSE_CTRL3_RG_PAUSE_ACCEPT_MAC_SA_MASK (0x1 << RTL8373_RA_PAUSE_CTRL3_RG_PAUSE_ACCEPT_MAC_SA_OFFSET) + #define RTL8373_RA_PAUSE_CTRL3_RG_SDS_PAUSE_DECT_EN_OFFSET (17) + #define RTL8373_RA_PAUSE_CTRL3_RG_SDS_PAUSE_DECT_EN_MASK (0x1 << RTL8373_RA_PAUSE_CTRL3_RG_SDS_PAUSE_DECT_EN_OFFSET) + #define RTL8373_RA_PAUSE_CTRL3_RG_ETH_PAUSE_DECT_EN_OFFSET (16) + #define RTL8373_RA_PAUSE_CTRL3_RG_ETH_PAUSE_DECT_EN_MASK (0x1 << RTL8373_RA_PAUSE_CTRL3_RG_ETH_PAUSE_DECT_EN_OFFSET) + #define RTL8373_RA_PAUSE_CTRL3_RG_H2E_MAC_SA_H_OFFSET (0) + #define RTL8373_RA_PAUSE_CTRL3_RG_H2E_MAC_SA_H_MASK (0xFFFF << RTL8373_RA_PAUSE_CTRL3_RG_H2E_MAC_SA_H_OFFSET) + #define RTL8373_RA_PAUSE_CTRL3_RG_H2E_MAC_SA_L_OFFSET (32) + #define RTL8373_RA_PAUSE_CTRL3_RG_H2E_MAC_SA_L_MASK (0xFFFFFFFF << RTL8373_RA_PAUSE_CTRL3_RG_H2E_MAC_SA_L_OFFSET) + +#define RTL8373_RA_GLB_CTRL3_ADDR (0xE738) + #define RTL8373_RA_GLB_CTRL3_RG_PRMB_NUM_OFFSET (2) + #define RTL8373_RA_GLB_CTRL3_RG_PRMB_NUM_MASK (0x7 << RTL8373_RA_GLB_CTRL3_RG_PRMB_NUM_OFFSET) + #define RTL8373_RA_GLB_CTRL3_RG_H2E_ENABLE_OFFSET (1) + #define RTL8373_RA_GLB_CTRL3_RG_H2E_ENABLE_MASK (0x1 << RTL8373_RA_GLB_CTRL3_RG_H2E_ENABLE_OFFSET) + #define RTL8373_RA_GLB_CTRL3_RG_H2E_BYPASS_MODE_OFFSET (0) + #define RTL8373_RA_GLB_CTRL3_RG_H2E_BYPASS_MODE_MASK (0x1 << RTL8373_RA_GLB_CTRL3_RG_H2E_BYPASS_MODE_OFFSET) + +#define RTL8373_RA_PADDING_CTRL3_ADDR (0xE73C) + #define RTL8373_RA_PADDING_CTRL3_RG_H2E_PADDING_VLAN_OFFSET (2) + #define RTL8373_RA_PADDING_CTRL3_RG_H2E_PADDING_VLAN_MASK (0x1 << RTL8373_RA_PADDING_CTRL3_RG_H2E_PADDING_VLAN_OFFSET) + #define RTL8373_RA_PADDING_CTRL3_RG_H2E_PADDING_MACSEC_OFFSET (1) + #define RTL8373_RA_PADDING_CTRL3_RG_H2E_PADDING_MACSEC_MASK (0x1 << RTL8373_RA_PADDING_CTRL3_RG_H2E_PADDING_MACSEC_OFFSET) + #define RTL8373_RA_PADDING_CTRL3_RG_H2E_PADDING_EN_OFFSET (0) + #define RTL8373_RA_PADDING_CTRL3_RG_H2E_PADDING_EN_MASK (0x1 << RTL8373_RA_PADDING_CTRL3_RG_H2E_PADDING_EN_OFFSET) + +#define RTL8373_RA_SLOT_TIME3_ADDR (0xE740) + #define RTL8373_RA_SLOT_TIME3_SLOT_TIME_OFFSET (0) + #define RTL8373_RA_SLOT_TIME3_SLOT_TIME_MASK (0xFFFF << RTL8373_RA_SLOT_TIME3_SLOT_TIME_OFFSET) + +#define RTL8373_RA_SOFT_RST3_ADDR (0xE744) + #define RTL8373_RA_SOFT_RST3_RST_OFFSET (0) + #define RTL8373_RA_SOFT_RST3_RST_MASK (0x1 << RTL8373_RA_SOFT_RST3_RST_OFFSET) + +/* + * Feature: NIC + */ +#define RTL8373_NIC_BUFFSIZE_CTRL_ADDR (0x7844) + #define RTL8373_NIC_BUFFSIZE_CTRL_TXSTOP_ADDR_OFFSET (0) + #define RTL8373_NIC_BUFFSIZE_CTRL_TXSTOP_ADDR_MASK (0x7FF << RTL8373_NIC_BUFFSIZE_CTRL_TXSTOP_ADDR_OFFSET) + +#define RTL8373_NIC_RXBUFF_CTRL_ADDR (0x7848) + #define RTL8373_NIC_RXBUFF_CTRL_RXSTOP_ADDR_OFFSET (0) + #define RTL8373_NIC_RXBUFF_CTRL_RXSTOP_ADDR_MASK (0x7FF << RTL8373_NIC_RXBUFF_CTRL_RXSTOP_ADDR_OFFSET) + +#define RTL8373_NIC_RXCMD_ADDR (0x784C) + #define RTL8373_NIC_RXCMD_FLAG_OFFSET (0) + #define RTL8373_NIC_RXCMD_FLAG_MASK (0x1 << RTL8373_NIC_RXCMD_FLAG_OFFSET) + +#define RTL8373_NIC_TXCMD_ADDR (0x7850) + #define RTL8373_NIC_TXCMD_FLAG_OFFSET (0) + #define RTL8373_NIC_TXCMD_FLAG_MASK (0x1 << RTL8373_NIC_TXCMD_FLAG_OFFSET) + +#define RTL8373_NIC_INT_STS_ADDR (0x7854) + #define RTL8373_NIC_INT_STS_RXIS_OFFSET (1) + #define RTL8373_NIC_INT_STS_RXIS_MASK (0x1 << RTL8373_NIC_INT_STS_RXIS_OFFSET) + #define RTL8373_NIC_INT_STS_TXES_OFFSET (0) + #define RTL8373_NIC_INT_STS_TXES_MASK (0x1 << RTL8373_NIC_INT_STS_TXES_OFFSET) + +#define RTL8373_NIC_INT_MSK_ADDR (0x7858) + #define RTL8373_NIC_INT_MSK_RXIE_OFFSET (1) + #define RTL8373_NIC_INT_MSK_RXIE_MASK (0x1 << RTL8373_NIC_INT_MSK_RXIE_OFFSET) + #define RTL8373_NIC_INT_MSK_TXEE_OFFSET (0) + #define RTL8373_NIC_INT_MSK_TXEE_MASK (0x1 << RTL8373_NIC_INT_MSK_TXEE_OFFSET) + +#define RTL8373_NIC_RX_CTRL_ADDR (0x785C) + #define RTL8373_NIC_RX_CTRL_RXFST_OFFSET (24) + #define RTL8373_NIC_RX_CTRL_RXFST_MASK (0xFF << RTL8373_NIC_RX_CTRL_RXFST_OFFSET) + #define RTL8373_NIC_RX_CTRL_RXPAD_OFFSET (18) + #define RTL8373_NIC_RX_CTRL_RXPAD_MASK (0x1 << RTL8373_NIC_RX_CTRL_RXPAD_OFFSET) + #define RTL8373_NIC_RX_CTRL_RXMTU_OFFSET (16) + #define RTL8373_NIC_RX_CTRL_RXMTU_MASK (0x3 << RTL8373_NIC_RX_CTRL_RXMTU_OFFSET) + #define RTL8373_NIC_RX_CTRL_HFMPE_OFFSET (15) + #define RTL8373_NIC_RX_CTRL_HFMPE_MASK (0x1 << RTL8373_NIC_RX_CTRL_HFMPE_OFFSET) + #define RTL8373_NIC_RX_CTRL_HFPPE_OFFSET (14) + #define RTL8373_NIC_RX_CTRL_HFPPE_MASK (0x1 << RTL8373_NIC_RX_CTRL_HFPPE_OFFSET) + #define RTL8373_NIC_RX_CTRL_RXAPE_OFFSET (13) + #define RTL8373_NIC_RX_CTRL_RXAPE_MASK (0x1 << RTL8373_NIC_RX_CTRL_RXAPE_OFFSET) + #define RTL8373_NIC_RX_CTRL_ARPPE_OFFSET (12) + #define RTL8373_NIC_RX_CTRL_ARPPE_MASK (0x1 << RTL8373_NIC_RX_CTRL_ARPPE_OFFSET) + #define RTL8373_NIC_RX_CTRL_RXBPE_OFFSET (11) + #define RTL8373_NIC_RX_CTRL_RXBPE_MASK (0x1 << RTL8373_NIC_RX_CTRL_RXBPE_OFFSET) + #define RTL8373_NIC_RX_CTRL_RXMPE_OFFSET (10) + #define RTL8373_NIC_RX_CTRL_RXMPE_MASK (0x1 << RTL8373_NIC_RX_CTRL_RXMPE_OFFSET) + #define RTL8373_NIC_RX_CTRL_RXPPS_OFFSET (8) + #define RTL8373_NIC_RX_CTRL_RXPPS_MASK (0x3 << RTL8373_NIC_RX_CTRL_RXPPS_OFFSET) + #define RTL8373_NIC_RX_CTRL_RL4CEPE_OFFSET (4) + #define RTL8373_NIC_RX_CTRL_RL4CEPE_MASK (0x1 << RTL8373_NIC_RX_CTRL_RL4CEPE_OFFSET) + #define RTL8373_NIC_RX_CTRL_RL3CEPE_OFFSET (3) + #define RTL8373_NIC_RX_CTRL_RL3CEPE_MASK (0x1 << RTL8373_NIC_RX_CTRL_RL3CEPE_OFFSET) + #define RTL8373_NIC_RX_CTRL_RCRCEPE_OFFSET (2) + #define RTL8373_NIC_RX_CTRL_RCRCEPE_MASK (0x1 << RTL8373_NIC_RX_CTRL_RCRCEPE_OFFSET) + #define RTL8373_NIC_RX_CTRL_RMCRC_EN_OFFSET (1) + #define RTL8373_NIC_RX_CTRL_RMCRC_EN_MASK (0x1 << RTL8373_NIC_RX_CTRL_RMCRC_EN_OFFSET) + #define RTL8373_NIC_RX_CTRL_RX_EN_OFFSET (0) + #define RTL8373_NIC_RX_CTRL_RX_EN_MASK (0x1 << RTL8373_NIC_RX_CTRL_RX_EN_OFFSET) + +#define RTL8373_NIC_TX_CTRL_ADDR (0x7860) + #define RTL8373_NIC_TX_CTRL_LOOPBACK_EN_OFFSET (1) + #define RTL8373_NIC_TX_CTRL_LOOPBACK_EN_MASK (0x1 << RTL8373_NIC_TX_CTRL_LOOPBACK_EN_OFFSET) + #define RTL8373_NIC_TX_CTRL_TX_EN_OFFSET (0) + #define RTL8373_NIC_TX_CTRL_TX_EN_MASK (0x1 << RTL8373_NIC_TX_CTRL_TX_EN_OFFSET) + +#define RTL8373_NIC_MC_HASH_TBL_ADDR(index) (0x7864 + (((index >> 5) << 2))) /* index: 0-63 */ + #define RTL8373_NIC_MC_HASH_TBL_HF_VAL_OFFSET(index) (index % 0x20) + #define RTL8373_NIC_MC_HASH_TBL_HF_VAL_MASK(index) (0x1 << RTL8373_NIC_MC_HASH_TBL_HF_VAL_OFFSET(index)) + +#define RTL8373_NIC_UC_HASH_TBL_ADDR(index) (0x786C + (((index >> 5) << 2))) /* index: 0-63 */ + #define RTL8373_NIC_UC_HASH_TBL_HF_VAL_OFFSET(index) (index % 0x20) + #define RTL8373_NIC_UC_HASH_TBL_HF_VAL_MASK(index) (0x1 << RTL8373_NIC_UC_HASH_TBL_HF_VAL_OFFSET(index)) + +#define RTL8373_NIC_RX_BUFF_DATA_ADDR (0x7874) + #define RTL8373_NIC_RX_BUFF_DATA_LEN_OFFSET (0) + #define RTL8373_NIC_RX_BUFF_DATA_LEN_MASK (0x3FFF << RTL8373_NIC_RX_BUFF_DATA_LEN_OFFSET) + +#define RTL8373_NIC_RX_CURR_PKT_ADDR (0x7878) + #define RTL8373_NIC_RX_CURR_PKT_ADDR_OFFSET (0) + #define RTL8373_NIC_RX_CURR_PKT_ADDR_MASK (0x7FF << RTL8373_NIC_RX_CURR_PKT_ADDR_OFFSET) + +#define RTL8373_CPU_RX_CURR_PKT_ADDR (0x787C) + #define RTL8373_CPU_RX_CURR_PKT_ADDR_OFFSET (0) + #define RTL8373_CPU_RX_CURR_PKT_ADDR_MASK (0x7FF << RTL8373_CPU_RX_CURR_PKT_ADDR_OFFSET) + +#define RTL8373_NIC_TX_BUFF_AVAIL_ADDR (0x7880) + #define RTL8373_NIC_TX_BUFF_AVAIL_FREE_SPACE_OFFSET (0) + #define RTL8373_NIC_TX_BUFF_AVAIL_FREE_SPACE_MASK (0x7FF << RTL8373_NIC_TX_BUFF_AVAIL_FREE_SPACE_OFFSET) + +#define RTL8373_NIC_TX_CURR_PKT_ADDR (0x7884) + #define RTL8373_NIC_TX_CURR_PKT_ADDR_OFFSET (0) + #define RTL8373_NIC_TX_CURR_PKT_ADDR_MASK (0x7FF << RTL8373_NIC_TX_CURR_PKT_ADDR_OFFSET) + +#define RTL8373_NIC_TX_CURR_UNIT_ADDR (0x7888) + #define RTL8373_NIC_TX_CURR_UNIT_ADDR_OFFSET (0) + #define RTL8373_NIC_TX_CURR_UNIT_ADDR_MASK (0x7FF << RTL8373_NIC_TX_CURR_UNIT_ADDR_OFFSET) + +#define RTL8373_NIC_TX_PKT_INFO_ADDR (0x788C) + #define RTL8373_NIC_TX_PKT_INFO_LEN_OFFSET (0) + #define RTL8373_NIC_TX_PKT_INFO_LEN_MASK (0x3FFF << RTL8373_NIC_TX_PKT_INFO_LEN_OFFSET) + +#define RTL8373_CPU_TX_CURR_PKT_ADDR (0x7890) + #define RTL8373_CPU_TX_CURR_PKT_ADDR_OFFSET (0) + #define RTL8373_CPU_TX_CURR_PKT_ADDR_MASK (0x7FF << RTL8373_CPU_TX_CURR_PKT_ADDR_OFFSET) + +#define RTL8373_DMY_REG0_NIC_ADDR (0x7894) + #define RTL8373_DMY_REG0_NIC_DUMMY_REG0_NIC_OFFSET (0) + #define RTL8373_DMY_REG0_NIC_DUMMY_REG0_NIC_MASK (0xFFFFFFFF << RTL8373_DMY_REG0_NIC_DUMMY_REG0_NIC_OFFSET) + +#define RTL8373_DMY_REG1_NIC_ADDR (0x7898) + #define RTL8373_DMY_REG1_NIC_DUMMY_REG1_NIC_OFFSET (0) + #define RTL8373_DMY_REG1_NIC_DUMMY_REG1_NIC_MASK (0xFFFFFFFF << RTL8373_DMY_REG1_NIC_DUMMY_REG1_NIC_OFFSET) + +/* + * Feature: Cpu Tag + */ +#define RTL8373_CPU_TAG_TPID_CTRL_ADDR (0x6038) + #define RTL8373_CPU_TAG_TPID_CTRL_TPID_OFFSET (0) + #define RTL8373_CPU_TAG_TPID_CTRL_TPID_MASK (0xFFFF << RTL8373_CPU_TAG_TPID_CTRL_TPID_OFFSET) + +#define RTL8373_CPU_TAG_CTRL_ADDR (0x6720) + #define RTL8373_CPU_TAG_CTRL_EXT_CPUTAG_INSERTMOD_OFFSET (10) + #define RTL8373_CPU_TAG_CTRL_EXT_CPUTAG_INSERTMOD_MASK (0x3 << RTL8373_CPU_TAG_CTRL_EXT_CPUTAG_INSERTMOD_OFFSET) + #define RTL8373_CPU_TAG_CTRL_INT_CPUTAG_INSERTMOD_OFFSET (8) + #define RTL8373_CPU_TAG_CTRL_INT_CPUTAG_INSERTMOD_MASK (0x3 << RTL8373_CPU_TAG_CTRL_INT_CPUTAG_INSERTMOD_OFFSET) + #define RTL8373_CPU_TAG_CTRL_EXT_CPUTAG_EN_OFFSET (1) + #define RTL8373_CPU_TAG_CTRL_EXT_CPUTAG_EN_MASK (0x1 << RTL8373_CPU_TAG_CTRL_EXT_CPUTAG_EN_OFFSET) + #define RTL8373_CPU_TAG_CTRL_INT_CPUTAG_EN_OFFSET (0) + #define RTL8373_CPU_TAG_CTRL_INT_CPUTAG_EN_MASK (0x1 << RTL8373_CPU_TAG_CTRL_INT_CPUTAG_EN_OFFSET) + +#define RTL8373_EXT_CPU_CTRL_ADDR (0x6724) + #define RTL8373_EXT_CPU_CTRL_PORT_OFFSET (0) + #define RTL8373_EXT_CPU_CTRL_PORT_MASK (0xF << RTL8373_EXT_CPU_CTRL_PORT_OFFSET) + +#define RTL8373_CPU_TAG_AWARE_CTRL_ADDR (0x603C) + #define RTL8373_CPU_TAG_AWARE_CTRL_PMSK_OFFSET (0) + #define RTL8373_CPU_TAG_AWARE_CTRL_PMSK_MASK (0x3FF << RTL8373_CPU_TAG_AWARE_CTRL_PMSK_OFFSET) + +/* + * Feature: Table Access + */ +#define RTL8373_ITA_CTRL0_ADDR (0x5CAC) + #define RTL8373_ITA_CTRL0_TBL_ADDR_OFFSET (16) + #define RTL8373_ITA_CTRL0_TBL_ADDR_MASK (0x1FFF << RTL8373_ITA_CTRL0_TBL_ADDR_OFFSET) + #define RTL8373_ITA_CTRL0_TLB_TYPE_OFFSET (8) + #define RTL8373_ITA_CTRL0_TLB_TYPE_MASK (0x7 << RTL8373_ITA_CTRL0_TLB_TYPE_OFFSET) + #define RTL8373_ITA_CTRL0_TLB_ACT_OFFSET (1) + #define RTL8373_ITA_CTRL0_TLB_ACT_MASK (0x1 << RTL8373_ITA_CTRL0_TLB_ACT_OFFSET) + #define RTL8373_ITA_CTRL0_TLB_EXECUTE_OFFSET (0) + #define RTL8373_ITA_CTRL0_TLB_EXECUTE_MASK (0x1 << RTL8373_ITA_CTRL0_TLB_EXECUTE_OFFSET) + +#define RTL8373_ITA_L2_CTRL_ADDR (0x5CB0) + #define RTL8373_ITA_L2_CTRL_PORT_NUM_OFFSET (19) + #define RTL8373_ITA_L2_CTRL_PORT_NUM_MASK (0xF << RTL8373_ITA_L2_CTRL_PORT_NUM_OFFSET) + #define RTL8373_ITA_L2_CTRL_ENTRY_CLR_OFFSET (18) + #define RTL8373_ITA_L2_CTRL_ENTRY_CLR_MASK (0x1 << RTL8373_ITA_L2_CTRL_ENTRY_CLR_OFFSET) + #define RTL8373_ITA_L2_CTRL_READ_MTHD_OFFSET (14) + #define RTL8373_ITA_L2_CTRL_READ_MTHD_MASK (0xF << RTL8373_ITA_L2_CTRL_READ_MTHD_OFFSET) + #define RTL8373_ITA_L2_CTRL_TBL_TYPE_OFFSET (13) + #define RTL8373_ITA_L2_CTRL_TBL_TYPE_MASK (0x1 << RTL8373_ITA_L2_CTRL_TBL_TYPE_OFFSET) + #define RTL8373_ITA_L2_CTRL_ACT_STS_OFFSET (12) + #define RTL8373_ITA_L2_CTRL_ACT_STS_MASK (0x1 << RTL8373_ITA_L2_CTRL_ACT_STS_OFFSET) + #define RTL8373_ITA_L2_CTRL_TBL_ADDR_OFFSET (0) + #define RTL8373_ITA_L2_CTRL_TBL_ADDR_MASK (0xFFF << RTL8373_ITA_L2_CTRL_TBL_ADDR_OFFSET) + +#define RTL8373_ITA_HSAB_CTRL_ADDR (0x5CB4) + #define RTL8373_ITA_HSAB_CTRL_LATCH_ALWAYS_OFFSET (16) + #define RTL8373_ITA_HSAB_CTRL_LATCH_ALWAYS_MASK (0x1 << RTL8373_ITA_HSAB_CTRL_LATCH_ALWAYS_OFFSET) + #define RTL8373_ITA_HSAB_CTRL_LATCH_FIRST_OFFSET (15) + #define RTL8373_ITA_HSAB_CTRL_LATCH_FIRST_MASK (0x1 << RTL8373_ITA_HSAB_CTRL_LATCH_FIRST_OFFSET) + #define RTL8373_ITA_HSAB_CTRL_SPA_EN_OFFSET (14) + #define RTL8373_ITA_HSAB_CTRL_SPA_EN_MASK (0x1 << RTL8373_ITA_HSAB_CTRL_SPA_EN_OFFSET) + #define RTL8373_ITA_HSAB_CTRL_FORWARD_EN_OFFSET (13) + #define RTL8373_ITA_HSAB_CTRL_FORWARD_EN_MASK (0x1 << RTL8373_ITA_HSAB_CTRL_FORWARD_EN_OFFSET) + #define RTL8373_ITA_HSAB_CTRL_REASON_EN_OFFSET (12) + #define RTL8373_ITA_HSAB_CTRL_REASON_EN_MASK (0x1 << RTL8373_ITA_HSAB_CTRL_REASON_EN_OFFSET) + #define RTL8373_ITA_HSAB_CTRL_SPA_OFFSET (8) + #define RTL8373_ITA_HSAB_CTRL_SPA_MASK (0xF << RTL8373_ITA_HSAB_CTRL_SPA_OFFSET) + #define RTL8373_ITA_HSAB_CTRL_FORWARD_OFFSET (6) + #define RTL8373_ITA_HSAB_CTRL_FORWARD_MASK (0x3 << RTL8373_ITA_HSAB_CTRL_FORWARD_OFFSET) + #define RTL8373_ITA_HSAB_CTRL_REASON_OFFSET (0) + #define RTL8373_ITA_HSAB_CTRL_REASON_MASK (0x3F << RTL8373_ITA_HSAB_CTRL_REASON_OFFSET) + +#define RTL8373_ITA_WRITE_DATA0_ADDR(index) (0x5CB8 + (((index) << 2))) /* index: 0-4 */ + #define RTL8373_ITA_WRITE_DATA0_WRITE_DATA_OFFSET (0) + #define RTL8373_ITA_WRITE_DATA0_WRITE_DATA_MASK (0xFFFFFFFF << RTL8373_ITA_WRITE_DATA0_WRITE_DATA_OFFSET) + +#define RTL8373_ITA_READ_DATA0_ADDR(index) (0x5CCC + (((index) << 2))) /* index: 0-4 */ + #define RTL8373_ITA_READ_DATA0_READ_DATA_OFFSET (0) + #define RTL8373_ITA_READ_DATA0_READ_DATA_MASK (0xFFFFFFFF << RTL8373_ITA_READ_DATA0_READ_DATA_OFFSET) + +#define RTL8373_TEST_MODE_ALE_HSA_MULTI_CTRL_ADDR (0x4444) + #define RTL8373_TEST_MODE_ALE_HSA_MULTI_CTRL_CNT_OFFSET (2) + #define RTL8373_TEST_MODE_ALE_HSA_MULTI_CTRL_CNT_MASK (0x7FF << RTL8373_TEST_MODE_ALE_HSA_MULTI_CTRL_CNT_OFFSET) + #define RTL8373_TEST_MODE_ALE_HSA_MULTI_CTRL_CNT_RST_OFFSET (1) + #define RTL8373_TEST_MODE_ALE_HSA_MULTI_CTRL_CNT_RST_MASK (0x1 << RTL8373_TEST_MODE_ALE_HSA_MULTI_CTRL_CNT_RST_OFFSET) + #define RTL8373_TEST_MODE_ALE_HSA_MULTI_CTRL_EN_OFFSET (0) + #define RTL8373_TEST_MODE_ALE_HSA_MULTI_CTRL_EN_MASK (0x1 << RTL8373_TEST_MODE_ALE_HSA_MULTI_CTRL_EN_OFFSET) + +#define RTL8373_TBL_ACCESS_HSA_CTRL_ADDR (0x4448) + #define RTL8373_TBL_ACCESS_HSA_CTRL_EXEC_OFFSET (13) + #define RTL8373_TBL_ACCESS_HSA_CTRL_EXEC_MASK (0x1 << RTL8373_TBL_ACCESS_HSA_CTRL_EXEC_OFFSET) + #define RTL8373_TBL_ACCESS_HSA_CTRL_CMD_OFFSET (12) + #define RTL8373_TBL_ACCESS_HSA_CTRL_CMD_MASK (0x1 << RTL8373_TBL_ACCESS_HSA_CTRL_CMD_OFFSET) + #define RTL8373_TBL_ACCESS_HSA_CTRL_TBL_OFFSET (11) + #define RTL8373_TBL_ACCESS_HSA_CTRL_TBL_MASK (0x1 << RTL8373_TBL_ACCESS_HSA_CTRL_TBL_OFFSET) + #define RTL8373_TBL_ACCESS_HSA_CTRL_ADDR_OFFSET (0) + #define RTL8373_TBL_ACCESS_HSA_CTRL_ADDR_MASK (0x7FF << RTL8373_TBL_ACCESS_HSA_CTRL_ADDR_OFFSET) + +#define RTL8373_TBL_ACCESS_HSA_DATA_ADDR(index) (0x444C + (((index) << 2))) /* index: 0-9 */ + #define RTL8373_TBL_ACCESS_HSA_DATA_DATA_OFFSET (0) + #define RTL8373_TBL_ACCESS_HSA_DATA_DATA_MASK (0xFFFFFFFF << RTL8373_TBL_ACCESS_HSA_DATA_DATA_OFFSET) + +/* + * Feature: 8051 + */ +#define RTL8373_DW8051_CFG_ADDR (0x6040) + #define RTL8373_DW8051_CFG_NIC_EN_OFFSET (12) + #define RTL8373_DW8051_CFG_NIC_EN_MASK (0x1 << RTL8373_DW8051_CFG_NIC_EN_OFFSET) + #define RTL8373_DW8051_CFG_CPUIDL_EXT_OFFSET (11) + #define RTL8373_DW8051_CFG_CPUIDL_EXT_MASK (0x1 << RTL8373_DW8051_CFG_CPUIDL_EXT_OFFSET) + #define RTL8373_DW8051_CFG_CPUIDL_ENR_OFFSET (10) + #define RTL8373_DW8051_CFG_CPUIDL_ENR_MASK (0x1 << RTL8373_DW8051_CFG_CPUIDL_ENR_OFFSET) + #define RTL8373_DW8051_CFG_VIAROM_WRITE_EN_OFFSET (9) + #define RTL8373_DW8051_CFG_VIAROM_WRITE_EN_MASK (0x1 << RTL8373_DW8051_CFG_VIAROM_WRITE_EN_OFFSET) + #define RTL8373_DW8051_CFG_SPIF_CK2_OFFSET (8) + #define RTL8373_DW8051_CFG_SPIF_CK2_MASK (0x1 << RTL8373_DW8051_CFG_SPIF_CK2_OFFSET) + #define RTL8373_DW8051_CFG_RRCP_MDOE_OFFSET (7) + #define RTL8373_DW8051_CFG_RRCP_MDOE_MASK (0x1 << RTL8373_DW8051_CFG_RRCP_MDOE_OFFSET) + #define RTL8373_DW8051_CFG_DW8051_RATE_OFFSET (4) + #define RTL8373_DW8051_CFG_DW8051_RATE_MASK (0x3 << RTL8373_DW8051_CFG_DW8051_RATE_OFFSET) + #define RTL8373_DW8051_CFG_IROM_MSB_OFFSET (2) + #define RTL8373_DW8051_CFG_IROM_MSB_MASK (0x3 << RTL8373_DW8051_CFG_IROM_MSB_OFFSET) + #define RTL8373_DW8051_CFG_ACS_IROM_ENABLE_OFFSET (1) + #define RTL8373_DW8051_CFG_ACS_IROM_ENABLE_MASK (0x1 << RTL8373_DW8051_CFG_ACS_IROM_ENABLE_OFFSET) + #define RTL8373_DW8051_CFG_DW8051_READY_OFFSET (0) + #define RTL8373_DW8051_CFG_DW8051_READY_MASK (0x1 << RTL8373_DW8051_CFG_DW8051_READY_OFFSET) + +#define RTL8373_DW8051_IROM_ADDR(index) (0x80B0 + (((index) << 2))) /* index: 0-4095 */ + #define RTL8373_DW8051_IROM_IROM_DATA_OFFSET (0) + #define RTL8373_DW8051_IROM_IROM_DATA_MASK (0xFF << RTL8373_DW8051_IROM_IROM_DATA_OFFSET) + +/* + * Feature: 802.1Q VLAN + */ +#define RTL8373_VLAN_PORT_AFT_ADDR(port) (0x4E10 + (((port / 10) << 2))) /* port: 0-9 */ + #define RTL8373_VLAN_PORT_AFT_CTAG_ACCEPT_TYPE_OFFSET(port) ((port % 0xA) << 1) + #define RTL8373_VLAN_PORT_AFT_CTAG_ACCEPT_TYPE_MASK(port) (0x3 << RTL8373_VLAN_PORT_AFT_CTAG_ACCEPT_TYPE_OFFSET(port)) + +#define RTL8373_VLAN_CTRL_ADDR (0x4E14) + #define RTL8373_VLAN_CTRL_TABLE_RST_OFFSET (3) + #define RTL8373_VLAN_CTRL_TABLE_RST_MASK (0x1 << RTL8373_VLAN_CTRL_TABLE_RST_OFFSET) + #define RTL8373_VLAN_CTRL_CVLAN_FILTER_OFFSET (2) + #define RTL8373_VLAN_CTRL_CVLAN_FILTER_MASK (0x1 << RTL8373_VLAN_CTRL_CVLAN_FILTER_OFFSET) + #define RTL8373_VLAN_CTRL_VID4095_TYPE_OFFSET (1) + #define RTL8373_VLAN_CTRL_VID4095_TYPE_MASK (0x1 << RTL8373_VLAN_CTRL_VID4095_TYPE_OFFSET) + #define RTL8373_VLAN_CTRL_VID0_TYPE_OFFSET (0) + #define RTL8373_VLAN_CTRL_VID0_TYPE_MASK (0x1 << RTL8373_VLAN_CTRL_VID0_TYPE_OFFSET) + +#define RTL8373_VLAN_PORT_IGR_FLTR_ADDR(port) (0x4E18 + (((port / 10) << 2))) /* port: 0-9 */ + #define RTL8373_VLAN_PORT_IGR_FLTR_IGR_FLTR_ACT_OFFSET(port) (port % 0xA) + #define RTL8373_VLAN_PORT_IGR_FLTR_IGR_FLTR_ACT_MASK(port) (0x1 << RTL8373_VLAN_PORT_IGR_FLTR_IGR_FLTR_ACT_OFFSET(port)) + +#define RTL8373_VLAN_PORT_PB_VLAN_ADDR(port) (0x4E1C + (((port >> 1) << 2))) /* port: 0-9 */ + #define RTL8373_VLAN_PORT_PB_VLAN_PVID_OFFSET(port) ((port & 0x1) * 12) + #define RTL8373_VLAN_PORT_PB_VLAN_PVID_MASK(port) (0xFFF << RTL8373_VLAN_PORT_PB_VLAN_PVID_OFFSET(port)) + +#define RTL8373_VLAN_PORT_EGR_TRANS_ADDR(port) (0x4EB8 + (((port / 3) << 2))) /* port: 0-9 */ + #define RTL8373_VLAN_PORT_EGR_TRANS_PMSK_OFFSET(port) ((port % 0x3) * 10) + #define RTL8373_VLAN_PORT_EGR_TRANS_PMSK_MASK(port) (0x3FF << RTL8373_VLAN_PORT_EGR_TRANS_PMSK_OFFSET(port)) + +#define RTL8373_VLAN_PORT_EGR_KEEP_ADDR(port) (0x6728 + (((port / 3) << 2))) /* port: 0-9 */ + #define RTL8373_VLAN_PORT_EGR_KEEP_PMSK_OFFSET(port) ((port % 0x3) * 10) + #define RTL8373_VLAN_PORT_EGR_KEEP_PMSK_MASK(port) (0x3FF << RTL8373_VLAN_PORT_EGR_KEEP_PMSK_OFFSET(port)) + +#define RTL8373_VLAN_PORT_EGR_TAG_ADDR(port) (0x6738 + (((port / 10) << 2))) /* port: 0-9 */ + #define RTL8373_VLAN_PORT_EGR_TAG_MODE_OFFSET(port) ((port % 0xA) << 1) + #define RTL8373_VLAN_PORT_EGR_TAG_MODE_MASK(port) (0x3 << RTL8373_VLAN_PORT_EGR_TAG_MODE_OFFSET(port)) + +#define RTL8373_VLAN_L2_LRN_DIS_ADDR(index) (0x4E30 + (((index) << 2))) /* index: 0-1 */ + #define RTL8373_VLAN_L2_LRN_DIS_ACT_OFFSET (13) + #define RTL8373_VLAN_L2_LRN_DIS_ACT_MASK (0x1 << RTL8373_VLAN_L2_LRN_DIS_ACT_OFFSET) + #define RTL8373_VLAN_L2_LRN_DIS_VID_OFFSET (1) + #define RTL8373_VLAN_L2_LRN_DIS_VID_MASK (0xFFF << RTL8373_VLAN_L2_LRN_DIS_VID_OFFSET) + #define RTL8373_VLAN_L2_LRN_DIS_VALID_OFFSET (0) + #define RTL8373_VLAN_L2_LRN_DIS_VALID_MASK (0x1 << RTL8373_VLAN_L2_LRN_DIS_VALID_OFFSET) + +#define RTL8373_PORT_BASED_FID_EN_ADDR (0x4E38) + #define RTL8373_PORT_BASED_FID_EN_PMSK_OFFSET (0) + #define RTL8373_PORT_BASED_FID_EN_PMSK_MASK (0x3FF << RTL8373_PORT_BASED_FID_EN_PMSK_OFFSET) + +#define RTL8373_PORT_BASED_FID_ADDR(port) (0x4E3C + (((port >> 3) << 2))) /* port: 0-9 */ + #define RTL8373_PORT_BASED_FID_FID_OFFSET(port) ((port & 0x7) << 2) + #define RTL8373_PORT_BASED_FID_FID_MASK(port) (0xF << RTL8373_PORT_BASED_FID_FID_OFFSET(port)) + +#define RTL8373_VLAN_TAG_PRI_CFG_ADDR (0x673C) + #define RTL8373_VLAN_TAG_PRI_CFG_RMK1P_BYPASS_REALKEEP_OFFSET (0) + #define RTL8373_VLAN_TAG_PRI_CFG_RMK1P_BYPASS_REALKEEP_MASK (0x1 << RTL8373_VLAN_TAG_PRI_CFG_RMK1P_BYPASS_REALKEEP_OFFSET) + +/* + * Feature: 802.1D SVLAN + */ +#define RTL8373_VS_GLB_CTRL_ADDR (0x6044) + #define RTL8373_VS_GLB_CTRL_VS_TPID_OFFSET (0) + #define RTL8373_VS_GLB_CTRL_VS_TPID_MASK (0xFFFF << RTL8373_VS_GLB_CTRL_VS_TPID_OFFSET) + +#define RTL8373_VS_UPLINK_PORT_ADDR (0x57C0) + #define RTL8373_VS_UPLINK_PORT_MSK_OFFSET (0) + #define RTL8373_VS_UPLINK_PORT_MSK_MASK (0x3FF << RTL8373_VS_UPLINK_PORT_MSK_OFFSET) + +#define RTL8373_VS_CTRL_ADDR (0x57C4) + #define RTL8373_VS_CTRL_SPRISEL_OFFSET (3) + #define RTL8373_VS_CTRL_SPRISEL_MASK (0x3 << RTL8373_VS_CTRL_SPRISEL_OFFSET) + #define RTL8373_VS_CTRL_UIFSEG_OFFSET (2) + #define RTL8373_VS_CTRL_UIFSEG_MASK (0x1 << RTL8373_VS_CTRL_UIFSEG_OFFSET) + #define RTL8373_VS_CTRL_UNTAG_OFFSET (0) + #define RTL8373_VS_CTRL_UNTAG_MASK (0x3 << RTL8373_VS_CTRL_UNTAG_OFFSET) + +#define RTL8373_VS_UNTAG_SVID_ADDR (0x57C8) + #define RTL8373_VS_UNTAG_SVID_UNTAG_SVID_OFFSET (0) + #define RTL8373_VS_UNTAG_SVID_UNTAG_SVID_MASK (0xFFF << RTL8373_VS_UNTAG_SVID_UNTAG_SVID_OFFSET) + +#define RTL8373_VS_PORT_DFLT_SVID_ADDR(port) (0x57CC + (((port >> 1) << 2))) /* port: 0-9 */ + #define RTL8373_VS_PORT_DFLT_SVID_PORT_DFLT_SVID_OFFSET(port) ((port & 0x1) * 12) + #define RTL8373_VS_PORT_DFLT_SVID_PORT_DFLT_SVID_MASK(port) (0xFFF << RTL8373_VS_PORT_DFLT_SVID_PORT_DFLT_SVID_OFFSET(port)) + +#define RTL8373_SVLAN_TRAP_CTRL_ADDR (0x4EC8) + #define RTL8373_SVLAN_TRAP_CTRL_CPU_PMSK_OFFSET (16) + #define RTL8373_SVLAN_TRAP_CTRL_CPU_PMSK_MASK (0x3 << RTL8373_SVLAN_TRAP_CTRL_CPU_PMSK_OFFSET) + #define RTL8373_SVLAN_TRAP_CTRL_PRI_OFFSET (0) + #define RTL8373_SVLAN_TRAP_CTRL_PRI_MASK (0x7 << RTL8373_SVLAN_TRAP_CTRL_PRI_OFFSET) + +/* + * Feature: C2S Table + */ +#define RTL8373_VLAN_C2S_ENTRY_ADDR(index) (0x57E0 + (((index) << 3))) /* index: 0-127 */ + #define RTL8373_VLAN_C2S_ENTRY_SVID_ASSIGN_OFFSET (0) + #define RTL8373_VLAN_C2S_ENTRY_SVID_ASSIGN_MASK (0xFFF << RTL8373_VLAN_C2S_ENTRY_SVID_ASSIGN_OFFSET) + #define RTL8373_VLAN_C2S_ENTRY_CVID_OFFSET (42) + #define RTL8373_VLAN_C2S_ENTRY_CVID_MASK (0xFFF << RTL8373_VLAN_C2S_ENTRY_CVID_OFFSET) + #define RTL8373_VLAN_C2S_ENTRY_PMSK_EN_OFFSET (32) + #define RTL8373_VLAN_C2S_ENTRY_PMSK_EN_MASK (0x3FF << RTL8373_VLAN_C2S_ENTRY_PMSK_EN_OFFSET) + +/* + * Feature: RMA + */ +#define RTL8373_RMA_OP_CTRL_00_ADDR (0x4ECC) + #define RTL8373_RMA_OP_CTRL_00_RMA_ACT_00_OFFSET (4) + #define RTL8373_RMA_OP_CTRL_00_RMA_ACT_00_MASK (0x3 << RTL8373_RMA_OP_CTRL_00_RMA_ACT_00_OFFSET) + #define RTL8373_RMA_OP_CTRL_00_DIS_STORM_CTRL_00_OFFSET (3) + #define RTL8373_RMA_OP_CTRL_00_DIS_STORM_CTRL_00_MASK (0x1 << RTL8373_RMA_OP_CTRL_00_DIS_STORM_CTRL_00_OFFSET) + #define RTL8373_RMA_OP_CTRL_00_CKEEP_00_OFFSET (2) + #define RTL8373_RMA_OP_CTRL_00_CKEEP_00_MASK (0x1 << RTL8373_RMA_OP_CTRL_00_CKEEP_00_OFFSET) + #define RTL8373_RMA_OP_CTRL_00_VLAN_LEAKY_00_OFFSET (1) + #define RTL8373_RMA_OP_CTRL_00_VLAN_LEAKY_00_MASK (0x1 << RTL8373_RMA_OP_CTRL_00_VLAN_LEAKY_00_OFFSET) + #define RTL8373_RMA_OP_CTRL_00_PISO_LEAKY_00_OFFSET (0) + #define RTL8373_RMA_OP_CTRL_00_PISO_LEAKY_00_MASK (0x1 << RTL8373_RMA_OP_CTRL_00_PISO_LEAKY_00_OFFSET) + +#define RTL8373_RMA_OP_CTRL_01_ADDR (0x4ED0) + #define RTL8373_RMA_OP_CTRL_01_RMA_ACT_01_OFFSET (4) + #define RTL8373_RMA_OP_CTRL_01_RMA_ACT_01_MASK (0x3 << RTL8373_RMA_OP_CTRL_01_RMA_ACT_01_OFFSET) + #define RTL8373_RMA_OP_CTRL_01_DIS_STORM_CTRL_01_OFFSET (3) + #define RTL8373_RMA_OP_CTRL_01_DIS_STORM_CTRL_01_MASK (0x1 << RTL8373_RMA_OP_CTRL_01_DIS_STORM_CTRL_01_OFFSET) + #define RTL8373_RMA_OP_CTRL_01_CKEEP_01_OFFSET (2) + #define RTL8373_RMA_OP_CTRL_01_CKEEP_01_MASK (0x1 << RTL8373_RMA_OP_CTRL_01_CKEEP_01_OFFSET) + #define RTL8373_RMA_OP_CTRL_01_VLAN_LEAKY_01_OFFSET (1) + #define RTL8373_RMA_OP_CTRL_01_VLAN_LEAKY_01_MASK (0x1 << RTL8373_RMA_OP_CTRL_01_VLAN_LEAKY_01_OFFSET) + #define RTL8373_RMA_OP_CTRL_01_PISO_LEAKY_01_OFFSET (0) + #define RTL8373_RMA_OP_CTRL_01_PISO_LEAKY_01_MASK (0x1 << RTL8373_RMA_OP_CTRL_01_PISO_LEAKY_01_OFFSET) + +#define RTL8373_RMA_OP_CTRL_02_ADDR (0x4ED4) + #define RTL8373_RMA_OP_CTRL_02_RMA_ACT_02_OFFSET (4) + #define RTL8373_RMA_OP_CTRL_02_RMA_ACT_02_MASK (0x3 << RTL8373_RMA_OP_CTRL_02_RMA_ACT_02_OFFSET) + #define RTL8373_RMA_OP_CTRL_02_DIS_STORM_CTRL_02_OFFSET (3) + #define RTL8373_RMA_OP_CTRL_02_DIS_STORM_CTRL_02_MASK (0x1 << RTL8373_RMA_OP_CTRL_02_DIS_STORM_CTRL_02_OFFSET) + #define RTL8373_RMA_OP_CTRL_02_CKEEP_02_OFFSET (2) + #define RTL8373_RMA_OP_CTRL_02_CKEEP_02_MASK (0x1 << RTL8373_RMA_OP_CTRL_02_CKEEP_02_OFFSET) + #define RTL8373_RMA_OP_CTRL_02_VLAN_LEAKY_02_OFFSET (1) + #define RTL8373_RMA_OP_CTRL_02_VLAN_LEAKY_02_MASK (0x1 << RTL8373_RMA_OP_CTRL_02_VLAN_LEAKY_02_OFFSET) + #define RTL8373_RMA_OP_CTRL_02_PISO_LEAKY_02_OFFSET (0) + #define RTL8373_RMA_OP_CTRL_02_PISO_LEAKY_02_MASK (0x1 << RTL8373_RMA_OP_CTRL_02_PISO_LEAKY_02_OFFSET) + +#define RTL8373_RMA_OP_CTRL_03_ADDR (0x4ED8) + #define RTL8373_RMA_OP_CTRL_03_RMA_ACT_03_OFFSET (4) + #define RTL8373_RMA_OP_CTRL_03_RMA_ACT_03_MASK (0x3 << RTL8373_RMA_OP_CTRL_03_RMA_ACT_03_OFFSET) + #define RTL8373_RMA_OP_CTRL_03_DIS_STORM_CTRL_03_OFFSET (3) + #define RTL8373_RMA_OP_CTRL_03_DIS_STORM_CTRL_03_MASK (0x1 << RTL8373_RMA_OP_CTRL_03_DIS_STORM_CTRL_03_OFFSET) + #define RTL8373_RMA_OP_CTRL_03_CKEEP_03_OFFSET (2) + #define RTL8373_RMA_OP_CTRL_03_CKEEP_03_MASK (0x1 << RTL8373_RMA_OP_CTRL_03_CKEEP_03_OFFSET) + #define RTL8373_RMA_OP_CTRL_03_VLAN_LEAKY_03_OFFSET (1) + #define RTL8373_RMA_OP_CTRL_03_VLAN_LEAKY_03_MASK (0x1 << RTL8373_RMA_OP_CTRL_03_VLAN_LEAKY_03_OFFSET) + #define RTL8373_RMA_OP_CTRL_03_PISO_LEAKY_03_OFFSET (0) + #define RTL8373_RMA_OP_CTRL_03_PISO_LEAKY_03_MASK (0x1 << RTL8373_RMA_OP_CTRL_03_PISO_LEAKY_03_OFFSET) + +#define RTL8373_RMA_OP_CTRL_04_ADDR (0x4EDC) + #define RTL8373_RMA_OP_CTRL_04_RMA_ACT_04_OFFSET (4) + #define RTL8373_RMA_OP_CTRL_04_RMA_ACT_04_MASK (0x3 << RTL8373_RMA_OP_CTRL_04_RMA_ACT_04_OFFSET) + #define RTL8373_RMA_OP_CTRL_04_DIS_STORM_CTRL_04_OFFSET (3) + #define RTL8373_RMA_OP_CTRL_04_DIS_STORM_CTRL_04_MASK (0x1 << RTL8373_RMA_OP_CTRL_04_DIS_STORM_CTRL_04_OFFSET) + #define RTL8373_RMA_OP_CTRL_04_CKEEP_04_OFFSET (2) + #define RTL8373_RMA_OP_CTRL_04_CKEEP_04_MASK (0x1 << RTL8373_RMA_OP_CTRL_04_CKEEP_04_OFFSET) + #define RTL8373_RMA_OP_CTRL_04_VLAN_LEAKY_04_OFFSET (1) + #define RTL8373_RMA_OP_CTRL_04_VLAN_LEAKY_04_MASK (0x1 << RTL8373_RMA_OP_CTRL_04_VLAN_LEAKY_04_OFFSET) + #define RTL8373_RMA_OP_CTRL_04_PISO_LEAKY_04_OFFSET (0) + #define RTL8373_RMA_OP_CTRL_04_PISO_LEAKY_04_MASK (0x1 << RTL8373_RMA_OP_CTRL_04_PISO_LEAKY_04_OFFSET) + +#define RTL8373_RMA_OP_CTRL_08_ADDR (0x4EE0) + #define RTL8373_RMA_OP_CTRL_08_RMA_ACT_08_OFFSET (4) + #define RTL8373_RMA_OP_CTRL_08_RMA_ACT_08_MASK (0x3 << RTL8373_RMA_OP_CTRL_08_RMA_ACT_08_OFFSET) + #define RTL8373_RMA_OP_CTRL_08_DIS_STORM_CTRL_08_OFFSET (3) + #define RTL8373_RMA_OP_CTRL_08_DIS_STORM_CTRL_08_MASK (0x1 << RTL8373_RMA_OP_CTRL_08_DIS_STORM_CTRL_08_OFFSET) + #define RTL8373_RMA_OP_CTRL_08_CKEEP_08_OFFSET (2) + #define RTL8373_RMA_OP_CTRL_08_CKEEP_08_MASK (0x1 << RTL8373_RMA_OP_CTRL_08_CKEEP_08_OFFSET) + #define RTL8373_RMA_OP_CTRL_08_VLAN_LEAKY_08_OFFSET (1) + #define RTL8373_RMA_OP_CTRL_08_VLAN_LEAKY_08_MASK (0x1 << RTL8373_RMA_OP_CTRL_08_VLAN_LEAKY_08_OFFSET) + #define RTL8373_RMA_OP_CTRL_08_PISO_LEAKY_08_OFFSET (0) + #define RTL8373_RMA_OP_CTRL_08_PISO_LEAKY_08_MASK (0x1 << RTL8373_RMA_OP_CTRL_08_PISO_LEAKY_08_OFFSET) + +#define RTL8373_RMA_OP_CTRL_0D_ADDR (0x4EE4) + #define RTL8373_RMA_OP_CTRL_0D_RMA_ACT_0D_OFFSET (4) + #define RTL8373_RMA_OP_CTRL_0D_RMA_ACT_0D_MASK (0x3 << RTL8373_RMA_OP_CTRL_0D_RMA_ACT_0D_OFFSET) + #define RTL8373_RMA_OP_CTRL_0D_DIS_STORM_CTRL_0D_OFFSET (3) + #define RTL8373_RMA_OP_CTRL_0D_DIS_STORM_CTRL_0D_MASK (0x1 << RTL8373_RMA_OP_CTRL_0D_DIS_STORM_CTRL_0D_OFFSET) + #define RTL8373_RMA_OP_CTRL_0D_CKEEP_0D_OFFSET (2) + #define RTL8373_RMA_OP_CTRL_0D_CKEEP_0D_MASK (0x1 << RTL8373_RMA_OP_CTRL_0D_CKEEP_0D_OFFSET) + #define RTL8373_RMA_OP_CTRL_0D_VLAN_LEAKY_0D_OFFSET (1) + #define RTL8373_RMA_OP_CTRL_0D_VLAN_LEAKY_0D_MASK (0x1 << RTL8373_RMA_OP_CTRL_0D_VLAN_LEAKY_0D_OFFSET) + #define RTL8373_RMA_OP_CTRL_0D_PISO_LEAKY_0D_OFFSET (0) + #define RTL8373_RMA_OP_CTRL_0D_PISO_LEAKY_0D_MASK (0x1 << RTL8373_RMA_OP_CTRL_0D_PISO_LEAKY_0D_OFFSET) + +#define RTL8373_RMA_OP_CTRL_0E_ADDR (0x4EE8) + #define RTL8373_RMA_OP_CTRL_0E_RMA_ACT_0E_OFFSET (4) + #define RTL8373_RMA_OP_CTRL_0E_RMA_ACT_0E_MASK (0x3 << RTL8373_RMA_OP_CTRL_0E_RMA_ACT_0E_OFFSET) + #define RTL8373_RMA_OP_CTRL_0E_DIS_STORM_CTRL_0E_OFFSET (3) + #define RTL8373_RMA_OP_CTRL_0E_DIS_STORM_CTRL_0E_MASK (0x1 << RTL8373_RMA_OP_CTRL_0E_DIS_STORM_CTRL_0E_OFFSET) + #define RTL8373_RMA_OP_CTRL_0E_CKEEP_0E_OFFSET (2) + #define RTL8373_RMA_OP_CTRL_0E_CKEEP_0E_MASK (0x1 << RTL8373_RMA_OP_CTRL_0E_CKEEP_0E_OFFSET) + #define RTL8373_RMA_OP_CTRL_0E_VLAN_LEAKY_0E_OFFSET (1) + #define RTL8373_RMA_OP_CTRL_0E_VLAN_LEAKY_0E_MASK (0x1 << RTL8373_RMA_OP_CTRL_0E_VLAN_LEAKY_0E_OFFSET) + #define RTL8373_RMA_OP_CTRL_0E_PISO_LEAKY_0E_OFFSET (0) + #define RTL8373_RMA_OP_CTRL_0E_PISO_LEAKY_0E_MASK (0x1 << RTL8373_RMA_OP_CTRL_0E_PISO_LEAKY_0E_OFFSET) + +#define RTL8373_RMA_OP_CTRL_10_ADDR (0x4EEC) + #define RTL8373_RMA_OP_CTRL_10_RMA_ACT_10_OFFSET (4) + #define RTL8373_RMA_OP_CTRL_10_RMA_ACT_10_MASK (0x3 << RTL8373_RMA_OP_CTRL_10_RMA_ACT_10_OFFSET) + #define RTL8373_RMA_OP_CTRL_10_DIS_STORM_CTRL_10_OFFSET (3) + #define RTL8373_RMA_OP_CTRL_10_DIS_STORM_CTRL_10_MASK (0x1 << RTL8373_RMA_OP_CTRL_10_DIS_STORM_CTRL_10_OFFSET) + #define RTL8373_RMA_OP_CTRL_10_CKEEP_10_OFFSET (2) + #define RTL8373_RMA_OP_CTRL_10_CKEEP_10_MASK (0x1 << RTL8373_RMA_OP_CTRL_10_CKEEP_10_OFFSET) + #define RTL8373_RMA_OP_CTRL_10_VLAN_LEAKY_10_OFFSET (1) + #define RTL8373_RMA_OP_CTRL_10_VLAN_LEAKY_10_MASK (0x1 << RTL8373_RMA_OP_CTRL_10_VLAN_LEAKY_10_OFFSET) + #define RTL8373_RMA_OP_CTRL_10_PISO_LEAKY_10_OFFSET (0) + #define RTL8373_RMA_OP_CTRL_10_PISO_LEAKY_10_MASK (0x1 << RTL8373_RMA_OP_CTRL_10_PISO_LEAKY_10_OFFSET) + +#define RTL8373_RMA_OP_CTRL_11_ADDR (0x4EF0) + #define RTL8373_RMA_OP_CTRL_11_RMA_ACT_11_OFFSET (4) + #define RTL8373_RMA_OP_CTRL_11_RMA_ACT_11_MASK (0x3 << RTL8373_RMA_OP_CTRL_11_RMA_ACT_11_OFFSET) + #define RTL8373_RMA_OP_CTRL_11_DIS_STORM_CTRL_11_OFFSET (3) + #define RTL8373_RMA_OP_CTRL_11_DIS_STORM_CTRL_11_MASK (0x1 << RTL8373_RMA_OP_CTRL_11_DIS_STORM_CTRL_11_OFFSET) + #define RTL8373_RMA_OP_CTRL_11_CKEEP_11_OFFSET (2) + #define RTL8373_RMA_OP_CTRL_11_CKEEP_11_MASK (0x1 << RTL8373_RMA_OP_CTRL_11_CKEEP_11_OFFSET) + #define RTL8373_RMA_OP_CTRL_11_VLAN_LEAKY_11_OFFSET (1) + #define RTL8373_RMA_OP_CTRL_11_VLAN_LEAKY_11_MASK (0x1 << RTL8373_RMA_OP_CTRL_11_VLAN_LEAKY_11_OFFSET) + #define RTL8373_RMA_OP_CTRL_11_PISO_LEAKY_11_OFFSET (0) + #define RTL8373_RMA_OP_CTRL_11_PISO_LEAKY_11_MASK (0x1 << RTL8373_RMA_OP_CTRL_11_PISO_LEAKY_11_OFFSET) + +#define RTL8373_RMA_OP_CTRL_12_ADDR (0x4EF4) + #define RTL8373_RMA_OP_CTRL_12_RMA_ACT_12_OFFSET (4) + #define RTL8373_RMA_OP_CTRL_12_RMA_ACT_12_MASK (0x3 << RTL8373_RMA_OP_CTRL_12_RMA_ACT_12_OFFSET) + #define RTL8373_RMA_OP_CTRL_12_DIS_STORM_CTRL_12_OFFSET (3) + #define RTL8373_RMA_OP_CTRL_12_DIS_STORM_CTRL_12_MASK (0x1 << RTL8373_RMA_OP_CTRL_12_DIS_STORM_CTRL_12_OFFSET) + #define RTL8373_RMA_OP_CTRL_12_CKEEP_12_OFFSET (2) + #define RTL8373_RMA_OP_CTRL_12_CKEEP_12_MASK (0x1 << RTL8373_RMA_OP_CTRL_12_CKEEP_12_OFFSET) + #define RTL8373_RMA_OP_CTRL_12_VLAN_LEAKY_12_OFFSET (1) + #define RTL8373_RMA_OP_CTRL_12_VLAN_LEAKY_12_MASK (0x1 << RTL8373_RMA_OP_CTRL_12_VLAN_LEAKY_12_OFFSET) + #define RTL8373_RMA_OP_CTRL_12_PISO_LEAKY_12_OFFSET (0) + #define RTL8373_RMA_OP_CTRL_12_PISO_LEAKY_12_MASK (0x1 << RTL8373_RMA_OP_CTRL_12_PISO_LEAKY_12_OFFSET) + +#define RTL8373_RMA_OP_CTRL_13_ADDR (0x4EF8) + #define RTL8373_RMA_OP_CTRL_13_RMA_ACT_13_OFFSET (4) + #define RTL8373_RMA_OP_CTRL_13_RMA_ACT_13_MASK (0x3 << RTL8373_RMA_OP_CTRL_13_RMA_ACT_13_OFFSET) + #define RTL8373_RMA_OP_CTRL_13_DIS_STORM_CTRL_13_OFFSET (3) + #define RTL8373_RMA_OP_CTRL_13_DIS_STORM_CTRL_13_MASK (0x1 << RTL8373_RMA_OP_CTRL_13_DIS_STORM_CTRL_13_OFFSET) + #define RTL8373_RMA_OP_CTRL_13_CKEEP_13_OFFSET (2) + #define RTL8373_RMA_OP_CTRL_13_CKEEP_13_MASK (0x1 << RTL8373_RMA_OP_CTRL_13_CKEEP_13_OFFSET) + #define RTL8373_RMA_OP_CTRL_13_VLAN_LEAKY_13_OFFSET (1) + #define RTL8373_RMA_OP_CTRL_13_VLAN_LEAKY_13_MASK (0x1 << RTL8373_RMA_OP_CTRL_13_VLAN_LEAKY_13_OFFSET) + #define RTL8373_RMA_OP_CTRL_13_PISO_LEAKY_13_OFFSET (0) + #define RTL8373_RMA_OP_CTRL_13_PISO_LEAKY_13_MASK (0x1 << RTL8373_RMA_OP_CTRL_13_PISO_LEAKY_13_OFFSET) + +#define RTL8373_RMA_OP_CTRL_18_ADDR (0x4EFC) + #define RTL8373_RMA_OP_CTRL_18_RMA_ACT_18_OFFSET (4) + #define RTL8373_RMA_OP_CTRL_18_RMA_ACT_18_MASK (0x3 << RTL8373_RMA_OP_CTRL_18_RMA_ACT_18_OFFSET) + #define RTL8373_RMA_OP_CTRL_18_DIS_STORM_CTRL_18_OFFSET (3) + #define RTL8373_RMA_OP_CTRL_18_DIS_STORM_CTRL_18_MASK (0x1 << RTL8373_RMA_OP_CTRL_18_DIS_STORM_CTRL_18_OFFSET) + #define RTL8373_RMA_OP_CTRL_18_CKEEP_18_OFFSET (2) + #define RTL8373_RMA_OP_CTRL_18_CKEEP_18_MASK (0x1 << RTL8373_RMA_OP_CTRL_18_CKEEP_18_OFFSET) + #define RTL8373_RMA_OP_CTRL_18_VLAN_LEAKY_18_OFFSET (1) + #define RTL8373_RMA_OP_CTRL_18_VLAN_LEAKY_18_MASK (0x1 << RTL8373_RMA_OP_CTRL_18_VLAN_LEAKY_18_OFFSET) + #define RTL8373_RMA_OP_CTRL_18_PISO_LEAKY_18_OFFSET (0) + #define RTL8373_RMA_OP_CTRL_18_PISO_LEAKY_18_MASK (0x1 << RTL8373_RMA_OP_CTRL_18_PISO_LEAKY_18_OFFSET) + +#define RTL8373_RMA_OP_CTRL_1A_ADDR (0x4F00) + #define RTL8373_RMA_OP_CTRL_1A_RMA_ACT_1A_OFFSET (4) + #define RTL8373_RMA_OP_CTRL_1A_RMA_ACT_1A_MASK (0x3 << RTL8373_RMA_OP_CTRL_1A_RMA_ACT_1A_OFFSET) + #define RTL8373_RMA_OP_CTRL_1A_DIS_STORM_CTRL_1A_OFFSET (3) + #define RTL8373_RMA_OP_CTRL_1A_DIS_STORM_CTRL_1A_MASK (0x1 << RTL8373_RMA_OP_CTRL_1A_DIS_STORM_CTRL_1A_OFFSET) + #define RTL8373_RMA_OP_CTRL_1A_CKEEP_1A_OFFSET (2) + #define RTL8373_RMA_OP_CTRL_1A_CKEEP_1A_MASK (0x1 << RTL8373_RMA_OP_CTRL_1A_CKEEP_1A_OFFSET) + #define RTL8373_RMA_OP_CTRL_1A_VLAN_LEAKY_1A_OFFSET (1) + #define RTL8373_RMA_OP_CTRL_1A_VLAN_LEAKY_1A_MASK (0x1 << RTL8373_RMA_OP_CTRL_1A_VLAN_LEAKY_1A_OFFSET) + #define RTL8373_RMA_OP_CTRL_1A_PISO_LEAKY_1A_OFFSET (0) + #define RTL8373_RMA_OP_CTRL_1A_PISO_LEAKY_1A_MASK (0x1 << RTL8373_RMA_OP_CTRL_1A_PISO_LEAKY_1A_OFFSET) + +#define RTL8373_RMA_OP_CTRL_20_ADDR (0x4F04) + #define RTL8373_RMA_OP_CTRL_20_RMA_ACT_20_OFFSET (4) + #define RTL8373_RMA_OP_CTRL_20_RMA_ACT_20_MASK (0x3 << RTL8373_RMA_OP_CTRL_20_RMA_ACT_20_OFFSET) + #define RTL8373_RMA_OP_CTRL_20_DIS_STORM_CTRL_20_OFFSET (3) + #define RTL8373_RMA_OP_CTRL_20_DIS_STORM_CTRL_20_MASK (0x1 << RTL8373_RMA_OP_CTRL_20_DIS_STORM_CTRL_20_OFFSET) + #define RTL8373_RMA_OP_CTRL_20_CKEEP_20_OFFSET (2) + #define RTL8373_RMA_OP_CTRL_20_CKEEP_20_MASK (0x1 << RTL8373_RMA_OP_CTRL_20_CKEEP_20_OFFSET) + #define RTL8373_RMA_OP_CTRL_20_VLAN_LEAKY_20_OFFSET (1) + #define RTL8373_RMA_OP_CTRL_20_VLAN_LEAKY_20_MASK (0x1 << RTL8373_RMA_OP_CTRL_20_VLAN_LEAKY_20_OFFSET) + #define RTL8373_RMA_OP_CTRL_20_PISO_LEAKY_20_OFFSET (0) + #define RTL8373_RMA_OP_CTRL_20_PISO_LEAKY_20_MASK (0x1 << RTL8373_RMA_OP_CTRL_20_PISO_LEAKY_20_OFFSET) + +#define RTL8373_RMA_OP_CTRL_21_ADDR (0x4F08) + #define RTL8373_RMA_OP_CTRL_21_RMA_ACT_21_OFFSET (4) + #define RTL8373_RMA_OP_CTRL_21_RMA_ACT_21_MASK (0x3 << RTL8373_RMA_OP_CTRL_21_RMA_ACT_21_OFFSET) + #define RTL8373_RMA_OP_CTRL_21_DIS_STORM_CTRL_21_OFFSET (3) + #define RTL8373_RMA_OP_CTRL_21_DIS_STORM_CTRL_21_MASK (0x1 << RTL8373_RMA_OP_CTRL_21_DIS_STORM_CTRL_21_OFFSET) + #define RTL8373_RMA_OP_CTRL_21_CKEEP_21_OFFSET (2) + #define RTL8373_RMA_OP_CTRL_21_CKEEP_21_MASK (0x1 << RTL8373_RMA_OP_CTRL_21_CKEEP_21_OFFSET) + #define RTL8373_RMA_OP_CTRL_21_VLAN_LEAKY_21_OFFSET (1) + #define RTL8373_RMA_OP_CTRL_21_VLAN_LEAKY_21_MASK (0x1 << RTL8373_RMA_OP_CTRL_21_VLAN_LEAKY_21_OFFSET) + #define RTL8373_RMA_OP_CTRL_21_PISO_LEAKY_21_OFFSET (0) + #define RTL8373_RMA_OP_CTRL_21_PISO_LEAKY_21_MASK (0x1 << RTL8373_RMA_OP_CTRL_21_PISO_LEAKY_21_OFFSET) + +#define RTL8373_RMA_OP_CTRL_22_ADDR (0x4F0C) + #define RTL8373_RMA_OP_CTRL_22_RMA_ACT_22_OFFSET (4) + #define RTL8373_RMA_OP_CTRL_22_RMA_ACT_22_MASK (0x3 << RTL8373_RMA_OP_CTRL_22_RMA_ACT_22_OFFSET) + #define RTL8373_RMA_OP_CTRL_22_DIS_STORM_CTRL_22_OFFSET (3) + #define RTL8373_RMA_OP_CTRL_22_DIS_STORM_CTRL_22_MASK (0x1 << RTL8373_RMA_OP_CTRL_22_DIS_STORM_CTRL_22_OFFSET) + #define RTL8373_RMA_OP_CTRL_22_CKEEP_22_OFFSET (2) + #define RTL8373_RMA_OP_CTRL_22_CKEEP_22_MASK (0x1 << RTL8373_RMA_OP_CTRL_22_CKEEP_22_OFFSET) + #define RTL8373_RMA_OP_CTRL_22_VLAN_LEAKY_22_OFFSET (1) + #define RTL8373_RMA_OP_CTRL_22_VLAN_LEAKY_22_MASK (0x1 << RTL8373_RMA_OP_CTRL_22_VLAN_LEAKY_22_OFFSET) + #define RTL8373_RMA_OP_CTRL_22_PISO_LEAKY_22_OFFSET (0) + #define RTL8373_RMA_OP_CTRL_22_PISO_LEAKY_22_MASK (0x1 << RTL8373_RMA_OP_CTRL_22_PISO_LEAKY_22_OFFSET) + +#define RTL8373_RMA_OP_CTRL_CDP_ADDR (0x4F10) + #define RTL8373_RMA_OP_CTRL_CDP_RMA_ACT_CDP_OFFSET (4) + #define RTL8373_RMA_OP_CTRL_CDP_RMA_ACT_CDP_MASK (0x3 << RTL8373_RMA_OP_CTRL_CDP_RMA_ACT_CDP_OFFSET) + #define RTL8373_RMA_OP_CTRL_CDP_DIS_STORM_CTRL_CDP_OFFSET (3) + #define RTL8373_RMA_OP_CTRL_CDP_DIS_STORM_CTRL_CDP_MASK (0x1 << RTL8373_RMA_OP_CTRL_CDP_DIS_STORM_CTRL_CDP_OFFSET) + #define RTL8373_RMA_OP_CTRL_CDP_CKEEP_CDP_OFFSET (2) + #define RTL8373_RMA_OP_CTRL_CDP_CKEEP_CDP_MASK (0x1 << RTL8373_RMA_OP_CTRL_CDP_CKEEP_CDP_OFFSET) + #define RTL8373_RMA_OP_CTRL_CDP_VLAN_LEAKY_CDP_OFFSET (1) + #define RTL8373_RMA_OP_CTRL_CDP_VLAN_LEAKY_CDP_MASK (0x1 << RTL8373_RMA_OP_CTRL_CDP_VLAN_LEAKY_CDP_OFFSET) + #define RTL8373_RMA_OP_CTRL_CDP_PISO_LEAKY_CDP_OFFSET (0) + #define RTL8373_RMA_OP_CTRL_CDP_PISO_LEAKY_CDP_MASK (0x1 << RTL8373_RMA_OP_CTRL_CDP_PISO_LEAKY_CDP_OFFSET) + +#define RTL8373_RMA_OP_CTRL_CSSTP_ADDR (0x4F14) + #define RTL8373_RMA_OP_CTRL_CSSTP_RMA_ACT_CSSTP_OFFSET (4) + #define RTL8373_RMA_OP_CTRL_CSSTP_RMA_ACT_CSSTP_MASK (0x3 << RTL8373_RMA_OP_CTRL_CSSTP_RMA_ACT_CSSTP_OFFSET) + #define RTL8373_RMA_OP_CTRL_CSSTP_DIS_STORM_CTRL_CSSTP_OFFSET (3) + #define RTL8373_RMA_OP_CTRL_CSSTP_DIS_STORM_CTRL_CSSTP_MASK (0x1 << RTL8373_RMA_OP_CTRL_CSSTP_DIS_STORM_CTRL_CSSTP_OFFSET) + #define RTL8373_RMA_OP_CTRL_CSSTP_CKEEP_CSSTP_OFFSET (2) + #define RTL8373_RMA_OP_CTRL_CSSTP_CKEEP_CSSTP_MASK (0x1 << RTL8373_RMA_OP_CTRL_CSSTP_CKEEP_CSSTP_OFFSET) + #define RTL8373_RMA_OP_CTRL_CSSTP_VLAN_LEAKY_CSSTP_OFFSET (1) + #define RTL8373_RMA_OP_CTRL_CSSTP_VLAN_LEAKY_CSSTP_MASK (0x1 << RTL8373_RMA_OP_CTRL_CSSTP_VLAN_LEAKY_CSSTP_OFFSET) + #define RTL8373_RMA_OP_CTRL_CSSTP_PISO_LEAKY_CSSTP_OFFSET (0) + #define RTL8373_RMA_OP_CTRL_CSSTP_PISO_LEAKY_CSSTP_MASK (0x1 << RTL8373_RMA_OP_CTRL_CSSTP_PISO_LEAKY_CSSTP_OFFSET) + +#define RTL8373_RMA_OP_CTRL_LLDP_ADDR (0x4F18) + #define RTL8373_RMA_OP_CTRL_LLDP_RMA_ACT_LLDP_OFFSET (4) + #define RTL8373_RMA_OP_CTRL_LLDP_RMA_ACT_LLDP_MASK (0x3 << RTL8373_RMA_OP_CTRL_LLDP_RMA_ACT_LLDP_OFFSET) + #define RTL8373_RMA_OP_CTRL_LLDP_DIS_STORM_CTRL_LLDP_OFFSET (3) + #define RTL8373_RMA_OP_CTRL_LLDP_DIS_STORM_CTRL_LLDP_MASK (0x1 << RTL8373_RMA_OP_CTRL_LLDP_DIS_STORM_CTRL_LLDP_OFFSET) + #define RTL8373_RMA_OP_CTRL_LLDP_CKEEP_LLDP_OFFSET (2) + #define RTL8373_RMA_OP_CTRL_LLDP_CKEEP_LLDP_MASK (0x1 << RTL8373_RMA_OP_CTRL_LLDP_CKEEP_LLDP_OFFSET) + #define RTL8373_RMA_OP_CTRL_LLDP_VLAN_LEAKY_LLDP_OFFSET (1) + #define RTL8373_RMA_OP_CTRL_LLDP_VLAN_LEAKY_LLDP_MASK (0x1 << RTL8373_RMA_OP_CTRL_LLDP_VLAN_LEAKY_LLDP_OFFSET) + #define RTL8373_RMA_OP_CTRL_LLDP_PISO_LEAKY_LLDP_OFFSET (0) + #define RTL8373_RMA_OP_CTRL_LLDP_PISO_LEAKY_LLDP_MASK (0x1 << RTL8373_RMA_OP_CTRL_LLDP_PISO_LEAKY_LLDP_OFFSET) + +#define RTL8373_RMA_CFG_ADDR (0x4F1C) + #define RTL8373_RMA_CFG_LLDP_EN_OFFSET (3) + #define RTL8373_RMA_CFG_LLDP_EN_MASK (0x1 << RTL8373_RMA_CFG_LLDP_EN_OFFSET) + #define RTL8373_RMA_CFG_RMA_TRAP_PRI_OFFSET (0) + #define RTL8373_RMA_CFG_RMA_TRAP_PRI_MASK (0x7 << RTL8373_RMA_CFG_RMA_TRAP_PRI_OFFSET) + +#define RTL8373_RMA_PORT_PTP_ETH2_CTRL_ADDR(port) (0x4F20 + (((port / 9) << 2))) /* port: 0-8 */ + #define RTL8373_RMA_PORT_PTP_ETH2_CTRL_ETH2_P0_ACT_OFFSET(port) ((port % 0x9) << 1) + #define RTL8373_RMA_PORT_PTP_ETH2_CTRL_ETH2_P0_ACT_MASK(port) (0x3 << RTL8373_RMA_PORT_PTP_ETH2_CTRL_ETH2_P0_ACT_OFFSET(port)) + +#define RTL8373_RMA_PORT_PTP_UDP_CTRL_ADDR(port) (0x4F24 + (((port / 9) << 2))) /* port: 0-8 */ + #define RTL8373_RMA_PORT_PTP_UDP_CTRL_UDP_P0_ACT_OFFSET(port) ((port % 0x9) << 1) + #define RTL8373_RMA_PORT_PTP_UDP_CTRL_UDP_P0_ACT_MASK(port) (0x3 << RTL8373_RMA_PORT_PTP_UDP_CTRL_UDP_P0_ACT_OFFSET(port)) + +#define RTL8373_RMA_PORT_PTP_DELAY_CARE_CTRL_ADDR(port) (0x4F28 + (((port / 9) << 2))) /* port: 0-8 */ + #define RTL8373_RMA_PORT_PTP_DELAY_CARE_CTRL_P0_PTP_DELAY_CARE_OFFSET(port) (port % 0x9) + #define RTL8373_RMA_PORT_PTP_DELAY_CARE_CTRL_P0_PTP_DELAY_CARE_MASK(port) (0x1 << RTL8373_RMA_PORT_PTP_DELAY_CARE_CTRL_P0_PTP_DELAY_CARE_OFFSET(port)) + +#define RTL8373_RMA_PORT_PTP_PDELAY_CARE_CTRL_ADDR(port) (0x4F2C + (((port / 9) << 2))) /* port: 0-8 */ + #define RTL8373_RMA_PORT_PTP_PDELAY_CARE_CTRL_P0_PTP_PDELAY_CARE_OFFSET(port) (port % 0x9) + #define RTL8373_RMA_PORT_PTP_PDELAY_CARE_CTRL_P0_PTP_PDELAY_CARE_MASK(port) (0x1 << RTL8373_RMA_PORT_PTP_PDELAY_CARE_CTRL_P0_PTP_PDELAY_CARE_OFFSET(port)) + +#define RTL8373_RMA_PORT_PTP_ASM_CARE_CTRL_ADDR(port) (0x4F30 + (((port / 9) << 2))) /* port: 0-8 */ + #define RTL8373_RMA_PORT_PTP_ASM_CARE_CTRL_P0_PTP_ASM_CARE_OFFSET(port) (port % 0x9) + #define RTL8373_RMA_PORT_PTP_ASM_CARE_CTRL_P0_PTP_ASM_CARE_MASK(port) (0x1 << RTL8373_RMA_PORT_PTP_ASM_CARE_CTRL_P0_PTP_ASM_CARE_OFFSET(port)) + +#define RTL8373_RMA_PTP_TRAP_CTRL_ADDR (0x4F34) + #define RTL8373_RMA_PTP_TRAP_CTRL_CPU_PMSK_OFFSET (16) + #define RTL8373_RMA_PTP_TRAP_CTRL_CPU_PMSK_MASK (0x3 << RTL8373_RMA_PTP_TRAP_CTRL_CPU_PMSK_OFFSET) + #define RTL8373_RMA_PTP_TRAP_CTRL_PRI_OFFSET (0) + #define RTL8373_RMA_PTP_TRAP_CTRL_PRI_MASK (0x7 << RTL8373_RMA_PTP_TRAP_CTRL_PRI_OFFSET) + +/* + * Feature: Link Aggregation + */ +#define RTL8373_TRK_MBR_CTRL_ADDR(index) (0x4F38 + (((index) << 2))) /* index: 0-3 */ + #define RTL8373_TRK_MBR_CTRL_TRK_PMSK_OFFSET (0) + #define RTL8373_TRK_MBR_CTRL_TRK_PMSK_MASK (0x3FF << RTL8373_TRK_MBR_CTRL_TRK_PMSK_OFFSET) + +#define RTL8373_TRK_HASH_CTRL_ADDR(index) (0x4F48 + (((index) << 2))) /* index: 0-3 */ + #define RTL8373_TRK_HASH_CTRL_HASH_MSK_OFFSET (0) + #define RTL8373_TRK_HASH_CTRL_HASH_MSK_MASK (0x7F << RTL8373_TRK_HASH_CTRL_HASH_MSK_OFFSET) + +#define RTL8373_TRK_CTRL_ADDR (0x4F58) + #define RTL8373_TRK_CTRL_TRUNK_FLD_OFFSET (1) + #define RTL8373_TRK_CTRL_TRUNK_FLD_MASK (0x1 << RTL8373_TRK_CTRL_TRUNK_FLD_OFFSET) + +#define RTL8373_TRK_FLOW_CTRL_ADDR(index) (0x4F5C + (((index) << 2))) /* index: 0-3 */ + #define RTL8373_TRK_FLOW_CTRL_TRK_FLCTRL_EN_OFFSET (0) + #define RTL8373_TRK_FLOW_CTRL_TRK_FLCTRL_EN_MASK (0x1 << RTL8373_TRK_FLOW_CTRL_TRK_FLCTRL_EN_OFFSET) + +#define RTL8373_TRK_QUEUE_EMPTY_ADDR (0x4474) + #define RTL8373_TRK_QUEUE_EMPTY_QEMPTY_OFFSET (0) + #define RTL8373_TRK_QUEUE_EMPTY_QEMPTY_MASK (0x3FF << RTL8373_TRK_QUEUE_EMPTY_QEMPTY_OFFSET) + +/* + * Feature: Spanning Tree + */ +#define RTL8373_MSPT_STATE_ADDR(index) (0x5310 + (((index) << 2))) /* index: 0-15 */ + #define RTL8373_MSPT_STATE_PORT9_STATE_OFFSET (18) + #define RTL8373_MSPT_STATE_PORT9_STATE_MASK (0x3 << RTL8373_MSPT_STATE_PORT9_STATE_OFFSET) + #define RTL8373_MSPT_STATE_PORT8_STATE_OFFSET (16) + #define RTL8373_MSPT_STATE_PORT8_STATE_MASK (0x3 << RTL8373_MSPT_STATE_PORT8_STATE_OFFSET) + #define RTL8373_MSPT_STATE_PORT7_STATE_OFFSET (14) + #define RTL8373_MSPT_STATE_PORT7_STATE_MASK (0x3 << RTL8373_MSPT_STATE_PORT7_STATE_OFFSET) + #define RTL8373_MSPT_STATE_PORT6_STATE_OFFSET (12) + #define RTL8373_MSPT_STATE_PORT6_STATE_MASK (0x3 << RTL8373_MSPT_STATE_PORT6_STATE_OFFSET) + #define RTL8373_MSPT_STATE_PORT5_STATE_OFFSET (10) + #define RTL8373_MSPT_STATE_PORT5_STATE_MASK (0x3 << RTL8373_MSPT_STATE_PORT5_STATE_OFFSET) + #define RTL8373_MSPT_STATE_PORT4_STATE_OFFSET (8) + #define RTL8373_MSPT_STATE_PORT4_STATE_MASK (0x3 << RTL8373_MSPT_STATE_PORT4_STATE_OFFSET) + #define RTL8373_MSPT_STATE_PORT3_STATE_OFFSET (6) + #define RTL8373_MSPT_STATE_PORT3_STATE_MASK (0x3 << RTL8373_MSPT_STATE_PORT3_STATE_OFFSET) + #define RTL8373_MSPT_STATE_PORT2_STATE_OFFSET (4) + #define RTL8373_MSPT_STATE_PORT2_STATE_MASK (0x3 << RTL8373_MSPT_STATE_PORT2_STATE_OFFSET) + #define RTL8373_MSPT_STATE_PORT1_STATE_OFFSET (2) + #define RTL8373_MSPT_STATE_PORT1_STATE_MASK (0x3 << RTL8373_MSPT_STATE_PORT1_STATE_OFFSET) + #define RTL8373_MSPT_STATE_PORT0_STATE_OFFSET (0) + #define RTL8373_MSPT_STATE_PORT0_STATE_MASK (0x3 << RTL8373_MSPT_STATE_PORT0_STATE_OFFSET) + +/* + * Feature: MAC Forwarding Control + */ +#define RTL8373_L2_CTRL_ADDR (0x5350) + #define RTL8373_L2_CTRL_CPU_PMSK_OFFSET (15) + #define RTL8373_L2_CTRL_CPU_PMSK_MASK (0x3 << RTL8373_L2_CTRL_CPU_PMSK_OFFSET) + #define RTL8373_L2_CTRL_MUL_TRAP_PRI_OFFSET (12) + #define RTL8373_L2_CTRL_MUL_TRAP_PRI_MASK (0x7 << RTL8373_L2_CTRL_MUL_TRAP_PRI_OFFSET) + #define RTL8373_L2_CTRL_TRAP_PRI_OFFSET (9) + #define RTL8373_L2_CTRL_TRAP_PRI_MASK (0x7 << RTL8373_L2_CTRL_TRAP_PRI_OFFSET) + #define RTL8373_L2_CTRL_CFG_LOOKUP_HIT_ISO_ACT_OFFSET (8) + #define RTL8373_L2_CTRL_CFG_LOOKUP_HIT_ISO_ACT_MASK (0x1 << RTL8373_L2_CTRL_CFG_LOOKUP_HIT_ISO_ACT_OFFSET) + #define RTL8373_L2_CTRL_HASH_FULL_ACT_OFFSET (6) + #define RTL8373_L2_CTRL_HASH_FULL_ACT_MASK (0x3 << RTL8373_L2_CTRL_HASH_FULL_ACT_OFFSET) + #define RTL8373_L2_CTRL_LUTCAM_DISABLE_OFFSET (5) + #define RTL8373_L2_CTRL_LUTCAM_DISABLE_MASK (0x1 << RTL8373_L2_CTRL_LUTCAM_DISABLE_OFFSET) + #define RTL8373_L2_CTRL_LINKDOWN_AGEOUT_OFFSET (4) + #define RTL8373_L2_CTRL_LINKDOWN_AGEOUT_MASK (0x1 << RTL8373_L2_CTRL_LINKDOWN_AGEOUT_OFFSET) + #define RTL8373_L2_CTRL_LUT_IPMC_HASH_OFFSET (3) + #define RTL8373_L2_CTRL_LUT_IPMC_HASH_MASK (0x1 << RTL8373_L2_CTRL_LUT_IPMC_HASH_OFFSET) + #define RTL8373_L2_CTRL_AGE_TIMER_OFFSET (0) + #define RTL8373_L2_CTRL_AGE_TIMER_MASK (0x7 << RTL8373_L2_CTRL_AGE_TIMER_OFFSET) + +#define RTL8373_L2_AGE_CTRL_ADDR (0x5354) + #define RTL8373_L2_AGE_CTRL_AGE_UNIT_OFFSET (0) + #define RTL8373_L2_AGE_CTRL_AGE_UNIT_MASK (0xFFFF << RTL8373_L2_AGE_CTRL_AGE_UNIT_OFFSET) + +#define RTL8373_L2_PORT_AGE_CTRL_ADDR(port) (0x5358 + (((port / 10) << 2))) /* port: 0-9 */ + #define RTL8373_L2_PORT_AGE_CTRL_DIS_AGE_OFFSET(port) (port % 0xA) + #define RTL8373_L2_PORT_AGE_CTRL_DIS_AGE_MASK(port) (0x1 << RTL8373_L2_PORT_AGE_CTRL_DIS_AGE_OFFSET(port)) + +#define RTL8373_L2_NEWSA_CTRL_ADDR(port) (0x4F6C + (((port / 10) << 2))) /* port: 0-9 */ + #define RTL8373_L2_NEWSA_CTRL_NEW_SA_OFFSET(port) ((port % 0xA) << 1) + #define RTL8373_L2_NEWSA_CTRL_NEW_SA_MASK(port) (0x3 << RTL8373_L2_NEWSA_CTRL_NEW_SA_OFFSET(port)) + +#define RTL8373_L2_UNMATCH_SA_CTRL_ADDR(port) (0x4F70 + (((port / 10) << 2))) /* port: 0-9 */ + #define RTL8373_L2_UNMATCH_SA_CTRL_UNMATCH_SA_OFFSET(port) ((port % 0xA) << 1) + #define RTL8373_L2_UNMATCH_SA_CTRL_UNMATCH_SA_MASK(port) (0x3 << RTL8373_L2_UNMATCH_SA_CTRL_UNMATCH_SA_OFFSET(port)) + +#define RTL8373_L2_SA_MOVING_FORBID_ADDR(port) (0x535C + (((port / 10) << 2))) /* port: 0-9 */ + #define RTL8373_L2_SA_MOVING_FORBID_FORBID_OFFSET(port) (port % 0xA) + #define RTL8373_L2_SA_MOVING_FORBID_FORBID_MASK(port) (0x1 << RTL8373_L2_SA_MOVING_FORBID_FORBID_OFFSET(port)) + +#define RTL8373_L2_UNKN_UC_FLD_PMSK_ADDR (0x5360) + #define RTL8373_L2_UNKN_UC_FLD_PMSK_PORTMASK_OFFSET (0) + #define RTL8373_L2_UNKN_UC_FLD_PMSK_PORTMASK_MASK (0x3FF << RTL8373_L2_UNKN_UC_FLD_PMSK_PORTMASK_OFFSET) + +#define RTL8373_L2_UNKN_MC_FLD_PMSK_ADDR (0x5364) + #define RTL8373_L2_UNKN_MC_FLD_PMSK_PORTMASK_OFFSET (0) + #define RTL8373_L2_UNKN_MC_FLD_PMSK_PORTMASK_MASK (0x3FF << RTL8373_L2_UNKN_MC_FLD_PMSK_PORTMASK_OFFSET) + +#define RTL8373_IPV4_UNKN_MC_FLD_PMSK_ADDR (0x5368) + #define RTL8373_IPV4_UNKN_MC_FLD_PMSK_PORTMASK_OFFSET (0) + #define RTL8373_IPV4_UNKN_MC_FLD_PMSK_PORTMASK_MASK (0x3FF << RTL8373_IPV4_UNKN_MC_FLD_PMSK_PORTMASK_OFFSET) + +#define RTL8373_IPV6_UNKN_MC_FLD_PMSK_ADDR (0x536C) + #define RTL8373_IPV6_UNKN_MC_FLD_PMSK_PORTMASK_OFFSET (0) + #define RTL8373_IPV6_UNKN_MC_FLD_PMSK_PORTMASK_MASK (0x3FF << RTL8373_IPV6_UNKN_MC_FLD_PMSK_PORTMASK_OFFSET) + +#define RTL8373_L2_BC_FLD_PMSK_ADDR (0x5370) + #define RTL8373_L2_BC_FLD_PMSK_PORTMASK_OFFSET (0) + #define RTL8373_L2_BC_FLD_PMSK_PORTMASK_MASK (0x3FF << RTL8373_L2_BC_FLD_PMSK_PORTMASK_OFFSET) + +#define RTL8373_L2_PORT_UC_LM_ACT_ADDR(port) (0x5374 + (((port / 10) << 2))) /* port: 0-9 */ + #define RTL8373_L2_PORT_UC_LM_ACT_ACT_OFFSET(port) ((port % 0xA) << 1) + #define RTL8373_L2_PORT_UC_LM_ACT_ACT_MASK(port) (0x3 << RTL8373_L2_PORT_UC_LM_ACT_ACT_OFFSET(port)) + +#define RTL8373_L2_PORT_MC_LM_ACT_ADDR(port) (0x4F74 + (((port / 10) << 2))) /* port: 0-9 */ + #define RTL8373_L2_PORT_MC_LM_ACT_ACT_OFFSET(port) ((port % 0xA) << 1) + #define RTL8373_L2_PORT_MC_LM_ACT_ACT_MASK(port) (0x3 << RTL8373_L2_PORT_MC_LM_ACT_ACT_OFFSET(port)) + +#define RTL8373_IPV4_PORT_MC_LM_ACT_ADDR(port) (0x4F78 + (((port / 10) << 2))) /* port: 0-9 */ + #define RTL8373_IPV4_PORT_MC_LM_ACT_ACT_OFFSET(port) ((port % 0xA) << 1) + #define RTL8373_IPV4_PORT_MC_LM_ACT_ACT_MASK(port) (0x3 << RTL8373_IPV4_PORT_MC_LM_ACT_ACT_OFFSET(port)) + +#define RTL8373_IPV6_PORT_MC_LM_ACT_ADDR(port) (0x4F7C + (((port / 10) << 2))) /* port: 0-9 */ + #define RTL8373_IPV6_PORT_MC_LM_ACT_ACT_OFFSET(port) ((port % 0xA) << 1) + #define RTL8373_IPV6_PORT_MC_LM_ACT_ACT_MASK(port) (0x3 << RTL8373_IPV6_PORT_MC_LM_ACT_ACT_OFFSET(port)) + +#define RTL8373_L2_LRN_CONSTRT_CTRL_ADDR (0x5378) + #define RTL8373_L2_LRN_CONSTRT_CTRL_PORT_MASK_OFFSET (16) + #define RTL8373_L2_LRN_CONSTRT_CTRL_PORT_MASK_MASK (0x3FF << RTL8373_L2_LRN_CONSTRT_CTRL_PORT_MASK_OFFSET) + #define RTL8373_L2_LRN_CONSTRT_CTRL_CONSTRT_NUM_OFFSET (0) + #define RTL8373_L2_LRN_CONSTRT_CTRL_CONSTRT_NUM_MASK (0x1FFF << RTL8373_L2_LRN_CONSTRT_CTRL_CONSTRT_NUM_OFFSET) + +#define RTL8373_L2_LRN_CONSTRT_CNT_ADDR (0x537C) + #define RTL8373_L2_LRN_CONSTRT_CNT_LRN_CNT_OFFSET (0) + #define RTL8373_L2_LRN_CONSTRT_CNT_LRN_CNT_MASK (0x1FFF << RTL8373_L2_LRN_CONSTRT_CNT_LRN_CNT_OFFSET) + +#define RTL8373_L2_LRN_CONSTRT_ACT_ADDR (0x5380) + #define RTL8373_L2_LRN_CONSTRT_ACT_LRN_ACT_OFFSET (0) + #define RTL8373_L2_LRN_CONSTRT_ACT_LRN_ACT_MASK (0x3 << RTL8373_L2_LRN_CONSTRT_ACT_LRN_ACT_OFFSET) + +#define RTL8373_L2_LRN_PORT_CONSTRT_CTRL_ADDR(port) (0x5384 + (((port) << 2))) /* port: 0-9 */ + #define RTL8373_L2_LRN_PORT_CONSTRT_CTRL_CONSTRT_NUM_OFFSET (0) + #define RTL8373_L2_LRN_PORT_CONSTRT_CTRL_CONSTRT_NUM_MASK (0x1FFF << RTL8373_L2_LRN_PORT_CONSTRT_CTRL_CONSTRT_NUM_OFFSET) + +#define RTL8373_L2_LRN_PORT_CONSTRT_CNT_ADDR(port) (0x53AC + (((port) << 2))) /* port: 0-9 */ + #define RTL8373_L2_LRN_PORT_CONSTRT_CNT_LRN_CNT_OFFSET (0) + #define RTL8373_L2_LRN_PORT_CONSTRT_CNT_LRN_CNT_MASK (0x1FFF << RTL8373_L2_LRN_PORT_CONSTRT_CNT_LRN_CNT_OFFSET) + +#define RTL8373_L2_LRN_PORT_CONSTRT_ACT_ADDR (0x4F80) + #define RTL8373_L2_LRN_PORT_CONSTRT_ACT_LRN_ACT_OFFSET (0) + #define RTL8373_L2_LRN_PORT_CONSTRT_ACT_LRN_ACT_MASK (0x3 << RTL8373_L2_LRN_PORT_CONSTRT_ACT_LRN_ACT_OFFSET) + +#define RTL8373_L2_TBL_FLUSH_CMD_ADDR (0x53D4) + #define RTL8373_L2_TBL_FLUSH_CMD_FLUSH_BUSY_OFFSET (17) + #define RTL8373_L2_TBL_FLUSH_CMD_FLUSH_BUSY_MASK (0x1 << RTL8373_L2_TBL_FLUSH_CMD_FLUSH_BUSY_OFFSET) + #define RTL8373_L2_TBL_FLUSH_CMD_FLUSH_ACT_OFFSET (16) + #define RTL8373_L2_TBL_FLUSH_CMD_FLUSH_ACT_MASK (0x1 << RTL8373_L2_TBL_FLUSH_CMD_FLUSH_ACT_OFFSET) + #define RTL8373_L2_TBL_FLUSH_CMD_FLUSH_PMSK_OFFSET (0) + #define RTL8373_L2_TBL_FLUSH_CMD_FLUSH_PMSK_MASK (0x3FF << RTL8373_L2_TBL_FLUSH_CMD_FLUSH_PMSK_OFFSET) + +#define RTL8373_L2_TBL_FLUSH_ALL_ADDR (0x53D8) + #define RTL8373_L2_TBL_FLUSH_ALL_FLUSH_ALL_OFFSET (0) + #define RTL8373_L2_TBL_FLUSH_ALL_FLUSH_ALL_MASK (0x1 << RTL8373_L2_TBL_FLUSH_ALL_FLUSH_ALL_OFFSET) + +#define RTL8373_L2_TBL_FLUSH_MODE_ADDR (0x53DC) + #define RTL8373_L2_TBL_FLUSH_MODE_FLUSH_TYPE_OFFSET (2) + #define RTL8373_L2_TBL_FLUSH_MODE_FLUSH_TYPE_MASK (0x1 << RTL8373_L2_TBL_FLUSH_MODE_FLUSH_TYPE_OFFSET) + #define RTL8373_L2_TBL_FLUSH_MODE_FLUSH_MODE_OFFSET (0) + #define RTL8373_L2_TBL_FLUSH_MODE_FLUSH_MODE_MASK (0x3 << RTL8373_L2_TBL_FLUSH_MODE_FLUSH_MODE_OFFSET) + +#define RTL8373_L2_TBL_FLUSH_XID_ADDR (0x53E0) + #define RTL8373_L2_TBL_FLUSH_XID_FLUSH_FID_OFFSET (16) + #define RTL8373_L2_TBL_FLUSH_XID_FLUSH_FID_MASK (0xF << RTL8373_L2_TBL_FLUSH_XID_FLUSH_FID_OFFSET) + #define RTL8373_L2_TBL_FLUSH_XID_FLUSH_VID_OFFSET (0) + #define RTL8373_L2_TBL_FLUSH_XID_FLUSH_VID_MASK (0xFFF << RTL8373_L2_TBL_FLUSH_XID_FLUSH_VID_OFFSET) + +#define RTL8373_SOURCE_PORT_PERMIT_ADDR(port) (0x4F84 + (((port / 10) << 2))) /* port: 0-9 */ + #define RTL8373_SOURCE_PORT_PERMIT_SRC_PERMIT_EN_OFFSET(port) (port % 0xA) + #define RTL8373_SOURCE_PORT_PERMIT_SRC_PERMIT_EN_MASK(port) (0x1 << RTL8373_SOURCE_PORT_PERMIT_SRC_PERMIT_EN_OFFSET(port)) + +#define RTL8373_IPMC_GROUP_DIP_ADDR(index) (0x4F88 + (((index) << 2))) /* index: 0-63 */ + #define RTL8373_IPMC_GROUP_DIP_DIP_OFFSET (0) + #define RTL8373_IPMC_GROUP_DIP_DIP_MASK (0xFFFFFFF << RTL8373_IPMC_GROUP_DIP_DIP_OFFSET) + +#define RTL8373_IPMC_GROUP_PMSK_ADDR(index) (0x53E4 + (((index) << 2))) /* index: 0-63 */ + #define RTL8373_IPMC_GROUP_PMSK_PMSK_OFFSET (0) + #define RTL8373_IPMC_GROUP_PMSK_PMSK_MASK (0x3FF << RTL8373_IPMC_GROUP_PMSK_PMSK_OFFSET) + +#define RTL8373_IPMC_GROUP_VALID_ADDR(index) (0x5BE0 + (((index >> 5) << 2))) /* index: 0-63 */ + #define RTL8373_IPMC_GROUP_VALID_VALID_OFFSET(index) (index % 0x20) + #define RTL8373_IPMC_GROUP_VALID_VALID_MASK(index) (0x1 << RTL8373_IPMC_GROUP_VALID_VALID_OFFSET(index)) + +#define RTL8373_IPMUL_NO_VLAN_EGRESS_ADDR(port) (0x5088 + (((port / 10) << 2))) /* port: 0-9 */ + #define RTL8373_IPMUL_NO_VLAN_EGRESS_IPMUL_VLAN_LEAKY_OFFSET(port) (port % 0xA) + #define RTL8373_IPMUL_NO_VLAN_EGRESS_IPMUL_VLAN_LEAKY_MASK(port) (0x1 << RTL8373_IPMUL_NO_VLAN_EGRESS_IPMUL_VLAN_LEAKY_OFFSET(port)) + +#define RTL8373_IPMUL_NO_PORTISO_ADDR(port) (0x508C + (((port / 10) << 2))) /* port: 0-9 */ + #define RTL8373_IPMUL_NO_PORTISO_IPMUL_PORTISO_LEAKY_OFFSET(port) (port % 0xA) + #define RTL8373_IPMUL_NO_PORTISO_IPMUL_PORTISO_LEAKY_MASK(port) (0x1 << RTL8373_IPMUL_NO_PORTISO_IPMUL_PORTISO_LEAKY_OFFSET(port)) + +#define RTL8373_L2_FORCE_MODE_ADDR(port) (0x5090 + (((port / 10) << 2))) /* port: 0-9 */ + #define RTL8373_L2_FORCE_MODE_FORCE_CTRL_OFFSET(port) (port % 0xA) + #define RTL8373_L2_FORCE_MODE_FORCE_CTRL_MASK(port) (0x1 << RTL8373_L2_FORCE_MODE_FORCE_CTRL_OFFSET(port)) + +#define RTL8373_L2_FORCE_DPM_PORT_ADDR(port) (0x5094 + (((port) << 2))) /* port: 0-9 */ + #define RTL8373_L2_FORCE_DPM_PORT_FORCE_PORT_MASK_OFFSET (0) + #define RTL8373_L2_FORCE_DPM_PORT_FORCE_PORT_MASK_MASK (0x3FF << RTL8373_L2_FORCE_DPM_PORT_FORCE_PORT_MASK_OFFSET) + +/* + * Feature: IGMP & MLD + */ +#define RTL8373_IGMP_CTRL_ADDR (0x5290) + #define RTL8373_IGMP_CTRL_IGMP_MLD_IP6_BYPASS_OFFSET (25) + #define RTL8373_IGMP_CTRL_IGMP_MLD_IP6_BYPASS_MASK (0x1 << RTL8373_IGMP_CTRL_IGMP_MLD_IP6_BYPASS_OFFSET) + #define RTL8373_IGMP_CTRL_IGMP_MLD_IP4_BYPASS_239_255_255_OFFSET (24) + #define RTL8373_IGMP_CTRL_IGMP_MLD_IP4_BYPASS_239_255_255_MASK (0x1 << RTL8373_IGMP_CTRL_IGMP_MLD_IP4_BYPASS_239_255_255_OFFSET) + #define RTL8373_IGMP_CTRL_IGMP_MLD_IP4_BYPASS_224_0_1_OFFSET (23) + #define RTL8373_IGMP_CTRL_IGMP_MLD_IP4_BYPASS_224_0_1_MASK (0x1 << RTL8373_IGMP_CTRL_IGMP_MLD_IP4_BYPASS_224_0_1_OFFSET) + #define RTL8373_IGMP_CTRL_IGMP_MLD_IP4_BYPASS_224_0_0_OFFSET (22) + #define RTL8373_IGMP_CTRL_IGMP_MLD_IP4_BYPASS_224_0_0_MASK (0x1 << RTL8373_IGMP_CTRL_IGMP_MLD_IP4_BYPASS_224_0_0_OFFSET) + #define RTL8373_IGMP_CTRL_DROP_LEAVE_ZERO_OFFSET (21) + #define RTL8373_IGMP_CTRL_DROP_LEAVE_ZERO_MASK (0x1 << RTL8373_IGMP_CTRL_DROP_LEAVE_ZERO_OFFSET) + #define RTL8373_IGMP_CTRL_TABLE_FULL_OP_OFFSET (19) + #define RTL8373_IGMP_CTRL_TABLE_FULL_OP_MASK (0x3 << RTL8373_IGMP_CTRL_TABLE_FULL_OP_OFFSET) + #define RTL8373_IGMP_CTRL_IGMP_MLD_PORTISO_LKY_OFFSET (18) + #define RTL8373_IGMP_CTRL_IGMP_MLD_PORTISO_LKY_MASK (0x1 << RTL8373_IGMP_CTRL_IGMP_MLD_PORTISO_LKY_OFFSET) + #define RTL8373_IGMP_CTRL_IGMP_MLD_VLAN_LKY_OFFSET (17) + #define RTL8373_IGMP_CTRL_IGMP_MLD_VLAN_LKY_MASK (0x1 << RTL8373_IGMP_CTRL_IGMP_MLD_VLAN_LKY_OFFSET) + #define RTL8373_IGMP_CTRL_IGMP_MLD_DISC_STORM_FLTR_OFFSET (16) + #define RTL8373_IGMP_CTRL_IGMP_MLD_DISC_STORM_FLTR_MASK (0x1 << RTL8373_IGMP_CTRL_IGMP_MLD_DISC_STORM_FLTR_OFFSET) + #define RTL8373_IGMP_CTRL_REPORT_LEAVE_FWD_OFFSET (14) + #define RTL8373_IGMP_CTRL_REPORT_LEAVE_FWD_MASK (0x3 << RTL8373_IGMP_CTRL_REPORT_LEAVE_FWD_OFFSET) + #define RTL8373_IGMP_CTRL_REPORT_FWD_OFFSET (13) + #define RTL8373_IGMP_CTRL_REPORT_FWD_MASK (0x1 << RTL8373_IGMP_CTRL_REPORT_FWD_OFFSET) + #define RTL8373_IGMP_CTRL_ROBUSTNESS_VAR_OFFSET (10) + #define RTL8373_IGMP_CTRL_ROBUSTNESS_VAR_MASK (0x7 << RTL8373_IGMP_CTRL_ROBUSTNESS_VAR_OFFSET) + #define RTL8373_IGMP_CTRL_LEAVE_SUPPRESSION_OFFSET (9) + #define RTL8373_IGMP_CTRL_LEAVE_SUPPRESSION_MASK (0x1 << RTL8373_IGMP_CTRL_LEAVE_SUPPRESSION_OFFSET) + #define RTL8373_IGMP_CTRL_REPORT_SUPPRESSION_OFFSET (8) + #define RTL8373_IGMP_CTRL_REPORT_SUPPRESSION_MASK (0x1 << RTL8373_IGMP_CTRL_REPORT_SUPPRESSION_OFFSET) + #define RTL8373_IGMP_CTRL_LEAVE_TIMER_OFFSET (5) + #define RTL8373_IGMP_CTRL_LEAVE_TIMER_MASK (0x7 << RTL8373_IGMP_CTRL_LEAVE_TIMER_OFFSET) + #define RTL8373_IGMP_CTRL_FAST_LEAVE_EN_OFFSET (4) + #define RTL8373_IGMP_CTRL_FAST_LEAVE_EN_MASK (0x1 << RTL8373_IGMP_CTRL_FAST_LEAVE_EN_OFFSET) + #define RTL8373_IGMP_CTRL_CKS_ERR_OP_OFFSET (2) + #define RTL8373_IGMP_CTRL_CKS_ERR_OP_MASK (0x3 << RTL8373_IGMP_CTRL_CKS_ERR_OP_OFFSET) + #define RTL8373_IGMP_CTRL_IGMP_MLD_EN_OFFSET (0) + #define RTL8373_IGMP_CTRL_IGMP_MLD_EN_MASK (0x1 << RTL8373_IGMP_CTRL_IGMP_MLD_EN_OFFSET) + +#define RTL8373_IGMP_QUERY_INTVL_ADDR (0x5294) + #define RTL8373_IGMP_QUERY_INTVL_VALUE_OFFSET (0) + #define RTL8373_IGMP_QUERY_INTVL_VALUE_MASK (0xFFFF << RTL8373_IGMP_QUERY_INTVL_VALUE_OFFSET) + +#define RTL8373_IGMP_DYN_ROUTER_INFO_ADDR (0x5298) + #define RTL8373_IGMP_DYN_ROUTER_INFO_ROUTER_PORT_FORBID_2_OFFSET (15) + #define RTL8373_IGMP_DYN_ROUTER_INFO_ROUTER_PORT_FORBID_2_MASK (0x1 << RTL8373_IGMP_DYN_ROUTER_INFO_ROUTER_PORT_FORBID_2_OFFSET) + #define RTL8373_IGMP_DYN_ROUTER_INFO_PORT2_ID_OFFSET (11) + #define RTL8373_IGMP_DYN_ROUTER_INFO_PORT2_ID_MASK (0xF << RTL8373_IGMP_DYN_ROUTER_INFO_PORT2_ID_OFFSET) + #define RTL8373_IGMP_DYN_ROUTER_INFO_TIMER2_OFFSET (8) + #define RTL8373_IGMP_DYN_ROUTER_INFO_TIMER2_MASK (0x7 << RTL8373_IGMP_DYN_ROUTER_INFO_TIMER2_OFFSET) + #define RTL8373_IGMP_DYN_ROUTER_INFO_ROUTER_PORT_FORBID_1_OFFSET (7) + #define RTL8373_IGMP_DYN_ROUTER_INFO_ROUTER_PORT_FORBID_1_MASK (0x1 << RTL8373_IGMP_DYN_ROUTER_INFO_ROUTER_PORT_FORBID_1_OFFSET) + #define RTL8373_IGMP_DYN_ROUTER_INFO_PORT1_ID_OFFSET (3) + #define RTL8373_IGMP_DYN_ROUTER_INFO_PORT1_ID_MASK (0xF << RTL8373_IGMP_DYN_ROUTER_INFO_PORT1_ID_OFFSET) + #define RTL8373_IGMP_DYN_ROUTER_INFO_TIMER1_OFFSET (0) + #define RTL8373_IGMP_DYN_ROUTER_INFO_TIMER1_MASK (0x7 << RTL8373_IGMP_DYN_ROUTER_INFO_TIMER1_OFFSET) + +#define RTL8373_IGMP_ROUTER_PORT_CRTL_ADDR (0x529C) + #define RTL8373_IGMP_ROUTER_PORT_CRTL_ALLOW_DYN_ROTR_PMSK_OFFSET (16) + #define RTL8373_IGMP_ROUTER_PORT_CRTL_ALLOW_DYN_ROTR_PMSK_MASK (0x3FF << RTL8373_IGMP_ROUTER_PORT_CRTL_ALLOW_DYN_ROTR_PMSK_OFFSET) + #define RTL8373_IGMP_ROUTER_PORT_CRTL_STIC_PMSK_OFFSET (0) + #define RTL8373_IGMP_ROUTER_PORT_CRTL_STIC_PMSK_MASK (0x3FF << RTL8373_IGMP_ROUTER_PORT_CRTL_STIC_PMSK_OFFSET) + +#define RTL8373_IGMP_PORT_CTRL_ADDR(port) (0x52A0 + (((port) << 2))) /* port: 0-9 */ + #define RTL8373_IGMP_PORT_CTRL_MAX_GROUP_NUM_OFFSET (16) + #define RTL8373_IGMP_PORT_CTRL_MAX_GROUP_NUM_MASK (0xFF << RTL8373_IGMP_PORT_CTRL_MAX_GROUP_NUM_OFFSET) + #define RTL8373_IGMP_PORT_CTRL_ALLOW_QUERY_OFFSET (14) + #define RTL8373_IGMP_PORT_CTRL_ALLOW_QUERY_MASK (0x1 << RTL8373_IGMP_PORT_CTRL_ALLOW_QUERY_OFFSET) + #define RTL8373_IGMP_PORT_CTRL_ALLOW_REPORT_OFFSET (13) + #define RTL8373_IGMP_PORT_CTRL_ALLOW_REPORT_MASK (0x1 << RTL8373_IGMP_PORT_CTRL_ALLOW_REPORT_OFFSET) + #define RTL8373_IGMP_PORT_CTRL_ALLOW_LEAVE_OFFSET (12) + #define RTL8373_IGMP_PORT_CTRL_ALLOW_LEAVE_MASK (0x1 << RTL8373_IGMP_PORT_CTRL_ALLOW_LEAVE_OFFSET) + #define RTL8373_IGMP_PORT_CTRL_ALLOW_MRP_OFFSET (11) + #define RTL8373_IGMP_PORT_CTRL_ALLOW_MRP_MASK (0x1 << RTL8373_IGMP_PORT_CTRL_ALLOW_MRP_OFFSET) + #define RTL8373_IGMP_PORT_CTRL_ALLOW_MC_DATA_OFFSET (10) + #define RTL8373_IGMP_PORT_CTRL_ALLOW_MC_DATA_MASK (0x1 << RTL8373_IGMP_PORT_CTRL_ALLOW_MC_DATA_OFFSET) + #define RTL8373_IGMP_PORT_CTRL_MLDV2_OP_OFFSET (8) + #define RTL8373_IGMP_PORT_CTRL_MLDV2_OP_MASK (0x3 << RTL8373_IGMP_PORT_CTRL_MLDV2_OP_OFFSET) + #define RTL8373_IGMP_PORT_CTRL_MLDV1_OP_OFFSET (6) + #define RTL8373_IGMP_PORT_CTRL_MLDV1_OP_MASK (0x3 << RTL8373_IGMP_PORT_CTRL_MLDV1_OP_OFFSET) + #define RTL8373_IGMP_PORT_CTRL_IGMPV3_OP_OFFSET (4) + #define RTL8373_IGMP_PORT_CTRL_IGMPV3_OP_MASK (0x3 << RTL8373_IGMP_PORT_CTRL_IGMPV3_OP_OFFSET) + #define RTL8373_IGMP_PORT_CTRL_IGMPV2_OP_OFFSET (2) + #define RTL8373_IGMP_PORT_CTRL_IGMPV2_OP_MASK (0x3 << RTL8373_IGMP_PORT_CTRL_IGMPV2_OP_OFFSET) + #define RTL8373_IGMP_PORT_CTRL_IGMPV1_OP_OFFSET (0) + #define RTL8373_IGMP_PORT_CTRL_IGMPV1_OP_MASK (0x3 << RTL8373_IGMP_PORT_CTRL_IGMPV1_OP_OFFSET) + +#define RTL8373_PORT_CURR_GROUP_ADDR(port) (0x52C8 + (((port >> 2) << 2))) /* port: 0-9 */ + #define RTL8373_PORT_CURR_GROUP_NUM_OFFSET(port) ((port & 0x3) << 3) + #define RTL8373_PORT_CURR_GROUP_NUM_MASK(port) (0xFF << RTL8373_PORT_CURR_GROUP_NUM_OFFSET(port)) + +#define RTL8373_IGMP_TBL_USAGE_ADDR(index) (0x52D4 + (((index >> 5) << 2))) /* index: 0-255 */ + #define RTL8373_IGMP_TBL_USAGE_LIST_BIT_OFFSET(index) (index % 0x20) + #define RTL8373_IGMP_TBL_USAGE_LIST_BIT_MASK(index) (0x1 << RTL8373_IGMP_TBL_USAGE_LIST_BIT_OFFSET(index)) + +#define RTL8373_IGMP_TRAP_CTRL_ADDR (0x50BC) + #define RTL8373_IGMP_TRAP_CTRL_CPU_PMSK_OFFSET (16) + #define RTL8373_IGMP_TRAP_CTRL_CPU_PMSK_MASK (0x3 << RTL8373_IGMP_TRAP_CTRL_CPU_PMSK_OFFSET) + #define RTL8373_IGMP_TRAP_CTRL_PRI_OFFSET (0) + #define RTL8373_IGMP_TRAP_CTRL_PRI_MASK (0x7 << RTL8373_IGMP_TRAP_CTRL_PRI_OFFSET) + +/* + * Feature: Port Isolation + */ +#define RTL8373_PORT_ISO_PORT_PMSK_ADDR(port) (0x50C0 + (((port) << 2))) /* port: 0-9 */ + #define RTL8373_PORT_ISO_PORT_PMSK_PMSK_OFFSET (0) + #define RTL8373_PORT_ISO_PORT_PMSK_PMSK_MASK (0x3FF << RTL8373_PORT_ISO_PORT_PMSK_PMSK_OFFSET) + +/* + * Feature: Port Mirror + */ +#define RTL8373_MIR_CTRL_ADDR (0x50E8) + #define RTL8373_MIR_CTRL_MIR_REALKEEP_EN_OFFSET (7) + #define RTL8373_MIR_CTRL_MIR_REALKEEP_EN_MASK (0x1 << RTL8373_MIR_CTRL_MIR_REALKEEP_EN_OFFSET) + #define RTL8373_MIR_CTRL_MIR_RX_ISOLATE_LKY_OFFSET (6) + #define RTL8373_MIR_CTRL_MIR_RX_ISOLATE_LKY_MASK (0x1 << RTL8373_MIR_CTRL_MIR_RX_ISOLATE_LKY_OFFSET) + #define RTL8373_MIR_CTRL_MIR_TX_ISOLATE_LKY_OFFSET (5) + #define RTL8373_MIR_CTRL_MIR_TX_ISOLATE_LKY_MASK (0x1 << RTL8373_MIR_CTRL_MIR_TX_ISOLATE_LKY_OFFSET) + #define RTL8373_MIR_CTRL_MIR_RX_VLAN_LKY_OFFSET (4) + #define RTL8373_MIR_CTRL_MIR_RX_VLAN_LKY_MASK (0x1 << RTL8373_MIR_CTRL_MIR_RX_VLAN_LKY_OFFSET) + #define RTL8373_MIR_CTRL_MIR_TX_VLAN_LKY_OFFSET (3) + #define RTL8373_MIR_CTRL_MIR_TX_VLAN_LKY_MASK (0x1 << RTL8373_MIR_CTRL_MIR_TX_VLAN_LKY_OFFSET) + #define RTL8373_MIR_CTRL_MIRROR_ACL_OVERRIDE_EN_OFFSET (2) + #define RTL8373_MIR_CTRL_MIRROR_ACL_OVERRIDE_EN_MASK (0x1 << RTL8373_MIR_CTRL_MIRROR_ACL_OVERRIDE_EN_OFFSET) + #define RTL8373_MIR_CTRL_MIRROR_TX_OVERRIDE_EN_OFFSET (1) + #define RTL8373_MIR_CTRL_MIRROR_TX_OVERRIDE_EN_MASK (0x1 << RTL8373_MIR_CTRL_MIRROR_TX_OVERRIDE_EN_OFFSET) + #define RTL8373_MIR_CTRL_MIRROR_RX_OVERRIDE_EN_OFFSET (0) + #define RTL8373_MIR_CTRL_MIRROR_RX_OVERRIDE_EN_MASK (0x1 << RTL8373_MIR_CTRL_MIRROR_RX_OVERRIDE_EN_OFFSET) + +#define RTL8373_MIR_SET_CTRL_ADDR (0x6048) + #define RTL8373_MIR_SET_CTRL_MIR_ISO_OFFSET (6) + #define RTL8373_MIR_SET_CTRL_MIR_ISO_MASK (0x1 << RTL8373_MIR_SET_CTRL_MIR_ISO_OFFSET) + #define RTL8373_MIR_SET_CTRL_MIR_RX_TX_SEL_OFFSET (5) + #define RTL8373_MIR_SET_CTRL_MIR_RX_TX_SEL_MASK (0x1 << RTL8373_MIR_SET_CTRL_MIR_RX_TX_SEL_OFFSET) + #define RTL8373_MIR_SET_CTRL_MTP_PORT_OFFSET (1) + #define RTL8373_MIR_SET_CTRL_MTP_PORT_MASK (0xF << RTL8373_MIR_SET_CTRL_MTP_PORT_OFFSET) + #define RTL8373_MIR_SET_CTRL_MIR_EN_OFFSET (0) + #define RTL8373_MIR_SET_CTRL_MIR_EN_MASK (0x1 << RTL8373_MIR_SET_CTRL_MIR_EN_OFFSET) + +#define RTL8373_MIR_SET_PMSK_ADDR (0x604C) + #define RTL8373_MIR_SET_PMSK_RX_PMSK_OFFSET (16) + #define RTL8373_MIR_SET_PMSK_RX_PMSK_MASK (0x3FF << RTL8373_MIR_SET_PMSK_RX_PMSK_OFFSET) + #define RTL8373_MIR_SET_PMSK_TX_PMSK_OFFSET (0) + #define RTL8373_MIR_SET_PMSK_TX_PMSK_MASK (0x3FF << RTL8373_MIR_SET_PMSK_TX_PMSK_OFFSET) + +#define RTL8373_MIR_SAMPLE_CRTL_ADDR (0x50EC) + #define RTL8373_MIR_SAMPLE_CRTL_RATE_OFFSET (0) + #define RTL8373_MIR_SAMPLE_CRTL_RATE_MASK (0xFFFF << RTL8373_MIR_SAMPLE_CRTL_RATE_OFFSET) + +#define RTL8373_MIR_MATCHED_ADDR (0x50F0) + #define RTL8373_MIR_MATCHED_PKT_CNT_OFFSET (16) + #define RTL8373_MIR_MATCHED_PKT_CNT_MASK (0xFFFF << RTL8373_MIR_MATCHED_PKT_CNT_OFFSET) + #define RTL8373_MIR_MATCHED_SAMPLE_PKT_CNT_OFFSET (0) + #define RTL8373_MIR_MATCHED_SAMPLE_PKT_CNT_MASK (0xFFFF << RTL8373_MIR_MATCHED_SAMPLE_PKT_CNT_OFFSET) + +/* + * Feature: RSPAN + */ +#define RTL8373_MIR_RSPAN_CTRL_ADDR (0x6050) + #define RTL8373_MIR_RSPAN_CTRL_RX_TAG_EN_OFFSET (0) + #define RTL8373_MIR_RSPAN_CTRL_RX_TAG_EN_MASK (0x1 << RTL8373_MIR_RSPAN_CTRL_RX_TAG_EN_OFFSET) + +#define RTL8373_MIR_RSPAN_TAG_CTRL_ADDR (0x6740) + #define RTL8373_MIR_RSPAN_TAG_CTRL_TPID_OFFSET (16) + #define RTL8373_MIR_RSPAN_TAG_CTRL_TPID_MASK (0xFFFF << RTL8373_MIR_RSPAN_TAG_CTRL_TPID_OFFSET) + #define RTL8373_MIR_RSPAN_TAG_CTRL_PRI_OFFSET (13) + #define RTL8373_MIR_RSPAN_TAG_CTRL_PRI_MASK (0x7 << RTL8373_MIR_RSPAN_TAG_CTRL_PRI_OFFSET) + #define RTL8373_MIR_RSPAN_TAG_CTRL_CFI_OFFSET (12) + #define RTL8373_MIR_RSPAN_TAG_CTRL_CFI_MASK (0x1 << RTL8373_MIR_RSPAN_TAG_CTRL_CFI_OFFSET) + #define RTL8373_MIR_RSPAN_TAG_CTRL_VID_OFFSET (0) + #define RTL8373_MIR_RSPAN_TAG_CTRL_VID_MASK (0xFFF << RTL8373_MIR_RSPAN_TAG_CTRL_VID_OFFSET) + +#define RTL8373_MIR_RSPAN_TX_PORT_CTRL_ADDR (0x6744) + #define RTL8373_MIR_RSPAN_TX_PORT_CTRL_TAG_ADD_OFFSET (0) + #define RTL8373_MIR_RSPAN_TX_PORT_CTRL_TAG_ADD_MASK (0x3FF << RTL8373_MIR_RSPAN_TX_PORT_CTRL_TAG_ADD_OFFSET) + +#define RTL8373_MIR_RSPAN_RX_ACT_ADDR (0x6748) + #define RTL8373_MIR_RSPAN_RX_ACT_TAG_RM_OFFSET (0) + #define RTL8373_MIR_RSPAN_RX_ACT_TAG_RM_MASK (0x1 << RTL8373_MIR_RSPAN_RX_ACT_TAG_RM_OFFSET) + +/* + * Feature: ACL Module + */ +#define RTL8373_ACL_CTRL_ADDR (0x4810) + #define RTL8373_ACL_CTRL_TABLE_RST_OFFSET (0) + #define RTL8373_ACL_CTRL_TABLE_RST_MASK (0x1 << RTL8373_ACL_CTRL_TABLE_RST_OFFSET) + +#define RTL8373_ACL_GPIO_CTRL_ADDR (0x4814) + #define RTL8373_ACL_GPIO_CTRL_DFLT_PLTY_OFFSET (0) + #define RTL8373_ACL_GPIO_CTRL_DFLT_PLTY_MASK (0x1 << RTL8373_ACL_GPIO_CTRL_DFLT_PLTY_OFFSET) + +#define RTL8373_ACL_PORT_EN_ADDR (0x4818) + #define RTL8373_ACL_PORT_EN_PMSK_OFFSET (0) + #define RTL8373_ACL_PORT_EN_PMSK_MASK (0x3FF << RTL8373_ACL_PORT_EN_PMSK_OFFSET) + +#define RTL8373_ACL_PORT_UNMATCH_PERMIT_ADDR (0x481C) + #define RTL8373_ACL_PORT_UNMATCH_PERMIT_PMSK_ACT_OFFSET (0) + #define RTL8373_ACL_PORT_UNMATCH_PERMIT_PMSK_ACT_MASK (0x3FF << RTL8373_ACL_PORT_UNMATCH_PERMIT_PMSK_ACT_OFFSET) + +#define RTL8373_ACL_TEMPLATE_CTRL_ADDR(index) (0x4820 + (((index) << 3))) /* index: 0-4 */ + #define RTL8373_ACL_TEMPLATE_CTRL_FILED7_TYPE_OFFSET (24) + #define RTL8373_ACL_TEMPLATE_CTRL_FILED7_TYPE_MASK (0xFF << RTL8373_ACL_TEMPLATE_CTRL_FILED7_TYPE_OFFSET) + #define RTL8373_ACL_TEMPLATE_CTRL_FILED6_TYPE_OFFSET (16) + #define RTL8373_ACL_TEMPLATE_CTRL_FILED6_TYPE_MASK (0xFF << RTL8373_ACL_TEMPLATE_CTRL_FILED6_TYPE_OFFSET) + #define RTL8373_ACL_TEMPLATE_CTRL_FILED5_TYPE_OFFSET (8) + #define RTL8373_ACL_TEMPLATE_CTRL_FILED5_TYPE_MASK (0xFF << RTL8373_ACL_TEMPLATE_CTRL_FILED5_TYPE_OFFSET) + #define RTL8373_ACL_TEMPLATE_CTRL_FILED4_TYPE_OFFSET (0) + #define RTL8373_ACL_TEMPLATE_CTRL_FILED4_TYPE_MASK (0xFF << RTL8373_ACL_TEMPLATE_CTRL_FILED4_TYPE_OFFSET) + #define RTL8373_ACL_TEMPLATE_CTRL_FILED3_TYPE_OFFSET (56) + #define RTL8373_ACL_TEMPLATE_CTRL_FILED3_TYPE_MASK (0xFF << RTL8373_ACL_TEMPLATE_CTRL_FILED3_TYPE_OFFSET) + #define RTL8373_ACL_TEMPLATE_CTRL_FILED2_TYPE_OFFSET (48) + #define RTL8373_ACL_TEMPLATE_CTRL_FILED2_TYPE_MASK (0xFF << RTL8373_ACL_TEMPLATE_CTRL_FILED2_TYPE_OFFSET) + #define RTL8373_ACL_TEMPLATE_CTRL_FILED1_TYPE_OFFSET (40) + #define RTL8373_ACL_TEMPLATE_CTRL_FILED1_TYPE_MASK (0xFF << RTL8373_ACL_TEMPLATE_CTRL_FILED1_TYPE_OFFSET) + #define RTL8373_ACL_TEMPLATE_CTRL_FILED0_TYPE_OFFSET (32) + #define RTL8373_ACL_TEMPLATE_CTRL_FILED0_TYPE_MASK (0xFF << RTL8373_ACL_TEMPLATE_CTRL_FILED0_TYPE_OFFSET) + +#define RTL8373_ACL_ACT_CTRL_ADDR(index) (0x4848 + (((index) << 2))) /* index: 0-95 */ + #define RTL8373_ACL_ACT_CTRL_NOT_OFFSET (8) + #define RTL8373_ACL_ACT_CTRL_NOT_MASK (0x1 << RTL8373_ACL_ACT_CTRL_NOT_OFFSET) + #define RTL8373_ACL_ACT_CTRL_BYPASS_CTRL_BIT_OFFSET (7) + #define RTL8373_ACL_ACT_CTRL_BYPASS_CTRL_BIT_MASK (0x1 << RTL8373_ACL_ACT_CTRL_BYPASS_CTRL_BIT_OFFSET) + #define RTL8373_ACL_ACT_CTRL_GPIO_CTRL_BIT_OFFSET (6) + #define RTL8373_ACL_ACT_CTRL_GPIO_CTRL_BIT_MASK (0x1 << RTL8373_ACL_ACT_CTRL_GPIO_CTRL_BIT_OFFSET) + #define RTL8373_ACL_ACT_CTRL_FWD_CTRL_BIT_OFFSET (5) + #define RTL8373_ACL_ACT_CTRL_FWD_CTRL_BIT_MASK (0x1 << RTL8373_ACL_ACT_CTRL_FWD_CTRL_BIT_OFFSET) + #define RTL8373_ACL_ACT_CTRL_POLIC_LOG_CTRL_BIT_OFFSET (4) + #define RTL8373_ACL_ACT_CTRL_POLIC_LOG_CTRL_BIT_MASK (0x1 << RTL8373_ACL_ACT_CTRL_POLIC_LOG_CTRL_BIT_OFFSET) + #define RTL8373_ACL_ACT_CTRL_RMK_CTRL_BIT_OFFSET (3) + #define RTL8373_ACL_ACT_CTRL_RMK_CTRL_BIT_MASK (0x1 << RTL8373_ACL_ACT_CTRL_RMK_CTRL_BIT_OFFSET) + #define RTL8373_ACL_ACT_CTRL_PRI_CTRL_BIT_OFFSET (2) + #define RTL8373_ACL_ACT_CTRL_PRI_CTRL_BIT_MASK (0x1 << RTL8373_ACL_ACT_CTRL_PRI_CTRL_BIT_OFFSET) + #define RTL8373_ACL_ACT_CTRL_SVLAN_CTRL_BIT_OFFSET (1) + #define RTL8373_ACL_ACT_CTRL_SVLAN_CTRL_BIT_MASK (0x1 << RTL8373_ACL_ACT_CTRL_SVLAN_CTRL_BIT_OFFSET) + #define RTL8373_ACL_ACT_CTRL_CVLAN_CTRL_BIT_OFFSET (0) + #define RTL8373_ACL_ACT_CTRL_CVLAN_CTRL_BIT_MASK (0x1 << RTL8373_ACL_ACT_CTRL_CVLAN_CTRL_BIT_OFFSET) + +#define RTL8373_ACL_HIT_INDICATOR_ADDR (0x49C8) + #define RTL8373_ACL_HIT_INDICATOR_BYPASS_ACT_HIT_OFFSET (31) + #define RTL8373_ACL_HIT_INDICATOR_BYPASS_ACT_HIT_MASK (0x1 << RTL8373_ACL_HIT_INDICATOR_BYPASS_ACT_HIT_OFFSET) + #define RTL8373_ACL_HIT_INDICATOR_BYPASS_RULE_IDX_OFFSET (24) + #define RTL8373_ACL_HIT_INDICATOR_BYPASS_RULE_IDX_MASK (0x7F << RTL8373_ACL_HIT_INDICATOR_BYPASS_RULE_IDX_OFFSET) + #define RTL8373_ACL_HIT_INDICATOR_GPO_ACT_HIT_OFFSET (23) + #define RTL8373_ACL_HIT_INDICATOR_GPO_ACT_HIT_MASK (0x1 << RTL8373_ACL_HIT_INDICATOR_GPO_ACT_HIT_OFFSET) + #define RTL8373_ACL_HIT_INDICATOR_GPO_RULE_IDX_OFFSET (16) + #define RTL8373_ACL_HIT_INDICATOR_GPO_RULE_IDX_MASK (0x7F << RTL8373_ACL_HIT_INDICATOR_GPO_RULE_IDX_OFFSET) + #define RTL8373_ACL_HIT_INDICATOR_FWD_ACT_HIT_OFFSET (15) + #define RTL8373_ACL_HIT_INDICATOR_FWD_ACT_HIT_MASK (0x1 << RTL8373_ACL_HIT_INDICATOR_FWD_ACT_HIT_OFFSET) + #define RTL8373_ACL_HIT_INDICATOR_FWD_RULE_IDX_OFFSET (8) + #define RTL8373_ACL_HIT_INDICATOR_FWD_RULE_IDX_MASK (0x7F << RTL8373_ACL_HIT_INDICATOR_FWD_RULE_IDX_OFFSET) + #define RTL8373_ACL_HIT_INDICATOR_POLIC_LOG_ACT_HIT_OFFSET (7) + #define RTL8373_ACL_HIT_INDICATOR_POLIC_LOG_ACT_HIT_MASK (0x1 << RTL8373_ACL_HIT_INDICATOR_POLIC_LOG_ACT_HIT_OFFSET) + #define RTL8373_ACL_HIT_INDICATOR_POLIC_LOG_RULE_IDX_OFFSET (0) + #define RTL8373_ACL_HIT_INDICATOR_POLIC_LOG_RULE_IDX_MASK (0x7F << RTL8373_ACL_HIT_INDICATOR_POLIC_LOG_RULE_IDX_OFFSET) + #define RTL8373_ACL_HIT_INDICATOR_RMK_ACT_HIT_OFFSET (63) + #define RTL8373_ACL_HIT_INDICATOR_RMK_ACT_HIT_MASK (0x1 << RTL8373_ACL_HIT_INDICATOR_RMK_ACT_HIT_OFFSET) + #define RTL8373_ACL_HIT_INDICATOR_P1_DSCP_RULE_IDX_OFFSET (56) + #define RTL8373_ACL_HIT_INDICATOR_P1_DSCP_RULE_IDX_MASK (0x7F << RTL8373_ACL_HIT_INDICATOR_P1_DSCP_RULE_IDX_OFFSET) + #define RTL8373_ACL_HIT_INDICATOR_PRI_ACT_HIT_OFFSET (55) + #define RTL8373_ACL_HIT_INDICATOR_PRI_ACT_HIT_MASK (0x1 << RTL8373_ACL_HIT_INDICATOR_PRI_ACT_HIT_OFFSET) + #define RTL8373_ACL_HIT_INDICATOR_PRI_RULE_IDX_OFFSET (48) + #define RTL8373_ACL_HIT_INDICATOR_PRI_RULE_IDX_MASK (0x7F << RTL8373_ACL_HIT_INDICATOR_PRI_RULE_IDX_OFFSET) + #define RTL8373_ACL_HIT_INDICATOR_SVLAN_ACT_HIT_OFFSET (47) + #define RTL8373_ACL_HIT_INDICATOR_SVLAN_ACT_HIT_MASK (0x1 << RTL8373_ACL_HIT_INDICATOR_SVLAN_ACT_HIT_OFFSET) + #define RTL8373_ACL_HIT_INDICATOR_SVLAN_RULE_IDX_OFFSET (40) + #define RTL8373_ACL_HIT_INDICATOR_SVLAN_RULE_IDX_MASK (0x7F << RTL8373_ACL_HIT_INDICATOR_SVLAN_RULE_IDX_OFFSET) + #define RTL8373_ACL_HIT_INDICATOR_CVLAN_ACT_HIT_OFFSET (39) + #define RTL8373_ACL_HIT_INDICATOR_CVLAN_ACT_HIT_MASK (0x1 << RTL8373_ACL_HIT_INDICATOR_CVLAN_ACT_HIT_OFFSET) + #define RTL8373_ACL_HIT_INDICATOR_CVLAN_RULE_IDX_OFFSET (32) + #define RTL8373_ACL_HIT_INDICATOR_CVLAN_RULE_IDX_MASK (0x7F << RTL8373_ACL_HIT_INDICATOR_CVLAN_RULE_IDX_OFFSET) + +/* + * Feature: Range Check (port/vlan/ip/L4port) + */ +#define RTL8373_RNG_CHK_VID_ADDR(index) (0x49D0 + (((index) << 2))) /* index: 0-15 */ + #define RTL8373_RNG_CHK_VID_UPPER_OFFSET (14) + #define RTL8373_RNG_CHK_VID_UPPER_MASK (0xFFF << RTL8373_RNG_CHK_VID_UPPER_OFFSET) + #define RTL8373_RNG_CHK_VID_LOWER_OFFSET (2) + #define RTL8373_RNG_CHK_VID_LOWER_MASK (0xFFF << RTL8373_RNG_CHK_VID_LOWER_OFFSET) + #define RTL8373_RNG_CHK_VID_TYPE_OFFSET (0) + #define RTL8373_RNG_CHK_VID_TYPE_MASK (0x3 << RTL8373_RNG_CHK_VID_TYPE_OFFSET) + +#define RTL8373_RNG_CHK_IP_ADDR(index) (0x4A10 + (((index) * 12))) /* index: 0-15 */ + #define RTL8373_RNG_CHK_IP_TYPE_OFFSET (0) + #define RTL8373_RNG_CHK_IP_TYPE_MASK (0x7 << RTL8373_RNG_CHK_IP_TYPE_OFFSET) + #define RTL8373_RNG_CHK_IP_UPPER_OFFSET (32) + #define RTL8373_RNG_CHK_IP_UPPER_MASK (0xFFFFFFFF << RTL8373_RNG_CHK_IP_UPPER_OFFSET) + #define RTL8373_RNG_CHK_IP_LOWER_OFFSET (64) + #define RTL8373_RNG_CHK_IP_LOWER_MASK (0xFFFFFFFF << RTL8373_RNG_CHK_IP_LOWER_OFFSET) + +#define RTL8373_RNG_CHK_PORT_ADDR(index) (0x4AD0 + (((index) << 3))) /* index: 0-15 */ + #define RTL8373_RNG_CHK_PORT_TYPE_OFFSET (0) + #define RTL8373_RNG_CHK_PORT_TYPE_MASK (0x3 << RTL8373_RNG_CHK_PORT_TYPE_OFFSET) + #define RTL8373_RNG_CHK_PORT_UPPER_OFFSET (48) + #define RTL8373_RNG_CHK_PORT_UPPER_MASK (0xFFFF << RTL8373_RNG_CHK_PORT_UPPER_OFFSET) + #define RTL8373_RNG_CHK_PORT_LOWER_OFFSET (32) + #define RTL8373_RNG_CHK_PORT_LOWER_MASK (0xFFFF << RTL8373_RNG_CHK_PORT_LOWER_OFFSET) + +/* + * Feature: ACL LOG COUNTER + */ +#define RTL8373_ACL_LOG_CNTR_RST_ADDR (0x4B50) + #define RTL8373_ACL_LOG_CNTR_RST_RST_OFFSET (0) + #define RTL8373_ACL_LOG_CNTR_RST_RST_MASK (0xFFFFFFFF << RTL8373_ACL_LOG_CNTR_RST_RST_OFFSET) + +#define RTL8373_ACL_CNTR_RST_VAL_ADDR (0x4B54) + #define RTL8373_ACL_CNTR_RST_VAL_VAL_OFFSET (0) + #define RTL8373_ACL_CNTR_RST_VAL_VAL_MASK (0x1 << RTL8373_ACL_CNTR_RST_VAL_VAL_OFFSET) + +#define RTL8373_ACL_LOG_CNTR_TYPE_ADDR (0x4B58) + #define RTL8373_ACL_LOG_CNTR_TYPE_TYPE_OFFSET (0) + #define RTL8373_ACL_LOG_CNTR_TYPE_TYPE_MASK (0xFFFF << RTL8373_ACL_LOG_CNTR_TYPE_TYPE_OFFSET) + +#define RTL8373_ACL_LOG_CNTR_MODE_ADDR (0x4B5C) + #define RTL8373_ACL_LOG_CNTR_MODE_MODE_OFFSET (0) + #define RTL8373_ACL_LOG_CNTR_MODE_MODE_MASK (0xFFFF << RTL8373_ACL_LOG_CNTR_MODE_MODE_OFFSET) + +#define RTL8373_ACL_LOG_CNTR_DATA_ADDR(index) (0x4B60 + (((index) << 2))) /* index: 0-31 */ + #define RTL8373_ACL_LOG_CNTR_DATA_CNTR_VAL_OFFSET (0) + #define RTL8373_ACL_LOG_CNTR_DATA_CNTR_VAL_MASK (0xFFFFFFFF << RTL8373_ACL_LOG_CNTR_DATA_CNTR_VAL_OFFSET) + +#define RTL8373_ACL_LATCH_TRIGGER_ADDR (0x4BE0) + #define RTL8373_ACL_LATCH_TRIGGER_CMD_OFFSET (0) + #define RTL8373_ACL_LATCH_TRIGGER_CMD_MASK (0x1 << RTL8373_ACL_LATCH_TRIGGER_CMD_OFFSET) + +#define RTL8373_ACL_LATCH_ADDR_ADDR (0x4BE4) + #define RTL8373_ACL_LATCH_ADDR_ADDR_OFFSET (0) + #define RTL8373_ACL_LATCH_ADDR_ADDR_MASK (0xFFFFFFFF << RTL8373_ACL_LATCH_ADDR_ADDR_OFFSET) + +#define RTL8373_ACL_LATCH_VAL_L_ADDR (0x4BE8) + #define RTL8373_ACL_LATCH_VAL_L_VAL_L_OFFSET (0) + #define RTL8373_ACL_LATCH_VAL_L_VAL_L_MASK (0xFFFFFFFF << RTL8373_ACL_LATCH_VAL_L_VAL_L_OFFSET) + +#define RTL8373_ACL_LATCH_VAL_H_ADDR (0x4BEC) + #define RTL8373_ACL_LATCH_VAL_H_VAL_H_OFFSET (0) + #define RTL8373_ACL_LATCH_VAL_H_VAL_H_MASK (0xFFFFFFFF << RTL8373_ACL_LATCH_VAL_H_VAL_H_OFFSET) + +/* + * Feature: PTP (Precision Time Protocol) + */ +#define RTL8373_PTP_TIME_TOD_DELAY_ADDR (0x7C20) + #define RTL8373_PTP_TIME_TOD_DELAY_TOD_DELAY_OFFSET (0) + #define RTL8373_PTP_TIME_TOD_DELAY_TOD_DELAY_MASK (0xFFFF << RTL8373_PTP_TIME_TOD_DELAY_TOD_DELAY_OFFSET) + +#define RTL8373_PTP_TIME_OP_DURATION_ADDR (0x7C24) + #define RTL8373_PTP_TIME_OP_DURATION_TIME_OP_DURATION_OFFSET (0) + #define RTL8373_PTP_TIME_OP_DURATION_TIME_OP_DURATION_MASK (0x3FF << RTL8373_PTP_TIME_OP_DURATION_TIME_OP_DURATION_OFFSET) + +#define RTL8373_PTP_DUMMY_RG02_ADDR (0x7C28) + #define RTL8373_PTP_DUMMY_RG02_PTP_DUMMY_RG02_OFFSET (0) + #define RTL8373_PTP_DUMMY_RG02_PTP_DUMMY_RG02_MASK (0xFFFFFFFF << RTL8373_PTP_DUMMY_RG02_PTP_DUMMY_RG02_OFFSET) + +#define RTL8373_PTP_DUMMY_RG03_ADDR (0x7C2C) + #define RTL8373_PTP_DUMMY_RG03_PTP_DUMMY_RG03_OFFSET (0) + #define RTL8373_PTP_DUMMY_RG03_PTP_DUMMY_RG03_MASK (0xFFFFFFFF << RTL8373_PTP_DUMMY_RG03_PTP_DUMMY_RG03_OFFSET) + +#define RTL8373_PTP_OTAG_CONFIG0_ADDR (0x7C30) + #define RTL8373_PTP_OTAG_CONFIG0_OTAG_TPID_0_OFFSET (0) + #define RTL8373_PTP_OTAG_CONFIG0_OTAG_TPID_0_MASK (0xFFFF << RTL8373_PTP_OTAG_CONFIG0_OTAG_TPID_0_OFFSET) + +#define RTL8373_PTP_OTAG_CONFIG1_ADDR (0x7C34) + #define RTL8373_PTP_OTAG_CONFIG1_OTAG_TPID_1_OFFSET (0) + #define RTL8373_PTP_OTAG_CONFIG1_OTAG_TPID_1_MASK (0xFFFF << RTL8373_PTP_OTAG_CONFIG1_OTAG_TPID_1_OFFSET) + +#define RTL8373_PTP_OTAG_CONFIG2_ADDR (0x7C38) + #define RTL8373_PTP_OTAG_CONFIG2_OTAG_TPID_2_OFFSET (0) + #define RTL8373_PTP_OTAG_CONFIG2_OTAG_TPID_2_MASK (0xFFFF << RTL8373_PTP_OTAG_CONFIG2_OTAG_TPID_2_OFFSET) + +#define RTL8373_PTP_OTAG_CONFIG3_ADDR (0x7C3C) + #define RTL8373_PTP_OTAG_CONFIG3_OTAG_TPID_3_OFFSET (0) + #define RTL8373_PTP_OTAG_CONFIG3_OTAG_TPID_3_MASK (0xFFFF << RTL8373_PTP_OTAG_CONFIG3_OTAG_TPID_3_OFFSET) + +#define RTL8373_PTP_ITAG_CONFIG0_ADDR (0x7C40) + #define RTL8373_PTP_ITAG_CONFIG0_ITAG_TPID_0_OFFSET (0) + #define RTL8373_PTP_ITAG_CONFIG0_ITAG_TPID_0_MASK (0xFFFF << RTL8373_PTP_ITAG_CONFIG0_ITAG_TPID_0_OFFSET) + +#define RTL8373_PTP_DUMMY_RG09_ADDR (0x7C44) + #define RTL8373_PTP_DUMMY_RG09_PTP_TIMER_RESERVE_RG09_OFFSET (0) + #define RTL8373_PTP_DUMMY_RG09_PTP_TIMER_RESERVE_RG09_MASK (0xFFFFFFFF << RTL8373_PTP_DUMMY_RG09_PTP_TIMER_RESERVE_RG09_OFFSET) + +#define RTL8373_PTP_DUMMY_RG10_ADDR (0x7C48) + #define RTL8373_PTP_DUMMY_RG10_PTP_TIMER_RESERVE_RG10_OFFSET (0) + #define RTL8373_PTP_DUMMY_RG10_PTP_TIMER_RESERVE_RG10_MASK (0xFFFFFFFF << RTL8373_PTP_DUMMY_RG10_PTP_TIMER_RESERVE_RG10_OFFSET) + +#define RTL8373_PTP_APPLY_FREQ_ADDR (0x7C4C) + #define RTL8373_PTP_APPLY_FREQ_APPLY_FREQ_OFFSET (0) + #define RTL8373_PTP_APPLY_FREQ_APPLY_FREQ_MASK (0x1 << RTL8373_PTP_APPLY_FREQ_APPLY_FREQ_OFFSET) + +#define RTL8373_PTP_TIME_FREQ0_ADDR (0x7C50) + #define RTL8373_PTP_TIME_FREQ0_CFG_PTP_TIME_FREQ0_OFFSET (0) + #define RTL8373_PTP_TIME_FREQ0_CFG_PTP_TIME_FREQ0_MASK (0xFFFF << RTL8373_PTP_TIME_FREQ0_CFG_PTP_TIME_FREQ0_OFFSET) + +#define RTL8373_PTP_TIME_FREQ1_ADDR (0x7C54) + #define RTL8373_PTP_TIME_FREQ1_CFG_PTP_TIME_FREQ1_OFFSET (0) + #define RTL8373_PTP_TIME_FREQ1_CFG_PTP_TIME_FREQ1_MASK (0xFFFF << RTL8373_PTP_TIME_FREQ1_CFG_PTP_TIME_FREQ1_OFFSET) + +#define RTL8373_PTP_CUR_TIME_FREQ0_ADDR (0x7C58) + #define RTL8373_PTP_CUR_TIME_FREQ0_CUR_PTP_TIME_FREQ0_OFFSET (0) + #define RTL8373_PTP_CUR_TIME_FREQ0_CUR_PTP_TIME_FREQ0_MASK (0xFFFF << RTL8373_PTP_CUR_TIME_FREQ0_CUR_PTP_TIME_FREQ0_OFFSET) + +#define RTL8373_PTP_CUR_TIME_FREQ1_ADDR (0x7C5C) + #define RTL8373_PTP_CUR_TIME_FREQ1_CUR_PTP_TIME_FREQ1_OFFSET (0) + #define RTL8373_PTP_CUR_TIME_FREQ1_CUR_PTP_TIME_FREQ1_MASK (0xFFFF << RTL8373_PTP_CUR_TIME_FREQ1_CUR_PTP_TIME_FREQ1_OFFSET) + +#define RTL8373_PTP_TIME_NSEC0_ADDR (0x7C60) + #define RTL8373_PTP_TIME_NSEC0_CFG_PTP_TIME_NSEC_L_OFFSET (0) + #define RTL8373_PTP_TIME_NSEC0_CFG_PTP_TIME_NSEC_L_MASK (0xFFFF << RTL8373_PTP_TIME_NSEC0_CFG_PTP_TIME_NSEC_L_OFFSET) + +#define RTL8373_PTP_TIME_NSEC1_ADDR (0x7C64) + #define RTL8373_PTP_TIME_NSEC1_CFG_TOD_VALID_OFFSET (15) + #define RTL8373_PTP_TIME_NSEC1_CFG_TOD_VALID_MASK (0x1 << RTL8373_PTP_TIME_NSEC1_CFG_TOD_VALID_OFFSET) + #define RTL8373_PTP_TIME_NSEC1_CFG_PTP_TIME_NSEC_H_OFFSET (0) + #define RTL8373_PTP_TIME_NSEC1_CFG_PTP_TIME_NSEC_H_MASK (0x3FFF << RTL8373_PTP_TIME_NSEC1_CFG_PTP_TIME_NSEC_H_OFFSET) + +#define RTL8373_PTP_TIME_SEC0_ADDR (0x7C68) + #define RTL8373_PTP_TIME_SEC0_CFG_PTP_TIME_SEC_L_OFFSET (0) + #define RTL8373_PTP_TIME_SEC0_CFG_PTP_TIME_SEC_L_MASK (0xFFFF << RTL8373_PTP_TIME_SEC0_CFG_PTP_TIME_SEC_L_OFFSET) + +#define RTL8373_PTP_TIME_SEC1_ADDR (0x7C6C) + #define RTL8373_PTP_TIME_SEC1_CFG_PTP_TIME_SEC_M_OFFSET (0) + #define RTL8373_PTP_TIME_SEC1_CFG_PTP_TIME_SEC_M_MASK (0xFFFF << RTL8373_PTP_TIME_SEC1_CFG_PTP_TIME_SEC_M_OFFSET) + +#define RTL8373_PTP_TIME_SEC2_ADDR (0x7C70) + #define RTL8373_PTP_TIME_SEC2_CFG_PTP_TIME_SEC_H_OFFSET (0) + #define RTL8373_PTP_TIME_SEC2_CFG_PTP_TIME_SEC_H_MASK (0xFFFF << RTL8373_PTP_TIME_SEC2_CFG_PTP_TIME_SEC_H_OFFSET) + +#define RTL8373_PTP_TIME_CRTL_ADDR (0x7C74) + #define RTL8373_PTP_TIME_CRTL_PTP_TIME_EXEC_OFFSET (2) + #define RTL8373_PTP_TIME_CRTL_PTP_TIME_EXEC_MASK (0x1 << RTL8373_PTP_TIME_CRTL_PTP_TIME_EXEC_OFFSET) + #define RTL8373_PTP_TIME_CRTL_PTP_TIME_CMD_OFFSET (0) + #define RTL8373_PTP_TIME_CRTL_PTP_TIME_CMD_MASK (0x3 << RTL8373_PTP_TIME_CRTL_PTP_TIME_CMD_OFFSET) + +#define RTL8373_PTP_TIME_NSEC_RD0_ADDR (0x7C78) + #define RTL8373_PTP_TIME_NSEC_RD0_RD_PTP_TIME_NSEC_L_OFFSET (0) + #define RTL8373_PTP_TIME_NSEC_RD0_RD_PTP_TIME_NSEC_L_MASK (0xFFFF << RTL8373_PTP_TIME_NSEC_RD0_RD_PTP_TIME_NSEC_L_OFFSET) + +#define RTL8373_PTP_TIME_NSEC_RD1_ADDR (0x7C7C) + #define RTL8373_PTP_TIME_NSEC_RD1_RD_PTP_TIME_NSEC_H_OFFSET (0) + #define RTL8373_PTP_TIME_NSEC_RD1_RD_PTP_TIME_NSEC_H_MASK (0x3FFF << RTL8373_PTP_TIME_NSEC_RD1_RD_PTP_TIME_NSEC_H_OFFSET) + +#define RTL8373_PTP_TIME_SEC_RD0_ADDR (0x7C80) + #define RTL8373_PTP_TIME_SEC_RD0_RD_PTP_TIME_SEC_L_OFFSET (0) + #define RTL8373_PTP_TIME_SEC_RD0_RD_PTP_TIME_SEC_L_MASK (0xFFFF << RTL8373_PTP_TIME_SEC_RD0_RD_PTP_TIME_SEC_L_OFFSET) + +#define RTL8373_PTP_TIME_SEC_RD1_ADDR (0x7C84) + #define RTL8373_PTP_TIME_SEC_RD1_RD_PTP_TIME_SEC_M_OFFSET (0) + #define RTL8373_PTP_TIME_SEC_RD1_RD_PTP_TIME_SEC_M_MASK (0xFFFF << RTL8373_PTP_TIME_SEC_RD1_RD_PTP_TIME_SEC_M_OFFSET) + +#define RTL8373_PTP_TIME_SEC_RD2_ADDR (0x7C88) + #define RTL8373_PTP_TIME_SEC_RD2_RD_PTP_TIME_SEC_H_OFFSET (0) + #define RTL8373_PTP_TIME_SEC_RD2_RD_PTP_TIME_SEC_H_MASK (0xFFFF << RTL8373_PTP_TIME_SEC_RD2_RD_PTP_TIME_SEC_H_OFFSET) + +#define RTL8373_PTP_CLKOUT_NSEC0_ADDR (0x7C8C) + #define RTL8373_PTP_CLKOUT_NSEC0_CLKOUT_PTP_TIME_NSEC_L_OFFSET (0) + #define RTL8373_PTP_CLKOUT_NSEC0_CLKOUT_PTP_TIME_NSEC_L_MASK (0xFFFF << RTL8373_PTP_CLKOUT_NSEC0_CLKOUT_PTP_TIME_NSEC_L_OFFSET) + +#define RTL8373_PTP_CLKOUT_NSEC1_ADDR (0x7C90) + #define RTL8373_PTP_CLKOUT_NSEC1_CLKOUT_PTP_RSV_OFFSET (14) + #define RTL8373_PTP_CLKOUT_NSEC1_CLKOUT_PTP_RSV_MASK (0x3 << RTL8373_PTP_CLKOUT_NSEC1_CLKOUT_PTP_RSV_OFFSET) + #define RTL8373_PTP_CLKOUT_NSEC1_CLKOUT_PTP_TIME_NSEC_H_OFFSET (0) + #define RTL8373_PTP_CLKOUT_NSEC1_CLKOUT_PTP_TIME_NSEC_H_MASK (0x3FFF << RTL8373_PTP_CLKOUT_NSEC1_CLKOUT_PTP_TIME_NSEC_H_OFFSET) + +#define RTL8373_PTP_CLKOUT_SEC0_ADDR (0x7C94) + #define RTL8373_PTP_CLKOUT_SEC0_CLKOUT_PTP_TIME_SEC_L_OFFSET (0) + #define RTL8373_PTP_CLKOUT_SEC0_CLKOUT_PTP_TIME_SEC_L_MASK (0xFFFF << RTL8373_PTP_CLKOUT_SEC0_CLKOUT_PTP_TIME_SEC_L_OFFSET) + +#define RTL8373_PTP_CLKOUT_SEC1_ADDR (0x7C98) + #define RTL8373_PTP_CLKOUT_SEC1_CLKOUT_PTP_TIME_SEC_M_OFFSET (0) + #define RTL8373_PTP_CLKOUT_SEC1_CLKOUT_PTP_TIME_SEC_M_MASK (0xFFFF << RTL8373_PTP_CLKOUT_SEC1_CLKOUT_PTP_TIME_SEC_M_OFFSET) + +#define RTL8373_PTP_CLKOUT_SEC2_ADDR (0x7C9C) + #define RTL8373_PTP_CLKOUT_SEC2_CLKOUT_PTP_TIME_SEC_H_OFFSET (0) + #define RTL8373_PTP_CLKOUT_SEC2_CLKOUT_PTP_TIME_SEC_H_MASK (0xFFFF << RTL8373_PTP_CLKOUT_SEC2_CLKOUT_PTP_TIME_SEC_H_OFFSET) + +#define RTL8373_PTP_CLKOUT_CTRL_ADDR (0x7CA0) + #define RTL8373_PTP_CLKOUT_CTRL_CFG_PULSE_RSV_OFFSET (3) + #define RTL8373_PTP_CLKOUT_CTRL_CFG_PULSE_RSV_MASK (0x1FFF << RTL8373_PTP_CLKOUT_CTRL_CFG_PULSE_RSV_OFFSET) + #define RTL8373_PTP_CLKOUT_CTRL_CFG_PULSE_MODE_OFFSET (2) + #define RTL8373_PTP_CLKOUT_CTRL_CFG_PULSE_MODE_MASK (0x1 << RTL8373_PTP_CLKOUT_CTRL_CFG_PULSE_MODE_OFFSET) + #define RTL8373_PTP_CLKOUT_CTRL_CFG_CLKOUT_EN_OFFSET (1) + #define RTL8373_PTP_CLKOUT_CTRL_CFG_CLKOUT_EN_MASK (0x1 << RTL8373_PTP_CLKOUT_CTRL_CFG_CLKOUT_EN_OFFSET) + #define RTL8373_PTP_CLKOUT_CTRL_RD_CLKOUT_RUN_OFFSET (0) + #define RTL8373_PTP_CLKOUT_CTRL_RD_CLKOUT_RUN_MASK (0x1 << RTL8373_PTP_CLKOUT_CTRL_RD_CLKOUT_RUN_OFFSET) + +#define RTL8373_PTP_CLKOUT_HALF_PERD_NS_L_ADDR (0x7CA4) + #define RTL8373_PTP_CLKOUT_HALF_PERD_NS_L_CFG_CLKOUT_HALF_PERIOD_NS_L_OFFSET (0) + #define RTL8373_PTP_CLKOUT_HALF_PERD_NS_L_CFG_CLKOUT_HALF_PERIOD_NS_L_MASK (0xFFFF << RTL8373_PTP_CLKOUT_HALF_PERD_NS_L_CFG_CLKOUT_HALF_PERIOD_NS_L_OFFSET) + +#define RTL8373_PTP_CLKOUT_HALF_PERD_NS_H_ADDR (0x7CA8) + #define RTL8373_PTP_CLKOUT_HALF_PERD_NS_H_CFG_CLKOUT_HALF_PERIOD_RSV_OFFSET (14) + #define RTL8373_PTP_CLKOUT_HALF_PERD_NS_H_CFG_CLKOUT_HALF_PERIOD_RSV_MASK (0x3 << RTL8373_PTP_CLKOUT_HALF_PERD_NS_H_CFG_CLKOUT_HALF_PERIOD_RSV_OFFSET) + #define RTL8373_PTP_CLKOUT_HALF_PERD_NS_H_CFG_CLKOUT_HALF_PERIOD_NS_H_OFFSET (0) + #define RTL8373_PTP_CLKOUT_HALF_PERD_NS_H_CFG_CLKOUT_HALF_PERIOD_NS_H_MASK (0x3FFF << RTL8373_PTP_CLKOUT_HALF_PERD_NS_H_CFG_CLKOUT_HALF_PERIOD_NS_H_OFFSET) + +#define RTL8373_PTP_TIME_OP_CTRL_ADDR (0x7CAC) + #define RTL8373_PTP_TIME_OP_CTRL_CFG_GPI_RSV_15_7_OFFSET (7) + #define RTL8373_PTP_TIME_OP_CTRL_CFG_GPI_RSV_15_7_MASK (0x1FF << RTL8373_PTP_TIME_OP_CTRL_CFG_GPI_RSV_15_7_OFFSET) + #define RTL8373_PTP_TIME_OP_CTRL_CFG_GPI_OP_OFFSET (4) + #define RTL8373_PTP_TIME_OP_CTRL_CFG_GPI_OP_MASK (0x7 << RTL8373_PTP_TIME_OP_CTRL_CFG_GPI_OP_OFFSET) + #define RTL8373_PTP_TIME_OP_CTRL_CFG_GPI_RISE_TRIG_OFFSET (3) + #define RTL8373_PTP_TIME_OP_CTRL_CFG_GPI_RISE_TRIG_MASK (0x1 << RTL8373_PTP_TIME_OP_CTRL_CFG_GPI_RISE_TRIG_OFFSET) + #define RTL8373_PTP_TIME_OP_CTRL_CFG_GPI_FALL_TRIG_OFFSET (2) + #define RTL8373_PTP_TIME_OP_CTRL_CFG_GPI_FALL_TRIG_MASK (0x1 << RTL8373_PTP_TIME_OP_CTRL_CFG_GPI_FALL_TRIG_OFFSET) + #define RTL8373_PTP_TIME_OP_CTRL_CFG_GPI_RSV_1_0_OFFSET (0) + #define RTL8373_PTP_TIME_OP_CTRL_CFG_GPI_RSV_1_0_MASK (0x3 << RTL8373_PTP_TIME_OP_CTRL_CFG_GPI_RSV_1_0_OFFSET) + +#define RTL8373_PTP_PPS_CTRL_ADDR (0x7CB0) + #define RTL8373_PTP_PPS_CTRL_CFG_PPS_RSV_OFFSET (7) + #define RTL8373_PTP_PPS_CTRL_CFG_PPS_RSV_MASK (0x1FF << RTL8373_PTP_PPS_CTRL_CFG_PPS_RSV_OFFSET) + #define RTL8373_PTP_PPS_CTRL_CFG_PPS_EN_OFFSET (6) + #define RTL8373_PTP_PPS_CTRL_CFG_PPS_EN_MASK (0x1 << RTL8373_PTP_PPS_CTRL_CFG_PPS_EN_OFFSET) + #define RTL8373_PTP_PPS_CTRL_CFG_PPS_WIDTH_OFFSET (0) + #define RTL8373_PTP_PPS_CTRL_CFG_PPS_WIDTH_MASK (0x3F << RTL8373_PTP_PPS_CTRL_CFG_PPS_WIDTH_OFFSET) + +#define RTL8373_PTP_TX_TIMESTAMP_RD0_ADDR (0x7CB4) + #define RTL8373_PTP_TX_TIMESTAMP_RD0_RD_TX_TIMESTAMP_VALID_OFFSET (15) + #define RTL8373_PTP_TX_TIMESTAMP_RD0_RD_TX_TIMESTAMP_VALID_MASK (0x1 << RTL8373_PTP_TX_TIMESTAMP_RD0_RD_TX_TIMESTAMP_VALID_OFFSET) + #define RTL8373_PTP_TX_TIMESTAMP_RD0_RD_PORT_ID_OFFSET (8) + #define RTL8373_PTP_TX_TIMESTAMP_RD0_RD_PORT_ID_MASK (0x3F << RTL8373_PTP_TX_TIMESTAMP_RD0_RD_PORT_ID_OFFSET) + #define RTL8373_PTP_TX_TIMESTAMP_RD0_RD_MSG_TYPE_OFFSET (6) + #define RTL8373_PTP_TX_TIMESTAMP_RD0_RD_MSG_TYPE_MASK (0x3 << RTL8373_PTP_TX_TIMESTAMP_RD0_RD_MSG_TYPE_OFFSET) + #define RTL8373_PTP_TX_TIMESTAMP_RD0_RD_SEQ_ID_H_OFFSET (0) + #define RTL8373_PTP_TX_TIMESTAMP_RD0_RD_SEQ_ID_H_MASK (0x3F << RTL8373_PTP_TX_TIMESTAMP_RD0_RD_SEQ_ID_H_OFFSET) + +#define RTL8373_PTP_TX_TIMESTAMP_RD1_ADDR (0x7CB8) + #define RTL8373_PTP_TX_TIMESTAMP_RD1_RD_SEQ_ID_L_OFFSET (6) + #define RTL8373_PTP_TX_TIMESTAMP_RD1_RD_SEQ_ID_L_MASK (0x3FF << RTL8373_PTP_TX_TIMESTAMP_RD1_RD_SEQ_ID_L_OFFSET) + #define RTL8373_PTP_TX_TIMESTAMP_RD1_RD_TX_TIMESTAMP_SEC_H_OFFSET (0) + #define RTL8373_PTP_TX_TIMESTAMP_RD1_RD_TX_TIMESTAMP_SEC_H_MASK (0x3F << RTL8373_PTP_TX_TIMESTAMP_RD1_RD_TX_TIMESTAMP_SEC_H_OFFSET) + +#define RTL8373_PTP_TX_TIMESTAMP_RD2_ADDR (0x7CBC) + #define RTL8373_PTP_TX_TIMESTAMP_RD2_RD_TX_TIMESTAMP_SEC_L_OFFSET (14) + #define RTL8373_PTP_TX_TIMESTAMP_RD2_RD_TX_TIMESTAMP_SEC_L_MASK (0x3 << RTL8373_PTP_TX_TIMESTAMP_RD2_RD_TX_TIMESTAMP_SEC_L_OFFSET) + #define RTL8373_PTP_TX_TIMESTAMP_RD2_RD_TX_TIMESTAMP_NSEC_H_OFFSET (0) + #define RTL8373_PTP_TX_TIMESTAMP_RD2_RD_TX_TIMESTAMP_NSEC_H_MASK (0x3FFF << RTL8373_PTP_TX_TIMESTAMP_RD2_RD_TX_TIMESTAMP_NSEC_H_OFFSET) + +#define RTL8373_PTP_TX_TIMESTAMP_RD3_ADDR (0x7CC0) + #define RTL8373_PTP_TX_TIMESTAMP_RD3_RD_TX_TIMESTAMP_NSEC_L_OFFSET (0) + #define RTL8373_PTP_TX_TIMESTAMP_RD3_RD_TX_TIMESTAMP_NSEC_L_MASK (0xFFFF << RTL8373_PTP_TX_TIMESTAMP_RD3_RD_TX_TIMESTAMP_NSEC_L_OFFSET) + +#define RTL8373_PTP_MIB_INTR_ADDR (0x7CC4) + #define RTL8373_PTP_MIB_INTR_CFG_MIB_EN_OFFSET (8) + #define RTL8373_PTP_MIB_INTR_CFG_MIB_EN_MASK (0x1 << RTL8373_PTP_MIB_INTR_CFG_MIB_EN_OFFSET) + #define RTL8373_PTP_MIB_INTR_RD_ISR_PPS_I_OFFSET (3) + #define RTL8373_PTP_MIB_INTR_RD_ISR_PPS_I_MASK (0x1 << RTL8373_PTP_MIB_INTR_RD_ISR_PPS_I_OFFSET) + #define RTL8373_PTP_MIB_INTR_CFG_IMR_PPS_I_OFFSET (2) + #define RTL8373_PTP_MIB_INTR_CFG_IMR_PPS_I_MASK (0x1 << RTL8373_PTP_MIB_INTR_CFG_IMR_PPS_I_OFFSET) + #define RTL8373_PTP_MIB_INTR_RD_ISR_PTP_OFFSET (1) + #define RTL8373_PTP_MIB_INTR_RD_ISR_PTP_MASK (0x1 << RTL8373_PTP_MIB_INTR_RD_ISR_PTP_OFFSET) + #define RTL8373_PTP_MIB_INTR_CFG_IMR_PTP_OFFSET (0) + #define RTL8373_PTP_MIB_INTR_CFG_IMR_PTP_MASK (0x1 << RTL8373_PTP_MIB_INTR_CFG_IMR_PTP_OFFSET) + +#define RTL8373_PTP_GLOBAL_DBG_ADDR (0x7CC8) + #define RTL8373_PTP_GLOBAL_DBG_CFG_DBG_SEL_MODE_OFFSET (8) + #define RTL8373_PTP_GLOBAL_DBG_CFG_DBG_SEL_MODE_MASK (0xFF << RTL8373_PTP_GLOBAL_DBG_CFG_DBG_SEL_MODE_OFFSET) + #define RTL8373_PTP_GLOBAL_DBG_CFG_DBG_SEL_PTP_OFFSET (4) + #define RTL8373_PTP_GLOBAL_DBG_CFG_DBG_SEL_PTP_MASK (0xF << RTL8373_PTP_GLOBAL_DBG_CFG_DBG_SEL_PTP_OFFSET) + #define RTL8373_PTP_GLOBAL_DBG_CFG_DBG_SEL_INST_OFFSET (0) + #define RTL8373_PTP_GLOBAL_DBG_CFG_DBG_SEL_INST_MASK (0xF << RTL8373_PTP_GLOBAL_DBG_CFG_DBG_SEL_INST_OFFSET) + +#define RTL8373_PTP_CLK_SRC_CTRL_ADDR (0x7CCC) + #define RTL8373_PTP_CLK_SRC_CTRL_CFG_CLK_RSV_OFFSET (1) + #define RTL8373_PTP_CLK_SRC_CTRL_CFG_CLK_RSV_MASK (0x7FFF << RTL8373_PTP_CLK_SRC_CTRL_CFG_CLK_RSV_OFFSET) + #define RTL8373_PTP_CLK_SRC_CTRL_CFG_CLK_SRC_OFFSET (0) + #define RTL8373_PTP_CLK_SRC_CTRL_CFG_CLK_SRC_MASK (0x1 << RTL8373_PTP_CLK_SRC_CTRL_CFG_CLK_SRC_OFFSET) + +#define RTL8373_PTP_CLKOUT_HALF_PERD_FS_L_ADDR (0x7CD0) + #define RTL8373_PTP_CLKOUT_HALF_PERD_FS_L_CFG_CLKOUT_HALF_PERIOD_FS_L_OFFSET (0) + #define RTL8373_PTP_CLKOUT_HALF_PERD_FS_L_CFG_CLKOUT_HALF_PERIOD_FS_L_MASK (0xFFFF << RTL8373_PTP_CLKOUT_HALF_PERD_FS_L_CFG_CLKOUT_HALF_PERIOD_FS_L_OFFSET) + +#define RTL8373_PTP_CLKOUT_HALF_PERD_FS_H_ADDR (0x7CD4) + #define RTL8373_PTP_CLKOUT_HALF_PERD_FS_H_CFG_CLKOUT_RSV_OFFSET (15) + #define RTL8373_PTP_CLKOUT_HALF_PERD_FS_H_CFG_CLKOUT_RSV_MASK (0x1 << RTL8373_PTP_CLKOUT_HALF_PERD_FS_H_CFG_CLKOUT_RSV_OFFSET) + #define RTL8373_PTP_CLKOUT_HALF_PERD_FS_H_CFG_CLKOUT_HALF_PERIOD_FS_H_OFFSET (0) + #define RTL8373_PTP_CLKOUT_HALF_PERD_FS_H_CFG_CLKOUT_HALF_PERIOD_FS_H_MASK (0x7FFF << RTL8373_PTP_CLKOUT_HALF_PERD_FS_H_CFG_CLKOUT_HALF_PERIOD_FS_H_OFFSET) + +#define RTL8373_PTP_DUMMY_RG46_ADDR (0x7CD8) + #define RTL8373_PTP_DUMMY_RG46_PTP_TIMER_RESERVE_RG46_OFFSET (0) + #define RTL8373_PTP_DUMMY_RG46_PTP_TIMER_RESERVE_RG46_MASK (0xFFFFFFFF << RTL8373_PTP_DUMMY_RG46_PTP_TIMER_RESERVE_RG46_OFFSET) + +#define RTL8373_PTP_DUMMY_RG47_ADDR (0x7CDC) + #define RTL8373_PTP_DUMMY_RG47_PTP_TIMER_RESERVE_RG47_OFFSET (0) + #define RTL8373_PTP_DUMMY_RG47_PTP_TIMER_RESERVE_RG47_MASK (0xFFFFFFFF << RTL8373_PTP_DUMMY_RG47_PTP_TIMER_RESERVE_RG47_OFFSET) + +#define RTL8373_PPS_IN_LATCH_TIME_NSEC_L_ADDR (0x7CE0) + #define RTL8373_PPS_IN_LATCH_TIME_NSEC_L_PPS_LATCH_PTP_TIME_NSEC_L_OFFSET (0) + #define RTL8373_PPS_IN_LATCH_TIME_NSEC_L_PPS_LATCH_PTP_TIME_NSEC_L_MASK (0xFFFF << RTL8373_PPS_IN_LATCH_TIME_NSEC_L_PPS_LATCH_PTP_TIME_NSEC_L_OFFSET) + +#define RTL8373_PPS_IN_LATCH_TIME_NSEC_H_ADDR (0x7CE4) + #define RTL8373_PPS_IN_LATCH_TIME_NSEC_H_PPS_LATCH_PTP_TIME_NSEC_H_OFFSET (0) + #define RTL8373_PPS_IN_LATCH_TIME_NSEC_H_PPS_LATCH_PTP_TIME_NSEC_H_MASK (0x3FFF << RTL8373_PPS_IN_LATCH_TIME_NSEC_H_PPS_LATCH_PTP_TIME_NSEC_H_OFFSET) + +#define RTL8373_PPS_IN_LATCH_TIME_SEC_L_ADDR (0x7CE8) + #define RTL8373_PPS_IN_LATCH_TIME_SEC_L_PPS_LATCH_PTP_TIME_SEC_L_OFFSET (0) + #define RTL8373_PPS_IN_LATCH_TIME_SEC_L_PPS_LATCH_PTP_TIME_SEC_L_MASK (0xFFFF << RTL8373_PPS_IN_LATCH_TIME_SEC_L_PPS_LATCH_PTP_TIME_SEC_L_OFFSET) + +#define RTL8373_PPS_IN_LATCH_TIME_SEC_M_ADDR (0x7CEC) + #define RTL8373_PPS_IN_LATCH_TIME_SEC_M_PPS_LATCH_PTP_TIME_SEC_M_OFFSET (0) + #define RTL8373_PPS_IN_LATCH_TIME_SEC_M_PPS_LATCH_PTP_TIME_SEC_M_MASK (0xFFFF << RTL8373_PPS_IN_LATCH_TIME_SEC_M_PPS_LATCH_PTP_TIME_SEC_M_OFFSET) + +#define RTL8373_PPS_IN_LATCH_TIME_SEC_H_ADDR (0x7CF0) + #define RTL8373_PPS_IN_LATCH_TIME_SEC_H_PPS_LATCH_PTP_TIME_SEC_H_OFFSET (0) + #define RTL8373_PPS_IN_LATCH_TIME_SEC_H_PPS_LATCH_PTP_TIME_SEC_H_MASK (0xFFFF << RTL8373_PPS_IN_LATCH_TIME_SEC_H_PPS_LATCH_PTP_TIME_SEC_H_OFFSET) + +#define RTL8373_PTP_DUMMY_RG53_ADDR (0x7CF4) + #define RTL8373_PTP_DUMMY_RG53_PTP_DUMMY_RG53_OFFSET (0) + #define RTL8373_PTP_DUMMY_RG53_PTP_DUMMY_RG53_MASK (0xFFFFFFFF << RTL8373_PTP_DUMMY_RG53_PTP_DUMMY_RG53_OFFSET) + +#define RTL8373_PTP_DUMMY_RG54_ADDR (0x7CF8) + #define RTL8373_PTP_DUMMY_RG54_PTP_DUMMY_RG54_OFFSET (0) + #define RTL8373_PTP_DUMMY_RG54_PTP_DUMMY_RG54_MASK (0xFFFFFFFF << RTL8373_PTP_DUMMY_RG54_PTP_DUMMY_RG54_OFFSET) + +#define RTL8373_PTP_DUMMY_RG55_ADDR (0x7CFC) + #define RTL8373_PTP_DUMMY_RG55_PTP_DUMMY_RG55_OFFSET (0) + #define RTL8373_PTP_DUMMY_RG55_PTP_DUMMY_RG55_MASK (0xFFFFFFFF << RTL8373_PTP_DUMMY_RG55_PTP_DUMMY_RG55_OFFSET) + +#define RTL8373_PTP_DUMMY_RG56_ADDR (0x7D00) + #define RTL8373_PTP_DUMMY_RG56_PTP_DUMMY_RG56_OFFSET (0) + #define RTL8373_PTP_DUMMY_RG56_PTP_DUMMY_RG56_MASK (0xFFFFFFFF << RTL8373_PTP_DUMMY_RG56_PTP_DUMMY_RG56_OFFSET) + +#define RTL8373_PTP_DUMMY_RG57_ADDR (0x7D04) + #define RTL8373_PTP_DUMMY_RG57_PTP_DUMMY_RG57_OFFSET (0) + #define RTL8373_PTP_DUMMY_RG57_PTP_DUMMY_RG57_MASK (0xFFFFFFFF << RTL8373_PTP_DUMMY_RG57_PTP_DUMMY_RG57_OFFSET) + +#define RTL8373_PTP_DUMMY_RG58_ADDR (0x7D08) + #define RTL8373_PTP_DUMMY_RG58_PTP_DUMMY_RG58_OFFSET (0) + #define RTL8373_PTP_DUMMY_RG58_PTP_DUMMY_RG58_MASK (0xFFFFFFFF << RTL8373_PTP_DUMMY_RG58_PTP_DUMMY_RG58_OFFSET) + +#define RTL8373_PTP_DUMMY_RG59_ADDR (0x7D0C) + #define RTL8373_PTP_DUMMY_RG59_PTP_DUMMY_RG59_OFFSET (0) + #define RTL8373_PTP_DUMMY_RG59_PTP_DUMMY_RG59_MASK (0xFFFFFFFF << RTL8373_PTP_DUMMY_RG59_PTP_DUMMY_RG59_OFFSET) + +#define RTL8373_PTP_DUMMY_RG60_ADDR (0x7D10) + #define RTL8373_PTP_DUMMY_RG60_PTP_DUMMY_RG60_OFFSET (0) + #define RTL8373_PTP_DUMMY_RG60_PTP_DUMMY_RG60_MASK (0xFFFFFFFF << RTL8373_PTP_DUMMY_RG60_PTP_DUMMY_RG60_OFFSET) + +#define RTL8373_PTP_DUMMY_RG61_ADDR (0x7D14) + #define RTL8373_PTP_DUMMY_RG61_PTP_DUMMY_RG61_OFFSET (0) + #define RTL8373_PTP_DUMMY_RG61_PTP_DUMMY_RG61_MASK (0xFFFFFFFF << RTL8373_PTP_DUMMY_RG61_PTP_DUMMY_RG61_OFFSET) + +#define RTL8373_PTP_TIME_SPEED_UP_ADDR (0x7D18) + #define RTL8373_PTP_TIME_SPEED_UP_CFG_DUR_SPDUP_OFFSET (0) + #define RTL8373_PTP_TIME_SPEED_UP_CFG_DUR_SPDUP_MASK (0x1 << RTL8373_PTP_TIME_SPEED_UP_CFG_DUR_SPDUP_OFFSET) + +#define RTL8373_PTP_VERSION_ADDR (0x7D1C) + #define RTL8373_PTP_VERSION_PTP_VERSION_OFFSET (0) + #define RTL8373_PTP_VERSION_PTP_VERSION_MASK (0xFFFF << RTL8373_PTP_VERSION_PTP_VERSION_OFFSET) + +#define RTL8373_P0_PORT_CTRL_ADDR(port) (0x7D20 + (((port) << 5))) /* port: 0-9 */ + #define RTL8373_P0_PORT_CTRL_P0_CFG_LINK_DELAY_L_OFFSET (6) + #define RTL8373_P0_PORT_CTRL_P0_CFG_LINK_DELAY_L_MASK (0x3FF << RTL8373_P0_PORT_CTRL_P0_CFG_LINK_DELAY_L_OFFSET) + #define RTL8373_P0_PORT_CTRL_P0_CFG_ALWAYS_TS_OFFSET (5) + #define RTL8373_P0_PORT_CTRL_P0_CFG_ALWAYS_TS_MASK (0x1 << RTL8373_P0_PORT_CTRL_P0_CFG_ALWAYS_TS_OFFSET) + #define RTL8373_P0_PORT_CTRL_P0_PTP_ROLE_OFFSET (2) + #define RTL8373_P0_PORT_CTRL_P0_PTP_ROLE_MASK (0x3 << RTL8373_P0_PORT_CTRL_P0_PTP_ROLE_OFFSET) + #define RTL8373_P0_PORT_CTRL_P0_CFG_UDP_EN_OFFSET (1) + #define RTL8373_P0_PORT_CTRL_P0_CFG_UDP_EN_MASK (0x1 << RTL8373_P0_PORT_CTRL_P0_CFG_UDP_EN_OFFSET) + #define RTL8373_P0_PORT_CTRL_P0_CFG_ETH_EN_OFFSET (0) + #define RTL8373_P0_PORT_CTRL_P0_CFG_ETH_EN_MASK (0x1 << RTL8373_P0_PORT_CTRL_P0_CFG_ETH_EN_OFFSET) + +#define RTL8373_P0_LINK_DELAY_H_ADDR(port) (0x7D24 + (((port) << 5))) /* port: 0-9 */ + #define RTL8373_P0_LINK_DELAY_H_P0_CFG_LINK_DELAY_H_OFFSET (0) + #define RTL8373_P0_LINK_DELAY_H_P0_CFG_LINK_DELAY_H_MASK (0xFFFF << RTL8373_P0_LINK_DELAY_H_P0_CFG_LINK_DELAY_H_OFFSET) + +#define RTL8373_P0_MISC_CTRL_ADDR(port) (0x7D28 + (((port) << 5))) /* port: 0-9 */ + #define RTL8373_P0_MISC_CTRL_P0_PTP_DUMMY_OFFSET (1) + #define RTL8373_P0_MISC_CTRL_P0_PTP_DUMMY_MASK (0x7FFF << RTL8373_P0_MISC_CTRL_P0_PTP_DUMMY_OFFSET) + #define RTL8373_P0_MISC_CTRL_P0_CFG_BYPASS_OFFSET (0) + #define RTL8373_P0_MISC_CTRL_P0_CFG_BYPASS_MASK (0x1 << RTL8373_P0_MISC_CTRL_P0_CFG_BYPASS_OFFSET) + +#define RTL8373_P0_TX_IMBAL_ADDR(port) (0x7D2C + (((port) << 5))) /* port: 0-9 */ + #define RTL8373_P0_TX_IMBAL_P0_TX_IMBAL_OFFSET (0) + #define RTL8373_P0_TX_IMBAL_P0_TX_IMBAL_MASK (0xFFF << RTL8373_P0_TX_IMBAL_P0_TX_IMBAL_OFFSET) + +#define RTL8373_P0_RX_IMBAL_ADDR(port) (0x7D30 + (((port) << 5))) /* port: 0-9 */ + #define RTL8373_P0_RX_IMBAL_P0_RX_IMBAL_OFFSET (0) + #define RTL8373_P0_RX_IMBAL_P0_RX_IMBAL_MASK (0xFFF << RTL8373_P0_RX_IMBAL_P0_RX_IMBAL_OFFSET) + +#define RTL8373_P0_PTP_PORTID_ADDR(port) (0x7D34 + (((port) << 5))) /* port: 0-9 */ + #define RTL8373_P0_PTP_PORTID_P0_ID_OFFSET (0) + #define RTL8373_P0_PTP_PORTID_P0_ID_MASK (0x3F << RTL8373_P0_PTP_PORTID_P0_ID_OFFSET) + +#define RTL8373_P0_PTP_DUMMY_RG06_ADDR(port) (0x7D38 + (((port) << 5))) /* port: 0-9 */ + #define RTL8373_P0_PTP_DUMMY_RG06_P0_PTP_DUMMY_RG06_OFFSET (0) + #define RTL8373_P0_PTP_DUMMY_RG06_P0_PTP_DUMMY_RG06_MASK (0xFFFFFFFF << RTL8373_P0_PTP_DUMMY_RG06_P0_PTP_DUMMY_RG06_OFFSET) + +#define RTL8373_P0_DBG_PTP_CTRL_ADDR(port) (0x7D3C + (((port) << 5))) /* port: 0-9 */ + #define RTL8373_P0_DBG_PTP_CTRL_P0_DBG_PTP_OFFSET (0) + #define RTL8373_P0_DBG_PTP_CTRL_P0_DBG_PTP_MASK (0xFFFF << RTL8373_P0_DBG_PTP_CTRL_P0_DBG_PTP_OFFSET) + +#define RTL8373_TOD_OUT_DATA_CTRL_ADDR(index) (0x7E60 + (((index) << 2))) /* index: 0-15 */ + #define RTL8373_TOD_OUT_DATA_CTRL_TOD_DATA_OFFSET (0) + #define RTL8373_TOD_OUT_DATA_CTRL_TOD_DATA_MASK (0xFFFF << RTL8373_TOD_OUT_DATA_CTRL_TOD_DATA_OFFSET) + +#define RTL8373_TOD_OUT_CTRL0_ADDR (0x7EA0) + #define RTL8373_TOD_OUT_CTRL0_TOD_DATA_LEN_OFFSET (8) + #define RTL8373_TOD_OUT_CTRL0_TOD_DATA_LEN_MASK (0xFF << RTL8373_TOD_OUT_CTRL0_TOD_DATA_LEN_OFFSET) + #define RTL8373_TOD_OUT_CTRL0_DIVISOR_LATCH_VAL_BIT16_OFFSET (7) + #define RTL8373_TOD_OUT_CTRL0_DIVISOR_LATCH_VAL_BIT16_MASK (0x1 << RTL8373_TOD_OUT_CTRL0_DIVISOR_LATCH_VAL_BIT16_OFFSET) + #define RTL8373_TOD_OUT_CTRL0_MANUAL_OFFSET (6) + #define RTL8373_TOD_OUT_CTRL0_MANUAL_MASK (0x1 << RTL8373_TOD_OUT_CTRL0_MANUAL_OFFSET) + #define RTL8373_TOD_OUT_CTRL0_TOD_DELAY_OFFSET (0) + #define RTL8373_TOD_OUT_CTRL0_TOD_DELAY_MASK (0x3F << RTL8373_TOD_OUT_CTRL0_TOD_DELAY_OFFSET) + +#define RTL8373_TOD_OUT_CTRL1_ADDR (0x7EA4) + #define RTL8373_TOD_OUT_CTRL1_DIVISOR_LATCH_VAL_BIT15_0_OFFSET (0) + #define RTL8373_TOD_OUT_CTRL1_DIVISOR_LATCH_VAL_BIT15_0_MASK (0xFFFF << RTL8373_TOD_OUT_CTRL1_DIVISOR_LATCH_VAL_BIT15_0_OFFSET) + +#define RTL8373_TOD_SARP_GPS_WEEK_ADDR (0x7EA8) + #define RTL8373_TOD_SARP_GPS_WEEK_TOD_SARP_GPS_WEEK_OFFSET (0) + #define RTL8373_TOD_SARP_GPS_WEEK_TOD_SARP_GPS_WEEK_MASK (0xFFFF << RTL8373_TOD_SARP_GPS_WEEK_TOD_SARP_GPS_WEEK_OFFSET) + +#define RTL8373_TOD_SARP_GPS_SEC_L_ADDR (0x7EAC) + #define RTL8373_TOD_SARP_GPS_SEC_L_TOD_SARP_GPS_SEC_L_OFFSET (0) + #define RTL8373_TOD_SARP_GPS_SEC_L_TOD_SARP_GPS_SEC_L_MASK (0xFFFF << RTL8373_TOD_SARP_GPS_SEC_L_TOD_SARP_GPS_SEC_L_OFFSET) + +#define RTL8373_TOD_SARP_GPS_SEC_H_ADDR (0x7EB0) + #define RTL8373_TOD_SARP_GPS_SEC_H_TOD_SARP_GPS_SEC_H_OFFSET (0) + #define RTL8373_TOD_SARP_GPS_SEC_H_TOD_SARP_GPS_SEC_H_MASK (0xFFFF << RTL8373_TOD_SARP_GPS_SEC_H_TOD_SARP_GPS_SEC_H_OFFSET) + +#define RTL8373_TOD_UART_SETTING_ADDR (0x7EB4) + #define RTL8373_TOD_UART_SETTING_DBG_SEL_OFFSET (11) + #define RTL8373_TOD_UART_SETTING_DBG_SEL_MASK (0xF << RTL8373_TOD_UART_SETTING_DBG_SEL_OFFSET) + #define RTL8373_TOD_UART_SETTING_TIMER_GPIO_OE_OFFSET (10) + #define RTL8373_TOD_UART_SETTING_TIMER_GPIO_OE_MASK (0x1 << RTL8373_TOD_UART_SETTING_TIMER_GPIO_OE_OFFSET) + #define RTL8373_TOD_UART_SETTING_SELF_GPI_OFFSET (9) + #define RTL8373_TOD_UART_SETTING_SELF_GPI_MASK (0x1 << RTL8373_TOD_UART_SETTING_SELF_GPI_OFFSET) + #define RTL8373_TOD_UART_SETTING_TIMER_GPO_OFFSET (8) + #define RTL8373_TOD_UART_SETTING_TIMER_GPO_MASK (0x1 << RTL8373_TOD_UART_SETTING_TIMER_GPO_OFFSET) + #define RTL8373_TOD_UART_SETTING_DBG_EN_OFFSET (7) + #define RTL8373_TOD_UART_SETTING_DBG_EN_MASK (0x1 << RTL8373_TOD_UART_SETTING_DBG_EN_OFFSET) + #define RTL8373_TOD_UART_SETTING_PARITY_OFFSET (5) + #define RTL8373_TOD_UART_SETTING_PARITY_MASK (0x3 << RTL8373_TOD_UART_SETTING_PARITY_OFFSET) + #define RTL8373_TOD_UART_SETTING_STOP_BIT_OFFSET (2) + #define RTL8373_TOD_UART_SETTING_STOP_BIT_MASK (0x7 << RTL8373_TOD_UART_SETTING_STOP_BIT_OFFSET) + #define RTL8373_TOD_UART_SETTING_DATA_BIT_OFFSET (0) + #define RTL8373_TOD_UART_SETTING_DATA_BIT_MASK (0x3 << RTL8373_TOD_UART_SETTING_DATA_BIT_OFFSET) + +#define RTL8373_TOD_INTR_ADDR (0x7EB8) + #define RTL8373_TOD_INTR_TOD_DUMMY_OFFSET (2) + #define RTL8373_TOD_INTR_TOD_DUMMY_MASK (0x3FFF << RTL8373_TOD_INTR_TOD_DUMMY_OFFSET) + #define RTL8373_TOD_INTR_ISR_TOD_OFFSET (1) + #define RTL8373_TOD_INTR_ISR_TOD_MASK (0x1 << RTL8373_TOD_INTR_ISR_TOD_OFFSET) + #define RTL8373_TOD_INTR_IMR_TOD_OFFSET (0) + #define RTL8373_TOD_INTR_IMR_TOD_MASK (0x1 << RTL8373_TOD_INTR_IMR_TOD_OFFSET) + +/* + * Feature: Storm Control (B/M/UM/DLF) + */ +#define RTL8373_RX_STORM_BCAST_CTRL_ADDR(port) (0x54E4 + (((port / 10) << 2))) /* port: 0-9 */ + #define RTL8373_RX_STORM_BCAST_CTRL_RX_STROM_BCAST_EN_OFFSET(port) (port % 0xA) + #define RTL8373_RX_STORM_BCAST_CTRL_RX_STROM_BCAST_EN_MASK(port) (0x1 << RTL8373_RX_STORM_BCAST_CTRL_RX_STROM_BCAST_EN_OFFSET(port)) + +#define RTL8373_RX_STORM_MCAST_CTRL_ADDR(port) (0x54E8 + (((port / 10) << 2))) /* port: 0-9 */ + #define RTL8373_RX_STORM_MCAST_CTRL_RX_STROM_MCAST_EN_OFFSET(port) (port % 0xA) + #define RTL8373_RX_STORM_MCAST_CTRL_RX_STROM_MCAST_EN_MASK(port) (0x1 << RTL8373_RX_STORM_MCAST_CTRL_RX_STROM_MCAST_EN_OFFSET(port)) + +#define RTL8373_RX_STORM_UNUCAST_CTRL_ADDR(port) (0x54EC + (((port / 10) << 2))) /* port: 0-9 */ + #define RTL8373_RX_STORM_UNUCAST_CTRL_RX_STROM_UNUCAST_EN_OFFSET(port) (port % 0xA) + #define RTL8373_RX_STORM_UNUCAST_CTRL_RX_STROM_UNUCAST_EN_MASK(port) (0x1 << RTL8373_RX_STORM_UNUCAST_CTRL_RX_STROM_UNUCAST_EN_OFFSET(port)) + +#define RTL8373_RX_STORM_UNMCAST_CTRL_ADDR(port) (0x54F0 + (((port / 10) << 2))) /* port: 0-9 */ + #define RTL8373_RX_STORM_UNMCAST_CTRL_RX_STROM_UNMCAST_EN_OFFSET(port) (port % 0xA) + #define RTL8373_RX_STORM_UNMCAST_CTRL_RX_STROM_UNMCAST_EN_MASK(port) (0x1 << RTL8373_RX_STORM_UNMCAST_CTRL_RX_STROM_UNMCAST_EN_OFFSET(port)) + +#define RTL8373_RX_STORM_BCAST_METER_ADDR(port) (0x54F4 + (((port / 5) << 2))) /* port: 0-9 */ + #define RTL8373_RX_STORM_BCAST_METER_RX_STROM_BCAST_MIDX_OFFSET(port) ((port % 0x5) * 6) + #define RTL8373_RX_STORM_BCAST_METER_RX_STROM_BCAST_MIDX_MASK(port) (0x3F << RTL8373_RX_STORM_BCAST_METER_RX_STROM_BCAST_MIDX_OFFSET(port)) + +#define RTL8373_RX_STORM_MCAST_METER_ADDR(port) (0x54FC + (((port / 5) << 2))) /* port: 0-9 */ + #define RTL8373_RX_STORM_MCAST_METER_RX_STROM_MCAST_MIDX_OFFSET(port) ((port % 0x5) * 6) + #define RTL8373_RX_STORM_MCAST_METER_RX_STROM_MCAST_MIDX_MASK(port) (0x3F << RTL8373_RX_STORM_MCAST_METER_RX_STROM_MCAST_MIDX_OFFSET(port)) + +#define RTL8373_RX_STORM_UNUCAST_METER_ADDR(port) (0x5504 + (((port / 5) << 2))) /* port: 0-9 */ + #define RTL8373_RX_STORM_UNUCAST_METER_RX_STROM_UNUCAST_MIDX_OFFSET(port) ((port % 0x5) * 6) + #define RTL8373_RX_STORM_UNUCAST_METER_RX_STROM_UNUCAST_MIDX_MASK(port) (0x3F << RTL8373_RX_STORM_UNUCAST_METER_RX_STROM_UNUCAST_MIDX_OFFSET(port)) + +#define RTL8373_RX_STORM_UNMCAST_METER_ADDR(port) (0x550C + (((port / 5) << 2))) /* port: 0-9 */ + #define RTL8373_RX_STORM_UNMCAST_METER_RX_STROM_UNMCAST_MIDX_OFFSET(port) ((port % 0x5) * 6) + #define RTL8373_RX_STORM_UNMCAST_METER_RX_STROM_UNMCAST_MIDX_MASK(port) (0x3F << RTL8373_RX_STORM_UNMCAST_METER_RX_STROM_UNMCAST_MIDX_OFFSET(port)) + +#define RTL8373_CFG_STORM_EXT_ADDR (0x5514) + #define RTL8373_CFG_STORM_EXT_STORM_EXT_EN_PORTMASK_OFFSET (4) + #define RTL8373_CFG_STORM_EXT_STORM_EXT_EN_PORTMASK_MASK (0x3FF << RTL8373_CFG_STORM_EXT_STORM_EXT_EN_PORTMASK_OFFSET) + #define RTL8373_CFG_STORM_EXT_STORM_UNKNOWN_MCAST_EXT_EN_OFFSET (3) + #define RTL8373_CFG_STORM_EXT_STORM_UNKNOWN_MCAST_EXT_EN_MASK (0x1 << RTL8373_CFG_STORM_EXT_STORM_UNKNOWN_MCAST_EXT_EN_OFFSET) + #define RTL8373_CFG_STORM_EXT_STORM_UNKNOWN_UCAST_EXT_EN_OFFSET (2) + #define RTL8373_CFG_STORM_EXT_STORM_UNKNOWN_UCAST_EXT_EN_MASK (0x1 << RTL8373_CFG_STORM_EXT_STORM_UNKNOWN_UCAST_EXT_EN_OFFSET) + #define RTL8373_CFG_STORM_EXT_STORM_MCAST_EXT_EN_OFFSET (1) + #define RTL8373_CFG_STORM_EXT_STORM_MCAST_EXT_EN_MASK (0x1 << RTL8373_CFG_STORM_EXT_STORM_MCAST_EXT_EN_OFFSET) + #define RTL8373_CFG_STORM_EXT_STORM_BCAST_EXT_EN_OFFSET (0) + #define RTL8373_CFG_STORM_EXT_STORM_BCAST_EXT_EN_MASK (0x1 << RTL8373_CFG_STORM_EXT_STORM_BCAST_EXT_EN_OFFSET) + +#define RTL8373_STORM_EXT_MTRIDX_CFG_ADDR (0x5518) + #define RTL8373_STORM_EXT_MTRIDX_CFG_STORM_UNKNOWN_MCAST_EXT_METERID_OFFSET (24) + #define RTL8373_STORM_EXT_MTRIDX_CFG_STORM_UNKNOWN_MCAST_EXT_METERID_MASK (0x3F << RTL8373_STORM_EXT_MTRIDX_CFG_STORM_UNKNOWN_MCAST_EXT_METERID_OFFSET) + #define RTL8373_STORM_EXT_MTRIDX_CFG_STORM_UNKNOWN_UCAST_EXT_METERID_OFFSET (16) + #define RTL8373_STORM_EXT_MTRIDX_CFG_STORM_UNKNOWN_UCAST_EXT_METERID_MASK (0x3F << RTL8373_STORM_EXT_MTRIDX_CFG_STORM_UNKNOWN_UCAST_EXT_METERID_OFFSET) + #define RTL8373_STORM_EXT_MTRIDX_CFG_STORM_MCAST_EXT_METERID_OFFSET (8) + #define RTL8373_STORM_EXT_MTRIDX_CFG_STORM_MCAST_EXT_METERID_MASK (0x3F << RTL8373_STORM_EXT_MTRIDX_CFG_STORM_MCAST_EXT_METERID_OFFSET) + #define RTL8373_STORM_EXT_MTRIDX_CFG_STORM_BCAST_EXT_METERID_OFFSET (0) + #define RTL8373_STORM_EXT_MTRIDX_CFG_STORM_BCAST_EXT_METERID_MASK (0x3F << RTL8373_STORM_EXT_MTRIDX_CFG_STORM_BCAST_EXT_METERID_OFFSET) + +/* + * Feature: IngressBW + */ +#define RTL8373_IGBW_CTRL_ADDR (0x4C10) + #define RTL8373_IGBW_CTRL_INC_BYPASS_PKT_OFFSET (8) + #define RTL8373_IGBW_CTRL_INC_BYPASS_PKT_MASK (0x1 << RTL8373_IGBW_CTRL_INC_BYPASS_PKT_OFFSET) + #define RTL8373_IGBW_CTRL_INC_IFG_OFFSET (7) + #define RTL8373_IGBW_CTRL_INC_IFG_MASK (0x1 << RTL8373_IGBW_CTRL_INC_IFG_OFFSET) + #define RTL8373_IGBW_CTRL_ADMIT_DHCP_OFFSET (5) + #define RTL8373_IGBW_CTRL_ADMIT_DHCP_MASK (0x1 << RTL8373_IGBW_CTRL_ADMIT_DHCP_OFFSET) + #define RTL8373_IGBW_CTRL_ADMIT_ARPREQ_OFFSET (4) + #define RTL8373_IGBW_CTRL_ADMIT_ARPREQ_MASK (0x1 << RTL8373_IGBW_CTRL_ADMIT_ARPREQ_OFFSET) + #define RTL8373_IGBW_CTRL_ADMIT_RMA_OFFSET (3) + #define RTL8373_IGBW_CTRL_ADMIT_RMA_MASK (0x1 << RTL8373_IGBW_CTRL_ADMIT_RMA_OFFSET) + #define RTL8373_IGBW_CTRL_ADMIT_BPDU_OFFSET (2) + #define RTL8373_IGBW_CTRL_ADMIT_BPDU_MASK (0x1 << RTL8373_IGBW_CTRL_ADMIT_BPDU_OFFSET) + #define RTL8373_IGBW_CTRL_ADMIT_RTKPKT_OFFSET (1) + #define RTL8373_IGBW_CTRL_ADMIT_RTKPKT_MASK (0x1 << RTL8373_IGBW_CTRL_ADMIT_RTKPKT_OFFSET) + #define RTL8373_IGBW_CTRL_ADMIT_IGMP_OFFSET (0) + #define RTL8373_IGBW_CTRL_ADMIT_IGMP_MASK (0x1 << RTL8373_IGBW_CTRL_ADMIT_IGMP_OFFSET) + +#define RTL8373_IGBW_LB_CTRL_ADDR (0x4C14) + #define RTL8373_IGBW_LB_CTRL_TICK_OFFSET (16) + #define RTL8373_IGBW_LB_CTRL_TICK_MASK (0xFFFF << RTL8373_IGBW_LB_CTRL_TICK_OFFSET) + #define RTL8373_IGBW_LB_CTRL_TKN_OFFSET (0) + #define RTL8373_IGBW_LB_CTRL_TKN_MASK (0xFFFF << RTL8373_IGBW_LB_CTRL_TKN_OFFSET) + +#define RTL8373_IGBW_PORT_CTRL_ADDR(port) (0x4C18 + (((port) << 2))) /* port: 0-8 */ + #define RTL8373_IGBW_PORT_CTRL_BW_EN_OFFSET (20) + #define RTL8373_IGBW_PORT_CTRL_BW_EN_MASK (0x1 << RTL8373_IGBW_PORT_CTRL_BW_EN_OFFSET) + #define RTL8373_IGBW_PORT_CTRL_RATE_OFFSET (0) + #define RTL8373_IGBW_PORT_CTRL_RATE_MASK (0xFFFFF << RTL8373_IGBW_PORT_CTRL_RATE_OFFSET) + +#define RTL8373_IGBW_PORT_BURST_CTRL_ADDR(port) (0x4C3C + (((port) << 3))) /* port: 0-8 */ + #define RTL8373_IGBW_PORT_BURST_CTRL_HIGH_ON_OFFSET (0) + #define RTL8373_IGBW_PORT_BURST_CTRL_HIGH_ON_MASK (0x7FFFFFFF << RTL8373_IGBW_PORT_BURST_CTRL_HIGH_ON_OFFSET) + #define RTL8373_IGBW_PORT_BURST_CTRL_HIGH_OFF_OFFSET (32) + #define RTL8373_IGBW_PORT_BURST_CTRL_HIGH_OFF_MASK (0x7FFFFFFF << RTL8373_IGBW_PORT_BURST_CTRL_HIGH_OFF_OFFSET) + +#define RTL8373_IGBW_PORT_LB_RST_ADDR(port) (0x4C84 + (((port / 9) << 2))) /* port: 0-8 */ + #define RTL8373_IGBW_PORT_LB_RST_RST_OFFSET(port) (port % 0x9) + #define RTL8373_IGBW_PORT_LB_RST_RST_MASK(port) (0x1 << RTL8373_IGBW_PORT_LB_RST_RST_OFFSET(port)) + +#define RTL8373_IGBW_PORT_CNGST_FLAG_ADDR(port) (0x4C88 + (((port / 9) << 2))) /* port: 0-8 */ + #define RTL8373_IGBW_PORT_CNGST_FLAG_FLAG_OFFSET(port) (port % 0x9) + #define RTL8373_IGBW_PORT_CNGST_FLAG_FLAG_MASK(port) (0x1 << RTL8373_IGBW_PORT_CNGST_FLAG_FLAG_OFFSET(port)) + +#define RTL8373_IGBW_PORT_FC_CTRL_ADDR(port) (0x4C8C + (((port / 9) << 2))) /* port: 0-8 */ + #define RTL8373_IGBW_PORT_FC_CTRL_EN_OFFSET(port) (port % 0x9) + #define RTL8373_IGBW_PORT_FC_CTRL_EN_MASK(port) (0x1 << RTL8373_IGBW_PORT_FC_CTRL_EN_OFFSET(port)) + +#define RTL8373_IGBW_PORT_DROP_CTRL_ADDR(port) (0x4C90 + (((port) << 2))) /* port: 0-8 */ + #define RTL8373_IGBW_PORT_DROP_CTRL_DROP_THR_OFFSET (0) + #define RTL8373_IGBW_PORT_DROP_CTRL_DROP_THR_MASK (0xFFFFFFFF << RTL8373_IGBW_PORT_DROP_CTRL_DROP_THR_OFFSET) + +/* + * Feature: Egress Bandwidth Control + */ +#define RTL8373_EGBW_ENCAP_CTRL_ADDR (0x4478) + #define RTL8373_EGBW_ENCAP_CTRL_ASSURED_DIS_ENCAP_FEED_BACK_OFFSET (1) + #define RTL8373_EGBW_ENCAP_CTRL_ASSURED_DIS_ENCAP_FEED_BACK_MASK (0x1 << RTL8373_EGBW_ENCAP_CTRL_ASSURED_DIS_ENCAP_FEED_BACK_OFFSET) + +#define RTL8373_EGBW_CTRL_ADDR (0x447C) + #define RTL8373_EGBW_CTRL_INC_IFG_OFFSET (1) + #define RTL8373_EGBW_CTRL_INC_IFG_MASK (0x1 << RTL8373_EGBW_CTRL_INC_IFG_OFFSET) + #define RTL8373_EGBW_CTRL_RATE_MODE_CPU_OFFSET (0) + #define RTL8373_EGBW_CTRL_RATE_MODE_CPU_MASK (0x1 << RTL8373_EGBW_CTRL_RATE_MODE_CPU_OFFSET) + +#define RTL8373_EGBW_LB_CTRL_ADDR (0x4480) + #define RTL8373_EGBW_LB_CTRL_TKN_OFFSET (16) + #define RTL8373_EGBW_LB_CTRL_TKN_MASK (0xFFFF << RTL8373_EGBW_LB_CTRL_TKN_OFFSET) + #define RTL8373_EGBW_LB_CTRL_TICK_OFFSET (0) + #define RTL8373_EGBW_LB_CTRL_TICK_MASK (0xFFFF << RTL8373_EGBW_LB_CTRL_TICK_OFFSET) + +#define RTL8373_EGBW_PORT_CTRL_ADDR(port) (0x1C34 + (((port) << 10))) /* port: 0-9 */ + #define RTL8373_EGBW_PORT_CTRL_EN_OFFSET (20) + #define RTL8373_EGBW_PORT_CTRL_EN_MASK (0x1 << RTL8373_EGBW_PORT_CTRL_EN_OFFSET) + #define RTL8373_EGBW_PORT_CTRL_RATE_OFFSET (0) + #define RTL8373_EGBW_PORT_CTRL_RATE_MASK (0xFFFFF << RTL8373_EGBW_PORT_CTRL_RATE_OFFSET) + #define RTL8373_EGBW_PORT_CTRL_BURST_OFFSET (32) + #define RTL8373_EGBW_PORT_CTRL_BURST_MASK (0xFFFF << RTL8373_EGBW_PORT_CTRL_BURST_OFFSET) + +#define RTL8373_EGBW_PORT_LB_RST_ADDR(port) (0x4484 + (((port / 10) << 2))) /* port: 0-9 */ + #define RTL8373_EGBW_PORT_LB_RST_RST_OFFSET(port) (port % 0xA) + #define RTL8373_EGBW_PORT_LB_RST_RST_MASK(port) (0x1 << RTL8373_EGBW_PORT_LB_RST_RST_OFFSET(port)) + +#define RTL8373_EGBW_PORT_Q_MAX_LB_CTRL_SET_ADDR(port, index) (0x1C3C + (port << 10) + (((index) << 3))) /* port: 0-9, index: 0-7 */ + #define RTL8373_EGBW_PORT_Q_MAX_LB_CTRL_SET_EN_OFFSET (20) + #define RTL8373_EGBW_PORT_Q_MAX_LB_CTRL_SET_EN_MASK (0x1 << RTL8373_EGBW_PORT_Q_MAX_LB_CTRL_SET_EN_OFFSET) + #define RTL8373_EGBW_PORT_Q_MAX_LB_CTRL_SET_RATE_OFFSET (0) + #define RTL8373_EGBW_PORT_Q_MAX_LB_CTRL_SET_RATE_MASK (0xFFFFF << RTL8373_EGBW_PORT_Q_MAX_LB_CTRL_SET_RATE_OFFSET) + #define RTL8373_EGBW_PORT_Q_MAX_LB_CTRL_SET_BURST_OFFSET (32) + #define RTL8373_EGBW_PORT_Q_MAX_LB_CTRL_SET_BURST_MASK (0xFFFF << RTL8373_EGBW_PORT_Q_MAX_LB_CTRL_SET_BURST_OFFSET) + +#define RTL8373_EGBW_PORT_Q_MAX_LB_RST_SET_ADDR(port, index) (0x1C7C + (port << 10) + (((index >> 3) << 2))) /* port: 0-9, index: 0-7 */ + #define RTL8373_EGBW_PORT_Q_MAX_LB_RST_SET_RST_OFFSET(index) (index % 0x8) + #define RTL8373_EGBW_PORT_Q_MAX_LB_RST_SET_RST_MASK(index) (0x1 << RTL8373_EGBW_PORT_Q_MAX_LB_RST_SET_RST_OFFSET(index)) + +#define RTL8373_EGBW_PORT_Q_ASSURED_FIX_BURST_CTRL_SET_ADDR(port, index) (0x1C80 + (port << 10) + (((index) << 2))) /* port: 0-9, index: 0-7 */ + #define RTL8373_EGBW_PORT_Q_ASSURED_FIX_BURST_CTRL_SET_BURST_OFFSET (0) + #define RTL8373_EGBW_PORT_Q_ASSURED_FIX_BURST_CTRL_SET_BURST_MASK (0xFFFF << RTL8373_EGBW_PORT_Q_ASSURED_FIX_BURST_CTRL_SET_BURST_OFFSET) + +#define RTL8373_EGBW_PORT_Q_ASSURED_LB_CTRL_SET_ADDR(port, index) (0x1CA0 + (port << 10) + (((index) << 2))) /* port: 0-9, index: 0-7 */ + #define RTL8373_EGBW_PORT_Q_ASSURED_LB_CTRL_SET_EN_OFFSET (20) + #define RTL8373_EGBW_PORT_Q_ASSURED_LB_CTRL_SET_EN_MASK (0x1 << RTL8373_EGBW_PORT_Q_ASSURED_LB_CTRL_SET_EN_OFFSET) + #define RTL8373_EGBW_PORT_Q_ASSURED_LB_CTRL_SET_RATE_OFFSET (0) + #define RTL8373_EGBW_PORT_Q_ASSURED_LB_CTRL_SET_RATE_MASK (0xFFFFF << RTL8373_EGBW_PORT_Q_ASSURED_LB_CTRL_SET_RATE_OFFSET) + +#define RTL8373_EGBW_PORT_Q_FIX_LB_CTRL_SET_ADDR(port, index) (0x1CC0 + (port << 10) + (((index) << 2))) /* port: 0-9, index: 0-7 */ + #define RTL8373_EGBW_PORT_Q_FIX_LB_CTRL_SET_EN_OFFSET (20) + #define RTL8373_EGBW_PORT_Q_FIX_LB_CTRL_SET_EN_MASK (0x1 << RTL8373_EGBW_PORT_Q_FIX_LB_CTRL_SET_EN_OFFSET) + #define RTL8373_EGBW_PORT_Q_FIX_LB_CTRL_SET_RATE_OFFSET (0) + #define RTL8373_EGBW_PORT_Q_FIX_LB_CTRL_SET_RATE_MASK (0xFFFFF << RTL8373_EGBW_PORT_Q_FIX_LB_CTRL_SET_RATE_OFFSET) + +#define RTL8373_EGBW_PORT_Q_ASSURED_FIX_LB_RST_SET_ADDR(port, index) (0x1CE0 + (port << 10) + (((index >> 3) << 2))) /* port: 0-9, index: 0-7 */ + #define RTL8373_EGBW_PORT_Q_ASSURED_FIX_LB_RST_SET_RST_OFFSET(index) (index % 0x8) + #define RTL8373_EGBW_PORT_Q_ASSURED_FIX_LB_RST_SET_RST_MASK(index) (0x1 << RTL8373_EGBW_PORT_Q_ASSURED_FIX_LB_RST_SET_RST_OFFSET(index)) + +#define RTL8373_EGBW_RATE_10M_CTRL_ADDR (0x4488) + #define RTL8373_EGBW_RATE_10M_CTRL_RATE_OFFSET (0) + #define RTL8373_EGBW_RATE_10M_CTRL_RATE_MASK (0xFFFFF << RTL8373_EGBW_RATE_10M_CTRL_RATE_OFFSET) + +#define RTL8373_EGBW_RATE_100M_CTRL_ADDR (0x448C) + #define RTL8373_EGBW_RATE_100M_CTRL_RATE_OFFSET (0) + #define RTL8373_EGBW_RATE_100M_CTRL_RATE_MASK (0xFFFFF << RTL8373_EGBW_RATE_100M_CTRL_RATE_OFFSET) + +#define RTL8373_EGBW_RATE_1G_CTRL_ADDR (0x4490) + #define RTL8373_EGBW_RATE_1G_CTRL_RATE_OFFSET (0) + #define RTL8373_EGBW_RATE_1G_CTRL_RATE_MASK (0xFFFFF << RTL8373_EGBW_RATE_1G_CTRL_RATE_OFFSET) + +#define RTL8373_EGBW_RATE_500M_CTRL_ADDR (0x4494) + #define RTL8373_EGBW_RATE_500M_CTRL_RATE_OFFSET (0) + #define RTL8373_EGBW_RATE_500M_CTRL_RATE_MASK (0xFFFFF << RTL8373_EGBW_RATE_500M_CTRL_RATE_OFFSET) + +#define RTL8373_EGBW_RATE_10G_CTRL_ADDR (0x4498) + #define RTL8373_EGBW_RATE_10G_CTRL_RATE_OFFSET (0) + #define RTL8373_EGBW_RATE_10G_CTRL_RATE_MASK (0xFFFFF << RTL8373_EGBW_RATE_10G_CTRL_RATE_OFFSET) + +#define RTL8373_EGBW_RATE_2500M_CTRL_ADDR (0x449C) + #define RTL8373_EGBW_RATE_2500M_CTRL_RATE_OFFSET (0) + #define RTL8373_EGBW_RATE_2500M_CTRL_RATE_MASK (0xFFFFF << RTL8373_EGBW_RATE_2500M_CTRL_RATE_OFFSET) + +#define RTL8373_EGBW_RATE_1250M_CTRL_ADDR (0x44A0) + #define RTL8373_EGBW_RATE_1250M_CTRL_RATE_OFFSET (0) + #define RTL8373_EGBW_RATE_1250M_CTRL_RATE_MASK (0xFFFFF << RTL8373_EGBW_RATE_1250M_CTRL_RATE_OFFSET) + +#define RTL8373_EGBW_RATE_5G_CTRL_ADDR (0x44A4) + #define RTL8373_EGBW_RATE_5G_CTRL_RATE_OFFSET (0) + #define RTL8373_EGBW_RATE_5G_CTRL_RATE_MASK (0xFFFFF << RTL8373_EGBW_RATE_5G_CTRL_RATE_OFFSET) + +#define RTL8373_DMY_REG0_EGRESS_CTRL_ADDR (0x44A8) + #define RTL8373_DMY_REG0_EGRESS_CTRL_STRIC_WFQ_JUMBO_BUG_FIX_OFFSET (17) + #define RTL8373_DMY_REG0_EGRESS_CTRL_STRIC_WFQ_JUMBO_BUG_FIX_MASK (0x1 << RTL8373_DMY_REG0_EGRESS_CTRL_STRIC_WFQ_JUMBO_BUG_FIX_OFFSET) + #define RTL8373_DMY_REG0_EGRESS_CTRL_SPD_UP_REFILL_OFFSET (16) + #define RTL8373_DMY_REG0_EGRESS_CTRL_SPD_UP_REFILL_MASK (0x1 << RTL8373_DMY_REG0_EGRESS_CTRL_SPD_UP_REFILL_OFFSET) + #define RTL8373_DMY_REG0_EGRESS_CTRL_AMP_FACTOR_OFFSET (0) + #define RTL8373_DMY_REG0_EGRESS_CTRL_AMP_FACTOR_MASK (0xFFFF << RTL8373_DMY_REG0_EGRESS_CTRL_AMP_FACTOR_OFFSET) + +/* + * Feature: Meter Marker + */ +#define RTL8373_SHARED_METER_RATE_CTRL_ADDR(index) (0x5CF0 + (((index) << 2))) /* index: 0-63 */ + #define RTL8373_SHARED_METER_RATE_CTRL_LB_RATE_OFFSET (0) + #define RTL8373_SHARED_METER_RATE_CTRL_LB_RATE_MASK (0xFFFFFF << RTL8373_SHARED_METER_RATE_CTRL_LB_RATE_OFFSET) + +#define RTL8373_SHARED_METER_BURST_CTRL_ADDR(index) (0x5DF0 + (((index) << 2))) /* index: 0-63 */ + #define RTL8373_SHARED_METER_BURST_CTRL_LB_BURST_OFFSET (0) + #define RTL8373_SHARED_METER_BURST_CTRL_LB_BURST_MASK (0xFFFFFFF << RTL8373_SHARED_METER_BURST_CTRL_LB_BURST_OFFSET) + +#define RTL8373_SHARED_METER_MODE_ADDR(index) (0x5EF0 + (((index >> 5) << 2))) /* index: 0-63 */ + #define RTL8373_SHARED_METER_MODE_LB_MODE_OFFSET(index) (index % 0x20) + #define RTL8373_SHARED_METER_MODE_LB_MODE_MASK(index) (0x1 << RTL8373_SHARED_METER_MODE_LB_MODE_OFFSET(index)) + +#define RTL8373_SHARED_METER_EXCEED_ADDR(index) (0x5EF8 + (((index >> 5) << 2))) /* index: 0-63 */ + #define RTL8373_SHARED_METER_EXCEED_LB_EXCEED_OFFSET(index) (index % 0x20) + #define RTL8373_SHARED_METER_EXCEED_LB_EXCEED_MASK(index) (0x1 << RTL8373_SHARED_METER_EXCEED_LB_EXCEED_OFFSET(index)) + +#define RTL8373_SHARED_METER_EXCEED_ICPU_ADDR(index) (0x5F00 + (((index >> 5) << 2))) /* index: 0-63 */ + #define RTL8373_SHARED_METER_EXCEED_ICPU_LB_EXCEED_ICPU_OFFSET(index) (index % 0x20) + #define RTL8373_SHARED_METER_EXCEED_ICPU_LB_EXCEED_ICPU_MASK(index) (0x1 << RTL8373_SHARED_METER_EXCEED_ICPU_LB_EXCEED_ICPU_OFFSET(index)) + +#define RTL8373_SHARED_METER_IPG_CTRL_ADDR(index) (0x5F08 + (((index >> 5) << 2))) /* index: 0-63 */ + #define RTL8373_SHARED_METER_IPG_CTRL_IPG_CNTR_OFFSET(index) (index % 0x20) + #define RTL8373_SHARED_METER_IPG_CTRL_IPG_CNTR_MASK(index) (0x1 << RTL8373_SHARED_METER_IPG_CTRL_IPG_CNTR_OFFSET(index)) + +#define RTL8373_SHARED_METER_LB_CTRL_ADDR (0x5F10) + #define RTL8373_SHARED_METER_LB_CTRL_TICK_OFFSET (16) + #define RTL8373_SHARED_METER_LB_CTRL_TICK_MASK (0xFFFF << RTL8373_SHARED_METER_LB_CTRL_TICK_OFFSET) + #define RTL8373_SHARED_METER_LB_CTRL_TKN_OFFSET (0) + #define RTL8373_SHARED_METER_LB_CTRL_TKN_MASK (0xFFFF << RTL8373_SHARED_METER_LB_CTRL_TKN_OFFSET) + +#define RTL8373_SHARED_METER_LB_PPS_CTRL_ADDR (0x5F14) + #define RTL8373_SHARED_METER_LB_PPS_CTRL_TICK_OFFSET (16) + #define RTL8373_SHARED_METER_LB_PPS_CTRL_TICK_MASK (0xFFFF << RTL8373_SHARED_METER_LB_PPS_CTRL_TICK_OFFSET) + #define RTL8373_SHARED_METER_LB_PPS_CTRL_TKN_OFFSET (0) + #define RTL8373_SHARED_METER_LB_PPS_CTRL_TKN_MASK (0xFFFF << RTL8373_SHARED_METER_LB_PPS_CTRL_TKN_OFFSET) + +/* + * Feature: FlowControl & Backpressure + */ +#define RTL8373_FC_CTRL_ADDR (0x7120) + #define RTL8373_FC_CTRL_JUMBO_FRAME_CNT_OFFSET (16) + #define RTL8373_FC_CTRL_JUMBO_FRAME_CNT_MASK (0xFFF << RTL8373_FC_CTRL_JUMBO_FRAME_CNT_OFFSET) + #define RTL8373_FC_CTRL_PRECISE_DROP_ALL_EN_OFFSET (1) + #define RTL8373_FC_CTRL_PRECISE_DROP_ALL_EN_MASK (0x1 << RTL8373_FC_CTRL_PRECISE_DROP_ALL_EN_OFFSET) + +#define RTL8373_FC_PORT_ACT_CTRL_ADDR(port) (0x7124 + (((port) << 2))) /* port: 0-9 */ + #define RTL8373_FC_PORT_ACT_CTRL_ACT_OFFSET (12) + #define RTL8373_FC_PORT_ACT_CTRL_ACT_MASK (0x1 << RTL8373_FC_PORT_ACT_CTRL_ACT_OFFSET) + #define RTL8373_FC_PORT_ACT_CTRL_ALLOW_PAGE_CNT_OFFSET (0) + #define RTL8373_FC_PORT_ACT_CTRL_ALLOW_PAGE_CNT_MASK (0xFFF << RTL8373_FC_PORT_ACT_CTRL_ALLOW_PAGE_CNT_OFFSET) + +#define RTL8373_FC_GLB_SYS_UTIL_THR_ADDR (0x714C) + #define RTL8373_FC_GLB_SYS_UTIL_THR_THR_OFF_OFFSET (12) + #define RTL8373_FC_GLB_SYS_UTIL_THR_THR_OFF_MASK (0xFFF << RTL8373_FC_GLB_SYS_UTIL_THR_THR_OFF_OFFSET) + #define RTL8373_FC_GLB_SYS_UTIL_THR_THR_ON_OFFSET (0) + #define RTL8373_FC_GLB_SYS_UTIL_THR_THR_ON_MASK (0xFFF << RTL8373_FC_GLB_SYS_UTIL_THR_THR_ON_OFFSET) + +#define RTL8373_FC_GLB_DROP_THR_ADDR (0x7150) + #define RTL8373_FC_GLB_DROP_THR_PUB_PAGE_OFFSET (16) + #define RTL8373_FC_GLB_DROP_THR_PUB_PAGE_MASK (0xFFF << RTL8373_FC_GLB_DROP_THR_PUB_PAGE_OFFSET) + #define RTL8373_FC_GLB_DROP_THR_DROP_ALL_OFFSET (0) + #define RTL8373_FC_GLB_DROP_THR_DROP_ALL_MASK (0xFFF << RTL8373_FC_GLB_DROP_THR_DROP_ALL_OFFSET) + +#define RTL8373_FC_GLB_HI_THR_ADDR (0x7154) + #define RTL8373_FC_GLB_HI_THR_ON_OFFSET (16) + #define RTL8373_FC_GLB_HI_THR_ON_MASK (0xFFF << RTL8373_FC_GLB_HI_THR_ON_OFFSET) + #define RTL8373_FC_GLB_HI_THR_OFF_OFFSET (0) + #define RTL8373_FC_GLB_HI_THR_OFF_MASK (0xFFF << RTL8373_FC_GLB_HI_THR_OFF_OFFSET) + +#define RTL8373_FC_GLB_LO_THR_ADDR (0x7158) + #define RTL8373_FC_GLB_LO_THR_ON_OFFSET (16) + #define RTL8373_FC_GLB_LO_THR_ON_MASK (0xFFF << RTL8373_FC_GLB_LO_THR_ON_OFFSET) + #define RTL8373_FC_GLB_LO_THR_OFF_OFFSET (0) + #define RTL8373_FC_GLB_LO_THR_OFF_MASK (0xFFF << RTL8373_FC_GLB_LO_THR_OFF_OFFSET) + +#define RTL8373_FC_GLB_FCOFF_HI_THR_ADDR (0x715C) + #define RTL8373_FC_GLB_FCOFF_HI_THR_ON_OFFSET (16) + #define RTL8373_FC_GLB_FCOFF_HI_THR_ON_MASK (0xFFF << RTL8373_FC_GLB_FCOFF_HI_THR_ON_OFFSET) + #define RTL8373_FC_GLB_FCOFF_HI_THR_OFF_OFFSET (0) + #define RTL8373_FC_GLB_FCOFF_HI_THR_OFF_MASK (0xFFF << RTL8373_FC_GLB_FCOFF_HI_THR_OFF_OFFSET) + +#define RTL8373_FC_GLB_FCOFF_LO_THR_ADDR (0x7160) + #define RTL8373_FC_GLB_FCOFF_LO_THR_ON_OFFSET (16) + #define RTL8373_FC_GLB_FCOFF_LO_THR_ON_MASK (0xFFF << RTL8373_FC_GLB_FCOFF_LO_THR_ON_OFFSET) + #define RTL8373_FC_GLB_FCOFF_LO_THR_OFF_OFFSET (0) + #define RTL8373_FC_GLB_FCOFF_LO_THR_OFF_MASK (0xFFF << RTL8373_FC_GLB_FCOFF_LO_THR_OFF_OFFSET) + +#define RTL8373_FC_JUMBO_HI_THR_ADDR (0x7164) + #define RTL8373_FC_JUMBO_HI_THR_ON_OFFSET (16) + #define RTL8373_FC_JUMBO_HI_THR_ON_MASK (0xFFF << RTL8373_FC_JUMBO_HI_THR_ON_OFFSET) + #define RTL8373_FC_JUMBO_HI_THR_OFF_OFFSET (0) + #define RTL8373_FC_JUMBO_HI_THR_OFF_MASK (0xFFF << RTL8373_FC_JUMBO_HI_THR_OFF_OFFSET) + +#define RTL8373_FC_JUMBO_LO_THR_ADDR (0x7168) + #define RTL8373_FC_JUMBO_LO_THR_ON_OFFSET (16) + #define RTL8373_FC_JUMBO_LO_THR_ON_MASK (0xFFF << RTL8373_FC_JUMBO_LO_THR_ON_OFFSET) + #define RTL8373_FC_JUMBO_LO_THR_OFF_OFFSET (0) + #define RTL8373_FC_JUMBO_LO_THR_OFF_MASK (0xFFF << RTL8373_FC_JUMBO_LO_THR_OFF_OFFSET) + +#define RTL8373_FC_JUMBO_FCOFF_HI_THR_ADDR (0x716C) + #define RTL8373_FC_JUMBO_FCOFF_HI_THR_ON_OFFSET (16) + #define RTL8373_FC_JUMBO_FCOFF_HI_THR_ON_MASK (0xFFF << RTL8373_FC_JUMBO_FCOFF_HI_THR_ON_OFFSET) + #define RTL8373_FC_JUMBO_FCOFF_HI_THR_OFF_OFFSET (0) + #define RTL8373_FC_JUMBO_FCOFF_HI_THR_OFF_MASK (0xFFF << RTL8373_FC_JUMBO_FCOFF_HI_THR_OFF_OFFSET) + +#define RTL8373_FC_JUMBO_FCOFF_LO_THR_ADDR (0x7170) + #define RTL8373_FC_JUMBO_FCOFF_LO_THR_ON_OFFSET (16) + #define RTL8373_FC_JUMBO_FCOFF_LO_THR_ON_MASK (0xFFF << RTL8373_FC_JUMBO_FCOFF_LO_THR_ON_OFFSET) + #define RTL8373_FC_JUMBO_FCOFF_LO_THR_OFF_OFFSET (0) + #define RTL8373_FC_JUMBO_FCOFF_LO_THR_OFF_MASK (0xFFF << RTL8373_FC_JUMBO_FCOFF_LO_THR_OFF_OFFSET) + +#define RTL8373_FC_JUMBO_THR_ADJUST_ADDR (0x7174) + #define RTL8373_FC_JUMBO_THR_ADJUST_EN_OFFSET (31) + #define RTL8373_FC_JUMBO_THR_ADJUST_EN_MASK (0x1 << RTL8373_FC_JUMBO_THR_ADJUST_EN_OFFSET) + #define RTL8373_FC_JUMBO_THR_ADJUST_STS_OFFSET (30) + #define RTL8373_FC_JUMBO_THR_ADJUST_STS_MASK (0x1 << RTL8373_FC_JUMBO_THR_ADJUST_STS_OFFSET) + #define RTL8373_FC_JUMBO_THR_ADJUST_PKT_LEN_OFFSET (16) + #define RTL8373_FC_JUMBO_THR_ADJUST_PKT_LEN_MASK (0x3FFF << RTL8373_FC_JUMBO_THR_ADJUST_PKT_LEN_OFFSET) + #define RTL8373_FC_JUMBO_THR_ADJUST_SYS_USED_PAGE_THR_OFFSET (0) + #define RTL8373_FC_JUMBO_THR_ADJUST_SYS_USED_PAGE_THR_MASK (0xFFF << RTL8373_FC_JUMBO_THR_ADJUST_SYS_USED_PAGE_THR_OFFSET) + +#define RTL8373_FC_PORT_HI_THR_ADDR(index) (0x7178 + (((index) << 2))) /* index: 0-3 */ + #define RTL8373_FC_PORT_HI_THR_ON_OFFSET (16) + #define RTL8373_FC_PORT_HI_THR_ON_MASK (0xFFF << RTL8373_FC_PORT_HI_THR_ON_OFFSET) + #define RTL8373_FC_PORT_HI_THR_OFF_OFFSET (0) + #define RTL8373_FC_PORT_HI_THR_OFF_MASK (0xFFF << RTL8373_FC_PORT_HI_THR_OFF_OFFSET) + +#define RTL8373_FC_PORT_LO_THR_ADDR(index) (0x7188 + (((index) << 2))) /* index: 0-3 */ + #define RTL8373_FC_PORT_LO_THR_ON_OFFSET (16) + #define RTL8373_FC_PORT_LO_THR_ON_MASK (0xFFF << RTL8373_FC_PORT_LO_THR_ON_OFFSET) + #define RTL8373_FC_PORT_LO_THR_OFF_OFFSET (0) + #define RTL8373_FC_PORT_LO_THR_OFF_MASK (0xFFF << RTL8373_FC_PORT_LO_THR_OFF_OFFSET) + +#define RTL8373_FC_PORT_FCOFF_HI_THR_ADDR(index) (0x7198 + (((index) << 2))) /* index: 0-3 */ + #define RTL8373_FC_PORT_FCOFF_HI_THR_ON_OFFSET (16) + #define RTL8373_FC_PORT_FCOFF_HI_THR_ON_MASK (0xFFF << RTL8373_FC_PORT_FCOFF_HI_THR_ON_OFFSET) + #define RTL8373_FC_PORT_FCOFF_HI_THR_OFF_OFFSET (0) + #define RTL8373_FC_PORT_FCOFF_HI_THR_OFF_MASK (0xFFF << RTL8373_FC_PORT_FCOFF_HI_THR_OFF_OFFSET) + +#define RTL8373_FC_PORT_FCOFF_LO_THR_ADDR(index) (0x71A8 + (((index) << 2))) /* index: 0-3 */ + #define RTL8373_FC_PORT_FCOFF_LO_THR_ON_OFFSET (16) + #define RTL8373_FC_PORT_FCOFF_LO_THR_ON_MASK (0xFFF << RTL8373_FC_PORT_FCOFF_LO_THR_ON_OFFSET) + #define RTL8373_FC_PORT_FCOFF_LO_THR_OFF_OFFSET (0) + #define RTL8373_FC_PORT_FCOFF_LO_THR_OFF_MASK (0xFFF << RTL8373_FC_PORT_FCOFF_LO_THR_OFF_OFFSET) + +#define RTL8373_FC_PORT_GUAR_THR_ADDR(index) (0x71B8 + (((index) << 2))) /* index: 0-3 */ + #define RTL8373_FC_PORT_GUAR_THR_THR_OFFSET (0) + #define RTL8373_FC_PORT_GUAR_THR_THR_MASK (0xFFF << RTL8373_FC_PORT_GUAR_THR_THR_OFFSET) + +#define RTL8373_FC_PORT_THR_SET_SEL_ADDR(port) (0x71C8 + (((port / 10) << 2))) /* port: 0-9 */ + #define RTL8373_FC_PORT_THR_SET_SEL_IDX_OFFSET(port) ((port % 0xA) << 1) + #define RTL8373_FC_PORT_THR_SET_SEL_IDX_MASK(port) (0x3 << RTL8373_FC_PORT_THR_SET_SEL_IDX_OFFSET(port)) + +#define RTL8373_FC_PORT_EGR_DROP_CTRL_ADDR(port) (0x50F4 + (((port) << 2))) /* port: 0-9 */ + #define RTL8373_FC_PORT_EGR_DROP_CTRL_REF_RXCNGST_OFFSET (1) + #define RTL8373_FC_PORT_EGR_DROP_CTRL_REF_RXCNGST_MASK (0x1 << RTL8373_FC_PORT_EGR_DROP_CTRL_REF_RXCNGST_OFFSET) + #define RTL8373_FC_PORT_EGR_DROP_CTRL_HOL_PRVNT_EN_OFFSET (0) + #define RTL8373_FC_PORT_EGR_DROP_CTRL_HOL_PRVNT_EN_MASK (0x1 << RTL8373_FC_PORT_EGR_DROP_CTRL_HOL_PRVNT_EN_OFFSET) + +#define RTL8373_FC_HOL_PRVNT_CTRL_ADDR (0x511C) + #define RTL8373_FC_HOL_PRVNT_CTRL_BC_EN_OFFSET (2) + #define RTL8373_FC_HOL_PRVNT_CTRL_BC_EN_MASK (0x1 << RTL8373_FC_HOL_PRVNT_CTRL_BC_EN_OFFSET) + #define RTL8373_FC_HOL_PRVNT_CTRL_L2_MC_EN_OFFSET (1) + #define RTL8373_FC_HOL_PRVNT_CTRL_L2_MC_EN_MASK (0x1 << RTL8373_FC_HOL_PRVNT_CTRL_L2_MC_EN_OFFSET) + #define RTL8373_FC_HOL_PRVNT_CTRL_UNKN_UC_EN_OFFSET (0) + #define RTL8373_FC_HOL_PRVNT_CTRL_UNKN_UC_EN_MASK (0x1 << RTL8373_FC_HOL_PRVNT_CTRL_UNKN_UC_EN_OFFSET) + +#define RTL8373_FC_PORT_Q_EGR_DROP_CTRL_SET_ADDR(index1, index2) (0x5120 + (index1 << 2) + (((index2 >> 3) << 2))) /* index1: 0-9, index2: 0-7 */ + #define RTL8373_FC_PORT_Q_EGR_DROP_CTRL_SET_EN_OFFSET(index2) (index2 % 0x8) + #define RTL8373_FC_PORT_Q_EGR_DROP_CTRL_SET_EN_MASK(index2) (0x1 << RTL8373_FC_PORT_Q_EGR_DROP_CTRL_SET_EN_OFFSET(index2)) + +#define RTL8373_FC_PORT_Q_EGR_FORCE_DROP_CTRL_SET_ADDR(index1, index2) (0x5148 + (index1 << 2) + (((index2 >> 3) << 2))) /* index1: 0-9, index2: 0-7 */ + #define RTL8373_FC_PORT_Q_EGR_FORCE_DROP_CTRL_SET_EN_OFFSET(index2) (index2 % 0x8) + #define RTL8373_FC_PORT_Q_EGR_FORCE_DROP_CTRL_SET_EN_MASK(index2) (0x1 << RTL8373_FC_PORT_Q_EGR_FORCE_DROP_CTRL_SET_EN_OFFSET(index2)) + +#define RTL8373_FC_Q_EGR_DROP_THR_ADDR(index1, index2) (0x44AC + (index1 << 4) + (((index2) << 2))) /* index1: 0-7, index2: 0-3 */ + #define RTL8373_FC_Q_EGR_DROP_THR_ON_OFFSET (16) + #define RTL8373_FC_Q_EGR_DROP_THR_ON_MASK (0xFFF << RTL8373_FC_Q_EGR_DROP_THR_ON_OFFSET) + #define RTL8373_FC_Q_EGR_DROP_THR_OFF_OFFSET (0) + #define RTL8373_FC_Q_EGR_DROP_THR_OFF_MASK (0xFFF << RTL8373_FC_Q_EGR_DROP_THR_OFF_OFFSET) + +#define RTL8373_FC_PORT_EGR_DROP_THR_SET_SEL_ADDR(port) (0x452C + (((port / 10) << 2))) /* port: 0-9 */ + #define RTL8373_FC_PORT_EGR_DROP_THR_SET_SEL_IDX_OFFSET(port) ((port % 0xA) << 1) + #define RTL8373_FC_PORT_EGR_DROP_THR_SET_SEL_IDX_MASK(port) (0x3 << RTL8373_FC_PORT_EGR_DROP_THR_SET_SEL_IDX_OFFSET(port)) + +#define RTL8373_FC_GLB_PAGE_CNT_ADDR (0x71CC) + #define RTL8373_FC_GLB_PAGE_CNT_GLB_PAGE_CNT_OFFSET (0) + #define RTL8373_FC_GLB_PAGE_CNT_GLB_PAGE_CNT_MASK (0xFFF << RTL8373_FC_GLB_PAGE_CNT_GLB_PAGE_CNT_OFFSET) + +#define RTL8373_FC_PORT_PAGE_CNT_ADDR(port) (0x71D0 + (((port) << 2))) /* port: 0-9 */ + #define RTL8373_FC_PORT_PAGE_CNT_P_PAGE_CNT_IGR_OFFSET (0) + #define RTL8373_FC_PORT_PAGE_CNT_P_PAGE_CNT_IGR_MASK (0xFFF << RTL8373_FC_PORT_PAGE_CNT_P_PAGE_CNT_IGR_OFFSET) + +#define RTL8373_FC_GLB_PAGE_PEAKCNT_ADDR (0x71F8) + #define RTL8373_FC_GLB_PAGE_PEAKCNT_GLB_PAGE_PEAKCNT_OFFSET (0) + #define RTL8373_FC_GLB_PAGE_PEAKCNT_GLB_PAGE_PEAKCNT_MASK (0xFFF << RTL8373_FC_GLB_PAGE_PEAKCNT_GLB_PAGE_PEAKCNT_OFFSET) + +#define RTL8373_FC_PORT_CUR_PAGE_CNT_ADDR(port) (0x71FC + (((port) << 2))) /* port: 0-9 */ + #define RTL8373_FC_PORT_CUR_PAGE_CNT_P_PAGE_CURCNT_OFFSET (0) + #define RTL8373_FC_PORT_CUR_PAGE_CNT_P_PAGE_CURCNT_MASK (0xFFF << RTL8373_FC_PORT_CUR_PAGE_CNT_P_PAGE_CURCNT_OFFSET) + +#define RTL8373_FC_PORT_PEAK_PAGE_CNT_ADDR(port) (0x7224 + (((port) << 2))) /* port: 0-9 */ + #define RTL8373_FC_PORT_PEAK_PAGE_CNT_GLB_PAGE_CURCNT_OFFSET (16) + #define RTL8373_FC_PORT_PEAK_PAGE_CNT_GLB_PAGE_CURCNT_MASK (0xFFF << RTL8373_FC_PORT_PEAK_PAGE_CNT_GLB_PAGE_CURCNT_OFFSET) + #define RTL8373_FC_PORT_PEAK_PAGE_CNT_P_PAGE_PEAKCNT_IGR_OFFSET (0) + #define RTL8373_FC_PORT_PEAK_PAGE_CNT_P_PAGE_PEAKCNT_IGR_MASK (0xFFF << RTL8373_FC_PORT_PEAK_PAGE_CNT_P_PAGE_PEAKCNT_IGR_OFFSET) + +#define RTL8373_FC_PORT_EGR_PAGE_CNT_ADDR(port) (0x1CE4 + (((port) << 10))) /* port: 0-9 */ + #define RTL8373_FC_PORT_EGR_PAGE_CNT_P_PAGE_PEAKCNT_EGR_OFFSET (16) + #define RTL8373_FC_PORT_EGR_PAGE_CNT_P_PAGE_PEAKCNT_EGR_MASK (0xFFF << RTL8373_FC_PORT_EGR_PAGE_CNT_P_PAGE_PEAKCNT_EGR_OFFSET) + #define RTL8373_FC_PORT_EGR_PAGE_CNT_P_PAGE_CNT_EGR_OFFSET (0) + #define RTL8373_FC_PORT_EGR_PAGE_CNT_P_PAGE_CNT_EGR_MASK (0xFFF << RTL8373_FC_PORT_EGR_PAGE_CNT_P_PAGE_CNT_EGR_OFFSET) + +#define RTL8373_FC_PORT_Q_EGR_PAGE_CNT_SET_ADDR(port, index) (0x1CE8 + (port << 10) + (((index) << 2))) /* port: 0-9, index: 0-7 */ + #define RTL8373_FC_PORT_Q_EGR_PAGE_CNT_SET_Q_PAGE_PEAKCNT_OFFSET (16) + #define RTL8373_FC_PORT_Q_EGR_PAGE_CNT_SET_Q_PAGE_PEAKCNT_MASK (0xFFF << RTL8373_FC_PORT_Q_EGR_PAGE_CNT_SET_Q_PAGE_PEAKCNT_OFFSET) + #define RTL8373_FC_PORT_Q_EGR_PAGE_CNT_SET_Q_PAGE_CNT_OFFSET (0) + #define RTL8373_FC_PORT_Q_EGR_PAGE_CNT_SET_Q_PAGE_CNT_MASK (0xFFF << RTL8373_FC_PORT_Q_EGR_PAGE_CNT_SET_Q_PAGE_CNT_OFFSET) + +#define RTL8373_FC_PORT_Q_EGR_PKT_CNT_SET_ADDR(port, index) (0x1D08 + (port << 10) + (((index) << 2))) /* port: 0-9, index: 0-7 */ + #define RTL8373_FC_PORT_Q_EGR_PKT_CNT_SET_Q_PKT_PEAKCNT_OFFSET (16) + #define RTL8373_FC_PORT_Q_EGR_PKT_CNT_SET_Q_PKT_PEAKCNT_MASK (0xFFF << RTL8373_FC_PORT_Q_EGR_PKT_CNT_SET_Q_PKT_PEAKCNT_OFFSET) + #define RTL8373_FC_PORT_Q_EGR_PKT_CNT_SET_Q_PKT_CNT_OFFSET (0) + #define RTL8373_FC_PORT_Q_EGR_PKT_CNT_SET_Q_PKT_CNT_MASK (0xFFF << RTL8373_FC_PORT_Q_EGR_PKT_CNT_SET_Q_PKT_CNT_OFFSET) + +#define RTL8373_FC_PORT_PAGE_CNT_ERROR_ADDR(port) (0x75A4 + (((port / 10) << 2))) /* port: 0-9 */ + #define RTL8373_FC_PORT_PAGE_CNT_ERROR_FLAG_OFFSET(port) (port % 0xA) + #define RTL8373_FC_PORT_PAGE_CNT_ERROR_FLAG_MASK(port) (0x1 << RTL8373_FC_PORT_PAGE_CNT_ERROR_FLAG_OFFSET(port)) + +#define RTL8373_PFC_ENABLE_0_ADDR(port) (0x103C + (((port) << 2))) /* port: 0-1 */ + #define RTL8373_PFC_ENABLE_0_PORT_PFC_EN_OFFSET (24) + #define RTL8373_PFC_ENABLE_0_PORT_PFC_EN_MASK (0x1 << RTL8373_PFC_ENABLE_0_PORT_PFC_EN_OFFSET) + #define RTL8373_PFC_ENABLE_0_PRI_PFC_RX_EN_OFFSET (16) + #define RTL8373_PFC_ENABLE_0_PRI_PFC_RX_EN_MASK (0xFF << RTL8373_PFC_ENABLE_0_PRI_PFC_RX_EN_OFFSET) + #define RTL8373_PFC_ENABLE_0_PRI_PFC_TX_EN_OFFSET (8) + #define RTL8373_PFC_ENABLE_0_PRI_PFC_TX_EN_MASK (0xFF << RTL8373_PFC_ENABLE_0_PRI_PFC_TX_EN_OFFSET) + #define RTL8373_PFC_ENABLE_0_PRI_PFC_EN_OFFSET (0) + #define RTL8373_PFC_ENABLE_0_PRI_PFC_EN_MASK (0xFF << RTL8373_PFC_ENABLE_0_PRI_PFC_EN_OFFSET) + +#define RTL8373_PFC_ENABLE_1_ADDR(port) (0x724C + (((port) << 2))) /* port: 0-1 */ + #define RTL8373_PFC_ENABLE_1_PG_PFC_EN_OFFSET (0) + #define RTL8373_PFC_ENABLE_1_PG_PFC_EN_MASK (0xFF << RTL8373_PFC_ENABLE_1_PG_PFC_EN_OFFSET) + +#define RTL8373_PFC_CTRL_0_ADDR(port) (0x551C + (((port) << 2))) /* port: 0-1 */ + #define RTL8373_PFC_CTRL_0_UNTAG_PRI_SRC_OFFSET (14) + #define RTL8373_PFC_CTRL_0_UNTAG_PRI_SRC_MASK (0x1 << RTL8373_PFC_CTRL_0_UNTAG_PRI_SRC_OFFSET) + #define RTL8373_PFC_CTRL_0_PFC_PCPSRC_SEL_OFFSET (12) + #define RTL8373_PFC_CTRL_0_PFC_PCPSRC_SEL_MASK (0x3 << RTL8373_PFC_CTRL_0_PFC_PCPSRC_SEL_OFFSET) + #define RTL8373_PFC_CTRL_0_PFC_PCP_UTAG_OFFSET (9) + #define RTL8373_PFC_CTRL_0_PFC_PCP_UTAG_MASK (0x7 << RTL8373_PFC_CTRL_0_PFC_PCP_UTAG_OFFSET) + #define RTL8373_PFC_CTRL_0_PFC_MODE_SEL_OFFSET (8) + #define RTL8373_PFC_CTRL_0_PFC_MODE_SEL_MASK (0x1 << RTL8373_PFC_CTRL_0_PFC_MODE_SEL_OFFSET) + #define RTL8373_PFC_CTRL_0_PFC_STSPRI_OFFSET (0) + #define RTL8373_PFC_CTRL_0_PFC_STSPRI_MASK (0xFF << RTL8373_PFC_CTRL_0_PFC_STSPRI_OFFSET) + +#define RTL8373_PFC_ACTDROP_CTRL_ADDR(index1, index2) (0x5524 + (index1 << 5) + (((index2) << 2))) /* index1: 0-1, index2: 0-7 */ + #define RTL8373_PFC_ACTDROP_CTRL_PFC_ACTDROP_PG_EN_OFFSET (12) + #define RTL8373_PFC_ACTDROP_CTRL_PFC_ACTDROP_PG_EN_MASK (0x1 << RTL8373_PFC_ACTDROP_CTRL_PFC_ACTDROP_PG_EN_OFFSET) + #define RTL8373_PFC_ACTDROP_CTRL_PFC_ALLOWPAGE_CNT_OFFSET (0) + #define RTL8373_PFC_ACTDROP_CTRL_PFC_ALLOWPAGE_CNT_MASK (0xFFF << RTL8373_PFC_ACTDROP_CTRL_PFC_ALLOWPAGE_CNT_OFFSET) + +#define RTL8373_P_PFC_THR_ADDR(index) (0x7254 + (((index) << 2))) /* index: 0-2 */ + #define RTL8373_P_PFC_THR_ON_OFFSET (16) + #define RTL8373_P_PFC_THR_ON_MASK (0xFFF << RTL8373_P_PFC_THR_ON_OFFSET) + #define RTL8373_P_PFC_THR_OFF_OFFSET (0) + #define RTL8373_P_PFC_THR_OFF_MASK (0xFFF << RTL8373_P_PFC_THR_OFF_OFFSET) + +#define RTL8373_P_PFCOFF_THR_ADDR(index) (0x7260 + (((index) << 2))) /* index: 0-2 */ + #define RTL8373_P_PFCOFF_THR_ON_OFFSET (16) + #define RTL8373_P_PFCOFF_THR_ON_MASK (0xFFF << RTL8373_P_PFCOFF_THR_ON_OFFSET) + #define RTL8373_P_PFCOFF_THR_OFF_OFFSET (0) + #define RTL8373_P_PFCOFF_THR_OFF_MASK (0xFFF << RTL8373_P_PFCOFF_THR_OFF_OFFSET) + +#define RTL8373_PG_HI_THR_ADDR(index1, index2) (0x726C + (index1 << 5) + (((index2) << 2))) /* index1: 0-2, index2: 0-7 */ + #define RTL8373_PG_HI_THR_ON_OFFSET (16) + #define RTL8373_PG_HI_THR_ON_MASK (0xFFF << RTL8373_PG_HI_THR_ON_OFFSET) + #define RTL8373_PG_HI_THR_OFF_OFFSET (0) + #define RTL8373_PG_HI_THR_OFF_MASK (0xFFF << RTL8373_PG_HI_THR_OFF_OFFSET) + +#define RTL8373_PG_LO_THR_ADDR(index1, index2) (0x72CC + (index1 << 5) + (((index2) << 2))) /* index1: 0-2, index2: 0-7 */ + #define RTL8373_PG_LO_THR_ON_OFFSET (16) + #define RTL8373_PG_LO_THR_ON_MASK (0xFFF << RTL8373_PG_LO_THR_ON_OFFSET) + #define RTL8373_PG_LO_THR_OFF_OFFSET (0) + #define RTL8373_PG_LO_THR_OFF_MASK (0xFFF << RTL8373_PG_LO_THR_OFF_OFFSET) + +#define RTL8373_PG_PFCOFF_HI_THR_ADDR(index1, index2) (0x732C + (index1 << 5) + (((index2) << 2))) /* index1: 0-2, index2: 0-7 */ + #define RTL8373_PG_PFCOFF_HI_THR_ON_OFFSET (16) + #define RTL8373_PG_PFCOFF_HI_THR_ON_MASK (0xFFF << RTL8373_PG_PFCOFF_HI_THR_ON_OFFSET) + #define RTL8373_PG_PFCOFF_HI_THR_OFF_OFFSET (0) + #define RTL8373_PG_PFCOFF_HI_THR_OFF_MASK (0xFFF << RTL8373_PG_PFCOFF_HI_THR_OFF_OFFSET) + +#define RTL8373_PG_PFCOFF_LO_THR_ADDR(index1, index2) (0x738C + (index1 << 5) + (((index2) << 2))) /* index1: 0-2, index2: 0-7 */ + #define RTL8373_PG_PFCOFF_LO_THR_ON_OFFSET (16) + #define RTL8373_PG_PFCOFF_LO_THR_ON_MASK (0xFFF << RTL8373_PG_PFCOFF_LO_THR_ON_OFFSET) + #define RTL8373_PG_PFCOFF_LO_THR_OFF_OFFSET (0) + #define RTL8373_PG_PFCOFF_LO_THR_OFF_MASK (0xFFF << RTL8373_PG_PFCOFF_LO_THR_OFF_OFFSET) + +#define RTL8373_PG_GURANTEE_THR_ADDR(index1, index2) (0x73EC + (index1 << 5) + (((index2) << 2))) /* index1: 0-2, index2: 0-7 */ + #define RTL8373_PG_GURANTEE_THR_PG_PFCON_GURANTEE_THR_OFFSET (16) + #define RTL8373_PG_GURANTEE_THR_PG_PFCON_GURANTEE_THR_MASK (0xFFF << RTL8373_PG_GURANTEE_THR_PG_PFCON_GURANTEE_THR_OFFSET) + #define RTL8373_PG_GURANTEE_THR_PG_PFCOFF_GURANTEE_THR_OFFSET (0) + #define RTL8373_PG_GURANTEE_THR_PG_PFCOFF_GURANTEE_THR_MASK (0xFFF << RTL8373_PG_GURANTEE_THR_PG_PFCOFF_GURANTEE_THR_OFFSET) + +#define RTL8373_PFC_CTRL_1_ADDR(port) (0x744C + (((port) << 2))) /* port: 0-1 */ + #define RTL8373_PFC_CTRL_1_PFC_PG_FORCE_CNG_EN_OFFSET (24) + #define RTL8373_PFC_CTRL_1_PFC_PG_FORCE_CNG_EN_MASK (0xFF << RTL8373_PFC_CTRL_1_PFC_PG_FORCE_CNG_EN_OFFSET) + #define RTL8373_PFC_CTRL_1_PFC_PG_FORCE_CNG_VALUE_OFFSET (16) + #define RTL8373_PFC_CTRL_1_PFC_PG_FORCE_CNG_VALUE_MASK (0xFF << RTL8373_PFC_CTRL_1_PFC_PG_FORCE_CNG_VALUE_OFFSET) + #define RTL8373_PFC_CTRL_1_PFC_PG_ISCNG_OFFSET (8) + #define RTL8373_PFC_CTRL_1_PFC_PG_ISCNG_MASK (0xFF << RTL8373_PFC_CTRL_1_PFC_PG_ISCNG_OFFSET) + #define RTL8373_PFC_CTRL_1_P_PG_REF_PORT_OFFSET (0) + #define RTL8373_PFC_CTRL_1_P_PG_REF_PORT_MASK (0xFF << RTL8373_PFC_CTRL_1_P_PG_REF_PORT_OFFSET) + +#define RTL8373_PFC_CTRL_2_ADDR(port) (0x1044 + (((port) << 2))) /* port: 0-1 */ + #define RTL8373_PFC_CTRL_2_PFC_STSPRI_FORCE_EN_OFFSET (8) + #define RTL8373_PFC_CTRL_2_PFC_STSPRI_FORCE_EN_MASK (0xFF << RTL8373_PFC_CTRL_2_PFC_STSPRI_FORCE_EN_OFFSET) + #define RTL8373_PFC_CTRL_2_PFC_STSPRI_FORCE_VALUE_OFFSET (0) + #define RTL8373_PFC_CTRL_2_PFC_STSPRI_FORCE_VALUE_MASK (0xFF << RTL8373_PFC_CTRL_2_PFC_STSPRI_FORCE_VALUE_OFFSET) + +#define RTL8373_PG_2_PEV_TABLE_ADDR(port) (0x104C + (((port) << 3))) /* port: 0-1 */ + #define RTL8373_PG_2_PEV_TABLE_PG7_PEV_MAP_OFFSET (24) + #define RTL8373_PG_2_PEV_TABLE_PG7_PEV_MAP_MASK (0xFF << RTL8373_PG_2_PEV_TABLE_PG7_PEV_MAP_OFFSET) + #define RTL8373_PG_2_PEV_TABLE_PG6_PEV_MAP_OFFSET (16) + #define RTL8373_PG_2_PEV_TABLE_PG6_PEV_MAP_MASK (0xFF << RTL8373_PG_2_PEV_TABLE_PG6_PEV_MAP_OFFSET) + #define RTL8373_PG_2_PEV_TABLE_PG5_PEV_MAP_OFFSET (8) + #define RTL8373_PG_2_PEV_TABLE_PG5_PEV_MAP_MASK (0xFF << RTL8373_PG_2_PEV_TABLE_PG5_PEV_MAP_OFFSET) + #define RTL8373_PG_2_PEV_TABLE_PG4_PEV_MAP_OFFSET (0) + #define RTL8373_PG_2_PEV_TABLE_PG4_PEV_MAP_MASK (0xFF << RTL8373_PG_2_PEV_TABLE_PG4_PEV_MAP_OFFSET) + #define RTL8373_PG_2_PEV_TABLE_PG3_PEV_MAP_OFFSET (56) + #define RTL8373_PG_2_PEV_TABLE_PG3_PEV_MAP_MASK (0xFF << RTL8373_PG_2_PEV_TABLE_PG3_PEV_MAP_OFFSET) + #define RTL8373_PG_2_PEV_TABLE_PG2_PEV_MAP_OFFSET (48) + #define RTL8373_PG_2_PEV_TABLE_PG2_PEV_MAP_MASK (0xFF << RTL8373_PG_2_PEV_TABLE_PG2_PEV_MAP_OFFSET) + #define RTL8373_PG_2_PEV_TABLE_PG1_PEV_MAP_OFFSET (40) + #define RTL8373_PG_2_PEV_TABLE_PG1_PEV_MAP_MASK (0xFF << RTL8373_PG_2_PEV_TABLE_PG1_PEV_MAP_OFFSET) + #define RTL8373_PG_2_PEV_TABLE_PG0_PEV_MAP_OFFSET (32) + #define RTL8373_PG_2_PEV_TABLE_PG0_PEV_MAP_MASK (0xFF << RTL8373_PG_2_PEV_TABLE_PG0_PEV_MAP_OFFSET) + +#define RTL8373_DPRI_2_PG_TABLE_ADDR(port) (0x5564 + (((port) << 2))) /* port: 0-1 */ + #define RTL8373_DPRI_2_PG_TABLE_DPRI7_PG_MAP_OFFSET (21) + #define RTL8373_DPRI_2_PG_TABLE_DPRI7_PG_MAP_MASK (0x7 << RTL8373_DPRI_2_PG_TABLE_DPRI7_PG_MAP_OFFSET) + #define RTL8373_DPRI_2_PG_TABLE_DPRI6_PG_MAP_OFFSET (18) + #define RTL8373_DPRI_2_PG_TABLE_DPRI6_PG_MAP_MASK (0x7 << RTL8373_DPRI_2_PG_TABLE_DPRI6_PG_MAP_OFFSET) + #define RTL8373_DPRI_2_PG_TABLE_DPRI5_PG_MAP_OFFSET (15) + #define RTL8373_DPRI_2_PG_TABLE_DPRI5_PG_MAP_MASK (0x7 << RTL8373_DPRI_2_PG_TABLE_DPRI5_PG_MAP_OFFSET) + #define RTL8373_DPRI_2_PG_TABLE_DPRI4_PG_MAP_OFFSET (12) + #define RTL8373_DPRI_2_PG_TABLE_DPRI4_PG_MAP_MASK (0x7 << RTL8373_DPRI_2_PG_TABLE_DPRI4_PG_MAP_OFFSET) + #define RTL8373_DPRI_2_PG_TABLE_DPRI3_PG_MAP_OFFSET (9) + #define RTL8373_DPRI_2_PG_TABLE_DPRI3_PG_MAP_MASK (0x7 << RTL8373_DPRI_2_PG_TABLE_DPRI3_PG_MAP_OFFSET) + #define RTL8373_DPRI_2_PG_TABLE_DPRI2_PG_MAP_OFFSET (6) + #define RTL8373_DPRI_2_PG_TABLE_DPRI2_PG_MAP_MASK (0x7 << RTL8373_DPRI_2_PG_TABLE_DPRI2_PG_MAP_OFFSET) + #define RTL8373_DPRI_2_PG_TABLE_DPRI1_PG_MAP_OFFSET (3) + #define RTL8373_DPRI_2_PG_TABLE_DPRI1_PG_MAP_MASK (0x7 << RTL8373_DPRI_2_PG_TABLE_DPRI1_PG_MAP_OFFSET) + #define RTL8373_DPRI_2_PG_TABLE_DPRI0_PG_MAP_OFFSET (0) + #define RTL8373_DPRI_2_PG_TABLE_DPRI0_PG_MAP_MASK (0x7 << RTL8373_DPRI_2_PG_TABLE_DPRI0_PG_MAP_OFFSET) + +#define RTL8373_PCP_2_PG_TABLE_ADDR(port) (0x556C + (((port) << 2))) /* port: 0-1 */ + #define RTL8373_PCP_2_PG_TABLE_PCP7_PG_MAP_OFFSET (21) + #define RTL8373_PCP_2_PG_TABLE_PCP7_PG_MAP_MASK (0x7 << RTL8373_PCP_2_PG_TABLE_PCP7_PG_MAP_OFFSET) + #define RTL8373_PCP_2_PG_TABLE_PCP6_PG_MAP_OFFSET (18) + #define RTL8373_PCP_2_PG_TABLE_PCP6_PG_MAP_MASK (0x7 << RTL8373_PCP_2_PG_TABLE_PCP6_PG_MAP_OFFSET) + #define RTL8373_PCP_2_PG_TABLE_PCP5_PG_MAP_OFFSET (15) + #define RTL8373_PCP_2_PG_TABLE_PCP5_PG_MAP_MASK (0x7 << RTL8373_PCP_2_PG_TABLE_PCP5_PG_MAP_OFFSET) + #define RTL8373_PCP_2_PG_TABLE_PCP4_PG_MAP_OFFSET (12) + #define RTL8373_PCP_2_PG_TABLE_PCP4_PG_MAP_MASK (0x7 << RTL8373_PCP_2_PG_TABLE_PCP4_PG_MAP_OFFSET) + #define RTL8373_PCP_2_PG_TABLE_PCP3_PG_MAP_OFFSET (9) + #define RTL8373_PCP_2_PG_TABLE_PCP3_PG_MAP_MASK (0x7 << RTL8373_PCP_2_PG_TABLE_PCP3_PG_MAP_OFFSET) + #define RTL8373_PCP_2_PG_TABLE_PCP2_PG_MAP_OFFSET (6) + #define RTL8373_PCP_2_PG_TABLE_PCP2_PG_MAP_MASK (0x7 << RTL8373_PCP_2_PG_TABLE_PCP2_PG_MAP_OFFSET) + #define RTL8373_PCP_2_PG_TABLE_PCP1_PG_MAP_OFFSET (3) + #define RTL8373_PCP_2_PG_TABLE_PCP1_PG_MAP_MASK (0x7 << RTL8373_PCP_2_PG_TABLE_PCP1_PG_MAP_OFFSET) + #define RTL8373_PCP_2_PG_TABLE_PCP0_PG_MAP_OFFSET (0) + #define RTL8373_PCP_2_PG_TABLE_PCP0_PG_MAP_MASK (0x7 << RTL8373_PCP_2_PG_TABLE_PCP0_PG_MAP_OFFSET) + +#define RTL8373_PEV_2_TXQ_TABLE_ADDR(port) (0x105C + (((port) << 3))) /* port: 0-1 */ + #define RTL8373_PEV_2_TXQ_TABLE_PEV7_TXQ_MAP_OFFSET (24) + #define RTL8373_PEV_2_TXQ_TABLE_PEV7_TXQ_MAP_MASK (0xFF << RTL8373_PEV_2_TXQ_TABLE_PEV7_TXQ_MAP_OFFSET) + #define RTL8373_PEV_2_TXQ_TABLE_PEV6_TXQ_MAP_OFFSET (16) + #define RTL8373_PEV_2_TXQ_TABLE_PEV6_TXQ_MAP_MASK (0xFF << RTL8373_PEV_2_TXQ_TABLE_PEV6_TXQ_MAP_OFFSET) + #define RTL8373_PEV_2_TXQ_TABLE_PEV5_TXQ_MAP_OFFSET (8) + #define RTL8373_PEV_2_TXQ_TABLE_PEV5_TXQ_MAP_MASK (0xFF << RTL8373_PEV_2_TXQ_TABLE_PEV5_TXQ_MAP_OFFSET) + #define RTL8373_PEV_2_TXQ_TABLE_PEV4_TXQ_MAP_OFFSET (0) + #define RTL8373_PEV_2_TXQ_TABLE_PEV4_TXQ_MAP_MASK (0xFF << RTL8373_PEV_2_TXQ_TABLE_PEV4_TXQ_MAP_OFFSET) + #define RTL8373_PEV_2_TXQ_TABLE_PEV3_TXQ_MAP_OFFSET (56) + #define RTL8373_PEV_2_TXQ_TABLE_PEV3_TXQ_MAP_MASK (0xFF << RTL8373_PEV_2_TXQ_TABLE_PEV3_TXQ_MAP_OFFSET) + #define RTL8373_PEV_2_TXQ_TABLE_PEV2_TXQ_MAP_OFFSET (48) + #define RTL8373_PEV_2_TXQ_TABLE_PEV2_TXQ_MAP_MASK (0xFF << RTL8373_PEV_2_TXQ_TABLE_PEV2_TXQ_MAP_OFFSET) + #define RTL8373_PEV_2_TXQ_TABLE_PEV1_TXQ_MAP_OFFSET (40) + #define RTL8373_PEV_2_TXQ_TABLE_PEV1_TXQ_MAP_MASK (0xFF << RTL8373_PEV_2_TXQ_TABLE_PEV1_TXQ_MAP_OFFSET) + #define RTL8373_PEV_2_TXQ_TABLE_PEV0_TXQ_MAP_OFFSET (32) + #define RTL8373_PEV_2_TXQ_TABLE_PEV0_TXQ_MAP_MASK (0xFF << RTL8373_PEV_2_TXQ_TABLE_PEV0_TXQ_MAP_OFFSET) + +#define RTL8373_PFC_PORT_PG_RX_PAGE_CNT_ADDR(index1, index2) (0x7454 + (index1 << 5) + (((index2) << 2))) /* index1: 0-1, index2: 0-7 */ + #define RTL8373_PFC_PORT_PG_RX_PAGE_CNT_PG_PAGE_PEAKCNT_OFFSET (16) + #define RTL8373_PFC_PORT_PG_RX_PAGE_CNT_PG_PAGE_PEAKCNT_MASK (0xFFF << RTL8373_PFC_PORT_PG_RX_PAGE_CNT_PG_PAGE_PEAKCNT_OFFSET) + #define RTL8373_PFC_PORT_PG_RX_PAGE_CNT_PG_PAGE_CNT_OFFSET (0) + #define RTL8373_PFC_PORT_PG_RX_PAGE_CNT_PG_PAGE_CNT_MASK (0xFFF << RTL8373_PFC_PORT_PG_RX_PAGE_CNT_PG_PAGE_CNT_OFFSET) + +/* + * Feature: Congestion Avoidance + */ +#define RTL8373_SC_P_CTRL_ADDR (0x4530) + #define RTL8373_SC_P_CTRL_DRAIN_OUT_THR_H_OFFSET (16) + #define RTL8373_SC_P_CTRL_DRAIN_OUT_THR_H_MASK (0xFFF << RTL8373_SC_P_CTRL_DRAIN_OUT_THR_H_OFFSET) + #define RTL8373_SC_P_CTRL_DRAIN_OUT_THR_OFFSET (0) + #define RTL8373_SC_P_CTRL_DRAIN_OUT_THR_MASK (0xFFF << RTL8373_SC_P_CTRL_DRAIN_OUT_THR_OFFSET) + +#define RTL8373_SC_P_EN_ADDR(port) (0x1260 + (((port) << 8))) /* port: 0-9 */ + #define RTL8373_SC_P_EN_CNGST_TMR_H_OFFSET (20) + #define RTL8373_SC_P_EN_CNGST_TMR_H_MASK (0xF << RTL8373_SC_P_EN_CNGST_TMR_H_OFFSET) + #define RTL8373_SC_P_EN_CNGST_SUST_TMR_LMT_H_OFFSET (16) + #define RTL8373_SC_P_EN_CNGST_SUST_TMR_LMT_H_MASK (0xF << RTL8373_SC_P_EN_CNGST_SUST_TMR_LMT_H_OFFSET) + #define RTL8373_SC_P_EN_CNGST_TMR_OFFSET (4) + #define RTL8373_SC_P_EN_CNGST_TMR_MASK (0xF << RTL8373_SC_P_EN_CNGST_TMR_OFFSET) + #define RTL8373_SC_P_EN_CNGST_SUST_TMR_LMT_OFFSET (0) + #define RTL8373_SC_P_EN_CNGST_SUST_TMR_LMT_MASK (0xF << RTL8373_SC_P_EN_CNGST_SUST_TMR_LMT_OFFSET) + +/* + * Feature: Ingress Priority Decision + */ +#define RTL8373_PORT_PRI_ADDR(port) (0x5170 + (((port / 10) << 2))) /* port: 0-9 */ + #define RTL8373_PORT_PRI_PORT_BASE_PRI_OFFSET(port) ((port % 0xA) * 3) + #define RTL8373_PORT_PRI_PORT_BASE_PRI_MASK(port) (0x7 << RTL8373_PORT_PRI_PORT_BASE_PRI_OFFSET(port)) + +#define RTL8373_DOT1Q_PRI_REMAP_ADDR (0x5174) + #define RTL8373_DOT1Q_PRI_REMAP_PRI7_OFFSET (28) + #define RTL8373_DOT1Q_PRI_REMAP_PRI7_MASK (0x7 << RTL8373_DOT1Q_PRI_REMAP_PRI7_OFFSET) + #define RTL8373_DOT1Q_PRI_REMAP_PRI6_OFFSET (24) + #define RTL8373_DOT1Q_PRI_REMAP_PRI6_MASK (0x7 << RTL8373_DOT1Q_PRI_REMAP_PRI6_OFFSET) + #define RTL8373_DOT1Q_PRI_REMAP_PRI5_OFFSET (20) + #define RTL8373_DOT1Q_PRI_REMAP_PRI5_MASK (0x7 << RTL8373_DOT1Q_PRI_REMAP_PRI5_OFFSET) + #define RTL8373_DOT1Q_PRI_REMAP_PRI4_OFFSET (16) + #define RTL8373_DOT1Q_PRI_REMAP_PRI4_MASK (0x7 << RTL8373_DOT1Q_PRI_REMAP_PRI4_OFFSET) + #define RTL8373_DOT1Q_PRI_REMAP_PRI3_OFFSET (12) + #define RTL8373_DOT1Q_PRI_REMAP_PRI3_MASK (0x7 << RTL8373_DOT1Q_PRI_REMAP_PRI3_OFFSET) + #define RTL8373_DOT1Q_PRI_REMAP_PRI2_OFFSET (8) + #define RTL8373_DOT1Q_PRI_REMAP_PRI2_MASK (0x7 << RTL8373_DOT1Q_PRI_REMAP_PRI2_OFFSET) + #define RTL8373_DOT1Q_PRI_REMAP_PRI1_OFFSET (4) + #define RTL8373_DOT1Q_PRI_REMAP_PRI1_MASK (0x7 << RTL8373_DOT1Q_PRI_REMAP_PRI1_OFFSET) + #define RTL8373_DOT1Q_PRI_REMAP_PRI0_OFFSET (0) + #define RTL8373_DOT1Q_PRI_REMAP_PRI0_MASK (0x7 << RTL8373_DOT1Q_PRI_REMAP_PRI0_OFFSET) + +#define RTL8373_PRI_SEL_REMAP_DSCP_ADDR(index) (0x5178 + (((index / 10) << 2))) /* index: 0-63 */ + #define RTL8373_PRI_SEL_REMAP_DSCP_INTPRI_DSCP_OFFSET(index) ((index % 0xA) * 3) + #define RTL8373_PRI_SEL_REMAP_DSCP_INTPRI_DSCP_MASK(index) (0x7 << RTL8373_PRI_SEL_REMAP_DSCP_INTPRI_DSCP_OFFSET(index)) + +#define RTL8373_RSPAN_PRI_REMAP_ADDR (0x5194) + #define RTL8373_RSPAN_PRI_REMAP_PRI7_OFFSET (28) + #define RTL8373_RSPAN_PRI_REMAP_PRI7_MASK (0x7 << RTL8373_RSPAN_PRI_REMAP_PRI7_OFFSET) + #define RTL8373_RSPAN_PRI_REMAP_PRI6_OFFSET (24) + #define RTL8373_RSPAN_PRI_REMAP_PRI6_MASK (0x7 << RTL8373_RSPAN_PRI_REMAP_PRI6_OFFSET) + #define RTL8373_RSPAN_PRI_REMAP_PRI5_OFFSET (20) + #define RTL8373_RSPAN_PRI_REMAP_PRI5_MASK (0x7 << RTL8373_RSPAN_PRI_REMAP_PRI5_OFFSET) + #define RTL8373_RSPAN_PRI_REMAP_PRI4_OFFSET (16) + #define RTL8373_RSPAN_PRI_REMAP_PRI4_MASK (0x7 << RTL8373_RSPAN_PRI_REMAP_PRI4_OFFSET) + #define RTL8373_RSPAN_PRI_REMAP_PRI3_OFFSET (12) + #define RTL8373_RSPAN_PRI_REMAP_PRI3_MASK (0x7 << RTL8373_RSPAN_PRI_REMAP_PRI3_OFFSET) + #define RTL8373_RSPAN_PRI_REMAP_PRI2_OFFSET (8) + #define RTL8373_RSPAN_PRI_REMAP_PRI2_MASK (0x7 << RTL8373_RSPAN_PRI_REMAP_PRI2_OFFSET) + #define RTL8373_RSPAN_PRI_REMAP_PRI1_OFFSET (4) + #define RTL8373_RSPAN_PRI_REMAP_PRI1_MASK (0x7 << RTL8373_RSPAN_PRI_REMAP_PRI1_OFFSET) + #define RTL8373_RSPAN_PRI_REMAP_PRI0_OFFSET (0) + #define RTL8373_RSPAN_PRI_REMAP_PRI0_MASK (0x7 << RTL8373_RSPAN_PRI_REMAP_PRI0_OFFSET) + +#define RTL8373_PRI_WEIGHT_ADDR(index) (0x5198 + (((index) << 2))) /* index: 0-1 */ + #define RTL8373_PRI_WEIGHT_SVLAN_WEIGHT_OFFSET (20) + #define RTL8373_PRI_WEIGHT_SVLAN_WEIGHT_MASK (0x1F << RTL8373_PRI_WEIGHT_SVLAN_WEIGHT_OFFSET) + #define RTL8373_PRI_WEIGHT_ACL_WEIGHT_OFFSET (15) + #define RTL8373_PRI_WEIGHT_ACL_WEIGHT_MASK (0x1F << RTL8373_PRI_WEIGHT_ACL_WEIGHT_OFFSET) + #define RTL8373_PRI_WEIGHT_DSCP_WEIGHT_OFFSET (10) + #define RTL8373_PRI_WEIGHT_DSCP_WEIGHT_MASK (0x1F << RTL8373_PRI_WEIGHT_DSCP_WEIGHT_OFFSET) + #define RTL8373_PRI_WEIGHT_PORT_WEIGHT_OFFSET (5) + #define RTL8373_PRI_WEIGHT_PORT_WEIGHT_MASK (0x1F << RTL8373_PRI_WEIGHT_PORT_WEIGHT_OFFSET) + #define RTL8373_PRI_WEIGHT_DOT1Q_WEIGHT_OFFSET (0) + #define RTL8373_PRI_WEIGHT_DOT1Q_WEIGHT_MASK (0x1F << RTL8373_PRI_WEIGHT_DOT1Q_WEIGHT_OFFSET) + +#define RTL8373_PORT_WEIGHT_SEL_ADDR(port) (0x51A0 + (((port / 10) << 2))) /* port: 0-9 */ + #define RTL8373_PORT_WEIGHT_SEL_WEIGHT_SEL_OFFSET(port) (port % 0xA) + #define RTL8373_PORT_WEIGHT_SEL_WEIGHT_SEL_MASK(port) (0x1 << RTL8373_PORT_WEIGHT_SEL_WEIGHT_SEL_OFFSET(port)) + +#define RTL8373_QID_TO_PRI_ADDR(port) (0x51A4 + (((port) << 2))) /* port: 0-9 */ + #define RTL8373_QID_TO_PRI_PRI7QNUM_OFFSET (28) + #define RTL8373_QID_TO_PRI_PRI7QNUM_MASK (0x7 << RTL8373_QID_TO_PRI_PRI7QNUM_OFFSET) + #define RTL8373_QID_TO_PRI_PRI6QNUM_OFFSET (24) + #define RTL8373_QID_TO_PRI_PRI6QNUM_MASK (0x7 << RTL8373_QID_TO_PRI_PRI6QNUM_OFFSET) + #define RTL8373_QID_TO_PRI_PRI5QNUM_OFFSET (20) + #define RTL8373_QID_TO_PRI_PRI5QNUM_MASK (0x7 << RTL8373_QID_TO_PRI_PRI5QNUM_OFFSET) + #define RTL8373_QID_TO_PRI_PRI4QNUM_OFFSET (16) + #define RTL8373_QID_TO_PRI_PRI4QNUM_MASK (0x7 << RTL8373_QID_TO_PRI_PRI4QNUM_OFFSET) + #define RTL8373_QID_TO_PRI_PRI3QNUM_OFFSET (12) + #define RTL8373_QID_TO_PRI_PRI3QNUM_MASK (0x7 << RTL8373_QID_TO_PRI_PRI3QNUM_OFFSET) + #define RTL8373_QID_TO_PRI_PRI2QNUM_OFFSET (8) + #define RTL8373_QID_TO_PRI_PRI2QNUM_MASK (0x7 << RTL8373_QID_TO_PRI_PRI2QNUM_OFFSET) + #define RTL8373_QID_TO_PRI_PRI1QNUM_OFFSET (4) + #define RTL8373_QID_TO_PRI_PRI1QNUM_MASK (0x7 << RTL8373_QID_TO_PRI_PRI1QNUM_OFFSET) + #define RTL8373_QID_TO_PRI_PRI0QNUM_OFFSET (0) + #define RTL8373_QID_TO_PRI_PRI0QNUM_MASK (0x7 << RTL8373_QID_TO_PRI_PRI0QNUM_OFFSET) + +#define RTL8373_INCPU_PRI_REMAP_ADDR (0x51CC) + #define RTL8373_INCPU_PRI_REMAP_INTPRI7_TO_VAL_OFFSET (28) + #define RTL8373_INCPU_PRI_REMAP_INTPRI7_TO_VAL_MASK (0x7 << RTL8373_INCPU_PRI_REMAP_INTPRI7_TO_VAL_OFFSET) + #define RTL8373_INCPU_PRI_REMAP_INTPRI6_TO_VAL_OFFSET (24) + #define RTL8373_INCPU_PRI_REMAP_INTPRI6_TO_VAL_MASK (0x7 << RTL8373_INCPU_PRI_REMAP_INTPRI6_TO_VAL_OFFSET) + #define RTL8373_INCPU_PRI_REMAP_INTPRI5_TO_VAL_OFFSET (20) + #define RTL8373_INCPU_PRI_REMAP_INTPRI5_TO_VAL_MASK (0x7 << RTL8373_INCPU_PRI_REMAP_INTPRI5_TO_VAL_OFFSET) + #define RTL8373_INCPU_PRI_REMAP_INTPRI4_TO_VAL_OFFSET (16) + #define RTL8373_INCPU_PRI_REMAP_INTPRI4_TO_VAL_MASK (0x7 << RTL8373_INCPU_PRI_REMAP_INTPRI4_TO_VAL_OFFSET) + #define RTL8373_INCPU_PRI_REMAP_INTPRI3_TO_VAL_OFFSET (12) + #define RTL8373_INCPU_PRI_REMAP_INTPRI3_TO_VAL_MASK (0x7 << RTL8373_INCPU_PRI_REMAP_INTPRI3_TO_VAL_OFFSET) + #define RTL8373_INCPU_PRI_REMAP_INTPRI2_TO_VAL_OFFSET (8) + #define RTL8373_INCPU_PRI_REMAP_INTPRI2_TO_VAL_MASK (0x7 << RTL8373_INCPU_PRI_REMAP_INTPRI2_TO_VAL_OFFSET) + #define RTL8373_INCPU_PRI_REMAP_INTPRI1_TO_VAL_OFFSET (4) + #define RTL8373_INCPU_PRI_REMAP_INTPRI1_TO_VAL_MASK (0x7 << RTL8373_INCPU_PRI_REMAP_INTPRI1_TO_VAL_OFFSET) + #define RTL8373_INCPU_PRI_REMAP_INTPRI0_TO_VAL_OFFSET (0) + #define RTL8373_INCPU_PRI_REMAP_INTPRI0_TO_VAL_MASK (0x7 << RTL8373_INCPU_PRI_REMAP_INTPRI0_TO_VAL_OFFSET) + +#define RTL8373_EXCPU_PRI_REMAP_ADDR (0x51D0) + #define RTL8373_EXCPU_PRI_REMAP_INTPRI7_TO_VAL_OFFSET (28) + #define RTL8373_EXCPU_PRI_REMAP_INTPRI7_TO_VAL_MASK (0x7 << RTL8373_EXCPU_PRI_REMAP_INTPRI7_TO_VAL_OFFSET) + #define RTL8373_EXCPU_PRI_REMAP_INTPRI6_TO_VAL_OFFSET (24) + #define RTL8373_EXCPU_PRI_REMAP_INTPRI6_TO_VAL_MASK (0x7 << RTL8373_EXCPU_PRI_REMAP_INTPRI6_TO_VAL_OFFSET) + #define RTL8373_EXCPU_PRI_REMAP_INTPRI5_TO_VAL_OFFSET (20) + #define RTL8373_EXCPU_PRI_REMAP_INTPRI5_TO_VAL_MASK (0x7 << RTL8373_EXCPU_PRI_REMAP_INTPRI5_TO_VAL_OFFSET) + #define RTL8373_EXCPU_PRI_REMAP_INTPRI4_TO_VAL_OFFSET (16) + #define RTL8373_EXCPU_PRI_REMAP_INTPRI4_TO_VAL_MASK (0x7 << RTL8373_EXCPU_PRI_REMAP_INTPRI4_TO_VAL_OFFSET) + #define RTL8373_EXCPU_PRI_REMAP_INTPRI3_TO_VAL_OFFSET (12) + #define RTL8373_EXCPU_PRI_REMAP_INTPRI3_TO_VAL_MASK (0x7 << RTL8373_EXCPU_PRI_REMAP_INTPRI3_TO_VAL_OFFSET) + #define RTL8373_EXCPU_PRI_REMAP_INTPRI2_TO_VAL_OFFSET (8) + #define RTL8373_EXCPU_PRI_REMAP_INTPRI2_TO_VAL_MASK (0x7 << RTL8373_EXCPU_PRI_REMAP_INTPRI2_TO_VAL_OFFSET) + #define RTL8373_EXCPU_PRI_REMAP_INTPRI1_TO_VAL_OFFSET (4) + #define RTL8373_EXCPU_PRI_REMAP_INTPRI1_TO_VAL_MASK (0x7 << RTL8373_EXCPU_PRI_REMAP_INTPRI1_TO_VAL_OFFSET) + #define RTL8373_EXCPU_PRI_REMAP_INTPRI0_TO_VAL_OFFSET (0) + #define RTL8373_EXCPU_PRI_REMAP_INTPRI0_TO_VAL_MASK (0x7 << RTL8373_EXCPU_PRI_REMAP_INTPRI0_TO_VAL_OFFSET) + +#define RTL8373_PORT_PRI_DUP_ADDR(port) (0x674C + (((port / 10) << 2))) /* port: 0-9 */ + #define RTL8373_PORT_PRI_DUP_PORT_BASE_PRI_DUP_OFFSET(port) ((port % 0xA) * 3) + #define RTL8373_PORT_PRI_DUP_PORT_BASE_PRI_DUP_MASK(port) (0x7 << RTL8373_PORT_PRI_DUP_PORT_BASE_PRI_DUP_OFFSET(port)) + +/* + * Feature: Scheduling & Queue Management + */ +#define RTL8373_SCHED_PORT_Q_CTRL_SET_ADDR(port, index) (0x1D28 + (port << 10) + (((index) << 2))) /* port: 0-9, index: 0-7 */ + #define RTL8373_SCHED_PORT_Q_CTRL_SET_STRICT_EN_OFFSET (7) + #define RTL8373_SCHED_PORT_Q_CTRL_SET_STRICT_EN_MASK (0x1 << RTL8373_SCHED_PORT_Q_CTRL_SET_STRICT_EN_OFFSET) + #define RTL8373_SCHED_PORT_Q_CTRL_SET_WEIGHT_OFFSET (0) + #define RTL8373_SCHED_PORT_Q_CTRL_SET_WEIGHT_MASK (0x7F << RTL8373_SCHED_PORT_Q_CTRL_SET_WEIGHT_OFFSET) + +#define RTL8373_SCHED_PORT_ALGO_CTRL_ADDR(port) (0x4534 + (((port / 10) << 2))) /* port: 0-9 */ + #define RTL8373_SCHED_PORT_ALGO_CTRL_SCHED_TYPE_OFFSET(port) (port % 0xA) + #define RTL8373_SCHED_PORT_ALGO_CTRL_SCHED_TYPE_MASK(port) (0x1 << RTL8373_SCHED_PORT_ALGO_CTRL_SCHED_TYPE_OFFSET(port)) + +#define RTL8373_CFG_TG_URR_SEL_ADDR (0x4538) + #define RTL8373_CFG_TG_URR_SEL_CFG_TG_URR_SEL_OFFSET (0) + #define RTL8373_CFG_TG_URR_SEL_CFG_TG_URR_SEL_MASK (0x3 << RTL8373_CFG_TG_URR_SEL_CFG_TG_URR_SEL_OFFSET) + +/* + * Feature: Remarking + */ +#define RTL8373_RMK_CTRL_ADDR (0x6750) + #define RTL8373_RMK_CTRL_IPRI_RMK_SRC_OFFSET (1) + #define RTL8373_RMK_CTRL_IPRI_RMK_SRC_MASK (0x1 << RTL8373_RMK_CTRL_IPRI_RMK_SRC_OFFSET) + #define RTL8373_RMK_CTRL_DSCP_RMK_SRC_OFFSET (0) + #define RTL8373_RMK_CTRL_DSCP_RMK_SRC_MASK (0x1 << RTL8373_RMK_CTRL_DSCP_RMK_SRC_OFFSET) + +#define RTL8373_RMK_PORT_CTRL_ADDR(port) (0x6754 + (((port) << 2))) /* port: 0-9 */ + #define RTL8373_RMK_PORT_CTRL_DSCP_RMK_EN_OFFSET (1) + #define RTL8373_RMK_PORT_CTRL_DSCP_RMK_EN_MASK (0x1 << RTL8373_RMK_PORT_CTRL_DSCP_RMK_EN_OFFSET) + #define RTL8373_RMK_PORT_CTRL_IPRI_RMK_EN_OFFSET (0) + #define RTL8373_RMK_PORT_CTRL_IPRI_RMK_EN_MASK (0x1 << RTL8373_RMK_PORT_CTRL_IPRI_RMK_EN_OFFSET) + +#define RTL8373_RMK_INTPRI2IPRI_CTRL_ADDR (0x677C) + #define RTL8373_RMK_INTPRI2IPRI_CTRL_IPRI7_OFFSET (28) + #define RTL8373_RMK_INTPRI2IPRI_CTRL_IPRI7_MASK (0x7 << RTL8373_RMK_INTPRI2IPRI_CTRL_IPRI7_OFFSET) + #define RTL8373_RMK_INTPRI2IPRI_CTRL_IPRI6_OFFSET (24) + #define RTL8373_RMK_INTPRI2IPRI_CTRL_IPRI6_MASK (0x7 << RTL8373_RMK_INTPRI2IPRI_CTRL_IPRI6_OFFSET) + #define RTL8373_RMK_INTPRI2IPRI_CTRL_IPRI5_OFFSET (20) + #define RTL8373_RMK_INTPRI2IPRI_CTRL_IPRI5_MASK (0x7 << RTL8373_RMK_INTPRI2IPRI_CTRL_IPRI5_OFFSET) + #define RTL8373_RMK_INTPRI2IPRI_CTRL_IPRI4_OFFSET (16) + #define RTL8373_RMK_INTPRI2IPRI_CTRL_IPRI4_MASK (0x7 << RTL8373_RMK_INTPRI2IPRI_CTRL_IPRI4_OFFSET) + #define RTL8373_RMK_INTPRI2IPRI_CTRL_IPRI3_OFFSET (12) + #define RTL8373_RMK_INTPRI2IPRI_CTRL_IPRI3_MASK (0x7 << RTL8373_RMK_INTPRI2IPRI_CTRL_IPRI3_OFFSET) + #define RTL8373_RMK_INTPRI2IPRI_CTRL_IPRI2_OFFSET (8) + #define RTL8373_RMK_INTPRI2IPRI_CTRL_IPRI2_MASK (0x7 << RTL8373_RMK_INTPRI2IPRI_CTRL_IPRI2_OFFSET) + #define RTL8373_RMK_INTPRI2IPRI_CTRL_IPRI1_OFFSET (4) + #define RTL8373_RMK_INTPRI2IPRI_CTRL_IPRI1_MASK (0x7 << RTL8373_RMK_INTPRI2IPRI_CTRL_IPRI1_OFFSET) + #define RTL8373_RMK_INTPRI2IPRI_CTRL_IPRI0_OFFSET (0) + #define RTL8373_RMK_INTPRI2IPRI_CTRL_IPRI0_MASK (0x7 << RTL8373_RMK_INTPRI2IPRI_CTRL_IPRI0_OFFSET) + +#define RTL8373_RMK_INTPRI2DSCP_CTRL_ADDR(index) (0x6780 + (((index / 5) << 2))) /* index: 0-7 */ + #define RTL8373_RMK_INTPRI2DSCP_CTRL_DSCP_OFFSET(index) ((index % 0x5) * 6) + #define RTL8373_RMK_INTPRI2DSCP_CTRL_DSCP_MASK(index) (0x3F << RTL8373_RMK_INTPRI2DSCP_CTRL_DSCP_OFFSET(index)) + +#define RTL8373_RMK_DSCP2DSCP_CTRL_ADDR(index) (0x6788 + (((index / 5) << 2))) /* index: 0-63 */ + #define RTL8373_RMK_DSCP2DSCP_CTRL_DSCP_OFFSET(index) ((index % 0x5) * 6) + #define RTL8373_RMK_DSCP2DSCP_CTRL_DSCP_MASK(index) (0x3F << RTL8373_RMK_DSCP2DSCP_CTRL_DSCP_OFFSET(index)) + +/* + * Feature: 802.1X + */ +#define RTL8373_DOT1X_PORT_EN_ADDR(port) (0x5574 + (((port / 10) << 2))) /* port: 0-9 */ + #define RTL8373_DOT1X_PORT_EN_PORT_EN_OFFSET(port) (port % 0xA) + #define RTL8373_DOT1X_PORT_EN_PORT_EN_MASK(port) (0x1 << RTL8373_DOT1X_PORT_EN_PORT_EN_OFFSET(port)) + +#define RTL8373_DOT1X_MAC_EN_ADDR(port) (0x5578 + (((port / 10) << 2))) /* port: 0-9 */ + #define RTL8373_DOT1X_MAC_EN_MAC_EN_OFFSET(port) (port % 0xA) + #define RTL8373_DOT1X_MAC_EN_MAC_EN_MASK(port) (0x1 << RTL8373_DOT1X_MAC_EN_MAC_EN_OFFSET(port)) + +#define RTL8373_DOT1X_PORT_AUTH_ADDR(port) (0x557C + (((port / 10) << 2))) /* port: 0-9 */ + #define RTL8373_DOT1X_PORT_AUTH_PORT_AUTH_OFFSET(port) (port % 0xA) + #define RTL8373_DOT1X_PORT_AUTH_PORT_AUTH_MASK(port) (0x1 << RTL8373_DOT1X_PORT_AUTH_PORT_AUTH_OFFSET(port)) + +#define RTL8373_DOT1X_PORT_DIR_ADDR(port) (0x5580 + (((port / 10) << 2))) /* port: 0-9 */ + #define RTL8373_DOT1X_PORT_DIR_PORT_DIR_OFFSET(port) (port % 0xA) + #define RTL8373_DOT1X_PORT_DIR_PORT_DIR_MASK(port) (0x1 << RTL8373_DOT1X_PORT_DIR_PORT_DIR_OFFSET(port)) + +#define RTL8373_DOT1X_TRAP_PRIORITY_ADDR (0x51D4) + #define RTL8373_DOT1X_TRAP_PRIORITY_TRAP_PRI_OFFSET (0) + #define RTL8373_DOT1X_TRAP_PRIORITY_TRAP_PRI_MASK (0x7 << RTL8373_DOT1X_TRAP_PRIORITY_TRAP_PRI_OFFSET) + +#define RTL8373_DOT1X_UNAUTH_ACT_ADDR(port) (0x5584 + (((port / 10) << 2))) /* port: 0-9 */ + #define RTL8373_DOT1X_UNAUTH_ACT_PORT_ACT_OFFSET(port) ((port % 0xA) << 1) + #define RTL8373_DOT1X_UNAUTH_ACT_PORT_ACT_MASK(port) (0x3 << RTL8373_DOT1X_UNAUTH_ACT_PORT_ACT_OFFSET(port)) + +#define RTL8373_DOT1X_TRAP_CPU_SEL_ADDR (0x51D8) + #define RTL8373_DOT1X_TRAP_CPU_SEL_TRAP_CPU_SEL_OFFSET (0) + #define RTL8373_DOT1X_TRAP_CPU_SEL_TRAP_CPU_SEL_MASK (0x3 << RTL8373_DOT1X_TRAP_CPU_SEL_TRAP_CPU_SEL_OFFSET) + +#define RTL8373_DOT1X_CFG_ADDR (0x5588) + #define RTL8373_DOT1X_CFG_GUSET_OP_OFFSET (13) + #define RTL8373_DOT1X_CFG_GUSET_OP_MASK (0x1 << RTL8373_DOT1X_CFG_GUSET_OP_OFFSET) + #define RTL8373_DOT1X_CFG_MAC_DIR_OFFSET (12) + #define RTL8373_DOT1X_CFG_MAC_DIR_MASK (0x1 << RTL8373_DOT1X_CFG_MAC_DIR_OFFSET) + #define RTL8373_DOT1X_CFG_GUEST_VID_OFFSET (0) + #define RTL8373_DOT1X_CFG_GUEST_VID_MASK (0xFFF << RTL8373_DOT1X_CFG_GUEST_VID_OFFSET) + +/* + * Feature: Attack Prevention + */ +#define RTL8373_ATK_PRVNT_CTRL_ADDR (0x51DC) + #define RTL8373_ATK_PRVNT_CTRL_ICMPFRAGMENT_OFFSET (10) + #define RTL8373_ATK_PRVNT_CTRL_ICMPFRAGMENT_MASK (0x1 << RTL8373_ATK_PRVNT_CTRL_ICMPFRAGMENT_OFFSET) + #define RTL8373_ATK_PRVNT_CTRL_TCPFRAGERR_OFFSET (9) + #define RTL8373_ATK_PRVNT_CTRL_TCPFRAGERR_MASK (0x1 << RTL8373_ATK_PRVNT_CTRL_TCPFRAGERR_OFFSET) + #define RTL8373_ATK_PRVNT_CTRL_TCPSHORTHDR_OFFSET (8) + #define RTL8373_ATK_PRVNT_CTRL_TCPSHORTHDR_MASK (0x1 << RTL8373_ATK_PRVNT_CTRL_TCPSHORTHDR_OFFSET) + #define RTL8373_ATK_PRVNT_CTRL_SYN1024_OFFSET (7) + #define RTL8373_ATK_PRVNT_CTRL_SYN1024_MASK (0x1 << RTL8373_ATK_PRVNT_CTRL_SYN1024_OFFSET) + #define RTL8373_ATK_PRVNT_CTRL_NULLSCAN_OFFSET (6) + #define RTL8373_ATK_PRVNT_CTRL_NULLSCAN_MASK (0x1 << RTL8373_ATK_PRVNT_CTRL_NULLSCAN_OFFSET) + #define RTL8373_ATK_PRVNT_CTRL_XMASCAN_OFFSET (5) + #define RTL8373_ATK_PRVNT_CTRL_XMASCAN_MASK (0x1 << RTL8373_ATK_PRVNT_CTRL_XMASCAN_OFFSET) + #define RTL8373_ATK_PRVNT_CTRL_SYNFINSCAN_OFFSET (4) + #define RTL8373_ATK_PRVNT_CTRL_SYNFINSCAN_MASK (0x1 << RTL8373_ATK_PRVNT_CTRL_SYNFINSCAN_OFFSET) + #define RTL8373_ATK_PRVNT_CTRL_BLAT_OFFSET (3) + #define RTL8373_ATK_PRVNT_CTRL_BLAT_MASK (0x1 << RTL8373_ATK_PRVNT_CTRL_BLAT_OFFSET) + #define RTL8373_ATK_PRVNT_CTRL_LAND_V6_OFFSET (2) + #define RTL8373_ATK_PRVNT_CTRL_LAND_V6_MASK (0x1 << RTL8373_ATK_PRVNT_CTRL_LAND_V6_OFFSET) + #define RTL8373_ATK_PRVNT_CTRL_LAND_V4_OFFSET (1) + #define RTL8373_ATK_PRVNT_CTRL_LAND_V4_MASK (0x1 << RTL8373_ATK_PRVNT_CTRL_LAND_V4_OFFSET) + #define RTL8373_ATK_PRVNT_CTRL_DAEQSA_OFFSET (0) + #define RTL8373_ATK_PRVNT_CTRL_DAEQSA_MASK (0x1 << RTL8373_ATK_PRVNT_CTRL_DAEQSA_OFFSET) + +#define RTL8373_MIN_TCPHDR_LEN_ADDR (0x51E0) + #define RTL8373_MIN_TCPHDR_LEN_LEN_OFFSET (0) + #define RTL8373_MIN_TCPHDR_LEN_LEN_MASK (0x1F << RTL8373_MIN_TCPHDR_LEN_LEN_OFFSET) + +/* + * Feature: WOL + */ +#define RTL8373_WOL_CTRL_ADDR (0x6F4C) + #define RTL8373_WOL_CTRL_WOL_EN_OFFSET (10) + #define RTL8373_WOL_CTRL_WOL_EN_MASK (0x1 << RTL8373_WOL_CTRL_WOL_EN_OFFSET) + #define RTL8373_WOL_CTRL_WOL_PMSK_OFFSET (0) + #define RTL8373_WOL_CTRL_WOL_PMSK_MASK (0x3FF << RTL8373_WOL_CTRL_WOL_PMSK_OFFSET) + +#define RTL8373_WOL_MAC0_ADDR (0x6F50) + #define RTL8373_WOL_MAC0_WOL_MAC_0_31_OFFSET (0) + #define RTL8373_WOL_MAC0_WOL_MAC_0_31_MASK (0xFFFFFFFF << RTL8373_WOL_MAC0_WOL_MAC_0_31_OFFSET) + +#define RTL8373_WOL_MAC1_ADDR (0x6F54) + #define RTL8373_WOL_MAC1_WOL_MAC_32_47_OFFSET (0) + #define RTL8373_WOL_MAC1_WOL_MAC_32_47_MASK (0xFFFF << RTL8373_WOL_MAC1_WOL_MAC_32_47_OFFSET) + +#define RTL8373_PHY_WOL_CTRL_ADDR (0xBD4) + #define RTL8373_PHY_WOL_CTRL_PHY_WOL_EN_OFFSET (0) + #define RTL8373_PHY_WOL_CTRL_PHY_WOL_EN_MASK (0x1 << RTL8373_PHY_WOL_CTRL_PHY_WOL_EN_OFFSET) + +#define RTL8373_PHY_WOL_MAC0_ADDR (0xBD8) + #define RTL8373_PHY_WOL_MAC0_PHY_WOL_MAC_0_31_OFFSET (0) + #define RTL8373_PHY_WOL_MAC0_PHY_WOL_MAC_0_31_MASK (0xFFFFFFFF << RTL8373_PHY_WOL_MAC0_PHY_WOL_MAC_0_31_OFFSET) + +#define RTL8373_PHY_WOL_MAC1_ADDR (0xBDC) + #define RTL8373_PHY_WOL_MAC1_PHY_WOL_MAC_32_47_OFFSET (0) + #define RTL8373_PHY_WOL_MAC1_PHY_WOL_MAC_32_47_MASK (0xFFFF << RTL8373_PHY_WOL_MAC1_PHY_WOL_MAC_32_47_OFFSET) + +/* + * Feature: Parser + */ +#define RTL8373_PARSER_FIELD_SELTOR_CTRL_ADDR(index) (0x6F58 + (((index) << 2))) /* index: 0-15 */ + #define RTL8373_PARSER_FIELD_SELTOR_CTRL_OFFSET_OFFSET (3) + #define RTL8373_PARSER_FIELD_SELTOR_CTRL_OFFSET_MASK (0xFF << RTL8373_PARSER_FIELD_SELTOR_CTRL_OFFSET_OFFSET) + #define RTL8373_PARSER_FIELD_SELTOR_CTRL_FMT_OFFSET (0) + #define RTL8373_PARSER_FIELD_SELTOR_CTRL_FMT_MASK (0x7 << RTL8373_PARSER_FIELD_SELTOR_CTRL_FMT_OFFSET) + +#define RTL8373_PARSER_CTRL_ADDR (0x6F98) + #define RTL8373_PARSER_CTRL_RFC1042_OUI_IGNORE_OFFSET (0) + #define RTL8373_PARSER_CTRL_RFC1042_OUI_IGNORE_MASK (0x1 << RTL8373_PARSER_CTRL_RFC1042_OUI_IGNORE_OFFSET) + +#define RTL8373_PARSER_DROP_REASON_ADDR(port) (0x1264 + (((port) << 8))) /* port: 0-9 */ + #define RTL8373_PARSER_DROP_REASON_REASON_OFFSET (0) + #define RTL8373_PARSER_DROP_REASON_REASON_MASK (0xF << RTL8373_PARSER_DROP_REASON_REASON_OFFSET) + +/* + * Feature: Parser HSB + */ +#define RTL8373_HSB_DATA0_ADDR (0x6F9C) + #define RTL8373_HSB_DATA0_DMAC17_0_OFFSET (14) + #define RTL8373_HSB_DATA0_DMAC17_0_MASK (0x3FFFF << RTL8373_HSB_DATA0_DMAC17_0_OFFSET) + #define RTL8373_HSB_DATA0_PKE_LEN_OFFSET (0) + #define RTL8373_HSB_DATA0_PKE_LEN_MASK (0x3FFF << RTL8373_HSB_DATA0_PKE_LEN_OFFSET) + +#define RTL8373_HSB_DATA1_ADDR (0x6FA0) + #define RTL8373_HSB_DATA1_SMAC1_0_OFFSET (30) + #define RTL8373_HSB_DATA1_SMAC1_0_MASK (0x3 << RTL8373_HSB_DATA1_SMAC1_0_OFFSET) + #define RTL8373_HSB_DATA1_DMAC47_18_OFFSET (0) + #define RTL8373_HSB_DATA1_DMAC47_18_MASK (0x3FFFFFFF << RTL8373_HSB_DATA1_DMAC47_18_OFFSET) + +#define RTL8373_HSB_DATA2_ADDR (0x6FA4) + #define RTL8373_HSB_DATA2_SMAC33_2_OFFSET (0) + #define RTL8373_HSB_DATA2_SMAC33_2_MASK (0xFFFFFFFF << RTL8373_HSB_DATA2_SMAC33_2_OFFSET) + +#define RTL8373_HSB_DATA3_ADDR (0x6FA8) + #define RTL8373_HSB_DATA3_CPUTAG16_0_OFFSET (15) + #define RTL8373_HSB_DATA3_CPUTAG16_0_MASK (0x1FFFF << RTL8373_HSB_DATA3_CPUTAG16_0_OFFSET) + #define RTL8373_HSB_DATA3_CPUTAG_IF_OFFSET (14) + #define RTL8373_HSB_DATA3_CPUTAG_IF_MASK (0x1 << RTL8373_HSB_DATA3_CPUTAG_IF_OFFSET) + #define RTL8373_HSB_DATA3_SMAC47_34_OFFSET (0) + #define RTL8373_HSB_DATA3_SMAC47_34_MASK (0x3FFF << RTL8373_HSB_DATA3_SMAC47_34_OFFSET) + +#define RTL8373_HSB_DATA4_ADDR (0x6FAC) + #define RTL8373_HSB_DATA4_STAG_OFFSET (16) + #define RTL8373_HSB_DATA4_STAG_MASK (0xFFFF << RTL8373_HSB_DATA4_STAG_OFFSET) + #define RTL8373_HSB_DATA4_STAG_IF_OFFSET (15) + #define RTL8373_HSB_DATA4_STAG_IF_MASK (0x1 << RTL8373_HSB_DATA4_STAG_IF_OFFSET) + #define RTL8373_HSB_DATA4_CPUTAG31_17_OFFSET (0) + #define RTL8373_HSB_DATA4_CPUTAG31_17_MASK (0x7FFF << RTL8373_HSB_DATA4_CPUTAG31_17_OFFSET) + +#define RTL8373_HSB_DATA5_ADDR (0x6FB0) + #define RTL8373_HSB_DATA5_ETYPE13_0_OFFSET (18) + #define RTL8373_HSB_DATA5_ETYPE13_0_MASK (0x3FFF << RTL8373_HSB_DATA5_ETYPE13_0_OFFSET) + #define RTL8373_HSB_DATA5_RTAG_IF_OFFSET (17) + #define RTL8373_HSB_DATA5_RTAG_IF_MASK (0x1 << RTL8373_HSB_DATA5_RTAG_IF_OFFSET) + #define RTL8373_HSB_DATA5_CTAG_OFFSET (1) + #define RTL8373_HSB_DATA5_CTAG_MASK (0xFFFF << RTL8373_HSB_DATA5_CTAG_OFFSET) + #define RTL8373_HSB_DATA5_CTAG_IF_OFFSET (0) + #define RTL8373_HSB_DATA5_CTAG_IF_MASK (0x1 << RTL8373_HSB_DATA5_CTAG_IF_OFFSET) + +#define RTL8373_HSB_DATA6_ADDR (0x6FB4) + #define RTL8373_HSB_DATA6_DIP16_0_OFFSET (15) + #define RTL8373_HSB_DATA6_DIP16_0_MASK (0x1FFFF << RTL8373_HSB_DATA6_DIP16_0_OFFSET) + #define RTL8373_HSB_DATA6_IGMP_OFFSET (14) + #define RTL8373_HSB_DATA6_IGMP_MASK (0x1 << RTL8373_HSB_DATA6_IGMP_OFFSET) + #define RTL8373_HSB_DATA6_ICMP_OFFSET (13) + #define RTL8373_HSB_DATA6_ICMP_MASK (0x1 << RTL8373_HSB_DATA6_ICMP_OFFSET) + #define RTL8373_HSB_DATA6_UDP_OFFSET (12) + #define RTL8373_HSB_DATA6_UDP_MASK (0x1 << RTL8373_HSB_DATA6_UDP_OFFSET) + #define RTL8373_HSB_DATA6_TCP_OFFSET (11) + #define RTL8373_HSB_DATA6_TCP_MASK (0x1 << RTL8373_HSB_DATA6_TCP_OFFSET) + #define RTL8373_HSB_DATA6_IPTYPE_OFFSET (9) + #define RTL8373_HSB_DATA6_IPTYPE_MASK (0x3 << RTL8373_HSB_DATA6_IPTYPE_OFFSET) + #define RTL8373_HSB_DATA6_ARP_OFFSET (8) + #define RTL8373_HSB_DATA6_ARP_MASK (0x1 << RTL8373_HSB_DATA6_ARP_OFFSET) + #define RTL8373_HSB_DATA6_OAM_OFFSET (7) + #define RTL8373_HSB_DATA6_OAM_MASK (0x1 << RTL8373_HSB_DATA6_OAM_OFFSET) + #define RTL8373_HSB_DATA6_RLPP_OFFSET (6) + #define RTL8373_HSB_DATA6_RLPP_MASK (0x1 << RTL8373_HSB_DATA6_RLPP_OFFSET) + #define RTL8373_HSB_DATA6_RLDP_OFFSET (5) + #define RTL8373_HSB_DATA6_RLDP_MASK (0x1 << RTL8373_HSB_DATA6_RLDP_OFFSET) + #define RTL8373_HSB_DATA6_RRCP_OFFSET (4) + #define RTL8373_HSB_DATA6_RRCP_MASK (0x1 << RTL8373_HSB_DATA6_RRCP_OFFSET) + #define RTL8373_HSB_DATA6_PPPOE_OFFSET (3) + #define RTL8373_HSB_DATA6_PPPOE_MASK (0x1 << RTL8373_HSB_DATA6_PPPOE_OFFSET) + #define RTL8373_HSB_DATA6_SNAP_OFFSET (2) + #define RTL8373_HSB_DATA6_SNAP_MASK (0x1 << RTL8373_HSB_DATA6_SNAP_OFFSET) + #define RTL8373_HSB_DATA6_ETYPE15_14_OFFSET (0) + #define RTL8373_HSB_DATA6_ETYPE15_14_MASK (0x3 << RTL8373_HSB_DATA6_ETYPE15_14_OFFSET) + +#define RTL8373_HSB_DATA7_ADDR (0x6FB8) + #define RTL8373_HSB_DATA7_SIP16_0_OFFSET (15) + #define RTL8373_HSB_DATA7_SIP16_0_MASK (0x1FFFF << RTL8373_HSB_DATA7_SIP16_0_OFFSET) + #define RTL8373_HSB_DATA7_DIP31_17_OFFSET (0) + #define RTL8373_HSB_DATA7_DIP31_17_MASK (0x7FFF << RTL8373_HSB_DATA7_DIP31_17_OFFSET) + +#define RTL8373_HSB_DATA8_ADDR (0x6FBC) + #define RTL8373_HSB_DATA8_L4SPORT0_OFFSET (31) + #define RTL8373_HSB_DATA8_L4SPORT0_MASK (0x1 << RTL8373_HSB_DATA8_L4SPORT0_OFFSET) + #define RTL8373_HSB_DATA8_L4DPORT_OFFSET (15) + #define RTL8373_HSB_DATA8_L4DPORT_MASK (0xFFFF << RTL8373_HSB_DATA8_L4DPORT_OFFSET) + #define RTL8373_HSB_DATA8_SIP31_17_OFFSET (0) + #define RTL8373_HSB_DATA8_SIP31_17_MASK (0x7FFF << RTL8373_HSB_DATA8_SIP31_17_OFFSET) + +#define RTL8373_HSB_DATA9_ADDR (0x6FC0) + #define RTL8373_HSB_DATA9_UDV0_OFFSET (31) + #define RTL8373_HSB_DATA9_UDV0_MASK (0x1 << RTL8373_HSB_DATA9_UDV0_OFFSET) + #define RTL8373_HSB_DATA9_TOS_OFFSET (15) + #define RTL8373_HSB_DATA9_TOS_MASK (0xFFFF << RTL8373_HSB_DATA9_TOS_OFFSET) + #define RTL8373_HSB_DATA9_L4SPORT15_1_OFFSET (0) + #define RTL8373_HSB_DATA9_L4SPORT15_1_MASK (0x7FFF << RTL8373_HSB_DATA9_L4SPORT15_1_OFFSET) + +#define RTL8373_HSB_DATA10_ADDR (0x6FC4) + #define RTL8373_HSB_DATA10_UDF1_0_0_OFFSET (31) + #define RTL8373_HSB_DATA10_UDF1_0_0_MASK (0x1 << RTL8373_HSB_DATA10_UDF1_0_0_OFFSET) + #define RTL8373_HSB_DATA10_UDF0_OFFSET (15) + #define RTL8373_HSB_DATA10_UDF0_MASK (0xFFFF << RTL8373_HSB_DATA10_UDF0_OFFSET) + #define RTL8373_HSB_DATA10_UDV15_OFFSET (14) + #define RTL8373_HSB_DATA10_UDV15_MASK (0x1 << RTL8373_HSB_DATA10_UDV15_OFFSET) + #define RTL8373_HSB_DATA10_UDV14_OFFSET (13) + #define RTL8373_HSB_DATA10_UDV14_MASK (0x1 << RTL8373_HSB_DATA10_UDV14_OFFSET) + #define RTL8373_HSB_DATA10_UDV13_OFFSET (12) + #define RTL8373_HSB_DATA10_UDV13_MASK (0x1 << RTL8373_HSB_DATA10_UDV13_OFFSET) + #define RTL8373_HSB_DATA10_UDV12_OFFSET (11) + #define RTL8373_HSB_DATA10_UDV12_MASK (0x1 << RTL8373_HSB_DATA10_UDV12_OFFSET) + #define RTL8373_HSB_DATA10_UDV11_OFFSET (10) + #define RTL8373_HSB_DATA10_UDV11_MASK (0x1 << RTL8373_HSB_DATA10_UDV11_OFFSET) + #define RTL8373_HSB_DATA10_UDV10_OFFSET (9) + #define RTL8373_HSB_DATA10_UDV10_MASK (0x1 << RTL8373_HSB_DATA10_UDV10_OFFSET) + #define RTL8373_HSB_DATA10_UDV9_OFFSET (8) + #define RTL8373_HSB_DATA10_UDV9_MASK (0x1 << RTL8373_HSB_DATA10_UDV9_OFFSET) + #define RTL8373_HSB_DATA10_UDV8_OFFSET (7) + #define RTL8373_HSB_DATA10_UDV8_MASK (0x1 << RTL8373_HSB_DATA10_UDV8_OFFSET) + #define RTL8373_HSB_DATA10_UDV7_OFFSET (6) + #define RTL8373_HSB_DATA10_UDV7_MASK (0x1 << RTL8373_HSB_DATA10_UDV7_OFFSET) + #define RTL8373_HSB_DATA10_UDV6_OFFSET (5) + #define RTL8373_HSB_DATA10_UDV6_MASK (0x1 << RTL8373_HSB_DATA10_UDV6_OFFSET) + #define RTL8373_HSB_DATA10_UDV5_OFFSET (4) + #define RTL8373_HSB_DATA10_UDV5_MASK (0x1 << RTL8373_HSB_DATA10_UDV5_OFFSET) + #define RTL8373_HSB_DATA10_UDV4_OFFSET (3) + #define RTL8373_HSB_DATA10_UDV4_MASK (0x1 << RTL8373_HSB_DATA10_UDV4_OFFSET) + #define RTL8373_HSB_DATA10_UDV3_OFFSET (2) + #define RTL8373_HSB_DATA10_UDV3_MASK (0x1 << RTL8373_HSB_DATA10_UDV3_OFFSET) + #define RTL8373_HSB_DATA10_UDV2_OFFSET (1) + #define RTL8373_HSB_DATA10_UDV2_MASK (0x1 << RTL8373_HSB_DATA10_UDV2_OFFSET) + #define RTL8373_HSB_DATA10_UDV1_OFFSET (0) + #define RTL8373_HSB_DATA10_UDV1_MASK (0x1 << RTL8373_HSB_DATA10_UDV1_OFFSET) + +#define RTL8373_HSB_DATA11_ADDR (0x6FC8) + #define RTL8373_HSB_DATA11_UDF3_0_0_OFFSET (31) + #define RTL8373_HSB_DATA11_UDF3_0_0_MASK (0x1 << RTL8373_HSB_DATA11_UDF3_0_0_OFFSET) + #define RTL8373_HSB_DATA11_UDF2_OFFSET (15) + #define RTL8373_HSB_DATA11_UDF2_MASK (0xFFFF << RTL8373_HSB_DATA11_UDF2_OFFSET) + #define RTL8373_HSB_DATA11_UDF1_15_1_OFFSET (0) + #define RTL8373_HSB_DATA11_UDF1_15_1_MASK (0x7FFF << RTL8373_HSB_DATA11_UDF1_15_1_OFFSET) + +#define RTL8373_HSB_DATA12_ADDR (0x6FCC) + #define RTL8373_HSB_DATA12_UDF5_0_0_OFFSET (31) + #define RTL8373_HSB_DATA12_UDF5_0_0_MASK (0x1 << RTL8373_HSB_DATA12_UDF5_0_0_OFFSET) + #define RTL8373_HSB_DATA12_UDF4_OFFSET (15) + #define RTL8373_HSB_DATA12_UDF4_MASK (0xFFFF << RTL8373_HSB_DATA12_UDF4_OFFSET) + #define RTL8373_HSB_DATA12_UDF3_15_1_OFFSET (0) + #define RTL8373_HSB_DATA12_UDF3_15_1_MASK (0x7FFF << RTL8373_HSB_DATA12_UDF3_15_1_OFFSET) + +#define RTL8373_HSB_DATA13_ADDR (0x6FD0) + #define RTL8373_HSB_DATA13_UDF7_0_0_OFFSET (31) + #define RTL8373_HSB_DATA13_UDF7_0_0_MASK (0x1 << RTL8373_HSB_DATA13_UDF7_0_0_OFFSET) + #define RTL8373_HSB_DATA13_UDF6_OFFSET (15) + #define RTL8373_HSB_DATA13_UDF6_MASK (0xFFFF << RTL8373_HSB_DATA13_UDF6_OFFSET) + #define RTL8373_HSB_DATA13_UDF5_15_1_OFFSET (0) + #define RTL8373_HSB_DATA13_UDF5_15_1_MASK (0x7FFF << RTL8373_HSB_DATA13_UDF5_15_1_OFFSET) + +#define RTL8373_HSB_DATA14_ADDR (0x6FD4) + #define RTL8373_HSB_DATA14_UDF9_0_0_OFFSET (31) + #define RTL8373_HSB_DATA14_UDF9_0_0_MASK (0x1 << RTL8373_HSB_DATA14_UDF9_0_0_OFFSET) + #define RTL8373_HSB_DATA14_UDF8_OFFSET (15) + #define RTL8373_HSB_DATA14_UDF8_MASK (0xFFFF << RTL8373_HSB_DATA14_UDF8_OFFSET) + #define RTL8373_HSB_DATA14_UDF7_15_1_OFFSET (0) + #define RTL8373_HSB_DATA14_UDF7_15_1_MASK (0x7FFF << RTL8373_HSB_DATA14_UDF7_15_1_OFFSET) + +#define RTL8373_HSB_DATA15_ADDR (0x6FD8) + #define RTL8373_HSB_DATA15_UDF11_0_0_OFFSET (31) + #define RTL8373_HSB_DATA15_UDF11_0_0_MASK (0x1 << RTL8373_HSB_DATA15_UDF11_0_0_OFFSET) + #define RTL8373_HSB_DATA15_UDF10_OFFSET (15) + #define RTL8373_HSB_DATA15_UDF10_MASK (0xFFFF << RTL8373_HSB_DATA15_UDF10_OFFSET) + #define RTL8373_HSB_DATA15_UDF9_15_1_OFFSET (0) + #define RTL8373_HSB_DATA15_UDF9_15_1_MASK (0x7FFF << RTL8373_HSB_DATA15_UDF9_15_1_OFFSET) + +#define RTL8373_HSB_DATA16_ADDR (0x6FDC) + #define RTL8373_HSB_DATA16_UDF13_0_0_OFFSET (31) + #define RTL8373_HSB_DATA16_UDF13_0_0_MASK (0x1 << RTL8373_HSB_DATA16_UDF13_0_0_OFFSET) + #define RTL8373_HSB_DATA16_UDF12_OFFSET (15) + #define RTL8373_HSB_DATA16_UDF12_MASK (0xFFFF << RTL8373_HSB_DATA16_UDF12_OFFSET) + #define RTL8373_HSB_DATA16_UDF11_15_1_OFFSET (0) + #define RTL8373_HSB_DATA16_UDF11_15_1_MASK (0x7FFF << RTL8373_HSB_DATA16_UDF11_15_1_OFFSET) + +#define RTL8373_HSB_DATA17_ADDR (0x6FE0) + #define RTL8373_HSB_DATA17_UDF15_0_0_OFFSET (31) + #define RTL8373_HSB_DATA17_UDF15_0_0_MASK (0x1 << RTL8373_HSB_DATA17_UDF15_0_0_OFFSET) + #define RTL8373_HSB_DATA17_UDF14_OFFSET (15) + #define RTL8373_HSB_DATA17_UDF14_MASK (0xFFFF << RTL8373_HSB_DATA17_UDF14_OFFSET) + #define RTL8373_HSB_DATA17_UDF13_15_1_OFFSET (0) + #define RTL8373_HSB_DATA17_UDF13_15_1_MASK (0x7FFF << RTL8373_HSB_DATA17_UDF13_15_1_OFFSET) + +#define RTL8373_HSB_DATA18_ADDR (0x6FE4) + #define RTL8373_HSB_DATA18_BDSC6_0_OFFSET (25) + #define RTL8373_HSB_DATA18_BDSC6_0_MASK (0x7F << RTL8373_HSB_DATA18_BDSC6_0_OFFSET) + #define RTL8373_HSB_DATA18_L3ERR_OFFSET (24) + #define RTL8373_HSB_DATA18_L3ERR_MASK (0x1 << RTL8373_HSB_DATA18_L3ERR_OFFSET) + #define RTL8373_HSB_DATA18_ERRPKT_OFFSET (23) + #define RTL8373_HSB_DATA18_ERRPKT_MASK (0x1 << RTL8373_HSB_DATA18_ERRPKT_OFFSET) + #define RTL8373_HSB_DATA18_INGR_ERR_OFFSET (22) + #define RTL8373_HSB_DATA18_INGR_ERR_MASK (0x1 << RTL8373_HSB_DATA18_INGR_ERR_OFFSET) + #define RTL8373_HSB_DATA18_UDPPTP_OFFSET (21) + #define RTL8373_HSB_DATA18_UDPPTP_MASK (0x1 << RTL8373_HSB_DATA18_UDPPTP_OFFSET) + #define RTL8373_HSB_DATA18_L2PTP_OFFSET (20) + #define RTL8373_HSB_DATA18_L2PTP_MASK (0x1 << RTL8373_HSB_DATA18_L2PTP_OFFSET) + #define RTL8373_HSB_DATA18_WOL_OFFSET (19) + #define RTL8373_HSB_DATA18_WOL_MASK (0x1 << RTL8373_HSB_DATA18_WOL_OFFSET) + #define RTL8373_HSB_DATA18_RXPORT_OFFSET (15) + #define RTL8373_HSB_DATA18_RXPORT_MASK (0xF << RTL8373_HSB_DATA18_RXPORT_OFFSET) + #define RTL8373_HSB_DATA18_UDF15_15_1_OFFSET (0) + #define RTL8373_HSB_DATA18_UDF15_15_1_MASK (0x7FFF << RTL8373_HSB_DATA18_UDF15_15_1_OFFSET) + +#define RTL8373_HSB_DATA19_ADDR (0x6FE8) + #define RTL8373_HSB_DATA19_EDSC_OFFSET (5) + #define RTL8373_HSB_DATA19_EDSC_MASK (0xFFF << RTL8373_HSB_DATA19_EDSC_OFFSET) + #define RTL8373_HSB_DATA19_BDSC11_7_OFFSET (0) + #define RTL8373_HSB_DATA19_BDSC11_7_MASK (0x1F << RTL8373_HSB_DATA19_BDSC11_7_OFFSET) + +#define RTL8373_HSB_CTRL_ADDR (0x6FEC) + #define RTL8373_HSB_CTRL_READHSB_OFFSET (0) + #define RTL8373_HSB_CTRL_READHSB_MASK (0x1 << RTL8373_HSB_CTRL_READHSB_OFFSET) + +/* + * Feature: RLDP & RLPP + */ +#define RTL8373_RLDP_RLPP_CTRL_ADDR (0x106C) + #define RTL8373_RLDP_RLPP_CTRL_FRC_LOOP_MASK_OFFSET (7) + #define RTL8373_RLDP_RLPP_CTRL_FRC_LOOP_MASK_MASK (0x3FF << RTL8373_RLDP_RLPP_CTRL_FRC_LOOP_MASK_OFFSET) + #define RTL8373_RLDP_RLPP_CTRL_RLPP_TRAP_OFFSET (6) + #define RTL8373_RLDP_RLPP_CTRL_RLPP_TRAP_MASK (0x1 << RTL8373_RLDP_RLPP_CTRL_RLPP_TRAP_OFFSET) + #define RTL8373_RLDP_RLPP_CTRL_RLDP_MODE_OFFSET (5) + #define RTL8373_RLDP_RLPP_CTRL_RLDP_MODE_MASK (0x1 << RTL8373_RLDP_RLPP_CTRL_RLDP_MODE_OFFSET) + #define RTL8373_RLDP_RLPP_CTRL_INDICATOR_OFFSET (4) + #define RTL8373_RLDP_RLPP_CTRL_INDICATOR_MASK (0x1 << RTL8373_RLDP_RLPP_CTRL_INDICATOR_OFFSET) + #define RTL8373_RLDP_RLPP_CTRL_GEN_RANDOM_OFFSET (3) + #define RTL8373_RLDP_RLPP_CTRL_GEN_RANDOM_MASK (0x1 << RTL8373_RLDP_RLPP_CTRL_GEN_RANDOM_OFFSET) + #define RTL8373_RLDP_RLPP_CTRL_COMP_ID_OFFSET (2) + #define RTL8373_RLDP_RLPP_CTRL_COMP_ID_MASK (0x1 << RTL8373_RLDP_RLPP_CTRL_COMP_ID_OFFSET) + #define RTL8373_RLDP_RLPP_CTRL_RLDP_ICPU_EN_OFFSET (1) + #define RTL8373_RLDP_RLPP_CTRL_RLDP_ICPU_EN_MASK (0x1 << RTL8373_RLDP_RLPP_CTRL_RLDP_ICPU_EN_OFFSET) + #define RTL8373_RLDP_RLPP_CTRL_RLDP_EN_OFFSET (0) + #define RTL8373_RLDP_RLPP_CTRL_RLDP_EN_MASK (0x1 << RTL8373_RLDP_RLPP_CTRL_RLDP_EN_OFFSET) + +#define RTL8373_RETRY_CTRL_ADDR (0x1070) + #define RTL8373_RETRY_CTRL_RETRY_LOOP_OFFSET (8) + #define RTL8373_RETRY_CTRL_RETRY_LOOP_MASK (0xFF << RTL8373_RETRY_CTRL_RETRY_LOOP_OFFSET) + #define RTL8373_RETRY_CTRL_RETRY_CHK_OFFSET (0) + #define RTL8373_RETRY_CTRL_RETRY_CHK_MASK (0xFF << RTL8373_RETRY_CTRL_RETRY_CHK_OFFSET) + +#define RTL8373_PERIOD_CTRL_ADDR (0x1074) + #define RTL8373_PERIOD_CTRL_PERIOD_LOOP_OFFSET (16) + #define RTL8373_PERIOD_CTRL_PERIOD_LOOP_MASK (0xFFFF << RTL8373_PERIOD_CTRL_PERIOD_LOOP_OFFSET) + #define RTL8373_PERIOD_CTRL_PERIOD_CHK_OFFSET (0) + #define RTL8373_PERIOD_CTRL_PERIOD_CHK_MASK (0xFFFF << RTL8373_PERIOD_CTRL_PERIOD_CHK_OFFSET) + +#define RTL8373_RLDP_TX_PMSK_ADDR (0x1078) + #define RTL8373_RLDP_TX_PMSK_PMSK_OFFSET (0) + #define RTL8373_RLDP_TX_PMSK_PMSK_MASK (0x3FF << RTL8373_RLDP_TX_PMSK_PMSK_OFFSET) + +#define RTL8373_RAND_NUM0_ADDR (0x107C) + #define RTL8373_RAND_NUM0_RAN0_31_OFFSET (0) + #define RTL8373_RAND_NUM0_RAN0_31_MASK (0xFFFFFFFF << RTL8373_RAND_NUM0_RAN0_31_OFFSET) + +#define RTL8373_RAND_NUM1_ADDR (0x1080) + #define RTL8373_RAND_NUM1_RAN32_47_OFFSET (0) + #define RTL8373_RAND_NUM1_RAN32_47_MASK (0xFFFF << RTL8373_RAND_NUM1_RAN32_47_OFFSET) + +#define RTL8373_MAGIC_NUM0_ADDR (0x1084) + #define RTL8373_MAGIC_NUM0_MGC0_31_OFFSET (0) + #define RTL8373_MAGIC_NUM0_MGC0_31_MASK (0xFFFFFFFF << RTL8373_MAGIC_NUM0_MGC0_31_OFFSET) + +#define RTL8373_MAGIC_NUM1_ADDR (0x1088) + #define RTL8373_MAGIC_NUM1_MGC32_47_OFFSET (0) + #define RTL8373_MAGIC_NUM1_MGC32_47_MASK (0xFFFF << RTL8373_MAGIC_NUM1_MGC32_47_OFFSET) + +#define RTL8373_LOOP_STATE_ADDR(port) (0x108C + (((port / 10) << 2))) /* port: 0-9 */ + #define RTL8373_LOOP_STATE_LOOP_PMSK_OFFSET(port) (port % 0xA) + #define RTL8373_LOOP_STATE_LOOP_PMSK_MASK(port) (0x1 << RTL8373_LOOP_STATE_LOOP_PMSK_OFFSET(port)) + +#define RTL8373_LOOPED_STATE_ADDR(port) (0x1090 + (((port / 10) << 2))) /* port: 0-9 */ + #define RTL8373_LOOPED_STATE_LOOPED_PMSK_OFFSET(port) (port % 0xA) + #define RTL8373_LOOPED_STATE_LOOPED_PMSK_MASK(port) (0x1 << RTL8373_LOOPED_STATE_LOOPED_PMSK_OFFSET(port)) + +#define RTL8373_LEAVE_LOOP_STATE_ADDR(port) (0x1094 + (((port / 10) << 2))) /* port: 0-9 */ + #define RTL8373_LEAVE_LOOP_STATE_LEAVE_LOOP_PMSK_OFFSET(port) (port % 0xA) + #define RTL8373_LEAVE_LOOP_STATE_LEAVE_LOOP_PMSK_MASK(port) (0x1 << RTL8373_LEAVE_LOOP_STATE_LEAVE_LOOP_PMSK_OFFSET(port)) + +#define RTL8373_LOOPPAIR_ADDR(port) (0x1098 + (((port >> 3) << 2))) /* port: 0-9 */ + #define RTL8373_LOOPPAIR_LOOP_PAIR_OFFSET(port) ((port & 0x7) << 2) + #define RTL8373_LOOPPAIR_LOOP_PAIR_MASK(port) (0xF << RTL8373_LOOPPAIR_LOOP_PAIR_OFFSET(port)) + +#define RTL8373_RRCP_CTRL_ADDR (0x51E4) + #define RTL8373_RRCP_CTRL_RRCP_TRAP_OFFSET (0) + #define RTL8373_RRCP_CTRL_RRCP_TRAP_MASK (0x3 << RTL8373_RRCP_CTRL_RRCP_TRAP_OFFSET) + +/* + * Feature: Auto Recovery + */ +#define RTL8373_RXPORT_DSC_STS_ADDR (0x75A8) + #define RTL8373_RXPORT_DSC_STS_RXPORT_DSC_STS_OFFSET (16) + #define RTL8373_RXPORT_DSC_STS_RXPORT_DSC_STS_MASK (0x3FF << RTL8373_RXPORT_DSC_STS_RXPORT_DSC_STS_OFFSET) + #define RTL8373_RXPORT_DSC_STS_RXPORT_DSC_ERR_OFFSET (0) + #define RTL8373_RXPORT_DSC_STS_RXPORT_DSC_ERR_MASK (0x3FF << RTL8373_RXPORT_DSC_STS_RXPORT_DSC_ERR_OFFSET) + +#define RTL8373_SW_Q_RST_THR_ADDR (0x75AC) + #define RTL8373_SW_Q_RST_THR_SW_Q_RST_SYS_THR_OFFSET (0) + #define RTL8373_SW_Q_RST_THR_SW_Q_RST_SYS_THR_MASK (0xFFF << RTL8373_SW_Q_RST_THR_SW_Q_RST_SYS_THR_OFFSET) + +#define RTL8373_SW_Q_RST_P_THR_ADDR (0x75B0) + #define RTL8373_SW_Q_RST_P_THR_SW_Q_RST_P_THR_OFFSET (0) + #define RTL8373_SW_Q_RST_P_THR_SW_Q_RST_P_THR_MASK (0xFFF << RTL8373_SW_Q_RST_P_THR_SW_Q_RST_P_THR_OFFSET) + +#define RTL8373_LD_TX_DSC_STS_ADDR (0x453C) + #define RTL8373_LD_TX_DSC_STS_LD_TX_DSC_STS_OFFSET (16) + #define RTL8373_LD_TX_DSC_STS_LD_TX_DSC_STS_MASK (0x3FF << RTL8373_LD_TX_DSC_STS_LD_TX_DSC_STS_OFFSET) + #define RTL8373_LD_TX_DSC_STS_LD_TX_DSC_ERR_OFFSET (0) + #define RTL8373_LD_TX_DSC_STS_LD_TX_DSC_ERR_MASK (0x3FF << RTL8373_LD_TX_DSC_STS_LD_TX_DSC_ERR_OFFSET) + +#define RTL8373_TX_DSC_CHK_TMR_ADDR (0x4540) + #define RTL8373_TX_DSC_CHK_TMR_TX_DSC_CHK_TMR_OFFSET (0) + #define RTL8373_TX_DSC_CHK_TMR_TX_DSC_CHK_TMR_MASK (0xFF << RTL8373_TX_DSC_CHK_TMR_TX_DSC_CHK_TMR_OFFSET) + +#define RTL8373_RXFIFO_OVERFLOW_STS_ADDR (0x10A0) + #define RTL8373_RXFIFO_OVERFLOW_STS_RXFIFO_OVERFLOW_STS_OFFSET (16) + #define RTL8373_RXFIFO_OVERFLOW_STS_RXFIFO_OVERFLOW_STS_MASK (0x3FF << RTL8373_RXFIFO_OVERFLOW_STS_RXFIFO_OVERFLOW_STS_OFFSET) + #define RTL8373_RXFIFO_OVERFLOW_STS_RXFIFO_OVERFLOW_ERR_OFFSET (0) + #define RTL8373_RXFIFO_OVERFLOW_STS_RXFIFO_OVERFLOW_ERR_MASK (0x3FF << RTL8373_RXFIFO_OVERFLOW_STS_RXFIFO_OVERFLOW_ERR_OFFSET) + +#define RTL8373_RXFIFO_RDEMPTY_STS_ADDR (0x10A4) + #define RTL8373_RXFIFO_RDEMPTY_STS_RXFIFO_RDEMPTY_STS_OFFSET (16) + #define RTL8373_RXFIFO_RDEMPTY_STS_RXFIFO_RDEMPTY_STS_MASK (0x3FF << RTL8373_RXFIFO_RDEMPTY_STS_RXFIFO_RDEMPTY_STS_OFFSET) + #define RTL8373_RXFIFO_RDEMPTY_STS_RXFIFO_RDEMPTY_ERR_OFFSET (0) + #define RTL8373_RXFIFO_RDEMPTY_STS_RXFIFO_RDEMPTY_ERR_MASK (0x3FF << RTL8373_RXFIFO_RDEMPTY_STS_RXFIFO_RDEMPTY_ERR_OFFSET) + +#define RTL8373_TXFIFO_OVERFLOW_STS_ADDR (0x10A8) + #define RTL8373_TXFIFO_OVERFLOW_STS_TXFIFO_OVERFLOW_STS_OFFSET (16) + #define RTL8373_TXFIFO_OVERFLOW_STS_TXFIFO_OVERFLOW_STS_MASK (0x3FF << RTL8373_TXFIFO_OVERFLOW_STS_TXFIFO_OVERFLOW_STS_OFFSET) + #define RTL8373_TXFIFO_OVERFLOW_STS_TXFIFO_OVERFLOW_ERR_OFFSET (0) + #define RTL8373_TXFIFO_OVERFLOW_STS_TXFIFO_OVERFLOW_ERR_MASK (0x3FF << RTL8373_TXFIFO_OVERFLOW_STS_TXFIFO_OVERFLOW_ERR_OFFSET) + +#define RTL8373_TXFIFO_RDEMPTY_STS_ADDR (0x10AC) + #define RTL8373_TXFIFO_RDEMPTY_STS_TXFIFO_RDEMPTY_STS_OFFSET (16) + #define RTL8373_TXFIFO_RDEMPTY_STS_TXFIFO_RDEMPTY_STS_MASK (0x3FF << RTL8373_TXFIFO_RDEMPTY_STS_TXFIFO_RDEMPTY_STS_OFFSET) + #define RTL8373_TXFIFO_RDEMPTY_STS_TXFIFO_RDEMPTY_ERR_OFFSET (0) + #define RTL8373_TXFIFO_RDEMPTY_STS_TXFIFO_RDEMPTY_ERR_MASK (0x3FF << RTL8373_TXFIFO_RDEMPTY_STS_TXFIFO_RDEMPTY_ERR_OFFSET) + +#define RTL8373_PINGPONG_PLUS_STS_ADDR (0x4544) + #define RTL8373_PINGPONG_PLUS_STS_PINGPONG_PLUS_STS_OFFSET (16) + #define RTL8373_PINGPONG_PLUS_STS_PINGPONG_PLUS_STS_MASK (0x3FF << RTL8373_PINGPONG_PLUS_STS_PINGPONG_PLUS_STS_OFFSET) + #define RTL8373_PINGPONG_PLUS_STS_PINGPONG_PLUS_ERR_OFFSET (0) + #define RTL8373_PINGPONG_PLUS_STS_PINGPONG_PLUS_ERR_MASK (0x3FF << RTL8373_PINGPONG_PLUS_STS_PINGPONG_PLUS_ERR_OFFSET) + +#define RTL8373_TOKEN_STS_ADDR (0x75B4) + #define RTL8373_TOKEN_STS_TOKEN_STS_OFFSET (16) + #define RTL8373_TOKEN_STS_TOKEN_STS_MASK (0x3FF << RTL8373_TOKEN_STS_TOKEN_STS_OFFSET) + #define RTL8373_TOKEN_STS_TOKEN_ERR_OFFSET (0) + #define RTL8373_TOKEN_STS_TOKEN_ERR_MASK (0x3FF << RTL8373_TOKEN_STS_TOKEN_ERR_OFFSET) + +#define RTL8373_SW_Q_RST_CNT_ADDR (0x6054) + #define RTL8373_SW_Q_RST_CNT_SW_Q_RST_ASIC_CNT_OFFSET (0) + #define RTL8373_SW_Q_RST_CNT_SW_Q_RST_ASIC_CNT_MASK (0xFFFF << RTL8373_SW_Q_RST_CNT_SW_Q_RST_ASIC_CNT_OFFSET) + +#define RTL8373_AUTO_RECOVER_SRC_SEL_INGRESS_ADDR (0x75B8) + #define RTL8373_AUTO_RECOVER_SRC_SEL_INGRESS_TOKEN_ERR_MSK_OFFSET (16) + #define RTL8373_AUTO_RECOVER_SRC_SEL_INGRESS_TOKEN_ERR_MSK_MASK (0x3FF << RTL8373_AUTO_RECOVER_SRC_SEL_INGRESS_TOKEN_ERR_MSK_OFFSET) + #define RTL8373_AUTO_RECOVER_SRC_SEL_INGRESS_RXSYS_DSC_ERR_MSK_OFFSET (10) + #define RTL8373_AUTO_RECOVER_SRC_SEL_INGRESS_RXSYS_DSC_ERR_MSK_MASK (0x1 << RTL8373_AUTO_RECOVER_SRC_SEL_INGRESS_RXSYS_DSC_ERR_MSK_OFFSET) + #define RTL8373_AUTO_RECOVER_SRC_SEL_INGRESS_RXPORT_DSC_ERR_MSK_OFFSET (0) + #define RTL8373_AUTO_RECOVER_SRC_SEL_INGRESS_RXPORT_DSC_ERR_MSK_MASK (0x3FF << RTL8373_AUTO_RECOVER_SRC_SEL_INGRESS_RXPORT_DSC_ERR_MSK_OFFSET) + +#define RTL8373_AUTO_RECOVER_SRC_SEL_EGRESS_ADDR (0x4548) + #define RTL8373_AUTO_RECOVER_SRC_SEL_EGRESS_PINGPONG_PLUS_ERR_MSK_OFFSET (16) + #define RTL8373_AUTO_RECOVER_SRC_SEL_EGRESS_PINGPONG_PLUS_ERR_MSK_MASK (0x3FF << RTL8373_AUTO_RECOVER_SRC_SEL_EGRESS_PINGPONG_PLUS_ERR_MSK_OFFSET) + #define RTL8373_AUTO_RECOVER_SRC_SEL_EGRESS_LD_TX_DSC_ERR_MSK_OFFSET (0) + #define RTL8373_AUTO_RECOVER_SRC_SEL_EGRESS_LD_TX_DSC_ERR_MSK_MASK (0x3FF << RTL8373_AUTO_RECOVER_SRC_SEL_EGRESS_LD_TX_DSC_ERR_MSK_OFFSET) + +#define RTL8373_AUTO_RECOVER_SRC_SEL_MAC_0_ADDR (0x10B0) + #define RTL8373_AUTO_RECOVER_SRC_SEL_MAC_0_RXFIFO_RDEMPTY_ERR_MSK_OFFSET (16) + #define RTL8373_AUTO_RECOVER_SRC_SEL_MAC_0_RXFIFO_RDEMPTY_ERR_MSK_MASK (0x3FF << RTL8373_AUTO_RECOVER_SRC_SEL_MAC_0_RXFIFO_RDEMPTY_ERR_MSK_OFFSET) + #define RTL8373_AUTO_RECOVER_SRC_SEL_MAC_0_RXFIFO_OVERFLOW_ERR_MSK_OFFSET (0) + #define RTL8373_AUTO_RECOVER_SRC_SEL_MAC_0_RXFIFO_OVERFLOW_ERR_MSK_MASK (0x3FF << RTL8373_AUTO_RECOVER_SRC_SEL_MAC_0_RXFIFO_OVERFLOW_ERR_MSK_OFFSET) + +#define RTL8373_AUTO_RECOVER_SRC_SEL_MAC_1_ADDR (0x10B4) + #define RTL8373_AUTO_RECOVER_SRC_SEL_MAC_1_TXFIFO_RDEMPTY_ERR_MSK_OFFSET (16) + #define RTL8373_AUTO_RECOVER_SRC_SEL_MAC_1_TXFIFO_RDEMPTY_ERR_MSK_MASK (0x3FF << RTL8373_AUTO_RECOVER_SRC_SEL_MAC_1_TXFIFO_RDEMPTY_ERR_MSK_OFFSET) + #define RTL8373_AUTO_RECOVER_SRC_SEL_MAC_1_TXFIFO_OVERFLOW_ERR_MSK_OFFSET (0) + #define RTL8373_AUTO_RECOVER_SRC_SEL_MAC_1_TXFIFO_OVERFLOW_ERR_MSK_MASK (0x3FF << RTL8373_AUTO_RECOVER_SRC_SEL_MAC_1_TXFIFO_OVERFLOW_ERR_MSK_OFFSET) + +#define RTL8373_TRIG_AUTO_RECOVER_CTRL_INGRESS_ADDR (0x75BC) + #define RTL8373_TRIG_AUTO_RECOVER_CTRL_INGRESS_EN_TOKEN_ERR_TRIG_OFFSET (2) + #define RTL8373_TRIG_AUTO_RECOVER_CTRL_INGRESS_EN_TOKEN_ERR_TRIG_MASK (0x1 << RTL8373_TRIG_AUTO_RECOVER_CTRL_INGRESS_EN_TOKEN_ERR_TRIG_OFFSET) + #define RTL8373_TRIG_AUTO_RECOVER_CTRL_INGRESS_EN_RXPORT_DSC_ERR_TRIG_OFFSET (1) + #define RTL8373_TRIG_AUTO_RECOVER_CTRL_INGRESS_EN_RXPORT_DSC_ERR_TRIG_MASK (0x1 << RTL8373_TRIG_AUTO_RECOVER_CTRL_INGRESS_EN_RXPORT_DSC_ERR_TRIG_OFFSET) + #define RTL8373_TRIG_AUTO_RECOVER_CTRL_INGRESS_EN_SYS_DSC_ERR_TRIG_OFFSET (0) + #define RTL8373_TRIG_AUTO_RECOVER_CTRL_INGRESS_EN_SYS_DSC_ERR_TRIG_MASK (0x1 << RTL8373_TRIG_AUTO_RECOVER_CTRL_INGRESS_EN_SYS_DSC_ERR_TRIG_OFFSET) + +#define RTL8373_TRIG_AUTO_RECOVER_CTRL_EGRESS_ADDR (0x454C) + #define RTL8373_TRIG_AUTO_RECOVER_CTRL_EGRESS_EN_PINGPONG_PLUS_ERR_TRIG_OFFSET (1) + #define RTL8373_TRIG_AUTO_RECOVER_CTRL_EGRESS_EN_PINGPONG_PLUS_ERR_TRIG_MASK (0x1 << RTL8373_TRIG_AUTO_RECOVER_CTRL_EGRESS_EN_PINGPONG_PLUS_ERR_TRIG_OFFSET) + #define RTL8373_TRIG_AUTO_RECOVER_CTRL_EGRESS_EN_LD_TX_DSC_ERR_TRIG_OFFSET (0) + #define RTL8373_TRIG_AUTO_RECOVER_CTRL_EGRESS_EN_LD_TX_DSC_ERR_TRIG_MASK (0x1 << RTL8373_TRIG_AUTO_RECOVER_CTRL_EGRESS_EN_LD_TX_DSC_ERR_TRIG_OFFSET) + +#define RTL8373_TRIG_AUTO_RECOVER_CTRL_MAC_ADDR (0x10B8) + #define RTL8373_TRIG_AUTO_RECOVER_CTRL_MAC_EN_FIFO_ERR_TRIG_OFFSET (0) + #define RTL8373_TRIG_AUTO_RECOVER_CTRL_MAC_EN_FIFO_ERR_TRIG_MASK (0x1 << RTL8373_TRIG_AUTO_RECOVER_CTRL_MAC_EN_FIFO_ERR_TRIG_OFFSET) + +#define RTL8373_AUTO_RECOVER_EVENT_FLAG_STS_INGRESS_ADDR (0x75C0) + #define RTL8373_AUTO_RECOVER_EVENT_FLAG_STS_INGRESS_GLB_TOKEN_STS_OFFSET (2) + #define RTL8373_AUTO_RECOVER_EVENT_FLAG_STS_INGRESS_GLB_TOKEN_STS_MASK (0x1 << RTL8373_AUTO_RECOVER_EVENT_FLAG_STS_INGRESS_GLB_TOKEN_STS_OFFSET) + #define RTL8373_AUTO_RECOVER_EVENT_FLAG_STS_INGRESS_GLB_RXPORT_DSC_STS_OFFSET (1) + #define RTL8373_AUTO_RECOVER_EVENT_FLAG_STS_INGRESS_GLB_RXPORT_DSC_STS_MASK (0x1 << RTL8373_AUTO_RECOVER_EVENT_FLAG_STS_INGRESS_GLB_RXPORT_DSC_STS_OFFSET) + #define RTL8373_AUTO_RECOVER_EVENT_FLAG_STS_INGRESS_GLB_SYS_DSC_STS_OFFSET (0) + #define RTL8373_AUTO_RECOVER_EVENT_FLAG_STS_INGRESS_GLB_SYS_DSC_STS_MASK (0x1 << RTL8373_AUTO_RECOVER_EVENT_FLAG_STS_INGRESS_GLB_SYS_DSC_STS_OFFSET) + +#define RTL8373_AUTO_RECOVER_EVENT_FLAG_STS_EGRESS_ADDR (0x4550) + #define RTL8373_AUTO_RECOVER_EVENT_FLAG_STS_EGRESS_GLB_PINGPONG_STS_OFFSET (1) + #define RTL8373_AUTO_RECOVER_EVENT_FLAG_STS_EGRESS_GLB_PINGPONG_STS_MASK (0x1 << RTL8373_AUTO_RECOVER_EVENT_FLAG_STS_EGRESS_GLB_PINGPONG_STS_OFFSET) + #define RTL8373_AUTO_RECOVER_EVENT_FLAG_STS_EGRESS_GLB_LD_TX_DSC_STS_OFFSET (0) + #define RTL8373_AUTO_RECOVER_EVENT_FLAG_STS_EGRESS_GLB_LD_TX_DSC_STS_MASK (0x1 << RTL8373_AUTO_RECOVER_EVENT_FLAG_STS_EGRESS_GLB_LD_TX_DSC_STS_OFFSET) + +#define RTL8373_AUTO_RECOVER_EVENT_FLAG_STS_MAC_ADDR (0x10BC) + #define RTL8373_AUTO_RECOVER_EVENT_FLAG_STS_MAC_GLB_FIFO_STS_OFFSET (0) + #define RTL8373_AUTO_RECOVER_EVENT_FLAG_STS_MAC_GLB_FIFO_STS_MASK (0x1 << RTL8373_AUTO_RECOVER_EVENT_FLAG_STS_MAC_GLB_FIFO_STS_OFFSET) + +#define RTL8373_AUTO_RECOVER_EVENT_FLAG_ERR_INGRESS_ADDR (0x75C4) + #define RTL8373_AUTO_RECOVER_EVENT_FLAG_ERR_INGRESS_GLB_TOKEN_ERR_OFFSET (2) + #define RTL8373_AUTO_RECOVER_EVENT_FLAG_ERR_INGRESS_GLB_TOKEN_ERR_MASK (0x1 << RTL8373_AUTO_RECOVER_EVENT_FLAG_ERR_INGRESS_GLB_TOKEN_ERR_OFFSET) + #define RTL8373_AUTO_RECOVER_EVENT_FLAG_ERR_INGRESS_GLB_RX_P_DSC_ERR_OFFSET (1) + #define RTL8373_AUTO_RECOVER_EVENT_FLAG_ERR_INGRESS_GLB_RX_P_DSC_ERR_MASK (0x1 << RTL8373_AUTO_RECOVER_EVENT_FLAG_ERR_INGRESS_GLB_RX_P_DSC_ERR_OFFSET) + #define RTL8373_AUTO_RECOVER_EVENT_FLAG_ERR_INGRESS_GLB_SYS_DSC_ERR_OFFSET (0) + #define RTL8373_AUTO_RECOVER_EVENT_FLAG_ERR_INGRESS_GLB_SYS_DSC_ERR_MASK (0x1 << RTL8373_AUTO_RECOVER_EVENT_FLAG_ERR_INGRESS_GLB_SYS_DSC_ERR_OFFSET) + +#define RTL8373_AUTO_RECOVER_EVENT_FLAG_ERR_EGRESS_ADDR (0x4554) + #define RTL8373_AUTO_RECOVER_EVENT_FLAG_ERR_EGRESS_GLB_PINGPONG_ERR_OFFSET (1) + #define RTL8373_AUTO_RECOVER_EVENT_FLAG_ERR_EGRESS_GLB_PINGPONG_ERR_MASK (0x1 << RTL8373_AUTO_RECOVER_EVENT_FLAG_ERR_EGRESS_GLB_PINGPONG_ERR_OFFSET) + #define RTL8373_AUTO_RECOVER_EVENT_FLAG_ERR_EGRESS_GLB_LD_TX_DSC_ERR_OFFSET (0) + #define RTL8373_AUTO_RECOVER_EVENT_FLAG_ERR_EGRESS_GLB_LD_TX_DSC_ERR_MASK (0x1 << RTL8373_AUTO_RECOVER_EVENT_FLAG_ERR_EGRESS_GLB_LD_TX_DSC_ERR_OFFSET) + +#define RTL8373_AUTO_RECOVER_EVENT_FLAG_ERR_MAC_ADDR (0x10C0) + #define RTL8373_AUTO_RECOVER_EVENT_FLAG_ERR_MAC_GLB_FIFO_ERR_OFFSET (0) + #define RTL8373_AUTO_RECOVER_EVENT_FLAG_ERR_MAC_GLB_FIFO_ERR_MASK (0x1 << RTL8373_AUTO_RECOVER_EVENT_FLAG_ERR_MAC_GLB_FIFO_ERR_OFFSET) + +#define RTL8373_FIFO_FLOW_FLAG_MSK_ADDR (0x10C4) + #define RTL8373_FIFO_FLOW_FLAG_MSK_RXFIFO_DGLT_EN_OFFSET (6) + #define RTL8373_FIFO_FLOW_FLAG_MSK_RXFIFO_DGLT_EN_MASK (0x1 << RTL8373_FIFO_FLOW_FLAG_MSK_RXFIFO_DGLT_EN_OFFSET) + #define RTL8373_FIFO_FLOW_FLAG_MSK_EGR_P_DGLT_EN_OFFSET (5) + #define RTL8373_FIFO_FLOW_FLAG_MSK_EGR_P_DGLT_EN_MASK (0x1 << RTL8373_FIFO_FLOW_FLAG_MSK_EGR_P_DGLT_EN_OFFSET) + #define RTL8373_FIFO_FLOW_FLAG_MSK_TXFIFO_DGLT_EN_OFFSET (4) + #define RTL8373_FIFO_FLOW_FLAG_MSK_TXFIFO_DGLT_EN_MASK (0x1 << RTL8373_FIFO_FLOW_FLAG_MSK_TXFIFO_DGLT_EN_OFFSET) + #define RTL8373_FIFO_FLOW_FLAG_MSK_FIFO_FLAG_MSK_OFFSET (0) + #define RTL8373_FIFO_FLOW_FLAG_MSK_FIFO_FLAG_MSK_MASK (0xF << RTL8373_FIFO_FLOW_FLAG_MSK_FIFO_FLAG_MSK_OFFSET) + +/* + * Feature: ECO + */ +#define RTL8373_CHIP_MISC_DUMY_0_ADDR (0x60) + #define RTL8373_CHIP_MISC_DUMY_0_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_CHIP_MISC_DUMY_0_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_CHIP_MISC_DUMY_0_DUMMY_REGISTER_OFFSET) + +#define RTL8373_CHIP_MISC_DUMY_1_ADDR (0x64) + #define RTL8373_CHIP_MISC_DUMY_1_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_CHIP_MISC_DUMY_1_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_CHIP_MISC_DUMY_1_DUMMY_REGISTER_OFFSET) + +#define RTL8373_TM0_CTRL_DUMY_0_ADDR (0x2F4) + #define RTL8373_TM0_CTRL_DUMY_0_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_TM0_CTRL_DUMY_0_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_TM0_CTRL_DUMY_0_DUMMY_REGISTER_OFFSET) + +#define RTL8373_TM0_CTRL_DUMY_1_ADDR (0x2F8) + #define RTL8373_TM0_CTRL_DUMY_1_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_TM0_CTRL_DUMY_1_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_TM0_CTRL_DUMY_1_DUMMY_REGISTER_OFFSET) + +#define RTL8373_TM1_CTRL_DUMY_0_ADDR (0x354) + #define RTL8373_TM1_CTRL_DUMY_0_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_TM1_CTRL_DUMY_0_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_TM1_CTRL_DUMY_0_DUMMY_REGISTER_OFFSET) + +#define RTL8373_TM1_CTRL_DUMY_1_ADDR (0x358) + #define RTL8373_TM1_CTRL_DUMY_1_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_TM1_CTRL_DUMY_1_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_TM1_CTRL_DUMY_1_DUMMY_REGISTER_OFFSET) + +#define RTL8373_VOLT_PROB_DUMY_0_ADDR (0x39C) + #define RTL8373_VOLT_PROB_DUMY_0_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_VOLT_PROB_DUMY_0_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_VOLT_PROB_DUMY_0_DUMMY_REGISTER_OFFSET) + +#define RTL8373_VOLT_PROB_DUMY_1_ADDR (0x3A0) + #define RTL8373_VOLT_PROB_DUMY_1_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_VOLT_PROB_DUMY_1_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_VOLT_PROB_DUMY_1_DUMMY_REGISTER_OFFSET) + +#define RTL8373_REG_IF_DUMY_0_ADDR (0x44C) + #define RTL8373_REG_IF_DUMY_0_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_REG_IF_DUMY_0_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_REG_IF_DUMY_0_DUMMY_REGISTER_OFFSET) + +#define RTL8373_REG_IF_DUMY_1_ADDR (0x450) + #define RTL8373_REG_IF_DUMY_1_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_REG_IF_DUMY_1_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_REG_IF_DUMY_1_DUMMY_REGISTER_OFFSET) + +#define RTL8373_MIB_0_DUMY_0_ADDR (0x6F4) + #define RTL8373_MIB_0_DUMY_0_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_MIB_0_DUMY_0_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_MIB_0_DUMY_0_DUMMY_REGISTER_OFFSET) + +#define RTL8373_MIB_0_DUMY_1_ADDR (0x6F8) + #define RTL8373_MIB_0_DUMY_1_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_MIB_0_DUMY_1_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_MIB_0_DUMY_1_DUMMY_REGISTER_OFFSET) + +#define RTL8373_MIB_1_DUMY_0_ADDR (0x720) + #define RTL8373_MIB_1_DUMY_0_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_MIB_1_DUMY_0_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_MIB_1_DUMY_0_DUMMY_REGISTER_OFFSET) + +#define RTL8373_MIB_1_DUMY_1_ADDR (0x724) + #define RTL8373_MIB_1_DUMY_1_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_MIB_1_DUMY_1_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_MIB_1_DUMY_1_DUMMY_REGISTER_OFFSET) + +#define RTL8373_MIB_2_DUMY_0_ADDR (0x740) + #define RTL8373_MIB_2_DUMY_0_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_MIB_2_DUMY_0_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_MIB_2_DUMY_0_DUMMY_REGISTER_OFFSET) + +#define RTL8373_MIB_2_DUMY_1_ADDR (0x744) + #define RTL8373_MIB_2_DUMY_1_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_MIB_2_DUMY_1_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_MIB_2_DUMY_1_DUMMY_REGISTER_OFFSET) + +#define RTL8373_MIB_3_DUMY_0_ADDR (0x760) + #define RTL8373_MIB_3_DUMY_0_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_MIB_3_DUMY_0_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_MIB_3_DUMY_0_DUMMY_REGISTER_OFFSET) + +#define RTL8373_MIB_3_DUMY_1_ADDR (0x764) + #define RTL8373_MIB_3_DUMY_1_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_MIB_3_DUMY_1_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_MIB_3_DUMY_1_DUMMY_REGISTER_OFFSET) + +#define RTL8373_MIB_4_DUMY_0_ADDR (0x780) + #define RTL8373_MIB_4_DUMY_0_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_MIB_4_DUMY_0_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_MIB_4_DUMY_0_DUMMY_REGISTER_OFFSET) + +#define RTL8373_MIB_4_DUMY_1_ADDR (0x784) + #define RTL8373_MIB_4_DUMY_1_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_MIB_4_DUMY_1_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_MIB_4_DUMY_1_DUMMY_REGISTER_OFFSET) + +#define RTL8373_MIB_5_DUMY_0_ADDR (0x7A0) + #define RTL8373_MIB_5_DUMY_0_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_MIB_5_DUMY_0_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_MIB_5_DUMY_0_DUMMY_REGISTER_OFFSET) + +#define RTL8373_MIB_5_DUMY_1_ADDR (0x7A4) + #define RTL8373_MIB_5_DUMY_1_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_MIB_5_DUMY_1_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_MIB_5_DUMY_1_DUMMY_REGISTER_OFFSET) + +#define RTL8373_MIB_6_DUMY_0_ADDR (0x7C0) + #define RTL8373_MIB_6_DUMY_0_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_MIB_6_DUMY_0_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_MIB_6_DUMY_0_DUMMY_REGISTER_OFFSET) + +#define RTL8373_MIB_6_DUMY_1_ADDR (0x7C4) + #define RTL8373_MIB_6_DUMY_1_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_MIB_6_DUMY_1_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_MIB_6_DUMY_1_DUMMY_REGISTER_OFFSET) + +#define RTL8373_MIB_7_DUMY_0_ADDR (0x7E0) + #define RTL8373_MIB_7_DUMY_0_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_MIB_7_DUMY_0_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_MIB_7_DUMY_0_DUMMY_REGISTER_OFFSET) + +#define RTL8373_MIB_7_DUMY_1_ADDR (0x7E4) + #define RTL8373_MIB_7_DUMY_1_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_MIB_7_DUMY_1_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_MIB_7_DUMY_1_DUMMY_REGISTER_OFFSET) + +#define RTL8373_MIB_8_DUMY_0_ADDR (0x800) + #define RTL8373_MIB_8_DUMY_0_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_MIB_8_DUMY_0_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_MIB_8_DUMY_0_DUMMY_REGISTER_OFFSET) + +#define RTL8373_MIB_8_DUMY_1_ADDR (0x804) + #define RTL8373_MIB_8_DUMY_1_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_MIB_8_DUMY_1_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_MIB_8_DUMY_1_DUMMY_REGISTER_OFFSET) + +#define RTL8373_MIB_9_DUMY_0_ADDR (0x820) + #define RTL8373_MIB_9_DUMY_0_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_MIB_9_DUMY_0_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_MIB_9_DUMY_0_DUMMY_REGISTER_OFFSET) + +#define RTL8373_MIB_9_DUMY_1_ADDR (0x824) + #define RTL8373_MIB_9_DUMY_1_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_MIB_9_DUMY_1_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_MIB_9_DUMY_1_DUMMY_REGISTER_OFFSET) + +#define RTL8373_MIB_10_DUMY_0_ADDR (0x840) + #define RTL8373_MIB_10_DUMY_0_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_MIB_10_DUMY_0_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_MIB_10_DUMY_0_DUMMY_REGISTER_OFFSET) + +#define RTL8373_MIB_10_DUMY_1_ADDR (0x844) + #define RTL8373_MIB_10_DUMY_1_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_MIB_10_DUMY_1_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_MIB_10_DUMY_1_DUMMY_REGISTER_OFFSET) + +#define RTL8373_MIB_11_DUMY_0_ADDR (0x860) + #define RTL8373_MIB_11_DUMY_0_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_MIB_11_DUMY_0_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_MIB_11_DUMY_0_DUMMY_REGISTER_OFFSET) + +#define RTL8373_MIB_11_DUMY_1_ADDR (0x864) + #define RTL8373_MIB_11_DUMY_1_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_MIB_11_DUMY_1_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_MIB_11_DUMY_1_DUMMY_REGISTER_OFFSET) + +#define RTL8373_MIB_12_DUMY_0_ADDR (0x880) + #define RTL8373_MIB_12_DUMY_0_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_MIB_12_DUMY_0_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_MIB_12_DUMY_0_DUMMY_REGISTER_OFFSET) + +#define RTL8373_MIB_12_DUMY_1_ADDR (0x884) + #define RTL8373_MIB_12_DUMY_1_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_MIB_12_DUMY_1_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_MIB_12_DUMY_1_DUMMY_REGISTER_OFFSET) + +#define RTL8373_MIB_13_DUMY_0_ADDR (0x8A0) + #define RTL8373_MIB_13_DUMY_0_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_MIB_13_DUMY_0_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_MIB_13_DUMY_0_DUMMY_REGISTER_OFFSET) + +#define RTL8373_MIB_13_DUMY_1_ADDR (0x8A4) + #define RTL8373_MIB_13_DUMY_1_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_MIB_13_DUMY_1_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_MIB_13_DUMY_1_DUMMY_REGISTER_OFFSET) + +#define RTL8373_MIB_14_DUMY_0_ADDR (0x8C0) + #define RTL8373_MIB_14_DUMY_0_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_MIB_14_DUMY_0_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_MIB_14_DUMY_0_DUMMY_REGISTER_OFFSET) + +#define RTL8373_MIB_14_DUMY_1_ADDR (0x8C4) + #define RTL8373_MIB_14_DUMY_1_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_MIB_14_DUMY_1_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_MIB_14_DUMY_1_DUMMY_REGISTER_OFFSET) + +#define RTL8373_MIB_15_DUMY_0_ADDR (0x8E0) + #define RTL8373_MIB_15_DUMY_0_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_MIB_15_DUMY_0_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_MIB_15_DUMY_0_DUMMY_REGISTER_OFFSET) + +#define RTL8373_MIB_15_DUMY_1_ADDR (0x8E4) + #define RTL8373_MIB_15_DUMY_1_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_MIB_15_DUMY_1_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_MIB_15_DUMY_1_DUMMY_REGISTER_OFFSET) + +#define RTL8373_MIB_16_DUMY_0_ADDR (0x900) + #define RTL8373_MIB_16_DUMY_0_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_MIB_16_DUMY_0_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_MIB_16_DUMY_0_DUMMY_REGISTER_OFFSET) + +#define RTL8373_MIB_16_DUMY_1_ADDR (0x904) + #define RTL8373_MIB_16_DUMY_1_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_MIB_16_DUMY_1_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_MIB_16_DUMY_1_DUMMY_REGISTER_OFFSET) + +#define RTL8373_PHY_INTF_DUMY_0_ADDR (0x970) + #define RTL8373_PHY_INTF_DUMY_0_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_PHY_INTF_DUMY_0_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_PHY_INTF_DUMY_0_DUMMY_REGISTER_OFFSET) + +#define RTL8373_PHY_INTF_DUMY_1_ADDR (0x974) + #define RTL8373_PHY_INTF_DUMY_1_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_PHY_INTF_DUMY_1_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_PHY_INTF_DUMY_1_DUMMY_REGISTER_OFFSET) + +#define RTL8373_PHY_INTF_DUMY_2_ADDR (0x978) + #define RTL8373_PHY_INTF_DUMY_2_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_PHY_INTF_DUMY_2_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_PHY_INTF_DUMY_2_DUMMY_REGISTER_OFFSET) + +#define RTL8373_PHY_INTF_DUMY_3_ADDR (0x97C) + #define RTL8373_PHY_INTF_DUMY_3_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_PHY_INTF_DUMY_3_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_PHY_INTF_DUMY_3_DUMMY_REGISTER_OFFSET) + +#define RTL8373_PHY_PKG_DUMY_0_ADDR (0xA2C) + #define RTL8373_PHY_PKG_DUMY_0_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_PHY_PKG_DUMY_0_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_PHY_PKG_DUMY_0_DUMMY_REGISTER_OFFSET) + +#define RTL8373_PHY_PKG_DUMY_1_ADDR (0xA30) + #define RTL8373_PHY_PKG_DUMY_1_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_PHY_PKG_DUMY_1_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_PHY_PKG_DUMY_1_DUMMY_REGISTER_OFFSET) + +#define RTL8373_PHY_MISC_DUMY_0_ADDR (0xBE0) + #define RTL8373_PHY_MISC_DUMY_0_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_PHY_MISC_DUMY_0_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_PHY_MISC_DUMY_0_DUMMY_REGISTER_OFFSET) + +#define RTL8373_PHY_MISC_DUMY_1_ADDR (0xBE4) + #define RTL8373_PHY_MISC_DUMY_1_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_PHY_MISC_DUMY_1_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_PHY_MISC_DUMY_1_DUMMY_REGISTER_OFFSET) + +#define RTL8373_RANDOM_SEED_DUMY_0_ADDR (0xEC0) + #define RTL8373_RANDOM_SEED_DUMY_0_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_RANDOM_SEED_DUMY_0_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_RANDOM_SEED_DUMY_0_DUMMY_REGISTER_OFFSET) + +#define RTL8373_RANDOM_SEED_DUMY_1_ADDR (0xEC4) + #define RTL8373_RANDOM_SEED_DUMY_1_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_RANDOM_SEED_DUMY_1_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_RANDOM_SEED_DUMY_1_DUMMY_REGISTER_OFFSET) + +#define RTL8373_RANDOM_SEED_DUMY_2_ADDR (0xEC8) + #define RTL8373_RANDOM_SEED_DUMY_2_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_RANDOM_SEED_DUMY_2_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_RANDOM_SEED_DUMY_2_DUMMY_REGISTER_OFFSET) + +#define RTL8373_RANDOM_SEED_DUMY_3_ADDR (0xECC) + #define RTL8373_RANDOM_SEED_DUMY_3_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_RANDOM_SEED_DUMY_3_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_RANDOM_SEED_DUMY_3_DUMMY_REGISTER_OFFSET) + +#define RTL8373_MIB_CTRL_DUMY_0_ADDR (0xF6C) + #define RTL8373_MIB_CTRL_DUMY_0_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_MIB_CTRL_DUMY_0_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_MIB_CTRL_DUMY_0_DUMMY_REGISTER_OFFSET) + +#define RTL8373_MIB_CTRL_DUMY_1_ADDR (0xF70) + #define RTL8373_MIB_CTRL_DUMY_1_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_MIB_CTRL_DUMY_1_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_MIB_CTRL_DUMY_1_DUMMY_REGISTER_OFFSET) + +#define RTL8373_MAC_GLB_DUMY_0_ADDR (0x10C8) + #define RTL8373_MAC_GLB_DUMY_0_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_MAC_GLB_DUMY_0_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_MAC_GLB_DUMY_0_DUMMY_REGISTER_OFFSET) + +#define RTL8373_MAC_GLB_DUMY_1_ADDR (0x10CC) + #define RTL8373_MAC_GLB_DUMY_1_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_MAC_GLB_DUMY_1_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_MAC_GLB_DUMY_1_DUMMY_REGISTER_OFFSET) + +#define RTL8373_PER_PORT_MAC_DUMY_0_ADDR(port) (0x1268 + (((port) << 8))) /* port: 0-9 */ + #define RTL8373_PER_PORT_MAC_DUMY_0_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_PER_PORT_MAC_DUMY_0_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_PER_PORT_MAC_DUMY_0_DUMMY_REGISTER_OFFSET) + +#define RTL8373_PER_PORT_MAC_DUMY_1_ADDR(port) (0x126C + (((port) << 8))) /* port: 0-9 */ + #define RTL8373_PER_PORT_MAC_DUMY_1_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_PER_PORT_MAC_DUMY_1_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_PER_PORT_MAC_DUMY_1_DUMMY_REGISTER_OFFSET) + +#define RTL8373_PER_PORT_TXQ_REG_10P_DUMY_0_ADDR(port) (0x1D48 + (((port) << 10))) /* port: 0-9 */ + #define RTL8373_PER_PORT_TXQ_REG_10P_DUMY_0_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_PER_PORT_TXQ_REG_10P_DUMY_0_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_PER_PORT_TXQ_REG_10P_DUMY_0_DUMMY_REGISTER_OFFSET) + +#define RTL8373_PER_PORT_TXQ_REG_10P_DUMY_1_ADDR(port) (0x1D4C + (((port) << 10))) /* port: 0-9 */ + #define RTL8373_PER_PORT_TXQ_REG_10P_DUMY_1_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_PER_PORT_TXQ_REG_10P_DUMY_1_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_PER_PORT_TXQ_REG_10P_DUMY_1_DUMMY_REGISTER_OFFSET) + +#define RTL8373_EGRESS_CTRL_DUMY_0_ADDR (0x4558) + #define RTL8373_EGRESS_CTRL_DUMY_0_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_EGRESS_CTRL_DUMY_0_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_EGRESS_CTRL_DUMY_0_DUMMY_REGISTER_OFFSET) + +#define RTL8373_EGRESS_CTRL_DUMY_1_ADDR (0x455C) + #define RTL8373_EGRESS_CTRL_DUMY_1_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_EGRESS_CTRL_DUMY_1_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_EGRESS_CTRL_DUMY_1_DUMMY_REGISTER_OFFSET) + +#define RTL8373_EGRESS_CTRL_DUMY_2_ADDR (0x4560) + #define RTL8373_EGRESS_CTRL_DUMY_2_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_EGRESS_CTRL_DUMY_2_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_EGRESS_CTRL_DUMY_2_DUMMY_REGISTER_OFFSET) + +#define RTL8373_EGRESS_CTRL_DUMY_3_ADDR (0x4564) + #define RTL8373_EGRESS_CTRL_DUMY_3_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_EGRESS_CTRL_DUMY_3_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_EGRESS_CTRL_DUMY_3_DUMMY_REGISTER_OFFSET) + +#define RTL8373_ACL_DUMY_0_ADDR (0x4BF0) + #define RTL8373_ACL_DUMY_0_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_ACL_DUMY_0_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_ACL_DUMY_0_DUMMY_REGISTER_OFFSET) + +#define RTL8373_ACL_DUMY_1_ADDR (0x4BF4) + #define RTL8373_ACL_DUMY_1_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_ACL_DUMY_1_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_ACL_DUMY_1_DUMMY_REGISTER_OFFSET) + +#define RTL8373_ACL_DUMY_2_ADDR (0x4BF8) + #define RTL8373_ACL_DUMY_2_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_ACL_DUMY_2_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_ACL_DUMY_2_DUMMY_REGISTER_OFFSET) + +#define RTL8373_ACL_DUMY_3_ADDR (0x4BFC) + #define RTL8373_ACL_DUMY_3_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_ACL_DUMY_3_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_ACL_DUMY_3_DUMMY_REGISTER_OFFSET) + +#define RTL8373_INBW_DUMY_0_ADDR (0x4CB4) + #define RTL8373_INBW_DUMY_0_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_INBW_DUMY_0_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_INBW_DUMY_0_DUMMY_REGISTER_OFFSET) + +#define RTL8373_INBW_DUMY_1_ADDR (0x4CB8) + #define RTL8373_INBW_DUMY_1_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_INBW_DUMY_1_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_INBW_DUMY_1_DUMMY_REGISTER_OFFSET) + +#define RTL8373_CVLAN_DUMY_0_ADDR (0x4E44) + #define RTL8373_CVLAN_DUMY_0_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_CVLAN_DUMY_0_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_CVLAN_DUMY_0_DUMMY_REGISTER_OFFSET) + +#define RTL8373_CVLAN_DUMY_1_ADDR (0x4E48) + #define RTL8373_CVLAN_DUMY_1_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_CVLAN_DUMY_1_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_CVLAN_DUMY_1_DUMMY_REGISTER_OFFSET) + +#define RTL8373_CVLAN_DUMY_2_ADDR (0x4E4C) + #define RTL8373_CVLAN_DUMY_2_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_CVLAN_DUMY_2_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_CVLAN_DUMY_2_DUMMY_REGISTER_OFFSET) + +#define RTL8373_CVLAN_DUMY_3_ADDR (0x4E50) + #define RTL8373_CVLAN_DUMY_3_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_CVLAN_DUMY_3_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_CVLAN_DUMY_3_DUMMY_REGISTER_OFFSET) + +#define RTL8373_DPM_DUMY_0_ADDR (0x51E8) + #define RTL8373_DPM_DUMY_0_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_DPM_DUMY_0_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_DPM_DUMY_0_DUMMY_REGISTER_OFFSET) + +#define RTL8373_DPM_DUMY_1_ADDR (0x51EC) + #define RTL8373_DPM_DUMY_1_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_DPM_DUMY_1_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_DPM_DUMY_1_DUMMY_REGISTER_OFFSET) + +#define RTL8373_IGMP_DUMY_0_ADDR (0x52F4) + #define RTL8373_IGMP_DUMY_0_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_IGMP_DUMY_0_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_IGMP_DUMY_0_DUMMY_REGISTER_OFFSET) + +#define RTL8373_IGMP_DUMY_1_ADDR (0x52F8) + #define RTL8373_IGMP_DUMY_1_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_IGMP_DUMY_1_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_IGMP_DUMY_1_DUMMY_REGISTER_OFFSET) + +#define RTL8373_L2_DUMY_0_ADDR (0x558C) + #define RTL8373_L2_DUMY_0_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_L2_DUMY_0_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_L2_DUMY_0_DUMMY_REGISTER_OFFSET) + +#define RTL8373_L2_DUMY_1_ADDR (0x5590) + #define RTL8373_L2_DUMY_1_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_L2_DUMY_1_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_L2_DUMY_1_DUMMY_REGISTER_OFFSET) + +#define RTL8373_SVLAN_DUMY_0_ADDR (0x5BE8) + #define RTL8373_SVLAN_DUMY_0_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_SVLAN_DUMY_0_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_SVLAN_DUMY_0_DUMMY_REGISTER_OFFSET) + +#define RTL8373_SVLAN_DUMY_1_ADDR (0x5BEC) + #define RTL8373_SVLAN_DUMY_1_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_SVLAN_DUMY_1_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_SVLAN_DUMY_1_DUMMY_REGISTER_OFFSET) + +#define RTL8373_SVLAN_DUMY_2_ADDR (0x5BF0) + #define RTL8373_SVLAN_DUMY_2_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_SVLAN_DUMY_2_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_SVLAN_DUMY_2_DUMMY_REGISTER_OFFSET) + +#define RTL8373_SVLAN_DUMY_3_ADDR (0x5BF4) + #define RTL8373_SVLAN_DUMY_3_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_SVLAN_DUMY_3_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_SVLAN_DUMY_3_DUMMY_REGISTER_OFFSET) + +#define RTL8373_TABLE_DUMY_0_ADDR (0x5CE0) + #define RTL8373_TABLE_DUMY_0_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_TABLE_DUMY_0_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_TABLE_DUMY_0_DUMMY_REGISTER_OFFSET) + +#define RTL8373_TABLE_DUMY_1_ADDR (0x5CE4) + #define RTL8373_TABLE_DUMY_1_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_TABLE_DUMY_1_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_TABLE_DUMY_1_DUMMY_REGISTER_OFFSET) + +#define RTL8373_MTRPOOL_DUMY_0_ADDR (0x5F18) + #define RTL8373_MTRPOOL_DUMY_0_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_MTRPOOL_DUMY_0_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_MTRPOOL_DUMY_0_DUMMY_REGISTER_OFFSET) + +#define RTL8373_MTRPOOL_DUMY_1_ADDR (0x5F1C) + #define RTL8373_MTRPOOL_DUMY_1_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_MTRPOOL_DUMY_1_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_MTRPOOL_DUMY_1_DUMMY_REGISTER_OFFSET) + +#define RTL8373_GLB_CTRL_DUMY_0_ADDR (0x6058) + #define RTL8373_GLB_CTRL_DUMY_0_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_GLB_CTRL_DUMY_0_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_GLB_CTRL_DUMY_0_DUMMY_REGISTER_OFFSET) + +#define RTL8373_GLB_CTRL_DUMY_1_ADDR (0x605C) + #define RTL8373_GLB_CTRL_DUMY_1_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_GLB_CTRL_DUMY_1_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_GLB_CTRL_DUMY_1_DUMMY_REGISTER_OFFSET) + +#define RTL8373_GLB_CTRL_DUMY_2_ADDR (0x6060) + #define RTL8373_GLB_CTRL_DUMY_2_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_GLB_CTRL_DUMY_2_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_GLB_CTRL_DUMY_2_DUMMY_REGISTER_OFFSET) + +#define RTL8373_GLB_CTRL_DUMY_3_ADDR (0x6064) + #define RTL8373_GLB_CTRL_DUMY_3_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_GLB_CTRL_DUMY_3_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_GLB_CTRL_DUMY_3_DUMMY_REGISTER_OFFSET) + +#define RTL8373_SMI_CTRL_DUMY_0_ADDR (0x649C) + #define RTL8373_SMI_CTRL_DUMY_0_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_SMI_CTRL_DUMY_0_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_SMI_CTRL_DUMY_0_DUMMY_REGISTER_OFFSET) + +#define RTL8373_SMI_CTRL_DUMY_1_ADDR (0x64A0) + #define RTL8373_SMI_CTRL_DUMY_1_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_SMI_CTRL_DUMY_1_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_SMI_CTRL_DUMY_1_DUMMY_REGISTER_OFFSET) + +#define RTL8373_LED_DUMY_0_ADDR (0x6604) + #define RTL8373_LED_DUMY_0_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_LED_DUMY_0_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_LED_DUMY_0_DUMMY_REGISTER_OFFSET) + +#define RTL8373_LED_DUMY_1_ADDR (0x6608) + #define RTL8373_LED_DUMY_1_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_LED_DUMY_1_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_LED_DUMY_1_DUMMY_REGISTER_OFFSET) + +#define RTL8373_PKT_ENCAP_DUMY_0_ADDR (0x67BC) + #define RTL8373_PKT_ENCAP_DUMY_0_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_PKT_ENCAP_DUMY_0_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_PKT_ENCAP_DUMY_0_DUMMY_REGISTER_OFFSET) + +#define RTL8373_PKT_ENCAP_DUMY_1_ADDR (0x67C0) + #define RTL8373_PKT_ENCAP_DUMY_1_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_PKT_ENCAP_DUMY_1_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_PKT_ENCAP_DUMY_1_DUMMY_REGISTER_OFFSET) + +#define RTL8373_PKT_ENCAP_DUMY_2_ADDR (0x67C4) + #define RTL8373_PKT_ENCAP_DUMY_2_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_PKT_ENCAP_DUMY_2_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_PKT_ENCAP_DUMY_2_DUMMY_REGISTER_OFFSET) + +#define RTL8373_PKT_ENCAP_DUMY_3_ADDR (0x67C8) + #define RTL8373_PKT_ENCAP_DUMY_3_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_PKT_ENCAP_DUMY_3_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_PKT_ENCAP_DUMY_3_DUMMY_REGISTER_OFFSET) + +#define RTL8373_PKT_PARSER_DUMY_0_ADDR (0x6FF0) + #define RTL8373_PKT_PARSER_DUMY_0_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_PKT_PARSER_DUMY_0_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_PKT_PARSER_DUMY_0_DUMMY_REGISTER_OFFSET) + +#define RTL8373_PKT_PARSER_DUMY_1_ADDR (0x6FF4) + #define RTL8373_PKT_PARSER_DUMY_1_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_PKT_PARSER_DUMY_1_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_PKT_PARSER_DUMY_1_DUMMY_REGISTER_OFFSET) + +#define RTL8373_INGRESS_CTRL_DUMY_0_ADDR (0x7494) + #define RTL8373_INGRESS_CTRL_DUMY_0_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_INGRESS_CTRL_DUMY_0_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_INGRESS_CTRL_DUMY_0_DUMMY_REGISTER_OFFSET) + +#define RTL8373_INGRESS_CTRL_DUMY_1_ADDR (0x7498) + #define RTL8373_INGRESS_CTRL_DUMY_1_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_INGRESS_CTRL_DUMY_1_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_INGRESS_CTRL_DUMY_1_DUMMY_REGISTER_OFFSET) + +#define RTL8373_INGRESS_CTRL_DUMY_2_ADDR (0x749C) + #define RTL8373_INGRESS_CTRL_DUMY_2_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_INGRESS_CTRL_DUMY_2_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_INGRESS_CTRL_DUMY_2_DUMMY_REGISTER_OFFSET) + +#define RTL8373_INGRESS_CTRL_DUMY_3_ADDR (0x74A0) + #define RTL8373_INGRESS_CTRL_DUMY_3_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_INGRESS_CTRL_DUMY_3_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_INGRESS_CTRL_DUMY_3_DUMMY_REGISTER_OFFSET) + +#define RTL8373_INGRESS_CTRL_2_DUMY_0_ADDR (0x75C8) + #define RTL8373_INGRESS_CTRL_2_DUMY_0_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_INGRESS_CTRL_2_DUMY_0_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_INGRESS_CTRL_2_DUMY_0_DUMMY_REGISTER_OFFSET) + +#define RTL8373_INGRESS_CTRL_2_DUMY_1_ADDR (0x75CC) + #define RTL8373_INGRESS_CTRL_2_DUMY_1_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_INGRESS_CTRL_2_DUMY_1_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_INGRESS_CTRL_2_DUMY_1_DUMMY_REGISTER_OFFSET) + +#define RTL8373_INGRESS_CTRL_2_DUMY_2_ADDR (0x75D0) + #define RTL8373_INGRESS_CTRL_2_DUMY_2_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_INGRESS_CTRL_2_DUMY_2_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_INGRESS_CTRL_2_DUMY_2_DUMMY_REGISTER_OFFSET) + +#define RTL8373_INGRESS_CTRL_2_DUMY_3_ADDR (0x75D4) + #define RTL8373_INGRESS_CTRL_2_DUMY_3_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_INGRESS_CTRL_2_DUMY_3_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_INGRESS_CTRL_2_DUMY_3_DUMMY_REGISTER_OFFSET) + +#define RTL8373_NIC_DUMY_0_ADDR (0x789C) + #define RTL8373_NIC_DUMY_0_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_NIC_DUMY_0_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_NIC_DUMY_0_DUMMY_REGISTER_OFFSET) + +#define RTL8373_NIC_DUMY_1_ADDR (0x78A0) + #define RTL8373_NIC_DUMY_1_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_NIC_DUMY_1_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_NIC_DUMY_1_DUMMY_REGISTER_OFFSET) + +#define RTL8373_CHIP_BIST_DUMY_0_ADDR (0x7A30) + #define RTL8373_CHIP_BIST_DUMY_0_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_CHIP_BIST_DUMY_0_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_CHIP_BIST_DUMY_0_DUMMY_REGISTER_OFFSET) + +#define RTL8373_CHIP_BIST_DUMY_1_ADDR (0x7A34) + #define RTL8373_CHIP_BIST_DUMY_1_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_CHIP_BIST_DUMY_1_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_CHIP_BIST_DUMY_1_DUMMY_REGISTER_OFFSET) + +#define RTL8373_SDS_DUMY_0_ADDR (0x7B70) + #define RTL8373_SDS_DUMY_0_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_SDS_DUMY_0_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_SDS_DUMY_0_DUMMY_REGISTER_OFFSET) + +#define RTL8373_SDS_DUMY_1_ADDR (0x7B74) + #define RTL8373_SDS_DUMY_1_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_SDS_DUMY_1_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_SDS_DUMY_1_DUMMY_REGISTER_OFFSET) + +#define RTL8373_IO_DUMY_0_ADDR (0x7FB8) + #define RTL8373_IO_DUMY_0_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_IO_DUMY_0_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_IO_DUMY_0_DUMMY_REGISTER_OFFSET) + +#define RTL8373_IO_DUMY_1_ADDR (0x7FBC) + #define RTL8373_IO_DUMY_1_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_IO_DUMY_1_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_IO_DUMY_1_DUMMY_REGISTER_OFFSET) + +#define RTL8373_EFUSE_CTRL_DUMY_0_ADDR (0x8094) + #define RTL8373_EFUSE_CTRL_DUMY_0_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_EFUSE_CTRL_DUMY_0_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_EFUSE_CTRL_DUMY_0_DUMMY_REGISTER_OFFSET) + +#define RTL8373_EFUSE_CTRL_DUMY_1_ADDR (0x8098) + #define RTL8373_EFUSE_CTRL_DUMY_1_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_EFUSE_CTRL_DUMY_1_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_EFUSE_CTRL_DUMY_1_DUMMY_REGISTER_OFFSET) + +#define RTL8373_DBG_CTRL_DUMY_0_ADDR (0xC0D4) + #define RTL8373_DBG_CTRL_DUMY_0_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_DBG_CTRL_DUMY_0_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_DBG_CTRL_DUMY_0_DUMMY_REGISTER_OFFSET) + +#define RTL8373_DBG_CTRL_DUMY_1_ADDR (0xC0D8) + #define RTL8373_DBG_CTRL_DUMY_1_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_DBG_CTRL_DUMY_1_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_DBG_CTRL_DUMY_1_DUMMY_REGISTER_OFFSET) + +#define RTL8373_RATE_ADAPTER0_DUMY_0_ADDR (0xE148) + #define RTL8373_RATE_ADAPTER0_DUMY_0_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_RATE_ADAPTER0_DUMY_0_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_RATE_ADAPTER0_DUMY_0_DUMMY_REGISTER_OFFSET) + +#define RTL8373_RATE_ADAPTER0_DUMY_1_ADDR (0xE14C) + #define RTL8373_RATE_ADAPTER0_DUMY_1_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_RATE_ADAPTER0_DUMY_1_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_RATE_ADAPTER0_DUMY_1_DUMMY_REGISTER_OFFSET) + +#define RTL8373_RATE_ADAPTER1_DUMY_0_ADDR (0xE348) + #define RTL8373_RATE_ADAPTER1_DUMY_0_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_RATE_ADAPTER1_DUMY_0_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_RATE_ADAPTER1_DUMY_0_DUMMY_REGISTER_OFFSET) + +#define RTL8373_RATE_ADAPTER1_DUMY_1_ADDR (0xE34C) + #define RTL8373_RATE_ADAPTER1_DUMY_1_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_RATE_ADAPTER1_DUMY_1_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_RATE_ADAPTER1_DUMY_1_DUMMY_REGISTER_OFFSET) + +#define RTL8373_RATE_ADAPTER2_DUMY_0_ADDR (0xE548) + #define RTL8373_RATE_ADAPTER2_DUMY_0_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_RATE_ADAPTER2_DUMY_0_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_RATE_ADAPTER2_DUMY_0_DUMMY_REGISTER_OFFSET) + +#define RTL8373_RATE_ADAPTER2_DUMY_1_ADDR (0xE54C) + #define RTL8373_RATE_ADAPTER2_DUMY_1_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_RATE_ADAPTER2_DUMY_1_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_RATE_ADAPTER2_DUMY_1_DUMMY_REGISTER_OFFSET) + +#define RTL8373_RATE_ADAPTER3_DUMY_0_ADDR (0xE748) + #define RTL8373_RATE_ADAPTER3_DUMY_0_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_RATE_ADAPTER3_DUMY_0_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_RATE_ADAPTER3_DUMY_0_DUMMY_REGISTER_OFFSET) + +#define RTL8373_RATE_ADAPTER3_DUMY_1_ADDR (0xE74C) + #define RTL8373_RATE_ADAPTER3_DUMY_1_DUMMY_REGISTER_OFFSET (0) + #define RTL8373_RATE_ADAPTER3_DUMY_1_DUMMY_REGISTER_MASK (0xFFFFFFFF << RTL8373_RATE_ADAPTER3_DUMY_1_DUMMY_REGISTER_OFFSET) + + +#endif /* __RTL8373_REG_DEFINITION_H__ */ + diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/rtl8373_reg_list.c b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/rtl8373_reg_list.c new file mode 100755 index 00000000..0aaa3a8d --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/rtl8373_reg_list.c @@ -0,0 +1,14429 @@ +/* + * ## Please DO NOT edit this file!! ## + * This file is auto-generated from the register source files. + * Any modifications to this file will be LOST when it is re-generated. + * + * ---------------------------------------------------------------- + * (C) Copyright 2009-2016 Realtek Semiconductor Corp. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * ---------------------------------------------------------------- + * Purpose: chip register definition and structure of RTL8373 + * + * ---------------------------------------------------------------- + */ + +#include "rtl8373_reg_definition.h" +#include "rtl8373_reg_struct.h" +#include "rtl8373_regField_list.h" + +rtk_reg_t rtl8373_reg_list[] = +{ + { /* register name MODEL_NAME_INFO */ + /* offset address */ 0x4, + /* field numbers */ 5, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MODEL_NAME_INFO_FIELDS + }, + { /* register name CHIP_MODE_INFO */ + /* offset address */ 0x8, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ CHIP_MODE_INFO_FIELDS + }, + { /* register name CHIP_INFO */ + /* offset address */ 0xC, + /* field numbers */ 5, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ CHIP_INFO_FIELDS + }, + { /* register name CHIP_UUID_REG */ + /* offset address */ 0x10, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ CHIP_UUID_REG_FIELDS + }, + { /* register name CHIP_LOT_NO_REG0 */ + /* offset address */ 0x14, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ CHIP_LOT_NO_REG0_FIELDS + }, + { /* register name CHIP_LOT_NO_REG1 */ + /* offset address */ 0x18, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ CHIP_LOT_NO_REG1_FIELDS + }, + { /* register name SMI_MMD_SP */ + /* offset address */ 0x1C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SMI_MMD_SP_FIELDS + }, + { /* register name CFG_DMY_CHIP_INFO_1 */ + /* offset address */ 0x20, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ CFG_DMY_CHIP_INFO_1_FIELDS + }, + { /* register name RST_GLB_CTRL_0 */ + /* offset address */ 0x24, + /* field numbers */ 10, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RST_GLB_CTRL_0_FIELDS + }, + { /* register name RST_GLB_DBG_0 */ + /* offset address */ 0x28, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RST_GLB_DBG_0_FIELDS + }, + { /* register name RST_GLB_DBG_1 */ + /* offset address */ 0x2C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RST_GLB_DBG_1_FIELDS + }, + { /* register name MAC_BIST_MODE */ + /* offset address */ 0xF90, + /* field numbers */ 9, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MAC_BIST_MODE_FIELDS + }, + { /* register name MAC_DRF_BIST_MODE */ + /* offset address */ 0xF94, + /* field numbers */ 9, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MAC_DRF_BIST_MODE_FIELDS + }, + { /* register name MAC_BIST_RSTN */ + /* offset address */ 0xF98, + /* field numbers */ 9, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MAC_BIST_RSTN_FIELDS + }, + { /* register name MAC_BIST_LOOP_MODE */ + /* offset address */ 0xF9C, + /* field numbers */ 9, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MAC_BIST_LOOP_MODE_FIELDS + }, + { /* register name MAC_BIST_DYN_READ_EN */ + /* offset address */ 0xFA0, + /* field numbers */ 9, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MAC_BIST_DYN_READ_EN_FIELDS + }, + { /* register name MAC_DRF_TEST_RESUME */ + /* offset address */ 0xFA4, + /* field numbers */ 9, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MAC_DRF_TEST_RESUME_FIELDS + }, + { /* register name MAC_DRF_START_PAUSE */ + /* offset address */ 0xFA8, + /* field numbers */ 9, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MAC_DRF_START_PAUSE_FIELDS + }, + { /* register name MAC_MBIST_DONE */ + /* offset address */ 0xFAC, + /* field numbers */ 9, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MAC_MBIST_DONE_FIELDS + }, + { /* register name MAC_MBIST_DRF_DONE */ + /* offset address */ 0xFB0, + /* field numbers */ 9, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MAC_MBIST_DRF_DONE_FIELDS + }, + { /* register name MAC_MBIST_FAIL_PG00_PG01 */ + /* offset address */ 0xFB4, + /* field numbers */ 5, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MAC_MBIST_FAIL_PG00_PG01_FIELDS + }, + { /* register name MAC_MBIST_FAIL_PG02_PG03 */ + /* offset address */ 0xFB8, + /* field numbers */ 5, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MAC_MBIST_FAIL_PG02_PG03_FIELDS + }, + { /* register name MAC_MBIST_DRF_FAIL_PG00_PG01 */ + /* offset address */ 0xFBC, + /* field numbers */ 5, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MAC_MBIST_DRF_FAIL_PG00_PG01_FIELDS + }, + { /* register name MAC_MBIST_DRF_FAIL_PG02_PG03 */ + /* offset address */ 0xFC0, + /* field numbers */ 5, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MAC_MBIST_DRF_FAIL_PG02_PG03_FIELDS + }, + { /* register name MAC_RXFIFO_LS */ + /* offset address */ 0xFC4, + /* field numbers */ 5, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MAC_RXFIFO_LS_FIELDS + }, + { /* register name MAC_RXFIFO_RMEA */ + /* offset address */ 0xFC8, + /* field numbers */ 5, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MAC_RXFIFO_RMEA_FIELDS + }, + { /* register name MAC_RXFIFO_RMA_PG00 */ + /* offset address */ 0xFCC, + /* field numbers */ 8, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MAC_RXFIFO_RMA_PG00_FIELDS + }, + { /* register name MAC_RXFIFO_RMA_PG01 */ + /* offset address */ 0xFD0, + /* field numbers */ 8, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MAC_RXFIFO_RMA_PG01_FIELDS + }, + { /* register name MAC_RXFIFO_RMA_PG02 */ + /* offset address */ 0xFD4, + /* field numbers */ 7, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MAC_RXFIFO_RMA_PG02_FIELDS + }, + { /* register name MAC_RXFIFO_RMA_PG03 */ + /* offset address */ 0xFD8, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MAC_RXFIFO_RMA_PG03_FIELDS + }, + { /* register name MAC_RXFIFO_RMEB */ + /* offset address */ 0xFDC, + /* field numbers */ 5, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MAC_RXFIFO_RMEB_FIELDS + }, + { /* register name MAC_RXFIFO_RMB_PG00 */ + /* offset address */ 0xFE0, + /* field numbers */ 8, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MAC_RXFIFO_RMB_PG00_FIELDS + }, + { /* register name MAC_RXFIFO_RMB_PG01 */ + /* offset address */ 0xFE4, + /* field numbers */ 8, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MAC_RXFIFO_RMB_PG01_FIELDS + }, + { /* register name MAC_RXFIFO_RMB_PG02 */ + /* offset address */ 0xFE8, + /* field numbers */ 7, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MAC_RXFIFO_RMB_PG02_FIELDS + }, + { /* register name MAC_RXFIFO_RMB_PG03 */ + /* offset address */ 0xFEC, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MAC_RXFIFO_RMB_PG03_FIELDS + }, + { /* register name MAC_TXFIFO_LS */ + /* offset address */ 0xFF0, + /* field numbers */ 5, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MAC_TXFIFO_LS_FIELDS + }, + { /* register name MAC_TXFIFO_RMEA */ + /* offset address */ 0xFF4, + /* field numbers */ 5, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MAC_TXFIFO_RMEA_FIELDS + }, + { /* register name MAC_TXFIFO_RMA_PG00 */ + /* offset address */ 0xFF8, + /* field numbers */ 7, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MAC_TXFIFO_RMA_PG00_FIELDS + }, + { /* register name MAC_TXFIFO_RMA_PG01 */ + /* offset address */ 0xFFC, + /* field numbers */ 5, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MAC_TXFIFO_RMA_PG01_FIELDS + }, + { /* register name MAC_TXFIFO_RMA_PG02 */ + /* offset address */ 0x1000, + /* field numbers */ 7, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MAC_TXFIFO_RMA_PG02_FIELDS + }, + { /* register name MAC_TXFIFO_RMA_PG03 */ + /* offset address */ 0x1004, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MAC_TXFIFO_RMA_PG03_FIELDS + }, + { /* register name MAC_TXFIFO_RMEB */ + /* offset address */ 0x1008, + /* field numbers */ 5, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MAC_TXFIFO_RMEB_FIELDS + }, + { /* register name MAC_TXFIFO_RMB_PG00 */ + /* offset address */ 0x100C, + /* field numbers */ 7, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MAC_TXFIFO_RMB_PG00_FIELDS + }, + { /* register name MAC_TXFIFO_RMB_PG01 */ + /* offset address */ 0x1010, + /* field numbers */ 5, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MAC_TXFIFO_RMB_PG01_FIELDS + }, + { /* register name MAC_TXFIFO_RMB_PG02 */ + /* offset address */ 0x1014, + /* field numbers */ 7, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MAC_TXFIFO_RMB_PG02_FIELDS + }, + { /* register name MAC_TXFIFO_RMB_PG03 */ + /* offset address */ 0x1018, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MAC_TXFIFO_RMB_PG03_FIELDS + }, + { /* register name CHIP_ALL_RESULT */ + /* offset address */ 0x7A20, + /* field numbers */ 5, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ CHIP_ALL_RESULT_FIELDS + }, + { /* register name CHIP_BISR_CTRL */ + /* offset address */ 0x7A24, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ CHIP_BISR_CTRL_FIELDS + }, + { /* register name GLB_MBISD_DATA */ + /* offset address */ 0x7A28, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ GLB_MBISD_DATA_FIELDS + }, + { /* register name GLB_MBISD_CFG */ + /* offset address */ 0x7A2C, + /* field numbers */ 5, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ GLB_MBISD_CFG_FIELDS + }, + { /* register name INGR_BIST_CTRL0 */ + /* offset address */ 0x7520, + /* field numbers */ 6, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ INGR_BIST_CTRL0_FIELDS + }, + { /* register name INGR_BIST_CTRL1 */ + /* offset address */ 0x7524, + /* field numbers */ 6, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ INGR_BIST_CTRL1_FIELDS + }, + { /* register name INGR_BIST_CTRL2 */ + /* offset address */ 0x7528, + /* field numbers */ 6, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ INGR_BIST_CTRL2_FIELDS + }, + { /* register name INGR_BIST_CTRL3 */ + /* offset address */ 0x752C, + /* field numbers */ 6, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ INGR_BIST_CTRL3_FIELDS + }, + { /* register name INGR_BIST_CTRL4 */ + /* offset address */ 0x7530, + /* field numbers */ 6, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ INGR_BIST_CTRL4_FIELDS + }, + { /* register name INGR_BIST_CTRL5 */ + /* offset address */ 0x7534, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ INGR_BIST_CTRL5_FIELDS + }, + { /* register name INGR_BIST_CTRL6 */ + /* offset address */ 0x7538, + /* field numbers */ 6, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ INGR_BIST_CTRL6_FIELDS + }, + { /* register name INGR_BIST_RSLT0 */ + /* offset address */ 0x753C, + /* field numbers */ 6, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ INGR_BIST_RSLT0_FIELDS + }, + { /* register name INGR_BIST_RSLT1 */ + /* offset address */ 0x7540, + /* field numbers */ 6, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ INGR_BIST_RSLT1_FIELDS + }, + { /* register name INGR_BIST_RSLT2 */ + /* offset address */ 0x7544, + /* field numbers */ 6, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ INGR_BIST_RSLT2_FIELDS + }, + { /* register name INGR_BIST_RSLT3 */ + /* offset address */ 0x7548, + /* field numbers */ 5, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ INGR_BIST_RSLT3_FIELDS + }, + { /* register name INGR_BIST_RSLT4 */ + /* offset address */ 0x754C, + /* field numbers */ 5, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ INGR_BIST_RSLT4_FIELDS + }, + { /* register name INGR_SRAM_CTRL_0 */ + /* offset address */ 0x7550, + /* field numbers */ 9, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ INGR_SRAM_CTRL_0_FIELDS + }, + { /* register name INGR_SRAM_CTRL_1 */ + /* offset address */ 0x7554, + /* field numbers */ 13, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ INGR_SRAM_CTRL_1_FIELDS + }, + { /* register name INGR_BISR_CTRL */ + /* offset address */ 0x7558, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ INGR_BISR_CTRL_FIELDS + }, + { /* register name INGR_BISR_RSLT0 */ + /* offset address */ 0x755C, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ INGR_BISR_RSLT0_FIELDS + }, + { /* register name INGR_BISR_RSLT1 */ + /* offset address */ 0x7560, + /* field numbers */ 6, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ INGR_BISR_RSLT1_FIELDS + }, + { /* register name INGR_BISR_RSLT2 */ + /* offset address */ 0x7564, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ INGR_BISR_RSLT2_FIELDS + }, + { /* register name INGR_BISR_RSLT3 */ + /* offset address */ 0x7568, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ INGR_BISR_RSLT3_FIELDS + }, + { /* register name EGR_BIST_CTRL0 */ + /* offset address */ 0x4410, + /* field numbers */ 8, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ EGR_BIST_CTRL0_FIELDS + }, + { /* register name EGR_BIST_CTRL1 */ + /* offset address */ 0x4414, + /* field numbers */ 8, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ EGR_BIST_CTRL1_FIELDS + }, + { /* register name EGR_BIST_CTRL2 */ + /* offset address */ 0x4418, + /* field numbers */ 8, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ EGR_BIST_CTRL2_FIELDS + }, + { /* register name EGR_SRAM_CTRL3 */ + /* offset address */ 0x441C, + /* field numbers */ 8, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ EGR_SRAM_CTRL3_FIELDS + }, + { /* register name EGR_BIST_CTRL4 */ + /* offset address */ 0x4420, + /* field numbers */ 8, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ EGR_BIST_CTRL4_FIELDS + }, + { /* register name EGR_BIST_CTRL5 */ + /* offset address */ 0x4424, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ EGR_BIST_CTRL5_FIELDS + }, + { /* register name EGR_BIST_RSLT0 */ + /* offset address */ 0x4428, + /* field numbers */ 8, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ EGR_BIST_RSLT0_FIELDS + }, + { /* register name EGR_BIST_RSLT1 */ + /* offset address */ 0x442C, + /* field numbers */ 8, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ EGR_BIST_RSLT1_FIELDS + }, + { /* register name EGR_BIST_RSLT2 */ + /* offset address */ 0x4430, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ EGR_BIST_RSLT2_FIELDS + }, + { /* register name NIC_BIST_CTRL0 */ + /* offset address */ 0x7820, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ NIC_BIST_CTRL0_FIELDS + }, + { /* register name NIC_BIST_CTRL1 */ + /* offset address */ 0x7824, + /* field numbers */ 10, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ NIC_BIST_CTRL1_FIELDS + }, + { /* register name NIC_BIST_CTRL2 */ + /* offset address */ 0x7828, + /* field numbers */ 11, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ NIC_BIST_CTRL2_FIELDS + }, + { /* register name NIC_BIST_CTRL3 */ + /* offset address */ 0x782C, + /* field numbers */ 10, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ NIC_BIST_CTRL3_FIELDS + }, + { /* register name NIC_BIST_CTRL4 */ + /* offset address */ 0x7830, + /* field numbers */ 10, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ NIC_BIST_CTRL4_FIELDS + }, + { /* register name NIC_BIST_CTRL5 */ + /* offset address */ 0x7834, + /* field numbers */ 10, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ NIC_BIST_CTRL5_FIELDS + }, + { /* register name NIC_BIST_RSLT0 */ + /* offset address */ 0x7838, + /* field numbers */ 5, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ NIC_BIST_RSLT0_FIELDS + }, + { /* register name NIC_BIST_RSLT1 */ + /* offset address */ 0x783C, + /* field numbers */ 10, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ NIC_BIST_RSLT1_FIELDS + }, + { /* register name NIC_BIST_RSLT2 */ + /* offset address */ 0x7840, + /* field numbers */ 10, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ NIC_BIST_RSLT2_FIELDS + }, + { /* register name SPI_BIST_CTRL */ + /* offset address */ 0x3F0, + /* field numbers */ 11, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SPI_BIST_CTRL_FIELDS + }, + { /* register name SPI_BIST_RSLT */ + /* offset address */ 0x3F4, + /* field numbers */ 6, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SPI_BIST_RSLT_FIELDS + }, + { /* register name ALE_MEM_CFG_0 */ + /* offset address */ 0x5C70, + /* field numbers */ 9, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ ALE_MEM_CFG_0_FIELDS + }, + { /* register name ALE_MEM_CFG_1 */ + /* offset address */ 0x5C74, + /* field numbers */ 8, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ ALE_MEM_CFG_1_FIELDS + }, + { /* register name ALE_CAM_CFG */ + /* offset address */ 0x5C78, + /* field numbers */ 10, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ ALE_CAM_CFG_FIELDS + }, + { /* register name ALE_BIST_LOOP_EN */ + /* offset address */ 0x5C7C, + /* field numbers */ 7, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ ALE_BIST_LOOP_EN_FIELDS + }, + { /* register name ALE_BIST_DYN_READ_EN */ + /* offset address */ 0x5C80, + /* field numbers */ 7, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ ALE_BIST_DYN_READ_EN_FIELDS + }, + { /* register name ALE_BIST_GRP_EN */ + /* offset address */ 0x5C84, + /* field numbers */ 7, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ ALE_BIST_GRP_EN_FIELDS + }, + { /* register name ALE_BIST_RSTN */ + /* offset address */ 0x5C88, + /* field numbers */ 7, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ ALE_BIST_RSTN_FIELDS + }, + { /* register name ALE_BIST_MODE */ + /* offset address */ 0x5C8C, + /* field numbers */ 7, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ ALE_BIST_MODE_FIELDS + }, + { /* register name ALE_BIST_DONE */ + /* offset address */ 0x5C90, + /* field numbers */ 7, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ ALE_BIST_DONE_FIELDS + }, + { /* register name ALE_BIST_FAIL */ + /* offset address */ 0x5C94, + /* field numbers */ 7, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ ALE_BIST_FAIL_FIELDS + }, + { /* register name ALE_DRF_MODE */ + /* offset address */ 0x5C98, + /* field numbers */ 7, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ ALE_DRF_MODE_FIELDS + }, + { /* register name ALE_DRF_PAUSE */ + /* offset address */ 0x5C9C, + /* field numbers */ 7, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ ALE_DRF_PAUSE_FIELDS + }, + { /* register name ALE_DRF_RESUME */ + /* offset address */ 0x5CA0, + /* field numbers */ 7, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ ALE_DRF_RESUME_FIELDS + }, + { /* register name ALE_DRF_DONE */ + /* offset address */ 0x5CA4, + /* field numbers */ 7, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ ALE_DRF_DONE_FIELDS + }, + { /* register name ALE_DRF_FAIL */ + /* offset address */ 0x5CA8, + /* field numbers */ 7, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ ALE_DRF_FAIL_FIELDS + }, + { /* register name PAR_MEM_CFG_0 */ + /* offset address */ 0x6F20, + /* field numbers */ 8, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PAR_MEM_CFG_0_FIELDS + }, + { /* register name PAR_MEM_CFG_1 */ + /* offset address */ 0x6F24, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PAR_MEM_CFG_1_FIELDS + }, + { /* register name PAR_MEM_CFG_2 */ + /* offset address */ 0x6F28, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PAR_MEM_CFG_2_FIELDS + }, + { /* register name PAR_MEM_CFG_3 */ + /* offset address */ 0x6F2C, + /* field numbers */ 6, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PAR_MEM_CFG_3_FIELDS + }, + { /* register name PAR_BIST_RESET_RESUME */ + /* offset address */ 0x6F30, + /* field numbers */ 6, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PAR_BIST_RESET_RESUME_FIELDS + }, + { /* register name PAR_BIST_MODE_DRFMODE */ + /* offset address */ 0x6F34, + /* field numbers */ 6, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PAR_BIST_MODE_DRFMODE_FIELDS + }, + { /* register name PAR_BIST_VDDR_LOOP */ + /* offset address */ 0x6F38, + /* field numbers */ 6, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PAR_BIST_VDDR_LOOP_FIELDS + }, + { /* register name PAR_BIST_START_PAUSE */ + /* offset address */ 0x6F3C, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PAR_BIST_START_PAUSE_FIELDS + }, + { /* register name PAR_BIST_DONE_DRFDONE */ + /* offset address */ 0x6F40, + /* field numbers */ 6, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PAR_BIST_DONE_DRFDONE_FIELDS + }, + { /* register name PAR_BIST_FAIL_DRFFAIL */ + /* offset address */ 0x6F44, + /* field numbers */ 6, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PAR_BIST_FAIL_DRFFAIL_FIELDS + }, + { /* register name PAR_BIST_CTRL_0 */ + /* offset address */ 0x6F48, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PAR_BIST_CTRL_0_FIELDS + }, + { /* register name MBIST_CTRL */ + /* offset address */ 0xF40, + /* field numbers */ 11, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MBIST_CTRL_FIELDS + }, + { /* register name MBIST_RSLT */ + /* offset address */ 0xF44, + /* field numbers */ 6, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MBIST_RSLT_FIELDS + }, + { /* register name BOND_INFO */ + /* offset address */ 0x7F60, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ BOND_INFO_FIELDS + }, + { /* register name STRAP_INFO_0 */ + /* offset address */ 0x7F64, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ STRAP_INFO_0_FIELDS + }, + { /* register name IO_DRVING_0 */ + /* offset address */ 0x7F68, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ IO_DRVING_0_FIELDS + }, + { /* register name IO_DRVING_1 */ + /* offset address */ 0x7F6C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ IO_DRVING_1_FIELDS + }, + { /* register name IO_DRVING_2 */ + /* offset address */ 0x7F70, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ IO_DRVING_2_FIELDS + }, + { /* register name IO_SLEW_0 */ + /* offset address */ 0x7F74, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ IO_SLEW_0_FIELDS + }, + { /* register name IO_SLEW_1 */ + /* offset address */ 0x7F78, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ IO_SLEW_1_FIELDS + }, + { /* register name IO_SLEW_2 */ + /* offset address */ 0x7F7C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ IO_SLEW_2_FIELDS + }, + { /* register name IO_SMT_EN_0 */ + /* offset address */ 0x7F80, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ IO_SMT_EN_0_FIELDS + }, + { /* register name IO_SMT_EN_1 */ + /* offset address */ 0x7F84, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ IO_SMT_EN_1_FIELDS + }, + { /* register name IO_SMT_EN_2 */ + /* offset address */ 0x7F88, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ IO_SMT_EN_2_FIELDS + }, + { /* register name IO_MUX_SEL_0 */ + /* offset address */ 0x7F8C, + /* field numbers */ 32, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ IO_MUX_SEL_0_FIELDS + }, + { /* register name IO_MUX_SEL_1 */ + /* offset address */ 0x7F90, + /* field numbers */ 31, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ IO_MUX_SEL_1_FIELDS + }, + { /* register name IO_MUX_SEL_2 */ + /* offset address */ 0x7F94, + /* field numbers */ 5, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ IO_MUX_SEL_2_FIELDS + }, + { /* register name IO_MUX_SEL_3 */ + /* offset address */ 0x7F98, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ IO_MUX_SEL_3_FIELDS + }, + { /* register name DBG_MODE */ + /* offset address */ 0x30, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ DBG_MODE_FIELDS + }, + { /* register name DBG_PAD_CTRL */ + /* offset address */ 0x34, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ DBG_PAD_CTRL_FIELDS + }, + { /* register name DBG_CTRL_ADR0 */ + /* offset address */ 0xC0B0, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ DBG_CTRL_ADR0_FIELDS + }, + { /* register name DBG_CTRL_ADR1 */ + /* offset address */ 0xC0B4, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ DBG_CTRL_ADR1_FIELDS + }, + { /* register name DBG_CTRL_ADR2 */ + /* offset address */ 0xC0B8, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ DBG_CTRL_ADR2_FIELDS + }, + { /* register name DBG_CTRL_ADR3 */ + /* offset address */ 0xC0BC, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ DBG_CTRL_ADR3_FIELDS + }, + { /* register name DBG_CTRL_SEL0 */ + /* offset address */ 0xC0C0, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ DBG_CTRL_SEL0_FIELDS + }, + { /* register name DBG_CTRL_SEL1 */ + /* offset address */ 0xC0C4, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ DBG_CTRL_SEL1_FIELDS + }, + { /* register name DBG_CTRL_SEL2 */ + /* offset address */ 0xC0C8, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ DBG_CTRL_SEL2_FIELDS + }, + { /* register name DBG_CTRL_SEL3 */ + /* offset address */ 0xC0CC, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ DBG_CTRL_SEL3_FIELDS + }, + { /* register name DBG_CTRL_VAL */ + /* offset address */ 0xC0D0, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ DBG_CTRL_VAL_FIELDS + }, + { /* register name FORCE_PU_PD_EN_0 */ + /* offset address */ 0x7F9C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ FORCE_PU_PD_EN_0_FIELDS + }, + { /* register name FORCE_PU_PD_EN_1 */ + /* offset address */ 0x7FA0, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ FORCE_PU_PD_EN_1_FIELDS + }, + { /* register name FORCE_PU_0 */ + /* offset address */ 0x7FA4, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ FORCE_PU_0_FIELDS + }, + { /* register name FORCE_PU_1 */ + /* offset address */ 0x7FA8, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ FORCE_PU_1_FIELDS + }, + { /* register name FORCE_PD_0 */ + /* offset address */ 0x7FAC, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ FORCE_PD_0_FIELDS + }, + { /* register name FORCE_PD_1 */ + /* offset address */ 0x7FB0, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ FORCE_PD_1_FIELDS + }, + { /* register name CFG_PAD_MDIO0_DRV_MODE */ + /* offset address */ 0x7FB4, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ CFG_PAD_MDIO0_DRV_MODE_FIELDS + }, + { /* register name VOLT_PROB_CTRL */ + /* offset address */ 0x390, + /* field numbers */ 10, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ VOLT_PROB_CTRL_FIELDS + }, + { /* register name VOLT_PROB_RESULT0 */ + /* offset address */ 0x394, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ VOLT_PROB_RESULT0_FIELDS + }, + { /* register name VOLT_PROB_RESULT1 */ + /* offset address */ 0x398, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ VOLT_PROB_RESULT1_FIELDS + }, + { /* register name CFG_XTAL */ + /* offset address */ 0x38, + /* field numbers */ 6, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ CFG_XTAL_FIELDS + }, + { /* register name CFG_EEE_FLG_DLY */ + /* offset address */ 0x910, + /* field numbers */ 8, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ CFG_EEE_FLG_DLY_FIELDS + }, + { /* register name CFG_PHY_MDI_REVERSE */ + /* offset address */ 0xA90, + /* field numbers */ 9, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ CFG_PHY_MDI_REVERSE_FIELDS + }, + { /* register name CFG_PHY_TX_POLARITY_SWAP */ + /* offset address */ 0xA94, + /* field numbers */ 5, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ CFG_PHY_TX_POLARITY_SWAP_FIELDS + }, + { /* register name CFG_PHY_OCP_TIMEOUT */ + /* offset address */ 0xA98, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ CFG_PHY_OCP_TIMEOUT_FIELDS + }, + { /* register name CFG_PHY_PCSXF_1 */ + /* offset address */ 0xA9C, + /* field numbers */ 5, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ CFG_PHY_PCSXF_1_FIELDS + }, + { /* register name CFG_PHY_PCSXF_2 */ + /* offset address */ 0xAA0, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ CFG_PHY_PCSXF_2_FIELDS + }, + { /* register name CFG_PHY_G2XG_IPG */ + /* offset address */ 0xAA4, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ CFG_PHY_G2XG_IPG_FIELDS + }, + { /* register name CFG_PHY_G2XG_FIFO_THR */ + /* offset address */ 0xAA8, + /* field numbers */ 7, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ CFG_PHY_G2XG_FIFO_THR_FIELDS + }, + { /* register name CFG_PHY_G2XG_AUTORST */ + /* offset address */ 0xAAC, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ CFG_PHY_G2XG_AUTORST_FIELDS + }, + { /* register name CFG_PHY_G2XG_MISC */ + /* offset address */ 0xAB0, + /* field numbers */ 5, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ CFG_PHY_G2XG_MISC_FIELDS + }, + { /* register name CFG_PHY_G2XG_MODULE_RST */ + /* offset address */ 0xAB4, + /* field numbers */ 6, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ CFG_PHY_G2XG_MODULE_RST_FIELDS + }, + { /* register name P0_PHY_G2XG_BCH_ERR_FLAG */ + /* offset address */ 0xAB8, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ P0_PHY_G2XG_BCH_ERR_FLAG_FIELDS + }, + { /* register name P1_PHY_G2XG_BCH_ERR_FLAG */ + /* offset address */ 0xABC, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ P1_PHY_G2XG_BCH_ERR_FLAG_FIELDS + }, + { /* register name P2_PHY_G2XG_BCH_ERR_FLAG */ + /* offset address */ 0xAC0, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ P2_PHY_G2XG_BCH_ERR_FLAG_FIELDS + }, + { /* register name P3_PHY_G2XG_BCH_ERR_FLAG */ + /* offset address */ 0xAC4, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ P3_PHY_G2XG_BCH_ERR_FLAG_FIELDS + }, + { /* register name CFG_PHY_MISC */ + /* offset address */ 0xAC8, + /* field numbers */ 12, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ CFG_PHY_MISC_FIELDS + }, + { /* register name PHY_LINK_FAULT_STS */ + /* offset address */ 0xACC, + /* field numbers */ 5, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PHY_LINK_FAULT_STS_FIELDS + }, + { /* register name CFG_PHY_BRD */ + /* offset address */ 0xAD0, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ CFG_PHY_BRD_FIELDS + }, + { /* register name CFG_PHY_INI */ + /* offset address */ 0xAD4, + /* field numbers */ 6, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ CFG_PHY_INI_FIELDS + }, + { /* register name CFG_PHY_POLL_CMD1 */ + /* offset address */ 0xAD8, + /* field numbers */ 5, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ CFG_PHY_POLL_CMD1_FIELDS + }, + { /* register name CFG_PHY_POLL_CMD2 */ + /* offset address */ 0xADC, + /* field numbers */ 5, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ CFG_PHY_POLL_CMD2_FIELDS + }, + { /* register name CFG_PHY_HOTCMD1_ADR */ + /* offset address */ 0xAE0, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ CFG_PHY_HOTCMD1_ADR_FIELDS + }, + { /* register name CFG_PHY_HOTCMD1_DAT */ + /* offset address */ 0xAE4, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ CFG_PHY_HOTCMD1_DAT_FIELDS + }, + { /* register name P0_XG2XG_IPG_DBG_INFO */ + /* offset address */ 0x914, + /* field numbers */ 5, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ P0_XG2XG_IPG_DBG_INFO_FIELDS + }, + { /* register name P0_XG2XG_PRMB_DBG_INFO */ + /* offset address */ 0x918, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ P0_XG2XG_PRMB_DBG_INFO_FIELDS + }, + { /* register name P0_XG2XG_THR_DBG_INFO */ + /* offset address */ 0x91C, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ P0_XG2XG_THR_DBG_INFO_FIELDS + }, + { /* register name CFG_PHY_POLL_ADR0 */ + /* offset address */ 0xAE8, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ CFG_PHY_POLL_ADR0_FIELDS + }, + { /* register name CFG_PHY_POLL_ADR1 */ + /* offset address */ 0xAEC, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ CFG_PHY_POLL_ADR1_FIELDS + }, + { /* register name CFG_PHY_POLL_ADR2 */ + /* offset address */ 0xAF0, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ CFG_PHY_POLL_ADR2_FIELDS + }, + { /* register name CFG_PHY_POLL_ADR3 */ + /* offset address */ 0xAF4, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ CFG_PHY_POLL_ADR3_FIELDS + }, + { /* register name CFG_PHY_POLL_INV0 */ + /* offset address */ 0xAF8, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ CFG_PHY_POLL_INV0_FIELDS + }, + { /* register name CFG_PHY_POLL_INV1 */ + /* offset address */ 0xAFC, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ CFG_PHY_POLL_INV1_FIELDS + }, + { /* register name CFG_PHY_POLL_INV2 */ + /* offset address */ 0xB00, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ CFG_PHY_POLL_INV2_FIELDS + }, + { /* register name CFG_PHY_POLL_INV3 */ + /* offset address */ 0xB04, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ CFG_PHY_POLL_INV3_FIELDS + }, + { /* register name CFG_PHY_POLL_WD0 */ + /* offset address */ 0xB08, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ CFG_PHY_POLL_WD0_FIELDS + }, + { /* register name CFG_PHY_POLL_WD1 */ + /* offset address */ 0xB0C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ CFG_PHY_POLL_WD1_FIELDS + }, + { /* register name CFG_PHY_POLL_WD2 */ + /* offset address */ 0xB10, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ CFG_PHY_POLL_WD2_FIELDS + }, + { /* register name CFG_PHY_POLL_WD3 */ + /* offset address */ 0xB14, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ CFG_PHY_POLL_WD3_FIELDS + }, + { /* register name PHY_SDET_STATUS */ + /* offset address */ 0xB18, + /* field numbers */ 5, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PHY_SDET_STATUS_FIELDS + }, + { /* register name P0_PHY_POLL_CMD0_RDAT */ + /* offset address */ 0xB1C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ P0_PHY_POLL_CMD0_RDAT_FIELDS + }, + { /* register name P0_PHY_POLL_CMD1_RDAT */ + /* offset address */ 0xB20, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ P0_PHY_POLL_CMD1_RDAT_FIELDS + }, + { /* register name P0_PHY_POLL_CMD2_RDAT */ + /* offset address */ 0xB24, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ P0_PHY_POLL_CMD2_RDAT_FIELDS + }, + { /* register name P0_PHY_POLL_CMD3_RDAT */ + /* offset address */ 0xB28, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ P0_PHY_POLL_CMD3_RDAT_FIELDS + }, + { /* register name P1_PHY_POLL_CMD0_RDAT */ + /* offset address */ 0xB2C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ P1_PHY_POLL_CMD0_RDAT_FIELDS + }, + { /* register name P1_PHY_POLL_CMD1_RDAT */ + /* offset address */ 0xB30, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ P1_PHY_POLL_CMD1_RDAT_FIELDS + }, + { /* register name P1_PHY_POLL_CMD2_RDAT */ + /* offset address */ 0xB34, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ P1_PHY_POLL_CMD2_RDAT_FIELDS + }, + { /* register name P1_PHY_POLL_CMD3_RDAT */ + /* offset address */ 0xB38, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ P1_PHY_POLL_CMD3_RDAT_FIELDS + }, + { /* register name P2_PHY_POLL_CMD0_RDAT */ + /* offset address */ 0xB3C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ P2_PHY_POLL_CMD0_RDAT_FIELDS + }, + { /* register name P2_PHY_POLL_CMD1_RDAT */ + /* offset address */ 0xB40, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ P2_PHY_POLL_CMD1_RDAT_FIELDS + }, + { /* register name P2_PHY_POLL_CMD2_RDAT */ + /* offset address */ 0xB44, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ P2_PHY_POLL_CMD2_RDAT_FIELDS + }, + { /* register name P2_PHY_POLL_CMD3_RDAT */ + /* offset address */ 0xB48, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ P2_PHY_POLL_CMD3_RDAT_FIELDS + }, + { /* register name P3_PHY_POLL_CMD0_RDAT */ + /* offset address */ 0xB4C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ P3_PHY_POLL_CMD0_RDAT_FIELDS + }, + { /* register name P3_PHY_POLL_CMD1_RDAT */ + /* offset address */ 0xB50, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ P3_PHY_POLL_CMD1_RDAT_FIELDS + }, + { /* register name P3_PHY_POLL_CMD2_RDAT */ + /* offset address */ 0xB54, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ P3_PHY_POLL_CMD2_RDAT_FIELDS + }, + { /* register name P3_PHY_POLL_CMD3_RDAT */ + /* offset address */ 0xB58, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ P3_PHY_POLL_CMD3_RDAT_FIELDS + }, + { /* register name PHY_ABLTY_RESOLUTION_FRC_MODE */ + /* offset address */ 0xB5C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PHY_ABLTY_RESOLUTION_FRC_MODE_FIELDS + }, + { /* register name P0_PHY_ABLTY_RESOLUTION_FORCE */ + /* offset address */ 0xB60, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ P0_PHY_ABLTY_RESOLUTION_FORCE_FIELDS + }, + { /* register name P1_PHY_ABLTY_RESOLUTION_FORCE */ + /* offset address */ 0xB64, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ P1_PHY_ABLTY_RESOLUTION_FORCE_FIELDS + }, + { /* register name P2_PHY_ABLTY_RESOLUTION_FORCE */ + /* offset address */ 0xB68, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ P2_PHY_ABLTY_RESOLUTION_FORCE_FIELDS + }, + { /* register name P3_PHY_ABLTY_RESOLUTION_FORCE */ + /* offset address */ 0xB6C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ P3_PHY_ABLTY_RESOLUTION_FORCE_FIELDS + }, + { /* register name POWCTRL_ADR */ + /* offset address */ 0xB70, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ POWCTRL_ADR_FIELDS + }, + { /* register name POWCTRL1_BIT */ + /* offset address */ 0xB74, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ POWCTRL1_BIT_FIELDS + }, + { /* register name POWCTRL0_BIT */ + /* offset address */ 0xB78, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ POWCTRL0_BIT_FIELDS + }, + { /* register name RS_LAYER_CONFIG */ + /* offset address */ 0xB7C, + /* field numbers */ 9, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RS_LAYER_CONFIG_FIELDS + }, + { /* register name PHY0_RD_PCS_ABILITY */ + /* offset address */ 0xB80, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PHY0_RD_PCS_ABILITY_FIELDS + }, + { /* register name PHY1_RD_PCS_ABILITY */ + /* offset address */ 0xB84, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PHY1_RD_PCS_ABILITY_FIELDS + }, + { /* register name PHY2_RD_PCS_ABILITY */ + /* offset address */ 0xB88, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PHY2_RD_PCS_ABILITY_FIELDS + }, + { /* register name PHY3_RD_PCS_ABILITY */ + /* offset address */ 0xB8C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PHY3_RD_PCS_ABILITY_FIELDS + }, + { /* register name CFG_PHY_XG2G_G_MISC */ + /* offset address */ 0xB90, + /* field numbers */ 13, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ CFG_PHY_XG2G_G_MISC_FIELDS + }, + { /* register name P1_XG2XG_IPG_DBG_INFO */ + /* offset address */ 0x920, + /* field numbers */ 5, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ P1_XG2XG_IPG_DBG_INFO_FIELDS + }, + { /* register name P1_XG2XG_PRMB_DBG_INFO */ + /* offset address */ 0x924, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ P1_XG2XG_PRMB_DBG_INFO_FIELDS + }, + { /* register name P1_XG2XG_THR_DBG_INFO */ + /* offset address */ 0x928, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ P1_XG2XG_THR_DBG_INFO_FIELDS + }, + { /* register name RANDOM_UPD_PERIOD */ + /* offset address */ 0xE90, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RANDOM_UPD_PERIOD_FIELDS + }, + { /* register name RANDOM_UPD_CTRL */ + /* offset address */ 0xE94, + /* field numbers */ 11, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RANDOM_UPD_CTRL_FIELDS + }, + { /* register name RG_RDM_SEED_SRC_ADDR */ + /* offset address */ 0xE98, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RG_RDM_SEED_SRC_ADDR_FIELDS + }, + { /* register name RING_RATE_REGADDR */ + /* offset address */ 0xE9C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RING_RATE_REGADDR_FIELDS + }, + { /* register name RING_RATE_SEL_MASK_L */ + /* offset address */ 0xEA0, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RING_RATE_SEL_MASK_L_FIELDS + }, + { /* register name RING_RATE_SEL_MASK_H */ + /* offset address */ 0xEA4, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RING_RATE_SEL_MASK_H_FIELDS + }, + { /* register name RING_RATE_FRC_VALUE_H */ + /* offset address */ 0xEA8, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RING_RATE_FRC_VALUE_H_FIELDS + }, + { /* register name RING_RATE_FRC_VALUE_L */ + /* offset address */ 0xEAC, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RING_RATE_FRC_VALUE_L_FIELDS + }, + { /* register name LFSR_INIT_SEED_FRC_VALUE */ + /* offset address */ 0xEB0, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ LFSR_INIT_SEED_FRC_VALUE_FIELDS + }, + { /* register name RING_RATE_RD_VALUE_H */ + /* offset address */ 0xEB4, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RING_RATE_RD_VALUE_H_FIELDS + }, + { /* register name RING_RATE_RD_VALUE_L */ + /* offset address */ 0xEB8, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RING_RATE_RD_VALUE_L_FIELDS + }, + { /* register name LFSR_INIT_SEED_RD_VALUE */ + /* offset address */ 0xEBC, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ LFSR_INIT_SEED_RD_VALUE_FIELDS + }, + { /* register name P0_G2XG_CFG_CLR_ERR_FLAG */ + /* offset address */ 0xB94, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ P0_G2XG_CFG_CLR_ERR_FLAG_FIELDS + }, + { /* register name P1_G2XG_CFG_CLR_ERR_FLAG */ + /* offset address */ 0xB98, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ P1_G2XG_CFG_CLR_ERR_FLAG_FIELDS + }, + { /* register name P2_G2XG_CFG_CLR_ERR_FLAG */ + /* offset address */ 0xB9C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ P2_G2XG_CFG_CLR_ERR_FLAG_FIELDS + }, + { /* register name P3_G2XG_CFG_CLR_ERR_FLAG */ + /* offset address */ 0xBA0, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ P3_G2XG_CFG_CLR_ERR_FLAG_FIELDS + }, + { /* register name G2XG_FIFO_CLR_CFG */ + /* offset address */ 0xBA4, + /* field numbers */ 17, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ G2XG_FIFO_CLR_CFG_FIELDS + }, + { /* register name P2_XG2XG_IPG_DBG_INFO */ + /* offset address */ 0x92C, + /* field numbers */ 5, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ P2_XG2XG_IPG_DBG_INFO_FIELDS + }, + { /* register name P2_XG2XG_PRMB_DBG_INFO */ + /* offset address */ 0x930, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ P2_XG2XG_PRMB_DBG_INFO_FIELDS + }, + { /* register name P2_XG2XG_THR_DBG_INFO */ + /* offset address */ 0x934, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ P2_XG2XG_THR_DBG_INFO_FIELDS + }, + { /* register name G2G_WATER_LEVEL */ + /* offset address */ 0x938, + /* field numbers */ 6, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ G2G_WATER_LEVEL_FIELDS + }, + { /* register name G2G_MISC_CFG */ + /* offset address */ 0x93C, + /* field numbers */ 11, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ G2G_MISC_CFG_FIELDS + }, + { /* register name G2G_ERR_CNT_01 */ + /* offset address */ 0x940, + /* field numbers */ 5, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ G2G_ERR_CNT_01_FIELDS + }, + { /* register name G2G_ERR_CNT_23 */ + /* offset address */ 0x944, + /* field numbers */ 5, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ G2G_ERR_CNT_23_FIELDS + }, + { /* register name XG2XG_WATER_LEVEL */ + /* offset address */ 0x948, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ XG2XG_WATER_LEVEL_FIELDS + }, + { /* register name XG2XG_MISC_CFG */ + /* offset address */ 0x94C, + /* field numbers */ 11, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ XG2XG_MISC_CFG_FIELDS + }, + { /* register name XG2XG_ERR_STATUS */ + /* offset address */ 0x950, + /* field numbers */ 5, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ XG2XG_ERR_STATUS_FIELDS + }, + { /* register name EEE_LPI_DLY_CYCLE */ + /* offset address */ 0x954, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ EEE_LPI_DLY_CYCLE_FIELDS + }, + { /* register name PREAMBLE_RECOVERY_CRTL */ + /* offset address */ 0x958, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PREAMBLE_RECOVERY_CRTL_FIELDS + }, + { /* register name G2G_FIFO_CLR_CFG */ + /* offset address */ 0x95C, + /* field numbers */ 17, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ G2G_FIFO_CLR_CFG_FIELDS + }, + { /* register name XG2XG_FIFO_CLR_CFG */ + /* offset address */ 0x960, + /* field numbers */ 17, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ XG2XG_FIFO_CLR_CFG_FIELDS + }, + { /* register name P3_XG2XG_IPG_DBG_INFO */ + /* offset address */ 0x964, + /* field numbers */ 5, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ P3_XG2XG_IPG_DBG_INFO_FIELDS + }, + { /* register name P3_XG2XG_PRMB_DBG_INFO */ + /* offset address */ 0x968, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ P3_XG2XG_PRMB_DBG_INFO_FIELDS + }, + { /* register name P3_XG2XG_THR_DBG_INFO */ + /* offset address */ 0x96C, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ P3_XG2XG_THR_DBG_INFO_FIELDS + }, + { /* register name SYNCE_CTRL_0 */ + /* offset address */ 0xBA8, + /* field numbers */ 26, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SYNCE_CTRL_0_FIELDS + }, + { /* register name SYNCE_CTRL_1 */ + /* offset address */ 0xBAC, + /* field numbers */ 22, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SYNCE_CTRL_1_FIELDS + }, + { /* register name SYNCE_DUMMY1 */ + /* offset address */ 0xBB0, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SYNCE_DUMMY1_FIELDS + }, + { /* register name SYNCE_DUMMY2 */ + /* offset address */ 0xBB4, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SYNCE_DUMMY2_FIELDS + }, + { /* register name SYNCE_DUMMY3 */ + /* offset address */ 0xBB8, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SYNCE_DUMMY3_FIELDS + }, + { /* register name SYNCE_DUMMY4 */ + /* offset address */ 0xBBC, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SYNCE_DUMMY4_FIELDS + }, + { /* register name SYNCE_DUMMY5 */ + /* offset address */ 0xBC0, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SYNCE_DUMMY5_FIELDS + }, + { /* register name PKTGEN_GLOBAL_CTRL */ + /* offset address */ 0x990, + /* field numbers */ 7, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PKTGEN_GLOBAL_CTRL_FIELDS + }, + { /* register name PKTGEN_PAYLOAD_IND_ACCESS_CTRL */ + /* offset address */ 0x994, + /* field numbers */ 6, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PKTGEN_PAYLOAD_IND_ACCESS_CTRL_FIELDS + }, + { /* register name PKTGEN_G2XG_FIFO_CTRL */ + /* offset address */ 0x998, + /* field numbers */ 8, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PKTGEN_G2XG_FIFO_CTRL_FIELDS + }, + { /* register name PKTGEN0_CTRL0 */ + /* offset address */ 0x99C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PKTGEN0_CTRL0_FIELDS + }, + { /* register name PKTGEN0_CTRL1 */ + /* offset address */ 0x9A0, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PKTGEN0_CTRL1_FIELDS + }, + { /* register name PKTGEN0_CTRL2 */ + /* offset address */ 0x9A4, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PKTGEN0_CTRL2_FIELDS + }, + { /* register name PKTGEN0_CTRL3 */ + /* offset address */ 0x9A8, + /* field numbers */ 5, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PKTGEN0_CTRL3_FIELDS + }, + { /* register name PKTGEN0_CTRL4 */ + /* offset address */ 0x9AC, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PKTGEN0_CTRL4_FIELDS + }, + { /* register name PKTGEN0_CTRL5 */ + /* offset address */ 0x9B0, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PKTGEN0_CTRL5_FIELDS + }, + { /* register name PKTGEN0_CTRL6 */ + /* offset address */ 0x9B4, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PKTGEN0_CTRL6_FIELDS + }, + { /* register name PKTGEN0_CTRL7 */ + /* offset address */ 0x9B8, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PKTGEN0_CTRL7_FIELDS + }, + { /* register name PKTGEN1_CTRL0 */ + /* offset address */ 0x9BC, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PKTGEN1_CTRL0_FIELDS + }, + { /* register name PKTGEN1_CTRL1 */ + /* offset address */ 0x9C0, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PKTGEN1_CTRL1_FIELDS + }, + { /* register name PKTGEN1_CTRL2 */ + /* offset address */ 0x9C4, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PKTGEN1_CTRL2_FIELDS + }, + { /* register name PKTGEN1_CTRL3 */ + /* offset address */ 0x9C8, + /* field numbers */ 5, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PKTGEN1_CTRL3_FIELDS + }, + { /* register name PKTGEN1_CTRL4 */ + /* offset address */ 0x9CC, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PKTGEN1_CTRL4_FIELDS + }, + { /* register name PKTGEN1_CTRL5 */ + /* offset address */ 0x9D0, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PKTGEN1_CTRL5_FIELDS + }, + { /* register name PKTGEN1_CTRL6 */ + /* offset address */ 0x9D4, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PKTGEN1_CTRL6_FIELDS + }, + { /* register name PKTGEN1_CTRL7 */ + /* offset address */ 0x9D8, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PKTGEN1_CTRL7_FIELDS + }, + { /* register name PKTGEN2_CTRL0 */ + /* offset address */ 0x9DC, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PKTGEN2_CTRL0_FIELDS + }, + { /* register name PKTGEN2_CTRL1 */ + /* offset address */ 0x9E0, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PKTGEN2_CTRL1_FIELDS + }, + { /* register name PKTGEN2_CTRL2 */ + /* offset address */ 0x9E4, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PKTGEN2_CTRL2_FIELDS + }, + { /* register name PKTGEN2_CTRL3 */ + /* offset address */ 0x9E8, + /* field numbers */ 5, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PKTGEN2_CTRL3_FIELDS + }, + { /* register name PKTGEN2_CTRL4 */ + /* offset address */ 0x9EC, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PKTGEN2_CTRL4_FIELDS + }, + { /* register name PKTGEN2_CTRL5 */ + /* offset address */ 0x9F0, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PKTGEN2_CTRL5_FIELDS + }, + { /* register name PKTGEN2_CTRL6 */ + /* offset address */ 0x9F4, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PKTGEN2_CTRL6_FIELDS + }, + { /* register name PKTGEN2_CTRL7 */ + /* offset address */ 0x9F8, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PKTGEN2_CTRL7_FIELDS + }, + { /* register name PKTGEN3_CTRL0 */ + /* offset address */ 0x9FC, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PKTGEN3_CTRL0_FIELDS + }, + { /* register name PKTGEN3_CTRL1 */ + /* offset address */ 0xA00, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PKTGEN3_CTRL1_FIELDS + }, + { /* register name PKTGEN3_CTRL2 */ + /* offset address */ 0xA04, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PKTGEN3_CTRL2_FIELDS + }, + { /* register name PKTGEN3_CTRL3 */ + /* offset address */ 0xA08, + /* field numbers */ 5, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PKTGEN3_CTRL3_FIELDS + }, + { /* register name PKTGEN3_CTRL4 */ + /* offset address */ 0xA0C, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PKTGEN3_CTRL4_FIELDS + }, + { /* register name PKTGEN3_CTRL5 */ + /* offset address */ 0xA10, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PKTGEN3_CTRL5_FIELDS + }, + { /* register name PKTGEN3_CTRL6 */ + /* offset address */ 0xA14, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PKTGEN3_CTRL6_FIELDS + }, + { /* register name PKTGEN3_CTRL7 */ + /* offset address */ 0xA18, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PKTGEN3_CTRL7_FIELDS + }, + { /* register name PKTGEN0_CTRL15 */ + /* offset address */ 0xA1C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PKTGEN0_CTRL15_FIELDS + }, + { /* register name PKTGEN1_CTRL15 */ + /* offset address */ 0xA20, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PKTGEN1_CTRL15_FIELDS + }, + { /* register name PKTGEN2_CTRL15 */ + /* offset address */ 0xA24, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PKTGEN2_CTRL15_FIELDS + }, + { /* register name PKTGEN3_CTRL15 */ + /* offset address */ 0xA28, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PKTGEN3_CTRL15_FIELDS + }, + { /* register name PHY_MODEL_ID_REV_CTRL */ + /* offset address */ 0xBC4, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PHY_MODEL_ID_REV_CTRL_FIELDS + }, + { /* register name SDS_MODE_SEL */ + /* offset address */ 0x7B20, + /* field numbers */ 8, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SDS_MODE_SEL_FIELDS + }, + { /* register name SDS_INDACS_CMD */ + /* offset address */ 0x3F8, + /* field numbers */ 7, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SDS_INDACS_CMD_FIELDS + }, + { /* register name SDS_INDACS_RD */ + /* offset address */ 0x3FC, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SDS_INDACS_RD_FIELDS + }, + { /* register name SDS_INDACS_WD */ + /* offset address */ 0x400, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SDS_INDACS_WD_FIELDS + }, + { /* register name SDS0_STATUS */ + /* offset address */ 0x7B24, + /* field numbers */ 6, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SDS0_STATUS_FIELDS + }, + { /* register name SDS0_CH0_RO_ABLTY */ + /* offset address */ 0x7B28, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SDS0_CH0_RO_ABLTY_FIELDS + }, + { /* register name SDS0_CH1_RO_ABLTY */ + /* offset address */ 0x7B2C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SDS0_CH1_RO_ABLTY_FIELDS + }, + { /* register name SDS0_CH2_RO_ABLTY */ + /* offset address */ 0x7B30, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SDS0_CH2_RO_ABLTY_FIELDS + }, + { /* register name SDS0_CH3_3_RO_ABLTY */ + /* offset address */ 0x7B34, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SDS0_CH3_3_RO_ABLTY_FIELDS + }, + { /* register name SDS1_CH0_RO_ABLTY */ + /* offset address */ 0x7B38, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SDS1_CH0_RO_ABLTY_FIELDS + }, + { /* register name SDS0_1_MODE_RO */ + /* offset address */ 0x7B3C, + /* field numbers */ 6, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SDS0_1_MODE_RO_FIELDS + }, + { /* register name CFG_DMY_SDS_0 */ + /* offset address */ 0x7B40, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ CFG_DMY_SDS_0_FIELDS + }, + { /* register name CFG_DMY_SDS_1 */ + /* offset address */ 0x7B44, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ CFG_DMY_SDS_1_FIELDS + }, + { /* register name SDS_OUI */ + /* offset address */ 0x7B48, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SDS_OUI_FIELDS + }, + { /* register name SDS_VERSION */ + /* offset address */ 0x7B4C, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SDS_VERSION_FIELDS + }, + { /* register name SDS_OUI_TGR */ + /* offset address */ 0x7B50, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SDS_OUI_TGR_FIELDS + }, + { /* register name SDS_VERSION_TGR */ + /* offset address */ 0x7B54, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SDS_VERSION_TGR_FIELDS + }, + { /* register name SDS_INTF_CTRL1 */ + /* offset address */ 0x7B58, + /* field numbers */ 18, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 1, + /* register fields */ SDS_INTF_CTRL1_FIELDS + }, + { /* register name SDS_INTF_CTRL2 */ + /* offset address */ 0x7B60, + /* field numbers */ 12, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 1, + /* register fields */ SDS_INTF_CTRL2_FIELDS + }, + { /* register name SDS_INTF_OUT1 */ + /* offset address */ 0x7B68, + /* field numbers */ 11, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 1, + /* register fields */ SDS_INTF_OUT1_FIELDS + }, + { /* register name LED_GLB_CTRL */ + /* offset address */ 0x6520, + /* field numbers */ 12, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ LED_GLB_CTRL_FIELDS + }, + { /* register name LED3_0_SET3_2_CTRL1 */ + /* offset address */ 0x6524, + /* field numbers */ 8, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ LED3_0_SET3_2_CTRL1_FIELDS + }, + { /* register name LED3_0_SET1_0_CTRL1 */ + /* offset address */ 0x6528, + /* field numbers */ 8, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ LED3_0_SET1_0_CTRL1_FIELDS + }, + { /* register name LED3_2_SET3_CTRL0 */ + /* offset address */ 0x652C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ LED3_2_SET3_CTRL0_FIELDS + }, + { /* register name LED1_0_SET3_CTRL0 */ + /* offset address */ 0x6530, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ LED1_0_SET3_CTRL0_FIELDS + }, + { /* register name LED3_2_SET2_CTRL0 */ + /* offset address */ 0x6534, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ LED3_2_SET2_CTRL0_FIELDS + }, + { /* register name LED1_0_SET2_CTRL0 */ + /* offset address */ 0x6538, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ LED1_0_SET2_CTRL0_FIELDS + }, + { /* register name LED3_2_SET1_CTRL0 */ + /* offset address */ 0x653C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ LED3_2_SET1_CTRL0_FIELDS + }, + { /* register name LED1_0_SET1_CTRL0 */ + /* offset address */ 0x6540, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ LED1_0_SET1_CTRL0_FIELDS + }, + { /* register name LED3_2_SET0_CTRL0 */ + /* offset address */ 0x6544, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ LED3_2_SET0_CTRL0_FIELDS + }, + { /* register name LED1_0_SET0_CTRL0 */ + /* offset address */ 0x6548, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ LED1_0_SET0_CTRL0_FIELDS + }, + { /* register name LED_PORT_SET_SEL_CTRL */ + /* offset address */ 0x654C, + /* field numbers */ 1, + /* array offset */ 2, + /* array index */ 0, 0, + /* port index */ 0, 8, + /* register fields */ LED_PORT_SET_SEL_CTRL_FIELDS + }, + { /* register name SW_LED_LOAD */ + /* offset address */ 0x6550, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SW_LED_LOAD_FIELDS + }, + { /* register name LED_PORT_SW_EN_CTRL */ + /* offset address */ 0x6554, + /* field numbers */ 1, + /* array offset */ 4, + /* array index */ 0, 0, + /* port index */ 0, 8, + /* register fields */ LED_PORT_SW_EN_CTRL_FIELDS + }, + { /* register name LED_PORT_SW_CTRL */ + /* offset address */ 0x655C, + /* field numbers */ 5, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 8, + /* register fields */ LED_PORT_SW_CTRL_FIELDS + }, + { /* register name LED_LOAD_LV1_10G */ + /* offset address */ 0x6580, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ LED_LOAD_LV1_10G_FIELDS + }, + { /* register name LED_LOAD_LV2_10G */ + /* offset address */ 0x6584, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ LED_LOAD_LV2_10G_FIELDS + }, + { /* register name LED_LOAD_LV3_10G */ + /* offset address */ 0x6588, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ LED_LOAD_LV3_10G_FIELDS + }, + { /* register name LED_LOAD_LV1_5G */ + /* offset address */ 0x658C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ LED_LOAD_LV1_5G_FIELDS + }, + { /* register name LED_LOAD_LV2_5G */ + /* offset address */ 0x6590, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ LED_LOAD_LV2_5G_FIELDS + }, + { /* register name LED_LOAD_LV3_5G */ + /* offset address */ 0x6594, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ LED_LOAD_LV3_5G_FIELDS + }, + { /* register name LED_LOAD_LV1_2P5G */ + /* offset address */ 0x6598, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ LED_LOAD_LV1_2P5G_FIELDS + }, + { /* register name LED_LOAD_LV2_2P5G */ + /* offset address */ 0x659C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ LED_LOAD_LV2_2P5G_FIELDS + }, + { /* register name LED_LOAD_LV3_2P5G */ + /* offset address */ 0x65A0, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ LED_LOAD_LV3_2P5G_FIELDS + }, + { /* register name LED_LOAD_LV1_1G */ + /* offset address */ 0x65A4, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ LED_LOAD_LV1_1G_FIELDS + }, + { /* register name LED_LOAD_LV2_1G */ + /* offset address */ 0x65A8, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ LED_LOAD_LV2_1G_FIELDS + }, + { /* register name LED_LOAD_LV3_1G */ + /* offset address */ 0x65AC, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ LED_LOAD_LV3_1G_FIELDS + }, + { /* register name LED_LOAD_LV1_500M */ + /* offset address */ 0x65B0, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ LED_LOAD_LV1_500M_FIELDS + }, + { /* register name LED_LOAD_LV2_500M */ + /* offset address */ 0x65B4, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ LED_LOAD_LV2_500M_FIELDS + }, + { /* register name LED_LOAD_LV3_500M */ + /* offset address */ 0x65B8, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ LED_LOAD_LV3_500M_FIELDS + }, + { /* register name LED_LOAD_LV1_100M */ + /* offset address */ 0x65BC, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ LED_LOAD_LV1_100M_FIELDS + }, + { /* register name LED_LOAD_LV2_100M */ + /* offset address */ 0x65C0, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ LED_LOAD_LV2_100M_FIELDS + }, + { /* register name LED_LOAD_LV3_100M */ + /* offset address */ 0x65C4, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ LED_LOAD_LV3_100M_FIELDS + }, + { /* register name LED_LOAD_LV1_10M */ + /* offset address */ 0x65C8, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ LED_LOAD_LV1_10M_FIELDS + }, + { /* register name LED_LOAD_LV2_10M */ + /* offset address */ 0x65CC, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ LED_LOAD_LV2_10M_FIELDS + }, + { /* register name LED_LOAD_LV3_10M */ + /* offset address */ 0x65D0, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ LED_LOAD_LV3_10M_FIELDS + }, + { /* register name LED_P_LOAD_CTRL */ + /* offset address */ 0x65D4, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ LED_P_LOAD_CTRL_FIELDS + }, + { /* register name LED_GLB_ACTIVE */ + /* offset address */ 0x65D8, + /* field numbers */ 31, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ LED_GLB_ACTIVE_FIELDS + }, + { /* register name LED_GLB_IO_EN */ + /* offset address */ 0x65DC, + /* field numbers */ 32, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ LED_GLB_IO_EN_FIELDS + }, + { /* register name LED_GLB_MUX_1 */ + /* offset address */ 0x65E0, + /* field numbers */ 6, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ LED_GLB_MUX_1_FIELDS + }, + { /* register name LED_GLB_MUX_2 */ + /* offset address */ 0x65E4, + /* field numbers */ 6, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ LED_GLB_MUX_2_FIELDS + }, + { /* register name LED_GLB_MUX_3 */ + /* offset address */ 0x65E8, + /* field numbers */ 6, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ LED_GLB_MUX_3_FIELDS + }, + { /* register name LED_GLB_MUX_4 */ + /* offset address */ 0x65EC, + /* field numbers */ 6, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ LED_GLB_MUX_4_FIELDS + }, + { /* register name LED_GLB_MUX_5 */ + /* offset address */ 0x65F0, + /* field numbers */ 6, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ LED_GLB_MUX_5_FIELDS + }, + { /* register name LED_GLB_MUX_6 */ + /* offset address */ 0x65F4, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ LED_GLB_MUX_6_FIELDS + }, + { /* register name LED_RLDP_CTRL_1 */ + /* offset address */ 0x65F8, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ LED_RLDP_CTRL_1_FIELDS + }, + { /* register name LED_RLDP_CTRL_2 */ + /* offset address */ 0x65FC, + /* field numbers */ 8, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ LED_RLDP_CTRL_2_FIELDS + }, + { /* register name LED_RLDP_CTRL_3 */ + /* offset address */ 0x6600, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ LED_RLDP_CTRL_3_FIELDS + }, + { /* register name SPG_GLB_CTRL */ + /* offset address */ 0x4434, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SPG_GLB_CTRL_FIELDS + }, + { /* register name PKB_ACC_DEBUG_CTRL */ + /* offset address */ 0x756C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PKB_ACC_DEBUG_CTRL_FIELDS + }, + { /* register name SPG_PORT_TX_GRP_CTRL */ + /* offset address */ 0x4438, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SPG_PORT_TX_GRP_CTRL_FIELDS + }, + { /* register name SPG_GLOBAL_STS */ + /* offset address */ 0x443C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SPG_GLOBAL_STS_FIELDS + }, + { /* register name SPG_PORT_IBG_CTRL0 */ + /* offset address */ 0x1210, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ SPG_PORT_IBG_CTRL0_FIELDS + }, + { /* register name SPG_PORT_IBG_CTRL1 */ + /* offset address */ 0x1214, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ SPG_PORT_IBG_CTRL1_FIELDS + }, + { /* register name SPG_PORT_IPG_CTRL */ + /* offset address */ 0x1218, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ SPG_PORT_IPG_CTRL_FIELDS + }, + { /* register name SPG_PORT_PKT_CNT_H */ + /* offset address */ 0x1C10, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ SPG_PORT_PKT_CNT_H_FIELDS + }, + { /* register name SPG_PORT_PKT_CNT_L */ + /* offset address */ 0x1C14, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ SPG_PORT_PKT_CNT_L_FIELDS + }, + { /* register name SPG_PORT_PKT_CNT_DBG_H */ + /* offset address */ 0x1C18, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ SPG_PORT_PKT_CNT_DBG_H_FIELDS + }, + { /* register name SPG_PORT_PKT_CNT_DBG_L */ + /* offset address */ 0x1C1C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ SPG_PORT_PKT_CNT_DBG_L_FIELDS + }, + { /* register name SPG_PORT_STREAM0_CTRL0 */ + /* offset address */ 0x1C20, + /* field numbers */ 7, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ SPG_PORT_STREAM0_CTRL0_FIELDS + }, + { /* register name SPG_PORT_STREAM0_CTRL1 */ + /* offset address */ 0x1C24, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ SPG_PORT_STREAM0_CTRL1_FIELDS + }, + { /* register name SPG_PORT_STREAM0_CTRL2 */ + /* offset address */ 0x1C28, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ SPG_PORT_STREAM0_CTRL2_FIELDS + }, + { /* register name SPG_PORT_STREAM0_CTRL3 */ + /* offset address */ 0x1C2C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ SPG_PORT_STREAM0_CTRL3_FIELDS + }, + { /* register name SPG_PB_ACCESS_CTRL0 */ + /* offset address */ 0x7570, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SPG_PB_ACCESS_CTRL0_FIELDS + }, + { /* register name SPG_PB_ACCESS_CTRL1 */ + /* offset address */ 0x7574, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SPG_PB_ACCESS_CTRL1_FIELDS + }, + { /* register name SPG_PB_ACCESS_CTRL2 */ + /* offset address */ 0x7578, + /* field numbers */ 5, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SPG_PB_ACCESS_CTRL2_FIELDS + }, + { /* register name SPG_PORT_INDEX_CTRL0 */ + /* offset address */ 0x1C30, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ SPG_PORT_INDEX_CTRL0_FIELDS + }, + { /* register name SPG_GLOBAL_INDEX_CTRL0 */ + /* offset address */ 0x757C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ SPG_GLOBAL_INDEX_CTRL0_FIELDS + }, + { /* register name SPG_PREAMBLE_LENGTH_CTRL */ + /* offset address */ 0x121C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ SPG_PREAMBLE_LENGTH_CTRL_FIELDS + }, + { /* register name SPG_PREAMBLE_CONTENT_CTRL2 */ + /* offset address */ 0x1220, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ SPG_PREAMBLE_CONTENT_CTRL2_FIELDS + }, + { /* register name SPG_PREAMBLE_CONTENT_CTRL1 */ + /* offset address */ 0x1224, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ SPG_PREAMBLE_CONTENT_CTRL1_FIELDS + }, + { /* register name SPG_PREAMBLE_CONTENT_CTRL0 */ + /* offset address */ 0x1228, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ SPG_PREAMBLE_CONTENT_CTRL0_FIELDS + }, + { /* register name I2C_SLV_CTRL */ + /* offset address */ 0x404, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ I2C_SLV_CTRL_FIELDS + }, + { /* register name MAC_SLV_TIMEOUT */ + /* offset address */ 0x408, + /* field numbers */ 5, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MAC_SLV_TIMEOUT_FIELDS + }, + { /* register name MAC_IF_CTRL */ + /* offset address */ 0x40C, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MAC_IF_CTRL_FIELDS + }, + { /* register name SLV_MDX_CTRL */ + /* offset address */ 0x410, + /* field numbers */ 7, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SLV_MDX_CTRL_FIELDS + }, + { /* register name I2C_MST_IF_CTRL */ + /* offset address */ 0x414, + /* field numbers */ 6, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ I2C_MST_IF_CTRL_FIELDS + }, + { /* register name I2C_MST1_CTRL1 */ + /* offset address */ 0x418, + /* field numbers */ 10, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ I2C_MST1_CTRL1_FIELDS + }, + { /* register name I2C_MST1_CTRL2 */ + /* offset address */ 0x41C, + /* field numbers */ 10, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ I2C_MST1_CTRL2_FIELDS + }, + { /* register name I2C_MST1_MEMADDR_CTRL */ + /* offset address */ 0x420, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ I2C_MST1_MEMADDR_CTRL_FIELDS + }, + { /* register name I2C_MST1_DATA_CTRL */ + /* offset address */ 0x424, + /* field numbers */ 1, + /* array offset */ 8, + /* array index */ 0, 15, + /* port index */ 0, 0, + /* register fields */ I2C_MST1_DATA_CTRL_FIELDS + }, + { /* register name SPI_CTRL0 */ + /* offset address */ 0x434, + /* field numbers */ 10, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SPI_CTRL0_FIELDS + }, + { /* register name SPI_CTRL1 */ + /* offset address */ 0x438, + /* field numbers */ 7, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SPI_CTRL1_FIELDS + }, + { /* register name SPI_DATA */ + /* offset address */ 0x4F0, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 127, + /* port index */ 0, 0, + /* register fields */ SPI_DATA_FIELDS + }, + { /* register name SPI_ADDR */ + /* offset address */ 0x43C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SPI_ADDR_FIELDS + }, + { /* register name GPIO_OUT0 */ + /* offset address */ 0x3C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ GPIO_OUT0_FIELDS + }, + { /* register name GPIO_OUT1 */ + /* offset address */ 0x40, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ GPIO_OUT1_FIELDS + }, + { /* register name GPIO_IN0 */ + /* offset address */ 0x44, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ GPIO_IN0_FIELDS + }, + { /* register name GPIO_IN1 */ + /* offset address */ 0x48, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ GPIO_IN1_FIELDS + }, + { /* register name GPIO_OE0 */ + /* offset address */ 0x4C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ GPIO_OE0_FIELDS + }, + { /* register name GPIO_OE1 */ + /* offset address */ 0x50, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ GPIO_OE1_FIELDS + }, + { /* register name GPIO_IMODE_54_52 */ + /* offset address */ 0x54, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ GPIO_IMODE_54_52_FIELDS + }, + { /* register name INI_MODE */ + /* offset address */ 0x58, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ INI_MODE_FIELDS + }, + { /* register name PWM_CTRL */ + /* offset address */ 0x5C, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PWM_CTRL_FIELDS + }, + { /* register name REGIF_TIMEOUT_INFO */ + /* offset address */ 0x440, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ REGIF_TIMEOUT_INFO_FIELDS + }, + { /* register name TM0_CTRL0 */ + /* offset address */ 0x2D0, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ TM0_CTRL0_FIELDS + }, + { /* register name TM0_CTRL1 */ + /* offset address */ 0x2D4, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ TM0_CTRL1_FIELDS + }, + { /* register name TM0_CTRL2 */ + /* offset address */ 0x2D8, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ TM0_CTRL2_FIELDS + }, + { /* register name TM0_CTRL3 */ + /* offset address */ 0x2DC, + /* field numbers */ 5, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ TM0_CTRL3_FIELDS + }, + { /* register name TM0_RESULT0 */ + /* offset address */ 0x2E0, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ TM0_RESULT0_FIELDS + }, + { /* register name TM0_RESULT1 */ + /* offset address */ 0x2E4, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ TM0_RESULT1_FIELDS + }, + { /* register name TM0_RESULT2 */ + /* offset address */ 0x2E8, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ TM0_RESULT2_FIELDS + }, + { /* register name TM0_RESULT3 */ + /* offset address */ 0x2EC, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ TM0_RESULT3_FIELDS + }, + { /* register name TM0_RESULT4 */ + /* offset address */ 0x2F0, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ TM0_RESULT4_FIELDS + }, + { /* register name TM1_CTRL0 */ + /* offset address */ 0x330, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ TM1_CTRL0_FIELDS + }, + { /* register name TM1_CTRL1 */ + /* offset address */ 0x334, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ TM1_CTRL1_FIELDS + }, + { /* register name TM1_CTRL2 */ + /* offset address */ 0x338, + /* field numbers */ 10, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ TM1_CTRL2_FIELDS + }, + { /* register name TM1_CTRL3 */ + /* offset address */ 0x33C, + /* field numbers */ 5, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ TM1_CTRL3_FIELDS + }, + { /* register name TM1_RESULT0 */ + /* offset address */ 0x340, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ TM1_RESULT0_FIELDS + }, + { /* register name TM1_RESULT1 */ + /* offset address */ 0x344, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ TM1_RESULT1_FIELDS + }, + { /* register name TM1_RESULT2 */ + /* offset address */ 0x348, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ TM1_RESULT2_FIELDS + }, + { /* register name TM1_RESULT3 */ + /* offset address */ 0x34C, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ TM1_RESULT3_FIELDS + }, + { /* register name TM1_RESULT4 */ + /* offset address */ 0x350, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ TM1_RESULT4_FIELDS + }, + { /* register name EFUSE_ACCESS_EN */ + /* offset address */ 0x7FE0, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ EFUSE_ACCESS_EN_FIELDS + }, + { /* register name EFUSE_AUTOLOAD_CTRL */ + /* offset address */ 0x7FE4, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ EFUSE_AUTOLOAD_CTRL_FIELDS + }, + { /* register name EFUSE_ACCESS_CTRL */ + /* offset address */ 0x7FE8, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ EFUSE_ACCESS_CTRL_FIELDS + }, + { /* register name EFUSE_WDATA_CTRL */ + /* offset address */ 0x7FEC, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ EFUSE_WDATA_CTRL_FIELDS + }, + { /* register name EFUSE_RDATA_CTRL */ + /* offset address */ 0x7FF0, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ EFUSE_RDATA_CTRL_FIELDS + }, + { /* register name EFUSE_CP_MISC */ + /* offset address */ 0x7FF4, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ EFUSE_CP_MISC_FIELDS + }, + { /* register name EFUSE_MARGIN_RD_CFG */ + /* offset address */ 0x7FF8, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ EFUSE_MARGIN_RD_CFG_FIELDS + }, + { /* register name EFUSE_MARGIN_RD_ERR_1 */ + /* offset address */ 0x7FFC, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ EFUSE_MARGIN_RD_ERR_1_FIELDS + }, + { /* register name EFUSE_MARGIN_RD_ERR_2 */ + /* offset address */ 0x8000, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ EFUSE_MARGIN_RD_ERR_2_FIELDS + }, + { /* register name EFUSE_FREQ_SEL */ + /* offset address */ 0x8004, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ EFUSE_FREQ_SEL_FIELDS + }, + { /* register name EFUSE_MASS_OPERATION_CFG */ + /* offset address */ 0x8008, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ EFUSE_MASS_OPERATION_CFG_FIELDS + }, + { /* register name EFUSE_MASS_COMP_ERR_1 */ + /* offset address */ 0x800C, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ EFUSE_MASS_COMP_ERR_1_FIELDS + }, + { /* register name EFUSE_MASS_COMP_ERR_2 */ + /* offset address */ 0x8010, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ EFUSE_MASS_COMP_ERR_2_FIELDS + }, + { /* register name EFUSE_MASS_DATA_REG */ + /* offset address */ 0x8014, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 31, + /* port index */ 0, 0, + /* register fields */ EFUSE_MASS_DATA_REG_FIELDS + }, + { /* register name MAC_EEPROM_DOWN_LOAD_FREQ */ + /* offset address */ 0x5F20, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MAC_EEPROM_DOWN_LOAD_FREQ_FIELDS + }, + { /* register name MAC_EEPROM_DOWN_LOAD_STS */ + /* offset address */ 0x5F24, + /* field numbers */ 5, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MAC_EEPROM_DOWN_LOAD_STS_FIELDS + }, + { /* register name EEPROM_VER_INFO */ + /* offset address */ 0x5F28, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ EEPROM_VER_INFO_FIELDS + }, + { /* register name EEPROM_AUTOLOAD_TIMER */ + /* offset address */ 0x5F2C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ EEPROM_AUTOLOAD_TIMER_FIELDS + }, + { /* register name MAC_EEPROM_ADDR_LEN */ + /* offset address */ 0x5F30, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MAC_EEPROM_ADDR_LEN_FIELDS + }, + { /* register name IMR_INT_PORT_LINK_STS_CHG */ + /* offset address */ 0x5F34, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ IMR_INT_PORT_LINK_STS_CHG_FIELDS + }, + { /* register name IMR_INT_GPHY */ + /* offset address */ 0x5F38, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ IMR_INT_GPHY_FIELDS + }, + { /* register name IMR_INT_LEARNOVER */ + /* offset address */ 0x5F3C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ IMR_INT_LEARNOVER_FIELDS + }, + { /* register name IMR_INT_RLFD */ + /* offset address */ 0x5F40, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ IMR_INT_RLFD_FIELDS + }, + { /* register name IMR_INT_WOL */ + /* offset address */ 0x5F44, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ IMR_INT_WOL_FIELDS + }, + { /* register name IMR_INT_SERDES_LINK_FAULT_P */ + /* offset address */ 0x5F48, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ IMR_INT_SERDES_LINK_FAULT_P_FIELDS + }, + { /* register name IMR_INT_SDS_UPD_PHYSTS0 */ + /* offset address */ 0x5F4C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ IMR_INT_SDS_UPD_PHYSTS0_FIELDS + }, + { /* register name IMR_INT_GPIO */ + /* offset address */ 0x5F50, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ IMR_INT_GPIO_FIELDS + }, + { /* register name IMR_INT_MISC */ + /* offset address */ 0x5F54, + /* field numbers */ 18, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ IMR_INT_MISC_FIELDS + }, + { /* register name IMR_EXT_PORT_LINK_STS_CHG */ + /* offset address */ 0x5F58, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ IMR_EXT_PORT_LINK_STS_CHG_FIELDS + }, + { /* register name IMR_EXT_GPHY */ + /* offset address */ 0x5F5C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ IMR_EXT_GPHY_FIELDS + }, + { /* register name IMR_EXT_LEARNOVER */ + /* offset address */ 0x5F60, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ IMR_EXT_LEARNOVER_FIELDS + }, + { /* register name IMR_EXT_RLFD */ + /* offset address */ 0x5F64, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ IMR_EXT_RLFD_FIELDS + }, + { /* register name IMR_EXT_WOL */ + /* offset address */ 0x5F68, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ IMR_EXT_WOL_FIELDS + }, + { /* register name IMR_EXT_SERDES_LINK_FAULT_P */ + /* offset address */ 0x5F6C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ IMR_EXT_SERDES_LINK_FAULT_P_FIELDS + }, + { /* register name IMR_EXT_SDS_UPD_PHYSTS0 */ + /* offset address */ 0x5F70, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ IMR_EXT_SDS_UPD_PHYSTS0_FIELDS + }, + { /* register name IMR_EXT_GPIO */ + /* offset address */ 0x5F74, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ IMR_EXT_GPIO_FIELDS + }, + { /* register name IMR_EXT_MISC */ + /* offset address */ 0x5F78, + /* field numbers */ 16, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ IMR_EXT_MISC_FIELDS + }, + { /* register name ISR_INT_GLB */ + /* offset address */ 0x5F7C, + /* field numbers */ 26, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ ISR_INT_GLB_FIELDS + }, + { /* register name ISR_EXT_GLB */ + /* offset address */ 0x5F80, + /* field numbers */ 28, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ ISR_EXT_GLB_FIELDS + }, + { /* register name ISR_SW_INT_MODE */ + /* offset address */ 0x5F84, + /* field numbers */ 6, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ ISR_SW_INT_MODE_FIELDS + }, + { /* register name ISR_INT_PORT_LINK_STS_CHG */ + /* offset address */ 0x5F88, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ ISR_INT_PORT_LINK_STS_CHG_FIELDS + }, + { /* register name ISR_INT_GPHY */ + /* offset address */ 0x5F8C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ ISR_INT_GPHY_FIELDS + }, + { /* register name ISR_INT_LEARNOVER */ + /* offset address */ 0x5F90, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ ISR_INT_LEARNOVER_FIELDS + }, + { /* register name ISR_INT_TM_RLFD */ + /* offset address */ 0x5F94, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ ISR_INT_TM_RLFD_FIELDS + }, + { /* register name ISR_INT_WOL */ + /* offset address */ 0x5F98, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ ISR_INT_WOL_FIELDS + }, + { /* register name ISR_INT_SERDES_LINK_FAULT_P */ + /* offset address */ 0x5F9C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ ISR_INT_SERDES_LINK_FAULT_P_FIELDS + }, + { /* register name ISR_INT_SDS_UPD_PHYSTS0 */ + /* offset address */ 0x5FA0, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ ISR_INT_SDS_UPD_PHYSTS0_FIELDS + }, + { /* register name ISR_INT_GPIO */ + /* offset address */ 0x5FA4, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ ISR_INT_GPIO_FIELDS + }, + { /* register name ISR_INT_MISC */ + /* offset address */ 0x5FA8, + /* field numbers */ 16, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ ISR_INT_MISC_FIELDS + }, + { /* register name ISR_EXT_PORT_LINK_STS_CHG */ + /* offset address */ 0x5FAC, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ ISR_EXT_PORT_LINK_STS_CHG_FIELDS + }, + { /* register name ISR_EXT_GPHY */ + /* offset address */ 0x5FB0, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ ISR_EXT_GPHY_FIELDS + }, + { /* register name ISR_EXT_LEARNOVER */ + /* offset address */ 0x5FB4, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ ISR_EXT_LEARNOVER_FIELDS + }, + { /* register name ISR_EXT_TM_RLFD */ + /* offset address */ 0x5FB8, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ ISR_EXT_TM_RLFD_FIELDS + }, + { /* register name ISR_EXT_WOL */ + /* offset address */ 0x5FBC, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ ISR_EXT_WOL_FIELDS + }, + { /* register name ISR_EXT_SERDES_LINK_FAULT_P */ + /* offset address */ 0x5FC0, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ ISR_EXT_SERDES_LINK_FAULT_P_FIELDS + }, + { /* register name ISR_EXT_SDS_UPD_PHYSTS0 */ + /* offset address */ 0x5FC4, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ ISR_EXT_SDS_UPD_PHYSTS0_FIELDS + }, + { /* register name ISR_EXT_GPIO */ + /* offset address */ 0x5FC8, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ ISR_EXT_GPIO_FIELDS + }, + { /* register name ISR_EXT_MISC */ + /* offset address */ 0x5FCC, + /* field numbers */ 16, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ ISR_EXT_MISC_FIELDS + }, + { /* register name STAT_RST */ + /* offset address */ 0xF48, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ STAT_RST_FIELDS + }, + { /* register name STAT_PORT_RST */ + /* offset address */ 0xF4C, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ STAT_PORT_RST_FIELDS + }, + { /* register name STAT_CTRL */ + /* offset address */ 0xF50, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ STAT_CTRL_FIELDS + }, + { /* register name STAT_CNT_SET1_CTRL */ + /* offset address */ 0xF54, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ STAT_CNT_SET1_CTRL_FIELDS + }, + { /* register name STAT_CNT_SET0_CTRL */ + /* offset address */ 0xF58, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ STAT_CNT_SET0_CTRL_FIELDS + }, + { /* register name PHY_MIB_GLOBAL_CONFIG */ + /* offset address */ 0x6F0, + /* field numbers */ 6, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PHY_MIB_GLOBAL_CONFIG_FIELDS + }, + { /* register name DEBUG_MIB_RST */ + /* offset address */ 0xF5C, + /* field numbers */ 1, + /* array offset */ 1, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ DEBUG_MIB_RST_FIELDS + }, + { /* register name INDIRECT_ACCESS_CTRL */ + /* offset address */ 0xF60, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ INDIRECT_ACCESS_CTRL_FIELDS + }, + { /* register name INDIRECT_ACCESS_CNT_L */ + /* offset address */ 0xF64, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ INDIRECT_ACCESS_CNT_L_FIELDS + }, + { /* register name INDIRECT_ACCESS_CNT_H */ + /* offset address */ 0xF68, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ INDIRECT_ACCESS_CNT_H_FIELDS + }, + { /* register name PHY0_RX_MIB_CNTR0 */ + /* offset address */ 0x710, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PHY0_RX_MIB_CNTR0_FIELDS + }, + { /* register name PHY0_RX_MIB_CNTR1 */ + /* offset address */ 0x714, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PHY0_RX_MIB_CNTR1_FIELDS + }, + { /* register name PHY0_RX_MIB_CNTR2 */ + /* offset address */ 0x718, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PHY0_RX_MIB_CNTR2_FIELDS + }, + { /* register name PHY0_RX_MIB_CNTR3 */ + /* offset address */ 0x71C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PHY0_RX_MIB_CNTR3_FIELDS + }, + { /* register name PHY0_TX_MIB_CNTR0 */ + /* offset address */ 0x730, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PHY0_TX_MIB_CNTR0_FIELDS + }, + { /* register name PHY0_TX_MIB_CNTR1 */ + /* offset address */ 0x734, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PHY0_TX_MIB_CNTR1_FIELDS + }, + { /* register name PHY0_TX_MIB_CNTR2 */ + /* offset address */ 0x738, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PHY0_TX_MIB_CNTR2_FIELDS + }, + { /* register name PHY0_TX_MIB_CNTR3 */ + /* offset address */ 0x73C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PHY0_TX_MIB_CNTR3_FIELDS + }, + { /* register name PHY1_RX_MIB_CNTR0 */ + /* offset address */ 0x750, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PHY1_RX_MIB_CNTR0_FIELDS + }, + { /* register name PHY1_RX_MIB_CNTR1 */ + /* offset address */ 0x754, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PHY1_RX_MIB_CNTR1_FIELDS + }, + { /* register name PHY1_RX_MIB_CNTR2 */ + /* offset address */ 0x758, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PHY1_RX_MIB_CNTR2_FIELDS + }, + { /* register name PHY1_RX_MIB_CNTR3 */ + /* offset address */ 0x75C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PHY1_RX_MIB_CNTR3_FIELDS + }, + { /* register name PHY1_TX_MIB_CNTR0 */ + /* offset address */ 0x770, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PHY1_TX_MIB_CNTR0_FIELDS + }, + { /* register name PHY1_TX_MIB_CNTR1 */ + /* offset address */ 0x774, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PHY1_TX_MIB_CNTR1_FIELDS + }, + { /* register name PHY1_TX_MIB_CNTR2 */ + /* offset address */ 0x778, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PHY1_TX_MIB_CNTR2_FIELDS + }, + { /* register name PHY1_TX_MIB_CNTR3 */ + /* offset address */ 0x77C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PHY1_TX_MIB_CNTR3_FIELDS + }, + { /* register name PHY2_RX_MIB_CNTR0 */ + /* offset address */ 0x790, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PHY2_RX_MIB_CNTR0_FIELDS + }, + { /* register name PHY2_RX_MIB_CNTR1 */ + /* offset address */ 0x794, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PHY2_RX_MIB_CNTR1_FIELDS + }, + { /* register name PHY2_RX_MIB_CNTR2 */ + /* offset address */ 0x798, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PHY2_RX_MIB_CNTR2_FIELDS + }, + { /* register name PHY2_RX_MIB_CNTR3 */ + /* offset address */ 0x79C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PHY2_RX_MIB_CNTR3_FIELDS + }, + { /* register name PHY2_TX_MIB_CNTR0 */ + /* offset address */ 0x7B0, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PHY2_TX_MIB_CNTR0_FIELDS + }, + { /* register name PHY2_TX_MIB_CNTR1 */ + /* offset address */ 0x7B4, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PHY2_TX_MIB_CNTR1_FIELDS + }, + { /* register name PHY2_TX_MIB_CNTR2 */ + /* offset address */ 0x7B8, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PHY2_TX_MIB_CNTR2_FIELDS + }, + { /* register name PHY2_TX_MIB_CNTR3 */ + /* offset address */ 0x7BC, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PHY2_TX_MIB_CNTR3_FIELDS + }, + { /* register name PHY3_RX_MIB_CNTR0 */ + /* offset address */ 0x7D0, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PHY3_RX_MIB_CNTR0_FIELDS + }, + { /* register name PHY3_RX_MIB_CNTR1 */ + /* offset address */ 0x7D4, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PHY3_RX_MIB_CNTR1_FIELDS + }, + { /* register name PHY3_RX_MIB_CNTR2 */ + /* offset address */ 0x7D8, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PHY3_RX_MIB_CNTR2_FIELDS + }, + { /* register name PHY3_RX_MIB_CNTR3 */ + /* offset address */ 0x7DC, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PHY3_RX_MIB_CNTR3_FIELDS + }, + { /* register name PHY3_TX_MIB_CNTR0 */ + /* offset address */ 0x7F0, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PHY3_TX_MIB_CNTR0_FIELDS + }, + { /* register name PHY3_TX_MIB_CNTR1 */ + /* offset address */ 0x7F4, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PHY3_TX_MIB_CNTR1_FIELDS + }, + { /* register name PHY3_TX_MIB_CNTR2 */ + /* offset address */ 0x7F8, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PHY3_TX_MIB_CNTR2_FIELDS + }, + { /* register name PHY3_TX_MIB_CNTR3 */ + /* offset address */ 0x7FC, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PHY3_TX_MIB_CNTR3_FIELDS + }, + { /* register name SDS_CH0_RX_MIB_CNTR0 */ + /* offset address */ 0x810, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SDS_CH0_RX_MIB_CNTR0_FIELDS + }, + { /* register name SDS_CH0_RX_MIB_CNTR1 */ + /* offset address */ 0x814, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SDS_CH0_RX_MIB_CNTR1_FIELDS + }, + { /* register name SDS_CH0_RX_MIB_CNTR2 */ + /* offset address */ 0x818, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SDS_CH0_RX_MIB_CNTR2_FIELDS + }, + { /* register name SDS_CH0_RX_MIB_CNTR3 */ + /* offset address */ 0x81C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SDS_CH0_RX_MIB_CNTR3_FIELDS + }, + { /* register name SDS_CH0_TX_MIB_CNTR0 */ + /* offset address */ 0x830, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SDS_CH0_TX_MIB_CNTR0_FIELDS + }, + { /* register name SDS_CH0_TX_MIB_CNTR1 */ + /* offset address */ 0x834, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SDS_CH0_TX_MIB_CNTR1_FIELDS + }, + { /* register name SDS_CH0_TX_MIB_CNTR2 */ + /* offset address */ 0x838, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SDS_CH0_TX_MIB_CNTR2_FIELDS + }, + { /* register name SDS_CH0_TX_MIB_CNTR3 */ + /* offset address */ 0x83C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SDS_CH0_TX_MIB_CNTR3_FIELDS + }, + { /* register name SDS_CH1_RX_MIB_CNTR0 */ + /* offset address */ 0x850, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SDS_CH1_RX_MIB_CNTR0_FIELDS + }, + { /* register name SDS_CH1_RX_MIB_CNTR1 */ + /* offset address */ 0x854, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SDS_CH1_RX_MIB_CNTR1_FIELDS + }, + { /* register name SDS_CH1_RX_MIB_CNTR2 */ + /* offset address */ 0x858, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SDS_CH1_RX_MIB_CNTR2_FIELDS + }, + { /* register name SDS_CH1_RX_MIB_CNTR3 */ + /* offset address */ 0x85C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SDS_CH1_RX_MIB_CNTR3_FIELDS + }, + { /* register name SDS_CH1_TX_MIB_CNTR0 */ + /* offset address */ 0x870, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SDS_CH1_TX_MIB_CNTR0_FIELDS + }, + { /* register name SDS_CH1_TX_MIB_CNTR1 */ + /* offset address */ 0x874, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SDS_CH1_TX_MIB_CNTR1_FIELDS + }, + { /* register name SDS_CH1_TX_MIB_CNTR2 */ + /* offset address */ 0x878, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SDS_CH1_TX_MIB_CNTR2_FIELDS + }, + { /* register name SDS_CH1_TX_MIB_CNTR3 */ + /* offset address */ 0x87C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SDS_CH1_TX_MIB_CNTR3_FIELDS + }, + { /* register name SDS_CH2_RX_MIB_CNTR0 */ + /* offset address */ 0x890, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SDS_CH2_RX_MIB_CNTR0_FIELDS + }, + { /* register name SDS_CH2_RX_MIB_CNTR1 */ + /* offset address */ 0x894, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SDS_CH2_RX_MIB_CNTR1_FIELDS + }, + { /* register name SDS_CH2_RX_MIB_CNTR2 */ + /* offset address */ 0x898, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SDS_CH2_RX_MIB_CNTR2_FIELDS + }, + { /* register name SDS_CH2_RX_MIB_CNTR3 */ + /* offset address */ 0x89C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SDS_CH2_RX_MIB_CNTR3_FIELDS + }, + { /* register name SDS_CH2_TX_MIB_CNTR0 */ + /* offset address */ 0x8B0, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SDS_CH2_TX_MIB_CNTR0_FIELDS + }, + { /* register name SDS_CH2_TX_MIB_CNTR1 */ + /* offset address */ 0x8B4, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SDS_CH2_TX_MIB_CNTR1_FIELDS + }, + { /* register name SDS_CH2_TX_MIB_CNTR2 */ + /* offset address */ 0x8B8, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SDS_CH2_TX_MIB_CNTR2_FIELDS + }, + { /* register name SDS_CH2_TX_MIB_CNTR3 */ + /* offset address */ 0x8BC, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SDS_CH2_TX_MIB_CNTR3_FIELDS + }, + { /* register name SDS_CH3_RX_MIB_CNTR0 */ + /* offset address */ 0x8D0, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SDS_CH3_RX_MIB_CNTR0_FIELDS + }, + { /* register name SDS_CH3_RX_MIB_CNTR1 */ + /* offset address */ 0x8D4, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SDS_CH3_RX_MIB_CNTR1_FIELDS + }, + { /* register name SDS_CH3_RX_MIB_CNTR2 */ + /* offset address */ 0x8D8, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SDS_CH3_RX_MIB_CNTR2_FIELDS + }, + { /* register name SDS_CH3_RX_MIB_CNTR3 */ + /* offset address */ 0x8DC, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SDS_CH3_RX_MIB_CNTR3_FIELDS + }, + { /* register name SDS_CH3_TX_MIB_CNTR0 */ + /* offset address */ 0x8F0, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SDS_CH3_TX_MIB_CNTR0_FIELDS + }, + { /* register name SDS_CH3_TX_MIB_CNTR1 */ + /* offset address */ 0x8F4, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SDS_CH3_TX_MIB_CNTR1_FIELDS + }, + { /* register name SDS_CH3_TX_MIB_CNTR2 */ + /* offset address */ 0x8F8, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SDS_CH3_TX_MIB_CNTR2_FIELDS + }, + { /* register name SDS_CH3_TX_MIB_CNTR3 */ + /* offset address */ 0x8FC, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SDS_CH3_TX_MIB_CNTR3_FIELDS + }, + { /* register name DMY_REG0_MIB_DATA */ + /* offset address */ 0xF30, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ DMY_REG0_MIB_DATA_FIELDS + }, + { /* register name DMY_REG1_MIB_DATA */ + /* offset address */ 0xF34, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ DMY_REG1_MIB_DATA_FIELDS + }, + { /* register name DMY_REG2_MIB_DATA */ + /* offset address */ 0xF38, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ DMY_REG2_MIB_DATA_FIELDS + }, + { /* register name DMY_REG3_MIB_DATA */ + /* offset address */ 0xF3C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ DMY_REG3_MIB_DATA_FIELDS + }, + { /* register name MAC_L2_PORT_TX_MAX_LEN_CTRL */ + /* offset address */ 0x4E90, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ MAC_L2_PORT_TX_MAX_LEN_CTRL_FIELDS + }, + { /* register name SMI_BYPASS_ABLTY_LOCK_CTRL */ + /* offset address */ 0x6320, + /* field numbers */ 1, + /* array offset */ 1, + /* array index */ 0, 0, + /* port index */ 0, 8, + /* register fields */ SMI_BYPASS_ABLTY_LOCK_CTRL_FIELDS + }, + { /* register name LINK_DOWN_CTRL */ + /* offset address */ 0x6324, + /* field numbers */ 7, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ LINK_DOWN_CTRL_FIELDS + }, + { /* register name MAC_GLB_CTRL */ + /* offset address */ 0x5FD0, + /* field numbers */ 13, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MAC_GLB_CTRL_FIELDS + }, + { /* register name MAC_PORT_CTRL */ + /* offset address */ 0x122C, + /* field numbers */ 6, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ MAC_PORT_CTRL_FIELDS + }, + { /* register name HALF_CHG_CTRL */ + /* offset address */ 0x1230, + /* field numbers */ 7, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ HALF_CHG_CTRL_FIELDS + }, + { /* register name SMI_GLB_CTRL2 */ + /* offset address */ 0x6328, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SMI_GLB_CTRL2_FIELDS + }, + { /* register name SMI_GLB_CTRL */ + /* offset address */ 0x632C, + /* field numbers */ 12, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SMI_GLB_CTRL_FIELDS + }, + { /* register name SMI_MAC_TYPE_CTRL */ + /* offset address */ 0x6330, + /* field numbers */ 10, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SMI_MAC_TYPE_CTRL_FIELDS + }, + { /* register name SMI_PORT_POLLING_SEL */ + /* offset address */ 0x6334, + /* field numbers */ 10, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SMI_PORT_POLLING_SEL_FIELDS + }, + { /* register name SMI_MDIO_FREE_CNT_CTRL */ + /* offset address */ 0x6338, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SMI_MDIO_FREE_CNT_CTRL_FIELDS + }, + { /* register name SMI_PRVTE_POLLING_CTRL */ + /* offset address */ 0x633C, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SMI_PRVTE_POLLING_CTRL_FIELDS + }, + { /* register name SMI_10GPHY_POLLING_SEL_0 */ + /* offset address */ 0x6340, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SMI_10GPHY_POLLING_SEL_0_FIELDS + }, + { /* register name MAC_FORCE_MODE_CTRL0 */ + /* offset address */ 0x6344, + /* field numbers */ 10, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ MAC_FORCE_MODE_CTRL0_FIELDS + }, + { /* register name MAC_FORCE_MODE_CTRL1 */ + /* offset address */ 0x636C, + /* field numbers */ 10, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ MAC_FORCE_MODE_CTRL1_FIELDS + }, + { /* register name SMI_REG_CHK1_CTRL1 */ + /* offset address */ 0x6394, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SMI_REG_CHK1_CTRL1_FIELDS + }, + { /* register name SMI_REG_CHK1_PMSK */ + /* offset address */ 0x6398, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SMI_REG_CHK1_PMSK_FIELDS + }, + { /* register name SMI_REG_CHK1_DATA_10G */ + /* offset address */ 0x639C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SMI_REG_CHK1_DATA_10G_FIELDS + }, + { /* register name SMI_REG_CHK1_RESULT */ + /* offset address */ 0x63A0, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SMI_REG_CHK1_RESULT_FIELDS + }, + { /* register name SMI_REG_CHK2_CTRL1 */ + /* offset address */ 0x63A4, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SMI_REG_CHK2_CTRL1_FIELDS + }, + { /* register name SMI_REG_CHK2_PMSK */ + /* offset address */ 0x63A8, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SMI_REG_CHK2_PMSK_FIELDS + }, + { /* register name SMI_REG_CHK2_DATA_10G */ + /* offset address */ 0x63AC, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SMI_REG_CHK2_DATA_10G_FIELDS + }, + { /* register name SMI_REG_CHK2_RESULT */ + /* offset address */ 0x63B0, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SMI_REG_CHK2_RESULT_FIELDS + }, + { /* register name SMI_REG_CHK3_CTRL1 */ + /* offset address */ 0x63B4, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SMI_REG_CHK3_CTRL1_FIELDS + }, + { /* register name SMI_REG_CHK3_PMSK */ + /* offset address */ 0x63B8, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SMI_REG_CHK3_PMSK_FIELDS + }, + { /* register name SMI_REG_CHK3_DATA_10G */ + /* offset address */ 0x63BC, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SMI_REG_CHK3_DATA_10G_FIELDS + }, + { /* register name SMI_REG_CHK3_RESULT */ + /* offset address */ 0x63C0, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SMI_REG_CHK3_RESULT_FIELDS + }, + { /* register name SMI_REG_CHK4_CTRL1 */ + /* offset address */ 0x63C4, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SMI_REG_CHK4_CTRL1_FIELDS + }, + { /* register name SMI_REG_CHK4_PMSK */ + /* offset address */ 0x63C8, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SMI_REG_CHK4_PMSK_FIELDS + }, + { /* register name SMI_REG_CHK4_DATA_10G */ + /* offset address */ 0x63CC, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SMI_REG_CHK4_DATA_10G_FIELDS + }, + { /* register name SMI_REG_CHK4_RESULT */ + /* offset address */ 0x63D0, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SMI_REG_CHK4_RESULT_FIELDS + }, + { /* register name SMI_REG_CHK5_CTRL1 */ + /* offset address */ 0x63D4, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SMI_REG_CHK5_CTRL1_FIELDS + }, + { /* register name SMI_REG_CHK5_PMSK */ + /* offset address */ 0x63D8, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SMI_REG_CHK5_PMSK_FIELDS + }, + { /* register name SMI_REG_CHK5_DATA_10G */ + /* offset address */ 0x63DC, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SMI_REG_CHK5_DATA_10G_FIELDS + }, + { /* register name SMI_REG_CHK5_RESULT */ + /* offset address */ 0x63E0, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SMI_REG_CHK5_RESULT_FIELDS + }, + { /* register name LINK_DELAY_CTRL */ + /* offset address */ 0x63E4, + /* field numbers */ 7, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ LINK_DELAY_CTRL_FIELDS + }, + { /* register name MAC_LINK_STS */ + /* offset address */ 0x63E8, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MAC_LINK_STS_FIELDS + }, + { /* register name MAC_LINK_MEDIA_STS */ + /* offset address */ 0x63EC, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MAC_LINK_MEDIA_STS_FIELDS + }, + { /* register name MAC_LINK_SPD_STS */ + /* offset address */ 0x63F0, + /* field numbers */ 1, + /* array offset */ 4, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ MAC_LINK_SPD_STS_FIELDS + }, + { /* register name MAC_LINK_DUP_STS */ + /* offset address */ 0x63F8, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MAC_LINK_DUP_STS_FIELDS + }, + { /* register name MAC_TX_PAUSE_STS */ + /* offset address */ 0x63FC, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MAC_TX_PAUSE_STS_FIELDS + }, + { /* register name MAC_RX_PAUSE_STS */ + /* offset address */ 0x6400, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MAC_RX_PAUSE_STS_FIELDS + }, + { /* register name MAC_EEE_ABLTY */ + /* offset address */ 0x6404, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MAC_EEE_ABLTY_FIELDS + }, + { /* register name MAC_MSTR_SLV_STS */ + /* offset address */ 0x6408, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MAC_MSTR_SLV_STS_FIELDS + }, + { /* register name MAC_MSTR_SLV_FAULT_STS */ + /* offset address */ 0x640C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MAC_MSTR_SLV_FAULT_STS_FIELDS + }, + { /* register name PHY_LINK_STS */ + /* offset address */ 0x6410, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PHY_LINK_STS_FIELDS + }, + { /* register name PHY_LINK_MEDIA_STS */ + /* offset address */ 0x6414, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PHY_LINK_MEDIA_STS_FIELDS + }, + { /* register name PHY_LINK_SPD_STS */ + /* offset address */ 0x6418, + /* field numbers */ 1, + /* array offset */ 4, + /* array index */ 0, 0, + /* port index */ 0, 8, + /* register fields */ PHY_LINK_SPD_STS_FIELDS + }, + { /* register name PHY_LINK_DUP_STS */ + /* offset address */ 0x6420, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PHY_LINK_DUP_STS_FIELDS + }, + { /* register name PHY_TX_PAUSE_STS */ + /* offset address */ 0x6424, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PHY_TX_PAUSE_STS_FIELDS + }, + { /* register name PHY_RX_PAUSE_STS */ + /* offset address */ 0x6428, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PHY_RX_PAUSE_STS_FIELDS + }, + { /* register name PHY_EEE_ABLTY */ + /* offset address */ 0x642C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PHY_EEE_ABLTY_FIELDS + }, + { /* register name PHY_MSTR_SLV_STS */ + /* offset address */ 0x6430, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PHY_MSTR_SLV_STS_FIELDS + }, + { /* register name PHY_MSTR_SLV_FAULT_STS */ + /* offset address */ 0x6434, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PHY_MSTR_SLV_FAULT_STS_FIELDS + }, + { /* register name SMI_ACCESS_PHY_CTRL_0 */ + /* offset address */ 0x6438, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SMI_ACCESS_PHY_CTRL_0_FIELDS + }, + { /* register name SMI_ACCESS_PHY_CTRL_1 */ + /* offset address */ 0x643C, + /* field numbers */ 7, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SMI_ACCESS_PHY_CTRL_1_FIELDS + }, + { /* register name SMI_ACCESS_PHY_CTRL_2 */ + /* offset address */ 0x6440, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SMI_ACCESS_PHY_CTRL_2_FIELDS + }, + { /* register name SMI_ACCESS_PHY_CTRL_3 */ + /* offset address */ 0x6444, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SMI_ACCESS_PHY_CTRL_3_FIELDS + }, + { /* register name SMI_ACCESS_PHY_CTRL_4 */ + /* offset address */ 0x6448, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SMI_ACCESS_PHY_CTRL_4_FIELDS + }, + { /* register name SMI_PORT0_5_ADDR_CTRL */ + /* offset address */ 0x644C, + /* field numbers */ 7, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SMI_PORT0_5_ADDR_CTRL_FIELDS + }, + { /* register name SMI_PORT6_9_ADDR_CTRL */ + /* offset address */ 0x6450, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SMI_PORT6_9_ADDR_CTRL_FIELDS + }, + { /* register name SMI_CTRL */ + /* offset address */ 0x6454, + /* field numbers */ 7, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SMI_CTRL_FIELDS + }, + { /* register name RLFD_CTRL */ + /* offset address */ 0x6458, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RLFD_CTRL_FIELDS + }, + { /* register name RLFD_10G_ADDR */ + /* offset address */ 0x645C, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RLFD_10G_ADDR_FIELDS + }, + { /* register name UNI_DIR_CTRL */ + /* offset address */ 0x6460, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNI_DIR_CTRL_FIELDS + }, + { /* register name SMI_10GPHY_POLLING_SEL_1 */ + /* offset address */ 0x6464, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SMI_10GPHY_POLLING_SEL_1_FIELDS + }, + { /* register name SMI_10GPHY_POLLING_REG0_CFG */ + /* offset address */ 0x6468, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 2, + /* register fields */ SMI_10GPHY_POLLING_REG0_CFG_FIELDS + }, + { /* register name SMI_10GPHY_POLLING_REG9_CFG */ + /* offset address */ 0x6474, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 2, + /* register fields */ SMI_10GPHY_POLLING_REG9_CFG_FIELDS + }, + { /* register name SMI_10GPHY_POLLING_REG10_CFG */ + /* offset address */ 0x6480, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 2, + /* register fields */ SMI_10GPHY_POLLING_REG10_CFG_FIELDS + }, + { /* register name MAC_CTRL_1 */ + /* offset address */ 0x648C, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MAC_CTRL_1_FIELDS + }, + { /* register name MAC_CTRL_2 */ + /* offset address */ 0x6490, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MAC_CTRL_2_FIELDS + }, + { /* register name MAC8_RTL8226B_CTRL */ + /* offset address */ 0x6494, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MAC8_RTL8226B_CTRL_FIELDS + }, + { /* register name TX_RX_IDLE */ + /* offset address */ 0x6498, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ TX_RX_IDLE_FIELDS + }, + { /* register name IDLE_DLY_CTRL */ + /* offset address */ 0x101C, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ IDLE_DLY_CTRL_FIELDS + }, + { /* register name MAC_IPG_COMPS_CTRL */ + /* offset address */ 0x1234, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ MAC_IPG_COMPS_CTRL_FIELDS + }, + { /* register name MAC_L2_GLOBAL_CTRL0 */ + /* offset address */ 0x5FD4, + /* field numbers */ 12, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MAC_L2_GLOBAL_CTRL0_FIELDS + }, + { /* register name MAC_L2_GLOBAL_CTRL1 */ + /* offset address */ 0x5FD8, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MAC_L2_GLOBAL_CTRL1_FIELDS + }, + { /* register name MAC_L2_PORT_CTRL */ + /* offset address */ 0x1238, + /* field numbers */ 13, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ MAC_L2_PORT_CTRL_FIELDS + }, + { /* register name MAC_MACSEC_IPG_CFG */ + /* offset address */ 0x123C, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ MAC_MACSEC_IPG_CFG_FIELDS + }, + { /* register name MAC_MACSEC_ETH_1_0 */ + /* offset address */ 0x1240, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ MAC_MACSEC_ETH_1_0_FIELDS + }, + { /* register name MAC_MACSEC_ETH_3_2 */ + /* offset address */ 0x1244, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ MAC_MACSEC_ETH_3_2_FIELDS + }, + { /* register name MAC_MACSEC_ETH_5_4 */ + /* offset address */ 0x1248, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ MAC_MACSEC_ETH_5_4_FIELDS + }, + { /* register name MAC_MACSEC_ETH_7_6 */ + /* offset address */ 0x124C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ MAC_MACSEC_ETH_7_6_FIELDS + }, + { /* register name MAC_L2_PADDING_SEL */ + /* offset address */ 0x5FDC, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MAC_L2_PADDING_SEL_FIELDS + }, + { /* register name MAC_L2_ADDR_CTRL */ + /* offset address */ 0x5FE0, + /* field numbers */ 3, + /* array offset */ 64, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MAC_L2_ADDR_CTRL_FIELDS + }, + { /* register name MAC_L2_PORT_MAX_LEN_CTRL */ + /* offset address */ 0x1250, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ MAC_L2_PORT_MAX_LEN_CTRL_FIELDS + }, + { /* register name MAC_L2_TGPORT_PRMB_DBG0 */ + /* offset address */ 0x1254, + /* field numbers */ 11, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ MAC_L2_TGPORT_PRMB_DBG0_FIELDS + }, + { /* register name MAC_L2_TGPORT_PRMB_DBG1 */ + /* offset address */ 0x1258, + /* field numbers */ 6, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ MAC_L2_TGPORT_PRMB_DBG1_FIELDS + }, + { /* register name PHY_CFG_8224 */ + /* offset address */ 0x444, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PHY_CFG_8224_FIELDS + }, + { /* register name MDX_CTRL_8224 */ + /* offset address */ 0x448, + /* field numbers */ 8, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MDX_CTRL_8224_FIELDS + }, + { /* register name INT_PHY_OCP_INDR_ACC_CTRL_0 */ + /* offset address */ 0xBC8, + /* field numbers */ 7, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ INT_PHY_OCP_INDR_ACC_CTRL_0_FIELDS + }, + { /* register name INT_PHY_OCP_INDR_ACC_CTRL_1 */ + /* offset address */ 0xBCC, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ INT_PHY_OCP_INDR_ACC_CTRL_1_FIELDS + }, + { /* register name INT_PHY_OCP_INDR_ACC_CTRL_2 */ + /* offset address */ 0xBD0, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ INT_PHY_OCP_INDR_ACC_CTRL_2_FIELDS + }, + { /* register name MAC_PFC_FORCE_FC */ + /* offset address */ 0x5FE8, + /* field numbers */ 7, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MAC_PFC_FORCE_FC_FIELDS + }, + { /* register name MAC_TXFIFO_FULTH_CTRL_0 */ + /* offset address */ 0x1020, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MAC_TXFIFO_FULTH_CTRL_0_FIELDS + }, + { /* register name MAC_TXFIFO_FULTH_CTRL_1 */ + /* offset address */ 0x1024, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MAC_TXFIFO_FULTH_CTRL_1_FIELDS + }, + { /* register name MAC_TXFIFO_FULTH_CTRL_2 */ + /* offset address */ 0x1028, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MAC_TXFIFO_FULTH_CTRL_2_FIELDS + }, + { /* register name MAC_TXFIFO_FULTH_CTRL_3 */ + /* offset address */ 0x102C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MAC_TXFIFO_FULTH_CTRL_3_FIELDS + }, + { /* register name MAC_TXFIFO_FULTH_CTRL_4 */ + /* offset address */ 0x1030, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MAC_TXFIFO_FULTH_CTRL_4_FIELDS + }, + { /* register name MAC_TXFIFO_FULTH_CTRL_5 */ + /* offset address */ 0x1034, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MAC_TXFIFO_FULTH_CTRL_5_FIELDS + }, + { /* register name MACSEC_REG_GLB_SET1_PORT4 */ + /* offset address */ 0xC0F0, + /* field numbers */ 27, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_REG_GLB_SET1_PORT4_FIELDS + }, + { /* register name MACSEC_REG_GLB_IMR_PORT4 */ + /* offset address */ 0xC0F4, + /* field numbers */ 10, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_REG_GLB_IMR_PORT4_FIELDS + }, + { /* register name MACSEC_REG_GLB_ISR_PORT4 */ + /* offset address */ 0xC0F8, + /* field numbers */ 10, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_REG_GLB_ISR_PORT4_FIELDS + }, + { /* register name UNUSED_000C_PORT4 */ + /* offset address */ 0xC0FC, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_000C_PORT4_FIELDS + }, + { /* register name MACSEC_PM_CTRL_PORT4 */ + /* offset address */ 0xC100, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_PM_CTRL_PORT4_FIELDS + }, + { /* register name MACSEC_REG_GLB_MASK_PORT4 */ + /* offset address */ 0xC104, + /* field numbers */ 12, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_REG_GLB_MASK_PORT4_FIELDS + }, + { /* register name MACSEC_REG_GLB_SET4_PORT4 */ + /* offset address */ 0xC108, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_REG_GLB_SET4_PORT4_FIELDS + }, + { /* register name MACSEC_REG_IP_PROBE_PORT4 */ + /* offset address */ 0xC10C, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_REG_IP_PROBE_PORT4_FIELDS + }, + { /* register name UNUSED_0020_PORT4 */ + /* offset address */ 0xC110, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0020_PORT4_FIELDS + }, + { /* register name UNUSED_0024_PORT4 */ + /* offset address */ 0xC114, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0024_PORT4_FIELDS + }, + { /* register name MACSEC_MBIST_SA_CTRL_PORT4 */ + /* offset address */ 0xC118, + /* field numbers */ 16, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_MBIST_SA_CTRL_PORT4_FIELDS + }, + { /* register name MACSEC_MBIST_STAT_CTRL_PORT4 */ + /* offset address */ 0xC11C, + /* field numbers */ 28, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_MBIST_STAT_CTRL_PORT4_FIELDS + }, + { /* register name MACSEC_MBIST_SA_AE_TEST_PORT4 */ + /* offset address */ 0xC120, + /* field numbers */ 20, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_MBIST_SA_AE_TEST_PORT4_FIELDS + }, + { /* register name MACSEC_MBIST_STAT_AE_TEST_PORT4 */ + /* offset address */ 0xC124, + /* field numbers */ 16, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_MBIST_STAT_AE_TEST_PORT4_FIELDS + }, + { /* register name MACSEC_MBIST_SA_FAIL_PORT4 */ + /* offset address */ 0xC128, + /* field numbers */ 21, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_MBIST_SA_FAIL_PORT4_FIELDS + }, + { /* register name MACSEC_XGLBK_FIFO_DBG_PORT4 */ + /* offset address */ 0xC12C, + /* field numbers */ 10, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_XGLBK_FIFO_DBG_PORT4_FIELDS + }, + { /* register name MACSEC_REG_RWDH_AE_PORT4 */ + /* offset address */ 0xC130, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_REG_RWDH_AE_PORT4_FIELDS + }, + { /* register name MACSEC_REG_ADDR_AE_PORT4 */ + /* offset address */ 0xC134, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_REG_ADDR_AE_PORT4_FIELDS + }, + { /* register name MACSEC_REG_CMD_AE_PORT4 */ + /* offset address */ 0xC138, + /* field numbers */ 5, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_REG_CMD_AE_PORT4_FIELDS + }, + { /* register name MACSEC_REG_RWDL_AI_PORT4 */ + /* offset address */ 0xC13C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_REG_RWDL_AI_PORT4_FIELDS + }, + { /* register name MACSEC_REG_ADDR_AI_PORT4 */ + /* offset address */ 0xC140, + /* field numbers */ 5, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_REG_ADDR_AI_PORT4_FIELDS + }, + { /* register name MACSEC_REG_RWD_PTP_PORT4 */ + /* offset address */ 0xC144, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_REG_RWD_PTP_PORT4_FIELDS + }, + { /* register name MACSEC_REG_CMD_PTP_PORT4 */ + /* offset address */ 0xC148, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_REG_CMD_PTP_PORT4_FIELDS + }, + { /* register name UNUSED_005C_PORT4 */ + /* offset address */ 0xC14C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_005C_PORT4_FIELDS + }, + { /* register name UNUSED_0060_PORT4 */ + /* offset address */ 0xC150, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0060_PORT4_FIELDS + }, + { /* register name UNUSED_0064_PORT4 */ + /* offset address */ 0xC154, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0064_PORT4_FIELDS + }, + { /* register name UNUSED_0068_PORT4 */ + /* offset address */ 0xC158, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0068_PORT4_FIELDS + }, + { /* register name UNUSED_006C_PORT4 */ + /* offset address */ 0xC15C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_006C_PORT4_FIELDS + }, + { /* register name UNUSED_0070_PORT4 */ + /* offset address */ 0xC160, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0070_PORT4_FIELDS + }, + { /* register name UNUSED_0074_PORT4 */ + /* offset address */ 0xC164, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0074_PORT4_FIELDS + }, + { /* register name RESERVED_0078_PORT4 */ + /* offset address */ 0xC168, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RESERVED_0078_PORT4_FIELDS + }, + { /* register name RESERVED_007C_PORT4 */ + /* offset address */ 0xC16C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RESERVED_007C_PORT4_FIELDS + }, + { /* register name MACSEC_TXSYSCRCERR_CNT_PORT4 */ + /* offset address */ 0xC170, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXSYSCRCERR_CNT_PORT4_FIELDS + }, + { /* register name MACSEC_TXSYSPKTERR_CNT_PORT4 */ + /* offset address */ 0xC174, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXSYSPKTERR_CNT_PORT4_FIELDS + }, + { /* register name MACSEC_TXSYSOK_CNT_0_PORT4 */ + /* offset address */ 0xC178, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXSYSOK_CNT_0_PORT4_FIELDS + }, + { /* register name MACSEC_TXSYSOK_CNT_2_PORT4 */ + /* offset address */ 0xC17C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXSYSOK_CNT_2_PORT4_FIELDS + }, + { /* register name MACSEC_TXSYSGERR_CNT_PORT4 */ + /* offset address */ 0xC180, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXSYSGERR_CNT_PORT4_FIELDS + }, + { /* register name MACSEC_TXSYSGLPIERR_CNT_PORT4 */ + /* offset address */ 0xC184, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXSYSGLPIERR_CNT_PORT4_FIELDS + }, + { /* register name MACSEC_TXSYS_DBG_PORT4 */ + /* offset address */ 0xC188, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXSYS_DBG_PORT4_FIELDS + }, + { /* register name MACSEC_TX_RX_CNT_INCR_PORT4 */ + /* offset address */ 0xC18C, + /* field numbers */ 18, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TX_RX_CNT_INCR_PORT4_FIELDS + }, + { /* register name MACSEC_TXLINECRCERR_CNT_PORT4 */ + /* offset address */ 0xC190, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXLINECRCERR_CNT_PORT4_FIELDS + }, + { /* register name MACSEC_TXLINEPKTERR_CNT_PORT4 */ + /* offset address */ 0xC194, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXLINEPKTERR_CNT_PORT4_FIELDS + }, + { /* register name MACSEC_TXLINEOK_CNT_0_PORT4 */ + /* offset address */ 0xC198, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXLINEOK_CNT_0_PORT4_FIELDS + }, + { /* register name MACSEC_TXLINEOK_CNT_2_PORT4 */ + /* offset address */ 0xC19C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXLINEOK_CNT_2_PORT4_FIELDS + }, + { /* register name MACSEC_TXLINEDROP_CNT_PORT4 */ + /* offset address */ 0xC1A0, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXLINEDROP_CNT_PORT4_FIELDS + }, + { /* register name MACSEC_TXLINESRT_CNT_PORT4 */ + /* offset address */ 0xC1A4, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXLINESRT_CNT_PORT4_FIELDS + }, + { /* register name MACSEC_TXLINEGERR_CNT_PORT4 */ + /* offset address */ 0xC1A8, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXLINEGERR_CNT_PORT4_FIELDS + }, + { /* register name MACSEC_TXLINE_DBG_PORT4 */ + /* offset address */ 0xC1AC, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXLINE_DBG_PORT4_FIELDS + }, + { /* register name MACSEC_RXLINECRCERR_CNT_PORT4 */ + /* offset address */ 0xC1B0, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXLINECRCERR_CNT_PORT4_FIELDS + }, + { /* register name MACSEC_RXLINEPKTERR_CNT_PORT4 */ + /* offset address */ 0xC1B4, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXLINEPKTERR_CNT_PORT4_FIELDS + }, + { /* register name MACSEC_RXLINEOK_CNT_0_PORT4 */ + /* offset address */ 0xC1B8, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXLINEOK_CNT_0_PORT4_FIELDS + }, + { /* register name MACSEC_RXLINEOK_CNT_2_PORT4 */ + /* offset address */ 0xC1BC, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXLINEOK_CNT_2_PORT4_FIELDS + }, + { /* register name MACSEC_RXLINESRT_CNT_PORT4 */ + /* offset address */ 0xC1C0, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXLINESRT_CNT_PORT4_FIELDS + }, + { /* register name MACSEC_RXLINEGERR_CNT_PORT4 */ + /* offset address */ 0xC1C4, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXLINEGERR_CNT_PORT4_FIELDS + }, + { /* register name MACSEC_RXLINEGLPIERR_CNT_PORT4 */ + /* offset address */ 0xC1C8, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXLINEGLPIERR_CNT_PORT4_FIELDS + }, + { /* register name MACSEC_RXLINE_DBG_PORT4 */ + /* offset address */ 0xC1CC, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXLINE_DBG_PORT4_FIELDS + }, + { /* register name MACSEC_RXSYSCRCERR_CNT_PORT4 */ + /* offset address */ 0xC1D0, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXSYSCRCERR_CNT_PORT4_FIELDS + }, + { /* register name MACSEC_RXSYSPKTERR_CNT_PORT4 */ + /* offset address */ 0xC1D4, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXSYSPKTERR_CNT_PORT4_FIELDS + }, + { /* register name MACSEC_RXSYSOK_CNT_0_PORT4 */ + /* offset address */ 0xC1D8, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXSYSOK_CNT_0_PORT4_FIELDS + }, + { /* register name MACSEC_RXSYSOK_CNT_2_PORT4 */ + /* offset address */ 0xC1DC, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXSYSOK_CNT_2_PORT4_FIELDS + }, + { /* register name MACSEC_RXSYSDROP_CNT_PORT4 */ + /* offset address */ 0xC1E0, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXSYSDROP_CNT_PORT4_FIELDS + }, + { /* register name MACSEC_RXSYSSRT_CNT_PORT4 */ + /* offset address */ 0xC1E4, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXSYSSRT_CNT_PORT4_FIELDS + }, + { /* register name MACSEC_RXSYSGERR_CNT_PORT4 */ + /* offset address */ 0xC1E8, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXSYSGERR_CNT_PORT4_FIELDS + }, + { /* register name MACSEC_RXSYS_DBG_PORT4 */ + /* offset address */ 0xC1EC, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXSYS_DBG_PORT4_FIELDS + }, + { /* register name MACSEC_TXSYS_CFG1_PORT4 */ + /* offset address */ 0xC1F0, + /* field numbers */ 6, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXSYS_CFG1_PORT4_FIELDS + }, + { /* register name MACSEC_TXSYS_PTPCFG_PORT4 */ + /* offset address */ 0xC1F4, + /* field numbers */ 8, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXSYS_PTPCFG_PORT4_FIELDS + }, + { /* register name MACSEC_TXSYS_OUTERVLAN2_PORT4 */ + /* offset address */ 0xC1F8, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXSYS_OUTERVLAN2_PORT4_FIELDS + }, + { /* register name MACSEC_TXSYS_OUTERVLAN4_PORT4 */ + /* offset address */ 0xC1FC, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXSYS_OUTERVLAN4_PORT4_FIELDS + }, + { /* register name MACSEC_TXSYS_INNERVLAN2_PORT4 */ + /* offset address */ 0xC200, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXSYS_INNERVLAN2_PORT4_FIELDS + }, + { /* register name MACSEC_TXSYS_INNERVLAN4_PORT4 */ + /* offset address */ 0xC204, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXSYS_INNERVLAN4_PORT4_FIELDS + }, + { /* register name MACSEC_TXSYS_INNERVLAN6_PORT4 */ + /* offset address */ 0xC208, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXSYS_INNERVLAN6_PORT4_FIELDS + }, + { /* register name UNUSED_011C_PORT4 */ + /* offset address */ 0xC20C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_011C_PORT4_FIELDS + }, + { /* register name UNUSED_0120_PORT4 */ + /* offset address */ 0xC210, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0120_PORT4_FIELDS + }, + { /* register name UNUSED_0124_PORT4 */ + /* offset address */ 0xC214, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0124_PORT4_FIELDS + }, + { /* register name UNUSED_0128_PORT4 */ + /* offset address */ 0xC218, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0128_PORT4_FIELDS + }, + { /* register name UNUSED_012C_PORT4 */ + /* offset address */ 0xC21C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_012C_PORT4_FIELDS + }, + { /* register name UNUSED_0130_PORT4 */ + /* offset address */ 0xC220, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0130_PORT4_FIELDS + }, + { /* register name UNUSED_0134_PORT4 */ + /* offset address */ 0xC224, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0134_PORT4_FIELDS + }, + { /* register name UNUSED_0138_PORT4 */ + /* offset address */ 0xC228, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0138_PORT4_FIELDS + }, + { /* register name UNUSED_013C_PORT4 */ + /* offset address */ 0xC22C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_013C_PORT4_FIELDS + }, + { /* register name MACSEC_TXLINE_CFG1_PORT4 */ + /* offset address */ 0xC230, + /* field numbers */ 5, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXLINE_CFG1_PORT4_FIELDS + }, + { /* register name MACSEC_TXLINE_CFG3_PORT4 */ + /* offset address */ 0xC234, + /* field numbers */ 13, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXLINE_CFG3_PORT4_FIELDS + }, + { /* register name MACSEC_TXLINE_CFG5_PORT4 */ + /* offset address */ 0xC238, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXLINE_CFG5_PORT4_FIELDS + }, + { /* register name UNUSED_014C_PORT4 */ + /* offset address */ 0xC23C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_014C_PORT4_FIELDS + }, + { /* register name UNUSED_0150_PORT4 */ + /* offset address */ 0xC240, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0150_PORT4_FIELDS + }, + { /* register name UNUSED_0154_PORT4 */ + /* offset address */ 0xC244, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0154_PORT4_FIELDS + }, + { /* register name UNUSED_0158_PORT4 */ + /* offset address */ 0xC248, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0158_PORT4_FIELDS + }, + { /* register name UNUSED_015C_PORT4 */ + /* offset address */ 0xC24C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_015C_PORT4_FIELDS + }, + { /* register name UNUSED_0160_PORT4 */ + /* offset address */ 0xC250, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0160_PORT4_FIELDS + }, + { /* register name UNUSED_0164_PORT4 */ + /* offset address */ 0xC254, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0164_PORT4_FIELDS + }, + { /* register name UNUSED_0168_PORT4 */ + /* offset address */ 0xC258, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0168_PORT4_FIELDS + }, + { /* register name UNUSED_016C_PORT4 */ + /* offset address */ 0xC25C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_016C_PORT4_FIELDS + }, + { /* register name UNUSED_0170_PORT4 */ + /* offset address */ 0xC260, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0170_PORT4_FIELDS + }, + { /* register name UNUSED_0174_PORT4 */ + /* offset address */ 0xC264, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0174_PORT4_FIELDS + }, + { /* register name UNUSED_0178_PORT4 */ + /* offset address */ 0xC268, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0178_PORT4_FIELDS + }, + { /* register name UNUSED_017C_PORT4 */ + /* offset address */ 0xC26C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_017C_PORT4_FIELDS + }, + { /* register name MACSEC_RXLINE_CFG1_PORT4 */ + /* offset address */ 0xC270, + /* field numbers */ 6, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXLINE_CFG1_PORT4_FIELDS + }, + { /* register name UNUSED_0184_PORT4 */ + /* offset address */ 0xC274, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0184_PORT4_FIELDS + }, + { /* register name UNUSED_0188_PORT4 */ + /* offset address */ 0xC278, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0188_PORT4_FIELDS + }, + { /* register name UNUSED_018C_PORT4 */ + /* offset address */ 0xC27C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_018C_PORT4_FIELDS + }, + { /* register name UNUSED_0190_PORT4 */ + /* offset address */ 0xC280, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0190_PORT4_FIELDS + }, + { /* register name UNUSED_0194_PORT4 */ + /* offset address */ 0xC284, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0194_PORT4_FIELDS + }, + { /* register name UNUSED_0198_PORT4 */ + /* offset address */ 0xC288, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0198_PORT4_FIELDS + }, + { /* register name UNUSED_019C_PORT4 */ + /* offset address */ 0xC28C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_019C_PORT4_FIELDS + }, + { /* register name UNUSED_01A0_PORT4 */ + /* offset address */ 0xC290, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_01A0_PORT4_FIELDS + }, + { /* register name UNUSED_01A4_PORT4 */ + /* offset address */ 0xC294, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_01A4_PORT4_FIELDS + }, + { /* register name UNUSED_01A8_PORT4 */ + /* offset address */ 0xC298, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_01A8_PORT4_FIELDS + }, + { /* register name UNUSED_01AC_PORT4 */ + /* offset address */ 0xC29C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_01AC_PORT4_FIELDS + }, + { /* register name UNUSED_01B0_PORT4 */ + /* offset address */ 0xC2A0, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_01B0_PORT4_FIELDS + }, + { /* register name UNUSED_01B4_PORT4 */ + /* offset address */ 0xC2A4, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_01B4_PORT4_FIELDS + }, + { /* register name UNUSED_01B8_PORT4 */ + /* offset address */ 0xC2A8, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_01B8_PORT4_FIELDS + }, + { /* register name UNUSED_01BC_PORT4 */ + /* offset address */ 0xC2AC, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_01BC_PORT4_FIELDS + }, + { /* register name MACSEC_RXSYS_CFG1_PORT4 */ + /* offset address */ 0xC2B0, + /* field numbers */ 5, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXSYS_CFG1_PORT4_FIELDS + }, + { /* register name MACSEC_RXSYS_CFG3_PORT4 */ + /* offset address */ 0xC2B4, + /* field numbers */ 12, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXSYS_CFG3_PORT4_FIELDS + }, + { /* register name MACSEC_RXSYS_OUTERVLAN2_PORT4 */ + /* offset address */ 0xC2B8, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXSYS_OUTERVLAN2_PORT4_FIELDS + }, + { /* register name MACSEC_RXSYS_OUTERVLAN4_PORT4 */ + /* offset address */ 0xC2BC, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXSYS_OUTERVLAN4_PORT4_FIELDS + }, + { /* register name MACSEC_RXSYS_INNERVLAN2_PORT4 */ + /* offset address */ 0xC2C0, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXSYS_INNERVLAN2_PORT4_FIELDS + }, + { /* register name MACSEC_RXSYS_INNERVLAN4_PORT4 */ + /* offset address */ 0xC2C4, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXSYS_INNERVLAN4_PORT4_FIELDS + }, + { /* register name MACSEC_RXSYS_INNERVLAN6_PORT4 */ + /* offset address */ 0xC2C8, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXSYS_INNERVLAN6_PORT4_FIELDS + }, + { /* register name MACSEC_RXSYS_CFG4_PORT4 */ + /* offset address */ 0xC2CC, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXSYS_CFG4_PORT4_FIELDS + }, + { /* register name MACSEC_RXSYS_CFG6_PORT4 */ + /* offset address */ 0xC2D0, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXSYS_CFG6_PORT4_FIELDS + }, + { /* register name MACSEC_REG_GLB_SET1_PORT5 */ + /* offset address */ 0xC8F0, + /* field numbers */ 27, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_REG_GLB_SET1_PORT5_FIELDS + }, + { /* register name MACSEC_REG_GLB_IMR_PORT5 */ + /* offset address */ 0xC8F4, + /* field numbers */ 10, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_REG_GLB_IMR_PORT5_FIELDS + }, + { /* register name MACSEC_REG_GLB_ISR_PORT5 */ + /* offset address */ 0xC8F8, + /* field numbers */ 10, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_REG_GLB_ISR_PORT5_FIELDS + }, + { /* register name UNUSED_000C_PORT5 */ + /* offset address */ 0xC8FC, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_000C_PORT5_FIELDS + }, + { /* register name MACSEC_PM_CTRL_PORT5 */ + /* offset address */ 0xC900, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_PM_CTRL_PORT5_FIELDS + }, + { /* register name MACSEC_REG_GLB_MASK_PORT5 */ + /* offset address */ 0xC904, + /* field numbers */ 12, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_REG_GLB_MASK_PORT5_FIELDS + }, + { /* register name MACSEC_REG_GLB_SET4_PORT5 */ + /* offset address */ 0xC908, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_REG_GLB_SET4_PORT5_FIELDS + }, + { /* register name MACSEC_REG_IP_PROBE_PORT5 */ + /* offset address */ 0xC90C, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_REG_IP_PROBE_PORT5_FIELDS + }, + { /* register name UNUSED_0020_PORT5 */ + /* offset address */ 0xC910, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0020_PORT5_FIELDS + }, + { /* register name UNUSED_0024_PORT5 */ + /* offset address */ 0xC914, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0024_PORT5_FIELDS + }, + { /* register name MACSEC_MBIST_SA_CTRL_PORT5 */ + /* offset address */ 0xC918, + /* field numbers */ 16, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_MBIST_SA_CTRL_PORT5_FIELDS + }, + { /* register name MACSEC_MBIST_STAT_CTRL_PORT5 */ + /* offset address */ 0xC91C, + /* field numbers */ 28, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_MBIST_STAT_CTRL_PORT5_FIELDS + }, + { /* register name MACSEC_MBIST_SA_AE_TEST_PORT5 */ + /* offset address */ 0xC920, + /* field numbers */ 20, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_MBIST_SA_AE_TEST_PORT5_FIELDS + }, + { /* register name MACSEC_MBIST_STAT_AE_TEST_PORT5 */ + /* offset address */ 0xC924, + /* field numbers */ 16, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_MBIST_STAT_AE_TEST_PORT5_FIELDS + }, + { /* register name MACSEC_MBIST_SA_FAIL_PORT5 */ + /* offset address */ 0xC928, + /* field numbers */ 21, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_MBIST_SA_FAIL_PORT5_FIELDS + }, + { /* register name MACSEC_XGLBK_FIFO_DBG_PORT5 */ + /* offset address */ 0xC92C, + /* field numbers */ 10, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_XGLBK_FIFO_DBG_PORT5_FIELDS + }, + { /* register name MACSEC_REG_RWDH_AE_PORT5 */ + /* offset address */ 0xC930, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_REG_RWDH_AE_PORT5_FIELDS + }, + { /* register name MACSEC_REG_ADDR_AE_PORT5 */ + /* offset address */ 0xC934, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_REG_ADDR_AE_PORT5_FIELDS + }, + { /* register name MACSEC_REG_CMD_AE_PORT5 */ + /* offset address */ 0xC938, + /* field numbers */ 5, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_REG_CMD_AE_PORT5_FIELDS + }, + { /* register name MACSEC_REG_RWDL_AI_PORT5 */ + /* offset address */ 0xC93C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_REG_RWDL_AI_PORT5_FIELDS + }, + { /* register name MACSEC_REG_ADDR_AI_PORT5 */ + /* offset address */ 0xC940, + /* field numbers */ 5, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_REG_ADDR_AI_PORT5_FIELDS + }, + { /* register name MACSEC_REG_RWD_PTP_PORT5 */ + /* offset address */ 0xC944, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_REG_RWD_PTP_PORT5_FIELDS + }, + { /* register name MACSEC_REG_CMD_PTP_PORT5 */ + /* offset address */ 0xC948, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_REG_CMD_PTP_PORT5_FIELDS + }, + { /* register name UNUSED_005C_PORT5 */ + /* offset address */ 0xC94C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_005C_PORT5_FIELDS + }, + { /* register name UNUSED_0060_PORT5 */ + /* offset address */ 0xC950, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0060_PORT5_FIELDS + }, + { /* register name UNUSED_0064_PORT5 */ + /* offset address */ 0xC954, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0064_PORT5_FIELDS + }, + { /* register name UNUSED_0068_PORT5 */ + /* offset address */ 0xC958, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0068_PORT5_FIELDS + }, + { /* register name UNUSED_006C_PORT5 */ + /* offset address */ 0xC95C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_006C_PORT5_FIELDS + }, + { /* register name UNUSED_0070_PORT5 */ + /* offset address */ 0xC960, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0070_PORT5_FIELDS + }, + { /* register name UNUSED_0074_PORT5 */ + /* offset address */ 0xC964, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0074_PORT5_FIELDS + }, + { /* register name RESERVED_0078_PORT5 */ + /* offset address */ 0xC968, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RESERVED_0078_PORT5_FIELDS + }, + { /* register name RESERVED_007C_PORT5 */ + /* offset address */ 0xC96C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RESERVED_007C_PORT5_FIELDS + }, + { /* register name MACSEC_TXSYSCRCERR_CNT_PORT5 */ + /* offset address */ 0xC970, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXSYSCRCERR_CNT_PORT5_FIELDS + }, + { /* register name MACSEC_TXSYSPKTERR_CNT_PORT5 */ + /* offset address */ 0xC974, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXSYSPKTERR_CNT_PORT5_FIELDS + }, + { /* register name MACSEC_TXSYSOK_CNT_0_PORT5 */ + /* offset address */ 0xC978, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXSYSOK_CNT_0_PORT5_FIELDS + }, + { /* register name MACSEC_TXSYSOK_CNT_2_PORT5 */ + /* offset address */ 0xC97C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXSYSOK_CNT_2_PORT5_FIELDS + }, + { /* register name MACSEC_TXSYSGERR_CNT_PORT5 */ + /* offset address */ 0xC980, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXSYSGERR_CNT_PORT5_FIELDS + }, + { /* register name MACSEC_TXSYSGLPIERR_CNT_PORT5 */ + /* offset address */ 0xC984, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXSYSGLPIERR_CNT_PORT5_FIELDS + }, + { /* register name MACSEC_TXSYS_DBG_PORT5 */ + /* offset address */ 0xC988, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXSYS_DBG_PORT5_FIELDS + }, + { /* register name MACSEC_TX_RX_CNT_INCR_PORT5 */ + /* offset address */ 0xC98C, + /* field numbers */ 18, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TX_RX_CNT_INCR_PORT5_FIELDS + }, + { /* register name MACSEC_TXLINECRCERR_CNT_PORT5 */ + /* offset address */ 0xC990, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXLINECRCERR_CNT_PORT5_FIELDS + }, + { /* register name MACSEC_TXLINEPKTERR_CNT_PORT5 */ + /* offset address */ 0xC994, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXLINEPKTERR_CNT_PORT5_FIELDS + }, + { /* register name MACSEC_TXLINEOK_CNT_0_PORT5 */ + /* offset address */ 0xC998, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXLINEOK_CNT_0_PORT5_FIELDS + }, + { /* register name MACSEC_TXLINEOK_CNT_2_PORT5 */ + /* offset address */ 0xC99C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXLINEOK_CNT_2_PORT5_FIELDS + }, + { /* register name MACSEC_TXLINEDROP_CNT_PORT5 */ + /* offset address */ 0xC9A0, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXLINEDROP_CNT_PORT5_FIELDS + }, + { /* register name MACSEC_TXLINESRT_CNT_PORT5 */ + /* offset address */ 0xC9A4, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXLINESRT_CNT_PORT5_FIELDS + }, + { /* register name MACSEC_TXLINEGERR_CNT_PORT5 */ + /* offset address */ 0xC9A8, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXLINEGERR_CNT_PORT5_FIELDS + }, + { /* register name MACSEC_TXLINE_DBG_PORT5 */ + /* offset address */ 0xC9AC, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXLINE_DBG_PORT5_FIELDS + }, + { /* register name MACSEC_RXLINECRCERR_CNT_PORT5 */ + /* offset address */ 0xC9B0, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXLINECRCERR_CNT_PORT5_FIELDS + }, + { /* register name MACSEC_RXLINEPKTERR_CNT_PORT5 */ + /* offset address */ 0xC9B4, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXLINEPKTERR_CNT_PORT5_FIELDS + }, + { /* register name MACSEC_RXLINEOK_CNT_0_PORT5 */ + /* offset address */ 0xC9B8, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXLINEOK_CNT_0_PORT5_FIELDS + }, + { /* register name MACSEC_RXLINEOK_CNT_2_PORT5 */ + /* offset address */ 0xC9BC, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXLINEOK_CNT_2_PORT5_FIELDS + }, + { /* register name MACSEC_RXLINESRT_CNT_PORT5 */ + /* offset address */ 0xC9C0, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXLINESRT_CNT_PORT5_FIELDS + }, + { /* register name MACSEC_RXLINEGERR_CNT_PORT5 */ + /* offset address */ 0xC9C4, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXLINEGERR_CNT_PORT5_FIELDS + }, + { /* register name MACSEC_RXLINEGLPIERR_CNT_PORT5 */ + /* offset address */ 0xC9C8, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXLINEGLPIERR_CNT_PORT5_FIELDS + }, + { /* register name MACSEC_RXLINE_DBG_PORT5 */ + /* offset address */ 0xC9CC, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXLINE_DBG_PORT5_FIELDS + }, + { /* register name MACSEC_RXSYSCRCERR_CNT_PORT5 */ + /* offset address */ 0xC9D0, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXSYSCRCERR_CNT_PORT5_FIELDS + }, + { /* register name MACSEC_RXSYSPKTERR_CNT_PORT5 */ + /* offset address */ 0xC9D4, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXSYSPKTERR_CNT_PORT5_FIELDS + }, + { /* register name MACSEC_RXSYSOK_CNT_0_PORT5 */ + /* offset address */ 0xC9D8, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXSYSOK_CNT_0_PORT5_FIELDS + }, + { /* register name MACSEC_RXSYSOK_CNT_2_PORT5 */ + /* offset address */ 0xC9DC, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXSYSOK_CNT_2_PORT5_FIELDS + }, + { /* register name MACSEC_RXSYSDROP_CNT_PORT5 */ + /* offset address */ 0xC9E0, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXSYSDROP_CNT_PORT5_FIELDS + }, + { /* register name MACSEC_RXSYSSRT_CNT_PORT5 */ + /* offset address */ 0xC9E4, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXSYSSRT_CNT_PORT5_FIELDS + }, + { /* register name MACSEC_RXSYSGERR_CNT_PORT5 */ + /* offset address */ 0xC9E8, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXSYSGERR_CNT_PORT5_FIELDS + }, + { /* register name MACSEC_RXSYS_DBG_PORT5 */ + /* offset address */ 0xC9EC, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXSYS_DBG_PORT5_FIELDS + }, + { /* register name MACSEC_TXSYS_CFG1_PORT5 */ + /* offset address */ 0xC9F0, + /* field numbers */ 6, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXSYS_CFG1_PORT5_FIELDS + }, + { /* register name MACSEC_TXSYS_PTPCFG_PORT5 */ + /* offset address */ 0xC9F4, + /* field numbers */ 8, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXSYS_PTPCFG_PORT5_FIELDS + }, + { /* register name MACSEC_TXSYS_OUTERVLAN2_PORT5 */ + /* offset address */ 0xC9F8, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXSYS_OUTERVLAN2_PORT5_FIELDS + }, + { /* register name MACSEC_TXSYS_OUTERVLAN4_PORT5 */ + /* offset address */ 0xC9FC, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXSYS_OUTERVLAN4_PORT5_FIELDS + }, + { /* register name MACSEC_TXSYS_INNERVLAN2_PORT5 */ + /* offset address */ 0xCA00, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXSYS_INNERVLAN2_PORT5_FIELDS + }, + { /* register name MACSEC_TXSYS_INNERVLAN4_PORT5 */ + /* offset address */ 0xCA04, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXSYS_INNERVLAN4_PORT5_FIELDS + }, + { /* register name MACSEC_TXSYS_INNERVLAN6_PORT5 */ + /* offset address */ 0xCA08, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXSYS_INNERVLAN6_PORT5_FIELDS + }, + { /* register name UNUSED_011C_PORT5 */ + /* offset address */ 0xCA0C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_011C_PORT5_FIELDS + }, + { /* register name UNUSED_0120_PORT5 */ + /* offset address */ 0xCA10, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0120_PORT5_FIELDS + }, + { /* register name UNUSED_0124_PORT5 */ + /* offset address */ 0xCA14, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0124_PORT5_FIELDS + }, + { /* register name UNUSED_0128_PORT5 */ + /* offset address */ 0xCA18, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0128_PORT5_FIELDS + }, + { /* register name UNUSED_012C_PORT5 */ + /* offset address */ 0xCA1C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_012C_PORT5_FIELDS + }, + { /* register name UNUSED_0130_PORT5 */ + /* offset address */ 0xCA20, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0130_PORT5_FIELDS + }, + { /* register name UNUSED_0134_PORT5 */ + /* offset address */ 0xCA24, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0134_PORT5_FIELDS + }, + { /* register name UNUSED_0138_PORT5 */ + /* offset address */ 0xCA28, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0138_PORT5_FIELDS + }, + { /* register name UNUSED_013C_PORT5 */ + /* offset address */ 0xCA2C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_013C_PORT5_FIELDS + }, + { /* register name MACSEC_TXLINE_CFG1_PORT5 */ + /* offset address */ 0xCA30, + /* field numbers */ 5, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXLINE_CFG1_PORT5_FIELDS + }, + { /* register name MACSEC_TXLINE_CFG3_PORT5 */ + /* offset address */ 0xCA34, + /* field numbers */ 13, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXLINE_CFG3_PORT5_FIELDS + }, + { /* register name MACSEC_TXLINE_CFG5_PORT5 */ + /* offset address */ 0xCA38, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXLINE_CFG5_PORT5_FIELDS + }, + { /* register name UNUSED_014C_PORT5 */ + /* offset address */ 0xCA3C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_014C_PORT5_FIELDS + }, + { /* register name UNUSED_0150_PORT5 */ + /* offset address */ 0xCA40, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0150_PORT5_FIELDS + }, + { /* register name UNUSED_0154_PORT5 */ + /* offset address */ 0xCA44, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0154_PORT5_FIELDS + }, + { /* register name UNUSED_0158_PORT5 */ + /* offset address */ 0xCA48, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0158_PORT5_FIELDS + }, + { /* register name UNUSED_015C_PORT5 */ + /* offset address */ 0xCA4C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_015C_PORT5_FIELDS + }, + { /* register name UNUSED_0160_PORT5 */ + /* offset address */ 0xCA50, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0160_PORT5_FIELDS + }, + { /* register name UNUSED_0164_PORT5 */ + /* offset address */ 0xCA54, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0164_PORT5_FIELDS + }, + { /* register name UNUSED_0168_PORT5 */ + /* offset address */ 0xCA58, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0168_PORT5_FIELDS + }, + { /* register name UNUSED_016C_PORT5 */ + /* offset address */ 0xCA5C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_016C_PORT5_FIELDS + }, + { /* register name UNUSED_0170_PORT5 */ + /* offset address */ 0xCA60, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0170_PORT5_FIELDS + }, + { /* register name UNUSED_0174_PORT5 */ + /* offset address */ 0xCA64, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0174_PORT5_FIELDS + }, + { /* register name UNUSED_0178_PORT5 */ + /* offset address */ 0xCA68, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0178_PORT5_FIELDS + }, + { /* register name UNUSED_017C_PORT5 */ + /* offset address */ 0xCA6C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_017C_PORT5_FIELDS + }, + { /* register name MACSEC_RXLINE_CFG1_PORT5 */ + /* offset address */ 0xCA70, + /* field numbers */ 6, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXLINE_CFG1_PORT5_FIELDS + }, + { /* register name UNUSED_0184_PORT5 */ + /* offset address */ 0xCA74, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0184_PORT5_FIELDS + }, + { /* register name UNUSED_0188_PORT5 */ + /* offset address */ 0xCA78, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0188_PORT5_FIELDS + }, + { /* register name UNUSED_018C_PORT5 */ + /* offset address */ 0xCA7C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_018C_PORT5_FIELDS + }, + { /* register name UNUSED_0190_PORT5 */ + /* offset address */ 0xCA80, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0190_PORT5_FIELDS + }, + { /* register name UNUSED_0194_PORT5 */ + /* offset address */ 0xCA84, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0194_PORT5_FIELDS + }, + { /* register name UNUSED_0198_PORT5 */ + /* offset address */ 0xCA88, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0198_PORT5_FIELDS + }, + { /* register name UNUSED_019C_PORT5 */ + /* offset address */ 0xCA8C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_019C_PORT5_FIELDS + }, + { /* register name UNUSED_01A0_PORT5 */ + /* offset address */ 0xCA90, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_01A0_PORT5_FIELDS + }, + { /* register name UNUSED_01A4_PORT5 */ + /* offset address */ 0xCA94, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_01A4_PORT5_FIELDS + }, + { /* register name UNUSED_01A8_PORT5 */ + /* offset address */ 0xCA98, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_01A8_PORT5_FIELDS + }, + { /* register name UNUSED_01AC_PORT5 */ + /* offset address */ 0xCA9C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_01AC_PORT5_FIELDS + }, + { /* register name UNUSED_01B0_PORT5 */ + /* offset address */ 0xCAA0, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_01B0_PORT5_FIELDS + }, + { /* register name UNUSED_01B4_PORT5 */ + /* offset address */ 0xCAA4, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_01B4_PORT5_FIELDS + }, + { /* register name UNUSED_01B8_PORT5 */ + /* offset address */ 0xCAA8, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_01B8_PORT5_FIELDS + }, + { /* register name UNUSED_01BC_PORT5 */ + /* offset address */ 0xCAAC, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_01BC_PORT5_FIELDS + }, + { /* register name MACSEC_RXSYS_CFG1_PORT5 */ + /* offset address */ 0xCAB0, + /* field numbers */ 5, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXSYS_CFG1_PORT5_FIELDS + }, + { /* register name MACSEC_RXSYS_CFG3_PORT5 */ + /* offset address */ 0xCAB4, + /* field numbers */ 12, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXSYS_CFG3_PORT5_FIELDS + }, + { /* register name MACSEC_RXSYS_OUTERVLAN2_PORT5 */ + /* offset address */ 0xCAB8, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXSYS_OUTERVLAN2_PORT5_FIELDS + }, + { /* register name MACSEC_RXSYS_OUTERVLAN4_PORT5 */ + /* offset address */ 0xCABC, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXSYS_OUTERVLAN4_PORT5_FIELDS + }, + { /* register name MACSEC_RXSYS_INNERVLAN2_PORT5 */ + /* offset address */ 0xCAC0, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXSYS_INNERVLAN2_PORT5_FIELDS + }, + { /* register name MACSEC_RXSYS_INNERVLAN4_PORT5 */ + /* offset address */ 0xCAC4, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXSYS_INNERVLAN4_PORT5_FIELDS + }, + { /* register name MACSEC_RXSYS_INNERVLAN6_PORT5 */ + /* offset address */ 0xCAC8, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXSYS_INNERVLAN6_PORT5_FIELDS + }, + { /* register name MACSEC_RXSYS_CFG4_PORT5 */ + /* offset address */ 0xCACC, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXSYS_CFG4_PORT5_FIELDS + }, + { /* register name MACSEC_RXSYS_CFG6_PORT5 */ + /* offset address */ 0xCAD0, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXSYS_CFG6_PORT5_FIELDS + }, + { /* register name MACSEC_REG_GLB_SET1_PORT6 */ + /* offset address */ 0xD0F0, + /* field numbers */ 27, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_REG_GLB_SET1_PORT6_FIELDS + }, + { /* register name MACSEC_REG_GLB_IMR_PORT6 */ + /* offset address */ 0xD0F4, + /* field numbers */ 10, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_REG_GLB_IMR_PORT6_FIELDS + }, + { /* register name MACSEC_REG_GLB_ISR_PORT6 */ + /* offset address */ 0xD0F8, + /* field numbers */ 10, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_REG_GLB_ISR_PORT6_FIELDS + }, + { /* register name UNUSED_000C_PORT6 */ + /* offset address */ 0xD0FC, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_000C_PORT6_FIELDS + }, + { /* register name MACSEC_PM_CTRL_PORT6 */ + /* offset address */ 0xD100, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_PM_CTRL_PORT6_FIELDS + }, + { /* register name MACSEC_REG_GLB_MASK_PORT6 */ + /* offset address */ 0xD104, + /* field numbers */ 12, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_REG_GLB_MASK_PORT6_FIELDS + }, + { /* register name MACSEC_REG_GLB_SET4_PORT6 */ + /* offset address */ 0xD108, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_REG_GLB_SET4_PORT6_FIELDS + }, + { /* register name MACSEC_REG_IP_PROBE_PORT6 */ + /* offset address */ 0xD10C, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_REG_IP_PROBE_PORT6_FIELDS + }, + { /* register name UNUSED_0020_PORT6 */ + /* offset address */ 0xD110, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0020_PORT6_FIELDS + }, + { /* register name UNUSED_0024_PORT6 */ + /* offset address */ 0xD114, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0024_PORT6_FIELDS + }, + { /* register name MACSEC_MBIST_SA_CTRL_PORT6 */ + /* offset address */ 0xD118, + /* field numbers */ 16, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_MBIST_SA_CTRL_PORT6_FIELDS + }, + { /* register name MACSEC_MBIST_STAT_CTRL_PORT6 */ + /* offset address */ 0xD11C, + /* field numbers */ 28, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_MBIST_STAT_CTRL_PORT6_FIELDS + }, + { /* register name MACSEC_MBIST_SA_AE_TEST_PORT6 */ + /* offset address */ 0xD120, + /* field numbers */ 20, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_MBIST_SA_AE_TEST_PORT6_FIELDS + }, + { /* register name MACSEC_MBIST_STAT_AE_TEST_PORT6 */ + /* offset address */ 0xD124, + /* field numbers */ 16, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_MBIST_STAT_AE_TEST_PORT6_FIELDS + }, + { /* register name MACSEC_MBIST_SA_FAIL_PORT6 */ + /* offset address */ 0xD128, + /* field numbers */ 21, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_MBIST_SA_FAIL_PORT6_FIELDS + }, + { /* register name MACSEC_XGLBK_FIFO_DBG_PORT6 */ + /* offset address */ 0xD12C, + /* field numbers */ 10, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_XGLBK_FIFO_DBG_PORT6_FIELDS + }, + { /* register name MACSEC_REG_RWDH_AE_PORT6 */ + /* offset address */ 0xD130, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_REG_RWDH_AE_PORT6_FIELDS + }, + { /* register name MACSEC_REG_ADDR_AE_PORT6 */ + /* offset address */ 0xD134, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_REG_ADDR_AE_PORT6_FIELDS + }, + { /* register name MACSEC_REG_CMD_AE_PORT6 */ + /* offset address */ 0xD138, + /* field numbers */ 5, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_REG_CMD_AE_PORT6_FIELDS + }, + { /* register name MACSEC_REG_RWDL_AI_PORT6 */ + /* offset address */ 0xD13C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_REG_RWDL_AI_PORT6_FIELDS + }, + { /* register name MACSEC_REG_ADDR_AI_PORT6 */ + /* offset address */ 0xD140, + /* field numbers */ 5, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_REG_ADDR_AI_PORT6_FIELDS + }, + { /* register name MACSEC_REG_RWD_PTP_PORT6 */ + /* offset address */ 0xD144, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_REG_RWD_PTP_PORT6_FIELDS + }, + { /* register name MACSEC_REG_CMD_PTP_PORT6 */ + /* offset address */ 0xD148, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_REG_CMD_PTP_PORT6_FIELDS + }, + { /* register name UNUSED_005C_PORT6 */ + /* offset address */ 0xD14C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_005C_PORT6_FIELDS + }, + { /* register name UNUSED_0060_PORT6 */ + /* offset address */ 0xD150, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0060_PORT6_FIELDS + }, + { /* register name UNUSED_0064_PORT6 */ + /* offset address */ 0xD154, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0064_PORT6_FIELDS + }, + { /* register name UNUSED_0068_PORT6 */ + /* offset address */ 0xD158, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0068_PORT6_FIELDS + }, + { /* register name UNUSED_006C_PORT6 */ + /* offset address */ 0xD15C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_006C_PORT6_FIELDS + }, + { /* register name UNUSED_0070_PORT6 */ + /* offset address */ 0xD160, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0070_PORT6_FIELDS + }, + { /* register name UNUSED_0074_PORT6 */ + /* offset address */ 0xD164, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0074_PORT6_FIELDS + }, + { /* register name RESERVED_0078_PORT6 */ + /* offset address */ 0xD168, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RESERVED_0078_PORT6_FIELDS + }, + { /* register name RESERVED_007C_PORT6 */ + /* offset address */ 0xD16C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RESERVED_007C_PORT6_FIELDS + }, + { /* register name MACSEC_TXSYSCRCERR_CNT_PORT6 */ + /* offset address */ 0xD170, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXSYSCRCERR_CNT_PORT6_FIELDS + }, + { /* register name MACSEC_TXSYSPKTERR_CNT_PORT6 */ + /* offset address */ 0xD174, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXSYSPKTERR_CNT_PORT6_FIELDS + }, + { /* register name MACSEC_TXSYSOK_CNT_0_PORT6 */ + /* offset address */ 0xD178, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXSYSOK_CNT_0_PORT6_FIELDS + }, + { /* register name MACSEC_TXSYSOK_CNT_2_PORT6 */ + /* offset address */ 0xD17C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXSYSOK_CNT_2_PORT6_FIELDS + }, + { /* register name MACSEC_TXSYSGERR_CNT_PORT6 */ + /* offset address */ 0xD180, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXSYSGERR_CNT_PORT6_FIELDS + }, + { /* register name MACSEC_TXSYSGLPIERR_CNT_PORT6 */ + /* offset address */ 0xD184, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXSYSGLPIERR_CNT_PORT6_FIELDS + }, + { /* register name MACSEC_TXSYS_DBG_PORT6 */ + /* offset address */ 0xD188, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXSYS_DBG_PORT6_FIELDS + }, + { /* register name MACSEC_TX_RX_CNT_INCR_PORT6 */ + /* offset address */ 0xD18C, + /* field numbers */ 18, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TX_RX_CNT_INCR_PORT6_FIELDS + }, + { /* register name MACSEC_TXLINECRCERR_CNT_PORT6 */ + /* offset address */ 0xD190, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXLINECRCERR_CNT_PORT6_FIELDS + }, + { /* register name MACSEC_TXLINEPKTERR_CNT_PORT6 */ + /* offset address */ 0xD194, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXLINEPKTERR_CNT_PORT6_FIELDS + }, + { /* register name MACSEC_TXLINEOK_CNT_0_PORT6 */ + /* offset address */ 0xD198, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXLINEOK_CNT_0_PORT6_FIELDS + }, + { /* register name MACSEC_TXLINEOK_CNT_2_PORT6 */ + /* offset address */ 0xD19C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXLINEOK_CNT_2_PORT6_FIELDS + }, + { /* register name MACSEC_TXLINEDROP_CNT_PORT6 */ + /* offset address */ 0xD1A0, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXLINEDROP_CNT_PORT6_FIELDS + }, + { /* register name MACSEC_TXLINESRT_CNT_PORT6 */ + /* offset address */ 0xD1A4, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXLINESRT_CNT_PORT6_FIELDS + }, + { /* register name MACSEC_TXLINEGERR_CNT_PORT6 */ + /* offset address */ 0xD1A8, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXLINEGERR_CNT_PORT6_FIELDS + }, + { /* register name MACSEC_TXLINE_DBG_PORT6 */ + /* offset address */ 0xD1AC, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXLINE_DBG_PORT6_FIELDS + }, + { /* register name MACSEC_RXLINECRCERR_CNT_PORT6 */ + /* offset address */ 0xD1B0, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXLINECRCERR_CNT_PORT6_FIELDS + }, + { /* register name MACSEC_RXLINEPKTERR_CNT_PORT6 */ + /* offset address */ 0xD1B4, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXLINEPKTERR_CNT_PORT6_FIELDS + }, + { /* register name MACSEC_RXLINEOK_CNT_0_PORT6 */ + /* offset address */ 0xD1B8, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXLINEOK_CNT_0_PORT6_FIELDS + }, + { /* register name MACSEC_RXLINEOK_CNT_2_PORT6 */ + /* offset address */ 0xD1BC, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXLINEOK_CNT_2_PORT6_FIELDS + }, + { /* register name MACSEC_RXLINESRT_CNT_PORT6 */ + /* offset address */ 0xD1C0, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXLINESRT_CNT_PORT6_FIELDS + }, + { /* register name MACSEC_RXLINEGERR_CNT_PORT6 */ + /* offset address */ 0xD1C4, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXLINEGERR_CNT_PORT6_FIELDS + }, + { /* register name MACSEC_RXLINEGLPIERR_CNT_PORT6 */ + /* offset address */ 0xD1C8, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXLINEGLPIERR_CNT_PORT6_FIELDS + }, + { /* register name MACSEC_RXLINE_DBG_PORT6 */ + /* offset address */ 0xD1CC, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXLINE_DBG_PORT6_FIELDS + }, + { /* register name MACSEC_RXSYSCRCERR_CNT_PORT6 */ + /* offset address */ 0xD1D0, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXSYSCRCERR_CNT_PORT6_FIELDS + }, + { /* register name MACSEC_RXSYSPKTERR_CNT_PORT6 */ + /* offset address */ 0xD1D4, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXSYSPKTERR_CNT_PORT6_FIELDS + }, + { /* register name MACSEC_RXSYSOK_CNT_0_PORT6 */ + /* offset address */ 0xD1D8, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXSYSOK_CNT_0_PORT6_FIELDS + }, + { /* register name MACSEC_RXSYSOK_CNT_2_PORT6 */ + /* offset address */ 0xD1DC, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXSYSOK_CNT_2_PORT6_FIELDS + }, + { /* register name MACSEC_RXSYSDROP_CNT_PORT6 */ + /* offset address */ 0xD1E0, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXSYSDROP_CNT_PORT6_FIELDS + }, + { /* register name MACSEC_RXSYSSRT_CNT_PORT6 */ + /* offset address */ 0xD1E4, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXSYSSRT_CNT_PORT6_FIELDS + }, + { /* register name MACSEC_RXSYSGERR_CNT_PORT6 */ + /* offset address */ 0xD1E8, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXSYSGERR_CNT_PORT6_FIELDS + }, + { /* register name MACSEC_RXSYS_DBG_PORT6 */ + /* offset address */ 0xD1EC, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXSYS_DBG_PORT6_FIELDS + }, + { /* register name MACSEC_TXSYS_CFG1_PORT6 */ + /* offset address */ 0xD1F0, + /* field numbers */ 6, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXSYS_CFG1_PORT6_FIELDS + }, + { /* register name MACSEC_TXSYS_PTPCFG_PORT6 */ + /* offset address */ 0xD1F4, + /* field numbers */ 8, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXSYS_PTPCFG_PORT6_FIELDS + }, + { /* register name MACSEC_TXSYS_OUTERVLAN2_PORT6 */ + /* offset address */ 0xD1F8, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXSYS_OUTERVLAN2_PORT6_FIELDS + }, + { /* register name MACSEC_TXSYS_OUTERVLAN4_PORT6 */ + /* offset address */ 0xD1FC, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXSYS_OUTERVLAN4_PORT6_FIELDS + }, + { /* register name MACSEC_TXSYS_INNERVLAN2_PORT6 */ + /* offset address */ 0xD200, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXSYS_INNERVLAN2_PORT6_FIELDS + }, + { /* register name MACSEC_TXSYS_INNERVLAN4_PORT6 */ + /* offset address */ 0xD204, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXSYS_INNERVLAN4_PORT6_FIELDS + }, + { /* register name MACSEC_TXSYS_INNERVLAN6_PORT6 */ + /* offset address */ 0xD208, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXSYS_INNERVLAN6_PORT6_FIELDS + }, + { /* register name UNUSED_011C_PORT6 */ + /* offset address */ 0xD20C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_011C_PORT6_FIELDS + }, + { /* register name UNUSED_0120_PORT6 */ + /* offset address */ 0xD210, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0120_PORT6_FIELDS + }, + { /* register name UNUSED_0124_PORT6 */ + /* offset address */ 0xD214, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0124_PORT6_FIELDS + }, + { /* register name UNUSED_0128_PORT6 */ + /* offset address */ 0xD218, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0128_PORT6_FIELDS + }, + { /* register name UNUSED_012C_PORT6 */ + /* offset address */ 0xD21C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_012C_PORT6_FIELDS + }, + { /* register name UNUSED_0130_PORT6 */ + /* offset address */ 0xD220, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0130_PORT6_FIELDS + }, + { /* register name UNUSED_0134_PORT6 */ + /* offset address */ 0xD224, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0134_PORT6_FIELDS + }, + { /* register name UNUSED_0138_PORT6 */ + /* offset address */ 0xD228, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0138_PORT6_FIELDS + }, + { /* register name UNUSED_013C_PORT6 */ + /* offset address */ 0xD22C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_013C_PORT6_FIELDS + }, + { /* register name MACSEC_TXLINE_CFG1_PORT6 */ + /* offset address */ 0xD230, + /* field numbers */ 5, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXLINE_CFG1_PORT6_FIELDS + }, + { /* register name MACSEC_TXLINE_CFG3_PORT6 */ + /* offset address */ 0xD234, + /* field numbers */ 13, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXLINE_CFG3_PORT6_FIELDS + }, + { /* register name MACSEC_TXLINE_CFG5_PORT6 */ + /* offset address */ 0xD238, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXLINE_CFG5_PORT6_FIELDS + }, + { /* register name UNUSED_014C_PORT6 */ + /* offset address */ 0xD23C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_014C_PORT6_FIELDS + }, + { /* register name UNUSED_0150_PORT6 */ + /* offset address */ 0xD240, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0150_PORT6_FIELDS + }, + { /* register name UNUSED_0154_PORT6 */ + /* offset address */ 0xD244, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0154_PORT6_FIELDS + }, + { /* register name UNUSED_0158_PORT6 */ + /* offset address */ 0xD248, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0158_PORT6_FIELDS + }, + { /* register name UNUSED_015C_PORT6 */ + /* offset address */ 0xD24C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_015C_PORT6_FIELDS + }, + { /* register name UNUSED_0160_PORT6 */ + /* offset address */ 0xD250, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0160_PORT6_FIELDS + }, + { /* register name UNUSED_0164_PORT6 */ + /* offset address */ 0xD254, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0164_PORT6_FIELDS + }, + { /* register name UNUSED_0168_PORT6 */ + /* offset address */ 0xD258, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0168_PORT6_FIELDS + }, + { /* register name UNUSED_016C_PORT6 */ + /* offset address */ 0xD25C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_016C_PORT6_FIELDS + }, + { /* register name UNUSED_0170_PORT6 */ + /* offset address */ 0xD260, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0170_PORT6_FIELDS + }, + { /* register name UNUSED_0174_PORT6 */ + /* offset address */ 0xD264, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0174_PORT6_FIELDS + }, + { /* register name UNUSED_0178_PORT6 */ + /* offset address */ 0xD268, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0178_PORT6_FIELDS + }, + { /* register name UNUSED_017C_PORT6 */ + /* offset address */ 0xD26C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_017C_PORT6_FIELDS + }, + { /* register name MACSEC_RXLINE_CFG1_PORT6 */ + /* offset address */ 0xD270, + /* field numbers */ 6, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXLINE_CFG1_PORT6_FIELDS + }, + { /* register name UNUSED_0184_PORT6 */ + /* offset address */ 0xD274, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0184_PORT6_FIELDS + }, + { /* register name UNUSED_0188_PORT6 */ + /* offset address */ 0xD278, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0188_PORT6_FIELDS + }, + { /* register name UNUSED_018C_PORT6 */ + /* offset address */ 0xD27C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_018C_PORT6_FIELDS + }, + { /* register name UNUSED_0190_PORT6 */ + /* offset address */ 0xD280, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0190_PORT6_FIELDS + }, + { /* register name UNUSED_0194_PORT6 */ + /* offset address */ 0xD284, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0194_PORT6_FIELDS + }, + { /* register name UNUSED_0198_PORT6 */ + /* offset address */ 0xD288, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0198_PORT6_FIELDS + }, + { /* register name UNUSED_019C_PORT6 */ + /* offset address */ 0xD28C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_019C_PORT6_FIELDS + }, + { /* register name UNUSED_01A0_PORT6 */ + /* offset address */ 0xD290, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_01A0_PORT6_FIELDS + }, + { /* register name UNUSED_01A4_PORT6 */ + /* offset address */ 0xD294, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_01A4_PORT6_FIELDS + }, + { /* register name UNUSED_01A8_PORT6 */ + /* offset address */ 0xD298, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_01A8_PORT6_FIELDS + }, + { /* register name UNUSED_01AC_PORT6 */ + /* offset address */ 0xD29C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_01AC_PORT6_FIELDS + }, + { /* register name UNUSED_01B0_PORT6 */ + /* offset address */ 0xD2A0, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_01B0_PORT6_FIELDS + }, + { /* register name UNUSED_01B4_PORT6 */ + /* offset address */ 0xD2A4, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_01B4_PORT6_FIELDS + }, + { /* register name UNUSED_01B8_PORT6 */ + /* offset address */ 0xD2A8, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_01B8_PORT6_FIELDS + }, + { /* register name UNUSED_01BC_PORT6 */ + /* offset address */ 0xD2AC, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_01BC_PORT6_FIELDS + }, + { /* register name MACSEC_RXSYS_CFG1_PORT6 */ + /* offset address */ 0xD2B0, + /* field numbers */ 5, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXSYS_CFG1_PORT6_FIELDS + }, + { /* register name MACSEC_RXSYS_CFG3_PORT6 */ + /* offset address */ 0xD2B4, + /* field numbers */ 12, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXSYS_CFG3_PORT6_FIELDS + }, + { /* register name MACSEC_RXSYS_OUTERVLAN2_PORT6 */ + /* offset address */ 0xD2B8, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXSYS_OUTERVLAN2_PORT6_FIELDS + }, + { /* register name MACSEC_RXSYS_OUTERVLAN4_PORT6 */ + /* offset address */ 0xD2BC, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXSYS_OUTERVLAN4_PORT6_FIELDS + }, + { /* register name MACSEC_RXSYS_INNERVLAN2_PORT6 */ + /* offset address */ 0xD2C0, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXSYS_INNERVLAN2_PORT6_FIELDS + }, + { /* register name MACSEC_RXSYS_INNERVLAN4_PORT6 */ + /* offset address */ 0xD2C4, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXSYS_INNERVLAN4_PORT6_FIELDS + }, + { /* register name MACSEC_RXSYS_INNERVLAN6_PORT6 */ + /* offset address */ 0xD2C8, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXSYS_INNERVLAN6_PORT6_FIELDS + }, + { /* register name MACSEC_RXSYS_CFG4_PORT6 */ + /* offset address */ 0xD2CC, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXSYS_CFG4_PORT6_FIELDS + }, + { /* register name MACSEC_RXSYS_CFG6_PORT6 */ + /* offset address */ 0xD2D0, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXSYS_CFG6_PORT6_FIELDS + }, + { /* register name MACSEC_REG_GLB_SET1_PORT7 */ + /* offset address */ 0xD8F0, + /* field numbers */ 27, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_REG_GLB_SET1_PORT7_FIELDS + }, + { /* register name MACSEC_REG_GLB_IMR_PORT7 */ + /* offset address */ 0xD8F4, + /* field numbers */ 10, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_REG_GLB_IMR_PORT7_FIELDS + }, + { /* register name MACSEC_REG_GLB_ISR_PORT7 */ + /* offset address */ 0xD8F8, + /* field numbers */ 10, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_REG_GLB_ISR_PORT7_FIELDS + }, + { /* register name UNUSED_000C_PORT7 */ + /* offset address */ 0xD8FC, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_000C_PORT7_FIELDS + }, + { /* register name MACSEC_PM_CTRL_PORT7 */ + /* offset address */ 0xD900, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_PM_CTRL_PORT7_FIELDS + }, + { /* register name MACSEC_REG_GLB_MASK_PORT7 */ + /* offset address */ 0xD904, + /* field numbers */ 12, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_REG_GLB_MASK_PORT7_FIELDS + }, + { /* register name MACSEC_REG_GLB_SET4_PORT7 */ + /* offset address */ 0xD908, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_REG_GLB_SET4_PORT7_FIELDS + }, + { /* register name MACSEC_REG_IP_PROBE_PORT7 */ + /* offset address */ 0xD90C, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_REG_IP_PROBE_PORT7_FIELDS + }, + { /* register name UNUSED_0020_PORT7 */ + /* offset address */ 0xD910, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0020_PORT7_FIELDS + }, + { /* register name UNUSED_0024_PORT7 */ + /* offset address */ 0xD914, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0024_PORT7_FIELDS + }, + { /* register name MACSEC_MBIST_SA_CTRL_PORT7 */ + /* offset address */ 0xD918, + /* field numbers */ 16, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_MBIST_SA_CTRL_PORT7_FIELDS + }, + { /* register name MACSEC_MBIST_STAT_CTRL_PORT7 */ + /* offset address */ 0xD91C, + /* field numbers */ 28, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_MBIST_STAT_CTRL_PORT7_FIELDS + }, + { /* register name MACSEC_MBIST_SA_AE_TEST_PORT7 */ + /* offset address */ 0xD920, + /* field numbers */ 20, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_MBIST_SA_AE_TEST_PORT7_FIELDS + }, + { /* register name MACSEC_MBIST_STAT_AE_TEST_PORT7 */ + /* offset address */ 0xD924, + /* field numbers */ 16, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_MBIST_STAT_AE_TEST_PORT7_FIELDS + }, + { /* register name MACSEC_MBIST_SA_FAIL_PORT7 */ + /* offset address */ 0xD928, + /* field numbers */ 21, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_MBIST_SA_FAIL_PORT7_FIELDS + }, + { /* register name MACSEC_XGLBK_FIFO_DBG_PORT7 */ + /* offset address */ 0xD92C, + /* field numbers */ 10, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_XGLBK_FIFO_DBG_PORT7_FIELDS + }, + { /* register name MACSEC_REG_RWDH_AE_PORT7 */ + /* offset address */ 0xD930, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_REG_RWDH_AE_PORT7_FIELDS + }, + { /* register name MACSEC_REG_ADDR_AE_PORT7 */ + /* offset address */ 0xD934, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_REG_ADDR_AE_PORT7_FIELDS + }, + { /* register name MACSEC_REG_CMD_AE_PORT7 */ + /* offset address */ 0xD938, + /* field numbers */ 5, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_REG_CMD_AE_PORT7_FIELDS + }, + { /* register name MACSEC_REG_RWDL_AI_PORT7 */ + /* offset address */ 0xD93C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_REG_RWDL_AI_PORT7_FIELDS + }, + { /* register name MACSEC_REG_ADDR_AI_PORT7 */ + /* offset address */ 0xD940, + /* field numbers */ 5, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_REG_ADDR_AI_PORT7_FIELDS + }, + { /* register name MACSEC_REG_RWD_PTP_PORT7 */ + /* offset address */ 0xD944, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_REG_RWD_PTP_PORT7_FIELDS + }, + { /* register name MACSEC_REG_CMD_PTP_PORT7 */ + /* offset address */ 0xD948, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_REG_CMD_PTP_PORT7_FIELDS + }, + { /* register name UNUSED_005C_PORT7 */ + /* offset address */ 0xD94C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_005C_PORT7_FIELDS + }, + { /* register name UNUSED_0060_PORT7 */ + /* offset address */ 0xD950, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0060_PORT7_FIELDS + }, + { /* register name UNUSED_0064_PORT7 */ + /* offset address */ 0xD954, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0064_PORT7_FIELDS + }, + { /* register name UNUSED_0068_PORT7 */ + /* offset address */ 0xD958, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0068_PORT7_FIELDS + }, + { /* register name UNUSED_006C_PORT7 */ + /* offset address */ 0xD95C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_006C_PORT7_FIELDS + }, + { /* register name UNUSED_0070_PORT7 */ + /* offset address */ 0xD960, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0070_PORT7_FIELDS + }, + { /* register name UNUSED_0074_PORT7 */ + /* offset address */ 0xD964, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0074_PORT7_FIELDS + }, + { /* register name RESERVED_0078_PORT7 */ + /* offset address */ 0xD968, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RESERVED_0078_PORT7_FIELDS + }, + { /* register name RESERVED_007C_PORT7 */ + /* offset address */ 0xD96C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RESERVED_007C_PORT7_FIELDS + }, + { /* register name MACSEC_TXSYSCRCERR_CNT_PORT7 */ + /* offset address */ 0xD970, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXSYSCRCERR_CNT_PORT7_FIELDS + }, + { /* register name MACSEC_TXSYSPKTERR_CNT_PORT7 */ + /* offset address */ 0xD974, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXSYSPKTERR_CNT_PORT7_FIELDS + }, + { /* register name MACSEC_TXSYSOK_CNT_0_PORT7 */ + /* offset address */ 0xD978, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXSYSOK_CNT_0_PORT7_FIELDS + }, + { /* register name MACSEC_TXSYSOK_CNT_2_PORT7 */ + /* offset address */ 0xD97C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXSYSOK_CNT_2_PORT7_FIELDS + }, + { /* register name MACSEC_TXSYSGERR_CNT_PORT7 */ + /* offset address */ 0xD980, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXSYSGERR_CNT_PORT7_FIELDS + }, + { /* register name MACSEC_TXSYSGLPIERR_CNT_PORT7 */ + /* offset address */ 0xD984, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXSYSGLPIERR_CNT_PORT7_FIELDS + }, + { /* register name MACSEC_TXSYS_DBG_PORT7 */ + /* offset address */ 0xD988, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXSYS_DBG_PORT7_FIELDS + }, + { /* register name MACSEC_TX_RX_CNT_INCR_PORT7 */ + /* offset address */ 0xD98C, + /* field numbers */ 18, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TX_RX_CNT_INCR_PORT7_FIELDS + }, + { /* register name MACSEC_TXLINECRCERR_CNT_PORT7 */ + /* offset address */ 0xD990, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXLINECRCERR_CNT_PORT7_FIELDS + }, + { /* register name MACSEC_TXLINEPKTERR_CNT_PORT7 */ + /* offset address */ 0xD994, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXLINEPKTERR_CNT_PORT7_FIELDS + }, + { /* register name MACSEC_TXLINEOK_CNT_0_PORT7 */ + /* offset address */ 0xD998, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXLINEOK_CNT_0_PORT7_FIELDS + }, + { /* register name MACSEC_TXLINEOK_CNT_2_PORT7 */ + /* offset address */ 0xD99C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXLINEOK_CNT_2_PORT7_FIELDS + }, + { /* register name MACSEC_TXLINEDROP_CNT_PORT7 */ + /* offset address */ 0xD9A0, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXLINEDROP_CNT_PORT7_FIELDS + }, + { /* register name MACSEC_TXLINESRT_CNT_PORT7 */ + /* offset address */ 0xD9A4, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXLINESRT_CNT_PORT7_FIELDS + }, + { /* register name MACSEC_TXLINEGERR_CNT_PORT7 */ + /* offset address */ 0xD9A8, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXLINEGERR_CNT_PORT7_FIELDS + }, + { /* register name MACSEC_TXLINE_DBG_PORT7 */ + /* offset address */ 0xD9AC, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXLINE_DBG_PORT7_FIELDS + }, + { /* register name MACSEC_RXLINECRCERR_CNT_PORT7 */ + /* offset address */ 0xD9B0, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXLINECRCERR_CNT_PORT7_FIELDS + }, + { /* register name MACSEC_RXLINEPKTERR_CNT_PORT7 */ + /* offset address */ 0xD9B4, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXLINEPKTERR_CNT_PORT7_FIELDS + }, + { /* register name MACSEC_RXLINEOK_CNT_0_PORT7 */ + /* offset address */ 0xD9B8, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXLINEOK_CNT_0_PORT7_FIELDS + }, + { /* register name MACSEC_RXLINEOK_CNT_2_PORT7 */ + /* offset address */ 0xD9BC, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXLINEOK_CNT_2_PORT7_FIELDS + }, + { /* register name MACSEC_RXLINESRT_CNT_PORT7 */ + /* offset address */ 0xD9C0, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXLINESRT_CNT_PORT7_FIELDS + }, + { /* register name MACSEC_RXLINEGERR_CNT_PORT7 */ + /* offset address */ 0xD9C4, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXLINEGERR_CNT_PORT7_FIELDS + }, + { /* register name MACSEC_RXLINEGLPIERR_CNT_PORT7 */ + /* offset address */ 0xD9C8, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXLINEGLPIERR_CNT_PORT7_FIELDS + }, + { /* register name MACSEC_RXLINE_DBG_PORT7 */ + /* offset address */ 0xD9CC, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXLINE_DBG_PORT7_FIELDS + }, + { /* register name MACSEC_RXSYSCRCERR_CNT_PORT7 */ + /* offset address */ 0xD9D0, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXSYSCRCERR_CNT_PORT7_FIELDS + }, + { /* register name MACSEC_RXSYSPKTERR_CNT_PORT7 */ + /* offset address */ 0xD9D4, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXSYSPKTERR_CNT_PORT7_FIELDS + }, + { /* register name MACSEC_RXSYSOK_CNT_0_PORT7 */ + /* offset address */ 0xD9D8, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXSYSOK_CNT_0_PORT7_FIELDS + }, + { /* register name MACSEC_RXSYSOK_CNT_2_PORT7 */ + /* offset address */ 0xD9DC, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXSYSOK_CNT_2_PORT7_FIELDS + }, + { /* register name MACSEC_RXSYSDROP_CNT_PORT7 */ + /* offset address */ 0xD9E0, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXSYSDROP_CNT_PORT7_FIELDS + }, + { /* register name MACSEC_RXSYSSRT_CNT_PORT7 */ + /* offset address */ 0xD9E4, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXSYSSRT_CNT_PORT7_FIELDS + }, + { /* register name MACSEC_RXSYSGERR_CNT_PORT7 */ + /* offset address */ 0xD9E8, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXSYSGERR_CNT_PORT7_FIELDS + }, + { /* register name MACSEC_RXSYS_DBG_PORT7 */ + /* offset address */ 0xD9EC, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXSYS_DBG_PORT7_FIELDS + }, + { /* register name MACSEC_TXSYS_CFG1_PORT7 */ + /* offset address */ 0xD9F0, + /* field numbers */ 6, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXSYS_CFG1_PORT7_FIELDS + }, + { /* register name MACSEC_TXSYS_PTPCFG_PORT7 */ + /* offset address */ 0xD9F4, + /* field numbers */ 8, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXSYS_PTPCFG_PORT7_FIELDS + }, + { /* register name MACSEC_TXSYS_OUTERVLAN2_PORT7 */ + /* offset address */ 0xD9F8, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXSYS_OUTERVLAN2_PORT7_FIELDS + }, + { /* register name MACSEC_TXSYS_OUTERVLAN4_PORT7 */ + /* offset address */ 0xD9FC, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXSYS_OUTERVLAN4_PORT7_FIELDS + }, + { /* register name MACSEC_TXSYS_INNERVLAN2_PORT7 */ + /* offset address */ 0xDA00, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXSYS_INNERVLAN2_PORT7_FIELDS + }, + { /* register name MACSEC_TXSYS_INNERVLAN4_PORT7 */ + /* offset address */ 0xDA04, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXSYS_INNERVLAN4_PORT7_FIELDS + }, + { /* register name MACSEC_TXSYS_INNERVLAN6_PORT7 */ + /* offset address */ 0xDA08, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXSYS_INNERVLAN6_PORT7_FIELDS + }, + { /* register name UNUSED_011C_PORT7 */ + /* offset address */ 0xDA0C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_011C_PORT7_FIELDS + }, + { /* register name UNUSED_0120_PORT7 */ + /* offset address */ 0xDA10, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0120_PORT7_FIELDS + }, + { /* register name UNUSED_0124_PORT7 */ + /* offset address */ 0xDA14, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0124_PORT7_FIELDS + }, + { /* register name UNUSED_0128_PORT7 */ + /* offset address */ 0xDA18, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0128_PORT7_FIELDS + }, + { /* register name UNUSED_012C_PORT7 */ + /* offset address */ 0xDA1C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_012C_PORT7_FIELDS + }, + { /* register name UNUSED_0130_PORT7 */ + /* offset address */ 0xDA20, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0130_PORT7_FIELDS + }, + { /* register name UNUSED_0134_PORT7 */ + /* offset address */ 0xDA24, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0134_PORT7_FIELDS + }, + { /* register name UNUSED_0138_PORT7 */ + /* offset address */ 0xDA28, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0138_PORT7_FIELDS + }, + { /* register name UNUSED_013C_PORT7 */ + /* offset address */ 0xDA2C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_013C_PORT7_FIELDS + }, + { /* register name MACSEC_TXLINE_CFG1_PORT7 */ + /* offset address */ 0xDA30, + /* field numbers */ 5, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXLINE_CFG1_PORT7_FIELDS + }, + { /* register name MACSEC_TXLINE_CFG3_PORT7 */ + /* offset address */ 0xDA34, + /* field numbers */ 13, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXLINE_CFG3_PORT7_FIELDS + }, + { /* register name MACSEC_TXLINE_CFG5_PORT7 */ + /* offset address */ 0xDA38, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_TXLINE_CFG5_PORT7_FIELDS + }, + { /* register name UNUSED_014C_PORT7 */ + /* offset address */ 0xDA3C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_014C_PORT7_FIELDS + }, + { /* register name UNUSED_0150_PORT7 */ + /* offset address */ 0xDA40, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0150_PORT7_FIELDS + }, + { /* register name UNUSED_0154_PORT7 */ + /* offset address */ 0xDA44, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0154_PORT7_FIELDS + }, + { /* register name UNUSED_0158_PORT7 */ + /* offset address */ 0xDA48, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0158_PORT7_FIELDS + }, + { /* register name UNUSED_015C_PORT7 */ + /* offset address */ 0xDA4C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_015C_PORT7_FIELDS + }, + { /* register name UNUSED_0160_PORT7 */ + /* offset address */ 0xDA50, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0160_PORT7_FIELDS + }, + { /* register name UNUSED_0164_PORT7 */ + /* offset address */ 0xDA54, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0164_PORT7_FIELDS + }, + { /* register name UNUSED_0168_PORT7 */ + /* offset address */ 0xDA58, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0168_PORT7_FIELDS + }, + { /* register name UNUSED_016C_PORT7 */ + /* offset address */ 0xDA5C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_016C_PORT7_FIELDS + }, + { /* register name UNUSED_0170_PORT7 */ + /* offset address */ 0xDA60, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0170_PORT7_FIELDS + }, + { /* register name UNUSED_0174_PORT7 */ + /* offset address */ 0xDA64, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0174_PORT7_FIELDS + }, + { /* register name UNUSED_0178_PORT7 */ + /* offset address */ 0xDA68, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0178_PORT7_FIELDS + }, + { /* register name UNUSED_017C_PORT7 */ + /* offset address */ 0xDA6C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_017C_PORT7_FIELDS + }, + { /* register name MACSEC_RXLINE_CFG1_PORT7 */ + /* offset address */ 0xDA70, + /* field numbers */ 6, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXLINE_CFG1_PORT7_FIELDS + }, + { /* register name UNUSED_0184_PORT7 */ + /* offset address */ 0xDA74, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0184_PORT7_FIELDS + }, + { /* register name UNUSED_0188_PORT7 */ + /* offset address */ 0xDA78, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0188_PORT7_FIELDS + }, + { /* register name UNUSED_018C_PORT7 */ + /* offset address */ 0xDA7C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_018C_PORT7_FIELDS + }, + { /* register name UNUSED_0190_PORT7 */ + /* offset address */ 0xDA80, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0190_PORT7_FIELDS + }, + { /* register name UNUSED_0194_PORT7 */ + /* offset address */ 0xDA84, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0194_PORT7_FIELDS + }, + { /* register name UNUSED_0198_PORT7 */ + /* offset address */ 0xDA88, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_0198_PORT7_FIELDS + }, + { /* register name UNUSED_019C_PORT7 */ + /* offset address */ 0xDA8C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_019C_PORT7_FIELDS + }, + { /* register name UNUSED_01A0_PORT7 */ + /* offset address */ 0xDA90, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_01A0_PORT7_FIELDS + }, + { /* register name UNUSED_01A4_PORT7 */ + /* offset address */ 0xDA94, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_01A4_PORT7_FIELDS + }, + { /* register name UNUSED_01A8_PORT7 */ + /* offset address */ 0xDA98, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_01A8_PORT7_FIELDS + }, + { /* register name UNUSED_01AC_PORT7 */ + /* offset address */ 0xDA9C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_01AC_PORT7_FIELDS + }, + { /* register name UNUSED_01B0_PORT7 */ + /* offset address */ 0xDAA0, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_01B0_PORT7_FIELDS + }, + { /* register name UNUSED_01B4_PORT7 */ + /* offset address */ 0xDAA4, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_01B4_PORT7_FIELDS + }, + { /* register name UNUSED_01B8_PORT7 */ + /* offset address */ 0xDAA8, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_01B8_PORT7_FIELDS + }, + { /* register name UNUSED_01BC_PORT7 */ + /* offset address */ 0xDAAC, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ UNUSED_01BC_PORT7_FIELDS + }, + { /* register name MACSEC_RXSYS_CFG1_PORT7 */ + /* offset address */ 0xDAB0, + /* field numbers */ 5, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXSYS_CFG1_PORT7_FIELDS + }, + { /* register name MACSEC_RXSYS_CFG3_PORT7 */ + /* offset address */ 0xDAB4, + /* field numbers */ 12, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXSYS_CFG3_PORT7_FIELDS + }, + { /* register name MACSEC_RXSYS_OUTERVLAN2_PORT7 */ + /* offset address */ 0xDAB8, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXSYS_OUTERVLAN2_PORT7_FIELDS + }, + { /* register name MACSEC_RXSYS_OUTERVLAN4_PORT7 */ + /* offset address */ 0xDABC, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXSYS_OUTERVLAN4_PORT7_FIELDS + }, + { /* register name MACSEC_RXSYS_INNERVLAN2_PORT7 */ + /* offset address */ 0xDAC0, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXSYS_INNERVLAN2_PORT7_FIELDS + }, + { /* register name MACSEC_RXSYS_INNERVLAN4_PORT7 */ + /* offset address */ 0xDAC4, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXSYS_INNERVLAN4_PORT7_FIELDS + }, + { /* register name MACSEC_RXSYS_INNERVLAN6_PORT7 */ + /* offset address */ 0xDAC8, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXSYS_INNERVLAN6_PORT7_FIELDS + }, + { /* register name MACSEC_RXSYS_CFG4_PORT7 */ + /* offset address */ 0xDACC, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXSYS_CFG4_PORT7_FIELDS + }, + { /* register name MACSEC_RXSYS_CFG6_PORT7 */ + /* offset address */ 0xDAD0, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MACSEC_RXSYS_CFG6_PORT7_FIELDS + }, + { /* register name GATING_CLOCK0 */ + /* offset address */ 0x5FEC, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ GATING_CLOCK0_FIELDS + }, + { /* register name GATING_CLOCK1 */ + /* offset address */ 0x5FF0, + /* field numbers */ 11, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ GATING_CLOCK1_FIELDS + }, + { /* register name EEE_TX_Q_CTRL */ + /* offset address */ 0x4440, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ EEE_TX_Q_CTRL_FIELDS + }, + { /* register name EEE_TX_MINIFG_CTRL0 */ + /* offset address */ 0x5FF4, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ EEE_TX_MINIFG_CTRL0_FIELDS + }, + { /* register name EEE_TX_MINIFG_CTRL1 */ + /* offset address */ 0x5FF8, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ EEE_TX_MINIFG_CTRL1_FIELDS + }, + { /* register name EEE_TX_MINIFG_CTRL2 */ + /* offset address */ 0x5FFC, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ EEE_TX_MINIFG_CTRL2_FIELDS + }, + { /* register name EEE_TX_MINIFG_CTRL3 */ + /* offset address */ 0x6000, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ EEE_TX_MINIFG_CTRL3_FIELDS + }, + { /* register name EEE_TX_MINIFG_CTRL4 */ + /* offset address */ 0x6004, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ EEE_TX_MINIFG_CTRL4_FIELDS + }, + { /* register name EEE_TX_CTRL */ + /* offset address */ 0x6008, + /* field numbers */ 9, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ EEE_TX_CTRL_FIELDS + }, + { /* register name EEE_TX_TIMER_100M_CTRL */ + /* offset address */ 0x600C, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ EEE_TX_TIMER_100M_CTRL_FIELDS + }, + { /* register name EEE_TX_TIMER_GELITE_CTRL */ + /* offset address */ 0x6010, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ EEE_TX_TIMER_GELITE_CTRL_FIELDS + }, + { /* register name EEE_TX_TIMER_GIGA_CTRL */ + /* offset address */ 0x6014, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ EEE_TX_TIMER_GIGA_CTRL_FIELDS + }, + { /* register name EEE_TX_TIMER_2P5GLITE_CTRL */ + /* offset address */ 0x6018, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ EEE_TX_TIMER_2P5GLITE_CTRL_FIELDS + }, + { /* register name EEE_TX_TIMER_2P5G_CTRL */ + /* offset address */ 0x601C, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ EEE_TX_TIMER_2P5G_CTRL_FIELDS + }, + { /* register name EEE_TX_TIMER_5GLITE_CTRL */ + /* offset address */ 0x6020, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ EEE_TX_TIMER_5GLITE_CTRL_FIELDS + }, + { /* register name EEE_TX_TIMER_5G_CTRL */ + /* offset address */ 0x6024, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ EEE_TX_TIMER_5G_CTRL_FIELDS + }, + { /* register name EEE_TX_TIMER_10GLITE_CTRL */ + /* offset address */ 0x6028, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ EEE_TX_TIMER_10GLITE_CTRL_FIELDS + }, + { /* register name EEE_TX_TIMER_10G_CTRL */ + /* offset address */ 0x602C, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ EEE_TX_TIMER_10G_CTRL_FIELDS + }, + { /* register name EEE_CTRL */ + /* offset address */ 0x125C, + /* field numbers */ 5, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ EEE_CTRL_FIELDS + }, + { /* register name EEE_RX_GELITE_CTRL */ + /* offset address */ 0x6030, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ EEE_RX_GELITE_CTRL_FIELDS + }, + { /* register name EEE_RX_GE_CTRL */ + /* offset address */ 0x6034, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ EEE_RX_GE_CTRL_FIELDS + }, + { /* register name LPI_OPTION */ + /* offset address */ 0x1038, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ LPI_OPTION_FIELDS + }, + { /* register name RA_FIFO_FUL_THR0 */ + /* offset address */ 0xE0F0, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RA_FIFO_FUL_THR0_FIELDS + }, + { /* register name RA_FIFO_EMPTY_THR0 */ + /* offset address */ 0xE0F4, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RA_FIFO_EMPTY_THR0_FIELDS + }, + { /* register name RA_TX_STATUS0 */ + /* offset address */ 0xE0F8, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RA_TX_STATUS0_FIELDS + }, + { /* register name RA_RX_STATUS0 */ + /* offset address */ 0xE0FC, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RA_RX_STATUS0_FIELDS + }, + { /* register name RA_HSG_IFG0 */ + /* offset address */ 0xE100, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RA_HSG_IFG0_FIELDS + }, + { /* register name RA_MACSEC_ETH0 */ + /* offset address */ 0xE104, + /* field numbers */ 1, + /* array offset */ 16, + /* array index */ 0, 7, + /* port index */ 0, 0, + /* register fields */ RA_MACSEC_ETH0_FIELDS + }, + { /* register name RA_MACSEC_VLAN0 */ + /* offset address */ 0xE114, + /* field numbers */ 1, + /* array offset */ 16, + /* array index */ 0, 10, + /* port index */ 0, 0, + /* register fields */ RA_MACSEC_VLAN0_FIELDS + }, + { /* register name RA_MACSEC_IFG_CTRL0 */ + /* offset address */ 0xE12C, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RA_MACSEC_IFG_CTRL0_FIELDS + }, + { /* register name RA_PAUSE_CTRL0 */ + /* offset address */ 0xE130, + /* field numbers */ 6, + /* array offset */ 64, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RA_PAUSE_CTRL0_FIELDS + }, + { /* register name RA_GLB_CTRL0 */ + /* offset address */ 0xE138, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RA_GLB_CTRL0_FIELDS + }, + { /* register name RA_PADDING_CTRL0 */ + /* offset address */ 0xE13C, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RA_PADDING_CTRL0_FIELDS + }, + { /* register name RA_SLOT_TIME0 */ + /* offset address */ 0xE140, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RA_SLOT_TIME0_FIELDS + }, + { /* register name RA_SOFT_RST0 */ + /* offset address */ 0xE144, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RA_SOFT_RST0_FIELDS + }, + { /* register name RA_FIFO_FUL_THR1 */ + /* offset address */ 0xE2F0, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RA_FIFO_FUL_THR1_FIELDS + }, + { /* register name RA_FIFO_EMPTY_THR1 */ + /* offset address */ 0xE2F4, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RA_FIFO_EMPTY_THR1_FIELDS + }, + { /* register name RA_TX_STATUS1 */ + /* offset address */ 0xE2F8, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RA_TX_STATUS1_FIELDS + }, + { /* register name RA_RX_STATUS1 */ + /* offset address */ 0xE2FC, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RA_RX_STATUS1_FIELDS + }, + { /* register name RA_HSG_IFG1 */ + /* offset address */ 0xE300, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RA_HSG_IFG1_FIELDS + }, + { /* register name RA_MACSEC_ETH1 */ + /* offset address */ 0xE304, + /* field numbers */ 1, + /* array offset */ 16, + /* array index */ 0, 7, + /* port index */ 0, 0, + /* register fields */ RA_MACSEC_ETH1_FIELDS + }, + { /* register name RA_MACSEC_VLAN1 */ + /* offset address */ 0xE314, + /* field numbers */ 1, + /* array offset */ 16, + /* array index */ 0, 10, + /* port index */ 0, 0, + /* register fields */ RA_MACSEC_VLAN1_FIELDS + }, + { /* register name RA_MACSEC_IFG_CTRL1 */ + /* offset address */ 0xE32C, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RA_MACSEC_IFG_CTRL1_FIELDS + }, + { /* register name RA_PAUSE_CTRL1 */ + /* offset address */ 0xE330, + /* field numbers */ 6, + /* array offset */ 64, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RA_PAUSE_CTRL1_FIELDS + }, + { /* register name RA_GLB_CTRL1 */ + /* offset address */ 0xE338, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RA_GLB_CTRL1_FIELDS + }, + { /* register name RA_PADDING_CTRL1 */ + /* offset address */ 0xE33C, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RA_PADDING_CTRL1_FIELDS + }, + { /* register name RA_SLOT_TIME1 */ + /* offset address */ 0xE340, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RA_SLOT_TIME1_FIELDS + }, + { /* register name RA_SOFT_RST1 */ + /* offset address */ 0xE344, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RA_SOFT_RST1_FIELDS + }, + { /* register name RA_FIFO_FUL_THR2 */ + /* offset address */ 0xE4F0, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RA_FIFO_FUL_THR2_FIELDS + }, + { /* register name RA_FIFO_EMPTY_THR2 */ + /* offset address */ 0xE4F4, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RA_FIFO_EMPTY_THR2_FIELDS + }, + { /* register name RA_TX_STATUS2 */ + /* offset address */ 0xE4F8, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RA_TX_STATUS2_FIELDS + }, + { /* register name RA_RX_STATUS2 */ + /* offset address */ 0xE4FC, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RA_RX_STATUS2_FIELDS + }, + { /* register name RA_HSG_IFG2 */ + /* offset address */ 0xE500, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RA_HSG_IFG2_FIELDS + }, + { /* register name RA_MACSEC_ETH2 */ + /* offset address */ 0xE504, + /* field numbers */ 1, + /* array offset */ 16, + /* array index */ 0, 7, + /* port index */ 0, 0, + /* register fields */ RA_MACSEC_ETH2_FIELDS + }, + { /* register name RA_MACSEC_VLAN2 */ + /* offset address */ 0xE514, + /* field numbers */ 1, + /* array offset */ 16, + /* array index */ 0, 10, + /* port index */ 0, 0, + /* register fields */ RA_MACSEC_VLAN2_FIELDS + }, + { /* register name RA_MACSEC_IFG_CTRL2 */ + /* offset address */ 0xE52C, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RA_MACSEC_IFG_CTRL2_FIELDS + }, + { /* register name RA_PAUSE_CTRL2 */ + /* offset address */ 0xE530, + /* field numbers */ 6, + /* array offset */ 64, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RA_PAUSE_CTRL2_FIELDS + }, + { /* register name RA_GLB_CTRL2 */ + /* offset address */ 0xE538, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RA_GLB_CTRL2_FIELDS + }, + { /* register name RA_PADDING_CTRL2 */ + /* offset address */ 0xE53C, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RA_PADDING_CTRL2_FIELDS + }, + { /* register name RA_SLOT_TIME2 */ + /* offset address */ 0xE540, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RA_SLOT_TIME2_FIELDS + }, + { /* register name RA_SOFT_RST2 */ + /* offset address */ 0xE544, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RA_SOFT_RST2_FIELDS + }, + { /* register name RA_FIFO_FUL_THR3 */ + /* offset address */ 0xE6F0, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RA_FIFO_FUL_THR3_FIELDS + }, + { /* register name RA_FIFO_EMPTY_THR3 */ + /* offset address */ 0xE6F4, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RA_FIFO_EMPTY_THR3_FIELDS + }, + { /* register name RA_TX_STATUS3 */ + /* offset address */ 0xE6F8, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RA_TX_STATUS3_FIELDS + }, + { /* register name RA_RX_STATUS3 */ + /* offset address */ 0xE6FC, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RA_RX_STATUS3_FIELDS + }, + { /* register name RA_HSG_IFG3 */ + /* offset address */ 0xE700, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RA_HSG_IFG3_FIELDS + }, + { /* register name RA_MACSEC_ETH3 */ + /* offset address */ 0xE704, + /* field numbers */ 1, + /* array offset */ 16, + /* array index */ 0, 7, + /* port index */ 0, 0, + /* register fields */ RA_MACSEC_ETH3_FIELDS + }, + { /* register name RA_MACSEC_VLAN3 */ + /* offset address */ 0xE714, + /* field numbers */ 1, + /* array offset */ 16, + /* array index */ 0, 10, + /* port index */ 0, 0, + /* register fields */ RA_MACSEC_VLAN3_FIELDS + }, + { /* register name RA_MACSEC_IFG_CTRL3 */ + /* offset address */ 0xE72C, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RA_MACSEC_IFG_CTRL3_FIELDS + }, + { /* register name RA_PAUSE_CTRL3 */ + /* offset address */ 0xE730, + /* field numbers */ 6, + /* array offset */ 64, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RA_PAUSE_CTRL3_FIELDS + }, + { /* register name RA_GLB_CTRL3 */ + /* offset address */ 0xE738, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RA_GLB_CTRL3_FIELDS + }, + { /* register name RA_PADDING_CTRL3 */ + /* offset address */ 0xE73C, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RA_PADDING_CTRL3_FIELDS + }, + { /* register name RA_SLOT_TIME3 */ + /* offset address */ 0xE740, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RA_SLOT_TIME3_FIELDS + }, + { /* register name RA_SOFT_RST3 */ + /* offset address */ 0xE744, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RA_SOFT_RST3_FIELDS + }, + { /* register name NIC_BUFFSIZE_CTRL */ + /* offset address */ 0x7844, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ NIC_BUFFSIZE_CTRL_FIELDS + }, + { /* register name NIC_RXBUFF_CTRL */ + /* offset address */ 0x7848, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ NIC_RXBUFF_CTRL_FIELDS + }, + { /* register name NIC_RXCMD */ + /* offset address */ 0x784C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ NIC_RXCMD_FIELDS + }, + { /* register name NIC_TXCMD */ + /* offset address */ 0x7850, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ NIC_TXCMD_FIELDS + }, + { /* register name NIC_INT_STS */ + /* offset address */ 0x7854, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ NIC_INT_STS_FIELDS + }, + { /* register name NIC_INT_MSK */ + /* offset address */ 0x7858, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ NIC_INT_MSK_FIELDS + }, + { /* register name NIC_RX_CTRL */ + /* offset address */ 0x785C, + /* field numbers */ 17, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ NIC_RX_CTRL_FIELDS + }, + { /* register name NIC_TX_CTRL */ + /* offset address */ 0x7860, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ NIC_TX_CTRL_FIELDS + }, + { /* register name NIC_MC_HASH_TBL */ + /* offset address */ 0x7864, + /* field numbers */ 1, + /* array offset */ 1, + /* array index */ 0, 63, + /* port index */ 0, 0, + /* register fields */ NIC_MC_HASH_TBL_FIELDS + }, + { /* register name NIC_UC_HASH_TBL */ + /* offset address */ 0x786C, + /* field numbers */ 1, + /* array offset */ 1, + /* array index */ 0, 63, + /* port index */ 0, 0, + /* register fields */ NIC_UC_HASH_TBL_FIELDS + }, + { /* register name NIC_RX_BUFF_DATA */ + /* offset address */ 0x7874, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ NIC_RX_BUFF_DATA_FIELDS + }, + { /* register name NIC_RX_CURR_PKT */ + /* offset address */ 0x7878, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ NIC_RX_CURR_PKT_FIELDS + }, + { /* register name CPU_RX_CURR_PKT */ + /* offset address */ 0x787C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ CPU_RX_CURR_PKT_FIELDS + }, + { /* register name NIC_TX_BUFF_AVAIL */ + /* offset address */ 0x7880, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ NIC_TX_BUFF_AVAIL_FIELDS + }, + { /* register name NIC_TX_CURR_PKT */ + /* offset address */ 0x7884, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ NIC_TX_CURR_PKT_FIELDS + }, + { /* register name NIC_TX_CURR_UNIT */ + /* offset address */ 0x7888, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ NIC_TX_CURR_UNIT_FIELDS + }, + { /* register name NIC_TX_PKT_INFO */ + /* offset address */ 0x788C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ NIC_TX_PKT_INFO_FIELDS + }, + { /* register name CPU_TX_CURR_PKT */ + /* offset address */ 0x7890, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ CPU_TX_CURR_PKT_FIELDS + }, + { /* register name DMY_REG0_NIC */ + /* offset address */ 0x7894, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ DMY_REG0_NIC_FIELDS + }, + { /* register name DMY_REG1_NIC */ + /* offset address */ 0x7898, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ DMY_REG1_NIC_FIELDS + }, + { /* register name CPU_TAG_TPID_CTRL */ + /* offset address */ 0x6038, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ CPU_TAG_TPID_CTRL_FIELDS + }, + { /* register name CPU_TAG_CTRL */ + /* offset address */ 0x6720, + /* field numbers */ 6, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ CPU_TAG_CTRL_FIELDS + }, + { /* register name EXT_CPU_CTRL */ + /* offset address */ 0x6724, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ EXT_CPU_CTRL_FIELDS + }, + { /* register name CPU_TAG_AWARE_CTRL */ + /* offset address */ 0x603C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ CPU_TAG_AWARE_CTRL_FIELDS + }, + { /* register name ITA_CTRL0 */ + /* offset address */ 0x5CAC, + /* field numbers */ 7, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ ITA_CTRL0_FIELDS + }, + { /* register name ITA_L2_CTRL */ + /* offset address */ 0x5CB0, + /* field numbers */ 7, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ ITA_L2_CTRL_FIELDS + }, + { /* register name ITA_HSAB_CTRL */ + /* offset address */ 0x5CB4, + /* field numbers */ 9, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ ITA_HSAB_CTRL_FIELDS + }, + { /* register name ITA_WRITE_DATA0 */ + /* offset address */ 0x5CB8, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 4, + /* port index */ 0, 0, + /* register fields */ ITA_WRITE_DATA0_FIELDS + }, + { /* register name ITA_READ_DATA0 */ + /* offset address */ 0x5CCC, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 4, + /* port index */ 0, 0, + /* register fields */ ITA_READ_DATA0_FIELDS + }, + { /* register name TEST_MODE_ALE_HSA_MULTI_CTRL */ + /* offset address */ 0x4444, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ TEST_MODE_ALE_HSA_MULTI_CTRL_FIELDS + }, + { /* register name TBL_ACCESS_HSA_CTRL */ + /* offset address */ 0x4448, + /* field numbers */ 5, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ TBL_ACCESS_HSA_CTRL_FIELDS + }, + { /* register name TBL_ACCESS_HSA_DATA */ + /* offset address */ 0x444C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 9, + /* port index */ 0, 0, + /* register fields */ TBL_ACCESS_HSA_DATA_FIELDS + }, + { /* register name DW8051_CFG */ + /* offset address */ 0x6040, + /* field numbers */ 12, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ DW8051_CFG_FIELDS + }, + { /* register name DW8051_IROM */ + /* offset address */ 0x80B0, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 4095, + /* port index */ 0, 0, + /* register fields */ DW8051_IROM_FIELDS + }, + { /* register name VLAN_PORT_AFT */ + /* offset address */ 0x4E10, + /* field numbers */ 1, + /* array offset */ 2, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ VLAN_PORT_AFT_FIELDS + }, + { /* register name VLAN_CTRL */ + /* offset address */ 0x4E14, + /* field numbers */ 5, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ VLAN_CTRL_FIELDS + }, + { /* register name VLAN_PORT_IGR_FLTR */ + /* offset address */ 0x4E18, + /* field numbers */ 1, + /* array offset */ 1, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ VLAN_PORT_IGR_FLTR_FIELDS + }, + { /* register name VLAN_PORT_PB_VLAN */ + /* offset address */ 0x4E1C, + /* field numbers */ 1, + /* array offset */ 12, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ VLAN_PORT_PB_VLAN_FIELDS + }, + { /* register name VLAN_PORT_EGR_TRANS */ + /* offset address */ 0x4EB8, + /* field numbers */ 1, + /* array offset */ 10, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ VLAN_PORT_EGR_TRANS_FIELDS + }, + { /* register name VLAN_PORT_EGR_KEEP */ + /* offset address */ 0x6728, + /* field numbers */ 1, + /* array offset */ 10, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ VLAN_PORT_EGR_KEEP_FIELDS + }, + { /* register name VLAN_PORT_EGR_TAG */ + /* offset address */ 0x6738, + /* field numbers */ 1, + /* array offset */ 2, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ VLAN_PORT_EGR_TAG_FIELDS + }, + { /* register name VLAN_L2_LRN_DIS */ + /* offset address */ 0x4E30, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 1, + /* port index */ 0, 0, + /* register fields */ VLAN_L2_LRN_DIS_FIELDS + }, + { /* register name PORT_BASED_FID_EN */ + /* offset address */ 0x4E38, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PORT_BASED_FID_EN_FIELDS + }, + { /* register name PORT_BASED_FID */ + /* offset address */ 0x4E3C, + /* field numbers */ 1, + /* array offset */ 4, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ PORT_BASED_FID_FIELDS + }, + { /* register name VLAN_TAG_PRI_CFG */ + /* offset address */ 0x673C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ VLAN_TAG_PRI_CFG_FIELDS + }, + { /* register name VS_GLB_CTRL */ + /* offset address */ 0x6044, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ VS_GLB_CTRL_FIELDS + }, + { /* register name VS_UPLINK_PORT */ + /* offset address */ 0x57C0, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ VS_UPLINK_PORT_FIELDS + }, + { /* register name VS_CTRL */ + /* offset address */ 0x57C4, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ VS_CTRL_FIELDS + }, + { /* register name VS_UNTAG_SVID */ + /* offset address */ 0x57C8, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ VS_UNTAG_SVID_FIELDS + }, + { /* register name VS_PORT_DFLT_SVID */ + /* offset address */ 0x57CC, + /* field numbers */ 1, + /* array offset */ 12, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ VS_PORT_DFLT_SVID_FIELDS + }, + { /* register name SVLAN_TRAP_CTRL */ + /* offset address */ 0x4EC8, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SVLAN_TRAP_CTRL_FIELDS + }, + { /* register name VLAN_C2S_ENTRY */ + /* offset address */ 0x57E0, + /* field numbers */ 5, + /* array offset */ 64, + /* array index */ 0, 127, + /* port index */ 0, 0, + /* register fields */ VLAN_C2S_ENTRY_FIELDS + }, + { /* register name RMA_OP_CTRL_00 */ + /* offset address */ 0x4ECC, + /* field numbers */ 6, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RMA_OP_CTRL_00_FIELDS + }, + { /* register name RMA_OP_CTRL_01 */ + /* offset address */ 0x4ED0, + /* field numbers */ 6, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RMA_OP_CTRL_01_FIELDS + }, + { /* register name RMA_OP_CTRL_02 */ + /* offset address */ 0x4ED4, + /* field numbers */ 6, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RMA_OP_CTRL_02_FIELDS + }, + { /* register name RMA_OP_CTRL_03 */ + /* offset address */ 0x4ED8, + /* field numbers */ 6, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RMA_OP_CTRL_03_FIELDS + }, + { /* register name RMA_OP_CTRL_04 */ + /* offset address */ 0x4EDC, + /* field numbers */ 6, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RMA_OP_CTRL_04_FIELDS + }, + { /* register name RMA_OP_CTRL_08 */ + /* offset address */ 0x4EE0, + /* field numbers */ 6, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RMA_OP_CTRL_08_FIELDS + }, + { /* register name RMA_OP_CTRL_0D */ + /* offset address */ 0x4EE4, + /* field numbers */ 6, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RMA_OP_CTRL_0D_FIELDS + }, + { /* register name RMA_OP_CTRL_0E */ + /* offset address */ 0x4EE8, + /* field numbers */ 6, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RMA_OP_CTRL_0E_FIELDS + }, + { /* register name RMA_OP_CTRL_10 */ + /* offset address */ 0x4EEC, + /* field numbers */ 6, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RMA_OP_CTRL_10_FIELDS + }, + { /* register name RMA_OP_CTRL_11 */ + /* offset address */ 0x4EF0, + /* field numbers */ 6, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RMA_OP_CTRL_11_FIELDS + }, + { /* register name RMA_OP_CTRL_12 */ + /* offset address */ 0x4EF4, + /* field numbers */ 6, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RMA_OP_CTRL_12_FIELDS + }, + { /* register name RMA_OP_CTRL_13 */ + /* offset address */ 0x4EF8, + /* field numbers */ 6, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RMA_OP_CTRL_13_FIELDS + }, + { /* register name RMA_OP_CTRL_18 */ + /* offset address */ 0x4EFC, + /* field numbers */ 6, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RMA_OP_CTRL_18_FIELDS + }, + { /* register name RMA_OP_CTRL_1A */ + /* offset address */ 0x4F00, + /* field numbers */ 6, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RMA_OP_CTRL_1A_FIELDS + }, + { /* register name RMA_OP_CTRL_20 */ + /* offset address */ 0x4F04, + /* field numbers */ 6, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RMA_OP_CTRL_20_FIELDS + }, + { /* register name RMA_OP_CTRL_21 */ + /* offset address */ 0x4F08, + /* field numbers */ 6, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RMA_OP_CTRL_21_FIELDS + }, + { /* register name RMA_OP_CTRL_22 */ + /* offset address */ 0x4F0C, + /* field numbers */ 6, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RMA_OP_CTRL_22_FIELDS + }, + { /* register name RMA_OP_CTRL_CDP */ + /* offset address */ 0x4F10, + /* field numbers */ 6, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RMA_OP_CTRL_CDP_FIELDS + }, + { /* register name RMA_OP_CTRL_CSSTP */ + /* offset address */ 0x4F14, + /* field numbers */ 6, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RMA_OP_CTRL_CSSTP_FIELDS + }, + { /* register name RMA_OP_CTRL_LLDP */ + /* offset address */ 0x4F18, + /* field numbers */ 6, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RMA_OP_CTRL_LLDP_FIELDS + }, + { /* register name RMA_CFG */ + /* offset address */ 0x4F1C, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RMA_CFG_FIELDS + }, + { /* register name RMA_PORT_PTP_ETH2_CTRL */ + /* offset address */ 0x4F20, + /* field numbers */ 1, + /* array offset */ 2, + /* array index */ 0, 0, + /* port index */ 0, 8, + /* register fields */ RMA_PORT_PTP_ETH2_CTRL_FIELDS + }, + { /* register name RMA_PORT_PTP_UDP_CTRL */ + /* offset address */ 0x4F24, + /* field numbers */ 1, + /* array offset */ 2, + /* array index */ 0, 0, + /* port index */ 0, 8, + /* register fields */ RMA_PORT_PTP_UDP_CTRL_FIELDS + }, + { /* register name RMA_PORT_PTP_DELAY_CARE_CTRL */ + /* offset address */ 0x4F28, + /* field numbers */ 1, + /* array offset */ 1, + /* array index */ 0, 0, + /* port index */ 0, 8, + /* register fields */ RMA_PORT_PTP_DELAY_CARE_CTRL_FIELDS + }, + { /* register name RMA_PORT_PTP_PDELAY_CARE_CTRL */ + /* offset address */ 0x4F2C, + /* field numbers */ 1, + /* array offset */ 1, + /* array index */ 0, 0, + /* port index */ 0, 8, + /* register fields */ RMA_PORT_PTP_PDELAY_CARE_CTRL_FIELDS + }, + { /* register name RMA_PORT_PTP_ASM_CARE_CTRL */ + /* offset address */ 0x4F30, + /* field numbers */ 1, + /* array offset */ 1, + /* array index */ 0, 0, + /* port index */ 0, 8, + /* register fields */ RMA_PORT_PTP_ASM_CARE_CTRL_FIELDS + }, + { /* register name RMA_PTP_TRAP_CTRL */ + /* offset address */ 0x4F34, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RMA_PTP_TRAP_CTRL_FIELDS + }, + { /* register name TRK_MBR_CTRL */ + /* offset address */ 0x4F38, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 3, + /* port index */ 0, 0, + /* register fields */ TRK_MBR_CTRL_FIELDS + }, + { /* register name TRK_HASH_CTRL */ + /* offset address */ 0x4F48, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 3, + /* port index */ 0, 0, + /* register fields */ TRK_HASH_CTRL_FIELDS + }, + { /* register name TRK_CTRL */ + /* offset address */ 0x4F58, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ TRK_CTRL_FIELDS + }, + { /* register name TRK_FLOW_CTRL */ + /* offset address */ 0x4F5C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 3, + /* port index */ 0, 0, + /* register fields */ TRK_FLOW_CTRL_FIELDS + }, + { /* register name TRK_QUEUE_EMPTY */ + /* offset address */ 0x4474, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ TRK_QUEUE_EMPTY_FIELDS + }, + { /* register name MSPT_STATE */ + /* offset address */ 0x5310, + /* field numbers */ 11, + /* array offset */ 32, + /* array index */ 0, 15, + /* port index */ 0, 0, + /* register fields */ MSPT_STATE_FIELDS + }, + { /* register name L2_CTRL */ + /* offset address */ 0x5350, + /* field numbers */ 10, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ L2_CTRL_FIELDS + }, + { /* register name L2_AGE_CTRL */ + /* offset address */ 0x5354, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ L2_AGE_CTRL_FIELDS + }, + { /* register name L2_PORT_AGE_CTRL */ + /* offset address */ 0x5358, + /* field numbers */ 1, + /* array offset */ 1, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ L2_PORT_AGE_CTRL_FIELDS + }, + { /* register name L2_NEWSA_CTRL */ + /* offset address */ 0x4F6C, + /* field numbers */ 1, + /* array offset */ 2, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ L2_NEWSA_CTRL_FIELDS + }, + { /* register name L2_UNMATCH_SA_CTRL */ + /* offset address */ 0x4F70, + /* field numbers */ 1, + /* array offset */ 2, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ L2_UNMATCH_SA_CTRL_FIELDS + }, + { /* register name L2_SA_MOVING_FORBID */ + /* offset address */ 0x535C, + /* field numbers */ 1, + /* array offset */ 1, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ L2_SA_MOVING_FORBID_FIELDS + }, + { /* register name L2_UNKN_UC_FLD_PMSK */ + /* offset address */ 0x5360, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ L2_UNKN_UC_FLD_PMSK_FIELDS + }, + { /* register name L2_UNKN_MC_FLD_PMSK */ + /* offset address */ 0x5364, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ L2_UNKN_MC_FLD_PMSK_FIELDS + }, + { /* register name IPV4_UNKN_MC_FLD_PMSK */ + /* offset address */ 0x5368, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ IPV4_UNKN_MC_FLD_PMSK_FIELDS + }, + { /* register name IPV6_UNKN_MC_FLD_PMSK */ + /* offset address */ 0x536C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ IPV6_UNKN_MC_FLD_PMSK_FIELDS + }, + { /* register name L2_BC_FLD_PMSK */ + /* offset address */ 0x5370, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ L2_BC_FLD_PMSK_FIELDS + }, + { /* register name L2_PORT_UC_LM_ACT */ + /* offset address */ 0x5374, + /* field numbers */ 1, + /* array offset */ 2, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ L2_PORT_UC_LM_ACT_FIELDS + }, + { /* register name L2_PORT_MC_LM_ACT */ + /* offset address */ 0x4F74, + /* field numbers */ 1, + /* array offset */ 2, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ L2_PORT_MC_LM_ACT_FIELDS + }, + { /* register name IPV4_PORT_MC_LM_ACT */ + /* offset address */ 0x4F78, + /* field numbers */ 1, + /* array offset */ 2, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ IPV4_PORT_MC_LM_ACT_FIELDS + }, + { /* register name IPV6_PORT_MC_LM_ACT */ + /* offset address */ 0x4F7C, + /* field numbers */ 1, + /* array offset */ 2, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ IPV6_PORT_MC_LM_ACT_FIELDS + }, + { /* register name L2_LRN_CONSTRT_CTRL */ + /* offset address */ 0x5378, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ L2_LRN_CONSTRT_CTRL_FIELDS + }, + { /* register name L2_LRN_CONSTRT_CNT */ + /* offset address */ 0x537C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ L2_LRN_CONSTRT_CNT_FIELDS + }, + { /* register name L2_LRN_CONSTRT_ACT */ + /* offset address */ 0x5380, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ L2_LRN_CONSTRT_ACT_FIELDS + }, + { /* register name L2_LRN_PORT_CONSTRT_CTRL */ + /* offset address */ 0x5384, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ L2_LRN_PORT_CONSTRT_CTRL_FIELDS + }, + { /* register name L2_LRN_PORT_CONSTRT_CNT */ + /* offset address */ 0x53AC, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ L2_LRN_PORT_CONSTRT_CNT_FIELDS + }, + { /* register name L2_LRN_PORT_CONSTRT_ACT */ + /* offset address */ 0x4F80, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ L2_LRN_PORT_CONSTRT_ACT_FIELDS + }, + { /* register name L2_TBL_FLUSH_CMD */ + /* offset address */ 0x53D4, + /* field numbers */ 5, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ L2_TBL_FLUSH_CMD_FIELDS + }, + { /* register name L2_TBL_FLUSH_ALL */ + /* offset address */ 0x53D8, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ L2_TBL_FLUSH_ALL_FIELDS + }, + { /* register name L2_TBL_FLUSH_MODE */ + /* offset address */ 0x53DC, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ L2_TBL_FLUSH_MODE_FIELDS + }, + { /* register name L2_TBL_FLUSH_XID */ + /* offset address */ 0x53E0, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ L2_TBL_FLUSH_XID_FIELDS + }, + { /* register name SOURCE_PORT_PERMIT */ + /* offset address */ 0x4F84, + /* field numbers */ 1, + /* array offset */ 1, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ SOURCE_PORT_PERMIT_FIELDS + }, + { /* register name IPMC_GROUP_DIP */ + /* offset address */ 0x4F88, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 63, + /* port index */ 0, 0, + /* register fields */ IPMC_GROUP_DIP_FIELDS + }, + { /* register name IPMC_GROUP_PMSK */ + /* offset address */ 0x53E4, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 63, + /* port index */ 0, 0, + /* register fields */ IPMC_GROUP_PMSK_FIELDS + }, + { /* register name IPMC_GROUP_VALID */ + /* offset address */ 0x5BE0, + /* field numbers */ 1, + /* array offset */ 1, + /* array index */ 0, 63, + /* port index */ 0, 0, + /* register fields */ IPMC_GROUP_VALID_FIELDS + }, + { /* register name IPMUL_NO_VLAN_EGRESS */ + /* offset address */ 0x5088, + /* field numbers */ 1, + /* array offset */ 1, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ IPMUL_NO_VLAN_EGRESS_FIELDS + }, + { /* register name IPMUL_NO_PORTISO */ + /* offset address */ 0x508C, + /* field numbers */ 1, + /* array offset */ 1, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ IPMUL_NO_PORTISO_FIELDS + }, + { /* register name L2_FORCE_MODE */ + /* offset address */ 0x5090, + /* field numbers */ 1, + /* array offset */ 1, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ L2_FORCE_MODE_FIELDS + }, + { /* register name L2_FORCE_DPM_PORT */ + /* offset address */ 0x5094, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ L2_FORCE_DPM_PORT_FIELDS + }, + { /* register name IGMP_CTRL */ + /* offset address */ 0x5290, + /* field numbers */ 20, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ IGMP_CTRL_FIELDS + }, + { /* register name IGMP_QUERY_INTVL */ + /* offset address */ 0x5294, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ IGMP_QUERY_INTVL_FIELDS + }, + { /* register name IGMP_DYN_ROUTER_INFO */ + /* offset address */ 0x5298, + /* field numbers */ 7, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ IGMP_DYN_ROUTER_INFO_FIELDS + }, + { /* register name IGMP_ROUTER_PORT_CRTL */ + /* offset address */ 0x529C, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ IGMP_ROUTER_PORT_CRTL_FIELDS + }, + { /* register name IGMP_PORT_CTRL */ + /* offset address */ 0x52A0, + /* field numbers */ 13, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ IGMP_PORT_CTRL_FIELDS + }, + { /* register name PORT_CURR_GROUP */ + /* offset address */ 0x52C8, + /* field numbers */ 1, + /* array offset */ 8, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ PORT_CURR_GROUP_FIELDS + }, + { /* register name IGMP_TBL_USAGE */ + /* offset address */ 0x52D4, + /* field numbers */ 1, + /* array offset */ 1, + /* array index */ 0, 255, + /* port index */ 0, 0, + /* register fields */ IGMP_TBL_USAGE_FIELDS + }, + { /* register name IGMP_TRAP_CTRL */ + /* offset address */ 0x50BC, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ IGMP_TRAP_CTRL_FIELDS + }, + { /* register name PORT_ISO_PORT_PMSK */ + /* offset address */ 0x50C0, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ PORT_ISO_PORT_PMSK_FIELDS + }, + { /* register name MIR_CTRL */ + /* offset address */ 0x50E8, + /* field numbers */ 9, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MIR_CTRL_FIELDS + }, + { /* register name MIR_SET_CTRL */ + /* offset address */ 0x6048, + /* field numbers */ 5, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MIR_SET_CTRL_FIELDS + }, + { /* register name MIR_SET_PMSK */ + /* offset address */ 0x604C, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MIR_SET_PMSK_FIELDS + }, + { /* register name MIR_SAMPLE_CRTL */ + /* offset address */ 0x50EC, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MIR_SAMPLE_CRTL_FIELDS + }, + { /* register name MIR_MATCHED */ + /* offset address */ 0x50F0, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MIR_MATCHED_FIELDS + }, + { /* register name MIR_RSPAN_CTRL */ + /* offset address */ 0x6050, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MIR_RSPAN_CTRL_FIELDS + }, + { /* register name MIR_RSPAN_TAG_CTRL */ + /* offset address */ 0x6740, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MIR_RSPAN_TAG_CTRL_FIELDS + }, + { /* register name MIR_RSPAN_TX_PORT_CTRL */ + /* offset address */ 0x6744, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MIR_RSPAN_TX_PORT_CTRL_FIELDS + }, + { /* register name MIR_RSPAN_RX_ACT */ + /* offset address */ 0x6748, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MIR_RSPAN_RX_ACT_FIELDS + }, + { /* register name ACL_CTRL */ + /* offset address */ 0x4810, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ ACL_CTRL_FIELDS + }, + { /* register name ACL_GPIO_CTRL */ + /* offset address */ 0x4814, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ ACL_GPIO_CTRL_FIELDS + }, + { /* register name ACL_PORT_EN */ + /* offset address */ 0x4818, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ ACL_PORT_EN_FIELDS + }, + { /* register name ACL_PORT_UNMATCH_PERMIT */ + /* offset address */ 0x481C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ ACL_PORT_UNMATCH_PERMIT_FIELDS + }, + { /* register name ACL_TEMPLATE_CTRL */ + /* offset address */ 0x4820, + /* field numbers */ 8, + /* array offset */ 64, + /* array index */ 0, 4, + /* port index */ 0, 0, + /* register fields */ ACL_TEMPLATE_CTRL_FIELDS + }, + { /* register name ACL_ACT_CTRL */ + /* offset address */ 0x4848, + /* field numbers */ 10, + /* array offset */ 32, + /* array index */ 0, 95, + /* port index */ 0, 0, + /* register fields */ ACL_ACT_CTRL_FIELDS + }, + { /* register name ACL_HIT_INDICATOR */ + /* offset address */ 0x49C8, + /* field numbers */ 16, + /* array offset */ 64, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ ACL_HIT_INDICATOR_FIELDS + }, + { /* register name RNG_CHK_VID */ + /* offset address */ 0x49D0, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 15, + /* port index */ 0, 0, + /* register fields */ RNG_CHK_VID_FIELDS + }, + { /* register name RNG_CHK_IP */ + /* offset address */ 0x4A10, + /* field numbers */ 4, + /* array offset */ 96, + /* array index */ 0, 15, + /* port index */ 0, 0, + /* register fields */ RNG_CHK_IP_FIELDS + }, + { /* register name RNG_CHK_PORT */ + /* offset address */ 0x4AD0, + /* field numbers */ 4, + /* array offset */ 64, + /* array index */ 0, 15, + /* port index */ 0, 0, + /* register fields */ RNG_CHK_PORT_FIELDS + }, + { /* register name ACL_LOG_CNTR_RST */ + /* offset address */ 0x4B50, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ ACL_LOG_CNTR_RST_FIELDS + }, + { /* register name ACL_CNTR_RST_VAL */ + /* offset address */ 0x4B54, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ ACL_CNTR_RST_VAL_FIELDS + }, + { /* register name ACL_LOG_CNTR_TYPE */ + /* offset address */ 0x4B58, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ ACL_LOG_CNTR_TYPE_FIELDS + }, + { /* register name ACL_LOG_CNTR_MODE */ + /* offset address */ 0x4B5C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ ACL_LOG_CNTR_MODE_FIELDS + }, + { /* register name ACL_LOG_CNTR_DATA */ + /* offset address */ 0x4B60, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 31, + /* port index */ 0, 0, + /* register fields */ ACL_LOG_CNTR_DATA_FIELDS + }, + { /* register name ACL_LATCH_TRIGGER */ + /* offset address */ 0x4BE0, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ ACL_LATCH_TRIGGER_FIELDS + }, + { /* register name ACL_LATCH_ADDR */ + /* offset address */ 0x4BE4, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ ACL_LATCH_ADDR_FIELDS + }, + { /* register name ACL_LATCH_VAL_L */ + /* offset address */ 0x4BE8, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ ACL_LATCH_VAL_L_FIELDS + }, + { /* register name ACL_LATCH_VAL_H */ + /* offset address */ 0x4BEC, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ ACL_LATCH_VAL_H_FIELDS + }, + { /* register name PTP_TIME_TOD_DELAY */ + /* offset address */ 0x7C20, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PTP_TIME_TOD_DELAY_FIELDS + }, + { /* register name PTP_TIME_OP_DURATION */ + /* offset address */ 0x7C24, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PTP_TIME_OP_DURATION_FIELDS + }, + { /* register name PTP_DUMMY_RG02 */ + /* offset address */ 0x7C28, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PTP_DUMMY_RG02_FIELDS + }, + { /* register name PTP_DUMMY_RG03 */ + /* offset address */ 0x7C2C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PTP_DUMMY_RG03_FIELDS + }, + { /* register name PTP_OTAG_CONFIG0 */ + /* offset address */ 0x7C30, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PTP_OTAG_CONFIG0_FIELDS + }, + { /* register name PTP_OTAG_CONFIG1 */ + /* offset address */ 0x7C34, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PTP_OTAG_CONFIG1_FIELDS + }, + { /* register name PTP_OTAG_CONFIG2 */ + /* offset address */ 0x7C38, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PTP_OTAG_CONFIG2_FIELDS + }, + { /* register name PTP_OTAG_CONFIG3 */ + /* offset address */ 0x7C3C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PTP_OTAG_CONFIG3_FIELDS + }, + { /* register name PTP_ITAG_CONFIG0 */ + /* offset address */ 0x7C40, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PTP_ITAG_CONFIG0_FIELDS + }, + { /* register name PTP_DUMMY_RG09 */ + /* offset address */ 0x7C44, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PTP_DUMMY_RG09_FIELDS + }, + { /* register name PTP_DUMMY_RG10 */ + /* offset address */ 0x7C48, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PTP_DUMMY_RG10_FIELDS + }, + { /* register name PTP_APPLY_FREQ */ + /* offset address */ 0x7C4C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PTP_APPLY_FREQ_FIELDS + }, + { /* register name PTP_TIME_FREQ0 */ + /* offset address */ 0x7C50, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PTP_TIME_FREQ0_FIELDS + }, + { /* register name PTP_TIME_FREQ1 */ + /* offset address */ 0x7C54, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PTP_TIME_FREQ1_FIELDS + }, + { /* register name PTP_CUR_TIME_FREQ0 */ + /* offset address */ 0x7C58, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PTP_CUR_TIME_FREQ0_FIELDS + }, + { /* register name PTP_CUR_TIME_FREQ1 */ + /* offset address */ 0x7C5C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PTP_CUR_TIME_FREQ1_FIELDS + }, + { /* register name PTP_TIME_NSEC0 */ + /* offset address */ 0x7C60, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PTP_TIME_NSEC0_FIELDS + }, + { /* register name PTP_TIME_NSEC1 */ + /* offset address */ 0x7C64, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PTP_TIME_NSEC1_FIELDS + }, + { /* register name PTP_TIME_SEC0 */ + /* offset address */ 0x7C68, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PTP_TIME_SEC0_FIELDS + }, + { /* register name PTP_TIME_SEC1 */ + /* offset address */ 0x7C6C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PTP_TIME_SEC1_FIELDS + }, + { /* register name PTP_TIME_SEC2 */ + /* offset address */ 0x7C70, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PTP_TIME_SEC2_FIELDS + }, + { /* register name PTP_TIME_CRTL */ + /* offset address */ 0x7C74, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PTP_TIME_CRTL_FIELDS + }, + { /* register name PTP_TIME_NSEC_RD0 */ + /* offset address */ 0x7C78, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PTP_TIME_NSEC_RD0_FIELDS + }, + { /* register name PTP_TIME_NSEC_RD1 */ + /* offset address */ 0x7C7C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PTP_TIME_NSEC_RD1_FIELDS + }, + { /* register name PTP_TIME_SEC_RD0 */ + /* offset address */ 0x7C80, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PTP_TIME_SEC_RD0_FIELDS + }, + { /* register name PTP_TIME_SEC_RD1 */ + /* offset address */ 0x7C84, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PTP_TIME_SEC_RD1_FIELDS + }, + { /* register name PTP_TIME_SEC_RD2 */ + /* offset address */ 0x7C88, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PTP_TIME_SEC_RD2_FIELDS + }, + { /* register name PTP_CLKOUT_NSEC0 */ + /* offset address */ 0x7C8C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PTP_CLKOUT_NSEC0_FIELDS + }, + { /* register name PTP_CLKOUT_NSEC1 */ + /* offset address */ 0x7C90, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PTP_CLKOUT_NSEC1_FIELDS + }, + { /* register name PTP_CLKOUT_SEC0 */ + /* offset address */ 0x7C94, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PTP_CLKOUT_SEC0_FIELDS + }, + { /* register name PTP_CLKOUT_SEC1 */ + /* offset address */ 0x7C98, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PTP_CLKOUT_SEC1_FIELDS + }, + { /* register name PTP_CLKOUT_SEC2 */ + /* offset address */ 0x7C9C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PTP_CLKOUT_SEC2_FIELDS + }, + { /* register name PTP_CLKOUT_CTRL */ + /* offset address */ 0x7CA0, + /* field numbers */ 5, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PTP_CLKOUT_CTRL_FIELDS + }, + { /* register name PTP_CLKOUT_HALF_PERD_NS_L */ + /* offset address */ 0x7CA4, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PTP_CLKOUT_HALF_PERD_NS_L_FIELDS + }, + { /* register name PTP_CLKOUT_HALF_PERD_NS_H */ + /* offset address */ 0x7CA8, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PTP_CLKOUT_HALF_PERD_NS_H_FIELDS + }, + { /* register name PTP_TIME_OP_CTRL */ + /* offset address */ 0x7CAC, + /* field numbers */ 6, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PTP_TIME_OP_CTRL_FIELDS + }, + { /* register name PTP_PPS_CTRL */ + /* offset address */ 0x7CB0, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PTP_PPS_CTRL_FIELDS + }, + { /* register name PTP_TX_TIMESTAMP_RD0 */ + /* offset address */ 0x7CB4, + /* field numbers */ 6, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PTP_TX_TIMESTAMP_RD0_FIELDS + }, + { /* register name PTP_TX_TIMESTAMP_RD1 */ + /* offset address */ 0x7CB8, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PTP_TX_TIMESTAMP_RD1_FIELDS + }, + { /* register name PTP_TX_TIMESTAMP_RD2 */ + /* offset address */ 0x7CBC, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PTP_TX_TIMESTAMP_RD2_FIELDS + }, + { /* register name PTP_TX_TIMESTAMP_RD3 */ + /* offset address */ 0x7CC0, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PTP_TX_TIMESTAMP_RD3_FIELDS + }, + { /* register name PTP_MIB_INTR */ + /* offset address */ 0x7CC4, + /* field numbers */ 7, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PTP_MIB_INTR_FIELDS + }, + { /* register name PTP_GLOBAL_DBG */ + /* offset address */ 0x7CC8, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PTP_GLOBAL_DBG_FIELDS + }, + { /* register name PTP_CLK_SRC_CTRL */ + /* offset address */ 0x7CCC, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PTP_CLK_SRC_CTRL_FIELDS + }, + { /* register name PTP_CLKOUT_HALF_PERD_FS_L */ + /* offset address */ 0x7CD0, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PTP_CLKOUT_HALF_PERD_FS_L_FIELDS + }, + { /* register name PTP_CLKOUT_HALF_PERD_FS_H */ + /* offset address */ 0x7CD4, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PTP_CLKOUT_HALF_PERD_FS_H_FIELDS + }, + { /* register name PTP_DUMMY_RG46 */ + /* offset address */ 0x7CD8, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PTP_DUMMY_RG46_FIELDS + }, + { /* register name PTP_DUMMY_RG47 */ + /* offset address */ 0x7CDC, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PTP_DUMMY_RG47_FIELDS + }, + { /* register name PPS_IN_LATCH_TIME_NSEC_L */ + /* offset address */ 0x7CE0, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PPS_IN_LATCH_TIME_NSEC_L_FIELDS + }, + { /* register name PPS_IN_LATCH_TIME_NSEC_H */ + /* offset address */ 0x7CE4, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PPS_IN_LATCH_TIME_NSEC_H_FIELDS + }, + { /* register name PPS_IN_LATCH_TIME_SEC_L */ + /* offset address */ 0x7CE8, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PPS_IN_LATCH_TIME_SEC_L_FIELDS + }, + { /* register name PPS_IN_LATCH_TIME_SEC_M */ + /* offset address */ 0x7CEC, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PPS_IN_LATCH_TIME_SEC_M_FIELDS + }, + { /* register name PPS_IN_LATCH_TIME_SEC_H */ + /* offset address */ 0x7CF0, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PPS_IN_LATCH_TIME_SEC_H_FIELDS + }, + { /* register name PTP_DUMMY_RG53 */ + /* offset address */ 0x7CF4, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PTP_DUMMY_RG53_FIELDS + }, + { /* register name PTP_DUMMY_RG54 */ + /* offset address */ 0x7CF8, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PTP_DUMMY_RG54_FIELDS + }, + { /* register name PTP_DUMMY_RG55 */ + /* offset address */ 0x7CFC, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PTP_DUMMY_RG55_FIELDS + }, + { /* register name PTP_DUMMY_RG56 */ + /* offset address */ 0x7D00, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PTP_DUMMY_RG56_FIELDS + }, + { /* register name PTP_DUMMY_RG57 */ + /* offset address */ 0x7D04, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PTP_DUMMY_RG57_FIELDS + }, + { /* register name PTP_DUMMY_RG58 */ + /* offset address */ 0x7D08, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PTP_DUMMY_RG58_FIELDS + }, + { /* register name PTP_DUMMY_RG59 */ + /* offset address */ 0x7D0C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PTP_DUMMY_RG59_FIELDS + }, + { /* register name PTP_DUMMY_RG60 */ + /* offset address */ 0x7D10, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PTP_DUMMY_RG60_FIELDS + }, + { /* register name PTP_DUMMY_RG61 */ + /* offset address */ 0x7D14, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PTP_DUMMY_RG61_FIELDS + }, + { /* register name PTP_TIME_SPEED_UP */ + /* offset address */ 0x7D18, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PTP_TIME_SPEED_UP_FIELDS + }, + { /* register name PTP_VERSION */ + /* offset address */ 0x7D1C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PTP_VERSION_FIELDS + }, + { /* register name P0_PORT_CTRL */ + /* offset address */ 0x7D20, + /* field numbers */ 7, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ P0_PORT_CTRL_FIELDS + }, + { /* register name P0_LINK_DELAY_H */ + /* offset address */ 0x7D24, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ P0_LINK_DELAY_H_FIELDS + }, + { /* register name P0_MISC_CTRL */ + /* offset address */ 0x7D28, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ P0_MISC_CTRL_FIELDS + }, + { /* register name P0_TX_IMBAL */ + /* offset address */ 0x7D2C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ P0_TX_IMBAL_FIELDS + }, + { /* register name P0_RX_IMBAL */ + /* offset address */ 0x7D30, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ P0_RX_IMBAL_FIELDS + }, + { /* register name P0_PTP_PORTID */ + /* offset address */ 0x7D34, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ P0_PTP_PORTID_FIELDS + }, + { /* register name P0_PTP_DUMMY_RG06 */ + /* offset address */ 0x7D38, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ P0_PTP_DUMMY_RG06_FIELDS + }, + { /* register name P0_DBG_PTP_CTRL */ + /* offset address */ 0x7D3C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ P0_DBG_PTP_CTRL_FIELDS + }, + { /* register name TOD_OUT_DATA_CTRL */ + /* offset address */ 0x7E60, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 15, + /* port index */ 0, 0, + /* register fields */ TOD_OUT_DATA_CTRL_FIELDS + }, + { /* register name TOD_OUT_CTRL0 */ + /* offset address */ 0x7EA0, + /* field numbers */ 5, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ TOD_OUT_CTRL0_FIELDS + }, + { /* register name TOD_OUT_CTRL1 */ + /* offset address */ 0x7EA4, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ TOD_OUT_CTRL1_FIELDS + }, + { /* register name TOD_SARP_GPS_WEEK */ + /* offset address */ 0x7EA8, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ TOD_SARP_GPS_WEEK_FIELDS + }, + { /* register name TOD_SARP_GPS_SEC_L */ + /* offset address */ 0x7EAC, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ TOD_SARP_GPS_SEC_L_FIELDS + }, + { /* register name TOD_SARP_GPS_SEC_H */ + /* offset address */ 0x7EB0, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ TOD_SARP_GPS_SEC_H_FIELDS + }, + { /* register name TOD_UART_SETTING */ + /* offset address */ 0x7EB4, + /* field numbers */ 9, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ TOD_UART_SETTING_FIELDS + }, + { /* register name TOD_INTR */ + /* offset address */ 0x7EB8, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ TOD_INTR_FIELDS + }, + { /* register name RX_STORM_BCAST_CTRL */ + /* offset address */ 0x54E4, + /* field numbers */ 1, + /* array offset */ 1, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ RX_STORM_BCAST_CTRL_FIELDS + }, + { /* register name RX_STORM_MCAST_CTRL */ + /* offset address */ 0x54E8, + /* field numbers */ 1, + /* array offset */ 1, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ RX_STORM_MCAST_CTRL_FIELDS + }, + { /* register name RX_STORM_UNUCAST_CTRL */ + /* offset address */ 0x54EC, + /* field numbers */ 1, + /* array offset */ 1, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ RX_STORM_UNUCAST_CTRL_FIELDS + }, + { /* register name RX_STORM_UNMCAST_CTRL */ + /* offset address */ 0x54F0, + /* field numbers */ 1, + /* array offset */ 1, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ RX_STORM_UNMCAST_CTRL_FIELDS + }, + { /* register name RX_STORM_BCAST_METER */ + /* offset address */ 0x54F4, + /* field numbers */ 1, + /* array offset */ 6, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ RX_STORM_BCAST_METER_FIELDS + }, + { /* register name RX_STORM_MCAST_METER */ + /* offset address */ 0x54FC, + /* field numbers */ 1, + /* array offset */ 6, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ RX_STORM_MCAST_METER_FIELDS + }, + { /* register name RX_STORM_UNUCAST_METER */ + /* offset address */ 0x5504, + /* field numbers */ 1, + /* array offset */ 6, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ RX_STORM_UNUCAST_METER_FIELDS + }, + { /* register name RX_STORM_UNMCAST_METER */ + /* offset address */ 0x550C, + /* field numbers */ 1, + /* array offset */ 6, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ RX_STORM_UNMCAST_METER_FIELDS + }, + { /* register name CFG_STORM_EXT */ + /* offset address */ 0x5514, + /* field numbers */ 6, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ CFG_STORM_EXT_FIELDS + }, + { /* register name STORM_EXT_MTRIDX_CFG */ + /* offset address */ 0x5518, + /* field numbers */ 8, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ STORM_EXT_MTRIDX_CFG_FIELDS + }, + { /* register name IGBW_CTRL */ + /* offset address */ 0x4C10, + /* field numbers */ 10, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ IGBW_CTRL_FIELDS + }, + { /* register name IGBW_LB_CTRL */ + /* offset address */ 0x4C14, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ IGBW_LB_CTRL_FIELDS + }, + { /* register name IGBW_PORT_CTRL */ + /* offset address */ 0x4C18, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 8, + /* register fields */ IGBW_PORT_CTRL_FIELDS + }, + { /* register name IGBW_PORT_BURST_CTRL */ + /* offset address */ 0x4C3C, + /* field numbers */ 4, + /* array offset */ 64, + /* array index */ 0, 0, + /* port index */ 0, 8, + /* register fields */ IGBW_PORT_BURST_CTRL_FIELDS + }, + { /* register name IGBW_PORT_LB_RST */ + /* offset address */ 0x4C84, + /* field numbers */ 1, + /* array offset */ 1, + /* array index */ 0, 0, + /* port index */ 0, 8, + /* register fields */ IGBW_PORT_LB_RST_FIELDS + }, + { /* register name IGBW_PORT_CNGST_FLAG */ + /* offset address */ 0x4C88, + /* field numbers */ 1, + /* array offset */ 1, + /* array index */ 0, 0, + /* port index */ 0, 8, + /* register fields */ IGBW_PORT_CNGST_FLAG_FIELDS + }, + { /* register name IGBW_PORT_FC_CTRL */ + /* offset address */ 0x4C8C, + /* field numbers */ 1, + /* array offset */ 1, + /* array index */ 0, 0, + /* port index */ 0, 8, + /* register fields */ IGBW_PORT_FC_CTRL_FIELDS + }, + { /* register name IGBW_PORT_DROP_CTRL */ + /* offset address */ 0x4C90, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 8, + /* register fields */ IGBW_PORT_DROP_CTRL_FIELDS + }, + { /* register name EGBW_ENCAP_CTRL */ + /* offset address */ 0x4478, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ EGBW_ENCAP_CTRL_FIELDS + }, + { /* register name EGBW_CTRL */ + /* offset address */ 0x447C, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ EGBW_CTRL_FIELDS + }, + { /* register name EGBW_LB_CTRL */ + /* offset address */ 0x4480, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ EGBW_LB_CTRL_FIELDS + }, + { /* register name EGBW_PORT_CTRL */ + /* offset address */ 0x1C34, + /* field numbers */ 5, + /* array offset */ 64, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ EGBW_PORT_CTRL_FIELDS + }, + { /* register name EGBW_PORT_LB_RST */ + /* offset address */ 0x4484, + /* field numbers */ 1, + /* array offset */ 1, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ EGBW_PORT_LB_RST_FIELDS + }, + { /* register name EGBW_PORT_Q_MAX_LB_CTRL_SET */ + /* offset address */ 0x1C3C, + /* field numbers */ 5, + /* array offset */ 64, + /* array index */ 0, 7, + /* port index */ 0, 9, + /* register fields */ EGBW_PORT_Q_MAX_LB_CTRL_SET_FIELDS + }, + { /* register name EGBW_PORT_Q_MAX_LB_RST_SET */ + /* offset address */ 0x1C7C, + /* field numbers */ 1, + /* array offset */ 1, + /* array index */ 0, 7, + /* port index */ 0, 9, + /* register fields */ EGBW_PORT_Q_MAX_LB_RST_SET_FIELDS + }, + { /* register name EGBW_PORT_Q_ASSURED_FIX_BURST_CTRL_SET */ + /* offset address */ 0x1C80, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 7, + /* port index */ 0, 9, + /* register fields */ EGBW_PORT_Q_ASSURED_FIX_BURST_CTRL_SET_FIELDS + }, + { /* register name EGBW_PORT_Q_ASSURED_LB_CTRL_SET */ + /* offset address */ 0x1CA0, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 7, + /* port index */ 0, 9, + /* register fields */ EGBW_PORT_Q_ASSURED_LB_CTRL_SET_FIELDS + }, + { /* register name EGBW_PORT_Q_FIX_LB_CTRL_SET */ + /* offset address */ 0x1CC0, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 7, + /* port index */ 0, 9, + /* register fields */ EGBW_PORT_Q_FIX_LB_CTRL_SET_FIELDS + }, + { /* register name EGBW_PORT_Q_ASSURED_FIX_LB_RST_SET */ + /* offset address */ 0x1CE0, + /* field numbers */ 1, + /* array offset */ 1, + /* array index */ 0, 7, + /* port index */ 0, 9, + /* register fields */ EGBW_PORT_Q_ASSURED_FIX_LB_RST_SET_FIELDS + }, + { /* register name EGBW_RATE_10M_CTRL */ + /* offset address */ 0x4488, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ EGBW_RATE_10M_CTRL_FIELDS + }, + { /* register name EGBW_RATE_100M_CTRL */ + /* offset address */ 0x448C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ EGBW_RATE_100M_CTRL_FIELDS + }, + { /* register name EGBW_RATE_1G_CTRL */ + /* offset address */ 0x4490, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ EGBW_RATE_1G_CTRL_FIELDS + }, + { /* register name EGBW_RATE_500M_CTRL */ + /* offset address */ 0x4494, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ EGBW_RATE_500M_CTRL_FIELDS + }, + { /* register name EGBW_RATE_10G_CTRL */ + /* offset address */ 0x4498, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ EGBW_RATE_10G_CTRL_FIELDS + }, + { /* register name EGBW_RATE_2500M_CTRL */ + /* offset address */ 0x449C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ EGBW_RATE_2500M_CTRL_FIELDS + }, + { /* register name EGBW_RATE_1250M_CTRL */ + /* offset address */ 0x44A0, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ EGBW_RATE_1250M_CTRL_FIELDS + }, + { /* register name EGBW_RATE_5G_CTRL */ + /* offset address */ 0x44A4, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ EGBW_RATE_5G_CTRL_FIELDS + }, + { /* register name DMY_REG0_EGRESS_CTRL */ + /* offset address */ 0x44A8, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ DMY_REG0_EGRESS_CTRL_FIELDS + }, + { /* register name SHARED_METER_RATE_CTRL */ + /* offset address */ 0x5CF0, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 63, + /* port index */ 0, 0, + /* register fields */ SHARED_METER_RATE_CTRL_FIELDS + }, + { /* register name SHARED_METER_BURST_CTRL */ + /* offset address */ 0x5DF0, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 63, + /* port index */ 0, 0, + /* register fields */ SHARED_METER_BURST_CTRL_FIELDS + }, + { /* register name SHARED_METER_MODE */ + /* offset address */ 0x5EF0, + /* field numbers */ 1, + /* array offset */ 1, + /* array index */ 0, 63, + /* port index */ 0, 0, + /* register fields */ SHARED_METER_MODE_FIELDS + }, + { /* register name SHARED_METER_EXCEED */ + /* offset address */ 0x5EF8, + /* field numbers */ 1, + /* array offset */ 1, + /* array index */ 0, 63, + /* port index */ 0, 0, + /* register fields */ SHARED_METER_EXCEED_FIELDS + }, + { /* register name SHARED_METER_EXCEED_ICPU */ + /* offset address */ 0x5F00, + /* field numbers */ 1, + /* array offset */ 1, + /* array index */ 0, 63, + /* port index */ 0, 0, + /* register fields */ SHARED_METER_EXCEED_ICPU_FIELDS + }, + { /* register name SHARED_METER_IPG_CTRL */ + /* offset address */ 0x5F08, + /* field numbers */ 1, + /* array offset */ 1, + /* array index */ 0, 63, + /* port index */ 0, 0, + /* register fields */ SHARED_METER_IPG_CTRL_FIELDS + }, + { /* register name SHARED_METER_LB_CTRL */ + /* offset address */ 0x5F10, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SHARED_METER_LB_CTRL_FIELDS + }, + { /* register name SHARED_METER_LB_PPS_CTRL */ + /* offset address */ 0x5F14, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SHARED_METER_LB_PPS_CTRL_FIELDS + }, + { /* register name FC_CTRL */ + /* offset address */ 0x7120, + /* field numbers */ 5, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ FC_CTRL_FIELDS + }, + { /* register name FC_PORT_ACT_CTRL */ + /* offset address */ 0x7124, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ FC_PORT_ACT_CTRL_FIELDS + }, + { /* register name FC_GLB_SYS_UTIL_THR */ + /* offset address */ 0x714C, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ FC_GLB_SYS_UTIL_THR_FIELDS + }, + { /* register name FC_GLB_DROP_THR */ + /* offset address */ 0x7150, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ FC_GLB_DROP_THR_FIELDS + }, + { /* register name FC_GLB_HI_THR */ + /* offset address */ 0x7154, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ FC_GLB_HI_THR_FIELDS + }, + { /* register name FC_GLB_LO_THR */ + /* offset address */ 0x7158, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ FC_GLB_LO_THR_FIELDS + }, + { /* register name FC_GLB_FCOFF_HI_THR */ + /* offset address */ 0x715C, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ FC_GLB_FCOFF_HI_THR_FIELDS + }, + { /* register name FC_GLB_FCOFF_LO_THR */ + /* offset address */ 0x7160, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ FC_GLB_FCOFF_LO_THR_FIELDS + }, + { /* register name FC_JUMBO_HI_THR */ + /* offset address */ 0x7164, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ FC_JUMBO_HI_THR_FIELDS + }, + { /* register name FC_JUMBO_LO_THR */ + /* offset address */ 0x7168, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ FC_JUMBO_LO_THR_FIELDS + }, + { /* register name FC_JUMBO_FCOFF_HI_THR */ + /* offset address */ 0x716C, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ FC_JUMBO_FCOFF_HI_THR_FIELDS + }, + { /* register name FC_JUMBO_FCOFF_LO_THR */ + /* offset address */ 0x7170, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ FC_JUMBO_FCOFF_LO_THR_FIELDS + }, + { /* register name FC_JUMBO_THR_ADJUST */ + /* offset address */ 0x7174, + /* field numbers */ 5, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ FC_JUMBO_THR_ADJUST_FIELDS + }, + { /* register name FC_PORT_HI_THR */ + /* offset address */ 0x7178, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 3, + /* port index */ 0, 0, + /* register fields */ FC_PORT_HI_THR_FIELDS + }, + { /* register name FC_PORT_LO_THR */ + /* offset address */ 0x7188, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 3, + /* port index */ 0, 0, + /* register fields */ FC_PORT_LO_THR_FIELDS + }, + { /* register name FC_PORT_FCOFF_HI_THR */ + /* offset address */ 0x7198, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 3, + /* port index */ 0, 0, + /* register fields */ FC_PORT_FCOFF_HI_THR_FIELDS + }, + { /* register name FC_PORT_FCOFF_LO_THR */ + /* offset address */ 0x71A8, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 3, + /* port index */ 0, 0, + /* register fields */ FC_PORT_FCOFF_LO_THR_FIELDS + }, + { /* register name FC_PORT_GUAR_THR */ + /* offset address */ 0x71B8, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 3, + /* port index */ 0, 0, + /* register fields */ FC_PORT_GUAR_THR_FIELDS + }, + { /* register name FC_PORT_THR_SET_SEL */ + /* offset address */ 0x71C8, + /* field numbers */ 1, + /* array offset */ 2, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ FC_PORT_THR_SET_SEL_FIELDS + }, + { /* register name FC_PORT_EGR_DROP_CTRL */ + /* offset address */ 0x50F4, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ FC_PORT_EGR_DROP_CTRL_FIELDS + }, + { /* register name FC_HOL_PRVNT_CTRL */ + /* offset address */ 0x511C, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ FC_HOL_PRVNT_CTRL_FIELDS + }, + { /* register name FC_PORT_Q_EGR_DROP_CTRL_SET */ + /* offset address */ 0x5120, + /* field numbers */ 1, + /* array offset */ 1, + /* array index */ 0, 7, + /* port index */ 0, 9, + /* register fields */ FC_PORT_Q_EGR_DROP_CTRL_SET_FIELDS + }, + { /* register name FC_PORT_Q_EGR_FORCE_DROP_CTRL_SET */ + /* offset address */ 0x5148, + /* field numbers */ 1, + /* array offset */ 1, + /* array index */ 0, 7, + /* port index */ 0, 9, + /* register fields */ FC_PORT_Q_EGR_FORCE_DROP_CTRL_SET_FIELDS + }, + { /* register name FC_Q_EGR_DROP_THR */ + /* offset address */ 0x44AC, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 3, + /* port index */ 0, 7, + /* register fields */ FC_Q_EGR_DROP_THR_FIELDS + }, + { /* register name FC_PORT_EGR_DROP_THR_SET_SEL */ + /* offset address */ 0x452C, + /* field numbers */ 1, + /* array offset */ 2, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ FC_PORT_EGR_DROP_THR_SET_SEL_FIELDS + }, + { /* register name FC_GLB_PAGE_CNT */ + /* offset address */ 0x71CC, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ FC_GLB_PAGE_CNT_FIELDS + }, + { /* register name FC_PORT_PAGE_CNT */ + /* offset address */ 0x71D0, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ FC_PORT_PAGE_CNT_FIELDS + }, + { /* register name FC_GLB_PAGE_PEAKCNT */ + /* offset address */ 0x71F8, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ FC_GLB_PAGE_PEAKCNT_FIELDS + }, + { /* register name FC_PORT_CUR_PAGE_CNT */ + /* offset address */ 0x71FC, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ FC_PORT_CUR_PAGE_CNT_FIELDS + }, + { /* register name FC_PORT_PEAK_PAGE_CNT */ + /* offset address */ 0x7224, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ FC_PORT_PEAK_PAGE_CNT_FIELDS + }, + { /* register name FC_PORT_EGR_PAGE_CNT */ + /* offset address */ 0x1CE4, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ FC_PORT_EGR_PAGE_CNT_FIELDS + }, + { /* register name FC_PORT_Q_EGR_PAGE_CNT_SET */ + /* offset address */ 0x1CE8, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 7, + /* port index */ 0, 9, + /* register fields */ FC_PORT_Q_EGR_PAGE_CNT_SET_FIELDS + }, + { /* register name FC_PORT_Q_EGR_PKT_CNT_SET */ + /* offset address */ 0x1D08, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 7, + /* port index */ 0, 9, + /* register fields */ FC_PORT_Q_EGR_PKT_CNT_SET_FIELDS + }, + { /* register name FC_PORT_PAGE_CNT_ERROR */ + /* offset address */ 0x75A4, + /* field numbers */ 1, + /* array offset */ 1, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ FC_PORT_PAGE_CNT_ERROR_FIELDS + }, + { /* register name PFC_ENABLE_0 */ + /* offset address */ 0x103C, + /* field numbers */ 5, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 1, + /* register fields */ PFC_ENABLE_0_FIELDS + }, + { /* register name PFC_ENABLE_1 */ + /* offset address */ 0x724C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 1, + /* register fields */ PFC_ENABLE_1_FIELDS + }, + { /* register name PFC_CTRL_0 */ + /* offset address */ 0x551C, + /* field numbers */ 6, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 1, + /* register fields */ PFC_CTRL_0_FIELDS + }, + { /* register name PFC_ACTDROP_CTRL */ + /* offset address */ 0x5524, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 7, + /* port index */ 0, 1, + /* register fields */ PFC_ACTDROP_CTRL_FIELDS + }, + { /* register name P_PFC_THR */ + /* offset address */ 0x7254, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 2, + /* port index */ 0, 0, + /* register fields */ P_PFC_THR_FIELDS + }, + { /* register name P_PFCOFF_THR */ + /* offset address */ 0x7260, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 2, + /* port index */ 0, 0, + /* register fields */ P_PFCOFF_THR_FIELDS + }, + { /* register name PG_HI_THR */ + /* offset address */ 0x726C, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 7, + /* port index */ 0, 2, + /* register fields */ PG_HI_THR_FIELDS + }, + { /* register name PG_LO_THR */ + /* offset address */ 0x72CC, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 7, + /* port index */ 0, 2, + /* register fields */ PG_LO_THR_FIELDS + }, + { /* register name PG_PFCOFF_HI_THR */ + /* offset address */ 0x732C, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 7, + /* port index */ 0, 2, + /* register fields */ PG_PFCOFF_HI_THR_FIELDS + }, + { /* register name PG_PFCOFF_LO_THR */ + /* offset address */ 0x738C, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 7, + /* port index */ 0, 2, + /* register fields */ PG_PFCOFF_LO_THR_FIELDS + }, + { /* register name PG_GURANTEE_THR */ + /* offset address */ 0x73EC, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 7, + /* port index */ 0, 2, + /* register fields */ PG_GURANTEE_THR_FIELDS + }, + { /* register name PFC_CTRL_1 */ + /* offset address */ 0x744C, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 1, + /* register fields */ PFC_CTRL_1_FIELDS + }, + { /* register name PFC_CTRL_2 */ + /* offset address */ 0x1044, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 1, + /* register fields */ PFC_CTRL_2_FIELDS + }, + { /* register name PG_2_PEV_TABLE */ + /* offset address */ 0x104C, + /* field numbers */ 8, + /* array offset */ 64, + /* array index */ 0, 0, + /* port index */ 0, 1, + /* register fields */ PG_2_PEV_TABLE_FIELDS + }, + { /* register name DPRI_2_PG_TABLE */ + /* offset address */ 0x5564, + /* field numbers */ 9, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 1, + /* register fields */ DPRI_2_PG_TABLE_FIELDS + }, + { /* register name PCP_2_PG_TABLE */ + /* offset address */ 0x556C, + /* field numbers */ 9, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 1, + /* register fields */ PCP_2_PG_TABLE_FIELDS + }, + { /* register name PEV_2_TXQ_TABLE */ + /* offset address */ 0x105C, + /* field numbers */ 8, + /* array offset */ 64, + /* array index */ 0, 0, + /* port index */ 0, 1, + /* register fields */ PEV_2_TXQ_TABLE_FIELDS + }, + { /* register name PFC_PORT_PG_RX_PAGE_CNT */ + /* offset address */ 0x7454, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 7, + /* port index */ 0, 1, + /* register fields */ PFC_PORT_PG_RX_PAGE_CNT_FIELDS + }, + { /* register name SC_P_CTRL */ + /* offset address */ 0x4530, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SC_P_CTRL_FIELDS + }, + { /* register name SC_P_EN */ + /* offset address */ 0x1260, + /* field numbers */ 6, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ SC_P_EN_FIELDS + }, + { /* register name PORT_PRI */ + /* offset address */ 0x5170, + /* field numbers */ 1, + /* array offset */ 3, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ PORT_PRI_FIELDS + }, + { /* register name DOT1Q_PRI_REMAP */ + /* offset address */ 0x5174, + /* field numbers */ 16, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ DOT1Q_PRI_REMAP_FIELDS + }, + { /* register name PRI_SEL_REMAP_DSCP */ + /* offset address */ 0x5178, + /* field numbers */ 1, + /* array offset */ 3, + /* array index */ 0, 63, + /* port index */ 0, 0, + /* register fields */ PRI_SEL_REMAP_DSCP_FIELDS + }, + { /* register name RSPAN_PRI_REMAP */ + /* offset address */ 0x5194, + /* field numbers */ 16, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RSPAN_PRI_REMAP_FIELDS + }, + { /* register name PRI_WEIGHT */ + /* offset address */ 0x5198, + /* field numbers */ 6, + /* array offset */ 32, + /* array index */ 0, 1, + /* port index */ 0, 0, + /* register fields */ PRI_WEIGHT_FIELDS + }, + { /* register name PORT_WEIGHT_SEL */ + /* offset address */ 0x51A0, + /* field numbers */ 1, + /* array offset */ 1, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ PORT_WEIGHT_SEL_FIELDS + }, + { /* register name QID_TO_PRI */ + /* offset address */ 0x51A4, + /* field numbers */ 16, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ QID_TO_PRI_FIELDS + }, + { /* register name INCPU_PRI_REMAP */ + /* offset address */ 0x51CC, + /* field numbers */ 16, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ INCPU_PRI_REMAP_FIELDS + }, + { /* register name EXCPU_PRI_REMAP */ + /* offset address */ 0x51D0, + /* field numbers */ 16, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ EXCPU_PRI_REMAP_FIELDS + }, + { /* register name PORT_PRI_DUP */ + /* offset address */ 0x674C, + /* field numbers */ 1, + /* array offset */ 3, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ PORT_PRI_DUP_FIELDS + }, + { /* register name SCHED_PORT_Q_CTRL_SET */ + /* offset address */ 0x1D28, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 7, + /* port index */ 0, 9, + /* register fields */ SCHED_PORT_Q_CTRL_SET_FIELDS + }, + { /* register name SCHED_PORT_ALGO_CTRL */ + /* offset address */ 0x4534, + /* field numbers */ 1, + /* array offset */ 1, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ SCHED_PORT_ALGO_CTRL_FIELDS + }, + { /* register name CFG_TG_URR_SEL */ + /* offset address */ 0x4538, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ CFG_TG_URR_SEL_FIELDS + }, + { /* register name RMK_CTRL */ + /* offset address */ 0x6750, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RMK_CTRL_FIELDS + }, + { /* register name RMK_PORT_CTRL */ + /* offset address */ 0x6754, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ RMK_PORT_CTRL_FIELDS + }, + { /* register name RMK_INTPRI2IPRI_CTRL */ + /* offset address */ 0x677C, + /* field numbers */ 16, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RMK_INTPRI2IPRI_CTRL_FIELDS + }, + { /* register name RMK_INTPRI2DSCP_CTRL */ + /* offset address */ 0x6780, + /* field numbers */ 1, + /* array offset */ 6, + /* array index */ 0, 7, + /* port index */ 0, 0, + /* register fields */ RMK_INTPRI2DSCP_CTRL_FIELDS + }, + { /* register name RMK_DSCP2DSCP_CTRL */ + /* offset address */ 0x6788, + /* field numbers */ 1, + /* array offset */ 6, + /* array index */ 0, 63, + /* port index */ 0, 0, + /* register fields */ RMK_DSCP2DSCP_CTRL_FIELDS + }, + { /* register name DOT1X_PORT_EN */ + /* offset address */ 0x5574, + /* field numbers */ 1, + /* array offset */ 1, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ DOT1X_PORT_EN_FIELDS + }, + { /* register name DOT1X_MAC_EN */ + /* offset address */ 0x5578, + /* field numbers */ 1, + /* array offset */ 1, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ DOT1X_MAC_EN_FIELDS + }, + { /* register name DOT1X_PORT_AUTH */ + /* offset address */ 0x557C, + /* field numbers */ 1, + /* array offset */ 1, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ DOT1X_PORT_AUTH_FIELDS + }, + { /* register name DOT1X_PORT_DIR */ + /* offset address */ 0x5580, + /* field numbers */ 1, + /* array offset */ 1, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ DOT1X_PORT_DIR_FIELDS + }, + { /* register name DOT1X_TRAP_PRIORITY */ + /* offset address */ 0x51D4, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ DOT1X_TRAP_PRIORITY_FIELDS + }, + { /* register name DOT1X_UNAUTH_ACT */ + /* offset address */ 0x5584, + /* field numbers */ 1, + /* array offset */ 2, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ DOT1X_UNAUTH_ACT_FIELDS + }, + { /* register name DOT1X_TRAP_CPU_SEL */ + /* offset address */ 0x51D8, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ DOT1X_TRAP_CPU_SEL_FIELDS + }, + { /* register name DOT1X_CFG */ + /* offset address */ 0x5588, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ DOT1X_CFG_FIELDS + }, + { /* register name ATK_PRVNT_CTRL */ + /* offset address */ 0x51DC, + /* field numbers */ 12, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ ATK_PRVNT_CTRL_FIELDS + }, + { /* register name MIN_TCPHDR_LEN */ + /* offset address */ 0x51E0, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MIN_TCPHDR_LEN_FIELDS + }, + { /* register name WOL_CTRL */ + /* offset address */ 0x6F4C, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ WOL_CTRL_FIELDS + }, + { /* register name WOL_MAC0 */ + /* offset address */ 0x6F50, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ WOL_MAC0_FIELDS + }, + { /* register name WOL_MAC1 */ + /* offset address */ 0x6F54, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ WOL_MAC1_FIELDS + }, + { /* register name PHY_WOL_CTRL */ + /* offset address */ 0xBD4, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PHY_WOL_CTRL_FIELDS + }, + { /* register name PHY_WOL_MAC0 */ + /* offset address */ 0xBD8, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PHY_WOL_MAC0_FIELDS + }, + { /* register name PHY_WOL_MAC1 */ + /* offset address */ 0xBDC, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PHY_WOL_MAC1_FIELDS + }, + { /* register name PARSER_FIELD_SELTOR_CTRL */ + /* offset address */ 0x6F58, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 15, + /* port index */ 0, 0, + /* register fields */ PARSER_FIELD_SELTOR_CTRL_FIELDS + }, + { /* register name PARSER_CTRL */ + /* offset address */ 0x6F98, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PARSER_CTRL_FIELDS + }, + { /* register name PARSER_DROP_REASON */ + /* offset address */ 0x1264, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ PARSER_DROP_REASON_FIELDS + }, + { /* register name HSB_DATA0 */ + /* offset address */ 0x6F9C, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ HSB_DATA0_FIELDS + }, + { /* register name HSB_DATA1 */ + /* offset address */ 0x6FA0, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ HSB_DATA1_FIELDS + }, + { /* register name HSB_DATA2 */ + /* offset address */ 0x6FA4, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ HSB_DATA2_FIELDS + }, + { /* register name HSB_DATA3 */ + /* offset address */ 0x6FA8, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ HSB_DATA3_FIELDS + }, + { /* register name HSB_DATA4 */ + /* offset address */ 0x6FAC, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ HSB_DATA4_FIELDS + }, + { /* register name HSB_DATA5 */ + /* offset address */ 0x6FB0, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ HSB_DATA5_FIELDS + }, + { /* register name HSB_DATA6 */ + /* offset address */ 0x6FB4, + /* field numbers */ 14, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ HSB_DATA6_FIELDS + }, + { /* register name HSB_DATA7 */ + /* offset address */ 0x6FB8, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ HSB_DATA7_FIELDS + }, + { /* register name HSB_DATA8 */ + /* offset address */ 0x6FBC, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ HSB_DATA8_FIELDS + }, + { /* register name HSB_DATA9 */ + /* offset address */ 0x6FC0, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ HSB_DATA9_FIELDS + }, + { /* register name HSB_DATA10 */ + /* offset address */ 0x6FC4, + /* field numbers */ 17, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ HSB_DATA10_FIELDS + }, + { /* register name HSB_DATA11 */ + /* offset address */ 0x6FC8, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ HSB_DATA11_FIELDS + }, + { /* register name HSB_DATA12 */ + /* offset address */ 0x6FCC, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ HSB_DATA12_FIELDS + }, + { /* register name HSB_DATA13 */ + /* offset address */ 0x6FD0, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ HSB_DATA13_FIELDS + }, + { /* register name HSB_DATA14 */ + /* offset address */ 0x6FD4, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ HSB_DATA14_FIELDS + }, + { /* register name HSB_DATA15 */ + /* offset address */ 0x6FD8, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ HSB_DATA15_FIELDS + }, + { /* register name HSB_DATA16 */ + /* offset address */ 0x6FDC, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ HSB_DATA16_FIELDS + }, + { /* register name HSB_DATA17 */ + /* offset address */ 0x6FE0, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ HSB_DATA17_FIELDS + }, + { /* register name HSB_DATA18 */ + /* offset address */ 0x6FE4, + /* field numbers */ 9, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ HSB_DATA18_FIELDS + }, + { /* register name HSB_DATA19 */ + /* offset address */ 0x6FE8, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ HSB_DATA19_FIELDS + }, + { /* register name HSB_CTRL */ + /* offset address */ 0x6FEC, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ HSB_CTRL_FIELDS + }, + { /* register name RLDP_RLPP_CTRL */ + /* offset address */ 0x106C, + /* field numbers */ 9, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RLDP_RLPP_CTRL_FIELDS + }, + { /* register name RETRY_CTRL */ + /* offset address */ 0x1070, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RETRY_CTRL_FIELDS + }, + { /* register name PERIOD_CTRL */ + /* offset address */ 0x1074, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PERIOD_CTRL_FIELDS + }, + { /* register name RLDP_TX_PMSK */ + /* offset address */ 0x1078, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RLDP_TX_PMSK_FIELDS + }, + { /* register name RAND_NUM0 */ + /* offset address */ 0x107C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RAND_NUM0_FIELDS + }, + { /* register name RAND_NUM1 */ + /* offset address */ 0x1080, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RAND_NUM1_FIELDS + }, + { /* register name MAGIC_NUM0 */ + /* offset address */ 0x1084, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MAGIC_NUM0_FIELDS + }, + { /* register name MAGIC_NUM1 */ + /* offset address */ 0x1088, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MAGIC_NUM1_FIELDS + }, + { /* register name LOOP_STATE */ + /* offset address */ 0x108C, + /* field numbers */ 1, + /* array offset */ 1, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ LOOP_STATE_FIELDS + }, + { /* register name LOOPED_STATE */ + /* offset address */ 0x1090, + /* field numbers */ 1, + /* array offset */ 1, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ LOOPED_STATE_FIELDS + }, + { /* register name LEAVE_LOOP_STATE */ + /* offset address */ 0x1094, + /* field numbers */ 1, + /* array offset */ 1, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ LEAVE_LOOP_STATE_FIELDS + }, + { /* register name LOOPPAIR */ + /* offset address */ 0x1098, + /* field numbers */ 1, + /* array offset */ 4, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ LOOPPAIR_FIELDS + }, + { /* register name RRCP_CTRL */ + /* offset address */ 0x51E4, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RRCP_CTRL_FIELDS + }, + { /* register name RXPORT_DSC_STS */ + /* offset address */ 0x75A8, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RXPORT_DSC_STS_FIELDS + }, + { /* register name SW_Q_RST_THR */ + /* offset address */ 0x75AC, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SW_Q_RST_THR_FIELDS + }, + { /* register name SW_Q_RST_P_THR */ + /* offset address */ 0x75B0, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SW_Q_RST_P_THR_FIELDS + }, + { /* register name LD_TX_DSC_STS */ + /* offset address */ 0x453C, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ LD_TX_DSC_STS_FIELDS + }, + { /* register name TX_DSC_CHK_TMR */ + /* offset address */ 0x4540, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ TX_DSC_CHK_TMR_FIELDS + }, + { /* register name RXFIFO_OVERFLOW_STS */ + /* offset address */ 0x10A0, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RXFIFO_OVERFLOW_STS_FIELDS + }, + { /* register name RXFIFO_RDEMPTY_STS */ + /* offset address */ 0x10A4, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RXFIFO_RDEMPTY_STS_FIELDS + }, + { /* register name TXFIFO_OVERFLOW_STS */ + /* offset address */ 0x10A8, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ TXFIFO_OVERFLOW_STS_FIELDS + }, + { /* register name TXFIFO_RDEMPTY_STS */ + /* offset address */ 0x10AC, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ TXFIFO_RDEMPTY_STS_FIELDS + }, + { /* register name PINGPONG_PLUS_STS */ + /* offset address */ 0x4544, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PINGPONG_PLUS_STS_FIELDS + }, + { /* register name TOKEN_STS */ + /* offset address */ 0x75B4, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ TOKEN_STS_FIELDS + }, + { /* register name SW_Q_RST_CNT */ + /* offset address */ 0x6054, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SW_Q_RST_CNT_FIELDS + }, + { /* register name AUTO_RECOVER_SRC_SEL_INGRESS */ + /* offset address */ 0x75B8, + /* field numbers */ 5, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ AUTO_RECOVER_SRC_SEL_INGRESS_FIELDS + }, + { /* register name AUTO_RECOVER_SRC_SEL_EGRESS */ + /* offset address */ 0x4548, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ AUTO_RECOVER_SRC_SEL_EGRESS_FIELDS + }, + { /* register name AUTO_RECOVER_SRC_SEL_MAC_0 */ + /* offset address */ 0x10B0, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ AUTO_RECOVER_SRC_SEL_MAC_0_FIELDS + }, + { /* register name AUTO_RECOVER_SRC_SEL_MAC_1 */ + /* offset address */ 0x10B4, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ AUTO_RECOVER_SRC_SEL_MAC_1_FIELDS + }, + { /* register name TRIG_AUTO_RECOVER_CTRL_INGRESS */ + /* offset address */ 0x75BC, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ TRIG_AUTO_RECOVER_CTRL_INGRESS_FIELDS + }, + { /* register name TRIG_AUTO_RECOVER_CTRL_EGRESS */ + /* offset address */ 0x454C, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ TRIG_AUTO_RECOVER_CTRL_EGRESS_FIELDS + }, + { /* register name TRIG_AUTO_RECOVER_CTRL_MAC */ + /* offset address */ 0x10B8, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ TRIG_AUTO_RECOVER_CTRL_MAC_FIELDS + }, + { /* register name AUTO_RECOVER_EVENT_FLAG_STS_INGRESS */ + /* offset address */ 0x75C0, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ AUTO_RECOVER_EVENT_FLAG_STS_INGRESS_FIELDS + }, + { /* register name AUTO_RECOVER_EVENT_FLAG_STS_EGRESS */ + /* offset address */ 0x4550, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ AUTO_RECOVER_EVENT_FLAG_STS_EGRESS_FIELDS + }, + { /* register name AUTO_RECOVER_EVENT_FLAG_STS_MAC */ + /* offset address */ 0x10BC, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ AUTO_RECOVER_EVENT_FLAG_STS_MAC_FIELDS + }, + { /* register name AUTO_RECOVER_EVENT_FLAG_ERR_INGRESS */ + /* offset address */ 0x75C4, + /* field numbers */ 4, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ AUTO_RECOVER_EVENT_FLAG_ERR_INGRESS_FIELDS + }, + { /* register name AUTO_RECOVER_EVENT_FLAG_ERR_EGRESS */ + /* offset address */ 0x4554, + /* field numbers */ 3, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ AUTO_RECOVER_EVENT_FLAG_ERR_EGRESS_FIELDS + }, + { /* register name AUTO_RECOVER_EVENT_FLAG_ERR_MAC */ + /* offset address */ 0x10C0, + /* field numbers */ 2, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ AUTO_RECOVER_EVENT_FLAG_ERR_MAC_FIELDS + }, + { /* register name FIFO_FLOW_FLAG_MSK */ + /* offset address */ 0x10C4, + /* field numbers */ 5, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ FIFO_FLOW_FLAG_MSK_FIELDS + }, + { /* register name CHIP_MISC_DUMY_0 */ + /* offset address */ 0x60, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ CHIP_MISC_DUMY_0_FIELDS + }, + { /* register name CHIP_MISC_DUMY_1 */ + /* offset address */ 0x64, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ CHIP_MISC_DUMY_1_FIELDS + }, + { /* register name TM0_CTRL_DUMY_0 */ + /* offset address */ 0x2F4, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ TM0_CTRL_DUMY_0_FIELDS + }, + { /* register name TM0_CTRL_DUMY_1 */ + /* offset address */ 0x2F8, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ TM0_CTRL_DUMY_1_FIELDS + }, + { /* register name TM1_CTRL_DUMY_0 */ + /* offset address */ 0x354, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ TM1_CTRL_DUMY_0_FIELDS + }, + { /* register name TM1_CTRL_DUMY_1 */ + /* offset address */ 0x358, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ TM1_CTRL_DUMY_1_FIELDS + }, + { /* register name VOLT_PROB_DUMY_0 */ + /* offset address */ 0x39C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ VOLT_PROB_DUMY_0_FIELDS + }, + { /* register name VOLT_PROB_DUMY_1 */ + /* offset address */ 0x3A0, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ VOLT_PROB_DUMY_1_FIELDS + }, + { /* register name REG_IF_DUMY_0 */ + /* offset address */ 0x44C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ REG_IF_DUMY_0_FIELDS + }, + { /* register name REG_IF_DUMY_1 */ + /* offset address */ 0x450, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ REG_IF_DUMY_1_FIELDS + }, + { /* register name MIB_0_DUMY_0 */ + /* offset address */ 0x6F4, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MIB_0_DUMY_0_FIELDS + }, + { /* register name MIB_0_DUMY_1 */ + /* offset address */ 0x6F8, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MIB_0_DUMY_1_FIELDS + }, + { /* register name MIB_1_DUMY_0 */ + /* offset address */ 0x720, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MIB_1_DUMY_0_FIELDS + }, + { /* register name MIB_1_DUMY_1 */ + /* offset address */ 0x724, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MIB_1_DUMY_1_FIELDS + }, + { /* register name MIB_2_DUMY_0 */ + /* offset address */ 0x740, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MIB_2_DUMY_0_FIELDS + }, + { /* register name MIB_2_DUMY_1 */ + /* offset address */ 0x744, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MIB_2_DUMY_1_FIELDS + }, + { /* register name MIB_3_DUMY_0 */ + /* offset address */ 0x760, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MIB_3_DUMY_0_FIELDS + }, + { /* register name MIB_3_DUMY_1 */ + /* offset address */ 0x764, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MIB_3_DUMY_1_FIELDS + }, + { /* register name MIB_4_DUMY_0 */ + /* offset address */ 0x780, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MIB_4_DUMY_0_FIELDS + }, + { /* register name MIB_4_DUMY_1 */ + /* offset address */ 0x784, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MIB_4_DUMY_1_FIELDS + }, + { /* register name MIB_5_DUMY_0 */ + /* offset address */ 0x7A0, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MIB_5_DUMY_0_FIELDS + }, + { /* register name MIB_5_DUMY_1 */ + /* offset address */ 0x7A4, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MIB_5_DUMY_1_FIELDS + }, + { /* register name MIB_6_DUMY_0 */ + /* offset address */ 0x7C0, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MIB_6_DUMY_0_FIELDS + }, + { /* register name MIB_6_DUMY_1 */ + /* offset address */ 0x7C4, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MIB_6_DUMY_1_FIELDS + }, + { /* register name MIB_7_DUMY_0 */ + /* offset address */ 0x7E0, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MIB_7_DUMY_0_FIELDS + }, + { /* register name MIB_7_DUMY_1 */ + /* offset address */ 0x7E4, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MIB_7_DUMY_1_FIELDS + }, + { /* register name MIB_8_DUMY_0 */ + /* offset address */ 0x800, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MIB_8_DUMY_0_FIELDS + }, + { /* register name MIB_8_DUMY_1 */ + /* offset address */ 0x804, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MIB_8_DUMY_1_FIELDS + }, + { /* register name MIB_9_DUMY_0 */ + /* offset address */ 0x820, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MIB_9_DUMY_0_FIELDS + }, + { /* register name MIB_9_DUMY_1 */ + /* offset address */ 0x824, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MIB_9_DUMY_1_FIELDS + }, + { /* register name MIB_10_DUMY_0 */ + /* offset address */ 0x840, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MIB_10_DUMY_0_FIELDS + }, + { /* register name MIB_10_DUMY_1 */ + /* offset address */ 0x844, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MIB_10_DUMY_1_FIELDS + }, + { /* register name MIB_11_DUMY_0 */ + /* offset address */ 0x860, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MIB_11_DUMY_0_FIELDS + }, + { /* register name MIB_11_DUMY_1 */ + /* offset address */ 0x864, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MIB_11_DUMY_1_FIELDS + }, + { /* register name MIB_12_DUMY_0 */ + /* offset address */ 0x880, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MIB_12_DUMY_0_FIELDS + }, + { /* register name MIB_12_DUMY_1 */ + /* offset address */ 0x884, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MIB_12_DUMY_1_FIELDS + }, + { /* register name MIB_13_DUMY_0 */ + /* offset address */ 0x8A0, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MIB_13_DUMY_0_FIELDS + }, + { /* register name MIB_13_DUMY_1 */ + /* offset address */ 0x8A4, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MIB_13_DUMY_1_FIELDS + }, + { /* register name MIB_14_DUMY_0 */ + /* offset address */ 0x8C0, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MIB_14_DUMY_0_FIELDS + }, + { /* register name MIB_14_DUMY_1 */ + /* offset address */ 0x8C4, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MIB_14_DUMY_1_FIELDS + }, + { /* register name MIB_15_DUMY_0 */ + /* offset address */ 0x8E0, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MIB_15_DUMY_0_FIELDS + }, + { /* register name MIB_15_DUMY_1 */ + /* offset address */ 0x8E4, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MIB_15_DUMY_1_FIELDS + }, + { /* register name MIB_16_DUMY_0 */ + /* offset address */ 0x900, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MIB_16_DUMY_0_FIELDS + }, + { /* register name MIB_16_DUMY_1 */ + /* offset address */ 0x904, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MIB_16_DUMY_1_FIELDS + }, + { /* register name PHY_INTF_DUMY_0 */ + /* offset address */ 0x970, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PHY_INTF_DUMY_0_FIELDS + }, + { /* register name PHY_INTF_DUMY_1 */ + /* offset address */ 0x974, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PHY_INTF_DUMY_1_FIELDS + }, + { /* register name PHY_INTF_DUMY_2 */ + /* offset address */ 0x978, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PHY_INTF_DUMY_2_FIELDS + }, + { /* register name PHY_INTF_DUMY_3 */ + /* offset address */ 0x97C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PHY_INTF_DUMY_3_FIELDS + }, + { /* register name PHY_PKG_DUMY_0 */ + /* offset address */ 0xA2C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PHY_PKG_DUMY_0_FIELDS + }, + { /* register name PHY_PKG_DUMY_1 */ + /* offset address */ 0xA30, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PHY_PKG_DUMY_1_FIELDS + }, + { /* register name PHY_MISC_DUMY_0 */ + /* offset address */ 0xBE0, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PHY_MISC_DUMY_0_FIELDS + }, + { /* register name PHY_MISC_DUMY_1 */ + /* offset address */ 0xBE4, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PHY_MISC_DUMY_1_FIELDS + }, + { /* register name RANDOM_SEED_DUMY_0 */ + /* offset address */ 0xEC0, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RANDOM_SEED_DUMY_0_FIELDS + }, + { /* register name RANDOM_SEED_DUMY_1 */ + /* offset address */ 0xEC4, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RANDOM_SEED_DUMY_1_FIELDS + }, + { /* register name RANDOM_SEED_DUMY_2 */ + /* offset address */ 0xEC8, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RANDOM_SEED_DUMY_2_FIELDS + }, + { /* register name RANDOM_SEED_DUMY_3 */ + /* offset address */ 0xECC, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RANDOM_SEED_DUMY_3_FIELDS + }, + { /* register name MIB_CTRL_DUMY_0 */ + /* offset address */ 0xF6C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MIB_CTRL_DUMY_0_FIELDS + }, + { /* register name MIB_CTRL_DUMY_1 */ + /* offset address */ 0xF70, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MIB_CTRL_DUMY_1_FIELDS + }, + { /* register name MAC_GLB_DUMY_0 */ + /* offset address */ 0x10C8, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MAC_GLB_DUMY_0_FIELDS + }, + { /* register name MAC_GLB_DUMY_1 */ + /* offset address */ 0x10CC, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MAC_GLB_DUMY_1_FIELDS + }, + { /* register name PER_PORT_MAC_DUMY_0 */ + /* offset address */ 0x1268, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ PER_PORT_MAC_DUMY_0_FIELDS + }, + { /* register name PER_PORT_MAC_DUMY_1 */ + /* offset address */ 0x126C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ PER_PORT_MAC_DUMY_1_FIELDS + }, + { /* register name PER_PORT_TXQ_REG_10P_DUMY_0 */ + /* offset address */ 0x1D48, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ PER_PORT_TXQ_REG_10P_DUMY_0_FIELDS + }, + { /* register name PER_PORT_TXQ_REG_10P_DUMY_1 */ + /* offset address */ 0x1D4C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 9, + /* register fields */ PER_PORT_TXQ_REG_10P_DUMY_1_FIELDS + }, + { /* register name EGRESS_CTRL_DUMY_0 */ + /* offset address */ 0x4558, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ EGRESS_CTRL_DUMY_0_FIELDS + }, + { /* register name EGRESS_CTRL_DUMY_1 */ + /* offset address */ 0x455C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ EGRESS_CTRL_DUMY_1_FIELDS + }, + { /* register name EGRESS_CTRL_DUMY_2 */ + /* offset address */ 0x4560, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ EGRESS_CTRL_DUMY_2_FIELDS + }, + { /* register name EGRESS_CTRL_DUMY_3 */ + /* offset address */ 0x4564, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ EGRESS_CTRL_DUMY_3_FIELDS + }, + { /* register name ACL_DUMY_0 */ + /* offset address */ 0x4BF0, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ ACL_DUMY_0_FIELDS + }, + { /* register name ACL_DUMY_1 */ + /* offset address */ 0x4BF4, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ ACL_DUMY_1_FIELDS + }, + { /* register name ACL_DUMY_2 */ + /* offset address */ 0x4BF8, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ ACL_DUMY_2_FIELDS + }, + { /* register name ACL_DUMY_3 */ + /* offset address */ 0x4BFC, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ ACL_DUMY_3_FIELDS + }, + { /* register name INBW_DUMY_0 */ + /* offset address */ 0x4CB4, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ INBW_DUMY_0_FIELDS + }, + { /* register name INBW_DUMY_1 */ + /* offset address */ 0x4CB8, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ INBW_DUMY_1_FIELDS + }, + { /* register name CVLAN_DUMY_0 */ + /* offset address */ 0x4E44, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ CVLAN_DUMY_0_FIELDS + }, + { /* register name CVLAN_DUMY_1 */ + /* offset address */ 0x4E48, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ CVLAN_DUMY_1_FIELDS + }, + { /* register name CVLAN_DUMY_2 */ + /* offset address */ 0x4E4C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ CVLAN_DUMY_2_FIELDS + }, + { /* register name CVLAN_DUMY_3 */ + /* offset address */ 0x4E50, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ CVLAN_DUMY_3_FIELDS + }, + { /* register name DPM_DUMY_0 */ + /* offset address */ 0x51E8, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ DPM_DUMY_0_FIELDS + }, + { /* register name DPM_DUMY_1 */ + /* offset address */ 0x51EC, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ DPM_DUMY_1_FIELDS + }, + { /* register name IGMP_DUMY_0 */ + /* offset address */ 0x52F4, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ IGMP_DUMY_0_FIELDS + }, + { /* register name IGMP_DUMY_1 */ + /* offset address */ 0x52F8, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ IGMP_DUMY_1_FIELDS + }, + { /* register name L2_DUMY_0 */ + /* offset address */ 0x558C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ L2_DUMY_0_FIELDS + }, + { /* register name L2_DUMY_1 */ + /* offset address */ 0x5590, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ L2_DUMY_1_FIELDS + }, + { /* register name SVLAN_DUMY_0 */ + /* offset address */ 0x5BE8, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SVLAN_DUMY_0_FIELDS + }, + { /* register name SVLAN_DUMY_1 */ + /* offset address */ 0x5BEC, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SVLAN_DUMY_1_FIELDS + }, + { /* register name SVLAN_DUMY_2 */ + /* offset address */ 0x5BF0, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SVLAN_DUMY_2_FIELDS + }, + { /* register name SVLAN_DUMY_3 */ + /* offset address */ 0x5BF4, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SVLAN_DUMY_3_FIELDS + }, + { /* register name TABLE_DUMY_0 */ + /* offset address */ 0x5CE0, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ TABLE_DUMY_0_FIELDS + }, + { /* register name TABLE_DUMY_1 */ + /* offset address */ 0x5CE4, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ TABLE_DUMY_1_FIELDS + }, + { /* register name MTRPOOL_DUMY_0 */ + /* offset address */ 0x5F18, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MTRPOOL_DUMY_0_FIELDS + }, + { /* register name MTRPOOL_DUMY_1 */ + /* offset address */ 0x5F1C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ MTRPOOL_DUMY_1_FIELDS + }, + { /* register name GLB_CTRL_DUMY_0 */ + /* offset address */ 0x6058, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ GLB_CTRL_DUMY_0_FIELDS + }, + { /* register name GLB_CTRL_DUMY_1 */ + /* offset address */ 0x605C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ GLB_CTRL_DUMY_1_FIELDS + }, + { /* register name GLB_CTRL_DUMY_2 */ + /* offset address */ 0x6060, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ GLB_CTRL_DUMY_2_FIELDS + }, + { /* register name GLB_CTRL_DUMY_3 */ + /* offset address */ 0x6064, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ GLB_CTRL_DUMY_3_FIELDS + }, + { /* register name SMI_CTRL_DUMY_0 */ + /* offset address */ 0x649C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SMI_CTRL_DUMY_0_FIELDS + }, + { /* register name SMI_CTRL_DUMY_1 */ + /* offset address */ 0x64A0, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SMI_CTRL_DUMY_1_FIELDS + }, + { /* register name LED_DUMY_0 */ + /* offset address */ 0x6604, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ LED_DUMY_0_FIELDS + }, + { /* register name LED_DUMY_1 */ + /* offset address */ 0x6608, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ LED_DUMY_1_FIELDS + }, + { /* register name PKT_ENCAP_DUMY_0 */ + /* offset address */ 0x67BC, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PKT_ENCAP_DUMY_0_FIELDS + }, + { /* register name PKT_ENCAP_DUMY_1 */ + /* offset address */ 0x67C0, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PKT_ENCAP_DUMY_1_FIELDS + }, + { /* register name PKT_ENCAP_DUMY_2 */ + /* offset address */ 0x67C4, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PKT_ENCAP_DUMY_2_FIELDS + }, + { /* register name PKT_ENCAP_DUMY_3 */ + /* offset address */ 0x67C8, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PKT_ENCAP_DUMY_3_FIELDS + }, + { /* register name PKT_PARSER_DUMY_0 */ + /* offset address */ 0x6FF0, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PKT_PARSER_DUMY_0_FIELDS + }, + { /* register name PKT_PARSER_DUMY_1 */ + /* offset address */ 0x6FF4, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ PKT_PARSER_DUMY_1_FIELDS + }, + { /* register name INGRESS_CTRL_DUMY_0 */ + /* offset address */ 0x7494, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ INGRESS_CTRL_DUMY_0_FIELDS + }, + { /* register name INGRESS_CTRL_DUMY_1 */ + /* offset address */ 0x7498, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ INGRESS_CTRL_DUMY_1_FIELDS + }, + { /* register name INGRESS_CTRL_DUMY_2 */ + /* offset address */ 0x749C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ INGRESS_CTRL_DUMY_2_FIELDS + }, + { /* register name INGRESS_CTRL_DUMY_3 */ + /* offset address */ 0x74A0, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ INGRESS_CTRL_DUMY_3_FIELDS + }, + { /* register name INGRESS_CTRL_2_DUMY_0 */ + /* offset address */ 0x75C8, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ INGRESS_CTRL_2_DUMY_0_FIELDS + }, + { /* register name INGRESS_CTRL_2_DUMY_1 */ + /* offset address */ 0x75CC, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ INGRESS_CTRL_2_DUMY_1_FIELDS + }, + { /* register name INGRESS_CTRL_2_DUMY_2 */ + /* offset address */ 0x75D0, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ INGRESS_CTRL_2_DUMY_2_FIELDS + }, + { /* register name INGRESS_CTRL_2_DUMY_3 */ + /* offset address */ 0x75D4, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ INGRESS_CTRL_2_DUMY_3_FIELDS + }, + { /* register name NIC_DUMY_0 */ + /* offset address */ 0x789C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ NIC_DUMY_0_FIELDS + }, + { /* register name NIC_DUMY_1 */ + /* offset address */ 0x78A0, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ NIC_DUMY_1_FIELDS + }, + { /* register name CHIP_BIST_DUMY_0 */ + /* offset address */ 0x7A30, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ CHIP_BIST_DUMY_0_FIELDS + }, + { /* register name CHIP_BIST_DUMY_1 */ + /* offset address */ 0x7A34, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ CHIP_BIST_DUMY_1_FIELDS + }, + { /* register name SDS_DUMY_0 */ + /* offset address */ 0x7B70, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SDS_DUMY_0_FIELDS + }, + { /* register name SDS_DUMY_1 */ + /* offset address */ 0x7B74, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ SDS_DUMY_1_FIELDS + }, + { /* register name IO_DUMY_0 */ + /* offset address */ 0x7FB8, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ IO_DUMY_0_FIELDS + }, + { /* register name IO_DUMY_1 */ + /* offset address */ 0x7FBC, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ IO_DUMY_1_FIELDS + }, + { /* register name EFUSE_CTRL_DUMY_0 */ + /* offset address */ 0x8094, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ EFUSE_CTRL_DUMY_0_FIELDS + }, + { /* register name EFUSE_CTRL_DUMY_1 */ + /* offset address */ 0x8098, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ EFUSE_CTRL_DUMY_1_FIELDS + }, + { /* register name DBG_CTRL_DUMY_0 */ + /* offset address */ 0xC0D4, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ DBG_CTRL_DUMY_0_FIELDS + }, + { /* register name DBG_CTRL_DUMY_1 */ + /* offset address */ 0xC0D8, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ DBG_CTRL_DUMY_1_FIELDS + }, + { /* register name RATE_ADAPTER0_DUMY_0 */ + /* offset address */ 0xE148, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RATE_ADAPTER0_DUMY_0_FIELDS + }, + { /* register name RATE_ADAPTER0_DUMY_1 */ + /* offset address */ 0xE14C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RATE_ADAPTER0_DUMY_1_FIELDS + }, + { /* register name RATE_ADAPTER1_DUMY_0 */ + /* offset address */ 0xE348, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RATE_ADAPTER1_DUMY_0_FIELDS + }, + { /* register name RATE_ADAPTER1_DUMY_1 */ + /* offset address */ 0xE34C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RATE_ADAPTER1_DUMY_1_FIELDS + }, + { /* register name RATE_ADAPTER2_DUMY_0 */ + /* offset address */ 0xE548, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RATE_ADAPTER2_DUMY_0_FIELDS + }, + { /* register name RATE_ADAPTER2_DUMY_1 */ + /* offset address */ 0xE54C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RATE_ADAPTER2_DUMY_1_FIELDS + }, + { /* register name RATE_ADAPTER3_DUMY_0 */ + /* offset address */ 0xE748, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RATE_ADAPTER3_DUMY_0_FIELDS + }, + { /* register name RATE_ADAPTER3_DUMY_1 */ + /* offset address */ 0xE74C, + /* field numbers */ 1, + /* array offset */ 32, + /* array index */ 0, 0, + /* port index */ 0, 0, + /* register fields */ RATE_ADAPTER3_DUMY_1_FIELDS + }, +}; + diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/rtl8373_reg_struct.h b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/rtl8373_reg_struct.h new file mode 100755 index 00000000..7efd867e --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/rtl8373_reg_struct.h @@ -0,0 +1,5483 @@ +/* + * ## Please DO NOT edit this file!! ## + * This file is auto-generated from the register source files. + * Any modifications to this file will be LOST when it is re-generated. + * + * ---------------------------------------------------------------- + * (C) Copyright 2009-2016 Realtek Semiconductor Corp. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * ---------------------------------------------------------------- + * Purpose: chip register definition and structure of RTL8373 + * + * ---------------------------------------------------------------- + */ + +#ifndef __RTL8373_REG_STRUCT_H__ +#define __RTL8373_REG_STRUCT_H__ + +typedef enum rtk_reg_list_e +{ + + /* Chip Information */ + MODEL_NAME_INFOr = 0, + CHIP_MODE_INFOr, + CHIP_INFOr, + CHIP_UUID_REGr, + CHIP_LOT_NO_REG0r, + CHIP_LOT_NO_REG1r, + SMI_MMD_SPr, + CFG_DMY_CHIP_INFO_1r, + + /* Reset */ + RST_GLB_CTRL_0r, + RST_GLB_DBG_0r, + RST_GLB_DBG_1r = 10, + + /* BIST & BISR */ + MAC_BIST_MODEr, + MAC_DRF_BIST_MODEr, + MAC_BIST_RSTNr, + MAC_BIST_LOOP_MODEr, + MAC_BIST_DYN_READ_ENr, + MAC_DRF_TEST_RESUMEr, + MAC_DRF_START_PAUSEr, + MAC_MBIST_DONEr, + MAC_MBIST_DRF_DONEr, + MAC_MBIST_FAIL_PG00_PG01r = 20, + MAC_MBIST_FAIL_PG02_PG03r, + MAC_MBIST_DRF_FAIL_PG00_PG01r, + MAC_MBIST_DRF_FAIL_PG02_PG03r, + MAC_RXFIFO_LSr, + MAC_RXFIFO_RMEAr, + MAC_RXFIFO_RMA_PG00r, + MAC_RXFIFO_RMA_PG01r, + MAC_RXFIFO_RMA_PG02r, + MAC_RXFIFO_RMA_PG03r, + MAC_RXFIFO_RMEBr = 30, + MAC_RXFIFO_RMB_PG00r, + MAC_RXFIFO_RMB_PG01r, + MAC_RXFIFO_RMB_PG02r, + MAC_RXFIFO_RMB_PG03r, + MAC_TXFIFO_LSr, + MAC_TXFIFO_RMEAr, + MAC_TXFIFO_RMA_PG00r, + MAC_TXFIFO_RMA_PG01r, + MAC_TXFIFO_RMA_PG02r, + MAC_TXFIFO_RMA_PG03r = 40, + MAC_TXFIFO_RMEBr, + MAC_TXFIFO_RMB_PG00r, + MAC_TXFIFO_RMB_PG01r, + MAC_TXFIFO_RMB_PG02r, + MAC_TXFIFO_RMB_PG03r, + CHIP_ALL_RESULTr, + CHIP_BISR_CTRLr, + GLB_MBISD_DATAr, + GLB_MBISD_CFGr, + INGR_BIST_CTRL0r = 50, + INGR_BIST_CTRL1r, + INGR_BIST_CTRL2r, + INGR_BIST_CTRL3r, + INGR_BIST_CTRL4r, + INGR_BIST_CTRL5r, + INGR_BIST_CTRL6r, + INGR_BIST_RSLT0r, + INGR_BIST_RSLT1r, + INGR_BIST_RSLT2r, + INGR_BIST_RSLT3r = 60, + INGR_BIST_RSLT4r, + INGR_SRAM_CTRL_0r, + INGR_SRAM_CTRL_1r, + INGR_BISR_CTRLr, + INGR_BISR_RSLT0r, + INGR_BISR_RSLT1r, + INGR_BISR_RSLT2r, + INGR_BISR_RSLT3r, + EGR_BIST_CTRL0r, + EGR_BIST_CTRL1r = 70, + EGR_BIST_CTRL2r, + EGR_SRAM_CTRL3r, + EGR_BIST_CTRL4r, + EGR_BIST_CTRL5r, + EGR_BIST_RSLT0r, + EGR_BIST_RSLT1r, + EGR_BIST_RSLT2r, + NIC_BIST_CTRL0r, + NIC_BIST_CTRL1r, + NIC_BIST_CTRL2r = 80, + NIC_BIST_CTRL3r, + NIC_BIST_CTRL4r, + NIC_BIST_CTRL5r, + NIC_BIST_RSLT0r, + NIC_BIST_RSLT1r, + NIC_BIST_RSLT2r, + SPI_BIST_CTRLr, + SPI_BIST_RSLTr, + ALE_MEM_CFG_0r, + ALE_MEM_CFG_1r = 90, + ALE_CAM_CFGr, + ALE_BIST_LOOP_ENr, + ALE_BIST_DYN_READ_ENr, + ALE_BIST_GRP_ENr, + ALE_BIST_RSTNr, + ALE_BIST_MODEr, + ALE_BIST_DONEr, + ALE_BIST_FAILr, + ALE_DRF_MODEr, + ALE_DRF_PAUSEr = 100, + ALE_DRF_RESUMEr, + ALE_DRF_DONEr, + ALE_DRF_FAILr, + PAR_MEM_CFG_0r, + PAR_MEM_CFG_1r, + PAR_MEM_CFG_2r, + PAR_MEM_CFG_3r, + PAR_BIST_RESET_RESUMEr, + PAR_BIST_MODE_DRFMODEr, + PAR_BIST_VDDR_LOOPr = 110, + PAR_BIST_START_PAUSEr, + PAR_BIST_DONE_DRFDONEr, + PAR_BIST_FAIL_DRFFAILr, + PAR_BIST_CTRL_0r, + MBIST_CTRLr, + MBIST_RSLTr, + + /* HW_MISC */ + BOND_INFOr, + STRAP_INFO_0r, + IO_DRVING_0r, + IO_DRVING_1r = 120, + IO_DRVING_2r, + IO_SLEW_0r, + IO_SLEW_1r, + IO_SLEW_2r, + IO_SMT_EN_0r, + IO_SMT_EN_1r, + IO_SMT_EN_2r, + IO_MUX_SEL_0r, + IO_MUX_SEL_1r, + IO_MUX_SEL_2r = 130, + IO_MUX_SEL_3r, + DBG_MODEr, + DBG_PAD_CTRLr, + DBG_CTRL_ADR0r, + DBG_CTRL_ADR1r, + DBG_CTRL_ADR2r, + DBG_CTRL_ADR3r, + DBG_CTRL_SEL0r, + DBG_CTRL_SEL1r, + DBG_CTRL_SEL2r = 140, + DBG_CTRL_SEL3r, + DBG_CTRL_VALr, + FORCE_PU_PD_EN_0r, + FORCE_PU_PD_EN_1r, + FORCE_PU_0r, + FORCE_PU_1r, + FORCE_PD_0r, + FORCE_PD_1r, + CFG_PAD_MDIO0_DRV_MODEr, + VOLT_PROB_CTRLr = 150, + VOLT_PROB_RESULT0r, + VOLT_PROB_RESULT1r, + CFG_XTALr, + + /* Wrapper_PHY */ + CFG_EEE_FLG_DLYr, + CFG_PHY_MDI_REVERSEr, + CFG_PHY_TX_POLARITY_SWAPr, + CFG_PHY_OCP_TIMEOUTr, + CFG_PHY_PCSXF_1r, + CFG_PHY_PCSXF_2r, + CFG_PHY_G2XG_IPGr = 160, + CFG_PHY_G2XG_FIFO_THRr, + CFG_PHY_G2XG_AUTORSTr, + CFG_PHY_G2XG_MISCr, + CFG_PHY_G2XG_MODULE_RSTr, + P0_PHY_G2XG_BCH_ERR_FLAGr, + P1_PHY_G2XG_BCH_ERR_FLAGr, + P2_PHY_G2XG_BCH_ERR_FLAGr, + P3_PHY_G2XG_BCH_ERR_FLAGr, + CFG_PHY_MISCr, + PHY_LINK_FAULT_STSr = 170, + CFG_PHY_BRDr, + CFG_PHY_INIr, + CFG_PHY_POLL_CMD1r, + CFG_PHY_POLL_CMD2r, + CFG_PHY_HOTCMD1_ADRr, + CFG_PHY_HOTCMD1_DATr, + P0_XG2XG_IPG_DBG_INFOr, + P0_XG2XG_PRMB_DBG_INFOr, + P0_XG2XG_THR_DBG_INFOr, + CFG_PHY_POLL_ADR0r = 180, + CFG_PHY_POLL_ADR1r, + CFG_PHY_POLL_ADR2r, + CFG_PHY_POLL_ADR3r, + CFG_PHY_POLL_INV0r, + CFG_PHY_POLL_INV1r, + CFG_PHY_POLL_INV2r, + CFG_PHY_POLL_INV3r, + CFG_PHY_POLL_WD0r, + CFG_PHY_POLL_WD1r, + CFG_PHY_POLL_WD2r = 190, + CFG_PHY_POLL_WD3r, + PHY_SDET_STATUSr, + P0_PHY_POLL_CMD0_RDATr, + P0_PHY_POLL_CMD1_RDATr, + P0_PHY_POLL_CMD2_RDATr, + P0_PHY_POLL_CMD3_RDATr, + P1_PHY_POLL_CMD0_RDATr, + P1_PHY_POLL_CMD1_RDATr, + P1_PHY_POLL_CMD2_RDATr, + P1_PHY_POLL_CMD3_RDATr = 200, + P2_PHY_POLL_CMD0_RDATr, + P2_PHY_POLL_CMD1_RDATr, + P2_PHY_POLL_CMD2_RDATr, + P2_PHY_POLL_CMD3_RDATr, + P3_PHY_POLL_CMD0_RDATr, + P3_PHY_POLL_CMD1_RDATr, + P3_PHY_POLL_CMD2_RDATr, + P3_PHY_POLL_CMD3_RDATr, + PHY_ABLTY_RESOLUTION_FRC_MODEr, + P0_PHY_ABLTY_RESOLUTION_FORCEr = 210, + P1_PHY_ABLTY_RESOLUTION_FORCEr, + P2_PHY_ABLTY_RESOLUTION_FORCEr, + P3_PHY_ABLTY_RESOLUTION_FORCEr, + POWCTRL_ADRr, + POWCTRL1_BITr, + POWCTRL0_BITr, + RS_LAYER_CONFIGr, + PHY0_RD_PCS_ABILITYr, + PHY1_RD_PCS_ABILITYr, + PHY2_RD_PCS_ABILITYr = 220, + PHY3_RD_PCS_ABILITYr, + CFG_PHY_XG2G_G_MISCr, + P1_XG2XG_IPG_DBG_INFOr, + P1_XG2XG_PRMB_DBG_INFOr, + P1_XG2XG_THR_DBG_INFOr, + RANDOM_UPD_PERIODr, + RANDOM_UPD_CTRLr, + RG_RDM_SEED_SRC_ADDRr, + RING_RATE_REGADDRr, + RING_RATE_SEL_MASK_Lr = 230, + RING_RATE_SEL_MASK_Hr, + RING_RATE_FRC_VALUE_Hr, + RING_RATE_FRC_VALUE_Lr, + LFSR_INIT_SEED_FRC_VALUEr, + RING_RATE_RD_VALUE_Hr, + RING_RATE_RD_VALUE_Lr, + LFSR_INIT_SEED_RD_VALUEr, + P0_G2XG_CFG_CLR_ERR_FLAGr, + P1_G2XG_CFG_CLR_ERR_FLAGr, + P2_G2XG_CFG_CLR_ERR_FLAGr = 240, + P3_G2XG_CFG_CLR_ERR_FLAGr, + G2XG_FIFO_CLR_CFGr, + P2_XG2XG_IPG_DBG_INFOr, + P2_XG2XG_PRMB_DBG_INFOr, + P2_XG2XG_THR_DBG_INFOr, + G2G_WATER_LEVELr, + G2G_MISC_CFGr, + G2G_ERR_CNT_01r, + G2G_ERR_CNT_23r, + XG2XG_WATER_LEVELr = 250, + XG2XG_MISC_CFGr, + XG2XG_ERR_STATUSr, + EEE_LPI_DLY_CYCLEr, + PREAMBLE_RECOVERY_CRTLr, + G2G_FIFO_CLR_CFGr, + XG2XG_FIFO_CLR_CFGr, + P3_XG2XG_IPG_DBG_INFOr, + P3_XG2XG_PRMB_DBG_INFOr, + P3_XG2XG_THR_DBG_INFOr, + SYNCE_CTRL_0r = 260, + SYNCE_CTRL_1r, + SYNCE_DUMMY1r, + SYNCE_DUMMY2r, + SYNCE_DUMMY3r, + SYNCE_DUMMY4r, + SYNCE_DUMMY5r, + PKTGEN_GLOBAL_CTRLr, + PKTGEN_PAYLOAD_IND_ACCESS_CTRLr, + PKTGEN_G2XG_FIFO_CTRLr, + PKTGEN0_CTRL0r = 270, + PKTGEN0_CTRL1r, + PKTGEN0_CTRL2r, + PKTGEN0_CTRL3r, + PKTGEN0_CTRL4r, + PKTGEN0_CTRL5r, + PKTGEN0_CTRL6r, + PKTGEN0_CTRL7r, + PKTGEN1_CTRL0r, + PKTGEN1_CTRL1r, + PKTGEN1_CTRL2r = 280, + PKTGEN1_CTRL3r, + PKTGEN1_CTRL4r, + PKTGEN1_CTRL5r, + PKTGEN1_CTRL6r, + PKTGEN1_CTRL7r, + PKTGEN2_CTRL0r, + PKTGEN2_CTRL1r, + PKTGEN2_CTRL2r, + PKTGEN2_CTRL3r, + PKTGEN2_CTRL4r = 290, + PKTGEN2_CTRL5r, + PKTGEN2_CTRL6r, + PKTGEN2_CTRL7r, + PKTGEN3_CTRL0r, + PKTGEN3_CTRL1r, + PKTGEN3_CTRL2r, + PKTGEN3_CTRL3r, + PKTGEN3_CTRL4r, + PKTGEN3_CTRL5r, + PKTGEN3_CTRL6r = 300, + PKTGEN3_CTRL7r, + PKTGEN0_CTRL15r, + PKTGEN1_CTRL15r, + PKTGEN2_CTRL15r, + PKTGEN3_CTRL15r, + PHY_MODEL_ID_REV_CTRLr, + + /* SDS */ + SDS_MODE_SELr, + SDS_INDACS_CMDr, + SDS_INDACS_RDr, + SDS_INDACS_WDr = 310, + SDS0_STATUSr, + SDS0_CH0_RO_ABLTYr, + SDS0_CH1_RO_ABLTYr, + SDS0_CH2_RO_ABLTYr, + SDS0_CH3_3_RO_ABLTYr, + SDS1_CH0_RO_ABLTYr, + SDS0_1_MODE_ROr, + CFG_DMY_SDS_0r, + CFG_DMY_SDS_1r, + SDS_OUIr = 320, + SDS_VERSIONr, + SDS_OUI_TGRr, + SDS_VERSION_TGRr, + SDS_INTF_CTRL1r, + SDS_INTF_CTRL2r, + SDS_INTF_OUT1r, + + /* LED */ + LED_GLB_CTRLr, + LED3_0_SET3_2_CTRL1r, + LED3_0_SET1_0_CTRL1r, + LED3_2_SET3_CTRL0r = 330, + LED1_0_SET3_CTRL0r, + LED3_2_SET2_CTRL0r, + LED1_0_SET2_CTRL0r, + LED3_2_SET1_CTRL0r, + LED1_0_SET1_CTRL0r, + LED3_2_SET0_CTRL0r, + LED1_0_SET0_CTRL0r, + LED_PORT_SET_SEL_CTRLr, + SW_LED_LOADr, + LED_PORT_SW_EN_CTRLr = 340, + LED_PORT_SW_CTRLr, + LED_LOAD_LV1_10Gr, + LED_LOAD_LV2_10Gr, + LED_LOAD_LV3_10Gr, + LED_LOAD_LV1_5Gr, + LED_LOAD_LV2_5Gr, + LED_LOAD_LV3_5Gr, + LED_LOAD_LV1_2P5Gr, + LED_LOAD_LV2_2P5Gr, + LED_LOAD_LV3_2P5Gr = 350, + LED_LOAD_LV1_1Gr, + LED_LOAD_LV2_1Gr, + LED_LOAD_LV3_1Gr, + LED_LOAD_LV1_500Mr, + LED_LOAD_LV2_500Mr, + LED_LOAD_LV3_500Mr, + LED_LOAD_LV1_100Mr, + LED_LOAD_LV2_100Mr, + LED_LOAD_LV3_100Mr, + LED_LOAD_LV1_10Mr = 360, + LED_LOAD_LV2_10Mr, + LED_LOAD_LV3_10Mr, + LED_P_LOAD_CTRLr, + LED_GLB_ACTIVEr, + LED_GLB_IO_ENr, + LED_GLB_MUX_1r, + LED_GLB_MUX_2r, + LED_GLB_MUX_3r, + LED_GLB_MUX_4r, + LED_GLB_MUX_5r = 370, + LED_GLB_MUX_6r, + LED_RLDP_CTRL_1r, + LED_RLDP_CTRL_2r, + LED_RLDP_CTRL_3r, + + /* Smart Packet Generator */ + SPG_GLB_CTRLr, + PKB_ACC_DEBUG_CTRLr, + SPG_PORT_TX_GRP_CTRLr, + SPG_GLOBAL_STSr, + SPG_PORT_IBG_CTRL0r, + SPG_PORT_IBG_CTRL1r = 380, + SPG_PORT_IPG_CTRLr, + SPG_PORT_PKT_CNT_Hr, + SPG_PORT_PKT_CNT_Lr, + SPG_PORT_PKT_CNT_DBG_Hr, + SPG_PORT_PKT_CNT_DBG_Lr, + SPG_PORT_STREAM0_CTRL0r, + SPG_PORT_STREAM0_CTRL1r, + SPG_PORT_STREAM0_CTRL2r, + SPG_PORT_STREAM0_CTRL3r, + SPG_PB_ACCESS_CTRL0r = 390, + SPG_PB_ACCESS_CTRL1r, + SPG_PB_ACCESS_CTRL2r, + SPG_PORT_INDEX_CTRL0r, + SPG_GLOBAL_INDEX_CTRL0r, + SPG_PREAMBLE_LENGTH_CTRLr, + SPG_PREAMBLE_CONTENT_CTRL2r, + SPG_PREAMBLE_CONTENT_CTRL1r, + SPG_PREAMBLE_CONTENT_CTRL0r, + + /* Interface */ + I2C_SLV_CTRLr, + MAC_SLV_TIMEOUTr = 400, + MAC_IF_CTRLr, + SLV_MDX_CTRLr, + I2C_MST_IF_CTRLr, + I2C_MST1_CTRL1r, + I2C_MST1_CTRL2r, + I2C_MST1_MEMADDR_CTRLr, + I2C_MST1_DATA_CTRLr, + SPI_CTRL0r, + SPI_CTRL1r, + SPI_DATAr = 410, + SPI_ADDRr, + GPIO_OUT0r, + GPIO_OUT1r, + GPIO_IN0r, + GPIO_IN1r, + GPIO_OE0r, + GPIO_OE1r, + GPIO_IMODE_54_52r, + INI_MODEr, + PWM_CTRLr = 420, + REGIF_TIMEOUT_INFOr, + + /* TM */ + TM0_CTRL0r, + TM0_CTRL1r, + TM0_CTRL2r, + TM0_CTRL3r, + TM0_RESULT0r, + TM0_RESULT1r, + TM0_RESULT2r, + TM0_RESULT3r, + TM0_RESULT4r = 430, + TM1_CTRL0r, + TM1_CTRL1r, + TM1_CTRL2r, + TM1_CTRL3r, + TM1_RESULT0r, + TM1_RESULT1r, + TM1_RESULT2r, + TM1_RESULT3r, + TM1_RESULT4r, + + /* EFUSE&EEPROM */ + EFUSE_ACCESS_ENr = 440, + EFUSE_AUTOLOAD_CTRLr, + EFUSE_ACCESS_CTRLr, + EFUSE_WDATA_CTRLr, + EFUSE_RDATA_CTRLr, + EFUSE_CP_MISCr, + EFUSE_MARGIN_RD_CFGr, + EFUSE_MARGIN_RD_ERR_1r, + EFUSE_MARGIN_RD_ERR_2r, + EFUSE_FREQ_SELr, + EFUSE_MASS_OPERATION_CFGr = 450, + EFUSE_MASS_COMP_ERR_1r, + EFUSE_MASS_COMP_ERR_2r, + EFUSE_MASS_DATA_REGr, + MAC_EEPROM_DOWN_LOAD_FREQr, + MAC_EEPROM_DOWN_LOAD_STSr, + EEPROM_VER_INFOr, + EEPROM_AUTOLOAD_TIMERr, + MAC_EEPROM_ADDR_LENr, + + /* Interrupt */ + IMR_INT_PORT_LINK_STS_CHGr, + IMR_INT_GPHYr = 460, + IMR_INT_LEARNOVERr, + IMR_INT_RLFDr, + IMR_INT_WOLr, + IMR_INT_SERDES_LINK_FAULT_Pr, + IMR_INT_SDS_UPD_PHYSTS0r, + IMR_INT_GPIOr, + IMR_INT_MISCr, + IMR_EXT_PORT_LINK_STS_CHGr, + IMR_EXT_GPHYr, + IMR_EXT_LEARNOVERr = 470, + IMR_EXT_RLFDr, + IMR_EXT_WOLr, + IMR_EXT_SERDES_LINK_FAULT_Pr, + IMR_EXT_SDS_UPD_PHYSTS0r, + IMR_EXT_GPIOr, + IMR_EXT_MISCr, + ISR_INT_GLBr, + ISR_EXT_GLBr, + ISR_SW_INT_MODEr, + ISR_INT_PORT_LINK_STS_CHGr = 480, + ISR_INT_GPHYr, + ISR_INT_LEARNOVERr, + ISR_INT_TM_RLFDr, + ISR_INT_WOLr, + ISR_INT_SERDES_LINK_FAULT_Pr, + ISR_INT_SDS_UPD_PHYSTS0r, + ISR_INT_GPIOr, + ISR_INT_MISCr, + ISR_EXT_PORT_LINK_STS_CHGr, + ISR_EXT_GPHYr = 490, + ISR_EXT_LEARNOVERr, + ISR_EXT_TM_RLFDr, + ISR_EXT_WOLr, + ISR_EXT_SERDES_LINK_FAULT_Pr, + ISR_EXT_SDS_UPD_PHYSTS0r, + ISR_EXT_GPIOr, + ISR_EXT_MISCr, + + /* MIB Control */ + STAT_RSTr, + STAT_PORT_RSTr, + STAT_CTRLr = 500, + STAT_CNT_SET1_CTRLr, + STAT_CNT_SET0_CTRLr, + PHY_MIB_GLOBAL_CONFIGr, + DEBUG_MIB_RSTr, + INDIRECT_ACCESS_CTRLr, + INDIRECT_ACCESS_CNT_Lr, + INDIRECT_ACCESS_CNT_Hr, + + /* MIB Counter */ + PHY0_RX_MIB_CNTR0r, + PHY0_RX_MIB_CNTR1r, + PHY0_RX_MIB_CNTR2r = 510, + PHY0_RX_MIB_CNTR3r, + PHY0_TX_MIB_CNTR0r, + PHY0_TX_MIB_CNTR1r, + PHY0_TX_MIB_CNTR2r, + PHY0_TX_MIB_CNTR3r, + PHY1_RX_MIB_CNTR0r, + PHY1_RX_MIB_CNTR1r, + PHY1_RX_MIB_CNTR2r, + PHY1_RX_MIB_CNTR3r, + PHY1_TX_MIB_CNTR0r = 520, + PHY1_TX_MIB_CNTR1r, + PHY1_TX_MIB_CNTR2r, + PHY1_TX_MIB_CNTR3r, + PHY2_RX_MIB_CNTR0r, + PHY2_RX_MIB_CNTR1r, + PHY2_RX_MIB_CNTR2r, + PHY2_RX_MIB_CNTR3r, + PHY2_TX_MIB_CNTR0r, + PHY2_TX_MIB_CNTR1r, + PHY2_TX_MIB_CNTR2r = 530, + PHY2_TX_MIB_CNTR3r, + PHY3_RX_MIB_CNTR0r, + PHY3_RX_MIB_CNTR1r, + PHY3_RX_MIB_CNTR2r, + PHY3_RX_MIB_CNTR3r, + PHY3_TX_MIB_CNTR0r, + PHY3_TX_MIB_CNTR1r, + PHY3_TX_MIB_CNTR2r, + PHY3_TX_MIB_CNTR3r, + SDS_CH0_RX_MIB_CNTR0r = 540, + SDS_CH0_RX_MIB_CNTR1r, + SDS_CH0_RX_MIB_CNTR2r, + SDS_CH0_RX_MIB_CNTR3r, + SDS_CH0_TX_MIB_CNTR0r, + SDS_CH0_TX_MIB_CNTR1r, + SDS_CH0_TX_MIB_CNTR2r, + SDS_CH0_TX_MIB_CNTR3r, + SDS_CH1_RX_MIB_CNTR0r, + SDS_CH1_RX_MIB_CNTR1r, + SDS_CH1_RX_MIB_CNTR2r = 550, + SDS_CH1_RX_MIB_CNTR3r, + SDS_CH1_TX_MIB_CNTR0r, + SDS_CH1_TX_MIB_CNTR1r, + SDS_CH1_TX_MIB_CNTR2r, + SDS_CH1_TX_MIB_CNTR3r, + SDS_CH2_RX_MIB_CNTR0r, + SDS_CH2_RX_MIB_CNTR1r, + SDS_CH2_RX_MIB_CNTR2r, + SDS_CH2_RX_MIB_CNTR3r, + SDS_CH2_TX_MIB_CNTR0r = 560, + SDS_CH2_TX_MIB_CNTR1r, + SDS_CH2_TX_MIB_CNTR2r, + SDS_CH2_TX_MIB_CNTR3r, + SDS_CH3_RX_MIB_CNTR0r, + SDS_CH3_RX_MIB_CNTR1r, + SDS_CH3_RX_MIB_CNTR2r, + SDS_CH3_RX_MIB_CNTR3r, + SDS_CH3_TX_MIB_CNTR0r, + SDS_CH3_TX_MIB_CNTR1r, + SDS_CH3_TX_MIB_CNTR2r = 570, + SDS_CH3_TX_MIB_CNTR3r, + DMY_REG0_MIB_DATAr, + DMY_REG1_MIB_DATAr, + DMY_REG2_MIB_DATAr, + DMY_REG3_MIB_DATAr, + + /* MAC Control */ + MAC_L2_PORT_TX_MAX_LEN_CTRLr, + SMI_BYPASS_ABLTY_LOCK_CTRLr, + LINK_DOWN_CTRLr, + MAC_GLB_CTRLr, + MAC_PORT_CTRLr = 580, + HALF_CHG_CTRLr, + SMI_GLB_CTRL2r, + SMI_GLB_CTRLr, + SMI_MAC_TYPE_CTRLr, + SMI_PORT_POLLING_SELr, + SMI_MDIO_FREE_CNT_CTRLr, + SMI_PRVTE_POLLING_CTRLr, + SMI_10GPHY_POLLING_SEL_0r, + MAC_FORCE_MODE_CTRL0r, + MAC_FORCE_MODE_CTRL1r = 590, + SMI_REG_CHK1_CTRL1r, + SMI_REG_CHK1_PMSKr, + SMI_REG_CHK1_DATA_10Gr, + SMI_REG_CHK1_RESULTr, + SMI_REG_CHK2_CTRL1r, + SMI_REG_CHK2_PMSKr, + SMI_REG_CHK2_DATA_10Gr, + SMI_REG_CHK2_RESULTr, + SMI_REG_CHK3_CTRL1r, + SMI_REG_CHK3_PMSKr = 600, + SMI_REG_CHK3_DATA_10Gr, + SMI_REG_CHK3_RESULTr, + SMI_REG_CHK4_CTRL1r, + SMI_REG_CHK4_PMSKr, + SMI_REG_CHK4_DATA_10Gr, + SMI_REG_CHK4_RESULTr, + SMI_REG_CHK5_CTRL1r, + SMI_REG_CHK5_PMSKr, + SMI_REG_CHK5_DATA_10Gr, + SMI_REG_CHK5_RESULTr = 610, + LINK_DELAY_CTRLr, + MAC_LINK_STSr, + MAC_LINK_MEDIA_STSr, + MAC_LINK_SPD_STSr, + MAC_LINK_DUP_STSr, + MAC_TX_PAUSE_STSr, + MAC_RX_PAUSE_STSr, + MAC_EEE_ABLTYr, + MAC_MSTR_SLV_STSr, + MAC_MSTR_SLV_FAULT_STSr = 620, + PHY_LINK_STSr, + PHY_LINK_MEDIA_STSr, + PHY_LINK_SPD_STSr, + PHY_LINK_DUP_STSr, + PHY_TX_PAUSE_STSr, + PHY_RX_PAUSE_STSr, + PHY_EEE_ABLTYr, + PHY_MSTR_SLV_STSr, + PHY_MSTR_SLV_FAULT_STSr, + SMI_ACCESS_PHY_CTRL_0r = 630, + SMI_ACCESS_PHY_CTRL_1r, + SMI_ACCESS_PHY_CTRL_2r, + SMI_ACCESS_PHY_CTRL_3r, + SMI_ACCESS_PHY_CTRL_4r, + SMI_PORT0_5_ADDR_CTRLr, + SMI_PORT6_9_ADDR_CTRLr, + SMI_CTRLr, + RLFD_CTRLr, + RLFD_10G_ADDRr, + UNI_DIR_CTRLr = 640, + SMI_10GPHY_POLLING_SEL_1r, + SMI_10GPHY_POLLING_REG0_CFGr, + SMI_10GPHY_POLLING_REG9_CFGr, + SMI_10GPHY_POLLING_REG10_CFGr, + MAC_CTRL_1r, + MAC_CTRL_2r, + MAC8_RTL8226B_CTRLr, + TX_RX_IDLEr, + IDLE_DLY_CTRLr, + MAC_IPG_COMPS_CTRLr = 650, + MAC_L2_GLOBAL_CTRL0r, + MAC_L2_GLOBAL_CTRL1r, + MAC_L2_PORT_CTRLr, + MAC_MACSEC_IPG_CFGr, + MAC_MACSEC_ETH_1_0r, + MAC_MACSEC_ETH_3_2r, + MAC_MACSEC_ETH_5_4r, + MAC_MACSEC_ETH_7_6r, + MAC_L2_PADDING_SELr, + MAC_L2_ADDR_CTRLr = 660, + MAC_L2_PORT_MAX_LEN_CTRLr, + MAC_L2_TGPORT_PRMB_DBG0r, + MAC_L2_TGPORT_PRMB_DBG1r, + PHY_CFG_8224r, + MDX_CTRL_8224r, + INT_PHY_OCP_INDR_ACC_CTRL_0r, + INT_PHY_OCP_INDR_ACC_CTRL_1r, + INT_PHY_OCP_INDR_ACC_CTRL_2r, + MAC_PFC_FORCE_FCr, + MAC_TXFIFO_FULTH_CTRL_0r = 670, + MAC_TXFIFO_FULTH_CTRL_1r, + MAC_TXFIFO_FULTH_CTRL_2r, + MAC_TXFIFO_FULTH_CTRL_3r, + MAC_TXFIFO_FULTH_CTRL_4r, + MAC_TXFIFO_FULTH_CTRL_5r, + MACSEC_REG_GLB_SET1_PORT4r, + MACSEC_REG_GLB_IMR_PORT4r, + MACSEC_REG_GLB_ISR_PORT4r, + UNUSED_000C_PORT4r, + MACSEC_PM_CTRL_PORT4r = 680, + MACSEC_REG_GLB_MASK_PORT4r, + MACSEC_REG_GLB_SET4_PORT4r, + MACSEC_REG_IP_PROBE_PORT4r, + UNUSED_0020_PORT4r, + UNUSED_0024_PORT4r, + MACSEC_MBIST_SA_CTRL_PORT4r, + MACSEC_MBIST_STAT_CTRL_PORT4r, + MACSEC_MBIST_SA_AE_TEST_PORT4r, + MACSEC_MBIST_STAT_AE_TEST_PORT4r, + MACSEC_MBIST_SA_FAIL_PORT4r = 690, + MACSEC_XGLBK_FIFO_DBG_PORT4r, + MACSEC_REG_RWDH_AE_PORT4r, + MACSEC_REG_ADDR_AE_PORT4r, + MACSEC_REG_CMD_AE_PORT4r, + MACSEC_REG_RWDL_AI_PORT4r, + MACSEC_REG_ADDR_AI_PORT4r, + MACSEC_REG_RWD_PTP_PORT4r, + MACSEC_REG_CMD_PTP_PORT4r, + UNUSED_005C_PORT4r, + UNUSED_0060_PORT4r = 700, + UNUSED_0064_PORT4r, + UNUSED_0068_PORT4r, + UNUSED_006C_PORT4r, + UNUSED_0070_PORT4r, + UNUSED_0074_PORT4r, + RESERVED_0078_PORT4r, + RESERVED_007C_PORT4r, + MACSEC_TXSYSCRCERR_CNT_PORT4r, + MACSEC_TXSYSPKTERR_CNT_PORT4r, + MACSEC_TXSYSOK_CNT_0_PORT4r = 710, + MACSEC_TXSYSOK_CNT_2_PORT4r, + MACSEC_TXSYSGERR_CNT_PORT4r, + MACSEC_TXSYSGLPIERR_CNT_PORT4r, + MACSEC_TXSYS_DBG_PORT4r, + MACSEC_TX_RX_CNT_INCR_PORT4r, + MACSEC_TXLINECRCERR_CNT_PORT4r, + MACSEC_TXLINEPKTERR_CNT_PORT4r, + MACSEC_TXLINEOK_CNT_0_PORT4r, + MACSEC_TXLINEOK_CNT_2_PORT4r, + MACSEC_TXLINEDROP_CNT_PORT4r = 720, + MACSEC_TXLINESRT_CNT_PORT4r, + MACSEC_TXLINEGERR_CNT_PORT4r, + MACSEC_TXLINE_DBG_PORT4r, + MACSEC_RXLINECRCERR_CNT_PORT4r, + MACSEC_RXLINEPKTERR_CNT_PORT4r, + MACSEC_RXLINEOK_CNT_0_PORT4r, + MACSEC_RXLINEOK_CNT_2_PORT4r, + MACSEC_RXLINESRT_CNT_PORT4r, + MACSEC_RXLINEGERR_CNT_PORT4r, + MACSEC_RXLINEGLPIERR_CNT_PORT4r = 730, + MACSEC_RXLINE_DBG_PORT4r, + MACSEC_RXSYSCRCERR_CNT_PORT4r, + MACSEC_RXSYSPKTERR_CNT_PORT4r, + MACSEC_RXSYSOK_CNT_0_PORT4r, + MACSEC_RXSYSOK_CNT_2_PORT4r, + MACSEC_RXSYSDROP_CNT_PORT4r, + MACSEC_RXSYSSRT_CNT_PORT4r, + MACSEC_RXSYSGERR_CNT_PORT4r, + MACSEC_RXSYS_DBG_PORT4r, + MACSEC_TXSYS_CFG1_PORT4r = 740, + MACSEC_TXSYS_PTPCFG_PORT4r, + MACSEC_TXSYS_OUTERVLAN2_PORT4r, + MACSEC_TXSYS_OUTERVLAN4_PORT4r, + MACSEC_TXSYS_INNERVLAN2_PORT4r, + MACSEC_TXSYS_INNERVLAN4_PORT4r, + MACSEC_TXSYS_INNERVLAN6_PORT4r, + UNUSED_011C_PORT4r, + UNUSED_0120_PORT4r, + UNUSED_0124_PORT4r, + UNUSED_0128_PORT4r = 750, + UNUSED_012C_PORT4r, + UNUSED_0130_PORT4r, + UNUSED_0134_PORT4r, + UNUSED_0138_PORT4r, + UNUSED_013C_PORT4r, + MACSEC_TXLINE_CFG1_PORT4r, + MACSEC_TXLINE_CFG3_PORT4r, + MACSEC_TXLINE_CFG5_PORT4r, + UNUSED_014C_PORT4r, + UNUSED_0150_PORT4r = 760, + UNUSED_0154_PORT4r, + UNUSED_0158_PORT4r, + UNUSED_015C_PORT4r, + UNUSED_0160_PORT4r, + UNUSED_0164_PORT4r, + UNUSED_0168_PORT4r, + UNUSED_016C_PORT4r, + UNUSED_0170_PORT4r, + UNUSED_0174_PORT4r, + UNUSED_0178_PORT4r = 770, + UNUSED_017C_PORT4r, + MACSEC_RXLINE_CFG1_PORT4r, + UNUSED_0184_PORT4r, + UNUSED_0188_PORT4r, + UNUSED_018C_PORT4r, + UNUSED_0190_PORT4r, + UNUSED_0194_PORT4r, + UNUSED_0198_PORT4r, + UNUSED_019C_PORT4r, + UNUSED_01A0_PORT4r = 780, + UNUSED_01A4_PORT4r, + UNUSED_01A8_PORT4r, + UNUSED_01AC_PORT4r, + UNUSED_01B0_PORT4r, + UNUSED_01B4_PORT4r, + UNUSED_01B8_PORT4r, + UNUSED_01BC_PORT4r, + MACSEC_RXSYS_CFG1_PORT4r, + MACSEC_RXSYS_CFG3_PORT4r, + MACSEC_RXSYS_OUTERVLAN2_PORT4r = 790, + MACSEC_RXSYS_OUTERVLAN4_PORT4r, + MACSEC_RXSYS_INNERVLAN2_PORT4r, + MACSEC_RXSYS_INNERVLAN4_PORT4r, + MACSEC_RXSYS_INNERVLAN6_PORT4r, + MACSEC_RXSYS_CFG4_PORT4r, + MACSEC_RXSYS_CFG6_PORT4r, + MACSEC_REG_GLB_SET1_PORT5r, + MACSEC_REG_GLB_IMR_PORT5r, + MACSEC_REG_GLB_ISR_PORT5r, + UNUSED_000C_PORT5r = 800, + MACSEC_PM_CTRL_PORT5r, + MACSEC_REG_GLB_MASK_PORT5r, + MACSEC_REG_GLB_SET4_PORT5r, + MACSEC_REG_IP_PROBE_PORT5r, + UNUSED_0020_PORT5r, + UNUSED_0024_PORT5r, + MACSEC_MBIST_SA_CTRL_PORT5r, + MACSEC_MBIST_STAT_CTRL_PORT5r, + MACSEC_MBIST_SA_AE_TEST_PORT5r, + MACSEC_MBIST_STAT_AE_TEST_PORT5r = 810, + MACSEC_MBIST_SA_FAIL_PORT5r, + MACSEC_XGLBK_FIFO_DBG_PORT5r, + MACSEC_REG_RWDH_AE_PORT5r, + MACSEC_REG_ADDR_AE_PORT5r, + MACSEC_REG_CMD_AE_PORT5r, + MACSEC_REG_RWDL_AI_PORT5r, + MACSEC_REG_ADDR_AI_PORT5r, + MACSEC_REG_RWD_PTP_PORT5r, + MACSEC_REG_CMD_PTP_PORT5r, + UNUSED_005C_PORT5r = 820, + UNUSED_0060_PORT5r, + UNUSED_0064_PORT5r, + UNUSED_0068_PORT5r, + UNUSED_006C_PORT5r, + UNUSED_0070_PORT5r, + UNUSED_0074_PORT5r, + RESERVED_0078_PORT5r, + RESERVED_007C_PORT5r, + MACSEC_TXSYSCRCERR_CNT_PORT5r, + MACSEC_TXSYSPKTERR_CNT_PORT5r = 830, + MACSEC_TXSYSOK_CNT_0_PORT5r, + MACSEC_TXSYSOK_CNT_2_PORT5r, + MACSEC_TXSYSGERR_CNT_PORT5r, + MACSEC_TXSYSGLPIERR_CNT_PORT5r, + MACSEC_TXSYS_DBG_PORT5r, + MACSEC_TX_RX_CNT_INCR_PORT5r, + MACSEC_TXLINECRCERR_CNT_PORT5r, + MACSEC_TXLINEPKTERR_CNT_PORT5r, + MACSEC_TXLINEOK_CNT_0_PORT5r, + MACSEC_TXLINEOK_CNT_2_PORT5r = 840, + MACSEC_TXLINEDROP_CNT_PORT5r, + MACSEC_TXLINESRT_CNT_PORT5r, + MACSEC_TXLINEGERR_CNT_PORT5r, + MACSEC_TXLINE_DBG_PORT5r, + MACSEC_RXLINECRCERR_CNT_PORT5r, + MACSEC_RXLINEPKTERR_CNT_PORT5r, + MACSEC_RXLINEOK_CNT_0_PORT5r, + MACSEC_RXLINEOK_CNT_2_PORT5r, + MACSEC_RXLINESRT_CNT_PORT5r, + MACSEC_RXLINEGERR_CNT_PORT5r = 850, + MACSEC_RXLINEGLPIERR_CNT_PORT5r, + MACSEC_RXLINE_DBG_PORT5r, + MACSEC_RXSYSCRCERR_CNT_PORT5r, + MACSEC_RXSYSPKTERR_CNT_PORT5r, + MACSEC_RXSYSOK_CNT_0_PORT5r, + MACSEC_RXSYSOK_CNT_2_PORT5r, + MACSEC_RXSYSDROP_CNT_PORT5r, + MACSEC_RXSYSSRT_CNT_PORT5r, + MACSEC_RXSYSGERR_CNT_PORT5r, + MACSEC_RXSYS_DBG_PORT5r = 860, + MACSEC_TXSYS_CFG1_PORT5r, + MACSEC_TXSYS_PTPCFG_PORT5r, + MACSEC_TXSYS_OUTERVLAN2_PORT5r, + MACSEC_TXSYS_OUTERVLAN4_PORT5r, + MACSEC_TXSYS_INNERVLAN2_PORT5r, + MACSEC_TXSYS_INNERVLAN4_PORT5r, + MACSEC_TXSYS_INNERVLAN6_PORT5r, + UNUSED_011C_PORT5r, + UNUSED_0120_PORT5r, + UNUSED_0124_PORT5r = 870, + UNUSED_0128_PORT5r, + UNUSED_012C_PORT5r, + UNUSED_0130_PORT5r, + UNUSED_0134_PORT5r, + UNUSED_0138_PORT5r, + UNUSED_013C_PORT5r, + MACSEC_TXLINE_CFG1_PORT5r, + MACSEC_TXLINE_CFG3_PORT5r, + MACSEC_TXLINE_CFG5_PORT5r, + UNUSED_014C_PORT5r = 880, + UNUSED_0150_PORT5r, + UNUSED_0154_PORT5r, + UNUSED_0158_PORT5r, + UNUSED_015C_PORT5r, + UNUSED_0160_PORT5r, + UNUSED_0164_PORT5r, + UNUSED_0168_PORT5r, + UNUSED_016C_PORT5r, + UNUSED_0170_PORT5r, + UNUSED_0174_PORT5r = 890, + UNUSED_0178_PORT5r, + UNUSED_017C_PORT5r, + MACSEC_RXLINE_CFG1_PORT5r, + UNUSED_0184_PORT5r, + UNUSED_0188_PORT5r, + UNUSED_018C_PORT5r, + UNUSED_0190_PORT5r, + UNUSED_0194_PORT5r, + UNUSED_0198_PORT5r, + UNUSED_019C_PORT5r = 900, + UNUSED_01A0_PORT5r, + UNUSED_01A4_PORT5r, + UNUSED_01A8_PORT5r, + UNUSED_01AC_PORT5r, + UNUSED_01B0_PORT5r, + UNUSED_01B4_PORT5r, + UNUSED_01B8_PORT5r, + UNUSED_01BC_PORT5r, + MACSEC_RXSYS_CFG1_PORT5r, + MACSEC_RXSYS_CFG3_PORT5r = 910, + MACSEC_RXSYS_OUTERVLAN2_PORT5r, + MACSEC_RXSYS_OUTERVLAN4_PORT5r, + MACSEC_RXSYS_INNERVLAN2_PORT5r, + MACSEC_RXSYS_INNERVLAN4_PORT5r, + MACSEC_RXSYS_INNERVLAN6_PORT5r, + MACSEC_RXSYS_CFG4_PORT5r, + MACSEC_RXSYS_CFG6_PORT5r, + MACSEC_REG_GLB_SET1_PORT6r, + MACSEC_REG_GLB_IMR_PORT6r, + MACSEC_REG_GLB_ISR_PORT6r = 920, + UNUSED_000C_PORT6r, + MACSEC_PM_CTRL_PORT6r, + MACSEC_REG_GLB_MASK_PORT6r, + MACSEC_REG_GLB_SET4_PORT6r, + MACSEC_REG_IP_PROBE_PORT6r, + UNUSED_0020_PORT6r, + UNUSED_0024_PORT6r, + MACSEC_MBIST_SA_CTRL_PORT6r, + MACSEC_MBIST_STAT_CTRL_PORT6r, + MACSEC_MBIST_SA_AE_TEST_PORT6r = 930, + MACSEC_MBIST_STAT_AE_TEST_PORT6r, + MACSEC_MBIST_SA_FAIL_PORT6r, + MACSEC_XGLBK_FIFO_DBG_PORT6r, + MACSEC_REG_RWDH_AE_PORT6r, + MACSEC_REG_ADDR_AE_PORT6r, + MACSEC_REG_CMD_AE_PORT6r, + MACSEC_REG_RWDL_AI_PORT6r, + MACSEC_REG_ADDR_AI_PORT6r, + MACSEC_REG_RWD_PTP_PORT6r, + MACSEC_REG_CMD_PTP_PORT6r = 940, + UNUSED_005C_PORT6r, + UNUSED_0060_PORT6r, + UNUSED_0064_PORT6r, + UNUSED_0068_PORT6r, + UNUSED_006C_PORT6r, + UNUSED_0070_PORT6r, + UNUSED_0074_PORT6r, + RESERVED_0078_PORT6r, + RESERVED_007C_PORT6r, + MACSEC_TXSYSCRCERR_CNT_PORT6r = 950, + MACSEC_TXSYSPKTERR_CNT_PORT6r, + MACSEC_TXSYSOK_CNT_0_PORT6r, + MACSEC_TXSYSOK_CNT_2_PORT6r, + MACSEC_TXSYSGERR_CNT_PORT6r, + MACSEC_TXSYSGLPIERR_CNT_PORT6r, + MACSEC_TXSYS_DBG_PORT6r, + MACSEC_TX_RX_CNT_INCR_PORT6r, + MACSEC_TXLINECRCERR_CNT_PORT6r, + MACSEC_TXLINEPKTERR_CNT_PORT6r, + MACSEC_TXLINEOK_CNT_0_PORT6r = 960, + MACSEC_TXLINEOK_CNT_2_PORT6r, + MACSEC_TXLINEDROP_CNT_PORT6r, + MACSEC_TXLINESRT_CNT_PORT6r, + MACSEC_TXLINEGERR_CNT_PORT6r, + MACSEC_TXLINE_DBG_PORT6r, + MACSEC_RXLINECRCERR_CNT_PORT6r, + MACSEC_RXLINEPKTERR_CNT_PORT6r, + MACSEC_RXLINEOK_CNT_0_PORT6r, + MACSEC_RXLINEOK_CNT_2_PORT6r, + MACSEC_RXLINESRT_CNT_PORT6r = 970, + MACSEC_RXLINEGERR_CNT_PORT6r, + MACSEC_RXLINEGLPIERR_CNT_PORT6r, + MACSEC_RXLINE_DBG_PORT6r, + MACSEC_RXSYSCRCERR_CNT_PORT6r, + MACSEC_RXSYSPKTERR_CNT_PORT6r, + MACSEC_RXSYSOK_CNT_0_PORT6r, + MACSEC_RXSYSOK_CNT_2_PORT6r, + MACSEC_RXSYSDROP_CNT_PORT6r, + MACSEC_RXSYSSRT_CNT_PORT6r, + MACSEC_RXSYSGERR_CNT_PORT6r = 980, + MACSEC_RXSYS_DBG_PORT6r, + MACSEC_TXSYS_CFG1_PORT6r, + MACSEC_TXSYS_PTPCFG_PORT6r, + MACSEC_TXSYS_OUTERVLAN2_PORT6r, + MACSEC_TXSYS_OUTERVLAN4_PORT6r, + MACSEC_TXSYS_INNERVLAN2_PORT6r, + MACSEC_TXSYS_INNERVLAN4_PORT6r, + MACSEC_TXSYS_INNERVLAN6_PORT6r, + UNUSED_011C_PORT6r, + UNUSED_0120_PORT6r = 990, + UNUSED_0124_PORT6r, + UNUSED_0128_PORT6r, + UNUSED_012C_PORT6r, + UNUSED_0130_PORT6r, + UNUSED_0134_PORT6r, + UNUSED_0138_PORT6r, + UNUSED_013C_PORT6r, + MACSEC_TXLINE_CFG1_PORT6r, + MACSEC_TXLINE_CFG3_PORT6r, + MACSEC_TXLINE_CFG5_PORT6r = 1000, + UNUSED_014C_PORT6r, + UNUSED_0150_PORT6r, + UNUSED_0154_PORT6r, + UNUSED_0158_PORT6r, + UNUSED_015C_PORT6r, + UNUSED_0160_PORT6r, + UNUSED_0164_PORT6r, + UNUSED_0168_PORT6r, + UNUSED_016C_PORT6r, + UNUSED_0170_PORT6r = 1010, + UNUSED_0174_PORT6r, + UNUSED_0178_PORT6r, + UNUSED_017C_PORT6r, + MACSEC_RXLINE_CFG1_PORT6r, + UNUSED_0184_PORT6r, + UNUSED_0188_PORT6r, + UNUSED_018C_PORT6r, + UNUSED_0190_PORT6r, + UNUSED_0194_PORT6r, + UNUSED_0198_PORT6r = 1020, + UNUSED_019C_PORT6r, + UNUSED_01A0_PORT6r, + UNUSED_01A4_PORT6r, + UNUSED_01A8_PORT6r, + UNUSED_01AC_PORT6r, + UNUSED_01B0_PORT6r, + UNUSED_01B4_PORT6r, + UNUSED_01B8_PORT6r, + UNUSED_01BC_PORT6r, + MACSEC_RXSYS_CFG1_PORT6r = 1030, + MACSEC_RXSYS_CFG3_PORT6r, + MACSEC_RXSYS_OUTERVLAN2_PORT6r, + MACSEC_RXSYS_OUTERVLAN4_PORT6r, + MACSEC_RXSYS_INNERVLAN2_PORT6r, + MACSEC_RXSYS_INNERVLAN4_PORT6r, + MACSEC_RXSYS_INNERVLAN6_PORT6r, + MACSEC_RXSYS_CFG4_PORT6r, + MACSEC_RXSYS_CFG6_PORT6r, + MACSEC_REG_GLB_SET1_PORT7r, + MACSEC_REG_GLB_IMR_PORT7r = 1040, + MACSEC_REG_GLB_ISR_PORT7r, + UNUSED_000C_PORT7r, + MACSEC_PM_CTRL_PORT7r, + MACSEC_REG_GLB_MASK_PORT7r, + MACSEC_REG_GLB_SET4_PORT7r, + MACSEC_REG_IP_PROBE_PORT7r, + UNUSED_0020_PORT7r, + UNUSED_0024_PORT7r, + MACSEC_MBIST_SA_CTRL_PORT7r, + MACSEC_MBIST_STAT_CTRL_PORT7r = 1050, + MACSEC_MBIST_SA_AE_TEST_PORT7r, + MACSEC_MBIST_STAT_AE_TEST_PORT7r, + MACSEC_MBIST_SA_FAIL_PORT7r, + MACSEC_XGLBK_FIFO_DBG_PORT7r, + MACSEC_REG_RWDH_AE_PORT7r, + MACSEC_REG_ADDR_AE_PORT7r, + MACSEC_REG_CMD_AE_PORT7r, + MACSEC_REG_RWDL_AI_PORT7r, + MACSEC_REG_ADDR_AI_PORT7r, + MACSEC_REG_RWD_PTP_PORT7r = 1060, + MACSEC_REG_CMD_PTP_PORT7r, + UNUSED_005C_PORT7r, + UNUSED_0060_PORT7r, + UNUSED_0064_PORT7r, + UNUSED_0068_PORT7r, + UNUSED_006C_PORT7r, + UNUSED_0070_PORT7r, + UNUSED_0074_PORT7r, + RESERVED_0078_PORT7r, + RESERVED_007C_PORT7r = 1070, + MACSEC_TXSYSCRCERR_CNT_PORT7r, + MACSEC_TXSYSPKTERR_CNT_PORT7r, + MACSEC_TXSYSOK_CNT_0_PORT7r, + MACSEC_TXSYSOK_CNT_2_PORT7r, + MACSEC_TXSYSGERR_CNT_PORT7r, + MACSEC_TXSYSGLPIERR_CNT_PORT7r, + MACSEC_TXSYS_DBG_PORT7r, + MACSEC_TX_RX_CNT_INCR_PORT7r, + MACSEC_TXLINECRCERR_CNT_PORT7r, + MACSEC_TXLINEPKTERR_CNT_PORT7r = 1080, + MACSEC_TXLINEOK_CNT_0_PORT7r, + MACSEC_TXLINEOK_CNT_2_PORT7r, + MACSEC_TXLINEDROP_CNT_PORT7r, + MACSEC_TXLINESRT_CNT_PORT7r, + MACSEC_TXLINEGERR_CNT_PORT7r, + MACSEC_TXLINE_DBG_PORT7r, + MACSEC_RXLINECRCERR_CNT_PORT7r, + MACSEC_RXLINEPKTERR_CNT_PORT7r, + MACSEC_RXLINEOK_CNT_0_PORT7r, + MACSEC_RXLINEOK_CNT_2_PORT7r = 1090, + MACSEC_RXLINESRT_CNT_PORT7r, + MACSEC_RXLINEGERR_CNT_PORT7r, + MACSEC_RXLINEGLPIERR_CNT_PORT7r, + MACSEC_RXLINE_DBG_PORT7r, + MACSEC_RXSYSCRCERR_CNT_PORT7r, + MACSEC_RXSYSPKTERR_CNT_PORT7r, + MACSEC_RXSYSOK_CNT_0_PORT7r, + MACSEC_RXSYSOK_CNT_2_PORT7r, + MACSEC_RXSYSDROP_CNT_PORT7r, + MACSEC_RXSYSSRT_CNT_PORT7r = 1100, + MACSEC_RXSYSGERR_CNT_PORT7r, + MACSEC_RXSYS_DBG_PORT7r, + MACSEC_TXSYS_CFG1_PORT7r, + MACSEC_TXSYS_PTPCFG_PORT7r, + MACSEC_TXSYS_OUTERVLAN2_PORT7r, + MACSEC_TXSYS_OUTERVLAN4_PORT7r, + MACSEC_TXSYS_INNERVLAN2_PORT7r, + MACSEC_TXSYS_INNERVLAN4_PORT7r, + MACSEC_TXSYS_INNERVLAN6_PORT7r, + UNUSED_011C_PORT7r = 1110, + UNUSED_0120_PORT7r, + UNUSED_0124_PORT7r, + UNUSED_0128_PORT7r, + UNUSED_012C_PORT7r, + UNUSED_0130_PORT7r, + UNUSED_0134_PORT7r, + UNUSED_0138_PORT7r, + UNUSED_013C_PORT7r, + MACSEC_TXLINE_CFG1_PORT7r, + MACSEC_TXLINE_CFG3_PORT7r = 1120, + MACSEC_TXLINE_CFG5_PORT7r, + UNUSED_014C_PORT7r, + UNUSED_0150_PORT7r, + UNUSED_0154_PORT7r, + UNUSED_0158_PORT7r, + UNUSED_015C_PORT7r, + UNUSED_0160_PORT7r, + UNUSED_0164_PORT7r, + UNUSED_0168_PORT7r, + UNUSED_016C_PORT7r = 1130, + UNUSED_0170_PORT7r, + UNUSED_0174_PORT7r, + UNUSED_0178_PORT7r, + UNUSED_017C_PORT7r, + MACSEC_RXLINE_CFG1_PORT7r, + UNUSED_0184_PORT7r, + UNUSED_0188_PORT7r, + UNUSED_018C_PORT7r, + UNUSED_0190_PORT7r, + UNUSED_0194_PORT7r = 1140, + UNUSED_0198_PORT7r, + UNUSED_019C_PORT7r, + UNUSED_01A0_PORT7r, + UNUSED_01A4_PORT7r, + UNUSED_01A8_PORT7r, + UNUSED_01AC_PORT7r, + UNUSED_01B0_PORT7r, + UNUSED_01B4_PORT7r, + UNUSED_01B8_PORT7r, + UNUSED_01BC_PORT7r = 1150, + MACSEC_RXSYS_CFG1_PORT7r, + MACSEC_RXSYS_CFG3_PORT7r, + MACSEC_RXSYS_OUTERVLAN2_PORT7r, + MACSEC_RXSYS_OUTERVLAN4_PORT7r, + MACSEC_RXSYS_INNERVLAN2_PORT7r, + MACSEC_RXSYS_INNERVLAN4_PORT7r, + MACSEC_RXSYS_INNERVLAN6_PORT7r, + MACSEC_RXSYS_CFG4_PORT7r, + MACSEC_RXSYS_CFG6_PORT7r, + + /* Power Saving */ + GATING_CLOCK0r = 1160, + GATING_CLOCK1r, + EEE_TX_Q_CTRLr, + EEE_TX_MINIFG_CTRL0r, + EEE_TX_MINIFG_CTRL1r, + EEE_TX_MINIFG_CTRL2r, + EEE_TX_MINIFG_CTRL3r, + EEE_TX_MINIFG_CTRL4r, + EEE_TX_CTRLr, + EEE_TX_TIMER_100M_CTRLr, + EEE_TX_TIMER_GELITE_CTRLr = 1170, + EEE_TX_TIMER_GIGA_CTRLr, + EEE_TX_TIMER_2P5GLITE_CTRLr, + EEE_TX_TIMER_2P5G_CTRLr, + EEE_TX_TIMER_5GLITE_CTRLr, + EEE_TX_TIMER_5G_CTRLr, + EEE_TX_TIMER_10GLITE_CTRLr, + EEE_TX_TIMER_10G_CTRLr, + EEE_CTRLr, + EEE_RX_GELITE_CTRLr, + EEE_RX_GE_CTRLr = 1180, + LPI_OPTIONr, + + /* RA */ + RA_FIFO_FUL_THR0r, + RA_FIFO_EMPTY_THR0r, + RA_TX_STATUS0r, + RA_RX_STATUS0r, + RA_HSG_IFG0r, + RA_MACSEC_ETH0r, + RA_MACSEC_VLAN0r, + RA_MACSEC_IFG_CTRL0r, + RA_PAUSE_CTRL0r = 1190, + RA_GLB_CTRL0r, + RA_PADDING_CTRL0r, + RA_SLOT_TIME0r, + RA_SOFT_RST0r, + RA_FIFO_FUL_THR1r, + RA_FIFO_EMPTY_THR1r, + RA_TX_STATUS1r, + RA_RX_STATUS1r, + RA_HSG_IFG1r, + RA_MACSEC_ETH1r = 1200, + RA_MACSEC_VLAN1r, + RA_MACSEC_IFG_CTRL1r, + RA_PAUSE_CTRL1r, + RA_GLB_CTRL1r, + RA_PADDING_CTRL1r, + RA_SLOT_TIME1r, + RA_SOFT_RST1r, + RA_FIFO_FUL_THR2r, + RA_FIFO_EMPTY_THR2r, + RA_TX_STATUS2r = 1210, + RA_RX_STATUS2r, + RA_HSG_IFG2r, + RA_MACSEC_ETH2r, + RA_MACSEC_VLAN2r, + RA_MACSEC_IFG_CTRL2r, + RA_PAUSE_CTRL2r, + RA_GLB_CTRL2r, + RA_PADDING_CTRL2r, + RA_SLOT_TIME2r, + RA_SOFT_RST2r = 1220, + RA_FIFO_FUL_THR3r, + RA_FIFO_EMPTY_THR3r, + RA_TX_STATUS3r, + RA_RX_STATUS3r, + RA_HSG_IFG3r, + RA_MACSEC_ETH3r, + RA_MACSEC_VLAN3r, + RA_MACSEC_IFG_CTRL3r, + RA_PAUSE_CTRL3r, + RA_GLB_CTRL3r = 1230, + RA_PADDING_CTRL3r, + RA_SLOT_TIME3r, + RA_SOFT_RST3r, + + /* NIC */ + NIC_BUFFSIZE_CTRLr, + NIC_RXBUFF_CTRLr, + NIC_RXCMDr, + NIC_TXCMDr, + NIC_INT_STSr, + NIC_INT_MSKr, + NIC_RX_CTRLr = 1240, + NIC_TX_CTRLr, + NIC_MC_HASH_TBLr, + NIC_UC_HASH_TBLr, + NIC_RX_BUFF_DATAr, + NIC_RX_CURR_PKTr, + CPU_RX_CURR_PKTr, + NIC_TX_BUFF_AVAILr, + NIC_TX_CURR_PKTr, + NIC_TX_CURR_UNITr, + NIC_TX_PKT_INFOr = 1250, + CPU_TX_CURR_PKTr, + DMY_REG0_NICr, + DMY_REG1_NICr, + + /* Cpu Tag */ + CPU_TAG_TPID_CTRLr, + CPU_TAG_CTRLr, + EXT_CPU_CTRLr, + CPU_TAG_AWARE_CTRLr, + + /* Table Access */ + ITA_CTRL0r, + ITA_L2_CTRLr, + ITA_HSAB_CTRLr = 1260, + ITA_WRITE_DATA0r, + ITA_READ_DATA0r, + TEST_MODE_ALE_HSA_MULTI_CTRLr, + TBL_ACCESS_HSA_CTRLr, + TBL_ACCESS_HSA_DATAr, + + /* 8051 */ + DW8051_CFGr, + DW8051_IROMr, + + /* 802.1Q VLAN */ + VLAN_PORT_AFTr, + VLAN_CTRLr, + VLAN_PORT_IGR_FLTRr = 1270, + VLAN_PORT_PB_VLANr, + VLAN_PORT_EGR_TRANSr, + VLAN_PORT_EGR_KEEPr, + VLAN_PORT_EGR_TAGr, + VLAN_L2_LRN_DISr, + PORT_BASED_FID_ENr, + PORT_BASED_FIDr, + VLAN_TAG_PRI_CFGr, + + /* 802.1D SVLAN */ + VS_GLB_CTRLr, + VS_UPLINK_PORTr = 1280, + VS_CTRLr, + VS_UNTAG_SVIDr, + VS_PORT_DFLT_SVIDr, + SVLAN_TRAP_CTRLr, + + /* C2S Table */ + VLAN_C2S_ENTRYr, + + /* RMA */ + RMA_OP_CTRL_00r, + RMA_OP_CTRL_01r, + RMA_OP_CTRL_02r, + RMA_OP_CTRL_03r, + RMA_OP_CTRL_04r = 1290, + RMA_OP_CTRL_08r, + RMA_OP_CTRL_0Dr, + RMA_OP_CTRL_0Er, + RMA_OP_CTRL_10r, + RMA_OP_CTRL_11r, + RMA_OP_CTRL_12r, + RMA_OP_CTRL_13r, + RMA_OP_CTRL_18r, + RMA_OP_CTRL_1Ar, + RMA_OP_CTRL_20r = 1300, + RMA_OP_CTRL_21r, + RMA_OP_CTRL_22r, + RMA_OP_CTRL_CDPr, + RMA_OP_CTRL_CSSTPr, + RMA_OP_CTRL_LLDPr, + RMA_CFGr, + RMA_PORT_PTP_ETH2_CTRLr, + RMA_PORT_PTP_UDP_CTRLr, + RMA_PORT_PTP_DELAY_CARE_CTRLr, + RMA_PORT_PTP_PDELAY_CARE_CTRLr = 1310, + RMA_PORT_PTP_ASM_CARE_CTRLr, + RMA_PTP_TRAP_CTRLr, + + /* Link Aggregation */ + TRK_MBR_CTRLr, + TRK_HASH_CTRLr, + TRK_CTRLr, + TRK_FLOW_CTRLr, + TRK_QUEUE_EMPTYr, + + /* Spanning Tree */ + MSPT_STATEr, + + /* MAC Forwarding Control */ + L2_CTRLr, + L2_AGE_CTRLr = 1320, + L2_PORT_AGE_CTRLr, + L2_NEWSA_CTRLr, + L2_UNMATCH_SA_CTRLr, + L2_SA_MOVING_FORBIDr, + L2_UNKN_UC_FLD_PMSKr, + L2_UNKN_MC_FLD_PMSKr, + IPV4_UNKN_MC_FLD_PMSKr, + IPV6_UNKN_MC_FLD_PMSKr, + L2_BC_FLD_PMSKr, + L2_PORT_UC_LM_ACTr = 1330, + L2_PORT_MC_LM_ACTr, + IPV4_PORT_MC_LM_ACTr, + IPV6_PORT_MC_LM_ACTr, + L2_LRN_CONSTRT_CTRLr, + L2_LRN_CONSTRT_CNTr, + L2_LRN_CONSTRT_ACTr, + L2_LRN_PORT_CONSTRT_CTRLr, + L2_LRN_PORT_CONSTRT_CNTr, + L2_LRN_PORT_CONSTRT_ACTr, + L2_TBL_FLUSH_CMDr = 1340, + L2_TBL_FLUSH_ALLr, + L2_TBL_FLUSH_MODEr, + L2_TBL_FLUSH_XIDr, + SOURCE_PORT_PERMITr, + IPMC_GROUP_DIPr, + IPMC_GROUP_PMSKr, + IPMC_GROUP_VALIDr, + IPMUL_NO_VLAN_EGRESSr, + IPMUL_NO_PORTISOr, + L2_FORCE_MODEr = 1350, + L2_FORCE_DPM_PORTr, + + /* IGMP & MLD */ + IGMP_CTRLr, + IGMP_QUERY_INTVLr, + IGMP_DYN_ROUTER_INFOr, + IGMP_ROUTER_PORT_CRTLr, + IGMP_PORT_CTRLr, + PORT_CURR_GROUPr, + IGMP_TBL_USAGEr, + IGMP_TRAP_CTRLr, + + /* Port Isolation */ + PORT_ISO_PORT_PMSKr = 1360, + + /* Port Mirror */ + MIR_CTRLr, + MIR_SET_CTRLr, + MIR_SET_PMSKr, + MIR_SAMPLE_CRTLr, + MIR_MATCHEDr, + + /* RSPAN */ + MIR_RSPAN_CTRLr, + MIR_RSPAN_TAG_CTRLr, + MIR_RSPAN_TX_PORT_CTRLr, + MIR_RSPAN_RX_ACTr, + + /* ACL Module */ + ACL_CTRLr = 1370, + ACL_GPIO_CTRLr, + ACL_PORT_ENr, + ACL_PORT_UNMATCH_PERMITr, + ACL_TEMPLATE_CTRLr, + ACL_ACT_CTRLr, + ACL_HIT_INDICATORr, + + /* Range Check (port/vlan/ip/L4port) */ + RNG_CHK_VIDr, + RNG_CHK_IPr, + RNG_CHK_PORTr, + + /* ACL LOG COUNTER */ + ACL_LOG_CNTR_RSTr = 1380, + ACL_CNTR_RST_VALr, + ACL_LOG_CNTR_TYPEr, + ACL_LOG_CNTR_MODEr, + ACL_LOG_CNTR_DATAr, + ACL_LATCH_TRIGGERr, + ACL_LATCH_ADDRr, + ACL_LATCH_VAL_Lr, + ACL_LATCH_VAL_Hr, + + /* PTP (Precision Time Protocol) */ + PTP_TIME_TOD_DELAYr, + PTP_TIME_OP_DURATIONr = 1390, + PTP_DUMMY_RG02r, + PTP_DUMMY_RG03r, + PTP_OTAG_CONFIG0r, + PTP_OTAG_CONFIG1r, + PTP_OTAG_CONFIG2r, + PTP_OTAG_CONFIG3r, + PTP_ITAG_CONFIG0r, + PTP_DUMMY_RG09r, + PTP_DUMMY_RG10r, + PTP_APPLY_FREQr = 1400, + PTP_TIME_FREQ0r, + PTP_TIME_FREQ1r, + PTP_CUR_TIME_FREQ0r, + PTP_CUR_TIME_FREQ1r, + PTP_TIME_NSEC0r, + PTP_TIME_NSEC1r, + PTP_TIME_SEC0r, + PTP_TIME_SEC1r, + PTP_TIME_SEC2r, + PTP_TIME_CRTLr = 1410, + PTP_TIME_NSEC_RD0r, + PTP_TIME_NSEC_RD1r, + PTP_TIME_SEC_RD0r, + PTP_TIME_SEC_RD1r, + PTP_TIME_SEC_RD2r, + PTP_CLKOUT_NSEC0r, + PTP_CLKOUT_NSEC1r, + PTP_CLKOUT_SEC0r, + PTP_CLKOUT_SEC1r, + PTP_CLKOUT_SEC2r = 1420, + PTP_CLKOUT_CTRLr, + PTP_CLKOUT_HALF_PERD_NS_Lr, + PTP_CLKOUT_HALF_PERD_NS_Hr, + PTP_TIME_OP_CTRLr, + PTP_PPS_CTRLr, + PTP_TX_TIMESTAMP_RD0r, + PTP_TX_TIMESTAMP_RD1r, + PTP_TX_TIMESTAMP_RD2r, + PTP_TX_TIMESTAMP_RD3r, + PTP_MIB_INTRr = 1430, + PTP_GLOBAL_DBGr, + PTP_CLK_SRC_CTRLr, + PTP_CLKOUT_HALF_PERD_FS_Lr, + PTP_CLKOUT_HALF_PERD_FS_Hr, + PTP_DUMMY_RG46r, + PTP_DUMMY_RG47r, + PPS_IN_LATCH_TIME_NSEC_Lr, + PPS_IN_LATCH_TIME_NSEC_Hr, + PPS_IN_LATCH_TIME_SEC_Lr, + PPS_IN_LATCH_TIME_SEC_Mr = 1440, + PPS_IN_LATCH_TIME_SEC_Hr, + PTP_DUMMY_RG53r, + PTP_DUMMY_RG54r, + PTP_DUMMY_RG55r, + PTP_DUMMY_RG56r, + PTP_DUMMY_RG57r, + PTP_DUMMY_RG58r, + PTP_DUMMY_RG59r, + PTP_DUMMY_RG60r, + PTP_DUMMY_RG61r = 1450, + PTP_TIME_SPEED_UPr, + PTP_VERSIONr, + P0_PORT_CTRLr, + P0_LINK_DELAY_Hr, + P0_MISC_CTRLr, + P0_TX_IMBALr, + P0_RX_IMBALr, + P0_PTP_PORTIDr, + P0_PTP_DUMMY_RG06r, + P0_DBG_PTP_CTRLr = 1460, + TOD_OUT_DATA_CTRLr, + TOD_OUT_CTRL0r, + TOD_OUT_CTRL1r, + TOD_SARP_GPS_WEEKr, + TOD_SARP_GPS_SEC_Lr, + TOD_SARP_GPS_SEC_Hr, + TOD_UART_SETTINGr, + TOD_INTRr, + + /* Storm Control (B/M/UM/DLF) */ + RX_STORM_BCAST_CTRLr, + RX_STORM_MCAST_CTRLr = 1470, + RX_STORM_UNUCAST_CTRLr, + RX_STORM_UNMCAST_CTRLr, + RX_STORM_BCAST_METERr, + RX_STORM_MCAST_METERr, + RX_STORM_UNUCAST_METERr, + RX_STORM_UNMCAST_METERr, + CFG_STORM_EXTr, + STORM_EXT_MTRIDX_CFGr, + + /* IngressBW */ + IGBW_CTRLr, + IGBW_LB_CTRLr = 1480, + IGBW_PORT_CTRLr, + IGBW_PORT_BURST_CTRLr, + IGBW_PORT_LB_RSTr, + IGBW_PORT_CNGST_FLAGr, + IGBW_PORT_FC_CTRLr, + IGBW_PORT_DROP_CTRLr, + + /* Egress Bandwidth Control */ + EGBW_ENCAP_CTRLr, + EGBW_CTRLr, + EGBW_LB_CTRLr, + EGBW_PORT_CTRLr = 1490, + EGBW_PORT_LB_RSTr, + EGBW_PORT_Q_MAX_LB_CTRL_SETr, + EGBW_PORT_Q_MAX_LB_RST_SETr, + EGBW_PORT_Q_ASSURED_FIX_BURST_CTRL_SETr, + EGBW_PORT_Q_ASSURED_LB_CTRL_SETr, + EGBW_PORT_Q_FIX_LB_CTRL_SETr, + EGBW_PORT_Q_ASSURED_FIX_LB_RST_SETr, + EGBW_RATE_10M_CTRLr, + EGBW_RATE_100M_CTRLr, + EGBW_RATE_1G_CTRLr = 1500, + EGBW_RATE_500M_CTRLr, + EGBW_RATE_10G_CTRLr, + EGBW_RATE_2500M_CTRLr, + EGBW_RATE_1250M_CTRLr, + EGBW_RATE_5G_CTRLr, + DMY_REG0_EGRESS_CTRLr, + + /* Meter Marker */ + SHARED_METER_RATE_CTRLr, + SHARED_METER_BURST_CTRLr, + SHARED_METER_MODEr, + SHARED_METER_EXCEEDr = 1510, + SHARED_METER_EXCEED_ICPUr, + SHARED_METER_IPG_CTRLr, + SHARED_METER_LB_CTRLr, + SHARED_METER_LB_PPS_CTRLr, + + /* FlowControl & Backpressure */ + FC_CTRLr, + FC_PORT_ACT_CTRLr, + FC_GLB_SYS_UTIL_THRr, + FC_GLB_DROP_THRr, + FC_GLB_HI_THRr, + FC_GLB_LO_THRr = 1520, + FC_GLB_FCOFF_HI_THRr, + FC_GLB_FCOFF_LO_THRr, + FC_JUMBO_HI_THRr, + FC_JUMBO_LO_THRr, + FC_JUMBO_FCOFF_HI_THRr, + FC_JUMBO_FCOFF_LO_THRr, + FC_JUMBO_THR_ADJUSTr, + FC_PORT_HI_THRr, + FC_PORT_LO_THRr, + FC_PORT_FCOFF_HI_THRr = 1530, + FC_PORT_FCOFF_LO_THRr, + FC_PORT_GUAR_THRr, + FC_PORT_THR_SET_SELr, + FC_PORT_EGR_DROP_CTRLr, + FC_HOL_PRVNT_CTRLr, + FC_PORT_Q_EGR_DROP_CTRL_SETr, + FC_PORT_Q_EGR_FORCE_DROP_CTRL_SETr, + FC_Q_EGR_DROP_THRr, + FC_PORT_EGR_DROP_THR_SET_SELr, + FC_GLB_PAGE_CNTr = 1540, + FC_PORT_PAGE_CNTr, + FC_GLB_PAGE_PEAKCNTr, + FC_PORT_CUR_PAGE_CNTr, + FC_PORT_PEAK_PAGE_CNTr, + FC_PORT_EGR_PAGE_CNTr, + FC_PORT_Q_EGR_PAGE_CNT_SETr, + FC_PORT_Q_EGR_PKT_CNT_SETr, + FC_PORT_PAGE_CNT_ERRORr, + PFC_ENABLE_0r, + PFC_ENABLE_1r = 1550, + PFC_CTRL_0r, + PFC_ACTDROP_CTRLr, + P_PFC_THRr, + P_PFCOFF_THRr, + PG_HI_THRr, + PG_LO_THRr, + PG_PFCOFF_HI_THRr, + PG_PFCOFF_LO_THRr, + PG_GURANTEE_THRr, + PFC_CTRL_1r = 1560, + PFC_CTRL_2r, + PG_2_PEV_TABLEr, + DPRI_2_PG_TABLEr, + PCP_2_PG_TABLEr, + PEV_2_TXQ_TABLEr, + PFC_PORT_PG_RX_PAGE_CNTr, + + /* Congestion Avoidance */ + SC_P_CTRLr, + SC_P_ENr, + + /* Ingress Priority Decision */ + PORT_PRIr, + DOT1Q_PRI_REMAPr = 1570, + PRI_SEL_REMAP_DSCPr, + RSPAN_PRI_REMAPr, + PRI_WEIGHTr, + PORT_WEIGHT_SELr, + QID_TO_PRIr, + INCPU_PRI_REMAPr, + EXCPU_PRI_REMAPr, + PORT_PRI_DUPr, + + /* Scheduling & Queue Management */ + SCHED_PORT_Q_CTRL_SETr, + SCHED_PORT_ALGO_CTRLr = 1580, + CFG_TG_URR_SELr, + + /* Remarking */ + RMK_CTRLr, + RMK_PORT_CTRLr, + RMK_INTPRI2IPRI_CTRLr, + RMK_INTPRI2DSCP_CTRLr, + RMK_DSCP2DSCP_CTRLr, + + /* 802.1X */ + DOT1X_PORT_ENr, + DOT1X_MAC_ENr, + DOT1X_PORT_AUTHr, + DOT1X_PORT_DIRr = 1590, + DOT1X_TRAP_PRIORITYr, + DOT1X_UNAUTH_ACTr, + DOT1X_TRAP_CPU_SELr, + DOT1X_CFGr, + + /* Attack Prevention */ + ATK_PRVNT_CTRLr, + MIN_TCPHDR_LENr, + + /* WOL */ + WOL_CTRLr, + WOL_MAC0r, + WOL_MAC1r, + PHY_WOL_CTRLr = 1600, + PHY_WOL_MAC0r, + PHY_WOL_MAC1r, + + /* Parser */ + PARSER_FIELD_SELTOR_CTRLr, + PARSER_CTRLr, + PARSER_DROP_REASONr, + + /* Parser HSB */ + HSB_DATA0r, + HSB_DATA1r, + HSB_DATA2r, + HSB_DATA3r, + HSB_DATA4r = 1610, + HSB_DATA5r, + HSB_DATA6r, + HSB_DATA7r, + HSB_DATA8r, + HSB_DATA9r, + HSB_DATA10r, + HSB_DATA11r, + HSB_DATA12r, + HSB_DATA13r, + HSB_DATA14r = 1620, + HSB_DATA15r, + HSB_DATA16r, + HSB_DATA17r, + HSB_DATA18r, + HSB_DATA19r, + HSB_CTRLr, + + /* RLDP & RLPP */ + RLDP_RLPP_CTRLr, + RETRY_CTRLr, + PERIOD_CTRLr, + RLDP_TX_PMSKr = 1630, + RAND_NUM0r, + RAND_NUM1r, + MAGIC_NUM0r, + MAGIC_NUM1r, + LOOP_STATEr, + LOOPED_STATEr, + LEAVE_LOOP_STATEr, + LOOPPAIRr, + RRCP_CTRLr, + + /* Auto Recovery */ + RXPORT_DSC_STSr = 1640, + SW_Q_RST_THRr, + SW_Q_RST_P_THRr, + LD_TX_DSC_STSr, + TX_DSC_CHK_TMRr, + RXFIFO_OVERFLOW_STSr, + RXFIFO_RDEMPTY_STSr, + TXFIFO_OVERFLOW_STSr, + TXFIFO_RDEMPTY_STSr, + PINGPONG_PLUS_STSr, + TOKEN_STSr = 1650, + SW_Q_RST_CNTr, + AUTO_RECOVER_SRC_SEL_INGRESSr, + AUTO_RECOVER_SRC_SEL_EGRESSr, + AUTO_RECOVER_SRC_SEL_MAC_0r, + AUTO_RECOVER_SRC_SEL_MAC_1r, + TRIG_AUTO_RECOVER_CTRL_INGRESSr, + TRIG_AUTO_RECOVER_CTRL_EGRESSr, + TRIG_AUTO_RECOVER_CTRL_MACr, + AUTO_RECOVER_EVENT_FLAG_STS_INGRESSr, + AUTO_RECOVER_EVENT_FLAG_STS_EGRESSr = 1660, + AUTO_RECOVER_EVENT_FLAG_STS_MACr, + AUTO_RECOVER_EVENT_FLAG_ERR_INGRESSr, + AUTO_RECOVER_EVENT_FLAG_ERR_EGRESSr, + AUTO_RECOVER_EVENT_FLAG_ERR_MACr, + FIFO_FLOW_FLAG_MSKr, + + /* ECO */ + CHIP_MISC_DUMY_0r, + CHIP_MISC_DUMY_1r, + TM0_CTRL_DUMY_0r, + TM0_CTRL_DUMY_1r, + TM1_CTRL_DUMY_0r = 1670, + TM1_CTRL_DUMY_1r, + VOLT_PROB_DUMY_0r, + VOLT_PROB_DUMY_1r, + REG_IF_DUMY_0r, + REG_IF_DUMY_1r, + MIB_0_DUMY_0r, + MIB_0_DUMY_1r, + MIB_1_DUMY_0r, + MIB_1_DUMY_1r, + MIB_2_DUMY_0r = 1680, + MIB_2_DUMY_1r, + MIB_3_DUMY_0r, + MIB_3_DUMY_1r, + MIB_4_DUMY_0r, + MIB_4_DUMY_1r, + MIB_5_DUMY_0r, + MIB_5_DUMY_1r, + MIB_6_DUMY_0r, + MIB_6_DUMY_1r, + MIB_7_DUMY_0r = 1690, + MIB_7_DUMY_1r, + MIB_8_DUMY_0r, + MIB_8_DUMY_1r, + MIB_9_DUMY_0r, + MIB_9_DUMY_1r, + MIB_10_DUMY_0r, + MIB_10_DUMY_1r, + MIB_11_DUMY_0r, + MIB_11_DUMY_1r, + MIB_12_DUMY_0r = 1700, + MIB_12_DUMY_1r, + MIB_13_DUMY_0r, + MIB_13_DUMY_1r, + MIB_14_DUMY_0r, + MIB_14_DUMY_1r, + MIB_15_DUMY_0r, + MIB_15_DUMY_1r, + MIB_16_DUMY_0r, + MIB_16_DUMY_1r, + PHY_INTF_DUMY_0r = 1710, + PHY_INTF_DUMY_1r, + PHY_INTF_DUMY_2r, + PHY_INTF_DUMY_3r, + PHY_PKG_DUMY_0r, + PHY_PKG_DUMY_1r, + PHY_MISC_DUMY_0r, + PHY_MISC_DUMY_1r, + RANDOM_SEED_DUMY_0r, + RANDOM_SEED_DUMY_1r, + RANDOM_SEED_DUMY_2r = 1720, + RANDOM_SEED_DUMY_3r, + MIB_CTRL_DUMY_0r, + MIB_CTRL_DUMY_1r, + MAC_GLB_DUMY_0r, + MAC_GLB_DUMY_1r, + PER_PORT_MAC_DUMY_0r, + PER_PORT_MAC_DUMY_1r, + PER_PORT_TXQ_REG_10P_DUMY_0r, + PER_PORT_TXQ_REG_10P_DUMY_1r, + EGRESS_CTRL_DUMY_0r = 1730, + EGRESS_CTRL_DUMY_1r, + EGRESS_CTRL_DUMY_2r, + EGRESS_CTRL_DUMY_3r, + ACL_DUMY_0r, + ACL_DUMY_1r, + ACL_DUMY_2r, + ACL_DUMY_3r, + INBW_DUMY_0r, + INBW_DUMY_1r, + CVLAN_DUMY_0r = 1740, + CVLAN_DUMY_1r, + CVLAN_DUMY_2r, + CVLAN_DUMY_3r, + DPM_DUMY_0r, + DPM_DUMY_1r, + IGMP_DUMY_0r, + IGMP_DUMY_1r, + L2_DUMY_0r, + L2_DUMY_1r, + SVLAN_DUMY_0r = 1750, + SVLAN_DUMY_1r, + SVLAN_DUMY_2r, + SVLAN_DUMY_3r, + TABLE_DUMY_0r, + TABLE_DUMY_1r, + MTRPOOL_DUMY_0r, + MTRPOOL_DUMY_1r, + GLB_CTRL_DUMY_0r, + GLB_CTRL_DUMY_1r, + GLB_CTRL_DUMY_2r = 1760, + GLB_CTRL_DUMY_3r, + SMI_CTRL_DUMY_0r, + SMI_CTRL_DUMY_1r, + LED_DUMY_0r, + LED_DUMY_1r, + PKT_ENCAP_DUMY_0r, + PKT_ENCAP_DUMY_1r, + PKT_ENCAP_DUMY_2r, + PKT_ENCAP_DUMY_3r, + PKT_PARSER_DUMY_0r = 1770, + PKT_PARSER_DUMY_1r, + INGRESS_CTRL_DUMY_0r, + INGRESS_CTRL_DUMY_1r, + INGRESS_CTRL_DUMY_2r, + INGRESS_CTRL_DUMY_3r, + INGRESS_CTRL_2_DUMY_0r, + INGRESS_CTRL_2_DUMY_1r, + INGRESS_CTRL_2_DUMY_2r, + INGRESS_CTRL_2_DUMY_3r, + NIC_DUMY_0r = 1780, + NIC_DUMY_1r, + CHIP_BIST_DUMY_0r, + CHIP_BIST_DUMY_1r, + SDS_DUMY_0r, + SDS_DUMY_1r, + IO_DUMY_0r, + IO_DUMY_1r, + EFUSE_CTRL_DUMY_0r, + EFUSE_CTRL_DUMY_1r, + DBG_CTRL_DUMY_0r = 1790, + DBG_CTRL_DUMY_1r, + RATE_ADAPTER0_DUMY_0r, + RATE_ADAPTER0_DUMY_1r, + RATE_ADAPTER1_DUMY_0r, + RATE_ADAPTER1_DUMY_1r, + RATE_ADAPTER2_DUMY_0r, + RATE_ADAPTER2_DUMY_1r, + RATE_ADAPTER3_DUMY_0r, + RATE_ADAPTER3_DUMY_1r, + + REG_LIST_END = 1800 +} rtk_reg_list_t; + +typedef enum rtk_regField_list_e +{ + ACCESS_DATAf = 0, + ACC_CMDf, + ACL_BIT0_ENf, + ACL_BIT1_ENf, + ACL_BIT2_ENf, + ACL_BIT3_ENf, + ACL_WEIGHTf, + ACS_IROM_ENABLEf, + ACTf, + ACT_BIST_DONEf, + ACT_BIST_DYN_READ_ENf = 10, + ACT_BIST_FAILf, + ACT_BIST_GRP_ENf, + ACT_BIST_LOOP_ENf, + ACT_BIST_MODEf, + ACT_BIST_RSTNf, + ACT_DRF_DONEf, + ACT_DRF_FAILf, + ACT_DRF_MODEf, + ACT_DRF_PAUSEf, + ACT_DRF_RESUMEf = 20, + ACT_DVSf, + ACT_DVSEf, + ACT_LSf, + ACT_STSf, + ACT_TEST1f, + ADDRf, + ADDR_WIDTHf, + ADMIT_ARPREQf, + ADMIT_BPDUf, + ADMIT_DHCPf = 30, + ADMIT_IGMPf, + ADMIT_RMAf, + ADMIT_RTKPKTf, + AGE_TIMERf, + AGE_UNITf, + ALE_GATCLK_ENf, + ALLOW_DYN_ROTR_PMSKf, + ALLOW_LEAVEf, + ALLOW_MC_DATAf, + ALLOW_MRPf = 40, + ALLOW_PAGE_CNTf, + ALLOW_QUERYf, + ALLOW_REPORTf, + ALLPORT_MASKf, + ALL_BIST_DONEf, + ALL_DRF_BIST_DONEf, + ALWAYS_TX_CRC_RC_ENf, + AMP_FACTORf, + ANY_BIST_FAILf, + ANY_DRF_BIST_FAILf = 50, + APPLY_FREQf, + ARPf, + ARPPEf, + ASSURED_DIS_ENCAP_FEED_BACKf, + AUTO_DET_SG0_UPD_ENf, + AUTO_DET_SG1_UPD_ENf, + AUTO_DET_SG2_UPD_ENf, + AUTO_DET_SG3_UPD_ENf, + BAD_CRC_EN_0f, + BASE_PHY_ADDR_8224f = 60, + BCAM_BIST_DONEf, + BCAM_BIST_DYN_READ_ENf, + BCAM_BIST_FAILf, + BCAM_BIST_GRP_ENf, + BCAM_BIST_LOOP_ENf, + BCAM_BIST_MODEf, + BCAM_BIST_RSTNf, + BCAM_DRF_DONEf, + BCAM_DRF_FAILf, + BCAM_DRF_MODEf = 70, + BCAM_DRF_PAUSEf, + BCAM_DRF_RESUMEf, + BCAM_MDSf, + BCAM_RDSf, + BCAM_UDSf, + BC_ENf, + BDSC11_7f, + BDSC6_0f, + BHSA_BIST_DONEf, + BHSA_BIST_FAILf = 80, + BHSA_BIST_MODEf, + BHSA_BIST_RSTBf, + BHSA_DRF_BIST_DONEf, + BHSA_DRF_BIST_FAILf, + BHSA_DRF_BIST_MODEf, + BHSA_DRF_START_PAUSEf, + BHSA_SRAM_RMEf, + BHSA_SRAM_RM_3_0f, + BHSA_TEST_RESUMEf, + BISD_CLK_ENf = 90, + BISD_CLK_SELf, + BISD_DATA_OUTf, + BISD_DATA_SELf, + BIST_DIAG_MODEf, + BIST_DONE_MACSEC_SA_AEf, + BIST_DONE_MACSEC_SA_AIf, + BIST_DONE_MACSEC_STAT_AEf, + BIST_DONE_MACSEC_STAT_AIf, + BIST_DONE_RXFIFO_PG00f, + BIST_DONE_RXFIFO_PG01f = 100, + BIST_DONE_RXFIFO_PG02f, + BIST_DONE_RXFIFO_PG03f, + BIST_DONE_TXFIFO_PG00f, + BIST_DONE_TXFIFO_PG01f, + BIST_DONE_TXFIFO_PG02f, + BIST_DONE_TXFIFO_PG03f, + BIST_DRF_DONE_RXFIFO_PG00f, + BIST_DRF_DONE_RXFIFO_PG01f, + BIST_DRF_DONE_RXFIFO_PG02f, + BIST_DRF_DONE_RXFIFO_PG03f = 110, + BIST_DRF_DONE_TXFIFO_PG00f, + BIST_DRF_DONE_TXFIFO_PG01f, + BIST_DRF_DONE_TXFIFO_PG02f, + BIST_DRF_DONE_TXFIFO_PG03f, + BIST_DRF_FAIL_RXFIFO_PG00f, + BIST_DRF_FAIL_RXFIFO_PG01f, + BIST_DRF_FAIL_RXFIFO_PG02f, + BIST_DRF_FAIL_RXFIFO_PG03f, + BIST_DRF_FAIL_TXFIFO_PG00f, + BIST_DRF_FAIL_TXFIFO_PG01f = 120, + BIST_DRF_FAIL_TXFIFO_PG02f, + BIST_DRF_FAIL_TXFIFO_PG03f, + BIST_DYN_READ_EN_RXFIFO_PG00f, + BIST_DYN_READ_EN_RXFIFO_PG01f, + BIST_DYN_READ_EN_RXFIFO_PG02f, + BIST_DYN_READ_EN_RXFIFO_PG03f, + BIST_DYN_READ_EN_TXFIFO_PG00f, + BIST_DYN_READ_EN_TXFIFO_PG01f, + BIST_DYN_READ_EN_TXFIFO_PG02f, + BIST_DYN_READ_EN_TXFIFO_PG03f = 130, + BIST_FAIL_MACSEC_SA_AE0f, + BIST_FAIL_MACSEC_SA_AE1f, + BIST_FAIL_MACSEC_SA_AE2f, + BIST_FAIL_MACSEC_SA_AE3f, + BIST_FAIL_MACSEC_SA_AI0f, + BIST_FAIL_MACSEC_SA_AI1f, + BIST_FAIL_MACSEC_SA_AI2f, + BIST_FAIL_MACSEC_SA_AI3f, + BIST_FAIL_MACSEC_STAT_AEf, + BIST_FAIL_MACSEC_STAT_AIf = 140, + BIST_FAIL_RXFIFO_PG00f, + BIST_FAIL_RXFIFO_PG01f, + BIST_FAIL_RXFIFO_PG02f, + BIST_FAIL_RXFIFO_PG03f, + BIST_FAIL_TXFIFO_PG00f, + BIST_FAIL_TXFIFO_PG01f, + BIST_FAIL_TXFIFO_PG02f, + BIST_FAIL_TXFIFO_PG03f, + BIST_LOOP_MODE_MACSEC_SA_AEf, + BIST_LOOP_MODE_MACSEC_SA_AIf = 150, + BIST_LOOP_MODE_MACSEC_STAT_AEf, + BIST_LOOP_MODE_MACSEC_STAT_AIf, + BIST_LOOP_MODE_RXFIFO_PG00f, + BIST_LOOP_MODE_RXFIFO_PG01f, + BIST_LOOP_MODE_RXFIFO_PG02f, + BIST_LOOP_MODE_RXFIFO_PG03f, + BIST_LOOP_MODE_TXFIFO_PG00f, + BIST_LOOP_MODE_TXFIFO_PG01f, + BIST_LOOP_MODE_TXFIFO_PG02f, + BIST_LOOP_MODE_TXFIFO_PG03f = 160, + BIST_MODE_MACSEC_SA_AEf, + BIST_MODE_MACSEC_SA_AIf, + BIST_MODE_MACSEC_STAT_AEf, + BIST_MODE_MACSEC_STAT_AIf, + BIST_MODE_RXFIFO_PG00f, + BIST_MODE_RXFIFO_PG01f, + BIST_MODE_RXFIFO_PG02f, + BIST_MODE_RXFIFO_PG03f, + BIST_MODE_TXFIFO_PG00f, + BIST_MODE_TXFIFO_PG01f = 170, + BIST_MODE_TXFIFO_PG02f, + BIST_MODE_TXFIFO_PG03f, + BIST_RSTN_MACSEC_SA_AEf, + BIST_RSTN_MACSEC_SA_AIf, + BIST_RSTN_MACSEC_STAT_AEf, + BIST_RSTN_MACSEC_STAT_AIf, + BIST_RSTN_RXFIFO_PG00f, + BIST_RSTN_RXFIFO_PG01f, + BIST_RSTN_RXFIFO_PG02f, + BIST_RSTN_RXFIFO_PG03f = 180, + BIST_RSTN_TXFIFO_PG00f, + BIST_RSTN_TXFIFO_PG01f, + BIST_RSTN_TXFIFO_PG02f, + BIST_RSTN_TXFIFO_PG03f, + BKOFF_SELf, + BKOFF_SPDUPf, + BKPRES_ENf, + BKPRES_MTHD_SELf, + BLATf, + BLINK_TIME_SELf = 190, + BOND_INFO_ROf, + BO_CHIP_MODE_ROf, + BURSTf, + BURST_CNTf, + BURST_CNT_DBGf, + BURST_SIZEf, + BW_ENf, + BYPASS_ABLTY_LOCKf, + BYPASS_ACT_HITf, + BYPASS_CTRL_BITf = 200, + BYPASS_DATA_BYTEf, + BYPASS_PG_AD0_11_0f, + BYPASS_PG_AD1_11_0f, + BYPASS_PG_AD2_11_0f, + BYPASS_PG_VLD_2_0f, + BYPASS_RULE_IDXf, + BYPS_CHK_INIf, + BYP_TX_CRCf, + BYTE_TO_BYTE_DLYf, + CBUF_BIST_DONEf = 210, + CBUF_BIST_FAILf, + CBUF_DRF_BIST_DONEf, + CBUF_DRF_BIST_FAILf, + CBUF_DRF_START_PAUSEf, + CFG_312P5_CLK_SELf, + CFG_BISR_MODEf, + CFG_BISR_SERIALf, + CFG_BYPASS_PG_AD0_11_0f, + CFG_BYPASS_PG_AD1_11_0f, + CFG_BYPASS_PG_AD2_11_0f = 220, + CFG_BYPASS_PG_VLD_2_0f, + CFG_BYP_PHY_LDNf, + CFG_BYP_SDS_LDNf, + CFG_CBUF_BIST_GRP_ENf, + CFG_CBUF_BIST_LOOP_MODEf, + CFG_CBUF_BIST_MODEf, + CFG_CBUF_BIST_RSTBf, + CFG_CBUF_BIST_TEST1f, + CFG_CBUF_DRF_BIST_DYN_RD_ENf, + CFG_CBUF_DRF_BIST_MODEf = 230, + CFG_CBUF_DRF_TEST_RESUMEf, + CFG_CBUF_SRAM_RMf, + CFG_CBUF_SRAM_RMEf, + CFG_CKR_SEL0f, + CFG_CKR_SEL1f, + CFG_CKR_SEL2f, + CFG_CKR_SEL3f, + CFG_CLKOUT_ENf, + CFG_CLKOUT_HALF_PERIOD_FS_Hf, + CFG_CLKOUT_HALF_PERIOD_FS_Lf = 240, + CFG_CLKOUT_HALF_PERIOD_NS_Hf, + CFG_CLKOUT_HALF_PERIOD_NS_Lf, + CFG_CLKOUT_HALF_PERIOD_RSVf, + CFG_CLKOUT_RSVf, + CFG_CLK_CH_SEL0f, + CFG_CLK_CH_SEL1f, + CFG_CLK_CH_SEL2f, + CFG_CLK_CH_SEL3f, + CFG_CLK_RSVf, + CFG_CLK_SRCf = 250, + CFG_CLR_FIFO_OVTHRf, + CFG_CUBF_SRAM_LSf, + CFG_DATA_HOLD_TIME_1f, + CFG_DBG_SEL_INSTf, + CFG_DBG_SEL_MODEf, + CFG_DBG_SEL_PTPf, + CFG_DMY_0f, + CFG_DMY_1f, + CFG_DROP_FIFO_BIST_LOOP_MODEf, + CFG_DROP_FIFO_BIST_MODEf = 260, + CFG_DROP_FIFO_BIST_RSTBf, + CFG_DROP_FIFO_BIST_TEST1f, + CFG_DROP_FIFO_DRF_BIST_DYN_RD_ENf, + CFG_DROP_FIFO_DRF_BIST_MODEf, + CFG_DROP_FIFO_DRF_TEST_RESUMEf, + CFG_DROP_FIFO_SRAM_LSf, + CFG_DROP_FIFO_SRAM_RMf, + CFG_DROP_FIFO_SRAM_RMEf, + CFG_DUR_SPDUPf, + CFG_EEE_DELETEf = 270, + CFG_EN_8051f, + CFG_EN_ICG_SEL0f, + CFG_EN_ICG_SEL1f, + CFG_ERROR_ONf, + CFG_FAIL_AD_ENf, + CFG_FAULT_ONf, + CFG_FB_ONf, + CFG_FIFO_START_FBf, + CFG_FIFO_START_SEQf, + CFG_G2G_AFE_IPG_CNTf = 280, + CFG_G2G_AFO_IPGCOMPf, + CFG_G2G_BGPTR_CHKf, + CFG_G2G_DIS_AUTO_RST_FIFOf, + CFG_G2G_EDPTR_CHKf, + CFG_G2G_WATER_LEVEL_FDf, + CFG_G2G_WATER_LEVEL_X2Yf, + CFG_G2G_WATER_LEVEL_Y2Xf, + CFG_GPI_FALL_TRIGf, + CFG_GPI_OPf, + CFG_GPI_RISE_TRIGf = 290, + CFG_GPI_RSV_15_7f, + CFG_GPI_RSV_1_0f, + CFG_G_EEE_LPI_RX_DLY_ENf, + CFG_G_EEE_LPI_RX_SHIFTf, + CFG_IDLE_MODE0f, + CFG_IDLE_MODE1f, + CFG_IDLE_OUT_SEL0f, + CFG_IDLE_OUT_SEL1f, + CFG_IMR_PPS_If, + CFG_IMR_PTPf = 300, + CFG_LDN_CLR_FIFO_FRC_ONf, + CFG_LDN_CLR_FIFO_FRC_VALf, + CFG_LDN_CLR_FIFO_RXf, + CFG_LDN_CLR_FIFO_TXf, + CFG_LL_BIST_LOOP_MODEf, + CFG_LL_BIST_MODEf, + CFG_LL_BIST_RSTBf, + CFG_LL_BIST_TEST1f, + CFG_LL_DRF_BIST_DYN_RD_ENf, + CFG_LL_DRF_BIST_MODEf = 310, + CFG_LL_DRF_TEST_RESUMEf, + CFG_LL_SRAM_LSf, + CFG_LL_SRAM_RMf, + CFG_LL_SRAM_RMEf, + CFG_LOCK_SEL0f, + CFG_LOCK_SEL1f, + CFG_LOOKUP_HIT_ISO_ACTf, + CFG_MAC3_8221Bf, + CFG_MAC8_8221Bf, + CFG_MDIO_DRV_PADf = 320, + CFG_MDY_G_EEE_LPI_RXf, + CFG_MDY_XG_EEE_LPI_TXf, + CFG_MIB_ENf, + CFG_MULTI_GPHY_MDC_DEGLITCH_EN_8224f, + CFG_MULTI_GPHY_MDIO_DLY_8224f, + CFG_P0_CUR_IPGf, + CFG_P0_CUR_PRMBf, + CFG_P0_CUR_THRf, + CFG_P0_DBG_INFO_OFFf, + CFG_P0_MAX_IPGf = 330, + CFG_P0_MAX_PRMBf, + CFG_P0_MAX_THRf, + CFG_P0_MIN_IPGf, + CFG_P0_MIN_PRMBf, + CFG_P1_CUR_IPGf, + CFG_P1_CUR_PRMBf, + CFG_P1_CUR_THRf, + CFG_P1_DBG_INFO_OFFf, + CFG_P1_MAX_IPGf, + CFG_P1_MAX_PRMBf = 340, + CFG_P1_MAX_THRf, + CFG_P1_MIN_IPGf, + CFG_P1_MIN_PRMBf, + CFG_P2_CUR_IPGf, + CFG_P2_CUR_PRMBf, + CFG_P2_CUR_THRf, + CFG_P2_DBG_INFO_OFFf, + CFG_P2_MAX_IPGf, + CFG_P2_MAX_PRMBf, + CFG_P2_MAX_THRf = 350, + CFG_P2_MIN_IPGf, + CFG_P2_MIN_PRMBf, + CFG_P3_CUR_IPGf, + CFG_P3_CUR_PRMBf, + CFG_P3_CUR_THRf, + CFG_P3_DBG_INFO_OFFf, + CFG_P3_MAX_IPGf, + CFG_P3_MAX_PRMBf, + CFG_P3_MAX_THRf, + CFG_P3_MIN_IPGf = 360, + CFG_P3_MIN_PRMBf, + CFG_PAD_LED0_ACTIVE_LOWf, + CFG_PAD_LED0_MUXf, + CFG_PAD_LED10_ACTIVE_LOWf, + CFG_PAD_LED10_MUXf, + CFG_PAD_LED11_ACTIVE_LOWf, + CFG_PAD_LED11_MUXf, + CFG_PAD_LED12_ACTIVE_LOWf, + CFG_PAD_LED12_MUXf, + CFG_PAD_LED13_ACTIVE_LOWf = 370, + CFG_PAD_LED13_MUXf, + CFG_PAD_LED14_ACTIVE_LOWf, + CFG_PAD_LED14_MUXf, + CFG_PAD_LED15_ACTIVE_LOWf, + CFG_PAD_LED15_MUXf, + CFG_PAD_LED16_ACTIVE_LOWf, + CFG_PAD_LED16_MUXf, + CFG_PAD_LED17_ACTIVE_LOWf, + CFG_PAD_LED17_MUXf, + CFG_PAD_LED18_ACTIVE_LOWf = 380, + CFG_PAD_LED18_MUXf, + CFG_PAD_LED19_ACTIVE_LOWf, + CFG_PAD_LED19_MUXf, + CFG_PAD_LED1_ACTIVE_LOWf, + CFG_PAD_LED1_MUXf, + CFG_PAD_LED20_ACTIVE_LOWf, + CFG_PAD_LED20_MUXf, + CFG_PAD_LED21_ACTIVE_LOWf, + CFG_PAD_LED21_MUXf, + CFG_PAD_LED22_ACTIVE_LOWf = 390, + CFG_PAD_LED22_MUXf, + CFG_PAD_LED23_ACTIVE_LOWf, + CFG_PAD_LED23_MUXf, + CFG_PAD_LED24_ACTIVE_LOWf, + CFG_PAD_LED24_MUXf, + CFG_PAD_LED25_ACTIVE_LOWf, + CFG_PAD_LED25_MUXf, + CFG_PAD_LED26_ACTIVE_LOWf, + CFG_PAD_LED26_MUXf, + CFG_PAD_LED27_ACTIVE_LOWf = 400, + CFG_PAD_LED27_MUXf, + CFG_PAD_LED28_ACTIVE_LOWf, + CFG_PAD_LED29_ACTIVE_LOWf, + CFG_PAD_LED2_ACTIVE_LOWf, + CFG_PAD_LED2_MUXf, + CFG_PAD_LED3_ACTIVE_LOWf, + CFG_PAD_LED3_MUXf, + CFG_PAD_LED4_ACTIVE_LOWf, + CFG_PAD_LED4_MUXf, + CFG_PAD_LED5_ACTIVE_LOWf = 410, + CFG_PAD_LED5_MUXf, + CFG_PAD_LED6_ACTIVE_LOWf, + CFG_PAD_LED6_MUXf, + CFG_PAD_LED7_ACTIVE_LOWf, + CFG_PAD_LED7_MUXf, + CFG_PAD_LED8_ACTIVE_LOWf, + CFG_PAD_LED8_MUXf, + CFG_PAD_LED9_ACTIVE_LOWf, + CFG_PAD_LED9_MUXf, + CFG_PARA_LED0_IO_ENf = 420, + CFG_PARA_LED10_IO_ENf, + CFG_PARA_LED11_IO_ENf, + CFG_PARA_LED12_IO_ENf, + CFG_PARA_LED13_IO_ENf, + CFG_PARA_LED14_IO_ENf, + CFG_PARA_LED15_IO_ENf, + CFG_PARA_LED16_IO_ENf, + CFG_PARA_LED17_IO_ENf, + CFG_PARA_LED18_IO_ENf, + CFG_PARA_LED19_IO_ENf = 430, + CFG_PARA_LED1_IO_ENf, + CFG_PARA_LED20_IO_ENf, + CFG_PARA_LED21_IO_ENf, + CFG_PARA_LED22_IO_ENf, + CFG_PARA_LED23_IO_ENf, + CFG_PARA_LED24_IO_ENf, + CFG_PARA_LED25_IO_ENf, + CFG_PARA_LED26_IO_ENf, + CFG_PARA_LED27_IO_ENf, + CFG_PARA_LED28_IO_ENf = 440, + CFG_PARA_LED29_IO_ENf, + CFG_PARA_LED2_IO_ENf, + CFG_PARA_LED3_IO_ENf, + CFG_PARA_LED4_IO_ENf, + CFG_PARA_LED5_IO_ENf, + CFG_PARA_LED6_IO_ENf, + CFG_PARA_LED7_IO_ENf, + CFG_PARA_LED8_IO_ENf, + CFG_PARA_LED9_IO_ENf, + CFG_PHY_MODEL_NOf = 450, + CFG_PHY_OUI_BIT19_BIT24f, + CFG_PHY_OUI_BIT3_BIT18f, + CFG_PHY_REVISION_NUMf, + CFG_PKB_BIST_GRP_EN_2_0f, + CFG_PKB_BIST_LOOP_MODE_2_0f, + CFG_PKB_BIST_MODE_2_0f, + CFG_PKB_BIST_RSTB_2_0f, + CFG_PKB_BIST_TEST1_2_0f, + CFG_PKB_DRF_BIST_DYN_RD_EN_2_0f, + CFG_PKB_DRF_BIST_MODE_2_0f = 460, + CFG_PKB_DRF_BIST_TEST_RESUME_2_0f, + CFG_PKB_SRAM_LS_2_0f, + CFG_PKB_SRAM_RME_2_0f, + CFG_PKB_SRAM_RM_2_0f, + CFG_PN_CUR_IPGf, + CFG_PN_CUR_PRMBf, + CFG_PN_CUR_THRf, + CFG_PN_DBG_INFO_OFFf, + CFG_PN_FRAG_FLTf, + CFG_PN_MAX_IPGf = 470, + CFG_PN_MAX_PRMBf, + CFG_PN_MAX_THRf, + CFG_PN_MIN_IPGf, + CFG_PN_MIN_PRMBf, + CFG_PORT_L_LPBKf, + CFG_PPS_ENf, + CFG_PPS_RSVf, + CFG_PPS_WIDTHf, + CFG_PRMB_6BYTE_MODEf, + CFG_PRMB_RCVY_ENf = 480, + CFG_PRMB_SUPPf, + CFG_PRMB_SUPP_8224f, + CFG_PTP_TIME_FREQ0f, + CFG_PTP_TIME_FREQ1f, + CFG_PTP_TIME_NSEC_Hf, + CFG_PTP_TIME_NSEC_Lf, + CFG_PTP_TIME_SEC_Hf, + CFG_PTP_TIME_SEC_Lf, + CFG_PTP_TIME_SEC_Mf, + CFG_PULSE_MODEf = 490, + CFG_PULSE_RSVf, + CFG_REC_LINK_INTRf, + CFG_RSC_FIFO_BIST_LOOP_MODEf, + CFG_RSC_FIFO_BIST_MODEf, + CFG_RSC_FIFO_BIST_RSTBf, + CFG_RSC_FIFO_BIST_TEST1f, + CFG_RSC_FIFO_DRF_BIST_DYN_RD_ENf, + CFG_RSC_FIFO_DRF_BIST_MODEf, + CFG_RSC_FIFO_DRF_TEST_RESUMEf, + CFG_RSC_FIFO_SRAM_LSf = 500, + CFG_RSC_FIFO_SRAM_RMf, + CFG_RSC_FIFO_SRAM_RMEf, + CFG_RXFIFO_LS_PG00f, + CFG_RXFIFO_LS_PG01f, + CFG_RXFIFO_LS_PG02f, + CFG_RXFIFO_LS_PG03f, + CFG_RXFIFO_RMA_0_PG00f, + CFG_RXFIFO_RMA_0_PG01f, + CFG_RXFIFO_RMA_0_PG02f, + CFG_RXFIFO_RMA_0_PG03f = 510, + CFG_RXFIFO_RMA_1_PG00f, + CFG_RXFIFO_RMA_1_PG01f, + CFG_RXFIFO_RMA_1_PG02f, + CFG_RXFIFO_RMA_1_PG03f, + CFG_RXFIFO_RMA_2_PG00f, + CFG_RXFIFO_RMA_2_PG01f, + CFG_RXFIFO_RMA_2_PG02f, + CFG_RXFIFO_RMA_3_PG00f, + CFG_RXFIFO_RMA_3_PG01f, + CFG_RXFIFO_RMA_3_PG02f = 520, + CFG_RXFIFO_RMA_4_PG00f, + CFG_RXFIFO_RMA_4_PG01f, + CFG_RXFIFO_RMA_4_PG02f, + CFG_RXFIFO_RMA_5_PG00f, + CFG_RXFIFO_RMA_5_PG01f, + CFG_RXFIFO_RMA_5_PG02f, + CFG_RXFIFO_RMA_6_PG00f, + CFG_RXFIFO_RMA_6_PG01f, + CFG_RXFIFO_RMA_7_PG00f, + CFG_RXFIFO_RMA_7_PG01f = 530, + CFG_RXFIFO_RMB_0_PG00f, + CFG_RXFIFO_RMB_0_PG01f, + CFG_RXFIFO_RMB_0_PG02f, + CFG_RXFIFO_RMB_0_PG03f, + CFG_RXFIFO_RMB_1_PG00f, + CFG_RXFIFO_RMB_1_PG01f, + CFG_RXFIFO_RMB_1_PG02f, + CFG_RXFIFO_RMB_1_PG03f, + CFG_RXFIFO_RMB_2_PG00f, + CFG_RXFIFO_RMB_2_PG01f = 540, + CFG_RXFIFO_RMB_2_PG02f, + CFG_RXFIFO_RMB_3_PG00f, + CFG_RXFIFO_RMB_3_PG01f, + CFG_RXFIFO_RMB_3_PG02f, + CFG_RXFIFO_RMB_4_PG00f, + CFG_RXFIFO_RMB_4_PG01f, + CFG_RXFIFO_RMB_4_PG02f, + CFG_RXFIFO_RMB_5_PG00f, + CFG_RXFIFO_RMB_5_PG01f, + CFG_RXFIFO_RMB_5_PG02f = 550, + CFG_RXFIFO_RMB_6_PG00f, + CFG_RXFIFO_RMB_6_PG01f, + CFG_RXFIFO_RMB_7_PG00f, + CFG_RXFIFO_RMB_7_PG01f, + CFG_RXFIFO_RMEA_PG00f, + CFG_RXFIFO_RMEA_PG01f, + CFG_RXFIFO_RMEA_PG02f, + CFG_RXFIFO_RMEA_PG03f, + CFG_RXFIFO_RMEB_PG00f, + CFG_RXFIFO_RMEB_PG01f = 560, + CFG_RXFIFO_RMEB_PG02f, + CFG_RXFIFO_RMEB_PG03f, + CFG_RX_RXDV_CNTf, + CFG_SCK_I_DLY_1f, + CFG_SDA_DLYf, + CFG_SDSREG_BCST_ONf, + CFG_SDS_BCST_IDXf, + CFG_SEQ_RSV_ONf, + CFG_SHORT_PRMBf, + CFG_SLV_EDGE_SELf = 570, + CFG_SLV_MDIO_DLYf, + CFG_STK_PORT_P0f, + CFG_SYNC_OUT_SEL0f, + CFG_SYNC_OUT_SEL1f, + CFG_TA_CHK_ENf, + CFG_TA_CHK_EN_8224f, + CFG_TG_URR_SELf, + CFG_TOD_VALIDf, + CFG_TOP_MDC_DEGLITCH_EN_8224f, + CFG_TOP_MDIO_DLY_8224f = 580, + CFG_TXFIFO_LS_PG00f, + CFG_TXFIFO_LS_PG01f, + CFG_TXFIFO_LS_PG02f, + CFG_TXFIFO_LS_PG03f, + CFG_TXFIFO_RMA_0_PG00f, + CFG_TXFIFO_RMA_0_PG01f, + CFG_TXFIFO_RMA_0_PG02f, + CFG_TXFIFO_RMA_0_PG03f, + CFG_TXFIFO_RMA_1_PG00f, + CFG_TXFIFO_RMA_1_PG01f = 590, + CFG_TXFIFO_RMA_1_PG02f, + CFG_TXFIFO_RMA_2_PG00f, + CFG_TXFIFO_RMA_2_PG01f, + CFG_TXFIFO_RMA_2_PG02f, + CFG_TXFIFO_RMA_3_PG00f, + CFG_TXFIFO_RMA_3_PG01f, + CFG_TXFIFO_RMA_3_PG02f, + CFG_TXFIFO_RMA_4_PG00f, + CFG_TXFIFO_RMA_4_PG02f, + CFG_TXFIFO_RMA_5_PG00f = 600, + CFG_TXFIFO_RMA_5_PG02f, + CFG_TXFIFO_RMB_0_PG00f, + CFG_TXFIFO_RMB_0_PG01f, + CFG_TXFIFO_RMB_0_PG02f, + CFG_TXFIFO_RMB_0_PG03f, + CFG_TXFIFO_RMB_1_PG00f, + CFG_TXFIFO_RMB_1_PG01f, + CFG_TXFIFO_RMB_1_PG02f, + CFG_TXFIFO_RMB_2_PG00f, + CFG_TXFIFO_RMB_2_PG01f = 610, + CFG_TXFIFO_RMB_2_PG02f, + CFG_TXFIFO_RMB_3_PG00f, + CFG_TXFIFO_RMB_3_PG01f, + CFG_TXFIFO_RMB_3_PG02f, + CFG_TXFIFO_RMB_4_PG00f, + CFG_TXFIFO_RMB_4_PG02f, + CFG_TXFIFO_RMB_5_PG00f, + CFG_TXFIFO_RMB_5_PG02f, + CFG_TXFIFO_RMEA_PG00f, + CFG_TXFIFO_RMEA_PG01f = 620, + CFG_TXFIFO_RMEA_PG02f, + CFG_TXFIFO_RMEA_PG03f, + CFG_TXFIFO_RMEB_PG00f, + CFG_TXFIFO_RMEB_PG01f, + CFG_TXFIFO_RMEB_PG02f, + CFG_TXFIFO_RMEB_PG03f, + CFG_UNIDIR_EN_TGXR0f, + CFG_WAIT_SCK_MODE_1f, + CFG_WATER_LEVEL_Hf, + CFG_WATER_LEVEL_Lf = 630, + CFG_WATER_LEVEL_STf, + CFG_XG2XG_FAULT_ONf, + CFG_XG_EEE_LPI_TX_DLY_ENf, + CFG_XG_EEE_LPI_TX_SHIFTf, + CFIf, + CGF_G2G_LPBKf, + CHECK1_MMD_DEVADf, + CHECK1_MMD_REGf, + CHECK2_MMD_DEVADf, + CHECK2_MMD_REGf = 640, + CHECK3_MMD_DEVADf, + CHECK3_MMD_REGf, + CHECK4_MMD_DEVADf, + CHECK4_MMD_REGf, + CHECK5_MMD_DEVADf, + CHECK5_MMD_REGf, + CHG_DUP_THRf, + CHIP_INFO_ENf, + CHIP_LOT_NO_CRCf, + CHIP_LOT_NO_REG0f = 650, + CHIP_LOT_NO_REG1f, + CHIP_UUIDf, + CHK1_DATA_10Gf, + CHK1_DMSK_10Gf, + CHK1_MODE_10Gf, + CHK1_PMSKf, + CHK1_RESULTf, + CHK2_DATA_10Gf, + CHK2_DMSK_10Gf, + CHK2_MODE_10Gf = 660, + CHK2_PMSKf, + CHK2_RESULTf, + CHK3_DATA_10Gf, + CHK3_DMSK_10Gf, + CHK3_MODE_10Gf, + CHK3_PMSKf, + CHK3_RESULTf, + CHK4_DATA_10Gf, + CHK4_DMSK_10Gf, + CHK4_MODE_10Gf = 670, + CHK4_PMSKf, + CHK4_RESULTf, + CHK5_DATA_10Gf, + CHK5_DMSK_10Gf, + CHK5_MODE_10Gf, + CHK5_PMSKf, + CHK5_RESULTf, + CHK_ACK_DLYf, + CKEEP_00f, + CKEEP_01f = 680, + CKEEP_02f, + CKEEP_03f, + CKEEP_04f, + CKEEP_08f, + CKEEP_0Df, + CKEEP_0Ef, + CKEEP_10f, + CKEEP_11f, + CKEEP_12f, + CKEEP_13f = 690, + CKEEP_18f, + CKEEP_1Af, + CKEEP_20f, + CKEEP_21f, + CKEEP_22f, + CKEEP_CDPf, + CKEEP_CSSTPf, + CKEEP_LLDPf, + CKS_ERR_OPf, + CLKOUT_PTP_RSVf = 700, + CLKOUT_PTP_TIME_NSEC_Hf, + CLKOUT_PTP_TIME_NSEC_Lf, + CLKOUT_PTP_TIME_SEC_Hf, + CLKOUT_PTP_TIME_SEC_Lf, + CLKOUT_PTP_TIME_SEC_Mf, + CLOCK_SWITCHf, + CLR_G2G_FIFOf, + CMDf, + CMD0_ADRf, + CMD0_INVf = 710, + CMD0_WDATf, + CMD1_ADRf, + CMD1_INVf, + CMD1_WDATf, + CMD2_ADRf, + CMD2_INVf, + CMD2_WDATf, + CMD3_ADRf, + CMD3_INVf, + CMD3_WDATf = 720, + CMD_PRDf, + CMD_RD_ENf, + CMD_WRMSK_ENf, + CMD_WR_ENf, + CNGST_SUST_TMR_LMTf, + CNGST_SUST_TMR_LMT_Hf, + CNGST_TMRf, + CNGST_TMR_Hf, + CNTf, + CNTR_VALf = 730, + CNT_RSTf, + CNT_SET0_LEN_MAXf, + CNT_SET0_LEN_MINf, + CNT_SET1_LEN_MAXf, + CNT_SET1_LEN_MINf, + COL_10Mf, + COL_CUR_CNTf, + COMP_IDf, + CONSTRT_NUMf, + CPUIDL_ENRf = 740, + CPUIDL_EXTf, + CPUTAG16_0f, + CPUTAG31_17f, + CPUTAG_IFf, + CPU_PMSKf, + CRC_CPU_RC_ENf, + CTAGf, + CTAG_ACCEPT_TYPEf, + CTAG_IFf, + CUR_PTP_TIME_FREQ0f = 750, + CUR_PTP_TIME_FREQ1f, + CVIDf, + CVLAN_ACT_HITf, + CVLAN_BIST_DONEf, + CVLAN_BIST_DYN_READ_ENf, + CVLAN_BIST_FAILf, + CVLAN_BIST_GRP_ENf, + CVLAN_BIST_LOOP_ENf, + CVLAN_BIST_MODEf, + CVLAN_BIST_RSTNf = 760, + CVLAN_CTRL_BITf, + CVLAN_DRF_DONEf, + CVLAN_DRF_FAILf, + CVLAN_DRF_MODEf, + CVLAN_DRF_PAUSEf, + CVLAN_DRF_RESUMEf, + CVLAN_DVSf, + CVLAN_DVSEf, + CVLAN_FILTERf, + CVLAN_LSf = 770, + CVLAN_RULE_IDXf, + CVLAN_TEST1f, + DAEQSAf, + DATAf, + DATA_15_0f, + DATA_BITf, + DATA_WIDTHf, + DBGO_RST_0f, + DBGO_RST_1f, + DBG_ACC_PKB_ENf = 780, + DBG_ADR0f, + DBG_ADR1f, + DBG_ADR2f, + DBG_ADR3f, + DBG_BIT_SEL0f, + DBG_BIT_SEL1f, + DBG_BIT_SEL2f, + DBG_BIT_SEL3f, + DBG_BLK_SEL0f, + DBG_BLK_SEL1f = 790, + DBG_BLK_SEL2f, + DBG_BLK_SEL3f, + DBG_ENf, + DBG_OUTf, + DBG_PAD_CTRLf, + DBG_SELf, + DBG_SHIFTf, + DBG_SHIFT_SEL0f, + DBG_SHIFT_SEL1f, + DBG_SHIFT_SEL2f = 800, + DBG_SHIFT_SEL3f, + DBG_SPD_SELf, + DCO_CLK_SRCf, + DEFER_IPG_SELf, + DEFER_PKT_CONT_SELf, + DEV_ADDRf, + DEV_PRESENTf, + DFLT_PLTYf, + DIPf, + DIP16_0f = 810, + DIP31_17f, + DIS_AGEf, + DIS_STORM_CTRL_00f, + DIS_STORM_CTRL_01f, + DIS_STORM_CTRL_02f, + DIS_STORM_CTRL_03f, + DIS_STORM_CTRL_04f, + DIS_STORM_CTRL_08f, + DIS_STORM_CTRL_0Df, + DIS_STORM_CTRL_0Ef = 820, + DIS_STORM_CTRL_10f, + DIS_STORM_CTRL_11f, + DIS_STORM_CTRL_12f, + DIS_STORM_CTRL_13f, + DIS_STORM_CTRL_18f, + DIS_STORM_CTRL_1Af, + DIS_STORM_CTRL_20f, + DIS_STORM_CTRL_21f, + DIS_STORM_CTRL_22f, + DIS_STORM_CTRL_CDPf = 830, + DIS_STORM_CTRL_CSSTPf, + DIS_STORM_CTRL_LLDPf, + DIVISOR_LATCH_VAL_BIT15_0f, + DIVISOR_LATCH_VAL_BIT16f, + DMAC17_0f, + DMAC47_18f, + DOT1Q_WEIGHTf, + DOUT_CURRENTf, + DOWN2UP_DLY_ENf, + DPC_BIST_DONEf = 840, + DPC_BIST_FAILf, + DPC_BIST_LOOPf, + DPC_BIST_MODEf, + DPC_BIST_RSTBf, + DPC_DRF_BIST_DONEf, + DPC_DRF_BIST_FAILf, + DPC_DRF_BIST_MODEf, + DPC_DRF_START_PAUSEf, + DPC_DRF_TEST_RESUMEf, + DPC_DYN_READf = 850, + DPC_LSf, + DPC_SRAM_RMEf, + DPC_SRAM_RM_3_0f, + DPC_TEST1f, + DPRI0_PG_MAPf, + DPRI1_PG_MAPf, + DPRI2_PG_MAPf, + DPRI3_PG_MAPf, + DPRI4_PG_MAPf, + DPRI5_PG_MAPf = 860, + DPRI6_PG_MAPf, + DPRI7_PG_MAPf, + DRAIN_OUT_THRf, + DRAIN_OUT_THR_Hf, + DRF_BIST_DONE_MACSEC_SA_AEf, + DRF_BIST_DONE_MACSEC_SA_AIf, + DRF_BIST_DONE_MACSEC_STAT_AEf, + DRF_BIST_DONE_MACSEC_STAT_AIf, + DRF_BIST_FAIL_MACSEC_SA_AE0f, + DRF_BIST_FAIL_MACSEC_SA_AE1f = 870, + DRF_BIST_FAIL_MACSEC_SA_AE2f, + DRF_BIST_FAIL_MACSEC_SA_AE3f, + DRF_BIST_FAIL_MACSEC_SA_AI0f, + DRF_BIST_FAIL_MACSEC_SA_AI1f, + DRF_BIST_FAIL_MACSEC_SA_AI2f, + DRF_BIST_FAIL_MACSEC_SA_AI3f, + DRF_BIST_FAIL_MACSEC_STAT_AEf, + DRF_BIST_FAIL_MACSEC_STAT_AIf, + DRF_BIST_MODE_MACSEC_SA_AEf, + DRF_BIST_MODE_MACSEC_SA_AIf = 880, + DRF_BIST_MODE_MACSEC_STAT_AEf, + DRF_BIST_MODE_MACSEC_STAT_AIf, + DRF_BIST_MODE_RXFIFO_PG00f, + DRF_BIST_MODE_RXFIFO_PG01f, + DRF_BIST_MODE_RXFIFO_PG02f, + DRF_BIST_MODE_RXFIFO_PG03f, + DRF_BIST_MODE_TXFIFO_PG00f, + DRF_BIST_MODE_TXFIFO_PG01f, + DRF_BIST_MODE_TXFIFO_PG02f, + DRF_BIST_MODE_TXFIFO_PG03f = 890, + DRF_START_PAUSE_MACSEC_SA_AEf, + DRF_START_PAUSE_MACSEC_SA_AIf, + DRF_START_PAUSE_MACSEC_STAT_AEf, + DRF_START_PAUSE_MACSEC_STAT_AIf, + DRF_START_PAUSE_RXFIFO_PG00f, + DRF_START_PAUSE_RXFIFO_PG01f, + DRF_START_PAUSE_RXFIFO_PG02f, + DRF_START_PAUSE_RXFIFO_PG03f, + DRF_START_PAUSE_TXFIFO_PG00f, + DRF_START_PAUSE_TXFIFO_PG01f = 900, + DRF_START_PAUSE_TXFIFO_PG02f, + DRF_START_PAUSE_TXFIFO_PG03f, + DRF_TESS_RESUME_MACSEC_SA_AEf, + DRF_TESS_RESUME_MACSEC_SA_AIf, + DRF_TESS_RESUME_MACSEC_STAT_AEf, + DRF_TESS_RESUME_MACSEC_STAT_AIf, + DRF_TEST_RESUME_RXFIFO_PG00f, + DRF_TEST_RESUME_RXFIFO_PG01f, + DRF_TEST_RESUME_RXFIFO_PG02f, + DRF_TEST_RESUME_RXFIFO_PG03f = 910, + DRF_TEST_RESUME_TXFIFO_PG00f, + DRF_TEST_RESUME_TXFIFO_PG01f, + DRF_TEST_RESUME_TXFIFO_PG02f, + DRF_TEST_RESUME_TXFIFO_PG03f, + DROP_ALLf, + DROP_FIFO_BIST_DONEf, + DROP_FIFO_BIST_FAILf, + DROP_FIFO_DRF_BIST_DONEf, + DROP_FIFO_DRF_BIST_FAILf, + DROP_FIFO_DRF_START_PAUSEf = 920, + DROP_LEAVE_ZEROf, + DROP_THRf, + DRV_ACK_DLYf, + DSCPf, + DSCP_RMK_ENf, + DSCP_RMK_SRCf, + DSCP_WEIGHTf, + DUMMYf, + DUMMY_REG0_NICf, + DUMMY_REG1_NICf = 930, + DUMMY_REGISTERf, + DUMY_TM0_CTRL0f, + DUMY_TM0_CTRL1f, + DUP_SELf, + DUP_STS_8_0f, + DUP_STS_9_0f, + DV_SPEEDUP_LEDf, + DW8051_DRF_ERAM_BIST_MODEf, + DW8051_DRF_IRAM_BIST_MODEf, + DW8051_DRF_IROM_BIST_MODEf = 940, + DW8051_ERAM_BIST_DONEf, + DW8051_ERAM_BIST_FAILf, + DW8051_ERAM_BIST_GRP_ENf, + DW8051_ERAM_BIST_LOOP_MODEf, + DW8051_ERAM_BIST_MODEf, + DW8051_ERAM_BIST_RSTNf, + DW8051_ERAM_DRF_BIST_DONEf, + DW8051_ERAM_DRF_BIST_FAILf, + DW8051_ERAM_DRF_START_PAUSEf, + DW8051_ERAM_DRF_TEST_RESUMEf = 950, + DW8051_ERAM_DYN_READ_ENf, + DW8051_ERAM_LSf, + DW8051_ERAM_RMEf, + DW8051_ERAM_RM_0f, + DW8051_ERAM_RM_1f, + DW8051_ERAM_RM_2f, + DW8051_ERAM_TEST1f, + DW8051_INDIRECT_EE_ENf, + DW8051_IRAM_BIST_DONEf, + DW8051_IRAM_BIST_FAILf = 960, + DW8051_IRAM_BIST_LOOP_MODEf, + DW8051_IRAM_BIST_MODEf, + DW8051_IRAM_BIST_RSTNf, + DW8051_IRAM_DRF_BIST_DONEf, + DW8051_IRAM_DRF_BIST_FAILf, + DW8051_IRAM_DRF_START_PAUSEf, + DW8051_IRAM_DRF_TEST_RESUMEf, + DW8051_IRAM_DYN_READ_ENf, + DW8051_IRAM_LSf, + DW8051_IRAM_RMf = 970, + DW8051_IRAM_RMEf, + DW8051_IRAM_TEST1f, + DW8051_IROM_BIST_DONEf, + DW8051_IROM_BIST_FAILf, + DW8051_IROM_BIST_LOOP_MODEf, + DW8051_IROM_BIST_MODEf, + DW8051_IROM_BIST_RSTNf, + DW8051_IROM_DRF_BIST_DONEf, + DW8051_IROM_DRF_BIST_FAILf, + DW8051_IROM_DRF_START_PAUSEf = 980, + DW8051_IROM_DRF_TEST_RESUMEf, + DW8051_IROM_DYN_READ_ENf, + DW8051_IROM_LSf, + DW8051_IROM_RMf, + DW8051_IROM_RMEf, + DW8051_IROM_TEST1f, + DW8051_RATEf, + DW8051_READYf, + DW8051_RSTf, + DYN_READ_EN_MACSEC_SA_AEf = 990, + DYN_READ_EN_MACSEC_SA_AIf, + DYN_READ_EN_MACSEC_STAT_AEf, + DYN_READ_EN_MACSEC_STAT_AIf, + EDSCf, + EEE_100M_ENf, + EEE_10GLITE_ENf, + EEE_10G_ENf, + EEE_2P5GLITE_ENf, + EEE_2P5G_ENf, + EEE_500M_ENf = 1000, + EEE_5GLITE_ENf, + EEE_5G_ENf, + EEE_ABLTY_8_0f, + EEE_ABLTY_9_0f, + EEE_GIGA_ENf, + EEE_PORT_RX_ENf, + EEE_PORT_TX_ENf, + EEE_RX_STSf, + EEE_TX_STSf, + EEPROM_ADDR_LENf = 1010, + EEPROM_AUTOLOAD_TIMERf, + EEPROM_AUTO_LOAD_LENf, + EEPROM_CODE_DATE_0f, + EEPROM_CODE_DATE_1f, + EEPROM_CODE_DATE_2f, + EEPROM_CODE_VERf, + EEPROM_COMPLf, + EEPROM_VALID_FAILf, + EFUSE_ACCESS_ENf, + EFUSE_ADDRf = 1020, + EFUSE_AUTOLOAD_CNTf, + EFUSE_AUTOLOAD_TIMERf, + EFUSE_CMDf, + EFUSE_COMP_ERR_CNTf, + EFUSE_CP_CHKf, + EFUSE_FREQ_SELf, + EFUSE_MARGIN_RD_END_ADRf, + EFUSE_MARGIN_RD_ERR_ADR1f, + EFUSE_MARGIN_RD_ERR_ADR2f, + EFUSE_MARGIN_RD_ERR_CNTf = 1030, + EFUSE_MARGIN_RD_ERR_DAT1f, + EFUSE_MARGIN_RD_ERR_DAT2f, + EFUSE_MASS_COMP_ERR_ADR1f, + EFUSE_MASS_COMP_ERR_ADR2f, + EFUSE_MASS_COMP_ERR_DAT1f, + EFUSE_MASS_COMP_ERR_DAT2f, + EFUSE_MASS_DATAf, + EFUSE_MASS_OP_END_ADRf, + EFUSE_MODEf, + EFUSE_RDATAf = 1040, + EFUSE_REPAIR_CHKf, + EFUSE_RE_AUTOLOADf, + EFUSE_WDATAf, + EGR_CTRL_GATCLK_ENf, + EGR_P_DGLT_ENf, + ENf, + ENTRY_CLRf, + EN_FC_EFCTf, + EN_FIFO_ERR_TRIGf, + EN_LATCHf = 1050, + EN_LD_TX_DSC_ERR_TRIGf, + EN_PINGPONG_PLUS_ERR_TRIGf, + EN_RXPORT_DSC_ERR_TRIGf, + EN_SYNCE_LOCK0f, + EN_SYNCE_LOCK1f, + EN_SYS_DSC_ERR_TRIGf, + EN_TM_MAXf, + EN_TM_MINf, + EN_TOKEN_ERR_TRIGf, + ERRPKTf = 1060, + ETH2_P0_ACTf, + ETYPE13_0f, + ETYPE15_14f, + EXECf, + EXT_CPUTAG_ENf, + EXT_CPUTAG_INSERTMODf, + FAILf, + FAST_LEAVE_ENf, + FIB_UNIDIR_ENf, + FIB_UNIDIR_LED_ENf = 1070, + FIB_UNIDIR_ONLY_CPUTX_ENf, + FIDf, + FIFO_EMPTY_THf, + FIFO_FLAG_MSKf, + FILED0_TYPEf, + FILED1_TYPEf, + FILED2_TYPEf, + FILED3_TYPEf, + FILED4_TYPEf, + FILED5_TYPEf = 1080, + FILED6_TYPEf, + FILED7_TYPEf, + FLAGf, + FLASH_FORCE_CTR_ENf, + FLUSH_ACTf, + FLUSH_ALLf, + FLUSH_BUSYf, + FLUSH_FIDf, + FLUSH_MODEf, + FLUSH_PMSKf = 1090, + FLUSH_TYPEf, + FLUSH_VIDf, + FMTf, + FORBIDf, + FORCE_BYP_LINKf, + FORCE_CTRLf, + FORCE_LINK_ENf, + FORCE_PD_0f, + FORCE_PD_1f, + FORCE_PORT_MASKf = 1100, + FORCE_PU_0f, + FORCE_PU_1f, + FORCE_PU_PD_EN_0f, + FORCE_PU_PD_EN_1f, + FORWARDf, + FORWARD_ENf, + FRC_LOOP_MASKf, + FREE_SPACEf, + FULL_DET_ENf, + FWD_ACT_HITf = 1110, + FWD_CTRL_BITf, + FWD_INVLD_MAC_CTRL_ENf, + FWD_PAUSE_ENf, + FWD_PFC_ENf, + FWD_RULE_IDXf, + FWD_UNKN_OPCODE_ENf, + G2G_0_ERR_CNT_X2Yf, + G2G_0_ERR_CNT_Y2Xf, + G2G_1_ERR_CNT_X2Yf, + G2G_1_ERR_CNT_Y2Xf = 1120, + G2G_2_ERR_CNT_X2Yf, + G2G_2_ERR_CNT_Y2Xf, + G2G_3_ERR_CNT_X2Yf, + G2G_3_ERR_CNT_Y2Xf, + G2G_CLR_ERR_CNT_X2Yf, + G2G_CLR_ERR_CNT_Y2Xf, + G2XG_BYPASS_BCHf, + G2XG_EN_AUTO_RSTf, + G2XG_EN_ECODEf, + G2XG_EN_G_LPIf = 1130, + G2XG_EN_XG_LPIf, + G2XG_GRX_MIN_IPGf, + G2XG_GTX_MIN_IPGf, + G2XG_MODULE_RSTf, + G2XG_RX_RDFIFO_THRf, + G2XG_TX_RDFIFO_THRf, + GEN_RANDOMf, + GETPOWCTRL0_BITf, + GETPOWCTRL1_BITf, + GETPOWCTRL_ADRf = 1140, + GLB_FIFO_ERRf, + GLB_FIFO_STSf, + GLB_LD_TX_DSC_ERRf, + GLB_LD_TX_DSC_STSf, + GLB_PAGE_CNTf, + GLB_PAGE_CURCNTf, + GLB_PAGE_PEAKCNTf, + GLB_PINGPONG_ERRf, + GLB_PINGPONG_STSf, + GLB_RLDP_LED_ENf = 1150, + GLB_RLDP_LED_ENABLEf, + GLB_RXPORT_DSC_STSf, + GLB_RX_P_DSC_ERRf, + GLB_SYS_DSC_ERRf, + GLB_SYS_DSC_STSf, + GLB_TOKEN_ERRf, + GLB_TOKEN_STSf, + GPHY_ENf, + GPIO_CTRL_BITf, + GPIO_INT_SELf = 1160, + GPIO_IN_31_0f, + GPIO_IN_62_32f, + GPIO_LED0_SELf, + GPIO_LED10_SELf, + GPIO_LED11_SELf, + GPIO_LED12_SELf, + GPIO_LED13_SELf, + GPIO_LED14_SELf, + GPIO_LED15_SELf, + GPIO_LED16_SELf = 1170, + GPIO_LED17_SELf, + GPIO_LED18_SELf, + GPIO_LED19_SELf, + GPIO_LED1_SELf, + GPIO_LED20_SELf, + GPIO_LED21_SELf, + GPIO_LED22_SELf, + GPIO_LED23_SELf, + GPIO_LED24_SELf, + GPIO_LED25_SELf = 1180, + GPIO_LED26_SELf, + GPIO_LED27_SELf, + GPIO_LED2_SELf, + GPIO_LED3_SELf, + GPIO_LED4_SELf, + GPIO_LED5_SELf, + GPIO_LED6_SELf, + GPIO_LED7_SELf, + GPIO_LED8_SELf, + GPIO_LED9_SELf = 1190, + GPIO_MDC0_SELf, + GPIO_MDIO0_SELf, + GPIO_MDX1_SEL_0f, + GPIO_MDX1_SEL_1f, + GPIO_OE_31_0f, + GPIO_OE_62_32f, + GPIO_OUT_31_0f, + GPIO_OUT_62_32f, + GPIO_PWM_OUT_SELf, + GPIO_SDA4_SELf = 1200, + GPO_ACT_HITf, + GPO_RULE_IDXf, + GRP_TX_CMDf, + GRP_TX_PORTf, + GUEST_VIDf, + GUSET_OPf, + H2E_RX_STATUSf, + H2E_TX_STATUSf, + HALF_48PASS1_ENf, + HALF_TO_FULL_PAUSEf = 1210, + HASH_FULL_ACTf, + HASH_MSKf, + HFMPEf, + HFPPEf, + HF_VALf, + HIGH_OFFf, + HIGH_ONf, + HIGH_Qf, + HOL_PRVNT_ENf, + HOTCMD1_ADRf = 1220, + HOTCMD1_DATf, + HOTCMD_ENf, + HOTCMD_PRD_ENf, + HSA_BIST_GRP_ENf, + HSA_BIST_LOOPf, + HSA_DYN_READf, + HSA_LSf, + HSA_TEST1f, + HSB_BIST_DONEf, + HSB_BIST_ENf = 1230, + HSB_BIST_FAILf, + HSB_BIST_LOOP_MODEf, + HSB_BIST_MODEf, + HSB_BIST_RSTNf, + HSB_DRF_DONEf, + HSB_DRF_FAILf, + HSB_DRF_MODEf, + HSB_DRF_START_PAUSEf, + HSB_DRF_TEST_RESUMEf, + HSB_DYN_READ_ENf = 1240, + HSB_LSf, + HSB_RMAf, + HSB_RMBf, + HSB_RMEAf, + HSB_RMEBf, + HSB_TEST1Af, + HSB_TEST1Bf, + HSG_GMI_RX_IFGf, + HSG_GMI_TX_IFGf, + HSG_XGMI_RX_IFGf = 1250, + HSG_XGMI_TX_IFGf, + I2C_DATA_ENDIAN_SELf, + I2C_FAILf, + I2C_MST_CODEf, + I2C_OPEN_DRN_SCK_1f, + I2C_OPEN_DRN_SDA_1f, + I2C_RESETf, + I2C_TIMEOUT_FLAGf, + I2C_TIMEOUT_SETf, + I2C_TRIGf = 1260, + IBG_LENf, + IBG_SIZEf, + ICMPf, + ICMPFRAGMENTf, + IDXf, + IGMPf, + IGMPV1_OPf, + IGMPV2_OPf, + IGMPV3_OPf, + IGMP_MLD_DISC_STORM_FLTRf = 1270, + IGMP_MLD_ENf, + IGMP_MLD_IP4_BYPASS_224_0_0f, + IGMP_MLD_IP4_BYPASS_224_0_1f, + IGMP_MLD_IP4_BYPASS_239_255_255f, + IGMP_MLD_IP6_BYPASSf, + IGMP_MLD_PORTISO_LKYf, + IGMP_MLD_VLAN_LKYf, + IGR_CTRL_GATCLK_ENf, + IGR_FLTR_ACTf, + IMODE_GPIO_52f = 1280, + IMODE_GPIO_53f, + IMODE_GPIO_54f, + IMR_EXT_8051f, + IMR_EXT_ACLf, + IMR_EXT_AUTO_RECf, + IMR_EXT_CPUIDE_ENRf, + IMR_EXT_CPUIDE_EXTf, + IMR_EXT_GPHY_3_0f, + IMR_EXT_GPIOf, + IMR_EXT_LEARN_OVER_PORT_9_0f = 1290, + IMR_EXT_LOOP_DETECTIONf, + IMR_EXT_MACSECWRP_3_0f, + IMR_EXT_METER_EXCEEDf, + IMR_EXT_PHYWOL_PORT_3_0f, + IMR_EXT_PORT_LINK_STS_CHG_10_0f, + IMR_EXT_PTP1588f, + IMR_EXT_RLFD_PORT_8_0f, + IMR_EXT_ROUT_PBUFf, + IMR_EXT_SAMOVEf, + IMR_EXT_SDS_UPD_PHYSTSf = 1300, + IMR_EXT_SERDES_LINK_FAULT_PORTf, + IMR_EXT_SERDES_RX_SYM_ERR_1_0f, + IMR_EXT_SMI_CHECK_REG_4_0f, + IMR_EXT_TM_HIGHf, + IMR_EXT_TM_LOWf, + IMR_EXT_WOL_PORT_8_0f, + IMR_INT_ACLf, + IMR_INT_AUTO_RECf, + IMR_INT_GPHY_3_0f, + IMR_INT_GPIOf = 1310, + IMR_INT_LEARN_OVER_PORT_9_0f, + IMR_INT_LOOP_DETECTIONf, + IMR_INT_MACSECWRP_3_0f, + IMR_INT_METER_EXCEEDf, + IMR_INT_PHYWOL_PORT_3_0f, + IMR_INT_PORT_LINK_STS_CHG_10_0f, + IMR_INT_PTP1588f, + IMR_INT_RLFD_PORT_8_0f, + IMR_INT_ROUT_PBUFf, + IMR_INT_SAMOVEf = 1320, + IMR_INT_SDS_UPD_PHYSTSf, + IMR_INT_SERDES_LINK_FAULT_PORTf, + IMR_INT_SERDES_RX_SYM_ERR_1_0f, + IMR_INT_SMI_CHECK_REG_4_0f, + IMR_INT_TM_HIGHf, + IMR_INT_TM_LOWf, + IMR_INT_WOL_PORT_8_0f, + IMR_TODf, + INC_BYPASS_PKTf, + INC_IFGf = 1330, + INDATA_15_0f, + INDICATORf, + INGR_ERRf, + INI_MODEf, + INTDEV0_POLLING_10GPHYf, + INTDEV1_POLLING_10GPHYf, + INTPRI0_TO_VALf, + INTPRI1_TO_VALf, + INTPRI2_TO_VALf, + INTPRI3_TO_VALf = 1340, + INTPRI4_TO_VALf, + INTPRI5_TO_VALf, + INTPRI6_TO_VALf, + INTPRI7_TO_VALf, + INTPRI_DSCPf, + INTP_OUT_SDS_CTRLf, + INTP_SRC_TGR0f, + INTREG0_POLLING_10GPHYf, + INTREG1_POLLING_10GPHYf, + INT_CPUTAG_ENf = 1350, + INT_CPUTAG_INSERTMODf, + INT_PHY_OCP_INDACC_ADDRf, + INT_PHY_OCP_INDACC_CMDf, + INT_PHY_OCP_INDACC_FAILf, + INT_PHY_OCP_INDACC_PHYADRf, + INT_PHY_OCP_INDACC_RDDATAf, + INT_PHY_OCP_INDACC_RWf, + INT_PHY_OCP_INDACC_WRDATAf, + IOL_LEN_ERR_ENf, + IOL_MAX_LEN_ENf = 1360, + IOL_MAX_RETRY_ENf, + IO_BISD_ENf, + IO_DRVING_0f, + IO_DRVING_1f, + IO_DRVING_2f, + IO_SLEW_0f, + IO_SLEW_1f, + IO_SLEW_2f, + IO_SMT_EN_0f, + IO_SMT_EN_1f = 1370, + IO_SMT_EN_2f, + IPG_4N_BYTE_COMPS_ENf, + IPG_CNTRf, + IPG_COMPS_ENf, + IPG_COMPS_SELf, + IPG_LENf, + IPMUL_PORTISO_LEAKYf, + IPMUL_VLAN_LEAKYf, + IPRI0f, + IPRI1f = 1380, + IPRI2f, + IPRI3f, + IPRI4f, + IPRI5f, + IPRI6f, + IPRI7f, + IPRI_RMK_ENf, + IPRI_RMK_SRCf, + IPTYPEf, + IROM_DATAf = 1390, + IROM_MSBf, + ISR_EXT_8051f, + ISR_EXT_ACLf, + ISR_EXT_AUTO_RECf, + ISR_EXT_GLB_8051f, + ISR_EXT_GLB_ACLf, + ISR_EXT_GLB_AUTO_RECf, + ISR_EXT_GLB_CPUIDE_ENRf, + ISR_EXT_GLB_CPUIDE_EXTf, + ISR_EXT_GLB_GPHYf = 1400, + ISR_EXT_GLB_GPIOf, + ISR_EXT_GLB_LEARN_OVERf, + ISR_EXT_GLB_LINK_CHGf, + ISR_EXT_GLB_LOOP_DETECTIONf, + ISR_EXT_GLB_MACSECWRPf, + ISR_EXT_GLB_METER_EXCEEDf, + ISR_EXT_GLB_PHYWOLf, + ISR_EXT_GLB_PTP1588f, + ISR_EXT_GLB_RLFDf, + ISR_EXT_GLB_ROUT_PBUFf = 1410, + ISR_EXT_GLB_SAMOVEf, + ISR_EXT_GLB_SDS_RX_SYM_ERRf, + ISR_EXT_GLB_SDS_UPD_PHYSTSf, + ISR_EXT_GLB_SERDES_LINK_FAULT_Pf, + ISR_EXT_GLB_SMI_CHECKf, + ISR_EXT_GLB_TERMAL_DETECTf, + ISR_EXT_GLB_WOLf, + ISR_EXT_GPHYf, + ISR_EXT_GPIOf, + ISR_EXT_LEARN_OVER_PORT_9_0f = 1420, + ISR_EXT_LOOP_DETECTIONf, + ISR_EXT_MACSECWRP_3_0f, + ISR_EXT_METER_EXCEEDf, + ISR_EXT_PHYWOL_PORT_3_0f, + ISR_EXT_PORT_LINK_STS_CHG_9_0f, + ISR_EXT_PTP1588f, + ISR_EXT_RLFD_PORT_8_0f, + ISR_EXT_ROUT_PBUFf, + ISR_EXT_SAMOVEf, + ISR_EXT_SDS_UPD_PHYSTSf = 1430, + ISR_EXT_SERDES_LINK_FAULT_PORTf, + ISR_EXT_SERDES_RX_SYM_ERR_1_0f, + ISR_EXT_SMI_CHECK_REG_4_0f, + ISR_EXT_TM_HIGHf, + ISR_EXT_TM_LOWf, + ISR_EXT_WOL_PORT_8_0f, + ISR_INT_ACLf, + ISR_INT_AUTO_RECf, + ISR_INT_GLB_ACLf, + ISR_INT_GLB_AUTO_RECf = 1440, + ISR_INT_GLB_GPHYf, + ISR_INT_GLB_GPIOf, + ISR_INT_GLB_LEARN_OVERf, + ISR_INT_GLB_LINK_CHGf, + ISR_INT_GLB_LOOP_DETECTIONf, + ISR_INT_GLB_MACSECWRPf, + ISR_INT_GLB_METER_EXCEEDf, + ISR_INT_GLB_PHYWOLf, + ISR_INT_GLB_PTP1588f, + ISR_INT_GLB_RLFDf = 1450, + ISR_INT_GLB_ROUT_PBUFf, + ISR_INT_GLB_SAMOVEf, + ISR_INT_GLB_SDS_RX_SYM_ERRf, + ISR_INT_GLB_SDS_UPD_PHYSTSf, + ISR_INT_GLB_SERDES_LINK_FAULT_Pf, + ISR_INT_GLB_SMI_CHECKf, + ISR_INT_GLB_TERMAL_DETECTf, + ISR_INT_GLB_WOLf, + ISR_INT_GPHYf, + ISR_INT_GPIOf = 1460, + ISR_INT_LEARN_OVER_PORT_9_0f, + ISR_INT_LOOP_DETECTIONf, + ISR_INT_MACSECWRP_3_0f, + ISR_INT_METER_EXCEEDf, + ISR_INT_PHYWOL_PORT_3_0f, + ISR_INT_PORT_LINK_STS_CHG_9_0f, + ISR_INT_PTP1588f, + ISR_INT_RLFD_PORT_8_0f, + ISR_INT_ROUT_PBUFf, + ISR_INT_SAMOVEf = 1470, + ISR_INT_SDS_UPD_PHYSTSf, + ISR_INT_SERDES_LINK_FAULT_PORTf, + ISR_INT_SERDES_RX_SYM_ERR_1_0f, + ISR_INT_SMI_CHECK_REG_4_0f, + ISR_INT_TM_HIGHf, + ISR_INT_TM_LOWf, + ISR_INT_WOL_PORT_8_0f, + ISR_TODf, + ITAG_TPID_0f, + JUMBO_FRAME_CNTf = 1480, + L2PTPf, + L2_BIST_DONEf, + L2_BIST_DYN_READ_ENf, + L2_BIST_FAILf, + L2_BIST_GRP_ENf, + L2_BIST_LOOP_ENf, + L2_BIST_MODEf, + L2_BIST_RSTNf, + L2_DRF_DONEf, + L2_DRF_FAILf = 1490, + L2_DRF_MODEf, + L2_DRF_PAUSEf, + L2_DRF_RESUMEf, + L2_DVSEf, + L2_DVS_0f, + L2_DVS_1f, + L2_DVS_2f, + L2_DVS_3f, + L2_LSf, + L2_MC_ENf = 1500, + L2_TEST1f, + L3ERRf, + L4DPORTf, + L4SPORT0f, + L4SPORT15_1f, + LAND_V4f, + LAND_V6f, + LATCH_ALWAYSf, + LATCH_FIRSTf, + LATE_COLI_DROP_ENf = 1510, + LATE_COLI_THRf, + LB_BURSTf, + LB_EXCEEDf, + LB_EXCEED_ICPUf, + LB_MODEf, + LB_RATEf, + LD_TX_DSC_ERRf, + LD_TX_DSC_ERR_MSKf, + LD_TX_DSC_STSf, + LEAVE_LOOP_PMSKf = 1520, + LEAVE_SUPPRESSIONf, + LEAVE_TIMERf, + LED_LOAD_ENf, + LED_PAD_ENf, + LED_SET_PSELf, + LENf, + LIMIT_IPG_CFG_10M_100Mf, + LIMIT_IPG_CFG_1G_2P5Gf, + LIMIT_PAUSE_ENf, + LIMIT_PFC_ENf = 1530, + LINELPBK_ENf, + LINKDOWN_AGEOUTf, + LINKDOWN_TO_UPSf, + LINKINTRP_TX_EN_8_0f, + LINKUP_DELAY_10G_5Gf, + LINKUP_DELAY_10Mf, + LINKUP_DELAY_2P5G_1000M_100Mf, + LINK_DOWN_TIME0f, + LINK_DOWN_TIME1f, + LINK_DOWN_TIME2f = 1540, + LINK_DOWN_TIME_EN0f, + LINK_DOWN_TIME_EN1f, + LINK_DOWN_TIME_EN2f, + LINK_FAULT_SDS0_TGXR0_CH0f, + LINK_FAULT_SDS0_TGXR0_CH1f, + LINK_FAULT_SDS0_TGXR0_CH2f, + LINK_FAULT_SDS0_TGXR0_CH3f, + LINK_FAULT_SDS1_TGXR0_CH0f, + LINK_STS_8_0f, + LINK_STS_9_0f = 1550, + LINK_UP_DELAYf, + LIST_BITf, + LLDP_ENf, + LL_BIST_DONEf, + LL_BIST_FAILf, + LL_DRF_BIST_DONEf, + LL_DRF_BIST_FAILf, + LL_DRF_START_PAUSEf, + LNKDN_CLK_GATE_FLAGf, + LNKDN_FRC_DISf = 1560, + LOAD_SYS_PARf, + LOOPBACK_ENf, + LOOPED_PMSKf, + LOOP_DETECT_RATEf, + LOOP_PAIRf, + LOOP_PMSKf, + LOWERf, + LOW_Q_THRf, + LOW_Q_TX_DELAY_10Gf, + LOW_Q_TX_DELAY_10GLITEf = 1570, + LOW_Q_TX_DELAY_2P5Gf, + LOW_Q_TX_DELAY_2P5GLITEf, + LOW_Q_TX_DELAY_5Gf, + LOW_Q_TX_DELAY_5GLITEf, + LOW_Q_TX_DELAY_FEf, + LOW_Q_TX_DELAY_GEf, + LOW_Q_TX_DELAY_GELITEf, + LOW_VOLT_CH_FLAGf, + LRN_ACTf, + LRN_CNTf = 1580, + LUTCAM_DISABLEf, + LUT_IPMC_HASHf, + LV1_THR_100Mf, + LV1_THR_10Gf, + LV1_THR_10Mf, + LV1_THR_1Gf, + LV1_THR_2P5Gf, + LV1_THR_500Mf, + LV1_THR_5Gf, + LV2_THR_100Mf = 1590, + LV2_THR_10Gf, + LV2_THR_10Mf, + LV2_THR_1Gf, + LV2_THR_2P5Gf, + LV2_THR_500Mf, + LV2_THR_5Gf, + LV3_THR_100Mf, + LV3_THR_10Gf, + LV3_THR_10Mf, + LV3_THR_1Gf = 1600, + LV3_THR_2P5Gf, + LV3_THR_500Mf, + LV3_THR_5Gf, + MAC0_TXFIFO_THR_CTRLf, + MAC1_TXFIFO_THR_CTRLf, + MAC2PHY_ENf, + MAC2_TXFIFO_THR_CTRLf, + MAC3_LPI_OPTIONf, + MAC3_PFC_FRC_FC_ENf, + MAC3_PFC_FRC_FC_RXf = 1610, + MAC3_PFC_FRC_FC_TXf, + MAC3_SDS0_MODEf, + MAC3_TXFIFO_THR_CTRL_1Gf, + MAC3_TXFIFO_THR_CTRL_TGf, + MAC4_TXFIFO_THR_CTRLf, + MAC5_TXFIFO_THR_CTRLf, + MAC6_TXFIFO_THR_CTRLf, + MAC7_TXFIFO_THR_CTRLf, + MAC8_LPI_OPTIONf, + MAC8_PFC_FRC_FC_ENf = 1620, + MAC8_PFC_FRC_FC_RXf, + MAC8_PFC_FRC_FC_TXf, + MAC8_SDS1_MODEf, + MAC8_TXFIFO_THR_CTRL_1Gf, + MAC8_TXFIFO_THR_CTRL_TGf, + MAC9_TXFIFO_THR_CTRLf, + MACSEC_ETHf, + MACSEC_ETH_0f, + MACSEC_ETH_1f, + MACSEC_ETH_2f = 1630, + MACSEC_ETH_3f, + MACSEC_ETH_4f, + MACSEC_ETH_5f, + MACSEC_ETH_6f, + MACSEC_ETH_7f, + MACSEC_IFG_SELf, + MACSEC_IPG_LENGTHf, + MACSEC_IPG_MODEf, + MACSEC_RX_ICG_ENf, + MACSEC_SA_AE0_TEST1f = 1640, + MACSEC_SA_AE1_TEST1f, + MACSEC_SA_AE2_TEST1f, + MACSEC_SA_AE3_TEST1f, + MACSEC_SA_AE_DSf, + MACSEC_SA_AE_DVSf, + MACSEC_SA_AE_DVSEf, + MACSEC_SA_AE_ICG_ENf, + MACSEC_SA_AE_LSf, + MACSEC_SA_AE_SDf, + MACSEC_SA_AI0_TEST1f = 1650, + MACSEC_SA_AI1_TEST1f, + MACSEC_SA_AI2_TEST1f, + MACSEC_SA_AI3_TEST1f, + MACSEC_SA_AI_DSf, + MACSEC_SA_AI_DVSf, + MACSEC_SA_AI_DVSEf, + MACSEC_SA_AI_ICG_ENf, + MACSEC_SA_AI_LSf, + MACSEC_SA_AI_SDf, + MACSEC_STAT_AE_DSf = 1660, + MACSEC_STAT_AE_DVSf, + MACSEC_STAT_AE_DVSEf, + MACSEC_STAT_AE_ICG_ENf, + MACSEC_STAT_AE_LSf, + MACSEC_STAT_AE_SDf, + MACSEC_STAT_AE_TEST1f, + MACSEC_STAT_AE_TESTRWMf, + MACSEC_STAT_AI_DSf, + MACSEC_STAT_AI_DVSf, + MACSEC_STAT_AI_DVSEf = 1670, + MACSEC_STAT_AI_ICG_ENf, + MACSEC_STAT_AI_LSf, + MACSEC_STAT_AI_SDf, + MACSEC_STAT_AI_TEST1f, + MACSEC_STAT_AI_TESTRWMf, + MACSEC_TX_ICG_ENf, + MACSEC_VLANf, + MAC_48PASS1_DROP_ENf, + MAC_CHG_DUPf, + MAC_DIRf = 1680, + MAC_ENf, + MAC_FORCE_ENf, + MAC_GATCLK_ENf, + MAC_LINK_STS_9_0f, + MAC_PORT0_TYPEf, + MAC_PORT1_TYPEf, + MAC_PORT2_TYPEf, + MAC_PORT3_TYPEf, + MAC_PORT4_TYPEf, + MAC_PORT5_TYPEf = 1690, + MAC_PORT6_TYPEf, + MAC_PORT7_TYPEf, + MAC_PORT8_TYPEf, + MAC_SPD_ABLTY0f, + MAC_SPD_ABLTY1f, + MAC_SPD_ABLTY2f, + MAC_SPD_ABLTY_BYPf, + MAIN_PAGE_11_0f, + MANUALf, + MAX_GROUP_NUMf = 1700, + MAX_LEN_100M_10M_SELf, + MAX_LEN_1G_2P5G_5G_10G_SELf, + MAX_LEN_TAG_INCf, + MAX_LEN_TX_100M_10M_SELf, + MAX_LEN_TX_1G_2P5G_5G_10G_SELf, + MAX_RETX_SELf, + MCIDf, + MDIO_FREE_CNT_ENf, + MDIO_FREE_CNT_SELf, + MDI_BRD_MSKf = 1710, + MEDIA_SELf, + MEDIA_STS_8_0f, + MEDIA_STS_9_0f, + MEM_ADDRf, + MEM_ADDR_WIDTHf, + MGC0_31f, + MGC32_47f, + MIBCNT_MODEf, + MIBCNT_SWRST_Nf, + MIB_COUNTER_Hf = 1720, + MIB_COUNTER_Lf, + MIB_DONEf, + MIB_DRF_DONEf, + MIB_DRF_FAILf, + MIB_DRF_MODEf, + MIB_DRF_PAUSEf, + MIB_DYN_READ_ENf, + MIB_FAILf, + MIB_GLOBAL_RESETf, + MIB_IDf = 1730, + MIB_LOOP_MODEf, + MIB_LS_MODEf, + MIB_MB_RMf, + MIB_MB_RMEf, + MIB_MODEf, + MIB_PORTN_RESETf, + MIB_RESET_VALUEf, + MIB_RESUMEf, + MIB_RSTNf, + MIB_TEST1f = 1740, + MIRROR_ACL_OVERRIDE_ENf, + MIRROR_RX_OVERRIDE_ENf, + MIRROR_TX_OVERRIDE_ENf, + MIR_ENf, + MIR_ISOf, + MIR_REALKEEP_ENf, + MIR_RX_ISOLATE_LKYf, + MIR_RX_TX_SELf, + MIR_RX_VLAN_LKYf, + MIR_TX_ISOLATE_LKYf = 1750, + MIR_TX_VLAN_LKYf, + MLDV1_OPf, + MLDV2_OPf, + MMD_DEVAD_4_0f, + MMD_REG_15_0f, + MODEf, + MODEL_CHAR_1STf, + MODEL_CHAR_2NDf, + MSKf, + MSTR_SLV_FAULT_STS_8_0f = 1760, + MSTR_SLV_STS_8_0f, + MST_CODEf, + MTP_PORTf, + MULTIWAKE_ENf, + MULTIWAKE_INTLVf, + MULTIWAKE_PORTSf, + MULTIWAKE_TIME_UNITf, + MUL_TRAP_PRIf, + NEW_SAf, + NIC_BIST_DONEf = 1770, + NIC_BIST_FAILf, + NIC_BIST_LOOP_MODEf, + NIC_BIST_MODEf, + NIC_BIST_RSTNf, + NIC_DRF_BIST_DONEf, + NIC_DRF_BIST_FAILf, + NIC_DRF_BIST_MODEf, + NIC_DRF_START_PAUSEf, + NIC_DRF_TEST_RESUMEf, + NIC_DYN_READ_ENf = 1780, + NIC_ENf, + NIC_LSf, + NIC_RMf, + NIC_RMEf, + NIC_TEST1f, + NOEEPROMf, + NOTf, + NULLSCANf, + NUMf, + OAMf = 1790, + OFFf, + OFFSETf, + ONf, + ORIGINAL_COLf, + ORIGINAL_CRSf, + OTAG_TPID_0f, + OTAG_TPID_1f, + OTAG_TPID_2f, + OTAG_TPID_3f, + P0_BYPASS_SMOOTHf = 1800, + P0_CFG_ALWAYS_TSf, + P0_CFG_BYPASSf, + P0_CFG_ETH_ENf, + P0_CFG_LINK_DELAY_Hf, + P0_CFG_LINK_DELAY_Lf, + P0_CFG_UDP_ENf, + P0_CLR_G2G_FIFO_RXf, + P0_CLR_G2G_FIFO_TXf, + P0_CLR_G2XG_FIFO_RXf, + P0_CLR_G2XG_FIFO_TXf = 1810, + P0_CLR_XG2XG_FIFO_RXf, + P0_CLR_XG2XG_FIFO_TXf, + P0_CMD0_RDATf, + P0_CMD1_RDATf, + P0_CMD2_RDATf, + P0_CMD3_RDATf, + P0_DBG_PTPf, + P0_G2XG_BCH_ERR_FLAGf, + P0_G2XG_CFG_CLR_ERR_FLAGf, + P0_IDf = 1820, + P0_IPG_DIFFf, + P0_LDN_CLR_G2G_FIFO_RXf, + P0_LDN_CLR_G2G_FIFO_TXf, + P0_LDN_CLR_G2XG_FIFO_RXf, + P0_LDN_CLR_G2XG_FIFO_TXf, + P0_LDN_CLR_XG2XG_FIFO_RXf, + P0_LDN_CLR_XG2XG_FIFO_TXf, + P0_LED3_0_RLDP_MASKf, + P0_LINK_FAULT_STSf, + P0_MDI_REVERSEf = 1830, + P0_PHY_ABLTY_RESOLUTION_FRC_VALUEf, + P0_PHY_R_FRCf, + P0_PTP_ASM_CAREf, + P0_PTP_DELAY_CAREf, + P0_PTP_DUMMYf, + P0_PTP_DUMMY_RG06f, + P0_PTP_PDELAY_CAREf, + P0_PTP_ROLEf, + P0_RD_PCS_ABILITYf, + P0_RST_LATCH_MIN_IPGf = 1840, + P0_RX_IMBALf, + P0_SDET_STSf, + P0_TX_IMBALf, + P0_TX_POLARITY_SWAPf, + P1_BYPASS_SMOOTHf, + P1_CLR_G2G_FIFO_RXf, + P1_CLR_G2G_FIFO_TXf, + P1_CLR_G2XG_FIFO_RXf, + P1_CLR_G2XG_FIFO_TXf, + P1_CLR_XG2XG_FIFO_RXf = 1850, + P1_CLR_XG2XG_FIFO_TXf, + P1_CMD0_RDATf, + P1_CMD1_RDATf, + P1_CMD2_RDATf, + P1_CMD3_RDATf, + P1_DSCP_RULE_IDXf, + P1_G2XG_BCH_ERR_FLAGf, + P1_G2XG_CFG_CLR_ERR_FLAGf, + P1_IPG_DIFFf, + P1_LDN_CLR_G2G_FIFO_RXf = 1860, + P1_LDN_CLR_G2G_FIFO_TXf, + P1_LDN_CLR_G2XG_FIFO_RXf, + P1_LDN_CLR_G2XG_FIFO_TXf, + P1_LDN_CLR_XG2XG_FIFO_RXf, + P1_LDN_CLR_XG2XG_FIFO_TXf, + P1_LED3_0_RLDP_MASKf, + P1_LINK_FAULT_STSf, + P1_MDI_REVERSEf, + P1_PHY_ABLTY_RESOLUTION_FRC_VALUEf, + P1_PHY_R_FRCf = 1870, + P1_RD_PCS_ABILITYf, + P1_RST_LATCH_MIN_IPGf, + P1_SDET_STSf, + P1_TX_POLARITY_SWAPf, + P2_BYPASS_SMOOTHf, + P2_CLR_G2G_FIFO_RXf, + P2_CLR_G2G_FIFO_TXf, + P2_CLR_G2XG_FIFO_RXf, + P2_CLR_G2XG_FIFO_TXf, + P2_CLR_XG2XG_FIFO_RXf = 1880, + P2_CLR_XG2XG_FIFO_TXf, + P2_CMD0_RDATf, + P2_CMD1_RDATf, + P2_CMD2_RDATf, + P2_CMD3_RDATf, + P2_G2XG_BCH_ERR_FLAGf, + P2_G2XG_CFG_CLR_ERR_FLAGf, + P2_IPG_DIFFf, + P2_LDN_CLR_G2G_FIFO_RXf, + P2_LDN_CLR_G2G_FIFO_TXf = 1890, + P2_LDN_CLR_G2XG_FIFO_RXf, + P2_LDN_CLR_G2XG_FIFO_TXf, + P2_LDN_CLR_XG2XG_FIFO_RXf, + P2_LDN_CLR_XG2XG_FIFO_TXf, + P2_LED3_0_RLDP_MASKf, + P2_LINK_FAULT_STSf, + P2_MDI_REVERSEf, + P2_PHY_ABLTY_RESOLUTION_FRC_VALUEf, + P2_PHY_R_FRCf, + P2_RD_PCS_ABILITYf = 1900, + P2_RST_LATCH_MIN_IPGf, + P2_SDET_STSf, + P2_TX_POLARITY_SWAPf, + P3_BYPASS_SMOOTHf, + P3_CLR_G2G_FIFO_RXf, + P3_CLR_G2G_FIFO_TXf, + P3_CLR_G2XG_FIFO_RXf, + P3_CLR_G2XG_FIFO_TXf, + P3_CLR_XG2XG_FIFO_RXf, + P3_CLR_XG2XG_FIFO_TXf = 1910, + P3_CMD0_RDATf, + P3_CMD1_RDATf, + P3_CMD2_RDATf, + P3_CMD3_RDATf, + P3_G2XG_BCH_ERR_FLAGf, + P3_G2XG_CFG_CLR_ERR_FLAGf, + P3_IPG_DIFFf, + P3_LDN_CLR_G2G_FIFO_RXf, + P3_LDN_CLR_G2G_FIFO_TXf, + P3_LDN_CLR_G2XG_FIFO_RXf = 1920, + P3_LDN_CLR_G2XG_FIFO_TXf, + P3_LDN_CLR_XG2XG_FIFO_RXf, + P3_LDN_CLR_XG2XG_FIFO_TXf, + P3_LED3_0_RLDP_MASKf, + P3_LINK_FAULT_STSf, + P3_MDI_REVERSEf, + P3_PHY_ABLTY_RESOLUTION_FRC_VALUEf, + P3_PHY_R_FRCf, + P3_RD_PCS_ABILITYf, + P3_RST_LATCH_MIN_IPGf = 1930, + P3_SDET_STSf, + P3_TX_POLARITY_SWAPf, + P4_LED3_0_RLDP_MASKf, + P5_LED3_0_RLDP_MASKf, + P6_LED3_0_RLDP_MASKf, + P7_LED3_0_RLDP_MASKf, + P8_LED3_0_RLDP_MASKf, + PADDING_SELf, + PADDING_UND_SIZE_ENf, + PAD_MSCK0_SEL_0f = 1940, + PAD_MSCK0_SEL_1f, + PAD_MSCK1_SEL_0f, + PAD_MSCK1_SEL_1f, + PAD_MSCK2_SEL_0f, + PAD_MSCK2_SEL_1f, + PAD_MSDA0_SEL_0f, + PAD_MSDA0_SEL_1f, + PAD_MSDA1_SEL_0f, + PAD_MSDA1_SEL_1f, + PAD_MSDA2_SEL_0f = 1950, + PAD_MSDA2_SEL_1f, + PAD_UART0_SEL_0f, + PAD_UART0_SEL_1f, + PARITYf, + PARK_PAGE_4_0f, + PASS_ALL_MODE_ENf, + PB_BYTE_INDEXf, + PB_CELL_INDEXf, + PB_INDEXf, + PB_TRIGf = 1960, + PB_TYPEf, + PCP0_PG_MAPf, + PCP1_PG_MAPf, + PCP2_PG_MAPf, + PCP3_PG_MAPf, + PCP4_PG_MAPf, + PCP5_PG_MAPf, + PCP6_PG_MAPf, + PCP7_PG_MAPf, + PCSXF_MCFGf = 1970, + PCSXF_MIIRX_IPGf, + PCSXF_RST_RXFIFOf, + PCSXF_RXFIFO_ERR_FLAGf, + PCSXF_STOP_RXCf, + PCSXF_STOP_TXCf, + PDOWN_EN_INI_TGRf, + PERIOD_CHKf, + PERIOD_LOOPf, + PER_PORT_RSTBf, + PER_PORT_RX_RSTBf = 1980, + PER_PORT_TX_RSTBf, + PEV0_TXQ_MAPf, + PEV1_TXQ_MAPf, + PEV2_TXQ_MAPf, + PEV3_TXQ_MAPf, + PEV4_TXQ_MAPf, + PEV5_TXQ_MAPf, + PEV6_TXQ_MAPf, + PEV7_TXQ_MAPf, + PFC_ACTDROP_PG_ENf = 1990, + PFC_ALLOWPAGE_CNTf, + PFC_MODE_SELf, + PFC_PCPSRC_SELf, + PFC_PCP_UTAGf, + PFC_PG_FORCE_CNG_ENf, + PFC_PG_FORCE_CNG_VALUEf, + PFC_PG_ISCNGf, + PFC_STSPRIf, + PFC_STSPRI_FORCE_ENf, + PFC_STSPRI_FORCE_VALUEf = 2000, + PG0_PEV_MAPf, + PG1_PEV_MAPf, + PG2_PEV_MAPf, + PG3_PEV_MAPf, + PG4_PEV_MAPf, + PG5_PEV_MAPf, + PG6_PEV_MAPf, + PG7_PEV_MAPf, + PG_PAGE_CNTf, + PG_PAGE_PEAKCNTf = 2010, + PG_PFCOFF_GURANTEE_THRf, + PG_PFCON_GURANTEE_THRf, + PG_PFC_ENf, + PHY0_RX_CRC_ERRORSf, + PHY0_RX_GOOD_OCTETS_Hf, + PHY0_RX_GOOD_OCTETS_Lf, + PHY0_RX_GOOD_PKTS_Hf, + PHY0_RX_GOOD_PKTS_Lf, + PHY0_RX_SYMBOL_ERRORSf, + PHY0_RX_TOTAL_PKTS_Hf = 2020, + PHY0_RX_TOTAL_PKTS_Lf, + PHY0_TX_CRC_ERRORSf, + PHY0_TX_GOOD_OCTETS_Hf, + PHY0_TX_GOOD_OCTETS_Lf, + PHY0_TX_GOOD_PKTS_Hf, + PHY0_TX_GOOD_PKTS_Lf, + PHY0_TX_TOTAL_PKTS_Hf, + PHY0_TX_TOTAL_PKTS_Lf, + PHY1_RX_CRC_ERRORSf, + PHY1_RX_GOOD_OCTETS_Hf = 2030, + PHY1_RX_GOOD_OCTETS_Lf, + PHY1_RX_GOOD_PKTS_Hf, + PHY1_RX_GOOD_PKTS_Lf, + PHY1_RX_SYMBOL_ERRORSf, + PHY1_RX_TOTAL_PKTS_Hf, + PHY1_RX_TOTAL_PKTS_Lf, + PHY1_TX_CRC_ERRORSf, + PHY1_TX_GOOD_OCTETS_Hf, + PHY1_TX_GOOD_OCTETS_Lf, + PHY1_TX_GOOD_PKTS_Hf = 2040, + PHY1_TX_GOOD_PKTS_Lf, + PHY1_TX_TOTAL_PKTS_Hf, + PHY1_TX_TOTAL_PKTS_Lf, + PHY2MAC_ENf, + PHY2SDS_EEE_FLG_DLY0f, + PHY2SDS_EEE_FLG_DLY1f, + PHY2SDS_EEE_FLG_DLY2f, + PHY2SDS_EEE_FLG_DLY3f, + PHY2_RX_CRC_ERRORSf, + PHY2_RX_GOOD_OCTETS_Hf = 2050, + PHY2_RX_GOOD_OCTETS_Lf, + PHY2_RX_GOOD_PKTS_Hf, + PHY2_RX_GOOD_PKTS_Lf, + PHY2_RX_SYMBOL_ERRORSf, + PHY2_RX_TOTAL_PKTS_Hf, + PHY2_RX_TOTAL_PKTS_Lf, + PHY2_TX_CRC_ERRORSf, + PHY2_TX_GOOD_OCTETS_Hf, + PHY2_TX_GOOD_OCTETS_Lf, + PHY2_TX_GOOD_PKTS_Hf = 2060, + PHY2_TX_GOOD_PKTS_Lf, + PHY2_TX_TOTAL_PKTS_Hf, + PHY2_TX_TOTAL_PKTS_Lf, + PHY3_RX_CRC_ERRORSf, + PHY3_RX_GOOD_OCTETS_Hf, + PHY3_RX_GOOD_OCTETS_Lf, + PHY3_RX_GOOD_PKTS_Hf, + PHY3_RX_GOOD_PKTS_Lf, + PHY3_RX_SYMBOL_ERRORSf, + PHY3_RX_TOTAL_PKTS_Hf = 2070, + PHY3_RX_TOTAL_PKTS_Lf, + PHY3_TX_CRC_ERRORSf, + PHY3_TX_GOOD_OCTETS_Hf, + PHY3_TX_GOOD_OCTETS_Lf, + PHY3_TX_GOOD_PKTS_Hf, + PHY3_TX_GOOD_PKTS_Lf, + PHY3_TX_TOTAL_PKTS_Hf, + PHY3_TX_TOTAL_PKTS_Lf, + PHY_ABLTY_RESOLUTION_FRC_MODEf, + PHY_BASE_ADRf = 2080, + PHY_BRDCASTf, + PHY_BRD_ADRf, + PHY_BRD_MODEf, + PHY_FORCE_PAUSE_ABLTY_SELf, + PHY_FORCE_RX_PAUSE_ABLTYf, + PHY_FORCE_TX_PAUSE_ABLTYf, + PHY_INI_DISGIGAf, + PHY_INI_EEE_ENf, + PHY_INI_POWER_DOWNf, + PHY_MASKf = 2090, + PHY_MISC_FAULT_ONf, + PHY_OCP_TOf, + PHY_OCP_TOFf, + PHY_SDET_SELf, + PHY_WOL_ENf, + PHY_WOL_MAC_0_31f, + PHY_WOL_MAC_32_47f, + PINGPONG_PLUS_ERRf, + PINGPONG_PLUS_ERR_MSKf, + PINGPONG_PLUS_STSf = 2100, + PISO_LEAKY_00f, + PISO_LEAKY_01f, + PISO_LEAKY_02f, + PISO_LEAKY_03f, + PISO_LEAKY_04f, + PISO_LEAKY_08f, + PISO_LEAKY_0Df, + PISO_LEAKY_0Ef, + PISO_LEAKY_10f, + PISO_LEAKY_11f = 2110, + PISO_LEAKY_12f, + PISO_LEAKY_13f, + PISO_LEAKY_18f, + PISO_LEAKY_1Af, + PISO_LEAKY_20f, + PISO_LEAKY_21f, + PISO_LEAKY_22f, + PISO_LEAKY_CDPf, + PISO_LEAKY_CSSTPf, + PISO_LEAKY_LLDPf = 2120, + PKB_BISR_DONEf, + PKB_BISR_FAILf, + PKB_BIST_DONE_2_0f, + PKB_BIST_FAIL_2_0f, + PKB_DRF_BISR_DONEf, + PKB_DRF_BISR_FAILf, + PKB_DRF_BIST_DONE_2_0f, + PKB_DRF_BIST_FAIL_2_0f, + PKB_DRF_START_PAUSE_2_0f, + PKB_HOLD_REMAPf = 2130, + PKB_SECOND_RUN_ENf, + PKE_LENf, + PKG0_TX_CLK_SELf, + PKG0_TX_SELf, + PKG1_TX_CLK_SELf, + PKG1_TX_SELf, + PKG2_TX_CLK_SELf, + PKG2_TX_SELf, + PKG3_TX_CLK_SELf, + PKG3_TX_SELf = 2140, + PKGN_TX_CMDf, + PKGN_TX_DONEf, + PKG_G2XG_GTX_MIN_IPGf, + PKG_G2XG_TX_RDFIFO_THRf, + PKTGEN_DUMMY0f, + PKT_CNTf, + PKT_CNT_DBG_HIGHf, + PKT_CNT_DBG_LOWf, + PKT_CNT_HIGHf, + PKT_CNT_LOWf = 2150, + PKT_ENCAP_GATCLK_ENf, + PKT_INDEXf, + PKT_LENf, + PKT_PRS_GATCLK_ENf, + PMSKf, + PMSK_ACTf, + PMSK_ENf, + POB_ENf, + POLIC_LOG_ACT_HITf, + POLIC_LOG_CTRL_BITf = 2160, + POLIC_LOG_RULE_IDXf, + PORTf, + PORT0_ADDRf, + PORT0_STATEf, + PORT1_ADDRf, + PORT1_IDf, + PORT1_STATEf, + PORT2_ADDRf, + PORT2_IDf, + PORT2_STATEf = 2170, + PORT3_ADDRf, + PORT3_STATEf, + PORT4_ADDRf, + PORT4_STATEf, + PORT5_ADDRf, + PORT5_STATEf, + PORT6_ADDRf, + PORT6_STATEf, + PORT7_ADDRf, + PORT7_STATEf = 2180, + PORT8_ADDRf, + PORT8_STATEf, + PORT9_STATEf, + PORTMASKf, + PORTN_INDEXf, + PORT_ACTf, + PORT_AUTHf, + PORT_BASE_PRIf, + PORT_BASE_PRI_DUPf, + PORT_DFLT_SVIDf = 2190, + PORT_DIRf, + PORT_ENf, + PORT_IDf, + PORT_MASKf, + PORT_NUMf, + PORT_PFC_ENf, + PORT_WEIGHTf, + POW_SAR_ENf, + PPPOEf, + PPS_LATCH_PTP_TIME_NSEC_Hf = 2200, + PPS_LATCH_PTP_TIME_NSEC_Lf, + PPS_LATCH_PTP_TIME_SEC_Hf, + PPS_LATCH_PTP_TIME_SEC_Lf, + PPS_LATCH_PTP_TIME_SEC_Mf, + PRECISE_DROP_ALL_ENf, + PRECOLLAT_SELf, + PRIf, + PRI0f, + PRI0QNUMf, + PRI1f = 2210, + PRI1QNUMf, + PRI2f, + PRI2QNUMf, + PRI3f, + PRI3QNUMf, + PRI4f, + PRI4QNUMf, + PRI5f, + PRI5QNUMf, + PRI6f = 2220, + PRI6QNUMf, + PRI7f, + PRI7QNUMf, + PRI_ACT_HITf, + PRI_CTRL_BITf, + PRI_PFC_ENf, + PRI_PFC_RX_ENf, + PRI_PFC_TX_ENf, + PRI_RULE_IDXf, + PRMB_RCVY_OVTHR_MONf = 2230, + PROBE_SEL_AEf, + PROBE_SEL_AIf, + PTPBYPASS_ENf, + PTP_CLK125M_IN_SELf, + PTP_CLK_OUT_SELf, + PTP_DUMMY_RG02f, + PTP_DUMMY_RG03f, + PTP_DUMMY_RG53f, + PTP_DUMMY_RG54f, + PTP_DUMMY_RG55f = 2240, + PTP_DUMMY_RG56f, + PTP_DUMMY_RG57f, + PTP_DUMMY_RG58f, + PTP_DUMMY_RG59f, + PTP_DUMMY_RG60f, + PTP_DUMMY_RG61f, + PTP_ETH_ENf, + PTP_PPS_IN_SELf, + PTP_PPS_OUT_SELf, + PTP_TIMER_RESERVE_RG09f = 2250, + PTP_TIMER_RESERVE_RG10f, + PTP_TIMER_RESERVE_RG46f, + PTP_TIMER_RESERVE_RG47f, + PTP_TIME_CMDf, + PTP_TIME_EXECf, + PTP_TOD_IN_SELf, + PTP_TOD_OUT_SELf, + PTP_UDP_ENf, + PTP_VERSIONf, + PTR_BIST_DONEf = 2260, + PTR_BIST_ENf, + PTR_BIST_FAILf, + PTR_BIST_LOOP_MODEf, + PTR_BIST_MODEf, + PTR_BIST_RSTNf, + PTR_DRF_DONEf, + PTR_DRF_FAILf, + PTR_DRF_MODEf, + PTR_DRF_START_PAUSEf, + PTR_DRF_TEST_RESUMEf = 2270, + PTR_DYN_READ_ENf, + PTR_LSf, + PTR_RMAf, + PTR_RMBf, + PTR_RMEAf, + PTR_RMEBf, + PTR_TEST1Af, + PTR_TEST1Bf, + PUB_PAGEf, + PVIDf = 2280, + PWM_CLK_SELf, + PWM_DUTY_RATIOf, + PWM_OEf, + PWR_ON_BLINK_SELf, + P_LOAD_CNTRf, + P_LOAD_CNTR_IDXf, + P_PAGE_CNT_EGRf, + P_PAGE_CNT_IGRf, + P_PAGE_CURCNTf, + P_PAGE_PEAKCNT_EGRf = 2290, + P_PAGE_PEAKCNT_IGRf, + P_PG_REF_PORTf, + QEMPTYf, + QHSGMII_EEE_ENf, + Q_PAGE_CNTf, + Q_PAGE_PEAKCNTf, + Q_PKT_CNTf, + Q_PKT_PEAKCNTf, + RAN0_31f, + RAN32_47f = 2300, + RATEf, + RATE_MASK_15_0f, + RATE_MASK_31_16f, + RATE_MODE_CPUf, + RCRCEPEf, + RDM_SEED_REGADDRf, + RD_CLKOUT_RUNf, + RD_ISR_PPS_If, + RD_ISR_PTPf, + RD_MSG_TYPEf = 2310, + RD_PORT_IDf, + RD_PTP_TIME_NSEC_Hf, + RD_PTP_TIME_NSEC_Lf, + RD_PTP_TIME_SEC_Hf, + RD_PTP_TIME_SEC_Lf, + RD_PTP_TIME_SEC_Mf, + RD_SEQ_ID_Hf, + RD_SEQ_ID_Lf, + RD_TX_TIMESTAMP_NSEC_Hf, + RD_TX_TIMESTAMP_NSEC_Lf = 2320, + RD_TX_TIMESTAMP_SEC_Hf, + RD_TX_TIMESTAMP_SEC_Lf, + RD_TX_TIMESTAMP_VALIDf, + READHSBf, + READ_DATAf, + READ_MODEf, + READ_MTHDf, + REASONf, + REASON_ENf, + REF_RXCNGSTf = 2330, + REF_RXLPIf, + REF_RX_CONGESTf, + REF_RX_IDLEf, + REG0_BIT_2P5G_10GPHYf, + REG0_DEV_2P5G_10GPHYf, + REG0_REG_2P5G_10GPHYf, + REG10_BIT_2P5G_10GPHYf, + REG10_DEV_2P5G_10GPHYf, + REG10_REG_2P5G_10GPHYf, + REG9_BIT_2P5G_10GPHYf = 2340, + REG9_DEV_2P5G_10GPHYf, + REG9_REG_2P5G_10GPHYf, + REGIF_AC_ADDRf, + REGIF_AC_SOURf, + REGIF_TIME_OUTf, + REG_Af, + REG_ADCCKSELf, + REG_ADDR_4_0f, + REG_ADDR_AEf, + REG_ADDR_AIf = 2350, + REG_ADDR_PTPf, + REG_Bf, + REG_BIASDEM_ENf, + REG_CHOPENf, + REG_CHOPFREQSELf, + REG_CKREFBUF_CML_I_APHYf, + REG_CKREFBUF_CML_I_SDSf, + REG_CKREFBUF_ENf, + REG_CMU_TEST_EN_XTALf, + REG_DATA_AE_Hf = 2360, + REG_DATA_AE_Lf, + REG_DATA_AI_Hf, + REG_DATA_AI_Lf, + REG_DATA_PTPf, + REG_DIVIDER_SEL0f, + REG_DIVIDER_SEL1f, + REG_EN_CH_SEL_MANUAL0f, + REG_EN_CH_SEL_MANUAL1f, + REG_EN_CH_SEL_MANUAL2f, + REG_EN_CH_SEL_MANUAL3f = 2370, + REG_EN_CKR_SEL_MANUAL0f, + REG_EN_CKR_SEL_MANUAL1f, + REG_EN_CKR_SEL_MANUAL2f, + REG_EN_CKR_SEL_MANUAL3f, + REG_EN_ICG_MANUAL0f, + REG_EN_ICG_MANUAL1f, + REG_EN_LATCHf, + REG_EN_LOCK_SEL_MANUAL0f, + REG_EN_LOCK_SEL_MANUAL1f, + REG_EN_SYNC_OUT_MANUAL0f = 2380, + REG_EN_SYNC_OUT_MANUAL1f, + REG_HOLD_DLYf, + REG_HOLD_ENf, + REG_IF_SELf, + REG_OSRf, + REG_PHY_SEL0f, + REG_PHY_SEL1f, + REG_PIN_SEL_25M_TEST_ENf, + REG_RD_REQ_AEf, + REG_RD_REQ_AIf = 2390, + REG_RD_REQ_PTPf, + REG_SYNC_LOCK_OUT_SEL0f, + REG_SYNC_LOCK_OUT_SEL1f, + REG_WR_REQ_AEf, + REG_WR_REQ_AIf, + REG_WR_REQ_PTPf, + REPORT_FWDf, + REPORT_LEAVE_FWDf, + REPORT_SUPPRESSIONf, + RESERVEDf = 2400, + RESERVED_0078_PORT4f, + RESERVED_0078_PORT5f, + RESERVED_0078_PORT6f, + RESERVED_0078_PORT7f, + RESERVED_007C_PORT4f, + RESERVED_007C_PORT5f, + RESERVED_007C_PORT6f, + RESERVED_007C_PORT7f, + RETRY_CHKf, + RETRY_LOOPf = 2410, + RFC1042_OUI_IGNOREf, + RG_ETH_PAUSE_DECT_ENf, + RG_H2E_BYPASS_MODEf, + RG_H2E_ENABLEf, + RG_H2E_MACSEC_IFG_ENf, + RG_H2E_MAC_SA_Hf, + RG_H2E_MAC_SA_Lf, + RG_H2E_PADDING_ENf, + RG_H2E_PADDING_MACSECf, + RG_H2E_PADDING_VLANf = 2420, + RG_PAUSE_ACCEPT_MAC_SAf, + RG_PRMB_NUMf, + RG_SDS_PAUSE_DECT_ENf, + RING_RATE_REGADDRf, + RL3CEPEf, + RL4CEPEf, + RLDPf, + RLDP_ENf, + RLDP_ICPU_ENf, + RLDP_LED_ENABLEf = 2430, + RLDP_MODEf, + RLFD_BIT_2P5G_10GPHYf, + RLFD_DEV_2P5G_10GPHYf, + RLFD_ENf, + RLFD_REG_2P5G_10GPHYf, + RLFD_SELf, + RLFD_STSf, + RLPPf, + RLPP_TRAPf, + RL_IDf = 2440, + RL_VIDf, + RMA_ACT_00f, + RMA_ACT_01f, + RMA_ACT_02f, + RMA_ACT_03f, + RMA_ACT_04f, + RMA_ACT_08f, + RMA_ACT_0Df, + RMA_ACT_0Ef, + RMA_ACT_10f = 2450, + RMA_ACT_11f, + RMA_ACT_12f, + RMA_ACT_13f, + RMA_ACT_18f, + RMA_ACT_1Af, + RMA_ACT_20f, + RMA_ACT_21f, + RMA_ACT_22f, + RMA_ACT_CDPf, + RMA_ACT_CSSTPf = 2460, + RMA_ACT_LLDPf, + RMA_TRAP_PRIf, + RMCRC_ENf, + RMK1P_BYPASS_REALKEEPf, + RMK_ACT_HITf, + RMK_CTRL_BITf, + ROBUSTNESS_VARf, + ROUTER_PORT_FORBID_1f, + ROUTER_PORT_FORBID_2f, + RRCPf = 2470, + RRCP_MDOEf, + RRCP_TRAPf, + RRRND_SRC_SELf, + RRSTEP_4_0f, + RRUPD_ENf, + RRUPD_ONCEf, + RRUPD_PERIODf, + RR_FRC_MODEf, + RR_FRC_VAL_19_10f, + RR_FRC_VAL_9_0f = 2480, + RR_RD_VAL_19_10f, + RR_RD_VAL_9_0f, + RR_SEL_MTHDf, + RSC_FIFO_BIST_DONEf, + RSC_FIFO_BIST_FAILf, + RSC_FIFO_DRF_BIST_DONEf, + RSC_FIFO_DRF_BIST_FAILf, + RSC_FIFO_DRF_START_PAUSEf, + RSRND_SRC_SELf, + RSTf = 2490, + RSTB_TMf, + RSTR_ORI_AUTO_DET_SGf, + RST_GLB_MIBf, + RST_MIB_VALf, + RST_PORT_FLAGf, + RST_PORT_MIBf, + RSUPD_ENf, + RSUPD_ONCEf, + RSUPD_PERIODf, + RS_BYPASSf = 2500, + RS_FB_ONf, + RS_FRC_MODEf, + RS_FRC_VAL_9_0f, + RS_LINK_FAULT_INDI_OFFf, + RS_LINK_FAULT_LINT_OFFf, + RS_LINK_FAULT_LOCAL_OFFf, + RS_LINK_FAULT_REMOTE_OFFf, + RS_PASS_FAULT2MACf, + RS_RD_VAL_9_0f, + RS_SEQ_CONVf = 2510, + RTAG_IFf, + RTL_IDf, + RTL_VIDf, + RWOPf, + RXAPEf, + RXBPEf, + RXDV_GMASKf, + RXFIFO_DGLT_ENf, + RXFIFO_FULL_THf, + RXFIFO_OVERFLOW_ERRf = 2520, + RXFIFO_OVERFLOW_ERR_MSKf, + RXFIFO_OVERFLOW_STSf, + RXFIFO_RDEMPTY_ERRf, + RXFIFO_RDEMPTY_ERR_MSKf, + RXFIFO_RDEMPTY_STSf, + RXFSTf, + RXIDLE_Df, + RXIEf, + RXISf, + RXLINE_CRCERR_CNT_Hf = 2530, + RXLINE_CRCERR_CNT_INCRf, + RXLINE_CRCERR_CNT_Lf, + RXLINE_GERR_CNT_Hf, + RXLINE_GERR_CNT_Lf, + RXLINE_GLPIERR_CNT_Hf, + RXLINE_GLPIERR_CNT_Lf, + RXLINE_MINIPGf, + RXLINE_OK_CNT_0f, + RXLINE_OK_CNT_1f, + RXLINE_OK_CNT_2f = 2540, + RXLINE_OK_CNT_3f, + RXLINE_OVERFLOW_CNT_INCRf, + RXLINE_PKTERR_CNT_Hf, + RXLINE_PKTERR_CNT_INCRf, + RXLINE_PKTERR_CNT_Lf, + RXLINE_PMBNUMf, + RXLINE_SHORTPKT_CNT_Hf, + RXLINE_SHORTPKT_CNT_Lf, + RXLINE_WRP2IP_FSMf, + RXLINE_XG2IP_FSMf = 2550, + RXLINE_XGMINIFGf, + RXMPEf, + RXMSKDELAY_VALf, + RXMTUf, + RXPADf, + RXPORTf, + RXPORT_DSC_ERRf, + RXPORT_DSC_ERR_MSKf, + RXPORT_DSC_STSf, + RXPPSf = 2560, + RXSTOP_ADDRf, + RXSYS_AVG_IPGf, + RXSYS_CLASSDROP_ENf, + RXSYS_CRCERR_CNT_Hf, + RXSYS_CRCERR_CNT_INCRf, + RXSYS_CRCERR_CNT_Lf, + RXSYS_CRCERR_INVRSCRC_ENf, + RXSYS_DECRYPTSRT_CNT_Hf, + RXSYS_DECRYPTSRT_CNT_Lf, + RXSYS_DROP_CNT_Hf = 2570, + RXSYS_DROP_CNT_INCRf, + RXSYS_DROP_CNT_Lf, + RXSYS_DSC_ERR_MSKf, + RXSYS_FIFO_FTUNEf, + RXSYS_FIFO_TSHDf, + RXSYS_GERR_CNT_Hf, + RXSYS_GERR_CNT_Lf, + RXSYS_GMIIER_INVRSCRC_ENf, + RXSYS_INNERVLAN1f, + RXSYS_INNERVLAN2f = 2580, + RXSYS_INNERVLAN3f, + RXSYS_INNERVLAN4f, + RXSYS_INNERVLAN5f, + RXSYS_INNERVLAN6f, + RXSYS_INNERVLAN7f, + RXSYS_IP2WRP_FSMf, + RXSYS_IP2XG_FSMf, + RXSYS_LPIEXIT_Tf, + RXSYS_MINIPGf, + RXSYS_OK_CNT_0f = 2590, + RXSYS_OK_CNT_1f, + RXSYS_OK_CNT_2f, + RXSYS_OK_CNT_3f, + RXSYS_OUTERVLAN1f, + RXSYS_OUTERVLAN2f, + RXSYS_OUTERVLAN3f, + RXSYS_OUTERVLAN4f, + RXSYS_PAD_DECRYPTSRT_ENf, + RXSYS_PAD_LINESRT_ENf, + RXSYS_PAD_VLAN_ENf = 2600, + RXSYS_PKTERR_CNT_Hf, + RXSYS_PKTERR_CNT_INCRf, + RXSYS_PKTERR_CNT_Lf, + RXSYS_PKTERR_INVRSCRC_ENf, + RXSYS_PMBNUMf, + RXSYS_UNDERRUN_CNT_INCRf, + RXSYS_WAIT_Tf, + RX_CHK_CRC_ENf, + RX_CNT_TAGf, + RX_ENf = 2610, + RX_GATINGf, + RX_G_IOSAMEPMBf, + RX_IDLE_TIMERf, + RX_IPBYPASS_ENf, + RX_IPILOCK_IMRf, + RX_IPILOCK_ISRf, + RX_IPILOCK_XG_IMRf, + RX_IPILOCK_XG_ISRf, + RX_IPISECFAIL_IMRf, + RX_IPISECFAIL_ISRf = 2620, + RX_IPI_GLB_IMRf, + RX_IPI_GLB_ISRf, + RX_IPRST_Nf, + RX_LPI_DLY_CYCLEf, + RX_MACSECBYPASS_ENf, + RX_MTUf, + RX_PAUSE_ENf, + RX_PAUSE_STS_8_0f, + RX_PAUSE_STS_9_0f, + RX_PMSKf = 2630, + RX_STROM_BCAST_ENf, + RX_STROM_BCAST_MIDXf, + RX_STROM_MCAST_ENf, + RX_STROM_MCAST_MIDXf, + RX_STROM_UNMCAST_ENf, + RX_STROM_UNMCAST_MIDXf, + RX_STROM_UNUCAST_ENf, + RX_STROM_UNUCAST_MIDXf, + RX_SWRST_ENf, + RX_SYM_ERR_TGXR0f = 2640, + RX_TAG_ENf, + RX_XGDIC_ENf, + RX_XGMASKf, + SAMPLE_PKT_CNTf, + SAR_REFf, + SAR_REG_WTf, + SCHED_TYPEf, + SCK_FREQ_SELf, + SCL_FREQf, + SCL_OUT_SELf = 2650, + SDf, + SDA_OUT_SELf, + SDS01_AUTODET_EN_INIf, + SDS01_AUTONEG_EN_INIf, + SDS01_CMD_STOP_GLI_CLKf, + SDS01_FIB100_DETf, + SDS01_FIB100_SDETf, + SDS01_FIB_ISOf, + SDS01_FRC_REG4_ENf, + SDS01_FRC_REG4_FIB100f = 2660, + SDS01_LPI_GMII_SELf, + SDS01_PAUSE_INIf, + SDS01_PDOWN_EN_INIf, + SDS01_SDS_FRC_LDf, + SDS01_SDS_LINK_OKf, + SDS01_SDS_LINK_OK_SUMf, + SDS01_SDS_PHY_MODEf, + SDS01_SDS_RX_DISABLEf, + SDS01_SDS_RX_SYM_ERR_ALLf, + SDS01_SDS_SDET_OUTf = 2670, + SDS01_SDS_TX_DISABLEf, + SDS01_SILENT_EN_INIf, + SDS01_STS_UPD_RXf, + SDS01_STS_UPD_TXf, + SDS01_UNIDIR_TX_ABLEf, + SDS0_CH0_RO_ABLTYf, + SDS0_CH1_RO_ABLTYf, + SDS0_CH2_RO_ABLTYf, + SDS0_CH3_RO_ABLTYf, + SDS0_MODE_ROf = 2680, + SDS0_MODE_SELf, + SDS0_SUB_MODE_ROf, + SDS0_USX_SUB_MODEf, + SDS1_CH0_RO_ABLTYf, + SDS1_MODE_ROf, + SDS1_MODE_SELf, + SDS1_SUB_MODE_ROf, + SDS1_USX_SUB_MODEf, + SDS2PHY_EEE_FLG_DLY0f, + SDS2PHY_EEE_FLG_DLY1f = 2690, + SDS2PHY_EEE_FLG_DLY2f, + SDS2PHY_EEE_FLG_DLY3f, + SDS_CH0_RX_CRC_ERRORSf, + SDS_CH0_RX_GOOD_OCTETS_Hf, + SDS_CH0_RX_GOOD_OCTETS_Lf, + SDS_CH0_RX_GOOD_PKTS_Hf, + SDS_CH0_RX_GOOD_PKTS_Lf, + SDS_CH0_RX_SYMBOL_ERRORSf, + SDS_CH0_RX_TOTAL_PKTS_Hf, + SDS_CH0_RX_TOTAL_PKTS_Lf = 2700, + SDS_CH0_TX_CRC_ERRORSf, + SDS_CH0_TX_GOOD_OCTETS_Hf, + SDS_CH0_TX_GOOD_OCTETS_Lf, + SDS_CH0_TX_GOOD_PKTS_Hf, + SDS_CH0_TX_GOOD_PKTS_Lf, + SDS_CH0_TX_TOTAL_PKTS_Hf, + SDS_CH0_TX_TOTAL_PKTS_Lf, + SDS_CH1_RX_CRC_ERRORSf, + SDS_CH1_RX_GOOD_OCTETS_Hf, + SDS_CH1_RX_GOOD_OCTETS_Lf = 2710, + SDS_CH1_RX_GOOD_PKTS_Hf, + SDS_CH1_RX_GOOD_PKTS_Lf, + SDS_CH1_RX_SYMBOL_ERRORSf, + SDS_CH1_RX_TOTAL_PKTS_Hf, + SDS_CH1_RX_TOTAL_PKTS_Lf, + SDS_CH1_TX_CRC_ERRORSf, + SDS_CH1_TX_GOOD_OCTETS_Hf, + SDS_CH1_TX_GOOD_OCTETS_Lf, + SDS_CH1_TX_GOOD_PKTS_Hf, + SDS_CH1_TX_GOOD_PKTS_Lf = 2720, + SDS_CH1_TX_TOTAL_PKTS_Hf, + SDS_CH1_TX_TOTAL_PKTS_Lf, + SDS_CH2_RX_CRC_ERRORSf, + SDS_CH2_RX_GOOD_OCTETS_Hf, + SDS_CH2_RX_GOOD_OCTETS_Lf, + SDS_CH2_RX_GOOD_PKTS_Hf, + SDS_CH2_RX_GOOD_PKTS_Lf, + SDS_CH2_RX_SYMBOL_ERRORSf, + SDS_CH2_RX_TOTAL_PKTS_Hf, + SDS_CH2_RX_TOTAL_PKTS_Lf = 2730, + SDS_CH2_TX_CRC_ERRORSf, + SDS_CH2_TX_GOOD_OCTETS_Hf, + SDS_CH2_TX_GOOD_OCTETS_Lf, + SDS_CH2_TX_GOOD_PKTS_Hf, + SDS_CH2_TX_GOOD_PKTS_Lf, + SDS_CH2_TX_TOTAL_PKTS_Hf, + SDS_CH2_TX_TOTAL_PKTS_Lf, + SDS_CH3_RX_CRC_ERRORSf, + SDS_CH3_RX_GOOD_OCTETS_Hf, + SDS_CH3_RX_GOOD_OCTETS_Lf = 2740, + SDS_CH3_RX_GOOD_PKTS_Hf, + SDS_CH3_RX_GOOD_PKTS_Lf, + SDS_CH3_RX_SYMBOL_ERRORSf, + SDS_CH3_RX_TOTAL_PKTS_Hf, + SDS_CH3_RX_TOTAL_PKTS_Lf, + SDS_CH3_TX_CRC_ERRORSf, + SDS_CH3_TX_GOOD_OCTETS_Hf, + SDS_CH3_TX_GOOD_OCTETS_Lf, + SDS_CH3_TX_GOOD_PKTS_Hf, + SDS_CH3_TX_GOOD_PKTS_Lf = 2750, + SDS_CH3_TX_TOTAL_PKTS_Hf, + SDS_CH3_TX_TOTAL_PKTS_Lf, + SDS_CMDf, + SDS_INDEXf, + SDS_MODEL_NOf, + SDS_MODEL_NO_TGRf, + SDS_PAGEf, + SDS_RDf, + SDS_REGADf, + SDS_REG_RSTf = 2760, + SDS_REVISION_NOf, + SDS_REVISION_NO_TGRf, + SDS_RTK_OUIf, + SDS_RTK_OUI_TGRf, + SDS_RWOPf, + SDS_WDf, + SELF_GPIf, + SET0_LED0_SEL0f, + SET0_LED0_SEL1f, + SET0_LED1_SEL0f = 2770, + SET0_LED1_SEL1f, + SET0_LED2_SEL0f, + SET0_LED2_SEL1f, + SET0_LED3_SEL0f, + SET0_LED3_SEL1f, + SET1_LED0_SEL0f, + SET1_LED0_SEL1f, + SET1_LED1_SEL0f, + SET1_LED1_SEL1f, + SET1_LED2_SEL0f = 2780, + SET1_LED2_SEL1f, + SET1_LED3_SEL0f, + SET1_LED3_SEL1f, + SET2_LED0_SEL0f, + SET2_LED0_SEL1f, + SET2_LED1_SEL0f, + SET2_LED1_SEL1f, + SET2_LED2_SEL0f, + SET2_LED2_SEL1f, + SET2_LED3_SEL0f = 2790, + SET2_LED3_SEL1f, + SET3_LED0_SEL0f, + SET3_LED0_SEL1f, + SET3_LED1_SEL0f, + SET3_LED1_SEL1f, + SET3_LED2_SEL0f, + SET3_LED2_SEL1f, + SET3_LED3_SEL0f, + SET3_LED3_SEL1f, + SIP16_0f = 2800, + SIP31_17f, + SLOT_TIMEf, + SLOW_CLK_TG1_RATEf, + SLOW_DOWN_PLL_ENf, + SLV_CLK_EDGE_SELf, + SMAC1_0f, + SMAC33_2f, + SMAC47_34f, + SMI0_BROADCAST_SET_ENf, + SMI0_DLY_CFGf = 2810, + SMI0_FREQ_SELf, + SMI0_MDC_ENf, + SMI0_PREAMBLE_SELf, + SMI1_BROADCAST_SET_ENf, + SMI1_DLY_CFGf, + SMI1_FREQ_SELf, + SMI1_MDC_ENf, + SMI1_PREAMBLE_SELf, + SMI2_BROADCAST_SET_ENf, + SMI2_DLY_CFGf = 2820, + SMI2_FREQ_SELf, + SMI2_MDC_ENf, + SMI2_PREAMBLE_SELf, + SMI_DGL_EN_8224f, + SMI_FORCE_FC_ENf, + SMI_GLB_RSTf, + SMI_MMD_SPf, + SMI_POLLING_MASKf, + SMI_POLLING_SEL0f, + SMI_POLLING_SEL1f = 2830, + SMI_POLLING_SEL2f, + SMI_POLLING_SEL3f, + SMI_POLLING_SEL4f, + SMI_POLLING_SEL5f, + SMI_POLLING_SEL6f, + SMI_POLLING_SEL7f, + SMI_POLLING_SEL8f, + SMI_PRVTE1_POLLING8_0f, + SMI_PRVTE_POLLING8_0f, + SNAPf = 2840, + SPAf, + SPA_ENf, + SPD_SELf, + SPD_STS_8_0f, + SPD_STS_9_0f, + SPD_UP_REFILLf, + SPG_MODEf, + SPG_PREAMBLE_CONTENT0f, + SPG_PREAMBLE_CONTENT1f, + SPG_PREAMBLE_CONTENT2f = 2850, + SPG_PREAMBLE_LENGTHf, + SPIF_CK2f, + SPI_ADDRf, + SPI_BIST_DONEf, + SPI_BIST_FAILf, + SPI_BIST_LOOP_MODEf, + SPI_BIST_MODEf, + SPI_BIST_RSTNf, + SPI_CLK_DIVf, + SPI_CLK_DLYf = 2860, + SPI_CMDf, + SPI_CMD_TYPEf, + SPI_CPHAf, + SPI_CPOLf, + SPI_DATAf, + SPI_DRF_BIST_DONEf, + SPI_DRF_BIST_FAILf, + SPI_DRF_BIST_MODEf, + SPI_DRF_START_PAUSEf, + SPI_DRF_TEST_RESUMEf = 2870, + SPI_DYN_READ_ENf, + SPI_LSf, + SPI_OUT_SELf, + SPI_RMf, + SPI_RMEf, + SPI_RX_DLYf, + SPI_SO_REFf, + SPI_TCHSHf, + SPI_TEST1f, + SPI_TIMEOUT_FLAGf = 2880, + SPI_TIMEOUT_SETf, + SPI_TRIGf, + SPI_TSLCHf, + SPI_TX_DLYf, + SPRISELf, + SRAM_ACCCESS_CMDf, + SRAM_ADDRESSf, + SRC_PERMIT_ENf, + STAGf, + STAG_IFf = 2890, + START_MIBf, + STIC_PMSKf, + STOP_BITf, + STORM_BCAST_EXT_ENf, + STORM_BCAST_EXT_METERIDf, + STORM_EXT_EN_PORTMASKf, + STORM_MCAST_EXT_ENf, + STORM_MCAST_EXT_METERIDf, + STORM_UNKNOWN_MCAST_EXT_ENf, + STORM_UNKNOWN_MCAST_EXT_METERIDf = 2900, + STORM_UNKNOWN_UCAST_EXT_ENf, + STORM_UNKNOWN_UCAST_EXT_METERIDf, + STP1_PWR_ON_LEDf, + STP2_PWR_ON_LEDf, + STRAP_INFO_ROf, + STREAM_CONTENT_MOD_0f, + STREAM_CONTENT_OFFSET_0f, + STREAM_DA_ADD_CNT_0f, + STREAM_DA_MOD_0f, + STREAM_ETHERTYPEf = 2910, + STREAM_ETHERTYPE_MODf, + STREAM_FIX_DMAC_Hf, + STREAM_FIX_DMAC_Lf, + STREAM_FIX_SMAC_Hf, + STREAM_FIX_SMAC_Lf, + STREAM_LEN_MODf, + STREAM_LEN_RNG_ENDf, + STREAM_LEN_RNG_END_0f, + STREAM_LEN_RNG_STARTf, + STREAM_LEN_RNG_START_0f = 2920, + STREAM_LEN_TYPE_0f, + STREAM_PAYLOAD_ACCCESS_TRIGGERf, + STREAM_PAYLOAD_MASKf, + STREAM_PAYLOAD_MODf, + STREAM_PAYLOAD_SRAM_DATAf, + STREAM_REPEAT_CONTENT_0f, + STREAM_SA_ADD_CNT_0f, + STREAM_SA_MOD_0f, + STRICT_ENf, + STRIC_WFQ_JUMBO_BUG_FIXf = 2930, + STRP_DIS_POR_DBG_8224f, + STRP_EN_SLV_MDC_DEGf, + STSf, + SVID_ASSIGNf, + SVLAN_ACT_HITf, + SVLAN_CTRL_BITf, + SVLAN_RULE_IDXf, + SVLAN_WEIGHTf, + SWITCH_IEf, + SW_CHIP_RSTf = 2940, + SW_CTRL_LED_ENf, + SW_INT_MODEf, + SW_INT_ODf, + SW_INT_PULSE_INTERVALf, + SW_LED0_MODEf, + SW_LED1_MODEf, + SW_LED2_MODEf, + SW_LED3_MODEf, + SW_LED_LOADf, + SW_MAC_ADDR_31_0f = 2950, + SW_MAC_ADDR_47_32f, + SW_NIC_RSTf, + SW_Q_RSTf, + SW_Q_RST_ASIC_CNTf, + SW_Q_RST_P_THRf, + SW_Q_RST_SYS_THRf, + SW_RSTf, + SW_SERDES_RSTf, + SYN1024f, + SYNCELOCK0_SELf = 2960, + SYNCELOCK1_SELf, + SYNCE_DUMMY1f, + SYNCE_DUMMY2f, + SYNCE_DUMMY3f, + SYNCE_DUMMY4f, + SYNCE_DUMMY5f, + SYNCE_EN0f, + SYNCE_EN1f, + SYNFINSCANf, + SYSLPBK_ENf = 2970, + SYS_LED_ENf, + SYS_LED_MODEf, + SYS_USED_PAGE_THRf, + TABLE_FULL_OPf, + TABLE_RSTf, + TAG_ADDf, + TAG_RMf, + TBLf, + TBL_ADDRf, + TBL_TYPEf = 2980, + TBUF_DELAYf, + TCAM_BIST_DONE_Hf, + TCAM_BIST_DONE_Lf, + TCAM_BIST_DYN_READ_EN_Hf, + TCAM_BIST_DYN_READ_EN_Lf, + TCAM_BIST_FAIL_Hf, + TCAM_BIST_FAIL_Lf, + TCAM_BIST_GRP_EN_Hf, + TCAM_BIST_GRP_EN_Lf, + TCAM_BIST_LOOP_EN_Hf = 2990, + TCAM_BIST_LOOP_EN_Lf, + TCAM_BIST_MODE_Hf, + TCAM_BIST_MODE_Lf, + TCAM_BIST_RSTN_Hf, + TCAM_BIST_RSTN_Lf, + TCAM_DRF_DONE_Hf, + TCAM_DRF_DONE_Lf, + TCAM_DRF_FAIL_Hf, + TCAM_DRF_FAIL_Lf, + TCAM_DRF_MODE_Hf = 3000, + TCAM_DRF_MODE_Lf, + TCAM_DRF_PAUSE_Hf, + TCAM_DRF_PAUSE_Lf, + TCAM_DRF_RESUME_Hf, + TCAM_DRF_RESUME_Lf, + TCAM_MDS_Hf, + TCAM_MDS_Lf, + TCAM_RDS_Hf, + TCAM_RDS_Lf, + TCAM_UDS_Hf = 3010, + TCAM_UDS_Lf, + TCPf, + TCPFRAGERRf, + TCPSHORTHDRf, + TEMP_OUT_POWERON_18_3f, + TEMP_OUT_POWERON_2_0f, + TEST_CUTf, + TGR_ECC_ENf, + TG_SFD_FB_DIS_RXf, + TG_SFD_FB_DIS_TXf = 3020, + THRf, + THR_OFFf, + THR_ONf, + TICKf, + TIMER1f, + TIMER2f, + TIMER_GPIO_OEf, + TIMER_GPOf, + TIME_OP_DURATIONf, + TKNf = 3030, + TLB_ACTf, + TLB_EXECUTEf, + TLB_TYPEf, + TMLSB_2_0f, + TMTENBITf, + TM_ADC_OUTf, + TM_HIGHCMP_ENf, + TM_HIGH_THRf, + TM_LOWCMP_ENf, + TM_LOW_THRf = 3040, + TM_MAX_18_3f, + TM_MAX_2_0f, + TM_MIN_18_3f, + TM_MIN_2_0f, + TM_OUT_18_3f, + TM_OUT_2_0f, + TOD_DATAf, + TOD_DATA_LENf, + TOD_DELAYf, + TOD_DUMMYf = 3050, + TOD_SARP_GPS_SEC_Hf, + TOD_SARP_GPS_SEC_Lf, + TOD_SARP_GPS_WEEKf, + TOKEN_ERRf, + TOKEN_ERR_MSKf, + TOKEN_STSf, + TOSf, + TPIDf, + TRAIN_SRC0f, + TRAIN_SRC1f = 3060, + TRAP_CPU_SELf, + TRAP_PRIf, + TRK_FLCTRL_ENf, + TRK_PMSKf, + TRUNK_FLDf, + TXEEf, + TXEN_GMASKf, + TXESf, + TXFIFO_DGLT_ENf, + TXFIFO_FULL_THf = 3070, + TXFIFO_OVERFLOW_ERRf, + TXFIFO_OVERFLOW_ERR_MSKf, + TXFIFO_OVERFLOW_STSf, + TXFIFO_RDEMPTY_ERRf, + TXFIFO_RDEMPTY_ERR_MSKf, + TXFIFO_RDEMPTY_STSf, + TXLIEN_LPIEXIT_Tf, + TXLINE_AVG_IPGf, + TXLINE_CLASSDROP_ENf, + TXLINE_CRCERR_CNT_Hf = 3080, + TXLINE_CRCERR_CNT_INCRf, + TXLINE_CRCERR_CNT_Lf, + TXLINE_CRCERR_INVRSCRC_ENf, + TXLINE_DROP_CNT_Hf, + TXLINE_DROP_CNT_INCRf, + TXLINE_DROP_CNT_Lf, + TXLINE_FIFO_TSHDf, + TXLINE_GERR_CNT_Hf, + TXLINE_GERR_CNT_Lf, + TXLINE_GMIIER_INVRSCRC_ENf = 3090, + TXLINE_IP2WRP_FSMf, + TXLINE_IP2XG_FSMf, + TXLINE_MINIFGf, + TXLINE_OK_CNT_0f, + TXLINE_OK_CNT_1f, + TXLINE_OK_CNT_2f, + TXLINE_OK_CNT_3f, + TXLINE_PAD_ENf, + TXLINE_PAD_MACSEC_ENf, + TXLINE_PAD_VLAN_ENf = 3100, + TXLINE_PKTERR_CNT_Hf, + TXLINE_PKTERR_CNT_INCRf, + TXLINE_PKTERR_CNT_Lf, + TXLINE_PKTERR_INVRSCRC_ENf, + TXLINE_PMBNUMf, + TXLINE_SRTPKT_CNT_Hf, + TXLINE_SRTPKT_CNT_Lf, + TXLINE_UNDERRUN_CNT_INCRf, + TXLINE_WAIT_Tf, + TXMSKDELAY_VALf = 3110, + TXQ_BIST_DONE_1_0f, + TXQ_BIST_FAIL_9_0f, + TXQ_BIST_GRP_ENf, + TXQ_BIST_LOOP_1_0f, + TXQ_BIST_MODE_1_0f, + TXQ_BIST_RSTBf, + TXQ_DRF_BIST_DONE_1_0f, + TXQ_DRF_BIST_FAIL_9_0f, + TXQ_DRF_BIST_MODE_1_0f, + TXQ_DRF_START_PAUSE_1_0f = 3120, + TXQ_DRF_TEST_RESUME_1_0f, + TXQ_DYN_READ_1_0f, + TXQ_LSf, + TXQ_SRAM_RMEf, + TXQ_SRAM_RM_3_0f, + TXQ_TEST1f, + TXSTOP_ADDRf, + TXSYS_CRCERR_CNT_Hf, + TXSYS_CRCERR_CNT_INCRf, + TXSYS_CRCERR_CNT_Lf = 3130, + TXSYS_FLOWIDf, + TXSYS_GERR_CNT_Hf, + TXSYS_GERR_CNT_Lf, + TXSYS_GLPIERR_CNT_Hf, + TXSYS_GLPIERR_CNT_Lf, + TXSYS_INNERVLAN1f, + TXSYS_INNERVLAN2f, + TXSYS_INNERVLAN3f, + TXSYS_INNERVLAN4f, + TXSYS_INNERVLAN5f = 3140, + TXSYS_INNERVLAN6f, + TXSYS_INNERVLAN7f, + TXSYS_MINIFGf, + TXSYS_OK_CNT_0f, + TXSYS_OK_CNT_1f, + TXSYS_OK_CNT_2f, + TXSYS_OK_CNT_3f, + TXSYS_OUTERVLAN1f, + TXSYS_OUTERVLAN2f, + TXSYS_OUTERVLAN3f = 3150, + TXSYS_OUTERVLAN4f, + TXSYS_OVERFLOW_CNT_INCRf, + TXSYS_PKTERR_CNT_Hf, + TXSYS_PKTERR_CNT_INCRf, + TXSYS_PKTERR_CNT_Lf, + TXSYS_PMBNUMf, + TXSYS_PTPCRYPT_ENf, + TXSYS_WRP2IP_FSMf, + TXSYS_XG2IP_FSMf, + TXSYS_XGMINIFGf = 3160, + TX_CNT_TAGf, + TX_DONE_PORTf, + TX_DSC_CHK_TMRf, + TX_ENf, + TX_GATINGf, + TX_G_IOSAMEPMBf, + TX_IDLE_TIMERf, + TX_IDLE_TMRf, + TX_IPBYPASS_ENf, + TX_IPELOCK_IMRf = 3170, + TX_IPELOCK_ISRf, + TX_IPELOCK_XG_IMRf, + TX_IPELOCK_XG_ISRf, + TX_IPESECFAIL_IMRf, + TX_IPESECFAIL_ISRf, + TX_IPE_GLB_IMRf, + TX_IPE_GLB_ISRf, + TX_IPRST_Nf, + TX_LPI_DLY_CYCLEf, + TX_LPI_MINIPG_10Gf = 3180, + TX_LPI_MINIPG_10GLITEf, + TX_LPI_MINIPG_2P5Gf, + TX_LPI_MINIPG_2P5GLITEf, + TX_LPI_MINIPG_5Gf, + TX_LPI_MINIPG_5GLITEf, + TX_LPI_MINIPG_FEf, + TX_LPI_MINIPG_GEf, + TX_LPI_MINIPG_GELITEf, + TX_MACSECBYPASS_ENf, + TX_MTUf = 3190, + TX_PAUSE_ENf, + TX_PAUSE_STS_8_0f, + TX_PAUSE_STS_9_0f, + TX_PAUSE_WAKE_TIMER_GEf, + TX_PAUSE_WAKE_TIMER_GELITEf, + TX_PMSKf, + TX_SWRST_ENf, + TX_WAKE_SELf, + TX_WAKE_TIMER_10Gf, + TX_WAKE_TIMER_10GLITEf = 3200, + TX_WAKE_TIMER_2P5Gf, + TX_WAKE_TIMER_2P5GLITEf, + TX_WAKE_TIMER_5Gf, + TX_WAKE_TIMER_5GLITEf, + TX_WAKE_TIMER_FEf, + TX_WAKE_TIMER_GEf, + TX_WAKE_TIMER_GELITEf, + TX_XGDIC_ENf, + TX_XGMASKf, + TYPEf = 3210, + UDF0f, + UDF10f, + UDF11_0_0f, + UDF11_15_1f, + UDF12f, + UDF13_0_0f, + UDF13_15_1f, + UDF14f, + UDF15_0_0f, + UDF15_15_1f = 3220, + UDF1_0_0f, + UDF1_15_1f, + UDF2f, + UDF3_0_0f, + UDF3_15_1f, + UDF4f, + UDF5_0_0f, + UDF5_15_1f, + UDF6f, + UDF7_0_0f = 3230, + UDF7_15_1f, + UDF8f, + UDF9_0_0f, + UDF9_15_1f, + UDPf, + UDPPTPf, + UDP_P0_ACTf, + UDV0f, + UDV1f, + UDV10f = 3240, + UDV11f, + UDV12f, + UDV13f, + UDV14f, + UDV15f, + UDV2f, + UDV3f, + UDV4f, + UDV5f, + UDV6f = 3250, + UDV7f, + UDV8f, + UDV9f, + UIFSEGf, + UNIDIR_ENf, + UNIDIR_WIN_DLYf, + UNKN_UC_ENf, + UNMATCH_SAf, + UNTAGf, + UNTAG_PRI_SRCf = 3260, + UNTAG_SVIDf, + UNUSED_000C_PORT4f, + UNUSED_000C_PORT5f, + UNUSED_000C_PORT6f, + UNUSED_000C_PORT7f, + UNUSED_0020_PORT4f, + UNUSED_0020_PORT5f, + UNUSED_0020_PORT6f, + UNUSED_0020_PORT7f, + UNUSED_0024_PORT4f = 3270, + UNUSED_0024_PORT5f, + UNUSED_0024_PORT6f, + UNUSED_0024_PORT7f, + UNUSED_005C_PORT4f, + UNUSED_005C_PORT5f, + UNUSED_005C_PORT6f, + UNUSED_005C_PORT7f, + UNUSED_0060_PORT4f, + UNUSED_0060_PORT5f, + UNUSED_0060_PORT6f = 3280, + UNUSED_0060_PORT7f, + UNUSED_0064_PORT4f, + UNUSED_0064_PORT5f, + UNUSED_0064_PORT6f, + UNUSED_0064_PORT7f, + UNUSED_0068_PORT4f, + UNUSED_0068_PORT5f, + UNUSED_0068_PORT6f, + UNUSED_0068_PORT7f, + UNUSED_006C_PORT4f = 3290, + UNUSED_006C_PORT5f, + UNUSED_006C_PORT6f, + UNUSED_006C_PORT7f, + UNUSED_0070_PORT4f, + UNUSED_0070_PORT5f, + UNUSED_0070_PORT6f, + UNUSED_0070_PORT7f, + UNUSED_0074_PORT4f, + UNUSED_0074_PORT5f, + UNUSED_0074_PORT6f = 3300, + UNUSED_0074_PORT7f, + UNUSED_011C_PORT4f, + UNUSED_011C_PORT5f, + UNUSED_011C_PORT6f, + UNUSED_011C_PORT7f, + UNUSED_0120_PORT4f, + UNUSED_0120_PORT5f, + UNUSED_0120_PORT6f, + UNUSED_0120_PORT7f, + UNUSED_0124_PORT4f = 3310, + UNUSED_0124_PORT5f, + UNUSED_0124_PORT6f, + UNUSED_0124_PORT7f, + UNUSED_0128_PORT4f, + UNUSED_0128_PORT5f, + UNUSED_0128_PORT6f, + UNUSED_0128_PORT7f, + UNUSED_012C_PORT4f, + UNUSED_012C_PORT5f, + UNUSED_012C_PORT6f = 3320, + UNUSED_012C_PORT7f, + UNUSED_0130_PORT4f, + UNUSED_0130_PORT5f, + UNUSED_0130_PORT6f, + UNUSED_0130_PORT7f, + UNUSED_0134_PORT4f, + UNUSED_0134_PORT5f, + UNUSED_0134_PORT6f, + UNUSED_0134_PORT7f, + UNUSED_0138_PORT4f = 3330, + UNUSED_0138_PORT5f, + UNUSED_0138_PORT6f, + UNUSED_0138_PORT7f, + UNUSED_013C_PORT4f, + UNUSED_013C_PORT5f, + UNUSED_013C_PORT6f, + UNUSED_013C_PORT7f, + UNUSED_014C_PORT4f, + UNUSED_014C_PORT5f, + UNUSED_014C_PORT6f = 3340, + UNUSED_014C_PORT7f, + UNUSED_0150_PORT4f, + UNUSED_0150_PORT5f, + UNUSED_0150_PORT6f, + UNUSED_0150_PORT7f, + UNUSED_0154_PORT4f, + UNUSED_0154_PORT5f, + UNUSED_0154_PORT6f, + UNUSED_0154_PORT7f, + UNUSED_0158_PORT4f = 3350, + UNUSED_0158_PORT5f, + UNUSED_0158_PORT6f, + UNUSED_0158_PORT7f, + UNUSED_015C_PORT4f, + UNUSED_015C_PORT5f, + UNUSED_015C_PORT6f, + UNUSED_015C_PORT7f, + UNUSED_0160_PORT4f, + UNUSED_0160_PORT5f, + UNUSED_0160_PORT6f = 3360, + UNUSED_0160_PORT7f, + UNUSED_0164_PORT4f, + UNUSED_0164_PORT5f, + UNUSED_0164_PORT6f, + UNUSED_0164_PORT7f, + UNUSED_0168_PORT4f, + UNUSED_0168_PORT5f, + UNUSED_0168_PORT6f, + UNUSED_0168_PORT7f, + UNUSED_016C_PORT4f = 3370, + UNUSED_016C_PORT5f, + UNUSED_016C_PORT6f, + UNUSED_016C_PORT7f, + UNUSED_0170_PORT4f, + UNUSED_0170_PORT5f, + UNUSED_0170_PORT6f, + UNUSED_0170_PORT7f, + UNUSED_0174_PORT4f, + UNUSED_0174_PORT5f, + UNUSED_0174_PORT6f = 3380, + UNUSED_0174_PORT7f, + UNUSED_0178_PORT4f, + UNUSED_0178_PORT5f, + UNUSED_0178_PORT6f, + UNUSED_0178_PORT7f, + UNUSED_017C_PORT4f, + UNUSED_017C_PORT5f, + UNUSED_017C_PORT6f, + UNUSED_017C_PORT7f, + UNUSED_0184_PORT4f = 3390, + UNUSED_0184_PORT5f, + UNUSED_0184_PORT6f, + UNUSED_0184_PORT7f, + UNUSED_0188_PORT4f, + UNUSED_0188_PORT5f, + UNUSED_0188_PORT6f, + UNUSED_0188_PORT7f, + UNUSED_018C_PORT4f, + UNUSED_018C_PORT5f, + UNUSED_018C_PORT6f = 3400, + UNUSED_018C_PORT7f, + UNUSED_0190_PORT4f, + UNUSED_0190_PORT5f, + UNUSED_0190_PORT6f, + UNUSED_0190_PORT7f, + UNUSED_0194_PORT4f, + UNUSED_0194_PORT5f, + UNUSED_0194_PORT6f, + UNUSED_0194_PORT7f, + UNUSED_0198_PORT4f = 3410, + UNUSED_0198_PORT5f, + UNUSED_0198_PORT6f, + UNUSED_0198_PORT7f, + UNUSED_019C_PORT4f, + UNUSED_019C_PORT5f, + UNUSED_019C_PORT6f, + UNUSED_019C_PORT7f, + UNUSED_01A0_PORT4f, + UNUSED_01A0_PORT5f, + UNUSED_01A0_PORT6f = 3420, + UNUSED_01A0_PORT7f, + UNUSED_01A4_PORT4f, + UNUSED_01A4_PORT5f, + UNUSED_01A4_PORT6f, + UNUSED_01A4_PORT7f, + UNUSED_01A8_PORT4f, + UNUSED_01A8_PORT5f, + UNUSED_01A8_PORT6f, + UNUSED_01A8_PORT7f, + UNUSED_01AC_PORT4f = 3430, + UNUSED_01AC_PORT5f, + UNUSED_01AC_PORT6f, + UNUSED_01AC_PORT7f, + UNUSED_01B0_PORT4f, + UNUSED_01B0_PORT5f, + UNUSED_01B0_PORT6f, + UNUSED_01B0_PORT7f, + UNUSED_01B4_PORT4f, + UNUSED_01B4_PORT5f, + UNUSED_01B4_PORT6f = 3440, + UNUSED_01B4_PORT7f, + UNUSED_01B8_PORT4f, + UNUSED_01B8_PORT5f, + UNUSED_01B8_PORT6f, + UNUSED_01B8_PORT7f, + UNUSED_01BC_PORT4f, + UNUSED_01BC_PORT5f, + UNUSED_01BC_PORT6f, + UNUSED_01BC_PORT7f, + UPPERf = 3450, + VALf, + VALIDf, + VALUEf, + VAL_Hf, + VAL_Lf, + VIAROM_WRITE_ENf, + VIDf, + VID0_TYPEf, + VID4095_TYPEf, + VLAN_LEAKY_00f = 3460, + VLAN_LEAKY_01f, + VLAN_LEAKY_02f, + VLAN_LEAKY_03f, + VLAN_LEAKY_04f, + VLAN_LEAKY_08f, + VLAN_LEAKY_0Df, + VLAN_LEAKY_0Ef, + VLAN_LEAKY_10f, + VLAN_LEAKY_11f, + VLAN_LEAKY_12f = 3470, + VLAN_LEAKY_13f, + VLAN_LEAKY_18f, + VLAN_LEAKY_1Af, + VLAN_LEAKY_20f, + VLAN_LEAKY_21f, + VLAN_LEAKY_22f, + VLAN_LEAKY_CDPf, + VLAN_LEAKY_CSSTPf, + VLAN_LEAKY_LLDPf, + VOLT_CMP_ENf = 3480, + VOLT_PROB_MAXf, + VOLT_PROB_MINf, + VOLT_PROB_PAD_OUT_ENf, + VOLT_PROB_RECORDf, + VOLT_PROB_SELf, + VOLT_THRf, + VS_TPIDf, + WAIT_FOR_RX_IDLEf, + WAIT_FOR_TX_IDLEf, + WAIT_RX_INACTIVE_GEf = 3490, + WAIT_RX_INACTIVE_GELITEf, + WAIT_RX_INACTIVE_TIMER_GEf, + WAIT_RX_INACTIVE_TIMER_GELITEf, + WEIGHTf, + WEIGHT_SELf, + WOLf, + WOL_ENf, + WOL_MAC_0_31f, + WOL_MAC_32_47f, + WOL_PMSKf = 3500, + WRAP_MIB_RSTf, + WRAP_PHY_DBGf, + WRITE_DATAf, + XG2XG_OVRUN_Xf, + XG2XG_OVRUN_Yf, + XG2XG_UDRUN_Xf, + XG2XG_UDRUN_Yf, + XGLBK_FIFO_DBG_ENf, + XGLBK_FIFO_DBG_SELf, + XMASCANf = 3510, + REGFIELD_LIST_END = 3511 +} rtk_regField_list_t; + +typedef struct rtk_regField_s +{ + rtk_regField_list_t name; /* field name */ + unsigned short lsp; /* LSP of the field */ + unsigned short len; /* field length */ +} rtk_regField_t; + +typedef struct rtk_reg_s +{ + unsigned int offset; /* offset address */ + unsigned int field_num; /* total field numbers */ + unsigned int array_offset:16; /* array offset */ + unsigned int larray:16; /* array start index */ + unsigned int harray:16; /* array end index */ + unsigned int lport:16; /* port start index */ + unsigned int hport:16; /* port end index */ + rtk_regField_t *fields; /* register fields */ +} rtk_reg_t; + +extern rtk_reg_t rtl8373_reg_list[]; + +#define RTL8373_REGSIZE_MAX1 (96) +#define RTL8373_REGSIZE_MAX2 (64) +#define RTL8373_REGSIZE_MAX3 (32) +#define RTL8373_REGSIZE_MAX4 (16) +#define RTL8373_REGSIZE_MAX5 (12) +#define RTL8373_REGSIZE_BYTELEN (RTL8373_REGSIZE_MAX1 / 8) +#define RTL8373_REGSIZE_WORDLEN (RTL8373_REGSIZE_MAX1 / 32) + +#endif /* __RTL8373_REG_STRUCT_H__ */ + diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/rtl8373_smi.c b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/rtl8373_smi.c new file mode 100755 index 00000000..aeb36239 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/rtl8373_smi.c @@ -0,0 +1,502 @@ +/* +* Copyright c Realtek Semiconductor Corporation, 2006 +* All rights reserved. +* +* Program : Control smi connected RTL8366 +* Abstract : +* Author : Yu-Mei Pan (ympan@realtek.com.cn) +* $Id: smi.c,v 1.2 2008-04-10 03:04:19 shiehyy Exp $ +*/ +#include +#include +#include "rtk_error.h" + +#if defined(MDC_MDIO_OPERATION) +/*******************************************************************************/ +/* MDC/MDIO porting */ +/*******************************************************************************/ +/* define the PHY ID currently used */ +#define MDC_MDIO_PHY_ID 29 /* PHY ID 0 or 29 */ + +extern int ipq_mdio_read(int mii_id, int regnum, unsigned short *data); +extern int ipq_mdio_write(int mii_id, int regnum, unsigned short value); + +static inline unsigned int rtk_mdio_write(int mii_id, int regnum, unsigned int value) +{ + return ipq_mdio_write(mii_id, regnum, (unsigned short)value); +} + +static inline int rtk_mdio_read(int mii_id, int regnum, unsigned int *data) +{ + unsigned short temp_data = 0; + + ipq_mdio_read(mii_id, regnum, &temp_data); + + if (data != NULL) + *data = temp_data; + + return temp_data; +} + +static inline int rtk_mdio_read_h(int mii_id, int regnum, rtk_uint16 *data) +{ + unsigned short temp_data = 0; + + ipq_mdio_read(mii_id, regnum, &temp_data); + + if (data != NULL) + *data = temp_data; + + return temp_data; +} + + +/* MDC/MDIO, redefine/implement the following Macro */ +#define MDC_MDIO_WRITE(preamableLength, phyID, regID, data) rtk_mdio_write(phyID, regID, data) +#define MDC_MDIO_READ(preamableLength, phyID, regID, pData) rtk_mdio_read(phyID, regID, pData) +#define MDC_MDIO_READ_H(preamableLength, phyID, regID, pData) rtk_mdio_read_h(phyID, regID, pData) + +#elif defined(SPI_OPERATION) +/*******************************************************************************/ +/* SPI porting */ +/*******************************************************************************/ +/* SPI, redefine/implement the following Macro */ +#define SPI_WRITE(data, length) +#define SPI_READ(pData, length) + + + + + +#else +/*******************************************************************************/ +/* I2C porting */ +/*******************************************************************************/ +/* Define the GPIO ID for SCK & SDA */ +rtk_uint32 smi_SCK = 1; /* GPIO used for SMI Clock Generation */ +rtk_uint32 smi_SDA = 2; /* GPIO used for SMI Data signal */ + +/* I2C, redefine/implement the following Macro */ +#define GPIO_DIRECTION_SET(gpioID, direction) +#define GPIO_DATA_SET(gpioID, data) +#define GPIO_DATA_GET(gpioID, pData) + + + + + +#endif + +static void rtlglue_drvMutexLock(void) +{ + /* It is empty currently. Implement this function if Lock/Unlock function is needed */ + return; +} + +static void rtlglue_drvMutexUnlock(void) +{ + /* It is empty currently. Implement this function if Lock/Unlock function is needed */ + return; +} + + + +#if defined(MDC_MDIO_OPERATION) || defined(SPI_OPERATION) + /* No local function in MDC/MDIO & SPI mode */ +#else +static void _smi_start(void) +{ + + /* change GPIO pin to Output only */ + GPIO_DIRECTION_SET(smi_SCK, GPIO_DIR_OUT); + GPIO_DIRECTION_SET(smi_SDA, GPIO_DIR_OUT); + + /* Initial state: SCK: 0, SDA: 1 */ + GPIO_DATA_SET(smi_SCK, 0); + GPIO_DATA_SET(smi_SDA, 1); + CLK_DURATION(DELAY); + + /* CLK 1: 0 -> 1, 1 -> 0 */ + GPIO_DATA_SET(smi_SCK, 1); + CLK_DURATION(DELAY); + GPIO_DATA_SET(smi_SCK, 0); + CLK_DURATION(DELAY); + + /* CLK 2: */ + GPIO_DATA_SET(smi_SCK, 1); + CLK_DURATION(DELAY); + GPIO_DATA_SET(smi_SDA, 0); + CLK_DURATION(DELAY); + GPIO_DATA_SET(smi_SCK, 0); + CLK_DURATION(DELAY); + GPIO_DATA_SET(smi_SDA, 1); + +} + + + +static void _smi_writeBit(rtk_uint16 signal, rtk_uint32 bitLen) +{ + for( ; bitLen > 0; bitLen--) + { + CLK_DURATION(DELAY); + + /* prepare data */ + if ( signal & (1<<(bitLen-1)) ) + { + GPIO_DATA_SET(smi_SDA, 1); + } + else + { + GPIO_DATA_SET(smi_SDA, 0); + } + CLK_DURATION(DELAY); + + /* clocking */ + GPIO_DATA_SET(smi_SCK, 1); + CLK_DURATION(DELAY); + GPIO_DATA_SET(smi_SCK, 0); + } +} + + + +static void _smi_readBit(rtk_uint32 bitLen, rtk_uint32 *rData) +{ + rtk_uint32 u = 0; + + /* change GPIO pin to Input only */ + GPIO_DIRECTION_SET(smi_SDA, GPIO_DIR_IN); + + for (*rData = 0; bitLen > 0; bitLen--) + { + CLK_DURATION(DELAY); + + /* clocking */ + GPIO_DATA_SET(smi_SCK, 1); + CLK_DURATION(DELAY); + GPIO_DATA_GET(smi_SDA, &u); + GPIO_DATA_SET(smi_SCK, 0); + + *rData |= (u << (bitLen - 1)); + } + + /* change GPIO pin to Output only */ + GPIO_DIRECTION_SET(smi_SDA, GPIO_DIR_OUT); +} + + + +static void _smi_stop(void) +{ + + CLK_DURATION(DELAY); + GPIO_DATA_SET(smi_SDA, 0); + GPIO_DATA_SET(smi_SCK, 1); + CLK_DURATION(DELAY); + GPIO_DATA_SET(smi_SDA, 1); + CLK_DURATION(DELAY); + GPIO_DATA_SET(smi_SCK, 1); + CLK_DURATION(DELAY); + GPIO_DATA_SET(smi_SCK, 0); + CLK_DURATION(DELAY); + GPIO_DATA_SET(smi_SCK, 1); + + /* add a click */ + CLK_DURATION(DELAY); + GPIO_DATA_SET(smi_SCK, 0); + CLK_DURATION(DELAY); + GPIO_DATA_SET(smi_SCK, 1); + + + /* change GPIO pin to Input only */ + GPIO_DIRECTION_SET(smi_SDA, GPIO_DIR_IN); + GPIO_DIRECTION_SET(smi_SCK, GPIO_DIR_IN); +} + +#endif /* End of #if defined(MDC_MDIO_OPERATION) || defined(SPI_OPERATION) */ + +rtk_int32 rtl8373_smi_read(rtk_uint32 mAddrs, rtk_uint32 *rData) +{ +#if (!defined(MDC_MDIO_OPERATION) && !defined(SPI_OPERATION)) + rtk_uint32 rawData=0, ACK; + rtk_uint8 con; + rtk_uint32 ret = RT_ERR_OK; + +#endif +#if defined(MDC_MDIO_OPERATION) + rtk_uint32 regData=0; + rtk_uint16 datah=0; + rtk_uint16 datal=0; +#endif + + + if(mAddrs > 0xFFFF) + return RT_ERR_INPUT; + + if(rData == NULL) + return RT_ERR_NULL_POINTER; + +#if defined(MDC_MDIO_OPERATION) + + /* Lock */ + rtlglue_drvMutexLock(); + + /*Ckeck busy bit, register21, bit2*/ + MDC_MDIO_READ(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_PHY_ID,MDC_MDIO_CTRL_REG, ®Data); + + if(regData & 0x4) + { + return RT_ERR_BUSYWAIT_TIMEOUT; + } + + /*write reg address, register22*/ + MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_PHY_ID, MDC_MDIO_ADDR_REG, mAddrs); + + /* Write read command register21 */ + MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_PHY_ID, MDC_MDIO_CTRL_REG, MDC_MDIO_READ_CMD); + + + /*Ckeck busy bit, register21, bit2*/ + MDC_MDIO_READ(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_PHY_ID,MDC_MDIO_CTRL_REG, ®Data); + + if(regData & 0x4) + { + return RT_ERR_BUSYWAIT_TIMEOUT; + } + + /* Write read control code to register 23 */ + MDC_MDIO_READ_H(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_PHY_ID, MDC_MDIO_DATA_LOW, &datal); + + /* Read data from register 24 */ + MDC_MDIO_READ_H(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_PHY_ID, MDC_MDIO_DATA_HIGH, &datah); + + *rData = datal & 0xffff; + *rData |= (datah & 0xffff) << 16; + + /* Unlock */ + rtlglue_drvMutexUnlock(); + + return RT_ERR_OK; + +#elif defined(SPI_OPERATION) + + /* Lock */ + rtlglue_drvMutexLock(); + + /* Write 8 bits READ OP_CODE */ + SPI_WRITE(SPI_READ_OP, SPI_READ_OP_LEN); + + /* Write 16 bits register address */ + SPI_WRITE(mAddrs, SPI_REG_LEN); + + /* Read 16 bits data */ + SPI_READ(rData, SPI_DATA_LEN); + + /* Unlock */ + rtlglue_drvMutexUnlock(); + + return RT_ERR_OK; + +#else + + /*Disable CPU interrupt to ensure that the SMI operation is atomic. + The API is based on RTL865X, rewrite the API if porting to other platform.*/ + rtlglue_drvMutexLock(); + + _smi_start(); /* Start SMI */ + + _smi_writeBit(0x0b, 4); /* CTRL code: 4'b1011 for RTL8370 */ + + _smi_writeBit(0x4, 3); /* CTRL code: 3'b100 */ + + _smi_writeBit(0x1, 1); /* 1: issue READ command */ + + con = 0; + do { + con++; + _smi_readBit(1, &ACK); /* ACK for issuing READ command*/ + } while ((ACK != 0) && (con < ack_timer)); + + if (ACK != 0) ret = RT_ERR_FAILED; + + _smi_writeBit((mAddrs&0xff), 8); /* Set reg_addr[7:0] */ + + con = 0; + do { + con++; + _smi_readBit(1, &ACK); /* ACK for setting reg_addr[7:0] */ + } while ((ACK != 0) && (con < ack_timer)); + + if (ACK != 0) ret = RT_ERR_FAILED; + + _smi_writeBit((mAddrs>>8), 8); /* Set reg_addr[15:8] */ + + con = 0; + do { + con++; + _smi_readBit(1, &ACK); /* ACK by RTL8369 */ + } while ((ACK != 0) && (con < ack_timer)); + if (ACK != 0) ret = RT_ERR_FAILED; + + _smi_readBit(8, &rawData); /* Read DATA [7:0] */ + *rData = rawData&0xff; + + _smi_writeBit(0x00, 1); /* ACK by CPU */ + + _smi_readBit(8, &rawData); /* Read DATA [15: 8] */ + + _smi_writeBit(0x01, 1); /* ACK by CPU */ + *rData |= (rawData<<8); + + _smi_stop(); + + rtlglue_drvMutexUnlock();/*enable CPU interrupt*/ + + return ret; +#endif /* end of #if defined(MDC_MDIO_OPERATION) */ +} + + + +rtk_int32 rtl8373_smi_write(rtk_uint32 mAddrs, rtk_uint32 rData) +{ +#if (!defined(MDC_MDIO_OPERATION) && !defined(SPI_OPERATION)) + rtk_int8 con; + rtk_uint32 ACK; + rtk_uint32 ret = RT_ERR_OK; +#endif + +#if defined(MDC_MDIO_OPERATION) + rtk_uint32 regData=0; + rtk_uint16 datal; + rtk_uint16 datah; +#endif + + + if(mAddrs > 0xFFFF) + return RT_ERR_INPUT; + +#if defined(MDC_MDIO_OPERATION) + + /* Lock */ + rtlglue_drvMutexLock(); + + /*Ckeck busy bit, register21, bit2*/ + MDC_MDIO_READ(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_PHY_ID,MDC_MDIO_CTRL_REG, ®Data); + + if(regData & 0x4) + { + return RT_ERR_BUSYWAIT_TIMEOUT; + } + + /*write reg address, register22*/ + MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_PHY_ID, MDC_MDIO_ADDR_REG, mAddrs); + + /*write low 16bits data, register23*/ + datal = rData & 0xffff; + MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_PHY_ID, MDC_MDIO_DATA_LOW, datal); + + /*write high 16bits data, register24*/ + datah = (rData >> 16) & 0xffff; + MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_PHY_ID, MDC_MDIO_DATA_HIGH, datah); + + /*write write cmd, register 21*/ + MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_PHY_ID, MDC_MDIO_CTRL_REG, MDC_MDIO_WRITE_CMD); + + + /*Ckeck busy bit, register21, bit2*/ + MDC_MDIO_READ(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_PHY_ID,MDC_MDIO_CTRL_REG, ®Data); + + if(regData & 0x4) + { + return RT_ERR_BUSYWAIT_TIMEOUT; + } + /* Unlock */ + rtlglue_drvMutexUnlock(); + + return RT_ERR_OK; + +#elif defined(SPI_OPERATION) + + /* Lock */ + rtlglue_drvMutexLock(); + + /* Write 8 bits WRITE OP_CODE */ + SPI_WRITE(SPI_WRITE_OP, SPI_WRITE_OP_LEN); + + /* Write 16 bits register address */ + SPI_WRITE(mAddrs, SPI_REG_LEN); + + /* Write 16 bits data */ + SPI_WRITE(rData, SPI_DATA_LEN); + + /* Unlock */ + rtlglue_drvMutexUnlock(); + + return RT_ERR_OK; +#else + + /*Disable CPU interrupt to ensure that the SMI operation is atomic. + The API is based on RTL865X, rewrite the API if porting to other platform.*/ + rtlglue_drvMutexLock(); + + _smi_start(); /* Start SMI */ + + _smi_writeBit(0x0b, 4); /* CTRL code: 4'b1011 for RTL8370*/ + + _smi_writeBit(0x4, 3); /* CTRL code: 3'b100 */ + + _smi_writeBit(0x0, 1); /* 0: issue WRITE command */ + + con = 0; + do { + con++; + _smi_readBit(1, &ACK); /* ACK for issuing WRITE command*/ + } while ((ACK != 0) && (con < ack_timer)); + if (ACK != 0) ret = RT_ERR_FAILED; + + _smi_writeBit((mAddrs&0xff), 8); /* Set reg_addr[7:0] */ + + con = 0; + do { + con++; + _smi_readBit(1, &ACK); /* ACK for setting reg_addr[7:0] */ + } while ((ACK != 0) && (con < ack_timer)); + if (ACK != 0) ret = RT_ERR_FAILED; + + _smi_writeBit((mAddrs>>8), 8); /* Set reg_addr[15:8] */ + + con = 0; + do { + con++; + _smi_readBit(1, &ACK); /* ACK for setting reg_addr[15:8] */ + } while ((ACK != 0) && (con < ack_timer)); + if (ACK != 0) ret = RT_ERR_FAILED; + + _smi_writeBit(rData&0xff, 8); /* Write Data [7:0] out */ + + con = 0; + do { + con++; + _smi_readBit(1, &ACK); /* ACK for writting data [7:0] */ + } while ((ACK != 0) && (con < ack_timer)); + if (ACK != 0) ret = RT_ERR_FAILED; + + _smi_writeBit(rData>>8, 8); /* Write Data [15:8] out */ + + con = 0; + do { + con++; + _smi_readBit(1, &ACK); /* ACK for writting data [15:8] */ + } while ((ACK != 0) && (con < ack_timer)); + if (ACK != 0) ret = RT_ERR_FAILED; + + _smi_stop(); + + rtlglue_drvMutexUnlock();/*enable CPU interrupt*/ + + return ret; +#endif /* end of #if defined(MDC_MDIO_OPERATION) */ +} + diff --git a/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/rtl8373_smi.h b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/rtl8373_smi.h new file mode 100755 index 00000000..211177ba --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dal/rtl8373/rtl8373_smi.h @@ -0,0 +1,36 @@ +#ifndef __SMI_H__ +#define __SMI_H__ + +#include +#include "rtk_error.h" + +#define MDC_MDIO_PREAMBLE_LEN 32 + +#define MDC_MDIO_CTRL_REG 21 +#define MDC_MDIO_ADDR_REG 22 +#define MDC_MDIO_DATA_LOW 23 +#define MDC_MDIO_DATA_HIGH 24 +#define MDC_MDIO_READ_CMD 0x1B +#define MDC_MDIO_WRITE_CMD 0x19 + + +#define SPI_READ_OP 0x3 +#define SPI_WRITE_OP 0x2 +#define SPI_READ_OP_LEN 0x8 +#define SPI_WRITE_OP_LEN 0x8 +#define SPI_REG_LEN 16 +#define SPI_DATA_LEN 16 + +#define GPIO_DIR_IN 1 +#define GPIO_DIR_OUT 0 + +#define ack_timer 5 + +#define DELAY 10000 +#define CLK_DURATION(clk) { int i; for(i=0; i +#include +#include +#include + +#include + +#if 1 +/* Function Name: + * rtk_port_autoDos_set + * Description: + * Set Auto Dos state + * Input: + * type - Auto DoS type + * state - 1: Eanble(Drop), 0: Disable(Forward) + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set Auto Dos state + */ +rtk_api_ret_t rtk_port_autoDos_set(rtk_port_autoDosType_t type, rtk_enable_t state) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->port_autoDos_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->port_autoDos_set(type, state); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_port_autoDos_get + * Description: + * Get Auto Dos state + * Input: + * type - Auto DoS type + * Output: + * pState - 1: Eanble(Drop), 0: Disable(Forward) + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Null Pointer + * Note: + * The API can get Auto Dos state + */ +rtk_api_ret_t rtk_port_autoDos_get(rtk_port_autoDosType_t type, rtk_enable_t *pState) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->port_autoDos_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->port_autoDos_get(type, pState); + RTK_API_UNLOCK(); + + return retVal; +} + +#endif + diff --git a/sources/uboot-be550/drivers/net/rtl8372/dos.h b/sources/uboot-be550/drivers/net/rtl8372/dos.h new file mode 100755 index 00000000..a720f6bf --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dos.h @@ -0,0 +1,76 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8373 switch high-level API + * + * Feature : The file includes Trunk module high-layer TRUNK defination + * + */ + +#ifndef __RTK_API_DOS_H__ +#define __RTK_API_DOS_H__ + + +typedef enum rtk_port_autoDosType_e +{ + AUTODOS_DAEQSA = 0, + AUTODOS_LANDATTACKS_V4, + AUTODOS_LANDATTACKS_V6, + AUTODOS_BLATATTACKS, + AUTODOS_SYNFINSCAN, + AUTODOS_XMASCAN, + AUTODOS_NULLSCAN, + AUTODOS_SYN1024, + AUTODOS_TCPSHORTHDR, + AUTODOS_TCPFRAGERROR, + AUTODOS_ICMPFRAGMENT, + AUTODOS_END, + +} rtk_port_autoDosType_t; + +/* Function Name: + * rtk_port_autoDos_set + * Description: + * Set Auto Dos state + * Input: + * type - Auto DoS type + * state - 1: Eanble(Drop), 0: Disable(Forward) + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set Auto Dos state + */ +extern rtk_api_ret_t rtk_port_autoDos_set(rtk_port_autoDosType_t type, rtk_enable_t state); + +/* Function Name: + * rtk_port_autoDos_get + * Description: + * Get Auto Dos state + * Input: + * type - Auto DoS type + * Output: + * pState - 1: Eanble(Drop), 0: Disable(Forward) + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Null Pointer + * Note: + * The API can get Auto Dos state + */ +extern rtk_api_ret_t rtk_port_autoDos_get(rtk_port_autoDosType_t type, rtk_enable_t *pState); + + +#endif /* __RTK_API_TRUNK_H__ */ diff --git a/sources/uboot-be550/drivers/net/rtl8372/dot1x.c b/sources/uboot-be550/drivers/net/rtl8372/dot1x.c new file mode 100755 index 00000000..d787af14 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dot1x.c @@ -0,0 +1,816 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8367C + * Feature : Here is a list of all functions and variables in 1X module. + * + */ + +#include +#include +#include +#include + +#include + +/* Function Name: + * rtk_dot1x_unauthPacketOper_set + * Description: + * Set 802.1x unauth action configuration. + * Input: + * port - Port id. + * unauth_action - 802.1X unauth action. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameter. + * Note: + * This API can set 802.1x unauth action configuration. + * The unauth action is as following: + * - DOT1X_ACTION_DROP + * - DOT1X_ACTION_TRAP2CPU + * - DOT1X_ACTION_GUESTVLAN + */ +rtk_api_ret_t rtk_dot1x_unauthPacketOper_set(rtk_port_t port, rtk_dot1x_unauth_action_t unauth_action) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->dot1x_unauthPacketOper_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->dot1x_unauthPacketOper_set(port, unauth_action); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_dot1x_unauthPacketOper_get + * Description: + * Get 802.1x unauth action configuration. + * Input: + * port - Port id. + * Output: + * pUnauth_action - 802.1X unauth action. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can get 802.1x unauth action configuration. + * The unauth action is as following: + * - DOT1X_ACTION_DROP + * - DOT1X_ACTION_TRAP2CPU + * - DOT1X_ACTION_GUESTVLAN + */ +rtk_api_ret_t rtk_dot1x_unauthPacketOper_get(rtk_port_t port, rtk_dot1x_unauth_action_t *pUnauth_action) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->dot1x_unauthPacketOper_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->dot1x_unauthPacketOper_get(port, pUnauth_action); + RTK_API_UNLOCK(); + + return retVal; +} +#if 0 +/* Function Name: + * rtk_dot1x_eapolFrame2CpuEnable_set + * Description: + * Set 802.1x EAPOL packet trap to CPU configuration + * Input: + * enable - The status of 802.1x EAPOL packet. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * To support 802.1x authentication functionality, EAPOL frame (ether type = 0x888E) has to + * be trapped to CPU. + * The status of EAPOL frame trap to CPU is as following: + * - DISABLED + * - ENABLED + */ +rtk_api_ret_t rtk_dot1x_eapolFrame2CpuEnable_set(rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->dot1x_eapolFrame2CpuEnable_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->dot1x_eapolFrame2CpuEnable_set(enable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_dot1x_eapolFrame2CpuEnable_get + * Description: + * Get 802.1x EAPOL packet trap to CPU configuration + * Input: + * None + * Output: + * pEnable - The status of 802.1x EAPOL packet. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * To support 802.1x authentication functionality, EAPOL frame (ether type = 0x888E) has to + * be trapped to CPU. + * The status of EAPOL frame trap to CPU is as following: + * - DISABLED + * - ENABLED + */ +rtk_api_ret_t rtk_dot1x_eapolFrame2CpuEnable_get(rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->dot1x_eapolFrame2CpuEnable_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->dot1x_eapolFrame2CpuEnable_get(pEnable); + RTK_API_UNLOCK(); + + return retVal; +} +#endif +/* Function Name: + * rtk_dot1x_trap2CPU_Sel_set + * Description: + * Select cpu config which unauth packet trap. + * Input: + * cpu_sel - select cpu value. + * Output: + * NULL + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can set cpu config which unauth packet trap. + */ +rtk_api_ret_t rtk_dot1x_trap2CPU_Sel_set(rtk_dot1x_cpu_select_t cpu_sel) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->dot1x_trap2CPU_Sel_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->dot1x_trap2CPU_Sel_set(cpu_sel); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_dot1x_trap2CPU_Sel_get + * Description: + * Select cpu config which unauth packet trap. + * Input: + * NULL + * Output: + * pCpu_sel - 802.1X trap cpu select value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can set cpu config which unauth packet trap. + */ +rtk_api_ret_t rtk_dot1x_trap2CPU_Sel_get(rtk_dot1x_cpu_select_t *pCpu_sel) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->dot1x_trap2CPU_Sel_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->dot1x_trap2CPU_Sel_get(pCpu_sel); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_dot1x_trap_priority_set + * Description: + * Set trap priority for unauth packet. + * Input: + * pri_value - priority value. + * Output: + * NULL + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can set trap priority for unauth packet. + */ +rtk_api_ret_t rtk_dot1x_trap_priority_set(rtk_pri_t pri_value) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->dot1x_trap_priority_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->dot1x_trap_priority_set(pri_value); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_dot1x_trap_priority_get + * Description: + * Get trap priority for unauth packet. + * Input: + * pri_value - priority value. + * Output: + * NULL + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can get trap priority for unauth packet. + */ +rtk_api_ret_t rtk_dot1x_trap_priority_get(rtk_pri_t *pri_value) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->dot1x_trap_priority_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->dot1x_trap_priority_get(pri_value); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_dot1x_portBasedEnable_set + * Description: + * Set 802.1x port-based enable configuration + * Input: + * port - Port id. + * enable - The status of 802.1x port. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * RT_ERR_DOT1X_PORTBASEDPNEN - 802.1X port-based enable error + * Note: + * The API can update the port-based port enable register content. If a port is 802.1x + * port based network access control "enabled", it should be authenticated so packets + * from that port won't be dropped or trapped to CPU. + * The status of 802.1x port-based network access control is as following: + * - DISABLED + * - ENABLED + */ +rtk_api_ret_t rtk_dot1x_portBasedEnable_set(rtk_port_t port, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->dot1x_portBasedEnable_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->dot1x_portBasedEnable_set(port, enable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_dot1x_portBasedEnable_get + * Description: + * Get 802.1x port-based enable configuration + * Input: + * port - Port id. + * Output: + * pEnable - The status of 802.1x port. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get the 802.1x port-based port status. + */ +rtk_api_ret_t rtk_dot1x_portBasedEnable_get(rtk_port_t port, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->dot1x_portBasedEnable_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->dot1x_portBasedEnable_get(port, pEnable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_dot1x_portBasedAuthStatus_set + * Description: + * Set 802.1x port-based auth. port configuration + * Input: + * port - Port id. + * port_auth - The status of 802.1x port. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_DOT1X_PORTBASEDAUTH - 802.1X port-based auth error + * Note: + * The authenticated status of 802.1x port-based network access control is as following: + * - UNAUTH + * - AUTH + */ +rtk_api_ret_t rtk_dot1x_portBasedAuthStatus_set(rtk_port_t port, rtk_dot1x_auth_status_t port_auth) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->dot1x_portBasedAuthStatus_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->dot1x_portBasedAuthStatus_set(port, port_auth); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_dot1x_portBasedAuthStatus_get + * Description: + * Get 802.1x port-based auth. port configuration + * Input: + * port - Port id. + * Output: + * pPort_auth - The status of 802.1x port. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get 802.1x port-based port auth.information. + */ +rtk_api_ret_t rtk_dot1x_portBasedAuthStatus_get(rtk_port_t port, rtk_dot1x_auth_status_t *pPort_auth) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->dot1x_portBasedAuthStatus_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->dot1x_portBasedAuthStatus_get(port, pPort_auth); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_dot1x_portBasedDirection_set + * Description: + * Set 802.1x port-based operational direction configuration + * Input: + * port - Port id. + * port_direction - Operation direction + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_DOT1X_PORTBASEDOPDIR - 802.1X port-based operation direction error + * Note: + * The operate controlled direction of 802.1x port-based network access control is as following: + * - BOTH + * - IN + */ +rtk_api_ret_t rtk_dot1x_portBasedDirection_set(rtk_port_t port, rtk_dot1x_direction_t port_direction) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->dot1x_portBasedDirection_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->dot1x_portBasedDirection_set(port, port_direction); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_dot1x_portBasedDirection_get + * Description: + * Get 802.1X port-based operational direction configuration + * Input: + * port - Port id. + * Output: + * pPort_direction - Operation direction + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get 802.1x port-based operational direction information. + */ +rtk_api_ret_t rtk_dot1x_portBasedDirection_get(rtk_port_t port, rtk_dot1x_direction_t *pPort_direction) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->dot1x_portBasedDirection_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->dot1x_portBasedDirection_get(port, pPort_direction); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_dot1x_macBasedEnable_set + * Description: + * Set 802.1x mac-based port enable configuration + * Input: + * port - Port id. + * enable - The status of 802.1x port. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * RT_ERR_DOT1X_MACBASEDPNEN - 802.1X mac-based enable error + * Note: + * If a port is 802.1x MAC based network access control "enabled", the incoming packets should + * be authenticated so packets from that port won't be dropped or trapped to CPU. + * The status of 802.1x MAC-based network access control is as following: + * - DISABLED + * - ENABLED + */ +rtk_api_ret_t rtk_dot1x_macBasedEnable_set(rtk_port_t port, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->dot1x_macBasedEnable_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->dot1x_macBasedEnable_set(port, enable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_dot1x_macBasedEnable_get + * Description: + * Get 802.1x mac-based port enable configuration + * Input: + * port - Port id. + * Output: + * pEnable - The status of 802.1x port. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * If a port is 802.1x MAC based network access control "enabled", the incoming packets should + * be authenticated so packets from that port wont be dropped or trapped to CPU. + * The status of 802.1x MAC-based network access control is as following: + * - DISABLED + * - ENABLED + */ +rtk_api_ret_t rtk_dot1x_macBasedEnable_get(rtk_port_t port, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->dot1x_macBasedEnable_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->dot1x_macBasedEnable_get(port, pEnable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_dot1x_macBasedAuthMac_add + * Description: + * Add an authenticated MAC to ASIC + * Input: + * port - Port id. + * pAuth_mac - The authenticated MAC. + * fid - filtering database. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * RT_ERR_DOT1X_MACBASEDPNEN - 802.1X mac-based enable error + * Note: + * The API can add a 802.1x authenticated MAC address to port. If the MAC does not exist in LUT, + * user can't add this MAC to auth status. + */ +rtk_api_ret_t rtk_dot1x_macBasedAuthMac_add(rtk_port_t port, rtk_mac_t *pAuth_mac, rtk_fid_t fid) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->dot1x_macBasedAuthMac_add) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->dot1x_macBasedAuthMac_add(port, pAuth_mac, fid); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_dot1x_macBasedAuthMac_del + * Description: + * Delete an authenticated MAC to ASIC + * Input: + * port - Port id. + * pAuth_mac - The authenticated MAC. + * fid - filtering database. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can delete a 802.1x authenticated MAC address to port. It only change the auth status of + * the MAC and won't delete it from LUT. + */ +rtk_api_ret_t rtk_dot1x_macBasedAuthMac_del(rtk_port_t port, rtk_mac_t *pAuth_mac, rtk_fid_t fid) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->dot1x_macBasedAuthMac_del) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->dot1x_macBasedAuthMac_del(port, pAuth_mac, fid); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_dot1x_macBasedDirection_set + * Description: + * Set 802.1x mac-based operational direction configuration + * Input: + * mac_direction - Operation direction + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_DOT1X_MACBASEDOPDIR - 802.1X mac-based operation direction error + * Note: + * The operate controlled direction of 802.1x mac-based network access control is as following: + * - BOTH + * - IN + */ +rtk_api_ret_t rtk_dot1x_macBasedDirection_set(rtk_dot1x_direction_t mac_direction) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->dot1x_macBasedDirection_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->dot1x_macBasedDirection_set(mac_direction); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_dot1x_macBasedDirection_get + * Description: + * Get 802.1x mac-based operational direction configuration + * Input: + * port - Port id. + * Output: + * pMac_direction - Operation direction + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get 802.1x mac-based operational direction information. + */ +rtk_api_ret_t rtk_dot1x_macBasedDirection_get(rtk_dot1x_direction_t *pMac_direction) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->dot1x_macBasedDirection_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->dot1x_macBasedDirection_get(pMac_direction); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * Set 802.1x guest VLAN configuration + * Description: + * Set 802.1x mac-based operational direction configuration + * Input: + * vid - 802.1x guest VLAN ID + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * Note: + * The operate controlled 802.1x guest VLAN + */ +rtk_api_ret_t rtk_dot1x_guestVlan_set(rtk_vlan_t vid) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->dot1x_guestVlan_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->dot1x_guestVlan_set(vid); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_dot1x_guestVlan_get + * Description: + * Get 802.1x guest VLAN configuration + * Input: + * None + * Output: + * pVid - 802.1x guest VLAN ID + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get 802.1x guest VLAN information. + */ +rtk_api_ret_t rtk_dot1x_guestVlan_get(rtk_vlan_t *pVid) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->dot1x_guestVlan_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->dot1x_guestVlan_get(pVid); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_dot1x_guestVlan2Auth_set + * Description: + * Set 802.1x guest VLAN to auth host configuration + * Input: + * enable - The status of guest VLAN to auth host. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * Note: + * The operational direction of 802.1x guest VLAN to auth host control is as following: + * - ENABLED + * - DISABLED + */ +rtk_api_ret_t rtk_dot1x_guestVlan2Auth_set(rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->dot1x_guestVlan2Auth_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->dot1x_guestVlan2Auth_set(enable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_dot1x_guestVlan2Auth_get + * Description: + * Get 802.1x guest VLAN to auth host configuration + * Input: + * None + * Output: + * pEnable - The status of guest VLAN to auth host. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get 802.1x guest VLAN to auth host information. + */ +rtk_api_ret_t rtk_dot1x_guestVlan2Auth_get(rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->dot1x_guestVlan2Auth_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->dot1x_guestVlan2Auth_get(pEnable); + RTK_API_UNLOCK(); + + return retVal; +} + + + diff --git a/sources/uboot-be550/drivers/net/rtl8372/dot1x.h b/sources/uboot-be550/drivers/net/rtl8372/dot1x.h new file mode 100755 index 00000000..ed9975b7 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/dot1x.h @@ -0,0 +1,557 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8367/RTL8367C switch high-level API + * + * Feature : The file includes 1X module high-layer API defination + * + */ + +#ifndef __RTK_API_DOT1X_H__ +#define __RTK_API_DOT1X_H__ + + +/* Type of port-based dot1x auth/unauth*/ +typedef enum rtk_dot1x_auth_status_e +{ + UNAUTH = 0, + AUTH, + AUTH_STATUS_END +} rtk_dot1x_auth_status_t; + +typedef enum rtk_dot1x_direction_e +{ + DIR_BOTH = 0, + DIR_IN, + DIRECTION_END +} rtk_dot1x_direction_t; + +/* unauth pkt action */ +typedef enum rtk_dot1x_unauth_action_e +{ + DOT1X_ACTION_DROP = 0, + DOT1X_ACTION_TRAP2CPU, + DOT1X_ACTION_GUESTVLAN, + DOT1X_ACTION_END +} rtk_dot1x_unauth_action_t; + +typedef enum rtk_dot1x_cpu_select_e +{ + DOT1X_CPU_SEL_INTERNAL = 1, + DOT1X_CPU_SEL_EXTERNAL, + DOT1X_CPU_SEL_ALL, + DOT1X_CPU_SEL_END +}rtk_dot1x_cpu_select_t; + +/* Function Name: + * rtk_dot1x_unauthPacketOper_set + * Description: + * Set 802.1x unauth action configuration. + * Input: + * port - Port id. + * unauth_action - 802.1X unauth action. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameter. + * Note: + * This API can set 802.1x unauth action configuration. + * The unauth action is as following: + * - DOT1X_ACTION_DROP + * - DOT1X_ACTION_TRAP2CPU + * - DOT1X_ACTION_GUESTVLAN + */ +extern rtk_api_ret_t rtk_dot1x_unauthPacketOper_set(rtk_port_t port, rtk_dot1x_unauth_action_t unauth_action); + +/* Function Name: + * rtk_dot1x_unauthPacketOper_get + * Description: + * Get 802.1x unauth action configuration. + * Input: + * port - Port id. + * Output: + * pUnauth_action - 802.1X unauth action. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can get 802.1x unauth action configuration. + * The unauth action is as following: + * - DOT1X_ACTION_DROP + * - DOT1X_ACTION_TRAP2CPU + * - DOT1X_ACTION_GUESTVLAN + */ +extern rtk_api_ret_t rtk_dot1x_unauthPacketOper_get(rtk_port_t port, rtk_dot1x_unauth_action_t *pUnauth_action); + +/* Function Name: + * rtk_dot1x_eapolFrame2CpuEnable_set + * Description: + * Set 802.1x EAPOL packet trap to CPU configuration + * Input: + * enable - The status of 802.1x EAPOL packet. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * To support 802.1x authentication functionality, EAPOL frame (ether type = 0x888E) has to + * be trapped to CPU. + * The status of EAPOL frame trap to CPU is as following: + * - DISABLED + * - ENABLED + */ +extern rtk_api_ret_t rtk_dot1x_eapolFrame2CpuEnable_set(rtk_enable_t enable); + +/* Function Name: + * rtk_dot1x_eapolFrame2CpuEnable_get + * Description: + * Get 802.1x EAPOL packet trap to CPU configuration + * Input: + * None + * Output: + * pEnable - The status of 802.1x EAPOL packet. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * To support 802.1x authentication functionality, EAPOL frame (ether type = 0x888E) has to + * be trapped to CPU. + * The status of EAPOL frame trap to CPU is as following: + * - DISABLED + * - ENABLED + */ +extern rtk_api_ret_t rtk_dot1x_eapolFrame2CpuEnable_get(rtk_enable_t *pEnable); + +/* Function Name: + * rtk_dot1x_trap2CPU_Sel_set + * Description: + * Select cpu config which unauth packet trap. + * Input: + * cpu_sel - select cpu value. + * Output: + * NULL + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can set cpu config which unauth packet trap. + */ +extern rtk_api_ret_t rtk_dot1x_trap2CPU_Sel_set(rtk_dot1x_cpu_select_t cpu_sel); + +/* Function Name: + * rtk_dot1x_trap2CPU_Sel_get + * Description: + * Select cpu config which unauth packet trap. + * Input: + * NULL + * Output: + * pCpu_sel - 802.1X trap cpu select value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can set cpu config which unauth packet trap. + */ +extern rtk_api_ret_t rtk_dot1x_trap2CPU_Sel_get(rtk_dot1x_cpu_select_t *pCpu_sel); + +/* Function Name: + * rtk_dot1x_trap_priority_set + * Description: + * Set trap priority for unauth packet. + * Input: + * pri_value - priority value. + * Output: + * NULL + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can set trap priority for unauth packet. + */ +extern rtk_api_ret_t rtk_dot1x_trap_priority_set(rtk_pri_t pri_value); + +/* Function Name: + * rtk_dot1x_trap_priority_get + * Description: + * Get trap priority for unauth packet. + * Input: + * pri_value - priority value. + * Output: + * NULL + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can get trap priority for unauth packet. + */ +extern rtk_api_ret_t rtk_dot1x_trap_priority_get(rtk_pri_t *pri_value); + +/* Function Name: + * rtk_dot1x_portBasedEnable_set + * Description: + * Set 802.1x port-based enable configuration + * Input: + * port - Port id. + * enable - The status of 802.1x port. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * RT_ERR_DOT1X_PORTBASEDPNEN - 802.1X port-based enable error + * Note: + * The API can update the port-based port enable register content. If a port is 802.1x + * port based network access control "enabled", it should be authenticated so packets + * from that port won't be dropped or trapped to CPU. + * The status of 802.1x port-based network access control is as following: + * - DISABLED + * - ENABLED + */ +extern rtk_api_ret_t rtk_dot1x_portBasedEnable_set(rtk_port_t port, rtk_enable_t enable); + +/* Function Name: + * rtk_dot1x_portBasedEnable_get + * Description: + * Get 802.1x port-based enable configuration + * Input: + * port - Port id. + * Output: + * pEnable - The status of 802.1x port. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get the 802.1x port-based port status. + */ +extern rtk_api_ret_t rtk_dot1x_portBasedEnable_get(rtk_port_t port, rtk_enable_t *pEnable); + +/* Function Name: + * rtk_dot1x_portBasedAuthStatus_set + * Description: + * Set 802.1x port-based auth. port configuration + * Input: + * port - Port id. + * port_auth - The status of 802.1x port. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_DOT1X_PORTBASEDAUTH - 802.1X port-based auth error + * Note: + * The authenticated status of 802.1x port-based network access control is as following: + * - UNAUTH + * - AUTH + */ +extern rtk_api_ret_t rtk_dot1x_portBasedAuthStatus_set(rtk_port_t port, rtk_dot1x_auth_status_t port_auth); + +/* Function Name: + * rtk_dot1x_portBasedAuthStatus_get + * Description: + * Get 802.1x port-based auth. port configuration + * Input: + * port - Port id. + * Output: + * pPort_auth - The status of 802.1x port. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get 802.1x port-based port auth.information. + */ +extern rtk_api_ret_t rtk_dot1x_portBasedAuthStatus_get(rtk_port_t port, rtk_dot1x_auth_status_t *pPort_auth); + +/* Function Name: + * rtk_dot1x_portBasedDirection_set + * Description: + * Set 802.1x port-based operational direction configuration + * Input: + * port - Port id. + * port_direction - Operation direction + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_DOT1X_PORTBASEDOPDIR - 802.1X port-based operation direction error + * Note: + * The operate controlled direction of 802.1x port-based network access control is as following: + * - BOTH + * - IN + */ +extern rtk_api_ret_t rtk_dot1x_portBasedDirection_set(rtk_port_t port, rtk_dot1x_direction_t port_direction); + +/* Function Name: + * rtk_dot1x_portBasedDirection_get + * Description: + * Get 802.1X port-based operational direction configuration + * Input: + * port - Port id. + * Output: + * pPort_direction - Operation direction + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get 802.1x port-based operational direction information. + */ +extern rtk_api_ret_t rtk_dot1x_portBasedDirection_get(rtk_port_t port, rtk_dot1x_direction_t *pPort_direction); + +/* Function Name: + * rtk_dot1x_macBasedEnable_set + * Description: + * Set 802.1x mac-based port enable configuration + * Input: + * port - Port id. + * enable - The status of 802.1x port. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * RT_ERR_DOT1X_MACBASEDPNEN - 802.1X mac-based enable error + * Note: + * If a port is 802.1x MAC based network access control "enabled", the incoming packets should + * be authenticated so packets from that port won't be dropped or trapped to CPU. + * The status of 802.1x MAC-based network access control is as following: + * - DISABLED + * - ENABLED + */ +extern rtk_api_ret_t rtk_dot1x_macBasedEnable_set(rtk_port_t port, rtk_enable_t enable); + +/* Function Name: + * rtk_dot1x_macBasedEnable_get + * Description: + * Get 802.1x mac-based port enable configuration + * Input: + * port - Port id. + * Output: + * pEnable - The status of 802.1x port. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * If a port is 802.1x MAC based network access control "enabled", the incoming packets should + * be authenticated so packets from that port wont be dropped or trapped to CPU. + * The status of 802.1x MAC-based network access control is as following: + * - DISABLED + * - ENABLED + */ +extern rtk_api_ret_t rtk_dot1x_macBasedEnable_get(rtk_port_t port, rtk_enable_t *pEnable); + +/* Function Name: + * rtk_dot1x_macBasedAuthMac_add + * Description: + * Add an authenticated MAC to ASIC + * Input: + * port - Port id. + * pAuth_mac - The authenticated MAC. + * fid - filtering database. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * RT_ERR_DOT1X_MACBASEDPNEN - 802.1X mac-based enable error + * Note: + * The API can add a 802.1x authenticated MAC address to port. If the MAC does not exist in LUT, + * user can't add this MAC to auth status. + */ +extern rtk_api_ret_t rtk_dot1x_macBasedAuthMac_add(rtk_port_t port, rtk_mac_t *pAuth_mac, rtk_fid_t fid); + +/* Function Name: + * rtk_dot1x_macBasedAuthMac_del + * Description: + * Delete an authenticated MAC to ASIC + * Input: + * port - Port id. + * pAuth_mac - The authenticated MAC. + * fid - filtering database. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can delete a 802.1x authenticated MAC address to port. It only change the auth status of + * the MAC and won't delete it from LUT. + */ +extern rtk_api_ret_t rtk_dot1x_macBasedAuthMac_del(rtk_port_t port, rtk_mac_t *pAuth_mac, rtk_fid_t fid); + +/* Function Name: + * rtk_dot1x_macBasedDirection_set + * Description: + * Set 802.1x mac-based operational direction configuration + * Input: + * mac_direction - Operation direction + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_DOT1X_MACBASEDOPDIR - 802.1X mac-based operation direction error + * Note: + * The operate controlled direction of 802.1x mac-based network access control is as following: + * - BOTH + * - IN + */ +extern rtk_api_ret_t rtk_dot1x_macBasedDirection_set(rtk_dot1x_direction_t mac_direction); + +/* Function Name: + * rtk_dot1x_macBasedDirection_get + * Description: + * Get 802.1x mac-based operational direction configuration + * Input: + * port - Port id. + * Output: + * pMac_direction - Operation direction + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get 802.1x mac-based operational direction information. + */ +extern rtk_api_ret_t rtk_dot1x_macBasedDirection_get(rtk_dot1x_direction_t *pMac_direction); + +/* Function Name: + * Set 802.1x guest VLAN configuration + * Description: + * Set 802.1x mac-based operational direction configuration + * Input: + * vid - 802.1x guest VLAN ID + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * Note: + * The operate controlled 802.1x guest VLAN + */ +extern rtk_api_ret_t rtk_dot1x_guestVlan_set(rtk_vlan_t vid); + +/* Function Name: + * rtk_dot1x_guestVlan_get + * Description: + * Get 802.1x guest VLAN configuration + * Input: + * None + * Output: + * pVid - 802.1x guest VLAN ID + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get 802.1x guest VLAN information. + */ +extern rtk_api_ret_t rtk_dot1x_guestVlan_get(rtk_vlan_t *pVid); + +/* Function Name: + * rtk_dot1x_guestVlan2Auth_set + * Description: + * Set 802.1x guest VLAN to auth host configuration + * Input: + * enable - The status of guest VLAN to auth host. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * Note: + * The operational direction of 802.1x guest VLAN to auth host control is as following: + * - ENABLED + * - DISABLED + */ +extern rtk_api_ret_t rtk_dot1x_guestVlan2Auth_set(rtk_enable_t enable); + +/* Function Name: + * rtk_dot1x_guestVlan2Auth_get + * Description: + * Get 802.1x guest VLAN to auth host configuration + * Input: + * None + * Output: + * pEnable - The status of guest VLAN to auth host. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get 802.1x guest VLAN to auth host information. + */ +extern rtk_api_ret_t rtk_dot1x_guestVlan2Auth_get(rtk_enable_t *pEnable); + + +#endif /* __RTK_API_DOT1X_H__ */ + + diff --git a/sources/uboot-be550/drivers/net/rtl8372/eee.c b/sources/uboot-be550/drivers/net/rtl8372/eee.c new file mode 100755 index 00000000..e3ee87af --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/eee.c @@ -0,0 +1,240 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8373 + * Feature : Here is a list of all functions and variables in EEE module. + * + */ + +#include +#include +#include +#include + +#include + + +/* Function Name: + * rtk_eee_init + * Description: + * Initial EEE function. + * Input: + * None + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * This API can set EEE function to the specific port. + * The configuration of the port is as following: + * - DISABLE + * - ENABLE + */ + +rtk_api_ret_t rtk_eee_init(void) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->eee_init) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->eee_init(); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_eee_macForceSpeedEn_set + * Description: + * Set enable status of EEE for a Specified Speed, + * Input: + * port - port id. + * speed - a specified + * enable - enable EEE status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * This API can set EEE function to the specific port. + * The configuration of the port is as following: + * - DISABLE + * - ENABLE + */ +rtk_api_ret_t rtk_eee_macForceSpeedEn_set(rtk_port_t port, rtk_eee_speedInMacForceMode_t speed, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->eee_macForceSpeedEn_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->eee_macForceSpeedEn_set(port, speed, enable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_eee_macForceSpeedEn_get + * Description: + * Get port_n status of EEE for a Specified Speed, + * Input: + * port - port id. + * speed - a specified + * Output: + * pEnable - EEE status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * This API can get EEE function to the specific port. + * The configuration of the port is as following: + * - DISABLE + * - ENABLE + */ +rtk_api_ret_t rtk_eee_macForceSpeedEn_get(rtk_port_t port, rtk_eee_speedInMacForceMode_t speed, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->eee_macForceSpeedEn_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->eee_macForceSpeedEn_get(port, speed, pEnable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_eee_macForceAllSpeedEn_get + * Description: + * Get port_n status of EEE for all Speed. + * port - port id. + * Output: + * pState - EEE status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * This API can get EEE function to the specific port. + * The configuration of the port is as following: + * - DISABLE + * - ENABLE + */ +rtk_api_ret_t rtk_eee_macForceAllSpeedEn_get(rtk_port_t port, rtk_uint32 *pState) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->eee_macForceAllSpeedEn_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->eee_macForceAllSpeedEn_get(port, pState); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_eee_portTxRxEn_set + * Description: + * Set port_n Tx & Rx EEE capability. + * Input: + * port - port id. + * rxEn - Enable or Disable Rx EEE capability. + * txEn - Enable or Disable Tx EEE capability. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * This API can config tx EEE and rx EEE capability to the specific port. + * The configuration of the port is as following: + * - DISABLE + * - ENABLE + */ +rtk_api_ret_t rtk_eee_portTxRxEn_set(rtk_port_t port, rtk_enable_t rxEn, rtk_enable_t txEn) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->eee_portTxRxEn_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->eee_portTxRxEn_set(port, rxEn, txEn); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_eee_portTxRxEn_set + * Description: + * Set port_n Tx & Rx EEE capability. + * Input: + * port - port id. + * rxEn - Enable or Disable Rx EEE capability. + * txEn - Enable or Disable Tx EEE capability. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * This API can config tx EEE and rx EEE capability to the specific port. + * The configuration of the port is as following: + * - DISABLE + * - ENABLE + */ +rtk_api_ret_t rtk_eee_portTxRxEn_get(rtk_port_t port, rtk_enable_t *pRxEn, rtk_enable_t *pTxEn) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->eee_portTxRxEn_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->eee_portTxRxEn_get(port, pRxEn, pTxEn); + RTK_API_UNLOCK(); + + return retVal; +} + + diff --git a/sources/uboot-be550/drivers/net/rtl8372/eee.h b/sources/uboot-be550/drivers/net/rtl8372/eee.h new file mode 100755 index 00000000..f9fe9952 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/eee.h @@ -0,0 +1,181 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8373 switch high-level API + * + * Feature : The file includes I2C module high-layer API defination + * + */ + +#ifndef __RTK_API_EEE_H__ +#define __RTK_API_EEE_H__ + +#define EEE_GROUP_NUM (5) +#define EEE_MEM_ADDR_WIDTH_MAX (3) +#define EEEE_DATA_WIDTH_MAX (16) + + +typedef enum rtk_eee_speedInMacForceMode_e +{ + EEE_MAC_FORCE_SPEED_100M = 0, + EEE_MAC_FORCE_SPEED_500M, + EEE_MAC_FORCE_SPEED_1000M, + EEE_MAC_FORCE_SPEED_2P5G_LITE, + EEE_MAC_FORCE_SPEED_2P5G, + EEE_MAC_FORCE_SPEED_5G_LITE, + EEE_MAC_FORCE_SPEED_5G, + EEE_MAC_FORCE_SPEED_10G_LITE, + EEE_MAC_FORCE_SPEED_10G, + EEE_MAC_FORCE_SPEED_END +}rtk_eee_speedInMacForceMode_t; + +/* Function Name: + * rtk_eee_init + * Description: + * Initial EEE function. + * Input: + * None + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * This API can set EEE function to the specific port. + * The configuration of the port is as following: + * - DISABLE + * - ENABLE + */ + +extern rtk_api_ret_t rtk_eee_init(void); + +/* Function Name: + * rtk_eee_macForceSpeedEn_set + * Description: + * Set enable status of EEE for a Specified Speed, + * Input: + * port - port id. + * speed - a specified + * enable - enable EEE status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * This API can set EEE function to the specific port. + * The configuration of the port is as following: + * - DISABLE + * - ENABLE + */ +extern rtk_api_ret_t rtk_eee_macForceSpeedEn_set(rtk_port_t port, rtk_eee_speedInMacForceMode_t speed, rtk_enable_t enable); + +/* Function Name: + * rtk_eee_macForceSpeedEn_get + * Description: + * Get port_n status of EEE for a Specified Speed, + * Input: + * port - port id. + * speed - a specified + * Output: + * pEnable - EEE status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * This API can get EEE function to the specific port. + * The configuration of the port is as following: + * - DISABLE + * - ENABLE + */ +extern rtk_api_ret_t rtk_eee_macForceSpeedEn_get(rtk_port_t port, rtk_eee_speedInMacForceMode_t speed, rtk_enable_t *pEnable); + +/* Function Name: + * rtk_eee_macForceAllSpeedEn_get + * Description: + * Get port_n status of EEE for all Speed. + * port - port id. + * Output: + * pState - EEE status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * This API can get EEE function to the specific port. + * The configuration of the port is as following: + * - DISABLE + * - ENABLE + */ +extern rtk_api_ret_t rtk_eee_macForceAllSpeedEn_get(rtk_port_t port, rtk_uint32 *pState); + +/* Function Name: + * rtk_eee_portTxRxEn_set + * Description: + * Set port_n Tx & Rx EEE capability. + * Input: + * port - port id. + * rxEn - Enable or Disable Rx EEE capability. + * txEn - Enable or Disable Tx EEE capability. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * This API can config tx EEE and rx EEE capability to the specific port. + * The configuration of the port is as following: + * - DISABLE + * - ENABLE + */ +extern rtk_api_ret_t rtk_eee_portTxRxEn_set(rtk_port_t port, rtk_enable_t rxEn, rtk_enable_t txEn); + +/* Function Name: + * rtk_eee_portTxRxEn_set + * Description: + * Set port_n Tx & Rx EEE capability. + * Input: + * port - port id. + * rxEn - Enable or Disable Rx EEE capability. + * txEn - Enable or Disable Tx EEE capability. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * This API can config tx EEE and rx EEE capability to the specific port. + * The configuration of the port is as following: + * - DISABLE + * - ENABLE + */ +extern rtk_api_ret_t rtk_eee_portTxRxEn_get(rtk_port_t port, rtk_enable_t *pRxEn, rtk_enable_t *pTxEn); + +#endif /* __RTK_API_EEE_H__ */ + diff --git a/sources/uboot-be550/drivers/net/rtl8372/gpio.c b/sources/uboot-be550/drivers/net/rtl8372/gpio.c new file mode 100755 index 00000000..58daf990 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/gpio.c @@ -0,0 +1,322 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8373 + * Feature : Here is a list of all functions and variables in GPIO module. + * + */ + +#include +#include +#include +#include +#include + + + + +/* Function Name: + * rtk_gpio_muxSel_set + * Description: + * enable gpio function + * Input: + * gpioNum - GPIO pin number + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RANGE - out of range + * Note: + * + */ +rtk_api_ret_t rtk_gpio_muxSel_set(rtk_uint32 gpioNum) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (NULL == RT_MAPPER->gpio_muxSel_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->gpio_muxSel_set(gpioNum); + RTK_API_UNLOCK(); + + return retVal; +} + + +/* Function Name: + * dal_rtl8371c_gpio_muxSel_get + * Description: + * Get gpio pin status + * Input: + * gpioNum - GPIO pin number + * Output: + * *pStatus - status + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RANGE - out of range + * Note: + * + */ + rtk_api_ret_t rtk_gpio_muxSel_get(rtk_uint32 gpioNum, rtk_enable_t *pStatus ) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (NULL == RT_MAPPER->gpio_muxSel_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->gpio_muxSel_get(gpioNum, pStatus); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_gpio_groupVal_write + * Description: + * write group 32bits gpio pin val + * Input: + * idx - GPIO pin LSB 32bits or MSB 31bits + * val - value + * Output: + * none + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RANGE - out of range + * Note: + * + */ +rtk_api_ret_t rtk_gpio_groupVal_write(rtk_gpio_groupReg_t idx, rtk_uint32 val ) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (NULL == RT_MAPPER->gpio_pinVal_write) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->gpio_pinVal_write(idx, val); + RTK_API_UNLOCK(); + + return retVal; + +} + +/* Function Name: + * rtk_gpio_groupVal_read + * Description: + * Read group 32bits gpio pin val + * Input: + * idx - GPIO pin LSB 32bits or MSB 31bits + * Output: + * *pVal - value + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RANGE - out of range + * Note: + * + */ +rtk_api_ret_t rtk_gpio_groupVal_read(rtk_gpio_groupReg_t idx, rtk_uint32 *pVal) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (NULL == RT_MAPPER->gpio_pinVal_read) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->gpio_pinVal_read(idx, pVal); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_gpio_pinVal_write + * Description: + * write gpio pin val + * Input: + * gpioNum - GPIO pin num + * val - value + * Output: + * none + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RANGE - out of range + * Note: + * + */ +rtk_api_ret_t rtk_gpio_pinVal_write(rtk_uint32 gpioNum, rtk_gpio_level_t val) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (NULL == RT_MAPPER->gpio_pinVal_write) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->gpio_pinVal_write(gpioNum, val); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_gpio_pinVal_read + * Description: + * Read gpio pin val + * Input: + * gpioNum - GPIO pin num + * Output: + * *pVal - value + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RANGE - out of range + * Note: + * + */ +rtk_api_ret_t rtk_gpio_pinVal_read(rtk_uint32 gpioNum, rtk_gpio_level_t *pVal) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (NULL == RT_MAPPER->gpio_pinVal_read) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->gpio_pinVal_read(gpioNum, pVal); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_gpio_pinDir_set + * Description: + * set gpio pin direction + * Input: + * gpioNum - GPIO pin num + * dir - GPIO pin direction + * Output: + * none + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RANGE - out of range + * Note: + * + */ +rtk_api_ret_t rtk_gpio_pinDir_set(rtk_uint32 gpioNum, rtk_gpio_direction_t dir) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (NULL == RT_MAPPER->gpio_pinDir_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->gpio_pinDir_set(gpioNum, dir); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_gpio_pinDir_get + * Description: + * Get gpio pin direction + * Input: + * gpioNum - GPIO pin num + * Output: + * dir - GPIO pin direction + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RANGE - out of range + * Note: + * + */ +rtk_api_ret_t rtk_gpio_pinDir_get(rtk_uint32 gpioNum, rtk_gpio_direction_t *pDir) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (NULL == RT_MAPPER->gpio_pinDir_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->gpio_pinDir_get(gpioNum, pDir); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_gpio_groupDir_get + * Description: + * Get gpio pin direction + * Input: + * idx - GPIO pin LSB 32bits or MSB 31bits + * Output: + * pDirVal - Group GPIO pin direction + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RANGE - out of range + * Note: + * + */ +rtk_api_ret_t rtk_gpio_groupDir_get(rtk_gpio_groupReg_t idx, rtk_uint32 *pDirVal) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (NULL == RT_MAPPER->gpio_groupDir_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->gpio_groupDir_get(idx, pDirVal); + RTK_API_UNLOCK(); + + return retVal; +} + + diff --git a/sources/uboot-be550/drivers/net/rtl8372/gpio.h b/sources/uboot-be550/drivers/net/rtl8372/gpio.h new file mode 100755 index 00000000..6a4a1a4a --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/gpio.h @@ -0,0 +1,203 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8373 switch high-level API + * + * Feature : The file includes GPIO module high-layer API defination + * + */ + +#ifndef __RTK_API_GPIO_H__ +#define __RTK_API_GPIO_H__ + +#define GPIO_PIN_NUM (64) +#define GPIO_MAX_PIN_NUM (GPIO_PIN_NUM -1) + +typedef enum rtk_gpio_groupReg_e +{ + GPIO_INOUT_LSB_REG = 0, + GPIO_INOUT_MSB_REG, + GPIO_INOUT_REG_END, +}rtk_gpio_groupReg_t; + +typedef enum rtk_gpio_direction_e +{ + GPIO_DIR_INPUT = 0, + GPIO_DIR_OUTPUT, + GPIO_DIR_END, +}rtk_gpio_direction_t; + +typedef enum rtk_gpio_level_e +{ + GPIO_LEVEL_LOW = 0, + GPIO_LEVEL_HIGH, + GPIO_LEVEL_END, +}rtk_gpio_level_t; + +/* Function Name: + * rtk_gpio_muxSel_set + * Description: + * enable gpio function + * Input: + * gpioNum - GPIO pin number + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RANGE - out of range + * Note: + * + */ +extern rtk_api_ret_t rtk_gpio_muxSel_set(rtk_uint32 gpioNum); + +/* Function Name: + * dal_rtl8371c_gpio_muxSel_get + * Description: + * Get gpio pin status + * Input: + * gpioNum - GPIO pin number + * Output: + * *pStatus - status + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RANGE - out of range + * Note: + * + */ +extern rtk_api_ret_t rtk_gpio_muxSel_get(rtk_uint32 gpioNum, rtk_enable_t *pStatus ); + +/* Function Name: + * rtk_gpio_groupVal_write + * Description: + * write group 32bits gpio pin val + * Input: + * idx - GPIO pin LSB 32bits or MSB 31bits + * val - value + * Output: + * none + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RANGE - out of range + * Note: + * + */ +extern rtk_api_ret_t rtk_gpio_groupVal_write(rtk_gpio_groupReg_t idx, rtk_uint32 val); + +/* Function Name: + * rtk_gpio_groupVal_read + * Description: + * Read group 32bits gpio pin val + * Input: + * idx - GPIO pin LSB 32bits or MSB 31bits + * Output: + * *pVal - value + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RANGE - out of range + * Note: + * + */ +extern rtk_api_ret_t rtk_gpio_groupVal_read(rtk_gpio_groupReg_t idx, rtk_uint32 *pVal); + +/* Function Name: + * rtk_gpio_pinVal_write + * Description: + * write gpio pin val + * Input: + * gpioNum - GPIO pin num + * val - value + * Output: + * none + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RANGE - out of range + * Note: + * + */ +extern rtk_api_ret_t rtk_gpio_pinVal_write(rtk_uint32 gpioNum, rtk_gpio_level_t val ); + +/* Function Name: + * rtk_gpio_pinVal_read + * Description: + * Read gpio pin val + * Input: + * gpioNum - GPIO pin num + * Output: + * *pVal - value + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RANGE - out of range + * Note: + * + */ +extern rtk_api_ret_t rtk_gpio_pinVal_read(rtk_uint32 gpioNum, rtk_gpio_level_t *pVal); + +/* Function Name: + * rtk_gpio_pinDir_set + * Description: + * set gpio pin direction + * Input: + * gpioNum - GPIO pin num + * dir - GPIO pin direction + * Output: + * none + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RANGE - out of range + * Note: + * + */ +extern rtk_api_ret_t rtk_gpio_pinDir_set(rtk_uint32 gpioNum, rtk_gpio_direction_t dir); + +/* Function Name: + * rtk_gpio_pinDir_get + * Description: + * Get gpio pin direction + * Input: + * gpioNum - GPIO pin num + * Output: + * dir - GPIO pin direction + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RANGE - out of range + * Note: + * + */ +extern rtk_api_ret_t rtk_gpio_pinDir_get(rtk_uint32 gpioNum, rtk_gpio_direction_t *pDir); + +/* Function Name: + * rtk_gpio_groupDir_get + * Description: + * Get gpio pin direction + * Input: + * idx - GPIO pin LSB 32bits or MSB 31bits + * Output: + * pDirVal - Group GPIO pin direction + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RANGE - out of range + * Note: + * + */ +extern rtk_api_ret_t rtk_gpio_groupDir_get(rtk_gpio_groupReg_t idx, rtk_uint32 *pDirVal); + +#endif /* __RTK_API_GPIO_H__ */ + + diff --git a/sources/uboot-be550/drivers/net/rtl8372/i2c.c b/sources/uboot-be550/drivers/net/rtl8372/i2c.c new file mode 100755 index 00000000..3f14b819 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/i2c.c @@ -0,0 +1,265 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8373 + * Feature : Here is a list of all functions and variables in I2C module. + * + */ + +#include +#include +#include +#include +#include + +/* Function Name: + * rtk_i2c_init + * Description: + * initial i2c config + * Input: + * clkRate - I2C SCL clock rate + * deviceAddr - I2C slave device address + * Output: + * none + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RANGE - out of range + * Note: + * + */ +rtk_api_ret_t rtk_i2c_init(rtk_i2c_sclClockRate_t clkRate, rtk_uint32 deviceAddr) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (NULL == RT_MAPPER->i2c_init) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->i2c_init(clkRate, deviceAddr); + RTK_API_UNLOCK(); + + return retVal; + +} + +/* Function Name: + * rtk_i2c_readMode_set + * Description: + * set i2c read mode + * Input: + * mode - standard mode or old mode + * Output: + * none + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RANGE - out of range + * Note: + * + */ +rtk_api_ret_t rtk_i2c_readMode_set(rtk_i2c_readMode_t mode) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (NULL == RT_MAPPER->i2c_readMode_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->i2c_readMode_set(mode); + RTK_API_UNLOCK(); + + return retVal; + +} + +/* Function Name: + * rtk_i2c_readMode_get + * Description: + * get i2c read mode + * Input: + * none + * Output: + * pMode - standard mode or old mode + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RANGE - out of range + * Note: + * + */ +rtk_api_ret_t rtk_i2c_readMode_get(rtk_i2c_readMode_t *pMode) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (NULL == RT_MAPPER->i2c_readMode_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->i2c_readMode_get(pMode); + RTK_API_UNLOCK(); + + return retVal; + +} + +/* Function Name: + * rtk_i2c_gpioPinGroup_set + * Description: + * config i2c scl and sda used gpio pin + * Input: + * sclNum - scl pad num + * sdaNum - sda pad num + * Output: + * none + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RANGE - out of range + * Note: + * + */ +rtk_api_ret_t rtk_i2c_gpioPinGroup_set(rtk_uint32 sclNum, rtk_uint32 sdaNum) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (NULL == RT_MAPPER->i2c_gpioPinGroup_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->i2c_gpioPinGroup_set(sclNum, sdaNum); + RTK_API_UNLOCK(); + + return retVal; + +} + +/* Function Name: + * rtk_i2c_gpioPinGroup_get + * Description: + * config i2c scl and sda used gpio pin + * Input: + * none + * Output: + * pSclNum - scl pad num + * pSdaNum - sda pad num + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RANGE - out of range + * Note: + * + */ +rtk_api_ret_t rtk_i2c_gpioPinGroup_get(rtk_uint32 *pSclNum, rtk_uint32 *pSdaNum) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (NULL == RT_MAPPER->i2c_gpioPinGroup_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->i2c_gpioPinGroup_get(pSclNum, pSdaNum); + RTK_API_UNLOCK(); + + return retVal; + +} + +/* Function Name: + * rtk_i2c_data_read + * Description: + * i2c master read slave device data + * Input: + * memAddr - slave device memory address + * dataWidth - want to read data width (1~16) + * memAddrWidth - slave device memory address width (0~3) + * Output: + * pReadData - slave device data that has read + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RANGE - out of range + * Note: + * + */ +rtk_api_ret_t rtk_i2c_data_read(rtk_uint32 memAddr, rtk_uint32 dataWidth, rtk_uint32 memAddrWidth, rtk_uint32 *pReadData) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (NULL == RT_MAPPER->i2c_data_read) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->i2c_data_read(memAddr, dataWidth, memAddrWidth, pReadData); + RTK_API_UNLOCK(); + + return retVal; + +} + +/* Function Name: + * rtk_i2c_data_write + * Description: + * i2c master write data to slave device's memory + * Input: + * memAddr - slave device memory address want to write + * dataWidth - want to write data's width (1~16) + * memAddrWidth - slave device memory address width (0~3) + * pWriteData - the data going to wirte to slave device + * Output: + * none + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RANGE - out of range + * Note: + * + */ +rtk_api_ret_t rtk_i2c_data_write(rtk_uint32 memAddr, rtk_uint32 dataWidth, rtk_uint32 memAddrWidth, rtk_uint32 *pWriteData) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (NULL == RT_MAPPER->i2c_data_write) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->i2c_data_write(memAddr, dataWidth, memAddrWidth, pWriteData); + RTK_API_UNLOCK(); + + return retVal; +} + + + diff --git a/sources/uboot-be550/drivers/net/rtl8372/i2c.h b/sources/uboot-be550/drivers/net/rtl8372/i2c.h new file mode 100755 index 00000000..30543264 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/i2c.h @@ -0,0 +1,187 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8373 switch high-level API + * + * Feature : The file includes I2C module high-layer API defination + * + */ + +#ifndef __RTK_API_I2C_H__ +#define __RTK_API_I2C_H__ + +#define I2C_GROUP_NUM (5) +#define I2C_MEM_ADDR_WIDTH_MAX (3) +#define I2C_DATA_WIDTH_MAX (16) + + +typedef enum rtk_i2c_readMode_e +{ + I2C_READ_STANDARD_MODE = 0, + I2C_READ_OLD_MODE, + I2C_READ_MODE_END +}rtk_i2c_readMode_t; + +typedef enum rtk_i2c_sclClockRate_e +{ + I2C_SCL_CLK_50KHZ = 0, + I2C_SCL_CLK_100KHZ, + I2C_SCL_CLK_400KHZ, + I2C_SCL_CLK_2500KHZ, + I2C_SCL_CLK_END +}rtk_i2c_sclClockRate_t; + +typedef enum rtk_i2c_rwActTrigger_e +{ + I2C_RW_ACT_IDLE = 0, + I2C_RW_ACT_TRIGGER, + I2C_RW_ACT_END +}rtk_i2c_rwActTrigger_t; + +typedef enum rtk_i2c_rwOperation_e +{ + I2C_RW_OP_READ = 0, + I2C_RW_OP_WRITE, + I2C_RW_OP_END +}rtk_i2c_rwOperation_t; + + +/* Function Name: + * rtk_i2c_init + * Description: + * initial i2c config + * Input: + * clkRate - I2C SCL clock rate + * deviceAddr - I2C slave device address + * Output: + * none + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RANGE - out of range + * Note: + * + */ +extern rtk_api_ret_t rtk_i2c_init(rtk_i2c_sclClockRate_t clkRate, rtk_uint32 deviceAddr); + +/* Function Name: + * rtk_i2c_readMode_set + * Description: + * set i2c read mode + * Input: + * mode - standard mode or old mode + * Output: + * none + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RANGE - out of range + * Note: + * + */ +extern rtk_api_ret_t rtk_i2c_readMode_set(rtk_i2c_readMode_t mode); + +/* Function Name: + * rtk_i2c_readMode_get + * Description: + * get i2c read mode + * Input: + * none + * Output: + * pMode - standard mode or old mode + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RANGE - out of range + * Note: + * + */ +extern rtk_api_ret_t rtk_i2c_readMode_get(rtk_i2c_readMode_t *pMode); + +/* Function Name: + * rtk_i2c_gpioPinGroup_set + * Description: + * config i2c scl and sda used gpio pin + * Input: + * sclNum - scl pad num + * sdaNum - sda pad num + * Output: + * none + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RANGE - out of range + * Note: + * + */ +extern rtk_api_ret_t rtk_i2c_gpioPinGroup_set(rtk_uint32 sclNum, rtk_uint32 sdaNum); + +/* Function Name: + * rtk_i2c_gpioPinGroup_get + * Description: + * config i2c scl and sda used gpio pin + * Input: + * none + * Output: + * pSclNum - scl pad num + * pSdaNum - sda pad num + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RANGE - out of range + * Note: + * + */ +extern rtk_api_ret_t rtk_i2c_gpioPinGroup_get(rtk_uint32 *pSclNum, rtk_uint32 *pSdaNum); + +/* Function Name: + * rtk_i2c_data_read + * Description: + * i2c master read slave device data + * Input: + * memAddr - slave device memory address + * dataWidth - want to read data width (1~16) + * memAddrWidth - slave device memory address width (0~3) + * Output: + * pReadData - slave device data that has read + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RANGE - out of range + * Note: + * + */ +extern rtk_api_ret_t rtk_i2c_data_read(rtk_uint32 memAddr, rtk_uint32 dataWidth, rtk_uint32 memAddrWidth, rtk_uint32 *pReadData); + +/* Function Name: + * rtk_i2c_data_write + * Description: + * i2c master write data to slave device's memory + * Input: + * memAddr - slave device memory address want to write + * dataWidth - want to write data's width (1~16) + * memAddrWidth - slave device memory address width (0~3) + * pWriteData - the data going to wirte to slave device + * Output: + * none + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_RANGE - out of range + * Note: + * + */ +extern rtk_api_ret_t rtk_i2c_data_write(rtk_uint32 memAddr, rtk_uint32 dataWidth, rtk_uint32 memAddrWidth, rtk_uint32 *pWriteData); + + +#endif /* __RTK_API_I2C_H__ */ + + diff --git a/sources/uboot-be550/drivers/net/rtl8372/identify.c b/sources/uboot-be550/drivers/net/rtl8372/identify.c new file mode 100755 index 00000000..6028298e --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/identify.c @@ -0,0 +1,126 @@ + +/* + * Copyright (C) 2010 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API + * Feature : Here is a list of all functions and variables in this module. + * + */ + //#include "phydef.h" +#include +#include +#include +#include "miim.h" +#include "ptp.h" +#include "identify.h" +#if defined(CONFIG_SDK_RTL8224) +#include "phy_rtl8224.h" +#endif +#include + +#if defined(CONFIG_SDK_RTL8224) +static rt_phyInfo_t rtl8224_hal_Ctrl = +{ + 4, + HWP_2_5GE +}; +/* Function Name: + * _phy_identify_8371_serdes + * Description: + * Identify the port is 8371 intra serdes PHY or not? + * Input: + * model_id - model id + * rev_id - revision id + * Output: + * None + * Return: + * RT_ERR_OK - is intra serdes PHY + * RT_ERR_FAILED - access failure or others + * RT_ERR_PHY_NOT_MATCH - is not intra serdes PHY + * Note: + * None + */ +static ret_t _phy_identify_8371_serdes(rtk_uint32 model_id, rtk_uint32 rev_id) +{ + + model_id=rev_id=0; + rev_id=model_id; + + return RT_ERR_OK; +} +#endif + +/* supported internal PHY chip lists */ +static rt_phyctrl_t supported_phys[] = +{ +#if defined(CONFIG_SDK_RTL8224) + {_phy_identify_8371_serdes, RTL8371_FAMILY_ID, PHY_MODEL_ID_NULL, RTK_PHYTYPE_RTL8224,NULL, phy_8224drv_mapper_get, 0, &rtl8224_hal_Ctrl}, +#endif +}; + + +/* Function Name: + * phy_identify_driver_find_blind + * Description: + * Find PHY driver from all drivers + * Input: + * Output: + * None + * Return: + * Otherwise - Pointer of PHY control that found + * Note: + * None + */ +rt_phyctrl_t * phy_identify_driver_find_blindly(void) +{ + rtk_int32 size = 0, i; + + size = sizeof(supported_phys) / sizeof(rt_phyctrl_t); + for (i = size - 1; i >= 0; i--) + { + if ((supported_phys[i].chk_func)( supported_phys[i].phy_model_id, supported_phys[i].phy_rev_id) == RT_ERR_OK) + { + return (&supported_phys[i]); + } + } + return NULL; +} + +/* Function Name: + * phy_identify_init + * Description: + * Initial identify databases + * Input: + * None + * Output: + * None + * Return: + * None + * Note: + * None + */ +rtk_api_ret_t phy_identify_init(void) +{ + rtk_switch_halCtrl_t *pHalCtrl ; + + pHalCtrl = hal_ctrlInfo_get(); + pHalCtrl->pPhy_ctrl= phy_identify_driver_find_blindly(); + if(pHalCtrl->pPhy_ctrl != NULL) + { + pHalCtrl->pPhy_ctrl->pPhydrv = pHalCtrl->pPhy_ctrl->mapperInit_func(); + } + + return RT_ERR_OK; +} + diff --git a/sources/uboot-be550/drivers/net/rtl8372/identify.h b/sources/uboot-be550/drivers/net/rtl8372/identify.h new file mode 100755 index 00000000..08a5543d --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/identify.h @@ -0,0 +1,55 @@ +/* + * Copyright (C) 2009-2016 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : PHY identify service APIs in the SDK. + * + * Feature : PHY identify service APIs + * + */ + +#ifndef __HAL_PHY_IDENTIFY_H__ +#define __HAL_PHY_IDENTIFY_H__ +#include "phydef.h" +/* Function Name: + * phy_identify_driver_find_blind + * Description: + * Find PHY driver from all drivers + * Input: + * Output: + * None + * Return: + * Otherwise - Pointer of PHY control that found + * Note: + * None + */ +extern rt_phyctrl_t * phy_identify_driver_find_blindly(void); + + +/* Function Name: + * phy_identify_init + * Description: + * Initial identify databases + * Input: + * None + * Output: + * None + * Return: + * None + * Note: + * None + */ +extern rtk_api_ret_t phy_identify_init(void); + + +#endif \ No newline at end of file diff --git a/sources/uboot-be550/drivers/net/rtl8372/igmp.c b/sources/uboot-be550/drivers/net/rtl8372/igmp.c new file mode 100755 index 00000000..18c68afe --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/igmp.c @@ -0,0 +1,1117 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8367C + * Feature : Here is a list of all functions and variables in IGMP module. + * + */ + +#include +#include +#include +#include + +#include +#include +/* Function Name: + * rtk_igmp_init + * Description: + * This API enables H/W IGMP and set a default initial configuration. + * Input: + * None. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API enables H/W IGMP and set a default initial configuration. + */ +rtk_api_ret_t rtk_igmp_init(void) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->igmp_init) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->igmp_init(); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_igmp_state_set + * Description: + * This API set H/W IGMP state. + * Input: + * enabled - H/W IGMP state + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error parameter + * Note: + * This API set H/W IGMP state. + */ +rtk_api_ret_t rtk_igmp_state_set(rtk_enable_t enabled) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->igmp_state_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->igmp_state_set(enabled); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_igmp_state_get + * Description: + * This API get H/W IGMP state. + * Input: + * None. + * Output: + * pEnabled - H/W IGMP state + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error parameter + * Note: + * This API set current H/W IGMP state. + */ +rtk_api_ret_t rtk_igmp_state_get(rtk_enable_t *pEnabled) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->igmp_state_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->igmp_state_get(pEnabled); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_igmp_static_router_port_set + * Description: + * Configure static router port + * Input: + * pPortmask - Static Port mask + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Error parameter + * Note: + * This API set static router port + */ +rtk_api_ret_t rtk_igmp_static_router_port_set(rtk_portmask_t *pPortmask) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->igmp_static_router_port_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->igmp_static_router_port_set(pPortmask); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_igmp_static_router_port_get + * Description: + * Get static router port + * Input: + * None. + * Output: + * pPortmask - Static port mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Error parameter + * Note: + * This API get static router port + */ +rtk_api_ret_t rtk_igmp_static_router_port_get(rtk_portmask_t *pPortmask) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->igmp_static_router_port_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->igmp_static_router_port_get(pPortmask); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_igmp_protocol_set + * Description: + * set IGMP/MLD protocol action + * Input: + * port - Port ID + * protocol - IGMP/MLD protocol + * action - Per-port and per-protocol IGMP action seeting + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Error parameter + * Note: + * This API set IGMP/MLD protocol action + */ +rtk_api_ret_t rtk_igmp_protocol_set(rtk_port_t port, rtk_igmp_protocol_t protocol, rtk_igmp_action_t action) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->igmp_protocol_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->igmp_protocol_set(port, protocol, action); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_igmp_protocol_get + * Description: + * set IGMP/MLD protocol action + * Input: + * port - Port ID + * protocol - IGMP/MLD protocol + * action - Per-port and per-protocol IGMP action seeting + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Error parameter + * Note: + * This API set IGMP/MLD protocol action + */ +rtk_api_ret_t rtk_igmp_protocol_get(rtk_port_t port, rtk_igmp_protocol_t protocol, rtk_igmp_action_t *pAction) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->igmp_protocol_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->igmp_protocol_get(port, protocol, pAction); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_igmp_fastLeave_set + * Description: + * set IGMP/MLD FastLeave state + * Input: + * state - ENABLED: Enable FastLeave, DISABLED: disable FastLeave + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_INPUT - Error Input + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API set IGMP/MLD FastLeave state + */ +rtk_api_ret_t rtk_igmp_fastLeave_set(rtk_enable_t state) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->igmp_fastLeave_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->igmp_fastLeave_set(state); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_igmp_fastLeave_get + * Description: + * get IGMP/MLD FastLeave state + * Input: + * None + * Output: + * pState - ENABLED: Enable FastLeave, DISABLED: disable FastLeave + * Return: + * RT_ERR_OK - OK + * RT_ERR_NULL_POINTER - NULL pointer + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API get IGMP/MLD FastLeave state + */ +rtk_api_ret_t rtk_igmp_fastLeave_get(rtk_enable_t *pState) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->igmp_fastLeave_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->igmp_fastLeave_get(pState); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_igmp_maxGroup_set + * Description: + * Set per port multicast group learning limit. + * Input: + * port - Port ID + * group - The number of multicast group learning limit. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_PORT_ID - Error Port ID + * RT_ERR_OUT_OF_RANGE - parameter out of range + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API set per port multicast group learning limit. + */ +rtk_api_ret_t rtk_igmp_maxGroup_set(rtk_port_t port, rtk_uint32 group) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->igmp_maxGroup_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->igmp_maxGroup_set(port, group); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_igmp_maxGroup_get + * Description: + * Get per port multicast group learning limit. + * Input: + * port - Port ID + * Output: + * pGroup - The number of multicast group learning limit. + * Return: + * RT_ERR_OK - OK + * RT_ERR_PORT_ID - Error Port ID + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API get per port multicast group learning limit. + */ +rtk_api_ret_t rtk_igmp_maxGroup_get(rtk_port_t port, rtk_uint32 *pGroup) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->igmp_maxGroup_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->igmp_maxGroup_get(port, pGroup); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_igmp_currentGroup_get + * Description: + * Get per port multicast group learning count. + * Input: + * port - Port ID + * Output: + * pGroup - The number of multicast group learning count. + * Return: + * RT_ERR_OK - OK + * RT_ERR_PORT_ID - Error Port ID + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API get per port multicast group learning count. + */ +rtk_api_ret_t rtk_igmp_currentGroup_get(rtk_port_t port, rtk_uint32 *pGroup) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->igmp_currentGroup_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->igmp_currentGroup_get(port, pGroup); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_igmp_tableFullAction_set + * Description: + * set IGMP/MLD Table Full Action + * Input: + * action - Table Full Action + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_INPUT - Error Input + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +rtk_api_ret_t rtk_igmp_tableFullAction_set(rtk_igmp_tableFullAction_t action) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->igmp_tableFullAction_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->igmp_tableFullAction_set(action); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_igmp_tableFullAction_get + * Description: + * get IGMP/MLD Table Full Action + * Input: + * None + * Output: + * pAction - Table Full Action + * Return: + * RT_ERR_OK - OK + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +rtk_api_ret_t rtk_igmp_tableFullAction_get(rtk_igmp_tableFullAction_t *pAction) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->igmp_tableFullAction_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->igmp_tableFullAction_get(pAction); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_igmp_checksumErrorAction_set + * Description: + * set IGMP/MLD Checksum Error Action + * Input: + * action - Checksum error Action + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_INPUT - Error Input + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +rtk_api_ret_t rtk_igmp_checksumErrorAction_set(rtk_igmp_checksumErrorAction_t action) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->igmp_checksumErrorAction_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->igmp_checksumErrorAction_set(action); + RTK_API_UNLOCK(); + + return retVal; +} + + +/* Function Name: + * rtk_igmp_checksumErrorAction_get + * Description: + * get IGMP/MLD Checksum Error Action + * Input: + * None + * Output: + * pAction - Checksum error Action + * Return: + * RT_ERR_OK - OK + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +rtk_api_ret_t rtk_igmp_checksumErrorAction_get(rtk_igmp_checksumErrorAction_t *pAction) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->igmp_checksumErrorAction_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->igmp_checksumErrorAction_get(pAction); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_igmp_leaveTimer_set + * Description: + * set IGMP/MLD Leave timer + * Input: + * timer - Leave timer + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_INPUT - Error Input + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +rtk_api_ret_t rtk_igmp_leaveTimer_set(rtk_uint32 timer) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->igmp_leaveTimer_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->igmp_leaveTimer_set(timer); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_igmp_leaveTimer_get + * Description: + * get IGMP/MLD Leave timer + * Input: + * None + * Output: + * pTimer - Leave Timer. + * Return: + * RT_ERR_OK - OK + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +rtk_api_ret_t rtk_igmp_leaveTimer_get(rtk_uint32 *pTimer) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->igmp_leaveTimer_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->igmp_leaveTimer_get(pTimer); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_igmp_queryInterval_set + * Description: + * set IGMP/MLD Query Interval + * Input: + * interval - Query Interval + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_INPUT - Error Input + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +rtk_api_ret_t rtk_igmp_queryInterval_set(rtk_uint32 interval) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->igmp_queryInterval_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->igmp_queryInterval_set(interval); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_igmp_queryInterval_get + * Description: + * get IGMP/MLD Query Interval + * Input: + * None. + * Output: + * pInterval - Query Interval + * Return: + * RT_ERR_OK - OK + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +rtk_api_ret_t rtk_igmp_queryInterval_get(rtk_uint32 *pInterval) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->igmp_queryInterval_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->igmp_queryInterval_get(pInterval); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_igmp_robustness_set + * Description: + * set IGMP/MLD Robustness value + * Input: + * robustness - Robustness value + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_INPUT - Error Input + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +rtk_api_ret_t rtk_igmp_robustness_set(rtk_uint32 robustness) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->igmp_robustness_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->igmp_robustness_set(robustness); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_igmp_robustness_get + * Description: + * get IGMP/MLD Robustness value + * Input: + * None + * Output: + * pRobustness - Robustness value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +rtk_api_ret_t rtk_igmp_robustness_get(rtk_uint32 *pRobustness) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->igmp_robustness_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->igmp_robustness_get(pRobustness); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_igmp_dynamicRouterRortAllow_set + * Description: + * Configure dynamic router port allow option + * Input: + * pPortmask - Dynamic Port allow mask + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Error parameter + * Note: + * + */ +rtk_api_ret_t rtk_igmp_dynamicRouterPortAllow_set(rtk_portmask_t *pPortmask) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->igmp_dynamicRouterPortAllow_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->igmp_dynamicRouterPortAllow_set(pPortmask); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_igmp_dynamicRouterRortAllow_get + * Description: + * Get dynamic router port allow option + * Input: + * None. + * Output: + * pPortmask - Dynamic Port allow mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Error parameter + * Note: + * + */ +rtk_api_ret_t rtk_igmp_dynamicRouterPortAllow_get(rtk_portmask_t *pPortmask) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->igmp_dynamicRouterPortAllow_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->igmp_dynamicRouterPortAllow_get(pPortmask); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_igmp_dynamicRouterPort_get + * Description: + * Get dynamic router port + * Input: + * None. + * Output: + * pDynamicRouterPort - Dynamic Router Port + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Error parameter + * Note: + * + */ +rtk_api_ret_t rtk_igmp_dynamicRouterPort_get(rtk_igmp_dynamicRouterPort_t *pDynamicRouterPort) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->igmp_dynamicRouterPort_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->igmp_dynamicRouterPort_get(pDynamicRouterPort); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_igmp_suppressionEnable_set + * Description: + * Configure IGMPv1/v2 & MLDv1 Report/Leave/Done suppression + * Input: + * reportSuppression - Report suppression + * leaveSuppression - Leave suppression + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + * + */ +rtk_api_ret_t rtk_igmp_suppressionEnable_set(rtk_enable_t reportSuppression, rtk_enable_t leaveSuppression) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->igmp_suppressionEnable_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->igmp_suppressionEnable_set(reportSuppression, leaveSuppression); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_igmp_suppressionEnable_get + * Description: + * Get IGMPv1/v2 & MLDv1 Report/Leave/Done suppression + * Input: + * None + * Output: + * pReportSuppression - Report suppression + * pLeaveSuppression - Leave suppression + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * + */ +rtk_api_ret_t rtk_igmp_suppressionEnable_get(rtk_enable_t *pReportSuppression, rtk_enable_t *pLeaveSuppression) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->igmp_suppressionEnable_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->igmp_suppressionEnable_get(pReportSuppression, pLeaveSuppression); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_igmp_portRxPktEnable_set + * Description: + * Configure IGMP/MLD RX Packet configuration + * Input: + * port - Port ID + * pRxCfg - RX Packet Configuration + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * + */ +rtk_api_ret_t rtk_igmp_portRxPktEnable_set(rtk_port_t port, rtk_igmp_rxPktEnable_t *pRxCfg) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->igmp_portRxPktEnable_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->igmp_portRxPktEnable_set(port, pRxCfg); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_igmp_portRxPktEnable_get + * Description: + * Get IGMP/MLD RX Packet configuration + * Input: + * port - Port ID + * pRxCfg - RX Packet Configuration + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * + */ +rtk_api_ret_t rtk_igmp_portRxPktEnable_get(rtk_port_t port, rtk_igmp_rxPktEnable_t *pRxCfg) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->igmp_portRxPktEnable_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->igmp_portRxPktEnable_get(port, pRxCfg); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_igmp_groupInfo_get + * Description: + * Get IGMP/MLD Group database + * Input: + * indes - Index (0~255) + * Output: + * pGroup - Group database information. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * + */ +rtk_api_ret_t rtk_igmp_groupInfo_get(rtk_uint32 index, rtk_igmp_groupInfo_t *pGroup) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->igmp_groupInfo_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->igmp_groupInfo_get(index, pGroup); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_igmp_ReportLeaveFwdAction_set + * Description: + * Set Report Leave packet forwarding action + * Input: + * action - Action + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + * + */ +rtk_api_ret_t rtk_igmp_ReportLeaveFwdAction_set(rtk_igmp_ReportLeaveFwdAct_t action) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->igmp_ReportLeaveFwdAction_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->igmp_ReportLeaveFwdAction_set(action); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_igmp_ReportLeaveFwdAction_get + * Description: + * Get Report Leave packet forwarding action + * Input: + * action - Action + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * RT_ERR_NULL_POINTER - Null Pointer + * Note: + * + */ +rtk_api_ret_t rtk_igmp_ReportLeaveFwdAction_get(rtk_igmp_ReportLeaveFwdAct_t *pAction) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->igmp_ReportLeaveFwdAction_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->igmp_ReportLeaveFwdAction_get(pAction); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_igmp_dropLeaveZeroEnable_set + * Description: + * Set the function of droppping Leave packet with group IP = 0.0.0.0 + * Input: + * enabled - Action 1: drop, 0:pass + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + * + */ +rtk_api_ret_t rtk_igmp_dropLeaveZeroEnable_set(rtk_enable_t enabled) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->igmp_dropLeaveZeroEnable_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->igmp_dropLeaveZeroEnable_set(enabled); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_igmp_dropLeaveZeroEnable_get + * Description: + * Get the function of droppping Leave packet with group IP = 0.0.0.0 + * Input: + * None + * Output: + * pEnabled. - Action 1: drop, 0:pass + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * RT_ERR_NULL_POINTER - Null Pointer + * Note: + * + */ +rtk_api_ret_t rtk_igmp_dropLeaveZeroEnable_get(rtk_enable_t *pEnabled) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->igmp_dropLeaveZeroEnable_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->igmp_dropLeaveZeroEnable_get(pEnabled); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_igmp_bypassGroupRange_set + * Description: + * Set Bypass group + * Input: + * group - bypassed group + * enabled - enabled 1: Bypassed, 0: not bypass + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + * + */ +rtk_api_ret_t rtk_igmp_bypassGroupRange_set(rtk_igmp_bypassGroup_t group, rtk_enable_t enabled) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->igmp_bypassGroupRange_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->igmp_bypassGroupRange_set(group, enabled); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_igmp_bypassGroupRange_get + * Description: + * get Bypass group + * Input: + * group - bypassed group + * Output: + * pEnable - enabled 1: Bypassed, 0: not bypass + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * RT_ERR_NULL_POINTER - Null Pointer + * Note: + * + */ +rtk_api_ret_t rtk_igmp_bypassGroupRange_get(rtk_igmp_bypassGroup_t group, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->igmp_bypassGroupRange_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->igmp_bypassGroupRange_get(group, pEnable); + RTK_API_UNLOCK(); + + return retVal; +} + diff --git a/sources/uboot-be550/drivers/net/rtl8372/igmp.h b/sources/uboot-be550/drivers/net/rtl8372/igmp.h new file mode 100755 index 00000000..dafb482a --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/igmp.h @@ -0,0 +1,771 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8367/RTL8367C switch high-level API + * + * Feature : The file includes IGMP module high-layer API defination + * + */ + +#ifndef __RTK_API_IGMP_H__ +#define __RTK_API_IGMP_H__ + +/* + * Data Type Declaration + */ +typedef enum rtk_igmp_type_e +{ + IGMP_IPV4 = 0, + IGMP_PPPOE_IPV4, + IGMP_MLD, + IGMP_PPPOE_MLD, + IGMP_TYPE_END +} rtk_igmp_type_t; + +typedef enum rtk_trap_igmp_action_e +{ + IGMP_ACTION_FORWARD = 0, + IGMP_ACTION_TRAP2CPU, + IGMP_ACTION_DROP, + IGMP_ACTION_ASIC, + IGMP_ACTION_END +} rtk_igmp_action_t; + +typedef enum rtk_igmp_protocol_e +{ + PROTOCOL_IGMPv1 = 0, + PROTOCOL_IGMPv2, + PROTOCOL_IGMPv3, + PROTOCOL_MLDv1, + PROTOCOL_MLDv2, + PROTOCOL_END +} rtk_igmp_protocol_t; + +typedef enum rtk_igmp_tableFullAction_e +{ + IGMP_TABLE_FULL_FORWARD = 0, + IGMP_TABLE_FULL_DROP, + IGMP_TABLE_FULL_TRAP, + IGMP_TABLE_FULL_OP_END +}rtk_igmp_tableFullAction_t; + +typedef enum rtk_igmp_checksumErrorAction_e +{ + IGMP_CRC_ERR_DROP = 0, + IGMP_CRC_ERR_TRAP, + IGMP_CRC_ERR_FORWARD, + IGMP_CRC_ERR_OP_END +}rtk_igmp_checksumErrorAction_t; + +typedef enum rtk_igmp_bypassGroup_e +{ + IGMP_BYPASS_224_0_0_X = 0, + IGMP_BYPASS_224_0_1_X, + IGMP_BYPASS_239_255_255_X, + IGMP_BYPASS_IPV6_00XX, + IGMP_BYPASS_GROUP_END +}rtk_igmp_bypassGroup_t; + + +typedef struct rtk_igmp_dynamicRouterPort_s +{ + rtk_enable_t dynamicRouterPort0Valid; + rtk_port_t dynamicRouterPort0; + rtk_uint32 dynamicRouterPort0Timer; + rtk_enable_t dynamicRouterPort1Valid; + rtk_port_t dynamicRouterPort1; + rtk_uint32 dynamicRouterPort1Timer; + +}rtk_igmp_dynamicRouterPort_t; + +typedef struct rtk_igmp_rxPktEnable_s +{ + rtk_enable_t rxQuery; + rtk_enable_t rxReport; + rtk_enable_t rxLeave; + rtk_enable_t rxMRP; + rtk_enable_t rxMcast; +}rtk_igmp_rxPktEnable_t; + +typedef struct rtk_igmp_groupInfo_s +{ + rtk_enable_t valid; + rtk_portmask_t member; + rtk_uint32 timer[RTK_PORT_MAX]; + rtk_uint32 reportSuppFlag; +}rtk_igmp_groupInfo_t; + +typedef enum rtk_igmp_ReportLeaveFwdAct_e +{ + IGMP_REPORT_LEAVE_TO_ROUTER = 0, + IGMP_REPORT_LEAVE_TO_ALLPORT, + IGMP_REPORT_LEAVE_TO_ROUTER_PORT_ADV, + IGMP_REPORT_LEAVE_ACT_END +}rtk_igmp_ReportLeaveFwdAct_t; + +/* Function Name: + * rtk_igmp_init + * Description: + * This API enables H/W IGMP and set a default initial configuration. + * Input: + * None. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API enables H/W IGMP and set a default initial configuration. + */ +extern rtk_api_ret_t rtk_igmp_init(void); + +/* Function Name: + * rtk_igmp_state_set + * Description: + * This API set H/W IGMP state. + * Input: + * enabled - H/W IGMP state + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error parameter + * Note: + * This API set H/W IGMP state. + */ +extern rtk_api_ret_t rtk_igmp_state_set(rtk_enable_t enabled); + +/* Function Name: + * rtk_igmp_state_get + * Description: + * This API get H/W IGMP state. + * Input: + * None. + * Output: + * pEnabled - H/W IGMP state + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error parameter + * Note: + * This API set current H/W IGMP state. + */ +extern rtk_api_ret_t rtk_igmp_state_get(rtk_enable_t *pEnabled); + +/* Function Name: + * rtk_igmp_static_router_port_set + * Description: + * Configure static router port + * Input: + * pPortmask - Static Port mask + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Error parameter + * Note: + * This API set static router port + */ +extern rtk_api_ret_t rtk_igmp_static_router_port_set(rtk_portmask_t *pPortmask); + +/* Function Name: + * rtk_igmp_static_router_port_get + * Description: + * Get static router port + * Input: + * None. + * Output: + * pPortmask - Static port mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Error parameter + * Note: + * This API get static router port + */ +extern rtk_api_ret_t rtk_igmp_static_router_port_get(rtk_portmask_t *pPortmask); + +/* Function Name: + * rtk_igmp_protocol_set + * Description: + * set IGMP/MLD protocol action + * Input: + * port - Port ID + * protocol - IGMP/MLD protocol + * action - Per-port and per-protocol IGMP action seeting + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Error parameter + * Note: + * This API set IGMP/MLD protocol action + */ +extern rtk_api_ret_t rtk_igmp_protocol_set(rtk_port_t port, rtk_igmp_protocol_t protocol, rtk_igmp_action_t action); + +/* Function Name: + * rtk_igmp_protocol_get + * Description: + * set IGMP/MLD protocol action + * Input: + * port - Port ID + * protocol - IGMP/MLD protocol + * action - Per-port and per-protocol IGMP action seeting + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Error parameter + * Note: + * This API set IGMP/MLD protocol action + */ +extern rtk_api_ret_t rtk_igmp_protocol_get(rtk_port_t port, rtk_igmp_protocol_t protocol, rtk_igmp_action_t *pAction); + +/* Function Name: + * rtk_igmp_fastLeave_set + * Description: + * set IGMP/MLD FastLeave state + * Input: + * state - ENABLED: Enable FastLeave, DISABLED: disable FastLeave + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_INPUT - Error Input + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API set IGMP/MLD FastLeave state + */ +extern rtk_api_ret_t rtk_igmp_fastLeave_set(rtk_enable_t state); + +/* Function Name: + * rtk_igmp_fastLeave_get + * Description: + * get IGMP/MLD FastLeave state + * Input: + * None + * Output: + * pState - ENABLED: Enable FastLeave, DISABLED: disable FastLeave + * Return: + * RT_ERR_OK - OK + * RT_ERR_NULL_POINTER - NULL pointer + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API get IGMP/MLD FastLeave state + */ +extern rtk_api_ret_t rtk_igmp_fastLeave_get(rtk_enable_t *pState); + +/* Function Name: + * rtk_igmp_maxGroup_set + * Description: + * Set per port multicast group learning limit. + * Input: + * port - Port ID + * group - The number of multicast group learning limit. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_PORT_ID - Error Port ID + * RT_ERR_OUT_OF_RANGE - parameter out of range + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API set per port multicast group learning limit. + */ +extern rtk_api_ret_t rtk_igmp_maxGroup_set(rtk_port_t port, rtk_uint32 group); + +/* Function Name: + * rtk_igmp_maxGroup_get + * Description: + * Get per port multicast group learning limit. + * Input: + * port - Port ID + * Output: + * pGroup - The number of multicast group learning limit. + * Return: + * RT_ERR_OK - OK + * RT_ERR_PORT_ID - Error Port ID + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API get per port multicast group learning limit. + */ +extern rtk_api_ret_t rtk_igmp_maxGroup_get(rtk_port_t port, rtk_uint32 *pGroup); + +/* Function Name: + * rtk_igmp_currentGroup_get + * Description: + * Get per port multicast group learning count. + * Input: + * port - Port ID + * Output: + * pGroup - The number of multicast group learning count. + * Return: + * RT_ERR_OK - OK + * RT_ERR_PORT_ID - Error Port ID + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API get per port multicast group learning count. + */ +extern rtk_api_ret_t rtk_igmp_currentGroup_get(rtk_port_t port, rtk_uint32 *pGroup); + +/* Function Name: + * rtk_igmp_tableFullAction_set + * Description: + * set IGMP/MLD Table Full Action + * Input: + * action - Table Full Action + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_INPUT - Error Input + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +extern rtk_api_ret_t rtk_igmp_tableFullAction_set(rtk_igmp_tableFullAction_t action); + +/* Function Name: + * rtk_igmp_tableFullAction_get + * Description: + * get IGMP/MLD Table Full Action + * Input: + * None + * Output: + * pAction - Table Full Action + * Return: + * RT_ERR_OK - OK + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +extern rtk_api_ret_t rtk_igmp_tableFullAction_get(rtk_igmp_tableFullAction_t *pAction); + +/* Function Name: + * rtk_igmp_checksumErrorAction_set + * Description: + * set IGMP/MLD Checksum Error Action + * Input: + * action - Checksum error Action + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_INPUT - Error Input + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +extern rtk_api_ret_t rtk_igmp_checksumErrorAction_set(rtk_igmp_checksumErrorAction_t action); + +/* Function Name: + * rtk_igmp_checksumErrorAction_get + * Description: + * get IGMP/MLD Checksum Error Action + * Input: + * None + * Output: + * pAction - Checksum error Action + * Return: + * RT_ERR_OK - OK + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +extern rtk_api_ret_t rtk_igmp_checksumErrorAction_get(rtk_igmp_checksumErrorAction_t *pAction); + +/* Function Name: + * rtk_igmp_leaveTimer_set + * Description: + * set IGMP/MLD Leave timer + * Input: + * timer - Leave timer + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_INPUT - Error Input + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +extern rtk_api_ret_t rtk_igmp_leaveTimer_set(rtk_uint32 timer); + +/* Function Name: + * rtk_igmp_leaveTimer_get + * Description: + * get IGMP/MLD Leave timer + * Input: + * None + * Output: + * pTimer - Leave Timer. + * Return: + * RT_ERR_OK - OK + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +extern rtk_api_ret_t rtk_igmp_leaveTimer_get(rtk_uint32 *pTimer); + +/* Function Name: + * rtk_igmp_queryInterval_set + * Description: + * set IGMP/MLD Query Interval + * Input: + * interval - Query Interval + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_INPUT - Error Input + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +extern rtk_api_ret_t rtk_igmp_queryInterval_set(rtk_uint32 interval); + +/* Function Name: + * rtk_igmp_queryInterval_get + * Description: + * get IGMP/MLD Query Interval + * Input: + * None. + * Output: + * pInterval - Query Interval + * Return: + * RT_ERR_OK - OK + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +extern rtk_api_ret_t rtk_igmp_queryInterval_get(rtk_uint32 *pInterval); + +/* Function Name: + * rtk_igmp_robustness_set + * Description: + * set IGMP/MLD Robustness value + * Input: + * robustness - Robustness value + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_INPUT - Error Input + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +extern rtk_api_ret_t rtk_igmp_robustness_set(rtk_uint32 robustness); + +/* Function Name: + * rtk_igmp_robustness_get + * Description: + * get IGMP/MLD Robustness value + * Input: + * None + * Output: + * pRobustness - Robustness value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +extern rtk_api_ret_t rtk_igmp_robustness_get(rtk_uint32 *pRobustness); + +/* Function Name: + * rtk_igmp_dynamicRouterRortAllow_set + * Description: + * Configure dynamic router port allow option + * Input: + * pPortmask - Dynamic Port allow mask + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Error parameter + * Note: + * + */ +extern rtk_api_ret_t rtk_igmp_dynamicRouterPortAllow_set(rtk_portmask_t *pPortmask); + +/* Function Name: + * rtk_igmp_dynamicRouterRortAllow_get + * Description: + * Get dynamic router port allow option + * Input: + * None. + * Output: + * pPortmask - Dynamic Port allow mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Error parameter + * Note: + * + */ +extern rtk_api_ret_t rtk_igmp_dynamicRouterPortAllow_get(rtk_portmask_t *pPortmask); + +/* Function Name: + * rtk_igmp_dynamicRouterPort_get + * Description: + * Get dynamic router port + * Input: + * None. + * Output: + * pDynamicRouterPort - Dynamic Router Port + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Error parameter + * Note: + * + */ +extern rtk_api_ret_t rtk_igmp_dynamicRouterPort_get(rtk_igmp_dynamicRouterPort_t *pDynamicRouterPort); + +/* Function Name: + * rtk_igmp_suppressionEnable_set + * Description: + * Configure IGMPv1/v2 & MLDv1 Report/Leave/Done suppression + * Input: + * reportSuppression - Report suppression + * leaveSuppression - Leave suppression + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + * + */ +extern rtk_api_ret_t rtk_igmp_suppressionEnable_set(rtk_enable_t reportSuppression, rtk_enable_t leaveSuppression); + +/* Function Name: + * rtk_igmp_suppressionEnable_get + * Description: + * Get IGMPv1/v2 & MLDv1 Report/Leave/Done suppression + * Input: + * None + * Output: + * pReportSuppression - Report suppression + * pLeaveSuppression - Leave suppression + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * + */ +extern rtk_api_ret_t rtk_igmp_suppressionEnable_get(rtk_enable_t *pReportSuppression, rtk_enable_t *pLeaveSuppression); + +/* Function Name: + * rtk_igmp_portRxPktEnable_set + * Description: + * Configure IGMP/MLD RX Packet configuration + * Input: + * port - Port ID + * pRxCfg - RX Packet Configuration + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * + */ +extern rtk_api_ret_t rtk_igmp_portRxPktEnable_set(rtk_port_t port, rtk_igmp_rxPktEnable_t *pRxCfg); + +/* Function Name: + * rtk_igmp_portRxPktEnable_get + * Description: + * Get IGMP/MLD RX Packet configuration + * Input: + * port - Port ID + * pRxCfg - RX Packet Configuration + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * + */ +extern rtk_api_ret_t rtk_igmp_portRxPktEnable_get(rtk_port_t port, rtk_igmp_rxPktEnable_t *pRxCfg); + +/* Function Name: + * rtk_igmp_groupInfo_get + * Description: + * Get IGMP/MLD Group database + * Input: + * indes - Index (0~255) + * Output: + * pGroup - Group database information. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * + */ +extern rtk_api_ret_t rtk_igmp_groupInfo_get(rtk_uint32 index, rtk_igmp_groupInfo_t *pGroup); + +/* Function Name: + * rtk_igmp_ReportLeaveFwdAction_set + * Description: + * Set Report Leave packet forwarding action + * Input: + * action - Action + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + * + */ +extern rtk_api_ret_t rtk_igmp_ReportLeaveFwdAction_set(rtk_igmp_ReportLeaveFwdAct_t action); + +/* Function Name: + * rtk_igmp_ReportLeaveFwdAction_get + * Description: + * Get Report Leave packet forwarding action + * Input: + * action - Action + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * RT_ERR_NULL_POINTER - Null Pointer + * Note: + * + */ +extern rtk_api_ret_t rtk_igmp_ReportLeaveFwdAction_get(rtk_igmp_ReportLeaveFwdAct_t *pAction); + +/* Function Name: + * rtk_igmp_dropLeaveZeroEnable_set + * Description: + * Set the function of droppping Leave packet with group IP = 0.0.0.0 + * Input: + * enabled - Action 1: drop, 0:pass + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + * + */ +extern rtk_api_ret_t rtk_igmp_dropLeaveZeroEnable_set(rtk_enable_t enabled); + +/* Function Name: + * rtk_igmp_dropLeaveZeroEnable_get + * Description: + * Get the function of droppping Leave packet with group IP = 0.0.0.0 + * Input: + * None + * Output: + * pEnabled. - Action 1: drop, 0:pass + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * RT_ERR_NULL_POINTER - Null Pointer + * Note: + * + */ +extern rtk_api_ret_t rtk_igmp_dropLeaveZeroEnable_get(rtk_enable_t *pEnabled); + +/* Function Name: + * rtk_igmp_bypassGroupRange_set + * Description: + * Set Bypass group + * Input: + * group - bypassed group + * enabled - enabled 1: Bypassed, 0: not bypass + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + * + */ +extern rtk_api_ret_t rtk_igmp_bypassGroupRange_set(rtk_igmp_bypassGroup_t group, rtk_enable_t enabled); + +/* Function Name: + * rtk_igmp_bypassGroupRange_get + * Description: + * get Bypass group + * Input: + * group - bypassed group + * Output: + * pEnable - enabled 1: Bypassed, 0: not bypass + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * RT_ERR_NULL_POINTER - Null Pointer + * Note: + * + */ +extern rtk_api_ret_t rtk_igmp_bypassGroupRange_get(rtk_igmp_bypassGroup_t group, rtk_enable_t *pEnable); + +#endif /* __RTK_API_IGMP_H__ */ diff --git a/sources/uboot-be550/drivers/net/rtl8372/interrupt.c b/sources/uboot-be550/drivers/net/rtl8372/interrupt.c new file mode 100755 index 00000000..974412ef --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/interrupt.c @@ -0,0 +1,455 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8373 + * Feature : Here is a list of all functions and variables in Interrupt module. + * + */ + +#include +#include +#include +#include + +#include + +/* Function Name: + * rtk_int_enable + * Description: + * Enable interrupt function. + * Input: + * enable - 0 disable, 1 enable. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can set interrupt polarity configuration. + */ +rtk_api_ret_t rtk_int_enable(rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->int_enable) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->int_enable(enable); + RTK_API_UNLOCK(); + + return retVal; +} + + + +/* Function Name: + * rtk_int_polarity_set + * Description: + * Set interrupt polarity configuration. + * Input: + * type - Interruptpolarity type. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can set interrupt polarity configuration. + */ +rtk_api_ret_t rtk_int_polarity_set(rtk_int_polarity_t type) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->int_polarity_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->int_polarity_set(type); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_int_polarity_get + * Description: + * Get interrupt polarity configuration. + * Input: + * None + * Output: + * pType - Interruptpolarity type. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can get interrupt polarity configuration. + */ +rtk_api_ret_t rtk_int_polarity_get(rtk_int_polarity_t *pType) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->int_polarity_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->int_polarity_get(pType); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_portInt_control_set + * Description: + * Set interrupt trigger status configuration. + * Input: + * port - port id + * intcpu - 0 internal cpu interrupt 1 external cpu interrupt + * type - Interrupt type. + * enable - Interrupt status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * The API can set interrupt status configuration. + * The interrupt trigger status is shown in the following: + * - INT_TYPE_LINK_CHANGE, + * - INT_TYPE_GPHY, + * - INT_TYPE_LEARN_OVER, + * - INT_TYPE_RLFD, + * - INT_TYPE_WOL, + * - INT_TYPE_SDS_LINK_FAULT, + * - INT_TYPE_SDS_UPDATE_PHY, + */ +rtk_api_ret_t rtk_portInt_control_set(rtk_port_t port, rtk_int_cpu_t intcpu, rtk_int_type_t type, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->int_control_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->int_control_set(port, intcpu, type, enable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_portInt_control_get + * Description: + * Get interrupt trigger status configuration. + * Input: + * port - port id + * intcpu - 0 internal cpu interrupt 1 external cpu interrupt + * type - Interrupt type. + * enable - Interrupt status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * The API can set interrupt status configuration. + * The interrupt trigger status is shown in the following: + * - INT_TYPE_LINK_CHANGE, + * - INT_TYPE_GPHY, + * - INT_TYPE_LEARN_OVER, + * - INT_TYPE_RLFD, + * - INT_TYPE_WOL, + * - INT_TYPE_SDS_LINK_FAULT, + * - INT_TYPE_SDS_UPDATE_PHY, + */ + +rtk_api_ret_t rtk_portInt_control_get(rtk_port_t port, rtk_int_cpu_t intcpu, rtk_int_type_t type, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->int_control_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->int_control_get(port, intcpu, type, pEnable); + RTK_API_UNLOCK(); + + return retVal; +} +/* Function Name: + * rtk_int_miscIMR_set + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ +rtk_api_ret_t rtk_int_miscIMR_set(rtk_uint32 type, interrupt_misc_t interrupt, rtk_uint32 enable) +{ + + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->int_miscIMR_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->int_miscIMR_set( type, interrupt, enable); + RTK_API_UNLOCK(); + + return retVal; +} + + +/* Function Name: + * dal_rtl8373_miscIMR_get + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ + +rtk_api_ret_t rtk_int_miscIMR_get(rtk_uint32 type, interrupt_misc_t interrupt, rtk_uint32* pEnable) +{ + + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->int_miscIMR_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->int_miscIMR_get(type, interrupt, pEnable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * dal_rtl8373_miscISR_clear + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ + +rtk_api_ret_t rtk_int_miscISR_clear(rtk_uint32 type, interrupt_misc_t interrupt) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->int_miscISR_clear) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->int_miscISR_clear(type, interrupt); + RTK_API_UNLOCK(); + + return retVal; +} + + + + + +/* Function Name: + * dal_rtl8373_glbISR_get + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ + +rtk_api_ret_t rtk_int_miscISR_get(rtk_uint32 type, interrupt_misc_t interrupt, rtk_uint32* pStatus) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->int_miscISR_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->int_miscISR_get(type, interrupt,pStatus); + RTK_API_UNLOCK(); + + return retVal; +} + +#if 0 +/* Function Name: + * rtk_int_status_set + * Description: + * Set interrupt trigger status to clean. + * Input: + * None + * Output: + * pStatusMask - Interrupt status bit mask. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can clean interrupt trigger status when interrupt happened. + * The interrupt trigger status is shown in the following: + * - INT_TYPE_LINK_STATUS (value[0] (Bit0)) + * - INT_TYPE_METER_EXCEED (value[0] (Bit1)) + * - INT_TYPE_LEARN_LIMIT (value[0] (Bit2)) + * - INT_TYPE_LINK_SPEED (value[0] (Bit3)) + * - INT_TYPE_CONGEST (value[0] (Bit4)) + * - INT_TYPE_GREEN_FEATURE (value[0] (Bit5)) + * - INT_TYPE_LOOP_DETECT (value[0] (Bit6)) + * - INT_TYPE_8051 (value[0] (Bit7)) + * - INT_TYPE_CABLE_DIAG (value[0] (Bit8)) + * - INT_TYPE_ACL (value[0] (Bit9)) + * - INT_TYPE_SLIENT (value[0] (Bit11)) + * The status will be cleared after execute this API. + */ +rtk_api_ret_t rtk_int_status_set(rtk_int_status_t *pStatusMask) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->int_status_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->int_status_set(pStatusMask); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_int_status_get + * Description: + * Get interrupt trigger status. + * Input: + * None + * Output: + * pStatusMask - Interrupt status bit mask. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get interrupt trigger status when interrupt happened. + * The interrupt trigger status is shown in the following: + * - INT_TYPE_LINK_STATUS (value[0] (Bit0)) + * - INT_TYPE_METER_EXCEED (value[0] (Bit1)) + * - INT_TYPE_LEARN_LIMIT (value[0] (Bit2)) + * - INT_TYPE_LINK_SPEED (value[0] (Bit3)) + * - INT_TYPE_CONGEST (value[0] (Bit4)) + * - INT_TYPE_GREEN_FEATURE (value[0] (Bit5)) + * - INT_TYPE_LOOP_DETECT (value[0] (Bit6)) + * - INT_TYPE_8051 (value[0] (Bit7)) + * - INT_TYPE_CABLE_DIAG (value[0] (Bit8)) + * - INT_TYPE_ACL (value[0] (Bit9)) + * - INT_TYPE_SLIENT (value[0] (Bit11)) + * + */ +rtk_api_ret_t rtk_int_status_get(rtk_int_status_t* pStatusMask) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->int_status_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->int_status_get(pStatusMask); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_int_advanceInfo_get + * Description: + * Get interrupt advanced information. + * Input: + * adv_type - Advanced interrupt type. + * Output: + * info - Information per type. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can get advanced information when interrupt happened. + * The status will be cleared after execute this API. + */ +rtk_api_ret_t rtk_int_advanceInfo_get(rtk_int_advType_t adv_type, rtk_int_info_t *pInfo) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->int_advanceInfo_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->int_advanceInfo_get(adv_type, pInfo); + RTK_API_UNLOCK(); + + return retVal; +} + + #endif + diff --git a/sources/uboot-be550/drivers/net/rtl8372/interrupt.h b/sources/uboot-be550/drivers/net/rtl8372/interrupt.h new file mode 100755 index 00000000..bc377e96 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/interrupt.h @@ -0,0 +1,303 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8373 switch high-level API + * + * Feature : The file includes Interrupt module high-layer API defination + * + */ + +#ifndef __RTK_API_INTERRUPT_H__ +#define __RTK_API_INTERRUPT_H__ + + +/* + * Data Type Declaration + */ + + +typedef enum rtk_int_type_e +{ + INT_TYPE_LINK_CHANGE = 0, + INT_TYPE_GPHY, + INT_TYPE_LEARN_OVER, + INT_TYPE_RLFD, + INT_TYPE_WOL, + INT_TYPE_SDS_LINK_FAULT, + INT_TYPE_SDS_UPDATE_PHY, + INT_TYPE_END +}rtk_int_type_t; + +typedef enum rtk_int_cpu_e +{ + INT_CPU_INTERNAL = 0, + INT_CPU_EXTERNAL, + INT_CPU_END +}rtk_int_cpu_t; + + + +typedef enum rtk_int_polarity_e +{ + INT_POLAR_HIGH = 0, + INT_POLAR_LOW, + INT_POSITIVE_PULSE, + INT_NEGATIVE_PULSE, + INT_POLAR_END +} rtk_int_polarity_t; + +typedef enum interrupt_misc_e +{ + TM_HIGH=0, + TM_LOW, + SMI_CHECK_REG_0, + SMI_CHECK_REG_1, + SMI_CHECK_REG_2, + SMI_CHECK_REG_3, + SMI_CHECK_REG_4, + SDS_RX_SYM_ERR_0, + SDS_RX_SYM_ERR_1, + SAMOVE = 10, + AUTO_REC, + ACL = 13, + INCPU, + LOOP_DETEC, + METER_EXCEED, + ROUT_PBUF, + PTP1588, + INTERRUPT_MISC_END +}interrupt_misc_t; + +typedef enum interrupt_glb_e +{ + THERMAL_DET=0, + SMI_CHK=2, + SDS_RX_ERR=4, + GPIO, + GLB_SAMOVE=7, + GLB_AUTO_REC, + GLBACL=10, + GLB_LOOP_DETEC=12, + GLB_METER_EXCEED, + PTP, + GLB_ROUT_PBUF=24, + SDS_UPD_PHY, + SDS_LNK_FLT, + WOL, + RLFD, + GPHY, + LRN_OVER, + LINK_CHG, + INTERRUPT_GLB_END +}interrupt_glb_t; +/* Function Name: + * rtk_int_enable + * Description: + * Enable interrupt function. + * Input: + * enable - 0 disable, 1 enable. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can set interrupt polarity configuration. + */ +extern rtk_api_ret_t rtk_int_enable(rtk_enable_t enable); + + + +/* Function Name: + * rtk_int_polarity_set + * Description: + * Set interrupt polarity configuration. + * Input: + * type - Interruptpolarity type. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can set interrupt polarity configuration. + */ +extern rtk_api_ret_t rtk_int_polarity_set(rtk_int_polarity_t type); + +/* Function Name: + * rtk_int_polarity_get + * Description: + * Get interrupt polarity configuration. + * Input: + * None + * Output: + * pType - Interruptpolarity type. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can get interrupt polarity configuration. + */ +extern rtk_api_ret_t rtk_int_polarity_get(rtk_int_polarity_t *pType); + +/* Function Name: + * rtk_portInt_control_set + * Description: + * Set interrupt trigger status configuration. + * Input: + * port - port id + * intcpu - 0 internal cpu interrupt 1 external cpu interrupt + * type - Interrupt type. + * enable - Interrupt status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * The API can set interrupt status configuration. + * The interrupt trigger status is shown in the following: + * - INT_TYPE_LINK_CHANGE, + * - INT_TYPE_GPHY, + * - INT_TYPE_LEARN_OVER, + * - INT_TYPE_RLFD, + * - INT_TYPE_WOL, + * - INT_TYPE_SDS_LINK_FAULT, + * - INT_TYPE_SDS_UPDATE_PHY, + */ +extern rtk_api_ret_t rtk_portInt_control_set(rtk_port_t port, rtk_int_cpu_t intcpu, rtk_int_type_t type, rtk_enable_t enable); + +/* Function Name: + * rtk_portInt_control_get + * Description: + * Get interrupt trigger status configuration. + * Input: + * port - port id + * intcpu - 0 internal cpu interrupt 1 external cpu interrupt + * type - Interrupt type. + * enable - Interrupt status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * The API can set interrupt status configuration. + * The interrupt trigger status is shown in the following: + * - INT_TYPE_LINK_CHANGE, + * - INT_TYPE_GPHY, + * - INT_TYPE_LEARN_OVER, + * - INT_TYPE_RLFD, + * - INT_TYPE_WOL, + * - INT_TYPE_SDS_LINK_FAULT, + * - INT_TYPE_SDS_UPDATE_PHY, + */ + +extern rtk_api_ret_t rtk_portInt_control_get(rtk_port_t port, rtk_int_cpu_t intcpu, rtk_int_type_t type, rtk_enable_t *pEnable); +/* Function Name: + * rtk_int_miscIMR_set + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ +extern rtk_api_ret_t rtk_int_miscIMR_set(rtk_uint32 type, interrupt_misc_t interrupt, rtk_uint32 enable); + + + +/* Function Name: + * dal_rtl8373_miscIMR_get + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ + +extern rtk_api_ret_t rtk_int_miscIMR_get(rtk_uint32 type, interrupt_misc_t interrupt, rtk_uint32* pEnable); + + +/* Function Name: + * dal_rtl8373_miscISR_clear + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ + +extern rtk_api_ret_t rtk_int_miscISR_clear(rtk_uint32 type, interrupt_misc_t interrupt); + + + + + +/* Function Name: + * dal_rtl8373_glbISR_get + * Description: + * Set link change interrupt IMR + * Input: + * type : 0 internal interrupt; 1: external interrupt + * port: port id + * enable: 0:disable, 1: enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set wol enable + */ + +extern rtk_api_ret_t rtk_int_miscISR_get(rtk_uint32 type, interrupt_misc_t interrupt, rtk_uint32* pStatus); + +#endif /* __RTK_API_INTERRUPT_H*/ + diff --git a/sources/uboot-be550/drivers/net/rtl8372/isolation.c b/sources/uboot-be550/drivers/net/rtl8372/isolation.c new file mode 100755 index 00000000..7026e4aa --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/isolation.c @@ -0,0 +1,89 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8373 + * Feature : Here is a list of all functions and variables in ISOLATION module. + * + */ + + #include +#include +#include +#include + +#include + + +/* Function Name: + * rtk_port_isolation_set + * Description: + * Set permitted port isolation portmask + * Input: + * port - Physical port number (0~9) + * permitPortmask - port mask + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * RT_ERR_PORT_MASK - Invalid portmask + * Note: + * None + */ +ret_t rtk_port_isolation_set(rtk_port_t port, rtk_uint32 permitPortmask) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->port_isolation_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->port_isolation_set(port, permitPortmask); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_port_isolation_get + * Description: + * Get permitted port isolation portmask + * Input: + * port - Physical port number (0~9) + * pPermitPortmask - port mask + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +ret_t rtk_port_isolation_get(rtk_port_t port, rtk_uint32 *pPermitPortmask) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->port_isolation_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->port_isolation_get(port, pPermitPortmask); + RTK_API_UNLOCK(); + + return retVal; +} + + diff --git a/sources/uboot-be550/drivers/net/rtl8372/isolation.h b/sources/uboot-be550/drivers/net/rtl8372/isolation.h new file mode 100755 index 00000000..a9f41830 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/isolation.h @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8373 switch high-level API + * + * Feature : The file includes ISOLATION module high-layer API defination + * + */ + + +/* Function Name: + * rtk_port_isolation_set + * Description: + * Set permitted port isolation portmask + * Input: + * port - Physical port number (0~9) + * permitPortmask - port mask + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * RT_ERR_PORT_MASK - Invalid portmask + * Note: + * None + */ +extern ret_t rtk_port_isolation_set(rtk_port_t port, rtk_uint32 permitPortmask); + +/* Function Name: + * rtk_port_isolation_get + * Description: + * Get permitted port isolation portmask + * Input: + * port - Physical port number (0~9) + * pPermitPortmask - port mask + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * Note: + * None + */ +extern ret_t rtk_port_isolation_get(rtk_port_t port, rtk_uint32 *pPermitPortmask); + + + + diff --git a/sources/uboot-be550/drivers/net/rtl8372/l2.c b/sources/uboot-be550/drivers/net/rtl8372/l2.c new file mode 100755 index 00000000..33b11731 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/l2.c @@ -0,0 +1,2186 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8367C + * Feature : Here is a list of all functions and variables in L2 module. + * + */ + +#include +#include +#include +#include + +#include + +#if 1 +/* Function Name: + * rtk_l2_init + * Description: + * Initialize l2 module of the specified device. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * Initialize l2 module before calling any l2 APIs. + */ +rtk_api_ret_t rtk_l2_init(void) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_init) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_init(); + RTK_API_UNLOCK(); + + return retVal; +} + + +/* Function Name: + * rtk_l2_addr_add + * Description: + * Add LUT unicast entry. + * Input: + * pMac - 6 bytes unicast(I/G bit is 0) mac address to be written into LUT. + * pL2_data - Unicast entry parameter + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_L2_FID - Invalid FID . + * RT_ERR_L2_INDEXTBL_FULL - hashed index is full of entries. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * If the unicast mac address already existed in LUT, it will udpate the status of the entry. + * Otherwise, it will find an empty or asic auto learned entry to write. If all the entries + * with the same hash value can't be replaced, ASIC will return a RT_ERR_L2_INDEXTBL_FULL error. + */ +rtk_api_ret_t rtk_l2_addr_add(rtk_mac_t *pMac, rtk_l2_ucastAddr_t *pL2_data) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_addr_add) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_addr_add(pMac, pL2_data); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_addr_get + * Description: + * Get LUT unicast entry. + * Input: + * pMac - 6 bytes unicast(I/G bit is 0) mac address to be written into LUT. + * Output: + * pL2_data - Unicast entry parameter + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_L2_FID - Invalid FID . + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * If the unicast mac address existed in LUT, it will return the port and fid where + * the mac is learned. Otherwise, it will return a RT_ERR_L2_ENTRY_NOTFOUND error. + */ +rtk_api_ret_t rtk_l2_addr_get(rtk_mac_t *pMac, rtk_l2_ucastAddr_t *pL2_data) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_addr_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_addr_get(pMac, pL2_data); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_addr_next_get + * Description: + * Get Next LUT unicast entry. + * Input: + * read_method - The reading method. + * port - The port number if the read_metohd is READMETHOD_NEXT_L2UCSPA + * pAddress - The Address ID + * Output: + * pL2_data - Unicast entry parameter + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_L2_FID - Invalid FID . + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * Get the next unicast entry after the current entry pointed by pAddress. + * The address of next entry is returned by pAddress. User can use (address + 1) + * as pAddress to call this API again for dumping all entries is LUT. + */ +rtk_api_ret_t rtk_l2_addr_next_get(rtk_l2_read_method_t read_method, rtk_port_t port, rtk_uint32 *pAddress, rtk_l2_ucastAddr_t *pL2_data) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_addr_next_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_addr_next_get(read_method, port, pAddress, pL2_data); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_addr_del + * Description: + * Delete LUT unicast entry. + * Input: + * pMac - 6 bytes unicast(I/G bit is 0) mac address to be written into LUT. + * fid - Filtering database + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_L2_FID - Invalid FID . + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * If the mac has existed in the LUT, it will be deleted. Otherwise, it will return RT_ERR_L2_ENTRY_NOTFOUND. + */ +rtk_api_ret_t rtk_l2_addr_del(rtk_mac_t *pMac, rtk_l2_ucastAddr_t *pL2_data) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_addr_del) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_addr_del(pMac, pL2_data); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_mcastAddr_add + * Description: + * Add LUT multicast entry. + * Input: + * pMcastAddr - L2 multicast entry structure + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_L2_FID - Invalid FID . + * RT_ERR_L2_VID - Invalid VID . + * RT_ERR_L2_INDEXTBL_FULL - hashed index is full of entries. + * RT_ERR_PORT_MASK - Invalid portmask. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * If the multicast mac address already existed in the LUT, it will udpate the + * port mask of the entry. Otherwise, it will find an empty or asic auto learned + * entry to write. If all the entries with the same hash value can't be replaced, + * ASIC will return a RT_ERR_L2_INDEXTBL_FULL error. + */ +rtk_api_ret_t rtk_l2_mcastAddr_add(rtk_l2_mcastAddr_t *pMcastAddr) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_mcastAddr_add) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_mcastAddr_add(pMcastAddr); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_mcastAddr_get + * Description: + * Get LUT multicast entry. + * Input: + * pMcastAddr - L2 multicast entry structure + * Output: + * pMcastAddr - L2 multicast entry structure + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_L2_FID - Invalid FID . + * RT_ERR_L2_VID - Invalid VID . + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * If the multicast mac address existed in the LUT, it will return the port where + * the mac is learned. Otherwise, it will return a RT_ERR_L2_ENTRY_NOTFOUND error. + */ +rtk_api_ret_t rtk_l2_mcastAddr_get(rtk_l2_mcastAddr_t *pMcastAddr) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_mcastAddr_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_mcastAddr_get(pMcastAddr); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_mcastAddr_next_get + * Description: + * Get Next L2 Multicast entry. + * Input: + * pAddress - The Address ID + * Output: + * pMcastAddr - L2 multicast entry structure + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * Get the next L2 multicast entry after the current entry pointed by pAddress. + * The address of next entry is returned by pAddress. User can use (address + 1) + * as pAddress to call this API again for dumping all multicast entries is LUT. + */ +rtk_api_ret_t rtk_l2_mcastAddr_next_get(rtk_uint32 *pAddress, rtk_l2_mcastAddr_t *pMcastAddr) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_mcastAddr_next_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_mcastAddr_next_get(pAddress, pMcastAddr); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_mcastAddr_del + * Description: + * Delete LUT multicast entry. + * Input: + * pMcastAddr - L2 multicast entry structure + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_L2_FID - Invalid FID . + * RT_ERR_L2_VID - Invalid VID . + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * If the mac has existed in the LUT, it will be deleted. Otherwise, it will return RT_ERR_L2_ENTRY_NOTFOUND. + */ +rtk_api_ret_t rtk_l2_mcastAddr_del(rtk_l2_mcastAddr_t *pMcastAddr) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_mcastAddr_del) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_mcastAddr_del(pMcastAddr); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_ipMcastAddr_add + * Description: + * Add Lut IP multicast entry + * Input: + * pIpMcastAddr - IP Multicast entry + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_L2_INDEXTBL_FULL - hashed index is full of entries. + * RT_ERR_PORT_MASK - Invalid portmask. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * System supports L2 entry with IP multicast DIP/SIP to forward IP multicasting frame as user + * desired. If this function is enabled, then system will be looked up L2 IP multicast entry to + * forward IP multicast frame directly without flooding. + */ +rtk_api_ret_t rtk_l2_ipMcastAddr_add(rtk_l2_ipMcastAddr_t *pIpMcastAddr) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_ipMcastAddr_add) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_ipMcastAddr_add(pIpMcastAddr); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_ipMcastAddr_get + * Description: + * Get LUT IP multicast entry. + * Input: + * pIpMcastAddr - IP Multicast entry + * Output: + * pIpMcastAddr - IP Multicast entry + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get Lut table of IP multicast entry. + */ +rtk_api_ret_t rtk_l2_ipMcastAddr_get(rtk_l2_ipMcastAddr_t *pIpMcastAddr) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_ipMcastAddr_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_ipMcastAddr_get(pIpMcastAddr); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_ipMcastAddr_next_get + * Description: + * Get Next IP Multicast entry. + * Input: + * pAddress - The Address ID + * Output: + * pIpMcastAddr - IP Multicast entry + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * Get the next IP multicast entry after the current entry pointed by pAddress. + * The address of next entry is returned by pAddress. User can use (address + 1) + * as pAddress to call this API again for dumping all IP multicast entries is LUT. + */ +rtk_api_ret_t rtk_l2_ipMcastAddr_next_get(rtk_uint32 *pAddress, rtk_l2_ipMcastAddr_t *pIpMcastAddr) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_ipMcastAddr_next_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_ipMcastAddr_next_get(pAddress, pIpMcastAddr); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_ipMcastAddr_del + * Description: + * Delete a ip multicast address entry from the specified device. + * Input: + * pIpMcastAddr - IP Multicast entry + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can delete a IP multicast address entry from the specified device. + */ +rtk_api_ret_t rtk_l2_ipMcastAddr_del(rtk_l2_ipMcastAddr_t *pIpMcastAddr) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_ipMcastAddr_del) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_ipMcastAddr_del(pIpMcastAddr); + RTK_API_UNLOCK(); + + return retVal; +} + + +/* Function Name: + * rtk_l2_ucastAddr_flush + * Description: + * Flush L2 mac address by type in the specified device (both dynamic and static). + * Input: + * pConfig - flush configuration + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * flushByVid - 1: Flush by VID, 0: Don't flush by VID + * vid - VID (0 ~ 4095) + * flushByFid - 1: Flush by FID, 0: Don't flush by FID + * fid - FID (0 ~ 15) + * flushByPort - 1: Flush by Port, 0: Don't flush by Port + * port - Port ID + * flushByMac - Not Supported + * ucastAddr - Not Supported + * flushStaticAddr - 1: Flush both Static and Dynamic entries, 0: Flush only Dynamic entries + * flushAddrOnAllPorts - 1: Flush VID-matched entries at all ports, 0: Flush VID-matched entries per port. + */ +rtk_api_ret_t rtk_l2_ucastAddr_flush(rtk_l2_flushCfg_t *pConfig) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_ucastAddr_flush) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_ucastAddr_flush(pConfig); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_table_clear + * Description: + * Flush all static & dynamic entries in LUT. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * + */ +rtk_api_ret_t rtk_l2_table_clear(void) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_table_clear) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_table_clear(); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_table_clearStatus_get + * Description: + * Get table clear status + * Input: + * None + * Output: + * pStatus - Clear status, 1:Busy, 0:finish + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * + */ +rtk_api_ret_t rtk_l2_table_clearStatus_get(rtk_l2_clearStatus_t *pStatus) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_table_clearStatus_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_table_clearStatus_get(pStatus); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_flushLinkDownPortAddrEnable_set + * Description: + * Set HW flush linkdown port mac configuration of the specified device. + * Input: + * port - Port id. + * enable - link down flush status + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * The status of flush linkdown port address is as following: + * - DISABLED + * - ENABLED + */ +rtk_api_ret_t rtk_l2_flushLinkDownPortAddrEnable_set(rtk_port_t port, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_flushLinkDownPortAddrEnable_set) + return RT_ERR_DRIVER_NOT_FOUND; + else if (port > RTK_PORT_ID_MAX) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_flushLinkDownPortAddrEnable_set(enable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_flushLinkDownPortAddrEnable_get + * Description: + * Get HW flush linkdown port mac configuration of the specified device. + * Input: + * port - Port id. + * Output: + * pEnable - link down flush status + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The status of flush linkdown port address is as following: + * - DISABLED + * - ENABLED + */ +rtk_api_ret_t rtk_l2_flushLinkDownPortAddrEnable_get(rtk_port_t port, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_flushLinkDownPortAddrEnable_get) + return RT_ERR_DRIVER_NOT_FOUND; + else if (port > RTK_PORT_ID_MAX) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_flushLinkDownPortAddrEnable_get(pEnable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_agingEnable_set + * Description: + * Set L2 LUT aging status per port setting. + * Input: + * port - Port id. + * enable - Aging status + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * This API can be used to set L2 LUT aging status per port. + */ +rtk_api_ret_t rtk_l2_agingEnable_set(rtk_port_t port, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_agingEnable_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_agingEnable_set(port, enable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_agingEnable_get + * Description: + * Get L2 LUT aging status per port setting. + * Input: + * port - Port id. + * Output: + * pEnable - Aging status + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can be used to get L2 LUT aging function per port. + */ +rtk_api_ret_t rtk_l2_agingEnable_get(rtk_port_t port, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_agingEnable_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_agingEnable_get(port, pEnable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_limitLearningCnt_set + * Description: + * Set per-Port auto learning limit number + * Input: + * port - Port id. + * mac_cnt - Auto learning entries limit number + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_LIMITED_L2ENTRY_NUM - Invalid auto learning limit number + * Note: + * The API can set per-port ASIC auto learning limit number from 0(disable learning) + * to 2112. + */ +rtk_api_ret_t rtk_l2_limitLearningCnt_set(rtk_port_t port, rtk_mac_cnt_t mac_cnt) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_limitLearningCnt_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_limitLearningCnt_set(port, mac_cnt); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_limitLearningCnt_get + * Description: + * Get per-Port auto learning limit number + * Input: + * port - Port id. + * Output: + * pMac_cnt - Auto learning entries limit number + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get per-port ASIC auto learning limit number. + */ +rtk_api_ret_t rtk_l2_limitLearningCnt_get(rtk_port_t port, rtk_mac_cnt_t *pMac_cnt) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_limitLearningCnt_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_limitLearningCnt_get(port, pMac_cnt); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_limitSystemLearningCnt_set + * Description: + * Set System auto learning limit number + * Input: + * mac_cnt - Auto learning entries limit number + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_LIMITED_L2ENTRY_NUM - Invalid auto learning limit number + * Note: + * The API can set system ASIC auto learning limit number from 0(disable learning) + * to 2112. + */ +rtk_api_ret_t rtk_l2_limitSystemLearningCnt_set(rtk_mac_cnt_t mac_cnt) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_limitSystemLearningCnt_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_limitSystemLearningCnt_set(mac_cnt); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_limitSystemLearningCnt_get + * Description: + * Get System auto learning limit number + * Input: + * None + * Output: + * pMac_cnt - Auto learning entries limit number + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get system ASIC auto learning limit number. + */ +rtk_api_ret_t rtk_l2_limitSystemLearningCnt_get(rtk_mac_cnt_t *pMac_cnt) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_limitSystemLearningCnt_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_limitSystemLearningCnt_get(pMac_cnt); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_limitLearningCntAction_set + * Description: + * Configure auto learn over limit number action. + * Input: + * port - Port id. + * action - Auto learning entries limit number + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_NOT_ALLOWED - Invalid learn over action + * Note: + * The API can set SA unknown packet action while auto learn limit number is over + * The action symbol as following: + * - LIMIT_LEARN_CNT_ACTION_DROP, + * - LIMIT_LEARN_CNT_ACTION_FORWARD, + * - LIMIT_LEARN_CNT_ACTION_TO_CPU, + */ +rtk_api_ret_t rtk_l2_limitLearningCntAction_set(rtk_port_t port, rtk_l2_limitLearnCntAction_t action) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_limitLearningCntAction_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_limitLearningCntAction_set(port, action); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_limitLearningCntAction_get + * Description: + * Get auto learn over limit number action. + * Input: + * port - Port id. + * Output: + * pAction - Learn over action + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get SA unknown packet action while auto learn limit number is over + * The action symbol as following: + * - LIMIT_LEARN_CNT_ACTION_DROP, + * - LIMIT_LEARN_CNT_ACTION_FORWARD, + * - LIMIT_LEARN_CNT_ACTION_TO_CPU, + */ +rtk_api_ret_t rtk_l2_limitLearningCntAction_get(rtk_port_t port, rtk_l2_limitLearnCntAction_t *pAction) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_limitLearningCntAction_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_limitLearningCntAction_get(port, pAction); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_limitSystemLearningCntAction_set + * Description: + * Configure system auto learn over limit number action. + * Input: + * port - Port id. + * action - Auto learning entries limit number + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_NOT_ALLOWED - Invalid learn over action + * Note: + * The API can set SA unknown packet action while auto learn limit number is over + * The action symbol as following: + * - LIMIT_LEARN_CNT_ACTION_DROP, + * - LIMIT_LEARN_CNT_ACTION_FORWARD, + * - LIMIT_LEARN_CNT_ACTION_TO_CPU, + */ +rtk_api_ret_t rtk_l2_limitSystemLearningCntAction_set(rtk_l2_limitLearnCntAction_t action) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_limitSystemLearningCntAction_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_limitSystemLearningCntAction_set(action); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_limitSystemLearningCntAction_get + * Description: + * Get system auto learn over limit number action. + * Input: + * None. + * Output: + * pAction - Learn over action + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get SA unknown packet action while auto learn limit number is over + * The action symbol as following: + * - LIMIT_LEARN_CNT_ACTION_DROP, + * - LIMIT_LEARN_CNT_ACTION_FORWARD, + * - LIMIT_LEARN_CNT_ACTION_TO_CPU, + */ +rtk_api_ret_t rtk_l2_limitSystemLearningCntAction_get(rtk_l2_limitLearnCntAction_t *pAction) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_limitSystemLearningCntAction_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_limitSystemLearningCntAction_get(pAction); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_limitSystemLearningCntPortMask_set + * Description: + * Configure system auto learn portmask + * Input: + * pPortmask - Port Mask + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Invalid port mask. + * Note: + * + */ +rtk_api_ret_t rtk_l2_limitSystemLearningCntPortMask_set(rtk_portmask_t *pPortmask) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_limitSystemLearningCntPortMask_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_limitSystemLearningCntPortMask_set(pPortmask); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_limitSystemLearningCntPortMask_get + * Description: + * get system auto learn portmask + * Input: + * None + * Output: + * pPortmask - Port Mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Null pointer. + * Note: + * + */ +rtk_api_ret_t rtk_l2_limitSystemLearningCntPortMask_get(rtk_portmask_t *pPortmask) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_limitSystemLearningCntPortMask_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_limitSystemLearningCntPortMask_get(pPortmask); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_learningCnt_get + * Description: + * Get per-Port current auto learning number + * Input: + * port - Port id. + * Output: + * pMac_cnt - ASIC auto learning entries number + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get per-port ASIC auto learning number + */ +rtk_api_ret_t rtk_l2_learningCnt_get(rtk_port_t port, rtk_mac_cnt_t *pMac_cnt) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_learningCnt_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_learningCnt_get(port, pMac_cnt); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_floodPortMask_set + * Description: + * Set flooding portmask + * Input: + * type - flooding type. + * pFlood_portmask - flooding porkmask + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Invalid portmask. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can set the flooding mask. + * The flooding type is as following: + * - FLOOD_UNKNOWNDA + * - FLOOD_UNKNOWNMC + * - FLOOD_BC + */ +rtk_api_ret_t rtk_l2_floodPortMask_set(rtk_l2_flood_type_t floood_type, rtk_portmask_t *pFlood_portmask) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_floodPortMask_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_floodPortMask_set(floood_type, pFlood_portmask); + RTK_API_UNLOCK(); + + return retVal; +} +/* Function Name: + * rtk_l2_floodPortMask_get + * Description: + * Get flooding portmask + * Input: + * type - flooding type. + * Output: + * pFlood_portmask - flooding porkmask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can get the flooding mask. + * The flooding type is as following: + * - FLOOD_UNKNOWNDA + * - FLOOD_UNKNOWNMC + * - FLOOD_BC + */ +rtk_api_ret_t rtk_l2_floodPortMask_get(rtk_l2_flood_type_t floood_type, rtk_portmask_t *pFlood_portmask) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_floodPortMask_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_floodPortMask_get(floood_type, pFlood_portmask); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_localPktPermit_set + * Description: + * Set permittion of frames if source port and destination port are the same. + * Input: + * port - Port id. + * permit - permittion status + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid permit value. + * Note: + * This API is setted to permit frame if its source port is equal to destination port. + */ +rtk_api_ret_t rtk_l2_localPktPermit_set(rtk_port_t port, rtk_enable_t permit) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_localPktPermit_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_localPktPermit_set(port, permit); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_localPktPermit_get + * Description: + * Get permittion of frames if source port and destination port are the same. + * Input: + * port - Port id. + * Output: + * pPermit - permittion status + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API is to get permittion status for frames if its source port is equal to destination port. + */ +rtk_api_ret_t rtk_l2_localPktPermit_get(rtk_port_t port, rtk_enable_t *pPermit) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_localPktPermit_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_localPktPermit_get(port, pPermit); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_aging_set + * Description: + * Set LUT agging out speed + * Input: + * aging_time - Agging out time. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - input out of range. + * Note: + * The API can set LUT agging out period for each entry and the range is from 45s to 458s. + */ +rtk_api_ret_t rtk_l2_aging_set(rtk_l2_age_time_t aging_time) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_aging_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_aging_set(aging_time); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_aging_get + * Description: + * Get LUT agging out time + * Input: + * None + * Output: + * pEnable - Aging status + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get LUT agging out period for each entry. + */ +rtk_api_ret_t rtk_l2_aging_get(rtk_l2_age_time_t *pAging_time) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_aging_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_aging_get(pAging_time); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_ipMcastAddrLookup_set + * Description: + * Set Lut IP multicast lookup function + * Input: + * type - Lookup type for IPMC packet. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * LOOKUP_MAC - Lookup by MAC address + * LOOKUP_IP - Lookup by IP address + * LOOKUP_IP_VID - Lookup by IP address & VLAN ID + */ +rtk_api_ret_t rtk_l2_ipMcastAddrLookup_set(rtk_l2_ipmc_lookup_type_t type) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_ipMcastAddrLookup_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_ipMcastAddrLookup_set(type); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_ipMcastAddrLookup_get + * Description: + * Get Lut IP multicast lookup function + * Input: + * None. + * Output: + * pType - Lookup type for IPMC packet. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * None. + */ +rtk_api_ret_t rtk_l2_ipMcastAddrLookup_get(rtk_l2_ipmc_lookup_type_t *pType) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_ipMcastAddrLookup_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_ipMcastAddrLookup_get(pType); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_ipMcastForwardRouterPort_set + * Description: + * Set IPMC packet forward to rounter port also or not + * Input: + * enabled - 1: Inlcude router port, 0, exclude router port + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * + */ +rtk_api_ret_t rtk_l2_ipMcastForwardRouterPort_set(rtk_enable_t enabled) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_ipMcastForwardRouterPort_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_ipMcastForwardRouterPort_set(enabled); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_ipMcastForwardRouterPort_get + * Description: + * Get IPMC packet forward to rounter port also or not + * Input: + * None. + * Output: + * pEnabled - 1: Inlcude router port, 0, exclude router port + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * + */ +rtk_api_ret_t rtk_l2_ipMcastForwardRouterPort_get(rtk_enable_t *pEnabled) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_ipMcastForwardRouterPort_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_ipMcastForwardRouterPort_get(pEnabled); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_ipMcastGroupEntry_add + * Description: + * Add an IP Multicast entry to group table + * Input: + * ip_addr - IP address + * vid - VLAN ID + * pPortmask - portmask + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_TBL_FULL - Table Full + * Note: + * Add an entry to IP Multicast Group table. + */ +rtk_api_ret_t rtk_l2_ipMcastGroupEntry_add(ipaddr_t ip_addr, rtk_uint32 vid, rtk_portmask_t *pPortmask) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_ipMcastGroupEntry_add) + return RT_ERR_DRIVER_NOT_FOUND; + else if(vid > RTK_VID_MAX) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_ipMcastGroupEntry_add(ip_addr, pPortmask); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_ipMcastGroupEntry_del + * Description: + * Delete an entry from IP Multicast group table + * Input: + * ip_addr - IP address + * vid - VLAN ID + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_TBL_FULL - Table Full + * Note: + * Delete an entry from IP Multicast group table. + */ +rtk_api_ret_t rtk_l2_ipMcastGroupEntry_del(ipaddr_t ip_addr, rtk_uint32 vid) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_ipMcastGroupEntry_del) + return RT_ERR_DRIVER_NOT_FOUND; + else if(vid > RTK_VID_MAX) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_ipMcastGroupEntry_del(ip_addr); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_ipMcastGroupEntry_get + * Description: + * get an entry from IP Multicast group table + * Input: + * ip_addr - IP address + * vid - VLAN ID + * Output: + * pPortmask - member port mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_TBL_FULL - Table Full + * Note: + * Delete an entry from IP Multicast group table. + */ +rtk_api_ret_t rtk_l2_ipMcastGroupEntry_get(ipaddr_t ip_addr, rtk_uint32 vid, rtk_portmask_t *pPortmask) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_ipMcastGroupEntry_get) + return RT_ERR_DRIVER_NOT_FOUND; + else if(vid > RTK_VID_MAX) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_ipMcastGroupEntry_get(ip_addr, pPortmask); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_entry_get + * Description: + * Get LUT unicast entry. + * Input: + * pL2_entry - Index field in the structure. + * Output: + * pL2_entry - other fields such as MAC, port, age... + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_EMPTY_ENTRY - Empty LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API is used to get address by index from 0~2111. + */ +rtk_api_ret_t rtk_l2_entry_get(rtk_l2_addr_table_t *pL2_entry) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_entry_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_entry_get(pL2_entry); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_lookupHitIsolationAction_set + * Description: + * Set action of lookup hit & isolation. + * Input: + * action - The action + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API is used to configure the action of packet which is lookup hit + * in L2 table but the destination port/portmask are not in the port isolation + * group. + */ +rtk_api_ret_t rtk_l2_lookupHitIsolationAction_set(rtk_l2_lookupHitIsolationAction_t action) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_lookupHitIsolationAction_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_lookupHitIsolationAction_set(action); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_lookupHitIsolationAction_get + * Description: + * Get action of lookup hit & isolation. + * Input: + * None. + * Output: + * pAction - The action + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API is used to get the action of packet which is lookup hit + * in L2 table but the destination port/portmask are not in the port isolation + * group. + */ +rtk_api_ret_t rtk_l2_lookupHitIsolationAction_get(rtk_l2_lookupHitIsolationAction_t *pAction) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_lookupHitIsolationAction_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_lookupHitIsolationAction_get(pAction); + RTK_API_UNLOCK(); + + return retVal; +} + + +#if 0 + +/* Function Name: + * rtk_l2_unknownUnicastPktAction_set + * Description: + * Set unknown unicast packet action configuration. + * Input: + * port - ingress port ID for unknown unicast packet + * ucast_action - Unknown unicast action. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid action. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can set unknown unicast packet action configuration. + * The unknown unicast action is as following: + * 0b00:fwd in L2_UNKNOW_UC_FLD_PMSK + * 0b01 drop + * 0b10 trap + * 0b11 flood + + */ +rtk_api_ret_t rtk_l2_unknownUnicastPktAction_set(rtk_port_t port, rtk_uint32 ucast_action) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_unknownUnicastPktAction_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_unknownUnicastPktAction_set(port, ucast_action); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_unknownUnicastPktAction_get + * Description: + * Get unknown unicast packet action configuration. + * Input: + * port - ingress port ID for unknown unicast packet + * Output: + * pUcast_action - Unknown unicast action. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid action. + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * This API can get unknown unicast packet action configuration. + * The unknown unicast action is as following: + * 0b00:fwd in L2_UNKNOW_UC_FLD_PMSK + * 0b01 drop + * 0b10 trap + * 0b11 flood + + */ +rtk_api_ret_t rtk_l2_unknownUnicastPktAction_get(rtk_port_t port, rtk_uint32 *pUcast_action) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_unknownUnicastPktAction_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_unknownUnicastPktAction_get(port, pUcast_action); + RTK_API_UNLOCK(); + + return retVal; +} + + +/* Function Name: + * rtk_l2_unknownMulticastPktAction_set + * Description: + * Set unknown l2 multicast packet action configuration. + * Input: + * port - ingress port ID for unknown unicast packet + * ucast_action - Unknown unicast action. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid action. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can set unknown unicast packet action configuration. + * The unknown unicast action is as following: + * 0b00:fwd in L2_UNKNOW_MC_FLD_PMSK + * 0b01 drop + * 0b10 trap + * 0b11 exclude RMA + + */ +rtk_api_ret_t rtk_l2_unknownMulticastPktAction_set(rtk_port_t port, rtk_uint32 action) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_unknownMulticastPktAction_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_unknownMulticastPktAction_set(port, action); + RTK_API_UNLOCK(); + + return retVal; +} + + +/* Function Name: + * rtk_l2_unknownMulticastPktAction_get + * Description: + * Get unknown l2 multicast packet action configuration. + * Input: + * port - ingress port ID for unknown unicast packet + * ucast_action - Unknown unicast action. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid action. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can set unknown unicast packet action configuration. + * The unknown unicast action is as following: + * 0b00:fwd in L2_UNKNOW_MC_FLD_PMSK + * 0b01 drop + * 0b10 trap + * 0b11 exclude RMA + + */ +rtk_api_ret_t rtk_l2_unknownMulticastPktAction_get(rtk_port_t port, rtk_uint32 action) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_unknownMulticastPktAction_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_unknownMulticastPktAction_set(port, action); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_unknownMulticastPktAction_Set + * Description: + * Set unknown ipv4 multicast packet action configuration. + * Input: + * port - ingress port ID for unknown unicast packet + * ucast_action - Unknown unicast action. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid action. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can set unknown unicast packet action configuration. + * The unknown unicast action is as following: + * 0b00:fwd in L2_UNKNOW_MC_FLD_PMSK + * 0b01 drop + * 0b10 trap + * 0b11 exclude RMA + + */ +rtk_api_ret_t rtk_l2_unknownV4MulticastPktAction_set(rtk_port_t port, rtk_uint32* action) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_unknownMulticastPktAction_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_unknownMulticastPktAction_get(port, action); + RTK_API_UNLOCK(); + + return retVal; +} + + + +#if 0 +/* Function Name: + * rtk_l2_unknownMacPktAction_set + * Description: + * Set unknown source MAC packet action configuration. + * Input: + * ucast_action - Unknown source MAC action. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid action. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can set unknown unicast packet action configuration. + * The unknown unicast action is as following: + * - UCAST_ACTION_FORWARD_PMASK + * - UCAST_ACTION_DROP + * - UCAST_ACTION_TRAP2CPU + */ +rtk_api_ret_t rtk_l2_unknownMacPktAction_set(rtk_uint32 ucast_action) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_unknownMacPktAction_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_unknownMacPktAction_set(ucast_action); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_unknownMacPktAction_get + * Description: + * Get unknown source MAC packet action configuration. + * Input: + * None. + * Output: + * pUcast_action - Unknown source MAC action. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Null Pointer. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * + */ +rtk_api_ret_t rtk_l2_unknownMacPktAction_get(rtk_uint32 *pUcast_action) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_unknownMacPktAction_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_unknownMacPktAction_get(pUcast_action); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_unmatchMacPktAction_set + * Description: + * Set unmatch source MAC packet action configuration. + * Input: + * ucast_action - Unmatch source MAC action. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid action. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can set unknown unicast packet action configuration. + * The unknown unicast action is as following: + * - UCAST_ACTION_FORWARD_PMASK + * - UCAST_ACTION_DROP + * - UCAST_ACTION_TRAP2CPU + */ +rtk_api_ret_t rtk_l2_unmatchMacPktAction_set(rtk_uint32 ucast_action) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_unmatchMacPktAction_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_unmatchMacPktAction_set(ucast_action); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_unmatchMacPktAction_get + * Description: + * Get unmatch source MAC packet action configuration. + * Input: + * None. + * Output: + * pUcast_action - Unmatch source MAC action. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid action. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can set unknown unicast packet action configuration. + * The unknown unicast action is as following: + * - UCAST_ACTION_FORWARD_PMASK + * - UCAST_ACTION_DROP + * - UCAST_ACTION_TRAP2CPU + */ +rtk_api_ret_t rtk_l2_unmatchMacPktAction_get(rtk_uint32 *pUcast_action) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_unmatchMacPktAction_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_unmatchMacPktAction_get(pUcast_action); + RTK_API_UNLOCK(); + + return retVal; +} +#endif + +/* Function Name: + * rtk_l2_unmatchMacMoving_set + * Description: + * Set unmatch source MAC packet moving state. + * Input: + * port - Port ID. + * enable - ENABLED: allow SA moving, DISABLE: don't allow SA moving. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid action. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + */ +rtk_api_ret_t rtk_l2_unmatchMacMoving_set(rtk_port_t port, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_unmatchMacMoving_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_unmatchMacMoving_set(port, enable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_unmatchMacMoving_get + * Description: + * Set unmatch source MAC packet moving state. + * Input: + * port - Port ID. + * Output: + * pEnable - ENABLED: allow SA moving, DISABLE: don't allow SA moving. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid action. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + */ +rtk_api_ret_t rtk_l2_unmatchMacMoving_get(rtk_port_t port, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->l2_unmatchMacMoving_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->l2_unmatchMacMoving_get(port, pEnable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_unknownMcastPktAction_set + * Description: + * Set behavior of unknown multicast + * Input: + * port - Port id. + * type - unknown multicast packet type. + * mcast_action - unknown multicast action. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_NOT_ALLOWED - Invalid action. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * When receives an unknown multicast packet, switch may trap, drop or flood this packet + * (1) The unknown multicast packet type is as following: + * - MCAST_L2 + * - MCAST_IPV4 + * - MCAST_IPV6 + * (2) The unknown multicast action is as following: + * - MCAST_ACTION_FORWARD + * - MCAST_ACTION_DROP + * - MCAST_ACTION_TRAP2CPU + */ +rtk_api_ret_t rtk_l2_unknownMcastPktAction_set(rtk_port_t port, rtk_uint32 type, rtk_uint32 mcast_action) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->trap_unknownMcastPktAction_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->trap_unknownMcastPktAction_set(port, type, mcast_action); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_l2_unknownMcastPktAction_get + * Description: + * Get behavior of unknown multicast + * Input: + * type - unknown multicast packet type. + * Output: + * pMcast_action - unknown multicast action. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_NOT_ALLOWED - Invalid operation. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * When receives an unknown multicast packet, switch may trap, drop or flood this packet + * (1) The unknown multicast packet type is as following: + * - MCAST_L2 + * - MCAST_IPV4 + * - MCAST_IPV6 + * (2) The unknown multicast action is as following: + * - MCAST_ACTION_FORWARD + * - MCAST_ACTION_DROP + * - MCAST_ACTION_TRAP2CPU + */ +rtk_api_ret_t rtk_l2_unknownMcastPktAction_get(rtk_port_t port, rtk_uint32 type, rtk_uint32 *pMcast_action) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->trap_unknownMcastPktAction_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->trap_unknownMcastPktAction_get(port, type, pMcast_action); + RTK_API_UNLOCK(); + + return retVal; +} + + +/* Function Name: + * rtk_trap_portUnknownMacPktAction_set + * Description: + * Set unknown source MAC packet action configuration. + * Input: + * port - Port ID. + * ucast_action - Unknown source MAC action. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid action. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can set unknown unicast packet action configuration. + * The unknown unicast action is as following: + * - UCAST_ACTION_FORWARD_PMASK + * - UCAST_ACTION_DROP + * - UCAST_ACTION_TRAP2CPU + */ +rtk_api_ret_t rtk_trap_portUnknownMacPktAction_set(rtk_port_t port, rtk_trap_ucast_action_t ucast_action) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->trap_portUnknownMacPktAction_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->trap_portUnknownMacPktAction_set(port, ucast_action); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_trap_portUnknownMacPktAction_get + * Description: + * Get unknown source MAC packet action configuration. + * Input: + * port - Port ID. + * Output: + * pUcast_action - Unknown source MAC action. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Null Pointer. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * + */ +rtk_api_ret_t rtk_trap_portUnknownMacPktAction_get(rtk_port_t port, rtk_trap_ucast_action_t *pUcast_action) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->trap_portUnknownMacPktAction_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->trap_portUnknownMacPktAction_get(port, pUcast_action); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_trap_portUnmatchMacPktAction_set + * Description: + * Set unmatch source MAC packet action configuration. + * Input: + * port - Port ID + * ucast_action - Unmatch source MAC action. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid action. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can set unknown unicast packet action configuration. + * The unknown unicast action is as following: + * - UCAST_ACTION_FORWARD_PMASK + * - UCAST_ACTION_DROP + * - UCAST_ACTION_TRAP2CPU + */ +rtk_api_ret_t rtk_trap_portUnmatchMacPktAction_set(rtk_port_t port, rtk_trap_ucast_action_t ucast_action) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->trap_portUnmatchMacPktAction_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->trap_portUnmatchMacPktAction_set(port, ucast_action); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_trap_portUnmatchMacPktAction_get + * Description: + * Get unmatch source MAC packet action configuration. + * Input: + * port - Port ID + * Output: + * pUcast_action - Unmatch source MAC action. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NOT_ALLOWED - Invalid action. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can set unknown unicast packet action configuration. + * The unknown unicast action is as following: + * - UCAST_ACTION_FORWARD_PMASK + * - UCAST_ACTION_DROP + * - UCAST_ACTION_TRAP2CPU + */ +rtk_api_ret_t rtk_trap_portUnmatchMacPktAction_get(rtk_port_t port, rtk_trap_ucast_action_t *pUcast_action) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->trap_portUnmatchMacPktAction_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->trap_portUnmatchMacPktAction_get(port, pUcast_action); + RTK_API_UNLOCK(); + + return retVal; +} + +#endif + + +#endif + diff --git a/sources/uboot-be550/drivers/net/rtl8372/l2.h b/sources/uboot-be550/drivers/net/rtl8372/l2.h new file mode 100755 index 00000000..75b4e890 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/l2.h @@ -0,0 +1,1130 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8367/RTL8367C switch high-level API + * + * Feature : The file includes L2 module high-layer API defination + * + */ + +#ifndef __RTK_API_L2_H__ +#define __RTK_API_L2_H__ + + +/* + * Data Type Declaration + */ +#define RTK_MAX_NUM_OF_LEARN_LIMIT (rtk_switch_maxLutAddrNumber_get()) + +#define RTK_MAC_ADDR_LEN 6 +#define RTK_MAX_LUT_ADDRESS (RTK_MAX_NUM_OF_LEARN_LIMIT) +#define RTK_MAX_LUT_ADDR_ID (RTK_MAX_LUT_ADDRESS - 1) + +typedef rtk_uint32 rtk_l2_age_time_t; + +typedef enum rtk_l2_flood_type_e +{ + FLOOD_UNKNOWNDA = 0, + FLOOD_UNKNOWNL2MC, + FLOOD_UNKNOWNV4MC, + FLOOD_UNKNOWNV6MC, + FLOOD_BC, + FLOOD_END +} rtk_l2_flood_type_t; + +typedef rtk_uint32 rtk_l2_flushItem_t; + +typedef enum rtk_l2_flushType_e +{ + FLUSH_TYPE_BY_PORT = 0, /* physical port */ + FLUSH_TYPE_BY_PORT_VID, /* physical port + VID */ + FLUSH_TYPE_BY_PORT_FID, /* physical port + FID */ + FLUSH_TYPE_END +} rtk_l2_flushType_t; + +typedef struct rtk_l2_flushCfg_s +{ + rtk_enable_t flushByVid; + rtk_vlan_t vid; + rtk_enable_t flushByFid; + rtk_uint32 fid; + rtk_enable_t flushByPort; + rtk_uint32 portmask; + rtk_enable_t flushStaticAddr; + rtk_enable_t flushAddrOnAllPorts; +} rtk_l2_flushCfg_t; + +typedef enum rtk_l2_read_method_e{ + + READMETHOD_MAC = 0, + READMETHOD_ADDRESS, + READMETHOD_NEXT_ADDRESS, + READMETHOD_NEXT_L2UC, + READMETHOD_NEXT_L2MC, + READMETHOD_NEXT_L3MC, + READMETHOD_NEXT_L2L3MC, + READMETHOD_NEXT_L2UCSPA, + READMETHOD_END +}rtk_l2_read_method_t; + +/* l2 limit learning count action */ +typedef enum rtk_l2_limitLearnCntAction_e +{ + LIMIT_LEARN_CNT_ACTION_DROP = 0, + LIMIT_LEARN_CNT_ACTION_FORWARD, + LIMIT_LEARN_CNT_ACTION_TO_CPU, + LIMIT_LEARN_CNT_ACTION_END +} rtk_l2_limitLearnCntAction_t; + +typedef enum rtk_l2_ipmc_lookup_type_e +{ + LOOKUP_MAC = 0, + LOOKUP_IP, + LOOKUP_END +} rtk_l2_ipmc_lookup_type_t; + +/* l2 address table - unicast data structure */ +typedef struct rtk_l2_ucastAddr_s +{ + rtk_mac_t mac; + rtk_uint32 ivl; + rtk_uint32 vid_fid; + rtk_uint32 port; + rtk_uint32 auth; + rtk_uint32 is_static; + rtk_uint32 address; + rtk_uint32 age; +}rtk_l2_ucastAddr_t; + +/* l2 address table - multicast data structure */ +typedef struct rtk_l2_mcastAddr_s +{ + rtk_uint32 vid_fid; + rtk_mac_t mac; + rtk_portmask_t portmask; + rtk_uint32 ivl; + rtk_uint32 igmp_asic; + rtk_uint32 igmp_index; + rtk_uint32 address; +}rtk_l2_mcastAddr_t; + +/* l2 address table - ip multicast data structure */ +typedef struct rtk_l2_ipMcastAddr_s +{ + ipaddr_t dip; + ipaddr_t sip; + rtk_portmask_t portmask; + rtk_uint32 igmp_asic; + rtk_uint32 igmp_index; + rtk_uint32 address; +}rtk_l2_ipMcastAddr_t; + + +typedef struct rtk_l2_addr_table_s +{ + rtk_uint32 index; + ipaddr_t sip; + ipaddr_t dip; + rtk_mac_t mac; + rtk_uint32 auth; + rtk_portmask_t portmask; + rtk_uint32 age; + rtk_uint32 ivl; + rtk_uint32 vid_fid; + rtk_uint32 is_ipmul; + rtk_uint32 is_static; + rtk_uint32 igmp_idx; + rtk_uint32 igmp_asic; + rtk_uint32 srcport; +}rtk_l2_addr_table_t; + +typedef enum rtk_l2_clearStatus_e +{ + L2_CLEAR_STATE_FINISH = 0, + L2_CLEAR_STATE_BUSY, + L2_CLEAR_STATE_END +}rtk_l2_clearStatus_t; + +typedef enum rtk_l2_lookupHitIsolationAction_e +{ + L2_LOOKUPHIT_ISOACTION_NOP = 0, + L2_LOOKUPHIT_ISOACTION_UNKNOWN, + L2_LOOKUPHIT_ISOACTION_END +}rtk_l2_lookupHitIsolationAction_t; + +/* Function Name: + * rtk_l2_init + * Description: + * Initialize l2 module of the specified device. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * Initialize l2 module before calling any l2 APIs. + */ +extern rtk_api_ret_t rtk_l2_init(void); + +/* Function Name: + * rtk_l2_addr_add + * Description: + * Add LUT unicast entry. + * Input: + * pMac - 6 bytes unicast(I/G bit is 0) mac address to be written into LUT. + * pL2_data - Unicast entry parameter + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_L2_FID - Invalid FID . + * RT_ERR_L2_INDEXTBL_FULL - hashed index is full of entries. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * If the unicast mac address already existed in LUT, it will udpate the status of the entry. + * Otherwise, it will find an empty or asic auto learned entry to write. If all the entries + * with the same hash value can't be replaced, ASIC will return a RT_ERR_L2_INDEXTBL_FULL error. + */ +extern rtk_api_ret_t rtk_l2_addr_add(rtk_mac_t *pMac, rtk_l2_ucastAddr_t *pL2_data); + +/* Function Name: + * rtk_l2_addr_get + * Description: + * Get LUT unicast entry. + * Input: + * pMac - 6 bytes unicast(I/G bit is 0) mac address to be written into LUT. + * Output: + * pL2_data - Unicast entry parameter + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_L2_FID - Invalid FID . + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * If the unicast mac address existed in LUT, it will return the port and fid where + * the mac is learned. Otherwise, it will return a RT_ERR_L2_ENTRY_NOTFOUND error. + */ +extern rtk_api_ret_t rtk_l2_addr_get(rtk_mac_t *pMac, rtk_l2_ucastAddr_t *pL2_data); + +/* Function Name: + * rtk_l2_addr_next_get + * Description: + * Get Next LUT unicast entry. + * Input: + * read_method - The reading method. + * port - The port number if the read_metohd is READMETHOD_NEXT_L2UCSPA + * pAddress - The Address ID + * Output: + * pL2_data - Unicast entry parameter + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_L2_FID - Invalid FID . + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * Get the next unicast entry after the current entry pointed by pAddress. + * The address of next entry is returned by pAddress. User can use (address + 1) + * as pAddress to call this API again for dumping all entries is LUT. + */ +extern rtk_api_ret_t rtk_l2_addr_next_get(rtk_l2_read_method_t read_method, rtk_port_t port, rtk_uint32 *pAddress, rtk_l2_ucastAddr_t *pL2_data); + +/* Function Name: + * rtk_l2_addr_del + * Description: + * Delete LUT unicast entry. + * Input: + * pMac - 6 bytes unicast(I/G bit is 0) mac address to be written into LUT. + * fid - Filtering database + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_L2_FID - Invalid FID . + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * If the mac has existed in the LUT, it will be deleted. Otherwise, it will return RT_ERR_L2_ENTRY_NOTFOUND. + */ +extern rtk_api_ret_t rtk_l2_addr_del(rtk_mac_t *pMac, rtk_l2_ucastAddr_t *pL2_data); + +/* Function Name: + * rtk_l2_mcastAddr_add + * Description: + * Add LUT multicast entry. + * Input: + * pMcastAddr - L2 multicast entry structure + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_L2_FID - Invalid FID . + * RT_ERR_L2_VID - Invalid VID . + * RT_ERR_L2_INDEXTBL_FULL - hashed index is full of entries. + * RT_ERR_PORT_MASK - Invalid portmask. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * If the multicast mac address already existed in the LUT, it will udpate the + * port mask of the entry. Otherwise, it will find an empty or asic auto learned + * entry to write. If all the entries with the same hash value can't be replaced, + * ASIC will return a RT_ERR_L2_INDEXTBL_FULL error. + */ +extern rtk_api_ret_t rtk_l2_mcastAddr_add(rtk_l2_mcastAddr_t *pMcastAddr); + +/* Function Name: + * rtk_l2_mcastAddr_get + * Description: + * Get LUT multicast entry. + * Input: + * pMcastAddr - L2 multicast entry structure + * Output: + * pMcastAddr - L2 multicast entry structure + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_L2_FID - Invalid FID . + * RT_ERR_L2_VID - Invalid VID . + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * If the multicast mac address existed in the LUT, it will return the port where + * the mac is learned. Otherwise, it will return a RT_ERR_L2_ENTRY_NOTFOUND error. + */ +extern rtk_api_ret_t rtk_l2_mcastAddr_get(rtk_l2_mcastAddr_t *pMcastAddr); + +/* Function Name: + * rtk_l2_mcastAddr_next_get + * Description: + * Get Next L2 Multicast entry. + * Input: + * pAddress - The Address ID + * Output: + * pMcastAddr - L2 multicast entry structure + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * Get the next L2 multicast entry after the current entry pointed by pAddress. + * The address of next entry is returned by pAddress. User can use (address + 1) + * as pAddress to call this API again for dumping all multicast entries is LUT. + */ +extern rtk_api_ret_t rtk_l2_mcastAddr_next_get(rtk_uint32 *pAddress, rtk_l2_mcastAddr_t *pMcastAddr); + +/* Function Name: + * rtk_l2_mcastAddr_del + * Description: + * Delete LUT multicast entry. + * Input: + * pMcastAddr - L2 multicast entry structure + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_MAC - Invalid MAC address. + * RT_ERR_L2_FID - Invalid FID . + * RT_ERR_L2_VID - Invalid VID . + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * If the mac has existed in the LUT, it will be deleted. Otherwise, it will return RT_ERR_L2_ENTRY_NOTFOUND. + */ +extern rtk_api_ret_t rtk_l2_mcastAddr_del(rtk_l2_mcastAddr_t *pMcastAddr); + +/* Function Name: + * rtk_l2_ipMcastAddr_add + * Description: + * Add Lut IP multicast entry + * Input: + * pIpMcastAddr - IP Multicast entry + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_L2_INDEXTBL_FULL - hashed index is full of entries. + * RT_ERR_PORT_MASK - Invalid portmask. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * System supports L2 entry with IP multicast DIP/SIP to forward IP multicasting frame as user + * desired. If this function is enabled, then system will be looked up L2 IP multicast entry to + * forward IP multicast frame directly without flooding. + */ +extern rtk_api_ret_t rtk_l2_ipMcastAddr_add(rtk_l2_ipMcastAddr_t *pIpMcastAddr); + +/* Function Name: + * rtk_l2_ipMcastAddr_get + * Description: + * Get LUT IP multicast entry. + * Input: + * pIpMcastAddr - IP Multicast entry + * Output: + * pIpMcastAddr - IP Multicast entry + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get Lut table of IP multicast entry. + */ +extern rtk_api_ret_t rtk_l2_ipMcastAddr_get(rtk_l2_ipMcastAddr_t *pIpMcastAddr); + +/* Function Name: + * rtk_l2_ipMcastAddr_next_get + * Description: + * Get Next IP Multicast entry. + * Input: + * pAddress - The Address ID + * Output: + * pIpMcastAddr - IP Multicast entry + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * Get the next IP multicast entry after the current entry pointed by pAddress. + * The address of next entry is returned by pAddress. User can use (address + 1) + * as pAddress to call this API again for dumping all IP multicast entries is LUT. + */ +extern rtk_api_ret_t rtk_l2_ipMcastAddr_next_get(rtk_uint32 *pAddress, rtk_l2_ipMcastAddr_t *pIpMcastAddr); + +/* Function Name: + * rtk_l2_ipMcastAddr_del + * Description: + * Delete a ip multicast address entry from the specified device. + * Input: + * pIpMcastAddr - IP Multicast entry + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can delete a IP multicast address entry from the specified device. + */ +extern rtk_api_ret_t rtk_l2_ipMcastAddr_del(rtk_l2_ipMcastAddr_t *pIpMcastAddr); + + + +/* Function Name: + * rtk_l2_ucastAddr_flush + * Description: + * Flush L2 mac address by type in the specified device (both dynamic and static). + * Input: + * pConfig - flush configuration + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * flushByVid - 1: Flush by VID, 0: Don't flush by VID + * vid - VID (0 ~ 4095) + * flushByFid - 1: Flush by FID, 0: Don't flush by FID + * fid - FID (0 ~ 15) + * flushByPort - 1: Flush by Port, 0: Don't flush by Port + * port - Port ID + * flushByMac - Not Supported + * ucastAddr - Not Supported + * flushStaticAddr - 1: Flush both Static and Dynamic entries, 0: Flush only Dynamic entries + * flushAddrOnAllPorts - 1: Flush VID-matched entries at all ports, 0: Flush VID-matched entries per port. + */ +extern rtk_api_ret_t rtk_l2_ucastAddr_flush(rtk_l2_flushCfg_t *pConfig); + +/* Function Name: + * rtk_l2_table_clear + * Description: + * Flush all static & dynamic entries in LUT. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * + */ +extern rtk_api_ret_t rtk_l2_table_clear(void); + +/* Function Name: + * rtk_l2_table_clearStatus_get + * Description: + * Get table clear status + * Input: + * None + * Output: + * pStatus - Clear status, 1:Busy, 0:finish + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * + */ +extern rtk_api_ret_t rtk_l2_table_clearStatus_get(rtk_l2_clearStatus_t *pStatus); + +/* Function Name: + * rtk_l2_flushLinkDownPortAddrEnable_set + * Description: + * Set HW flush linkdown port mac configuration of the specified device. + * Input: + * port - Port id. + * enable - link down flush status + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * The status of flush linkdown port address is as following: + * - DISABLED + * - ENABLED + */ +extern rtk_api_ret_t rtk_l2_flushLinkDownPortAddrEnable_set(rtk_port_t port, rtk_enable_t enable); + +/* Function Name: + * rtk_l2_flushLinkDownPortAddrEnable_get + * Description: + * Get HW flush linkdown port mac configuration of the specified device. + * Input: + * port - Port id. + * Output: + * pEnable - link down flush status + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The status of flush linkdown port address is as following: + * - DISABLED + * - ENABLED + */ +extern rtk_api_ret_t rtk_l2_flushLinkDownPortAddrEnable_get(rtk_port_t port, rtk_enable_t *pEnable); + +/* Function Name: + * rtk_l2_agingEnable_set + * Description: + * Set L2 LUT aging status per port setting. + * Input: + * port - Port id. + * enable - Aging status + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * This API can be used to set L2 LUT aging status per port. + */ +extern rtk_api_ret_t rtk_l2_agingEnable_set(rtk_port_t port, rtk_enable_t enable); + +/* Function Name: + * rtk_l2_agingEnable_get + * Description: + * Get L2 LUT aging status per port setting. + * Input: + * port - Port id. + * Output: + * pEnable - Aging status + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can be used to get L2 LUT aging function per port. + */ +extern rtk_api_ret_t rtk_l2_agingEnable_get(rtk_port_t port, rtk_enable_t *pEnable); + +/* Function Name: + * rtk_l2_limitLearningCnt_set + * Description: + * Set per-Port auto learning limit number + * Input: + * port - Port id. + * mac_cnt - Auto learning entries limit number + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_LIMITED_L2ENTRY_NUM - Invalid auto learning limit number + * Note: + * The API can set per-port ASIC auto learning limit number from 0(disable learning) + * to 8k. + */ +extern rtk_api_ret_t rtk_l2_limitLearningCnt_set(rtk_port_t port, rtk_mac_cnt_t mac_cnt); + +/* Function Name: + * rtk_l2_limitLearningCnt_get + * Description: + * Get per-Port auto learning limit number + * Input: + * port - Port id. + * Output: + * pMac_cnt - Auto learning entries limit number + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get per-port ASIC auto learning limit number. + */ +extern rtk_api_ret_t rtk_l2_limitLearningCnt_get(rtk_port_t port, rtk_mac_cnt_t *pMac_cnt); + +/* Function Name: + * rtk_l2_limitSystemLearningCnt_set + * Description: + * Set System auto learning limit number + * Input: + * mac_cnt - Auto learning entries limit number + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_LIMITED_L2ENTRY_NUM - Invalid auto learning limit number + * Note: + * The API can set system ASIC auto learning limit number from 0(disable learning) + * to 2112. + */ +extern rtk_api_ret_t rtk_l2_limitSystemLearningCnt_set(rtk_mac_cnt_t mac_cnt); + +/* Function Name: + * rtk_l2_limitSystemLearningCnt_get + * Description: + * Get System auto learning limit number + * Input: + * None + * Output: + * pMac_cnt - Auto learning entries limit number + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get system ASIC auto learning limit number. + */ +extern rtk_api_ret_t rtk_l2_limitSystemLearningCnt_get(rtk_mac_cnt_t *pMac_cnt); + +/* Function Name: + * rtk_l2_limitLearningCntAction_set + * Description: + * Configure auto learn over limit number action. + * Input: + * port - Port id. + * action - Auto learning entries limit number + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_NOT_ALLOWED - Invalid learn over action + * Note: + * The API can set SA unknown packet action while auto learn limit number is over + * The action symbol as following: + * - LIMIT_LEARN_CNT_ACTION_DROP, + * - LIMIT_LEARN_CNT_ACTION_FORWARD, + * - LIMIT_LEARN_CNT_ACTION_TO_CPU, + */ +extern rtk_api_ret_t rtk_l2_limitLearningCntAction_set(rtk_port_t port, rtk_l2_limitLearnCntAction_t action); + +/* Function Name: + * rtk_l2_limitLearningCntAction_get + * Description: + * Get auto learn over limit number action. + * Input: + * port - Port id. + * Output: + * pAction - Learn over action + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get SA unknown packet action while auto learn limit number is over + * The action symbol as following: + * - LIMIT_LEARN_CNT_ACTION_DROP, + * - LIMIT_LEARN_CNT_ACTION_FORWARD, + * - LIMIT_LEARN_CNT_ACTION_TO_CPU, + */ +extern rtk_api_ret_t rtk_l2_limitLearningCntAction_get(rtk_port_t port, rtk_l2_limitLearnCntAction_t *pAction); + +/* Function Name: + * rtk_l2_limitSystemLearningCntAction_set + * Description: + * Configure system auto learn over limit number action. + * Input: + * port - Port id. + * action - Auto learning entries limit number + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_NOT_ALLOWED - Invalid learn over action + * Note: + * The API can set SA unknown packet action while auto learn limit number is over + * The action symbol as following: + * - LIMIT_LEARN_CNT_ACTION_DROP, + * - LIMIT_LEARN_CNT_ACTION_FORWARD, + * - LIMIT_LEARN_CNT_ACTION_TO_CPU, + */ +extern rtk_api_ret_t rtk_l2_limitSystemLearningCntAction_set(rtk_l2_limitLearnCntAction_t action); + +/* Function Name: + * rtk_l2_limitSystemLearningCntAction_get + * Description: + * Get system auto learn over limit number action. + * Input: + * None. + * Output: + * pAction - Learn over action + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get SA unknown packet action while auto learn limit number is over + * The action symbol as following: + * - LIMIT_LEARN_CNT_ACTION_DROP, + * - LIMIT_LEARN_CNT_ACTION_FORWARD, + * - LIMIT_LEARN_CNT_ACTION_TO_CPU, + */ +extern rtk_api_ret_t rtk_l2_limitSystemLearningCntAction_get(rtk_l2_limitLearnCntAction_t *pAction); + +/* Function Name: + * rtk_l2_limitSystemLearningCntPortMask_set + * Description: + * Configure system auto learn portmask + * Input: + * pPortmask - Port Mask + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Invalid port mask. + * Note: + * + */ +extern rtk_api_ret_t rtk_l2_limitSystemLearningCntPortMask_set(rtk_portmask_t *pPortmask); + +/* Function Name: + * rtk_l2_limitSystemLearningCntPortMask_get + * Description: + * get system auto learn portmask + * Input: + * None + * Output: + * pPortmask - Port Mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Null pointer. + * Note: + * + */ +extern rtk_api_ret_t rtk_l2_limitSystemLearningCntPortMask_get(rtk_portmask_t *pPortmask); + +/* Function Name: + * rtk_l2_learningCnt_get + * Description: + * Get per-Port current auto learning number + * Input: + * port - Port id. + * Output: + * pMac_cnt - ASIC auto learning entries number + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get per-port ASIC auto learning number + */ +extern rtk_api_ret_t rtk_l2_learningCnt_get(rtk_port_t port, rtk_mac_cnt_t *pMac_cnt); + +/* Function Name: + * rtk_l2_floodPortMask_set + * Description: + * Set flooding portmask + * Input: + * type - flooding type. + * pFlood_portmask - flooding porkmask + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Invalid portmask. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can set the flooding mask. + * The flooding type is as following: + * - FLOOD_UNKNOWNDA + * - FLOOD_UNKNOWNMC + * - FLOOD_BC + */ +extern rtk_api_ret_t rtk_l2_floodPortMask_set(rtk_l2_flood_type_t floood_type, rtk_portmask_t *pFlood_portmask); + +/* Function Name: + * rtk_l2_floodPortMask_get + * Description: + * Get flooding portmask + * Input: + * type - flooding type. + * Output: + * pFlood_portmask - flooding porkmask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can get the flooding mask. + * The flooding type is as following: + * - FLOOD_UNKNOWNDA + * - FLOOD_UNKNOWNMC + * - FLOOD_BC + */ +extern rtk_api_ret_t rtk_l2_floodPortMask_get(rtk_l2_flood_type_t floood_type, rtk_portmask_t *pFlood_portmask); + +/* Function Name: + * rtk_l2_localPktPermit_set + * Description: + * Set permittion of frames if source port and destination port are the same. + * Input: + * port - Port id. + * permit - permittion status + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid permit value. + * Note: + * This API is setted to permit frame if its source port is equal to destination port. + */ +extern rtk_api_ret_t rtk_l2_localPktPermit_set(rtk_port_t port, rtk_enable_t permit); + +/* Function Name: + * rtk_l2_localPktPermit_get + * Description: + * Get permittion of frames if source port and destination port are the same. + * Input: + * port - Port id. + * Output: + * pPermit - permittion status + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API is to get permittion status for frames if its source port is equal to destination port. + */ +extern rtk_api_ret_t rtk_l2_localPktPermit_get(rtk_port_t port, rtk_enable_t *pPermit); + +/* Function Name: + * rtk_l2_aging_set + * Description: + * Set LUT agging out speed + * Input: + * aging_time - Agging out time. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_OUT_OF_RANGE - input out of range. + * Note: + * The API can set LUT agging out period for each entry and the range is from 14s to 800s. + */ +extern rtk_api_ret_t rtk_l2_aging_set(rtk_l2_age_time_t aging_time); + +/* Function Name: + * rtk_l2_aging_get + * Description: + * Get LUT agging out time + * Input: + * None + * Output: + * pEnable - Aging status + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get LUT agging out period for each entry. + */ +extern rtk_api_ret_t rtk_l2_aging_get(rtk_l2_age_time_t *pAging_time); + +/* Function Name: + * rtk_l2_ipMcastAddrLookup_set + * Description: + * Set Lut IP multicast lookup function + * Input: + * type - Lookup type for IPMC packet. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API can work with rtk_l2_ipMcastAddrLookupException_add. + * If users set the lookup type to DIP, the group in exception table + * will be lookup by DIP+SIP + * If users set the lookup type to DIP+SIP, the group in exception table + * will be lookup by only DIP + */ +extern rtk_api_ret_t rtk_l2_ipMcastAddrLookup_set(rtk_l2_ipmc_lookup_type_t type); + +/* Function Name: + * rtk_l2_ipMcastAddrLookup_get + * Description: + * Get Lut IP multicast lookup function + * Input: + * None. + * Output: + * pType - Lookup type for IPMC packet. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * None. + */ +extern rtk_api_ret_t rtk_l2_ipMcastAddrLookup_get(rtk_l2_ipmc_lookup_type_t *pType); + +/* Function Name: + * rtk_l2_ipMcastForwardRouterPort_set + * Description: + * Set IPMC packet forward to rounter port also or not + * Input: + * enabled - 1: Inlcude router port, 0, exclude router port + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * + */ +extern rtk_api_ret_t rtk_l2_ipMcastForwardRouterPort_set(rtk_enable_t enabled); + +/* Function Name: + * rtk_l2_ipMcastForwardRouterPort_get + * Description: + * Get IPMC packet forward to rounter port also or not + * Input: + * None. + * Output: + * pEnabled - 1: Inlcude router port, 0, exclude router port + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * + */ +extern rtk_api_ret_t rtk_l2_ipMcastForwardRouterPort_get(rtk_enable_t *pEnabled); + +/* Function Name: + * rtk_l2_ipMcastGroupEntry_add + * Description: + * Add an IP Multicast entry to group table + * Input: + * ip_addr - IP address + * vid - VLAN ID + * pPortmask - portmask + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_TBL_FULL - Table Full + * Note: + * Add an entry to IP Multicast Group table. + */ +extern rtk_api_ret_t rtk_l2_ipMcastGroupEntry_add(ipaddr_t ip_addr, rtk_uint32 vid, rtk_portmask_t *pPortmask); + +/* Function Name: + * rtk_l2_ipMcastGroupEntry_del + * Description: + * Delete an entry from IP Multicast group table + * Input: + * ip_addr - IP address + * vid - VLAN ID + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_TBL_FULL - Table Full + * Note: + * Delete an entry from IP Multicast group table. + */ +extern rtk_api_ret_t rtk_l2_ipMcastGroupEntry_del(ipaddr_t ip_addr, rtk_uint32 vid); + +/* Function Name: + * rtk_l2_ipMcastGroupEntry_get + * Description: + * get an entry from IP Multicast group table + * Input: + * ip_addr - IP address + * vid - VLAN ID + * Output: + * pPortmask - member port mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_TBL_FULL - Table Full + * Note: + * Delete an entry from IP Multicast group table. + */ +extern rtk_api_ret_t rtk_l2_ipMcastGroupEntry_get(ipaddr_t ip_addr, rtk_uint32 vid, rtk_portmask_t *pPortmask); + +/* Function Name: + * rtk_l2_entry_get + * Description: + * Get LUT unicast entry. + * Input: + * pL2_entry - Index field in the structure. + * Output: + * pL2_entry - other fields such as MAC, port, age... + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_EMPTY_ENTRY - Empty LUT entry. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API is used to get address by index from 0~2111. + */ +extern rtk_api_ret_t rtk_l2_entry_get(rtk_l2_addr_table_t *pL2_entry); + +/* Function Name: + * rtk_l2_lookupHitIsolationAction_set + * Description: + * Set action of lookup hit & isolation. + * Input: + * action - The action + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API is used to configure the action of packet which is lookup hit + * in L2 table but the destination port/portmask are not in the port isolation + * group. + */ +extern rtk_api_ret_t rtk_l2_lookupHitIsolationAction_set(rtk_l2_lookupHitIsolationAction_t action); + +/* Function Name: + * rtk_l2_lookupHitIsolationAction_get + * Description: + * Get action of lookup hit & isolation. + * Input: + * None. + * Output: + * pAction - The action + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API is used to get the action of packet which is lookup hit + * in L2 table but the destination port/portmask are not in the port isolation + * group. + */ +extern rtk_api_ret_t rtk_l2_lookupHitIsolationAction_get(rtk_l2_lookupHitIsolationAction_t *pAction); + +#endif /* __RTK_API_L2_H__ */ + diff --git a/sources/uboot-be550/drivers/net/rtl8372/led.c b/sources/uboot-be550/drivers/net/rtl8372/led.c new file mode 100755 index 00000000..50bec51e --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/led.c @@ -0,0 +1,203 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8373 + * Feature : Here is a list of all functions and variables in LED module. + * + */ + +#include +#include +#include +#include +#include + + + +/* Function Name: + * rtk_led_blinkRate_set + * Description: + * Set LED blinking rate + * Input: + * blinkRate - blinking rate. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * ASIC support 6 types of LED blinking rates at 32ms, 64ms, 128ms, 256ms, 512ms and 1024ms. + */ +rtk_api_ret_t rtk_led_blinkRate_set(rtk_led_blink_rate_t blinkRate) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->led_blinkRate_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->led_blinkRate_set(blinkRate); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_led_blinkRate_get + * Description: + * Get LED blinking rate at mode 0 to mode 3 + * Input: + * None + * Output: + * pBlinkRate - blinking rate. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * There are 6 types of LED blinking rates at32ms, 64ms, 128ms, 256ms, 512ms and 1024ms. + */ +rtk_api_ret_t rtk_led_blinkRate_get(rtk_led_blink_rate_t *pBlinkRate) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->led_blinkRate_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->led_blinkRate_get(pBlinkRate); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_led_groupConfig_set + * Description: + * Set per group Led to congiuration mode + * Input: + * setid - 4 groups led setting 0 ~ 3 + * ledid - 4 leds, 0 ~ 3 + * pConfig . + * led_2p5g; + * led_two_pair_1g; + * led_1g; + * led_500m; + * led_100m; + * led_10m; + * led_link; + * led_link_flash; + * led_act; + * led_rx; + * led_tx; + * led_col; + * led_duplex; + * led_training; + * led_master; + * led_10g; + * led_two_pair_5g; + * led_5g; + * led_two_pair_2p5g; + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can be used to enable LED per port per group. + */ + +rtk_api_ret_t rtk_led_groupConfig_set(rtk_led_set_t setid, rtk_uint32 ledid, rtk_led_config_t * config) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->led_groupConfig_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->led_groupConfig_set(setid, ledid, config); + RTK_API_UNLOCK(); + + return retVal; +} + + +/* Function Name: + * rtk_led_portSelConfig_set + * Description: + * Set led group connfig for per port + * Input: + * port - port id 0 ~ 8 + * setid - led config group id 0 ~ 3 + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * ASIC support 6 types of LED blinking rates at 32ms, 64ms, 128ms, 256ms, 512ms and 1024ms. + */ +rtk_api_ret_t rtk_led_portSelConfig_set(rtk_port_t port, rtk_led_set_t setid) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->led_portSelConfig_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->led_portSelConfig_set(port, setid); + RTK_API_UNLOCK(); + + return retVal; +} + + +/* Function Name: + * rtk_led_portSelConfig_get + * Description: + * Get led group connfig for per port + * Input: + * port - port id 0 ~ 8 + * setid - led config group id 0 ~ 3 + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * ASIC support 6 types of LED blinking rates at 32ms, 64ms, 128ms, 256ms, 512ms and 1024ms. + */ +rtk_api_ret_t rtk_led_portSelConfig_get(rtk_port_t port, rtk_led_set_t * setid) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->led_portSelConfig_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->led_portSelConfig_get(port, setid); + RTK_API_UNLOCK(); + + return retVal; +} + diff --git a/sources/uboot-be550/drivers/net/rtl8372/led.h b/sources/uboot-be550/drivers/net/rtl8372/led.h new file mode 100755 index 00000000..79c138f1 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/led.h @@ -0,0 +1,207 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8373 switch high-level API + * + * Feature : The file includes LED module high-layer API defination + * + */ + +#ifndef __RTK_API_LED_H__ +#define __RTK_API_LED_H__ + +typedef enum rtk_led_operation_e +{ + LED_OP_SCAN=0, + LED_OP_PARALLEL, + LED_OP_SERIAL, + LED_OP_END, +}rtk_led_operation_t; + + +typedef enum rtk_led_active_e +{ + LED_ACTIVE_HIGH=0, + LED_ACTIVE_LOW, + LED_ACTIVE_END, +}rtk_led_active_t; + + +typedef struct rtk_led_ability_s +{ + rtk_enable_t link_10m; + rtk_enable_t link_100m; + rtk_enable_t link_500m; + rtk_enable_t link_1000m; + rtk_enable_t link_2500m; + rtk_enable_t act_rx; + rtk_enable_t act_tx; +}rtk_led_ability_t; + +typedef enum rtk_led_blink_rate_e +{ + LED_BLINKRATE_32MS=1, + LED_BLINKRATE_64MS, + LED_BLINKRATE_128MS, + LED_BLINKRATE_256MS, + LED_BLINKRATE_512MS, + LED_BLINKRATE_1024MS, + LED_BLINKRATE_END, +}rtk_led_blink_rate_t; + +typedef enum rtk_led_set_e +{ + LED_SET_0 = 0, + LED_SET_1, + LED_SET_2, + LED_SET_3, + LED_SET_END +}rtk_led_set_t; + + +typedef struct rtk_led_config_e +{ + rtk_uint8 led_2p5g; + rtk_uint8 led_two_pair_1g; + rtk_uint8 led_1g; + rtk_uint8 led_500m; + rtk_uint8 led_100m; + rtk_uint8 led_10m; + rtk_uint8 led_link; + rtk_uint8 led_link_flash; + rtk_uint8 led_act; + rtk_uint8 led_rx; + rtk_uint8 led_tx; + rtk_uint8 led_col; + rtk_uint8 led_duplex; + rtk_uint8 led_training; + rtk_uint8 led_master; + rtk_uint8 led_10g; + rtk_uint8 led_two_pair_5g; + rtk_uint8 led_5g; + rtk_uint8 led_two_pair_2p5g; +}rtk_led_config_t; + + +/* Function Name: + * rtk_led_blinkRate_set + * Description: + * Set LED blinking rate + * Input: + * blinkRate - blinking rate. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * ASIC support 6 types of LED blinking rates at 43ms, 84ms, 120ms, 170ms, 340ms and 670ms. + */ +extern rtk_api_ret_t rtk_led_blinkRate_set(rtk_led_blink_rate_t blinkRate); + +/* Function Name: + * rtk_led_blinkRate_get + * Description: + * Get LED blinking rate at mode 0 to mode 3 + * Input: + * None + * Output: + * pBlinkRate - blinking rate. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * There are 6 types of LED blinking rates at 43ms, 84ms, 120ms, 170ms, 340ms and 670ms. + */ +extern rtk_api_ret_t rtk_led_blinkRate_get(rtk_led_blink_rate_t *pBlinkRate); + +/* Function Name: + * rtk_led_groupConfig_set + * Description: + * Set per group Led to congiuration mode + * Input: + * group - LED group. + * config - LED configuration + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can set LED indicated information configuration for each LED group with 1 to 1 led mapping to each port. + * - Definition LED Statuses Description + * - 0000 LED_Off LED pin Tri-State. + * - 0001 Dup/Col Collision, Full duplex Indicator. + * - 0010 Link/Act Link, Activity Indicator. + * - 0011 Spd1000 1000Mb/s Speed Indicator. + * - 0100 Spd100 100Mb/s Speed Indicator. + * - 0101 Spd10 10Mb/s Speed Indicator. + * - 0110 Spd1000/Act 1000Mb/s Speed/Activity Indicator. + * - 0111 Spd100/Act 100Mb/s Speed/Activity Indicator. + * - 1000 Spd10/Act 10Mb/s Speed/Activity Indicator. + * - 1001 Spd100 (10)/Act 10/100Mb/s Speed/Activity Indicator. + * - 1010 LoopDetect LoopDetect Indicator. + * - 1011 EEE EEE Indicator. + * - 1100 Link/Rx Link, Activity Indicator. + * - 1101 Link/Tx Link, Activity Indicator. + * - 1110 Master Link on Master Indicator. + * - 1111 Act Activity Indicator. Low for link established. + */ +extern rtk_api_ret_t rtk_led_groupConfig_set(rtk_led_set_t setid, rtk_uint32 ledid, rtk_led_config_t * config); + +/* Function Name: + * rtk_led_portSelConfig_set + * Description: + * Set led group connfig for per port + * Input: + * port - port id 0 ~ 8 + * setid - led config group id 0 ~ 3 + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * ASIC support 6 types of LED blinking rates at 32ms, 64ms, 128ms, 256ms, 512ms and 1024ms. + */ +extern rtk_api_ret_t rtk_led_portSelConfig_set(rtk_port_t port, rtk_led_set_t setid); + + +/* Function Name: + * rtk_led_portSelConfig_get + * Description: + * Get led group connfig for per port + * Input: + * port - port id 0 ~ 8 + * setid - led config group id 0 ~ 3 + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * ASIC support 6 types of LED blinking rates at 32ms, 64ms, 128ms, 256ms, 512ms and 1024ms. + */ +extern rtk_api_ret_t rtk_led_portSelConfig_get(rtk_port_t port, rtk_led_set_t * setid); + + +#endif /* __RTK_API_LED_H__ */ + diff --git a/sources/uboot-be550/drivers/net/rtl8372/macsec.c b/sources/uboot-be550/drivers/net/rtl8372/macsec.c new file mode 100755 index 00000000..ddf6b13a --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/macsec.c @@ -0,0 +1,1063 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8371c switch high-level API + * + * Feature : The file includes MACsec module high-layer API defination + * + */ + + #include +#include +#include +#include + +#include + +/* Function Name: + * rtk_macsec_enable_set + * Description: + * Configure macsec enable. + * Input: + * port - port id + * ingress_en - ingress enable + * egress_en - egress enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure macsec enable. + */ +rtk_api_ret_t rtk_macsec_enable_set(rtk_uint32 port, rtk_uint32 ingress_en, rtk_uint32 egress_en) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->macsec_enable_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->macsec_enable_set(port, ingress_en, egress_en); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_macsec_enable_get + * Description: + * get macsec enable status. + * Input: + * port - port id + * Output: + * ingress_en - ingress enable + * egress_en - egress enable + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will get macsec enable status. + */ +rtk_api_ret_t rtk_macsec_enable_get(rtk_uint32 port, rtk_uint32 *ingress_en, rtk_uint32 *egress_en) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->macsec_enable_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->macsec_enable_get(port, ingress_en, egress_en); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_macsec_egress_set + * Description: + * Configure macsec egress rule. + * Input: + * port - port id + * addr - macsec ip core register address + * value - data for rule + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure macsec egress rule:SA match rule, flow control register and transform record. + */ +rtk_api_ret_t rtk_macsec_egress_set(rtk_uint32 port, rtk_uint32 addr, rtk_uint32 value) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->macsec_egress_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->macsec_egress_set(port, addr, value); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_macsec_egress_get + * Description: + * get macsec egress rule. + * Input: + * port - port id + * addr - macsec ip core register address + * Output: + * value - data for rule + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will get macsec egress rule:SA match rule, flow control register and transform record. + */ +rtk_api_ret_t rtk_macsec_egress_get(rtk_uint32 port, rtk_uint32 addr, rtk_uint32 *value) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->macsec_egress_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->macsec_egress_get(port, addr, value); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_macsec_ingress_set + * Description: + * Configure macsec ingress rule. + * Input: + * port - port id + * addr - macsec ip core register address + * value - data for rule + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure macsec ingress rule:SA match rule, flow control register and transform record. + */ +rtk_api_ret_t rtk_macsec_ingress_set(rtk_uint32 port, rtk_uint32 addr, rtk_uint32 value) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->macsec_ingress_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->macsec_ingress_set(port, addr, value); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_macsec_ingress_get + * Description: + * get macsec egress rule. + * Input: + * port - port id + * addr - macsec ip core register address + * Output: + * value - data for rule + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will get macsec ingress rule:SA match rule, flow control register and transform record. + */ +rtk_api_ret_t rtk_macsec_ingress_get(rtk_uint32 port, rtk_uint32 addr, rtk_uint32 *value) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->macsec_ingress_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->macsec_ingress_get(port, addr, value); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_macsec_rxgating_set + * Description: + * Configure macsec rx gating value + * Input: + * port - port id + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure macsec rx gating value,before set the packet flow path called this API. + */ +rtk_api_ret_t rtk_macsec_rxgating_set(rtk_uint32 port) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->macsec_rxgating_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->macsec_rxgating_set(port); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_macsec_rxgating_cancel + * Description: + * Configure macsec rx gating value + * Input: + * port - port id + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure macsec rx gating value, called after packet flow path changed. + */ +rtk_api_ret_t rtk_macsec_rxgating_cancel(rtk_uint32 port) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->macsec_rxgating_cancel) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->macsec_rxgating_cancel(port); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_macsec_txgating_set + * Description: + * Configure macsec tx gating value + * Input: + * port - port id + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure macsec tx gating value, before set the packet flow path called this API. + */ +rtk_api_ret_t rtk_macsec_txgating_set(rtk_uint32 port) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->macsec_txgating_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->macsec_txgating_set(port); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_macsec_txgating_cancel + * Description: + * Configure macsec tx gating value + * Input: + * port - port id + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure macsec tx gating value, called after packet flow path changed.. + */ +rtk_api_ret_t rtk_macsec_txgating_cancel(rtk_uint32 port) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->macsec_txgating_cancel) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->macsec_txgating_cancel(port); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_macsec_rxIPbypass_set + * Description: + * Configure macsec bypass MACsec IP function. + * Input: + * port - port id + * enable - enable ip bypass + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure macsec bypass MACsec IP function. + */ +rtk_api_ret_t rtk_macsec_rxIPbypass_set(rtk_uint32 port, rtk_uint32 enable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->macsec_rxIPbypass_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->macsec_rxIPbypass_set(port, enable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_macsec_rxIPbypass_get + * Description: + * get macsec bypass MACsec IP function status. + * Input: + * port - port id + * Output: + * enable - enable ip bypass + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will get macsec bypass MACsec IP function status. + */ +rtk_api_ret_t rtk_macsec_rxIPbypass_get(rtk_uint32 port, rtk_uint32 *enable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->macsec_rxIPbypass_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->macsec_rxIPbypass_get(port, enable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_macsec_txIPbypass_set + * Description: + * Configure macsec bypass MACsec IP function. + * Input: + * port - port id + * enable - enable ip bypass + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure macsec bypass MACsec IP function. + */ +rtk_api_ret_t rtk_macsec_txIPbypass_set(rtk_uint32 port, rtk_uint32 enable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->macsec_txIPbypass_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->macsec_txIPbypass_set(port, enable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_macsec_txIPbypass_get + * Description: + * Configure macsec bypass MACsec IP function. + * Input: + * port - port id + * enable - enable ip bypass + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure macsec bypass MACsec IP function. + */ +rtk_api_ret_t rtk_macsec_txIPbypass_get(rtk_uint32 port, rtk_uint32 *enable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->macsec_txIPbypass_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->macsec_txIPbypass_get(port, enable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_macsec_rxbypass_set + * Description: + * Configure macsec bypass in MACsec IP function. + * Input: + * port - port id + * enable - enable ip bypass + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure macsec bypass in MACsec IP function. + */ +rtk_api_ret_t rtk_macsec_rxbypass_set(rtk_uint32 port, rtk_uint32 enable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->macsec_rxbypass_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->macsec_rxbypass_set(port, enable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_macsec_rxbypass_get + * Description: + * get macsec bypass in MACsec IP function status. + * Input: + * port - port id + * Output: + * enable - enable ip bypass + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will get macsec bypass in MACsec IP function status. + */ +rtk_api_ret_t rtk_macsec_rxbypass_get(rtk_uint32 port, rtk_uint32 *enable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->macsec_rxbypass_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->macsec_rxbypass_get(port, enable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_macsec_txbypass_set + * Description: + * Configure macsec bypass in MACsec IP function. + * Input: + * port - port id + * enable - enable ip bypass + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure macsec bypass in MACsec IP function. + */ +rtk_api_ret_t rtk_macsec_txbypass_set(rtk_uint32 port, rtk_uint32 enable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->macsec_txbypass_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->macsec_txbypass_set(port, enable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_macsec_txbypass_get + * Description: + * get macsec bypass in MACsec IP function status. + * Input: + * port - port id + * Output: + * enable - enable ip bypass + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will get macsec bypass in MACsec IP function status. + */ +rtk_api_ret_t rtk_macsec_txbypass_get(rtk_uint32 port, rtk_uint32 *enable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->macsec_txbypass_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->macsec_txbypass_get(port, enable); + RTK_API_UNLOCK(); + + return retVal; +} + + +/* Function Name: + * rtk_wrapper_int_control_set + * Description: + * Configure MACsec interrupt. + * Input: + * port - port id + * type - interrupt type + * enable - enable interrupt + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure MACsec interrupt. + * The interrupt trigger status is shown in the following: + * - INT_TYPE_TX_IPE_GLB + * - INT_TYPE_TX_IPESECFAIL + * - INT_TYPE_TX_IPELOCK + * - INT_TYPE_TX_IPELOCK_XG + * - INT_TYPE_RX_IPI_GLB + * - INT_TYPE_RX_IPISECFAIL + * - INT_TYPE_RX_IPILOCK + * - INT_TYPE_RX_IPILOCK_XG + */ +rtk_api_ret_t rtk_wrapper_int_control_set(rtk_uint32 port, rtk_macsec_int_type_t type, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->wrapper_int_control_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->wrapper_int_control_set(port, type, enable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_wrapper_int_control_get + * Description: + * gonfigure MACsec interrupt. + * Input: + * port - port id + * type - interrupt type + * Output: + * pEnable - enable interrupt + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will get MACsec interrupt. + * The interrupt trigger status is shown in the following: + * - INT_TYPE_TX_IPE_GLB + * - INT_TYPE_TX_IPESECFAIL + * - INT_TYPE_TX_IPELOCK + * - INT_TYPE_TX_IPELOCK_XG + * - INT_TYPE_RX_IPI_GLB + * - INT_TYPE_RX_IPISECFAIL + * - INT_TYPE_RX_IPILOCK + * - INT_TYPE_RX_IPILOCK_XG + */ +rtk_api_ret_t rtk_wrapper_int_control_get(rtk_uint32 port, rtk_macsec_int_type_t type, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->wrapper_int_control_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->wrapper_int_control_get(port, type, pEnable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_wrapper_int_status_set + * Description: + * Configure MACsec interrupt status. + * Input: + * port - port id + * statusMask - interrupt status mask + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will clean MACsec interrupt status when interrupt happened. + * The interrupt trigger status is shown in the following: + * - INT_TYPE_TX_IPE_GLB [bit[0]] + * - INT_TYPE_TX_IPESECFAIL [bit[1]] + * - INT_TYPE_TX_IPELOCK [bit[2]] + * - INT_TYPE_TX_IPELOCK_XG [bit[3]] + * - INT_TYPE_RX_IPI_GLB [bit[8]] + * - INT_TYPE_RX_IPISECFAIL [bit[9]] + * - INT_TYPE_RX_IPILOCK [bit[10]] + * - INT_TYPE_RX_IPILOCK_XG [bit[11]] + */ +rtk_api_ret_t rtk_wrapper_int_status_set(rtk_uint32 port, rtk_uint32 statusMask) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->wrapper_int_status_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->wrapper_int_status_set(port, statusMask); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_wrapper_int_status_get + * Description: + * Configure MACsec interrupt status. + * Input: + * port - port id + * statusMask - interrupt status mask + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will clean MACsec interrupt status when interrupt happened. + * The interrupt trigger status is shown in the following: + * - INT_TYPE_TX_IPE_GLB [bit[0]] + * - INT_TYPE_TX_IPESECFAIL [bit[1]] + * - INT_TYPE_TX_IPELOCK [bit[2]] + * - INT_TYPE_TX_IPELOCK_XG [bit[3]] + * - INT_TYPE_RX_IPI_GLB [bit[8]] + * - INT_TYPE_RX_IPISECFAIL [bit[9]] + * - INT_TYPE_RX_IPILOCK [bit[10]] + * - INT_TYPE_RX_IPILOCK_XG [bit[11]] + */ +rtk_api_ret_t rtk_wrapper_int_status_get(rtk_uint32 port, rtk_uint32 *pStatusMask) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->wrapper_int_status_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->wrapper_int_status_get(port, pStatusMask); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_wrapper_mib_reset + * Description: + * Configure wrapper mib reset. + * Input: + * port - port id + * reset - reset value + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure wrapper mib reset. + */ +rtk_api_ret_t rtk_wrapper_mib_reset(rtk_uint32 port, rtk_uint32 reset) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->wrapper_mib_reset) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->wrapper_mib_reset(port, reset); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_wrapper_mib_counter + * Description: + * get wrapper mib counters. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will get wrapper mib counters. + */ +rtk_api_ret_t rtk_wrapper_mib_counter(rtk_uint32 port, RTL8373_WRAPPER_MIBCOUNTER mibIdx, rtk_uint64* pCounter) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->wrapper_mib_counter) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->wrapper_mib_counter(port, mibIdx, pCounter); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_macsec_ipg_len_set + * Description: + * mac mode MACsec ipg length set. + * Input: + * port - port number + * length - ipg length + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will set mac mode MACsec ipg length. + */ +rtk_api_ret_t rtk_macsec_ipg_len_set(rtk_uint32 port, rtk_uint32 length) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->macsec_ipg_len_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->macsec_ipg_len_set(port,length); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_macsec_ipg_len_get + * Description: + * mac mode MACsec ipg length get. + * Input: + * port - port number + * Output: + * plength - ipg length + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will get mac mode MACsec ipg length. + */ +rtk_api_ret_t rtk_macsec_ipg_len_get(rtk_uint32 port, rtk_uint32 *plength) +{ + rtk_api_ret_t retVal; + if (NULL == RT_MAPPER->macsec_ipg_len_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->macsec_ipg_len_get(port,plength); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_macsec_ipg_mode_set + * Description: + * mac mode MACsec ipg mode set. + * Input: + * port - port number + * mode - ipg config mode + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will set mac mode MACsec ipg mode. + * mode[1:0]: + 0: don't insert ipg for macsec + 1: insert ipg for macsec according to macsec feedback signal + 2: insert ipg for masec according to ethertype & cfg_macsec_ipg_length + 3: always insert ipg for macsec, length according to cfg_macsec_ipg_length + */ +rtk_api_ret_t rtk_macsec_ipg_mode_set(rtk_uint32 port, rtk_uint32 mode) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->macsec_ipg_mode_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->macsec_ipg_mode_set(port,mode); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_macsec_ipg_mode_get + * Description: + * mac mode MACsec ipg mode get. + * Input: + * port - port number + * Output: + * pmode - ipg config mode + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will get mac mode MACsec ipg mode. + * mode[1:0]: + 0: don't insert ipg for macsec + 1: insert ipg for macsec according to macsec feedback signal + 2: insert ipg for masec according to ethertype & cfg_macsec_ipg_length + 3: always insert ipg for macsec, length according to cfg_macsec_ipg_length + */ +rtk_api_ret_t rtk_macsec_ipg_mode_get(rtk_uint32 port, rtk_uint32 *pmode) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->macsec_ipg_mode_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->macsec_ipg_mode_get(port,pmode); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_macsec_eth_set + * Description: + * mac mode MACsec eth set. + * Input: + * port - port number + * entry - entry number(0-7) + * ethertype - ether type value + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will set mac mode MACsec eth. + */ +rtk_api_ret_t rtk_macsec_eth_set(rtk_uint32 port, rtk_uint32 entry, rtk_uint32 ethertype) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->macsec_eth_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->macsec_eth_set(port, entry, ethertype); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_macsec_eth_get + * Description: + * mac mode MACsec eth get. + * Input: + * port - port number + * entry - entry number(0-7) + * Output: + * pethertype - ether type value + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will get mac mode MACsec eth. + */ +rtk_api_ret_t rtk_macsec_eth_get(rtk_uint32 port, rtk_uint32 entry, rtk_uint32 *pethertype) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->macsec_eth_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->macsec_eth_get(port, entry, pethertype); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * dal_rtl8371c_macsec_init + * Description: + * Initialize MACsec information. + * Input: + * port_mask - port mask, bit[4:7] + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will initialize MACsec information. + */ +rtk_api_ret_t rtk_macsec_init(rtk_uint32 port_mask) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->macsec_init) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->macsec_init(port_mask); + RTK_API_UNLOCK(); + + return retVal; +} + + + + + + + + diff --git a/sources/uboot-be550/drivers/net/rtl8372/macsec.h b/sources/uboot-be550/drivers/net/rtl8372/macsec.h new file mode 100755 index 00000000..c8e37041 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/macsec.h @@ -0,0 +1,726 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8371c switch high-level API + * + * Feature : The file includes MACsec module high-layer API defination + * + */ + +#ifndef __RTK_API_MACSEC_H__ +#define __RTK_API_MACSEC_H__ + +typedef enum rtk_macsec_int_type_e +{ + INT_TYPE_TX_IPE_GLB = 0, + INT_TYPE_TX_IPESECFAIL, + INT_TYPE_TX_IPELOCK, + INT_TYPE_TX_IPELOCK_XG, + INT_TYPE_RX_IPI_GLB, + INT_TYPE_RX_IPISECFAIL, + INT_TYPE_RX_IPILOCK, + INT_TYPE_RX_IPILOCK_XG, + INT_TYPE_MACSEC_END +}rtk_macsec_int_type_t; + +typedef enum RTL8373_WRAPPER_MIBCOUNTER_e +{ + /* TX */ + TXSYS_CRCERR = 0, + TXSYS_PKTERR, + TXSYS_OK, //64bit + TXSYS_GERR = 4, + TXSYS_GLPIERR, + TXLINE_CRCERR = 8, + TXLINE_PKTERR, + TXLINE_OK, //64bit + TXLINE_DROP = 12, + TXLINE_SRTPKT, + TXLINE_GERR, + + /* RX */ + RXLINE_CRCERR = 16, + RXLINE_PKTERR, + RXLINE_OK, //64bit + RXLINE_SHORTPKT = 20, + RXLINE_GERR, + RXLINE_GLPIERR, + RXSYS_CRCERR = 24, + RXSYS_PKTERR, + RXSYS_OK, //64bit + RXSYS_DROP = 28, + RXSYS_DECRYPTSRT, + RXSYS_GERR +}RTL8373_WRAPPER_MIBCOUNTER; + +/* Function Name: + * rtk_macsec_enable_set + * Description: + * Configure macsec enable. + * Input: + * port - port id + * ingress_en - ingress enable + * egress_en - egress enable + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure macsec enable. + */ +extern rtk_api_ret_t rtk_macsec_enable_set(rtk_uint32 port, rtk_uint32 ingress_en, rtk_uint32 egress_en); + +/* Function Name: + * rtk_macsec_enable_get + * Description: + * get macsec enable status. + * Input: + * port - port id + * Output: + * ingress_en - ingress enable + * egress_en - egress enable + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will get macsec enable status. + */ +extern rtk_api_ret_t rtk_macsec_enable_get(rtk_uint32 port, rtk_uint32 *ingress_en, rtk_uint32 *egress_en); + +/* Function Name: + * rtk_macsec_egress_set + * Description: + * Configure macsec egress rule. + * Input: + * port - port id + * addr - macsec ip core register address + * value - data for rule + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure macsec egress rule:SA match rule, flow control register and transform record. + */ +extern rtk_api_ret_t rtk_macsec_egress_set(rtk_uint32 port, rtk_uint32 addr, rtk_uint32 value); + +/* Function Name: + * rtk_macsec_egress_get + * Description: + * get macsec egress rule. + * Input: + * port - port id + * addr - macsec ip core register address + * Output: + * value - data for rule + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will get macsec egress rule:SA match rule, flow control register and transform record. + */ +extern rtk_api_ret_t rtk_macsec_egress_get(rtk_uint32 port, rtk_uint32 addr, rtk_uint32 *value); + +/* Function Name: + * rtk_macsec_ingress_set + * Description: + * Configure macsec ingress rule. + * Input: + * port - port id + * addr - macsec ip core register address + * value - data for rule + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure macsec ingress rule:SA match rule, flow control register and transform record. + */ +extern rtk_api_ret_t rtk_macsec_ingress_set(rtk_uint32 port, rtk_uint32 addr, rtk_uint32 value); + +/* Function Name: + * rtk_macsec_ingress_get + * Description: + * get macsec egress rule. + * Input: + * port - port id + * addr - macsec ip core register address + * Output: + * value - data for rule + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will get macsec ingress rule:SA match rule, flow control register and transform record. + */ +extern rtk_api_ret_t rtk_macsec_ingress_get(rtk_uint32 port, rtk_uint32 addr, rtk_uint32 *value); + +/* Function Name: + * rtk_macsec_rxgating_set + * Description: + * Configure macsec rx gating value + * Input: + * port - port id + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure macsec rx gating value,before set the packet flow path called this API. + */ +extern rtk_api_ret_t rtk_macsec_rxgating_set(rtk_uint32 port); + +/* Function Name: + * rtk_macsec_rxgating_cancel + * Description: + * Configure macsec rx gating value + * Input: + * port - port id + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure macsec rx gating value, called after packet flow path changed. + */ +extern rtk_api_ret_t rtk_macsec_rxgating_cancel(rtk_uint32 port); + +/* Function Name: + * rtk_macsec_txgating_set + * Description: + * Configure macsec tx gating value + * Input: + * port - port id + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure macsec tx gating value, before set the packet flow path called this API. + */ +extern rtk_api_ret_t rtk_macsec_txgating_set(rtk_uint32 port); + +/* Function Name: + * rtk_macsec_txgating_cancel + * Description: + * Configure macsec tx gating value + * Input: + * port - port id + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure macsec tx gating value, called after packet flow path changed.. + */ +extern rtk_api_ret_t rtk_macsec_txgating_cancel(rtk_uint32 port); + +/* Function Name: + * rtk_macsec_rxIPbypass_set + * Description: + * Configure macsec bypass MACsec IP function. + * Input: + * port - port id + * enable - enable ip bypass + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure macsec bypass MACsec IP function. + */ +extern rtk_api_ret_t rtk_macsec_rxIPbypass_set(rtk_uint32 port, rtk_uint32 enable); + +/* Function Name: + * rtk_macsec_rxIPbypass_get + * Description: + * get macsec bypass MACsec IP function status. + * Input: + * port - port id + * Output: + * enable - enable ip bypass + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will get macsec bypass MACsec IP function status. + */ +extern rtk_api_ret_t rtk_macsec_rxIPbypass_get(rtk_uint32 port, rtk_uint32 *enable); + +/* Function Name: + * rtk_macsec_txIPbypass_set + * Description: + * Configure macsec bypass MACsec IP function. + * Input: + * port - port id + * enable - enable ip bypass + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure macsec bypass MACsec IP function. + */ +extern rtk_api_ret_t rtk_macsec_txIPbypass_set(rtk_uint32 port, rtk_uint32 enable); + +/* Function Name: + * rtk_macsec_txIPbypass_get + * Description: + * Configure macsec bypass MACsec IP function. + * Input: + * port - port id + * enable - enable ip bypass + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure macsec bypass MACsec IP function. + */ +extern rtk_api_ret_t rtk_macsec_txIPbypass_get(rtk_uint32 port, rtk_uint32 *enable); + +/* Function Name: + * rtk_macsec_rxbypass_set + * Description: + * Configure macsec bypass in MACsec IP function. + * Input: + * port - port id + * enable - enable ip bypass + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure macsec bypass in MACsec IP function. + */ +extern rtk_api_ret_t rtk_macsec_rxbypass_set(rtk_uint32 port, rtk_uint32 enable); + +/* Function Name: + * rtk_macsec_rxbypass_get + * Description: + * get macsec bypass in MACsec IP function status. + * Input: + * port - port id + * Output: + * enable - enable ip bypass + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will get macsec bypass in MACsec IP function status. + */ +extern rtk_api_ret_t rtk_macsec_rxbypass_get(rtk_uint32 port, rtk_uint32 *enable); + +/* Function Name: + * rtk_macsec_txbypass_set + * Description: + * Configure macsec bypass in MACsec IP function. + * Input: + * port - port id + * enable - enable ip bypass + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure macsec bypass in MACsec IP function. + */ +extern rtk_api_ret_t rtk_macsec_txbypass_set(rtk_uint32 port, rtk_uint32 enable); + +/* Function Name: + * rtk_macsec_txbypass_get + * Description: + * get macsec bypass in MACsec IP function status. + * Input: + * port - port id + * Output: + * enable - enable ip bypass + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will get macsec bypass in MACsec IP function status. + */ +extern rtk_api_ret_t rtk_macsec_txbypass_get(rtk_uint32 port, rtk_uint32 *enable); + +/* Function Name: + * rtk_wrapper_int_control_set + * Description: + * Configure MACsec interrupt. + * Input: + * port - port id + * type - interrupt type + * enable - enable interrupt + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure MACsec interrupt. + * The interrupt trigger status is shown in the following: + * - INT_TYPE_TX_IPE_GLB + * - INT_TYPE_TX_IPESECFAIL + * - INT_TYPE_TX_IPELOCK + * - INT_TYPE_TX_IPELOCK_XG + * - INT_TYPE_RX_IPI_GLB + * - INT_TYPE_RX_IPISECFAIL + * - INT_TYPE_RX_IPILOCK + * - INT_TYPE_RX_IPILOCK_XG + */ +extern rtk_api_ret_t rtk_wrapper_int_control_set(rtk_uint32 port, rtk_macsec_int_type_t type, rtk_enable_t enable); + +/* Function Name: + * rtk_wrapper_int_control_get + * Description: + * gonfigure MACsec interrupt. + * Input: + * port - port id + * type - interrupt type + * Output: + * pEnable - enable interrupt + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will get MACsec interrupt. + * The interrupt trigger status is shown in the following: + * - INT_TYPE_TX_IPE_GLB + * - INT_TYPE_TX_IPESECFAIL + * - INT_TYPE_TX_IPELOCK + * - INT_TYPE_TX_IPELOCK_XG + * - INT_TYPE_RX_IPI_GLB + * - INT_TYPE_RX_IPISECFAIL + * - INT_TYPE_RX_IPILOCK + * - INT_TYPE_RX_IPILOCK_XG + */ +extern rtk_api_ret_t rtk_wrapper_int_control_get(rtk_uint32 port, rtk_macsec_int_type_t type, rtk_enable_t *pEnable); + +/* Function Name: + * rtk_wrapper_int_status_set + * Description: + * Configure MACsec interrupt status. + * Input: + * port - port id + * statusMask - interrupt status mask + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will clean MACsec interrupt status when interrupt happened. + * The interrupt trigger status is shown in the following: + * - INT_TYPE_TX_IPE_GLB [bit[0]] + * - INT_TYPE_TX_IPESECFAIL [bit[1]] + * - INT_TYPE_TX_IPELOCK [bit[2]] + * - INT_TYPE_TX_IPELOCK_XG [bit[3]] + * - INT_TYPE_RX_IPI_GLB [bit[8]] + * - INT_TYPE_RX_IPISECFAIL [bit[9]] + * - INT_TYPE_RX_IPILOCK [bit[10]] + * - INT_TYPE_RX_IPILOCK_XG [bit[11]] + */ +extern rtk_api_ret_t rtk_wrapper_int_status_set(rtk_uint32 port, rtk_uint32 statusMask); + +/* Function Name: + * rtk_wrapper_int_status_get + * Description: + * Configure MACsec interrupt status. + * Input: + * port - port id + * statusMask - interrupt status mask + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will clean MACsec interrupt status when interrupt happened. + * The interrupt trigger status is shown in the following: + * - INT_TYPE_TX_IPE_GLB [bit[0]] + * - INT_TYPE_TX_IPESECFAIL [bit[1]] + * - INT_TYPE_TX_IPELOCK [bit[2]] + * - INT_TYPE_TX_IPELOCK_XG [bit[3]] + * - INT_TYPE_RX_IPI_GLB [bit[8]] + * - INT_TYPE_RX_IPISECFAIL [bit[9]] + * - INT_TYPE_RX_IPILOCK [bit[10]] + * - INT_TYPE_RX_IPILOCK_XG [bit[11]] + */ +extern rtk_api_ret_t rtk_wrapper_int_status_get(rtk_uint32 port, rtk_uint32 *pStatusMask); + +/* Function Name: + * rtk_wrapper_mib_reset + * Description: + * Configure wrapper mib reset. + * Input: + * port - port id + * reset - reset value + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure wrapper mib reset. + */ +extern rtk_api_ret_t rtk_wrapper_mib_reset(rtk_uint32 port, rtk_uint32 reset); + +/* Function Name: + * rtk_wrapper_mib_counter + * Description: + * get wrapper mib counters. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will get wrapper mib counters. + */ +extern rtk_api_ret_t rtk_wrapper_mib_counter(rtk_uint32 port, RTL8373_WRAPPER_MIBCOUNTER mibIdx, rtk_uint64* pCounter); + +/* Function Name: + * rtk_macsec_ipg_len_set + * Description: + * mac mode MACsec ipg length set. + * Input: + * port - port number + * length - ipg length + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will set mac mode MACsec ipg length. + */ +extern rtk_api_ret_t rtk_macsec_ipg_len_set(rtk_uint32 port, rtk_uint32 length); + +/* Function Name: + * rtk_macsec_ipg_len_get + * Description: + * mac mode MACsec ipg length get. + * Input: + * port - port number + * Output: + * plength - ipg length + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will get mac mode MACsec ipg length. + */ +extern rtk_api_ret_t rtk_macsec_ipg_len_get(rtk_uint32 port, rtk_uint32 *plength); + +/* Function Name: + * rtk_macsec_ipg_mode_set + * Description: + * mac mode MACsec ipg mode set. + * Input: + * port - port number + * mode - ipg config mode + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will set mac mode MACsec ipg mode. + * mode[1:0]: + 0: don't insert ipg for macsec + 1: insert ipg for macsec according to macsec feedback signal + 2: insert ipg for masec according to ethertype & cfg_macsec_ipg_length + 3: always insert ipg for macsec, length according to cfg_macsec_ipg_length + */ +extern rtk_api_ret_t rtk_macsec_ipg_mode_set(rtk_uint32 port, rtk_uint32 mode); + +/* Function Name: + * rtk_macsec_ipg_mode_get + * Description: + * mac mode MACsec ipg mode get. + * Input: + * port - port number + * Output: + * pmode - ipg config mode + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will get mac mode MACsec ipg mode. + * mode[1:0]: + 0: don't insert ipg for macsec + 1: insert ipg for macsec according to macsec feedback signal + 2: insert ipg for masec according to ethertype & cfg_macsec_ipg_length + 3: always insert ipg for macsec, length according to cfg_macsec_ipg_length + */ +extern rtk_api_ret_t rtk_macsec_ipg_mode_get(rtk_uint32 port, rtk_uint32 *pmode); + +/* Function Name: + * rtk_macsec_eth_set + * Description: + * mac mode MACsec eth set. + * Input: + * port - port number + * entry - entry number(0-7) + * ethertype - ether type value + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will set mac mode MACsec eth. + */ +extern rtk_api_ret_t rtk_macsec_eth_set(rtk_uint32 port, rtk_uint32 entry, rtk_uint32 ethertype); + +/* Function Name: + * rtk_macsec_eth_get + * Description: + * mac mode MACsec eth get. + * Input: + * port - port number + * entry - entry number(0-7) + * Output: + * pethertype - ether type value + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will get mac mode MACsec eth. + */ +extern rtk_api_ret_t rtk_macsec_eth_get(rtk_uint32 port, rtk_uint32 entry, rtk_uint32 *pethertype); + +/* Function Name: + * dal_rtl8371c_macsec_init + * Description: + * Initialize MACsec information. + * Input: + * port_mask - port mask, bit[4:7] + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will initialize MACsec information. + */ +extern rtk_api_ret_t rtk_macsec_init(rtk_uint32 port_mask); + +#endif + + diff --git a/sources/uboot-be550/drivers/net/rtl8372/mib.c b/sources/uboot-be550/drivers/net/rtl8372/mib.c new file mode 100755 index 00000000..217cd52e --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/mib.c @@ -0,0 +1,183 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8367C + * Feature : Here is a list of all functions and variables in MIB module. + * + */ + +#include +#include +#include +#include + +#include + + +#define MIB_NOT_SUPPORT (0xFFFF) + +/* Function Name: + * rtk_stat_global_reset + * Description: + * Reset global MIB counter. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * Reset MIB counter of ports. API will use global reset while port mask is all-ports. + */ +rtk_api_ret_t rtk_stat_global_reset(void) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->stat_global_reset) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->stat_global_reset(); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_stat_port_reset + * Description: + * Reset per port MIB counter by port. + * Input: + * port - port id. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * + */ +rtk_api_ret_t rtk_stat_port_reset(rtk_port_t port) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->stat_port_reset) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->stat_port_reset(port); + RTK_API_UNLOCK(); + + return retVal; +} + + + + +/* Function Name: + * rtk_stat_port_get + * Description: + * Get per port MIB counter by index + * Input: + * port - port id. + * cntr_idx - port counter index. + * Output: + * pCntr - MIB retrived counter. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * Get per port MIB counter by index definition. + */ +rtk_api_ret_t rtk_stat_port_get(rtk_port_t port, rtk_stat_port_type_t cntr_idx, rtk_stat_counter_t *pCntr) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->stat_port_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->stat_port_get(port, cntr_idx, pCntr); + RTK_API_UNLOCK(); + + return retVal; +} + + + +/* Function Name: + * rtk_stat_lengthMode_set + * Description: + * Set Legnth mode. + * Input: + * txMode - The length counting mode + * rxMode - The length counting mode + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_INPUT - Out of range. + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * + */ +rtk_api_ret_t rtk_stat_lengthMode_set(rtk_stat_lengthMode_t txMode, rtk_stat_lengthMode_t rxMode) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->stat_lengthMode_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->stat_lengthMode_set(txMode, rxMode); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_stat_lengthMode_get + * Description: + * Get Legnth mode. + * Input: + * None. + * Output: + * pTxMode - The length counting mode + * pRxMode - The length counting mode + * Return: + * RT_ERR_OK - OK + * RT_ERR_INPUT - Out of range. + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +rtk_api_ret_t rtk_stat_lengthMode_get(rtk_stat_lengthMode_t *pTxMode, rtk_stat_lengthMode_t *pRxMode) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->stat_lengthMode_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->stat_lengthMode_get(pTxMode, pRxMode); + RTK_API_UNLOCK(); + + return retVal; +} + diff --git a/sources/uboot-be550/drivers/net/rtl8372/mib.h b/sources/uboot-be550/drivers/net/rtl8372/mib.h new file mode 100755 index 00000000..4f014ce5 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/mib.h @@ -0,0 +1,323 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8367/RTL8367C switch high-level API + * + * Feature : The file includes MIB module high-layer API defination + * + */ + +#ifndef __RTK_API_MIB_H__ +#define __RTK_API_MIB_H__ + +/* + * Data Type Declaration + */ +typedef rtk_u_long_t rtk_stat_counter_t; + +/* global statistic counter structure */ +typedef struct rtk_stat_global_cntr_s +{ + rtk_uint64 dot1dTpLearnedEntryDiscards; +}rtk_stat_global_cntr_t; + +typedef enum rtk_stat_global_type_e +{ + DOT1D_TP_LEARNED_ENTRY_DISCARDS_INDEX = 58, + MIB_GLOBAL_CNTR_END +}rtk_stat_global_type_t; + +/* port statistic counter structure */ + + + +typedef enum rtk_logging_counter_mode_e +{ + LOGGING_MODE_32BIT = 0, + LOGGING_MODE_64BIT, + LOGGING_MODE_END +}rtk_logging_counter_mode_t; + +typedef enum rtk_logging_counter_type_e +{ + LOGGING_TYPE_PACKET = 0, + LOGGING_TYPE_BYTE, + LOGGING_TYPE_END +}rtk_logging_counter_type_t; + + +typedef enum rtk_stat_port_type_e{ + + /* RX */ + ifInOctets_H = 0, + ifInOctets_L, + ifOutOctets_H, + ifOutOctets_L, + ifInUcastPkts_H, + ifInUcastPkts_L, + ifInMulticastPkts_H, + ifInMulticastPkts_L, + ifInBroadcastPkts_H, + ifInBroadcastPkts_L, + ifOutUcastPkts_H, + ifOutUcastPkts_L, + ifOutMulticastPkts_H, + ifOutMulticastPkts_L, + ifOutBroadcastPkts_H, + ifOutBroadcastPkts_L, + + ifOutDiscards, + dot1dTpPortInDiscards, + dot3StatsSingleCollisionFrames, + dot3StatMultipleCollisionFrames, + dot3sDeferredTransmissions, + dot3StatsLateCollisions, + dot3StatsExcessiveCollisions, + dot3StatsSymbolErrors, + dot3ControlInUnknownOpcodes, + dot3InPauseFrames, + dot3OutPauseFrames, + etherStatsDropEvents, + tx_etherStatsBroadcastPkts, + tx_etherStatsMulticastPkts, + tx_etherStatsCRCAlignErrors, + rx_etherStatsCRCAlignErrors, + tx_etherStatsUndersizePkts, + rx_etherStatsUndersizePkts, + tx_etherStatsOversizePkts, + rx_etherStatsOversizePkts, + tx_etherStatsFragments, + rx_etherStatsFragments, + tx_etherStatsJabbers, + rx_etherStatsJabbers, + tx_etherStatsCollisions, + tx_etherStatsPkts64Octets, + rx_etherStatsPkts64Octets, + tx_etherStatsPkts65to127Octets, + rx_etherStatsPkts65to127Octets, + tx_etherStatsPkts128to255Octets, + rx_etherStatsPkts128to255Octets, + tx_etherStatsPkts256to511Octets, + rx_etherStatsPkts256to511Octets, + tx_etherStatsPkts512to1023Octets, + rx_etherStatsPkts512to1023Octets, + tx_etherStatsPkts1024to1518Octets, + rx_etherStatsPkts1024to1518Octets, + + rx_etherStatsUndersizedropPkts = 54, + tx_etherStatsPkts1519toMaxOctets, + rx_etherStatsPkts1519toMaxOctets, + tx_etherStatsPktsOverMaxOctets, + rx_etherStatsPktsOverMaxOctets, + tx_etherStatsPktsFlexibleOctetsSET1, + rx_etherStatsPktsFlexibleOctetsSET1, + tx_etherStatsPktsFlexibleOctetsCRCSET1, + rx_etherStatsPktsFlexibleOctetsCRCSET1, + tx_etherStatsPktsFlexibleOctetsSET0, + rx_etherStatsPktsFlexibleOctetsSET0, + tx_etherStatsPktsFlexibleOctetsCRSET0C, + rx_etherStatsPktsFlexibleOctetsCRSET0C, + lengthFieldError, + falseCarrieimes, + underSizeOctets, + framingErrors, + + rxMacDiscards = 72, + rxMacIPGShortDropRT, + + dot1dTpLearnedEntryDiscards = 75, + egrQueue7DropPktRT, + egrQueue6DropPktRT, + egrQueue5DropPktRT, + egrQueue4DropPktRT, + egrQueue3DropPktRT, + egrQueue2DropPktRT, + egrQueue1DropPktRT, + egrQueue0DropPktRT, + egrQueue7OutPktRT, + egrQueue6OutPktRT, + egrQueue5OutPktRT, + egrQueue4OutPktRT, + egrQueue3OutPktRT, + egrQueue2OutPktRT, + egrQueue1OutPktRT, + egrQueue0OutPktRT, + TxGoodCnt_H, + TxGoodCnt_L, + RxGoodCnt_H, + RxGoodCnt_L, + RxErrorCnt, + TxErrorCnt, + TxGoodCnt_phy_H, + TxGoodCnt_phy_L, + RxGoodCnt_phy_H, + RxGoodCnt_phy_L, + RxErrorCnt_phy, + TxErrorCnt_phy, + +}rtk_stat_port_type_t; + + +typedef enum rtk_stat_lengthMode_e +{ + LENGTH_MODE_EXC_TAG = 0, + LENGTH_MODE_INC_TAG, + LENGTH_MODE_END +}rtk_stat_lengthMode_t; + + + +/* Function Name: + * rtk_stat_global_reset + * Description: + * Reset global MIB counter. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * Reset MIB counter of ports. API will use global reset while port mask is all-ports. + */ +extern rtk_api_ret_t rtk_stat_global_reset(void); + +/* Function Name: + * rtk_stat_port_reset + * Description: + * Reset per port MIB counter by port. + * Input: + * port - port id. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * + */ +extern rtk_api_ret_t rtk_stat_port_reset(rtk_port_t port); + +/* Function Name: + * rtk_stat_queueManage_reset + * Description: + * Reset queue manage MIB counter. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * + */ +extern rtk_api_ret_t rtk_stat_queueManage_reset(void); + +/* Function Name: + * rtk_stat_global_get + * Description: + * Get global MIB counter + * Input: + * cntr_idx - global counter index. + * Output: + * pCntr - global counter value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * Get global MIB counter by index definition. + */ +extern rtk_api_ret_t rtk_stat_global_get(rtk_stat_global_type_t cntr_idx, rtk_stat_counter_t *pCntr); + +/* Function Name: + * rtk_stat_global_getAll + * Description: + * Get all global MIB counter + * Input: + * None + * Output: + * pGlobal_cntrs - global counter structure. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * Get all global MIB counter by index definition. + */ +extern rtk_api_ret_t rtk_stat_global_getAll(rtk_stat_global_cntr_t *pGlobal_cntrs); + +/* Function Name: + * rtk_stat_port_get + * Description: + * Get per port MIB counter by index + * Input: + * port - port id. + * cntr_idx - port counter index. + * Output: + * pCntr - MIB retrived counter. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * Get per port MIB counter by index definition. + */ +extern rtk_api_ret_t rtk_stat_port_get(rtk_port_t port, rtk_stat_port_type_t cntr_idx, rtk_stat_counter_t *pCntr); + + + +/* Function Name: + * rtk_stat_lengthMode_set + * Description: + * Set Legnth mode. + * Input: + * txMode - The length counting mode + * rxMode - The length counting mode + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_INPUT - Out of range. + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * + */ +extern rtk_api_ret_t rtk_stat_lengthMode_set(rtk_stat_lengthMode_t txMode, rtk_stat_lengthMode_t rxMode); + +/* Function Name: + * rtk_stat_lengthMode_get + * Description: + * Get Legnth mode. + * Input: + * None. + * Output: + * pTxMode - The length counting mode + * pRxMode - The length counting mode + * Return: + * RT_ERR_OK - OK + * RT_ERR_INPUT - Out of range. + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + */ +extern rtk_api_ret_t rtk_stat_lengthMode_get(rtk_stat_lengthMode_t *pTxMode, rtk_stat_lengthMode_t *pRxMode); + +#endif /* __RTK_API_MIB_H__ */ + diff --git a/sources/uboot-be550/drivers/net/rtl8372/miim.c b/sources/uboot-be550/drivers/net/rtl8372/miim.c new file mode 100755 index 00000000..d102ec45 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/miim.c @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2010 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API + * Feature : Here is a list of all functions and variables in this module. + * + */ + //#include "phydef.h" + #include +#include +#include "miim.h" +#include "ptp.h" +#include "phydef.h" + +#include +/* Function Name: + * phy_ptpRefTime_set + * Description: + * Set the reference time of PHY of the specified port. + * Input: + * timeStamp - reference timestamp value + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * RT_ERR_PORT_NOT_SUPPORTED - This function is not supported by the PHY of this port + * Note: + * None + */ +ret_t phy_ptpRefTime_set( rtk_time_timeStamp_t timeStamp) +{ + rtk_switch_halCtrl_t *pHalCtrl; + ret_t ret=0; + + if ((pHalCtrl = hal_ctrlInfo_get()) == NULL) + return RT_ERR_FAILED; + RTK_API_LOCK(); + ret = (pHalCtrl->pPhy_ctrl->pPhydrv->fPhydrv_ptpRefTime_set(timeStamp)); + RTK_API_UNLOCK(); + return ret; +} + + diff --git a/sources/uboot-be550/drivers/net/rtl8372/miim.h b/sources/uboot-be550/drivers/net/rtl8372/miim.h new file mode 100755 index 00000000..e81c6dac --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/miim.h @@ -0,0 +1,24 @@ +#ifndef __RTK_API_MIIM_H__ +#define __RTK_API_MIIM_H__ + +/* Function Name: + * phy_ptpRefTime_set + * Description: + * Set the reference time of PHY of the specified port. + * Input: + * timeStamp - reference timestamp value + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * RT_ERR_PORT_NOT_SUPPORTED - This function is not supported by the PHY of this port + * Note: + * None + */ +extern ret_t phy_ptpRefTime_set(rtk_time_timeStamp_t timeStamp); + +#endif \ No newline at end of file diff --git a/sources/uboot-be550/drivers/net/rtl8372/mirror.c b/sources/uboot-be550/drivers/net/rtl8372/mirror.c new file mode 100755 index 00000000..2f47e8a7 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/mirror.c @@ -0,0 +1,848 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8373 + * Feature : Here is a list of all functions and variables in Mirror module. + * + */ + +#include +#include +#include +#include +#include + + +/* Function Name: + * rtk_mirror_set_en + * Description: + * enable/disable port mirror set function. + * Input: + * enable - + * Output: + * None + * Return: + * RT_ERR_OK - OK + * Note: + * The API is to enable/disable mirror function + */ +rtk_api_ret_t rtk_mirror_set_en(rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (NULL == RT_MAPPER->mirror_set_en) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->mirror_set_en(enable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_mirror_setStatus_get + * Description: + * get port mirror function state: enable/disable. + * Input: + * None - + * Output: + * pEnable - mirror set enable or not + * Return: + * RT_ERR_OK - OK + * Note: + * The API is to enable/disable mirror function + */ +rtk_api_ret_t rtk_mirror_setStatus_get(rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (NULL == RT_MAPPER->mirror_setStatus_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->mirror_setStatus_get(pEnable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_mirror_portBased_set + * Description: + * Set port mirror function. + * Input: + * mirroring_port - Monitor port. + * pMirrored_rx_portmask - Rx mirror port mask. + * pMirrored_tx_portmask - Tx mirror port mask. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * RT_ERR_PORT_MASK - Invalid portmask. + * Note: + * The API is to set mirror function of source port and mirror port. + * The mirror port can only be set to one port and the TX and RX mirror ports + * should be identical. + */ +rtk_api_ret_t rtk_mirror_portBased_set(rtk_port_mir_set_t *pMirSet) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->mirror_entry_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->mirror_entry_set(pMirSet); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_mirror_portBased_get + * Description: + * Get port mirror function. + * Input: + * None + * Output: + * pMirroring_port - Monitor port. + * pMirrored_rx_portmask - Rx mirror port mask. + * pMirrored_tx_portmask - Tx mirror port mask. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API is to get mirror function of source port and mirror port. + */ +rtk_api_ret_t rtk_mirror_portBased_get(rtk_port_mir_set_t *pMirSet) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->mirror_entry_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->mirror_entry_get(pMirSet); + RTK_API_UNLOCK(); + return retVal; +} + +/* Function Name: + * rtk_mirror_portIso_set + * Description: + * Set mirror port isolation. + * Input: + * enable |Mirror isolation status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid enable input + * Note: + * The API is to set mirror isolation function that prevent normal forwarding packets to miror port. + */ +rtk_api_ret_t rtk_mirror_portIso_set(rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->mirror_portIso_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->mirror_portIso_set(enable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_mirror_portIso_get + * Description: + * Get mirror port isolation. + * Input: + * None + * Output: + * pEnable |Mirror isolation status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API is to get mirror isolation status. + */ +rtk_api_ret_t rtk_mirror_portIso_get(rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->mirror_portIso_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->mirror_portIso_get(pEnable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_mirror_vlanLeaky_set + * Description: + * Set mirror VLAN leaky. + * Input: + * txenable -TX leaky enable. + * rxenable - RX leaky enable. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid enable input + * Note: + * The API is to set mirror VLAN leaky function forwarding packets to miror port. + */ +rtk_api_ret_t rtk_mirror_vlanLeaky_set(rtk_enable_t txenable, rtk_enable_t rxenable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->mirror_vlanLeaky_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->mirror_vlanLeaky_set(txenable, rxenable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_mirror_vlanLeaky_get + * Description: + * Get mirror VLAN leaky. + * Input: + * None + * Output: + * pTxenable - TX leaky enable. + * pRxenable - RX leaky enable. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API is to get mirror VLAN leaky status. + */ +rtk_api_ret_t rtk_mirror_vlanLeaky_get(rtk_enable_t *pTxenable, rtk_enable_t *pRxenable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->mirror_vlanLeaky_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->mirror_vlanLeaky_get(pTxenable, pRxenable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_mirror_isolationLeaky_set + * Description: + * Set mirror Isolation leaky. + * Input: + * txenable -TX leaky enable. + * rxenable - RX leaky enable. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid enable input + * Note: + * The API is to set mirror VLAN leaky function forwarding packets to miror port. + */ +rtk_api_ret_t rtk_mirror_isolationLeaky_set(rtk_enable_t txenable, rtk_enable_t rxenable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->mirror_isolationLeaky_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->mirror_isolationLeaky_set(txenable, rxenable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_mirror_isolationLeaky_get + * Description: + * Get mirror isolation leaky. + * Input: + * None + * Output: + * pTxenable - TX leaky enable. + * pRxenable - RX leaky enable. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API is to get mirror isolation leaky status. + */ +rtk_api_ret_t rtk_mirror_isolationLeaky_get(rtk_enable_t *pTxenable, rtk_enable_t *pRxenable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->mirror_isolationLeaky_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->mirror_isolationLeaky_get(pTxenable, pRxenable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_mirror_keep_set + * Description: + * Set mirror packet format keep. + * Input: + * mode - -mirror keep mode. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid enable input + * Note: + * The API is to set -mirror keep mode. + * The mirror keep mode is as following: + * - MIRROR_FOLLOW_VLAN + * - MIRROR_KEEP_ORIGINAL + * - MIRROR_KEEP_END + */ +rtk_api_ret_t rtk_mirror_keep_set(rtk_mirror_keep_t mode) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->mirror_keep_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->mirror_keep_set(mode); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_mirror_keep_get + * Description: + * Get mirror packet format keep. + * Input: + * None + * Output: + * pMode -mirror keep mode. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API is to get mirror keep mode. + * The mirror keep mode is as following: + * - MIRROR_FOLLOW_VLAN + * - MIRROR_KEEP_ORIGINAL + * - MIRROR_KEEP_END + */ +rtk_api_ret_t rtk_mirror_keep_get(rtk_mirror_keep_t *pMode) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->mirror_keep_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->mirror_keep_get(pMode); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_mirror_override_set + * Description: + * Set port mirror override function. + * Input: + * rxMirror - 1: output mirrored packet, 0: output normal forward packet + * txMirror - 1: output mirrored packet, 0: output normal forward packet + * aclMirror - 1: output mirrored packet, 0: output normal forward packet + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API is to set mirror override function. + * This function control the output format when a port output + * normal forward & mirrored packet at the same time. + */ +rtk_api_ret_t rtk_mirror_override_set(rtk_enable_t rxMirror, rtk_enable_t txMirror, rtk_enable_t aclMirror) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->mirror_override_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->mirror_override_set(rxMirror, txMirror, aclMirror); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_mirror_override_get + * Description: + * Get port mirror override function. + * Input: + * None + * Output: + * pRxMirror - 1: output mirrored packet, 0: output normal forward packet + * pTxMirror - 1: output mirrored packet, 0: output normal forward packet + * pAclMirror - 1: output mirrored packet, 0: output normal forward packet + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Null Pointer + * Note: + * The API is to Get mirror override function. + * This function control the output format when a port output + * normal forward & mirrored packet at the same time. + */ +rtk_api_ret_t rtk_mirror_override_get(rtk_enable_t *pRxMirror, rtk_enable_t *pTxMirror, rtk_enable_t *pAclMirror) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->mirror_override_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->mirror_override_get(pRxMirror, pTxMirror, pAclMirror); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_mirror_sampleRate_set + * Description: + * set port mirror sample rate. + * Input: + * rateVal - + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Null Pointer + * Note: + * The API is to Set mirror sample rate. + */ +rtk_api_ret_t rtk_mirror_sampleRate_set(rtk_uint32 rateVal) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->mirror_sampleRate_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->mirror_sampleRate_set(rateVal); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_mirror_sampleRate_get + * Description: + * get port mirror sample rate. + * Input: + * None - + * Output: + * pRateVal - sample rate value + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Null Pointer + * Note: + * The API is to Set mirror sample rate. + */ +rtk_api_ret_t rtk_mirror_sampleRate_get(rtk_uint32 *pRateVal) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->mirror_sampleRate_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->mirror_sampleRate_get(pRateVal); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_mirror_pktCnt_get + * Description: + * get Total counter for mirror condition satisfied packets + * Input: + * None - + * Output: + * pTotalPktCntr -Total counter for mirror condition satisfied packets + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Null Pointer + * Note: + * The API is to get Total counter for mirror condition satisfied packets + */ +rtk_api_ret_t rtk_mirror_pktCnt_get(rtk_uint32 *pTotalPktCntr) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->mirror_pktCnt_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->mirror_pktCnt_get(pTotalPktCntr); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_mirror_samplePktCnt_get + * Description: + * get Total sample counter for traffic mirror + * Input: + * None - + * Output: + * pSamplePktCntr - Total sample counter for traffic mirror + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Null Pointer + * Note: + * The API is to get Total sample counter for traffic mirror + */ +rtk_api_ret_t rtk_mirror_samplePktCnt_get(rtk_uint32 *pSamplePktCntr) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->mirror_samplePktCnt_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->mirror_samplePktCnt_get(pSamplePktCntr); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_rspan_rxTag_en + * Description: + * set rspan rx tag parser function enable/disable. + * Input: + * enable + * Output: + * None - + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + */ +rtk_api_ret_t rtk_rspan_rxTag_en(rtk_enable_t enable ) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (NULL == RT_MAPPER->rspan_rxTag_en) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rspan_rxTag_en(enable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_rspan_rxTagEnStatus_get + * Description: + * get rspan rx tag enable/disable status. + * Input: + * None + * Output: + * pEnable - + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + */ +rtk_api_ret_t rtk_rspan_rxTagEnStatus_get(rtk_enable_t *pEnable ) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (NULL == RT_MAPPER->rspan_rxTagEnSts_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rspan_rxTagEnSts_get(pEnable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_rspan_tagCtxt_set + * Description: + * set rspan tag context:TPID PRI CFI VID . + * Input: + * pRspanTag - rspan tag context:TPID PRI CFI VID . + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + */ +rtk_api_ret_t rtk_rspan_tagCtxt_set(rtk_rspan_tag_t *pRspanTag) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (NULL == RT_MAPPER->rspan_tagCtxt_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rspan_tagCtxt_set(pRspanTag); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_rspan_tagCtxt_get + * Description: + * set rspan tag context:TPID PRI CFI VID . + * Input: + * None + * Output: + * pRspanTag - rspan tag context:TPID PRI CFI VID . + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + */ + +rtk_api_ret_t rtk_rspan_tagCtxt_get(rtk_rspan_tag_t *pRspanTag) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (NULL == RT_MAPPER->rspan_tagCtxt_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rspan_tagCtxt_get(pRspanTag); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_rspan_tagAdd_set + * Description: + * per tx port set rspan tag added function. + * Input: + * egrPmsk - a portmask that want add rspantag while tx pkt + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + */ +rtk_api_ret_t rtk_rspan_tagAdd_set(rtk_portmask_t egrPmsk) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (NULL == RT_MAPPER->rspan_tagAdd_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rspan_tagAdd_set(egrPmsk); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_rspan_tagAdd_get + * Description: + * get a portmask which ports has enable add rspan tag function. + * Input: + * None + * Output: + * pPmsk - + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + */ +rtk_api_ret_t rtk_rspan_tagAdd_get(rtk_portmask_t *pPmskStatus ) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (NULL == RT_MAPPER->rspan_tagAdd_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rspan_tagAdd_get(pPmskStatus); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_rspan_tagRemove_set + * Description: + * set rspan rx tag remove enable/disable function. + * Input: + * enable - + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + */ +rtk_api_ret_t rtk_rspan_tagRemove_set(rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (NULL == RT_MAPPER->rspan_tagRemove_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rspan_tagRemove_set(enable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_rspan_tagRemove_get + * Description: + * get rspan rx tag remove state. + * Input: + * None + * Output: + * pEnable + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + */ +rtk_api_ret_t rtk_rspan_tagRemove_get(rtk_enable_t *pEnable ) +{ + rtk_api_ret_t retVal; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (NULL == RT_MAPPER->rspan_tagRemove_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rspan_tagRemove_get(pEnable); + RTK_API_UNLOCK(); + + return retVal; +} + diff --git a/sources/uboot-be550/drivers/net/rtl8372/mirror.h b/sources/uboot-be550/drivers/net/rtl8372/mirror.h new file mode 100755 index 00000000..606173c9 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/mirror.h @@ -0,0 +1,534 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8373 switch high-level API + * + * Feature : The file includes Mirror module high-layer API defination + * + */ + +#ifndef __RTK_API_MIRROR_H__ +#define __RTK_API_MIRROR_H__ + +typedef enum rtk_mirror_keep_e +{ + MIRROR_FOLLOW_VLAN = 0, + MIRROR_KEEP_ORIGINAL, + MIRROR_KEEP_END +}rtk_mirror_keep_t; + +typedef enum rtk_mirror_direction_e +{ + TX_DIR = 0, + RX_DIR, + MIRROR_DIR_END +}rtk_mirror_direction_t; + +typedef struct rtk_port_mir_set_s{ +rtk_uint32 mtp_port; +rtk_portmask_t tx_pmsk; +rtk_portmask_t rx_pmsk; +rtk_mirror_direction_t rx_tx_sel; +}rtk_port_mir_set_t; + + +typedef struct rtk_rspan_tag_s{ +rtk_uint32 tpid; +rtk_uint32 pri; +rtk_uint32 cfi; +rtk_uint32 vid; +}rtk_rspan_tag_t; + +/* Function Name: + * rtk_mirror_set_en + * Description: + * enable/disable port mirror set function. + * Input: + * enable - + * Output: + * None + * Return: + * RT_ERR_OK - OK + * Note: + * The API is to enable/disable mirror function + */ +extern rtk_api_ret_t rtk_mirror_set_en(rtk_enable_t enable); + +/* Function Name: + * rtk_mirror_setStatus_get + * Description: + * get port mirror function state: enable/disable. + * Input: + * None - + * Output: + * pEnable - mirror set enable or not + * Return: + * RT_ERR_OK - OK + * Note: + * The API is to enable/disable mirror function + */ +extern rtk_api_ret_t rtk_mirror_setStatus_get(rtk_enable_t *pEnable); + +/* Function Name: + * rtk_mirror_portBased_set + * Description: + * Set port mirror function. + * Input: + * mirroring_port - Monitor port. + * pMirrored_rx_portmask - Rx mirror port mask. + * pMirrored_tx_portmask - Tx mirror port mask. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * RT_ERR_PORT_MASK - Invalid portmask. + * Note: + * The API is to set mirror function of source port and mirror port. + * The mirror port can only be set to one port and the TX and RX mirror ports + * should be identical. + */ +extern rtk_api_ret_t rtk_mirror_portBased_set(rtk_port_mir_set_t *pMirSet); + +/* Function Name: + * rtk_mirror_portBased_get + * Description: + * Get port mirror function. + * Input: + * None + * Output: + * pMirroring_port - Monitor port. + * pMirrored_rx_portmask - Rx mirror port mask. + * pMirrored_tx_portmask - Tx mirror port mask. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API is to get mirror function of source port and mirror port. + */ +extern rtk_api_ret_t rtk_mirror_portBased_get(rtk_port_mir_set_t *pMirSet); + +/* Function Name: + * rtk_mirror_portIso_set + * Description: + * Set mirror port isolation. + * Input: + * enable |Mirror isolation status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid enable input + * Note: + * The API is to set mirror isolation function that prevent normal forwarding packets to miror port. + */ +extern rtk_api_ret_t rtk_mirror_portIso_set(rtk_enable_t enable); + +/* Function Name: + * rtk_mirror_portIso_get + * Description: + * Get mirror port isolation. + * Input: + * None + * Output: + * pEnable |Mirror isolation status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API is to get mirror isolation status. + */ +extern rtk_api_ret_t rtk_mirror_portIso_get(rtk_enable_t *pEnable); + +/* Function Name: + * rtk_mirror_vlanLeaky_set + * Description: + * Set mirror VLAN leaky. + * Input: + * txenable -TX leaky enable. + * rxenable - RX leaky enable. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid enable input + * Note: + * The API is to set mirror VLAN leaky function forwarding packets to miror port. + */ +extern rtk_api_ret_t rtk_mirror_vlanLeaky_set(rtk_enable_t txenable, rtk_enable_t rxenable); + + +/* Function Name: + * rtk_mirror_vlanLeaky_get + * Description: + * Get mirror VLAN leaky. + * Input: + * None + * Output: + * pTxenable - TX leaky enable. + * pRxenable - RX leaky enable. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API is to get mirror VLAN leaky status. + */ +extern rtk_api_ret_t rtk_mirror_vlanLeaky_get(rtk_enable_t *pTxenable, rtk_enable_t *pRxenable); + +/* Function Name: + * rtk_mirror_isolationLeaky_set + * Description: + * Set mirror Isolation leaky. + * Input: + * txenable -TX leaky enable. + * rxenable - RX leaky enable. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid enable input + * Note: + * The API is to set mirror VLAN leaky function forwarding packets to miror port. + */ +extern rtk_api_ret_t rtk_mirror_isolationLeaky_set(rtk_enable_t txenable, rtk_enable_t rxenable); + +/* Function Name: + * rtk_mirror_isolationLeaky_get + * Description: + * Get mirror isolation leaky. + * Input: + * None + * Output: + * pTxenable - TX leaky enable. + * pRxenable - RX leaky enable. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API is to get mirror isolation leaky status. + */ +extern rtk_api_ret_t rtk_mirror_isolationLeaky_get(rtk_enable_t *pTxenable, rtk_enable_t *pRxenable); + +/* Function Name: + * rtk_mirror_keep_set + * Description: + * Set mirror packet format keep. + * Input: + * mode - -mirror keep mode. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid enable input + * Note: + * The API is to set -mirror keep mode. + * The mirror keep mode is as following: + * - MIRROR_FOLLOW_VLAN + * - MIRROR_KEEP_ORIGINAL + * - MIRROR_KEEP_END + */ +extern rtk_api_ret_t rtk_mirror_keep_set(rtk_mirror_keep_t mode); + + +/* Function Name: + * rtk_mirror_keep_get + * Description: + * Get mirror packet format keep. + * Input: + * None + * Output: + * pMode -mirror keep mode. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API is to get mirror keep mode. + * The mirror keep mode is as following: + * - MIRROR_FOLLOW_VLAN + * - MIRROR_KEEP_ORIGINAL + * - MIRROR_KEEP_END + */ +extern rtk_api_ret_t rtk_mirror_keep_get(rtk_mirror_keep_t *pMode); + +/* Function Name: + * rtk_mirror_override_set + * Description: + * Set port mirror override function. + * Input: + * rxMirror - 1: output mirrored packet, 0: output normal forward packet + * txMirror - 1: output mirrored packet, 0: output normal forward packet + * aclMirror - 1: output mirrored packet, 0: output normal forward packet + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API is to set mirror override function. + * This function control the output format when a port output + * normal forward & mirrored packet at the same time. + */ +extern rtk_api_ret_t rtk_mirror_override_set(rtk_enable_t rxMirror, rtk_enable_t txMirror, rtk_enable_t aclMirror); + +/* Function Name: + * rtk_mirror_override_get + * Description: + * Get port mirror override function. + * Input: + * None + * Output: + * pRxMirror - 1: output mirrored packet, 0: output normal forward packet + * pTxMirror - 1: output mirrored packet, 0: output normal forward packet + * pAclMirror - 1: output mirrored packet, 0: output normal forward packet + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Null Pointer + * Note: + * The API is to Get mirror override function. + * This function control the output format when a port output + * normal forward & mirrored packet at the same time. + */ +extern rtk_api_ret_t rtk_mirror_override_get(rtk_enable_t *pRxMirror, rtk_enable_t *pTxMirror, rtk_enable_t *pAclMirror); + +/* Function Name: + * rtk_mirror_sampleRate_set + * Description: + * set port mirror sample rate. + * Input: + * rateVal - + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Null Pointer + * Note: + * The API is to Set mirror sample rate. + */ +extern rtk_api_ret_t rtk_mirror_sampleRate_set(rtk_uint32 rateVal); + +/* Function Name: + * rtk_mirror_sampleRate_get + * Description: + * get port mirror sample rate. + * Input: + * None - + * Output: + * pRateVal - sample rate value + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Null Pointer + * Note: + * The API is to Set mirror sample rate. + */ +extern rtk_api_ret_t rtk_mirror_sampleRate_get(rtk_uint32 *pRateVal); + +/* Function Name: + * rtk_mirror_pktCnt_get + * Description: + * get Total counter for mirror condition satisfied packets + * Input: + * None - + * Output: + * pTotalPktCntr -Total counter for mirror condition satisfied packets + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Null Pointer + * Note: + * The API is to get Total counter for mirror condition satisfied packets + */ +extern rtk_api_ret_t rtk_mirror_pktCnt_get(rtk_uint32 *pTotalPktCntr); + +/* Function Name: + * rtk_mirror_samplePktCnt_get + * Description: + * get Total sample counter for traffic mirror + * Input: + * None - + * Output: + * pSamplePktCntr - Total sample counter for traffic mirror + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Null Pointer + * Note: + * The API is to get Total sample counter for traffic mirror + */ +extern rtk_api_ret_t rtk_mirror_samplePktCnt_get(rtk_uint32 *pSamplePktCntr); + +/* Function Name: + * rtk_rspan_rxTag_en + * Description: + * set rspan rx tag parser function enable/disable. + * Input: + * None + * Output: + * enable - . + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + */ +extern rtk_api_ret_t rtk_rspan_rxTag_en(rtk_enable_t enable ); + +/* Function Name: + * rtk_rspan_rxTagEnStatus_get + * Description: + * get rspan rx tag enable/disable status. + * Input: + * None + * Output: + * pEnable - + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + */ +extern rtk_api_ret_t rtk_rspan_rxTagEnStatus_get(rtk_enable_t *pEnable ); + +/* Function Name: + * rtk_rspan_tagCtxt_set + * Description: + * set rspan tag context:TPID PRI CFI VID . + * Input: + * pRspanTag - rspan tag context:TPID PRI CFI VID . + * Output: + * None -mirror keep mode. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + */ +extern rtk_api_ret_t rtk_rspan_tagCtxt_set(rtk_rspan_tag_t *pRspanTag ); + +/* Function Name: + * rtk_rspan_tagCtxt_get + * Description: + * set rspan tag context:TPID PRI CFI VID . + * Input: + * None + * Output: + * pRspanTag - rspan tag context:TPID PRI CFI VID . + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + */ + +extern rtk_api_ret_t rtk_rspan_tagCtxt_get(rtk_rspan_tag_t *pRspanTag ); + +/* Function Name: + * rtk_rspan_tagAdd_set + * Description: + * per tx port set rspan tag added function. + * Input: + * egrPmsk - a portmask that want add rspantag while tx pkt + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + */ +extern rtk_api_ret_t rtk_rspan_tagAdd_set(rtk_portmask_t egrPmsk); + +/* Function Name: + * rtk_rspan_tagAdd_get + * Description: + * get a portmask which ports has enable add rspan tag function. + * Input: + * None + * Output: + * pPmskStatus - + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + */ +extern rtk_api_ret_t rtk_rspan_tagAdd_get(rtk_portmask_t *pPmskStatus); + +/* Function Name: + * rtk_rspan_tagRemove_set + * Description: + * set rspan rx tag remove enable/disable function. + * Input: + * enable - + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + */ +extern rtk_api_ret_t rtk_rspan_tagRemove_set(rtk_enable_t enable); + +/* Function Name: + * rtk_rspan_tagRemove_get + * Description: + * get rspan rx tag remove state. + * Input: + * None + * Output: + * pEnable + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + */ +extern rtk_api_ret_t rtk_rspan_tagRemove_get(rtk_enable_t *pEnable ); + +#endif /* __RTK_API_MIRROR_H__ */ + diff --git a/sources/uboot-be550/drivers/net/rtl8372/nic.c b/sources/uboot-be550/drivers/net/rtl8372/nic.c new file mode 100755 index 00000000..1e5dc2e0 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/nic.c @@ -0,0 +1,1293 @@ +/******************************************************************************* +* Copyright (C), 2013, Realtek Semiconductor Corp. +* All Rights Reserved. +* +* This program is the proprietary software of Realtek Semiconductor +* Corporation and/or its licensors, and only be used, duplicated, +* modified or distributed under the authorized license from Realtek. +* +* ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER +* THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. +* +* File Name: +* Author : Cynthia_wang +* Version : +* Date : 2020-9-24 +* Purpose : RTL8373 switch high-level API for RTL8373 +* Feature : Here is a list of all functions and variables in NIC module +* Note: +*******************************************************************************/ + +#include +#include +#include + +#include + +#include + + +/* Function Name: + * rtk_nic_rst_set + * Description: + * nic reset + * Input: + * enabled - enable or disable + * Output: + * none + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_ENABLE + * Note: + * nic reset + */ +rtk_api_ret_t rtk_nic_rst_set(void) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->nic_rst_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->nic_rst_set(); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_nic_txstop_set + * Description: + * Set rtk nic buffer tx stop address + * Input: + * addr - txstop address + * Output: + * none + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_ENABLE + * Note: + * + */ +rtk_api_ret_t rtk_nic_txstop_set( rtk_uint32 addr) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->nic_txStopAddr_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->nic_txStopAddr_set(addr); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_nic_txstop_get + * Description: + * Get rtk nic buffer tx stop address + * Input: + * none + * Output: + * pAddr - the pointer of address + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NULL_POINTER + * Note: + * + */ +rtk_api_ret_t rtk_nic_txstop_get(rtk_uint32 *pAddr) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->nic_txStopAddr_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->nic_txStopAddr_get(pAddr); + RTK_API_UNLOCK(); + + return retVal; +} + + +/* Function Name: + * rtk_nic_rxstop_set + * Description: + * Set rtk nic buffer rx stop address + * Input: + * addr - rxstop address + * Output: + * none + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_ENABLE + * Note: + * + */ +rtk_api_ret_t rtk_nic_rxstop_set( rtk_uint32 addr) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->nic_rxStopAddr_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->nic_rxStopAddr_set(addr); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_nic_rxstop_get + * Description: + * Get rtk nic buffer rx stop address + * Input: + * none + * Output: + * pAddr - the pointer of address + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NULL_POINTER + * Note: + * + */ +rtk_api_ret_t rtk_nic_rxstop_get(rtk_uint32 *pAddr) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->nic_rxStopAddr_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->nic_rxStopAddr_get(pAddr); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_nic_swRxCurPktAddr_get + * Description: + * Get Switch Rx current packet address + * Input: + * none + * Output: + * pAddr - the pointer of address + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NULL_POINTER + * Note: + * + */ +rtk_api_ret_t rtk_nic_swRxCurPktAddr_get(rtk_uint32 *pAddr) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->nic_swRxCurPktAddr_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->nic_swRxCurPktAddr_get(pAddr); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_nic_rxDataLength_get + * Description: + * Get nic rx buffer received packet length + * Input: + * none + * Output: + * pLength - rx buffer received packet length + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NULL_POINTER + * Note: + * + */ +rtk_api_ret_t rtk_nic_rxReceivedPktLen_get(rtk_uint32 *pLength) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->nic_rxReceivedPktLen_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->nic_rxReceivedPktLen_get(pLength); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_nic_txAvailableSpace_get + * Description: + * Get nic tx buffer available free space + * Input: + * none + * Output: + * pAddr - the pointer of address + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NULL_POINTER + * Note: + * + */ +rtk_api_ret_t rtk_nic_txAvailSpace_get(rtk_uint32 *pLength) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->nic_txAvailSpace_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->nic_txAvailSpace_get(pLength); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_nic_moduleEn_set + * Description: + * Enable/Disable NIC module . + * Input: + * none + * Output: + * pStatus - nic status + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_CHIP_NOT_FOUND + * RT_ERR_NOT_INIT - The module is not initial + * Applicable: + * + * Note: + * None + */ +rtk_api_ret_t rtk_nic_moduleEn_set(rtk_enable_t enable) +{ + rtk_api_ret_t retVal ; + + if (NULL == RT_MAPPER->nic_moduleEn_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->nic_moduleEn_set(enable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_nic_moduleEn_get + * Description: + * Get NIC module status . + * Input: + * none + * Output: + * pStatus - nic module status + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_CHIP_NOT_FOUND + * RT_ERR_NOT_INIT - The module is not initial + * Applicable: + * + * Note: + * None + */ +rtk_api_ret_t rtk_nic_moduleEn_get(rtk_enable_t *pStatus) +{ + rtk_api_ret_t retVal ; + + if (NULL == RT_MAPPER->nic_moduleEn_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->nic_moduleEn_get(pStatus); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_nic_rxEn_set + * Description: + * Set NIC rx status . + * Input: + * none + * Output: + * pStatus - rx status + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_CHIP_NOT_FOUND + * RT_ERR_NOT_INIT - The module is not initial + * Applicable: + * + * Note: + * None + */ +rtk_api_ret_t rtk_nic_rxEn_set(rtk_enable_t enable) +{ + rtk_api_ret_t retVal ; + + if (NULL == RT_MAPPER->nic_rxEn_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->nic_rxEn_set(enable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_nic_rx_en_get + * Description: + * Get NIC rx status . + * Input: + * none + * Output: + * pStatus - rx status + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_CHIP_NOT_FOUND + * RT_ERR_NOT_INIT - The module is not initial + * Applicable: + * + * Note: + * None + */ +rtk_api_ret_t rtk_nic_rxEn_get(rtk_enable_t *pStatus) +{ + rtk_api_ret_t retVal ; + + if (NULL == RT_MAPPER->nic_rxEn_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->nic_rxEn_get(pStatus); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_nic_txEn_set + * Description: + * Set NIC tx status . + * Input: + * none + * Output: + * pStatus - tx status + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_CHIP_NOT_FOUND + * RT_ERR_NOT_INIT - The module is not initial + * Applicable: + * + * Note: + * None + */ +rtk_api_ret_t rtk_nic_txEn_set(rtk_enable_t enable) +{ + rtk_api_ret_t retVal ; + + + if (NULL == RT_MAPPER->nic_txEn_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->nic_txEn_set(enable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_nic_tx_en_get + * Description: + * Get NIC tx status . + * Input: + * none + * Output: + * pStatus - tx status + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_CHIP_NOT_FOUND + * RT_ERR_NOT_INIT - The module is not initial + * Applicable: + * + * Note: + * None + */ +rtk_api_ret_t rtk_nic_txEn_get(rtk_enable_t *pStatus) +{ + rtk_uint32 retVal ; + + if (NULL == RT_MAPPER->nic_txEn_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->nic_txEn_get(pStatus); + RTK_API_UNLOCK(); + + return retVal; +} + + +/* Function Name: + * rtk_nic_rxRemoveCrc_set + * Description: + * enable rx remove crc or not. + * Input: + * enabled - enable or disable - + * Output: + * none + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI + * + * Note: + * + */ +rtk_api_ret_t rtk_nic_rxRemoveCrc_set(rtk_enable_t enabled) +{ + rtk_uint32 retVal ; + + if (NULL == RT_MAPPER->nic_rxRemoveCrc_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->nic_rxRemoveCrc_set(enabled); + RTK_API_UNLOCK(); + + return retVal; +} + +rtk_api_ret_t rtk_nic_rxRemoveCrc_get(rtk_enable_t *pEnabled) +{ + rtk_uint32 retVal ; + + if (NULL == RT_MAPPER->nic_rxRemoveCrc_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->nic_rxRemoveCrc_get(pEnabled); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_nic_rxPaddingEn_set + * Description: + * Setting Nic rx padding control + * Input: + * enabled - enable or disable - + * Output: + * none + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI + * + * Note: + * + */ +rtk_api_ret_t rtk_nic_rxPaddingEn_set(rtk_enable_t enabled) +{ + rtk_uint32 retVal ; + + if (NULL == RT_MAPPER->nic_rxPaddingEn_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->nic_rxPaddingEn_set(enabled); + RTK_API_UNLOCK(); + + return retVal; +} + +rtk_api_ret_t rtk_nic_rxPaddingEn_get(rtk_enable_t *pEnabled) +{ + rtk_uint32 retVal ; + + if (NULL == RT_MAPPER->nic_rxPaddingEn_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->nic_rxPaddingEn_get(pEnabled); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_nic_rxFreeSpaceThd_set + * Description: + * Setting Nic rx buffer free space threshold. + * Input: + * val - free space threshold(uint: 8Byte) - + * Output: + * none + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI + * + * Note: + * + */ +rtk_api_ret_t rtk_nic_rxFreeSpaceThd_set(rtk_uint32 val) +{ + rtk_uint32 retVal ; + + if (NULL == RT_MAPPER->nic_rxFreeSpaceThd_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->nic_rxFreeSpaceThd_set(val); + RTK_API_UNLOCK(); + + return retVal; +} + +rtk_api_ret_t rtk_nic_rxFreeSpaceThd_get(rtk_uint32 *pVal) +{ + rtk_uint32 retVal ; + + if (NULL == RT_MAPPER->nic_rxFreeSpaceThd_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->nic_rxFreeSpaceThd_get(pVal); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: +* rtk_nic_rxCrcErrEn_set +* Description: +* enable rx crc error pkt or not. +* Input: +* enabled - enable or disable - +* Output: +* none +* Return: +* RT_ERR_OK +* RT_ERR_FAILED +* RT_ERR_SMI +* +* Note: +* +*/ +rtk_api_ret_t rtk_nic_rxCrcErrEn_set(rtk_enable_t enabled) +{ + rtk_uint32 retVal ; + + if (NULL == RT_MAPPER->nic_rxCrcErrEn_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->nic_rxCrcErrEn_set(enabled); + RTK_API_UNLOCK(); + + return retVal; +} + +rtk_api_ret_t rtk_nic_rxCrcErrEn_get(rtk_enable_t *pEnabled) +{ + rtk_uint32 retVal ; + + if (NULL == RT_MAPPER->nic_rxCrcErrEn_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->nic_rxCrcErrEn_get(pEnabled); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_nic_rxL3CrcErrEn_set + * Description: + * enable rx l3 crc error pkt or not. + * Input: + * enabled - enable or disable - + * Output: + * none + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI + * + * Note: + * + */ +rtk_api_ret_t rtk_nic_rxL3CrcErrEn_set(rtk_enable_t enabled) +{ + rtk_uint32 retVal ; + if (NULL == RT_MAPPER->nic_rxL3CrcErrEn_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->nic_rxL3CrcErrEn_set(enabled); + RTK_API_UNLOCK(); + + return retVal; +} + +rtk_api_ret_t rtk_nic_rxL3CrcErrEn_get(rtk_enable_t *pEnabled) +{ + rtk_uint32 retVal ; + if (NULL == RT_MAPPER->nic_rxL3CrcErrEn_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->nic_rxL3CrcErrEn_get(pEnabled); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_nic_rxL4CrcErrEn_set + * Description: + * enable rx l4 crc error pkt or not. + * Input: + * enabled - enable or disable - + * Output: + * none + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI + * + * Note: + * + */ +rtk_api_ret_t rtk_nic_rxL4CrcErrEn_set(rtk_enable_t enabled) +{ + rtk_uint32 retVal ; + + if (NULL == RT_MAPPER->nic_rxL4CrcErrEn_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->nic_rxL4CrcErrEn_set(enabled); + RTK_API_UNLOCK(); + + return retVal; +} + +rtk_api_ret_t rtk_nic_rxL4CrcErrEn_get(rtk_enable_t *pEnabled) +{ + rtk_uint32 retVal ; + if (NULL == RT_MAPPER->nic_rxL4CrcErrEn_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->nic_rxL4CrcErrEn_get(pEnabled); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_nic_rxArpPassEn_set + * Description: + * enable ARP pkt pass or not. + * Input: + * enabled - enable or disable - + * Output: + * none + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI + * + * Note: + * + */ +rtk_api_ret_t rtk_nic_rxArpEn_set(rtk_enable_t enabled) +{ + rtk_uint32 retVal ; + + if (NULL == RT_MAPPER->nic_rxArpEn_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->nic_rxArpEn_set(enabled); + RTK_API_UNLOCK(); + + return retVal; +} + +rtk_api_ret_t rtk_nic_rxArpEn_get(rtk_enable_t *pEnabled) +{ + rtk_uint32 retVal ; + + if (NULL == RT_MAPPER->nic_rxArpEn_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->nic_rxArpEn_get(pEnabled); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_nic_rxAllPktEn_set + * Description: + * enable nic rx all pkt or not. + * Input: + * enabled - enable or disable - + * Output: + * none + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI + * + * Note: + * + */ +rtk_api_ret_t rtk_nic_rxAllPktEn_set(rtk_enable_t enabled) +{ + rtk_uint32 retVal ; + + if (NULL == RT_MAPPER->nic_rxAllPktEn_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->nic_rxAllPktEn_set(enabled); + RTK_API_UNLOCK(); + + return retVal; +} + +rtk_api_ret_t rtk_nic_rxAllPktEn_get(rtk_enable_t *pEnabled) +{ + rtk_uint32 retVal ; + + if (NULL == RT_MAPPER->nic_rxAllPktEn_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->nic_rxAllPktEn_get(pEnabled); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_nic_rxPhyPktSel_set + * Description: + * enable nic Receive Physical Address Packet Select or not. + * Input: + * enabled - enable or disable - + * Output: + * none + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI + * + * Note: + * + */ +rtk_api_ret_t rtk_nic_rxPhyPktSel_set(rtk_nic_rxpps_t behavior) +{ + rtk_uint32 retVal ; + + if (NULL == RT_MAPPER->nic_rxPhyPktSel_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->nic_rxPhyPktSel_set(behavior); + RTK_API_UNLOCK(); + + return retVal; +} + +rtk_api_ret_t rtk_nic_rxPhyPktSel_get(rtk_nic_rxpps_t *pBehavior) +{ + rtk_uint32 retVal ; + + if (NULL == RT_MAPPER->nic_rxPhyPktSel_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->nic_rxPhyPktSel_get(pBehavior); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_nic_rxMultiPktEn_set + * Description: + * enable nic Receive multicast packet or not. + * Input: + * enabled - enable or disable - + * Output: + * none + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI + * + * Note: + * + */ +rtk_api_ret_t rtk_nic_rxMultiPktEn_set(rtk_enable_t enabled) +{ + rtk_uint32 retVal ; + if (NULL == RT_MAPPER->nic_rxMultiPktEn_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->nic_rxMultiPktEn_set(enabled); + RTK_API_UNLOCK(); + + return retVal; +} + +rtk_api_ret_t rtk_nic_rxMultiPktEn_get(rtk_enable_t *pEnabled) +{ + rtk_uint32 retVal ; + + if (NULL == RT_MAPPER->nic_rxMultiPktEn_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->nic_rxMultiPktEn_get(pEnabled); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_nic_rxBcPktEn_set + * Description: + * enable nic Receive broadcast packet or not. + * Input: + * enabled - enable or disable - + * Output: + * none + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI + * + * Note: + * + */ +rtk_api_ret_t rtk_nic_rxBcPktEn_set(rtk_enable_t enabled) +{ + rtk_uint32 retVal ; + + if (NULL == RT_MAPPER->nic_rxBcPktEn_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->nic_rxBcPktEn_set(enabled); + RTK_API_UNLOCK(); + + return retVal; +} + +rtk_api_ret_t rtk_nic_rxBcPktEn_get(rtk_enable_t *pEnabled) +{ + rtk_uint32 retVal ; + + if (NULL == RT_MAPPER->nic_rxBcPktEn_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->nic_rxBcPktEn_get(pEnabled); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_nic_mcHashFltrEn_set + * Description: + * enable nic Received Multicast Packets Hash Filtering or not. + * Input: + * enabled - enable or disable - + * Output: + * none + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI + * + * Note: + * + */ +rtk_api_ret_t rtk_nic_mcHashFltrEn_set(rtk_enable_t enabled) +{ + rtk_uint32 retVal ; + + if (NULL == RT_MAPPER->nic_mcHashFltrEn_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->nic_mcHashFltrEn_set(enabled); + RTK_API_UNLOCK(); + + return retVal; +} + +rtk_api_ret_t rtk_nic_mcHashFltrEn_get(rtk_enable_t *pEnabled) +{ + rtk_uint32 retVal ; + if (NULL == RT_MAPPER->nic_mcHashFltrEn_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->nic_mcHashFltrEn_get(pEnabled); + RTK_API_UNLOCK(); + + return retVal; +} +/* Function Name: + * rtk_nic_PhyPktHashFltrEn_set + * Description: + * enable nic Received unicast Packets Hash Filtering or not. + * Input: + * enabled - enable or disable - + * Output: + * none + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI + * + * Note: + * + */ +rtk_api_ret_t rtk_nic_phyPktHashFltrEn_set(rtk_enable_t enabled) +{ + rtk_uint32 retVal ; + + if (NULL == RT_MAPPER->nic_phyPktHashFltrEn_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->nic_phyPktHashFltrEn_set(enabled); + RTK_API_UNLOCK(); + + return retVal; +} + +rtk_api_ret_t rtk_nic_phyPktHashFltrEn_get(rtk_enable_t *pEnabled) +{ + rtk_uint32 retVal ; + + if (NULL == RT_MAPPER->nic_phyPktHashFltrEn_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->nic_phyPktHashFltrEn_get(pEnabled); + RTK_API_UNLOCK(); + + return retVal; +} + + +/* Function Name: + * rtk_nic_mcHashTblVal_set + * Description: + * Set nic rx multicast pkt hash table value. + * Input: + * type - high 32 bits value / low 32 bits value + * val - value + * Output: + * none + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI + * + * Note: + * + */ +rtk_api_ret_t rtk_nic_mcHashTblVal_set(rtk_nic_hashValType_t type, rtk_uint32 val) +{ + rtk_uint32 retVal ; + + if (NULL == RT_MAPPER->nic_mcHashTblVal_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->nic_mcHashTblVal_set(type, val); + RTK_API_UNLOCK(); + + return retVal; +} + +rtk_api_ret_t rtk_nic_mcHashTblVal_get(rtk_nic_hashValType_t type, rtk_uint32 *pVal) +{ + rtk_uint32 retVal ; + + if (NULL == RT_MAPPER->nic_mcHashTblVal_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->nic_mcHashTblVal_get(type, pVal); + RTK_API_UNLOCK(); + + return retVal; +} + + +/* Function Name: + * rtk_nic_phyPktHashTblVal_set + * Description: + * Set nic rx unicast pkt hash table value. + * Input: + * type - high 32 bits value / low 32 bits value + * val - value + * Output: + * none + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI + * + * Note: + * + */ +rtk_api_ret_t rtk_nic_phyPktHashTblVal_set(rtk_nic_hashValType_t type, rtk_uint32 val) +{ + rtk_uint32 retVal ; + + if (NULL == RT_MAPPER->nic_phyPktHashTblVal_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->nic_phyPktHashTblVal_set(type, val); + RTK_API_UNLOCK(); + + return retVal; +} + +rtk_api_ret_t rtk_nic_phyPktHashTblVal_get(rtk_nic_hashValType_t type, rtk_uint32 *pVal) +{ + rtk_uint32 retVal ; + + if (NULL == RT_MAPPER->nic_phyPktHashTblVal_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->nic_phyPktHashTblVal_get(type, pVal); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_nic_rxMTU_set + * Description: + * set nic RXMTU. + * Input: + * length - max length nic could recieved - + * Output: + * none + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI + * + * Note: + * + */ +rtk_api_ret_t rtk_nic_rxMTU_set(rtk_nic_RxMTU_t length) +{ + rtk_uint32 retVal ; + + if (NULL == RT_MAPPER->nic_rxMTU_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->nic_rxMTU_set(length); + RTK_API_UNLOCK(); + + return retVal; +} + +rtk_api_ret_t rtk_nic_rxMTU_get(rtk_nic_RxMTU_t *pLength) +{ + rtk_uint32 retVal ; + + if (NULL == RT_MAPPER->nic_rxMTU_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->nic_rxMTU_get(pLength); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_nic_LoopbackEn_set + * Description: + * enable nic loopback ablity. + * Input: + * enabled - enable or disable + * Output: + * none + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI + * + * Note: + * + */ +rtk_api_ret_t rtk_nic_loopbackEn_set(rtk_enable_t enabled) +{ + rtk_uint32 retVal ; + + if (NULL == RT_MAPPER->nic_loopbackEn_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->nic_loopbackEn_set(enabled); + RTK_API_UNLOCK(); + + return retVal; +} + +rtk_api_ret_t rtk_nic_loopbackEn_get(rtk_enable_t *pEnabled) +{ + rtk_uint32 retVal; + + if (NULL == RT_MAPPER->nic_loopbackEn_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->nic_loopbackEn_get(pEnabled); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_nic_InterruptEn_set + * Description: + * enable nic Rx Interrupt and TX Error Interrupt. + * Input: + * enabled - enable or disable - + * Output: + * none + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI + * + * Note: + * + */ +rtk_api_ret_t rtk_nic_interruptEn_set(rtk_enable_t rxie, rtk_enable_t txee) +{ + rtk_uint32 retVal ; + + if (NULL == RT_MAPPER->nic_interruptEn_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->nic_interruptEn_set(rxie, txee); + RTK_API_UNLOCK(); + + return retVal; +} + +rtk_api_ret_t rtk_nic_interruptEn_get(rtk_enable_t * pRxie, rtk_enable_t *pTxee) +{ + rtk_uint32 retVal ; + + if (NULL == RT_MAPPER->nic_interruptEn_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->nic_interruptEn_get(pRxie, pTxee); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_nic_InterruptStatus_set + * Description: + * get nic Rx Interrupt's status and TX Error Interrupt's status. + * Input: + * enabled - enable or disable - + * Output: + * none + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_SMI + * + * Note: + * + */ +rtk_api_ret_t rtk_nic_interruptStatus_get(rtk_uint32 * pRxis, rtk_uint32 *pTxes) +{ + rtk_uint32 retVal ; + + if (NULL == RT_MAPPER->nic_interruptStatus_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->nic_interruptStatus_get(pRxis, pTxes); + RTK_API_UNLOCK(); + + return retVal; +} + +rtk_api_ret_t rtk_nic_interruptStatus_clear(rtk_uint32 rxis, rtk_uint32 txes) +{ + rtk_uint32 retVal ; + + if (NULL == RT_MAPPER->nic_interruptStatus_clear) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->nic_interruptStatus_clear(rxis, txes); + RTK_API_UNLOCK(); + + return retVal; +} + + + + diff --git a/sources/uboot-be550/drivers/net/rtl8372/nic.h b/sources/uboot-be550/drivers/net/rtl8372/nic.h new file mode 100755 index 00000000..b216acea --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/nic.h @@ -0,0 +1,110 @@ +/******************************************************************************* +* Copyright (C), 2013, Realtek Semiconductor Corp. +* All Rights Reserved. +* +* This program is the proprietary software of Realtek Semiconductor +* Corporation and/or its licensors, and only be used, duplicated, +* modified or distributed under the authorized license from Realtek. +* +* ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER +* THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. +* +* File Name: +* Author : Cynthia_wang +* Version : +* Date : 2020-9-24 +* Purpose : RTL8373 switch high-level API for RTL8373 +* Feature : Here is a list of all functions and variables in NIC module +* Note: +*******************************************************************************/ + + +#ifndef __RTK_API_NIC_H__ +#define __RTK_API_NIC_H__ + +#define RTK_NIC_RXSTOP_MAX (0x7FF) +#define RTK_NIC_TXSTOP_MAX (0x7FF) + +#define RTK_ETHER_TYPE_MAX (0xFFFF) +#define RTK_RXFST_WIDTH (0xFF) + +typedef enum rtk_nic_RxMTU_e +{ + NIC_RX_MTU_1534 = 0, + NIC_RX_MTU_2048 , + NIC_RX_MTU_4096 , + NIC_RX_MTU_END +} rtk_nic_RxMTU_t; + +typedef enum rtk_nic_rxpps_e +{ + NIC_RX_PPS_DROPALL = 0, + NIC_RX_PPS_RXMATCHED , + NIC_RX_PPS_RXUNMATCHED , + NIC_RX_PPS_RXALL, + NIC_RX_PPS_END +} rtk_nic_rxpps_t; + +typedef enum rtk_nic_hashValType_e +{ + NIC_HASH_VAL_LOW_WORD = 0, + NIC_HASH_VAL_HIGH_WORD, + NIC_HASH_TYPE_END +} rtk_nic_hashValType_t; + + +extern rtk_api_ret_t rtk_nic_rst_set(void); +extern rtk_api_ret_t rtk_nic_txstop_set(rtk_uint32 addr); +extern rtk_api_ret_t rtk_nic_txstop_get(rtk_uint32 *pAddr); +extern rtk_api_ret_t rtk_nic_rxstop_set( rtk_uint32 addr); +extern rtk_api_ret_t rtk_nic_rxstop_get(rtk_uint32 *pAddr); +extern rtk_api_ret_t rtk_nic_swRxCurPktAddr_get(rtk_uint32 *pAddr); +extern rtk_api_ret_t rtk_nic_rxReceivedPktLen_get(rtk_uint32 *pLength); +extern rtk_api_ret_t rtk_nic_txAvailSpace_get(rtk_uint32 *pLength); +extern rtk_api_ret_t rtk_nic_moduleEn_set(rtk_enable_t enable); +extern rtk_api_ret_t rtk_nic_moduleEn_get(rtk_enable_t *pStatus); +extern rtk_api_ret_t rtk_nic_rxEn_set(rtk_enable_t enable); +extern rtk_api_ret_t rtk_nic_rxEn_get(rtk_enable_t *pStatus); +extern rtk_api_ret_t rtk_nic_txEn_set(rtk_enable_t enable); +extern rtk_api_ret_t rtk_nic_txEn_get(rtk_enable_t *pStatus); +extern rtk_api_ret_t rtk_nic_rxRemoveCrc_set(rtk_enable_t enabled); +extern rtk_api_ret_t rtk_nic_rxRemoveCrc_get(rtk_enable_t *pEnabled); +extern rtk_api_ret_t rtk_nic_rxPaddingEn_set(rtk_enable_t enabled); +extern rtk_api_ret_t rtk_nic_rxPaddingEn_get(rtk_enable_t *pEnabled); +extern rtk_api_ret_t rtk_nic_rxFreeSpaceThd_set(rtk_uint32 val); +extern rtk_api_ret_t rtk_nic_rxFreeSpaceThd_get(rtk_uint32 *pVal); +extern rtk_api_ret_t rtk_nic_rxCrcErrEn_set(rtk_enable_t enabled); +extern rtk_api_ret_t rtk_nic_rxCrcErrEn_get(rtk_enable_t *pEnabled); +extern rtk_api_ret_t rtk_nic_rxL3CrcErrEn_set(rtk_enable_t enabled); +extern rtk_api_ret_t rtk_nic_rxL3CrcErrEn_get(rtk_enable_t *pEnabled); +extern rtk_api_ret_t rtk_nic_rxL4CrcErrEn_set(rtk_enable_t enabled); +extern rtk_api_ret_t rtk_nic_rxL4CrcErrEn_get(rtk_enable_t *pEnabled); +extern rtk_api_ret_t rtk_nic_rxArpEn_set(rtk_enable_t enabled); +extern rtk_api_ret_t rtk_nic_rxArpEn_get(rtk_enable_t *pEnabled); +extern rtk_api_ret_t rtk_nic_rxAllPktEn_set(rtk_enable_t enabled); +extern rtk_api_ret_t rtk_nic_rxAllPktEn_get(rtk_enable_t *pEnabled); +extern rtk_api_ret_t rtk_nic_rxPhyPktSel_set(rtk_nic_rxpps_t behavior); +extern rtk_api_ret_t rtk_nic_rxPhyPktSel_get(rtk_nic_rxpps_t *pBehavior); +extern rtk_api_ret_t rtk_nic_rxMultiPktEn_set(rtk_enable_t enabled); +extern rtk_api_ret_t rtk_nic_rxMultiPktEn_get(rtk_enable_t *pEnabled); +extern rtk_api_ret_t rtk_nic_rxBcPktEn_set(rtk_enable_t enabled); +extern rtk_api_ret_t rtk_nic_rxBcPktEn_get(rtk_enable_t *pEnabled); +extern rtk_api_ret_t rtk_nic_mcHashFltrEn_set(rtk_enable_t enabled); +extern rtk_api_ret_t rtk_nic_mcHashFltrEn_get(rtk_enable_t *pEnabled); +extern rtk_api_ret_t rtk_nic_phyPktHashFltrEn_set(rtk_enable_t enabled); +extern rtk_api_ret_t rtk_nic_phyPktHashFltrEn_get(rtk_enable_t *pEnabled); +extern rtk_api_ret_t rtk_nic_mcHashTblVal_set(rtk_nic_hashValType_t type, rtk_uint32 val); +extern rtk_api_ret_t rtk_nic_mcHashTblVal_get(rtk_nic_hashValType_t type, rtk_uint32 *pVal); +extern rtk_api_ret_t rtk_nic_phyPktHashTblVal_set(rtk_nic_hashValType_t type, rtk_uint32 val); +extern rtk_api_ret_t rtk_nic_phyPktHashTblVal_get(rtk_nic_hashValType_t type, rtk_uint32 *pVal); +extern rtk_api_ret_t rtk_nic_rxMTU_set(rtk_nic_RxMTU_t length); +extern rtk_api_ret_t rtk_nic_rxMTU_get(rtk_nic_RxMTU_t *pLength); +extern rtk_api_ret_t rtk_nic_loopbackEn_set(rtk_enable_t enabled); +extern rtk_api_ret_t rtk_nic_loopbackEn_get(rtk_enable_t *pEnabled); +extern rtk_api_ret_t rtk_nic_interruptEn_set(rtk_enable_t rxie, rtk_enable_t txee); +extern rtk_api_ret_t rtk_nic_interruptEn_get(rtk_enable_t *pRxie, rtk_enable_t *pTxee); +extern rtk_api_ret_t rtk_nic_interruptStatus_get(rtk_uint32 * pRxis, rtk_uint32 *pTxes); +extern rtk_api_ret_t rtk_nic_interruptStatus_clear(rtk_uint32 rxis, rtk_uint32 txes); + + +#endif diff --git a/sources/uboot-be550/drivers/net/rtl8372/phy_rtl8224.c b/sources/uboot-be550/drivers/net/rtl8372/phy_rtl8224.c new file mode 100755 index 00000000..6891714e --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/phy_rtl8224.c @@ -0,0 +1,1376 @@ +/* + * Copyright (C) 2018 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision: 75479 $ + * $Date: 2017-01-20 15:17:16 +0800 (Fri, 20 Jan 2017) $ + * + * Purpose : PHY 8284 Driver APIs. + * + * Feature : PHY 8284 Driver APIs + * + */ + #include +#include +#include "miim.h" +#include "ptp.h" +#include "chip.h" +#include "port.h" +#include "phydef.h" +#include +#include +#include +#include +/* + * Data Declaration + */ + +static rtk_uint32 ptp_portmask = 0x0f; + +/* Function Name: + * phy_8224_bypassptpEn_get + * Description: + * Get PTP status of the specified port. + * Input: + * port - port id + * Output: + * pEnable - status + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT - invalid port id + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None + */ +ret_t phy_8224_bypassptpEn_get( rtk_port_t port, rtk_enable_t *pEnable) +{ + ret_t retVal; + + if(pEnable==NULL) + return RT_ERR_INPUT; + + retVal= rtk_port_phyReg_getBits(RTL8224PHYID,RTL8224TOPDEVAD,RTL8373_P0_MISC_CTRL_ADDR(port),RTL8373_P0_MISC_CTRL_P0_CFG_BYPASS_MASK,pEnable); + if(retVal != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; +} + +/* Function Name: + * phy_8224_bypassptpEn_set + * Description: + * Get PTP status of the specified port. + * Input: + * port - port id + * pEnable - status + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT - invalid port id + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None + */ +ret_t phy_8224_bypassptpEn_set( rtk_port_t port, rtk_enable_t pEnable) +{ + return rtk_port_phyReg_setBits(RTL8224BASEID,RTL8224TOPDEVAD,RTL8373_P0_MISC_CTRL_ADDR(port),RTL8373_P0_MISC_CTRL_P0_CFG_BYPASS_MASK,pEnable); +} +/* Function Name: + * phy_8224_ptp_portmask + * Description: + * PTP function initialization. + * Input: + * portmask range 0~0xf + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API is used to initialize PTP status. + */ +ret_t phy_8224_ptp_portmask(rtk_portmask_t portmask) +{ + ptp_portmask=portmask.bits[0]; + return RT_ERR_OK; +} +/* Function Name: + * phy_8224_ptp_init + * Description: + * PTP function initialization. + * Input: + * ptpinternalpmask port range 0~0xf + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API is used to initialize PTP status. + */ +ret_t phy_8224_ptp_init( rtk_portmask_t ptppmask) +{ + + rtk_port_t port; + rtk_uint32 freq=0x10000000;//internal clock + + /* Check initialization state */ + phy_8224_ptp_portmask(ptppmask); + + for(port=UTP_PORT0;port= VLAN_TYPE_END) || (idx > 4)) + return RT_ERR_INPUT; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(type == OUTER_VLAN) + { + if((retVal = rtk_port_phyReg_set(RTL8224BASEID,RTL8224TOPDEVAD,RTL8373_PTP_OTAG_CONFIG0_ADDR+(4<= VLAN_TYPE_END) || (idx > 4)) + return RT_ERR_INPUT; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(type == OUTER_VLAN) + { + if((retVal = rtk_port_phyReg_get(RTL8224PHYID,RTL8224TOPDEVAD,RTL8373_PTP_OTAG_CONFIG0_ADDR+(4<> 4; + switch (oper) + { + case 0: + pOperCfg->oper = TIME_OPER_START; + break; + case 1: + pOperCfg->oper = TIME_OPER_LATCH; + break; + case 2: + pOperCfg->oper = TIME_OPER_STOP; + break; + case 3: + pOperCfg->oper = TIME_OPER_CMD_EXEC; + break; + case 4: + pOperCfg->oper = TIME_OPER_FREQ_APPLY; + break; + default: + return RT_ERR_FAILED; + } + + pOperCfg->rise_tri = (reg_val & RTL8373_PTP_TIME_OP_CTRL_CFG_GPI_RISE_TRIG_MASK) >> 3; + pOperCfg->fall_tri = (reg_val & RTL8373_PTP_TIME_OP_CTRL_CFG_GPI_FALL_TRIG_MASK) >> 2; + + /*to be added phy*/ + + return ret; +} + +/* Function Name: + * phy_8224_ptp_Oper_set + * Description: + * Set the PTP time operation configuration of specific port. + * Input: + * port - port ID + * pOperCfg - pointer to PTP time operation configuraton + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None + */ +ret_t phy_8224_ptp_Oper_set( rtk_time_operCfg_t pOperCfg) +{ + rtk_int32 ret = RT_ERR_OK; + rtk_uint32 reg_val = 0; + + switch (pOperCfg.oper) + { + case TIME_OPER_START: + reg_val = 0 << 4; + break; + case TIME_OPER_LATCH: + reg_val = 1 << 4; + break; + case TIME_OPER_STOP: + reg_val = 2 << 4; + break; + case TIME_OPER_CMD_EXEC: + reg_val = 3 << 4; + break; + case TIME_OPER_FREQ_APPLY: + reg_val = 4 << 4; + break; + default: + return RT_ERR_FAILED; + } + + reg_val |= (pOperCfg.rise_tri == ENABLED) ? (RTL8373_PTP_TIME_OP_CTRL_CFG_GPI_RISE_TRIG_MASK) : (0); + reg_val |= (pOperCfg.fall_tri == ENABLED) ? (RTL8373_PTP_TIME_OP_CTRL_CFG_GPI_FALL_TRIG_MASK) : (0); + if((ret = rtk_port_phyReg_set(RTL8224BASEID,RTL8224TOPDEVAD,RTL8373_PTP_TIME_OP_CTRL_ADDR, reg_val)) != RT_ERR_OK) + return ret; + + /*to be added phy*/ + + return ret; +} + +/* Function Name: + * dal_rtl8371c_ptp_LatchTime_get + * Description: + * Get the PTP latched time of specific port by hardware. + * Input: + * Output: + * pLatchTime - pointer to PTP time operation configuraton + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None + */ +ret_t phy_8224_ptp_LatchTime_get( rtk_time_timeStamp_t *pLatchTime) +{ + rtk_int32 ret = RT_ERR_OK; + rtk_uint32 sec_l = 0; + rtk_uint32 sec_m = 0; + rtk_uint32 sec_h = 0; + rtk_uint32 nsec_l = 0; + rtk_uint32 nsec_h = 0; + + if((ret = rtk_port_phyReg_get(RTL8224PHYID,RTL8224TOPDEVAD,RTL8373_PTP_TIME_SEC_RD2_ADDR, &sec_h)) != RT_ERR_OK) + return ret; + if((ret = rtk_port_phyReg_get(RTL8224PHYID,RTL8224TOPDEVAD,RTL8373_PTP_TIME_SEC_RD1_ADDR, &sec_m)) != RT_ERR_OK) + return ret; + if((ret = rtk_port_phyReg_get(RTL8224PHYID,RTL8224TOPDEVAD,RTL8373_PTP_TIME_SEC_RD0_ADDR, &sec_l)) != RT_ERR_OK) + return ret; + if((ret = rtk_port_phyReg_get(RTL8224PHYID,RTL8224TOPDEVAD,RTL8373_PTP_TIME_NSEC_RD1_ADDR, &nsec_h)) != RT_ERR_OK) + return ret; + if((ret = rtk_port_phyReg_get(RTL8224PHYID,RTL8224TOPDEVAD,RTL8373_PTP_TIME_NSEC_RD0_ADDR, &nsec_l)) != RT_ERR_OK) + return ret; + + pLatchTime->sec = ((rtk_uint64)sec_h << 32) | ((rtk_uint64)sec_m << 16) | ((rtk_uint64)sec_l & 0xFFFF); + pLatchTime->nsec = (((nsec_h & 0x3FFF) << 16) | (nsec_l & 0xFFFF)); + + /*to be added phy*/ + + return RT_ERR_OK; +} + +/* Function Name: + * phy_8224_ptp_refTimeOp_set + * Description: + * Set the reference time of the specified device. + * Input: + * extoption - reference timestamp value + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT - invalid input parameter + * Applicable: + * Note: + * need gpio triger + */ +ret_t phy_8224_ptp_refTimeOp_set(rtk_uint32 extoption) +{ + if(extoption>=PTP_TIME_CMD_END) + return RT_ERR_INPUT; + + return rtk_port_phyReg_setBits(RTL8224BASEID,RTL8224TOPDEVAD,RTL8373_PTP_TIME_CRTL_ADDR,RTL8373_PTP_TIME_CRTL_PTP_TIME_CMD_MASK, extoption); +} +/* Function Name: + * dal_rtl8371c_ptp_refTime_set + * Description: + * Set the reference time of the specified device. + * Input: + * type + * timeStamp - reference timestamp value + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT - invalid input parameter + * Applicable: + * Note: + * need gpio triger + */ +ret_t phy_8224_ptp_refTime_set(rtk_time_timeStamp_t timeStamp) +{ + ret_t retVal; + rtk_uint32 sec_h, sec_m,sec_l, nsec8_h, nsec8_l; + rtk_uint32 nano_second_8; + rtk_uint32 busyFlag, count; + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (timeStamp.nsec > RTK_MAX_NUM_OF_NANO_SECOND) + return RT_ERR_INPUT; + + sec_h = (timeStamp.sec>>32)& 0xFFFF; + sec_m = (timeStamp.sec >>16)& 0xFFFF; + sec_l = timeStamp.sec & 0xFFFF; + nano_second_8 = timeStamp.nsec >> 3; + nsec8_h = (nano_second_8 >>16) & 0xFFFF; + nsec8_l = nano_second_8 &0xFFFF; + + if((retVal = rtk_port_phyReg_set(RTL8224BASEID,RTL8224TOPDEVAD,RTL8373_PTP_TIME_NSEC1_ADDR, nsec8_h)) != RT_ERR_OK) + return retVal; + if((retVal = rtk_port_phyReg_set(RTL8224BASEID,RTL8224TOPDEVAD,RTL8373_PTP_TIME_NSEC0_ADDR, nsec8_l)) != RT_ERR_OK) + return retVal; + + if((retVal = rtk_port_phyReg_set(RTL8224BASEID,RTL8224TOPDEVAD,RTL8373_PTP_TIME_SEC2_ADDR, sec_h)) != RT_ERR_OK) + return retVal; + if((retVal = rtk_port_phyReg_set(RTL8224BASEID,RTL8224TOPDEVAD,RTL8373_PTP_TIME_SEC1_ADDR, sec_m)) != RT_ERR_OK) + return retVal; + if((retVal = rtk_port_phyReg_set(RTL8224BASEID,RTL8224TOPDEVAD,RTL8373_PTP_TIME_SEC0_ADDR, sec_l)) != RT_ERR_OK) + return retVal; + + if((retVal = rtk_port_phyReg_setBits(RTL8224BASEID,RTL8224TOPDEVAD,RTL8373_PTP_TIME_CRTL_ADDR,RTL8373_PTP_TIME_CRTL_PTP_TIME_CMD_MASK, PTP_TIME_WRITE)) != RT_ERR_OK) + return retVal; + if((retVal = rtk_port_phyReg_setBits(RTL8224BASEID,RTL8224TOPDEVAD,RTL8373_PTP_TIME_NSEC1_ADDR,RTL8373_PTP_TIME_NSEC1_CFG_TOD_VALID_MASK,ENABLED)) != RT_ERR_OK) + return retVal; + + if((retVal = rtk_port_phyReg_setBits(RTL8224BASEID,RTL8224TOPDEVAD,RTL8373_PTP_TIME_CRTL_ADDR,RTL8373_PTP_TIME_CRTL_PTP_TIME_EXEC_MASK, 1)) != RT_ERR_OK) + return retVal; + + count = 0; + do { + if((retVal = rtk_port_phyReg_getBits(RTL8224PHYID,RTL8224TOPDEVAD,RTL8373_PTP_TIME_CRTL_ADDR, RTL8373_PTP_TIME_CRTL_PTP_TIME_EXEC_MASK, &busyFlag)) != RT_ERR_OK) + return retVal; + count++; + } while ((busyFlag != 0)&&(count<5)); + + if (busyFlag != 0) + return RT_ERR_BUSYWAIT_TIMEOUT; + + return RT_ERR_OK; +} + + +/* Function Name: + * phy_8224_ptp_refTime_get + * Description: + * Get the reference time of the specified device by software. + * Input: + * Output: + * pTimeStamp - pointer buffer of the reference time + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Applicable: + * 8371 + * Note: + * need gpio triger + */ +ret_t phy_8224_ptp_refTime_get(rtk_time_timeStamp_t *pTimeStamp) +{ + ret_t retVal; + rtk_uint32 sec_h, sec_m,sec_l; + rtk_uint32 nsec8_h, nsec8_l; + rtk_uint32 nano_second_8; + rtk_uint32 busyFlag, count; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if(pTimeStamp == NULL) + { + return RT_ERR_INPUT; + } + if((retVal = rtk_port_phyReg_setBits(RTL8224BASEID,RTL8224TOPDEVAD,RTL8373_PTP_TIME_CRTL_ADDR,RTL8373_PTP_TIME_CRTL_PTP_TIME_CMD_MASK, PTP_TIME_READ)) != RT_ERR_OK) + return retVal; + + if((retVal = rtk_port_phyReg_setBits(RTL8224BASEID,RTL8224TOPDEVAD,RTL8373_PTP_TIME_CRTL_ADDR,RTL8373_PTP_TIME_CRTL_PTP_TIME_EXEC_MASK, 1)) != RT_ERR_OK) + return retVal; + + count = 0; + do { + if((retVal = rtk_port_phyReg_getBits(RTL8224PHYID,RTL8224TOPDEVAD,RTL8373_PTP_TIME_CRTL_ADDR, RTL8373_PTP_TIME_CRTL_PTP_TIME_EXEC_MASK, &busyFlag)) != RT_ERR_OK) + return retVal; + count++; + } while ((busyFlag != 0)&&(count<5)); + + if (busyFlag != 0) + return RT_ERR_BUSYWAIT_TIMEOUT; + + if((retVal = rtk_port_phyReg_get(RTL8224PHYID,RTL8224TOPDEVAD,RTL8373_PTP_TIME_SEC_RD2_ADDR, &sec_h)) != RT_ERR_OK) + return retVal; + if((retVal = rtk_port_phyReg_get(RTL8224PHYID,RTL8224TOPDEVAD,RTL8373_PTP_TIME_SEC_RD1_ADDR, &sec_m)) != RT_ERR_OK) + return retVal; + if((retVal = rtk_port_phyReg_get(RTL8224PHYID,RTL8224TOPDEVAD,RTL8373_PTP_TIME_SEC_RD0_ADDR, &sec_l)) != RT_ERR_OK) + return retVal; + if((retVal = rtk_port_phyReg_get(RTL8224PHYID,RTL8224TOPDEVAD,RTL8373_PTP_TIME_NSEC_RD1_ADDR, &nsec8_h)) != RT_ERR_OK) + return retVal; + if((retVal = rtk_port_phyReg_get(RTL8224PHYID,RTL8224TOPDEVAD,RTL8373_PTP_TIME_NSEC_RD0_ADDR, &nsec8_l)) != RT_ERR_OK) + return retVal; + + pTimeStamp->sec= ((rtk_uint64)sec_h<<32) | ((rtk_uint64)sec_m<<16) |(rtk_uint64)sec_l; + nano_second_8 = (nsec8_h<<16) | nsec8_l; + pTimeStamp->nsec= nano_second_8<<3; + +/*to be added*/ + return RT_ERR_OK; +} + +/* Function Name: + * phy_8224_ptp_refTimeAdjust_set + * Description: + * Adjust the reference time. + * Input: + * sign - significant + * timeStamp - reference timestamp value + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Note: + * sign=0 for positive adjustment, sign=1 for negative adjustment. + */ + ret_t phy_8224_ptp_refTimeAdjust_set( rtk_ptp_sys_adjust_t sign, rtk_time_timeStamp_t timeStamp) +{ + ret_t retVal; + rtk_uint32 sec_h, sec_m,sec_l, nsec8_h, nsec8_l; + rtk_uint32 nano_second_8; + rtk_uint64 sec; + rtk_uint32 nsec=0; + + /* Check initialization state */ + RTK_CHK_INIT_STATE(); + + if (timeStamp.nsec > DAL_RTL8373_MAX_NUM_OF_NANO_SECOND) + return RT_ERR_INPUT; + + if (sign >= SYS_ADJUST_END) + return RT_ERR_INPUT; + + if (sign == SYS_ADJUST_MINUS) + { + sec = 0; + } + else + { + /* adjust Timer of PHY */ + sec = 0 - (timeStamp.sec + 1); + nsec = 1000000000 - timeStamp.nsec; + } + + + sec_h = (rtk_uint32)(sec >>32)& 0xFFFF; + sec_m = (rtk_uint32)(sec >>16)& 0xFFFF; + sec_l = sec & 0xFFFF; + nano_second_8 = nsec >> 3; + nsec8_h = (nano_second_8 >>16) & 0xFFFF; + nsec8_l = nano_second_8 &0xFFFF; + + if((retVal = rtk_port_phyReg_set(RTL8224BASEID,RTL8224TOPDEVAD,RTL8373_PTP_TIME_SEC2_ADDR, sec_h)) != RT_ERR_OK) + return retVal; + if((retVal = rtk_port_phyReg_set(RTL8224BASEID,RTL8224TOPDEVAD,RTL8373_PTP_TIME_SEC1_ADDR, sec_m)) != RT_ERR_OK) + return retVal; + if((retVal = rtk_port_phyReg_set(RTL8224BASEID,RTL8224TOPDEVAD,RTL8373_PTP_TIME_SEC0_ADDR, sec_l)) != RT_ERR_OK) + return retVal; + + if((retVal = rtk_port_phyReg_set(RTL8224BASEID,RTL8224TOPDEVAD,RTL8373_PTP_TIME_NSEC1_ADDR, nsec8_h)) != RT_ERR_OK) + return retVal; + if((retVal = rtk_port_phyReg_set(RTL8224BASEID,RTL8224TOPDEVAD,RTL8373_PTP_TIME_NSEC0_ADDR, nsec8_l)) != RT_ERR_OK) + return retVal; + + return RT_ERR_OK; + +} + + +/* Function Name: + * phy_8224_ptp_TxTimestampFifo_get + * Description: + * Get the top entry from PTP Tx timstamp FIFO on the dedicated port from the specified device. + * Input: + * port - port id + * Output: + * pTimeEntry - pointer buffer of TIME timestamp entry + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None + */ +ret_t phy_8224_ptp_TxTimestampFifo_get(rtk_time_txTimeEntry_t *pTimeEntry) +{ + ret_t retVal = RT_ERR_OK; + rtk_uint32 reg_val = 0; + // rtk_uint32 reg_msk = 0; + rtk_uint32 sec_l = 0; + rtk_uint32 sec_m = 0; + rtk_uint32 sec_h = 0; + rtk_uint32 regData,count,busyFlag; + // rtl8371c_ptp_tx_time_stamp_t txtimestamp; + + if((retVal = rtk_port_phyReg_get(RTL8224PHYID,RTL8224TOPDEVAD,RTL8373_PTP_TX_TIMESTAMP_RD0_ADDR,®_val)) != RT_ERR_OK) + return retVal; + + pTimeEntry->valid = (reg_val & RTL8373_PTP_TX_TIMESTAMP_RD0_RD_TX_TIMESTAMP_VALID_MASK)? 1:0; + pTimeEntry->port = (reg_val & RTL8373_PTP_TX_TIMESTAMP_RD0_RD_PORT_ID_MASK) >> 8; + pTimeEntry->msg_type = (reg_val & RTL8373_PTP_TX_TIMESTAMP_RD0_RD_MSG_TYPE_MASK) >> 6; + pTimeEntry->seqId = (reg_val & RTL8373_PTP_TX_TIMESTAMP_RD0_RD_SEQ_ID_H_MASK) << 10; + + if((retVal = rtk_port_phyReg_get(RTL8224PHYID,RTL8224TOPDEVAD,RTL8373_PTP_TX_TIMESTAMP_RD1_ADDR,®_val)) != RT_ERR_OK) + return retVal; + + pTimeEntry->seqId |= (reg_val & RTL8373_PTP_TX_TIMESTAMP_RD1_RD_SEQ_ID_L_MASK) >> 6; + pTimeEntry->txTime.sec = (reg_val & RTL8373_PTP_TX_TIMESTAMP_RD1_RD_TX_TIMESTAMP_SEC_H_MASK) << 2; + + if((retVal = rtk_port_phyReg_get(RTL8224PHYID,RTL8224TOPDEVAD,RTL8373_PTP_TX_TIMESTAMP_RD2_ADDR,®_val)) != RT_ERR_OK) + return retVal; + + pTimeEntry->txTime.sec |= (reg_val & RTL8373_PTP_TX_TIMESTAMP_RD2_RD_TX_TIMESTAMP_SEC_L_MASK) >> 14; + pTimeEntry->txTime.nsec = (reg_val & RTL8373_PTP_TX_TIMESTAMP_RD2_RD_TX_TIMESTAMP_NSEC_H_MASK) << 16; + + if((retVal = rtk_port_phyReg_get(RTL8224PHYID,RTL8224TOPDEVAD,RTL8373_PTP_TX_TIMESTAMP_RD3_ADDR,®_val)) != RT_ERR_OK) + return retVal; + + pTimeEntry->txTime.nsec |= (reg_val & RTL8373_PTP_TX_TIMESTAMP_RD3_RD_TX_TIMESTAMP_NSEC_L_MASK); + + // rtl8371c_getAsicEavSysTime(&Sec,&NanoSec);/* 8 bits sec is not overflow yet */ + + regData = (PTP_TIME_READ<=pTimeEntry->txTime.sec) + { + pTimeEntry->txTime.sec |= ((rtk_uint64)sec_h << 32) | ((rtk_uint64)sec_m << 16) | ((rtk_uint64)sec_l & 0xFF00); + } + else + { + pTimeEntry->txTime.sec |= ((rtk_uint64)sec_h << 32) | ((rtk_uint64)sec_m << 16) | ((rtk_uint64)sec_l & 0xFF00); + pTimeEntry->txTime.sec -= 0x100; + } + + + /*to be added phy*/ + + return RT_ERR_OK; +} + + +/* Function Name: + * phy_8224_ptp_1PPSOutput_get + * Description: + * Get 1 PPS output configuration of the specified port. + * Input: + * type - phy or mac + * Output: + * pPulseWidth - pointer to 1 PPS pulse width, unit: 10 ms + * pEnable - pointer to 1 PPS output enable status + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None + */ +ret_t phy_8224_ptp_1PPSOutput_get( rtk_uint32 *pPulseWidth, rtk_enable_t *pEnable) +{ + ret_t ret ; + rtk_uint32 reg_val = 0; + + ret=rtk_port_phyReg_get(RTL8224PHYID,RTL8224TOPDEVAD,RTL8373_PTP_PPS_CTRL_ADDR,®_val); + + if (reg_val & RTL8373_PTP_PPS_CTRL_CFG_PPS_EN_MASK) + *pEnable = ENABLED; + else + *pEnable = DISABLED; + + *pPulseWidth = reg_val & RTL8373_PTP_PPS_CTRL_CFG_PPS_WIDTH_MASK; + + /*to be added phy*/ + + + return ret; +} + + +/* Function Name: + * phy_8224_ptp_1PPSOutput_set + * Description: + * Set 1 PPS output configuration of the specified port. + * Input: + * type - phy or mac + * pulseWidth - pointer to 1 PPS pulse width, unit: 10 ms + * enable - enable 1 PPS output + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * Note: + * None + */ +ret_t phy_8224_ptp_1PPSOutput_set( rtk_uint32 pulseWidth, rtk_enable_t enable) +{ + rtk_uint32 reg_val = 0; + + if (pulseWidth > RTL8373_MAX_PPS_WIDTH) + return RT_ERR_OUT_OF_RANGE; + + reg_val = (enable << RTL8373_PTP_PPS_CTRL_CFG_PPS_EN_OFFSET) | (pulseWidth); + return rtk_port_phyReg_set(RTL8224BASEID,RTL8224TOPDEVAD,RTL8373_PTP_PPS_CTRL_ADDR,reg_val); +} + + +/* Function Name: + * phy_8224_ptp_ClockOutput_get + * Description: + * Get clock output configuration of the specified port. + * Input: + * pClkOutput -pClkOutput + * Output: + * pClkOutput - pointer to clock output configuration + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None + */ +ret_t phy_8224_ptp_ClockOutput_get( rtk_time_clkOutput_t *pClkOutput) +{ + ret_t ret = RT_ERR_OK; + rtk_uint32 reg_val = 0; + rtk_uint32 sec_l = 0; + rtk_uint32 sec_m = 0; + rtk_uint32 sec_h = 0; + rtk_uint32 nsec_l = 0; + rtk_uint32 nsec_h = 0; + + rtk_port_phyReg_get(RTL8224PHYID,RTL8224TOPDEVAD,RTL8373_PTP_CLKOUT_SEC0_ADDR, &sec_l); + rtk_port_phyReg_get(RTL8224PHYID,RTL8224TOPDEVAD,RTL8373_PTP_CLKOUT_SEC1_ADDR, &sec_m); + rtk_port_phyReg_get(RTL8224PHYID,RTL8224TOPDEVAD,RTL8373_PTP_CLKOUT_SEC2_ADDR, &sec_h); + rtk_port_phyReg_get(RTL8224PHYID,RTL8224TOPDEVAD,RTL8373_PTP_CLKOUT_NSEC0_ADDR, &nsec_l); + rtk_port_phyReg_get(RTL8224PHYID,RTL8224TOPDEVAD,RTL8373_PTP_CLKOUT_NSEC1_ADDR, &nsec_h); + + pClkOutput->startTime.sec = ((rtk_uint64)sec_h << 32) | ((rtk_uint64)sec_m << 16) | ((rtk_uint64)sec_l & 0xFFFF); + pClkOutput->startTime.nsec = (((nsec_h & 0x3FFF) << 16) | (nsec_l & 0xFFFF)); + + rtk_port_phyReg_get(RTL8224PHYID,RTL8224TOPDEVAD,RTL8373_PTP_CLKOUT_CTRL_ADDR, ®_val); + + if (reg_val & RTL8373_PTP_CLKOUT_CTRL_CFG_PULSE_MODE_MASK) + pClkOutput->mode = PTP_CLK_OUT_PULSE; + else + pClkOutput->mode = PTP_CLK_OUT_REPEAT; + + if (reg_val & RTL8373_PTP_CLKOUT_CTRL_CFG_CLKOUT_EN_MASK) + pClkOutput->enable = ENABLED; + else + pClkOutput->enable = DISABLED; + + if (reg_val & RTL8373_PTP_CLKOUT_CTRL_RD_CLKOUT_RUN_MASK) + pClkOutput->runing = TRUE; + else + pClkOutput->runing = FALSE; + + rtk_port_phyReg_get(RTL8224PHYID,RTL8224TOPDEVAD,RTL8373_PTP_CLKOUT_HALF_PERD_NS_L_ADDR, &nsec_l); + rtk_port_phyReg_get(RTL8224PHYID,RTL8224TOPDEVAD,RTL8373_PTP_CLKOUT_HALF_PERD_NS_H_ADDR, &nsec_h); + + pClkOutput->halfPeriodNsec = (((nsec_h & 0x3FFF) << 16) | (nsec_l & 0xFFFF)); + + /*to be added phy*/ + + return ret; +} + + +/* Function Name: + * phy_8224_ptp_ClockOutput_set + * Description: + * Set 1 PPS output configuration of the specified port. + * Input: +* type - phy or mac + * pClkOutput - pointer to clock output configuration + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * Note: + * None + */ +ret_t phy_8224_ptp_ClockOutput_set( rtk_time_clkOutput_t pClkOutput) +{ + rtk_uint32 reg_val = 0; + rtk_uint32 sec_l = 0; + rtk_uint32 sec_m = 0; + rtk_uint32 sec_h = 0; + rtk_uint32 nsec_l = 0; + rtk_uint32 nsec_h = 0; + + + /* adjust Timer of PHY */ + sec_l = (pClkOutput.startTime.sec) & 0xFFFF; + sec_m = ((pClkOutput.startTime.sec) >> 16) & 0xFFFF; + sec_h = ((pClkOutput.startTime.sec) >> 32) & 0xFFFF; + /* convert nsec to 8nsec */ + nsec_l = pClkOutput.startTime.nsec & 0xFFFF; + nsec_h = pClkOutput.startTime.nsec >> 16; + + rtk_port_phyReg_set(RTL8224BASEID,RTL8224TOPDEVAD,RTL8373_PTP_CLKOUT_SEC0_ADDR, sec_l); + rtk_port_phyReg_set(RTL8224BASEID,RTL8224TOPDEVAD,RTL8373_PTP_CLKOUT_SEC1_ADDR, sec_m); + rtk_port_phyReg_set(RTL8224BASEID,RTL8224TOPDEVAD,RTL8373_PTP_CLKOUT_SEC2_ADDR, sec_h); + rtk_port_phyReg_set(RTL8224BASEID,RTL8224TOPDEVAD,RTL8373_PTP_CLKOUT_NSEC0_ADDR, nsec_l); + rtk_port_phyReg_set(RTL8224BASEID,RTL8224TOPDEVAD,RTL8373_PTP_CLKOUT_NSEC1_ADDR, nsec_h); + + nsec_l = pClkOutput.halfPeriodNsec & 0xFFFF; + nsec_h = pClkOutput.halfPeriodNsec >> 16; + + rtk_port_phyReg_set(RTL8224BASEID,RTL8224TOPDEVAD,RTL8373_PTP_CLKOUT_HALF_PERD_NS_L_ADDR, nsec_l); + rtk_port_phyReg_set(RTL8224BASEID,RTL8224TOPDEVAD,RTL8373_PTP_CLKOUT_HALF_PERD_NS_H_ADDR, nsec_h); + + + reg_val = (pClkOutput.mode << RTL8373_PTP_CLKOUT_CTRL_CFG_PULSE_MODE_OFFSET) | (pClkOutput.enable << RTL8373_PTP_CLKOUT_CTRL_CFG_CLKOUT_EN_OFFSET); + + rtk_port_phyReg_set(RTL8224BASEID,RTL8224TOPDEVAD,RTL8373_PTP_CLKOUT_CTRL_ADDR, reg_val); + + + return RT_ERR_OK; + +} + +/* Function Name: + * phy_8224_ptp_portctrl_set + * Description: + * Get enable status for PTP transparent clock of the specified port. + * Input: + * port - port id + * portcfg -port role/udp_en/eth_en/always_ts + * Output: + * + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None + */ +ret_t phy_8224_ptp_portctrl_set( rtk_port_t port, rtk_ptp_port_ctrl_t portcfg) +{ + ret_t retVal = RT_ERR_OK; + rtk_uint32 link_delay_l,link_delay_h; + + if ((1<>10) & 0xFFFF; + + if((retVal = rtk_port_phyReg_setBits(RTL8224BASEID,RTL8224TOPDEVAD,RTL8373_P0_LINK_DELAY_H_ADDR(port), RTL8373_P0_LINK_DELAY_H_P0_CFG_LINK_DELAY_H_MASK,link_delay_h)) != RT_ERR_OK) + return retVal; + if((retVal = rtk_port_phyReg_setBits(RTL8224BASEID,RTL8224TOPDEVAD,RTL8373_P0_PORT_CTRL_ADDR(port), RTL8373_P0_PORT_CTRL_P0_CFG_LINK_DELAY_L_MASK,link_delay_l)) != RT_ERR_OK) + return retVal; + } + + + return retVal; +} + + +/* Function Name: + * phy_8224_ptp_portctrl_get + * Description: + * Get enable status for PTP transparent clock of the specified port. + * Input: + * port - port id + * Output: + * portcfg -port role/udp_en/eth_en/always_ts + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None + */ +ret_t phy_8224_ptp_portctrl_get( rtk_port_t port, rtk_ptp_port_ctrl_t *pportcfg) +{ + ret_t retVal = RT_ERR_OK; + rtk_uint32 link_delay_l=0; + rtk_uint32 link_delay_h=0; + rtk_uint32 portrole = 0; + rtk_uint32 udp_en = 0; + rtk_uint32 eth_en = 0; + rtk_uint32 always_ts_en = 0; + + if(pportcfg==NULL) + return RT_ERR_INPUT; + if ((1<always_ts_en=always_ts_en; + pportcfg->eth_en=eth_en; + pportcfg->udp_en=udp_en; + pportcfg->link_delay=link_delay_l|(link_delay_h<<10); + pportcfg->portrole=portrole; + } + + + return retVal; +} + + + +/* Function Name: + * phy_8224_ptp_TxImbal_set + * Description: + * Set TX/RX timer value compensation.. + * Input: + * port - port id + * TxImbal - TX timer value compensation + * RxImbal - RX timer value compensation + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * Note: + * unit: 1 ns + */ +ret_t phy_8224_ptp_TxImbal_set(rtk_port_t port, rtk_uint32 TxImbal,rtk_uint32 RxImbal) +{ + ret_t ret ; + + ret= rtk_port_phyReg_setBits(RTL8224BASEID,RTL8224TOPDEVAD,RTL8373_P0_TX_IMBAL_ADDR(port),RTL8373_P0_TX_IMBAL_P0_TX_IMBAL_MASK, TxImbal); + if(ret!=RT_ERR_OK) + return ret; + ret= rtk_port_phyReg_setBits(RTL8224BASEID,RTL8224TOPDEVAD,RTL8373_P0_RX_IMBAL_ADDR(port),RTL8373_P0_RX_IMBAL_P0_RX_IMBAL_MASK, RxImbal); + if(ret!=RT_ERR_OK) + return ret; + + return RT_ERR_OK; +} + +/* Function Name: + * phy_8224_ptp_TxImbal_get + * Description: + * Get TX/RX timer value compensation.. + * Input: + * port - port id + * PTxImbal - TX timer value compensation + * pRxImbal - RX timer value compensation + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * Note: + * unit: 1 ns + */ +ret_t phy_8224_ptp_TxImbal_get(rtk_port_t port, rtk_uint32 *pTxImbal,rtk_uint32 *pRxImbal) +{ + ret_t ret ; + + if ((pTxImbal==NULL)||(pRxImbal==NULL)) + return RT_ERR_INPUT; + + ret= rtk_port_phyReg_getBits(RTL8224PHYID,RTL8224TOPDEVAD,RTL8373_P0_TX_IMBAL_ADDR(port),RTL8373_P0_TX_IMBAL_P0_TX_IMBAL_MASK, pTxImbal); + if(ret!=RT_ERR_OK) + return ret; + ret=rtk_port_phyReg_getBits(RTL8224PHYID,RTL8224TOPDEVAD,RTL8373_P0_RX_IMBAL_ADDR(port),RTL8373_P0_RX_IMBAL_P0_RX_IMBAL_MASK, pRxImbal); + if(ret!=RT_ERR_OK) + return ret; + + return RT_ERR_OK; +} + +/* Function Name: + * phy_8224_ptp_phyidtoportid_set + * Description: + * Set Packet TX port ID.. + * Input: + * port - port id + * ptp_portino - TX timer value compensation + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * Note: + * unit: 1 ns + */ +ret_t phy_8224_ptp_phyidtoportid_set(rtk_port_t port, rtk_port_t ptp_portino) +{ + return rtk_port_phyReg_set(RTL8224BASEID,RTL8224TOPDEVAD,RTL8373_P0_PTP_PORTID_ADDR(port), ptp_portino); +} + +/* Function Name: + * phy_8224_ptp_phyidtoptpid_get + * Description: + * Get Packet TX port ID.. + * Input: + * port - port id + * TxImbal - TX timer value compensation + * RxImbal - RX timer value compensation + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * Note: + * unit: 1 ns + */ +ret_t phy_8224_ptp_phyidtoptpid_get(rtk_port_t port, rtk_port_t *pptp_portino) +{ + return rtk_port_phyReg_get(RTL8224PHYID,RTL8224TOPDEVAD,RTL8373_P0_PTP_PORTID_ADDR(port), pptp_portino); + +} +/* Function Name: + * phy_8224_ptp_PPSLatchTime_get + * Description: + * Set toddelay. + * Input: + * type - accessType + * Output: + * pLatchTime - latch time + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * Note: + * mac mode only + */ +ret_t phy_8224_ptp_PPSLatchTime_get( rtk_time_timeStamp_t *pLatchTime) +{ + ret_t ret = RT_ERR_OK; + rtk_uint32 sec_l = 0; + rtk_uint32 sec_m = 0; + rtk_uint32 sec_h = 0; + rtk_uint32 nsec_l = 0; + rtk_uint32 nsec_h = 0; + + if((ret = rtk_port_phyReg_get(RTL8224PHYID,RTL8224TOPDEVAD,RTL8373_PPS_IN_LATCH_TIME_SEC_H_ADDR, &sec_h)) != RT_ERR_OK) + return ret; + if((ret = rtk_port_phyReg_get(RTL8224PHYID,RTL8224TOPDEVAD,RTL8373_PPS_IN_LATCH_TIME_SEC_M_ADDR, &sec_m)) != RT_ERR_OK) + return ret; + if((ret = rtk_port_phyReg_get(RTL8224PHYID,RTL8224TOPDEVAD,RTL8373_PPS_IN_LATCH_TIME_SEC_L_ADDR, &sec_l)) != RT_ERR_OK) + return ret; + if((ret = rtk_port_phyReg_get(RTL8224PHYID,RTL8224TOPDEVAD,RTL8373_PPS_IN_LATCH_TIME_NSEC_H_ADDR, &nsec_h)) != RT_ERR_OK) + return ret; + if((ret = rtk_port_phyReg_get(RTL8224PHYID,RTL8224TOPDEVAD,RTL8373_PPS_IN_LATCH_TIME_NSEC_L_ADDR, &nsec_l)) != RT_ERR_OK) + return ret; + + pLatchTime->sec = ((rtk_uint64)sec_h << 32) | ((rtk_uint64)sec_m << 16) | ((rtk_uint64)sec_l & 0xFFFF); + pLatchTime->nsec = (((nsec_h & 0x3FFF) << 16) | (nsec_l & 0xFFFF)); + + + return ret; +} +/* Function Name: + * phy_8224_ptp_RefTimeFreqCfg_set + * Description: + * Set the frequency of reference time of PHY of the specified port. + * Input: + * freq - reference time frequency + * apply + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * Note: + * The frequency configuration decides the reference time tick frequency. + * The default value is 0x10000000. + * If it is configured to 0x8000000, the tick frequency would be half of default. + * If it is configured to 0x20000000, the tick frequency would be one and half times of default. + */ +ret_t phy_8224_ptp_RefTimeFreqCfg_set(rtk_uint32 freq, rtk_enable_t apply) +{ + ret_t ret; + + if((ret = rtk_port_phyReg_setBits(RTL8224BASEID,RTL8224TOPDEVAD,RTL8373_PTP_TIME_FREQ0_ADDR,RTL8373_PTP_TIME_FREQ0_CFG_PTP_TIME_FREQ0_MASK, freq&0xffff)) != RT_ERR_OK) + return ret; + if((ret = rtk_port_phyReg_setBits(RTL8224BASEID,RTL8224TOPDEVAD,RTL8373_PTP_TIME_FREQ1_ADDR,RTL8373_PTP_TIME_FREQ1_CFG_PTP_TIME_FREQ1_MASK, (freq>>16)&0xffff)) != RT_ERR_OK) + return ret; + if((ret = rtk_port_phyReg_set(RTL8224BASEID,RTL8224TOPDEVAD,RTL8373_PTP_APPLY_FREQ_ADDR,apply)) != RT_ERR_OK) + return ret; + + return RT_ERR_OK; +} + +/* Function Name: + * phy_8224_ptp_RefTimeFreqCfg_get + * Description: + * Set ptp_RefTimeFreqCfg_get. + * Input: + * None + * Output: + * cfgFreq + * curFreq + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * Note: + */ +ret_t phy_8224_ptp_RefTimeFreqCfg_get(rtk_uint32 *cfgFreq,rtk_uint32 *curFreq) +{ + rtk_uint32 freqtmp; + ret_t ret; + + if((ret = rtk_port_phyReg_getBits(RTL8224PHYID,RTL8224TOPDEVAD,RTL8373_PTP_TIME_FREQ0_ADDR,RTL8373_PTP_TIME_FREQ0_CFG_PTP_TIME_FREQ0_MASK, cfgFreq)) != RT_ERR_OK) + return ret; + if((ret = rtk_port_phyReg_getBits(RTL8224PHYID,RTL8224TOPDEVAD,RTL8373_PTP_TIME_FREQ1_ADDR,RTL8373_PTP_TIME_FREQ1_CFG_PTP_TIME_FREQ1_MASK, &freqtmp)) != RT_ERR_OK) + return ret; + *cfgFreq|=(freqtmp<<16); + + if((ret = rtk_port_phyReg_getBits(RTL8224PHYID,RTL8224TOPDEVAD,RTL8373_PTP_CUR_TIME_FREQ0_ADDR,RTL8373_PTP_CUR_TIME_FREQ0_CUR_PTP_TIME_FREQ0_MASK, curFreq)) != RT_ERR_OK) + return ret; + if((ret = rtk_port_phyReg_getBits(RTL8224PHYID,RTL8224TOPDEVAD,RTL8373_PTP_CUR_TIME_FREQ1_ADDR,RTL8373_PTP_CUR_TIME_FREQ1_CUR_PTP_TIME_FREQ1_MASK, &freqtmp)) != RT_ERR_OK) + return ret; + *curFreq|=(freqtmp<<16); + + return RT_ERR_OK; +} + + +/* Function Name: + * phy_8224_ptp_ClkSrcCtrl_set + * Description: + * Set PTP time Clock source selection + * Input: + * clksrc + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * 0: internal clock (Internal PLL, 1GMHz) + * 1: external clock, refer to cfg_ext_clk_src) + */ +ret_t phy_8224_ptp_ClkSrcCtrl_set(rtk_uint32 clksrc) +{ + if (clksrc>1) + return RT_ERR_INPUT; + + return rtk_port_phyReg_setBits(RTL8224BASEID,RTL8224TOPDEVAD,RTL8373_PTP_CLK_SRC_CTRL_ADDR, RTL8373_PTP_CLK_SRC_CTRL_CFG_CLK_SRC_MASK, clksrc); + +} + +/* Function Name: + * phy_8224_ptp_ClkSrcCtrl_set + * Description: + * Set PTP time Clock source selection + * Input: + * clksrc + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * 0: internal clock (Internal PLL, 1GMHz) + * 1: external clock, refer to cfg_ext_clk_src) + */ +ret_t phy_8224_ptp_ClkSrcCtrl_get(rtk_uint32 *pclksrc) +{ + if (pclksrc==NULL) + return RT_ERR_INPUT; + + return rtk_port_phyReg_getBits(RTL8224BASEID,RTL8224TOPDEVAD,RTL8373_PTP_CLK_SRC_CTRL_ADDR, RTL8373_PTP_CLK_SRC_CTRL_CFG_CLK_SRC_MASK, pclksrc); + +} +/* Function Name: + * phy_8224drv_mapperInit + * Description: + * Initialize PHY 8224 driver. + * Input: + * pPhydrv - pointer of phy driver + * Output: + * None + * Return: + * None + * Note: + * None + */ + /* + * Data Declaration + */ +static rt_phydrv_t phy_8224drv_mapperInit = +{ + .fPhydrv_ptpRefTime_set = phy_8224_ptp_refTime_set, + .fPhydrv_PtpbypassptpEn_get = phy_8224_bypassptpEn_get, + .fPhydrv_PtpbypassptpEn_set = phy_8224_bypassptpEn_set, + + .fPhydrv_RefTimeAdjust_set = phy_8224_ptp_refTimeAdjust_set, + + .fPhydrv_PtpVlanTpid_get = phy_8224_ptp_tpid_get, + .fPhydrv_PtpVlanTpid_set = phy_8224_ptp_tpid_set, + .fPhydrv_PtpOper_get = phy_8224_ptp_Oper_get, + .fPhydrv_PtpOper_set = phy_8224_ptp_Oper_set, + .fPhydrv_PtpLatchTime_get = phy_8224_ptp_LatchTime_get, + .fPhydrv_PtpRefTimeFreqCfg_get = phy_8224_ptp_RefTimeFreqCfg_get, + .fPhydrv_PtpRefTimeFreqCfg_set = phy_8224_ptp_RefTimeFreqCfg_set, + .fPhydrv_PtpTxTimestampFifo_get = phy_8224_ptp_TxTimestampFifo_get , + .fPhydrv_Ptp1PPSOutput_get = phy_8224_ptp_1PPSOutput_get, + .fPhydrv_Ptp1PPSOutput_set = phy_8224_ptp_1PPSOutput_set, + .fPhydrv_PtpClockOutput_get = phy_8224_ptp_ClockOutput_get, + .fPhydrv_PtpClockOutput_set = phy_8224_ptp_ClockOutput_set, + + + .fPhydrv_PtpPortctrl_get = phy_8224_ptp_portctrl_get, + .fPhydrv_PtpPortctrl_set = phy_8224_ptp_portctrl_set, + +}; + +/* Function Name: + * phy_8224drv_mapper_get + * Description: + * Get DAL mapper function + * Input: + * None + * Output: + * None + * Return: + * dal_mapper_t * - mapper pointer + * Note: + */ +rt_phydrv_t *phy_8224drv_mapper_get(void) +{ + return &phy_8224drv_mapperInit; +} /* end of dal_rtl8371c_mapper_get */ + + diff --git a/sources/uboot-be550/drivers/net/rtl8372/phy_rtl8224.h b/sources/uboot-be550/drivers/net/rtl8372/phy_rtl8224.h new file mode 100755 index 00000000..f2588397 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/phy_rtl8224.h @@ -0,0 +1,687 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8367/RTL8367C switch high-level API + * + * Feature : The file includes time module high-layer API defination + * + */ + +#ifndef __RTK_PHY_PHY_RTL8224__H__ +#define __RTK_PHY_PHY_RTL8224__H__ + +#define PORT_NUM_IN_8224 (4) + +#define RTL8224TOPDEVAD (30) +#define RTL8224BASEID (0x1) +#define RTL8224PHYID (0x0) + + + +/* Function Name: + * phy_8224drv_mapper_get + * Description: + * Get DAL mapper function + * Input: + * None + * Output: + * None + * Return: + * dal_mapper_t * - mapper pointer + * Note: + */ +extern rt_phydrv_t *phy_8224drv_mapper_get(void); + +/* Function Name: + * phy_8224_ptp_portmask + * Description: + * PTP function initialization. + * Input: + * portmask range 0~0xf + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API is used to initialize PTP status. + */ +extern ret_t phy_8224_ptp_portmask(rtk_portmask_t portmask); +/* Function Name: + * phy_8224_ptp_init + * Description: + * PTP function initialization. + * Input: + * ptpinternalpmask port range 0~0xf + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API is used to initialize PTP status. + */ +extern ret_t phy_8224_ptp_init( rtk_portmask_t ptppmask); + +/* Function Name: + * dal_rtl8371c_bypassptpEn_get + * Description: + * Get PTP status of the specified port. + * Input: + * port - port id + * Output: + * pEnable - status + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT - invalid port id + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None + */ +extern ret_t phy_8224_bypassptpEn_get( rtk_port_t port, rtk_enable_t *pEnable); + + +/* Function Name: + * phy_8224_bypassptpEn_set + * Description: + * Get PTP status of the specified port. + * Input: + * port - port id + * pEnable - status + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT - invalid port id + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None + */ +extern ret_t phy_8224_bypassptpEn_set( rtk_port_t port, rtk_enable_t pEnable); + +/* Function Name: + * phy_8224_ptpEn_get + * Description: + * Get PTP status of the specified port. + * Input: + * port - port id + * Output: + * pEnable - status + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT - invalid port id + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None + */ +extern ret_t phy_8224_ptpEn_get( rtk_port_t port, rtk_ptp_header_t type,rtk_enable_t *pEnable); + + +/* Function Name: + * phy_8224_ptpEn_get + * Description: + * Get PTP status of the specified port. + * Input: + * port - port id + * Output: + * pEnable - status + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT - invalid port id + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None + */ +extern ret_t phy_8224_ptpEn_set( rtk_port_t port, rtk_ptp_header_t type,rtk_enable_t pEnable); + +/* Function Name: + * phy_8224_ptp_tpid_set + * Description: + * Configure PTP accepted outer & inner tag TPID. + * Input: + * outerId - Ether type of S-tag frame parsing in PTP ports. + * innerId - Ether type of C-tag frame parsing in PTP ports. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * Note: + * None + */ +extern ret_t phy_8224_ptp_tpid_set(rtk_vlanType_t type, rtk_uint32 idx, rtk_uint32 Tpid); + +/* Function Name: + * phy_8224_ptp_tpid_get + * Description: + * Get PTP accepted outer or inner tag TPID. + * Input: + * type + * idx + * Output: + * pTpid - Ether type of tag frame parsing in PTP ports. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * None + */ +extern ret_t phy_8224_ptp_tpid_get(rtk_vlanType_t type, rtk_uint32 idx, rtk_uint32 *pTpid); + +/* Function Name: + * phy_8224_ptp_Oper_get + * Description: + * Get the PTP time operation configuration of specific port. + * Input: + * port - port ID + * Output: + * pOperCfg - pointer to PTP time operation configuraton + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None + */ +extern ret_t phy_8224_ptp_Oper_get(rtk_time_operCfg_t *pOperCfg); + +/* Function Name: + * phy_8224_ptp_Oper_set + * Description: + * Set the PTP time operation configuration of specific port. + * Input: + * port - port ID + * pOperCfg - pointer to PTP time operation configuraton + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None + */ +extern ret_t phy_8224_ptp_Oper_set( rtk_time_operCfg_t pOperCfg); + +/* Function Name: + * dal_rtl8371c_ptp_LatchTime_get + * Description: + * Get the PTP latched time of specific port by hardware. + * Input: + * Output: + * pLatchTime - pointer to PTP time operation configuraton + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None + */ +extern ret_t phy_8224_ptp_LatchTime_get( rtk_time_timeStamp_t *pLatchTime); + +/* Function Name: + * phy_8224_ptp_refTimeOp_set + * Description: + * Set the reference time of the specified device. + * Input: + * extoption - reference timestamp value + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT - invalid input parameter + * Applicable: + * Note: + * need gpio triger + */ +extern ret_t phy_8224_ptp_refTimeOp_set(rtk_uint32 extoption); + +/* Function Name: + * dal_rtl8371c_ptp_refTime_set + * Description: + * Set the reference time of the specified device. + * Input: + * type + * timeStamp - reference timestamp value + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT - invalid input parameter + * Applicable: + * Note: + * need gpio triger + */ +extern ret_t phy_8224_ptp_refTime_set(rtk_time_timeStamp_t timeStamp); + + +/* Function Name: + * phy_8224_ptp_refTime_get + * Description: + * Get the reference time of the specified device by software. + * Input: + * Output: + * pTimeStamp - pointer buffer of the reference time + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Applicable: + * 8371 + * Note: + * need gpio triger + */ +extern ret_t phy_8224_ptp_refTime_get(rtk_time_timeStamp_t *pTimeStamp); + +/* Function Name: + * phy_8224_ptp_refTimeAdjust_set + * Description: + * Adjust the reference time. + * Input: + * sign - significant + * timeStamp - reference timestamp value + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Note: + * sign=0 for positive adjustment, sign=1 for negative adjustment. + */ +extern ret_t phy_8224_ptp_refTimeAdjust_set( rtk_ptp_sys_adjust_t sign, rtk_time_timeStamp_t timeStamp); + +/* Function Name: + * phy_8224_ptp_TxTimestampFifo_get + * Description: + * Get the top entry from PTP Tx timstamp FIFO on the dedicated port from the specified device. + * Input: + * port - port id + * Output: + * pTimeEntry - pointer buffer of TIME timestamp entry + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None + */ +extern ret_t phy_8224_ptp_TxTimestampFifo_get(rtk_time_txTimeEntry_t *pTimeEntry); + +/* Function Name: + * phy_8224_ptp_1PPSOutput_get + * Description: + * Get 1 PPS output configuration of the specified port. + * Input: + * type - phy or mac + * Output: + * pPulseWidth - pointer to 1 PPS pulse width, unit: 10 ms + * pEnable - pointer to 1 PPS output enable status + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None + */ +extern ret_t phy_8224_ptp_1PPSOutput_get( rtk_uint32 *pPulseWidth, rtk_enable_t *pEnable); + +/* Function Name: + * phy_8224_ptp_1PPSOutput_set + * Description: + * Set 1 PPS output configuration of the specified port. + * Input: + * type - phy or mac + * pulseWidth - pointer to 1 PPS pulse width, unit: 10 ms + * enable - enable 1 PPS output + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * Note: + * None + */ +extern ret_t phy_8224_ptp_1PPSOutput_set( rtk_uint32 pulseWidth, rtk_enable_t enable); + +/* Function Name: + * phy_8224_ptp_1PPSOutput_set + * Description: + * Set 1 PPS output configuration of the specified port. + * Input: + * type - phy or mac + * pulseWidth - pointer to 1 PPS pulse width, unit: 10 ms + * enable - enable 1 PPS output + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * Note: + * None + */ +extern ret_t phy_8224_ptp_1PPSOutput_set( rtk_uint32 pulseWidth, rtk_enable_t enable); + +/* Function Name: + * phy_8224_ptp_ClockOutput_get + * Description: + * Get clock output configuration of the specified port. + * Input: + * pClkOutput -pClkOutput + * Output: + * pClkOutput - pointer to clock output configuration + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None + */ +extern ret_t phy_8224_ptp_ClockOutput_get( rtk_time_clkOutput_t *pClkOutput); + +/* Function Name: + * phy_8224_ptp_ClockOutput_set + * Description: + * Set 1 PPS output configuration of the specified port. + * Input: +* type - phy or mac + * pClkOutput - pointer to clock output configuration + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * Note: + * None + */ +extern ret_t phy_8224_ptp_ClockOutput_set( rtk_time_clkOutput_t pClkOutput); + +/* Function Name: + * phy_8224_ptp_portctrl_set + * Description: + * Get enable status for PTP transparent clock of the specified port. + * Input: + * port - port id + * portcfg -port role/udp_en/eth_en/always_ts + * Output: + * + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None + */ +extern ret_t phy_8224_ptp_portctrl_set( rtk_port_t port, rtk_ptp_port_ctrl_t portcfg); + +/* Function Name: + * phy_8224_ptp_portctrl_get + * Description: + * Get enable status for PTP transparent clock of the specified port. + * Input: + * port - port id + * Output: + * portcfg -port role/udp_en/eth_en/always_ts + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None + */ +extern ret_t phy_8224_ptp_portctrl_get( rtk_port_t port, rtk_ptp_port_ctrl_t *pportcfg); + +/* Function Name: + * phy_8224_ptp_TxImbal_set + * Description: + * Set TX/RX timer value compensation.. + * Input: + * port - port id + * TxImbal - TX timer value compensation + * RxImbal - RX timer value compensation + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * Note: + * unit: 1 ns + */ +extern ret_t phy_8224_ptp_TxImbal_set(rtk_port_t port, rtk_uint32 TxImbal,rtk_uint32 RxImbal); + +/* Function Name: + * phy_8224_ptp_TxImbal_get + * Description: + * Get TX/RX timer value compensation.. + * Input: + * port - port id + * PTxImbal - TX timer value compensation + * pRxImbal - RX timer value compensation + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * Note: + * unit: 1 ns + */ +extern ret_t phy_8224_ptp_TxImbal_get(rtk_port_t port, rtk_uint32 *pTxImbal,rtk_uint32 *pRxImbal); + +/* Function Name: + * phy_8224_ptp_phyidtoportid_set + * Description: + * Set Packet TX port ID.. + * Input: + * port - port id + * ptp_portino - TX timer value compensation + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * Note: + * unit: 1 ns + */ +extern ret_t phy_8224_ptp_phyidtoportid_set(rtk_port_t port, rtk_port_t ptp_portino); + +/* Function Name: + * phy_8224_ptp_phyidtoptpid_get + * Description: + * Get Packet TX port ID.. + * Input: + * port - port id + * TxImbal - TX timer value compensation + * RxImbal - RX timer value compensation + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * Note: + * unit: 1 ns + */ +extern ret_t phy_8224_ptp_phyidtoptpid_get(rtk_port_t port, rtk_port_t *pptp_portino); + +/* Function Name: + * phy_8224_ptp_PPSLatchTime_get + * Description: + * Set toddelay. + * Input: + * type - accessType + * Output: + * pLatchTime - latch time + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * Note: + * mac mode only + */ +extern ret_t phy_8224_ptp_PPSLatchTime_get( rtk_time_timeStamp_t *pLatchTime); + +/* Function Name: + * phy_8224_ptp_RefTimeFreqCfg_set + * Description: + * Set the frequency of reference time of PHY of the specified port. + * Input: + * freq - reference time frequency + * apply + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * Note: + * The frequency configuration decides the reference time tick frequency. + * The default value is 0x10000000. + * If it is configured to 0x8000000, the tick frequency would be half of default. + * If it is configured to 0x20000000, the tick frequency would be one and half times of default. + */ +extern ret_t phy_8224_ptp_RefTimeFreqCfg_set(rtk_uint32 freq, rtk_enable_t apply); + +/* Function Name: + * phy_8224_ptp_RefTimeFreqCfg_get + * Description: + * Set ptp_RefTimeFreqCfg_get. + * Input: + * None + * Output: + * cfgFreq + * curFreq + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * Note: + */ +extern ret_t phy_8224_ptp_RefTimeFreqCfg_get(rtk_uint32 *cfgFreq,rtk_uint32 *curFreq); + +/* Function Name: + * phy_8224_ptp_ClkSrcCtrl_set + * Description: + * Set PTP time Clock source selection + * Input: + * clksrc + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * 0: internal clock (Internal PLL, 1GMHz) + * 1: external clock, refer to cfg_ext_clk_src) + */ +extern ret_t phy_8224_ptp_ClkSrcCtrl_set(rtk_uint32 clksrc); + + + +/* Function Name: + * phy_8224_ptp_ClkSrcCtrl_set + * Description: + * Set PTP time Clock source selection + * Input: + * clksrc + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * 0: internal clock (Internal PLL, 1GMHz) + * 1: external clock, refer to cfg_ext_clk_src) + */ +extern ret_t phy_8224_ptp_ClkSrcCtrl_get(rtk_uint32 *pclksrc); +#endif diff --git a/sources/uboot-be550/drivers/net/rtl8372/phydef.h b/sources/uboot-be550/drivers/net/rtl8372/phydef.h new file mode 100755 index 00000000..730b13dd --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/phydef.h @@ -0,0 +1,106 @@ +/* + * Copyright (C) 2009-2016 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : PHY symbol and data type definition in the SDK. + * + * Feature : PHY symbol and data type definition + * + */ + +#ifndef __HAL_PHY_PHYDEF_H__ +#define __HAL_PHY_PHYDEF_H__ +#include "ptp.h" +/* definition phy driver structure */ +typedef struct rt_phydrv_s +{ + rtk_int32 phydrv_index; + ret_t (*fPhydrv_init)(rtk_port_t); + + ret_t (*fPhydrv_ptpRefTime_get)(rtk_time_timeStamp_t *); + ret_t (*fPhydrv_ptpRefTime_set)(rtk_time_timeStamp_t); + ret_t (*fPhydrv_PtpbypassptpEn_get)(rtk_port_t , rtk_enable_t *); + ret_t (*fPhydrv_PtpbypassptpEn_set)(rtk_port_t , rtk_enable_t ); + ret_t (*fPhydrv_PtpEnable_get)(rtk_port_t ,rtk_ptp_header_t, rtk_enable_t *); + ret_t (*fPhydrv_PtpEnable_set)(rtk_port_t ,rtk_ptp_header_t,rtk_enable_t ); + ret_t (*fPhydrv_RefTimeAdjust_set)( rtk_uint32 , rtk_time_timeStamp_t ); + ret_t (*fPhydrv_RefTimeEnable_get)( rtk_enable_t *); + ret_t (*fPhydrv_RefTimeEnable_set)( rtk_enable_t ); + + ret_t (*fPhydrv_PtpVlanTpid_get)( rtk_vlanType_t , rtk_uint32 , rtk_uint32 *); + ret_t (*fPhydrv_PtpVlanTpid_set)(rtk_vlanType_t , rtk_uint32 , rtk_uint32 ); + ret_t (*fPhydrv_PtpOper_get)(rtk_time_operCfg_t *); + ret_t (*fPhydrv_PtpOper_set)( rtk_time_operCfg_t ); + ret_t (*fPhydrv_PtpLatchTime_get)( rtk_time_timeStamp_t *); + ret_t (*fPhydrv_PtpRefTimeFreqCfg_get)(rtk_uint32 *, rtk_uint32 *); + ret_t (*fPhydrv_PtpRefTimeFreqCfg_set)(rtk_uint32, rtk_enable_t); + ret_t (*fPhydrv_PtpTxInterruptStatus_get)( rtk_uint32 *); + ret_t (*fPhydrv_PtpTxTimestampFifo_get)(rtk_time_txTimeEntry_t *); + ret_t (*fPhydrv_Ptp1PPSOutput_get)(rtk_uint32 *, rtk_enable_t *); + ret_t (*fPhydrv_Ptp1PPSOutput_set)( rtk_uint32, rtk_enable_t); + ret_t (*fPhydrv_PtpClockOutput_get)( rtk_time_clkOutput_t*); + ret_t (*fPhydrv_PtpClockOutput_set)( rtk_time_clkOutput_t ); + ret_t (*fPhydrv_PtpToddelay_get)( rtk_uint32 *); + ret_t (*fPhydrv_PtpToddelay_set)( rtk_uint32 ); + ret_t (*fPhydrv_PtpOutputSigSel_get)( rtk_time_outSigSel_t *); + ret_t (*fPhydrv_PtpOutputSigSel_set)( rtk_time_outSigSel_t); + ret_t (*fPhydrv_PtpPortctrl_get)( rtk_port_t, rtk_ptp_port_ctrl_t*); + ret_t (*fPhydrv_PtpPortctrl_set)(rtk_port_t, rtk_ptp_port_ctrl_t); +} rt_phydrv_t; + +typedef ret_t (*phy_ident_f)( rtk_uint32 model_id, rtk_uint32 rev_id); + +//typedef void (*fPhydrv_mapperInit_f)(rt_phydrv_t* pPhydrv); +typedef rt_phydrv_t *(*fPhydrv_mapperInit_f)(void); + +/* Definition family ID */ +#define RTL8371_FAMILY_ID (0x83710000) +#define RTK_PHYINFO_FLAG_NONE (0x0) +#define PHY_MODEL_ID_NULL (0x0) +typedef enum phy_type_e { + RTK_PHYTYPE_NONE = 0, /* no phy connected */ + RTK_PHYTYPE_RTL8224, + RTK_PHYTYPE_RTL8221B, + RTK_PHYTYPE_RTL8218E, + RTK_PHYTYPE_SERDES, + RTK_PHYTYPE_UNKNOWN, /* phy connected, but unknown type */ + RTK_PHYTYPE_INVALID, /* somehting wrong in hardware profile */ + RTK_PHYTYPE_END, +} phy_type_t_rtl8372; + +/* enum for supported phy driver */ +typedef enum rt_supported_phydrv_e +{ + RT_PHYDRV_RTL8224, + RT_PHYDRV_END +} rt_supported_phydrv_t; +typedef struct rt_phyInfo_s +{ + rtk_uint32 phy_num; /* PHY number in the chip, like 8218 is 8, 8224C is 4 */ + rtk_uint32 eth_type; /* PHY speed*/ +} rt_phyInfo_t; + +/* definition phy control structure */ +typedef struct rt_phyctrl_s +{ + phy_ident_f chk_func; + rtk_uint32 phy_model_id; + rtk_uint32 phy_rev_id; + phy_type_t_rtl8372 phyType; + rt_phydrv_t *pPhydrv; + fPhydrv_mapperInit_f mapperInit_func; + rtk_uint32 drv_rev_id; + rt_phyInfo_t *pPhyInfo; +} rt_phyctrl_t; + +#endif diff --git a/sources/uboot-be550/drivers/net/rtl8372/port.c b/sources/uboot-be550/drivers/net/rtl8372/port.c new file mode 100755 index 00000000..d9b7fe26 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/port.c @@ -0,0 +1,575 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8373 + * Feature : Here is a list of all functions and variables in port module. + * + */ + +#include +#include +#include +#include +#include +#include + + +/* Function Name: + * rtk_port_phyReg_set + * Description: + * Configure phy register data. + * Input: + * phy_mask - phy mask, bit[0:9] + * dev_addr - device address + * reg_addr - register address + * indata - input data + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure phy register data. + */ +rtk_api_ret_t rtk_port_phyReg_set(rtk_uint32 phy_mask, rtk_uint32 dev_addr, rtk_uint32 reg_addr, rtk_uint32 indata) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->fMdrv_miim_mmd_write) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->fMdrv_miim_mmd_write(phy_mask,dev_addr,reg_addr,indata); + RTK_API_UNLOCK(); + + return retVal; + +} + +/* Function Name: + * rtk_port_phyReg_get + * Description: + * Configure phy register data. + * Input: + * phy_id - phy id + * dev_addr - device address + * reg_addr - register address + * indata - input data + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure phy register data. + */ + +rtk_api_ret_t rtk_port_phyReg_get(rtk_uint32 phy_id, rtk_uint32 dev_addr, rtk_uint32 reg_addr, rtk_uint32 *pdata) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->fMdrv_miim_mmd_read) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->fMdrv_miim_mmd_read(phy_id,dev_addr,reg_addr,pdata); + RTK_API_UNLOCK(); + + return retVal; + +} + +/* Function Name: + * rtk_port_phyReg_getBits + * Description: + * Configure phy register data. + * Input: + * phy_id - phy id + * dev_addr - device address + * reg_addr - register address + * indata - input data + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure phy register data. + */ + +rtk_api_ret_t rtk_port_phyReg_getBits(rtk_uint32 phy_id, rtk_uint32 dev_addr, rtk_uint32 reg_addr, rtk_uint32 bitsMask,rtk_uint32 *pdata) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->fMdrv_miim_mmd_readbits) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->fMdrv_miim_mmd_readbits(phy_id,dev_addr,reg_addr,bitsMask,pdata); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_port_phyReg_setBits + * Description: + * Configure phy register data. + * Input: + * phy_mask - phy mask, bit[0:9] + * dev_addr - device address + * reg_addr - register address + * indata - input data + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure phy register data. + */ + +rtk_api_ret_t rtk_port_phyReg_setBits(rtk_uint32 phy_mask, rtk_uint32 dev_addr, rtk_uint32 reg_addr, rtk_uint32 bitsMask,rtk_uint32 indata) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->fMdrv_miim_mmd_writebits) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->fMdrv_miim_mmd_writebits(phy_mask,dev_addr,reg_addr,bitsMask,indata); + RTK_API_UNLOCK(); + + return retVal; + +} + + +/* Function Name: + * rtk_port_macForceLink_set + * Description: + * Set port force linking configuration. + * Input: + * port - port id. + * pPortability - port ability configuration + * 0x0: 10Mbps; + * 0x1: 100Mbps; + * 0x2: 1000Mbps; + * 0x3: 500Mbps; + * 0x4: 10Gbps; + * 0x5: 2.5Gbps; + * 0x6: 5Gbps; + * 0x7: two_pair 1Gbps; + * 0x8: two_pair 2.5Gbps; + * 0x9: two_pair 5Gbps; + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can set Port/MAC force mode properties. + */ +rtk_api_ret_t rtk_port_macForceLink_set(rtk_port_t port, rtk_port_ability_t *pPortability) +{ + rtk_api_ret_t retVal; + if (NULL == RT_MAPPER->port_macForceLink_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->port_macForceLink_set(port, pPortability); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_port_macForceLink_get + * Description: + * Get port force linking configuration. + * Input: + * port - Port id. + * Output: + * pPortability - port ability configuration + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can get Port/MAC force mode properties. + */ +rtk_api_ret_t rtk_port_macForceLink_get(rtk_port_t port, rtk_port_ability_t *pPortability) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->port_macForceLink_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->port_macForceLink_get(port, pPortability); + RTK_API_UNLOCK(); + + return retVal; +} + + +/* Function Name: + * rtk_port_macStatus_get + * Description: + * Get port link status. + * Input: + * port - Port id. + * Output: + * pPortstatus - port ability configuration + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can get Port/PHY properties. + */ +rtk_api_ret_t rtk_port_macStatus_get(rtk_port_t port, rtk_port_status_t *pPortstatus) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->port_macStatus_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->port_macStatus_get(port, pPortstatus); + RTK_API_UNLOCK(); + + return retVal; +} + + +/* Function Name: + * rtk_port_macLocalLoopbackEnable_set + * Description: + * Set Port Local Loopback. (Redirect TX to RX.) + * Input: + * port - Port id. + * enable - Loopback state, 0:disable, 1:enable + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can enable/disable Local loopback in MAC. + * For UTP port, This API will also enable the digital + * loopback bit in PHY register for sync of speed between + * PHY and MAC. For EXT port, users need to force the + * link state by themself. + */ +rtk_api_ret_t rtk_port_macLocalLoopbackEnable_set(rtk_port_t port, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->port_macLocalLoopbackEnable_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->port_macLocalLoopbackEnable_set(port, enable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_port_macLocalLoopbackEnable_get + * Description: + * Get Port Local Loopback. (Redirect TX to RX.) + * Input: + * port - Port id. + * Output: + * pEnable - Loopback state, 0:disable, 1:enable + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * None. + */ +rtk_api_ret_t rtk_port_macLocalLoopbackEnable_get(rtk_port_t port, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->port_macLocalLoopbackEnable_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->port_macLocalLoopbackEnable_get(port, pEnable); + RTK_API_UNLOCK(); + + return retVal; +} + + +/* Function Name: + * rtk_port_backpressureEnable_set + * Description: + * Set the half duplex backpressure enable status of the specific port. + * Input: + * port - port id. + * enable - Back pressure status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * This API can set the half duplex backpressure enable status of the specific port. + * The half duplex backpressure enable status of the port is as following: + * - DISABLE(Defer) + * - ENABLE (Backpressure) + */ +rtk_api_ret_t rtk_port_backpressureEnable_set(rtk_port_t port, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->port_backpressureEnable_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->port_backpressureEnable_set(port, enable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_port_backpressureEnable_get + * Description: + * Get the half duplex backpressure enable status of the specific port. + * Input: + * port - Port id. + * Output: + * pEnable - Back pressure status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can get the half duplex backpressure enable status of the specific port. + * The half duplex backpressure enable status of the port is as following: + * - DISABLE(Defer) + * - ENABLE (Backpressure) + */ +rtk_api_ret_t rtk_port_backpressureEnable_get(rtk_port_t port, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->port_backpressureEnable_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->port_backpressureEnable_get(port, pEnable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_port_rtctEnable_set + * Description: + * Enable RTCT test + * Input: + * portmask - Port mask of RTCT enabled port + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Invalid port mask. + * Note: + * The API can enable RTCT Test + */ +rtk_api_ret_t rtk_port_rtctEnable_set(rtk_uint32 portmask) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->port_rtct_start) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->port_rtct_start(portmask); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_port_rtct_init + * Description: + * Init RTCT test + * Input: + * pPortmask - Port mask of RTCT disabled port + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Invalid port mask. + * Note: + * The API can disable RTCT Test + */ +rtk_api_ret_t rtk_port_rtct_init(void) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->port_rtct_init) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->port_rtct_init(); + RTK_API_UNLOCK(); + + return retVal; +} + + + +/* Function Name: + * rtk_port_rtctResult_get + * Description: + * Get the result of RTCT test + * Input: + * port - Port ID + * Output: + * pRtctResult - The result of RTCT result + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port ID. + * RT_ERR_PHY_RTCT_NOT_FINISH - Testing does not finish. + * Note: + * The API can get RTCT test result. + * RTCT test may takes 4.8 seconds to finish its test at most. + * Thus, if this API return RT_ERR_PHY_RTCT_NOT_FINISH or + * other error code, the result can not be referenced and + * user should call this API again until this API returns + * a RT_ERR_OK. + * The result is stored at pRtctResult->ge_result + * pRtctResult->linkType is unused. + * The unit of channel length is 2.5cm. Ex. 300 means 300 * 2.5 = 750cm = 7.5M + */ +rtk_api_ret_t rtk_port_rtctResult_get(rtk_port_t port, rtk_rtct_result_t *pRtctResult) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->port_rtctResult_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->port_rtctResult_get(port, pRtctResult); + RTK_API_UNLOCK(); + + return retVal; +} + + + +/* Function Name: + * rtk_sdsMode_get + * Description: + * Get sds mode + * Input: + * sdsId - serdes ID,0-1 + * pSdsMode - serdes Mode + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port ID. + * RT_ERR_PHY_RTCT_NOT_FINISH - Testing does not finish. + * Note: + */ +rtk_api_ret_t rtk_sdsMode_get(rtk_uint32 sdsId, rtk_sds_mode_t *pSdsMode) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->port_sdsMode_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->port_sdsMode_get(sdsId, pSdsMode); + RTK_API_UNLOCK(); + + return retVal; +} + + +/* Function Name: + * rtk_sdsMode_set + * Description: + * Set sds mode + * Input: + * sdsId - serdes ID,0-1 + * sdsMode - serdes Mode + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port ID. + * RT_ERR_PHY_RTCT_NOT_FINISH - Testing does not finish. + * Note: + */ +rtk_api_ret_t rtk_sdsMode_set(rtk_uint32 sdsId, rtk_sds_mode_t sdsMode) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->port_sdsMode_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->port_sdsMode_set(sdsId, sdsMode); + RTK_API_UNLOCK(); + + return retVal; +} + + + diff --git a/sources/uboot-be550/drivers/net/rtl8372/port.h b/sources/uboot-be550/drivers/net/rtl8372/port.h new file mode 100755 index 00000000..f603e7b1 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/port.h @@ -0,0 +1,483 @@ + /* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8373 switch high-level API + * + * Feature : The file includes QoS module high-layer API defination + * + */ + +#ifndef __RTK_API_PORT_H__ +#define __RTK_API_PORT_H__ + +typedef enum rtk_port_speed_e +{ + PORT_SPEED_10M = 0, + PORT_SPEED_100M, + PORT_SPEED_1000M, + PORT_SPEED_500M, + PORT_SPEED_10G, + PORT_SPEED_2500M, + PORT_SPEED_5G, + PORT_SPEED_END +} rtk_port_speed_t; + +typedef enum rtk_port_duplex_e +{ + PORT_HALF_DUPLEX = 0, + PORT_FULL_DUPLEX, + PORT_DUPLEX_END +} rtk_port_duplex_t; + +typedef enum rtk_port_linkStatus_e +{ + PORT_LINKDOWN = 0, + PORT_LINKUP, + PORT_LINKSTATUS_END +} rtk_port_linkStatus_t; + +typedef enum rtk_port_media_e +{ + PORT_MEDIA_UTP = 0, + PORT_MEDIA_FIBER, + PORT_MEDIA_END +}rtk_port_media_t; + +typedef enum rtk_sds_mode_e +{ + SERDES_10GQXG, + SERDES_10GUSXG = 0xD, + SERDES_10GR = 0x1A, + SERDES_HSG = 0x12, + SERDES_2500BASEX = 0x16, + SERDES_SG = 2, + SERDES_1000BASEX = 4, + SERDES_100FX = 5, + SERDES_OFF = 0x1F, + SERDES_8221B = 0x21, + SERDES_END +}rtk_sds_mode_t; + +typedef struct rtk_port_ability_s{ + rtk_enable_t forcemode; + rtk_enable_t txpause; + rtk_enable_t rxpause; + rtk_port_linkStatus_t link; + rtk_port_duplex_t duplex; + rtk_port_speed_t speed; + rtk_port_media_t media; + rtk_enable_t smi_force_fc; +}rtk_port_ability_t; + + + +typedef struct rtk_port_status_s{ + rtk_uint32 txpause; + rtk_uint32 rxpause; + rtk_uint32 link; + rtk_uint32 duplex; + rtk_uint32 speed; + rtk_uint32 media; + rtk_uint32 eee; + rtk_uint32 master; + rtk_uint32 master_slave; + +}rtk_port_status_t; + + +typedef struct rtct_result_s +{ + rtk_uint32 channelABusy; + rtk_uint32 channelBBusy; + rtk_uint32 channelCBusy; + rtk_uint32 channelDBusy; + + rtk_uint32 channelAMisOpen; + rtk_uint32 channelBMisOpen; + rtk_uint32 channelCMisOpen; + rtk_uint32 channelDMisOpen; + + rtk_uint32 channelAMisShort; + rtk_uint32 channelBMisShort; + rtk_uint32 channelCMisShort; + rtk_uint32 channelDMisShort; + + rtk_uint32 channelAOpen; + rtk_uint32 channelBOpen; + rtk_uint32 channelCOpen; + rtk_uint32 channelDOpen; + + rtk_uint32 channelAShort; + rtk_uint32 channelBShort; + rtk_uint32 channelCShort; + rtk_uint32 channelDShort; + + rtk_uint32 channelANormal; + rtk_uint32 channelBNormal; + rtk_uint32 channelCNormal; + rtk_uint32 channelDNormal; + + rtk_uint32 channelADone; + rtk_uint32 channelBDone; + rtk_uint32 channelCDone; + rtk_uint32 channelDDone; + + rtk_uint32 channelAInterShort; + rtk_uint32 channelBInterShort; + rtk_uint32 channelCInterShort; + rtk_uint32 channelDInterShort; +} rtk_rtct_result_t; + + +/* Function Name: + * rtk_setAsicPHYReg + * Description: + * Configure phy register data. + * Input: + * phy_mask - phy mask, bit[0:9] + * dev_addr - device address + * reg_addr - register address + * indata - input data + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure phy register data. + */ +extern rtk_api_ret_t rtk_port_phyReg_set(rtk_uint32 phy_mask, rtk_uint32 dev_addr, rtk_uint32 reg_addr, rtk_uint32 indata); + +/* Function Name: + * rtk_getAsicPHYReg + * Description: + * Configure phy register data. + * Input: + * phy_mask - phy mask, bit[0:9] + * dev_addr - device address + * reg_addr - register address + * indata - input data + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure phy register data. + */ + +extern rtk_api_ret_t rtk_port_phyReg_get(rtk_uint32 phy_id, rtk_uint32 dev_addr, rtk_uint32 reg_addr, rtk_uint32 *pdata); + +/* Function Name: + * rtk_port_phyReg_getBits + * Description: + * Configure phy register data. + * Input: + * phy_mask - phy mask, bit[0:9] + * dev_addr - device address + * reg_addr - register address + * indata - input data + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure phy register data. + */ + +extern rtk_api_ret_t rtk_port_phyReg_getBits(rtk_uint32 phy_id, rtk_uint32 dev_addr, rtk_uint32 reg_addr, rtk_uint32 bitsMask,rtk_uint32 *pdata); + + +/* Function Name: + * rtk_port_phyReg_setBits + * Description: + * Configure phy register data. + * Input: + * phy_mask - phy mask, bit[0:9] + * dev_addr - device address + * reg_addr - register address + * indata - input data + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will configure phy register data. + */ + +extern rtk_api_ret_t rtk_port_phyReg_setBits(rtk_uint32 phy_mask, rtk_uint32 dev_addr, rtk_uint32 reg_addr, rtk_uint32 bitsMask,rtk_uint32 indata); + +/* Function Name: + * rtk_port_macForceLink_set + * Description: + * Set port force linking configuration. + * Input: + * port - port id. + * pPortability - port ability configuration + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can set Port/MAC force mode properties. + */ +extern rtk_api_ret_t rtk_port_macForceLink_set(rtk_port_t port, rtk_port_ability_t *pPortability); + + +/* Function Name: + * rtk_port_macForceLink_get + * Description: + * Get port force linking configuration. + * Input: + * port - Port id. + * Output: + * pPortability - port ability configuration + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can get Port/MAC force mode properties. + */ +extern rtk_api_ret_t rtk_port_macForceLink_get(rtk_port_t port, rtk_port_ability_t *pPortability); + + +/* Function Name: + * rtk_port_macStatus_get + * Description: + * Get port link status. + * Input: + * port - Port id. + * Output: + * pPortstatus - port ability configuration + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can get Port/PHY properties. + */ +extern rtk_api_ret_t rtk_port_macStatus_get(rtk_port_t port, rtk_port_status_t *pPortstatus); + + +/* Function Name: + * rtk_port_macLocalLoopbackEnable_set + * Description: + * Set Port Local Loopback. (Redirect TX to RX.) + * Input: + * port - Port id. + * enable - Loopback state, 0:disable, 1:enable + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can enable/disable Local loopback in MAC. + * For UTP port, This API will also enable the digital + * loopback bit in PHY register for sync of speed between + * PHY and MAC. For EXT port, users need to force the + * link state by themself. + */ +extern rtk_api_ret_t rtk_port_macLocalLoopbackEnable_set(rtk_port_t port, rtk_enable_t enable); + +/* Function Name: + * rtk_port_macLocalLoopbackEnable_get + * Description: + * Get Port Local Loopback. (Redirect TX to RX.) + * Input: + * port - Port id. + * Output: + * pEnable - Loopback state, 0:disable, 1:enable + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * None. + */ +extern rtk_api_ret_t rtk_port_macLocalLoopbackEnable_get(rtk_port_t port, rtk_enable_t *pEnable); + + +/* Function Name: + * rtk_port_backpressureEnable_set + * Description: + * Set the half duplex backpressure enable status of the specific port. + * Input: + * port - port id. + * enable - Back pressure status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * This API can set the half duplex backpressure enable status of the specific port. + * The half duplex backpressure enable status of the port is as following: + * - DISABLE(Defer) + * - ENABLE (Backpressure) + */ +extern rtk_api_ret_t rtk_port_backpressureEnable_set(rtk_port_t port, rtk_enable_t enable); + +/* Function Name: + * rtk_port_backpressureEnable_get + * Description: + * Get the half duplex backpressure enable status of the specific port. + * Input: + * port - Port id. + * Output: + * pEnable - Back pressure status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API can get the half duplex backpressure enable status of the specific port. + * The half duplex backpressure enable status of the port is as following: + * - DISABLE(Defer) + * - ENABLE (Backpressure) + */ +extern rtk_api_ret_t rtk_port_backpressureEnable_get(rtk_port_t port, rtk_enable_t *pEnable); + +/* Function Name: + * rtk_port_rtctEnable_set + * Description: + * Enable RTCT test + * Input: + * pPortmask - Port mask of RTCT enabled port + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Invalid port mask. + * Note: + * The API can enable RTCT Test + */ +extern rtk_api_ret_t rtk_port_rtctEnable_set(rtk_uint32 portmask); + +/* Function Name: + * rtk_port_rtct_init + * Description: + * Init RTCT test + * Input: + * pPortmask - Port mask of RTCT disabled port + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_MASK - Invalid port mask. + * Note: + * The API can disable RTCT Test + */ +extern rtk_api_ret_t rtk_port_rtct_init(void); + + +/* Function Name: + * rtk_port_rtctResult_get + * Description: + * Get the result of RTCT test + * Input: + * port - Port ID + * Output: + * pRtctResult - The result of RTCT result + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port ID. + * RT_ERR_PHY_RTCT_NOT_FINISH - Testing does not finish. + * Note: + * The API can get RTCT test result. + * RTCT test may takes 4.8 seconds to finish its test at most. + * Thus, if this API return RT_ERR_PHY_RTCT_NOT_FINISH or + * other error code, the result can not be referenced and + * user should call this API again until this API returns + * a RT_ERR_OK. + * The result is stored at pRtctResult->ge_result + * pRtctResult->linkType is unused. + * The unit of channel length is 2.5cm. Ex. 300 means 300 * 2.5 = 750cm = 7.5M + */ +extern rtk_api_ret_t rtk_port_rtctResult_get(rtk_port_t port, rtk_rtct_result_t *pRtctResult); + + +/* Function Name: + * rtk_sdsMode_get + * Description: + * Get sds mode + * Input: + * sdsId - serdes ID,0-1 + * pSdsMode - serdes Mode + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port ID. + * RT_ERR_PHY_RTCT_NOT_FINISH - Testing does not finish. + * Note: + */ +extern rtk_api_ret_t rtk_sdsMode_get(rtk_uint32 sdsId, rtk_sds_mode_t *pSdsMode); + + +/* Function Name: + * rtk_sdsMode_set + * Description: + * Set sds mode + * Input: + * sdsId - serdes ID,0-1 + * sdsMode - serdes Mode + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port ID. + * RT_ERR_PHY_RTCT_NOT_FINISH - Testing does not finish. + * Note: + */ +extern rtk_api_ret_t rtk_sdsMode_set(rtk_uint32 sdsId, rtk_sds_mode_t sdsMode); + + + +#endif \ No newline at end of file diff --git a/sources/uboot-be550/drivers/net/rtl8372/ptp.c b/sources/uboot-be550/drivers/net/rtl8372/ptp.c new file mode 100755 index 00000000..b3ae2612 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/ptp.c @@ -0,0 +1,1203 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision: 39583 $ + * $Date: 2013-05-20 16:59:23 +0800 (星期一, 20 五月 2013) $ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8367C + * Feature : Here is a list of all functions and variables in time module. + * + */ + +#include +#include +#include +#include +#include + +/* Function Name: + * rtk_ptp_init + * Description: + * PTP function initialization. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API is used to initialize PTP status. + */ +rtk_api_ret_t rtk_time_init(rtk_portmask_t ptpinternalpmask) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->time_init) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->time_init(ptpinternalpmask); + RTK_API_UNLOCK(); + + return retVal; +} +/* Function Name: + * rtk_time_portPtpbypassEnable_get + * Description: + * Get PTP status of the specified port. + * Input: + * port - port id + * Output: + * pEnable - status + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT - invalid port id + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Applicable: + * 8371 + * Note: + * None + * Changes: + * None + */ +rtk_api_ret_t rtk_time_portPtpbypassEnable_get(rtk_port_t port, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + if (NULL == RT_MAPPER->time_portPtpbypassptpEn_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->time_portPtpbypassptpEn_get(port, pEnable); + RTK_API_UNLOCK(); + return retVal; +} + +/* Function Name: + * rtk_time_portPtpbypassEnable_set + * Description: + * Set PTP status of the specified port. + * Input: + * port - port id + * enable - status + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT - invalid port id + * RT_ERR_INPUT - invalid input parameter + * Applicable: + * 8371 + * Note: + * None + * Changes: + * None + */ +rtk_api_ret_t rtk_time_portPtpbypassEnable_set(rtk_port_t port, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + if (NULL == RT_MAPPER->time_portPtpbypassptpEn_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->time_portPtpbypassptpEn_set(port, enable); + RTK_API_UNLOCK(); + return retVal; + +} /* end of rtk_time_portPtpEnable_set */ +/* Function Name: + * rtk_time_portPtpEnable_get + * Description: + * Get PTP status of the specified port. + * Input: + * port - port id + * type - PTP_ETH or UDP + * enable - status + * Output: + * pEnable - status + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT - invalid port id + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Applicable: + * + * Note: + * None + * Changes: + * None + */ +ret_t rtk_time_portPtpEnable_get( rtk_port_t port, rtk_ptp_header_t type,rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->time_portPtpEnable_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->time_portPtpEnable_get(port, type,pEnable); + RTK_API_UNLOCK(); + return retVal; +} +/* Function Name: + * rtk_time_portPtpEnable_set + * Description: + * Get PTP status of the specified port. + * Input: + * port - port id + * type - PTP_ETH or UDP + * enable - status + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT - invalid port id + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Applicable: + * + * Note: + * None + * Changes: + * None + */ +ret_t rtk_time_portPtpEnable_set( rtk_port_t port, rtk_ptp_header_t type,rtk_enable_t Enable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->time_portPtpEnable_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->time_portPtpEnable_set(port, type,Enable); + RTK_API_UNLOCK(); + return retVal; +} +/* Function Name: + * rtk_time_portRefTime_get + * Description: + * Get the reference time of the specified port. + * Input: + * port - port id, it should be base port of PHY + * Output: + * pTimeStamp - pointer buffer of the reference time + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Applicable: + * 8371 + * Note: + * None + * Changes: + * Add port parameter. + */ +rtk_api_ret_t rtk_time_portRefTime_get( rtk_time_timeStamp_t *pTimeStamp) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->time_portRefTime_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->time_portRefTime_get(pTimeStamp); + RTK_API_UNLOCK(); + return retVal; +} + + + +/* Function Name: + * rtk_time_portRefTime_set + * Description: + * Set the reference time of the specified portmask. + * Input: + * timeStamp - reference timestamp value + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Applicable: + * 8371 + * Note: + * None + * Changes: + * Add portmask parameter. + */ +rtk_api_ret_t rtk_time_portRefTime_set( rtk_time_timeStamp_t timeStamp,rtk_enable_t apply) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->time_portRefTime_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->time_portRefTime_set( timeStamp,apply); + RTK_API_UNLOCK(); + return retVal; + +} /* end of rtk_time_portRefTime_set */ + + +/* Function Name: + * rtk_time_portPtpOper_triger + * Description: + * Set the PTP time operation triger. + * Input: + * triType + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None + */ +rtk_api_ret_t rtk_time_portPtpOper_triger(void) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->time_portRefTime_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->time_portPtpOper_triger( ); + RTK_API_UNLOCK(); + return retVal; + +} +/* Function Name: + * rtk_time_portRefTimeAdjust_set + * Description: + * Adjust the reference time of portmask. + * Input: + * portmask - portmask, it should be base ports of PHYs + * sign - significant + * timeStamp - reference timestamp value + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Applicable: + * 8371 + * Note: + * sign=0 for positive adjustment, sign=1 for negative adjustment. + * Changes: + * Change name from rtk_time_refTimeAdjust_set. + * Add portmask parameter. + */ +rtk_api_ret_t rtk_time_portRefTimeAdjust_set(rtk_uint32 sign, rtk_time_timeStamp_t timeStamp, rtk_enable_t apply) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->time_portRefTimeAdjust_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->time_portRefTimeAdjust_set( sign, timeStamp, apply); + RTK_API_UNLOCK(); + return retVal; + +} /* end of rtk_time_refTimeAdjust_set */ + + +/* Function Name: + * rtk_time_portRefTimeEnable_get + * Description: + * Get the enable state of reference time of the specified port. + * Input: + * port - port id, it should be base port of PHY + * Output: + * pEnable - status + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Applicable: + * 8371 + * Note: + * None + * Changes: + * Change name from rtk_time_refTimeEnable_get. + * Add port parameter. + */ +rtk_api_ret_t rtk_time_portRefTimeEnable_get(rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->time_portRefTimeEnable_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->time_portRefTimeEnable_get(pEnable); + RTK_API_UNLOCK(); + return retVal; + +} /* end of rtk_time_portRefTimeEnable_get */ + + +/* Function Name: + * rtk_time_portRefTimeEnable_set + * Description: + * Set the enable state of reference time of the specified portmask. + * Input: + * portmask - portmask, it should be base ports of PHYs + * enable - status + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Applicable: + * 8371 + * Note: + * None + * Changes: + * Change name from rtk_time_refTimeEnable_set. + * Add portmask parameter. + */ +rtk_api_ret_t rtk_time_portRefTimeEnable_set( rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->time_portRefTimeEnable_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->time_portRefTimeEnable_set(enable); + RTK_API_UNLOCK(); + return retVal; + +} /* end of rtk_time_portRefTimeEnable_set */ + + + +/* Function Name: + * rtk_time_portPtpVlanTpid_get + * Description: + * Get the VLAN TPID of specific port. + * Input: + * port - port ID + * type - outer or inner VLAN + * idx - TPID entry index + * Output: + * pTpid - pointer to TPID + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None + * Changes: + * New added function. + */ +rtk_api_ret_t rtk_time_portPtpVlanTpid_get( rtk_vlanType_t type, rtk_uint32 idx, rtk_uint32 *pTpid) +{ + /* function body */ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->time_portPtpVlanTpid_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + /* function body */ + retVal = RT_MAPPER->time_portPtpVlanTpid_get( type, idx, pTpid); + RTK_API_UNLOCK(); + return retVal; +} /* end of rtk_time_portPtpVlanTpid_get */ + + +/* Function Name: + * rtk_time_portPtpVlanTpid_set + * Description: + * Set the VLAN TPID of specific port. + * Input: + * unit - unit id + * port - port ID + * type - outer or inner VLAN + * idx - TPID entry index + * tpid - VLAN TPID + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Applicable: + * 8371 + * Note: + * None + * Changes: + * New added function. + */ +rtk_api_ret_t rtk_time_portPtpVlanTpid_set( rtk_vlanType_t type, rtk_uint32 idx, rtk_uint32 tpid) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->time_portPtpVlanTpid_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + /* function body */ + retVal = RT_MAPPER->time_portPtpVlanTpid_set( type, idx, tpid); + RTK_API_UNLOCK(); + return retVal; + +} /* end of rtk_time_portPtpVlanTpid_get */ + +/* Function Name: + * rtk_time_portPtpOper_get + * Description: + * Get the PTP time operation configuration of specific port. + * Input: + * port - port ID + * Output: + * pOperCfg - pointer to PTP time operation configuraton + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Applicable: + * 8371 + * Note: + * None + * Changes: + * New added function. + */ +rtk_api_ret_t rtk_time_portPtpOper_get(rtk_time_operCfg_t *pOperCfg) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->time_portPtpOper_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + /* function body */ + retVal = RT_MAPPER->time_portPtpOper_get(pOperCfg); + RTK_API_UNLOCK(); + return retVal; + +} /* end of rtk_time_portPtpOper_get */ + + +/* Function Name: + * rtk_time_portPtpOper_set + * Description: + * Set the PTP time operation configuration of specific port. + * Input: + * port - port ID + * pOperCfg - pointer to PTP time operation configuraton + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Applicable: + * 8371 + * Note: + * None + * Changes: + * New added function. + */ +rtk_api_ret_t rtk_time_portPtpOper_set( rtk_time_operCfg_t pOperCfg) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->time_portPtpOper_set) + return RT_ERR_DRIVER_NOT_FOUND; + RTK_API_LOCK(); + /* function body */ + retVal = RT_MAPPER->time_portPtpOper_set(pOperCfg); + RTK_API_UNLOCK(); + return retVal; + +} /* end of rtk_time_portPtpOper_set */ + + +/* Function Name: + * rtk_time_portPtpLatchTime_get + * Description: + * Get the PTP latched time of specific port. + * Input: + * port - port ID + * Output: + * pOperCfg - pointer to PTP time operation configuraton + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Applicable: + * 8371 + * Note: + * None + * Changes: + * New added function. + */ +rtk_api_ret_t rtk_time_portPtpLatchTime_get(rtk_time_timeStamp_t *pLatchTime) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->time_portPtpLatchTime_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + /* function body */ + retVal = RT_MAPPER->time_portPtpLatchTime_get( pLatchTime); + RTK_API_UNLOCK(); + return retVal; + +} /* end of rtk_time_portPtpLatchTime_get */ + + +/* Function Name: + * rtk_time_portPtpRefTimeFreqCfg_get + * Description: + * Get the frequency of reference time of the specified port. + * Input: + * Output: + * pFreqCfg - pointer to configured reference time frequency + * pFreqCur - pointer to current reference time frequency + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Applicable: + * phy + * Note: + * None + * Changes: + * New added function. + */ +rtk_api_ret_t rtk_time_portPtpRefTimeFreqCfg_get(rtk_uint32 *pFreqCfg, rtk_uint32 *pFreqCur) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->time_portPtpRefTimeFreqCfg_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + /* function body */ + retVal = RT_MAPPER->time_portPtpRefTimeFreqCfg_get(pFreqCfg, pFreqCur); + RTK_API_UNLOCK(); + return retVal; +} + +/* Function Name: + * rtk_time_portPtpRefTimeFreqCfg_set + * Description: + * Set the frequency of reference time of the specified port. + * Input: + * port - port id + * freq - reference time frequency + * apply - if the frequency is applied immediately + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - input parameter out of range + * Applicable: + * phy + * Note: + * 0x80000000 external clock + * 0x10000000 internal clock + * Changes: + * New added function. + */ +rtk_api_ret_t rtk_time_portPtpRefTimeFreqCfg_set( rtk_uint32 freq, rtk_enable_t apply) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->time_portPtpRefTimeFreqCfg_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + /* function body */ + retVal = RT_MAPPER->time_portPtpRefTimeFreqCfg_set(freq, apply); + RTK_API_UNLOCK(); + return retVal; +} + + +/* Function Name: + * rtk_time_portPtpTxTimestampFifo_get + * Description: + * Get the top entry from PTP Tx timstamp FIFO on the dedicated port from the specified device. of the specified port. + * Input: + * port - port id + * Output: + * pTimeEntry - pointer buffer of TIME timestamp entry + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Applicable: + * phy + * Note: + * None + * Changes: + * [SDK_NEXT_RELEASE_VERSION] + * New added function. + */ +rtk_api_ret_t rtk_time_portPtpTxTimestampFifo_get( rtk_time_txTimeEntry_t *pTimeEntry) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->time_portPtpTxTimestampFifo_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + /* function body */ + retVal = RT_MAPPER->time_portPtpTxTimestampFifo_get(pTimeEntry); + RTK_API_UNLOCK(); + return retVal; +} + + +/* Function Name: + * rtk_time_portPtp1PPSOutput_get + * Description: + * Get the 1 PPS output configuration of the specified port. + * Input: + * port - port id + * Output: + * pPulseWidth - pointer to 1 PPS pulse width + * pEnable - pointer to 1 PPS output enable status + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Applicable: + * phy + * Note: + * None + * Changes: + * New added function. + */ +rtk_api_ret_t rtk_time_portPtp1PPSOutput_get( rtk_uint32 *pPulseWidth, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->time_portPtp1PPSOutput_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + /* function body */ + retVal = RT_MAPPER->time_portPtp1PPSOutput_get( pPulseWidth, pEnable); + RTK_API_UNLOCK(); + return retVal; + +} + + +/* Function Name: + * rtk_time_portPtp1PPSOutput_set + * Description: + * Set the 1 PPS output configuration of the specified port. + * Input: + * port - port id + * pulseWidth - pointer to 1 PPS pulse width + * enable - enable 1 PPS output + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - input parameter out of range + * Applicable: + * + * Note: + * None + * Changes: + * [SDK_NEXT_RELEASE_VERSION] + * New added function. + */ +rtk_api_ret_t rtk_time_portPtp1PPSOutput_set( rtk_uint32 pulseWidth, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->time_portPtp1PPSOutput_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + /* function body */ + retVal = RT_MAPPER->time_portPtp1PPSOutput_set(pulseWidth, enable); + RTK_API_UNLOCK(); + return retVal; + +} +/* Function Name: + * rtk_time_portPtpClkSrcCtrl_get + * Description: + * Set PTP time Clock source selection + * Input: + * clksrc + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * 0: internal clock (Internal PLL, 1GMHz) + * 1: external clock, refer to cfg_ext_clk_src) + */ +rtk_api_ret_t rtk_time_portPtpClkSrcCtrl_get(rtk_enable_t* clksrc) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->time_portPtpClkSrcCtrl_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + /* function body */ + retVal = RT_MAPPER->time_portPtpClkSrcCtrl_get(clksrc); + RTK_API_UNLOCK(); + return retVal; + +} + + +/* Function Name: + * rtk_time_portPtpClkSrcCtrl_set + * Description: + * Set PTP time Clock source selection + * Input: + * clksrc + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * 0: internal clock (Internal PLL, 1GMHz) + * 1: external clock, refer to cfg_ext_clk_src) + */ +rtk_api_ret_t rtk_time_portPtpClkSrcCtrl_set( rtk_enable_t clksrc) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->time_portPtpClkSrcCtrl_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + /* function body */ + retVal = RT_MAPPER->time_portPtpClkSrcCtrl_set(clksrc); + RTK_API_UNLOCK(); + return retVal; + +} +/* Function Name: + * rtk_time_portPtptoddelay_get + * Description: + * + * Input: + * port - port id + * Output: + * toddelay + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None + * Changes: + * New added function. + */ +rtk_api_ret_t rtk_time_portPtptoddelay_get(rtk_uint32* toddelay) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->time_portPtp1PPSOutput_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + /* function body */ + retVal = RT_MAPPER->time_portPtpToddelay_get(toddelay); + RTK_API_UNLOCK(); + return retVal; + +} + + +/* Function Name: + * rtk_time_portPtptoddelay_set + * Description: + * + * Input: + * toddelay + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - input parameter out of range + * Applicable: + * + * Note: + * None + * Changes: + * New added function. + */ +rtk_api_ret_t rtk_time_portPtptoddelay_set( rtk_uint32 toddelay) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->time_portPtp1PPSOutput_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + /* function body */ + retVal = RT_MAPPER->time_portPtpToddelay_set(toddelay); + RTK_API_UNLOCK(); + return retVal; + +} +/* Function Name: + * rtk_time_portPtpClockOutput_get + * Description: + * Get the clock output configuration of the specified port. + * Input: + * port - port id + * Output: + * pClkOutput - pointer to clock output configuration + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Applicable: + * 8218E + * Note: + * None + * Changes: + * [SDK_NEXT_RELEASE_VERSION] + * New added function. + */ +rtk_api_ret_t rtk_time_portPtpClockOutput_get(rtk_time_clkOutput_t *pClkOutput) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->time_portPtpClockOutput_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + /* function body */ + retVal = RT_MAPPER->time_portPtpClockOutput_get(pClkOutput); + RTK_API_UNLOCK(); + return retVal; + +} + + +/* Function Name: + * rtk_time_portPtpClockOutput_set + * Description: + * Set the clock output configuration of the specified port. + * Input: + * pClkOutput - pointer to clock output configuration + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - input parameter out of range + * Note: + * None + * Changes: + * New added function. + */ +rtk_api_ret_t rtk_time_portPtpClockOutput_set( rtk_time_clkOutput_t pClkOutput) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->time_portPtpClockOutput_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + /* function body */ + retVal = RT_MAPPER->time_portPtpClockOutput_set( pClkOutput); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_time_portPtpPortctrl_set + * Description: + * Set the PTP port ability. + * Input: + * portcfg - portrole,linkdelay,awaysts + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Applicable: + * phy + * Note: + * None + * Changes: + * New added function. + */ +rtk_api_ret_t rtk_time_portPtpPortctrl_set( rtk_port_t port,rtk_ptp_port_ctrl_t portcfg) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->time_portPtpPortctrl_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + /* function body */ + retVal = RT_MAPPER->time_portPtpPortctrl_set(port,portcfg); + RTK_API_UNLOCK(); + return retVal; +} + + +/* Function Name: + * Get the PTP rtk_time_portPtpPortctrl_get ability. + * Description: + * Get the PTP port ability.. + * Input: + * Output: + * portcfg + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - input parameter out of range + * Note: + * None + * Changes: + * New added function. + */ +rtk_api_ret_t rtk_time_portPtpPortctrl_get( rtk_port_t port, rtk_ptp_port_ctrl_t *portcfg) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->time_portPtpPortctrl_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + /* function body */ + retVal = RT_MAPPER->time_portPtpPortctrl_get(port,portcfg); + RTK_API_UNLOCK(); + return retVal; +} + +/* Function Name: + * rtk_ptp_intControl_set + * Description: + * Set PTP interrupt trigger status configuration. + * Input: + * enable - Interrupt status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * The API can set PTP interrupt status configuration. + * The interrupt trigger status is shown in the following: + */ +rtk_api_ret_t rtk_time_PtpIntControl_set(rtk_ptp_intType_t type,rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->ptp_intControl_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->ptp_intControl_set(type,enable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_ptp_intControl_get + * Description: + * Get PTP interrupt trigger status configuration. + * Input: + * Output: + * pEnable - Interrupt status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get interrupt status configuration. + * The interrupt trigger status is shown in the following: + */ +rtk_api_ret_t rtk_time_PtpIntControl_get(rtk_ptp_intType_t type,rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->ptp_intControl_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->ptp_intControl_get(type,pEnable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_ptp_intStatus_get + * Description: + * Get PTP port interrupt trigger status. + * Input: + * port - physical port + * Output: + * pStatusMask - Interrupt status bit mask. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get interrupt trigger status when interrupt happened. + * The interrupt trigger status is shown in the following: + * PTP_INT_TYPE_1PPS = 0, + * PTP_INT_TYPE_TOD_DONE, + * PTP_INT_TYPE_TXTIME_EMPTY, + * + */ +rtk_api_ret_t rtk_time_PtpIntStatus_get(rtk_ptp_intStatus_t *pStatusMask) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->ptp_intStatus_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->ptp_intStatus_get(pStatusMask); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_time_portPtpTrap_set + * Description: + * Set PTP packet trap of the specified port. + * Input: + * enable - status + * port - port id + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT - invalid port id + * RT_ERR_INPUT - invalid input parameter + * Note: + * None + */ +rtk_api_ret_t rtk_time_portPtpTrap_set( rtk_port_t port, rtk_ptp_porttrap_ctrl_t *trapctrl ) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->ptp_portTrap_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->ptp_portTrap_set(port,trapctrl); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_time_portPtpTrap_get + * Description: + * Get PTP packet trap of the specified port. + * Input: + * port - port id + * Output: + * pEnable - status + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT - invalid port id + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None + */ +rtk_api_ret_t rtk_time_portPtpTrap_get(rtk_port_t port, rtk_ptp_porttrap_ctrl_t *trapctrl ) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->ptp_portTrap_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->ptp_portTrap_get(port,trapctrl); + RTK_API_UNLOCK(); + + return retVal; +} + + diff --git a/sources/uboot-be550/drivers/net/rtl8372/ptp.h b/sources/uboot-be550/drivers/net/rtl8372/ptp.h new file mode 100755 index 00000000..87805b0c --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/ptp.h @@ -0,0 +1,1145 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8367/RTL8367C switch high-level API + * + * Feature : The file includes time module high-layer API defination + * + */ + +#ifndef __RTK_API_PTP_H__ +#define __RTK_API_PTP_H__ + +/* + * Symbol Definition + */ +#define RTK_MAX_NUM_OF_NANO_SECOND 0x3B9ACA00 +#define RTK_PTP_INTR_MASK 0xFF +#define RTK_MAX_NUM_OF_TPID 0xFFFF + +/* Message Type */ +typedef enum rtk_ptp_msgType_e +{ + PTP_MSG_TYPE_TX_SYNC = 0, + PTP_MSG_TYPE_TX_DELAY_REQ, + PTP_MSG_TYPE_TX_PDELAY_REQ, + PTP_MSG_TYPE_TX_PDELAY_RESP, + PTP_MSG_TYPE_RX_SYNC, + PTP_MSG_TYPE_RX_DELAY_REQ, + PTP_MSG_TYPE_RX_PDELAY_REQ, + PTP_MSG_TYPE_RX_PDELAY_RESP, + PTP_MSG_TYPE_END +} rtk_ptp_msgType_t; + +typedef enum rtk_ptp_intType_e +{ + PTP_INT_TYPE_1PPS = 0, + PTP_INT_TYPE_TOD_DONE, + PTP_INT_TYPE_TXTIME_EMPTY, + PTP_INT_TYPE_END +}rtk_ptp_intType_t; + +typedef enum rtk_ptp_sys_adjust_e +{ + SYS_ADJUST_PLUS = 0, + SYS_ADJUST_MINUS, + SYS_ADJUST_END +} rtk_ptp_sys_adjust_t; + +typedef enum rtk_ptp_header_e +{ + PTP_ETH = 0, + PTP_UDP , + PTP_END +} rtk_ptp_header_t; + +/* Reference Time */ +typedef struct rtk_time_timeStamp_s +{ + rtk_uint64 sec; + rtk_uint32 nsec; +} rtk_time_timeStamp_t; + +typedef struct rtk_ptp_info_s +{ + rtk_uint32 sequenceId; + rtk_time_timeStamp_t timeStamp; +} rtk_ptp_info_t; + +typedef enum rtk_ptp_port_role_e +{ + PTP_PORT_NONE= 0, + PTP_PORT_BCOC, + PTP_PORT_E2ETC, + PTP_PORT_P2PTC, + PTP_PORT_END, +} rtk_ptp_port_role_t; + +typedef struct +{ + rtk_ptp_port_role_t portrole; + rtk_enable_t udp_en; + rtk_enable_t eth_en; + rtk_enable_t always_ts_en; + rtk_uint32 link_delay; +} rtk_ptp_port_ctrl_t; + +typedef struct rtk_ptp_porttrap_ctrl_s{ + rtk_uint32 udp_en; + rtk_uint32 eth_en; + rtk_uint32 ptp_delay_en;//MSG TYPE 0,1,8,9 + rtk_uint32 ptp_pdelay_en;//MSG TYPE 2,3,A + rtk_uint32 ptp_pasm_en;//MSG TYPE B,C,D +}rtk_ptp_porttrap_ctrl_t; + +typedef rtk_uint32 rtk_ptp_tpid_t; + +typedef rtk_uint32 rtk_ptp_intStatus_t; /* interrupt status mask */ + +typedef enum rtk_vlanType_e +{ + INNER_VLAN = 0, + OUTER_VLAN, + VLAN_TYPE_END +} rtk_vlanType_t; + + +/* Message Type */ +typedef enum rtk_time_ptpMsgType_e +{ + PTP_MSG_TYPE_SYNC = 0, + PTP_MSG_TYPE_DELAY_REQ = 1, + PTP_MSG_TYPE_PDELAY_REQ = 2, + PTP_MSG_TYPE_PDELAY_RESP = 3, +} rtk_time_ptpMsgType_t; + +/* trap packet target */ +typedef enum rtk_trapTarget_e +{ + RTK_FORWARD, + RTK_TRAP, + RTK_DROP, + RTK_TRAP_END, +} rtk_trapTarget_t; + +/* TIME packet identifier */ +typedef struct rtk_time_ptpIdentifier_s +{ + rtk_time_ptpMsgType_t msgType; + rtk_uint32 sequenceId; +} rtk_time_ptpIdentifier_t; + +typedef enum rtk_time_oper_e +{ + TIME_OPER_START = 0, + TIME_OPER_STOP, + TIME_OPER_LATCH, + TIME_OPER_CMD_EXEC, + TIME_OPER_FREQ_APPLY, + TIME_OPER_END +} rtk_time_oper_t; + + +typedef enum rtk_time_opertriger_e +{ + TIME_FALL_TRI= 1, + TIME_RISE_TRI, + TIME_BOTH_TRI, + TIME_TRI_END +} rtk_time_opertriger_t; + +typedef struct rtk_time_operCfg_s +{ + rtk_time_oper_t oper; + rtk_enable_t rise_tri; + rtk_enable_t fall_tri; + rtk_enable_t tri_apply; +} rtk_time_operCfg_t; +typedef enum rtk_time_clkOutMode_e +{ + PTP_CLK_OUT_REPEAT = 0, + PTP_CLK_OUT_PULSE = 1, + PTP_CLK_OUT_END +} rtk_time_clkOutMode_t; + +typedef enum rtk_time_outSigSel_e +{ + PTP_OUT_SIG_SEL_CLOCK = 0, + PTP_OUT_SIG_SEL_1PPS = 1, + PTP_OUT_SIG_SEL_END +} rtk_time_outSigSel_t; + +/* TIME transmission callback function prototype */ +typedef rtk_int32 (rtk_time_ptpTime_cb_f)( + rtk_port_t port, + rtk_time_ptpIdentifier_t identifier, + rtk_time_timeStamp_t time); +/* + * Data Declaration + */ +typedef struct rtk_time_txTimeEntry_s +{ + rtk_uint8 valid; + rtk_port_t port; + rtk_time_ptpMsgType_t msg_type; + rtk_uint32 seqId; + rtk_time_timeStamp_t txTime; +} rtk_time_txTimeEntry_t; + +typedef struct rtk_time_clkOutput_s +{ + rtk_time_clkOutMode_t mode; + rtk_time_timeStamp_t startTime; + rtk_uint32 halfPeriodNsec; + rtk_enable_t enable; + rtk_uint8 runing; //Only valid for get API +} rtk_time_clkOutput_t; + + +/* Function Name: + * rtk_time_portPtpEnable_get + * Description: + * Get PTP status of the specified port. + * Input: + * port - port id + * type - PTP_ETH or UDP + * enable - status + * Output: + * pEnable - status + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT - invalid port id + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Applicable: + * + * Note: + * None + * Changes: + * None + */ +ret_t rtk_time_portPtpEnable_get( rtk_port_t port, rtk_ptp_header_t type,rtk_enable_t *pEnable); + + +/* Function Name: + * rtk_time_portPtpEnable_set + * Description: + * Get PTP status of the specified port. + * Input: + * port - port id + * type - PTP_ETH or UDP + * enable - status + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT - invalid port id + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Applicable: + * + * Note: + * None + * Changes: + * None + */ +ret_t rtk_time_portPtpEnable_set( rtk_port_t port, rtk_ptp_header_t type,rtk_enable_t Enable); + + + +/* Function Name: + * rtk_ptp_init + * Description: + * PTP function initialization. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API is used to initialize PTP status. + */ +rtk_api_ret_t rtk_time_init(rtk_portmask_t ptpinternalpmask); + +/* Function Name: + * rtk_time_portPtpbypassEnable_get + * Description: + * Get PTP status of the specified port. + * Input: + * Output: + * pEnable - status + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT - invalid port id + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Applicable: + * 8371 + * Note: + * None + * Changes: + * None + */ +extern rtk_api_ret_t rtk_time_portPtpbypassEnable_get(rtk_port_t port,rtk_enable_t *pEnable); + +/* Function Name: + * rtk_time_portPtpbypassEnable_set + * Description: + * Set PTP status of the specified port. + * Input: + * port - port id + * enable - status + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT - invalid port id + * RT_ERR_INPUT - invalid input parameter + * Applicable: + * 8371 + * Note: + * None + * Changes: + * None + */ +extern rtk_api_ret_t rtk_time_portPtpbypassEnable_set(rtk_port_t port,rtk_enable_t enable); + +/* Function Name: + * rtk_time_portRefTime_get + * Description: + * Get the reference time of the specified port. + * Input: + * port - port id, it should be base port of PHY + * Output: + * pTimeStamp - pointer buffer of the reference time + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Applicable: + * 8371 + * Note: + * None + * Changes: + * Add port parameter. + */ +extern rtk_api_ret_t rtk_time_portRefTime_get( rtk_time_timeStamp_t *pTimeStamp); + +/* Function Name: + * rtk_time_portRefTime_set + * Description: + * Set the reference time of the specified portmask. + * Input: + * timeStamp - reference timestamp value + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Applicable: + * 8371 + * Note: + * None + * Changes: + * Change name from rtk_time_refTime_set. + * Add portmask parameter. + */ +extern rtk_api_ret_t rtk_time_portRefTime_set( rtk_time_timeStamp_t timeStamp,rtk_enable_t apply); +/* Function Name: + * rtk_time_portRefTimeAdjust_set + * Description: + * Adjust the reference time of portmask. + * Input: + * portmask - portmask, it should be base ports of PHYs + * sign - significant + * timeStamp - reference timestamp value + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Applicable: + * 8371 + * Note: + * sign=0 for positive adjustment, sign=1 for negative adjustment. + * Changes: + * [3.2.0] + * Change name from rtk_time_refTimeAdjust_set. + * Add portmask parameter. + */ +extern rtk_api_ret_t rtk_time_portRefTimeAdjust_set(rtk_uint32 sign, rtk_time_timeStamp_t timeStamp,rtk_enable_t apply); + +/* Function Name: + * rtk_time_portRefTimeEnable_get + * Description: + * Get the enable state of reference time of the specified port. + * Input: + * port - port id, it should be base port of PHY + * Output: + * pEnable - status + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Applicable: + * 8371 + * Note: + * None + * Changes: + * Change name from rtk_time_refTimeEnable_get. + * Add port parameter. + */ +extern rtk_api_ret_t rtk_time_portRefTimeEnable_get( rtk_enable_t *pEnable); + +/* Function Name: + * rtk_time_portRefTimeEnable_set + * Description: + * Set the enable state of reference time of the specified portmask. + * Input: + * portmask - portmask, it should be base ports of PHYs + * enable - status + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Applicable: + * 8371 + * Note: + * None + * Changes: + * Change name from rtk_time_refTimeEnable_set. + * Add portmask parameter. + */ +extern rtk_api_ret_t rtk_time_portRefTimeEnable_set(rtk_enable_t enable); + +/* Function Name: + * rtk_time_portPtpOper_triger + * Description: + * Set the PTP time operation triger. + * Input: + * triType + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None + */ +extern rtk_api_ret_t rtk_time_portPtpOper_triger(void); +#if 0 +/* Function Name: + * rtk_time_portRefTimeFreq_get + * Description: + * Get the frequency of PTP reference time of the specified port. + * Input: + * port - port id, it should be base port of PHY + * Output: + * pFreq - pointer to reference time frequency + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Applicable: + * 8371 + * Note: + * The frequency configuration decides the reference time tick frequency. + * The default value is 0x80000000. + * If it is configured to 0x40000000, the tick frequency would be half of default. + * If it is configured to 0xC0000000, the tick frequency would be one and half times of default. + * Changes: + * New added function. + * Change name from rtk_time_refTimeFreq_get. + * Add port parameter. + */ +extern rtk_api_ret_t rtk_time_portRefTimeFreq_get( rtk_uint32 *pFreq); +#endif +/* Function Name: + * rtk_time_portRefTimeFreq_set + * Description: + * Set the frequency of PTP reference time of the specified portmask. + * Input: + * portmask - portmask, it should be base ports of PHYs + * freq - reference time frequency + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Applicable: + * 8371 + * Note: + * The frequency configuration decides the reference time tick frequency. + * The default value is 0x80000000. + * If it is configured to 0x40000000, the tick frequence would be half of default. + * If it is configured to 0xC0000000, the tick frequence would be one and half times of default. + * Changes: + * New added function. + */ +extern rtk_api_ret_t rtk_time_portRefTimeFreq_set( rtk_uint32 freq); + +/* Function Name: + * rtk_time_portPtpVlanTpid_get + * Description: + * Get the VLAN TPID of specific port. + * Input: + * port - port ID + * type - outer or inner VLAN + * idx - TPID entry index + * Output: + * pTpid - pointer to TPID + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None + * Changes: + * New added function. + */ +extern rtk_api_ret_t rtk_time_portPtpVlanTpid_get( rtk_vlanType_t type, rtk_uint32 idx, rtk_uint32 *pTpid); + +/* Function Name: + * rtk_time_portPtpVlanTpid_set + * Description: + * Set the VLAN TPID of specific port. + * Input: + * port - port ID + * type - outer or inner VLAN + * idx - TPID entry index + * tpid - VLAN TPID + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Applicable: + * 8371 + * Note: + * None + * Changes: + * New added function. + */ +extern rtk_api_ret_t rtk_time_portPtpVlanTpid_set( rtk_vlanType_t type, rtk_uint32 idx, rtk_uint32 tpid); + +/* Function Name: + * rtk_time_portPtpOper_get + * Description: + * Get the PTP time operation configuration of specific port. + * Input: + * Output: + * pOperCfg - pointer to PTP time operation configuraton + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Applicable: + * 8371 + * Note: + * None + * Changes: + * New added function. + */ +extern rtk_api_ret_t rtk_time_portPtpOper_get(rtk_time_operCfg_t *pOperCfg); + + +/* Function Name: + * rtk_time_portPtpOper_set + * Description: + * Set the PTP time operation configuration of specific port. + * Input: + * pOperCfg - pointer to PTP time operation configuraton + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Applicable: + * 8371 + * Note: + * None + * Changes: + * New added function. + */ +extern rtk_api_ret_t rtk_time_portPtpOper_set( rtk_time_operCfg_t pOperCfg); + +/* Function Name: + * rtk_time_portPtpLatchTime_get + * Description: + * Get the PTP latched time of specific port. + * Input: + * port - port ID + * Output: + * pOperCfg - pointer to PTP time operation configuraton + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Applicable: + * 8371 + * Note: + * None + * Changes: + * [SDK_3.6.0] + * New added function. + */ +extern rtk_api_ret_t rtk_time_portPtpLatchTime_get( rtk_time_timeStamp_t *pLatchTime); + + +/* Function Name: + * rtk_time_portPtpRefTimeFreqCfg_get + * Description: + * Get the frequency of reference time of the specified port. + * Input: + * port - port id + * Output: + * pFreqCfg - pointer to configured reference time frequency + * pFreqCur - pointer to current reference time frequency + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Applicable: + * phy + * Note: + * None + * Changes: + * [SDK_NEXT_RELEASE_VERSION] + * New added function. + */ +extern rtk_api_ret_t rtk_time_portPtpRefTimeFreqCfg_get( rtk_uint32 *pFreqCfg, rtk_uint32 *pFreqCur); + +/* Function Name: + * rtk_time_portPtpRefTimeFreqCfg_set + * Description: + * Set the frequency of reference time of the specified port. + * Input: + * port - port id + * freq - reference time frequency + * apply - if the frequency is applied immediately + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - input parameter out of range + * Applicable: + * phy + * Note: + * None + * Changes: + * [SDK_NEXT_RELEASE_VERSION] + * New added function. + */ +extern rtk_api_ret_t rtk_time_portPtpRefTimeFreqCfg_set(rtk_uint32 freq, rtk_uint32 apply); + +/* Function Name: + * rtk_time_portPtpTxInterruptStatus_get + * Description: + * Get the TX timestamp FIFO non-empty interrupt status of the specified port. + * Input: + * port - port id + * Output: + * pIntrSts - interrupt status of RX/TX PTP frame types + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Applicable: + * phy + * Note: + * None + * Changes: + * [SDK_NEXT_RELEASE_VERSION] + * New added function. + */ +extern rtk_api_ret_t rtk_time_portPtpTxInterruptStatus_get( rtk_uint32 *pIntrSts); + +/* Function Name: + * rtk_time_portPtpTxTimestampFifo_get + * Description: + * Get the top entry from PTP Tx timstamp FIFO on the dedicated port from the specified device. of the specified port. + * Input: + * port - port id + * Output: + * pTimeEntry - pointer buffer of TIME timestamp entry + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Applicable: + * phy + * Note: + * None + * Changes: + * [SDK_NEXT_RELEASE_VERSION] + * New added function. + */ +extern rtk_api_ret_t rtk_time_portPtpTxTimestampFifo_get(rtk_time_txTimeEntry_t *pTimeEntry); + +/* Function Name: + * rtk_time_portPtpClkSrcCtrl_get + * Description: + * Set PTP time Clock source selection + * Input: + * clksrc + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * 0: internal clock (Internal PLL, 1GMHz) + * 1: external clock, refer to cfg_ext_clk_src) + */ +extern rtk_api_ret_t rtk_time_portPtpClkSrcCtrl_get(rtk_enable_t* clksrc); + + + +/* Function Name: + * rtk_time_portPtpClkSrcCtrl_set + * Description: + * Set PTP time Clock source selection + * Input: + * clksrc + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * Note: + * 0: internal clock (Internal PLL, 1GMHz) + * 1: external clock, refer to cfg_ext_clk_src) + */ +extern rtk_api_ret_t rtk_time_portPtpClkSrcCtrl_set( rtk_enable_t clksrc); +/* Function Name: + * rtk_time_portPtptoddelay_get + * Description: + * + * Input: + * port - port id + * Output: + * toddelay + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None + * Changes: + * New added function. + */ +extern rtk_api_ret_t rtk_time_portPtptoddelay_get(rtk_uint32* toddelay); + + + +/* Function Name: + * rtk_time_portPtptoddelay_set + * Description: + * + * Input: + * toddelay + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - input parameter out of range + * Applicable: + * + * Note: + * None + * Changes: + * New added function. + */ +extern rtk_api_ret_t rtk_time_portPtptoddelay_set( rtk_uint32 toddelay); +/* Function Name: + * rtk_time_portPtp1PPSOutput_get + * Description: + * Get the 1 PPS output configuration of the specified port. + * Input: + * port - port id + * Output: + * pPulseWidth - pointer to 1 PPS pulse width + * pEnable - pointer to 1 PPS output enable status + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Applicable: + * phy + * Note: + * None + * Changes: + * New added function. + */ +extern rtk_api_ret_t rtk_time_portPtp1PPSOutput_get(rtk_uint32 *pPulseWidth, rtk_enable_t *pEnable); + + +/* Function Name: + * rtk_time_portPtp1PPSOutput_set + * Description: + * Set the 1 PPS output configuration of the specified port. + * Input: + * port - port id + * pulseWidth - pointer to 1 PPS pulse width + * enable - enable 1 PPS output + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - input parameter out of range + * Applicable: + * + * Note: + * None + * Changes: + * New added function. + */ +extern rtk_api_ret_t rtk_time_portPtp1PPSOutput_set(rtk_uint32 pulseWidth, rtk_enable_t enable); + +/* Function Name: + * rtk_time_portPtpClockOutput_get + * Description: + * Get the clock output configuration of the specified port. + * Input: + * port - port id + * Output: + * pClkOutput - pointer to clock output configuration + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Applicable: + * Note: + * None + * Changes: + * New added function. + */ +extern rtk_api_ret_t rtk_time_portPtpClockOutput_get(rtk_time_clkOutput_t *pClkOutput); + +/* Function Name: + * rtk_time_portPtpClockOutput_set + * Description: + * Set the clock output configuration of the specified port. + * Input: + * port - port id + * pClkOutput - pointer to clock output configuration + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - input parameter out of range + * Applicable: + * Note: + * None + * Changes: + * [SDK_NEXT_RELEASE_VERSION] + * New added function. + */ +extern rtk_api_ret_t rtk_time_portPtpClockOutput_set(rtk_time_clkOutput_t pClkOutput); + +/* Function Name: + * rtk_time_portPtpOutputSigSel_get + * Description: + * Get the output pin signal selection configuration of the specified port. + * Input: + * port - port id + * Output: + * pOutSigSel - pointer to output pin signal selection configuration + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Applicable: + * phy + * Note: + * None + * Changes: + * New added function. + */ +extern rtk_api_ret_t rtk_time_portPtpOutputSigSel_get(rtk_time_outSigSel_t *pOutSigSel); + +/* Function Name: + * rtk_time_portPtpOutputSigSel_set + * Description: + * Set the output pin signal selection configuration of the specified port. + * Input: + * port - port id + * outSigSel - output pin signal selection configuration + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - input parameter out of range + * Applicable: + * phy + * Note: + * None + * Changes: + * New added function. + */ +extern rtk_api_ret_t rtk_time_portPtpOutputSigSel_set(rtk_time_outSigSel_t outSigSel); + +/* Function Name: + * rtk_time_portPtpTransEnable_get + * Description: + * Get the enable status for PTP transparent clock of the specified port. + * Input: + * port - port id + * Output: + * pEnable - pointer to PTP transparent clock enable status + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Applicable: + * phy + * Note: + * None + * Changes: + * [SDK_NEXT_RELEASE_VERSION] + * New added function. + */ +extern rtk_api_ret_t rtk_time_portPtpTransEnable_get(rtk_enable_t *pEnable); + +/* Function Name: + * rtk_time_portPtpTransEnable_set + * Description: + * Set the enable status for PTP transparent clock of the specified port. + * Input: + * port - port id + * enable - PTP transparent clock enable status + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - input parameter out of range + * Applicable: + * PHY + * Note: + * None + * Changes: + * [SDK_NEXT_RELEASE_VERSION] + * New added function. + */ +extern rtk_api_ret_t rtk_time_portPtpTransEnable_set(rtk_enable_t enable); + +/* Function Name: + * Get the PTP rtk_time_portPtpPortctrl_get ability. + * Description: + * Get the PTP port ability.. + * Input: + * port - port id + * Output: + * portcfg + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - input parameter out of range + * Note: + * None + * Changes: + * New added function. + */ +extern rtk_api_ret_t rtk_time_portPtpPortctrl_get(rtk_port_t port,rtk_ptp_port_ctrl_t *portcfg); + +/* Function Name: + * rtk_time_portPtpPortctrl_set + * Description: + * Set the PTP port ability. + * Input: + * port - port id + * portcfg - portrole,linkdelay,awaysts + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Applicable: + * phy + * Note: + * None + * Changes: + * New added function. + */ +extern rtk_api_ret_t rtk_time_portPtpPortctrl_set(rtk_port_t port,rtk_ptp_port_ctrl_t portcfg); + +/* Function Name: + * rtk_ptp_intControl_set + * Description: + * Set PTP interrupt trigger status configuration. + * Input: + * enable - Interrupt status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * The API can set PTP interrupt status configuration. + * The interrupt trigger status is shown in the following: + */ +extern rtk_api_ret_t rtk_time_PtpIntControl_set(rtk_ptp_intType_t type,rtk_enable_t enable); + +/* Function Name: + * rtk_ptp_intControl_get + * Description: + * Get PTP interrupt trigger status configuration. + * Output: + * pEnable - Interrupt status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get interrupt status configuration. + */ +extern rtk_api_ret_t rtk_time_PtpIntControl_get(rtk_ptp_intType_t type,rtk_enable_t *pEnable); + +/* Function Name: + * rtk_ptp_intStatus_get + * Description: + * Get PTP port interrupt trigger status. + * Input: + * port - physical port + * Output: + * pStatusMask - Interrupt status bit mask. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get interrupt trigger status when interrupt happened. + * The interrupt trigger status is shown in the following: + * - PORT 0 INT (value[0] (Bit0)) + * - PORT 1 INT (value[0] (Bit1)) + * - PORT 2 INT (value[0] (Bit2)) + * - PORT 3 INT (value[0] (Bit3)) + * - PORT 4 INT (value[0] (Bit4)) + * + */ +extern rtk_api_ret_t rtk_time_PtpIntStatus_get(rtk_ptp_intStatus_t *pStatusMask); + +/* Function Name: + * rtk_time_portPtpTrap_set + * Description: + * Set PTP packet trap of the specified port. + * Input: + * port - port id + * *trapctrl -trapen mask + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT - invalid port id + * RT_ERR_INPUT - invalid input parameter + * Note: + * None + */ +extern rtk_api_ret_t rtk_time_portPtpTrap_set(rtk_port_t port, rtk_ptp_porttrap_ctrl_t *trapctrl ); + +/* Function Name: + * rtk_time_portPtpTrap_get + * Description: + * Get PTP packet trap of the specified port. + * Input: + * port - port id + * *trapctrl -trapen mask + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT - invalid port id + * RT_ERR_INPUT - invalid input parameter + * Note: + * None + */ +extern rtk_api_ret_t rtk_time_portPtpTrap_get(rtk_port_t port, rtk_ptp_porttrap_ctrl_t *trapctrl ); + +#endif /* __RTK_API_PTP_H__ */ + diff --git a/sources/uboot-be550/drivers/net/rtl8372/qos.c b/sources/uboot-be550/drivers/net/rtl8372/qos.c new file mode 100755 index 00000000..27595b2b --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/qos.c @@ -0,0 +1,1110 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8373 + * Feature : Here is a list of all functions and variables in QoS module. + * + */ + +#include +#include +#include +#include + +#include + +/* Function Name: + * rtk_qos_init + * Description: + * Configure Qos default settings. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will initialize related Qos setting. + */ +rtk_api_ret_t rtk_qos_init(void) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->qos_init) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->qos_init(); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_qos_priSel_set + * Description: + * Configure the priority order among different priority mechanism. + * Input: + * index - Priority decision table index (0~1) + * pPriDec - Priority assign for port, dscp, 802.1p, svlan, acl based priority decision. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_SEL_PRI_SOURCE - Invalid priority decision source parameter. + * Note: + * ASIC will follow user priority setting of mechanisms to select mapped queue priority for receiving frame. + * If two priority mechanisms are the same, the ASIC will chose the highest priority from mechanisms to + * assign queue priority to receiving frame. + * The priority sources are: + * - PRIDEC_PORT + * - PRIDEC_ACL + * - PRIDEC_DSCP + * - PRIDEC_1Q + * - PRIDEC_SVLAN + */ +rtk_api_ret_t rtk_qos_priSel_set(rtk_qos_priDecTbl_t index, rtk_priority_select_t *pPriDec) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->qos_priSel_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->qos_priSel_set(index, pPriDec); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_qos_priSel_get + * Description: + * Get the priority order configuration among different priority mechanism. + * Input: + * index - Priority decision table index (0~1) + * Output: + * pPriDec - Priority assign for port, dscp, 802.1p, svlan, acl based priority decision . + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * ASIC will follow user priority setting of mechanisms to select mapped queue priority for receiving frame. + * If two priority mechanisms are the same, the ASIC will chose the highest priority from mechanisms to + * assign queue priority to receiving frame. + * The priority sources are: + * - PRIDEC_PORT, + * - PRIDEC_ACL, + * - PRIDEC_DSCP, + * - PRIDEC_1Q, + * - PRIDEC_SVLAN, + */ +rtk_api_ret_t rtk_qos_priSel_get(rtk_qos_priDecTbl_t index, rtk_priority_select_t *pPriDec) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->qos_priSel_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->qos_priSel_get(index, pPriDec); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_qos_1pPriRemap_set + * Description: + * Configure 1Q priorities mapping to internal absolute priority. + * Input: + * dot1p_pri - 802.1p priority value. + * int_pri - internal priority value. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_VLAN_PRIORITY - Invalid 1p priority. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * Priority of 802.1Q assignment for internal asic priority, and it is used for queue usage and packet scheduling. + */ +rtk_api_ret_t rtk_qos_1pPriRemap_set(rtk_pri_t dot1p_pri, rtk_pri_t int_pri) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->qos_1pPriRemap_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->qos_1pPriRemap_set(dot1p_pri, int_pri); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_qos_1pPriRemap_get + * Description: + * Get 1Q priorities mapping to internal absolute priority. + * Input: + * dot1p_pri - 802.1p priority value . + * Output: + * pInt_pri - internal priority value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_VLAN_PRIORITY - Invalid priority. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * Priority of 802.1Q assigment for internal asic priority, and it is uesed for queue usage and packet scheduling. + */ +rtk_api_ret_t rtk_qos_1pPriRemap_get(rtk_pri_t dot1p_pri, rtk_pri_t *pInt_pri) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->qos_1pPriRemap_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->qos_1pPriRemap_get(dot1p_pri, pInt_pri); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_qos_dscpPriRemap_set + * Description: + * Map dscp value to internal priority. + * Input: + * dscp - Dscp value of receiving frame + * int_pri - internal priority value . + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_QOS_DSCP_VALUE - Invalid DSCP value. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * The Differentiated Service Code Point is a selector for router's per-hop behaviors. As a selector, there is no implication that a numerically + * greater DSCP implies a better network service. As can be seen, the DSCP totally overlaps the old precedence field of TOS. So if values of + * DSCP are carefully chosen then backward compatibility can be achieved. + */ +rtk_api_ret_t rtk_qos_dscpPriRemap_set(rtk_dscp_t dscp, rtk_pri_t int_pri) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->qos_dscpPriRemap_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->qos_dscpPriRemap_set(dscp, int_pri); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_qos_dscpPriRemap_get + * Description: + * Get dscp value to internal priority. + * Input: + * dscp - Dscp value of receiving frame + * Output: + * pInt_pri - internal priority value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_DSCP_VALUE - Invalid DSCP value. + * Note: + * The Differentiated Service Code Point is a selector for router's per-hop behaviors. As a selector, there is no implication that a numerically + * greater DSCP implies a better network service. As can be seen, the DSCP totally overlaps the old precedence field of TOS. So if values of + * DSCP are carefully chosen then backward compatibility can be achieved. + */ +rtk_api_ret_t rtk_qos_dscpPriRemap_get(rtk_dscp_t dscp, rtk_pri_t *pInt_pri) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->qos_dscpPriRemap_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->qos_dscpPriRemap_get(dscp, pInt_pri); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_qos_RspanPriRemap_set + * Description: + * Configure RSPAN priorities mapping to internal absolute priority. + * Input: + * rspan_pri - rspan priority value. + * int_pri - internal priority value. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_VLAN_PRIORITY - Invalid 1p priority. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * Priority of RSPAN assignment for internal asic priority, and it is used for queue usage and packet scheduling. + */ +rtk_api_ret_t rtk_qos_RspanPriRemap_set(rtk_pri_t rspan_pri, rtk_pri_t int_pri) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->qos_rspanpriRemap_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->qos_rspanpriRemap_set(rspan_pri, int_pri); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_qos_RspanPriRemap_get + * Description: + * Get RSPAN priorities mapping to internal absolute priority. + * Input: + * rspan_pri - rspan priority value. + * Output: + * pInt_pri - internal priority value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_VLAN_PRIORITY - Invalid priority. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * Priority of RSPAN assigment for internal asic priority, and it is uesed for queue usage and packet scheduling. + */ +rtk_api_ret_t rtk_qos_RspanPriRemap_get(rtk_pri_t rspan_pri, rtk_pri_t *pInt_pri) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->qos_rspanpriRemap_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->qos_rspanpriRemap_get(rspan_pri, pInt_pri); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_qos_portPri_set + * Description: + * Configure priority usage to each port. + * Input: + * port - Port id. + * int_pri - internal priority value. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_QOS_SEL_PORT_PRI - Invalid port priority. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * The API can set priority of port assignments for queue usage and packet scheduling. + */ +rtk_api_ret_t rtk_qos_portPri_set(rtk_port_t port, rtk_pri_t int_pri) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->qos_portPri_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->qos_portPri_set(port, int_pri); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_qos_portPri_get + * Description: + * Get priority usage to each port. + * Input: + * port - Port id. + * Output: + * pInt_pri - internal priority value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get priority of port assignments for queue usage and packet scheduling. + */ +rtk_api_ret_t rtk_qos_portPri_get(rtk_port_t port, rtk_pri_t *pInt_pri) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->qos_portPri_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->qos_portPri_get(port, pInt_pri); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_qos_priMap_set + * Description: + * Set output queue number for each port. + * Input: + * port - Port ID. + * pPri2qid - Priority mapping to queue ID. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_QUEUE_ID - Invalid queue id. + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * ASIC supports priority mapping to queue with different internal available queue IDs. + */ +rtk_api_ret_t rtk_qos_priMap_set(rtk_port_t port, rtk_qos_pri2queue_t *pPri2qid) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->qos_priMap_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->qos_priMap_set(port, pPri2qid); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * dal_rtl8371c_qos_priMap_get + * Description: + * Get priority to queue ID mapping table parameters. + * Input: + * port - Port ID. + * Output: + * pPri2qid - Priority mapping to queue ID. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_QUEUE_NUM - Invalid queue number. + * Note: + * The API can return the mapping queue id of the specified priority. + */ +rtk_api_ret_t rtk_qos_priMap_get(rtk_port_t port, rtk_qos_pri2queue_t *pPri2qid) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->qos_priMap_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->qos_priMap_get(port, pPri2qid); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_qos_schedulingQueue_set + * Description: + * Set weight and type of queues in dedicated port. + * Input: + * port - Port id. + * pQweights - The array of weights for WRR/WFQ queue (0 for STRICT_PRIORITY queue). + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_QOS_QUEUE_WEIGHT - Invalid queue weight. + * Note: + * The API can set weight and type, strict priority or weight fair queue (WFQ) for + * dedicated port for using queues. If queue id is not included in queue usage, + * then its type and weight setting in dummy for setting. There are priorities + * as queue id in strict queues. It means strict queue id 5 carrying higher priority + * than strict queue id 4. The WFQ queue weight is from 1 to 127, and weight 0 is + * for strict priority queue type. + */ +rtk_api_ret_t rtk_qos_schedulingQueue_set(rtk_port_t port, rtk_qos_queue_weights_t *pQweights) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->qos_schedulingQueue_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->qos_schedulingQueue_set(port, pQweights); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_qos_schedulingQueue_get + * Description: + * Get weight and type of queues in dedicated port. + * Input: + * port - Port id. + * Output: + * pQweights - The array of weights for WRR/WFQ queue (0 for STRICT_PRIORITY queue). + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get weight and type, strict priority or weight fair queue (WFQ) for dedicated port for using queues. + * The WFQ queue weight is from 1 to 127, and weight 0 is for strict priority queue type. + */ +rtk_api_ret_t rtk_qos_schedulingQueue_get(rtk_port_t port, rtk_qos_queue_weights_t *pQweights) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->qos_schedulingQueue_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->qos_schedulingQueue_get(port, pQweights); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_qos_1pRemarkEnable_set + * Description: + * Set 1p Remarking state + * Input: + * port - Port id. + * enable - State of per-port 1p Remarking + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable parameter. + * Note: + * The API can enable or disable 802.1p remarking ability for whole system. + * The status of 802.1p remark: + * - DISABLED + * - ENABLED + */ +rtk_api_ret_t rtk_qos_1pRemarkEnable_set(rtk_port_t port, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->qos_1pRemarkEnable_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->qos_1pRemarkEnable_set(port, enable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_qos_1pRemarkEnable_get + * Description: + * Get 802.1p remarking ability. + * Input: + * port - Port id. + * Output: + * pEnable - Status of 802.1p remark. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get 802.1p remarking ability. + * The status of 802.1p remark: + * - DISABLED + * - ENABLED + */ +rtk_api_ret_t rtk_qos_1pRemarkEnable_get(rtk_port_t port, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->qos_1pRemarkEnable_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->qos_1pRemarkEnable_get(port, pEnable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_qos_1pRemark_set + * Description: + * Set 802.1p remarking parameter. + * Input: + * int_pri - Internal priority value. + * dot1p_pri - 802.1p priority value. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_VLAN_PRIORITY - Invalid 1p priority. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * The API can set 802.1p parameters source priority and new priority. + */ +rtk_api_ret_t rtk_qos_1pRemark_set(rtk_pri_t int_pri, rtk_pri_t dot1p_pri) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->qos_1pRemark_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->qos_1pRemark_set(int_pri, dot1p_pri); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_qos_1pRemark_get + * Description: + * Get 802.1p remarking parameter. + * Input: + * int_pri - Internal priority value. + * Output: + * pDot1p_pri - 802.1p priority value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * The API can get 802.1p remarking parameters. It would return new priority of ingress priority. + */ +rtk_api_ret_t rtk_qos_1pRemark_get(rtk_pri_t int_pri, rtk_pri_t *pDot1p_pri) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->qos_1pRemark_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->qos_1pRemark_get(int_pri, pDot1p_pri); + RTK_API_UNLOCK(); + + return retVal; +} + + +/* Function Name: + * rtk_qos_1pRemarkSrcSel_set + * Description: + * Set remarking source of 802.1p remarking. + * Input: + * type - remarking source + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + + * Note: + * The API can configure 802.1p remark functionality to map original 802.1p value or internal + * priority to TX DSCP value. + */ +rtk_api_ret_t rtk_qos_1pRemarkSrcSel_set(rtk_qos_1pRmkSrc_t type) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->qos_1pRemarkSrcSel_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->qos_1pRemarkSrcSel_set(type); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_qos_1pRemarkSrcSel_get + * Description: + * Get remarking source of 802.1p remarking. + * Input: + * none + * Output: + * pType - remarking source + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None + */ +rtk_api_ret_t rtk_qos_1pRemarkSrcSel_get(rtk_qos_1pRmkSrc_t *pType) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->qos_1pRemarkSrcSel_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->qos_1pRemarkSrcSel_get(pType); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_qos_dscpRemarkEnable_set + * Description: + * Set DSCP remarking ability. + * Input: + * port - Port id. + * enable - status of DSCP remark. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * RT_ERR_ENABLE - Invalid enable parameter. + * Note: + * The API can enable or disable DSCP remarking ability for whole system. + * The status of DSCP remark: + * - DISABLED + * - ENABLED + */ +rtk_api_ret_t rtk_qos_dscpRemarkEnable_set(rtk_port_t port, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->qos_dscpRemarkEnable_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->qos_dscpRemarkEnable_set(port, enable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_qos_dscpRemarkEnable_get + * Description: + * Get DSCP remarking ability. + * Input: + * port - Port id. + * Output: + * pEnable - status of DSCP remarking. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get DSCP remarking ability. + * The status of DSCP remark: + * - DISABLED + * - ENABLED + */ +rtk_api_ret_t rtk_qos_dscpRemarkEnable_get(rtk_port_t port, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->qos_dscpRemarkEnable_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->qos_dscpRemarkEnable_get(port, pEnable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_qos_intpri2dscp_Remark_set + * Description: + * Set DSCP remarking parameter. + * Input: + * int_pri - Internal priority value. + * dscp - remark DSCP value. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * RT_ERR_QOS_DSCP_VALUE - Invalid DSCP value. + * Note: + * The API can set internal priority to DSCP value. + */ +rtk_api_ret_t rtk_qos_intpri2dscp_Remark_set(rtk_pri_t int_pri, rtk_dscp_t dscp) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->qos_intpri2dscpRemark_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->qos_intpri2dscpRemark_set(int_pri, dscp); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_qos_intpri2dscp_Remark_get + * Description: + * Get DSCP remarking parameter. + * Input: + * int_pri - Internal priority value. + * Output: + * pDscp - remark DSCP value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * The API can get DSCP parameters. It would return DSCP value for mapping priority. + */ +rtk_api_ret_t rtk_qos_intpri2dscp_Remark_get(rtk_pri_t int_pri, rtk_dscp_t *pDscp) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->qos_intpri2dscpRemark_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->qos_intpri2dscpRemark_get(int_pri, pDscp); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_qos_dscp2dscp_Remark_set + * Description: + * Set original DSCP remarking parameter. + * Input: + * ori_dscp - original dscp value. + * RmkDscp - remark DSCP value. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * RT_ERR_QOS_DSCP_VALUE - Invalid DSCP value. + * Note: + * The API can set original DSCP value to dscp value. + */ +rtk_api_ret_t rtk_qos_dscp2dscp_Remark_set(rtk_pri_t ori_dscp, rtk_dscp_t RmkDscp) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->qos_dscp2dscpRemark_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->qos_dscp2dscpRemark_set(ori_dscp, RmkDscp); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_qos_dscp2dscp_Remark_get + * Description: + * Get DSCP remarking parameter. + * Input: + * ori_dscp - original dscp value. + * Output: + * pRmkDscp - remark DSCP value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * The API can get DSCP parameters. It would return DSCP value for mapping priority. + */ +rtk_api_ret_t rtk_qos_dscp2dscp_Remark_get(rtk_pri_t ori_dscp, rtk_dscp_t *pRmkDscp) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->qos_dscp2dscpRemark_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->qos_dscp2dscpRemark_get(ori_dscp, pRmkDscp); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_qos_dscpRemarkSrcSel_set + * Description: + * Set remarking source of DSCP remarking. + * Input: + * type - remarking source + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + + * Note: + * The API can configure DSCP remark functionality to map original DSCP value or internal + * priority to TX DSCP value. + */ +rtk_api_ret_t rtk_qos_dscpRemarkSrcSel_set(rtk_qos_dscpRmkSrc_t type) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->qos_dscpRemarkSrcSel_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->qos_dscpRemarkSrcSel_set(type); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_qos_dscpRemarkSrcSel_get + * Description: + * Get remarking source of DSCP remarking. + * Input: + * none + * Output: + * pType - remarking source + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * RT_ERR_NULL_POINTER - input parameter may be null pointer + + * Note: + * None + */ +rtk_api_ret_t rtk_qos_dscpRemarkSrcSel_get(rtk_qos_dscpRmkSrc_t *pType) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->qos_dscpRemarkSrcSel_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->qos_dscpRemarkSrcSel_get(pType); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_qos_portPriSelIndex_set + * Description: + * Configure priority decision index to each port. + * Input: + * port - Port id. + * index - priority decision index. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENTRY_INDEX - Invalid entry index. + * Note: + * The API can set priority of port assignments for queue usage and packet scheduling. + */ +rtk_api_ret_t rtk_qos_portPriSelIndex_set(rtk_port_t port, rtk_qos_priDecTbl_t index) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->qos_portPriSelIndex_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->qos_portPriSelIndex_set(port, index); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_qos_portPriSelIndex_get + * Description: + * Get priority decision index from each port. + * Input: + * port - Port id. + * Output: + * pIndex - priority decision index. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get priority of port assignments for queue usage and packet scheduling. + */ +rtk_api_ret_t rtk_qos_portPriSelIndex_get(rtk_port_t port, rtk_qos_priDecTbl_t *pIndex) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->qos_portPriSelIndex_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->qos_portPriSelIndex_get(port, pIndex); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_qos_schedulingType_set + * Description: + * Configure type of scheduling. + * Input: + * port - port id + * queueType - Scheduling type. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_SCHE_TYPE - Invalid QoS scheduling type. + * Note: + * The API can set type of scheduling. + */ +rtk_api_ret_t rtk_qos_schedulingType_set(rtk_port_t port, rtk_qos_scheduling_type_t queueType) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->qos_schedulingType_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->qos_schedulingType_set(port, queueType); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_qos_schedulingType_get + * Description: + * Get type of scheduling. + * Input: + * port - port id + * Output: + * pIndex - priority decision index. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - NULL pointer + * Note: + * The API can get type of scheduling. + */ +rtk_api_ret_t rtk_qos_schedulingType_get(rtk_port_t port, rtk_qos_scheduling_type_t *pQueueType) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->qos_schedulingType_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->qos_schedulingType_get(port, pQueueType); + RTK_API_UNLOCK(); + + return retVal; +} + + + + + + diff --git a/sources/uboot-be550/drivers/net/rtl8372/qos.h b/sources/uboot-be550/drivers/net/rtl8372/qos.h new file mode 100755 index 00000000..89fd6d82 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/qos.h @@ -0,0 +1,804 @@ + /* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8373 switch high-level API + * + * Feature : The file includes QoS module high-layer API defination + * + */ + +#ifndef __RTK_API_QOS_H__ +#define __RTK_API_QOS_H__ + +/* + * Data Type Declaration + */ +#define QOS_DEFAULT_TICK_PERIOD (19-1) +#define QOS_DEFAULT_BYTE_PER_TOKEN 34 +#define QOS_DEFAULT_LK_THRESHOLD (34*3) /* Why use 0x400? */ + + +#define QOS_DEFAULT_INGRESS_BANDWIDTH 0x3FFF /* 0x3FFF => unlimit */ +#define QOS_DEFAULT_EGRESS_BANDWIDTH 0x3D08 /*( 0x3D08 + 1) * 64Kbps => 1Gbps*/ +#define QOS_DEFAULT_PREIFP 1 +#define QOS_DEFAULT_PACKET_USED_PAGES_FC 0x60 +#define QOS_DEFAULT_PACKET_USED_FC_EN 0 +#define QOS_DEFAULT_QUEUE_BASED_FC_EN 1 + +#define QOS_DEFAULT_PRIORITY_SELECT_PORT 8 +#define QOS_DEFAULT_PRIORITY_SELECT_1Q 0 +#define QOS_DEFAULT_PRIORITY_SELECT_ACL 0 +#define QOS_DEFAULT_PRIORITY_SELECT_DSCP 0 + +#define QOS_DEFAULT_DSCP_MAPPING_PRIORITY 0 + +#define QOS_DEFAULT_1Q_REMARKING_ABILITY 0 +#define QOS_DEFAULT_DSCP_REMARKING_ABILITY 0 +#define QOS_DEFAULT_QUEUE_GAP 20 +#define QOS_DEFAULT_QUEUE_NO_MAX 6 +#define QOS_DEFAULT_AVERAGE_PACKET_RATE 0x3FFF +#define QOS_DEFAULT_BURST_SIZE_IN_APR 0x3F +#define QOS_DEFAULT_PEAK_PACKET_RATE 2 +#define QOS_DEFAULT_SCHEDULER_ABILITY_APR 1 /*disable*/ +#define QOS_DEFAULT_SCHEDULER_ABILITY_PPR 1 /*disable*/ +#define QOS_DEFAULT_SCHEDULER_ABILITY_WFQ 1 /*disable*/ + +#define QOS_WEIGHT_MAX 127 + +#define RTK_MAX_NUM_OF_PRIORITY 8 +#define RTK_MAX_NUM_OF_QUEUE 8 + +#define RTK_PRIMAX 7 +#define RTK_QIDMAX 7 +#define RTK_DSCPMAX 63 + + +/* enum Priority Selection Index */ +typedef enum rtk_qos_priDecTbl_e +{ + PRIDECTBL_IDX0 = 0, + PRIDECTBL_IDX1, + PRIDECTBL_END, +}rtk_qos_priDecTbl_t; + + +/* Types of 802.1p remarking source */ +typedef enum rtk_qos_1pRmkSrc_e +{ + DOT1P_RMK_SRC_USER_PRI, + DOT1P_RMK_SRC_TAG_PRI, + DOT1P_RMK_SRC_END +} rtk_qos_1pRmkSrc_t; + + +/* Types of DSCP remarking source */ +typedef enum rtk_qos_dscpRmkSrc_e +{ + DSCP_RMK_SRC_INT_PRI, + DSCP_RMK_SRC_DSCP, + DSCP_RMK_SRC_USER_PRI, + DSCP_RMK_SRC_END +} rtk_qos_dscpRmkSrc_t; + +typedef struct rtk_priority_select_s +{ + rtk_uint32 port_pri; + rtk_uint32 dot1q_pri; + rtk_uint32 acl_pri; + rtk_uint32 dscp_pri;; + rtk_uint32 svlan_pri; +} rtk_priority_select_t; + +typedef struct rtk_qos_pri2queue_s +{ + rtk_uint32 pri2queue[RTK_MAX_NUM_OF_PRIORITY]; +} rtk_qos_pri2queue_t; + +typedef struct rtk_qos_queue_weights_s +{ + rtk_uint32 weights[RTK_MAX_NUM_OF_QUEUE]; +} rtk_qos_queue_weights_t; + +typedef enum rtk_qos_scheduling_type_e +{ + RTK_QOS_WFQ = 0, /* Weighted-Fair-Queue */ + RTK_QOS_SRR, /* Weighted-Round-Robin */ + SCHEDULING_TYPE_END +} rtk_qos_scheduling_type_t; + +typedef rtk_uint32 rtk_queue_num_t; /* queue number*/ + +/* Function Name: + * rtk_qos_init + * Description: + * Configure Qos default settings. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API will initialize related Qos setting. + */ +extern rtk_api_ret_t rtk_qos_init(void); + +/* Function Name: + * rtk_qos_priSel_set + * Description: + * Configure the priority order among different priority mechanism. + * Input: + * index - Priority decision table index (0~1) + * pPriDec - Priority assign for port, dscp, 802.1p, svlan, acl based priority decision. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_SEL_PRI_SOURCE - Invalid priority decision source parameter. + * Note: + * ASIC will follow user priority setting of mechanisms to select mapped queue priority for receiving frame. + * If two priority mechanisms are the same, the ASIC will chose the highest priority from mechanisms to + * assign queue priority to receiving frame. + * The priority sources are: + * - PRIDEC_PORT + * - PRIDEC_ACL + * - PRIDEC_DSCP + * - PRIDEC_1Q + * - PRIDEC_SVLAN + */ +extern rtk_api_ret_t rtk_qos_priSel_set(rtk_qos_priDecTbl_t index, rtk_priority_select_t *pPriDec); + +/* Function Name: + * rtk_qos_priSel_get + * Description: + * Get the priority order configuration among different priority mechanism. + * Input: + * index - Priority decision table index (0~1) + * Output: + * pPriDec - Priority assign for port, dscp, 802.1p, svlan, acl based priority decision . + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * ASIC will follow user priority setting of mechanisms to select mapped queue priority for receiving frame. + * If two priority mechanisms are the same, the ASIC will chose the highest priority from mechanisms to + * assign queue priority to receiving frame. + * The priority sources are: + * - PRIDEC_PORT, + * - PRIDEC_ACL, + * - PRIDEC_DSCP, + * - PRIDEC_1Q, + * - PRIDEC_SVLAN, + */ +extern rtk_api_ret_t rtk_qos_priSel_get(rtk_qos_priDecTbl_t index, rtk_priority_select_t *pPriDec); + +/* Function Name: + * rtk_qos_1pPriRemap_set + * Description: + * Configure 1Q priorities mapping to internal absolute priority. + * Input: + * dot1p_pri - 802.1p priority value. + * int_pri - internal priority value. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_VLAN_PRIORITY - Invalid 1p priority. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * Priority of 802.1Q assignment for internal asic priority, and it is used for queue usage and packet scheduling. + */ +extern rtk_api_ret_t rtk_qos_1pPriRemap_set(rtk_pri_t dot1p_pri, rtk_pri_t int_pri); + +/* Function Name: + * rtk_qos_1pPriRemap_get + * Description: + * Get 1Q priorities mapping to internal absolute priority. + * Input: + * dot1p_pri - 802.1p priority value . + * Output: + * pInt_pri - internal priority value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_VLAN_PRIORITY - Invalid priority. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * Priority of 802.1Q assigment for internal asic priority, and it is uesed for queue usage and packet scheduling. + */ +extern rtk_api_ret_t rtk_qos_1pPriRemap_get(rtk_pri_t dot1p_pri, rtk_pri_t *pInt_pri); + +/* Function Name: + * rtk_qos_dscpPriRemap_set + * Description: + * Map dscp value to internal priority. + * Input: + * dscp - Dscp value of receiving frame + * int_pri - internal priority value . + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_QOS_DSCP_VALUE - Invalid DSCP value. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * The Differentiated Service Code Point is a selector for router's per-hop behaviors. As a selector, there is no implication that a numerically + * greater DSCP implies a better network service. As can be seen, the DSCP totally overlaps the old precedence field of TOS. So if values of + * DSCP are carefully chosen then backward compatibility can be achieved. + */ +extern rtk_api_ret_t rtk_qos_dscpPriRemap_set(rtk_dscp_t dscp, rtk_pri_t int_pri); + +/* Function Name: + * rtk_qos_dscpPriRemap_get + * Description: + * Get dscp value to internal priority. + * Input: + * dscp - Dscp value of receiving frame + * Output: + * pInt_pri - internal priority value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_DSCP_VALUE - Invalid DSCP value. + * Note: + * The Differentiated Service Code Point is a selector for router's per-hop behaviors. As a selector, there is no implication that a numerically + * greater DSCP implies a better network service. As can be seen, the DSCP totally overlaps the old precedence field of TOS. So if values of + * DSCP are carefully chosen then backward compatibility can be achieved. + */ +extern rtk_api_ret_t rtk_qos_dscpPriRemap_get(rtk_dscp_t dscp, rtk_pri_t *pInt_pri); + +/* Function Name: + * rtk_qos_RspanPriRemap_set + * Description: + * Configure RSPAN priorities mapping to internal absolute priority. + * Input: + * rspan_pri - rspan priority value. + * int_pri - internal priority value. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_VLAN_PRIORITY - Invalid 1p priority. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * Priority of RSPAN assignment for internal asic priority, and it is used for queue usage and packet scheduling. + */ +extern rtk_api_ret_t rtk_qos_RspanPriRemap_set(rtk_pri_t rspan_pri, rtk_pri_t int_pri); + +/* Function Name: + * rtk_qos_RspanPriRemap_get + * Description: + * Get RSPAN priorities mapping to internal absolute priority. + * Input: + * rspan_pri - rspan priority value. + * Output: + * pInt_pri - internal priority value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_VLAN_PRIORITY - Invalid priority. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * Priority of RSPAN assigment for internal asic priority, and it is uesed for queue usage and packet scheduling. + */ +extern rtk_api_ret_t rtk_qos_RspanPriRemap_get(rtk_pri_t rspan_pri, rtk_pri_t *pInt_pri); + +/* Function Name: + * rtk_qos_portPri_set + * Description: + * Configure priority usage to each port. + * Input: + * port - Port id. + * int_pri - internal priority value. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_QOS_SEL_PORT_PRI - Invalid port priority. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * The API can set priority of port assignments for queue usage and packet scheduling. + */ +extern rtk_api_ret_t rtk_qos_portPri_set(rtk_port_t port, rtk_pri_t int_pri) ; + +/* Function Name: + * rtk_qos_portPri_get + * Description: + * Get priority usage to each port. + * Input: + * port - Port id. + * Output: + * pInt_pri - internal priority value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get priority of port assignments for queue usage and packet scheduling. + */ +extern rtk_api_ret_t rtk_qos_portPri_get(rtk_port_t port, rtk_pri_t *pInt_pri) ; + +/* Function Name: + * rtk_qos_priMap_set + * Description: + * Set output queue number for each port. + * Input: + * port - Port ID. + * pPri2qid - Priority mapping to queue ID. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_QUEUE_NUM - Invalid queue number. + * RT_ERR_QUEUE_ID - Invalid queue id. + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * ASIC supports priority mapping to queue with different internal available queue IDs. + */ +extern rtk_api_ret_t rtk_qos_priMap_set(rtk_port_t port, rtk_qos_pri2queue_t *pPri2qid); + +/* Function Name: + * dal_rtl8371c_qos_priMap_get + * Description: + * Get priority to queue ID mapping table parameters. + * Input: + * port - Port ID. + * Output: + * pPri2qid - Priority mapping to queue ID. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_QUEUE_NUM - Invalid queue number. + * Note: + * The API can return the mapping queue id of the specified priority. + */ +extern rtk_api_ret_t rtk_qos_priMap_get(rtk_port_t port, rtk_qos_pri2queue_t *pPri2qid); + +/* Function Name: + * rtk_qos_1pRemarkEnable_set + * Description: + * Set 1p Remarking state + * Input: + * port - Port id. + * enable - State of per-port 1p Remarking + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid enable parameter. + * Note: + * The API can enable or disable 802.1p remarking ability for whole system. + * The status of 802.1p remark: + * - DISABLED + * - ENABLED + */ +extern rtk_api_ret_t rtk_qos_1pRemarkEnable_set(rtk_port_t port, rtk_enable_t enable); + +/* Function Name: + * rtk_qos_1pRemarkEnable_get + * Description: + * Get 802.1p remarking ability. + * Input: + * port - Port id. + * Output: + * pEnable - Status of 802.1p remark. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get 802.1p remarking ability. + * The status of 802.1p remark: + * - DISABLED + * - ENABLED + */ +extern rtk_api_ret_t rtk_qos_1pRemarkEnable_get(rtk_port_t port, rtk_enable_t *pEnable); + +/* Function Name: + * rtk_qos_schedulingQueue_set + * Description: + * Set weight and type of queues in dedicated port. + * Input: + * port - Port id. + * pQweights - The array of weights for WRR/WFQ queue (0 for STRICT_PRIORITY queue). + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_QOS_QUEUE_WEIGHT - Invalid queue weight. + * Note: + * The API can set weight and type, strict priority or weight fair queue (WFQ) for + * dedicated port for using queues. If queue id is not included in queue usage, + * then its type and weight setting in dummy for setting. There are priorities + * as queue id in strict queues. It means strict queue id 5 carrying higher priority + * than strict queue id 4. The WFQ queue weight is from 1 to 128, and weight 0 is + * for strict priority queue type. + */ +extern rtk_api_ret_t rtk_qos_schedulingQueue_set(rtk_port_t port, rtk_qos_queue_weights_t *pQweights); + +/* Function Name: + * rtk_qos_schedulingQueue_get + * Description: + * Get weight and type of queues in dedicated port. + * Input: + * port - Port id. + * Output: + * pQweights - The array of weights for WRR/WFQ queue (0 for STRICT_PRIORITY queue). + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get weight and type, strict priority or weight fair queue (WFQ) for dedicated port for using queues. + * The WFQ queue weight is from 1 to 128, and weight 0 is for strict priority queue type. + */ +extern rtk_api_ret_t rtk_qos_schedulingQueue_get(rtk_port_t port, rtk_qos_queue_weights_t *pQweights); + +/* Function Name: + * rtk_qos_1pRemark_set + * Description: + * Set 802.1p remarking parameter. + * Input: + * int_pri - Internal priority value. + * dot1p_pri - 802.1p priority value. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_VLAN_PRIORITY - Invalid 1p priority. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * The API can set 802.1p parameters source priority and new priority. + */ +extern rtk_api_ret_t rtk_qos_1pRemark_set(rtk_pri_t int_pri, rtk_pri_t dot1p_pri); + +/* Function Name: + * rtk_qos_1pRemark_get + * Description: + * Get 802.1p remarking parameter. + * Input: + * int_pri - Internal priority value. + * Output: + * pDot1p_pri - 802.1p priority value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * The API can get 802.1p remarking parameters. It would return new priority of ingress priority. + */ +extern rtk_api_ret_t rtk_qos_1pRemark_get(rtk_pri_t int_pri, rtk_pri_t *pDot1p_pri); + +/* Function Name: + * rtk_qos_1pRemarkSrcSel_set + * Description: + * Set remarking source of 802.1p remarking. + * Input: + * type - remarking source + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + + * Note: + * The API can configure 802.1p remark functionality to map original 802.1p value or internal + * priority to TX DSCP value. + */ +extern rtk_api_ret_t rtk_qos_1pRemarkSrcSel_set(rtk_qos_1pRmkSrc_t type); + +/* Function Name: + * rtk_qos_1pRemarkSrcSel_get + * Description: + * Get remarking source of 802.1p remarking. + * Input: + * none + * Output: + * pType - remarking source + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None + */ +extern rtk_api_ret_t rtk_qos_1pRemarkSrcSel_get(rtk_qos_1pRmkSrc_t *pType); + +/* Function Name: + * rtk_qos_dscpRemarkEnable_set + * Description: + * Set DSCP remarking ability. + * Input: + * port - Port id. + * enable - status of DSCP remark. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * RT_ERR_ENABLE - Invalid enable parameter. + * Note: + * The API can enable or disable DSCP remarking ability for whole system. + * The status of DSCP remark: + * - DISABLED + * - ENABLED + */ +extern rtk_api_ret_t rtk_qos_dscpRemarkEnable_set(rtk_port_t port, rtk_enable_t enable); + +/* Function Name: + * rtk_qos_dscpRemarkEnable_get + * Description: + * Get DSCP remarking ability. + * Input: + * port - Port id. + * Output: + * pEnable - status of DSCP remarking. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get DSCP remarking ability. + * The status of DSCP remark: + * - DISABLED + * - ENABLED + */ +extern rtk_api_ret_t rtk_qos_dscpRemarkEnable_get(rtk_port_t port, rtk_enable_t *pEnable); + +/* Function Name: + * rtk_qos_intpri2dscp_Remark_set + * Description: + * Set DSCP remarking parameter. + * Input: + * int_pri - Internal priority value. + * dscp - remark DSCP value. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * RT_ERR_QOS_DSCP_VALUE - Invalid DSCP value. + * Note: + * The API can set internal priority to DSCP value. + */ +extern rtk_api_ret_t rtk_qos_intpri2dscp_Remark_set(rtk_pri_t int_pri, rtk_dscp_t dscp); + +/* Function Name: + * rtk_qos_intpri2dscp_Remark_get + * Description: + * Get DSCP remarking parameter. + * Input: + * int_pri - Internal priority value. + * Output: + * pDscp - remark DSCP value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * The API can get DSCP parameters. It would return DSCP value for mapping priority. + */ +extern rtk_api_ret_t rtk_qos_intpri2dscp_Remark_get(rtk_pri_t int_pri, rtk_dscp_t *pDscp); + +/* Function Name: + * rtk_qos_dscp2dscp_Remark_set + * Description: + * Set original DSCP remarking parameter. + * Input: + * ori_dscp - original dscp value. + * RmkDscp - remark DSCP value. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * RT_ERR_QOS_DSCP_VALUE - Invalid DSCP value. + * Note: + * The API can set original DSCP value to dscp value. + */ +rtk_api_ret_t rtk_qos_dscp2dscp_Remark_set(rtk_pri_t ori_dscp, rtk_dscp_t RmkDscp); + + +/* Function Name: + * rtk_qos_dscp2dscp_Remark_get + * Description: + * Get DSCP remarking parameter. + * Input: + * ori_dscp - original dscp value. + * Output: + * pRmkDscp - remark DSCP value. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_INT_PRIORITY - Invalid priority. + * Note: + * The API can get DSCP parameters. It would return DSCP value for mapping priority. + */ +rtk_api_ret_t rtk_qos_dscp2dscp_Remark_get(rtk_pri_t ori_dscp, rtk_dscp_t *pRmkDscp); + + +/* Function Name: + * rtk_qos_dscpRemarkSrcSel_set + * Description: + * Set remarking source of DSCP remarking. + * Input: + * type - remarking source + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + + * Note: + * The API can configure DSCP remark functionality to map original DSCP value or internal + * priority to TX DSCP value. + */ +extern rtk_api_ret_t rtk_qos_dscpRemarkSrcSel_set(rtk_qos_dscpRmkSrc_t type); + +/* Function Name: + * rtk_qos_dscpRemarkSrcSel_get + * Description: + * Get remarking source of DSCP remarking. + * Input: + * none + * Output: + * pType - remarking source + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * RT_ERR_NULL_POINTER - input parameter may be null pointer + + * Note: + * None + */ +extern rtk_api_ret_t rtk_qos_dscpRemarkSrcSel_get(rtk_qos_dscpRmkSrc_t *pType); + +/* Function Name: + * rtk_qos_portPriSelIndex_set + * Description: + * Configure priority decision index to each port. + * Input: + * port - Port id. + * index - priority decision index. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENTRY_INDEX - Invalid entry index. + * Note: + * The API can set priority of port assignments for queue usage and packet scheduling. + */ +extern rtk_api_ret_t rtk_qos_portPriSelIndex_set(rtk_port_t port, rtk_qos_priDecTbl_t index); + +/* Function Name: + * rtk_qos_portPriSelIndex_get + * Description: + * Get priority decision index from each port. + * Input: + * port - Port id. + * Output: + * pIndex - priority decision index. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get priority of port assignments for queue usage and packet scheduling. + */ +extern rtk_api_ret_t rtk_qos_portPriSelIndex_get(rtk_port_t port, rtk_qos_priDecTbl_t *pIndex); + +/* Function Name: + * rtk_qos_schedulingType_set + * Description: + * Configure type of scheduling. + * Input: + * queueType - Scheduling type. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_QOS_SCHE_TYPE - Invalid QoS scheduling type. + * Note: + * The API can set type of scheduling. + */ +extern rtk_api_ret_t rtk_qos_schedulingType_set(rtk_port_t port, rtk_qos_scheduling_type_t queueType); + +/* Function Name: + * rtk_qos_schedulingType_get + * Description: + * Get type of scheduling. + * Input: + * none. + * Output: + * pIndex - priority decision index. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - NULL pointer + * Note: + * The API can get type of scheduling. + */ +extern rtk_api_ret_t rtk_qos_schedulingType_get(rtk_port_t port, rtk_qos_scheduling_type_t *pQueueType); + + +#endif /* __RTK_API_QOS_H__ */ + diff --git a/sources/uboot-be550/drivers/net/rtl8372/rate.c b/sources/uboot-be550/drivers/net/rtl8372/rate.c new file mode 100755 index 00000000..c7142e81 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/rate.c @@ -0,0 +1,459 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8373 + * Feature : Here is a list of all functions and variables in ingress bandwitdh and egress bandwitdh module. + * + */ + +#include +#include +#include +#include + +#include + +/* Function Name: + * rtk_rate_igrBwCtrlPortEn_set + * Description: + * Enable or disable port ingress bandwidth control + * Input: + * port - Port id + * bwEn - enable ingress bandwidth control or not + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid IFG parameter. + * RT_ERR_INBW_RATE - Invalid ingress rate parameter. + * Note: + * + */ +rtk_api_ret_t rtk_rate_igrBwCtrlPortEn_set(rtk_port_t port, rtk_enable_t bwEn) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rate_igrBwCtrlPortEn_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rate_igrBwCtrlPortEn_set(port, bwEn); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_rate_igrBwCtrlPortEn_get + * Description: + * Enable or disable port ingress bandwidth control + * Input: + * port - Port id + * + * Output: + * pBwEn - Port ingress bandwidth control state + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid IFG parameter. + * RT_ERR_INBW_RATE - Invalid ingress rate parameter. + * Note: + * + */ +rtk_api_ret_t rtk_rate_igrBwCtrlPortEn_get(rtk_port_t port, rtk_enable_t *pBwEn) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rate_igrBwCtrlPortEn_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rate_igrBwCtrlPortEn_get(port, pBwEn); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_rate_igrBwCtrlRate_set + * Description: + * Set port ingress bandwidth control rate and FC config + * Input: + * port - Port id + * rate - Rate of share meter (uint: kpbs) + * fcEn - enable flow control or not, ENABLE:use flow control DISABLE:drop + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid IFG parameter. + * RT_ERR_INBW_RATE - Invalid ingress rate parameter. + * Note: + * The rate unit is 16 kbps and the range is from 16k to 10G. The granularity of rate is 16 kbps. + * The ifg_include parameter is used for rate calculation with/without inter-frame-gap and preamble. + */ +rtk_api_ret_t rtk_rate_igrBwCtrlRate_set(rtk_port_t port, rtk_rate_t rate, rtk_enable_t fcEn) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rate_igrBwCtrlRate_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rate_igrBwCtrlRate_set(port, rate, fcEn); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_rate_igrBwCtrlRate_get + * Description: + * Get port ingress bandwidth control rate and FC config + * Input: + * port - Port id + * + * Output: + * pRate - Rate of share meter(uint: kpbs) + * pFcEn - enable flow control or not, ENABLE:use flow control DISABLE:drop + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid IFG parameter. + * RT_ERR_INBW_RATE - Invalid ingress rate parameter. + * Note: + * The rate unit is 16 kbps and the range is from 16k to 10G. The granularity of rate is 16 kbps. + * The ifg_include parameter is used for rate calculation with/without inter-frame-gap and preamble. + */ +rtk_api_ret_t rtk_rate_igrBwCtrlRate_get(rtk_port_t port, rtk_rate_t *pRate, rtk_enable_t *pFcEn) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rate_igrBwCtrlRate_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rate_igrBwCtrlRate_get(port, pRate, pFcEn); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_rate_igrBwCtrlIfg_set + * Description: + * Set ingress bandwidth control include Preamble and IFG or not + * Input: + * ifgInclude - include or not, ENABLE:include DISABLE:exclude + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid IFG parameter. + * RT_ERR_INBW_RATE - Invalid ingress rate parameter. + * Note: + * + */ +rtk_api_ret_t rtk_rate_igrBwCtrlIfg_set(rtk_enable_t ifgInclude) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rate_igrBwCtrlIfg_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rate_igrBwCtrlIfg_set(ifgInclude); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_rate_igrBwCtrlIfg_get + * Description: + * Get ingress bandwidth control include 8B Preamble and 12B IFG or not + * Input: + * None + * Output: + * ifgInclude - include or not, ENABLE:include DISABLE:exclude + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid IFG parameter. + * RT_ERR_INBW_RATE - Invalid ingress rate parameter. + * Note: + * + */ +rtk_api_ret_t rtk_rate_igrBwCtrlIfg_get(rtk_enable_t *pIfgInclude) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rate_igrBwCtrlIfg_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rate_igrBwCtrlIfg_get(pIfgInclude); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_rate_igrBwCtrlCongestSts_get + * Description: + * Get port_n ingress bandwidth exceed leaky bucket high-on or not + * Input: + * port - port Idx + * Output: + * pCongestSts - Indicate ingress bandwidth exceed Pn_IGR_LB_ HIGH _ON for port n. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid IFG parameter. + * RT_ERR_INBW_RATE - Invalid ingress rate parameter. + * Note: + * + */ +rtk_api_ret_t rtk_rate_igrBwCtrlCongestSts_get(rtk_port_t port, rtk_rate_igrBwCongestSts_t *pCongestSts) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rate_igrBwCtrlCongestSts_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rate_igrBwCtrlCongestSts_get(port, pCongestSts); + RTK_API_UNLOCK(); + + return retVal; +} + + +/* Function Name: + * rtk_rate_egrBandwidthCtrlRate_set + * Description: + * Set port egress bandwidth control + * Input: + * port - Port id + * rate - Rate of egress bandwidth + * ifg_include - include IFG or not, ENABLE:include DISABLE:exclude + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_QOS_EBW_RATE - Invalid egress bandwidth/rate + * Note: + * The rate unit is 1 kbps and the range is from 8k to 1048568k. The granularity of rate is 8 kbps. + * The ifg_include parameter is used for rate calculation with/without inter-frame-gap and preamble. + */ +rtk_api_ret_t rtk_rate_egrBandwidthCtrlRate_set( rtk_port_t port, rtk_rate_t rate, rtk_enable_t ifg_include) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rate_egrBandwidthCtrlRate_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rate_egrBandwidthCtrlRate_set(port, rate, ifg_include); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_rate_egrBandwidthCtrlRate_get + * Description: + * Get port egress bandwidth control + * Input: + * port - Port id + * Output: + * pRate - Rate of egress bandwidth + * pIfg_include - Rate's calculation including IFG, ENABLE:include DISABLE:exclude + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The rate unit is 1 kbps and the range is from 8k to 1048568k. The granularity of rate is 8 kbps. + * The ifg_include parameter is used for rate calculation with/without inter-frame-gap and preamble. + */ +rtk_api_ret_t rtk_rate_egrBandwidthCtrlRate_get(rtk_port_t port, rtk_rate_t *pRate, rtk_enable_t *pIfg_include) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rate_egrBandwidthCtrlRate_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rate_egrBandwidthCtrlRate_get(port, pRate, pIfg_include); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_rate_egrQueueBwCtrlEnable_get + * Description: + * Get enable status of egress bandwidth control on specified queue. + * Input: + * unit - unit id + * port - port id + * queue - queue id + * Output: + * pEnable - Pointer to enable status of egress queue bandwidth control + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_QUEUE_ID - invalid queue id + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None + */ +rtk_api_ret_t rtk_rate_egrQueueBwCtrlEnable_get(rtk_port_t port, rtk_qid_t queue, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rate_egrQueueBwCtrlEnable_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rate_egrQueueBwCtrlEnable_get(port, queue, pEnable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_rate_egrQueueBwCtrlEnable_set + * Description: + * Set enable status of egress bandwidth control on specified queue. + * Input: + * port - port id + * queue - queue id + * enable - enable status of egress queue bandwidth control + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_QUEUE_ID - invalid queue id + * RT_ERR_INPUT - invalid input parameter + * Note: + * None + */ +rtk_api_ret_t rtk_rate_egrQueueBwCtrlEnable_set(rtk_port_t port, rtk_qid_t queue, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rate_egrQueueBwCtrlEnable_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rate_egrQueueBwCtrlEnable_set(port, queue, enable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_rate_egrQueueBwCtrlRate_get + * Description: + * Get rate of egress bandwidth control on specified queue. + * Input: + * port - port id + * queue - queue id + * pIndex - shared meter index + * Output: + * pRate - pointer to rate of egress queue bandwidth control + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_QUEUE_ID - invalid queue id + * RT_ERR_FILTER_METER_ID - Invalid meter id + * Note: + * The actual rate control is set in shared meters. + * The unit of granularity is 8Kbps. + */ +rtk_api_ret_t rtk_rate_egrQueueBwCtrlRate_get(rtk_port_t port, rtk_qid_t queue, rtk_meter_id_t *pIndex) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rate_egrQueueBwCtrlRate_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rate_egrQueueBwCtrlRate_get(port, queue, pIndex); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_rate_egrQueueBwCtrlRate_set + * Description: + * Set rate of egress bandwidth control on specified queue. + * Input: + * port - port id + * queue - queue id + * index - shared meter index + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_QUEUE_ID - invalid queue id + * RT_ERR_FILTER_METER_ID - Invalid meter id + * Note: + * The actual rate control is set in shared meters. + * The unit of granularity is 8Kbps. + */ +rtk_api_ret_t rtk_rate_egrQueueBwCtrlRate_set(rtk_port_t port, rtk_qid_t queue, rtk_meter_id_t index) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rate_egrQueueBwCtrlRate_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rate_egrQueueBwCtrlRate_set(port, queue, index); + RTK_API_UNLOCK(); + + return retVal; +} + + diff --git a/sources/uboot-be550/drivers/net/rtl8372/rate.h b/sources/uboot-be550/drivers/net/rtl8372/rate.h new file mode 100755 index 00000000..5fa459a9 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/rate.h @@ -0,0 +1,315 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8373 switch high-level API + * + * Feature : The file includes ingress bandwidth control module high-layer API defination + * + */ + +#ifndef __RTK_API_RATE_H__ +#define __RTK_API_RATE_H__ + +#define INBW_CTRL_RATE_MAX (0xFFFFF * 16) +#define INBW_CTRL_MAX_PORT_ID (8) + +#define EBW_CTRL_RATE_MAX (0xFFFFF * 16) +#define EBW_CTRL_MAX_PORT_ID (8) + + +typedef enum rtk_rate_igrBwCongestSts_e +{ + INBW_RATE_NOT_EXCEED = 0, + INBW_RATE_EXCEED, + INBW_RATE_STATE_END +} rtk_rate_igrBwCongestSts_t; + + +/* Function Name: + * rtk_rate_igrBwCtrlPortEn_set + * Description: + * Enable or disable port ingress bandwidth control + * Input: + * port - Port id + * bwEn - enable ingress bandwidth control or not + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid IFG parameter. + * RT_ERR_INBW_RATE - Invalid ingress rate parameter. + * Note: + * + */ +extern rtk_api_ret_t rtk_rate_igrBwCtrlPortEn_set(rtk_port_t port, rtk_enable_t bwEn); + +/* Function Name: + * rtk_rate_igrBwCtrlPortEn_get + * Description: + * Enable or disable port ingress bandwidth control + * Input: + * port - Port id + * + * Output: + * pBwEn - Port ingress bandwidth control state + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid IFG parameter. + * RT_ERR_INBW_RATE - Invalid ingress rate parameter. + * Note: + * + */ +extern rtk_api_ret_t rtk_rate_igrBwCtrlPortEn_get(rtk_port_t port, rtk_enable_t *pBwEn); + +/* Function Name: + * rtk_rate_igrBwCtrlRate_set + * Description: + * Set port ingress bandwidth control rate and FC config + * Input: + * port - Port id + * rate - Rate of share meter(uint: kpbs) + * fcEn - enable flow control or not, ENABLE:use flow control DISABLE:drop + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid IFG parameter. + * RT_ERR_INBW_RATE - Invalid ingress rate parameter. + * Note: + * The rate unit is 16 kbps and the range is from 16k to 10G. The granularity of rate is 16 kbps. + * The ifg_include parameter is used for rate calculation with/without inter-frame-gap and preamble. + */ +extern rtk_api_ret_t rtk_rate_igrBwCtrlRate_set(rtk_port_t port, rtk_rate_t rate, rtk_enable_t fcEn); + +/* Function Name: + * rtk_rate_igrBwCtrlRate_get + * Description: + * Get port ingress bandwidth control rate and FC config + * Input: + * port - Port id + * + * Output: + * pRate - Rate of share meter(uint: kpbs) + * pFcEn - enable flow control or not, ENABLE:use flow control DISABLE:drop + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid IFG parameter. + * RT_ERR_INBW_RATE - Invalid ingress rate parameter. + * Note: + * The rate unit is 16 kbps and the range is from 16k to 10G. The granularity of rate is 16 kbps. + * The ifg_include parameter is used for rate calculation with/without inter-frame-gap and preamble. + */ +extern rtk_api_ret_t rtk_rate_igrBwCtrlRate_get(rtk_port_t port, rtk_rate_t *pRate, rtk_enable_t *pFcEn); + +/* Function Name: + * rtk_rate_igrBwCtrlIfg_set + * Description: + * Set ingress bandwidth control include Preamble and IFG or not + * Input: + * ifgInclude - include or not, ENABLE:include DISABLE:exclude + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid IFG parameter. + * RT_ERR_INBW_RATE - Invalid ingress rate parameter. + * Note: + * + */ +extern rtk_api_ret_t rtk_rate_igrBwCtrlIfg_set(rtk_enable_t ifgInclude); + +/* Function Name: + * rtk_rate_igrBwCtrlIfg_get + * Description: + * Get ingress bandwidth control include 8B Preamble and 12B IFG or not + * Input: + * None + * Output: + * ifgInclude - include or not, ENABLE:include DISABLE:exclude + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid IFG parameter. + * RT_ERR_INBW_RATE - Invalid ingress rate parameter. + * Note: + * + */ +extern rtk_api_ret_t rtk_rate_igrBwCtrlIfg_get(rtk_enable_t *pIfgInclude); + +/* Function Name: + * rtk_rate_igrBwCtrlCongestSts_get + * Description: + * Get port_n ingress bandwidth exceed leaky bucket high-on or not + * Input: + * port - port Idx + * Output: + * pCongestSts - Indicate ingress bandwidth exceed Pn_IGR_LB_ HIGH _ON for port n. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid IFG parameter. + * RT_ERR_INBW_RATE - Invalid ingress rate parameter. + * Note: + * + */ +extern rtk_api_ret_t rtk_rate_igrBwCtrlCongestSts_get(rtk_port_t port, rtk_rate_igrBwCongestSts_t *pCongestSts); + +/* Function Name: + * rtk_rate_egrBandwidthCtrlRate_set + * Description: + * Set port egress bandwidth control + * Input: + * port - Port id + * rate - Rate of egress bandwidth + * ifg_include - include IFG or not, ENABLE:include DISABLE:exclude + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_QOS_EBW_RATE - Invalid egress bandwidth/rate + * Note: + * The rate unit is 1 kbps and the range is from 8k to 1048568k. The granularity of rate is 8 kbps. + * The ifg_include parameter is used for rate calculation with/without inter-frame-gap and preamble. + */ +extern rtk_api_ret_t rtk_rate_egrBandwidthCtrlRate_set( rtk_port_t port, rtk_rate_t rate, rtk_enable_t ifg_include); + +/* Function Name: + * rtk_rate_egrBandwidthCtrlRate_get + * Description: + * Get port egress bandwidth control + * Input: + * port - Port id + * Output: + * pRate - Rate of egress bandwidth + * pIfg_include - Rate's calculation including IFG, ENABLE:include DISABLE:exclude + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The rate unit is 1 kbps and the range is from 8k to 1048568k. The granularity of rate is 8 kbps. + * The ifg_include parameter is used for rate calculation with/without inter-frame-gap and preamble. + */ +extern rtk_api_ret_t rtk_rate_egrBandwidthCtrlRate_get(rtk_port_t port, rtk_rate_t *pRate, rtk_enable_t *pIfg_include); + +/* Function Name: + * rtk_rate_egrQueueBwCtrlEnable_get + * Description: + * Get enable status of egress bandwidth control on specified queue. + * Input: + * unit - unit id + * port - port id + * queue - queue id + * Output: + * pEnable - Pointer to enable status of egress queue bandwidth control + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_QUEUE_ID - invalid queue id + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None + */ +extern rtk_api_ret_t rtk_rate_egrQueueBwCtrlEnable_get(rtk_port_t port, rtk_qid_t queue, rtk_enable_t *pEnable); + +/* Function Name: + * rtk_rate_egrQueueBwCtrlEnable_set + * Description: + * Set enable status of egress bandwidth control on specified queue. + * Input: + * port - port id + * queue - queue id + * enable - enable status of egress queue bandwidth control + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_QUEUE_ID - invalid queue id + * RT_ERR_INPUT - invalid input parameter + * Note: + * None + */ +extern rtk_api_ret_t rtk_rate_egrQueueBwCtrlEnable_set(rtk_port_t port, rtk_qid_t queue, rtk_enable_t enable); + +/* Function Name: + * rtk_rate_egrQueueBwCtrlRate_get + * Description: + * Get rate of egress bandwidth control on specified queue. + * Input: + * port - port id + * queue - queue id + * pIndex - shared meter index + * Output: + * pRate - pointer to rate of egress queue bandwidth control + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_QUEUE_ID - invalid queue id + * RT_ERR_FILTER_METER_ID - Invalid meter id + * Note: + * The actual rate control is set in shared meters. + * The unit of granularity is 8Kbps. + */ +extern rtk_api_ret_t rtk_rate_egrQueueBwCtrlRate_get(rtk_port_t port, rtk_qid_t queue, rtk_meter_id_t *pIndex); + +/* Function Name: + * rtk_rate_egrQueueBwCtrlRate_set + * Description: + * Set rate of egress bandwidth control on specified queue. + * Input: + * port - port id + * queue - queue id + * index - shared meter index + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_QUEUE_ID - invalid queue id + * RT_ERR_FILTER_METER_ID - Invalid meter id + * Note: + * The actual rate control is set in shared meters. + * The unit of granularity is 8Kbps. + */ +extern rtk_api_ret_t rtk_rate_egrQueueBwCtrlRate_set(rtk_port_t port, rtk_qid_t queue, rtk_meter_id_t index); + + + +#endif /* __RTK_API_RATE_H__ */ + + diff --git a/sources/uboot-be550/drivers/net/rtl8372/rldp.c b/sources/uboot-be550/drivers/net/rtl8372/rldp.c new file mode 100755 index 00000000..997b1ece --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/rldp.c @@ -0,0 +1,278 @@ +/* + * Copyright (C) 2012 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision: $ + * $Date: $ + * + * Purpose : Declaration of RLDP and RLPP API + * + * Feature : The file have include the following module and sub-modules + * 1) RLDP and RLPP configuration and status + * + */ + + +/* + * Include Files + */ +#include +#include + +#include +#if 1 + +/* Function Name: + * rtk_rldp_config_set + * Description: + * Set RLDP module configuration + * Input: + * pConfig - configuration structure of RLDP + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT + * RT_ERR_NULL_POINTER + * Note: + * None + */ +rtk_api_ret_t rtk_rldp_config_set(rtk_rldp_config_t *pConfig) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rldp_config_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rldp_config_set(pConfig); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_rldp_config_get + * Description: + * Get RLDP module configuration + * Input: + * None + * Output: + * pConfig - configuration structure of RLDP + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT + * RT_ERR_NULL_POINTER + * Note: + * None + */ +rtk_api_ret_t rtk_rldp_config_get(rtk_rldp_config_t *pConfig) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rldp_config_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rldp_config_get(pConfig); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_rldp_portConfig_set + * Description: + * Set per port RLDP module configuration + * Input: + * port - port number to be configured + * pPortConfig - per port configuration structure of RLDP + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT + * RT_ERR_NULL_POINTER + * Note: + * None + */ +rtk_api_ret_t rtk_rldp_portConfig_set(rtk_port_t port, rtk_rldp_portConfig_t *pPortConfig) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rldp_portConfig_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rldp_portConfig_set(port, pPortConfig); + RTK_API_UNLOCK(); + + return retVal; +} /* end of rtk_rldp_portConfig_set */ + + +/* Function Name: + * rtk_rldp_portConfig_get + * Description: + * Get per port RLDP module configuration + * Input: + * port - port number to be get + * Output: + * pPortConfig - per port configuration structure of RLDP + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT + * RT_ERR_NULL_POINTER + * Note: + * None + */ +rtk_api_ret_t rtk_rldp_portConfig_get(rtk_port_t port, rtk_rldp_portConfig_t *pPortConfig) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rldp_portConfig_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rldp_portConfig_get(port, pPortConfig); + RTK_API_UNLOCK(); + + return retVal; +} /* end of rtk_rldp_portConfig_get */ + + +/* Function Name: + * rtk_rldp_status_get + * Description: + * Get RLDP module status + * Input: + * None + * Output: + * pStatus - status structure of RLDP + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NULL_POINTER + * Note: + * None + */ +rtk_api_ret_t rtk_rldp_status_get(rtk_rldp_status_t *pStatus) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rldp_status_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rldp_status_get(pStatus); + RTK_API_UNLOCK(); + + return retVal; +} /* end of rtk_rldp_status_get */ + + +/* Function Name: + * rtk_rldp_portStatus_get + * Description: + * Get RLDP module status + * Input: + * port - port number to be get + * Output: + * pPortStatus - per port status structure of RLDP + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT + * RT_ERR_NULL_POINTER + * Note: + * None + */ +rtk_api_ret_t rtk_rldp_portStatus_get(rtk_port_t port, rtk_rldp_portStatus_t *pPortStatus) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rldp_portStatus_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rldp_portStatus_get(port, pPortStatus); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_rldp_portStatus_set + * Description: + * Clear RLDP module status + * Input: + * port - port number to be clear + * pPortStatus - per port status structure of RLDP + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT + * RT_ERR_NULL_POINTER + * Note: + * Clear operation effect loop_enter and loop_leave only, other field in + * the structure are don't care. Loop status cab't be clean. + */ +rtk_api_ret_t rtk_rldp_portStatus_set(rtk_port_t port, rtk_rldp_portStatus_t *pPortStatus) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rldp_portStatus_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rldp_portStatus_set(port, pPortStatus); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_rldp_portLoopPair_get + * Description: + * Get RLDP port loop pairs + * Input: + * port - port number to be get + * Output: + * pPortmask - per port related loop ports + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT + * RT_ERR_NULL_POINTER + * Note: + * None + */ +rtk_api_ret_t rtk_rldp_portLoopPair_get(rtk_port_t port, rtk_portmask_t *pPortmask) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rldp_portLoopPair_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rldp_portLoopPair_get(port, pPortmask); + RTK_API_UNLOCK(); + + return retVal; +} +#endif + + diff --git a/sources/uboot-be550/drivers/net/rtl8372/rldp.h b/sources/uboot-be550/drivers/net/rtl8372/rldp.h new file mode 100755 index 00000000..bf2f044a --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/rldp.h @@ -0,0 +1,266 @@ +/* + * Copyright (C) 2012 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision: $ + * $Date: $ + * + * Purpose : Declaration of RLDP and RLPP API + * + * Feature : The file have include the following module and sub-modules + * 1) RLDP and RLPP configuration and status + * + */ + + +#ifndef __RTK_RLDP_H__ +#define __RTK_RLDP_H__ + + +/* + * Include Files + */ + + +/* + * Symbol Definition + */ +typedef enum rtk_rldp_trigger_e +{ + RTK_RLDP_TRIGGER_SAMOVING = 0, + RTK_RLDP_TRIGGER_PERIOD, + RTK_RLDP_TRIGGER_END +} rtk_rldp_trigger_t; + +typedef enum rtk_rldp_cmpType_e +{ + RTK_RLDP_CMPTYPE_MAGIC = 0, /* Compare the RLDP with magic only */ + RTK_RLDP_CMPTYPE_MAGIC_ID, /* Compare the RLDP with both magic + ID */ + RTK_RLDP_CMPTYPE_END +} rtk_rldp_cmpType_t; + +typedef enum rtk_rldp_loopStatus_e +{ + RTK_RLDP_LOOPSTS_NONE = 0, + RTK_RLDP_LOOPSTS_LOOPING, + RTK_RLDP_LOOPSTS_END +} rtk_rldp_loopStatus_t; + +typedef enum rtk_rlpp_trapType_e +{ + RTK_RLPP_TRAPTYPE_NONE = 0, + RTK_RLPP_TRAPTYPE_CPU, + RTK_RLPP_TRAPTYPE_END +} rtk_rlpp_trapType_t; + +typedef struct rtk_rldp_config_s +{ + rtk_enable_t rldp_enable; + rtk_rldp_trigger_t trigger_mode; + rtk_mac_t magic; + rtk_rldp_cmpType_t compare_type; + rtk_uint32 interval_check; /* Checking interval for check state */ + rtk_uint32 num_check; /* Checking number for check state */ + rtk_uint32 interval_loop; /* Checking interval for loop state */ + rtk_uint32 num_loop; /* Checking number for loop state */ +} rtk_rldp_config_t; + +typedef struct rtk_rldp_portConfig_s +{ + rtk_enable_t tx_enable; +} rtk_rldp_portConfig_t; + +typedef struct rtk_rldp_status_s +{ + rtk_mac_t id; +} rtk_rldp_status_t; + +typedef struct rtk_rldp_portStatus_s +{ + rtk_rldp_loopStatus_t loop_status; + rtk_rldp_loopStatus_t loop_enter; + rtk_rldp_loopStatus_t loop_leave; +} rtk_rldp_portStatus_t; + +/* + * Data Declaration + */ + + +/* + * Macro Declaration + */ + +#define RTK_RLDP_INTERVAL_MAX 0xffff +#define RTK_RLDP_NUM_MAX 0xff + + +/* + * Function Declaration + */ + +/* Module Name : RLDP */ + + +/* Function Name: + * rtk_rldp_config_set + * Description: + * Set RLDP module configuration + * Input: + * pConfig - configuration structure of RLDP + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT + * RT_ERR_NULL_POINTER + * Note: + * None + */ +extern rtk_api_ret_t rtk_rldp_config_set(rtk_rldp_config_t *pConfig); + + +/* Function Name: + * rtk_rldp_config_get + * Description: + * Get RLDP module configuration + * Input: + * None + * Output: + * pConfig - configuration structure of RLDP + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT + * RT_ERR_NULL_POINTER + * Note: + * None + */ +extern rtk_api_ret_t rtk_rldp_config_get(rtk_rldp_config_t *pConfig); + + +/* Function Name: + * rtk_rldp_portConfig_set + * Description: + * Set per port RLDP module configuration + * Input: + * port - port number to be configured + * pPortConfig - per port configuration structure of RLDP + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT + * RT_ERR_NULL_POINTER + * Note: + * None + */ +extern rtk_api_ret_t rtk_rldp_portConfig_set(rtk_port_t port, rtk_rldp_portConfig_t *pPortConfig); + + +/* Function Name: + * rtk_rldp_portConfig_get + * Description: + * Get per port RLDP module configuration + * Input: + * port - port number to be get + * Output: + * pPortConfig - per port configuration structure of RLDP + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT + * RT_ERR_NULL_POINTER + * Note: + * None + */ +extern rtk_api_ret_t rtk_rldp_portConfig_get(rtk_port_t port, rtk_rldp_portConfig_t *pPortConfig); + + +/* Function Name: + * rtk_rldp_status_get + * Description: + * Get RLDP module status + * Input: + * None + * Output: + * pStatus - status structure of RLDP + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NULL_POINTER + * Note: + * None + */ +extern rtk_api_ret_t rtk_rldp_status_get(rtk_rldp_status_t *pStatus); + + +/* Function Name: + * rtk_rldp_portStatus_get + * Description: + * Get RLDP module status + * Input: + * port - port number to be get + * Output: + * pPortStatus - per port status structure of RLDP + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT + * RT_ERR_NULL_POINTER + * Note: + * None + */ +extern rtk_api_ret_t rtk_rldp_portStatus_get(rtk_port_t port, rtk_rldp_portStatus_t *pPortStatus); + + +/* Function Name: + * rtk_rldp_portStatus_clear + * Description: + * Clear RLDP module status + * Input: + * port - port number to be clear + * pPortStatus - per port status structure of RLDP + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT + * RT_ERR_NULL_POINTER + * Note: + * Clear operation effect loop_enter and loop_leave only, other field in + * the structure are don't care + */ +extern rtk_api_ret_t rtk_rldp_portStatus_set(rtk_port_t port, rtk_rldp_portStatus_t *pPortStatus); + + +/* Function Name: + * rtk_rldp_portLoopPair_get + * Description: + * Get RLDP port loop pairs + * Input: + * port - port number to be get + * Output: + * pPortmask - per port related loop ports + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT + * RT_ERR_NULL_POINTER + * Note: + * None + */ +extern rtk_api_ret_t rtk_rldp_portLoopPair_get(rtk_port_t port, rtk_portmask_t *pPortmask); + +#endif /* __RTK_RLDP_H__ */ + diff --git a/sources/uboot-be550/drivers/net/rtl8372/rma.c b/sources/uboot-be550/drivers/net/rtl8372/rma.c new file mode 100755 index 00000000..62bbe303 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/rma.c @@ -0,0 +1,103 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8373 + * Feature : Here is a list of all functions and variables in RMA module. + * + */ + +#include +#include +#include +#include + +#include + + + +/* Function Name: + * rtk_rma_set + * Description: + * Set RMA action, priority & leaky function. + * Input: + * rmaAddr: 0x00 ~ 0x2f + * rmaParam: + * operation; + * discard_storm_filter; + * trap_priority; + * keep_format; + * vlan_leaky; + * portiso_leaky; + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * Reset MIB counter of ports. API will use global reset while port mask is all-ports. + */ +rtk_api_ret_t rtk_rma_set(rtk_uint32 rmaAddr, rtk_rmaParam_t* rmaParam) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rma_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rma_set(rmaAddr, rmaParam); + RTK_API_UNLOCK(); + + return retVal; +} + + + +/* Function Name: + * rtk_rma_get + * Description: + * Get RMA action, priority & leaky function. + * Input: + * rmaAddr: 0x00 ~ 0x2f + * rmaParam: + * operation; + * discard_storm_filter; + * trap_priority; + * keep_format; + * vlan_leaky; + * portiso_leaky; + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * Reset MIB counter of ports. API will use global reset while port mask is all-ports. + */ +rtk_api_ret_t rtk_rma_get(rtk_uint32 rmaAddr, rtk_rmaParam_t* rmaParam) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rma_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rma_get(rmaAddr, rmaParam); + RTK_API_UNLOCK(); + + return retVal; +} + + diff --git a/sources/uboot-be550/drivers/net/rtl8372/rma.h b/sources/uboot-be550/drivers/net/rtl8372/rma.h new file mode 100755 index 00000000..5638facc --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/rma.h @@ -0,0 +1,100 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8373 switch high-level API + * + * Feature : The file includes MIB module high-layer API defination + * + */ + +#ifndef __RTK_API_RMA_H__ +#define __RTK_API_RMA_H__ + + +enum RTK_RMAOP +{ + RMAOP_FORWARD = 0, + RMAOP_TRAP_TO_CPU, + RMAOP_DROP, + RMAOP_FORWARD_EXCLUDE_CPU, + RMAOP_END +}; + + + + + +typedef struct rtk_rmaParam_s{ + + rtk_uint32 operation; + rtk_uint32 discard_storm_filter; + rtk_uint32 trap_priority; + rtk_uint32 keep_format; + rtk_uint32 vlan_leaky; + rtk_uint32 portiso_leaky; + +}rtk_rmaParam_t; + + +/* Function Name: + * rtk_rma_set + * Description: + * Set RMA action, priority & leaky function. + * Input: + * rmaAddr: 0x00 ~ 0x2f + * rmaParam: + * operation; + * discard_storm_filter; + * trap_priority; + * keep_format; + * vlan_leaky; + * portiso_leaky; + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * Reset MIB counter of ports. API will use global reset while port mask is all-ports. + */ +extern rtk_api_ret_t rtk_rma_set(rtk_uint32 rmaAddr, rtk_rmaParam_t* rmaParam); + + +/* Function Name: + * rtk_rma_get + * Description: + * Get RMA action, priority & leaky function. + * Input: + * rmaAddr: 0x00 ~ 0x2f + * rmaParam: + * operation; + * discard_storm_filter; + * trap_priority; + * keep_format; + * vlan_leaky; + * portiso_leaky; + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * Reset MIB counter of ports. API will use global reset while port mask is all-ports. + */ +extern rtk_api_ret_t rtk_rma_get(rtk_uint32 rmaAddr, rtk_rmaParam_t* rmaParam); + + + + +#endif /* __RTK_API_RMA_H__ */ + diff --git a/sources/uboot-be550/drivers/net/rtl8372/rtk_error.h b/sources/uboot-be550/drivers/net/rtl8372/rtk_error.h new file mode 100755 index 00000000..94914201 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/rtk_error.h @@ -0,0 +1,255 @@ +/* + * Copyright(c) Realtek Semiconductor Corporation, 2008 + * All rights reserved. + * + * $Revision$ + * $Date$ + * + * Purpose : Definition the error number in the SDK. + * + * Feature : error definition + * + */ + +#ifndef __COMMON_RT_ERROR_H__ +#define __COMMON_RT_ERROR_H__ + +/* + * Include Files + */ + +/* + * Data Type Declaration + */ +typedef enum rt_error_code_e +{ + RT_ERR_FAILED = -1, /* General Error */ + + /* 0x0000xxxx for common error code */ + RT_ERR_OK = 0, /* 0x00000000, OK */ + RT_ERR_INPUT, /* 0x00000001, invalid input parameter */ + RT_ERR_UNIT_ID, /* 0x00000002, invalid unit id */ + RT_ERR_PORT_ID, /* 0x00000003, invalid port id */ + RT_ERR_PORT_MASK, /* 0x00000004, invalid port mask */ + RT_ERR_PORT_LINKDOWN, /* 0x00000005, link down port status */ + RT_ERR_ENTRY_INDEX, /* 0x00000006, invalid entry index */ + RT_ERR_NULL_POINTER, /* 0x00000007, input parameter is null pointer */ + RT_ERR_QUEUE_ID, /* 0x00000008, invalid queue id */ + RT_ERR_QUEUE_NUM, /* 0x00000009, invalid queue number */ + RT_ERR_BUSYWAIT_TIMEOUT, /* 0x0000000a, busy watting time out */ + RT_ERR_MAC, /* 0x0000000b, invalid mac address */ + RT_ERR_OUT_OF_RANGE, /* 0x0000000c, input parameter out of range */ + RT_ERR_CHIP_NOT_SUPPORTED, /* 0x0000000d, functions not supported by this chip model */ + RT_ERR_SMI, /* 0x0000000e, SMI error */ + RT_ERR_NOT_INIT, /* 0x0000000f, The module is not initial */ + RT_ERR_CHIP_NOT_FOUND, /* 0x00000010, The chip can not found */ + RT_ERR_NOT_ALLOWED, /* 0x00000011, actions not allowed by the function */ + RT_ERR_DRIVER_NOT_FOUND, /* 0x00000012, The driver can not found */ + RT_ERR_SEM_LOCK_FAILED, /* 0x00000013, Failed to lock semaphore */ + RT_ERR_SEM_UNLOCK_FAILED, /* 0x00000014, Failed to unlock semaphore */ + RT_ERR_ENABLE, /* 0x00000015, invalid enable parameter */ + RT_ERR_TBL_FULL, /* 0x00000016, input table full */ + RT_ERR_RANGE, /* 0x00000017, out of range*/ + + /* 0x0001xxxx for vlan */ + RT_ERR_VLAN_VID = 0x00010000, /* 0x00010000, invalid vid */ + RT_ERR_VLAN_PRIORITY, /* 0x00010001, invalid 1p priority */ + RT_ERR_VLAN_EMPTY_ENTRY, /* 0x00010002, emtpy entry of vlan table */ + RT_ERR_VLAN_ACCEPT_FRAME_TYPE, /* 0x00010003, invalid accept frame type */ + RT_ERR_VLAN_EXIST, /* 0x00010004, vlan is exist */ + RT_ERR_VLAN_ENTRY_NOT_FOUND, /* 0x00010005, specified vlan entry not found */ + RT_ERR_VLAN_PORT_MBR_EXIST, /* 0x00010006, member port exist in the specified vlan */ + RT_ERR_VLAN_PROTO_AND_PORT, /* 0x00010008, invalid protocol and port based vlan */ + + /* 0x0002xxxx for svlan */ + RT_ERR_SVLAN_ENTRY_INDEX = 0x00020000, /* 0x00020000, invalid svid entry no */ + RT_ERR_SVLAN_ETHER_TYPE, /* 0x00020001, invalid SVLAN ether type */ + RT_ERR_SVLAN_TABLE_FULL, /* 0x00020002, no empty entry in SVLAN table */ + RT_ERR_SVLAN_ENTRY_NOT_FOUND, /* 0x00020003, specified svlan entry not found */ + RT_ERR_SVLAN_EXIST, /* 0x00020004, SVLAN entry is exist */ + RT_ERR_SVLAN_VID, /* 0x00020005, invalid svid */ + + /* 0x0003xxxx for MSTP */ + RT_ERR_MSTI = 0x00030000, /* 0x00030000, invalid msti */ + RT_ERR_MSTP_STATE, /* 0x00030001, invalid spanning tree status */ + RT_ERR_MSTI_EXIST, /* 0x00030002, MSTI exist */ + RT_ERR_MSTI_NOT_EXIST, /* 0x00030003, MSTI not exist */ + + /* 0x0004xxxx for BUCKET */ + RT_ERR_TIMESLOT = 0x00040000, /* 0x00040000, invalid time slot */ + RT_ERR_TOKEN, /* 0x00040001, invalid token amount */ + RT_ERR_RATE, /* 0x00040002, invalid rate */ + RT_ERR_TICK, /* 0x00040003, invalid tick */ + + /* 0x0005xxxx for RMA */ + RT_ERR_RMA_ADDR = 0x00050000, /* 0x00050000, invalid rma mac address */ + RT_ERR_RMA_ACTION, /* 0x00050001, invalid rma action */ + + /* 0x0006xxxx for L2 */ + RT_ERR_L2_HASH_KEY = 0x00060000, /* 0x00060000, invalid L2 Hash key */ + RT_ERR_L2_HASH_INDEX, /* 0x00060001, invalid L2 Hash index */ + RT_ERR_L2_CAM_INDEX, /* 0x00060002, invalid L2 CAM index */ + RT_ERR_L2_ENRTYSEL, /* 0x00060003, invalid EntrySel */ + RT_ERR_L2_INDEXTABLE_INDEX, /* 0x00060004, invalid L2 index table(=portMask table) index */ + RT_ERR_LIMITED_L2ENTRY_NUM, /* 0x00060005, invalid limited L2 entry number */ + RT_ERR_L2_AGGREG_PORT, /* 0x00060006, this aggregated port is not the lowest physical + port of its aggregation group */ + RT_ERR_L2_FID, /* 0x00060007, invalid fid */ + RT_ERR_L2_VID, /* 0x00060008, invalid cvid */ + RT_ERR_L2_NO_EMPTY_ENTRY, /* 0x00060009, no empty entry in L2 table */ + RT_ERR_L2_ENTRY_NOTFOUND, /* 0x0006000a, specified entry not found */ + RT_ERR_L2_INDEXTBL_FULL, /* 0x0006000b, the L2 index table is full */ + RT_ERR_L2_INVALID_FLOWTYPE, /* 0x0006000c, invalid L2 flow type */ + RT_ERR_L2_L2UNI_PARAM, /* 0x0006000d, invalid L2 unicast parameter */ + RT_ERR_L2_L2MULTI_PARAM, /* 0x0006000e, invalid L2 multicast parameter */ + RT_ERR_L2_IPMULTI_PARAM, /* 0x0006000f, invalid L2 ip multicast parameter */ + RT_ERR_L2_PARTIAL_HASH_KEY, /* 0x00060010, invalid L2 partial Hash key */ + RT_ERR_L2_EMPTY_ENTRY, /* 0x00060011, the entry is empty(invalid) */ + RT_ERR_L2_FLUSH_TYPE, /* 0x00060012, the flush type is invalid */ + RT_ERR_L2_NO_CPU_PORT, /* 0x00060013, CPU port not exist */ + + /* 0x0007xxxx for FILTER (PIE) */ + RT_ERR_FILTER_BLOCKNUM = 0x00070000, /* 0x00070000, invalid block number */ + RT_ERR_FILTER_ENTRYIDX, /* 0x00070001, invalid entry index */ + RT_ERR_FILTER_CUTLINE, /* 0x00070002, invalid cutline value */ + RT_ERR_FILTER_FLOWTBLBLOCK, /* 0x00070003, block belongs to flow table */ + RT_ERR_FILTER_INACLBLOCK, /* 0x00070004, block belongs to ingress ACL */ + RT_ERR_FILTER_ACTION, /* 0x00070005, action doesn't consist to entry type */ + RT_ERR_FILTER_INACL_RULENUM, /* 0x00070006, invalid ACL rulenum */ + RT_ERR_FILTER_INACL_TYPE, /* 0x00070007, entry type isn't an ingress ACL rule */ + RT_ERR_FILTER_INACL_EXIST, /* 0x00070008, ACL entry is already exit */ + RT_ERR_FILTER_INACL_EMPTY, /* 0x00070009, ACL entry is empty */ + RT_ERR_FILTER_FLOWTBL_TYPE, /* 0x0007000a, entry type isn't an flow table rule */ + RT_ERR_FILTER_FLOWTBL_RULENUM, /* 0x0007000b, invalid flow table rulenum */ + RT_ERR_FILTER_FLOWTBL_EMPTY, /* 0x0007000c, flow table entry is empty */ + RT_ERR_FILTER_FLOWTBL_EXIST, /* 0x0007000d, flow table entry is already exist */ + RT_ERR_FILTER_METER_ID, /* 0x0007000e, invalid metering id */ + RT_ERR_FILTER_LOG_ID, /* 0x0007000f, invalid log id */ + RT_ERR_FILTER_INACL_NONE_BEGIN_IDX, /* 0x00070010, entry index is not starting index of a group of rules */ + RT_ERR_FILTER_INACL_ACT_NOT_SUPPORT, /* 0x00070011, action not support */ + RT_ERR_FILTER_INACL_RULE_NOT_SUPPORT, /* 0x00070012, rule not support */ + + /* 0x0008xxxx for ACL Rate Limit */ + RT_ERR_ACLRL_HTHR = 0x00080000, /* 0x00080000, invalid high threshold */ + RT_ERR_ACLRL_TIMESLOT, /* 0x00080001, invalid time slot */ + RT_ERR_ACLRL_TOKEN, /* 0x00080002, invalid token amount */ + RT_ERR_ACLRL_RATE, /* 0x00080003, invalid rate */ + + /* 0x0009xxxx for Link aggregation */ + RT_ERR_LA_CPUPORT = 0x00090000, /* 0x00090000, CPU port can not be aggregated port */ + RT_ERR_LA_TRUNK_ID, /* 0x00090001, invalid trunk id */ + RT_ERR_LA_PORTMASK, /* 0x00090002, invalid port mask */ + RT_ERR_LA_HASHMASK, /* 0x00090003, invalid hash mask */ + RT_ERR_LA_DUMB, /* 0x00090004, this API should be used in 802.1ad dumb mode */ + RT_ERR_LA_PORTNUM_DUMB, /* 0x00090005, it can only aggregate at most four ports when 802.1ad dumb mode */ + RT_ERR_LA_PORTNUM_NORMAL, /* 0x00090006, it can only aggregate at most eight ports when 802.1ad normal mode */ + RT_ERR_LA_MEMBER_OVERLAP, /* 0x00090007, the specified port mask is overlapped with other group */ + RT_ERR_LA_NOT_MEMBER_PORT, /* 0x00090008, the port is not a member port of the trunk */ + RT_ERR_LA_TRUNK_NOT_EXIST, /* 0x00090009, the trunk doesn't exist */ + + + /* 0x000axxxx for storm filter */ + RT_ERR_SFC_TICK_PERIOD = 0x000a0000, /* 0x000a0000, invalid SFC tick period */ + RT_ERR_SFC_UNKNOWN_GROUP, /* 0x000a0001, Unknown Storm filter group */ + + /* 0x000bxxxx for pattern match */ + RT_ERR_PM_MASK = 0x000b0000, /* 0x000b0000, invalid pattern length. Pattern length should be 8 */ + RT_ERR_PM_LENGTH, /* 0x000b0001, invalid pattern match mask, first byte must care */ + RT_ERR_PM_MODE, /* 0x000b0002, invalid pattern match mode */ + + /* 0x000cxxxx for input bandwidth control */ + RT_ERR_INBW_TICK_PERIOD = 0x000c0000, /* 0x000c0000, invalid tick period for input bandwidth control */ + RT_ERR_INBW_TOKEN_AMOUNT, /* 0x000c0001, invalid amount of token for input bandwidth control */ + RT_ERR_INBW_FCON_VALUE, /* 0x000c0002, invalid flow control ON threshold value for input bandwidth control */ + RT_ERR_INBW_FCOFF_VALUE, /* 0x000c0003, invalid flow control OFF threshold value for input bandwidth control */ + RT_ERR_INBW_FC_ALLOWANCE, /* 0x000c0004, invalid allowance of incomming packet for input bandwidth control */ + RT_ERR_INBW_RATE, /* 0x000c0005, invalid input bandwidth rate */ + RT_ERR_INBW_PORT_ID, /* 0x000c0006, invalid input bandwidth control port ID(0-8 */ + + /* 0x000dxxxx for QoS */ + RT_ERR_QOS_1P_PRIORITY = 0x000d0000, /* 0x000d0000, invalid 802.1P priority */ + RT_ERR_QOS_DSCP_VALUE, /* 0x000d0001, invalid DSCP value */ + RT_ERR_QOS_INT_PRIORITY, /* 0x000d0002, invalid internal priority */ + RT_ERR_QOS_SEL_DSCP_PRI, /* 0x000d0003, invalid DSCP selection priority */ + RT_ERR_QOS_SEL_PORT_PRI, /* 0x000d0004, invalid port selection priority */ + RT_ERR_QOS_SEL_IN_ACL_PRI, /* 0x000d0005, invalid ingress ACL selection priority */ + RT_ERR_QOS_SEL_CLASS_PRI, /* 0x000d0006, invalid classifier selection priority */ + RT_ERR_QOS_EBW_RATE, /* 0x000d0007, invalid egress bandwidth rate */ + RT_ERR_QOS_SCHE_TYPE, /* 0x000d0008, invalid QoS scheduling type */ + RT_ERR_QOS_QUEUE_WEIGHT, /* 0x000d0009, invalid Queue weight */ + RT_ERR_QOS_SEL_PRI_SOURCE, /* 0x000d000a, invalid selection of priority source */ + RT_ERR_QOS_EBW_PORT_ID, /* 0x000d000b, invalid selection of priority source */ + + /* 0x000exxxx for port ability */ + RT_ERR_PHY_PAGE_ID = 0x000e0000, /* 0x000e0000, invalid PHY page id */ + RT_ERR_PHY_REG_ID, /* 0x000e0001, invalid PHY reg id */ + RT_ERR_PHY_DATAMASK, /* 0x000e0002, invalid PHY data mask */ + RT_ERR_PHY_AUTO_NEGO_MODE, /* 0x000e0003, invalid PHY auto-negotiation mode*/ + RT_ERR_PHY_SPEED, /* 0x000e0004, invalid PHY speed setting */ + RT_ERR_PHY_DUPLEX, /* 0x000e0005, invalid PHY duplex setting */ + RT_ERR_PHY_FORCE_ABILITY, /* 0x000e0006, invalid PHY force mode ability parameter */ + RT_ERR_PHY_FORCE_1000, /* 0x000e0007, invalid PHY force mode 1G speed setting */ + RT_ERR_PHY_TXRX, /* 0x000e0008, invalid PHY tx/rx */ + RT_ERR_PHY_ID, /* 0x000e0009, invalid PHY id */ + RT_ERR_PHY_RTCT_NOT_FINISH, /* 0x000e000a, PHY RTCT in progress */ + RT_ERR_PHY_LINK_DOWN, /* 0x000e000b, phy link down */ + + /* 0x000fxxxx for mirror */ + RT_ERR_MIRROR_DIRECTION = 0x000f0000, /* 0x000f0000, invalid error mirror direction */ + RT_ERR_MIRROR_SESSION_FULL, /* 0x000f0001, mirroring session is full */ + RT_ERR_MIRROR_SESSION_NOEXIST, /* 0x000f0002, mirroring session not exist */ + RT_ERR_MIRROR_PORT_EXIST, /* 0x000f0003, mirroring port already exists */ + RT_ERR_MIRROR_PORT_NOT_EXIST, /* 0x000f0004, mirroring port does not exists */ + RT_ERR_MIRROR_PORT_FULL, /* 0x000f0005, Exceeds maximum number of supported mirroring port */ + + /* 0x0010xxxx for stat */ + RT_ERR_STAT_INVALID_GLOBAL_CNTR = 0x00100000, /* 0x00100000, Invalid Global Counter */ + RT_ERR_STAT_INVALID_PORT_CNTR, /* 0x00100001, Invalid Port Counter */ + RT_ERR_STAT_GLOBAL_CNTR_FAIL, /* 0x00100002, Could not retrieve/reset Global Counter */ + RT_ERR_STAT_PORT_CNTR_FAIL, /* 0x00100003, Could not retrieve/reset Port Counter */ + RT_ERR_STAT_INVALID_CNTR, /* 0x00100004, Invalid Counter */ + RT_ERR_STAT_CNTR_FAIL, /* 0x00100005, Could not retrieve/reset Counter */ + + /* 0x0011xxxx for dot1x */ + RT_ERR_DOT1X_INVALID_DIRECTION = 0x00110000, /* 0x00110000, Invalid Authentication Direction */ + RT_ERR_DOT1X_PORTBASEDPNEN, /* 0x00110001, Port-based enable port error */ + RT_ERR_DOT1X_PORTBASEDAUTH, /* 0x00110002, Port-based auth port error */ + RT_ERR_DOT1X_PORTBASEDOPDIR, /* 0x00110003, Port-based opdir error */ + RT_ERR_DOT1X_MACBASEDPNEN, /* 0x00110004, MAC-based enable port error */ + RT_ERR_DOT1X_MACBASEDOPDIR, /* 0x00110005, MAC-based opdir error */ + RT_ERR_DOT1X_PROC, /* 0x00110006, unauthorized behavior error */ + RT_ERR_DOT1X_GVLANIDX, /* 0x00110007, guest vlan index error */ + RT_ERR_DOT1X_GVLANTALK, /* 0x00110008, guest vlan OPDIR error */ + RT_ERR_DOT1X_MAC_PORT_MISMATCH, /* 0x00110009, Auth MAC and port mismatch eror */ + + RT_ERR_PTP_CLKOUTRUNSTOP= 0x00120000, + RT_ERR_PTP_TIMESTAMP_INVALID, + + /* 0x00130000 for MACsec */ + RT_ERR_MACSEC_EGRESS_DEVICE = 0x00130000, /* 0x00130000, MACsec egress device ID error */ + RT_ERR_MACSEC_INGRESS_DEVICE = 0x00130001, /* 0x00130001, MACsec ingress device ID error */ + + /* 0x0014xxxx for I2C */ + RT_ERR_I2C_COMMAND_FAIL = 0x00140000, /* 0x00140000, Indicate i2c command execute error */ + + RT_ERR_END /* The symbol is the latest symbol */ +} rt_error_code_t; + +#define RT_PARAM_CHK(expr, errCode)\ +do {\ + if ((rtk_int32)(expr)) {\ + return errCode; \ + }\ +} while (0) +#define RT_INIT_CHK(state)\ +do {\ + if (INIT_COMPLETED != (state)) {\ + return RT_ERR_NOT_INIT;\ + }\ +} while (0) +#define RT_ERR_CHK(op, ret)\ +do {\ + if ((ret = (op)) != RT_ERR_OK)\ + return ret;\ +} while(0) +#endif /* __COMMON_RT_ERROR_H__ */ diff --git a/sources/uboot-be550/drivers/net/rtl8372/rtk_switch.c b/sources/uboot-be550/drivers/net/rtl8372/rtk_switch.c new file mode 100755 index 00000000..93bd658d --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/rtk_switch.c @@ -0,0 +1,1016 @@ +/* + * Copyright (C) 2010 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API + * Feature : Here is a list of all functions and variables in this module. + * + */ +#include +#include +#include +#include +#include + +static init_state_t init_state = INIT_NOT_COMPLETED; + +#if defined(RTK_X86_CLE) +pthread_mutex_t api_mutex = PTHREAD_MUTEX_INITIALIZER; +#endif + +static rtk_switch_halCtrl_t *halCtrl = NULL; + + +static rtk_api_ret_t _rtk_switch_init(void) +{ + rtk_int32 retVal; + switch_chip_t switchChip; + + /* Find device */ + if((halCtrl = hal_find_device()) == NULL) + { + printf("hal_find_device error\n"); + return RT_ERR_CHIP_NOT_FOUND; + } + + if((retVal = phy_identify_init()) != RT_ERR_OK) + { + printf("phy_identify_init error\n"); + return retVal; + } + + /* Attached DAL mapper */ + switchChip = halCtrl->switch_type; + if((retVal = dal_mgmt_attachDevice(switchChip)) != RT_ERR_OK) + { + printf("dal_mgmt_attachDevice error\n"); + return retVal; + } + + /* Set initial state */ + if((retVal = rtk_switch_initialState_set(INIT_COMPLETED)) != RT_ERR_OK) + { + printf("rtk_switch_initialState_set error\n"); + return retVal; + } + + /* Call initial function */ + if((retVal = RT_MAPPER->switch_init()) != RT_ERR_OK) + { + printf("RT_MAPPER->switch_init error\n"); + return retVal; + } + + + return RT_ERR_OK; +} + +/* Function Name: + * hal_ctrlInfo_get + * Description: + * Find the hal control information structure . + * Input: + * Output: + * None + * Return: + * NULL - Not found + * Otherwise - Pointer of hal control information structure that found + * Note: + * The function have found the exactly hal control information structure. + */ +rtk_switch_halCtrl_t * +hal_ctrlInfo_get(void) +{ + return halCtrl; +} +/* Function Name: + * rtk_switch_initialState_set + * Description: + * Set initial status + * Input: + * state - Initial state; + * Output: + * None + * Return: + * RT_ERR_OK - Initialized + * RT_ERR_FAILED - Uninitialized + * Note: + * + */ +rtk_api_ret_t rtk_switch_initialState_set(init_state_t state) +{ + if(state >= INIT_STATE_END) + return RT_ERR_FAILED; + + init_state = state; + return RT_ERR_OK; +} + +/* Function Name: + * rtk_switch_initialState_get + * Description: + * Get initial status + * Input: + * None + * Output: + * None + * Return: + * INIT_COMPLETED - Initialized + * INIT_NOT_COMPLETED - Uninitialized + * Note: + * + */ +init_state_t rtk_switch_initialState_get(void) +{ + return init_state; +} + +/* Function Name: + * rtk_switch_logicalPortCheck + * Description: + * Check logical port ID. + * Input: + * logicalPort - logical port ID + * Output: + * None + * Return: + * RT_ERR_OK - Port ID is correct + * RT_ERR_FAILED - Port ID is not correct + * RT_ERR_NOT_INIT - Not Initialize + * Note: + * + */ +rtk_api_ret_t rtk_switch_logicalPortCheck(rtk_port_t logicalPort) +{ + if(init_state != INIT_COMPLETED) + return RT_ERR_NOT_INIT; + + if(logicalPort >= RTK_SWITCH_PORT_NUM) + return RT_ERR_FAILED; + + if(halCtrl->l2p_port[logicalPort] == 0xFF) + return RT_ERR_FAILED; + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_switch_isUtpPort + * Description: + * Check is logical port a UTP port + * Input: + * logicalPort - logical port ID + * Output: + * None + * Return: + * RT_ERR_OK - Port ID is a UTP port + * RT_ERR_FAILED - Port ID is not a UTP port + * RT_ERR_NOT_INIT - Not Initialize + * Note: + * + */ +rtk_api_ret_t rtk_switch_isUtpPort(rtk_port_t logicalPort) +{ + if(init_state != INIT_COMPLETED) + return RT_ERR_NOT_INIT; + + if(logicalPort >= RTK_SWITCH_PORT_NUM) + return RT_ERR_FAILED; + + if(halCtrl->log_port_type[logicalPort] == UTP_PORT) + return RT_ERR_OK; + else + return RT_ERR_FAILED; +} + +/* Function Name: + * rtk_switch_isExtPort + * Description: + * Check is logical port a Extension port + * Input: + * logicalPort - logical port ID + * Output: + * None + * Return: + * RT_ERR_OK - Port ID is a EXT port + * RT_ERR_FAILED - Port ID is not a EXT port + * RT_ERR_NOT_INIT - Not Initialize + * Note: + * + */ +rtk_api_ret_t rtk_switch_isExtPort(rtk_port_t logicalPort) +{ + if(init_state != INIT_COMPLETED) + return RT_ERR_NOT_INIT; + + if(logicalPort >= RTK_SWITCH_PORT_NUM) + return RT_ERR_FAILED; + + if(halCtrl->log_port_type[logicalPort] == EXT_PORT) + return RT_ERR_OK; + else + return RT_ERR_FAILED; +} + + +/* Function Name: + * rtk_switch_isHsgPort + * Description: + * Check is logical port a HSG port + * Input: + * logicalPort - logical port ID + * Output: + * None + * Return: + * RT_ERR_OK - Port ID is a HSG port + * RT_ERR_FAILED - Port ID is not a HSG port + * RT_ERR_NOT_INIT - Not Initialize + * Note: + * + */ +rtk_api_ret_t rtk_switch_isHsgPort(rtk_port_t logicalPort) +{ + if(init_state != INIT_COMPLETED) + return RT_ERR_NOT_INIT; + + if(logicalPort >= RTK_SWITCH_PORT_NUM) + return RT_ERR_FAILED; + + if( ((0x01 << logicalPort) & halCtrl->hsg_logical_portmask) != 0) + return RT_ERR_OK; + else + return RT_ERR_FAILED; +} + +/* Function Name: + * rtk_switch_isSgmiiPort + * Description: + * Check is logical port a SGMII port + * Input: + * logicalPort - logical port ID + * Output: + * None + * Return: + * RT_ERR_OK - Port ID is a SGMII port + * RT_ERR_FAILED - Port ID is not a SGMII port + * RT_ERR_NOT_INIT - Not Initialize + * Note: + * + */ +rtk_api_ret_t rtk_switch_isSgmiiPort(rtk_port_t logicalPort) +{ + if(init_state != INIT_COMPLETED) + return RT_ERR_NOT_INIT; + + if(logicalPort >= RTK_SWITCH_PORT_NUM) + return RT_ERR_FAILED; + + if( ((0x01 << logicalPort) & halCtrl->sg_logical_portmask) != 0) + return RT_ERR_OK; + else + return RT_ERR_FAILED; +} + +/* Function Name: + * rtk_switch_isCPUPort + * Description: + * Check is logical port a CPU port + * Input: + * logicalPort - logical port ID + * Output: + * None + * Return: + * RT_ERR_OK - Port ID is a CPU port + * RT_ERR_FAILED - Port ID is not a CPU port + * RT_ERR_NOT_INIT - Not Initialize + * Note: + * + */ +rtk_api_ret_t rtk_switch_isCPUPort(rtk_port_t logicalPort) +{ + if(init_state != INIT_COMPLETED) + return RT_ERR_NOT_INIT; + + if(logicalPort >= RTK_SWITCH_PORT_NUM) + return RT_ERR_FAILED; + + if( ((0x01 << logicalPort) & halCtrl->valid_cpu_portmask) != 0) + return RT_ERR_OK; + else + return RT_ERR_FAILED; +} + +/* Function Name: + * rtk_switch_isComboPort + * Description: + * Check is logical port a Combo port + * Input: + * logicalPort - logical port ID + * Output: + * None + * Return: + * RT_ERR_OK - Port ID is a combo port + * RT_ERR_FAILED - Port ID is not a combo port + * RT_ERR_NOT_INIT - Not Initialize + * Note: + * + */ +rtk_api_ret_t rtk_switch_isComboPort(rtk_port_t logicalPort) +{ + if(init_state != INIT_COMPLETED) + return RT_ERR_NOT_INIT; + + if(logicalPort >= RTK_SWITCH_PORT_NUM) + return RT_ERR_FAILED; + + if(halCtrl->combo_logical_port == logicalPort) + return RT_ERR_OK; + else + return RT_ERR_FAILED; +} + +/* Function Name: + * rtk_switch_ComboPort_get + * Description: + * Get Combo port ID + * Input: + * None + * Output: + * None + * Return: + * Port ID of combo port + * Note: + * + */ +rtk_uint32 rtk_switch_ComboPort_get(void) +{ + return halCtrl->combo_logical_port; +} + +/* Function Name: + * rtk_switch_isPtpPort + * Description: + * Check is logical port a PTP port + * Input: + * logicalPort - logical port ID + * Output: + * None + * Return: + * RT_ERR_OK - Port ID is a PTP port + * RT_ERR_FAILED - Port ID is not a PTP port + * RT_ERR_NOT_INIT - Not Initialize + * Note: + * + */ +rtk_api_ret_t rtk_switch_isPtpPort(rtk_port_t logicalPort) +{ + if(init_state != INIT_COMPLETED) + return RT_ERR_NOT_INIT; + + if(logicalPort >= RTK_SWITCH_PORT_NUM) + return RT_ERR_FAILED; + + if(halCtrl->ptp_port[logicalPort] == 1) + return RT_ERR_OK; + else + return RT_ERR_FAILED; +} + +/* Function Name: + * rtk_switch_port_L2P_get + * Description: + * Get physical port ID + * Input: + * logicalPort - logical port ID + * Output: + * None + * Return: + * Physical port ID + * Note: + * + */ +rtk_uint32 rtk_switch_port_L2P_get(rtk_port_t logicalPort) +{ + if(init_state != INIT_COMPLETED) + return UNDEFINE_PHY_PORT; + + if(logicalPort >= RTK_SWITCH_PORT_NUM) + return UNDEFINE_PHY_PORT; + + return (halCtrl->l2p_port[logicalPort]); +} + +/* Function Name: + * rtk_switch_port_P2L_get + * Description: + * Get logical port ID + * Input: + * physicalPort - physical port ID + * Output: + * None + * Return: + * logical port ID + * Note: + * + */ +rtk_port_t rtk_switch_port_P2L_get(rtk_uint32 physicalPort) +{ + if(init_state != INIT_COMPLETED) + return UNDEFINE_PORT; + + if(physicalPort >= RTK_SWITCH_PORT_NUM) + return UNDEFINE_PORT; + + return (halCtrl->p2l_port[physicalPort]); +} + +/* Function Name: + * rtk_switch_isPortMaskValid + * Description: + * Check portmask is valid or not + * Input: + * pPmask - logical port mask + * Output: + * None + * Return: + * RT_ERR_OK - port mask is valid + * RT_ERR_FAILED - port mask is not valid + * RT_ERR_NOT_INIT - Not Initialize + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * + */ +rtk_api_ret_t rtk_switch_isPortMaskValid(rtk_portmask_t *pPmask) +{ + if(init_state != INIT_COMPLETED) + return RT_ERR_NOT_INIT; + + if(NULL == pPmask) + return RT_ERR_NULL_POINTER; + + if( (pPmask->bits[0] | halCtrl->valid_portmask) != halCtrl->valid_portmask ) + return RT_ERR_FAILED; + else + return RT_ERR_OK; +} + +/* Function Name: + * rtk_switch_isPortMaskUtp + * Description: + * Check all ports in portmask are only UTP port + * Input: + * pPmask - logical port mask + * Output: + * None + * Return: + * RT_ERR_OK - Only UTP port in port mask + * RT_ERR_FAILED - Not only UTP port in port mask + * RT_ERR_NOT_INIT - Not Initialize + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * + */ +rtk_api_ret_t rtk_switch_isPortMaskUtp(rtk_portmask_t *pPmask) +{ + if(init_state != INIT_COMPLETED) + return RT_ERR_NOT_INIT; + + if(NULL == pPmask) + return RT_ERR_NULL_POINTER; + + if( (pPmask->bits[0] | halCtrl->valid_utp_portmask) != halCtrl->valid_utp_portmask ) + return RT_ERR_FAILED; + else + return RT_ERR_OK; +} + +/* Function Name: + * rtk_switch_isPortMaskExt + * Description: + * Check all ports in portmask are only EXT port + * Input: + * pPmask - logical port mask + * Output: + * None + * Return: + * RT_ERR_OK - Only EXT port in port mask + * RT_ERR_FAILED - Not only EXT port in port mask + * RT_ERR_NOT_INIT - Not Initialize + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * + */ +rtk_api_ret_t rtk_switch_isPortMaskExt(rtk_portmask_t *pPmask) +{ + if(init_state != INIT_COMPLETED) + return RT_ERR_NOT_INIT; + + if(NULL == pPmask) + return RT_ERR_NULL_POINTER; + + if( (pPmask->bits[0] | halCtrl->valid_ext_portmask) != halCtrl->valid_ext_portmask ) + return RT_ERR_FAILED; + else + return RT_ERR_OK; +} + +/* Function Name: + * rtk_switch_portmask_L2P_get + * Description: + * Get physicl portmask from logical portmask + * Input: + * pLogicalPmask - logical port mask + * Output: + * pPhysicalPortmask - physical port mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_NOT_INIT - Not Initialize + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_PORT_MASK - Error port mask + * Note: + * + */ +rtk_api_ret_t rtk_switch_portmask_L2P_get(rtk_portmask_t *pLogicalPmask, rtk_uint32 *pPhysicalPortmask) +{ + rtk_uint32 log_port, phy_port; + + if(init_state != INIT_COMPLETED) + return RT_ERR_NOT_INIT; + + if(NULL == pLogicalPmask) + return RT_ERR_NULL_POINTER; + + if(NULL == pPhysicalPortmask) + return RT_ERR_NULL_POINTER; + + if(rtk_switch_isPortMaskValid(pLogicalPmask) != RT_ERR_OK) + return RT_ERR_PORT_MASK; + + /* reset physical port mask */ + *pPhysicalPortmask = 0; + + RTK_PORTMASK_SCAN((*pLogicalPmask), log_port) + { + phy_port = rtk_switch_port_L2P_get((rtk_port_t)log_port); + *pPhysicalPortmask |= (0x0001 << phy_port); + } + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_switch_portmask_P2L_get + * Description: + * Get logical portmask from physical portmask + * Input: + * physicalPortmask - physical port mask + * Output: + * pLogicalPmask - logical port mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_NOT_INIT - Not Initialize + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_PORT_MASK - Error port mask + * Note: + * + */ +rtk_api_ret_t rtk_switch_portmask_P2L_get(rtk_uint32 physicalPortmask, rtk_portmask_t *pLogicalPmask) +{ + rtk_uint32 log_port, phy_port; + + if(init_state != INIT_COMPLETED) + return RT_ERR_NOT_INIT; + + if(NULL == pLogicalPmask) + return RT_ERR_NULL_POINTER; + + RTK_PORTMASK_CLEAR(*pLogicalPmask); + + for(phy_port = halCtrl->min_phy_port; phy_port <= halCtrl->max_phy_port; phy_port++) + { + if(physicalPortmask & (0x0001 << phy_port)) + { + log_port = rtk_switch_port_P2L_get(phy_port); + if(log_port != UNDEFINE_PORT) + { + RTK_PORTMASK_PORT_SET(*pLogicalPmask, log_port); + } + } + } + + return RT_ERR_OK; +} + +/* Function Name: + * rtk_switch_phyPortMask_get + * Description: + * Get physical portmask + * Input: + * None + * Output: + * None + * Return: + * 0x00 - Not Initialize + * Other value - Physical port mask + * Note: + * + */ +rtk_uint32 rtk_switch_phyPortMask_get(void) +{ + if(init_state != INIT_COMPLETED) + return 0x00; /* No port in portmask */ + + return (halCtrl->phy_portmask); +} + +/* Function Name: + * rtk_switch_logPortMask_get + * Description: + * Get Logical portmask + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_NOT_INIT - Not Initialize + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * + */ +rtk_api_ret_t rtk_switch_logPortMask_get(rtk_portmask_t *pPortmask) +{ + if(init_state != INIT_COMPLETED) + return RT_ERR_FAILED; + + if(NULL == pPortmask) + return RT_ERR_NULL_POINTER; + + pPortmask->bits[0] = halCtrl->valid_portmask; + return RT_ERR_OK; +} + +/* Function Name: + * rtk_switch_init + * Description: + * Set chip to default configuration enviroment + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set chip registers to default configuration for different release chip model. + */ +rtk_api_ret_t rtk_switch_init(void) +{ + rtk_api_ret_t retVal; + + RTK_API_LOCK(); + printf("rtk_switch_init !!!!!\n"); + retVal = _rtk_switch_init(); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_switch_portMaxPktLen_set + * Description: + * Set Max packet length + * Input: + * port - Port ID + * speed - Speed + * cfgId - Configuration ID + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + */ +rtk_api_ret_t rtk_switch_portMaxPktLen_set(rtk_port_t port, rtk_switch_maxPktLen_linkSpeed_t speed, rtk_uint32 cfgId) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->switch_portMaxPktLen_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->switch_portMaxPktLen_set(port, speed, cfgId); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_switch_portMaxPktLen_get + * Description: + * Get Max packet length + * Input: + * port - Port ID + * speed - Speed + * Output: + * pCfgId - Configuration ID + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + */ +rtk_api_ret_t rtk_switch_portMaxPktLen_get(rtk_port_t port, rtk_switch_maxPktLen_linkSpeed_t speed, rtk_uint32 *pCfgId) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->switch_portMaxPktLen_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->switch_portMaxPktLen_get(port, speed, pCfgId); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_switch_maxPktLenCfg_set + * Description: + * Set Max packet length configuration + * Input: + * cfgId - Configuration ID + * pktLen - Max packet length + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + */ +rtk_api_ret_t rtk_switch_maxPktLenCfg_set(rtk_uint32 cfgId, rtk_uint32 pktLen) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->switch_maxPktLenCfg_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->switch_maxPktLenCfg_set(cfgId, pktLen); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_switch_maxPktLenCfg_get + * Description: + * Get Max packet length configuration + * Input: + * cfgId - Configuration ID + * pPktLen - Max packet length + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + */ +rtk_api_ret_t rtk_switch_maxPktLenCfg_get(rtk_uint32 cfgId, rtk_uint32 *pPktLen) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->switch_maxPktLenCfg_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->switch_maxPktLenCfg_get(cfgId, pPktLen); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_switch_greenEthernet_set + * Description: + * Set all Ports Green Ethernet state. + * Input: + * enable - Green Ethernet state. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * This API can set all Ports Green Ethernet state. + * The configuration is as following: + * - DISABLE + * - ENABLE + */ +rtk_api_ret_t rtk_switch_greenEthernet_set(rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->switch_greenEthernet_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->switch_greenEthernet_set(enable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_switch_greenEthernet_get + * Description: + * Get all Ports Green Ethernet state. + * Input: + * None + * Output: + * pEnable - Green Ethernet state. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API can get Green Ethernet state. + */ +rtk_api_ret_t rtk_switch_greenEthernet_get(rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->switch_greenEthernet_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->switch_greenEthernet_get(pEnable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_switch_maxLogicalPort_get + * Description: + * Get Max logical port ID + * Input: + * None + * Output: + * None + * Return: + * Max logical port + * Note: + * This API can get max logical port + */ +rtk_port_t rtk_switch_maxLogicalPort_get(void) +{ + rtk_port_t port, maxLogicalPort = 0; + + /* Check initialization state */ + if(rtk_switch_initialState_get() != INIT_COMPLETED) + { + return UNDEFINE_PORT; + } + + for(port = 0; port < RTK_SWITCH_PORT_NUM; port++) + { + if( (halCtrl->log_port_type[port] == UTP_PORT) || (halCtrl->log_port_type[port] == EXT_PORT) ) + maxLogicalPort = port; + } + + return maxLogicalPort; +} + +/* Function Name: + * rtk_switch_maxMeterId_get + * Description: + * Get Max Meter ID + * Input: + * None + * Output: + * None + * Return: + * 0x00 - Not Initialize + * Other value - Max Meter ID + * Note: + * + */ +rtk_uint32 rtk_switch_maxMeterId_get(void) +{ + if(init_state != INIT_COMPLETED) + return 0x00; + + return (halCtrl->max_meter_id); +} + +/* Function Name: + * rtk_switch_maxLutAddrNumber_get + * Description: + * Get Max LUT Address number + * Input: + * None + * Output: + * None + * Return: + * 0x00 - Not Initialize + * Other value - Max LUT Address number + * Note: + * + */ +rtk_uint32 rtk_switch_maxLutAddrNumber_get(void) +{ + if(init_state != INIT_COMPLETED) + return 0x00; + + return (halCtrl->max_lut_addr_num); +} + +/* Function Name: + * rtk_switch_isValidTrunkGrpId + * Description: + * Check if trunk group is valid or not + * Input: + * grpId - Group ID + * Output: + * None + * Return: + * RT_ERR_OK - Trunk Group ID is valid + * RT_ERR_LA_TRUNK_ID - Trunk Group ID is not valid + * Note: + * + */ +rtk_uint32 rtk_switch_isValidTrunkGrpId(rtk_uint32 grpId) +{ + if(init_state != INIT_COMPLETED) + return 0x00; + + if( (halCtrl->trunk_group_mask & (0x01 << grpId) ) != 0) + return RT_ERR_OK; + else + return RT_ERR_LA_TRUNK_ID; + +} + +/* Function Name: + * rtk_switch_maxBufferPageNum_get + * Description: + * Get number of packet buffer page + * Input: + * None + * Output: + * None + * Return: + * Number of packet buffer page + * Note: + * + */ +rtk_uint32 rtk_switch_maxBufferPageNum_get(void) +{ + if(init_state != INIT_COMPLETED) + return 0x00; + + return (halCtrl->packet_buffer_page_num); +} + +/* Function Name: + * rtk_switch_chipType_get + * Description: + * Get switch chip type + * Input: + * None + * Output: + * None + * Return: + * CHIP_END - Unknown chip type + * other - Switch chip type + * Note: + * + */ +switch_chip_t rtk_switch_chipType_get(void) +{ + if (halCtrl == NULL) + return CHIP_END; + + return halCtrl->switch_type; +} diff --git a/sources/uboot-be550/drivers/net/rtl8372/rtk_switch.h b/sources/uboot-be550/drivers/net/rtl8372/rtk_switch.h new file mode 100755 index 00000000..4716e1e6 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/rtk_switch.h @@ -0,0 +1,751 @@ +/* + * Copyright(c) Realtek Semiconductor Corporation, 2008 + * All rights reserved. + * + * $Revision$ + * $Date$ + * + * Purpose : Definition function prototype of RTK switch API. + * + * Feature : Function prototype definition + * + */ + +#ifndef __RTK_SWITCH_H__ +#define __RTK_SWITCH_H__ + +#include +#include + +#if defined(RTK_X86_CLE) +#include +#endif + +#define MAXPKTLEN_CFG_ID_MAX (1) + +#define RTK_SWITCH_MAX_PKTLEN (0x3FFF) + +#if defined(RTK_X86_CLE) +extern pthread_mutex_t api_mutex; +#define RTK_API_LOCK() pthread_mutex_lock(&api_mutex) +#define RTK_API_UNLOCK() pthread_mutex_unlock(&api_mutex) +#else +#define RTK_API_LOCK() +#define RTK_API_UNLOCK() +#endif + +typedef enum init_state_e +{ + INIT_NOT_COMPLETED = 0, + INIT_COMPLETED, + INIT_STATE_END +} init_state_t; + +typedef enum rtk_switch_maxPktLen_linkSpeed_e { + MAXPKTLEN_LINK_SPEED_FE = 0, + MAXPKTLEN_LINK_SPEED_GE, + MAXPKTLEN_LINK_SPEED_END, +} rtk_switch_maxPktLen_linkSpeed_t; + + +/* UTIL MACRO */ +#define RTK_ERR_CHK(op) \ +do { \ + int errCode; \ + if ((errCode = (op)) != RT_ERR_OK) \ + return errCode; \ +} while(0) + +#define RTK_CHK_INIT_STATE() \ + do \ + { \ + if(rtk_switch_initialState_get() != INIT_COMPLETED) \ + { \ + return RT_ERR_NOT_INIT; \ + } \ + }while(0) + +#define RTK_CHK_PORT_VALID(__port__) \ + do \ + { \ + if(rtk_switch_logicalPortCheck(__port__) != RT_ERR_OK) \ + { \ + return RT_ERR_PORT_ID; \ + } \ + }while(0) + +#define RTK_CHK_PORTMASK_VALID(__portmask__) \ + do \ + { \ + if(rtk_switch_isPortMaskValid(__portmask__) != RT_ERR_OK) \ + { \ + return RT_ERR_PORT_MASK; \ + } \ + }while(0) +#if 0 +#define RTK_CHK_PORT_VALID(__port__) \ + do \ + { \ + if (__port__ > RTL8373_PORTIDMAX) \ + return RT_ERR_PORT_ID; \ + }while(0) +#endif +#define RTK_CHK_PORT_IS_UTP(__port__) \ + do \ + { \ + if(rtk_switch_isUtpPort(__port__) != RT_ERR_OK) \ + { \ + return RT_ERR_PORT_ID; \ + } \ + }while(0) + +#define RTK_CHK_PORT_IS_EXT(__port__) \ + do \ + { \ + if(rtk_switch_isExtPort(__port__) != RT_ERR_OK) \ + { \ + return RT_ERR_PORT_ID; \ + } \ + }while(0) + +#define RTK_CHK_PORT_IS_COMBO(__port__) \ + do \ + { \ + if(rtk_switch_isComboPort(__port__) != RT_ERR_OK) \ + { \ + return RT_ERR_PORT_ID; \ + } \ + }while(0) + +#define RTK_CHK_PORT_IS_PTP(__port__) \ + do \ + { \ + if(rtk_switch_isPtpPort(__port__) != RT_ERR_OK) \ + { \ + return RT_ERR_PORT_ID; \ + } \ + }while(0) + +#define RTK_CHK_PORTMASK_VALID_ONLY_UTP(__portmask__) \ + do \ + { \ + if(rtk_switch_isPortMaskUtp(__portmask__) != RT_ERR_OK) \ + { \ + return RT_ERR_PORT_MASK; \ + } \ + }while(0) + +#define RTK_CHK_PORTMASK_VALID_ONLY_EXT(__portmask__) \ + do \ + { \ + if(rtk_switch_isPortMaskExt(__portmask__) != RT_ERR_OK) \ + { \ + return RT_ERR_PORT_MASK; \ + } \ + }while(0) + +#define RTK_CHK_TRUNK_GROUP_VALID(__grpId__) \ + do \ + { \ + if(rtk_switch_isValidTrunkGrpId(__grpId__) != RT_ERR_OK) \ + { \ + return RT_ERR_LA_TRUNK_ID; \ + } \ + }while(0) + +#define RTK_PORTMASK_IS_PORT_SET(__portmask__, __port__) (((__portmask__).bits[0] & (0x00000001 << __port__)) ? 1 : 0) +#define RTK_PORTMASK_IS_EMPTY(__portmask__) (((__portmask__).bits[0] == 0) ? 1 : 0) +#define RTK_PORTMASK_CLEAR(__portmask__) ((__portmask__).bits[0] = 0) +#define RTK_PORTMASK_PORT_SET(__portmask__, __port__) ((__portmask__).bits[0] |= (0x00000001 << __port__)) +#define RTK_PORTMASK_PORT_CLEAR(__portmask__, __port__) ((__portmask__).bits[0] &= ~(0x00000001 << __port__)) +#define RTK_PORTMASK_ALLPORT_SET(__portmask__) (rtk_switch_logPortMask_get(&__portmask__)) +#define RTK_PORTMASK_SCAN(__portmask__, __port__) for(__port__ = 0; __port__ < RTK_SWITCH_PORT_NUM; __port__++) if(RTK_PORTMASK_IS_PORT_SET(__portmask__, __port__)) +#define RTK_PORTMASK_COMPARE(__portmask_A__, __portmask_B__) ((__portmask_A__).bits[0] - (__portmask_B__).bits[0]) + +#define RTK_SCAN_ALL_PHY_PORTMASK(__port__) for(__port__ = 0; __port__ < RTK_SWITCH_PORT_NUM; __port__++) if( (rtk_switch_phyPortMask_get() & (0x00000001 << __port__))) +#define RTK_SCAN_ALL_LOG_PORT(__port__) for(__port__ = 0; __port__ < RTK_SWITCH_PORT_NUM; __port__++) if( rtk_switch_logicalPortCheck(__port__) == RT_ERR_OK) +#define RTK_SCAN_ALL_LOG_PORTMASK(__portmask__) for((__portmask__).bits[0] = 0; (__portmask__).bits[0] < 0x7FFFF; (__portmask__).bits[0]++) if( rtk_switch_isPortMaskValid(&__portmask__) == RT_ERR_OK) + +/* Port mask defination */ +#define RTK_PHY_PORTMASK_ALL (rtk_switch_phyPortMask_get()) + +/* Port defination*/ +#define RTK_MAX_LOGICAL_PORT_ID (rtk_switch_maxLogicalPort_get()) + +/* Boundary defination */ +#define RTK_MAX_METER_ID (rtk_switch_maxMeterId_get()) +#define RTK_MAX_BUF_PAGE_NUM (rtk_switch_maxBufferPageNum_get()) + +/* Function Name: + * hal_ctrlInfo_get + * Description: + * Find the hal control information structure . + * Input: + * Output: + * None + * Return: + * NULL - Not found + * Otherwise - Pointer of hal control information structure that found + * Note: + * The function have found the exactly hal control information structure. + */ +extern rtk_switch_halCtrl_t *hal_ctrlInfo_get(void); +/* Function Name: + * rtk_switch_initialState_set + * Description: + * Set initial status + * Input: + * state - Initial state; + * Output: + * None + * Return: + * RT_ERR_OK - Initialized + * RT_ERR_FAILED - Uninitialized + * Note: + * + */ +extern rtk_api_ret_t rtk_switch_initialState_set(init_state_t state); + +/* Function Name: + * rtk_switch_initialState_get + * Description: + * Get initial status + * Input: + * None + * Output: + * None + * Return: + * INIT_COMPLETED - Initialized + * INIT_NOT_COMPLETED - Uninitialized + * Note: + * + */ +extern init_state_t rtk_switch_initialState_get(void); + +/* Function Name: + * rtk_switch_logicalPortCheck + * Description: + * Check logical port ID. + * Input: + * logicalPort - logical port ID + * Output: + * None + * Return: + * RT_ERR_OK - Port ID is correct + * RT_ERR_FAILED - Port ID is not correct + * RT_ERR_NOT_INIT - Not Initialize + * Note: + * + */ +extern rtk_api_ret_t rtk_switch_logicalPortCheck(rtk_port_t logicalPort); + +/* Function Name: + * rtk_switch_isUtpPort + * Description: + * Check is logical port a UTP port + * Input: + * logicalPort - logical port ID + * Output: + * None + * Return: + * RT_ERR_OK - Port ID is a UTP port + * RT_ERR_FAILED - Port ID is not a UTP port + * RT_ERR_NOT_INIT - Not Initialize + * Note: + * + */ +extern rtk_api_ret_t rtk_switch_isUtpPort(rtk_port_t logicalPort); + +/* Function Name: + * rtk_switch_isExtPort + * Description: + * Check is logical port a Extension port + * Input: + * logicalPort - logical port ID + * Output: + * None + * Return: + * RT_ERR_OK - Port ID is a EXT port + * RT_ERR_FAILED - Port ID is not a EXT port + * RT_ERR_NOT_INIT - Not Initialize + * Note: + * + */ +extern rtk_api_ret_t rtk_switch_isExtPort(rtk_port_t logicalPort); + +/* Function Name: + * rtk_switch_isHsgPort + * Description: + * Check is logical port a HSG port + * Input: + * logicalPort - logical port ID + * Output: + * None + * Return: + * RT_ERR_OK - Port ID is a HSG port + * RT_ERR_FAILED - Port ID is not a HSG port + * RT_ERR_NOT_INIT - Not Initialize + * Note: + * + */ +extern rtk_api_ret_t rtk_switch_isHsgPort(rtk_port_t logicalPort); + +/* Function Name: + * rtk_switch_isSgmiiPort + * Description: + * Check is logical port a SGMII port + * Input: + * logicalPort - logical port ID + * Output: + * None + * Return: + * RT_ERR_OK - Port ID is a SGMII port + * RT_ERR_FAILED - Port ID is not a SGMII port + * RT_ERR_NOT_INIT - Not Initialize + * Note: + * + */ +extern rtk_api_ret_t rtk_switch_isSgmiiPort(rtk_port_t logicalPort); + +/* Function Name: + * rtk_switch_isCPUPort + * Description: + * Check is logical port a CPU port + * Input: + * logicalPort - logical port ID + * Output: + * None + * Return: + * RT_ERR_OK - Port ID is a CPU port + * RT_ERR_FAILED - Port ID is not a CPU port + * RT_ERR_NOT_INIT - Not Initialize + * Note: + * + */ +extern rtk_api_ret_t rtk_switch_isCPUPort(rtk_port_t logicalPort); + +/* Function Name: + * rtk_switch_isComboPort + * Description: + * Check is logical port a Combo port + * Input: + * logicalPort - logical port ID + * Output: + * None + * Return: + * RT_ERR_OK - Port ID is a combo port + * RT_ERR_FAILED - Port ID is not a combo port + * RT_ERR_NOT_INIT - Not Initialize + * Note: + * + */ +extern rtk_api_ret_t rtk_switch_isComboPort(rtk_port_t logicalPort); + +/* Function Name: + * rtk_switch_ComboPort_get + * Description: + * Get Combo port ID + * Input: + * None + * Output: + * None + * Return: + * Port ID of combo port + * Note: + * + */ +extern rtk_uint32 rtk_switch_ComboPort_get(void); + +/* Function Name: + * rtk_switch_isPtpPort + * Description: + * Check is logical port a PTP port + * Input: + * logicalPort - logical port ID + * Output: + * None + * Return: + * RT_ERR_OK - Port ID is a PTP port + * RT_ERR_FAILED - Port ID is not a PTP port + * RT_ERR_NOT_INIT - Not Initialize + * Note: + * + */ +extern rtk_api_ret_t rtk_switch_isPtpPort(rtk_port_t logicalPort); + +/* Function Name: + * rtk_switch_port_L2P_get + * Description: + * Get physical port ID + * Input: + * logicalPort - logical port ID + * Output: + * None + * Return: + * Physical port ID + * Note: + * + */ +extern rtk_uint32 rtk_switch_port_L2P_get(rtk_port_t logicalPort); + +/* Function Name: + * rtk_switch_port_P2L_get + * Description: + * Get logical port ID + * Input: + * physicalPort - physical port ID + * Output: + * None + * Return: + * logical port ID + * Note: + * + */ +extern rtk_port_t rtk_switch_port_P2L_get(rtk_uint32 physicalPort); + +/* Function Name: + * rtk_switch_isPortMaskValid + * Description: + * Check portmask is valid or not + * Input: + * pPmask - logical port mask + * Output: + * None + * Return: + * RT_ERR_OK - port mask is valid + * RT_ERR_FAILED - port mask is not valid + * RT_ERR_NOT_INIT - Not Initialize + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * + */ +extern rtk_api_ret_t rtk_switch_isPortMaskValid(rtk_portmask_t *pPmask); + +/* Function Name: + * rtk_switch_isPortMaskUtp + * Description: + * Check all ports in portmask are only UTP port + * Input: + * pPmask - logical port mask + * Output: + * None + * Return: + * RT_ERR_OK - Only UTP port in port mask + * RT_ERR_FAILED - Not only UTP port in port mask + * RT_ERR_NOT_INIT - Not Initialize + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * + */ +extern rtk_api_ret_t rtk_switch_isPortMaskUtp(rtk_portmask_t *pPmask); + +/* Function Name: + * rtk_switch_isPortMaskExt + * Description: + * Check all ports in portmask are only EXT port + * Input: + * pPmask - logical port mask + * Output: + * None + * Return: + * RT_ERR_OK - Only EXT port in port mask + * RT_ERR_FAILED - Not only EXT port in port mask + * RT_ERR_NOT_INIT - Not Initialize + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * + */ +extern rtk_api_ret_t rtk_switch_isPortMaskExt(rtk_portmask_t *pPmask); + +/* Function Name: + * rtk_switch_portmask_L2P_get + * Description: + * Get physicl portmask from logical portmask + * Input: + * pLogicalPmask - logical port mask + * Output: + * pPhysicalPortmask - physical port mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_NOT_INIT - Not Initialize + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_PORT_MASK - Error port mask + * Note: + * + */ +extern rtk_api_ret_t rtk_switch_portmask_L2P_get(rtk_portmask_t *pLogicalPmask, rtk_uint32 *pPhysicalPortmask); + +/* Function Name: + * rtk_switch_portmask_P2L_get + * Description: + * Get logical portmask from physical portmask + * Input: + * physicalPortmask - physical port mask + * Output: + * pLogicalPmask - logical port mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_NOT_INIT - Not Initialize + * RT_ERR_NULL_POINTER - Null pointer + * RT_ERR_PORT_MASK - Error port mask + * Note: + * + */ +extern rtk_api_ret_t rtk_switch_portmask_P2L_get(rtk_uint32 physicalPortmask, rtk_portmask_t *pLogicalPmask); + +/* Function Name: + * rtk_switch_phyPortMask_get + * Description: + * Get physical portmask + * Input: + * None + * Output: + * None + * Return: + * 0x00 - Not Initialize + * Other value - Physical port mask + * Note: + * + */ +rtk_uint32 rtk_switch_phyPortMask_get(void); + +/* Function Name: + * rtk_switch_logPortMask_get + * Description: + * Get Logical portmask + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_NOT_INIT - Not Initialize + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * + */ +rtk_api_ret_t rtk_switch_logPortMask_get(rtk_portmask_t *pPortmask); + +/* Function Name: + * rtk_switch_init + * Description: + * Set chip to default configuration enviroment + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can set chip registers to default configuration for different release chip model. + */ +extern rtk_api_ret_t rtk_switch_init(void); + +/* Function Name: + * rtk_switch_portMaxPktLen_set + * Description: + * Set Max packet length + * Input: + * port - Port ID + * speed - Speed + * cfgId - Configuration ID + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + */ +extern rtk_api_ret_t rtk_switch_portMaxPktLen_set(rtk_port_t port, rtk_switch_maxPktLen_linkSpeed_t speed, rtk_uint32 cfgId); + +/* Function Name: + * rtk_switch_portMaxPktLen_get + * Description: + * Get Max packet length + * Input: + * port - Port ID + * speed - Speed + * Output: + * pCfgId - Configuration ID + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + */ +extern rtk_api_ret_t rtk_switch_portMaxPktLen_get(rtk_port_t port, rtk_switch_maxPktLen_linkSpeed_t speed, rtk_uint32 *pCfgId); + +/* Function Name: + * rtk_switch_maxPktLenCfg_set + * Description: + * Set Max packet length configuration + * Input: + * cfgId - Configuration ID + * pktLen - Max packet length + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + */ +extern rtk_api_ret_t rtk_switch_maxPktLenCfg_set(rtk_uint32 cfgId, rtk_uint32 pktLen); + +/* Function Name: + * rtk_switch_maxPktLenCfg_get + * Description: + * Get Max packet length configuration + * Input: + * cfgId - Configuration ID + * pPktLen - Max packet length + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + */ +extern rtk_api_ret_t rtk_switch_maxPktLenCfg_get(rtk_uint32 cfgId, rtk_uint32 *pPktLen); + +/* Function Name: + * rtk_switch_greenEthernet_set + * Description: + * Set all Ports Green Ethernet state. + * Input: + * enable - Green Ethernet state. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * This API can set all Ports Green Ethernet state. + * The configuration is as following: + * - DISABLE + * - ENABLE + */ +extern rtk_api_ret_t rtk_switch_greenEthernet_set(rtk_enable_t enable); + +/* Function Name: + * rtk_switch_greenEthernet_get + * Description: + * Get all Ports Green Ethernet state. + * Input: + * None + * Output: + * pEnable - Green Ethernet state. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API can get Green Ethernet state. + */ +extern rtk_api_ret_t rtk_switch_greenEthernet_get(rtk_enable_t *pEnable); + +/* Function Name: + * rtk_switch_maxLogicalPort_get + * Description: + * Get Max logical port ID + * Input: + * None + * Output: + * None + * Return: + * Max logical port + * Note: + * This API can get max logical port + */ +extern rtk_port_t rtk_switch_maxLogicalPort_get(void); + +/* Function Name: + * rtk_switch_maxMeterId_get + * Description: + * Get Max Meter ID + * Input: + * None + * Output: + * None + * Return: + * 0x00 - Not Initialize + * Other value - Max Meter ID + * Note: + * + */ +extern rtk_uint32 rtk_switch_maxMeterId_get(void); + +/* Function Name: + * rtk_switch_maxLutAddrNumber_get + * Description: + * Get Max LUT Address number + * Input: + * None + * Output: + * None + * Return: + * 0x00 - Not Initialize + * Other value - Max LUT Address number + * Note: + * + */ +extern rtk_uint32 rtk_switch_maxLutAddrNumber_get(void); + +/* Function Name: + * rtk_switch_isValidTrunkGrpId + * Description: + * Check if trunk group is valid or not + * Input: + * grpId - Group ID + * Output: + * None + * Return: + * RT_ERR_OK - Trunk Group ID is valid + * RT_ERR_LA_TRUNK_ID - Trunk Group ID is not valid + * Note: + * + */ +rtk_uint32 rtk_switch_isValidTrunkGrpId(rtk_uint32 grpId); + +/* Function Name: + * rtk_switch_maxBufferPageNum_get + * Description: + * Get number of packet buffer page + * Input: + * None + * Output: + * None + * Return: + * Number of packet buffer page + * Note: + * + */ +rtk_uint32 rtk_switch_maxBufferPageNum_get(void); + +/* Function Name: + * rtk_switch_chipType_get + * Description: + * Get switch chip type + * Input: + * None + * Output: + * None + * Return: + * CHIP_END - Unknown chip type + * other - Switch chip type + * Note: + * + */ +switch_chip_t rtk_switch_chipType_get(void); + +#endif diff --git a/sources/uboot-be550/drivers/net/rtl8372/rtk_types.h b/sources/uboot-be550/drivers/net/rtl8372/rtk_types.h new file mode 100755 index 00000000..75c5693b --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/rtk_types.h @@ -0,0 +1,131 @@ +#ifndef _RTL8373_TYPES_H_ +#define _RTL8373_TYPES_H_ + +#include +#include +#include + +typedef unsigned long long rtk_uint64; +typedef long long rtk_int64; +typedef unsigned int rtk_uint32; +typedef int rtk_int32; +typedef unsigned short rtk_uint16; +typedef short rtk_int16; +typedef unsigned char rtk_uint8; +typedef char rtk_int8; + +#define CONST_T const + +#define RTK_TOTAL_NUM_OF_WORD_FOR_1BIT_PORT_LIST 1 + +#define RTK_MAX_NUM_OF_PORT 10 +#define RTK_PORT_ID_MAX (RTK_MAX_NUM_OF_PORT-1) +#define RTK_PHY_ID_MAX (RTK_MAX_NUM_OF_PORT-4) +#define RTK_MAX_PORT_MASK 0x3FF +#define RTK_MAX_NUM_OF_PROTO_TYPE (0xFFFF) + +#define RTK_WHOLE_SYSTEM 0xFF + +typedef struct rtk_portmask_s +{ + rtk_uint32 bits[RTK_TOTAL_NUM_OF_WORD_FOR_1BIT_PORT_LIST]; +} rtk_portmask_t; + +typedef enum rtk_enable_e +{ + DISABLED = 0, + ENABLED, + RTK_ENABLE_END +} rtk_enable_t; + +typedef enum rtk_valid_e +{ + INVALID = 0, + VALID_RTL8372, + RTK_VALID_END +} rtk_valid_t; + + +#ifndef ETHER_ADDR_LEN +#define ETHER_ADDR_LEN 6 +#endif + +/* ethernet address type */ +typedef struct rtk_mac_s +{ + rtk_uint8 octet[ETHER_ADDR_LEN]; +} rtk_mac_t; + +typedef rtk_uint32 rtk_pri_t; /* priority vlaue */ +typedef rtk_uint32 rtk_qid_t; /* queue id type */ +typedef rtk_uint32 rtk_data_t; +typedef rtk_uint32 rtk_dscp_t; /* dscp vlaue */ +typedef rtk_uint32 rtk_fid_t; /* filter id type */ +typedef rtk_uint32 rtk_vlan_t; /* vlan id type */ +typedef rtk_uint32 rtk_mac_cnt_t; /* MAC count type */ +typedef rtk_uint32 rtk_meter_id_t; /* meter id type */ +typedef rtk_uint32 rtk_rate_t; /* rate type */ + +typedef enum rtk_port_e +{ + UTP_PORT0 = 0, + UTP_PORT1, + UTP_PORT2, + UTP_PORT3, + UTP_PORT4, + UTP_PORT5, + UTP_PORT6, + UTP_PORT7, + UTP_PORT8, + UTP_PORT9, + + UNDEFINE_PORT = 30, + RTK_PORT_MAX = 31 +} rtk_port_t; + + +#ifndef _RTL_TYPES_H + +typedef rtk_uint32 ipaddr_t; +typedef rtk_uint32 memaddr; + +#ifndef ETHER_ADDR_LEN +#define ETHER_ADDR_LEN 6 +#endif + +typedef struct ether_addr_s { + rtk_uint8 octet[ETHER_ADDR_LEN]; +} ether_addr_t; + +#define PRINT printf +#endif /*_RTL_TYPES_H*/ + +/* type abstraction */ +#ifdef EMBEDDED_SUPPORT + +typedef rtk_int16 rtk_api_ret_t; +typedef rtk_int16 ret_t; +typedef rtk_uint32 rtk_u_long; + +#else + +typedef rtk_int32 rtk_api_ret_t; +typedef rtk_int32 ret_t; +typedef rtk_uint64 rtk_u_long_t; + +#endif + +#ifndef NULL +#define NULL 0 +#endif + +#ifndef TRUE +#define TRUE 1 +#endif + +#ifndef FALSE +#define FALSE 0 +#endif + +#define CONST const +#endif /* _RTL8373_TYPES_H_ */ diff --git a/sources/uboot-be550/drivers/net/rtl8372/sharemeter.c b/sources/uboot-be550/drivers/net/rtl8372/sharemeter.c new file mode 100755 index 00000000..e25dc28b --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/sharemeter.c @@ -0,0 +1,554 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8373 + * Feature : Here is a list of all functions and variables in rate module. + * + */ + +#include +#include +#include +#include + +#include + +/* Function Name: + * rtk_rate_shareMeter_set + * Description: + * Set meter configuration + * Input: + * index - shared meter index(0 - 63) + * type - shared meter type + * rate - rate of share meter + * ifg_include - include IFG or not, ENABLE:include DISABLE:exclude + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_METER_ID - Invalid meter + * RT_ERR_RATE - Invalid rate + * RT_ERR_INPUT - Invalid input parameters + * Note: + * The API can set shared meter rate and ifg include for each meter. + * The rate unit is 16 kbps and the range is from 0 to 0x98968 if type is METER_TYPE_KBPS and + * the granularity of rate is 16 kbps. + * The rate unit is packets per second and the range is 0 ~ 0xFFFFF if type is METER_TYPE_PPS. + * The ifg_include parameter is used + * for rate calculation with/without inter-frame-gap and preamble. + */ +rtk_api_ret_t rtk_rate_shareMeter_set(rtk_meter_id_t index, rtk_meter_type_t type, rtk_rate_t rate, rtk_enable_t ifg_include) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rate_shareMeter_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rate_shareMeter_set(index, type, rate, ifg_include); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_rate_shareMeter_get + * Description: + * Get meter configuration + * Input: + * index - shared meter index(0 - 63) + * Output: + * pType - Meter Type + * pRate - pointer of rate of share meter + * pIfg_include - include IFG or not, ENABLE:include DISABLE:exclude + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_METER_ID - Invalid meter + * Note: + * + */ +rtk_api_ret_t rtk_rate_shareMeter_get(rtk_meter_id_t index, rtk_meter_type_t *pType, rtk_rate_t *pRate, rtk_enable_t *pIfg_include) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rate_shareMeter_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rate_shareMeter_get(index, pType, pRate, pIfg_include); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_rate_shareMeterBucket_set + * Description: + * Set meter Bucket Size + * Input: + * index - shared meter index + * bucket_size - Bucket Size + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_INPUT - Error Input + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_METER_ID - Invalid meter + * Note: + * The API can set shared meter bucket size. + */ +rtk_api_ret_t rtk_rate_shareMeterBucket_set(rtk_meter_id_t index, rtk_uint32 bucket_size) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rate_shareMeterBucket_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rate_shareMeterBucket_set(index, bucket_size); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_rate_shareMeterBucket_get + * Description: + * Get meter Bucket Size + * Input: + * index - shared meter index + * Output: + * pBucket_size - Bucket Size + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_METER_ID - Invalid meter + * Note: + * The API can get shared meter bucket size. + */ +rtk_api_ret_t rtk_rate_shareMeterBucket_get(rtk_meter_id_t index, rtk_uint32 *pBucket_size) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rate_shareMeterBucket_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rate_shareMeterBucket_get(index, pBucket_size); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_rate_shareMeterExceedStatus_set + * Description: + * Clear shared meter status + * Input: + * index - share meter index (0 - 63) + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_METER_ID - Invalid meter + * Note: + * None + */ +ret_t rtk_rate_shareMeterExceedStatus_set(rtk_uint32 index) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rate_shareMeterExceedStatus_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rate_shareMeterExceedStatus_set(index); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_rate_shareMeterExceedStatus_get + * Description: + * Get shared meter status + * Input: + * index - share meter index (0-63) + * pStatus - 0: rate doesn't exceed 1: rate exceeds + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_METER_ID - Invalid meter + * Note: + * If rate is over rate*16Kbps of a meter, the state bit of this meter is set to 1. + */ +ret_t rtk_rate_shareMeterExceedStatus_get(rtk_uint32 index, rtk_uint32 *pStatus) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rate_shareMeterExceedStatus_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rate_shareMeterExceedStatus_get(index, pStatus); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_rate_shareMeterICPUExceedStatus_set + * Description: + * Clear shared meter ICPU status + * Input: + * index - meter index (0 - 63) + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_METER_ID - Invalid meter + * Note: + * None + */ +ret_t rtk_rate_shareMeterICPUExceedStatus_set(rtk_uint32 index) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rate_shareMeterICPUExceedStatus_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rate_shareMeterICPUExceedStatus_set(index); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_rate_shareMeterICPUExceedStatus_get + * Description: + * Get shared meter ICPU exceed status + * Input: + * index - meter index (0 - 63) + * pStatus - 0: rate doesn't exceed 1: rate exceeds + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_METER_ID - Invalid meter + * Note: + * If rate is over rate*16Kbps of a meter, the state bit of this meter is set to 1. + */ +ret_t rtk_rate_shareMeterICPUExceedStatus_get(rtk_uint32 index, rtk_uint32* pStatus) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rate_shareMeterICPUExceedStatus_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rate_shareMeterICPUExceedStatus_get(index, pStatus); + RTK_API_UNLOCK(); + + return retVal; +} + +#if 0 +/* Function Name: + * rtk_rate_igrBandwidthCtrlRate_set + * Description: + * Set port ingress bandwidth control + * Input: + * port - Port id + * rate - Rate of share meter + * ifg_include - include IFG or not, ENABLE:include DISABLE:exclude + * fc_enable - enable flow control or not, ENABLE:use flow control DISABLE:drop + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid IFG parameter. + * RT_ERR_INBW_RATE - Invalid ingress rate parameter. + * Note: + * The rate unit is 1 kbps and the range is from 8k to 1048568k. The granularity of rate is 8 kbps. + * The ifg_include parameter is used for rate calculation with/without inter-frame-gap and preamble. + */ +rtk_api_ret_t rtk_rate_igrBandwidthCtrlRate_set(rtk_port_t port, rtk_rate_t rate, rtk_enable_t ifg_include, rtk_enable_t fc_enable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rate_igrBandwidthCtrlRate_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rate_igrBandwidthCtrlRate_set(port, rate, ifg_include, fc_enable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_rate_igrBandwidthCtrlRate_get + * Description: + * Get port ingress bandwidth control + * Input: + * port - Port id + * Output: + * pRate - Rate of share meter + * pIfg_include - Rate's calculation including IFG, ENABLE:include DISABLE:exclude + * pFc_enable - enable flow control or not, ENABLE:use flow control DISABLE:drop + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The rate unit is 1 kbps and the range is from 8k to 1048568k. The granularity of rate is 8 kbps. + * The ifg_include parameter is used for rate calculation with/without inter-frame-gap and preamble. + */ +rtk_api_ret_t rtk_rate_igrBandwidthCtrlRate_get(rtk_port_t port, rtk_rate_t *pRate, rtk_enable_t *pIfg_include, rtk_enable_t *pFc_enable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rate_igrBandwidthCtrlRate_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rate_igrBandwidthCtrlRate_get(port, pRate, pIfg_include, pFc_enable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_rate_egrBandwidthCtrlRate_set + * Description: + * Set port egress bandwidth control + * Input: + * port - Port id + * rate - Rate of egress bandwidth + * ifg_include - include IFG or not, ENABLE:include DISABLE:exclude + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_QOS_EBW_RATE - Invalid egress bandwidth/rate + * Note: + * The rate unit is 1 kbps and the range is from 8k to 1048568k. The granularity of rate is 8 kbps. + * The ifg_include parameter is used for rate calculation with/without inter-frame-gap and preamble. + */ +rtk_api_ret_t rtk_rate_egrBandwidthCtrlRate_set( rtk_port_t port, rtk_rate_t rate, rtk_enable_t ifg_include) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rate_egrBandwidthCtrlRate_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rate_egrBandwidthCtrlRate_set(port, rate, ifg_include); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_rate_egrBandwidthCtrlRate_get + * Description: + * Get port egress bandwidth control + * Input: + * port - Port id + * Output: + * pRate - Rate of egress bandwidth + * pIfg_include - Rate's calculation including IFG, ENABLE:include DISABLE:exclude + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The rate unit is 1 kbps and the range is from 8k to 1048568k. The granularity of rate is 8 kbps. + * The ifg_include parameter is used for rate calculation with/without inter-frame-gap and preamble. + */ +rtk_api_ret_t rtk_rate_egrBandwidthCtrlRate_get(rtk_port_t port, rtk_rate_t *pRate, rtk_enable_t *pIfg_include) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rate_egrBandwidthCtrlRate_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rate_egrBandwidthCtrlRate_get(port, pRate, pIfg_include); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_rate_egrQueueBwCtrlEnable_get + * Description: + * Get enable status of egress bandwidth control on specified queue. + * Input: + * unit - unit id + * port - port id + * queue - queue id + * Output: + * pEnable - Pointer to enable status of egress queue bandwidth control + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_QUEUE_ID - invalid queue id + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None + */ +rtk_api_ret_t rtk_rate_egrQueueBwCtrlEnable_get(rtk_port_t port, rtk_qid_t queue, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rate_egrQueueBwCtrlEnable_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rate_egrQueueBwCtrlEnable_get(port, queue, pEnable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_rate_egrQueueBwCtrlEnable_set + * Description: + * Set enable status of egress bandwidth control on specified queue. + * Input: + * port - port id + * queue - queue id + * enable - enable status of egress queue bandwidth control + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_QUEUE_ID - invalid queue id + * RT_ERR_INPUT - invalid input parameter + * Note: + * None + */ +rtk_api_ret_t rtk_rate_egrQueueBwCtrlEnable_set(rtk_port_t port, rtk_qid_t queue, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rate_egrQueueBwCtrlEnable_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rate_egrQueueBwCtrlEnable_set(port, queue, enable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_rate_egrQueueBwCtrlRate_get + * Description: + * Get rate of egress bandwidth control on specified queue. + * Input: + * port - port id + * queue - queue id + * pIndex - shared meter index + * Output: + * pRate - pointer to rate of egress queue bandwidth control + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_QUEUE_ID - invalid queue id + * RT_ERR_FILTER_METER_ID - Invalid meter id + * Note: + * The actual rate control is set in shared meters. + * The unit of granularity is 8Kbps. + */ +rtk_api_ret_t rtk_rate_egrQueueBwCtrlRate_get(rtk_port_t port, rtk_qid_t queue, rtk_meter_id_t *pIndex) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rate_egrQueueBwCtrlRate_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rate_egrQueueBwCtrlRate_get(port, queue, pIndex); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_rate_egrQueueBwCtrlRate_set + * Description: + * Set rate of egress bandwidth control on specified queue. + * Input: + * port - port id + * queue - queue id + * index - shared meter index + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_QUEUE_ID - invalid queue id + * RT_ERR_FILTER_METER_ID - Invalid meter id + * Note: + * The actual rate control is set in shared meters. + * The unit of granularity is 8Kbps. + */ +rtk_api_ret_t rtk_rate_egrQueueBwCtrlRate_set(rtk_port_t port, rtk_qid_t queue, rtk_meter_id_t index) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rate_egrQueueBwCtrlRate_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rate_egrQueueBwCtrlRate_set(port, queue, index); + RTK_API_UNLOCK(); + + return retVal; +} + +#endif + + diff --git a/sources/uboot-be550/drivers/net/rtl8372/sharemeter.h b/sources/uboot-be550/drivers/net/rtl8372/sharemeter.h new file mode 100755 index 00000000..f08b40d2 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/sharemeter.h @@ -0,0 +1,377 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8373 switch high-level API + * + * Feature : The file includes rate module high-layer API defination + * + */ + +#ifndef __RTK_API_SHAREDMETER_H__ +#define __RTK_API_SHAREDMETER_H__ + +/* + * Include Files + */ +//#include + +/* + * Data Type Declaration + */ +typedef enum rtk_meter_type_e{ + METER_TYPE_KBPS = 0, /* Kbps */ + METER_TYPE_PPS, /* Packet per second */ + METER_TYPE_END +}rtk_meter_type_t; + + +/* + * Function Declaration + */ + + /* Rate */ +/* Function Name: + * rtk_rate_shareMeter_set + * Description: + * Set meter configuration + * Input: + * index - shared meter index(0 - 63) + * type - shared meter type + * rate - rate of share meter + * ifg_include - include IFG or not, ENABLE:include DISABLE:exclude + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_METER_ID - Invalid meter + * RT_ERR_RATE - Invalid rate + * RT_ERR_INPUT - Invalid input parameters + * Note: + * The API can set shared meter rate and ifg include for each meter. + * The rate unit is 16 kbps and the range is from 0 to 0x98968 if type is METER_TYPE_KBPS and + * the granularity of rate is 16 kbps. + * The rate unit is packets per second and the range is 0 ~ 0xFFFFF if type is METER_TYPE_PPS. + * The ifg_include parameter is used + * for rate calculation with/without inter-frame-gap and preamble. + */ +extern rtk_api_ret_t rtk_rate_shareMeter_set(rtk_meter_id_t index, rtk_meter_type_t type, rtk_rate_t rate, rtk_enable_t ifg_include); + +/* Function Name: + * rtk_rate_shareMeter_get + * Description: + * Get meter configuration + * Input: + * index - shared meter index(0 - 63) + * Output: + * pType - Meter Type + * pRate - pointer of rate of share meter + * pIfg_include - include IFG or not, ENABLE:include DISABLE:exclude + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_METER_ID - Invalid meter + * Note: + * + */ +extern rtk_api_ret_t rtk_rate_shareMeter_get(rtk_meter_id_t index, rtk_meter_type_t *pType, rtk_rate_t *pRate, rtk_enable_t *pIfg_include); + +/* Function Name: + * rtk_rate_shareMeterBucket_set + * Description: + * Set meter Bucket Size + * Input: + * index - shared meter index + * bucket_size - Bucket Size + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_INPUT - Error Input + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_METER_ID - Invalid meter + * Note: + * The API can set shared meter bucket size. + */ +extern rtk_api_ret_t rtk_rate_shareMeterBucket_set(rtk_meter_id_t index, rtk_uint32 bucket_size); + +/* Function Name: + * rtk_rate_shareMeterBucket_get + * Description: + * Get meter Bucket Size + * Input: + * index - shared meter index + * Output: + * pBucket_size - Bucket Size + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_METER_ID - Invalid meter + * Note: + * The API can get shared meter bucket size. + */ +extern rtk_api_ret_t rtk_rate_shareMeterBucket_get(rtk_meter_id_t index, rtk_uint32 *pBucket_size); + +/* Function Name: + * rtk_rate_shareMeterExceedStatus_set + * Description: + * Clear shared meter status + * Input: + * index - share meter index (0 - 63) + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_METER_ID - Invalid meter + * Note: + * None + */ +extern ret_t rtk_rate_shareMeterExceedStatus_set(rtk_uint32 index); + +/* Function Name: + * rtk_rate_shareMeterExceedStatus_get + * Description: + * Get shared meter status + * Input: + * index - share meter index (0-63) + * pStatus - 0: rate doesn't exceed 1: rate exceeds + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_METER_ID - Invalid meter + * Note: + * If rate is over rate*16Kbps of a meter, the state bit of this meter is set to 1. + */ +extern ret_t rtk_rate_shareMeterExceedStatus_get(rtk_uint32 index, rtk_uint32 *pStatus); + +/* Function Name: + * rtk_rate_shareMeterICPUExceedStatus_set + * Description: + * Clear shared meter ICPU status + * Input: + * index - meter index (0 - 63) + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_METER_ID - Invalid meter + * Note: + * None + */ +extern ret_t rtk_rate_shareMeterICPUExceedStatus_set(rtk_uint32 index); + +/* Function Name: + * rtk_rate_shareMeterICPUExceedStatus_get + * Description: + * Get shared meter ICPU exceed status + * Input: + * index - meter index (0 - 63) + * pStatus - 0: rate doesn't exceed 1: rate exceeds + * Output: + * None + * Return: + * RT_ERR_OK - Success + * RT_ERR_SMI - SMI access error + * RT_ERR_FILTER_METER_ID - Invalid meter + * Note: + * If rate is over rate*16Kbps of a meter, the state bit of this meter is set to 1. + */ +extern ret_t rtk_rate_shareMeterICPUExceedStatus_get(rtk_uint32 index, rtk_uint32* pStatus); + +#if 0 +/* Function Name: + * rtk_rate_igrBandwidthCtrlRate_set + * Description: + * Set port ingress bandwidth control + * Input: + * port - Port id + * rate - Rate of share meter + * ifg_include - include IFG or not, ENABLE:include DISABLE:exclude + * fc_enable - enable flow control or not, ENABLE:use flow control DISABLE:drop + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_ENABLE - Invalid IFG parameter. + * RT_ERR_INBW_RATE - Invalid ingress rate parameter. + * Note: + * The rate unit is 1 kbps and the range is from 8k to 1048568k. The granularity of rate is 8 kbps. + * The ifg_include parameter is used for rate calculation with/without inter-frame-gap and preamble. + */ +extern rtk_api_ret_t rtk_rate_igrBandwidthCtrlRate_set( rtk_port_t port, rtk_rate_t rate, rtk_enable_t ifg_include, rtk_enable_t fc_enable); + +/* Function Name: + * rtk_rate_igrBandwidthCtrlRate_get + * Description: + * Get port ingress bandwidth control + * Input: + * port - Port id + * Output: + * pRate - Rate of share meter + * pIfg_include - Rate's calculation including IFG, ENABLE:include DISABLE:exclude + * pFc_enable - enable flow control or not, ENABLE:use flow control DISABLE:drop + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The rate unit is 1 kbps and the range is from 8k to 1048568k. The granularity of rate is 8 kbps. + * The ifg_include parameter is used for rate calculation with/without inter-frame-gap and preamble. + */ +extern rtk_api_ret_t rtk_rate_igrBandwidthCtrlRate_get(rtk_port_t port, rtk_rate_t *pRate, rtk_enable_t *pIfg_include, rtk_enable_t *pFc_enable); + +/* Function Name: + * rtk_rate_egrBandwidthCtrlRate_set + * Description: + * Set port egress bandwidth control + * Input: + * port - Port id + * rate - Rate of egress bandwidth + * ifg_include - include IFG or not, ENABLE:include DISABLE:exclude + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_QOS_EBW_RATE - Invalid egress bandwidth/rate + * Note: + * The rate unit is 1 kbps and the range is from 8k to 1048568k. The granularity of rate is 8 kbps. + * The ifg_include parameter is used for rate calculation with/without inter-frame-gap and preamble. + */ +extern rtk_api_ret_t rtk_rate_egrBandwidthCtrlRate_set(rtk_port_t port, rtk_rate_t rate, rtk_enable_t ifg_includ); + +/* Function Name: + * rtk_rate_egrBandwidthCtrlRate_get + * Description: + * Get port egress bandwidth control + * Input: + * port - Port id + * Output: + * pRate - Rate of egress bandwidth + * pIfg_include - Rate's calculation including IFG, ENABLE:include DISABLE:exclude + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The rate unit is 1 kbps and the range is from 8k to 1048568k. The granularity of rate is 8 kbps. + * The ifg_include parameter is used for rate calculation with/without inter-frame-gap and preamble. + */ +extern rtk_api_ret_t rtk_rate_egrBandwidthCtrlRate_get(rtk_port_t port, rtk_rate_t *pRate, rtk_enable_t *pIfg_include); + +/* Function Name: + * rtk_rate_egrQueueBwCtrlEnable_set + * Description: + * Set enable status of egress bandwidth control on specified queue. + * Input: + * port - port id + * queue - queue id + * enable - enable status of egress queue bandwidth control + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_QUEUE_ID - invalid queue id + * RT_ERR_INPUT - invalid input parameter + * Note: + * None + */ +extern rtk_api_ret_t rtk_rate_egrQueueBwCtrlEnable_set(rtk_port_t port, rtk_qid_t queue, rtk_enable_t enable); + +/* Function Name: + * rtk_rate_egrQueueBwCtrlRate_get + * Description: + * Get rate of egress bandwidth control on specified queue. + * Input: + * port - port id + * queue - queue id + * pIndex - shared meter index + * Output: + * pRate - pointer to rate of egress queue bandwidth control + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_QUEUE_ID - invalid queue id + * RT_ERR_FILTER_METER_ID - Invalid meter id + * Note: + * None. + */ +extern rtk_api_ret_t rtk_rate_egrQueueBwCtrlEnable_get(rtk_port_t port, rtk_qid_t queue, rtk_enable_t *pEnable); + +/* Function Name: + * rtk_rate_egrQueueBwCtrlRate_set + * Description: + * Set rate of egress bandwidth control on specified queue. + * Input: + * port - port id + * queue - queue id + * index - shared meter index + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_QUEUE_ID - invalid queue id + * RT_ERR_FILTER_METER_ID - Invalid meter id + * Note: + * The actual rate control is set in shared meters. + * The unit of granularity is 8Kbps. + */ +extern rtk_api_ret_t rtk_rate_egrQueueBwCtrlRate_set(rtk_port_t port, rtk_qid_t queue, rtk_meter_id_t index); + +/* Function Name: + * rtk_rate_egrQueueBwCtrlRate_get + * Description: + * Get rate of egress bandwidth control on specified queue. + * Input: + * port - port id + * queue - queue id + * pIndex - shared meter index + * Output: + * pRate - pointer to rate of egress queue bandwidth control + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_QUEUE_ID - invalid queue id + * RT_ERR_FILTER_METER_ID - Invalid meter id + * Note: + * The actual rate control is set in shared meters. + * The unit of granularity is 8Kbps. + */ +extern rtk_api_ret_t rtk_rate_egrQueueBwCtrlRate_get(rtk_port_t port, rtk_qid_t queue, rtk_meter_id_t *pIndex); +#endif + +#endif /* __RTK_API_SHAREDMETER_H__ */ + + diff --git a/sources/uboot-be550/drivers/net/rtl8372/storm.c b/sources/uboot-be550/drivers/net/rtl8372/storm.c new file mode 100755 index 00000000..da4f8eed --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/storm.c @@ -0,0 +1,507 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8373 + * Feature : Here is a list of all functions and variables in Storm module. + * + */ + +#include +#include +#include +#include + +#include + +/* Function Name: + * dal_rtl8371c_rate_stormControlMeterIdx_set + * Description: + * Set the storm control meter index. + * Input: + * port - port id + * storm_type - storm group type + * index - storm control meter index. + * Output: + * None. + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - Invalid port id + * RT_ERR_FILTER_METER_ID - Invalid meter + * Note: + * + */ +rtk_api_ret_t rtk_rate_stormControlMeterIdx_set(rtk_port_t port, rtk_rate_storm_group_t stormType, rtk_uint32 index) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rate_stormControlMeterIdx_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rate_stormControlMeterIdx_set(port, stormType, index); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_rate_stormControlMeterIdx_get + * Description: + * Get the storm control meter index. + * Input: + * port - port id + * storm_type - storm group type + * Output: + * pIndex - storm control meter index. + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - Invalid port id + * RT_ERR_FILTER_METER_ID - Invalid meter + * Note: + * + */ +rtk_api_ret_t rtk_rate_stormControlMeterIdx_get(rtk_port_t port, rtk_rate_storm_group_t stormType, rtk_uint32 *pIndex) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rate_stormControlMeterIdx_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rate_stormControlMeterIdx_get(port, stormType, pIndex); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_rate_stormControlPortEnable_set + * Description: + * Set enable status of storm control on specified port. + * Input: + * port - port id + * stormType - storm group type + * enable - enable status of storm control + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +rtk_api_ret_t rtk_rate_stormControlPortEnable_set(rtk_port_t port, rtk_rate_storm_group_t stormType, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rate_stormControlPortEnable_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rate_stormControlPortEnable_set(port, stormType, enable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_rate_stormControlPortEnable_set + * Description: + * Set enable status of storm control on specified port. + * Input: + * port - port id + * stormType - storm group type + * Output: + * pEnable - enable status of storm control + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +rtk_api_ret_t rtk_rate_stormControlPortEnable_get(rtk_port_t port, rtk_rate_storm_group_t stormType, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rate_stormControlPortEnable_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rate_stormControlPortEnable_get(port, stormType, pEnable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_storm_bypass_set + * Description: + * Set bypass storm filter control configuration. + * Input: + * type - Bypass storm filter control type. + * enable - Bypass status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_ENABLE - Invalid IFG parameter + * Note: + * + * This API can set per-port bypass stomr filter control frame type including RMA and igmp. + * The bypass frame type is as following: + * - BYPASS_BRG_GROUP, + * - BYPASS_FD_PAUSE, + * - BYPASS_SP_MCAST, + * - BYPASS_1X_PAE, + * - BYPASS_UNDEF_BRG_04, + * - BYPASS_UNDEF_BRG_05, + * - BYPASS_UNDEF_BRG_06, + * - BYPASS_UNDEF_BRG_07, + * - BYPASS_PROVIDER_BRIDGE_GROUP_ADDRESS, + * - BYPASS_UNDEF_BRG_09, + * - BYPASS_UNDEF_BRG_0A, + * - BYPASS_UNDEF_BRG_0B, + * - BYPASS_UNDEF_BRG_0C, + * - BYPASS_PROVIDER_BRIDGE_GVRP_ADDRESS, + * - BYPASS_8021AB, + * - BYPASS_UNDEF_BRG_0F, + * - BYPASS_BRG_MNGEMENT, + * - BYPASS_UNDEFINED_11, + * - BYPASS_UNDEFINED_12, + * - BYPASS_UNDEFINED_13, + * - BYPASS_UNDEFINED_14, + * - BYPASS_UNDEFINED_15, + * - BYPASS_UNDEFINED_16, + * - BYPASS_UNDEFINED_17, + * - BYPASS_UNDEFINED_18, + * - BYPASS_UNDEFINED_19, + * - BYPASS_UNDEFINED_1A, + * - BYPASS_UNDEFINED_1B, + * - BYPASS_UNDEFINED_1C, + * - BYPASS_UNDEFINED_1D, + * - BYPASS_UNDEFINED_1E, + * - BYPASS_UNDEFINED_1F, + * - BYPASS_GMRP, + * - BYPASS_GVRP, + * - BYPASS_UNDEF_GARP_22, + * - BYPASS_UNDEF_GARP_23, + * - BYPASS_UNDEF_GARP_24, + * - BYPASS_UNDEF_GARP_25, + * - BYPASS_UNDEF_GARP_26, + * - BYPASS_UNDEF_GARP_27, + * - BYPASS_UNDEF_GARP_28, + * - BYPASS_UNDEF_GARP_29, + * - BYPASS_UNDEF_GARP_2A, + * - BYPASS_UNDEF_GARP_2B, + * - BYPASS_UNDEF_GARP_2C, + * - BYPASS_UNDEF_GARP_2D, + * - BYPASS_UNDEF_GARP_2E, + * - BYPASS_UNDEF_GARP_2F, + * - BYPASS_IGMP. + * - BYPASS_CDP. + * - BYPASS_CSSTP. + * - BYPASS_LLDP. + */ +rtk_api_ret_t rtk_storm_bypass_set(rtk_storm_bypass_t type, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->storm_bypass_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->storm_bypass_set(type, enable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_storm_bypass_get + * Description: + * Get bypass storm filter control configuration. + * Input: + * type - Bypass storm filter control type. + * Output: + * pEnable - Bypass status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can get per-port bypass stomr filter control frame type including RMA and igmp. + * The bypass frame type is as following: + * - BYPASS_BRG_GROUP, + * - BYPASS_FD_PAUSE, + * - BYPASS_SP_MCAST, + * - BYPASS_1X_PAE, + * - BYPASS_UNDEF_BRG_04, + * - BYPASS_UNDEF_BRG_05, + * - BYPASS_UNDEF_BRG_06, + * - BYPASS_UNDEF_BRG_07, + * - BYPASS_PROVIDER_BRIDGE_GROUP_ADDRESS, + * - BYPASS_UNDEF_BRG_09, + * - BYPASS_UNDEF_BRG_0A, + * - BYPASS_UNDEF_BRG_0B, + * - BYPASS_UNDEF_BRG_0C, + * - BYPASS_PROVIDER_BRIDGE_GVRP_ADDRESS, + * - BYPASS_8021AB, + * - BYPASS_UNDEF_BRG_0F, + * - BYPASS_BRG_MNGEMENT, + * - BYPASS_UNDEFINED_11, + * - BYPASS_UNDEFINED_12, + * - BYPASS_UNDEFINED_13, + * - BYPASS_UNDEFINED_14, + * - BYPASS_UNDEFINED_15, + * - BYPASS_UNDEFINED_16, + * - BYPASS_UNDEFINED_17, + * - BYPASS_UNDEFINED_18, + * - BYPASS_UNDEFINED_19, + * - BYPASS_UNDEFINED_1A, + * - BYPASS_UNDEFINED_1B, + * - BYPASS_UNDEFINED_1C, + * - BYPASS_UNDEFINED_1D, + * - BYPASS_UNDEFINED_1E, + * - BYPASS_UNDEFINED_1F, + * - BYPASS_GMRP, + * - BYPASS_GVRP, + * - BYPASS_UNDEF_GARP_22, + * - BYPASS_UNDEF_GARP_23, + * - BYPASS_UNDEF_GARP_24, + * - BYPASS_UNDEF_GARP_25, + * - BYPASS_UNDEF_GARP_26, + * - BYPASS_UNDEF_GARP_27, + * - BYPASS_UNDEF_GARP_28, + * - BYPASS_UNDEF_GARP_29, + * - BYPASS_UNDEF_GARP_2A, + * - BYPASS_UNDEF_GARP_2B, + * - BYPASS_UNDEF_GARP_2C, + * - BYPASS_UNDEF_GARP_2D, + * - BYPASS_UNDEF_GARP_2E, + * - BYPASS_UNDEF_GARP_2F, + * - BYPASS_IGMP. + * - BYPASS_CDP. + * - BYPASS_CSSTP. + * - BYPASS_LLDP. + */ +rtk_api_ret_t rtk_storm_bypass_get(rtk_storm_bypass_t type, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->storm_bypass_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->storm_bypass_get(type, pEnable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_rate_stormControlExtPortmask_set + * Description: + * Set externsion storm control port mask + * Input: + * portmask - port mask + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +rtk_api_ret_t rtk_rate_stormControlExtPortmask_set(rtk_uint32 portmask) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rate_stormControlExtPortmask_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rate_stormControlExtPortmask_set(portmask); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_rate_stormControlExtPortmask_get + * Description: + * Set externsion storm control port mask + * Input: + * None + * Output: + * pPortmask - port mask + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +rtk_api_ret_t rtk_rate_stormControlExtPortmask_get(rtk_uint32 *pPortmask) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rate_stormControlExtPortmask_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rate_stormControlExtPortmask_get(pPortmask); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_rate_stormControlExtEnable_set + * Description: + * Set externsion storm control state + * Input: + * stormType - storm group type + * enable - externsion storm control state + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +rtk_api_ret_t rtk_rate_stormControlExtEnable_set(rtk_rate_storm_group_t stormType, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rate_stormControlExtEnable_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rate_stormControlExtEnable_set(stormType, enable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_rate_stormControlExtEnable_get + * Description: + * Get externsion storm control state + * Input: + * stormType - storm group type + * Output: + * pEnable - externsion storm control state + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +rtk_api_ret_t rtk_rate_stormControlExtEnable_get(rtk_rate_storm_group_t stormType, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rate_stormControlExtEnable_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rate_stormControlExtEnable_get(stormType, pEnable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_rate_stormControlExtMeterIdx_set + * Description: + * Set externsion storm control meter index + * Input: + * stormType - storm group type + * index - externsion storm control state + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +rtk_api_ret_t rtk_rate_stormControlExtMeterIdx_set(rtk_rate_storm_group_t stormType, rtk_uint32 index) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rate_stormControlExtMeterIdx_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rate_stormControlExtMeterIdx_set(stormType, index); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_rate_stormControlExtMeterIdx_get + * Description: + * Get externsion storm control meter index + * Input: + * stormType - storm group type + * pIndex - externsion storm control state + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +rtk_api_ret_t rtk_rate_stormControlExtMeterIdx_get(rtk_rate_storm_group_t stormType, rtk_uint32 *pIndex) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->rate_stormControlExtMeterIdx_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->rate_stormControlExtMeterIdx_get(stormType, pIndex); + RTK_API_UNLOCK(); + + return retVal; +} + + diff --git a/sources/uboot-be550/drivers/net/rtl8372/storm.h b/sources/uboot-be550/drivers/net/rtl8372/storm.h new file mode 100755 index 00000000..9e38f930 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/storm.h @@ -0,0 +1,420 @@ + /* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8373 switch high-level API + * + * Feature : The file includes Storm module high-layer API defination + * + */ + +#ifndef __RTK_API_STORM_H__ +#define __RTK_API_STORM_H__ + +typedef enum rtk_rate_storm_group_e +{ + STORM_GROUP_UNKNOWN_UNICAST = 0, + STORM_GROUP_UNKNOWN_MULTICAST, + STORM_GROUP_MULTICAST, + STORM_GROUP_BROADCAST, + STORM_GROUP_END +} rtk_rate_storm_group_t; + +typedef enum rtk_storm_bypass_e +{ + BYPASS_BRG_GROUP = 0, + BYPASS_FD_PAUSE, + BYPASS_SP_MCAST, + BYPASS_1X_PAE, + BYPASS_UNDEF_BRG_04, + BYPASS_UNDEF_BRG_05, + BYPASS_UNDEF_BRG_06, + BYPASS_UNDEF_BRG_07, + BYPASS_PROVIDER_BRIDGE_GROUP_ADDRESS, + BYPASS_UNDEF_BRG_09, + BYPASS_UNDEF_BRG_0A, + BYPASS_UNDEF_BRG_0B, + BYPASS_UNDEF_BRG_0C, + BYPASS_PROVIDER_BRIDGE_GVRP_ADDRESS, + BYPASS_8021AB, + BYPASS_UNDEF_BRG_0F, + BYPASS_BRG_MNGEMENT, + BYPASS_UNDEFINED_11, + BYPASS_UNDEFINED_12, + BYPASS_UNDEFINED_13, + BYPASS_UNDEFINED_14, + BYPASS_UNDEFINED_15, + BYPASS_UNDEFINED_16, + BYPASS_UNDEFINED_17, + BYPASS_UNDEFINED_18, + BYPASS_UNDEFINED_19, + BYPASS_UNDEFINED_1A, + BYPASS_UNDEFINED_1B, + BYPASS_UNDEFINED_1C, + BYPASS_UNDEFINED_1D, + BYPASS_UNDEFINED_1E, + BYPASS_UNDEFINED_1F, + BYPASS_GMRP, + BYPASS_GVRP, + BYPASS_UNDEF_GARP_22, + BYPASS_UNDEF_GARP_23, + BYPASS_UNDEF_GARP_24, + BYPASS_UNDEF_GARP_25, + BYPASS_UNDEF_GARP_26, + BYPASS_UNDEF_GARP_27, + BYPASS_UNDEF_GARP_28, + BYPASS_UNDEF_GARP_29, + BYPASS_UNDEF_GARP_2A, + BYPASS_UNDEF_GARP_2B, + BYPASS_UNDEF_GARP_2C, + BYPASS_UNDEF_GARP_2D, + BYPASS_UNDEF_GARP_2E, + BYPASS_UNDEF_GARP_2F, + BYPASS_IGMP, + BYPASS_CDP, + BYPASS_CSSTP, + BYPASS_LLDP, + BYPASS_END, +}rtk_storm_bypass_t; + +/* Function Name: + * rtk_rate_stormControlMeterIdx_set + * Description: + * Set the storm control meter index. + * Input: + * port - port id + * storm_type - storm group type + * index - storm control meter index. + * Output: + * None. + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - Invalid port id + * RT_ERR_FILTER_METER_ID - Invalid meter + * Note: + * + */ +extern rtk_api_ret_t rtk_rate_stormControlMeterIdx_set(rtk_port_t port, rtk_rate_storm_group_t stormType, rtk_uint32 index); + +/* Function Name: + * rtk_rate_stormControlMeterIdx_get + * Description: + * Get the storm control meter index. + * Input: + * port - port id + * storm_type - storm group type + * Output: + * pIndex - storm control meter index. + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_PORT_ID - Invalid port id + * RT_ERR_FILTER_METER_ID - Invalid meter + * Note: + * + */ +extern rtk_api_ret_t rtk_rate_stormControlMeterIdx_get(rtk_port_t port, rtk_rate_storm_group_t stormType, rtk_uint32 *pIndex); + +/* Function Name: + * rtk_rate_stormControlPortEnable_set + * Description: + * Set enable status of storm control on specified port. + * Input: + * port - port id + * stormType - storm group type + * enable - enable status of storm control + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +extern rtk_api_ret_t rtk_rate_stormControlPortEnable_set(rtk_port_t port, rtk_rate_storm_group_t stormType, rtk_enable_t enable); + +/* Function Name: + * rtk_rate_stormControlPortEnable_set + * Description: + * Set enable status of storm control on specified port. + * Input: + * port - port id + * stormType - storm group type + * Output: + * pEnable - enable status of storm control + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_PORT_ID - invalid port id + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +extern rtk_api_ret_t rtk_rate_stormControlPortEnable_get(rtk_port_t port, rtk_rate_storm_group_t stormType, rtk_enable_t *pEnable); + +/* Function Name: + * rtk_storm_bypass_set + * Description: + * Set bypass storm filter control configuration. + * Input: + * type - Bypass storm filter control type. + * enable - Bypass status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_ENABLE - Invalid IFG parameter + * Note: + * + * This API can set per-port bypass stomr filter control frame type including RMA and igmp. + * The bypass frame type is as following: + * - BYPASS_BRG_GROUP, + * - BYPASS_FD_PAUSE, + * - BYPASS_SP_MCAST, + * - BYPASS_1X_PAE, + * - BYPASS_UNDEF_BRG_04, + * - BYPASS_UNDEF_BRG_05, + * - BYPASS_UNDEF_BRG_06, + * - BYPASS_UNDEF_BRG_07, + * - BYPASS_PROVIDER_BRIDGE_GROUP_ADDRESS, + * - BYPASS_UNDEF_BRG_09, + * - BYPASS_UNDEF_BRG_0A, + * - BYPASS_UNDEF_BRG_0B, + * - BYPASS_UNDEF_BRG_0C, + * - BYPASS_PROVIDER_BRIDGE_GVRP_ADDRESS, + * - BYPASS_8021AB, + * - BYPASS_UNDEF_BRG_0F, + * - BYPASS_BRG_MNGEMENT, + * - BYPASS_UNDEFINED_11, + * - BYPASS_UNDEFINED_12, + * - BYPASS_UNDEFINED_13, + * - BYPASS_UNDEFINED_14, + * - BYPASS_UNDEFINED_15, + * - BYPASS_UNDEFINED_16, + * - BYPASS_UNDEFINED_17, + * - BYPASS_UNDEFINED_18, + * - BYPASS_UNDEFINED_19, + * - BYPASS_UNDEFINED_1A, + * - BYPASS_UNDEFINED_1B, + * - BYPASS_UNDEFINED_1C, + * - BYPASS_UNDEFINED_1D, + * - BYPASS_UNDEFINED_1E, + * - BYPASS_UNDEFINED_1F, + * - BYPASS_GMRP, + * - BYPASS_GVRP, + * - BYPASS_UNDEF_GARP_22, + * - BYPASS_UNDEF_GARP_23, + * - BYPASS_UNDEF_GARP_24, + * - BYPASS_UNDEF_GARP_25, + * - BYPASS_UNDEF_GARP_26, + * - BYPASS_UNDEF_GARP_27, + * - BYPASS_UNDEF_GARP_28, + * - BYPASS_UNDEF_GARP_29, + * - BYPASS_UNDEF_GARP_2A, + * - BYPASS_UNDEF_GARP_2B, + * - BYPASS_UNDEF_GARP_2C, + * - BYPASS_UNDEF_GARP_2D, + * - BYPASS_UNDEF_GARP_2E, + * - BYPASS_UNDEF_GARP_2F, + * - BYPASS_IGMP. + */ +extern rtk_api_ret_t rtk_storm_bypass_set(rtk_storm_bypass_t type, rtk_enable_t enable); + +/* Function Name: + * rtk_storm_bypass_get + * Description: + * Get bypass storm filter control configuration. + * Input: + * type - Bypass storm filter control type. + * Output: + * pEnable - Bypass status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API can get per-port bypass stomr filter control frame type including RMA and igmp. + * The bypass frame type is as following: + * - BYPASS_BRG_GROUP, + * - BYPASS_FD_PAUSE, + * - BYPASS_SP_MCAST, + * - BYPASS_1X_PAE, + * - BYPASS_UNDEF_BRG_04, + * - BYPASS_UNDEF_BRG_05, + * - BYPASS_UNDEF_BRG_06, + * - BYPASS_UNDEF_BRG_07, + * - BYPASS_PROVIDER_BRIDGE_GROUP_ADDRESS, + * - BYPASS_UNDEF_BRG_09, + * - BYPASS_UNDEF_BRG_0A, + * - BYPASS_UNDEF_BRG_0B, + * - BYPASS_UNDEF_BRG_0C, + * - BYPASS_PROVIDER_BRIDGE_GVRP_ADDRESS, + * - BYPASS_8021AB, + * - BYPASS_UNDEF_BRG_0F, + * - BYPASS_BRG_MNGEMENT, + * - BYPASS_UNDEFINED_11, + * - BYPASS_UNDEFINED_12, + * - BYPASS_UNDEFINED_13, + * - BYPASS_UNDEFINED_14, + * - BYPASS_UNDEFINED_15, + * - BYPASS_UNDEFINED_16, + * - BYPASS_UNDEFINED_17, + * - BYPASS_UNDEFINED_18, + * - BYPASS_UNDEFINED_19, + * - BYPASS_UNDEFINED_1A, + * - BYPASS_UNDEFINED_1B, + * - BYPASS_UNDEFINED_1C, + * - BYPASS_UNDEFINED_1D, + * - BYPASS_UNDEFINED_1E, + * - BYPASS_UNDEFINED_1F, + * - BYPASS_GMRP, + * - BYPASS_GVRP, + * - BYPASS_UNDEF_GARP_22, + * - BYPASS_UNDEF_GARP_23, + * - BYPASS_UNDEF_GARP_24, + * - BYPASS_UNDEF_GARP_25, + * - BYPASS_UNDEF_GARP_26, + * - BYPASS_UNDEF_GARP_27, + * - BYPASS_UNDEF_GARP_28, + * - BYPASS_UNDEF_GARP_29, + * - BYPASS_UNDEF_GARP_2A, + * - BYPASS_UNDEF_GARP_2B, + * - BYPASS_UNDEF_GARP_2C, + * - BYPASS_UNDEF_GARP_2D, + * - BYPASS_UNDEF_GARP_2E, + * - BYPASS_UNDEF_GARP_2F, + * - BYPASS_IGMP. + */ +extern rtk_api_ret_t rtk_storm_bypass_get(rtk_storm_bypass_t type, rtk_enable_t *pEnable); + +/* Function Name: + * rtk_rate_stormControlExtPortmask_set + * Description: + * Set externsion storm control port mask + * Input: + * pPortmask - port mask + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +extern rtk_api_ret_t rtk_rate_stormControlExtPortmask_set(rtk_uint32 portmask); + +/* Function Name: + * rtk_rate_stormControlExtPortmask_get + * Description: + * Set externsion storm control port mask + * Input: + * None + * Output: + * pPortmask - port mask + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +extern rtk_api_ret_t rtk_rate_stormControlExtPortmask_get(rtk_uint32 *pPortmask); + +/* Function Name: + * rtk_rate_stormControlExtEnable_set + * Description: + * Set externsion storm control state + * Input: + * stormType - storm group type + * enable - externsion storm control state + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +extern rtk_api_ret_t rtk_rate_stormControlExtEnable_set(rtk_rate_storm_group_t stormType, rtk_enable_t enable); + +/* Function Name: + * rtk_rate_stormControlExtEnable_get + * Description: + * Get externsion storm control state + * Input: + * stormType - storm group type + * Output: + * pEnable - externsion storm control state + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +extern rtk_api_ret_t rtk_rate_stormControlExtEnable_get(rtk_rate_storm_group_t stormType, rtk_enable_t *pEnable); + +/* Function Name: + * rtk_rate_stormControlExtMeterIdx_set + * Description: + * Set externsion storm control meter index + * Input: + * stormType - storm group type + * index - externsion storm control state + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +extern rtk_api_ret_t rtk_rate_stormControlExtMeterIdx_set(rtk_rate_storm_group_t stormType, rtk_uint32 index); + +/* Function Name: + * rtk_rate_stormControlExtMeterIdx_get + * Description: + * Get externsion storm control meter index + * Input: + * stormType - storm group type + * pIndex - externsion storm control state + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NOT_INIT - The module is not initial + * RT_ERR_INPUT - invalid input parameter + * Note: + * + */ +extern rtk_api_ret_t rtk_rate_stormControlExtMeterIdx_get(rtk_rate_storm_group_t stormType, rtk_uint32 *pIndex); + + + +#endif /* __RTK_API_STORM_H__ */ + diff --git a/sources/uboot-be550/drivers/net/rtl8372/svlan.c b/sources/uboot-be550/drivers/net/rtl8372/svlan.c new file mode 100755 index 00000000..d06478f3 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/svlan.c @@ -0,0 +1,823 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8373 + * Feature : Here is a list of all functions and variables in SVLAN module. + * + */ + +#include +#include +#include +#include +#include + +#include + + +/* Function Name: + * rtk_svlan_init + * Description: + * Initialize SVLAN Configuration + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * Ether type of S-tag in 802.1ad is 0x88a8 and there are existed ether type 0x9100 and 0x9200 for Q-in-Q SLAN design. + * User can set mathced ether type as service provider supported protocol. + */ +rtk_api_ret_t rtk_svlan_init(void) +{ + rtk_api_ret_t retVal = 0; + + if (NULL == RT_MAPPER->svlan_init) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->svlan_init(); + RTK_API_UNLOCK(); + return retVal; +} + +/* Function Name: + * rtk_svlan_servicePort_add + * Description: + * Add one service port in the specified device + * Input: + * port - Port id. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API is setting which port is connected to provider switch. All frames receiving from this port must + * contain accept SVID in S-tag field. + */ +rtk_api_ret_t rtk_svlan_servicePort_add(rtk_port_t port) +{ + rtk_api_ret_t retVal = 0; + + if (NULL == RT_MAPPER->svlan_servicePort_add) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->svlan_servicePort_add(port); + RTK_API_UNLOCK(); + + return retVal; +} +/* Function Name: + * rtk_svlan_servicePort_get + * Description: + * Get service ports in the specified device. + * Input: + * None + * Output: + * pSvlanPortmask - pointer buffer of svlan ports. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API is setting which port is connected to provider switch. All frames receiving from this port must + * contain accept SVID in S-tag field. + */ +rtk_api_ret_t rtk_svlan_servicePort_get(rtk_portmask_t *pSvlanPortmask) +{ + rtk_api_ret_t retVal = 0; + + if (NULL == RT_MAPPER->svlan_servicePort_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->svlan_servicePort_get(pSvlanPortmask); + RTK_API_UNLOCK(); + + return retVal; +} +/* Function Name: + * rtk_svlan_servicePort_del + * Description: + * Delete one service port in the specified device + * Input: + * port - Port id. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API is removing SVLAN service port in the specified device. + */ +rtk_api_ret_t rtk_svlan_servicePort_del(rtk_port_t port) +{ + rtk_api_ret_t retVal = 0; + + if (NULL == RT_MAPPER->svlan_servicePort_del) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->svlan_servicePort_del(port); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_svlan_tpidEntry_set + * Description: + * Configure accepted S-VLAN ether type. + * Input: + * svlanTpid - Ether type of S-tag frame parsing in uplink ports. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * Note: + * Ether type of S-tag in 802.1ad is 0x88a8 and there are existed ether type 0x9100 and 0x9200 for Q-in-Q SLAN design. + * User can set mathced ether type as service provider supported protocol. + */ +rtk_api_ret_t rtk_svlan_tpidEntry_set(rtk_svlan_tpid_t svlanTpid) +{ + rtk_api_ret_t retVal = 0; + + if (NULL == RT_MAPPER->svlan_tpidEntry_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->svlan_tpidEntry_set(svlanTpid); + RTK_API_UNLOCK(); + + return retVal; +} +/* Function Name: + * rtk_svlan_tpidEntry_get + * Description: + * Get accepted S-VLAN ether type setting. + * Input: + * None + * Output: + * pSvlanTpid - Ether type of S-tag frame parsing in uplink ports. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API is setting which port is connected to provider switch. All frames receiving from this port must + * contain accept SVID in S-tag field. + */ +rtk_api_ret_t rtk_svlan_tpidEntry_get(rtk_svlan_tpid_t *pSvlanTpid) +{ + rtk_api_ret_t retVal = 0; + + if (NULL == RT_MAPPER->svlan_tpidEntry_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->svlan_tpidEntry_get(pSvlanTpid); + RTK_API_UNLOCK(); + + return retVal; +} +/* Function Name: + * rtk_svlan_priorityRef_set + * Description: + * Set S-VLAN upstream priority reference setting. + * Input: + * ref - reference selection parameter. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * Note: + * The API can set the upstream SVLAN tag priority reference source. The related priority + * sources are as following: + * - REF_INTERNAL_PRI, + * - REF_CTAG_PRI, + * - REF_SVLAN_PRI, + * - REF_PB_PRI. + */ +rtk_api_ret_t rtk_svlan_priorityRef_set(rtk_svlan_pri_ref_t ref) +{ + rtk_api_ret_t retVal = 0; + + if (NULL == RT_MAPPER->svlan_priorityRef_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->svlan_priorityRef_set(ref); + RTK_API_UNLOCK(); + + return retVal; +} +/* Function Name: + * rtk_svlan_priorityRef_get + * Description: + * Get S-VLAN upstream priority reference setting. + * Input: + * None + * Output: + * pRef - reference selection parameter. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can get the upstream SVLAN tag priority reference source. The related priority + * sources are as following: + * - REF_INTERNAL_PRI, + * - REF_CTAG_PRI, + * - REF_SVLAN_PRI, + * - REF_PB_PRI + */ +rtk_api_ret_t rtk_svlan_priorityRef_get(rtk_svlan_pri_ref_t *pRef) +{ + rtk_api_ret_t retVal = 0; + + if (NULL == RT_MAPPER->svlan_priorityRef_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->svlan_priorityRef_get(pRef); + RTK_API_UNLOCK(); + + return retVal; +} +#if 0 +/* Function Name: + * rtk_svlan_memberPortEntry_set + * Description: + * Configure system SVLAN member content + * Input: + * svid - SVLAN id + * psvlan_cfg - SVLAN member configuration + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_PORT_MASK - Invalid portmask. + * RT_ERR_SVLAN_TABLE_FULL - SVLAN configuration is full. + * Note: + * The API can set system 64 accepted s-tag frame format. Only 64 SVID S-tag frame will be accpeted + * to receiving from uplink ports. Other SVID S-tag frame or S-untagged frame will be droped by default setup. + * - rtk_svlan_memberCfg_t->svid is SVID of SVLAN member configuration. + * - rtk_svlan_memberCfg_t->memberport is member port mask of SVLAN member configuration. + * - rtk_svlan_memberCfg_t->fid is filtering database of SVLAN member configuration. + * - rtk_svlan_memberCfg_t->priority is priority of SVLAN member configuration. + */ +rtk_api_ret_t rtk_svlan_memberPortEntry_set(rtk_vlan_t svid, rtk_svlan_memberCfg_t *pSvlan_cfg) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->svlan_memberPortEntry_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->svlan_memberPortEntry_set(svid, pSvlan_cfg); + RTK_API_UNLOCK(); + + return retVal; +} +/* Function Name: + * rtk_svlan_memberPortEntry_get + * Description: + * Get SVLAN member Configure. + * Input: + * svid - SVLAN id + * Output: + * pSvlan_cfg - SVLAN member configuration + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get system 64 accepted s-tag frame format. Only 64 SVID S-tag frame will be accpeted + * to receiving from uplink ports. Other SVID S-tag frame or S-untagged frame will be droped. + */ +rtk_api_ret_t rtk_svlan_memberPortEntry_get(rtk_vlan_t svid, rtk_svlan_memberCfg_t *pSvlan_cfg) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->svlan_memberPortEntry_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->svlan_memberPortEntry_get(svid, pSvlan_cfg); + RTK_API_UNLOCK(); + + return retVal; +} +/* Function Name: + * rtk_svlan_memberPortEntry_adv_set + * Description: + * Configure system SVLAN member by index + * Input: + * idx - Index (0 ~ 63) + * psvlan_cfg - SVLAN member configuration + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_PORT_MASK - Invalid portmask. + * RT_ERR_SVLAN_TABLE_FULL - SVLAN configuration is full. + * Note: + * The API can set system 64 accepted s-tag frame format by index. + * - rtk_svlan_memberCfg_t->svid is SVID of SVLAN member configuration. + * - rtk_svlan_memberCfg_t->memberport is member port mask of SVLAN member configuration. + * - rtk_svlan_memberCfg_t->fid is filtering database of SVLAN member configuration. + * - rtk_svlan_memberCfg_t->priority is priority of SVLAN member configuration. + */ +rtk_api_ret_t rtk_svlan_memberPortEntry_adv_set(rtk_uint32 idx, rtk_svlan_memberCfg_t *pSvlan_cfg) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->svlan_memberPortEntry_adv_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->svlan_memberPortEntry_adv_set(idx, pSvlan_cfg); + RTK_API_UNLOCK(); + + return retVal; +} +/* Function Name: + * rtk_svlan_memberPortEntry_adv_get + * Description: + * Get SVLAN member Configure by index. + * Input: + * idx - Index (0 ~ 63) + * Output: + * pSvlan_cfg - SVLAN member configuration + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get system 64 accepted s-tag frame format. Only 64 SVID S-tag frame will be accpeted + * to receiving from uplink ports. Other SVID S-tag frame or S-untagged frame will be droped. + */ +rtk_api_ret_t rtk_svlan_memberPortEntry_adv_get(rtk_uint32 idx, rtk_svlan_memberCfg_t *pSvlan_cfg) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->svlan_memberPortEntry_adv_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->svlan_memberPortEntry_adv_get(idx, pSvlan_cfg); + RTK_API_UNLOCK(); + + return retVal; +} +#endif +/* Function Name: + * rtk_svlan_defaultSvlan_set + * Description: + * Configure default egress SVLAN. + * Input: + * port - Source port + * svid - SVLAN id + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found. + * Note: + * The API can set port n S-tag format index while receiving frame from port n + * is transmit through uplink port with s-tag field + */ +rtk_api_ret_t rtk_svlan_defaultSvlan_set(rtk_port_t port, rtk_vlan_t svid) +{ + + rtk_api_ret_t retVal = 0; + + if (NULL == RT_MAPPER->svlan_defaultSvlan_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->svlan_defaultSvlan_set(port, svid); + RTK_API_UNLOCK(); + + return retVal; +} +/* Function Name: + * rtk_svlan_defaultSvlan_get + * Description: + * Get the configure default egress SVLAN. + * Input: + * port - Source port + * Output: + * pSvid - SVLAN VID + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get port n S-tag format index while receiving frame from port n + * is transmit through uplink port with s-tag field + */ +rtk_api_ret_t rtk_svlan_defaultSvlan_get(rtk_port_t port, rtk_vlan_t *pSvid) +{ + rtk_api_ret_t retVal = 0; + + if (NULL == RT_MAPPER->svlan_defaultSvlan_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->svlan_defaultSvlan_get(port, pSvid); + RTK_API_UNLOCK(); + + return retVal; +} +/* Function Name: + * rtk_svlan_c2s_add + * Description: + * Configure SVLAN C2S table + * Input: + * vid - VLAN ID + * srcPort - Ingress Port + * svid - SVLAN VID + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port ID. + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can set system C2S configuration. ASIC will check upstream's VID and assign related + * SVID to mathed packet. There are 128 SVLAN C2S configurations. + */ +rtk_api_ret_t rtk_svlan_c2s_add(rtk_vlan_t vid, rtk_port_t srcPort, rtk_vlan_t svid) +{ + rtk_api_ret_t retVal = 0; + + if (NULL == RT_MAPPER->svlan_c2s_add) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->svlan_c2s_add(vid, srcPort, svid); + RTK_API_UNLOCK(); + + return retVal; +} +/* Function Name: + * rtk_svlan_c2s_del + * Description: + * Delete one C2S entry + * Input: + * vid - VLAN ID + * srcPort - Ingress Port + * svid - SVLAN VID + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_VLAN_VID - Invalid VID parameter. + * RT_ERR_PORT_ID - Invalid port ID. + * RT_ERR_OUT_OF_RANGE - input out of range. + * Note: + * The API can delete system C2S configuration. There are 128 SVLAN C2S configurations. + */ +rtk_api_ret_t rtk_svlan_c2s_del(rtk_vlan_t vid, rtk_port_t srcPort) +{ + rtk_api_ret_t retVal = 0; + + if (NULL == RT_MAPPER->svlan_c2s_del) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->svlan_c2s_del(vid, srcPort); + RTK_API_UNLOCK(); + + return retVal; +} +/* Function Name: + * rtk_svlan_c2s_get + * Description: + * Get configure SVLAN C2S table + * Input: + * vid - VLAN ID + * srcPort - Ingress Port + * Output: + * pSvid - SVLAN ID + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port ID. + * RT_ERR_OUT_OF_RANGE - input out of range. + * Note: + * The API can get system C2S configuration. There are 128 SVLAN C2S configurations. + */ +rtk_api_ret_t rtk_svlan_c2s_get(rtk_vlan_t vid, rtk_port_t srcPort, rtk_vlan_t *pSvid) +{ + rtk_api_ret_t retVal = 0; + + if (NULL == RT_MAPPER->svlan_c2s_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->svlan_c2s_get(vid, srcPort, pSvid); + RTK_API_UNLOCK(); + + return retVal; +} +/* Function Name: + * rtk_svlan_untag_action_set + * Description: + * Configure Action of downstream UnStag packet + * Input: + * action - Action for UnStag + * svid - The SVID assigned to UnStag packet + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found. + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can configure action of downstream Un-Stag packet. A SVID assigned + * to the un-stag is also supported by this API. The parameter of svid is + * only referenced when the action is set to UNTAG_ASSIGN + */ +rtk_api_ret_t rtk_svlan_untag_action_set(rtk_svlan_untag_action_t action, rtk_vlan_t svid) +{ + rtk_api_ret_t retVal = 0; + + if (NULL == RT_MAPPER->svlan_untag_action_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->svlan_untag_action_set(action, svid); + RTK_API_UNLOCK(); + + return retVal; +} +/* Function Name: + * rtk_svlan_untag_action_get + * Description: + * Get Action of downstream UnStag packet + * Input: + * None + * Output: + * pAction - Action for UnStag + * pSvid - The SVID assigned to UnStag packet + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found. + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can Get action of downstream Un-Stag packet. A SVID assigned + * to the un-stag is also retrieved by this API. The parameter pSvid is + * only refernced when the action is UNTAG_ASSIGN + */ +rtk_api_ret_t rtk_svlan_untag_action_get(rtk_svlan_untag_action_t *pAction, rtk_vlan_t *pSvid) +{ + rtk_api_ret_t retVal = 0; + + if (NULL == RT_MAPPER->svlan_untag_action_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->svlan_untag_action_get(pAction, pSvid); + RTK_API_UNLOCK(); + + return retVal; +} +/* Function Name: + * rtk_svlan_unassign_action_set + * Description: + * Configure Action of upstream without svid assign action + * Input: + * action - Action for Un-assign + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can configure action of upstream Un-assign svid packet. If action is not + * trap to CPU, the port-based SVID sure be assign as system need + */ +rtk_api_ret_t rtk_svlan_unassign_action_set(rtk_svlan_unassign_action_t action) +{ + rtk_api_ret_t retVal = 0; + + if (NULL == RT_MAPPER->svlan_unassign_action_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->svlan_unassign_action_set(action); + RTK_API_UNLOCK(); + + return retVal; +} +/* Function Name: + * rtk_svlan_unassign_action_get + * Description: + * Get action of upstream without svid assignment + * Input: + * None + * Output: + * pAction - Action for Un-assign + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * Note: + * None + */ +rtk_api_ret_t rtk_svlan_unassign_action_get(rtk_svlan_unassign_action_t *pAction) +{ + rtk_api_ret_t retVal = 0; + + if (NULL == RT_MAPPER->svlan_unassign_action_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->svlan_unassign_action_get(pAction); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_svlan_trapPri_set + * Description: + * Set svlan trap priority + * Input: + * priority - priority for trap packets + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_QOS_INT_PRIORITY + * Note: + * None + */ +rtk_api_ret_t rtk_svlan_trapPri_set(rtk_pri_t priority) +{ + rtk_api_ret_t retVal = 0; + + if (NULL == RT_MAPPER->svlan_trapPri_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->svlan_trapPri_set(priority); + RTK_API_UNLOCK(); + + return retVal; +} /* end of rtk_svlan_trapPri_set */ + +/* Function Name: + * rtk_svlan_trapPri_get + * Description: + * Get svlan trap priority + * Input: + * None + * Output: + * pPriority - priority for trap packets + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None + */ +rtk_api_ret_t rtk_svlan_trapPri_get(rtk_pri_t *pPriority) +{ + rtk_api_ret_t retVal = 0; + + if (NULL == RT_MAPPER->svlan_trapPri_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->svlan_trapPri_get(pPriority); + RTK_API_UNLOCK(); + + return retVal; +} /* end of rtk_svlan_trapPri_get */ + + +/* Function Name: + * rtk_svlan_trapCpumsk_set + * Description: + * Set svlan trap priority + * Input: + * cpuMsk - cpu mask for trap packets + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_QOS_INT_PRIORITY + * Note: + * None + */ +rtk_api_ret_t rtk_svlan_trapCpumsk_set(rtk_uint32 cpuMsk) +{ + rtk_api_ret_t retVal = 0; + + if (NULL == RT_MAPPER->svlan_trapCpuMsk_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->svlan_trapCpuMsk_set(cpuMsk); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_svlan_trapCpumsk_get + * Description: + * Get svlan trap cpu mask + * Input: + * None + * Output: + * pCpuMsk - cpu mask for trap packets + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None + */ +rtk_api_ret_t rtk_svlan_trapCpumsk_get(rtk_uint32 *pCpuMsk) +{ + rtk_api_ret_t retVal = 0; + + if (NULL == RT_MAPPER->svlan_trapCpuMsk_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->svlan_trapCpuMsk_get(pCpuMsk); + RTK_API_UNLOCK(); + + return retVal; +} + + diff --git a/sources/uboot-be550/drivers/net/rtl8372/svlan.h b/sources/uboot-be550/drivers/net/rtl8372/svlan.h new file mode 100755 index 00000000..031e0114 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/svlan.h @@ -0,0 +1,582 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8373 switch high-level API + * + * Feature : The file includes SVLAN module high-layer API defination + * + */ + +#ifndef __RTK_API_SVLAN_H__ +#define __RTK_API_SVLAN_H__ + +typedef rtk_uint32 rtk_svlan_index_t; + +typedef struct rtk_svlan_memberCfg_s{ + rtk_uint32 svid; + rtk_portmask_t memberport; + rtk_portmask_t untagport; + rtk_uint32 fiden; + rtk_uint32 fid; + rtk_uint32 priority; + rtk_uint32 efiden; + rtk_uint32 efid; + rtk_uint32 chk_ivl_svl; + rtk_uint32 ivl_svl; +}rtk_svlan_memberCfg_t; + +typedef enum rtk_svlan_pri_ref_e +{ + REF_INTERNAL_PRI = 0, + REF_CTAG_PRI, + REF_RSV, + REF_PB_PRI, + REF_PRI_END +} rtk_svlan_pri_ref_t; + + +typedef rtk_uint32 rtk_svlan_tpid_t; + +typedef enum rtk_svlan_untag_action_e +{ + UNTAG_DROP = 0, + UNTAG_TRAP, + UNTAG_ASSIGN, + UNTAG_END +} rtk_svlan_untag_action_t; + +typedef enum rtk_svlan_unassign_action_e +{ + UNASSIGN_PBSVID = 0, + UNASSIGN_TRAP, + UNASSIGN_END +} rtk_svlan_unassign_action_t; + +typedef enum rtk_svlan_trapCpuMsk_e +{ + TRAP_TO_NONE = 0, + TRAP_TO_INT_CPU, + TRAP_TO_EXT_CPU, + TRAP_TO_BOTH_INT_EXT_CPU, + TRAP_TO_END +} rtk_svlan_trapCpuMsk_t; + +/* Function Name: + * rtk_svlan_init + * Description: + * Initialize SVLAN Configuration + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * Ether type of S-tag in 802.1ad is 0x88a8 and there are existed ether type 0x9100 and 0x9200 for Q-in-Q SLAN design. + * User can set mathced ether type as service provider supported protocol. + */ +extern rtk_api_ret_t rtk_svlan_init(void); + +/* Function Name: + * rtk_svlan_servicePort_add + * Description: + * Add one service port in the specified device + * Input: + * port - Port id. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * This API is setting which port is connected to provider switch. All frames receiving from this port must + * contain accept SVID in S-tag field. + */ +extern rtk_api_ret_t rtk_svlan_servicePort_add(rtk_port_t port); + +/* Function Name: + * rtk_svlan_servicePort_get + * Description: + * Get service ports in the specified device. + * Input: + * None + * Output: + * pSvlanPortmask - pointer buffer of svlan ports. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API is setting which port is connected to provider switch. All frames receiving from this port must + * contain accept SVID in S-tag field. + */ +extern rtk_api_ret_t rtk_svlan_servicePort_get(rtk_portmask_t *pSvlanPortmask); + +/* Function Name: + * rtk_svlan_servicePort_del + * Description: + * Delete one service port in the specified device + * Input: + * port - Port id. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * This API is removing SVLAN service port in the specified device. + */ +extern rtk_api_ret_t rtk_svlan_servicePort_del(rtk_port_t port); + +/* Function Name: + * rtk_svlan_tpidEntry_set + * Description: + * Configure accepted S-VLAN ether type. + * Input: + * svlanTpid - Ether type of S-tag frame parsing in uplink ports. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * Note: + * Ether type of S-tag in 802.1ad is 0x88a8 and there are existed ether type 0x9100 and 0x9200 for Q-in-Q SLAN design. + * User can set mathced ether type as service provider supported protocol. + */ +extern rtk_api_ret_t rtk_svlan_tpidEntry_set(rtk_uint32 svlanTpid); + +/* Function Name: + * rtk_svlan_tpidEntry_get + * Description: + * Get accepted S-VLAN ether type setting. + * Input: + * None + * Output: + * pSvlanTpid - Ether type of S-tag frame parsing in uplink ports. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * This API is setting which port is connected to provider switch. All frames receiving from this port must + * contain accept SVID in S-tag field. + */ +extern rtk_api_ret_t rtk_svlan_tpidEntry_get(rtk_uint32 *pSvlanTpid); + +/* Function Name: + * rtk_svlan_priorityRef_set + * Description: + * Set S-VLAN upstream priority reference setting. + * Input: + * ref - reference selection parameter. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * Note: + * The API can set the upstream SVLAN tag priority reference source. The related priority + * sources are as following: + * - REF_INTERNAL_PRI, + * - REF_CTAG_PRI, + * - REF_SVLAN_PRI, + * - REF_PB_PRI. + */ +extern rtk_api_ret_t rtk_svlan_priorityRef_set(rtk_svlan_pri_ref_t ref); + +/* Function Name: + * rtk_svlan_priorityRef_get + * Description: + * Get S-VLAN upstream priority reference setting. + * Input: + * None + * Output: + * pRef - reference selection parameter. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * The API can get the upstream SVLAN tag priority reference source. The related priority + * sources are as following: + * - REF_INTERNAL_PRI, + * - REF_CTAG_PRI, + * - REF_SVLAN_PRI, + * - REF_PB_PRI + */ +extern rtk_api_ret_t rtk_svlan_priorityRef_get(rtk_svlan_pri_ref_t *pRef); +#if 0 +/* Function Name: + * rtk_svlan_memberPortEntry_set + * Description: + * Configure system SVLAN member content + * Input: + * svid - SVLAN id + * psvlan_cfg - SVLAN member configuration + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_PORT_MASK - Invalid portmask. + * RT_ERR_SVLAN_TABLE_FULL - SVLAN configuration is full. + * Note: + * The API can set system 64 accepted s-tag frame format. Only 64 SVID S-tag frame will be accpeted + * to receiving from uplink ports. Other SVID S-tag frame or S-untagged frame will be droped by default setup. + * - rtk_svlan_memberCfg_t->svid is SVID of SVLAN member configuration. + * - rtk_svlan_memberCfg_t->memberport is member port mask of SVLAN member configuration. + * - rtk_svlan_memberCfg_t->fid is filtering database of SVLAN member configuration. + * - rtk_svlan_memberCfg_t->priority is priority of SVLAN member configuration. + */ +extern rtk_api_ret_t rtk_svlan_memberPortEntry_set(rtk_uint32 svid_idx, rtk_svlan_memberCfg_t *psvlan_cfg); + +/* Function Name: + * rtk_svlan_memberPortEntry_get + * Description: + * Get SVLAN member Configure. + * Input: + * svid - SVLAN id + * Output: + * pSvlan_cfg - SVLAN member configuration + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get system 64 accepted s-tag frame format. Only 64 SVID S-tag frame will be accpeted + * to receiving from uplink ports. Other SVID S-tag frame or S-untagged frame will be droped. + */ +extern rtk_api_ret_t rtk_svlan_memberPortEntry_get(rtk_uint32 svid_idx, rtk_svlan_memberCfg_t *pSvlan_cfg); + +/* Function Name: + * rtk_svlan_memberPortEntry_adv_set + * Description: + * Configure system SVLAN member by index + * Input: + * idx - Index (0 ~ 63) + * psvlan_cfg - SVLAN member configuration + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_PORT_MASK - Invalid portmask. + * RT_ERR_SVLAN_TABLE_FULL - SVLAN configuration is full. + * Note: + * The API can set system 64 accepted s-tag frame format by index. + * - rtk_svlan_memberCfg_t->svid is SVID of SVLAN member configuration. + * - rtk_svlan_memberCfg_t->memberport is member port mask of SVLAN member configuration. + * - rtk_svlan_memberCfg_t->fid is filtering database of SVLAN member configuration. + * - rtk_svlan_memberCfg_t->priority is priority of SVLAN member configuration. + */ +extern rtk_api_ret_t rtk_svlan_memberPortEntry_adv_set(rtk_uint32 idx, rtk_svlan_memberCfg_t *pSvlan_cfg); + +/* Function Name: + * rtk_svlan_memberPortEntry_adv_get + * Description: + * Get SVLAN member Configure by index. + * Input: + * idx - Index (0 ~ 63) + * Output: + * pSvlan_cfg - SVLAN member configuration + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get system 64 accepted s-tag frame format. Only 64 SVID S-tag frame will be accpeted + * to receiving from uplink ports. Other SVID S-tag frame or S-untagged frame will be droped. + */ +extern rtk_api_ret_t rtk_svlan_memberPortEntry_adv_get(rtk_uint32 idx, rtk_svlan_memberCfg_t *pSvlan_cfg); +#endif + +/* Function Name: + * rtk_svlan_defaultSvlan_set + * Description: + * Configure default egress SVLAN. + * Input: + * port - Source port + * svid - SVLAN id + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found. + * Note: + * The API can set port n S-tag format index while receiving frame from port n + * is transmit through uplink port with s-tag field + */ +extern rtk_api_ret_t rtk_svlan_defaultSvlan_set(rtk_port_t port, rtk_vlan_t svid); + +/* Function Name: + * rtk_svlan_defaultSvlan_get + * Description: + * Get the configure default egress SVLAN. + * Input: + * port - Source port + * Output: + * pSvid - SVLAN VID + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can get port n S-tag format index while receiving frame from port n + * is transmit through uplink port with s-tag field + */ +extern rtk_api_ret_t rtk_svlan_defaultSvlan_get(rtk_port_t port, rtk_vlan_t *pSvid); + +/* Function Name: + * rtk_svlan_c2s_add + * Description: + * Configure SVLAN C2S table + * Input: + * vid - VLAN ID + * srcPort - Ingress Port + * svid - SVLAN VID + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port ID. + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can set system C2S configuration. ASIC will check upstream's VID and assign related + * SVID to mathed packet. There are 128 SVLAN C2S configurations. + */ +extern rtk_api_ret_t rtk_svlan_c2s_add(rtk_vlan_t vid, rtk_port_t srcPort, rtk_vlan_t svid); + +/* Function Name: + * rtk_svlan_c2s_del + * Description: + * Delete one C2S entry + * Input: + * vid - VLAN ID + * srcPort - Ingress Port + * svid - SVLAN VID + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_VLAN_VID - Invalid VID parameter. + * RT_ERR_PORT_ID - Invalid port ID. + * RT_ERR_OUT_OF_RANGE - input out of range. + * Note: + * The API can delete system C2S configuration. There are 128 SVLAN C2S configurations. + */ +extern rtk_api_ret_t rtk_svlan_c2s_del(rtk_vlan_t vid, rtk_port_t srcPort); + +/* Function Name: + * rtk_svlan_c2s_get + * Description: + * Get configure SVLAN C2S table + * Input: + * vid - VLAN ID + * srcPort - Ingress Port + * Output: + * pSvid - SVLAN ID + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port ID. + * RT_ERR_OUT_OF_RANGE - input out of range. + * Note: + * The API can get system C2S configuration. There are 128 SVLAN C2S configurations. + */ +extern rtk_api_ret_t rtk_svlan_c2s_get(rtk_vlan_t vid, rtk_port_t srcPort, rtk_vlan_t *pSvid); + +/* Function Name: + * rtk_svlan_untag_action_set + * Description: + * Configure Action of downstream Un-Stag packet + * Input: + * action - Action for UnStag + * svid - The SVID assigned to UnStag packet + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found. + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can configure action of downstream Un-Stag packet. A SVID assigned + * to the un-stag is also supported by this API. The parameter of svid is + * only referenced when the action is set to UNTAG_ASSIGN + */ +extern rtk_api_ret_t rtk_svlan_untag_action_set(rtk_svlan_untag_action_t action, rtk_vlan_t svid); + +/* Function Name: + * rtk_svlan_untag_action_get + * Description: + * Get Action of downstream Un-Stag packet + * Input: + * None + * Output: + * pAction - Action for UnStag + * pSvid - The SVID assigned to UnStag packet + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. + * RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found. + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can Get action of downstream Un-Stag packet. A SVID assigned + * to the un-stag is also retrieved by this API. The parameter pSvid is + * only refernced when the action is UNTAG_ASSIGN + */ +extern rtk_api_ret_t rtk_svlan_untag_action_get(rtk_svlan_untag_action_t *pAction, rtk_vlan_t *pSvid); + +/* Function Name: + * rtk_svlan_trapPri_set + * Description: + * Set svlan trap priority + * Input: + * priority - priority for trap packets + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_QOS_INT_PRIORITY + * Note: + * None + */ +extern rtk_api_ret_t rtk_svlan_trapPri_set(rtk_pri_t priority); + +/* Function Name: + * rtk_svlan_trapPri_get + * Description: + * Get svlan trap priority + * Input: + * None + * Output: + * pPriority - priority for trap packets + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None + */ +extern rtk_api_ret_t rtk_svlan_trapPri_get(rtk_pri_t *pPriority); + +/* Function Name: + * rtk_svlan_trapCpumsk_set + * Description: + * Set svlan trap priority + * Input: + * cpuMsk - cpu mask for trap packets + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_QOS_INT_PRIORITY + * Note: + * None + */ +extern rtk_api_ret_t rtk_svlan_trapCpumsk_set(rtk_uint32 cpuMsk); + +/* Function Name: + * rtk_svlan_trapCpumsk_get + * Description: + * Get svlan trap cpu mask + * Input: + * None + * Output: + * pCpuMsk - cpu mask for trap packets + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None + */ +extern rtk_api_ret_t rtk_svlan_trapCpumsk_get(rtk_uint32 *pCpuMsk); + +/* Function Name: + * rtk_svlan_unassign_action_set + * Description: + * Configure Action of upstream without svid assign action + * Input: + * action - Action for Un-assign + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_OUT_OF_RANGE - input out of range. + * RT_ERR_INPUT - Invalid input parameters. + * Note: + * The API can configure action of upstream Un-assign svid packet. If action is not + * trap to CPU, the port-based SVID sure be assign as system need + */ +extern rtk_api_ret_t rtk_svlan_unassign_action_set(rtk_svlan_unassign_action_t action); + +/* Function Name: + * rtk_svlan_unassign_action_get + * Description: + * Get action of upstream without svid assignment + * Input: + * None + * Output: + * pAction - Action for Un-assign + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * Note: + * None + */ +extern rtk_api_ret_t rtk_svlan_unassign_action_get(rtk_svlan_unassign_action_t *pAction); + +#endif /* __RTK_API_SVLAN_H__ */ diff --git a/sources/uboot-be550/drivers/net/rtl8372/trunk.c b/sources/uboot-be550/drivers/net/rtl8372/trunk.c new file mode 100755 index 00000000..8c6276ce --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/trunk.c @@ -0,0 +1,448 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8367/RTL8367C + * Feature : Here is a list of all functions and variables in Trunk module. + * + */ + +#include +#include +#include +#include + +#include + +/* Function Name: + * rtk_trunk_port_set + * Description: + * Set trunking group available port mask + * Input: + * trk_gid - trunk group id + * pTrunk_member_portmask - Logic trunking member port mask + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_LA_TRUNK_ID - Invalid trunking group + * RT_ERR_PORT_MASK - Invalid portmask. + * Note: + * The API can set port trunking group port mask. Each port trunking group has max 4 ports. + * If enabled port mask has less than 2 ports available setting, then this trunking group function is disabled. + */ +rtk_api_ret_t rtk_trunk_port_set(rtk_trunk_group_t trk_gid, rtk_portmask_t *pTrunk_member_portmask) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->trunk_port_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->trunk_port_set(trk_gid, pTrunk_member_portmask); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_trunk_port_get + * Description: + * Get trunking group available port mask + * Input: + * trk_gid - trunk group id + * Output: + * pTrunk_member_portmask - Logic trunking member port mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_LA_TRUNK_ID - Invalid trunking group + * Note: + * The API can get 2 port trunking group. + */ +rtk_api_ret_t rtk_trunk_port_get(rtk_trunk_group_t trk_gid, rtk_portmask_t *pTrunk_member_portmask) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->trunk_port_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->trunk_port_get(trk_gid, pTrunk_member_portmask); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_trunk_distributionAlgorithm_set + * Description: + * Set port trunking hash select sources + * Input: + * trk_gid - trunk group id + * algo_bitmask - Bitmask of the distribution algorithm + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_LA_TRUNK_ID - Invalid trunking group + * RT_ERR_LA_HASHMASK - Hash algorithm selection error. + * RT_ERR_PORT_MASK - Invalid portmask. + * Note: + * The API can set port trunking hash algorithm sources. + * 7 bits mask for link aggregation group0 hash parameter selection {DIP, SIP, DMAC, SMAC, SPA} + * - 0b0000001: SPA + * - 0b0000010: SMAC + * - 0b0000100: DMAC + * - 0b0001000: SIP + * - 0b0010000: DIP + * - 0b0100000: TCP/UDP Source Port + * - 0b1000000: TCP/UDP Destination Port + * Example: + * - 0b0000011: SMAC & SPA + * - Note that it could be an arbitrary combination or independent set + */ +rtk_api_ret_t rtk_trunk_distributionAlgorithm_set(rtk_trunk_group_t trk_gid, rtk_uint32 algo_bitmask) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->trunk_distributionAlgorithm_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->trunk_distributionAlgorithm_set(trk_gid, algo_bitmask); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_trunk_distributionAlgorithm_get + * Description: + * Get port trunking hash select sources + * Input: + * trk_gid - trunk group id + * Output: + * pAlgo_bitmask - Bitmask of the distribution algorithm + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_LA_TRUNK_ID - Invalid trunking group + * Note: + * The API can get port trunking hash algorithm sources. + */ +rtk_api_ret_t rtk_trunk_distributionAlgorithm_get(rtk_trunk_group_t trk_gid, rtk_uint32 *pAlgo_bitmask) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->trunk_distributionAlgorithm_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->trunk_distributionAlgorithm_get(trk_gid, pAlgo_bitmask); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_trunk_trafficSeparate_set + * Description: + * Set the traffic separation setting of a trunk group from the specified device. + * Input: + * trk_gid - trunk group id + * separateType - traffic separation setting + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_LA_TRUNK_ID - invalid trunk ID + * RT_ERR_LA_HASHMASK - invalid hash mask + * Note: + * SEPARATE_NONE: disable traffic separation + * SEPARATE_FLOOD: trunk MSB link up port is dedicated to TX flooding (L2 lookup miss) traffic + */ +rtk_api_ret_t rtk_trunk_trafficSeparate_set(rtk_trunk_group_t trk_gid, rtk_trunk_separateType_t separateType) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->trunk_trafficSeparate_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->trunk_trafficSeparate_set(trk_gid, separateType); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_trunk_trafficSeparate_get + * Description: + * Get the traffic separation setting of a trunk group from the specified device. + * Input: + * trk_gid - trunk group id + * Output: + * pSeparateType - pointer separated traffic type + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_LA_TRUNK_ID - invalid trunk ID + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * SEPARATE_NONE: disable traffic separation + * SEPARATE_FLOOD: trunk MSB link up port is dedicated to TX flooding (L2 lookup miss) traffic + */ +rtk_api_ret_t rtk_trunk_trafficSeparate_get(rtk_trunk_group_t trk_gid, rtk_trunk_separateType_t *pSeparateType) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->trunk_trafficSeparate_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->trunk_trafficSeparate_get(trk_gid, pSeparateType); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_trunk_mode_set + * Description: + * Set the trunk mode to the specified device. + * Input: + * mode - trunk mode + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT - invalid input parameter + * Note: + * The enum of the trunk mode as following + * - TRUNK_MODE_NORMAL + * - TRUNK_MODE_DUMB + */ +rtk_api_ret_t rtk_trunk_mode_set(rtk_trunk_mode_t mode) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->trunk_mode_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->trunk_mode_set(mode); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_trunk_mode_get + * Description: + * Get the trunk mode from the specified device. + * Input: + * None + * Output: + * pMode - pointer buffer of trunk mode + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * The enum of the trunk mode as following + * - TRUNK_MODE_NORMAL + * - TRUNK_MODE_DUMB + */ +rtk_api_ret_t rtk_trunk_mode_get(rtk_trunk_mode_t *pMode) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->trunk_mode_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->trunk_mode_get(pMode); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_trunk_trafficPause_set + * Description: + * Set the traffic pause setting of a trunk group. + * Input: + * trk_gid - trunk group id + * enable - traffic pause state + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_LA_TRUNK_ID - invalid trunk ID + * Note: + * None. + */ +rtk_api_ret_t rtk_trunk_trafficPause_set(rtk_trunk_group_t trk_gid, rtk_enable_t enable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->trunk_trafficPause_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->trunk_trafficPause_set(trk_gid, enable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_trunk_trafficPause_get + * Description: + * Get the traffic pause setting of a trunk group. + * Input: + * trk_gid - trunk group id + * Output: + * pEnable - pointer of traffic pause state. + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_LA_TRUNK_ID - invalid trunk ID + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None. + */ +rtk_api_ret_t rtk_trunk_trafficPause_get(rtk_trunk_group_t trk_gid, rtk_enable_t *pEnable) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->trunk_trafficPause_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->trunk_trafficPause_get(trk_gid, pEnable); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_trunk_hashMappingTable_set + * Description: + * Set hash value to port array in the trunk group id from the specified device. + * Input: + * trk_gid - trunk group id + * pHash2Port_array - ports associate with the hash value + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_LA_TRUNK_ID - invalid trunk ID + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * RT_ERR_LA_TRUNK_NOT_EXIST - the trunk doesn't exist + * RT_ERR_LA_NOT_MEMBER_PORT - the port is not a member port of the trunk + * RT_ERR_LA_CPUPORT - CPU port can not be aggregated port + * Note: + * Trunk group 0 & 1 shares the same hash mapping table. + * Trunk group 2 uses a independent table. + */ +rtk_api_ret_t rtk_trunk_hashMappingTable_set(rtk_trunk_group_t trk_gid, rtk_trunk_hashVal2Port_t *pHash2Port_array) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->trunk_hashMappingTable_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->trunk_hashMappingTable_set(trk_gid, pHash2Port_array); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_trunk_hashMappingTable_get + * Description: + * Get hash value to port array in the trunk group id from the specified device. + * Input: + * trk_gid - trunk group id + * Output: + * pHash2Port_array - pointer buffer of ports associate with the hash value + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_LA_TRUNK_ID - invalid trunk ID + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * Trunk group 0 & 1 shares the same hash mapping table. + * Trunk group 2 uses a independent table. + */ +rtk_api_ret_t rtk_trunk_hashMappingTable_get(rtk_trunk_group_t trk_gid, rtk_trunk_hashVal2Port_t *pHash2Port_array) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->trunk_hashMappingTable_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->trunk_hashMappingTable_get(trk_gid, pHash2Port_array); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_trunk_portQueueEmpty_get + * Description: + * Get the port mask which all queues are empty. + * Input: + * None. + * Output: + * pEmpty_portmask - pointer empty port mask + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None. + */ +rtk_api_ret_t rtk_trunk_portQueueEmpty_get(rtk_portmask_t *pEmpty_portmask) +{ + rtk_api_ret_t retVal; + + if (NULL == RT_MAPPER->trunk_portQueueEmpty_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->trunk_portQueueEmpty_get(pEmpty_portmask); + RTK_API_UNLOCK(); + + return retVal; +} + + diff --git a/sources/uboot-be550/drivers/net/rtl8372/trunk.h b/sources/uboot-be550/drivers/net/rtl8372/trunk.h new file mode 100755 index 00000000..680a5701 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/trunk.h @@ -0,0 +1,330 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8367/RTL8367C switch high-level API + * + * Feature : The file includes Trunk module high-layer TRUNK defination + * + */ + +#ifndef __RTK_API_TRUNK_H__ +#define __RTK_API_TRUNK_H__ + +/* + * Data Type Declaration + */ +#define RTK_TRUNK_DPORT_HASH_MASK 0x40 +#define RTK_TRUNK_SPORT_HASH_MASK 0x20 +#define RTK_TRUNK_DIP_HASH_MASK 0x10 +#define RTK_TRUNK_SIP_HASH_MASK 0x8 +#define RTK_TRUNK_DMAC_HASH_MASK 0x4 +#define RTK_TRUNK_SMAC_HASH_MASK 0x2 +#define RTK_TRUNK_SPA_HASH_MASK 0x1 + + +#define RTK_MAX_NUM_OF_TRUNK_HASH_VAL 16 + +typedef struct rtk_trunk_hashVal2Port_s +{ + rtk_uint8 value[RTK_MAX_NUM_OF_TRUNK_HASH_VAL]; +} rtk_trunk_hashVal2Port_t; + +typedef enum rtk_trunk_group_e +{ + TRUNK_GROUP0 = 0, + TRUNK_GROUP1, + TRUNK_GROUP2, + TRUNK_GROUP3, + TRUNK_GROUP_END +} rtk_trunk_group_t; + +typedef enum rtk_trunk_separateType_e +{ + SEPARATE_NONE = 0, + SEPARATE_FLOOD, + SEPARATE_END + +} rtk_trunk_separateType_t; + +typedef enum rtk_trunk_mode_e +{ + TRUNK_MODE_NORMAL = 0, + TRUNK_MODE_DUMB, + TRUNK_MODE_END +} rtk_trunk_mode_t; + +/* Function Name: + * rtk_trunk_port_set + * Description: + * Set trunking group available port mask + * Input: + * trk_gid - trunk group id + * pTrunk_member_portmask - Logic trunking member port mask + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_LA_TRUNK_ID - Invalid trunking group + * RT_ERR_PORT_MASK - Invalid portmask. + * Note: + * The API can set port trunking group port mask. Each port trunking group has max 4 ports. + * If enabled port mask has less than 2 ports available setting, then this trunking group function is disabled. + */ +extern rtk_api_ret_t rtk_trunk_port_set(rtk_trunk_group_t trk_gid, rtk_portmask_t *pTrunk_member_portmask); + +/* Function Name: + * rtk_trunk_port_get + * Description: + * Get trunking group available port mask + * Input: + * trk_gid - trunk group id + * Output: + * pTrunk_member_portmask - Logic trunking member port mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_LA_TRUNK_ID - Invalid trunking group + * Note: + * The API can get 2 port trunking group. + */ +extern rtk_api_ret_t rtk_trunk_port_get(rtk_trunk_group_t trk_gid, rtk_portmask_t *pTrunk_member_portmask); + +/* Function Name: + * rtk_trunk_distributionAlgorithm_set + * Description: + * Set port trunking hash select sources + * Input: + * trk_gid - trunk group id + * algo_bitmask - Bitmask of the distribution algorithm + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_LA_TRUNK_ID - Invalid trunking group + * RT_ERR_LA_HASHMASK - Hash algorithm selection error. + * RT_ERR_PORT_MASK - Invalid portmask. + * Note: + * The API can set port trunking hash algorithm sources. + * 7 bits mask for link aggregation group0 hash parameter selection {DIP, SIP, DMAC, SMAC, SPA} + * - 0b0000001: SPA + * - 0b0000010: SMAC + * - 0b0000100: DMAC + * - 0b0001000: SIP + * - 0b0010000: DIP + * - 0b0100000: TCP/UDP Source Port + * - 0b1000000: TCP/UDP Destination Port + * Example: + * - 0b0000011: SMAC & SPA + * - Note that it could be an arbitrary combination or independent set + */ +extern rtk_api_ret_t rtk_trunk_distributionAlgorithm_set(rtk_trunk_group_t trk_gid, rtk_uint32 algo_bitmask); + +/* Function Name: + * rtk_trunk_distributionAlgorithm_get + * Description: + * Get port trunking hash select sources + * Input: + * trk_gid - trunk group id + * Output: + * pAlgo_bitmask - Bitmask of the distribution algorithm + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_LA_TRUNK_ID - Invalid trunking group + * Note: + * The API can get port trunking hash algorithm sources. + */ +extern rtk_api_ret_t rtk_trunk_distributionAlgorithm_get(rtk_trunk_group_t trk_gid, rtk_uint32 *pAlgo_bitmask); + +/* Function Name: + * rtk_trunk_trafficSeparate_set + * Description: + * Set the traffic separation setting of a trunk group from the specified device. + * Input: + * trk_gid - trunk group id + * separateType - traffic separation setting + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_LA_TRUNK_ID - invalid trunk ID + * RT_ERR_LA_HASHMASK - invalid hash mask + * Note: + * SEPARATE_NONE: disable traffic separation + * SEPARATE_FLOOD: trunk MSB link up port is dedicated to TX flooding (L2 lookup miss) traffic + */ +extern rtk_api_ret_t rtk_trunk_trafficSeparate_set(rtk_trunk_group_t trk_gid, rtk_trunk_separateType_t separateType); + +/* Function Name: + * rtk_trunk_trafficSeparate_get + * Description: + * Get the traffic separation setting of a trunk group from the specified device. + * Input: + * trk_gid - trunk group id + * Output: + * pSeparateType - pointer separated traffic type + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_LA_TRUNK_ID - invalid trunk ID + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * SEPARATE_NONE: disable traffic separation + * SEPARATE_FLOOD: trunk MSB link up port is dedicated to TX flooding (L2 lookup miss) traffic + */ +extern rtk_api_ret_t rtk_trunk_trafficSeparate_get(rtk_trunk_group_t trk_gid, rtk_trunk_separateType_t *pSeparateType); + + +/* Function Name: + * rtk_trunk_mode_set + * Description: + * Set the trunk mode to the specified device. + * Input: + * mode - trunk mode + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_INPUT - invalid input parameter + * Note: + * The enum of the trunk mode as following + * - TRUNK_MODE_NORMAL + * - TRUNK_MODE_DUMB + */ +extern rtk_api_ret_t rtk_trunk_mode_set(rtk_trunk_mode_t mode); + +/* Function Name: + * rtk_trunk_mode_get + * Description: + * Get the trunk mode from the specified device. + * Input: + * None + * Output: + * pMode - pointer buffer of trunk mode + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * The enum of the trunk mode as following + * - TRUNK_MODE_NORMAL + * - TRUNK_MODE_DUMB + */ +extern rtk_api_ret_t rtk_trunk_mode_get(rtk_trunk_mode_t *pMode); + +/* Function Name: + * rtk_trunk_trafficPause_set + * Description: + * Set the traffic pause setting of a trunk group. + * Input: + * trk_gid - trunk group id + * enable - traffic pause state + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_LA_TRUNK_ID - invalid trunk ID + * Note: + * None. + */ +extern rtk_api_ret_t rtk_trunk_trafficPause_set(rtk_trunk_group_t trk_gid, rtk_enable_t enable); + +/* Function Name: + * rtk_trunk_trafficPause_get + * Description: + * Get the traffic pause setting of a trunk group. + * Input: + * trk_gid - trunk group id + * Output: + * pEnable - pointer of traffic pause state. + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_LA_TRUNK_ID - invalid trunk ID + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None. + */ +extern rtk_api_ret_t rtk_trunk_trafficPause_get(rtk_trunk_group_t trk_gid, rtk_enable_t *pEnable); + +/* Function Name: + * rtk_trunk_hashMappingTable_set + * Description: + * Set hash value to port array in the trunk group id from the specified device. + * Input: + * trk_gid - trunk group id + * pHash2Port_array - ports associate with the hash value + * Output: + * None + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_LA_TRUNK_ID - invalid trunk ID + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * RT_ERR_LA_TRUNK_NOT_EXIST - the trunk doesn't exist + * RT_ERR_LA_NOT_MEMBER_PORT - the port is not a member port of the trunk + * RT_ERR_LA_CPUPORT - CPU port can not be aggregated port + * Note: + * Trunk group 0 & 1 shares the same hash mapping table. + * Trunk group 2 uses a independent table. + */ +extern rtk_api_ret_t rtk_trunk_hashMappingTable_set(rtk_trunk_group_t trk_gid, rtk_trunk_hashVal2Port_t *pHash2Port_array); + +/* Function Name: + * rtk_trunk_hashMappingTable_get + * Description: + * Get hash value to port array in the trunk group id from the specified device. + * Input: + * trk_gid - trunk group id + * Output: + * pHash2Port_array - pointer buffer of ports associate with the hash value + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_UNIT_ID - invalid unit id + * RT_ERR_LA_TRUNK_ID - invalid trunk ID + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * Trunk group 0 & 1 shares the same hash mapping table. + * Trunk group 2 uses a independent table. + */ +extern rtk_api_ret_t rtk_trunk_hashMappingTable_get(rtk_trunk_group_t trk_gid, rtk_trunk_hashVal2Port_t *pHash2Port_array); + +/* Function Name: + * rtk_trunk_portQueueEmpty_get + * Description: + * Get the port mask which all queues are empty. + * Input: + * None. + * Output: + * pEmpty_portmask - pointer empty port mask + * Return: + * RT_ERR_OK + * RT_ERR_FAILED + * RT_ERR_NULL_POINTER - input parameter may be null pointer + * Note: + * None. + */ +extern rtk_api_ret_t rtk_trunk_portQueueEmpty_get(rtk_portmask_t *pEmpty_portmask); + +#endif /* __RTK_API_TRUNK_H__ */ diff --git a/sources/uboot-be550/drivers/net/rtl8372/vlan.c b/sources/uboot-be550/drivers/net/rtl8372/vlan.c new file mode 100755 index 00000000..f4ccda76 --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/vlan.c @@ -0,0 +1,1022 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * $Revision$ + * $Date$ + * + * Purpose : RTK switch high-level API for RTL8373 + * Feature : Here is a list of all functions and variables in VLAN module. + * + + */ + + +#include +#include +#include +//#include +#include + +#include + +/* Function Name: + * rtk_vlan_init + * Description: + * Initialize VLAN. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * VLAN is disabled by default. User has to call this API to enable VLAN before + * using it. And It will set a default VLAN(vid 1) including all ports and set + * all ports PVID to the default VLAN. + */ +rtk_api_ret_t rtk_vlan_init(void) +{ + rtk_api_ret_t retVal = 0; + + if (NULL == RT_MAPPER->vlan_init) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->vlan_init(); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_vlan_set + * Description: + * Set a VLAN entry. + * Input: + * vid - VLAN ID to configure. + * pVlanCfg - VLAN Configuration + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_L2_FID - Invalid FID. + * RT_ERR_VLAN_PORT_MBR_EXIST - Invalid member port mask. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * Note: + * + */ +rtk_api_ret_t rtk_vlan_set(rtk_vlan_t vid, rtk_vlan_entry_t *pVlanCfg) +{ + rtk_api_ret_t retVal = 0; + + if (NULL == RT_MAPPER->vlan_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->vlan_set(vid, pVlanCfg); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_vlan_get + * Description: + * Get a VLAN entry. + * Input: + * vid - VLAN ID to configure. + * Output: + * pVlanCfg - VLAN Configuration + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * Note: + * + */ +rtk_api_ret_t rtk_vlan_get(rtk_vlan_t vid, rtk_vlan_entry_t *pVlanCfg) +{ + rtk_api_ret_t retVal = 0; + + if (NULL == RT_MAPPER->vlan_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->vlan_get(vid, pVlanCfg); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_vlan_egrFilterEnable_set + * Description: + * Set VLAN egress filter. + * Input: + * egrFilter - Egress filtering + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid input parameters. + * Note: + * + */ +rtk_api_ret_t rtk_vlan_egrFilterEnable_set(rtk_enable_t egrFilter) +{ + rtk_api_ret_t retVal = 0; + + if (NULL == RT_MAPPER->vlan_egrFilterEnable_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->vlan_egrFilterEnable_set(egrFilter); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_vlan_egrFilterEnable_get + * Description: + * Get VLAN egress filter. + * Input: + * pEgrFilter - Egress filtering + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - NULL Pointer. + * Note: + * + */ +rtk_api_ret_t rtk_vlan_egrFilterEnable_get(rtk_enable_t *pEgrFilter) +{ + rtk_api_ret_t retVal = 0; + + if (NULL == RT_MAPPER->vlan_egrFilterEnable_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->vlan_egrFilterEnable_get(pEgrFilter); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_vlan_portPvid_set + * Description: + * Set port to specified VLAN ID(PVID). + * Input: + * port - Port id. + * pvid - Specified VLAN ID. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_VLAN_PRIORITY - Invalid priority. + * RT_ERR_VLAN_ENTRY_NOT_FOUND - VLAN entry not found. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * Note: + * The API is used for Port-based VLAN. The untagged frame received from the + * port will be classified to the specified VLAN and assigned to the specified priority. + */ +rtk_api_ret_t rtk_vlan_portPvid_set(rtk_port_t port, rtk_vlan_t pvid) +{ + rtk_api_ret_t retVal = 0; + + if (NULL == RT_MAPPER->vlan_portPvid_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->vlan_portPvid_set(port, pvid); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_vlan_portPvid_get + * Description: + * Get VLAN ID(PVID) on specified port. + * Input: + * port - Port id. + * Output: + * pPvid - Specified VLAN ID. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get the PVID and 802.1p priority for the PVID of Port-based VLAN. + */ +rtk_api_ret_t rtk_vlan_portPvid_get(rtk_port_t port, rtk_vlan_t *pPvid) +{ + rtk_api_ret_t retVal = 0; + + if (NULL == RT_MAPPER->vlan_portPvid_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->vlan_portPvid_get(port, pPvid); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_vlan_portIgrFilterEnable_set + * Description: + * Set VLAN ingress for each port. + * Input: + * port - Port id. + * igrFilter - VLAN ingress function enable status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * RT_ERR_ENABLE - Invalid enable input + * Note: + * The status of vlan ingress filter is as following: + * - DISABLED + * - ENABLED + * While VLAN function is enabled, ASIC will decide VLAN ID for each received frame and get belonged member + * ports from VLAN table. If received port is not belonged to VLAN member ports, ASIC will drop received frame if VLAN ingress function is enabled. + */ +rtk_api_ret_t rtk_vlan_portIgrFilterEnable_set(rtk_port_t port, rtk_enable_t igrFilter) +{ + rtk_api_ret_t retVal = 0; + + if (NULL == RT_MAPPER->vlan_portIgrFilterEnable_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->vlan_portIgrFilterEnable_set(port, igrFilter); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_vlan_portIgrFilterEnable_get + * Description: + * Get VLAN Ingress Filter + * Input: + * port - Port id. + * Output: + * pIgFilter - VLAN ingress function enable status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can Get the VLAN ingress filter status. + * The status of vlan ingress filter is as following: + * - DISABLED + * - ENABLED + */ +rtk_api_ret_t rtk_vlan_portIgrFilterEnable_get(rtk_port_t port, rtk_enable_t *pIgFilter) +{ + rtk_api_ret_t retVal = 0; + + if (NULL == RT_MAPPER->vlan_portIgrFilterEnable_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->vlan_portIgrFilterEnable_get(port, pIgFilter); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_vlan_portAcceptFrameType_set + * Description: + * Set VLAN accept_frame_type + * Input: + * port - Port id. + * acceptFrameType - accept frame type + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_VLAN_ACCEPT_FRAME_TYPE - Invalid frame type. + * Note: + * The API is used for checking 802.1Q tagged frames. + * The accept frame type as following: + * - ACCEPT_FRAME_TYPE_ALL + * - ACCEPT_FRAME_TYPE_TAG_ONLY + * - ACCEPT_FRAME_TYPE_UNTAG_ONLY + */ +rtk_api_ret_t rtk_vlan_portAcceptFrameType_set(rtk_port_t port, rtk_vlan_acceptFrameType_t acceptFrameType) +{ + rtk_api_ret_t retVal = 0; + + if (NULL == RT_MAPPER->vlan_portAcceptFrameType_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->vlan_portAcceptFrameType_set(port, acceptFrameType); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_vlan_portAcceptFrameType_get + * Description: + * Get VLAN accept_frame_type + * Input: + * port - Port id. + * Output: + * pAcceptFrameType - accept frame type + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can Get the VLAN ingress filter. + * The accept frame type as following: + * - ACCEPT_FRAME_TYPE_ALL + * - ACCEPT_FRAME_TYPE_TAG_ONLY + * - ACCEPT_FRAME_TYPE_UNTAG_ONLY + */ +rtk_api_ret_t rtk_vlan_portAcceptFrameType_get(rtk_port_t port, rtk_vlan_acceptFrameType_t *pAcceptFrameType) +{ + rtk_api_ret_t retVal = 0; + + if (NULL == RT_MAPPER->vlan_portAcceptFrameType_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->vlan_portAcceptFrameType_get(port, pAcceptFrameType); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_vlan_tagMode_set + * Description: + * Set CVLAN egress tag mode + * Input: + * port - Port id. + * tagMode - The egress tag mode. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * The API can set Egress tag mode. There are 4 mode for egress tag: + * - VLAN_EGRESS_TAG_MODE_ORIGINAL, + * - VLAN_EGRESS_TAG_MODE_KEEP_FORMAT, + * - VLAN_EGRESS_TAG_MODE_PRI. + * - VLAN_EGRESS_TAG_MODE_REAL_KEEP, + */ +rtk_api_ret_t rtk_vlan_tagMode_set(rtk_port_t port, rtk_vlan_egressTagMode_t tagMode) +{ + rtk_api_ret_t retVal = 0; + + if (NULL == RT_MAPPER->vlan_tagMode_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->vlan_tagMode_set(port, tagMode); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_vlan_tagMode_get + * Description: + * Get CVLAN egress tag mode + * Input: + * port - Port id. + * Output: + * pTagMode - The egress tag mode. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get Egress tag mode. There are 4 mode for egress tag: + * - VLAN_EGRESS_TAG_MODE_ORIGINAL, + * - VLAN_EGRESS_TAG_MODE_KEEP_FORMAT, + * - VLAN_EGRESS_TAG_MODE_PRI. + * - VLAN_EGRESS_TAG_MODE_REAL_KEEP, + */ +rtk_api_ret_t rtk_vlan_tagMode_get(rtk_port_t port, rtk_vlan_egressTagMode_t *pTagMode) +{ + rtk_api_ret_t retVal = 0; + + if (NULL == RT_MAPPER->vlan_tagMode_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->vlan_tagMode_get(port, pTagMode); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_vlan_transparent_set + * Description: + * Set VLAN transparent mode + * Input: + * egrPort - Egress Port id. + * pIgrPmsk - Ingress Port Mask. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * None. + */ +rtk_api_ret_t rtk_vlan_transparent_set(rtk_port_t egrPort, rtk_portmask_t *pIgrPmsk) +{ + rtk_api_ret_t retVal = 0; + + if (NULL == RT_MAPPER->vlan_transparent_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->vlan_transparent_set(egrPort, pIgrPmsk); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_vlan_transparent_get + * Description: + * Get VLAN transparent mode + * Input: + * egrPort - Egress Port id. + * Output: + * pIgrPmsk - Ingress Port Mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * None. + */ +rtk_api_ret_t rtk_vlan_transparent_get(rtk_port_t egrPort, rtk_portmask_t *pIgrPmsk) +{ + rtk_api_ret_t retVal = 0; + + if (NULL == RT_MAPPER->vlan_transparent_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->vlan_transparent_get(egrPort, pIgrPmsk); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_vlan_keep_set + * Description: + * Set VLAN egress keep mode + * Input: + * egrPort - Egress Port id. + * pIgrPmsk - Ingress Port Mask. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * None. + */ +rtk_api_ret_t rtk_vlan_keep_set(rtk_port_t egrPort, rtk_portmask_t *pIgrPmsk) +{ + rtk_api_ret_t retVal = 0; + + if (NULL == RT_MAPPER->vlan_keep_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->vlan_keep_set(egrPort, pIgrPmsk); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_vlan_keep_get + * Description: + * Get VLAN egress keep mode + * Input: + * egrPort - Egress Port id. + * Output: + * pIgrPmsk - Ingress Port Mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * None. + */ +rtk_api_ret_t rtk_vlan_keep_get(rtk_port_t egrPort, rtk_portmask_t *pIgrPmsk) +{ + rtk_api_ret_t retVal = 0; + + if (NULL == RT_MAPPER->vlan_keep_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->vlan_keep_get(egrPort, pIgrPmsk); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_vlan_stg_set + * Description: + * Set spanning tree group instance of the vlan to the specified device + * Input: + * vid - Specified VLAN ID. + * stg - spanning tree group instance. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_MSTI - Invalid msti parameter + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * Note: + * The API can set spanning tree group instance of the vlan to the specified device. + */ +rtk_api_ret_t rtk_vlan_stg_set(rtk_vlan_t vid, rtk_stp_msti_id_t stg) +{ + rtk_api_ret_t retVal = 0; + + if (NULL == RT_MAPPER->vlan_stg_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->vlan_stg_set(vid, stg); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_vlan_stg_get + * Description: + * Get spanning tree group instance of the vlan to the specified device + * Input: + * vid - Specified VLAN ID. + * Output: + * pStg - spanning tree group instance. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * Note: + * The API can get spanning tree group instance of the vlan to the specified device. + */ +rtk_api_ret_t rtk_vlan_stg_get(rtk_vlan_t vid, rtk_stp_msti_id_t *pStg) +{ + rtk_api_ret_t retVal = 0; + + if (NULL == RT_MAPPER->vlan_stg_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->vlan_stg_get(vid, pStg); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_vlan_portFid_set + * Description: + * Set port-based filtering database + * Input: + * port - Port id. + * enable - ebable port-based FID + * fid - Specified filtering database. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_FID - Invalid fid. + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API can set port-based filtering database. If the function is enabled, all input + * packets will be assigned to the port-based fid regardless vlan tag. + */ +rtk_api_ret_t rtk_vlan_portFid_set(rtk_port_t port, rtk_enable_t enable, rtk_fid_t fid) +{ + rtk_api_ret_t retVal = 0; + + if (NULL == RT_MAPPER->vlan_portFid_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->vlan_portFid_set(port, enable, fid); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_vlan_portFid_get + * Description: + * Get port-based filtering database + * Input: + * port - Port id. + * Output: + * pEnable - ebable port-based FID + * pFid - Specified filtering database. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API can get port-based filtering database status. If the function is enabled, all input + * packets will be assigned to the port-based fid regardless vlan tag. + */ +rtk_api_ret_t rtk_vlan_portFid_get(rtk_port_t port, rtk_enable_t *pEnable, rtk_fid_t *pFid) +{ + rtk_api_ret_t retVal = 0; + + if (NULL == RT_MAPPER->vlan_portFid_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->vlan_portFid_get(port, pEnable, pFid); + RTK_API_UNLOCK(); + + return retVal; +} + +#if 0 +/* Function Name: + + * rtk_stp_mstpState_set + * Description: + * Configure spanning tree state per each port. + * Input: + * port - Port id + * msti - Multiple spanning tree instance. + * stpState - Spanning tree state for msti + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_MSTI - Invalid msti parameter. + * RT_ERR_MSTP_STATE - Invalid STP state. + * Note: + * System supports per-port multiple spanning tree state for each msti. + * There are four states supported by ASIC. + * - STP_STATE_DISABLED + * - STP_STATE_BLOCKING + * - STP_STATE_LEARNING + * - STP_STATE_FORWARDING + */ +rtk_api_ret_t rtk_stp_mstpState_set(rtk_stp_msti_id_t msti, rtk_port_t port, rtk_stp_state_t stpState) +{ + rtk_api_ret_t retVal = 0; + + if (NULL == RT_MAPPER->stp_mstpState_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->stp_mstpState_set(msti, port, stpState); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_stp_mstpState_get + * Description: + * Get spanning tree state per each port. + * Input: + * port - Port id. + * msti - Multiple spanning tree instance. + * Output: + * pStpState - Spanning tree state for msti + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_MSTI - Invalid msti parameter. + * Note: + * System supports per-port multiple spanning tree state for each msti. + * There are four states supported by ASIC. + * - STP_STATE_DISABLED + * - STP_STATE_BLOCKING + * - STP_STATE_LEARNING + * - STP_STATE_FORWARDING + */ +rtk_api_ret_t rtk_stp_mstpState_get(rtk_stp_msti_id_t msti, rtk_port_t port, rtk_stp_state_t *pStpState) +{ + rtk_api_ret_t retVal = 0; + + if (NULL == RT_MAPPER->stp_mstpState_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->stp_mstpState_get(msti, port, pStpState); + RTK_API_UNLOCK(); + + return retVal; +} + +#endif + +/* Function Name: + + * rtk_vlan_reservedVidAction_set + * Description: + * Set Action of VLAN ID = 0 & 4095 tagged packet + * Input: + * actionVid0 - Action for VID 0. + * actionVid4095 - Action for VID 4095. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + * + */ +rtk_api_ret_t rtk_vlan_reservedVidAction_set(rtk_vlan_resVidAction_t actionVid0, rtk_vlan_resVidAction_t actionVid4095) +{ + rtk_api_ret_t retVal = 0; + + if (NULL == RT_MAPPER->vlan_reservedVidAction_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->vlan_reservedVidAction_set(actionVid0, actionVid4095); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_vlan_reservedVidAction_get + * Description: + * Get Action of VLAN ID = 0 & 4095 tagged packet + * Input: + * pActionVid0 - Action for VID 0. + * pActionVid4095 - Action for VID 4095. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - NULL Pointer + * Note: + * + */ +rtk_api_ret_t rtk_vlan_reservedVidAction_get(rtk_vlan_resVidAction_t *pActionVid0, rtk_vlan_resVidAction_t *pActionVid4095) +{ + rtk_api_ret_t retVal = 0; + + if (NULL == RT_MAPPER->vlan_reservedVidAction_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->vlan_reservedVidAction_get(pActionVid0, pActionVid4095); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_vlan_realKeepRemarkEnable_set + * Description: + * Set Real keep 1p remarking feature + * Input: + * enabled - State of 1p remarking at real keep packet + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + * + */ +rtk_api_ret_t rtk_vlan_realKeepRemarkEnable_set(rtk_enable_t enabled) +{ + rtk_api_ret_t retVal = 0; + + if (NULL == RT_MAPPER->vlan_realKeepRemarkEnable_set) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->vlan_realKeepRemarkEnable_set(enabled); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_vlan_realKeepRemarkEnable_get + * Description: + * Get Real keep 1p remarking feature + * Input: + * None. + * Output: + * pEnabled - State of 1p remarking at real keep packet + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + * + */ +rtk_api_ret_t rtk_vlan_realKeepRemarkEnable_get(rtk_enable_t *pEnabled) +{ + rtk_api_ret_t retVal = 0; + + if (NULL == RT_MAPPER->vlan_realKeepRemarkEnable_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->vlan_realKeepRemarkEnable_get(pEnabled); + RTK_API_UNLOCK(); + + return retVal; +} + +/******************************************************************************* +* Function Name: rtk_vlan_disL2Learn_set +* +* Description: +* config a L2 disable learning entry which based on vlan id +*Input: +* index: entry index +* pDisL2LearnCfg: L2 disable learning database +*Output: +* None +*Return: +* RT_ERR_OK - OK +* RT_ERR_FAILED - Failed +* RT_ERR_ENTRY_INDEX - error entry +* RT_ERR_ENABLE - error action +* RT_ERR_NULL_POINTER - NULL Pointer +* RT_ERR_VLAN_VID - Invalid VID parameter. + +*Note: None +*******************************************************************************/ +rtk_api_ret_t rtk_vlan_disL2Learn_set(rtk_vlan_disL2_learn_t *pDisL2LearnCfg) +{ + rtk_api_ret_t retVal = 0; + + if (NULL == RT_MAPPER->vlan_disL2Learn_entry_set) + return RT_ERR_DRIVER_NOT_FOUND; + RTK_API_LOCK(); + retVal = RT_MAPPER->vlan_disL2Learn_entry_set(pDisL2LearnCfg); + RTK_API_UNLOCK(); + + return retVal; + +} +/******************************************************************************* +* Function Name: rtk_vlan_disL2Learn_get +* +* Description: +* get a L2 disable learning entry which based on vlan id +*Input: +* index: entry index +* pDisL2LearnCfg: L2 disable learning database +*Output: +* None +*Return: +* RT_ERR_OK - OK +* RT_ERR_FAILED - Failed +* RT_ERR_ENTRY_INDEX - error entry +* RT_ERR_ENABLE - error action +* RT_ERR_NULL_POINTER - NULL Pointer +* RT_ERR_VLAN_VID - Invalid VID parameter. + +*Note: None +*******************************************************************************/ +rtk_api_ret_t rtk_vlan_disL2Learn_get(rtk_uint32 index, rtk_vlan_disL2_learn_t *pDisL2LearnCfg) +{ + rtk_api_ret_t retVal = 0; + + if (NULL == RT_MAPPER->vlan_disL2Learn_entry_get) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->vlan_disL2Learn_entry_get(index, pDisL2LearnCfg); + RTK_API_UNLOCK(); + + return retVal; +} + +/* Function Name: + * rtk_vlan_reset + * Description: + * Reset VLAN + * Input: + * None. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + * + */ +rtk_api_ret_t rtk_vlan_reset(void) +{ + rtk_api_ret_t retVal = 0; + + if (NULL == RT_MAPPER->vlan_reset) + return RT_ERR_DRIVER_NOT_FOUND; + + RTK_API_LOCK(); + retVal = RT_MAPPER->vlan_reset(); + RTK_API_UNLOCK(); + + return retVal; +} + diff --git a/sources/uboot-be550/drivers/net/rtl8372/vlan.h b/sources/uboot-be550/drivers/net/rtl8372/vlan.h new file mode 100755 index 00000000..00ae17aa --- /dev/null +++ b/sources/uboot-be550/drivers/net/rtl8372/vlan.h @@ -0,0 +1,716 @@ +/* + * Copyright (C) 2013 Realtek Semiconductor Corp. + * All Rights Reserved. + * + * This program is the proprietary software of Realtek Semiconductor + * Corporation and/or its licensors, and only be used, duplicated, + * modified or distributed under the authorized license from Realtek. + * + * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER + * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED. + * + * Purpose : RTL8373 switch high-level API + * + * Feature : The file includes Trap module high-layer VLAN defination + * + */ + +#ifndef __RTK_API_VLAN_H__ +#define __RTK_API_VLAN_H__ + + +/* + * Data Type Declaration + */ +#define RTK_VID_MAX (0xFFF) +#define RTK_MAX_NUM_OF_MSTI (0xF) +#define RTK_FID_MAX (0xF) + +typedef rtk_uint32 rtk_stp_msti_id_t; /* MSTI ID */ + +typedef enum rtk_stp_state_e +{ + STP_STATE_DISABLED = 0, + STP_STATE_BLOCKING, + STP_STATE_LEARNING, + STP_STATE_FORWARDING, + STP_STATE_END +} rtk_stp_state_t; + +typedef rtk_uint32 rtk_vlan_proto_type_t; /* protocol and port based VLAN protocol type */ + + +typedef enum rtk_vlan_acceptFrameType_e +{ + ACCEPT_FRAME_TYPE_ALL = 0, /* untagged, priority-tagged and tagged */ + ACCEPT_FRAME_TYPE_TAG_ONLY, /* tagged */ + ACCEPT_FRAME_TYPE_UNTAG_ONLY, /* untagged and priority-tagged */ + ACCEPT_FRAME_TYPE_END +} rtk_vlan_acceptFrameType_t; + + +/* frame type of protocol vlan - reference 802.1v standard */ +typedef enum rtk_vlan_protoVlan_frameType_e +{ + FRAME_TYPE_ETHERNET = 0, + FRAME_TYPE_LLCOTHER, + FRAME_TYPE_RFC1042, + FRAME_TYPE_END +} rtk_vlan_protoVlan_frameType_t; + +/* tagged mode of VLAN - reference realtek private specification */ +typedef enum rtk_vlan_egressTagMode_e +{ + VLAN_EGRESS_TAG_MODE_ORIGINAL = 0, + VLAN_EGRESS_TAG_MODE_KEEP_FORMAT, + VLAN_EGRESS_TAG_MODE_PRI, + VLAN_EGRESS_TAG_MODE_REAL_KEEP, + VLAN_EGRESS_TAG_MODE_END +} rtk_vlan_egressTagMode_t; + +typedef enum rtk_vlan_resVidAction_e +{ + RSV_VID_ACTION_UNTAG = 0, + RSV_VID_ACTION_TAG, + RSV_VID_ACTION_END +} +rtk_vlan_resVidAction_t; + +/* Protocol-and-port-based Vlan structure */ +typedef struct rtk_vlan_protoAndPortInfo_s +{ + rtk_uint32 proto_type; + rtk_vlan_protoVlan_frameType_t frame_type; + rtk_vlan_t cvid; + rtk_pri_t cpri; +}rtk_vlan_protoAndPortInfo_t; + +typedef struct rtk_vlan_entry_s +{ + rtk_portmask_t mbr; + rtk_portmask_t untag; + rtk_uint16 fid_msti; + rtk_uint16 svlan_chk_ivl_svl; + rtk_uint16 ivl_svl; +}rtk_vlan_entry_t; + +typedef struct rtk_vlan_disL2_learn_s +{ + rtk_uint32 valid; + rtk_uint32 vid; + rtk_uint32 act; +}rtk_vlan_disL2_learn_t; + +/* Function Name: + * rtk_vlan_init + * Description: + * Initialize VLAN. + * Input: + * None + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * Note: + * VLAN is disabled by default. User has to call this API to enable VLAN before + * using it. And It will set a default VLAN(vid 1) including all ports and set + * all ports PVID to the default VLAN. + */ +extern rtk_api_ret_t rtk_vlan_init(void); + +/* Function Name: + * rtk_vlan_set + * Description: + * Set a VLAN entry. + * Input: + * vid - VLAN ID to configure. + * pVlanCfg - VLAN Configuration + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_L2_FID - Invalid FID. + * RT_ERR_VLAN_PORT_MBR_EXIST - Invalid member port mask. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * Note: + * + */ +extern rtk_api_ret_t rtk_vlan_set(rtk_vlan_t vid, rtk_vlan_entry_t *pVlanCfg); + +/* Function Name: + * rtk_vlan_get + * Description: + * Get a VLAN entry. + * Input: + * vid - VLAN ID to configure. + * Output: + * pVlanCfg - VLAN Configuration + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * Note: + * + */ +extern rtk_api_ret_t rtk_vlan_get(rtk_vlan_t vid, rtk_vlan_entry_t *pVlanCfg); + +/* Function Name: + * rtk_vlan_egrFilterEnable_set + * Description: + * Set VLAN egress filter. + * Input: + * egrFilter - Egress filtering + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid input parameters. + * Note: + * + */ +extern rtk_api_ret_t rtk_vlan_egrFilterEnable_set(rtk_enable_t egrFilter); + +/* Function Name: + * rtk_vlan_egrFilterEnable_get + * Description: + * Get VLAN egress filter. + * Input: + * pEgrFilter - Egress filtering + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - NULL Pointer. + * Note: + * + */ +extern rtk_api_ret_t rtk_vlan_egrFilterEnable_get(rtk_enable_t *pEgrFilter); + +/* Function Name: + * rtk_vlan_portPvid_set + * Description: + * Set port to specified VLAN ID(PVID). + * Input: + * port - Port id. + * pvid - Specified VLAN ID. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_VLAN_PRIORITY - Invalid priority. + * RT_ERR_VLAN_ENTRY_NOT_FOUND - VLAN entry not found. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * Note: + * The API is used for Port-based VLAN. The untagged frame received from the + * port will be classified to the specified VLAN and assigned to the specified priority. + */ +extern rtk_api_ret_t rtk_vlan_portPvid_set(rtk_port_t port, rtk_vlan_t pvid); + +/* Function Name: + * rtk_vlan_portPvid_get + * Description: + * Get VLAN ID(PVID) on specified port. + * Input: + * port - Port id. + * Output: + * pPvid - Specified VLAN ID. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get the PVID and 802.1p priority for the PVID of Port-based VLAN. + */ +extern rtk_api_ret_t rtk_vlan_portPvid_get(rtk_port_t port, rtk_vlan_t *pPvid); + +/* Function Name: + * rtk_vlan_portIgrFilterEnable_set + * Description: + * Set VLAN ingress for each port. + * Input: + * port - Port id. + * igrFilter - VLAN ingress function enable status. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number + * RT_ERR_ENABLE - Invalid enable input + * Note: + * The status of vlan ingress filter is as following: + * - DISABLED + * - ENABLED + * While VLAN function is enabled, ASIC will decide VLAN ID for each received frame and get belonged member + * ports from VLAN table. If received port is not belonged to VLAN member ports, ASIC will drop received frame if VLAN ingress function is enabled. + */ +extern rtk_api_ret_t rtk_vlan_portIgrFilterEnable_set(rtk_port_t port, rtk_enable_t igrFilter); + +/* Function Name: + * rtk_vlan_portIgrFilterEnable_get + * Description: + * Get VLAN Ingress Filter + * Input: + * port - Port id. + * Output: + * pIgrFilter - VLAN ingress function enable status. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can Get the VLAN ingress filter status. + * The status of vlan ingress filter is as following: + * - DISABLED + * - ENABLED + */ +extern rtk_api_ret_t rtk_vlan_portIgrFilterEnable_get(rtk_port_t port, rtk_enable_t *pIgrFilter); + +/* Function Name: + * rtk_vlan_portAcceptFrameType_set + * Description: + * Set VLAN accept_frame_type + * Input: + * port - Port id. + * acceptFrameType - accept frame type + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_VLAN_ACCEPT_FRAME_TYPE - Invalid frame type. + * Note: + * The API is used for checking 802.1Q tagged frames. + * The accept frame type as following: + * - ACCEPT_FRAME_TYPE_ALL + * - ACCEPT_FRAME_TYPE_TAG_ONLY + * - ACCEPT_FRAME_TYPE_UNTAG_ONLY + */ +extern rtk_api_ret_t rtk_vlan_portAcceptFrameType_set(rtk_port_t port, rtk_vlan_acceptFrameType_t acceptFrameType); + +/* Function Name: + * rtk_vlan_portAcceptFrameType_get + * Description: + * Get VLAN accept_frame_type + * Input: + * port - Port id. + * Output: + * pAcceptFrameType - accept frame type + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can Get the VLAN ingress filter. + * The accept frame type as following: + * - ACCEPT_FRAME_TYPE_ALL + * - ACCEPT_FRAME_TYPE_TAG_ONLY + * - ACCEPT_FRAME_TYPE_UNTAG_ONLY + */ +extern rtk_api_ret_t rtk_vlan_portAcceptFrameType_get(rtk_port_t port, rtk_vlan_acceptFrameType_t *pAcceptFrameType); + +/* Function Name: + * rtk_vlan_tagMode_set + * Description: + * Set CVLAN egress tag mode + * Input: + * port - Port id. + * tagMode - The egress tag mode. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_PORT_ID - Invalid port number. + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_ENABLE - Invalid enable input. + * Note: + * The API can set Egress tag mode. There are 4 mode for egress tag: + * - VLAN_EGRESS_TAG_MODE_ORIGINAL, + * - VLAN_EGRESS_TAG_MODE_KEEP_FORMAT, + * - VLAN_EGRESS_TAG_MODE_PRI. + * - VLAN_EGRESS_TAG_MODE_REAL_KEEP, + */ +extern rtk_api_ret_t rtk_vlan_tagMode_set(rtk_port_t port, rtk_vlan_egressTagMode_t tagMode); + +/* Function Name: + * rtk_vlan_tagMode_get + * Description: + * Get CVLAN egress tag mode + * Input: + * port - Port id. + * Output: + * pTagMode - The egress tag mode. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * The API can get Egress tag mode. There are 4 mode for egress tag: + * - VLAN_EGRESS_TAG_MODE_ORIGINAL, + * - VLAN_EGRESS_TAG_MODE_KEEP_FORMAT, + * - VLAN_EGRESS_TAG_MODE_PRI. + * - VLAN_EGRESS_TAG_MODE_REAL_KEEP, + */ +extern rtk_api_ret_t rtk_vlan_tagMode_get(rtk_port_t port, rtk_vlan_egressTagMode_t *pTagMode); + +/* Function Name: + * rtk_vlan_transparent_set + * Description: + * Set VLAN transparent mode + * Input: + * egrPort - Egress Port id. + * pIgrPmsk - Ingress Port Mask. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * None. + */ +extern rtk_api_ret_t rtk_vlan_transparent_set(rtk_port_t egrPort, rtk_portmask_t *pIgrPmsk); + +/* Function Name: + * rtk_vlan_transparent_get + * Description: + * Get VLAN transparent mode + * Input: + * egrPort - Egress Port id. + * Output: + * pIgrPmsk - Ingress Port Mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * None. + */ +extern rtk_api_ret_t rtk_vlan_transparent_get(rtk_port_t egrPort, rtk_portmask_t *pIgrPmsk); + +/* Function Name: + * rtk_vlan_keep_set + * Description: + * Set VLAN egress keep mode + * Input: + * egrPort - Egress Port id. + * pIgrPmsk - Ingress Port Mask. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * None. + */ +extern rtk_api_ret_t rtk_vlan_keep_set(rtk_port_t egrPort, rtk_portmask_t *pIgrPmsk); + +/* Function Name: + * rtk_vlan_keep_get + * Description: + * Get VLAN egress keep mode + * Input: + * egrPort - Egress Port id. + * Output: + * pIgrPmsk - Ingress Port Mask + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port number. + * Note: + * None. + */ +extern rtk_api_ret_t rtk_vlan_keep_get(rtk_port_t egrPort, rtk_portmask_t *pIgrPmsk); + +/* Function Name: + * rtk_vlan_stg_set + * Description: + * Set spanning tree group instance of the vlan to the specified device + * Input: + * vid - Specified VLAN ID. + * stg - spanning tree group instance. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_MSTI - Invalid msti parameter + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * Note: + * The API can set spanning tree group instance of the vlan to the specified device. + */ +extern rtk_api_ret_t rtk_vlan_stg_set(rtk_vlan_t vid, rtk_stp_msti_id_t stg); + +/* Function Name: + * rtk_vlan_stg_get + * Description: + * Get spanning tree group instance of the vlan to the specified device + * Input: + * vid - Specified VLAN ID. + * Output: + * pStg - spanning tree group instance. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_VLAN_VID - Invalid VID parameter. + * Note: + * The API can get spanning tree group instance of the vlan to the specified device. + */ +extern rtk_api_ret_t rtk_vlan_stg_get(rtk_vlan_t vid, rtk_stp_msti_id_t *pStg); + +/* Function Name: + * rtk_vlan_portFid_set + * Description: + * Set port-based filtering database + * Input: + * port - Port id. + * enable - ebable port-based FID + * fid - Specified filtering database. + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_L2_FID - Invalid fid. + * RT_ERR_INPUT - Invalid input parameter. + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API can set port-based filtering database. If the function is enabled, all input + * packets will be assigned to the port-based fid regardless vlan tag. + */ +extern rtk_api_ret_t rtk_vlan_portFid_set(rtk_port_t port, rtk_enable_t enable, rtk_fid_t fid); + +/* Function Name: + * rtk_vlan_portFid_get + * Description: + * Get port-based filtering database + * Input: + * port - Port id. + * Output: + * pEnable - ebable port-based FID + * pFid - Specified filtering database. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Invalid input parameters. + * RT_ERR_PORT_ID - Invalid port ID. + * Note: + * The API can get port-based filtering database status. If the function is enabled, all input + * packets will be assigned to the port-based fid regardless vlan tag. + */ +extern rtk_api_ret_t rtk_vlan_portFid_get(rtk_port_t port, rtk_enable_t *pEnable, rtk_fid_t *pFid); + +/* Function Name: + * rtk_vlan_UntagDscpPriorityEnable_set + * Description: + * Set Untag DSCP priority assign + * Input: + * enable - state of Untag DSCP priority assign + * Output: + * None + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_ENABLE - Invalid input parameters. + * Note: + * + */ +extern rtk_api_ret_t rtk_vlan_UntagDscpPriorityEnable_set(rtk_enable_t enable); + +/* Function Name: + * rtk_vlan_UntagDscpPriorityEnable_get + * Description: + * Get Untag DSCP priority assign + * Input: + * None + * Output: + * pEnable - state of Untag DSCP priority assign + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - Null pointer + * Note: + * + */ +extern rtk_api_ret_t rtk_vlan_UntagDscpPriorityEnable_get(rtk_enable_t *pEnable); + +/* Function Name: + * rtk_vlan_reservedVidAction_set + * Description: + * Set Action of VLAN ID = 0 & 4095 tagged packet + * Input: + * actionVid0 - Action for VID 0. + * actionVid4095 - Action for VID 4095. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + * + */ +extern rtk_api_ret_t rtk_vlan_reservedVidAction_set(rtk_vlan_resVidAction_t actionVid0, rtk_vlan_resVidAction_t actionVid4095); + +/* Function Name: + * rtk_vlan_reservedVidAction_get + * Description: + * Get Action of VLAN ID = 0 & 4095 tagged packet + * Input: + * pActionVid0 - Action for VID 0. + * pActionVid4095 - Action for VID 4095. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_NULL_POINTER - NULL Pointer + * Note: + * + */ +extern rtk_api_ret_t rtk_vlan_reservedVidAction_get(rtk_vlan_resVidAction_t *pActionVid0, rtk_vlan_resVidAction_t *pActionVid4095); + +/* Function Name: + * rtk_vlan_realKeepRemarkEnable_set + * Description: + * Set Real keep 1p remarking feature + * Input: + * enabled - State of 1p remarking at real keep packet + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + * + */ +extern rtk_api_ret_t rtk_vlan_realKeepRemarkEnable_set(rtk_enable_t enabled); + +/* Function Name: + * rtk_vlan_realKeepRemarkEnable_get + * Description: + * Get Real keep 1p remarking feature + * Input: + * None. + * Output: + * pEnabled - State of 1p remarking at real keep packet + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + * + */ +extern rtk_api_ret_t rtk_vlan_realKeepRemarkEnable_get(rtk_enable_t *pEnabled); + +/******************************************************************************* +* Function Name: rtk_vlan_disL2Learn_set +* +* Description: +* config a L2 disable learning entry which based on vlan id +*Input: +* index: entry index +* pDisL2LearnCfg: L2 disable learning database +*Output: +* None +*Return: +* RT_ERR_OK - OK +* RT_ERR_FAILED - Failed +* RT_ERR_ENTRY_INDEX - error entry +* RT_ERR_ENABLE - error action +* RT_ERR_NULL_POINTER - NULL Pointer +* RT_ERR_VLAN_VID - Invalid VID parameter. + +*Note: None +*******************************************************************************/ +extern rtk_api_ret_t rtk_vlan_disL2Learn_set(rtk_vlan_disL2_learn_t *pDisL2LearnCfg); +/******************************************************************************* +* Function Name: rtk_vlan_disL2Learn_get +* +* Description: +* get a L2 disable learning entry which based on vlan id +*Input: +* index: entry index +* pDisL2LearnCfg: L2 disable learning database +*Output: +* None +*Return: +* RT_ERR_OK - OK +* RT_ERR_FAILED - Failed +* RT_ERR_ENTRY_INDEX - error entry +* RT_ERR_ENABLE - error action +* RT_ERR_NULL_POINTER - NULL Pointer +* RT_ERR_VLAN_VID - Invalid VID parameter. + +*Note: None +*******************************************************************************/ +extern rtk_api_ret_t rtk_vlan_disL2Learn_get(rtk_uint32 index, rtk_vlan_disL2_learn_t *pDisL2LearnCfg); + +/* Function Name: + * rtk_vlan_reset + * Description: + * Reset VLAN + * Input: + * None. + * Output: + * None. + * Return: + * RT_ERR_OK - OK + * RT_ERR_FAILED - Failed + * RT_ERR_SMI - SMI access error + * RT_ERR_INPUT - Error Input + * Note: + * + */ +rtk_api_ret_t rtk_vlan_reset(void); + +#endif /* __RTK_API_VLAN_H__ */ diff --git a/sources/uboot-be550/drivers/net/sandbox-raw.c b/sources/uboot-be550/drivers/net/sandbox-raw.c new file mode 100644 index 00000000..59124279 --- /dev/null +++ b/sources/uboot-be550/drivers/net/sandbox-raw.c @@ -0,0 +1,165 @@ +/* + * Copyright (c) 2015 National Instruments + * + * (C) Copyright 2015 + * Joe Hershberger + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static int reply_arp; +static struct in_addr arp_ip; + +static int sb_eth_raw_start(struct udevice *dev) +{ + struct eth_sandbox_raw_priv *priv = dev_get_priv(dev); + struct eth_pdata *pdata = dev_get_platdata(dev); + const char *interface; + + debug("eth_sandbox_raw: Start\n"); + + interface = fdt_getprop(gd->fdt_blob, dev->of_offset, + "host-raw-interface", NULL); + if (interface == NULL) + return -EINVAL; + + if (strcmp(interface, "lo") == 0) { + priv->local = 1; + setenv("ipaddr", "127.0.0.1"); + setenv("serverip", "127.0.0.1"); + } + return sandbox_eth_raw_os_start(interface, pdata->enetaddr, priv); +} + +static int sb_eth_raw_send(struct udevice *dev, void *packet, int length) +{ + struct eth_sandbox_raw_priv *priv = dev_get_priv(dev); + + debug("eth_sandbox_raw: Send packet %d\n", length); + + if (priv->local) { + struct ethernet_hdr *eth = packet; + + if (ntohs(eth->et_protlen) == PROT_ARP) { + struct arp_hdr *arp = packet + ETHER_HDR_SIZE; + + /** + * localhost works on a higher-level API in Linux than + * ARP packets, so fake it + */ + arp_ip = net_read_ip(&arp->ar_tpa); + reply_arp = 1; + return 0; + } + packet += ETHER_HDR_SIZE; + length -= ETHER_HDR_SIZE; + } + return sandbox_eth_raw_os_send(packet, length, priv); +} + +static int sb_eth_raw_recv(struct udevice *dev, int flags, uchar **packetp) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + struct eth_sandbox_raw_priv *priv = dev_get_priv(dev); + int retval = 0; + int length; + + if (reply_arp) { + struct arp_hdr *arp = (void *)net_rx_packets[0] + + ETHER_HDR_SIZE; + + /* + * Fake an ARP response. The u-boot network stack is sending an + * ARP request (to find the MAC address to address the actual + * packet to) and requires an ARP response to continue. Since + * this is the localhost interface, there is no Etherent level + * traffic at all, so there is no way to send an ARP request or + * to get a response. For this reason we fake the response to + * make the u-boot network stack happy. + */ + arp->ar_hrd = htons(ARP_ETHER); + arp->ar_pro = htons(PROT_IP); + arp->ar_hln = ARP_HLEN; + arp->ar_pln = ARP_PLEN; + arp->ar_op = htons(ARPOP_REPLY); + /* Any non-zero MAC address will work */ + memset(&arp->ar_sha, 0x01, ARP_HLEN); + /* Use whatever IP we were looking for (always 127.0.0.1?) */ + net_write_ip(&arp->ar_spa, arp_ip); + memcpy(&arp->ar_tha, pdata->enetaddr, ARP_HLEN); + net_write_ip(&arp->ar_tpa, net_ip); + length = ARP_HDR_SIZE; + } else { + /* If local, the Ethernet header won't be included; skip it */ + uchar *pktptr = priv->local ? + net_rx_packets[0] + ETHER_HDR_SIZE : net_rx_packets[0]; + + retval = sandbox_eth_raw_os_recv(pktptr, &length, priv); + } + + if (!retval && length) { + if (priv->local) { + struct ethernet_hdr *eth = (void *)net_rx_packets[0]; + + /* Fill in enough of the missing Ethernet header */ + memcpy(eth->et_dest, pdata->enetaddr, ARP_HLEN); + memset(eth->et_src, 0x01, ARP_HLEN); + eth->et_protlen = htons(reply_arp ? PROT_ARP : PROT_IP); + reply_arp = 0; + length += ETHER_HDR_SIZE; + } + + debug("eth_sandbox_raw: received packet %d\n", + length); + *packetp = net_rx_packets[0]; + return length; + } + return retval; +} + +static void sb_eth_raw_stop(struct udevice *dev) +{ + struct eth_sandbox_raw_priv *priv = dev_get_priv(dev); + + debug("eth_sandbox_raw: Stop\n"); + + sandbox_eth_raw_os_stop(priv); +} + +static const struct eth_ops sb_eth_raw_ops = { + .start = sb_eth_raw_start, + .send = sb_eth_raw_send, + .recv = sb_eth_raw_recv, + .stop = sb_eth_raw_stop, +}; + +static int sb_eth_raw_ofdata_to_platdata(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + + pdata->iobase = dev_get_addr(dev); + return 0; +} + +static const struct udevice_id sb_eth_raw_ids[] = { + { .compatible = "sandbox,eth-raw" }, + { } +}; + +U_BOOT_DRIVER(eth_sandbox_raw) = { + .name = "eth_sandbox_raw", + .id = UCLASS_ETH, + .of_match = sb_eth_raw_ids, + .ofdata_to_platdata = sb_eth_raw_ofdata_to_platdata, + .ops = &sb_eth_raw_ops, + .priv_auto_alloc_size = sizeof(struct eth_sandbox_raw_priv), + .platdata_auto_alloc_size = sizeof(struct eth_pdata), +}; diff --git a/sources/uboot-be550/drivers/net/sandbox.c b/sources/uboot-be550/drivers/net/sandbox.c new file mode 100644 index 00000000..d538d379 --- /dev/null +++ b/sources/uboot-be550/drivers/net/sandbox.c @@ -0,0 +1,225 @@ +/* + * Copyright (c) 2015 National Instruments + * + * (C) Copyright 2015 + * Joe Hershberger + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/** + * struct eth_sandbox_priv - memory for sandbox mock driver + * + * fake_host_hwaddr: MAC address of mocked machine + * fake_host_ipaddr: IP address of mocked machine + * recv_packet_buffer: buffer of the packet returned as received + * recv_packet_length: length of the packet returned as received + */ +struct eth_sandbox_priv { + uchar fake_host_hwaddr[ARP_HLEN]; + struct in_addr fake_host_ipaddr; + uchar *recv_packet_buffer; + int recv_packet_length; +}; + +static bool disabled[8] = {false}; +static bool skip_timeout; + +/* + * sandbox_eth_disable_response() + * + * index - The alias index (also DM seq number) + * disable - If non-zero, ignore sent packets and don't send mock response + */ +void sandbox_eth_disable_response(int index, bool disable) +{ + disabled[index] = disable; +} + +/* + * sandbox_eth_skip_timeout() + * + * When the first packet read is attempted, fast-forward time + */ +void sandbox_eth_skip_timeout(void) +{ + skip_timeout = true; +} + +static int sb_eth_start(struct udevice *dev) +{ + struct eth_sandbox_priv *priv = dev_get_priv(dev); + + debug("eth_sandbox: Start\n"); + + fdtdec_get_byte_array(gd->fdt_blob, dev->of_offset, "fake-host-hwaddr", + priv->fake_host_hwaddr, ARP_HLEN); + priv->recv_packet_buffer = net_rx_packets[0]; + return 0; +} + +static int sb_eth_send(struct udevice *dev, void *packet, int length) +{ + struct eth_sandbox_priv *priv = dev_get_priv(dev); + struct ethernet_hdr *eth = packet; + + debug("eth_sandbox: Send packet %d\n", length); + + if (dev->seq >= 0 && dev->seq < ARRAY_SIZE(disabled) && + disabled[dev->seq]) + return 0; + + if (ntohs(eth->et_protlen) == PROT_ARP) { + struct arp_hdr *arp = packet + ETHER_HDR_SIZE; + + if (ntohs(arp->ar_op) == ARPOP_REQUEST) { + struct ethernet_hdr *eth_recv; + struct arp_hdr *arp_recv; + + /* store this as the assumed IP of the fake host */ + priv->fake_host_ipaddr = net_read_ip(&arp->ar_tpa); + /* Formulate a fake response */ + eth_recv = (void *)priv->recv_packet_buffer; + memcpy(eth_recv->et_dest, eth->et_src, ARP_HLEN); + memcpy(eth_recv->et_src, priv->fake_host_hwaddr, + ARP_HLEN); + eth_recv->et_protlen = htons(PROT_ARP); + + arp_recv = (void *)priv->recv_packet_buffer + + ETHER_HDR_SIZE; + arp_recv->ar_hrd = htons(ARP_ETHER); + arp_recv->ar_pro = htons(PROT_IP); + arp_recv->ar_hln = ARP_HLEN; + arp_recv->ar_pln = ARP_PLEN; + arp_recv->ar_op = htons(ARPOP_REPLY); + memcpy(&arp_recv->ar_sha, priv->fake_host_hwaddr, + ARP_HLEN); + net_write_ip(&arp_recv->ar_spa, priv->fake_host_ipaddr); + memcpy(&arp_recv->ar_tha, &arp->ar_sha, ARP_HLEN); + net_copy_ip(&arp_recv->ar_tpa, &arp->ar_spa); + + priv->recv_packet_length = ETHER_HDR_SIZE + + ARP_HDR_SIZE; + } + } else if (ntohs(eth->et_protlen) == PROT_IP) { + struct ip_udp_hdr *ip = packet + ETHER_HDR_SIZE; + + if (ip->ip_p == IPPROTO_ICMP) { + struct icmp_hdr *icmp = (struct icmp_hdr *)&ip->udp_src; + + if (icmp->type == ICMP_ECHO_REQUEST) { + struct ethernet_hdr *eth_recv; + struct ip_udp_hdr *ipr; + struct icmp_hdr *icmpr; + + /* reply to the ping */ + memcpy(priv->recv_packet_buffer, packet, + length); + eth_recv = (void *)priv->recv_packet_buffer; + ipr = (void *)priv->recv_packet_buffer + + ETHER_HDR_SIZE; + icmpr = (struct icmp_hdr *)&ipr->udp_src; + memcpy(eth_recv->et_dest, eth->et_src, + ARP_HLEN); + memcpy(eth_recv->et_src, priv->fake_host_hwaddr, + ARP_HLEN); + ipr->ip_sum = 0; + ipr->ip_off = 0; + net_copy_ip((void *)&ipr->ip_dst, &ip->ip_src); + net_write_ip((void *)&ipr->ip_src, + priv->fake_host_ipaddr); + ipr->ip_sum = compute_ip_checksum(ipr, + IP_HDR_SIZE); + + icmpr->type = ICMP_ECHO_REPLY; + icmpr->checksum = 0; + icmpr->checksum = compute_ip_checksum(icmpr, + ICMP_HDR_SIZE); + + priv->recv_packet_length = length; + } + } + } + + return 0; +} + +static int sb_eth_recv(struct udevice *dev, int flags, uchar **packetp) +{ + struct eth_sandbox_priv *priv = dev_get_priv(dev); + + if (skip_timeout) { + sandbox_timer_add_offset(11000UL); + skip_timeout = false; + } + + if (priv->recv_packet_length) { + int lcl_recv_packet_length = priv->recv_packet_length; + + debug("eth_sandbox: received packet %d\n", + priv->recv_packet_length); + priv->recv_packet_length = 0; + *packetp = priv->recv_packet_buffer; + return lcl_recv_packet_length; + } + return 0; +} + +static void sb_eth_stop(struct udevice *dev) +{ + debug("eth_sandbox: Stop\n"); +} + +static int sb_eth_write_hwaddr(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + + debug("eth_sandbox %s: Write HW ADDR - %pM\n", dev->name, + pdata->enetaddr); + return 0; +} + +static const struct eth_ops sb_eth_ops = { + .start = sb_eth_start, + .send = sb_eth_send, + .recv = sb_eth_recv, + .stop = sb_eth_stop, + .write_hwaddr = sb_eth_write_hwaddr, +}; + +static int sb_eth_remove(struct udevice *dev) +{ + return 0; +} + +static int sb_eth_ofdata_to_platdata(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + + pdata->iobase = dev_get_addr(dev); + return 0; +} + +static const struct udevice_id sb_eth_ids[] = { + { .compatible = "sandbox,eth" }, + { } +}; + +U_BOOT_DRIVER(eth_sandbox) = { + .name = "eth_sandbox", + .id = UCLASS_ETH, + .of_match = sb_eth_ids, + .ofdata_to_platdata = sb_eth_ofdata_to_platdata, + .remove = sb_eth_remove, + .ops = &sb_eth_ops, + .priv_auto_alloc_size = sizeof(struct eth_sandbox_priv), + .platdata_auto_alloc_size = sizeof(struct eth_pdata), +}; diff --git a/sources/uboot-be550/drivers/net/sh_eth.c b/sources/uboot-be550/drivers/net/sh_eth.c new file mode 100644 index 00000000..a320b4d7 --- /dev/null +++ b/sources/uboot-be550/drivers/net/sh_eth.c @@ -0,0 +1,663 @@ +/* + * sh_eth.c - Driver for Renesas ethernet controler. + * + * Copyright (C) 2008, 2011 Renesas Solutions Corp. + * Copyright (c) 2008, 2011, 2014 2014 Nobuhiro Iwamatsu + * Copyright (c) 2007 Carlos Munoz + * Copyright (C) 2013, 2014 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "sh_eth.h" + +#ifndef CONFIG_SH_ETHER_USE_PORT +# error "Please define CONFIG_SH_ETHER_USE_PORT" +#endif +#ifndef CONFIG_SH_ETHER_PHY_ADDR +# error "Please define CONFIG_SH_ETHER_PHY_ADDR" +#endif + +#if defined(CONFIG_SH_ETHER_CACHE_WRITEBACK) && !defined(CONFIG_SYS_DCACHE_OFF) +#define flush_cache_wback(addr, len) \ + flush_dcache_range((u32)addr, (u32)(addr + len - 1)) +#else +#define flush_cache_wback(...) +#endif + +#if defined(CONFIG_SH_ETHER_CACHE_INVALIDATE) && defined(CONFIG_ARM) +#define invalidate_cache(addr, len) \ + { \ + u32 line_size = CONFIG_SH_ETHER_ALIGNE_SIZE; \ + u32 start, end; \ + \ + start = (u32)addr; \ + end = start + len; \ + start &= ~(line_size - 1); \ + end = ((end + line_size - 1) & ~(line_size - 1)); \ + \ + invalidate_dcache_range(start, end); \ + } +#else +#define invalidate_cache(...) +#endif + +#define TIMEOUT_CNT 1000 + +int sh_eth_send(struct eth_device *dev, void *packet, int len) +{ + struct sh_eth_dev *eth = dev->priv; + int port = eth->port, ret = 0, timeout; + struct sh_eth_info *port_info = ð->port_info[port]; + + if (!packet || len > 0xffff) { + printf(SHETHER_NAME ": %s: Invalid argument\n", __func__); + ret = -EINVAL; + goto err; + } + + /* packet must be a 4 byte boundary */ + if ((int)packet & 3) { + printf(SHETHER_NAME ": %s: packet not 4 byte alligned\n" + , __func__); + ret = -EFAULT; + goto err; + } + + /* Update tx descriptor */ + flush_cache_wback(packet, len); + port_info->tx_desc_cur->td2 = ADDR_TO_PHY(packet); + port_info->tx_desc_cur->td1 = len << 16; + /* Must preserve the end of descriptor list indication */ + if (port_info->tx_desc_cur->td0 & TD_TDLE) + port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP | TD_TDLE; + else + port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP; + + flush_cache_wback(port_info->tx_desc_cur, sizeof(struct tx_desc_s)); + + /* Restart the transmitter if disabled */ + if (!(sh_eth_read(eth, EDTRR) & EDTRR_TRNS)) + sh_eth_write(eth, EDTRR_TRNS, EDTRR); + + /* Wait until packet is transmitted */ + timeout = TIMEOUT_CNT; + do { + invalidate_cache(port_info->tx_desc_cur, + sizeof(struct tx_desc_s)); + udelay(100); + } while (port_info->tx_desc_cur->td0 & TD_TACT && timeout--); + + if (timeout < 0) { + printf(SHETHER_NAME ": transmit timeout\n"); + ret = -ETIMEDOUT; + goto err; + } + + port_info->tx_desc_cur++; + if (port_info->tx_desc_cur >= port_info->tx_desc_base + NUM_TX_DESC) + port_info->tx_desc_cur = port_info->tx_desc_base; + +err: + return ret; +} + +int sh_eth_recv(struct eth_device *dev) +{ + struct sh_eth_dev *eth = dev->priv; + int port = eth->port, len = 0; + struct sh_eth_info *port_info = ð->port_info[port]; + uchar *packet; + + /* Check if the rx descriptor is ready */ + invalidate_cache(port_info->rx_desc_cur, sizeof(struct rx_desc_s)); + if (!(port_info->rx_desc_cur->rd0 & RD_RACT)) { + /* Check for errors */ + if (!(port_info->rx_desc_cur->rd0 & RD_RFE)) { + len = port_info->rx_desc_cur->rd1 & 0xffff; + packet = (uchar *) + ADDR_TO_P2(port_info->rx_desc_cur->rd2); + invalidate_cache(packet, len); + net_process_received_packet(packet, len); + } + + /* Make current descriptor available again */ + if (port_info->rx_desc_cur->rd0 & RD_RDLE) + port_info->rx_desc_cur->rd0 = RD_RACT | RD_RDLE; + else + port_info->rx_desc_cur->rd0 = RD_RACT; + + flush_cache_wback(port_info->rx_desc_cur, + sizeof(struct rx_desc_s)); + + /* Point to the next descriptor */ + port_info->rx_desc_cur++; + if (port_info->rx_desc_cur >= + port_info->rx_desc_base + NUM_RX_DESC) + port_info->rx_desc_cur = port_info->rx_desc_base; + } + + /* Restart the receiver if disabled */ + if (!(sh_eth_read(eth, EDRRR) & EDRRR_R)) + sh_eth_write(eth, EDRRR_R, EDRRR); + + return len; +} + +static int sh_eth_reset(struct sh_eth_dev *eth) +{ +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) + int ret = 0, i; + + /* Start e-dmac transmitter and receiver */ + sh_eth_write(eth, EDSR_ENALL, EDSR); + + /* Perform a software reset and wait for it to complete */ + sh_eth_write(eth, EDMR_SRST, EDMR); + for (i = 0; i < TIMEOUT_CNT; i++) { + if (!(sh_eth_read(eth, EDMR) & EDMR_SRST)) + break; + udelay(1000); + } + + if (i == TIMEOUT_CNT) { + printf(SHETHER_NAME ": Software reset timeout\n"); + ret = -EIO; + } + + return ret; +#else + sh_eth_write(eth, sh_eth_read(eth, EDMR) | EDMR_SRST, EDMR); + udelay(3000); + sh_eth_write(eth, sh_eth_read(eth, EDMR) & ~EDMR_SRST, EDMR); + + return 0; +#endif +} + +static int sh_eth_tx_desc_init(struct sh_eth_dev *eth) +{ + int port = eth->port, i, ret = 0; + u32 alloc_desc_size = NUM_TX_DESC * sizeof(struct tx_desc_s); + struct sh_eth_info *port_info = ð->port_info[port]; + struct tx_desc_s *cur_tx_desc; + + /* + * Allocate rx descriptors. They must be aligned to size of struct + * tx_desc_s. + */ + port_info->tx_desc_alloc = + memalign(sizeof(struct tx_desc_s), alloc_desc_size); + if (!port_info->tx_desc_alloc) { + printf(SHETHER_NAME ": memalign failed\n"); + ret = -ENOMEM; + goto err; + } + + flush_cache_wback((u32)port_info->tx_desc_alloc, alloc_desc_size); + + /* Make sure we use a P2 address (non-cacheable) */ + port_info->tx_desc_base = + (struct tx_desc_s *)ADDR_TO_P2((u32)port_info->tx_desc_alloc); + port_info->tx_desc_cur = port_info->tx_desc_base; + + /* Initialize all descriptors */ + for (cur_tx_desc = port_info->tx_desc_base, i = 0; i < NUM_TX_DESC; + cur_tx_desc++, i++) { + cur_tx_desc->td0 = 0x00; + cur_tx_desc->td1 = 0x00; + cur_tx_desc->td2 = 0x00; + } + + /* Mark the end of the descriptors */ + cur_tx_desc--; + cur_tx_desc->td0 |= TD_TDLE; + + /* Point the controller to the tx descriptor list. Must use physical + addresses */ + sh_eth_write(eth, ADDR_TO_PHY(port_info->tx_desc_base), TDLAR); +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) + sh_eth_write(eth, ADDR_TO_PHY(port_info->tx_desc_base), TDFAR); + sh_eth_write(eth, ADDR_TO_PHY(cur_tx_desc), TDFXR); + sh_eth_write(eth, 0x01, TDFFR);/* Last discriptor bit */ +#endif + +err: + return ret; +} + +static int sh_eth_rx_desc_init(struct sh_eth_dev *eth) +{ + int port = eth->port, i , ret = 0; + u32 alloc_desc_size = NUM_RX_DESC * sizeof(struct rx_desc_s); + struct sh_eth_info *port_info = ð->port_info[port]; + struct rx_desc_s *cur_rx_desc; + u8 *rx_buf; + + /* + * Allocate rx descriptors. They must be aligned to size of struct + * rx_desc_s. + */ + port_info->rx_desc_alloc = + memalign(sizeof(struct rx_desc_s), alloc_desc_size); + if (!port_info->rx_desc_alloc) { + printf(SHETHER_NAME ": memalign failed\n"); + ret = -ENOMEM; + goto err; + } + + flush_cache_wback(port_info->rx_desc_alloc, alloc_desc_size); + + /* Make sure we use a P2 address (non-cacheable) */ + port_info->rx_desc_base = + (struct rx_desc_s *)ADDR_TO_P2((u32)port_info->rx_desc_alloc); + + port_info->rx_desc_cur = port_info->rx_desc_base; + + /* + * Allocate rx data buffers. They must be RX_BUF_ALIGNE_SIZE bytes + * aligned and in P2 area. + */ + port_info->rx_buf_alloc = + memalign(RX_BUF_ALIGNE_SIZE, NUM_RX_DESC * MAX_BUF_SIZE); + if (!port_info->rx_buf_alloc) { + printf(SHETHER_NAME ": alloc failed\n"); + ret = -ENOMEM; + goto err_buf_alloc; + } + + port_info->rx_buf_base = (u8 *)ADDR_TO_P2((u32)port_info->rx_buf_alloc); + + /* Initialize all descriptors */ + for (cur_rx_desc = port_info->rx_desc_base, + rx_buf = port_info->rx_buf_base, i = 0; + i < NUM_RX_DESC; cur_rx_desc++, rx_buf += MAX_BUF_SIZE, i++) { + cur_rx_desc->rd0 = RD_RACT; + cur_rx_desc->rd1 = MAX_BUF_SIZE << 16; + cur_rx_desc->rd2 = (u32) ADDR_TO_PHY(rx_buf); + } + + /* Mark the end of the descriptors */ + cur_rx_desc--; + cur_rx_desc->rd0 |= RD_RDLE; + + /* Point the controller to the rx descriptor list */ + sh_eth_write(eth, ADDR_TO_PHY(port_info->rx_desc_base), RDLAR); +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) + sh_eth_write(eth, ADDR_TO_PHY(port_info->rx_desc_base), RDFAR); + sh_eth_write(eth, ADDR_TO_PHY(cur_rx_desc), RDFXR); + sh_eth_write(eth, RDFFR_RDLF, RDFFR); +#endif + + return ret; + +err_buf_alloc: + free(port_info->rx_desc_alloc); + port_info->rx_desc_alloc = NULL; + +err: + return ret; +} + +static void sh_eth_tx_desc_free(struct sh_eth_dev *eth) +{ + int port = eth->port; + struct sh_eth_info *port_info = ð->port_info[port]; + + if (port_info->tx_desc_alloc) { + free(port_info->tx_desc_alloc); + port_info->tx_desc_alloc = NULL; + } +} + +static void sh_eth_rx_desc_free(struct sh_eth_dev *eth) +{ + int port = eth->port; + struct sh_eth_info *port_info = ð->port_info[port]; + + if (port_info->rx_desc_alloc) { + free(port_info->rx_desc_alloc); + port_info->rx_desc_alloc = NULL; + } + + if (port_info->rx_buf_alloc) { + free(port_info->rx_buf_alloc); + port_info->rx_buf_alloc = NULL; + } +} + +static int sh_eth_desc_init(struct sh_eth_dev *eth) +{ + int ret = 0; + + ret = sh_eth_tx_desc_init(eth); + if (ret) + goto err_tx_init; + + ret = sh_eth_rx_desc_init(eth); + if (ret) + goto err_rx_init; + + return ret; +err_rx_init: + sh_eth_tx_desc_free(eth); + +err_tx_init: + return ret; +} + +static int sh_eth_phy_config(struct sh_eth_dev *eth) +{ + int port = eth->port, ret = 0; + struct sh_eth_info *port_info = ð->port_info[port]; + struct eth_device *dev = port_info->dev; + struct phy_device *phydev; + + phydev = phy_connect( + miiphy_get_dev_by_name(dev->name), + port_info->phy_addr, dev, CONFIG_SH_ETHER_PHY_MODE); + port_info->phydev = phydev; + phy_config(phydev); + + return ret; +} + +static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd) +{ + int port = eth->port, ret = 0; + u32 val; + struct sh_eth_info *port_info = ð->port_info[port]; + struct eth_device *dev = port_info->dev; + struct phy_device *phy; + + /* Configure e-dmac registers */ + sh_eth_write(eth, (sh_eth_read(eth, EDMR) & ~EMDR_DESC_R) | + (EMDR_DESC | EDMR_EL), EDMR); + + sh_eth_write(eth, 0, EESIPR); + sh_eth_write(eth, 0, TRSCER); + sh_eth_write(eth, 0, TFTR); + sh_eth_write(eth, (FIFO_SIZE_T | FIFO_SIZE_R), FDR); + sh_eth_write(eth, RMCR_RST, RMCR); +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) + sh_eth_write(eth, 0, RPADIR); +#endif + sh_eth_write(eth, (FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR); + + /* Configure e-mac registers */ + sh_eth_write(eth, 0, ECSIPR); + + /* Set Mac address */ + val = dev->enetaddr[0] << 24 | dev->enetaddr[1] << 16 | + dev->enetaddr[2] << 8 | dev->enetaddr[3]; + sh_eth_write(eth, val, MAHR); + + val = dev->enetaddr[4] << 8 | dev->enetaddr[5]; + sh_eth_write(eth, val, MALR); + + sh_eth_write(eth, RFLR_RFL_MIN, RFLR); +#if defined(SH_ETH_TYPE_GETHER) + sh_eth_write(eth, 0, PIPR); +#endif +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) + sh_eth_write(eth, APR_AP, APR); + sh_eth_write(eth, MPR_MP, MPR); + sh_eth_write(eth, TPAUSER_TPAUSE, TPAUSER); +#endif + +#if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740) + sh_eth_write(eth, CONFIG_SH_ETHER_SH7734_MII, RMII_MII); +#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \ + defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794) + sh_eth_write(eth, sh_eth_read(eth, RMIIMR) | 0x1, RMIIMR); +#endif + /* Configure phy */ + ret = sh_eth_phy_config(eth); + if (ret) { + printf(SHETHER_NAME ": phy config timeout\n"); + goto err_phy_cfg; + } + phy = port_info->phydev; + ret = phy_startup(phy); + if (ret) { + printf(SHETHER_NAME ": phy startup failure\n"); + return ret; + } + + val = 0; + + /* Set the transfer speed */ + if (phy->speed == 100) { + printf(SHETHER_NAME ": 100Base/"); +#if defined(SH_ETH_TYPE_GETHER) + sh_eth_write(eth, GECMR_100B, GECMR); +#elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752) + sh_eth_write(eth, 1, RTRATE); +#elif defined(CONFIG_CPU_SH7724) || defined(CONFIG_R8A7790) || \ + defined(CONFIG_R8A7791) || defined(CONFIG_R8A7793) || \ + defined(CONFIG_R8A7794) + val = ECMR_RTM; +#endif + } else if (phy->speed == 10) { + printf(SHETHER_NAME ": 10Base/"); +#if defined(SH_ETH_TYPE_GETHER) + sh_eth_write(eth, GECMR_10B, GECMR); +#elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752) + sh_eth_write(eth, 0, RTRATE); +#endif + } +#if defined(SH_ETH_TYPE_GETHER) + else if (phy->speed == 1000) { + printf(SHETHER_NAME ": 1000Base/"); + sh_eth_write(eth, GECMR_1000B, GECMR); + } +#endif + + /* Check if full duplex mode is supported by the phy */ + if (phy->duplex) { + printf("Full\n"); + sh_eth_write(eth, val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE|ECMR_DM), + ECMR); + } else { + printf("Half\n"); + sh_eth_write(eth, val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE), ECMR); + } + + return ret; + +err_phy_cfg: + return ret; +} + +static void sh_eth_start(struct sh_eth_dev *eth) +{ + /* + * Enable the e-dmac receiver only. The transmitter will be enabled when + * we have something to transmit + */ + sh_eth_write(eth, EDRRR_R, EDRRR); +} + +static void sh_eth_stop(struct sh_eth_dev *eth) +{ + sh_eth_write(eth, ~EDRRR_R, EDRRR); +} + +int sh_eth_init(struct eth_device *dev, bd_t *bd) +{ + int ret = 0; + struct sh_eth_dev *eth = dev->priv; + + ret = sh_eth_reset(eth); + if (ret) + goto err; + + ret = sh_eth_desc_init(eth); + if (ret) + goto err; + + ret = sh_eth_config(eth, bd); + if (ret) + goto err_config; + + sh_eth_start(eth); + + return ret; + +err_config: + sh_eth_tx_desc_free(eth); + sh_eth_rx_desc_free(eth); + +err: + return ret; +} + +void sh_eth_halt(struct eth_device *dev) +{ + struct sh_eth_dev *eth = dev->priv; + sh_eth_stop(eth); +} + +int sh_eth_initialize(bd_t *bd) +{ + int ret = 0; + struct sh_eth_dev *eth = NULL; + struct eth_device *dev = NULL; + + eth = (struct sh_eth_dev *)malloc(sizeof(struct sh_eth_dev)); + if (!eth) { + printf(SHETHER_NAME ": %s: malloc failed\n", __func__); + ret = -ENOMEM; + goto err; + } + + dev = (struct eth_device *)malloc(sizeof(struct eth_device)); + if (!dev) { + printf(SHETHER_NAME ": %s: malloc failed\n", __func__); + ret = -ENOMEM; + goto err; + } + memset(dev, 0, sizeof(struct eth_device)); + memset(eth, 0, sizeof(struct sh_eth_dev)); + + eth->port = CONFIG_SH_ETHER_USE_PORT; + eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR; + + dev->priv = (void *)eth; + dev->iobase = 0; + dev->init = sh_eth_init; + dev->halt = sh_eth_halt; + dev->send = sh_eth_send; + dev->recv = sh_eth_recv; + eth->port_info[eth->port].dev = dev; + + sprintf(dev->name, SHETHER_NAME); + + /* Register Device to EtherNet subsystem */ + eth_register(dev); + + bb_miiphy_buses[0].priv = eth; + miiphy_register(dev->name, bb_miiphy_read, bb_miiphy_write); + + if (!eth_getenv_enetaddr("ethaddr", dev->enetaddr)) + puts("Please set MAC address\n"); + + return ret; + +err: + if (dev) + free(dev); + + if (eth) + free(eth); + + printf(SHETHER_NAME ": Failed\n"); + return ret; +} + +/******* for bb_miiphy *******/ +static int sh_eth_bb_init(struct bb_miiphy_bus *bus) +{ + return 0; +} + +static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus) +{ + struct sh_eth_dev *eth = bus->priv; + + sh_eth_write(eth, sh_eth_read(eth, PIR) | PIR_MMD, PIR); + + return 0; +} + +static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus) +{ + struct sh_eth_dev *eth = bus->priv; + + sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MMD, PIR); + + return 0; +} + +static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v) +{ + struct sh_eth_dev *eth = bus->priv; + + if (v) + sh_eth_write(eth, sh_eth_read(eth, PIR) | PIR_MDO, PIR); + else + sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MDO, PIR); + + return 0; +} + +static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v) +{ + struct sh_eth_dev *eth = bus->priv; + + *v = (sh_eth_read(eth, PIR) & PIR_MDI) >> 3; + + return 0; +} + +static int sh_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v) +{ + struct sh_eth_dev *eth = bus->priv; + + if (v) + sh_eth_write(eth, sh_eth_read(eth, PIR) | PIR_MDC, PIR); + else + sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MDC, PIR); + + return 0; +} + +static int sh_eth_bb_delay(struct bb_miiphy_bus *bus) +{ + udelay(10); + + return 0; +} + +struct bb_miiphy_bus bb_miiphy_buses[] = { + { + .name = "sh_eth", + .init = sh_eth_bb_init, + .mdio_active = sh_eth_bb_mdio_active, + .mdio_tristate = sh_eth_bb_mdio_tristate, + .set_mdio = sh_eth_bb_set_mdio, + .get_mdio = sh_eth_bb_get_mdio, + .set_mdc = sh_eth_bb_set_mdc, + .delay = sh_eth_bb_delay, + } +}; +int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses); diff --git a/sources/uboot-be550/drivers/net/sh_eth.h b/sources/uboot-be550/drivers/net/sh_eth.h new file mode 100644 index 00000000..5cb520c6 --- /dev/null +++ b/sources/uboot-be550/drivers/net/sh_eth.h @@ -0,0 +1,682 @@ +/* + * sh_eth.h - Driver for Renesas SuperH ethernet controler. + * + * Copyright (C) 2008 - 2012 Renesas Solutions Corp. + * Copyright (c) 2008 - 2012 Nobuhiro Iwamatsu + * Copyright (c) 2007 Carlos Munoz + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +#define SHETHER_NAME "sh_eth" + +#if defined(CONFIG_SH) +/* Malloc returns addresses in the P1 area (cacheable). However we need to + use area P2 (non-cacheable) */ +#define ADDR_TO_P2(addr) ((((int)(addr) & ~0xe0000000) | 0xa0000000)) + +/* The ethernet controller needs to use physical addresses */ +#if defined(CONFIG_SH_32BIT) +#define ADDR_TO_PHY(addr) ((((int)(addr) & ~0xe0000000) | 0x40000000)) +#else +#define ADDR_TO_PHY(addr) ((int)(addr) & ~0xe0000000) +#endif +#elif defined(CONFIG_ARM) +#define inl readl +#define outl writel +#define ADDR_TO_PHY(addr) ((int)(addr)) +#define ADDR_TO_P2(addr) (addr) +#endif /* defined(CONFIG_SH) */ + +/* base padding size is 16 */ +#ifndef CONFIG_SH_ETHER_ALIGNE_SIZE +#define CONFIG_SH_ETHER_ALIGNE_SIZE 16 +#endif + +/* Number of supported ports */ +#define MAX_PORT_NUM 2 + +/* Buffers must be big enough to hold the largest ethernet frame. Also, rx + buffers must be a multiple of 32 bytes */ +#define MAX_BUF_SIZE (48 * 32) + +/* The number of tx descriptors must be large enough to point to 5 or more + frames. If each frame uses 2 descriptors, at least 10 descriptors are needed. + We use one descriptor per frame */ +#define NUM_TX_DESC 8 + +/* The size of the tx descriptor is determined by how much padding is used. + 4, 20, or 52 bytes of padding can be used */ +#define TX_DESC_PADDING (CONFIG_SH_ETHER_ALIGNE_SIZE - 12) + +/* Tx descriptor. We always use 3 bytes of padding */ +struct tx_desc_s { + volatile u32 td0; + u32 td1; + u32 td2; /* Buffer start */ + u8 padding[TX_DESC_PADDING]; /* aligned cache line size */ +}; + +/* There is no limitation in the number of rx descriptors */ +#define NUM_RX_DESC 8 + +/* The size of the rx descriptor is determined by how much padding is used. + 4, 20, or 52 bytes of padding can be used */ +#define RX_DESC_PADDING (CONFIG_SH_ETHER_ALIGNE_SIZE - 12) +/* aligned cache line size */ +#define RX_BUF_ALIGNE_SIZE (CONFIG_SH_ETHER_ALIGNE_SIZE > 32 ? 64 : 32) + +/* Rx descriptor. We always use 4 bytes of padding */ +struct rx_desc_s { + volatile u32 rd0; + volatile u32 rd1; + u32 rd2; /* Buffer start */ + u8 padding[TX_DESC_PADDING]; /* aligned cache line size */ +}; + +struct sh_eth_info { + struct tx_desc_s *tx_desc_alloc; + struct tx_desc_s *tx_desc_base; + struct tx_desc_s *tx_desc_cur; + struct rx_desc_s *rx_desc_alloc; + struct rx_desc_s *rx_desc_base; + struct rx_desc_s *rx_desc_cur; + u8 *rx_buf_alloc; + u8 *rx_buf_base; + u8 mac_addr[6]; + u8 phy_addr; + struct eth_device *dev; + struct phy_device *phydev; +}; + +struct sh_eth_dev { + int port; + struct sh_eth_info port_info[MAX_PORT_NUM]; +}; + +/* from linux/drivers/net/ethernet/renesas/sh_eth.h */ +enum { + /* E-DMAC registers */ + EDSR = 0, + EDMR, + EDTRR, + EDRRR, + EESR, + EESIPR, + TDLAR, + TDFAR, + TDFXR, + TDFFR, + RDLAR, + RDFAR, + RDFXR, + RDFFR, + TRSCER, + RMFCR, + TFTR, + FDR, + RMCR, + EDOCR, + TFUCR, + RFOCR, + FCFTR, + RPADIR, + TRIMD, + RBWAR, + TBRAR, + + /* Ether registers */ + ECMR, + ECSR, + ECSIPR, + PIR, + PSR, + RDMLR, + PIPR, + RFLR, + IPGR, + APR, + MPR, + PFTCR, + PFRCR, + RFCR, + RFCF, + TPAUSER, + TPAUSECR, + BCFR, + BCFRR, + GECMR, + BCULR, + MAHR, + MALR, + TROCR, + CDCR, + LCCR, + CNDCR, + CEFCR, + FRECR, + TSFRCR, + TLFRCR, + CERCR, + CEECR, + RMIIMR, /* R8A7790 */ + MAFCR, + RTRATE, + CSMR, + RMII_MII, + + /* This value must be written at last. */ + SH_ETH_MAX_REGISTER_OFFSET, +}; + +static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = { + [EDSR] = 0x0000, + [EDMR] = 0x0400, + [EDTRR] = 0x0408, + [EDRRR] = 0x0410, + [EESR] = 0x0428, + [EESIPR] = 0x0430, + [TDLAR] = 0x0010, + [TDFAR] = 0x0014, + [TDFXR] = 0x0018, + [TDFFR] = 0x001c, + [RDLAR] = 0x0030, + [RDFAR] = 0x0034, + [RDFXR] = 0x0038, + [RDFFR] = 0x003c, + [TRSCER] = 0x0438, + [RMFCR] = 0x0440, + [TFTR] = 0x0448, + [FDR] = 0x0450, + [RMCR] = 0x0458, + [RPADIR] = 0x0460, + [FCFTR] = 0x0468, + [CSMR] = 0x04E4, + + [ECMR] = 0x0500, + [ECSR] = 0x0510, + [ECSIPR] = 0x0518, + [PIR] = 0x0520, + [PSR] = 0x0528, + [PIPR] = 0x052c, + [RFLR] = 0x0508, + [APR] = 0x0554, + [MPR] = 0x0558, + [PFTCR] = 0x055c, + [PFRCR] = 0x0560, + [TPAUSER] = 0x0564, + [GECMR] = 0x05b0, + [BCULR] = 0x05b4, + [MAHR] = 0x05c0, + [MALR] = 0x05c8, + [TROCR] = 0x0700, + [CDCR] = 0x0708, + [LCCR] = 0x0710, + [CEFCR] = 0x0740, + [FRECR] = 0x0748, + [TSFRCR] = 0x0750, + [TLFRCR] = 0x0758, + [RFCR] = 0x0760, + [CERCR] = 0x0768, + [CEECR] = 0x0770, + [MAFCR] = 0x0778, + [RMII_MII] = 0x0790, +}; + +#if defined(SH_ETH_TYPE_RZ) +static const u16 sh_eth_offset_rz[SH_ETH_MAX_REGISTER_OFFSET] = { + [EDSR] = 0x0000, + [EDMR] = 0x0400, + [EDTRR] = 0x0408, + [EDRRR] = 0x0410, + [EESR] = 0x0428, + [EESIPR] = 0x0430, + [TDLAR] = 0x0010, + [TDFAR] = 0x0014, + [TDFXR] = 0x0018, + [TDFFR] = 0x001c, + [RDLAR] = 0x0030, + [RDFAR] = 0x0034, + [RDFXR] = 0x0038, + [RDFFR] = 0x003c, + [TRSCER] = 0x0438, + [RMFCR] = 0x0440, + [TFTR] = 0x0448, + [FDR] = 0x0450, + [RMCR] = 0x0458, + [RPADIR] = 0x0460, + [FCFTR] = 0x0468, + [CSMR] = 0x04E4, + + [ECMR] = 0x0500, + [ECSR] = 0x0510, + [ECSIPR] = 0x0518, + [PSR] = 0x0528, + [PIPR] = 0x052c, + [RFLR] = 0x0508, + [APR] = 0x0554, + [MPR] = 0x0558, + [PFTCR] = 0x055c, + [PFRCR] = 0x0560, + [TPAUSER] = 0x0564, + [GECMR] = 0x05b0, + [BCULR] = 0x05b4, + [MAHR] = 0x05c0, + [MALR] = 0x05c8, + [TROCR] = 0x0700, + [CDCR] = 0x0708, + [LCCR] = 0x0710, + [CEFCR] = 0x0740, + [FRECR] = 0x0748, + [TSFRCR] = 0x0750, + [TLFRCR] = 0x0758, + [RFCR] = 0x0760, + [CERCR] = 0x0768, + [CEECR] = 0x0770, + [MAFCR] = 0x0778, + [RMII_MII] = 0x0790, +}; +#endif + +static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = { + [ECMR] = 0x0100, + [RFLR] = 0x0108, + [ECSR] = 0x0110, + [ECSIPR] = 0x0118, + [PIR] = 0x0120, + [PSR] = 0x0128, + [RDMLR] = 0x0140, + [IPGR] = 0x0150, + [APR] = 0x0154, + [MPR] = 0x0158, + [TPAUSER] = 0x0164, + [RFCF] = 0x0160, + [TPAUSECR] = 0x0168, + [BCFRR] = 0x016c, + [MAHR] = 0x01c0, + [MALR] = 0x01c8, + [TROCR] = 0x01d0, + [CDCR] = 0x01d4, + [LCCR] = 0x01d8, + [CNDCR] = 0x01dc, + [CEFCR] = 0x01e4, + [FRECR] = 0x01e8, + [TSFRCR] = 0x01ec, + [TLFRCR] = 0x01f0, + [RFCR] = 0x01f4, + [MAFCR] = 0x01f8, + [RTRATE] = 0x01fc, + + [EDMR] = 0x0000, + [EDTRR] = 0x0008, + [EDRRR] = 0x0010, + [TDLAR] = 0x0018, + [RDLAR] = 0x0020, + [EESR] = 0x0028, + [EESIPR] = 0x0030, + [TRSCER] = 0x0038, + [RMFCR] = 0x0040, + [TFTR] = 0x0048, + [FDR] = 0x0050, + [RMCR] = 0x0058, + [TFUCR] = 0x0064, + [RFOCR] = 0x0068, + [RMIIMR] = 0x006C, + [FCFTR] = 0x0070, + [RPADIR] = 0x0078, + [TRIMD] = 0x007c, + [RBWAR] = 0x00c8, + [RDFAR] = 0x00cc, + [TBRAR] = 0x00d4, + [TDFAR] = 0x00d8, +}; + +/* Register Address */ +#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734) +#define SH_ETH_TYPE_GETHER +#define BASE_IO_ADDR 0xfee00000 +#elif defined(CONFIG_CPU_SH7757) || \ + defined(CONFIG_CPU_SH7752) || \ + defined(CONFIG_CPU_SH7753) +#if defined(CONFIG_SH_ETHER_USE_GETHER) +#define SH_ETH_TYPE_GETHER +#define BASE_IO_ADDR 0xfee00000 +#else +#define SH_ETH_TYPE_ETHER +#define BASE_IO_ADDR 0xfef00000 +#endif +#elif defined(CONFIG_CPU_SH7724) +#define SH_ETH_TYPE_ETHER +#define BASE_IO_ADDR 0xA4600000 +#elif defined(CONFIG_R8A7740) +#define SH_ETH_TYPE_GETHER +#define BASE_IO_ADDR 0xE9A00000 +#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \ + defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794) +#define SH_ETH_TYPE_ETHER +#define BASE_IO_ADDR 0xEE700200 +#elif defined(CONFIG_R7S72100) +#define SH_ETH_TYPE_RZ +#define BASE_IO_ADDR 0xE8203000 +#endif + +/* + * Register's bits + * Copy from Linux driver source code + */ +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) +/* EDSR */ +enum EDSR_BIT { + EDSR_ENT = 0x01, EDSR_ENR = 0x02, +}; +#define EDSR_ENALL (EDSR_ENT|EDSR_ENR) +#endif + +/* EDMR */ +enum DMAC_M_BIT { + EDMR_DL1 = 0x20, EDMR_DL0 = 0x10, +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) + EDMR_SRST = 0x03, /* Receive/Send reset */ + EMDR_DESC_R = 0x30, /* Descriptor reserve size */ + EDMR_EL = 0x40, /* Litte endian */ +#elif defined(SH_ETH_TYPE_ETHER) + EDMR_SRST = 0x01, + EMDR_DESC_R = 0x30, /* Descriptor reserve size */ + EDMR_EL = 0x40, /* Litte endian */ +#else + EDMR_SRST = 0x01, +#endif +}; + +#if CONFIG_SH_ETHER_ALIGNE_SIZE == 64 +# define EMDR_DESC EDMR_DL1 +#elif CONFIG_SH_ETHER_ALIGNE_SIZE == 32 +# define EMDR_DESC EDMR_DL0 +#elif CONFIG_SH_ETHER_ALIGNE_SIZE == 16 /* Default */ +# define EMDR_DESC 0 +#endif + +/* RFLR */ +#define RFLR_RFL_MIN 0x05EE /* Recv Frame length 1518 byte */ + +/* EDTRR */ +enum DMAC_T_BIT { +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) + EDTRR_TRNS = 0x03, +#else + EDTRR_TRNS = 0x01, +#endif +}; + +/* GECMR */ +enum GECMR_BIT { +#if defined(CONFIG_CPU_SH7757) || \ + defined(CONFIG_CPU_SH7752) || \ + defined(CONFIG_CPU_SH7753) + GECMR_1000B = 0x20, GECMR_100B = 0x01, GECMR_10B = 0x00, +#else + GECMR_1000B = 0x01, GECMR_100B = 0x04, GECMR_10B = 0x00, +#endif +}; + +/* EDRRR*/ +enum EDRRR_R_BIT { + EDRRR_R = 0x01, +}; + +/* TPAUSER */ +enum TPAUSER_BIT { + TPAUSER_TPAUSE = 0x0000ffff, + TPAUSER_UNLIMITED = 0, +}; + +/* BCFR */ +enum BCFR_BIT { + BCFR_RPAUSE = 0x0000ffff, + BCFR_UNLIMITED = 0, +}; + +/* PIR */ +enum PIR_BIT { + PIR_MDI = 0x08, PIR_MDO = 0x04, PIR_MMD = 0x02, PIR_MDC = 0x01, +}; + +/* PSR */ +enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, }; + +/* EESR */ +enum EESR_BIT { +#if defined(SH_ETH_TYPE_ETHER) + EESR_TWB = 0x40000000, +#else + EESR_TWB = 0xC0000000, + EESR_TC1 = 0x20000000, + EESR_TUC = 0x10000000, + EESR_ROC = 0x80000000, +#endif + EESR_TABT = 0x04000000, + EESR_RABT = 0x02000000, EESR_RFRMER = 0x01000000, +#if defined(SH_ETH_TYPE_ETHER) + EESR_ADE = 0x00800000, +#endif + EESR_ECI = 0x00400000, + EESR_FTC = 0x00200000, EESR_TDE = 0x00100000, + EESR_TFE = 0x00080000, EESR_FRC = 0x00040000, + EESR_RDE = 0x00020000, EESR_RFE = 0x00010000, +#if defined(SH_ETH_TYPE_ETHER) + EESR_CND = 0x00000800, +#endif + EESR_DLC = 0x00000400, + EESR_CD = 0x00000200, EESR_RTO = 0x00000100, + EESR_RMAF = 0x00000080, EESR_CEEF = 0x00000040, + EESR_CELF = 0x00000020, EESR_RRF = 0x00000010, + EESR_RTLF = 0x00000008, EESR_RTSF = 0x00000004, + EESR_PRE = 0x00000002, EESR_CERF = 0x00000001, +}; + + +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) +# define TX_CHECK (EESR_TC1 | EESR_FTC) +# define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \ + | EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI) +# define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE) + +#else +# define TX_CHECK (EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO) +# define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \ + | EESR_RFRMER | EESR_ADE | EESR_TFE | EESR_TDE | EESR_ECI) +# define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE) +#endif + +/* EESIPR */ +enum DMAC_IM_BIT { + DMAC_M_TWB = 0x40000000, DMAC_M_TABT = 0x04000000, + DMAC_M_RABT = 0x02000000, + DMAC_M_RFRMER = 0x01000000, DMAC_M_ADF = 0x00800000, + DMAC_M_ECI = 0x00400000, DMAC_M_FTC = 0x00200000, + DMAC_M_TDE = 0x00100000, DMAC_M_TFE = 0x00080000, + DMAC_M_FRC = 0x00040000, DMAC_M_RDE = 0x00020000, + DMAC_M_RFE = 0x00010000, DMAC_M_TINT4 = 0x00000800, + DMAC_M_TINT3 = 0x00000400, DMAC_M_TINT2 = 0x00000200, + DMAC_M_TINT1 = 0x00000100, DMAC_M_RINT8 = 0x00000080, + DMAC_M_RINT5 = 0x00000010, DMAC_M_RINT4 = 0x00000008, + DMAC_M_RINT3 = 0x00000004, DMAC_M_RINT2 = 0x00000002, + DMAC_M_RINT1 = 0x00000001, +}; + +/* Receive descriptor bit */ +enum RD_STS_BIT { + RD_RACT = 0x80000000, RD_RDLE = 0x40000000, + RD_RFP1 = 0x20000000, RD_RFP0 = 0x10000000, + RD_RFE = 0x08000000, RD_RFS10 = 0x00000200, + RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080, + RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020, + RD_RFS5 = 0x00000010, RD_RFS4 = 0x00000008, + RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002, + RD_RFS1 = 0x00000001, +}; +#define RDF1ST RD_RFP1 +#define RDFEND RD_RFP0 +#define RD_RFP (RD_RFP1|RD_RFP0) + +/* RDFFR*/ +enum RDFFR_BIT { + RDFFR_RDLF = 0x01, +}; + +/* FCFTR */ +enum FCFTR_BIT { + FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000, + FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004, + FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001, +}; +#define FIFO_F_D_RFF (FCFTR_RFF2|FCFTR_RFF1|FCFTR_RFF0) +#define FIFO_F_D_RFD (FCFTR_RFD2|FCFTR_RFD1|FCFTR_RFD0) + +/* Transfer descriptor bit */ +enum TD_STS_BIT { +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_ETHER) || \ + defined(SH_ETH_TYPE_RZ) + TD_TACT = 0x80000000, +#else + TD_TACT = 0x7fffffff, +#endif + TD_TDLE = 0x40000000, TD_TFP1 = 0x20000000, + TD_TFP0 = 0x10000000, +}; +#define TDF1ST TD_TFP1 +#define TDFEND TD_TFP0 +#define TD_TFP (TD_TFP1|TD_TFP0) + +/* RMCR */ +enum RECV_RST_BIT { RMCR_RST = 0x01, }; +/* ECMR */ +enum FELIC_MODE_BIT { +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) + ECMR_TRCCM = 0x04000000, ECMR_RCSC = 0x00800000, + ECMR_DPAD = 0x00200000, ECMR_RZPF = 0x00100000, +#endif + ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000, + ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000, + ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020, + ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004, ECMR_DM = 0x00000002, + ECMR_PRM = 0x00000001, +#ifdef CONFIG_CPU_SH7724 + ECMR_RTM = 0x00000010, +#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \ + defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794) + ECMR_RTM = 0x00000004, +#endif + +}; + +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) +#define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF | ECMR_PFR | \ + ECMR_RXF | ECMR_TXF | ECMR_MCT) +#elif defined(SH_ETH_TYPE_ETHER) +#define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF) +#else +#define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF | ECMR_MCT) +#endif + +/* ECSR */ +enum ECSR_STATUS_BIT { +#if defined(SH_ETH_TYPE_ETHER) + ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10, +#endif + ECSR_LCHNG = 0x04, + ECSR_MPD = 0x02, ECSR_ICD = 0x01, +}; + +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) +# define ECSR_INIT (ECSR_ICD | ECSIPR_MPDIP) +#else +# define ECSR_INIT (ECSR_BRCRX | ECSR_PSRTO | \ + ECSR_LCHNG | ECSR_ICD | ECSIPR_MPDIP) +#endif + +/* ECSIPR */ +enum ECSIPR_STATUS_MASK_BIT { +#if defined(SH_ETH_TYPE_ETHER) + ECSIPR_BRCRXIP = 0x20, + ECSIPR_PSRTOIP = 0x10, +#elif defined(SH_ETY_TYPE_GETHER) + ECSIPR_PSRTOIP = 0x10, + ECSIPR_PHYIP = 0x08, +#endif + ECSIPR_LCHNGIP = 0x04, + ECSIPR_MPDIP = 0x02, + ECSIPR_ICDIP = 0x01, +}; + +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) +# define ECSIPR_INIT (ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP) +#else +# define ECSIPR_INIT (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | \ + ECSIPR_ICDIP | ECSIPR_MPDIP) +#endif + +/* APR */ +enum APR_BIT { + APR_AP = 0x00000004, +}; + +/* MPR */ +enum MPR_BIT { + MPR_MP = 0x00000006, +}; + +/* TRSCER */ +enum DESC_I_BIT { + DESC_I_TINT4 = 0x0800, DESC_I_TINT3 = 0x0400, DESC_I_TINT2 = 0x0200, + DESC_I_TINT1 = 0x0100, DESC_I_RINT8 = 0x0080, DESC_I_RINT5 = 0x0010, + DESC_I_RINT4 = 0x0008, DESC_I_RINT3 = 0x0004, DESC_I_RINT2 = 0x0002, + DESC_I_RINT1 = 0x0001, +}; + +/* RPADIR */ +enum RPADIR_BIT { + RPADIR_PADS1 = 0x20000, RPADIR_PADS0 = 0x10000, + RPADIR_PADR = 0x0003f, +}; + +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) +# define RPADIR_INIT (0x00) +#else +# define RPADIR_INIT (RPADIR_PADS1) +#endif + +/* FDR */ +enum FIFO_SIZE_BIT { + FIFO_SIZE_T = 0x00000700, FIFO_SIZE_R = 0x00000007, +}; + +static inline unsigned long sh_eth_reg_addr(struct sh_eth_dev *eth, + int enum_index) +{ +#if defined(SH_ETH_TYPE_GETHER) + const u16 *reg_offset = sh_eth_offset_gigabit; +#elif defined(SH_ETH_TYPE_ETHER) + const u16 *reg_offset = sh_eth_offset_fast_sh4; +#elif defined(SH_ETH_TYPE_RZ) + const u16 *reg_offset = sh_eth_offset_rz; +#else +#error +#endif + return BASE_IO_ADDR + reg_offset[enum_index] + 0x800 * eth->port; +} + +static inline void sh_eth_write(struct sh_eth_dev *eth, unsigned long data, + int enum_index) +{ + outl(data, sh_eth_reg_addr(eth, enum_index)); +} + +static inline unsigned long sh_eth_read(struct sh_eth_dev *eth, + int enum_index) +{ + return inl(sh_eth_reg_addr(eth, enum_index)); +} diff --git a/sources/uboot-be550/drivers/net/smc91111.c b/sources/uboot-be550/drivers/net/smc91111.c new file mode 100644 index 00000000..f31216ff --- /dev/null +++ b/sources/uboot-be550/drivers/net/smc91111.c @@ -0,0 +1,1306 @@ +/*------------------------------------------------------------------------ + . smc91111.c + . This is a driver for SMSC's 91C111 single-chip Ethernet device. + . + . (C) Copyright 2002 + . Sysgo Real-Time Solutions, GmbH + . Rolf Offermanns + . + . Copyright (C) 2001 Standard Microsystems Corporation (SMSC) + . Developed by Simple Network Magic Corporation (SNMC) + . Copyright (C) 1996 by Erik Stahlman (ES) + . + * SPDX-License-Identifier: GPL-2.0+ + . + . Information contained in this file was obtained from the LAN91C111 + . manual from SMC. To get a copy, if you really want one, you can find + . information under www.smsc.com. + . + . + . "Features" of the SMC chip: + . Integrated PHY/MAC for 10/100BaseT Operation + . Supports internal and external MII + . Integrated 8K packet memory + . EEPROM interface for configuration + . + . Arguments: + . io = for the base address + . irq = for the IRQ + . + . author: + . Erik Stahlman ( erik@vt.edu ) + . Daris A Nevil ( dnevil@snmc.com ) + . + . + . Hardware multicast code from Peter Cammaert ( pc@denkart.be ) + . + . Sources: + . o SMSC LAN91C111 databook (www.smsc.com) + . o smc9194.c by Erik Stahlman + . o skeleton.c by Donald Becker ( becker@cesdis.gsfc.nasa.gov ) + . + . History: + . 06/19/03 Richard Woodruff Made u-boot environment aware and added mac addr checks. + . 10/17/01 Marco Hasewinkel Modify for DNP/1110 + . 07/25/01 Woojung Huh Modify for ADS Bitsy + . 04/25/01 Daris A Nevil Initial public release through SMSC + . 03/16/01 Daris A Nevil Modified smc9194.c for use with LAN91C111 + ----------------------------------------------------------------------------*/ + +#include +#include +#include +#include +#include "smc91111.h" +#include + +/* Use power-down feature of the chip */ +#define POWER_DOWN 0 + +#define NO_AUTOPROBE + +#define SMC_DEBUG 0 + +#if SMC_DEBUG > 1 +static const char version[] = + "smc91111.c:v1.0 04/25/01 by Daris A Nevil (dnevil@snmc.com)\n"; +#endif + +/* Autonegotiation timeout in seconds */ +#ifndef CONFIG_SMC_AUTONEG_TIMEOUT +#define CONFIG_SMC_AUTONEG_TIMEOUT 10 +#endif + +/*------------------------------------------------------------------------ + . + . Configuration options, for the experienced user to change. + . + -------------------------------------------------------------------------*/ + +/* + . Wait time for memory to be free. This probably shouldn't be + . tuned that much, as waiting for this means nothing else happens + . in the system +*/ +#define MEMORY_WAIT_TIME 16 + + +#if (SMC_DEBUG > 2 ) +#define PRINTK3(args...) printf(args) +#else +#define PRINTK3(args...) +#endif + +#if SMC_DEBUG > 1 +#define PRINTK2(args...) printf(args) +#else +#define PRINTK2(args...) +#endif + +#ifdef SMC_DEBUG +#define PRINTK(args...) printf(args) +#else +#define PRINTK(args...) +#endif + + +/*------------------------------------------------------------------------ + . + . The internal workings of the driver. If you are changing anything + . here with the SMC stuff, you should have the datasheet and know + . what you are doing. + . + -------------------------------------------------------------------------*/ + +/* Memory sizing constant */ +#define LAN91C111_MEMORY_MULTIPLIER (1024*2) + +#ifndef CONFIG_SMC91111_BASE +#error "SMC91111 Base address must be passed to initialization funciton" +/* #define CONFIG_SMC91111_BASE 0x20000300 */ +#endif + +#define SMC_DEV_NAME "SMC91111" +#define SMC_PHY_ADDR 0x0000 +#define SMC_ALLOC_MAX_TRY 5 +#define SMC_TX_TIMEOUT 30 + +#define SMC_PHY_CLOCK_DELAY 1000 + +#define ETH_ZLEN 60 + +#ifdef CONFIG_SMC_USE_32_BIT +#define USE_32_BIT 1 +#else +#undef USE_32_BIT +#endif + +#ifdef SHARED_RESOURCES +extern void swap_to(int device_id); +#else +# define swap_to(x) +#endif + +#ifndef CONFIG_SMC91111_EXT_PHY +static void smc_phy_configure(struct eth_device *dev); +#endif /* !CONFIG_SMC91111_EXT_PHY */ + +/* + ------------------------------------------------------------ + . + . Internal routines + . + ------------------------------------------------------------ +*/ + +#ifdef CONFIG_SMC_USE_IOFUNCS +/* + * input and output functions + * + * Implemented due to inx,outx macros accessing the device improperly + * and putting the device into an unkown state. + * + * For instance, on Sharp LPD7A400 SDK, affects were chip memory + * could not be free'd (hence the alloc failures), duplicate packets, + * packets being corrupt (shifted) on the wire, etc. Switching to the + * inx,outx functions fixed this problem. + */ + +static inline word SMC_inw(struct eth_device *dev, dword offset) +{ + word v; + v = *((volatile word*)(dev->iobase + offset)); + barrier(); *(volatile u32*)(0xc0000000); + return v; +} + +static inline void SMC_outw(struct eth_device *dev, word value, dword offset) +{ + *((volatile word*)(dev->iobase + offset)) = value; + barrier(); *(volatile u32*)(0xc0000000); +} + +static inline byte SMC_inb(struct eth_device *dev, dword offset) +{ + word _w; + + _w = SMC_inw(dev, offset & ~((dword)1)); + return (offset & 1) ? (byte)(_w >> 8) : (byte)(_w); +} + +static inline void SMC_outb(struct eth_device *dev, byte value, dword offset) +{ + word _w; + + _w = SMC_inw(dev, offset & ~((dword)1)); + if (offset & 1) + *((volatile word*)(dev->iobase + (offset & ~((dword)1)))) = + (value<<8) | (_w & 0x00ff); + else + *((volatile word*)(dev->iobase + offset)) = + value | (_w & 0xff00); +} + +static inline void SMC_insw(struct eth_device *dev, dword offset, + volatile uchar* buf, dword len) +{ + volatile word *p = (volatile word *)buf; + + while (len-- > 0) { + *p++ = SMC_inw(dev, offset); + barrier(); + *((volatile u32*)(0xc0000000)); + } +} + +static inline void SMC_outsw(struct eth_device *dev, dword offset, + uchar* buf, dword len) +{ + volatile word *p = (volatile word *)buf; + + while (len-- > 0) { + SMC_outw(dev, *p++, offset); + barrier(); + *(volatile u32*)(0xc0000000); + } +} +#endif /* CONFIG_SMC_USE_IOFUNCS */ + +/* + . A rather simple routine to print out a packet for debugging purposes. +*/ +#if SMC_DEBUG > 2 +static void print_packet( byte *, int ); +#endif + +#define tx_done(dev) 1 + +static int poll4int (struct eth_device *dev, byte mask, int timeout) +{ + int tmo = get_timer (0) + timeout * CONFIG_SYS_HZ; + int is_timeout = 0; + word old_bank = SMC_inw (dev, BSR_REG); + + PRINTK2 ("Polling...\n"); + SMC_SELECT_BANK (dev, 2); + while ((SMC_inw (dev, SMC91111_INT_REG) & mask) == 0) { + if (get_timer (0) >= tmo) { + is_timeout = 1; + break; + } + } + + /* restore old bank selection */ + SMC_SELECT_BANK (dev, old_bank); + + if (is_timeout) + return 1; + else + return 0; +} + +/* Only one release command at a time, please */ +static inline void smc_wait_mmu_release_complete (struct eth_device *dev) +{ + int count = 0; + + /* assume bank 2 selected */ + while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) { + udelay (1); /* Wait until not busy */ + if (++count > 200) + break; + } +} + +/* + . Function: smc_reset( void ) + . Purpose: + . This sets the SMC91111 chip to its normal state, hopefully from whatever + . mess that any other DOS driver has put it in. + . + . Maybe I should reset more registers to defaults in here? SOFTRST should + . do that for me. + . + . Method: + . 1. send a SOFT RESET + . 2. wait for it to finish + . 3. enable autorelease mode + . 4. reset the memory management unit + . 5. clear all interrupts + . +*/ +static void smc_reset (struct eth_device *dev) +{ + PRINTK2 ("%s: smc_reset\n", SMC_DEV_NAME); + + /* This resets the registers mostly to defaults, but doesn't + affect EEPROM. That seems unnecessary */ + SMC_SELECT_BANK (dev, 0); + SMC_outw (dev, RCR_SOFTRST, RCR_REG); + + /* Setup the Configuration Register */ + /* This is necessary because the CONFIG_REG is not affected */ + /* by a soft reset */ + + SMC_SELECT_BANK (dev, 1); +#if defined(CONFIG_SMC91111_EXT_PHY) + SMC_outw (dev, CONFIG_DEFAULT | CONFIG_EXT_PHY, CONFIG_REG); +#else + SMC_outw (dev, CONFIG_DEFAULT, CONFIG_REG); +#endif + + + /* Release from possible power-down state */ + /* Configuration register is not affected by Soft Reset */ + SMC_outw (dev, SMC_inw (dev, CONFIG_REG) | CONFIG_EPH_POWER_EN, + CONFIG_REG); + + SMC_SELECT_BANK (dev, 0); + + /* this should pause enough for the chip to be happy */ + udelay (10); + + /* Disable transmit and receive functionality */ + SMC_outw (dev, RCR_CLEAR, RCR_REG); + SMC_outw (dev, TCR_CLEAR, TCR_REG); + + /* set the control register */ + SMC_SELECT_BANK (dev, 1); + SMC_outw (dev, CTL_DEFAULT, CTL_REG); + + /* Reset the MMU */ + SMC_SELECT_BANK (dev, 2); + smc_wait_mmu_release_complete (dev); + SMC_outw (dev, MC_RESET, MMU_CMD_REG); + while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) + udelay (1); /* Wait until not busy */ + + /* Note: It doesn't seem that waiting for the MMU busy is needed here, + but this is a place where future chipsets _COULD_ break. Be wary + of issuing another MMU command right after this */ + + /* Disable all interrupts */ + SMC_outb (dev, 0, IM_REG); +} + +/* + . Function: smc_enable + . Purpose: let the chip talk to the outside work + . Method: + . 1. Enable the transmitter + . 2. Enable the receiver + . 3. Enable interrupts +*/ +static void smc_enable(struct eth_device *dev) +{ + PRINTK2("%s: smc_enable\n", SMC_DEV_NAME); + SMC_SELECT_BANK( dev, 0 ); + /* see the header file for options in TCR/RCR DEFAULT*/ + SMC_outw( dev, TCR_DEFAULT, TCR_REG ); + SMC_outw( dev, RCR_DEFAULT, RCR_REG ); + + /* clear MII_DIS */ +/* smc_write_phy_register(PHY_CNTL_REG, 0x0000); */ +} + +/* + . Function: smc_halt + . Purpose: closes down the SMC91xxx chip. + . Method: + . 1. zero the interrupt mask + . 2. clear the enable receive flag + . 3. clear the enable xmit flags + . + . TODO: + . (1) maybe utilize power down mode. + . Why not yet? Because while the chip will go into power down mode, + . the manual says that it will wake up in response to any I/O requests + . in the register space. Empirical results do not show this working. +*/ +static void smc_halt(struct eth_device *dev) +{ + PRINTK2("%s: smc_halt\n", SMC_DEV_NAME); + + /* no more interrupts for me */ + SMC_SELECT_BANK( dev, 2 ); + SMC_outb( dev, 0, IM_REG ); + + /* and tell the card to stay away from that nasty outside world */ + SMC_SELECT_BANK( dev, 0 ); + SMC_outb( dev, RCR_CLEAR, RCR_REG ); + SMC_outb( dev, TCR_CLEAR, TCR_REG ); + + swap_to(FLASH); +} + + +/* + . Function: smc_send(struct net_device * ) + . Purpose: + . This sends the actual packet to the SMC9xxx chip. + . + . Algorithm: + . First, see if a saved_skb is available. + . ( this should NOT be called if there is no 'saved_skb' + . Now, find the packet number that the chip allocated + . Point the data pointers at it in memory + . Set the length word in the chip's memory + . Dump the packet to chip memory + . Check if a last byte is needed ( odd length packet ) + . if so, set the control flag right + . Tell the card to send it + . Enable the transmit interrupt, so I know if it failed + . Free the kernel data if I actually sent it. +*/ +static int smc_send(struct eth_device *dev, void *packet, int packet_length) +{ + byte packet_no; + byte *buf; + int length; + int numPages; + int try = 0; + int time_out; + byte status; + byte saved_pnr; + word saved_ptr; + + /* save PTR and PNR registers before manipulation */ + SMC_SELECT_BANK (dev, 2); + saved_pnr = SMC_inb( dev, PN_REG ); + saved_ptr = SMC_inw( dev, PTR_REG ); + + PRINTK3 ("%s: smc_hardware_send_packet\n", SMC_DEV_NAME); + + length = ETH_ZLEN < packet_length ? packet_length : ETH_ZLEN; + + /* allocate memory + ** The MMU wants the number of pages to be the number of 256 bytes + ** 'pages', minus 1 ( since a packet can't ever have 0 pages :) ) + ** + ** The 91C111 ignores the size bits, but the code is left intact + ** for backwards and future compatibility. + ** + ** Pkt size for allocating is data length +6 (for additional status + ** words, length and ctl!) + ** + ** If odd size then last byte is included in this header. + */ + numPages = ((length & 0xfffe) + 6); + numPages >>= 8; /* Divide by 256 */ + + if (numPages > 7) { + printf ("%s: Far too big packet error. \n", SMC_DEV_NAME); + return 0; + } + + /* now, try to allocate the memory */ + SMC_SELECT_BANK (dev, 2); + SMC_outw (dev, MC_ALLOC | numPages, MMU_CMD_REG); + + /* FIXME: the ALLOC_INT bit never gets set * + * so the following will always give a * + * memory allocation error. * + * same code works in armboot though * + * -ro + */ + +again: + try++; + time_out = MEMORY_WAIT_TIME; + do { + status = SMC_inb (dev, SMC91111_INT_REG); + if (status & IM_ALLOC_INT) { + /* acknowledge the interrupt */ + SMC_outb (dev, IM_ALLOC_INT, SMC91111_INT_REG); + break; + } + } while (--time_out); + + if (!time_out) { + PRINTK2 ("%s: memory allocation, try %d failed ...\n", + SMC_DEV_NAME, try); + if (try < SMC_ALLOC_MAX_TRY) + goto again; + else + return 0; + } + + PRINTK2 ("%s: memory allocation, try %d succeeded ...\n", + SMC_DEV_NAME, try); + + buf = (byte *) packet; + + /* If I get here, I _know_ there is a packet slot waiting for me */ + packet_no = SMC_inb (dev, AR_REG); + if (packet_no & AR_FAILED) { + /* or isn't there? BAD CHIP! */ + printf ("%s: Memory allocation failed. \n", SMC_DEV_NAME); + return 0; + } + + /* we have a packet address, so tell the card to use it */ + SMC_outb (dev, packet_no, PN_REG); + + /* do not write new ptr value if Write data fifo not empty */ + while ( saved_ptr & PTR_NOTEMPTY ) + printf ("Write data fifo not empty!\n"); + + /* point to the beginning of the packet */ + SMC_outw (dev, PTR_AUTOINC, PTR_REG); + + PRINTK3 ("%s: Trying to xmit packet of length %x\n", + SMC_DEV_NAME, length); + +#if SMC_DEBUG > 2 + printf ("Transmitting Packet\n"); + print_packet (buf, length); +#endif + + /* send the packet length ( +6 for status, length and ctl byte ) + and the status word ( set to zeros ) */ +#ifdef USE_32_BIT + SMC_outl (dev, (length + 6) << 16, SMC91111_DATA_REG); +#else + SMC_outw (dev, 0, SMC91111_DATA_REG); + /* send the packet length ( +6 for status words, length, and ctl */ + SMC_outw (dev, (length + 6), SMC91111_DATA_REG); +#endif + + /* send the actual data + . I _think_ it's faster to send the longs first, and then + . mop up by sending the last word. It depends heavily + . on alignment, at least on the 486. Maybe it would be + . a good idea to check which is optimal? But that could take + . almost as much time as is saved? + */ +#ifdef USE_32_BIT + SMC_outsl (dev, SMC91111_DATA_REG, buf, length >> 2); + if (length & 0x2) + SMC_outw (dev, *((word *) (buf + (length & 0xFFFFFFFC))), + SMC91111_DATA_REG); +#else + SMC_outsw (dev, SMC91111_DATA_REG, buf, (length) >> 1); +#endif /* USE_32_BIT */ + + /* Send the last byte, if there is one. */ + if ((length & 1) == 0) { + SMC_outw (dev, 0, SMC91111_DATA_REG); + } else { + SMC_outw (dev, buf[length - 1] | 0x2000, SMC91111_DATA_REG); + } + + /* and let the chipset deal with it */ + SMC_outw (dev, MC_ENQUEUE, MMU_CMD_REG); + + /* poll for TX INT */ + /* if (poll4int (dev, IM_TX_INT, SMC_TX_TIMEOUT)) { */ + /* poll for TX_EMPTY INT - autorelease enabled */ + if (poll4int(dev, IM_TX_EMPTY_INT, SMC_TX_TIMEOUT)) { + /* sending failed */ + PRINTK2 ("%s: TX timeout, sending failed...\n", SMC_DEV_NAME); + + /* release packet */ + /* no need to release, MMU does that now */ + + /* wait for MMU getting ready (low) */ + while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) { + udelay (10); + } + + PRINTK2 ("MMU ready\n"); + + + return 0; + } else { + /* ack. int */ + SMC_outb (dev, IM_TX_EMPTY_INT, SMC91111_INT_REG); + /* SMC_outb (IM_TX_INT, SMC91111_INT_REG); */ + PRINTK2 ("%s: Sent packet of length %d \n", SMC_DEV_NAME, + length); + + /* release packet */ + /* no need to release, MMU does that now */ + + /* wait for MMU getting ready (low) */ + while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) { + udelay (10); + } + + PRINTK2 ("MMU ready\n"); + + + } + + /* restore previously saved registers */ + SMC_outb( dev, saved_pnr, PN_REG ); + SMC_outw( dev, saved_ptr, PTR_REG ); + + return length; +} + +static int smc_write_hwaddr(struct eth_device *dev) +{ + int i; + + swap_to(ETHERNET); + SMC_SELECT_BANK (dev, 1); +#ifdef USE_32_BIT + for (i = 0; i < 6; i += 2) { + word address; + + address = dev->enetaddr[i + 1] << 8; + address |= dev->enetaddr[i]; + SMC_outw(dev, address, (ADDR0_REG + i)); + } +#else + for (i = 0; i < 6; i++) + SMC_outb(dev, dev->enetaddr[i], (ADDR0_REG + i)); +#endif + swap_to(FLASH); + return 0; +} + +/* + * Open and Initialize the board + * + * Set up everything, reset the card, etc .. + * + */ +static int smc_init(struct eth_device *dev, bd_t *bd) +{ + swap_to(ETHERNET); + + PRINTK2 ("%s: smc_init\n", SMC_DEV_NAME); + + /* reset the hardware */ + smc_reset (dev); + smc_enable (dev); + + /* Configure the PHY */ +#ifndef CONFIG_SMC91111_EXT_PHY + smc_phy_configure (dev); +#endif + + /* conservative setting (10Mbps, HalfDuplex, no AutoNeg.) */ +/* SMC_SELECT_BANK(dev, 0); */ +/* SMC_outw(dev, 0, RPC_REG); */ + + printf(SMC_DEV_NAME ": MAC %pM\n", dev->enetaddr); + + return 0; +} + +/*------------------------------------------------------------- + . + . smc_rcv - receive a packet from the card + . + . There is ( at least ) a packet waiting to be read from + . chip-memory. + . + . o Read the status + . o If an error, record it + . o otherwise, read in the packet + -------------------------------------------------------------- +*/ +static int smc_rcv(struct eth_device *dev) +{ + int packet_number; + word status; + word packet_length; + int is_error = 0; +#ifdef USE_32_BIT + dword stat_len; +#endif + byte saved_pnr; + word saved_ptr; + + SMC_SELECT_BANK(dev, 2); + /* save PTR and PTR registers */ + saved_pnr = SMC_inb( dev, PN_REG ); + saved_ptr = SMC_inw( dev, PTR_REG ); + + packet_number = SMC_inw( dev, RXFIFO_REG ); + + if ( packet_number & RXFIFO_REMPTY ) { + + return 0; + } + + PRINTK3("%s: smc_rcv\n", SMC_DEV_NAME); + /* start reading from the start of the packet */ + SMC_outw( dev, PTR_READ | PTR_RCV | PTR_AUTOINC, PTR_REG ); + + /* First two words are status and packet_length */ +#ifdef USE_32_BIT + stat_len = SMC_inl(dev, SMC91111_DATA_REG); + status = stat_len & 0xffff; + packet_length = stat_len >> 16; +#else + status = SMC_inw( dev, SMC91111_DATA_REG ); + packet_length = SMC_inw( dev, SMC91111_DATA_REG ); +#endif + + packet_length &= 0x07ff; /* mask off top bits */ + + PRINTK2("RCV: STATUS %4x LENGTH %4x\n", status, packet_length ); + + if ( !(status & RS_ERRORS ) ){ + /* Adjust for having already read the first two words */ + packet_length -= 4; /*4; */ + + + /* set odd length for bug in LAN91C111, */ + /* which never sets RS_ODDFRAME */ + /* TODO ? */ + + +#ifdef USE_32_BIT + PRINTK3(" Reading %d dwords (and %d bytes)\n", + packet_length >> 2, packet_length & 3 ); + /* QUESTION: Like in the TX routine, do I want + to send the DWORDs or the bytes first, or some + mixture. A mixture might improve already slow PIO + performance */ + SMC_insl(dev, SMC91111_DATA_REG, net_rx_packets[0], + packet_length >> 2); + /* read the left over bytes */ + if (packet_length & 3) { + int i; + + byte *tail = (byte *)(net_rx_packets[0] + + (packet_length & ~3)); + dword leftover = SMC_inl(dev, SMC91111_DATA_REG); + for (i=0; i<(packet_length & 3); i++) + *tail++ = (byte) (leftover >> (8*i)) & 0xff; + } +#else + PRINTK3(" Reading %d words and %d byte(s)\n", + (packet_length >> 1 ), packet_length & 1 ); + SMC_insw(dev, SMC91111_DATA_REG , net_rx_packets[0], + packet_length >> 1); + +#endif /* USE_32_BIT */ + +#if SMC_DEBUG > 2 + printf("Receiving Packet\n"); + print_packet(net_rx_packets[0], packet_length); +#endif + } else { + /* error ... */ + /* TODO ? */ + is_error = 1; + } + + while ( SMC_inw( dev, MMU_CMD_REG ) & MC_BUSY ) + udelay(1); /* Wait until not busy */ + + /* error or good, tell the card to get rid of this packet */ + SMC_outw( dev, MC_RELEASE, MMU_CMD_REG ); + + while ( SMC_inw( dev, MMU_CMD_REG ) & MC_BUSY ) + udelay(1); /* Wait until not busy */ + + /* restore saved registers */ + SMC_outb( dev, saved_pnr, PN_REG ); + SMC_outw( dev, saved_ptr, PTR_REG ); + + if (!is_error) { + /* Pass the packet up to the protocol layers. */ + net_process_received_packet(net_rx_packets[0], packet_length); + return packet_length; + } else { + return 0; + } + +} + + +#if 0 +/*------------------------------------------------------------ + . Modify a bit in the LAN91C111 register set + .-------------------------------------------------------------*/ +static word smc_modify_regbit(struct eth_device *dev, int bank, int ioaddr, int reg, + unsigned int bit, int val) +{ + word regval; + + SMC_SELECT_BANK( dev, bank ); + + regval = SMC_inw( dev, reg ); + if (val) + regval |= bit; + else + regval &= ~bit; + + SMC_outw( dev, regval, 0 ); + return(regval); +} + + +/*------------------------------------------------------------ + . Retrieve a bit in the LAN91C111 register set + .-------------------------------------------------------------*/ +static int smc_get_regbit(struct eth_device *dev, int bank, int ioaddr, int reg, unsigned int bit) +{ + SMC_SELECT_BANK( dev, bank ); + if ( SMC_inw( dev, reg ) & bit) + return(1); + else + return(0); +} + + +/*------------------------------------------------------------ + . Modify a LAN91C111 register (word access only) + .-------------------------------------------------------------*/ +static void smc_modify_reg(struct eth_device *dev, int bank, int ioaddr, int reg, word val) +{ + SMC_SELECT_BANK( dev, bank ); + SMC_outw( dev, val, reg ); +} + + +/*------------------------------------------------------------ + . Retrieve a LAN91C111 register (word access only) + .-------------------------------------------------------------*/ +static int smc_get_reg(struct eth_device *dev, int bank, int ioaddr, int reg) +{ + SMC_SELECT_BANK( dev, bank ); + return(SMC_inw( dev, reg )); +} + +#endif /* 0 */ + +/*---PHY CONTROL AND CONFIGURATION----------------------------------------- */ + +#if (SMC_DEBUG > 2 ) + +/*------------------------------------------------------------ + . Debugging function for viewing MII Management serial bitstream + .-------------------------------------------------------------*/ +static void smc_dump_mii_stream (byte * bits, int size) +{ + int i; + + printf ("BIT#:"); + for (i = 0; i < size; ++i) { + printf ("%d", i % 10); + } + + printf ("\nMDOE:"); + for (i = 0; i < size; ++i) { + if (bits[i] & MII_MDOE) + printf ("1"); + else + printf ("0"); + } + + printf ("\nMDO :"); + for (i = 0; i < size; ++i) { + if (bits[i] & MII_MDO) + printf ("1"); + else + printf ("0"); + } + + printf ("\nMDI :"); + for (i = 0; i < size; ++i) { + if (bits[i] & MII_MDI) + printf ("1"); + else + printf ("0"); + } + + printf ("\n"); +} +#endif + +/*------------------------------------------------------------ + . Reads a register from the MII Management serial interface + .-------------------------------------------------------------*/ +#ifndef CONFIG_SMC91111_EXT_PHY +static word smc_read_phy_register (struct eth_device *dev, byte phyreg) +{ + int oldBank; + int i; + byte mask; + word mii_reg; + byte bits[64]; + int clk_idx = 0; + int input_idx; + word phydata; + byte phyaddr = SMC_PHY_ADDR; + + /* 32 consecutive ones on MDO to establish sync */ + for (i = 0; i < 32; ++i) + bits[clk_idx++] = MII_MDOE | MII_MDO; + + /* Start code <01> */ + bits[clk_idx++] = MII_MDOE; + bits[clk_idx++] = MII_MDOE | MII_MDO; + + /* Read command <10> */ + bits[clk_idx++] = MII_MDOE | MII_MDO; + bits[clk_idx++] = MII_MDOE; + + /* Output the PHY address, msb first */ + mask = (byte) 0x10; + for (i = 0; i < 5; ++i) { + if (phyaddr & mask) + bits[clk_idx++] = MII_MDOE | MII_MDO; + else + bits[clk_idx++] = MII_MDOE; + + /* Shift to next lowest bit */ + mask >>= 1; + } + + /* Output the phy register number, msb first */ + mask = (byte) 0x10; + for (i = 0; i < 5; ++i) { + if (phyreg & mask) + bits[clk_idx++] = MII_MDOE | MII_MDO; + else + bits[clk_idx++] = MII_MDOE; + + /* Shift to next lowest bit */ + mask >>= 1; + } + + /* Tristate and turnaround (2 bit times) */ + bits[clk_idx++] = 0; + /*bits[clk_idx++] = 0; */ + + /* Input starts at this bit time */ + input_idx = clk_idx; + + /* Will input 16 bits */ + for (i = 0; i < 16; ++i) + bits[clk_idx++] = 0; + + /* Final clock bit */ + bits[clk_idx++] = 0; + + /* Save the current bank */ + oldBank = SMC_inw (dev, BANK_SELECT); + + /* Select bank 3 */ + SMC_SELECT_BANK (dev, 3); + + /* Get the current MII register value */ + mii_reg = SMC_inw (dev, MII_REG); + + /* Turn off all MII Interface bits */ + mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO); + + /* Clock all 64 cycles */ + for (i = 0; i < sizeof bits; ++i) { + /* Clock Low - output data */ + SMC_outw (dev, mii_reg | bits[i], MII_REG); + udelay (SMC_PHY_CLOCK_DELAY); + + + /* Clock Hi - input data */ + SMC_outw (dev, mii_reg | bits[i] | MII_MCLK, MII_REG); + udelay (SMC_PHY_CLOCK_DELAY); + bits[i] |= SMC_inw (dev, MII_REG) & MII_MDI; + } + + /* Return to idle state */ + /* Set clock to low, data to low, and output tristated */ + SMC_outw (dev, mii_reg, MII_REG); + udelay (SMC_PHY_CLOCK_DELAY); + + /* Restore original bank select */ + SMC_SELECT_BANK (dev, oldBank); + + /* Recover input data */ + phydata = 0; + for (i = 0; i < 16; ++i) { + phydata <<= 1; + + if (bits[input_idx++] & MII_MDI) + phydata |= 0x0001; + } + +#if (SMC_DEBUG > 2 ) + printf ("smc_read_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n", + phyaddr, phyreg, phydata); + smc_dump_mii_stream (bits, sizeof bits); +#endif + + return (phydata); +} + + +/*------------------------------------------------------------ + . Writes a register to the MII Management serial interface + .-------------------------------------------------------------*/ +static void smc_write_phy_register (struct eth_device *dev, byte phyreg, + word phydata) +{ + int oldBank; + int i; + word mask; + word mii_reg; + byte bits[65]; + int clk_idx = 0; + byte phyaddr = SMC_PHY_ADDR; + + /* 32 consecutive ones on MDO to establish sync */ + for (i = 0; i < 32; ++i) + bits[clk_idx++] = MII_MDOE | MII_MDO; + + /* Start code <01> */ + bits[clk_idx++] = MII_MDOE; + bits[clk_idx++] = MII_MDOE | MII_MDO; + + /* Write command <01> */ + bits[clk_idx++] = MII_MDOE; + bits[clk_idx++] = MII_MDOE | MII_MDO; + + /* Output the PHY address, msb first */ + mask = (byte) 0x10; + for (i = 0; i < 5; ++i) { + if (phyaddr & mask) + bits[clk_idx++] = MII_MDOE | MII_MDO; + else + bits[clk_idx++] = MII_MDOE; + + /* Shift to next lowest bit */ + mask >>= 1; + } + + /* Output the phy register number, msb first */ + mask = (byte) 0x10; + for (i = 0; i < 5; ++i) { + if (phyreg & mask) + bits[clk_idx++] = MII_MDOE | MII_MDO; + else + bits[clk_idx++] = MII_MDOE; + + /* Shift to next lowest bit */ + mask >>= 1; + } + + /* Tristate and turnaround (2 bit times) */ + bits[clk_idx++] = 0; + bits[clk_idx++] = 0; + + /* Write out 16 bits of data, msb first */ + mask = 0x8000; + for (i = 0; i < 16; ++i) { + if (phydata & mask) + bits[clk_idx++] = MII_MDOE | MII_MDO; + else + bits[clk_idx++] = MII_MDOE; + + /* Shift to next lowest bit */ + mask >>= 1; + } + + /* Final clock bit (tristate) */ + bits[clk_idx++] = 0; + + /* Save the current bank */ + oldBank = SMC_inw (dev, BANK_SELECT); + + /* Select bank 3 */ + SMC_SELECT_BANK (dev, 3); + + /* Get the current MII register value */ + mii_reg = SMC_inw (dev, MII_REG); + + /* Turn off all MII Interface bits */ + mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO); + + /* Clock all cycles */ + for (i = 0; i < sizeof bits; ++i) { + /* Clock Low - output data */ + SMC_outw (dev, mii_reg | bits[i], MII_REG); + udelay (SMC_PHY_CLOCK_DELAY); + + + /* Clock Hi - input data */ + SMC_outw (dev, mii_reg | bits[i] | MII_MCLK, MII_REG); + udelay (SMC_PHY_CLOCK_DELAY); + bits[i] |= SMC_inw (dev, MII_REG) & MII_MDI; + } + + /* Return to idle state */ + /* Set clock to low, data to low, and output tristated */ + SMC_outw (dev, mii_reg, MII_REG); + udelay (SMC_PHY_CLOCK_DELAY); + + /* Restore original bank select */ + SMC_SELECT_BANK (dev, oldBank); + +#if (SMC_DEBUG > 2 ) + printf ("smc_write_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n", + phyaddr, phyreg, phydata); + smc_dump_mii_stream (bits, sizeof bits); +#endif +} +#endif /* !CONFIG_SMC91111_EXT_PHY */ + + +/*------------------------------------------------------------ + . Configures the specified PHY using Autonegotiation. Calls + . smc_phy_fixed() if the user has requested a certain config. + .-------------------------------------------------------------*/ +#ifndef CONFIG_SMC91111_EXT_PHY +static void smc_phy_configure (struct eth_device *dev) +{ + int timeout; + word my_phy_caps; /* My PHY capabilities */ + word my_ad_caps; /* My Advertised capabilities */ + word status = 0; /*;my status = 0 */ + + PRINTK3 ("%s: smc_program_phy()\n", SMC_DEV_NAME); + + /* Reset the PHY, setting all other bits to zero */ + smc_write_phy_register (dev, PHY_CNTL_REG, PHY_CNTL_RST); + + /* Wait for the reset to complete, or time out */ + timeout = 6; /* Wait up to 3 seconds */ + while (timeout--) { + if (!(smc_read_phy_register (dev, PHY_CNTL_REG) + & PHY_CNTL_RST)) { + /* reset complete */ + break; + } + + mdelay(500); /* wait 500 millisecs */ + } + + if (timeout < 1) { + printf ("%s:PHY reset timed out\n", SMC_DEV_NAME); + goto smc_phy_configure_exit; + } + + /* Read PHY Register 18, Status Output */ + /* lp->lastPhy18 = smc_read_phy_register(PHY_INT_REG); */ + + /* Enable PHY Interrupts (for register 18) */ + /* Interrupts listed here are disabled */ + smc_write_phy_register (dev, PHY_MASK_REG, 0xffff); + + /* Configure the Receive/Phy Control register */ + SMC_SELECT_BANK (dev, 0); + SMC_outw (dev, RPC_DEFAULT, RPC_REG); + + /* Copy our capabilities from PHY_STAT_REG to PHY_AD_REG */ + my_phy_caps = smc_read_phy_register (dev, PHY_STAT_REG); + my_ad_caps = PHY_AD_CSMA; /* I am CSMA capable */ + + if (my_phy_caps & PHY_STAT_CAP_T4) + my_ad_caps |= PHY_AD_T4; + + if (my_phy_caps & PHY_STAT_CAP_TXF) + my_ad_caps |= PHY_AD_TX_FDX; + + if (my_phy_caps & PHY_STAT_CAP_TXH) + my_ad_caps |= PHY_AD_TX_HDX; + + if (my_phy_caps & PHY_STAT_CAP_TF) + my_ad_caps |= PHY_AD_10_FDX; + + if (my_phy_caps & PHY_STAT_CAP_TH) + my_ad_caps |= PHY_AD_10_HDX; + + /* Update our Auto-Neg Advertisement Register */ + smc_write_phy_register (dev, PHY_AD_REG, my_ad_caps); + + /* Read the register back. Without this, it appears that when */ + /* auto-negotiation is restarted, sometimes it isn't ready and */ + /* the link does not come up. */ + smc_read_phy_register(dev, PHY_AD_REG); + + PRINTK2 ("%s: phy caps=%x\n", SMC_DEV_NAME, my_phy_caps); + PRINTK2 ("%s: phy advertised caps=%x\n", SMC_DEV_NAME, my_ad_caps); + + /* Restart auto-negotiation process in order to advertise my caps */ + smc_write_phy_register (dev, PHY_CNTL_REG, + PHY_CNTL_ANEG_EN | PHY_CNTL_ANEG_RST); + + /* Wait for the auto-negotiation to complete. This may take from */ + /* 2 to 3 seconds. */ + /* Wait for the reset to complete, or time out */ + timeout = CONFIG_SMC_AUTONEG_TIMEOUT * 2; + while (timeout--) { + + status = smc_read_phy_register (dev, PHY_STAT_REG); + if (status & PHY_STAT_ANEG_ACK) { + /* auto-negotiate complete */ + break; + } + + mdelay(500); /* wait 500 millisecs */ + + /* Restart auto-negotiation if remote fault */ + if (status & PHY_STAT_REM_FLT) { + printf ("%s: PHY remote fault detected\n", + SMC_DEV_NAME); + + /* Restart auto-negotiation */ + printf ("%s: PHY restarting auto-negotiation\n", + SMC_DEV_NAME); + smc_write_phy_register (dev, PHY_CNTL_REG, + PHY_CNTL_ANEG_EN | + PHY_CNTL_ANEG_RST | + PHY_CNTL_SPEED | + PHY_CNTL_DPLX); + } + } + + if (timeout < 1) { + printf ("%s: PHY auto-negotiate timed out\n", SMC_DEV_NAME); + } + + /* Fail if we detected an auto-negotiate remote fault */ + if (status & PHY_STAT_REM_FLT) { + printf ("%s: PHY remote fault detected\n", SMC_DEV_NAME); + } + + /* Re-Configure the Receive/Phy Control register */ + SMC_outw (dev, RPC_DEFAULT, RPC_REG); + +smc_phy_configure_exit: ; + +} +#endif /* !CONFIG_SMC91111_EXT_PHY */ + + +#if SMC_DEBUG > 2 +static void print_packet( byte * buf, int length ) +{ + int i; + int remainder; + int lines; + + printf("Packet of length %d \n", length ); + +#if SMC_DEBUG > 3 + lines = length / 16; + remainder = length % 16; + + for ( i = 0; i < lines ; i ++ ) { + int cur; + + for ( cur = 0; cur < 8; cur ++ ) { + byte a, b; + + a = *(buf ++ ); + b = *(buf ++ ); + printf("%02x%02x ", a, b ); + } + printf("\n"); + } + for ( i = 0; i < remainder/2 ; i++ ) { + byte a, b; + + a = *(buf ++ ); + b = *(buf ++ ); + printf("%02x%02x ", a, b ); + } + printf("\n"); +#endif +} +#endif + +int smc91111_initialize(u8 dev_num, int base_addr) +{ + struct smc91111_priv *priv; + struct eth_device *dev; + int i; + + priv = malloc(sizeof(*priv)); + if (!priv) + return 0; + dev = malloc(sizeof(*dev)); + if (!dev) { + free(priv); + return 0; + } + + memset(dev, 0, sizeof(*dev)); + priv->dev_num = dev_num; + dev->priv = priv; + dev->iobase = base_addr; + + swap_to(ETHERNET); + SMC_SELECT_BANK(dev, 1); + for (i = 0; i < 6; ++i) + dev->enetaddr[i] = SMC_inb(dev, (ADDR0_REG + i)); + swap_to(FLASH); + + dev->init = smc_init; + dev->halt = smc_halt; + dev->send = smc_send; + dev->recv = smc_rcv; + dev->write_hwaddr = smc_write_hwaddr; + sprintf(dev->name, "%s-%hu", SMC_DEV_NAME, dev_num); + + eth_register(dev); + return 0; +} diff --git a/sources/uboot-be550/drivers/net/smc91111.h b/sources/uboot-be550/drivers/net/smc91111.h new file mode 100644 index 00000000..5197f360 --- /dev/null +++ b/sources/uboot-be550/drivers/net/smc91111.h @@ -0,0 +1,796 @@ +/*------------------------------------------------------------------------ + . smc91111.h - macros for the LAN91C111 Ethernet Driver + . + . (C) Copyright 2002 + . Sysgo Real-Time Solutions, GmbH + . Rolf Offermanns + . Copyright (C) 2001 Standard Microsystems Corporation (SMSC) + . Developed by Simple Network Magic Corporation (SNMC) + . Copyright (C) 1996 by Erik Stahlman (ES) + . + * SPDX-License-Identifier: GPL-2.0+ + . + . This file contains register information and access macros for + . the LAN91C111 single chip ethernet controller. It is a modified + . version of the smc9194.h file. + . + . Information contained in this file was obtained from the LAN91C111 + . manual from SMC. To get a copy, if you really want one, you can find + . information under www.smsc.com. + . + . Authors + . Erik Stahlman ( erik@vt.edu ) + . Daris A Nevil ( dnevil@snmc.com ) + . + . History + . 03/16/01 Daris A Nevil Modified for use with LAN91C111 device + . + ---------------------------------------------------------------------------*/ +#ifndef _SMC91111_H_ +#define _SMC91111_H_ + +#include +#include + +/* + * This function may be called by the board specific initialisation code + * in order to override the default mac address. + */ + +void smc_set_mac_addr (const unsigned char *addr); + + +/* I want some simple types */ + +typedef unsigned char byte; +typedef unsigned short word; +typedef unsigned long int dword; + +struct smc91111_priv{ + u8 dev_num; +}; + +/* + . DEBUGGING LEVELS + . + . 0 for normal operation + . 1 for slightly more details + . >2 for various levels of increasingly useless information + . 2 for interrupt tracking, status flags + . 3 for packet info + . 4 for complete packet dumps +*/ +/*#define SMC_DEBUG 0 */ + +/* Because of bank switching, the LAN91xxx uses only 16 I/O ports */ + +#define SMC_IO_EXTENT 16 + +#ifdef CONFIG_CPU_PXA25X + +#ifdef CONFIG_XSENGINE +#define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+((r)<<1)))) +#define SMC_inw(a,r) (*((volatile word *)((a)->iobase+((r)<<1)))) +#define SMC_inb(a,p) ({ \ + unsigned int __p = (unsigned int)((a)->iobase + ((p)<<1)); \ + unsigned int __v = *(volatile unsigned short *)((__p) & ~2); \ + if (__p & 2) __v >>= 8; \ + else __v &= 0xff; \ + __v; }) +#else +#define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+(r)))) +#define SMC_inw(a,r) (*((volatile word *)((a)->iobase+(r)))) +#define SMC_inb(a,p) ({ \ + unsigned int __p = (unsigned int)((a)->iobase + (p)); \ + unsigned int __v = *(volatile unsigned short *)((__p) & ~1); \ + if (__p & 1) __v >>= 8; \ + else __v &= 0xff; \ + __v; }) +#endif + +#ifdef CONFIG_XSENGINE +#define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r<<1))) = d) +#define SMC_outw(a,d,r) (*((volatile word *)((a)->iobase+(r<<1))) = d) +#else +#define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r))) = d) +#define SMC_outw(a,d,r) (*((volatile word *)((a)->iobase+(r))) = d) +#endif + +#define SMC_outb(a,d,r) ({ word __d = (byte)(d); \ + word __w = SMC_inw((a),(r)&~1); \ + __w &= ((r)&1) ? 0x00FF : 0xFF00; \ + __w |= ((r)&1) ? __d<<8 : __d; \ + SMC_outw((a),__w,(r)&~1); \ + }) + +#define SMC_outsl(a,r,b,l) ({ int __i; \ + dword *__b2; \ + __b2 = (dword *) b; \ + for (__i = 0; __i < l; __i++) { \ + SMC_outl((a), *(__b2 + __i), r); \ + } \ + }) + +#define SMC_outsw(a,r,b,l) ({ int __i; \ + word *__b2; \ + __b2 = (word *) b; \ + for (__i = 0; __i < l; __i++) { \ + SMC_outw((a), *(__b2 + __i), r); \ + } \ + }) + +#define SMC_insl(a,r,b,l) ({ int __i ; \ + dword *__b2; \ + __b2 = (dword *) b; \ + for (__i = 0; __i < l; __i++) { \ + *(__b2 + __i) = SMC_inl((a),(r)); \ + SMC_inl((a),0); \ + }; \ + }) + +#define SMC_insw(a,r,b,l) ({ int __i ; \ + word *__b2; \ + __b2 = (word *) b; \ + for (__i = 0; __i < l; __i++) { \ + *(__b2 + __i) = SMC_inw((a),(r)); \ + SMC_inw((a),0); \ + }; \ + }) + +#define SMC_insb(a,r,b,l) ({ int __i ; \ + byte *__b2; \ + __b2 = (byte *) b; \ + for (__i = 0; __i < l; __i++) { \ + *(__b2 + __i) = SMC_inb((a),(r)); \ + SMC_inb((a),0); \ + }; \ + }) + +#elif defined(CONFIG_LEON) /* if not CONFIG_CPU_PXA25X */ + +#define SMC_LEON_SWAP16(_x_) ({ word _x = (_x_); ((_x << 8) | (_x >> 8)); }) + +#define SMC_LEON_SWAP32(_x_) \ + ({ dword _x = (_x_); \ + ((_x << 24) | \ + ((0x0000FF00UL & _x) << 8) | \ + ((0x00FF0000UL & _x) >> 8) | \ + (_x >> 24)); }) + +#define SMC_inl(a,r) (SMC_LEON_SWAP32((*(volatile dword *)((a)->iobase+((r)<<0))))) +#define SMC_inl_nosw(a,r) ((*(volatile dword *)((a)->iobase+((r)<<0)))) +#define SMC_inw(a,r) (SMC_LEON_SWAP16((*(volatile word *)((a)->iobase+((r)<<0))))) +#define SMC_inw_nosw(a,r) ((*(volatile word *)((a)->iobase+((r)<<0)))) +#define SMC_inb(a,p) ({ \ + word ___v = SMC_inw((a),(p) & ~1); \ + if ((p) & 1) ___v >>= 8; \ + else ___v &= 0xff; \ + ___v; }) + +#define SMC_outl(a,d,r) (*(volatile dword *)((a)->iobase+((r)<<0))=SMC_LEON_SWAP32(d)) +#define SMC_outl_nosw(a,d,r) (*(volatile dword *)((a)->iobase+((r)<<0))=(d)) +#define SMC_outw(a,d,r) (*(volatile word *)((a)->iobase+((r)<<0))=SMC_LEON_SWAP16(d)) +#define SMC_outw_nosw(a,d,r) (*(volatile word *)((a)->iobase+((r)<<0))=(d)) +#define SMC_outb(a,d,r) do{ word __d = (byte)(d); \ + word __w = SMC_inw((a),(r)&~1); \ + __w &= ((r)&1) ? 0x00FF : 0xFF00; \ + __w |= ((r)&1) ? __d<<8 : __d; \ + SMC_outw((a),__w,(r)&~1); \ + }while(0) +#define SMC_outsl(a,r,b,l) do{ int __i; \ + dword *__b2; \ + __b2 = (dword *) b; \ + for (__i = 0; __i < l; __i++) { \ + SMC_outl_nosw((a), *(__b2 + __i), r); \ + } \ + }while(0) +#define SMC_outsw(a,r,b,l) do{ int __i; \ + word *__b2; \ + __b2 = (word *) b; \ + for (__i = 0; __i < l; __i++) { \ + SMC_outw_nosw((a), *(__b2 + __i), r); \ + } \ + }while(0) +#define SMC_insl(a,r,b,l) do{ int __i ; \ + dword *__b2; \ + __b2 = (dword *) b; \ + for (__i = 0; __i < l; __i++) { \ + *(__b2 + __i) = SMC_inl_nosw((a),(r)); \ + }; \ + }while(0) + +#define SMC_insw(a,r,b,l) do{ int __i ; \ + word *__b2; \ + __b2 = (word *) b; \ + for (__i = 0; __i < l; __i++) { \ + *(__b2 + __i) = SMC_inw_nosw((a),(r)); \ + }; \ + }while(0) + +#define SMC_insb(a,r,b,l) do{ int __i ; \ + byte *__b2; \ + __b2 = (byte *) b; \ + for (__i = 0; __i < l; __i++) { \ + *(__b2 + __i) = SMC_inb((a),(r)); \ + }; \ + }while(0) +#elif defined(CONFIG_MS7206SE) +#define SWAB7206(x) ({ word __x = x; ((__x << 8)|(__x >> 8)); }) +#define SMC_inw(a, r) *((volatile word*)((a)->iobase + (r))) +#define SMC_inb(a, r) (*((volatile byte*)((a)->iobase + ((r) ^ 0x01)))) +#define SMC_insw(a, r, b, l) \ + do { \ + int __i; \ + word *__b2 = (word *)(b); \ + for (__i = 0; __i < (l); __i++) { \ + *__b2++ = SWAB7206(SMC_inw(a, r)); \ + } \ + } while (0) +#define SMC_outw(a, d, r) (*((volatile word *)((a)->iobase+(r))) = d) +#define SMC_outb(a, d, r) ({ word __d = (byte)(d); \ + word __w = SMC_inw((a), ((r)&(~1))); \ + if (((r) & 1)) \ + __w = (__w & 0x00ff) | (__d << 8); \ + else \ + __w = (__w & 0xff00) | (__d); \ + SMC_outw((a), __w, ((r)&(~1))); \ + }) +#define SMC_outsw(a, r, b, l) \ + do { \ + int __i; \ + word *__b2 = (word *)(b); \ + for (__i = 0; __i < (l); __i++) { \ + SMC_outw(a, SWAB7206(*__b2), r); \ + __b2++; \ + } \ + } while (0) +#else /* if not CONFIG_CPU_PXA25X and not CONFIG_LEON */ + +#ifndef CONFIG_SMC_USE_IOFUNCS /* these macros don't work on some boards */ +/* + * We have only 16 Bit PCMCIA access on Socket 0 + */ + +#ifdef CONFIG_ADNPESC1 +#define SMC_inw(a,r) (*((volatile word *)((a)->iobase+((r)<<1)))) +#elif CONFIG_BLACKFIN +#define SMC_inw(a,r) ({ word __v = (*((volatile word *)((a)->iobase+(r)))); SSYNC(); __v;}) +#elif CONFIG_ARM64 +#define SMC_inw(a, r) (*((volatile word*)((a)->iobase+((dword)(r))))) +#else +#define SMC_inw(a, r) (*((volatile word*)((a)->iobase+(r)))) +#endif +#define SMC_inb(a,r) (((r)&1) ? SMC_inw((a),(r)&~1)>>8 : SMC_inw((a),(r)&0xFF)) + +#ifdef CONFIG_ADNPESC1 +#define SMC_outw(a,d,r) (*((volatile word *)((a)->iobase+((r)<<1))) = d) +#elif CONFIG_BLACKFIN +#define SMC_outw(a, d, r) \ + ({ (*((volatile word*)((a)->iobase+((r)))) = d); \ + SSYNC(); \ + }) +#elif CONFIG_ARM64 +#define SMC_outw(a, d, r) \ + (*((volatile word*)((a)->iobase+((dword)(r)))) = d) +#else +#define SMC_outw(a, d, r) \ + (*((volatile word*)((a)->iobase+(r))) = d) +#endif +#define SMC_outb(a,d,r) ({ word __d = (byte)(d); \ + word __w = SMC_inw((a),(r)&~1); \ + __w &= ((r)&1) ? 0x00FF : 0xFF00; \ + __w |= ((r)&1) ? __d<<8 : __d; \ + SMC_outw((a),__w,(r)&~1); \ + }) +#if 0 +#define SMC_outsw(a,r,b,l) outsw((a)->iobase+(r), (b), (l)) +#else +#define SMC_outsw(a,r,b,l) ({ int __i; \ + word *__b2; \ + __b2 = (word *) b; \ + for (__i = 0; __i < l; __i++) { \ + SMC_outw((a), *(__b2 + __i), r); \ + } \ + }) +#endif + +#if 0 +#define SMC_insw(a,r,b,l) insw((a)->iobase+(r), (b), (l)) +#else +#define SMC_insw(a,r,b,l) ({ int __i ; \ + word *__b2; \ + __b2 = (word *) b; \ + for (__i = 0; __i < l; __i++) { \ + *(__b2 + __i) = SMC_inw((a),(r)); \ + SMC_inw((a),0); \ + }; \ + }) +#endif + +#endif /* CONFIG_SMC_USE_IOFUNCS */ + +#if defined(CONFIG_SMC_USE_32_BIT) + +#ifdef CONFIG_XSENGINE +#define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+(r<<1)))) +#else +#define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+(r)))) +#endif + +#define SMC_insl(a,r,b,l) ({ int __i ; \ + dword *__b2; \ + __b2 = (dword *) b; \ + for (__i = 0; __i < l; __i++) { \ + *(__b2 + __i) = SMC_inl((a),(r)); \ + SMC_inl((a),0); \ + }; \ + }) + +#ifdef CONFIG_XSENGINE +#define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r<<1))) = d) +#else +#define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r))) = d) +#endif +#define SMC_outsl(a,r,b,l) ({ int __i; \ + dword *__b2; \ + __b2 = (dword *) b; \ + for (__i = 0; __i < l; __i++) { \ + SMC_outl((a), *(__b2 + __i), r); \ + } \ + }) + +#endif /* CONFIG_SMC_USE_32_BIT */ + +#endif + +/*--------------------------------------------------------------- + . + . A description of the SMSC registers is probably in order here, + . although for details, the SMC datasheet is invaluable. + . + . Basically, the chip has 4 banks of registers ( 0 to 3 ), which + . are accessed by writing a number into the BANK_SELECT register + . ( I also use a SMC_SELECT_BANK macro for this ). + . + . The banks are configured so that for most purposes, bank 2 is all + . that is needed for simple run time tasks. + -----------------------------------------------------------------------*/ + +/* + . Bank Select Register: + . + . yyyy yyyy 0000 00xx + . xx = bank number + . yyyy yyyy = 0x33, for identification purposes. +*/ +#define BANK_SELECT 14 + +/* Transmit Control Register */ +/* BANK 0 */ +#define TCR_REG 0x0000 /* transmit control register */ +#define TCR_ENABLE 0x0001 /* When 1 we can transmit */ +#define TCR_LOOP 0x0002 /* Controls output pin LBK */ +#define TCR_FORCOL 0x0004 /* When 1 will force a collision */ +#define TCR_PAD_EN 0x0080 /* When 1 will pad tx frames < 64 bytes w/0 */ +#define TCR_NOCRC 0x0100 /* When 1 will not append CRC to tx frames */ +#define TCR_MON_CSN 0x0400 /* When 1 tx monitors carrier */ +#define TCR_FDUPLX 0x0800 /* When 1 enables full duplex operation */ +#define TCR_STP_SQET 0x1000 /* When 1 stops tx if Signal Quality Error */ +#define TCR_EPH_LOOP 0x2000 /* When 1 enables EPH block loopback */ +#define TCR_SWFDUP 0x8000 /* When 1 enables Switched Full Duplex mode */ + +#define TCR_CLEAR 0 /* do NOTHING */ +/* the default settings for the TCR register : */ +/* QUESTION: do I want to enable padding of short packets ? */ +#define TCR_DEFAULT TCR_ENABLE + + +/* EPH Status Register */ +/* BANK 0 */ +#define EPH_STATUS_REG 0x0002 +#define ES_TX_SUC 0x0001 /* Last TX was successful */ +#define ES_SNGL_COL 0x0002 /* Single collision detected for last tx */ +#define ES_MUL_COL 0x0004 /* Multiple collisions detected for last tx */ +#define ES_LTX_MULT 0x0008 /* Last tx was a multicast */ +#define ES_16COL 0x0010 /* 16 Collisions Reached */ +#define ES_SQET 0x0020 /* Signal Quality Error Test */ +#define ES_LTXBRD 0x0040 /* Last tx was a broadcast */ +#define ES_TXDEFR 0x0080 /* Transmit Deferred */ +#define ES_LATCOL 0x0200 /* Late collision detected on last tx */ +#define ES_LOSTCARR 0x0400 /* Lost Carrier Sense */ +#define ES_EXC_DEF 0x0800 /* Excessive Deferral */ +#define ES_CTR_ROL 0x1000 /* Counter Roll Over indication */ +#define ES_LINK_OK 0x4000 /* Driven by inverted value of nLNK pin */ +#define ES_TXUNRN 0x8000 /* Tx Underrun */ + + +/* Receive Control Register */ +/* BANK 0 */ +#define RCR_REG 0x0004 +#define RCR_RX_ABORT 0x0001 /* Set if a rx frame was aborted */ +#define RCR_PRMS 0x0002 /* Enable promiscuous mode */ +#define RCR_ALMUL 0x0004 /* When set accepts all multicast frames */ +#define RCR_RXEN 0x0100 /* IFF this is set, we can receive packets */ +#define RCR_STRIP_CRC 0x0200 /* When set strips CRC from rx packets */ +#define RCR_ABORT_ENB 0x0200 /* When set will abort rx on collision */ +#define RCR_FILT_CAR 0x0400 /* When set filters leading 12 bit s of carrier */ +#define RCR_SOFTRST 0x8000 /* resets the chip */ + +/* the normal settings for the RCR register : */ +#define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN) +#define RCR_CLEAR 0x0 /* set it to a base state */ + +/* Counter Register */ +/* BANK 0 */ +#define COUNTER_REG 0x0006 + +/* Memory Information Register */ +/* BANK 0 */ +#define MIR_REG 0x0008 + +/* Receive/Phy Control Register */ +/* BANK 0 */ +#define RPC_REG 0x000A +#define RPC_SPEED 0x2000 /* When 1 PHY is in 100Mbps mode. */ +#define RPC_DPLX 0x1000 /* When 1 PHY is in Full-Duplex Mode */ +#define RPC_ANEG 0x0800 /* When 1 PHY is in Auto-Negotiate Mode */ +#define RPC_LSXA_SHFT 5 /* Bits to shift LS2A,LS1A,LS0A to lsb */ +#define RPC_LSXB_SHFT 2 /* Bits to get LS2B,LS1B,LS0B to lsb */ +#define RPC_LED_100_10 (0x00) /* LED = 100Mbps OR's with 10Mbps link detect */ +#define RPC_LED_RES (0x01) /* LED = Reserved */ +#define RPC_LED_10 (0x02) /* LED = 10Mbps link detect */ +#define RPC_LED_FD (0x03) /* LED = Full Duplex Mode */ +#define RPC_LED_TX_RX (0x04) /* LED = TX or RX packet occurred */ +#define RPC_LED_100 (0x05) /* LED = 100Mbps link dectect */ +#define RPC_LED_TX (0x06) /* LED = TX packet occurred */ +#define RPC_LED_RX (0x07) /* LED = RX packet occurred */ +#if defined(CONFIG_DK1C20) || defined(CONFIG_DK1S10) +/* buggy schematic: LEDa -> yellow, LEDb --> green */ +#define RPC_DEFAULT ( RPC_SPEED | RPC_DPLX | RPC_ANEG \ + | (RPC_LED_TX_RX << RPC_LSXA_SHFT) \ + | (RPC_LED_100_10 << RPC_LSXB_SHFT) ) +#elif defined(CONFIG_ADNPESC1) +/* SSV ADNP/ESC1 has only one LED: LEDa -> Rx/Tx indicator */ +#define RPC_DEFAULT ( RPC_SPEED | RPC_DPLX | RPC_ANEG \ + | (RPC_LED_TX_RX << RPC_LSXA_SHFT) \ + | (RPC_LED_100_10 << RPC_LSXB_SHFT) ) +#else +/* SMSC reference design: LEDa --> green, LEDb --> yellow */ +#define RPC_DEFAULT ( RPC_SPEED | RPC_DPLX | RPC_ANEG \ + | (RPC_LED_100_10 << RPC_LSXA_SHFT) \ + | (RPC_LED_TX_RX << RPC_LSXB_SHFT) ) +#endif + +/* Bank 0 0x000C is reserved */ + +/* Bank Select Register */ +/* All Banks */ +#define BSR_REG 0x000E + + +/* Configuration Reg */ +/* BANK 1 */ +#define CONFIG_REG 0x0000 +#define CONFIG_EXT_PHY 0x0200 /* 1=external MII, 0=internal Phy */ +#define CONFIG_GPCNTRL 0x0400 /* Inverse value drives pin nCNTRL */ +#define CONFIG_NO_WAIT 0x1000 /* When 1 no extra wait states on ISA bus */ +#define CONFIG_EPH_POWER_EN 0x8000 /* When 0 EPH is placed into low power mode. */ + +/* Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low */ +#define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN) + + +/* Base Address Register */ +/* BANK 1 */ +#define BASE_REG 0x0002 + + +/* Individual Address Registers */ +/* BANK 1 */ +#define ADDR0_REG 0x0004 +#define ADDR1_REG 0x0006 +#define ADDR2_REG 0x0008 + + +/* General Purpose Register */ +/* BANK 1 */ +#define GP_REG 0x000A + + +/* Control Register */ +/* BANK 1 */ +#define CTL_REG 0x000C +#define CTL_RCV_BAD 0x4000 /* When 1 bad CRC packets are received */ +#define CTL_AUTO_RELEASE 0x0800 /* When 1 tx pages are released automatically */ +#define CTL_LE_ENABLE 0x0080 /* When 1 enables Link Error interrupt */ +#define CTL_CR_ENABLE 0x0040 /* When 1 enables Counter Rollover interrupt */ +#define CTL_TE_ENABLE 0x0020 /* When 1 enables Transmit Error interrupt */ +#define CTL_EEPROM_SELECT 0x0004 /* Controls EEPROM reload & store */ +#define CTL_RELOAD 0x0002 /* When set reads EEPROM into registers */ +#define CTL_STORE 0x0001 /* When set stores registers into EEPROM */ +#define CTL_DEFAULT (0x1A10) /* Autorelease enabled*/ + +/* MMU Command Register */ +/* BANK 2 */ +#define MMU_CMD_REG 0x0000 +#define MC_BUSY 1 /* When 1 the last release has not completed */ +#define MC_NOP (0<<5) /* No Op */ +#define MC_ALLOC (1<<5) /* OR with number of 256 byte packets */ +#define MC_RESET (2<<5) /* Reset MMU to initial state */ +#define MC_REMOVE (3<<5) /* Remove the current rx packet */ +#define MC_RELEASE (4<<5) /* Remove and release the current rx packet */ +#define MC_FREEPKT (5<<5) /* Release packet in PNR register */ +#define MC_ENQUEUE (6<<5) /* Enqueue the packet for transmit */ +#define MC_RSTTXFIFO (7<<5) /* Reset the TX FIFOs */ + + +/* Packet Number Register */ +/* BANK 2 */ +#define PN_REG 0x0002 + + +/* Allocation Result Register */ +/* BANK 2 */ +#define AR_REG 0x0003 +#define AR_FAILED 0x80 /* Alocation Failed */ + + +/* RX FIFO Ports Register */ +/* BANK 2 */ +#define RXFIFO_REG 0x0004 /* Must be read as a word */ +#define RXFIFO_REMPTY 0x8000 /* RX FIFO Empty */ + + +/* TX FIFO Ports Register */ +/* BANK 2 */ +#define TXFIFO_REG RXFIFO_REG /* Must be read as a word */ +#define TXFIFO_TEMPTY 0x80 /* TX FIFO Empty */ + + +/* Pointer Register */ +/* BANK 2 */ +#define PTR_REG 0x0006 +#define PTR_RCV 0x8000 /* 1=Receive area, 0=Transmit area */ +#define PTR_AUTOINC 0x4000 /* Auto increment the pointer on each access */ +#define PTR_READ 0x2000 /* When 1 the operation is a read */ +#define PTR_NOTEMPTY 0x0800 /* When 1 _do not_ write fifo DATA REG */ + + +/* Data Register */ +/* BANK 2 */ +#define SMC91111_DATA_REG 0x0008 + + +/* Interrupt Status/Acknowledge Register */ +/* BANK 2 */ +#define SMC91111_INT_REG 0x000C + + +/* Interrupt Mask Register */ +/* BANK 2 */ +#define IM_REG 0x000D +#define IM_MDINT 0x80 /* PHY MI Register 18 Interrupt */ +#define IM_ERCV_INT 0x40 /* Early Receive Interrupt */ +#define IM_EPH_INT 0x20 /* Set by Etheret Protocol Handler section */ +#define IM_RX_OVRN_INT 0x10 /* Set by Receiver Overruns */ +#define IM_ALLOC_INT 0x08 /* Set when allocation request is completed */ +#define IM_TX_EMPTY_INT 0x04 /* Set if the TX FIFO goes empty */ +#define IM_TX_INT 0x02 /* Transmit Interrrupt */ +#define IM_RCV_INT 0x01 /* Receive Interrupt */ + + +/* Multicast Table Registers */ +/* BANK 3 */ +#define MCAST_REG1 0x0000 +#define MCAST_REG2 0x0002 +#define MCAST_REG3 0x0004 +#define MCAST_REG4 0x0006 + + +/* Management Interface Register (MII) */ +/* BANK 3 */ +#define MII_REG 0x0008 +#define MII_MSK_CRS100 0x4000 /* Disables CRS100 detection during tx half dup */ +#define MII_MDOE 0x0008 /* MII Output Enable */ +#define MII_MCLK 0x0004 /* MII Clock, pin MDCLK */ +#define MII_MDI 0x0002 /* MII Input, pin MDI */ +#define MII_MDO 0x0001 /* MII Output, pin MDO */ + + +/* Revision Register */ +/* BANK 3 */ +#define REV_REG 0x000A /* ( hi: chip id low: rev # ) */ + + +/* Early RCV Register */ +/* BANK 3 */ +/* this is NOT on SMC9192 */ +#define ERCV_REG 0x000C +#define ERCV_RCV_DISCRD 0x0080 /* When 1 discards a packet being received */ +#define ERCV_THRESHOLD 0x001F /* ERCV Threshold Mask */ + +/* External Register */ +/* BANK 7 */ +#define EXT_REG 0x0000 + + +#define CHIP_9192 3 +#define CHIP_9194 4 +#define CHIP_9195 5 +#define CHIP_9196 6 +#define CHIP_91100 7 +#define CHIP_91100FD 8 +#define CHIP_91111FD 9 + +#if 0 +static const char * chip_ids[ 15 ] = { + NULL, NULL, NULL, + /* 3 */ "SMC91C90/91C92", + /* 4 */ "SMC91C94", + /* 5 */ "SMC91C95", + /* 6 */ "SMC91C96", + /* 7 */ "SMC91C100", + /* 8 */ "SMC91C100FD", + /* 9 */ "SMC91C111", + NULL, NULL, + NULL, NULL, NULL}; +#endif + +/* + . Transmit status bits +*/ +#define TS_SUCCESS 0x0001 +#define TS_LOSTCAR 0x0400 +#define TS_LATCOL 0x0200 +#define TS_16COL 0x0010 + +/* + . Receive status bits +*/ +#define RS_ALGNERR 0x8000 +#define RS_BRODCAST 0x4000 +#define RS_BADCRC 0x2000 +#define RS_ODDFRAME 0x1000 /* bug: the LAN91C111 never sets this on receive */ +#define RS_TOOLONG 0x0800 +#define RS_TOOSHORT 0x0400 +#define RS_MULTICAST 0x0001 +#define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT) + + +/* PHY Types */ +enum { + PHY_LAN83C183 = 1, /* LAN91C111 Internal PHY */ + PHY_LAN83C180 +}; + + +/* PHY Register Addresses (LAN91C111 Internal PHY) */ + +/* PHY Control Register */ +#define PHY_CNTL_REG 0x00 +#define PHY_CNTL_RST 0x8000 /* 1=PHY Reset */ +#define PHY_CNTL_LPBK 0x4000 /* 1=PHY Loopback */ +#define PHY_CNTL_SPEED 0x2000 /* 1=100Mbps, 0=10Mpbs */ +#define PHY_CNTL_ANEG_EN 0x1000 /* 1=Enable Auto negotiation */ +#define PHY_CNTL_PDN 0x0800 /* 1=PHY Power Down mode */ +#define PHY_CNTL_MII_DIS 0x0400 /* 1=MII 4 bit interface disabled */ +#define PHY_CNTL_ANEG_RST 0x0200 /* 1=Reset Auto negotiate */ +#define PHY_CNTL_DPLX 0x0100 /* 1=Full Duplex, 0=Half Duplex */ +#define PHY_CNTL_COLTST 0x0080 /* 1= MII Colision Test */ + +/* PHY Status Register */ +#define PHY_STAT_REG 0x01 +#define PHY_STAT_CAP_T4 0x8000 /* 1=100Base-T4 capable */ +#define PHY_STAT_CAP_TXF 0x4000 /* 1=100Base-X full duplex capable */ +#define PHY_STAT_CAP_TXH 0x2000 /* 1=100Base-X half duplex capable */ +#define PHY_STAT_CAP_TF 0x1000 /* 1=10Mbps full duplex capable */ +#define PHY_STAT_CAP_TH 0x0800 /* 1=10Mbps half duplex capable */ +#define PHY_STAT_CAP_SUPR 0x0040 /* 1=recv mgmt frames with not preamble */ +#define PHY_STAT_ANEG_ACK 0x0020 /* 1=ANEG has completed */ +#define PHY_STAT_REM_FLT 0x0010 /* 1=Remote Fault detected */ +#define PHY_STAT_CAP_ANEG 0x0008 /* 1=Auto negotiate capable */ +#define PHY_STAT_LINK 0x0004 /* 1=valid link */ +#define PHY_STAT_JAB 0x0002 /* 1=10Mbps jabber condition */ +#define PHY_STAT_EXREG 0x0001 /* 1=extended registers implemented */ + +/* PHY Identifier Registers */ +#define PHY_ID1_REG 0x02 /* PHY Identifier 1 */ +#define PHY_ID2_REG 0x03 /* PHY Identifier 2 */ + +/* PHY Auto-Negotiation Advertisement Register */ +#define PHY_AD_REG 0x04 +#define PHY_AD_NP 0x8000 /* 1=PHY requests exchange of Next Page */ +#define PHY_AD_ACK 0x4000 /* 1=got link code word from remote */ +#define PHY_AD_RF 0x2000 /* 1=advertise remote fault */ +#define PHY_AD_T4 0x0200 /* 1=PHY is capable of 100Base-T4 */ +#define PHY_AD_TX_FDX 0x0100 /* 1=PHY is capable of 100Base-TX FDPLX */ +#define PHY_AD_TX_HDX 0x0080 /* 1=PHY is capable of 100Base-TX HDPLX */ +#define PHY_AD_10_FDX 0x0040 /* 1=PHY is capable of 10Base-T FDPLX */ +#define PHY_AD_10_HDX 0x0020 /* 1=PHY is capable of 10Base-T HDPLX */ +#define PHY_AD_CSMA 0x0001 /* 1=PHY is capable of 802.3 CMSA */ + +/* PHY Auto-negotiation Remote End Capability Register */ +#define PHY_RMT_REG 0x05 +/* Uses same bit definitions as PHY_AD_REG */ + +/* PHY Configuration Register 1 */ +#define PHY_CFG1_REG 0x10 +#define PHY_CFG1_LNKDIS 0x8000 /* 1=Rx Link Detect Function disabled */ +#define PHY_CFG1_XMTDIS 0x4000 /* 1=TP Transmitter Disabled */ +#define PHY_CFG1_XMTPDN 0x2000 /* 1=TP Transmitter Powered Down */ +#define PHY_CFG1_BYPSCR 0x0400 /* 1=Bypass scrambler/descrambler */ +#define PHY_CFG1_UNSCDS 0x0200 /* 1=Unscramble Idle Reception Disable */ +#define PHY_CFG1_EQLZR 0x0100 /* 1=Rx Equalizer Disabled */ +#define PHY_CFG1_CABLE 0x0080 /* 1=STP(150ohm), 0=UTP(100ohm) */ +#define PHY_CFG1_RLVL0 0x0040 /* 1=Rx Squelch level reduced by 4.5db */ +#define PHY_CFG1_TLVL_SHIFT 2 /* Transmit Output Level Adjust */ +#define PHY_CFG1_TLVL_MASK 0x003C +#define PHY_CFG1_TRF_MASK 0x0003 /* Transmitter Rise/Fall time */ + + +/* PHY Configuration Register 2 */ +#define PHY_CFG2_REG 0x11 +#define PHY_CFG2_APOLDIS 0x0020 /* 1=Auto Polarity Correction disabled */ +#define PHY_CFG2_JABDIS 0x0010 /* 1=Jabber disabled */ +#define PHY_CFG2_MREG 0x0008 /* 1=Multiple register access (MII mgt) */ +#define PHY_CFG2_INTMDIO 0x0004 /* 1=Interrupt signaled with MDIO pulseo */ + +/* PHY Status Output (and Interrupt status) Register */ +#define PHY_INT_REG 0x12 /* Status Output (Interrupt Status) */ +#define PHY_INT_INT 0x8000 /* 1=bits have changed since last read */ +#define PHY_INT_LNKFAIL 0x4000 /* 1=Link Not detected */ +#define PHY_INT_LOSSSYNC 0x2000 /* 1=Descrambler has lost sync */ +#define PHY_INT_CWRD 0x1000 /* 1=Invalid 4B5B code detected on rx */ +#define PHY_INT_SSD 0x0800 /* 1=No Start Of Stream detected on rx */ +#define PHY_INT_ESD 0x0400 /* 1=No End Of Stream detected on rx */ +#define PHY_INT_RPOL 0x0200 /* 1=Reverse Polarity detected */ +#define PHY_INT_JAB 0x0100 /* 1=Jabber detected */ +#define PHY_INT_SPDDET 0x0080 /* 1=100Base-TX mode, 0=10Base-T mode */ +#define PHY_INT_DPLXDET 0x0040 /* 1=Device in Full Duplex */ + +/* PHY Interrupt/Status Mask Register */ +#define PHY_MASK_REG 0x13 /* Interrupt Mask */ +/* Uses the same bit definitions as PHY_INT_REG */ + + +/*------------------------------------------------------------------------- + . I define some macros to make it easier to do somewhat common + . or slightly complicated, repeated tasks. + --------------------------------------------------------------------------*/ + +/* select a register bank, 0 to 3 */ + +#define SMC_SELECT_BANK(a,x) { SMC_outw((a), (x), BANK_SELECT ); } + +/* this enables an interrupt in the interrupt mask register */ +#define SMC_ENABLE_INT(a,x) {\ + unsigned char mask;\ + SMC_SELECT_BANK((a),2);\ + mask = SMC_inb((a), IM_REG );\ + mask |= (x);\ + SMC_outb( (a), mask, IM_REG ); \ +} + +/* this disables an interrupt from the interrupt mask register */ + +#define SMC_DISABLE_INT(a,x) {\ + unsigned char mask;\ + SMC_SELECT_BANK(2);\ + mask = SMC_inb( (a), IM_REG );\ + mask &= ~(x);\ + SMC_outb( (a), mask, IM_REG ); \ +} + +/*---------------------------------------------------------------------- + . Define the interrupts that I want to receive from the card + . + . I want: + . IM_EPH_INT, for nasty errors + . IM_RCV_INT, for happy received packets + . IM_RX_OVRN_INT, because I have to kick the receiver + . IM_MDINT, for PHY Register 18 Status Changes + --------------------------------------------------------------------------*/ +#define SMC_INTERRUPT_MASK (IM_EPH_INT | IM_RX_OVRN_INT | IM_RCV_INT | \ + IM_MDINT) + +#endif /* _SMC_91111_H_ */ diff --git a/sources/uboot-be550/drivers/net/smc911x.c b/sources/uboot-be550/drivers/net/smc911x.c new file mode 100644 index 00000000..c85a178c --- /dev/null +++ b/sources/uboot-be550/drivers/net/smc911x.c @@ -0,0 +1,283 @@ +/* + * SMSC LAN9[12]1[567] Network driver + * + * (c) 2007 Pengutronix, Sascha Hauer + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +#include "smc911x.h" + +u32 pkt_data_pull(struct eth_device *dev, u32 addr) \ + __attribute__ ((weak, alias ("smc911x_reg_read"))); +void pkt_data_push(struct eth_device *dev, u32 addr, u32 val) \ + __attribute__ ((weak, alias ("smc911x_reg_write"))); + +static void smc911x_handle_mac_address(struct eth_device *dev) +{ + unsigned long addrh, addrl; + uchar *m = dev->enetaddr; + + addrl = m[0] | (m[1] << 8) | (m[2] << 16) | (m[3] << 24); + addrh = m[4] | (m[5] << 8); + smc911x_set_mac_csr(dev, ADDRL, addrl); + smc911x_set_mac_csr(dev, ADDRH, addrh); + + printf(DRIVERNAME ": MAC %pM\n", m); +} + +static int smc911x_eth_phy_read(struct eth_device *dev, + u8 phy, u8 reg, u16 *val) +{ + while (smc911x_get_mac_csr(dev, MII_ACC) & MII_ACC_MII_BUSY) + ; + + smc911x_set_mac_csr(dev, MII_ACC, phy << 11 | reg << 6 | + MII_ACC_MII_BUSY); + + while (smc911x_get_mac_csr(dev, MII_ACC) & MII_ACC_MII_BUSY) + ; + + *val = smc911x_get_mac_csr(dev, MII_DATA); + + return 0; +} + +static int smc911x_eth_phy_write(struct eth_device *dev, + u8 phy, u8 reg, u16 val) +{ + while (smc911x_get_mac_csr(dev, MII_ACC) & MII_ACC_MII_BUSY) + ; + + smc911x_set_mac_csr(dev, MII_DATA, val); + smc911x_set_mac_csr(dev, MII_ACC, + phy << 11 | reg << 6 | MII_ACC_MII_BUSY | MII_ACC_MII_WRITE); + + while (smc911x_get_mac_csr(dev, MII_ACC) & MII_ACC_MII_BUSY) + ; + return 0; +} + +static int smc911x_phy_reset(struct eth_device *dev) +{ + u32 reg; + + reg = smc911x_reg_read(dev, PMT_CTRL); + reg &= ~0xfffff030; + reg |= PMT_CTRL_PHY_RST; + smc911x_reg_write(dev, PMT_CTRL, reg); + + mdelay(100); + + return 0; +} + +static void smc911x_phy_configure(struct eth_device *dev) +{ + int timeout; + u16 status; + + smc911x_phy_reset(dev); + + smc911x_eth_phy_write(dev, 1, MII_BMCR, BMCR_RESET); + mdelay(1); + smc911x_eth_phy_write(dev, 1, MII_ADVERTISE, 0x01e1); + smc911x_eth_phy_write(dev, 1, MII_BMCR, BMCR_ANENABLE | + BMCR_ANRESTART); + + timeout = 5000; + do { + mdelay(1); + if ((timeout--) == 0) + goto err_out; + + if (smc911x_eth_phy_read(dev, 1, MII_BMSR, &status) != 0) + goto err_out; + } while (!(status & BMSR_LSTATUS)); + + printf(DRIVERNAME ": phy initialized\n"); + + return; + +err_out: + printf(DRIVERNAME ": autonegotiation timed out\n"); +} + +static void smc911x_enable(struct eth_device *dev) +{ + /* Enable TX */ + smc911x_reg_write(dev, HW_CFG, 8 << 16 | HW_CFG_SF); + + smc911x_reg_write(dev, GPT_CFG, GPT_CFG_TIMER_EN | 10000); + + smc911x_reg_write(dev, TX_CFG, TX_CFG_TX_ON); + + /* no padding to start of packets */ + smc911x_reg_write(dev, RX_CFG, 0); + + smc911x_set_mac_csr(dev, MAC_CR, MAC_CR_TXEN | MAC_CR_RXEN | + MAC_CR_HBDIS); + +} + +static int smc911x_init(struct eth_device *dev, bd_t * bd) +{ + struct chip_id *id = dev->priv; + + printf(DRIVERNAME ": detected %s controller\n", id->name); + + smc911x_reset(dev); + + /* Configure the PHY, initialize the link state */ + smc911x_phy_configure(dev); + + smc911x_handle_mac_address(dev); + + /* Turn on Tx + Rx */ + smc911x_enable(dev); + + return 0; +} + +static int smc911x_send(struct eth_device *dev, void *packet, int length) +{ + u32 *data = (u32*)packet; + u32 tmplen; + u32 status; + + smc911x_reg_write(dev, TX_DATA_FIFO, TX_CMD_A_INT_FIRST_SEG | + TX_CMD_A_INT_LAST_SEG | length); + smc911x_reg_write(dev, TX_DATA_FIFO, length); + + tmplen = (length + 3) / 4; + + while (tmplen--) + pkt_data_push(dev, TX_DATA_FIFO, *data++); + + /* wait for transmission */ + while (!((smc911x_reg_read(dev, TX_FIFO_INF) & + TX_FIFO_INF_TSUSED) >> 16)); + + /* get status. Ignore 'no carrier' error, it has no meaning for + * full duplex operation + */ + status = smc911x_reg_read(dev, TX_STATUS_FIFO) & + (TX_STS_LOC | TX_STS_LATE_COLL | TX_STS_MANY_COLL | + TX_STS_MANY_DEFER | TX_STS_UNDERRUN); + + if (!status) + return 0; + + printf(DRIVERNAME ": failed to send packet: %s%s%s%s%s\n", + status & TX_STS_LOC ? "TX_STS_LOC " : "", + status & TX_STS_LATE_COLL ? "TX_STS_LATE_COLL " : "", + status & TX_STS_MANY_COLL ? "TX_STS_MANY_COLL " : "", + status & TX_STS_MANY_DEFER ? "TX_STS_MANY_DEFER " : "", + status & TX_STS_UNDERRUN ? "TX_STS_UNDERRUN" : ""); + + return -1; +} + +static void smc911x_halt(struct eth_device *dev) +{ + smc911x_reset(dev); + smc911x_handle_mac_address(dev); +} + +static int smc911x_rx(struct eth_device *dev) +{ + u32 *data = (u32 *)net_rx_packets[0]; + u32 pktlen, tmplen; + u32 status; + + if ((smc911x_reg_read(dev, RX_FIFO_INF) & RX_FIFO_INF_RXSUSED) >> 16) { + status = smc911x_reg_read(dev, RX_STATUS_FIFO); + pktlen = (status & RX_STS_PKT_LEN) >> 16; + + smc911x_reg_write(dev, RX_CFG, 0); + + tmplen = (pktlen + 3) / 4; + while (tmplen--) + *data++ = pkt_data_pull(dev, RX_DATA_FIFO); + + if (status & RX_STS_ES) + printf(DRIVERNAME + ": dropped bad packet. Status: 0x%08x\n", + status); + else + net_process_received_packet(net_rx_packets[0], pktlen); + } + + return 0; +} + +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) +/* wrapper for smc911x_eth_phy_read */ +static int smc911x_miiphy_read(const char *devname, u8 phy, u8 reg, u16 *val) +{ + struct eth_device *dev = eth_get_dev_by_name(devname); + if (dev) + return smc911x_eth_phy_read(dev, phy, reg, val); + return -1; +} +/* wrapper for smc911x_eth_phy_write */ +static int smc911x_miiphy_write(const char *devname, u8 phy, u8 reg, u16 val) +{ + struct eth_device *dev = eth_get_dev_by_name(devname); + if (dev) + return smc911x_eth_phy_write(dev, phy, reg, val); + return -1; +} +#endif + +int smc911x_initialize(u8 dev_num, int base_addr) +{ + unsigned long addrl, addrh; + struct eth_device *dev; + + dev = malloc(sizeof(*dev)); + if (!dev) { + return -1; + } + memset(dev, 0, sizeof(*dev)); + + dev->iobase = base_addr; + + /* Try to detect chip. Will fail if not present. */ + if (smc911x_detect_chip(dev)) { + free(dev); + return 0; + } + + addrh = smc911x_get_mac_csr(dev, ADDRH); + addrl = smc911x_get_mac_csr(dev, ADDRL); + if (!(addrl == 0xffffffff && addrh == 0x0000ffff)) { + /* address is obtained from optional eeprom */ + dev->enetaddr[0] = addrl; + dev->enetaddr[1] = addrl >> 8; + dev->enetaddr[2] = addrl >> 16; + dev->enetaddr[3] = addrl >> 24; + dev->enetaddr[4] = addrh; + dev->enetaddr[5] = addrh >> 8; + } + + dev->init = smc911x_init; + dev->halt = smc911x_halt; + dev->send = smc911x_send; + dev->recv = smc911x_rx; + sprintf(dev->name, "%s-%hu", DRIVERNAME, dev_num); + + eth_register(dev); + +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) + miiphy_register(dev->name, smc911x_miiphy_read, smc911x_miiphy_write); +#endif + + return 1; +} diff --git a/sources/uboot-be550/drivers/net/smc911x.h b/sources/uboot-be550/drivers/net/smc911x.h new file mode 100644 index 00000000..acae0cfb --- /dev/null +++ b/sources/uboot-be550/drivers/net/smc911x.h @@ -0,0 +1,500 @@ +/* + * SMSC LAN9[12]1[567] Network driver + * + * (c) 2007 Pengutronix, Sascha Hauer + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SMC911X_H_ +#define _SMC911X_H_ + +#include + +#define DRIVERNAME "smc911x" + +#if defined (CONFIG_SMC911X_32_BIT) && \ + defined (CONFIG_SMC911X_16_BIT) +#error "SMC911X: Only one of CONFIG_SMC911X_32_BIT and \ + CONFIG_SMC911X_16_BIT shall be set" +#endif + +#if defined (CONFIG_SMC911X_32_BIT) +static inline u32 __smc911x_reg_read(struct eth_device *dev, u32 offset) +{ + return *(volatile u32*)(dev->iobase + offset); +} +u32 smc911x_reg_read(struct eth_device *dev, u32 offset) + __attribute__((weak, alias("__smc911x_reg_read"))); + +static inline void __smc911x_reg_write(struct eth_device *dev, + u32 offset, u32 val) +{ + *(volatile u32*)(dev->iobase + offset) = val; +} +void smc911x_reg_write(struct eth_device *dev, u32 offset, u32 val) + __attribute__((weak, alias("__smc911x_reg_write"))); +#elif defined (CONFIG_SMC911X_16_BIT) +static inline u32 smc911x_reg_read(struct eth_device *dev, u32 offset) +{ + volatile u16 *addr_16 = (u16 *)(dev->iobase + offset); + return ((*addr_16 & 0x0000ffff) | (*(addr_16 + 1) << 16)); +} +static inline void smc911x_reg_write(struct eth_device *dev, + u32 offset, u32 val) +{ + *(volatile u16 *)(dev->iobase + offset) = (u16)val; + *(volatile u16 *)(dev->iobase + offset + 2) = (u16)(val >> 16); +} +#else +#error "SMC911X: undefined bus width" +#endif /* CONFIG_SMC911X_16_BIT */ + +/* Below are the register offsets and bit definitions + * of the Lan911x memory space + */ +#define RX_DATA_FIFO 0x00 + +#define TX_DATA_FIFO 0x20 +#define TX_CMD_A_INT_ON_COMP 0x80000000 +#define TX_CMD_A_INT_BUF_END_ALGN 0x03000000 +#define TX_CMD_A_INT_4_BYTE_ALGN 0x00000000 +#define TX_CMD_A_INT_16_BYTE_ALGN 0x01000000 +#define TX_CMD_A_INT_32_BYTE_ALGN 0x02000000 +#define TX_CMD_A_INT_DATA_OFFSET 0x001F0000 +#define TX_CMD_A_INT_FIRST_SEG 0x00002000 +#define TX_CMD_A_INT_LAST_SEG 0x00001000 +#define TX_CMD_A_BUF_SIZE 0x000007FF +#define TX_CMD_B_PKT_TAG 0xFFFF0000 +#define TX_CMD_B_ADD_CRC_DISABLE 0x00002000 +#define TX_CMD_B_DISABLE_PADDING 0x00001000 +#define TX_CMD_B_PKT_BYTE_LENGTH 0x000007FF + +#define RX_STATUS_FIFO 0x40 +#define RX_STS_PKT_LEN 0x3FFF0000 +#define RX_STS_ES 0x00008000 +#define RX_STS_BCST 0x00002000 +#define RX_STS_LEN_ERR 0x00001000 +#define RX_STS_RUNT_ERR 0x00000800 +#define RX_STS_MCAST 0x00000400 +#define RX_STS_TOO_LONG 0x00000080 +#define RX_STS_COLL 0x00000040 +#define RX_STS_ETH_TYPE 0x00000020 +#define RX_STS_WDOG_TMT 0x00000010 +#define RX_STS_MII_ERR 0x00000008 +#define RX_STS_DRIBBLING 0x00000004 +#define RX_STS_CRC_ERR 0x00000002 +#define RX_STATUS_FIFO_PEEK 0x44 +#define TX_STATUS_FIFO 0x48 +#define TX_STS_TAG 0xFFFF0000 +#define TX_STS_ES 0x00008000 +#define TX_STS_LOC 0x00000800 +#define TX_STS_NO_CARR 0x00000400 +#define TX_STS_LATE_COLL 0x00000200 +#define TX_STS_MANY_COLL 0x00000100 +#define TX_STS_COLL_CNT 0x00000078 +#define TX_STS_MANY_DEFER 0x00000004 +#define TX_STS_UNDERRUN 0x00000002 +#define TX_STS_DEFERRED 0x00000001 +#define TX_STATUS_FIFO_PEEK 0x4C +#define ID_REV 0x50 +#define ID_REV_CHIP_ID 0xFFFF0000 /* RO */ +#define ID_REV_REV_ID 0x0000FFFF /* RO */ + +#define INT_CFG 0x54 +#define INT_CFG_INT_DEAS 0xFF000000 /* R/W */ +#define INT_CFG_INT_DEAS_CLR 0x00004000 +#define INT_CFG_INT_DEAS_STS 0x00002000 +#define INT_CFG_IRQ_INT 0x00001000 /* RO */ +#define INT_CFG_IRQ_EN 0x00000100 /* R/W */ + /* R/W Not Affected by SW Reset */ +#define INT_CFG_IRQ_POL 0x00000010 + /* R/W Not Affected by SW Reset */ +#define INT_CFG_IRQ_TYPE 0x00000001 + +#define INT_STS 0x58 +#define INT_STS_SW_INT 0x80000000 /* R/WC */ +#define INT_STS_TXSTOP_INT 0x02000000 /* R/WC */ +#define INT_STS_RXSTOP_INT 0x01000000 /* R/WC */ +#define INT_STS_RXDFH_INT 0x00800000 /* R/WC */ +#define INT_STS_RXDF_INT 0x00400000 /* R/WC */ +#define INT_STS_TX_IOC 0x00200000 /* R/WC */ +#define INT_STS_RXD_INT 0x00100000 /* R/WC */ +#define INT_STS_GPT_INT 0x00080000 /* R/WC */ +#define INT_STS_PHY_INT 0x00040000 /* RO */ +#define INT_STS_PME_INT 0x00020000 /* R/WC */ +#define INT_STS_TXSO 0x00010000 /* R/WC */ +#define INT_STS_RWT 0x00008000 /* R/WC */ +#define INT_STS_RXE 0x00004000 /* R/WC */ +#define INT_STS_TXE 0x00002000 /* R/WC */ +/*#define INT_STS_ERX 0x00001000*/ /* R/WC */ +#define INT_STS_TDFU 0x00000800 /* R/WC */ +#define INT_STS_TDFO 0x00000400 /* R/WC */ +#define INT_STS_TDFA 0x00000200 /* R/WC */ +#define INT_STS_TSFF 0x00000100 /* R/WC */ +#define INT_STS_TSFL 0x00000080 /* R/WC */ +/*#define INT_STS_RXDF 0x00000040*/ /* R/WC */ +#define INT_STS_RDFO 0x00000040 /* R/WC */ +#define INT_STS_RDFL 0x00000020 /* R/WC */ +#define INT_STS_RSFF 0x00000010 /* R/WC */ +#define INT_STS_RSFL 0x00000008 /* R/WC */ +#define INT_STS_GPIO2_INT 0x00000004 /* R/WC */ +#define INT_STS_GPIO1_INT 0x00000002 /* R/WC */ +#define INT_STS_GPIO0_INT 0x00000001 /* R/WC */ +#define INT_EN 0x5C +#define INT_EN_SW_INT_EN 0x80000000 /* R/W */ +#define INT_EN_TXSTOP_INT_EN 0x02000000 /* R/W */ +#define INT_EN_RXSTOP_INT_EN 0x01000000 /* R/W */ +#define INT_EN_RXDFH_INT_EN 0x00800000 /* R/W */ +/*#define INT_EN_RXDF_INT_EN 0x00400000*/ /* R/W */ +#define INT_EN_TIOC_INT_EN 0x00200000 /* R/W */ +#define INT_EN_RXD_INT_EN 0x00100000 /* R/W */ +#define INT_EN_GPT_INT_EN 0x00080000 /* R/W */ +#define INT_EN_PHY_INT_EN 0x00040000 /* R/W */ +#define INT_EN_PME_INT_EN 0x00020000 /* R/W */ +#define INT_EN_TXSO_EN 0x00010000 /* R/W */ +#define INT_EN_RWT_EN 0x00008000 /* R/W */ +#define INT_EN_RXE_EN 0x00004000 /* R/W */ +#define INT_EN_TXE_EN 0x00002000 /* R/W */ +/*#define INT_EN_ERX_EN 0x00001000*/ /* R/W */ +#define INT_EN_TDFU_EN 0x00000800 /* R/W */ +#define INT_EN_TDFO_EN 0x00000400 /* R/W */ +#define INT_EN_TDFA_EN 0x00000200 /* R/W */ +#define INT_EN_TSFF_EN 0x00000100 /* R/W */ +#define INT_EN_TSFL_EN 0x00000080 /* R/W */ +/*#define INT_EN_RXDF_EN 0x00000040*/ /* R/W */ +#define INT_EN_RDFO_EN 0x00000040 /* R/W */ +#define INT_EN_RDFL_EN 0x00000020 /* R/W */ +#define INT_EN_RSFF_EN 0x00000010 /* R/W */ +#define INT_EN_RSFL_EN 0x00000008 /* R/W */ +#define INT_EN_GPIO2_INT 0x00000004 /* R/W */ +#define INT_EN_GPIO1_INT 0x00000002 /* R/W */ +#define INT_EN_GPIO0_INT 0x00000001 /* R/W */ + +#define BYTE_TEST 0x64 +#define FIFO_INT 0x68 +#define FIFO_INT_TX_AVAIL_LEVEL 0xFF000000 /* R/W */ +#define FIFO_INT_TX_STS_LEVEL 0x00FF0000 /* R/W */ +#define FIFO_INT_RX_AVAIL_LEVEL 0x0000FF00 /* R/W */ +#define FIFO_INT_RX_STS_LEVEL 0x000000FF /* R/W */ + +#define RX_CFG 0x6C +#define RX_CFG_RX_END_ALGN 0xC0000000 /* R/W */ +#define RX_CFG_RX_END_ALGN4 0x00000000 /* R/W */ +#define RX_CFG_RX_END_ALGN16 0x40000000 /* R/W */ +#define RX_CFG_RX_END_ALGN32 0x80000000 /* R/W */ +#define RX_CFG_RX_DMA_CNT 0x0FFF0000 /* R/W */ +#define RX_CFG_RX_DUMP 0x00008000 /* R/W */ +#define RX_CFG_RXDOFF 0x00001F00 /* R/W */ +/*#define RX_CFG_RXBAD 0x00000001*/ /* R/W */ + +#define TX_CFG 0x70 +/*#define TX_CFG_TX_DMA_LVL 0xE0000000*/ /* R/W */ + /* R/W Self Clearing */ +/*#define TX_CFG_TX_DMA_CNT 0x0FFF0000*/ +#define TX_CFG_TXS_DUMP 0x00008000 /* Self Clearing */ +#define TX_CFG_TXD_DUMP 0x00004000 /* Self Clearing */ +#define TX_CFG_TXSAO 0x00000004 /* R/W */ +#define TX_CFG_TX_ON 0x00000002 /* R/W */ +#define TX_CFG_STOP_TX 0x00000001 /* Self Clearing */ + +#define HW_CFG 0x74 +#define HW_CFG_TTM 0x00200000 /* R/W */ +#define HW_CFG_SF 0x00100000 /* R/W */ +#define HW_CFG_TX_FIF_SZ 0x000F0000 /* R/W */ +#define HW_CFG_TR 0x00003000 /* R/W */ +#define HW_CFG_PHY_CLK_SEL 0x00000060 /* R/W */ +#define HW_CFG_PHY_CLK_SEL_INT_PHY 0x00000000 /* R/W */ +#define HW_CFG_PHY_CLK_SEL_EXT_PHY 0x00000020 /* R/W */ +#define HW_CFG_PHY_CLK_SEL_CLK_DIS 0x00000040 /* R/W */ +#define HW_CFG_SMI_SEL 0x00000010 /* R/W */ +#define HW_CFG_EXT_PHY_DET 0x00000008 /* RO */ +#define HW_CFG_EXT_PHY_EN 0x00000004 /* R/W */ +#define HW_CFG_32_16_BIT_MODE 0x00000004 /* RO */ +#define HW_CFG_SRST_TO 0x00000002 /* RO */ +#define HW_CFG_SRST 0x00000001 /* Self Clearing */ + +#define RX_DP_CTRL 0x78 +#define RX_DP_CTRL_RX_FFWD 0x80000000 /* R/W */ +#define RX_DP_CTRL_FFWD_BUSY 0x80000000 /* RO */ + +#define RX_FIFO_INF 0x7C +#define RX_FIFO_INF_RXSUSED 0x00FF0000 /* RO */ +#define RX_FIFO_INF_RXDUSED 0x0000FFFF /* RO */ + +#define TX_FIFO_INF 0x80 +#define TX_FIFO_INF_TSUSED 0x00FF0000 /* RO */ +#define TX_FIFO_INF_TDFREE 0x0000FFFF /* RO */ + +#define PMT_CTRL 0x84 +#define PMT_CTRL_PM_MODE 0x00003000 /* Self Clearing */ +#define PMT_CTRL_PHY_RST 0x00000400 /* Self Clearing */ +#define PMT_CTRL_WOL_EN 0x00000200 /* R/W */ +#define PMT_CTRL_ED_EN 0x00000100 /* R/W */ + /* R/W Not Affected by SW Reset */ +#define PMT_CTRL_PME_TYPE 0x00000040 +#define PMT_CTRL_WUPS 0x00000030 /* R/WC */ +#define PMT_CTRL_WUPS_NOWAKE 0x00000000 /* R/WC */ +#define PMT_CTRL_WUPS_ED 0x00000010 /* R/WC */ +#define PMT_CTRL_WUPS_WOL 0x00000020 /* R/WC */ +#define PMT_CTRL_WUPS_MULTI 0x00000030 /* R/WC */ +#define PMT_CTRL_PME_IND 0x00000008 /* R/W */ +#define PMT_CTRL_PME_POL 0x00000004 /* R/W */ + /* R/W Not Affected by SW Reset */ +#define PMT_CTRL_PME_EN 0x00000002 +#define PMT_CTRL_READY 0x00000001 /* RO */ + +#define GPIO_CFG 0x88 +#define GPIO_CFG_LED3_EN 0x40000000 /* R/W */ +#define GPIO_CFG_LED2_EN 0x20000000 /* R/W */ +#define GPIO_CFG_LED1_EN 0x10000000 /* R/W */ +#define GPIO_CFG_GPIO2_INT_POL 0x04000000 /* R/W */ +#define GPIO_CFG_GPIO1_INT_POL 0x02000000 /* R/W */ +#define GPIO_CFG_GPIO0_INT_POL 0x01000000 /* R/W */ +#define GPIO_CFG_EEPR_EN 0x00700000 /* R/W */ +#define GPIO_CFG_GPIOBUF2 0x00040000 /* R/W */ +#define GPIO_CFG_GPIOBUF1 0x00020000 /* R/W */ +#define GPIO_CFG_GPIOBUF0 0x00010000 /* R/W */ +#define GPIO_CFG_GPIODIR2 0x00000400 /* R/W */ +#define GPIO_CFG_GPIODIR1 0x00000200 /* R/W */ +#define GPIO_CFG_GPIODIR0 0x00000100 /* R/W */ +#define GPIO_CFG_GPIOD4 0x00000010 /* R/W */ +#define GPIO_CFG_GPIOD3 0x00000008 /* R/W */ +#define GPIO_CFG_GPIOD2 0x00000004 /* R/W */ +#define GPIO_CFG_GPIOD1 0x00000002 /* R/W */ +#define GPIO_CFG_GPIOD0 0x00000001 /* R/W */ + +#define GPT_CFG 0x8C +#define GPT_CFG_TIMER_EN 0x20000000 /* R/W */ +#define GPT_CFG_GPT_LOAD 0x0000FFFF /* R/W */ + +#define GPT_CNT 0x90 +#define GPT_CNT_GPT_CNT 0x0000FFFF /* RO */ + +#define ENDIAN 0x98 +#define FREE_RUN 0x9C +#define RX_DROP 0xA0 +#define MAC_CSR_CMD 0xA4 +#define MAC_CSR_CMD_CSR_BUSY 0x80000000 /* Self Clearing */ +#define MAC_CSR_CMD_R_NOT_W 0x40000000 /* R/W */ +#define MAC_CSR_CMD_CSR_ADDR 0x000000FF /* R/W */ + +#define MAC_CSR_DATA 0xA8 +#define AFC_CFG 0xAC +#define AFC_CFG_AFC_HI 0x00FF0000 /* R/W */ +#define AFC_CFG_AFC_LO 0x0000FF00 /* R/W */ +#define AFC_CFG_BACK_DUR 0x000000F0 /* R/W */ +#define AFC_CFG_FCMULT 0x00000008 /* R/W */ +#define AFC_CFG_FCBRD 0x00000004 /* R/W */ +#define AFC_CFG_FCADD 0x00000002 /* R/W */ +#define AFC_CFG_FCANY 0x00000001 /* R/W */ + +#define E2P_CMD 0xB0 +#define E2P_CMD_EPC_BUSY 0x80000000 /* Self Clearing */ +#define E2P_CMD_EPC_CMD 0x70000000 /* R/W */ +#define E2P_CMD_EPC_CMD_READ 0x00000000 /* R/W */ +#define E2P_CMD_EPC_CMD_EWDS 0x10000000 /* R/W */ +#define E2P_CMD_EPC_CMD_EWEN 0x20000000 /* R/W */ +#define E2P_CMD_EPC_CMD_WRITE 0x30000000 /* R/W */ +#define E2P_CMD_EPC_CMD_WRAL 0x40000000 /* R/W */ +#define E2P_CMD_EPC_CMD_ERASE 0x50000000 /* R/W */ +#define E2P_CMD_EPC_CMD_ERAL 0x60000000 /* R/W */ +#define E2P_CMD_EPC_CMD_RELOAD 0x70000000 /* R/W */ +#define E2P_CMD_EPC_TIMEOUT 0x00000200 /* RO */ +#define E2P_CMD_MAC_ADDR_LOADED 0x00000100 /* RO */ +#define E2P_CMD_EPC_ADDR 0x000000FF /* R/W */ + +#define E2P_DATA 0xB4 +#define E2P_DATA_EEPROM_DATA 0x000000FF /* R/W */ +/* end of LAN register offsets and bit definitions */ + +/* MAC Control and Status registers */ +#define MAC_CR 0x01 /* R/W */ + +/* MAC_CR - MAC Control Register */ +#define MAC_CR_RXALL 0x80000000 +/* TODO: delete this bit? It is not described in the data sheet. */ +#define MAC_CR_HBDIS 0x10000000 +#define MAC_CR_RCVOWN 0x00800000 +#define MAC_CR_LOOPBK 0x00200000 +#define MAC_CR_FDPX 0x00100000 +#define MAC_CR_MCPAS 0x00080000 +#define MAC_CR_PRMS 0x00040000 +#define MAC_CR_INVFILT 0x00020000 +#define MAC_CR_PASSBAD 0x00010000 +#define MAC_CR_HFILT 0x00008000 +#define MAC_CR_HPFILT 0x00002000 +#define MAC_CR_LCOLL 0x00001000 +#define MAC_CR_BCAST 0x00000800 +#define MAC_CR_DISRTY 0x00000400 +#define MAC_CR_PADSTR 0x00000100 +#define MAC_CR_BOLMT_MASK 0x000000C0 +#define MAC_CR_DFCHK 0x00000020 +#define MAC_CR_TXEN 0x00000008 +#define MAC_CR_RXEN 0x00000004 + +#define ADDRH 0x02 /* R/W mask 0x0000FFFFUL */ +#define ADDRL 0x03 /* R/W mask 0xFFFFFFFFUL */ +#define HASHH 0x04 /* R/W */ +#define HASHL 0x05 /* R/W */ + +#define MII_ACC 0x06 /* R/W */ +#define MII_ACC_PHY_ADDR 0x0000F800 +#define MII_ACC_MIIRINDA 0x000007C0 +#define MII_ACC_MII_WRITE 0x00000002 +#define MII_ACC_MII_BUSY 0x00000001 + +#define MII_DATA 0x07 /* R/W mask 0x0000FFFFUL */ + +#define FLOW 0x08 /* R/W */ +#define FLOW_FCPT 0xFFFF0000 +#define FLOW_FCPASS 0x00000004 +#define FLOW_FCEN 0x00000002 +#define FLOW_FCBSY 0x00000001 + +#define VLAN1 0x09 /* R/W mask 0x0000FFFFUL */ +#define VLAN1_VTI1 0x0000ffff + +#define VLAN2 0x0A /* R/W mask 0x0000FFFFUL */ +#define VLAN2_VTI2 0x0000ffff + +#define WUFF 0x0B /* WO */ + +#define WUCSR 0x0C /* R/W */ +#define WUCSR_GUE 0x00000200 +#define WUCSR_WUFR 0x00000040 +#define WUCSR_MPR 0x00000020 +#define WUCSR_WAKE_EN 0x00000004 +#define WUCSR_MPEN 0x00000002 + +/* Chip ID values */ +#define CHIP_89218 0x218a +#define CHIP_9115 0x115 +#define CHIP_9116 0x116 +#define CHIP_9117 0x117 +#define CHIP_9118 0x118 +#define CHIP_9211 0x9211 +#define CHIP_9215 0x115a +#define CHIP_9216 0x116a +#define CHIP_9217 0x117a +#define CHIP_9218 0x118a +#define CHIP_9220 0x9220 +#define CHIP_9221 0x9221 + +struct chip_id { + u16 id; + char *name; +}; + +static const struct chip_id chip_ids[] = { + { CHIP_89218, "LAN89218" }, + { CHIP_9115, "LAN9115" }, + { CHIP_9116, "LAN9116" }, + { CHIP_9117, "LAN9117" }, + { CHIP_9118, "LAN9118" }, + { CHIP_9211, "LAN9211" }, + { CHIP_9215, "LAN9215" }, + { CHIP_9216, "LAN9216" }, + { CHIP_9217, "LAN9217" }, + { CHIP_9218, "LAN9218" }, + { CHIP_9220, "LAN9220" }, + { CHIP_9221, "LAN9221" }, + { 0, NULL }, +}; + +static u32 smc911x_get_mac_csr(struct eth_device *dev, u8 reg) +{ + while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) + ; + smc911x_reg_write(dev, MAC_CSR_CMD, + MAC_CSR_CMD_CSR_BUSY | MAC_CSR_CMD_R_NOT_W | reg); + while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) + ; + + return smc911x_reg_read(dev, MAC_CSR_DATA); +} + +static void smc911x_set_mac_csr(struct eth_device *dev, u8 reg, u32 data) +{ + while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) + ; + smc911x_reg_write(dev, MAC_CSR_DATA, data); + smc911x_reg_write(dev, MAC_CSR_CMD, MAC_CSR_CMD_CSR_BUSY | reg); + while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) + ; +} + +static int smc911x_detect_chip(struct eth_device *dev) +{ + unsigned long val, i; + + val = smc911x_reg_read(dev, BYTE_TEST); + if (val == 0xffffffff) { + /* Special case -- no chip present */ + return -1; + } else if (val != 0x87654321) { + printf(DRIVERNAME ": Invalid chip endian 0x%08lx\n", val); + return -1; + } + + val = smc911x_reg_read(dev, ID_REV) >> 16; + for (i = 0; chip_ids[i].id != 0; i++) { + if (chip_ids[i].id == val) break; + } + if (!chip_ids[i].id) { + printf(DRIVERNAME ": Unknown chip ID %04lx\n", val); + return -1; + } + + dev->priv = (void *)&chip_ids[i]; + + return 0; +} + +static void smc911x_reset(struct eth_device *dev) +{ + int timeout; + + /* + * Take out of PM setting first + * Device is already wake up if PMT_CTRL_READY bit is set + */ + if ((smc911x_reg_read(dev, PMT_CTRL) & PMT_CTRL_READY) == 0) { + /* Write to the bytetest will take out of powerdown */ + smc911x_reg_write(dev, BYTE_TEST, 0x0); + + timeout = 10; + + while (timeout-- && + !(smc911x_reg_read(dev, PMT_CTRL) & PMT_CTRL_READY)) + udelay(10); + if (timeout < 0) { + printf(DRIVERNAME + ": timeout waiting for PM restore\n"); + return; + } + } + + /* Disable interrupts */ + smc911x_reg_write(dev, INT_EN, 0); + + smc911x_reg_write(dev, HW_CFG, HW_CFG_SRST); + + timeout = 1000; + while (timeout-- && smc911x_reg_read(dev, E2P_CMD) & E2P_CMD_EPC_BUSY) + udelay(10); + + if (timeout < 0) { + printf(DRIVERNAME ": reset timeout\n"); + return; + } + + /* Reset the FIFO level and flow control settings */ + smc911x_set_mac_csr(dev, FLOW, FLOW_FCPT | FLOW_FCEN); + smc911x_reg_write(dev, AFC_CFG, 0x0050287F); + + /* Set to LED outputs */ + smc911x_reg_write(dev, GPIO_CFG, 0x70070000); +} + +#endif diff --git a/sources/uboot-be550/drivers/net/sunxi_emac.c b/sources/uboot-be550/drivers/net/sunxi_emac.c new file mode 100644 index 00000000..11cd0ea0 --- /dev/null +++ b/sources/uboot-be550/drivers/net/sunxi_emac.c @@ -0,0 +1,587 @@ +/* + * sunxi_emac.c -- Allwinner A10 ethernet driver + * + * (C) Copyright 2012, Stefan Roese + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* EMAC register */ +struct emac_regs { + u32 ctl; /* 0x00 */ + u32 tx_mode; /* 0x04 */ + u32 tx_flow; /* 0x08 */ + u32 tx_ctl0; /* 0x0c */ + u32 tx_ctl1; /* 0x10 */ + u32 tx_ins; /* 0x14 */ + u32 tx_pl0; /* 0x18 */ + u32 tx_pl1; /* 0x1c */ + u32 tx_sta; /* 0x20 */ + u32 tx_io_data; /* 0x24 */ + u32 tx_io_data1;/* 0x28 */ + u32 tx_tsvl0; /* 0x2c */ + u32 tx_tsvh0; /* 0x30 */ + u32 tx_tsvl1; /* 0x34 */ + u32 tx_tsvh1; /* 0x38 */ + u32 rx_ctl; /* 0x3c */ + u32 rx_hash0; /* 0x40 */ + u32 rx_hash1; /* 0x44 */ + u32 rx_sta; /* 0x48 */ + u32 rx_io_data; /* 0x4c */ + u32 rx_fbc; /* 0x50 */ + u32 int_ctl; /* 0x54 */ + u32 int_sta; /* 0x58 */ + u32 mac_ctl0; /* 0x5c */ + u32 mac_ctl1; /* 0x60 */ + u32 mac_ipgt; /* 0x64 */ + u32 mac_ipgr; /* 0x68 */ + u32 mac_clrt; /* 0x6c */ + u32 mac_maxf; /* 0x70 */ + u32 mac_supp; /* 0x74 */ + u32 mac_test; /* 0x78 */ + u32 mac_mcfg; /* 0x7c */ + u32 mac_mcmd; /* 0x80 */ + u32 mac_madr; /* 0x84 */ + u32 mac_mwtd; /* 0x88 */ + u32 mac_mrdd; /* 0x8c */ + u32 mac_mind; /* 0x90 */ + u32 mac_ssrr; /* 0x94 */ + u32 mac_a0; /* 0x98 */ + u32 mac_a1; /* 0x9c */ +}; + +/* SRAMC register */ +struct sunxi_sramc_regs { + u32 ctrl0; + u32 ctrl1; +}; + +/* 0: Disable 1: Aborted frame enable(default) */ +#define EMAC_TX_AB_M (0x1 << 0) +/* 0: CPU 1: DMA(default) */ +#define EMAC_TX_TM (0x1 << 1) + +#define EMAC_TX_SETUP (0) + +/* 0: DRQ asserted 1: DRQ automatically(default) */ +#define EMAC_RX_DRQ_MODE (0x1 << 1) +/* 0: CPU 1: DMA(default) */ +#define EMAC_RX_TM (0x1 << 2) +/* 0: Normal(default) 1: Pass all Frames */ +#define EMAC_RX_PA (0x1 << 4) +/* 0: Normal(default) 1: Pass Control Frames */ +#define EMAC_RX_PCF (0x1 << 5) +/* 0: Normal(default) 1: Pass Frames with CRC Error */ +#define EMAC_RX_PCRCE (0x1 << 6) +/* 0: Normal(default) 1: Pass Frames with Length Error */ +#define EMAC_RX_PLE (0x1 << 7) +/* 0: Normal 1: Pass Frames length out of range(default) */ +#define EMAC_RX_POR (0x1 << 8) +/* 0: Not accept 1: Accept unicast Packets(default) */ +#define EMAC_RX_UCAD (0x1 << 16) +/* 0: Normal(default) 1: DA Filtering */ +#define EMAC_RX_DAF (0x1 << 17) +/* 0: Not accept 1: Accept multicast Packets(default) */ +#define EMAC_RX_MCO (0x1 << 20) +/* 0: Disable(default) 1: Enable Hash filter */ +#define EMAC_RX_MHF (0x1 << 21) +/* 0: Not accept 1: Accept Broadcast Packets(default) */ +#define EMAC_RX_BCO (0x1 << 22) +/* 0: Disable(default) 1: Enable SA Filtering */ +#define EMAC_RX_SAF (0x1 << 24) +/* 0: Normal(default) 1: Inverse Filtering */ +#define EMAC_RX_SAIF (0x1 << 25) + +#define EMAC_RX_SETUP (EMAC_RX_POR | EMAC_RX_UCAD | EMAC_RX_DAF | \ + EMAC_RX_MCO | EMAC_RX_BCO) + +/* 0: Disable 1: Enable Receive Flow Control(default) */ +#define EMAC_MAC_CTL0_RFC (0x1 << 2) +/* 0: Disable 1: Enable Transmit Flow Control(default) */ +#define EMAC_MAC_CTL0_TFC (0x1 << 3) + +#define EMAC_MAC_CTL0_SETUP (EMAC_MAC_CTL0_RFC | EMAC_MAC_CTL0_TFC) + +/* 0: Disable 1: Enable MAC Frame Length Checking(default) */ +#define EMAC_MAC_CTL1_FLC (0x1 << 1) +/* 0: Disable(default) 1: Enable Huge Frame */ +#define EMAC_MAC_CTL1_HF (0x1 << 2) +/* 0: Disable(default) 1: Enable MAC Delayed CRC */ +#define EMAC_MAC_CTL1_DCRC (0x1 << 3) +/* 0: Disable 1: Enable MAC CRC(default) */ +#define EMAC_MAC_CTL1_CRC (0x1 << 4) +/* 0: Disable 1: Enable MAC PAD Short frames(default) */ +#define EMAC_MAC_CTL1_PC (0x1 << 5) +/* 0: Disable(default) 1: Enable MAC PAD Short frames and append CRC */ +#define EMAC_MAC_CTL1_VC (0x1 << 6) +/* 0: Disable(default) 1: Enable MAC auto detect Short frames */ +#define EMAC_MAC_CTL1_ADP (0x1 << 7) +/* 0: Disable(default) 1: Enable */ +#define EMAC_MAC_CTL1_PRE (0x1 << 8) +/* 0: Disable(default) 1: Enable */ +#define EMAC_MAC_CTL1_LPE (0x1 << 9) +/* 0: Disable(default) 1: Enable no back off */ +#define EMAC_MAC_CTL1_NB (0x1 << 12) +/* 0: Disable(default) 1: Enable */ +#define EMAC_MAC_CTL1_BNB (0x1 << 13) +/* 0: Disable(default) 1: Enable */ +#define EMAC_MAC_CTL1_ED (0x1 << 14) + +#define EMAC_MAC_CTL1_SETUP (EMAC_MAC_CTL1_FLC | EMAC_MAC_CTL1_CRC | \ + EMAC_MAC_CTL1_PC) + +#define EMAC_MAC_IPGT 0x15 + +#define EMAC_MAC_NBTB_IPG1 0xc +#define EMAC_MAC_NBTB_IPG2 0x12 + +#define EMAC_MAC_CW 0x37 +#define EMAC_MAC_RM 0xf + +#define EMAC_MAC_MFL 0x0600 + +/* Receive status */ +#define EMAC_CRCERR (0x1 << 4) +#define EMAC_LENERR (0x3 << 5) + +#define EMAC_RX_BUFSIZE 2000 + +struct emac_eth_dev { + struct emac_regs *regs; + struct mii_dev *bus; + struct phy_device *phydev; + int link_printed; +#ifdef CONFIG_DM_ETH + uchar rx_buf[EMAC_RX_BUFSIZE]; +#endif +}; + +struct emac_rxhdr { + s16 rx_len; + u16 rx_status; +}; + +static void emac_inblk_32bit(void *reg, void *data, int count) +{ + int cnt = (count + 3) >> 2; + + if (cnt) { + u32 *buf = data; + + do { + u32 x = readl(reg); + *buf++ = x; + } while (--cnt); + } +} + +static void emac_outblk_32bit(void *reg, void *data, int count) +{ + int cnt = (count + 3) >> 2; + + if (cnt) { + const u32 *buf = data; + + do { + writel(*buf++, reg); + } while (--cnt); + } +} + +/* Read a word from phyxcer */ +static int emac_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) +{ + struct emac_eth_dev *priv = bus->priv; + struct emac_regs *regs = priv->regs; + + /* issue the phy address and reg */ + writel(addr << 8 | reg, ®s->mac_madr); + + /* pull up the phy io line */ + writel(0x1, ®s->mac_mcmd); + + /* Wait read complete */ + mdelay(1); + + /* push down the phy io line */ + writel(0x0, ®s->mac_mcmd); + + /* And read data */ + return readl(®s->mac_mrdd); +} + +/* Write a word to phyxcer */ +static int emac_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, + u16 value) +{ + struct emac_eth_dev *priv = bus->priv; + struct emac_regs *regs = priv->regs; + + /* issue the phy address and reg */ + writel(addr << 8 | reg, ®s->mac_madr); + + /* pull up the phy io line */ + writel(0x1, ®s->mac_mcmd); + + /* Wait write complete */ + mdelay(1); + + /* push down the phy io line */ + writel(0x0, ®s->mac_mcmd); + + /* and write data */ + writel(value, ®s->mac_mwtd); + + return 0; +} + +static int sunxi_emac_init_phy(struct emac_eth_dev *priv, void *dev) +{ + int ret, mask = 0xffffffff; + +#ifdef CONFIG_PHY_ADDR + mask = 1 << CONFIG_PHY_ADDR; +#endif + + priv->bus = mdio_alloc(); + if (!priv->bus) { + printf("Failed to allocate MDIO bus\n"); + return -ENOMEM; + } + + priv->bus->read = emac_mdio_read; + priv->bus->write = emac_mdio_write; + priv->bus->priv = priv; + strcpy(priv->bus->name, "emac"); + + ret = mdio_register(priv->bus); + if (ret) + return ret; + + priv->phydev = phy_find_by_mask(priv->bus, mask, + PHY_INTERFACE_MODE_MII); + if (!priv->phydev) + return -ENODEV; + + phy_connect_dev(priv->phydev, dev); + phy_config(priv->phydev); + + return 0; +} + +static void emac_setup(struct emac_eth_dev *priv) +{ + struct emac_regs *regs = priv->regs; + u32 reg_val; + + /* Set up TX */ + writel(EMAC_TX_SETUP, ®s->tx_mode); + + /* Set up RX */ + writel(EMAC_RX_SETUP, ®s->rx_ctl); + + /* Set MAC */ + /* Set MAC CTL0 */ + writel(EMAC_MAC_CTL0_SETUP, ®s->mac_ctl0); + + /* Set MAC CTL1 */ + reg_val = 0; + if (priv->phydev->duplex == DUPLEX_FULL) + reg_val = (0x1 << 0); + writel(EMAC_MAC_CTL1_SETUP | reg_val, ®s->mac_ctl1); + + /* Set up IPGT */ + writel(EMAC_MAC_IPGT, ®s->mac_ipgt); + + /* Set up IPGR */ + writel(EMAC_MAC_NBTB_IPG2 | (EMAC_MAC_NBTB_IPG1 << 8), ®s->mac_ipgr); + + /* Set up Collison window */ + writel(EMAC_MAC_RM | (EMAC_MAC_CW << 8), ®s->mac_clrt); + + /* Set up Max Frame Length */ + writel(EMAC_MAC_MFL, ®s->mac_maxf); +} + +static void emac_reset(struct emac_eth_dev *priv) +{ + struct emac_regs *regs = priv->regs; + + debug("resetting device\n"); + + /* RESET device */ + writel(0, ®s->ctl); + udelay(200); + + writel(1, ®s->ctl); + udelay(200); +} + +static int _sunxi_emac_eth_init(struct emac_eth_dev *priv, u8 *enetaddr) +{ + struct emac_regs *regs = priv->regs; + int ret; + + /* Init EMAC */ + + /* Flush RX FIFO */ + setbits_le32(®s->rx_ctl, 0x8); + udelay(1); + + /* Init MAC */ + + /* Soft reset MAC */ + clrbits_le32(®s->mac_ctl0, 0x1 << 15); + + /* Clear RX counter */ + writel(0x0, ®s->rx_fbc); + udelay(1); + + /* Set up EMAC */ + emac_setup(priv); + + writel(enetaddr[0] << 16 | enetaddr[1] << 8 | enetaddr[2], + ®s->mac_a1); + writel(enetaddr[3] << 16 | enetaddr[4] << 8 | enetaddr[5], + ®s->mac_a0); + + mdelay(1); + + emac_reset(priv); + + /* PHY POWER UP */ + ret = phy_startup(priv->phydev); + if (ret) { + printf("Could not initialize PHY %s\n", + priv->phydev->dev->name); + return ret; + } + + /* Print link status only once */ + if (!priv->link_printed) { + printf("ENET Speed is %d Mbps - %s duplex connection\n", + priv->phydev->speed, + priv->phydev->duplex ? "FULL" : "HALF"); + priv->link_printed = 1; + } + + /* Set EMAC SPEED depend on PHY */ + if (priv->phydev->speed == SPEED_100) + setbits_le32(®s->mac_supp, 1 << 8); + else + clrbits_le32(®s->mac_supp, 1 << 8); + + /* Set duplex depend on phy */ + if (priv->phydev->duplex == DUPLEX_FULL) + setbits_le32(®s->mac_ctl1, 1 << 0); + else + clrbits_le32(®s->mac_ctl1, 1 << 0); + + /* Enable RX/TX */ + setbits_le32(®s->ctl, 0x7); + + return 0; +} + +static int _sunxi_emac_eth_recv(struct emac_eth_dev *priv, void *packet) +{ + struct emac_regs *regs = priv->regs; + struct emac_rxhdr rxhdr; + u32 rxcount; + u32 reg_val; + int rx_len; + int rx_status; + int good_packet; + + /* Check packet ready or not */ + + /* Race warning: The first packet might arrive with + * the interrupts disabled, but the second will fix + */ + rxcount = readl(®s->rx_fbc); + if (!rxcount) { + /* Had one stuck? */ + rxcount = readl(®s->rx_fbc); + if (!rxcount) + return -EAGAIN; + } + + reg_val = readl(®s->rx_io_data); + if (reg_val != 0x0143414d) { + /* Disable RX */ + clrbits_le32(®s->ctl, 0x1 << 2); + + /* Flush RX FIFO */ + setbits_le32(®s->rx_ctl, 0x1 << 3); + while (readl(®s->rx_ctl) & (0x1 << 3)) + ; + + /* Enable RX */ + setbits_le32(®s->ctl, 0x1 << 2); + + return -EAGAIN; + } + + /* A packet ready now + * Get status/length + */ + good_packet = 1; + + emac_inblk_32bit(®s->rx_io_data, &rxhdr, sizeof(rxhdr)); + + rx_len = rxhdr.rx_len; + rx_status = rxhdr.rx_status; + + /* Packet Status check */ + if (rx_len < 0x40) { + good_packet = 0; + debug("RX: Bad Packet (runt)\n"); + } + + /* rx_status is identical to RSR register. */ + if (0 & rx_status & (EMAC_CRCERR | EMAC_LENERR)) { + good_packet = 0; + if (rx_status & EMAC_CRCERR) + printf("crc error\n"); + if (rx_status & EMAC_LENERR) + printf("length error\n"); + } + + /* Move data from EMAC */ + if (good_packet) { + if (rx_len > EMAC_RX_BUFSIZE) { + printf("Received packet is too big (len=%d)\n", rx_len); + return -EMSGSIZE; + } + emac_inblk_32bit((void *)®s->rx_io_data, packet, rx_len); + return rx_len; + } + + return -EIO; /* Bad packet */ +} + +static int _sunxi_emac_eth_send(struct emac_eth_dev *priv, void *packet, + int len) +{ + struct emac_regs *regs = priv->regs; + + /* Select channel 0 */ + writel(0, ®s->tx_ins); + + /* Write packet */ + emac_outblk_32bit((void *)®s->tx_io_data, packet, len); + + /* Set TX len */ + writel(len, ®s->tx_pl0); + + /* Start translate from fifo to phy */ + setbits_le32(®s->tx_ctl0, 1); + + return 0; +} + +static void sunxi_emac_board_setup(struct emac_eth_dev *priv) +{ + struct sunxi_ccm_reg *const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + struct sunxi_sramc_regs *sram = + (struct sunxi_sramc_regs *)SUNXI_SRAMC_BASE; + struct emac_regs *regs = priv->regs; + int pin; + + /* Map SRAM to EMAC */ + setbits_le32(&sram->ctrl1, 0x5 << 2); + + /* Configure pin mux settings for MII Ethernet */ + for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(17); pin++) + sunxi_gpio_set_cfgpin(pin, SUNXI_GPA_EMAC); + + /* Set up clock gating */ + setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_EMAC); + + /* Set MII clock */ + clrsetbits_le32(®s->mac_mcfg, 0xf << 2, 0xd << 2); +} + +static int sunxi_emac_eth_start(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + + return _sunxi_emac_eth_init(dev->priv, pdata->enetaddr); +} + +static int sunxi_emac_eth_send(struct udevice *dev, void *packet, int length) +{ + struct emac_eth_dev *priv = dev_get_priv(dev); + + return _sunxi_emac_eth_send(priv, packet, length); +} + +static int sunxi_emac_eth_recv(struct udevice *dev, int flags, uchar **packetp) +{ + struct emac_eth_dev *priv = dev_get_priv(dev); + int rx_len; + + rx_len = _sunxi_emac_eth_recv(priv, priv->rx_buf); + *packetp = priv->rx_buf; + + return rx_len; +} + +static void sunxi_emac_eth_stop(struct udevice *dev) +{ + /* Nothing to do here */ +} + +static int sunxi_emac_eth_probe(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + struct emac_eth_dev *priv = dev_get_priv(dev); + + priv->regs = (struct emac_regs *)pdata->iobase; + sunxi_emac_board_setup(priv); + + return sunxi_emac_init_phy(priv, dev); +} + +static const struct eth_ops sunxi_emac_eth_ops = { + .start = sunxi_emac_eth_start, + .send = sunxi_emac_eth_send, + .recv = sunxi_emac_eth_recv, + .stop = sunxi_emac_eth_stop, +}; + +static int sunxi_emac_eth_ofdata_to_platdata(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + + pdata->iobase = dev_get_addr(dev); + + return 0; +} + +static const struct udevice_id sunxi_emac_eth_ids[] = { + { .compatible = "allwinner,sun4i-a10-emac" }, + { } +}; + +U_BOOT_DRIVER(eth_sunxi_emac) = { + .name = "eth_sunxi_emac", + .id = UCLASS_ETH, + .of_match = sunxi_emac_eth_ids, + .ofdata_to_platdata = sunxi_emac_eth_ofdata_to_platdata, + .probe = sunxi_emac_eth_probe, + .ops = &sunxi_emac_eth_ops, + .priv_auto_alloc_size = sizeof(struct emac_eth_dev), + .platdata_auto_alloc_size = sizeof(struct eth_pdata), +}; diff --git a/sources/uboot-be550/drivers/net/tsec.c b/sources/uboot-be550/drivers/net/tsec.c new file mode 100644 index 00000000..4bdc188c --- /dev/null +++ b/sources/uboot-be550/drivers/net/tsec.c @@ -0,0 +1,692 @@ +/* + * Freescale Three Speed Ethernet Controller driver + * + * This software may be used and distributed according to the + * terms of the GNU Public License, Version 2, incorporated + * herein by reference. + * + * Copyright 2004-2011, 2013 Freescale Semiconductor, Inc. + * (C) Copyright 2003, Motorola, Inc. + * author Andy Fleming + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define TX_BUF_CNT 2 + +static uint rx_idx; /* index of the current RX buffer */ +static uint tx_idx; /* index of the current TX buffer */ + +#ifdef __GNUC__ +static struct txbd8 __iomem txbd[TX_BUF_CNT] __aligned(8); +static struct rxbd8 __iomem rxbd[PKTBUFSRX] __aligned(8); + +#else +#error "rtx must be 64-bit aligned" +#endif + +static int tsec_send(struct eth_device *dev, void *packet, int length); + +/* Default initializations for TSEC controllers. */ + +static struct tsec_info_struct tsec_info[] = { +#ifdef CONFIG_TSEC1 + STD_TSEC_INFO(1), /* TSEC1 */ +#endif +#ifdef CONFIG_TSEC2 + STD_TSEC_INFO(2), /* TSEC2 */ +#endif +#ifdef CONFIG_MPC85XX_FEC + { + .regs = TSEC_GET_REGS(2, 0x2000), + .devname = CONFIG_MPC85XX_FEC_NAME, + .phyaddr = FEC_PHY_ADDR, + .flags = FEC_FLAGS, + .mii_devname = DEFAULT_MII_NAME + }, /* FEC */ +#endif +#ifdef CONFIG_TSEC3 + STD_TSEC_INFO(3), /* TSEC3 */ +#endif +#ifdef CONFIG_TSEC4 + STD_TSEC_INFO(4), /* TSEC4 */ +#endif +}; + +#define TBIANA_SETTINGS ( \ + TBIANA_ASYMMETRIC_PAUSE \ + | TBIANA_SYMMETRIC_PAUSE \ + | TBIANA_FULL_DUPLEX \ + ) + +/* By default force the TBI PHY into 1000Mbps full duplex when in SGMII mode */ +#ifndef CONFIG_TSEC_TBICR_SETTINGS +#define CONFIG_TSEC_TBICR_SETTINGS ( \ + TBICR_PHY_RESET \ + | TBICR_ANEG_ENABLE \ + | TBICR_FULL_DUPLEX \ + | TBICR_SPEED1_SET \ + ) +#endif /* CONFIG_TSEC_TBICR_SETTINGS */ + +/* Configure the TBI for SGMII operation */ +static void tsec_configure_serdes(struct tsec_private *priv) +{ + /* Access TBI PHY registers at given TSEC register offset as opposed + * to the register offset used for external PHY accesses */ + tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa), + 0, TBI_ANA, TBIANA_SETTINGS); + tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa), + 0, TBI_TBICON, TBICON_CLK_SELECT); + tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa), + 0, TBI_CR, CONFIG_TSEC_TBICR_SETTINGS); +} + +#ifdef CONFIG_MCAST_TFTP + +/* CREDITS: linux gianfar driver, slightly adjusted... thanx. */ + +/* Set the appropriate hash bit for the given addr */ + +/* The algorithm works like so: + * 1) Take the Destination Address (ie the multicast address), and + * do a CRC on it (little endian), and reverse the bits of the + * result. + * 2) Use the 8 most significant bits as a hash into a 256-entry + * table. The table is controlled through 8 32-bit registers: + * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is entry + * 255. This means that the 3 most significant bits in the + * hash index which gaddr register to use, and the 5 other bits + * indicate which bit (assuming an IBM numbering scheme, which + * for PowerPC (tm) is usually the case) in the register holds + * the entry. */ +static int +tsec_mcast_addr(struct eth_device *dev, const u8 *mcast_mac, u8 set) +{ + struct tsec_private *priv = (struct tsec_private *)dev->priv; + struct tsec __iomem *regs = priv->regs; + u32 result, value; + u8 whichbit, whichreg; + + result = ether_crc(MAC_ADDR_LEN, mcast_mac); + whichbit = (result >> 24) & 0x1f; /* the 5 LSB = which bit to set */ + whichreg = result >> 29; /* the 3 MSB = which reg to set it in */ + + value = 1 << (31-whichbit); + + if (set) + setbits_be32(®s->hash.gaddr0 + whichreg, value); + else + clrbits_be32(®s->hash.gaddr0 + whichreg, value); + + return 0; +} +#endif /* Multicast TFTP ? */ + +/* Initialized required registers to appropriate values, zeroing + * those we don't care about (unless zero is bad, in which case, + * choose a more appropriate value) + */ +static void init_registers(struct tsec __iomem *regs) +{ + /* Clear IEVENT */ + out_be32(®s->ievent, IEVENT_INIT_CLEAR); + + out_be32(®s->imask, IMASK_INIT_CLEAR); + + out_be32(®s->hash.iaddr0, 0); + out_be32(®s->hash.iaddr1, 0); + out_be32(®s->hash.iaddr2, 0); + out_be32(®s->hash.iaddr3, 0); + out_be32(®s->hash.iaddr4, 0); + out_be32(®s->hash.iaddr5, 0); + out_be32(®s->hash.iaddr6, 0); + out_be32(®s->hash.iaddr7, 0); + + out_be32(®s->hash.gaddr0, 0); + out_be32(®s->hash.gaddr1, 0); + out_be32(®s->hash.gaddr2, 0); + out_be32(®s->hash.gaddr3, 0); + out_be32(®s->hash.gaddr4, 0); + out_be32(®s->hash.gaddr5, 0); + out_be32(®s->hash.gaddr6, 0); + out_be32(®s->hash.gaddr7, 0); + + out_be32(®s->rctrl, 0x00000000); + + /* Init RMON mib registers */ + memset((void *)®s->rmon, 0, sizeof(regs->rmon)); + + out_be32(®s->rmon.cam1, 0xffffffff); + out_be32(®s->rmon.cam2, 0xffffffff); + + out_be32(®s->mrblr, MRBLR_INIT_SETTINGS); + + out_be32(®s->minflr, MINFLR_INIT_SETTINGS); + + out_be32(®s->attr, ATTR_INIT_SETTINGS); + out_be32(®s->attreli, ATTRELI_INIT_SETTINGS); + +} + +/* Configure maccfg2 based on negotiated speed and duplex + * reported by PHY handling code + */ +static void adjust_link(struct tsec_private *priv, struct phy_device *phydev) +{ + struct tsec __iomem *regs = priv->regs; + u32 ecntrl, maccfg2; + + if (!phydev->link) { + printf("%s: No link.\n", phydev->dev->name); + return; + } + + /* clear all bits relative with interface mode */ + ecntrl = in_be32(®s->ecntrl); + ecntrl &= ~ECNTRL_R100; + + maccfg2 = in_be32(®s->maccfg2); + maccfg2 &= ~(MACCFG2_IF | MACCFG2_FULL_DUPLEX); + + if (phydev->duplex) + maccfg2 |= MACCFG2_FULL_DUPLEX; + + switch (phydev->speed) { + case 1000: + maccfg2 |= MACCFG2_GMII; + break; + case 100: + case 10: + maccfg2 |= MACCFG2_MII; + + /* Set R100 bit in all modes although + * it is only used in RGMII mode + */ + if (phydev->speed == 100) + ecntrl |= ECNTRL_R100; + break; + default: + printf("%s: Speed was bad\n", phydev->dev->name); + break; + } + + out_be32(®s->ecntrl, ecntrl); + out_be32(®s->maccfg2, maccfg2); + + printf("Speed: %d, %s duplex%s\n", phydev->speed, + (phydev->duplex) ? "full" : "half", + (phydev->port == PORT_FIBRE) ? ", fiber mode" : ""); +} + +#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 +/* + * When MACCFG1[Rx_EN] is enabled during system boot as part + * of the eTSEC port initialization sequence, + * the eTSEC Rx logic may not be properly initialized. + */ +void redundant_init(struct eth_device *dev) +{ + struct tsec_private *priv = dev->priv; + struct tsec __iomem *regs = priv->regs; + uint t, count = 0; + int fail = 1; + static const u8 pkt[] = { + 0x00, 0x1e, 0x4f, 0x12, 0xcb, 0x2c, 0x00, 0x25, + 0x64, 0xbb, 0xd1, 0xab, 0x08, 0x00, 0x45, 0x00, + 0x00, 0x5c, 0xdd, 0x22, 0x00, 0x00, 0x80, 0x01, + 0x1f, 0x71, 0x0a, 0xc1, 0x14, 0x22, 0x0a, 0xc1, + 0x14, 0x6a, 0x08, 0x00, 0xef, 0x7e, 0x02, 0x00, + 0x94, 0x05, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, + 0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, + 0x6f, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, + 0x77, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, + 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, + 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, + 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, + 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70, + 0x71, 0x72}; + + /* Enable promiscuous mode */ + setbits_be32(®s->rctrl, 0x8); + /* Enable loopback mode */ + setbits_be32(®s->maccfg1, MACCFG1_LOOPBACK); + /* Enable transmit and receive */ + setbits_be32(®s->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN); + + /* Tell the DMA it is clear to go */ + setbits_be32(®s->dmactrl, DMACTRL_INIT_SETTINGS); + out_be32(®s->tstat, TSTAT_CLEAR_THALT); + out_be32(®s->rstat, RSTAT_CLEAR_RHALT); + clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS); + + do { + uint16_t status; + tsec_send(dev, (void *)pkt, sizeof(pkt)); + + /* Wait for buffer to be received */ + for (t = 0; in_be16(&rxbd[rx_idx].status) & RXBD_EMPTY; t++) { + if (t >= 10 * TOUT_LOOP) { + printf("%s: tsec: rx error\n", dev->name); + break; + } + } + + if (!memcmp(pkt, (void *)net_rx_packets[rx_idx], sizeof(pkt))) + fail = 0; + + out_be16(&rxbd[rx_idx].length, 0); + status = RXBD_EMPTY; + if ((rx_idx + 1) == PKTBUFSRX) + status |= RXBD_WRAP; + out_be16(&rxbd[rx_idx].status, status); + rx_idx = (rx_idx + 1) % PKTBUFSRX; + + if (in_be32(®s->ievent) & IEVENT_BSY) { + out_be32(®s->ievent, IEVENT_BSY); + out_be32(®s->rstat, RSTAT_CLEAR_RHALT); + } + if (fail) { + printf("loopback recv packet error!\n"); + clrbits_be32(®s->maccfg1, MACCFG1_RX_EN); + udelay(1000); + setbits_be32(®s->maccfg1, MACCFG1_RX_EN); + } + } while ((count++ < 4) && (fail == 1)); + + if (fail) + panic("eTSEC init fail!\n"); + /* Disable promiscuous mode */ + clrbits_be32(®s->rctrl, 0x8); + /* Disable loopback mode */ + clrbits_be32(®s->maccfg1, MACCFG1_LOOPBACK); +} +#endif + +/* Set up the buffers and their descriptors, and bring up the + * interface + */ +static void startup_tsec(struct eth_device *dev) +{ + struct tsec_private *priv = (struct tsec_private *)dev->priv; + struct tsec __iomem *regs = priv->regs; + uint16_t status; + int i; + + /* reset the indices to zero */ + rx_idx = 0; + tx_idx = 0; +#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 + uint svr; +#endif + + /* Point to the buffer descriptors */ + out_be32(®s->tbase, (u32)&txbd[0]); + out_be32(®s->rbase, (u32)&rxbd[0]); + + /* Initialize the Rx Buffer descriptors */ + for (i = 0; i < PKTBUFSRX; i++) { + out_be16(&rxbd[i].status, RXBD_EMPTY); + out_be16(&rxbd[i].length, 0); + out_be32(&rxbd[i].bufptr, (u32)net_rx_packets[i]); + } + status = in_be16(&rxbd[PKTBUFSRX - 1].status); + out_be16(&rxbd[PKTBUFSRX - 1].status, status | RXBD_WRAP); + + /* Initialize the TX Buffer Descriptors */ + for (i = 0; i < TX_BUF_CNT; i++) { + out_be16(&txbd[i].status, 0); + out_be16(&txbd[i].length, 0); + out_be32(&txbd[i].bufptr, 0); + } + status = in_be16(&txbd[TX_BUF_CNT - 1].status); + out_be16(&txbd[TX_BUF_CNT - 1].status, status | TXBD_WRAP); + +#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 + svr = get_svr(); + if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0)) + redundant_init(dev); +#endif + /* Enable Transmit and Receive */ + setbits_be32(®s->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN); + + /* Tell the DMA it is clear to go */ + setbits_be32(®s->dmactrl, DMACTRL_INIT_SETTINGS); + out_be32(®s->tstat, TSTAT_CLEAR_THALT); + out_be32(®s->rstat, RSTAT_CLEAR_RHALT); + clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS); +} + +/* This returns the status bits of the device. The return value + * is never checked, and this is what the 8260 driver did, so we + * do the same. Presumably, this would be zero if there were no + * errors + */ +static int tsec_send(struct eth_device *dev, void *packet, int length) +{ + struct tsec_private *priv = (struct tsec_private *)dev->priv; + struct tsec __iomem *regs = priv->regs; + uint16_t status; + int result = 0; + int i; + + /* Find an empty buffer descriptor */ + for (i = 0; in_be16(&txbd[tx_idx].status) & TXBD_READY; i++) { + if (i >= TOUT_LOOP) { + debug("%s: tsec: tx buffers full\n", dev->name); + return result; + } + } + + out_be32(&txbd[tx_idx].bufptr, (u32)packet); + out_be16(&txbd[tx_idx].length, length); + status = in_be16(&txbd[tx_idx].status); + out_be16(&txbd[tx_idx].status, status | + (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT)); + + /* Tell the DMA to go */ + out_be32(®s->tstat, TSTAT_CLEAR_THALT); + + /* Wait for buffer to be transmitted */ + for (i = 0; in_be16(&txbd[tx_idx].status) & TXBD_READY; i++) { + if (i >= TOUT_LOOP) { + debug("%s: tsec: tx error\n", dev->name); + return result; + } + } + + tx_idx = (tx_idx + 1) % TX_BUF_CNT; + result = in_be16(&txbd[tx_idx].status) & TXBD_STATS; + + return result; +} + +static int tsec_recv(struct eth_device *dev) +{ + struct tsec_private *priv = (struct tsec_private *)dev->priv; + struct tsec __iomem *regs = priv->regs; + + while (!(in_be16(&rxbd[rx_idx].status) & RXBD_EMPTY)) { + int length = in_be16(&rxbd[rx_idx].length); + uint16_t status = in_be16(&rxbd[rx_idx].status); + + /* Send the packet up if there were no errors */ + if (!(status & RXBD_STATS)) + net_process_received_packet(net_rx_packets[rx_idx], + length - 4); + else + printf("Got error %x\n", (status & RXBD_STATS)); + + out_be16(&rxbd[rx_idx].length, 0); + + status = RXBD_EMPTY; + /* Set the wrap bit if this is the last element in the list */ + if ((rx_idx + 1) == PKTBUFSRX) + status |= RXBD_WRAP; + out_be16(&rxbd[rx_idx].status, status); + + rx_idx = (rx_idx + 1) % PKTBUFSRX; + } + + if (in_be32(®s->ievent) & IEVENT_BSY) { + out_be32(®s->ievent, IEVENT_BSY); + out_be32(®s->rstat, RSTAT_CLEAR_RHALT); + } + + return -1; + +} + +/* Stop the interface */ +static void tsec_halt(struct eth_device *dev) +{ + struct tsec_private *priv = (struct tsec_private *)dev->priv; + struct tsec __iomem *regs = priv->regs; + + clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS); + setbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS); + + while ((in_be32(®s->ievent) & (IEVENT_GRSC | IEVENT_GTSC)) + != (IEVENT_GRSC | IEVENT_GTSC)) + ; + + clrbits_be32(®s->maccfg1, MACCFG1_TX_EN | MACCFG1_RX_EN); + + /* Shut down the PHY, as needed */ + phy_shutdown(priv->phydev); +} + +/* Initializes data structures and registers for the controller, + * and brings the interface up. Returns the link status, meaning + * that it returns success if the link is up, failure otherwise. + * This allows u-boot to find the first active controller. + */ +static int tsec_init(struct eth_device *dev, bd_t * bd) +{ + struct tsec_private *priv = (struct tsec_private *)dev->priv; + struct tsec __iomem *regs = priv->regs; + u32 tempval; + int ret; + + /* Make sure the controller is stopped */ + tsec_halt(dev); + + /* Init MACCFG2. Defaults to GMII */ + out_be32(®s->maccfg2, MACCFG2_INIT_SETTINGS); + + /* Init ECNTRL */ + out_be32(®s->ecntrl, ECNTRL_INIT_SETTINGS); + + /* Copy the station address into the address registers. + * For a station address of 0x12345678ABCD in transmission + * order (BE), MACnADDR1 is set to 0xCDAB7856 and + * MACnADDR2 is set to 0x34120000. + */ + tempval = (dev->enetaddr[5] << 24) | (dev->enetaddr[4] << 16) | + (dev->enetaddr[3] << 8) | dev->enetaddr[2]; + + out_be32(®s->macstnaddr1, tempval); + + tempval = (dev->enetaddr[1] << 24) | (dev->enetaddr[0] << 16); + + out_be32(®s->macstnaddr2, tempval); + + /* Clear out (for the most part) the other registers */ + init_registers(regs); + + /* Ready the device for tx/rx */ + startup_tsec(dev); + + /* Start up the PHY */ + ret = phy_startup(priv->phydev); + if (ret) { + printf("Could not initialize PHY %s\n", + priv->phydev->dev->name); + return ret; + } + + adjust_link(priv, priv->phydev); + + /* If there's no link, fail */ + return priv->phydev->link ? 0 : -1; +} + +static phy_interface_t tsec_get_interface(struct tsec_private *priv) +{ + struct tsec __iomem *regs = priv->regs; + u32 ecntrl; + + ecntrl = in_be32(®s->ecntrl); + + if (ecntrl & ECNTRL_SGMII_MODE) + return PHY_INTERFACE_MODE_SGMII; + + if (ecntrl & ECNTRL_TBI_MODE) { + if (ecntrl & ECNTRL_REDUCED_MODE) + return PHY_INTERFACE_MODE_RTBI; + else + return PHY_INTERFACE_MODE_TBI; + } + + if (ecntrl & ECNTRL_REDUCED_MODE) { + if (ecntrl & ECNTRL_REDUCED_MII_MODE) + return PHY_INTERFACE_MODE_RMII; + else { + phy_interface_t interface = priv->interface; + + /* + * This isn't autodetected, so it must + * be set by the platform code. + */ + if ((interface == PHY_INTERFACE_MODE_RGMII_ID) || + (interface == PHY_INTERFACE_MODE_RGMII_TXID) || + (interface == PHY_INTERFACE_MODE_RGMII_RXID)) + return interface; + + return PHY_INTERFACE_MODE_RGMII; + } + } + + if (priv->flags & TSEC_GIGABIT) + return PHY_INTERFACE_MODE_GMII; + + return PHY_INTERFACE_MODE_MII; +} + + +/* Discover which PHY is attached to the device, and configure it + * properly. If the PHY is not recognized, then return 0 + * (failure). Otherwise, return 1 + */ +static int init_phy(struct eth_device *dev) +{ + struct tsec_private *priv = (struct tsec_private *)dev->priv; + struct phy_device *phydev; + struct tsec __iomem *regs = priv->regs; + u32 supported = (SUPPORTED_10baseT_Half | + SUPPORTED_10baseT_Full | + SUPPORTED_100baseT_Half | + SUPPORTED_100baseT_Full); + + if (priv->flags & TSEC_GIGABIT) + supported |= SUPPORTED_1000baseT_Full; + + /* Assign a Physical address to the TBI */ + out_be32(®s->tbipa, CONFIG_SYS_TBIPA_VALUE); + + priv->interface = tsec_get_interface(priv); + + if (priv->interface == PHY_INTERFACE_MODE_SGMII) + tsec_configure_serdes(priv); + + phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface); + if (!phydev) + return 0; + + phydev->supported &= supported; + phydev->advertising = phydev->supported; + + priv->phydev = phydev; + + phy_config(phydev); + + return 1; +} + +/* Initialize device structure. Returns success if PHY + * initialization succeeded (i.e. if it recognizes the PHY) + */ +static int tsec_initialize(bd_t *bis, struct tsec_info_struct *tsec_info) +{ + struct eth_device *dev; + int i; + struct tsec_private *priv; + + dev = (struct eth_device *)malloc(sizeof *dev); + + if (NULL == dev) + return 0; + + memset(dev, 0, sizeof *dev); + + priv = (struct tsec_private *)malloc(sizeof(*priv)); + + if (NULL == priv) + return 0; + + priv->regs = tsec_info->regs; + priv->phyregs_sgmii = tsec_info->miiregs_sgmii; + + priv->phyaddr = tsec_info->phyaddr; + priv->flags = tsec_info->flags; + + sprintf(dev->name, tsec_info->devname); + priv->interface = tsec_info->interface; + priv->bus = miiphy_get_dev_by_name(tsec_info->mii_devname); + dev->iobase = 0; + dev->priv = priv; + dev->init = tsec_init; + dev->halt = tsec_halt; + dev->send = tsec_send; + dev->recv = tsec_recv; +#ifdef CONFIG_MCAST_TFTP + dev->mcast = tsec_mcast_addr; +#endif + + /* Tell u-boot to get the addr from the env */ + for (i = 0; i < 6; i++) + dev->enetaddr[i] = 0; + + eth_register(dev); + + /* Reset the MAC */ + setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET); + udelay(2); /* Soft Reset must be asserted for 3 TX clocks */ + clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET); + + /* Try to initialize PHY here, and return */ + return init_phy(dev); +} + +/* + * Initialize all the TSEC devices + * + * Returns the number of TSEC devices that were initialized + */ +int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsecs, int num) +{ + int i; + int ret, count = 0; + + for (i = 0; i < num; i++) { + ret = tsec_initialize(bis, &tsecs[i]); + if (ret > 0) + count += ret; + } + + return count; +} + +int tsec_standard_init(bd_t *bis) +{ + struct fsl_pq_mdio_info info; + + info.regs = TSEC_GET_MDIO_REGS_BASE(1); + info.name = DEFAULT_MII_NAME; + + fsl_pq_mdio_init(bis, &info); + + return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info)); +} diff --git a/sources/uboot-be550/drivers/net/tsi108_eth.c b/sources/uboot-be550/drivers/net/tsi108_eth.c new file mode 100644 index 00000000..9da59a01 --- /dev/null +++ b/sources/uboot-be550/drivers/net/tsi108_eth.c @@ -0,0 +1,1016 @@ +/*********************************************************************** + * + * Copyright (c) 2005 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Description: + * Ethernet interface for Tundra TSI108 bridge chip + * + ***********************************************************************/ + +#include + +#if !defined(CONFIG_TSI108_ETH_NUM_PORTS) || (CONFIG_TSI108_ETH_NUM_PORTS > 2) +#error "CONFIG_TSI108_ETH_NUM_PORTS must be defined as 1 or 2" +#endif + +#include +#include +#include +#include +#include + +#ifdef DEBUG +#define TSI108_ETH_DEBUG 7 +#else +#define TSI108_ETH_DEBUG 0 +#endif + +#if TSI108_ETH_DEBUG > 0 +#define debug_lev(lev, fmt, args...) \ +if (lev <= TSI108_ETH_DEBUG) \ +printf ("%s %d: " fmt, __FUNCTION__, __LINE__, ##args) +#else +#define debug_lev(lev, fmt, args...) do{}while(0) +#endif + +#define RX_PRINT_ERRORS +#define TX_PRINT_ERRORS + +#define ETH_BASE (CONFIG_SYS_TSI108_CSR_BASE + 0x6000) + +#define ETH_PORT_OFFSET 0x400 + +#define __REG32(base, offset) (*((volatile u32 *)((char *)(base) + (offset)))) + +#define reg_MAC_CONFIG_1(base) __REG32(base, 0x00000000) +#define MAC_CONFIG_1_TX_ENABLE (0x00000001) +#define MAC_CONFIG_1_SYNC_TX_ENABLE (0x00000002) +#define MAC_CONFIG_1_RX_ENABLE (0x00000004) +#define MAC_CONFIG_1_SYNC_RX_ENABLE (0x00000008) +#define MAC_CONFIG_1_TX_FLOW_CONTROL (0x00000010) +#define MAC_CONFIG_1_RX_FLOW_CONTROL (0x00000020) +#define MAC_CONFIG_1_LOOP_BACK (0x00000100) +#define MAC_CONFIG_1_RESET_TX_FUNCTION (0x00010000) +#define MAC_CONFIG_1_RESET_RX_FUNCTION (0x00020000) +#define MAC_CONFIG_1_RESET_TX_MAC (0x00040000) +#define MAC_CONFIG_1_RESET_RX_MAC (0x00080000) +#define MAC_CONFIG_1_SIM_RESET (0x40000000) +#define MAC_CONFIG_1_SOFT_RESET (0x80000000) + +#define reg_MAC_CONFIG_2(base) __REG32(base, 0x00000004) +#define MAC_CONFIG_2_FULL_DUPLEX (0x00000001) +#define MAC_CONFIG_2_CRC_ENABLE (0x00000002) +#define MAC_CONFIG_2_PAD_CRC (0x00000004) +#define MAC_CONFIG_2_LENGTH_CHECK (0x00000010) +#define MAC_CONFIG_2_HUGE_FRAME (0x00000020) +#define MAC_CONFIG_2_INTERFACE_MODE(val) (((val) & 0x3) << 8) +#define MAC_CONFIG_2_PREAMBLE_LENGTH(val) (((val) & 0xf) << 12) +#define INTERFACE_MODE_NIBBLE 1 /* 10/100 Mb/s MII) */ +#define INTERFACE_MODE_BYTE 2 /* 1000 Mb/s GMII/TBI */ + +#define reg_MAXIMUM_FRAME_LENGTH(base) __REG32(base, 0x00000010) + +#define reg_MII_MGMT_CONFIG(base) __REG32(base, 0x00000020) +#define MII_MGMT_CONFIG_MGMT_CLOCK_SELECT(val) ((val) & 0x7) +#define MII_MGMT_CONFIG_NO_PREAMBLE (0x00000010) +#define MII_MGMT_CONFIG_SCAN_INCREMENT (0x00000020) +#define MII_MGMT_CONFIG_RESET_MGMT (0x80000000) + +#define reg_MII_MGMT_COMMAND(base) __REG32(base, 0x00000024) +#define MII_MGMT_COMMAND_READ_CYCLE (0x00000001) +#define MII_MGMT_COMMAND_SCAN_CYCLE (0x00000002) + +#define reg_MII_MGMT_ADDRESS(base) __REG32(base, 0x00000028) +#define reg_MII_MGMT_CONTROL(base) __REG32(base, 0x0000002c) +#define reg_MII_MGMT_STATUS(base) __REG32(base, 0x00000030) + +#define reg_MII_MGMT_INDICATORS(base) __REG32(base, 0x00000034) +#define MII_MGMT_INDICATORS_BUSY (0x00000001) +#define MII_MGMT_INDICATORS_SCAN (0x00000002) +#define MII_MGMT_INDICATORS_NOT_VALID (0x00000004) + +#define reg_INTERFACE_STATUS(base) __REG32(base, 0x0000003c) +#define INTERFACE_STATUS_LINK_FAIL (0x00000008) +#define INTERFACE_STATUS_EXCESS_DEFER (0x00000200) + +#define reg_STATION_ADDRESS_1(base) __REG32(base, 0x00000040) +#define reg_STATION_ADDRESS_2(base) __REG32(base, 0x00000044) + +#define reg_PORT_CONTROL(base) __REG32(base, 0x00000200) +#define PORT_CONTROL_PRI (0x00000001) +#define PORT_CONTROL_BPT (0x00010000) +#define PORT_CONTROL_SPD (0x00040000) +#define PORT_CONTROL_RBC (0x00080000) +#define PORT_CONTROL_PRB (0x00200000) +#define PORT_CONTROL_DIS (0x00400000) +#define PORT_CONTROL_TBI (0x00800000) +#define PORT_CONTROL_STE (0x10000000) +#define PORT_CONTROL_ZOR (0x20000000) +#define PORT_CONTROL_CLR (0x40000000) +#define PORT_CONTROL_SRT (0x80000000) + +#define reg_TX_CONFIG(base) __REG32(base, 0x00000220) +#define TX_CONFIG_START_Q (0x00000003) +#define TX_CONFIG_EHP (0x00400000) +#define TX_CONFIG_CHP (0x00800000) +#define TX_CONFIG_RST (0x80000000) + +#define reg_TX_CONTROL(base) __REG32(base, 0x00000224) +#define TX_CONTROL_GO (0x00008000) +#define TX_CONTROL_MP (0x01000000) +#define TX_CONTROL_EAI (0x20000000) +#define TX_CONTROL_ABT (0x40000000) +#define TX_CONTROL_EII (0x80000000) + +#define reg_TX_STATUS(base) __REG32(base, 0x00000228) +#define TX_STATUS_QUEUE_USABLE (0x0000000f) +#define TX_STATUS_CURR_Q (0x00000300) +#define TX_STATUS_ACT (0x00008000) +#define TX_STATUS_QUEUE_IDLE (0x000f0000) +#define TX_STATUS_EOQ_PENDING (0x0f000000) + +#define reg_TX_EXTENDED_STATUS(base) __REG32(base, 0x0000022c) +#define TX_EXTENDED_STATUS_END_OF_QUEUE_CONDITION (0x0000000f) +#define TX_EXTENDED_STATUS_END_OF_FRAME_CONDITION (0x00000f00) +#define TX_EXTENDED_STATUS_DESCRIPTOR_INTERRUPT_CONDITION (0x000f0000) +#define TX_EXTENDED_STATUS_ERROR_FLAG (0x0f000000) + +#define reg_TX_THRESHOLDS(base) __REG32(base, 0x00000230) + +#define reg_TX_DIAGNOSTIC_ADDR(base) __REG32(base, 0x00000270) +#define TX_DIAGNOSTIC_ADDR_INDEX (0x0000007f) +#define TX_DIAGNOSTIC_ADDR_DFR (0x40000000) +#define TX_DIAGNOSTIC_ADDR_AI (0x80000000) + +#define reg_TX_DIAGNOSTIC_DATA(base) __REG32(base, 0x00000274) + +#define reg_TX_ERROR_STATUS(base) __REG32(base, 0x00000278) +#define TX_ERROR_STATUS (0x00000278) +#define TX_ERROR_STATUS_QUEUE_0_ERROR_RESPONSE (0x0000000f) +#define TX_ERROR_STATUS_TEA_ON_QUEUE_0 (0x00000010) +#define TX_ERROR_STATUS_RER_ON_QUEUE_0 (0x00000020) +#define TX_ERROR_STATUS_TER_ON_QUEUE_0 (0x00000040) +#define TX_ERROR_STATUS_DER_ON_QUEUE_0 (0x00000080) +#define TX_ERROR_STATUS_QUEUE_1_ERROR_RESPONSE (0x00000f00) +#define TX_ERROR_STATUS_TEA_ON_QUEUE_1 (0x00001000) +#define TX_ERROR_STATUS_RER_ON_QUEUE_1 (0x00002000) +#define TX_ERROR_STATUS_TER_ON_QUEUE_1 (0x00004000) +#define TX_ERROR_STATUS_DER_ON_QUEUE_1 (0x00008000) +#define TX_ERROR_STATUS_QUEUE_2_ERROR_RESPONSE (0x000f0000) +#define TX_ERROR_STATUS_TEA_ON_QUEUE_2 (0x00100000) +#define TX_ERROR_STATUS_RER_ON_QUEUE_2 (0x00200000) +#define TX_ERROR_STATUS_TER_ON_QUEUE_2 (0x00400000) +#define TX_ERROR_STATUS_DER_ON_QUEUE_2 (0x00800000) +#define TX_ERROR_STATUS_QUEUE_3_ERROR_RESPONSE (0x0f000000) +#define TX_ERROR_STATUS_TEA_ON_QUEUE_3 (0x10000000) +#define TX_ERROR_STATUS_RER_ON_QUEUE_3 (0x20000000) +#define TX_ERROR_STATUS_TER_ON_QUEUE_3 (0x40000000) +#define TX_ERROR_STATUS_DER_ON_QUEUE_3 (0x80000000) + +#define reg_TX_QUEUE_0_CONFIG(base) __REG32(base, 0x00000280) +#define TX_QUEUE_0_CONFIG_OCN_PORT (0x0000003f) +#define TX_QUEUE_0_CONFIG_BSWP (0x00000400) +#define TX_QUEUE_0_CONFIG_WSWP (0x00000800) +#define TX_QUEUE_0_CONFIG_AM (0x00004000) +#define TX_QUEUE_0_CONFIG_GVI (0x00008000) +#define TX_QUEUE_0_CONFIG_EEI (0x00010000) +#define TX_QUEUE_0_CONFIG_ELI (0x00020000) +#define TX_QUEUE_0_CONFIG_ENI (0x00040000) +#define TX_QUEUE_0_CONFIG_ESI (0x00080000) +#define TX_QUEUE_0_CONFIG_EDI (0x00100000) + +#define reg_TX_QUEUE_0_BUF_CONFIG(base) __REG32(base, 0x00000284) +#define TX_QUEUE_0_BUF_CONFIG_OCN_PORT (0x0000003f) +#define TX_QUEUE_0_BUF_CONFIG_BURST (0x00000300) +#define TX_QUEUE_0_BUF_CONFIG_BSWP (0x00000400) +#define TX_QUEUE_0_BUF_CONFIG_WSWP (0x00000800) + +#define OCN_PORT_HLP 0 /* HLP Interface */ +#define OCN_PORT_PCI_X 1 /* PCI-X Interface */ +#define OCN_PORT_PROCESSOR_MASTER 2 /* Processor Interface (master) */ +#define OCN_PORT_PROCESSOR_SLAVE 3 /* Processor Interface (slave) */ +#define OCN_PORT_MEMORY 4 /* Memory Controller */ +#define OCN_PORT_DMA 5 /* DMA Controller */ +#define OCN_PORT_ETHERNET 6 /* Ethernet Controller */ +#define OCN_PORT_PRINT 7 /* Print Engine Interface */ + +#define reg_TX_QUEUE_0_PTR_LOW(base) __REG32(base, 0x00000288) + +#define reg_TX_QUEUE_0_PTR_HIGH(base) __REG32(base, 0x0000028c) +#define TX_QUEUE_0_PTR_HIGH_VALID (0x80000000) + +#define reg_RX_CONFIG(base) __REG32(base, 0x00000320) +#define RX_CONFIG_DEF_Q (0x00000003) +#define RX_CONFIG_EMF (0x00000100) +#define RX_CONFIG_EUF (0x00000200) +#define RX_CONFIG_BFE (0x00000400) +#define RX_CONFIG_MFE (0x00000800) +#define RX_CONFIG_UFE (0x00001000) +#define RX_CONFIG_SE (0x00002000) +#define RX_CONFIG_ABF (0x00200000) +#define RX_CONFIG_APE (0x00400000) +#define RX_CONFIG_CHP (0x00800000) +#define RX_CONFIG_RST (0x80000000) + +#define reg_RX_CONTROL(base) __REG32(base, 0x00000324) +#define GE_E0_RX_CONTROL_QUEUE_ENABLES (0x0000000f) +#define GE_E0_RX_CONTROL_GO (0x00008000) +#define GE_E0_RX_CONTROL_EAI (0x20000000) +#define GE_E0_RX_CONTROL_ABT (0x40000000) +#define GE_E0_RX_CONTROL_EII (0x80000000) + +#define reg_RX_EXTENDED_STATUS(base) __REG32(base, 0x0000032c) +#define RX_EXTENDED_STATUS (0x0000032c) +#define RX_EXTENDED_STATUS_EOQ (0x0000000f) +#define RX_EXTENDED_STATUS_EOQ_0 (0x00000001) +#define RX_EXTENDED_STATUS_EOF (0x00000f00) +#define RX_EXTENDED_STATUS_DESCRIPTOR_INTERRUPT_CONDITION (0x000f0000) +#define RX_EXTENDED_STATUS_ERROR_FLAG (0x0f000000) + +#define reg_RX_THRESHOLDS(base) __REG32(base, 0x00000330) + +#define reg_RX_DIAGNOSTIC_ADDR(base) __REG32(base, 0x00000370) +#define RX_DIAGNOSTIC_ADDR_INDEX (0x0000007f) +#define RX_DIAGNOSTIC_ADDR_DFR (0x40000000) +#define RX_DIAGNOSTIC_ADDR_AI (0x80000000) + +#define reg_RX_DIAGNOSTIC_DATA(base) __REG32(base, 0x00000374) + +#define reg_RX_QUEUE_0_CONFIG(base) __REG32(base, 0x00000380) +#define RX_QUEUE_0_CONFIG_OCN_PORT (0x0000003f) +#define RX_QUEUE_0_CONFIG_BSWP (0x00000400) +#define RX_QUEUE_0_CONFIG_WSWP (0x00000800) +#define RX_QUEUE_0_CONFIG_AM (0x00004000) +#define RX_QUEUE_0_CONFIG_EEI (0x00010000) +#define RX_QUEUE_0_CONFIG_ELI (0x00020000) +#define RX_QUEUE_0_CONFIG_ENI (0x00040000) +#define RX_QUEUE_0_CONFIG_ESI (0x00080000) +#define RX_QUEUE_0_CONFIG_EDI (0x00100000) + +#define reg_RX_QUEUE_0_BUF_CONFIG(base) __REG32(base, 0x00000384) +#define RX_QUEUE_0_BUF_CONFIG_OCN_PORT (0x0000003f) +#define RX_QUEUE_0_BUF_CONFIG_BURST (0x00000300) +#define RX_QUEUE_0_BUF_CONFIG_BSWP (0x00000400) +#define RX_QUEUE_0_BUF_CONFIG_WSWP (0x00000800) + +#define reg_RX_QUEUE_0_PTR_LOW(base) __REG32(base, 0x00000388) + +#define reg_RX_QUEUE_0_PTR_HIGH(base) __REG32(base, 0x0000038c) +#define RX_QUEUE_0_PTR_HIGH_VALID (0x80000000) + +/* + * PHY register definitions + */ +/* the first 15 PHY registers are standard. */ +#define PHY_CTRL_REG 0 /* Control Register */ +#define PHY_STATUS_REG 1 /* Status Regiser */ +#define PHY_ID1_REG 2 /* Phy Id Reg (word 1) */ +#define PHY_ID2_REG 3 /* Phy Id Reg (word 2) */ +#define PHY_AN_ADV_REG 4 /* Autoneg Advertisement */ +#define PHY_LP_ABILITY_REG 5 /* Link Partner Ability (Base Page) */ +#define PHY_AUTONEG_EXP_REG 6 /* Autoneg Expansion Reg */ +#define PHY_NEXT_PAGE_TX_REG 7 /* Next Page TX */ +#define PHY_LP_NEXT_PAGE_REG 8 /* Link Partner Next Page */ +#define PHY_1000T_CTRL_REG 9 /* 1000Base-T Control Reg */ +#define PHY_1000T_STATUS_REG 10 /* 1000Base-T Status Reg */ +#define PHY_EXT_STATUS_REG 11 /* Extended Status Reg */ + +/* + * PHY Register bit masks. + */ +#define PHY_CTRL_RESET (1 << 15) +#define PHY_CTRL_LOOPBACK (1 << 14) +#define PHY_CTRL_SPEED0 (1 << 13) +#define PHY_CTRL_AN_EN (1 << 12) +#define PHY_CTRL_PWR_DN (1 << 11) +#define PHY_CTRL_ISOLATE (1 << 10) +#define PHY_CTRL_RESTART_AN (1 << 9) +#define PHY_CTRL_FULL_DUPLEX (1 << 8) +#define PHY_CTRL_CT_EN (1 << 7) +#define PHY_CTRL_SPEED1 (1 << 6) + +#define PHY_STAT_100BASE_T4 (1 << 15) +#define PHY_STAT_100BASE_X_FD (1 << 14) +#define PHY_STAT_100BASE_X_HD (1 << 13) +#define PHY_STAT_10BASE_T_FD (1 << 12) +#define PHY_STAT_10BASE_T_HD (1 << 11) +#define PHY_STAT_100BASE_T2_FD (1 << 10) +#define PHY_STAT_100BASE_T2_HD (1 << 9) +#define PHY_STAT_EXT_STAT (1 << 8) +#define PHY_STAT_RESERVED (1 << 7) +#define PHY_STAT_MFPS (1 << 6) /* Management Frames Preamble Suppression */ +#define PHY_STAT_AN_COMPLETE (1 << 5) +#define PHY_STAT_REM_FAULT (1 << 4) +#define PHY_STAT_AN_CAP (1 << 3) +#define PHY_STAT_LINK_UP (1 << 2) +#define PHY_STAT_JABBER (1 << 1) +#define PHY_STAT_EXT_CAP (1 << 0) + +#define TBI_CONTROL_2 0x11 +#define TBI_CONTROL_2_ENABLE_COMMA_DETECT 0x0001 +#define TBI_CONTROL_2_ENABLE_WRAP 0x0002 +#define TBI_CONTROL_2_G_MII_MODE 0x0010 +#define TBI_CONTROL_2_RECEIVE_CLOCK_SELECT 0x0020 +#define TBI_CONTROL_2_AUTO_NEGOTIATION_SENSE 0x0100 +#define TBI_CONTROL_2_DISABLE_TRANSMIT_RUNNING_DISPARITY 0x1000 +#define TBI_CONTROL_2_DISABLE_RECEIVE_RUNNING_DISPARITY 0x2000 +#define TBI_CONTROL_2_SHORTCUT_LINK_TIMER 0x4000 +#define TBI_CONTROL_2_SOFT_RESET 0x8000 + +/* marvel specific */ +#define MV1111_EXT_CTRL1_REG 16 /* PHY Specific Control Reg */ +#define MV1111_SPEC_STAT_REG 17 /* PHY Specific Status Reg */ +#define MV1111_EXT_CTRL2_REG 20 /* Extended PHY Specific Control Reg */ + +/* + * MARVELL 88E1111 PHY register bit masks + */ +/* PHY Specific Status Register (MV1111_EXT_CTRL1_REG) */ + +#define SPEC_STAT_SPEED_MASK (3 << 14) +#define SPEC_STAT_FULL_DUP (1 << 13) +#define SPEC_STAT_PAGE_RCVD (1 << 12) +#define SPEC_STAT_RESOLVED (1 << 11) /* Speed and Duplex Resolved */ +#define SPEC_STAT_LINK_UP (1 << 10) +#define SPEC_STAT_CABLE_LEN_MASK (7 << 7)/* Cable Length (100/1000 modes only) */ +#define SPEC_STAT_MDIX (1 << 6) +#define SPEC_STAT_POLARITY (1 << 1) +#define SPEC_STAT_JABBER (1 << 0) + +#define SPEED_1000 (2 << 14) +#define SPEED_100 (1 << 14) +#define SPEED_10 (0 << 14) + +#define TBI_ADDR 0x1E /* Ten Bit Interface address */ + +/* negotiated link parameters */ +#define LINK_SPEED_UNKNOWN 0 +#define LINK_SPEED_10 1 +#define LINK_SPEED_100 2 +#define LINK_SPEED_1000 3 + +#define LINK_DUPLEX_UNKNOWN 0 +#define LINK_DUPLEX_HALF 1 +#define LINK_DUPLEX_FULL 2 + +static unsigned int phy_address[] = { 8, 9 }; + +#define vuint32 volatile u32 + +/* TX/RX buffer descriptors. MUST be cache line aligned in memory. (32 byte) + * This structure is accessed by the ethernet DMA engine which means it + * MUST be in LITTLE ENDIAN format */ +struct dma_descriptor { + vuint32 start_addr0; /* buffer address, least significant bytes. */ + vuint32 start_addr1; /* buffer address, most significant bytes. */ + vuint32 next_descr_addr0;/* next descriptor address, least significant bytes. Must be 64-bit aligned. */ + vuint32 next_descr_addr1;/* next descriptor address, most significant bytes. */ + vuint32 vlan_byte_count;/* VLAN tag(top 2 bytes) and byte countt (bottom 2 bytes). */ + vuint32 config_status; /* Configuration/Status. */ + vuint32 reserved1; /* reserved to make the descriptor cache line aligned. */ + vuint32 reserved2; /* reserved to make the descriptor cache line aligned. */ +}; + +/* last next descriptor address flag */ +#define DMA_DESCR_LAST (1 << 31) + +/* TX DMA descriptor config status bits */ +#define DMA_DESCR_TX_EOF (1 << 0) /* end of frame */ +#define DMA_DESCR_TX_SOF (1 << 1) /* start of frame */ +#define DMA_DESCR_TX_PFVLAN (1 << 2) +#define DMA_DESCR_TX_HUGE (1 << 3) +#define DMA_DESCR_TX_PAD (1 << 4) +#define DMA_DESCR_TX_CRC (1 << 5) +#define DMA_DESCR_TX_DESCR_INT (1 << 14) +#define DMA_DESCR_TX_RETRY_COUNT 0x000F0000 +#define DMA_DESCR_TX_ONE_COLLISION (1 << 20) +#define DMA_DESCR_TX_LATE_COLLISION (1 << 24) +#define DMA_DESCR_TX_UNDERRUN (1 << 25) +#define DMA_DESCR_TX_RETRY_LIMIT (1 << 26) +#define DMA_DESCR_TX_OK (1 << 30) +#define DMA_DESCR_TX_OWNER (1 << 31) + +/* RX DMA descriptor status bits */ +#define DMA_DESCR_RX_EOF (1 << 0) +#define DMA_DESCR_RX_SOF (1 << 1) +#define DMA_DESCR_RX_VTF (1 << 2) +#define DMA_DESCR_RX_FRAME_IS_TYPE (1 << 3) +#define DMA_DESCR_RX_SHORT_FRAME (1 << 4) +#define DMA_DESCR_RX_HASH_MATCH (1 << 7) +#define DMA_DESCR_RX_BAD_FRAME (1 << 8) +#define DMA_DESCR_RX_OVERRUN (1 << 9) +#define DMA_DESCR_RX_MAX_FRAME_LEN (1 << 11) +#define DMA_DESCR_RX_CRC_ERROR (1 << 12) +#define DMA_DESCR_RX_DESCR_INT (1 << 13) +#define DMA_DESCR_RX_OWNER (1 << 15) + +#define RX_BUFFER_SIZE PKTSIZE +#define NUM_RX_DESC PKTBUFSRX + +static struct dma_descriptor tx_descriptor __attribute__ ((aligned(32))); + +static struct dma_descriptor rx_descr_array[NUM_RX_DESC] + __attribute__ ((aligned(32))); + +static struct dma_descriptor *rx_descr_current; + +static int tsi108_eth_probe (struct eth_device *dev, bd_t * bis); +static int tsi108_eth_send(struct eth_device *dev, void *packet, int length); +static int tsi108_eth_recv (struct eth_device *dev); +static void tsi108_eth_halt (struct eth_device *dev); +static unsigned int read_phy (unsigned int base, + unsigned int phy_addr, unsigned int phy_reg); +static void write_phy (unsigned int base, + unsigned int phy_addr, + unsigned int phy_reg, unsigned int phy_data); + +#if TSI108_ETH_DEBUG > 100 +/* + * print phy debug infomation + */ +static void dump_phy_regs (unsigned int phy_addr) +{ + int i; + + printf ("PHY %d registers\n", phy_addr); + for (i = 0; i <= 30; i++) { + printf ("%2d 0x%04x\n", i, read_phy (ETH_BASE, phy_addr, i)); + } + printf ("\n"); + +} +#else +#define dump_phy_regs(base) do{}while(0) +#endif + +#if TSI108_ETH_DEBUG > 100 +/* + * print debug infomation + */ +static void tx_diag_regs (unsigned int base) +{ + int i; + unsigned long dummy; + + printf ("TX diagnostics registers\n"); + reg_TX_DIAGNOSTIC_ADDR(base) = 0x00 | TX_DIAGNOSTIC_ADDR_AI; + udelay (1000); + dummy = reg_TX_DIAGNOSTIC_DATA(base); + for (i = 0x00; i <= 0x05; i++) { + udelay (1000); + printf ("0x%02x 0x%08x\n", i, reg_TX_DIAGNOSTIC_DATA(base)); + } + reg_TX_DIAGNOSTIC_ADDR(base) = 0x40 | TX_DIAGNOSTIC_ADDR_AI; + udelay (1000); + dummy = reg_TX_DIAGNOSTIC_DATA(base); + for (i = 0x40; i <= 0x47; i++) { + udelay (1000); + printf ("0x%02x 0x%08x\n", i, reg_TX_DIAGNOSTIC_DATA(base)); + } + printf ("\n"); + +} +#else +#define tx_diag_regs(base) do{}while(0) +#endif + +#if TSI108_ETH_DEBUG > 100 +/* + * print debug infomation + */ +static void rx_diag_regs (unsigned int base) +{ + int i; + unsigned long dummy; + + printf ("RX diagnostics registers\n"); + reg_RX_DIAGNOSTIC_ADDR(base) = 0x00 | RX_DIAGNOSTIC_ADDR_AI; + udelay (1000); + dummy = reg_RX_DIAGNOSTIC_DATA(base); + for (i = 0x00; i <= 0x05; i++) { + udelay (1000); + printf ("0x%02x 0x%08x\n", i, reg_RX_DIAGNOSTIC_DATA(base)); + } + reg_RX_DIAGNOSTIC_ADDR(base) = 0x40 | RX_DIAGNOSTIC_ADDR_AI; + udelay (1000); + dummy = reg_RX_DIAGNOSTIC_DATA(base); + for (i = 0x08; i <= 0x0a; i++) { + udelay (1000); + printf ("0x%02x 0x%08x\n", i, reg_RX_DIAGNOSTIC_DATA(base)); + } + printf ("\n"); + +} +#else +#define rx_diag_regs(base) do{}while(0) +#endif + +#if TSI108_ETH_DEBUG > 100 +/* + * print debug infomation + */ +static void debug_mii_regs (unsigned int base) +{ + printf ("MII_MGMT_CONFIG 0x%08x\n", reg_MII_MGMT_CONFIG(base)); + printf ("MII_MGMT_COMMAND 0x%08x\n", reg_MII_MGMT_COMMAND(base)); + printf ("MII_MGMT_ADDRESS 0x%08x\n", reg_MII_MGMT_ADDRESS(base)); + printf ("MII_MGMT_CONTROL 0x%08x\n", reg_MII_MGMT_CONTROL(base)); + printf ("MII_MGMT_STATUS 0x%08x\n", reg_MII_MGMT_STATUS(base)); + printf ("MII_MGMT_INDICATORS 0x%08x\n", reg_MII_MGMT_INDICATORS(base)); + printf ("\n"); + +} +#else +#define debug_mii_regs(base) do{}while(0) +#endif + +/* + * Wait until the phy bus is non-busy + */ +static void phy_wait (unsigned int base, unsigned int condition) +{ + int timeout; + + timeout = 0; + while (reg_MII_MGMT_INDICATORS(base) & condition) { + udelay (10); + if (++timeout > 10000) { + printf ("ERROR: timeout waiting for phy bus (%d)\n", + condition); + break; + } + } +} + +/* + * read phy register + */ +static unsigned int read_phy (unsigned int base, + unsigned int phy_addr, unsigned int phy_reg) +{ + unsigned int value; + + phy_wait (base, MII_MGMT_INDICATORS_BUSY); + + reg_MII_MGMT_ADDRESS(base) = (phy_addr << 8) | phy_reg; + + /* Ensure that the Read Cycle bit is cleared prior to next read cycle */ + reg_MII_MGMT_COMMAND(base) = 0; + + /* start the read */ + reg_MII_MGMT_COMMAND(base) = MII_MGMT_COMMAND_READ_CYCLE; + + /* wait for the read to complete */ + phy_wait (base, + MII_MGMT_INDICATORS_NOT_VALID | MII_MGMT_INDICATORS_BUSY); + + value = reg_MII_MGMT_STATUS(base); + + reg_MII_MGMT_COMMAND(base) = 0; + + return value; +} + +/* + * write phy register + */ +static void write_phy (unsigned int base, + unsigned int phy_addr, + unsigned int phy_reg, unsigned int phy_data) +{ + phy_wait (base, MII_MGMT_INDICATORS_BUSY); + + reg_MII_MGMT_ADDRESS(base) = (phy_addr << 8) | phy_reg; + + /* Ensure that the Read Cycle bit is cleared prior to next cycle */ + reg_MII_MGMT_COMMAND(base) = 0; + + /* start the write */ + reg_MII_MGMT_CONTROL(base) = phy_data; +} + +/* + * configure the marvell 88e1111 phy + */ +static int marvell_88e_phy_config (struct eth_device *dev, int *speed, + int *duplex) +{ + unsigned long base; + unsigned long phy_addr; + unsigned int phy_status; + unsigned int phy_spec_status; + int timeout; + int phy_speed; + int phy_duplex; + unsigned int value; + + phy_speed = LINK_SPEED_UNKNOWN; + phy_duplex = LINK_DUPLEX_UNKNOWN; + + base = dev->iobase; + phy_addr = (unsigned long)dev->priv; + + /* Take the PHY out of reset. */ + write_phy (ETH_BASE, phy_addr, PHY_CTRL_REG, PHY_CTRL_RESET); + + /* Wait for the reset process to complete. */ + udelay (10); + timeout = 0; + while ((phy_status = + read_phy (ETH_BASE, phy_addr, PHY_CTRL_REG)) & PHY_CTRL_RESET) { + udelay (10); + if (++timeout > 10000) { + printf ("ERROR: timeout waiting for phy reset\n"); + break; + } + } + + /* TBI Configuration. */ + write_phy (base, TBI_ADDR, TBI_CONTROL_2, TBI_CONTROL_2_G_MII_MODE | + TBI_CONTROL_2_RECEIVE_CLOCK_SELECT); + /* Wait for the link to be established. */ + timeout = 0; + do { + udelay (20000); + phy_status = read_phy (ETH_BASE, phy_addr, PHY_STATUS_REG); + if (++timeout > 100) { + debug_lev(1, "ERROR: unable to establish link!!!\n"); + break; + } + } while ((phy_status & PHY_STAT_LINK_UP) == 0); + + if ((phy_status & PHY_STAT_LINK_UP) == 0) + return 0; + + value = 0; + phy_spec_status = read_phy (ETH_BASE, phy_addr, MV1111_SPEC_STAT_REG); + if (phy_spec_status & SPEC_STAT_RESOLVED) { + switch (phy_spec_status & SPEC_STAT_SPEED_MASK) { + case SPEED_1000: + phy_speed = LINK_SPEED_1000; + value |= PHY_CTRL_SPEED1; + break; + case SPEED_100: + phy_speed = LINK_SPEED_100; + value |= PHY_CTRL_SPEED0; + break; + case SPEED_10: + phy_speed = LINK_SPEED_10; + break; + } + if (phy_spec_status & SPEC_STAT_FULL_DUP) { + phy_duplex = LINK_DUPLEX_FULL; + value |= PHY_CTRL_FULL_DUPLEX; + } else + phy_duplex = LINK_DUPLEX_HALF; + } + /* set TBI speed */ + write_phy (base, TBI_ADDR, PHY_CTRL_REG, value); + write_phy (base, TBI_ADDR, PHY_AN_ADV_REG, 0x0060); + +#if TSI108_ETH_DEBUG > 0 + printf ("%s link is up", dev->name); + phy_spec_status = read_phy (ETH_BASE, phy_addr, MV1111_SPEC_STAT_REG); + if (phy_spec_status & SPEC_STAT_RESOLVED) { + switch (phy_speed) { + case LINK_SPEED_1000: + printf (", 1000 Mbps"); + break; + case LINK_SPEED_100: + printf (", 100 Mbps"); + break; + case LINK_SPEED_10: + printf (", 10 Mbps"); + break; + } + if (phy_duplex == LINK_DUPLEX_FULL) + printf (", Full duplex"); + else + printf (", Half duplex"); + } + printf ("\n"); +#endif + + dump_phy_regs (TBI_ADDR); + if (speed) + *speed = phy_speed; + if (duplex) + *duplex = phy_duplex; + + return 1; +} + +/* + * External interface + * + * register the tsi108 ethernet controllers with the multi-ethernet system + */ +int tsi108_eth_initialize (bd_t * bis) +{ + struct eth_device *dev; + int index; + + for (index = 0; index < CONFIG_TSI108_ETH_NUM_PORTS; index++) { + dev = (struct eth_device *)malloc(sizeof(struct eth_device)); + if (!dev) { + printf("tsi108: Can not allocate memory\n"); + break; + } + memset(dev, 0, sizeof(*dev)); + sprintf (dev->name, "TSI108_eth%d", index); + + dev->iobase = ETH_BASE + (index * ETH_PORT_OFFSET); + dev->priv = (void *)(phy_address[index]); + dev->init = tsi108_eth_probe; + dev->halt = tsi108_eth_halt; + dev->send = tsi108_eth_send; + dev->recv = tsi108_eth_recv; + + eth_register(dev); + } + return index; +} + +/* + * probe for and initialize a single ethernet interface + */ +static int tsi108_eth_probe (struct eth_device *dev, bd_t * bis) +{ + unsigned long base; + unsigned long value; + int index; + struct dma_descriptor *tx_descr; + struct dma_descriptor *rx_descr; + int speed; + int duplex; + + base = dev->iobase; + + reg_PORT_CONTROL(base) = PORT_CONTROL_STE | PORT_CONTROL_BPT; + + /* Bring DMA/FIFO out of reset. */ + reg_TX_CONFIG(base) = 0x00000000; + reg_RX_CONFIG(base) = 0x00000000; + + reg_TX_THRESHOLDS(base) = (192 << 16) | 192; + reg_RX_THRESHOLDS(base) = (192 << 16) | 112; + + /* Bring MAC out of reset. */ + reg_MAC_CONFIG_1(base) = 0x00000000; + + /* DMA MAC configuration. */ + reg_MAC_CONFIG_1(base) = + MAC_CONFIG_1_RX_ENABLE | MAC_CONFIG_1_TX_ENABLE; + + reg_MII_MGMT_CONFIG(base) = MII_MGMT_CONFIG_NO_PREAMBLE; + reg_MAXIMUM_FRAME_LENGTH(base) = RX_BUFFER_SIZE; + + /* Note: Early tsi108 manual did not have correct byte order + * for the station address.*/ + reg_STATION_ADDRESS_1(base) = (dev->enetaddr[5] << 24) | + (dev->enetaddr[4] << 16) | + (dev->enetaddr[3] << 8) | (dev->enetaddr[2] << 0); + + reg_STATION_ADDRESS_2(base) = (dev->enetaddr[1] << 24) | + (dev->enetaddr[0] << 16); + + if (marvell_88e_phy_config(dev, &speed, &duplex) == 0) + return -1; + + value = + MAC_CONFIG_2_PREAMBLE_LENGTH(7) | MAC_CONFIG_2_PAD_CRC | + MAC_CONFIG_2_CRC_ENABLE; + if (speed == LINK_SPEED_1000) + value |= MAC_CONFIG_2_INTERFACE_MODE(INTERFACE_MODE_BYTE); + else { + value |= MAC_CONFIG_2_INTERFACE_MODE(INTERFACE_MODE_NIBBLE); + reg_PORT_CONTROL(base) |= PORT_CONTROL_SPD; + } + if (duplex == LINK_DUPLEX_FULL) { + value |= MAC_CONFIG_2_FULL_DUPLEX; + reg_PORT_CONTROL(base) &= ~PORT_CONTROL_BPT; + } else + reg_PORT_CONTROL(base) |= PORT_CONTROL_BPT; + reg_MAC_CONFIG_2(base) = value; + + reg_RX_CONFIG(base) = RX_CONFIG_SE; + reg_RX_QUEUE_0_CONFIG(base) = OCN_PORT_MEMORY; + reg_RX_QUEUE_0_BUF_CONFIG(base) = OCN_PORT_MEMORY; + + /* initialize the RX DMA descriptors */ + rx_descr = &rx_descr_array[0]; + rx_descr_current = rx_descr; + for (index = 0; index < NUM_RX_DESC; index++) { + /* make sure the receive buffers are not in cache */ + invalidate_dcache_range((unsigned long)net_rx_packets[index], + (unsigned long)net_rx_packets[index] + + RX_BUFFER_SIZE); + rx_descr->start_addr0 = + cpu_to_le32((vuint32) net_rx_packets[index]); + rx_descr->start_addr1 = 0; + rx_descr->next_descr_addr0 = + cpu_to_le32((vuint32) (rx_descr + 1)); + rx_descr->next_descr_addr1 = 0; + rx_descr->vlan_byte_count = 0; + rx_descr->config_status = cpu_to_le32((RX_BUFFER_SIZE << 16) | + DMA_DESCR_RX_OWNER); + rx_descr++; + } + rx_descr--; + rx_descr->next_descr_addr0 = 0; + rx_descr->next_descr_addr1 = cpu_to_le32(DMA_DESCR_LAST); + /* Push the descriptors to RAM so the ethernet DMA can see them */ + invalidate_dcache_range((unsigned long)rx_descr_array, + (unsigned long)rx_descr_array + + sizeof(rx_descr_array)); + + /* enable RX queue */ + reg_RX_CONTROL(base) = TX_CONTROL_GO | 0x01; + reg_RX_QUEUE_0_PTR_LOW(base) = (u32) rx_descr_current; + /* enable receive DMA */ + reg_RX_QUEUE_0_PTR_HIGH(base) = RX_QUEUE_0_PTR_HIGH_VALID; + + reg_TX_QUEUE_0_CONFIG(base) = OCN_PORT_MEMORY; + reg_TX_QUEUE_0_BUF_CONFIG(base) = OCN_PORT_MEMORY; + + /* initialize the TX DMA descriptor */ + tx_descr = &tx_descriptor; + + tx_descr->start_addr0 = 0; + tx_descr->start_addr1 = 0; + tx_descr->next_descr_addr0 = 0; + tx_descr->next_descr_addr1 = cpu_to_le32(DMA_DESCR_LAST); + tx_descr->vlan_byte_count = 0; + tx_descr->config_status = cpu_to_le32(DMA_DESCR_TX_OK | + DMA_DESCR_TX_SOF | + DMA_DESCR_TX_EOF); + /* enable TX queue */ + reg_TX_CONTROL(base) = TX_CONTROL_GO | 0x01; + + return 0; +} + +/* + * send a packet + */ +static int tsi108_eth_send(struct eth_device *dev, void *packet, int length) +{ + unsigned long base; + int timeout; + struct dma_descriptor *tx_descr; + unsigned long status; + + base = dev->iobase; + tx_descr = &tx_descriptor; + + /* Wait until the last packet has been transmitted. */ + timeout = 0; + do { + /* make sure we see the changes made by the DMA engine */ + invalidate_dcache_range((unsigned long)tx_descr, + (unsigned long)tx_descr + + sizeof(struct dma_descriptor)); + + if (timeout != 0) + udelay (15); + if (++timeout > 10000) { + tx_diag_regs(base); + debug_lev(1, + "ERROR: timeout waiting for last transmit packet to be sent\n"); + return 0; + } + } while (tx_descr->config_status & cpu_to_le32(DMA_DESCR_TX_OWNER)); + + status = le32_to_cpu(tx_descr->config_status); + if ((status & DMA_DESCR_TX_OK) == 0) { +#ifdef TX_PRINT_ERRORS + printf ("TX packet error: 0x%08lx\n %s%s%s%s\n", status, + status & DMA_DESCR_TX_OK ? "tx error, " : "", + status & DMA_DESCR_TX_RETRY_LIMIT ? + "retry limit reached, " : "", + status & DMA_DESCR_TX_UNDERRUN ? "underrun, " : "", + status & DMA_DESCR_TX_LATE_COLLISION ? "late collision, " + : ""); +#endif + } + + debug_lev (9, "sending packet %d\n", length); + tx_descr->start_addr0 = cpu_to_le32((vuint32) packet); + tx_descr->start_addr1 = 0; + tx_descr->next_descr_addr0 = 0; + tx_descr->next_descr_addr1 = cpu_to_le32(DMA_DESCR_LAST); + tx_descr->vlan_byte_count = cpu_to_le32(length); + tx_descr->config_status = cpu_to_le32(DMA_DESCR_TX_OWNER | + DMA_DESCR_TX_CRC | + DMA_DESCR_TX_PAD | + DMA_DESCR_TX_SOF | + DMA_DESCR_TX_EOF); + + invalidate_dcache_range((unsigned long)tx_descr, + (unsigned long)tx_descr + + sizeof(struct dma_descriptor)); + + invalidate_dcache_range((unsigned long)packet, + (unsigned long)packet + length); + + reg_TX_QUEUE_0_PTR_LOW(base) = (u32) tx_descr; + reg_TX_QUEUE_0_PTR_HIGH(base) = TX_QUEUE_0_PTR_HIGH_VALID; + + return length; +} + +/* + * Check for received packets and send them up the protocal stack + */ +static int tsi108_eth_recv (struct eth_device *dev) +{ + struct dma_descriptor *rx_descr; + unsigned long base; + int length = 0; + unsigned long status; + uchar *buffer; + + base = dev->iobase; + + /* make sure we see the changes made by the DMA engine */ + invalidate_dcache_range ((unsigned long)rx_descr_array, + (unsigned long)rx_descr_array + + sizeof(rx_descr_array)); + + /* process all of the received packets */ + rx_descr = rx_descr_current; + while ((rx_descr->config_status & cpu_to_le32(DMA_DESCR_RX_OWNER)) == 0) { + /* check for error */ + status = le32_to_cpu(rx_descr->config_status); + if (status & DMA_DESCR_RX_BAD_FRAME) { +#ifdef RX_PRINT_ERRORS + printf ("RX packet error: 0x%08lx\n %s%s%s%s%s%s\n", + status, + status & DMA_DESCR_RX_FRAME_IS_TYPE ? "too big, " + : "", + status & DMA_DESCR_RX_SHORT_FRAME ? "too short, " + : "", + status & DMA_DESCR_RX_BAD_FRAME ? "bad frame, " : + "", + status & DMA_DESCR_RX_OVERRUN ? "overrun, " : "", + status & DMA_DESCR_RX_MAX_FRAME_LEN ? + "max length, " : "", + status & DMA_DESCR_RX_CRC_ERROR ? "CRC error, " : + ""); +#endif + } else { + length = + le32_to_cpu(rx_descr->vlan_byte_count) & 0xFFFF; + + /*** process packet ***/ + buffer = (uchar *)(le32_to_cpu(rx_descr->start_addr0)); + net_process_received_packet(buffer, length); + + invalidate_dcache_range ((unsigned long)buffer, + (unsigned long)buffer + + RX_BUFFER_SIZE); + } + /* Give this buffer back to the DMA engine */ + rx_descr->vlan_byte_count = 0; + rx_descr->config_status = cpu_to_le32 ((RX_BUFFER_SIZE << 16) | + DMA_DESCR_RX_OWNER); + /* move descriptor pointer forward */ + rx_descr = + (struct dma_descriptor + *)(le32_to_cpu (rx_descr->next_descr_addr0)); + if (rx_descr == 0) + rx_descr = &rx_descr_array[0]; + } + /* remember where we are for next time */ + rx_descr_current = rx_descr; + + /* If the DMA engine has reached the end of the queue + * start over at the begining */ + if (reg_RX_EXTENDED_STATUS(base) & RX_EXTENDED_STATUS_EOQ_0) { + + reg_RX_EXTENDED_STATUS(base) = RX_EXTENDED_STATUS_EOQ_0; + reg_RX_QUEUE_0_PTR_LOW(base) = (u32) & rx_descr_array[0]; + reg_RX_QUEUE_0_PTR_HIGH(base) = RX_QUEUE_0_PTR_HIGH_VALID; + } + + return length; +} + +/* + * disable an ethernet interface + */ +static void tsi108_eth_halt (struct eth_device *dev) +{ + unsigned long base; + + base = dev->iobase; + + /* Put DMA/FIFO into reset state. */ + reg_TX_CONFIG(base) = TX_CONFIG_RST; + reg_RX_CONFIG(base) = RX_CONFIG_RST; + + /* Put MAC into reset state. */ + reg_MAC_CONFIG_1(base) = MAC_CONFIG_1_SOFT_RESET; +} diff --git a/sources/uboot-be550/drivers/net/uli526x.c b/sources/uboot-be550/drivers/net/uli526x.c new file mode 100644 index 00000000..47cdb858 --- /dev/null +++ b/sources/uboot-be550/drivers/net/uli526x.c @@ -0,0 +1,997 @@ +/* + * Copyright 2007, 2010 Freescale Semiconductor, Inc. + * + * Author: Roy Zang , Sep, 2007 + * + * Description: + * ULI 526x Ethernet port driver. + * Based on the Linux driver: drivers/net/tulip/uli526x.c + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +/* some kernel function compatible define */ + +#undef DEBUG + +/* Board/System/Debug information/definition */ +#define ULI_VENDOR_ID 0x10B9 +#define ULI5261_DEVICE_ID 0x5261 +#define ULI5263_DEVICE_ID 0x5263 +/* ULi M5261 ID*/ +#define PCI_ULI5261_ID (ULI5261_DEVICE_ID << 16 | ULI_VENDOR_ID) +/* ULi M5263 ID*/ +#define PCI_ULI5263_ID (ULI5263_DEVICE_ID << 16 | ULI_VENDOR_ID) + +#define ULI526X_IO_SIZE 0x100 +#define TX_DESC_CNT 0x10 /* Allocated Tx descriptors */ +#define RX_DESC_CNT PKTBUFSRX /* Allocated Rx descriptors */ +#define TX_FREE_DESC_CNT (TX_DESC_CNT - 2) /* Max TX packet count */ +#define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3) /* TX wakeup count */ +#define DESC_ALL_CNT (TX_DESC_CNT + RX_DESC_CNT) +#define TX_BUF_ALLOC 0x300 +#define RX_ALLOC_SIZE PKTSIZE +#define ULI526X_RESET 1 +#define CR0_DEFAULT 0 +#define CR6_DEFAULT 0x22200000 +#define CR7_DEFAULT 0x180c1 +#define CR15_DEFAULT 0x06 /* TxJabber RxWatchdog */ +#define TDES0_ERR_MASK 0x4302 /* TXJT, LC, EC, FUE */ +#define MAX_PACKET_SIZE 1514 +#define ULI5261_MAX_MULTICAST 14 +#define RX_COPY_SIZE 100 +#define MAX_CHECK_PACKET 0x8000 + +#define ULI526X_10MHF 0 +#define ULI526X_100MHF 1 +#define ULI526X_10MFD 4 +#define ULI526X_100MFD 5 +#define ULI526X_AUTO 8 + +#define ULI526X_TXTH_72 0x400000 /* TX TH 72 byte */ +#define ULI526X_TXTH_96 0x404000 /* TX TH 96 byte */ +#define ULI526X_TXTH_128 0x0000 /* TX TH 128 byte */ +#define ULI526X_TXTH_256 0x4000 /* TX TH 256 byte */ +#define ULI526X_TXTH_512 0x8000 /* TX TH 512 byte */ +#define ULI526X_TXTH_1K 0xC000 /* TX TH 1K byte */ + +/* CR9 definition: SROM/MII */ +#define CR9_SROM_READ 0x4800 +#define CR9_SRCS 0x1 +#define CR9_SRCLK 0x2 +#define CR9_CRDOUT 0x8 +#define SROM_DATA_0 0x0 +#define SROM_DATA_1 0x4 +#define PHY_DATA_1 0x20000 +#define PHY_DATA_0 0x00000 +#define MDCLKH 0x10000 + +#define PHY_POWER_DOWN 0x800 + +#define SROM_V41_CODE 0x14 + +#define SROM_CLK_WRITE(data, ioaddr) do { \ + outl(data|CR9_SROM_READ|CR9_SRCS, ioaddr); \ + udelay(5); \ + outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK, ioaddr); \ + udelay(5); \ + outl(data|CR9_SROM_READ|CR9_SRCS, ioaddr); \ + udelay(5); \ + } while (0) + +/* Structure/enum declaration */ + +struct tx_desc { + u32 tdes0, tdes1, tdes2, tdes3; /* Data for the card */ + char *tx_buf_ptr; /* Data for us */ + struct tx_desc *next_tx_desc; +}; + +struct rx_desc { + u32 rdes0, rdes1, rdes2, rdes3; /* Data for the card */ + char *rx_buf_ptr; /* Data for us */ + struct rx_desc *next_rx_desc; +}; + +struct uli526x_board_info { + u32 chip_id; /* Chip vendor/Device ID */ + pci_dev_t pdev; + + long ioaddr; /* I/O base address */ + u32 cr0_data; + u32 cr5_data; + u32 cr6_data; + u32 cr7_data; + u32 cr15_data; + + /* pointer for memory physical address */ + dma_addr_t buf_pool_dma_ptr; /* Tx buffer pool memory */ + dma_addr_t buf_pool_dma_start; /* Tx buffer pool align dword */ + dma_addr_t desc_pool_dma_ptr; /* descriptor pool memory */ + dma_addr_t first_tx_desc_dma; + dma_addr_t first_rx_desc_dma; + + /* descriptor pointer */ + unsigned char *buf_pool_ptr; /* Tx buffer pool memory */ + unsigned char *buf_pool_start; /* Tx buffer pool align dword */ + unsigned char *desc_pool_ptr; /* descriptor pool memory */ + struct tx_desc *first_tx_desc; + struct tx_desc *tx_insert_ptr; + struct tx_desc *tx_remove_ptr; + struct rx_desc *first_rx_desc; + struct rx_desc *rx_ready_ptr; /* packet come pointer */ + unsigned long tx_packet_cnt; /* transmitted packet count */ + + u16 PHY_reg4; /* Saved Phyxcer register 4 value */ + + u8 media_mode; /* user specify media mode */ + u8 op_mode; /* real work dedia mode */ + u8 phy_addr; + + /* NIC SROM data */ + unsigned char srom[128]; +}; + +enum uli526x_offsets { + DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20, + DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48, + DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 = 0x70, + DCR15 = 0x78 +}; + +enum uli526x_CR6_bits { + CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80, + CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000, + CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000 +}; + +/* Global variable declaration -- */ + +static unsigned char uli526x_media_mode = ULI526X_AUTO; + +static struct tx_desc desc_pool_array[DESC_ALL_CNT + 0x20] + __attribute__ ((aligned(32))); +static char buf_pool[TX_BUF_ALLOC * TX_DESC_CNT + 4]; + +/* For module input parameter */ +static int mode = 8; + +/* function declaration -- */ +static int uli526x_start_xmit(struct eth_device *dev, void *packet, int length); +static const struct ethtool_ops netdev_ethtool_ops; +static u16 read_srom_word(long, int); +static void uli526x_descriptor_init(struct uli526x_board_info *, unsigned long); +static void allocate_rx_buffer(struct uli526x_board_info *); +static void update_cr6(u32, unsigned long); +static u16 uli_phy_read(unsigned long, u8, u8, u32); +static u16 phy_readby_cr10(unsigned long, u8, u8); +static void uli_phy_write(unsigned long, u8, u8, u16, u32); +static void phy_writeby_cr10(unsigned long, u8, u8, u16); +static void phy_write_1bit(unsigned long, u32, u32); +static u16 phy_read_1bit(unsigned long, u32); +static int uli526x_rx_packet(struct eth_device *); +static void uli526x_free_tx_pkt(struct eth_device *, + struct uli526x_board_info *); +static void uli526x_reuse_buf(struct rx_desc *); +static void uli526x_init(struct eth_device *); +static void uli526x_set_phyxcer(struct uli526x_board_info *); + + +static int uli526x_init_one(struct eth_device *, bd_t *); +static void uli526x_disable(struct eth_device *); +static void set_mac_addr(struct eth_device *); + +static struct pci_device_id uli526x_pci_tbl[] = { + { ULI_VENDOR_ID, ULI5261_DEVICE_ID}, /* 5261 device */ + { ULI_VENDOR_ID, ULI5263_DEVICE_ID}, /* 5263 device */ + {} +}; + +/* ULI526X network board routine */ + +/* + * Search ULI526X board, register it + */ + +int uli526x_initialize(bd_t *bis) +{ + pci_dev_t devno; + int card_number = 0; + struct eth_device *dev; + struct uli526x_board_info *db; /* board information structure */ + + u32 iobase; + int idx = 0; + + while (1) { + /* Find PCI device */ + devno = pci_find_devices(uli526x_pci_tbl, idx++); + if (devno < 0) + break; + + pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase); + iobase &= ~0xf; + + dev = (struct eth_device *)malloc(sizeof *dev); + if (!dev) { + printf("uli526x: Can not allocate memory\n"); + break; + } + memset(dev, 0, sizeof(*dev)); + sprintf(dev->name, "uli526x#%d", card_number); + db = (struct uli526x_board_info *) + malloc(sizeof(struct uli526x_board_info)); + + dev->priv = db; + db->pdev = devno; + dev->iobase = iobase; + + dev->init = uli526x_init_one; + dev->halt = uli526x_disable; + dev->send = uli526x_start_xmit; + dev->recv = uli526x_rx_packet; + + /* init db */ + db->ioaddr = dev->iobase; + /* get chip id */ + + pci_read_config_dword(devno, PCI_VENDOR_ID, &db->chip_id); +#ifdef DEBUG + printf("uli526x: uli526x @0x%x\n", iobase); + printf("uli526x: chip_id%x\n", db->chip_id); +#endif + eth_register(dev); + card_number++; + pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x20); + udelay(10 * 1000); + } + return card_number; +} + +static int uli526x_init_one(struct eth_device *dev, bd_t *bis) +{ + + struct uli526x_board_info *db = dev->priv; + int i; + + switch (mode) { + case ULI526X_10MHF: + case ULI526X_100MHF: + case ULI526X_10MFD: + case ULI526X_100MFD: + uli526x_media_mode = mode; + break; + default: + uli526x_media_mode = ULI526X_AUTO; + break; + } + + /* Allocate Tx/Rx descriptor memory */ + db->desc_pool_ptr = (uchar *)&desc_pool_array[0]; + db->desc_pool_dma_ptr = (dma_addr_t)&desc_pool_array[0]; + if (db->desc_pool_ptr == NULL) + return -1; + + db->buf_pool_ptr = (uchar *)&buf_pool[0]; + db->buf_pool_dma_ptr = (dma_addr_t)&buf_pool[0]; + if (db->buf_pool_ptr == NULL) + return -1; + + db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr; + db->first_tx_desc_dma = db->desc_pool_dma_ptr; + + db->buf_pool_start = db->buf_pool_ptr; + db->buf_pool_dma_start = db->buf_pool_dma_ptr; + +#ifdef DEBUG + printf("%s(): db->ioaddr= 0x%x\n", + __FUNCTION__, db->ioaddr); + printf("%s(): media_mode= 0x%x\n", + __FUNCTION__, uli526x_media_mode); + printf("%s(): db->desc_pool_ptr= 0x%x\n", + __FUNCTION__, db->desc_pool_ptr); + printf("%s(): db->desc_pool_dma_ptr= 0x%x\n", + __FUNCTION__, db->desc_pool_dma_ptr); + printf("%s(): db->buf_pool_ptr= 0x%x\n", + __FUNCTION__, db->buf_pool_ptr); + printf("%s(): db->buf_pool_dma_ptr= 0x%x\n", + __FUNCTION__, db->buf_pool_dma_ptr); +#endif + + /* read 64 word srom data */ + for (i = 0; i < 64; i++) + ((u16 *) db->srom)[i] = cpu_to_le16(read_srom_word(db->ioaddr, + i)); + + /* Set Node address */ + if (((db->srom[0] == 0xff) && (db->srom[1] == 0xff)) || + ((db->srom[0] == 0x00) && (db->srom[1] == 0x00))) + /* SROM absent, so write MAC address to ID Table */ + set_mac_addr(dev); + else { /*Exist SROM*/ + for (i = 0; i < 6; i++) + dev->enetaddr[i] = db->srom[20 + i]; + } +#ifdef DEBUG + for (i = 0; i < 6; i++) + printf("%c%02x", i ? ':' : ' ', dev->enetaddr[i]); +#endif + db->PHY_reg4 = 0x1e0; + + /* system variable init */ + db->cr6_data = CR6_DEFAULT ; + db->cr6_data |= ULI526X_TXTH_256; + db->cr0_data = CR0_DEFAULT; + uli526x_init(dev); + return 0; +} + +static void uli526x_disable(struct eth_device *dev) +{ +#ifdef DEBUG + printf("uli526x_disable\n"); +#endif + struct uli526x_board_info *db = dev->priv; + + if (!((inl(db->ioaddr + DCR12)) & 0x8)) { + /* Reset & stop ULI526X board */ + outl(ULI526X_RESET, db->ioaddr + DCR0); + udelay(5); + uli_phy_write(db->ioaddr, db->phy_addr, 0, 0x8000, db->chip_id); + + /* reset the board */ + db->cr6_data &= ~(CR6_RXSC | CR6_TXSC); /* Disable Tx/Rx */ + update_cr6(db->cr6_data, dev->iobase); + outl(0, dev->iobase + DCR7); /* Disable Interrupt */ + outl(inl(dev->iobase + DCR5), dev->iobase + DCR5); + } +} + +/* Initialize ULI526X board + * Reset ULI526X board + * Initialize TX/Rx descriptor chain structure + * Send the set-up frame + * Enable Tx/Rx machine + */ + +static void uli526x_init(struct eth_device *dev) +{ + + struct uli526x_board_info *db = dev->priv; + u8 phy_tmp; + u16 phy_value; + u16 phy_reg_reset; + + /* Reset M526x MAC controller */ + outl(ULI526X_RESET, db->ioaddr + DCR0); /* RESET MAC */ + udelay(100); + outl(db->cr0_data, db->ioaddr + DCR0); + udelay(5); + + /* Phy addr : In some boards,M5261/M5263 phy address != 1 */ + db->phy_addr = 1; + db->tx_packet_cnt = 0; + for (phy_tmp = 0; phy_tmp < 32; phy_tmp++) { + /* peer add */ + phy_value = uli_phy_read(db->ioaddr, phy_tmp, 3, db->chip_id); + if (phy_value != 0xffff && phy_value != 0) { + db->phy_addr = phy_tmp; + break; + } + } + +#ifdef DEBUG + printf("%s(): db->ioaddr= 0x%x\n", __FUNCTION__, db->ioaddr); + printf("%s(): db->phy_addr= 0x%x\n", __FUNCTION__, db->phy_addr); +#endif + if (phy_tmp == 32) + printf("Can not find the phy address!!!"); + + /* Parser SROM and media mode */ + db->media_mode = uli526x_media_mode; + + if (!(inl(db->ioaddr + DCR12) & 0x8)) { + /* Phyxcer capability setting */ + phy_reg_reset = uli_phy_read(db->ioaddr, + db->phy_addr, 0, db->chip_id); + phy_reg_reset = (phy_reg_reset | 0x8000); + uli_phy_write(db->ioaddr, db->phy_addr, 0, + phy_reg_reset, db->chip_id); + udelay(500); + + /* Process Phyxcer Media Mode */ + uli526x_set_phyxcer(db); + } + /* Media Mode Process */ + if (!(db->media_mode & ULI526X_AUTO)) + db->op_mode = db->media_mode; /* Force Mode */ + + /* Initialize Transmit/Receive decriptor and CR3/4 */ + uli526x_descriptor_init(db, db->ioaddr); + + /* Init CR6 to program M526X operation */ + update_cr6(db->cr6_data, db->ioaddr); + + /* Init CR7, interrupt active bit */ + db->cr7_data = CR7_DEFAULT; + outl(db->cr7_data, db->ioaddr + DCR7); + + /* Init CR15, Tx jabber and Rx watchdog timer */ + outl(db->cr15_data, db->ioaddr + DCR15); + + /* Enable ULI526X Tx/Rx function */ + db->cr6_data |= CR6_RXSC | CR6_TXSC; + update_cr6(db->cr6_data, db->ioaddr); + while (!(inl(db->ioaddr + DCR12) & 0x8)) + udelay(10); +} + +/* + * Hardware start transmission. + * Send a packet to media from the upper layer. + */ + +static int uli526x_start_xmit(struct eth_device *dev, void *packet, int length) +{ + struct uli526x_board_info *db = dev->priv; + struct tx_desc *txptr; + unsigned int len = length; + /* Too large packet check */ + if (len > MAX_PACKET_SIZE) { + printf(": big packet = %d\n", len); + return 0; + } + + /* No Tx resource check, it never happen nromally */ + if (db->tx_packet_cnt >= TX_FREE_DESC_CNT) { + printf("No Tx resource %ld\n", db->tx_packet_cnt); + return 0; + } + + /* Disable NIC interrupt */ + outl(0, dev->iobase + DCR7); + + /* transmit this packet */ + txptr = db->tx_insert_ptr; + memcpy((char *)txptr->tx_buf_ptr, (char *)packet, (int)length); + txptr->tdes1 = cpu_to_le32(0xe1000000 | length); + + /* Point to next transmit free descriptor */ + db->tx_insert_ptr = txptr->next_tx_desc; + + /* Transmit Packet Process */ + if ((db->tx_packet_cnt < TX_DESC_CNT)) { + txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */ + db->tx_packet_cnt++; /* Ready to send */ + outl(0x1, dev->iobase + DCR1); /* Issue Tx polling */ + } + + /* Got ULI526X status */ + db->cr5_data = inl(db->ioaddr + DCR5); + outl(db->cr5_data, db->ioaddr + DCR5); + +#ifdef TX_DEBUG + printf("%s(): length = 0x%x\n", __FUNCTION__, length); + printf("%s(): cr5_data=%x\n", __FUNCTION__, db->cr5_data); +#endif + + outl(db->cr7_data, dev->iobase + DCR7); + uli526x_free_tx_pkt(dev, db); + + return length; +} + +/* + * Free TX resource after TX complete + */ + +static void uli526x_free_tx_pkt(struct eth_device *dev, + struct uli526x_board_info *db) +{ + struct tx_desc *txptr; + u32 tdes0; + + txptr = db->tx_remove_ptr; + while (db->tx_packet_cnt) { + tdes0 = le32_to_cpu(txptr->tdes0); + /* printf(DRV_NAME ": tdes0=%x\n", tdes0); */ + if (tdes0 & 0x80000000) + break; + + /* A packet sent completed */ + db->tx_packet_cnt--; + + if (tdes0 != 0x7fffffff) { +#ifdef TX_DEBUG + printf("%s()tdes0=%x\n", __FUNCTION__, tdes0); +#endif + if (tdes0 & TDES0_ERR_MASK) { + if (tdes0 & 0x0002) { /* UnderRun */ + if (!(db->cr6_data & CR6_SFT)) { + db->cr6_data = db->cr6_data | + CR6_SFT; + update_cr6(db->cr6_data, + db->ioaddr); + } + } + } + } + + txptr = txptr->next_tx_desc; + }/* End of while */ + + /* Update TX remove pointer to next */ + db->tx_remove_ptr = txptr; +} + + +/* + * Receive the come packet and pass to upper layer + */ + +static int uli526x_rx_packet(struct eth_device *dev) +{ + struct uli526x_board_info *db = dev->priv; + struct rx_desc *rxptr; + int rxlen = 0; + u32 rdes0; + + rxptr = db->rx_ready_ptr; + + rdes0 = le32_to_cpu(rxptr->rdes0); +#ifdef RX_DEBUG + printf("%s(): rxptr->rdes0=%x\n", __FUNCTION__, rxptr->rdes0); +#endif + if (!(rdes0 & 0x80000000)) { /* packet owner check */ + if ((rdes0 & 0x300) != 0x300) { + /* A packet without First/Last flag */ + /* reuse this buf */ + printf("A packet without First/Last flag"); + uli526x_reuse_buf(rxptr); + } else { + /* A packet with First/Last flag */ + rxlen = ((rdes0 >> 16) & 0x3fff) - 4; +#ifdef RX_DEBUG + printf("%s(): rxlen =%x\n", __FUNCTION__, rxlen); +#endif + /* error summary bit check */ + if (rdes0 & 0x8000) { + /* This is a error packet */ + printf("Error: rdes0: %x\n", rdes0); + } + + if (!(rdes0 & 0x8000) || + ((db->cr6_data & CR6_PM) && (rxlen > 6))) { + +#ifdef RX_DEBUG + printf("%s(): rx_skb_ptr =%x\n", + __FUNCTION__, rxptr->rx_buf_ptr); + printf("%s(): rxlen =%x\n", + __FUNCTION__, rxlen); + + printf("%s(): buf addr =%x\n", + __FUNCTION__, rxptr->rx_buf_ptr); + printf("%s(): rxlen =%x\n", + __FUNCTION__, rxlen); + int i; + for (i = 0; i < 0x20; i++) + printf("%s(): data[%x] =%x\n", + __FUNCTION__, i, rxptr->rx_buf_ptr[i]); +#endif + + net_process_received_packet( + (uchar *)rxptr->rx_buf_ptr, rxlen); + uli526x_reuse_buf(rxptr); + + } else { + /* Reuse SKB buffer when the packet is error */ + printf("Reuse buffer, rdes0"); + uli526x_reuse_buf(rxptr); + } + } + + rxptr = rxptr->next_rx_desc; + } + + db->rx_ready_ptr = rxptr; + return rxlen; +} + +/* + * Reuse the RX buffer + */ + +static void uli526x_reuse_buf(struct rx_desc *rxptr) +{ + + if (!(rxptr->rdes0 & cpu_to_le32(0x80000000))) + rxptr->rdes0 = cpu_to_le32(0x80000000); + else + printf("Buffer reuse method error"); +} +/* + * Initialize transmit/Receive descriptor + * Using Chain structure, and allocate Tx/Rx buffer + */ + +static void uli526x_descriptor_init(struct uli526x_board_info *db, + unsigned long ioaddr) +{ + struct tx_desc *tmp_tx; + struct rx_desc *tmp_rx; + unsigned char *tmp_buf; + dma_addr_t tmp_tx_dma, tmp_rx_dma; + dma_addr_t tmp_buf_dma; + int i; + /* tx descriptor start pointer */ + db->tx_insert_ptr = db->first_tx_desc; + db->tx_remove_ptr = db->first_tx_desc; + + outl(db->first_tx_desc_dma, ioaddr + DCR4); /* TX DESC address */ + + /* rx descriptor start pointer */ + db->first_rx_desc = (void *)db->first_tx_desc + + sizeof(struct tx_desc) * TX_DESC_CNT; + db->first_rx_desc_dma = db->first_tx_desc_dma + + sizeof(struct tx_desc) * TX_DESC_CNT; + db->rx_ready_ptr = db->first_rx_desc; + outl(db->first_rx_desc_dma, ioaddr + DCR3); /* RX DESC address */ +#ifdef DEBUG + printf("%s(): db->first_tx_desc= 0x%x\n", + __FUNCTION__, db->first_tx_desc); + printf("%s(): db->first_rx_desc_dma= 0x%x\n", + __FUNCTION__, db->first_rx_desc_dma); +#endif + /* Init Transmit chain */ + tmp_buf = db->buf_pool_start; + tmp_buf_dma = db->buf_pool_dma_start; + tmp_tx_dma = db->first_tx_desc_dma; + for (tmp_tx = db->first_tx_desc, i = 0; + i < TX_DESC_CNT; i++, tmp_tx++) { + tmp_tx->tx_buf_ptr = (char *)tmp_buf; + tmp_tx->tdes0 = cpu_to_le32(0); + tmp_tx->tdes1 = cpu_to_le32(0x81000000); /* IC, chain */ + tmp_tx->tdes2 = cpu_to_le32(tmp_buf_dma); + tmp_tx_dma += sizeof(struct tx_desc); + tmp_tx->tdes3 = cpu_to_le32(tmp_tx_dma); + tmp_tx->next_tx_desc = tmp_tx + 1; + tmp_buf = tmp_buf + TX_BUF_ALLOC; + tmp_buf_dma = tmp_buf_dma + TX_BUF_ALLOC; + } + (--tmp_tx)->tdes3 = cpu_to_le32(db->first_tx_desc_dma); + tmp_tx->next_tx_desc = db->first_tx_desc; + + /* Init Receive descriptor chain */ + tmp_rx_dma = db->first_rx_desc_dma; + for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT; + i++, tmp_rx++) { + tmp_rx->rdes0 = cpu_to_le32(0); + tmp_rx->rdes1 = cpu_to_le32(0x01000600); + tmp_rx_dma += sizeof(struct rx_desc); + tmp_rx->rdes3 = cpu_to_le32(tmp_rx_dma); + tmp_rx->next_rx_desc = tmp_rx + 1; + } + (--tmp_rx)->rdes3 = cpu_to_le32(db->first_rx_desc_dma); + tmp_rx->next_rx_desc = db->first_rx_desc; + + /* pre-allocate Rx buffer */ + allocate_rx_buffer(db); +} + +/* + * Update CR6 value + * Firstly stop ULI526X, then written value and start + */ + +static void update_cr6(u32 cr6_data, unsigned long ioaddr) +{ + + outl(cr6_data, ioaddr + DCR6); + udelay(5); +} + +/* + * Allocate rx buffer, + */ + +static void allocate_rx_buffer(struct uli526x_board_info *db) +{ + int index; + struct rx_desc *rxptr; + rxptr = db->first_rx_desc; + u32 addr; + + for (index = 0; index < RX_DESC_CNT; index++) { + addr = (u32)net_rx_packets[index]; + addr += (16 - (addr & 15)); + rxptr->rx_buf_ptr = (char *) addr; + rxptr->rdes2 = cpu_to_le32(addr); + rxptr->rdes0 = cpu_to_le32(0x80000000); +#ifdef DEBUG + printf("%s(): Number 0x%x:\n", __FUNCTION__, index); + printf("%s(): addr 0x%x:\n", __FUNCTION__, addr); + printf("%s(): rxptr address = 0x%x\n", __FUNCTION__, rxptr); + printf("%s(): rxptr buf address = 0x%x\n", \ + __FUNCTION__, rxptr->rx_buf_ptr); + printf("%s(): rdes2 = 0x%x\n", __FUNCTION__, rxptr->rdes2); +#endif + rxptr = rxptr->next_rx_desc; + } +} + +/* + * Read one word data from the serial ROM + */ + +static u16 read_srom_word(long ioaddr, int offset) +{ + int i; + u16 srom_data = 0; + long cr9_ioaddr = ioaddr + DCR9; + + outl(CR9_SROM_READ, cr9_ioaddr); + outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr); + + /* Send the Read Command 110b */ + SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr); + SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr); + SROM_CLK_WRITE(SROM_DATA_0, cr9_ioaddr); + + /* Send the offset */ + for (i = 5; i >= 0; i--) { + srom_data = (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0; + SROM_CLK_WRITE(srom_data, cr9_ioaddr); + } + + outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr); + + for (i = 16; i > 0; i--) { + outl(CR9_SROM_READ | CR9_SRCS | CR9_SRCLK, cr9_ioaddr); + udelay(5); + srom_data = (srom_data << 1) | ((inl(cr9_ioaddr) & CR9_CRDOUT) + ? 1 : 0); + outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr); + udelay(5); + } + + outl(CR9_SROM_READ, cr9_ioaddr); + return srom_data; +} + +/* + * Set 10/100 phyxcer capability + * AUTO mode : phyxcer register4 is NIC capability + * Force mode: phyxcer register4 is the force media + */ + +static void uli526x_set_phyxcer(struct uli526x_board_info *db) +{ + u16 phy_reg; + + /* Phyxcer capability setting */ + phy_reg = uli_phy_read(db->ioaddr, + db->phy_addr, 4, db->chip_id) & ~0x01e0; + + if (db->media_mode & ULI526X_AUTO) { + /* AUTO Mode */ + phy_reg |= db->PHY_reg4; + } else { + /* Force Mode */ + switch (db->media_mode) { + case ULI526X_10MHF: phy_reg |= 0x20; break; + case ULI526X_10MFD: phy_reg |= 0x40; break; + case ULI526X_100MHF: phy_reg |= 0x80; break; + case ULI526X_100MFD: phy_reg |= 0x100; break; + } + + } + + /* Write new capability to Phyxcer Reg4 */ + if (!(phy_reg & 0x01e0)) { + phy_reg |= db->PHY_reg4; + db->media_mode |= ULI526X_AUTO; + } + uli_phy_write(db->ioaddr, db->phy_addr, 4, phy_reg, db->chip_id); + + /* Restart Auto-Negotiation */ + uli_phy_write(db->ioaddr, db->phy_addr, 0, 0x1200, db->chip_id); + udelay(50); +} + +/* + * Write a word to Phy register + */ + +static void uli_phy_write(unsigned long iobase, u8 phy_addr, u8 offset, + u16 phy_data, u32 chip_id) +{ + u16 i; + unsigned long ioaddr; + + if (chip_id == PCI_ULI5263_ID) { + phy_writeby_cr10(iobase, phy_addr, offset, phy_data); + return; + } + /* M5261/M5263 Chip */ + ioaddr = iobase + DCR9; + + /* Send 33 synchronization clock to Phy controller */ + for (i = 0; i < 35; i++) + phy_write_1bit(ioaddr, PHY_DATA_1, chip_id); + + /* Send start command(01) to Phy */ + phy_write_1bit(ioaddr, PHY_DATA_0, chip_id); + phy_write_1bit(ioaddr, PHY_DATA_1, chip_id); + + /* Send write command(01) to Phy */ + phy_write_1bit(ioaddr, PHY_DATA_0, chip_id); + phy_write_1bit(ioaddr, PHY_DATA_1, chip_id); + + /* Send Phy address */ + for (i = 0x10; i > 0; i = i >> 1) + phy_write_1bit(ioaddr, phy_addr & i ? + PHY_DATA_1 : PHY_DATA_0, chip_id); + + /* Send register address */ + for (i = 0x10; i > 0; i = i >> 1) + phy_write_1bit(ioaddr, offset & i ? + PHY_DATA_1 : PHY_DATA_0, chip_id); + + /* written trasnition */ + phy_write_1bit(ioaddr, PHY_DATA_1, chip_id); + phy_write_1bit(ioaddr, PHY_DATA_0, chip_id); + + /* Write a word data to PHY controller */ + for (i = 0x8000; i > 0; i >>= 1) + phy_write_1bit(ioaddr, phy_data & i ? + PHY_DATA_1 : PHY_DATA_0, chip_id); +} + +/* + * Read a word data from phy register + */ + +static u16 uli_phy_read(unsigned long iobase, u8 phy_addr, u8 offset, + u32 chip_id) +{ + int i; + u16 phy_data; + unsigned long ioaddr; + + if (chip_id == PCI_ULI5263_ID) + return phy_readby_cr10(iobase, phy_addr, offset); + /* M5261/M5263 Chip */ + ioaddr = iobase + DCR9; + + /* Send 33 synchronization clock to Phy controller */ + for (i = 0; i < 35; i++) + phy_write_1bit(ioaddr, PHY_DATA_1, chip_id); + + /* Send start command(01) to Phy */ + phy_write_1bit(ioaddr, PHY_DATA_0, chip_id); + phy_write_1bit(ioaddr, PHY_DATA_1, chip_id); + + /* Send read command(10) to Phy */ + phy_write_1bit(ioaddr, PHY_DATA_1, chip_id); + phy_write_1bit(ioaddr, PHY_DATA_0, chip_id); + + /* Send Phy address */ + for (i = 0x10; i > 0; i = i >> 1) + phy_write_1bit(ioaddr, phy_addr & i ? + PHY_DATA_1 : PHY_DATA_0, chip_id); + + /* Send register address */ + for (i = 0x10; i > 0; i = i >> 1) + phy_write_1bit(ioaddr, offset & i ? + PHY_DATA_1 : PHY_DATA_0, chip_id); + + /* Skip transition state */ + phy_read_1bit(ioaddr, chip_id); + + /* read 16bit data */ + for (phy_data = 0, i = 0; i < 16; i++) { + phy_data <<= 1; + phy_data |= phy_read_1bit(ioaddr, chip_id); + } + + return phy_data; +} + +static u16 phy_readby_cr10(unsigned long iobase, u8 phy_addr, u8 offset) +{ + unsigned long ioaddr, cr10_value; + + ioaddr = iobase + DCR10; + cr10_value = phy_addr; + cr10_value = (cr10_value<<5) + offset; + cr10_value = (cr10_value<<16) + 0x08000000; + outl(cr10_value, ioaddr); + udelay(1); + while (1) { + cr10_value = inl(ioaddr); + if (cr10_value & 0x10000000) + break; + } + return (cr10_value&0x0ffff); +} + +static void phy_writeby_cr10(unsigned long iobase, u8 phy_addr, + u8 offset, u16 phy_data) +{ + unsigned long ioaddr, cr10_value; + + ioaddr = iobase + DCR10; + cr10_value = phy_addr; + cr10_value = (cr10_value<<5) + offset; + cr10_value = (cr10_value<<16) + 0x04000000 + phy_data; + outl(cr10_value, ioaddr); + udelay(1); +} +/* + * Write one bit data to Phy Controller + */ + +static void phy_write_1bit(unsigned long ioaddr, u32 phy_data, u32 chip_id) +{ + outl(phy_data , ioaddr); /* MII Clock Low */ + udelay(1); + outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */ + udelay(1); + outl(phy_data , ioaddr); /* MII Clock Low */ + udelay(1); +} + +/* + * Read one bit phy data from PHY controller + */ + +static u16 phy_read_1bit(unsigned long ioaddr, u32 chip_id) +{ + u16 phy_data; + + outl(0x50000 , ioaddr); + udelay(1); + phy_data = (inl(ioaddr) >> 19) & 0x1; + outl(0x40000 , ioaddr); + udelay(1); + + return phy_data; +} + +/* + * Set MAC address to ID Table + */ + +static void set_mac_addr(struct eth_device *dev) +{ + int i; + u16 addr; + struct uli526x_board_info *db = dev->priv; + outl(0x10000, db->ioaddr + DCR0); /* Diagnosis mode */ + /* Reset dianostic pointer port */ + outl(0x1c0, db->ioaddr + DCR13); + outl(0, db->ioaddr + DCR14); /* Clear reset port */ + outl(0x10, db->ioaddr + DCR14); /* Reset ID Table pointer */ + outl(0, db->ioaddr + DCR14); /* Clear reset port */ + outl(0, db->ioaddr + DCR13); /* Clear CR13 */ + /* Select ID Table access port */ + outl(0x1b0, db->ioaddr + DCR13); + /* Read MAC address from CR14 */ + for (i = 0; i < 3; i++) { + addr = dev->enetaddr[2 * i] | (dev->enetaddr[2 * i + 1] << 8); + outl(addr, db->ioaddr + DCR14); + } + /* write end */ + outl(0, db->ioaddr + DCR13); /* Clear CR13 */ + outl(0, db->ioaddr + DCR0); /* Clear CR0 */ + udelay(10); + return; +} diff --git a/sources/uboot-be550/drivers/net/vsc7385.c b/sources/uboot-be550/drivers/net/vsc7385.c new file mode 100644 index 00000000..c6d6dce4 --- /dev/null +++ b/sources/uboot-be550/drivers/net/vsc7385.c @@ -0,0 +1,98 @@ +/* + * Vitesse 7385 Switch Firmware Upload + * + * Author: Timur Tabi + * + * Copyright 2008 Freescale Semiconductor, Inc. This file is licensed + * under the terms of the GNU General Public License version 2. This + * program is licensed "as is" without any warranty of any kind, whether + * express or implied. + * + * This module uploads proprietary firmware for the Vitesse VSC7385 5-port + * switch. + */ + +#include +#include +#include +#include +#include +#include "vsc7385.h" + +/* + * Upload a Vitesse VSC7385 firmware image to the hardware + * + * This function takes a pointer to a VSC7385 firmware image and a size, and + * uploads that firmware to the VSC7385. + * + * This firmware is typically located at a board-specific flash address, + * and the size is typically 8KB. + * + * The firmware is Vitesse proprietary. + * + * Further details on the register information can be obtained from Vitesse. + */ +int vsc7385_upload_firmware(void *firmware, unsigned int size) +{ + u8 *fw = firmware; + unsigned int i; + + u32 *gloreset = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c050); + u32 *icpu_ctrl = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c040); + u32 *icpu_addr = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c044); + u32 *icpu_data = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c048); + u32 *icpu_rom_map = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c070); +#ifdef DEBUG + u32 *chipid = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c060); +#endif + + out_be32(gloreset, 3); + udelay(200); + + out_be32(icpu_ctrl, 0x8E); + udelay(20); + + out_be32(icpu_rom_map, 1); + udelay(20); + + /* Write the firmware to I-RAM */ + out_be32(icpu_addr, 0); + udelay(20); + + for (i = 0; i < size; i++) { + out_be32(icpu_data, fw[i]); + udelay(20); + if (ctrlc()) + return -EINTR; + } + + /* Read back and compare */ + out_be32(icpu_addr, 0); + udelay(20); + + for (i = 0; i < size; i++) { + u8 value; + + value = (u8) in_be32(icpu_data); + udelay(20); + if (value != fw[i]) { + debug("VSC7385: Upload mismatch: address 0x%x, " + "read value 0x%x, image value 0x%x\n", + i, value, fw[i]); + + return -EIO; + } + if (ctrlc()) + break; + } + + out_be32(icpu_ctrl, 0x0B); + udelay(20); + +#ifdef DEBUG + printf("VSC7385: Chip ID is %08x\n", in_be32(chipid)); + udelay(20); +#endif + + return 0; +} diff --git a/sources/uboot-be550/drivers/net/vsc9953.c b/sources/uboot-be550/drivers/net/vsc9953.c new file mode 100644 index 00000000..7595db1a --- /dev/null +++ b/sources/uboot-be550/drivers/net/vsc9953.c @@ -0,0 +1,2261 @@ +/* + * Copyright 2014 - 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Driver for the Vitesse VSC9953 L2 Switch + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static struct vsc9953_info vsc9953_l2sw = { + .port[0] = VSC9953_PORT_INFO_INITIALIZER(0), + .port[1] = VSC9953_PORT_INFO_INITIALIZER(1), + .port[2] = VSC9953_PORT_INFO_INITIALIZER(2), + .port[3] = VSC9953_PORT_INFO_INITIALIZER(3), + .port[4] = VSC9953_PORT_INFO_INITIALIZER(4), + .port[5] = VSC9953_PORT_INFO_INITIALIZER(5), + .port[6] = VSC9953_PORT_INFO_INITIALIZER(6), + .port[7] = VSC9953_PORT_INFO_INITIALIZER(7), + .port[8] = VSC9953_PORT_INFO_INITIALIZER(8), + .port[9] = VSC9953_PORT_INFO_INITIALIZER(9), +}; + +void vsc9953_port_info_set_mdio(int port_no, struct mii_dev *bus) +{ + if (!VSC9953_PORT_CHECK(port_no)) + return; + + vsc9953_l2sw.port[port_no].bus = bus; +} + +void vsc9953_port_info_set_phy_address(int port_no, int address) +{ + if (!VSC9953_PORT_CHECK(port_no)) + return; + + vsc9953_l2sw.port[port_no].phyaddr = address; +} + +void vsc9953_port_info_set_phy_int(int port_no, phy_interface_t phy_int) +{ + if (!VSC9953_PORT_CHECK(port_no)) + return; + + vsc9953_l2sw.port[port_no].enet_if = phy_int; +} + +void vsc9953_port_enable(int port_no) +{ + if (!VSC9953_PORT_CHECK(port_no)) + return; + + vsc9953_l2sw.port[port_no].enabled = 1; +} + +void vsc9953_port_disable(int port_no) +{ + if (!VSC9953_PORT_CHECK(port_no)) + return; + + vsc9953_l2sw.port[port_no].enabled = 0; +} + +static void vsc9953_mdio_write(struct vsc9953_mii_mng *phyregs, int port_addr, + int regnum, int value) +{ + int timeout = 50000; + + out_le32(&phyregs->miimcmd, (0x1 << 31) | ((port_addr & 0x1f) << 25) | + ((regnum & 0x1f) << 20) | ((value & 0xffff) << 4) | + (0x1 << 1)); + asm("sync"); + + while ((in_le32(&phyregs->miimstatus) & 0x8) && --timeout) + udelay(1); + + if (timeout == 0) + debug("Timeout waiting for MDIO write\n"); +} + +static int vsc9953_mdio_read(struct vsc9953_mii_mng *phyregs, int port_addr, + int regnum) +{ + int value = 0xFFFF; + int timeout = 50000; + + while ((in_le32(&phyregs->miimstatus) & MIIMIND_OPR_PEND) && --timeout) + udelay(1); + if (timeout == 0) { + debug("Timeout waiting for MDIO operation to finish\n"); + return value; + } + + /* Put the address of the phy, and the register + * number into MIICMD + */ + out_le32(&phyregs->miimcmd, (0x1 << 31) | ((port_addr & 0x1f) << 25) | + ((regnum & 0x1f) << 20) | ((value & 0xffff) << 4) | + (0x2 << 1)); + + timeout = 50000; + /* Wait for the the indication that the read is done */ + while ((in_le32(&phyregs->miimstatus) & 0x8) && --timeout) + udelay(1); + if (timeout == 0) + debug("Timeout waiting for MDIO read\n"); + + /* Grab the value read from the PHY */ + value = in_le32(&phyregs->miimdata); + + if ((value & 0x00030000) == 0) + return value & 0x0000ffff; + + return value; +} + +static int init_phy(struct eth_device *dev) +{ + struct vsc9953_port_info *l2sw_port = dev->priv; + struct phy_device *phydev = NULL; + +#ifdef CONFIG_PHYLIB + if (!l2sw_port->bus) + return 0; + phydev = phy_connect(l2sw_port->bus, l2sw_port->phyaddr, dev, + l2sw_port->enet_if); + if (!phydev) { + printf("Failed to connect\n"); + return -1; + } + + phydev->supported &= SUPPORTED_10baseT_Half | + SUPPORTED_10baseT_Full | + SUPPORTED_100baseT_Half | + SUPPORTED_100baseT_Full | + SUPPORTED_1000baseT_Full; + phydev->advertising = phydev->supported; + + l2sw_port->phydev = phydev; + + phy_config(phydev); +#endif + + return 0; +} + +static int vsc9953_port_init(int port_no) +{ + struct eth_device *dev; + + /* Internal ports never have a PHY */ + if (VSC9953_INTERNAL_PORT_CHECK(port_no)) + return 0; + + /* alloc eth device */ + dev = (struct eth_device *)calloc(1, sizeof(struct eth_device)); + if (!dev) + return -ENOMEM; + + sprintf(dev->name, "SW@PORT%d", port_no); + dev->priv = &vsc9953_l2sw.port[port_no]; + dev->init = NULL; + dev->halt = NULL; + dev->send = NULL; + dev->recv = NULL; + + if (init_phy(dev)) { + free(dev); + return -ENODEV; + } + + return 0; +} + +static int vsc9953_vlan_table_poll_idle(void) +{ + struct vsc9953_analyzer *l2ana_reg; + int timeout; + + l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + + VSC9953_ANA_OFFSET); + + timeout = 50000; + while (((in_le32(&l2ana_reg->ana_tables.vlan_access) & + VSC9953_VLAN_CMD_MASK) != VSC9953_VLAN_CMD_IDLE) && --timeout) + udelay(1); + + return timeout ? 0 : -EBUSY; +} + +#ifdef CONFIG_CMD_ETHSW +/* Add/remove a port to/from a VLAN */ +static void vsc9953_vlan_table_membership_set(int vid, u32 port_no, u8 add) +{ + u32 val; + struct vsc9953_analyzer *l2ana_reg; + + l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + + VSC9953_ANA_OFFSET); + + if (vsc9953_vlan_table_poll_idle() < 0) { + debug("VLAN table timeout\n"); + return; + } + + val = in_le32(&l2ana_reg->ana_tables.vlan_tidx); + val = bitfield_replace_by_mask(val, VSC9953_ANA_TBL_VID_MASK, vid); + out_le32(&l2ana_reg->ana_tables.vlan_tidx, val); + + clrsetbits_le32(&l2ana_reg->ana_tables.vlan_access, + VSC9953_VLAN_CMD_MASK, VSC9953_VLAN_CMD_READ); + + if (vsc9953_vlan_table_poll_idle() < 0) { + debug("VLAN table timeout\n"); + return; + } + + val = in_le32(&l2ana_reg->ana_tables.vlan_tidx); + val = bitfield_replace_by_mask(val, VSC9953_ANA_TBL_VID_MASK, vid); + out_le32(&l2ana_reg->ana_tables.vlan_tidx, val); + + val = in_le32(&l2ana_reg->ana_tables.vlan_access); + if (!add) { + val = bitfield_replace_by_mask(val, VSC9953_VLAN_CMD_MASK, + VSC9953_VLAN_CMD_WRITE) & + ~(bitfield_replace_by_mask(0, VSC9953_VLAN_PORT_MASK, + (1 << port_no))); + ; + } else { + val = bitfield_replace_by_mask(val, VSC9953_VLAN_CMD_MASK, + VSC9953_VLAN_CMD_WRITE) | + bitfield_replace_by_mask(0, VSC9953_VLAN_PORT_MASK, + (1 << port_no)); + } + out_le32(&l2ana_reg->ana_tables.vlan_access, val); + + /* wait for VLAN table command to flush */ + if (vsc9953_vlan_table_poll_idle() < 0) { + debug("VLAN table timeout\n"); + return; + } +} + +/* show VLAN membership for a port */ +static void vsc9953_vlan_membership_show(int port_no) +{ + u32 val; + struct vsc9953_analyzer *l2ana_reg; + u32 vid; + + l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + + VSC9953_ANA_OFFSET); + + printf("Port %d VLAN membership: ", port_no); + + for (vid = 0; vid < VSC9953_MAX_VLAN; vid++) { + if (vsc9953_vlan_table_poll_idle() < 0) { + debug("VLAN table timeout\n"); + return; + } + + val = in_le32(&l2ana_reg->ana_tables.vlan_tidx); + val = bitfield_replace_by_mask(val, VSC9953_ANA_TBL_VID_MASK, + vid); + out_le32(&l2ana_reg->ana_tables.vlan_tidx, val); + + clrsetbits_le32(&l2ana_reg->ana_tables.vlan_access, + VSC9953_VLAN_CMD_MASK, VSC9953_VLAN_CMD_READ); + + if (vsc9953_vlan_table_poll_idle() < 0) { + debug("VLAN table timeout\n"); + return; + } + + val = in_le32(&l2ana_reg->ana_tables.vlan_access); + + if (bitfield_extract_by_mask(val, VSC9953_VLAN_PORT_MASK) & + (1 << port_no)) + printf("%d ", vid); + } + printf("\n"); +} +#endif + +/* vlan table set/clear all membership of vid */ +static void vsc9953_vlan_table_membership_all_set(int vid, int set_member) +{ + uint val; + struct vsc9953_analyzer *l2ana_reg; + + l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + + VSC9953_ANA_OFFSET); + + if (vsc9953_vlan_table_poll_idle() < 0) { + debug("VLAN table timeout\n"); + return; + } + + /* read current vlan configuration */ + val = in_le32(&l2ana_reg->ana_tables.vlan_tidx); + out_le32(&l2ana_reg->ana_tables.vlan_tidx, + bitfield_replace_by_mask(val, VSC9953_ANA_TBL_VID_MASK, vid)); + + clrsetbits_le32(&l2ana_reg->ana_tables.vlan_access, + VSC9953_VLAN_CMD_MASK, VSC9953_VLAN_CMD_READ); + + if (vsc9953_vlan_table_poll_idle() < 0) { + debug("VLAN table timeout\n"); + return; + } + + val = in_le32(&l2ana_reg->ana_tables.vlan_tidx); + out_le32(&l2ana_reg->ana_tables.vlan_tidx, + bitfield_replace_by_mask(val, VSC9953_ANA_TBL_VID_MASK, vid)); + + clrsetbits_le32(&l2ana_reg->ana_tables.vlan_access, + VSC9953_VLAN_PORT_MASK | VSC9953_VLAN_CMD_MASK, + VSC9953_VLAN_CMD_WRITE | + (set_member ? VSC9953_VLAN_PORT_MASK : 0)); +} + +#ifdef CONFIG_CMD_ETHSW +/* Get PVID of a VSC9953 port */ +static int vsc9953_port_vlan_pvid_get(int port_nr, int *pvid) +{ + u32 val; + struct vsc9953_analyzer *l2ana_reg; + + /* Administrative down */ + if (vsc9953_l2sw.port[port_nr].enabled) { + printf("Port %d is administrative down\n", port_nr); + return -1; + } + + l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + + VSC9953_ANA_OFFSET); + + /* Get ingress PVID */ + val = in_le32(&l2ana_reg->port[port_nr].vlan_cfg); + *pvid = bitfield_extract_by_mask(val, VSC9953_VLAN_CFG_VID_MASK); + + return 0; +} +#endif + +/* Set PVID for a VSC9953 port */ +static void vsc9953_port_vlan_pvid_set(int port_no, int pvid) +{ + uint val; + struct vsc9953_analyzer *l2ana_reg; + struct vsc9953_rew_reg *l2rew_reg; + + /* Administrative down */ + if (!vsc9953_l2sw.port[port_no].enabled) { + printf("Port %d is administrative down\n", port_no); + return; + } + + l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + + VSC9953_ANA_OFFSET); + l2rew_reg = (struct vsc9953_rew_reg *)(VSC9953_OFFSET + + VSC9953_REW_OFFSET); + + /* Set PVID on ingress */ + val = in_le32(&l2ana_reg->port[port_no].vlan_cfg); + val = bitfield_replace_by_mask(val, VSC9953_VLAN_CFG_VID_MASK, pvid); + out_le32(&l2ana_reg->port[port_no].vlan_cfg, val); + + /* Set PVID on egress */ + val = in_le32(&l2rew_reg->port[port_no].port_vlan_cfg); + val = bitfield_replace_by_mask(val, VSC9953_PORT_VLAN_CFG_VID_MASK, + pvid); + out_le32(&l2rew_reg->port[port_no].port_vlan_cfg, val); +} + +static void vsc9953_port_all_vlan_pvid_set(int pvid) +{ + int i; + + for (i = 0; i < VSC9953_MAX_PORTS; i++) + vsc9953_port_vlan_pvid_set(i, pvid); +} + +/* Enable/disable vlan aware of a VSC9953 port */ +static void vsc9953_port_vlan_aware_set(int port_no, int enabled) +{ + struct vsc9953_analyzer *l2ana_reg; + + /* Administrative down */ + if (!vsc9953_l2sw.port[port_no].enabled) { + printf("Port %d is administrative down\n", port_no); + return; + } + + l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + + VSC9953_ANA_OFFSET); + + if (enabled) + setbits_le32(&l2ana_reg->port[port_no].vlan_cfg, + VSC9953_VLAN_CFG_AWARE_ENA); + else + clrbits_le32(&l2ana_reg->port[port_no].vlan_cfg, + VSC9953_VLAN_CFG_AWARE_ENA); +} + +/* Set all VSC9953 ports' vlan aware */ +static void vsc9953_port_all_vlan_aware_set(int enabled) +{ + int i; + + for (i = 0; i < VSC9953_MAX_PORTS; i++) + vsc9953_port_vlan_aware_set(i, enabled); +} + +/* Enable/disable vlan pop count of a VSC9953 port */ +static void vsc9953_port_vlan_popcnt_set(int port_no, int popcnt) +{ + uint val; + struct vsc9953_analyzer *l2ana_reg; + + /* Administrative down */ + if (!vsc9953_l2sw.port[port_no].enabled) { + printf("Port %d is administrative down\n", port_no); + return; + } + + if (popcnt > 3 || popcnt < 0) { + printf("Invalid pop count value: %d\n", port_no); + return; + } + + l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + + VSC9953_ANA_OFFSET); + + val = in_le32(&l2ana_reg->port[port_no].vlan_cfg); + val = bitfield_replace_by_mask(val, VSC9953_VLAN_CFG_POP_CNT_MASK, + popcnt); + out_le32(&l2ana_reg->port[port_no].vlan_cfg, val); +} + +/* Set all VSC9953 ports' pop count */ +static void vsc9953_port_all_vlan_poncnt_set(int popcnt) +{ + int i; + + for (i = 0; i < VSC9953_MAX_PORTS; i++) + vsc9953_port_vlan_popcnt_set(i, popcnt); +} + +/* Enable/disable learning for frames dropped due to ingress filtering */ +static void vsc9953_vlan_ingr_fltr_learn_drop(int enable) +{ + struct vsc9953_analyzer *l2ana_reg; + + l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + + VSC9953_ANA_OFFSET); + + if (enable) + setbits_le32(&l2ana_reg->ana.adv_learn, VSC9953_VLAN_CHK); + else + clrbits_le32(&l2ana_reg->ana.adv_learn, VSC9953_VLAN_CHK); +} + +/* Egress untag modes of a VSC9953 port */ +enum egress_untag_mode { + EGRESS_UNTAG_ALL = 0, + EGRESS_UNTAG_PVID_AND_ZERO, + EGRESS_UNTAG_ZERO, + EGRESS_UNTAG_NONE, +}; + +#ifdef CONFIG_CMD_ETHSW +/* Get egress tagging configuration for a VSC9953 port */ +static int vsc9953_port_vlan_egr_untag_get(int port_no, + enum egress_untag_mode *mode) +{ + u32 val; + struct vsc9953_rew_reg *l2rew_reg; + + /* Administrative down */ + if (!vsc9953_l2sw.port[port_no].enabled) { + printf("Port %d is administrative down\n", port_no); + return -1; + } + + l2rew_reg = (struct vsc9953_rew_reg *)(VSC9953_OFFSET + + VSC9953_REW_OFFSET); + + val = in_le32(&l2rew_reg->port[port_no].port_tag_cfg); + + switch (val & VSC9953_TAG_CFG_MASK) { + case VSC9953_TAG_CFG_NONE: + *mode = EGRESS_UNTAG_ALL; + return 0; + case VSC9953_TAG_CFG_ALL_BUT_PVID_ZERO: + *mode = EGRESS_UNTAG_PVID_AND_ZERO; + return 0; + case VSC9953_TAG_CFG_ALL_BUT_ZERO: + *mode = EGRESS_UNTAG_ZERO; + return 0; + case VSC9953_TAG_CFG_ALL: + *mode = EGRESS_UNTAG_NONE; + return 0; + default: + printf("Unknown egress tagging configuration for port %d\n", + port_no); + return -1; + } +} + +/* Show egress tagging configuration for a VSC9953 port */ +static void vsc9953_port_vlan_egr_untag_show(int port_no) +{ + enum egress_untag_mode mode; + + if (vsc9953_port_vlan_egr_untag_get(port_no, &mode)) { + printf("%7d\t%17s\n", port_no, "-"); + return; + } + + printf("%7d\t", port_no); + switch (mode) { + case EGRESS_UNTAG_ALL: + printf("%17s\n", "all"); + break; + case EGRESS_UNTAG_NONE: + printf("%17s\n", "none"); + break; + case EGRESS_UNTAG_PVID_AND_ZERO: + printf("%17s\n", "PVID and 0"); + break; + case EGRESS_UNTAG_ZERO: + printf("%17s\n", "0"); + break; + default: + printf("%17s\n", "-"); + } +} +#endif + +static void vsc9953_port_vlan_egr_untag_set(int port_no, + enum egress_untag_mode mode) +{ + struct vsc9953_rew_reg *l2rew_reg; + + /* Administrative down */ + if (!vsc9953_l2sw.port[port_no].enabled) { + printf("Port %d is administrative down\n", port_no); + return; + } + + l2rew_reg = (struct vsc9953_rew_reg *)(VSC9953_OFFSET + + VSC9953_REW_OFFSET); + + switch (mode) { + case EGRESS_UNTAG_ALL: + clrsetbits_le32(&l2rew_reg->port[port_no].port_tag_cfg, + VSC9953_TAG_CFG_MASK, VSC9953_TAG_CFG_NONE); + break; + case EGRESS_UNTAG_PVID_AND_ZERO: + clrsetbits_le32(&l2rew_reg->port[port_no].port_tag_cfg, + VSC9953_TAG_CFG_MASK, + VSC9953_TAG_CFG_ALL_BUT_PVID_ZERO); + break; + case EGRESS_UNTAG_ZERO: + clrsetbits_le32(&l2rew_reg->port[port_no].port_tag_cfg, + VSC9953_TAG_CFG_MASK, + VSC9953_TAG_CFG_ALL_BUT_ZERO); + break; + case EGRESS_UNTAG_NONE: + clrsetbits_le32(&l2rew_reg->port[port_no].port_tag_cfg, + VSC9953_TAG_CFG_MASK, VSC9953_TAG_CFG_ALL); + break; + default: + printf("Unknown untag mode for port %d\n", port_no); + } +} + +static void vsc9953_port_all_vlan_egress_untagged_set( + enum egress_untag_mode mode) +{ + int i; + + for (i = 0; i < VSC9953_MAX_PORTS; i++) + vsc9953_port_vlan_egr_untag_set(i, mode); +} + +#ifdef CONFIG_CMD_ETHSW + +/* Enable/disable status of a VSC9953 port */ +static void vsc9953_port_status_set(int port_no, u8 enabled) +{ + struct vsc9953_qsys_reg *l2qsys_reg; + + /* Administrative down */ + if (!vsc9953_l2sw.port[port_no].enabled) + return; + + l2qsys_reg = (struct vsc9953_qsys_reg *)(VSC9953_OFFSET + + VSC9953_QSYS_OFFSET); + + if (enabled) + setbits_le32(&l2qsys_reg->sys.switch_port_mode[port_no], + VSC9953_PORT_ENA); + else + clrbits_le32(&l2qsys_reg->sys.switch_port_mode[port_no], + VSC9953_PORT_ENA); +} + +/* Start autonegotiation for a VSC9953 PHY */ +static void vsc9953_phy_autoneg(int port_no) +{ + if (!vsc9953_l2sw.port[port_no].phydev) + return; + + if (vsc9953_l2sw.port[port_no].phydev->drv->startup( + vsc9953_l2sw.port[port_no].phydev)) + printf("Failed to start PHY for port %d\n", port_no); +} + +/* Print a VSC9953 port's configuration */ +static void vsc9953_port_config_show(int port_no) +{ + int speed; + int duplex; + int link; + u8 enabled; + u32 val; + struct vsc9953_qsys_reg *l2qsys_reg; + + l2qsys_reg = (struct vsc9953_qsys_reg *)(VSC9953_OFFSET + + VSC9953_QSYS_OFFSET); + + val = in_le32(&l2qsys_reg->sys.switch_port_mode[port_no]); + enabled = vsc9953_l2sw.port[port_no].enabled && + (val & VSC9953_PORT_ENA); + + /* internal ports (8 and 9) are fixed */ + if (VSC9953_INTERNAL_PORT_CHECK(port_no)) { + link = 1; + speed = SPEED_2500; + duplex = DUPLEX_FULL; + } else { + if (vsc9953_l2sw.port[port_no].phydev) { + link = vsc9953_l2sw.port[port_no].phydev->link; + speed = vsc9953_l2sw.port[port_no].phydev->speed; + duplex = vsc9953_l2sw.port[port_no].phydev->duplex; + } else { + link = -1; + speed = -1; + duplex = -1; + } + } + + printf("%8d ", port_no); + printf("%8s ", enabled == 1 ? "enabled" : "disabled"); + printf("%8s ", link == 1 ? "up" : "down"); + + switch (speed) { + case SPEED_10: + printf("%8d ", 10); + break; + case SPEED_100: + printf("%8d ", 100); + break; + case SPEED_1000: + printf("%8d ", 1000); + break; + case SPEED_2500: + printf("%8d ", 2500); + break; + case SPEED_10000: + printf("%8d ", 10000); + break; + default: + printf("%8s ", "-"); + } + + printf("%8s\n", duplex == DUPLEX_FULL ? "full" : "half"); +} + +/* Show VSC9953 ports' statistics */ +static void vsc9953_port_statistics_show(int port_no) +{ + u32 rx_val; + u32 tx_val; + struct vsc9953_system_reg *l2sys_reg; + + /* Administrative down */ + if (!vsc9953_l2sw.port[port_no].enabled) { + printf("Port %d is administrative down\n", port_no); + return; + } + + l2sys_reg = (struct vsc9953_system_reg *)(VSC9953_OFFSET + + VSC9953_SYS_OFFSET); + + printf("Statistics for L2 Switch port %d:\n", port_no); + + /* Set counter view for our port */ + out_le32(&l2sys_reg->sys.stat_cfg, port_no); + +#define VSC9953_STATS_PRINTF "%-15s %10u" + + /* Get number of Rx and Tx frames */ + rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_short) + + in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_frag) + + in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_jabber) + + in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_long) + + in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_64) + + in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_65_127) + + in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_128_255) + + in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_256_511) + + in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_512_1023) + + in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_1024_1526) + + in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_jumbo); + tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_64) + + in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_65_127) + + in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_128_255) + + in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_256_511) + + in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_512_1023) + + in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_1024_1526) + + in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_jumbo); + printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n", + "Rx frames:", rx_val, "Tx frames:", tx_val); + + /* Get number of Rx and Tx bytes */ + rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_oct); + tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_oct); + printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n", + "Rx bytes:", rx_val, "Tx bytes:", tx_val); + + /* Get number of Rx frames received ok and Tx frames sent ok */ + rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_yellow_prio_0) + + in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_yellow_prio_1) + + in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_yellow_prio_2) + + in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_yellow_prio_3) + + in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_yellow_prio_4) + + in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_yellow_prio_5) + + in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_yellow_prio_6) + + in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_yellow_prio_7) + + in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_green_prio_0) + + in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_green_prio_1) + + in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_green_prio_2) + + in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_green_prio_3) + + in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_green_prio_4) + + in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_green_prio_5) + + in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_green_prio_6) + + in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_green_prio_7); + tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_64) + + in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_65_127) + + in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_128_255) + + in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_256_511) + + in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_512_1023) + + in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_1024_1526) + + in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_jumbo); + printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n", + "Rx frames ok:", rx_val, "Tx frames ok:", tx_val); + + /* Get number of Rx and Tx unicast frames */ + rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_uc); + tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_uc); + printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n", + "Rx unicast:", rx_val, "Tx unicast:", tx_val); + + /* Get number of Rx and Tx broadcast frames */ + rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_bc); + tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_bc); + printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n", + "Rx broadcast:", rx_val, "Tx broadcast:", tx_val); + + /* Get number of Rx and Tx frames of 64B */ + rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_64); + tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_64); + printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n", + "Rx 64B:", rx_val, "Tx 64B:", tx_val); + + /* Get number of Rx and Tx frames with sizes between 65B and 127B */ + rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_65_127); + tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_65_127); + printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n", + "Rx 65B-127B:", rx_val, "Tx 65B-127B:", tx_val); + + /* Get number of Rx and Tx frames with sizes between 128B and 255B */ + rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_128_255); + tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_128_255); + printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n", + "Rx 128B-255B:", rx_val, "Tx 128B-255B:", tx_val); + + /* Get number of Rx and Tx frames with sizes between 256B and 511B */ + rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_256_511); + tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_256_511); + printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n", + "Rx 256B-511B:", rx_val, "Tx 256B-511B:", tx_val); + + /* Get number of Rx and Tx frames with sizes between 512B and 1023B */ + rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_512_1023); + tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_512_1023); + printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n", + "Rx 512B-1023B:", rx_val, "Tx 512B-1023B:", tx_val); + + /* Get number of Rx and Tx frames with sizes between 1024B and 1526B */ + rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_1024_1526); + tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_1024_1526); + printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n", + "Rx 1024B-1526B:", rx_val, "Tx 1024B-1526B:", tx_val); + + /* Get number of Rx and Tx jumbo frames */ + rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_jumbo); + tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_jumbo); + printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n", + "Rx jumbo:", rx_val, "Tx jumbo:", tx_val); + + /* Get number of Rx and Tx dropped frames */ + rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_cat_drop) + + in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_tail) + + in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_yellow_prio_0) + + in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_yellow_prio_1) + + in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_yellow_prio_2) + + in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_yellow_prio_3) + + in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_yellow_prio_4) + + in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_yellow_prio_5) + + in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_yellow_prio_6) + + in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_yellow_prio_7) + + in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_green_prio_0) + + in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_green_prio_1) + + in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_green_prio_2) + + in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_green_prio_3) + + in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_green_prio_4) + + in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_green_prio_5) + + in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_green_prio_6) + + in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_green_prio_7); + tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_drop) + + in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_aged); + printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n", + "Rx drops:", rx_val, "Tx drops:", tx_val); + + /* + * Get number of Rx frames with CRC or alignment errors + * and number of detected Tx collisions + */ + rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_crc); + tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_col); + printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n", + "Rx CRC&align:", rx_val, "Tx coll:", tx_val); + + /* + * Get number of Rx undersized frames and + * number of Tx aged frames + */ + rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_short); + tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_aged); + printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n", + "Rx undersize:", rx_val, "Tx aged:", tx_val); + + /* Get number of Rx oversized frames */ + rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_long); + printf(VSC9953_STATS_PRINTF"\n", "Rx oversized:", rx_val); + + /* Get number of Rx fragmented frames */ + rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_frag); + printf(VSC9953_STATS_PRINTF"\n", "Rx fragments:", rx_val); + + /* Get number of Rx jabber errors */ + rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_jabber); + printf(VSC9953_STATS_PRINTF"\n", "Rx jabbers:", rx_val); + + /* + * Get number of Rx frames filtered due to classification rules or + * no destination ports + */ + rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_cat_drop) + + in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_local); + printf(VSC9953_STATS_PRINTF"\n", "Rx filtered:", rx_val); + + printf("\n"); +} + +/* Clear statistics for a VSC9953 port */ +static void vsc9953_port_statistics_clear(int port_no) +{ + struct vsc9953_system_reg *l2sys_reg; + + /* Administrative down */ + if (!vsc9953_l2sw.port[port_no].enabled) { + printf("Port %d is administrative down\n", port_no); + return; + } + + l2sys_reg = (struct vsc9953_system_reg *)(VSC9953_OFFSET + + VSC9953_SYS_OFFSET); + + /* Clear all counter groups for our ports */ + out_le32(&l2sys_reg->sys.stat_cfg, port_no | + VSC9953_STAT_CLEAR_RX | VSC9953_STAT_CLEAR_TX | + VSC9953_STAT_CLEAR_DR); +} + +enum port_learn_mode { + PORT_LEARN_NONE, + PORT_LEARN_AUTO +}; + +/* Set learning configuration for a VSC9953 port */ +static void vsc9953_port_learn_mode_set(int port_no, enum port_learn_mode mode) +{ + struct vsc9953_analyzer *l2ana_reg; + + /* Administrative down */ + if (!vsc9953_l2sw.port[port_no].enabled) { + printf("Port %d is administrative down\n", port_no); + return; + } + + l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + + VSC9953_ANA_OFFSET); + + switch (mode) { + case PORT_LEARN_NONE: + clrbits_le32(&l2ana_reg->port[port_no].port_cfg, + VSC9953_PORT_CFG_LEARN_DROP | + VSC9953_PORT_CFG_LEARN_CPU | + VSC9953_PORT_CFG_LEARN_AUTO | + VSC9953_PORT_CFG_LEARN_ENA); + break; + case PORT_LEARN_AUTO: + clrsetbits_le32(&l2ana_reg->port[port_no].port_cfg, + VSC9953_PORT_CFG_LEARN_DROP | + VSC9953_PORT_CFG_LEARN_CPU, + VSC9953_PORT_CFG_LEARN_ENA | + VSC9953_PORT_CFG_LEARN_AUTO); + break; + default: + printf("Unknown learn mode for port %d\n", port_no); + } +} + +/* Get learning configuration for a VSC9953 port */ +static int vsc9953_port_learn_mode_get(int port_no, enum port_learn_mode *mode) +{ + u32 val; + struct vsc9953_analyzer *l2ana_reg; + + /* Administrative down */ + if (!vsc9953_l2sw.port[port_no].enabled) { + printf("Port %d is administrative down\n", port_no); + return -1; + } + + l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + + VSC9953_ANA_OFFSET); + + /* For now we only support HW learning (auto) and no learning */ + val = in_le32(&l2ana_reg->port[port_no].port_cfg); + if ((val & (VSC9953_PORT_CFG_LEARN_ENA | + VSC9953_PORT_CFG_LEARN_AUTO)) == + (VSC9953_PORT_CFG_LEARN_ENA | VSC9953_PORT_CFG_LEARN_AUTO)) + *mode = PORT_LEARN_AUTO; + else + *mode = PORT_LEARN_NONE; + + return 0; +} + +/* wait for FDB to become available */ +static int vsc9953_mac_table_poll_idle(void) +{ + struct vsc9953_analyzer *l2ana_reg; + u32 timeout; + + l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + + VSC9953_ANA_OFFSET); + + timeout = 50000; + while (((in_le32(&l2ana_reg->ana_tables.mac_access) & + VSC9953_MAC_CMD_MASK) != + VSC9953_MAC_CMD_IDLE) && --timeout) + udelay(1); + + return timeout ? 0 : -EBUSY; +} + +/* enum describing available commands for the MAC table */ +enum mac_table_cmd { + MAC_TABLE_READ, + MAC_TABLE_LOOKUP, + MAC_TABLE_WRITE, + MAC_TABLE_LEARN, + MAC_TABLE_FORGET, + MAC_TABLE_GET_NEXT, + MAC_TABLE_AGE, +}; + +/* Issues a command to the FDB table */ +static int vsc9953_mac_table_cmd(enum mac_table_cmd cmd) +{ + struct vsc9953_analyzer *l2ana_reg; + + l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + + VSC9953_ANA_OFFSET); + + switch (cmd) { + case MAC_TABLE_READ: + clrsetbits_le32(&l2ana_reg->ana_tables.mac_access, + VSC9953_MAC_CMD_MASK | VSC9953_MAC_CMD_VALID, + VSC9953_MAC_CMD_READ); + break; + case MAC_TABLE_LOOKUP: + clrsetbits_le32(&l2ana_reg->ana_tables.mac_access, + VSC9953_MAC_CMD_MASK, VSC9953_MAC_CMD_READ | + VSC9953_MAC_CMD_VALID); + break; + case MAC_TABLE_WRITE: + clrsetbits_le32(&l2ana_reg->ana_tables.mac_access, + VSC9953_MAC_CMD_MASK | + VSC9953_MAC_ENTRYTYPE_MASK, + VSC9953_MAC_CMD_WRITE | + VSC9953_MAC_ENTRYTYPE_LOCKED); + break; + case MAC_TABLE_LEARN: + clrsetbits_le32(&l2ana_reg->ana_tables.mac_access, + VSC9953_MAC_CMD_MASK | + VSC9953_MAC_ENTRYTYPE_MASK, + VSC9953_MAC_CMD_LEARN | + VSC9953_MAC_ENTRYTYPE_LOCKED | + VSC9953_MAC_CMD_VALID); + break; + case MAC_TABLE_FORGET: + clrsetbits_le32(&l2ana_reg->ana_tables.mac_access, + VSC9953_MAC_CMD_MASK | + VSC9953_MAC_ENTRYTYPE_MASK, + VSC9953_MAC_CMD_FORGET); + break; + case MAC_TABLE_GET_NEXT: + clrsetbits_le32(&l2ana_reg->ana_tables.mac_access, + VSC9953_MAC_CMD_MASK | + VSC9953_MAC_ENTRYTYPE_MASK, + VSC9953_MAC_CMD_NEXT); + break; + case MAC_TABLE_AGE: + clrsetbits_le32(&l2ana_reg->ana_tables.mac_access, + VSC9953_MAC_CMD_MASK | + VSC9953_MAC_ENTRYTYPE_MASK, + VSC9953_MAC_CMD_AGE); + break; + default: + printf("Unknown MAC table command\n"); + } + + if (vsc9953_mac_table_poll_idle() < 0) { + debug("MAC table timeout\n"); + return -1; + } + + return 0; +} + +/* show the FDB entries that correspond to a port and a VLAN */ +static void vsc9953_mac_table_show(int port_no, int vid) +{ + int rc[VSC9953_MAX_PORTS]; + enum port_learn_mode mode[VSC9953_MAX_PORTS]; + int i; + u32 val; + u32 vlan; + u32 mach; + u32 macl; + u32 dest_indx; + struct vsc9953_analyzer *l2ana_reg; + + l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + + VSC9953_ANA_OFFSET); + + /* disable auto learning */ + if (port_no == ETHSW_CMD_PORT_ALL) { + for (i = 0; i < VSC9953_MAX_PORTS; i++) { + rc[i] = vsc9953_port_learn_mode_get(i, &mode[i]); + if (!rc[i] && mode[i] != PORT_LEARN_NONE) + vsc9953_port_learn_mode_set(i, PORT_LEARN_NONE); + } + } else { + rc[port_no] = vsc9953_port_learn_mode_get(port_no, + &mode[port_no]); + if (!rc[port_no] && mode[port_no] != PORT_LEARN_NONE) + vsc9953_port_learn_mode_set(port_no, PORT_LEARN_NONE); + } + + /* write port and vid to get selected FDB entries */ + val = in_le32(&l2ana_reg->ana.anag_efil); + if (port_no != ETHSW_CMD_PORT_ALL) { + val = bitfield_replace_by_mask(val, VSC9953_AGE_PORT_MASK, + port_no) | VSC9953_AGE_PORT_EN; + } + if (vid != ETHSW_CMD_VLAN_ALL) { + val = bitfield_replace_by_mask(val, VSC9953_AGE_VID_MASK, + vid) | VSC9953_AGE_VID_EN; + } + out_le32(&l2ana_reg->ana.anag_efil, val); + + /* set MAC and VLAN to 0 to look from beginning */ + clrbits_le32(&l2ana_reg->ana_tables.mach_data, + VSC9953_MAC_VID_MASK | VSC9953_MAC_MACH_MASK); + out_le32(&l2ana_reg->ana_tables.macl_data, 0); + + /* get entries */ + printf("%10s %17s %5s %4s\n", "EntryType", "MAC", "PORT", "VID"); + do { + if (vsc9953_mac_table_cmd(MAC_TABLE_GET_NEXT) < 0) { + debug("GET NEXT MAC table command failed\n"); + break; + } + + val = in_le32(&l2ana_reg->ana_tables.mac_access); + + /* get out when an invalid entry is found */ + if (!(val & VSC9953_MAC_CMD_VALID)) + break; + + switch (val & VSC9953_MAC_ENTRYTYPE_MASK) { + case VSC9953_MAC_ENTRYTYPE_NORMAL: + printf("%10s ", "Dynamic"); + break; + case VSC9953_MAC_ENTRYTYPE_LOCKED: + printf("%10s ", "Static"); + break; + case VSC9953_MAC_ENTRYTYPE_IPV4MCAST: + printf("%10s ", "IPv4 Mcast"); + break; + case VSC9953_MAC_ENTRYTYPE_IPV6MCAST: + printf("%10s ", "IPv6 Mcast"); + break; + default: + printf("%10s ", "Unknown"); + } + + dest_indx = bitfield_extract_by_mask(val, + VSC9953_MAC_DESTIDX_MASK); + + val = in_le32(&l2ana_reg->ana_tables.mach_data); + vlan = bitfield_extract_by_mask(val, VSC9953_MAC_VID_MASK); + mach = bitfield_extract_by_mask(val, VSC9953_MAC_MACH_MASK); + macl = in_le32(&l2ana_reg->ana_tables.macl_data); + + printf("%02x:%02x:%02x:%02x:%02x:%02x ", (mach >> 8) & 0xff, + mach & 0xff, (macl >> 24) & 0xff, (macl >> 16) & 0xff, + (macl >> 8) & 0xff, macl & 0xff); + printf("%5d ", dest_indx); + printf("%4d\n", vlan); + } while (1); + + /* set learning mode to previous value */ + if (port_no == ETHSW_CMD_PORT_ALL) { + for (i = 0; i < VSC9953_MAX_PORTS; i++) { + if (!rc[i] && mode[i] != PORT_LEARN_NONE) + vsc9953_port_learn_mode_set(i, mode[i]); + } + } else { + /* If administrative down, skip */ + if (!rc[port_no] && mode[port_no] != PORT_LEARN_NONE) + vsc9953_port_learn_mode_set(port_no, mode[port_no]); + } + + /* reset FDB port and VLAN FDB selection */ + clrbits_le32(&l2ana_reg->ana.anag_efil, VSC9953_AGE_PORT_EN | + VSC9953_AGE_PORT_MASK | VSC9953_AGE_VID_EN | + VSC9953_AGE_VID_MASK); +} + +/* Add a static FDB entry */ +static int vsc9953_mac_table_add(u8 port_no, uchar mac[6], int vid) +{ + u32 val; + struct vsc9953_analyzer *l2ana_reg; + + l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + + VSC9953_ANA_OFFSET); + + val = in_le32(&l2ana_reg->ana_tables.mach_data); + val = bitfield_replace_by_mask(val, VSC9953_MACHDATA_VID_MASK, vid) | + (mac[0] << 8) | (mac[1] << 0); + out_le32(&l2ana_reg->ana_tables.mach_data, val); + + out_le32(&l2ana_reg->ana_tables.macl_data, + (mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | + (mac[5] << 0)); + + /* set on which port is the MAC address added */ + val = in_le32(&l2ana_reg->ana_tables.mac_access); + val = bitfield_replace_by_mask(val, VSC9953_MAC_DESTIDX_MASK, port_no); + out_le32(&l2ana_reg->ana_tables.mac_access, val); + + if (vsc9953_mac_table_cmd(MAC_TABLE_LEARN) < 0) + return -1; + + /* check if the MAC address was indeed added */ + val = in_le32(&l2ana_reg->ana_tables.mach_data); + val = bitfield_replace_by_mask(val, VSC9953_MACHDATA_VID_MASK, vid) | + (mac[0] << 8) | (mac[1] << 0); + out_le32(&l2ana_reg->ana_tables.mach_data, val); + + out_le32(&l2ana_reg->ana_tables.macl_data, + (mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | + (mac[5] << 0)); + + if (vsc9953_mac_table_cmd(MAC_TABLE_READ) < 0) + return -1; + + val = in_le32(&l2ana_reg->ana_tables.mac_access); + + if ((port_no != bitfield_extract_by_mask(val, + VSC9953_MAC_DESTIDX_MASK))) { + printf("Failed to add MAC address\n"); + return -1; + } + return 0; +} + +/* Delete a FDB entry */ +static int vsc9953_mac_table_del(uchar mac[6], u16 vid) +{ + u32 val; + struct vsc9953_analyzer *l2ana_reg; + + l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + + VSC9953_ANA_OFFSET); + + /* check first if MAC entry is present */ + val = in_le32(&l2ana_reg->ana_tables.mach_data); + val = bitfield_replace_by_mask(val, VSC9953_MACHDATA_VID_MASK, vid) | + (mac[0] << 8) | (mac[1] << 0); + out_le32(&l2ana_reg->ana_tables.mach_data, val); + + out_le32(&l2ana_reg->ana_tables.macl_data, + (mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | + (mac[5] << 0)); + + if (vsc9953_mac_table_cmd(MAC_TABLE_LOOKUP) < 0) { + debug("Lookup in the MAC table failed\n"); + return -1; + } + + if (!(in_le32(&l2ana_reg->ana_tables.mac_access) & + VSC9953_MAC_CMD_VALID)) { + printf("The MAC address: %02x:%02x:%02x:%02x:%02x:%02x ", + mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); + printf("VLAN: %d does not exist.\n", vid); + return -1; + } + + /* FDB entry found, proceed to delete */ + val = in_le32(&l2ana_reg->ana_tables.mach_data); + val = bitfield_replace_by_mask(val, VSC9953_MACHDATA_VID_MASK, vid) | + (mac[0] << 8) | (mac[1] << 0); + out_le32(&l2ana_reg->ana_tables.mach_data, val); + + out_le32(&l2ana_reg->ana_tables.macl_data, (mac[2] << 24) | + (mac[3] << 16) | (mac[4] << 8) | (mac[5] << 0)); + + if (vsc9953_mac_table_cmd(MAC_TABLE_FORGET) < 0) + return -1; + + /* check if the MAC entry is still in FDB */ + val = in_le32(&l2ana_reg->ana_tables.mach_data); + val = bitfield_replace_by_mask(val, VSC9953_MACHDATA_VID_MASK, vid) | + (mac[0] << 8) | (mac[1] << 0); + out_le32(&l2ana_reg->ana_tables.mach_data, val); + + out_le32(&l2ana_reg->ana_tables.macl_data, (mac[2] << 24) | + (mac[3] << 16) | (mac[4] << 8) | (mac[5] << 0)); + + if (vsc9953_mac_table_cmd(MAC_TABLE_LOOKUP) < 0) { + debug("Lookup in the MAC table failed\n"); + return -1; + } + if (in_le32(&l2ana_reg->ana_tables.mac_access) & + VSC9953_MAC_CMD_VALID) { + printf("Failed to delete MAC address\n"); + return -1; + } + + return 0; +} + +/* age the unlocked entries in FDB */ +static void vsc9953_mac_table_age(int port_no, int vid) +{ + int rc[VSC9953_MAX_PORTS]; + enum port_learn_mode mode[VSC9953_MAX_PORTS]; + u32 val; + int i; + struct vsc9953_analyzer *l2ana_reg; + + l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + + VSC9953_ANA_OFFSET); + + /* set port and VID for selective aging */ + val = in_le32(&l2ana_reg->ana.anag_efil); + if (port_no != ETHSW_CMD_PORT_ALL) { + /* disable auto learning */ + rc[port_no] = vsc9953_port_learn_mode_get(port_no, + &mode[port_no]); + if (!rc[port_no] && mode[port_no] != PORT_LEARN_NONE) + vsc9953_port_learn_mode_set(port_no, PORT_LEARN_NONE); + + val = bitfield_replace_by_mask(val, VSC9953_AGE_PORT_MASK, + port_no) | VSC9953_AGE_PORT_EN; + } else { + /* disable auto learning on all ports */ + for (i = 0; i < VSC9953_MAX_PORTS; i++) { + rc[i] = vsc9953_port_learn_mode_get(i, &mode[i]); + if (!rc[i] && mode[i] != PORT_LEARN_NONE) + vsc9953_port_learn_mode_set(i, PORT_LEARN_NONE); + } + } + + if (vid != ETHSW_CMD_VLAN_ALL) { + val = bitfield_replace_by_mask(val, VSC9953_AGE_VID_MASK, vid) | + VSC9953_AGE_VID_EN; + } + out_le32(&l2ana_reg->ana.anag_efil, val); + + /* age the dynamic FDB entries */ + vsc9953_mac_table_cmd(MAC_TABLE_AGE); + + /* clear previously set port and VID */ + clrbits_le32(&l2ana_reg->ana.anag_efil, VSC9953_AGE_PORT_EN | + VSC9953_AGE_PORT_MASK | VSC9953_AGE_VID_EN | + VSC9953_AGE_VID_MASK); + + if (port_no != ETHSW_CMD_PORT_ALL) { + if (!rc[port_no] && mode[port_no] != PORT_LEARN_NONE) + vsc9953_port_learn_mode_set(port_no, mode[port_no]); + } else { + for (i = 0; i < VSC9953_MAX_PORTS; i++) { + if (!rc[i] && mode[i] != PORT_LEARN_NONE) + vsc9953_port_learn_mode_set(i, mode[i]); + } + } +} + +/* Delete all the dynamic FDB entries */ +static void vsc9953_mac_table_flush(int port, int vid) +{ + vsc9953_mac_table_age(port, vid); + vsc9953_mac_table_age(port, vid); +} + +enum egress_vlan_tag { + EGR_TAG_CLASS = 0, + EGR_TAG_PVID, +}; + +/* Set egress tag mode for a VSC9953 port */ +static void vsc9953_port_vlan_egress_tag_set(int port_no, + enum egress_vlan_tag mode) +{ + struct vsc9953_rew_reg *l2rew_reg; + + l2rew_reg = (struct vsc9953_rew_reg *)(VSC9953_OFFSET + + VSC9953_REW_OFFSET); + + switch (mode) { + case EGR_TAG_CLASS: + clrbits_le32(&l2rew_reg->port[port_no].port_tag_cfg, + VSC9953_TAG_VID_PVID); + break; + case EGR_TAG_PVID: + setbits_le32(&l2rew_reg->port[port_no].port_tag_cfg, + VSC9953_TAG_VID_PVID); + break; + default: + printf("Unknown egress VLAN tag mode for port %d\n", port_no); + } +} + +/* Get egress tag mode for a VSC9953 port */ +static void vsc9953_port_vlan_egress_tag_get(int port_no, + enum egress_vlan_tag *mode) +{ + u32 val; + struct vsc9953_rew_reg *l2rew_reg; + + l2rew_reg = (struct vsc9953_rew_reg *)(VSC9953_OFFSET + + VSC9953_REW_OFFSET); + + val = in_le32(&l2rew_reg->port[port_no].port_tag_cfg); + if (val & VSC9953_TAG_VID_PVID) + *mode = EGR_TAG_PVID; + else + *mode = EGR_TAG_CLASS; +} + +/* VSC9953 VLAN learning modes */ +enum vlan_learning_mode { + SHARED_VLAN_LEARNING, + PRIVATE_VLAN_LEARNING, +}; + +/* Set VLAN learning mode for VSC9953 */ +static void vsc9953_vlan_learning_set(enum vlan_learning_mode lrn_mode) +{ + struct vsc9953_analyzer *l2ana_reg; + + l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + + VSC9953_ANA_OFFSET); + + switch (lrn_mode) { + case SHARED_VLAN_LEARNING: + setbits_le32(&l2ana_reg->ana.agen_ctrl, VSC9953_FID_MASK_ALL); + break; + case PRIVATE_VLAN_LEARNING: + clrbits_le32(&l2ana_reg->ana.agen_ctrl, VSC9953_FID_MASK_ALL); + break; + default: + printf("Unknown VLAN learn mode\n"); + } +} + +/* Get VLAN learning mode for VSC9953 */ +static int vsc9953_vlan_learning_get(enum vlan_learning_mode *lrn_mode) +{ + u32 val; + struct vsc9953_analyzer *l2ana_reg; + + l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + + VSC9953_ANA_OFFSET); + + val = in_le32(&l2ana_reg->ana.agen_ctrl); + + if (!(val & VSC9953_FID_MASK_ALL)) { + *lrn_mode = PRIVATE_VLAN_LEARNING; + } else if ((val & VSC9953_FID_MASK_ALL) == VSC9953_FID_MASK_ALL) { + *lrn_mode = SHARED_VLAN_LEARNING; + } else { + printf("Unknown VLAN learning mode\n"); + return -EINVAL; + } + + return 0; +} + +/* Enable/disable VLAN ingress filtering on a VSC9953 port */ +static void vsc9953_port_ingress_filtering_set(int port_no, int enabled) +{ + struct vsc9953_analyzer *l2ana_reg; + + l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + + VSC9953_ANA_OFFSET); + + if (enabled) + setbits_le32(&l2ana_reg->ana.vlan_mask, 1 << port_no); + else + clrbits_le32(&l2ana_reg->ana.vlan_mask, 1 << port_no); +} + +/* Return VLAN ingress filtering on a VSC9953 port */ +static int vsc9953_port_ingress_filtering_get(int port_no) +{ + u32 val; + struct vsc9953_analyzer *l2ana_reg; + + l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + + VSC9953_ANA_OFFSET); + + val = in_le32(&l2ana_reg->ana.vlan_mask); + return !!(val & (1 << port_no)); +} + +static int vsc9953_port_status_key_func(struct ethsw_command_def *parsed_cmd) +{ + int i; + u8 enabled; + + /* Last keyword should tell us if we should enable/disable the port */ + if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] == + ethsw_id_enable) + enabled = 1; + else if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] == + ethsw_id_disable) + enabled = 0; + else + return CMD_RET_USAGE; + + if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) { + if (!VSC9953_PORT_CHECK(parsed_cmd->port)) { + printf("Invalid port number: %d\n", parsed_cmd->port); + return CMD_RET_FAILURE; + } + vsc9953_port_status_set(parsed_cmd->port, enabled); + } else { + for (i = 0; i < VSC9953_MAX_PORTS; i++) + vsc9953_port_status_set(i, enabled); + } + + return CMD_RET_SUCCESS; +} + +static int vsc9953_port_config_key_func(struct ethsw_command_def *parsed_cmd) +{ + int i; + + if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) { + if (!VSC9953_PORT_CHECK(parsed_cmd->port)) { + printf("Invalid port number: %d\n", parsed_cmd->port); + return CMD_RET_FAILURE; + } + vsc9953_phy_autoneg(parsed_cmd->port); + printf("%8s %8s %8s %8s %8s\n", + "Port", "Status", "Link", "Speed", + "Duplex"); + vsc9953_port_config_show(parsed_cmd->port); + + } else { + for (i = 0; i < VSC9953_MAX_PORTS; i++) + vsc9953_phy_autoneg(i); + printf("%8s %8s %8s %8s %8s\n", + "Port", "Status", "Link", "Speed", "Duplex"); + for (i = 0; i < VSC9953_MAX_PORTS; i++) + vsc9953_port_config_show(i); + } + + return CMD_RET_SUCCESS; +} + +static int vsc9953_port_stats_key_func(struct ethsw_command_def *parsed_cmd) +{ + int i; + + if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) { + if (!VSC9953_PORT_CHECK(parsed_cmd->port)) { + printf("Invalid port number: %d\n", parsed_cmd->port); + return CMD_RET_FAILURE; + } + vsc9953_port_statistics_show(parsed_cmd->port); + } else { + for (i = 0; i < VSC9953_MAX_PORTS; i++) + vsc9953_port_statistics_show(i); + } + + return CMD_RET_SUCCESS; +} + +static int vsc9953_port_stats_clear_key_func(struct ethsw_command_def + *parsed_cmd) +{ + int i; + + if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) { + if (!VSC9953_PORT_CHECK(parsed_cmd->port)) { + printf("Invalid port number: %d\n", parsed_cmd->port); + return CMD_RET_FAILURE; + } + vsc9953_port_statistics_clear(parsed_cmd->port); + } else { + for (i = 0; i < VSC9953_MAX_PORTS; i++) + vsc9953_port_statistics_clear(i); + } + + return CMD_RET_SUCCESS; +} + +static int vsc9953_learn_show_key_func(struct ethsw_command_def *parsed_cmd) +{ + int i; + enum port_learn_mode mode; + + if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) { + if (!VSC9953_PORT_CHECK(parsed_cmd->port)) { + printf("Invalid port number: %d\n", parsed_cmd->port); + return CMD_RET_FAILURE; + } + if (vsc9953_port_learn_mode_get(parsed_cmd->port, &mode)) + return CMD_RET_FAILURE; + printf("%7s %11s\n", "Port", "Learn mode"); + switch (mode) { + case PORT_LEARN_NONE: + printf("%7d %11s\n", parsed_cmd->port, "disable"); + break; + case PORT_LEARN_AUTO: + printf("%7d %11s\n", parsed_cmd->port, "auto"); + break; + default: + printf("%7d %11s\n", parsed_cmd->port, "-"); + } + } else { + printf("%7s %11s\n", "Port", "Learn mode"); + for (i = 0; i < VSC9953_MAX_PORTS; i++) { + if (vsc9953_port_learn_mode_get(i, &mode)) + continue; + switch (mode) { + case PORT_LEARN_NONE: + printf("%7d %11s\n", i, "disable"); + break; + case PORT_LEARN_AUTO: + printf("%7d %11s\n", i, "auto"); + break; + default: + printf("%7d %11s\n", i, "-"); + } + } + } + + return CMD_RET_SUCCESS; +} + +static int vsc9953_learn_set_key_func(struct ethsw_command_def *parsed_cmd) +{ + int i; + enum port_learn_mode mode; + + /* Last keyword should tell us the learn mode */ + if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] == + ethsw_id_auto) + mode = PORT_LEARN_AUTO; + else if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] == + ethsw_id_disable) + mode = PORT_LEARN_NONE; + else + return CMD_RET_USAGE; + + if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) { + if (!VSC9953_PORT_CHECK(parsed_cmd->port)) { + printf("Invalid port number: %d\n", parsed_cmd->port); + return CMD_RET_FAILURE; + } + vsc9953_port_learn_mode_set(parsed_cmd->port, mode); + } else { + for (i = 0; i < VSC9953_MAX_PORTS; i++) + vsc9953_port_learn_mode_set(i, mode); + } + + return CMD_RET_SUCCESS; +} + +static int vsc9953_fdb_show_key_func(struct ethsw_command_def *parsed_cmd) +{ + if (parsed_cmd->port != ETHSW_CMD_PORT_ALL && + !VSC9953_PORT_CHECK(parsed_cmd->port)) { + printf("Invalid port number: %d\n", parsed_cmd->port); + return CMD_RET_FAILURE; + } + + if (parsed_cmd->vid != ETHSW_CMD_VLAN_ALL && + !VSC9953_VLAN_CHECK(parsed_cmd->vid)) { + printf("Invalid VID number: %d\n", parsed_cmd->vid); + return CMD_RET_FAILURE; + } + + vsc9953_mac_table_show(parsed_cmd->port, parsed_cmd->vid); + + return CMD_RET_SUCCESS; +} + +static int vsc9953_fdb_flush_key_func(struct ethsw_command_def *parsed_cmd) +{ + if (parsed_cmd->port != ETHSW_CMD_PORT_ALL && + !VSC9953_PORT_CHECK(parsed_cmd->port)) { + printf("Invalid port number: %d\n", parsed_cmd->port); + return CMD_RET_FAILURE; + } + + if (parsed_cmd->vid != ETHSW_CMD_VLAN_ALL && + !VSC9953_VLAN_CHECK(parsed_cmd->vid)) { + printf("Invalid VID number: %d\n", parsed_cmd->vid); + return CMD_RET_FAILURE; + } + + vsc9953_mac_table_flush(parsed_cmd->port, parsed_cmd->vid); + + return CMD_RET_SUCCESS; +} + +static int vsc9953_fdb_entry_add_key_func(struct ethsw_command_def *parsed_cmd) +{ + int vid; + + /* a port number must be present */ + if (parsed_cmd->port == ETHSW_CMD_PORT_ALL) { + printf("Please specify a port\n"); + return CMD_RET_FAILURE; + } + + if (!VSC9953_PORT_CHECK(parsed_cmd->port)) { + printf("Invalid port number: %d\n", parsed_cmd->port); + return CMD_RET_FAILURE; + } + + /* Use VLAN 1 if VID is not set */ + vid = (parsed_cmd->vid == ETHSW_CMD_VLAN_ALL ? 1 : parsed_cmd->vid); + + if (!VSC9953_VLAN_CHECK(vid)) { + printf("Invalid VID number: %d\n", vid); + return CMD_RET_FAILURE; + } + + if (vsc9953_mac_table_add(parsed_cmd->port, parsed_cmd->ethaddr, vid)) + return CMD_RET_FAILURE; + + return CMD_RET_SUCCESS; +} + +static int vsc9953_fdb_entry_del_key_func(struct ethsw_command_def *parsed_cmd) +{ + int vid; + + /* Use VLAN 1 if VID is not set */ + vid = (parsed_cmd->vid == ETHSW_CMD_VLAN_ALL ? 1 : parsed_cmd->vid); + + if (!VSC9953_VLAN_CHECK(vid)) { + printf("Invalid VID number: %d\n", vid); + return CMD_RET_FAILURE; + } + + if (vsc9953_mac_table_del(parsed_cmd->ethaddr, vid)) + return CMD_RET_FAILURE; + + return CMD_RET_SUCCESS; +} + +static int vsc9953_pvid_show_key_func(struct ethsw_command_def *parsed_cmd) +{ + int i; + int pvid; + + if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) { + if (!VSC9953_PORT_CHECK(parsed_cmd->port)) { + printf("Invalid port number: %d\n", parsed_cmd->port); + return CMD_RET_FAILURE; + } + + if (vsc9953_port_vlan_pvid_get(parsed_cmd->port, &pvid)) + return CMD_RET_FAILURE; + printf("%7s %7s\n", "Port", "PVID"); + printf("%7d %7d\n", parsed_cmd->port, pvid); + } else { + printf("%7s %7s\n", "Port", "PVID"); + for (i = 0; i < VSC9953_MAX_PORTS; i++) { + if (vsc9953_port_vlan_pvid_get(i, &pvid)) + continue; + printf("%7d %7d\n", i, pvid); + } + } + + return CMD_RET_SUCCESS; +} + +static int vsc9953_pvid_set_key_func(struct ethsw_command_def *parsed_cmd) +{ + /* PVID number should be set in parsed_cmd->vid */ + if (parsed_cmd->vid == ETHSW_CMD_VLAN_ALL) { + printf("Please set a pvid value\n"); + return CMD_RET_FAILURE; + } + + if (!VSC9953_VLAN_CHECK(parsed_cmd->vid)) { + printf("Invalid VID number: %d\n", parsed_cmd->vid); + return CMD_RET_FAILURE; + } + + if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) { + if (!VSC9953_PORT_CHECK(parsed_cmd->port)) { + printf("Invalid port number: %d\n", parsed_cmd->port); + return CMD_RET_FAILURE; + } + vsc9953_port_vlan_pvid_set(parsed_cmd->port, parsed_cmd->vid); + } else { + vsc9953_port_all_vlan_pvid_set(parsed_cmd->vid); + } + + return CMD_RET_SUCCESS; +} + +static int vsc9953_vlan_show_key_func(struct ethsw_command_def *parsed_cmd) +{ + int i; + + if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) { + if (!VSC9953_PORT_CHECK(parsed_cmd->port)) { + printf("Invalid port number: %d\n", parsed_cmd->port); + return CMD_RET_FAILURE; + } + vsc9953_vlan_membership_show(parsed_cmd->port); + } else { + for (i = 0; i < VSC9953_MAX_PORTS; i++) + vsc9953_vlan_membership_show(i); + } + + return CMD_RET_SUCCESS; +} + +static int vsc9953_vlan_set_key_func(struct ethsw_command_def *parsed_cmd) +{ + int i; + int add; + + /* VLAN should be set in parsed_cmd->vid */ + if (parsed_cmd->vid == ETHSW_CMD_VLAN_ALL) { + printf("Please set a vlan value\n"); + return CMD_RET_FAILURE; + } + + if (!VSC9953_VLAN_CHECK(parsed_cmd->vid)) { + printf("Invalid VID number: %d\n", parsed_cmd->vid); + return CMD_RET_FAILURE; + } + + /* keywords add/delete should be the last but one in array */ + if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 2] == + ethsw_id_add) + add = 1; + else if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 2] == + ethsw_id_del) + add = 0; + else + return CMD_RET_USAGE; + + if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) { + if (!VSC9953_PORT_CHECK(parsed_cmd->port)) { + printf("Invalid port number: %d\n", parsed_cmd->port); + return CMD_RET_FAILURE; + } + vsc9953_vlan_table_membership_set(parsed_cmd->vid, + parsed_cmd->port, add); + } else { + for (i = 0; i < VSC9953_MAX_PORTS; i++) + vsc9953_vlan_table_membership_set(parsed_cmd->vid, i, + add); + } + + return CMD_RET_SUCCESS; +} +static int vsc9953_port_untag_show_key_func( + struct ethsw_command_def *parsed_cmd) +{ + int i; + + printf("%7s\t%17s\n", "Port", "Untag"); + if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) { + if (!VSC9953_PORT_CHECK(parsed_cmd->port)) { + printf("Invalid port number: %d\n", parsed_cmd->port); + return CMD_RET_FAILURE; + } + vsc9953_port_vlan_egr_untag_show(parsed_cmd->port); + } else { + for (i = 0; i < VSC9953_MAX_PORTS; i++) + vsc9953_port_vlan_egr_untag_show(i); + } + + return CMD_RET_SUCCESS; +} + +static int vsc9953_port_untag_set_key_func(struct ethsw_command_def *parsed_cmd) +{ + int i; + enum egress_untag_mode mode; + + /* keywords for the untagged mode are the last in the array */ + if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] == + ethsw_id_all) + mode = EGRESS_UNTAG_ALL; + else if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] == + ethsw_id_none) + mode = EGRESS_UNTAG_NONE; + else if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] == + ethsw_id_pvid) + mode = EGRESS_UNTAG_PVID_AND_ZERO; + else + return CMD_RET_USAGE; + + if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) { + if (!VSC9953_PORT_CHECK(parsed_cmd->port)) { + printf("Invalid port number: %d\n", parsed_cmd->port); + return CMD_RET_FAILURE; + } + vsc9953_port_vlan_egr_untag_set(parsed_cmd->port, mode); + } else { + for (i = 0; i < VSC9953_MAX_PORTS; i++) + vsc9953_port_vlan_egr_untag_set(i, mode); + } + + return CMD_RET_SUCCESS; +} + +static int vsc9953_egr_vlan_tag_show_key_func( + struct ethsw_command_def *parsed_cmd) +{ + int i; + enum egress_vlan_tag mode; + + if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) { + if (!VSC9953_PORT_CHECK(parsed_cmd->port)) { + printf("Invalid port number: %d\n", parsed_cmd->port); + return CMD_RET_FAILURE; + } + vsc9953_port_vlan_egress_tag_get(parsed_cmd->port, &mode); + printf("%7s\t%12s\n", "Port", "Egress VID"); + printf("%7d\t", parsed_cmd->port); + switch (mode) { + case EGR_TAG_CLASS: + printf("%12s\n", "classified"); + break; + case EGR_TAG_PVID: + printf("%12s\n", "pvid"); + break; + default: + printf("%12s\n", "-"); + } + } else { + printf("%7s\t%12s\n", "Port", "Egress VID"); + for (i = 0; i < VSC9953_MAX_PORTS; i++) { + vsc9953_port_vlan_egress_tag_get(i, &mode); + switch (mode) { + case EGR_TAG_CLASS: + printf("%7d\t%12s\n", i, "classified"); + break; + case EGR_TAG_PVID: + printf("%7d\t%12s\n", i, "pvid"); + break; + default: + printf("%7d\t%12s\n", i, "-"); + } + } + } + + return CMD_RET_SUCCESS; +} + +static int vsc9953_egr_vlan_tag_set_key_func( + struct ethsw_command_def *parsed_cmd) +{ + int i; + enum egress_vlan_tag mode; + + /* keywords for the egress vlan tag mode are the last in the array */ + if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] == + ethsw_id_pvid) + mode = EGR_TAG_PVID; + else if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] == + ethsw_id_classified) + mode = EGR_TAG_CLASS; + else + return CMD_RET_USAGE; + + if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) { + if (!VSC9953_PORT_CHECK(parsed_cmd->port)) { + printf("Invalid port number: %d\n", parsed_cmd->port); + return CMD_RET_FAILURE; + } + vsc9953_port_vlan_egress_tag_set(parsed_cmd->port, mode); + } else { + for (i = 0; i < VSC9953_MAX_PORTS; i++) + vsc9953_port_vlan_egress_tag_set(i, mode); + } + + return CMD_RET_SUCCESS; +} + +static int vsc9953_vlan_learn_show_key_func( + struct ethsw_command_def *parsed_cmd) +{ + int rc; + enum vlan_learning_mode mode; + + rc = vsc9953_vlan_learning_get(&mode); + if (rc) + return CMD_RET_FAILURE; + + switch (mode) { + case SHARED_VLAN_LEARNING: + printf("VLAN learning mode: shared\n"); + break; + case PRIVATE_VLAN_LEARNING: + printf("VLAN learning mode: private\n"); + break; + default: + printf("Unknown VLAN learning mode\n"); + rc = CMD_RET_FAILURE; + } + + return CMD_RET_SUCCESS; +} + +static int vsc9953_vlan_learn_set_key_func(struct ethsw_command_def *parsed_cmd) +{ + enum vlan_learning_mode mode; + + /* keywords for shared/private are the last in the array */ + if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] == + ethsw_id_shared) + mode = SHARED_VLAN_LEARNING; + else if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] == + ethsw_id_private) + mode = PRIVATE_VLAN_LEARNING; + else + return CMD_RET_USAGE; + + vsc9953_vlan_learning_set(mode); + + return CMD_RET_SUCCESS; +} + +static int vsc9953_ingr_fltr_show_key_func(struct ethsw_command_def *parsed_cmd) +{ + int i; + int enabled; + + printf("%7s\t%18s\n", "Port", "Ingress filtering"); + if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) { + if (!VSC9953_PORT_CHECK(parsed_cmd->port)) { + printf("Invalid port number: %d\n", parsed_cmd->port); + return CMD_RET_FAILURE; + } + enabled = vsc9953_port_ingress_filtering_get(parsed_cmd->port); + printf("%7d\t%18s\n", parsed_cmd->port, enabled ? "enable" : + "disable"); + } else { + for (i = 0; i < VSC9953_MAX_PORTS; i++) { + enabled = vsc9953_port_ingress_filtering_get(i); + printf("%7d\t%18s\n", parsed_cmd->port, enabled ? + "enable" : + "disable"); + } + } + + return CMD_RET_SUCCESS; +} + +static int vsc9953_ingr_fltr_set_key_func(struct ethsw_command_def *parsed_cmd) +{ + int i; + int enable; + + /* keywords for enabling/disabling ingress filtering + * are the last in the array + */ + if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] == + ethsw_id_enable) + enable = 1; + else if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] == + ethsw_id_disable) + enable = 0; + else + return CMD_RET_USAGE; + + if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) { + if (!VSC9953_PORT_CHECK(parsed_cmd->port)) { + printf("Invalid port number: %d\n", parsed_cmd->port); + return CMD_RET_FAILURE; + } + vsc9953_port_ingress_filtering_set(parsed_cmd->port, enable); + } else { + for (i = 0; i < VSC9953_MAX_PORTS; i++) + vsc9953_port_ingress_filtering_set(i, enable); + } + + return CMD_RET_SUCCESS; +} + +static struct ethsw_command_func vsc9953_cmd_func = { + .ethsw_name = "L2 Switch VSC9953", + .port_enable = &vsc9953_port_status_key_func, + .port_disable = &vsc9953_port_status_key_func, + .port_show = &vsc9953_port_config_key_func, + .port_stats = &vsc9953_port_stats_key_func, + .port_stats_clear = &vsc9953_port_stats_clear_key_func, + .port_learn = &vsc9953_learn_set_key_func, + .port_learn_show = &vsc9953_learn_show_key_func, + .fdb_show = &vsc9953_fdb_show_key_func, + .fdb_flush = &vsc9953_fdb_flush_key_func, + .fdb_entry_add = &vsc9953_fdb_entry_add_key_func, + .fdb_entry_del = &vsc9953_fdb_entry_del_key_func, + .pvid_show = &vsc9953_pvid_show_key_func, + .pvid_set = &vsc9953_pvid_set_key_func, + .vlan_show = &vsc9953_vlan_show_key_func, + .vlan_set = &vsc9953_vlan_set_key_func, + .port_untag_show = &vsc9953_port_untag_show_key_func, + .port_untag_set = &vsc9953_port_untag_set_key_func, + .port_egr_vlan_show = &vsc9953_egr_vlan_tag_show_key_func, + .port_egr_vlan_set = &vsc9953_egr_vlan_tag_set_key_func, + .vlan_learn_show = &vsc9953_vlan_learn_show_key_func, + .vlan_learn_set = &vsc9953_vlan_learn_set_key_func, + .port_ingr_filt_show = &vsc9953_ingr_fltr_show_key_func, + .port_ingr_filt_set = &vsc9953_ingr_fltr_set_key_func +}; + +#endif /* CONFIG_CMD_ETHSW */ + +/***************************************************************************** +At startup, the default configuration would be: + - HW learning enabled on all ports; (HW default) + - All ports are in VLAN 1; + - All ports are VLAN aware; + - All ports have POP_COUNT 1; + - All ports have PVID 1; + - All ports have TPID 0x8100; (HW default) + - All ports tag frames classified to all VLANs that are not PVID; +*****************************************************************************/ +void vsc9953_default_configuration(void) +{ + int i; + + for (i = 0; i < VSC9953_MAX_VLAN; i++) + vsc9953_vlan_table_membership_all_set(i, 0); + vsc9953_port_all_vlan_aware_set(1); + vsc9953_port_all_vlan_pvid_set(1); + vsc9953_port_all_vlan_poncnt_set(1); + vsc9953_vlan_table_membership_all_set(1, 1); + vsc9953_vlan_ingr_fltr_learn_drop(1); + vsc9953_port_all_vlan_egress_untagged_set(EGRESS_UNTAG_PVID_AND_ZERO); +} + +void vsc9953_init(bd_t *bis) +{ + u32 i; + u32 hdx_cfg = 0; + u32 phy_addr = 0; + int timeout; + struct vsc9953_system_reg *l2sys_reg; + struct vsc9953_qsys_reg *l2qsys_reg; + struct vsc9953_dev_gmii *l2dev_gmii_reg; + struct vsc9953_analyzer *l2ana_reg; + struct vsc9953_devcpu_gcb *l2dev_gcb; + + l2dev_gmii_reg = (struct vsc9953_dev_gmii *)(VSC9953_OFFSET + + VSC9953_DEV_GMII_OFFSET); + + l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + + VSC9953_ANA_OFFSET); + + l2sys_reg = (struct vsc9953_system_reg *)(VSC9953_OFFSET + + VSC9953_SYS_OFFSET); + + l2qsys_reg = (struct vsc9953_qsys_reg *)(VSC9953_OFFSET + + VSC9953_QSYS_OFFSET); + + l2dev_gcb = (struct vsc9953_devcpu_gcb *)(VSC9953_OFFSET + + VSC9953_DEVCPU_GCB); + + out_le32(&l2dev_gcb->chip_regs.soft_rst, + VSC9953_SOFT_SWC_RST_ENA); + timeout = 50000; + while ((in_le32(&l2dev_gcb->chip_regs.soft_rst) & + VSC9953_SOFT_SWC_RST_ENA) && --timeout) + udelay(1); /* busy wait for vsc9953 soft reset */ + if (timeout == 0) + debug("Timeout waiting for VSC9953 to reset\n"); + + out_le32(&l2sys_reg->sys.reset_cfg, VSC9953_MEM_ENABLE | + VSC9953_MEM_INIT); + + timeout = 50000; + while ((in_le32(&l2sys_reg->sys.reset_cfg) & + VSC9953_MEM_INIT) && --timeout) + udelay(1); /* busy wait for vsc9953 memory init */ + if (timeout == 0) + debug("Timeout waiting for VSC9953 memory to initialize\n"); + + out_le32(&l2sys_reg->sys.reset_cfg, (in_le32(&l2sys_reg->sys.reset_cfg) + | VSC9953_CORE_ENABLE)); + + /* VSC9953 Setting to be done once only */ + out_le32(&l2qsys_reg->sys.ext_cpu_cfg, 0x00000b00); + + for (i = 0; i < VSC9953_MAX_PORTS; i++) { + if (vsc9953_port_init(i)) + printf("Failed to initialize l2switch port %d\n", i); + + /* Enable VSC9953 GMII Ports Port ID 0 - 7 */ + if (VSC9953_INTERNAL_PORT_CHECK(i)) { + out_le32(&l2ana_reg->pfc[i].pfc_cfg, + VSC9953_PFC_FC_QSGMII); + out_le32(&l2sys_reg->pause_cfg.mac_fc_cfg[i], + VSC9953_MAC_FC_CFG_QSGMII); + } else { + out_le32(&l2ana_reg->pfc[i].pfc_cfg, + VSC9953_PFC_FC); + out_le32(&l2sys_reg->pause_cfg.mac_fc_cfg[i], + VSC9953_MAC_FC_CFG); + } + out_le32(&l2dev_gmii_reg->port_mode.clock_cfg, + VSC9953_CLOCK_CFG); + out_le32(&l2dev_gmii_reg->mac_cfg_status.mac_ena_cfg, + VSC9953_MAC_ENA_CFG); + out_le32(&l2dev_gmii_reg->mac_cfg_status.mac_mode_cfg, + VSC9953_MAC_MODE_CFG); + out_le32(&l2dev_gmii_reg->mac_cfg_status.mac_ifg_cfg, + VSC9953_MAC_IFG_CFG); + /* mac_hdx_cfg varies with port id*/ + hdx_cfg = VSC9953_MAC_HDX_CFG | (i << 16); + out_le32(&l2dev_gmii_reg->mac_cfg_status.mac_hdx_cfg, hdx_cfg); + out_le32(&l2sys_reg->sys.front_port_mode[i], + VSC9953_FRONT_PORT_MODE); + setbits_le32(&l2qsys_reg->sys.switch_port_mode[i], + VSC9953_PORT_ENA); + out_le32(&l2dev_gmii_reg->mac_cfg_status.mac_maxlen_cfg, + VSC9953_MAC_MAX_LEN); + out_le32(&l2sys_reg->pause_cfg.pause_cfg[i], + VSC9953_PAUSE_CFG); + /* WAIT FOR 2 us*/ + udelay(2); + + l2dev_gmii_reg = (struct vsc9953_dev_gmii *)( + (char *)l2dev_gmii_reg + + T1040_SWITCH_GMII_DEV_OFFSET); + + /* Initialize Lynx PHY Wrappers */ + phy_addr = 0; + if (vsc9953_l2sw.port[i].enet_if == + PHY_INTERFACE_MODE_QSGMII) + phy_addr = (i + 0x4) & 0x1F; + else if (vsc9953_l2sw.port[i].enet_if == + PHY_INTERFACE_MODE_SGMII) + phy_addr = (i + 1) & 0x1F; + + if (phy_addr) { + /* SGMII IF mode + AN enable */ + vsc9953_mdio_write(&l2dev_gcb->mii_mng[0], phy_addr, + 0x14, PHY_SGMII_IF_MODE_AN | + PHY_SGMII_IF_MODE_SGMII); + /* Dev ability according to SGMII specification */ + vsc9953_mdio_write(&l2dev_gcb->mii_mng[0], phy_addr, + 0x4, PHY_SGMII_DEV_ABILITY_SGMII); + /* Adjust link timer for SGMII + * 1.6 ms in units of 8 ns = 2 * 10^5 = 0x30d40 + */ + vsc9953_mdio_write(&l2dev_gcb->mii_mng[0], phy_addr, + 0x13, 0x0003); + vsc9953_mdio_write(&l2dev_gcb->mii_mng[0], phy_addr, + 0x12, 0x0d40); + /* Restart AN */ + vsc9953_mdio_write(&l2dev_gcb->mii_mng[0], phy_addr, + 0x0, PHY_SGMII_CR_DEF_VAL | + PHY_SGMII_CR_RESET_AN); + + timeout = 50000; + while ((vsc9953_mdio_read(&l2dev_gcb->mii_mng[0], + phy_addr, 0x01) & 0x0020) && --timeout) + udelay(1); /* wait for AN to complete */ + if (timeout == 0) + debug("Timeout waiting for AN to complete\n"); + } + } + + vsc9953_default_configuration(); + +#ifdef CONFIG_CMD_ETHSW + if (ethsw_define_functions(&vsc9953_cmd_func) < 0) + debug("Unable to use \"ethsw\" commands\n"); +#endif + + printf("VSC9953 L2 switch initialized\n"); + return; +} diff --git a/sources/uboot-be550/drivers/net/xilinx_axi_emac.c b/sources/uboot-be550/drivers/net/xilinx_axi_emac.c new file mode 100644 index 00000000..df053fee --- /dev/null +++ b/sources/uboot-be550/drivers/net/xilinx_axi_emac.c @@ -0,0 +1,656 @@ +/* + * Copyright (C) 2011 Michal Simek + * Copyright (C) 2011 PetaLogix + * Copyright (C) 2010 Xilinx, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +#if !defined(CONFIG_PHYLIB) +# error AXI_ETHERNET requires PHYLIB +#endif + +/* Link setup */ +#define XAE_EMMC_LINKSPEED_MASK 0xC0000000 /* Link speed */ +#define XAE_EMMC_LINKSPD_10 0x00000000 /* Link Speed mask for 10 Mbit */ +#define XAE_EMMC_LINKSPD_100 0x40000000 /* Link Speed mask for 100 Mbit */ +#define XAE_EMMC_LINKSPD_1000 0x80000000 /* Link Speed mask for 1000 Mbit */ + +/* Interrupt Status/Enable/Mask Registers bit definitions */ +#define XAE_INT_RXRJECT_MASK 0x00000008 /* Rx frame rejected */ +#define XAE_INT_MGTRDY_MASK 0x00000080 /* MGT clock Lock */ + +/* Receive Configuration Word 1 (RCW1) Register bit definitions */ +#define XAE_RCW1_RX_MASK 0x10000000 /* Receiver enable */ + +/* Transmitter Configuration (TC) Register bit definitions */ +#define XAE_TC_TX_MASK 0x10000000 /* Transmitter enable */ + +#define XAE_UAW1_UNICASTADDR_MASK 0x0000FFFF + +/* MDIO Management Configuration (MC) Register bit definitions */ +#define XAE_MDIO_MC_MDIOEN_MASK 0x00000040 /* MII management enable*/ + +/* MDIO Management Control Register (MCR) Register bit definitions */ +#define XAE_MDIO_MCR_PHYAD_MASK 0x1F000000 /* Phy Address Mask */ +#define XAE_MDIO_MCR_PHYAD_SHIFT 24 /* Phy Address Shift */ +#define XAE_MDIO_MCR_REGAD_MASK 0x001F0000 /* Reg Address Mask */ +#define XAE_MDIO_MCR_REGAD_SHIFT 16 /* Reg Address Shift */ +#define XAE_MDIO_MCR_OP_READ_MASK 0x00008000 /* Op Code Read Mask */ +#define XAE_MDIO_MCR_OP_WRITE_MASK 0x00004000 /* Op Code Write Mask */ +#define XAE_MDIO_MCR_INITIATE_MASK 0x00000800 /* Ready Mask */ +#define XAE_MDIO_MCR_READY_MASK 0x00000080 /* Ready Mask */ + +#define XAE_MDIO_DIV_DFT 29 /* Default MDIO clock divisor */ + +/* DMA macros */ +/* Bitmasks of XAXIDMA_CR_OFFSET register */ +#define XAXIDMA_CR_RUNSTOP_MASK 0x00000001 /* Start/stop DMA channel */ +#define XAXIDMA_CR_RESET_MASK 0x00000004 /* Reset DMA engine */ + +/* Bitmasks of XAXIDMA_SR_OFFSET register */ +#define XAXIDMA_HALTED_MASK 0x00000001 /* DMA channel halted */ + +/* Bitmask for interrupts */ +#define XAXIDMA_IRQ_IOC_MASK 0x00001000 /* Completion intr */ +#define XAXIDMA_IRQ_DELAY_MASK 0x00002000 /* Delay interrupt */ +#define XAXIDMA_IRQ_ALL_MASK 0x00007000 /* All interrupts */ + +/* Bitmasks of XAXIDMA_BD_CTRL_OFFSET register */ +#define XAXIDMA_BD_CTRL_TXSOF_MASK 0x08000000 /* First tx packet */ +#define XAXIDMA_BD_CTRL_TXEOF_MASK 0x04000000 /* Last tx packet */ + +#define DMAALIGN 128 + +static u8 rxframe[PKTSIZE_ALIGN] __attribute((aligned(DMAALIGN))); + +/* Reflect dma offsets */ +struct axidma_reg { + u32 control; /* DMACR */ + u32 status; /* DMASR */ + u32 current; /* CURDESC */ + u32 reserved; + u32 tail; /* TAILDESC */ +}; + +/* Private driver structures */ +struct axidma_priv { + struct axidma_reg *dmatx; + struct axidma_reg *dmarx; + int phyaddr; + + struct phy_device *phydev; + struct mii_dev *bus; +}; + +/* BD descriptors */ +struct axidma_bd { + u32 next; /* Next descriptor pointer */ + u32 reserved1; + u32 phys; /* Buffer address */ + u32 reserved2; + u32 reserved3; + u32 reserved4; + u32 cntrl; /* Control */ + u32 status; /* Status */ + u32 app0; + u32 app1; /* TX start << 16 | insert */ + u32 app2; /* TX csum seed */ + u32 app3; + u32 app4; + u32 sw_id_offset; + u32 reserved5; + u32 reserved6; +}; + +/* Static BDs - driver uses only one BD */ +static struct axidma_bd tx_bd __attribute((aligned(DMAALIGN))); +static struct axidma_bd rx_bd __attribute((aligned(DMAALIGN))); + +struct axi_regs { + u32 reserved[3]; + u32 is; /* 0xC: Interrupt status */ + u32 reserved2; + u32 ie; /* 0x14: Interrupt enable */ + u32 reserved3[251]; + u32 rcw1; /* 0x404: Rx Configuration Word 1 */ + u32 tc; /* 0x408: Tx Configuration */ + u32 reserved4; + u32 emmc; /* 0x410: EMAC mode configuration */ + u32 reserved5[59]; + u32 mdio_mc; /* 0x500: MII Management Config */ + u32 mdio_mcr; /* 0x504: MII Management Control */ + u32 mdio_mwd; /* 0x508: MII Management Write Data */ + u32 mdio_mrd; /* 0x50C: MII Management Read Data */ + u32 reserved6[124]; + u32 uaw0; /* 0x700: Unicast address word 0 */ + u32 uaw1; /* 0x704: Unicast address word 1 */ +}; + +/* Use MII register 1 (MII status register) to detect PHY */ +#define PHY_DETECT_REG 1 + +/* + * Mask used to verify certain PHY features (or register contents) + * in the register above: + * 0x1000: 10Mbps full duplex support + * 0x0800: 10Mbps half duplex support + * 0x0008: Auto-negotiation support + */ +#define PHY_DETECT_MASK 0x1808 + +static inline int mdio_wait(struct eth_device *dev) +{ + struct axi_regs *regs = (struct axi_regs *)dev->iobase; + u32 timeout = 200; + + /* Wait till MDIO interface is ready to accept a new transaction. */ + while (timeout && (!(in_be32(®s->mdio_mcr) + & XAE_MDIO_MCR_READY_MASK))) { + timeout--; + udelay(1); + } + if (!timeout) { + printf("%s: Timeout\n", __func__); + return 1; + } + return 0; +} + +static u32 phyread(struct eth_device *dev, u32 phyaddress, u32 registernum, + u16 *val) +{ + struct axi_regs *regs = (struct axi_regs *)dev->iobase; + u32 mdioctrlreg = 0; + + if (mdio_wait(dev)) + return 1; + + mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) & + XAE_MDIO_MCR_PHYAD_MASK) | + ((registernum << XAE_MDIO_MCR_REGAD_SHIFT) + & XAE_MDIO_MCR_REGAD_MASK) | + XAE_MDIO_MCR_INITIATE_MASK | + XAE_MDIO_MCR_OP_READ_MASK; + + out_be32(®s->mdio_mcr, mdioctrlreg); + + if (mdio_wait(dev)) + return 1; + + /* Read data */ + *val = in_be32(®s->mdio_mrd); + return 0; +} + +static u32 phywrite(struct eth_device *dev, u32 phyaddress, u32 registernum, + u32 data) +{ + struct axi_regs *regs = (struct axi_regs *)dev->iobase; + u32 mdioctrlreg = 0; + + if (mdio_wait(dev)) + return 1; + + mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) & + XAE_MDIO_MCR_PHYAD_MASK) | + ((registernum << XAE_MDIO_MCR_REGAD_SHIFT) + & XAE_MDIO_MCR_REGAD_MASK) | + XAE_MDIO_MCR_INITIATE_MASK | + XAE_MDIO_MCR_OP_WRITE_MASK; + + /* Write data */ + out_be32(®s->mdio_mwd, data); + + out_be32(®s->mdio_mcr, mdioctrlreg); + + if (mdio_wait(dev)) + return 1; + + return 0; +} + +/* Setting axi emac and phy to proper setting */ +static int setup_phy(struct eth_device *dev) +{ + u16 phyreg; + u32 i, speed, emmc_reg, ret; + struct axidma_priv *priv = dev->priv; + struct axi_regs *regs = (struct axi_regs *)dev->iobase; + struct phy_device *phydev; + + u32 supported = SUPPORTED_10baseT_Half | + SUPPORTED_10baseT_Full | + SUPPORTED_100baseT_Half | + SUPPORTED_100baseT_Full | + SUPPORTED_1000baseT_Half | + SUPPORTED_1000baseT_Full; + + if (priv->phyaddr == -1) { + /* Detect the PHY address */ + for (i = 31; i >= 0; i--) { + ret = phyread(dev, i, PHY_DETECT_REG, &phyreg); + if (!ret && (phyreg != 0xFFFF) && + ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { + /* Found a valid PHY address */ + priv->phyaddr = i; + debug("axiemac: Found valid phy address, %x\n", + phyreg); + break; + } + } + } + + /* Interface - look at tsec */ + phydev = phy_connect(priv->bus, priv->phyaddr, dev, 0); + + phydev->supported &= supported; + phydev->advertising = phydev->supported; + priv->phydev = phydev; + phy_config(phydev); + if (phy_startup(phydev)) { + printf("axiemac: could not initialize PHY %s\n", + phydev->dev->name); + return 0; + } + if (!phydev->link) { + printf("%s: No link.\n", phydev->dev->name); + return 0; + } + + switch (phydev->speed) { + case 1000: + speed = XAE_EMMC_LINKSPD_1000; + break; + case 100: + speed = XAE_EMMC_LINKSPD_100; + break; + case 10: + speed = XAE_EMMC_LINKSPD_10; + break; + default: + return 0; + } + + /* Setup the emac for the phy speed */ + emmc_reg = in_be32(®s->emmc); + emmc_reg &= ~XAE_EMMC_LINKSPEED_MASK; + emmc_reg |= speed; + + /* Write new speed setting out to Axi Ethernet */ + out_be32(®s->emmc, emmc_reg); + + /* + * Setting the operating speed of the MAC needs a delay. There + * doesn't seem to be register to poll, so please consider this + * during your application design. + */ + udelay(1); + + return 1; +} + +/* STOP DMA transfers */ +static void axiemac_halt(struct eth_device *dev) +{ + struct axidma_priv *priv = dev->priv; + u32 temp; + + /* Stop the hardware */ + temp = in_be32(&priv->dmatx->control); + temp &= ~XAXIDMA_CR_RUNSTOP_MASK; + out_be32(&priv->dmatx->control, temp); + + temp = in_be32(&priv->dmarx->control); + temp &= ~XAXIDMA_CR_RUNSTOP_MASK; + out_be32(&priv->dmarx->control, temp); + + debug("axiemac: Halted\n"); +} + +static int axi_ethernet_init(struct eth_device *dev) +{ + struct axi_regs *regs = (struct axi_regs *)dev->iobase; + u32 timeout = 200; + + /* + * Check the status of the MgtRdy bit in the interrupt status + * registers. This must be done to allow the MGT clock to become stable + * for the Sgmii and 1000BaseX PHY interfaces. No other register reads + * will be valid until this bit is valid. + * The bit is always a 1 for all other PHY interfaces. + */ + while (timeout && (!(in_be32(®s->is) & XAE_INT_MGTRDY_MASK))) { + timeout--; + udelay(1); + } + if (!timeout) { + printf("%s: Timeout\n", __func__); + return 1; + } + + /* Stop the device and reset HW */ + /* Disable interrupts */ + out_be32(®s->ie, 0); + + /* Disable the receiver */ + out_be32(®s->rcw1, in_be32(®s->rcw1) & ~XAE_RCW1_RX_MASK); + + /* + * Stopping the receiver in mid-packet causes a dropped packet + * indication from HW. Clear it. + */ + /* Set the interrupt status register to clear the interrupt */ + out_be32(®s->is, XAE_INT_RXRJECT_MASK); + + /* Setup HW */ + /* Set default MDIO divisor */ + out_be32(®s->mdio_mc, XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK); + + debug("axiemac: InitHw done\n"); + return 0; +} + +static int axiemac_setup_mac(struct eth_device *dev) +{ + struct axi_regs *regs = (struct axi_regs *)dev->iobase; + + /* Set the MAC address */ + int val = ((dev->enetaddr[3] << 24) | (dev->enetaddr[2] << 16) | + (dev->enetaddr[1] << 8) | (dev->enetaddr[0])); + out_be32(®s->uaw0, val); + + val = (dev->enetaddr[5] << 8) | dev->enetaddr[4] ; + val |= in_be32(®s->uaw1) & ~XAE_UAW1_UNICASTADDR_MASK; + out_be32(®s->uaw1, val); + return 0; +} + +/* Reset DMA engine */ +static void axi_dma_init(struct eth_device *dev) +{ + struct axidma_priv *priv = dev->priv; + u32 timeout = 500; + + /* Reset the engine so the hardware starts from a known state */ + out_be32(&priv->dmatx->control, XAXIDMA_CR_RESET_MASK); + out_be32(&priv->dmarx->control, XAXIDMA_CR_RESET_MASK); + + /* At the initialization time, hardware should finish reset quickly */ + while (timeout--) { + /* Check transmit/receive channel */ + /* Reset is done when the reset bit is low */ + if (!(in_be32(&priv->dmatx->control) | + in_be32(&priv->dmarx->control)) + & XAXIDMA_CR_RESET_MASK) { + break; + } + } + if (!timeout) + printf("%s: Timeout\n", __func__); +} + +static int axiemac_init(struct eth_device *dev, bd_t * bis) +{ + struct axidma_priv *priv = dev->priv; + struct axi_regs *regs = (struct axi_regs *)dev->iobase; + u32 temp; + + debug("axiemac: Init started\n"); + /* + * Initialize AXIDMA engine. AXIDMA engine must be initialized before + * AxiEthernet. During AXIDMA engine initialization, AXIDMA hardware is + * reset, and since AXIDMA reset line is connected to AxiEthernet, this + * would ensure a reset of AxiEthernet. + */ + axi_dma_init(dev); + + /* Initialize AxiEthernet hardware. */ + if (axi_ethernet_init(dev)) + return -1; + + /* Disable all RX interrupts before RxBD space setup */ + temp = in_be32(&priv->dmarx->control); + temp &= ~XAXIDMA_IRQ_ALL_MASK; + out_be32(&priv->dmarx->control, temp); + + /* Start DMA RX channel. Now it's ready to receive data.*/ + out_be32(&priv->dmarx->current, (u32)&rx_bd); + + /* Setup the BD. */ + memset(&rx_bd, 0, sizeof(rx_bd)); + rx_bd.next = (u32)&rx_bd; + rx_bd.phys = (u32)&rxframe; + rx_bd.cntrl = sizeof(rxframe); + /* Flush the last BD so DMA core could see the updates */ + flush_cache((u32)&rx_bd, sizeof(rx_bd)); + + /* It is necessary to flush rxframe because if you don't do it + * then cache can contain uninitialized data */ + flush_cache((u32)&rxframe, sizeof(rxframe)); + + /* Start the hardware */ + temp = in_be32(&priv->dmarx->control); + temp |= XAXIDMA_CR_RUNSTOP_MASK; + out_be32(&priv->dmarx->control, temp); + + /* Rx BD is ready - start */ + out_be32(&priv->dmarx->tail, (u32)&rx_bd); + + /* Enable TX */ + out_be32(®s->tc, XAE_TC_TX_MASK); + /* Enable RX */ + out_be32(®s->rcw1, XAE_RCW1_RX_MASK); + + /* PHY setup */ + if (!setup_phy(dev)) { + axiemac_halt(dev); + return -1; + } + + debug("axiemac: Init complete\n"); + return 0; +} + +static int axiemac_send(struct eth_device *dev, void *ptr, int len) +{ + struct axidma_priv *priv = dev->priv; + u32 timeout; + + if (len > PKTSIZE_ALIGN) + len = PKTSIZE_ALIGN; + + /* Flush packet to main memory to be trasfered by DMA */ + flush_cache((u32)ptr, len); + + /* Setup Tx BD */ + memset(&tx_bd, 0, sizeof(tx_bd)); + /* At the end of the ring, link the last BD back to the top */ + tx_bd.next = (u32)&tx_bd; + tx_bd.phys = (u32)ptr; + /* Save len */ + tx_bd.cntrl = len | XAXIDMA_BD_CTRL_TXSOF_MASK | + XAXIDMA_BD_CTRL_TXEOF_MASK; + + /* Flush the last BD so DMA core could see the updates */ + flush_cache((u32)&tx_bd, sizeof(tx_bd)); + + if (in_be32(&priv->dmatx->status) & XAXIDMA_HALTED_MASK) { + u32 temp; + out_be32(&priv->dmatx->current, (u32)&tx_bd); + /* Start the hardware */ + temp = in_be32(&priv->dmatx->control); + temp |= XAXIDMA_CR_RUNSTOP_MASK; + out_be32(&priv->dmatx->control, temp); + } + + /* Start transfer */ + out_be32(&priv->dmatx->tail, (u32)&tx_bd); + + /* Wait for transmission to complete */ + debug("axiemac: Waiting for tx to be done\n"); + timeout = 200; + while (timeout && (!in_be32(&priv->dmatx->status) & + (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK))) { + timeout--; + udelay(1); + } + if (!timeout) { + printf("%s: Timeout\n", __func__); + return 1; + } + + debug("axiemac: Sending complete\n"); + return 0; +} + +static int isrxready(struct eth_device *dev) +{ + u32 status; + struct axidma_priv *priv = dev->priv; + + /* Read pending interrupts */ + status = in_be32(&priv->dmarx->status); + + /* Acknowledge pending interrupts */ + out_be32(&priv->dmarx->status, status & XAXIDMA_IRQ_ALL_MASK); + + /* + * If Reception done interrupt is asserted, call RX call back function + * to handle the processed BDs and then raise the according flag. + */ + if ((status & (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK))) + return 1; + + return 0; +} + +static int axiemac_recv(struct eth_device *dev) +{ + u32 length; + struct axidma_priv *priv = dev->priv; + u32 temp; + + /* Wait for an incoming packet */ + if (!isrxready(dev)) + return 0; + + debug("axiemac: RX data ready\n"); + + /* Disable IRQ for a moment till packet is handled */ + temp = in_be32(&priv->dmarx->control); + temp &= ~XAXIDMA_IRQ_ALL_MASK; + out_be32(&priv->dmarx->control, temp); + + length = rx_bd.app4 & 0xFFFF; /* max length mask */ +#ifdef DEBUG + print_buffer(&rxframe, &rxframe[0], 1, length, 16); +#endif + /* Pass the received frame up for processing */ + if (length) + net_process_received_packet(rxframe, length); + +#ifdef DEBUG + /* It is useful to clear buffer to be sure that it is consistent */ + memset(rxframe, 0, sizeof(rxframe)); +#endif + /* Setup RxBD */ + /* Clear the whole buffer and setup it again - all flags are cleared */ + memset(&rx_bd, 0, sizeof(rx_bd)); + rx_bd.next = (u32)&rx_bd; + rx_bd.phys = (u32)&rxframe; + rx_bd.cntrl = sizeof(rxframe); + + /* Write bd to HW */ + flush_cache((u32)&rx_bd, sizeof(rx_bd)); + + /* It is necessary to flush rxframe because if you don't do it + * then cache will contain previous packet */ + flush_cache((u32)&rxframe, sizeof(rxframe)); + + /* Rx BD is ready - start again */ + out_be32(&priv->dmarx->tail, (u32)&rx_bd); + + debug("axiemac: RX completed, framelength = %d\n", length); + + return length; +} + +static int axiemac_miiphy_read(const char *devname, uchar addr, + uchar reg, ushort *val) +{ + struct eth_device *dev = eth_get_dev(); + u32 ret; + + ret = phyread(dev, addr, reg, val); + debug("axiemac: Read MII 0x%x, 0x%x, 0x%x\n", addr, reg, *val); + return ret; +} + +static int axiemac_miiphy_write(const char *devname, uchar addr, + uchar reg, ushort val) +{ + struct eth_device *dev = eth_get_dev(); + + debug("axiemac: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, val); + return phywrite(dev, addr, reg, val); +} + +static int axiemac_bus_reset(struct mii_dev *bus) +{ + debug("axiemac: Bus reset\n"); + return 0; +} + +int xilinx_axiemac_initialize(bd_t *bis, unsigned long base_addr, + unsigned long dma_addr) +{ + struct eth_device *dev; + struct axidma_priv *priv; + + dev = calloc(1, sizeof(struct eth_device)); + if (dev == NULL) + return -1; + + dev->priv = calloc(1, sizeof(struct axidma_priv)); + if (dev->priv == NULL) { + free(dev); + return -1; + } + priv = dev->priv; + + sprintf(dev->name, "aximac.%lx", base_addr); + + dev->iobase = base_addr; + priv->dmatx = (struct axidma_reg *)dma_addr; + /* RX channel offset is 0x30 */ + priv->dmarx = (struct axidma_reg *)(dma_addr + 0x30); + dev->init = axiemac_init; + dev->halt = axiemac_halt; + dev->send = axiemac_send; + dev->recv = axiemac_recv; + dev->write_hwaddr = axiemac_setup_mac; + +#ifdef CONFIG_PHY_ADDR + priv->phyaddr = CONFIG_PHY_ADDR; +#else + priv->phyaddr = -1; +#endif + + eth_register(dev); + +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) + miiphy_register(dev->name, axiemac_miiphy_read, axiemac_miiphy_write); + priv->bus = miiphy_get_dev_by_name(dev->name); + priv->bus->reset = axiemac_bus_reset; +#endif + return 1; +} diff --git a/sources/uboot-be550/drivers/net/xilinx_emaclite.c b/sources/uboot-be550/drivers/net/xilinx_emaclite.c new file mode 100644 index 00000000..564205df --- /dev/null +++ b/sources/uboot-be550/drivers/net/xilinx_emaclite.c @@ -0,0 +1,392 @@ +/* + * (C) Copyright 2007-2009 Michal Simek + * (C) Copyright 2003 Xilinx Inc. + * + * Michal SIMEK + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +#undef DEBUG + +#define ENET_ADDR_LENGTH 6 + +/* EmacLite constants */ +#define XEL_BUFFER_OFFSET 0x0800 /* Next buffer's offset */ +#define XEL_TPLR_OFFSET 0x07F4 /* Tx packet length */ +#define XEL_TSR_OFFSET 0x07FC /* Tx status */ +#define XEL_RSR_OFFSET 0x17FC /* Rx status */ +#define XEL_RXBUFF_OFFSET 0x1000 /* Receive Buffer */ + +/* Xmit complete */ +#define XEL_TSR_XMIT_BUSY_MASK 0x00000001UL +/* Xmit interrupt enable bit */ +#define XEL_TSR_XMIT_IE_MASK 0x00000008UL +/* Buffer is active, SW bit only */ +#define XEL_TSR_XMIT_ACTIVE_MASK 0x80000000UL +/* Program the MAC address */ +#define XEL_TSR_PROGRAM_MASK 0x00000002UL +/* define for programming the MAC address into the EMAC Lite */ +#define XEL_TSR_PROG_MAC_ADDR (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_PROGRAM_MASK) + +/* Transmit packet length upper byte */ +#define XEL_TPLR_LENGTH_MASK_HI 0x0000FF00UL +/* Transmit packet length lower byte */ +#define XEL_TPLR_LENGTH_MASK_LO 0x000000FFUL + +/* Recv complete */ +#define XEL_RSR_RECV_DONE_MASK 0x00000001UL +/* Recv interrupt enable bit */ +#define XEL_RSR_RECV_IE_MASK 0x00000008UL + +struct xemaclite { + u32 nexttxbuffertouse; /* Next TX buffer to write to */ + u32 nextrxbuffertouse; /* Next RX buffer to read from */ + u32 txpp; /* TX ping pong buffer */ + u32 rxpp; /* RX ping pong buffer */ +}; + +static u32 etherrxbuff[PKTSIZE_ALIGN/4]; /* Receive buffer */ + +static void xemaclite_alignedread(u32 *srcptr, void *destptr, u32 bytecount) +{ + u32 i; + u32 alignbuffer; + u32 *to32ptr; + u32 *from32ptr; + u8 *to8ptr; + u8 *from8ptr; + + from32ptr = (u32 *) srcptr; + + /* Word aligned buffer, no correction needed. */ + to32ptr = (u32 *) destptr; + while (bytecount > 3) { + *to32ptr++ = *from32ptr++; + bytecount -= 4; + } + to8ptr = (u8 *) to32ptr; + + alignbuffer = *from32ptr++; + from8ptr = (u8 *) &alignbuffer; + + for (i = 0; i < bytecount; i++) + *to8ptr++ = *from8ptr++; +} + +static void xemaclite_alignedwrite(void *srcptr, u32 destptr, u32 bytecount) +{ + u32 i; + u32 alignbuffer; + u32 *to32ptr = (u32 *) destptr; + u32 *from32ptr; + u8 *to8ptr; + u8 *from8ptr; + + from32ptr = (u32 *) srcptr; + while (bytecount > 3) { + + *to32ptr++ = *from32ptr++; + bytecount -= 4; + } + + alignbuffer = 0; + to8ptr = (u8 *) &alignbuffer; + from8ptr = (u8 *) from32ptr; + + for (i = 0; i < bytecount; i++) + *to8ptr++ = *from8ptr++; + + *to32ptr++ = alignbuffer; +} + +static void emaclite_halt(struct eth_device *dev) +{ + debug("eth_halt\n"); +} + +static int emaclite_init(struct eth_device *dev, bd_t *bis) +{ + struct xemaclite *emaclite = dev->priv; + debug("EmacLite Initialization Started\n"); + +/* + * TX - TX_PING & TX_PONG initialization + */ + /* Restart PING TX */ + out_be32 (dev->iobase + XEL_TSR_OFFSET, 0); + /* Copy MAC address */ + xemaclite_alignedwrite(dev->enetaddr, dev->iobase, ENET_ADDR_LENGTH); + /* Set the length */ + out_be32 (dev->iobase + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH); + /* Update the MAC address in the EMAC Lite */ + out_be32 (dev->iobase + XEL_TSR_OFFSET, XEL_TSR_PROG_MAC_ADDR); + /* Wait for EMAC Lite to finish with the MAC address update */ + while ((in_be32 (dev->iobase + XEL_TSR_OFFSET) & + XEL_TSR_PROG_MAC_ADDR) != 0) + ; + + if (emaclite->txpp) { + /* The same operation with PONG TX */ + out_be32 (dev->iobase + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET, 0); + xemaclite_alignedwrite(dev->enetaddr, dev->iobase + + XEL_BUFFER_OFFSET, ENET_ADDR_LENGTH); + out_be32 (dev->iobase + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH); + out_be32 (dev->iobase + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET, + XEL_TSR_PROG_MAC_ADDR); + while ((in_be32 (dev->iobase + XEL_TSR_OFFSET + + XEL_BUFFER_OFFSET) & XEL_TSR_PROG_MAC_ADDR) != 0) + ; + } + +/* + * RX - RX_PING & RX_PONG initialization + */ + /* Write out the value to flush the RX buffer */ + out_be32 (dev->iobase + XEL_RSR_OFFSET, XEL_RSR_RECV_IE_MASK); + + if (emaclite->rxpp) + out_be32 (dev->iobase + XEL_RSR_OFFSET + XEL_BUFFER_OFFSET, + XEL_RSR_RECV_IE_MASK); + + debug("EmacLite Initialization complete\n"); + return 0; +} + +static int xemaclite_txbufferavailable(struct eth_device *dev) +{ + u32 reg; + u32 txpingbusy; + u32 txpongbusy; + struct xemaclite *emaclite = dev->priv; + + /* + * Read the other buffer register + * and determine if the other buffer is available + */ + reg = in_be32 (dev->iobase + + emaclite->nexttxbuffertouse + 0); + txpingbusy = ((reg & XEL_TSR_XMIT_BUSY_MASK) == + XEL_TSR_XMIT_BUSY_MASK); + + reg = in_be32 (dev->iobase + + (emaclite->nexttxbuffertouse ^ XEL_TSR_OFFSET) + 0); + txpongbusy = ((reg & XEL_TSR_XMIT_BUSY_MASK) == + XEL_TSR_XMIT_BUSY_MASK); + + return !(txpingbusy && txpongbusy); +} + +static int emaclite_send(struct eth_device *dev, void *ptr, int len) +{ + u32 reg; + u32 baseaddress; + struct xemaclite *emaclite = dev->priv; + + u32 maxtry = 1000; + + if (len > PKTSIZE) + len = PKTSIZE; + + while (!xemaclite_txbufferavailable(dev) && maxtry) { + udelay(10); + maxtry--; + } + + if (!maxtry) { + printf("Error: Timeout waiting for ethernet TX buffer\n"); + /* Restart PING TX */ + out_be32 (dev->iobase + XEL_TSR_OFFSET, 0); + if (emaclite->txpp) { + out_be32 (dev->iobase + XEL_TSR_OFFSET + + XEL_BUFFER_OFFSET, 0); + } + return -1; + } + + /* Determine the expected TX buffer address */ + baseaddress = (dev->iobase + emaclite->nexttxbuffertouse); + + /* Determine if the expected buffer address is empty */ + reg = in_be32 (baseaddress + XEL_TSR_OFFSET); + if (((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) + && ((in_be32 ((baseaddress) + XEL_TSR_OFFSET) + & XEL_TSR_XMIT_ACTIVE_MASK) == 0)) { + + if (emaclite->txpp) + emaclite->nexttxbuffertouse ^= XEL_BUFFER_OFFSET; + + debug("Send packet from 0x%x\n", baseaddress); + /* Write the frame to the buffer */ + xemaclite_alignedwrite(ptr, baseaddress, len); + out_be32 (baseaddress + XEL_TPLR_OFFSET,(len & + (XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO))); + reg = in_be32 (baseaddress + XEL_TSR_OFFSET); + reg |= XEL_TSR_XMIT_BUSY_MASK; + if ((reg & XEL_TSR_XMIT_IE_MASK) != 0) + reg |= XEL_TSR_XMIT_ACTIVE_MASK; + out_be32 (baseaddress + XEL_TSR_OFFSET, reg); + return 0; + } + + if (emaclite->txpp) { + /* Switch to second buffer */ + baseaddress ^= XEL_BUFFER_OFFSET; + /* Determine if the expected buffer address is empty */ + reg = in_be32 (baseaddress + XEL_TSR_OFFSET); + if (((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) + && ((in_be32 ((baseaddress) + XEL_TSR_OFFSET) + & XEL_TSR_XMIT_ACTIVE_MASK) == 0)) { + debug("Send packet from 0x%x\n", baseaddress); + /* Write the frame to the buffer */ + xemaclite_alignedwrite(ptr, baseaddress, len); + out_be32 (baseaddress + XEL_TPLR_OFFSET, (len & + (XEL_TPLR_LENGTH_MASK_HI | + XEL_TPLR_LENGTH_MASK_LO))); + reg = in_be32 (baseaddress + XEL_TSR_OFFSET); + reg |= XEL_TSR_XMIT_BUSY_MASK; + if ((reg & XEL_TSR_XMIT_IE_MASK) != 0) + reg |= XEL_TSR_XMIT_ACTIVE_MASK; + out_be32 (baseaddress + XEL_TSR_OFFSET, reg); + return 0; + } + } + + puts("Error while sending frame\n"); + return -1; +} + +static int emaclite_recv(struct eth_device *dev) +{ + u32 length; + u32 reg; + u32 baseaddress; + struct xemaclite *emaclite = dev->priv; + + baseaddress = dev->iobase + emaclite->nextrxbuffertouse; + reg = in_be32 (baseaddress + XEL_RSR_OFFSET); + debug("Testing data at address 0x%x\n", baseaddress); + if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) { + if (emaclite->rxpp) + emaclite->nextrxbuffertouse ^= XEL_BUFFER_OFFSET; + } else { + + if (!emaclite->rxpp) { + debug("No data was available - address 0x%x\n", + baseaddress); + return 0; + } else { + baseaddress ^= XEL_BUFFER_OFFSET; + reg = in_be32 (baseaddress + XEL_RSR_OFFSET); + if ((reg & XEL_RSR_RECV_DONE_MASK) != + XEL_RSR_RECV_DONE_MASK) { + debug("No data was available - address 0x%x\n", + baseaddress); + return 0; + } + } + } + /* Get the length of the frame that arrived */ + switch(((ntohl(in_be32 (baseaddress + XEL_RXBUFF_OFFSET + 0xC))) & + 0xFFFF0000 ) >> 16) { + case 0x806: + length = 42 + 20; /* FIXME size of ARP */ + debug("ARP Packet\n"); + break; + case 0x800: + length = 14 + 14 + + (((ntohl(in_be32 (baseaddress + XEL_RXBUFF_OFFSET + + 0x10))) & 0xFFFF0000) >> 16); + /* FIXME size of IP packet */ + debug ("IP Packet\n"); + break; + default: + debug("Other Packet\n"); + length = PKTSIZE; + break; + } + + xemaclite_alignedread((u32 *) (baseaddress + XEL_RXBUFF_OFFSET), + etherrxbuff, length); + + /* Acknowledge the frame */ + reg = in_be32 (baseaddress + XEL_RSR_OFFSET); + reg &= ~XEL_RSR_RECV_DONE_MASK; + out_be32 (baseaddress + XEL_RSR_OFFSET, reg); + + debug("Packet receive from 0x%x, length %dB\n", baseaddress, length); + net_process_received_packet((uchar *)etherrxbuff, length); + return length; + +} + +int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr, + int txpp, int rxpp) +{ + struct eth_device *dev; + struct xemaclite *emaclite; + + dev = calloc(1, sizeof(*dev)); + if (dev == NULL) + return -1; + + emaclite = calloc(1, sizeof(struct xemaclite)); + if (emaclite == NULL) { + free(dev); + return -1; + } + + dev->priv = emaclite; + + emaclite->txpp = txpp; + emaclite->rxpp = rxpp; + + sprintf(dev->name, "Xelite.%lx", base_addr); + + dev->iobase = base_addr; + dev->init = emaclite_init; + dev->halt = emaclite_halt; + dev->send = emaclite_send; + dev->recv = emaclite_recv; + + eth_register(dev); + + return 1; +} + +#if CONFIG_IS_ENABLED(OF_CONTROL) +int xilinx_emaclite_of_init(const void *blob) +{ + int offset = 0; + u32 ret = 0; + u32 reg; + + do { + offset = fdt_node_offset_by_compatible(blob, offset, + "xlnx,xps-ethernetlite-1.00.a"); + if (offset != -1) { + reg = fdtdec_get_addr(blob, offset, "reg"); + if (reg != FDT_ADDR_T_NONE) { + u32 rxpp = fdtdec_get_int(blob, offset, + "xlnx,rx-ping-pong", 0); + u32 txpp = fdtdec_get_int(blob, offset, + "xlnx,tx-ping-pong", 0); + ret |= xilinx_emaclite_initialize(NULL, reg, + txpp, rxpp); + } else { + debug("EMACLITE: Can't get base address\n"); + return -1; + } + } + } while (offset != -1); + + return ret; +} +#endif diff --git a/sources/uboot-be550/drivers/net/xilinx_ll_temac.c b/sources/uboot-be550/drivers/net/xilinx_ll_temac.c new file mode 100644 index 00000000..7cc86571 --- /dev/null +++ b/sources/uboot-be550/drivers/net/xilinx_ll_temac.c @@ -0,0 +1,402 @@ +/* + * Xilinx xps_ll_temac ethernet driver for u-boot + * + * supports SDMA or FIFO access and MDIO bus communication + * + * Copyright (C) 2011 - 2012 Stephan Linz + * Copyright (C) 2008 - 2011 Michal Simek + * Copyright (C) 2008 - 2011 PetaLogix + * + * Based on Yoshio Kashiwagi kashiwagi@co-nss.co.jp driver + * Copyright (C) 2008 Nissin Systems Co.,Ltd. + * March 2008 created + * + * SPDX-License-Identifier: GPL-2.0+ + * + * [0]: http://www.xilinx.com/support/documentation + * + * [S]: [0]/ip_documentation/xps_ll_temac.pdf + * [A]: [0]/application_notes/xapp1041.pdf + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "xilinx_ll_temac.h" +#include "xilinx_ll_temac_fifo.h" +#include "xilinx_ll_temac_sdma.h" +#include "xilinx_ll_temac_mdio.h" + +#if !defined(CONFIG_MII) +# error "LL_TEMAC requires MII -- missing CONFIG_MII" +#endif + +#if !defined(CONFIG_PHYLIB) +# error "LL_TEMAC requires PHYLIB -- missing CONFIG_PHYLIB" +#endif + +struct ll_temac_info { + int flags; + unsigned long base_addr; + unsigned long ctrl_addr; + char *devname; + unsigned int phyaddr; + char *mdio_busname; +}; + +/* Ethernet interface ready status */ +int ll_temac_check_status(struct temac_reg *regs, u32 mask) +{ + unsigned timeout = 50; /* 1usec * 50 = 50usec */ + + /* + * Quote from LL TEMAC documentation: The bits in the RDY + * register are asserted when there is no access in progress. + * When an access is in progress, a bit corresponding to the + * type of access is automatically de-asserted. The bit is + * automatically re-asserted when the access is complete. + */ + while (timeout && (!(in_be32(®s->rdy) & mask))) { + timeout--; + udelay(1); + } + + if (!timeout) { + printf("%s: Timeout on 0x%08x @%p\n", __func__, + mask, ®s->rdy); + return 1; + } + + return 0; +} + +/* + * Indirect write to ll_temac. + * + * http://www.xilinx.com/support/documentation/ip_documentation/xps_ll_temac.pdf + * page 23, second paragraph, The use of CTL0 register or CTL1 register + */ +int ll_temac_indirect_set(struct temac_reg *regs, u16 regn, u32 reg_data) +{ + out_be32(®s->lsw, (reg_data & MLSW_MASK)); + out_be32(®s->ctl, CTL_WEN | (regn & CTL_ADDR_MASK)); + + if (ll_temac_check_status(regs, RSE_CFG_WR)) + return 0; + + return 1; +} + +/* + * Indirect read from ll_temac. + * + * http://www.xilinx.com/support/documentation/ip_documentation/xps_ll_temac.pdf + * page 23, second paragraph, The use of CTL0 register or CTL1 register + */ +int ll_temac_indirect_get(struct temac_reg *regs, u16 regn, u32* reg_data) +{ + out_be32(®s->ctl, (regn & CTL_ADDR_MASK)); + + if (ll_temac_check_status(regs, RSE_CFG_RR)) + return 0; + + *reg_data = in_be32(®s->lsw) & MLSW_MASK; + return 1; +} + +/* setting sub-controller and ll_temac to proper setting */ +static int ll_temac_setup_ctrl(struct eth_device *dev) +{ + struct ll_temac *ll_temac = dev->priv; + struct temac_reg *regs = (struct temac_reg *)dev->iobase; + + if (ll_temac->ctrlreset && ll_temac->ctrlreset(dev)) + return 0; + + if (ll_temac->ctrlinit && ll_temac->ctrlinit(dev)) + return 0; + + /* Promiscuous mode disable */ + if (!ll_temac_indirect_set(regs, TEMAC_AFM, 0)) + return 0; + + /* Enable Receiver - RX bit */ + if (!ll_temac_indirect_set(regs, TEMAC_RCW1, RCW1_RX)) + return 0; + + /* Enable Transmitter - TX bit */ + if (!ll_temac_indirect_set(regs, TEMAC_TC, TC_TX)) + return 0; + + return 1; +} + +/* + * Configure ll_temac based on negotiated speed and duplex + * reported by PHY handling code + */ +static int ll_temac_adjust_link(struct eth_device *dev) +{ + unsigned int speed, emmc_reg; + struct temac_reg *regs = (struct temac_reg *)dev->iobase; + struct ll_temac *ll_temac = dev->priv; + struct phy_device *phydev = ll_temac->phydev; + + if (!phydev->link) { + printf("%s: No link.\n", phydev->dev->name); + return 0; + } + + switch (phydev->speed) { + case 1000: + speed = EMMC_LSPD_1000; + break; + case 100: + speed = EMMC_LSPD_100; + break; + case 10: + speed = EMMC_LSPD_10; + break; + default: + return 0; + } + + if (!ll_temac_indirect_get(regs, TEMAC_EMMC, &emmc_reg)) + return 0; + + emmc_reg &= ~EMMC_LSPD_MASK; + emmc_reg |= speed; + + if (!ll_temac_indirect_set(regs, TEMAC_EMMC, emmc_reg)) + return 0; + + printf("%s: PHY is %s with %dbase%s, %s%s\n", + dev->name, phydev->drv->name, + phydev->speed, (phydev->port == PORT_TP) ? "T" : "X", + (phydev->duplex) ? "FDX" : "HDX", + (phydev->port == PORT_OTHER) ? ", unkown mode" : ""); + + return 1; +} + +/* setup mac addr */ +static int ll_temac_setup_mac_addr(struct eth_device *dev) +{ + struct temac_reg *regs = (struct temac_reg *)dev->iobase; + u32 val; + + /* set up unicast MAC address filter */ + val = ((dev->enetaddr[3] << 24) | (dev->enetaddr[2] << 16) | + (dev->enetaddr[1] << 8) | (dev->enetaddr[0])); + val &= UAW0_UADDR_MASK; + + if (!ll_temac_indirect_set(regs, TEMAC_UAW0, val)) + return 1; + + val = ((dev->enetaddr[5] << 8) | dev->enetaddr[4]); + val &= UAW1_UADDR_MASK; + + if (!ll_temac_indirect_set(regs, TEMAC_UAW1, val)) + return 1; + + return 0; +} + +/* halt device */ +static void ll_temac_halt(struct eth_device *dev) +{ + struct ll_temac *ll_temac = dev->priv; + struct temac_reg *regs = (struct temac_reg *)dev->iobase; + + /* Disable Receiver */ + ll_temac_indirect_set(regs, TEMAC_RCW0, 0); + + /* Disable Transmitter */ + ll_temac_indirect_set(regs, TEMAC_TC, 0); + + if (ll_temac->ctrlhalt) + ll_temac->ctrlhalt(dev); + + /* Shut down the PHY, as needed */ + phy_shutdown(ll_temac->phydev); +} + +static int ll_temac_init(struct eth_device *dev, bd_t *bis) +{ + struct ll_temac *ll_temac = dev->priv; + int ret; + + printf("%s: Xilinx XPS LocalLink Tri-Mode Ether MAC #%d at 0x%08lx.\n", + dev->name, dev->index, dev->iobase); + + if (!ll_temac_setup_ctrl(dev)) + return -1; + + /* Start up the PHY */ + ret = phy_startup(ll_temac->phydev); + if (ret) { + printf("%s: Could not initialize PHY %s\n", + dev->name, ll_temac->phydev->dev->name); + return ret; + } + + if (!ll_temac_adjust_link(dev)) { + ll_temac_halt(dev); + return -1; + } + + /* If there's no link, fail */ + return ll_temac->phydev->link ? 0 : -1; +} + +/* + * Discover which PHY is attached to the device, and configure it + * properly. If the PHY is not recognized, then return 0 + * (failure). Otherwise, return 1 + */ +static int ll_temac_phy_init(struct eth_device *dev) +{ + struct ll_temac *ll_temac = dev->priv; + struct phy_device *phydev; + unsigned int supported = PHY_GBIT_FEATURES; + + /* interface - look at driver/net/tsec.c */ + phydev = phy_connect(ll_temac->bus, ll_temac->phyaddr, + dev, PHY_INTERFACE_MODE_NONE); + + phydev->supported &= supported; + phydev->advertising = phydev->supported; + + ll_temac->phydev = phydev; + + phy_config(phydev); + + return 1; +} + +/* + * Initialize a single ll_temac devices + * + * Returns the result of ll_temac phy interface that were initialized + */ +int xilinx_ll_temac_initialize(bd_t *bis, struct ll_temac_info *devinf) +{ + struct eth_device *dev; + struct ll_temac *ll_temac; + + dev = calloc(1, sizeof(*dev)); + if (dev == NULL) + return 0; + + ll_temac = calloc(1, sizeof(struct ll_temac)); + if (ll_temac == NULL) { + free(dev); + return 0; + } + + /* use given name or generate its own unique name */ + if (devinf->devname) { + strncpy(dev->name, devinf->devname, sizeof(dev->name)); + } else { + snprintf(dev->name, sizeof(dev->name), "lltemac.%lx", devinf->base_addr); + devinf->devname = dev->name; + } + + dev->iobase = devinf->base_addr; + + dev->priv = ll_temac; + dev->init = ll_temac_init; + dev->halt = ll_temac_halt; + dev->write_hwaddr = ll_temac_setup_mac_addr; + + ll_temac->ctrladdr = devinf->ctrl_addr; + if (devinf->flags & XILINX_LL_TEMAC_M_SDMA_PLB) { +#if defined(CONFIG_XILINX_440) || defined(CONFIG_XILINX_405) + if (devinf->flags & XILINX_LL_TEMAC_M_SDMA_DCR) { + ll_temac_collect_xldcr_sdma_reg_addr(dev); + ll_temac->in32 = ll_temac_xldcr_in32; + ll_temac->out32 = ll_temac_xldcr_out32; + } else +#endif + { + ll_temac_collect_xlplb_sdma_reg_addr(dev); + ll_temac->in32 = ll_temac_xlplb_in32; + ll_temac->out32 = ll_temac_xlplb_out32; + } + ll_temac->ctrlinit = ll_temac_init_sdma; + ll_temac->ctrlhalt = ll_temac_halt_sdma; + ll_temac->ctrlreset = ll_temac_reset_sdma; + dev->recv = ll_temac_recv_sdma; + dev->send = ll_temac_send_sdma; + } else { + ll_temac->in32 = NULL; + ll_temac->out32 = NULL; + ll_temac->ctrlinit = NULL; + ll_temac->ctrlhalt = NULL; + ll_temac->ctrlreset = ll_temac_reset_fifo; + dev->recv = ll_temac_recv_fifo; + dev->send = ll_temac_send_fifo; + } + + /* Link to specified MDIO bus */ + strncpy(ll_temac->mdio_busname, devinf->mdio_busname, MDIO_NAME_LEN); + ll_temac->bus = miiphy_get_dev_by_name(ll_temac->mdio_busname); + + /* Looking for a valid PHY address if it is not yet set */ + if (devinf->phyaddr == -1) + ll_temac->phyaddr = ll_temac_phy_addr(ll_temac->bus); + else + ll_temac->phyaddr = devinf->phyaddr; + + eth_register(dev); + + /* Try to initialize PHY here, and return */ + return ll_temac_phy_init(dev); +} + +/* + * Initialize a single ll_temac device with its mdio bus behind ll_temac + * + * Returns 1 if the ll_temac device and the mdio bus were initialized + * otherwise returns 0 + */ +int xilinx_ll_temac_eth_init(bd_t *bis, unsigned long base_addr, int flags, + unsigned long ctrl_addr) +{ + struct ll_temac_info devinf; + struct ll_temac_mdio_info mdioinf; + int ret; + + /* prepare the internal driver informations */ + devinf.flags = flags; + devinf.base_addr = base_addr; + devinf.ctrl_addr = ctrl_addr; + devinf.devname = NULL; + devinf.phyaddr = -1; + + mdioinf.name = devinf.mdio_busname = NULL; + mdioinf.regs = (struct temac_reg *)devinf.base_addr; + + ret = xilinx_ll_temac_mdio_initialize(bis, &mdioinf); + if (ret >= 0) { + + /* + * If there was no MDIO bus name then take over the + * new automaticaly generated by the MDIO init code. + */ + if (mdioinf.name != devinf.mdio_busname) + devinf.mdio_busname = mdioinf.name; + + ret = xilinx_ll_temac_initialize(bis, &devinf); + if (ret > 0) + return 1; + + } + + return 0; +} diff --git a/sources/uboot-be550/drivers/net/xilinx_ll_temac.h b/sources/uboot-be550/drivers/net/xilinx_ll_temac.h new file mode 100644 index 00000000..56362ba2 --- /dev/null +++ b/sources/uboot-be550/drivers/net/xilinx_ll_temac.h @@ -0,0 +1,307 @@ +/* + * Xilinx xps_ll_temac ethernet driver for u-boot + * + * LL_TEMAC interface + * + * Copyright (C) 2011 - 2012 Stephan Linz + * Copyright (C) 2008 - 2011 Michal Simek + * Copyright (C) 2008 - 2011 PetaLogix + * + * Based on Yoshio Kashiwagi kashiwagi@co-nss.co.jp driver + * Copyright (C) 2008 Nissin Systems Co.,Ltd. + * March 2008 created + * + * SPDX-License-Identifier: GPL-2.0+ + * + * [0]: http://www.xilinx.com/support/documentation + * + * [S]: [0]/ip_documentation/xps_ll_temac.pdf + * [A]: [0]/application_notes/xapp1041.pdf + */ +#ifndef _XILINX_LL_TEMAC_ +#define _XILINX_LL_TEMAC_ + +#include +#include +#include +#include + +#include +#include + +#include "xilinx_ll_temac_sdma.h" + +#if !defined(__BIG_ENDIAN) +# error LL_TEMAC requires big endianess +#endif + +/* + * TEMAC Memory and Register Definition + * + * [1]: [0]/ip_documentation/xps_ll_temac.pdf + * page 19, Memory and Register Descriptions + */ +struct temac_reg { + /* direct soft registers (low part) */ + u32 raf; /* Reset and Address Filter */ + u32 tpf; /* Transmit Pause Frame */ + u32 ifgp; /* Transmit Inter Frame Gap Adjustment */ + u32 is; /* Interrupt Status */ + u32 ip; /* Interrupt Pending */ + u32 ie; /* Interrupt Enable */ + u32 ttag; /* Transmit VLAN Tag */ + u32 rtag; /* Receive VLAN Tag */ + /* hard TEMAC registers */ + u32 msw; /* Most Significant Word Data */ + u32 lsw; /* Least Significant Word Data */ + u32 ctl; /* Control */ + u32 rdy; /* Ready Status */ + /* direct soft registers (high part) */ + u32 uawl; /* Unicast Address Word Lower */ + u32 uawu; /* Unicast Address Word Upper */ + u32 tpid0; /* VLAN TPID Word 0 */ + u32 tpid1; /* VLAN TPID Word 1 */ +}; + +/* Reset and Address Filter Registers (raf), [1] p25 */ +#define RAF_SR (1 << 13) +#define RAF_EMFE (1 << 12) +#define RAF_NFE (1 << 11) +#define RAF_RVSTM_POS 9 +#define RAF_RVSTM_MASK (3 << RAF_RVSTM_POS) +#define RAF_TVSTM_POS 7 +#define RAF_TVSTM_MASK (3 << RAF_TVSTM_POS) +#define RAF_RVTM_POS 5 +#define RAF_RVTM_MASK (3 << RAF_RVTM_POS) +#define RAF_TVTM_POS 3 +#define RAF_TVTM_MASK (3 << RAF_TVTM_POS) +#define RAF_BCREJ (1 << 2) +#define RAF_MCREJ (1 << 1) +#define RAF_HTRST (1 << 0) + +/* Transmit Pause Frame Registers (tpf), [1] p28 */ +#define TPF_TPFV_POS 0 +#define TPF_TPFV_MASK (0xFFFF << TPF_TPFV_POS) + +/* Transmit Inter Frame Gap Adjustment Registers (ifgp), [1] p28 */ +#define IFGP_POS 0 +#define IFGP_MASK (0xFF << IFGP_POS) + +/* Interrupt Status, Pending, Enable Registers (is, ip, ie), [1] p29-33 */ +#define ISPE_MR (1 << 7) +#define ISPE_RDL (1 << 6) +#define ISPE_TC (1 << 5) +#define ISPE_RFO (1 << 4) +#define ISPE_RR (1 << 3) +#define ISPE_RC (1 << 2) +#define ISPE_AN (1 << 1) +#define ISPE_HAC (1 << 0) + +/* Transmit, Receive VLAN Tag Registers (ttag, rtag), [1] p34-35 */ +#define TRTAG_TPID_POS 16 +#define TRTAG_TPID_MASK (0xFFFF << TRTAG_TPID_POS) +#define TRTAG_PRIO_POS 13 +#define TRTAG_PRIO_MASK (7 << TRTAG_PRIO_POS) +#define TRTAG_CFI (1 << 12) +#define TRTAG_VID_POS 0 +#define TRTAG_VID_MASK (0xFFF << TRTAG_VID_POS) + +/* Most, Least Significant Word Data Register (msw, lsw), [1] p46 */ +#define MLSW_POS 0 +#define MLSW_MASK (~0UL << MLSW_POS) + +/* LSW Data Register for PHY addresses (lsw), [1] p66 */ +#define LSW_REGAD_POS 0 +#define LSW_REGAD_MASK (0x1F << LSW_REGAD_POS) +#define LSW_PHYAD_POS 5 +#define LSW_PHYAD_MASK (0x1F << LSW_PHYAD_POS) + +/* LSW Data Register for PHY data (lsw), [1] p66 */ +#define LSW_REGDAT_POS 0 +#define LSW_REGDAT_MASK (0xFFFF << LSW_REGDAT_POS) + +/* Control Register (ctl), [1] p47 */ +#define CTL_WEN (1 << 15) +#define CTL_ADDR_POS 0 +#define CTL_ADDR_MASK (0x3FF << CTL_ADDR_POS) + +/* Ready Status Register Ethernet (rdy), [1] p48 */ +#define RSE_HACS_RDY (1 << 14) +#define RSE_CFG_WR (1 << 6) +#define RSE_CFG_RR (1 << 5) +#define RSE_AF_WR (1 << 4) +#define RSE_AF_RR (1 << 3) +#define RSE_MIIM_WR (1 << 2) +#define RSE_MIIM_RR (1 << 1) +#define RSE_FABR_RR (1 << 0) + +/* Unicast Address Word Lower, Upper Registers (uawl, uawu), [1] p35-36 */ +#define UAWL_UADDR_POS 0 +#define UAWL_UADDR_MASK (~0UL << UAWL_UADDR_POS) +#define UAWU_UADDR_POS 0 +#define UAWU_UADDR_MASK (0xFFFF << UAWU_UADDR_POS) + +/* VLAN TPID Word 0, 1 Registers (tpid0, tpid1), [1] p37 */ +#define TPID0_V0_POS 0 +#define TPID0_V0_MASK (0xFFFF << TPID0_V0_POS) +#define TPID0_V1_POS 16 +#define TPID0_V1_MASK (0xFFFF << TPID0_V1_POS) +#define TPID1_V2_POS 0 +#define TPID1_V2_MASK (0xFFFF << TPID1_V2_POS) +#define TPID1_V3_POS 16 +#define TPID1_V3_MASK (0xFFFF << TPID1_V3_POS) + +/* + * TEMAC Indirectly Addressable Register Index Enumeration + * + * [0]: http://www.xilinx.com/support/documentation + * + * [1]: [0]/ip_documentation/xps_ll_temac.pdf + * page 23, PLB Indirectly Addressable TEMAC Registers + */ +enum temac_ctrl { + TEMAC_RCW0 = 0x200, + TEMAC_RCW1 = 0x240, + TEMAC_TC = 0x280, + TEMAC_FCC = 0x2C0, + TEMAC_EMMC = 0x300, + TEMAC_PHYC = 0x320, + TEMAC_MC = 0x340, + TEMAC_UAW0 = 0x380, + TEMAC_UAW1 = 0x384, + TEMAC_MAW0 = 0x388, + TEMAC_MAW1 = 0x38C, + TEMAC_AFM = 0x390, + TEMAC_TIS = 0x3A0, + TEMAC_TIE = 0x3A4, + TEMAC_MIIMWD = 0x3B0, + TEMAC_MIIMAI = 0x3B4 +}; + +/* Receive Configuration Word 0, 1 Registers (RCW0, RCW1), [1] p50-51 */ +#define RCW0_PADDR_POS 0 +#define RCW0_PADDR_MASK (~0UL << RCW_PADDR_POS) +#define RCW1_RST (1 << 31) +#define RCW1_JUM (1 << 30) +#define RCW1_FCS (1 << 29) +#define RCW1_RX (1 << 28) +#define RCW1_VLAN (1 << 27) +#define RCW1_HD (1 << 26) +#define RCW1_LT_DIS (1 << 25) +#define RCW1_PADDR_POS 0 +#define RCW1_PADDR_MASK (0xFFFF << RCW_PADDR_POS) + +/* Transmit Configuration Registers (TC), [1] p52 */ +#define TC_RST (1 << 31) +#define TC_JUM (1 << 30) +#define TC_FCS (1 << 29) +#define TC_TX (1 << 28) +#define TC_VLAN (1 << 27) +#define TC_HD (1 << 26) +#define TC_IFG (1 << 25) + +/* Flow Control Configuration Registers (FCC), [1] p54 */ +#define FCC_FCTX (1 << 30) +#define FCC_FCRX (1 << 29) + +/* Ethernet MAC Mode Configuration Registers (EMMC), [1] p54 */ +#define EMMC_LSPD_POS 30 +#define EMMC_LSPD_MASK (3 << EMMC_LSPD_POS) +#define EMMC_LSPD_1000 (2 << EMMC_LSPD_POS) +#define EMMC_LSPD_100 (1 << EMMC_LSPD_POS) +#define EMMC_LSPD_10 0 +#define EMMC_RGMII (1 << 29) +#define EMMC_SGMII (1 << 28) +#define EMMC_GPCS (1 << 27) +#define EMMC_HOST (1 << 26) +#define EMMC_TX16 (1 << 25) +#define EMMC_RX16 (1 << 24) + +/* RGMII/SGMII Configuration Registers (PHYC), [1] p56 */ +#define PHYC_SLSPD_POS 30 +#define PHYC_SLSPD_MASK (3 << EMMC_SLSPD_POS) +#define PHYC_SLSPD_1000 (2 << EMMC_SLSPD_POS) +#define PHYC_SLSPD_100 (1 << EMMC_SLSPD_POS) +#define PHYC_SLSPD_10 0 +#define PHYC_RLSPD_POS 2 +#define PHYC_RLSPD_MASK (3 << EMMC_RLSPD_POS) +#define PHYC_RLSPD_1000 (2 << EMMC_RLSPD_POS) +#define PHYC_RLSPD_100 (1 << EMMC_RLSPD_POS) +#define PHYC_RLSPD_10 0 +#define PHYC_RGMII_HD (1 << 1) +#define PHYC_RGMII_LINK (1 << 0) + +/* Management Configuration Registers (MC), [1] p57 */ +#define MC_MDIOEN (1 << 6) +#define MC_CLKDIV_POS 0 +#define MC_CLKDIV_MASK (0x3F << MC_CLKDIV_POS) + +/* + * fHOSTCLK fMDC = fHOSTCLK + * fMDC = ------------------- ---------> MC_CLKDIV = -------- - 1 + * (1 + MC_CLKDIV) * 2 2.5 MHz 5MHz + */ +#define MC_CLKDIV(f, m) ((f / (2 * m)) - 1) +#define MC_CLKDIV_25(f) MC_CLKDIV(f, 2500000) +#define MC_CLKDIV_20(f) MC_CLKDIV(f, 2000000) +#define MC_CLKDIV_15(f) MC_CLKDIV(f, 1500000) +#define MC_CLKDIV_10(f) MC_CLKDIV(f, 1000000) + +/* Unicast Address Word 0, 1 Registers (UAW0, UAW1), [1] p58-59 */ +#define UAW0_UADDR_POS 0 +#define UAW0_UADDR_MASK (~0UL << UAW0_UADDR_POS) +#define UAW1_UADDR_POS 0 +#define UAW1_UADDR_MASK (0xFFFF << UAW1_UADDR_POS) + +/* Multicast Address Word 0, 1 Registers (MAW0, MAW1), [1] p60 */ +#define MAW0_MADDR_POS 0 +#define MAW0_MADDR_MASK (~0UL << MAW0_MADDR_POS) +#define MAW1_RNW (1 << 23) +#define MAW1_MAIDX_POS 16 +#define MAW1_MAIDX_MASK (3 << MAW1_MAIDX_POS) +#define MAW1_MADDR_POS 0 +#define MAW1_MADDR_MASK (0xFFFF << MAW1_MADDR_POS) + +/* Address Filter Mode Registers (AFM), [1] p63 */ +#define AFM_PM (1 << 31) + +/* Interrupt Status, Enable Registers (TIS, TIE), [1] p63-65 */ +#define TISE_CFG_W (1 << 6) +#define TISE_CFG_R (1 << 5) +#define TISE_AF_W (1 << 4) +#define TISE_AF_R (1 << 3) +#define TISE_MIIM_W (1 << 2) +#define TISE_MIIM_R (1 << 1) +#define TISE_FABR_R (1 << 0) + +/* MII Management Write Data Registers (MIIMWD), [1] p66 */ +#define MIIMWD_DATA_POS 0 +#define MIIMWD_DATA_MASK (0xFFFF << MIIMWD_DATA_POS) + +/* Ethernet interface ready status */ +int ll_temac_check_status(struct temac_reg *regs, u32 mask); + +/* Indirect write to ll_temac. */ +int ll_temac_indirect_set(struct temac_reg *regs, u16 regn, u32 reg_data); + +/* Indirect read from ll_temac. */ +int ll_temac_indirect_get(struct temac_reg *regs, u16 regn, u32* reg_data); + +struct ll_temac { + phys_addr_t ctrladdr; + phys_addr_t sdma_reg_addr[SDMA_CTRL_REGNUMS]; + + unsigned (*in32)(phys_addr_t); + void (*out32)(phys_addr_t, unsigned); + + int (*ctrlinit) (struct eth_device *); + int (*ctrlhalt) (struct eth_device *); + int (*ctrlreset) (struct eth_device *); + + int phyaddr; + struct phy_device *phydev; + struct mii_dev *bus; + char mdio_busname[MDIO_NAME_LEN]; +}; + +#endif /* _XILINX_LL_TEMAC_ */ diff --git a/sources/uboot-be550/drivers/net/xilinx_ll_temac_fifo.c b/sources/uboot-be550/drivers/net/xilinx_ll_temac_fifo.c new file mode 100644 index 00000000..78319d7d --- /dev/null +++ b/sources/uboot-be550/drivers/net/xilinx_ll_temac_fifo.c @@ -0,0 +1,139 @@ +/* + * Xilinx xps_ll_temac ethernet driver for u-boot + * + * FIFO sub-controller + * + * Copyright (C) 2011 - 2012 Stephan Linz + * Copyright (C) 2008 - 2011 Michal Simek + * Copyright (C) 2008 - 2011 PetaLogix + * + * Based on Yoshio Kashiwagi kashiwagi@co-nss.co.jp driver + * Copyright (C) 2008 Nissin Systems Co.,Ltd. + * March 2008 created + * + * CREDITS: tsec driver + * + * SPDX-License-Identifier: GPL-2.0+ + * + * [0]: http://www.xilinx.com/support/documentation + * + * [F]: [0]/ip_documentation/xps_ll_fifo.pdf + * [S]: [0]/ip_documentation/xps_ll_temac.pdf + * [A]: [0]/application_notes/xapp1041.pdf + */ + +#include +#include +#include + +#include +#include + +#include "xilinx_ll_temac.h" +#include "xilinx_ll_temac_fifo.h" + +int ll_temac_reset_fifo(struct eth_device *dev) +{ + struct ll_temac *ll_temac = dev->priv; + struct fifo_ctrl *fifo_ctrl = (void *)ll_temac->ctrladdr; + + out_be32(&fifo_ctrl->tdfr, LL_FIFO_TDFR_KEY); + out_be32(&fifo_ctrl->rdfr, LL_FIFO_RDFR_KEY); + out_be32(&fifo_ctrl->isr, ~0UL); + out_be32(&fifo_ctrl->ier, 0); + + return 0; +} + +int ll_temac_recv_fifo(struct eth_device *dev) +{ + int i, length = 0; + u32 *buf = (u32 *)net_rx_packets[0]; + struct ll_temac *ll_temac = dev->priv; + struct fifo_ctrl *fifo_ctrl = (void *)ll_temac->ctrladdr; + + if (in_be32(&fifo_ctrl->isr) & LL_FIFO_ISR_RC) { + + /* reset isr */ + out_be32(&fifo_ctrl->isr, ~0UL); + + /* + * MAYBE here: + * while (fifo_ctrl->isr); + */ + + /* + * The length is written (into RLR) by the XPS LL FIFO + * when the packet is received across the RX LocalLink + * interface and the receive data FIFO had enough + * locations that all of the packet data has been saved. + * The RLR should only be read when a receive packet is + * available for processing (the receive occupancy is + * not zero). Once the RLR is read, the receive packet + * data should be read from the receive data FIFO before + * the RLR is read again. + * + * [F] page 17, Receive Length Register (RLR) + */ + if (in_be32(&fifo_ctrl->rdfo) & LL_FIFO_RDFO_MASK) { + length = in_be32(&fifo_ctrl->rlf) & LL_FIFO_RLF_MASK; + } else { + printf("%s: Got error, no receive occupancy\n", + __func__); + return -1; + } + + if (length > PKTSIZE_ALIGN) { + printf("%s: Got error, receive package too big (%i)\n", + __func__, length); + ll_temac_reset_fifo(dev); + return -1; + } + + for (i = 0; i < length; i += 4) + *buf++ = in_be32(&fifo_ctrl->rdfd); + + net_process_received_packet(net_rx_packets[0], length); + } + + return 0; +} + +int ll_temac_send_fifo(struct eth_device *dev, void *packet, int length) +{ + int i; + u32 *buf = (u32 *)packet; + struct ll_temac *ll_temac = dev->priv; + struct fifo_ctrl *fifo_ctrl = (void *)ll_temac->ctrladdr; + + if (length < LL_FIFO_TLF_MIN) { + printf("%s: Got error, transmit package too small (%i)\n", + __func__, length); + return -1; + } + + if (length > LL_FIFO_TLF_MAX) { + printf("%s: Got error, transmit package too big (%i)\n", + __func__, length); + return -1; + } + + for (i = 0; i < length; i += 4) + out_be32(&fifo_ctrl->tdfd, *buf++); + + /* + * Once the packet length is written to the TLR it is + * automatically moved to the transmit data FIFO with + * the packet data freeing up the TLR for another value. + * The packet length must be written to the TLR after + * the packet data is written to the transmit data FIFO. + * It is not valid to write data for multiple packets + * to the transmit data FIFO before writing the packet + * length values. + * + * [F] page 17, Transmit Length Register (TLR) + */ + out_be32(&fifo_ctrl->tlf, length); + + return 0; +} diff --git a/sources/uboot-be550/drivers/net/xilinx_ll_temac_fifo.h b/sources/uboot-be550/drivers/net/xilinx_ll_temac_fifo.h new file mode 100644 index 00000000..c1bf7cc6 --- /dev/null +++ b/sources/uboot-be550/drivers/net/xilinx_ll_temac_fifo.h @@ -0,0 +1,118 @@ +/* + * Xilinx xps_ll_temac ethernet driver for u-boot + * + * FIFO sub-controller interface + * + * Copyright (C) 2011 - 2012 Stephan Linz + * Copyright (C) 2008 - 2011 Michal Simek + * Copyright (C) 2008 - 2011 PetaLogix + * + * Based on Yoshio Kashiwagi kashiwagi@co-nss.co.jp driver + * Copyright (C) 2008 Nissin Systems Co.,Ltd. + * March 2008 created + * + * SPDX-License-Identifier: GPL-2.0+ + * + * [0]: http://www.xilinx.com/support/documentation + * + * [S]: [0]/ip_documentation/xps_ll_temac.pdf + * [A]: [0]/application_notes/xapp1041.pdf + */ +#ifndef _XILINX_LL_TEMAC_FIFO_ +#define _XILINX_LL_TEMAC_FIFO_ + +#include + +#include +#include + +#if !defined(__BIG_ENDIAN) +# error LL_TEMAC requires big endianess +#endif + +/* + * FIFO Register Definition + * + * Used for memory mapped access from and to (Rd/Td) the LocalLink (LL) + * Tri-Mode Ether MAC (TEMAC) via the 2 kb full duplex FIFO Controller, + * one for each. + * + * [1]: [0]/ip_documentation/xps_ll_fifo.pdf + * page 10, Registers Definition + */ +struct fifo_ctrl { + u32 isr; /* Interrupt Status Register (RW) */ + u32 ier; /* Interrupt Enable Register (RW) */ + u32 tdfr; /* Transmit Data FIFO Reset (WO) */ + u32 tdfv; /* Transmit Data FIFO Vacancy (RO) */ + u32 tdfd; /* Transmit Data FIFO 32bit wide Data write port (WO) */ + u32 tlf; /* Transmit Length FIFO (WO) */ + u32 rdfr; /* Receive Data FIFO Reset (WO) */ + u32 rdfo; /* Receive Data FIFO Occupancy (RO) */ + u32 rdfd; /* Receive Data FIFO 32bit wide Data read port (RO) */ + u32 rlf; /* Receive Length FIFO (RO) */ + u32 llr; /* LocalLink Reset (WO) */ +}; + +/* Interrupt Status Register (ISR), [1] p11 */ +#define LL_FIFO_ISR_RPURE (1 << 31) /* Receive Packet Underrun Read Err */ +#define LL_FIFO_ISR_RPORE (1 << 30) /* Receive Packet Overrun Read Err */ +#define LL_FIFO_ISR_RPUE (1 << 29) /* Receive Packet Underrun Error */ +#define LL_FIFO_ISR_TPOE (1 << 28) /* Transmit Packet Overrun Error */ +#define LL_FIFO_ISR_TC (1 << 27) /* Transmit Complete */ +#define LL_FIFO_ISR_RC (1 << 26) /* Receive Complete */ +#define LL_FIFO_ISR_TSE (1 << 25) /* Transmit Size Error */ +#define LL_FIFO_ISR_TRC (1 << 24) /* Transmit Reset Complete */ +#define LL_FIFO_ISR_RRC (1 << 23) /* Receive Reset Complete */ + +/* Interrupt Enable Register (IER), [1] p12/p13 */ +#define LL_FIFO_IER_RPURE (1 << 31) /* Receive Packet Underrun Read Err */ +#define LL_FIFO_IER_RPORE (1 << 30) /* Receive Packet Overrun Read Err */ +#define LL_FIFO_IER_RPUE (1 << 29) /* Receive Packet Underrun Error */ +#define LL_FIFO_IER_TPOE (1 << 28) /* Transmit Packet Overrun Error */ +#define LL_FIFO_IER_TC (1 << 27) /* Transmit Complete */ +#define LL_FIFO_IER_RC (1 << 26) /* Receive Complete */ +#define LL_FIFO_IER_TSE (1 << 25) /* Transmit Size Error */ +#define LL_FIFO_IER_TRC (1 << 24) /* Transmit Reset Complete */ +#define LL_FIFO_IER_RRC (1 << 23) /* Receive Reset Complete */ + +/* Transmit Data FIFO Reset (TDFR), [1] p13/p14 */ +#define LL_FIFO_TDFR_KEY 0x000000A5UL + +/* Transmit Data FIFO Vacancy (TDFV), [1] p14 */ +#define LL_FIFO_TDFV_POS 0 +#define LL_FIFO_TDFV_MASK (0x000001FFUL << LL_FIFO_TDFV_POS) + +/* Transmit Length FIFO (TLF), [1] p16/p17 */ +#define LL_FIFO_TLF_POS 0 +#define LL_FIFO_TLF_MASK (0x000007FFUL << LL_FIFO_TLF_POS) +#define LL_FIFO_TLF_MIN ((4 * sizeof(u32)) & LL_FIFO_TLF_MASK) +#define LL_FIFO_TLF_MAX ((510 * sizeof(u32)) & LL_FIFO_TLF_MASK) + +/* Receive Data FIFO Reset (RDFR), [1] p15 */ +#define LL_FIFO_RDFR_KEY 0x000000A5UL + +/* Receive Data FIFO Occupancy (RDFO), [1] p16 */ +#define LL_FIFO_RDFO_POS 0 +#define LL_FIFO_RDFO_MASK (0x000001FFUL << LL_FIFO_RDFO_POS) + +/* Receive Length FIFO (RLF), [1] p17/p18 */ +#define LL_FIFO_RLF_POS 0 +#define LL_FIFO_RLF_MASK (0x000007FFUL << LL_FIFO_RLF_POS) +#define LL_FIFO_RLF_MIN ((4 * sizeof(uint32)) & LL_FIFO_RLF_MASK) +#define LL_FIFO_RLF_MAX ((510 * sizeof(uint32)) & LL_FIFO_RLF_MASK) + +/* LocalLink Reset (LLR), [1] p18 */ +#define LL_FIFO_LLR_KEY 0x000000A5UL + + +/* reset FIFO and IRQ, disable interrupts */ +int ll_temac_reset_fifo(struct eth_device *dev); + +/* receive buffered data from FIFO (polling ISR) */ +int ll_temac_recv_fifo(struct eth_device *dev); + +/* send buffered data to FIFO */ +int ll_temac_send_fifo(struct eth_device *dev, void *packet, int length); + +#endif /* _XILINX_LL_TEMAC_FIFO_ */ diff --git a/sources/uboot-be550/drivers/net/xilinx_ll_temac_mdio.c b/sources/uboot-be550/drivers/net/xilinx_ll_temac_mdio.c new file mode 100644 index 00000000..b7bab794 --- /dev/null +++ b/sources/uboot-be550/drivers/net/xilinx_ll_temac_mdio.c @@ -0,0 +1,177 @@ +/* + * Xilinx xps_ll_temac ethernet driver for u-boot + * + * MDIO bus access + * + * Copyright (C) 2011 - 2012 Stephan Linz + * Copyright (C) 2008 - 2011 Michal Simek + * Copyright (C) 2008 - 2011 PetaLogix + * + * Based on Yoshio Kashiwagi kashiwagi@co-nss.co.jp driver + * Copyright (C) 2008 Nissin Systems Co.,Ltd. + * March 2008 created + * + * CREDITS: tsec driver + * + * SPDX-License-Identifier: GPL-2.0+ + * + * [0]: http://www.xilinx.com/support/documentation + * + * [S]: [0]/ip_documentation/xps_ll_temac.pdf + * [A]: [0]/application_notes/xapp1041.pdf + */ + +#include +#include +#include +#include +#include +#include + +#include "xilinx_ll_temac.h" +#include "xilinx_ll_temac_mdio.h" + +#if !defined(CONFIG_MII) +# error "LL_TEMAC requires MII -- missing CONFIG_MII" +#endif + +#if !defined(CONFIG_PHYLIB) +# error "LL_TEMAC requires PHYLIB -- missing CONFIG_PHYLIB" +#endif + +/* + * Prior to PHY access, the MDIO clock must be setup. This driver will set a + * safe default that should work with PLB bus speeds of up to 150 MHz and keep + * the MDIO clock below 2.5 MHz. If the user wishes faster access to the PHY + * then the clock divisor can be set to a different value by setting the + * correct bus speed value with CONFIG_XILINX_LL_TEMAC_CLK. + */ +#if !defined(CONFIG_XILINX_LL_TEMAC_CLK) +#define MDIO_CLOCK_DIV MC_CLKDIV_10(150000000) +#else +#define MDIO_CLOCK_DIV MC_CLKDIV_25(CONFIG_XILINX_LL_TEMAC_CLK) +#endif + +static int ll_temac_mdio_setup(struct mii_dev *bus) +{ + struct temac_reg *regs = (struct temac_reg *)bus->priv; + + /* setup MDIO clock */ + ll_temac_indirect_set(regs, TEMAC_MC, + MC_MDIOEN | (MDIO_CLOCK_DIV & MC_CLKDIV_MASK)); + + return 0; +} + +/* + * Indirect MII PHY read via ll_temac. + * + * http://www.xilinx.com/support/documentation/ip_documentation/xps_ll_temac.pdf + * page 67, Using the MII Management to Access PHY Registers + */ +int ll_temac_local_mdio_read(struct temac_reg *regs, int addr, int devad, + int regnum) +{ + out_be32(®s->lsw, + ((addr << LSW_PHYAD_POS) & LSW_PHYAD_MASK) | + (regnum & LSW_REGAD_MASK)); + out_be32(®s->ctl, TEMAC_MIIMAI); + + ll_temac_check_status(regs, RSE_MIIM_RR); + + return in_be32(®s->lsw) & LSW_REGDAT_MASK; +} + +/* + * Indirect MII PHY write via ll_temac. + * + * http://www.xilinx.com/support/documentation/ip_documentation/xps_ll_temac.pdf + * page 67, Using the MII Management to Access PHY Registers + */ +void ll_temac_local_mdio_write(struct temac_reg *regs, int addr, int devad, + int regnum, u16 value) +{ + out_be32(®s->lsw, (value & LSW_REGDAT_MASK)); + out_be32(®s->ctl, CTL_WEN | TEMAC_MIIMWD); + + out_be32(®s->lsw, + ((addr << LSW_PHYAD_POS) & LSW_PHYAD_MASK) | + (regnum & LSW_REGAD_MASK)); + out_be32(®s->ctl, CTL_WEN | TEMAC_MIIMAI); + + ll_temac_check_status(regs, RSE_MIIM_WR); +} + +int ll_temac_phy_read(struct mii_dev *bus, int addr, int devad, int regnum) +{ + struct temac_reg *regs = (struct temac_reg *)bus->priv; + + return ll_temac_local_mdio_read(regs, addr, devad, regnum); +} + +int ll_temac_phy_write(struct mii_dev *bus, int addr, int devad, int regnum, + u16 value) +{ + struct temac_reg *regs = (struct temac_reg *)bus->priv; + + ll_temac_local_mdio_write(regs, addr, devad, regnum, value); + + return 0; +} + +/* + * Use MII register 1 (MII status register) to detect PHY + * + * A Mask used to verify certain PHY features (register content) + * in the PHY detection register: + * Auto-negotiation support, 10Mbps half/full duplex support + */ +#define PHY_DETECT_REG MII_BMSR +#define PHY_DETECT_MASK (BMSR_10FULL | BMSR_10HALF | BMSR_ANEGCAPABLE) + +/* Looking for a valid PHY address */ +int ll_temac_phy_addr(struct mii_dev *bus) +{ + struct temac_reg *regs = (struct temac_reg *)bus->priv; + unsigned short val; + unsigned int phy; + + for (phy = PHY_MAX_ADDR; phy >= 0; phy--) { + val = ll_temac_local_mdio_read(regs, phy, 0, PHY_DETECT_REG); + if ((val != 0xFFFF) && + ((val & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { + /* Found a valid PHY address */ + return phy; + } + } + + return -1; +} + +int xilinx_ll_temac_mdio_initialize(bd_t *bis, struct ll_temac_mdio_info *info) +{ + struct mii_dev *bus = mdio_alloc(); + + if (!bus) { + printf("Failed to allocate LL_TEMAC MDIO bus: %s\n", + info->name); + return -1; + } + + bus->read = ll_temac_phy_read; + bus->write = ll_temac_phy_write; + bus->reset = NULL; + + /* use given name or generate its own unique name */ + if (info->name) { + strncpy(bus->name, info->name, MDIO_NAME_LEN); + } else { + snprintf(bus->name, MDIO_NAME_LEN, "lltemii.%p", info->regs); + info->name = bus->name; + } + + bus->priv = info->regs; + + ll_temac_mdio_setup(bus); + return mdio_register(bus); +} diff --git a/sources/uboot-be550/drivers/net/xilinx_ll_temac_mdio.h b/sources/uboot-be550/drivers/net/xilinx_ll_temac_mdio.h new file mode 100644 index 00000000..0603c644 --- /dev/null +++ b/sources/uboot-be550/drivers/net/xilinx_ll_temac_mdio.h @@ -0,0 +1,50 @@ +/* + * Xilinx xps_ll_temac ethernet driver for u-boot + * + * MDIO bus access interface + * + * Copyright (C) 2011 - 2012 Stephan Linz + * Copyright (C) 2008 - 2011 Michal Simek + * Copyright (C) 2008 - 2011 PetaLogix + * + * Based on Yoshio Kashiwagi kashiwagi@co-nss.co.jp driver + * Copyright (C) 2008 Nissin Systems Co.,Ltd. + * March 2008 created + * + * SPDX-License-Identifier: GPL-2.0+ + * + * [0]: http://www.xilinx.com/support/documentation + * + * [S]: [0]/ip_documentation/xps_ll_temac.pdf + * [A]: [0]/application_notes/xapp1041.pdf + */ +#ifndef _XILINX_LL_TEMAC_MDIO_ +#define _XILINX_LL_TEMAC_MDIO_ + +#include +#include + +#include +#include + +#include "xilinx_ll_temac.h" + +int ll_temac_local_mdio_read(struct temac_reg *regs, int addr, int devad, + int regnum); +void ll_temac_local_mdio_write(struct temac_reg *regs, int addr, int devad, + int regnum, u16 value); + +int ll_temac_phy_read(struct mii_dev *bus, int addr, int devad, int regnum); +int ll_temac_phy_write(struct mii_dev *bus, int addr, int devad, int regnum, + u16 value); + +int ll_temac_phy_addr(struct mii_dev *bus); + +struct ll_temac_mdio_info { + struct temac_reg *regs; + char *name; +}; + +int xilinx_ll_temac_mdio_initialize(bd_t *bis, struct ll_temac_mdio_info *info); + +#endif /* _XILINX_LL_TEMAC_MDIO_ */ diff --git a/sources/uboot-be550/drivers/net/xilinx_ll_temac_sdma.c b/sources/uboot-be550/drivers/net/xilinx_ll_temac_sdma.c new file mode 100644 index 00000000..07c5f6bf --- /dev/null +++ b/sources/uboot-be550/drivers/net/xilinx_ll_temac_sdma.c @@ -0,0 +1,366 @@ +/* + * Xilinx xps_ll_temac ethernet driver for u-boot + * + * SDMA sub-controller + * + * Copyright (C) 2011 - 2012 Stephan Linz + * Copyright (C) 2008 - 2011 Michal Simek + * Copyright (C) 2008 - 2011 PetaLogix + * + * Based on Yoshio Kashiwagi kashiwagi@co-nss.co.jp driver + * Copyright (C) 2008 Nissin Systems Co.,Ltd. + * March 2008 created + * + * CREDITS: tsec driver + * + * SPDX-License-Identifier: GPL-2.0+ + * + * [0]: http://www.xilinx.com/support/documentation + * + * [M]: [0]/ip_documentation/mpmc.pdf + * [S]: [0]/ip_documentation/xps_ll_temac.pdf + * [A]: [0]/application_notes/xapp1041.pdf + */ + +#include +#include +#include + +#include +#include + +#include "xilinx_ll_temac.h" +#include "xilinx_ll_temac_sdma.h" + +#define TX_BUF_CNT 2 + +static unsigned int rx_idx; /* index of the current RX buffer */ +static unsigned int tx_idx; /* index of the current TX buffer */ + +struct rtx_cdmac_bd { + struct cdmac_bd rx[PKTBUFSRX]; + struct cdmac_bd tx[TX_BUF_CNT]; +}; + +/* + * DMA Buffer Descriptor alignment + * + * If the address contained in the Next Descriptor Pointer register is not + * 8-word aligned or reaches beyond the range of available memory, the SDMA + * halts processing and sets the CDMAC_BD_STCTRL_ERROR bit in the respective + * status register (tx_chnl_sts or rx_chnl_sts). + * + * [1]: [0]/ip_documentation/mpmc.pdf + * page 161, Next Descriptor Pointer + */ +static struct rtx_cdmac_bd cdmac_bd __aligned(32); + +#if defined(CONFIG_XILINX_440) || defined(CONFIG_XILINX_405) + +/* + * Indirect DCR access operations mi{ft}dcr_xilinx() espacialy + * for Xilinx PowerPC implementations on FPGA. + * + * FIXME: This part should go up to arch/powerpc -- but where? + */ +#include +#define XILINX_INDIRECT_DCR_ADDRESS_REG 0 +#define XILINX_INDIRECT_DCR_ACCESS_REG 1 +inline unsigned mifdcr_xilinx(const unsigned dcrn) +{ + mtdcr(XILINX_INDIRECT_DCR_ADDRESS_REG, dcrn); + return mfdcr(XILINX_INDIRECT_DCR_ACCESS_REG); +} +inline void mitdcr_xilinx(const unsigned dcrn, int val) +{ + mtdcr(XILINX_INDIRECT_DCR_ADDRESS_REG, dcrn); + mtdcr(XILINX_INDIRECT_DCR_ACCESS_REG, val); +} + +/* Xilinx Device Control Register (DCR) in/out accessors */ +inline unsigned ll_temac_xldcr_in32(phys_addr_t addr) +{ + return mifdcr_xilinx((const unsigned)addr); +} +inline void ll_temac_xldcr_out32(phys_addr_t addr, unsigned value) +{ + mitdcr_xilinx((const unsigned)addr, value); +} + +void ll_temac_collect_xldcr_sdma_reg_addr(struct eth_device *dev) +{ + struct ll_temac *ll_temac = dev->priv; + phys_addr_t dmac_ctrl = ll_temac->ctrladdr; + phys_addr_t *ra = ll_temac->sdma_reg_addr; + + ra[TX_NXTDESC_PTR] = dmac_ctrl + TX_NXTDESC_PTR; + ra[TX_CURBUF_ADDR] = dmac_ctrl + TX_CURBUF_ADDR; + ra[TX_CURBUF_LENGTH] = dmac_ctrl + TX_CURBUF_LENGTH; + ra[TX_CURDESC_PTR] = dmac_ctrl + TX_CURDESC_PTR; + ra[TX_TAILDESC_PTR] = dmac_ctrl + TX_TAILDESC_PTR; + ra[TX_CHNL_CTRL] = dmac_ctrl + TX_CHNL_CTRL; + ra[TX_IRQ_REG] = dmac_ctrl + TX_IRQ_REG; + ra[TX_CHNL_STS] = dmac_ctrl + TX_CHNL_STS; + ra[RX_NXTDESC_PTR] = dmac_ctrl + RX_NXTDESC_PTR; + ra[RX_CURBUF_ADDR] = dmac_ctrl + RX_CURBUF_ADDR; + ra[RX_CURBUF_LENGTH] = dmac_ctrl + RX_CURBUF_LENGTH; + ra[RX_CURDESC_PTR] = dmac_ctrl + RX_CURDESC_PTR; + ra[RX_TAILDESC_PTR] = dmac_ctrl + RX_TAILDESC_PTR; + ra[RX_CHNL_CTRL] = dmac_ctrl + RX_CHNL_CTRL; + ra[RX_IRQ_REG] = dmac_ctrl + RX_IRQ_REG; + ra[RX_CHNL_STS] = dmac_ctrl + RX_CHNL_STS; + ra[DMA_CONTROL_REG] = dmac_ctrl + DMA_CONTROL_REG; +} + +#endif /* CONFIG_XILINX_440 || ONFIG_XILINX_405 */ + +/* Xilinx Processor Local Bus (PLB) in/out accessors */ +inline unsigned ll_temac_xlplb_in32(phys_addr_t addr) +{ + return in_be32((void *)addr); +} +inline void ll_temac_xlplb_out32(phys_addr_t addr, unsigned value) +{ + out_be32((void *)addr, value); +} + +/* collect all register addresses for Xilinx PLB in/out accessors */ +void ll_temac_collect_xlplb_sdma_reg_addr(struct eth_device *dev) +{ + struct ll_temac *ll_temac = dev->priv; + struct sdma_ctrl *sdma_ctrl = (void *)ll_temac->ctrladdr; + phys_addr_t *ra = ll_temac->sdma_reg_addr; + + ra[TX_NXTDESC_PTR] = (phys_addr_t)&sdma_ctrl->tx_nxtdesc_ptr; + ra[TX_CURBUF_ADDR] = (phys_addr_t)&sdma_ctrl->tx_curbuf_addr; + ra[TX_CURBUF_LENGTH] = (phys_addr_t)&sdma_ctrl->tx_curbuf_length; + ra[TX_CURDESC_PTR] = (phys_addr_t)&sdma_ctrl->tx_curdesc_ptr; + ra[TX_TAILDESC_PTR] = (phys_addr_t)&sdma_ctrl->tx_taildesc_ptr; + ra[TX_CHNL_CTRL] = (phys_addr_t)&sdma_ctrl->tx_chnl_ctrl; + ra[TX_IRQ_REG] = (phys_addr_t)&sdma_ctrl->tx_irq_reg; + ra[TX_CHNL_STS] = (phys_addr_t)&sdma_ctrl->tx_chnl_sts; + ra[RX_NXTDESC_PTR] = (phys_addr_t)&sdma_ctrl->rx_nxtdesc_ptr; + ra[RX_CURBUF_ADDR] = (phys_addr_t)&sdma_ctrl->rx_curbuf_addr; + ra[RX_CURBUF_LENGTH] = (phys_addr_t)&sdma_ctrl->rx_curbuf_length; + ra[RX_CURDESC_PTR] = (phys_addr_t)&sdma_ctrl->rx_curdesc_ptr; + ra[RX_TAILDESC_PTR] = (phys_addr_t)&sdma_ctrl->rx_taildesc_ptr; + ra[RX_CHNL_CTRL] = (phys_addr_t)&sdma_ctrl->rx_chnl_ctrl; + ra[RX_IRQ_REG] = (phys_addr_t)&sdma_ctrl->rx_irq_reg; + ra[RX_CHNL_STS] = (phys_addr_t)&sdma_ctrl->rx_chnl_sts; + ra[DMA_CONTROL_REG] = (phys_addr_t)&sdma_ctrl->dma_control_reg; +} + +/* Check for TX and RX channel errors. */ +static inline int ll_temac_sdma_error(struct eth_device *dev) +{ + int err; + struct ll_temac *ll_temac = dev->priv; + phys_addr_t *ra = ll_temac->sdma_reg_addr; + + err = ll_temac->in32(ra[TX_CHNL_STS]) & CHNL_STS_ERROR; + err |= ll_temac->in32(ra[RX_CHNL_STS]) & CHNL_STS_ERROR; + + return err; +} + +int ll_temac_init_sdma(struct eth_device *dev) +{ + struct ll_temac *ll_temac = dev->priv; + struct cdmac_bd *rx_dp; + struct cdmac_bd *tx_dp; + phys_addr_t *ra = ll_temac->sdma_reg_addr; + int i; + + printf("%s: SDMA: %d Rx buffers, %d Tx buffers\n", + dev->name, PKTBUFSRX, TX_BUF_CNT); + + /* Initialize the Rx Buffer descriptors */ + for (i = 0; i < PKTBUFSRX; i++) { + rx_dp = &cdmac_bd.rx[i]; + memset(rx_dp, 0, sizeof(*rx_dp)); + rx_dp->next_p = rx_dp; + rx_dp->buf_len = PKTSIZE_ALIGN; + rx_dp->phys_buf_p = (u8 *)net_rx_packets[i]; + flush_cache((u32)rx_dp->phys_buf_p, PKTSIZE_ALIGN); + } + flush_cache((u32)cdmac_bd.rx, sizeof(cdmac_bd.rx)); + + /* Initialize the TX Buffer Descriptors */ + for (i = 0; i < TX_BUF_CNT; i++) { + tx_dp = &cdmac_bd.tx[i]; + memset(tx_dp, 0, sizeof(*tx_dp)); + tx_dp->next_p = tx_dp; + } + flush_cache((u32)cdmac_bd.tx, sizeof(cdmac_bd.tx)); + + /* Reset index counter to the Rx and Tx Buffer descriptors */ + rx_idx = tx_idx = 0; + + /* initial Rx DMA start by writing to respective TAILDESC_PTR */ + ll_temac->out32(ra[RX_CURDESC_PTR], (int)&cdmac_bd.rx[rx_idx]); + ll_temac->out32(ra[RX_TAILDESC_PTR], (int)&cdmac_bd.rx[rx_idx]); + + return 0; +} + +int ll_temac_halt_sdma(struct eth_device *dev) +{ + unsigned timeout = 50; /* 1usec * 50 = 50usec */ + struct ll_temac *ll_temac = dev->priv; + phys_addr_t *ra = ll_temac->sdma_reg_addr; + + /* + * Soft reset the DMA + * + * Quote from MPMC documentation: Writing a 1 to this field + * forces the DMA engine to shutdown and reset itself. After + * setting this bit, software must poll it until the bit is + * cleared by the DMA. This indicates that the reset process + * is done and the pipeline has been flushed. + */ + ll_temac->out32(ra[DMA_CONTROL_REG], DMA_CONTROL_RESET); + while (timeout && (ll_temac->in32(ra[DMA_CONTROL_REG]) + & DMA_CONTROL_RESET)) { + timeout--; + udelay(1); + } + + if (!timeout) { + printf("%s: Timeout\n", __func__); + return -1; + } + + return 0; +} + +int ll_temac_reset_sdma(struct eth_device *dev) +{ + u32 r; + struct ll_temac *ll_temac = dev->priv; + phys_addr_t *ra = ll_temac->sdma_reg_addr; + + /* Soft reset the DMA. */ + if (ll_temac_halt_sdma(dev)) + return -1; + + /* Now clear the interrupts. */ + r = ll_temac->in32(ra[TX_CHNL_CTRL]); + r &= ~CHNL_CTRL_IRQ_MASK; + ll_temac->out32(ra[TX_CHNL_CTRL], r); + + r = ll_temac->in32(ra[RX_CHNL_CTRL]); + r &= ~CHNL_CTRL_IRQ_MASK; + ll_temac->out32(ra[RX_CHNL_CTRL], r); + + /* Now ACK pending IRQs. */ + ll_temac->out32(ra[TX_IRQ_REG], IRQ_REG_IRQ_MASK); + ll_temac->out32(ra[RX_IRQ_REG], IRQ_REG_IRQ_MASK); + + /* Set tail-ptr mode, disable errors for both channels. */ + ll_temac->out32(ra[DMA_CONTROL_REG], + /* Enable use of tail pointer register */ + DMA_CONTROL_TPE | + /* Disable error when 2 or 4 bit coalesce cnt overfl */ + DMA_CONTROL_RXOCEID | + /* Disable error when 2 or 4 bit coalesce cnt overfl */ + DMA_CONTROL_TXOCEID); + + return 0; +} + +int ll_temac_recv_sdma(struct eth_device *dev) +{ + int length, pb_idx; + struct cdmac_bd *rx_dp = &cdmac_bd.rx[rx_idx]; + struct ll_temac *ll_temac = dev->priv; + phys_addr_t *ra = ll_temac->sdma_reg_addr; + + if (ll_temac_sdma_error(dev)) { + + if (ll_temac_reset_sdma(dev)) + return -1; + + ll_temac_init_sdma(dev); + } + + flush_cache((u32)rx_dp, sizeof(*rx_dp)); + + if (!(rx_dp->sca.stctrl & CDMAC_BD_STCTRL_COMPLETED)) + return 0; + + if (rx_dp->sca.stctrl & (CDMAC_BD_STCTRL_SOP | CDMAC_BD_STCTRL_EOP)) { + pb_idx = rx_idx; + length = rx_dp->sca.app[4] & CDMAC_BD_APP4_RXBYTECNT_MASK; + } else { + pb_idx = -1; + length = 0; + printf("%s: Got part of package, unsupported (%x)\n", + __func__, rx_dp->sca.stctrl); + } + + /* flip the buffer */ + flush_cache((u32)rx_dp->phys_buf_p, length); + + /* reset the current descriptor */ + rx_dp->sca.stctrl = 0; + rx_dp->sca.app[4] = 0; + flush_cache((u32)rx_dp, sizeof(*rx_dp)); + + /* Find next empty buffer descriptor, preparation for next iteration */ + rx_idx = (rx_idx + 1) % PKTBUFSRX; + rx_dp = &cdmac_bd.rx[rx_idx]; + flush_cache((u32)rx_dp, sizeof(*rx_dp)); + + /* DMA start by writing to respective TAILDESC_PTR */ + ll_temac->out32(ra[RX_CURDESC_PTR], (int)&cdmac_bd.rx[rx_idx]); + ll_temac->out32(ra[RX_TAILDESC_PTR], (int)&cdmac_bd.rx[rx_idx]); + + if (length > 0 && pb_idx != -1) + net_process_received_packet(net_rx_packets[pb_idx], length); + + return 0; +} + +int ll_temac_send_sdma(struct eth_device *dev, void *packet, int length) +{ + unsigned timeout = 50; /* 1usec * 50 = 50usec */ + struct cdmac_bd *tx_dp = &cdmac_bd.tx[tx_idx]; + struct ll_temac *ll_temac = dev->priv; + phys_addr_t *ra = ll_temac->sdma_reg_addr; + + if (ll_temac_sdma_error(dev)) { + + if (ll_temac_reset_sdma(dev)) + return -1; + + ll_temac_init_sdma(dev); + } + + tx_dp->phys_buf_p = (u8 *)packet; + tx_dp->buf_len = length; + tx_dp->sca.stctrl = CDMAC_BD_STCTRL_SOP | CDMAC_BD_STCTRL_EOP | + CDMAC_BD_STCTRL_STOP_ON_END; + + flush_cache((u32)packet, length); + flush_cache((u32)tx_dp, sizeof(*tx_dp)); + + /* DMA start by writing to respective TAILDESC_PTR */ + ll_temac->out32(ra[TX_CURDESC_PTR], (int)tx_dp); + ll_temac->out32(ra[TX_TAILDESC_PTR], (int)tx_dp); + + /* Find next empty buffer descriptor, preparation for next iteration */ + tx_idx = (tx_idx + 1) % TX_BUF_CNT; + tx_dp = &cdmac_bd.tx[tx_idx]; + + do { + flush_cache((u32)tx_dp, sizeof(*tx_dp)); + udelay(1); + } while (timeout-- && !(tx_dp->sca.stctrl & CDMAC_BD_STCTRL_COMPLETED)); + + if (!timeout) { + printf("%s: Timeout\n", __func__); + return -1; + } + + return 0; +} diff --git a/sources/uboot-be550/drivers/net/xilinx_ll_temac_sdma.h b/sources/uboot-be550/drivers/net/xilinx_ll_temac_sdma.h new file mode 100644 index 00000000..41659c0e --- /dev/null +++ b/sources/uboot-be550/drivers/net/xilinx_ll_temac_sdma.h @@ -0,0 +1,277 @@ +/* + * Xilinx xps_ll_temac ethernet driver for u-boot + * + * SDMA sub-controller interface + * + * Copyright (C) 2011 - 2012 Stephan Linz + * Copyright (C) 2008 - 2011 Michal Simek + * Copyright (C) 2008 - 2011 PetaLogix + * + * Based on Yoshio Kashiwagi kashiwagi@co-nss.co.jp driver + * Copyright (C) 2008 Nissin Systems Co.,Ltd. + * March 2008 created + * + * SPDX-License-Identifier: GPL-2.0+ + * + * [0]: http://www.xilinx.com/support/documentation + * + * [S]: [0]/ip_documentation/xps_ll_temac.pdf + * [A]: [0]/application_notes/xapp1041.pdf + */ +#ifndef _XILINX_LL_TEMAC_SDMA_ +#define _XILINX_LL_TEMAC_SDMA_ + +#include + +#include +#include + +#include + +#if !defined(__BIG_ENDIAN) +# error LL_TEMAC requires big endianess +#endif + +/* + * DMA Buffer Descriptor for CDMAC + * + * Used for data connection from and to (Rx/Tx) the LocalLink (LL) TEMAC via + * the Communications Direct Memory Access Controller (CDMAC) -- one for each. + * + * overview: + * ftp://ftp.xilinx.com/pub/documentation/misc/mpmc_getting_started.pdf + * + * [1]: [0]/ip_documentation/mpmc.pdf + * page 140, DMA Operation Descriptors + * + * [2]: [0]/user_guides/ug200.pdf + * page 229, DMA Controller -- Descriptor Format + * + * [3]: [0]/ip_documentation/xps_ll_temac.pdf + * page 72, Transmit LocalLink Frame Format + * page 73, Receive LocalLink Frame Format + */ +struct cdmac_bd { + struct cdmac_bd *next_p; /* Next Descriptor Pointer */ + u8 *phys_buf_p; /* Buffer Address */ + u32 buf_len; /* Buffer Length */ + union { + u8 stctrl; /* Status/Control the DMA transfer */ + u32 app[5]; /* application specific data */ + } __packed __aligned(1) sca; +}; + +/* CDMAC Descriptor Status and Control (stctrl), [1] p140, [2] p230 */ +#define CDMAC_BD_STCTRL_ERROR (1 << 7) +#define CDMAC_BD_STCTRL_IRQ_ON_END (1 << 6) +#define CDMAC_BD_STCTRL_STOP_ON_END (1 << 5) +#define CDMAC_BD_STCTRL_COMPLETED (1 << 4) +#define CDMAC_BD_STCTRL_SOP (1 << 3) +#define CDMAC_BD_STCTRL_EOP (1 << 2) +#define CDMAC_BD_STCTRL_DMACHBUSY (1 << 1) + +/* CDMAC Descriptor APP0: Transmit LocalLink Footer Word 3, [3] p72 */ +#define CDMAC_BD_APP0_TXCSCNTRL (1 << 0) + +/* CDMAC Descriptor APP1: Transmit LocalLink Footer Word 4, [3] p73 */ +#define CDMAC_BD_APP1_TXCSBEGIN_POS 16 +#define CDMAC_BD_APP1_TXCSBEGIN_MASK (0xFFFF << CDMAC_BD_APP1_TXCSBEGIN_POS) +#define CDMAC_BD_APP1_TXCSINSERT_POS 0 +#define CDMAC_BD_APP1_TXCSINSERT_MASK (0xFFFF << CDMAC_BD_APP1_TXCSINSERT_POS) + +/* CDMAC Descriptor APP2: Transmit LocalLink Footer Word 5, [3] p73 */ +#define CDMAC_BD_APP2_TXCSINIT_POS 0 +#define CDMAC_BD_APP2_TXCSINIT_MASK (0xFFFF << CDMAC_BD_APP2_TXCSINIT_POS) + +/* CDMAC Descriptor APP0: Receive LocalLink Footer Word 3, [3] p73 */ +#define CDMAC_BD_APP0_MADDRU_POS 0 +#define CDMAC_BD_APP0_MADDRU_MASK (0xFFFF << CDMAC_BD_APP0_MADDRU_POS) + +/* CDMAC Descriptor APP1: Receive LocalLink Footer Word 4, [3] p74 */ +#define CDMAC_BD_APP1_MADDRL_POS 0 +#define CDMAC_BD_APP1_MADDRL_MASK (~0UL << CDMAC_BD_APP1_MADDRL_POS) + +/* CDMAC Descriptor APP2: Receive LocalLink Footer Word 5, [3] p74 */ +#define CDMAC_BD_APP2_BCAST_FRAME (1 << 2) +#define CDMAC_BD_APP2_IPC_MCAST_FRAME (1 << 1) +#define CDMAC_BD_APP2_MAC_MCAST_FRAME (1 << 0) + +/* CDMAC Descriptor APP3: Receive LocalLink Footer Word 6, [3] p74 */ +#define CDMAC_BD_APP3_TLTPID_POS 16 +#define CDMAC_BD_APP3_TLTPID_MASK (0xFFFF << CDMAC_BD_APP3_TLTPID_POS) +#define CDMAC_BD_APP3_RXCSRAW_POS 0 +#define CDMAC_BD_APP3_RXCSRAW_MASK (0xFFFF << CDMAC_BD_APP3_RXCSRAW_POS) + +/* CDMAC Descriptor APP4: Receive LocalLink Footer Word 7, [3] p74 */ +#define CDMAC_BD_APP4_VLANTAG_POS 16 +#define CDMAC_BD_APP4_VLANTAG_MASK (0xFFFF << CDMAC_BD_APP4_VLANTAG_POS) +#define CDMAC_BD_APP4_RXBYTECNT_POS 0 +#define CDMAC_BD_APP4_RXBYTECNT_MASK (0x3FFF << CDMAC_BD_APP4_RXBYTECNT_POS) + +/* + * SDMA Register Definition + * + * [0]: http://www.xilinx.com/support/documentation + * + * [1]: [0]/ip_documentation/mpmc.pdf + * page 54, SDMA Register Summary + * page 160, SDMA Registers + * + * [2]: [0]/user_guides/ug200.pdf + * page 244, DMA Controller -- Programming Interface and Registers + */ +#define SDMA_CTRL_REGTYPE u32 +#define SDMA_CTRL_REGSIZE sizeof(SDMA_CTRL_REGTYPE) +struct sdma_ctrl { + /* Transmit Registers */ + SDMA_CTRL_REGTYPE tx_nxtdesc_ptr; /* TX Next Description Pointer */ + SDMA_CTRL_REGTYPE tx_curbuf_addr; /* TX Current Buffer Address */ + SDMA_CTRL_REGTYPE tx_curbuf_length; /* TX Current Buffer Length */ + SDMA_CTRL_REGTYPE tx_curdesc_ptr; /* TX Current Descriptor Pointer */ + SDMA_CTRL_REGTYPE tx_taildesc_ptr; /* TX Tail Descriptor Pointer */ + SDMA_CTRL_REGTYPE tx_chnl_ctrl; /* TX Channel Control */ + SDMA_CTRL_REGTYPE tx_irq_reg; /* TX Interrupt Register */ + SDMA_CTRL_REGTYPE tx_chnl_sts; /* TX Status Register */ + /* Receive Registers */ + SDMA_CTRL_REGTYPE rx_nxtdesc_ptr; /* RX Next Descriptor Pointer */ + SDMA_CTRL_REGTYPE rx_curbuf_addr; /* RX Current Buffer Address */ + SDMA_CTRL_REGTYPE rx_curbuf_length; /* RX Current Buffer Length */ + SDMA_CTRL_REGTYPE rx_curdesc_ptr; /* RX Current Descriptor Pointer */ + SDMA_CTRL_REGTYPE rx_taildesc_ptr; /* RX Tail Descriptor Pointer */ + SDMA_CTRL_REGTYPE rx_chnl_ctrl; /* RX Channel Control */ + SDMA_CTRL_REGTYPE rx_irq_reg; /* RX Interrupt Register */ + SDMA_CTRL_REGTYPE rx_chnl_sts; /* RX Status Register */ + /* Control Registers */ + SDMA_CTRL_REGTYPE dma_control_reg; /* DMA Control Register */ +}; + +#define SDMA_CTRL_REGNUMS sizeof(struct sdma_ctrl)/SDMA_CTRL_REGSIZE + +/* + * DMAC Register Index Enumeration + * + * [2]: http://www.xilinx.com/support/documentation/user_guides/ug200.pdf + * page 244, DMA Controller -- Programming Interface and Registers + */ +enum dmac_ctrl { + /* Transmit Registers */ + TX_NXTDESC_PTR = 0, /* TX Next Description Pointer */ + TX_CURBUF_ADDR, /* TX Current Buffer Address */ + TX_CURBUF_LENGTH, /* TX Current Buffer Length */ + TX_CURDESC_PTR, /* TX Current Descriptor Pointer */ + TX_TAILDESC_PTR, /* TX Tail Descriptor Pointer */ + TX_CHNL_CTRL, /* TX Channel Control */ + TX_IRQ_REG, /* TX Interrupt Register */ + TX_CHNL_STS, /* TX Status Register */ + /* Receive Registers */ + RX_NXTDESC_PTR, /* RX Next Descriptor Pointer */ + RX_CURBUF_ADDR, /* RX Current Buffer Address */ + RX_CURBUF_LENGTH, /* RX Current Buffer Length */ + RX_CURDESC_PTR, /* RX Current Descriptor Pointer */ + RX_TAILDESC_PTR, /* RX Tail Descriptor Pointer */ + RX_CHNL_CTRL, /* RX Channel Control */ + RX_IRQ_REG, /* RX Interrupt Register */ + RX_CHNL_STS, /* RX Status Register */ + /* Control Registers */ + DMA_CONTROL_REG /* DMA Control Register */ +}; + +/* Rx/Tx Channel Control Register (*_chnl_ctrl), [1] p163, [2] p246/p252 */ +#define CHNL_CTRL_ITO_POS 24 +#define CHNL_CTRL_ITO_MASK (0xFF << CHNL_CTRL_ITO_POS) +#define CHNL_CTRL_IC_POS 16 +#define CHNL_CTRL_IC_MASK (0xFF << CHNL_CTRL_IC_POS) +#define CHNL_CTRL_MSBADDR_POS 12 +#define CHNL_CTRL_MSBADDR_MASK (0xF << CHNL_CTRL_MSBADDR_POS) +#define CHNL_CTRL_AME (1 << 11) +#define CHNL_CTRL_OBWC (1 << 10) +#define CHNL_CTRL_IOE (1 << 9) +#define CHNL_CTRL_LIC (1 << 8) +#define CHNL_CTRL_IE (1 << 7) +#define CHNL_CTRL_IEE (1 << 2) +#define CHNL_CTRL_IDE (1 << 1) +#define CHNL_CTRL_ICE (1 << 0) + +/* All interrupt enable bits */ +#define CHNL_CTRL_IRQ_MASK (CHNL_CTRL_IE | \ + CHNL_CTRL_IEE | \ + CHNL_CTRL_IDE | \ + CHNL_CTRL_ICE) + +/* Rx/Tx Interrupt Status Register (*_irq_reg), [1] p164, [2] p247/p253 */ +#define IRQ_REG_DTV_POS 24 +#define IRQ_REG_DTV_MASK (0xFF << IRQ_REG_DTV_POS) +#define IRQ_REG_CCV_POS 16 +#define IRQ_REG_CCV_MASK (0xFF << IRQ_REG_CCV_POS) +#define IRQ_REG_WRCQ_EMPTY (1 << 14) +#define IRQ_REG_CIC_POS 10 +#define IRQ_REG_CIC_MASK (0xF << IRQ_REG_CIC_POS) +#define IRQ_REG_DIC_POS 8 +#define IRQ_REG_DIC_MASK (3 << 8) +#define IRQ_REG_PLB_RD_NMI (1 << 4) +#define IRQ_REG_PLB_WR_NMI (1 << 3) +#define IRQ_REG_EI (1 << 2) +#define IRQ_REG_DI (1 << 1) +#define IRQ_REG_CI (1 << 0) + +/* All interrupt bits */ +#define IRQ_REG_IRQ_MASK (IRQ_REG_PLB_RD_NMI | \ + IRQ_REG_PLB_WR_NMI | \ + IRQ_REG_EI | IRQ_REG_DI | IRQ_REG_CI) + +/* Rx/Tx Channel Status Register (*_chnl_sts), [1] p165, [2] p249/p255 */ +#define CHNL_STS_ERROR_TAIL (1 << 21) +#define CHNL_STS_ERROR_CMP (1 << 20) +#define CHNL_STS_ERROR_ADDR (1 << 19) +#define CHNL_STS_ERROR_NXTP (1 << 18) +#define CHNL_STS_ERROR_CURP (1 << 17) +#define CHNL_STS_ERROR_BSYWR (1 << 16) +#define CHNL_STS_ERROR (1 << 7) +#define CHNL_STS_IOE (1 << 6) +#define CHNL_STS_SOE (1 << 5) +#define CHNL_STS_CMPLT (1 << 4) +#define CHNL_STS_SOP (1 << 3) +#define CHNL_STS_EOP (1 << 2) +#define CHNL_STS_EBUSY (1 << 1) + +/* DMA Control Register (dma_control_reg), [1] p166, [2] p256 */ +#define DMA_CONTROL_PLBED (1 << 5) +#define DMA_CONTROL_RXOCEID (1 << 4) +#define DMA_CONTROL_TXOCEID (1 << 3) +#define DMA_CONTROL_TPE (1 << 2) +#define DMA_CONTROL_RESET (1 << 0) + +#if defined(CONFIG_XILINX_440) || defined(CONFIG_XILINX_405) + +/* Xilinx Device Control Register (DCR) in/out accessors */ +unsigned ll_temac_xldcr_in32(phys_addr_t addr); +void ll_temac_xldcr_out32(phys_addr_t addr, unsigned value); + +/* collect all register addresses for Xilinx DCR in/out accessors */ +void ll_temac_collect_xldcr_sdma_reg_addr(struct eth_device *dev); + +#endif /* CONFIG_XILINX_440 || CONFIG_XILINX_405 */ + +/* Xilinx Processor Local Bus (PLB) in/out accessors */ +unsigned ll_temac_xlplb_in32(phys_addr_t base); +void ll_temac_xlplb_out32(phys_addr_t base, unsigned value); + +/* collect all register addresses for Xilinx PLB in/out accessors */ +void ll_temac_collect_xlplb_sdma_reg_addr(struct eth_device *dev); + +/* initialize both Rx/Tx buffer descriptors */ +int ll_temac_init_sdma(struct eth_device *dev); + +/* halt both Rx/Tx transfers */ +int ll_temac_halt_sdma(struct eth_device *dev); + +/* reset SDMA and IRQ, disable interrupts and errors */ +int ll_temac_reset_sdma(struct eth_device *dev); + +/* receive buffered data from SDMA (polling ISR) */ +int ll_temac_recv_sdma(struct eth_device *dev); + +/* send buffered data to SDMA */ +int ll_temac_send_sdma(struct eth_device *dev, void *packet, int length); + +#endif /* _XILINX_LL_TEMAC_SDMA_ */ diff --git a/sources/uboot-be550/drivers/net/zynq_gem.c b/sources/uboot-be550/drivers/net/zynq_gem.c new file mode 100644 index 00000000..7059c843 --- /dev/null +++ b/sources/uboot-be550/drivers/net/zynq_gem.c @@ -0,0 +1,716 @@ +/* + * (C) Copyright 2011 Michal Simek + * + * Michal SIMEK + * + * Based on Xilinx gmac driver: + * (C) Copyright 2011 Xilinx + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* Bit/mask specification */ +#define ZYNQ_GEM_PHYMNTNC_OP_MASK 0x40020000 /* operation mask bits */ +#define ZYNQ_GEM_PHYMNTNC_OP_R_MASK 0x20000000 /* read operation */ +#define ZYNQ_GEM_PHYMNTNC_OP_W_MASK 0x10000000 /* write operation */ +#define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK 23 /* Shift bits for PHYAD */ +#define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK 18 /* Shift bits for PHREG */ + +#define ZYNQ_GEM_RXBUF_EOF_MASK 0x00008000 /* End of frame. */ +#define ZYNQ_GEM_RXBUF_SOF_MASK 0x00004000 /* Start of frame. */ +#define ZYNQ_GEM_RXBUF_LEN_MASK 0x00003FFF /* Mask for length field */ + +#define ZYNQ_GEM_RXBUF_WRAP_MASK 0x00000002 /* Wrap bit, last BD */ +#define ZYNQ_GEM_RXBUF_NEW_MASK 0x00000001 /* Used bit.. */ +#define ZYNQ_GEM_RXBUF_ADD_MASK 0xFFFFFFFC /* Mask for address */ + +/* Wrap bit, last descriptor */ +#define ZYNQ_GEM_TXBUF_WRAP_MASK 0x40000000 +#define ZYNQ_GEM_TXBUF_LAST_MASK 0x00008000 /* Last buffer */ +#define ZYNQ_GEM_TXBUF_USED_MASK 0x80000000 /* Used by Hw */ + +#define ZYNQ_GEM_NWCTRL_TXEN_MASK 0x00000008 /* Enable transmit */ +#define ZYNQ_GEM_NWCTRL_RXEN_MASK 0x00000004 /* Enable receive */ +#define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */ +#define ZYNQ_GEM_NWCTRL_STARTTX_MASK 0x00000200 /* Start tx (tx_go) */ + +#define ZYNQ_GEM_NWCFG_SPEED100 0x000000001 /* 100 Mbps operation */ +#define ZYNQ_GEM_NWCFG_SPEED1000 0x000000400 /* 1Gbps operation */ +#define ZYNQ_GEM_NWCFG_FDEN 0x000000002 /* Full Duplex mode */ +#define ZYNQ_GEM_NWCFG_FSREM 0x000020000 /* FCS removal */ +#define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x0000c0000 /* Div pclk by 48, max 120MHz */ + +#ifdef CONFIG_ARM64 +# define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */ +#else +# define ZYNQ_GEM_DBUS_WIDTH (0 << 21) /* 32 bit bus */ +#endif + +#define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_DBUS_WIDTH | \ + ZYNQ_GEM_NWCFG_FDEN | \ + ZYNQ_GEM_NWCFG_FSREM | \ + ZYNQ_GEM_NWCFG_MDCCLKDIV) + +#define ZYNQ_GEM_NWSR_MDIOIDLE_MASK 0x00000004 /* PHY management idle */ + +#define ZYNQ_GEM_DMACR_BLENGTH 0x00000004 /* INCR4 AHB bursts */ +/* Use full configured addressable space (8 Kb) */ +#define ZYNQ_GEM_DMACR_RXSIZE 0x00000300 +/* Use full configured addressable space (4 Kb) */ +#define ZYNQ_GEM_DMACR_TXSIZE 0x00000400 +/* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */ +#define ZYNQ_GEM_DMACR_RXBUF 0x00180000 + +#define ZYNQ_GEM_DMACR_INIT (ZYNQ_GEM_DMACR_BLENGTH | \ + ZYNQ_GEM_DMACR_RXSIZE | \ + ZYNQ_GEM_DMACR_TXSIZE | \ + ZYNQ_GEM_DMACR_RXBUF) + +#define ZYNQ_GEM_TSR_DONE 0x00000020 /* Tx done mask */ + +/* Use MII register 1 (MII status register) to detect PHY */ +#define PHY_DETECT_REG 1 + +/* Mask used to verify certain PHY features (or register contents) + * in the register above: + * 0x1000: 10Mbps full duplex support + * 0x0800: 10Mbps half duplex support + * 0x0008: Auto-negotiation support + */ +#define PHY_DETECT_MASK 0x1808 + +/* TX BD status masks */ +#define ZYNQ_GEM_TXBUF_FRMLEN_MASK 0x000007ff +#define ZYNQ_GEM_TXBUF_EXHAUSTED 0x08000000 +#define ZYNQ_GEM_TXBUF_UNDERRUN 0x10000000 + +/* Clock frequencies for different speeds */ +#define ZYNQ_GEM_FREQUENCY_10 2500000UL +#define ZYNQ_GEM_FREQUENCY_100 25000000UL +#define ZYNQ_GEM_FREQUENCY_1000 125000000UL + +/* Device registers */ +struct zynq_gem_regs { + u32 nwctrl; /* 0x0 - Network Control reg */ + u32 nwcfg; /* 0x4 - Network Config reg */ + u32 nwsr; /* 0x8 - Network Status reg */ + u32 reserved1; + u32 dmacr; /* 0x10 - DMA Control reg */ + u32 txsr; /* 0x14 - TX Status reg */ + u32 rxqbase; /* 0x18 - RX Q Base address reg */ + u32 txqbase; /* 0x1c - TX Q Base address reg */ + u32 rxsr; /* 0x20 - RX Status reg */ + u32 reserved2[2]; + u32 idr; /* 0x2c - Interrupt Disable reg */ + u32 reserved3; + u32 phymntnc; /* 0x34 - Phy Maintaince reg */ + u32 reserved4[18]; + u32 hashl; /* 0x80 - Hash Low address reg */ + u32 hashh; /* 0x84 - Hash High address reg */ +#define LADDR_LOW 0 +#define LADDR_HIGH 1 + u32 laddr[4][LADDR_HIGH + 1]; /* 0x8c - Specific1 addr low/high reg */ + u32 match[4]; /* 0xa8 - Type ID1 Match reg */ + u32 reserved6[18]; +#define STAT_SIZE 44 + u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */ + u32 reserved7[164]; + u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */ + u32 reserved8[15]; + u32 receive_q1_ptr; /* 0x480 - Receive priority queue 1 */ +}; + +/* BD descriptors */ +struct emac_bd { + u32 addr; /* Next descriptor pointer */ + u32 status; +}; + +#define RX_BUF 32 +/* Page table entries are set to 1MB, or multiples of 1MB + * (not < 1MB). driver uses less bd's so use 1MB bdspace. + */ +#define BD_SPACE 0x100000 +/* BD separation space */ +#define BD_SEPRN_SPACE (RX_BUF * sizeof(struct emac_bd)) + +/* Setup the first free TX descriptor */ +#define TX_FREE_DESC 2 + +/* Initialized, rxbd_current, rx_first_buf must be 0 after init */ +struct zynq_gem_priv { + struct emac_bd *tx_bd; + struct emac_bd *rx_bd; + char *rxbuffers; + u32 rxbd_current; + u32 rx_first_buf; + int phyaddr; + u32 emio; + int init; + struct zynq_gem_regs *iobase; + phy_interface_t interface; + struct phy_device *phydev; + struct mii_dev *bus; +}; + +static inline int mdio_wait(struct zynq_gem_regs *regs) +{ + u32 timeout = 20000; + + /* Wait till MDIO interface is ready to accept a new transaction. */ + while (--timeout) { + if (readl(®s->nwsr) & ZYNQ_GEM_NWSR_MDIOIDLE_MASK) + break; + WATCHDOG_RESET(); + } + + if (!timeout) { + printf("%s: Timeout\n", __func__); + return 1; + } + + return 0; +} + +static u32 phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum, + u32 op, u16 *data) +{ + u32 mgtcr; + struct zynq_gem_regs *regs = priv->iobase; + + if (mdio_wait(regs)) + return 1; + + /* Construct mgtcr mask for the operation */ + mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op | + (phy_addr << ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK) | + (regnum << ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK) | *data; + + /* Write mgtcr and wait for completion */ + writel(mgtcr, ®s->phymntnc); + + if (mdio_wait(regs)) + return 1; + + if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK) + *data = readl(®s->phymntnc); + + return 0; +} + +static u32 phyread(struct zynq_gem_priv *priv, u32 phy_addr, + u32 regnum, u16 *val) +{ + u32 ret; + + ret = phy_setup_op(priv, phy_addr, regnum, + ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val); + + if (!ret) + debug("%s: phy_addr %d, regnum 0x%x, val 0x%x\n", __func__, + phy_addr, regnum, *val); + + return ret; +} + +static u32 phywrite(struct zynq_gem_priv *priv, u32 phy_addr, + u32 regnum, u16 data) +{ + debug("%s: phy_addr %d, regnum 0x%x, data 0x%x\n", __func__, phy_addr, + regnum, data); + + return phy_setup_op(priv, phy_addr, regnum, + ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data); +} + +static int phy_detection(struct udevice *dev) +{ + int i; + u16 phyreg; + struct zynq_gem_priv *priv = dev->priv; + + if (priv->phyaddr != -1) { + phyread(priv, priv->phyaddr, PHY_DETECT_REG, &phyreg); + if ((phyreg != 0xFFFF) && + ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { + /* Found a valid PHY address */ + debug("Default phy address %d is valid\n", + priv->phyaddr); + return 0; + } else { + debug("PHY address is not setup correctly %d\n", + priv->phyaddr); + priv->phyaddr = -1; + } + } + + debug("detecting phy address\n"); + if (priv->phyaddr == -1) { + /* detect the PHY address */ + for (i = 31; i >= 0; i--) { + phyread(priv, i, PHY_DETECT_REG, &phyreg); + if ((phyreg != 0xFFFF) && + ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { + /* Found a valid PHY address */ + priv->phyaddr = i; + debug("Found valid phy address, %d\n", i); + return 0; + } + } + } + printf("PHY is not detected\n"); + return -1; +} + +static int zynq_gem_setup_mac(struct udevice *dev) +{ + u32 i, macaddrlow, macaddrhigh; + struct eth_pdata *pdata = dev_get_platdata(dev); + struct zynq_gem_priv *priv = dev_get_priv(dev); + struct zynq_gem_regs *regs = priv->iobase; + + /* Set the MAC bits [31:0] in BOT */ + macaddrlow = pdata->enetaddr[0]; + macaddrlow |= pdata->enetaddr[1] << 8; + macaddrlow |= pdata->enetaddr[2] << 16; + macaddrlow |= pdata->enetaddr[3] << 24; + + /* Set MAC bits [47:32] in TOP */ + macaddrhigh = pdata->enetaddr[4]; + macaddrhigh |= pdata->enetaddr[5] << 8; + + for (i = 0; i < 4; i++) { + writel(0, ®s->laddr[i][LADDR_LOW]); + writel(0, ®s->laddr[i][LADDR_HIGH]); + /* Do not use MATCHx register */ + writel(0, ®s->match[i]); + } + + writel(macaddrlow, ®s->laddr[0][LADDR_LOW]); + writel(macaddrhigh, ®s->laddr[0][LADDR_HIGH]); + + return 0; +} + +static int zynq_phy_init(struct udevice *dev) +{ + int ret; + struct zynq_gem_priv *priv = dev_get_priv(dev); + struct zynq_gem_regs *regs = priv->iobase; + const u32 supported = SUPPORTED_10baseT_Half | + SUPPORTED_10baseT_Full | + SUPPORTED_100baseT_Half | + SUPPORTED_100baseT_Full | + SUPPORTED_1000baseT_Half | + SUPPORTED_1000baseT_Full; + + /* Enable only MDIO bus */ + writel(ZYNQ_GEM_NWCTRL_MDEN_MASK, ®s->nwctrl); + + ret = phy_detection(dev); + if (ret) { + printf("GEM PHY init failed\n"); + return ret; + } + + priv->phydev = phy_connect(priv->bus, priv->phyaddr, dev, + priv->interface); + if (!priv->phydev) + return -ENODEV; + + priv->phydev->supported = supported | ADVERTISED_Pause | + ADVERTISED_Asym_Pause; + priv->phydev->advertising = priv->phydev->supported; + phy_config(priv->phydev); + + return 0; +} + +static int zynq_gem_init(struct udevice *dev) +{ + u32 i; + unsigned long clk_rate = 0; + struct zynq_gem_priv *priv = dev_get_priv(dev); + struct zynq_gem_regs *regs = priv->iobase; + struct emac_bd *dummy_tx_bd = &priv->tx_bd[TX_FREE_DESC]; + struct emac_bd *dummy_rx_bd = &priv->tx_bd[TX_FREE_DESC + 2]; + + if (!priv->init) { + /* Disable all interrupts */ + writel(0xFFFFFFFF, ®s->idr); + + /* Disable the receiver & transmitter */ + writel(0, ®s->nwctrl); + writel(0, ®s->txsr); + writel(0, ®s->rxsr); + writel(0, ®s->phymntnc); + + /* Clear the Hash registers for the mac address + * pointed by AddressPtr + */ + writel(0x0, ®s->hashl); + /* Write bits [63:32] in TOP */ + writel(0x0, ®s->hashh); + + /* Clear all counters */ + for (i = 0; i < STAT_SIZE; i++) + readl(®s->stat[i]); + + /* Setup RxBD space */ + memset(priv->rx_bd, 0, RX_BUF * sizeof(struct emac_bd)); + + for (i = 0; i < RX_BUF; i++) { + priv->rx_bd[i].status = 0xF0000000; + priv->rx_bd[i].addr = + ((ulong)(priv->rxbuffers) + + (i * PKTSIZE_ALIGN)); + } + /* WRAP bit to last BD */ + priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK; + /* Write RxBDs to IP */ + writel((ulong)priv->rx_bd, ®s->rxqbase); + + /* Setup for DMA Configuration register */ + writel(ZYNQ_GEM_DMACR_INIT, ®s->dmacr); + + /* Setup for Network Control register, MDIO, Rx and Tx enable */ + setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK); + + /* Disable the second priority queue */ + dummy_tx_bd->addr = 0; + dummy_tx_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK | + ZYNQ_GEM_TXBUF_LAST_MASK| + ZYNQ_GEM_TXBUF_USED_MASK; + + dummy_rx_bd->addr = ZYNQ_GEM_RXBUF_WRAP_MASK | + ZYNQ_GEM_RXBUF_NEW_MASK; + dummy_rx_bd->status = 0; + flush_dcache_range((ulong)&dummy_tx_bd, (ulong)&dummy_tx_bd + + sizeof(dummy_tx_bd)); + flush_dcache_range((ulong)&dummy_rx_bd, (ulong)&dummy_rx_bd + + sizeof(dummy_rx_bd)); + + writel((ulong)dummy_tx_bd, ®s->transmit_q1_ptr); + writel((ulong)dummy_rx_bd, ®s->receive_q1_ptr); + + priv->init++; + } + + phy_startup(priv->phydev); + + if (!priv->phydev->link) { + printf("%s: No link.\n", priv->phydev->dev->name); + return -1; + } + + switch (priv->phydev->speed) { + case SPEED_1000: + writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED1000, + ®s->nwcfg); + clk_rate = ZYNQ_GEM_FREQUENCY_1000; + break; + case SPEED_100: + writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED100, + ®s->nwcfg); + clk_rate = ZYNQ_GEM_FREQUENCY_100; + break; + case SPEED_10: + clk_rate = ZYNQ_GEM_FREQUENCY_10; + break; + } + + /* Change the rclk and clk only not using EMIO interface */ + if (!priv->emio) + zynq_slcr_gem_clk_setup((ulong)priv->iobase != + ZYNQ_GEM_BASEADDR0, clk_rate); + + setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | + ZYNQ_GEM_NWCTRL_TXEN_MASK); + + return 0; +} + +static int wait_for_bit(const char *func, u32 *reg, const u32 mask, + bool set, unsigned int timeout) +{ + u32 val; + unsigned long start = get_timer(0); + + while (1) { + val = readl(reg); + + if (!set) + val = ~val; + + if ((val & mask) == mask) + return 0; + + if (get_timer(start) > timeout) + break; + + if (ctrlc()) { + puts("Abort\n"); + return -EINTR; + } + + udelay(1); + } + + debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n", + func, reg, mask, set); + + return -ETIMEDOUT; +} + +static int zynq_gem_send(struct udevice *dev, void *ptr, int len) +{ + u32 addr, size; + struct zynq_gem_priv *priv = dev_get_priv(dev); + struct zynq_gem_regs *regs = priv->iobase; + struct emac_bd *current_bd = &priv->tx_bd[1]; + + /* Setup Tx BD */ + memset(priv->tx_bd, 0, sizeof(struct emac_bd)); + + priv->tx_bd->addr = (ulong)ptr; + priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) | + ZYNQ_GEM_TXBUF_LAST_MASK; + /* Dummy descriptor to mark it as the last in descriptor chain */ + current_bd->addr = 0x0; + current_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK | + ZYNQ_GEM_TXBUF_LAST_MASK| + ZYNQ_GEM_TXBUF_USED_MASK; + + /* setup BD */ + writel((ulong)priv->tx_bd, ®s->txqbase); + + addr = (ulong) ptr; + addr &= ~(ARCH_DMA_MINALIGN - 1); + size = roundup(len, ARCH_DMA_MINALIGN); + flush_dcache_range(addr, addr + size); + + addr = (ulong)priv->rxbuffers; + addr &= ~(ARCH_DMA_MINALIGN - 1); + size = roundup((RX_BUF * PKTSIZE_ALIGN), ARCH_DMA_MINALIGN); + flush_dcache_range(addr, addr + size); + barrier(); + + /* Start transmit */ + setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK); + + /* Read TX BD status */ + if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED) + printf("TX buffers exhausted in mid frame\n"); + + return wait_for_bit(__func__, ®s->txsr, ZYNQ_GEM_TSR_DONE, + true, 20000); +} + +/* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */ +static int zynq_gem_recv(struct udevice *dev, int flags, uchar **packetp) +{ + int frame_len; + u32 addr; + struct zynq_gem_priv *priv = dev_get_priv(dev); + struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current]; + + if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK)) + return -1; + + if (!(current_bd->status & + (ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) { + printf("GEM: SOF or EOF not set for last buffer received!\n"); + return -1; + } + + frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK; + if (!frame_len) { + printf("%s: Zero size packet?\n", __func__); + return -1; + } + + addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK; + addr &= ~(ARCH_DMA_MINALIGN - 1); + *packetp = (uchar *)(uintptr_t)addr; + + return frame_len; +} + +static int zynq_gem_free_pkt(struct udevice *dev, uchar *packet, int length) +{ + struct zynq_gem_priv *priv = dev_get_priv(dev); + struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current]; + struct emac_bd *first_bd; + + if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK) { + priv->rx_first_buf = priv->rxbd_current; + } else { + current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK; + current_bd->status = 0xF0000000; /* FIXME */ + } + + if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) { + first_bd = &priv->rx_bd[priv->rx_first_buf]; + first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK; + first_bd->status = 0xF0000000; + } + + if ((++priv->rxbd_current) >= RX_BUF) + priv->rxbd_current = 0; + + return 0; +} + +static void zynq_gem_halt(struct udevice *dev) +{ + struct zynq_gem_priv *priv = dev_get_priv(dev); + struct zynq_gem_regs *regs = priv->iobase; + + clrsetbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | + ZYNQ_GEM_NWCTRL_TXEN_MASK, 0); +} + +static int zynq_gem_miiphy_read(struct mii_dev *bus, int addr, + int devad, int reg) +{ + struct zynq_gem_priv *priv = bus->priv; + int ret; + u16 val; + + ret = phyread(priv, addr, reg, &val); + debug("%s 0x%x, 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val, ret); + return val; +} + +static int zynq_gem_miiphy_write(struct mii_dev *bus, int addr, int devad, + int reg, u16 value) +{ + struct zynq_gem_priv *priv = bus->priv; + + debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, value); + return phywrite(priv, addr, reg, value); +} + +static int zynq_gem_probe(struct udevice *dev) +{ + void *bd_space; + struct zynq_gem_priv *priv = dev_get_priv(dev); + int ret; + + /* Align rxbuffers to ARCH_DMA_MINALIGN */ + priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN); + memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN); + + /* Align bd_space to MMU_SECTION_SHIFT */ + bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE); + mmu_set_region_dcache_behaviour((phys_addr_t)bd_space, + BD_SPACE, DCACHE_OFF); + + /* Initialize the bd spaces for tx and rx bd's */ + priv->tx_bd = (struct emac_bd *)bd_space; + priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE); + + priv->bus = mdio_alloc(); + priv->bus->read = zynq_gem_miiphy_read; + priv->bus->write = zynq_gem_miiphy_write; + priv->bus->priv = priv; + strcpy(priv->bus->name, "gem"); + + ret = mdio_register(priv->bus); + if (ret) + return ret; + + zynq_phy_init(dev); + + return 0; +} + +static int zynq_gem_remove(struct udevice *dev) +{ + struct zynq_gem_priv *priv = dev_get_priv(dev); + + free(priv->phydev); + mdio_unregister(priv->bus); + mdio_free(priv->bus); + + return 0; +} + +static const struct eth_ops zynq_gem_ops = { + .start = zynq_gem_init, + .send = zynq_gem_send, + .recv = zynq_gem_recv, + .free_pkt = zynq_gem_free_pkt, + .stop = zynq_gem_halt, + .write_hwaddr = zynq_gem_setup_mac, +}; + +static int zynq_gem_ofdata_to_platdata(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + struct zynq_gem_priv *priv = dev_get_priv(dev); + int offset = 0; + const char *phy_mode; + + pdata->iobase = (phys_addr_t)dev_get_addr(dev); + priv->iobase = (struct zynq_gem_regs *)pdata->iobase; + /* Hardcode for now */ + priv->emio = 0; + priv->phyaddr = -1; + + offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset, + "phy-handle"); + if (offset > 0) + priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1); + + phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL); + if (phy_mode) + pdata->phy_interface = phy_get_interface_by_name(phy_mode); + if (pdata->phy_interface == -1) { + debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); + return -EINVAL; + } + priv->interface = pdata->phy_interface; + + printf("ZYNQ GEM: %lx, phyaddr %d, interface %s\n", (ulong)priv->iobase, + priv->phyaddr, phy_string_for_interface(priv->interface)); + + return 0; +} + +static const struct udevice_id zynq_gem_ids[] = { + { .compatible = "cdns,zynqmp-gem" }, + { .compatible = "cdns,zynq-gem" }, + { .compatible = "cdns,gem" }, + { } +}; + +U_BOOT_DRIVER(zynq_gem) = { + .name = "zynq_gem", + .id = UCLASS_ETH, + .of_match = zynq_gem_ids, + .ofdata_to_platdata = zynq_gem_ofdata_to_platdata, + .probe = zynq_gem_probe, + .remove = zynq_gem_remove, + .ops = &zynq_gem_ops, + .priv_auto_alloc_size = sizeof(struct zynq_gem_priv), + .platdata_auto_alloc_size = sizeof(struct eth_pdata), +};